From 93d93c770845c1d3f2d999b1bf1b659c036fc8f8 Mon Sep 17 00:00:00 2001 From: John Crispin Date: Thu, 12 May 2022 14:30:21 +0200 Subject: [PATCH] qsdk-ssdk: update to ath11.5-cs Signed-off-by: John Crispin --- feeds/ipq807x/qca-ssdk/Makefile | 112 +- feeds/ipq807x/qca-ssdk/Makefile.orig | 94 + feeds/ipq807x/qca-ssdk/patches/100-aq.patch | 26 +- feeds/ipq807x/qca-ssdk/src/ChangeLog | 129 - feeds/ipq807x/qca-ssdk/src/Makefile | 52 - .../src/app/nathelper/linux/host_helper.c | 2253 --- .../app/nathelper/linux/lib/nat_helper_dt.c | 1352 -- .../app/nathelper/linux/lib/nat_helper_dt.h | 22 - .../app/nathelper/linux/lib/nat_helper_hsl.c | 879 - .../app/nathelper/linux/lib/nat_helper_hsl.h | 257 - .../src/app/nathelper/linux/napt_acl.c | 1622 -- .../src/app/nathelper/linux/napt_acl.h | 94 - .../src/app/nathelper/linux/napt_helper.c | 406 - .../src/app/nathelper/linux/napt_helper.h | 91 - .../src/app/nathelper/linux/napt_procfs.c | 1316 -- .../src/app/nathelper/linux/nat_helper.c | 69 - .../src/app/nathelper/linux/nat_helper.h | 54 - .../src/app/nathelper/linux/nat_ipt_helper.c | 761 - feeds/ipq807x/qca-ssdk/src/config | 347 - .../ipq807x/qca-ssdk/src/include/adpt/adpt.h | 1604 -- .../src/include/adpt/cppe/adpt_cppe_flow.h | 38 - .../src/include/adpt/cppe/adpt_cppe_mib.h | 52 - .../src/include/adpt/cppe/adpt_cppe_misc.h | 37 - .../include/adpt/cppe/adpt_cppe_portctrl.h | 103 - .../src/include/adpt/cppe/adpt_cppe_qm.h | 41 - .../src/include/adpt/cppe/adpt_cppe_qos.h | 68 - .../src/include/adpt/cppe/adpt_cppe_uniphy.h | 47 - .../src/include/adpt/hppe/adpt_hppe.h | 112 - .../qca-ssdk/src/include/adpt/mp/adpt_mp.h | 43 - .../src/include/adpt/mp/adpt_mp_portctrl.h | 63 - .../src/include/adpt/mp/adpt_mp_uniphy.h | 45 - .../qca-ssdk/src/include/adpt/sfp/adpt_sfp.h | 32 - .../qca-ssdk/src/include/api/api_access.h | 39 - .../qca-ssdk/src/include/api/api_desc.h | 4771 ----- .../ipq807x/qca-ssdk/src/include/api/sw_api.h | 276 - .../qca-ssdk/src/include/api/sw_ioctl.h | 989 - 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+3,23 @@ include $(TOPDIR)/rules.mk include $(INCLUDE_DIR)/kernel.mk PKG_NAME:=qca-ssdk -PKG_SOURCE_DATE:=2020-07-10 +PKG_SOURCE_PROTO:=git +PKG_BRANCH:=master +PKG_RELEASE:=1 +PKG_SOURCE_URL:=https://git.codelinaro.org/clo/qsdk/oss/lklm/qca-ssdk +PKG_VERSION:=0d6d410637648b1bea0dede48d3fab791689cfce +PKG_MIRROR_HASH:=60a3f89c8d93eef1e21871a9ee9e0a4c8564a6499913695a17e3e481e80c8b63 + +PKG_SOURCE:=$(PKG_NAME)-$(PKG_VERSION).tar.gz +PKG_SOURCE_SUBDIR:=$(PKG_NAME)-$(PKG_VERSION) +PKG_SOURCE_VERSION:=$(PKG_VERSION) + +subtarget:=$(SUBTARGET) +hal_arch:=$(subtarget) include $(INCLUDE_DIR)/package.mk -define KernelPackage/qca-ssdk +define KernelPackage/qca-ssdk/default-nohnat SECTION:=kernel CATEGORY:=Kernel modules SUBMENU:=Network Devices @@ -17,13 +29,50 @@ define KernelPackage/qca-ssdk PROVIDES:=qca-ssdk endef +define KernelPackage/qca-ssdk +$(call KernelPackage/qca-ssdk/default-nohnat) + VARIANT:=nohnat + + ifneq (, $(findstring $(hal_arch), "ipq50xx")) + ifeq (, $(CONFIG_LOWMEM_FLASH)) + ifneq ($(LINUX_VERSION),$(filter 5.4%,$(LINUX_VERSION))) + DEPENDS+=kmod-ipt-filter +kmod-ppp + QCASSDK_CONFIG_OPTS+= HNAT_FEATURE=enable + endif + endif + endif +endef + define KernelPackage/qca-ssdk/Description This package contains a qca-ssdk driver for QCA chipset endef -GCC_VERSION=$(shell echo "$(CONFIG_GCC_VERSION)" | sed 's/[^0-9.]*\([0-9.]*\).*/\1/') +define KernelPackage/qca-ssdk-hnat +$(call KernelPackage/qca-ssdk/default-nohnat) + DEPENDS:=@TARGET_ipq_ipq40xx||TARGET_ipq40xx||TARGET_ar71xx||TARGET_ipq806x +kmod-ipt-extra +kmod-ipt-filter +(TARGET_ipq806x||TARGET_ipq):kmod-qca-rfs +kmod-ppp + TITLE+= (hnat) + VARIANT:=hnat +endef -TOOLCHAIN_BIN_PATH=$(TOOLCHAIN_DIR)/bin +define KernelPackage/qca-ssdk-hnat/Description +This package contains a qca-ssdk-hnat driver for QCA chipset +endef + +GCC_VERSION=$(shell echo "$(CONFIG_GCC_VERSION)" | sed 's/[^0-9.]*\([0-9.]*\).*/\1/') +ifeq ($(GCC_VERSION), 4.8) + GCC_VERSION=4.8.3 +endif + +ifdef CONFIG_TOOLCHAIN_BIN_PATH + TOOLCHAIN_BIN_PATH=$(CONFIG_TOOLCHAIN_BIN_PATH) +else + TOOLCHAIN_BIN_PATH=$(TOOLCHAIN_DIR)/bin +endif + +ifdef CONFIG_TARGET_NAME +QCASSDK_CONFIG_OPTS+= \ + TARGET_NAME=$(CONFIG_TARGET_NAME) +endif QCASSDK_CONFIG_OPTS+= TOOL_PATH=$(TOOLCHAIN_BIN_PATH) \ SYS_PATH=$(LINUX_DIR) \ @@ -34,17 +83,45 @@ QCASSDK_CONFIG_OPTS+= TOOL_PATH=$(TOOLCHAIN_BIN_PATH) \ GCC_VERSION=$(GCC_VERSION) \ CFLAGS=-I$(STAGING_DIR)/usr/include -QCASSDK_CONFIG_OPTS+= PTP_FEATURE=enable - -ifeq ($(SUBTARGET),ipq807x)) - QCASSDK_CONFIG_OPTS+= CHIP_TYPE=HPPE -else ifeq ($(SUBTARGET),ipq60xx)) - QCASSDK_CONFIG_OPTS+= CHIP_TYPE=CPPE +ifeq ($(LOCAL_VARIANT),hnat) + QCASSDK_CONFIG_OPTS+= HNAT_FEATURE=enable + ifeq ($(CONFIG_TARGET_ar71xx),) + QCASSDK_CONFIG_OPTS+= RFS_FEATURE=enable + endif endif -QCASSDK_CONFIG_OPTS+= MINI_SSDK=enable -QCASSDK_CONFIG_OPTS+= PTP_FEATURE=disable -QCASSDK_CONFIG_OPTS+= HK_CHIP=enable +ifneq (, $(findstring $(hal_arch), "ipq95xx")) + QCASSDK_CONFIG_OPTS+= CHIP_TYPE=APPE +endif + +ifneq (, $(findstring $(hal_arch), "ipq60xx" "ipq807x" "ipq95xx")) + QCASSDK_CONFIG_OPTS+= PTP_FEATURE=enable +endif + +ifneq (, $(findstring $(CONFIG_KERNEL_IPQ_MEM_PROFILE), 256 512)$(CONFIG_LOWMEM_FLASH)) + QCASSDK_CONFIG_OPTS+= MINI_SSDK=enable + + ifneq (, $(findstring $(hal_arch), "ipq807x")) + QCASSDK_CONFIG_OPTS+= CHIP_TYPE=HPPE + else ifneq (, $(findstring $(hal_arch), "ipq60xx")) + QCASSDK_CONFIG_OPTS+= CHIP_TYPE=CPPE + else ifneq (, $(findstring $(hal_arch), "ipq50xx")) + QCASSDK_CONFIG_OPTS+= ISISC_ENABLE=enable + QCASSDK_CONFIG_OPTS+= CHIP_TYPE=MP + + ifeq (, $(CONFIG_LOWMEM_FLASH)) + ifeq (, $(findstring $(CONFIG_KERNEL_IPQ_MEM_PROFILE), 256)) + QCASSDK_CONFIG_OPTS+= MINI_SSDK=disable + endif + endif + endif + + QCASSDK_CONFIG_OPTS+= PTP_FEATURE=disable +endif + +ifeq ($(CONFIG_TARGET_ipq806x_QSDK_Standard),) + QCASSDK_CONFIG_OPTS+= HK_CHIP=enable +endif define Build/InstallDev $(INSTALL_DIR) $(1)/usr/include/qca-ssdk @@ -66,6 +143,9 @@ define Build/InstallDev if [ -f $(PKG_BUILD_DIR)/include/init/ssdk_init.h ]; then \ $(CP) -rf $(PKG_BUILD_DIR)/include/init/ssdk_init.h $(1)/usr/include/qca-ssdk/init/; \ fi + if [ -f $(PKG_BUILD_DIR)/include/init/ssdk_netlink.h ]; then \ + $(CP) -rf $(PKG_BUILD_DIR)/include/init/ssdk_netlink.h $(1)/usr/include/qca-ssdk/init/; \ + fi $(CP) -rf $(PKG_BUILD_DIR)/include/fal $(1)/usr/include/qca-ssdk $(CP) -rf $(PKG_BUILD_DIR)/include/common/*.h $(1)/usr/include/qca-ssdk $(CP) -rf $(PKG_BUILD_DIR)/include/sal/os/linux/*.h $(1)/usr/include/qca-ssdk @@ -82,4 +162,10 @@ define KernelPackage/qca-ssdk/install $(INSTALL_BIN) ./files/qca-ssdk $(1)/etc/init.d/qca-ssdk endef +define KernelPackage/qca-ssdk-hnat/install + $(INSTALL_DIR) $(1)/etc/init.d + $(INSTALL_BIN) ./files/qca-ssdk $(1)/etc/init.d/qca-ssdk +endef + $(eval $(call KernelPackage,qca-ssdk)) +$(eval $(call KernelPackage,qca-ssdk-hnat)) diff --git a/feeds/ipq807x/qca-ssdk/Makefile.orig b/feeds/ipq807x/qca-ssdk/Makefile.orig new file mode 100755 index 000000000..c344d1a5a --- /dev/null +++ b/feeds/ipq807x/qca-ssdk/Makefile.orig @@ -0,0 +1,94 @@ + +include $(TOPDIR)/rules.mk +include $(INCLUDE_DIR)/kernel.mk + +PKG_NAME:=qca-ssdk +PKG_SOURCE_PROTO:=git +PKG_BRANCH:=master +PKG_RELEASE:=1 +PKG_SOURCE_URL:=https://git.codelinaro.org/clo/qsdk/oss/lklm/qca-ssdk +PKG_VERSION:=0d6d410637648b1bea0dede48d3fab791689cfce +PKG_MIRROR_HASH:=60a3f89c8d93eef1e21871a9ee9e0a4c8564a6499913695a17e3e481e80c8b63 + +PKG_SOURCE:=$(PKG_NAME)-$(PKG_VERSION).tar.gz +PKG_SOURCE_SUBDIR:=$(PKG_NAME)-$(PKG_VERSION) +PKG_SOURCE_VERSION:=$(PKG_VERSION) + +include $(INCLUDE_DIR)/package.mk + +define KernelPackage/qca-ssdk + SECTION:=kernel + CATEGORY:=Kernel modules + SUBMENU:=Network Devices + TITLE:=Kernel driver for QCA SSDK + FILES:=$(PKG_BUILD_DIR)/build/bin/qca-ssdk.ko + AUTOLOAD:=$(call AutoLoad,30,qca-ssdk) + PROVIDES:=qca-ssdk +endef + +define KernelPackage/qca-ssdk/Description +This package contains a qca-ssdk driver for QCA chipset +endef + +GCC_VERSION=$(shell echo "$(CONFIG_GCC_VERSION)" | sed 's/[^0-9.]*\([0-9.]*\).*/\1/') + +TOOLCHAIN_BIN_PATH=$(TOOLCHAIN_DIR)/bin + +QCASSDK_CONFIG_OPTS+= TOOL_PATH=$(TOOLCHAIN_BIN_PATH) \ + SYS_PATH=$(LINUX_DIR) \ + TOOLPREFIX=$(TARGET_CROSS) \ + KVER=$(LINUX_VERSION) \ + ARCH=$(LINUX_KARCH) \ + TARGET_SUFFIX=$(CONFIG_TARGET_SUFFIX) \ + GCC_VERSION=$(GCC_VERSION) \ + CFLAGS=-I$(STAGING_DIR)/usr/include + +QCASSDK_CONFIG_OPTS+= PTP_FEATURE=enable + +ifeq ($(SUBTARGET),ipq807x)) + QCASSDK_CONFIG_OPTS+= CHIP_TYPE=HPPE +else ifeq ($(SUBTARGET),ipq60xx)) + QCASSDK_CONFIG_OPTS+= CHIP_TYPE=CPPE +endif +QCASSDK_CONFIG_OPTS+= MINI_SSDK=enable +QCASSDK_CONFIG_OPTS+= PTP_FEATURE=disable + +QCASSDK_CONFIG_OPTS+= HK_CHIP=enable + +define Build/InstallDev + $(INSTALL_DIR) $(1)/usr/include/qca-ssdk + $(INSTALL_DIR) $(1)/usr/include/qca-ssdk/api + $(INSTALL_DIR) $(1)/usr/include/qca-ssdk/ref + $(INSTALL_DIR) $(1)/usr/include/qca-ssdk/fal + $(INSTALL_DIR) $(1)/usr/include/qca-ssdk/sal + $(INSTALL_DIR) $(1)/usr/include/qca-ssdk/init + $(CP) -rf $(PKG_BUILD_DIR)/include/api/sw_ioctl.h $(1)/usr/include/qca-ssdk/api + if [ -f $(PKG_BUILD_DIR)/include/ref/ref_vsi.h ]; then \ + $(CP) -rf $(PKG_BUILD_DIR)/include/ref/ref_vsi.h $(1)/usr/include/qca-ssdk/ref/; \ + fi + if [ -f $(PKG_BUILD_DIR)/include/ref/ref_fdb.h ]; then \ + $(CP) -rf $(PKG_BUILD_DIR)/include/ref/ref_fdb.h $(1)/usr/include/qca-ssdk/ref/; \ + fi + if [ -f $(PKG_BUILD_DIR)/include/ref/ref_port_ctrl.h ]; then \ + $(CP) -rf $(PKG_BUILD_DIR)/include/ref/ref_port_ctrl.h $(1)/usr/include/qca-ssdk/ref/; \ + fi + if [ -f $(PKG_BUILD_DIR)/include/init/ssdk_init.h ]; then \ + $(CP) -rf $(PKG_BUILD_DIR)/include/init/ssdk_init.h $(1)/usr/include/qca-ssdk/init/; \ + fi + $(CP) -rf $(PKG_BUILD_DIR)/include/fal $(1)/usr/include/qca-ssdk + $(CP) -rf $(PKG_BUILD_DIR)/include/common/*.h $(1)/usr/include/qca-ssdk + $(CP) -rf $(PKG_BUILD_DIR)/include/sal/os/linux/*.h $(1)/usr/include/qca-ssdk + $(CP) -rf $(PKG_BUILD_DIR)/include/sal/os/*.h $(1)/usr/include/qca-ssdk + +endef + +define Build/Compile + $(MAKE) -C $(PKG_BUILD_DIR) $(strip $(QCASSDK_CONFIG_OPTS)) +endef + +define KernelPackage/qca-ssdk/install + $(INSTALL_DIR) $(1)/etc/init.d + $(INSTALL_BIN) ./files/qca-ssdk $(1)/etc/init.d/qca-ssdk +endef + +$(eval $(call KernelPackage,qca-ssdk)) diff --git a/feeds/ipq807x/qca-ssdk/patches/100-aq.patch b/feeds/ipq807x/qca-ssdk/patches/100-aq.patch index b10be7076..6a82cfe59 100644 --- a/feeds/ipq807x/qca-ssdk/patches/100-aq.patch +++ b/feeds/ipq807x/qca-ssdk/patches/100-aq.patch @@ -1,8 +1,8 @@ -Index: qca-ssdk/include/hsl/phy/hsl_phy.h +Index: qca-ssdk-0d6d410637648b1bea0dede48d3fab791689cfce/include/hsl/phy/hsl_phy.h =================================================================== ---- qca-ssdk.orig/include/hsl/phy/hsl_phy.h -+++ qca-ssdk/include/hsl/phy/hsl_phy.h -@@ -562,6 +562,7 @@ typedef struct { +--- qca-ssdk-0d6d410637648b1bea0dede48d3fab791689cfce.orig/include/hsl/phy/hsl_phy.h ++++ qca-ssdk-0d6d410637648b1bea0dede48d3fab791689cfce/include/hsl/phy/hsl_phy.h +@@ -567,6 +567,7 @@ typedef struct { #define QCA8033_PHY 0x004DD074 #define QCA8035_PHY 0x004DD072 /*qca808x_start*/ @@ -10,7 +10,7 @@ Index: qca-ssdk/include/hsl/phy/hsl_phy.h #define QCA8081_PHY_V1_1 0x004DD101 #define INVALID_PHY_ID 0xFFFFFFFF -@@ -576,11 +577,14 @@ typedef struct { +@@ -581,12 +582,14 @@ typedef struct { #define AQUANTIA_PHY_109 0x03a1b502 #define AQUANTIA_PHY_111 0x03a1b610 #define AQUANTIA_PHY_111B0 0x03a1b612 @@ -18,18 +18,18 @@ Index: qca-ssdk/include/hsl/phy/hsl_phy.h #define AQUANTIA_PHY_112 0x03a1b660 #define AQUANTIA_PHY_113C_A0 0x31c31C10 #define AQUANTIA_PHY_113C_A1 0x31c31C11 + #define AQUANTIA_PHY_113C_B0 0x31c31C12 + #define AQUANTIA_PHY_113C_B1 0x31c31C13 #define AQUANTIA_PHY_112C 0x03a1b792 - +#define AQUANTIA_PHY_114C 0x31c31C22 -+ + #define PHY_805XV2 0x004DD082 #define PHY_805XV1 0x004DD081 - /*qca808x_start*/ -Index: qca-ssdk/src/hsl/phy/hsl_phy.c +Index: qca-ssdk-0d6d410637648b1bea0dede48d3fab791689cfce/src/hsl/phy/hsl_phy.c =================================================================== ---- qca-ssdk.orig/src/hsl/phy/hsl_phy.c -+++ qca-ssdk/src/hsl/phy/hsl_phy.c -@@ -231,6 +231,8 @@ phy_type_t hsl_phytype_get_by_phyid(a_ui +--- qca-ssdk-0d6d410637648b1bea0dede48d3fab791689cfce.orig/src/hsl/phy/hsl_phy.c ++++ qca-ssdk-0d6d410637648b1bea0dede48d3fab791689cfce/src/hsl/phy/hsl_phy.c +@@ -244,6 +244,8 @@ phy_type_t hsl_phytype_get_by_phyid(a_ui case AQUANTIA_PHY_108: case AQUANTIA_PHY_109: case AQUANTIA_PHY_111: @@ -38,7 +38,7 @@ Index: qca-ssdk/src/hsl/phy/hsl_phy.c case AQUANTIA_PHY_111B0: case AQUANTIA_PHY_112: case AQUANTIA_PHY_113C_A0: -@@ -250,6 +252,7 @@ phy_type_t hsl_phytype_get_by_phyid(a_ui +@@ -265,6 +267,7 @@ phy_type_t hsl_phytype_get_by_phyid(a_ui phytype = MPGE_PHY_CHIP; break; /*qca808x_start*/ diff --git a/feeds/ipq807x/qca-ssdk/src/ChangeLog b/feeds/ipq807x/qca-ssdk/src/ChangeLog deleted file mode 100644 index 547dba45d..000000000 --- a/feeds/ipq807x/qca-ssdk/src/ChangeLog +++ /dev/null @@ -1,129 +0,0 @@ -============================================================ -Changes for SSDK 1.0.3: -============================================================ - -* Support HORUS: - - Add chip type HORUS and related source code. - - - - -============================================================ -Changes for SSDK 1.0.4: -============================================================ - -* Support ISIS: - - Add chip type ISIS and related source code. - - - - -============================================================ -Changes for SSDK 1.0.5: -============================================================ - -* Speed up FDB entry next operation. -* Support linux 2.6.31 version. - - - - -============================================================ -Changes for SSDK 1.0.6: -============================================================ - -* New APIs pppoe_session_id_set/get are supported for ISIS chip. -* Fix parameter speed check bug in API isis_port_speed_set. - - - - -============================================================ -Changes for SSDK 1.0.7: -============================================================ -* Fix address bytes order bug in API _isis_ip6_base_addr_set/get. -* Change the socket call for user space and kernel communication to nonblocking way. -* Remove force routing function for ISIS acl action. -* Add configuration for ISIS register accessing speed up feature in ./config file. -* Add configuration for ISIS NAT helper feature in ./config.file. - - - - -============================================================ -Changes for SSDK 1.0.8: -============================================================ -* Offer ioctl based method for linux kernel&user space communication -* Remove some port property logic limitation for ISIS. -* Remove FDB CRC mode setting in ISIS init. -* Add some operation mode flag for ISIS NAPT entry next operation. -* Add some operation mode flag for ISIS NAPT del opertion. -* Fix one bug for fdb entry extendnext command parsing when shell works at slient mode. -* Fix one bug in ISIS ACL rule delete operation(isis_acl_rule_delete). -* Fix one bug in ISIS queue shapper get operation(isis_rate_queue_shaper_get). -* Add new API for ISIS MAC based VLAN translation.(isis_port_mac_vlan_xlt_set/isis_port_mac_vlan_xlt_get). -* Add new API for ISIS add/delete port to/from an exist FDB entry.(isis_fdb_port_add/isis_fdb_port_del). -* Add new API for ISIS ACL rules active/deactive. (isis_acl_rule_active/isis_acl_rule_deactive). -* Add new API for ISIS wcmp hash mode setting. (isis_ip_wcmp_hash_mode_set/isis_ip_wcmp_hash_mode_get). -* Add new API for ISIS host entry aging time setting. (isis_ip_age_time_set/isis_ip_age_time_get). -* Add new API for ISIS interrupt operation. (isis_intr_mask_set/isis_intr_mask_get/isis_intr_status_get/ - isis_intr_status_clear/isis_intr_port_link_mask_set/isis_intr_port_link_mask_get/isis_intr_port_link_status_get). -* Add new API for ISIS port MAC mode setting. (isis_interface_mac_mode_set/isis_interface_mac_mode_get). -* Add new API for ISIS port PHY mode setting. (isis_interface_phy_mode_set/isis_interface_phy_mode_get). -* Add new API for ISIS 802.3az setting. (isis_port_3az_status_set/isis_port_3az_status_get). -* Add new API for ISIS link status getting. (isis_port_link_status_get). -* Add new API for ISIS MAC TX status setting. (isis_port_txmac_status_set/isis_port_txmac_status_get). -* Add new API for ISIS MAC RX status setting. (isis_port_rxmac_status_set/isis_port_rxmac_status_get). -* Add new API for ISIS MAC TX flow control setting. (isis_port_txfc_status_set/isis_port_txfc_status_get). -* Add new API for ISIS MAC RX flow control setting. (isis_port_rxfc_status_set/isis_port_rxfc_status_get). -* Add new API for ISIS MAC back pressure setting. (isis_port_bp_status_set/isis_port_bp_status_get). -* Add new API for ISIS link force mode setting. (isis_port_link_forcemode_set/isis_port_link_forcemode_get). -* Fix one bug in Giga PHY device autoneg ability setting operation. -* Makefile change for ISIS NAT helper refactoring. - -============================================================ -Changes for SSDK 1.1.x: -============================================================ -* Add support for QCA833x family (ISISC, S17c). -* Add support for out-of-band register access through ethernet packets with Atheros header. (S17/S17c) -* Add IPV6 Hardware Routing (ISISC, S17c). -* Add new API for set/get status of one ACL rule source filter. (S17c only) -* Add new API for set/get arl search mode as ivl or svl when vlan invalid. (S17c only) -* Add new API for interface control: -fal_interface_fx100_ctrl_set/fal_interface_fx100_ctrl_get/fal_interface_fx100_status_get/fal_interface_fx100_status_set/fal_interface_mac06_exch_get/fal_interface_mac06_exch_set. (S17c only) -* Add new API for MIB counter: -fal_mib_port_flush_counters/fal_mib_cpukeep_set/fal_mib_cpukeep_get. (S17c only) -*Add new API for Misc: -fal_intr_mask_mac_linkchg_set/fal_intr_mask_mac_linkchg_get/fal_intr_status_mac_linkchg_get/fal_cpu_vid_en_set/fal_cpu_vid_en_get/fal_rtd_pppoe_en_set/fal_rtd_pppoe_en_get/fal_intr_status_mac_linkchg_clear (S17c only) -* Add new API for nat: nat_prv_base_mask_set/nat_prv_base_mask_get. (S17c only) -* Add new API for port ctrl: -fal_port_mac_loopback_set/fal_port_mac_loopback_set. (S17c only) -* Add new API for port vlan: -fal_netisolate_set/fal_netisolate_get/fal_eg_trans_filter_bypass_en_set/fal_eg_trans_filter_bypass_en_get. (S17c only) -* Add new API for QoS: -fal_qos_port_force_spri_status_set/fal_qos_port_force_spri_status_get/fal_qos_port_force_cpri_status_set/fal_qos_port_force_cpri_status_get. (S17c only) -* Add new API for Rate limit: -fal_rate_port_add_rate_byte_set/fal_rate_port_add_rate_byte_get/fal_rate_port_gol_flow_en_set/fal_rate_port_gol_flow_en_get. - -============================================================ -Changes for SSDK 1.1.1: -============================================================ -* Add IGMP mldv2 support - -============================================================ -Changes for SSDK 1.1.2: -============================================================ -* Add API for Trunk support -* Add API for MAC loopback support - -============================================================ -Changes for SSDK 1.1.3: -============================================================ -* Support CHIP_TYPE=ALL_CHIP -============================================================ -Changes for SSDK 1.1.3.2: -============================================================ -* Add hsl_shared_api.h (sync from Perforce server) -* Add support for Linux Kernel 3.2.0 -* Add support for LITTLE ENDIAN (especially for HNAT) -* Add support for ARM CPU diff --git a/feeds/ipq807x/qca-ssdk/src/Makefile b/feeds/ipq807x/qca-ssdk/src/Makefile deleted file mode 100755 index 779365171..000000000 --- a/feeds/ipq807x/qca-ssdk/src/Makefile +++ /dev/null @@ -1,52 +0,0 @@ -include ./config - -ifndef PRJ_PATH - PRJ_PATH=$(shell pwd) -endif -export PRJ_PATH - -include ./make/config.mk -include ./make/tools.mk -include ./make/$(OS)_opt.mk - -SUB_DIR=$(patsubst %/, %, $(dir $(wildcard src/*/Makefile))) -SUB_LIB=$(subst src/, , $(SUB_DIR)) - -all: $(BIN_DIR) kslib - mkdir -p ./temp/;cd ./temp;cp ../build/bin/ssdk_ks_km.a ./;ar -x ssdk_ks_km.a; cp ../ko_Makefile ./Makefile; - make -C $(SYS_PATH) M=$(PRJ_PATH)/temp/ CROSS_COMPILE=$(TOOLPREFIX) modules - cp $(PRJ_PATH)/temp/Module.symvers $(PRJ_PATH)/Module.symvers; - cp temp/*.ko build/bin; - rm -Rf ./temp/*.o ./temp/*.ko ./temp/*.a - @echo "---Build [SSDK-$(VERSION)] at $(BUILD_DATE) finished." - -kslib:kslib_o - $(AR) -r $(BIN_DIR)/$(KS_MOD)_$(RUNMODE).a $(wildcard $(BLD_DIR)/KSLIB/*.o) - -kslib_o: - $(foreach i, $(SUB_LIB), $(MAKE) MODULE_TYPE=KSLIB -C src/$i all || exit 1;) - -uslib:uslib_o - $(AR) -r $(BIN_DIR)/$(US_MOD)_$(RUNMODE).a $(wildcard $(BLD_DIR)/USLIB/*.o) - -uslib_o: - $(foreach i, $(SUB_LIB), $(MAKE) MODULE_TYPE=USLIB -C src/$i all || exit 1;) - -shell:uslib shell_o - $(CP) $(BLD_DIR)/SHELL/$(SHELLOBJ) $(BIN_DIR)/$(SHELLOBJ) - $(STRIP) $(BIN_DIR)/$(SHELLOBJ) - -shell_o: - $(foreach i, $(SUB_LIB), $(MAKE) MODULE_TYPE=SHELL -C src/$i all || exit 1;) - -$(BIN_DIR): - $(MKDIR) -p $@ - -release: - @cd make; ./release.sh $(VER) - -clean: - $(RM) -f $(BLD_DIR)/KSLIB/* - $(RM) -f $(BLD_DIR)/USLIB/* - $(RM) -f $(BLD_DIR)/SHELL/* - $(RM) -f $(BIN_DIR)/* diff --git a/feeds/ipq807x/qca-ssdk/src/app/nathelper/linux/host_helper.c b/feeds/ipq807x/qca-ssdk/src/app/nathelper/linux/host_helper.c deleted file mode 100755 index 8140233a8..000000000 --- a/feeds/ipq807x/qca-ssdk/src/app/nathelper/linux/host_helper.c +++ /dev/null @@ -1,2253 +0,0 @@ -/* - * Copyright (c) 2012, 2015, 2017-2018, The Linux Foundation. All rights reserved. - * Permission to use, copy, modify, and/or distribute this software for - * any purpose with or without fee is hereby granted, provided that the - * above copyright notice and this permission notice appear in all copies. - * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES - * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR - * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES - * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN - * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT - * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. - */ - - -#ifdef KVER32 -#include -#include -#include -#else -#include -#endif -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#ifdef KVER32 -#include -#endif -#include -#if defined(CONFIG_VLAN_8021Q) || defined(CONFIG_VLAN_8021Q_MODULE) -#include -#endif -#if defined (CONFIG_BRIDGE) -#include <../net/bridge/br_private.h> -#endif -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include "hsl_api.h" -#include "fal_nat.h" -#include "fal_ip.h" -#include "fal_fdb.h" -#include "hsl.h" -#include "nat_helper.h" -#include "napt_acl.h" -#include "lib/nat_helper_hsl.h" -#include "lib/nat_helper_dt.h" -#include "hsl_shared_api.h" -#include - - -#undef CONFIG_IPV6_HWACCEL - - -#ifdef CONFIG_IPV6_HWACCEL -#include -#include -#include -#include -#include -#include -#include -#endif - -//#define AP136_QCA_HEADER_EN 1 -#define MAC_LEN 6 -#define IP_LEN 4 -#define ARP_HEADER_LEN 8 - -#define ARP_ENTRY_MAX 128 - -#define DESS_CHIP_VER 0x14 -#define HOST_PREFIX_MAX 31 - -/* P6 is used by loop dev. */ -#define S17_P6PAD_MODE_REG_VALUE 0x01000000 - -#define MULTIROUTE_WR - -extern struct net init_net; - -//char *nat_lan_dev_list = "eth0.1"; -char nat_lan_dev_list[IFNAMSIZ*4] = "br-lan eth0.1"; -char nat_wan_dev_list[IFNAMSIZ*5] = "eth0.2"; - -char nat_wan_port = 0x20; -int setup_wan_if = 0; -int setup_lan_if=0; - -#define NAT_LAN_DEV_VID 1 -#define NAT_WAN_DEV_VID 2 - -uint32_t nat_lan_vid = NAT_LAN_DEV_VID; -uint32_t nat_wan_vid = NAT_WAN_DEV_VID; - - -static int wan_fid = 0xffff; -static fal_pppoe_session_t pppoetbl = {0}; -static uint32_t pppoe_gwid = 0; -static char nat_bridge_dev[IFNAMSIZ*4] = "br-lan"; -static uint8_t lanip[4] = {0}, lanipmask[4] = {0}, wanip[4] = {0}; -#ifdef CONFIG_IPV6_HWACCEL -static struct in6_addr wan6ip = IN6ADDR_ANY_INIT; -static struct in6_addr lan6ip = IN6ADDR_ANY_INIT; -#endif - -extern int nat_chip_ver; - - -#ifdef ISISC -struct ipv6_default_route_binding -{ - struct in6_addr next_hop; - uint32_t nh_entry_id; -}; -#endif - -#ifdef MULTIROUTE_WR -#define MAX_HOST 8 -struct wan_next_hop -{ - u_int32_t host_ip; - u_int32_t entry_id; - u_int32_t in_acl; - u_int32_t in_use; - u_int8_t host_mac[6]; -}; -static struct net_device *multi_route_indev = NULL; -static struct wan_next_hop wan_nh_ent[MAX_HOST] = {{0}}; - -#define NAT_BACKGROUND_TASK - -#ifdef NAT_BACKGROUND_TASK -#define NAT_HELPER_MSG_MAX 512 - -struct bg_ring_buf_cb { - unsigned int read_idx; - unsigned int write_idx; - unsigned int num; - unsigned int full_flag; - struct nat_helper_bg_msg *buf; -}; - -struct bg_task_cb { - /*struct semaphore bg_sem; */ /*trigger thread work*/ - spinlock_t bg_lock; /*ring buf access protect*/ - /*struct task_struct *bg_task;*/ - struct workqueue_struct *nat_wq; - struct bg_ring_buf_cb ring; -}; - -enum{ - NAT_HELPER_ARP_ADD_MSG = 0, - NAT_HELPER_ARP_DEL_MSG, - NAT_HELPER_IPV6_MSG -}; - -struct arp_in_msg { - uint8_t mac[ETH_ALEN]; - char name[IFNAMSIZ]; /* device name */ - uint32_t ip; - struct net_device *in; -}; - -struct ipv6_msg { - struct sk_buff *skb; - struct net_device *in; -}; - - -struct nat_helper_bg_msg { - struct work_struct work; - uint32_t msg_type; - uint16_t sub_type; - uint16_t reservd; - union { - struct arp_in_msg arp_in; - struct ipv6_msg ipv6; - }; -}; - - -struct bg_task_cb task_cb; - -int bg_ring_buf_write(struct nat_helper_bg_msg msg) -{ - unsigned int idx = 0; - - spin_lock_bh(&task_cb.bg_lock); - - if((task_cb.ring).full_flag && - ((task_cb.ring).read_idx == (task_cb.ring).write_idx)) { - HNAT_PRINTK("ring buf is full!\n"); - spin_unlock_bh(&task_cb.bg_lock); - return -1; - } - msg.work = (task_cb.ring).buf[(task_cb.ring).write_idx].work; - (task_cb.ring).buf[(task_cb.ring).write_idx] = msg; - idx = (task_cb.ring).write_idx; - - (task_cb.ring).write_idx = ((task_cb.ring).write_idx+1)%NAT_HELPER_MSG_MAX; - if(task_cb.ring.read_idx == task_cb.ring.write_idx) - task_cb.ring.full_flag = 1; - - spin_unlock_bh(&task_cb.bg_lock); - queue_work(task_cb.nat_wq, &(task_cb.ring).buf[idx].work); - - return 0; -} - -int bg_ring_buf_read(struct nat_helper_bg_msg *msg) -{ - spin_lock_bh(&task_cb.bg_lock); - task_cb.ring.read_idx = (task_cb.ring.read_idx+1)%NAT_HELPER_MSG_MAX; - task_cb.ring.full_flag = 0; - spin_unlock_bh(&task_cb.bg_lock); - - return 0; -} - - - -#endif - -a_uint32_t nat_helper_wan_port_get(void) -{ - a_uint32_t i = 0; - - for (i = 0; i < 6; i ++) { - if ((nat_wan_port >> i) & 1) - break; - } - - return i; -} - -static int wan_nh_get(u_int32_t host_ip) -{ - int i; - - host_ip = htonl(host_ip); - - for (i=0; iifindex, - .flowi4_mark = 0, - .flowi4_tos = 0, - .flowi4_scope = RT_SCOPE_UNIVERSE, - .daddr = htonl(daddr), - .saddr = htonl(saddr), - }; -#else - struct flowi fl = { .nl_u = { .ip4_u = - { - .daddr = daddr, - .saddr = saddr, - .tos = 0, - .scope = RT_SCOPE_UNIVERSE, - } - }, - .mark = 0, - .iif = multi_route_indev->ifindex - }; -#endif - struct net * net = dev_net(multi_route_indev); - struct fib_nh *mrnh = NULL; -#if (LINUX_VERSION_CODE < KERNEL_VERSION(4,4,0)) - if (fib_lookup(net, &fl, &res) != 0) -#else - if (fib_lookup(net, &fl, &res,0) != 0) -#endif - { - return 0; - } - else - { - mrnh = res.fi->fib_nh; - if (NULL == mrnh) - { - return 0; - } - } - - return ntohl(mrnh->nh_gw); -} - -uint32_t napt_set_default_route(fal_ip4_addr_t dst_addr, fal_ip4_addr_t src_addr) -{ - sw_error_t rv; - - /* search for the next hop (s) */ - if (!(get_aclrulemask() & (1 << S17_ACL_LIST_DROUTE))) - { - if (multi_route_indev && \ - (nf_athrs17_hnat_wan_type != NF_S17_WAN_TYPE_PPPOE) && - (nf_athrs17_hnat_wan_type != NF_S17_WAN_TYPE_PPPOES0)) - { - uint32_t next_hop = get_next_hop(dst_addr, src_addr); - - HNAT_PRINTK("Next hop: %08x\n", next_hop); - if (next_hop != 0) - { - fal_host_entry_t arp_entry; - - memset(&arp_entry, 0, sizeof(arp_entry)); - arp_entry.ip4_addr = next_hop; - arp_entry.flags = FAL_IP_IP4_ADDR; - rv = IP_HOST_GET(0, FAL_IP_ENTRY_IPADDR_EN, &arp_entry); - if (rv != SW_OK) - { - printk("%s: IP_HOST_GET error... (non-existed host: %08x?) \n", __func__, next_hop); - /* add into the nh_ent */ - wan_nh_add((u_int8_t *)&next_hop, (u_int8_t *)NULL, 0); - } - else - { - if (wan_nh_get(next_hop) != -1) - droute_add_acl_rules(*(uint32_t *)&lanip, *(uint32_t *)&lanipmask, arp_entry.entry_id); - else - printk("%s %d\n", __FUNCTION__, __LINE__); - } - } - else - { - HNAT_PRINTK("no need to set the default route... \n"); - // set_aclrulemask (S17_ACL_LIST_DROUTE); - } - } - else - { - printk("multi_route_indev %pK nf_athrs17_hnat_wan_type %d\n", multi_route_indev, nf_athrs17_hnat_wan_type); - } - } - /* end next hop (s) */ - - return SW_OK; -} -#endif /* MULTIROUTE_WR */ - -void qcaswitch_hostentry_flush(void) -{ - fal_host_entry_t hostentry; - sw_error_t ret; - - do - { - memset(&hostentry, 0, sizeof(fal_host_entry_t)); - hostentry.entry_id = FAL_NEXT_ENTRY_FIRST_ID; - ret = IP_HOST_NEXT (0, FAL_IP_ENTRY_ID_EN, &hostentry); - if (SW_OK == ret) - { - IP_HOST_DEL(0, FAL_IP_ENTRY_IPADDR_EN, &hostentry); - } - }while (SW_OK == ret); - - return; -} - -#ifdef CONFIG_IPV6_HWACCEL /* only for S17c */ -static struct in6_addr* get_ipv6_default_gateway(void) -{ - /* ip_route_output_key can't return correct default nexhop - * routes are less than 4 and it only searches in route - * hash, not in fib, so use fib_lookup. - */ - struct in6_addr *ip6addr = NULL; - struct in6_addr des_addr = IN6ADDR_ANY_INIT; - struct rt6_info *rt = rt6_lookup(&init_net, &des_addr, NULL, 0, 0); - - if (rt) - { - ip6addr = &rt->rt6i_gateway; - } - - return ip6addr; -} - -static int add_pppoev6_host_entry(void) -{ - struct in6_addr local_lan6ip = IN6ADDR_ANY_INIT; - unsigned long flags; - int ppp_sid, ppp_sid2; - unsigned char ppp_peer_mac[ETH_ALEN]; - unsigned char ppp_peer_mac2[ETH_ALEN]; - a_uint32_t ppp_peer_ip = 0; - int wvid; - fal_host_entry_t nh_arp_entry; - sw_error_t rv; - a_uint32_t droute_entry_id = 0; - a_bool_t ena; - static fal_pppoe_session_t pppoev6_sid_table = {0}; - struct in6_addr *next_hop; - - local_irq_save(flags); - memcpy(&local_lan6ip, &lan6ip, sizeof(struct in6_addr)); - ppp_sid2 = nf_athrs17_hnat_ppp_id2; - ppp_sid = nf_athrs17_hnat_ppp_id; - ppp_peer_ip = nf_athrs17_hnat_ppp_peer_ip; - memcpy(ppp_peer_mac, nf_athrs17_hnat_ppp_peer_mac, ETH_ALEN); - memcpy(ppp_peer_mac2, nf_athrs17_hnat_ppp_peer_mac2, ETH_ALEN); - wvid = wan_fid; - local_irq_restore(flags); - - if (NF_S17_WAN_TYPE_PPPOE != nf_athrs17_hnat_wan_type) - { - return SW_BAD_STATE; - } - - if (__ipv6_addr_type(&local_lan6ip) == IPV6_ADDR_ANY) - { - /* Cannot get lanip6 successfully. */ - return SW_BAD_STATE; - } - if (0xffff == wvid) - { - printk("%s: Cannot get WAN vid!\n", __FUNCTION__); - return SW_FAIL; - } - - if (0 == nf_athrs17_hnat_ppp_peer_ip) - { - return SW_FAIL; - } - - next_hop = get_ipv6_default_gateway(); - if (NULL == next_hop) - { - printk("No IPv6 Gateway!\n"); - return SW_BAD_STATE; - } - - if (0 != ppp_sid) - { - if ((ppp_sid == ppp_sid2)||(0 == ppp_sid2)) /* v4 and v6 have the same session id */ - { - memset(&nh_arp_entry, 0, sizeof(nh_arp_entry)); - nh_arp_entry.ip4_addr = ppp_peer_ip; - nh_arp_entry.flags = FAL_IP_IP4_ADDR; - rv = IP_HOST_GET(0, FAL_IP_ENTRY_IPADDR_EN, &nh_arp_entry); - if (rv != SW_OK) - { - printk("%s: IP_HOST_GET error (0x%08x)\n", __func__, ppp_peer_ip); - if (PPPOE_STATUS_GET(0, &ena) != SW_OK) - { - if (!ena) - { - if (PPPOE_STATUS_SET(0, A_TRUE) != SW_OK) - { - aos_printk("Cannot enable the PPPoE mode\n"); - return SW_FAIL; - } - } - } - pppoev6_sid_table.session_id = ppp_sid; - pppoev6_sid_table.multi_session = 1; - pppoev6_sid_table.uni_session = 1; - pppoev6_sid_table.entry_id = 0; - /* set the PPPoE edit reg (0x2200), and PPPoE session reg (0x5f000) */ - rv = PPPOE_SESSION_TABLE_ADD(0, &pppoev6_sid_table); - if (rv == SW_OK) - { - a_int32_t a_entry_id = -1; - - PPPOE_SESSION_ID_SET(0, pppoev6_sid_table.entry_id, pppoev6_sid_table.session_id); - aos_printk("pppoe session: %d, entry_id: %d\n", - pppoev6_sid_table.session_id, pppoev6_sid_table.entry_id); - /* create the peer host ARP entry */ - a_entry_id = arp_hw_add(S17_WAN_PORT, wan_fid, (void *)&ppp_peer_ip, (void *)ppp_peer_mac, 0); - if (a_entry_id >= 0) /* hostentry creation okay */ - { - rv = IP_HOST_PPPOE_BIND(0, a_entry_id, pppoev6_sid_table.entry_id, A_TRUE); - if ( rv != SW_OK) - { - aos_printk("IP_HOST_PPPOE_BIND failed (entry: %d, rv: %d)... \n", - a_entry_id, rv); - PPPOE_SESSION_TABLE_DEL(0, &pppoev6_sid_table); - return SW_FAIL; - } - droute_entry_id = a_entry_id; - } - else - { - PPPOE_SESSION_TABLE_DEL(0, &pppoev6_sid_table); - return SW_FAIL; - } - } - else - { - aos_printk("PPPoE session add failed.. (id: %d)\n", - pppoev6_sid_table.session_id); - aos_printk("rv: %d\n", rv); - return SW_FAIL; - } - } - else - { - droute_entry_id = nh_arp_entry.entry_id; - } - ipv6_droute_add_acl_rules(&local_lan6ip, droute_entry_id); - } - else /* Not the same session id */ - { - if (PPPOE_STATUS_GET(0, &ena) != SW_OK) - { - if (!ena) - { - if (PPPOE_STATUS_SET(0, A_TRUE) != SW_OK) - { - aos_printk("Cannot enable the PPPoE mode\n"); - return SW_FAIL; - } - } - } - memset(&nh_arp_entry, 0, sizeof(nh_arp_entry)); - memcpy((void *)&nh_arp_entry.ip6_addr, (void *)next_hop, sizeof(nh_arp_entry.ip6_addr)); - nh_arp_entry.flags = FAL_IP_IP6_ADDR; - rv = IP_HOST_GET(0, FAL_IP_ENTRY_IPADDR_EN, &nh_arp_entry); - if (rv != SW_OK) - { - /* ARP alread setup. */ - return SW_OK; - } - pppoev6_sid_table.session_id = ppp_sid2; - pppoev6_sid_table.multi_session = 1; - pppoev6_sid_table.uni_session = 1; - pppoev6_sid_table.entry_id = 0; - /* set the PPPoE edit reg (0x2200), and PPPoE session reg (0x5f000) */ - rv = PPPOE_SESSION_TABLE_ADD(0, &pppoev6_sid_table); - if (rv == SW_OK) - { - a_int32_t a_entry_id = -1; - - PPPOE_SESSION_ID_SET(0, pppoev6_sid_table.entry_id, pppoev6_sid_table.session_id); - aos_printk("pppoe session: %d, entry_id: %d\n", - pppoev6_sid_table.session_id, pppoev6_sid_table.entry_id); - /* create the peer host ARP entry */ - a_entry_id = arp_hw_add(S17_WAN_PORT, wan_fid, (void *)next_hop, ppp_peer_mac2, 1); - if (a_entry_id >= 0) /* hostentry creation okay */ - { - rv = IP_HOST_PPPOE_BIND(0, a_entry_id, pppoev6_sid_table.entry_id, A_TRUE); - if ( rv != SW_OK) - { - aos_printk("IP_HOST_PPPOE_BIND failed (entry: %d, rv: %d)... \n", - a_entry_id, rv); - PPPOE_SESSION_TABLE_DEL(0, &pppoev6_sid_table); - return SW_FAIL; - } - droute_entry_id = a_entry_id; - } - else - { - PPPOE_SESSION_TABLE_DEL(0, &pppoev6_sid_table); - return SW_FAIL; - } - } - else - { - aos_printk("PPPoE session add failed.. (id: %d)\n", - pppoev6_sid_table.session_id); - aos_printk("rv: %d\n", rv); - return SW_FAIL; - } - ipv6_droute_add_acl_rules(&local_lan6ip, droute_entry_id); - } - } - - return SW_OK; -} - -uint32_t napt_set_ipv6_default_route(void) -{ - sw_error_t rv; - static a_bool_t ipv6_droute_setup = A_FALSE; - static struct ipv6_default_route_binding ipv6_droute_bind = {IN6ADDR_ANY_INIT,0}; - struct in6_addr local_lan6ip = IN6ADDR_ANY_INIT; - unsigned long flags; - - if (((nat_chip_ver&0xffff)>>8) == DESS_CHIP_VER) - return SW_OK; - - /* search for the next hop (s)*/ - if (NF_S17_WAN_TYPE_IP == nf_athrs17_hnat_wan_type) - { - struct in6_addr *next_hop = get_ipv6_default_gateway(); - - // printk("IPv6 next hop: %pI6\n", next_hop); - - if (next_hop != NULL) - { - fal_host_entry_t ipv6_neigh_entry; - - if (__ipv6_addr_type(next_hop) == IPV6_ADDR_LINKLOCAL) - return SW_OK; - - local_irq_save(flags); - memcpy(&local_lan6ip, &lan6ip, sizeof(struct in6_addr)); - local_irq_restore(flags); - - memset(&ipv6_neigh_entry, 0, sizeof(ipv6_neigh_entry)); - memcpy(&ipv6_neigh_entry.ip6_addr, next_hop, 16); - ipv6_neigh_entry.flags = FAL_IP_IP6_ADDR; - rv = IP_HOST_GET(0, FAL_IP_ENTRY_IPADDR_EN, &ipv6_neigh_entry); - if ((rv != SW_OK)||(__ipv6_addr_type(&local_lan6ip) == IPV6_ADDR_ANY)) - { - if (ipv6_droute_setup) - { - ipv6_droute_del_acl_rules(); - memset(&ipv6_droute_bind, 0, sizeof(ipv6_droute_bind)); - ipv6_droute_setup = A_FALSE; - } - } - else - { - if (ipv6_droute_setup) - { - if (!ipv6_addr_equal(&ipv6_droute_bind.next_hop, next_hop) || - ipv6_droute_bind.nh_entry_id != ipv6_neigh_entry.entry_id) - { - ipv6_droute_del_acl_rules(); - } - } - ipv6_droute_bind.next_hop = *next_hop; - ipv6_droute_bind.nh_entry_id = ipv6_neigh_entry.entry_id; - - ipv6_droute_add_acl_rules(&local_lan6ip, ipv6_neigh_entry.entry_id); - ipv6_droute_setup = A_TRUE; - } - } - else - { - if (ipv6_droute_setup) - { - ipv6_droute_del_acl_rules(); - memset(&ipv6_droute_bind, 0, sizeof(ipv6_droute_bind)); - ipv6_droute_setup = A_FALSE; - } - } - } - else if (NF_S17_WAN_TYPE_IP == nf_athrs17_hnat_wan_type) - { - add_pppoev6_host_entry(); - } - - return SW_OK; -} -#endif /* ifdef CONFIG_IPV6_HWACCEL */ - -static sw_error_t hnat_add_host_route( - fal_ip4_addr_t ip_addr, - uint32_t prefix_len) -{ - fal_host_route_t host_route; - - memset(&host_route, 0, sizeof(fal_host_route_t)); - - fal_ip_host_route_get(0, 0, &host_route); - if ((host_route.route_addr.ip4_addr == ip_addr) && - (host_route.prefix_length == prefix_len) && - host_route.valid) - return SW_OK; - - host_route.valid = A_TRUE; - host_route.vrf_id = 0; - host_route.ip_version = 0; - host_route.route_addr.ip4_addr = ip_addr; - host_route.prefix_length = prefix_len; - - return fal_ip_host_route_set(0, 0, &host_route); -} -static sw_error_t setup_interface_entry(char *list_if, int is_wan) -{ - char temp[IFNAMSIZ*4]; /* Max 4 interface entries right now. */ - char *dev_name, *list_all; - struct net_device *nat_dev; - struct in_device *in_device_lan = NULL, *in_device_wan = NULL; - uint8_t *devmac, if_mac_addr[MAC_LEN]; - char *br_name; - uint32_t vid = 0; - sw_error_t setup_error; - uint32_t ipv6 = 0; - - memcpy(temp, list_if, strlen(list_if)+1); - list_all = temp; - - setup_error = SW_FAIL; - rcu_read_lock(); - while ((dev_name = strsep(&list_all, " ")) != NULL) - { - nat_dev = dev_get_by_name(&init_net, dev_name); - if (NULL == nat_dev) - { - // printk("%s: Cannot get device %s by name!\n", __FUNCTION__, dev_name); - setup_error = SW_FAIL; - continue; - } -#if defined (CONFIG_BRIDGE) -#ifdef KVER32 - if (NULL != br_port_get_rcu(nat_dev)) /* under bridge interface. */ - { - /* Get bridge interface name */ - br_name = (char *)(br_port_get_rcu(nat_dev)->br->dev->name); - if (!is_wan) { - strlcat (nat_lan_dev_list, " ", sizeof(nat_lan_dev_list)); - strlcat (nat_lan_dev_list, br_name, sizeof(nat_lan_dev_list)); - } - /* Get dmac */ - devmac = (uint8_t *)(br_port_get_rcu(nat_dev)->br->dev->dev_addr); - } -#else - if (NULL != nat_dev->br_port) /* under bridge interface. */ - { - /* Get bridge interface name */ - br_name = (char *)nat_dev->br_port->br->dev->name; - //memcpy (nat_bridge_dev, br_name, sizeof(br_name)); - strcat (nat_lan_dev_list, " "); - strcat (nat_lan_dev_list, br_name); - /* Get dmac */ - devmac = (uint8_t *)nat_dev->br_port->br->dev->dev_addr; - } -#endif - else -#endif /* CONFIG_BRIDGE */ - { - devmac = (uint8_t *)nat_dev->dev_addr; - } - /* get vid */ -#if 0 -#if defined(CONFIG_VLAN_8021Q) || defined(CONFIG_VLAN_8021Q_MODULE) - vid = vlan_dev_vlan_id(nat_dev); -#else - vid = 0; -#endif -#endif - if(is_wan) - vid = nat_wan_vid; - else - vid = nat_lan_vid; -#ifdef CONFIG_IPV6_HWACCEL - ipv6 = 1; - if (is_wan) - { - wan_fid = vid; - } -#else - ipv6 = 0; - if (is_wan) - { - if (NF_S17_WAN_TYPE_PPPOEV6 == nf_athrs17_hnat_wan_type) - ipv6 = 1; - wan_fid = vid; - } -#endif -#ifdef ISISC - if (0 == is_wan) /* Not WAN -> LAN */ - { - /* Setup private and netmask as soon as possible */ - if (br_port_get_rcu(nat_dev)) /* under bridge interface. */ - { - in_device_lan = (struct in_device *) (br_port_get_rcu(nat_dev)->br->dev->ip_ptr); - } - else - { - in_device_lan = (struct in_device *) nat_dev->ip_ptr; - } - - if ((in_device_lan) && (in_device_lan->ifa_list)) - { - nat_hw_prv_mask_set((a_uint32_t)(in_device_lan->ifa_list->ifa_mask)); - nat_hw_prv_base_set((a_uint32_t)(in_device_lan->ifa_list->ifa_address)); -#ifndef KVER32 - printk("Set private base 0x%08x for %s\n", (a_uint32_t)(in_device_lan->ifa_list->ifa_address), nat_dev->br_port->br->dev->name); -#endif - memcpy(&lanip, (void *)&(in_device_lan->ifa_list->ifa_address), 4); /* copy Lan port IP. */ - memcpy(&lanipmask, (void *)&(in_device_lan->ifa_list->ifa_mask), 4); -#ifndef ISISC - redirect_internal_ip_packets_to_cpu_on_wan_add_acl_rules((a_uint32_t)(in_device_lan->ifa_list->ifa_address), - (a_uint32_t)(in_device_lan->ifa_list->ifa_mask)); -#endif - } - - if(setup_lan_if) { - dev_put(nat_dev); - rcu_read_unlock(); - return SW_OK; - } else { - setup_lan_if = 1; - } - } -#endif - if (1 == is_wan) { - if (br_port_get_rcu(nat_dev)) { - in_device_wan = (struct in_device *) (br_port_get_rcu(nat_dev)->br->dev->ip_ptr); - } else { - in_device_wan = (struct in_device *) nat_dev->ip_ptr; - } - if((nf_athrs17_hnat_wan_type == NF_S17_WAN_TYPE_IP) && - (in_device_wan) && (in_device_wan->ifa_list)) - { - a_uint32_t index; - - if (((nat_chip_ver&0xffff) >> 8) == DESS_CHIP_VER) { - a_uint32_t ip, len; - - ip = in_device_wan->ifa_list->ifa_address & in_device_wan->ifa_list->ifa_mask; - ip = ntohl(ip); - len = 32 - ffs(ntohl(in_device_wan->ifa_list->ifa_mask)); - hnat_add_host_route(ip, len); - } - nat_hw_pub_ip_add(ntohl((a_uint32_t)(in_device_wan->ifa_list->ifa_address)), - &index); - HNAT_PRINTK("pubip add 0x%x\n", (a_uint32_t)(in_device_wan->ifa_list->ifa_address)); - } - } - memcpy(if_mac_addr, devmac, MAC_LEN); - devmac = if_mac_addr; - dev_put(nat_dev); - - if(if_mac_add(devmac, vid, ipv6) != 0) - { - setup_error = SW_FAIL; - continue; - } - else - { - setup_error = SW_OK; - break; - } - } - - rcu_read_unlock(); - return setup_error; -} - -static void setup_dev_list(void) -{ - fal_vlan_t entry; - uint32_t tmp_vid = 0xffffffff; - - /*get the vlan entry*/ - while(1) { - if(SW_OK != VLAN_NEXT(0, tmp_vid, &entry)) - break; - tmp_vid = entry.vid; - if(tmp_vid != 0) { - if(entry.mem_ports & nat_wan_port) { - /*wan port*/ - HNAT_PRINTK("wan port vid:%d\n", tmp_vid); - nat_wan_vid = tmp_vid; - snprintf(nat_wan_dev_list, IFNAMSIZ*5, - "eth0.%d eth0 pppoe-wan erouter0 br-wan", - tmp_vid); - } else { - /*lan port*/ - HNAT_PRINTK("lan port vid:%d\n", tmp_vid); - nat_lan_vid = tmp_vid; - snprintf(nat_lan_dev_list, IFNAMSIZ*4, "eth0.%d eth1 eth1.%d br-lan", - tmp_vid, tmp_vid); - } - } - } -} - -static int setup_all_interface_entry(void) -{ - //static int setup_lan_if=0; - static int setup_default_vid = 0; - int i = 0; - - setup_dev_list(); - - if (0 == setup_default_vid) - { - for (i=0; i<7; i++) /* For AR8327/AR8337, only 7 port */ - { -#ifdef NAT_TODO /* need to implement here */ - PORTVLAN_ROUTE_DEFV_SET(0, i); -#endif - } - setup_default_vid = 1; - } - - //if (0 == setup_lan_if) - { -#ifdef ISISC - //MISC_ARP_CMD_SET(0, FAL_MAC_FRWRD); /* Should be put in init function. */ -#if 0 - MISC_ARP_SP_NOT_FOUND_SET(0, FAL_MAC_RDT_TO_CPU); -#endif -#endif - if (SW_OK == setup_interface_entry(nat_lan_dev_list, 0)) - { - //setup_lan_if = 1; /* setup LAN interface entry success */ - //printk("Setup LAN interface entry done!\n"); - } - } - - if (0 == setup_wan_if) - { - if (SW_OK == setup_interface_entry(nat_wan_dev_list, 1)) - { - setup_wan_if = 1; /* setup WAN interface entry success */ - } - } - if (((nat_chip_ver&0xffff)>>8) == NAT_CHIP_VER_8327) { - if ((nf_athrs17_hnat_wan_type == NF_S17_WAN_TYPE_PPPOE) || - (nf_athrs17_hnat_wan_type == NF_S17_WAN_TYPE_PPPOEV6)) - { - uint8_t buf[6]; - - memcpy(buf, nf_athrs17_hnat_ppp_peer_mac, ETH_ALEN); - HNAT_PRINTK("Peer MAC: %s ", buf); - /* add the peer interface with VID */ - if_mac_add(buf, wan_fid, 0); - HNAT_PRINTK(" --> (%.2x-%.2x-%.2x-%.2x-%.2x-%.2x)\n", \ - buf[0], buf[1], buf[2], buf[3], buf[4], buf[5]); - memcpy(&wanip, (void *)&nf_athrs17_hnat_wan_ip, 4); - } - } - - return 1; -} - -/* check for pppoe session change */ -static void isis_pppoe_check_for_redial(void) -{ - if (nf_athrs17_hnat_wan_type == NF_S17_WAN_TYPE_IP) - return; - - if(((nf_athrs17_hnat_wan_type == NF_S17_WAN_TYPE_PPPOE) \ - || (nf_athrs17_hnat_wan_type == NF_S17_WAN_TYPE_PPPOEV6)) \ - && (pppoetbl.session_id != 0)) - { - if(pppoetbl.session_id != nf_athrs17_hnat_ppp_id) - { - aos_printk("%s: PPPoE session ID changed... \n", __func__); - if (nf_athrs17_hnat_wan_type != NF_S17_WAN_TYPE_PPPOEV6) - { - if (PPPOE_SESSION_TABLE_DEL(0, &pppoetbl) != SW_OK) - { - aos_printk("delete old pppoe session %d entry_id %d failed.. \n", pppoetbl.session_id, pppoetbl.entry_id); - return; - } - - /* force PPPoE parser for multi- and uni-cast packets; for v1.0.7+ */ - pppoetbl.session_id = nf_athrs17_hnat_ppp_id; - pppoetbl.multi_session = 1; - if (((nat_chip_ver & 0xffff)>>8) == NAT_CHIP_VER_8327) - pppoetbl.uni_session = 1; - else - pppoetbl.uni_session = 0; - pppoetbl.entry_id = 0; - /* set the PPPoE edit reg (0x2200), and PPPoE session reg (0x5f000) */ - if (PPPOE_SESSION_TABLE_ADD(0, &pppoetbl) == SW_OK) - { - PPPOE_SESSION_ID_SET(0, pppoetbl.entry_id, pppoetbl.session_id); - printk("%s: new pppoe session id: %x, entry_id: %x\n", __func__, pppoetbl.session_id, pppoetbl.entry_id); - } - } - else /* nf_athrs17_hnat_wan_type == NF_S17_WAN_TYPE_PPPOEV6 */ - { - /* reset the session Id only */ - aos_printk("IPV6 PPPOE mode... \n"); - pppoetbl.session_id = nf_athrs17_hnat_ppp_id; - PPPOE_SESSION_ID_SET(0, pppoetbl.entry_id, pppoetbl.session_id); - printk("%s: new pppoe session id: %x, entry_id: %x\n", __func__, pppoetbl.session_id, pppoetbl.entry_id); - } - /* read back the WAN IP */ - memcpy(&wanip, (void *)&nf_athrs17_hnat_wan_ip, 4); - aos_printk("Read the WAN IP back... %.8x\n", *(uint32_t *)&wanip); - /* change the PPPoE ACL to ensure the packet is correctly forwarded by the HNAT engine */ - pppoe_add_acl_rules(*(uint32_t *)&wanip, *(uint32_t *)&lanip, - *(uint32_t *)&lanipmask, pppoe_gwid); - } - } -} - -#ifdef ISIS /* only for S17 */ -static void pppoev6_mac6_loop_dev(void) -{ -#define PPPOEV6_SESSION_ID 0xfffe - fal_pppoe_session_t ptbl; - sw_error_t rv; - a_uint32_t entry; - - memset(&ptbl, 0, sizeof(fal_pppoe_session_t)); - - aos_printk("%s: set MAC6 as loopback device\n", __func__); - - ptbl.session_id = PPPOEV6_SESSION_ID; - ptbl.multi_session = 1; - ptbl.uni_session = 1; - ptbl.entry_id = 0xe; - - /* set the PPPoE edit reg (0x2200), and PPPoE session reg (0x5f000) */ - if (PPPOE_SESSION_TABLE_ADD(0, &ptbl) == SW_OK) - { - PPPOE_SESSION_ID_SET(0, ptbl.entry_id, ptbl.session_id); - aos_printk("%s: pppoe session id: %d added into entry: %d \n", __func__, ptbl.session_id, ptbl.entry_id); - } - else - { - aos_printk("%s: failed on adding pppoe session id: %d\n", __func__, ptbl.session_id); - } - - /* PPPoE entry 0 */ - entry = PPPOEV6_SESSION_ID; - HSL_REG_ENTRY_SET(rv, 0, PPPOE_EDIT, 0, (a_uint8_t *) (&entry), sizeof (a_uint32_t)); - - aos_printk("%s: end of function... \n", __func__); -} - -static void pppoev6_remove_parser(uint32_t entry_id) -{ - sw_error_t rv; - a_uint32_t entry; - - aos_printk("%s: clear entry id: %d\n", __func__, entry_id); - /* clear the session id in the PPPoE parser engine */ - entry = 0; - HSL_REG_ENTRY_SET(rv, 0, PPPOE_SESSION, - entry_id, (a_uint8_t *) (&entry), sizeof (a_uint32_t)); -} - -#if 0 -static void pppoev6_mac6_stop_learning(void) -{ - /* do not disable this port if some other registers are already filled in - to prevent setting conflict */ - int val = S17_P6PAD_MODE_REG_VALUE; - sw_error_t rv; - a_uint32_t entry; - - if ( val != (1<<24)) - { - aos_printk("%s: MAC 6 already being used!\n", __FUNCTION__); - return; - } - - - /* clear the MAC6 learning bit */ - HSL_REG_ENTRY_GET(rv, 0, PORT_LOOKUP_CTL, 6, (a_uint8_t *) (&entry), sizeof (a_uint32_t)); - entry = entry & ~(1<<20); - HSL_REG_ENTRY_SET(rv, 0, PORT_LOOKUP_CTL, 6, (a_uint8_t *) (&entry), sizeof (a_uint32_t)); - - /* force loopback mode */ - entry = 0x7e; - HSL_REG_ENTRY_SET(rv, 0, PORT_STATUS, 6, (a_uint8_t *) (&entry), sizeof (a_uint32_t)); - entry = 0x10; - HSL_REG_ENTRY_SET(rv, 0, PORT_HDR_CTL, 6, (a_uint8_t *) (&entry), sizeof (a_uint32_t)); -} -#endif -#endif // ifdef ISIS - -static int add_pppoe_host_entry(uint32_t sport, a_int32_t arp_entry_id) -{ - a_bool_t ena; - int rv = SW_OK; - fal_host_entry_t nh_arp_entry; - - if (0xffff == wan_fid) - { - printk("%s: Cannot get WAN vid!\n", __FUNCTION__); - return SW_FAIL; - } - - if (PPPOE_STATUS_GET(0, &ena) != SW_OK) - { - aos_printk("Cannot get the PPPoE mode\n"); - ena = 0; - } - - memset(&nh_arp_entry, 0, sizeof(nh_arp_entry)); - nh_arp_entry.ip4_addr = ntohl(nf_athrs17_hnat_ppp_peer_ip); - nh_arp_entry.flags = FAL_IP_IP4_ADDR; - rv = IP_HOST_GET(0, FAL_IP_ENTRY_IPADDR_EN, &nh_arp_entry); - if (SW_OK != rv || pppoetbl.session_id != nf_athrs17_hnat_ppp_id) - { - if ((!ena) && (PPPOE_STATUS_SET(0, A_TRUE) != SW_OK)) - aos_printk("Cannot enable the PPPoE mode\n"); - - aos_printk("PPPoE enable mode: %d\n", ena); - - pppoetbl.session_id = nf_athrs17_hnat_ppp_id; - pppoetbl.multi_session = 1; - if (((nat_chip_ver & 0xffff)>>8) == NAT_CHIP_VER_8327) - pppoetbl.uni_session = 1; - else - pppoetbl.uni_session = 0; - pppoetbl.entry_id = 0; - - /* set the PPPoE edit reg (0x2200), and PPPoE session reg (0x5f000) */ - rv = PPPOE_SESSION_TABLE_ADD(0, &pppoetbl); - if (rv == SW_OK) - { - uint8_t mbuf[6], ibuf[4]; - a_int32_t a_entry_id = -1; - a_uint32_t index; - - PPPOE_SESSION_ID_SET(0, pppoetbl.entry_id, pppoetbl.session_id); - aos_printk("pppoe session: %d, entry_id: %d\n", pppoetbl.session_id, pppoetbl.entry_id); - - if (((nat_chip_ver&0xffff)>>8) == DESS_CHIP_VER) { - hnat_add_host_route(ntohl(nf_athrs17_hnat_wan_ip), - HOST_PREFIX_MAX); - } - - /* create the peer host ARP entry */ - memcpy(ibuf, (void *)&nf_athrs17_hnat_ppp_peer_ip, 4); - memcpy(mbuf, nf_athrs17_hnat_ppp_peer_mac, ETH_ALEN); - - a_entry_id = arp_hw_add(S17_WAN_PORT, wan_fid, ibuf, mbuf, 0); - if (a_entry_id >= 0) /* hostentry creation okay */ - { - aos_printk("(1)Bind PPPoE session ID: %d, entry_id: %d to host entry: %d\n", \ - pppoetbl.session_id, pppoetbl.entry_id, a_entry_id); - - rv = IP_HOST_PPPOE_BIND(0, a_entry_id, pppoetbl.entry_id, A_TRUE); - if ( rv != SW_OK) - { - aos_printk("IP_HOST_PPPOE_BIND failed (entry: %d, rv: %d)... \n", a_entry_id, rv); - } - - aos_printk("adding ACLs \n"); - pppoe_gwid = a_entry_id; - pppoe_add_acl_rules(nf_athrs17_hnat_wan_ip, *(uint32_t *)&lanip, - *(uint32_t *)&lanipmask, a_entry_id); - nat_hw_pub_ip_add(ntohl(nf_athrs17_hnat_wan_ip), &index); - aos_printk("ACL creation okay... \n"); - } else { - HNAT_PRINTK("pppoe arp add fail!\n"); - } - } - else - { - aos_printk("PPPoE session add failed.. (id: %d)\n", pppoetbl.session_id); - aos_printk("rv: %d\n", rv); - } - -#ifdef ISIS - if (nf_athrs17_hnat_wan_type == NF_S17_WAN_TYPE_PPPOEV6) - { - aos_printk("IPV6 PPPOE mode... (share the same ID with IPV4's)\n"); - pppoev6_mac6_loop_dev(); - pppoev6_remove_parser(pppoetbl.entry_id); - - /* bind the first LAN host to the pseudo PPPoE ID */ - rv = IP_HOST_PPPOE_BIND(0, arp_entry_id, 0, A_TRUE); - if ( rv != SW_OK) - { - aos_printk("IP_HOST_PPPOE_BIND failed (entry: %d, rv: %d)... \n", arp_entry_id, rv); - } - } -#endif // ifdef ISIS - } -#ifdef ISIS - else /* ena */ - { - if ((nf_athrs17_hnat_wan_type == NF_S17_WAN_TYPE_PPPOEV6) && - (sport != S17_WAN_PORT)&& (arp_entry_id != 0)) - { - aos_printk("IPV6 PPPoE mode\n"); - /* bind LAN hosts to the pseudo PPPoE ID */ - rv = IP_HOST_PPPOE_BIND(0, arp_entry_id, 0, A_TRUE); - if ( rv != SW_OK) - { - aos_printk("IP_HOST_PPPOE_BIND failed (entry: %d, rv: %d)... \n", arp_entry_id, rv); - } - } - } -#endif // ifdef ISIS - - return SW_OK; -} - -static int -dev_check(char *in_dev, char *dev_list) -{ - char *list_dev; - char temp[100] = {0}; - char *list; - - if(!in_dev || !dev_list) - { - return 0; - } - - strlcpy(temp, dev_list, sizeof(temp)); - list = temp; - - while ((list_dev = strsep(&list, " ")) != NULL) - { - HNAT_PRINTK("%s: strlen:%d list_dev:%s in_dev:%s\n", - __func__, strlen(list_dev), list_dev, in_dev); - - if (!strncmp(list_dev, in_dev, strlen(list_dev))) - { - HNAT_PRINTK("%s: %s\n", __FUNCTION__, list_dev); - return 1; - } - } - - return 0; -} - -#ifndef ISISC -static uint32_t get_netmask_from_netdevice(const struct net_device *in_net_dev) -{ - struct in_device *my_in_device = NULL; - uint32_t result = 0xffffff00; - - if((in_net_dev) && (in_net_dev->ip_ptr != NULL)) - { - my_in_device = (struct in_device *)(in_net_dev->ip_ptr); - if(my_in_device->ifa_list != NULL) - { - result = my_in_device->ifa_list->ifa_mask; - } - } - - return result; -} -#endif - - -static void hnat_add_neigh(struct neighbour *neigh) -{ - struct nat_helper_bg_msg msg; - struct net_device *dev = NULL; - - memset(&msg, 0, sizeof(msg)); - msg.arp_in.ip = *((uint32_t *)neigh->primary_key); - memcpy(msg.arp_in.mac, neigh->ha, ETH_ALEN); - strlcpy(msg.arp_in.name, neigh->dev->name, IFNAMSIZ); - msg.arp_in.in = neigh->dev; - - if (neigh->dev->priv_flags & IFF_EBRIDGE) { - if (!(dev = br_port_dev_get(neigh->dev, neigh->ha, NULL, 0))) { - HNAT_ERR_PRINTK("Failed to find bridge port by [%pM]\n", - neigh->ha); - return ; - } - } else { - dev = neigh->dev; - dev_hold(dev); - } - - if (strncmp(dev->name, "eth", strlen("eth")) && - strncmp(dev->name, "erouter", strlen("erouter"))) { - dev_put(dev); - return ; - } - - dev_put(dev); - - msg.msg_type = NAT_HELPER_ARP_ADD_MSG; - bg_ring_buf_write(msg); -} - -static void hnat_del_neigh(struct neighbour *neigh) -{ - struct nat_helper_bg_msg msg; - - memset(&msg, 0, sizeof(msg)); - msg.arp_in.ip = ntohl(*((uint32_t *)neigh->primary_key)); - - msg.msg_type = NAT_HELPER_ARP_DEL_MSG; - bg_ring_buf_write(msg); -} - -static int hnat_netevent_event(struct notifier_block *unused, unsigned long event, void *ptr) -{ - struct neigh_table *tbl; - struct neighbour *neigh; - - if (event != NETEVENT_NEIGH_UPDATE) - return NOTIFY_DONE; - - neigh = ptr; - tbl = neigh->tbl; - - if (tbl->family != AF_INET) - return NOTIFY_DONE; - - HNAT_PRINTK("netevent state %d for ip[%pI4]\n", - neigh->nud_state, (uint32_t *)neigh->primary_key); - - if (neigh->nud_state & NUD_VALID) { - if (neigh->nud_state & NUD_NOARP) { - return NOTIFY_DONE; - } - - HNAT_PRINTK("New ARP entry ip[%pI4] mac[%pM]\n", - (uint32_t *)neigh->primary_key, neigh->ha); - hnat_add_neigh(neigh); - } else { - HNAT_PRINTK("Del ARP entry ip[%pI4] mac[%pM] with status[%d]\n", - (uint32_t *)neigh->primary_key, neigh->ha, neigh->nud_state); - hnat_del_neigh(neigh); - } - - return NOTIFY_DONE; -} - -#ifdef NAT_BACKGROUND_TASK -static unsigned int -arp_del(struct nat_helper_bg_msg *msg) -{ - fal_host_entry_t host; - - memset(&host, 0, sizeof(host)); - - if (!nat_hw_prv_base_is_match(msg->arp_in.ip)) - return 0; - - if (napt_hw_get_by_sip(msg->arp_in.ip)) { - host.flags |= FAL_IP_IP4_ADDR; - host.ip4_addr = msg->arp_in.ip; - IP_HOST_DEL(0, FAL_IP_ENTRY_IPADDR_EN, &host); - } - - return 0; -} - -static unsigned int -arp_add(struct nat_helper_bg_msg *msg) -{ - uint8_t *smac; - uint8_t dev_is_lan = 0; - uint32_t sport = 0, vid = 0; - a_bool_t prvbasemode = 1; - sw_error_t rv = SW_OK; - struct arp_in_msg *arp_info = &msg->arp_in; - a_int32_t arp_entry_id = -1; - fal_fdb_entry_t entry; - - - /* check for PPPoE redial here, to reduce overheads */ - isis_pppoe_check_for_redial(); - - /* do not write out host table if HNAT is disabled */ - if (!nf_athrs17_hnat) - return 0; - - setup_all_interface_entry(); - - if(dev_check((char *)arp_info->name, (char *)nat_wan_dev_list)) - { - - } - else if (dev_check((char *)arp_info->name, (char *)nat_lan_dev_list)) - { - dev_is_lan = 1; - } - else - { - HNAT_INFO_PRINTK("Not Support device: %s\n", (char *)arp_info->name); - return 0; - } - - if(dev_is_lan) { - vid = nat_lan_vid; - } else { - vid = nat_wan_vid; - } - - memset(&entry, 0, sizeof(entry)); - - entry.fid = vid; - - smac = arp_info->mac; - aos_mem_copy(&(entry.addr), smac, sizeof(fal_mac_addr_t)); - if(fal_fdb_entry_search(0, &entry) == SW_OK) { - vid = entry.fid; - sport = 0; - while (sport < 32) { - if(entry.port.map & (1 << sport)) { - break; - } - sport++; - } - } else { - HNAT_PRINTK("not find the FDB entry\n"); - } - - - if (sport == 0) { - HNAT_PRINTK("Not the expected arp, ignore it!\n"); - return 0; - } - - arp_entry_id = arp_hw_add(sport, vid, (a_uint8_t *)&arp_info->ip, smac, 0); - if(arp_entry_id < 0) - { - HNAT_ERR_PRINTK("ARP entry error!!\n"); - return 0; - } - - if (0 == dev_is_lan) - { - struct in_device *in_dev; - - in_dev = __in_dev_get_rtnl(arp_info->in); - if (in_dev) { - if (in_dev->ifa_list) { - *(uint32_t *)&wanip = ntohl(in_dev->ifa_list->ifa_local); - } - } -#ifdef MULTIROUTE_WR - wan_nh_add((u_int8_t *)&arp_info->ip, smac, arp_entry_id); -#endif - } - - if(dev_is_lan && nat_hw_prv_base_can_update()) - { - nat_hw_flush(); - nat_hw_prv_base_update_disable(); -#ifdef MULTIROUTE_WR - //multi_route_indev = in; -#endif - } - multi_route_indev = arp_info->in; - - if ((nf_athrs17_hnat_wan_type == NF_S17_WAN_TYPE_PPPOE) || - (nf_athrs17_hnat_wan_type == NF_S17_WAN_TYPE_PPPOEV6)) - { - add_pppoe_host_entry(sport, arp_entry_id); - } - - if (((nat_chip_ver & 0xffff)>>8) != NAT_CHIP_VER_8327) - return 1; - - /* check for SIP and DIP range */ - if ((lanip[0] != 0) && (wanip[0] != 0)) - { - rv = NAT_PRV_ADDR_MODE_GET(0, &prvbasemode); - if (rv == SW_NOT_SUPPORTED || rv == SW_NOT_INITIALIZED) { - return 1; - } - else if (rv != SW_OK) { - aos_printk("Private IP base mode check failed: %d\n", prvbasemode); - } - - if (!prvbasemode) /* mode 0 */ - { - if ((lanip[0] == wanip[0]) && (lanip[1] == wanip[1])) - { - if ((lanip[2] & 0xf0) == (wanip[2] & 0xf0)) - { - if (get_aclrulemask()& (1 << S17_ACL_LIST_IPCONF)) - return 0; - - aos_printk("LAN IP and WAN IP conflict... \n"); - /* set h/w acl to filter out this case */ -#ifdef MULTIROUTE_WR - // if ( (wan_nh_ent[0].host_ip != 0) && (wan_nh_ent[0].entry_id != 0)) - if ( (wan_nh_ent[0].host_ip != 0)) - ip_conflict_add_acl_rules(*(uint32_t *)&wanip, *(uint32_t *)&lanip, wan_nh_ent[0].entry_id); -#endif - return 0; - } - } - } - else /* mode 1*/ - { - ;; /* do nothing */ - } - } - - return 1; -} -#endif - -static struct notifier_block hnat_netevent_notifier = { - .notifier_call = hnat_netevent_event, -}; - -#ifdef AUTO_UPDATE_PPPOE_INFO -#if (LINUX_VERSION_CODE < KERNEL_VERSION(3,14,0)) -struct prv_ppp_file { - int k; - struct sk_buff_head xmitq; - struct sk_buff_head recvq; - wait_queue_head_t wait; - atomic_t cnt; - int hlen; - int idx; - int d; -}; -struct prv_ppp { - struct prv_ppp_file file; - char *o; - struct list_head channels; - int n_channels; - spinlock_t rlock; - spinlock_t wlock; - int m; - unsigned int flags; - unsigned int xmitstate; - unsigned int recvstate; - int d; - char *vj; - int mode[6]; - struct sk_buff *xpending; - char *xcmp; - void *xstate; - char *rcmp; - void *rstate; - unsigned long l_xmit; - unsigned long l_recv; - struct net_device *dev; - int resv1; -#ifdef CONFIG_PPP_MULTILINK - int resv2; - u32 resv3; - int resv4; - u32 resv5; - u32 resv6; - struct sk_buff_head rq; -#endif /* CONFIG_PPP_MULTILINK */ -#ifdef CONFIG_PPP_FILTER - char *p_filter; - char *a_filter; - unsigned p_len, a_len; -#endif /* CONFIG_PPP_FILTER */ - char *pnet; -}; - -struct prv_channel { - struct prv_ppp_file file; - struct list_head list; - struct ppp_channel *chan; - struct rw_semaphore sem; - spinlock_t downlock; - struct prv_ppp *ppp; - char *cnet; - struct list_head clist; - rwlock_t uplock; -#ifdef CONFIG_PPP_MULTILINK - u8 resv1; - u8 resv2; - u32 resv3; - int resv4; -#endif -}; -#endif - -static int qcaswitch_pppoe_ip_event(struct notifier_block *this, - unsigned long event, void *ptr) -{ - struct in_ifaddr *ifa = (struct in_ifaddr *)ptr; - struct net_device *dev = (struct net_device *)ifa->ifa_dev->dev; - #if (LINUX_VERSION_CODE < KERNEL_VERSION(3,14,0)) - struct list_head *list; - struct prv_channel *pch; - struct prv_ppp *ppp = netdev_priv(dev); - #endif - struct sock *sk; - struct pppox_sock *po; - static int connection_count = 0; - fal_pppoe_session_t del_pppoetbl; - int channel_count; - struct ppp_channel *ppp_chan[1]; - int channel_protocol; - - if (!((dev->type == ARPHRD_PPP) && (dev->flags & IFF_POINTOPOINT))) - return NOTIFY_DONE; - - if (dev_net(dev) != &init_net) - return NOTIFY_DONE; - - setup_all_interface_entry(); - - switch (event) - { - case NETDEV_UP: - #if (LINUX_VERSION_CODE >= KERNEL_VERSION(3,14,0)) - if (ppp_is_multilink(dev) == 0) { - /* not doing multilink: send it down the first channel */ - channel_count = ppp_hold_channels(dev, ppp_chan, 1); - if (channel_count != 1) - return NOTIFY_DONE; - - channel_protocol = ppp_channel_get_protocol(ppp_chan[0]); - if (channel_protocol == PX_PROTO_OE) - { - if (ppp_chan[0]->private) - { - /* the NETDEV_UP event will be sent many times - * because of ifa operation ifa->ifa_local != ifa->ifa_address - * means that remote ip is really added. - */ - if (ifa->ifa_local == ifa->ifa_address) - { - ppp_release_channels(ppp_chan, 1); - return NOTIFY_DONE; - } - sk = (struct sock *)(ppp_chan[0]->private); - po = (struct pppox_sock*)sk; - connection_count++; - if (((NF_S17_WAN_TYPE_PPPOE == nf_athrs17_hnat_wan_type) && - (0 != nf_athrs17_hnat_ppp_id))) /* another session for IPv6 */ - { - nf_athrs17_hnat_ppp_id2 = ntohs(po->proto.pppoe.pa.sid); - memcpy(nf_athrs17_hnat_ppp_peer_mac2, - po->proto.pppoe.pa.remote, ETH_ALEN); - } else { - nf_athrs17_hnat_wan_type = NF_S17_WAN_TYPE_PPPOE; - nf_athrs17_hnat_wan_ip = ifa->ifa_local; - nf_athrs17_hnat_ppp_peer_ip = ifa->ifa_address; - memcpy(nf_athrs17_hnat_ppp_peer_mac, - po->pppoe_pa.remote, ETH_ALEN); - nf_athrs17_hnat_ppp_id = ntohs(po->pppoe_pa.sid); - } - ppp_release_channels(ppp_chan, 1); - } else { - ppp_release_channels(ppp_chan, 1); - /* channel got unregistered */ - return NOTIFY_DONE; - } - } else { - ppp_release_channels(ppp_chan, 1); - /* channel got unregistered */ - return NOTIFY_DONE; - } - } - #else - //struct prv_ppp *ppp = netdev_priv(dev); - //struct prv_channel *pch; - list = &ppp->channels; - if (list_empty(list)) - return NOTIFY_DONE; - if ((ppp->flags & SC_MULTILINK) == 0) { - list = list->next; - pch = list_entry(list, struct prv_channel, clist); - if (pch->chan) - { - if (pch->chan->private) { - if (ifa->ifa_local == ifa->ifa_address) - return NOTIFY_DONE; - sk = (struct sock *)pch->chan->private; - po = (struct pppox_sock*)sk; - connection_count++; - if (((NF_S17_WAN_TYPE_PPPOE == nf_athrs17_hnat_wan_type) && - (0 != nf_athrs17_hnat_ppp_id))) - { - nf_athrs17_hnat_ppp_id2 = po->num; - memcpy(nf_athrs17_hnat_ppp_peer_mac2, po->pppoe_pa.remote, ETH_ALEN); - } - else - { - nf_athrs17_hnat_wan_type = NF_S17_WAN_TYPE_PPPOE; - nf_athrs17_hnat_wan_ip = ifa->ifa_local; - nf_athrs17_hnat_ppp_peer_ip = ifa->ifa_address; - memcpy(nf_athrs17_hnat_ppp_peer_mac, po->pppoe_pa.remote, ETH_ALEN); - nf_athrs17_hnat_ppp_id = ntohs(po->pppoe_pa.sid); - } - } - } - else - { - return NOTIFY_DONE; - } - } - #endif - break; - - case NETDEV_DOWN: - if (NF_S17_WAN_TYPE_PPPOE != nf_athrs17_hnat_wan_type) - { - return NOTIFY_DONE; - } - connection_count--; - if (ifa->ifa_local == nf_athrs17_hnat_wan_ip) - { - /* PPPoE Interface really down */ - ipv6_droute_del_acl_rules(); - del_pppoetbl.session_id = nf_athrs17_hnat_ppp_id; - del_pppoetbl.multi_session = 1; - if (((nat_chip_ver & 0xffff)>>8) == NAT_CHIP_VER_8327) - del_pppoetbl.uni_session = 1; - else - del_pppoetbl.uni_session = 0; - del_pppoetbl.entry_id = 0; - PPPOE_SESSION_TABLE_DEL(0, &del_pppoetbl); - memset(&pppoetbl, 0, sizeof(pppoetbl)); - nf_athrs17_hnat_wan_type = NF_S17_WAN_TYPE_IP; - nf_athrs17_hnat_wan_ip = 0; - nf_athrs17_hnat_ppp_peer_ip = 0; - nf_athrs17_hnat_ppp_id = 0; - memset(&nf_athrs17_hnat_ppp_peer_mac, 0, ETH_ALEN); - } - else - { - if (0 != nf_athrs17_hnat_ppp_id2) - { - del_pppoetbl.session_id = nf_athrs17_hnat_ppp_id2; - del_pppoetbl.multi_session = 1; - if (((nat_chip_ver & 0xffff)>>8) == NAT_CHIP_VER_8327) - del_pppoetbl.uni_session = 1; - else - del_pppoetbl.uni_session = 0; - del_pppoetbl.entry_id = 0; - PPPOE_SESSION_TABLE_DEL(0, &del_pppoetbl); - memset(&pppoetbl, 0, sizeof(pppoetbl)); - } - nf_athrs17_hnat_ppp_id2 = 0; - memset(&nf_athrs17_hnat_ppp_peer_mac2, 0, ETH_ALEN); - } - qcaswitch_hostentry_flush(); - break; - - default: - break; - } - return NOTIFY_DONE; -} - -/* a linux interface is configured with ipaddr, then - * it becomes a L3 routing interface - * add the router mac of this interface to the table - */ -/* FIXME: only hande pppoe event right now. */ -static int qcaswitch_ip_event(struct notifier_block *this, - unsigned long event, void *ptr) -{ - struct in_ifaddr *ifa = (struct in_ifaddr *)ptr; - struct net_device *dev = (struct net_device *)ifa->ifa_dev->dev; - - if ((dev->type == ARPHRD_PPP) && (dev->flags & IFF_POINTOPOINT)) - { - return qcaswitch_pppoe_ip_event(this, event, ptr); - } - - return NOTIFY_DONE; -} - - -static struct notifier_block qcaswitch_ip_notifier = -{ - .notifier_call = qcaswitch_ip_event, - .priority = 100, -}; -#endif // ifdef AUTO_UPDATE_PPPOE_INFO - -#define HOST_AGEOUT_STATUS 1 -void host_check_aging(void) -{ - fal_host_entry_t *host_entry_p, host_entry= {0}; - sw_error_t rv; - int cnt = 0; - unsigned long flags; - fal_napt_entry_t src_napt = {0}, pub_napt = {0}; - - host_entry_p = &host_entry; - host_entry_p->entry_id = FAL_NEXT_ENTRY_FIRST_ID; - - /*check host is not neccessary, check napt is enough*/ - return; - - local_irq_save(flags); - while (1) - { - host_entry_p->status = HOST_AGEOUT_STATUS; - /* FIXME: now device id is set to 0. */ - rv = IP_HOST_NEXT (0, FAL_IP_ENTRY_STATUS_EN, host_entry_p); - // rv = IP_HOST_NEXT (0, 0, host_entry_p); - if (SW_OK != rv) - break; - if (cnt >= ARP_ENTRY_MAX) // arp entry number - break; - - if (ARP_AGE_NEVER == host_entry_p->status) - continue; - - if ((S17_WAN_PORT == host_entry_p->port_id) && - (host_entry_p->counter_en)) - { - if (0 != host_entry_p->packet) - { - // arp entry is using, update it. - host_entry.status = ARP_AGE; - printk("Update WAN port hostentry!\n"); - IP_HOST_ADD(0, host_entry_p); - } - else - { - printk("Del WAN port hostentry!\n"); - IP_HOST_DEL(0, FAL_IP_ENTRY_IPADDR_EN, host_entry_p); - } - continue; - } - - src_napt.entry_id = FAL_NEXT_ENTRY_FIRST_ID; - memcpy(&src_napt.src_addr, &host_entry_p->ip4_addr, sizeof(fal_ip4_addr_t)); - pub_napt.entry_id = FAL_NEXT_ENTRY_FIRST_ID; - memcpy(&pub_napt.trans_addr, &host_entry_p->ip4_addr, sizeof(fal_ip4_addr_t)); - if((NAPT_NEXT(0, FAL_NAT_ENTRY_SOURCE_IP_EN ,&src_napt) !=0) && \ - (NAPT_NEXT(0, FAL_NAT_ENTRY_PUBLIC_IP_EN ,&pub_napt) != 0)) - { - /* Cannot find naptentry */ - printk("ARP id 0x%x: Cannot find NAPT entry!\n", host_entry_p->entry_id); - IP_HOST_DEL(0, FAL_IP_ENTRY_IPADDR_EN, host_entry_p); - continue; - } - // arp entry is using, update it. - host_entry_p->status = ARP_AGE; - IP_HOST_ADD(0, host_entry_p); - printk("update entry 0x%x port %d\n", host_entry_p->entry_id, host_entry_p->port_id); - cnt++; - } - local_irq_restore(flags); -} - -#ifdef CONFIG_IPV6_HWACCEL -#define IPV6_LEN 16 -#define MAC_LEN 6 -#define PROTO_ICMPV6 0x3a -#define NEIGHBOUR_SOL 135 -#define NEIGHBOUR_AD 136 - -struct icmpv6_option -{ - __u8 type; - __u8 len; - __u8 mac[MAC_LEN]; -}; -#if 0 -static unsigned int ipv6_handle(unsigned int hooknum, - struct sk_buff *skb, - const struct net_device *in, - const struct net_device *out, - int (*okfn)(struct sk_buff *)) -{ - struct sk_buff *new_skb = NULL; - struct nat_helper_bg_msg msg; - /*unsigned long flags = 0;*/ - - if (!nf_athrs17_hnat) - return NF_ACCEPT; - - new_skb = skb_clone(skb, GFP_ATOMIC); - if(new_skb) { - memset(&msg, 0, sizeof(msg)); - msg.msg_type = NAT_HELPER_IPV6_MSG; - msg.ipv6.skb = new_skb; - msg.ipv6.in = (struct net_device *)in; - - /*send msgto background task*/ - /*spin_lock_irqsave(&task_cb.bg_lock, flags);*/ - if(bg_ring_buf_write(msg)) - kfree_skb(new_skb); - /*spin_unlock_irqrestore(&task_cb.bg_lock, flags);*/ - } - - return NF_ACCEPT; - -} -#endif - -#ifdef NAT_BACKGROUND_TASK - -static unsigned int ipv6_bg_handle(struct nat_helper_bg_msg *msg) -{ - struct net_device *in = msg->arp_in.in; - struct sk_buff *skb = msg->arp_in.skb; - - struct ipv6hdr *iph6 = ipv6_hdr(skb); - struct icmp6hdr *icmp6 = icmp6_hdr(skb); - __u8 *sip = ((__u8 *)icmp6)+sizeof(struct icmp6hdr); - struct icmpv6_option *icmpv6_opt = (struct icmpv6_option *)(sip+IPV6_LEN); - __u8 *sa = icmpv6_opt->mac; - - uint32_t sport = 0, vid = 0; - struct inet6_ifaddr *in_device_addr = NULL; - uint8_t dev_is_lan = 0; - uint8_t *smac; - - - /* do not write out host table if HNAT is disabled */ - if (!nf_athrs17_hnat) - return 0; - - setup_all_interface_entry(); - - if(dev_check((char *)in->name, (char *)nat_wan_dev_list)) - { - dev_is_lan = 0; - } - else if (dev_check((char *)in->name, (char *)nat_lan_dev_list)) - { - dev_is_lan = 1; - } - else - { - HNAT_PRINTK("Not Support device: %s\n", (char *)in->name); - return 0; - } - - if(PROTO_ICMPV6 == iph6->nexthdr) - { - if(NEIGHBOUR_AD == icmp6->icmp6_type) - { - fal_fdb_entry_t entry; - if (__ipv6_addr_type((struct in6_addr*)sip) & IPV6_ADDR_LINKLOCAL) - return 0; - -#ifdef AP136_QCA_HEADER_EN - if(arp_if_info_get((void *)(skb->head), &sport, &vid) != 0) - { - return 0; - } - - if ((0 == vid)||(0 == sport)) - { - printk("Error: Null sport or vid!!\n"); - return 0; - } -#else - if(dev_is_lan) { - vid = NAT_LAN_DEV_VID; - } else { - vid = NAT_WAN_DEV_VID; - } - - memset(&entry, 0, sizeof(entry)); - - entry.fid = vid; - smac = skb_mac_header(skb) + MAC_LEN; - aos_mem_copy(&(entry.addr), smac, sizeof(fal_mac_addr_t)); - - if(fal_fdb_entry_search(0, &entry) == SW_OK) { - vid = entry.fid; - sport = 0; - while (sport < 32) { - if(entry.port.map & (1 << sport)) { - break; - } - sport++; - } - } else { - printk("not find the FDB entry\n"); - } -#endif - if ((0 == dev_is_lan) && (S17_WAN_PORT != sport)) - { - printk("Error: WAN port %d\n", sport); - return 0; - } - - HNAT_PRINTK("ND Reply %x %x\n",icmpv6_opt->type,icmpv6_opt->len); - HNAT_PRINTK("isis_v6: incoming packet, sip = %02x%02x:%02x%02x:%02x%02x:%02x%02x:%02x%02x:%02x%02x:%02x%02x:%02x%02x\n" - ,sip[0],sip[1],sip[2],sip[3],sip[4],sip[5],sip[6],sip[7] - ,sip[8],sip[9],sip[10],sip[11],sip[12],sip[13],sip[14],sip[15] - ); - HNAT_PRINTK("isis_v6: incoming packet, sa = %.2x-%.2x-%.2x-%.2x-%.2x-%.2x\n", sa[0], sa[1], sa[2], sa[3], sa[4], sa[5]); - HNAT_PRINTK("isis_v6: vid = %d sport = %d\n", vid, sport); - - //add nd entry - if((2 == icmpv6_opt->type) && (1 == icmpv6_opt->len)) - { - arp_hw_add(sport, vid, sip, sa, 1); - } - else /* ND AD packets without option filed? Fix Me!! */ - { - sa = skb_mac_header(skb) + MAC_LEN; - HNAT_PRINTK("isis_v6 Changed sa = %.2x-%.2x-%.2x-%.2x-%.2x-%.2x\n", sa[0], sa[1], sa[2], sa[3], sa[4], sa[5]); - arp_hw_add(sport, vid, sip, sa, 1); - } - -#ifdef NAT_TODO /* should be ok */ - if ((NULL != in->ip6_ptr) && (NULL != ((struct inet6_dev *)in->ip6_ptr)->addr_list)) -#else - if (NULL != in->ip6_ptr) -#endif - { - //list_for_each_entry(in_device_addr, &(in->ip6_ptr)->addr_list, if_list); - struct inet6_dev *idev = __in6_dev_get(in); - list_for_each_entry(in_device_addr, &idev->addr_list, if_list) { - if (in_device_addr->scope == 0 && - !(in_device_addr->flags & IFA_F_TENTATIVE)) { - break; - } - } - - if (0 == dev_is_lan) - { - /* WAN ipv6 address*/ - memcpy(&wan6ip, (__u8 *)&in_device_addr->addr, sizeof(struct in6_addr)); - HNAT_PRINTK("%s: ipv6 wanip %pI6\n", in->name, &wan6ip); - } - else - { - /* LAN ipv6 address*/ - memcpy(&lan6ip, (__u8 *)&in_device_addr->addr, sizeof(struct in6_addr)); - HNAT_PRINTK("%s: ipv6 lanip %pI6\n", in->name, &lan6ip); - } - } - } - } - - return 1; -} -#endif - -#if 0 -static struct nf_hook_ops ipv6_inhook = -{ - .hook = ipv6_handle, - #if (LINUX_VERSION_CODE < KERNEL_VERSION(4,4,0)) - .owner = THIS_MODULE, - #endif - .pf = PF_INET6, - .hooknum = NF_INET_PRE_ROUTING, - .priority = NF_IP6_PRI_CONNTRACK, -}; -#endif -#endif /* CONFIG_IPV6_HWACCEL */ - -#ifdef NAT_BACKGROUND_TASK - -static void nat_task_entry(struct work_struct *wq) -{ - struct nat_helper_bg_msg msg; - /*unsigned long flags = 0;*/ - unsigned int result = 0; - - msg = *(struct nat_helper_bg_msg *)wq; - - /*spin_lock_irqsave(&task_cb.bg_lock, flags);*/ - bg_ring_buf_read(NULL); - /*spin_unlock_irqrestore(&task_cb.bg_lock, flags);*/ - - if(msg.msg_type == NAT_HELPER_ARP_ADD_MSG) { - result = arp_add(&msg); - } else if (msg.msg_type == NAT_HELPER_ARP_DEL_MSG) { - result = arp_del(&msg); - } - #ifdef CONFIG_IPV6_HWACCEL - else if(msg.msg_type == NAT_HELPER_IPV6_MSG) { - result = ipv6_bg_handle(&msg); - } - #endif - - HNAT_PRINTK("handle msg: %d, result: %d\n", msg.msg_type, result); - -} - -void nat_helper_bg_task_init() -{ - unsigned int i = 0; - struct nat_helper_bg_msg *msg; - /*create the thread and alloc ring buffer*/ - - memset(&task_cb, 0, sizeof(task_cb)); - - task_cb.nat_wq = create_singlethread_workqueue("nat_wq"); - - if(!task_cb.nat_wq) - { - aos_printk("create nat workqueuefail\n"); - return; - } - - /*init lock and alloc the ring buffer*/ - - /*sema_init(&task_cb.bg_sem, 0);*/ - spin_lock_init(&task_cb.bg_lock); - - task_cb.ring.num = NAT_HELPER_MSG_MAX; - task_cb.ring.buf = kzalloc(NAT_HELPER_MSG_MAX * sizeof(struct nat_helper_bg_msg), GFP_ATOMIC); - if(!task_cb.ring.buf) { - aos_printk("ring buf alloc fail!\n"); - return; - } - msg = (struct nat_helper_bg_msg*)task_cb.ring.buf; - for(i = 0; i < task_cb.ring.num; i++) - { - INIT_WORK(&msg[i].work, nat_task_entry); - } - - aos_printk("bg task init successfull!\n"); - -} - -void nat_helper_bg_task_exit() -{ - /*stop the workqueue and release the ring buffer*/ - if(task_cb.nat_wq) - destroy_workqueue(task_cb.nat_wq); - if(task_cb.ring.buf) - kfree(task_cb.ring.buf); -} -#endif - - -extern int napt_procfs_init(void); -extern void napt_procfs_exit(void); - -void host_helper_init(a_uint32_t portbmp) -{ - REG_GET(0, 0, (a_uint8_t *)&nat_chip_ver, 4); - - /* header len 4 with type 0xaaaa */ - HEADER_TYPE_SET(0, A_TRUE, 0xaaaa); - if (((nat_chip_ver & 0xffff)>>8) == NAT_CHIP_VER_8337 || - ((nat_chip_ver & 0xffff)>>8) == NAT_CHIP_VER_DESS) { - /* For S17c (ISISC), it is not necessary to make all frame with header */ - printk("host_helper_init start\n"); - //PORT_TXHDR_MODE_SET(0, 0, FAL_ONLY_MANAGE_FRAME_EN); - /* Fix tag disappear problem, set TO_CPU_VID_CHG_EN, 0xc00 bit1 */ - CPU_VID_EN_SET(0, A_TRUE); - /* set RM_RTD_PPPOE_EN, 0xc00 bit0 */ - RTD_PPPOE_EN_SET(0, A_TRUE); - /* Avoid ARP response storm for HUB, now this fix only apply on PORT5 */ - #if 0 - MISC_ARP_SP_NOT_FOUND_SET(0, FAL_MAC_RDT_TO_CPU); - MISC_ARP_GUARD_SET(0, S17_WAN_PORT, FAL_MAC_IP_PORT_GUARD); - #endif - /* set VLAN_TRANS_TEST register bit, to block packets from WAN port has private dip */ - NETISOLATE_SET(0, A_TRUE); - } else { - PORT_TXHDR_MODE_SET(0, 0, FAL_ALL_TYPE_FRAME_EN); - } - CPU_PORT_STATUS_SET(0, A_TRUE); - IP_ROUTE_STATUS_SET(0, A_TRUE); - - napt_procfs_init(); - memcpy(nat_bridge_dev, nat_lan_dev_list, strlen(nat_lan_dev_list)+1); - - register_netevent_notifier(&hnat_netevent_notifier); -/*hnat not upport ipv6*/ -#if 0 -#ifdef CONFIG_IPV6_HWACCEL - aos_printk("Registering IPv6 hooks... \n"); - nf_register_hook(&ipv6_inhook); -#endif -#endif - -#ifdef AUTO_UPDATE_PPPOE_INFO - register_inetaddr_notifier(&qcaswitch_ip_notifier); -#endif // ifdef AUTO_UPDATE_PPPOE_INFO - - nat_wan_port = portbmp; - - /* Enable ACLs to handle MLD packets */ - upnp_ssdp_add_acl_rules(); - ipv6_snooping_solicted_node_add_acl_rules(); - ipv6_snooping_sextuple0_group_add_acl_rules(); - ipv6_snooping_quintruple0_1_group_add_acl_rules(); - - napt_helper_hsl_init(); -} - -void host_helper_exit(void) -{ - napt_procfs_exit(); - - unregister_netevent_notifier(&hnat_netevent_notifier); -#if 0 -#ifdef CONFIG_IPV6_HWACCEL - nf_unregister_hook(&ipv6_inhook); -#endif -#endif - - #ifdef AUTO_UPDATE_PPPOE_INFO - unregister_inetaddr_notifier(&qcaswitch_ip_notifier); - #endif -} - diff --git a/feeds/ipq807x/qca-ssdk/src/app/nathelper/linux/lib/nat_helper_dt.c b/feeds/ipq807x/qca-ssdk/src/app/nathelper/linux/lib/nat_helper_dt.c deleted file mode 100755 index a76f0a8b9..000000000 --- a/feeds/ipq807x/qca-ssdk/src/app/nathelper/linux/lib/nat_helper_dt.c +++ /dev/null @@ -1,1352 +0,0 @@ -/* - * Copyright (c) 2012, 2015, 2018, The Linux Foundation. All rights reserved. - * Permission to use, copy, modify, and/or distribute this software for - * any purpose with or without fee is hereby granted, provided that the - * above copyright notice and this permission notice appear in all copies. - * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES - * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR - * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES - * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN - * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT - * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. - */ - - -#ifdef KVER32 -#include -#include -#else -#include -#endif -#include -#include -#include -#include - -#include "../nat_helper.h" -#include "../napt_helper.h" -#include "../napt_acl.h" - -#include "fal_type.h" -#include "fal_nat.h" - -#include "nat_helper_dt.h" -#include "nat_helper_hsl.h" - -#define NAPT_CT_POLLING_SEC 5 -#define NPAT_CT_POLLING_QUOTA 256 - -extern int nat_sockopts_init; -extern uint32_t napt_set_default_route(fal_ip4_addr_t dst_addr, fal_ip4_addr_t src_addr); -#ifdef CONFIG_IPV6_HWACCEL -extern uint32_t napt_set_ipv6_default_route(void); -#endif -extern void nat_ipt_sockopts_replace(void); -extern void qcaswitch_hostentry_flush(void); - -#define NAPT_BUFFER_HASH_SIZE (NAPT_TABLE_SIZE) -#define NAPT_BUFFER_SIZE ((NAPT_BUFFER_HASH_SIZE)*8) - -static a_uint32_t napt_buffer_hash_size = NAPT_TABLE_SIZE; -static a_uint32_t napt_buffer_size = (NAPT_BUFFER_HASH_SIZE)*8; -static a_uint32_t napt_ct_hw_cnt = 0; -static a_uint8_t napt_thread_pending = 0; - -a_uint32_t polling_quota = NPAT_CT_POLLING_QUOTA; - -extern int nat_chip_ver; - -struct napt_ct -{ - struct napt_ct *next; - a_uint32_t ct_addr; - a_uint64_t ct_packets; - a_uint8_t in_hw; - a_uint16_t hw_index; - a_uint8_t deny; - a_uint64_t last_jiffies; -}; - -struct napt_debug_counter -{ - a_uint32_t interate_cnt; - a_uint32_t care_cnt; - a_uint32_t thresh_low_cnt; -}; - -struct nhlist_head -{ - struct napt_ct *next; -}; - -static struct nhlist_head *ct_buf_hash_head = NULL; -static struct napt_ct *ct_buf = NULL; -static a_uint32_t ct_buf_ct_cnt = 0; -static struct napt_debug_counter napt_ct_debug_info; - -int scan_period = NAPT_CT_POLLING_SEC; -int scan_enable = 1; -int napt_need_clean = 0; -/*pppoe dhcp siwtch pre-handle*/ -int wan_switch = 0; - - -static a_int32_t -napt_hash_buf_init(struct napt_ct **hash, struct nhlist_head **hash_head) -{ - a_uint32_t hash_size = NAPT_BUFFER_HASH_SIZE; - a_uint32_t buffer_size = NAPT_BUFFER_SIZE; - - *hash = (struct napt_ct *)kmalloc(sizeof(struct napt_ct)*buffer_size, GFP_ATOMIC); - if(!(*hash)) - { - HNAT_PRINTK("NAPT INIT ERROR! No Sufficient Memory!"); - return -1; - } - - *hash_head = (struct nhlist_head *)kmalloc(sizeof(struct nhlist_head)*hash_size, GFP_ATOMIC); - if(!(*hash_head)) - { - HNAT_PRINTK("NAPT INIT ERROR! No Sufficient Memory!"); - kfree(*hash); - return -1; - } - - memset(*hash,0,sizeof(struct napt_ct)*buffer_size); - memset(*hash_head,0,sizeof(struct nhlist_head)*hash_size); - - return 0; -} - -static a_uint32_t -napt_ct_hash(a_uint32_t ct_addr) -{ - if(nf_athrs17_hnat_sync_counter_en == 0) - return (((ct_addr) * (0x9e370001UL)) >> 22); - else - return (((ct_addr) * (0x9e370001UL)) >> 29); -} - -static struct napt_ct * -napt_hash_add(a_uint32_t ct_addr, a_uint32_t *hash_cnt, - struct napt_ct *hash, struct nhlist_head *hash_head) -{ - struct napt_ct *entry = 0,*last = 0,*node = 0; - struct nhlist_head *head = 0; - a_uint32_t hash_index = napt_ct_hash(ct_addr); - a_uint32_t i = 0, j = 0, index = 0xffffffff; - - if(*hash_cnt >= napt_buffer_size) - { - return NULL; - } - head = &(hash_head[hash_index]); - entry = head->next; - - while(entry) - { - if(ct_addr == entry->ct_addr) - { - return entry; - } - else - { - last = entry; - entry = entry->next; - } - } - /*find a valid position*/ - for (i = *hash_cnt; i < napt_buffer_size; i++) { - if (hash[i].ct_addr == 0) - break; - } - if (i >= napt_buffer_size) { - for (j = 0; j < *hash_cnt; j++) { - if (hash[j].ct_addr == 0) - break; - } - if (j >= *hash_cnt) - return NULL; - index = j; - } else { - index = i; - } - - node = &(hash[index]); - node->ct_addr = ct_addr; - node->ct_packets = 0; - node->in_hw = 0; - node->hw_index = 0; - node->deny = 0; - - if(head->next == 0) - { - head->next = node; - } - else - { - last->next = node; - } - (*hash_cnt)++; - - return node; -} - -static struct napt_ct * -napt_hash_find(a_uint32_t ct_addr, a_uint32_t *hash_cnt, - struct napt_ct *hash, struct nhlist_head *hash_head) -{ - struct napt_ct *entry = 0; - struct nhlist_head *head = 0; - a_uint32_t hash_index = napt_ct_hash(ct_addr); - - if(*hash_cnt == 0) - { - return NULL; - } -#if 0 /* prevent empty entries. */ - if(*hash_cnt >= NAPT_BUFFER_SIZE) - { - return NULL; - } -#endif - - head = &(hash_head[hash_index]); - - if(head->next == 0) - { - return NULL; - } - entry = head->next; - do - { - if(ct_addr == entry->ct_addr) - { - return entry; - } - - entry = entry->next; - } - while(entry); - - return NULL; -} - -static a_int32_t -napt_ct_buf_init(void) -{ - return napt_hash_buf_init(&ct_buf, &ct_buf_hash_head); -} - -static void -napt_ct_buf_exit(void) -{ - if(ct_buf_hash_head) - kfree(ct_buf_hash_head); - - if(ct_buf) - kfree(ct_buf); -} - -static void -napt_ct_buf_flush(void) -{ - ct_buf_ct_cnt = 0; - memset(ct_buf,0,sizeof(struct napt_ct)*NAPT_BUFFER_SIZE); - memset(ct_buf_hash_head,0,sizeof(struct nhlist_head)*NAPT_BUFFER_HASH_SIZE); -} - -static a_uint32_t -napt_ct_cnt_get(void) -{ - return ct_buf_ct_cnt; -} - -static struct napt_ct * -napt_ct_buf_ct_find(a_uint32_t ct_addr) -{ - return napt_hash_find(ct_addr, &ct_buf_ct_cnt, - ct_buf, ct_buf_hash_head); -} - -static a_uint64_t -napt_ct_buf_pkts_get(struct napt_ct *napt_ct) -{ - return napt_ct->ct_packets; -} - -static void -napt_ct_buf_pkts_update(struct napt_ct *napt_ct, a_uint64_t packets) -{ - napt_ct->ct_packets = packets; -} - -static a_uint8_t -napt_ct_buf_deny_get(struct napt_ct *napt_ct) -{ - return napt_ct->deny; -} - -static void -napt_ct_buf_deny_set(struct napt_ct *napt_ct, a_uint8_t deny) -{ - napt_ct->deny = deny; -} - -static void -napt_ct_buf_deny_clear(struct napt_ct *napt_ct) -{ - napt_ct->deny = 0; -} - -static a_uint8_t -napt_ct_buf_in_hw_get(struct napt_ct *napt_ct, a_uint16_t *hw_index) -{ - *hw_index = napt_ct->hw_index; - return napt_ct->in_hw; -} - -static void -napt_ct_buf_in_hw_set(struct napt_ct *napt_ct, a_uint16_t hw_index) -{ - napt_ct->in_hw = 1; - napt_ct->hw_index = hw_index; -} - -static void -napt_ct_buf_in_hw_clear(struct napt_ct *napt_ct) -{ - napt_ct->in_hw = 0; - napt_ct->hw_index = 0; -} - -static void -napt_ct_buf_ct_info_clear(struct napt_ct *napt_ct) -{ - a_uint32_t hash_index = napt_ct_hash(napt_ct->ct_addr); - struct nhlist_head *head = 0; - struct napt_ct *entry = 0, *last = 0; - - head = &ct_buf_hash_head[hash_index]; - entry = head->next; - while (entry && entry != napt_ct) { - last = entry; - entry = entry->next; - } - if (last == 0) - head->next = napt_ct->next; - else - last->next = napt_ct->next; - napt_ct->ct_addr = 0; - napt_ct->ct_packets = 0; - napt_ct->deny = 0; - napt_ct->next = NULL; -} - -static struct napt_ct * -napt_ct_buf_ct_add(a_uint32_t ct_addr) -{ - struct napt_ct *napt_ct; - napt_ct = napt_hash_add(ct_addr, &ct_buf_ct_cnt, - ct_buf, ct_buf_hash_head); - - if(napt_ct) - { - /*ct pkts initial*/ - napt_ct_buf_pkts_update(napt_ct, NAPT_CT_PKTS_GET(ct_addr)); - } - - return napt_ct; -} - -#define NAPT_CT_PERMANENT_DENY 5 -static a_uint32_t napt_ct_addr[NAPT_TABLE_SIZE] = {0}; -a_uint32_t napt_cookie[NAPT_TABLE_SIZE*2] = {0}; - -a_uint32_t packet_thres_base = 50; -static a_uint64_t packets_bdir_total = 0; -static a_uint64_t packets_bdir_thres = 0; - -static inline a_int32_t -before(a_uint64_t seq1, a_uint64_t seq2) -{ - return ((int64_t)(seq1-seq2) < 0); -} - -static a_uint8_t -napt_ct_pkts_reach_thres(a_uint32_t ct_addr, struct napt_ct *napt_ct, - a_uint8_t pkts_sum) -{ - a_uint64_t packets_bdir_old = napt_ct_buf_pkts_get(napt_ct); - a_uint64_t packets_bdir_new = NAPT_CT_PKTS_GET(ct_addr); - - if(pkts_sum) - { - if(packets_bdir_new > packets_bdir_old) - { - packets_bdir_total += (packets_bdir_new - packets_bdir_old); - } - } - - napt_ct_buf_pkts_update(napt_ct, packets_bdir_new); - - HNAT_PRINTK("<%s> ct:%x packets_bdir_old:%lld ==> packets_bdir_new:%lld, thresh:%lld\n", - __func__, ct_addr, packets_bdir_old, packets_bdir_new, packets_bdir_thres); - - if(before((packets_bdir_old+packets_bdir_thres), packets_bdir_new)) - { - return 1; - } - - return 0; -} - -a_uint8_t napt_dnat_flow_find_del( - napt_entry_t *napt, - fal_napt_entry_t *entry) -{ - fal_napt_entry_t tmp_entry; - napt_entry_t tmp_napt; - a_int32_t ret; - - memset(&tmp_entry, 0, sizeof(tmp_entry)); - memset(&tmp_napt, 0, sizeof(tmp_napt)); - tmp_napt = *napt; - tmp_napt.src_addr = 0; - ret = napt_hw_get(&tmp_napt, &tmp_entry); - if(!ret) { - napt_hw_del(&tmp_napt); - *entry = tmp_entry; - return 0; - } - return 1; -} - -a_uint8_t napt_snat_flow_find_del( - napt_entry_t *napt, - fal_napt_entry_t *entry) -{ - fal_napt_entry_t tmp_entry; - napt_entry_t tmp_napt; - a_int32_t ret; - - memset(&tmp_entry, 0, sizeof(tmp_entry)); - memset(&tmp_napt, 0, sizeof(tmp_napt)); - tmp_napt = *napt; - tmp_napt.trans_addr = 0; - ret = napt_hw_get(&tmp_napt, &tmp_entry); - if(!ret) { - napt_hw_del(&tmp_napt); - *entry = tmp_entry; - return 0; - } - return 1; -} - - - - -static a_int32_t -napt_ct_hw_add(a_uint32_t ct_addr, a_uint16_t *hw_index) -{ - napt_entry_t napt = {0}; - a_uint32_t index, i, dcookie = 0, scookie = 0; - fal_napt_entry_t entry; - a_uint8_t ret = 0; - sw_error_t rv = SW_OK; - - if (!ct_addr) - return -1; - - NAPT_CT_TO_HW_ENTRY(ct_addr, &napt); - - if(nat_hw_pub_ip_add(napt.trans_addr, &index) == 0) - { - napt.trans_addr = index; - - } - else - { - HNAT_ERR_PRINTK("####%s##nat_hw_pub_ip_add fail!\n", __func__); - return -1; - } - if (((nat_chip_ver & 0xffff)>>8) == NAT_CHIP_VER_DESS) { - ret = napt_dnat_flow_find_del(&napt, &entry); - if(!ret) { - dcookie = entry.flow_cookie; - } - ret = napt_snat_flow_find_del(&napt, &entry); - if(!ret) { - scookie = entry.flow_cookie; - } - } - rv = napt_hw_add(&napt); - - if(rv == 0) - { - HNAT_PRINTK("%s: success entry_id:0x%x ct 0x%x\n", __func__, napt.entry_id, ct_addr); - - if(napt_ct_addr[napt.entry_id]) - { - HNAT_ERR_PRINTK("fault: napt HW:%x can not be overwrited!\n", - napt.entry_id); - - } - else - { - napt_ct_addr[napt.entry_id] = ct_addr; - *hw_index = napt.entry_id; - // Added from 1.0.7 for default route. - napt_set_default_route(napt.dst_addr, napt.src_addr); - if (((nat_chip_ver & 0xffff)>>8) == NAT_CHIP_VER_DESS) { - i = napt.entry_id; - napt_cookie[i*2] = dcookie; - napt_cookie[i*2+1] = scookie; - } - napt_ct_hw_cnt++; - - return 0; - } - } - else - { - HNAT_PRINTK("%s:fail rv:%d entry_id:%x(maybe full)\n", - __func__,rv, napt.entry_id); - nat_hw_pub_ip_del(napt.trans_addr); - } - - return -1; -} - -static a_int32_t -napt_ct_hw_del (napt_entry_t *napt) -{ - if(napt_hw_del(napt)!= 0) - { - HNAT_ERR_PRINTK("%s: isis_napt_del fail\n", __func__); - return -1; - } - napt_ct_hw_cnt--; - if(nat_hw_pub_ip_del(napt->trans_addr) != 0) - { - HNAT_ERR_PRINTK("%s: public_ip_del fail\n", __func__); - //return -1; - } - return 0; -} - -void nat_helper_cookie_del(a_uint32_t hw_index) -{ - struct napt_ct *napt_ct = NULL; - a_uint32_t ct_addr; - ct_addr = napt_ct_addr[hw_index]; - if(ct_addr) { - napt_ct = napt_ct_buf_ct_find(ct_addr); - } - if(napt_ct) - { - napt_ct_buf_in_hw_clear(napt_ct); - - if(napt_ct_buf_deny_get(napt_ct) != NAPT_CT_PERMANENT_DENY) - { - napt_ct_buf_ct_info_clear(napt_ct); - } - NAPT_CT_AGING_ENABLE(napt_ct_addr[hw_index]); - } - napt_ct_addr[hw_index] = 0; - napt_cookie[hw_index*2] = 0; - napt_cookie[hw_index*2+1] = 0; - HNAT_INFO_PRINTK("nat_helper_cookie_del for index 0x%x\n", hw_index); -} - - -static a_int32_t -napt_ct_del(struct napt_ct *napt_ct, napt_entry_t *napt) -{ - a_uint16_t hw_index = napt->entry_id; - - HNAT_PRINTK("%s: 0x%x ct 0x%x\n", __FUNCTION__, hw_index, napt_ct_addr[hw_index]); - - if(napt_ct_hw_del(napt) != 0) - { - return -1; - } - - NAPT_CT_AGING_ENABLE(napt_ct_addr[hw_index]); - napt_ct_addr[hw_index] = 0; - if(napt_cookie[hw_index*2]) { - napt_hw_dnat_cookie_add(napt, napt_cookie[hw_index*2]); - napt_cookie[hw_index*2] = 0; - } - if(napt_cookie[hw_index*2+1]) { - napt_hw_snat_cookie_add(napt, napt_cookie[hw_index*2+1]); - napt_cookie[hw_index*2+1] = 0; - } - - if(napt_ct) - { - napt_ct_buf_in_hw_clear(napt_ct); - - if(napt_ct_buf_deny_get(napt_ct) != NAPT_CT_PERMANENT_DENY) - { - napt_ct_buf_ct_info_clear(napt_ct); - } - } - - return 0; -} - -static a_int32_t -napt_ct_del_by_index (struct napt_ct *napt_ct, a_uint16_t hw_index) -{ - napt_entry_t napt = {0}; - - if(napt_hw_get_by_index(&napt, hw_index) != 0) - { - return -1; - } - - return napt_ct_del(napt_ct, &napt); -} - -static a_int32_t -napt_ct_in_hw_sanity_check(struct napt_ct *napt_ct, a_uint16_t hw_index) -{ - a_uint16_t ct_hw_index = 0; - if(!napt_ct) - { - HNAT_ERR_PRINTK("<%s>hw_index:%d error napt_ct can't find\n", - __func__, hw_index); - return -1; - } - - if(napt_ct_buf_in_hw_get(napt_ct, &ct_hw_index) == 0) - { - HNAT_ERR_PRINTK("<%s>hw_index:%d in_hw:0 error\n", - __func__, hw_index); - return -1; - } - - if(hw_index != ct_hw_index) - { - HNAT_ERR_PRINTK("<%s>hw_index:%d buf_hw_index:%d\n", - __func__, hw_index, ct_hw_index); - return -1; - } - - return 0; -} - -void -napt_ct_hw_aging(void) -{ -#define NAPT_AGEOUT_STATUS 1 - - a_uint32_t ct_addr, cnt= 0; - napt_entry_t napt = {0}; - - - if(napt_hw_first_by_age(&napt, NAPT_AGEOUT_STATUS) != 0) - { - return; - } - - do - { - a_uint16_t hw_index = napt.entry_id; - struct napt_ct *napt_ct = NULL; - ct_addr = napt_ct_addr[hw_index]; - - if(ct_addr) - { - napt_ct = napt_ct_buf_ct_find(ct_addr); - if(napt_ct_in_hw_sanity_check(napt_ct, hw_index) != 0) - { - HNAT_ERR_PRINTK("<%s> napt_ct_in_hw_sanity_check fail\n", __func__); - continue; - } - - if((nf_athrs17_hnat_sync_counter_en == 0) && (napt_ct_pkts_reach_thres(ct_addr, napt_ct, 0))) - { - printk("set PERMANENT deny ct:%x\n", ct_addr); - napt_ct_buf_deny_set(napt_ct, NAPT_CT_PERMANENT_DENY); - } - } - else - { - HNAT_ERR_PRINTK(" error: in_hw but ct = NULL hw_index:%x\n", hw_index); - } - - napt_ct_del(napt_ct, &napt); - HNAT_INFO_PRINTK("ct:%x aged!\n", ct_addr); - cnt++; - if ((cnt % polling_quota) == 0) { - NAPT_CT_TASK_SLEEP(1); - } - - } - while(napt_hw_next_by_age(&napt, NAPT_AGEOUT_STATUS) != -1); - -#if 0 - if(napt_hw_used_count_get() == 0) - { - nat_hw_prv_base_update_enable(); - } -#endif - - return; -} - -static a_uint32_t -napt_ct_counter_sync(a_uint32_t hw_index) -{ - napt_entry_t napt = {0}; - struct nf_conn *ct = NULL; - struct nf_conn_counter *cct = NULL; - a_uint64_t delta_jiffies = 0, now_jiffies; - a_uint32_t ct_addr = napt_ct_addr[hw_index]; - struct napt_ct *napt_ct; - - if((nf_athrs17_hnat_sync_counter_en == 0) || (napt_ct_addr[hw_index] == 0) || (hw_index >= NAPT_TABLE_SIZE)) - return -1; - - ct = (struct nf_conn *)napt_ct_addr[hw_index]; - cct = (struct nf_conn_counter *)nf_conn_acct_find(ct); - napt_ct = napt_ct_buf_ct_find(ct_addr); - if (napt_ct) { - now_jiffies = (a_uint64_t)get_jiffies_64(); - delta_jiffies = now_jiffies - napt_ct->last_jiffies; - napt_ct->last_jiffies = now_jiffies; - } - - if (!test_bit(IPS_FIXED_TIMEOUT_BIT, &ct->status)) { - ct->timeout.expires += delta_jiffies; - } - - if((cct != NULL) && (napt_hw_get_by_index(&napt, hw_index) == 0)) - { - spin_lock_bh(&ct->lock); - if ((ct->status & IPS_NAT_MASK) == IPS_SRC_NAT) { - atomic64_add(napt.egress_packet, &cct[IP_CT_DIR_ORIGINAL].packets); - atomic64_add(napt.egress_byte, &cct[IP_CT_DIR_ORIGINAL].bytes); - atomic64_add(napt.ingress_packet, &cct[IP_CT_DIR_REPLY].packets); - atomic64_add(napt.ingress_byte, &cct[IP_CT_DIR_REPLY].bytes); - } else { - atomic64_add(napt.ingress_packet, &cct[IP_CT_DIR_ORIGINAL].packets); - atomic64_add(napt.ingress_byte, &cct[IP_CT_DIR_ORIGINAL].bytes); - atomic64_add(napt.egress_packet, &cct[IP_CT_DIR_REPLY].packets); - atomic64_add(napt.egress_byte, &cct[IP_CT_DIR_REPLY].bytes); - } - spin_unlock_bh(&ct->lock); - HNAT_PRINTK("original packets:0x%llx bytes:0x%llx\n", - cct[IP_CT_DIR_ORIGINAL].packets, cct[IP_CT_DIR_ORIGINAL].bytes); - HNAT_PRINTK("reply packets:0x%llx bytes:0x%llx\n", - cct[IP_CT_DIR_REPLY].packets, cct[IP_CT_DIR_REPLY].bytes); - } - - return 0; -} - -static a_int32_t -napt_ct_timer_update(a_uint32_t hw_index) -{ - struct nf_conn *ct = NULL; - struct nf_conn_counter *cct = NULL; - a_uint64_t delta_jiffies = 0, now_jiffies; - a_uint32_t ct_addr = napt_ct_addr[hw_index]; - struct napt_ct *napt_ct; - - if((napt_ct_addr[hw_index] == 0) || (hw_index >= NAPT_TABLE_SIZE)) - return -1; - - ct = (struct nf_conn *)napt_ct_addr[hw_index]; - cct = (struct nf_conn_counter *)nf_conn_acct_find(ct); - napt_ct = napt_ct_buf_ct_find(ct_addr); - if (napt_ct) { - now_jiffies = (a_uint64_t)get_jiffies_64(); - delta_jiffies = now_jiffies - napt_ct->last_jiffies; - napt_ct->last_jiffies = now_jiffies; - } - - if (!test_bit(IPS_FIXED_TIMEOUT_BIT, &ct->status)) { - ct->timeout.expires += delta_jiffies; - } - - return 0; -} - -void napt_ct_counter_decrease(void) -{ - ct_buf_ct_cnt--; -} - -#define NAPT_INVALID_CT_NEED_HW_CLEAR(hw_index) \ - ((napt_ct_valid[hw_index] == 0) && \ - (napt_ct_addr[hw_index] != 0)) -static a_uint32_t -napt_ct_hw_sync(a_uint8_t napt_ct_valid[]) -{ - a_uint16_t hw_index; - a_uint32_t napt_ct_offload_cnt = 0; - - for(hw_index = 0; hw_index < NAPT_TABLE_SIZE; hw_index++) - { - #if 0 - napt_ct_counter_sync(hw_index); - #endif - - if(NAPT_INVALID_CT_NEED_HW_CLEAR(hw_index)) - { - - a_uint32_t ct_addr = napt_ct_addr[hw_index]; - struct napt_ct *napt_ct = napt_ct_buf_ct_find(ct_addr); - - HNAT_INFO_PRINTK("should hw clear for %d\n", hw_index); - - if(napt_ct_in_hw_sanity_check(napt_ct, hw_index) != 0) - { - HNAT_ERR_PRINTK("<%s> napt_ct_in_hw_sanity_check fail\n", __func__); - continue; - } - - if(napt_ct_del_by_index(napt_ct, hw_index) == 0) - { - napt_ct_buf_deny_clear(napt_ct); - } - else - { - HNAT_ERR_PRINTK("hw_index:%d napt_hw_del_by_index fail\n", - hw_index); - } - } - - if(napt_ct_valid[hw_index]) - { - napt_ct_offload_cnt++; - } - } - - return napt_ct_offload_cnt; -} - -static void -napt_ct_frag_hw_yield(struct napt_ct *napt_ct, a_uint16_t hw_index) -{ - napt_entry_t napt = {0}; - - /*os and hw are both traffic; hw offload giveup*/ - if(napt_hw_get_by_index(&napt, hw_index) == 0) - { - if(napt.status == 0xe) - { - a_uint8_t deny = napt_ct_buf_deny_get(napt_ct); - napt_ct_buf_deny_set(napt_ct, (++deny)); - - if(deny >= NAPT_CT_PERMANENT_DENY) - { - /*os service only*/ - HNAT_ERR_PRINTK(" hw service deny\n"); - napt_ct_del(napt_ct, &napt); - } - - //printk(" deny:%d\n", deny); - } - } -} - -#define NAPT_CT_IS_REUSED_BY_OS(in_hw, ct_addr) ((in_hw) && \ - NAPT_CT_AGING_IS_ENABLE(ct_addr)) -static a_int32_t -napt_ct_check_add_one(a_uint32_t ct_addr, a_uint8_t *napt_ct_valid) -{ - struct napt_ct *napt_ct = NULL; - a_uint16_t hw_index; - a_uint8_t in_hw; - - if((napt_ct = napt_ct_buf_ct_find(ct_addr)) == NULL) - { - if((napt_ct = napt_ct_buf_ct_add(ct_addr)) == NULL) - { - HNAT_ERR_PRINTK(" error hash full\n"); - return -1; - } - } - - if(napt_ct_buf_deny_get(napt_ct) >= NAPT_CT_PERMANENT_DENY) - { - HNAT_INFO_PRINTK(" ct:%x is PERMANENT deny\n", - ct_addr); - return -1; - - } - else - { - if (napt_ct_pkts_reach_thres(ct_addr, napt_ct, 1)) - { - if(napt_ct_buf_in_hw_get(napt_ct, &hw_index)) - { - //printk(" ct:%x* is exist\n", ct_addr); - if(nf_athrs17_hnat_sync_counter_en == 0) - { - HNAT_ERR_PRINTK(" ct:%x* is exist\n", ct_addr); - napt_ct_frag_hw_yield(napt_ct, hw_index); - } - } - else - { - if(napt_ct_hw_add(ct_addr, &hw_index) == 0) - { - NAPT_CT_AGING_DISABLE(ct_addr); - napt_ct->last_jiffies = get_jiffies_64(); - - napt_ct_buf_in_hw_set(napt_ct, hw_index); -#ifdef NAT_TODO - ct->in_hnat = 1; /* contrack in HNAT now. */ -#endif - } - } - } else { - HNAT_INFO_PRINTK("can not reach thres for napt_ct=%pK\n", napt_ct); - } - - in_hw = napt_ct_buf_in_hw_get(napt_ct, &hw_index); - if(in_hw) - { - if(!NAPT_CT_IS_REUSED_BY_OS(in_hw, ct_addr)) - { - napt_ct_valid[hw_index] = 1; - } - } - } - - return 0; -} - -static void -napt_ct_pkts_thres_calc_init(void) -{ - packets_bdir_total = 0; - packets_bdir_thres = packet_thres_base; - -} - -a_uint64_t -uint64_div_uint32(a_uint64_t div, a_uint32_t base) -{ - register a_uint32_t i; - a_uint64_t result; - - union - { - a_uint64_t n64[2]; - struct - { - a_uint32_t l0;// 0 - a_uint32_t h0;// 1 - a_uint32_t l1;// 2 - a_uint32_t h1;// 3 - } n32; - } n; - - if(base == 0) - { - return 0; - } - - if(div < base) - { - return 0; - } - - n.n64[0] = div; - n.n64[1] = 0; - result = 0; - i = 0; - - //if div is 32bits, set start from 32 - if(n.n32.h0 == 0) - { - n.n32.h0 = n.n32.l0; - n.n32.l0 = 0; - i = 32; - } - - //left shift until highest bit - for(; i<64; ++i) - { - if((n.n32.h0 & 0x80000000) == 0x80000000) - { - break; - } - else - { - n.n64[0] = n.n64[0] << 1; - } - } - - for (; i<64; ++i) - { - n.n64[1] = (n.n64[1] << 1) + (n.n64[0] >> 63); - n.n64[0] = (n.n64[0] << 1); - result = result << 1 ; - - if(n.n64[1] >= base) - { - n.n64[1] = n.n64[1]- base; - ++result; - } - } - - return result; -} - -static void -napt_ct_pkts_thres_calc(a_uint32_t cnt, a_uint32_t napt_ct_offload_cnt) -{ - a_uint64_t packets_bdir_avg = 0; - a_uint64_t packets_bdir_thres_temp = 0; - - /*ct_avg_pkts* (1+ (ct_offload_cnt/ct_hw_max) )*/ - packets_bdir_avg = uint64_div_uint32(packets_bdir_total, cnt); - packets_bdir_thres_temp = packets_bdir_avg + - uint64_div_uint32((packets_bdir_avg *(a_uint64_t)napt_ct_offload_cnt), - NAPT_TABLE_SIZE); - - if(packets_bdir_thres_temp > packet_thres_base) - { - packets_bdir_thres = packets_bdir_thres_temp; - } - - //HNAT_ERR_PRINTK("###<%s> total:%lld cnt:%d avg:%lld threshold:%lld###\n", __func__, - // packets_bdir_total, cnt, packets_bdir_avg, packets_bdir_thres); - HNAT_INFO_PRINTK("calc pkts avg:%lld offload_cnt:%d threshold:%lld\n", - packets_bdir_avg, napt_ct_offload_cnt, packets_bdir_thres); -} - -#define NAPT_CT_SHOULD_CARE(ct) ((ct) && \ - NAPT_CT_TYPE_IS_NAT(ct) && \ - !NAPT_CT_TYPE_IS_NAT_ALG(ct) && \ - NAPT_CT_INTF_EXPECTED(ct) && \ - NAPT_CT_STATUS_IS_ESTAB(ct) &&\ - nat_hw_prv_base_is_match( \ - NAPT_CT_PRIV_IP_GET(ct))) -a_uint8_t napt_ct_valid_tbl[NAPT_TABLE_SIZE] = {0}; -static a_int32_t -napt_ct_check_add(void) -{ - a_uint32_t ct_addr = 0; - a_uint32_t ct_buf_valid_cnt = 0, care_cnt = 0, ct_cnt = 0; - static a_uint32_t hash = 0; - a_uint32_t iterate = 0; - a_uint32_t napt_ct_offload_cnt = 0; - a_uint16_t hw_index; - - napt_ct_pkts_thres_calc_init(); - - NAPT_CT_LIST_LOCK(); - while((ct_addr = NAPT_CT_LIST_ITERATE(&hash, &iterate))) - { - ct_cnt++; - if (NAPT_CT_SHOULD_CARE(ct_addr)) - { - if(napt_ct_check_add_one(ct_addr, napt_ct_valid_tbl) != -1) - { - ct_buf_valid_cnt++; - } - care_cnt++; - if (care_cnt >= polling_quota) { - break; - } - } - } - - NAPT_CT_LIST_UNLOCK(); - HNAT_INFO_PRINTK("ct_cnt=0x%x, care_cnt=0x%x\n", ct_cnt, care_cnt); - - - if (!ct_addr) { - napt_ct_offload_cnt = napt_ct_hw_sync(napt_ct_valid_tbl); - napt_ct_pkts_thres_calc(ct_buf_valid_cnt, napt_ct_offload_cnt); - memset(napt_ct_valid_tbl, 0, NAPT_TABLE_SIZE); - } - - for(hw_index = 0; hw_index < NAPT_TABLE_SIZE; hw_index++) { - if (nf_athrs17_hnat_sync_counter_en) - napt_ct_counter_sync(hw_index); - else - napt_ct_timer_update(hw_index); - } - - return ct_buf_valid_cnt; -} - -static a_int32_t -napt_ct_add(a_uint32_t ct_addr, a_uint8_t *napt_ct_valid) -{ - struct napt_ct *napt_ct; - - if((napt_ct = napt_ct_buf_ct_add(ct_addr)) == NULL) - { - HNAT_ERR_PRINTK(" error hash full\n"); - return -1; - } - - return 0; -} - -static a_int32_t -napt_ct_buffer_ct_status_update(void) -{ - a_uint32_t ct_addr = 0; - a_uint32_t hash = 0; - a_uint32_t iterate = 0; - - NAPT_CT_LIST_LOCK(); - - while((ct_addr = NAPT_CT_LIST_ITERATE(&hash, &iterate))) - { - if (NAPT_CT_SHOULD_CARE(ct_addr)) - { - napt_ct_add(ct_addr, NULL); - } - } - - NAPT_CT_LIST_UNLOCK(); - - return 0; -} - -static void -napt_ct_buffer_hw_status_update(void) -{ - a_uint16_t hw_index; - - for(hw_index = 0; hw_index < NAPT_TABLE_SIZE; hw_index++) - { - a_uint32_t ct_addr = napt_ct_addr[hw_index]; - if(ct_addr) - { - struct napt_ct *napt_ct = napt_ct_buf_ct_find(ct_addr); - if(napt_ct) - { - napt_ct_buf_in_hw_set(napt_ct, hw_index); - - } - else - { - if(napt_ct_del_by_index(napt_ct, hw_index) != 0) - { - HNAT_ERR_PRINTK("<%s>hw_index:%d napt_ct_del_by_index fail\n", - __func__, hw_index); - } - } - } - } - - return; -} - -static void -napt_ct_buffer_refresh(void) -{ - HNAT_INFO_PRINTK("napt_ct_buffer_refresh\n"); - - napt_ct_buf_flush(); - - napt_ct_buffer_ct_status_update(); - napt_ct_buffer_hw_status_update(); -} - -static void -napt_ct_buffer_refresh_check(a_uint32_t ct_buf_valid_cnt) -{ -#define NAPT_CT_BUF_REFRESH_THRES 1000 - HNAT_INFO_PRINTK("ct_buffer_hash_cnt:%d cnt:%d max:%d\n", - napt_ct_cnt_get(), ct_buf_valid_cnt/2, NAPT_CT_BUF_REFRESH_THRES); - - if((napt_ct_cnt_get() - ct_buf_valid_cnt/2) > NAPT_CT_BUF_REFRESH_THRES) - { - napt_ct_buffer_refresh(); - } -} - -static void -napt_ct_hw_exit(void) -{ - a_uint8_t napt_ct_valid[NAPT_TABLE_SIZE]; - - /*set all ct invalid to cleanup*/ - memset(napt_ct_valid, 0, sizeof(napt_ct_valid)); - - napt_ct_hw_sync(napt_ct_valid); -} - -void -napt_ct_scan(void) -{ - a_uint32_t ct_buf_valid_cnt = 0; - - ct_buf_valid_cnt = napt_ct_check_add(); - - napt_ct_buffer_refresh_check(ct_buf_valid_cnt); -} - -void napt_wan_switch_prehandle(void) -{ - if (wan_switch) { - napt_thread_pending = 1; - napt_l3_status_set(0, A_FALSE); - napt_ct_hw_exit(); - napt_hw_flush(); - qcaswitch_hostentry_flush(); - droute_del_acl_rules(); - ipv6_droute_del_acl_rules(); - if (nf_athrs17_hnat_wan_type == NF_S17_WAN_TYPE_PPPOE) - pppoe_del_acl_rules(); - #ifdef MULTIROUTE_WR - ip_conflict_del_acl_rules(); - #endif - if_mac_cleanup(); - napt_l3_status_set(0, A_TRUE); - napt_thread_pending = 0; - } -} - -static a_int32_t -napt_ct_init(void) -{ - if(nf_athrs17_hnat_sync_counter_en == 0) - { - napt_buffer_hash_size = NAPT_TABLE_SIZE; - napt_buffer_size = NAPT_TABLE_SIZE*8; - } - else - { - napt_buffer_hash_size = 8; - napt_buffer_size = napt_buffer_hash_size; - } - - napt_hw_mode_init(); - - if(napt_ct_buf_init() != 0) - { - HNAT_ERR_PRINTK("*****napt_ct_buf_init fail*******\n"); - return -1; - } - - return 0; -} - -static a_int32_t -napt_ct_exit(void) -{ - napt_hw_mode_cleanup(); - - napt_ct_hw_exit(); - napt_ct_buf_exit(); - - return 0; -} - -static a_int32_t -napt_ct_scan_thread(void *param) -{ -#define NAPT_CT_AGING_SEC 20 -#define ARP_CHECK_AGING_SEC 40 - - a_uint32_t times = (NAPT_CT_AGING_SEC/scan_period); - a_uint32_t arp_check_time = (ARP_CHECK_AGING_SEC/scan_period); - // a_bool_t l3_enable; - - if(napt_ct_init() != 0) - { - return 0; - } - - while(1) - { - if(!nat_sockopts_init) { - nat_ipt_sockopts_replace(); - } - if (napt_thread_pending) { - NAPT_CT_TASK_SLEEP(scan_period); - continue; - } - - if (scan_enable) { - if((--times) == 0) - { - HNAT_PRINTK("[ct hw aging start]\n"); - napt_ct_hw_aging(); - HNAT_PRINTK("[ct hw aging end]\n"); - times = (NAPT_CT_AGING_SEC/scan_period); - } - - if((--arp_check_time) == 0) - { - host_check_aging(); - arp_check_time = (ARP_CHECK_AGING_SEC/scan_period); - } - - if (times != NAPT_CT_AGING_SEC/scan_period) { - HNAT_PRINTK("[ct scan start]\n"); - napt_ct_scan(); - HNAT_PRINTK("[ct scan end]\n"); - } - } else { - if (napt_need_clean) { - napt_need_clean = 0; - napt_ct_hw_exit(); - } - } - -#ifdef ISISC /* only for S17c */ -#ifdef CONFIG_IPV6_HWACCEL - napt_set_ipv6_default_route(); -#endif -#endif - - if (NAPT_CT_TASK_SHOULD_STOP()) { - printk("should stop!\n"); - break; - } - - NAPT_CT_TASK_SLEEP(scan_period); - } - - napt_ct_exit(); - - return 0; -} - -void napt_helper_show(void) -{ - a_uint16_t hw_index; - for(hw_index = 0; hw_index < NAPT_TABLE_SIZE; hw_index++) { - if (napt_ct_addr[hw_index]) { - printk("index[%d] exist: 0x%x\n", hw_index, napt_ct_addr[hw_index]); - } - } - printk("current hardware offload count: 0x%x\n", napt_ct_hw_cnt); - printk("interate:0x%x, care:0x%x, low_thresh=0x%x\n", - napt_ct_debug_info.interate_cnt, - napt_ct_debug_info.care_cnt, - napt_ct_debug_info.thresh_low_cnt); -} - -void -napt_helper_init(void) -{ - const char napt_thread_name[] = "napt_ct_scan"; - - NAPT_CT_TASK_START(napt_ct_scan_thread, napt_thread_name); -} - - -void -napt_helper_exit(void) -{ - NAPT_CT_TASK_STOP(); -} - diff --git a/feeds/ipq807x/qca-ssdk/src/app/nathelper/linux/lib/nat_helper_dt.h b/feeds/ipq807x/qca-ssdk/src/app/nathelper/linux/lib/nat_helper_dt.h deleted file mode 100755 index bd3550b9c..000000000 --- a/feeds/ipq807x/qca-ssdk/src/app/nathelper/linux/lib/nat_helper_dt.h +++ /dev/null @@ -1,22 +0,0 @@ -/* - * Copyright (c) 2012, The Linux Foundation. All rights reserved. - * Permission to use, copy, modify, and/or distribute this software for - * any purpose with or without fee is hereby granted, provided that the - * above copyright notice and this permission notice appear in all copies. - * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES - * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR - * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES - * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN - * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT - * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. - */ - - -#ifndef _NAT_HELPER_DT_H -#define _NAT_HELPER_DT_H - -extern void host_check_aging(void); -void napt_ct_counter_decrease(void); - -#endif /*_NAT_HELPER_DT_H*/ diff --git a/feeds/ipq807x/qca-ssdk/src/app/nathelper/linux/lib/nat_helper_hsl.c b/feeds/ipq807x/qca-ssdk/src/app/nathelper/linux/lib/nat_helper_hsl.c deleted file mode 100755 index ba7bad121..000000000 --- a/feeds/ipq807x/qca-ssdk/src/app/nathelper/linux/lib/nat_helper_hsl.c +++ /dev/null @@ -1,879 +0,0 @@ -/* - * Copyright (c) 2012, 2015, 2018, The Linux Foundation. All rights reserved. - * Permission to use, copy, modify, and/or distribute this software for - * any purpose with or without fee is hereby granted, provided that the - * above copyright notice and this permission notice appear in all copies. - * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES - * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR - * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES - * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN - * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT - * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. - */ - - -#ifdef KVER32 -#include -#include -#else -#include -#endif -#include -#include -#include -#include -#include - -#include "fal_nat.h" -#include "fal_ip.h" - -#include "hsl_api.h" -#include "hsl.h" -#include "hsl_shared_api.h" -#include "../nat_helper.h" -#include "nat_helper_dt.h" -#include "nat_helper_hsl.h" -#include "../napt_acl.h" - -int nat_chip_ver = 0; -a_bool_t napt_add_bypass_check = A_TRUE; - -/* support 4 different interfaces (or 4 VLANs) */ -static fal_intf_mac_entry_t global_if_mac_entry[MAX_INTF_NUM] = {{0}}; -static a_uint8_t if_mac_count = 0; - -extern int setup_wan_if; -extern int setup_lan_if; - -#define DESS_CHIP(ver) ((((ver)&0xffff)>>8) == NAT_CHIP_VER_DESS) - -#define ARP_HW_COUNTER_OFFSET 8 - -static a_uint8_t -nat_hw_debug_counter_get(void) -{ - static a_uint32_t nat_debug_counter = 0; - - return ((nat_debug_counter++) & 0x7); -} - -static a_uint8_t -arp_hw_debug_counter_get(void) -{ - static a_uint32_t ip_debug_counter = 0; - - return ((ip_debug_counter++) & 0x7) + ARP_HW_COUNTER_OFFSET; -} - - -a_int32_t -nat_hw_add(nat_entry_t *nat) -{ - fal_nat_entry_t hw_nat = {0}; - - hw_nat.flags = nat->flags; - hw_nat.src_addr = nat->src_addr; - hw_nat.trans_addr = nat->trans_addr; - hw_nat.port_num = nat->port_num; - hw_nat.port_range = nat->port_range; - hw_nat.counter_en = 1; - hw_nat.counter_id = nat_hw_debug_counter_get(); - - if(NAT_ADD(0, &hw_nat) != 0) - { - return -1; - } - nat->entry_id = hw_nat.entry_id; - - return 0; -} - -a_int32_t -nat_hw_del_by_index(a_uint32_t index) -{ - fal_nat_entry_t nat_entry = {0}; - - HNAT_PRINTK("NAT_DEL(1) index=%d########\n", index); - - nat_entry.entry_id = index; - if(NAT_DEL(0, FAL_NAT_ENTRY_ID_EN, &nat_entry)!= 0) - { - return -1; - } - - return 0; -} - -a_int32_t -nat_hw_flush(void) -{ - if(NAT_DEL(0, 0, 0)!= 0) - { - return -1; - } - - return 0; -} - -a_int32_t -napt_hw_flush(void) -{ - if(NAPT_DEL(0, 0, 0)!= 0) - { - return -1; - } - - return 0; -} - -static a_uint32_t private_ip_can_update = 1; -a_int32_t -nat_hw_prv_base_can_update(void) -{ - return private_ip_can_update; -} - -void -nat_hw_prv_base_update_enable(void) -{ - private_ip_can_update = 1; -} - -void -nat_hw_prv_base_update_disable(void) -{ - private_ip_can_update = 0; -} - -static a_uint32_t private_ip_base = 0xc0a80000; -static a_uint32_t private_net_mask = 0xffffff00; -a_int32_t -nat_hw_prv_base_set(a_uint32_t ip) -{ -#define PRIVATE_IP_MASK 0xffffff00 - - ip = ntohl(ip); - - if (((nat_chip_ver & 0xffff) >> 8) == NAT_CHIP_VER_8327) - private_ip_base = ip & PRIVATE_IP_MASK; - else - private_ip_base = ip & nat_hw_prv_mask_get(); - - - if(DESS_CHIP(nat_chip_ver)) { - if (IP_PRV_BASE_ADDR_SET(0, 0, (fal_ip4_addr_t)ip) != 0) - { - return -1; - } - } else { - if (NAT_PRV_BASE_ADDR_SET(0, (fal_ip4_addr_t)ip) != 0) - { - return -1; - } - } - - HNAT_PRINTK("%s: private_ip_base:%x private_ip_can_update:%d\n", - __func__, private_ip_base, private_ip_can_update); - - return 0; -} - -a_uint32_t -nat_hw_prv_base_get(void) -{ - return private_ip_base; -} - - -a_int32_t -nat_hw_prv_mask_set(a_uint32_t ipmask) -{ - ipmask = ntohl(ipmask); - - if(DESS_CHIP(nat_chip_ver)) { - if (IP_PRV_BASE_MASK_SET(0, 0, (fal_ip4_addr_t)ipmask) != 0) - { - return -1; - } - } else if (((nat_chip_ver & 0xffff)>>8) == NAT_CHIP_VER_8337) { - if (NAT_PRV_BASE_MASK_SET(0, (fal_ip4_addr_t)ipmask) != 0) - { - return -1; - } - } - private_net_mask = ipmask; - - HNAT_PRINTK("%s: 0x%08x\n", __FUNCTION__, private_net_mask); - - return 0; -} - -a_uint32_t -nat_hw_prv_mask_get(void) -{ - return private_net_mask; -} - - -a_int32_t -nat_hw_prv_base_is_match(a_uint32_t ip) -{ -#define PRIVATE_IP_MASK 0xffffff00 - - a_uint32_t prv_base = private_ip_base; - a_uint32_t prv_mask; - - if (((nat_chip_ver & 0xffff)>>8) == NAT_CHIP_VER_8327) { - if((prv_base & PRIVATE_IP_MASK) == (ip & PRIVATE_IP_MASK)) - return 1; - } else { - prv_mask = nat_hw_prv_mask_get(); - if((prv_base & prv_mask) == (ip & prv_mask)) - return 1; - } - - HNAT_PRINTK("%s: private_ip_base:%x usaddr:%x mismatch\n", - __func__, prv_base, ip); - - return 0; -} - -static a_int32_t -_arp_hw_if_mac_add(fal_intf_mac_entry_t *if_mac_entry) -{ - return IP_INTF_ENTRY_ADD(0, if_mac_entry); -} - -static a_int32_t -_arp_hw_if_mac_del(fal_intf_mac_entry_t *if_mac_entry) -{ - return IP_INTF_ENTRY_DEL(0, FAL_IP_ENTRY_ID_EN, if_mac_entry); -} - -a_int32_t -if_mac_cleanup(void) -{ - a_uint8_t i = 0; - - if_mac_count = 0; - for(i = 0; i < MAX_INTF_NUM; i++) - { - if(_arp_hw_if_mac_del(&global_if_mac_entry[i]) != 0) { - printk("mac del fail!\n"); - return -1; - } - memset(&global_if_mac_entry[i], 0, sizeof(fal_intf_mac_entry_t)); - } - - setup_wan_if = 0; - setup_lan_if = 0; - - return 0; -} - -#define MACADDR_LEN 6 -a_int32_t -if_mac_add(a_uint8_t *mac, a_uint32_t vid, uint32_t ipv6) -{ - a_uint8_t i = 0; - a_uint8_t zero_mac[MACADDR_LEN] = {0}; - - if (!memcmp(mac, zero_mac, MACADDR_LEN)) - return 0; - - if(if_mac_count > MAX_INTF_NUM) - return -1; - - for(i = 0; i < if_mac_count; i++) - { - if((!memcmp(global_if_mac_entry[i].mac_addr.uc, mac, 6)) && - (global_if_mac_entry[i].vid_low == vid)) - { - HNAT_PRINTK("%s: mac exist id:%d\n", __func__, - global_if_mac_entry[i].entry_id); - return 0; - } - } - - if(if_mac_count == MAX_INTF_NUM) - { - HNAT_ERR_PRINTK("%s: reach mac count max\n", __func__); - return -1; - } - - memset(&global_if_mac_entry[if_mac_count], 0, sizeof(fal_intf_mac_entry_t)); - memcpy(global_if_mac_entry[if_mac_count].mac_addr.uc, mac, 6); - - global_if_mac_entry[if_mac_count].entry_id = if_mac_count; - if (1 == ipv6) - { - global_if_mac_entry[if_mac_count].ip6_route = 1; - } - else - { - global_if_mac_entry[if_mac_count].ip6_route = 0; - } - global_if_mac_entry[if_mac_count].ip4_route = 1; - - if (vid == 0) - { - global_if_mac_entry[if_mac_count].vid_low = 0; - global_if_mac_entry[if_mac_count].vid_high = 511; - } - else - { - global_if_mac_entry[if_mac_count].vid_low = vid; - global_if_mac_entry[if_mac_count].vid_high = vid; - } - - if(_arp_hw_if_mac_add(&global_if_mac_entry[if_mac_count])!= 0) - { - return -1; - } - - HNAT_PRINTK("%s: count:%d index:%d vid:%d mac:%02x-%02x-%02x-%02x-%02x-%02x\n", - __func__, if_mac_count, global_if_mac_entry[if_mac_count].entry_id, vid, - mac[0],mac[1],mac[2],mac[3],mac[4],mac[5]); - if_mac_count ++; - - return 0; -} - -static a_int32_t -_arp_hw_add(fal_host_entry_t *arp_entry) -{ - return IP_HOST_ADD(0, arp_entry); -} - -a_int32_t -arp_hw_add(a_uint32_t port, a_uint32_t intf_id, a_uint8_t *ip, a_uint8_t *mac, int is_ipv6_entry) -{ - fal_host_entry_t arp_entry; - - -#ifdef ISIS /* Only for AR8337(S17) */ - if (NF_S17_WAN_TYPE_PPPOEV6 == nf_athrs17_hnat_wan_type) - { - memset(&arp_entry,0,sizeof(arp_entry)); - memcpy(&arp_entry.ip4_addr, ip, 4); - memcpy(arp_entry.mac_addr.uc, mac, 6); - arp_entry.status = ARP_AGE_NEVER; - if (port == S17_WAN_PORT) - { - arp_entry.port_id = port; - } - else - { - arp_entry.port_id = 6; /* always assigned to MAC 6 */ - } - arp_entry.flags = FAL_IP_IP4_ADDR; - } - else -#endif /* not ISIS */ - { - memset(&arp_entry,0,sizeof(arp_entry)); - if (0 == is_ipv6_entry) - { - memcpy(&arp_entry.ip4_addr, ip, 4); - arp_entry.ip4_addr = ntohl(arp_entry.ip4_addr); - arp_entry.flags = FAL_IP_IP4_ADDR; - } - else - { - memcpy(&arp_entry.ip6_addr, ip, 16); - arp_entry.flags = FAL_IP_IP6_ADDR; - } - memcpy(arp_entry.mac_addr.uc, mac, 6); - if ((NF_S17_WAN_TYPE_PPPOE == nf_athrs17_hnat_wan_type) && \ - (S17_WAN_PORT == port)) - { - arp_entry.status = ARP_AGE_NEVER; - } - else - { - arp_entry.status = ARP_AGE; - } - arp_entry.port_id = port; - } - - arp_entry.intf_id = intf_id; - - arp_entry.counter_en = 1; - if (S17_WAN_PORT == port) - { - arp_entry.counter_id = 0xf; - } - else - { - arp_entry.counter_id = arp_hw_debug_counter_get(); - } - - if (IP_HOST_GET(0, 0x10, &arp_entry)) { - HNAT_PRINTK("new arp for 0x%x\n", arp_entry.ip4_addr); - if(_arp_hw_add(&arp_entry) != 0) - { - HNAT_ERR_PRINTK("%s: fail\n", __func__); - return -1; - } - } - - if (0 == is_ipv6_entry) - { - HNAT_PRINTK("%s: index:%x port:%d ip:%d.%d.%d.%d\n", - __func__, arp_entry.entry_id, port, - *(ip), *(ip+1), *(ip+2), *(ip+3)); - } - - if (0 != (arp_entry.entry_id & 0xFFFFFC00)) - { - printk("Warning: arp_entry id should be only 10 bits!\n"); - } - - return arp_entry.entry_id; -} - -#define AOS_HEADER_MAGIC 0xC0DE - -a_int32_t -arp_if_info_get(void *data, a_uint32_t *sport, a_uint32_t *vid) -{ - aos_header_t *athr_header = NULL; - if((data==0) || (sport==0) || (vid==0)) - { - return -1; - } - - athr_header = (aos_header_t *)data; - -#if 0 - /*atheros header magic check*/ - if(athr_header->magic != AOS_HEADER_MAGIC) - { - return -1; - } -#endif - - *sport = athr_header->sport; - *vid = athr_header->vid; - - return 0; -} - -#define MAX_PUBLIC_IP_CNT 16 -struct public_ip_shadow -{ - a_uint32_t ip; - a_uint32_t use_cnt; -}; - -static struct public_ip_shadow public_ip_shadow[MAX_PUBLIC_IP_CNT]= {{0}}; -static a_uint32_t public_ip_cnt = 0; - -a_int32_t -nat_hw_pub_ip_add(a_uint32_t ip, a_uint32_t *index) -{ - sw_error_t rv; - a_uint32_t hw_index; - a_uint32_t i; - fal_nat_pub_addr_t ip_entry; - - for(i=0; i= MAX_PUBLIC_IP_CNT) - { - return -1; - } - - memset(&ip_entry, 0, sizeof(ip_entry)); - ip_entry.pub_addr = ip; - rv = NAT_PUB_ADDR_ADD(0,&ip_entry); - if(rv != 0) - { - return -1; - } - - public_ip_cnt++; - hw_index = ip_entry.entry_id; - public_ip_shadow[hw_index].ip = ip; - public_ip_shadow[hw_index].use_cnt++; - *index = hw_index; - - HNAT_PRINTK("%s: public_ip_cnt:%d index:%d ip:0x%x\n", - __func__, public_ip_cnt, hw_index, public_ip_shadow[hw_index].ip); - return 0; -} - - -void -napt_hw_mode_init(void) -{ - sw_error_t rv; - /* age_speedup+age_thres_1/4+age_step_4+age_timer_28s*1+ - stop_age_when1+overwrite_disable */ - /* Also set NAT mode Port strict mode/symmetric mode */ - a_uint32_t entry = 0x15F01CB; - - HSL_REG_ENTRY_SET(rv, 0, NAT_CTRL, 0, (a_uint8_t *) (&entry), - sizeof (a_uint32_t)); - - HSL_REG_ENTRY_GET(rv, 0, ROUTER_CTRL, 0, - (a_uint8_t *) (&entry), sizeof (a_uint32_t)); - - /*set locktime 100us*/ - SW_SET_REG_BY_FIELD(ROUTER_CTRL, GLB_LOCKTIME, 1, entry); - SW_SET_REG_BY_FIELD(ROUTER_CTRL, ARP_AGE_MODE, 1, entry); - - HSL_REG_ENTRY_SET(rv, 0, ROUTER_CTRL, 0, - (a_uint8_t *) (&entry), sizeof (a_uint32_t)); - HSL_REG_ENTRY_GET(rv, 0, MOD_ENABLE, 0, - (a_uint8_t *) (&entry), sizeof (a_uint32_t)); - SW_SET_REG_BY_FIELD(MOD_ENABLE, L3_EN, 1, entry); - HSL_REG_ENTRY_SET(rv, 0, MOD_ENABLE, 0, - (a_uint8_t *) (&entry), sizeof (a_uint32_t)); - - ACL_STATUS_SET(0, A_TRUE); -} - -void -napt_hw_mode_cleanup(void) -{ - a_uint32_t entry; - sw_error_t rv; - if (!DESS_CHIP(nat_chip_ver)) { - IP_ROUTE_STATUS_SET(0, A_FALSE); - entry = 0; - } else { - HSL_REG_ENTRY_GET(rv, 0, NAT_CTRL, 0, - (a_uint8_t *) (&entry), sizeof (a_uint32_t)); - SW_SET_REG_BY_FIELD(NAT_CTRL, NAT_EN, 0, entry); - } - HSL_REG_ENTRY_SET(rv, 0, NAT_CTRL, 0, - (a_uint8_t *) (&entry), sizeof (a_uint32_t)); - ACL_STATUS_SET(0, A_FALSE); -} - -a_int32_t -nat_hw_pub_ip_del(a_uint32_t index) -{ - sw_error_t rv; - - if(public_ip_shadow[index].use_cnt>0) - { - public_ip_shadow[index].use_cnt--; - if(public_ip_shadow[index].use_cnt == 0) - { - fal_nat_pub_addr_t ip_entry; - HNAT_PRINTK("%s: public_ip_cnt:%d index:%d ip:0x%x\n", - __func__, public_ip_cnt, index, public_ip_shadow[index].ip); - memset(&ip_entry,0,sizeof(ip_entry)); - ip_entry.pub_addr = public_ip_shadow[index].ip; - rv = NAT_PUB_ADDR_DEL(0, 1, &ip_entry); - if(rv != 0) - { - return -1; - } - - public_ip_cnt--; - } - return 0; - } - - return -1; -} - -#define napt_entry_cp(to, from) \ -{ \ - (to)->entry_id = (from)->entry_id; \ - (to)->status = (from)->status; \ - (to)->flags = (from)->flags; \ - (to)->src_addr = (from)->src_addr; \ - (to)->src_port = (from)->src_port; \ - (to)->dst_addr = (from)->dst_addr; \ - (to)->dst_port = (from)->dst_port; \ - (to)->trans_addr = (from)->trans_addr; \ - (to)->trans_port = (from)->trans_port; \ - (to)->ingress_packet = (from)->ingress_packet; \ - (to)->ingress_byte = (from)->ingress_byte; \ - (to)->egress_packet = (from)->egress_packet; \ - (to)->egress_byte = (from)->egress_byte; \ -} - -a_int32_t -napt_hw_add(napt_entry_t *napt) -{ - a_int32_t ret = 0; - fal_napt_entry_t fal_napt = {0}; - fal_host_entry_t host_entry = {0}; - a_uint32_t next_hop = 0; - - napt_entry_cp(&fal_napt, napt); - - fal_napt.flags |= FAL_NAT_ENTRY_TRANS_IPADDR_INDEX; - fal_napt.counter_en = 1; - fal_napt.counter_id = nat_hw_debug_counter_get(); - fal_napt.action = FAL_MAC_FRWRD; - - if (!napt_add_bypass_check) { - /*check arp entry*/ - host_entry.flags = FAL_IP_IP4_ADDR; - host_entry.ip4_addr = fal_napt.src_addr; - ret = IP_HOST_GET(0, FAL_IP_ENTRY_IPADDR_EN, &host_entry); - if (ret) { - HNAT_ERR_PRINTK("can not find src host entry!\n"); - return ret; - } - if (nf_athrs17_hnat_wan_type != NF_S17_WAN_TYPE_PPPOE) { - next_hop = get_next_hop(fal_napt.dst_addr, fal_napt.src_addr); - host_entry.ip4_addr = next_hop ? next_hop : fal_napt.dst_addr; - ret = IP_HOST_GET(0, FAL_IP_ENTRY_IPADDR_EN, &host_entry); - if (ret) { - HNAT_ERR_PRINTK("can not find dst host entry!\n"); - return ret; - } - } - } - - ret = NAPT_ADD(0, &fal_napt); - - napt->entry_id = fal_napt.entry_id; - return ret; -} - -a_int32_t -napt_hw_get(napt_entry_t *napt, fal_napt_entry_t *entry) -{ - a_int32_t ret = 0; - fal_napt_entry_t fal_napt = {0}; - - napt_entry_cp(&fal_napt, napt); - - ret = NAPT_GET(0, 0, &fal_napt); - - if(!ret) - *entry = fal_napt; - return ret; -} - -a_int32_t -napt_hw_dnat_cookie_add(napt_entry_t *napt, a_uint32_t cookie) -{ - a_int32_t ret = 0; - fal_napt_entry_t fal_napt = {0}; - fal_napt.flags = napt->flags | 0x10; - fal_napt.status = 0xf; - fal_napt.dst_addr = napt->dst_addr; - fal_napt.dst_port = napt->dst_port; - fal_napt.trans_addr = napt->trans_addr; - fal_napt.trans_port = napt->trans_port; - fal_napt.src_port = napt->src_port; - fal_napt.action = FAL_MAC_RDT_TO_CPU; - fal_napt.flow_cookie = cookie; - ret = NAPT_ADD(0, &fal_napt); - return ret; -} - -a_int32_t -napt_hw_snat_cookie_add(napt_entry_t *napt, a_uint32_t cookie) -{ - a_int32_t ret = 0; - fal_napt_entry_t fal_napt = {0}; - fal_napt.flags = napt->flags | 0x10; - fal_napt.status = 0xf; - fal_napt.dst_addr = napt->dst_addr; - fal_napt.dst_port = napt->dst_port; - fal_napt.src_addr = napt->src_addr; - fal_napt.src_port = napt->src_port; - fal_napt.trans_port = napt->trans_port; - fal_napt.action = FAL_MAC_RDT_TO_CPU; - fal_napt.flow_cookie = cookie; - ret = NAPT_ADD(0, &fal_napt); - return ret; -} - - - - -a_int32_t -napt_hw_del(napt_entry_t *napt) -{ - a_int32_t ret = 0; - - fal_napt_entry_t fal_napt = {0}; - - napt_entry_cp(&fal_napt, napt); - napt_ct_counter_decrease(); - - ret = NAPT_DEL(0, FAL_NAT_ENTRY_KEY_EN, &fal_napt); - - if(ret != 0) - { - return -1; - } - else - { - return 0; - } -} - -a_int32_t -napt_hw_first_by_age(napt_entry_t *napt, a_uint32_t age) -{ - a_int32_t ret = 0; - fal_napt_entry_t fal_napt = {0}; - - fal_napt.entry_id = FAL_NEXT_ENTRY_FIRST_ID; - fal_napt.status = age; - - if(NAPT_NEXT(0, FAL_NAT_ENTRY_AGE_EN ,&fal_napt) !=0) - { - ret = -1; - } - - napt_entry_cp(napt, &fal_napt); - - return ret; -} - -a_int32_t -napt_hw_next_by_age(napt_entry_t *napt, a_uint32_t age) -{ - a_int32_t ret = 0; - fal_napt_entry_t fal_napt = {0}; - - fal_napt.entry_id = napt->entry_id; - fal_napt.status = age; - - if(NAPT_NEXT(0, FAL_NAT_ENTRY_AGE_EN ,&fal_napt) !=0) - { - ret = -1; - } - - napt_entry_cp(napt, &fal_napt); - - return ret; -} - -a_int32_t -napt_hw_get_by_index(napt_entry_t *napt, a_uint16_t hw_index) -{ - fal_napt_entry_t fal_napt = {0}; - sw_error_t rv; - - if(hw_index == 0) - { - fal_napt.entry_id = FAL_NEXT_ENTRY_FIRST_ID; - } - else - { - fal_napt.entry_id = hw_index - 1; - } - - if((rv = NAPT_NEXT(0, 0, &fal_napt)) != 0) - { - HNAT_ERR_PRINTK("[rv:%d] error hw:%x sw:%x\n", - rv, napt->entry_id, hw_index); - return -1; - } - - napt_entry_cp(napt, &fal_napt); - - if(napt->entry_id != hw_index) - { - HNAT_ERR_PRINTK("hw_index error hw:%x sw:%x\n", - napt->entry_id, hw_index); - return -1; - } - - return 0; -} - -a_int32_t napt_hw_get_by_sip(a_uint32_t sip) -{ - fal_napt_entry_t napt; - - memset(&napt, 0, sizeof(fal_napt_entry_t)); - napt.entry_id = FAL_NEXT_ENTRY_FIRST_ID; - napt.src_addr = sip; - if (fal_napt_next(0, FAL_NAT_ENTRY_SOURCE_IP_EN, &napt) == SW_OK) { - return 0; - } - - return -1; -} - -a_uint32_t -napt_hw_used_count_get(void) -{ -#define NAPT_USED_COUNT -#define NAPT_USED_COUNT_OFFSET 0x0e44 /*was:0x0e38*/ -#define NAPT_USED_COUNT_E_LENGTH 11 -#define NAPT_USED_COUNT_E_OFFSET 0x0 -#define NAPT_USED_COUNT_NR_E 1 - sw_error_t rv; - - a_uint32_t count = 0; - HSL_REG_ENTRY_GET(rv, 0, NAPT_USED_COUNT, 0, (a_uint8_t *) (&count), - sizeof (a_uint32_t)); - - return count; -} - -sw_error_t napt_l3_status_set(a_uint32_t dev_id, a_bool_t enable) -{ - sw_error_t rv; - a_uint32_t val; - - if (A_TRUE == enable) - { - val = 1; - } - else if (A_FALSE == enable) - { - val = 0; - } - else - { - return SW_BAD_PARAM; - } - - HSL_REG_FIELD_SET(rv, dev_id, MOD_ENABLE, 0, L3_EN, (a_uint8_t *) (&val), - sizeof (a_uint32_t)); - return rv; -} - -sw_error_t napt_l3_status_get(a_uint32_t dev_id, a_bool_t * enable) -{ - sw_error_t rv; - a_uint32_t val; - - HSL_REG_FIELD_GET(rv, dev_id, MOD_ENABLE, 0, L3_EN, (a_uint8_t *) (&val), - sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - - if (val) - { - *enable = A_TRUE; - } - else - { - *enable = A_FALSE; - } - - return SW_OK; -} - -sw_error_t napt_helper_hsl_init() -{ - return SW_OK; -} - - diff --git a/feeds/ipq807x/qca-ssdk/src/app/nathelper/linux/lib/nat_helper_hsl.h b/feeds/ipq807x/qca-ssdk/src/app/nathelper/linux/lib/nat_helper_hsl.h deleted file mode 100755 index bb7a778d7..000000000 --- a/feeds/ipq807x/qca-ssdk/src/app/nathelper/linux/lib/nat_helper_hsl.h +++ /dev/null @@ -1,257 +0,0 @@ -/* - * Copyright (c) 2012, 2015, 2018, The Linux Foundation. All rights reserved. - * Permission to use, copy, modify, and/or distribute this software for - * any purpose with or without fee is hereby granted, provided that the - * above copyright notice and this permission notice appear in all copies. - * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES - * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR - * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES - * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN - * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT - * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. - */ - - -#ifndef _NAT_HELPER_HSL_H -#define _NAT_HELPER_HSL_H - -#ifdef KVER32 -#include -#include -#else -#include -#endif - -#include -#include "fal_nat.h" - -#define NAT_HW_NUM 32 -#define NAT_HW_PORT_RANGE_MAX 255 - -#define FAL_NAT_ENTRY_PROTOCOL_TCP 0x1 -#define FAL_NAT_ENTRY_PROTOCOL_UDP 0x2 -#define FAL_NAT_ENTRY_PROTOCOL_PPTP 0x4 -#define FAL_NAT_ENTRY_PROTOCOL_ANY 0x8 -#define FAL_NAT_ENTRY_PORT_CHECK 0x20 - -#define MAX_INTF_NUM 4 - -/* WAN connection types */ -#define NF_S17_WAN_TYPE_IP 0 /* DHCP, static IP connection */ -#define NF_S17_WAN_TYPE_PPPOE 1 /* PPPoE connection */ -#define NF_S17_WAN_TYPE_GRE 2 /* GRE connections, ex: PPTP */ -#define NF_S17_WAN_TYPE_PPPOEV6 3 /* IPv6 PPPoE connection using the same session as IPv4 connection */ -#define NF_S17_WAN_TYPE_PPPOES0 4 /* PPPoE connection but not yet connected */ -/* define the H/W Age mode for NAPT entries */ -#define ARP_AGE_NEVER 7 -#define ARP_AGE 6 - -#if !defined (HSL_STANDALONG) -/*NAT API*/ -#define NAPT_ADD fal_napt_add -#define NAPT_GET fal_napt_get -#define NAT_PUB_ADDR_ADD fal_nat_pub_addr_add -#define NAPT_NEXT fal_napt_next -#define NAT_PRV_BASE_ADDR_SET fal_nat_prv_base_addr_set -#define NAT_PRV_BASE_MASK_SET fal_nat_prv_base_mask_set -#define NAPT_DEL fal_napt_del -#define NAT_DEL fal_nat_del -#define NAT_PUB_ADDR_DEL fal_nat_pub_addr_del -#define NAT_ADD fal_nat_add -#define NAT_PRV_ADDR_MODE_GET fal_nat_prv_addr_mode_get - -/*IP API*/ -#define IP_INTF_ENTRY_ADD fal_ip_intf_entry_add -#define IP_HOST_ADD fal_ip_host_add -#define IP_HOST_DEL fal_ip_host_del -#define IP_HOST_GET fal_ip_host_get -#define IP_HOST_NEXT fal_ip_host_next -#define IP_INTF_ENTRY_DEL fal_ip_intf_entry_del -#define IP_HOST_PPPOE_BIND fal_ip_host_pppoe_bind -#define IP_ROUTE_STATUS_SET fal_ip_route_status_set -#define IP_HOST_ROUTE_ADD fal_ip_host_route_set -#define IP_PRV_BASE_ADDR_SET fal_ip_vrf_base_addr_set -#define IP_PRV_BASE_MASK_SET fal_ip_vrf_base_mask_set - -/* PPPOE */ -#define PPPOE_STATUS_GET fal_pppoe_status_get -#define PPPOE_STATUS_SET fal_pppoe_status_set -#define PPPOE_SESSION_ID_SET fal_pppoe_session_id_set -#define PPPOE_SESSION_TABLE_ADD fal_pppoe_session_table_add -#define PPPOE_SESSION_TABLE_DEL fal_pppoe_session_table_del -#define RTD_PPPOE_EN_SET fal_rtd_pppoe_en_set - -/*MISC API*/ -#define MISC_ARP_CMD_SET fal_arp_cmd_set -#define CPU_VID_EN_SET fal_cpu_vid_en_set -#define PORT_ARP_ACK_STATUS_SET fal_port_arp_ack_status_set -#define CPU_PORT_STATUS_SET fal_cpu_port_status_set - -/*ACL API*/ -#define ACL_RULE_ADD fal_acl_rule_add -#define ACL_RULE_DEL fal_acl_rule_delete -#define ACL_LIST_CREATE fal_acl_list_creat -#define ACL_LIST_DESTROY fal_acl_list_destroy -#define ACL_LIST_BIND fal_acl_list_bind -#define ACL_LIST_UNBIND fal_acl_list_unbind -#define ACL_STATUS_GET fal_acl_status_get -#define ACL_STATUS_SET fal_acl_status_set -#define ACL_PORT_UDF_PROFILE_SET fal_acl_port_udf_profile_set - -/*VLAN API */ -#define VLAN_NEXT fal_vlan_next - -/* PORTVLAN API */ -#define PORTVLAN_ROUTE_DEFV_SET(dev_id, port_id) -#define NETISOLATE_SET fal_netisolate_set - -/* PORT_CTRL API */ -#define HEADER_TYPE_SET fal_header_type_set -#define PORT_TXHDR_MODE_SET fal_port_txhdr_mode_set - -/* REG ACCESS API */ -#define REG_GET fal_reg_get -#endif - -extern int nf_athrs17_hnat; -extern int nf_athrs17_hnat_wan_type; -extern int nf_athrs17_hnat_ppp_id; -extern int nf_athrs17_hnat_udp_thresh; -extern a_uint32_t nf_athrs17_hnat_wan_ip; -extern a_uint32_t nf_athrs17_hnat_ppp_peer_ip; -extern unsigned char nf_athrs17_hnat_ppp_peer_mac[ETH_ALEN]; -extern unsigned char nf_athrs17_hnat_wan_mac[ETH_ALEN]; -extern int nf_athrs17_hnat_sync_counter_en; - -extern int nf_athrs17_hnat_ppp_id2; -extern unsigned char nf_athrs17_hnat_ppp_peer_mac2[ETH_ALEN]; - -enum { - NAT_CHIP_VER_8327 = 0x12, - NAT_CHIP_VER_8337 = 0x13, - NAT_CHIP_VER_DESS = 0x14, -}; - -typedef struct -{ - a_uint32_t entry_id; - a_uint32_t flags; - a_uint32_t src_addr; - a_uint32_t trans_addr; - a_uint16_t port_num; - a_uint16_t port_range; -} nat_entry_t; - -typedef struct -{ - a_uint32_t entry_id; - a_uint32_t flags; - a_uint32_t status; - a_uint32_t src_addr; - a_uint32_t dst_addr; - a_uint16_t src_port; - a_uint16_t dst_port; - a_uint32_t trans_addr; - a_uint16_t trans_port; - a_uint32_t ingress_packet; - a_uint32_t ingress_byte; - a_uint32_t egress_packet; - a_uint32_t egress_byte; -} napt_entry_t; - -#if defined (__BIG_ENDIAN) -typedef struct -{ - a_uint16_t ver:2; - a_uint16_t pri:3; - a_uint16_t type:5; - a_uint16_t rev:2; - a_uint16_t with_tag:1; - a_uint16_t sport:3; - a_uint16_t vid; - a_uint16_t magic; -} aos_header_t; -#elif defined (__LITTLE_ENDIAN) -typedef struct -{ - a_uint16_t vid; - a_uint16_t sport:3; - a_uint16_t with_tag:1; - a_uint16_t rev:2; - a_uint16_t type:5; - a_uint16_t pri:3; - a_uint16_t ver:2; -} aos_header_t; -#else -#error "no ENDIAN" -#endif - -a_int32_t -nat_hw_add(nat_entry_t *nat); -a_int32_t -nat_hw_del_by_index(a_uint32_t index); -a_int32_t -nat_hw_flush(void); -a_int32_t -napt_hw_flush(void); -a_int32_t -nat_hw_prv_base_can_update(void); -void -nat_hw_prv_base_update_enable(void); -void -nat_hw_prv_base_update_disable(void); -a_int32_t -nat_hw_prv_base_set(a_uint32_t ip); -a_uint32_t -nat_hw_prv_base_get(void); -a_int32_t -nat_hw_prv_mask_set(a_uint32_t ipmask); -a_uint32_t -nat_hw_prv_mask_get(void); -a_int32_t -nat_hw_prv_base_is_match(a_uint32_t ip); -a_int32_t -if_mac_add(uint8_t *mac, uint32_t vid, uint32_t ipv6); -a_int32_t -if_mac_cleanup(void); -a_int32_t -arp_hw_add(a_uint32_t port, a_uint32_t intf_id, a_uint8_t *ip, a_uint8_t *mac, int is_ipv6_entry); -a_int32_t -arp_if_info_get(void *data, a_uint32_t *sport, a_uint32_t *vid); -a_int32_t -nat_hw_pub_ip_add(a_uint32_t ip, a_uint32_t *index); -void -napt_hw_mode_init(void); -void -napt_hw_mode_cleanup(void); -a_int32_t -nat_hw_pub_ip_del(a_uint32_t index); -a_int32_t -napt_hw_add(napt_entry_t *napt_entry); -a_int32_t -napt_hw_get(napt_entry_t *napt, fal_napt_entry_t *entry); -a_int32_t -napt_hw_dnat_cookie_add(napt_entry_t *napt, a_uint32_t cookie); -a_int32_t -napt_hw_snat_cookie_add(napt_entry_t *napt, a_uint32_t cookie); -a_int32_t -napt_hw_del(napt_entry_t *napt_entry); -a_int32_t -napt_hw_first_by_age(napt_entry_t *napt, a_uint32_t age); -a_int32_t -napt_hw_next_by_age(napt_entry_t *napt, a_uint32_t age); -a_int32_t -napt_hw_get_by_index(napt_entry_t *napt, a_uint16_t hw_index); -a_int32_t napt_hw_get_by_sip(a_uint32_t sip); -a_uint32_t -napt_hw_used_count_get(void); - -sw_error_t napt_l3_status_set(a_uint32_t dev_id, a_bool_t enable); -sw_error_t napt_l3_status_get(a_uint32_t dev_id, a_bool_t * enable); - -sw_error_t napt_helper_hsl_init(void); - - -#endif /*_NAT_HELPER_HSL_H*/ - diff --git a/feeds/ipq807x/qca-ssdk/src/app/nathelper/linux/napt_acl.c b/feeds/ipq807x/qca-ssdk/src/app/nathelper/linux/napt_acl.c deleted file mode 100755 index 2d0de4f9a..000000000 --- a/feeds/ipq807x/qca-ssdk/src/app/nathelper/linux/napt_acl.c +++ /dev/null @@ -1,1622 +0,0 @@ -/* - * Copyright (c) 2012, 2017, The Linux Foundation. All rights reserved. - * Permission to use, copy, modify, and/or distribute this software for - * any purpose with or without fee is hereby granted, provided that the - * above copyright notice and this permission notice appear in all copies. - * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES - * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR - * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES - * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN - * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT - * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. - */ - - -#ifdef KVER32 -#include -#include -#else -#include -#endif -#include -#include - -#include "napt_acl.h" -#include "nat_helper.h" -#include "lib/nat_helper_hsl.h" -#include "hsl_shared_api.h" - -static uint32_t aclrulemask = 0; -extern int nat_chip_ver; - -uint32_t -get_aclrulemask(void) -{ - uint32_t ret; - unsigned long flags; - - local_irq_save(flags); - ret = aclrulemask; - local_irq_restore(flags); - - return ret; -} - -void -set_aclrulemask(uint32_t acl_list) -{ - unsigned long flags; - - local_irq_save(flags); - aclrulemask |= 1<s6_addr32[0]; /* FF02::1:FF00:0000/104 */ - myacl.dest_ip6_val.ul[1] = local_ip->s6_addr32[1]; - myacl.dest_ip6_val.ul[2] = local_ip->s6_addr32[2]; - myacl.dest_ip6_val.ul[3] = local_ip->s6_addr32[3]; - myacl.dest_ip6_mask.ul[0] = 0xffffffff; - myacl.dest_ip6_mask.ul[1] = 0xffffffff; - myacl.dest_ip6_mask.ul[2] = 0xffffffff; - myacl.dest_ip6_mask.ul[3] = 0xff000000; - - FAL_FIELD_FLG_SET ( myacl.field_flg, FAL_ACL_FIELD_INVERSE_ALL ); - FAL_FIELD_FLG_SET ( myacl.field_flg, FAL_ACL_FIELD_IP6_DIP ); - FAL_ACTION_FLG_SET ( myacl.action_flg, FAL_ACL_ACTION_ARP_EN ); - - myacl.arp_ptr = gw_entry_id; - - rtnval = ACL_LIST_CREATE(0, S17_ACL_LIST_IPV6DROUTE, S17_ACL_LIST_PRIO_HIGH); - if ( rtnval != SW_OK ) - { - printk("qcaswitch_acl_list_creat ERROR...\n" ); - printk("already created!? \n"); - return ; - } - - rtnval = ACL_RULE_ADD (0, S17_ACL_LIST_IPV6DROUTE, 0, 1, &myacl ); - if ( rtnval != SW_OK ) - { - printk ( "qcaswitch_acl_rule_add ERROR...\n" ); - return ; - } - - for (i = S17_LAN_PORT0; i <= S17_LAN_PORT4; i++) { - if (i != S17_WAN_PORT) - ACL_LIST_BIND (0, S17_ACL_LIST_IPV6DROUTE, FAL_ACL_DIREC_IN, FAL_ACL_BIND_PORT, i); - } - - /* check for the ACL enable bit */ - if (ACL_STATUS_GET(0, &val) == SW_OK) - { - if (val != A_TRUE) - { - printk("ACL is not yet enabled. Enabling... \n"); - ACL_STATUS_SET(0, A_TRUE); - } - } - - set_aclrulemask(S17_ACL_LIST_IPV6DROUTE); -} - -/* - * Del Default Route ACL rules - */ -void ipv6_droute_del_acl_rules(void) -{ - int i; - - HNAT_PRINTK("IPv6 default route del rule #%d\n", S17_ACL_LIST_IPV6DROUTE); - - if (!(get_aclrulemask() & (1 << S17_ACL_LIST_IPV6DROUTE))) - return; - - for (i = S17_LAN_PORT0; i <= S17_LAN_PORT4; i++) { - if (i != S17_WAN_PORT) - ACL_LIST_UNBIND(0, S17_ACL_LIST_IPV6DROUTE, FAL_ACL_DIREC_IN, FAL_ACL_BIND_PORT, i); - } - - ACL_RULE_DEL(0, S17_ACL_LIST_IPV6DROUTE, 0, 1); - - - ACL_LIST_DESTROY(0, S17_ACL_LIST_IPV6DROUTE); - - unset_aclrulemask(S17_ACL_LIST_IPV6DROUTE); -} - - -static int isis_pppoe_del_rule0(void) -{ - int rtnval; - - rtnval = ACL_LIST_UNBIND(0, S17_ACL_LIST_PPPOE, FAL_ACL_DIREC_IN, FAL_ACL_BIND_PORT, S17_CPU_PORT); - if (rtnval != SW_OK) - aos_printk("unbind error... \n"); - - rtnval = ACL_RULE_DEL(0, S17_ACL_LIST_PPPOE, 0, 1); - if (rtnval != SW_OK) - aos_printk("delete error... \n"); - - rtnval = ACL_LIST_DESTROY(0, S17_ACL_LIST_PPPOE); - if (rtnval != SW_OK) - aos_printk("destroy error... \n"); - - return rtnval; -} - - -/* - * PPPoE ACL rules - * Force ARP_INDEX_EN to the next hop for CPU port - * Force SNAT and ARP_INDEX_EN to the next hop for LAN ports - */ -void pppoe_add_acl_rules( - uint32_t wan_ip, uint32_t local_ip, - uint32_t local_ip_mask, uint32_t gw_entry_id) -{ - fal_acl_rule_t myacl; - uint32_t rtnval, cnt; - a_bool_t val; - int i; - - /* do the 1st, 2nd and 3rd rules */ - for (cnt = 0; cnt < 3; cnt++) - { - memset(&myacl, 0, sizeof(fal_acl_rule_t)); - - switch (cnt) - { - case 0: - if (((nat_chip_ver & 0xffff)>>8) != NAT_CHIP_VER_8327) - break; - - aos_printk("PPPoE adding rule #%d\n", S17_ACL_LIST_PPPOE); - myacl.rule_type = FAL_ACL_RULE_IP4; - myacl.src_ip4_val = wan_ip; - myacl.src_ip4_mask = 0xffffffff; - aos_printk("WAN IP: %.8x\n", wan_ip); - /* - IPv4 rule, with SIP field - IF SIP == WAN IP, FORCE the ARP_INDEX_EN to the PPPoE ARP INDEX - enable packet forwarding & forward only. i.e. no FORCE_L3_MODE - ARP_INDEX_EN, to the PPPoE peer ARP index, - Change the CVID to WAN_VID (2) - Bind to CPU port - */ - FAL_FIELD_FLG_SET(myacl.field_flg, FAL_ACL_FIELD_IP4_SIP); - FAL_FIELD_FLG_SET(myacl.field_flg, FAL_ACL_FIELD_MAC_CTAG_VID); - - FAL_ACTION_FLG_SET(myacl.action_flg, FAL_ACL_ACTION_ARP_EN); - FAL_ACTION_FLG_SET(myacl.action_flg, FAL_ACL_ACTION_REMARK_CTAG_VID); - - myacl.arp_ptr = gw_entry_id; - /* fixed with CVID = 2 */ - myacl.ctag_vid = 2; - - rtnval = ACL_LIST_CREATE(0, S17_ACL_LIST_PPPOE, S17_ACL_LIST_PRIO_HIGH); - if (rtnval != SW_OK) - { - aos_printk("ACL_LIST_CREATE ERROR...\n"); - aos_printk("PPPoE Session ID changed !? \n"); - /* delete the old ACL list */ - rtnval = isis_pppoe_del_rule0(); - if (rtnval != SW_OK) - aos_printk("pppoe_del_rule0: %d \n", rtnval); - - /* create the ACL list again */ - rtnval = ACL_LIST_CREATE(0, S17_ACL_LIST_PPPOE, S17_ACL_LIST_PRIO_HIGH); - if (rtnval != SW_OK) - { - aos_printk("ACL_LIST_CREATE ERROR...\n"); - break; - } - } - - rtnval = ACL_RULE_ADD(0, S17_ACL_LIST_PPPOE, 0, 1, &myacl); - if (rtnval != SW_OK) - { - aos_printk("ACL_RULE_ADD ERROR...\n"); - break; - } - - ACL_LIST_BIND(0, S17_ACL_LIST_PPPOE, FAL_ACL_DIREC_IN, FAL_ACL_BIND_PORT, S17_CPU_PORT_W); - - break; - - case 1: - aos_printk("PPPoE adding rule #%d\n", S17_ACL_LIST_PPPOE+1); - myacl.rule_type = FAL_ACL_RULE_IP4; - myacl.dest_ip4_val = ntohl(local_ip); - myacl.dest_ip4_mask = ntohl(local_ip_mask); - - /* - IPv4 rule, with DIP field - IF DIP != LAN IP, FORCE the ARP_INDEX_EN to the PPPoE ARP INDEX - AND FORCE L3 SNAT - ARP_INDEX_EN, to the PPPoE peer ARP index - Bind to LAN ports - */ - - FAL_FIELD_FLG_SET(myacl.field_flg, FAL_ACL_FIELD_INVERSE_ALL); - FAL_FIELD_FLG_SET(myacl.field_flg, FAL_ACL_FIELD_IP4_DIP); - - FAL_ACTION_FLG_SET(myacl.action_flg, FAL_ACL_ACTION_POLICY_FORWARD_EN); - FAL_ACTION_FLG_SET(myacl.action_flg, FAL_ACL_ACTION_ARP_EN); - - myacl.arp_ptr = gw_entry_id; - myacl.policy_fwd = FAL_ACL_POLICY_SNAT; - - rtnval = ACL_LIST_CREATE(0, S17_ACL_LIST_PPPOE+1, S17_ACL_LIST_PRIO_HIGH); - if (rtnval != SW_OK) - { - aos_printk("ACL_LIST_CREATE ERROR...\n"); - break; - } - - rtnval = ACL_RULE_ADD(0, S17_ACL_LIST_PPPOE+1, 0, 1, &myacl); - if (rtnval != SW_OK) - { - aos_printk("ACL_RULE_ADD ERROR...\n"); - break; - } - /* bind to LAN ports (1-4) */ - for (i = S17_LAN_PORT0; i <= S17_LAN_PORT4; i++) { - if (i != S17_WAN_PORT) - ACL_LIST_BIND(0, S17_ACL_LIST_PPPOE+1, FAL_ACL_DIREC_IN, FAL_ACL_BIND_PORT, i); - } - - break; - - case 2: - /* - User defined filter ACL - filter out 0x8100000288641100 packets and set the CVID to - a predefined VID (100 in this case) - ARP_INDEX_EN, to the PPPoE peer ARP index - Bind to CPU port - */ - aos_printk("PPPoE adding rule #%d\n", S17_ACL_LIST_PPPOE+2); - myacl.rule_type = FAL_ACL_RULE_UDF; - /* set the UDP ACL type as L2, with length 8, offset 12 */ - ACL_PORT_UDF_PROFILE_SET(0, S17_CPU_PORT, FAL_ACL_UDF_TYPE_L2, 12, 8); - myacl.udf_len = 8; - myacl.udf_offset = 12; - myacl.udf_type = FAL_ACL_UDF_TYPE_L2; - memset(&myacl.udf_val, 0, sizeof(myacl.udf_val)); - memset(&myacl.udf_mask, 0, sizeof(myacl.udf_mask)); - /* UDF filter to check for 0x8100000288641100 packets */ - myacl.udf_val[0] = 0x81; - myacl.udf_val[1] = 0x00; - myacl.udf_val[2] = 0x00; - myacl.udf_val[3] = 0x02; - myacl.udf_val[4] = 0x88; - myacl.udf_val[5] = 0x64; - myacl.udf_val[6] = 0x11; - myacl.udf_val[7] = 0x00; - - myacl.udf_mask[0] = 0xff; - myacl.udf_mask[1] = 0xff; - myacl.udf_mask[2] = 0xff; - myacl.udf_mask[3] = 0xff; - myacl.udf_mask[4] = 0xff; - myacl.udf_mask[5] = 0xff; - myacl.udf_mask[6] = 0xff; - myacl.udf_mask[7] = 0xff; - - FAL_FIELD_FLG_SET(myacl.field_flg, FAL_ACL_FIELD_UDF); - FAL_FIELD_FLG_SET(myacl.field_flg, FAL_ACL_FIELD_MAC_CTAG_VID); - - FAL_ACTION_FLG_SET(myacl.action_flg, FAL_ACL_ACTION_ARP_EN); - FAL_ACTION_FLG_SET(myacl.action_flg, FAL_ACL_ACTION_REMARK_CTAG_VID); - - myacl.arp_ptr = gw_entry_id; - /* fixed with CVID = 100 */ - myacl.ctag_vid = 100; - - rtnval = ACL_LIST_CREATE(0, S17_ACL_LIST_PPPOE + 2, S17_ACL_LIST_PRIO_HIGH); - if (rtnval != SW_OK) - { - aos_printk("ACL_LIST_CREATE ERROR...\n"); - break; - } - - rtnval = ACL_RULE_ADD(0, S17_ACL_LIST_PPPOE + 2, 0, 1, &myacl); - if (rtnval != SW_OK) - { - aos_printk("ACL_RULE_ADD ERROR...\n"); - break; - } - - ACL_LIST_BIND(0, S17_ACL_LIST_PPPOE + 2, FAL_ACL_DIREC_IN, FAL_ACL_BIND_PORT, S17_CPU_PORT); - break; - } - } - - if (ACL_STATUS_GET(0, &val) == SW_OK) - { - if (val != A_TRUE) - { - aos_printk("ACL is not yet enabled. Enabling... \n"); - ACL_STATUS_SET(0, A_TRUE); - } - } -} - -static void pppoe_del_acl_rule1(void) -{ - int i; - for (i = S17_LAN_PORT0; i <= S17_LAN_PORT4; i++) { - if (i != S17_WAN_PORT) - ACL_LIST_UNBIND(0, S17_ACL_LIST_PPPOE+1, - FAL_ACL_DIREC_IN, FAL_ACL_BIND_PORT, i); - } - - ACL_RULE_DEL(0, S17_ACL_LIST_PPPOE+1, 0, 1); - - ACL_LIST_DESTROY(0, S17_ACL_LIST_PPPOE+1); -} - -static void pppoe_del_acl_rule2(void) -{ - ACL_LIST_UNBIND(0, S17_ACL_LIST_PPPOE+2, FAL_ACL_DIREC_IN, FAL_ACL_BIND_PORT, S17_CPU_PORT); - ACL_LIST_UNBIND(0, S17_ACL_LIST_PPPOE+2, FAL_ACL_DIREC_IN, FAL_ACL_BIND_PORT, S17_LAN_PORT1); - ACL_LIST_UNBIND(0, S17_ACL_LIST_PPPOE+2, FAL_ACL_DIREC_IN, FAL_ACL_BIND_PORT, S17_LAN_PORT2); - ACL_LIST_UNBIND(0, S17_ACL_LIST_PPPOE+2, FAL_ACL_DIREC_IN, FAL_ACL_BIND_PORT, S17_LAN_PORT3); - - ACL_RULE_DEL(0, S17_ACL_LIST_PPPOE+2, 0, 1); - - ACL_LIST_DESTROY(0, S17_ACL_LIST_PPPOE+2); -} -void pppoe_del_acl_rules(void) -{ - if (((nat_chip_ver & 0xffff)>>8) == NAT_CHIP_VER_8327) - isis_pppoe_del_rule0(); - pppoe_del_acl_rule1(); - pppoe_del_acl_rule2(); -} -/* - * When LAN & WAN IPs are too close, apply this ACL - * ex: WAN 192.168.1.x, LAN 192.168.0.x - */ -void -ip_conflict_add_acl_rules(uint32_t wan_ip, uint32_t lan_ip, uint32_t gw_entry_id) -{ - fal_acl_rule_t myacl; - uint32_t rtnval, cnt; - a_bool_t val; - int i; - - if (get_aclrulemask() & (1 << S17_ACL_LIST_IPCONF)) return; - - for (cnt = 0; cnt < 2; cnt++) - { - memset(&myacl, 0, sizeof(fal_acl_rule_t)); - - aos_printk("IP conflict adding rule #%d\n", cnt); - - switch (cnt) - { - case 0: - myacl.rule_type = FAL_ACL_RULE_IP4; - myacl.dest_ip4_val = lan_ip; - myacl.dest_ip4_mask = 0xffffff00; - myacl.src_ip4_val = lan_ip; - myacl.src_ip4_mask = 0xffffff00; - - /* - IPv4 rule, with DIP & SIP field - for DIP and SIP = LAN IP, do the next step - */ - FAL_FIELD_FLG_SET(myacl.field_flg, FAL_ACL_FIELD_IP4_DIP); - FAL_FIELD_FLG_SET(myacl.field_flg, FAL_ACL_FIELD_IP4_SIP); - - rtnval = ACL_LIST_CREATE(0, S17_ACL_LIST_IPCONF, S17_ACL_LIST_PRIO_HIGH); - if (rtnval != SW_OK) - { - aos_printk("ACL_LIST_CREATE ERROR...\n"); - break; - } - - rtnval = ACL_RULE_ADD(0, S17_ACL_LIST_IPCONF, 0, 1, &myacl); - if (rtnval != SW_OK) - { - aos_printk("ACL_RULE_ADD ERROR...\n"); - break; - } - - /* bind to LAN ports */ - for (i = S17_LAN_PORT0; i <= S17_LAN_PORT4; i++) { - if (i != S17_WAN_PORT) - ACL_LIST_BIND(0, S17_ACL_LIST_IPCONF, FAL_ACL_DIREC_IN, FAL_ACL_BIND_PORT, i); - } - - aclrulemask |= (1 << S17_ACL_LIST_IPCONF); - set_aclrulemask(S17_ACL_LIST_IPCONF); - - break; - - case 1: - aos_printk("ARP index entry_id: %d\n", gw_entry_id); - - myacl.rule_type = FAL_ACL_RULE_IP4; - myacl.src_ip4_val = lan_ip; - myacl.src_ip4_mask = 0xffffff00; - - /* - IPv4 rule, with SIP field - enable packet forwarding & forward only. i.e. no FORCE_L3_MODE - ARP_INDEX_EN, to the PPPoE peer ARP index - */ - - FAL_FIELD_FLG_SET(myacl.field_flg, FAL_ACL_FIELD_IP4_SIP); - - FAL_ACTION_FLG_SET(myacl.action_flg, FAL_ACL_ACTION_POLICY_FORWARD_EN); - FAL_ACTION_FLG_SET(myacl.action_flg, FAL_ACL_ACTION_ARP_EN); - - myacl.arp_ptr = gw_entry_id; - myacl.policy_fwd = FAL_ACL_POLICY_SNAT; - - /* rule no. 4 */ - rtnval = ACL_LIST_CREATE(0, S17_ACL_LIST_IPCONF+1, S17_ACL_LIST_PRIO_HIGH); - if (rtnval != SW_OK) - { - aos_printk("ACL_LIST_CREATE ERROR...\n"); - break; - } - - rtnval = ACL_RULE_ADD(0, S17_ACL_LIST_IPCONF+1, 0, 1, &myacl); - if (rtnval != SW_OK) - { - aos_printk("ACL_RULE_ADD ERROR...\n"); - break; - } - /* bind to LAN ports (1-4) */ - for (i = S17_LAN_PORT0; i <= S17_LAN_PORT4; i++) { - if (i != S17_WAN_PORT) - ACL_LIST_BIND(0, S17_ACL_LIST_IPCONF+1, FAL_ACL_DIREC_IN, FAL_ACL_BIND_PORT, i); - } - - break; - - default: - break; - } - } - - if (ACL_STATUS_GET(0, &val) == SW_OK) - { - if (val != A_TRUE) - { - aos_printk("ACL is not yet enabled. Enabling... \n"); - ACL_STATUS_SET(0, A_TRUE); - } - } -} - -void ip_conflict_del_acl_rules(void) -{ - int i; - - if (!(get_aclrulemask() & (1 << S17_ACL_LIST_IPCONF))) - return; - - for (i = S17_LAN_PORT0; i <= S17_LAN_PORT4; i++) { - if (i != S17_WAN_PORT) { - ACL_LIST_UNBIND(0, S17_ACL_LIST_IPCONF, FAL_ACL_DIREC_IN, FAL_ACL_BIND_PORT, i); - ACL_LIST_UNBIND(0, S17_ACL_LIST_IPCONF+1, FAL_ACL_DIREC_IN, FAL_ACL_BIND_PORT, i); - } - } - - ACL_RULE_DEL(0, S17_ACL_LIST_IPCONF, 0, 1); - - ACL_LIST_DESTROY(0, S17_ACL_LIST_IPCONF); - - ACL_RULE_DEL(0, S17_ACL_LIST_IPCONF+1, 0, 1); - - ACL_LIST_DESTROY(0, S17_ACL_LIST_IPCONF+1); - - unset_aclrulemask(S17_ACL_LIST_IPCONF); -} - - -/* -solicted_node address - FF02::1:FF00:0000/104 => Solicited-Node Address -*/ -void -ipv6_snooping_solicted_node_add_acl_rules ( void ) -{ - fal_acl_rule_t myacl; - uint32_t rtnval; - a_bool_t val; - int i; - - memset ( &myacl, 0, sizeof ( fal_acl_rule_t ) ); - - aos_printk("Adding ACL rules %d - %s\n", S17_ACL_LIST_IPV6_SOLICITED_NODE, __func__); - myacl.rule_type = FAL_ACL_RULE_IP6; - myacl.dest_ip6_val.ul[0] = 0xff020000; /* FF02::1:FF00:0000/104 */ - myacl.dest_ip6_val.ul[1] = 0x00000000; - myacl.dest_ip6_val.ul[2] = 0x00000001; - myacl.dest_ip6_val.ul[3] = 0xff000000; - - myacl.dest_ip6_mask.ul[0] = 0xffffffff; - myacl.dest_ip6_mask.ul[1] = 0xffffffff; - myacl.dest_ip6_mask.ul[2] = 0xffffffff; - myacl.dest_ip6_mask.ul[3] = 0xff000000; - -#ifdef CONFIG_ATH_8327_ACL_IPV6_PASSTHROUGH - /* ACL action destination port, WAN, LAN and CPU ports */ - myacl.ports = (1 << S17_WAN_PORT) | (1 << S17_CPU_PORT) | (1 << S17_LAN_PORT0) | - (1 << S17_LAN_PORT1) | (1 << S17_LAN_PORT2) | (1 << S17_LAN_PORT3); - - FAL_FIELD_FLG_SET ( myacl.field_flg, FAL_ACL_FIELD_IP6_DIP ); -#else - /* ACL action destination port, LAN and CPU ports */ - myacl.ports = (1 << S17_CPU_PORT) | (1 << S17_LAN_PORT0) | - (1 << S17_LAN_PORT1) | (1 << S17_LAN_PORT2) | (1 << S17_LAN_PORT3); - myacl.vid_val = 0x1; - myacl.vid_mask = 0xfff; - - FAL_FIELD_FLG_SET ( myacl.field_flg, FAL_ACL_FIELD_IP6_DIP ); - FAL_FIELD_FLG_SET ( myacl.field_flg, FAL_ACL_FIELD_MAC_VID ); -#endif - - FAL_ACTION_FLG_SET ( myacl.action_flg, FAL_ACL_ACTION_REDPT ); - - rtnval = ACL_LIST_CREATE ( 0, S17_ACL_LIST_IPV6_SOLICITED_NODE, S17_ACL_LIST_PRIO_MID); - if ( rtnval != SW_OK ) - { - if(rtnval == SW_ALREADY_EXIST) - { - //aos_printk ( "ipv6_snooping_solicted rules acl list already exists.\n"); - - } else { - aos_printk ( "%s: ACL_LIST_CREATE ERROR (%d)...\n", __func__, rtnval ); - } - return; - } - - rtnval = ACL_RULE_ADD ( 0, S17_ACL_LIST_IPV6_SOLICITED_NODE, 0, 1, &myacl ); - if ( rtnval != SW_OK ) - { - aos_printk ( "%s: ACL_RULE_ADD ERROR...(%d)\n", __func__, rtnval ); - return; - } - - // ACL pattern source port -#ifdef CONFIG_ATH_8327_ACL_IPV6_PASSTHROUGH - ACL_LIST_BIND ( 0, S17_ACL_LIST_IPV6_SOLICITED_NODE, FAL_ACL_DIREC_IN, FAL_ACL_BIND_PORT, S17_WAN_PORT ); -#endif - ACL_LIST_BIND ( 0, S17_ACL_LIST_IPV6_SOLICITED_NODE, FAL_ACL_DIREC_IN, FAL_ACL_BIND_PORT, S17_CPU_PORT ); - for (i = S17_LAN_PORT0; i <= S17_LAN_PORT4; i++) { - if (i != S17_WAN_PORT) - ACL_LIST_BIND ( 0, S17_ACL_LIST_IPV6_SOLICITED_NODE, FAL_ACL_DIREC_IN, FAL_ACL_BIND_PORT, i); - } - - if ( ACL_STATUS_GET ( 0, &val ) == SW_OK ) - { - if ( val != A_TRUE ) - { - aos_printk ( "ACL is not yet enabled. Enabling... \n" ); - ACL_STATUS_SET(0, A_TRUE); - } - } -} - - -/* -Node Information Queries (RFC 4620 is experimental) - FF02:0:0:0:0:2:FF00::/104 => Node Information Queries -*/ -void -ipv6_snooping_nodeinfo_query_add_acl_rules ( void ) -{ - fal_acl_rule_t myacl; - uint32_t rtnval; - a_bool_t val; - int i; - - memset ( &myacl, 0, sizeof ( fal_acl_rule_t ) ); - - aos_printk("Adding ACL rules %d - %s\n", S17_ACL_LIST_IPV6_NODEINFO_QUERY, __func__); - myacl.rule_type = FAL_ACL_RULE_IP6; - myacl.dest_ip6_val.ul[0] = 0xff020000; /* FF02:0:0:0:0:2:FF00::/104 */ - myacl.dest_ip6_val.ul[1] = 0x00000000; - myacl.dest_ip6_val.ul[2] = 0x00000002; - myacl.dest_ip6_val.ul[3] = 0xff000000; - - myacl.dest_ip6_mask.ul[0] = 0xffffffff; - myacl.dest_ip6_mask.ul[1] = 0xffffffff; - myacl.dest_ip6_mask.ul[2] = 0xffffffff; - myacl.dest_ip6_mask.ul[3] = 0xff000000; - -#ifdef CONFIG_ATH_8327_ACL_IPV6_PASSTHROUGH - /* ACL action destination port, WAN, LAN and CPU ports */ - myacl.ports = (1 << S17_WAN_PORT) | (1 << S17_CPU_PORT) | (1 << S17_LAN_PORT0) | - (1 << S17_LAN_PORT1) | (1 << S17_LAN_PORT2) | (1 << S17_LAN_PORT3); - - FAL_FIELD_FLG_SET ( myacl.field_flg, FAL_ACL_FIELD_IP6_DIP ); -#else - /* ACL action destination port, LAN and CPU ports */ - myacl.ports = (1 << S17_CPU_PORT) | (1 << S17_LAN_PORT0) | - (1 << S17_LAN_PORT1) | (1 << S17_LAN_PORT2) | (1 << S17_LAN_PORT3); - myacl.vid_val = 0x1; - myacl.vid_mask = 0xfff; - - FAL_FIELD_FLG_SET ( myacl.field_flg, FAL_ACL_FIELD_IP6_DIP ); - FAL_FIELD_FLG_SET ( myacl.field_flg, FAL_ACL_FIELD_MAC_VID ); -#endif - - FAL_ACTION_FLG_SET ( myacl.action_flg, FAL_ACL_ACTION_REDPT ); - - rtnval = ACL_LIST_CREATE ( 0, S17_ACL_LIST_IPV6_NODEINFO_QUERY, S17_ACL_LIST_PRIO_MID); - if ( rtnval != SW_OK ) - { - aos_printk ( "%s: ACL_LIST_CREATE ERROR (%d)...\n", __func__, rtnval ); - return; - } - - rtnval = ACL_RULE_ADD ( 0, S17_ACL_LIST_IPV6_NODEINFO_QUERY, 0, 1, &myacl ); - if ( rtnval != SW_OK ) - { - aos_printk ( "%s: ACL_RULE_ADD ERROR...(%d)\n", __func__, rtnval ); - return; - } - - // ACL pattern source port -#ifdef CONFIG_ATH_8327_ACL_IPV6_PASSTHROUGH - ACL_LIST_BIND ( 0, S17_ACL_LIST_IPV6_NODEINFO_QUERY, FAL_ACL_DIREC_IN, FAL_ACL_BIND_PORT, S17_WAN_PORT ); -#endif - ACL_LIST_BIND ( 0, S17_ACL_LIST_IPV6_NODEINFO_QUERY, FAL_ACL_DIREC_IN, FAL_ACL_BIND_PORT, S17_CPU_PORT ); - for (i = S17_LAN_PORT0; i <= S17_LAN_PORT4; i++) { - if (i != S17_WAN_PORT) - ACL_LIST_BIND ( 0, S17_ACL_LIST_IPV6_NODEINFO_QUERY, FAL_ACL_DIREC_IN, FAL_ACL_BIND_PORT, i); - } - - if ( ACL_STATUS_GET ( 0, &val ) == SW_OK ) - { - if ( val != A_TRUE ) - { - aos_printk ( "ACL is not yet enabled. Enabling... \n" ); - ACL_STATUS_SET(0, A_TRUE); - } - } -} - - -/* -sextuple0_group_acl_rules contains following addresses: - FF02:0:0:0:0:0:0:1 => All Nodes Address - FF02:0:0:0:0:0:0:2 => All Routers Address - FF02:0:0:0:0:0:0:9 => RIP Routers - FF02:0:0:0:0:0:0:C => SSDP - FF02:0:0:0:0:0:0:16 => All MLDv2-capable routers - FF02:0:0:0:0:0:0:FB => mDNSv6 -*/ -void -ipv6_snooping_sextuple0_group_add_acl_rules ( void ) -{ - fal_acl_rule_t myacl; - uint32_t rtnval; - a_bool_t val; - int i; - - memset ( &myacl, 0, sizeof ( fal_acl_rule_t ) ); - - aos_printk("Adding ACL rules %d - %s\n", S17_ACL_LIST_IPV6_SEXTUPLE0_GROUP, __func__); - myacl.rule_type = FAL_ACL_RULE_IP6; - myacl.dest_ip6_val.ul[0] = 0xff020000; /* FF02::/120 */ - myacl.dest_ip6_val.ul[1] = 0x00000000; - myacl.dest_ip6_val.ul[2] = 0x00000000; - myacl.dest_ip6_val.ul[3] = 0x00000000; - - myacl.dest_ip6_mask.ul[0] = 0xffffffff; - myacl.dest_ip6_mask.ul[1] = 0xffffffff; - myacl.dest_ip6_mask.ul[2] = 0xffffffff; - myacl.dest_ip6_mask.ul[3] = 0xffffff00; - -#ifdef CONFIG_ATH_8327_ACL_IPV6_PASSTHROUGH - /* ACL action destination port, WAN, LAN and CPU ports */ - myacl.ports = (1 << S17_WAN_PORT) | (1 << S17_CPU_PORT) | (1 << S17_LAN_PORT0) | - (1 << S17_LAN_PORT1) | (1 << S17_LAN_PORT2) | (1 << S17_LAN_PORT3); - - FAL_FIELD_FLG_SET ( myacl.field_flg, FAL_ACL_FIELD_IP6_DIP ); -#else - /* ACL action destination port, LAN and CPU ports */ - myacl.ports = (1 << S17_CPU_PORT) | (1 << S17_LAN_PORT0) | - (1 << S17_LAN_PORT1) | (1 << S17_LAN_PORT2) | (1 << S17_LAN_PORT3); - myacl.vid_val = 0x1; - myacl.vid_mask = 0xfff; - - FAL_FIELD_FLG_SET ( myacl.field_flg, FAL_ACL_FIELD_IP6_DIP ); - FAL_FIELD_FLG_SET ( myacl.field_flg, FAL_ACL_FIELD_MAC_VID ); -#endif - - FAL_ACTION_FLG_SET ( myacl.action_flg, FAL_ACL_ACTION_REDPT ); - - rtnval = ACL_LIST_CREATE ( 0, S17_ACL_LIST_IPV6_SEXTUPLE0_GROUP, S17_ACL_LIST_PRIO_MID); - if ( rtnval != SW_OK ) - { - if(rtnval == SW_ALREADY_EXIST) - { - //aos_printk ( "ipv6_snooping_sextuple0 rules acl list already exists.\n"); - } else { - aos_printk ( "%s: ACL_LIST_CREATE ERROR (%d)...\n", __func__, rtnval ); - } - return; - } - rtnval = ACL_RULE_ADD ( 0, S17_ACL_LIST_IPV6_SEXTUPLE0_GROUP, 0, 1, &myacl ); - if ( rtnval != SW_OK ) - { - aos_printk ( "%s: ACL_RULE_ADD ERROR...(%d)\n", __func__, rtnval ); - return; - } - - // ACL pattern source port -#ifdef CONFIG_ATH_8327_ACL_IPV6_PASSTHROUGH - ACL_LIST_BIND ( 0, S17_ACL_LIST_IPV6_SEXTUPLE0_GROUP, FAL_ACL_DIREC_IN, FAL_ACL_BIND_PORT, S17_WAN_PORT ); -#endif - ACL_LIST_BIND ( 0, S17_ACL_LIST_IPV6_SEXTUPLE0_GROUP, FAL_ACL_DIREC_IN, FAL_ACL_BIND_PORT, S17_CPU_PORT ); - for (i = S17_LAN_PORT0; i <= S17_LAN_PORT4; i++) { - if (i != S17_WAN_PORT) - ACL_LIST_BIND ( 0, S17_ACL_LIST_IPV6_SEXTUPLE0_GROUP, FAL_ACL_DIREC_IN, FAL_ACL_BIND_PORT, i ); - } - - if ( ACL_STATUS_GET ( 0, &val ) == SW_OK ) - { - if ( val != A_TRUE ) - { - aos_printk ( "ACL is not yet enabled. Enabling... \n" ); - ACL_STATUS_SET(0, A_TRUE); - } - } -} - - -/* -quintruple0_1_group_acl_rules contains following addresses: - FF02:0:0:0:0:0:1:2 => All-dhcp-agents - FF02:0:0:0:0:0:1:3 => LLMNR -*/ -void -ipv6_snooping_quintruple0_1_group_add_acl_rules ( void ) -{ - fal_acl_rule_t myacl; - uint32_t rtnval; - a_bool_t val; - int i; - - memset ( &myacl, 0, sizeof ( fal_acl_rule_t ) ); - - aos_printk("Adding ACL rules %d - %s\n", S17_ACL_LIST_IPV6_QUINTRUPLE0_1_GROUP, __func__); - myacl.rule_type = FAL_ACL_RULE_IP6; - myacl.dest_ip6_val.ul[0] = 0xff020000; /* FF02:0:0:0:0:0:1::/125 */ - myacl.dest_ip6_val.ul[1] = 0x00000000; - myacl.dest_ip6_val.ul[2] = 0x00000000; - myacl.dest_ip6_val.ul[3] = 0x00010000; - - myacl.dest_ip6_mask.ul[0] = 0xffffffff; - myacl.dest_ip6_mask.ul[1] = 0xffffffff; - myacl.dest_ip6_mask.ul[2] = 0xffffffff; - myacl.dest_ip6_mask.ul[3] = 0xfffffff8; - -#ifdef CONFIG_ATH_8327_ACL_IPV6_PASSTHROUGH - myacl.ports = (1 << S17_WAN_PORT) | (1 << S17_CPU_PORT) | (1 << S17_LAN_PORT0) | - (1 << S17_LAN_PORT1) | (1 << S17_LAN_PORT2) | (1 << S17_LAN_PORT3); - - FAL_FIELD_FLG_SET ( myacl.field_flg, FAL_ACL_FIELD_IP6_DIP ); -#else - /* ACL action destination port, LAN and CPU ports */ - myacl.ports = (1 << S17_CPU_PORT) | (1 << S17_LAN_PORT0) | - (1 << S17_LAN_PORT1) | (1 << S17_LAN_PORT2) | (1 << S17_LAN_PORT3); - myacl.vid_val = 0x1; - myacl.vid_mask = 0xfff; - - FAL_FIELD_FLG_SET ( myacl.field_flg, FAL_ACL_FIELD_IP6_DIP ); - FAL_FIELD_FLG_SET ( myacl.field_flg, FAL_ACL_FIELD_MAC_VID ); -#endif - - FAL_ACTION_FLG_SET ( myacl.action_flg, FAL_ACL_ACTION_REDPT ); - - rtnval = ACL_LIST_CREATE ( 0, S17_ACL_LIST_IPV6_QUINTRUPLE0_1_GROUP, S17_ACL_LIST_PRIO_MID); - if ( rtnval != SW_OK ) - { - if(rtnval == SW_ALREADY_EXIST) - { - //aos_printk ( "ipv6_snooping_quintruple0 rules acl list already exists.\n"); - } else { - aos_printk ( "%s: ACL_LIST_CREATE ERROR (%d)...\n", __func__, rtnval ); - } - return; - } - rtnval = ACL_RULE_ADD ( 0, S17_ACL_LIST_IPV6_QUINTRUPLE0_1_GROUP, 0, 1, &myacl ); - if ( rtnval != SW_OK ) - { - aos_printk ( "%s: ACL_RULE_ADD ERROR...(%d)\n", __func__, rtnval ); - return; - } - - /* ACL pattern soruce port */ -#ifdef CONFIG_ATH_8327_ACL_IPV6_PASSTHROUGH - ACL_LIST_BIND ( 0, S17_ACL_LIST_IPV6_QUINTRUPLE0_1_GROUP, FAL_ACL_DIREC_IN, FAL_ACL_BIND_PORT, S17_WAN_PORT ); -#endif - ACL_LIST_BIND ( 0, S17_ACL_LIST_IPV6_QUINTRUPLE0_1_GROUP, FAL_ACL_DIREC_IN, FAL_ACL_BIND_PORT, S17_CPU_PORT ); - for (i = S17_LAN_PORT0; i <= S17_LAN_PORT4; i++) { - if (i != S17_WAN_PORT) - ACL_LIST_BIND ( 0, S17_ACL_LIST_IPV6_QUINTRUPLE0_1_GROUP, FAL_ACL_DIREC_IN, FAL_ACL_BIND_PORT, i ); - } - - if ( ACL_STATUS_GET ( 0, &val ) == SW_OK ) - { - if ( val != A_TRUE ) - { - aos_printk ( "ACL is not yet enabled. Enabling... \n" ); - ACL_STATUS_SET(0, A_TRUE); - } - } -} - -/* -When HW IGMPSNOOPING Enabled, we need to let UPnP SSDP Multicast packets send to lan -*/ -void upnp_ssdp_add_acl_rules(void) -{ - fal_acl_rule_t myacl; - uint32_t rtnval; - a_bool_t val; - int i; - - aos_printk("Adding ACL rules %d - %s\n", S17_ACL_LIST_UPNP_SSDP, __func__); - memset ( &myacl, 0, sizeof ( fal_acl_rule_t ) ); - - myacl.rule_type = FAL_ACL_RULE_IP4; - myacl.dest_ip4_val = 0xeffffffa; // 239.255.255.250 - myacl.dest_ip4_mask = 0xffffffff; - /* ACL action destination port, LAN and CPU ports */ - myacl.ports = (1 << S17_CPU_PORT) | (1 << S17_LAN_PORT0) | - (1 << S17_LAN_PORT1) | (1 << S17_LAN_PORT2) | (1 << S17_LAN_PORT3); - - FAL_FIELD_FLG_SET ( myacl.field_flg, FAL_ACL_FIELD_IP4_DIP ); - FAL_ACTION_FLG_SET ( myacl.action_flg, FAL_ACL_ACTION_REDPT ); - - rtnval = ACL_LIST_CREATE ( 0, S17_ACL_LIST_UPNP_SSDP, S17_ACL_LIST_PRIO_MID); - if ( rtnval != SW_OK ) - { - if(rtnval == SW_ALREADY_EXIST) - { - //aos_printk ( "upnp_ssdp rules acl list already exists.\n"); - } else { - aos_printk ( "upnp_ssdp_acl_rules: ACL_LIST_CREATE ERROR (%d)...\n",rtnval ); - } - return ; - } - - rtnval = ACL_RULE_ADD ( 0, S17_ACL_LIST_UPNP_SSDP, 0, 1, &myacl ); - if ( rtnval != SW_OK ) - { - aos_printk ( "upnp_ssdp_acl_rules: ACL_RULE_ADD ERROR...(%d)\n" ,rtnval ); - return ; - } - - // Pattern source port - ACL_LIST_BIND ( 0, S17_ACL_LIST_UPNP_SSDP, FAL_ACL_DIREC_IN, FAL_ACL_BIND_PORT, S17_CPU_PORT ); - for (i = S17_LAN_PORT0; i <= S17_LAN_PORT4; i++) { - if (i != S17_WAN_PORT) - ACL_LIST_BIND ( 0, S17_ACL_LIST_UPNP_SSDP, FAL_ACL_DIREC_IN, FAL_ACL_BIND_PORT, i ); - } - - if (ACL_STATUS_GET(0, &val) == SW_OK) - { - if (val != A_TRUE) - { - aos_printk("ACL is not yet enabled. Enabling... \n"); - ACL_STATUS_SET(0, A_TRUE); - } - } -} - -void filter_power_cord_acl_rules(void) -{ - fal_acl_rule_t myacl; - uint32_t rtnval; - a_bool_t val; - - aos_printk("Adding ACL rules %d - %s\n", S17_ACL_LIST_PLC_FILTER, __func__); - - memset ( &myacl, 0, sizeof ( fal_acl_rule_t ) ); - myacl.rule_type = FAL_ACL_RULE_MAC; - - myacl.ethtype_val = 0x88e1; - myacl.ethtype_mask = 0xffff; - - /* ACL action destination port PLC port */ - myacl.ports = (1 << S17_CPU_PORT) | (1 << 6); - - /* Set pattern type*/ - memset ( &myacl.field_flg, 0, sizeof ( myacl.field_flg ) ); - FAL_FIELD_FLG_SET ( myacl.field_flg, FAL_ACL_FIELD_MAC_ETHTYPE ); // set ethtype as pattern - - /* Set action type*/ - memset ( &myacl.action_flg, 0, sizeof ( myacl.action_flg ) ); - FAL_ACTION_FLG_SET ( myacl.action_flg, FAL_ACL_ACTION_REDPT); // set action as DENY, FAL_ACL_ACTION_DENY - - /* - memcpy ( myacl.dest_mac_val.uc, mac, 6 ); - memcpy ( myacl.dest_mac_mask.uc, mac_mask, 6 ); - FAL_FIELD_FLG_SET ( myacl.field_flg, FAL_ACL_FIELD_MAC_DA ); - */ - - rtnval = ACL_LIST_CREATE (0, S17_ACL_LIST_PLC_FILTER, S17_ACL_LIST_PRIO_HIGH); - if(rtnval != SW_OK) - { - aos_printk ( "filter_power_cord_acl_rules: ACL_LIST_CREATE ERROR (%d)\n",rtnval ); - return; - } - - rtnval = ACL_RULE_ADD ( 0, S17_ACL_LIST_PLC_FILTER, 0, 1, &myacl ); - if ( rtnval != SW_OK ) - { - aos_printk ( "filter_power_cord_acl_rules: ACL_RULE_ADD ERROR...(%d)\n", rtnval ); - return; - } - - // ACL pattern source port - ACL_LIST_BIND ( 0, S17_ACL_LIST_PLC_FILTER, FAL_ACL_DIREC_IN, FAL_ACL_BIND_PORT, S17_CPU_PORT); - ACL_LIST_BIND ( 0, S17_ACL_LIST_PLC_FILTER, FAL_ACL_DIREC_IN, FAL_ACL_BIND_PORT, 6); - - if ( ACL_STATUS_GET ( 0, &val ) == SW_OK ) - { - if ( val != A_TRUE ) - { - aos_printk ( "ACL is not yet enabled. Enabling... \n" ); - ACL_STATUS_SET ( 0, A_TRUE ); - } - } -} - -/* enable pppoe_passthrough by default */ -static int isis_pppoe_passthrough = 0; - -unsigned int isis_pppoe_passthrough_process(struct sk_buff *skb, aos_header_t *athr_header) -{ - unsigned char *smac = &skb->data[6]; - - if ( isis_pppoe_passthrough == 0 ) - return -1; - - if ( ( ( skb->data[20] == 0x88 && ( skb->data[21] == 0x63 ) ) || ( skb->data[16] == 0x88 && ( skb->data[17] == 0x63 ) ) ) - && ( athr_header->sport != S17_WAN_PORT ) ) - { - pppoe_passthrough_acl_rules ( 0, smac ); - } - - return 0; -} - -unsigned int isis_set_pppoe_passthrough ( int enable ) -{ - if ( enable ) - isis_pppoe_passthrough = 1; - else - isis_pppoe_passthrough = 0; - - printk ( "## isis_set_pppoe_passthrough %s !\n", enable != 0 ? "enabled" : "disabled" ); - - return 0; -} - -unsigned int isis_enable_pppoe_discovery_acl(void) -{ -#if 0 - printk ( "## isis_enable_pppoe_discovery_acl !\n"); - - athrs17_reg_write ( MOD_ENABLE_OFFSET, athrs17_reg_read ( MOD_ENABLE_OFFSET ) | ( 1 << MOD_ENABLE_ACL_EN_BOFFSET ) ); - printk ( "athrs17_reg_write(MOD_ENABLE_OFFSET) = 0x%08x\n", athrs17_reg_read ( MOD_ENABLE_OFFSET ) ); -#endif - return 0; -} - - -int pppoe_passthrough_acl_rules(uint32_t gw_entry_id, unsigned char *mac) -{ - fal_acl_rule_t myacl; - uint32_t rtnval; - a_bool_t val; - uint32_t rule_list_id; - unsigned char mac_mask[6] = { 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}; - int i; - - if (isis_pppoe_passthrough > MAX_PPPOE_PASSTHROUGH_NUM) - { - aos_printk("Support %d PPPoE passthrough hosts only... \n", MAX_PPPOE_PASSTHROUGH_NUM); - return -1; - } - - { - /* lan -> wan, pppoe discovery */ - rule_list_id = S17_ACL_LIST_PPPOE_PASSTHROUGH_LAN_TO_WAN + (isis_pppoe_passthrough - 1) * 2; - printk ( "creating ACL list_id: %d \n", rule_list_id ); - - memset ( &myacl, 0, sizeof ( fal_acl_rule_t ) ); - myacl.rule_type = FAL_ACL_RULE_MAC; - memcpy ( myacl.src_mac_val.uc, mac, 6 ); - memcpy ( myacl.src_mac_mask.uc, mac_mask, 6 ); - myacl.ethtype_val = 0x8863; - myacl.ethtype_mask = 0xffff; - - myacl.ports = (1 << S17_WAN_PORT); - - memset ( &myacl.field_flg, 0, sizeof ( myacl.field_flg ) ); - - FAL_FIELD_FLG_SET ( myacl.field_flg, FAL_ACL_FIELD_MAC_SA ); - FAL_FIELD_FLG_SET ( myacl.field_flg, FAL_ACL_FIELD_MAC_ETHTYPE ); - - memset ( &myacl.action_flg, 0, sizeof ( myacl.action_flg ) ); - - FAL_ACTION_FLG_SET ( myacl.action_flg, FAL_ACL_ACTION_REDPT ); - - rtnval = ACL_LIST_CREATE (0, rule_list_id, S17_ACL_LIST_PRIO_MID); - if ( rtnval != SW_OK ) - { - aos_printk ( "pppoe_passthrough_acl_rules: ACL_LIST_CREATE ERROR (%d)\n",rtnval ); - return -1; - } - - rtnval = ACL_RULE_ADD ( 0, rule_list_id, 0, 1, &myacl ); - if ( rtnval != SW_OK ) - { - aos_printk ( "pppoe_passthrough_acl_rules: ACL_RULE_ADD ERROR...(%d)\n", rtnval ); - return -1; - } - - for (i = S17_LAN_PORT0; i <= S17_LAN_PORT4; i++) { - if (i != S17_WAN_PORT) - ACL_LIST_BIND ( 0, rule_list_id, FAL_ACL_DIREC_IN, FAL_ACL_BIND_PORT, i); - } - - } - - { - /* lan -> wan, pppoe session */ - rule_list_id = S17_ACL_LIST_PPPOE_PASSTHROUGH_LAN_TO_WAN + (isis_pppoe_passthrough - 1) * 2 + 1; - - printk ( "creating ACL list_id: %d \n", rule_list_id ); - - memset ( &myacl, 0, sizeof ( fal_acl_rule_t ) ); - myacl.rule_type = FAL_ACL_RULE_MAC; - memcpy ( myacl.src_mac_val.uc, mac, 6 ); - memcpy ( myacl.src_mac_mask.uc, mac_mask, 6 ); - - myacl.ethtype_val = 0x8864; - myacl.ethtype_mask = 0xffff; - - myacl.ports = ( 1< -#include -#else -#include -#endif -#include -#include -#include -#ifdef KVER32 -#include -#endif -#include -#include -#include -#include -#include -#include -#include -#include "nat_helper.h" -#include "napt_acl.h" - -#include "lib/nat_helper_hsl.h" - -extern struct net init_net; -static struct task_struct *ct_task; - -/*#undef HNAT_PRINTK -#define HNAT_PRINTK(x...) aos_printk(x)*/ - -#ifdef KVER32 -extern void __rcu_read_lock(void); -extern void __rcu_read_unlock(void); -extern unsigned int nf_conntrack_htable_size; -#endif - -a_bool_t napt_aging_ctrl_en = 0; - -void -napt_ct_aging_disable(uint32_t ct_addr) -{ - struct nf_conn *ct = NULL; - if(nf_athrs17_hnat_sync_counter_en || !napt_aging_ctrl_en) - return; - - if(!ct_addr) - { - return; - } - - ct = (struct nf_conn *)ct_addr; - - if (timer_pending(&ct->timeout)) - { - del_timer(&ct->timeout); - } -} - -int -napt_ct_aging_is_enable(uint32_t ct_addr) -{ - struct nf_conn *ct = NULL; - if(!ct_addr) - { - return 0; - } - - if(nf_athrs17_hnat_sync_counter_en || !napt_aging_ctrl_en) - return 0; - - ct = (struct nf_conn *)ct_addr; - - return timer_pending(&(((struct nf_conn *)ct)->timeout)); -} - -void -napt_ct_aging_enable(uint32_t ct_addr) -{ - struct nf_conn *ct = NULL; - uint16_t l3num = 0; - uint8_t protonum = 0; - if(nf_athrs17_hnat_sync_counter_en || !napt_aging_ctrl_en) - return; - - if(!ct_addr) - { - return; - } - - if(napt_ct_aging_is_enable(ct_addr)) - { - return; - } - - ct = (struct nf_conn *)ct_addr; - l3num = ct->tuplehash[IP_CT_DIR_ORIGINAL].tuple.src.l3num; - protonum = ct->tuplehash[IP_CT_DIR_ORIGINAL].tuple.dst.protonum; - - ct->timeout.expires = jiffies+10*HZ; - - if ((l3num == AF_INET) && (protonum == IPPROTO_TCP)) - { - if (ct->proto.tcp.state == TCP_CONNTRACK_ESTABLISHED) - { - ct->timeout.expires = jiffies+(5*24*60*60*HZ); - } - } - - HNAT_PRINTK(" ct:[%x] add timeout again\n", ct_addr); - add_timer(&ct->timeout); -} - -void -napt_ct_to_hw_entry(uint32_t ct_addr, napt_entry_t *napt) -{ - struct nf_conn *ct = NULL; - struct nf_conntrack_tuple *org_tuple, *rep_tuple; - uint8_t protonum = 0; - - if(!ct_addr) - { - return; - } - -#define NAPT_AGE 0xe - - ct = (struct nf_conn *)ct_addr; - - if ((ct->status & IPS_NAT_MASK) == IPS_SRC_NAT) //snat - { - org_tuple = &(ct->tuplehash[IP_CT_DIR_ORIGINAL].tuple); - rep_tuple = &(ct->tuplehash[IP_CT_DIR_REPLY].tuple); - - } - else //dnat - { - org_tuple = &(ct->tuplehash[IP_CT_DIR_REPLY].tuple); - rep_tuple = &(ct->tuplehash[IP_CT_DIR_ORIGINAL].tuple); - } - - protonum = org_tuple->dst.protonum; - - if(org_tuple->src.l3num == AF_INET) - { - if(protonum == IPPROTO_TCP) - { - napt->flags = FAL_NAT_ENTRY_PROTOCOL_TCP; - - } - else if(protonum == IPPROTO_UDP) - { - napt->flags = FAL_NAT_ENTRY_PROTOCOL_UDP; - - } - } - - napt->src_addr = ntohl(org_tuple->src.u3.ip); - napt->src_port = ntohs(org_tuple->src.u.all); - napt->dst_addr = ntohl(org_tuple->dst.u3.ip); - napt->dst_port = ntohs(org_tuple->dst.u.all); - napt->trans_addr = ntohl(rep_tuple->dst.u3.ip); - napt->trans_port = ntohs(rep_tuple->dst.u.all); - napt->status = NAPT_AGE; - - return; -} - -uint64_t -napt_ct_pkts_get(uint32_t ct_addr) -{ - struct nf_conn *ct = NULL; - struct nf_conn_counter *cct = NULL; - if(!ct_addr) - { - return 0; - } - - ct = (struct nf_conn *)ct_addr; - cct = (struct nf_conn_counter *)nf_conn_acct_find(ct); - - if(cct) - { - return (atomic64_read(&cct[IP_CT_DIR_ORIGINAL].packets) + - atomic64_read(&cct[IP_CT_DIR_REPLY].packets)); - } - else - { - return 0; - } -} - -int -napt_ct_type_is_nat(uint32_t ct_addr) -{ - struct nf_conn *ct = NULL; - if(!ct_addr) - { - return 0; - } - - ct = (struct nf_conn *)ct_addr; - - return ((IPS_NAT_MASK & (ct)->status)?1:0); -} - -int -napt_ct_type_is_nat_alg(uint32_t ct_addr) -{ - struct nf_conn *ct = NULL; - if(!ct_addr) - { - return 0; - } - ct = (struct nf_conn *)ct_addr; - return ((nfct_help(ct))?1:0); -} - -int -napt_ct_intf_is_expected(uint32_t ct_addr) -{ - struct nf_conn *ct = (struct nf_conn *)ct_addr; - struct nf_conntrack_tuple *rep_tuple; - uint32_t dst_ip; - struct net_device *dev = NULL; - - if(!ct_addr) - { - return 0; - } - - if ((ct->status & IPS_NAT_MASK) == IPS_SRC_NAT) - rep_tuple = &(ct->tuplehash[IP_CT_DIR_REPLY].tuple); - else - rep_tuple = &(ct->tuplehash[IP_CT_DIR_ORIGINAL].tuple); - dst_ip = rep_tuple->dst.u3.ip; - dev = ip_dev_find(&init_net, dst_ip); - if(dev) { - if(dev->type == ARPHRD_ETHER) { - if(strstr(dev->name, "eth0") || strstr(dev->name, "erouter0") || - strstr(dev->name, "br-wan")) { - dev_put(dev); - return 1; - } - } else if (dev->type == ARPHRD_PPP) { - dev_put(dev); - return 1; - } - dev_put(dev); - } - - return 0; -} - -int -napt_ct_status_is_estab(uint32_t ct_addr) -{ - struct nf_conn *ct = NULL; - uint16_t l3num = 0; - uint8_t protonum = 0; - - if(!ct_addr) - { - return 0; - } - - ct = (struct nf_conn *)ct_addr; - l3num = ct->tuplehash[IP_CT_DIR_ORIGINAL].tuple.src.l3num; - protonum = ct->tuplehash[IP_CT_DIR_ORIGINAL].tuple.dst.protonum; - - if ((l3num == AF_INET) && (protonum == IPPROTO_TCP)) - { - if (ct->proto.tcp.state == TCP_CONNTRACK_ESTABLISHED) - { - return 1; - } - } - else if ((l3num == AF_INET) && (protonum == IPPROTO_UDP)) - { - return 1; - } - - return 0; -} - -uint32_t -napt_ct_priv_ip_get(uint32_t ct_addr) -{ - struct nf_conn *ct = NULL; - uint32_t usaddr = 0; - - if(!ct_addr) - { - return 0; - } - - ct = (struct nf_conn *)ct_addr; - - if ((ct->status & IPS_NAT_MASK) == IPS_SRC_NAT) //snat - { - usaddr = ct->tuplehash[IP_CT_DIR_ORIGINAL].tuple.src.u3.ip; - } - else - { - usaddr = ct->tuplehash[IP_CT_DIR_REPLY].tuple.src.u3.ip; - } - - usaddr = ntohl(usaddr); - - return usaddr; -} - -void -napt_ct_list_lock(void) -{ - rcu_read_lock(); -} - -void -napt_ct_list_unlock(void) -{ - rcu_read_unlock(); -} - -uint32_t -napt_ct_list_iterate(uint32_t *hash, uint32_t *iterate) -{ - struct net *net = &init_net; - struct nf_conntrack_tuple_hash *h = NULL; - struct nf_conn *ct = NULL; - struct hlist_nulls_node *pos = (struct hlist_nulls_node *) (*iterate); - - while(*hash < nf_conntrack_htable_size) - { - if(pos == 0) - { - /*get head for list*/ - pos = rcu_dereference((&net->ct.hash[*hash])->first); - } - - hlist_nulls_for_each_entry_from(h, pos, hnnode) - { - (*iterate) = (uint32_t)(pos->next); - ct = nf_ct_tuplehash_to_ctrack(h); - return (uint32_t) ct; - } - - ++(*hash); - pos = 0; - } - - *hash = 0; - return 0; -} - -int -napt_ct_task_should_stop(void) -{ - return kthread_should_stop(); -} - -void -napt_ct_task_start(int (*task)(void*), const char *task_name) -{ - ct_task = kthread_create(task, NULL, task_name); - - if(IS_ERR(ct_task)) - { - aos_printk("thread: %s create fail\n", task_name); - return; - } - - wake_up_process(ct_task); - - HNAT_PRINTK("thread: %s create success pid:%d\n", - task_name, ct_task->pid); -} - -void -napt_ct_task_stop(void) -{ - if(ct_task) - { - kthread_stop(ct_task); - } -} - -void -napt_ct_task_sleep(int secs) -{ - msleep_interruptible(secs*1000); -} diff --git a/feeds/ipq807x/qca-ssdk/src/app/nathelper/linux/napt_helper.h b/feeds/ipq807x/qca-ssdk/src/app/nathelper/linux/napt_helper.h deleted file mode 100755 index 4cd21a90b..000000000 --- a/feeds/ipq807x/qca-ssdk/src/app/nathelper/linux/napt_helper.h +++ /dev/null @@ -1,91 +0,0 @@ -/* - * Copyright (c) 2012, 2015, The Linux Foundation. All rights reserved. - * Permission to use, copy, modify, and/or distribute this software for - * any purpose with or without fee is hereby granted, provided that the - * above copyright notice and this permission notice appear in all copies. - * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES - * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR - * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES - * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN - * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT - * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. - */ - - -#ifndef _NAPT_HELPER_H -#define _NAPT_HELPER_H - - - -#define USING_LINUX2631 1 - -#ifdef USING_LINUX2631 - -void -napt_ct_task_start(int (*task)(void*), const char *task_name); -void -napt_ct_task_stop(void); -int -napt_ct_task_should_stop(void); -void -napt_ct_task_sleep(int secs); -void -napt_ct_list_lock(void); -void -napt_ct_list_unlock(void); -uint32_t -napt_ct_list_iterate(uint32_t *hash, uint32_t *pos) ; -void -napt_ct_to_hw_entry(uint32_t ct_addr, void *napt); -void -napt_ct_aging_enable(uint32_t ct_addr); -void -napt_ct_aging_disable(uint32_t ct_addr); -int -napt_ct_aging_is_enable(uint32_t ct_addr); -uint64_t -napt_ct_pkts_get(uint32_t ct_addr); -int -napt_ct_type_is_nat(uint32_t ct_addr); -int -napt_ct_type_is_nat_alg(uint32_t ct_addr); -int -napt_ct_status_is_estab(uint32_t ct_addr); -uint32_t -napt_ct_priv_ip_get(uint32_t ct_addr); -int -napt_ct_intf_is_expected(uint32_t ct_addr); - - - -#define NAPT_CT_TASK_START napt_ct_task_start -#define NAPT_CT_TASK_STOP napt_ct_task_stop -#define NAPT_CT_TASK_SHOULD_STOP napt_ct_task_should_stop -#define NAPT_CT_TASK_SLEEP napt_ct_task_sleep - -#define NAPT_CT_LIST_LOCK napt_ct_list_lock -#define NAPT_CT_LIST_UNLOCK napt_ct_list_unlock -#define NAPT_CT_LIST_ITERATE napt_ct_list_iterate - -#define NAPT_CT_AGING_IS_ENABLE napt_ct_aging_is_enable -#define NAPT_CT_AGING_ENABLE napt_ct_aging_enable -#define NAPT_CT_AGING_DISABLE napt_ct_aging_disable - -#define NAPT_CT_TYPE_IS_NAT napt_ct_type_is_nat -#define NAPT_CT_STATUS_IS_ESTAB napt_ct_status_is_estab -#define NAPT_CT_PRIV_IP_GET napt_ct_priv_ip_get -#define NAPT_CT_PKTS_GET napt_ct_pkts_get -#define NAPT_CT_TO_HW_ENTRY napt_ct_to_hw_entry -#define NAPT_CT_TYPE_IS_NAT_ALG napt_ct_type_is_nat_alg -#define NAPT_CT_INTF_EXPECTED napt_ct_intf_is_expected - - -#else - - - -#endif - - -#endif diff --git a/feeds/ipq807x/qca-ssdk/src/app/nathelper/linux/napt_procfs.c b/feeds/ipq807x/qca-ssdk/src/app/nathelper/linux/napt_procfs.c deleted file mode 100755 index 4f5a66482..000000000 --- a/feeds/ipq807x/qca-ssdk/src/app/nathelper/linux/napt_procfs.c +++ /dev/null @@ -1,1316 +0,0 @@ -/* - * Copyright (c) 2012, 2015, The Linux Foundation. All rights reserved. - * Permission to use, copy, modify, and/or distribute this software for - * any purpose with or without fee is hereby granted, provided that the - * above copyright notice and this permission notice appear in all copies. - * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES - * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR - * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES - * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN - * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT - * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. - */ - - -/** - * napt_procfs.c - create files in /proc - * - */ -#include -#ifdef KVER32 -#include -#else -#include -#include -#endif -#include -#include -#include -#include -#include /* for copy_from_user */ -#include "aos_types.h" - -#ifdef AUTO_UPDATE_PPPOE_INFO -#define NF_PROCFS_PERM 0444 -#else -#define NF_PROCFS_PERM 0644 -#endif - -#define ATHRS17_MAC_LEN 13 // 12+1 -#define ATHRS17_IP_LEN 9 // 8+1 -#define ATHRS17_CHAR_MAX_LEN ATHRS17_MAC_LEN - -#define NF_PROCFS_DIR "qca_switch" - -#define NF_ATHRS17_HNAT_NAME "nf_athrs17_hnat" -#define NF_ATHRS17_HNAT_WAN_TYPE_NAME "nf_athrs17_hnat_wan_type" -#define NF_ATHRS17_HNAT_PPP_ID_NAME "nf_athrs17_hnat_ppp_id" -#define NF_ATHRS17_HNAT_UDP_THRESH_NAME "nf_athrs17_hnat_udp_thresh" -#define NF_ATHRS17_HNAT_WAN_IP_NAME "nf_athrs17_hnat_wan_ip" -#define NF_ATHRS17_HNAT_PPP_PEER_IP_NAME "nf_athrs17_hnat_ppp_peer_ip" -#define NF_ATHRS17_HNAT_PPP_PEER_MAC_NAME "nf_athrs17_hnat_ppp_peer_mac" -#define NF_ATHRS17_HNAT_WAN_MAC_NAME "nf_athrs17_hnat_wan_mac" - -#define NF_ATHRS17_HNAT_PPP_ID2_NAME "nf_athrs17_hnat_ppp_id2" -#define NF_ATHRS17_HNAT_PPP_PEER_MAC2_NAME "nf_athrs17_hnat_ppp_peer_mac2" - -/* for PPPoE */ -int nf_athrs17_hnat = 1; -int nf_athrs17_hnat_wan_type = 0; -int nf_athrs17_hnat_ppp_id = 0; -int nf_athrs17_hnat_udp_thresh = 0; -a_uint32_t nf_athrs17_hnat_wan_ip = 0; -a_uint32_t nf_athrs17_hnat_ppp_peer_ip = 0; -unsigned char nf_athrs17_hnat_ppp_peer_mac[ETH_ALEN] = {0}; -unsigned char nf_athrs17_hnat_wan_mac[ETH_ALEN] = {0}; -extern int nf_athrs17_hnat_sync_counter_en; -extern char hnat_log_en; -extern int scan_period; -extern int scan_enable; -extern int napt_need_clean; -extern int wan_switch; -extern char nat_wan_port; -extern a_uint32_t packet_thres_base; -extern a_uint32_t polling_quota; -extern a_bool_t napt_add_bypass_check; -extern void napt_wan_switch_prehandle(void); -/* for IPv6 over PPPoE (only for S17c)*/ -int nf_athrs17_hnat_ppp_id2 = 0; -unsigned char nf_athrs17_hnat_ppp_peer_mac2[ETH_ALEN] = {0}; - -#if 0 -static void setup_proc_entry(void) -{ - nf_athrs17_hnat = 1; - nf_athrs17_hnat_wan_type = 0; - nf_athrs17_hnat_ppp_id = 0; - memset(&nf_athrs17_hnat_ppp_peer_mac, 0, ETH_ALEN); - memset(&nf_athrs17_hnat_wan_mac, 0, ETH_ALEN); - nf_athrs17_hnat_ppp_peer_ip = 0; - nf_athrs17_hnat_wan_ip = 0; - - nf_athrs17_hnat_ppp_id2 = 0; - memset(&nf_athrs17_hnat_ppp_peer_mac2, 0, ETH_ALEN); - nf_athrs17_hnat_sync_counter_en = 0; -} - -/** - * This structure hold information about the /proc file - * - */ -static struct proc_dir_entry *qca_switch_dir; - -static struct proc_dir_entry *nf_athrs17_hnat_file; -static struct proc_dir_entry *nf_athrs17_hnat_wan_type_file; -static struct proc_dir_entry *nf_athrs17_hnat_ppp_id_file; -static struct proc_dir_entry *nf_athrs17_hnat_udp_thresh_file; -static struct proc_dir_entry *nf_athrs17_hnat_wan_ip_file; -static struct proc_dir_entry *nf_athrs17_hnat_ppp_peer_ip_file; -static struct proc_dir_entry *nf_athrs17_hnat_ppp_peer_mac_file; -static struct proc_dir_entry *nf_athrs17_hnat_wan_mac_file; - -static struct proc_dir_entry *nf_athrs17_hnat_ppp_id2_file; -static struct proc_dir_entry *nf_athrs17_hnat_ppp_peer_mac2_file; - -/** - * This function is called then the /proc file is read - * - */ -static int procfile_read_int(char *page, char **start, off_t off, int count, int *eof, void *data) -{ - int ret; - int *prv_data = (int *)data; - - ret = snprintf(page, sizeof(int), "%d\n", *prv_data); - - return ret; -} - -static int procfile_read_ip(char *page, char **start, off_t off, int count, int *eof, void *data) -{ - int ret; - unsigned char *prv_data = (unsigned char *)data; - - ret = snprintf(page, sizeof(a_uint32_t), "%d.%d.%d.%d\n", prv_data[0], prv_data[1], prv_data[2], prv_data[3]); - - return ret; -} - -static int procfile_read_mac(char *page, char **start, off_t off, int count, int *eof, void *data) -{ - int ret; - unsigned char *prv_data = (unsigned char *)data; - unsigned long long *ptr_ull; - - ret = snprintf(page, sizeof(unsigned char)*ETH_ALEN, "%.2x-%.2x-%.2x-%.2x-%.2x-%.2x\n", - prv_data[0], prv_data[1], prv_data[2], prv_data[3], prv_data[4], prv_data[5]); - - ptr_ull = (unsigned long long *)prv_data; - - return ret; -} - -/** - * This function is called with the /proc file is written - * - */ -#ifdef AUTO_UPDATE_PPPOE_INFO -#define procfile_write_int NULL -#define procfile_write_ip NULL -#define procfile_write_mac NULL -#else -static int procfile_write_int(struct file *file, const char *buffer, unsigned long count, void *data) -{ - int len; - uint8_t tmp_buf[9] = {'0', '0', '0', '0', '0', '0', '0', '0', '0'}; - unsigned int *prv_data = (unsigned int *)data; - int res = 0; - - if(count > sizeof(tmp_buf)) - len = sizeof(tmp_buf); - else - len = count; - - if(copy_from_user(tmp_buf, buffer, len)) - return -EFAULT; - - tmp_buf[len-1] = '\0'; - res = kstrtol((const char *)tmp_buf, 10, prv_data); - if(res < 0) - return res; - - // printk("[write] prv_data 0x%p -> 0x%08x\n", prv_data, *prv_data); - - return len; -} - -static int procfile_write_ip(struct file *file, const char *buffer, unsigned long count, void *data) -{ - int ret; - int len; - unsigned char tmp_buf[ATHRS17_IP_LEN]; - unsigned long *prv_data = (unsigned long *)data; - int res = 0; - - if(count > ATHRS17_IP_LEN) - len = ATHRS17_IP_LEN; - else - len = count; - - if(copy_from_user(tmp_buf, buffer, len)) - return -EFAULT; - - tmp_buf[len-1] = '\0'; - - res = kstrtol((const char *)tmp_buf, 16, prv_data); - if(res < 0) - return res; - - return ret; -} - -static int procfile_write_mac(struct file *file, const char *buffer, unsigned long count, void *data) -{ - int ret; - int len; - unsigned char tmp_buf[ATHRS17_MAC_LEN]; - unsigned char *ptr_char; - unsigned long long *prv_data = (unsigned long long *)data; - int res = 0; - - if(count > ATHRS17_MAC_LEN) - len = ATHRS17_MAC_LEN; - else - len = count; - - if(copy_from_user((void *)tmp_buf, buffer, len)) - return -EFAULT; - - tmp_buf[len-1] = 't'; - - res = kstrtoll((const char *)tmp_buf, 16, prv_data); - if(res < 0) - return res; - *prv_data = cpu_to_be64p(prv_data); - ptr_char = (unsigned char *)prv_data; - ptr_char[0] = ptr_char[2]; - ptr_char[1] = ptr_char[3]; - ptr_char[2] = ptr_char[4]; - ptr_char[3] = ptr_char[5]; - ptr_char[4] = ptr_char[6]; - ptr_char[5] = ptr_char[7]; - - return ret; -} -#endif // ifdef AUTO_UPDATE_PPPOE_INFO - - -int napt_procfs_init(void) -{ - int ret = 0; - - setup_proc_entry(); - - /* create directory */ - qca_switch_dir = proc_mkdir(NF_PROCFS_DIR, NULL); - if(qca_switch_dir == NULL) - { - ret = -ENOMEM; - goto err_out; - } - - /* create the /proc file */ - nf_athrs17_hnat_file = create_proc_entry(NF_ATHRS17_HNAT_NAME, 0644, qca_switch_dir); - if (NULL == nf_athrs17_hnat_file) - { - printk("Error: Can not create /proc/%s/%s\n", NF_PROCFS_DIR, NF_ATHRS17_HNAT_NAME); - goto no_athrs17_hnat; - } - nf_athrs17_hnat_file->data = &nf_athrs17_hnat; - nf_athrs17_hnat_file->read_proc = procfile_read_int; - nf_athrs17_hnat_file->write_proc = procfile_write_int; - printk("/proc/%s/%s is created\n", NF_PROCFS_DIR, NF_ATHRS17_HNAT_NAME); - - nf_athrs17_hnat_wan_type_file = create_proc_entry(NF_ATHRS17_HNAT_WAN_TYPE_NAME, NF_PROCFS_PERM, qca_switch_dir); - if (NULL == nf_athrs17_hnat_wan_type_file) - { - printk("Error: Can not create /proc/%s/%s\n", NF_PROCFS_DIR, NF_ATHRS17_HNAT_WAN_TYPE_NAME); - goto no_athrs17_hnat_wan_type; - } - nf_athrs17_hnat_wan_type_file->data = &nf_athrs17_hnat_wan_type; - nf_athrs17_hnat_wan_type_file->read_proc = procfile_read_int; - nf_athrs17_hnat_wan_type_file->write_proc = procfile_write_int; - printk("/proc/%s/%s is created\n", NF_PROCFS_DIR, NF_ATHRS17_HNAT_WAN_TYPE_NAME); - - nf_athrs17_hnat_ppp_id_file = create_proc_entry(NF_ATHRS17_HNAT_PPP_ID_NAME, NF_PROCFS_PERM, qca_switch_dir); - if (NULL == nf_athrs17_hnat_ppp_id_file) - { - printk("Error: Can not create /proc/%s/%s\n", NF_PROCFS_DIR, NF_ATHRS17_HNAT_PPP_ID_NAME); - goto no_athrs17_hnat_ppp_id; - } - nf_athrs17_hnat_ppp_id_file->data = &nf_athrs17_hnat_ppp_id; - nf_athrs17_hnat_ppp_id_file->read_proc = procfile_read_int; - nf_athrs17_hnat_ppp_id_file->write_proc = procfile_write_int; - printk("/proc/%s/%s is created\n", NF_PROCFS_DIR, NF_ATHRS17_HNAT_PPP_ID_NAME); - - nf_athrs17_hnat_udp_thresh_file = create_proc_entry(NF_ATHRS17_HNAT_UDP_THRESH_NAME, NF_PROCFS_PERM, qca_switch_dir); - if (NULL == nf_athrs17_hnat_udp_thresh_file) - { - printk("Error: Can not create /proc/%s/%s\n", NF_PROCFS_DIR, NF_ATHRS17_HNAT_UDP_THRESH_NAME); - goto no_athrs17_hnat_udp_thresh; - } - nf_athrs17_hnat_udp_thresh_file->data = &nf_athrs17_hnat_udp_thresh; - nf_athrs17_hnat_udp_thresh_file->read_proc = procfile_read_int; - nf_athrs17_hnat_udp_thresh_file->write_proc = procfile_write_int; - printk("/proc/%s/%s is created\n", NF_PROCFS_DIR, NF_ATHRS17_HNAT_UDP_THRESH_NAME); - - nf_athrs17_hnat_wan_ip_file = create_proc_entry(NF_ATHRS17_HNAT_WAN_IP_NAME, NF_PROCFS_PERM, qca_switch_dir); - if (NULL == nf_athrs17_hnat_wan_ip_file) - { - printk("Error: Can not create /proc/%s/%s\n", NF_PROCFS_DIR, NF_ATHRS17_HNAT_WAN_IP_NAME); - goto no_athrs17_hnat_wan_ip; - } - nf_athrs17_hnat_wan_ip_file->data = &nf_athrs17_hnat_wan_ip; - nf_athrs17_hnat_wan_ip_file->read_proc = procfile_read_ip; - nf_athrs17_hnat_wan_ip_file->write_proc = procfile_write_ip; - printk("/proc/%s/%s is created\n", NF_PROCFS_DIR, NF_ATHRS17_HNAT_WAN_IP_NAME); - - nf_athrs17_hnat_ppp_peer_ip_file = create_proc_entry(NF_ATHRS17_HNAT_PPP_PEER_IP_NAME, NF_PROCFS_PERM, qca_switch_dir); - if (NULL == nf_athrs17_hnat_ppp_peer_ip_file) - { - printk("Error: Can not create /proc/%s/%s\n", NF_PROCFS_DIR, NF_ATHRS17_HNAT_PPP_PEER_IP_NAME); - goto no_athrs17_hnat_ppp_peer_ip; - } - nf_athrs17_hnat_ppp_peer_ip_file->data = &nf_athrs17_hnat_ppp_peer_ip; - nf_athrs17_hnat_ppp_peer_ip_file->read_proc = procfile_read_ip; - nf_athrs17_hnat_ppp_peer_ip_file->write_proc = procfile_write_ip; - printk("/proc/%s/%s is created\n", NF_PROCFS_DIR, NF_ATHRS17_HNAT_PPP_PEER_IP_NAME); - - nf_athrs17_hnat_ppp_peer_mac_file = create_proc_entry(NF_ATHRS17_HNAT_PPP_PEER_MAC_NAME, NF_PROCFS_PERM, qca_switch_dir); - if (NULL == nf_athrs17_hnat_ppp_peer_mac_file) - { - printk("Error: Can not create /proc/%s/%s\n", NF_PROCFS_DIR, NF_ATHRS17_HNAT_PPP_PEER_MAC_NAME); - goto no_athrs17_hnat_ppp_peer_mac; - } - nf_athrs17_hnat_ppp_peer_mac_file->data = &nf_athrs17_hnat_ppp_peer_mac; - nf_athrs17_hnat_ppp_peer_mac_file->read_proc = procfile_read_mac; - nf_athrs17_hnat_ppp_peer_mac_file->write_proc = procfile_write_mac; - printk("/proc/%s/%s is created\n", NF_PROCFS_DIR, NF_ATHRS17_HNAT_PPP_PEER_MAC_NAME); - - nf_athrs17_hnat_wan_mac_file = create_proc_entry(NF_ATHRS17_HNAT_WAN_MAC_NAME, NF_PROCFS_PERM, qca_switch_dir); - if (NULL == nf_athrs17_hnat_wan_mac_file) - { - printk("Error: Can not create /proc/%s/%s\n", NF_PROCFS_DIR, NF_ATHRS17_HNAT_WAN_MAC_NAME); - goto no_athrs17_hnat_wan_mac; - } - nf_athrs17_hnat_wan_mac_file->data = &nf_athrs17_hnat_wan_mac; - nf_athrs17_hnat_wan_mac_file->read_proc = procfile_read_mac; - nf_athrs17_hnat_wan_mac_file->write_proc = procfile_write_mac; - printk("/proc/%s/%s is created\n", NF_PROCFS_DIR, NF_ATHRS17_HNAT_WAN_MAC_NAME); - - nf_athrs17_hnat_ppp_id2_file = create_proc_entry(NF_ATHRS17_HNAT_PPP_ID2_NAME, NF_PROCFS_PERM, qca_switch_dir); - if (NULL == nf_athrs17_hnat_ppp_id2_file) - { - printk("Error: Can not create /proc/%s/%s\n", NF_PROCFS_DIR, NF_ATHRS17_HNAT_PPP_ID2_NAME); - goto no_athrs17_hnat_ppp_id; - } - nf_athrs17_hnat_ppp_id2_file->data = &nf_athrs17_hnat_ppp_id2; - nf_athrs17_hnat_ppp_id2_file->read_proc = procfile_read_int; - nf_athrs17_hnat_ppp_id2_file->write_proc = procfile_write_int; - printk("/proc/%s/%s is created\n", NF_PROCFS_DIR, NF_ATHRS17_HNAT_PPP_ID2_NAME); - - nf_athrs17_hnat_ppp_peer_mac2_file = create_proc_entry(NF_ATHRS17_HNAT_PPP_PEER_MAC2_NAME, NF_PROCFS_PERM, qca_switch_dir); - if (NULL == nf_athrs17_hnat_ppp_peer_mac2_file) - { - printk("Error: Can not create /proc/%s/%s\n", NF_PROCFS_DIR, NF_ATHRS17_HNAT_PPP_PEER_MAC2_NAME); - goto no_athrs17_hnat_ppp_peer_mac; - } - nf_athrs17_hnat_ppp_peer_mac2_file->data = &nf_athrs17_hnat_ppp_peer_mac2; - nf_athrs17_hnat_ppp_peer_mac2_file->read_proc = procfile_read_mac; - nf_athrs17_hnat_ppp_peer_mac2_file->write_proc = procfile_write_mac; - printk("/proc/%s/%s is created\n", NF_PROCFS_DIR, NF_ATHRS17_HNAT_PPP_PEER_MAC_NAME); - - return 0; - -no_athrs17_hnat_wan_mac: - remove_proc_entry(NF_ATHRS17_HNAT_PPP_PEER_MAC_NAME, qca_switch_dir); -no_athrs17_hnat_ppp_peer_mac: - remove_proc_entry(NF_ATHRS17_HNAT_PPP_PEER_IP_NAME, qca_switch_dir); -no_athrs17_hnat_ppp_peer_ip: - remove_proc_entry(NF_ATHRS17_HNAT_WAN_IP_NAME, qca_switch_dir); -no_athrs17_hnat_wan_ip: - remove_proc_entry(NF_ATHRS17_HNAT_UDP_THRESH_NAME, qca_switch_dir); -no_athrs17_hnat_udp_thresh: - remove_proc_entry(NF_ATHRS17_HNAT_PPP_ID_NAME, qca_switch_dir); -no_athrs17_hnat_ppp_id: - remove_proc_entry(NF_ATHRS17_HNAT_WAN_TYPE_NAME, qca_switch_dir); -no_athrs17_hnat_wan_type: - remove_proc_entry(NF_ATHRS17_HNAT_NAME, qca_switch_dir); -no_athrs17_hnat: - remove_proc_entry(NF_PROCFS_DIR, NULL); -err_out: - return ret; -} - -void napt_procfs_exit(void) -{ - remove_proc_entry(NF_ATHRS17_HNAT_NAME, qca_switch_dir); - remove_proc_entry(NF_ATHRS17_HNAT_WAN_TYPE_NAME, qca_switch_dir); - remove_proc_entry(NF_ATHRS17_HNAT_PPP_ID_NAME, qca_switch_dir); - remove_proc_entry(NF_ATHRS17_HNAT_UDP_THRESH_NAME, qca_switch_dir); - remove_proc_entry(NF_ATHRS17_HNAT_WAN_IP_NAME, qca_switch_dir); - remove_proc_entry(NF_ATHRS17_HNAT_PPP_PEER_IP_NAME, qca_switch_dir); - remove_proc_entry(NF_ATHRS17_HNAT_PPP_PEER_MAC_NAME, qca_switch_dir); - remove_proc_entry(NF_ATHRS17_HNAT_WAN_MAC_NAME, qca_switch_dir); - remove_proc_entry(NF_ATHRS17_HNAT_PPP_ID2_NAME, qca_switch_dir); - remove_proc_entry(NF_ATHRS17_HNAT_PPP_PEER_MAC2_NAME, qca_switch_dir); - remove_proc_entry(NF_PROCFS_DIR, NULL); - printk(KERN_INFO "/proc/%s/%s removed\n", NF_PROCFS_DIR, NF_ATHRS17_HNAT_NAME); -} -#else -static ssize_t napt_hnat_get(struct device *dev, - struct device_attribute *attr, - char *buf) -{ - ssize_t count; - a_uint32_t num; - - num = (a_uint32_t)nf_athrs17_hnat; - - count = snprintf(buf, (ssize_t)PAGE_SIZE, "%u", num); - return count; -} - -static ssize_t napt_hnat_set(struct device *dev, - struct device_attribute *attr, - const char *buf, size_t count) -{ - char num_buf[12]; - a_uint32_t num; - - - if (count >= sizeof(num_buf)) return 0; - memcpy(num_buf, buf, count); - num_buf[count] = '\0'; - sscanf(num_buf, "%u", &num); - - nf_athrs17_hnat = num; - - return count; -} - -static ssize_t napt_wan_type_get(struct device *dev, - struct device_attribute *attr, - char *buf) -{ - ssize_t count; - a_uint32_t num; - - num = (a_uint32_t)nf_athrs17_hnat_wan_type; - - count = snprintf(buf, (ssize_t)PAGE_SIZE, "%u", num); - return count; -} - -static ssize_t napt_wan_type_set(struct device *dev, - struct device_attribute *attr, - const char *buf, size_t count) -{ - char num_buf[12]; - a_uint32_t num; - - - if (count >= sizeof(num_buf)) return 0; - memcpy(num_buf, buf, count); - num_buf[count] = '\0'; - sscanf(num_buf, "%u", &num); - - nf_athrs17_hnat_wan_type = num; - - return count; -} - -static ssize_t napt_ppp_id_get(struct device *dev, - struct device_attribute *attr, - char *buf) -{ - ssize_t count; - a_uint32_t num; - - num = (a_uint32_t)nf_athrs17_hnat_ppp_id; - - count = snprintf(buf, (ssize_t)PAGE_SIZE, "%u", num); - return count; -} - -static ssize_t napt_ppp_id_set(struct device *dev, - struct device_attribute *attr, - const char *buf, size_t count) -{ - char num_buf[12]; - a_uint32_t num; - - - if (count >= sizeof(num_buf)) return 0; - memcpy(num_buf, buf, count); - num_buf[count] = '\0'; - sscanf(num_buf, "%u", &num); - - nf_athrs17_hnat_ppp_id = num; - - return count; -} - -static ssize_t napt_udp_thresh_get(struct device *dev, - struct device_attribute *attr, - char *buf) -{ - ssize_t count; - a_uint32_t num; - - num = (a_uint32_t)nf_athrs17_hnat_udp_thresh; - - count = snprintf(buf, (ssize_t)PAGE_SIZE, "%u", num); - return count; -} - -static ssize_t napt_udp_thresh_set(struct device *dev, - struct device_attribute *attr, - const char *buf, size_t count) -{ - char num_buf[12]; - a_uint32_t num; - - - if (count >= sizeof(num_buf)) return 0; - memcpy(num_buf, buf, count); - num_buf[count] = '\0'; - sscanf(num_buf, "%u", &num); - - nf_athrs17_hnat_udp_thresh = num; - - return count; -} - -static ssize_t napt_wan_ip_get(struct device *dev, - struct device_attribute *attr, - char *buf) -{ - ssize_t count; - unsigned char* data; - - data = (unsigned char*)&nf_athrs17_hnat_wan_ip; - - count = snprintf(buf, (ssize_t)PAGE_SIZE, "%d.%d.%d.%d", - data[0], data[1], data[2], data[3]); - return count; -} - -static ssize_t napt_wan_ip_set(struct device *dev, - struct device_attribute *attr, - const char *buf, size_t count) -{ - char num_buf[12]; - a_uint32_t num; - - - if (count >= sizeof(num_buf)) return 0; - memcpy(num_buf, buf, count); - num_buf[count] = '\0'; - sscanf(num_buf, "%u", &num); - - nf_athrs17_hnat_wan_ip = num; - - return count; -} - -static ssize_t napt_ppp_peer_ip_get(struct device *dev, - struct device_attribute *attr, - char *buf) -{ - ssize_t count; - unsigned char* data; - - data = (unsigned char*)&nf_athrs17_hnat_ppp_peer_ip; - - count = snprintf(buf, (ssize_t)PAGE_SIZE, "%d.%d.%d.%d", - data[0], data[1], data[2], data[3]); - return count; -} - -static ssize_t napt_ppp_peer_ip_set(struct device *dev, - struct device_attribute *attr, - const char *buf, size_t count) -{ - char num_buf[12]; - a_uint32_t num; - - - if (count >= sizeof(num_buf)) return 0; - memcpy(num_buf, buf, count); - num_buf[count] = '\0'; - sscanf(num_buf, "%u", &num); - - nf_athrs17_hnat_ppp_peer_ip = num; - - return count; -} - -static ssize_t napt_peer_mac_get(struct device *dev, - struct device_attribute *attr, - char *buf) -{ - ssize_t count; - unsigned char* data; - - data = (unsigned char*)&nf_athrs17_hnat_ppp_peer_mac; - - count = snprintf(buf, (ssize_t)PAGE_SIZE, "%.2x-%.2x-%.2x-%.2x-%.2x-%.2x", - data[0], data[1], data[2], data[3], data[4], data[5]); - return count; -} - -static ssize_t napt_peer_mac_set(struct device *dev, - struct device_attribute *attr, - const char *buf, size_t count) -{ - char num_buf[32]; - unsigned long long prv_data; - unsigned char *ptr_char; - int res = 0; - - if (count >= sizeof(num_buf)) return 0; - memcpy(num_buf, buf, count); - num_buf[count] = '\0'; - res = kstrtoll((const char *)num_buf, 16, &prv_data); - if(res < 0) - return res; - - prv_data = cpu_to_be64p(&prv_data); - ptr_char = (unsigned char *)&prv_data; - nf_athrs17_hnat_ppp_peer_mac[0] = ptr_char[2]; - nf_athrs17_hnat_ppp_peer_mac[1] = ptr_char[3]; - nf_athrs17_hnat_ppp_peer_mac[2] = ptr_char[4]; - nf_athrs17_hnat_ppp_peer_mac[3] = ptr_char[5]; - nf_athrs17_hnat_ppp_peer_mac[4] = ptr_char[6]; - nf_athrs17_hnat_ppp_peer_mac[5] = ptr_char[7]; - - return count; -} - -static ssize_t napt_wan_mac_get(struct device *dev, - struct device_attribute *attr, - char *buf) -{ - ssize_t count; - unsigned char* data; - - data = (unsigned char*)&nf_athrs17_hnat_wan_mac; - - count = snprintf(buf, (ssize_t)PAGE_SIZE, "%.2x-%.2x-%.2x-%.2x-%.2x-%.2x", - data[0], data[1], data[2], data[3], data[4], data[5]); - return count; -} - -static ssize_t napt_wan_mac_set(struct device *dev, - struct device_attribute *attr, - const char *buf, size_t count) -{ - char num_buf[32]; - unsigned long long prv_data; - unsigned char *ptr_char; - int res = 0; - - if (count >= sizeof(num_buf)) return 0; - memcpy(num_buf, buf, count); - num_buf[count] = '\0'; - res = kstrtoll((const char *)num_buf, 16, &prv_data); - if(res < 0) - return res; - - prv_data = cpu_to_be64p(&prv_data); - ptr_char = (unsigned char *)&prv_data; - nf_athrs17_hnat_wan_mac[0] = ptr_char[2]; - nf_athrs17_hnat_wan_mac[1] = ptr_char[3]; - nf_athrs17_hnat_wan_mac[2] = ptr_char[4]; - nf_athrs17_hnat_wan_mac[3] = ptr_char[5]; - nf_athrs17_hnat_wan_mac[4] = ptr_char[6]; - nf_athrs17_hnat_wan_mac[5] = ptr_char[7]; - - return count; -} - -static ssize_t napt_peer_mac2_get(struct device *dev, - struct device_attribute *attr, - char *buf) -{ - ssize_t count; - unsigned char* data; - - data = (unsigned char*)&nf_athrs17_hnat_ppp_peer_mac2; - - count = snprintf(buf, (ssize_t)PAGE_SIZE, "%.2x-%.2x-%.2x-%.2x-%.2x-%.2x", - data[0], data[1], data[2], data[3], data[4], data[5]); - return count; -} - -static ssize_t napt_peer_mac2_set(struct device *dev, - struct device_attribute *attr, - const char *buf, size_t count) -{ - char num_buf[32]; - unsigned long long prv_data; - unsigned char *ptr_char; - int res = 0; - - if (count >= sizeof(num_buf)) return 0; - memcpy(num_buf, buf, count); - num_buf[count] = '\0'; - res = kstrtoll((const char *)num_buf, 16, &prv_data); - if(res < 0) - return res; - - prv_data = cpu_to_be64p(&prv_data); - ptr_char = (unsigned char *)&prv_data; - nf_athrs17_hnat_ppp_peer_mac2[0] = ptr_char[2]; - nf_athrs17_hnat_ppp_peer_mac2[1] = ptr_char[3]; - nf_athrs17_hnat_ppp_peer_mac2[2] = ptr_char[4]; - nf_athrs17_hnat_ppp_peer_mac2[3] = ptr_char[5]; - nf_athrs17_hnat_ppp_peer_mac2[4] = ptr_char[6]; - nf_athrs17_hnat_ppp_peer_mac2[5] = ptr_char[7]; - - return count; -} - -static ssize_t napt_ppp_id2_get(struct device *dev, - struct device_attribute *attr, - char *buf) -{ - ssize_t count; - a_uint32_t num; - - num = (a_uint32_t)nf_athrs17_hnat_ppp_id2; - - count = snprintf(buf, (ssize_t)PAGE_SIZE, "%u", num); - return count; -} - -static ssize_t napt_ppp_id2_set(struct device *dev, - struct device_attribute *attr, - const char *buf, size_t count) -{ - char num_buf[12]; - a_uint32_t num; - - - if (count >= sizeof(num_buf)) return 0; - memcpy(num_buf, buf, count); - num_buf[count] = '\0'; - sscanf(num_buf, "%u", &num); - - nf_athrs17_hnat_ppp_id2 = num; - - return count; -} - -static ssize_t napt_sync_counter_en_get(struct device *dev, - struct device_attribute *attr, - char *buf) -{ - ssize_t count; - a_uint32_t num; - - num = (a_uint32_t)nf_athrs17_hnat_sync_counter_en; - - count = snprintf(buf, (ssize_t)PAGE_SIZE, "%u", num); - return count; -} - -static ssize_t napt_sync_counter_en_set(struct device *dev, - struct device_attribute *attr, - const char *buf, size_t count) -{ - char num_buf[12]; - a_uint32_t num; - - - if (count >= sizeof(num_buf)) return 0; - memcpy(num_buf, buf, count); - num_buf[count] = '\0'; - sscanf(num_buf, "%u", &num); - - nf_athrs17_hnat_sync_counter_en = num; - - return count; -} - -static ssize_t napt_log_en_get(struct device *dev, - struct device_attribute *attr, - char *buf) -{ - ssize_t count; - a_uint32_t num; - - num = (a_uint32_t)hnat_log_en; - - count = snprintf(buf, (ssize_t)PAGE_SIZE, "%u", num); - return count; -} - -static ssize_t napt_log_en_set(struct device *dev, - struct device_attribute *attr, - const char *buf, size_t count) -{ - char num_buf[12]; - a_uint32_t num; - - - if (count >= sizeof(num_buf)) return 0; - memcpy(num_buf, buf, count); - num_buf[count] = '\0'; - sscanf(num_buf, "%u", &num); - - hnat_log_en = num; - - return count; -} - -static ssize_t napt_scan_period_get(struct device *dev, - struct device_attribute *attr, - char *buf) -{ - ssize_t count; - a_uint32_t num; - - num = (a_uint32_t)scan_period; - - count = snprintf(buf, (ssize_t)PAGE_SIZE, "%u", num); - return count; -} - -static ssize_t napt_scan_period_set(struct device *dev, - struct device_attribute *attr, - const char *buf, size_t count) -{ - char num_buf[12]; - a_uint32_t num; - - - if (count >= sizeof(num_buf)) return 0; - memcpy(num_buf, buf, count); - num_buf[count] = '\0'; - sscanf(num_buf, "%u", &num); - - scan_period = num; - - return count; -} - -static ssize_t napt_scan_enable_get(struct device *dev, - struct device_attribute *attr, - char *buf) -{ - ssize_t count; - a_uint32_t num; - - num = (a_uint32_t)scan_enable; - - count = snprintf(buf, (ssize_t)PAGE_SIZE, "%u", num); - return count; -} - -static ssize_t napt_scan_enable_set(struct device *dev, - struct device_attribute *attr, - const char *buf, size_t count) -{ - char num_buf[12]; - a_uint32_t num; - - - if (count >= sizeof(num_buf)) return 0; - memcpy(num_buf, buf, count); - num_buf[count] = '\0'; - sscanf(num_buf, "%u", &num); - - scan_enable = num; - - return count; -} - -static ssize_t napt_need_clean_get(struct device *dev, - struct device_attribute *attr, - char *buf) -{ - ssize_t count; - a_uint32_t num; - - num = (a_uint32_t)napt_need_clean; - - count = snprintf(buf, (ssize_t)PAGE_SIZE, "%u", num); - return count; -} - -static ssize_t napt_need_clean_set(struct device *dev, - struct device_attribute *attr, - const char *buf, size_t count) -{ - char num_buf[12]; - a_uint32_t num; - - - if (count >= sizeof(num_buf)) return 0; - memcpy(num_buf, buf, count); - num_buf[count] = '\0'; - sscanf(num_buf, "%u", &num); - - napt_need_clean = num; - - return count; -} - -static ssize_t napt_wan_switch_get(struct device *dev, - struct device_attribute *attr, - char *buf) -{ - ssize_t count; - a_uint32_t num; - - num = (a_uint32_t)wan_switch; - - count = snprintf(buf, (ssize_t)PAGE_SIZE, "%u", num); - return count; -} - -static ssize_t napt_wan_switch_set(struct device *dev, - struct device_attribute *attr, - const char *buf, size_t count) -{ - char num_buf[12]; - a_uint32_t num; - - - if (count >= sizeof(num_buf)) return 0; - memcpy(num_buf, buf, count); - num_buf[count] = '\0'; - sscanf(num_buf, "%u", &num); - - wan_switch = num; - napt_wan_switch_prehandle(); - - return count; -} - -static ssize_t napt_wan_port_get(struct device *dev, - struct device_attribute *attr, - char *buf) -{ - ssize_t count; - a_uint32_t num; - - num = (a_uint32_t)nat_wan_port; - - count = snprintf(buf, (ssize_t)PAGE_SIZE, "%u", num); - return count; -} - -static ssize_t napt_wan_port_set(struct device *dev, - struct device_attribute *attr, - const char *buf, size_t count) -{ - char num_buf[12]; - a_uint32_t num; - - - if (count >= sizeof(num_buf)) return 0; - memcpy(num_buf, buf, count); - num_buf[count] = '\0'; - sscanf(num_buf, "%u", &num); - - nat_wan_port = num; - - return count; -} - -static ssize_t napt_thresh_base_get(struct device *dev, - struct device_attribute *attr, - char *buf) -{ - ssize_t count; - a_uint32_t num; - - num = packet_thres_base; - - count = snprintf(buf, (ssize_t)PAGE_SIZE, "%u", num); - return count; -} - -static ssize_t napt_thresh_base_set(struct device *dev, - struct device_attribute *attr, - const char *buf, size_t count) -{ - char num_buf[12]; - a_uint32_t num; - - - if (count >= sizeof(num_buf)) return 0; - memcpy(num_buf, buf, count); - num_buf[count] = '\0'; - sscanf(num_buf, "%u", &num); - - packet_thres_base = num; - - return count; -} - -static ssize_t napt_polling_quota_get(struct device *dev, - struct device_attribute *attr, - char *buf) -{ - ssize_t count; - a_uint32_t num; - - num = polling_quota; - - count = snprintf(buf, (ssize_t)PAGE_SIZE, "%u", num); - return count; -} - -static ssize_t napt_polling_quota_set(struct device *dev, - struct device_attribute *attr, - const char *buf, size_t count) -{ - char num_buf[12]; - a_uint32_t num; - - - if (count >= sizeof(num_buf)) return 0; - memcpy(num_buf, buf, count); - num_buf[count] = '\0'; - sscanf(num_buf, "%u", &num); - - polling_quota = num; - - return count; -} - -static ssize_t napt_bypass_check_get(struct device *dev, - struct device_attribute *attr, - char *buf) -{ - ssize_t count; - a_uint32_t num; - - num = napt_add_bypass_check; - - count = snprintf(buf, (ssize_t)PAGE_SIZE, "%u", num); - return count; -} - -static ssize_t napt_bypass_check_set(struct device *dev, - struct device_attribute *attr, - const char *buf, size_t count) -{ - char num_buf[12]; - a_uint32_t num; - - - if (count >= sizeof(num_buf)) return 0; - memcpy(num_buf, buf, count); - num_buf[count] = '\0'; - sscanf(num_buf, "%u", &num); - - napt_add_bypass_check = num; - - return count; -} - -extern void napt_helper_show(void); -static ssize_t napt_log_show_get(struct device *dev, - struct device_attribute *attr, - char *buf) -{ - napt_helper_show(); - return 0; -} - -struct kobject *napt_sys = NULL; -static const struct device_attribute napt_hnat_attr = - __ATTR(hnat, 0660, napt_hnat_get, napt_hnat_set); -static const struct device_attribute napt_wan_type_attr = - __ATTR(wan_type, 0660, napt_wan_type_get, napt_wan_type_set); -static const struct device_attribute napt_ppp_id_attr = - __ATTR(ppp_id, 0660, napt_ppp_id_get, napt_ppp_id_set); -static const struct device_attribute napt_udp_thresh_attr = - __ATTR(udp_thresh, 0660, napt_udp_thresh_get, napt_udp_thresh_set); -static const struct device_attribute napt_wan_ip_attr = - __ATTR(wan_ip, 0660, napt_wan_ip_get, napt_wan_ip_set); -static const struct device_attribute napt_ppp_peer_ip_attr = - __ATTR(peer_ip, 0660, napt_ppp_peer_ip_get, napt_ppp_peer_ip_set); -static const struct device_attribute napt_ppp_peer_mac_attr = - __ATTR(peer_mac, 0660, napt_peer_mac_get, napt_peer_mac_set); -static const struct device_attribute napt_wan_mac_attr = - __ATTR(wan_mac, 0660, napt_wan_mac_get, napt_wan_mac_set); -static const struct device_attribute napt_ppp_id2_attr = - __ATTR(ppp_id2, 0660, napt_ppp_id2_get, napt_ppp_id2_set); -static const struct device_attribute napt_ppp_peer_mac2_attr = - __ATTR(peer_mac2, 0660, napt_peer_mac2_get, napt_peer_mac2_set); -static const struct device_attribute napt_sync_counter_en_attr = - __ATTR(sync_counter_en, 0660, napt_sync_counter_en_get, napt_sync_counter_en_set); -static const struct device_attribute napt_log_en_attr = - __ATTR(log_en, 0660, napt_log_en_get, napt_log_en_set); -static const struct device_attribute napt_log_show_attr = - __ATTR(log_show, 0660, napt_log_show_get, NULL); -static const struct device_attribute napt_scan_period_attr = - __ATTR(speriod, 0660, napt_scan_period_get, napt_scan_period_set); -static const struct device_attribute napt_scan_enable_attr = - __ATTR(scan_en, 0660, napt_scan_enable_get, napt_scan_enable_set); -static const struct device_attribute napt_need_clean_attr = - __ATTR(napt_clean, 0660, napt_need_clean_get, napt_need_clean_set); -static const struct device_attribute napt_wan_switch_attr = - __ATTR(napt_switch, 0660, napt_wan_switch_get, napt_wan_switch_set); -static const struct device_attribute napt_wan_port_attr = - __ATTR(wan_port, 0660, napt_wan_port_get, napt_wan_port_set); -static const struct device_attribute napt_thresh_base_attr = - __ATTR(thresh_base, 0660, napt_thresh_base_get, napt_thresh_base_set); -static const struct device_attribute napt_polling_quota_attr = - __ATTR(ct_quota, 0660, napt_polling_quota_get, napt_polling_quota_set); -static const struct device_attribute napt_bypass_check_attr = - __ATTR(bypass_check, 0660, napt_bypass_check_get, napt_bypass_check_set); - -int napt_procfs_init(void) -{ - int ret = 0; - - napt_sys = kobject_create_and_add("ssdk_napt", NULL); - if (!napt_sys) { - printk("napt failed to register sysfs\n "); - return ret; - } - - - - ret = sysfs_create_file(napt_sys, &napt_hnat_attr.attr); - if (ret) { - printk("Failed to register hnat SysFS file\n"); - goto CLEANUP_1; - } - ret = sysfs_create_file(napt_sys, &napt_wan_type_attr.attr); - if (ret) { - printk("Failed to register wan type SysFS file\n"); - goto CLEANUP_2; - } - ret = sysfs_create_file(napt_sys, &napt_ppp_id_attr.attr); - if (ret) { - printk("Failed to register ppp id SysFS file\n"); - goto CLEANUP_3; - } - ret = sysfs_create_file(napt_sys, &napt_udp_thresh_attr.attr); - if (ret) { - printk("Failed to register udp thresh SysFS file\n"); - goto CLEANUP_4; - } - ret = sysfs_create_file(napt_sys, &napt_wan_ip_attr.attr); - if (ret) { - printk("Failed to register wan ip SysFS file\n"); - goto CLEANUP_5; - } - ret = sysfs_create_file(napt_sys, &napt_ppp_peer_ip_attr.attr); - if (ret) { - printk("Failed to register ppp peer ip SysFS file\n"); - goto CLEANUP_6; - } - ret = sysfs_create_file(napt_sys, &napt_ppp_peer_mac_attr.attr); - if (ret) { - printk("Failed to register ppp peer mac SysFS file\n"); - goto CLEANUP_7; - } - ret = sysfs_create_file(napt_sys, &napt_wan_mac_attr.attr); - if (ret) { - printk("Failed to register wan mac SysFS file\n"); - goto CLEANUP_8; - } - ret = sysfs_create_file(napt_sys, &napt_ppp_id2_attr.attr); - if (ret) { - printk("Failed to register ppp id2 SysFS file\n"); - goto CLEANUP_9; - } - ret = sysfs_create_file(napt_sys, &napt_ppp_peer_mac2_attr.attr); - if (ret) { - printk("Failed to register ppp peer mac2 SysFS file\n"); - goto CLEANUP_10; - } - ret = sysfs_create_file(napt_sys, &napt_sync_counter_en_attr.attr); - if (ret) { - printk("Failed to register sync counter en SysFS file\n"); - goto CLEANUP_11; - } - ret = sysfs_create_file(napt_sys, &napt_log_en_attr.attr); - if (ret) { - printk("Failed to register log en SysFS file\n"); - goto CLEANUP_12; - } - ret = sysfs_create_file(napt_sys, &napt_log_show_attr.attr); - if (ret) { - printk("Failed to register log show SysFS file\n"); - goto CLEANUP_13; - } - ret = sysfs_create_file(napt_sys, &napt_scan_period_attr.attr); - if (ret) { - printk("Failed to register scan period SysFS file\n"); - goto CLEANUP_14; - } - ret = sysfs_create_file(napt_sys, &napt_scan_enable_attr.attr); - if (ret) { - printk("Failed to register scan enable SysFS file\n"); - goto CLEANUP_15; - } - ret = sysfs_create_file(napt_sys, &napt_need_clean_attr.attr); - if (ret) { - printk("Failed to register napt clean SysFS file\n"); - goto CLEANUP_16; - } - ret = sysfs_create_file(napt_sys, &napt_wan_switch_attr.attr); - if (ret) { - printk("Failed to register napt wan switch SysFS file\n"); - goto CLEANUP_17; - } - ret = sysfs_create_file(napt_sys, &napt_wan_port_attr.attr); - if (ret) { - printk("Failed to register napt wan port SysFS file\n"); - goto CLEANUP_18; - } - ret = sysfs_create_file(napt_sys, &napt_thresh_base_attr.attr); - if (ret) { - printk("Failed to register napt thresh base SysFS file\n"); - goto CLEANUP_19; - } - ret = sysfs_create_file(napt_sys, &napt_polling_quota_attr.attr); - if (ret) { - printk("Failed to register napt polling quota SysFS file\n"); - goto CLEANUP_20; - } - ret = sysfs_create_file(napt_sys, &napt_bypass_check_attr.attr); - if (ret) { - printk("Failed to register napt add check bypass SysFS file\n"); - goto CLEANUP_21; - } - return 0; -CLEANUP_21: - sysfs_remove_file(napt_sys, &napt_polling_quota_attr.attr); -CLEANUP_20: - sysfs_remove_file(napt_sys, &napt_thresh_base_attr.attr); -CLEANUP_19: - sysfs_remove_file(napt_sys, &napt_wan_port_attr.attr); -CLEANUP_18: - sysfs_remove_file(napt_sys, &napt_wan_switch_attr.attr); -CLEANUP_17: - sysfs_remove_file(napt_sys, &napt_need_clean_attr.attr); -CLEANUP_16: - sysfs_remove_file(napt_sys, &napt_scan_enable_attr.attr); -CLEANUP_15: - sysfs_remove_file(napt_sys, &napt_scan_period_attr.attr); -CLEANUP_14: - sysfs_remove_file(napt_sys, &napt_log_show_attr.attr); -CLEANUP_13: - sysfs_remove_file(napt_sys, &napt_log_en_attr.attr); -CLEANUP_12: - sysfs_remove_file(napt_sys, &napt_sync_counter_en_attr.attr); -CLEANUP_11: - sysfs_remove_file(napt_sys, &napt_ppp_peer_mac2_attr.attr); -CLEANUP_10: - sysfs_remove_file(napt_sys, &napt_ppp_id2_attr.attr); -CLEANUP_9: - sysfs_remove_file(napt_sys, &napt_wan_mac_attr.attr); -CLEANUP_8: - sysfs_remove_file(napt_sys, &napt_ppp_peer_mac_attr.attr); -CLEANUP_7: - sysfs_remove_file(napt_sys, &napt_ppp_peer_ip_attr.attr); -CLEANUP_6: - sysfs_remove_file(napt_sys, &napt_wan_ip_attr.attr); -CLEANUP_5: - sysfs_remove_file(napt_sys, &napt_udp_thresh_attr.attr); -CLEANUP_4: - sysfs_remove_file(napt_sys, &napt_ppp_id_attr.attr); -CLEANUP_3: - sysfs_remove_file(napt_sys, &napt_wan_type_attr.attr); -CLEANUP_2: - sysfs_remove_file(napt_sys, &napt_hnat_attr.attr); -CLEANUP_1: - kobject_put(napt_sys); - - return ret; -} - -void napt_procfs_exit(void) -{ - printk("napt procfs exit\n"); - - sysfs_remove_file(napt_sys, &napt_bypass_check_attr.attr); - sysfs_remove_file(napt_sys, &napt_polling_quota_attr.attr); - sysfs_remove_file(napt_sys, &napt_thresh_base_attr.attr); - sysfs_remove_file(napt_sys, &napt_wan_port_attr.attr); - sysfs_remove_file(napt_sys, &napt_wan_switch_attr.attr); - sysfs_remove_file(napt_sys, &napt_need_clean_attr.attr); - sysfs_remove_file(napt_sys, &napt_scan_enable_attr.attr); - sysfs_remove_file(napt_sys, &napt_scan_period_attr.attr); - sysfs_remove_file(napt_sys, &napt_log_show_attr.attr); - sysfs_remove_file(napt_sys, &napt_log_en_attr.attr); - sysfs_remove_file(napt_sys, &napt_sync_counter_en_attr.attr); - sysfs_remove_file(napt_sys, &napt_ppp_peer_mac2_attr.attr); - sysfs_remove_file(napt_sys, &napt_ppp_id2_attr.attr); - sysfs_remove_file(napt_sys, &napt_wan_mac_attr.attr); - sysfs_remove_file(napt_sys, &napt_ppp_peer_mac_attr.attr); - sysfs_remove_file(napt_sys, &napt_ppp_peer_ip_attr.attr); - sysfs_remove_file(napt_sys, &napt_wan_ip_attr.attr); - sysfs_remove_file(napt_sys, &napt_udp_thresh_attr.attr); - sysfs_remove_file(napt_sys, &napt_ppp_id_attr.attr); - sysfs_remove_file(napt_sys, &napt_wan_type_attr.attr); - sysfs_remove_file(napt_sys, &napt_hnat_attr.attr); - - kobject_put(napt_sys); -} - - -#endif - diff --git a/feeds/ipq807x/qca-ssdk/src/app/nathelper/linux/nat_helper.c b/feeds/ipq807x/qca-ssdk/src/app/nathelper/linux/nat_helper.c deleted file mode 100755 index 441eeab5e..000000000 --- a/feeds/ipq807x/qca-ssdk/src/app/nathelper/linux/nat_helper.c +++ /dev/null @@ -1,69 +0,0 @@ -/* - * Copyright (c) 2012, The Linux Foundation. All rights reserved. - * Permission to use, copy, modify, and/or distribute this software for - * any purpose with or without fee is hereby granted, provided that the - * above copyright notice and this permission notice appear in all copies. - * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES - * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR - * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES - * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN - * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT - * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. - */ - -#ifdef KVER32 -#include -#include -#else -#include -#endif -#include - - -#include "nat_helper.h" - -char hnat_log_en = HNAT_LOG_LEVEL_DISABLE; -char hnat_log_buffer[NAT_LOG_MAX_SIZE]; - -void hnat_log_msg(int level, char *string, ...) -{ - - va_list ptr; - - if(level < hnat_log_en) - return; - memset(hnat_log_buffer, 0, sizeof(hnat_log_buffer)); - va_start(ptr,string); - vsnprintf(hnat_log_buffer,sizeof(hnat_log_buffer), string, ptr); - va_end(ptr); - aos_printk("%s\n", hnat_log_buffer); -} - - -sw_error_t -nat_helper_init(uint32_t dev_id, uint32_t portbmp) -{ - nat_helper_bg_task_init(); - host_helper_init(portbmp); - napt_helper_init(); - nat_ipt_helper_init(); - - aos_printk("Hello, nat helper module for 1.1!\n"); - - return SW_OK; -} - -sw_error_t -nat_helper_cleanup(uint32_t dev_id) -{ - host_helper_exit(); - napt_helper_exit(); - nat_ipt_helper_exit(); - nat_helper_bg_task_exit(); - - aos_printk("Goodbye, nat helper module!\n"); - - return SW_OK; -} - diff --git a/feeds/ipq807x/qca-ssdk/src/app/nathelper/linux/nat_helper.h b/feeds/ipq807x/qca-ssdk/src/app/nathelper/linux/nat_helper.h deleted file mode 100755 index 6fad83e8f..000000000 --- a/feeds/ipq807x/qca-ssdk/src/app/nathelper/linux/nat_helper.h +++ /dev/null @@ -1,54 +0,0 @@ -/* - * Copyright (c) 2012, 2015, 2017, The Linux Foundation. All rights reserved. - * Permission to use, copy, modify, and/or distribute this software for - * any purpose with or without fee is hereby granted, provided that the - * above copyright notice and this permission notice appear in all copies. - * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES - * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR - * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES - * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN - * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT - * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. - */ - - -#ifndef _NAT_HELPER_H -#define _NAT_HELPER_H - -#include "sw.h" - -#define NAPT_TABLE_SIZE 1024 - -#define S17_WAN_PORT nat_helper_wan_port_get() - -void host_helper_init(a_uint32_t portbmp); -void host_helper_exit(void); -void napt_helper_init(void); -void napt_helper_exit(void); -void nat_ipt_helper_init(void); -void nat_ipt_helper_exit(void); - -void nat_helper_bg_task_init(void); -void nat_helper_bg_task_exit(void); - -a_uint32_t nat_helper_wan_port_get(void); -uint32_t get_next_hop(uint32_t daddr, uint32_t saddr); - -void hnat_log_msg(int level, char *string, ...); -#define NAT_LOG_MAX_SIZE 1024 -enum { - HNAT_LOG_LEVEL_DEBUG = 0, - HNAT_LOG_LEVEL_INFO, - HNAT_LOG_LEVEL_ERR, - HNAT_LOG_LEVEL_DISABLE -}; -#define HNAT_PRINTK(arg...) \ - hnat_log_msg(HNAT_LOG_LEVEL_DEBUG, arg) -#define HNAT_INFO_PRINTK(arg...) \ - hnat_log_msg(HNAT_LOG_LEVEL_INFO, arg) -#define HNAT_ERR_PRINTK(arg...) \ - hnat_log_msg(HNAT_LOG_LEVEL_ERR, arg) - - -#endif diff --git a/feeds/ipq807x/qca-ssdk/src/app/nathelper/linux/nat_ipt_helper.c b/feeds/ipq807x/qca-ssdk/src/app/nathelper/linux/nat_ipt_helper.c deleted file mode 100755 index c5918c66f..000000000 --- a/feeds/ipq807x/qca-ssdk/src/app/nathelper/linux/nat_ipt_helper.c +++ /dev/null @@ -1,761 +0,0 @@ -/* - * Copyright (c) 2012, 2015, The Linux Foundation. All rights reserved. - * Permission to use, copy, modify, and/or distribute this software for - * any purpose with or without fee is hereby granted, provided that the - * above copyright notice and this permission notice appear in all copies. - * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES - * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR - * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES - * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN - * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT - * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. - */ - - -#ifdef KVER32 -#include -#include -#else -#include -#endif -#include -#include -#include -#include -#include -#include -#include "nat_helper.h" - -#include "lib/nat_helper_hsl.h" -#include "lib/nat_helper_dt.h" - - -#define nf_nat_ipv4_multi_range_compat \ - nf_nat_ipv4_multi_range_compat -#define nf_nat_range nf_nat_ipv4_range -#define ipt_entry_target xt_entry_target -#define ipt_entry_match xt_entry_match - -#define IPT_MATCH_ITERATE(e, fun, args...) \ -({ \ - unsigned int i; \ - int ret = 0; \ - struct xt_entry_match *m; \ - \ - for (i = sizeof(struct ipt_entry); \ - i < (e)->target_offset; \ - i += m->u.match_size) { \ - m = (void *)e + i; \ - ret = fun(m , ##args); \ - if (ret != 0) \ - break; \ - } \ - ret; \ -}) - -#define IPT_ENTRY_ITERATE(entries, size, fun, args...) \ -({ \ - unsigned int k, j; \ - int ret = 0; \ - struct ipt_entry *e; \ - \ - for (k = 0, j = 0; k < (size); \ - k += (e)->next_offset, j++) { \ - e = (void *)(entries) + k; \ - if (j < 0) \ - continue; \ - \ - ret = fun(e , ##args); \ - if (ret != 0) \ - break; \ - } \ - ret; \ -}) - - -#define IPT_BUFFER_INIT_LEN 1000 -#define NF_NAT_INIT_ENTRIES_NUM 5 - -static int -nat_ipt_set_ctl(struct sock *sk, int cmd, void __user * user, unsigned int len); -static int -nat_ipt_get_ctl(struct sock *sk, int cmd, void __user * user, int *len); - -int nat_sockopts_init = 0; - -/*those initial value will be overwrited by orignal iptables sockopts*/ -static struct nf_sockopt_ops orgi_ipt_sockopts; -static struct nf_sockopt_ops tmp_ipt_sockopts = -{ - /*pls check linux/in.h*/ -#define IPT_TEMP_BASE_CTL 60 -#define IPT_TEMP_SET_MAX (IPT_TEMP_BASE_CTL+1) -#define IPT_TEMP_GET_MAX (IPT_TEMP_BASE_CTL+2) - .pf = PF_INET, - .set_optmin = IPT_TEMP_BASE_CTL, - .set_optmax = IPT_TEMP_SET_MAX, - .set = nat_ipt_set_ctl, - .get_optmin = IPT_TEMP_BASE_CTL, - .get_optmax = IPT_TEMP_GET_MAX, - .get = nat_ipt_get_ctl -}; - -static struct nf_sockopt_ops *ipt_sockopts = NULL; -static uint32_t snat_seq = 0; -static uint32_t hw_nat_ipt_seq[NAT_HW_NUM] = {0}; -static uint32_t hw_nat_pip_idx[NAT_HW_NUM] = {0}; -static uint8_t *gbuffer, *sbuffer; -static unsigned int glen, slen; -static struct ipt_replace old_replace; - -static void -nat_ipt_del(struct ipt_replace ireplace) -{ - int i, j; - struct ipt_entry *gentry = NULL; - struct ipt_entry *sentry = NULL; - struct xt_entry_target *gtarget = NULL; - struct xt_entry_target *starget = NULL; - struct nf_nat_ipv4_multi_range_compat *grange = NULL; - struct nf_nat_ipv4_multi_range_compat *srange = NULL; - uint8_t *gptr, *sptr; - unsigned int oldnum = ireplace.num_counters; - unsigned int seq = 1; - gptr = gbuffer; - sptr = sbuffer; - - HNAT_PRINTK("into nat_ipt_del\n"); - for (i = oldnum; i >= 0; i--)//NF_NAT_INIT_ENTRIES_NUM; i--) - { - gentry = (struct ipt_entry *)gptr; - sentry = (struct ipt_entry *)sptr; - gtarget = (struct xt_entry_target *)((uint8_t *) gentry + gentry->target_offset); - starget = (struct xt_entry_target *)((uint8_t *) sentry + sentry->target_offset); - grange = (struct nf_nat_ipv4_multi_range_compat *)((uint8_t *) gtarget + sizeof (*gtarget)); - srange = (struct nf_nat_ipv4_multi_range_compat *)((uint8_t *) starget + sizeof (*starget)); - - HNAT_PRINTK("(%d)isis_nat_del name %s:%s#####(%x:%x %x)###\n", - i, gtarget->u.user.name, starget->u.user.name, - gentry->ip.src.s_addr, gentry->ip.dst.s_addr, - grange->range[0].min.all); - - if (strcmp(gtarget->u.user.name, starget->u.user.name)) - { - /*if (!strcmp(gtarget->u.user.name, "DNAT")) { - if (gentry->ip.src.s_addr || !gentry->ip.dst.s_addr - || grange->range[0].min.all) - return; - goto delete; - } else */ - if (!strcmp(gtarget->u.user.name, "SNAT")) - { - if (!gentry->ip.src.s_addr || gentry->ip.dst.s_addr - || grange->range[0].min.all) - return; - goto delete; - } - return; - } /*else if (!strcmp(gtarget->u.user.name, "DNAT")) { - if (memcmp(gentry, sentry, gentry->next_offset)) { - if (gentry->ip.src.s_addr || !gentry->ip.dst.s_addr - || grange->range[0].min.all) - return; - goto delete; - } - } */else if (!strcmp(gtarget->u.user.name, "SNAT")) - { - if (memcmp(gentry, sentry, gentry->next_offset)) - { - if (!gentry->ip.src.s_addr || gentry->ip.dst.s_addr - || grange->range[0].min.all) - return; - goto delete; - } - } - gptr += gentry->next_offset; - sptr += gentry->next_offset; - if(!strcmp(gtarget->u.user.name, "SNAT")) - { - seq++; - } - } - HNAT_PRINTK("NONE to delete\n"); - return; - -delete: - HNAT_PRINTK("READY to delete one\n"); - for (j = 0; j < NAT_HW_NUM; j++) - { - HNAT_PRINTK("ready [%d] (hw)%x:(sw)%x######\n", - j, hw_nat_ipt_seq[j], seq); - if (hw_nat_ipt_seq[j] == seq) - { - if(nat_hw_del_by_index(j) != 0) - { - return; - } - //public_ip_del(hw_nat_pip_idx[j]); - } - } - - for(i = 0; i < NAT_HW_NUM; i++) - { - if(hw_nat_ipt_seq[i] > seq) - { - hw_nat_ipt_seq[i]--; - } - else if(hw_nat_ipt_seq[i] == seq) - { - hw_nat_ipt_seq[i]=0; - } - } - - return; -} - -static void -nat_ipt_to_hw_entry(struct ipt_entry *e, - nat_entry_t *nat) -{ -#define P_ANY 0 -#define P_TCP 6 -#define P_UDP 17 - - struct ipt_entry_target *t = (struct ipt_entry_target *)ipt_get_target(e); - - const struct nf_nat_ipv4_multi_range_compat *mr = - (struct nf_nat_ipv4_multi_range_compat *)(t->data); - const struct nf_nat_range *range = &mr->range[0]; - - uint32_t sip = ntohl(e->ip.src.s_addr); - uint32_t pip = ntohl(range->min_ip); - uint16_t proto = e->ip.proto; - - memset((void *) nat, 0, sizeof (nat_entry_t)); - - nat->src_addr = sip; - nat->trans_addr = pip; - - if (proto == P_TCP) - { - nat->flags = FAL_NAT_ENTRY_PROTOCOL_TCP; - } - else if (proto == P_UDP) - { - nat->flags = FAL_NAT_ENTRY_PROTOCOL_UDP; - } - else if (proto == P_ANY) - { - nat->flags = FAL_NAT_ENTRY_PROTOCOL_ANY; - } -} - -static int -nat_ipt_hw_add(nat_entry_t *nat) -{ - uint32_t index = 0; - if(nat_hw_add(nat) != 0) - { - return -1; - } - - hw_nat_ipt_seq[nat->entry_id] = snat_seq; - HNAT_PRINTK("###nat_ipt_hw_add hw_nat_ipt_seq[%d]:%d###\n", - nat->entry_id, snat_seq); - - hw_nat_pip_idx[nat->entry_id] = nat->trans_addr; - - if(nat_hw_prv_base_can_update()) - { - nat_hw_prv_base_set(nat->src_addr); - nat_hw_prv_base_update_disable(); - } - - if(nat_hw_pub_ip_add(nat->trans_addr, &index)!= 0) - { - return -1; - } - - return 0; -} - -static int -nat_ipt_hw_port_range_add(nat_entry_t *nat, - uint16_t port_start, uint16_t port_end, - struct xt_multiport *xport) -{ - unsigned int i; - - nat->flags |= FAL_NAT_ENTRY_PORT_CHECK; - - if(xport) - { - //some discontinuous ports - for (i = 0; i < xport->count; i++) - { - - nat->port_num = xport->ports[i]; - nat->port_range = 1; - - if(nat_ipt_hw_add(nat)) - { - HNAT_PRINTK("isis_nat_add(xport:%d) fail!\n", nat->port_num); - return -1; - } - - HNAT_PRINTK("(1)isis_nat_add(xport:%d) success\n", nat->port_num); - } - } - else - { - //one port or port range - uint16_t port_min, port_max; - - for (i = port_start; i <= port_end; i+= NAT_HW_PORT_RANGE_MAX) - { - port_min = i; - if((port_end-port_min)>(NAT_HW_PORT_RANGE_MAX-1)) - { - port_max = port_min+(NAT_HW_PORT_RANGE_MAX-1); - } - else - { - port_max = port_end; - } - - nat->port_num = port_min; - nat->port_range = (port_max - port_min + 1); - - if(nat_ipt_hw_add(nat)) - { - HNAT_PRINTK("isis_nat_add(range port:%d~%d) fail!\n", - port_min, port_max); - return -1; - } - - HNAT_PRINTK("(2)isis_nat_add(range port:%d~%d) success\n", port_min, port_max); - } - } - - return 0; -} - -static int -nat_ipt_check_none_matches(struct ipt_entry *e) -{ - nat_entry_t nat = {0}; - - nat_ipt_to_hw_entry(e, &nat); - - if(nat_ipt_hw_add(&nat) != 0) - { - HNAT_PRINTK("(1)isis_nat_add(none port)fail!\n"); - return -1; - } - - HNAT_PRINTK("(1)isis_nat_add(none port) success\n"); - - return 0; -} -static int -nat_ipt_check_matches(struct ipt_entry_match *m, - struct ipt_entry *e, - unsigned int *j) -{ - int ret = 0; - - nat_entry_t nat = {0}; - uint16_t port_start = 0, port_end = 0; - struct xt_multiport *xport = NULL; - - if(strcmp(m->u.user.name, "udp") == 0) - { - struct xt_udp *udpinfo = (struct xt_udp *)m->data; - port_start = udpinfo->spts[0]; - port_end = udpinfo->spts[1]; - - } - else if(strcmp(m->u.user.name, "tcp") == 0) - { - struct xt_tcp *tcpinfo = (struct xt_tcp *)m->data; - port_start = tcpinfo->spts[0]; - port_end = tcpinfo->spts[1]; - - } - else if(strcmp(m->u.user.name, "multiport") == 0) - { - struct xt_multiport xport_data = {0}; - struct ipt_entry_target *t = ipt_get_target(e); - xport = &xport_data; - - if(t->u.user.revision == 0) - { - xport = (struct xt_multiport *)m->data; - - } - else if(t->u.user.revision == 1) - { - const struct xt_multiport_v1 *xportv1 = - (struct xt_multiport_v1 *)m->data; - memcpy(xport->ports, xportv1->ports, sizeof(xportv1->ports)); - xport->count = xportv1->count; - } - - if(xport->flags != XT_MULTIPORT_SOURCE) - { - memset(xport->ports, 0, sizeof(xport->ports)); - } - - } - else - { - (*j)++ ; - HNAT_PRINTK("###no support matches m->u.user.name:%s\n", - m->u.user.name); - return -1; - } - - nat_ipt_to_hw_entry(e, &nat); - ret = nat_ipt_hw_port_range_add(&nat, port_start, port_end, xport); - - (*j)++ ; - - return ret; -} - -//check netmask !=32 -#define NAT_IPT_RULE_IS_FOR_NAPT(e) (((e)->ip.smsk.s_addr) != 0xffffffff) -#define NAT_IPT_RULE_IS_NONE_MATCHES(e) (((e)->target_offset) == \ - (sizeof(struct ipt_entry))) - -static int -nat_ipt_find_check_entry(struct ipt_entry *e, unsigned int underflow, - unsigned int *i) -{ - int ret = 0; - static uint16_t next_offset = 0; - struct ipt_entry_target *t = ipt_get_target(e); - - if(*i == 0) - { - snat_seq = 0; - next_offset = e->next_offset; - } - else - { - next_offset += e->next_offset; - } - - if (!strcmp(t->u.user.name, "SNAT")) - { - ++snat_seq; - - if(NAT_IPT_RULE_IS_FOR_NAPT(e)) - { - HNAT_PRINTK("this ipt rule only for HW napt offload\n"); - - } - else - { - /*for basic nat offload*/ - HNAT_PRINTK("[%d]next_offset:%d underflow:%d\n", - *i, next_offset, underflow); - - if(next_offset == underflow) //new one - { - - if(NAT_IPT_RULE_IS_NONE_MATCHES(e)) - { - /*none matches*/ - ret = nat_ipt_check_none_matches(e); - - } - else - { - unsigned int j = 0; - /*iterate matches*/ - ret = IPT_MATCH_ITERATE(e, nat_ipt_check_matches, e, &j); - } - } - } - } - - (*i)++ ; - - return ret; -} - -static void -nat_ipt_data_cleanup(void) -{ - if (gbuffer) - kfree(gbuffer); - - gbuffer = NULL; - - if (sbuffer) - kfree(sbuffer); - - sbuffer = NULL; -} - -static void -nat_ipt_data_init(void) -{ - /*alloc initial set buffer*/ - sbuffer = kmalloc(IPT_BUFFER_INIT_LEN, GFP_ATOMIC); - - if(sbuffer) - { - memset(sbuffer, 0, IPT_BUFFER_INIT_LEN); - slen = IPT_BUFFER_INIT_LEN; - } - else - { - HNAT_PRINTK("%s sbuffer memory allocate fail\n", __func__); - } - - /*alloc initial get buffer*/ - gbuffer = kmalloc(IPT_BUFFER_INIT_LEN, GFP_ATOMIC); - - if(gbuffer) - { - memset(gbuffer, 0, IPT_BUFFER_INIT_LEN); - glen = IPT_BUFFER_INIT_LEN; - } - else - { - HNAT_PRINTK("%s gbuffer memory allocate fail\n", __func__); - } - - - /*set initial underflow: nf_nat_rule.c*/ - memset(&old_replace, 0, sizeof (old_replace)); - - /*record ipt rule(SNAT) sequence for hw nat*/ - memset(hw_nat_ipt_seq, 0, NAT_HW_NUM); - - /*record ipt rule(SNAT) pubip index for hw nat*/ - memset(hw_nat_pip_idx, 0, NAT_HW_NUM); -} - -static void -nat_ipt_flush(void) -{ - napt_hw_flush(); - - nat_hw_flush(); - - nat_ipt_data_cleanup(); - nat_ipt_data_init(); - - HNAT_PRINTK("------(nat flush done)------\n"); -} - -static void -nat_ipt_add(struct ipt_replace ireplace) -{ - unsigned int i = 0; - - IPT_ENTRY_ITERATE(sbuffer, - ireplace.size, - nat_ipt_find_check_entry, - ireplace.underflow[NF_INET_POST_ROUTING], - &i); -} - -static int -nat_ipt_hook_type_check(struct ipt_replace ireplace) -{ - int ret = -1; - - HNAT_PRINTK("------we only support SNAT-----\n"); - - if((old_replace.underflow[NF_INET_POST_ROUTING]- - old_replace.hook_entry[NF_INET_POST_ROUTING]) != - (ireplace.underflow[NF_INET_POST_ROUTING]- - ireplace.hook_entry[NF_INET_POST_ROUTING])) - { - HNAT_PRINTK("------this is POSTROUTING(SNAT):yes!------\n"); - ret = 0; - - } - else if ((old_replace.underflow[NF_INET_PRE_ROUTING]- - old_replace.hook_entry[NF_INET_PRE_ROUTING]) != - (ireplace.underflow[NF_INET_PRE_ROUTING]- - ireplace.hook_entry[NF_INET_PRE_ROUTING])) - { - HNAT_PRINTK("------this is PREROUTING(DNAT):no!------\n"); - - } - else if((old_replace.underflow[NF_INET_LOCAL_OUT]- - old_replace.hook_entry[NF_INET_LOCAL_OUT]) != - (ireplace.underflow[NF_INET_LOCAL_OUT]- - ireplace.hook_entry[NF_INET_LOCAL_OUT])) - { - HNAT_PRINTK("------this is OUTPUT:no!------\n"); - - } - else - { - HNAT_PRINTK("------this is UNKNOW:no!------\n"); - - } - - return ret; -} - -static void -nat_ipt_rules_cp_from_user(void **buf, unsigned int *buf_len, - void __user *user, unsigned int user_len) -{ - if((*buf == 0) || (user == 0)) - { - return; - } - - if (*buf_len < user_len) - { - if(*buf) - { - kfree(*buf); - *buf = kmalloc(user_len, GFP_ATOMIC); - if(*buf == NULL) - { - HNAT_PRINTK("%s memory allocate fail\n", __func__); - return; - } - *buf_len = user_len; - } - } - HNAT_PRINTK("(2)nat_ipt_rules_cp_from_user *buf:%x user:%x user_len:%d\n", - (unsigned int)*buf, (unsigned int)user, user_len); - copy_from_user(*buf, user, user_len); - - return; -} - -static int -nat_ipt_set_ctl(struct sock *sk, int cmd, void __user * user, unsigned int len) -{ - struct ipt_replace ireplace; - - memset(&ireplace, 0, sizeof(ireplace)); - - HNAT_PRINTK("NAT set hook\n"); - - if (cmd != IPT_SO_SET_REPLACE) - goto normal; - - copy_from_user(&ireplace, user, sizeof (ireplace)); - - if (strcmp(ireplace.name, "nat") - || (ireplace.num_entries == ireplace.num_counters)) - { - HNAT_PRINTK("none NAT or no new entry %d", ireplace.num_entries); - goto normal; - } - - - if (ireplace.num_entries == NF_NAT_INIT_ENTRIES_NUM) - { - nat_ipt_flush(); - goto normal; - } - - if (nat_ipt_hook_type_check(ireplace) != 0) - { - goto normal; - } - - nat_ipt_rules_cp_from_user((void **)&sbuffer, &slen, - (user + sizeof (ireplace)), - ireplace.size); - - if (ireplace.num_entries > ireplace.num_counters) - { - nat_ipt_add(ireplace); - } - else - { - nat_ipt_del(ireplace); - } - -normal: - /*save old_replace for next hook type check*/ - old_replace = ireplace; - - return orgi_ipt_sockopts.set(sk, cmd, user, len); -} - -static int -nat_ipt_get_ctl(struct sock *sk, int cmd, void __user * user, int *len) -{ - int k = orgi_ipt_sockopts.get(sk, cmd, user, len); - - if (cmd == IPT_SO_GET_ENTRIES) - { - - struct ipt_get_entries entries; - - copy_from_user(&entries, user, sizeof (entries)); - - nat_ipt_rules_cp_from_user((void **)&gbuffer, &glen, - (user + sizeof (struct ipt_get_entries)), - (*len - sizeof (entries))); - } - return k; -} - - -void -nat_ipt_sockopts_replace(void) -{ - int ret = 0; - /*register an temp sockopts to find ipt_sockopts*/ - if((ret = nf_register_sockopt(&tmp_ipt_sockopts)) < 0) { - return; - } - list_for_each_entry(ipt_sockopts, tmp_ipt_sockopts.list.next, list) - { - if (ipt_sockopts->set_optmin == IPT_BASE_CTL) - { - nat_sockopts_init = 1; - break; - } - } - nf_unregister_sockopt(&tmp_ipt_sockopts); - if(!nat_sockopts_init) - return; - - /*save orginal ipt_sockopts*/ - orgi_ipt_sockopts = *ipt_sockopts; - - /*replace ipt_sockopts with our opts*/ - ipt_sockopts->set = nat_ipt_set_ctl; - ipt_sockopts->get = nat_ipt_get_ctl; -} - -static void -nat_ipt_sockopts_restore(void) -{ - ipt_sockopts->set = orgi_ipt_sockopts.set; - ipt_sockopts->get = orgi_ipt_sockopts.get; -} - -void -nat_ipt_helper_init(void) -{ - nat_ipt_sockopts_replace(); - nat_ipt_data_init(); -} - -void -nat_ipt_helper_exit(void) -{ - nat_ipt_sockopts_restore(); - nat_ipt_data_cleanup(); - nat_hw_flush(); -} - diff --git a/feeds/ipq807x/qca-ssdk/src/config b/feeds/ipq807x/qca-ssdk/src/config deleted file mode 100644 index 9ee9472f8..000000000 --- a/feeds/ipq807x/qca-ssdk/src/config +++ /dev/null @@ -1,347 +0,0 @@ -#CPU=mips - -OS=linux - -ifeq ($(KVER),$(filter 3.14%,$(KVER))) -OS_VER=3_14 -endif - -ifeq ($(KVER),$(filter 4.4%,$(KVER))) -OS_VER=4_4 -endif - -ifeq ($(KVER),$(filter 4.1%,$(KVER))) -OS_VER=4_1 -endif - -ifeq ($(KVER),$(filter 4.9%,$(KVER))) -OS_VER=4_9 -endif - -ifeq ($(KVER),$(filter 5.4%,$(KVER))) -OS_VER=5_4 -endif - -ifeq ($(KVER), 3.4.0) -OS_VER=3_4 -endif - -ifeq ($(KVER), 3.18) -OS_VER=3_18 -endif - -ifeq ($(KVER), 3.18.21) -OS_VER=3_18 -endif - -ifeq ($(KVER), 3.4.103) -OS_VER=3_4 -endif - -ifeq ($(KVER), 3.3.8) -OS_VER=3_2 -endif - -ifeq ($(ARCH), arm) -BOARD=ipq806x -endif - -ifeq ($(ARCH), mips) -BOARD=ar71xx -endif - -ifeq ($(BOARD), ar71xx) -BOARD_NAME=BOARD_AR71XX -endif - -ifeq ($(BOARD), ipq806x) -BOARD_NAME=BOARD_IPQ806X -endif - -OS_SUB=31 - -ifndef OS_VER -OS_VER=2_6 -endif -# OS subversion, 2.6.31 for WASP (db120) -#OS_SUB=31 -# GCC version, 3 or 4 -#GCC_VER=4 - -#For MIPS Linux2.6 - #pb45 - #TOOL_PATH=/disk/pb45/sw/build/gcc-3.4.4-2.16.1/build_mips_nofpu/bin - #SYS_PATH=/disk/pb45/sw/linux/kernels/mips-linux-2.6.15 - - #ap81 -# compatiable with OpenWRT -ifndef TOOL_PATH -TOOL_PATH=/disk/ap81fus/sw/build/gcc-3.4.4-2.16.1/build_mips/bin -endif -ifndef SYS_PATH -SYS_PATH=/disk/ap81fus/sw/linux/kernels/mips-linux-2.6.15 -endif -ifeq ($(ARCH), mips) - CPU_CFLAG=-Wstrict-prototypes -fomit-frame-pointer -G 0 -mno-abicalls -fno-common -fno-strict-aliasing -O2 -fno-pic -pipe -mabi=32 -march=mips32r2 -DMODULE -mlong-calls -DEXPORT_SYMTAB -D$(BOARD_NAME) -endif - - -#db120 -ifeq ($(BOARD_TYPE),db12x) -OS_SUB=31 -GCC_VER=4 -TOOL_PATH=$(TOPDIR)/build/gcc-4.3.3/build_mips/staging_dir/usr/bin -SYS_PATH=$(TOPDIR)/linux/kernels/mips-linux-2.6.31 -CPU_CFLAG=-Wstrict-prototypes -fomit-frame-pointer -G 0 -mno-abicalls -fno-strict-aliasing -O2 -fno-pic -pipe -mabi=32 -march=mips32r2 -DMODULE -mlong-calls -DEXPORT_SYMTAB -endif - -ifeq ($(ARCH), arm) -ifeq ($(KVER), 3.4.0) - CPU_CFLAG=-D__LINUX_ARM_ARCH__=7 -DMODULE -fno-common -DCONFIG_MMU -D$(BOARD_NAME) -endif -ifeq ($(KVER), 3.4.103) - CPU_CFLAG=-D__LINUX_ARM_ARCH__=7 -DMODULE -fno-common -DCONFIG_MMU -D$(BOARD_NAME) -endif -ifeq ($(KVER), 3.18.21) - CPU_CFLAG=-D__LINUX_ARM_ARCH__=7 -DMODULE -fno-common -DCONFIG_MMU -D$(BOARD_NAME) -endif -ifeq ($(KVER),$(filter 4.4% 5.4%,$(KVER))) - CPU_CFLAG=-D__LINUX_ARM_ARCH__=7 -DMODULE -fno-common -DCONFIG_MMU -D$(BOARD_NAME) -endif - -ifeq ($(KVER),$(filter 3.14%,$(KVER))) - CPU_CFLAG= -DMODULE -nostdinc -D$(BOARD_NAME) -mlittle-endian -Wundef -Wstrict-prototypes -Wno-trigraphs -Werror -fno-strict-aliasing -fno-common -Wno-format-security -fno-delete-null-pointer-checks -O2 -fno-dwarf2-cfi-asm -mabi=aapcs-linux -mno-thumb-interwork -mfpu=vfp -funwind-tables -marm -D__LINUX_ARM_ARCH__=7 -march=armv7-a -msoft-float -Uarm -Wframe-larger-than=1024 -fno-stack-protector -Wno-unused-but-set-variable -fomit-frame-pointer -g -Wdeclaration-after-statement -Wno-pointer-sign -fno-strict-overflow -fconserve-stack -Werror=implicit-int -DCC_HAVE_ASM_GOTO -D"KBUILD_STR(s)=\#s" -D"KBUILD_BASENAME=KBUILD_STR(mem)" -endif - -ifeq ($(KVER),$(filter 4.9% 4.4% 5.4%,$(KVER))) - CPU_CFLAG= -DMODULE -nostdinc -D$(BOARD_NAME) -mlittle-endian -Wundef -Wstrict-prototypes -Wno-trigraphs -Werror -fno-strict-aliasing -fno-common -Wno-format-security -fno-delete-null-pointer-checks -O2 -fno-dwarf2-cfi-asm -mabi=aapcs-linux -mno-thumb-interwork -mfpu=vfp -funwind-tables -marm -D__LINUX_ARM_ARCH__=7 -march=armv7-a -msoft-float -Uarm -Wframe-larger-than=2048 -fno-stack-protector -Wno-unused-but-set-variable -fomit-frame-pointer -g -Wdeclaration-after-statement -Wno-pointer-sign -fno-strict-overflow -fconserve-stack -Werror=implicit-int -DCC_HAVE_ASM_GOTO -D"KBUILD_STR(s)=\#s" -D"KBUILD_BASENAME=KBUILD_STR(mem)" -endif - -ifeq ($(KVER),$(filter 3.18%,$(KVER))) - CPU_CFLAG= -DMODULE -nostdinc -D$(BOARD_NAME) -mlittle-endian -Wundef -Wstrict-prototypes -Wno-trigraphs -fno-strict-aliasing -fno-common -Wno-format-security -fno-delete-null-pointer-checks -O2 -fno-dwarf2-cfi-asm -mabi=aapcs-linux -mno-thumb-interwork -mfpu=vfp -funwind-tables -marm -D__LINUX_ARM_ARCH__=7 -march=armv7-a -msoft-float -Uarm -Wframe-larger-than=1024 -fno-stack-protector -Wno-unused-but-set-variable -fomit-frame-pointer -g -Wdeclaration-after-statement -Wno-pointer-sign -fno-strict-overflow -fconserve-stack -Werror=implicit-int -DCC_HAVE_ASM_GOTO -D"KBUILD_STR(s)=\#s" -D"KBUILD_BASENAME=KBUILD_STR(mem)" -endif -endif - -ifeq ($(ARCH), arm64) -ifeq ($(KVER),$(filter 4.1% 4.4% 4.9% 5.4%,$(KVER))) - CPU_CFLAG= -DMODULE -Os -pipe -march=armv8-a -mcpu=cortex-a53+crypto -fno-caller-saves -fno-strict-aliasing -Werror -fno-common -Wno-format-security -Wno-pointer-sign -Wno-unused-but-set-variable -Wno-error=unused-result -mcmodel=large -endif -endif - -ifeq ($(BOARD_TYPE), ap136) -OS_SUB=31 -GCC_VER=4 -TOOL_PATH=$(TOPDIR)/build/gcc-4.3.3/build_mips/staging_dir/usr/bin -SYS_PATH=$(TOPDIR)/linux/kernels/mips-linux-2.6.31 -CPU_CFLAG=-Wstrict-prototypes -fomit-frame-pointer -G 0 -mno-abicalls -fno-strict-aliasing -O2 -fno-pic -pipe -mabi=32 -march=mips32r2 -DMODULE -mlong-calls -DEXPORT_SYMTAB -endif - -#For MIPS Linux2.4 - #TOOL_PATH=/home/perforce/kernel2.4/5.3.1.20/tools/gcc-3.3.3-2.4.25/toolchain_mips/bin - #SYS_PATH=/home/perforce/kernel2.4/5.3.1.20/src/kernels/mips-linux-2.4.25 - - #TOOLPREFIX=$(CPU)-$(OS)- - #CPU_CFLAG=-Wstrict-prototypes -Wundef -fomit-frame-pointer -G 0 -mno-abicalls -Wno-trigraphs -fno-strict-aliasing -fno-common -ffreestanding -O2 -fno-pic -pipe -mabi=32 -march=r4600 -Wa,-32 -Wa,-march=r4600 -Wa,--trap -DMODULE -mlong-calls -DEXPORT_SYMTAB - -ifeq ($(SWCONFIG_FEATURE), disable) -SWCONFIG=FALSE -else -SWCONFIG=TRUE -endif - -KERNEL_MODE=TRUE -#compatiable with OpenWRT -ifeq ($(SWITCH_SSDK_MODE),user) -KERNEL_MODE=FLASE -endif - -#FAL=FALSE or not define FAL, FAL will not be included in SSDK -FAL=TRUE - -#CHIP_TYPE can be defined as ATHENA, GARUDA, SHIVA, HORUS, ISIS, ISISC, DESS, HPPE, CPPE, MP and ALL_CHIP(ALL_CHIP means GARUDA, SHIVA, HORUS, ISIS, ISISC, DESS and HPPE CPPE MP) -ifndef CHIP_TYPE -CHIP_TYPE=ALL_CHIP -endif - -#UK_IF=FALSE or not define UK_IF, UK_IF will not be included in SSDK -#when UK_IF=TRUE one of UK_NETLINK,UK_IOCTL must be defined as TRUE -UK_IF=TRUE -#UK_IOCTL=TRUE define user-kernel space communication based on ioctl -UK_IOCTL=TRUE -UK_MINOR_DEV=254 - -#API_LOCK=FALSE or not define API_LOCK, API_LOCK will not be included in SSDK -API_LOCK=FALSE - -#REG_ACCESS_SPEEDUP=FALSE or not define REG_ACCESS_SPEEDUP, REG_ACCESS_SPEEDUP will not be enabled, now only ISIS supports -REG_ACCESS_SPEEDUP=FALSE - -#ALL supported features: -#ACL FDB IGMP LEAKY LED MIB MIRROR MISC PORTCONTROL PORTVLAN QOS RATE STP VLAN -#IN_X=FALSE or not define IN_X, X will not be included in SSDK -IN_ACL=TRUE -IN_FDB=TRUE -IN_IGMP=TRUE -IN_LEAKY=TRUE -IN_LED=TRUE -IN_MIB=TRUE -IN_MIRROR=TRUE -IN_MISC=TRUE -IN_PORTCONTROL=TRUE -IN_PORTVLAN=TRUE -IN_QOS=TRUE -IN_RATE=TRUE -IN_STP=TRUE -IN_VLAN=TRUE -IN_REDUCED_ACL=FALSE -IN_COSMAP=TRUE -IN_IP=TRUE -IN_NAT=TRUE -IN_TRUNK=TRUE -IN_SEC=TRUE -IN_PPPOE=TRUE -ifeq ($(HNAT_FEATURE), enable) -IN_NAT_HELPER=TRUE -else -IN_NAT_HELPER=FALSE -endif -ifeq ($(RFS_FEATURE), enable) -IN_RFS=TRUE -else -IN_RFS=FALSE -endif -IN_INTERFACECONTROL=TRUE -IN_MACBLOCK=FALSE -#The PHY CHIP defined according to the switch CHIP -ifeq (ALL_CHIP, $(CHIP_TYPE)) -IN_AQUANTIA_PHY=TRUE -IN_QCA803X_PHY=TRUE -IN_QCA808X_PHY=TRUE -IN_PHY_I2C_MODE=TRUE -IN_MALIBU_PHY=TRUE -IN_SFP_PHY=TRUE -IN_SFP=TRUE -else ifeq (HPPE, $(CHIP_TYPE)) -IN_AQUANTIA_PHY=TRUE -IN_QCA803X_PHY=TRUE -IN_QCA808X_PHY=TRUE -IN_PHY_I2C_MODE=TRUE -IN_SFP_PHY=TRUE -IN_MALIBU_PHY=TRUE -else ifeq (CPPE, $(CHIP_TYPE)) -IN_QCA808X_PHY=TRUE -IN_QCA803X_PHY=TRUE -IN_SFP_PHY=TRUE -IN_PHY_I2C_MODE=TRUE -IN_MALIBU_PHY=TRUE -else ifeq (DESS, $(CHIP_TYPE)) -IN_MALIBU_PHY=TRUE -else ifeq (MP, $(CHIP_TYPE)) -IN_QCA803X_PHY=TRUE -IN_QCA808X_PHY=TRUE -else -IN_QCA803X_PHY=FALSE -IN_QCA808X_PHY=FALSE -IN_AQUANTIA_PHY=FALSE -IN_MALIBU_PHY=FALSE -IN_SFP_PHY=FALSE -IN_SFP=FALSE -endif -ifeq ($(SFE_FEATURE), enable) -IN_SFE=TRUE -else -IN_SFE=FALSE -endif -#QCA808X PHY features -ifeq ($(IN_QCA808X_PHY), TRUE) -ifeq ($(PTP_FEATURE), enable) -IN_PTP=TRUE -else -IN_PTP=FALSE -endif -endif -#IN_PHY_I2C_MODE depends on IN_SFP_PHY -ifeq ($(IN_PHY_I2C_MODE), TRUE) -IN_SFP_PHY=TRUE -endif -ifneq (, $(filter HPPE CPPE ALL_CHIP, $(CHIP_TYPE))) -IN_FLOW=TRUE -IN_RSS_HASH=TRUE -IN_QM=TRUE -IN_VSI=TRUE -IN_CTRLPKT=TRUE -IN_SERVCODE=TRUE -IN_BM=TRUE -IN_SHAPER=TRUE -IN_POLICER=TRUE -endif -ifneq (, $(filter HPPE CPPE MP ALL_CHIP, $(CHIP_TYPE))) -IN_UNIPHY=TRUE -endif -#MINI SSDK enabled -ifeq ($(MINI_SSDK), enable) -IN_FDB_MINI=TRUE -IN_MISC_MINI=TRUE -IN_PORTCONTROL_MINI=TRUE -IN_QOS_MINI=TRUE -IN_COSMAP_MINI=TRUE -IN_PORTVLAN_MINI=TRUE -IN_VLAN_MINI=TRUE -IN_VSI_MINI=TRUE -IN_BM_MINI=TRUE -IN_SHAPER_MINI=TRUE -IN_POLICER_MINI=TRUE -IN_FLOW_MINI=TRUE -IN_QM_MINI=TRUE -IN_UNIPHY_MINI=TRUE -IN_IP_MINI=TRUE -IN_SFP=FALSE -#disable modules for MINI HPPE/CPPE -ifneq (, $(filter HPPE CPPE, $(CHIP_TYPE))) -IN_SERVCODE=FALSE -IN_PPPOE=FALSE -IN_NAT=FALSE -IN_COSMAP=FALSE -IN_RATE=FALSE -IN_IGMP=FALSE -IN_LEAKY=FALSE -IN_LED=FALSE -IN_INTERFACECONTROL=FALSE -endif -endif -ifneq ($(HK_CHIP), enable) -CHIP_TYPE=NONHK_CHIP -endif - -ifeq (MP, $(CHIP_TYPE)) -ifeq (disable, $(ISISC_ENABLE)) -IN_ACL=FALSE -IN_FDB=FALSE -IN_IGMP=FALSE -IN_LEAKY=FALSE -IN_LED=FALSE -IN_MIRROR=FALSE -IN_MISC=FALSE -IN_PORTVLAN=FALSE -IN_QOS=FALSE -IN_RATE=FALSE -IN_STP=FALSE -IN_VLAN=FALSE -IN_REDUCED_ACL=FALSE -IN_COSMAP=FALSE -IN_IP=FALSE -IN_NAT=FALSE -IN_FLOW=FALSE -IN_TRUNK=FALSE -IN_RSS_HASH=FALSE -IN_SEC=FALSE -IN_QM=FALSE -IN_PPPOE=FALSE -IN_VSI=FALSE -IN_CTRLPKT=FALSE -IN_SERVCODE=FALSE -IN_BM=FALSE -IN_SHAPER=FALSE -IN_POLICER=FALSE -endif -endif diff --git a/feeds/ipq807x/qca-ssdk/src/include/adpt/adpt.h b/feeds/ipq807x/qca-ssdk/src/include/adpt/adpt.h deleted file mode 100755 index b497350af..000000000 --- a/feeds/ipq807x/qca-ssdk/src/include/adpt/adpt.h +++ /dev/null @@ -1,1604 +0,0 @@ -/* - * Copyright (c) 2016-2021, The Linux Foundation. All rights reserved. - * Permission to use, copy, modify, and/or distribute this software for - * any purpose with or without fee is hereby granted, provided that the - * above copyright notice and this permission notice appear in all copies. - * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES - * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR - * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES - * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN - * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT - * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. - */ - - -/** - * @defgroup - * @{ - */ -#ifndef _ADPT_H_ -#define _ADPT_H_ - -#ifdef __cplusplus -extern "C" { -#endif /* __cplusplus */ - -#include "sw.h" -#include "fal_fdb.h" -#include "fal_portvlan.h" -#include "fal_ctrlpkt.h" -#include "fal_servcode.h" -#include "fal_rss_hash.h" -#include "fal_mib.h" -#include "fal_port_ctrl.h" -#include "fal_mirror.h" -#include "fal_trunk.h" -#include "fal_ip.h" -#include "fal_qm.h" -#include "fal_flow.h" -#include "ssdk_init.h" -#include "fal_type.h" -#include "fal_stp.h" -#include "fal_vsi.h" -#include "fal_pppoe.h" -#include "fal_sec.h" -#include "fal_acl.h" -#include "fal_qos.h" -#include "fal_shaper.h" -#include "fal_bm.h" -#include "fal_init.h" -#include "fal_policer.h" -#include "fal_misc.h" -#include "fal_ptp.h" -#include "fal_sfp.h" -#include "ssdk_plat.h" - -#define ADPT_DEV_ID_CHECK(dev_id) \ -do { \ - if (dev_id >= SW_MAX_NR_DEV) \ - return SW_OUT_OF_RANGE; \ -} while (0) - -#define ADPT_PORT_ID_CHECK(port_id) \ -do { \ - if (port_id >= SW_MAX_NR_PORT) \ - return SW_OUT_OF_RANGE; \ -} while (0) - -#define ADPT_NULL_POINT_CHECK(point) \ -do { \ - if (point == NULL) \ - return SW_BAD_PTR; \ -} while (0) - -typedef sw_error_t (*adpt_fdb_first_func)(a_uint32_t dev_id, fal_fdb_entry_t * entry); -typedef sw_error_t (*adpt_fdb_next_func)(a_uint32_t dev_id, fal_fdb_entry_t * entry); -typedef sw_error_t (*adpt_fdb_add_func)(a_uint32_t dev_id, const fal_fdb_entry_t * entry); -typedef sw_error_t (*adpt_fdb_age_time_set_func)(a_uint32_t dev_id, a_uint32_t * time); -typedef sw_error_t (*adpt_fdb_extend_next_func)(a_uint32_t dev_id, fal_fdb_op_t * option, - fal_fdb_entry_t * entry); -typedef sw_error_t (*adpt_fdb_learn_ctrl_get_func)(a_uint32_t dev_id, a_bool_t * enable); -typedef sw_error_t (*adpt_fdb_age_time_get_func)(a_uint32_t dev_id, a_uint32_t * time); -typedef sw_error_t (*adpt_port_fdb_learn_limit_set_func)(a_uint32_t dev_id, fal_port_t port_id, - a_bool_t enable, a_uint32_t cnt); -typedef sw_error_t (*adpt_fdb_port_add_func)(a_uint32_t dev_id, a_uint32_t fid, fal_mac_addr_t * addr, fal_port_t port_id); -typedef sw_error_t (*adpt_fdb_port_learn_set_func)(a_uint32_t dev_id, fal_port_t port_id, a_bool_t enable); -typedef sw_error_t (*adpt_fdb_port_learn_get_func)(a_uint32_t dev_id, fal_port_t port_id, a_bool_t *enable); -typedef sw_error_t (*adpt_fdb_port_newaddr_lrn_set_func)(a_uint32_t dev_id, fal_port_t port_id, a_bool_t enable, fal_fwd_cmd_t cmd); -typedef sw_error_t (*adpt_fdb_port_newaddr_lrn_get_func)(a_uint32_t dev_id, fal_port_t port_id, a_bool_t *enable, fal_fwd_cmd_t *cmd); -typedef sw_error_t (*adpt_fdb_port_stamove_set_func)(a_uint32_t dev_id, fal_port_t port_id, a_bool_t enable, fal_fwd_cmd_t cmd); -typedef sw_error_t (*adpt_fdb_port_stamove_get_func)(a_uint32_t dev_id, fal_port_t port_id, a_bool_t *enable, fal_fwd_cmd_t *cmd); -typedef sw_error_t (*adpt_port_fdb_learn_counter_get_func)(a_uint32_t dev_id, fal_port_t port_id, - a_uint32_t * cnt); -typedef sw_error_t (*adpt_fdb_extend_first_func)(a_uint32_t dev_id, fal_fdb_op_t * option, - fal_fdb_entry_t * entry); -typedef sw_error_t (*adpt_fdb_transfer_func)(a_uint32_t dev_id, fal_port_t old_port, fal_port_t new_port, - a_uint32_t fid, fal_fdb_op_t * option); -typedef sw_error_t (*adpt_fdb_port_del_func)(a_uint32_t dev_id, a_uint32_t fid, fal_mac_addr_t * addr, fal_port_t port_id); -typedef sw_error_t (*adpt_fdb_find_func)(a_uint32_t dev_id, fal_fdb_entry_t * entry); -typedef sw_error_t (*adpt_fdb_learn_ctrl_set_func)(a_uint32_t dev_id, a_bool_t enable); -typedef sw_error_t (*adpt_port_fdb_learn_exceed_cmd_get_func)(a_uint32_t dev_id, fal_port_t port_id, - fal_fwd_cmd_t * cmd); -typedef sw_error_t (*adpt_fdb_del_by_port_func)(a_uint32_t dev_id, a_uint32_t port_id, a_uint32_t flag); -typedef sw_error_t (*adpt_port_fdb_learn_limit_get_func)(a_uint32_t dev_id, fal_port_t port_id, - a_bool_t * enable, a_uint32_t * cnt); -typedef sw_error_t (*adpt_fdb_age_ctrl_set_func)(a_uint32_t dev_id, a_bool_t enable); -typedef sw_error_t (*adpt_fdb_del_by_mac_func)(a_uint32_t dev_id, const fal_fdb_entry_t *entry); -typedef sw_error_t (*adpt_fdb_iterate_func)(a_uint32_t dev_id, a_uint32_t * iterator, fal_fdb_entry_t * entry); -typedef sw_error_t (*adpt_port_fdb_learn_exceed_cmd_set_func)(a_uint32_t dev_id, fal_port_t port_id, - fal_fwd_cmd_t cmd); -typedef sw_error_t (*adpt_fdb_del_all_func)(a_uint32_t dev_id, a_uint32_t flag); -typedef sw_error_t (*adpt_fdb_age_ctrl_get_func)(a_uint32_t dev_id, a_bool_t * enable); -typedef sw_error_t (*adpt_fdb_port_maclimit_ctrl_set_func)(a_uint32_t dev_id, fal_port_t port_id, fal_maclimit_ctrl_t * maclimit_ctrl); -typedef sw_error_t (*adpt_fdb_port_maclimit_ctrl_get_func)(a_uint32_t dev_id, fal_port_t port_id, fal_maclimit_ctrl_t * maclimit_ctrl); -typedef sw_error_t (*adpt_fdb_del_by_fid_func)(a_uint32_t dev_id, a_uint16_t fid, a_uint32_t flag); - -typedef sw_error_t (*adpt_mib_cpukeep_get_func)(a_uint32_t dev_id, a_bool_t * enable); -typedef sw_error_t (*adpt_mib_cpukeep_set_func)(a_uint32_t dev_id, a_bool_t enable); -typedef sw_error_t (*adpt_get_mib_info_func)(a_uint32_t dev_id, fal_port_t port_id, - fal_mib_info_t * mib_info ); -typedef sw_error_t (*adpt_get_tx_mib_info_func)(a_uint32_t dev_id, fal_port_t port_id, - fal_mib_info_t * mib_info ); -typedef sw_error_t (*adpt_mib_status_set_func)(a_uint32_t dev_id, a_bool_t enable); -typedef sw_error_t (*adpt_mib_port_flush_counters_func)(a_uint32_t dev_id, fal_port_t port_id); -typedef sw_error_t (*adpt_mib_status_get_func)(a_uint32_t dev_id, a_bool_t * enable); -typedef sw_error_t (*adpt_get_rx_mib_info_func)(a_uint32_t dev_id, fal_port_t port_id, - fal_mib_info_t * mib_info ); -typedef sw_error_t (*adpt_get_xgmib_info_func)(a_uint32_t dev_id, fal_port_t port_id, - fal_xgmib_info_t * mib_info ); -typedef sw_error_t (*adpt_get_tx_xgmib_info_func)(a_uint32_t dev_id, fal_port_t port_id, - fal_xgmib_info_t * mib_info ); -typedef sw_error_t (*adpt_get_rx_xgmib_info_func)(a_uint32_t dev_id, fal_port_t port_id, - fal_xgmib_info_t * mib_info ); - -typedef sw_error_t (*adpt_stp_port_state_get_func)(a_uint32_t dev_id, a_uint32_t st_id, - fal_port_t port_id, fal_stp_state_t * state); -typedef sw_error_t (*adpt_stp_port_state_set_func)(a_uint32_t dev_id, a_uint32_t st_id, - fal_port_t port_id, fal_stp_state_t state); - -typedef sw_error_t (*adpt_port_vlan_vsi_set_func)(a_uint32_t dev_id, fal_port_t port_id, a_uint32_t stag_vid, a_uint32_t ctag_vid, a_uint32_t vsi_id); -typedef sw_error_t (*adpt_port_vlan_vsi_get_func)(a_uint32_t dev_id, fal_port_t port_id, a_uint32_t stag_vid, a_uint32_t ctag_vid, a_uint32_t *vsi_id); -typedef sw_error_t (*adpt_port_vsi_set_func)(a_uint32_t dev_id, fal_port_t port_id, a_uint32_t vsi_id); -typedef sw_error_t (*adpt_port_vsi_get_func)(a_uint32_t dev_id, fal_port_t port_id, a_uint32_t *vsi_id); -typedef sw_error_t (*adpt_vsi_stamove_set_func)(a_uint32_t dev_id, a_uint32_t vsi_id, fal_vsi_stamove_t *stamove); -typedef sw_error_t (*adpt_vsi_stamove_get_func)(a_uint32_t dev_id, a_uint32_t vsi_id, fal_vsi_stamove_t *stamove); -typedef sw_error_t (*adpt_vsi_newaddr_lrn_set_func)(a_uint32_t dev_id, a_uint32_t vsi_id, fal_vsi_newaddr_lrn_t *newaddr_lrn); -typedef sw_error_t (*adpt_vsi_newaddr_lrn_get_func)(a_uint32_t dev_id, a_uint32_t vsi_id, fal_vsi_newaddr_lrn_t *newaddr_lrn); -typedef sw_error_t (*adpt_vsi_member_set_func)(a_uint32_t dev_id, a_uint32_t vsi_id, fal_vsi_member_t *vsi_member); -typedef sw_error_t (*adpt_vsi_member_get_func)(a_uint32_t dev_id, a_uint32_t vsi_id, fal_vsi_member_t *vsi_member); -typedef sw_error_t (*adpt_vsi_counter_get_func)(a_uint32_t dev_id, a_uint32_t vsi_id, fal_vsi_counter_t *counter); -typedef sw_error_t (*adpt_vsi_counter_cleanup_func)(a_uint32_t dev_id, a_uint32_t vsi_id); - -// portctrl function. - -typedef sw_error_t (*adpt_port_local_loopback_get_func)(a_uint32_t dev_id, fal_port_t port_id, - a_bool_t * enable); -typedef sw_error_t (*adpt_port_autoneg_restart_func)(a_uint32_t dev_id, fal_port_t port_id); -typedef sw_error_t (*adpt_port_duplex_set_func)(a_uint32_t dev_id, fal_port_t port_id, - fal_port_duplex_t duplex); -typedef sw_error_t (*adpt_port_rxmac_status_get_func)(a_uint32_t dev_id, fal_port_t port_id, - a_bool_t * enable); -typedef sw_error_t (*adpt_port_cdt_func)(a_uint32_t dev_id, fal_port_t port_id, - a_uint32_t mdi_pair, fal_cable_status_t * cable_status, - a_uint32_t * cable_len); -typedef sw_error_t (*adpt_port_txmac_status_set_func)(a_uint32_t dev_id, fal_port_t port_id, - a_bool_t enable); -typedef sw_error_t (*adpt_port_combo_fiber_mode_set_func)(a_uint32_t dev_id, - a_uint32_t port_id, - fal_port_fiber_mode_t mode); -typedef sw_error_t (*adpt_port_combo_medium_status_get_func)(a_uint32_t dev_id, - a_uint32_t port_id, - fal_port_medium_t * - medium); -typedef sw_error_t (*adpt_port_magic_frame_mac_set_func)(a_uint32_t dev_id, fal_port_t port_id, - fal_mac_addr_t * mac); -typedef sw_error_t (*adpt_port_powersave_set_func)(a_uint32_t dev_id, fal_port_t port_id, - a_bool_t enable); -typedef sw_error_t (*adpt_port_hibernate_set_func)(a_uint32_t dev_id, fal_port_t port_id, - a_bool_t enable); -typedef sw_error_t (*adpt_port_max_frame_size_set_func)(a_uint32_t dev_id, fal_port_t port_id, - a_uint32_t max_frame); -typedef sw_error_t (*adpt_port_8023az_get_func)(a_uint32_t dev_id, fal_port_t port_id, - a_bool_t * enable); -typedef sw_error_t (*adpt_port_rxfc_status_get_func)(a_uint32_t dev_id, fal_port_t port_id, - a_bool_t * enable); -typedef sw_error_t (*adpt_port_txfc_status_get_func)(a_uint32_t dev_id, fal_port_t port_id, - a_bool_t * enable); -typedef sw_error_t (*adpt_port_remote_loopback_set_func)(a_uint32_t dev_id, fal_port_t port_id, - a_bool_t enable); -typedef sw_error_t (*adpt_port_flowctrl_set_func)(a_uint32_t dev_id, fal_port_t port_id, - a_bool_t enable); -typedef sw_error_t (*adpt_port_mru_set_func)(a_uint32_t dev_id, fal_port_t port_id, - fal_mru_ctrl_t *ctrl); -typedef sw_error_t (*adpt_port_autoneg_status_get_func)(a_uint32_t dev_id, fal_port_t port_id, - a_bool_t * status); -typedef sw_error_t (*adpt_port_txmac_status_get_func)(a_uint32_t dev_id, fal_port_t port_id, - a_bool_t * enable); -typedef sw_error_t (*adpt_port_mdix_get_func)(a_uint32_t dev_id, fal_port_t port_id, - fal_port_mdix_mode_t * mode); -typedef sw_error_t (*adpt_ports_link_status_get_func)(a_uint32_t dev_id, a_uint32_t * status); -typedef sw_error_t (*adpt_port_mac_loopback_set_func)(a_uint32_t dev_id, fal_port_t port_id, - a_bool_t enable); -typedef sw_error_t (*adpt_port_phy_id_get_func)(a_uint32_t dev_id, fal_port_t port_id, - a_uint16_t * org_id, a_uint16_t * rev_id); -typedef sw_error_t (*adpt_port_mru_get_func)(a_uint32_t dev_id, fal_port_t port_id, - fal_mru_ctrl_t *ctrl); -typedef sw_error_t (*adpt_port_power_on_func)(a_uint32_t dev_id, fal_port_t port_id); -typedef sw_error_t (*adpt_port_speed_set_func)(a_uint32_t dev_id, fal_port_t port_id, - fal_port_speed_t speed); -typedef sw_error_t (*adpt_port_interface_mode_get_func)(a_uint32_t dev_id, fal_port_t port_id, - fal_port_interface_mode_t * mode); -typedef sw_error_t (*adpt_port_duplex_get_func)(a_uint32_t dev_id, fal_port_t port_id, - fal_port_duplex_t * pduplex); -typedef sw_error_t (*adpt_port_autoneg_adv_get_func)(a_uint32_t dev_id, fal_port_t port_id, - a_uint32_t * autoadv); -typedef sw_error_t (*adpt_port_mdix_status_get_func)(a_uint32_t dev_id, fal_port_t port_id, - fal_port_mdix_status_t * mode); -typedef sw_error_t (*adpt_port_mtu_set_func)(a_uint32_t dev_id, fal_port_t port_id, - fal_mtu_ctrl_t *ctrl); -typedef sw_error_t (*adpt_port_link_status_get_func)(a_uint32_t dev_id, fal_port_t port_id, - a_bool_t * status); -typedef sw_error_t (*adpt_port_8023az_set_func)(a_uint32_t dev_id, fal_port_t port_id, - a_bool_t enable); -typedef sw_error_t (*adpt_port_powersave_get_func)(a_uint32_t dev_id, fal_port_t port_id, - a_bool_t * enable); -typedef sw_error_t (*adpt_port_combo_prefer_medium_get_func)(a_uint32_t dev_id, - a_uint32_t port_id, - fal_port_medium_t * - medium); -typedef sw_error_t (*adpt_port_max_frame_size_get_func)(a_uint32_t dev_id, fal_port_t port_id, - a_uint32_t *max_frame); -typedef sw_error_t (*adpt_port_combo_prefer_medium_set_func)(a_uint32_t dev_id, - a_uint32_t port_id, - fal_port_medium_t medium); -typedef sw_error_t (*adpt_port_power_off_func)(a_uint32_t dev_id, fal_port_t port_id); -typedef sw_error_t (*adpt_port_txfc_status_set_func)(a_uint32_t dev_id, fal_port_t port_id, - a_bool_t enable); -typedef sw_error_t (*adpt_port_counter_set_func)(a_uint32_t dev_id, fal_port_t port_id, - a_bool_t enable); -typedef sw_error_t (*adpt_port_combo_fiber_mode_get_func)(a_uint32_t dev_id, - a_uint32_t port_id, - fal_port_fiber_mode_t * mode); -typedef sw_error_t (*adpt_port_local_loopback_set_func)(a_uint32_t dev_id, - fal_port_t port_id, - a_bool_t enable); -typedef sw_error_t (*adpt_port_wol_status_set_func)(a_uint32_t dev_id, fal_port_t port_id, - a_bool_t enable); -typedef sw_error_t (*adpt_port_magic_frame_mac_get_func)(a_uint32_t dev_id, fal_port_t port_id, - fal_mac_addr_t * mac); -typedef sw_error_t (*adpt_port_flowctrl_get_func)(a_uint32_t dev_id, fal_port_t port_id, - a_bool_t * enable); -typedef sw_error_t (*adpt_port_rxmac_status_set_func)(a_uint32_t dev_id, fal_port_t port_id, - a_bool_t enable); -typedef sw_error_t (*adpt_port_counter_get_func)(a_uint32_t dev_id, fal_port_t port_id, - a_bool_t * enable); -typedef sw_error_t (*adpt_port_interface_mode_set_func)(a_uint32_t dev_id, fal_port_t port_id, - fal_port_interface_mode_t mode); -typedef sw_error_t (*adpt_port_mac_loopback_get_func)(a_uint32_t dev_id, fal_port_t port_id, - a_bool_t * enable); -typedef sw_error_t (*adpt_port_hibernate_get_func)(a_uint32_t dev_id, fal_port_t port_id, - a_bool_t * enable); -typedef sw_error_t (*adpt_port_autoneg_adv_set_func)(a_uint32_t dev_id, fal_port_t port_id, - a_uint32_t autoadv); -typedef sw_error_t (*adpt_port_remote_loopback_get_func)(a_uint32_t dev_id, fal_port_t port_id, - a_bool_t * enable); -typedef sw_error_t (*adpt_port_counter_show_func)(a_uint32_t dev_id, fal_port_t port_id, - fal_port_counter_info_t * counter_info); -typedef sw_error_t (*adpt_port_autoneg_enable_func)(a_uint32_t dev_id, fal_port_t port_id); -typedef sw_error_t (*adpt_port_mtu_get_func)(a_uint32_t dev_id, fal_port_t port_id, - fal_mtu_ctrl_t *ctrl); -typedef sw_error_t (*adpt_port_interface_mode_status_get_func)(a_uint32_t dev_id, fal_port_t port_id, - fal_port_interface_mode_t * mode); -typedef sw_error_t (*adpt_port_reset_func)(a_uint32_t dev_id, fal_port_t port_id); -typedef sw_error_t (*adpt_port_rxfc_status_set_func)(a_uint32_t dev_id, fal_port_t port_id, - a_bool_t enable); -typedef sw_error_t (*adpt_port_speed_get_func)(a_uint32_t dev_id, fal_port_t port_id, - fal_port_speed_t * pspeed); -typedef sw_error_t (*adpt_port_mdix_set_func)(a_uint32_t dev_id, fal_port_t port_id, - fal_port_mdix_mode_t mode); -typedef sw_error_t (*adpt_port_wol_status_get_func)(a_uint32_t dev_id, fal_port_t port_id, - a_bool_t * enable); -typedef sw_error_t (*adpt_port_source_filter_get_func)(a_uint32_t dev_id, fal_port_t port_id, - a_bool_t * enable); -typedef sw_error_t (*adpt_port_source_filter_set_func)(a_uint32_t dev_id, fal_port_t port_id, - a_bool_t enable); -typedef sw_error_t (*adpt_port_mux_mac_type_set_func)(a_uint32_t dev_id, fal_port_t port_id, - a_uint32_t mode0, a_uint32_t mode1, a_uint32_t mode2); -typedef sw_error_t (*adpt_port_mac_speed_set_func)(a_uint32_t dev_id, fal_port_t port_id, - fal_port_speed_t speed); -typedef sw_error_t (*adpt_port_mac_duplex_set_func)(a_uint32_t dev_id, fal_port_t port_id, - fal_port_duplex_t duplex); -typedef sw_error_t (*adpt_port_polling_sw_sync_func)(struct qca_phy_priv *priv); - -typedef sw_error_t (*adpt_port_bridge_txmac_set_func)(a_uint32_t dev_id, - fal_port_t port_id, a_bool_t enable); - -typedef sw_error_t (*adpt_port_interface_mode_apply_func)(a_uint32_t dev_id); - -typedef sw_error_t (*adpt_port_interface_3az_status_set_func)(a_uint32_t dev_id, - a_uint32_t port_id, a_bool_t enable); -typedef sw_error_t (*adpt_port_interface_3az_status_get_func)(a_uint32_t dev_id, - a_uint32_t port_id, a_bool_t * enable); -typedef sw_error_t (*adpt_port_flowctrl_forcemode_set_func) (a_uint32_t dev_id, - fal_port_t port_id, a_bool_t enable); -typedef sw_error_t (*adpt_port_flowctrl_forcemode_get_func) (a_uint32_t dev_id, - fal_port_t port_id, a_bool_t * enable); -typedef sw_error_t (*adpt_port_promisc_mode_set_func)(a_uint32_t dev_id, - fal_port_t port_id, a_bool_t enable); -typedef sw_error_t (*adpt_port_promisc_mode_get_func)(a_uint32_t dev_id, - fal_port_t port_id, a_bool_t *enable); -typedef sw_error_t (*adpt_port_interface_eee_cfg_set_func)(a_uint32_t dev_id, - fal_port_t port_id, fal_port_eee_cfg_t *port_eee_cfg); -typedef sw_error_t (*adpt_port_interface_eee_cfg_get_func)(a_uint32_t dev_id, - fal_port_t port_id, fal_port_eee_cfg_t *port_eee_cfg); -typedef sw_error_t (*adpt_port_source_filter_config_set_func)(a_uint32_t dev_id, - fal_port_t port_id, fal_src_filter_config_t *src_filter_config); -typedef sw_error_t (*adpt_port_source_filter_config_get_func)(a_uint32_t dev_id, - fal_port_t port_id, fal_src_filter_config_t *src_filter_config); -typedef sw_error_t (*adpt_switch_port_loopback_set_func)(a_uint32_t dev_id, - fal_port_t port_id, fal_loopback_config_t *loopback_cfg); -typedef sw_error_t (*adpt_switch_port_loopback_get_func)(a_uint32_t dev_id, - fal_port_t port_id, fal_loopback_config_t *loopback_cfg); -typedef sw_error_t (*adpt_port_netdev_notify_func)(struct qca_phy_priv *priv, - a_uint32_t port_id); -typedef sw_error_t (*adpt_port_phy_status_get_func)(a_uint32_t dev_id, - fal_port_t port_id, struct port_phy_status *phy_status); -// mirror -typedef sw_error_t (*adpt_mirr_port_in_set_func)(a_uint32_t dev_id, fal_port_t port_id, - a_bool_t enable); -typedef sw_error_t (*adpt_mirr_port_in_get_func)(a_uint32_t dev_id, fal_port_t port_id, - a_bool_t * enable); -typedef sw_error_t (*adpt_mirr_port_eg_set_func)(a_uint32_t dev_id, fal_port_t port_id, - a_bool_t enable); -typedef sw_error_t (*adpt_mirr_port_eg_get_func)(a_uint32_t dev_id, fal_port_t port_id, - a_bool_t * enable); -typedef sw_error_t (*adpt_mirr_analysis_port_set_func)(a_uint32_t dev_id, fal_port_t port_id); -typedef sw_error_t (*adpt_mirr_analysis_port_get_func)(a_uint32_t dev_id, fal_port_t * port_id); -typedef sw_error_t (*adpt_mirr_analysis_config_set_func)(a_uint32_t dev_id, fal_mirr_direction_t direction, - fal_mirr_analysis_config_t * config); -typedef sw_error_t (*adpt_mirr_analysis_config_get_func)(a_uint32_t dev_id, fal_mirr_direction_t direction, - fal_mirr_analysis_config_t * config); - -//rss hash -typedef sw_error_t (*adpt_rss_hash_config_set_func)(a_uint32_t dev_id, fal_rss_hash_mode_t mode, fal_rss_hash_config_t * config); -typedef sw_error_t (*adpt_rss_hash_config_get_func)(a_uint32_t dev_id, fal_rss_hash_mode_t mode, fal_rss_hash_config_t * config); - -//trunk -typedef sw_error_t (*adpt_trunk_fail_over_en_get_func)(a_uint32_t dev_id, a_bool_t * fail_over); -typedef sw_error_t (*adpt_trunk_hash_mode_get_func)(a_uint32_t dev_id, a_uint32_t * hash_mode); -typedef sw_error_t (*adpt_trunk_group_get_func)(a_uint32_t dev_id, a_uint32_t trunk_id, - a_bool_t * enable, fal_pbmp_t * member); -typedef sw_error_t (*adpt_trunk_group_set_func)(a_uint32_t dev_id, a_uint32_t trunk_id, - a_bool_t enable, fal_pbmp_t member); -typedef sw_error_t (*adpt_trunk_fail_over_en_set_func)(a_uint32_t dev_id, a_bool_t fail_over); -typedef sw_error_t (*adpt_trunk_hash_mode_set_func)(a_uint32_t dev_id, a_uint32_t hash_mode); - -typedef sw_error_t (*adpt_ip_network_route_get_func)(a_uint32_t dev_id, - a_uint32_t index, a_uint8_t type, - fal_network_route_entry_t *entry); -typedef sw_error_t (*adpt_ip_network_route_add_func)(a_uint32_t dev_id, - a_uint32_t index, - fal_network_route_entry_t *entry); -typedef sw_error_t (*adpt_ip_network_route_del_func)(a_uint32_t dev_id, - a_uint32_t index, - a_uint8_t type); -typedef sw_error_t (*adpt_ip_host_add_func)( - a_uint32_t dev_id, fal_host_entry_t * host_entry); -typedef sw_error_t (*adpt_ip_vsi_sg_cfg_get_func)( - a_uint32_t dev_id, a_uint32_t vsi, - fal_sg_cfg_t *sg_cfg); -typedef sw_error_t (*adpt_ip_pub_addr_set_func)( - a_uint32_t dev_id, a_uint32_t index, - fal_ip_pub_addr_t *entry); -typedef sw_error_t (*adpt_ip_pub_addr_get_func)( - a_uint32_t dev_id, a_uint32_t index, - fal_ip_pub_addr_t *entry); -typedef sw_error_t (*adpt_ip_port_sg_cfg_set_func)( - a_uint32_t dev_id, fal_port_t port_id, - fal_sg_cfg_t *sg_cfg); -typedef sw_error_t (*adpt_ip_port_intf_get_func)( - a_uint32_t dev_id, fal_port_t port_id, fal_intf_id_t *id); -typedef sw_error_t (*adpt_ip_vsi_arp_sg_cfg_set_func)( - a_uint32_t dev_id, a_uint32_t vsi, - fal_arp_sg_cfg_t *arp_sg_cfg); -typedef sw_error_t (*adpt_ip_port_intf_set_func)( - a_uint32_t dev_id, fal_port_t port_id, fal_intf_id_t *id); -typedef sw_error_t (*adpt_ip_vsi_sg_cfg_set_func)( - a_uint32_t dev_id, a_uint32_t vsi, - fal_sg_cfg_t *sg_cfg); -typedef sw_error_t (*adpt_ip_host_next_func)( - a_uint32_t dev_id, a_uint32_t next_mode, - fal_host_entry_t * host_entry); -typedef sw_error_t (*adpt_ip_port_macaddr_set_func)(a_uint32_t dev_id, fal_port_t port_id, - fal_macaddr_entry_t *macaddr); -typedef sw_error_t (*adpt_ip_vsi_intf_get_func)( - a_uint32_t dev_id, a_uint32_t vsi, fal_intf_id_t *id); -typedef sw_error_t (*adpt_ip_port_sg_cfg_get_func)( - a_uint32_t dev_id, fal_port_t port_id, - fal_sg_cfg_t *sg_cfg); -typedef sw_error_t (*adpt_ip_intf_get_func)( - a_uint32_t dev_id, - a_uint32_t index, - fal_intf_entry_t *entry); -typedef sw_error_t (*adpt_ip_host_del_func)( - a_uint32_t dev_id, a_uint32_t del_mode, - fal_host_entry_t * host_entry); -typedef sw_error_t (*adpt_ip_route_mismatch_get_func)( - a_uint32_t dev_id, fal_fwd_cmd_t *cmd); -typedef sw_error_t (*adpt_ip_vsi_arp_sg_cfg_get_func)( - a_uint32_t dev_id, a_uint32_t vsi, - fal_arp_sg_cfg_t *arp_sg_cfg); -typedef sw_error_t (*adpt_ip_port_arp_sg_cfg_set_func)( - a_uint32_t dev_id, fal_port_t port_id, - fal_arp_sg_cfg_t *arp_sg_cfg); -typedef sw_error_t (*adpt_ip_vsi_mc_mode_set_func)( - a_uint32_t dev_id, a_uint32_t vsi, - fal_mc_mode_cfg_t *cfg); -typedef sw_error_t (*adpt_ip_vsi_intf_set_func)( - a_uint32_t dev_id, a_uint32_t vsi, fal_intf_id_t *id); -typedef sw_error_t (*adpt_ip_nexthop_get_func)(a_uint32_t dev_id, - a_uint32_t index, fal_ip_nexthop_t *entry); -typedef sw_error_t (*adpt_ip_route_mismatch_set_func)( - a_uint32_t dev_id, fal_fwd_cmd_t cmd); -typedef sw_error_t (*adpt_ip_host_get_func)( - a_uint32_t dev_id, a_uint32_t get_mode, - fal_host_entry_t * host_entry); -typedef sw_error_t (*adpt_ip_intf_set_func)( - a_uint32_t dev_id, - a_uint32_t index, - fal_intf_entry_t *entry); -typedef sw_error_t (*adpt_ip_vsi_mc_mode_get_func)( - a_uint32_t dev_id, - a_uint32_t vsi, - fal_mc_mode_cfg_t *cfg); -typedef sw_error_t (*adpt_ip_port_macaddr_get_func)( - a_uint32_t dev_id, fal_port_t port_id, - fal_macaddr_entry_t *macaddr); -typedef sw_error_t (*adpt_ip_port_arp_sg_cfg_get_func)( - a_uint32_t dev_id, fal_port_t port_id, - fal_arp_sg_cfg_t *arp_sg_cfg); -typedef sw_error_t (*adpt_ip_nexthop_set_func)(a_uint32_t dev_id, - a_uint32_t index, fal_ip_nexthop_t *entry); -typedef sw_error_t (*adpt_ip_global_ctrl_get_func)(a_uint32_t dev_id, - fal_ip_global_cfg_t *cfg); -typedef sw_error_t (*adpt_ip_global_ctrl_set_func)(a_uint32_t dev_id, - fal_ip_global_cfg_t *cfg); - -typedef sw_error_t (*adpt_flow_global_cfg_get_func)( - a_uint32_t dev_id, - fal_flow_global_cfg_t *cfg); -typedef sw_error_t (*adpt_flow_global_cfg_set_func)( - a_uint32_t dev_id, - fal_flow_global_cfg_t *cfg); -typedef sw_error_t (*adpt_flow_host_add_func)( - a_uint32_t dev_id, - a_uint32_t add_mode, - fal_flow_host_entry_t *flow_host_entry); -typedef sw_error_t (*adpt_flow_entry_get_func)( - a_uint32_t dev_id, - a_uint32_t get_mode, - fal_flow_entry_t *flow_entry); -typedef sw_error_t (*adpt_flow_entry_del_func)( - a_uint32_t dev_id, - a_uint32_t del_mode, - fal_flow_entry_t *flow_entry); -typedef sw_error_t (*adpt_flow_entry_next_func)( - a_uint32_t dev_id, - a_uint32_t next_mode, - fal_flow_entry_t *flow_entry); -typedef sw_error_t (*adpt_flow_status_get_func)( - a_uint32_t dev_id, a_bool_t *enable); -typedef sw_error_t (*adpt_flow_ctrl_set_func)( - a_uint32_t dev_id, - fal_flow_pkt_type_t type, - fal_flow_direction_t dir, - fal_flow_mgmt_t *ctrl); -typedef sw_error_t (*adpt_flow_age_timer_get_func)( - a_uint32_t dev_id, fal_flow_age_timer_t *age_timer); -typedef sw_error_t (*adpt_flow_status_set_func)( - a_uint32_t dev_id, a_bool_t enable); -typedef sw_error_t (*adpt_flow_host_get_func)( - a_uint32_t dev_id, - a_uint32_t get_mode, - fal_flow_host_entry_t *flow_host_entry); -typedef sw_error_t (*adpt_flow_host_del_func)( - a_uint32_t dev_id, - a_uint32_t del_mode, - fal_flow_host_entry_t *flow_host_entry); -typedef sw_error_t (*adpt_flow_ctrl_get_func)( - a_uint32_t dev_id, - fal_flow_pkt_type_t type, - fal_flow_direction_t dir, - fal_flow_mgmt_t *ctrl); -typedef sw_error_t (*adpt_flow_age_timer_set_func)( - a_uint32_t dev_id, fal_flow_age_timer_t *age_timer); -typedef sw_error_t (*adpt_flow_entry_add_func)( - a_uint32_t dev_id, - a_uint32_t add_mode, /*index or hash*/ - fal_flow_entry_t *flow_entry); -typedef sw_error_t (*adpt_ucast_hash_map_set_func)( - a_uint32_t dev_id, - a_uint8_t profile, - a_uint8_t rss_hash, - a_int8_t queue_hash); -typedef sw_error_t (*adpt_ac_dynamic_threshold_get_func)( - a_uint32_t dev_id, - a_uint32_t queue_id, - fal_ac_dynamic_threshold_t *cfg); -typedef sw_error_t (*adpt_ucast_queue_base_profile_get_func)( - a_uint32_t dev_id, - fal_ucast_queue_dest_t *queue_dest, - a_uint32_t *queue_base, a_uint8_t *profile); -typedef sw_error_t (*adpt_port_mcast_priority_class_get_func)( - a_uint32_t dev_id, - fal_port_t port, - a_uint8_t priority, - a_uint8_t *queue_class); -typedef sw_error_t (*adpt_ac_dynamic_threshold_set_func)( - a_uint32_t dev_id, - a_uint32_t queue_id, - fal_ac_dynamic_threshold_t *cfg); -typedef sw_error_t (*adpt_ac_prealloc_buffer_set_func)( - a_uint32_t dev_id, - fal_ac_obj_t *obj, - a_uint16_t num); -typedef sw_error_t (*adpt_ucast_default_hash_get_func)( - a_uint32_t dev_id, - a_uint8_t *hash_value); -typedef sw_error_t (*adpt_ucast_default_hash_set_func)( - a_uint32_t dev_id, - a_uint8_t hash_value); -typedef sw_error_t (*adpt_ac_queue_group_get_func)( - a_uint32_t dev_id, - a_uint32_t queue_id, - a_uint8_t *group_id); -typedef sw_error_t (*adpt_ac_ctrl_get_func)( - a_uint32_t dev_id, - fal_ac_obj_t *obj, - fal_ac_ctrl_t *cfg); -typedef sw_error_t (*adpt_ac_prealloc_buffer_get_func)( - a_uint32_t dev_id, - fal_ac_obj_t *obj, - a_uint16_t *num); -typedef sw_error_t (*adpt_port_mcast_priority_class_set_func)( - a_uint32_t dev_id, - fal_port_t port, - a_uint8_t priority, - a_uint8_t queue_class); -typedef sw_error_t (*adpt_ucast_hash_map_get_func)( - a_uint32_t dev_id, - a_uint8_t profile, - a_uint8_t rss_hash, - a_int8_t *queue_hash); -typedef sw_error_t (*adpt_ac_static_threshold_set_func)( - a_uint32_t dev_id, - fal_ac_obj_t *obj, - fal_ac_static_threshold_t *cfg); -typedef sw_error_t (*adpt_ac_queue_group_set_func)( - a_uint32_t dev_id, - a_uint32_t queue_id, - a_uint8_t group_id); -typedef sw_error_t (*adpt_ac_group_buffer_get_func)( - a_uint32_t dev_id, - a_uint8_t group_id, - fal_ac_group_buffer_t *cfg); -typedef sw_error_t (*adpt_mcast_cpu_code_class_get_func)( - a_uint32_t dev_id, - a_uint8_t cpu_code, - a_uint8_t *queue_class); -typedef sw_error_t (*adpt_ac_ctrl_set_func)( - a_uint32_t dev_id, - fal_ac_obj_t *obj, - fal_ac_ctrl_t *cfg); -typedef sw_error_t (*adpt_ucast_priority_class_get_func)( - a_uint32_t dev_id, - a_uint8_t profile, - a_uint8_t priority, - a_uint8_t *class); -typedef sw_error_t (*adpt_queue_flush_func)( - a_uint32_t dev_id, - fal_port_t port, - a_uint16_t queue_id); -typedef sw_error_t (*adpt_mcast_cpu_code_class_set_func)( - a_uint32_t dev_id, - a_uint8_t cpu_code, - a_uint8_t queue_class); -typedef sw_error_t (*adpt_ucast_priority_class_set_func)( - a_uint32_t dev_id, - a_uint8_t profile, - a_uint8_t priority, - a_uint8_t class); -typedef sw_error_t (*adpt_ac_static_threshold_get_func)( - a_uint32_t dev_id, - fal_ac_obj_t *obj, - fal_ac_static_threshold_t *cfg); -typedef sw_error_t (*adpt_ucast_queue_base_profile_set_func)( - a_uint32_t dev_id, - fal_ucast_queue_dest_t *queue_dest, - a_uint32_t queue_base, a_uint8_t profile); -typedef sw_error_t (*adpt_ac_group_buffer_set_func)( - a_uint32_t dev_id, - a_uint8_t group_id, - fal_ac_group_buffer_t *cfg); -typedef sw_error_t (*adpt_queue_counter_cleanup_func)( - a_uint32_t dev_id, a_uint32_t queue_id); -typedef sw_error_t (*adpt_queue_counter_get_func)( - a_uint32_t dev_id, a_uint32_t queue_id, - fal_queue_stats_t *info); -typedef sw_error_t (*adpt_queue_counter_ctrl_get_func)( - a_uint32_t dev_id, a_bool_t *cnt_en); -typedef sw_error_t (*adpt_queue_counter_ctrl_set_func)( - a_uint32_t dev_id, a_bool_t cnt_en); -typedef sw_error_t (*adpt_qm_enqueue_ctrl_set_func)( - a_uint32_t dev_id, a_uint32_t queue_id, a_bool_t enable); -typedef sw_error_t (*adpt_qm_enqueue_ctrl_get_func)( - a_uint32_t dev_id, a_uint32_t queue_id, a_bool_t *enable); -typedef sw_error_t (*adpt_qm_port_source_profile_set_func)( - a_uint32_t dev_id, fal_port_t port, a_uint32_t src_profile); -typedef sw_error_t (*adpt_qm_port_source_profile_get_func)( - a_uint32_t dev_id, fal_port_t port, a_uint32_t *src_profile); - - -/*portvlan module begin*/ -typedef sw_error_t (*adpt_global_qinq_mode_set_func)(a_uint32_t dev_id, fal_global_qinq_mode_t *mode); -typedef sw_error_t (*adpt_global_qinq_mode_get_func)(a_uint32_t dev_id, fal_global_qinq_mode_t *mode); -typedef sw_error_t (*adpt_tpid_set_func)(a_uint32_t dev_id, fal_tpid_t *tpid); -typedef sw_error_t (*adpt_tpid_get_func)(a_uint32_t dev_id, fal_tpid_t *tpid); -typedef sw_error_t (*adpt_egress_tpid_set_func)(a_uint32_t dev_id, fal_tpid_t *tpid); -typedef sw_error_t (*adpt_egress_tpid_get_func)(a_uint32_t dev_id, fal_tpid_t *tpid); -typedef sw_error_t (*adpt_port_qinq_mode_set_func)(a_uint32_t dev_id, fal_port_t port_id, fal_port_qinq_role_t *mode); -typedef sw_error_t (*adpt_port_qinq_mode_get_func)(a_uint32_t dev_id, fal_port_t port_id, fal_port_qinq_role_t *mode); -typedef sw_error_t (*adpt_port_ingress_vlan_filter_set_func)(a_uint32_t dev_id, fal_port_t port_id, fal_ingress_vlan_filter_t *filter); -typedef sw_error_t (*adpt_port_ingress_vlan_filter_get_func)(a_uint32_t dev_id, fal_port_t port_id, fal_ingress_vlan_filter_t *filter); -typedef sw_error_t (*adpt_port_default_vlantag_set_func)(a_uint32_t dev_id, fal_port_t port_id, fal_port_vlan_direction_t direction, - fal_port_default_vid_enable_t *default_vid_en, fal_port_vlan_tag_t *default_tag); -typedef sw_error_t (*adpt_port_default_vlantag_get_func)(a_uint32_t dev_id, fal_port_t port_id, fal_port_vlan_direction_t direction, - fal_port_default_vid_enable_t *default_vid_en, fal_port_vlan_tag_t *default_tag); -typedef sw_error_t (*adpt_port_tag_propagation_set_func)(a_uint32_t dev_id, fal_port_t port_id, fal_port_vlan_direction_t direction, - fal_vlantag_propagation_t *prop); -typedef sw_error_t (*adpt_port_tag_propagation_get_func)(a_uint32_t dev_id, fal_port_t port_id, fal_port_vlan_direction_t direction, - fal_vlantag_propagation_t *prop); -typedef sw_error_t (*adpt_port_vlantag_egmode_set_func)(a_uint32_t dev_id, fal_port_t port_id, - fal_vlantag_egress_mode_t *port_egvlanmode); -typedef sw_error_t (*adpt_port_vlantag_egmode_get_func)(a_uint32_t dev_id, fal_port_t port_id, - fal_vlantag_egress_mode_t *port_egvlanmode); -typedef sw_error_t (*adpt_port_vlan_xlt_miss_cmd_get_func)(a_uint32_t dev_id, fal_port_t port_id, - fal_fwd_cmd_t *cmd); -typedef sw_error_t (*adpt_port_vlan_xlt_miss_cmd_set_func)(a_uint32_t dev_id, fal_port_t port_id, - fal_fwd_cmd_t cmd); -typedef sw_error_t (*adpt_port_vlan_trans_add_func)(a_uint32_t dev_id, fal_port_t port_id, fal_vlan_trans_entry_t *entry); -typedef sw_error_t (*adpt_port_vlan_trans_get_func)(a_uint32_t dev_id, fal_port_t port_id, fal_vlan_trans_entry_t *entry); -typedef sw_error_t (*adpt_port_vlan_trans_del_func)(a_uint32_t dev_id, fal_port_t port_id, fal_vlan_trans_entry_t *entry); -typedef sw_error_t (*adpt_port_vlan_trans_iterate_func)(a_uint32_t dev_id, fal_port_t port_id, - a_uint32_t * iterator, fal_vlan_trans_entry_t *entry); -typedef sw_error_t (*adpt_port_vsi_egmode_set_func)(a_uint32_t dev_id, a_uint32_t vsi, a_uint32_t port_id, fal_pt_1q_egmode_t egmode); -typedef sw_error_t (*adpt_port_vsi_egmode_get_func)(a_uint32_t dev_id, a_uint32_t vsi, a_uint32_t port_id, fal_pt_1q_egmode_t * egmode); -typedef sw_error_t (*adpt_port_vlantag_vsi_egmode_enable_set_func)(a_uint32_t dev_id, fal_port_t port_id, a_bool_t enable); -typedef sw_error_t (*adpt_port_vlantag_vsi_egmode_enable_get_func)(a_uint32_t dev_id, fal_port_t port_id, a_bool_t * enable); -typedef sw_error_t (*adpt_qinq_mode_set_func)(a_uint32_t dev_id, fal_qinq_mode_t mode); -typedef sw_error_t (*adpt_qinq_mode_get_func)(a_uint32_t dev_id, fal_qinq_mode_t * mode); -typedef sw_error_t (*adpt_port_qinq_role_set_func)(a_uint32_t dev_id, fal_port_t port_id, fal_qinq_port_role_t role); -typedef sw_error_t (*adpt_port_qinq_role_get_func)(a_uint32_t dev_id, fal_port_t port_id, fal_qinq_port_role_t * role); -typedef sw_error_t (*adpt_port_invlan_mode_set_func)(a_uint32_t dev_id, fal_port_t port_id, fal_pt_invlan_mode_t mode); -typedef sw_error_t (*adpt_port_invlan_mode_get_func)(a_uint32_t dev_id, fal_port_t port_id, fal_pt_invlan_mode_t * mode); -typedef sw_error_t (*adpt_port_vlan_trans_adv_add_func)(a_uint32_t dev_id, fal_port_t port_id, fal_port_vlan_direction_t direction, - fal_vlan_trans_adv_rule_t * rule, fal_vlan_trans_adv_action_t * action); -typedef sw_error_t (*adpt_port_vlan_trans_adv_del_func)(a_uint32_t dev_id, fal_port_t port_id, fal_port_vlan_direction_t direction, - fal_vlan_trans_adv_rule_t * rule, fal_vlan_trans_adv_action_t * action); -typedef sw_error_t (*adpt_port_vlan_trans_adv_getfirst_func)(a_uint32_t dev_id, fal_port_t port_id, fal_port_vlan_direction_t direction, - fal_vlan_trans_adv_rule_t * rule, fal_vlan_trans_adv_action_t * action); -typedef sw_error_t (*adpt_port_vlan_trans_adv_getnext_func)(a_uint32_t dev_id, fal_port_t port_id, fal_port_vlan_direction_t direction, - fal_vlan_trans_adv_rule_t * rule, fal_vlan_trans_adv_action_t * action); -typedef sw_error_t (*adpt_port_vlan_counter_get_func)(a_uint32_t dev_id, a_uint32_t cnt_index, fal_port_vlan_counter_t * counter); -typedef sw_error_t (*adpt_port_vlan_counter_cleanup_func)(a_uint32_t dev_id, a_uint32_t cnt_index); -typedef sw_error_t (*adpt_portvlan_member_add_func)(a_uint32_t dev_id, fal_port_t port_id, fal_port_t mem_port_id); -typedef sw_error_t (*adpt_portvlan_member_del_func)(a_uint32_t dev_id, fal_port_t port_id, fal_port_t mem_port_id); -typedef sw_error_t (*adpt_portvlan_member_update_func)(a_uint32_t dev_id, fal_port_t port_id, fal_pbmp_t mem_port_map); -typedef sw_error_t (*adpt_portvlan_member_get_func)(a_uint32_t dev_id, fal_port_t port_id, fal_pbmp_t * mem_port_map); -/*portvlan module end*/ - -/*ctrlpkt module end*/ -typedef sw_error_t (*adpt_mgmtctrl_ethtype_profile_set_func)(a_uint32_t dev_id, a_uint32_t profile_id, a_uint32_t ethtype); -typedef sw_error_t (*adpt_mgmtctrl_ethtype_profile_get_func)(a_uint32_t dev_id, a_uint32_t profile_id, a_uint32_t * ethtype); -typedef sw_error_t (*adpt_mgmtctrl_rfdb_profile_set_func)(a_uint32_t dev_id, a_uint32_t profile_id, fal_mac_addr_t *addr); -typedef sw_error_t (*adpt_mgmtctrl_rfdb_profile_get_func)(a_uint32_t dev_id, a_uint32_t profile_id, fal_mac_addr_t *addr); -typedef sw_error_t (*adpt_mgmtctrl_ctrlpkt_profile_add_func)(a_uint32_t dev_id, fal_ctrlpkt_profile_t *ctrlpkt); -typedef sw_error_t (*adpt_mgmtctrl_ctrlpkt_profile_del_func)(a_uint32_t dev_id, fal_ctrlpkt_profile_t *ctrlpkt); -typedef sw_error_t (*adpt_mgmtctrl_ctrlpkt_profile_getfirst_func)(a_uint32_t dev_id, fal_ctrlpkt_profile_t *ctrlpkt); -typedef sw_error_t (*adpt_mgmtctrl_ctrlpkt_profile_getnext_func)(a_uint32_t dev_id, fal_ctrlpkt_profile_t *ctrlpkt); -/*ctrlpkt module end*/ - -/*service module end*/ -typedef sw_error_t (*adpt_servcode_config_set_func)(a_uint32_t dev_id, - a_uint32_t servcode_index, fal_servcode_config_t *entry); -typedef sw_error_t (*adpt_servcode_config_get_func)(a_uint32_t dev_id, - a_uint32_t servcode_index, fal_servcode_config_t *entry); -typedef sw_error_t (*adpt_servcode_loopcheck_en_func)(a_uint32_t dev_id, a_bool_t enable); -typedef sw_error_t (*adpt_servcode_loopcheck_status_get_func)(a_uint32_t dev_id, a_bool_t *enable); -/*service module end*/ - -//pppoe -typedef sw_error_t (*adpt_pppoe_session_table_add_func)( - a_uint32_t dev_id, - fal_pppoe_session_t * session_tbl); -typedef sw_error_t (*adpt_pppoe_session_table_del_func)( - a_uint32_t dev_id, - fal_pppoe_session_t * session_tbl); -typedef sw_error_t (*adpt_pppoe_session_table_get_func)( - a_uint32_t dev_id, - fal_pppoe_session_t * session_tbl); -typedef sw_error_t (*adpt_pppoe_en_set_func)( - a_uint32_t dev_id, - a_uint32_t l3_if, - a_uint32_t enable); -typedef sw_error_t (*adpt_pppoe_en_get_func)( - a_uint32_t dev_id, - a_uint32_t l3_if, - a_uint32_t *enable); - -typedef sw_error_t (*adpt_sec_l3_excep_parser_ctrl_set_func)( - a_uint32_t dev_id, - fal_l3_excep_parser_ctrl *ctrl); -typedef sw_error_t (*adpt_sec_l3_excep_ctrl_get_func)( - a_uint32_t dev_id, a_uint32_t excep_type, fal_l3_excep_ctrl_t *ctrl); -typedef sw_error_t (*adpt_sec_l3_excep_parser_ctrl_get_func)( - a_uint32_t dev_id, fal_l3_excep_parser_ctrl *ctrl); -typedef sw_error_t (*adpt_sec_l4_excep_parser_ctrl_set_func)( - a_uint32_t dev_id, fal_l4_excep_parser_ctrl *ctrl); -typedef sw_error_t (*adpt_sec_l3_excep_ctrl_set_func)( - a_uint32_t dev_id, a_uint32_t excep_type, fal_l3_excep_ctrl_t *ctrl); -typedef sw_error_t (*adpt_sec_l4_excep_parser_ctrl_get_func)( - a_uint32_t dev_id, fal_l4_excep_parser_ctrl *ctrl); - -typedef sw_error_t (*adpt_acl_list_bind_func)(a_uint32_t dev_id, a_uint32_t list_id, fal_acl_direc_t direc, fal_acl_bind_obj_t obj_t, a_uint32_t obj_idx); -typedef sw_error_t (*adpt_acl_list_dump_func)(a_uint32_t dev_id); -typedef sw_error_t (*adpt_acl_udf_profile_set_func)(a_uint32_t dev_id, fal_acl_udf_pkt_type_t pkt_type,a_uint32_t udf_idx, fal_acl_udf_type_t udf_type, a_uint32_t offset); -typedef sw_error_t (*adpt_acl_rule_query_func)(a_uint32_t dev_id, a_uint32_t list_id, a_uint32_t rule_id, fal_acl_rule_t * rule); -typedef sw_error_t (*adpt_acl_list_unbind_func)(a_uint32_t dev_id, a_uint32_t list_id, fal_acl_direc_t direc, fal_acl_bind_obj_t obj_t, a_uint32_t obj_idx); -typedef sw_error_t (*adpt_acl_rule_add_func)(a_uint32_t dev_id, a_uint32_t list_id, a_uint32_t rule_id, a_uint32_t rule_nr, fal_acl_rule_t * rule); -typedef sw_error_t (*adpt_acl_rule_delete_func)(a_uint32_t dev_id, a_uint32_t list_id, a_uint32_t rule_id, a_uint32_t rule_nr); -typedef sw_error_t (*adpt_acl_rule_dump_func)(a_uint32_t dev_id); -typedef sw_error_t (*adpt_acl_udf_profile_get_func)(a_uint32_t dev_id, fal_acl_udf_pkt_type_t pkt_type,a_uint32_t udf_idx, fal_acl_udf_type_t *udf_type, a_uint32_t *offset); -typedef sw_error_t (*adpt_acl_list_creat_func)(a_uint32_t dev_id, a_uint32_t list_id, a_uint32_t list_pri); -typedef sw_error_t (*adpt_acl_list_destroy_func)(a_uint32_t dev_id, a_uint32_t list_id); - -typedef sw_error_t (*adpt_qos_port_pri_set_func)(a_uint32_t dev_id, fal_port_t port_id, - fal_qos_pri_precedence_t *pri); -typedef sw_error_t (*adpt_qos_port_pri_get_func)(a_uint32_t dev_id, fal_port_t port_id, - fal_qos_pri_precedence_t *pri); -typedef sw_error_t (*adpt_qos_cosmap_pcp_get_func)(a_uint32_t dev_id, a_uint8_t group_id, - a_uint8_t pcp, fal_qos_cosmap_t *cosmap); -typedef sw_error_t (*adpt_queue_scheduler_set_func)(a_uint32_t dev_id, - a_uint32_t node_id, - fal_queue_scheduler_level_t level, - fal_port_t port_id, - fal_qos_scheduler_cfg_t *scheduler_cfg); -typedef sw_error_t (*adpt_queue_scheduler_get_func)(a_uint32_t dev_id, - a_uint32_t node_id, - fal_queue_scheduler_level_t level, - fal_port_t *port_id, - fal_qos_scheduler_cfg_t *scheduler_cfg); -typedef sw_error_t (*adpt_port_queues_get_func)(a_uint32_t dev_id, - fal_port_t port_id, - fal_queue_bmp_t *queue_bmp); -typedef sw_error_t (*adpt_qos_cosmap_pcp_set_func)(a_uint32_t dev_id, a_uint8_t group_id, - a_uint8_t pcp, fal_qos_cosmap_t *cosmap); -typedef sw_error_t (*adpt_qos_port_remark_get_func)(a_uint32_t dev_id, fal_port_t port_id, - fal_qos_remark_enable_t *remark); -typedef sw_error_t (*adpt_qos_cosmap_dscp_get_func)(a_uint32_t dev_id, a_uint8_t group_id, - a_uint8_t dscp, fal_qos_cosmap_t *cosmap); -typedef sw_error_t (*adpt_qos_cosmap_flow_set_func)(a_uint32_t dev_id, a_uint8_t group_id, - a_uint16_t flow, fal_qos_cosmap_t *cosmap); -typedef sw_error_t (*adpt_qos_port_group_set_func)(a_uint32_t dev_id, fal_port_t port_id, - fal_qos_group_t *group); -typedef sw_error_t (*adpt_ring_queue_map_set_func)(a_uint32_t dev_id, - a_uint32_t ring_id, fal_queue_bmp_t *queue_bmp); -typedef sw_error_t (*adpt_qos_cosmap_dscp_set_func)(a_uint32_t dev_id, a_uint8_t group_id, - a_uint8_t dscp, fal_qos_cosmap_t *cosmap); -typedef sw_error_t (*adpt_qos_port_remark_set_func)(a_uint32_t dev_id, fal_port_t port_id, - fal_qos_remark_enable_t *remark); -typedef sw_error_t (*adpt_qos_cosmap_flow_get_func)(a_uint32_t dev_id, a_uint8_t group_id, - a_uint16_t flow, fal_qos_cosmap_t *cosmap); -typedef sw_error_t (*adpt_qos_port_group_get_func)(a_uint32_t dev_id, fal_port_t port_id, - fal_qos_group_t *group); -typedef sw_error_t (*adpt_ring_queue_map_get_func)(a_uint32_t dev_id, - a_uint32_t ring_id, fal_queue_bmp_t *queue_bmp); - -//shaper - -typedef sw_error_t (*adpt_flow_shaper_set_func)(a_uint32_t dev_id, a_uint32_t flow_id, - fal_shaper_config_t * shaper); -typedef sw_error_t (*adpt_queue_shaper_get_func)(a_uint32_t dev_id, a_uint32_t queue_id, - fal_shaper_config_t * shaper); -typedef sw_error_t (*adpt_queue_shaper_token_number_set_func)(a_uint32_t dev_id,a_uint32_t queue_id, - fal_shaper_token_number_t *token_number); -typedef sw_error_t (*adpt_port_shaper_get_func)(a_uint32_t dev_id, fal_port_t port_id, - fal_shaper_config_t * shaper); -typedef sw_error_t (*adpt_flow_shaper_time_slot_get_func)(a_uint32_t dev_id, a_uint32_t *time_slot); -typedef sw_error_t (*adpt_port_shaper_time_slot_get_func)(a_uint32_t dev_id, a_uint32_t *time_slot); -typedef sw_error_t (*adpt_flow_shaper_time_slot_set_func)(a_uint32_t dev_id, a_uint32_t time_slot); -typedef sw_error_t (*adpt_port_shaper_token_number_set_func)(a_uint32_t dev_id, fal_port_t port_id, - fal_shaper_token_number_t *token_number); -typedef sw_error_t (*adpt_queue_shaper_token_number_get_func)(a_uint32_t dev_id, a_uint32_t queue_id, - fal_shaper_token_number_t *token_number); -typedef sw_error_t (*adpt_queue_shaper_time_slot_get_func)(a_uint32_t dev_id, a_uint32_t *time_slot); -typedef sw_error_t (*adpt_port_shaper_token_number_get_func)(a_uint32_t dev_id, fal_port_t port_id, - fal_shaper_token_number_t *token_number); -typedef sw_error_t (*adpt_flow_shaper_token_number_set_func)(a_uint32_t dev_id, a_uint32_t flow_id, - fal_shaper_token_number_t *token_number); -typedef sw_error_t (*adpt_flow_shaper_token_number_get_func)(a_uint32_t dev_id, a_uint32_t flow_id, - fal_shaper_token_number_t *token_number); -typedef sw_error_t (*adpt_port_shaper_set_func)(a_uint32_t dev_id, fal_port_t port_id, - fal_shaper_config_t * shaper); -typedef sw_error_t (*adpt_port_shaper_time_slot_set_func)(a_uint32_t dev_id, a_uint32_t time_slot); -typedef sw_error_t (*adpt_flow_shaper_get_func)(a_uint32_t dev_id, a_uint32_t flow_id, - fal_shaper_config_t * shaper); -typedef sw_error_t (*adpt_queue_shaper_set_func)(a_uint32_t dev_id,a_uint32_t queue_id, - fal_shaper_config_t * shaper); -typedef sw_error_t (*adpt_queue_shaper_time_slot_set_func)(a_uint32_t dev_id, a_uint32_t time_slot); -typedef sw_error_t (*adpt_shaper_ipg_preamble_length_get_func)(a_uint32_t dev_id, a_uint32_t *ipg_pre_length); -typedef sw_error_t (*adpt_shaper_ipg_preamble_length_set_func)(a_uint32_t dev_id, a_uint32_t ipg_pre_length); - -typedef sw_error_t (*adpt_tdm_tick_num_set_func)(a_uint32_t dev_id, a_uint32_t tick_num); -typedef sw_error_t (*adpt_tdm_tick_num_get_func)(a_uint32_t dev_id, a_uint32_t *tick_num); -typedef sw_error_t (*adpt_port_scheduler_cfg_set_func)(a_uint32_t dev_id, a_uint32_t tick_index, - fal_port_scheduler_cfg_t *cfg); -typedef sw_error_t (*adpt_port_scheduler_cfg_reset_func)(a_uint32_t dev_id, fal_port_t port_id); -typedef sw_error_t (*adpt_port_scheduler_cfg_get_func)(a_uint32_t dev_id, a_uint32_t tick_index, - fal_port_scheduler_cfg_t *cfg); -typedef sw_error_t (*adpt_scheduler_dequeue_ctrl_get_func)(a_uint32_t dev_id, a_uint32_t queue_id, - a_bool_t *enable); -typedef sw_error_t (*adpt_scheduler_dequeue_ctrl_set_func)(a_uint32_t dev_id, a_uint32_t queue_id, - a_bool_t enable); -typedef sw_error_t (*adpt_qos_port_mode_pri_get_func)(a_uint32_t dev_id, fal_port_t port_id, - fal_qos_mode_t mode, a_uint32_t *pri); -typedef sw_error_t (*adpt_qos_port_mode_pri_set_func)(a_uint32_t dev_id, fal_port_t port_id, - fal_qos_mode_t mode, a_uint32_t pri); -typedef sw_error_t (*adpt_port_scheduler_resource_get_func)(a_uint32_t dev_id, fal_port_t port_id, - fal_portscheduler_resource_t *cfg); -typedef sw_error_t (*adpt_port_bufgroup_map_get_func)(a_uint32_t dev_id, fal_port_t port, - a_uint8_t *group); -typedef sw_error_t (*adpt_bm_port_reserved_buffer_get_func)(a_uint32_t dev_id, fal_port_t port, - a_uint16_t *prealloc_buff, a_uint16_t *react_buff); -typedef sw_error_t (*adpt_bm_bufgroup_buffer_get_func)(a_uint32_t dev_id, a_uint8_t group, - a_uint16_t *buff_num); -typedef sw_error_t (*adpt_bm_port_dynamic_thresh_get_func)(a_uint32_t dev_id, fal_port_t port, - fal_bm_dynamic_cfg_t *cfg); -typedef sw_error_t (*adpt_port_bm_ctrl_get_func)(a_uint32_t dev_id, fal_port_t port, a_bool_t *enable); -typedef sw_error_t (*adpt_bm_bufgroup_buffer_set_func)(a_uint32_t dev_id, a_uint8_t group, - a_uint16_t buff_num); -typedef sw_error_t (*adpt_port_bufgroup_map_set_func)(a_uint32_t dev_id, fal_port_t port, - a_uint8_t group); -typedef sw_error_t (*adpt_bm_port_static_thresh_get_func)(a_uint32_t dev_id, fal_port_t port, - fal_bm_static_cfg_t *cfg); -typedef sw_error_t (*adpt_bm_port_reserved_buffer_set_func)(a_uint32_t dev_id, fal_port_t port, - a_uint16_t prealloc_buff, a_uint16_t react_buff); -typedef sw_error_t (*adpt_bm_port_static_thresh_set_func)(a_uint32_t dev_id, fal_port_t port, - fal_bm_static_cfg_t *cfg); -typedef sw_error_t (*adpt_bm_port_dynamic_thresh_set_func)(a_uint32_t dev_id, fal_port_t port, - fal_bm_dynamic_cfg_t *cfg); -typedef sw_error_t (*adpt_port_bm_ctrl_set_func)(a_uint32_t dev_id, fal_port_t port, a_bool_t enable); -typedef sw_error_t (*adpt_port_tdm_ctrl_set_func)(a_uint32_t dev_id, fal_port_tdm_ctrl_t *ctrl); -typedef sw_error_t (*adpt_port_tdm_tick_cfg_set_func)(a_uint32_t dev_id, a_uint32_t tick_index, - fal_port_tdm_tick_cfg_t *cfg); -typedef sw_error_t (*adpt_bm_port_counter_get_func)(a_uint32_t dev_id, fal_port_t port, - fal_bm_port_counter_t *counter); - -//policer -typedef sw_error_t (*adpt_acl_policer_counter_get_func)(a_uint32_t dev_id, a_uint32_t index, - fal_policer_counter_t *counter); -typedef sw_error_t (*adpt_port_policer_counter_get_func)(a_uint32_t dev_id, fal_port_t port_id, - fal_policer_counter_t *counter); -typedef sw_error_t (*adpt_port_compensation_byte_get_func)(a_uint32_t dev_id, fal_port_t port_id, - a_uint32_t *length); -typedef sw_error_t (*adpt_port_policer_entry_get_func)(a_uint32_t dev_id, fal_port_t port_id, - fal_policer_config_t *policer, fal_policer_action_t *ation); -typedef sw_error_t (*adpt_port_policer_entry_set_func)(a_uint32_t dev_id, fal_port_t port_id, - fal_policer_config_t *policer, fal_policer_action_t *ation); -typedef sw_error_t (*adpt_acl_policer_entry_get_func)(a_uint32_t dev_id, a_uint32_t index, - fal_policer_config_t *policer, fal_policer_action_t *ation); -typedef sw_error_t (*adpt_acl_policer_entry_set_func)(a_uint32_t dev_id, a_uint32_t index, - fal_policer_config_t *policer, fal_policer_action_t *ation); -typedef sw_error_t (*adpt_policer_time_slot_get_func)(a_uint32_t dev_id, a_uint32_t *time_slot); -typedef sw_error_t (*adpt_port_compensation_byte_set_func)(a_uint32_t dev_id, fal_port_t port_id, - a_uint32_t length); -typedef sw_error_t (*adpt_policer_time_slot_set_func)(a_uint32_t dev_id, a_uint32_t time_slot); - -typedef sw_error_t (*adpt_policer_global_counter_get_func)(a_uint32_t dev_id, - fal_policer_global_counter_t *counter); -typedef sw_error_t (*adpt_policer_bypass_en_set_func)(a_uint32_t dev_id, - fal_policer_frame_type_t frame_type, a_bool_t enable); -typedef sw_error_t (*adpt_policer_bypass_en_get_func)(a_uint32_t dev_id, - fal_policer_frame_type_t frame_type, a_bool_t *enable); - -/* misc */ -typedef sw_error_t (*adpt_debug_port_counter_enable_func)(a_uint32_t dev_id, - fal_port_t port_id, fal_counter_en_t * cnt_en); -typedef sw_error_t (*adpt_debug_port_counter_status_get_func)(a_uint32_t dev_id, - fal_port_t port_id, fal_counter_en_t * cnt_en); -typedef sw_error_t (*adpt_debug_counter_get_func)(a_bool_t show_type); -typedef sw_error_t (*adpt_debug_counter_set_func)(void); -typedef sw_error_t (*adpt_intr_port_link_mask_set_func) (a_uint32_t dev_id, - fal_port_t port_id, a_uint32_t intr_mask); -typedef sw_error_t (*adpt_intr_port_link_mask_get_func) (a_uint32_t dev_id, - fal_port_t port_id, a_uint32_t * intr_mask); -typedef sw_error_t (*adpt_intr_port_link_status_get_func)(a_uint32_t dev_id, - fal_port_t port_id, a_uint32_t * intr_status); - -/* uniphy */ -typedef sw_error_t (*adpt_uniphy_mode_set_func)(a_uint32_t dev_id, a_uint32_t index, a_uint32_t mode); - -/* ptp */ -typedef sw_error_t (*adpt_ptp_config_set_func)(a_uint32_t dev_id, - a_uint32_t port_id, fal_ptp_config_t *config); -typedef sw_error_t (*adpt_ptp_config_get_func)(a_uint32_t dev_id, - a_uint32_t port_id, fal_ptp_config_t *config); -typedef sw_error_t (*adpt_ptp_reference_clock_set_func)(a_uint32_t dev_id, - a_uint32_t port_id, fal_ptp_reference_clock_t ref_clock); -typedef sw_error_t (*adpt_ptp_reference_clock_get_func)(a_uint32_t dev_id, - a_uint32_t port_id, fal_ptp_reference_clock_t *ref_clock); -typedef sw_error_t (*adpt_ptp_rx_timestamp_mode_set_func)(a_uint32_t dev_id, - a_uint32_t port_id, fal_ptp_rx_timestamp_mode_t ts_mode); -typedef sw_error_t (*adpt_ptp_rx_timestamp_mode_get_func)(a_uint32_t dev_id, - a_uint32_t port_id, fal_ptp_rx_timestamp_mode_t *ts_mode); -typedef sw_error_t (*adpt_ptp_timestamp_get_func)(a_uint32_t dev_id, - a_uint32_t port_id, fal_ptp_direction_t direction, - fal_ptp_pkt_info_t *pkt_info, fal_ptp_time_t *time); -typedef sw_error_t (*adpt_ptp_pkt_timestamp_set_func)(a_uint32_t dev_id, - a_uint32_t port_id, fal_ptp_time_t *time); -typedef sw_error_t (*adpt_ptp_pkt_timestamp_get_func)(a_uint32_t dev_id, - a_uint32_t port_id, fal_ptp_time_t *time); -typedef sw_error_t (*adpt_ptp_grandmaster_mode_set_func)(a_uint32_t dev_id, - a_uint32_t port_id, fal_ptp_grandmaster_mode_t *gm_mode); -typedef sw_error_t (*adpt_ptp_grandmaster_mode_get_func)(a_uint32_t dev_id, - a_uint32_t port_id, fal_ptp_grandmaster_mode_t *gm_mode); -typedef sw_error_t (*adpt_ptp_rtc_time_get_func)(a_uint32_t dev_id, - a_uint32_t port_id, fal_ptp_time_t *time); -typedef sw_error_t (*adpt_ptp_rtc_time_set_func)(a_uint32_t dev_id, - a_uint32_t port_id, fal_ptp_time_t *time); -typedef sw_error_t (*adpt_ptp_rtc_time_clear_func)(a_uint32_t dev_id, - a_uint32_t port_id); -typedef sw_error_t (*adpt_ptp_rtc_adjtime_set_func)(a_uint32_t dev_id, - a_uint32_t port_id, fal_ptp_time_t *time); -typedef sw_error_t (*adpt_ptp_rtc_adjfreq_set_func)(a_uint32_t dev_id, - a_uint32_t port_id, fal_ptp_time_t *time); -typedef sw_error_t (*adpt_ptp_rtc_adjfreq_get_func)(a_uint32_t dev_id, - a_uint32_t port_id, fal_ptp_time_t *time); -typedef sw_error_t (*adpt_ptp_link_delay_set_func)(a_uint32_t dev_id, - a_uint32_t port_id, fal_ptp_time_t *time); -typedef sw_error_t (*adpt_ptp_link_delay_get_func)(a_uint32_t dev_id, - a_uint32_t port_id, fal_ptp_time_t *time); -typedef sw_error_t (*adpt_ptp_security_set_func)(a_uint32_t dev_id, - a_uint32_t port_id, fal_ptp_security_t *sec); -typedef sw_error_t (*adpt_ptp_security_get_func)(a_uint32_t dev_id, - a_uint32_t port_id, fal_ptp_security_t *sec); -typedef sw_error_t (*adpt_ptp_pps_signal_control_set_func)(a_uint32_t dev_id, - a_uint32_t port_id, fal_ptp_pps_signal_control_t *sig_control); -typedef sw_error_t (*adpt_ptp_pps_signal_control_get_func)(a_uint32_t dev_id, - a_uint32_t port_id, fal_ptp_pps_signal_control_t *sig_control); -typedef sw_error_t (*adpt_ptp_rx_crc_recalc_enable_func)(a_uint32_t dev_id, - a_uint32_t port_id, a_bool_t status); -typedef sw_error_t (*adpt_ptp_rx_crc_recalc_status_get_func)(a_uint32_t dev_id, - a_uint32_t port_id, a_bool_t *status); -typedef sw_error_t (*adpt_ptp_asym_correction_set_func)(a_uint32_t dev_id, - a_uint32_t port_id, fal_ptp_asym_correction_t *asym_cf); -typedef sw_error_t (*adpt_ptp_asym_correction_get_func)(a_uint32_t dev_id, - a_uint32_t port_id, fal_ptp_asym_correction_t *asym_cf); -typedef sw_error_t (*adpt_ptp_output_waveform_set_func)(a_uint32_t dev_id, - a_uint32_t port_id, fal_ptp_output_waveform_t *waveform); -typedef sw_error_t (*adpt_ptp_output_waveform_get_func)(a_uint32_t dev_id, - a_uint32_t port_id, fal_ptp_output_waveform_t *waveform); -typedef sw_error_t (*adpt_ptp_rtc_time_snapshot_enable_func)(a_uint32_t dev_id, - a_uint32_t port_id, a_bool_t status); -typedef sw_error_t (*adpt_ptp_rtc_time_snapshot_status_get_func)(a_uint32_t dev_id, - a_uint32_t port_id, a_bool_t *status); -typedef sw_error_t (*adpt_ptp_increment_sync_from_clock_enable_func)(a_uint32_t dev_id, - a_uint32_t port_id, a_bool_t status); -typedef sw_error_t (*adpt_ptp_increment_sync_from_clock_status_get_func)(a_uint32_t dev_id, - a_uint32_t port_id, a_bool_t *status); -typedef sw_error_t (*adpt_ptp_tod_uart_set_func)(a_uint32_t dev_id, - a_uint32_t port_id, fal_ptp_tod_uart_t *tod_uart); -typedef sw_error_t (*adpt_ptp_tod_uart_get_func)(a_uint32_t dev_id, - a_uint32_t port_id, fal_ptp_tod_uart_t *tod_uart); -typedef sw_error_t (*adpt_ptp_enhanced_timestamp_engine_set_func)(a_uint32_t dev_id, - a_uint32_t port_id, fal_ptp_direction_t direction, - fal_ptp_enhanced_ts_engine_t *ts_engine); -typedef sw_error_t (*adpt_ptp_enhanced_timestamp_engine_get_func)(a_uint32_t dev_id, - a_uint32_t port_id, fal_ptp_direction_t direction, - fal_ptp_enhanced_ts_engine_t *ts_engine); -typedef sw_error_t (*adpt_ptp_trigger_set_func)(a_uint32_t dev_id, a_uint32_t port_id, - a_uint32_t trigger_id, fal_ptp_trigger_t *triger); -typedef sw_error_t (*adpt_ptp_trigger_get_func)(a_uint32_t dev_id, a_uint32_t port_id, - a_uint32_t trigger_id, fal_ptp_trigger_t *triger); -typedef sw_error_t (*adpt_ptp_capture_set_func)(a_uint32_t dev_id, a_uint32_t port_id, - a_uint32_t capture_id, fal_ptp_capture_t *capture); -typedef sw_error_t (*adpt_ptp_capture_get_func)(a_uint32_t dev_id, a_uint32_t port_id, - a_uint32_t capture_id, fal_ptp_capture_t *capture); -typedef sw_error_t (*adpt_ptp_interrupt_set_func)(a_uint32_t dev_id, - a_uint32_t port_id, fal_ptp_interrupt_t *interrupt); -typedef sw_error_t (*adpt_ptp_interrupt_get_func)(a_uint32_t dev_id, - a_uint32_t port_id, fal_ptp_interrupt_t *interrupt); - -/* sfp */ -typedef sw_error_t (*adpt_sfp_eeprom_data_get_func)(a_uint32_t dev_id, - a_uint32_t port_id, fal_sfp_data_t *entry); -typedef sw_error_t (*adpt_sfp_eeprom_data_set_func)(a_uint32_t dev_id, - a_uint32_t port_id, fal_sfp_data_t *entry); -typedef sw_error_t (*adpt_sfp_diag_ctrl_status_get_func)(a_uint32_t dev_id, - a_uint32_t port_id, fal_sfp_ctrl_status_t *ctrl_status); -typedef sw_error_t (*adpt_sfp_diag_extenal_calibration_const_get_func)(a_uint32_t dev_id, - a_uint32_t port_id, fal_sfp_cal_const_t *cal_const); -typedef sw_error_t (*adpt_sfp_link_length_get_func)(a_uint32_t dev_id, - a_uint32_t port_id, fal_sfp_link_length_t *link_len); -typedef sw_error_t (*adpt_sfp_diag_internal_threshold_get_func)(a_uint32_t dev_id, - a_uint32_t port_id, fal_sfp_internal_threshold_t *threshold); -typedef sw_error_t (*adpt_sfp_diag_realtime_get_func)(a_uint32_t dev_id, - a_uint32_t port_id, fal_sfp_realtime_diag_t *real_diag); -typedef sw_error_t (*adpt_sfp_laser_wavelength_get_func)(a_uint32_t dev_id, - a_uint32_t port_id, fal_sfp_laser_wavelength_t *laser_wavelen); -typedef sw_error_t (*adpt_sfp_option_get_func)(a_uint32_t dev_id, - a_uint32_t port_id, fal_sfp_option_t *option); -typedef sw_error_t (*adpt_sfp_checkcode_get_func)(a_uint32_t dev_id, - a_uint32_t port_id, fal_sfp_cc_type_t cc_type, a_uint8_t *ccode); -typedef sw_error_t (*adpt_sfp_diag_alarm_warning_flag_get_func)(a_uint32_t dev_id, - a_uint32_t port_id, fal_sfp_alarm_warn_flag_t *alarm_warn_flag); -typedef sw_error_t (*adpt_sfp_device_type_get_func)(a_uint32_t dev_id, - a_uint32_t port_id, fal_sfp_dev_type_t *sfp_id); -typedef sw_error_t (*adpt_sfp_vendor_info_get_func)(a_uint32_t dev_id, - a_uint32_t port_id, fal_sfp_vendor_info_t *vender_info); -typedef sw_error_t (*adpt_sfp_transceiver_code_get_func)(a_uint32_t dev_id, - a_uint32_t port_id, fal_sfp_transc_code_t *transc_code); -typedef sw_error_t (*adpt_sfp_ctrl_rate_get_func)(a_uint32_t dev_id, - a_uint32_t port_id, fal_sfp_rate_t *rate_limit); -typedef sw_error_t (*adpt_sfp_enhanced_cfg_get_func)(a_uint32_t dev_id, - a_uint32_t port_id, fal_sfp_enhanced_cfg_t *enhanced_feature); -typedef sw_error_t (*adpt_sfp_rate_encode_get_func)(a_uint32_t dev_id, - a_uint32_t port_id, fal_sfp_rate_encode_t *encode); - -/*led*/ -typedef sw_error_t (*adpt_led_ctrl_pattern_set_func)(a_uint32_t dev_id, - led_pattern_group_t group, led_pattern_id_t led_pattern_id, - led_ctrl_pattern_t * pattern); -typedef sw_error_t (*adpt_led_ctrl_pattern_get_func)(a_uint32_t dev_id, - led_pattern_group_t group, led_pattern_id_t led_pattern_id, - led_ctrl_pattern_t * pattern); -typedef sw_error_t (*adpt_led_ctrl_source_set_func)(a_uint32_t dev_id, - a_uint32_t source_id, led_ctrl_pattern_t *pattern); - -typedef struct -{ - ssdk_chip_type chip_type; - a_uint32_t chip_revision; -}adpt_chip_ver_t; -typedef struct -{ - a_uint32_t adpt_fdb_func_bitmap[2]; - adpt_fdb_first_func adpt_fdb_first; - adpt_fdb_next_func adpt_fdb_next; - adpt_fdb_add_func adpt_fdb_add; - adpt_fdb_age_time_set_func adpt_fdb_age_time_set; - adpt_fdb_extend_next_func adpt_fdb_extend_next; - adpt_fdb_learn_ctrl_get_func adpt_fdb_learn_ctrl_get; - adpt_fdb_age_time_get_func adpt_fdb_age_time_get; - adpt_port_fdb_learn_limit_set_func adpt_port_fdb_learn_limit_set; - adpt_fdb_port_add_func adpt_fdb_port_add; - adpt_fdb_port_learn_set_func adpt_fdb_port_learn_set; - adpt_fdb_port_learn_get_func adpt_fdb_port_learn_get; - adpt_fdb_port_newaddr_lrn_set_func adpt_fdb_port_newaddr_lrn_set; - adpt_fdb_port_newaddr_lrn_get_func adpt_fdb_port_newaddr_lrn_get; - adpt_fdb_port_stamove_set_func adpt_fdb_port_stamove_set; - adpt_fdb_port_stamove_get_func adpt_fdb_port_stamove_get; - adpt_port_fdb_learn_counter_get_func adpt_port_fdb_learn_counter_get; - adpt_fdb_extend_first_func adpt_fdb_extend_first; - adpt_fdb_transfer_func adpt_fdb_transfer; - adpt_fdb_port_del_func adpt_fdb_port_del; - adpt_fdb_find_func adpt_fdb_find; - adpt_fdb_learn_ctrl_set_func adpt_fdb_learn_ctrl_set; - adpt_port_fdb_learn_exceed_cmd_get_func adpt_port_fdb_learn_exceed_cmd_get; - adpt_fdb_del_by_port_func adpt_fdb_del_by_port; - adpt_port_fdb_learn_limit_get_func adpt_port_fdb_learn_limit_get; - adpt_fdb_age_ctrl_set_func adpt_fdb_age_ctrl_set; - adpt_fdb_del_by_mac_func adpt_fdb_del_by_mac; - adpt_fdb_iterate_func adpt_fdb_iterate; - adpt_port_fdb_learn_exceed_cmd_set_func adpt_port_fdb_learn_exceed_cmd_set; - adpt_fdb_del_all_func adpt_fdb_del_all; - adpt_fdb_age_ctrl_get_func adpt_fdb_age_ctrl_get; - adpt_fdb_port_maclimit_ctrl_set_func adpt_fdb_port_maclimit_ctrl_set; - adpt_fdb_port_maclimit_ctrl_get_func adpt_fdb_port_maclimit_ctrl_get; - adpt_fdb_del_by_fid_func adpt_fdb_del_by_fid; - /*mib*/ - a_uint32_t adpt_mib_func_bitmap; - adpt_mib_cpukeep_get_func adpt_mib_cpukeep_get; - adpt_mib_cpukeep_set_func adpt_mib_cpukeep_set; - adpt_get_mib_info_func adpt_get_mib_info; - adpt_get_tx_mib_info_func adpt_get_tx_mib_info; - adpt_mib_status_set_func adpt_mib_status_set; - adpt_mib_port_flush_counters_func adpt_mib_port_flush_counters; - adpt_mib_status_get_func adpt_mib_status_get; - adpt_get_rx_mib_info_func adpt_get_rx_mib_info; - adpt_get_xgmib_info_func adpt_get_xgmib_info; - adpt_get_tx_xgmib_info_func adpt_get_tx_xgmib_info; - adpt_get_rx_xgmib_info_func adpt_get_rx_xgmib_info; - - a_uint32_t adpt_stp_func_bitmap; - adpt_stp_port_state_get_func adpt_stp_port_state_get; - adpt_stp_port_state_set_func adpt_stp_port_state_set; - - /*vsi*/ - a_uint32_t adpt_vsi_func_bitmap; - adpt_port_vlan_vsi_set_func adpt_port_vlan_vsi_set; - adpt_port_vlan_vsi_get_func adpt_port_vlan_vsi_get; - adpt_port_vsi_set_func adpt_port_vsi_set; - adpt_port_vsi_get_func adpt_port_vsi_get; - adpt_vsi_stamove_set_func adpt_vsi_stamove_set; - adpt_vsi_stamove_get_func adpt_vsi_stamove_get; - adpt_vsi_newaddr_lrn_set_func adpt_vsi_newaddr_lrn_set; - adpt_vsi_newaddr_lrn_get_func adpt_vsi_newaddr_lrn_get; - adpt_vsi_member_set_func adpt_vsi_member_set; - adpt_vsi_member_get_func adpt_vsi_member_get; - adpt_vsi_counter_get_func adpt_vsi_counter_get; - adpt_vsi_counter_cleanup_func adpt_vsi_counter_cleanup; - - // port_ctrl - a_uint32_t adpt_port_ctrl_func_bitmap[3]; - adpt_port_local_loopback_get_func adpt_port_local_loopback_get; - adpt_port_autoneg_restart_func adpt_port_autoneg_restart; - adpt_port_duplex_set_func adpt_port_duplex_set; - adpt_port_rxmac_status_get_func adpt_port_rxmac_status_get; - adpt_port_cdt_func adpt_port_cdt; - adpt_port_txmac_status_set_func adpt_port_txmac_status_set; - adpt_port_combo_fiber_mode_set_func adpt_port_combo_fiber_mode_set; - adpt_port_combo_medium_status_get_func adpt_port_combo_medium_status_get; - adpt_port_magic_frame_mac_set_func adpt_port_magic_frame_mac_set; - adpt_port_powersave_set_func adpt_port_powersave_set; - adpt_port_hibernate_set_func adpt_port_hibernate_set; - adpt_port_max_frame_size_get_func adpt_port_max_frame_size_get; - adpt_port_8023az_get_func adpt_port_8023az_get; - adpt_port_rxfc_status_get_func adpt_port_rxfc_status_get; - adpt_port_txfc_status_get_func adpt_port_txfc_status_get; - adpt_port_remote_loopback_set_func adpt_port_remote_loopback_set; - adpt_port_flowctrl_set_func adpt_port_flowctrl_set; - adpt_port_mru_set_func adpt_port_mru_set; - adpt_port_autoneg_status_get_func adpt_port_autoneg_status_get; - adpt_port_txmac_status_get_func adpt_port_txmac_status_get; - adpt_port_mdix_get_func adpt_port_mdix_get; - adpt_ports_link_status_get_func adpt_ports_link_status_get; - adpt_port_mac_loopback_set_func adpt_port_mac_loopback_set; - adpt_port_phy_id_get_func adpt_port_phy_id_get; - adpt_port_mru_get_func adpt_port_mru_get; - adpt_port_power_on_func adpt_port_power_on; - adpt_port_speed_set_func adpt_port_speed_set; - adpt_port_interface_mode_get_func adpt_port_interface_mode_get; - adpt_port_duplex_get_func adpt_port_duplex_get; - adpt_port_autoneg_adv_get_func adpt_port_autoneg_adv_get; - adpt_port_mdix_status_get_func adpt_port_mdix_status_get; - adpt_port_mtu_set_func adpt_port_mtu_set; - adpt_port_link_status_get_func adpt_port_link_status_get; - adpt_port_8023az_set_func adpt_port_8023az_set; - adpt_port_powersave_get_func adpt_port_powersave_get; - adpt_port_combo_prefer_medium_get_func adpt_port_combo_prefer_medium_get; - adpt_port_max_frame_size_set_func adpt_port_max_frame_size_set; - adpt_port_combo_prefer_medium_set_func adpt_port_combo_prefer_medium_set; - adpt_port_power_off_func adpt_port_power_off; - adpt_port_txfc_status_set_func adpt_port_txfc_status_set; - adpt_port_counter_set_func adpt_port_counter_set; - adpt_port_combo_fiber_mode_get_func adpt_port_combo_fiber_mode_get; - adpt_port_local_loopback_set_func adpt_port_local_loopback_set; - adpt_port_wol_status_set_func adpt_port_wol_status_set; - adpt_port_magic_frame_mac_get_func adpt_port_magic_frame_mac_get; - adpt_port_flowctrl_get_func adpt_port_flowctrl_get; - adpt_port_rxmac_status_set_func adpt_port_rxmac_status_set; - adpt_port_counter_get_func adpt_port_counter_get; - adpt_port_interface_mode_set_func adpt_port_interface_mode_set; - adpt_port_mac_loopback_get_func adpt_port_mac_loopback_get; - adpt_port_hibernate_get_func adpt_port_hibernate_get; - adpt_port_autoneg_adv_set_func adpt_port_autoneg_adv_set; - adpt_port_remote_loopback_get_func adpt_port_remote_loopback_get; - adpt_port_counter_show_func adpt_port_counter_show; - adpt_port_autoneg_enable_func adpt_port_autoneg_enable; - adpt_port_mtu_get_func adpt_port_mtu_get; - adpt_port_interface_mode_status_get_func adpt_port_interface_mode_status_get; - adpt_port_reset_func adpt_port_reset; - adpt_port_rxfc_status_set_func adpt_port_rxfc_status_set; - adpt_port_speed_get_func adpt_port_speed_get; - adpt_port_mdix_set_func adpt_port_mdix_set; - adpt_port_wol_status_get_func adpt_port_wol_status_get; - adpt_port_source_filter_set_func adpt_port_source_filter_set; - adpt_port_source_filter_get_func adpt_port_source_filter_get; - adpt_port_mux_mac_type_set_func adpt_port_mux_mac_type_set; - adpt_port_mac_speed_set_func adpt_port_mac_speed_set; - adpt_port_mac_duplex_set_func adpt_port_mac_duplex_set; - adpt_port_netdev_notify_func adpt_port_netdev_notify_set; - adpt_port_polling_sw_sync_func adpt_port_polling_sw_sync_set; - - adpt_port_bridge_txmac_set_func adpt_port_bridge_txmac_set; - - adpt_port_interface_mode_apply_func adpt_port_interface_mode_apply; - adpt_port_interface_3az_status_set_func adpt_port_interface_3az_status_set; - adpt_port_interface_3az_status_get_func adpt_port_interface_3az_status_get; - adpt_port_flowctrl_forcemode_set_func adpt_port_flowctrl_forcemode_set; - adpt_port_flowctrl_forcemode_get_func adpt_port_flowctrl_forcemode_get; - adpt_port_promisc_mode_set_func adpt_port_promisc_mode_set; - adpt_port_promisc_mode_get_func adpt_port_promisc_mode_get; - adpt_port_interface_eee_cfg_set_func adpt_port_interface_eee_cfg_set; - adpt_port_interface_eee_cfg_get_func adpt_port_interface_eee_cfg_get; - adpt_port_source_filter_config_set_func adpt_port_source_filter_config_set; - adpt_port_source_filter_config_get_func adpt_port_source_filter_config_get; - adpt_switch_port_loopback_set_func adpt_switch_port_loopback_set; - adpt_switch_port_loopback_get_func adpt_switch_port_loopback_get; - adpt_port_phy_status_get_func adpt_port_phy_status_get; -// mirror - a_uint32_t adpt_mirror_func_bitmap; - adpt_mirr_port_in_set_func adpt_mirr_port_in_set; - adpt_mirr_port_in_get_func adpt_mirr_port_in_get; - adpt_mirr_port_eg_set_func adpt_mirr_port_eg_set; - adpt_mirr_port_eg_get_func adpt_mirr_port_eg_get; - adpt_mirr_analysis_port_set_func adpt_mirr_analysis_port_set; - adpt_mirr_analysis_port_get_func adpt_mirr_analysis_port_get; - adpt_mirr_analysis_config_set_func adpt_mirr_analysis_config_set; - adpt_mirr_analysis_config_get_func adpt_mirr_analysis_config_get; -//rss hash - a_uint32_t adpt_rss_hash_func_bitmap; - adpt_rss_hash_config_set_func adpt_rss_hash_config_set; - adpt_rss_hash_config_get_func adpt_rss_hash_config_get; -//trunk - a_uint32_t adpt_trunk_func_bitmap; - adpt_trunk_fail_over_en_get_func adpt_trunk_fail_over_en_get; - adpt_trunk_hash_mode_get_func adpt_trunk_hash_mode_get; - adpt_trunk_group_get_func adpt_trunk_group_get; - adpt_trunk_group_set_func adpt_trunk_group_set; - adpt_trunk_fail_over_en_set_func adpt_trunk_fail_over_en_set; - adpt_trunk_hash_mode_set_func adpt_trunk_hash_mode_set; - - /* ip */ - a_uint32_t adpt_ip_func_bitmap[2]; - adpt_ip_network_route_get_func adpt_ip_network_route_get; - adpt_ip_network_route_add_func adpt_ip_network_route_add; - adpt_ip_network_route_del_func adpt_ip_network_route_del; - adpt_ip_host_add_func adpt_ip_host_add; - adpt_ip_vsi_sg_cfg_get_func adpt_ip_vsi_sg_cfg_get; - adpt_ip_pub_addr_set_func adpt_ip_pub_addr_set; - adpt_ip_pub_addr_get_func adpt_ip_pub_addr_get; - adpt_ip_port_sg_cfg_set_func adpt_ip_port_sg_cfg_set; - adpt_ip_port_intf_get_func adpt_ip_port_intf_get; - adpt_ip_vsi_arp_sg_cfg_set_func adpt_ip_vsi_arp_sg_cfg_set; - adpt_ip_port_intf_set_func adpt_ip_port_intf_set; - adpt_ip_vsi_sg_cfg_set_func adpt_ip_vsi_sg_cfg_set; - adpt_ip_host_next_func adpt_ip_host_next; - adpt_ip_port_macaddr_set_func adpt_ip_port_macaddr_set; - adpt_ip_vsi_intf_get_func adpt_ip_vsi_intf_get; - adpt_ip_port_sg_cfg_get_func adpt_ip_port_sg_cfg_get; - adpt_ip_intf_get_func adpt_ip_intf_get; - adpt_ip_host_del_func adpt_ip_host_del; - adpt_ip_route_mismatch_get_func adpt_ip_route_mismatch_get; - adpt_ip_vsi_arp_sg_cfg_get_func adpt_ip_vsi_arp_sg_cfg_get; - adpt_ip_port_arp_sg_cfg_set_func adpt_ip_port_arp_sg_cfg_set; - adpt_ip_vsi_mc_mode_set_func adpt_ip_vsi_mc_mode_set; - adpt_ip_vsi_intf_set_func adpt_ip_vsi_intf_set; - adpt_ip_nexthop_get_func adpt_ip_nexthop_get; - adpt_ip_route_mismatch_set_func adpt_ip_route_mismatch_set; - adpt_ip_host_get_func adpt_ip_host_get; - adpt_ip_intf_set_func adpt_ip_intf_set; - adpt_ip_vsi_mc_mode_get_func adpt_ip_vsi_mc_mode_get; - adpt_ip_port_macaddr_get_func adpt_ip_port_macaddr_get; - adpt_ip_port_arp_sg_cfg_get_func adpt_ip_port_arp_sg_cfg_get; - adpt_ip_nexthop_set_func adpt_ip_nexthop_set; - adpt_ip_global_ctrl_get_func adpt_ip_global_ctrl_get; - adpt_ip_global_ctrl_set_func adpt_ip_global_ctrl_set; - /* flow */ - a_uint32_t adpt_flow_func_bitmap; - adpt_flow_host_add_func adpt_flow_host_add; - adpt_flow_entry_get_func adpt_flow_entry_get; - adpt_flow_entry_del_func adpt_flow_entry_del; - adpt_flow_entry_next_func adpt_flow_entry_next; - adpt_flow_status_get_func adpt_flow_status_get; - adpt_flow_ctrl_set_func adpt_flow_ctrl_set; - adpt_flow_age_timer_get_func adpt_flow_age_timer_get; - adpt_flow_status_set_func adpt_flow_status_set; - adpt_flow_host_get_func adpt_flow_host_get; - adpt_flow_host_del_func adpt_flow_host_del; - adpt_flow_ctrl_get_func adpt_flow_ctrl_get; - adpt_flow_age_timer_set_func adpt_flow_age_timer_set; - adpt_flow_entry_add_func adpt_flow_entry_add; - adpt_flow_global_cfg_get_func adpt_flow_global_cfg_get; - adpt_flow_global_cfg_set_func adpt_flow_global_cfg_set; - - /* qm */ - a_uint32_t adpt_qm_func_bitmap[2]; - adpt_ucast_hash_map_set_func adpt_ucast_hash_map_set; - adpt_ac_dynamic_threshold_get_func adpt_ac_dynamic_threshold_get; - adpt_ucast_queue_base_profile_get_func adpt_ucast_queue_base_profile_get; - adpt_port_mcast_priority_class_get_func adpt_port_mcast_priority_class_get; - adpt_ac_dynamic_threshold_set_func adpt_ac_dynamic_threshold_set; - adpt_ac_prealloc_buffer_set_func adpt_ac_prealloc_buffer_set; - adpt_ucast_default_hash_get_func adpt_ucast_default_hash_get; - adpt_ucast_default_hash_set_func adpt_ucast_default_hash_set; - adpt_ac_queue_group_get_func adpt_ac_queue_group_get; - adpt_ac_ctrl_get_func adpt_ac_ctrl_get; - adpt_ac_prealloc_buffer_get_func adpt_ac_prealloc_buffer_get; - adpt_port_mcast_priority_class_set_func adpt_port_mcast_priority_class_set; - adpt_ucast_hash_map_get_func adpt_ucast_hash_map_get; - adpt_ac_static_threshold_set_func adpt_ac_static_threshold_set; - adpt_ac_queue_group_set_func adpt_ac_queue_group_set; - adpt_ac_group_buffer_get_func adpt_ac_group_buffer_get; - adpt_mcast_cpu_code_class_get_func adpt_mcast_cpu_code_class_get; - adpt_ac_ctrl_set_func adpt_ac_ctrl_set; - adpt_ucast_priority_class_get_func adpt_ucast_priority_class_get; - adpt_queue_flush_func adpt_queue_flush; - adpt_mcast_cpu_code_class_set_func adpt_mcast_cpu_code_class_set; - adpt_ucast_priority_class_set_func adpt_ucast_priority_class_set; - adpt_ac_static_threshold_get_func adpt_ac_static_threshold_get; - adpt_ucast_queue_base_profile_set_func adpt_ucast_queue_base_profile_set; - adpt_ac_group_buffer_set_func adpt_ac_group_buffer_set; - adpt_queue_counter_cleanup_func adpt_queue_counter_cleanup; - adpt_queue_counter_get_func adpt_queue_counter_get; - adpt_queue_counter_ctrl_get_func adpt_queue_counter_ctrl_get; - adpt_queue_counter_ctrl_set_func adpt_queue_counter_ctrl_set; - adpt_qm_enqueue_ctrl_set_func adpt_qm_enqueue_ctrl_set; - adpt_qm_enqueue_ctrl_get_func adpt_qm_enqueue_ctrl_get; - adpt_qm_port_source_profile_set_func adpt_qm_port_source_profile_set; - adpt_qm_port_source_profile_get_func adpt_qm_port_source_profile_get; - - /*portvlan module begin*/ - a_uint32_t adpt_portvlan_func_bitmap[2]; - adpt_global_qinq_mode_set_func adpt_global_qinq_mode_set; - adpt_global_qinq_mode_get_func adpt_global_qinq_mode_get; - adpt_tpid_set_func adpt_tpid_set; - adpt_tpid_get_func adpt_tpid_get; - adpt_egress_tpid_set_func adpt_egress_tpid_set; - adpt_egress_tpid_get_func adpt_egress_tpid_get; - adpt_port_qinq_mode_set_func adpt_port_qinq_mode_set; - adpt_port_qinq_mode_get_func adpt_port_qinq_mode_get; - adpt_port_ingress_vlan_filter_set_func adpt_port_ingress_vlan_filter_set; - adpt_port_ingress_vlan_filter_get_func adpt_port_ingress_vlan_filter_get; - adpt_port_default_vlantag_set_func adpt_port_default_vlantag_set; - adpt_port_default_vlantag_get_func adpt_port_default_vlantag_get; - adpt_port_tag_propagation_set_func adpt_port_tag_propagation_set; - adpt_port_tag_propagation_get_func adpt_port_tag_propagation_get; - adpt_port_vlantag_egmode_set_func adpt_port_vlantag_egmode_set; - adpt_port_vlantag_egmode_get_func adpt_port_vlantag_egmode_get; - adpt_port_vlan_xlt_miss_cmd_set_func adpt_port_vlan_xlt_miss_cmd_set; - adpt_port_vlan_xlt_miss_cmd_get_func adpt_port_vlan_xlt_miss_cmd_get; - adpt_port_vlan_trans_add_func adpt_port_vlan_trans_add; - adpt_port_vlan_trans_get_func adpt_port_vlan_trans_get; - adpt_port_vlan_trans_del_func adpt_port_vlan_trans_del; - adpt_port_vlan_trans_iterate_func adpt_port_vlan_trans_iterate; - adpt_port_vsi_egmode_set_func adpt_port_vsi_egmode_set; - adpt_port_vsi_egmode_get_func adpt_port_vsi_egmode_get; - adpt_port_vlantag_vsi_egmode_enable_set_func adpt_port_vlantag_vsi_egmode_enable_set; - adpt_port_vlantag_vsi_egmode_enable_get_func adpt_port_vlantag_vsi_egmode_enable_get; - adpt_qinq_mode_set_func adpt_qinq_mode_set; - adpt_qinq_mode_get_func adpt_qinq_mode_get; - adpt_port_qinq_role_set_func adpt_port_qinq_role_set; - adpt_port_qinq_role_get_func adpt_port_qinq_role_get; - adpt_port_invlan_mode_set_func adpt_port_invlan_mode_set; - adpt_port_invlan_mode_get_func adpt_port_invlan_mode_get; - adpt_port_vlan_trans_adv_add_func adpt_port_vlan_trans_adv_add; - adpt_port_vlan_trans_adv_del_func adpt_port_vlan_trans_adv_del; - adpt_port_vlan_trans_adv_getfirst_func adpt_port_vlan_trans_adv_getfirst; - adpt_port_vlan_trans_adv_getnext_func adpt_port_vlan_trans_adv_getnext; - adpt_port_vlan_counter_get_func adpt_port_vlan_counter_get; - adpt_port_vlan_counter_cleanup_func adpt_port_vlan_counter_cleanup; - adpt_portvlan_member_add_func adpt_portvlan_member_add; - adpt_portvlan_member_del_func adpt_portvlan_member_del; - adpt_portvlan_member_update_func adpt_portvlan_member_update; - adpt_portvlan_member_get_func adpt_portvlan_member_get; - /*portvlan module end*/ - - /*ctrlpkt module begin*/ - a_uint32_t adpt_ctrlpkt_func_bitmap; - adpt_mgmtctrl_ethtype_profile_set_func adpt_mgmtctrl_ethtype_profile_set; - adpt_mgmtctrl_ethtype_profile_get_func adpt_mgmtctrl_ethtype_profile_get; - adpt_mgmtctrl_rfdb_profile_set_func adpt_mgmtctrl_rfdb_profile_set; - adpt_mgmtctrl_rfdb_profile_get_func adpt_mgmtctrl_rfdb_profile_get; - adpt_mgmtctrl_ctrlpkt_profile_add_func adpt_mgmtctrl_ctrlpkt_profile_add; - adpt_mgmtctrl_ctrlpkt_profile_del_func adpt_mgmtctrl_ctrlpkt_profile_del; - adpt_mgmtctrl_ctrlpkt_profile_getfirst_func adpt_mgmtctrl_ctrlpkt_profile_getfirst; - adpt_mgmtctrl_ctrlpkt_profile_getnext_func adpt_mgmtctrl_ctrlpkt_profile_getnext; - /*ctrlpkt module end*/ - - /*servcode module begin*/ - a_uint32_t adpt_servcode_func_bitmap; - adpt_servcode_config_set_func adpt_servcode_config_set; - adpt_servcode_config_get_func adpt_servcode_config_get; - adpt_servcode_loopcheck_en_func adpt_servcode_loopcheck_en; - adpt_servcode_loopcheck_status_get_func adpt_servcode_loopcheck_status_get; - /*servcode module end*/ - - /* pppoe */ - a_uint32_t adpt_pppoe_func_bitmap; - adpt_pppoe_session_table_add_func adpt_pppoe_session_table_add; - adpt_pppoe_session_table_del_func adpt_pppoe_session_table_del; - adpt_pppoe_session_table_get_func adpt_pppoe_session_table_get; - adpt_pppoe_en_set_func adpt_pppoe_en_set; - adpt_pppoe_en_get_func adpt_pppoe_en_get; - - /*sec */ - a_uint32_t adpt_sec_func_bitmap; - adpt_sec_l3_excep_parser_ctrl_set_func adpt_sec_l3_excep_parser_ctrl_set; - adpt_sec_l3_excep_ctrl_get_func adpt_sec_l3_excep_ctrl_get; - adpt_sec_l3_excep_parser_ctrl_get_func adpt_sec_l3_excep_parser_ctrl_get; - adpt_sec_l4_excep_parser_ctrl_set_func adpt_sec_l4_excep_parser_ctrl_set; - adpt_sec_l3_excep_ctrl_set_func adpt_sec_l3_excep_ctrl_set; - adpt_sec_l4_excep_parser_ctrl_get_func adpt_sec_l4_excep_parser_ctrl_get; - - /*acl*/ - a_uint32_t adpt_acl_func_bitmap; - adpt_acl_list_bind_func adpt_acl_list_bind; - adpt_acl_list_dump_func adpt_acl_list_dump; - adpt_acl_udf_profile_set_func adpt_acl_udf_profile_set; - adpt_acl_rule_query_func adpt_acl_rule_query; - adpt_acl_list_unbind_func adpt_acl_list_unbind; - adpt_acl_rule_add_func adpt_acl_rule_add; - adpt_acl_rule_delete_func adpt_acl_rule_delete; - adpt_acl_rule_dump_func adpt_acl_rule_dump; - adpt_acl_udf_profile_get_func adpt_acl_udf_profile_get; - adpt_acl_list_creat_func adpt_acl_list_creat; - adpt_acl_list_destroy_func adpt_acl_list_destroy; - - /* qos */ - a_uint32_t adpt_qos_func_bitmap; - adpt_qos_port_pri_set_func adpt_qos_port_pri_set; - adpt_qos_port_pri_get_func adpt_qos_port_pri_get; - adpt_qos_cosmap_pcp_get_func adpt_qos_cosmap_pcp_get; - adpt_queue_scheduler_set_func adpt_queue_scheduler_set; - adpt_queue_scheduler_get_func adpt_queue_scheduler_get; - adpt_port_queues_get_func adpt_port_queues_get; - adpt_qos_cosmap_pcp_set_func adpt_qos_cosmap_pcp_set; - adpt_qos_port_remark_get_func adpt_qos_port_remark_get; - adpt_qos_cosmap_dscp_get_func adpt_qos_cosmap_dscp_get; - adpt_qos_cosmap_flow_set_func adpt_qos_cosmap_flow_set; - adpt_qos_port_group_set_func adpt_qos_port_group_set; - adpt_ring_queue_map_set_func adpt_ring_queue_map_set; - adpt_qos_cosmap_dscp_set_func adpt_qos_cosmap_dscp_set; - adpt_qos_port_remark_set_func adpt_qos_port_remark_set; - adpt_qos_cosmap_flow_get_func adpt_qos_cosmap_flow_get; - adpt_qos_port_group_get_func adpt_qos_port_group_get; - adpt_ring_queue_map_get_func adpt_ring_queue_map_get; - adpt_tdm_tick_num_set_func adpt_tdm_tick_num_set; - adpt_tdm_tick_num_get_func adpt_tdm_tick_num_get; - adpt_port_scheduler_cfg_set_func adpt_port_scheduler_cfg_set; - adpt_port_scheduler_cfg_get_func adpt_port_scheduler_cfg_get; - adpt_scheduler_dequeue_ctrl_get_func adpt_scheduler_dequeue_ctrl_get; - adpt_scheduler_dequeue_ctrl_set_func adpt_scheduler_dequeue_ctrl_set; - adpt_qos_port_mode_pri_get_func adpt_qos_port_mode_pri_get; - adpt_qos_port_mode_pri_set_func adpt_qos_port_mode_pri_set; - adpt_port_scheduler_cfg_reset_func adpt_port_scheduler_cfg_reset; - adpt_port_scheduler_resource_get_func adpt_port_scheduler_resource_get; - - /* bm */ - a_uint32_t adpt_bm_func_bitmap; - adpt_port_bufgroup_map_get_func adpt_port_bufgroup_map_get; - adpt_bm_port_reserved_buffer_get_func adpt_bm_port_reserved_buffer_get; - adpt_bm_bufgroup_buffer_get_func adpt_bm_bufgroup_buffer_get; - adpt_bm_port_dynamic_thresh_get_func adpt_bm_port_dynamic_thresh_get; - adpt_port_bm_ctrl_get_func adpt_port_bm_ctrl_get; - adpt_bm_bufgroup_buffer_set_func adpt_bm_bufgroup_buffer_set; - adpt_port_bufgroup_map_set_func adpt_port_bufgroup_map_set; - adpt_bm_port_static_thresh_get_func adpt_bm_port_static_thresh_get; - adpt_bm_port_reserved_buffer_set_func adpt_bm_port_reserved_buffer_set; - adpt_bm_port_static_thresh_set_func adpt_bm_port_static_thresh_set; - adpt_bm_port_dynamic_thresh_set_func adpt_bm_port_dynamic_thresh_set; - adpt_port_bm_ctrl_set_func adpt_port_bm_ctrl_set; - adpt_port_tdm_ctrl_set_func adpt_port_tdm_ctrl_set; - adpt_port_tdm_tick_cfg_set_func adpt_port_tdm_tick_cfg_set; - adpt_bm_port_counter_get_func adpt_bm_port_counter_get; - - //shaper - a_uint32_t adpt_shaper_func_bitmap; - adpt_flow_shaper_set_func adpt_flow_shaper_set; - adpt_queue_shaper_get_func adpt_queue_shaper_get; - adpt_queue_shaper_token_number_set_func adpt_queue_shaper_token_number_set; - adpt_port_shaper_get_func adpt_port_shaper_get; - adpt_flow_shaper_time_slot_get_func adpt_flow_shaper_time_slot_get; - adpt_port_shaper_time_slot_get_func adpt_port_shaper_time_slot_get; - adpt_flow_shaper_time_slot_set_func adpt_flow_shaper_time_slot_set; - adpt_shaper_ipg_preamble_length_set_func adpt_shaper_ipg_preamble_length_set; - adpt_port_shaper_token_number_set_func adpt_port_shaper_token_number_set; - adpt_queue_shaper_token_number_get_func adpt_queue_shaper_token_number_get; - adpt_queue_shaper_time_slot_get_func adpt_queue_shaper_time_slot_get; - adpt_port_shaper_token_number_get_func adpt_port_shaper_token_number_get; - adpt_flow_shaper_token_number_set_func adpt_flow_shaper_token_number_set; - adpt_flow_shaper_token_number_get_func adpt_flow_shaper_token_number_get; - adpt_shaper_ipg_preamble_length_get_func adpt_shaper_ipg_preamble_length_get; - adpt_port_shaper_set_func adpt_port_shaper_set; - adpt_port_shaper_time_slot_set_func adpt_port_shaper_time_slot_set; - adpt_flow_shaper_get_func adpt_flow_shaper_get; - adpt_queue_shaper_set_func adpt_queue_shaper_set; - adpt_queue_shaper_time_slot_set_func adpt_queue_shaper_time_slot_set; - -//policer - a_uint32_t adpt_policer_func_bitmap; - adpt_acl_policer_counter_get_func adpt_acl_policer_counter_get; - adpt_port_policer_counter_get_func adpt_port_policer_counter_get; - adpt_port_compensation_byte_get_func adpt_port_compensation_byte_get; - adpt_port_policer_entry_get_func adpt_port_policer_entry_get; - adpt_port_policer_entry_set_func adpt_port_policer_entry_set; - adpt_acl_policer_entry_get_func adpt_acl_policer_entry_get; - adpt_acl_policer_entry_set_func adpt_acl_policer_entry_set; - adpt_policer_time_slot_get_func adpt_policer_time_slot_get; - adpt_port_compensation_byte_set_func adpt_port_compensation_byte_set; - adpt_policer_time_slot_set_func adpt_policer_time_slot_set; - adpt_policer_global_counter_get_func adpt_policer_global_counter_get; - adpt_policer_bypass_en_set_func adpt_policer_bypass_en_set; - adpt_policer_bypass_en_get_func adpt_policer_bypass_en_get; - - /* misc */ - adpt_debug_port_counter_enable_func adpt_debug_port_counter_enable; - adpt_debug_port_counter_status_get_func adpt_debug_port_counter_status_get; - adpt_debug_counter_set_func adpt_debug_counter_set; - adpt_debug_counter_get_func adpt_debug_counter_get; - adpt_intr_port_link_mask_set_func adpt_intr_port_link_mask_set; - adpt_intr_port_link_mask_get_func adpt_intr_port_link_mask_get; - adpt_intr_port_link_status_get_func adpt_intr_port_link_status_get; - - /* uniphy */ - adpt_uniphy_mode_set_func adpt_uniphy_mode_set; - - /* ptp */ - adpt_ptp_config_set_func adpt_ptp_config_set; - adpt_ptp_config_get_func adpt_ptp_config_get; - adpt_ptp_reference_clock_set_func adpt_ptp_reference_clock_set; - adpt_ptp_reference_clock_get_func adpt_ptp_reference_clock_get; - adpt_ptp_rx_timestamp_mode_set_func adpt_ptp_rx_timestamp_mode_set; - adpt_ptp_rx_timestamp_mode_get_func adpt_ptp_rx_timestamp_mode_get; - adpt_ptp_timestamp_get_func adpt_ptp_timestamp_get; - adpt_ptp_pkt_timestamp_set_func adpt_ptp_pkt_timestamp_set; - adpt_ptp_pkt_timestamp_get_func adpt_ptp_pkt_timestamp_get; - adpt_ptp_grandmaster_mode_set_func adpt_ptp_grandmaster_mode_set; - adpt_ptp_grandmaster_mode_get_func adpt_ptp_grandmaster_mode_get; - adpt_ptp_rtc_time_get_func adpt_ptp_rtc_time_get; - adpt_ptp_rtc_time_set_func adpt_ptp_rtc_time_set; - adpt_ptp_rtc_time_clear_func adpt_ptp_rtc_time_clear; - adpt_ptp_rtc_adjtime_set_func adpt_ptp_rtc_adjtime_set; - adpt_ptp_rtc_adjfreq_set_func adpt_ptp_rtc_adjfreq_set; - adpt_ptp_rtc_adjfreq_get_func adpt_ptp_rtc_adjfreq_get; - adpt_ptp_link_delay_set_func adpt_ptp_link_delay_set; - adpt_ptp_link_delay_get_func adpt_ptp_link_delay_get; - adpt_ptp_security_set_func adpt_ptp_security_set; - adpt_ptp_security_get_func adpt_ptp_security_get; - adpt_ptp_pps_signal_control_set_func adpt_ptp_pps_signal_control_set; - adpt_ptp_pps_signal_control_get_func adpt_ptp_pps_signal_control_get; - adpt_ptp_rx_crc_recalc_enable_func adpt_ptp_rx_crc_recalc_enable; - adpt_ptp_rx_crc_recalc_status_get_func adpt_ptp_rx_crc_recalc_status_get; - adpt_ptp_asym_correction_set_func adpt_ptp_asym_correction_set; - adpt_ptp_asym_correction_get_func adpt_ptp_asym_correction_get; - adpt_ptp_output_waveform_set_func adpt_ptp_output_waveform_set; - adpt_ptp_output_waveform_get_func adpt_ptp_output_waveform_get; - adpt_ptp_rtc_time_snapshot_enable_func adpt_ptp_rtc_time_snapshot_enable; - adpt_ptp_rtc_time_snapshot_status_get_func adpt_ptp_rtc_time_snapshot_status_get; - adpt_ptp_increment_sync_from_clock_enable_func adpt_ptp_increment_sync_from_clock_enable; - adpt_ptp_increment_sync_from_clock_status_get_func \ - adpt_ptp_increment_sync_from_clock_status_get; - adpt_ptp_tod_uart_set_func adpt_ptp_tod_uart_set; - adpt_ptp_tod_uart_get_func adpt_ptp_tod_uart_get; - adpt_ptp_enhanced_timestamp_engine_set_func adpt_ptp_enhanced_timestamp_engine_set; - adpt_ptp_enhanced_timestamp_engine_get_func adpt_ptp_enhanced_timestamp_engine_get; - adpt_ptp_trigger_set_func adpt_ptp_trigger_set; - adpt_ptp_trigger_get_func adpt_ptp_trigger_get; - adpt_ptp_capture_set_func adpt_ptp_capture_set; - adpt_ptp_capture_get_func adpt_ptp_capture_get; - adpt_ptp_interrupt_set_func adpt_ptp_interrupt_set; - adpt_ptp_interrupt_get_func adpt_ptp_interrupt_get; - - /* sfp */ - adpt_sfp_eeprom_data_get_func adpt_sfp_eeprom_data_get; - adpt_sfp_eeprom_data_set_func adpt_sfp_eeprom_data_set; - adpt_sfp_diag_ctrl_status_get_func adpt_sfp_diag_ctrl_status_get; - adpt_sfp_diag_extenal_calibration_const_get_func - adpt_sfp_diag_extenal_calibration_const_get; - adpt_sfp_link_length_get_func adpt_sfp_link_length_get; - adpt_sfp_diag_internal_threshold_get_func adpt_sfp_diag_internal_threshold_get; - adpt_sfp_diag_realtime_get_func adpt_sfp_diag_realtime_get; - adpt_sfp_laser_wavelength_get_func adpt_sfp_laser_wavelength_get; - adpt_sfp_option_get_func adpt_sfp_option_get; - adpt_sfp_checkcode_get_func adpt_sfp_checkcode_get; - adpt_sfp_diag_alarm_warning_flag_get_func adpt_sfp_diag_alarm_warning_flag_get; - adpt_sfp_device_type_get_func adpt_sfp_device_type_get; - adpt_sfp_vendor_info_get_func adpt_sfp_vendor_info_get; - adpt_sfp_transceiver_code_get_func adpt_sfp_transceiver_code_get; - adpt_sfp_ctrl_rate_get_func adpt_sfp_ctrl_rate_get; - adpt_sfp_enhanced_cfg_get_func adpt_sfp_enhanced_cfg_get; - adpt_sfp_rate_encode_get_func adpt_sfp_rate_encode_get; - /*led*/ - adpt_led_ctrl_pattern_set_func adpt_led_ctrl_pattern_set; - adpt_led_ctrl_pattern_get_func adpt_led_ctrl_pattern_get; - adpt_led_ctrl_source_set_func adpt_led_ctrl_source_set; -}adpt_api_t; - - -adpt_api_t *adpt_api_ptr_get(a_uint32_t dev_id); -sw_error_t adpt_init(a_uint32_t dev_id, ssdk_init_cfg *cfg); -sw_error_t adpt_module_func_ctrl_set(a_uint32_t dev_id, - a_uint32_t module, fal_func_ctrl_t *func_ctrl); -sw_error_t adpt_module_func_ctrl_get(a_uint32_t dev_id, - a_uint32_t module, fal_func_ctrl_t *func_ctrl); -sw_error_t adpt_module_func_init(a_uint32_t dev_id, ssdk_init_cfg *cfg); -#ifdef SCOMPHY -a_uint32_t adapt_scomphy_revision_get(a_uint32_t dev_id); -#endif -#ifdef __cplusplus -} -#endif /* __cplusplus */ -#endif diff --git a/feeds/ipq807x/qca-ssdk/src/include/adpt/cppe/adpt_cppe_flow.h b/feeds/ipq807x/qca-ssdk/src/include/adpt/cppe/adpt_cppe_flow.h deleted file mode 100755 index 72480e511..000000000 --- a/feeds/ipq807x/qca-ssdk/src/include/adpt/cppe/adpt_cppe_flow.h +++ /dev/null @@ -1,38 +0,0 @@ -/* - * Copyright (c) 2019, The Linux Foundation. All rights reserved. - * Permission to use, copy, modify, and/or distribute this software for - * any purpose with or without fee is hereby granted, provided that the - * above copyright notice and this permission notice appear in all copies. - * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES - * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR - * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES - * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN - * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT - * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. - */ - - -/** - * @defgroup - * @{ - */ -#ifndef _ADPT_CPPE_FLOW_ -#define _ADPT_CPPE_FLOW_ - -#ifdef __cplusplus -extern "C" { -#endif /* __cplusplus */ - -#ifndef IN_FLOW_MINI -sw_error_t -adpt_cppe_flow_copy_escape_set(a_uint32_t dev_id, a_bool_t enable); - -sw_error_t -adpt_cppe_flow_copy_escape_get(a_uint32_t dev_id, a_bool_t *enable); -#endif - -#ifdef __cplusplus -} -#endif /* __cplusplus */ -#endif diff --git a/feeds/ipq807x/qca-ssdk/src/include/adpt/cppe/adpt_cppe_mib.h b/feeds/ipq807x/qca-ssdk/src/include/adpt/cppe/adpt_cppe_mib.h deleted file mode 100755 index 3b1302e8d..000000000 --- a/feeds/ipq807x/qca-ssdk/src/include/adpt/cppe/adpt_cppe_mib.h +++ /dev/null @@ -1,52 +0,0 @@ -/* - * Copyright (c) 2019, The Linux Foundation. All rights reserved. - * Permission to use, copy, modify, and/or distribute this software for - * any purpose with or without fee is hereby granted, provided that the - * above copyright notice and this permission notice appear in all copies. - * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES - * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR - * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES - * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN - * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT - * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. - */ -/** - * @defgroup - * @{ - */ -#ifndef _ADPT_CPPE_MIB_H_ -#define _ADPT_CPPE_MIB_H_ - -#ifdef __cplusplus -extern "C" { -#endif /* __cplusplus */ - -sw_error_t -adpt_cppe_lpbk_mib_cpukeep_get(a_uint32_t dev_id, a_uint32_t port_id, - a_bool_t *enable); - -sw_error_t -adpt_cppe_lpbk_mib_cpukeep_set(a_uint32_t dev_id, a_uint32_t port_id, - a_bool_t enable); - -sw_error_t -adpt_hppe_lpbk_mib_status_get(a_uint32_t dev_id, a_uint32_t port_id, - a_bool_t *enable); - -sw_error_t -adpt_cppe_lpbk_mib_status_set(a_uint32_t dev_id, a_uint32_t port_id, - a_bool_t enable); - -sw_error_t -adpt_cppe_lpbk_mib_flush_counters(a_uint32_t dev_id, - fal_port_t port_id); - -sw_error_t -adpt_cppe_lpbk_get_mib_info(a_uint32_t dev_id, fal_port_t port_id, - fal_mib_info_t * mib_info ); - -#ifdef __cplusplus -} -#endif /* __cplusplus */ -#endif diff --git a/feeds/ipq807x/qca-ssdk/src/include/adpt/cppe/adpt_cppe_misc.h b/feeds/ipq807x/qca-ssdk/src/include/adpt/cppe/adpt_cppe_misc.h deleted file mode 100755 index db2d7d989..000000000 --- a/feeds/ipq807x/qca-ssdk/src/include/adpt/cppe/adpt_cppe_misc.h +++ /dev/null @@ -1,37 +0,0 @@ -/* - * Copyright (c) 2019, The Linux Foundation. All rights reserved. - * Permission to use, copy, modify, and/or distribute this software for - * any purpose with or without fee is hereby granted, provided that the - * above copyright notice and this permission notice appear in all copies. - * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES - * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR - * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES - * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN - * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT - * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. - */ - - -/** - * @defgroup - * @{ - */ -#ifndef _ADPT_CPPE_MISC_ -#define _ADPT_CPPE_MISC_ - -#ifdef __cplusplus -extern "C" { -#endif /* __cplusplus */ - -sw_error_t -adpt_cppe_debug_port_counter_enable(a_uint32_t dev_id, fal_port_t port_id, - fal_counter_en_t *cnt_en); -sw_error_t -adpt_cppe_debug_port_counter_status_get(a_uint32_t dev_id, fal_port_t port_id, - fal_counter_en_t *cnt_en); - -#ifdef __cplusplus -} -#endif /* __cplusplus */ -#endif diff --git a/feeds/ipq807x/qca-ssdk/src/include/adpt/cppe/adpt_cppe_portctrl.h b/feeds/ipq807x/qca-ssdk/src/include/adpt/cppe/adpt_cppe_portctrl.h deleted file mode 100755 index 9e38ed3cb..000000000 --- a/feeds/ipq807x/qca-ssdk/src/include/adpt/cppe/adpt_cppe_portctrl.h +++ /dev/null @@ -1,103 +0,0 @@ -/* - * Copyright (c) 2018-2019, The Linux Foundation. All rights reserved. - * Permission to use, copy, modify, and/or distribute this software for - * any purpose with or without fee is hereby granted, provided that the - * above copyright notice and this permission notice appear in all copies. - * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES - * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR - * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES - * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN - * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT - * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. - */ - - -/** - * @defgroup - * @{ - */ -#ifndef _ADPT_CPPE_PORTCTRLH_ -#define _ADPT_CPPE_PORTCTRLH_ - -#ifdef __cplusplus -extern "C" { -#endif /* __cplusplus */ - -#define CPPE_PORT3_PCS_SEL_PCS0_CHANNEL2 0x0 -#define CPPE_PORT3_PCS_SEL_PCS0_CHANNEL4 0x1 -#define CPPE_PORT4_PCS_SEL_PCS0_CHANNEL3 0x0 -#define CPPE_PORT4_PCS_SEL_PCS0_SGMIIPLUS 0x1 -#define CPPE_PORT5_PCS_SEL_PCS0_CHANNEL4 0x0 -#define CPPE_PORT5_PCS_SEL_PCS1_CHANNEL0 0x1 -#define CPPE_PORT5_GMAC_SEL_GMAC 0x0 -#define CPPE_PORT5_GMAC_SEL_XGMAC 0x1 -#define CPPE_PCS0_CHANNEL4_SEL_PORT5_CLOCK 0x0 -#define CPPE_PCS0_CHANNEL4_SEL_PORT3_CLOCK 0x1 -#define CPPE_PCS0_CHANNEL0_SEL_PSGMII 0x0 -#define CPPE_PCS0_CHANNEL0_SEL_SGMIIPLUS 0x1 -#define CPPE_DETECTION_PHY_FAILURE 0xFFFF -#define CPPE_LOOPBACK_PORT_RATE_FREQUENCY 300 /* 300MHZ*/ -#define CPPE_LOOPBACK_PORT_NUM 0x1 - -sw_error_t -_adpt_cppe_port_mux_mac_set(a_uint32_t dev_id, fal_port_t port_id, - a_uint32_t port_type); -sw_error_t -adpt_cppe_port_mru_set(a_uint32_t dev_id, fal_port_t port_id, - fal_mru_ctrl_t *ctrl); -sw_error_t -adpt_cppe_port_mru_get(a_uint32_t dev_id, fal_port_t port_id, - fal_mru_ctrl_t *ctrl); -#ifndef IN_PORTCONTROL_MINI -sw_error_t -adpt_cppe_port_mtu_set(a_uint32_t dev_id, fal_port_t port_id, - fal_mtu_ctrl_t *ctrl); -sw_error_t -adpt_cppe_port_mtu_get(a_uint32_t dev_id, fal_port_t port_id, - fal_mtu_ctrl_t *ctrl); -sw_error_t -adpt_cppe_port_source_filter_set(a_uint32_t dev_id, - fal_port_t port_id, a_bool_t enable); -sw_error_t -adpt_cppe_port_source_filter_get(a_uint32_t dev_id, - fal_port_t port_id, a_bool_t * enable); -sw_error_t -adpt_cppe_port_source_filter_config_set( - a_uint32_t dev_id, fal_port_t port_id, - fal_src_filter_config_t *src_filter_config); -sw_error_t -adpt_cppe_port_source_filter_config_get - (a_uint32_t dev_id, fal_port_t port_id, - fal_src_filter_config_t* src_filter_config); -#endif -sw_error_t -adpt_cppe_port_to_channel_convert(a_uint32_t dev_id, - a_uint32_t port_id, a_uint32_t *channel_id); -sw_error_t -adpt_cppe_switch_port_loopback_set(a_uint32_t dev_id, - fal_port_t port_id, fal_loopback_config_t *loopback_cfg); - -sw_error_t -adpt_cppe_switch_port_loopback_get(a_uint32_t dev_id, - fal_port_t port_id, fal_loopback_config_t *loopback_cfg); - -sw_error_t -adpt_cppe_switch_port_loopback_flowctrl_set(a_uint32_t dev_id, - fal_port_t port_id, a_bool_t enable); - -sw_error_t -adpt_cppe_switch_port_loopback_flowctrl_get(a_uint32_t dev_id, - fal_port_t port_id, a_bool_t *enable); - -sw_error_t -adpt_cppe_lpbk_max_frame_size_get(a_uint32_t dev_id, fal_port_t port_id, - a_uint32_t *max_frame); - -sw_error_t -adpt_cppe_lpbk_max_frame_size_set(a_uint32_t dev_id, fal_port_t port_id, - a_uint32_t max_frame); -#ifdef __cplusplus -} -#endif /* __cplusplus */ -#endif diff --git a/feeds/ipq807x/qca-ssdk/src/include/adpt/cppe/adpt_cppe_qm.h b/feeds/ipq807x/qca-ssdk/src/include/adpt/cppe/adpt_cppe_qm.h deleted file mode 100755 index a38b475de..000000000 --- a/feeds/ipq807x/qca-ssdk/src/include/adpt/cppe/adpt_cppe_qm.h +++ /dev/null @@ -1,41 +0,0 @@ -/* - * Copyright (c) 2018, The Linux Foundation. All rights reserved. - * Permission to use, copy, modify, and/or distribute this software for - * any purpose with or without fee is hereby granted, provided that the - * above copyright notice and this permission notice appear in all copies. - * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES - * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR - * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES - * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN - * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT - * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. - */ - - -/** - * @defgroup - * @{ - */ -#ifndef _ADPT_CPPE_QM_H_ -#define _ADPT_CPPE_QM_H_ - -#ifdef __cplusplus -extern "C" { -#endif /* __cplusplus */ - -#ifndef IN_QM_MINI -sw_error_t -adpt_cppe_qm_port_source_profile_set( - a_uint32_t dev_id, fal_port_t port, a_uint32_t src_profile); -sw_error_t -adpt_cppe_qm_port_source_profile_get( - a_uint32_t dev_id, fal_port_t port, a_uint32_t *src_profile); -#endif - -#ifdef __cplusplus -} -#endif /* __cplusplus */ -#endif - - diff --git a/feeds/ipq807x/qca-ssdk/src/include/adpt/cppe/adpt_cppe_qos.h b/feeds/ipq807x/qca-ssdk/src/include/adpt/cppe/adpt_cppe_qos.h deleted file mode 100644 index 867e73346..000000000 --- a/feeds/ipq807x/qca-ssdk/src/include/adpt/cppe/adpt_cppe_qos.h +++ /dev/null @@ -1,68 +0,0 @@ -/* - * Copyright (c) 2018, The Linux Foundation. All rights reserved. - * Permission to use, copy, modify, and/or distribute this software for - * any purpose with or without fee is hereby granted, provided that the - * above copyright notice and this permission notice appear in all copies. - * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES - * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR - * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES - * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN - * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT - * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. - */ - - -/** - * @defgroup - * @{ - */ -#ifndef _ADPT_CPPE_QOS_H_ -#define _ADPT_CPPE_QOS_H_ - -#ifdef __cplusplus -extern "C" { -#endif /* __cplusplus */ - -sw_error_t -adpt_cppe_qos_port_pri_set(a_uint32_t dev_id, fal_port_t port_id, - fal_qos_pri_precedence_t *pri); -sw_error_t -adpt_cppe_qos_port_pri_get(a_uint32_t dev_id, fal_port_t port_id, - fal_qos_pri_precedence_t *pri); -sw_error_t -adpt_cppe_qos_cosmap_pcp_get(a_uint32_t dev_id, a_uint8_t group_id, - a_uint8_t pcp, - fal_qos_cosmap_t *cosmap); -sw_error_t -adpt_cppe_qos_cosmap_pcp_set(a_uint32_t dev_id, a_uint8_t group_id, - a_uint8_t pcp, - fal_qos_cosmap_t *cosmap); -sw_error_t -adpt_cppe_qos_cosmap_dscp_get(a_uint32_t dev_id, a_uint8_t group_id, - a_uint8_t dscp, - fal_qos_cosmap_t *cosmap); -sw_error_t -adpt_cppe_qos_cosmap_flow_set(a_uint32_t dev_id, a_uint8_t group_id, - a_uint16_t flow, - fal_qos_cosmap_t *cosmap); -sw_error_t -adpt_cppe_qos_port_group_set(a_uint32_t dev_id, fal_port_t port_id, - fal_qos_group_t *group); -sw_error_t -adpt_cppe_qos_cosmap_dscp_set(a_uint32_t dev_id, a_uint8_t group_id, - a_uint8_t dscp, - fal_qos_cosmap_t *cosmap); -sw_error_t -adpt_cppe_qos_cosmap_flow_get(a_uint32_t dev_id, a_uint8_t group_id, - a_uint16_t flow, - fal_qos_cosmap_t *cosmap); -sw_error_t -adpt_cppe_qos_port_group_get(a_uint32_t dev_id, fal_port_t port_id, - fal_qos_group_t *group); - -#ifdef __cplusplus -} -#endif /* __cplusplus */ -#endif - diff --git a/feeds/ipq807x/qca-ssdk/src/include/adpt/cppe/adpt_cppe_uniphy.h b/feeds/ipq807x/qca-ssdk/src/include/adpt/cppe/adpt_cppe_uniphy.h deleted file mode 100755 index 635fdbf61..000000000 --- a/feeds/ipq807x/qca-ssdk/src/include/adpt/cppe/adpt_cppe_uniphy.h +++ /dev/null @@ -1,47 +0,0 @@ -/* - * Copyright (c) 2019, The Linux Foundation. All rights reserved. - * Permission to use, copy, modify, and/or distribute this software for - * any purpose with or without fee is hereby granted, provided that the - * above copyright notice and this permission notice appear in all copies. - * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES - * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR - * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES - * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN - * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT - * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. - */ - - -/** - * @defgroup - * @{ - */ -#ifndef _ADPT_CPPE_UNIPHYH_ -#define _ADPT_CPPE_UNIPHYH_ - -#ifdef __cplusplus -extern "C" { -#endif /* __cplusplus */ - -sw_error_t -__adpt_cppe_uniphy_channel_selection_set(a_uint32_t dev_id, - a_uint32_t ch0_selection, a_uint32_t ch4_selection); - -void -__adpt_hppe_gcc_uniphy_xpcs_reset(a_uint32_t dev_id, a_uint32_t uniphy_index, - a_bool_t enable); -sw_error_t -__adpt_hppe_uniphy_calibrate(a_uint32_t dev_id, a_uint32_t uniphy_index); - -void -__adpt_cppe_gcc_uniphy_software_reset(a_uint32_t dev_id, - a_uint32_t uniphy_index); -sw_error_t -__adpt_cppe_uniphy_mode_set(a_uint32_t dev_id, - a_uint32_t uniphy_index, a_uint32_t mode); - -#ifdef __cplusplus -} -#endif /* __cplusplus */ -#endif diff --git a/feeds/ipq807x/qca-ssdk/src/include/adpt/hppe/adpt_hppe.h b/feeds/ipq807x/qca-ssdk/src/include/adpt/hppe/adpt_hppe.h deleted file mode 100755 index d8c5be46f..000000000 --- a/feeds/ipq807x/qca-ssdk/src/include/adpt/hppe/adpt_hppe.h +++ /dev/null @@ -1,112 +0,0 @@ -/* - * Copyright (c) 2016-2019, The Linux Foundation. All rights reserved. - * Permission to use, copy, modify, and/or distribute this software for - * any purpose with or without fee is hereby granted, provided that the - * above copyright notice and this permission notice appear in all copies. - * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES - * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR - * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES - * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN - * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT - * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. - */ - - -/** - * @defgroup - * @{ - */ -#ifndef _ADPT_HPPE_H_ -#define _ADPT_HPPE_H_ - -#ifdef __cplusplus -extern "C" { -#endif /* __cplusplus */ - -void adpt_hppe_fdb_func_bitmap_init(a_uint32_t dev_id); -sw_error_t adpt_hppe_fdb_init(a_uint32_t dev_id); -void adpt_hppe_portvlan_func_bitmap_init(a_uint32_t dev_id); -sw_error_t adpt_hppe_portvlan_init(a_uint32_t dev_id); -void adpt_hppe_ctrlpkt_func_bitmap_init(a_uint32_t dev_id); -sw_error_t adpt_hppe_ctrlpkt_init(a_uint32_t dev_id); -void adpt_hppe_servcode_func_bitmap_init(a_uint32_t dev_id); -sw_error_t adpt_hppe_servcode_init(a_uint32_t dev_id); -void adpt_hppe_rss_hash_func_bitmap_init(a_uint32_t dev_id); -sw_error_t adpt_hppe_rss_hash_init(a_uint32_t dev_id); -void adpt_hppe_mib_func_bitmap_init(a_uint32_t dev_id); -sw_error_t adpt_hppe_mib_init(a_uint32_t dev_id); -void adpt_hppe_stp_func_bitmap_init(a_uint32_t dev_id); -sw_error_t adpt_hppe_stp_init(a_uint32_t dev_id); -void adpt_hppe_vsi_func_bitmap_init(a_uint32_t dev_id); -sw_error_t adpt_hppe_vsi_init(a_uint32_t dev_id); -sw_error_t adpt_hppe_port_ctrl_init(a_uint32_t dev_id); -sw_error_t adpt_hppe_misc_init(a_uint32_t dev_id); - -void adpt_hppe_mirror_func_bitmap_init(a_uint32_t dev_id); -sw_error_t adpt_hppe_mirror_init(a_uint32_t dev_id); -void adpt_hppe_trunk_func_bitmap_init(a_uint32_t dev_id); -sw_error_t adpt_hppe_trunk_init(a_uint32_t dev_id); -void adpt_hppe_ip_func_bitmap_init(a_uint32_t dev_id); -sw_error_t adpt_hppe_ip_init(a_uint32_t dev_id); -void adpt_hppe_qm_func_bitmap_init(a_uint32_t dev_id); -sw_error_t adpt_hppe_qm_init(a_uint32_t dev_id); -void adpt_hppe_flow_func_bitmap_init(a_uint32_t dev_id); -sw_error_t adpt_hppe_flow_init(a_uint32_t dev_id); - -void adpt_hppe_pppoe_func_bitmap_init(a_uint32_t dev_id); -sw_error_t adpt_hppe_pppoe_init(a_uint32_t dev_id); -void adpt_hppe_sec_func_bitmap_init(a_uint32_t dev_id); -sw_error_t adpt_hppe_sec_init(a_uint32_t dev_id); - -void adpt_hppe_acl_func_bitmap_init(a_uint32_t dev_id); -sw_error_t adpt_hppe_acl_init(a_uint32_t dev_id); -void adpt_hppe_qos_func_bitmap_init(a_uint32_t dev_id); -sw_error_t adpt_hppe_qos_init(a_uint32_t dev_id); -void adpt_hppe_bm_func_bitmap_init(a_uint32_t dev_id); -sw_error_t adpt_hppe_bm_init(a_uint32_t dev_id); - -sw_error_t adpt_hppe_shaper_init(a_uint32_t dev_id); - -void adpt_hppe_port_ctrl_func_bitmap_init(a_uint32_t dev_id); - -void adpt_hppe_shaper_func_bitmap_init(a_uint32_t dev_id); - -sw_error_t adpt_hppe_policer_init(a_uint32_t dev_id); - -void adpt_hppe_policer_func_bitmap_init(a_uint32_t dev_id); - -sw_error_t adpt_hppe_uniphy_init(a_uint32_t dev_id); - -/*shaper*/ -#define HPPE_MAX_C_TOKEN_NUM 0x3fffffff -#define HPPE_MAX_E_TOKEN_NUM 0x3fffffff - -#define HPPE_POLICER_TIMESLOT_DFT 600 -#define HPPE_PORT_SHAPER_TIMESLOT_DFT 8 -#define HPPE_FLOW_SHAPER_TIMESLOT_DFT 64 -#define HPPE_QUEUE_SHAPER_TIMESLOT_DFT 300 -#define HPPE_SHAPER_IPG_PREAMBLE_LEN_DFT 20 - -/*BM*/ -#define HPPE_BM_PORT_NUM 15 -#define HPPE_BM_PHY_PORT_OFFSET 8 - -void adpt_hppe_ptp_func_bitmap_init(a_uint32_t dev_id); -sw_error_t adpt_hppe_ptp_init(a_uint32_t dev_id); - -#define HPPE_REVISION 0x0 -#define CPPE_REVISION 0x1 -#define UNKNOWN_REVISION 0xff - -a_uint32_t adpt_hppe_chip_revision_get(a_uint32_t dev_id); - -#ifdef IN_FDB -sw_error_t -adpt_hppe_fdb_del_by_port(a_uint32_t dev_id, a_uint32_t port_id, a_uint32_t flag); -#endif - -#ifdef __cplusplus -} -#endif /* __cplusplus */ -#endif diff --git a/feeds/ipq807x/qca-ssdk/src/include/adpt/mp/adpt_mp.h b/feeds/ipq807x/qca-ssdk/src/include/adpt/mp/adpt_mp.h deleted file mode 100644 index 47ba498c4..000000000 --- a/feeds/ipq807x/qca-ssdk/src/include/adpt/mp/adpt_mp.h +++ /dev/null @@ -1,43 +0,0 @@ -/* - * Copyright (c) 2020, The Linux Foundation. All rights reserved. - * - * Permission to use, copy, modify, and/or distribute this software for any - * purpose with or without fee is hereby granted, provided that the above - * copyright notice and this permission notice appear in all copies. - * - * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES - * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR - * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES - * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN - * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF - * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. - */ - -#ifndef _ADPT_MP_H_ -#define _ADPT_MP_H_ - -#ifdef __cplusplus -extern "C" { -#endif /* __cplusplus */ - -#define MP_PORT_TO_GMAC_ID(port_id) (port_id -1) -#define MP_MAX_PORT 2 -#define MP_GMAC0 0 -#define MP_GMAC1 1 -#define MP_PORT_ID_CHECK(port_id) \ -do { \ - if (port_id > MP_MAX_PORT) \ - return SW_OUT_OF_RANGE; \ -} while (0) - -sw_error_t adpt_mp_intr_init(a_uint32_t dev_id); -sw_error_t adpt_mp_mib_init(a_uint32_t dev_id); -sw_error_t adpt_mp_portctrl_init(a_uint32_t dev_id); -sw_error_t adpt_mp_uniphy_init(a_uint32_t dev_id); -sw_error_t adpt_mp_led_init(a_uint32_t dev_id); - -#ifdef __cplusplus -} -#endif /* __cplusplus */ -#endif diff --git a/feeds/ipq807x/qca-ssdk/src/include/adpt/mp/adpt_mp_portctrl.h b/feeds/ipq807x/qca-ssdk/src/include/adpt/mp/adpt_mp_portctrl.h deleted file mode 100755 index 364a28544..000000000 --- a/feeds/ipq807x/qca-ssdk/src/include/adpt/mp/adpt_mp_portctrl.h +++ /dev/null @@ -1,63 +0,0 @@ -/* - * Copyright (c) 2020, The Linux Foundation. All rights reserved. - * - * Permission to use, copy, modify, and/or distribute this software for any - * purpose with or without fee is hereby granted, provided that the above - * copyright notice and this permission notice appear in all copies. - * - * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES - * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR - * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES - * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN - * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF - * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. - */ - -#ifndef _ADPT_PORTCTRL_H_ -#define _ADPT_PORTCTRL_H_ - - -#define GMAC_SPEED_10M 0x0 -#define GMAC_SPEED_100M 0x1 -#define GMAC_SPEED_1000M 0x0 -#define GMAC_FULL_DUPLEX 0x1 -#define GMAC_HALF_DUPLEX 0x0 -#define GMAC_PAUSE_TIME 0xffff -#define GMAC_PAUSE_ZERO_QUANTA_ENABLE 0x0 -#define GMAC_JD_ENABLE 0x1 -#define GMAC_WD_DISABLE 0x0 -#define GMAC_FRAME_BURST_ENABLE 0x1 -#define GMAC_JUMBO_FRAME_ENABLE 0x1 -#define GMAC_MAX_FRAME_CTRL_ENABLE 0x1 -#define GMAC_LPI_LINK_UP 0x1 -#define GMAC_LPI_AUTO_MODE 0x1 -#define GMAC_TX_STORE_FORWAD_ENABLE 0x1 -#define GMAC_RX_STORE_FORWAD_ENABLE 0x1 -#define GMAC_FORWARD_ERROR_FRAME_DISABLE 0x0 -#define GMAC_DROP_GAINT_FRAME_DISABLE 0x0 -#define GMAC_FLUSH_RECEIVED_FRAMES_DISABLE 0x1 -#define GMAC_HW_FLOWCTRL_ENABLE 0x1 -#define GMAC_ACTIVATE_FLOWCTRL_MASK 0x800600 -#define GMAC_ACTIVATE_FLOWCTRL_WITH_1KB 0x0 -#define GMAC_ACTIVATE_FLOWCTRL_WITH_2KB 0x200 -#define GMAC_ACTIVATE_FLOWCTRL_WITH_3KB 0x400 -#define GMAC_ACTIVATE_FLOWCTRL_WITH_4KB 0x600 -#define GMAC_ACTIVATE_FLOWCTRL_WITH_5KB 0x800000 -#define GMAC_ACTIVATE_FLOWCTRL_WITH_6KB 0x800200 -#define GMAC_ACTIVATE_FLOWCTRL_WITH_7KB 0x800400 -#define GMAC_DACTIVATE_FLOWCTRL_MASK 0x401800 -#define GMAC_DACTIVATE_FLOWCTRL_WITH_1KB 0x0 -#define GMAC_DACTIVATE_FLOWCTRL_WITH_2KB 0x800 -#define GMAC_DACTIVATE_FLOWCTRL_WITH_3KB 0x1000 -#define GMAC_DACTIVATE_FLOWCTRL_WITH_4KB 0x1800 -#define GMAC_DACTIVATE_FLOWCTRL_WITH_5KB 0x400000 -#define GMAC_DACTIVATE_FLOWCTRL_WITH_6KB 0x400800 -#define GMAC_DACTIVATE_FLOWCTRL_WITH_7KB 0x401000 - -#define GMAC_HW_FLOWCTRL_DISABLE 0x0 -#define PORT_LPI_ENABLE_STATUS 0x3 -#define PORT_LPI_TASK_RUNNING 0x10000 -#define PORT_LPI_TASK_START 0x20000 - -#endif diff --git a/feeds/ipq807x/qca-ssdk/src/include/adpt/mp/adpt_mp_uniphy.h b/feeds/ipq807x/qca-ssdk/src/include/adpt/mp/adpt_mp_uniphy.h deleted file mode 100755 index 1e20b712c..000000000 --- a/feeds/ipq807x/qca-ssdk/src/include/adpt/mp/adpt_mp_uniphy.h +++ /dev/null @@ -1,45 +0,0 @@ -/* - * Copyright (c) 2020, The Linux Foundation. All rights reserved. - * - * Permission to use, copy, modify, and/or distribute this software for any - * purpose with or without fee is hereby granted, provided that the above - * copyright notice and this permission notice appear in all copies. - * - * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES - * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR - * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES - * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN - * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF - * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. - */ - - -/** - * @defgroup - * @{ - */ -#ifndef _ADPT_MP_UNIPHY_H_ -#define _ADPT_MP_UNIPHY_H_ - -#ifdef __cplusplus -extern "C" { -#endif /* __cplusplus */ - -void -adpt_mp_gcc_uniphy_port_reset(a_uint32_t dev_id, a_uint32_t port_id); - -sw_error_t -adpt_mp_gcc_uniphy_port_clock_set(a_uint32_t dev_id, a_uint32_t port_id, - a_bool_t enable); - -sw_error_t -adpt_mp_uniphy_adapter_port_reset(a_uint32_t dev_id, a_uint32_t port_id); - -sw_error_t -adpt_mp_uniphy_mode_configure(a_uint32_t dev_id, a_uint32_t index, a_uint32_t mode); - -#ifdef __cplusplus -} -#endif /* __cplusplus */ -#endif diff --git a/feeds/ipq807x/qca-ssdk/src/include/adpt/sfp/adpt_sfp.h b/feeds/ipq807x/qca-ssdk/src/include/adpt/sfp/adpt_sfp.h deleted file mode 100755 index 81cdf38a2..000000000 --- a/feeds/ipq807x/qca-ssdk/src/include/adpt/sfp/adpt_sfp.h +++ /dev/null @@ -1,32 +0,0 @@ -/* - * Copyright (c) 2019, The Linux Foundation. All rights reserved. - * Permission to use, copy, modify, and/or distribute this software for - * any purpose with or without fee is hereby granted, provided that the - * above copyright notice and this permission notice appear in all copies. - * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES - * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR - * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES - * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN - * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT - * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. - */ - - -/** - * @defgroup - * @{ - */ -#ifndef _ADPT_SFP_H_ -#define _ADPT_SFP_H_ - -#ifdef __cplusplus -extern "C" { -#endif /* __cplusplus */ - -sw_error_t adpt_sfp_init(a_uint32_t dev_id); - -#ifdef __cplusplus -} -#endif /* __cplusplus */ -#endif diff --git a/feeds/ipq807x/qca-ssdk/src/include/api/api_access.h b/feeds/ipq807x/qca-ssdk/src/include/api/api_access.h deleted file mode 100755 index 78e9eb07b..000000000 --- a/feeds/ipq807x/qca-ssdk/src/include/api/api_access.h +++ /dev/null @@ -1,39 +0,0 @@ -/* - * Copyright (c) 2012, The Linux Foundation. All rights reserved. - * Permission to use, copy, modify, and/or distribute this software for - * any purpose with or without fee is hereby granted, provided that the - * above copyright notice and this permission notice appear in all copies. - * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES - * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR - * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES - * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN - * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT - * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. - */ - - - -#ifndef _API_ACCESS_H -#define _API_ACCESS_H - -#ifdef __cplusplus -extern "C" { -#endif /* __cplusplus */ - - sw_api_func_t * - sw_api_func_find(a_uint32_t api_id); - - sw_api_param_t * - sw_api_param_find(a_uint32_t api_id); - - a_uint32_t - sw_api_param_nums(a_uint32_t api_id); - - sw_error_t - sw_api_get(sw_api_t *sw_api); - -#ifdef __cplusplus -} -#endif /* __cplusplus */ -#endif /* _API_ACCESS_H */ diff --git a/feeds/ipq807x/qca-ssdk/src/include/api/api_desc.h b/feeds/ipq807x/qca-ssdk/src/include/api/api_desc.h deleted file mode 100755 index 388f45476..000000000 --- a/feeds/ipq807x/qca-ssdk/src/include/api/api_desc.h +++ /dev/null @@ -1,4771 +0,0 @@ -/* - * Copyright (c) 2012, 2015-2019, 2021, The Linux Foundation. All rights reserved. - * Permission to use, copy, modify, and/or distribute this software for - * any purpose with or without fee is hereby granted, provided that the - * above copyright notice and this permission notice appear in all copies. - * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES - * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR - * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES - * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN - * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT - * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. - */ - - -/*qca808x_start*/ -#ifndef _API_DESC_H_ -#define _API_DESC_H_ - -#ifdef __cplusplus -extern "C" { -#endif /* __cplusplus */ - -#define SW_API_PT_DUPLEX_GET_DESC \ - SW_PARAM_DEF(SW_API_PT_DUPLEX_GET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \ - SW_PARAM_DEF(SW_API_PT_DUPLEX_GET, SW_UINT32, 4, SW_PARAM_IN, "Port No."), \ - SW_PARAM_DEF(SW_API_PT_DUPLEX_GET, SW_DUPLEX, \ - sizeof(fal_port_duplex_t), SW_PARAM_PTR|SW_PARAM_OUT, \ - "duplex"), - -#define SW_API_PT_DUPLEX_SET_DESC \ - SW_PARAM_DEF(SW_API_PT_DUPLEX_SET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \ - SW_PARAM_DEF(SW_API_PT_DUPLEX_SET, SW_UINT32, 4, SW_PARAM_IN, "Port No."), \ - SW_PARAM_DEF(SW_API_PT_DUPLEX_SET, SW_DUPLEX, \ - sizeof(fal_port_duplex_t), SW_PARAM_IN, \ - "duplex"), - -#define SW_API_PT_SPEED_GET_DESC \ - SW_PARAM_DEF(SW_API_PT_SPEED_GET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \ - SW_PARAM_DEF(SW_API_PT_SPEED_GET, SW_UINT32, 4, SW_PARAM_IN, "Port No."), \ - SW_PARAM_DEF(SW_API_PT_SPEED_GET, SW_SPEED, \ - sizeof(fal_port_speed_t), SW_PARAM_PTR|SW_PARAM_OUT, \ - "speed"), - -#define SW_API_PT_SPEED_SET_DESC \ - SW_PARAM_DEF(SW_API_PT_SPEED_SET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \ - SW_PARAM_DEF(SW_API_PT_SPEED_SET, SW_UINT32, 4, SW_PARAM_IN, "Port No."), \ - SW_PARAM_DEF(SW_API_PT_SPEED_SET, SW_SPEED, \ - sizeof(fal_port_speed_t), SW_PARAM_IN, \ - "speed"), - -#define SW_API_PT_AN_GET_DESC \ - SW_PARAM_DEF(SW_API_PT_AN_GET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \ - SW_PARAM_DEF(SW_API_PT_AN_GET, SW_UINT32, 4, SW_PARAM_IN, "Port No."), \ - SW_PARAM_DEF(SW_API_PT_AN_GET, SW_ENABLE, 4, SW_PARAM_PTR|SW_PARAM_OUT, "autoneg"), - - -#define SW_API_PT_AN_ENABLE_DESC \ - SW_PARAM_DEF(SW_API_PT_AN_ENABLE, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \ - SW_PARAM_DEF(SW_API_PT_AN_ENABLE, SW_UINT32, 4, SW_PARAM_IN, "Port No."), - - -#define SW_API_PT_AN_RESTART_DESC \ - SW_PARAM_DEF(SW_API_PT_AN_RESTART, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \ - SW_PARAM_DEF(SW_API_PT_AN_RESTART, SW_UINT32, 4, SW_PARAM_IN, "Port No."), - -#define SW_API_PT_AN_ADV_GET_DESC \ - SW_PARAM_DEF(SW_API_PT_AN_ADV_GET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \ - SW_PARAM_DEF(SW_API_PT_AN_ADV_GET, SW_UINT32, 4, SW_PARAM_IN, "Port No."), \ - SW_PARAM_DEF(SW_API_PT_AN_ADV_GET, SW_CAP, 4, SW_PARAM_PTR|SW_PARAM_OUT, "autoneg"), - -#define SW_API_PT_AN_ADV_SET_DESC \ - SW_PARAM_DEF(SW_API_PT_AN_ADV_SET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \ - SW_PARAM_DEF(SW_API_PT_AN_ADV_SET, SW_UINT32, 4, SW_PARAM_IN, "Port No."), \ - SW_PARAM_DEF(SW_API_PT_AN_ADV_SET, SW_CAP, 4, SW_PARAM_IN, "autoneg"), -/*qca808x_end*/ - -#define SW_API_PT_HDR_SET_DESC \ - SW_PARAM_DEF(SW_API_PT_HDR_SET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \ - SW_PARAM_DEF(SW_API_PT_HDR_SET, SW_UINT32, 4, SW_PARAM_IN, "Port ID"), \ - SW_PARAM_DEF(SW_API_PT_HDR_SET, SW_ENABLE, 4, SW_PARAM_IN, "Header"), - -#define SW_API_PT_HDR_GET_DESC \ - SW_PARAM_DEF(SW_API_PT_HDR_GET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \ - SW_PARAM_DEF(SW_API_PT_HDR_GET, SW_UINT32, 4, SW_PARAM_IN, "Port ID"), \ - SW_PARAM_DEF(SW_API_PT_HDR_GET, SW_ENABLE, 4, SW_PARAM_PTR|SW_PARAM_OUT, "Header"), - -#define SW_API_PT_FLOWCTRL_SET_DESC \ - SW_PARAM_DEF(SW_API_PT_FLOWCTRL_SET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \ - SW_PARAM_DEF(SW_API_PT_FLOWCTRL_SET, SW_UINT32, 4, SW_PARAM_IN, "Port ID"), \ - SW_PARAM_DEF(SW_API_PT_FLOWCTRL_SET, SW_ENABLE, 4, SW_PARAM_IN, "Flow control"), - -#define SW_API_PT_FLOWCTRL_GET_DESC \ - SW_PARAM_DEF(SW_API_PT_FLOWCTRL_GET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \ - SW_PARAM_DEF(SW_API_PT_FLOWCTRL_GET, SW_UINT32, 4, SW_PARAM_IN, "Port ID"), \ - SW_PARAM_DEF(SW_API_PT_FLOWCTRL_GET, SW_ENABLE, 4, SW_PARAM_PTR|SW_PARAM_OUT, "Flow control"), - -#define SW_API_PT_FLOWCTRL_MODE_SET_DESC \ - SW_PARAM_DEF(SW_API_PT_FLOWCTRL_MODE_SET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \ - SW_PARAM_DEF(SW_API_PT_FLOWCTRL_MODE_SET, SW_UINT32, 4, SW_PARAM_IN, "Port ID"), \ - SW_PARAM_DEF(SW_API_PT_FLOWCTRL_MODE_SET, SW_ENABLE, 4, SW_PARAM_IN, "Force mode"), - -#define SW_API_PT_FLOWCTRL_MODE_GET_DESC \ - SW_PARAM_DEF(SW_API_PT_FLOWCTRL_MODE_GET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \ - SW_PARAM_DEF(SW_API_PT_FLOWCTRL_MODE_GET, SW_UINT32, 4, SW_PARAM_IN, "Port ID"), \ - SW_PARAM_DEF(SW_API_PT_FLOWCTRL_MODE_GET, SW_ENABLE, 4, SW_PARAM_PTR|SW_PARAM_OUT, "Force mode"), - -#define SW_API_PT_POWERSAVE_SET_DESC \ - SW_PARAM_DEF(SW_API_PT_POWERSAVE_SET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \ - SW_PARAM_DEF(SW_API_PT_POWERSAVE_SET, SW_UINT32, 4, SW_PARAM_IN, "Port ID"), \ - SW_PARAM_DEF(SW_API_PT_POWERSAVE_SET, SW_ENABLE, 4, SW_PARAM_IN, "Powersave Status"), - -#define SW_API_PT_POWERSAVE_GET_DESC \ - SW_PARAM_DEF(SW_API_PT_POWERSAVE_GET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \ - SW_PARAM_DEF(SW_API_PT_POWERSAVE_GET, SW_UINT32, 4, SW_PARAM_IN, "Port ID"), \ - SW_PARAM_DEF(SW_API_PT_POWERSAVE_GET, SW_ENABLE, 4, SW_PARAM_PTR|SW_PARAM_OUT, "Powersave Status"), -/*qca808x_start*/ -#define SW_API_PT_HIBERNATE_SET_DESC \ - SW_PARAM_DEF(SW_API_PT_HIBERNATE_SET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \ - SW_PARAM_DEF(SW_API_PT_HIBERNATE_SET, SW_UINT32, 4, SW_PARAM_IN, "Port ID"), \ - SW_PARAM_DEF(SW_API_PT_HIBERNATE_SET, SW_ENABLE, 4, SW_PARAM_IN, "Hibernate status"), - -#define SW_API_PT_HIBERNATE_GET_DESC \ - SW_PARAM_DEF(SW_API_PT_HIBERNATE_GET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \ - SW_PARAM_DEF(SW_API_PT_HIBERNATE_GET, SW_UINT32, 4, SW_PARAM_IN, "Port ID"), \ - SW_PARAM_DEF(SW_API_PT_HIBERNATE_GET, SW_ENABLE, 4, SW_PARAM_PTR|SW_PARAM_OUT, "Hibernate Status"), - -#define SW_API_PT_CDT_DESC \ - SW_PARAM_DEF(SW_API_PT_CDT, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \ - SW_PARAM_DEF(SW_API_PT_CDT, SW_UINT32, 4, SW_PARAM_IN, "Port ID"), \ - SW_PARAM_DEF(SW_API_PT_CDT, SW_UINT32, 4, SW_PARAM_IN, "MDI Pair ID"), \ - SW_PARAM_DEF(SW_API_PT_CDT, SW_CABLESTATUS, 4, SW_PARAM_PTR|SW_PARAM_OUT, "cable status"), \ - SW_PARAM_DEF(SW_API_PT_CDT, SW_CABLELEN, 4, SW_PARAM_PTR|SW_PARAM_OUT, "cable len"), -/*qca808x_end*/ -#define SW_API_PT_TXHDR_SET_DESC \ - SW_PARAM_DEF(SW_API_PT_TXHDR_SET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \ - SW_PARAM_DEF(SW_API_PT_TXHDR_SET, SW_UINT32, 4, SW_PARAM_IN, "Port ID"), \ - SW_PARAM_DEF(SW_API_PT_TXHDR_SET, SW_HDRMODE, \ - sizeof(fal_port_header_mode_t), \ - SW_PARAM_IN, "HdrMode"), - -#define SW_API_PT_TXHDR_GET_DESC \ - SW_PARAM_DEF(SW_API_PT_TXHDR_GET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \ - SW_PARAM_DEF(SW_API_PT_TXHDR_GET, SW_UINT32, 4, SW_PARAM_IN, "Port ID"), \ - SW_PARAM_DEF(SW_API_PT_TXHDR_GET, SW_HDRMODE, \ - sizeof(fal_port_header_mode_t), \ - SW_PARAM_PTR|SW_PARAM_OUT, "HdrMode"), - -#define SW_API_PT_RXHDR_SET_DESC \ - SW_PARAM_DEF(SW_API_PT_RXHDR_SET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \ - SW_PARAM_DEF(SW_API_PT_RXHDR_SET, SW_UINT32, 4, SW_PARAM_IN, "Port ID"), \ - SW_PARAM_DEF(SW_API_PT_RXHDR_SET, SW_HDRMODE, \ - sizeof(fal_port_header_mode_t), \ - SW_PARAM_IN, "HdrMode"), - -#define SW_API_PT_RXHDR_GET_DESC \ - SW_PARAM_DEF(SW_API_PT_RXHDR_GET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \ - SW_PARAM_DEF(SW_API_PT_RXHDR_GET, SW_UINT32, 4, SW_PARAM_IN, "Port ID"), \ - SW_PARAM_DEF(SW_API_PT_RXHDR_GET, SW_HDRMODE, \ - sizeof(fal_port_header_mode_t), \ - SW_PARAM_PTR|SW_PARAM_OUT, "HdrMode"), - -#define SW_API_HEADER_TYPE_SET_DESC \ - SW_PARAM_DEF(SW_API_HEADER_TYPE_SET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \ - SW_PARAM_DEF(SW_API_HEADER_TYPE_SET, SW_ENABLE, 4, SW_PARAM_IN, "Enable"), \ - SW_PARAM_DEF(SW_API_HEADER_TYPE_SET, SW_UINT32, 4, SW_PARAM_IN, "Value"), - -#define SW_API_HEADER_TYPE_GET_DESC \ - SW_PARAM_DEF(SW_API_HEADER_TYPE_GET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \ - SW_PARAM_DEF(SW_API_HEADER_TYPE_GET, SW_ENABLE, 4, SW_PARAM_PTR|SW_PARAM_OUT, "Enable"), \ - SW_PARAM_DEF(SW_API_HEADER_TYPE_GET, SW_UINT32, 4, SW_PARAM_PTR|SW_PARAM_OUT, "Value"), - -#define SW_API_TXMAC_STATUS_SET_DESC \ - SW_PARAM_DEF(SW_API_TXMAC_STATUS_SET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \ - SW_PARAM_DEF(SW_API_TXMAC_STATUS_SET, SW_UINT32, 4, SW_PARAM_IN, "Port ID"), \ - SW_PARAM_DEF(SW_API_TXMAC_STATUS_SET, SW_ENABLE, 4, SW_PARAM_IN, "Value"), - -#define SW_API_TXMAC_STATUS_GET_DESC \ - SW_PARAM_DEF(SW_API_TXMAC_STATUS_GET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \ - SW_PARAM_DEF(SW_API_TXMAC_STATUS_GET, SW_UINT32, 4, SW_PARAM_IN, "Port ID"), \ - SW_PARAM_DEF(SW_API_TXMAC_STATUS_GET, SW_ENABLE, 4, SW_PARAM_PTR|SW_PARAM_OUT, "Value"), - -#define SW_API_RXMAC_STATUS_SET_DESC \ - SW_PARAM_DEF(SW_API_RXMAC_STATUS_SET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \ - SW_PARAM_DEF(SW_API_RXMAC_STATUS_SET, SW_UINT32, 4, SW_PARAM_IN, "Port ID"), \ - SW_PARAM_DEF(SW_API_RXMAC_STATUS_SET, SW_ENABLE, 4, SW_PARAM_IN, "Value"), - -#define SW_API_RXMAC_STATUS_GET_DESC \ - SW_PARAM_DEF(SW_API_RXMAC_STATUS_GET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \ - SW_PARAM_DEF(SW_API_RXMAC_STATUS_GET, SW_UINT32, 4, SW_PARAM_IN, "Port ID"), \ - SW_PARAM_DEF(SW_API_RXMAC_STATUS_GET, SW_ENABLE, 4, SW_PARAM_PTR|SW_PARAM_OUT, "Value"), - -#define SW_API_TXFC_STATUS_SET_DESC \ - SW_PARAM_DEF(SW_API_TXFC_STATUS_SET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \ - SW_PARAM_DEF(SW_API_TXFC_STATUS_SET, SW_UINT32, 4, SW_PARAM_IN, "Port ID"), \ - SW_PARAM_DEF(SW_API_TXFC_STATUS_SET, SW_ENABLE, 4, SW_PARAM_IN, "Value"), - -#define SW_API_TXFC_STATUS_GET_DESC \ - SW_PARAM_DEF(SW_API_TXFC_STATUS_GET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \ - SW_PARAM_DEF(SW_API_TXFC_STATUS_GET, SW_UINT32, 4, SW_PARAM_IN, "Port ID"), \ - SW_PARAM_DEF(SW_API_TXFC_STATUS_GET, SW_ENABLE, 4, SW_PARAM_PTR|SW_PARAM_OUT, "Value"), - -#define SW_API_RXFC_STATUS_SET_DESC \ - SW_PARAM_DEF(SW_API_RXFC_STATUS_SET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \ - SW_PARAM_DEF(SW_API_RXFC_STATUS_SET, SW_UINT32, 4, SW_PARAM_IN, "Port ID"), \ - SW_PARAM_DEF(SW_API_RXFC_STATUS_SET, SW_ENABLE, 4, SW_PARAM_IN, "Value"), - -#define SW_API_RXFC_STATUS_GET_DESC \ - SW_PARAM_DEF(SW_API_RXFC_STATUS_GET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \ - SW_PARAM_DEF(SW_API_RXFC_STATUS_GET, SW_UINT32, 4, SW_PARAM_IN, "Port ID"), \ - SW_PARAM_DEF(SW_API_RXFC_STATUS_GET, SW_ENABLE, 4, SW_PARAM_PTR|SW_PARAM_OUT, "Value"), - -#define SW_API_BP_STATUS_SET_DESC \ - SW_PARAM_DEF(SW_API_BP_STATUS_SET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \ - SW_PARAM_DEF(SW_API_BP_STATUS_SET, SW_UINT32, 4, SW_PARAM_IN, "Port ID"), \ - SW_PARAM_DEF(SW_API_BP_STATUS_SET, SW_ENABLE, 4, SW_PARAM_IN, "Value"), - -#define SW_API_BP_STATUS_GET_DESC \ - SW_PARAM_DEF(SW_API_BP_STATUS_GET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \ - SW_PARAM_DEF(SW_API_BP_STATUS_GET, SW_UINT32, 4, SW_PARAM_IN, "Port ID"), \ - SW_PARAM_DEF(SW_API_BP_STATUS_GET, SW_ENABLE, 4, SW_PARAM_PTR|SW_PARAM_OUT, "Value"), - -#define SW_API_PT_LINK_MODE_SET_DESC \ - SW_PARAM_DEF(SW_API_PT_LINK_MODE_SET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \ - SW_PARAM_DEF(SW_API_PT_LINK_MODE_SET, SW_UINT32, 4, SW_PARAM_IN, "Port ID"), \ - SW_PARAM_DEF(SW_API_PT_LINK_MODE_SET, SW_ENABLE, 4, SW_PARAM_IN, "Value"), - -#define SW_API_PT_LINK_MODE_GET_DESC \ - SW_PARAM_DEF(SW_API_PT_LINK_MODE_GET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \ - SW_PARAM_DEF(SW_API_PT_LINK_MODE_GET, SW_UINT32, 4, SW_PARAM_IN, "Port ID"), \ - SW_PARAM_DEF(SW_API_PT_LINK_MODE_GET, SW_ENABLE, 4, SW_PARAM_PTR|SW_PARAM_OUT, "Value"), -/*qca808x_start*/ -#define SW_API_PT_LINK_STATUS_GET_DESC \ - SW_PARAM_DEF(SW_API_PT_LINK_STATUS_GET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \ - SW_PARAM_DEF(SW_API_PT_LINK_STATUS_GET, SW_UINT32, 4, SW_PARAM_IN, "Port ID"), \ - SW_PARAM_DEF(SW_API_PT_LINK_STATUS_GET, SW_ENABLE, 4, SW_PARAM_PTR|SW_PARAM_OUT, "Status"), -/*qca808x_end*/ -#define SW_API_PTS_LINK_STATUS_GET_DESC \ - SW_PARAM_DEF(SW_API_PTS_LINK_STATUS_GET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \ - SW_PARAM_DEF(SW_API_PTS_LINK_STATUS_GET, SW_ENABLE, 4, SW_PARAM_PTR|SW_PARAM_OUT, "Status"), - -#define SW_API_PT_MAC_LOOPBACK_SET_DESC \ - SW_PARAM_DEF(SW_API_PT_MAC_LOOPBACK_SET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \ - SW_PARAM_DEF(SW_API_PT_MAC_LOOPBACK_SET, SW_UINT32, 4, SW_PARAM_IN, "Port ID"), \ - SW_PARAM_DEF(SW_API_PT_MAC_LOOPBACK_SET, SW_ENABLE, 4, SW_PARAM_IN, "Enable"), - -#define SW_API_PT_MAC_LOOPBACK_GET_DESC \ - SW_PARAM_DEF(SW_API_PT_MAC_LOOPBACK_GET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \ - SW_PARAM_DEF(SW_API_PT_MAC_LOOPBACK_GET, SW_UINT32, 4, SW_PARAM_IN, "Port ID"), \ - SW_PARAM_DEF(SW_API_PT_MAC_LOOPBACK_GET, SW_ENABLE, 4, SW_PARAM_PTR|SW_PARAM_OUT, "Enable"), - -#define SW_API_PT_CONGESTION_DROP_SET_DESC \ - SW_PARAM_DEF(SW_API_PT_CONGESTION_DROP_SET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \ - SW_PARAM_DEF(SW_API_PT_CONGESTION_DROP_SET, SW_UINT32, 4, SW_PARAM_IN, "Port ID"), \ - SW_PARAM_DEF(SW_API_PT_CONGESTION_DROP_SET, SW_UINT32, 4, SW_PARAM_IN, "Queue ID"), \ - SW_PARAM_DEF(SW_API_PT_CONGESTION_DROP_SET, SW_ENABLE, 4, SW_PARAM_IN, "Enable"), - -#define SW_API_PT_CONGESTION_DROP_GET_DESC \ - SW_PARAM_DEF(SW_API_PT_CONGESTION_DROP_GET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \ - SW_PARAM_DEF(SW_API_PT_CONGESTION_DROP_GET, SW_UINT32, 4, SW_PARAM_IN, "Port ID"), \ - SW_PARAM_DEF(SW_API_PT_CONGESTION_DROP_GET, SW_UINT32, 4, SW_PARAM_IN, "Queue ID"), \ - SW_PARAM_DEF(SW_API_PT_CONGESTION_DROP_GET, SW_ENABLE, 4, SW_PARAM_PTR|SW_PARAM_OUT, "Enable"), - -#define SW_API_PT_RING_FLOW_CTRL_THRES_SET_DESC \ - SW_PARAM_DEF(SW_API_PT_RING_FLOW_CTRL_THRES_SET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \ - SW_PARAM_DEF(SW_API_PT_RING_FLOW_CTRL_THRES_SET, SW_UINT32, 4, SW_PARAM_IN, "Ring ID"), \ - SW_PARAM_DEF(SW_API_PT_RING_FLOW_CTRL_THRES_SET, SW_UINT8, 1, SW_PARAM_IN, "On Thres"), \ - SW_PARAM_DEF(SW_API_PT_RING_FLOW_CTRL_THRES_SET, SW_UINT8, 1, SW_PARAM_IN, "Off Thres"), - -#define SW_API_PT_RING_FLOW_CTRL_THRES_GET_DESC \ - SW_PARAM_DEF(SW_API_PT_RING_FLOW_CTRL_THRES_GET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \ - SW_PARAM_DEF(SW_API_PT_RING_FLOW_CTRL_THRES_GET, SW_UINT32, 4, SW_PARAM_IN, "Ring ID"), \ - SW_PARAM_DEF(SW_API_PT_RING_FLOW_CTRL_THRES_GET, SW_UINT8, 1, SW_PARAM_PTR|SW_PARAM_OUT, "On Thres"), \ - SW_PARAM_DEF(SW_API_PT_RING_FLOW_CTRL_THRES_GET, SW_UINT8, 1, SW_PARAM_PTR|SW_PARAM_OUT, "Off Thres"), -/*qca808x_start*/ -#define SW_API_PT_8023AZ_SET_DESC \ - SW_PARAM_DEF(SW_API_PT_8023AZ_SET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \ - SW_PARAM_DEF(SW_API_PT_8023AZ_SET, SW_UINT32, 4, SW_PARAM_IN, "Port ID"), \ - SW_PARAM_DEF(SW_API_PT_8023AZ_SET, SW_ENABLE, 4, SW_PARAM_IN, "8023az Status"), - -#define SW_API_PT_8023AZ_GET_DESC \ - SW_PARAM_DEF(SW_API_PT_8023AZ_GET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \ - SW_PARAM_DEF(SW_API_PT_8023AZ_GET, SW_UINT32, 4, SW_PARAM_IN, "Port ID"), \ - SW_PARAM_DEF(SW_API_PT_8023AZ_GET, SW_ENABLE, 4, SW_PARAM_PTR|SW_PARAM_OUT, "8023az Status"), - -#define SW_API_PT_MDIX_SET_DESC \ - SW_PARAM_DEF(SW_API_PT_MDIX_SET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \ - SW_PARAM_DEF(SW_API_PT_MDIX_SET, SW_UINT32, 4, SW_PARAM_IN, "Port ID"), \ - SW_PARAM_DEF(SW_API_PT_MDIX_SET, SW_CROSSOVER_MODE, \ - sizeof(fal_port_mdix_mode_t), SW_PARAM_IN, "Crossover Mode"), - - -#define SW_API_PT_MDIX_GET_DESC \ - SW_PARAM_DEF(SW_API_PT_MDIX_GET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \ - SW_PARAM_DEF(SW_API_PT_MDIX_GET, SW_UINT32, 4, SW_PARAM_IN, "Port ID"), \ - SW_PARAM_DEF(SW_API_PT_MDIX_GET, SW_CROSSOVER_MODE, \ - sizeof(fal_port_mdix_mode_t), SW_PARAM_PTR|SW_PARAM_OUT, \ - "Crossover Mode"), - -#define SW_API_PT_MDIX_STATUS_GET_DESC \ - SW_PARAM_DEF(SW_API_PT_MDIX_STATUS_GET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \ - SW_PARAM_DEF(SW_API_PT_MDIX_STATUS_GET, SW_UINT32, 4, SW_PARAM_IN, "Port ID"), \ - SW_PARAM_DEF(SW_API_PT_MDIX_STATUS_GET, SW_CROSSOVER_STATUS, \ - sizeof(fal_port_mdix_status_t), SW_PARAM_PTR|SW_PARAM_OUT, \ - "Crossover Status"), -/*qca808x_end*/ - -#define SW_API_PT_COMBO_PREFER_MEDIUM_SET_DESC \ - SW_PARAM_DEF(SW_API_PT_COMBO_PREFER_MEDIUM_SET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \ - SW_PARAM_DEF(SW_API_PT_COMBO_PREFER_MEDIUM_SET, SW_UINT32, 4, SW_PARAM_IN, "Port ID"), \ - SW_PARAM_DEF(SW_API_PT_COMBO_PREFER_MEDIUM_SET, SW_PREFER_MEDIUM, \ - sizeof(fal_port_medium_t), SW_PARAM_IN, "Prefer Medium"), - - -#define SW_API_PT_COMBO_PREFER_MEDIUM_GET_DESC \ - SW_PARAM_DEF(SW_API_PT_COMBO_PREFER_MEDIUM_GET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \ - SW_PARAM_DEF(SW_API_PT_COMBO_PREFER_MEDIUM_GET, SW_UINT32, 4, SW_PARAM_IN, "Port ID"), \ - SW_PARAM_DEF(SW_API_PT_COMBO_PREFER_MEDIUM_GET, SW_PREFER_MEDIUM, \ - sizeof(fal_port_medium_t), SW_PARAM_PTR|SW_PARAM_OUT, \ - "Prefer Medium"), - -#define SW_API_PT_COMBO_MEDIUM_STATUS_GET_DESC \ - SW_PARAM_DEF(SW_API_PT_COMBO_MEDIUM_STATUS_GET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \ - SW_PARAM_DEF(SW_API_PT_COMBO_MEDIUM_STATUS_GET, SW_UINT32, 4, SW_PARAM_IN, "Port ID"), \ - SW_PARAM_DEF(SW_API_PT_COMBO_MEDIUM_STATUS_GET, SW_PREFER_MEDIUM, \ - sizeof(fal_port_medium_t), SW_PARAM_PTR|SW_PARAM_OUT, \ - "Medium Type"), - -#define SW_API_PT_COMBO_FIBER_MODE_SET_DESC \ - SW_PARAM_DEF(SW_API_PT_COMBO_FIBER_MODE_SET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \ - SW_PARAM_DEF(SW_API_PT_COMBO_FIBER_MODE_SET, SW_UINT32, 4, SW_PARAM_IN, "Port ID"), \ - SW_PARAM_DEF(SW_API_PT_COMBO_FIBER_MODE_SET, SW_FIBER_MODE, \ - sizeof(fal_port_fiber_mode_t), SW_PARAM_IN, "Fbier Mode"), - - -#define SW_API_PT_COMBO_FIBER_MODE_GET_DESC \ - SW_PARAM_DEF(SW_API_PT_COMBO_FIBER_MODE_GET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \ - SW_PARAM_DEF(SW_API_PT_COMBO_FIBER_MODE_GET, SW_UINT32, 4, SW_PARAM_IN, "Port ID"), \ - SW_PARAM_DEF(SW_API_PT_COMBO_FIBER_MODE_GET, SW_FIBER_MODE, \ - sizeof(fal_port_fiber_mode_t), SW_PARAM_PTR|SW_PARAM_OUT, \ - "Fiber Mode"), -/*qca808x_start*/ - -#define SW_API_PT_LOCAL_LOOPBACK_SET_DESC \ - SW_PARAM_DEF(SW_API_PT_LOCAL_LOOPBACK_SET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \ - SW_PARAM_DEF(SW_API_PT_LOCAL_LOOPBACK_SET, SW_UINT32, 4, SW_PARAM_IN, "Port ID"), \ - SW_PARAM_DEF(SW_API_PT_LOCAL_LOOPBACK_SET, SW_ENABLE, 4, \ - SW_PARAM_IN, "Local Loopback Status"), - -#define SW_API_PT_LOCAL_LOOPBACK_GET_DESC \ - SW_PARAM_DEF(SW_API_PT_LOCAL_LOOPBACK_GET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \ - SW_PARAM_DEF(SW_API_PT_LOCAL_LOOPBACK_GET, SW_UINT32, 4, SW_PARAM_IN, "Port ID"), \ - SW_PARAM_DEF(SW_API_PT_LOCAL_LOOPBACK_GET, SW_ENABLE, 4, \ - SW_PARAM_PTR|SW_PARAM_OUT, "Local Loopback Status"), - -#define SW_API_PT_REMOTE_LOOPBACK_SET_DESC \ - SW_PARAM_DEF(SW_API_PT_REMOTE_LOOPBACK_SET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \ - SW_PARAM_DEF(SW_API_PT_REMOTE_LOOPBACK_SET, SW_UINT32, 4, SW_PARAM_IN, "Port ID"), \ - SW_PARAM_DEF(SW_API_PT_REMOTE_LOOPBACK_SET, SW_ENABLE, 4, \ - SW_PARAM_IN, "Remote Loopback Status"), - -#define SW_API_PT_REMOTE_LOOPBACK_GET_DESC \ - SW_PARAM_DEF(SW_API_PT_REMOTE_LOOPBACK_GET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \ - SW_PARAM_DEF(SW_API_PT_REMOTE_LOOPBACK_GET, SW_UINT32, 4, SW_PARAM_IN, "Port ID"), \ - SW_PARAM_DEF(SW_API_PT_REMOTE_LOOPBACK_GET, SW_ENABLE, 4, \ - SW_PARAM_PTR|SW_PARAM_OUT, "Remote Loopback Status"), - -#define SW_API_PT_RESET_DESC \ - SW_PARAM_DEF(SW_API_PT_RESET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \ - SW_PARAM_DEF(SW_API_PT_RESET, SW_UINT32, 4, SW_PARAM_IN, "Port ID"), - -#define SW_API_PT_POWER_OFF_DESC \ - SW_PARAM_DEF(SW_API_PT_POWER_OFF, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \ - SW_PARAM_DEF(SW_API_PT_POWER_OFF, SW_UINT32, 4, SW_PARAM_IN, "Port ID"), - -#define SW_API_PT_POWER_ON_DESC \ - SW_PARAM_DEF(SW_API_PT_POWER_ON, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \ - SW_PARAM_DEF(SW_API_PT_POWER_ON, SW_UINT32, 4, SW_PARAM_IN, "Port ID"), - -#define SW_API_PT_MAGIC_FRAME_MAC_SET_DESC \ - SW_PARAM_DEF(SW_API_PT_MAGIC_FRAME_MAC_SET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \ - SW_PARAM_DEF(SW_API_PT_MAGIC_FRAME_MAC_SET, SW_UINT32, 4, SW_PARAM_IN, "Port ID"), \ - SW_PARAM_DEF(SW_API_PT_MAGIC_FRAME_MAC_SET, SW_MACADDR, \ - sizeof(fal_mac_addr_t), SW_PARAM_PTR|SW_PARAM_IN, "[Magic mac]"), - -#define SW_API_PT_MAGIC_FRAME_MAC_GET_DESC \ - SW_PARAM_DEF(SW_API_PT_MAGIC_FRAME_MAC_GET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \ - SW_PARAM_DEF(SW_API_PT_MAGIC_FRAME_MAC_GET, SW_UINT32, 4, SW_PARAM_IN, "Port ID"), \ - SW_PARAM_DEF(SW_API_PT_MAGIC_FRAME_MAC_GET, SW_MACADDR, \ - sizeof(fal_mac_addr_t), SW_PARAM_PTR|SW_PARAM_OUT, "[Magic mac]"), - -#define SW_API_PT_PHY_ID_GET_DESC \ - SW_PARAM_DEF(SW_API_PT_PHY_ID_GET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \ - SW_PARAM_DEF(SW_API_PT_PHY_ID_GET, SW_UINT32, 4, SW_PARAM_IN, "Port ID"), \ - SW_PARAM_DEF(SW_API_PT_PHY_ID_GET, SW_UINT16, 2, SW_PARAM_PTR|SW_PARAM_OUT, "Org ID"), \ - SW_PARAM_DEF(SW_API_PT_PHY_ID_GET, SW_UINT16, 2, SW_PARAM_PTR|SW_PARAM_OUT, "Rev ID"), - -#define SW_API_PT_WOL_STATUS_SET_DESC \ - SW_PARAM_DEF(SW_API_PT_WOL_STATUS_SET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \ - SW_PARAM_DEF(SW_API_PT_WOL_STATUS_SET, SW_UINT32, 4, SW_PARAM_IN, "Port ID"), \ - SW_PARAM_DEF(SW_API_PT_WOL_STATUS_SET, SW_ENABLE, 4, SW_PARAM_IN, "Wol Status"), - -#define SW_API_PT_WOL_STATUS_GET_DESC \ - SW_PARAM_DEF(SW_API_PT_WOL_STATUS_GET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \ - SW_PARAM_DEF(SW_API_PT_WOL_STATUS_GET, SW_UINT32, 4, SW_PARAM_IN, "Port ID"), \ - SW_PARAM_DEF(SW_API_PT_WOL_STATUS_GET, SW_ENABLE, 4, SW_PARAM_PTR|SW_PARAM_OUT, "Wol Status"), -/*qca808x_end*/ - -#define SW_API_PT_INTERFACE_MODE_SET_DESC \ - SW_PARAM_DEF(SW_API_PT_INTERFACE_MODE_SET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \ - SW_PARAM_DEF(SW_API_PT_INTERFACE_MODE_SET, SW_UINT32, 4, SW_PARAM_IN, "Port ID"), \ - SW_PARAM_DEF(SW_API_PT_INTERFACE_MODE_SET, SW_INTERFACE_MODE, \ - sizeof(fal_port_interface_mode_t), SW_PARAM_IN, "Interface Mode"), - - -#define SW_API_PT_INTERFACE_MODE_GET_DESC \ - SW_PARAM_DEF(SW_API_PT_INTERFACE_MODE_GET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \ - SW_PARAM_DEF(SW_API_PT_INTERFACE_MODE_GET, SW_UINT32, 4, SW_PARAM_IN, "Port ID"), \ - SW_PARAM_DEF(SW_API_PT_INTERFACE_MODE_GET, SW_INTERFACE_MODE, \ - sizeof(fal_port_interface_mode_t), SW_PARAM_PTR|SW_PARAM_OUT, \ - "Interface Mode"), -#define SW_API_PT_INTERFACE_MODE_APPLY_DESC \ - SW_PARAM_DEF(SW_API_PT_INTERFACE_MODE_APPLY, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), -/*qca808x_start*/ -#define SW_API_PT_INTERFACE_MODE_STATUS_GET_DESC \ - SW_PARAM_DEF(SW_API_PT_INTERFACE_MODE_STATUS_GET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \ - SW_PARAM_DEF(SW_API_PT_INTERFACE_MODE_STATUS_GET, SW_UINT32, 4, SW_PARAM_IN, "Port ID"), \ - SW_PARAM_DEF(SW_API_PT_INTERFACE_MODE_STATUS_GET, SW_INTERFACE_MODE, \ - sizeof(fal_port_interface_mode_t), SW_PARAM_PTR|SW_PARAM_OUT, \ - "Interface Status"), - -#define SW_API_DEBUG_PHYCOUNTER_SET_DESC \ - SW_PARAM_DEF(SW_API_DEBUG_PHYCOUNTER_SET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \ - SW_PARAM_DEF(SW_API_DEBUG_PHYCOUNTER_SET, SW_UINT32, 4, SW_PARAM_IN, "Port ID"), \ - SW_PARAM_DEF(SW_API_DEBUG_PHYCOUNTER_SET, SW_ENABLE, 4, SW_PARAM_IN, "Counter Status"), - -#define SW_API_DEBUG_PHYCOUNTER_GET_DESC \ - SW_PARAM_DEF(SW_API_DEBUG_PHYCOUNTER_GET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \ - SW_PARAM_DEF(SW_API_DEBUG_PHYCOUNTER_GET, SW_UINT32, 4, SW_PARAM_IN, "Port ID"), \ - SW_PARAM_DEF(SW_API_DEBUG_PHYCOUNTER_GET, SW_ENABLE, 4, \ - SW_PARAM_PTR|SW_PARAM_OUT, "Counter Status"), - -#define SW_API_DEBUG_PHYCOUNTER_SHOW_DESC \ - SW_PARAM_DEF(SW_API_DEBUG_PHYCOUNTER_SHOW, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \ - SW_PARAM_DEF(SW_API_DEBUG_PHYCOUNTER_SHOW, SW_UINT32, 4, SW_PARAM_IN, "Port ID"), \ - SW_PARAM_DEF(SW_API_DEBUG_PHYCOUNTER_SHOW, SW_COUNTER_INFO, \ - sizeof(fal_port_counter_info_t), SW_PARAM_PTR|SW_PARAM_OUT, \ - "Phy Counter Statistics On Port"), -/*qca808x_end*/ - -#define SW_API_PT_MTU_SET_DESC \ - SW_PARAM_DEF(SW_API_PT_MTU_SET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \ - SW_PARAM_DEF(SW_API_PT_MTU_SET, SW_UINT32, 4, SW_PARAM_IN, "Port ID"), \ - SW_PARAM_DEF(SW_API_PT_MTU_SET, SW_MTU_ENTRY, \ - sizeof(fal_mtu_ctrl_t), SW_PARAM_PTR|SW_PARAM_IN, "Port MTU"), - -#define SW_API_PT_MTU_GET_DESC \ - SW_PARAM_DEF(SW_API_PT_MTU_GET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \ - SW_PARAM_DEF(SW_API_PT_MTU_GET, SW_UINT32, 4, SW_PARAM_IN, "Port ID"), \ - SW_PARAM_DEF(SW_API_PT_MTU_GET, SW_MTU_INFO, \ - sizeof(fal_mtu_ctrl_t), SW_PARAM_PTR|SW_PARAM_IN|SW_PARAM_OUT, "Port MTU"), - -#define SW_API_PT_MRU_SET_DESC \ - SW_PARAM_DEF(SW_API_PT_MRU_SET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \ - SW_PARAM_DEF(SW_API_PT_MRU_SET, SW_UINT32, 4, SW_PARAM_IN, "Port ID"), \ - SW_PARAM_DEF(SW_API_PT_MRU_SET, SW_MRU_ENTRY, \ - sizeof(fal_mru_ctrl_t), SW_PARAM_PTR|SW_PARAM_IN, "Port MRU"), - -#define SW_API_PT_MRU_GET_DESC \ - SW_PARAM_DEF(SW_API_PT_MRU_GET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \ - SW_PARAM_DEF(SW_API_PT_MRU_GET, SW_UINT32, 4, SW_PARAM_IN, "Port ID"), \ - SW_PARAM_DEF(SW_API_PT_MRU_GET, SW_MRU_INFO, \ - sizeof(fal_mru_ctrl_t), SW_PARAM_PTR|SW_PARAM_IN|SW_PARAM_OUT, \ - "Port MRU"), - -#define SW_API_PT_SOURCE_FILTER_GET_DESC \ - SW_PARAM_DEF(SW_API_PT_SOURCE_FILTER_GET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \ - SW_PARAM_DEF(SW_API_PT_SOURCE_FILTER_GET, SW_UINT32, 4, SW_PARAM_IN, "Port ID"), \ - SW_PARAM_DEF(SW_API_PT_SOURCE_FILTER_GET, SW_ENABLE, 4, \ - SW_PARAM_PTR|SW_PARAM_OUT, "Enable"), - -#define SW_API_PT_SOURCE_FILTER_SET_DESC \ - SW_PARAM_DEF(SW_API_PT_SOURCE_FILTER_SET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \ - SW_PARAM_DEF(SW_API_PT_SOURCE_FILTER_SET, SW_UINT32, 4, SW_PARAM_IN, "Port ID"), \ - SW_PARAM_DEF(SW_API_PT_SOURCE_FILTER_SET, SW_ENABLE, 4, SW_PARAM_IN, "Enable"), - -#define SW_API_PT_FRAME_MAX_SIZE_GET_DESC \ - SW_PARAM_DEF(SW_API_PT_FRAME_MAX_SIZE_GET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \ - SW_PARAM_DEF(SW_API_PT_FRAME_MAX_SIZE_GET, SW_UINT32, 4, SW_PARAM_IN, "Port ID"), \ - SW_PARAM_DEF(SW_API_PT_FRAME_MAX_SIZE_GET, SW_UINT32, 4, \ - SW_PARAM_PTR|SW_PARAM_OUT, "Frame Max Size"), - -#define SW_API_PT_FRAME_MAX_SIZE_SET_DESC \ - SW_PARAM_DEF(SW_API_PT_FRAME_MAX_SIZE_SET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \ - SW_PARAM_DEF(SW_API_PT_FRAME_MAX_SIZE_SET, SW_UINT32, 4, SW_PARAM_IN, "Port ID"), \ - SW_PARAM_DEF(SW_API_PT_FRAME_MAX_SIZE_SET, SW_UINT32, 4, \ - SW_PARAM_IN, "Frame Max Size"), - -#define SW_API_PT_INTERFACE_3AZ_STATUS_SET_DESC \ - SW_PARAM_DEF(SW_API_PT_INTERFACE_3AZ_STATUS_SET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \ - SW_PARAM_DEF(SW_API_PT_INTERFACE_3AZ_STATUS_SET, SW_UINT32, 4, SW_PARAM_IN, "Port ID"), \ - SW_PARAM_DEF(SW_API_PT_INTERFACE_3AZ_STATUS_SET, SW_ENABLE, \ - sizeof(a_bool_t), SW_PARAM_IN, "Status"), - -#define SW_API_PT_INTERFACE_3AZ_STATUS_GET_DESC \ - SW_PARAM_DEF(SW_API_PT_INTERFACE_3AZ_STATUS_GET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \ - SW_PARAM_DEF(SW_API_PT_INTERFACE_3AZ_STATUS_GET, SW_UINT32, 4, SW_PARAM_IN, "Port ID"), \ - SW_PARAM_DEF(SW_API_PT_INTERFACE_3AZ_STATUS_GET, SW_ENABLE, \ - sizeof(a_bool_t), SW_PARAM_PTR|SW_PARAM_OUT, "Status"), - -#define SW_API_PT_PROMISC_MODE_SET_DESC \ - SW_PARAM_DEF(SW_API_PT_PROMISC_MODE_SET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \ - SW_PARAM_DEF(SW_API_PT_PROMISC_MODE_SET, SW_UINT32, 4, SW_PARAM_IN, "Port ID"),\ - SW_PARAM_DEF(SW_API_PT_PROMISC_MODE_SET, SW_ENABLE, 4, SW_PARAM_IN, "Enable"), - -#define SW_API_PT_PROMISC_MODE_GET_DESC \ - SW_PARAM_DEF(SW_API_PT_PROMISC_MODE_GET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"),\ - SW_PARAM_DEF(SW_API_PT_PROMISC_MODE_GET, SW_UINT32, 4, SW_PARAM_IN, "Port ID"),\ - SW_PARAM_DEF(SW_API_PT_PROMISC_MODE_GET, SW_ENABLE, 4, SW_PARAM_PTR|SW_PARAM_OUT, "Enable"), - -#define SW_API_PT_INTERFACE_EEE_CFG_SET_DESC \ - SW_PARAM_DEF(SW_API_PT_INTERFACE_EEE_CFG_SET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \ - SW_PARAM_DEF(SW_API_PT_INTERFACE_EEE_CFG_SET, SW_UINT32, 4, SW_PARAM_IN, "Port ID"), \ - SW_PARAM_DEF(SW_API_PT_INTERFACE_EEE_CFG_SET, SW_PORT_EEE_CONFIG, \ - sizeof(fal_port_eee_cfg_t), SW_PARAM_PTR|SW_PARAM_IN, "EEE"), - -#define SW_API_PT_INTERFACE_EEE_CFG_GET_DESC \ - SW_PARAM_DEF(SW_API_PT_INTERFACE_EEE_CFG_GET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \ - SW_PARAM_DEF(SW_API_PT_INTERFACE_EEE_CFG_GET, SW_UINT32, 4, SW_PARAM_IN, "Port ID"), \ - SW_PARAM_DEF(SW_API_PT_INTERFACE_EEE_CFG_GET, SW_PORT_EEE_CONFIG, \ - sizeof(fal_port_eee_cfg_t), SW_PARAM_PTR|SW_PARAM_OUT, "EEE"), - -#define SW_API_PT_SOURCE_FILTER_CONFIG_GET_DESC \ - SW_PARAM_DEF(SW_API_PT_SOURCE_FILTER_CONFIG_GET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \ - SW_PARAM_DEF(SW_API_PT_SOURCE_FILTER_CONFIG_GET, SW_UINT32, 4, SW_PARAM_IN, "Port ID"), \ - SW_PARAM_DEF(SW_API_PT_SOURCE_FILTER_CONFIG_GET, SW_SRC_FILTER_CONFIG, \ - sizeof(fal_src_filter_config_t), SW_PARAM_PTR|SW_PARAM_OUT, "srcfilter config"), - -#define SW_API_PT_SOURCE_FILTER_CONFIG_SET_DESC \ - SW_PARAM_DEF(SW_API_PT_SOURCE_FILTER_CONFIG_SET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \ - SW_PARAM_DEF(SW_API_PT_SOURCE_FILTER_CONFIG_SET, SW_UINT32, 4, SW_PARAM_IN, "Port ID"), \ - SW_PARAM_DEF(SW_API_PT_SOURCE_FILTER_CONFIG_SET, SW_SRC_FILTER_CONFIG, \ - sizeof(fal_src_filter_config_t), SW_PARAM_PTR|SW_PARAM_IN, "srcfilter config"), - -#define SW_API_PT_SWITCH_PORT_LOOPBACK_SET_DESC \ - SW_PARAM_DEF(SW_API_PT_SWITCH_PORT_LOOPBACK_SET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \ - SW_PARAM_DEF(SW_API_PT_SWITCH_PORT_LOOPBACK_SET, SW_UINT32, 4, SW_PARAM_IN, "Port ID"), \ - SW_PARAM_DEF(SW_API_PT_SWITCH_PORT_LOOPBACK_SET, SW_PORT_LOOPBACK_CONFIG, \ - sizeof(fal_loopback_config_t), SW_PARAM_PTR|SW_PARAM_IN, "LOOPBACK"), - -#define SW_API_PT_SWITCH_PORT_LOOPBACK_GET_DESC \ - SW_PARAM_DEF(SW_API_PT_SWITCH_PORT_LOOPBACK_GET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \ - SW_PARAM_DEF(SW_API_PT_SWITCH_PORT_LOOPBACK_GET, SW_UINT32, 4, SW_PARAM_IN, "Port ID"), \ - SW_PARAM_DEF(SW_API_PT_SWITCH_PORT_LOOPBACK_GET, SW_PORT_LOOPBACK_CONFIG,\ - sizeof(fal_loopback_config_t), SW_PARAM_PTR|SW_PARAM_OUT, "LOOPBACK"), - -#define SW_API_VLAN_ADD_DESC \ - SW_PARAM_DEF(SW_API_VLAN_ADD, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \ - SW_PARAM_DEF(SW_API_VLAN_ADD, SW_UINT32, 4, SW_PARAM_IN, "Vlan Id"), - -#define SW_API_VLAN_DEL_DESC \ - SW_PARAM_DEF(SW_API_VLAN_DEL, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \ - SW_PARAM_DEF(SW_API_VLAN_DEL, SW_UINT32, 4, SW_PARAM_IN, "Vlan Id"), - -#define SW_API_VLAN_MEM_UPDATE_DESC \ - SW_PARAM_DEF(SW_API_VLAN_MEM_UPDATE, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \ - SW_PARAM_DEF(SW_API_VLAN_MEM_UPDATE, SW_UINT32, 4, SW_PARAM_IN, "Vlan Id"), \ - SW_PARAM_DEF(SW_API_VLAN_MEM_UPDATE, SW_PBMP, \ - sizeof(fal_pbmp_t), SW_PARAM_IN, \ - "Member Port Map"), \ - SW_PARAM_DEF(SW_API_VLAN_MEM_UPDATE, SW_PBMP, \ - sizeof(fal_pbmp_t), SW_PARAM_IN, \ - "U Member Port Map"), - -#define SW_API_VLAN_FIND_DESC \ - SW_PARAM_DEF(SW_API_VLAN_FIND, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \ - SW_PARAM_DEF(SW_API_VLAN_FIND, SW_UINT32, 4, SW_PARAM_IN, "Vlan Id"), \ - SW_PARAM_DEF(SW_API_VLAN_FIND, SW_VLAN, \ - sizeof(fal_vlan_t), SW_PARAM_PTR|SW_PARAM_OUT, \ - "Vlan Entry"), - -#define SW_API_VLAN_NEXT_DESC \ - SW_PARAM_DEF(SW_API_VLAN_NEXT, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \ - SW_PARAM_DEF(SW_API_VLAN_NEXT, SW_UINT32, 4, SW_PARAM_IN, "Vlan Id"), \ - SW_PARAM_DEF(SW_API_VLAN_NEXT, SW_VLAN, \ - sizeof(fal_vlan_t), SW_PARAM_PTR|SW_PARAM_OUT, \ - "Vlan Entry"), - -#define SW_API_VLAN_APPEND_DESC \ - SW_PARAM_DEF(SW_API_VLAN_APPEND, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \ - SW_PARAM_DEF(SW_API_VLAN_APPEND, SW_VLAN, \ - sizeof(fal_vlan_t), SW_PARAM_PTR|SW_PARAM_IN, "Vlan Entry"), - -#define SW_API_VLAN_FLUSH_DESC \ - SW_PARAM_DEF(SW_API_VLAN_FLUSH, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), - -#define SW_API_VLAN_FID_SET_DESC \ - SW_PARAM_DEF(SW_API_VLAN_FID_SET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \ - SW_PARAM_DEF(SW_API_VLAN_FID_SET, SW_UINT32, 4, SW_PARAM_IN, "Vlan ID"), \ - SW_PARAM_DEF(SW_API_VLAN_FID_SET, SW_UINT32, 4, SW_PARAM_IN, "FDB ID"), - -#define SW_API_VLAN_FID_GET_DESC \ - SW_PARAM_DEF(SW_API_VLAN_FID_GET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \ - SW_PARAM_DEF(SW_API_VLAN_FID_GET, SW_UINT32, 4, SW_PARAM_IN, "Vlan ID"), \ - SW_PARAM_DEF(SW_API_VLAN_FID_GET, SW_UINT32, 4, SW_PARAM_PTR|SW_PARAM_OUT, "FDB ID"), - -#define SW_API_VLAN_MEMBER_ADD_DESC \ - SW_PARAM_DEF(SW_API_VLAN_MEMBER_ADD, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \ - SW_PARAM_DEF(SW_API_VLAN_MEMBER_ADD, SW_UINT32, 4, SW_PARAM_IN, "Vlan ID"), \ - SW_PARAM_DEF(SW_API_VLAN_MEMBER_ADD, SW_UINT32, 4, SW_PARAM_IN, "Port ID"), \ - SW_PARAM_DEF(SW_API_VLAN_MEMBER_ADD, SW_EGMODE, \ - sizeof(fal_pt_1q_egmode_t), \ - SW_PARAM_IN, "Port Info"), - -#define SW_API_VLAN_MEMBER_DEL_DESC \ - SW_PARAM_DEF(SW_API_VLAN_MEMBER_DEL, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \ - SW_PARAM_DEF(SW_API_VLAN_MEMBER_DEL, SW_UINT32, 4, SW_PARAM_IN, "Vlan ID"), \ - SW_PARAM_DEF(SW_API_VLAN_MEMBER_DEL, SW_UINT32, 4, SW_PARAM_IN, "Port ID"), - -#define SW_API_VLAN_LEARN_STATE_SET_DESC \ - SW_PARAM_DEF(SW_API_VLAN_LEARN_STATE_SET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \ - SW_PARAM_DEF(SW_API_VLAN_LEARN_STATE_SET, SW_UINT32, 4, SW_PARAM_IN, "Vlan ID"), \ - SW_PARAM_DEF(SW_API_VLAN_LEARN_STATE_SET, SW_ENABLE, 4, SW_PARAM_IN, "Enable"), - -#define SW_API_VLAN_LEARN_STATE_GET_DESC \ - SW_PARAM_DEF(SW_API_VLAN_LEARN_STATE_GET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \ - SW_PARAM_DEF(SW_API_VLAN_LEARN_STATE_GET, SW_UINT32, 4, SW_PARAM_IN, "Vlan ID"), \ - SW_PARAM_DEF(SW_API_VLAN_LEARN_STATE_GET, SW_ENABLE, 4, SW_PARAM_PTR|SW_PARAM_OUT, "Enable"), - -#define SW_API_LAN_WAN_CFG_SET_DESC \ - SW_PARAM_DEF(SW_API_LAN_WAN_CFG_SET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \ - SW_PARAM_DEF(SW_API_LAN_WAN_CFG_SET, SW_LAN_WAN_CFG, sizeof(qca_lan_wan_cfg_t), \ - SW_PARAM_PTR|SW_PARAM_IN, "Vlan Lan Wan Configuration"), - -#define SW_API_LAN_WAN_CFG_GET_DESC \ - SW_PARAM_DEF(SW_API_LAN_WAN_CFG_GET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \ - SW_PARAM_DEF(SW_API_LAN_WAN_CFG_GET, SW_LAN_WAN_CFG, sizeof(qca_lan_wan_cfg_t), \ - SW_PARAM_PTR|SW_PARAM_OUT, "Vlan Lan Wan Configuration"), - -#define SW_API_PT_ING_MODE_GET_DESC \ - SW_PARAM_DEF(SW_API_PT_ING_MODE_GET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \ - SW_PARAM_DEF(SW_API_PT_ING_MODE_GET, SW_UINT32, 4, SW_PARAM_IN, "Port No."), \ - SW_PARAM_DEF(SW_API_PT_ING_MODE_GET, SW_1QMODE, \ - sizeof(fal_pt_1qmode_t), \ - SW_PARAM_PTR|SW_PARAM_OUT, "1qmode"), - -#define SW_API_PT_ING_MODE_SET_DESC \ - SW_PARAM_DEF(SW_API_PT_ING_MODE_SET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \ - SW_PARAM_DEF(SW_API_PT_ING_MODE_SET, SW_UINT32, 4, SW_PARAM_IN, "Port No."), \ - SW_PARAM_DEF(SW_API_PT_ING_MODE_SET, SW_1QMODE, \ - sizeof(fal_pt_1qmode_t), \ - SW_PARAM_IN, "1qmode"), - -#define SW_API_PT_EG_MODE_GET_DESC \ - SW_PARAM_DEF(SW_API_PT_EG_MODE_GET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \ - SW_PARAM_DEF(SW_API_PT_EG_MODE_GET, SW_UINT32, 4, SW_PARAM_IN, "Port No."), \ - SW_PARAM_DEF(SW_API_PT_EG_MODE_GET, SW_EGMODE, \ - sizeof(fal_pt_1q_egmode_t),\ - SW_PARAM_PTR|SW_PARAM_OUT, "egvlan"), - -#define SW_API_PT_EG_MODE_SET_DESC \ - SW_PARAM_DEF(SW_API_PT_EG_MODE_SET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \ - SW_PARAM_DEF(SW_API_PT_EG_MODE_SET, SW_UINT32, 4, SW_PARAM_IN, "Port No."), \ - SW_PARAM_DEF(SW_API_PT_EG_MODE_SET, SW_EGMODE, \ - sizeof(fal_pt_1q_egmode_t), \ - SW_PARAM_IN, "egvlan"), - -#define SW_API_PT_VLAN_MEM_ADD_DESC \ - SW_PARAM_DEF(SW_API_PT_VLAN_MEM_ADD, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \ - SW_PARAM_DEF(SW_API_PT_VLAN_MEM_ADD, SW_UINT32, 4, SW_PARAM_IN, "Port No."), \ - SW_PARAM_DEF(SW_API_PT_VLAN_MEM_ADD, SW_UINT32, 4, SW_PARAM_IN, "Member Port Id"), - -#define SW_API_PT_VLAN_MEM_DEL_DESC \ - SW_PARAM_DEF(SW_API_PT_VLAN_MEM_DEL, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \ - SW_PARAM_DEF(SW_API_PT_VLAN_MEM_DEL, SW_UINT32, 4, SW_PARAM_IN, "Port No."), \ - SW_PARAM_DEF(SW_API_PT_VLAN_MEM_DEL, SW_UINT32, 4, SW_PARAM_IN, "Member Port Id"), - -#define SW_API_PT_VLAN_MEM_UPDATE_DESC \ - SW_PARAM_DEF(SW_API_PT_VLAN_MEM_UPDATE, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \ - SW_PARAM_DEF(SW_API_PT_VLAN_MEM_UPDATE, SW_UINT32, 4, SW_PARAM_IN, "Port No."), \ - SW_PARAM_DEF(SW_API_PT_VLAN_MEM_UPDATE, SW_PBMP, \ - sizeof(fal_pbmp_t), SW_PARAM_IN, \ - "Member Port Bitmap"), - -#define SW_API_PT_VLAN_MEM_GET_DESC \ - SW_PARAM_DEF(SW_API_PT_VLAN_MEM_GET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \ - SW_PARAM_DEF(SW_API_PT_VLAN_MEM_GET, SW_UINT32, 4, SW_PARAM_IN, "Port No."), \ - SW_PARAM_DEF(SW_API_PT_VLAN_MEM_GET, SW_PBMP, \ - sizeof(fal_pbmp_t), SW_PARAM_PTR|SW_PARAM_OUT, \ - "Member Port Bitmap"), - -#define SW_API_PT_DEF_VID_SET_DESC \ - SW_PARAM_DEF(SW_API_PT_DEF_VID_SET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \ - SW_PARAM_DEF(SW_API_PT_DEF_VID_SET, SW_UINT32, 4, SW_PARAM_IN, "Port ID."), \ - SW_PARAM_DEF(SW_API_PT_DEF_VID_SET, SW_UINT32, 4, SW_PARAM_IN, "Vlan Id"), - -#define SW_API_PT_DEF_VID_GET_DESC \ - SW_PARAM_DEF(SW_API_PT_DEF_VID_GET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \ - SW_PARAM_DEF(SW_API_PT_DEF_VID_GET, SW_UINT32, 4, SW_PARAM_IN, "Port ID."), \ - SW_PARAM_DEF(SW_API_PT_DEF_VID_GET, SW_UINT32, 4, SW_PARAM_PTR|SW_PARAM_OUT, "Vlan Id"), - -#define SW_API_PT_FORCE_DEF_VID_SET_DESC \ - SW_PARAM_DEF(SW_API_PT_FORCE_DEF_VID_SET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \ - SW_PARAM_DEF(SW_API_PT_FORCE_DEF_VID_SET, SW_UINT32, 4, SW_PARAM_IN, "Port ID"), \ - SW_PARAM_DEF(SW_API_PT_FORCE_DEF_VID_SET, SW_ENABLE, 4, SW_PARAM_IN, "Force"), - -#define SW_API_PT_FORCE_DEF_VID_GET_DESC \ - SW_PARAM_DEF(SW_API_PT_FORCE_DEF_VID_GET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \ - SW_PARAM_DEF(SW_API_PT_FORCE_DEF_VID_GET, SW_UINT32, 4, SW_PARAM_IN, "Port ID"), \ - SW_PARAM_DEF(SW_API_PT_FORCE_DEF_VID_GET, SW_ENABLE, 4, SW_PARAM_PTR|SW_PARAM_OUT, "Force"), - -#define SW_API_PT_FORCE_PORTVLAN_SET_DESC \ - SW_PARAM_DEF(SW_API_PT_FORCE_PORTVLAN_SET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \ - SW_PARAM_DEF(SW_API_PT_FORCE_PORTVLAN_SET, SW_UINT32, 4, SW_PARAM_IN, "Port ID"), \ - SW_PARAM_DEF(SW_API_PT_FORCE_PORTVLAN_SET, SW_ENABLE, 4, SW_PARAM_IN, "Force"), - -#define SW_API_PT_FORCE_PORTVLAN_GET_DESC \ - SW_PARAM_DEF(SW_API_PT_FORCE_PORTVLAN_GET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \ - SW_PARAM_DEF(SW_API_PT_FORCE_PORTVLAN_GET, SW_UINT32, 4, SW_PARAM_IN, "Port ID"), \ - SW_PARAM_DEF(SW_API_PT_FORCE_PORTVLAN_GET, SW_ENABLE, 4, SW_PARAM_PTR|SW_PARAM_OUT, "Force"), - -#define SW_API_PT_NESTVLAN_SET_DESC \ - SW_PARAM_DEF(SW_API_PT_NESTVLAN_SET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \ - SW_PARAM_DEF(SW_API_PT_NESTVLAN_SET, SW_UINT32, 4, SW_PARAM_IN, "Port ID"), \ - SW_PARAM_DEF(SW_API_PT_NESTVLAN_SET, SW_ENABLE, 4, SW_PARAM_IN, "Nestvlan"), - -#define SW_API_PT_NESTVLAN_GET_DESC \ - SW_PARAM_DEF(SW_API_PT_NESTVLAN_GET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \ - SW_PARAM_DEF(SW_API_PT_NESTVLAN_GET, SW_UINT32, 4, SW_PARAM_IN, "Port ID"), \ - SW_PARAM_DEF(SW_API_PT_NESTVLAN_GET, SW_ENABLE, 4, SW_PARAM_PTR|SW_PARAM_OUT, "Nestvlan"), - -#define SW_API_NESTVLAN_TPID_SET_DESC \ - SW_PARAM_DEF(SW_API_NESTVLAN_TPID_SET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \ - SW_PARAM_DEF(SW_API_NESTVLAN_TPID_SET, SW_UINT32, 4, SW_PARAM_IN, "TPID"), - -#define SW_API_NESTVLAN_TPID_GET_DESC \ - SW_PARAM_DEF(SW_API_NESTVLAN_TPID_GET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \ - SW_PARAM_DEF(SW_API_NESTVLAN_TPID_GET, SW_UINT32, 4, SW_PARAM_PTR|SW_PARAM_OUT, "TPID"), - -#define SW_API_PT_IN_VLAN_MODE_SET_DESC \ - SW_PARAM_DEF(SW_API_PT_IN_VLAN_MODE_SET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \ - SW_PARAM_DEF(SW_API_PT_IN_VLAN_MODE_SET, SW_UINT32, 4, SW_PARAM_IN, "Port ID"), \ - SW_PARAM_DEF(SW_API_PT_IN_VLAN_MODE_SET, SW_INVLAN, \ - sizeof(fal_pt_invlan_mode_t), SW_PARAM_IN, "Invlan"), - -#define SW_API_PT_IN_VLAN_MODE_GET_DESC \ - SW_PARAM_DEF(SW_API_PT_IN_VLAN_MODE_GET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \ - SW_PARAM_DEF(SW_API_PT_IN_VLAN_MODE_GET, SW_UINT32, 4, SW_PARAM_IN, "Port ID"), \ - SW_PARAM_DEF(SW_API_PT_IN_VLAN_MODE_GET, SW_INVLAN, \ - sizeof(fal_pt_invlan_mode_t), SW_PARAM_PTR|SW_PARAM_OUT, "Invlan"), - -#define SW_API_PT_TLS_SET_DESC \ - SW_PARAM_DEF(SW_API_PT_TLS_SET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \ - SW_PARAM_DEF(SW_API_PT_TLS_SET, SW_UINT32, 4, SW_PARAM_IN, "Port ID"), \ - SW_PARAM_DEF(SW_API_PT_TLS_SET, SW_ENABLE, 4, SW_PARAM_IN, "Enable"), - -#define SW_API_PT_TLS_GET_DESC \ - SW_PARAM_DEF(SW_API_PT_TLS_GET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \ - SW_PARAM_DEF(SW_API_PT_TLS_GET, SW_UINT32, 4, SW_PARAM_IN, "Port ID"), \ - SW_PARAM_DEF(SW_API_PT_TLS_GET, SW_ENABLE, 4, SW_PARAM_PTR|SW_PARAM_OUT, "Enable"), - -#define SW_API_PT_PRI_PROPAGATION_SET_DESC \ - SW_PARAM_DEF(SW_API_PT_PRI_PROPAGATION_SET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \ - SW_PARAM_DEF(SW_API_PT_PRI_PROPAGATION_SET, SW_UINT32, 4, SW_PARAM_IN, "Port ID"), \ - SW_PARAM_DEF(SW_API_PT_PRI_PROPAGATION_SET, SW_ENABLE, 4, SW_PARAM_IN, "Enable"), - -#define SW_API_PT_PRI_PROPAGATION_GET_DESC \ - SW_PARAM_DEF(SW_API_PT_PRI_PROPAGATION_GET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \ - SW_PARAM_DEF(SW_API_PT_PRI_PROPAGATION_GET, SW_UINT32, 4, SW_PARAM_IN, "Port ID"), \ - SW_PARAM_DEF(SW_API_PT_PRI_PROPAGATION_GET, SW_ENABLE, 4, SW_PARAM_PTR|SW_PARAM_OUT, "Enable"), - -#define SW_API_PT_DEF_SVID_SET_DESC \ - SW_PARAM_DEF(SW_API_PT_DEF_SVID_SET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \ - SW_PARAM_DEF(SW_API_PT_DEF_SVID_SET, SW_UINT32, 4, SW_PARAM_IN, "Port ID"), \ - SW_PARAM_DEF(SW_API_PT_DEF_SVID_SET, SW_UINT32, 4, SW_PARAM_IN, "svid"), - -#define SW_API_PT_DEF_SVID_GET_DESC \ - SW_PARAM_DEF(SW_API_PT_DEF_SVID_GET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \ - SW_PARAM_DEF(SW_API_PT_DEF_SVID_GET, SW_UINT32, 4, SW_PARAM_IN, "Port ID"), \ - SW_PARAM_DEF(SW_API_PT_DEF_SVID_GET, SW_UINT32, 4, SW_PARAM_PTR|SW_PARAM_OUT, "svid"), - -#define SW_API_PT_DEF_CVID_SET_DESC \ - SW_PARAM_DEF(SW_API_PT_DEF_CVID_SET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \ - SW_PARAM_DEF(SW_API_PT_DEF_CVID_SET, SW_UINT32, 4, SW_PARAM_IN, "Port ID"), \ - SW_PARAM_DEF(SW_API_PT_DEF_CVID_SET, SW_UINT32, 4, SW_PARAM_IN, "cvid"), - -#define SW_API_PT_DEF_CVID_GET_DESC \ - SW_PARAM_DEF(SW_API_PT_DEF_CVID_GET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \ - SW_PARAM_DEF(SW_API_PT_DEF_CVID_GET, SW_UINT32, 4, SW_PARAM_IN, "Port ID"), \ - SW_PARAM_DEF(SW_API_PT_DEF_CVID_GET, SW_UINT32, 4, SW_PARAM_PTR|SW_PARAM_OUT, "cvid"), - -#define SW_API_PT_VLAN_PROPAGATION_SET_DESC \ - SW_PARAM_DEF(SW_API_PT_VLAN_PROPAGATION_SET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \ - SW_PARAM_DEF(SW_API_PT_VLAN_PROPAGATION_SET, SW_UINT32, 4, SW_PARAM_IN, "Port ID"), \ - SW_PARAM_DEF(SW_API_PT_VLAN_PROPAGATION_SET, SW_VLANPROPAGATION, \ - sizeof(fal_vlan_propagation_mode_t), SW_PARAM_IN, "Vlan propagation"), - -#define SW_API_PT_VLAN_PROPAGATION_GET_DESC \ - SW_PARAM_DEF(SW_API_PT_VLAN_PROPAGATION_GET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \ - SW_PARAM_DEF(SW_API_PT_VLAN_PROPAGATION_GET, SW_UINT32, 4, SW_PARAM_IN, "Port ID"), \ - SW_PARAM_DEF(SW_API_PT_VLAN_PROPAGATION_GET, SW_VLANPROPAGATION, \ - sizeof(fal_vlan_propagation_mode_t), SW_PARAM_PTR|SW_PARAM_OUT, \ - "Vlan propagation"), - -#define SW_API_PT_VLAN_TRANS_ADD_DESC \ - SW_PARAM_DEF(SW_API_PT_VLAN_TRANS_ADD, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"),\ - SW_PARAM_DEF(SW_API_PT_VLAN_TRANS_ADD, SW_UINT32, 4, SW_PARAM_IN, "Port ID"),\ - SW_PARAM_DEF(SW_API_PT_VLAN_TRANS_ADD, SW_VLANTRANSLATION, \ - sizeof(fal_vlan_trans_entry_t), SW_PARAM_PTR|SW_PARAM_IN, "Vlan Translation"), - -#define SW_API_PT_VLAN_TRANS_DEL_DESC \ - SW_PARAM_DEF(SW_API_PT_VLAN_TRANS_DEL, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"),\ - SW_PARAM_DEF(SW_API_PT_VLAN_TRANS_DEL, SW_UINT32, 4, SW_PARAM_IN, "Port ID"),\ - SW_PARAM_DEF(SW_API_PT_VLAN_TRANS_DEL, SW_VLANTRANSLATION, \ - sizeof(fal_vlan_trans_entry_t), SW_PARAM_PTR|SW_PARAM_IN, "Vlan Translation"), - -#define SW_API_PT_VLAN_TRANS_GET_DESC \ - SW_PARAM_DEF(SW_API_PT_VLAN_TRANS_GET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"),\ - SW_PARAM_DEF(SW_API_PT_VLAN_TRANS_GET, SW_UINT32, 4, SW_PARAM_IN, "Port ID"),\ - SW_PARAM_DEF(SW_API_PT_VLAN_TRANS_GET, SW_VLANTRANSLATION, \ - sizeof(fal_vlan_trans_entry_t), SW_PARAM_PTR|SW_PARAM_IN|SW_PARAM_OUT, \ - "Vlan Translation"), - -#define SW_API_QINQ_MODE_SET_DESC \ - SW_PARAM_DEF(SW_API_QINQ_MODE_SET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \ - SW_PARAM_DEF(SW_API_QINQ_MODE_SET, SW_QINQMODE, \ - sizeof(fal_qinq_mode_t), SW_PARAM_IN, "qinq mode"), - -#define SW_API_QINQ_MODE_GET_DESC \ - SW_PARAM_DEF(SW_API_QINQ_MODE_GET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \ - SW_PARAM_DEF(SW_API_QINQ_MODE_GET, SW_QINQMODE, \ - sizeof(fal_qinq_mode_t), SW_PARAM_PTR|SW_PARAM_OUT, "qinq mode"), - -#define SW_API_PT_QINQ_ROLE_SET_DESC \ - SW_PARAM_DEF(SW_API_PT_QINQ_ROLE_SET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \ - SW_PARAM_DEF(SW_API_PT_QINQ_ROLE_SET, SW_UINT32, 4, SW_PARAM_IN, "Port ID"), \ - SW_PARAM_DEF(SW_API_PT_QINQ_ROLE_SET, SW_QINQROLE, \ - sizeof(fal_qinq_port_role_t), SW_PARAM_IN, "qinq role"), - -#define SW_API_PT_QINQ_ROLE_GET_DESC \ - SW_PARAM_DEF(SW_API_PT_QINQ_ROLE_GET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \ - SW_PARAM_DEF(SW_API_PT_QINQ_ROLE_GET, SW_UINT32, 4, SW_PARAM_IN, "Port ID"), \ - SW_PARAM_DEF(SW_API_PT_QINQ_ROLE_GET, SW_QINQROLE, \ - sizeof(fal_qinq_port_role_t), SW_PARAM_PTR|SW_PARAM_OUT, "qinq role"), - -#define SW_API_PT_VLAN_TRANS_ITERATE_DESC \ - SW_PARAM_DEF(SW_API_PT_VLAN_TRANS_ITERATE, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"),\ - SW_PARAM_DEF(SW_API_PT_VLAN_TRANS_ITERATE, SW_UINT32, 4, SW_PARAM_IN, "Port ID"),\ - SW_PARAM_DEF(SW_API_PT_VLAN_TRANS_ITERATE, SW_UINT32, 4, \ - SW_PARAM_PTR|SW_PARAM_IN|SW_PARAM_OUT, "Iterator"),\ - SW_PARAM_DEF(SW_API_PT_VLAN_TRANS_ITERATE, SW_VLANTRANSLATION, \ - sizeof(fal_vlan_trans_entry_t), SW_PARAM_PTR|SW_PARAM_OUT, "Vlan Translation"), - -#define SW_API_PT_MAC_VLAN_XLT_SET_DESC \ - SW_PARAM_DEF(SW_API_PT_MAC_VLAN_XLT_SET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \ - SW_PARAM_DEF(SW_API_PT_MAC_VLAN_XLT_SET, SW_UINT32, 4, SW_PARAM_IN, "Port ID"), \ - SW_PARAM_DEF(SW_API_PT_MAC_VLAN_XLT_SET, SW_ENABLE, 4, SW_PARAM_IN, "Status"), - -#define SW_API_PT_MAC_VLAN_XLT_GET_DESC \ - SW_PARAM_DEF(SW_API_PT_MAC_VLAN_XLT_GET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \ - SW_PARAM_DEF(SW_API_PT_MAC_VLAN_XLT_GET, SW_UINT32, 4, SW_PARAM_IN, "Port ID"), \ - SW_PARAM_DEF(SW_API_PT_MAC_VLAN_XLT_GET, SW_ENABLE, 4, SW_PARAM_PTR|SW_PARAM_OUT, "Status"), - -#define SW_API_NETISOLATE_SET_DESC \ - SW_PARAM_DEF(SW_API_NETISOLATE_SET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \ - SW_PARAM_DEF(SW_API_NETISOLATE_SET, SW_ENABLE, 4, SW_PARAM_IN, "enable"), - -#define SW_API_NETISOLATE_GET_DESC \ - SW_PARAM_DEF(SW_API_NETISOLATE_GET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \ - SW_PARAM_DEF(SW_API_NETISOLATE_GET, SW_ENABLE, 4, SW_PARAM_PTR|SW_PARAM_OUT, "enable"), - -#define SW_API_EG_FLTR_BYPASS_EN_SET_DESC \ - SW_PARAM_DEF(SW_API_EG_FLTR_BYPASS_EN_SET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \ - SW_PARAM_DEF(SW_API_EG_FLTR_BYPASS_EN_SET, SW_ENABLE, 4, SW_PARAM_IN, "enable"), - -#define SW_API_EG_FLTR_BYPASS_EN_GET_DESC \ - SW_PARAM_DEF(SW_API_EG_FLTR_BYPASS_EN_GET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \ - SW_PARAM_DEF(SW_API_EG_FLTR_BYPASS_EN_GET, SW_ENABLE, 4, SW_PARAM_PTR|SW_PARAM_OUT, "enable"), - -#define SW_API_PT_VRF_ID_SET_DESC \ - SW_PARAM_DEF(SW_API_PT_VRF_ID_SET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \ - SW_PARAM_DEF(SW_API_PT_VRF_ID_SET, SW_UINT32, 4, SW_PARAM_IN, "Port ID"), \ - SW_PARAM_DEF(SW_API_PT_VRF_ID_SET, SW_UINT32, 4, SW_PARAM_IN, "vrf_id"), - -#define SW_API_PT_VRF_ID_GET_DESC \ - SW_PARAM_DEF(SW_API_PT_VRF_ID_GET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \ - SW_PARAM_DEF(SW_API_PT_VRF_ID_GET, SW_UINT32, 4, SW_PARAM_IN, "Port ID"), \ - SW_PARAM_DEF(SW_API_PT_VRF_ID_GET, SW_UINT32, 4, SW_PARAM_PTR|SW_PARAM_OUT, "vrf_id"), - -#define SW_API_GLOBAL_QINQ_MODE_SET_DESC \ - SW_PARAM_DEF(SW_API_GLOBAL_QINQ_MODE_SET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \ - SW_PARAM_DEF(SW_API_GLOBAL_QINQ_MODE_SET, SW_GLOBAL_QINQMODE, \ - sizeof(fal_global_qinq_mode_t), SW_PARAM_PTR|SW_PARAM_IN, "global qinq mode"), - -#define SW_API_GLOBAL_QINQ_MODE_GET_DESC \ - SW_PARAM_DEF(SW_API_GLOBAL_QINQ_MODE_GET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \ - SW_PARAM_DEF(SW_API_GLOBAL_QINQ_MODE_GET, SW_GLOBAL_QINQMODE, \ - sizeof(fal_global_qinq_mode_t), SW_PARAM_PTR|SW_PARAM_OUT, "global qinq mode"), - -#define SW_API_PORT_QINQ_MODE_SET_DESC \ - SW_PARAM_DEF( SW_API_PORT_QINQ_MODE_SET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \ - SW_PARAM_DEF( SW_API_PORT_QINQ_MODE_SET, SW_UINT32, 4, SW_PARAM_IN, "Port ID"), \ - SW_PARAM_DEF( SW_API_PORT_QINQ_MODE_SET, SW_PT_QINQMODE, \ - sizeof(fal_port_qinq_role_t), SW_PARAM_PTR|SW_PARAM_IN, "port qinq mode"), - -#define SW_API_PORT_QINQ_MODE_GET_DESC \ - SW_PARAM_DEF(SW_API_PORT_QINQ_MODE_GET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \ - SW_PARAM_DEF(SW_API_PORT_QINQ_MODE_GET, SW_UINT32, 4, SW_PARAM_IN, "Port ID"), \ - SW_PARAM_DEF(SW_API_PORT_QINQ_MODE_GET, SW_PT_QINQMODE, \ - sizeof(fal_port_qinq_role_t), SW_PARAM_PTR|SW_PARAM_OUT, "port qinq mode"), - -#define SW_API_TPID_SET_DESC \ - SW_PARAM_DEF(SW_API_TPID_SET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \ - SW_PARAM_DEF(SW_API_TPID_SET, SW_TPID, \ - sizeof(fal_tpid_t), SW_PARAM_PTR|SW_PARAM_IN, "ingress tpid"), - -#define SW_API_TPID_GET_DESC \ - SW_PARAM_DEF(SW_API_TPID_GET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \ - SW_PARAM_DEF(SW_API_TPID_GET, SW_TPID, \ - sizeof(fal_tpid_t), SW_PARAM_PTR|SW_PARAM_OUT, "ingress tpid"), - -#define SW_API_EGRESS_TPID_SET_DESC \ - SW_PARAM_DEF(SW_API_EGRESS_TPID_SET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \ - SW_PARAM_DEF(SW_API_EGRESS_TPID_SET, SW_TPID, \ - sizeof(fal_tpid_t), SW_PARAM_PTR|SW_PARAM_IN, "egress tpid"), - -#define SW_API_EGRESS_TPID_GET_DESC \ - SW_PARAM_DEF(SW_API_EGRESS_TPID_GET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \ - SW_PARAM_DEF(SW_API_EGRESS_TPID_GET, SW_TPID, \ - sizeof(fal_tpid_t), SW_PARAM_PTR|SW_PARAM_OUT, "egress tpid"), - -#define SW_API_PT_INGRESS_VLAN_FILTER_SET_DESC \ - SW_PARAM_DEF( SW_API_PT_INGRESS_VLAN_FILTER_SET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \ - SW_PARAM_DEF( SW_API_PT_INGRESS_VLAN_FILTER_SET, SW_UINT32, 4, SW_PARAM_IN, "Port ID"), \ - SW_PARAM_DEF( SW_API_PT_INGRESS_VLAN_FILTER_SET, SW_INGRESS_FILTER, \ - sizeof(fal_ingress_vlan_filter_t), SW_PARAM_PTR|SW_PARAM_IN, \ - "ingress filter mode"), - -#define SW_API_PT_INGRESS_VLAN_FILTER_GET_DESC \ - SW_PARAM_DEF(SW_API_PT_INGRESS_VLAN_FILTER_GET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \ - SW_PARAM_DEF(SW_API_PT_INGRESS_VLAN_FILTER_GET, SW_UINT32, 4, SW_PARAM_IN, "Port ID"), \ - SW_PARAM_DEF(SW_API_PT_INGRESS_VLAN_FILTER_GET, SW_INGRESS_FILTER, \ - sizeof(fal_ingress_vlan_filter_t), SW_PARAM_PTR|SW_PARAM_OUT, \ - "ingress filter mode"), - -#define SW_API_PT_DEFAULT_VLANTAG_SET_DESC \ - SW_PARAM_DEF( SW_API_PT_DEFAULT_VLANTAG_SET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \ - SW_PARAM_DEF( SW_API_PT_DEFAULT_VLANTAG_SET, SW_UINT32, 4, SW_PARAM_IN, "Port ID"), \ - SW_PARAM_DEF( SW_API_PT_DEFAULT_VLANTAG_SET, SW_PT_VLAN_DIRECTION, \ - sizeof(fal_port_vlan_direction_t), SW_PARAM_IN, "vlan direction"), \ - SW_PARAM_DEF( SW_API_PT_DEFAULT_VLANTAG_SET, SW_PT_DEF_VID_EN, \ - sizeof(fal_port_default_vid_enable_t), SW_PARAM_PTR|SW_PARAM_IN, \ - "default vid en"), \ - SW_PARAM_DEF( SW_API_PT_DEFAULT_VLANTAG_SET, SW_PT_VLAN_TAG, \ - sizeof(fal_port_vlan_tag_t), SW_PARAM_PTR|SW_PARAM_IN, "vlan tag"), - -#define SW_API_PT_DEFAULT_VLANTAG_GET_DESC \ - SW_PARAM_DEF(SW_API_PT_DEFAULT_VLANTAG_GET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \ - SW_PARAM_DEF(SW_API_PT_DEFAULT_VLANTAG_GET, SW_UINT32, 4, SW_PARAM_IN, "Port ID"), \ - SW_PARAM_DEF(SW_API_PT_DEFAULT_VLANTAG_GET, SW_PT_VLAN_DIRECTION, \ - sizeof(fal_port_vlan_direction_t), SW_PARAM_IN, "vlan direction"), \ - SW_PARAM_DEF(SW_API_PT_DEFAULT_VLANTAG_GET, SW_PT_DEF_VID_EN, \ - sizeof(fal_port_default_vid_enable_t), SW_PARAM_PTR|SW_PARAM_OUT, \ - "default vid en"), \ - SW_PARAM_DEF(SW_API_PT_DEFAULT_VLANTAG_GET, SW_PT_VLAN_TAG, \ - sizeof(fal_port_vlan_tag_t), SW_PARAM_PTR|SW_PARAM_OUT, "vlan tag"), - -#define SW_API_PT_TAG_PROPAGATION_SET_DESC \ - SW_PARAM_DEF( SW_API_PT_TAG_PROPAGATION_SET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \ - SW_PARAM_DEF( SW_API_PT_TAG_PROPAGATION_SET, SW_UINT32, 4, SW_PARAM_IN, "Port ID"), \ - SW_PARAM_DEF( SW_API_PT_TAG_PROPAGATION_SET, SW_PT_VLAN_DIRECTION, \ - sizeof(fal_port_vlan_direction_t), SW_PARAM_IN, "vlan direction"), \ - SW_PARAM_DEF( SW_API_PT_TAG_PROPAGATION_SET, SW_TAG_PROPAGATION, \ - sizeof(fal_vlantag_propagation_t), SW_PARAM_PTR|SW_PARAM_IN, \ - "tag propagation"), - -#define SW_API_PT_TAG_PROPAGATION_GET_DESC \ - SW_PARAM_DEF(SW_API_PT_TAG_PROPAGATION_GET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \ - SW_PARAM_DEF(SW_API_PT_TAG_PROPAGATION_GET, SW_UINT32, 4, SW_PARAM_IN, "Port ID"), \ - SW_PARAM_DEF(SW_API_PT_TAG_PROPAGATION_GET, SW_PT_VLAN_DIRECTION, \ - sizeof(fal_port_vlan_direction_t), SW_PARAM_IN, "vlan direction"), \ - SW_PARAM_DEF(SW_API_PT_TAG_PROPAGATION_GET, SW_TAG_PROPAGATION, \ - sizeof(fal_vlantag_propagation_t), SW_PARAM_PTR|SW_PARAM_OUT, \ - "tag propagation"), - -#define SW_API_PT_VLANTAG_EGMODE_SET_DESC \ - SW_PARAM_DEF( SW_API_PT_VLANTAG_EGMODE_SET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \ - SW_PARAM_DEF( SW_API_PT_VLANTAG_EGMODE_SET, SW_UINT32, 4, SW_PARAM_IN, "Port ID"), \ - SW_PARAM_DEF( SW_API_PT_VLANTAG_EGMODE_SET, SW_EGRESS_MODE, \ - sizeof(fal_vlantag_egress_mode_t), SW_PARAM_PTR|SW_PARAM_IN, "egress mode"), - -#define SW_API_PT_VLANTAG_EGMODE_GET_DESC \ - SW_PARAM_DEF(SW_API_PT_VLANTAG_EGMODE_GET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \ - SW_PARAM_DEF(SW_API_PT_VLANTAG_EGMODE_GET, SW_UINT32, 4, SW_PARAM_IN, "Port ID"), \ - SW_PARAM_DEF(SW_API_PT_VLANTAG_EGMODE_GET, SW_EGRESS_MODE, \ - sizeof(fal_vlantag_egress_mode_t), SW_PARAM_PTR|SW_PARAM_OUT, "egress mode"), - -#define SW_API_PT_VLAN_XLT_MISS_CMD_SET_DESC \ - SW_PARAM_DEF( SW_API_PT_VLAN_XLT_MISS_CMD_SET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \ - SW_PARAM_DEF( SW_API_PT_VLAN_XLT_MISS_CMD_SET, SW_UINT32, 4, SW_PARAM_IN, "Port ID"), \ - SW_PARAM_DEF( SW_API_PT_VLAN_XLT_MISS_CMD_SET, SW_MACCMD, \ - sizeof(fal_fwd_cmd_t), SW_PARAM_IN, "miss xlt cmd"), - -#define SW_API_PT_VLAN_XLT_MISS_CMD_GET_DESC \ - SW_PARAM_DEF( SW_API_PT_VLAN_XLT_MISS_CMD_GET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \ - SW_PARAM_DEF( SW_API_PT_VLAN_XLT_MISS_CMD_GET, SW_UINT32, 4, SW_PARAM_IN, "Port ID"), \ - SW_PARAM_DEF( SW_API_PT_VLAN_XLT_MISS_CMD_GET, SW_MACCMD, \ - sizeof(fal_fwd_cmd_t), SW_PARAM_PTR|SW_PARAM_OUT, "miss xlt cmd"), - -#define SW_API_PT_VSI_EGMODE_SET_DESC \ - SW_PARAM_DEF(SW_API_PT_VSI_EGMODE_SET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \ - SW_PARAM_DEF(SW_API_PT_VSI_EGMODE_SET, SW_UINT32, 4, SW_PARAM_IN, "VSI ID"), \ - SW_PARAM_DEF(SW_API_PT_VSI_EGMODE_SET, SW_UINT32, 4, SW_PARAM_IN, "Port ID"), \ - SW_PARAM_DEF(SW_API_PT_VSI_EGMODE_SET, SW_EGMODE, \ - sizeof(fal_pt_1q_egmode_t), SW_PARAM_IN, "Egress mode"), - -#define SW_API_PT_VSI_EGMODE_GET_DESC \ - SW_PARAM_DEF(SW_API_PT_VSI_EGMODE_GET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \ - SW_PARAM_DEF(SW_API_PT_VSI_EGMODE_GET, SW_UINT32, 4, SW_PARAM_IN, "VSI ID"), \ - SW_PARAM_DEF(SW_API_PT_VSI_EGMODE_GET, SW_UINT32, 4, SW_PARAM_IN, "Port ID"), \ - SW_PARAM_DEF(SW_API_PT_VSI_EGMODE_GET, SW_EGMODE, \ - sizeof(fal_pt_1q_egmode_t), SW_PARAM_PTR|SW_PARAM_OUT, "Egress mode"), - -#define SW_API_PT_VLANTAG_VSI_EGMODE_EN_SET_DESC \ - SW_PARAM_DEF(SW_API_PT_VLANTAG_VSI_EGMODE_EN_SET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \ - SW_PARAM_DEF(SW_API_PT_VLANTAG_VSI_EGMODE_EN_SET, SW_UINT32, 4, SW_PARAM_IN, "Port ID"), \ - SW_PARAM_DEF(SW_API_PT_VLANTAG_VSI_EGMODE_EN_SET, SW_ENABLE, 4, SW_PARAM_IN, "Enable"), - -#define SW_API_PT_VLANTAG_VSI_EGMODE_EN_GET_DESC \ - SW_PARAM_DEF(SW_API_PT_VLANTAG_VSI_EGMODE_EN_GET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \ - SW_PARAM_DEF(SW_API_PT_VLANTAG_VSI_EGMODE_EN_GET, SW_UINT32, 4, SW_PARAM_IN, "Port ID"), \ - SW_PARAM_DEF(SW_API_PT_VLANTAG_VSI_EGMODE_EN_GET, SW_ENABLE, 4, \ - SW_PARAM_PTR|SW_PARAM_OUT, "Enable"), - -#define SW_API_PT_VLAN_TRANS_ADV_ADD_DESC \ - SW_PARAM_DEF(SW_API_PT_VLAN_TRANS_ADV_ADD, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \ - SW_PARAM_DEF(SW_API_PT_VLAN_TRANS_ADV_ADD, SW_UINT32, 4, SW_PARAM_IN, "Port ID"), \ - SW_PARAM_DEF(SW_API_PT_VLAN_TRANS_ADV_ADD, SW_PT_VLAN_DIRECTION, \ - sizeof(fal_port_vlan_direction_t), SW_PARAM_IN, "vlan direction"), \ - SW_PARAM_DEF(SW_API_PT_VLAN_TRANS_ADV_ADD, SW_PT_VLAN_TRANS_ADV_RULE, \ - sizeof(fal_vlan_trans_adv_rule_t), SW_PARAM_PTR|SW_PARAM_IN, \ - "vlan trans rule"), \ - SW_PARAM_DEF(SW_API_PT_VLAN_TRANS_ADV_ADD, SW_PT_VLAN_TRANS_ADV_ACTION, \ - sizeof(fal_vlan_trans_adv_action_t), SW_PARAM_PTR|SW_PARAM_IN, \ - "vlan trans action"), - -#define SW_API_PT_VLAN_TRANS_ADV_DEL_DESC \ - SW_PARAM_DEF(SW_API_PT_VLAN_TRANS_ADV_DEL, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \ - SW_PARAM_DEF(SW_API_PT_VLAN_TRANS_ADV_DEL, SW_UINT32, 4, SW_PARAM_IN, "Port ID"), \ - SW_PARAM_DEF(SW_API_PT_VLAN_TRANS_ADV_DEL, SW_PT_VLAN_DIRECTION, \ - sizeof(fal_port_vlan_direction_t), SW_PARAM_IN, "vlan direction"), \ - SW_PARAM_DEF(SW_API_PT_VLAN_TRANS_ADV_DEL, SW_PT_VLAN_TRANS_ADV_RULE, \ - sizeof(fal_vlan_trans_adv_rule_t), SW_PARAM_PTR|SW_PARAM_IN, \ - "vlan trans rule"), \ - SW_PARAM_DEF(SW_API_PT_VLAN_TRANS_ADV_DEL, SW_PT_VLAN_TRANS_ADV_ACTION, \ - sizeof(fal_vlan_trans_adv_action_t), SW_PARAM_PTR|SW_PARAM_IN, \ - "vlan trans action"), - -#define SW_API_PT_VLAN_TRANS_ADV_GETFIRST_DESC \ - SW_PARAM_DEF(SW_API_PT_VLAN_TRANS_ADV_GETFIRST, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \ - SW_PARAM_DEF(SW_API_PT_VLAN_TRANS_ADV_GETFIRST, SW_UINT32, 4, SW_PARAM_IN, "Port ID"), \ - SW_PARAM_DEF(SW_API_PT_VLAN_TRANS_ADV_GETFIRST, SW_PT_VLAN_DIRECTION, \ - sizeof(fal_port_vlan_direction_t), SW_PARAM_IN, "vlan direction"), \ - SW_PARAM_DEF(SW_API_PT_VLAN_TRANS_ADV_GETFIRST, SW_PT_VLAN_TRANS_ADV_RULE, \ - sizeof(fal_vlan_trans_adv_rule_t), SW_PARAM_PTR|SW_PARAM_OUT, \ - "vlan trans rule"), \ - SW_PARAM_DEF(SW_API_PT_VLAN_TRANS_ADV_GETFIRST, SW_PT_VLAN_TRANS_ADV_ACTION, \ - sizeof(fal_vlan_trans_adv_action_t), SW_PARAM_PTR|SW_PARAM_OUT, \ - "vlan trans action"), - -#define SW_API_PT_VLAN_TRANS_ADV_GETNEXT_DESC \ - SW_PARAM_DEF(SW_API_PT_VLAN_TRANS_ADV_GETNEXT, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \ - SW_PARAM_DEF(SW_API_PT_VLAN_TRANS_ADV_GETNEXT, SW_UINT32, 4, SW_PARAM_IN, "Port ID"), \ - SW_PARAM_DEF(SW_API_PT_VLAN_TRANS_ADV_GETNEXT, SW_PT_VLAN_DIRECTION, \ - sizeof(fal_port_vlan_direction_t), SW_PARAM_IN, "vlan direction"), \ - SW_PARAM_DEF(SW_API_PT_VLAN_TRANS_ADV_GETNEXT, SW_PT_VLAN_TRANS_ADV_RULE, \ - sizeof(fal_vlan_trans_adv_rule_t), SW_PARAM_PTR|SW_PARAM_IN|SW_PARAM_OUT, \ - "vlan trans rule"), \ - SW_PARAM_DEF(SW_API_PT_VLAN_TRANS_ADV_GETNEXT, SW_PT_VLAN_TRANS_ADV_ACTION, \ - sizeof(fal_vlan_trans_adv_action_t), SW_PARAM_PTR|SW_PARAM_IN|SW_PARAM_OUT, \ - "vlan trans action"), - -#define SW_API_PT_VLAN_COUNTER_GET_DESC \ - SW_PARAM_DEF(SW_API_PT_VLAN_COUNTER_GET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \ - SW_PARAM_DEF(SW_API_PT_VLAN_COUNTER_GET, SW_UINT32, 4, SW_PARAM_IN, "Cnt Index"), \ - SW_PARAM_DEF(SW_API_PT_VLAN_COUNTER_GET, SW_PT_VLAN_COUNTER, \ - sizeof(fal_port_vlan_counter_t), SW_PARAM_PTR|SW_PARAM_OUT, "enable"), - -#define SW_API_PT_VLAN_COUNTER_CLEANUP_DESC \ - SW_PARAM_DEF(SW_API_PT_VLAN_COUNTER_CLEANUP, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \ - SW_PARAM_DEF(SW_API_PT_VLAN_COUNTER_CLEANUP, SW_UINT32, 4, SW_PARAM_IN, "Cnt Index"), - -#define SW_API_FDB_ADD_DESC \ - SW_PARAM_DEF(SW_API_FDB_ADD, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"),\ - SW_PARAM_DEF(SW_API_FDB_ADD, SW_FDBENTRY, \ - sizeof(fal_fdb_entry_t), SW_PARAM_PTR|SW_PARAM_IN, "Fdb Entry"), - -#define SW_API_FDB_RFS_SET_DESC \ - SW_PARAM_DEF(SW_API_FDB_RFS_SET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"),\ - SW_PARAM_DEF(SW_API_FDB_RFS_SET, SW_FDB_RFS, \ - sizeof(fal_fdb_rfs_t), SW_PARAM_PTR|SW_PARAM_IN, "Fdb Rfs"), - -#define SW_API_FDB_RFS_DEL_DESC \ - SW_PARAM_DEF(SW_API_FDB_RFS_DEL, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"),\ - SW_PARAM_DEF(SW_API_FDB_RFS_DEL, SW_FDB_RFS, \ - sizeof(fal_fdb_rfs_t), SW_PARAM_PTR|SW_PARAM_IN, "Fdb Rfs"), - - -#define SW_API_FDB_DELALL_DESC \ - SW_PARAM_DEF(SW_API_FDB_DELALL, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"),\ - SW_PARAM_DEF(SW_API_FDB_DELALL, SW_UINT32, 4, SW_PARAM_IN, "Flag"), - -#define SW_API_FDB_DELPORT_DESC \ - SW_PARAM_DEF(SW_API_FDB_DELPORT, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"),\ - SW_PARAM_DEF(SW_API_FDB_DELPORT, SW_UINT32, 4, SW_PARAM_IN, "Port ID"),\ - SW_PARAM_DEF(SW_API_FDB_DELPORT, SW_UINT32, 4, SW_PARAM_IN, "Flag"), - -#define SW_API_FDB_DELMAC_DESC \ - SW_PARAM_DEF(SW_API_FDB_DELMAC, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"),\ - SW_PARAM_DEF(SW_API_FDB_DELMAC, SW_FDBENTRY, \ - sizeof(fal_fdb_entry_t), SW_PARAM_PTR|SW_PARAM_IN, "Fdb Entry"), - -#define SW_API_FDB_FIRST_DESC \ - SW_PARAM_DEF(SW_API_FDB_FIRST, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"),\ - SW_PARAM_DEF(SW_API_FDB_FIRST, SW_FDBENTRY, \ - sizeof(fal_fdb_entry_t), SW_PARAM_PTR|SW_PARAM_OUT, "Fdb Entry"), - -#define SW_API_FDB_NEXT_DESC \ - SW_PARAM_DEF(SW_API_FDB_NEXT, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"),\ - SW_PARAM_DEF(SW_API_FDB_NEXT, SW_FDBENTRY, \ - sizeof(fal_fdb_entry_t), SW_PARAM_PTR|SW_PARAM_IN|SW_PARAM_OUT, "Fdb Entry"), - -#define SW_API_FDB_FIND_DESC \ - SW_PARAM_DEF(SW_API_FDB_FIND, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"),\ - SW_PARAM_DEF(SW_API_FDB_FIND, SW_FDBENTRY, \ - sizeof(fal_fdb_entry_t), SW_PARAM_PTR|SW_PARAM_IN|SW_PARAM_OUT, "Fdb Entry"), - -#define SW_API_FDB_PT_LEARN_SET_DESC \ - SW_PARAM_DEF(SW_API_FDB_PT_LEARN_SET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"),\ - SW_PARAM_DEF(SW_API_FDB_PT_LEARN_SET, SW_UINT32, 4, SW_PARAM_IN, "Port ID"),\ - SW_PARAM_DEF(SW_API_FDB_PT_LEARN_SET, SW_ENABLE, 4, SW_PARAM_IN, "Learn"), - -#define SW_API_FDB_PT_LEARN_GET_DESC \ - SW_PARAM_DEF(SW_API_FDB_PT_LEARN_GET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"),\ - SW_PARAM_DEF(SW_API_FDB_PT_LEARN_GET, SW_UINT32, 4, SW_PARAM_IN, "Port ID"),\ - SW_PARAM_DEF(SW_API_FDB_PT_LEARN_GET, SW_ENABLE, 4, SW_PARAM_PTR|SW_PARAM_OUT, "Learn"), - -#define SW_API_FDB_PT_NEWADDR_LEARN_SET_DESC \ - SW_PARAM_DEF(SW_API_FDB_PT_NEWADDR_LEARN_SET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \ - SW_PARAM_DEF(SW_API_FDB_PT_NEWADDR_LEARN_SET, SW_UINT32, 4, SW_PARAM_IN, "Port ID"),\ - SW_PARAM_DEF(SW_API_FDB_PT_NEWADDR_LEARN_SET, SW_ENABLE, 4, SW_PARAM_IN, "Learn Ctrl"),\ - SW_PARAM_DEF(SW_API_FDB_PT_NEWADDR_LEARN_SET, SW_MACCMD, \ - sizeof(fal_fwd_cmd_t), SW_PARAM_IN, "Action"), - -#define SW_API_FDB_PT_NEWADDR_LEARN_GET_DESC \ - SW_PARAM_DEF(SW_API_FDB_PT_NEWADDR_LEARN_GET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \ - SW_PARAM_DEF(SW_API_FDB_PT_NEWADDR_LEARN_GET, SW_UINT32, 4, SW_PARAM_IN, "Port ID"),\ - SW_PARAM_DEF(SW_API_FDB_PT_NEWADDR_LEARN_GET, SW_ENABLE, 4, \ - SW_PARAM_PTR|SW_PARAM_OUT, "Learn Ctrl"),\ - SW_PARAM_DEF(SW_API_FDB_PT_NEWADDR_LEARN_GET, SW_MACCMD, \ - sizeof(fal_fwd_cmd_t), SW_PARAM_PTR|SW_PARAM_OUT, "Action"), - -#define SW_API_FDB_PT_STAMOVE_SET_DESC \ - SW_PARAM_DEF(SW_API_FDB_PT_STAMOVE_SET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \ - SW_PARAM_DEF(SW_API_FDB_PT_STAMOVE_SET, SW_UINT32, 4, SW_PARAM_IN, "Port ID"),\ - SW_PARAM_DEF(SW_API_FDB_PT_STAMOVE_SET, SW_ENABLE, 4, SW_PARAM_IN, "Station Move"),\ - SW_PARAM_DEF(SW_API_FDB_PT_STAMOVE_SET, SW_MACCMD, \ - sizeof(fal_fwd_cmd_t), SW_PARAM_IN, "Action"), - -#define SW_API_FDB_PT_STAMOVE_GET_DESC \ - SW_PARAM_DEF(SW_API_FDB_PT_STAMOVE_GET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \ - SW_PARAM_DEF(SW_API_FDB_PT_STAMOVE_GET, SW_UINT32, 4, SW_PARAM_IN, "Port ID"),\ - SW_PARAM_DEF(SW_API_FDB_PT_STAMOVE_GET, SW_ENABLE, 4, \ - SW_PARAM_PTR|SW_PARAM_OUT, "Station Move"),\ - SW_PARAM_DEF(SW_API_FDB_PT_STAMOVE_GET, SW_MACCMD, \ - sizeof(fal_fwd_cmd_t), SW_PARAM_PTR|SW_PARAM_OUT, "Action"), - -#define SW_API_FDB_AGE_CTRL_SET_DESC \ - SW_PARAM_DEF(SW_API_FDB_AGE_CTRL_SET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"),\ - SW_PARAM_DEF(SW_API_FDB_AGE_CTRL_SET, SW_ENABLE, 4, SW_PARAM_IN, "Age"), - -#define SW_API_FDB_AGE_CTRL_GET_DESC \ - SW_PARAM_DEF(SW_API_FDB_AGE_CTRL_GET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"),\ - SW_PARAM_DEF(SW_API_FDB_AGE_CTRL_GET, SW_ENABLE, 4, SW_PARAM_PTR|SW_PARAM_OUT, "Age"), - -#define SW_API_FDB_LEARN_CTRL_SET_DESC \ - SW_PARAM_DEF(SW_API_FDB_LEARN_CTRL_SET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"),\ - SW_PARAM_DEF(SW_API_FDB_LEARN_CTRL_SET, SW_ENABLE, 4, SW_PARAM_IN, "Learn Ctrl"), - -#define SW_API_FDB_LEARN_CTRL_GET_DESC \ - SW_PARAM_DEF(SW_API_FDB_LEARN_CTRL_GET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"),\ - SW_PARAM_DEF(SW_API_FDB_LEARN_CTRL_GET, SW_ENABLE, 4, \ - SW_PARAM_PTR|SW_PARAM_OUT, "Learn Ctrl"), - -#define SW_API_FDB_VLAN_IVL_SVL_SET_DESC \ - SW_PARAM_DEF(SW_API_FDB_VLAN_IVL_SVL_SET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"),\ - SW_PARAM_DEF(SW_API_FDB_VLAN_IVL_SVL_SET, SW_FDBSMODE, 4, SW_PARAM_IN, "Smode"), - -#define SW_API_FDB_VLAN_IVL_SVL_GET_DESC \ - SW_PARAM_DEF(SW_API_FDB_VLAN_IVL_SVL_GET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"),\ - SW_PARAM_DEF(SW_API_FDB_VLAN_IVL_SVL_GET, SW_FDBSMODE, 4, \ - SW_PARAM_PTR|SW_PARAM_OUT, "Smode"), - -#define SW_API_FDB_AGE_TIME_SET_DESC \ - SW_PARAM_DEF(SW_API_FDB_AGE_TIME_SET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"),\ - SW_PARAM_DEF(SW_API_FDB_AGE_TIME_SET, SW_UINT32, 4, \ - SW_PARAM_PTR|SW_PARAM_IN|SW_PARAM_OUT, "Time"), - -#define SW_API_FDB_AGE_TIME_GET_DESC \ - SW_PARAM_DEF(SW_API_FDB_AGE_TIME_GET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"),\ - SW_PARAM_DEF(SW_API_FDB_AGE_TIME_GET, SW_UINT32, 4, SW_PARAM_PTR|SW_PARAM_OUT, "Time"), - -#define SW_API_FDB_ITERATE_DESC \ - SW_PARAM_DEF(SW_API_FDB_ITERATE, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"),\ - SW_PARAM_DEF(SW_API_FDB_ITERATE, SW_UINT32, 4, \ - SW_PARAM_PTR|SW_PARAM_IN|SW_PARAM_OUT, "Iterator"),\ - SW_PARAM_DEF(SW_API_FDB_ITERATE, SW_FDBENTRY, \ - sizeof(fal_fdb_entry_t), SW_PARAM_PTR|SW_PARAM_OUT, "Fdb Entry"), - -#define SW_API_FDB_EXTEND_NEXT_DESC \ - SW_PARAM_DEF(SW_API_FDB_EXTEND_NEXT, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"),\ - SW_PARAM_DEF(SW_API_FDB_EXTEND_NEXT, SW_FDBOPRATION, \ - sizeof(fal_fdb_op_t), SW_PARAM_PTR|SW_PARAM_IN, "OperateOption"),\ - SW_PARAM_DEF(SW_API_FDB_EXTEND_NEXT, SW_FDBENTRY, \ - sizeof(fal_fdb_entry_t), SW_PARAM_PTR|SW_PARAM_IN|SW_PARAM_OUT, "Fdb Entry"), - -#define SW_API_FDB_EXTEND_FIRST_DESC \ - SW_PARAM_DEF(SW_API_FDB_EXTEND_FIRST, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"),\ - SW_PARAM_DEF(SW_API_FDB_EXTEND_FIRST, SW_FDBOPRATION, \ - sizeof(fal_fdb_op_t), SW_PARAM_PTR|SW_PARAM_IN, "OperateOption"),\ - SW_PARAM_DEF(SW_API_FDB_EXTEND_FIRST, SW_FDBENTRY, \ - sizeof(fal_fdb_entry_t), SW_PARAM_PTR|SW_PARAM_IN|SW_PARAM_OUT, "Fdb Entry"), - -#define SW_API_FDB_TRANSFER_DESC \ - SW_PARAM_DEF(SW_API_FDB_TRANSFER, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"),\ - SW_PARAM_DEF(SW_API_FDB_TRANSFER, SW_UINT32, 4, SW_PARAM_IN, "Old Port ID"),\ - SW_PARAM_DEF(SW_API_FDB_TRANSFER, SW_UINT32, 4, SW_PARAM_IN, "New Port ID"),\ - SW_PARAM_DEF(SW_API_FDB_TRANSFER, SW_UINT32, 4, SW_PARAM_IN, "FID"),\ - SW_PARAM_DEF(SW_API_FDB_TRANSFER, SW_FDBOPRATION, \ - sizeof(fal_fdb_op_t), SW_PARAM_PTR|SW_PARAM_IN, "OperateOption"), - -#define SW_API_PT_FDB_LEARN_COUNTER_GET_DESC \ - SW_PARAM_DEF(SW_API_PT_FDB_LEARN_COUNTER_GET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \ - SW_PARAM_DEF(SW_API_PT_FDB_LEARN_COUNTER_GET, SW_UINT32, 4, SW_PARAM_IN, "Port ID"),\ - SW_PARAM_DEF(SW_API_PT_FDB_LEARN_COUNTER_GET, SW_UINT32, 4, \ - SW_PARAM_PTR|SW_PARAM_OUT, "LearnCnt"), - -#define SW_API_PT_FDB_LEARN_LIMIT_SET_DESC \ - SW_PARAM_DEF(SW_API_PT_FDB_LEARN_LIMIT_SET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \ - SW_PARAM_DEF(SW_API_PT_FDB_LEARN_LIMIT_SET, SW_UINT32, 4, SW_PARAM_IN, "Port ID"),\ - SW_PARAM_DEF(SW_API_PT_FDB_LEARN_LIMIT_SET, SW_ENABLE, 4, SW_PARAM_IN, "Enable"), \ - SW_PARAM_DEF(SW_API_PT_FDB_LEARN_LIMIT_SET, SW_UINT32, 4, SW_PARAM_IN, "LimitCnt"), - -#define SW_API_PT_FDB_LEARN_LIMIT_GET_DESC \ - SW_PARAM_DEF(SW_API_PT_FDB_LEARN_LIMIT_GET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"),\ - SW_PARAM_DEF(SW_API_PT_FDB_LEARN_LIMIT_GET, SW_UINT32, 4, SW_PARAM_IN, "Port ID"),\ - SW_PARAM_DEF(SW_API_PT_FDB_LEARN_LIMIT_GET, SW_ENABLE, 4, \ - SW_PARAM_PTR|SW_PARAM_OUT, "Enable"), \ - SW_PARAM_DEF(SW_API_PT_FDB_LEARN_LIMIT_GET, SW_UINT32, 4, \ - SW_PARAM_PTR|SW_PARAM_OUT, "LimitCnt"), - -#define SW_API_PT_FDB_LEARN_EXCEED_CMD_SET_DESC \ - SW_PARAM_DEF(SW_API_PT_FDB_LEARN_EXCEED_CMD_SET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \ - SW_PARAM_DEF(SW_API_PT_FDB_LEARN_EXCEED_CMD_SET, SW_UINT32, 4, SW_PARAM_IN, "Port ID"),\ - SW_PARAM_DEF(SW_API_PT_FDB_LEARN_EXCEED_CMD_SET, SW_MACCMD, \ - sizeof(fal_fwd_cmd_t), SW_PARAM_IN, "cmd"), - -#define SW_API_PT_FDB_LEARN_EXCEED_CMD_GET_DESC \ - SW_PARAM_DEF(SW_API_PT_FDB_LEARN_EXCEED_CMD_GET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \ - SW_PARAM_DEF(SW_API_PT_FDB_LEARN_EXCEED_CMD_GET, SW_UINT32, 4, SW_PARAM_IN, "Port ID"),\ - SW_PARAM_DEF(SW_API_PT_FDB_LEARN_EXCEED_CMD_GET, SW_MACCMD, \ - sizeof(fal_fwd_cmd_t), SW_PARAM_PTR|SW_PARAM_OUT, "cmd"), - -#define SW_API_FDB_LEARN_LIMIT_SET_DESC \ - SW_PARAM_DEF(SW_API_FDB_LEARN_LIMIT_SET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \ - SW_PARAM_DEF(SW_API_FDB_LEARN_LIMIT_SET, SW_ENABLE, 4, SW_PARAM_IN, "Enable"), \ - SW_PARAM_DEF(SW_API_FDB_LEARN_LIMIT_SET, SW_UINT32, 4, SW_PARAM_IN, "LimitCnt"), - -#define SW_API_FDB_LEARN_LIMIT_GET_DESC \ - SW_PARAM_DEF(SW_API_FDB_LEARN_LIMIT_GET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"),\ - SW_PARAM_DEF(SW_API_FDB_LEARN_LIMIT_GET, SW_ENABLE, 4, \ - SW_PARAM_PTR|SW_PARAM_OUT, "Enable"), \ - SW_PARAM_DEF(SW_API_FDB_LEARN_LIMIT_GET, SW_UINT32, 4, \ - SW_PARAM_PTR|SW_PARAM_OUT, "LimitCnt"), - -#define SW_API_FDB_LEARN_EXCEED_CMD_SET_DESC \ - SW_PARAM_DEF(SW_API_FDB_LEARN_EXCEED_CMD_SET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \ - SW_PARAM_DEF(SW_API_FDB_LEARN_EXCEED_CMD_SET, SW_MACCMD, \ - sizeof(fal_fwd_cmd_t), SW_PARAM_IN, "cmd"), - -#define SW_API_FDB_LEARN_EXCEED_CMD_GET_DESC \ - SW_PARAM_DEF(SW_API_FDB_LEARN_EXCEED_CMD_GET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \ - SW_PARAM_DEF(SW_API_FDB_LEARN_EXCEED_CMD_GET, SW_MACCMD, \ - sizeof(fal_fwd_cmd_t), SW_PARAM_PTR|SW_PARAM_OUT, "cmd"), - -#define SW_API_FDB_RESV_ADD_DESC \ - SW_PARAM_DEF(SW_API_FDB_RESV_ADD, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"),\ - SW_PARAM_DEF(SW_API_FDB_RESV_ADD, SW_FDBENTRY, \ - sizeof(fal_fdb_entry_t), SW_PARAM_PTR|SW_PARAM_IN, "Fdb Resv Entry"), - -#define SW_API_FDB_RESV_DEL_DESC \ - SW_PARAM_DEF(SW_API_FDB_RESV_DEL, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"),\ - SW_PARAM_DEF(SW_API_FDB_RESV_DEL, SW_FDBENTRY, \ - sizeof(fal_fdb_entry_t), SW_PARAM_PTR|SW_PARAM_IN, "Fdb Resv Entry"), - -#define SW_API_FDB_RESV_FIND_DESC \ - SW_PARAM_DEF(SW_API_FDB_RESV_FIND, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"),\ - SW_PARAM_DEF(SW_API_FDB_RESV_FIND, SW_FDBENTRY, \ - sizeof(fal_fdb_entry_t), SW_PARAM_PTR|SW_PARAM_IN|SW_PARAM_OUT, \ - "Fdb Resv Entry"), - -#define SW_API_FDB_RESV_ITERATE_DESC \ - SW_PARAM_DEF(SW_API_FDB_RESV_ITERATE, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"),\ - SW_PARAM_DEF(SW_API_FDB_RESV_ITERATE, SW_UINT32, 4, \ - SW_PARAM_PTR|SW_PARAM_IN|SW_PARAM_OUT, "Iterator"),\ - SW_PARAM_DEF(SW_API_FDB_RESV_ITERATE, SW_FDBENTRY, \ - sizeof(fal_fdb_entry_t), SW_PARAM_PTR|SW_PARAM_OUT, "Fdb Resv Entry"), - -#define SW_API_FDB_PT_LEARN_STATIC_SET_DESC \ - SW_PARAM_DEF(SW_API_FDB_PT_LEARN_STATIC_SET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"),\ - SW_PARAM_DEF(SW_API_FDB_PT_LEARN_STATIC_SET, SW_UINT32, 4, SW_PARAM_IN, "Port ID"),\ - SW_PARAM_DEF(SW_API_FDB_PT_LEARN_STATIC_SET, SW_ENABLE, 4, SW_PARAM_IN, "LearnStatic"), - -#define SW_API_FDB_PT_LEARN_STATIC_GET_DESC \ - SW_PARAM_DEF(SW_API_FDB_PT_LEARN_STATIC_GET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"),\ - SW_PARAM_DEF(SW_API_FDB_PT_LEARN_STATIC_GET, SW_UINT32, 4, SW_PARAM_IN, "Port ID"),\ - SW_PARAM_DEF(SW_API_FDB_PT_LEARN_STATIC_GET, SW_ENABLE, 4, \ - SW_PARAM_PTR|SW_PARAM_OUT, "LearnStatic"), - -#define SW_API_FDB_PORT_ADD_DESC \ - SW_PARAM_DEF(SW_API_FDB_PORT_ADD, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"),\ - SW_PARAM_DEF(SW_API_FDB_PORT_ADD, SW_UINT32, 4, SW_PARAM_IN, "FID"),\ - SW_PARAM_DEF(SW_API_FDB_PORT_ADD, SW_MACADDR, \ - sizeof(fal_mac_addr_t), SW_PARAM_PTR|SW_PARAM_IN, "Address"),\ - SW_PARAM_DEF(SW_API_FDB_PORT_ADD, SW_UINT32, 4, SW_PARAM_IN, "Port ID"), - -#define SW_API_FDB_PORT_DEL_DESC \ - SW_PARAM_DEF(SW_API_FDB_PORT_DEL, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"),\ - SW_PARAM_DEF(SW_API_FDB_PORT_DEL, SW_UINT32, 4, SW_PARAM_IN, "FID"),\ - SW_PARAM_DEF(SW_API_FDB_PORT_DEL, SW_MACADDR, \ - sizeof(fal_mac_addr_t), SW_PARAM_PTR|SW_PARAM_IN, "Address"),\ - SW_PARAM_DEF(SW_API_FDB_PORT_DEL, SW_UINT32, 4, SW_PARAM_IN, "Port ID"), - -#define SW_API_FDB_PT_MACLIMIT_CTRL_SET_DESC \ - SW_PARAM_DEF(SW_API_FDB_PT_MACLIMIT_CTRL_SET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"),\ - SW_PARAM_DEF(SW_API_FDB_PT_MACLIMIT_CTRL_SET, SW_UINT32, 4, SW_PARAM_IN, "Port ID"),\ - SW_PARAM_DEF(SW_API_FDB_PT_MACLIMIT_CTRL_SET, SW_MACLIMIT_CTRL, \ - sizeof(fal_maclimit_ctrl_t), SW_PARAM_PTR|SW_PARAM_IN, "MacLimit Ctrl"), - -#define SW_API_FDB_PT_MACLIMIT_CTRL_GET_DESC \ - SW_PARAM_DEF(SW_API_FDB_PT_MACLIMIT_CTRL_GET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"),\ - SW_PARAM_DEF(SW_API_FDB_PT_MACLIMIT_CTRL_GET, SW_UINT32, 4, SW_PARAM_IN, "Port ID"),\ - SW_PARAM_DEF(SW_API_FDB_PT_MACLIMIT_CTRL_GET, SW_MACLIMIT_CTRL, \ - sizeof(fal_maclimit_ctrl_t), SW_PARAM_PTR|SW_PARAM_OUT, "MacLimit Ctrl"), - -#define SW_API_FDB_DEL_BY_FID_DESC \ - SW_PARAM_DEF(SW_API_FDB_DEL_BY_FID, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"),\ - SW_PARAM_DEF(SW_API_FDB_DEL_BY_FID, SW_UINT16, 2, SW_PARAM_IN, "FID"),\ - SW_PARAM_DEF(SW_API_FDB_DEL_BY_FID, SW_UINT32, 4, SW_PARAM_IN, "Flag"), - - -#define SW_API_ACL_LIST_CREAT_DESC \ - SW_PARAM_DEF(SW_API_ACL_LIST_CREAT, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"),\ - SW_PARAM_DEF(SW_API_ACL_LIST_CREAT, SW_UINT32, 4, SW_PARAM_IN, "List ID"),\ - SW_PARAM_DEF(SW_API_ACL_LIST_CREAT, SW_UINT32, 4, SW_PARAM_IN, "List Priority"), - -#define SW_API_ACL_LIST_DESTROY_DESC \ - SW_PARAM_DEF(SW_API_ACL_LIST_DESTROY, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"),\ - SW_PARAM_DEF(SW_API_ACL_LIST_DESTROY, SW_UINT32, 4, SW_PARAM_IN, "List ID"), - -#define SW_API_ACL_RULE_ADD_DESC \ - SW_PARAM_DEF(SW_API_ACL_RULE_ADD, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"),\ - SW_PARAM_DEF(SW_API_ACL_RULE_ADD, SW_UINT32, 4, SW_PARAM_IN, "List ID"),\ - SW_PARAM_DEF(SW_API_ACL_RULE_ADD, SW_UINT32, 4, SW_PARAM_IN, "Rule ID"),\ - SW_PARAM_DEF(SW_API_ACL_RULE_ADD, SW_UINT32, 4, SW_PARAM_IN, "Rule Number"),\ - SW_PARAM_DEF(SW_API_ACL_RULE_ADD, SW_ACLRULE, \ - sizeof(fal_acl_rule_t), SW_PARAM_PTR|SW_PARAM_IN, "Rule"), - -#define SW_API_ACL_RULE_DELETE_DESC \ - SW_PARAM_DEF(SW_API_ACL_RULE_DELETE, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"),\ - SW_PARAM_DEF(SW_API_ACL_RULE_DELETE, SW_UINT32, 4, SW_PARAM_IN, "List ID"),\ - SW_PARAM_DEF(SW_API_ACL_RULE_DELETE, SW_UINT32, 4, SW_PARAM_IN, "Rule ID"),\ - SW_PARAM_DEF(SW_API_ACL_RULE_DELETE, SW_UINT32, 4, SW_PARAM_IN, "Rule Number"), - -#define SW_API_ACL_RULE_QUERY_DESC \ - SW_PARAM_DEF(SW_API_ACL_RULE_QUERY, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"),\ - SW_PARAM_DEF(SW_API_ACL_RULE_QUERY, SW_UINT32, 4, SW_PARAM_IN, "List ID"),\ - SW_PARAM_DEF(SW_API_ACL_RULE_QUERY, SW_UINT32, 4, SW_PARAM_IN, "Rule ID"),\ - SW_PARAM_DEF(SW_API_ACL_RULE_QUERY, SW_ACLRULE, \ - sizeof(fal_acl_rule_t), SW_PARAM_PTR|SW_PARAM_OUT, "Rule"), - -#define SW_API_ACL_LIST_BIND_DESC \ - SW_PARAM_DEF(SW_API_ACL_LIST_BIND, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"),\ - SW_PARAM_DEF(SW_API_ACL_LIST_BIND, SW_UINT32, 4, SW_PARAM_IN, "List ID"),\ - SW_PARAM_DEF(SW_API_ACL_LIST_BIND, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"),\ - SW_PARAM_DEF(SW_API_ACL_LIST_BIND, SW_UINT32, 4, SW_PARAM_IN, "List ID"),\ - SW_PARAM_DEF(SW_API_ACL_LIST_BIND, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), - -#define SW_API_ACL_LIST_UNBIND_DESC \ - SW_PARAM_DEF(SW_API_ACL_LIST_UNBIND, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"),\ - SW_PARAM_DEF(SW_API_ACL_LIST_UNBIND, SW_UINT32, 4, SW_PARAM_IN, "List ID"),\ - SW_PARAM_DEF(SW_API_ACL_LIST_UNBIND, SW_UINT32, 4, SW_PARAM_IN, "Direction"),\ - SW_PARAM_DEF(SW_API_ACL_LIST_UNBIND, SW_UINT32, 4, SW_PARAM_IN, "Object Type"),\ - SW_PARAM_DEF(SW_API_ACL_LIST_UNBIND, SW_UINT32, 4, SW_PARAM_IN, "Object Index"), - -#define SW_API_ACL_STATUS_SET_DESC \ - SW_PARAM_DEF(SW_API_ACL_STATUS_SET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"),\ - SW_PARAM_DEF(SW_API_ACL_STATUS_SET, SW_ENABLE, 4, SW_PARAM_IN, "Status"), - -#define SW_API_ACL_STATUS_GET_DESC \ - SW_PARAM_DEF(SW_API_ACL_STATUS_GET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"),\ - SW_PARAM_DEF(SW_API_ACL_STATUS_GET, SW_ENABLE, 4, SW_PARAM_PTR|SW_PARAM_OUT, "Status"), - -#define SW_API_ACL_LIST_DUMP_DESC \ - SW_PARAM_DEF(SW_API_ACL_LIST_DUMP, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), - -#define SW_API_ACL_RULE_DUMP_DESC \ - SW_PARAM_DEF(SW_API_ACL_RULE_DUMP, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), - -#define SW_API_ACL_PT_UDF_PROFILE_SET_DESC \ - SW_PARAM_DEF(SW_API_ACL_PT_UDF_PROFILE_SET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"),\ - SW_PARAM_DEF(SW_API_ACL_PT_UDF_PROFILE_SET, SW_UINT32, 4, SW_PARAM_IN, "Port ID"),\ - SW_PARAM_DEF(SW_API_ACL_PT_UDF_PROFILE_SET, SW_ACL_UDF_TYPE, \ - sizeof(fal_acl_udf_type_t), SW_PARAM_IN, "udf_type"),\ - SW_PARAM_DEF(SW_API_ACL_PT_UDF_PROFILE_SET, SW_UINT32, 4, SW_PARAM_IN, "udf_offset"),\ - SW_PARAM_DEF(SW_API_ACL_PT_UDF_PROFILE_SET, SW_UINT32, 4, SW_PARAM_IN, "udf_length"), - -#define SW_API_ACL_PT_UDF_PROFILE_GET_DESC \ - SW_PARAM_DEF(SW_API_ACL_PT_UDF_PROFILE_GET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"),\ - SW_PARAM_DEF(SW_API_ACL_PT_UDF_PROFILE_GET, SW_UINT32, 4, SW_PARAM_IN, "Port ID"),\ - SW_PARAM_DEF(SW_API_ACL_PT_UDF_PROFILE_GET, SW_ACL_UDF_TYPE, \ - sizeof(fal_acl_udf_type_t), SW_PARAM_IN, "udf_type"),\ - SW_PARAM_DEF(SW_API_ACL_PT_UDF_PROFILE_GET, SW_UINT32, 4, \ - SW_PARAM_PTR|SW_PARAM_OUT, "udf_offset"),\ - SW_PARAM_DEF(SW_API_ACL_PT_UDF_PROFILE_GET, SW_UINT32, 4, \ - SW_PARAM_PTR|SW_PARAM_OUT, "udf_length"), - -#define SW_API_ACL_RULE_ACTIVE_DESC \ - SW_PARAM_DEF(SW_API_ACL_RULE_ACTIVE, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"),\ - SW_PARAM_DEF(SW_API_ACL_RULE_ACTIVE, SW_UINT32, 4, SW_PARAM_IN, "List ID"),\ - SW_PARAM_DEF(SW_API_ACL_RULE_ACTIVE, SW_UINT32, 4, SW_PARAM_IN, "Rule ID"),\ - SW_PARAM_DEF(SW_API_ACL_RULE_ACTIVE, SW_UINT32, 4, SW_PARAM_IN, "Rule Number"), - -#define SW_API_ACL_RULE_DEACTIVE_DESC \ - SW_PARAM_DEF(SW_API_ACL_RULE_DEACTIVE, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"),\ - SW_PARAM_DEF(SW_API_ACL_RULE_DEACTIVE, SW_UINT32, 4, SW_PARAM_IN, "List ID"),\ - SW_PARAM_DEF(SW_API_ACL_RULE_DEACTIVE, SW_UINT32, 4, SW_PARAM_IN, "Rule ID"),\ - SW_PARAM_DEF(SW_API_ACL_RULE_DEACTIVE, SW_UINT32, 4, SW_PARAM_IN, "Rule Number"), - -#define SW_API_ACL_RULE_SRC_FILTER_STS_SET_DESC \ - SW_PARAM_DEF(SW_API_ACL_RULE_SRC_FILTER_STS_SET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"),\ - SW_PARAM_DEF(SW_API_ACL_RULE_SRC_FILTER_STS_SET, SW_UINT32, 4, SW_PARAM_IN, "Rule ID"),\ - SW_PARAM_DEF(SW_API_ACL_RULE_SRC_FILTER_STS_SET, SW_ENABLE, 4, SW_PARAM_IN, "Enable"), - -#define SW_API_ACL_RULE_SRC_FILTER_STS_GET_DESC \ - SW_PARAM_DEF(SW_API_ACL_RULE_SRC_FILTER_STS_GET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"),\ - SW_PARAM_DEF(SW_API_ACL_RULE_SRC_FILTER_STS_GET, SW_UINT32, 4, SW_PARAM_IN, "Rule ID"),\ - SW_PARAM_DEF(SW_API_ACL_RULE_SRC_FILTER_STS_GET, SW_ENABLE, 4, \ - SW_PARAM_PTR|SW_PARAM_OUT, "Enable"), - -#define SW_API_ACL_UDF_SET_DESC \ - SW_PARAM_DEF(SW_API_ACL_UDF_SET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"),\ - SW_PARAM_DEF(SW_API_ACL_UDF_SET, SW_ACL_UDF_PKT_TYPE, \ - sizeof(fal_acl_udf_pkt_type_t), SW_PARAM_IN, "udf_packet_type"),\ - SW_PARAM_DEF(SW_API_ACL_UDF_SET, SW_UINT32, 4, SW_PARAM_IN, "udf_index"),\ - SW_PARAM_DEF(SW_API_ACL_UDF_SET, SW_ACL_UDF_TYPE, \ - sizeof(fal_acl_udf_type_t), SW_PARAM_IN, "udf_type"),\ - SW_PARAM_DEF(SW_API_ACL_UDF_SET, SW_UINT32, 4, SW_PARAM_IN, "udf_offset"), - -#define SW_API_ACL_UDF_GET_DESC \ - SW_PARAM_DEF(SW_API_ACL_UDF_GET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"),\ - SW_PARAM_DEF(SW_API_ACL_UDF_GET, SW_ACL_UDF_PKT_TYPE, \ - sizeof(fal_acl_udf_pkt_type_t), SW_PARAM_IN, "udf_packet_type"),\ - SW_PARAM_DEF(SW_API_ACL_UDF_GET, SW_UINT32, 4, SW_PARAM_IN, "udf_index"),\ - SW_PARAM_DEF(SW_API_ACL_UDF_GET, SW_ACL_UDF_TYPE, \ - sizeof(fal_acl_udf_type_t), SW_PARAM_PTR|SW_PARAM_OUT, "udf_type"),\ - SW_PARAM_DEF(SW_API_ACL_UDF_GET, SW_UINT32, 4, SW_PARAM_PTR|SW_PARAM_OUT, "udf_offset"), - -#define SW_API_QOS_SCH_MODE_SET_DESC \ - SW_PARAM_DEF(SW_API_QOS_SCH_MODE_SET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"),\ - SW_PARAM_DEF(SW_API_QOS_SCH_MODE_SET, SW_SCH, \ - sizeof(fal_sch_mode_t), SW_PARAM_IN, "Schedule mode"),\ - SW_PARAM_DEF(SW_API_QOS_SCH_MODE_SET, SW_UINT_A, 16, SW_PARAM_PTR|SW_PARAM_IN, "Weight"), - -#define SW_API_QOS_SCH_MODE_GET_DESC \ - SW_PARAM_DEF(SW_API_QOS_SCH_MODE_GET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"),\ - SW_PARAM_DEF(SW_API_QOS_SCH_MODE_GET, SW_SCH, \ - sizeof(fal_sch_mode_t), SW_PARAM_PTR|SW_PARAM_OUT, "Schedule mode"),\ - SW_PARAM_DEF(SW_API_QOS_SCH_MODE_GET, SW_UINT_A, 16, SW_PARAM_PTR|SW_PARAM_OUT, "Weight"), - -#define SW_API_QOS_QU_TX_BUF_ST_SET_DESC \ - SW_PARAM_DEF(SW_API_QOS_QU_TX_BUF_ST_SET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"),\ - SW_PARAM_DEF(SW_API_QOS_QU_TX_BUF_ST_SET, SW_UINT32, 4, SW_PARAM_IN, "Port ID"),\ - SW_PARAM_DEF(SW_API_QOS_QU_TX_BUF_ST_SET, SW_ENABLE, 4, SW_PARAM_IN, "Buffer limit"), - -#define SW_API_QOS_QU_TX_BUF_ST_GET_DESC \ - SW_PARAM_DEF(SW_API_QOS_QU_TX_BUF_ST_GET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"),\ - SW_PARAM_DEF(SW_API_QOS_QU_TX_BUF_ST_GET, SW_UINT32, 4, SW_PARAM_IN, "Port ID"),\ - SW_PARAM_DEF(SW_API_QOS_QU_TX_BUF_ST_GET, SW_ENABLE, 4, \ - SW_PARAM_PTR|SW_PARAM_OUT, "Buffer limit"), - -#define SW_API_QOS_QU_TX_BUF_NR_SET_DESC \ - SW_PARAM_DEF(SW_API_QOS_QU_TX_BUF_NR_SET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"),\ - SW_PARAM_DEF(SW_API_QOS_QU_TX_BUF_NR_SET, SW_UINT32, 4, SW_PARAM_IN, "Port ID"),\ - SW_PARAM_DEF(SW_API_QOS_QU_TX_BUF_NR_SET, SW_UINT32, 4, SW_PARAM_IN, "Queue ID"),\ - SW_PARAM_DEF(SW_API_QOS_QU_TX_BUF_NR_SET, SW_UINT32, 4, \ - SW_PARAM_PTR|SW_PARAM_IN|SW_PARAM_OUT, "Buffer Number"), - -#define SW_API_QOS_QU_TX_BUF_NR_GET_DESC \ - SW_PARAM_DEF(SW_API_QOS_QU_TX_BUF_NR_GET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"),\ - SW_PARAM_DEF(SW_API_QOS_QU_TX_BUF_NR_GET, SW_UINT32, 4, SW_PARAM_IN, "Port ID"),\ - SW_PARAM_DEF(SW_API_QOS_QU_TX_BUF_NR_GET, SW_UINT32, 4, SW_PARAM_IN, "Queue ID"),\ - SW_PARAM_DEF(SW_API_QOS_QU_TX_BUF_NR_GET, SW_UINT32, 4, \ - SW_PARAM_PTR|SW_PARAM_OUT, "Buffer Number"), - -#define SW_API_QOS_PT_TX_BUF_ST_SET_DESC \ - SW_PARAM_DEF(SW_API_QOS_PT_TX_BUF_ST_SET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"),\ - SW_PARAM_DEF(SW_API_QOS_PT_TX_BUF_ST_SET, SW_UINT32, 4, SW_PARAM_IN, "Port ID"),\ - SW_PARAM_DEF(SW_API_QOS_PT_TX_BUF_ST_SET, SW_ENABLE, 4, SW_PARAM_IN, "Buffer limit"), - -#define SW_API_QOS_PT_TX_BUF_ST_GET_DESC \ - SW_PARAM_DEF(SW_API_QOS_PT_TX_BUF_ST_GET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"),\ - SW_PARAM_DEF(SW_API_QOS_PT_TX_BUF_ST_GET, SW_UINT32, 4, SW_PARAM_IN, "Port ID"),\ - SW_PARAM_DEF(SW_API_QOS_PT_TX_BUF_ST_GET, SW_ENABLE, 4, \ - SW_PARAM_PTR|SW_PARAM_OUT, "Buffer limit"), - -#define SW_API_QOS_PT_RED_EN_SET_DESC \ - SW_PARAM_DEF(SW_API_QOS_PT_RED_EN_SET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"),\ - SW_PARAM_DEF(SW_API_QOS_PT_RED_EN_SET, SW_UINT32, 4, SW_PARAM_IN, "Port ID"),\ - SW_PARAM_DEF(SW_API_QOS_PT_RED_EN_SET, SW_ENABLE, 4, SW_PARAM_IN, "enable"), - -#define SW_API_QOS_PT_RED_EN_GET_DESC \ - SW_PARAM_DEF(SW_API_QOS_PT_RED_EN_GET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"),\ - SW_PARAM_DEF(SW_API_QOS_PT_RED_EN_GET, SW_UINT32, 4, SW_PARAM_IN, "Port ID"),\ - SW_PARAM_DEF(SW_API_QOS_PT_RED_EN_GET, SW_ENABLE, 4, SW_PARAM_PTR|SW_PARAM_OUT, "enable"), - -#define SW_API_QOS_PT_TX_BUF_NR_SET_DESC \ - SW_PARAM_DEF(SW_API_QOS_PT_TX_BUF_NR_SET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"),\ - SW_PARAM_DEF(SW_API_QOS_PT_TX_BUF_NR_SET, SW_UINT32, 4, SW_PARAM_IN, "Port ID"),\ - SW_PARAM_DEF(SW_API_QOS_PT_TX_BUF_NR_SET, SW_UINT32, 4, \ - SW_PARAM_PTR|SW_PARAM_IN|SW_PARAM_OUT, "Buffer Number"), - -#define SW_API_QOS_PT_TX_BUF_NR_GET_DESC \ - SW_PARAM_DEF(SW_API_QOS_PT_TX_BUF_NR_GET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"),\ - SW_PARAM_DEF(SW_API_QOS_PT_TX_BUF_NR_GET, SW_UINT32, 4, SW_PARAM_IN, "Port ID"),\ - SW_PARAM_DEF(SW_API_QOS_PT_TX_BUF_NR_GET, SW_UINT32, 4, \ - SW_PARAM_PTR|SW_PARAM_OUT, "Buffer Number"), - -#define SW_API_QOS_PT_RX_BUF_NR_SET_DESC \ - SW_PARAM_DEF(SW_API_QOS_PT_RX_BUF_NR_SET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"),\ - SW_PARAM_DEF(SW_API_QOS_PT_RX_BUF_NR_SET, SW_UINT32, 4, SW_PARAM_IN, "Port ID"),\ - SW_PARAM_DEF(SW_API_QOS_PT_RX_BUF_NR_SET, SW_UINT32, 4, \ - SW_PARAM_PTR|SW_PARAM_IN|SW_PARAM_OUT, "Buffer Number"), - -#define SW_API_QOS_PT_RX_BUF_NR_GET_DESC \ - SW_PARAM_DEF(SW_API_QOS_PT_RX_BUF_NR_GET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"),\ - SW_PARAM_DEF(SW_API_QOS_PT_RX_BUF_NR_GET, SW_UINT32, 4, SW_PARAM_IN, "Port ID"),\ - SW_PARAM_DEF(SW_API_QOS_PT_RX_BUF_NR_GET, SW_UINT32, 4, \ - SW_PARAM_PTR|SW_PARAM_OUT, "Buffer Number"), - -#define SW_API_QOS_PORT_GROUP_SET_DESC \ - SW_PARAM_DEF(SW_API_QOS_PORT_GROUP_SET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"),\ - SW_PARAM_DEF(SW_API_QOS_PORT_GROUP_SET, SW_UINT32, 4, SW_PARAM_IN, "Port ID"),\ - SW_PARAM_DEF(SW_API_QOS_PORT_GROUP_SET, SW_PORTGROUP, \ - sizeof(fal_qos_group_t), SW_PARAM_PTR|SW_PARAM_IN, "PortGroup"), - -#define SW_API_QOS_PORT_GROUP_GET_DESC \ - SW_PARAM_DEF(SW_API_QOS_PORT_GROUP_GET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"),\ - SW_PARAM_DEF(SW_API_QOS_PORT_GROUP_GET, SW_UINT32, 4, SW_PARAM_IN, "Port ID"),\ - SW_PARAM_DEF(SW_API_QOS_PORT_GROUP_GET, SW_PORTGROUP, \ - sizeof(fal_qos_group_t), SW_PARAM_PTR|SW_PARAM_OUT, "PortGroup"), - -#define SW_API_QOS_PORT_PRI_SET_DESC \ - SW_PARAM_DEF(SW_API_QOS_PORT_PRI_SET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"),\ - SW_PARAM_DEF(SW_API_QOS_PORT_PRI_SET, SW_UINT32, 4, SW_PARAM_IN, "Port ID"),\ - SW_PARAM_DEF(SW_API_QOS_PORT_PRI_SET, SW_PORTPRI, \ - sizeof(fal_qos_pri_precedence_t), SW_PARAM_PTR|SW_PARAM_IN, "PortPri"), - -#define SW_API_QOS_PORT_PRI_GET_DESC \ - SW_PARAM_DEF(SW_API_QOS_PORT_PRI_GET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"),\ - SW_PARAM_DEF(SW_API_QOS_PORT_PRI_GET, SW_UINT32, 4, SW_PARAM_IN, "Port ID"),\ - SW_PARAM_DEF(SW_API_QOS_PORT_PRI_GET, SW_PORTPRI, \ - sizeof(fal_qos_pri_precedence_t), SW_PARAM_PTR|SW_PARAM_OUT, "PortPri"), - -#define SW_API_QOS_PORT_REMARK_SET_DESC \ - SW_PARAM_DEF(SW_API_QOS_PORT_REMARK_SET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"),\ - SW_PARAM_DEF(SW_API_QOS_PORT_REMARK_SET, SW_UINT32, 4, SW_PARAM_IN, "Port ID"),\ - SW_PARAM_DEF(SW_API_QOS_PORT_REMARK_SET, SW_PORTREMARK, \ - sizeof(fal_qos_remark_enable_t), SW_PARAM_PTR|SW_PARAM_IN, "PortRemark"), - -#define SW_API_QOS_PORT_REMARK_GET_DESC \ - SW_PARAM_DEF(SW_API_QOS_PORT_REMARK_GET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"),\ - SW_PARAM_DEF(SW_API_QOS_PORT_REMARK_GET, SW_UINT32, 4, SW_PARAM_IN, "Port ID"),\ - SW_PARAM_DEF(SW_API_QOS_PORT_REMARK_GET, SW_PORTREMARK, \ - sizeof(fal_qos_remark_enable_t), SW_PARAM_PTR|SW_PARAM_OUT, "PortRemark"), - -#define SW_API_QOS_PCP_MAP_SET_DESC \ - SW_PARAM_DEF(SW_API_QOS_PCP_MAP_SET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"),\ - SW_PARAM_DEF(SW_API_QOS_PCP_MAP_SET, SW_UINT32, 4, SW_PARAM_IN, "Group ID"),\ - SW_PARAM_DEF(SW_API_QOS_PCP_MAP_SET, SW_UINT32, 4, SW_PARAM_IN, "PCP"),\ - SW_PARAM_DEF(SW_API_QOS_PCP_MAP_SET, SW_COSMAP, \ - sizeof(fal_qos_cosmap_t), SW_PARAM_PTR|SW_PARAM_IN, "Cosmap"), - -#define SW_API_QOS_PCP_MAP_GET_DESC \ - SW_PARAM_DEF(SW_API_QOS_PCP_MAP_GET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"),\ - SW_PARAM_DEF(SW_API_QOS_PCP_MAP_GET, SW_UINT32, 4, SW_PARAM_IN, "Group ID"),\ - SW_PARAM_DEF(SW_API_QOS_PCP_MAP_GET, SW_UINT32, 4, SW_PARAM_IN, "PCP"),\ - SW_PARAM_DEF(SW_API_QOS_PCP_MAP_GET, SW_COSMAP, \ - sizeof(fal_qos_cosmap_t), SW_PARAM_PTR|SW_PARAM_OUT, "Cosmap"), - -#define SW_API_QOS_FLOW_MAP_SET_DESC \ - SW_PARAM_DEF(SW_API_QOS_FLOW_MAP_SET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"),\ - SW_PARAM_DEF(SW_API_QOS_FLOW_MAP_SET, SW_UINT32, 4, SW_PARAM_IN, "Group ID"),\ - SW_PARAM_DEF(SW_API_QOS_FLOW_MAP_SET, SW_UINT32, 4, SW_PARAM_IN, "Flow"),\ - SW_PARAM_DEF(SW_API_QOS_FLOW_MAP_SET, SW_COSMAP, \ - sizeof(fal_qos_cosmap_t), SW_PARAM_PTR|SW_PARAM_IN, "Cosmap"), - -#define SW_API_QOS_FLOW_MAP_GET_DESC \ - SW_PARAM_DEF(SW_API_QOS_FLOW_MAP_GET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"),\ - SW_PARAM_DEF(SW_API_QOS_FLOW_MAP_GET, SW_UINT32, 4, SW_PARAM_IN, "Group ID"),\ - SW_PARAM_DEF(SW_API_QOS_FLOW_MAP_GET, SW_UINT32, 4, SW_PARAM_IN, "Flow"),\ - SW_PARAM_DEF(SW_API_QOS_FLOW_MAP_GET, SW_COSMAP, \ - sizeof(fal_qos_cosmap_t), SW_PARAM_PTR|SW_PARAM_OUT, "Cosmap"), - -#define SW_API_QOS_DSCP_MAP_SET_DESC \ - SW_PARAM_DEF(SW_API_QOS_DSCP_MAP_SET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"),\ - SW_PARAM_DEF(SW_API_QOS_DSCP_MAP_SET, SW_UINT32, 4, SW_PARAM_IN, "Group ID"),\ - SW_PARAM_DEF(SW_API_QOS_DSCP_MAP_SET, SW_UINT32, 4, SW_PARAM_IN, "Dscp"),\ - SW_PARAM_DEF(SW_API_QOS_DSCP_MAP_SET, SW_COSMAP, \ - sizeof(fal_qos_cosmap_t), SW_PARAM_PTR|SW_PARAM_IN, "Cosmap"), - -#define SW_API_QOS_DSCP_MAP_GET_DESC \ - SW_PARAM_DEF(SW_API_QOS_DSCP_MAP_GET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"),\ - SW_PARAM_DEF(SW_API_QOS_DSCP_MAP_GET, SW_UINT32, 4, SW_PARAM_IN, "Group ID"),\ - SW_PARAM_DEF(SW_API_QOS_DSCP_MAP_GET, SW_UINT32, 4, SW_PARAM_IN, "Dscp"),\ - SW_PARAM_DEF(SW_API_QOS_DSCP_MAP_GET, SW_COSMAP, \ - sizeof(fal_qos_cosmap_t), SW_PARAM_PTR|SW_PARAM_OUT, "Cosmap"), - -#define SW_API_QOS_QUEUE_SCHEDULER_SET_DESC \ - SW_PARAM_DEF(SW_API_QOS_QUEUE_SCHEDULER_SET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"),\ - SW_PARAM_DEF(SW_API_QOS_QUEUE_SCHEDULER_SET, SW_UINT32, 4, SW_PARAM_IN, "Node ID"),\ - SW_PARAM_DEF(SW_API_QOS_QUEUE_SCHEDULER_SET, SW_UINT32, 4, SW_PARAM_IN, "Level"),\ - SW_PARAM_DEF(SW_API_QOS_QUEUE_SCHEDULER_SET, SW_UINT32, 4, SW_PARAM_IN, "Port ID"),\ - SW_PARAM_DEF(SW_API_QOS_QUEUE_SCHEDULER_SET, SW_SCHEDULER, \ - sizeof(fal_qos_scheduler_cfg_t), SW_PARAM_PTR|SW_PARAM_IN, "Scheduler"), - -#define SW_API_QOS_QUEUE_SCHEDULER_GET_DESC \ - SW_PARAM_DEF(SW_API_QOS_QUEUE_SCHEDULER_GET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"),\ - SW_PARAM_DEF(SW_API_QOS_QUEUE_SCHEDULER_GET, SW_UINT32, 4, SW_PARAM_IN, "Node ID"),\ - SW_PARAM_DEF(SW_API_QOS_QUEUE_SCHEDULER_GET, SW_UINT32, 4, SW_PARAM_IN, "Level"),\ - SW_PARAM_DEF(SW_API_QOS_QUEUE_SCHEDULER_GET, SW_UINT32, 4, \ - SW_PARAM_PTR|SW_PARAM_OUT, "Port ID"),\ - SW_PARAM_DEF(SW_API_QOS_QUEUE_SCHEDULER_GET, SW_SCHEDULER, \ - sizeof(fal_qos_scheduler_cfg_t), SW_PARAM_PTR|SW_PARAM_OUT, "Scheduler"), - -#define SW_API_QOS_RING_QUEUE_MAP_SET_DESC \ - SW_PARAM_DEF(SW_API_QOS_RING_QUEUE_MAP_SET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"),\ - SW_PARAM_DEF(SW_API_QOS_RING_QUEUE_MAP_SET, SW_UINT32, 4, SW_PARAM_IN, "Ring ID"),\ - SW_PARAM_DEF(SW_API_QOS_RING_QUEUE_MAP_SET, SW_QUEUEBMP, \ - sizeof(fal_queue_bmp_t), SW_PARAM_PTR|SW_PARAM_IN, "Queue bmp"), - -#define SW_API_QOS_RING_QUEUE_MAP_GET_DESC \ - SW_PARAM_DEF(SW_API_QOS_RING_QUEUE_MAP_GET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"),\ - SW_PARAM_DEF(SW_API_QOS_RING_QUEUE_MAP_GET, SW_UINT32, 4, SW_PARAM_IN, "Ring ID"),\ - SW_PARAM_DEF(SW_API_QOS_RING_QUEUE_MAP_GET, SW_QUEUEBMP, \ - sizeof(fal_queue_bmp_t), SW_PARAM_PTR|SW_PARAM_OUT, "Queue bmp"), - -#define SW_API_QOS_PORT_SCHEDULER_CFG_RESET_DESC \ - SW_PARAM_DEF(SW_API_QOS_PORT_SCHEDULER_CFG_RESET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"),\ - SW_PARAM_DEF(SW_API_QOS_PORT_SCHEDULER_CFG_RESET, SW_UINT32, 4, SW_PARAM_IN, "Port ID"), - -#define SW_API_QOS_RING_QUEUE_MAP_GET_DESC \ - SW_PARAM_DEF(SW_API_QOS_RING_QUEUE_MAP_GET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"),\ - SW_PARAM_DEF(SW_API_QOS_RING_QUEUE_MAP_GET, SW_UINT32, 4, SW_PARAM_IN, "Ring ID"),\ - SW_PARAM_DEF(SW_API_QOS_RING_QUEUE_MAP_GET, SW_QUEUEBMP, \ - sizeof(fal_queue_bmp_t), SW_PARAM_PTR|SW_PARAM_OUT, "Queue bmp"), - -#define SW_API_QOS_PORT_QUEUES_GET_DESC \ - SW_PARAM_DEF(SW_API_QOS_PORT_QUEUES_GET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"),\ - SW_PARAM_DEF(SW_API_QOS_PORT_QUEUES_GET, SW_UINT32, 4, SW_PARAM_IN, "Port ID"),\ - SW_PARAM_DEF(SW_API_QOS_PORT_QUEUES_GET, SW_QUEUEBMP, \ - sizeof(fal_queue_bmp_t), SW_PARAM_PTR|SW_PARAM_OUT, "Queue bmp"), - -#define SW_API_QOS_SCHEDULER_DEQUEU_CTRL_SET_DESC \ - SW_PARAM_DEF(SW_API_QOS_SCHEDULER_DEQUEU_CTRL_SET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \ - SW_PARAM_DEF(SW_API_QOS_SCHEDULER_DEQUEU_CTRL_SET, SW_UINT32, 4, SW_PARAM_IN, "queue ID"), \ - SW_PARAM_DEF(SW_API_QOS_SCHEDULER_DEQUEU_CTRL_SET, SW_ENABLE, \ - sizeof(a_bool_t), SW_PARAM_IN, "dequeue en"), - -#define SW_API_QOS_SCHEDULER_DEQUEU_CTRL_GET_DESC \ - SW_PARAM_DEF(SW_API_QOS_SCHEDULER_DEQUEU_CTRL_GET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \ - SW_PARAM_DEF(SW_API_QOS_SCHEDULER_DEQUEU_CTRL_GET, SW_UINT32, 4, SW_PARAM_IN, "queue ID"), \ - SW_PARAM_DEF(SW_API_QOS_SCHEDULER_DEQUEU_CTRL_GET, SW_ENABLE, \ - sizeof(a_bool_t), SW_PARAM_PTR|SW_PARAM_OUT, "dequeue en"), - -#define SW_API_QOS_PORT_SCHEDULER_RESOURCE_GET_DESC \ - SW_PARAM_DEF(SW_API_QOS_PORT_SCHEDULER_RESOURCE_GET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \ - SW_PARAM_DEF(SW_API_QOS_PORT_SCHEDULER_RESOURCE_GET, SW_UINT32, 4, SW_PARAM_IN, "Port ID"), \ - SW_PARAM_DEF(SW_API_QOS_PORT_SCHEDULER_RESOURCE_GET, SW_RESOURCE_SCHE, \ - sizeof(fal_portscheduler_resource_t), SW_PARAM_PTR|SW_PARAM_OUT, \ - "scheduler resource"), - -#define SW_API_COSMAP_UP_QU_SET_DESC \ - SW_PARAM_DEF(SW_API_COSMAP_UP_QU_SET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"),\ - SW_PARAM_DEF(SW_API_COSMAP_UP_QU_SET, SW_UINT32, 4, SW_PARAM_IN, "Dot1p"),\ - SW_PARAM_DEF(SW_API_COSMAP_UP_QU_SET, SW_UINT32, 4, SW_PARAM_IN, "Queue"), - -#define SW_API_COSMAP_UP_QU_GET_DESC \ - SW_PARAM_DEF(SW_API_COSMAP_UP_QU_GET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"),\ - SW_PARAM_DEF(SW_API_COSMAP_UP_QU_GET, SW_UINT32, 4, SW_PARAM_IN, "Dot1p"),\ - SW_PARAM_DEF(SW_API_COSMAP_UP_QU_GET, SW_UINT32, 4, SW_PARAM_PTR|SW_PARAM_OUT, "Queue"), - -#define SW_API_COSMAP_DSCP_QU_SET_DESC \ - SW_PARAM_DEF(SW_API_COSMAP_DSCP_QU_SET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"),\ - SW_PARAM_DEF(SW_API_COSMAP_DSCP_QU_SET, SW_UINT32, 4, SW_PARAM_IN, "DSCP"),\ - SW_PARAM_DEF(SW_API_COSMAP_DSCP_QU_SET, SW_UINT32, 4, SW_PARAM_IN, "Queue"), - -#define SW_API_COSMAP_DSCP_QU_GET_DESC \ - SW_PARAM_DEF(SW_API_COSMAP_DSCP_QU_GET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"),\ - SW_PARAM_DEF(SW_API_COSMAP_DSCP_QU_GET, SW_UINT32, 4, SW_PARAM_IN, "DSCP"),\ - SW_PARAM_DEF(SW_API_COSMAP_DSCP_QU_GET, SW_UINT32, 4, SW_PARAM_PTR|SW_PARAM_OUT, "Queue"), - -#define SW_API_QOS_PT_MODE_SET_DESC \ - SW_PARAM_DEF(SW_API_QOS_PT_MODE_SET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"),\ - SW_PARAM_DEF(SW_API_QOS_PT_MODE_SET, SW_UINT32, 4, SW_PARAM_IN, "Port ID"),\ - SW_PARAM_DEF(SW_API_QOS_PT_MODE_SET, SW_QOS, \ - sizeof(fal_qos_mode_t), SW_PARAM_IN, "Qos mode"),\ - SW_PARAM_DEF(SW_API_QOS_PT_MODE_SET, SW_ENABLE, 4, SW_PARAM_IN, "Enable"), - -#define SW_API_QOS_PT_MODE_GET_DESC \ - SW_PARAM_DEF(SW_API_QOS_PT_MODE_GET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"),\ - SW_PARAM_DEF(SW_API_QOS_PT_MODE_GET, SW_UINT32, 4, SW_PARAM_IN, "Port ID"),\ - SW_PARAM_DEF(SW_API_QOS_PT_MODE_GET, SW_QOS, \ - sizeof(fal_qos_mode_t), SW_PARAM_IN, "Qos mode"),\ - SW_PARAM_DEF(SW_API_QOS_PT_MODE_GET, SW_ENABLE, 4, SW_PARAM_PTR|SW_PARAM_OUT, "Enable"), - -#define SW_API_QOS_PT_MODE_PRI_SET_DESC \ - SW_PARAM_DEF(SW_API_QOS_PT_MODE_PRI_SET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"),\ - SW_PARAM_DEF(SW_API_QOS_PT_MODE_PRI_SET, SW_UINT32, 4, SW_PARAM_IN, "Port ID"),\ - SW_PARAM_DEF(SW_API_QOS_PT_MODE_PRI_SET, SW_QOS, \ - sizeof(fal_qos_mode_t), SW_PARAM_IN, "Qos mode"),\ - SW_PARAM_DEF(SW_API_QOS_PT_MODE_PRI_SET, SW_UINT32, 4, SW_PARAM_IN, "Priority"), - -#define SW_API_QOS_PT_MODE_PRI_GET_DESC \ - SW_PARAM_DEF(SW_API_QOS_PT_MODE_PRI_GET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"),\ - SW_PARAM_DEF(SW_API_QOS_PT_MODE_PRI_GET, SW_UINT32, 4, SW_PARAM_IN, "Port ID"),\ - SW_PARAM_DEF(SW_API_QOS_PT_MODE_PRI_GET, SW_QOS, \ - sizeof(fal_qos_mode_t), SW_PARAM_IN, "Qos mode"),\ - SW_PARAM_DEF(SW_API_QOS_PT_MODE_PRI_GET, SW_UINT32, 4, SW_PARAM_PTR|SW_PARAM_OUT, "Priority"), - -#define SW_API_QOS_PORT_DEF_UP_SET_DESC \ - SW_PARAM_DEF(SW_API_QOS_PORT_DEF_UP_SET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"),\ - SW_PARAM_DEF(SW_API_QOS_PORT_DEF_UP_SET, SW_UINT32, 4, SW_PARAM_IN, "Port ID"),\ - SW_PARAM_DEF(SW_API_QOS_PORT_DEF_UP_SET, SW_UINT32, 4, SW_PARAM_IN, "default up"), - -#define SW_API_QOS_PORT_DEF_UP_GET_DESC \ - SW_PARAM_DEF(SW_API_QOS_PORT_DEF_UP_GET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"),\ - SW_PARAM_DEF(SW_API_QOS_PORT_DEF_UP_GET, SW_UINT32, 4, SW_PARAM_IN, "Port ID"),\ - SW_PARAM_DEF(SW_API_QOS_PORT_DEF_UP_GET, SW_UINT32, 4, SW_PARAM_PTR|SW_PARAM_OUT, "default up"), - -#define SW_API_QOS_PORT_SCH_MODE_SET_DESC \ - SW_PARAM_DEF(SW_API_QOS_PORT_SCH_MODE_SET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"),\ - SW_PARAM_DEF(SW_API_QOS_PORT_SCH_MODE_SET, SW_UINT32, 4, SW_PARAM_IN, "Port ID"),\ - SW_PARAM_DEF(SW_API_QOS_PORT_SCH_MODE_SET, SW_SCH, \ - sizeof(fal_sch_mode_t), SW_PARAM_IN, "Schedule mode"),\ - SW_PARAM_DEF(SW_API_QOS_PORT_SCH_MODE_SET, SW_UINT_A, 24, SW_PARAM_PTR|SW_PARAM_IN, "Weight"), - -#define SW_API_QOS_PORT_SCH_MODE_GET_DESC \ - SW_PARAM_DEF(SW_API_QOS_PORT_SCH_MODE_GET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"),\ - SW_PARAM_DEF(SW_API_QOS_PORT_SCH_MODE_GET, SW_UINT32, 4, SW_PARAM_IN, "Port ID"),\ - SW_PARAM_DEF(SW_API_QOS_PORT_SCH_MODE_GET, SW_SCH, \ - sizeof(fal_sch_mode_t), SW_PARAM_PTR|SW_PARAM_OUT, "Schedule mode"),\ - SW_PARAM_DEF(SW_API_QOS_PORT_SCH_MODE_GET, SW_UINT_A, 24, SW_PARAM_PTR|SW_PARAM_OUT, "Weight"), - -#define SW_API_QOS_PT_DEF_SPRI_SET_DESC \ - SW_PARAM_DEF(SW_API_QOS_PT_DEF_SPRI_SET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"),\ - SW_PARAM_DEF(SW_API_QOS_PT_DEF_SPRI_SET, SW_UINT32, 4, SW_PARAM_IN, "Port ID"),\ - SW_PARAM_DEF(SW_API_QOS_PT_DEF_SPRI_SET, SW_UINT32, 4, SW_PARAM_IN, "default spri"), - -#define SW_API_QOS_PT_DEF_SPRI_GET_DESC \ - SW_PARAM_DEF(SW_API_QOS_PT_DEF_SPRI_GET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"),\ - SW_PARAM_DEF(SW_API_QOS_PT_DEF_SPRI_GET, SW_UINT32, 4, SW_PARAM_IN, "Port ID"),\ - SW_PARAM_DEF(SW_API_QOS_PT_DEF_SPRI_GET, SW_UINT32, 4, SW_PARAM_PTR|SW_PARAM_OUT, "default spri"), - -#define SW_API_QOS_PT_DEF_CPRI_SET_DESC \ - SW_PARAM_DEF(SW_API_QOS_PT_DEF_CPRI_SET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"),\ - SW_PARAM_DEF(SW_API_QOS_PT_DEF_CPRI_SET, SW_UINT32, 4, SW_PARAM_IN, "Port ID"),\ - SW_PARAM_DEF(SW_API_QOS_PT_DEF_CPRI_SET, SW_UINT32, 4, SW_PARAM_IN, "default cpri"), - - -#define SW_API_QOS_PT_FORCE_SPRI_ST_SET_DESC \ - SW_PARAM_DEF(SW_API_QOS_PT_FORCE_SPRI_ST_SET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"),\ - SW_PARAM_DEF(SW_API_QOS_PT_FORCE_SPRI_ST_SET, SW_UINT32, 4, SW_PARAM_IN, "Port ID"),\ - SW_PARAM_DEF(SW_API_QOS_PT_FORCE_SPRI_ST_SET, SW_ENABLE, 4, SW_PARAM_IN, "Enable"), - -#define SW_API_QOS_PT_FORCE_SPRI_ST_GET_DESC \ - SW_PARAM_DEF(SW_API_QOS_PT_FORCE_SPRI_ST_GET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"),\ - SW_PARAM_DEF(SW_API_QOS_PT_FORCE_SPRI_ST_GET, SW_UINT32, 4, SW_PARAM_IN, "Port ID"),\ - SW_PARAM_DEF(SW_API_QOS_PT_FORCE_SPRI_ST_GET, SW_ENABLE, 4, SW_PARAM_PTR|SW_PARAM_OUT, "Enable"), - -#define SW_API_QOS_PT_FORCE_CPRI_ST_SET_DESC \ - SW_PARAM_DEF(SW_API_QOS_PT_FORCE_CPRI_ST_SET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"),\ - SW_PARAM_DEF(SW_API_QOS_PT_FORCE_CPRI_ST_SET, SW_UINT32, 4, SW_PARAM_IN, "Port ID"),\ - SW_PARAM_DEF(SW_API_QOS_PT_FORCE_CPRI_ST_SET, SW_ENABLE, 4, SW_PARAM_IN, "Enable"), - -#define SW_API_QOS_PT_FORCE_CPRI_ST_GET_DESC \ - SW_PARAM_DEF(SW_API_QOS_PT_FORCE_CPRI_ST_GET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"),\ - SW_PARAM_DEF(SW_API_QOS_PT_FORCE_CPRI_ST_GET, SW_UINT32, 4, SW_PARAM_IN, "Port ID"),\ - SW_PARAM_DEF(SW_API_QOS_PT_FORCE_CPRI_ST_GET, SW_ENABLE, 4, SW_PARAM_PTR|SW_PARAM_OUT, "Enable"), - - - -#define SW_API_QOS_PT_DEF_CPRI_GET_DESC \ - SW_PARAM_DEF(SW_API_QOS_PT_DEF_CPRI_GET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"),\ - SW_PARAM_DEF(SW_API_QOS_PT_DEF_CPRI_GET, SW_UINT32, 4, SW_PARAM_IN, "Port ID"),\ - SW_PARAM_DEF(SW_API_QOS_PT_DEF_CPRI_GET, SW_UINT32, 4, SW_PARAM_PTR|SW_PARAM_OUT, "default cpri"), - - -#define SW_API_QOS_QUEUE_REMARK_SET_DESC \ - SW_PARAM_DEF(SW_API_QOS_QUEUE_REMARK_SET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"),\ - SW_PARAM_DEF(SW_API_QOS_QUEUE_REMARK_SET, SW_UINT32, 4, SW_PARAM_IN, "Port ID"),\ - SW_PARAM_DEF(SW_API_QOS_QUEUE_REMARK_SET, SW_UINT32, 4, SW_PARAM_IN, "Queue ID"),\ - SW_PARAM_DEF(SW_API_QOS_QUEUE_REMARK_SET, SW_UINT32, 4, SW_PARAM_IN, "Table ID"), \ - SW_PARAM_DEF(SW_API_QOS_QUEUE_REMARK_SET, SW_ENABLE, 4, SW_PARAM_IN, "Enable"), - -#define SW_API_QOS_QUEUE_REMARK_GET_DESC \ - SW_PARAM_DEF(SW_API_QOS_QUEUE_REMARK_GET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"),\ - SW_PARAM_DEF(SW_API_QOS_QUEUE_REMARK_GET, SW_UINT32, 4, SW_PARAM_IN, "Port ID"),\ - SW_PARAM_DEF(SW_API_QOS_QUEUE_REMARK_GET, SW_UINT32, 4, SW_PARAM_IN, "Queue ID"),\ - SW_PARAM_DEF(SW_API_QOS_QUEUE_REMARK_GET, SW_UINT32, 4, \ - SW_PARAM_PTR|SW_PARAM_OUT, "Table ID"), \ - SW_PARAM_DEF(SW_API_QOS_QUEUE_REMARK_GET, SW_ENABLE, 4, \ - SW_PARAM_PTR|SW_PARAM_OUT, "Enable"), - - - - -#define SW_API_PT_IGMPS_MODE_SET_DESC \ - SW_PARAM_DEF(SW_API_PT_IGMPS_MODE_SET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"),\ - SW_PARAM_DEF(SW_API_PT_IGMPS_MODE_SET, SW_UINT32, 4, SW_PARAM_IN, "Port No."), \ - SW_PARAM_DEF(SW_API_PT_IGMPS_MODE_SET, SW_ENABLE, 4, SW_PARAM_IN, "IGMP snooping"), - -#define SW_API_PT_IGMPS_MODE_GET_DESC \ - SW_PARAM_DEF(SW_API_PT_IGMPS_MODE_GET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \ - SW_PARAM_DEF(SW_API_PT_IGMPS_MODE_GET, SW_UINT32, 4, SW_PARAM_IN, "Port No."), \ - SW_PARAM_DEF(SW_API_PT_IGMPS_MODE_GET, SW_ENABLE, 4, \ - SW_PARAM_PTR|SW_PARAM_OUT, "IGMP snooping"), - -#define SW_API_IGMP_MLD_CMD_SET_DESC \ - SW_PARAM_DEF(SW_API_IGMP_MLD_CMD_SET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \ - SW_PARAM_DEF(SW_API_IGMP_MLD_CMD_SET, SW_MACCMD, \ - sizeof(fal_fwd_cmd_t), SW_PARAM_IN, "cmd"), - -#define SW_API_IGMP_MLD_CMD_GET_DESC \ - SW_PARAM_DEF(SW_API_IGMP_MLD_CMD_GET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \ - SW_PARAM_DEF(SW_API_IGMP_MLD_CMD_GET, SW_MACCMD, \ - sizeof(fal_fwd_cmd_t), SW_PARAM_PTR|SW_PARAM_OUT, "cmd"), - -#define SW_API_IGMP_PT_JOIN_SET_DESC \ - SW_PARAM_DEF(SW_API_IGMP_PT_JOIN_SET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \ - SW_PARAM_DEF(SW_API_IGMP_PT_JOIN_SET, SW_UINT32, 4, SW_PARAM_IN, "Port ID"), \ - SW_PARAM_DEF(SW_API_IGMP_PT_JOIN_SET, SW_ENABLE, 4, SW_PARAM_IN, "Join"), - -#define SW_API_IGMP_PT_JOIN_GET_DESC \ - SW_PARAM_DEF(SW_API_IGMP_PT_JOIN_GET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \ - SW_PARAM_DEF(SW_API_IGMP_PT_JOIN_GET, SW_UINT32, 4, SW_PARAM_IN, "Port ID"), \ - SW_PARAM_DEF(SW_API_IGMP_PT_JOIN_GET, SW_ENABLE, 4, SW_PARAM_PTR|SW_PARAM_OUT, "Join"), - -#define SW_API_IGMP_PT_LEAVE_SET_DESC \ - SW_PARAM_DEF(SW_API_IGMP_PT_LEAVE_SET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \ - SW_PARAM_DEF(SW_API_IGMP_PT_LEAVE_SET, SW_UINT32, 4, SW_PARAM_IN, "Port ID"), \ - SW_PARAM_DEF(SW_API_IGMP_PT_LEAVE_SET, SW_ENABLE, 4, SW_PARAM_IN, "Leave"), - -#define SW_API_IGMP_PT_LEAVE_GET_DESC \ - SW_PARAM_DEF(SW_API_IGMP_PT_LEAVE_GET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \ - SW_PARAM_DEF(SW_API_IGMP_PT_LEAVE_GET, SW_UINT32, 4, SW_PARAM_IN, "Port ID"), \ - SW_PARAM_DEF(SW_API_IGMP_PT_LEAVE_GET, SW_ENABLE, 4, SW_PARAM_PTR|SW_PARAM_OUT, "Leave"), - -#define SW_API_IGMP_RP_SET_DESC \ - SW_PARAM_DEF(SW_API_IGMP_RP_SET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \ - SW_PARAM_DEF(SW_API_IGMP_RP_SET, SW_PBMP, \ - sizeof(fal_pbmp_t), SW_PARAM_IN, "Ports"), - -#define SW_API_IGMP_RP_GET_DESC \ - SW_PARAM_DEF(SW_API_IGMP_RP_GET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \ - SW_PARAM_DEF(SW_API_IGMP_RP_GET, SW_PBMP, \ - sizeof(fal_pbmp_t), SW_PARAM_PTR|SW_PARAM_OUT, "Ports"), - -#define SW_API_IGMP_ENTRY_CREAT_SET_DESC \ - SW_PARAM_DEF(SW_API_IGMP_ENTRY_CREAT_SET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \ - SW_PARAM_DEF(SW_API_IGMP_ENTRY_CREAT_SET, SW_ENABLE, 4, SW_PARAM_IN, "creat Entry"), - -#define SW_API_IGMP_ENTRY_CREAT_GET_DESC \ - SW_PARAM_DEF(SW_API_IGMP_ENTRY_CREAT_GET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \ - SW_PARAM_DEF(SW_API_IGMP_ENTRY_CREAT_GET, SW_ENABLE, 4, \ - SW_PARAM_PTR|SW_PARAM_OUT, "creat Entry"), - -#define SW_API_IGMP_ENTRY_STATIC_SET_DESC \ - SW_PARAM_DEF(SW_API_IGMP_ENTRY_STATIC_SET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \ - SW_PARAM_DEF(SW_API_IGMP_ENTRY_STATIC_SET, SW_ENABLE, 4, SW_PARAM_IN, "static"), - -#define SW_API_IGMP_ENTRY_STATIC_GET_DESC \ - SW_PARAM_DEF(SW_API_IGMP_ENTRY_STATIC_GET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \ - SW_PARAM_DEF(SW_API_IGMP_ENTRY_STATIC_GET, SW_ENABLE, 4, SW_PARAM_PTR|SW_PARAM_OUT, "static"), - -#define SW_API_IGMP_ENTRY_LEAKY_SET_DESC \ - SW_PARAM_DEF(SW_API_IGMP_ENTRY_LEAKY_SET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \ - SW_PARAM_DEF(SW_API_IGMP_ENTRY_LEAKY_SET, SW_ENABLE, 4, SW_PARAM_IN, "leaky"), - -#define SW_API_IGMP_ENTRY_LEAKY_GET_DESC \ - SW_PARAM_DEF(SW_API_IGMP_ENTRY_LEAKY_GET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \ - SW_PARAM_DEF(SW_API_IGMP_ENTRY_LEAKY_GET, SW_ENABLE, 4, SW_PARAM_PTR|SW_PARAM_OUT, "leaky"), - -#define SW_API_IGMP_ENTRY_V3_SET_DESC \ - SW_PARAM_DEF(SW_API_IGMP_ENTRY_V3_SET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \ - SW_PARAM_DEF(SW_API_IGMP_ENTRY_V3_SET, SW_ENABLE, 4, SW_PARAM_IN, "version3"), - -#define SW_API_IGMP_ENTRY_V3_GET_DESC \ - SW_PARAM_DEF(SW_API_IGMP_ENTRY_V3_GET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \ - SW_PARAM_DEF(SW_API_IGMP_ENTRY_V3_GET, SW_ENABLE, 4, SW_PARAM_PTR|SW_PARAM_OUT, "version3"), - -#define SW_API_IGMP_ENTRY_QUEUE_SET_DESC \ - SW_PARAM_DEF(SW_API_IGMP_ENTRY_QUEUE_SET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \ - SW_PARAM_DEF(SW_API_IGMP_ENTRY_QUEUE_SET, SW_ENABLE, 4, SW_PARAM_IN, "queue"), \ - SW_PARAM_DEF(SW_API_IGMP_ENTRY_QUEUE_SET, SW_UINT32, 4, SW_PARAM_IN, "queue_id"), - -#define SW_API_IGMP_ENTRY_QUEUE_GET_DESC \ - SW_PARAM_DEF(SW_API_IGMP_ENTRY_QUEUE_GET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \ - SW_PARAM_DEF(SW_API_IGMP_ENTRY_QUEUE_GET, SW_ENABLE, 4, SW_PARAM_PTR|SW_PARAM_OUT, "queue"), \ - SW_PARAM_DEF(SW_API_IGMP_ENTRY_QUEUE_GET, SW_UINT32, 4, SW_PARAM_PTR|SW_PARAM_OUT, "queue_id"), - -#define SW_API_PT_IGMP_LEARN_LIMIT_SET_DESC \ - SW_PARAM_DEF(SW_API_PT_IGMP_LEARN_LIMIT_SET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \ - SW_PARAM_DEF(SW_API_PT_IGMP_LEARN_LIMIT_SET, SW_UINT32, 4, SW_PARAM_IN, "Port ID"),\ - SW_PARAM_DEF(SW_API_PT_IGMP_LEARN_LIMIT_SET, SW_ENABLE, 4, SW_PARAM_IN, "Enable"), \ - SW_PARAM_DEF(SW_API_PT_IGMP_LEARN_LIMIT_SET, SW_UINT32, 4, SW_PARAM_IN, "LimitCnt"), - -#define SW_API_PT_IGMP_LEARN_LIMIT_GET_DESC \ - SW_PARAM_DEF(SW_API_PT_IGMP_LEARN_LIMIT_GET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"),\ - SW_PARAM_DEF(SW_API_PT_IGMP_LEARN_LIMIT_GET, SW_UINT32, 4, SW_PARAM_IN, "Port ID"),\ - SW_PARAM_DEF(SW_API_PT_IGMP_LEARN_LIMIT_GET, SW_ENABLE, 4, \ - SW_PARAM_PTR|SW_PARAM_OUT, "Enable"), \ - SW_PARAM_DEF(SW_API_PT_IGMP_LEARN_LIMIT_GET, SW_UINT32, 4, \ - SW_PARAM_PTR|SW_PARAM_OUT, "LimitCnt"), - -#define SW_API_PT_IGMP_LEARN_EXCEED_CMD_SET_DESC \ - SW_PARAM_DEF(SW_API_PT_IGMP_LEARN_EXCEED_CMD_SET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \ - SW_PARAM_DEF(SW_API_PT_IGMP_LEARN_EXCEED_CMD_SET, SW_UINT32, 4, SW_PARAM_IN, "Port ID"),\ - SW_PARAM_DEF(SW_API_PT_IGMP_LEARN_EXCEED_CMD_SET, SW_MACCMD, \ - sizeof(fal_fwd_cmd_t), SW_PARAM_IN, "cmd"), - -#define SW_API_PT_IGMP_LEARN_EXCEED_CMD_GET_DESC \ - SW_PARAM_DEF(SW_API_PT_IGMP_LEARN_EXCEED_CMD_GET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \ - SW_PARAM_DEF(SW_API_PT_IGMP_LEARN_EXCEED_CMD_GET, SW_UINT32, 4, SW_PARAM_IN, "Port ID"),\ - SW_PARAM_DEF(SW_API_PT_IGMP_LEARN_EXCEED_CMD_GET, SW_MACCMD, \ - sizeof(fal_fwd_cmd_t), SW_PARAM_PTR|SW_PARAM_OUT, "cmd"), - -#define SW_API_IGMP_SG_ENTRY_SET_DESC \ - SW_PARAM_DEF(SW_API_IGMP_SG_ENTRY_SET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \ - SW_PARAM_DEF(SW_API_IGMP_SG_ENTRY_SET, SW_SGENTRY, \ - sizeof(fal_igmp_sg_entry_t), SW_PARAM_PTR|SW_PARAM_IN|SW_PARAM_OUT, "entry"), - -#define SW_API_IGMP_SG_ENTRY_CLEAR_DESC \ - SW_PARAM_DEF(SW_API_IGMP_SG_ENTRY_CLEAR, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \ - SW_PARAM_DEF(SW_API_IGMP_SG_ENTRY_CLEAR, SW_SGENTRY, \ - sizeof(fal_igmp_sg_entry_t), SW_PARAM_PTR|SW_PARAM_IN|SW_PARAM_OUT, "entry"), - -#define SW_API_IGMP_SG_ENTRY_QUERY_DESC \ - SW_PARAM_DEF(SW_API_IGMP_SG_ENTRY_QUERY, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \ - SW_PARAM_DEF(SW_API_IGMP_SG_ENTRY_QUERY, SW_SGINFOENTRY, \ - sizeof(fal_igmp_sg_info_t), SW_PARAM_PTR|SW_PARAM_IN|SW_PARAM_OUT, "info"), - -#define SW_API_IGMP_SG_ENTRY_SHOW_DESC \ - SW_PARAM_DEF(SW_API_IGMP_SG_ENTRY_SHOW, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), - - - - -#define SW_API_UC_LEAKY_MODE_SET_DESC \ - SW_PARAM_DEF(SW_API_UC_LEAKY_MODE_SET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \ - SW_PARAM_DEF(SW_API_UC_LEAKY_MODE_SET, SW_LEAKY, \ - sizeof(fal_leaky_ctrl_mode_t), SW_PARAM_IN, "Uc Leaky mode"), - -#define SW_API_UC_LEAKY_MODE_GET_DESC \ - SW_PARAM_DEF(SW_API_UC_LEAKY_MODE_GET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \ - SW_PARAM_DEF(SW_API_UC_LEAKY_MODE_GET, SW_LEAKY, \ - sizeof(fal_leaky_ctrl_mode_t), SW_PARAM_PTR|SW_PARAM_OUT, "Uc Leaky mode"), - -#define SW_API_MC_LEAKY_MODE_SET_DESC \ - SW_PARAM_DEF(SW_API_MC_LEAKY_MODE_SET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \ - SW_PARAM_DEF(SW_API_MC_LEAKY_MODE_SET, SW_LEAKY, \ - sizeof(fal_leaky_ctrl_mode_t), SW_PARAM_IN, "Mc Leaky mode"), - -#define SW_API_MC_LEAKY_MODE_GET_DESC \ - SW_PARAM_DEF(SW_API_MC_LEAKY_MODE_GET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \ - SW_PARAM_DEF(SW_API_MC_LEAKY_MODE_GET, SW_LEAKY, \ - sizeof(fal_leaky_ctrl_mode_t), SW_PARAM_PTR|SW_PARAM_OUT, "Mc Leaky mode"), - -#define SW_API_ARP_LEAKY_MODE_SET_DESC \ - SW_PARAM_DEF(SW_API_ARP_LEAKY_MODE_SET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \ - SW_PARAM_DEF(SW_API_ARP_LEAKY_MODE_SET, SW_UINT32, 4, SW_PARAM_IN, "Port ID"), \ - SW_PARAM_DEF(SW_API_ARP_LEAKY_MODE_SET, SW_ENABLE, 4, SW_PARAM_IN, "Arp leaky"), - -#define SW_API_ARP_LEAKY_MODE_GET_DESC \ - SW_PARAM_DEF(SW_API_ARP_LEAKY_MODE_GET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \ - SW_PARAM_DEF(SW_API_ARP_LEAKY_MODE_GET, SW_UINT32, 4, SW_PARAM_IN, "Port ID"), \ - SW_PARAM_DEF(SW_API_ARP_LEAKY_MODE_GET, SW_ENABLE, 4, SW_PARAM_PTR|SW_PARAM_OUT, "Arp leaky"), - -#define SW_API_PT_UC_LEAKY_MODE_SET_DESC \ - SW_PARAM_DEF(SW_API_PT_UC_LEAKY_MODE_SET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \ - SW_PARAM_DEF(SW_API_PT_UC_LEAKY_MODE_SET, SW_UINT32, 4, SW_PARAM_IN, "Port ID"), \ - SW_PARAM_DEF(SW_API_PT_UC_LEAKY_MODE_SET, SW_ENABLE, 4, SW_PARAM_IN, "Port Unicast leaky"), - -#define SW_API_PT_UC_LEAKY_MODE_GET_DESC \ - SW_PARAM_DEF(SW_API_PT_UC_LEAKY_MODE_GET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \ - SW_PARAM_DEF(SW_API_PT_UC_LEAKY_MODE_GET, SW_UINT32, 4, SW_PARAM_IN, "Port ID"), \ - SW_PARAM_DEF(SW_API_PT_UC_LEAKY_MODE_GET, SW_ENABLE, 4, \ - SW_PARAM_PTR|SW_PARAM_OUT, "Port Uc leaky"), - -#define SW_API_PT_MC_LEAKY_MODE_SET_DESC \ - SW_PARAM_DEF(SW_API_PT_MC_LEAKY_MODE_SET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \ - SW_PARAM_DEF(SW_API_PT_MC_LEAKY_MODE_SET, SW_UINT32, 4, SW_PARAM_IN, "Port ID"), \ - SW_PARAM_DEF(SW_API_PT_MC_LEAKY_MODE_SET, SW_ENABLE, 4, SW_PARAM_IN, "Port Multicast leaky"), - -#define SW_API_PT_MC_LEAKY_MODE_GET_DESC \ - SW_PARAM_DEF(SW_API_PT_MC_LEAKY_MODE_GET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \ - SW_PARAM_DEF(SW_API_PT_MC_LEAKY_MODE_GET, SW_UINT32, 4, SW_PARAM_IN, "Port ID"), \ - SW_PARAM_DEF(SW_API_PT_MC_LEAKY_MODE_GET, SW_ENABLE, 4, \ - SW_PARAM_PTR|SW_PARAM_OUT, "Port Mc leaky"), - - - -#define SW_API_MIRROR_ANALY_PT_SET_DESC \ - SW_PARAM_DEF(SW_API_MIRROR_ANALY_PT_SET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \ - SW_PARAM_DEF(SW_API_MIRROR_ANALY_PT_SET, SW_UINT32, 4, SW_PARAM_IN, "Port ID"), - -#define SW_API_MIRROR_ANALY_PT_GET_DESC \ - SW_PARAM_DEF(SW_API_MIRROR_ANALY_PT_GET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \ - SW_PARAM_DEF(SW_API_MIRROR_ANALY_PT_GET, SW_UINT32, 4, SW_PARAM_PTR|SW_PARAM_OUT, "Port ID"), - -#define SW_API_MIRROR_IN_PT_SET_DESC \ - SW_PARAM_DEF(SW_API_MIRROR_IN_PT_SET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \ - SW_PARAM_DEF(SW_API_MIRROR_IN_PT_SET, SW_UINT32, 4, SW_PARAM_IN, "Port ID"), \ - SW_PARAM_DEF(SW_API_MIRROR_IN_PT_SET, SW_ENABLE, 4, SW_PARAM_IN, "Ingerss mirror"), - -#define SW_API_MIRROR_IN_PT_GET_DESC \ - SW_PARAM_DEF(SW_API_MIRROR_IN_PT_GET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \ - SW_PARAM_DEF(SW_API_MIRROR_IN_PT_GET, SW_UINT32, 4, SW_PARAM_IN, "Port ID"), \ - SW_PARAM_DEF(SW_API_MIRROR_IN_PT_GET, SW_ENABLE, 4, \ - SW_PARAM_PTR|SW_PARAM_OUT, "Ingeress mirror"), - -#define SW_API_MIRROR_EG_PT_SET_DESC \ - SW_PARAM_DEF(SW_API_MIRROR_EG_PT_SET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \ - SW_PARAM_DEF(SW_API_MIRROR_EG_PT_SET, SW_UINT32, 4, SW_PARAM_IN, "Port ID"), \ - SW_PARAM_DEF(SW_API_MIRROR_EG_PT_SET, SW_ENABLE, 4, SW_PARAM_IN, "Egerss mirror"), - -#define SW_API_MIRROR_EG_PT_GET_DESC \ - SW_PARAM_DEF(SW_API_MIRROR_EG_PT_GET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \ - SW_PARAM_DEF(SW_API_MIRROR_EG_PT_GET, SW_UINT32, 4, SW_PARAM_IN, "Port ID"), \ - SW_PARAM_DEF(SW_API_MIRROR_EG_PT_GET, SW_ENABLE, 4, SW_PARAM_PTR|SW_PARAM_OUT, \ - "Egeress mirror"), - -#define SW_API_MIRROR_ANALYSIS_CONFIG_SET_DESC \ - SW_PARAM_DEF(SW_API_MIRROR_ANALYSIS_CONFIG_SET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \ - SW_PARAM_DEF(SW_API_MIRROR_ANALYSIS_CONFIG_SET, SW_MIRR_DIRECTION, \ - sizeof(fal_mirr_direction_t), SW_PARAM_IN, "Direction"), \ - SW_PARAM_DEF(SW_API_MIRROR_ANALYSIS_CONFIG_SET, SW_MIRR_ANALYSIS_CONFIG, \ - sizeof(fal_mirr_analysis_config_t), SW_PARAM_PTR|SW_PARAM_IN, "Config"), - -#define SW_API_MIRROR_ANALYSIS_CONFIG_GET_DESC \ - SW_PARAM_DEF(SW_API_MIRROR_ANALYSIS_CONFIG_GET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \ - SW_PARAM_DEF(SW_API_MIRROR_ANALYSIS_CONFIG_GET, SW_MIRR_DIRECTION, \ - sizeof(fal_mirr_direction_t), SW_PARAM_IN, "Direction"), \ - SW_PARAM_DEF(SW_API_MIRROR_ANALYSIS_CONFIG_GET, SW_MIRR_ANALYSIS_CONFIG, \ - sizeof(fal_mirr_analysis_config_t), SW_PARAM_PTR|SW_PARAM_OUT, "Config"), - -#define SW_API_RSS_HASH_CONFIG_SET_DESC \ - SW_PARAM_DEF(SW_API_RSS_HASH_CONFIG_SET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \ - SW_PARAM_DEF(SW_API_RSS_HASH_CONFIG_SET, SW_RSS_HASH_MODE, \ - sizeof(fal_rss_hash_mode_t), SW_PARAM_IN, "Mode"), \ - SW_PARAM_DEF(SW_API_RSS_HASH_CONFIG_SET, SW_RSS_HASH_CONFIG, \ - sizeof(fal_rss_hash_config_t), SW_PARAM_PTR|SW_PARAM_IN, "Config"), - -#define SW_API_RSS_HASH_CONFIG_GET_DESC \ - SW_PARAM_DEF(SW_API_RSS_HASH_CONFIG_GET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \ - SW_PARAM_DEF(SW_API_RSS_HASH_CONFIG_GET, SW_RSS_HASH_MODE, \ - sizeof(fal_rss_hash_mode_t), SW_PARAM_IN, "Mode"), \ - SW_PARAM_DEF(SW_API_RSS_HASH_CONFIG_GET, SW_RSS_HASH_CONFIG, \ - sizeof(fal_rss_hash_config_t), SW_PARAM_PTR|SW_PARAM_OUT, "Config"), - -#define SW_API_RATE_QU_EGRL_SET_DESC \ - SW_PARAM_DEF(SW_API_RATE_QU_EGRL_SET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"),\ - SW_PARAM_DEF(SW_API_RATE_QU_EGRL_SET, SW_UINT32, 4, SW_PARAM_IN, "Port ID"),\ - SW_PARAM_DEF(SW_API_RATE_QU_EGRL_SET, SW_UINT32, 4, SW_PARAM_IN, "Queue ID"),\ - SW_PARAM_DEF(SW_API_RATE_QU_EGRL_SET, SW_UINT32, 4, \ - SW_PARAM_PTR|SW_PARAM_IN|SW_PARAM_OUT, "Speed"),\ - SW_PARAM_DEF(SW_API_RATE_QU_EGRL_SET, SW_ENABLE, 4, SW_PARAM_IN, "Rate limit"), - -#define SW_API_RATE_QU_EGRL_GET_DESC \ - SW_PARAM_DEF(SW_API_RATE_QU_EGRL_GET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"),\ - SW_PARAM_DEF(SW_API_RATE_QU_EGRL_GET, SW_UINT32, 4, SW_PARAM_IN, "Port ID"),\ - SW_PARAM_DEF(SW_API_RATE_QU_EGRL_GET, SW_UINT32, 4, SW_PARAM_IN, "Queue ID"),\ - SW_PARAM_DEF(SW_API_RATE_QU_EGRL_GET, SW_UINT32, 4, SW_PARAM_PTR|SW_PARAM_OUT, "Speed"),\ - SW_PARAM_DEF(SW_API_RATE_QU_EGRL_GET, SW_ENABLE, 4, SW_PARAM_PTR|SW_PARAM_OUT, "Rate limit"), - -#define SW_API_RATE_PT_EGRL_SET_DESC \ - SW_PARAM_DEF(SW_API_RATE_PT_EGRL_SET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"),\ - SW_PARAM_DEF(SW_API_RATE_PT_EGRL_SET, SW_UINT32, 4, SW_PARAM_IN, "Port ID"),\ - SW_PARAM_DEF(SW_API_RATE_PT_EGRL_SET, SW_UINT32, 4, \ - SW_PARAM_PTR|SW_PARAM_IN|SW_PARAM_OUT, "Speed"),\ - SW_PARAM_DEF(SW_API_RATE_PT_EGRL_SET, SW_ENABLE, 4, SW_PARAM_IN, "Rate limit"), - -#define SW_API_RATE_PT_EGRL_GET_DESC \ - SW_PARAM_DEF(SW_API_RATE_PT_EGRL_GET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"),\ - SW_PARAM_DEF(SW_API_RATE_PT_EGRL_GET, SW_UINT32, 4, SW_PARAM_IN, "Port ID"),\ - SW_PARAM_DEF(SW_API_RATE_PT_EGRL_GET, SW_UINT32, 4, SW_PARAM_PTR|SW_PARAM_OUT, "Speed"),\ - SW_PARAM_DEF(SW_API_RATE_PT_EGRL_GET, SW_ENABLE, 4, SW_PARAM_PTR|SW_PARAM_OUT, "Rate limit"), - -#define SW_API_RATE_PT_INRL_SET_DESC \ - SW_PARAM_DEF(SW_API_RATE_PT_INRL_SET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"),\ - SW_PARAM_DEF(SW_API_RATE_PT_INRL_SET, SW_UINT32, 4, SW_PARAM_IN, "Port ID"),\ - SW_PARAM_DEF(SW_API_RATE_PT_INRL_SET, SW_UINT32, 4, \ - SW_PARAM_PTR|SW_PARAM_IN|SW_PARAM_OUT, "Speed"),\ - SW_PARAM_DEF(SW_API_RATE_PT_INRL_SET, SW_ENABLE, 4, SW_PARAM_IN, "Rate limit"), - -#define SW_API_RATE_PT_INRL_GET_DESC \ - SW_PARAM_DEF(SW_API_RATE_PT_INRL_GET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"),\ - SW_PARAM_DEF(SW_API_RATE_PT_INRL_GET, SW_UINT32, 4, SW_PARAM_IN, "Port ID"),\ - SW_PARAM_DEF(SW_API_RATE_PT_INRL_GET, SW_UINT32, 4, \ - SW_PARAM_PTR|SW_PARAM_OUT, "Speed"),\ - SW_PARAM_DEF(SW_API_RATE_PT_INRL_GET, SW_ENABLE, 4, \ - SW_PARAM_PTR|SW_PARAM_OUT, "Rate limit"), - -#define SW_API_STORM_CTRL_FRAME_SET_DESC \ - SW_PARAM_DEF(SW_API_STORM_CTRL_FRAME_SET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"),\ - SW_PARAM_DEF(SW_API_STORM_CTRL_FRAME_SET, SW_UINT32, 4, SW_PARAM_IN, "Port ID"),\ - SW_PARAM_DEF(SW_API_STORM_CTRL_FRAME_SET, SW_STORM, \ - sizeof(fal_storm_type_t), SW_PARAM_IN, "Frame type"),\ - SW_PARAM_DEF(SW_API_STORM_CTRL_FRAME_SET, SW_ENABLE, 4, SW_PARAM_IN, "strom contrl"), - -#define SW_API_STORM_CTRL_FRAME_GET_DESC \ - SW_PARAM_DEF(SW_API_STORM_CTRL_FRAME_GET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"),\ - SW_PARAM_DEF(SW_API_STORM_CTRL_FRAME_GET, SW_UINT32, 4, SW_PARAM_IN, "Port ID"),\ - SW_PARAM_DEF(SW_API_STORM_CTRL_FRAME_GET, SW_STORM, \ - sizeof(fal_storm_type_t), SW_PARAM_IN, "Frame type"),\ - SW_PARAM_DEF(SW_API_STORM_CTRL_FRAME_GET, SW_ENABLE, 4, \ - SW_PARAM_PTR|SW_PARAM_OUT, "strom contrl"), - -#define SW_API_STORM_CTRL_RATE_SET_DESC \ - SW_PARAM_DEF(SW_API_STORM_CTRL_RATE_SET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"),\ - SW_PARAM_DEF(SW_API_STORM_CTRL_RATE_SET, SW_UINT32, 4, SW_PARAM_IN, "Port ID"),\ - SW_PARAM_DEF(SW_API_STORM_CTRL_RATE_SET, SW_UINT32, 4, \ - SW_PARAM_PTR|SW_PARAM_IN|SW_PARAM_OUT, "Speed"), - -#define SW_API_STORM_CTRL_RATE_GET_DESC \ - SW_PARAM_DEF(SW_API_STORM_CTRL_RATE_GET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"),\ - SW_PARAM_DEF(SW_API_STORM_CTRL_RATE_GET, SW_UINT32, 4, SW_PARAM_IN, "Port ID"),\ - SW_PARAM_DEF(SW_API_STORM_CTRL_RATE_GET, SW_UINT32, 4, \ - SW_PARAM_PTR|SW_PARAM_OUT, "Speed"), - -#define SW_API_RATE_PORT_POLICER_SET_DESC \ - SW_PARAM_DEF(SW_API_RATE_PORT_POLICER_SET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"),\ - SW_PARAM_DEF(SW_API_RATE_PORT_POLICER_SET, SW_UINT32, 4, SW_PARAM_IN, "Port ID"),\ - SW_PARAM_DEF(SW_API_RATE_PORT_POLICER_SET, SW_INGPOLICER, \ - sizeof(fal_port_policer_t), SW_PARAM_PTR|SW_PARAM_IN|SW_PARAM_OUT, \ - "Policer"), - -#define SW_API_RATE_PORT_POLICER_GET_DESC \ - SW_PARAM_DEF(SW_API_RATE_PORT_POLICER_GET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"),\ - SW_PARAM_DEF(SW_API_RATE_PORT_POLICER_GET, SW_UINT32, 4, SW_PARAM_IN, "Port ID"),\ - SW_PARAM_DEF(SW_API_RATE_PORT_POLICER_GET, SW_INGPOLICER, \ - sizeof(fal_port_policer_t), SW_PARAM_PTR|SW_PARAM_OUT, "Policer"), - -#define SW_API_RATE_PORT_SHAPER_SET_DESC \ - SW_PARAM_DEF(SW_API_RATE_PORT_SHAPER_SET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"),\ - SW_PARAM_DEF(SW_API_RATE_PORT_SHAPER_SET, SW_UINT32, 4, SW_PARAM_IN, "Port ID"),\ - SW_PARAM_DEF(SW_API_RATE_PORT_SHAPER_SET, SW_ENABLE, 4, SW_PARAM_IN, "Status"), \ - SW_PARAM_DEF(SW_API_RATE_PORT_SHAPER_SET, SW_EGSHAPER, \ - sizeof(fal_egress_shaper_t), SW_PARAM_PTR|SW_PARAM_IN|SW_PARAM_OUT, "Shaper"), - -#define SW_API_RATE_PORT_SHAPER_GET_DESC \ - SW_PARAM_DEF(SW_API_RATE_PORT_SHAPER_GET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"),\ - SW_PARAM_DEF(SW_API_RATE_PORT_SHAPER_GET, SW_UINT32, 4, SW_PARAM_IN, "Port ID"),\ - SW_PARAM_DEF(SW_API_RATE_PORT_SHAPER_GET, SW_ENABLE, 4, SW_PARAM_PTR|SW_PARAM_OUT, "Status"), \ - SW_PARAM_DEF(SW_API_RATE_PORT_SHAPER_GET, SW_EGSHAPER, \ - sizeof(fal_egress_shaper_t), SW_PARAM_PTR|SW_PARAM_OUT, "Shaper"), - -#define SW_API_RATE_QUEUE_SHAPER_SET_DESC \ - SW_PARAM_DEF(SW_API_RATE_QUEUE_SHAPER_SET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"),\ - SW_PARAM_DEF(SW_API_RATE_QUEUE_SHAPER_SET, SW_UINT32, 4, SW_PARAM_IN, "Port ID"),\ - SW_PARAM_DEF(SW_API_RATE_QUEUE_SHAPER_SET, SW_UINT32, 4, SW_PARAM_IN, "Queue ID"),\ - SW_PARAM_DEF(SW_API_RATE_QUEUE_SHAPER_SET, SW_ENABLE, 4, SW_PARAM_IN, "Enable"), \ - SW_PARAM_DEF(SW_API_RATE_QUEUE_SHAPER_SET, SW_EGSHAPER, \ - sizeof(fal_egress_shaper_t), SW_PARAM_PTR|SW_PARAM_IN|SW_PARAM_OUT, "Shaper"), - -#define SW_API_RATE_QUEUE_SHAPER_GET_DESC \ - SW_PARAM_DEF(SW_API_RATE_QUEUE_SHAPER_GET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"),\ - SW_PARAM_DEF(SW_API_RATE_QUEUE_SHAPER_GET, SW_UINT32, 4, SW_PARAM_IN, "Port ID"),\ - SW_PARAM_DEF(SW_API_RATE_QUEUE_SHAPER_GET, SW_UINT32, 4, SW_PARAM_IN, "Queue ID"),\ - SW_PARAM_DEF(SW_API_RATE_QUEUE_SHAPER_GET, SW_ENABLE, 4, SW_PARAM_PTR|SW_PARAM_OUT, "Status"), \ - SW_PARAM_DEF(SW_API_RATE_QUEUE_SHAPER_GET, SW_EGSHAPER, \ - sizeof(fal_egress_shaper_t), SW_PARAM_PTR|SW_PARAM_OUT, "Shaper"), - -#define SW_API_RATE_ACL_POLICER_SET_DESC \ - SW_PARAM_DEF(SW_API_RATE_ACL_POLICER_SET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"),\ - SW_PARAM_DEF(SW_API_RATE_ACL_POLICER_SET, SW_UINT32, 4, SW_PARAM_IN, "Policer ID"),\ - SW_PARAM_DEF(SW_API_RATE_ACL_POLICER_SET, SW_ACLPOLICER, \ - sizeof(fal_acl_policer_t), SW_PARAM_PTR|SW_PARAM_IN|SW_PARAM_OUT, "Policer"), - -#define SW_API_RATE_ACL_POLICER_GET_DESC \ - SW_PARAM_DEF(SW_API_RATE_ACL_POLICER_GET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"),\ - SW_PARAM_DEF(SW_API_RATE_ACL_POLICER_GET, SW_UINT32, 4, SW_PARAM_IN, "Policer ID"),\ - SW_PARAM_DEF(SW_API_RATE_ACL_POLICER_GET, SW_ACLPOLICER, \ - sizeof(fal_acl_policer_t), SW_PARAM_PTR|SW_PARAM_OUT, "Policer"), - -#define SW_API_RATE_PT_ADDRATEBYTE_SET_DESC\ - SW_PARAM_DEF(SW_API_RATE_PT_ADDRATEBYTE_SET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"),\ - SW_PARAM_DEF(SW_API_RATE_PT_ADDRATEBYTE_SET, SW_UINT32, 4, SW_PARAM_IN, "Port ID"),\ - SW_PARAM_DEF(SW_API_RATE_PT_ADDRATEBYTE_SET, SW_UINT32, 4, SW_PARAM_IN, "AddRateByte"), - -#define SW_API_RATE_PT_ADDRATEBYTE_GET_DESC\ - SW_PARAM_DEF(SW_API_RATE_PT_ADDRATEBYTE_GET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"),\ - SW_PARAM_DEF(SW_API_RATE_PT_ADDRATEBYTE_GET, SW_UINT32, 4, SW_PARAM_IN, "Port ID"),\ - SW_PARAM_DEF(SW_API_RATE_PT_ADDRATEBYTE_GET, SW_UINT32, 4, \ - SW_PARAM_PTR|SW_PARAM_OUT, "AddRateByte"), - -#define SW_API_RATE_PT_GOL_FLOW_EN_SET_DESC \ - SW_PARAM_DEF(SW_API_RATE_PT_GOL_FLOW_EN_SET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"),\ - SW_PARAM_DEF(SW_API_RATE_PT_GOL_FLOW_EN_SET, SW_UINT32, 4, SW_PARAM_IN, "Port ID"),\ - SW_PARAM_DEF(SW_API_RATE_PT_GOL_FLOW_EN_SET, SW_ENABLE, 4, SW_PARAM_IN, "Enable"), - -#define SW_API_RATE_PT_GOL_FLOW_EN_GET_DESC \ - SW_PARAM_DEF(SW_API_RATE_PT_GOL_FLOW_EN_GET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"),\ - SW_PARAM_DEF(SW_API_RATE_PT_GOL_FLOW_EN_GET, SW_UINT32, 4, SW_PARAM_IN, "Port ID"),\ - SW_PARAM_DEF(SW_API_RATE_PT_GOL_FLOW_EN_GET, SW_ENABLE, 4, SW_PARAM_PTR|SW_PARAM_OUT, "Enable"), - -#define SW_API_STP_PT_STATE_SET_DESC \ - SW_PARAM_DEF(SW_API_STP_PT_STATE_SET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"),\ - SW_PARAM_DEF(SW_API_STP_PT_STATE_SET, SW_UINT32, 4, SW_PARAM_IN, "Spaning tree ID"),\ - SW_PARAM_DEF(SW_API_STP_PT_STATE_SET, SW_UINT32, 4, SW_PARAM_IN, "Port ID"),\ - SW_PARAM_DEF(SW_API_STP_PT_STATE_SET, SW_STP, \ - sizeof(fal_stp_state_t), SW_PARAM_IN, "Port State"), - -#define SW_API_STP_PT_STATE_GET_DESC \ - SW_PARAM_DEF(SW_API_STP_PT_STATE_GET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"),\ - SW_PARAM_DEF(SW_API_STP_PT_STATE_GET, SW_UINT32, 4, SW_PARAM_IN, "Spaning tree ID"),\ - SW_PARAM_DEF(SW_API_STP_PT_STATE_GET, SW_UINT32, 4, SW_PARAM_IN, "Port ID"),\ - SW_PARAM_DEF(SW_API_STP_PT_STATE_GET, SW_STP, \ - sizeof(fal_stp_state_t), SW_PARAM_PTR|SW_PARAM_OUT, "Port State"), - - - - -#define SW_API_PT_MIB_GET_DESC \ - SW_PARAM_DEF(SW_API_PT_MIB_GET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \ - SW_PARAM_DEF(SW_API_PT_MIB_GET, SW_UINT32, 4, SW_PARAM_IN, "Port No."), \ - SW_PARAM_DEF(SW_API_PT_MIB_GET, SW_MIB, \ - sizeof(fal_mib_info_t), SW_PARAM_PTR|SW_PARAM_OUT, \ - "MIB info"), -#define SW_API_PT_XGMIB_GET_DESC \ - SW_PARAM_DEF(SW_API_PT_XGMIB_GET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \ - SW_PARAM_DEF(SW_API_PT_XGMIB_GET, SW_UINT32, 4, SW_PARAM_IN, "Port No."), \ - SW_PARAM_DEF(SW_API_PT_XGMIB_GET, SW_XGMIB, \ - sizeof(fal_xgmib_info_t), SW_PARAM_PTR|SW_PARAM_OUT, \ - "XGMIB info"), - -#define SW_API_MIB_STATUS_SET_DESC \ - SW_PARAM_DEF(SW_API_MIB_STATUS_SET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \ - SW_PARAM_DEF(SW_API_MIB_STATUS_SET, SW_ENABLE, 4, SW_PARAM_IN, "MIB status"), - -#define SW_API_MIB_STATUS_GET_DESC \ - SW_PARAM_DEF(SW_API_MIB_STATUS_GET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \ - SW_PARAM_DEF(SW_API_MIB_STATUS_GET, SW_ENABLE, 4, SW_PARAM_PTR|SW_PARAM_OUT, "MIB status"), - -#define SW_API_PT_MIB_FLUSH_COUNTERS_DESC\ - SW_PARAM_DEF(SW_API_PT_MIB_FLUSH_COUNTERS, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \ - SW_PARAM_DEF(SW_API_PT_MIB_FLUSH_COUNTERS, SW_UINT32, 4, SW_PARAM_IN, "Port No."), - -#define SW_API_MIB_CPU_KEEP_SET_DESC \ - SW_PARAM_DEF(SW_API_MIB_CPU_KEEP_SET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \ - SW_PARAM_DEF(SW_API_MIB_CPU_KEEP_SET, SW_ENABLE, 4, SW_PARAM_IN, "CPU_KEEP Set"), - -#define SW_API_MIB_CPU_KEEP_GET_DESC \ - SW_PARAM_DEF(SW_API_MIB_CPU_KEEP_GET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \ - SW_PARAM_DEF(SW_API_MIB_CPU_KEEP_GET, SW_ENABLE, 4, SW_PARAM_PTR|SW_PARAM_OUT, "CPU_KEEP Get"), - -#define SW_API_PT_MIB_COUNTER_GET_DESC \ - SW_PARAM_DEF(SW_API_PT_MIB_COUNTER_GET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \ - SW_PARAM_DEF(SW_API_PT_MIB_COUNTER_GET, SW_UINT32, 4, SW_PARAM_IN, "Port No."), \ - SW_PARAM_DEF(SW_API_PT_MIB_COUNTER_GET, SW_MIB_CNTR, \ - sizeof(fal_mib_counter_t), SW_PARAM_PTR|SW_PARAM_OUT, \ - "MIB Counter"), - - - -#define SW_API_ARP_STATUS_SET_DESC \ - SW_PARAM_DEF(SW_API_ARP_STATUS_SET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \ - SW_PARAM_DEF(SW_API_ARP_STATUS_SET, SW_ENABLE, 4, SW_PARAM_IN, "ARP acknowledge"), - -#define SW_API_ARP_STATUS_GET_DESC \ - SW_PARAM_DEF(SW_API_ARP_STATUS_GET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \ - SW_PARAM_DEF(SW_API_ARP_STATUS_GET, SW_ENABLE, 4, SW_PARAM_PTR|SW_PARAM_OUT, "ARP acknowledge"), - -#define SW_API_FRAME_MAX_SIZE_SET_DESC \ - SW_PARAM_DEF(SW_API_FRAME_MAX_SIZE_SET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \ - SW_PARAM_DEF(SW_API_FRAME_MAX_SIZE_SET, SW_UINT32, 4, SW_PARAM_IN, "Frame Size"), - -#define SW_API_FRAME_MAX_SIZE_GET_DESC \ - SW_PARAM_DEF(SW_API_FRAME_MAX_SIZE_GET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \ - SW_PARAM_DEF(SW_API_FRAME_MAX_SIZE_GET, SW_UINT32, 4, SW_PARAM_PTR|SW_PARAM_OUT, "Frame Size"), - -#define SW_API_PT_UNK_SA_CMD_SET_DESC \ - SW_PARAM_DEF(SW_API_PT_UNK_SA_CMD_SET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \ - SW_PARAM_DEF(SW_API_PT_UNK_SA_CMD_SET, SW_UINT32, 4, SW_PARAM_IN, "Port ID"), \ - SW_PARAM_DEF(SW_API_PT_UNK_SA_CMD_SET, SW_MACCMD, \ - sizeof(fal_fwd_cmd_t), SW_PARAM_IN, "Forwarding"), - -#define SW_API_PT_UNK_SA_CMD_GET_DESC \ - SW_PARAM_DEF(SW_API_PT_UNK_SA_CMD_GET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \ - SW_PARAM_DEF(SW_API_PT_UNK_SA_CMD_GET, SW_UINT32, 4, SW_PARAM_IN, "Port ID"), \ - SW_PARAM_DEF(SW_API_PT_UNK_SA_CMD_GET, SW_MACCMD, \ - sizeof(fal_fwd_cmd_t), SW_PARAM_PTR|SW_PARAM_OUT, "Forwarding"), - -#define SW_API_PT_UNK_UC_FILTER_SET_DESC \ - SW_PARAM_DEF(SW_API_PT_UNK_UC_FILTER_SET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \ - SW_PARAM_DEF(SW_API_PT_UNK_UC_FILTER_SET, SW_UINT32, 4, SW_PARAM_IN, "Port ID"), \ - SW_PARAM_DEF(SW_API_PT_UNK_UC_FILTER_SET, SW_ENABLE, 4, SW_PARAM_IN, "Filter"), - -#define SW_API_PT_UNK_UC_FILTER_GET_DESC \ - SW_PARAM_DEF(SW_API_PT_UNK_UC_FILTER_GET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \ - SW_PARAM_DEF(SW_API_PT_UNK_UC_FILTER_GET, SW_UINT32, 4, SW_PARAM_IN, "Port ID"), \ - SW_PARAM_DEF(SW_API_PT_UNK_UC_FILTER_GET, SW_ENABLE, 4, SW_PARAM_PTR|SW_PARAM_OUT, "Filter"), - -#define SW_API_PT_UNK_MC_FILTER_SET_DESC \ - SW_PARAM_DEF(SW_API_PT_UNK_MC_FILTER_SET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \ - SW_PARAM_DEF(SW_API_PT_UNK_MC_FILTER_SET, SW_UINT32, 4, SW_PARAM_IN, "Port ID"), \ - SW_PARAM_DEF(SW_API_PT_UNK_MC_FILTER_SET, SW_ENABLE, 4, SW_PARAM_IN, "Filter"), - -#define SW_API_PT_UNK_MC_FILTER_GET_DESC \ - SW_PARAM_DEF(SW_API_PT_UNK_MC_FILTER_GET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \ - SW_PARAM_DEF(SW_API_PT_UNK_MC_FILTER_GET, SW_UINT32, 4, SW_PARAM_IN, "Port ID"), \ - SW_PARAM_DEF(SW_API_PT_UNK_MC_FILTER_GET, SW_ENABLE, 4, SW_PARAM_PTR|SW_PARAM_OUT, "Filter"), - -#define SW_API_PT_BC_FILTER_SET_DESC \ - SW_PARAM_DEF(SW_API_PT_BC_FILTER_SET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \ - SW_PARAM_DEF(SW_API_PT_BC_FILTER_SET, SW_UINT32, 4, SW_PARAM_IN, "Port ID"), \ - SW_PARAM_DEF(SW_API_PT_BC_FILTER_SET, SW_ENABLE, 4, SW_PARAM_IN, "Filter"), - -#define SW_API_PT_BC_FILTER_GET_DESC \ - SW_PARAM_DEF(SW_API_PT_BC_FILTER_GET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \ - SW_PARAM_DEF(SW_API_PT_BC_FILTER_GET, SW_UINT32, 4, SW_PARAM_IN, "Port ID"), \ - SW_PARAM_DEF(SW_API_PT_BC_FILTER_GET, SW_ENABLE, 4, SW_PARAM_PTR|SW_PARAM_OUT, "Filter"), - -#define SW_API_CPU_PORT_STATUS_SET_DESC \ - SW_PARAM_DEF(SW_API_CPU_PORT_STATUS_SET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \ - SW_PARAM_DEF(SW_API_CPU_PORT_STATUS_SET, SW_ENABLE, 4, SW_PARAM_IN, "Cpu port"), - -#define SW_API_CPU_PORT_STATUS_GET_DESC \ - SW_PARAM_DEF(SW_API_CPU_PORT_STATUS_GET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \ - SW_PARAM_DEF(SW_API_CPU_PORT_STATUS_GET, SW_ENABLE, 4, SW_PARAM_PTR|SW_PARAM_OUT, "Cpu port"), - -#define SW_API_BC_TO_CPU_PORT_SET_DESC \ - SW_PARAM_DEF(SW_API_BC_TO_CPU_PORT_SET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \ - SW_PARAM_DEF(SW_API_BC_TO_CPU_PORT_SET, SW_ENABLE, 4, SW_PARAM_IN, "ToCpu"), - -#define SW_API_BC_TO_CPU_PORT_GET_DESC \ - SW_PARAM_DEF(SW_API_BC_TO_CPU_PORT_GET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \ - SW_PARAM_DEF(SW_API_BC_TO_CPU_PORT_GET, SW_ENABLE, 4, SW_PARAM_PTR|SW_PARAM_OUT, "ToCpu"), - -#define SW_API_PPPOE_CMD_SET_DESC \ - SW_PARAM_DEF(SW_API_PPPOE_CMD_SET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \ - SW_PARAM_DEF(SW_API_PPPOE_CMD_SET, SW_MACCMD, \ - sizeof(fal_fwd_cmd_t), SW_PARAM_IN, "Forwarding"), - -#define SW_API_PPPOE_CMD_GET_DESC \ - SW_PARAM_DEF(SW_API_PPPOE_CMD_GET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \ - SW_PARAM_DEF(SW_API_PPPOE_CMD_GET, SW_MACCMD, \ - sizeof(fal_fwd_cmd_t), SW_PARAM_PTR|SW_PARAM_OUT, "Forwarding"), - -#define SW_API_PPPOE_STATUS_SET_DESC \ - SW_PARAM_DEF(SW_API_PPPOE_STATUS_SET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \ - SW_PARAM_DEF(SW_API_PPPOE_STATUS_SET, SW_ENABLE, 4, SW_PARAM_IN, "PPPOE"), - -#define SW_API_PPPOE_STATUS_GET_DESC \ - SW_PARAM_DEF(SW_API_PPPOE_STATUS_GET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \ - SW_PARAM_DEF(SW_API_PPPOE_STATUS_GET, SW_ENABLE, 4, SW_PARAM_PTR|SW_PARAM_OUT, "PPPOE"), - -#define SW_API_PT_DHCP_SET_DESC \ - SW_PARAM_DEF(SW_API_PT_DHCP_SET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \ - SW_PARAM_DEF(SW_API_PT_DHCP_SET, SW_UINT32, 4, SW_PARAM_IN, "Port ID"), \ - SW_PARAM_DEF(SW_API_PT_DHCP_SET, SW_ENABLE, 4, SW_PARAM_IN, "DHCP"), - -#define SW_API_PT_DHCP_GET_DESC \ - SW_PARAM_DEF(SW_API_PT_DHCP_GET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \ - SW_PARAM_DEF(SW_API_PT_DHCP_GET, SW_UINT32, 4, SW_PARAM_IN, "Port ID"), \ - SW_PARAM_DEF(SW_API_PT_DHCP_GET, SW_ENABLE, 4, SW_PARAM_PTR|SW_PARAM_OUT, "DHCP"), - -#define SW_API_ARP_CMD_SET_DESC \ - SW_PARAM_DEF(SW_API_ARP_CMD_SET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \ - SW_PARAM_DEF(SW_API_ARP_CMD_SET, SW_MACCMD, \ - sizeof(fal_fwd_cmd_t), SW_PARAM_IN, "cmd"), - -#define SW_API_ARP_CMD_GET_DESC \ - SW_PARAM_DEF(SW_API_ARP_CMD_GET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \ - SW_PARAM_DEF(SW_API_ARP_CMD_GET, SW_MACCMD, \ - sizeof(fal_fwd_cmd_t), SW_PARAM_PTR|SW_PARAM_OUT, "cmd"), - -#define SW_API_EAPOL_CMD_SET_DESC \ - SW_PARAM_DEF(SW_API_EAPOL_CMD_SET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \ - SW_PARAM_DEF(SW_API_EAPOL_CMD_SET, SW_MACCMD, \ - sizeof(fal_fwd_cmd_t), SW_PARAM_IN, "cmd"), - -#define SW_API_EAPOL_CMD_GET_DESC \ - SW_PARAM_DEF(SW_API_EAPOL_CMD_GET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \ - SW_PARAM_DEF(SW_API_EAPOL_CMD_GET, SW_MACCMD, \ - sizeof(fal_fwd_cmd_t), SW_PARAM_PTR|SW_PARAM_OUT, "cmd"), - -#define SW_API_PPPOE_SESSION_ADD_DESC \ - SW_PARAM_DEF(SW_API_PPPOE_SESSION_ADD, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \ - SW_PARAM_DEF(SW_API_PPPOE_SESSION_ADD, SW_UINT32, 4, SW_PARAM_IN, "Session ID"), \ - SW_PARAM_DEF(SW_API_PPPOE_SESSION_ADD, SW_ENABLE, 4, SW_PARAM_IN, "StripHdr"), - -#define SW_API_PPPOE_SESSION_DEL_DESC \ - SW_PARAM_DEF(SW_API_PPPOE_SESSION_DEL, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \ - SW_PARAM_DEF(SW_API_PPPOE_SESSION_DEL, SW_UINT32, 4, SW_PARAM_IN, "Session ID"), - -#define SW_API_PPPOE_SESSION_GET_DESC \ - SW_PARAM_DEF(SW_API_PPPOE_SESSION_GET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \ - SW_PARAM_DEF(SW_API_PPPOE_SESSION_GET, SW_UINT32, 4, SW_PARAM_IN, "Session ID"), \ - SW_PARAM_DEF(SW_API_PPPOE_SESSION_GET, SW_ENABLE, 4, SW_PARAM_PTR|SW_PARAM_OUT, "StripHdr"), - -#define SW_API_EAPOL_STATUS_SET_DESC \ - SW_PARAM_DEF(SW_API_EAPOL_STATUS_SET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \ - SW_PARAM_DEF(SW_API_EAPOL_STATUS_SET, SW_UINT32, 4, SW_PARAM_IN, "Port ID"), \ - SW_PARAM_DEF(SW_API_EAPOL_STATUS_SET, SW_ENABLE, 4, SW_PARAM_IN, "Enable"), - -#define SW_API_EAPOL_STATUS_GET_DESC \ - SW_PARAM_DEF(SW_API_EAPOL_STATUS_GET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \ - SW_PARAM_DEF(SW_API_EAPOL_STATUS_GET, SW_UINT32, 4, SW_PARAM_IN, "Port ID"), \ - SW_PARAM_DEF(SW_API_EAPOL_STATUS_GET, SW_ENABLE, 4, SW_PARAM_PTR|SW_PARAM_OUT, "Enable"), - -#define SW_API_RIPV1_STATUS_SET_DESC \ - SW_PARAM_DEF(SW_API_RIPV1_STATUS_SET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \ - SW_PARAM_DEF(SW_API_RIPV1_STATUS_SET, SW_ENABLE, 4, SW_PARAM_IN, "Enable"), - -#define SW_API_RIPV1_STATUS_GET_DESC \ - SW_PARAM_DEF(SW_API_RIPV1_STATUS_GET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \ - SW_PARAM_DEF(SW_API_RIPV1_STATUS_GET, SW_ENABLE, 4, SW_PARAM_PTR|SW_PARAM_OUT, "Enable"), - -#define SW_API_PT_ARP_REQ_STATUS_SET_DESC \ - SW_PARAM_DEF(SW_API_PT_ARP_REQ_STATUS_SET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \ - SW_PARAM_DEF(SW_API_PT_ARP_REQ_STATUS_SET, SW_UINT32, 4, SW_PARAM_IN, "Port ID"), \ - SW_PARAM_DEF(SW_API_PT_ARP_REQ_STATUS_SET, SW_ENABLE, 4, SW_PARAM_IN, "ARP Req acknowledge"), - -#define SW_API_PT_ARP_REQ_STATUS_GET_DESC \ - SW_PARAM_DEF(SW_API_PT_ARP_REQ_STATUS_GET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \ - SW_PARAM_DEF(SW_API_PT_ARP_REQ_STATUS_GET, SW_UINT32, 4, SW_PARAM_IN, "Port ID"), \ - SW_PARAM_DEF(SW_API_PT_ARP_REQ_STATUS_GET, SW_ENABLE, 4, \ - SW_PARAM_PTR|SW_PARAM_OUT, "ARP Req acknowledge"), - -#define SW_API_PT_ARP_ACK_STATUS_SET_DESC \ - SW_PARAM_DEF(SW_API_PT_ARP_ACK_STATUS_SET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \ - SW_PARAM_DEF(SW_API_PT_ARP_ACK_STATUS_SET, SW_UINT32, 4, SW_PARAM_IN, "Port ID"), \ - SW_PARAM_DEF(SW_API_PT_ARP_ACK_STATUS_SET, SW_ENABLE, 4, SW_PARAM_IN, "ARP Ack acknowledge"), - -#define SW_API_PT_ARP_ACK_STATUS_GET_DESC \ - SW_PARAM_DEF(SW_API_PT_ARP_ACK_STATUS_GET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \ - SW_PARAM_DEF(SW_API_PT_ARP_ACK_STATUS_GET, SW_UINT32, 4, SW_PARAM_IN, "Port ID"), \ - SW_PARAM_DEF(SW_API_PT_ARP_ACK_STATUS_GET, SW_ENABLE, 4, \ - SW_PARAM_PTR|SW_PARAM_OUT, "ARP Ack acknowledge"), - -#define SW_API_PPPOE_SESSION_TABLE_ADD_DESC \ - SW_PARAM_DEF(SW_API_PPPOE_SESSION_TABLE_ADD, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \ - SW_PARAM_DEF(SW_API_PPPOE_SESSION_TABLE_ADD, SW_PPPOE, \ - sizeof(fal_pppoe_session_t), SW_PARAM_PTR|SW_PARAM_IN|SW_PARAM_OUT, "Session"), - -#define SW_API_PPPOE_SESSION_TABLE_DEL_DESC \ - SW_PARAM_DEF(SW_API_PPPOE_SESSION_TABLE_DEL, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \ - SW_PARAM_DEF(SW_API_PPPOE_SESSION_TABLE_DEL, SW_PPPOE, \ - sizeof(fal_pppoe_session_t), SW_PARAM_PTR|SW_PARAM_IN, "Session"), - -#define SW_API_PPPOE_SESSION_TABLE_GET_DESC \ - SW_PARAM_DEF(SW_API_PPPOE_SESSION_TABLE_GET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \ - SW_PARAM_DEF(SW_API_PPPOE_SESSION_TABLE_GET, SW_PPPOE, \ - sizeof(fal_pppoe_session_t), SW_PARAM_PTR|SW_PARAM_IN|SW_PARAM_OUT, "Session"), - -#define SW_API_PPPOE_SESSION_ID_SET_DESC \ - SW_PARAM_DEF(SW_API_PPPOE_SESSION_ID_SET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \ - SW_PARAM_DEF(SW_API_PPPOE_SESSION_ID_SET, SW_UINT32, 4, SW_PARAM_IN, "Index"), \ - SW_PARAM_DEF(SW_API_PPPOE_SESSION_ID_SET, SW_UINT32, 4, SW_PARAM_IN, "ID"), - -#define SW_API_PPPOE_SESSION_ID_GET_DESC \ - SW_PARAM_DEF(SW_API_PPPOE_SESSION_ID_GET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \ - SW_PARAM_DEF(SW_API_PPPOE_SESSION_ID_GET, SW_UINT32, 4, SW_PARAM_IN, "Index"), \ - SW_PARAM_DEF(SW_API_PPPOE_SESSION_ID_GET, SW_UINT32, 4, SW_PARAM_PTR|SW_PARAM_OUT, "ID"), - -#define SW_API_INTR_MASK_SET_DESC \ - SW_PARAM_DEF(SW_API_INTR_MASK_SET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \ - SW_PARAM_DEF(SW_API_INTR_MASK_SET, SW_UINT32, 4, SW_PARAM_IN, "Mask"), - -#define SW_API_INTR_MASK_GET_DESC \ - SW_PARAM_DEF(SW_API_INTR_MASK_GET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \ - SW_PARAM_DEF(SW_API_INTR_MASK_GET, SW_UINT32, 4, SW_PARAM_PTR|SW_PARAM_OUT, "Mask"), - -#define SW_API_INTR_STATUS_GET_DESC \ - SW_PARAM_DEF(SW_API_INTR_STATUS_GET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \ - SW_PARAM_DEF(SW_API_INTR_STATUS_GET, SW_UINT32, 4, SW_PARAM_PTR|SW_PARAM_OUT, "Status"), - -#define SW_API_INTR_STATUS_CLEAR_DESC \ - SW_PARAM_DEF(SW_API_INTR_STATUS_CLEAR, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \ - SW_PARAM_DEF(SW_API_INTR_STATUS_CLEAR, SW_UINT32, 4, SW_PARAM_IN, "Status"), - -#define SW_API_INTR_PORT_LINK_MASK_SET_DESC \ - SW_PARAM_DEF(SW_API_INTR_PORT_LINK_MASK_SET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \ - SW_PARAM_DEF(SW_API_INTR_PORT_LINK_MASK_SET, SW_UINT32, 4, SW_PARAM_IN, "Port ID"), \ - SW_PARAM_DEF(SW_API_INTR_PORT_LINK_MASK_SET, SW_UINT32, 4, SW_PARAM_IN, "Mask"), - -#define SW_API_INTR_PORT_LINK_MASK_GET_DESC \ - SW_PARAM_DEF(SW_API_INTR_PORT_LINK_MASK_GET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \ - SW_PARAM_DEF(SW_API_INTR_PORT_LINK_MASK_GET, SW_UINT32, 4, SW_PARAM_IN, "Port ID"), \ - SW_PARAM_DEF(SW_API_INTR_PORT_LINK_MASK_GET, SW_UINT32, 4, SW_PARAM_PTR|SW_PARAM_OUT, "Mask"), - -#define SW_API_INTR_PORT_LINK_STATUS_GET_DESC \ - SW_PARAM_DEF(SW_API_INTR_PORT_LINK_STATUS_GET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \ - SW_PARAM_DEF(SW_API_INTR_PORT_LINK_STATUS_GET, SW_UINT32, 4, SW_PARAM_IN, "Port ID"), \ - SW_PARAM_DEF(SW_API_INTR_PORT_LINK_STATUS_GET, SW_UINT32, 4, \ - SW_PARAM_PTR|SW_PARAM_OUT, "Status"), - -#define SW_API_INTR_MASK_MAC_LINKCHG_SET_DESC \ - SW_PARAM_DEF(SW_API_INTR_MASK_MAC_LINKCHG_SET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \ - SW_PARAM_DEF(SW_API_INTR_MASK_MAC_LINKCHG_SET, SW_UINT32, 4, SW_PARAM_IN, "Port ID"), \ - SW_PARAM_DEF(SW_API_INTR_MASK_MAC_LINKCHG_SET, SW_ENABLE, 4, SW_PARAM_IN, "Enable"), - -#define SW_API_INTR_MASK_MAC_LINKCHG_GET_DESC \ - SW_PARAM_DEF(SW_API_INTR_MASK_MAC_LINKCHG_GET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \ - SW_PARAM_DEF(SW_API_INTR_MASK_MAC_LINKCHG_GET, SW_UINT32, 4, SW_PARAM_IN, "Port ID"), \ - SW_PARAM_DEF(SW_API_INTR_MASK_MAC_LINKCHG_GET, SW_ENABLE, 4, \ - SW_PARAM_PTR|SW_PARAM_OUT, "Enable"), - -#define SW_API_INTR_STATUS_MAC_LINKCHG_GET_DESC \ - SW_PARAM_DEF(SW_API_INTR_STATUS_MAC_LINKCHG_GET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \ - SW_PARAM_DEF(SW_API_INTR_STATUS_MAC_LINKCHG_GET, SW_PBMP, \ - sizeof(fal_pbmp_t), SW_PARAM_PTR|SW_PARAM_OUT, "Intr Port Bitmap"), - -#define SW_API_INTR_STATUS_MAC_LINKCHG_CLEAR_DESC \ - SW_PARAM_DEF(SW_API_INTR_STATUS_MAC_LINKCHG_CLEAR, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), - -#define SW_API_CPU_VID_EN_SET_DESC \ - SW_PARAM_DEF(SW_API_CPU_VID_EN_SET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \ - SW_PARAM_DEF(SW_API_CPU_VID_EN_SET, SW_ENABLE, 4, SW_PARAM_IN, "Cpu vid"), - -#define SW_API_CPU_VID_EN_GET_DESC \ - SW_PARAM_DEF(SW_API_CPU_VID_EN_GET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \ - SW_PARAM_DEF(SW_API_CPU_VID_EN_GET, SW_ENABLE, 4, SW_PARAM_PTR|SW_PARAM_OUT, "Cpu vid"), - -#define SW_API_RTD_PPPOE_EN_SET_DESC \ - SW_PARAM_DEF(SW_API_RTD_PPPOE_EN_SET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \ - SW_PARAM_DEF(SW_API_RTD_PPPOE_EN_SET, SW_ENABLE, 4, SW_PARAM_IN, "RTD PPPoE"), - -#define SW_API_RTD_PPPOE_EN_GET_DESC \ - SW_PARAM_DEF(SW_API_RTD_PPPOE_EN_GET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \ - SW_PARAM_DEF(SW_API_RTD_PPPOE_EN_GET, SW_ENABLE, 4, SW_PARAM_PTR|SW_PARAM_OUT, "RTD PPPoE"), - -#define SW_API_PPPOE_EN_SET_DESC \ - SW_PARAM_DEF(SW_API_PPPOE_EN_SET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \ - SW_PARAM_DEF(SW_API_PPPOE_EN_SET, SW_UINT32, 4, SW_PARAM_IN, "L3 Interface"), \ - SW_PARAM_DEF(SW_API_PPPOE_EN_SET, SW_ENABLE, 4, SW_PARAM_IN, "Enable"), - -#define SW_API_PPPOE_EN_GET_DESC \ - SW_PARAM_DEF(SW_API_PPPOE_EN_GET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \ - SW_PARAM_DEF(SW_API_PPPOE_EN_GET, SW_UINT32, 4, SW_PARAM_IN, "L3 Interface"), \ - SW_PARAM_DEF(SW_API_PPPOE_EN_GET, SW_ENABLE, 4, SW_PARAM_PTR|SW_PARAM_OUT, "Enable"), - -#define SW_API_GLOBAL_MACADDR_SET_DESC \ - SW_PARAM_DEF(SW_API_GLOBAL_MACADDR_SET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \ - SW_PARAM_DEF(SW_API_GLOBAL_MACADDR_SET, SW_MACADDR, \ - sizeof(fal_mac_addr_t), SW_PARAM_PTR|SW_PARAM_IN, "[Macaddr]:"), - -#define SW_API_GLOBAL_MACADDR_GET_DESC \ - SW_PARAM_DEF(SW_API_GLOBAL_MACADDR_GET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \ - SW_PARAM_DEF(SW_API_GLOBAL_MACADDR_GET, SW_MACADDR, \ - sizeof(fal_mac_addr_t), SW_PARAM_PTR|SW_PARAM_OUT, "[Macaddr]:"), - -#define SW_API_LLDP_STATUS_SET_DESC \ - SW_PARAM_DEF(SW_API_LLDP_STATUS_SET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \ - SW_PARAM_DEF(SW_API_LLDP_STATUS_SET, SW_ENABLE, 4, SW_PARAM_IN, "LLDP"), - -#define SW_API_LLDP_STATUS_GET_DESC \ - SW_PARAM_DEF(SW_API_LLDP_STATUS_GET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \ - SW_PARAM_DEF(SW_API_LLDP_STATUS_GET, SW_ENABLE, 4, SW_PARAM_PTR|SW_PARAM_OUT, "LLDP"), - -#define SW_API_FRAME_CRC_RESERVE_SET_DESC \ - SW_PARAM_DEF(SW_API_FRAME_CRC_RESERVE_SET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \ - SW_PARAM_DEF(SW_API_FRAME_CRC_RESERVE_SET, SW_ENABLE, 4, SW_PARAM_IN, "Enable"), - -#define SW_API_FRAME_CRC_RESERVE_GET_DESC \ - SW_PARAM_DEF(SW_API_FRAME_CRC_RESERVE_GET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \ - SW_PARAM_DEF(SW_API_FRAME_CRC_RESERVE_GET, SW_ENABLE, 4, SW_PARAM_PTR|SW_PARAM_OUT, "Enable"), - -#define SW_API_DEBUG_PORT_COUNTER_ENABLE_DESC \ - SW_PARAM_DEF(SW_API_DEBUG_PORT_COUNTER_ENABLE, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \ - SW_PARAM_DEF(SW_API_DEBUG_PORT_COUNTER_ENABLE, SW_UINT32, 4, SW_PARAM_IN, "Port ID"), \ - SW_PARAM_DEF(SW_API_DEBUG_PORT_COUNTER_ENABLE, SW_DEBUG_COUNTER_EN, \ - sizeof(fal_counter_en_t), SW_PARAM_PTR|SW_PARAM_IN, "enable"), - -#define SW_API_DEBUG_PORT_COUNTER_STATUS_GET_DESC \ - SW_PARAM_DEF(SW_API_DEBUG_PORT_COUNTER_STATUS_GET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \ - SW_PARAM_DEF(SW_API_DEBUG_PORT_COUNTER_STATUS_GET, SW_UINT32, 4, SW_PARAM_IN, "Port ID"), \ - SW_PARAM_DEF(SW_API_DEBUG_PORT_COUNTER_STATUS_GET, SW_DEBUG_COUNTER_EN, \ - sizeof(fal_counter_en_t), SW_PARAM_PTR|SW_PARAM_OUT, "enable"), - -#define SW_API_LED_PATTERN_SET_DESC \ - SW_PARAM_DEF(SW_API_LED_PATTERN_SET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"),\ - SW_PARAM_DEF(SW_API_LED_PATTERN_SET, SW_UINT32, 4, SW_PARAM_IN, "Pattern Group"),\ - SW_PARAM_DEF(SW_API_LED_PATTERN_SET, SW_UINT32, 4, SW_PARAM_IN, "Pattern ID"),\ - SW_PARAM_DEF(SW_API_LED_PATTERN_SET, SW_LEDPATTERN, \ - sizeof(led_ctrl_pattern_t), SW_PARAM_PTR|SW_PARAM_IN, "Pattern"), - -#define SW_API_LED_PATTERN_GET_DESC \ - SW_PARAM_DEF(SW_API_LED_PATTERN_GET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"),\ - SW_PARAM_DEF(SW_API_LED_PATTERN_GET, SW_UINT32, 4, SW_PARAM_IN, "Pattern Group"),\ - SW_PARAM_DEF(SW_API_LED_PATTERN_GET, SW_UINT32, 4, SW_PARAM_IN, "Pattern ID"),\ - SW_PARAM_DEF(SW_API_LED_PATTERN_GET, SW_LEDPATTERN, \ - sizeof(led_ctrl_pattern_t), SW_PARAM_PTR|SW_PARAM_OUT, "Pattern"), - -/*qca808x_start*/ -#define SW_API_PHY_GET_DESC \ - SW_PARAM_DEF(SW_API_PHY_GET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"),\ - SW_PARAM_DEF(SW_API_PHY_GET, SW_UINT32, 4, SW_PARAM_IN, "Phy ID"),\ - SW_PARAM_DEF(SW_API_PHY_GET, SW_UINT32, 4, SW_PARAM_IN, "Reg ID"),\ - SW_PARAM_DEF(SW_API_PHY_GET, SW_UINT16, 2, SW_PARAM_PTR|SW_PARAM_OUT, "Data"), - - -#define SW_API_PHY_SET_DESC \ - SW_PARAM_DEF(SW_API_PHY_SET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"),\ - SW_PARAM_DEF(SW_API_PHY_SET, SW_UINT32, 4, SW_PARAM_IN, "Phy ID"),\ - SW_PARAM_DEF(SW_API_PHY_SET, SW_UINT32, 4, SW_PARAM_IN, "Reg ID"),\ - SW_PARAM_DEF(SW_API_PHY_SET, SW_UINT16, 2, SW_PARAM_IN, "Data"), -/*qca808x_end*/ - -#define SW_API_REG_GET_DESC \ - SW_PARAM_DEF(SW_API_REG_GET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"),\ - SW_PARAM_DEF(SW_API_REG_GET, SW_UINT32, 4, SW_PARAM_IN, "Reg Addr"),\ - SW_PARAM_DEF(SW_API_REG_GET, SW_UINT32, 4, SW_PARAM_PTR|SW_PARAM_OUT, "Data"),\ - SW_PARAM_DEF(SW_API_REG_GET, SW_UINT32, 4, SW_PARAM_IN, "Data Len"), - -#define SW_API_REG_SET_DESC \ - SW_PARAM_DEF(SW_API_REG_SET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"),\ - SW_PARAM_DEF(SW_API_REG_SET, SW_UINT32, 4, SW_PARAM_IN, "Reg Addr"),\ - SW_PARAM_DEF(SW_API_REG_SET, SW_UINT32, 4, SW_PARAM_PTR|SW_PARAM_IN, "Data"),\ - SW_PARAM_DEF(SW_API_REG_SET, SW_UINT32, 4, SW_PARAM_IN, "Data Len"), - -#define SW_API_PSGMII_REG_GET_DESC \ - SW_PARAM_DEF(SW_API_PSGMII_REG_GET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"),\ - SW_PARAM_DEF(SW_API_PSGMII_REG_GET, SW_UINT32, 4, SW_PARAM_IN, "Reg Addr"),\ - SW_PARAM_DEF(SW_API_PSGMII_REG_GET, SW_UINT32, 4, SW_PARAM_PTR|SW_PARAM_OUT, "Data"),\ - SW_PARAM_DEF(SW_API_PSGMII_REG_GET, SW_UINT32, 4, SW_PARAM_IN, "Data Len"), - -#define SW_API_PSGMII_REG_SET_DESC \ - SW_PARAM_DEF(SW_API_PSGMII_REG_SET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"),\ - SW_PARAM_DEF(SW_API_PSGMII_REG_SET, SW_UINT32, 4, SW_PARAM_IN, "Reg Addr"),\ - SW_PARAM_DEF(SW_API_PSGMII_REG_SET, SW_UINT32, 4, SW_PARAM_PTR|SW_PARAM_IN, "Data"),\ - SW_PARAM_DEF(SW_API_PSGMII_REG_SET, SW_UINT32, 4, SW_PARAM_IN, "Data Len"), - -#define SW_API_REG_FIELD_GET_DESC \ - SW_PARAM_DEF(SW_API_REG_FIELD_GET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"),\ - SW_PARAM_DEF(SW_API_REG_FIELD_GET, SW_UINT32, 4, SW_PARAM_IN, "Reg Addr"),\ - SW_PARAM_DEF(SW_API_REG_FIELD_GET, SW_UINT32, 4, SW_PARAM_IN, "Bit Offset"),\ - SW_PARAM_DEF(SW_API_REG_FIELD_GET, SW_UINT32, 4, SW_PARAM_IN, "Field Len"),\ - SW_PARAM_DEF(SW_API_REG_FIELD_GET, SW_UINT32, 4, SW_PARAM_PTR|SW_PARAM_OUT, "Data"),\ - SW_PARAM_DEF(SW_API_REG_FIELD_GET, SW_UINT32, 4, SW_PARAM_IN, "Data Len"), - -#define SW_API_REG_FIELD_SET_DESC \ - SW_PARAM_DEF(SW_API_REG_FIELD_SET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"),\ - SW_PARAM_DEF(SW_API_REG_FIELD_SET, SW_UINT32, 4, SW_PARAM_IN, "Reg Addr"),\ - SW_PARAM_DEF(SW_API_REG_FIELD_SET, SW_UINT32, 4, SW_PARAM_IN, "Bit Offset"),\ - SW_PARAM_DEF(SW_API_REG_FIELD_SET, SW_UINT32, 4, SW_PARAM_IN, "Field Len"),\ - SW_PARAM_DEF(SW_API_REG_FIELD_SET, SW_UINT32, 4, SW_PARAM_PTR|SW_PARAM_IN, "Data"),\ - SW_PARAM_DEF(SW_API_REG_FIELD_SET, SW_UINT32, 4, SW_PARAM_IN, "Data Len"), - -#define SW_API_REG_DUMP_DESC \ - SW_PARAM_DEF(SW_API_REG_DUMP, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \ - SW_PARAM_DEF(SW_API_REG_DUMP, SW_UINT32, 4, SW_PARAM_IN, "Register group idx"), \ - SW_PARAM_DEF(SW_API_REG_DUMP, SW_REG_DUMP, \ - sizeof(fal_reg_dump_t), SW_PARAM_PTR|SW_PARAM_OUT, \ - "Register dump"), - -#define SW_API_DBG_REG_DUMP_DESC \ - SW_PARAM_DEF(SW_API_DBG_REG_DUMP, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \ - SW_PARAM_DEF(SW_API_DBG_REG_DUMP, SW_DBG_REG_DUMP, \ - sizeof(fal_debug_reg_dump_t), SW_PARAM_PTR|SW_PARAM_OUT, \ - "Debug Register dump"), - -#define SW_API_DBG_PSGMII_SELF_TEST_DESC \ - SW_PARAM_DEF(SW_API_DBG_PSGMII_SELF_TEST, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"),\ - SW_PARAM_DEF(SW_API_DBG_PSGMII_SELF_TEST, SW_ENABLE, \ - sizeof(a_bool_t), SW_PARAM_IN, "enable"),\ - SW_PARAM_DEF(SW_API_DBG_PSGMII_SELF_TEST, SW_UINT32, 4, SW_PARAM_IN, "times"),\ - SW_PARAM_DEF(SW_API_DBG_PSGMII_SELF_TEST, SW_UINT32, 4, SW_PARAM_PTR|SW_PARAM_OUT, "Status"), - -#define SW_API_PHY_DUMP_DESC \ - SW_PARAM_DEF(SW_API_PHY_DUMP, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \ - SW_PARAM_DEF(SW_API_PHY_DUMP, SW_UINT32, 4, SW_PARAM_IN, "Phy ID"),\ - SW_PARAM_DEF(SW_API_PHY_DUMP, SW_UINT32, 4, SW_PARAM_IN, "Register group idx"), \ - SW_PARAM_DEF(SW_API_PHY_DUMP, SW_PHY_DUMP, \ - sizeof(fal_phy_dump_t), SW_PARAM_PTR|SW_PARAM_OUT, \ - "PHY dump"), - - -#define SW_API_UNIPHY_REG_GET_DESC \ - SW_PARAM_DEF(SW_API_UNIPHY_REG_GET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"),\ - SW_PARAM_DEF(SW_API_UNIPHY_REG_GET, SW_UINT32, 4, SW_PARAM_IN, "Reg Index"),\ - SW_PARAM_DEF(SW_API_UNIPHY_REG_GET, SW_UINT32, 4, SW_PARAM_IN, "Reg Addr"),\ - SW_PARAM_DEF(SW_API_UNIPHY_REG_GET, SW_UINT32, 4, SW_PARAM_PTR|SW_PARAM_OUT, "Data"),\ - SW_PARAM_DEF(SW_API_UNIPHY_REG_GET, SW_UINT32, 4, SW_PARAM_IN, "Data Len"), - -#define SW_API_UNIPHY_REG_SET_DESC \ - SW_PARAM_DEF(SW_API_UNIPHY_REG_SET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"),\ - SW_PARAM_DEF(SW_API_UNIPHY_REG_SET, SW_UINT32, 4, SW_PARAM_IN, "Reg Index"),\ - SW_PARAM_DEF(SW_API_UNIPHY_REG_SET, SW_UINT32, 4, SW_PARAM_IN, "Reg Addr"),\ - SW_PARAM_DEF(SW_API_UNIPHY_REG_SET, SW_UINT32, 4, SW_PARAM_PTR|SW_PARAM_IN, "Data"),\ - SW_PARAM_DEF(SW_API_UNIPHY_REG_SET, SW_UINT32, 4, SW_PARAM_IN, "Data Len"), - -#define SW_API_COSMAP_DSCP_TO_PRI_SET_DESC \ - SW_PARAM_DEF(SW_API_COSMAP_DSCP_TO_PRI_SET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \ - SW_PARAM_DEF(SW_API_COSMAP_DSCP_TO_PRI_SET, SW_UINT32, 4, SW_PARAM_IN, "DSCP"), \ - SW_PARAM_DEF(SW_API_COSMAP_DSCP_TO_PRI_SET, SW_UINT32, 4, SW_PARAM_IN, "Priority"), - -#define SW_API_COSMAP_DSCP_TO_PRI_GET_DESC \ - SW_PARAM_DEF(SW_API_COSMAP_DSCP_TO_PRI_GET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \ - SW_PARAM_DEF(SW_API_COSMAP_DSCP_TO_PRI_GET, SW_UINT32, 4, SW_PARAM_IN, "DSCP"), \ - SW_PARAM_DEF(SW_API_COSMAP_DSCP_TO_PRI_GET, SW_UINT32, 4, SW_PARAM_PTR|SW_PARAM_OUT, "Priority"), - -#define SW_API_COSMAP_DSCP_TO_DP_SET_DESC \ - SW_PARAM_DEF(SW_API_COSMAP_DSCP_TO_DP_SET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \ - SW_PARAM_DEF(SW_API_COSMAP_DSCP_TO_DP_SET, SW_UINT32, 4, SW_PARAM_IN, "DSCP"), \ - SW_PARAM_DEF(SW_API_COSMAP_DSCP_TO_DP_SET, SW_UINT32, 4, SW_PARAM_IN, "DP"), - -#define SW_API_COSMAP_DSCP_TO_DP_GET_DESC \ - SW_PARAM_DEF(SW_API_COSMAP_DSCP_TO_DP_GET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \ - SW_PARAM_DEF(SW_API_COSMAP_DSCP_TO_DP_GET, SW_UINT32, 4, SW_PARAM_IN, "DSCP"), \ - SW_PARAM_DEF(SW_API_COSMAP_DSCP_TO_DP_GET, SW_UINT32, 4, SW_PARAM_PTR|SW_PARAM_OUT, "DP"), - -#define SW_API_COSMAP_UP_TO_PRI_SET_DESC \ - SW_PARAM_DEF(SW_API_COSMAP_UP_TO_PRI_SET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \ - SW_PARAM_DEF(SW_API_COSMAP_UP_TO_PRI_SET, SW_UINT32, 4, SW_PARAM_IN, "Dot1p"), \ - SW_PARAM_DEF(SW_API_COSMAP_UP_TO_PRI_SET, SW_UINT32, 4, SW_PARAM_IN, "Priority"), - -#define SW_API_COSMAP_UP_TO_PRI_GET_DESC \ - SW_PARAM_DEF(SW_API_COSMAP_UP_TO_PRI_GET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \ - SW_PARAM_DEF(SW_API_COSMAP_UP_TO_PRI_GET, SW_UINT32, 4, SW_PARAM_IN, "Dot1p"), \ - SW_PARAM_DEF(SW_API_COSMAP_UP_TO_PRI_GET, SW_UINT32, 4, SW_PARAM_PTR|SW_PARAM_OUT, "Priority"), - -#define SW_API_COSMAP_UP_TO_DP_SET_DESC \ - SW_PARAM_DEF(SW_API_COSMAP_UP_TO_DP_SET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \ - SW_PARAM_DEF(SW_API_COSMAP_UP_TO_DP_SET, SW_UINT32, 4, SW_PARAM_IN, "Dot1p"), \ - SW_PARAM_DEF(SW_API_COSMAP_UP_TO_DP_SET, SW_UINT32, 4, SW_PARAM_IN, "DP"), - -#define SW_API_COSMAP_UP_TO_DP_GET_DESC \ - SW_PARAM_DEF(SW_API_COSMAP_UP_TO_DP_GET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \ - SW_PARAM_DEF(SW_API_COSMAP_UP_TO_DP_GET, SW_UINT32, 4, SW_PARAM_IN, "Dot1p"), \ - SW_PARAM_DEF(SW_API_COSMAP_UP_TO_DP_GET, SW_UINT32, 4, SW_PARAM_PTR|SW_PARAM_OUT, "DP"), - -#define SW_API_COSMAP_DSCP_TO_EHPRI_SET_DESC \ - SW_PARAM_DEF(SW_API_COSMAP_DSCP_TO_EHPRI_SET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \ - SW_PARAM_DEF(SW_API_COSMAP_DSCP_TO_EHPRI_SET, SW_UINT32, 4, SW_PARAM_IN, "DSCP"), \ - SW_PARAM_DEF(SW_API_COSMAP_DSCP_TO_EHPRI_SET, SW_UINT32, 4, SW_PARAM_IN, "Priority"), - -#define SW_API_COSMAP_DSCP_TO_EHPRI_GET_DESC \ - SW_PARAM_DEF(SW_API_COSMAP_DSCP_TO_EHPRI_GET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \ - SW_PARAM_DEF(SW_API_COSMAP_DSCP_TO_EHPRI_GET, SW_UINT32, 4, SW_PARAM_IN, "DSCP"), \ - SW_PARAM_DEF(SW_API_COSMAP_DSCP_TO_EHPRI_GET, SW_UINT32, 4, SW_PARAM_PTR|SW_PARAM_OUT, "Priority"), - -#define SW_API_COSMAP_DSCP_TO_EHDP_SET_DESC \ - SW_PARAM_DEF(SW_API_COSMAP_DSCP_TO_EHDP_SET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \ - SW_PARAM_DEF(SW_API_COSMAP_DSCP_TO_EHDP_SET, SW_UINT32, 4, SW_PARAM_IN, "DSCP"), \ - SW_PARAM_DEF(SW_API_COSMAP_DSCP_TO_EHDP_SET, SW_UINT32, 4, SW_PARAM_IN, "DP"), - -#define SW_API_COSMAP_DSCP_TO_EHDP_GET_DESC \ - SW_PARAM_DEF(SW_API_COSMAP_DSCP_TO_EHDP_GET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \ - SW_PARAM_DEF(SW_API_COSMAP_DSCP_TO_EHDP_GET, SW_UINT32, 4, SW_PARAM_IN, "DSCP"), \ - SW_PARAM_DEF(SW_API_COSMAP_DSCP_TO_EHDP_GET, SW_UINT32, 4, SW_PARAM_PTR|SW_PARAM_OUT, "DP"), - -#define SW_API_COSMAP_UP_TO_EHPRI_SET_DESC \ - SW_PARAM_DEF(SW_API_COSMAP_UP_TO_EHPRI_SET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \ - SW_PARAM_DEF(SW_API_COSMAP_UP_TO_EHPRI_SET, SW_UINT32, 4, SW_PARAM_IN, "Dot1p"), \ - SW_PARAM_DEF(SW_API_COSMAP_UP_TO_EHPRI_SET, SW_UINT32, 4, SW_PARAM_IN, "Priority"), - -#define SW_API_COSMAP_UP_TO_EHPRI_GET_DESC \ - SW_PARAM_DEF(SW_API_COSMAP_UP_TO_EHPRI_GET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \ - SW_PARAM_DEF(SW_API_COSMAP_UP_TO_EHPRI_GET, SW_UINT32, 4, SW_PARAM_IN, "Dot1p"), \ - SW_PARAM_DEF(SW_API_COSMAP_UP_TO_EHPRI_GET, SW_UINT32, 4, SW_PARAM_PTR|SW_PARAM_OUT, "Priority"), - -#define SW_API_COSMAP_UP_TO_EHDP_SET_DESC \ - SW_PARAM_DEF(SW_API_COSMAP_UP_TO_EHDP_SET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \ - SW_PARAM_DEF(SW_API_COSMAP_UP_TO_EHDP_SET, SW_UINT32, 4, SW_PARAM_IN, "Dot1p"), \ - SW_PARAM_DEF(SW_API_COSMAP_UP_TO_EHDP_SET, SW_UINT32, 4, SW_PARAM_IN, "DP"), - -#define SW_API_COSMAP_UP_TO_EHDP_GET_DESC \ - SW_PARAM_DEF(SW_API_COSMAP_UP_TO_EHDP_GET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \ - SW_PARAM_DEF(SW_API_COSMAP_UP_TO_EHDP_GET, SW_UINT32, 4, SW_PARAM_IN, "Dot1p"), \ - SW_PARAM_DEF(SW_API_COSMAP_UP_TO_EHDP_GET, SW_UINT32, 4, SW_PARAM_PTR|SW_PARAM_OUT, "DP"), - -#define SW_API_COSMAP_PRI_TO_QU_SET_DESC \ - SW_PARAM_DEF(SW_API_COSMAP_PRI_TO_QU_SET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \ - SW_PARAM_DEF(SW_API_COSMAP_PRI_TO_QU_SET, SW_UINT32, 4, SW_PARAM_IN, "Priority"), \ - SW_PARAM_DEF(SW_API_COSMAP_PRI_TO_QU_SET, SW_UINT32, 4, SW_PARAM_IN, "Queue"), - -#define SW_API_COSMAP_PRI_TO_QU_GET_DESC \ - SW_PARAM_DEF(SW_API_COSMAP_PRI_TO_QU_GET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \ - SW_PARAM_DEF(SW_API_COSMAP_PRI_TO_QU_GET, SW_UINT32, 4, SW_PARAM_IN, "Priority"), \ - SW_PARAM_DEF(SW_API_COSMAP_PRI_TO_QU_GET, SW_UINT32, 4, SW_PARAM_PTR|SW_PARAM_OUT, "Queue"), - -#define SW_API_COSMAP_PRI_TO_EHQU_SET_DESC \ - SW_PARAM_DEF(SW_API_COSMAP_PRI_TO_EHQU_SET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \ - SW_PARAM_DEF(SW_API_COSMAP_PRI_TO_EHQU_SET, SW_UINT32, 4, SW_PARAM_IN, "Priority"), \ - SW_PARAM_DEF(SW_API_COSMAP_PRI_TO_EHQU_SET, SW_UINT32, 4, SW_PARAM_IN, "Queue"), - -#define SW_API_COSMAP_PRI_TO_EHQU_GET_DESC \ - SW_PARAM_DEF(SW_API_COSMAP_PRI_TO_EHQU_GET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \ - SW_PARAM_DEF(SW_API_COSMAP_PRI_TO_EHQU_GET, SW_UINT32, 4, SW_PARAM_IN, "Priority"), \ - SW_PARAM_DEF(SW_API_COSMAP_PRI_TO_EHQU_GET, SW_UINT32, 4, SW_PARAM_PTR|SW_PARAM_OUT, "Queue"), - -#define SW_API_COSMAP_EG_REMARK_SET_DESC \ - SW_PARAM_DEF(SW_API_COSMAP_EG_REMARK_SET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \ - SW_PARAM_DEF(SW_API_COSMAP_EG_REMARK_SET, SW_UINT32, 4, SW_PARAM_IN, "Table ID"), \ - SW_PARAM_DEF(SW_API_COSMAP_EG_REMARK_SET, SW_REMARKENTRY, \ - sizeof(fal_egress_remark_table_t), SW_PARAM_IN|SW_PARAM_PTR, "Table Entry"), - -#define SW_API_COSMAP_EG_REMARK_GET_DESC \ - SW_PARAM_DEF(SW_API_COSMAP_EG_REMARK_GET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \ - SW_PARAM_DEF(SW_API_COSMAP_EG_REMARK_GET, SW_UINT32, 4, SW_PARAM_IN, "Table ID"), \ - SW_PARAM_DEF(SW_API_COSMAP_EG_REMARK_GET, SW_REMARKENTRY, \ - sizeof(fal_egress_remark_table_t), SW_PARAM_OUT|SW_PARAM_PTR, "Table Entry"), - - - -#define SW_API_SEC_NORM_SET_DESC \ - SW_PARAM_DEF(SW_API_SEC_NORM_SET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \ - SW_PARAM_DEF(SW_API_SEC_NORM_SET, SW_UINT32, 4, SW_PARAM_IN, "NormItem"), \ - SW_PARAM_DEF(SW_API_SEC_NORM_SET, SW_UINT32, 4, SW_PARAM_PTR|SW_PARAM_IN, "NormVal"), - -#define SW_API_SEC_NORM_GET_DESC \ - SW_PARAM_DEF(SW_API_SEC_NORM_GET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \ - SW_PARAM_DEF(SW_API_SEC_NORM_GET, SW_UINT32, 4, SW_PARAM_IN, "NormItem"), \ - SW_PARAM_DEF(SW_API_SEC_NORM_GET, SW_UINT32, 4, SW_PARAM_PTR|SW_PARAM_OUT, "NormVal"), - -#define SW_API_SEC_MAC_SET_DESC \ - SW_PARAM_DEF(SW_API_SEC_MAC_SET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \ - SW_PARAM_DEF(SW_API_SEC_MAC_SET, SW_SEC_MAC, 4, SW_PARAM_IN, "MAC related normalized item"), \ - SW_PARAM_DEF(SW_API_SEC_MAC_SET, SW_UINT32, 4, SW_PARAM_PTR|SW_PARAM_IN, "NormVal"), - -#define SW_API_SEC_MAC_GET_DESC \ - SW_PARAM_DEF(SW_API_SEC_MAC_GET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \ - SW_PARAM_DEF(SW_API_SEC_MAC_GET, SW_SEC_MAC, 4, SW_PARAM_IN, "MAC related normalized item"), \ - SW_PARAM_DEF(SW_API_SEC_MAC_GET, SW_UINT32, 4, SW_PARAM_PTR|SW_PARAM_OUT, "NormVal"), - -#define SW_API_SEC_IP_SET_DESC \ - SW_PARAM_DEF(SW_API_SEC_IP_SET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \ - SW_PARAM_DEF(SW_API_SEC_IP_SET, SW_SEC_IP, 4, SW_PARAM_IN, "IP related normalized item"), \ - SW_PARAM_DEF(SW_API_SEC_IP_SET, SW_UINT32, 4, SW_PARAM_PTR|SW_PARAM_IN, "NormVal"), - -#define SW_API_SEC_IP_GET_DESC \ - SW_PARAM_DEF(SW_API_SEC_IP_GET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \ - SW_PARAM_DEF(SW_API_SEC_IP_GET, SW_SEC_IP, 4, SW_PARAM_IN, "IP related normalized item"), \ - SW_PARAM_DEF(SW_API_SEC_IP_GET, SW_UINT32, 4, SW_PARAM_PTR|SW_PARAM_OUT, "NormVal"), - -#define SW_API_SEC_IP4_SET_DESC \ - SW_PARAM_DEF(SW_API_SEC_IP4_SET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \ - SW_PARAM_DEF(SW_API_SEC_IP4_SET, SW_SEC_IP4, 4, SW_PARAM_IN, "IP4 related normalized item"), \ - SW_PARAM_DEF(SW_API_SEC_IP4_SET, SW_UINT32, 4, SW_PARAM_PTR|SW_PARAM_IN, "NormVal"), - -#define SW_API_SEC_IP4_GET_DESC \ - SW_PARAM_DEF(SW_API_SEC_IP4_GET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \ - SW_PARAM_DEF(SW_API_SEC_IP4_GET, SW_SEC_IP4, 4, SW_PARAM_IN, "IP4 related normalized item"), \ - SW_PARAM_DEF(SW_API_SEC_IP4_GET, SW_UINT32, 4, SW_PARAM_PTR|SW_PARAM_OUT, "NormVal"), - -#define SW_API_SEC_IP6_SET_DESC \ - SW_PARAM_DEF(SW_API_SEC_IP6_SET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \ - SW_PARAM_DEF(SW_API_SEC_IP6_SET, SW_SEC_IP6, 4, SW_PARAM_IN, "IP6 related normalized item"), \ - SW_PARAM_DEF(SW_API_SEC_IP6_SET, SW_UINT32, 4, SW_PARAM_PTR|SW_PARAM_IN, "NormVal"), - -#define SW_API_SEC_IP6_GET_DESC \ - SW_PARAM_DEF(SW_API_SEC_IP6_GET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \ - SW_PARAM_DEF(SW_API_SEC_IP6_GET, SW_SEC_IP6, 4, SW_PARAM_IN, "IP6 related normalized item"), \ - SW_PARAM_DEF(SW_API_SEC_IP6_GET, SW_UINT32, 4, SW_PARAM_PTR|SW_PARAM_OUT, "NormVal"), - -#define SW_API_SEC_TCP_SET_DESC \ - SW_PARAM_DEF(SW_API_SEC_TCP_SET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \ - SW_PARAM_DEF(SW_API_SEC_TCP_SET, SW_SEC_TCP, 4, SW_PARAM_IN, "TCP related normalized item"), \ - SW_PARAM_DEF(SW_API_SEC_TCP_SET, SW_UINT32, 4, SW_PARAM_PTR|SW_PARAM_IN, "NormVal"), - -#define SW_API_SEC_TCP_GET_DESC \ - SW_PARAM_DEF(SW_API_SEC_TCP_GET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \ - SW_PARAM_DEF(SW_API_SEC_TCP_GET, SW_SEC_TCP, 4, SW_PARAM_IN, "TCP related normalized item"), \ - SW_PARAM_DEF(SW_API_SEC_TCP_GET, SW_UINT32, 4, SW_PARAM_PTR|SW_PARAM_OUT, "NormVal"), - -#define SW_API_SEC_UDP_SET_DESC \ - SW_PARAM_DEF(SW_API_SEC_UDP_SET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \ - SW_PARAM_DEF(SW_API_SEC_UDP_SET, SW_SEC_UDP, 4, SW_PARAM_IN, "UDP related normalized item"), \ - SW_PARAM_DEF(SW_API_SEC_UDP_SET, SW_UINT32, 4, SW_PARAM_PTR|SW_PARAM_IN, "NormVal"), - -#define SW_API_SEC_UDP_GET_DESC \ - SW_PARAM_DEF(SW_API_SEC_UDP_GET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \ - SW_PARAM_DEF(SW_API_SEC_UDP_GET, SW_SEC_UDP, 4, SW_PARAM_IN, "UDP related normalized item"), \ - SW_PARAM_DEF(SW_API_SEC_UDP_GET, SW_UINT32, 4, SW_PARAM_PTR|SW_PARAM_OUT, "NormVal"), - -#define SW_API_SEC_ICMP4_SET_DESC \ - SW_PARAM_DEF(SW_API_SEC_ICMP4_SET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \ - SW_PARAM_DEF(SW_API_SEC_ICMP4_SET, SW_SEC_ICMP4, 4, \ - SW_PARAM_IN, "ICMP4 related normalized item"), \ - SW_PARAM_DEF(SW_API_SEC_ICMP4_SET, SW_UINT32, 4, SW_PARAM_PTR|SW_PARAM_IN, "NormVal"), - -#define SW_API_SEC_ICMP4_GET_DESC \ - SW_PARAM_DEF(SW_API_SEC_ICMP4_GET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \ - SW_PARAM_DEF(SW_API_SEC_ICMP4_GET, SW_SEC_ICMP4, 4, \ - SW_PARAM_IN, "ICMP4 related normalized item"), \ - SW_PARAM_DEF(SW_API_SEC_ICMP4_GET, SW_UINT32, 4, SW_PARAM_PTR|SW_PARAM_OUT, "NormVal"), - -#define SW_API_SEC_ICMP6_SET_DESC \ - SW_PARAM_DEF(SW_API_SEC_ICMP6_SET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \ - SW_PARAM_DEF(SW_API_SEC_ICMP6_SET, SW_SEC_ICMP6, 4, \ - SW_PARAM_IN, "ICMP6 related normalized item"), \ - SW_PARAM_DEF(SW_API_SEC_ICMP6_SET, SW_UINT32, 4, SW_PARAM_PTR|SW_PARAM_IN, "NormVal"), - -#define SW_API_SEC_ICMP6_GET_DESC \ - SW_PARAM_DEF(SW_API_SEC_ICMP6_GET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \ - SW_PARAM_DEF(SW_API_SEC_ICMP6_GET, SW_SEC_ICMP6, 4, \ - SW_PARAM_IN, "ICMP6 related normalized item"), \ - SW_PARAM_DEF(SW_API_SEC_ICMP6_GET, SW_UINT32, 4, SW_PARAM_PTR|SW_PARAM_OUT, "NormVal"), - -#define SW_API_SEC_L3_PARSER_CTRL_GET_DESC \ - SW_PARAM_DEF(SW_API_SEC_L3_PARSER_CTRL_GET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \ - SW_PARAM_DEF(SW_API_SEC_L3_PARSER_CTRL_GET, SW_L3_PARSER, \ - sizeof(fal_l3_excep_parser_ctrl), SW_PARAM_PTR|SW_PARAM_OUT, "L3Parser"), - -#define SW_API_SEC_L3_PARSER_CTRL_SET_DESC \ - SW_PARAM_DEF(SW_API_SEC_L3_PARSER_CTRL_SET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \ - SW_PARAM_DEF(SW_API_SEC_L3_PARSER_CTRL_SET, SW_L3_PARSER, \ - sizeof(fal_l3_excep_parser_ctrl), SW_PARAM_PTR|SW_PARAM_IN, "L3Parser"), - -#define SW_API_SEC_L4_PARSER_CTRL_GET_DESC \ - SW_PARAM_DEF(SW_API_SEC_L4_PARSER_CTRL_GET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \ - SW_PARAM_DEF(SW_API_SEC_L4_PARSER_CTRL_GET, SW_L4_PARSER, \ - sizeof(fal_l4_excep_parser_ctrl), SW_PARAM_PTR|SW_PARAM_OUT, "L4Parser"), - -#define SW_API_SEC_L4_PARSER_CTRL_SET_DESC \ - SW_PARAM_DEF(SW_API_SEC_L4_PARSER_CTRL_SET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \ - SW_PARAM_DEF(SW_API_SEC_L4_PARSER_CTRL_SET, SW_L4_PARSER, \ - sizeof(fal_l4_excep_parser_ctrl), SW_PARAM_PTR|SW_PARAM_IN, "L4Parser"), - -#define SW_API_SEC_EXP_CTRL_GET_DESC \ - SW_PARAM_DEF(SW_API_SEC_EXP_CTRL_GET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \ - SW_PARAM_DEF(SW_API_SEC_EXP_CTRL_GET, SW_UINT32, 4, SW_PARAM_IN, "ExpType"), \ - SW_PARAM_DEF(SW_API_SEC_EXP_CTRL_GET, SW_EXP_CTRL, \ - sizeof(fal_l3_excep_ctrl_t), SW_PARAM_PTR|SW_PARAM_OUT, "ExpCtrl"), - -#define SW_API_SEC_EXP_CTRL_SET_DESC \ - SW_PARAM_DEF(SW_API_SEC_EXP_CTRL_SET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \ - SW_PARAM_DEF(SW_API_SEC_EXP_CTRL_SET, SW_UINT32, 4, SW_PARAM_IN, "ExpType"), \ - SW_PARAM_DEF(SW_API_SEC_EXP_CTRL_SET, SW_EXP_CTRL, \ - sizeof(fal_l3_excep_ctrl_t), SW_PARAM_PTR|SW_PARAM_IN, "ExpCtrl"), - -#define SW_API_IP_HOST_ADD_DESC \ - SW_PARAM_DEF(SW_API_IP_HOST_ADD, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \ - SW_PARAM_DEF(SW_API_IP_HOST_ADD, SW_IP_HOSTENTRY, \ - sizeof(fal_host_entry_t), SW_PARAM_PTR|SW_PARAM_IN|SW_PARAM_OUT, "Hostentry"), - -#define SW_API_IP_HOST_DEL_DESC \ - SW_PARAM_DEF(SW_API_IP_HOST_DEL, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \ - SW_PARAM_DEF(SW_API_IP_HOST_DEL, SW_UINT32, 4, SW_PARAM_IN, "DelMode"), \ - SW_PARAM_DEF(SW_API_IP_HOST_DEL, SW_IP_HOSTENTRY, \ - sizeof(fal_host_entry_t), SW_PARAM_PTR|SW_PARAM_IN, "Hostentry"), - -#define SW_API_IP_HOST_GET_DESC \ - SW_PARAM_DEF(SW_API_IP_HOST_GET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \ - SW_PARAM_DEF(SW_API_IP_HOST_GET, SW_UINT32, 4, SW_PARAM_IN, "GetMode"), \ - SW_PARAM_DEF(SW_API_IP_HOST_GET, SW_IP_HOSTENTRY, \ - sizeof(fal_host_entry_t), SW_PARAM_PTR|SW_PARAM_IN|SW_PARAM_OUT, "Hostentry"), - -#define SW_API_IP_HOST_NEXT_DESC \ - SW_PARAM_DEF(SW_API_IP_HOST_NEXT, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \ - SW_PARAM_DEF(SW_API_IP_HOST_NEXT, SW_UINT32, 4, SW_PARAM_IN, "NextMode"), \ - SW_PARAM_DEF(SW_API_IP_HOST_NEXT, SW_IP_HOSTENTRY, \ - sizeof(fal_host_entry_t), SW_PARAM_PTR|SW_PARAM_IN|SW_PARAM_OUT, "Hostentry"), - -#define SW_API_IP_HOST_COUNTER_BIND_DESC \ - SW_PARAM_DEF(SW_API_IP_HOST_COUNTER_BIND, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \ - SW_PARAM_DEF(SW_API_IP_HOST_COUNTER_BIND, SW_UINT32, 4, SW_PARAM_IN, "EntryID"), \ - SW_PARAM_DEF(SW_API_IP_HOST_COUNTER_BIND, SW_UINT32, 4, SW_PARAM_IN, "CounterID"),\ - SW_PARAM_DEF(SW_API_IP_HOST_COUNTER_BIND, SW_ENABLE, 4, SW_PARAM_IN, "Enable"), - -#define SW_API_IP_HOST_PPPOE_BIND_DESC \ - SW_PARAM_DEF(SW_API_IP_HOST_PPPOE_BIND, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \ - SW_PARAM_DEF(SW_API_IP_HOST_PPPOE_BIND, SW_UINT32, 4, SW_PARAM_IN, "EntryID"), \ - SW_PARAM_DEF(SW_API_IP_HOST_PPPOE_BIND, SW_UINT32, 4, SW_PARAM_IN, "PPPoEID"), \ - SW_PARAM_DEF(SW_API_IP_HOST_PPPOE_BIND, SW_ENABLE, 4, SW_PARAM_IN, "Enable"), - -#define SW_API_IP_PT_ARP_LEARN_SET_DESC \ - SW_PARAM_DEF(SW_API_IP_PT_ARP_LEARN_SET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \ - SW_PARAM_DEF(SW_API_IP_PT_ARP_LEARN_SET, SW_UINT32, 4, SW_PARAM_IN, "Port ID"), \ - SW_PARAM_DEF(SW_API_IP_PT_ARP_LEARN_SET, SW_UINT32, 4, SW_PARAM_IN, "LearnStatus"), - -#define SW_API_IP_PT_ARP_LEARN_GET_DESC \ - SW_PARAM_DEF(SW_API_IP_PT_ARP_LEARN_GET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \ - SW_PARAM_DEF(SW_API_IP_PT_ARP_LEARN_GET, SW_UINT32, 4, SW_PARAM_IN, "Port ID"), \ - SW_PARAM_DEF(SW_API_IP_PT_ARP_LEARN_GET, SW_UINT32, 4, \ - SW_PARAM_PTR|SW_PARAM_OUT, "LearnStatus"), - -#define SW_API_IP_ARP_LEARN_SET_DESC \ - SW_PARAM_DEF(SW_API_IP_ARP_LEARN_SET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \ - SW_PARAM_DEF(SW_API_IP_ARP_LEARN_SET, SW_ARP_LEARNMODE, \ - sizeof(fal_arp_learn_mode_t), SW_PARAM_IN, "LearnMode"), - -#define SW_API_IP_ARP_LEARN_GET_DESC \ - SW_PARAM_DEF(SW_API_IP_ARP_LEARN_GET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \ - SW_PARAM_DEF(SW_API_IP_ARP_LEARN_GET, SW_ARP_LEARNMODE, \ - sizeof(fal_arp_learn_mode_t), SW_PARAM_PTR|SW_PARAM_OUT, "LearnMode"), - -#define SW_API_IP_SOURCE_GUARD_SET_DESC \ - SW_PARAM_DEF(SW_API_IP_SOURCE_GUARD_SET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \ - SW_PARAM_DEF(SW_API_IP_SOURCE_GUARD_SET, SW_UINT32, 4, SW_PARAM_IN, "Port ID"), \ - SW_PARAM_DEF(SW_API_IP_SOURCE_GUARD_SET, SW_IP_GUARDMODE, \ - sizeof(fal_source_guard_mode_t), SW_PARAM_IN, "GuardMode"), - -#define SW_API_IP_SOURCE_GUARD_GET_DESC \ - SW_PARAM_DEF(SW_API_IP_SOURCE_GUARD_GET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \ - SW_PARAM_DEF(SW_API_IP_SOURCE_GUARD_GET, SW_UINT32, 4, SW_PARAM_IN, "Port ID"), \ - SW_PARAM_DEF(SW_API_IP_SOURCE_GUARD_GET, SW_IP_GUARDMODE, \ - sizeof(fal_source_guard_mode_t), SW_PARAM_PTR|SW_PARAM_OUT, "GuardMode"), - -#define SW_API_IP_ARP_GUARD_SET_DESC \ - SW_PARAM_DEF(SW_API_IP_ARP_GUARD_SET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \ - SW_PARAM_DEF(SW_API_IP_ARP_GUARD_SET, SW_UINT32, 4, SW_PARAM_IN, "Port ID"), \ - SW_PARAM_DEF(SW_API_IP_ARP_GUARD_SET, SW_IP_GUARDMODE, \ - sizeof(fal_source_guard_mode_t), SW_PARAM_IN, "GuardMode"), - -#define SW_API_IP_ARP_GUARD_GET_DESC \ - SW_PARAM_DEF(SW_API_IP_ARP_GUARD_GET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \ - SW_PARAM_DEF(SW_API_IP_ARP_GUARD_GET, SW_UINT32, 4, SW_PARAM_IN, "Port ID"), \ - SW_PARAM_DEF(SW_API_IP_ARP_GUARD_GET, SW_IP_GUARDMODE, \ - sizeof(fal_source_guard_mode_t), SW_PARAM_PTR|SW_PARAM_OUT, "GuardMode"), - -#define SW_API_IP_ROUTE_STATUS_SET_DESC \ - SW_PARAM_DEF(SW_API_IP_ROUTE_STATUS_SET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \ - SW_PARAM_DEF(SW_API_IP_ROUTE_STATUS_SET, SW_ENABLE, 4, SW_PARAM_IN, "Status"), - -#define SW_API_IP_ROUTE_STATUS_GET_DESC \ - SW_PARAM_DEF(SW_API_IP_ROUTE_STATUS_GET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \ - SW_PARAM_DEF(SW_API_IP_ROUTE_STATUS_GET, SW_ENABLE, 4, SW_PARAM_PTR|SW_PARAM_OUT, "Status"), - -#define SW_API_IP_INTF_ENTRY_ADD_DESC \ - SW_PARAM_DEF(SW_API_IP_INTF_ENTRY_ADD, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \ - SW_PARAM_DEF(SW_API_IP_INTF_ENTRY_ADD, SW_INTFMACENTRY, \ - sizeof(fal_intf_mac_entry_t), SW_PARAM_PTR|SW_PARAM_IN|SW_PARAM_OUT, "Entry"), - -#define SW_API_IP_INTF_ENTRY_DEL_DESC \ - SW_PARAM_DEF(SW_API_IP_INTF_ENTRY_DEL, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \ - SW_PARAM_DEF(SW_API_IP_INTF_ENTRY_DEL, SW_UINT32, 4, SW_PARAM_IN, "Del Mode"), \ - SW_PARAM_DEF(SW_API_IP_INTF_ENTRY_DEL, SW_INTFMACENTRY, \ - sizeof(fal_intf_mac_entry_t), SW_PARAM_PTR|SW_PARAM_IN, "Entry"), - -#define SW_API_IP_INTF_ENTRY_NEXT_DESC \ - SW_PARAM_DEF(SW_API_IP_INTF_ENTRY_NEXT, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \ - SW_PARAM_DEF(SW_API_IP_INTF_ENTRY_NEXT, SW_UINT32, 4, SW_PARAM_IN, "Next Mode"), \ - SW_PARAM_DEF(SW_API_IP_INTF_ENTRY_NEXT, SW_INTFMACENTRY, \ - sizeof(fal_intf_mac_entry_t), SW_PARAM_PTR|SW_PARAM_IN|SW_PARAM_OUT, "Entry"), - -#define SW_API_IP_UNK_SOURCE_CMD_SET_DESC \ - SW_PARAM_DEF(SW_API_IP_UNK_SOURCE_CMD_SET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \ - SW_PARAM_DEF(SW_API_IP_UNK_SOURCE_CMD_SET, SW_MACCMD, \ - sizeof(fal_fwd_cmd_t), SW_PARAM_IN, "Forwarding"), - -#define SW_API_IP_UNK_SOURCE_CMD_GET_DESC \ - SW_PARAM_DEF(SW_API_IP_UNK_SOURCE_CMD_GET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \ - SW_PARAM_DEF(SW_API_IP_UNK_SOURCE_CMD_GET, SW_MACCMD, \ - sizeof(fal_fwd_cmd_t), SW_PARAM_PTR|SW_PARAM_OUT, "Forwarding"), - -#define SW_API_ARP_UNK_SOURCE_CMD_SET_DESC \ - SW_PARAM_DEF(SW_API_ARP_UNK_SOURCE_CMD_SET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \ - SW_PARAM_DEF(SW_API_ARP_UNK_SOURCE_CMD_SET, SW_MACCMD, \ - sizeof(fal_fwd_cmd_t), SW_PARAM_IN, "Forwarding"), - -#define SW_API_ARP_UNK_SOURCE_CMD_GET_DESC \ - SW_PARAM_DEF(SW_API_ARP_UNK_SOURCE_CMD_GET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \ - SW_PARAM_DEF(SW_API_ARP_UNK_SOURCE_CMD_GET, SW_MACCMD, \ - sizeof(fal_fwd_cmd_t), SW_PARAM_PTR|SW_PARAM_OUT, "Forwarding"), - -#define SW_API_IP_AGE_TIME_SET_DESC \ - SW_PARAM_DEF(SW_API_IP_AGE_TIME_SET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \ - SW_PARAM_DEF(SW_API_IP_AGE_TIME_SET, SW_UINT32, 4, \ - SW_PARAM_PTR|SW_PARAM_IN|SW_PARAM_OUT, "Time"), - -#define SW_API_IP_AGE_TIME_GET_DESC \ - SW_PARAM_DEF(SW_API_IP_AGE_TIME_GET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \ - SW_PARAM_DEF(SW_API_IP_AGE_TIME_GET, SW_UINT32, 4, SW_PARAM_PTR|SW_PARAM_OUT, "Time"), - -#define SW_API_WCMP_HASH_MODE_SET_DESC \ - SW_PARAM_DEF(SW_API_WCMP_HASH_MODE_SET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \ - SW_PARAM_DEF(SW_API_WCMP_HASH_MODE_SET, SW_UINT32, 4, SW_PARAM_IN, "Hash Mode"), - -#define SW_API_WCMP_HASH_MODE_GET_DESC \ - SW_PARAM_DEF(SW_API_WCMP_HASH_MODE_GET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \ - SW_PARAM_DEF(SW_API_WCMP_HASH_MODE_GET, SW_UINT32, 4, SW_PARAM_PTR|SW_PARAM_OUT, "Hash Mode"), - -#define SW_API_IP_VRF_BASE_ADDR_SET_DESC \ - SW_PARAM_DEF(SW_API_IP_VRF_BASE_ADDR_SET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \ - SW_PARAM_DEF(SW_API_IP_VRF_BASE_ADDR_SET, SW_UINT32, 4, SW_PARAM_IN, "VRF ID"), \ - SW_PARAM_DEF(SW_API_IP_VRF_BASE_ADDR_SET, SW_IP4ADDR, \ - sizeof(fal_ip4_addr_t), SW_PARAM_IN, "BaseAddr"), - -#define SW_API_IP_VRF_BASE_ADDR_GET_DESC \ - SW_PARAM_DEF(SW_API_IP_VRF_BASE_ADDR_GET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \ - SW_PARAM_DEF(SW_API_IP_VRF_BASE_ADDR_GET, SW_UINT32, 4, SW_PARAM_IN, "VRF ID"), \ - SW_PARAM_DEF(SW_API_IP_VRF_BASE_ADDR_GET, SW_IP4ADDR, \ - sizeof(fal_ip4_addr_t), SW_PARAM_PTR|SW_PARAM_OUT, "BaseAddr"), - -#define SW_API_IP_VRF_BASE_MASK_SET_DESC \ - SW_PARAM_DEF(SW_API_IP_VRF_BASE_MASK_SET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \ - SW_PARAM_DEF(SW_API_IP_VRF_BASE_MASK_SET, SW_UINT32, 4, SW_PARAM_IN, "VRF ID"), \ - SW_PARAM_DEF(SW_API_IP_VRF_BASE_MASK_SET, SW_IP4ADDR, \ - sizeof(fal_ip4_addr_t), SW_PARAM_IN, "BaseMask"), - -#define SW_API_IP_VRF_BASE_MASK_GET_DESC \ - SW_PARAM_DEF(SW_API_IP_VRF_BASE_MASK_GET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \ - SW_PARAM_DEF(SW_API_IP_VRF_BASE_MASK_GET, SW_UINT32, 4, SW_PARAM_IN, "VRF ID"), \ - SW_PARAM_DEF(SW_API_IP_VRF_BASE_MASK_GET, SW_IP4ADDR, \ - sizeof(fal_ip4_addr_t), SW_PARAM_PTR|SW_PARAM_OUT, "BaseMask"), - -#define SW_API_IP_DEFAULT_ROUTE_SET_DESC \ - SW_PARAM_DEF(SW_API_IP_DEFAULT_ROUTE_SET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \ - SW_PARAM_DEF(SW_API_IP_DEFAULT_ROUTE_SET, SW_UINT32, 4, SW_PARAM_IN, "DefaultRoute ID"), \ - SW_PARAM_DEF(SW_API_IP_DEFAULT_ROUTE_SET, SW_DEFAULT_ROUTE_ENTRY, \ - sizeof(fal_default_route_t), SW_PARAM_PTR|SW_PARAM_IN, "DefaultRoute"), - -#define SW_API_IP_DEFAULT_ROUTE_GET_DESC \ - SW_PARAM_DEF(SW_API_IP_DEFAULT_ROUTE_GET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \ - SW_PARAM_DEF(SW_API_IP_DEFAULT_ROUTE_GET, SW_UINT32, 4, SW_PARAM_IN, "DefaultRoute ID"), \ - SW_PARAM_DEF(SW_API_IP_DEFAULT_ROUTE_GET, SW_DEFAULT_ROUTE_ENTRY, \ - sizeof(fal_default_route_t), SW_PARAM_PTR|SW_PARAM_IN|SW_PARAM_OUT, \ - "DefaultRoute"), - -#define SW_API_IP_HOST_ROUTE_SET_DESC \ - SW_PARAM_DEF(SW_API_IP_HOST_ROUTE_SET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \ - SW_PARAM_DEF(SW_API_IP_HOST_ROUTE_SET, SW_UINT32, 4, SW_PARAM_IN, "HostRoute ID"), \ - SW_PARAM_DEF(SW_API_IP_HOST_ROUTE_SET, SW_HOST_ROUTE_ENTRY, \ - sizeof(fal_host_route_t), SW_PARAM_PTR|SW_PARAM_IN, "HostRoute"), - -#define SW_API_IP_HOST_ROUTE_GET_DESC \ - SW_PARAM_DEF(SW_API_IP_HOST_ROUTE_GET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \ - SW_PARAM_DEF(SW_API_IP_HOST_ROUTE_GET, SW_UINT32, 4, SW_PARAM_IN, "HostRoute ID"), \ - SW_PARAM_DEF(SW_API_IP_HOST_ROUTE_GET, SW_HOST_ROUTE_ENTRY, \ - sizeof(fal_host_route_t), SW_PARAM_PTR|SW_PARAM_IN|SW_PARAM_OUT, "HostRoute"), - -#define SW_API_IP_WCMP_ENTRY_SET_DESC \ - SW_PARAM_DEF(SW_API_IP_WCMP_ENTRY_SET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \ - SW_PARAM_DEF(SW_API_IP_WCMP_ENTRY_SET, SW_UINT32, 4, SW_PARAM_IN, "Wcmp ID"), \ - SW_PARAM_DEF(SW_API_IP_WCMP_ENTRY_SET, SW_IP_WCMP_ENTRY, \ - sizeof(fal_ip_wcmp_t), SW_PARAM_PTR|SW_PARAM_IN, "WcmpEntry"), - -#define SW_API_IP_WCMP_ENTRY_GET_DESC \ - SW_PARAM_DEF(SW_API_IP_WCMP_ENTRY_GET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \ - SW_PARAM_DEF(SW_API_IP_WCMP_ENTRY_GET, SW_UINT32, 4, SW_PARAM_IN, "Wcmp ID"), \ - SW_PARAM_DEF(SW_API_IP_WCMP_ENTRY_GET, SW_IP_WCMP_ENTRY, \ - sizeof(fal_ip_wcmp_t), SW_PARAM_PTR|SW_PARAM_OUT, "WcmpEntry"), - -#define SW_API_IP_RFS_IP4_SET_DESC \ - SW_PARAM_DEF(SW_API_IP_RFS_IP4_SET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \ - SW_PARAM_DEF(SW_API_IP_RFS_IP4_SET, SW_IP_RFS_IP4, \ - sizeof(fal_ip4_rfs_t), SW_PARAM_PTR|SW_PARAM_IN, "RfsIp4"), - -#define SW_API_IP_RFS_IP6_SET_DESC \ - SW_PARAM_DEF(SW_API_IP_RFS_IP6_SET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \ - SW_PARAM_DEF(SW_API_IP_RFS_IP6_SET, SW_IP_RFS_IP6, \ - sizeof(fal_ip6_rfs_t), SW_PARAM_PTR|SW_PARAM_IN, "RfsIp6"), - -#define SW_API_IP_RFS_IP4_DEL_DESC \ - SW_PARAM_DEF(SW_API_IP_RFS_IP4_DEL, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \ - SW_PARAM_DEF(SW_API_IP_RFS_IP4_DEL, SW_IP_RFS_IP4, \ - sizeof(fal_ip4_rfs_t), SW_PARAM_PTR|SW_PARAM_IN, "RfsIp4"), - -#define SW_API_IP_RFS_IP6_DEL_DESC \ - SW_PARAM_DEF(SW_API_IP_RFS_IP6_DEL, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \ - SW_PARAM_DEF(SW_API_IP_RFS_IP6_DEL, SW_IP_RFS_IP6, \ - sizeof(fal_ip6_rfs_t), SW_PARAM_PTR|SW_PARAM_IN, "RfsIp6"), - -#define SW_API_IP_DEFAULT_FLOW_CMD_SET_DESC \ - SW_PARAM_DEF(SW_API_IP_DEFAULT_FLOW_CMD_SET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \ - SW_PARAM_DEF(SW_API_IP_DEFAULT_FLOW_CMD_SET, SW_UINT32, 4, SW_PARAM_IN, "Vrf ID"), \ - SW_PARAM_DEF(SW_API_IP_DEFAULT_FLOW_CMD_SET, SW_FLOWTYPE, \ - sizeof(fal_flow_type_t), SW_PARAM_IN, "FlowType"), \ - SW_PARAM_DEF(SW_API_IP_DEFAULT_FLOW_CMD_SET, SW_FLOWCMD, \ - sizeof(fal_default_flow_cmd_t), SW_PARAM_IN, "FlowCmd"), - -#define SW_API_IP_DEFAULT_FLOW_CMD_GET_DESC \ - SW_PARAM_DEF(SW_API_IP_DEFAULT_FLOW_CMD_GET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \ - SW_PARAM_DEF(SW_API_IP_DEFAULT_FLOW_CMD_GET, SW_UINT32, 4, SW_PARAM_IN, "Vrf ID"), \ - SW_PARAM_DEF(SW_API_IP_DEFAULT_FLOW_CMD_GET, SW_FLOWTYPE, \ - sizeof(fal_flow_type_t), SW_PARAM_IN, "FlowType"), \ - SW_PARAM_DEF(SW_API_IP_DEFAULT_FLOW_CMD_GET, SW_FLOWCMD, \ - sizeof(fal_default_flow_cmd_t), SW_PARAM_PTR|SW_PARAM_OUT, "FlowCmd"), - -#define SW_API_IP_DEFAULT_RT_FLOW_CMD_SET_DESC \ - SW_PARAM_DEF(SW_API_IP_DEFAULT_RT_FLOW_CMD_SET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \ - SW_PARAM_DEF(SW_API_IP_DEFAULT_RT_FLOW_CMD_SET, SW_UINT32, 4, SW_PARAM_IN, "Vrf ID"), \ - SW_PARAM_DEF(SW_API_IP_DEFAULT_RT_FLOW_CMD_SET, SW_FLOWTYPE, \ - sizeof(fal_flow_type_t), SW_PARAM_IN, "FlowType"), \ - SW_PARAM_DEF(SW_API_IP_DEFAULT_RT_FLOW_CMD_SET, SW_FLOWCMD, \ - sizeof(fal_default_flow_cmd_t), SW_PARAM_IN, "FlowCmd"), - -#define SW_API_IP_DEFAULT_RT_FLOW_CMD_GET_DESC \ - SW_PARAM_DEF(SW_API_IP_DEFAULT_RT_FLOW_CMD_GET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \ - SW_PARAM_DEF(SW_API_IP_DEFAULT_RT_FLOW_CMD_GET, SW_UINT32, 4, SW_PARAM_IN, "Vrf ID"), \ - SW_PARAM_DEF(SW_API_IP_DEFAULT_RT_FLOW_CMD_GET, SW_FLOWTYPE, \ - sizeof(fal_flow_type_t), SW_PARAM_IN, "FlowType"), \ - SW_PARAM_DEF(SW_API_IP_DEFAULT_RT_FLOW_CMD_GET, SW_FLOWCMD, \ - sizeof(fal_default_flow_cmd_t), SW_PARAM_PTR|SW_PARAM_OUT, "FlowCmd"), - -#define SW_API_IP_VIS_ARP_SG_CFG_GET_DESC \ - SW_PARAM_DEF(SW_API_IP_VIS_ARP_SG_CFG_GET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \ - SW_PARAM_DEF(SW_API_IP_VIS_ARP_SG_CFG_GET, SW_UINT32, 4, SW_PARAM_IN, "VSI ID"), \ - SW_PARAM_DEF(SW_API_IP_VIS_ARP_SG_CFG_GET, SW_ARP_SG_CFG, \ - sizeof(fal_arp_sg_cfg_t), SW_PARAM_PTR|SW_PARAM_OUT, "ArpSg"), - -#define SW_API_IP_VIS_ARP_SG_CFG_SET_DESC \ - SW_PARAM_DEF(SW_API_IP_VIS_ARP_SG_CFG_SET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \ - SW_PARAM_DEF(SW_API_IP_VIS_ARP_SG_CFG_SET, SW_UINT32, 4, SW_PARAM_IN, "VSI ID"), \ - SW_PARAM_DEF(SW_API_IP_VIS_ARP_SG_CFG_SET, SW_ARP_SG_CFG, \ - sizeof(fal_arp_sg_cfg_t), SW_PARAM_PTR|SW_PARAM_IN, "ArpSg"), - -#define SW_API_IP_NETWORK_ROUTE_GET_DESC \ - SW_PARAM_DEF(SW_API_IP_NETWORK_ROUTE_GET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \ - SW_PARAM_DEF(SW_API_IP_NETWORK_ROUTE_GET, SW_UINT32, 4, SW_PARAM_IN, "Index"), \ - SW_PARAM_DEF(SW_API_IP_NETWORK_ROUTE_GET, SW_UINT8, 1, SW_PARAM_IN, "Type"), \ - SW_PARAM_DEF(SW_API_IP_NETWORK_ROUTE_GET, SW_IP_NETWORK_ROUTE, \ - sizeof(fal_network_route_entry_t), SW_PARAM_PTR|SW_PARAM_OUT, "NetworkRoute"), - -#define SW_API_IP_NETWORK_ROUTE_ADD_DESC \ - SW_PARAM_DEF(SW_API_IP_NETWORK_ROUTE_ADD, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \ - SW_PARAM_DEF(SW_API_IP_NETWORK_ROUTE_ADD, SW_UINT32, 4, SW_PARAM_IN, "Index"), \ - SW_PARAM_DEF(SW_API_IP_NETWORK_ROUTE_ADD, SW_IP_NETWORK_ROUTE, \ - sizeof(fal_network_route_entry_t), SW_PARAM_PTR|SW_PARAM_IN, "NetworkRoute"), - -#define SW_API_IP_INTF_GET_DESC \ - SW_PARAM_DEF(SW_API_IP_INTF_GET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \ - SW_PARAM_DEF(SW_API_IP_INTF_GET, SW_UINT32, 4, SW_PARAM_IN, "Index"), \ - SW_PARAM_DEF(SW_API_IP_INTF_GET, SW_IP_INTF, \ - sizeof(fal_intf_entry_t), SW_PARAM_PTR|SW_PARAM_OUT, "INTF"), - -#define SW_API_IP_INTF_SET_DESC \ - SW_PARAM_DEF(SW_API_IP_INTF_SET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \ - SW_PARAM_DEF(SW_API_IP_INTF_SET, SW_UINT32, 4, SW_PARAM_IN, "Index"), \ - SW_PARAM_DEF(SW_API_IP_INTF_SET, SW_IP_INTF, \ - sizeof(fal_intf_entry_t), SW_PARAM_PTR|SW_PARAM_IN, "INTF"), - -#define SW_API_IP_VSI_INTF_GET_DESC \ - SW_PARAM_DEF(SW_API_IP_VSI_INTF_GET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \ - SW_PARAM_DEF(SW_API_IP_VSI_INTF_GET, SW_UINT32, 4, SW_PARAM_IN, "vSI"), \ - SW_PARAM_DEF(SW_API_IP_VSI_INTF_GET, SW_IP_VSI_INTF, \ - sizeof(fal_intf_id_t), SW_PARAM_PTR|SW_PARAM_OUT, "VsiIntf"), - -#define SW_API_IP_VSI_INTF_SET_DESC \ - SW_PARAM_DEF(SW_API_IP_VSI_INTF_SET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \ - SW_PARAM_DEF(SW_API_IP_VSI_INTF_SET, SW_UINT32, 4, SW_PARAM_IN, "Vsi"), \ - SW_PARAM_DEF(SW_API_IP_VSI_INTF_SET, SW_IP_VSI_INTF, \ - sizeof(fal_intf_id_t), SW_PARAM_PTR|SW_PARAM_IN, "VsiIntf"), - -#define SW_API_IP_PORT_INTF_GET_DESC \ - SW_PARAM_DEF(SW_API_IP_PORT_INTF_GET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \ - SW_PARAM_DEF(SW_API_IP_PORT_INTF_GET, SW_UINT32, 4, SW_PARAM_IN, "port"), \ - SW_PARAM_DEF(SW_API_IP_PORT_INTF_GET, SW_IP_VSI_INTF, \ - sizeof(fal_intf_id_t), SW_PARAM_PTR|SW_PARAM_OUT, "PortIntf"), - -#define SW_API_IP_PORT_INTF_SET_DESC \ - SW_PARAM_DEF(SW_API_IP_PORT_INTF_SET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \ - SW_PARAM_DEF(SW_API_IP_PORT_INTF_SET, SW_UINT32, 4, SW_PARAM_IN, "Port"), \ - SW_PARAM_DEF(SW_API_IP_PORT_INTF_SET, SW_IP_VSI_INTF, \ - sizeof(fal_intf_id_t), SW_PARAM_PTR|SW_PARAM_IN, "PortIntf"), - -#define SW_API_IP_NEXTHOP_GET_DESC \ - SW_PARAM_DEF(SW_API_IP_NEXTHOP_GET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \ - SW_PARAM_DEF(SW_API_IP_NEXTHOP_GET, SW_UINT32, 4, SW_PARAM_IN, "index"), \ - SW_PARAM_DEF(SW_API_IP_NEXTHOP_GET, SW_IP_NEXTHOP, \ - sizeof(fal_ip_nexthop_t), SW_PARAM_PTR|SW_PARAM_OUT, "Nexthop"), - -#define SW_API_IP_NEXTHOP_SET_DESC \ - SW_PARAM_DEF(SW_API_IP_NEXTHOP_SET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \ - SW_PARAM_DEF(SW_API_IP_NEXTHOP_SET, SW_UINT32, 4, SW_PARAM_IN, "index"), \ - SW_PARAM_DEF(SW_API_IP_NEXTHOP_SET, SW_IP_NEXTHOP, \ - sizeof(fal_ip_nexthop_t), SW_PARAM_PTR|SW_PARAM_IN, "Nexthop"), - -#define SW_API_IP_VSI_SG_SET_DESC \ - SW_PARAM_DEF(SW_API_IP_VSI_SG_SET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \ - SW_PARAM_DEF(SW_API_IP_VSI_SG_SET, SW_UINT32, 4, SW_PARAM_IN, "vsi"), \ - SW_PARAM_DEF(SW_API_IP_VSI_SG_SET, SW_IP_SG, \ - sizeof(fal_sg_cfg_t), SW_PARAM_PTR|SW_PARAM_IN, "vsisg"), - -#define SW_API_IP_VSI_SG_GET_DESC \ - SW_PARAM_DEF(SW_API_IP_VSI_SG_GET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \ - SW_PARAM_DEF(SW_API_IP_VSI_SG_GET, SW_UINT32, 4, SW_PARAM_IN, "vsi"), \ - SW_PARAM_DEF(SW_API_IP_VSI_SG_GET, SW_IP_SG, \ - sizeof(fal_sg_cfg_t), SW_PARAM_PTR|SW_PARAM_OUT, "vsisg"), - -#define SW_API_IP_PORT_SG_SET_DESC \ - SW_PARAM_DEF(SW_API_IP_PORT_SG_SET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \ - SW_PARAM_DEF(SW_API_IP_PORT_SG_SET, SW_UINT32, 4, SW_PARAM_IN, "port"), \ - SW_PARAM_DEF(SW_API_IP_PORT_SG_SET, SW_IP_SG, \ - sizeof(fal_sg_cfg_t), SW_PARAM_PTR|SW_PARAM_IN, "portsg"), - -#define SW_API_IP_PORT_SG_GET_DESC \ - SW_PARAM_DEF(SW_API_IP_PORT_SG_GET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \ - SW_PARAM_DEF(SW_API_IP_PORT_SG_GET, SW_UINT32, 4, SW_PARAM_IN, "port"), \ - SW_PARAM_DEF(SW_API_IP_PORT_SG_GET, SW_IP_SG, \ - sizeof(fal_sg_cfg_t), SW_PARAM_PTR|SW_PARAM_OUT, "portsg"), - -#define SW_API_IP_PUB_IP_SET_DESC \ - SW_PARAM_DEF(SW_API_IP_PUB_IP_SET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \ - SW_PARAM_DEF(SW_API_IP_PUB_IP_SET, SW_UINT32, 4, SW_PARAM_IN, "index"), \ - SW_PARAM_DEF(SW_API_IP_PUB_IP_SET, SW_IP_PUB, \ - sizeof(fal_ip_pub_addr_t), SW_PARAM_PTR|SW_PARAM_IN, "PubAdd"), - -#define SW_API_IP_NETWORK_ROUTE_DEL_DESC \ - SW_PARAM_DEF(SW_API_IP_NETWORK_ROUTE_DEL, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \ - SW_PARAM_DEF(SW_API_IP_NETWORK_ROUTE_DEL, SW_UINT32, 4, SW_PARAM_IN, "index"), \ - SW_PARAM_DEF(SW_API_IP_NETWORK_ROUTE_DEL, SW_UINT8, 1, SW_PARAM_IN, "type"), - -#define SW_API_IP_PUB_IP_GET_DESC \ - SW_PARAM_DEF(SW_API_IP_PUB_IP_GET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \ - SW_PARAM_DEF(SW_API_IP_PUB_IP_GET, SW_UINT32, 4, SW_PARAM_IN, "index"), \ - SW_PARAM_DEF(SW_API_IP_PUB_IP_GET, SW_IP_PUB, \ - sizeof(fal_ip_pub_addr_t), SW_PARAM_PTR|SW_PARAM_OUT, "PubGet"), - -#define SW_API_IP_PORT_MAC_GET_DESC \ - SW_PARAM_DEF(SW_API_IP_PORT_MAC_GET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \ - SW_PARAM_DEF(SW_API_IP_PORT_MAC_GET, SW_UINT32, 4, SW_PARAM_IN, "port"), \ - SW_PARAM_DEF(SW_API_IP_PORT_MAC_GET, SW_IP_PORTMAC, \ - sizeof(fal_macaddr_entry_t), SW_PARAM_PTR|SW_PARAM_OUT, "portmac"), - -#define SW_API_IP_PORT_MAC_SET_DESC \ - SW_PARAM_DEF(SW_API_IP_PORT_MAC_SET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \ - SW_PARAM_DEF(SW_API_IP_PORT_MAC_SET, SW_UINT32, 4, SW_PARAM_IN, "port"), \ - SW_PARAM_DEF(SW_API_IP_PORT_MAC_SET, SW_IP_PORTMAC, \ - sizeof(fal_macaddr_entry_t), SW_PARAM_PTR|SW_PARAM_IN, "portmac"), - -#define SW_API_IP_ROUTE_MISS_GET_DESC \ - SW_PARAM_DEF(SW_API_IP_ROUTE_MISS_GET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \ - SW_PARAM_DEF(SW_API_IP_ROUTE_MISS_GET, SW_UINT32, 4, SW_PARAM_PTR|SW_PARAM_OUT, "cmd"), - -#define SW_API_IP_ROUTE_MISS_SET_DESC \ - SW_PARAM_DEF(SW_API_IP_ROUTE_MISS_SET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \ - SW_PARAM_DEF(SW_API_IP_ROUTE_MISS_SET, SW_UINT32, 4, SW_PARAM_IN, "cmd"), - -#define SW_API_IP_PORT_ARP_SG_GET_DESC \ - SW_PARAM_DEF(SW_API_IP_PORT_ARP_SG_GET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \ - SW_PARAM_DEF(SW_API_IP_PORT_ARP_SG_GET, SW_UINT32, 4, SW_PARAM_IN, "Port ID"), \ - SW_PARAM_DEF(SW_API_IP_PORT_ARP_SG_GET, SW_ARP_SG_CFG, \ - sizeof(fal_arp_sg_cfg_t), SW_PARAM_PTR|SW_PARAM_OUT, "portArpSg"), - -#define SW_API_IP_PORT_ARP_SG_SET_DESC \ - SW_PARAM_DEF(SW_API_IP_PORT_ARP_SG_SET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \ - SW_PARAM_DEF(SW_API_IP_PORT_ARP_SG_SET, SW_UINT32, 4, SW_PARAM_IN, "Port ID"), \ - SW_PARAM_DEF(SW_API_IP_PORT_ARP_SG_SET, SW_ARP_SG_CFG, \ - sizeof(fal_arp_sg_cfg_t), SW_PARAM_PTR|SW_PARAM_IN, "portArpSg"), - -#define SW_API_IP_VSI_MC_MODE_GET_DESC \ - SW_PARAM_DEF(SW_API_IP_VSI_MC_MODE_GET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \ - SW_PARAM_DEF(SW_API_IP_VSI_MC_MODE_GET, SW_UINT32, 4, SW_PARAM_IN, "Vsi"), \ - SW_PARAM_DEF(SW_API_IP_VSI_MC_MODE_GET, SW_IP_MCMODE, \ - sizeof(fal_mc_mode_cfg_t), SW_PARAM_PTR|SW_PARAM_OUT, "mcmode"), - -#define SW_API_IP_VSI_MC_MODE_SET_DESC \ - SW_PARAM_DEF(SW_API_IP_VSI_MC_MODE_SET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \ - SW_PARAM_DEF(SW_API_IP_VSI_MC_MODE_SET, SW_UINT32, 4, SW_PARAM_IN, "Vsi"), \ - SW_PARAM_DEF(SW_API_IP_VSI_MC_MODE_SET, SW_IP_MCMODE, \ - sizeof(fal_mc_mode_cfg_t), SW_PARAM_PTR|SW_PARAM_IN, "mcmode"), - -#define SW_API_GLOBAL_CTRL_SET_DESC \ - SW_PARAM_DEF(SW_API_GLOBAL_CTRL_SET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \ - SW_PARAM_DEF(SW_API_GLOBAL_CTRL_SET, SW_IP_GLOBAL, \ - sizeof(fal_ip_global_cfg_t), SW_PARAM_PTR|SW_PARAM_IN, "global"), - -#define SW_API_GLOBAL_CTRL_GET_DESC \ - SW_PARAM_DEF(SW_API_GLOBAL_CTRL_GET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \ - SW_PARAM_DEF(SW_API_GLOBAL_CTRL_GET, SW_IP_GLOBAL, \ - sizeof(fal_ip_global_cfg_t), SW_PARAM_PTR|SW_PARAM_OUT, "global"), - - -#define SW_API_FLOW_STATUS_SET_DESC \ - SW_PARAM_DEF(SW_API_FLOW_STATUS_SET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \ - SW_PARAM_DEF(SW_API_FLOW_STATUS_SET, SW_UINT32, 4, SW_PARAM_IN, "status"), - -#define SW_API_FLOW_STATUS_GET_DESC \ - SW_PARAM_DEF(SW_API_FLOW_STATUS_GET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \ - SW_PARAM_DEF(SW_API_FLOW_STATUS_GET, SW_UINT32, 4, SW_PARAM_PTR|SW_PARAM_OUT, "status"), - -#define SW_API_FLOW_AGE_TIMER_SET_DESC \ - SW_PARAM_DEF(SW_API_FLOW_AGE_TIMER_SET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \ - SW_PARAM_DEF(SW_API_FLOW_AGE_TIMER_SET, SW_FLOW_AGE, \ - sizeof(fal_flow_age_timer_t), SW_PARAM_PTR|SW_PARAM_IN, "age"), - -#define SW_API_FLOW_AGE_TIMER_GET_DESC \ - SW_PARAM_DEF(SW_API_FLOW_AGE_TIMER_GET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \ - SW_PARAM_DEF(SW_API_FLOW_AGE_TIMER_GET, SW_FLOW_AGE, \ - sizeof(fal_flow_age_timer_t), SW_PARAM_PTR|SW_PARAM_OUT, "age"), - -#define SW_API_FLOW_CTRL_SET_DESC \ - SW_PARAM_DEF(SW_API_FLOW_CTRL_SET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \ - SW_PARAM_DEF(SW_API_FLOW_CTRL_SET, SW_UINT32, 4, SW_PARAM_IN, "type"), \ - SW_PARAM_DEF(SW_API_FLOW_CTRL_SET, SW_UINT32, 4, SW_PARAM_IN, "dir"), \ - SW_PARAM_DEF(SW_API_FLOW_CTRL_SET, SW_FLOW_CTRL, \ - sizeof(fal_flow_mgmt_t), SW_PARAM_PTR|SW_PARAM_IN, "ctrl"), - -#define SW_API_FLOW_CTRL_GET_DESC \ - SW_PARAM_DEF(SW_API_FLOW_CTRL_GET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \ - SW_PARAM_DEF(SW_API_FLOW_CTRL_GET, SW_UINT32, 4, SW_PARAM_IN, "type"), \ - SW_PARAM_DEF(SW_API_FLOW_CTRL_GET, SW_UINT32, 4, SW_PARAM_IN, "dir"), \ - SW_PARAM_DEF(SW_API_FLOW_CTRL_GET, SW_FLOW_CTRL, \ - sizeof(fal_flow_mgmt_t), SW_PARAM_PTR|SW_PARAM_OUT, "ctrl"), - -#define SW_API_FLOW_ENTRY_ADD_DESC \ - SW_PARAM_DEF(SW_API_FLOW_ENTRY_ADD, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \ - SW_PARAM_DEF(SW_API_FLOW_ENTRY_ADD, SW_UINT32, 4, SW_PARAM_IN, "add mode"), \ - SW_PARAM_DEF(SW_API_FLOW_ENTRY_ADD, SW_FLOW_ENTRY, \ - sizeof(fal_flow_entry_t), SW_PARAM_PTR|SW_PARAM_IN|SW_PARAM_OUT, \ - "Flowentry"), - -#define SW_API_FLOW_ENTRY_DEL_DESC \ - SW_PARAM_DEF(SW_API_FLOW_ENTRY_DEL, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \ - SW_PARAM_DEF(SW_API_FLOW_ENTRY_DEL, SW_UINT32, 4, SW_PARAM_IN, "Del mode"), \ - SW_PARAM_DEF(SW_API_FLOW_ENTRY_DEL, SW_FLOW_ENTRY, \ - sizeof(fal_flow_entry_t), SW_PARAM_PTR|SW_PARAM_IN, "Flowentry"), - -#define SW_API_FLOW_ENTRY_GET_DESC \ - SW_PARAM_DEF(SW_API_FLOW_ENTRY_GET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \ - SW_PARAM_DEF(SW_API_FLOW_ENTRY_GET, SW_UINT32, 4, SW_PARAM_IN, "get mode"), \ - SW_PARAM_DEF(SW_API_FLOW_ENTRY_GET, SW_FLOW_ENTRY, \ - sizeof(fal_flow_entry_t), SW_PARAM_PTR|SW_PARAM_IN|SW_PARAM_OUT, \ - "Flowentry"), - -#define SW_API_FLOW_HOST_ADD_DESC \ - SW_PARAM_DEF(SW_API_FLOW_HOST_ADD, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \ - SW_PARAM_DEF(SW_API_FLOW_HOST_ADD, SW_UINT32, 4, SW_PARAM_IN, "add mode"), \ - SW_PARAM_DEF(SW_API_FLOW_HOST_ADD, SW_FLOW_HOST, \ - sizeof(fal_flow_host_entry_t), SW_PARAM_PTR|SW_PARAM_IN|SW_PARAM_OUT, \ - "Flowhost"), - -#define SW_API_FLOW_HOST_DEL_DESC \ - SW_PARAM_DEF(SW_API_FLOW_HOST_DEL, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \ - SW_PARAM_DEF(SW_API_FLOW_HOST_DEL, SW_UINT32, 4, SW_PARAM_IN, "Del mode"), \ - SW_PARAM_DEF(SW_API_FLOW_HOST_DEL, SW_FLOW_HOST, \ - sizeof(fal_flow_host_entry_t), SW_PARAM_PTR|SW_PARAM_IN, "Flowhost"), - -#define SW_API_FLOW_HOST_GET_DESC \ - SW_PARAM_DEF(SW_API_FLOW_HOST_GET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \ - SW_PARAM_DEF(SW_API_FLOW_HOST_GET, SW_UINT32, 4, SW_PARAM_IN, "get mode"), \ - SW_PARAM_DEF(SW_API_FLOW_HOST_GET, SW_FLOW_HOST, \ - sizeof(fal_flow_host_entry_t), SW_PARAM_PTR|SW_PARAM_IN|SW_PARAM_OUT, \ - "Flowhost"), - -#define SW_API_FLOW_GLOBAL_CFG_GET_DESC \ - SW_PARAM_DEF(SW_API_FLOW_GLOBAL_CFG_GET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \ - SW_PARAM_DEF(SW_API_FLOW_GLOBAL_CFG_GET, SW_FLOW_GLOBAL, \ - sizeof(fal_flow_global_cfg_t), SW_PARAM_PTR|SW_PARAM_OUT, "Flowglobal"), - -#define SW_API_FLOW_GLOBAL_CFG_SET_DESC \ - SW_PARAM_DEF(SW_API_FLOW_GLOBAL_CFG_SET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \ - SW_PARAM_DEF(SW_API_FLOW_GLOBAL_CFG_SET, SW_FLOW_GLOBAL, \ - sizeof(fal_flow_global_cfg_t), SW_PARAM_PTR|SW_PARAM_IN, "Flowglobal"), - -#define SW_API_FLOWENTRY_NEXT_DESC \ - SW_PARAM_DEF(SW_API_FLOWENTRY_NEXT, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \ - SW_PARAM_DEF(SW_API_FLOWENTRY_NEXT, SW_UINT32, 4, SW_PARAM_IN, "Next mode"), \ - SW_PARAM_DEF(SW_API_FLOWENTRY_NEXT, SW_FLOW_ENTRY, \ - sizeof(fal_flow_entry_t), SW_PARAM_PTR|SW_PARAM_IN|SW_PARAM_OUT, "Flowentry"), - -#define SW_API_NAT_ADD_DESC \ - SW_PARAM_DEF(SW_API_NAT_ADD, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \ - SW_PARAM_DEF(SW_API_NAT_ADD, SW_NATENTRY, \ - sizeof(fal_nat_entry_t), SW_PARAM_PTR|SW_PARAM_IN|SW_PARAM_OUT, "Natentry"), - -#define SW_API_NAT_DEL_DESC \ - SW_PARAM_DEF(SW_API_NAT_DEL, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \ - SW_PARAM_DEF(SW_API_NAT_DEL, SW_UINT32, 4, SW_PARAM_IN, "DelMode"), \ - SW_PARAM_DEF(SW_API_NAT_DEL, SW_NATENTRY, \ - sizeof(fal_nat_entry_t), SW_PARAM_PTR|SW_PARAM_IN, "Natentry"), - -#define SW_API_NAT_GET_DESC \ - SW_PARAM_DEF(SW_API_NAT_GET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \ - SW_PARAM_DEF(SW_API_NAT_GET, SW_UINT32, 4, SW_PARAM_IN, "GetMode"), \ - SW_PARAM_DEF(SW_API_NAT_GET, SW_NATENTRY, \ - sizeof(fal_nat_entry_t), SW_PARAM_PTR|SW_PARAM_IN|SW_PARAM_OUT, "Natentry"), - -#define SW_API_NAT_NEXT_DESC \ - SW_PARAM_DEF(SW_API_NAT_NEXT, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \ - SW_PARAM_DEF(SW_API_NAT_NEXT, SW_UINT32, 4, SW_PARAM_IN, "NextMode"), \ - SW_PARAM_DEF(SW_API_NAT_NEXT, SW_NATENTRY, \ - sizeof(fal_nat_entry_t), SW_PARAM_PTR|SW_PARAM_IN|SW_PARAM_OUT, "Natentry"), - -#define SW_API_NAT_COUNTER_BIND_DESC \ - SW_PARAM_DEF(SW_API_NAT_COUNTER_BIND, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \ - SW_PARAM_DEF(SW_API_NAT_COUNTER_BIND, SW_UINT32, 4, SW_PARAM_IN, "EntryID"), \ - SW_PARAM_DEF(SW_API_NAT_COUNTER_BIND, SW_UINT32, 4, SW_PARAM_IN, "CounterID"),\ - SW_PARAM_DEF(SW_API_NAT_COUNTER_BIND, SW_ENABLE, 4, SW_PARAM_IN, "Enable"), - -#define SW_API_NAPT_ADD_DESC \ - SW_PARAM_DEF(SW_API_NAPT_ADD, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \ - SW_PARAM_DEF(SW_API_NAPT_ADD, SW_NAPTENTRY, \ - sizeof(fal_napt_entry_t), SW_PARAM_PTR|SW_PARAM_IN|SW_PARAM_OUT, "Naptentry"), - -#define SW_API_NAPT_DEL_DESC \ - SW_PARAM_DEF(SW_API_NAPT_DEL, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \ - SW_PARAM_DEF(SW_API_NAPT_DEL, SW_UINT32, 4, SW_PARAM_IN, "DelMode"), \ - SW_PARAM_DEF(SW_API_NAPT_DEL, SW_NAPTENTRY, \ - sizeof(fal_napt_entry_t), SW_PARAM_PTR|SW_PARAM_IN, "Naptentry"), - -#define SW_API_NAPT_GET_DESC \ - SW_PARAM_DEF(SW_API_NAPT_GET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \ - SW_PARAM_DEF(SW_API_NAPT_GET, SW_UINT32, 4, SW_PARAM_IN, "GetMode"), \ - SW_PARAM_DEF(SW_API_NAPT_GET, SW_NAPTENTRY, \ - sizeof(fal_napt_entry_t), SW_PARAM_PTR|SW_PARAM_IN|SW_PARAM_OUT, "Naptentry"), - -#define SW_API_NAPT_NEXT_DESC \ - SW_PARAM_DEF(SW_API_NAPT_NEXT, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \ - SW_PARAM_DEF(SW_API_NAPT_NEXT, SW_UINT32, 4, SW_PARAM_IN, "NextMode"), \ - SW_PARAM_DEF(SW_API_NAPT_NEXT, SW_NAPTENTRY, \ - sizeof(fal_napt_entry_t), SW_PARAM_PTR|SW_PARAM_IN|SW_PARAM_OUT, "Naptentry"), - -#define SW_API_NAPT_COUNTER_BIND_DESC \ - SW_PARAM_DEF(SW_API_NAPT_COUNTER_BIND, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \ - SW_PARAM_DEF(SW_API_NAPT_COUNTER_BIND, SW_UINT32, 4, SW_PARAM_IN, "EntryID"), \ - SW_PARAM_DEF(SW_API_NAPT_COUNTER_BIND, SW_UINT32, 4, SW_PARAM_IN, "CounterID"),\ - SW_PARAM_DEF(SW_API_NAPT_COUNTER_BIND, SW_ENABLE, 4, SW_PARAM_IN, "Enable"), - -#define SW_API_FLOW_ADD_DESC \ - SW_PARAM_DEF(SW_API_FLOW_ADD, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \ - SW_PARAM_DEF(SW_API_FLOW_ADD, SW_FLOWENTRY, \ - sizeof(fal_napt_entry_t), SW_PARAM_PTR|SW_PARAM_IN|SW_PARAM_OUT, "Flowentry"), - -#define SW_API_FLOW_DEL_DESC \ - SW_PARAM_DEF(SW_API_FLOW_DEL, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \ - SW_PARAM_DEF(SW_API_FLOW_DEL, SW_UINT32, 4, SW_PARAM_IN, "DelMode"), \ - SW_PARAM_DEF(SW_API_FLOW_DEL, SW_FLOWENTRY, \ - sizeof(fal_napt_entry_t), SW_PARAM_PTR|SW_PARAM_IN, "Flowentry"), - -#define SW_API_FLOW_GET_DESC \ - SW_PARAM_DEF(SW_API_FLOW_GET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \ - SW_PARAM_DEF(SW_API_FLOW_GET, SW_UINT32, 4, SW_PARAM_IN, "GetMode"), \ - SW_PARAM_DEF(SW_API_FLOW_GET, SW_FLOWENTRY, \ - sizeof(fal_napt_entry_t), SW_PARAM_PTR|SW_PARAM_IN|SW_PARAM_OUT, "Flowentry"), - -#define SW_API_FLOW_NEXT_DESC \ - SW_PARAM_DEF(SW_API_FLOW_NEXT, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \ - SW_PARAM_DEF(SW_API_FLOW_NEXT, SW_UINT32, 4, SW_PARAM_IN, "NextMode"), \ - SW_PARAM_DEF(SW_API_FLOW_NEXT, SW_FLOWENTRY, \ - sizeof(fal_napt_entry_t), SW_PARAM_PTR|SW_PARAM_IN|SW_PARAM_OUT, "Flowentry"), - -#define SW_API_FLOW_COOKIE_SET_DESC \ - SW_PARAM_DEF(SW_API_FLOW_COOKIE_SET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \ - SW_PARAM_DEF(SW_API_FLOW_COOKIE_SET, SW_FLOWCOOKIE, \ - sizeof(fal_flow_cookie_t), SW_PARAM_PTR|SW_PARAM_IN, "Flowcookieentry"), - -#define SW_API_FLOW_RFS_SET_DESC \ - SW_PARAM_DEF(SW_API_FLOW_RFS_SET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \ - SW_PARAM_DEF(SW_API_FLOW_RFS_SET, SW_UINT32, 4, SW_PARAM_IN, "action"), \ - SW_PARAM_DEF(SW_API_FLOW_RFS_SET, SW_FLOWRFS, \ - sizeof(fal_flow_rfs_t), SW_PARAM_PTR|SW_PARAM_IN, "Flowrfs"), - - -#define SW_API_FLOW_COUNTER_BIND_DESC \ - SW_PARAM_DEF(SW_API_FLOW_COUNTER_BIND, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \ - SW_PARAM_DEF(SW_API_FLOW_COUNTER_BIND, SW_UINT32, 4, SW_PARAM_IN, "EntryID"), \ - SW_PARAM_DEF(SW_API_FLOW_COUNTER_BIND, SW_UINT32, 4, SW_PARAM_IN, "CounterID"),\ - SW_PARAM_DEF(SW_API_FLOW_COUNTER_BIND, SW_ENABLE, 4, SW_PARAM_IN, "Enable"), - -#define SW_API_NAT_STATUS_SET_DESC \ - SW_PARAM_DEF(SW_API_NAT_STATUS_SET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \ - SW_PARAM_DEF(SW_API_NAT_STATUS_SET, SW_ENABLE, 4, SW_PARAM_IN, "Status"), - -#define SW_API_NAT_STATUS_GET_DESC \ - SW_PARAM_DEF(SW_API_NAT_STATUS_GET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \ - SW_PARAM_DEF(SW_API_NAT_STATUS_GET, SW_ENABLE, 4, SW_PARAM_PTR|SW_PARAM_OUT, "Status"), - -#define SW_API_NAT_HASH_MODE_SET_DESC \ - SW_PARAM_DEF(SW_API_NAT_HASH_MODE_SET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \ - SW_PARAM_DEF(SW_API_NAT_HASH_MODE_SET, SW_UINT32, 4, SW_PARAM_IN, "Hashmode"), - -#define SW_API_NAT_HASH_MODE_GET_DESC \ - SW_PARAM_DEF(SW_API_NAT_HASH_MODE_GET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \ - SW_PARAM_DEF(SW_API_NAT_HASH_MODE_GET, SW_UINT32, 4, SW_PARAM_PTR|SW_PARAM_OUT, "Hashmode"), - -#define SW_API_NAPT_STATUS_SET_DESC \ - SW_PARAM_DEF(SW_API_NAPT_STATUS_SET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \ - SW_PARAM_DEF(SW_API_NAPT_STATUS_SET, SW_ENABLE, 4, SW_PARAM_IN, "Status"), - -#define SW_API_NAPT_STATUS_GET_DESC \ - SW_PARAM_DEF(SW_API_NAPT_STATUS_GET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \ - SW_PARAM_DEF(SW_API_NAPT_STATUS_GET, SW_ENABLE, 4, SW_PARAM_PTR|SW_PARAM_OUT, "Status"), - -#define SW_API_NAPT_MODE_SET_DESC \ - SW_PARAM_DEF(SW_API_NAPT_MODE_SET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \ - SW_PARAM_DEF(SW_API_NAPT_MODE_SET, SW_NAPTMODE, \ - sizeof(fal_napt_mode_t), SW_PARAM_IN, "Mode"), - -#define SW_API_NAPT_MODE_GET_DESC \ - SW_PARAM_DEF(SW_API_NAPT_MODE_GET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \ - SW_PARAM_DEF(SW_API_NAPT_MODE_GET, SW_NAPTMODE, \ - sizeof(fal_napt_mode_t), SW_PARAM_PTR|SW_PARAM_OUT, "Mode"), - -#define SW_API_PRV_BASE_ADDR_SET_DESC \ - SW_PARAM_DEF(SW_API_PRV_BASE_ADDR_SET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \ - SW_PARAM_DEF(SW_API_PRV_BASE_ADDR_SET, SW_IP4ADDR, \ - sizeof(fal_ip4_addr_t), SW_PARAM_IN, "BaseAddr"), - -#define SW_API_PRV_BASE_ADDR_GET_DESC \ - SW_PARAM_DEF(SW_API_PRV_BASE_ADDR_GET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \ - SW_PARAM_DEF(SW_API_PRV_BASE_ADDR_GET, SW_IP4ADDR, \ - sizeof(fal_ip4_addr_t), SW_PARAM_PTR|SW_PARAM_OUT, "BaseAddr"), - -#define SW_API_PRV_ADDR_MODE_SET_DESC \ - SW_PARAM_DEF(SW_API_PRV_ADDR_MODE_SET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \ - SW_PARAM_DEF(SW_API_PRV_ADDR_MODE_SET, SW_ENABLE, \ - sizeof(a_bool_t), SW_PARAM_IN, "Mode"), - -#define SW_API_PRV_ADDR_MODE_GET_DESC \ - SW_PARAM_DEF(SW_API_PRV_ADDR_MODE_GET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \ - SW_PARAM_DEF(SW_API_PRV_ADDR_MODE_GET, SW_ENABLE, \ - sizeof(a_bool_t), SW_PARAM_PTR|SW_PARAM_OUT, "Mode"), - -#define SW_API_PUB_ADDR_ENTRY_ADD_DESC \ - SW_PARAM_DEF(SW_API_PUB_ADDR_ENTRY_ADD, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \ - SW_PARAM_DEF(SW_API_PUB_ADDR_ENTRY_ADD, SW_PUBADDRENTRY, \ - sizeof(fal_nat_pub_addr_t), SW_PARAM_PTR|SW_PARAM_IN|SW_PARAM_OUT, \ - "PubAddrEntry"), - -#define SW_API_PUB_ADDR_ENTRY_DEL_DESC \ - SW_PARAM_DEF(SW_API_PUB_ADDR_ENTRY_DEL, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \ - SW_PARAM_DEF(SW_API_PUB_ADDR_ENTRY_DEL, SW_UINT32, 4, SW_PARAM_IN, "DelMode"), \ - SW_PARAM_DEF(SW_API_PUB_ADDR_ENTRY_DEL, SW_PUBADDRENTRY, \ - sizeof(fal_nat_pub_addr_t), SW_PARAM_PTR|SW_PARAM_IN, "PubAddrEntry"), - -#define SW_API_PUB_ADDR_ENTRY_NEXT_DESC \ - SW_PARAM_DEF(SW_API_PUB_ADDR_ENTRY_NEXT, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \ - SW_PARAM_DEF(SW_API_PUB_ADDR_ENTRY_NEXT, SW_UINT32, 4, SW_PARAM_IN, "NextMode"), \ - SW_PARAM_DEF(SW_API_PUB_ADDR_ENTRY_NEXT, SW_PUBADDRENTRY, \ - sizeof(fal_nat_pub_addr_t), SW_PARAM_PTR|SW_PARAM_IN|SW_PARAM_OUT, \ - "PubAddrEntry"), - -#define SW_API_NAT_UNK_SESSION_CMD_SET_DESC \ - SW_PARAM_DEF(SW_API_NAT_UNK_SESSION_CMD_SET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \ - SW_PARAM_DEF(SW_API_NAT_UNK_SESSION_CMD_SET, SW_MACCMD, \ - sizeof(fal_fwd_cmd_t), SW_PARAM_IN, "Forwarding"), - -#define SW_API_NAT_UNK_SESSION_CMD_GET_DESC \ - SW_PARAM_DEF(SW_API_NAT_UNK_SESSION_CMD_GET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \ - SW_PARAM_DEF(SW_API_NAT_UNK_SESSION_CMD_GET, SW_MACCMD, \ - sizeof(fal_fwd_cmd_t), SW_PARAM_PTR|SW_PARAM_OUT, "Forwarding"), - -#define SW_API_PRV_BASE_MASK_SET_DESC \ - SW_PARAM_DEF(SW_API_PRV_BASE_MASK_SET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \ - SW_PARAM_DEF(SW_API_PRV_BASE_MASK_SET, SW_IP4ADDR, \ - sizeof(fal_ip4_addr_t), SW_PARAM_IN, "BaseMask"), - -#define SW_API_PRV_BASE_MASK_GET_DESC \ - SW_PARAM_DEF(SW_API_PRV_BASE_MASK_GET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \ - SW_PARAM_DEF(SW_API_PRV_BASE_MASK_GET, SW_IP4ADDR, \ - sizeof(fal_ip4_addr_t), SW_PARAM_PTR|SW_PARAM_OUT, "BaseMask"), - -#define SW_API_NAT_GLOBAL_SET_DESC \ - SW_PARAM_DEF(SW_API_NAT_GLOBAL_SET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \ - SW_PARAM_DEF(SW_API_NAT_GLOBAL_SET, SW_ENABLE, 4, SW_PARAM_IN, "Status"), \ - SW_PARAM_DEF(SW_API_NAT_GLOBAL_SET, SW_ENABLE, 4, SW_PARAM_IN, "Sync Flow Counter"), \ - SW_PARAM_DEF(SW_API_NAT_GLOBAL_SET, SW_UINT32, 4, SW_PARAM_IN, "wan portbmp"), - -#define SW_API_TRUNK_GROUP_SET_DESC \ - SW_PARAM_DEF(SW_API_TRUNK_GROUP_SET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \ - SW_PARAM_DEF(SW_API_TRUNK_GROUP_SET, SW_UINT32, 4, SW_PARAM_IN, "Trunk ID"), \ - SW_PARAM_DEF(SW_API_TRUNK_GROUP_SET, SW_ENABLE, \ - sizeof(a_bool_t), SW_PARAM_IN, "Status"), \ - SW_PARAM_DEF(SW_API_TRUNK_GROUP_SET, SW_PBMP, \ - sizeof(fal_pbmp_t), SW_PARAM_IN, "Member Port Bitmap"), - -#define SW_API_TRUNK_GROUP_GET_DESC \ - SW_PARAM_DEF(SW_API_TRUNK_GROUP_GET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \ - SW_PARAM_DEF(SW_API_TRUNK_GROUP_GET, SW_UINT32, 4, SW_PARAM_IN, "Trunk ID"), \ - SW_PARAM_DEF(SW_API_TRUNK_GROUP_GET, SW_ENABLE, \ - sizeof(a_bool_t), SW_PARAM_PTR|SW_PARAM_OUT, "Status"), \ - SW_PARAM_DEF(SW_API_TRUNK_GROUP_GET, SW_PBMP, \ - sizeof(fal_pbmp_t), SW_PARAM_PTR|SW_PARAM_OUT, "Member Port Bitmap"), - -#define SW_API_TRUNK_HASH_SET_DESC \ - SW_PARAM_DEF(SW_API_TRUNK_HASH_SET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \ - SW_PARAM_DEF(SW_API_TRUNK_HASH_SET, SW_UINT32, 4, SW_PARAM_IN, "Hash Mode"), - -#define SW_API_TRUNK_HASH_GET_DESC \ - SW_PARAM_DEF(SW_API_TRUNK_HASH_GET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \ - SW_PARAM_DEF(SW_API_TRUNK_HASH_GET, SW_UINT32, 4, SW_PARAM_PTR|SW_PARAM_OUT, "Hash Mode"), - -#define SW_API_TRUNK_MAN_SA_SET_DESC \ - SW_PARAM_DEF(SW_API_TRUNK_MAN_SA_SET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \ - SW_PARAM_DEF(SW_API_TRUNK_MAN_SA_SET, SW_MACADDR, \ - sizeof(fal_mac_addr_t), SW_PARAM_PTR|SW_PARAM_IN, "[Manipulable SA]:"), - -#define SW_API_TRUNK_MAN_SA_GET_DESC \ - SW_PARAM_DEF(SW_API_TRUNK_MAN_SA_GET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \ - SW_PARAM_DEF(SW_API_TRUNK_MAN_SA_GET, SW_MACADDR, \ - sizeof(fal_mac_addr_t), SW_PARAM_PTR|SW_PARAM_OUT, "[Manipulable SA]:"), - -#define SW_API_TRUNK_FAILOVER_EN_SET_DESC \ - SW_PARAM_DEF(SW_API_TRUNK_FAILOVER_EN_SET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \ - SW_PARAM_DEF(SW_API_TRUNK_FAILOVER_EN_SET, SW_ENABLE, 4, SW_PARAM_IN, "Failover Status"), - -#define SW_API_TRUNK_FAILOVER_EN_GET_DESC \ - SW_PARAM_DEF(SW_API_TRUNK_FAILOVER_EN_GET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \ - SW_PARAM_DEF(SW_API_TRUNK_FAILOVER_EN_GET, SW_ENABLE, 4, SW_PARAM_PTR|SW_PARAM_OUT, \ - "Failover Status"), - -#define SW_API_MAC_MODE_SET_DESC \ - SW_PARAM_DEF(SW_API_MAC_MODE_SET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \ - SW_PARAM_DEF(SW_API_MAC_MODE_SET, SW_UINT32, 4, SW_PARAM_IN, "Port ID"), \ - SW_PARAM_DEF(SW_API_MAC_MODE_SET, SW_MACCONFIG, \ - sizeof(fal_mac_config_t), SW_PARAM_PTR|SW_PARAM_IN, "MAC config"), - -#define SW_API_MAC_MODE_GET_DESC \ - SW_PARAM_DEF(SW_API_MAC_MODE_GET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \ - SW_PARAM_DEF(SW_API_MAC_MODE_GET, SW_UINT32, 4, SW_PARAM_IN, "Port ID"), \ - SW_PARAM_DEF(SW_API_MAC_MODE_GET, SW_MACCONFIG, \ - sizeof(fal_mac_config_t), SW_PARAM_PTR|SW_PARAM_OUT, "MAC config"), - -#define SW_API_PORT_3AZ_STATUS_SET_DESC \ - SW_PARAM_DEF(SW_API_PORT_3AZ_STATUS_SET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \ - SW_PARAM_DEF(SW_API_PORT_3AZ_STATUS_SET, SW_UINT32, 4, SW_PARAM_IN, "Port ID"), \ - SW_PARAM_DEF(SW_API_PORT_3AZ_STATUS_SET, SW_ENABLE, \ - sizeof(a_bool_t), SW_PARAM_IN, "Status"), - -#define SW_API_PORT_3AZ_STATUS_GET_DESC \ - SW_PARAM_DEF(SW_API_PORT_3AZ_STATUS_GET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \ - SW_PARAM_DEF(SW_API_PORT_3AZ_STATUS_GET, SW_UINT32, 4, SW_PARAM_IN, "Port ID"), \ - SW_PARAM_DEF(SW_API_PORT_3AZ_STATUS_GET, SW_ENABLE, \ - sizeof(a_bool_t), SW_PARAM_PTR|SW_PARAM_OUT, "Status"), - -#define SW_API_PHY_MODE_SET_DESC \ - SW_PARAM_DEF(SW_API_PHY_MODE_SET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \ - SW_PARAM_DEF(SW_API_PHY_MODE_SET, SW_UINT32, 4, SW_PARAM_IN, "Phy ID"), \ - SW_PARAM_DEF(SW_API_PHY_MODE_SET, SW_PHYCONFIG, \ - sizeof(fal_phy_config_t), SW_PARAM_PTR|SW_PARAM_IN, "PHY config"), - -#define SW_API_PHY_MODE_GET_DESC \ - SW_PARAM_DEF(SW_API_PHY_MODE_GET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \ - SW_PARAM_DEF(SW_API_PHY_MODE_GET, SW_UINT32, 4, SW_PARAM_IN, "Phy ID"), \ - SW_PARAM_DEF(SW_API_PHY_MODE_GET, SW_PHYCONFIG, \ - sizeof(fal_phy_config_t), SW_PARAM_PTR|SW_PARAM_OUT, "PHY config"), - -#define SW_API_FX100_CTRL_SET_DESC \ - SW_PARAM_DEF(SW_API_FX100_CTRL_SET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \ - SW_PARAM_DEF(SW_API_FX100_CTRL_SET, SW_FX100CONFIG, \ - sizeof(fal_fx100_ctrl_config_t), SW_PARAM_PTR|SW_PARAM_IN, "fx100 config"), - -#define SW_API_FX100_CTRL_GET_DESC \ - SW_PARAM_DEF(SW_API_FX100_CTRL_GET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \ - SW_PARAM_DEF(SW_API_FX100_CTRL_GET, SW_FX100CONFIG, \ - sizeof(fal_fx100_ctrl_config_t), SW_PARAM_PTR|SW_PARAM_OUT, "fx100 config"), - -#define SW_API_FX100_STATUS_GET_DESC \ - SW_PARAM_DEF(SW_API_FX100_STATUS_GET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \ - SW_PARAM_DEF(SW_API_FX100_STATUS_GET, SW_UINT32, 4, SW_PARAM_PTR|SW_PARAM_OUT, "fx100 status"), - - -#define SW_API_MAC06_EXCH_SET_DESC \ - SW_PARAM_DEF(SW_API_MAC06_EXCH_SET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \ - SW_PARAM_DEF(SW_API_MAC06_EXCH_SET, SW_ENABLE, \ - sizeof(a_bool_t), SW_PARAM_IN, "enable"), - -#define SW_API_MAC06_EXCH_GET_DESC \ - SW_PARAM_DEF(SW_API_MAC06_EXCH_GET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \ - SW_PARAM_DEF(SW_API_MAC06_EXCH_GET, SW_ENABLE, \ - sizeof(a_bool_t), SW_PARAM_PTR|SW_PARAM_OUT, "enable"), - -#define SW_API_VSI_ALLOC_DESC \ - SW_PARAM_DEF(SW_API_VSI_ALLOC, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \ - SW_PARAM_DEF(SW_API_VSI_ALLOC, SW_UINT32, \ - sizeof(a_bool_t), SW_PARAM_PTR|SW_PARAM_OUT, "VSI value"), - -#define SW_API_VSI_FREE_DESC \ - SW_PARAM_DEF(SW_API_VSI_FREE, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \ - SW_PARAM_DEF(SW_API_VSI_FREE, SW_UINT32, 4, SW_PARAM_IN, "VSI value"), \ - -#define SW_API_PORT_VSI_SET_DESC \ - SW_PARAM_DEF(SW_API_PORT_VSI_SET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \ - SW_PARAM_DEF(SW_API_PORT_VSI_SET, SW_UINT32, 4, SW_PARAM_IN, "Port ID"), \ - SW_PARAM_DEF(SW_API_PORT_VSI_SET, SW_UINT32, 4, SW_PARAM_IN, "VSI value"), - -#define SW_API_PORT_VSI_GET_DESC \ - SW_PARAM_DEF(SW_API_PORT_VSI_GET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \ - SW_PARAM_DEF(SW_API_PORT_VSI_GET, SW_UINT32, 4, SW_PARAM_IN, "Port ID"), \ - SW_PARAM_DEF(SW_API_PORT_VSI_GET, SW_UINT32, 4, SW_PARAM_PTR|SW_PARAM_OUT, "VSI value"), - -#define SW_API_PORT_VLAN_VSI_SET_DESC \ - SW_PARAM_DEF(SW_API_PORT_VLAN_VSI_SET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \ - SW_PARAM_DEF(SW_API_PORT_VLAN_VSI_SET, SW_UINT32, 4, SW_PARAM_IN, "Port ID"), \ - SW_PARAM_DEF(SW_API_PORT_VLAN_VSI_SET, SW_UINT32, 4, SW_PARAM_IN, "STAG VID"), \ - SW_PARAM_DEF(SW_API_PORT_VLAN_VSI_SET, SW_UINT32, 4, SW_PARAM_IN, "CTAG VID"), \ - SW_PARAM_DEF(SW_API_PORT_VLAN_VSI_SET, SW_UINT32, 4, SW_PARAM_IN, "VSI value"), - -#define SW_API_PORT_VLAN_VSI_GET_DESC \ - SW_PARAM_DEF(SW_API_PORT_VLAN_VSI_GET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \ - SW_PARAM_DEF(SW_API_PORT_VLAN_VSI_GET, SW_UINT32, 4, SW_PARAM_IN, "Port ID"), \ - SW_PARAM_DEF(SW_API_PORT_VLAN_VSI_GET, SW_UINT32, 4, SW_PARAM_IN, "STAG VID"), \ - SW_PARAM_DEF(SW_API_PORT_VLAN_VSI_GET, SW_UINT32, 4, SW_PARAM_IN, "CTAG VID"), \ - SW_PARAM_DEF(SW_API_PORT_VLAN_VSI_GET, SW_UINT32, 4, SW_PARAM_PTR|SW_PARAM_OUT, "VSI value"), - -#define SW_API_VSI_TBL_DUMP_DESC \ - SW_PARAM_DEF(SW_API_VSI_TBL_DUMP, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), - -#define SW_API_VSI_NEWADDR_LRN_GET_DESC \ - SW_PARAM_DEF(SW_API_VSI_NEWADDR_LRN_GET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \ - SW_PARAM_DEF(SW_API_VSI_NEWADDR_LRN_GET, SW_UINT32, 4, SW_PARAM_IN, "VSI ID"), \ - SW_PARAM_DEF(SW_API_VSI_NEWADDR_LRN_GET, SW_VSI_NEWADDR_LRN, \ - sizeof(fal_vsi_newaddr_lrn_t), SW_PARAM_PTR|SW_PARAM_OUT, "newaddr_lrn"), - -#define SW_API_VSI_NEWADDR_LRN_SET_DESC \ - SW_PARAM_DEF(SW_API_VSI_NEWADDR_LRN_SET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \ - SW_PARAM_DEF(SW_API_VSI_NEWADDR_LRN_SET, SW_UINT32, 4, SW_PARAM_IN, "VSI ID"), \ - SW_PARAM_DEF(SW_API_VSI_NEWADDR_LRN_SET, SW_VSI_NEWADDR_LRN, \ - sizeof(fal_vsi_newaddr_lrn_t), SW_PARAM_PTR|SW_PARAM_IN, "newaddr_lrn"), - -#define SW_API_VSI_STAMOVE_SET_DESC \ - SW_PARAM_DEF(SW_API_VSI_STAMOVE_SET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \ - SW_PARAM_DEF(SW_API_VSI_STAMOVE_SET, SW_UINT32, 4, SW_PARAM_IN, "VSI ID"), \ - SW_PARAM_DEF(SW_API_VSI_STAMOVE_SET, SW_VSI_STAMOVE, \ - sizeof(fal_vsi_stamove_t), SW_PARAM_PTR|SW_PARAM_IN, "stamove"), - -#define SW_API_VSI_STAMOVE_GET_DESC \ - SW_PARAM_DEF(SW_API_VSI_STAMOVE_GET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \ - SW_PARAM_DEF(SW_API_VSI_STAMOVE_GET, SW_UINT32, 4, SW_PARAM_IN, "VSI ID"), \ - SW_PARAM_DEF(SW_API_VSI_STAMOVE_GET, SW_VSI_STAMOVE, \ - sizeof(fal_vsi_stamove_t), SW_PARAM_PTR|SW_PARAM_OUT, "stamove"), - -#define SW_API_VSI_MEMBER_SET_DESC \ - SW_PARAM_DEF(SW_API_VSI_MEMBER_SET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \ - SW_PARAM_DEF(SW_API_VSI_MEMBER_SET, SW_UINT32, 4, SW_PARAM_IN, "VSI ID"), \ - SW_PARAM_DEF(SW_API_VSI_MEMBER_SET, SW_VSI_MEMBER, \ - sizeof(fal_vsi_member_t), SW_PARAM_PTR|SW_PARAM_IN, "members"), - -#define SW_API_VSI_MEMBER_GET_DESC \ - SW_PARAM_DEF(SW_API_VSI_MEMBER_GET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \ - SW_PARAM_DEF(SW_API_VSI_MEMBER_GET, SW_UINT32, 4, SW_PARAM_IN, "VSI ID"), \ - SW_PARAM_DEF(SW_API_VSI_MEMBER_GET, SW_VSI_MEMBER, \ - sizeof(fal_vsi_member_t), SW_PARAM_PTR|SW_PARAM_OUT, "members"), - -#define SW_API_VSI_COUNTER_GET_DESC \ - SW_PARAM_DEF(SW_API_VSI_COUNTER_GET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \ - SW_PARAM_DEF(SW_API_VSI_COUNTER_GET, SW_UINT32, 4, SW_PARAM_IN, "VSI ID"), \ - SW_PARAM_DEF(SW_API_VSI_COUNTER_GET, SW_VSI_COUNTER, \ - sizeof(fal_vsi_counter_t), SW_PARAM_PTR|SW_PARAM_OUT, "counter"), - -#define SW_API_VSI_COUNTER_CLEANUP_DESC \ - SW_PARAM_DEF(SW_API_VSI_COUNTER_CLEANUP, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \ - SW_PARAM_DEF(SW_API_VSI_COUNTER_CLEANUP, SW_UINT32, 4, SW_PARAM_IN, "VSI ID"), - -#define SW_API_UCAST_QUEUE_BASE_PROFILE_SET_DESC \ - SW_PARAM_DEF(SW_API_UCAST_QUEUE_BASE_PROFILE_SET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \ - SW_PARAM_DEF(SW_API_UCAST_QUEUE_BASE_PROFILE_SET, SW_UCAST_QUEUE_MAP, \ - sizeof(fal_ucast_queue_dest_t), SW_PARAM_PTR|SW_PARAM_IN, "queue dest"), \ - SW_PARAM_DEF(SW_API_UCAST_QUEUE_BASE_PROFILE_SET, SW_UINT32, 4, SW_PARAM_IN, "Queue base"), \ - SW_PARAM_DEF(SW_API_UCAST_QUEUE_BASE_PROFILE_SET, SW_UINT8, 1, SW_PARAM_IN, "Profile"), - -#define SW_API_UCAST_QUEUE_BASE_PROFILE_GET_DESC \ - SW_PARAM_DEF(SW_API_UCAST_QUEUE_BASE_PROFILE_GET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \ - SW_PARAM_DEF(SW_API_UCAST_QUEUE_BASE_PROFILE_GET, SW_UCAST_QUEUE_MAP, \ - sizeof(fal_ucast_queue_dest_t), SW_PARAM_PTR|SW_PARAM_IN, "queue dest"), \ - SW_PARAM_DEF(SW_API_UCAST_QUEUE_BASE_PROFILE_GET, SW_UINT32, 4, \ - SW_PARAM_PTR|SW_PARAM_OUT, "Queue base"), \ - SW_PARAM_DEF(SW_API_UCAST_QUEUE_BASE_PROFILE_GET, SW_UINT8, 1, \ - SW_PARAM_PTR|SW_PARAM_OUT, "Profile"), - -#define SW_API_UCAST_PRIORITY_CLASS_SET_DESC \ - SW_PARAM_DEF(SW_API_UCAST_PRIORITY_CLASS_SET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \ - SW_PARAM_DEF(SW_API_UCAST_PRIORITY_CLASS_SET, SW_UINT8, 1, SW_PARAM_IN, "Profile"), \ - SW_PARAM_DEF(SW_API_UCAST_PRIORITY_CLASS_SET, SW_UINT8, 1, SW_PARAM_IN, "Priority"), \ - SW_PARAM_DEF(SW_API_UCAST_PRIORITY_CLASS_SET, SW_UINT8, 1, SW_PARAM_IN, "Class"), - -#define SW_API_UCAST_PRIORITY_CLASS_GET_DESC \ - SW_PARAM_DEF(SW_API_UCAST_PRIORITY_CLASS_GET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \ - SW_PARAM_DEF(SW_API_UCAST_PRIORITY_CLASS_GET, SW_UINT8, 1, SW_PARAM_IN, "Profile"), \ - SW_PARAM_DEF(SW_API_UCAST_PRIORITY_CLASS_GET, SW_UINT8, 1, SW_PARAM_IN, "Priority"), \ - SW_PARAM_DEF(SW_API_UCAST_PRIORITY_CLASS_GET, SW_UINT8, 1, SW_PARAM_PTR|SW_PARAM_OUT, "Class"), - -#define SW_API_UCAST_HASH_MAP_SET_DESC \ - SW_PARAM_DEF(SW_API_UCAST_HASH_MAP_SET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \ - SW_PARAM_DEF(SW_API_UCAST_HASH_MAP_SET, SW_UINT8, 1, SW_PARAM_IN, "Profile"), \ - SW_PARAM_DEF(SW_API_UCAST_HASH_MAP_SET, SW_UINT8, 1, SW_PARAM_IN, "Rss hash"), \ - SW_PARAM_DEF(SW_API_UCAST_HASH_MAP_SET, SW_UINT8, 1, SW_PARAM_IN, "Queue hash"), - -#define SW_API_UCAST_HASH_MAP_GET_DESC \ - SW_PARAM_DEF(SW_API_UCAST_HASH_MAP_GET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \ - SW_PARAM_DEF(SW_API_UCAST_HASH_MAP_GET, SW_UINT8, 1, SW_PARAM_IN, "Profile"), \ - SW_PARAM_DEF(SW_API_UCAST_HASH_MAP_GET, SW_UINT8, 1, SW_PARAM_IN, "Rss hash"), \ - SW_PARAM_DEF(SW_API_UCAST_HASH_MAP_GET, SW_UINT8, 1, SW_PARAM_PTR|SW_PARAM_OUT, "Queue hash"), - -#define SW_API_MCAST_CPUCODE_CLASS_SET_DESC \ - SW_PARAM_DEF(SW_API_MCAST_CPUCODE_CLASS_SET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \ - SW_PARAM_DEF(SW_API_MCAST_CPUCODE_CLASS_SET, SW_UINT8, 1, SW_PARAM_IN, "Cpu code"), \ - SW_PARAM_DEF(SW_API_MCAST_CPUCODE_CLASS_SET, SW_UINT8, 1, SW_PARAM_IN, "Queue Class"), - -#define SW_API_MCAST_CPUCODE_CLASS_GET_DESC \ - SW_PARAM_DEF(SW_API_MCAST_CPUCODE_CLASS_GET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \ - SW_PARAM_DEF(SW_API_MCAST_CPUCODE_CLASS_GET, SW_UINT8, 1, SW_PARAM_IN, "Cpu code"), \ - SW_PARAM_DEF(SW_API_MCAST_CPUCODE_CLASS_GET, SW_UINT8, 1, \ - SW_PARAM_PTR|SW_PARAM_OUT, "Queue Class"), - -#define SW_API_MCAST_PRIORITY_CLASS_SET_DESC \ - SW_PARAM_DEF(SW_API_MCAST_PRIORITY_CLASS_SET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \ - SW_PARAM_DEF(SW_API_MCAST_PRIORITY_CLASS_SET, SW_UINT32, 4, SW_PARAM_IN, "Port ID"), \ - SW_PARAM_DEF(SW_API_MCAST_PRIORITY_CLASS_SET, SW_UINT8, 1, SW_PARAM_IN, "Priority"), \ - SW_PARAM_DEF(SW_API_MCAST_PRIORITY_CLASS_SET, SW_UINT8, 1, SW_PARAM_IN, "Queue Class"), - -#define SW_API_MCAST_PRIORITY_CLASS_GET_DESC \ - SW_PARAM_DEF(SW_API_MCAST_PRIORITY_CLASS_GET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \ - SW_PARAM_DEF(SW_API_MCAST_PRIORITY_CLASS_GET, SW_UINT32, 4, SW_PARAM_IN, "Port ID"), \ - SW_PARAM_DEF(SW_API_MCAST_PRIORITY_CLASS_GET, SW_UINT8, 1, SW_PARAM_IN, "Priority"), \ - SW_PARAM_DEF(SW_API_MCAST_PRIORITY_CLASS_GET, SW_UINT8, 1, \ - SW_PARAM_PTR|SW_PARAM_OUT, "Queue Class"), - -#define SW_API_QUEUE_FLUSH_DESC \ - SW_PARAM_DEF(SW_API_QUEUE_FLUSH, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \ - SW_PARAM_DEF(SW_API_QUEUE_FLUSH, SW_UINT32, 4, SW_PARAM_IN, "Port ID"), \ - SW_PARAM_DEF(SW_API_QUEUE_FLUSH, SW_UINT16, 2, SW_PARAM_IN, "queue ID"), - -#define SW_API_UCAST_DFLT_HASH_MAP_SET_DESC \ - SW_PARAM_DEF(SW_API_UCAST_DFLT_HASH_MAP_SET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \ - SW_PARAM_DEF(SW_API_UCAST_DFLT_HASH_MAP_SET, SW_UINT8, 1, SW_PARAM_IN, "ucast dflt hash"), - -#define SW_API_UCAST_DFLT_HASH_MAP_GET_DESC \ - SW_PARAM_DEF(SW_API_UCAST_DFLT_HASH_MAP_GET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \ - SW_PARAM_DEF(SW_API_UCAST_DFLT_HASH_MAP_GET, SW_UINT8, 1, \ - SW_PARAM_PTR|SW_PARAM_OUT, "ucast dflt hash"), - -#define SW_API_AC_CTRL_SET_DESC \ - SW_PARAM_DEF(SW_API_AC_CTRL_SET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \ - SW_PARAM_DEF(SW_API_AC_CTRL_SET, SW_AC_OBJ, \ - sizeof(fal_ac_obj_t), SW_PARAM_PTR|SW_PARAM_IN, "ac obj"), \ - SW_PARAM_DEF(SW_API_AC_CTRL_SET, SW_AC_CTRL, \ - sizeof(fal_ac_ctrl_t), SW_PARAM_PTR|SW_PARAM_IN, "ac ctrl"), - -#define SW_API_AC_CTRL_GET_DESC \ - SW_PARAM_DEF(SW_API_AC_CTRL_GET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \ - SW_PARAM_DEF(SW_API_AC_CTRL_GET, SW_AC_OBJ, \ - sizeof(fal_ac_obj_t), SW_PARAM_PTR|SW_PARAM_IN, "AC obj"), \ - SW_PARAM_DEF(SW_API_AC_CTRL_GET, SW_AC_CTRL, \ - sizeof(fal_ac_ctrl_t), SW_PARAM_PTR|SW_PARAM_OUT, "ac ctrl"), - -#define SW_API_AC_PRE_BUFFER_SET_DESC \ - SW_PARAM_DEF(SW_API_AC_PRE_BUFFER_SET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \ - SW_PARAM_DEF(SW_API_AC_PRE_BUFFER_SET, SW_AC_OBJ, \ - sizeof(fal_ac_obj_t), SW_PARAM_PTR|SW_PARAM_IN, "AC obj"), \ - SW_PARAM_DEF(SW_API_AC_PRE_BUFFER_SET, SW_UINT16, 2, SW_PARAM_IN, "num"), - -#define SW_API_AC_PRE_BUFFER_GET_DESC \ - SW_PARAM_DEF(SW_API_AC_PRE_BUFFER_GET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \ - SW_PARAM_DEF(SW_API_AC_PRE_BUFFER_GET, SW_AC_OBJ, \ - sizeof(fal_ac_obj_t), SW_PARAM_PTR|SW_PARAM_IN, "AC obj"), \ - SW_PARAM_DEF(SW_API_AC_PRE_BUFFER_GET, SW_UINT16, 2, SW_PARAM_PTR|SW_PARAM_OUT, "num"), - -#define SW_API_QUEUE_GROUP_SET_DESC \ - SW_PARAM_DEF(SW_API_QUEUE_GROUP_SET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \ - SW_PARAM_DEF(SW_API_QUEUE_GROUP_SET, SW_UINT32, 4, SW_PARAM_IN, "queue id"), \ - SW_PARAM_DEF(SW_API_QUEUE_GROUP_SET, SW_UINT8, 1, SW_PARAM_IN, "group id"), - -#define SW_API_QUEUE_GROUP_GET_DESC \ - SW_PARAM_DEF(SW_API_QUEUE_GROUP_GET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \ - SW_PARAM_DEF(SW_API_QUEUE_GROUP_GET, SW_UINT32, 4, SW_PARAM_IN, "queue id"), \ - SW_PARAM_DEF(SW_API_QUEUE_GROUP_GET, SW_UINT8, 1, SW_PARAM_PTR|SW_PARAM_OUT, "group id"), - -#define SW_API_STATIC_THRESH_SET_DESC \ - SW_PARAM_DEF(SW_API_STATIC_THRESH_SET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \ - SW_PARAM_DEF(SW_API_STATIC_THRESH_SET, SW_AC_OBJ, \ - sizeof(fal_ac_obj_t), SW_PARAM_PTR|SW_PARAM_IN, "AC obj"), \ - SW_PARAM_DEF(SW_API_STATIC_THRESH_SET, SW_STATIC_THRESH, \ - sizeof(fal_ac_static_threshold_t), SW_PARAM_PTR|SW_PARAM_IN, "static thresh"), - -#define SW_API_STATIC_THRESH_GET_DESC \ - SW_PARAM_DEF(SW_API_STATIC_THRESH_GET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \ - SW_PARAM_DEF(SW_API_STATIC_THRESH_GET, SW_AC_OBJ, \ - sizeof(fal_ac_obj_t), SW_PARAM_PTR|SW_PARAM_IN, "AC obj"), \ - SW_PARAM_DEF(SW_API_STATIC_THRESH_GET, SW_STATIC_THRESH, \ - sizeof(fal_ac_static_threshold_t), SW_PARAM_PTR|SW_PARAM_OUT, "static thresh"), - -#define SW_API_DYNAMIC_THRESH_SET_DESC \ - SW_PARAM_DEF(SW_API_DYNAMIC_THRESH_SET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \ - SW_PARAM_DEF(SW_API_DYNAMIC_THRESH_SET, SW_UINT32, 4, SW_PARAM_IN, "queue id"), \ - SW_PARAM_DEF(SW_API_DYNAMIC_THRESH_SET, SW_DYNAMIC_THRESH, \ - sizeof(fal_ac_dynamic_threshold_t), SW_PARAM_PTR|SW_PARAM_IN, \ - "dynamic thresh"), - -#define SW_API_DYNAMIC_THRESH_GET_DESC \ - SW_PARAM_DEF(SW_API_DYNAMIC_THRESH_GET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \ - SW_PARAM_DEF(SW_API_DYNAMIC_THRESH_GET, SW_UINT32, 4, SW_PARAM_IN, "queue id"), \ - SW_PARAM_DEF(SW_API_DYNAMIC_THRESH_GET, SW_DYNAMIC_THRESH, \ - sizeof(fal_ac_dynamic_threshold_t), SW_PARAM_PTR|SW_PARAM_OUT, \ - "dynamic thresh"), - -#define SW_API_GOURP_BUFFER_SET_DESC \ - SW_PARAM_DEF(SW_API_GOURP_BUFFER_SET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \ - SW_PARAM_DEF(SW_API_GOURP_BUFFER_SET, SW_UINT8, 1, SW_PARAM_IN, "group"), \ - SW_PARAM_DEF(SW_API_GOURP_BUFFER_SET, SW_GROUP_BUFFER, \ - sizeof(fal_ac_group_buffer_t), SW_PARAM_PTR|SW_PARAM_IN, "buffer cfg"), - -#define SW_API_GOURP_BUFFER_GET_DESC \ - SW_PARAM_DEF(SW_API_GOURP_BUFFER_GET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \ - SW_PARAM_DEF(SW_API_GOURP_BUFFER_GET, SW_UINT8, 1, SW_PARAM_IN, "group"), \ - SW_PARAM_DEF(SW_API_GOURP_BUFFER_GET, SW_GROUP_BUFFER, \ - sizeof(fal_ac_group_buffer_t), SW_PARAM_PTR|SW_PARAM_OUT, "buffer cfg"), - -#define SW_API_QUEUE_CNT_CTRL_GET_DESC \ - SW_PARAM_DEF(SW_API_QUEUE_CNT_CTRL_GET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \ - SW_PARAM_DEF(SW_API_QUEUE_CNT_CTRL_GET, SW_ENABLE, \ - sizeof(a_bool_t), SW_PARAM_PTR|SW_PARAM_OUT, "queue cnt en"), - -#define SW_API_QUEUE_CNT_CTRL_SET_DESC \ - SW_PARAM_DEF(SW_API_QUEUE_CNT_CTRL_SET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \ - SW_PARAM_DEF(SW_API_QUEUE_CNT_CTRL_SET, SW_ENABLE, \ - sizeof(a_bool_t), SW_PARAM_IN, "queue cnt en"), - -#define SW_API_QUEUE_CNT_CLEANUP_DESC \ - SW_PARAM_DEF(SW_API_QUEUE_CNT_CLEANUP, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \ - SW_PARAM_DEF(SW_API_QUEUE_CNT_CLEANUP, SW_UINT32, 4, SW_PARAM_IN, "queue id"), - -#define SW_API_QUEUE_CNT_GET_DESC \ - SW_PARAM_DEF(SW_API_QUEUE_CNT_GET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \ - SW_PARAM_DEF(SW_API_QUEUE_CNT_GET, SW_UINT32, 4, SW_PARAM_IN, "queue ID"), \ - SW_PARAM_DEF(SW_API_QUEUE_CNT_GET, SW_QM_CNT, \ - sizeof(fal_queue_stats_t), SW_PARAM_PTR|SW_PARAM_OUT, "queue cnt"), - -#define SW_API_QM_ENQUEUE_CTRL_SET_DESC \ - SW_PARAM_DEF(SW_API_QM_ENQUEUE_CTRL_SET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \ - SW_PARAM_DEF(SW_API_QM_ENQUEUE_CTRL_SET, SW_UINT32, 4, SW_PARAM_IN, "queue ID"), \ - SW_PARAM_DEF(SW_API_QM_ENQUEUE_CTRL_SET, SW_ENABLE, \ - sizeof(a_bool_t), SW_PARAM_IN, "enqueue en"), - -#define SW_API_QM_ENQUEUE_CTRL_GET_DESC \ - SW_PARAM_DEF(SW_API_QM_ENQUEUE_CTRL_GET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \ - SW_PARAM_DEF(SW_API_QM_ENQUEUE_CTRL_GET, SW_UINT32, 4, SW_PARAM_IN, "queue ID"), \ - SW_PARAM_DEF(SW_API_QM_ENQUEUE_CTRL_GET, SW_ENABLE, \ - sizeof(a_bool_t), SW_PARAM_PTR|SW_PARAM_OUT, "enqueue en"), - -#define SW_API_QM_SOURCE_PROFILE_SET_DESC \ - SW_PARAM_DEF(SW_API_QM_SOURCE_PROFILE_SET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \ - SW_PARAM_DEF(SW_API_QM_SOURCE_PROFILE_SET, SW_UINT32, 4, SW_PARAM_IN, "Port ID"), \ - SW_PARAM_DEF(SW_API_QM_SOURCE_PROFILE_SET, SW_UINT32, 4, SW_PARAM_IN, "Source profile"), - -#define SW_API_QM_SOURCE_PROFILE_GET_DESC \ - SW_PARAM_DEF(SW_API_QM_SOURCE_PROFILE_GET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \ - SW_PARAM_DEF(SW_API_QM_SOURCE_PROFILE_GET, SW_UINT32, 4, SW_PARAM_IN, "Port ID"), \ - SW_PARAM_DEF(SW_API_QM_SOURCE_PROFILE_GET, SW_UINT32, 4, \ - SW_PARAM_PTR|SW_PARAM_OUT, "Source profile"), - -#define SW_API_MGMTCTRL_ETHTYPE_PROFILE_SET_DESC \ - SW_PARAM_DEF(SW_API_MGMTCTRL_ETHTYPE_PROFILE_SET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \ - SW_PARAM_DEF(SW_API_MGMTCTRL_ETHTYPE_PROFILE_SET, SW_UINT32, 4, SW_PARAM_IN, "Profile ID"), \ - SW_PARAM_DEF(SW_API_MGMTCTRL_ETHTYPE_PROFILE_SET, SW_UINT32, 4, SW_PARAM_IN, "Ethernet Type"), - -#define SW_API_MGMTCTRL_ETHTYPE_PROFILE_GET_DESC \ - SW_PARAM_DEF(SW_API_MGMTCTRL_ETHTYPE_PROFILE_GET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \ - SW_PARAM_DEF(SW_API_MGMTCTRL_ETHTYPE_PROFILE_GET, SW_UINT32, 4, SW_PARAM_IN, "Profile ID"), \ - SW_PARAM_DEF(SW_API_MGMTCTRL_ETHTYPE_PROFILE_GET, SW_UINT32, 4, \ - SW_PARAM_PTR|SW_PARAM_OUT, "Ethernet Type"), - -#define SW_API_MGMTCTRL_RFDB_PROFILE_SET_DESC \ - SW_PARAM_DEF(SW_API_MGMTCTRL_RFDB_PROFILE_SET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \ - SW_PARAM_DEF(SW_API_MGMTCTRL_RFDB_PROFILE_SET, SW_UINT32, 4, SW_PARAM_IN, "Profile ID"), \ - SW_PARAM_DEF(SW_API_MGMTCTRL_RFDB_PROFILE_SET, SW_MACADDR, \ - sizeof(fal_mac_addr_t), SW_PARAM_PTR|SW_PARAM_IN, "Address"), - -#define SW_API_MGMTCTRL_RFDB_PROFILE_GET_DESC \ - SW_PARAM_DEF(SW_API_MGMTCTRL_RFDB_PROFILE_GET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \ - SW_PARAM_DEF(SW_API_MGMTCTRL_RFDB_PROFILE_GET, SW_UINT32, 4, SW_PARAM_IN, "Profile ID"), \ - SW_PARAM_DEF(SW_API_MGMTCTRL_RFDB_PROFILE_GET, SW_MACADDR, \ - sizeof(fal_mac_addr_t), SW_PARAM_PTR|SW_PARAM_OUT, "Address"), - -#define SW_API_MGMTCTRL_CTRLPKT_PROFILE_ADD_DESC \ - SW_PARAM_DEF(SW_API_MGMTCTRL_CTRLPKT_PROFILE_ADD, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \ - SW_PARAM_DEF(SW_API_MGMTCTRL_CTRLPKT_PROFILE_ADD, SW_CTRLPKT_PROFILE, \ - sizeof(fal_ctrlpkt_profile_t), SW_PARAM_PTR|SW_PARAM_IN, "app entry"), - -#define SW_API_MGMTCTRL_CTRLPKT_PROFILE_DEL_DESC \ - SW_PARAM_DEF(SW_API_MGMTCTRL_CTRLPKT_PROFILE_DEL, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \ - SW_PARAM_DEF(SW_API_MGMTCTRL_CTRLPKT_PROFILE_DEL, SW_CTRLPKT_PROFILE, \ - sizeof(fal_ctrlpkt_profile_t), SW_PARAM_PTR|SW_PARAM_IN, "app entry"), - -#define SW_API_MGMTCTRL_CTRLPKT_PROFILE_GETFIRST_DESC \ - SW_PARAM_DEF(SW_API_MGMTCTRL_CTRLPKT_PROFILE_GETFIRST, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \ - SW_PARAM_DEF(SW_API_MGMTCTRL_CTRLPKT_PROFILE_GETFIRST, SW_CTRLPKT_PROFILE, \ - sizeof(fal_ctrlpkt_profile_t), SW_PARAM_PTR|SW_PARAM_OUT, "app entry"), - -#define SW_API_MGMTCTRL_CTRLPKT_PROFILE_GETNEXT_DESC \ - SW_PARAM_DEF(SW_API_MGMTCTRL_CTRLPKT_PROFILE_GETNEXT, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \ - SW_PARAM_DEF(SW_API_MGMTCTRL_CTRLPKT_PROFILE_GETNEXT, SW_CTRLPKT_PROFILE, \ - sizeof(fal_ctrlpkt_profile_t), SW_PARAM_PTR|SW_PARAM_IN|SW_PARAM_OUT, \ - "app entry"), - -#define SW_API_SERVCODE_CONFIG_SET_DESC \ - SW_PARAM_DEF(SW_API_SERVCODE_CONFIG_SET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \ - SW_PARAM_DEF(SW_API_SERVCODE_CONFIG_SET, SW_UINT32, 4, SW_PARAM_IN, "Index"), \ - SW_PARAM_DEF(SW_API_SERVCODE_CONFIG_SET, SW_SERVCODE_CONFIG, \ - sizeof(fal_servcode_config_t), SW_PARAM_PTR|SW_PARAM_IN, "Servcode Config"), - -#define SW_API_SERVCODE_CONFIG_GET_DESC \ - SW_PARAM_DEF(SW_API_SERVCODE_CONFIG_GET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \ - SW_PARAM_DEF(SW_API_SERVCODE_CONFIG_GET, SW_UINT32, 4, SW_PARAM_IN, "Index"), \ - SW_PARAM_DEF(SW_API_SERVCODE_CONFIG_GET, SW_SERVCODE_CONFIG, \ - sizeof(fal_servcode_config_t), SW_PARAM_PTR|SW_PARAM_OUT, "Servcode Config"), - -#define SW_API_SERVCODE_LOOPCHECK_EN_DESC \ - SW_PARAM_DEF(SW_API_SERVCODE_LOOPCHECK_EN, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \ - SW_PARAM_DEF(SW_API_SERVCODE_LOOPCHECK_EN, SW_ENABLE, 4, SW_PARAM_IN, "Enable"), - -#define SW_API_SERVCODE_LOOPCHECK_STATUS_GET_DESC \ - SW_PARAM_DEF(SW_API_SERVCODE_LOOPCHECK_STATUS_GET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \ - SW_PARAM_DEF(SW_API_SERVCODE_LOOPCHECK_STATUS_GET, SW_ENABLE, 4, \ - SW_PARAM_PTR|SW_PARAM_OUT, "Enable"), - -#define SW_API_BM_CTRL_SET_DESC \ - SW_PARAM_DEF(SW_API_BM_CTRL_SET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \ - SW_PARAM_DEF(SW_API_BM_CTRL_SET, SW_UINT32, 4, SW_PARAM_IN, "port id"), \ - SW_PARAM_DEF(SW_API_BM_CTRL_SET, SW_ENABLE, 4, SW_PARAM_IN, "bm ctrl"), - -#define SW_API_BM_CTRL_GET_DESC \ - SW_PARAM_DEF(SW_API_BM_CTRL_GET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \ - SW_PARAM_DEF(SW_API_BM_CTRL_GET, SW_UINT32, 4, SW_PARAM_IN, "port id"), \ - SW_PARAM_DEF(SW_API_BM_CTRL_GET, SW_ENABLE, 4, SW_PARAM_PTR|SW_PARAM_OUT, "bm ctrl"), - -#define SW_API_BM_PORTGROUP_MAP_SET_DESC \ - SW_PARAM_DEF(SW_API_BM_PORTGROUP_MAP_SET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \ - SW_PARAM_DEF(SW_API_BM_PORTGROUP_MAP_SET, SW_UINT32, 4, SW_PARAM_IN, "port id"), \ - SW_PARAM_DEF(SW_API_BM_PORTGROUP_MAP_SET, SW_UINT8, 4, SW_PARAM_IN, "group"), - -#define SW_API_BM_PORTGROUP_MAP_GET_DESC \ - SW_PARAM_DEF(SW_API_BM_PORTGROUP_MAP_GET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \ - SW_PARAM_DEF(SW_API_BM_PORTGROUP_MAP_GET, SW_UINT32, 4, SW_PARAM_IN, "port id"), \ - SW_PARAM_DEF(SW_API_BM_PORTGROUP_MAP_GET, SW_UINT8, 4, SW_PARAM_PTR|SW_PARAM_OUT, "group"), - -#define SW_API_BM_GROUP_BUFFER_SET_DESC \ - SW_PARAM_DEF(SW_API_BM_GROUP_BUFFER_SET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \ - SW_PARAM_DEF(SW_API_BM_GROUP_BUFFER_SET, SW_UINT8, 1, SW_PARAM_IN, "group id"), \ - SW_PARAM_DEF(SW_API_BM_GROUP_BUFFER_SET, SW_UINT16, 2, SW_PARAM_IN, "buff num"), - -#define SW_API_BM_GROUP_BUFFER_GET_DESC \ - SW_PARAM_DEF(SW_API_BM_GROUP_BUFFER_GET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \ - SW_PARAM_DEF(SW_API_BM_GROUP_BUFFER_GET, SW_UINT8, 1, SW_PARAM_IN, "group id"), \ - SW_PARAM_DEF(SW_API_BM_GROUP_BUFFER_GET, SW_UINT16, 2, SW_PARAM_PTR|SW_PARAM_OUT, "buff num"), - -#define SW_API_BM_PORT_RSVBUFFER_SET_DESC \ - SW_PARAM_DEF(SW_API_BM_PORT_RSVBUFFER_SET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \ - SW_PARAM_DEF(SW_API_BM_PORT_RSVBUFFER_SET, SW_UINT32, 4, SW_PARAM_IN, "port id"), \ - SW_PARAM_DEF(SW_API_BM_PORT_RSVBUFFER_SET, SW_UINT16, 2, SW_PARAM_IN, "prealloc buff"), \ - SW_PARAM_DEF(SW_API_BM_PORT_RSVBUFFER_SET, SW_UINT16, 2, SW_PARAM_IN, "react buff"), - -#define SW_API_BM_PORT_RSVBUFFER_GET_DESC \ - SW_PARAM_DEF(SW_API_BM_PORT_RSVBUFFER_GET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \ - SW_PARAM_DEF(SW_API_BM_PORT_RSVBUFFER_GET, SW_UINT32, 4, SW_PARAM_IN, "port id"), \ - SW_PARAM_DEF(SW_API_BM_PORT_RSVBUFFER_GET, SW_UINT16, 2, \ - SW_PARAM_PTR|SW_PARAM_OUT, "prealloc buff"), \ - SW_PARAM_DEF(SW_API_BM_PORT_RSVBUFFER_GET, SW_UINT16, 2, \ - SW_PARAM_PTR|SW_PARAM_OUT, "react buff"), - -#define SW_API_BM_STATIC_THRESH_SET_DESC \ - SW_PARAM_DEF(SW_API_BM_STATIC_THRESH_SET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \ - SW_PARAM_DEF(SW_API_BM_STATIC_THRESH_SET, SW_UINT32, 4, SW_PARAM_IN, "port id"), \ - SW_PARAM_DEF(SW_API_BM_STATIC_THRESH_SET, SW_BMSTHRESH, \ - sizeof(fal_bm_static_cfg_t), SW_PARAM_PTR|SW_PARAM_IN, "static thresh"), - -#define SW_API_BM_STATIC_THRESH_GET_DESC \ - SW_PARAM_DEF(SW_API_BM_STATIC_THRESH_GET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \ - SW_PARAM_DEF(SW_API_BM_STATIC_THRESH_GET, SW_UINT32, 4, SW_PARAM_IN, "port id"), \ - SW_PARAM_DEF(SW_API_BM_STATIC_THRESH_GET, SW_BMSTHRESH, \ - sizeof(fal_bm_static_cfg_t), SW_PARAM_PTR|SW_PARAM_OUT, "static thresh"), - -#define SW_API_BM_DYNAMIC_THRESH_SET_DESC \ - SW_PARAM_DEF(SW_API_BM_DYNAMIC_THRESH_SET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \ - SW_PARAM_DEF(SW_API_BM_DYNAMIC_THRESH_SET, SW_UINT32, 4, SW_PARAM_IN, "port id"), \ - SW_PARAM_DEF(SW_API_BM_DYNAMIC_THRESH_SET, SW_BMDTHRESH, \ - sizeof(fal_bm_dynamic_cfg_t), SW_PARAM_PTR|SW_PARAM_IN, "dynamic thresh"), - -#define SW_API_BM_DYNAMIC_THRESH_GET_DESC \ - SW_PARAM_DEF(SW_API_BM_DYNAMIC_THRESH_GET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \ - SW_PARAM_DEF(SW_API_BM_DYNAMIC_THRESH_GET, SW_UINT32, 4, SW_PARAM_IN, "port id"), \ - SW_PARAM_DEF(SW_API_BM_DYNAMIC_THRESH_GET, SW_BMDTHRESH, \ - sizeof(fal_bm_dynamic_cfg_t), SW_PARAM_PTR|SW_PARAM_OUT, "dynamic thresh"), - -#define SW_API_BM_PORT_COUNTER_GET_DESC \ - SW_PARAM_DEF(SW_API_BM_PORT_COUNTER_GET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \ - SW_PARAM_DEF(SW_API_BM_PORT_COUNTER_GET, SW_UINT32, 4, SW_PARAM_IN, "port id"), \ - SW_PARAM_DEF(SW_API_BM_PORT_COUNTER_GET, SW_BMPORTCNT, \ - sizeof(fal_bm_port_counter_t), SW_PARAM_PTR|SW_PARAM_OUT, "port counter"), - -#define SW_API_PORT_SHAPER_TIMESLOT_SET_DESC \ - SW_PARAM_DEF(SW_API_PORT_SHAPER_TIMESLOT_SET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \ - SW_PARAM_DEF(SW_API_PORT_SHAPER_TIMESLOT_SET, SW_UINT32, 4, SW_PARAM_IN, "Time Slot"), - -#define SW_API_PORT_SHAPER_TIMESLOT_GET_DESC \ - SW_PARAM_DEF(SW_API_PORT_SHAPER_TIMESLOT_GET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \ - SW_PARAM_DEF(SW_API_PORT_SHAPER_TIMESLOT_GET, SW_UINT32, 4, \ - SW_PARAM_PTR|SW_PARAM_OUT, "Time Slot"), - -#define SW_API_FLOW_SHAPER_TIMESLOT_SET_DESC \ - SW_PARAM_DEF(SW_API_FLOW_SHAPER_TIMESLOT_SET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \ - SW_PARAM_DEF(SW_API_FLOW_SHAPER_TIMESLOT_SET, SW_UINT32, 4, SW_PARAM_IN, "Time Slot"), - -#define SW_API_FLOW_SHAPER_TIMESLOT_GET_DESC \ - SW_PARAM_DEF(SW_API_FLOW_SHAPER_TIMESLOT_GET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \ - SW_PARAM_DEF(SW_API_FLOW_SHAPER_TIMESLOT_GET, SW_UINT32, 4, \ - SW_PARAM_PTR|SW_PARAM_OUT, "Time Slot"), - -#define SW_API_QUEUE_SHAPER_TIMESLOT_SET_DESC \ - SW_PARAM_DEF(SW_API_QUEUE_SHAPER_TIMESLOT_SET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \ - SW_PARAM_DEF(SW_API_QUEUE_SHAPER_TIMESLOT_SET, SW_UINT32, 4, SW_PARAM_IN, "Time Slot"), - -#define SW_API_QUEUE_SHAPER_TIMESLOT_GET_DESC \ - SW_PARAM_DEF(SW_API_QUEUE_SHAPER_TIMESLOT_GET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \ - SW_PARAM_DEF(SW_API_QUEUE_SHAPER_TIMESLOT_GET, SW_UINT32, 4, \ - SW_PARAM_PTR|SW_PARAM_OUT, "Time Slot"), - -#define SW_API_PORT_SHAPER_TOKEN_NUMBER_SET_DESC \ - SW_PARAM_DEF(SW_API_PORT_SHAPER_TOKEN_NUMBER_SET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \ - SW_PARAM_DEF(SW_API_PORT_SHAPER_TOKEN_NUMBER_SET, SW_UINT32, 4, SW_PARAM_IN, "Port ID"), \ - SW_PARAM_DEF(SW_API_PORT_SHAPER_TOKEN_NUMBER_SET, SW_PORT_SHAPER_TOKEN_CONFIG, \ - sizeof(fal_shaper_token_number_t), SW_PARAM_PTR|SW_PARAM_IN, "CONFIG"), - -#define SW_API_PORT_SHAPER_TOKEN_NUMBER_GET_DESC \ - SW_PARAM_DEF(SW_API_PORT_SHAPER_TOKEN_NUMBER_GET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \ - SW_PARAM_DEF(SW_API_PORT_SHAPER_TOKEN_NUMBER_GET, SW_UINT32, 4, SW_PARAM_IN, "Port ID"), \ - SW_PARAM_DEF(SW_API_PORT_SHAPER_TOKEN_NUMBER_GET, SW_PORT_SHAPER_TOKEN_CONFIG, \ - sizeof(fal_shaper_token_number_t), SW_PARAM_PTR|SW_PARAM_OUT, "CONFIG"), - -#define SW_API_FLOW_SHAPER_TOKEN_NUMBER_SET_DESC \ - SW_PARAM_DEF(SW_API_FLOW_SHAPER_TOKEN_NUMBER_SET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \ - SW_PARAM_DEF(SW_API_FLOW_SHAPER_TOKEN_NUMBER_SET, SW_UINT32, 4, SW_PARAM_IN, "Flow ID"), \ - SW_PARAM_DEF(SW_API_FLOW_SHAPER_TOKEN_NUMBER_SET, SW_SHAPER_TOKEN_CONFIG, \ - sizeof(fal_shaper_token_number_t), SW_PARAM_PTR|SW_PARAM_IN, "CONFIG"), - -#define SW_API_FLOW_SHAPER_TOKEN_NUMBER_GET_DESC \ - SW_PARAM_DEF(SW_API_FLOW_SHAPER_TOKEN_NUMBER_GET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \ - SW_PARAM_DEF(SW_API_FLOW_SHAPER_TOKEN_NUMBER_GET, SW_UINT32, 4, SW_PARAM_IN, "Flow ID"), \ - SW_PARAM_DEF(SW_API_FLOW_SHAPER_TOKEN_NUMBER_GET, SW_SHAPER_TOKEN_CONFIG, \ - sizeof(fal_shaper_token_number_t), SW_PARAM_PTR|SW_PARAM_OUT, "CONFIG"), - -#define SW_API_QUEUE_SHAPER_TOKEN_NUMBER_SET_DESC \ - SW_PARAM_DEF(SW_API_QUEUE_SHAPER_TOKEN_NUMBER_SET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \ - SW_PARAM_DEF(SW_API_QUEUE_SHAPER_TOKEN_NUMBER_SET, SW_UINT32, 4, SW_PARAM_IN, "Queue ID"), \ - SW_PARAM_DEF(SW_API_QUEUE_SHAPER_TOKEN_NUMBER_SET, SW_SHAPER_TOKEN_CONFIG, \ - sizeof(fal_shaper_token_number_t), SW_PARAM_PTR|SW_PARAM_IN, "CONFIG"), - -#define SW_API_QUEUE_SHAPER_TOKEN_NUMBER_GET_DESC \ - SW_PARAM_DEF(SW_API_QUEUE_SHAPER_TOKEN_NUMBER_GET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \ - SW_PARAM_DEF(SW_API_QUEUE_SHAPER_TOKEN_NUMBER_GET, SW_UINT32, 4, SW_PARAM_IN, "Queue ID"), \ - SW_PARAM_DEF(SW_API_QUEUE_SHAPER_TOKEN_NUMBER_GET, SW_SHAPER_TOKEN_CONFIG, \ - sizeof(fal_shaper_token_number_t), SW_PARAM_PTR|SW_PARAM_OUT, "CONFIG"), - -#define SW_API_PORT_SHAPER_SET_DESC \ - SW_PARAM_DEF(SW_API_PORT_SHAPER_SET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \ - SW_PARAM_DEF(SW_API_PORT_SHAPER_SET, SW_UINT32, 4, SW_PARAM_IN, "Port ID"), \ - SW_PARAM_DEF(SW_API_PORT_SHAPER_SET, SW_PORT_SHAPER_CONFIG, \ - sizeof(fal_shaper_config_t), SW_PARAM_PTR|SW_PARAM_IN, "CONFIG"), - -#define SW_API_PORT_SHAPER_GET_DESC \ - SW_PARAM_DEF(SW_API_PORT_SHAPER_GET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \ - SW_PARAM_DEF(SW_API_PORT_SHAPER_GET, SW_UINT32, 4, SW_PARAM_IN, "Port ID"), \ - SW_PARAM_DEF(SW_API_PORT_SHAPER_GET, SW_PORT_SHAPER_CONFIG, \ - sizeof(fal_shaper_config_t), SW_PARAM_PTR|SW_PARAM_OUT, "CONFIG"), - -#define SW_API_FLOW_SHAPER_SET_DESC \ - SW_PARAM_DEF(SW_API_FLOW_SHAPER_SET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \ - SW_PARAM_DEF(SW_API_FLOW_SHAPER_SET, SW_UINT32, 4, SW_PARAM_IN, "Flow ID"), \ - SW_PARAM_DEF(SW_API_FLOW_SHAPER_SET, SW_SHAPER_CONFIG, \ - sizeof(fal_shaper_config_t), SW_PARAM_PTR|SW_PARAM_IN, "CONFIG"), - -#define SW_API_FLOW_SHAPER_GET_DESC \ - SW_PARAM_DEF(SW_API_FLOW_SHAPER_GET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \ - SW_PARAM_DEF(SW_API_FLOW_SHAPER_GET, SW_UINT32, 4, SW_PARAM_IN, "Flow ID"), \ - SW_PARAM_DEF(SW_API_FLOW_SHAPER_GET, SW_SHAPER_CONFIG, \ - sizeof(fal_shaper_config_t), SW_PARAM_PTR|SW_PARAM_OUT, "CONFIG"), - -#define SW_API_QUEUE_SHAPER_SET_DESC \ - SW_PARAM_DEF(SW_API_QUEUE_SHAPER_SET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \ - SW_PARAM_DEF(SW_API_QUEUE_SHAPER_SET, SW_UINT32, 4, SW_PARAM_IN, "Queue ID"), \ - SW_PARAM_DEF(SW_API_QUEUE_SHAPER_SET, SW_SHAPER_CONFIG, \ - sizeof(fal_shaper_config_t), SW_PARAM_PTR|SW_PARAM_IN, "CONFIG"), - -#define SW_API_QUEUE_SHAPER_GET_DESC \ - SW_PARAM_DEF(SW_API_QUEUE_SHAPER_GET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \ - SW_PARAM_DEF(SW_API_QUEUE_SHAPER_GET, SW_UINT32, 4, SW_PARAM_IN, "Queue ID"), \ - SW_PARAM_DEF(SW_API_QUEUE_SHAPER_GET, SW_SHAPER_CONFIG, \ - sizeof(fal_shaper_config_t), SW_PARAM_PTR|SW_PARAM_OUT, "CONFIG"), - -#define SW_API_SHAPER_IPG_PRE_SET_DESC \ - SW_PARAM_DEF(SW_API_SHAPER_IPG_PRE_SET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \ - SW_PARAM_DEF(SW_API_SHAPER_IPG_PRE_SET, SW_UINT32, 4, SW_PARAM_IN, "IPG and Preamble"), - -#define SW_API_SHAPER_IPG_PRE_GET_DESC \ - SW_PARAM_DEF(SW_API_SHAPER_IPG_PRE_GET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \ - SW_PARAM_DEF(SW_API_SHAPER_IPG_PRE_GET, SW_UINT32, 4, \ - SW_PARAM_PTR|SW_PARAM_OUT, "IPG and Preamble"), - -#define SW_API_POLICER_TIMESLOT_SET_DESC \ - SW_PARAM_DEF(SW_API_POLICER_TIMESLOT_SET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \ - SW_PARAM_DEF(SW_API_POLICER_TIMESLOT_SET, SW_UINT32, 4, SW_PARAM_IN, "Time Slot"), - -#define SW_API_POLICER_TIMESLOT_GET_DESC \ - SW_PARAM_DEF(SW_API_POLICER_TIMESLOT_GET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \ - SW_PARAM_DEF(SW_API_POLICER_TIMESLOT_GET, SW_UINT32, 4, SW_PARAM_PTR|SW_PARAM_OUT, "Time Slot"), - -#define SW_API_POLICER_PORT_COUNTER_GET_DESC \ - SW_PARAM_DEF(SW_API_POLICER_PORT_COUNTER_GET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \ - SW_PARAM_DEF(SW_API_POLICER_PORT_COUNTER_GET, SW_UINT32, 4, SW_PARAM_IN, "Port ID"), \ - SW_PARAM_DEF(SW_API_POLICER_PORT_COUNTER_GET, SW_POLICER_COUNTER, \ - sizeof(fal_policer_counter_t), SW_PARAM_PTR|SW_PARAM_OUT, "Port Statistics"), - -#define SW_API_POLICER_ACL_COUNTER_GET_DESC \ - SW_PARAM_DEF(SW_API_POLICER_ACL_COUNTER_GET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \ - SW_PARAM_DEF(SW_API_POLICER_ACL_COUNTER_GET, SW_UINT32, 4, SW_PARAM_IN, "Index"), \ - SW_PARAM_DEF(SW_API_POLICER_ACL_COUNTER_GET, SW_POLICER_COUNTER, \ - sizeof(fal_policer_counter_t), SW_PARAM_PTR|SW_PARAM_OUT, "ACL Statistics"), - -#define SW_API_POLICER_COMPENSATION_SET_DESC \ - SW_PARAM_DEF(SW_API_POLICER_COMPENSATION_SET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \ - SW_PARAM_DEF(SW_API_POLICER_COMPENSATION_SET, SW_UINT32, 4, SW_PARAM_IN, "Port ID"), \ - SW_PARAM_DEF(SW_API_POLICER_COMPENSATION_SET, SW_UINT32, 4, SW_PARAM_IN, "Number"), - -#define SW_API_POLICER_COMPENSATION_GET_DESC \ - SW_PARAM_DEF(SW_API_POLICER_COMPENSATION_GET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \ - SW_PARAM_DEF(SW_API_POLICER_COMPENSATION_GET, SW_UINT32, 4, SW_PARAM_IN, "Port ID"), \ - SW_PARAM_DEF(SW_API_POLICER_COMPENSATION_GET, SW_UINT32, 4, \ - SW_PARAM_PTR|SW_PARAM_OUT, "Number"), - -#define SW_API_POLICER_PORT_ENTRY_SET_DESC \ - SW_PARAM_DEF(SW_API_POLICER_PORT_ENTRY_SET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \ - SW_PARAM_DEF(SW_API_POLICER_PORT_ENTRY_SET, SW_UINT32, 4, SW_PARAM_IN, "Port ID"), \ - SW_PARAM_DEF(SW_API_POLICER_PORT_ENTRY_SET, SW_POLICER_PORT_CONFIG, \ - sizeof(fal_policer_config_t), SW_PARAM_PTR|SW_PARAM_IN, "Port Config"), \ - SW_PARAM_DEF(SW_API_POLICER_PORT_ENTRY_SET, SW_POLICER_CMD_CONFIG, \ - sizeof(fal_policer_action_t), SW_PARAM_PTR|SW_PARAM_IN, "CMD"), - -#define SW_API_POLICER_PORT_ENTRY_GET_DESC \ - SW_PARAM_DEF(SW_API_POLICER_PORT_ENTRY_GET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \ - SW_PARAM_DEF(SW_API_POLICER_PORT_ENTRY_GET, SW_UINT32, 4, SW_PARAM_IN, "Port ID"), \ - SW_PARAM_DEF(SW_API_POLICER_PORT_ENTRY_GET, SW_POLICER_PORT_CONFIG, \ - sizeof(fal_policer_config_t), SW_PARAM_PTR|SW_PARAM_OUT, "Port Config"), \ - SW_PARAM_DEF(SW_API_POLICER_PORT_ENTRY_GET, SW_POLICER_CMD_CONFIG, \ - sizeof(fal_policer_action_t), SW_PARAM_PTR|SW_PARAM_OUT, "CMD"), - -#define SW_API_POLICER_ACL_ENTRY_SET_DESC \ - SW_PARAM_DEF(SW_API_POLICER_ACL_ENTRY_SET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \ - SW_PARAM_DEF(SW_API_POLICER_ACL_ENTRY_SET, SW_UINT32, 4, SW_PARAM_IN, "Index"), \ - SW_PARAM_DEF(SW_API_POLICER_ACL_ENTRY_SET, SW_POLICER_ACL_CONFIG, \ - sizeof(fal_policer_config_t), SW_PARAM_PTR|SW_PARAM_IN, "ACL Config"), \ - SW_PARAM_DEF(SW_API_POLICER_ACL_ENTRY_SET, SW_POLICER_CMD_CONFIG, \ - sizeof(fal_policer_action_t), SW_PARAM_PTR|SW_PARAM_IN, "CMD"), - -#define SW_API_POLICER_ACL_ENTRY_GET_DESC \ - SW_PARAM_DEF(SW_API_POLICER_ACL_ENTRY_GET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \ - SW_PARAM_DEF(SW_API_POLICER_ACL_ENTRY_GET, SW_UINT32, 4, SW_PARAM_IN, "Index"), \ - SW_PARAM_DEF(SW_API_POLICER_ACL_ENTRY_GET, SW_POLICER_ACL_CONFIG, \ - sizeof(fal_policer_config_t), SW_PARAM_PTR|SW_PARAM_OUT, "ACL Config"), \ - SW_PARAM_DEF(SW_API_POLICER_ACL_ENTRY_GET, SW_POLICER_CMD_CONFIG, \ - sizeof(fal_policer_action_t), SW_PARAM_PTR|SW_PARAM_OUT, "CMD"), - -#define SW_API_POLICER_GLOBAL_COUNTER_GET_DESC \ - SW_PARAM_DEF(SW_API_POLICER_GLOBAL_COUNTER_GET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \ - SW_PARAM_DEF(SW_API_POLICER_GLOBAL_COUNTER_GET, SW_POLICER_GLOBAL_COUNTER, \ - sizeof(fal_policer_global_counter_t), SW_PARAM_PTR|SW_PARAM_OUT, \ - "Global Statistics"), - -#define SW_API_POLICER_BYPASS_EN_SET_DESC \ - SW_PARAM_DEF(SW_API_POLICER_BYPASS_EN_SET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \ - SW_PARAM_DEF(SW_API_POLICER_BYPASS_EN_SET, SW_UINT32, 4, SW_PARAM_IN, "frame_type"), \ - SW_PARAM_DEF(SW_API_POLICER_BYPASS_EN_SET, SW_ENABLE, 4, SW_PARAM_IN, "Status"), - -#define SW_API_POLICER_BYPASS_EN_GET_DESC \ - SW_PARAM_DEF(SW_API_POLICER_BYPASS_EN_GET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \ - SW_PARAM_DEF(SW_API_POLICER_BYPASS_EN_GET, SW_UINT32, 4, SW_PARAM_IN, "frame_type"), \ - SW_PARAM_DEF(SW_API_POLICER_BYPASS_EN_GET, SW_ENABLE, 4, SW_PARAM_PTR|SW_PARAM_OUT, "Status"), - -#define SW_API_PTP_CONFIG_SET_DESC \ - SW_PARAM_DEF(SW_API_PTP_CONFIG_SET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \ - SW_PARAM_DEF(SW_API_PTP_CONFIG_SET, SW_UINT32, 4, SW_PARAM_IN, "Port ID"), \ - SW_PARAM_DEF(SW_API_PTP_CONFIG_SET, SW_PTP_CONFIG, \ - sizeof(fal_ptp_config_t), SW_PARAM_PTR|SW_PARAM_IN, "CONFIG"), - -#define SW_API_PTP_CONFIG_GET_DESC \ - SW_PARAM_DEF(SW_API_PTP_CONFIG_GET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \ - SW_PARAM_DEF(SW_API_PTP_CONFIG_GET, SW_UINT32, 4, SW_PARAM_IN, "Port ID"), \ - SW_PARAM_DEF(SW_API_PTP_CONFIG_GET, SW_PTP_CONFIG, \ - sizeof(fal_ptp_config_t), SW_PARAM_PTR|SW_PARAM_OUT, "CONFIG"), - -#define SW_API_PTP_REFERENCE_CLOCK_SET_DESC \ - SW_PARAM_DEF(SW_API_PTP_REFERENCE_CLOCK_SET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \ - SW_PARAM_DEF(SW_API_PTP_REFERENCE_CLOCK_SET, SW_UINT32, 4, SW_PARAM_IN, "Port ID"), \ - SW_PARAM_DEF(SW_API_PTP_REFERENCE_CLOCK_SET, SW_PTP_REFERENCE_CLOCK, \ - sizeof(fal_ptp_reference_clock_t), SW_PARAM_IN, "Ref Clock"), - -#define SW_API_PTP_REFERENCE_CLOCK_GET_DESC \ - SW_PARAM_DEF(SW_API_PTP_REFERENCE_CLOCK_GET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \ - SW_PARAM_DEF(SW_API_PTP_REFERENCE_CLOCK_GET, SW_UINT32, 4, SW_PARAM_IN, "Port ID"), \ - SW_PARAM_DEF(SW_API_PTP_REFERENCE_CLOCK_GET, SW_PTP_REFERENCE_CLOCK, \ - sizeof(fal_ptp_reference_clock_t), SW_PARAM_PTR|SW_PARAM_OUT, "Ref Clock"), - -#define SW_API_PTP_RX_TIMESTAMP_MODE_SET_DESC \ - SW_PARAM_DEF(SW_API_PTP_RX_TIMESTAMP_MODE_SET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \ - SW_PARAM_DEF(SW_API_PTP_RX_TIMESTAMP_MODE_SET, SW_UINT32, 4, SW_PARAM_IN, "Port ID"), \ - SW_PARAM_DEF(SW_API_PTP_RX_TIMESTAMP_MODE_SET, SW_PTP_RX_TIMESTAMP_MODE, \ - sizeof(fal_ptp_rx_timestamp_mode_t), SW_PARAM_IN, "Timestamp Mode"), - -#define SW_API_PTP_RX_TIMESTAMP_MODE_GET_DESC \ - SW_PARAM_DEF(SW_API_PTP_RX_TIMESTAMP_MODE_GET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \ - SW_PARAM_DEF(SW_API_PTP_RX_TIMESTAMP_MODE_GET, SW_UINT32, 4, SW_PARAM_IN, "Port ID"), \ - SW_PARAM_DEF(SW_API_PTP_RX_TIMESTAMP_MODE_GET, SW_PTP_RX_TIMESTAMP_MODE, \ - sizeof(fal_ptp_rx_timestamp_mode_t), SW_PARAM_PTR|SW_PARAM_OUT, \ - "Timestamp Mode"), - -#define SW_API_PTP_TIMESTAMP_GET_DESC \ - SW_PARAM_DEF(SW_API_PTP_TIMESTAMP_GET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \ - SW_PARAM_DEF(SW_API_PTP_TIMESTAMP_GET, SW_UINT32, 4, SW_PARAM_IN, "Port ID"), \ - SW_PARAM_DEF(SW_API_PTP_TIMESTAMP_GET, SW_PTP_DIRECTION, \ - sizeof(fal_ptp_direction_t), SW_PARAM_IN, "Direction"), \ - SW_PARAM_DEF(SW_API_PTP_TIMESTAMP_GET, SW_PTP_PKT_INFO, \ - sizeof(fal_ptp_pkt_info_t), SW_PARAM_PTR|SW_PARAM_IN, "Pkt Info"), \ - SW_PARAM_DEF(SW_API_PTP_TIMESTAMP_GET, SW_PTP_TIME, \ - sizeof(fal_ptp_time_t), SW_PARAM_PTR|SW_PARAM_OUT, "Time"), - -#define SW_API_PTP_PKT_TIMESTAMP_SET_DESC \ - SW_PARAM_DEF(SW_API_PTP_PKT_TIMESTAMP_SET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \ - SW_PARAM_DEF(SW_API_PTP_PKT_TIMESTAMP_SET, SW_UINT32, 4, SW_PARAM_IN, "Port ID"), \ - SW_PARAM_DEF(SW_API_PTP_PKT_TIMESTAMP_SET, SW_PTP_TIME, \ - sizeof(fal_ptp_time_t), SW_PARAM_PTR|SW_PARAM_IN, "Time"), - -#define SW_API_PTP_PKT_TIMESTAMP_GET_DESC \ - SW_PARAM_DEF(SW_API_PTP_PKT_TIMESTAMP_GET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \ - SW_PARAM_DEF(SW_API_PTP_PKT_TIMESTAMP_GET, SW_UINT32, 4, SW_PARAM_IN, "Port ID"), \ - SW_PARAM_DEF(SW_API_PTP_PKT_TIMESTAMP_GET, SW_PTP_TIME, \ - sizeof(fal_ptp_time_t), SW_PARAM_PTR|SW_PARAM_OUT, "Time"), - -#define SW_API_PTP_GRANDMASTER_MODE_SET_DESC \ - SW_PARAM_DEF(SW_API_PTP_GRANDMASTER_MODE_SET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \ - SW_PARAM_DEF(SW_API_PTP_GRANDMASTER_MODE_SET, SW_UINT32, 4, SW_PARAM_IN, "Port ID"), \ - SW_PARAM_DEF(SW_API_PTP_GRANDMASTER_MODE_SET, SW_PTP_GRANDMASTER_MODE, \ - sizeof(fal_ptp_grandmaster_mode_t), SW_PARAM_PTR|SW_PARAM_IN, \ - "Grandmaster Mode"), - -#define SW_API_PTP_GRANDMASTER_MODE_GET_DESC \ - SW_PARAM_DEF(SW_API_PTP_GRANDMASTER_MODE_GET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \ - SW_PARAM_DEF(SW_API_PTP_GRANDMASTER_MODE_GET, SW_UINT32, 4, SW_PARAM_IN, "Port ID"), \ - SW_PARAM_DEF(SW_API_PTP_GRANDMASTER_MODE_GET, SW_PTP_GRANDMASTER_MODE, \ - sizeof(fal_ptp_grandmaster_mode_t), SW_PARAM_PTR|SW_PARAM_OUT, \ - "Grandmaster Mode"), - -#define SW_API_PTP_RTC_TIME_SET_DESC \ - SW_PARAM_DEF(SW_API_PTP_RTC_TIME_SET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \ - SW_PARAM_DEF(SW_API_PTP_RTC_TIME_SET, SW_UINT32, 4, SW_PARAM_IN, "Port ID"), \ - SW_PARAM_DEF(SW_API_PTP_RTC_TIME_SET, SW_PTP_TIME, \ - sizeof(fal_ptp_time_t), SW_PARAM_PTR|SW_PARAM_IN, "Time"), - -#define SW_API_PTP_RTC_TIME_GET_DESC \ - SW_PARAM_DEF(SW_API_PTP_RTC_TIME_GET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \ - SW_PARAM_DEF(SW_API_PTP_RTC_TIME_GET, SW_UINT32, 4, SW_PARAM_IN, "Port ID"), \ - SW_PARAM_DEF(SW_API_PTP_RTC_TIME_GET, SW_PTP_TIME, \ - sizeof(fal_ptp_time_t), SW_PARAM_PTR|SW_PARAM_OUT, "Time"), - -#define SW_API_PTP_RTC_TIME_CLEAR_DESC \ - SW_PARAM_DEF(SW_API_PTP_RTC_TIME_CLEAR, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \ - SW_PARAM_DEF(SW_API_PTP_RTC_TIME_CLEAR, SW_UINT32, 4, SW_PARAM_IN, "Port ID"), - -#define SW_API_PTP_RTC_ADJTIME_SET_DESC \ - SW_PARAM_DEF(SW_API_PTP_RTC_ADJTIME_SET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \ - SW_PARAM_DEF(SW_API_PTP_RTC_ADJTIME_SET, SW_UINT32, 4, SW_PARAM_IN, "Port ID"), \ - SW_PARAM_DEF(SW_API_PTP_RTC_ADJTIME_SET, SW_PTP_TIME, \ - sizeof(fal_ptp_time_t), SW_PARAM_PTR|SW_PARAM_IN, "Time"), - -#define SW_API_PTP_RTC_ADJFREQ_SET_DESC \ - SW_PARAM_DEF(SW_API_PTP_RTC_ADJFREQ_SET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \ - SW_PARAM_DEF(SW_API_PTP_RTC_ADJFREQ_SET, SW_UINT32, 4, SW_PARAM_IN, "Port ID"), \ - SW_PARAM_DEF(SW_API_PTP_RTC_ADJFREQ_SET, SW_PTP_TIME, \ - sizeof(fal_ptp_time_t), SW_PARAM_PTR|SW_PARAM_IN, "Time"), - -#define SW_API_PTP_RTC_ADJFREQ_GET_DESC \ - SW_PARAM_DEF(SW_API_PTP_RTC_ADJFREQ_GET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \ - SW_PARAM_DEF(SW_API_PTP_RTC_ADJFREQ_GET, SW_UINT32, 4, SW_PARAM_IN, "Port ID"), \ - SW_PARAM_DEF(SW_API_PTP_RTC_ADJFREQ_GET, SW_PTP_TIME, \ - sizeof(fal_ptp_time_t), SW_PARAM_PTR|SW_PARAM_OUT, "Time"), - -#define SW_API_PTP_LINK_DELAY_SET_DESC \ - SW_PARAM_DEF(SW_API_PTP_LINK_DELAY_SET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \ - SW_PARAM_DEF(SW_API_PTP_LINK_DELAY_SET, SW_UINT32, 4, SW_PARAM_IN, "Port ID"), \ - SW_PARAM_DEF(SW_API_PTP_LINK_DELAY_SET, SW_PTP_TIME, \ - sizeof(fal_ptp_time_t), SW_PARAM_PTR|SW_PARAM_IN, "Time"), - -#define SW_API_PTP_LINK_DELAY_GET_DESC \ - SW_PARAM_DEF(SW_API_PTP_LINK_DELAY_GET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \ - SW_PARAM_DEF(SW_API_PTP_LINK_DELAY_GET, SW_UINT32, 4, SW_PARAM_IN, "Port ID"), \ - SW_PARAM_DEF(SW_API_PTP_LINK_DELAY_GET, SW_PTP_TIME, \ - sizeof(fal_ptp_time_t), SW_PARAM_PTR|SW_PARAM_OUT, "Time"), - -#define SW_API_PTP_SECURITY_SET_DESC \ - SW_PARAM_DEF(SW_API_PTP_SECURITY_SET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \ - SW_PARAM_DEF(SW_API_PTP_SECURITY_SET, SW_UINT32, 4, SW_PARAM_IN, "Port ID"), \ - SW_PARAM_DEF(SW_API_PTP_SECURITY_SET, SW_PTP_SECURITY, \ - sizeof(fal_ptp_security_t), SW_PARAM_PTR|SW_PARAM_IN, "Security"), - -#define SW_API_PTP_SECURITY_GET_DESC \ - SW_PARAM_DEF(SW_API_PTP_SECURITY_GET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \ - SW_PARAM_DEF(SW_API_PTP_SECURITY_GET, SW_UINT32, 4, SW_PARAM_IN, "Port ID"), \ - SW_PARAM_DEF(SW_API_PTP_SECURITY_GET, SW_PTP_SECURITY, \ - sizeof(fal_ptp_security_t), SW_PARAM_PTR|SW_PARAM_OUT, "Security"), - -#define SW_API_PTP_PPS_SIGNAL_CONTROL_SET_DESC \ - SW_PARAM_DEF(SW_API_PTP_PPS_SIGNAL_CONTROL_SET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \ - SW_PARAM_DEF(SW_API_PTP_PPS_SIGNAL_CONTROL_SET, SW_UINT32, 4, SW_PARAM_IN, "Port ID"), \ - SW_PARAM_DEF(SW_API_PTP_PPS_SIGNAL_CONTROL_SET, SW_PTP_PPS_SIGNAL_CONTROL, \ - sizeof(fal_ptp_pps_signal_control_t), SW_PARAM_PTR|SW_PARAM_IN, "Sig Ctrl"), - -#define SW_API_PTP_PPS_SIGNAL_CONTROL_GET_DESC \ - SW_PARAM_DEF(SW_API_PTP_PPS_SIGNAL_CONTROL_GET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \ - SW_PARAM_DEF(SW_API_PTP_PPS_SIGNAL_CONTROL_GET, SW_UINT32, 4, SW_PARAM_IN, "Port ID"), \ - SW_PARAM_DEF(SW_API_PTP_PPS_SIGNAL_CONTROL_GET, SW_PTP_PPS_SIGNAL_CONTROL, \ - sizeof(fal_ptp_pps_signal_control_t), SW_PARAM_PTR|SW_PARAM_OUT, "Sig Ctrl"), - -#define SW_API_PTP_RX_CRC_RECALC_SET_DESC \ - SW_PARAM_DEF(SW_API_PTP_RX_CRC_RECALC_SET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \ - SW_PARAM_DEF(SW_API_PTP_RX_CRC_RECALC_SET, SW_UINT32, 4, SW_PARAM_IN, "Port ID"), \ - SW_PARAM_DEF(SW_API_PTP_RX_CRC_RECALC_SET, SW_ENABLE, sizeof(a_bool_t), SW_PARAM_IN, "Status"), - -#define SW_API_PTP_RX_CRC_RECALC_GET_DESC \ - SW_PARAM_DEF(SW_API_PTP_RX_CRC_RECALC_GET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \ - SW_PARAM_DEF(SW_API_PTP_RX_CRC_RECALC_GET, SW_UINT32, 4, SW_PARAM_IN, "Port ID"), \ - SW_PARAM_DEF(SW_API_PTP_RX_CRC_RECALC_GET, SW_ENABLE, \ - sizeof(a_bool_t), SW_PARAM_PTR|SW_PARAM_OUT, "Status"), - -#define SW_API_PTP_ASYM_CORRECTION_SET_DESC \ - SW_PARAM_DEF(SW_API_PTP_ASYM_CORRECTION_SET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \ - SW_PARAM_DEF(SW_API_PTP_ASYM_CORRECTION_SET, SW_UINT32, 4, SW_PARAM_IN, "Port ID"), \ - SW_PARAM_DEF(SW_API_PTP_ASYM_CORRECTION_SET, SW_PTP_ASYM_CORRECTION, \ - sizeof(fal_ptp_asym_correction_t), \ - SW_PARAM_PTR|SW_PARAM_IN, "Asym CF"), - -#define SW_API_PTP_ASYM_CORRECTION_GET_DESC \ - SW_PARAM_DEF(SW_API_PTP_ASYM_CORRECTION_GET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \ - SW_PARAM_DEF(SW_API_PTP_ASYM_CORRECTION_GET, SW_UINT32, 4, SW_PARAM_IN, "Port ID"), \ - SW_PARAM_DEF(SW_API_PTP_ASYM_CORRECTION_GET, SW_PTP_ASYM_CORRECTION, \ - sizeof(fal_ptp_asym_correction_t), \ - SW_PARAM_PTR|SW_PARAM_OUT, "Asym CF"), - -#define SW_API_PTP_OUTPUT_WAVEFORM_SET_DESC \ - SW_PARAM_DEF(SW_API_PTP_OUTPUT_WAVEFORM_SET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \ - SW_PARAM_DEF(SW_API_PTP_OUTPUT_WAVEFORM_SET, SW_UINT32, 4, SW_PARAM_IN, "Port ID"), \ - SW_PARAM_DEF(SW_API_PTP_OUTPUT_WAVEFORM_SET, SW_PTP_OUTPUT_WAVEFORM, \ - sizeof(fal_ptp_output_waveform_t), \ - SW_PARAM_PTR|SW_PARAM_IN, "Waveform"), - -#define SW_API_PTP_OUTPUT_WAVEFORM_GET_DESC \ - SW_PARAM_DEF(SW_API_PTP_OUTPUT_WAVEFORM_GET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \ - SW_PARAM_DEF(SW_API_PTP_OUTPUT_WAVEFORM_GET, SW_UINT32, 4, SW_PARAM_IN, "Port ID"), \ - SW_PARAM_DEF(SW_API_PTP_OUTPUT_WAVEFORM_GET, SW_PTP_OUTPUT_WAVEFORM, \ - sizeof(fal_ptp_output_waveform_t), \ - SW_PARAM_PTR|SW_PARAM_OUT, "Waveform"), - -#define SW_API_PTP_RTC_TIME_SNAPSHOT_SET_DESC \ - SW_PARAM_DEF(SW_API_PTP_RTC_TIME_SNAPSHOT_SET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \ - SW_PARAM_DEF(SW_API_PTP_RTC_TIME_SNAPSHOT_SET, SW_UINT32, 4, SW_PARAM_IN, "Port ID"), \ - SW_PARAM_DEF(SW_API_PTP_RTC_TIME_SNAPSHOT_SET, SW_ENABLE, \ - sizeof(a_bool_t), SW_PARAM_IN, "Status"), - -#define SW_API_PTP_RTC_TIME_SNAPSHOT_GET_DESC \ - SW_PARAM_DEF(SW_API_PTP_RTC_TIME_SNAPSHOT_GET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \ - SW_PARAM_DEF(SW_API_PTP_RTC_TIME_SNAPSHOT_GET, SW_UINT32, 4, SW_PARAM_IN, "Port ID"), \ - SW_PARAM_DEF(SW_API_PTP_RTC_TIME_SNAPSHOT_GET, SW_ENABLE, sizeof(a_bool_t), \ - SW_PARAM_PTR|SW_PARAM_OUT, "Status"), - -#define SW_API_PTP_INCREMENT_SYNC_FROM_CLOCK_SET_DESC \ - SW_PARAM_DEF(SW_API_PTP_INCREMENT_SYNC_FROM_CLOCK_SET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \ - SW_PARAM_DEF(SW_API_PTP_INCREMENT_SYNC_FROM_CLOCK_SET, SW_UINT32, 4, SW_PARAM_IN, "Port ID"), \ - SW_PARAM_DEF(SW_API_PTP_INCREMENT_SYNC_FROM_CLOCK_SET, SW_ENABLE, sizeof(a_bool_t), \ - SW_PARAM_IN, "Status"), - -#define SW_API_PTP_INCREMENT_SYNC_FROM_CLOCK_GET_DESC \ - SW_PARAM_DEF(SW_API_PTP_INCREMENT_SYNC_FROM_CLOCK_GET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \ - SW_PARAM_DEF(SW_API_PTP_INCREMENT_SYNC_FROM_CLOCK_GET, SW_UINT32, 4, SW_PARAM_IN, "Port ID"), \ - SW_PARAM_DEF(SW_API_PTP_INCREMENT_SYNC_FROM_CLOCK_GET, SW_ENABLE, sizeof(a_bool_t), \ - SW_PARAM_PTR|SW_PARAM_OUT, "Status"), - -#define SW_API_PTP_TOD_UART_SET_DESC \ - SW_PARAM_DEF(SW_API_PTP_TOD_UART_SET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \ - SW_PARAM_DEF(SW_API_PTP_TOD_UART_SET, SW_UINT32, 4, SW_PARAM_IN, "Port ID"), \ - SW_PARAM_DEF(SW_API_PTP_TOD_UART_SET, SW_PTP_TOD_UART, sizeof(fal_ptp_tod_uart_t), \ - SW_PARAM_PTR|SW_PARAM_IN, "TOD UART"), - -#define SW_API_PTP_TOD_UART_GET_DESC \ - SW_PARAM_DEF(SW_API_PTP_TOD_UART_GET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \ - SW_PARAM_DEF(SW_API_PTP_TOD_UART_GET, SW_UINT32, 4, SW_PARAM_IN, "Port ID"), \ - SW_PARAM_DEF(SW_API_PTP_TOD_UART_GET, SW_PTP_TOD_UART, sizeof(fal_ptp_tod_uart_t), \ - SW_PARAM_PTR|SW_PARAM_OUT, "TOD UART"), - -#define SW_API_PTP_ENHANCED_TIMESTAMP_ENGINE_SET_DESC \ - SW_PARAM_DEF(SW_API_PTP_ENHANCED_TIMESTAMP_ENGINE_SET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \ - SW_PARAM_DEF(SW_API_PTP_ENHANCED_TIMESTAMP_ENGINE_SET, SW_UINT32, 4, SW_PARAM_IN, "Port ID"), \ - SW_PARAM_DEF(SW_API_PTP_ENHANCED_TIMESTAMP_ENGINE_SET, SW_PTP_DIRECTION, \ - sizeof(fal_ptp_direction_t), SW_PARAM_IN, "Direction"), \ - SW_PARAM_DEF(SW_API_PTP_ENHANCED_TIMESTAMP_ENGINE_SET, SW_PTP_ENHANCED_TS_ENGINE, \ - sizeof(fal_ptp_enhanced_ts_engine_t), SW_PARAM_PTR|SW_PARAM_IN, "TS Engine"), - -#define SW_API_PTP_ENHANCED_TIMESTAMP_ENGINE_GET_DESC \ - SW_PARAM_DEF(SW_API_PTP_ENHANCED_TIMESTAMP_ENGINE_GET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \ - SW_PARAM_DEF(SW_API_PTP_ENHANCED_TIMESTAMP_ENGINE_GET, SW_UINT32, 4, SW_PARAM_IN, "Port ID"), \ - SW_PARAM_DEF(SW_API_PTP_ENHANCED_TIMESTAMP_ENGINE_GET, SW_PTP_DIRECTION, \ - sizeof(fal_ptp_direction_t), SW_PARAM_IN, "Direction"), \ - SW_PARAM_DEF(SW_API_PTP_ENHANCED_TIMESTAMP_ENGINE_GET, SW_PTP_ENHANCED_TS_ENGINE, \ - sizeof(fal_ptp_enhanced_ts_engine_t), SW_PARAM_PTR|SW_PARAM_OUT, "TS Engine"), - -#define SW_API_PTP_TRIGGER_SET_DESC \ - SW_PARAM_DEF(SW_API_PTP_TRIGGER_SET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \ - SW_PARAM_DEF(SW_API_PTP_TRIGGER_SET, SW_UINT32, 4, SW_PARAM_IN, "Port ID"), \ - SW_PARAM_DEF(SW_API_PTP_TRIGGER_SET, SW_UINT32, 4, SW_PARAM_IN, "Trigger ID"), \ - SW_PARAM_DEF(SW_API_PTP_TRIGGER_SET, SW_PTP_TRIGGER, sizeof(fal_ptp_trigger_t), \ - SW_PARAM_PTR|SW_PARAM_IN, "Trigger"), - -#define SW_API_PTP_TRIGGER_GET_DESC \ - SW_PARAM_DEF(SW_API_PTP_TRIGGER_GET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \ - SW_PARAM_DEF(SW_API_PTP_TRIGGER_GET, SW_UINT32, 4, SW_PARAM_IN, "Port ID"), \ - SW_PARAM_DEF(SW_API_PTP_TRIGGER_GET, SW_UINT32, 4, SW_PARAM_IN, "Trigger ID"), \ - SW_PARAM_DEF(SW_API_PTP_TRIGGER_GET, SW_PTP_TRIGGER, sizeof(fal_ptp_trigger_t), \ - SW_PARAM_PTR|SW_PARAM_OUT, "Trigger"), - -#define SW_API_PTP_CAPTURE_SET_DESC \ - SW_PARAM_DEF(SW_API_PTP_CAPTURE_SET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \ - SW_PARAM_DEF(SW_API_PTP_CAPTURE_SET, SW_UINT32, 4, SW_PARAM_IN, "Port ID"), \ - SW_PARAM_DEF(SW_API_PTP_CAPTURE_SET, SW_UINT32, 4, SW_PARAM_IN, "Capture ID"), \ - SW_PARAM_DEF(SW_API_PTP_CAPTURE_SET, SW_PTP_CAPTURE, sizeof(fal_ptp_capture_t), \ - SW_PARAM_PTR|SW_PARAM_IN, "Capture"), - -#define SW_API_PTP_CAPTURE_GET_DESC \ - SW_PARAM_DEF(SW_API_PTP_CAPTURE_GET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \ - SW_PARAM_DEF(SW_API_PTP_CAPTURE_GET, SW_UINT32, 4, SW_PARAM_IN, "Port ID"), \ - SW_PARAM_DEF(SW_API_PTP_CAPTURE_GET, SW_UINT32, 4, SW_PARAM_IN, "Capture ID"), \ - SW_PARAM_DEF(SW_API_PTP_CAPTURE_GET, SW_PTP_CAPTURE, sizeof(fal_ptp_capture_t), \ - SW_PARAM_PTR|SW_PARAM_OUT, "Capture"), - -#define SW_API_PTP_INTERRUPT_SET_DESC \ - SW_PARAM_DEF(SW_API_PTP_INTERRUPT_SET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \ - SW_PARAM_DEF(SW_API_PTP_INTERRUPT_SET, SW_UINT32, 4, SW_PARAM_IN, "Port ID"), \ - SW_PARAM_DEF(SW_API_PTP_INTERRUPT_SET, SW_PTP_INTERRUPT, sizeof(SW_PTP_INTERRUPT), \ - SW_PARAM_PTR|SW_PARAM_IN, "Interrupt"), - -#define SW_API_PTP_INTERRUPT_GET_DESC \ - SW_PARAM_DEF(SW_API_PTP_INTERRUPT_GET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \ - SW_PARAM_DEF(SW_API_PTP_INTERRUPT_GET, SW_UINT32, 4, SW_PARAM_IN, "Port ID"), \ - SW_PARAM_DEF(SW_API_PTP_INTERRUPT_GET, SW_PTP_INTERRUPT, sizeof(SW_PTP_INTERRUPT), \ - SW_PARAM_PTR|SW_PARAM_OUT, "Interrupt"), - -#define SW_API_SFP_DATA_GET_DESC \ - SW_PARAM_DEF(SW_API_SFP_DATA_GET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"),\ - SW_PARAM_DEF(SW_API_SFP_DATA_GET, SW_UINT32, 4, SW_PARAM_IN, "Port ID"), \ - SW_PARAM_DEF(SW_API_SFP_DATA_GET, SW_SFP_DATA, \ - sizeof(fal_sfp_data_t), SW_PARAM_PTR|SW_PARAM_IN|SW_PARAM_OUT, "Data"), - -#define SW_API_SFP_DATA_SET_DESC \ - SW_PARAM_DEF(SW_API_SFP_DATA_SET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"),\ - SW_PARAM_DEF(SW_API_SFP_DATA_SET, SW_UINT32, 4, SW_PARAM_IN, "Port ID"), \ - SW_PARAM_DEF(SW_API_SFP_DATA_SET, SW_SFP_DATA, \ - sizeof(fal_sfp_data_t), SW_PARAM_PTR|SW_PARAM_IN|SW_PARAM_OUT, "Data"), - -#define SW_API_SFP_DEV_TYPE_GET_DESC \ - SW_PARAM_DEF(SW_API_SFP_DEV_TYPE_GET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \ - SW_PARAM_DEF(SW_API_SFP_DEV_TYPE_GET, SW_UINT32, 4, SW_PARAM_IN, "Port ID"), \ - SW_PARAM_DEF(SW_API_SFP_DEV_TYPE_GET, SW_SFP_DEV_TYPE, \ - sizeof(fal_sfp_dev_type_t), SW_PARAM_PTR|SW_PARAM_OUT, "Device Type"), - -#define SW_API_SFP_TRANSC_CODE_GET_DESC \ - SW_PARAM_DEF(SW_API_SFP_TRANSC_CODE_GET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \ - SW_PARAM_DEF(SW_API_SFP_TRANSC_CODE_GET, SW_UINT32, 4, SW_PARAM_IN, "Port ID"), \ - SW_PARAM_DEF(SW_API_SFP_TRANSC_CODE_GET, SW_SFP_TRANSC_CODE, \ - sizeof(fal_sfp_transc_code_t), SW_PARAM_PTR|SW_PARAM_OUT, "Transceiver Code"), - -#define SW_API_SFP_RATE_ENCODE_GET_DESC \ - SW_PARAM_DEF(SW_API_SFP_RATE_ENCODE_GET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \ - SW_PARAM_DEF(SW_API_SFP_RATE_ENCODE_GET, SW_UINT32, 4, SW_PARAM_IN, "Port ID"), \ - SW_PARAM_DEF(SW_API_SFP_RATE_ENCODE_GET, SW_SFP_RATE_ENCODE, \ - sizeof(fal_sfp_rate_encode_t), SW_PARAM_PTR|SW_PARAM_OUT, "Rate Encode"), - -#define SW_API_SFP_LINK_LENGTH_GET_DESC \ - SW_PARAM_DEF(SW_API_SFP_LINK_LENGTH_GET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \ - SW_PARAM_DEF(SW_API_SFP_LINK_LENGTH_GET, SW_UINT32, 4, SW_PARAM_IN, "Port ID"), \ - SW_PARAM_DEF(SW_API_SFP_LINK_LENGTH_GET, SW_SFP_LINK_LENGTH, \ - sizeof(fal_sfp_link_length_t), SW_PARAM_PTR|SW_PARAM_OUT, "Link Length"), - -#define SW_API_SFP_VENDOR_INFO_GET_DESC \ - SW_PARAM_DEF(SW_API_SFP_VENDOR_INFO_GET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \ - SW_PARAM_DEF(SW_API_SFP_VENDOR_INFO_GET, SW_UINT32, 4, SW_PARAM_IN, "Port ID"), \ - SW_PARAM_DEF(SW_API_SFP_VENDOR_INFO_GET, SW_SFP_VENDOR_INFO, \ - sizeof(fal_sfp_vendor_info_t), SW_PARAM_PTR|SW_PARAM_OUT, "Vendor Info"), - -#define SW_API_SFP_LASER_WAVELENGTH_GET_DESC \ - SW_PARAM_DEF(SW_API_SFP_LASER_WAVELENGTH_GET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \ - SW_PARAM_DEF(SW_API_SFP_LASER_WAVELENGTH_GET, SW_UINT32, 4, SW_PARAM_IN, "Port ID"), \ - SW_PARAM_DEF(SW_API_SFP_LASER_WAVELENGTH_GET, SW_SFP_LASER_WAVELENGTH, \ - sizeof(fal_sfp_laser_wavelength_t), SW_PARAM_PTR|SW_PARAM_OUT, "Wave Length"), - -#define SW_API_SFP_OPTION_GET_DESC \ - SW_PARAM_DEF(SW_API_SFP_OPTION_GET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \ - SW_PARAM_DEF(SW_API_SFP_OPTION_GET, SW_UINT32, 4, SW_PARAM_IN, "Port ID"), \ - SW_PARAM_DEF(SW_API_SFP_OPTION_GET, SW_SFP_OPTION, \ - sizeof(fal_sfp_option_t), SW_PARAM_PTR|SW_PARAM_OUT, "Option"), - -#define SW_API_SFP_CTRL_RATE_GET_DESC \ - SW_PARAM_DEF(SW_API_SFP_CTRL_RATE_GET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \ - SW_PARAM_DEF(SW_API_SFP_CTRL_RATE_GET, SW_UINT32, 4, SW_PARAM_IN, "Port ID"), \ - SW_PARAM_DEF(SW_API_SFP_CTRL_RATE_GET, SW_SFP_CTRL_RATE, \ - sizeof(fal_sfp_rate_t), SW_PARAM_PTR|SW_PARAM_OUT, "Control Rate"), - -#define SW_API_SFP_ENHANCED_CFG_GET_DESC \ - SW_PARAM_DEF(SW_API_SFP_ENHANCED_CFG_GET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \ - SW_PARAM_DEF(SW_API_SFP_ENHANCED_CFG_GET, SW_UINT32, 4, SW_PARAM_IN, "Port ID"), \ - SW_PARAM_DEF(SW_API_SFP_ENHANCED_CFG_GET, SW_SFP_ENHANCED_CFG, \ - sizeof(fal_sfp_enhanced_cfg_t), SW_PARAM_PTR|SW_PARAM_OUT, "Enhanced Config"), - -#define SW_API_SFP_DIAG_THRESHOLD_GET_DESC \ - SW_PARAM_DEF(SW_API_SFP_DIAG_THRESHOLD_GET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \ - SW_PARAM_DEF(SW_API_SFP_DIAG_THRESHOLD_GET, SW_UINT32, 4, SW_PARAM_IN, "Port ID"), \ - SW_PARAM_DEF(SW_API_SFP_DIAG_THRESHOLD_GET, SW_SFP_DIAG_THRESHOLD, \ - sizeof(fal_sfp_internal_threshold_t), SW_PARAM_PTR|SW_PARAM_OUT, "Threshold"), - -#define SW_API_SFP_DIAG_CAL_CONST_GET_DESC \ - SW_PARAM_DEF(SW_API_SFP_DIAG_CAL_CONST_GET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \ - SW_PARAM_DEF(SW_API_SFP_DIAG_CAL_CONST_GET, SW_UINT32, 4, SW_PARAM_IN, "Port ID"), \ - SW_PARAM_DEF(SW_API_SFP_DIAG_CAL_CONST_GET, SW_SFP_DIAG_CAL_CONST, \ - sizeof(fal_sfp_cal_const_t), SW_PARAM_PTR|SW_PARAM_OUT, "Calibration"), - -#define SW_API_SFP_DIAG_REALTIME_GET_DESC \ - SW_PARAM_DEF(SW_API_SFP_DIAG_REALTIME_GET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \ - SW_PARAM_DEF(SW_API_SFP_DIAG_REALTIME_GET, SW_UINT32, 4, SW_PARAM_IN, "Port ID"), \ - SW_PARAM_DEF(SW_API_SFP_DIAG_REALTIME_GET, SW_SFP_DIAG_REALTIME, \ - sizeof(fal_sfp_realtime_diag_t), SW_PARAM_PTR|SW_PARAM_OUT, "Realtime Diag"), - -#define SW_API_SFP_DIAG_CTRL_STATUS_GET_DESC \ - SW_PARAM_DEF(SW_API_SFP_DIAG_CTRL_STATUS_GET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \ - SW_PARAM_DEF(SW_API_SFP_DIAG_CTRL_STATUS_GET, SW_UINT32, 4, SW_PARAM_IN, "Port ID"), \ - SW_PARAM_DEF(SW_API_SFP_DIAG_CTRL_STATUS_GET, SW_SFP_CTRL_STATUS, \ - sizeof(fal_sfp_ctrl_status_t), SW_PARAM_PTR|SW_PARAM_OUT, "Control Status"), - -#define SW_API_SFP_DIAG_ALARM_WARN_FLAG_GET_DESC \ - SW_PARAM_DEF(SW_API_SFP_DIAG_ALARM_WARN_FLAG_GET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \ - SW_PARAM_DEF(SW_API_SFP_DIAG_ALARM_WARN_FLAG_GET, SW_UINT32, 4, SW_PARAM_IN, "Port ID"), \ - SW_PARAM_DEF(SW_API_SFP_DIAG_ALARM_WARN_FLAG_GET, SW_SFP_ALARM_WARN_FLAG, \ - sizeof(fal_sfp_alarm_warn_flag_t), SW_PARAM_PTR|SW_PARAM_OUT, "A/W Flag"), - -#define SW_API_SFP_CHECKCODE_GET_DESC \ - SW_PARAM_DEF(SW_API_SFP_CHECKCODE_GET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \ - SW_PARAM_DEF(SW_API_SFP_CHECKCODE_GET, SW_UINT32, 4, SW_PARAM_IN, "Port ID"), \ - SW_PARAM_DEF(SW_API_SFP_CHECKCODE_GET, SW_SFP_CCODE_TYPE, \ - sizeof(fal_sfp_cc_type_t), SW_PARAM_IN, "Check Code Type"), \ - SW_PARAM_DEF(SW_API_SFP_CHECKCODE_GET, SW_UINT8, \ - sizeof(a_uint8_t), SW_PARAM_PTR|SW_PARAM_OUT, "Check Code"), - -/*qca808x_start*/ - -#define SW_API_DESC(api_id) api_id##_DESC - -#ifdef __cplusplus -} -#endif /* __cplusplus */ - -#endif /* _API_DESC_H_ */ -/*qca808x_end*/ - diff --git a/feeds/ipq807x/qca-ssdk/src/include/api/sw_api.h b/feeds/ipq807x/qca-ssdk/src/include/api/sw_api.h deleted file mode 100755 index 127fb59ef..000000000 --- a/feeds/ipq807x/qca-ssdk/src/include/api/sw_api.h +++ /dev/null @@ -1,276 +0,0 @@ -/* - * Copyright (c) 2012, 2015-2019, The Linux Foundation. All rights reserved. - * Permission to use, copy, modify, and/or distribute this software for - * any purpose with or without fee is hereby granted, provided that the - * above copyright notice and this permission notice appear in all copies. - * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES - * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR - * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES - * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN - * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT - * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. - */ - - - -#ifndef _SW_API_H -#define _SW_API_H - -#ifdef __cplusplus -extern "C" { -#endif /* __cplusplus */ - -#include "sw.h" -#include "sw_ioctl.h" - -#define SW_MAX_API_BUF 2048 -#define SW_MAX_API_PARAM 12 /* cmd type + return value + ten parameters */ -#define SW_MAX_PAYLOAD (SW_MAX_API_PARAM << 2) /* maximum payload size for netlink msg*/ -#define SW_PARAM_IN 0x1 -#define SW_PARAM_OUT 0x2 -#define SW_PARAM_PTR 0x4 - -#define SW_API_DEF(ioctl, name) {ioctl, name} - -#define SW_PARAM_DEF(ioctl, data, size, type, name) {ioctl, size, data, type} - -typedef enum -{ - SW_UINT8 = 1, - SW_INT8, - SW_UINT16, - SW_INT16, - SW_UINT32, - SW_INT32, - SW_UINT64, - SW_INT64, - SW_ENABLE, - SW_SPEED, - SW_DUPLEX, - SW_1QMODE, - SW_EGMODE, - SW_CAP, - SW_VLAN, - SW_LAN_WAN_CFG, - SW_PBMP, - SW_MIB, - SW_MIB_CNTR, - SW_XGMIB, - SW_MACADDR, - SW_FDBENTRY, - SW_MACLIMIT_CTRL, - SW_SCH, - SW_QOS, - SW_STORM, - SW_STP, - SW_LEAKY, - SW_MACCMD, - SW_FLOWTYPE, - SW_FLOWCMD, - SW_UINT_A, - SW_ACLRULE, - SW_LEDPATTERN, - SW_INVLAN, - SW_VLANPROPAGATION, - SW_VLANTRANSLATION, - SW_QINQMODE, - SW_QINQROLE, - SW_CABLESTATUS, - SW_CABLELEN, - SW_SSDK_CFG, - SW_HDRMODE, - SW_FDBOPRATION, - SW_PPPOE, - SW_PPPOE_LESS, - SW_ACL_UDF_TYPE, - SW_IP_HOSTENTRY, - SW_ARP_LEARNMODE, - SW_IP_GUARDMODE, - SW_NATENTRY, - SW_NAPTENTRY, - SW_FLOWENTRY, - SW_NAPTMODE, - SW_IP4ADDR, - SW_IP6ADDR, - SW_INTFMACENTRY, - SW_PUBADDRENTRY, - SW_INGPOLICER, - SW_EGSHAPER, - SW_ACLPOLICER, - SW_MACCONFIG, - SW_PHYCONFIG, - SW_DATA_MAX, - SW_FDBSMODE, - SW_FX100CONFIG, - SW_SGENTRY, - SW_SEC_MAC, - SW_SEC_IP, - SW_SEC_IP4, - SW_SEC_IP6, - SW_SEC_TCP, - SW_SEC_UDP, - SW_SEC_ICMP4, - SW_SEC_ICMP6, - SW_REMARKENTRY, - SW_SGINFOENTRY, - SW_DEFAULT_ROUTE_ENTRY, - SW_HOST_ROUTE_ENTRY, - SW_IP_WCMP_ENTRY, - SW_IP_RFS_IP4, - SW_IP_RFS_IP6, - SW_FLOWCOOKIE, - SW_FDB_RFS, - SW_FLOWRFS, - SW_CROSSOVER_MODE, - SW_CROSSOVER_STATUS, - SW_PREFER_MEDIUM, - SW_FIBER_MODE, - SW_INTERFACE_MODE, - SW_COUNTER_INFO, - SW_REG_DUMP, - SW_DBG_REG_DUMP, - SW_VSI_NEWADDR_LRN, - SW_VSI_STAMOVE, - SW_VSI_MEMBER, - SW_VSI_COUNTER, - SW_MTU_INFO, - SW_MRU_INFO, - SW_MTU_ENTRY, - SW_MRU_ENTRY, - SW_FRAME_MAX_SIZE, - SW_SOURCE_FILTER, - SW_ARP_SG_CFG, - SW_IP_NETWORK_ROUTE, - SW_IP_INTF, - SW_IP_VSI_INTF, - SW_IP_NEXTHOP, - SW_UCAST_QUEUE_MAP, - SW_UCAST_PRI_CLASS, - SW_MCAST_PRI_CLASS, - SW_IP_SG, - SW_IP_PUB, - SW_IP_PORTMAC, - SW_IP_MCMODE, - SW_FLOW_AGE, - SW_FLOW_CTRL, - SW_AC_CTRL, - SW_AC_OBJ, - SW_STATIC_THRESH, - SW_DYNAMIC_THRESH, - SW_GROUP_BUFFER, - SW_FLOW_ENTRY, - SW_FLOW_HOST, - SW_IP_GLOBAL, - SW_FLOW_GLOBAL, - SW_GLOBAL_QINQMODE, - SW_PT_QINQMODE, - SW_TPID, - SW_INGRESS_FILTER, - SW_PT_DEF_VID_EN, - SW_PT_VLAN_TAG, - SW_PT_VLAN_DIRECTION, - SW_PT_VLAN_TRANS_ADV_RULE, - SW_PT_VLAN_TRANS_ADV_ACTION, - SW_PT_VLAN_COUNTER, - SW_DEBUG_COUNTER_EN, - SW_TAG_PROPAGATION, - SW_EGRESS_DEFAULT_VID, - SW_EGRESS_MODE, - SW_CTRLPKT_PROFILE, - SW_SERVCODE_CONFIG, - SW_RSS_HASH_MODE, - SW_RSS_HASH_CONFIG, - SW_MIRR_ANALYSIS_CONFIG, - SW_MIRR_DIRECTION, - SW_L3_PARSER, - SW_L4_PARSER, - SW_EXP_CTRL, - SW_ACL_UDF_PKT_TYPE, - SW_PORTGROUP, - SW_PORTPRI, - SW_PORTREMARK, - SW_COSMAP, - SW_SCHEDULER, - SW_QUEUEBMP, - SW_BMSTHRESH, - SW_BMDTHRESH, - SW_BMPORTCNT, - SW_PORT_SHAPER_TOKEN_CONFIG, - SW_SHAPER_TOKEN_CONFIG, - SW_PORT_SHAPER_CONFIG, - SW_SHAPER_CONFIG, - SW_MODULE, - SW_FUNC_CTRL, - SW_QM_CNT, - SW_POLICER_COUNTER, - SW_POLICER_PORT_CONFIG, - SW_POLICER_ACL_CONFIG, - SW_POLICER_CMD_CONFIG, - SW_POLICER_GLOBAL_COUNTER, - SW_PHY_DUMP, - SW_RESOURCE_SCHE, - SW_PTP_CONFIG, - SW_PTP_REFERENCE_CLOCK, - SW_PTP_RX_TIMESTAMP_MODE, - SW_PTP_DIRECTION, - SW_PTP_PKT_INFO, - SW_PTP_TIME, - SW_PTP_GRANDMASTER_MODE, - SW_PTP_SECURITY, - SW_PTP_PPS_SIGNAL_CONTROL, - SW_PTP_ASYM_CORRECTION, - SW_PTP_OUTPUT_WAVEFORM, - SW_PTP_TOD_UART, - SW_PTP_ENHANCED_TS_ENGINE, - SW_PTP_TRIGGER, - SW_PTP_CAPTURE, - SW_PTP_INTERRUPT, - SW_PORT_EEE_CONFIG, - SW_SRC_FILTER_CONFIG, - SW_PORT_LOOPBACK_CONFIG, - SW_SFP_DATA, - SW_SFP_DEV_TYPE, - SW_SFP_TRANSC_CODE, - SW_SFP_RATE_ENCODE, - SW_SFP_LINK_LENGTH, - SW_SFP_VENDOR_INFO, - SW_SFP_LASER_WAVELENGTH, - SW_SFP_OPTION, - SW_SFP_CTRL_RATE, - SW_SFP_ENHANCED_CFG, - SW_SFP_DIAG_THRESHOLD, - SW_SFP_DIAG_CAL_CONST, - SW_SFP_DIAG_REALTIME, - SW_SFP_CTRL_STATUS, - SW_SFP_ALARM_WARN_FLAG, - SW_SFP_CCODE_TYPE, -} sw_data_type_e; - - typedef struct - { - a_uint32_t api_id; - void *func; - } sw_api_func_t; - - typedef struct - { - a_uint32_t api_id; - a_uint16_t data_size; - a_uint8_t data_type; - a_uint8_t param_type; - } sw_api_param_t; - - typedef struct - { - a_uint32_t api_id; - sw_api_func_t *api_fp; - sw_api_param_t *api_pp; - a_uint32_t api_nr; - } sw_api_t; - -#ifdef __cplusplus -} -#endif /* __cplusplus */ - -#endif /* _SW_API_H */ diff --git a/feeds/ipq807x/qca-ssdk/src/include/api/sw_ioctl.h b/feeds/ipq807x/qca-ssdk/src/include/api/sw_ioctl.h deleted file mode 100755 index 5c404e346..000000000 --- a/feeds/ipq807x/qca-ssdk/src/include/api/sw_ioctl.h +++ /dev/null @@ -1,989 +0,0 @@ -/* - * Copyright (c) 2012, 2015-2019, 2021, The Linux Foundation. All rights reserved. - * Permission to use, copy, modify, and/or distribute this software for - * any purpose with or without fee is hereby granted, provided that the - * above copyright notice and this permission notice appear in all copies. - * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES - * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR - * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES - * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN - * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT - * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. - */ - - -/*qca808x_start*/ -#ifndef _SW_IOCTL_H_ -#define _SW_IOCTL_H_ - -#ifdef __cplusplus -extern "C" { -#endif /* __cplusplus */ - - /*init*/ -#define SW_API_INIT_OFFSET 10 -#define SW_API_SWITCH_INIT (0 + SW_API_INIT_OFFSET) -#define SW_API_SWITCH_RESET (1 + SW_API_INIT_OFFSET) -#define SW_API_SSDK_CFG (2 + SW_API_INIT_OFFSET) -#define SW_API_MODULE_FUNC_CTRL_SET (3 + SW_API_INIT_OFFSET) -#define SW_API_MODULE_FUNC_CTRL_GET (4 + SW_API_INIT_OFFSET) - - /*port ctrl*/ -#define SW_API_PORT_OFFSET 30 -#define SW_API_PT_DUPLEX_GET (0 + SW_API_PORT_OFFSET) -#define SW_API_PT_DUPLEX_SET (1 + SW_API_PORT_OFFSET) -#define SW_API_PT_SPEED_GET (2 + SW_API_PORT_OFFSET) -#define SW_API_PT_SPEED_SET (3 + SW_API_PORT_OFFSET) -#define SW_API_PT_AN_ADV_GET (4 + SW_API_PORT_OFFSET) -#define SW_API_PT_AN_ADV_SET (5 + SW_API_PORT_OFFSET) -#define SW_API_PT_AN_GET (6 + SW_API_PORT_OFFSET) -#define SW_API_PT_AN_ENABLE (7 + SW_API_PORT_OFFSET) -#define SW_API_PT_AN_RESTART (8 + SW_API_PORT_OFFSET) -/*qca808x_end*/ -#define SW_API_PT_HDR_SET (9 + SW_API_PORT_OFFSET) -#define SW_API_PT_HDR_GET (10 + SW_API_PORT_OFFSET) -#define SW_API_PT_FLOWCTRL_SET (11 + SW_API_PORT_OFFSET) -#define SW_API_PT_FLOWCTRL_GET (12 + SW_API_PORT_OFFSET) -#define SW_API_PT_FLOWCTRL_MODE_SET (13 + SW_API_PORT_OFFSET) -#define SW_API_PT_FLOWCTRL_MODE_GET (14 + SW_API_PORT_OFFSET) -#define SW_API_PT_POWERSAVE_SET (15 + SW_API_PORT_OFFSET) -#define SW_API_PT_POWERSAVE_GET (16 + SW_API_PORT_OFFSET) -/*qca808x_start*/ -#define SW_API_PT_HIBERNATE_SET (17 + SW_API_PORT_OFFSET) -#define SW_API_PT_HIBERNATE_GET (18 + SW_API_PORT_OFFSET) -#define SW_API_PT_CDT (19 + SW_API_PORT_OFFSET) -/*qca808x_end*/ -#define SW_API_PT_TXHDR_SET (20 + SW_API_PORT_OFFSET) -#define SW_API_PT_TXHDR_GET (21 + SW_API_PORT_OFFSET) -#define SW_API_PT_RXHDR_SET (22 + SW_API_PORT_OFFSET) -#define SW_API_PT_RXHDR_GET (23 + SW_API_PORT_OFFSET) -#define SW_API_HEADER_TYPE_SET (24 + SW_API_PORT_OFFSET) -#define SW_API_HEADER_TYPE_GET (25 + SW_API_PORT_OFFSET) -#define SW_API_TXMAC_STATUS_SET (26 + SW_API_PORT_OFFSET) -#define SW_API_TXMAC_STATUS_GET (27 + SW_API_PORT_OFFSET) -#define SW_API_RXMAC_STATUS_SET (28 + SW_API_PORT_OFFSET) -#define SW_API_RXMAC_STATUS_GET (29 + SW_API_PORT_OFFSET) -#define SW_API_TXFC_STATUS_SET (30 + SW_API_PORT_OFFSET) -#define SW_API_TXFC_STATUS_GET (31 + SW_API_PORT_OFFSET) -#define SW_API_RXFC_STATUS_SET (32 + SW_API_PORT_OFFSET) -#define SW_API_RXFC_STATUS_GET (33 + SW_API_PORT_OFFSET) -#define SW_API_BP_STATUS_SET (34 + SW_API_PORT_OFFSET) -#define SW_API_BP_STATUS_GET (35 + SW_API_PORT_OFFSET) -#define SW_API_PT_LINK_MODE_SET (36 + SW_API_PORT_OFFSET) -#define SW_API_PT_LINK_MODE_GET (37 + SW_API_PORT_OFFSET) -/*qca808x_start*/ -#define SW_API_PT_LINK_STATUS_GET (38 + SW_API_PORT_OFFSET) -/*qca808x_end*/ -#define SW_API_PT_MAC_LOOPBACK_SET (39+ SW_API_PORT_OFFSET) -#define SW_API_PT_MAC_LOOPBACK_GET (40+ SW_API_PORT_OFFSET) -#define SW_API_PTS_LINK_STATUS_GET (41 + SW_API_PORT_OFFSET) -#define SW_API_PT_CONGESTION_DROP_SET (42+ SW_API_PORT_OFFSET) -#define SW_API_PT_CONGESTION_DROP_GET (43+ SW_API_PORT_OFFSET) -#define SW_API_PT_RING_FLOW_CTRL_THRES_SET (44+ SW_API_PORT_OFFSET) -#define SW_API_PT_RING_FLOW_CTRL_THRES_GET (45+ SW_API_PORT_OFFSET) -/*qca808x_start*/ -#define SW_API_PT_8023AZ_SET (46 + SW_API_PORT_OFFSET) -#define SW_API_PT_8023AZ_GET (47 + SW_API_PORT_OFFSET) -#define SW_API_PT_MDIX_SET (48 + SW_API_PORT_OFFSET) -#define SW_API_PT_MDIX_GET (49 + SW_API_PORT_OFFSET) -#define SW_API_PT_MDIX_STATUS_GET (50 + SW_API_PORT_OFFSET) -/*qca808x_end*/ -#define SW_API_PT_COMBO_PREFER_MEDIUM_SET (51 + SW_API_PORT_OFFSET) -#define SW_API_PT_COMBO_PREFER_MEDIUM_GET (52 + SW_API_PORT_OFFSET) -#define SW_API_PT_COMBO_MEDIUM_STATUS_GET (53 + SW_API_PORT_OFFSET) -#define SW_API_PT_COMBO_FIBER_MODE_SET (54 + SW_API_PORT_OFFSET) -#define SW_API_PT_COMBO_FIBER_MODE_GET (55 + SW_API_PORT_OFFSET) -/*qca808x_start*/ -#define SW_API_PT_LOCAL_LOOPBACK_SET (56 + SW_API_PORT_OFFSET) -#define SW_API_PT_LOCAL_LOOPBACK_GET (57 + SW_API_PORT_OFFSET) -#define SW_API_PT_REMOTE_LOOPBACK_SET (58 + SW_API_PORT_OFFSET) -#define SW_API_PT_REMOTE_LOOPBACK_GET (59 + SW_API_PORT_OFFSET) -#define SW_API_PT_RESET (60 + SW_API_PORT_OFFSET) -#define SW_API_PT_POWER_OFF (61 + SW_API_PORT_OFFSET) -#define SW_API_PT_POWER_ON (62 + SW_API_PORT_OFFSET) -#define SW_API_PT_MAGIC_FRAME_MAC_SET (63 + SW_API_PORT_OFFSET) -#define SW_API_PT_MAGIC_FRAME_MAC_GET (64 + SW_API_PORT_OFFSET) -#define SW_API_PT_PHY_ID_GET (65 + SW_API_PORT_OFFSET) -#define SW_API_PT_WOL_STATUS_SET (66 + SW_API_PORT_OFFSET) -#define SW_API_PT_WOL_STATUS_GET (67 + SW_API_PORT_OFFSET) -/*qca808x_end*/ -#define SW_API_PT_INTERFACE_MODE_SET (68 + SW_API_PORT_OFFSET) -#define SW_API_PT_INTERFACE_MODE_GET (69 + SW_API_PORT_OFFSET) -/*qca808x_start*/ -#define SW_API_PT_INTERFACE_MODE_STATUS_GET (70 + SW_API_PORT_OFFSET) -#define SW_API_DEBUG_PHYCOUNTER_SET (71 + SW_API_PORT_OFFSET) -#define SW_API_DEBUG_PHYCOUNTER_GET (72 + SW_API_PORT_OFFSET) -#define SW_API_DEBUG_PHYCOUNTER_SHOW (73 + SW_API_PORT_OFFSET) -/*qca808x_end*/ -#define SW_API_PT_INTERFACE_MODE_APPLY (74 + SW_API_PORT_OFFSET) -#define SW_API_PT_INTERFACE_3AZ_STATUS_SET (75 + SW_API_PORT_OFFSET) -#define SW_API_PT_INTERFACE_3AZ_STATUS_GET (76 + SW_API_PORT_OFFSET) -#define SW_API_PT_PROMISC_MODE_SET (77 + SW_API_PORT_OFFSET) -#define SW_API_PT_PROMISC_MODE_GET (78 + SW_API_PORT_OFFSET) -#define SW_API_PT_INTERFACE_EEE_CFG_SET (79 + SW_API_PORT_OFFSET) -#define SW_API_PT_INTERFACE_EEE_CFG_GET (80 + SW_API_PORT_OFFSET) -#define SW_API_PT_SWITCH_PORT_LOOPBACK_SET (81 + SW_API_PORT_OFFSET) -#define SW_API_PT_SWITCH_PORT_LOOPBACK_GET (82 + SW_API_PORT_OFFSET) - - - /*vlan*/ -#define SW_API_VLAN_OFFSET 130 -#define SW_API_VLAN_ADD (0 + SW_API_VLAN_OFFSET) -#define SW_API_VLAN_DEL (1 + SW_API_VLAN_OFFSET) -#define SW_API_VLAN_MEM_UPDATE (2 + SW_API_VLAN_OFFSET) -#define SW_API_VLAN_FIND (3 + SW_API_VLAN_OFFSET) -#define SW_API_VLAN_NEXT (4 + SW_API_VLAN_OFFSET) -#define SW_API_VLAN_APPEND (5 + SW_API_VLAN_OFFSET) -#define SW_API_VLAN_FLUSH (6 + SW_API_VLAN_OFFSET) -#define SW_API_VLAN_FID_SET (7 + SW_API_VLAN_OFFSET) -#define SW_API_VLAN_FID_GET (8 + SW_API_VLAN_OFFSET) -#define SW_API_VLAN_MEMBER_ADD (9 + SW_API_VLAN_OFFSET) -#define SW_API_VLAN_MEMBER_DEL (10 + SW_API_VLAN_OFFSET) -#define SW_API_VLAN_LEARN_STATE_SET (11 + SW_API_VLAN_OFFSET) -#define SW_API_VLAN_LEARN_STATE_GET (12 + SW_API_VLAN_OFFSET) -#define SW_API_LAN_WAN_CFG_SET (13 + SW_API_VLAN_OFFSET) -#define SW_API_LAN_WAN_CFG_GET (14 + SW_API_VLAN_OFFSET) - - /*port ctrl extend*/ -#define SW_API_PORT_EXT_OFFSET 160 -#define SW_API_PT_MTU_SET (0 + SW_API_PORT_EXT_OFFSET) -#define SW_API_PT_MTU_GET (1 + SW_API_PORT_EXT_OFFSET) -#define SW_API_PT_MRU_SET (2 + SW_API_PORT_EXT_OFFSET) -#define SW_API_PT_MRU_GET (3 + SW_API_PORT_EXT_OFFSET) -#define SW_API_PT_SOURCE_FILTER_GET (4 + SW_API_PORT_EXT_OFFSET) -#define SW_API_PT_SOURCE_FILTER_SET (5 + SW_API_PORT_EXT_OFFSET) -#define SW_API_PT_FRAME_MAX_SIZE_GET (6 + SW_API_PORT_EXT_OFFSET) -#define SW_API_PT_FRAME_MAX_SIZE_SET (7 + SW_API_PORT_EXT_OFFSET) -#define SW_API_PT_SOURCE_FILTER_CONFIG_GET (8 + SW_API_PORT_EXT_OFFSET) -#define SW_API_PT_SOURCE_FILTER_CONFIG_SET (9 + SW_API_PORT_EXT_OFFSET) - - - /*portvlan*/ -#define SW_API_PORTVLAN_OFFSET 200 -#define SW_API_PT_ING_MODE_GET (0 + SW_API_PORTVLAN_OFFSET) -#define SW_API_PT_ING_MODE_SET (1 + SW_API_PORTVLAN_OFFSET) -#define SW_API_PT_EG_MODE_GET (2 + SW_API_PORTVLAN_OFFSET) -#define SW_API_PT_EG_MODE_SET (3 + SW_API_PORTVLAN_OFFSET) -#define SW_API_PT_VLAN_MEM_ADD (4 + SW_API_PORTVLAN_OFFSET) -#define SW_API_PT_VLAN_MEM_DEL (5 + SW_API_PORTVLAN_OFFSET) -#define SW_API_PT_VLAN_MEM_UPDATE (6 + SW_API_PORTVLAN_OFFSET) -#define SW_API_PT_VLAN_MEM_GET (7 + SW_API_PORTVLAN_OFFSET) -#define SW_API_PT_DEF_VID_GET (8 + SW_API_PORTVLAN_OFFSET) -#define SW_API_PT_DEF_VID_SET (9 + SW_API_PORTVLAN_OFFSET) -#define SW_API_PT_FORCE_DEF_VID_SET (10 + SW_API_PORTVLAN_OFFSET) -#define SW_API_PT_FORCE_DEF_VID_GET (11 + SW_API_PORTVLAN_OFFSET) -#define SW_API_PT_FORCE_PORTVLAN_SET (12 + SW_API_PORTVLAN_OFFSET) -#define SW_API_PT_FORCE_PORTVLAN_GET (13 + SW_API_PORTVLAN_OFFSET) -#define SW_API_PT_NESTVLAN_SET (14 + SW_API_PORTVLAN_OFFSET) -#define SW_API_PT_NESTVLAN_GET (15 + SW_API_PORTVLAN_OFFSET) -#define SW_API_NESTVLAN_TPID_SET (16 + SW_API_PORTVLAN_OFFSET) -#define SW_API_NESTVLAN_TPID_GET (17 + SW_API_PORTVLAN_OFFSET) -#define SW_API_PT_IN_VLAN_MODE_SET (18 + SW_API_PORTVLAN_OFFSET) -#define SW_API_PT_IN_VLAN_MODE_GET (19 + SW_API_PORTVLAN_OFFSET) -#define SW_API_PT_TLS_SET (20 + SW_API_PORTVLAN_OFFSET) -#define SW_API_PT_TLS_GET (21 + SW_API_PORTVLAN_OFFSET) -#define SW_API_PT_PRI_PROPAGATION_SET (22 + SW_API_PORTVLAN_OFFSET) -#define SW_API_PT_PRI_PROPAGATION_GET (23 + SW_API_PORTVLAN_OFFSET) -#define SW_API_PT_DEF_SVID_SET (24 + SW_API_PORTVLAN_OFFSET) -#define SW_API_PT_DEF_SVID_GET (25 + SW_API_PORTVLAN_OFFSET) -#define SW_API_PT_DEF_CVID_SET (26 + SW_API_PORTVLAN_OFFSET) -#define SW_API_PT_DEF_CVID_GET (27 + SW_API_PORTVLAN_OFFSET) -#define SW_API_PT_VLAN_PROPAGATION_SET (28 + SW_API_PORTVLAN_OFFSET) -#define SW_API_PT_VLAN_PROPAGATION_GET (29 + SW_API_PORTVLAN_OFFSET) -#define SW_API_PT_VLAN_TRANS_ADD (30 + SW_API_PORTVLAN_OFFSET) -#define SW_API_PT_VLAN_TRANS_DEL (31 + SW_API_PORTVLAN_OFFSET) -#define SW_API_PT_VLAN_TRANS_GET (32 + SW_API_PORTVLAN_OFFSET) -#define SW_API_QINQ_MODE_SET (33 + SW_API_PORTVLAN_OFFSET) -#define SW_API_QINQ_MODE_GET (34 + SW_API_PORTVLAN_OFFSET) -#define SW_API_PT_QINQ_ROLE_SET (35 + SW_API_PORTVLAN_OFFSET) -#define SW_API_PT_QINQ_ROLE_GET (36 + SW_API_PORTVLAN_OFFSET) -#define SW_API_PT_VLAN_TRANS_ITERATE (37 + SW_API_PORTVLAN_OFFSET) -#define SW_API_PT_MAC_VLAN_XLT_SET (38 + SW_API_PORTVLAN_OFFSET) -#define SW_API_PT_MAC_VLAN_XLT_GET (39 + SW_API_PORTVLAN_OFFSET) -#define SW_API_NETISOLATE_SET (40 + SW_API_PORTVLAN_OFFSET) -#define SW_API_NETISOLATE_GET (41 + SW_API_PORTVLAN_OFFSET) -#define SW_API_EG_FLTR_BYPASS_EN_SET (42 + SW_API_PORTVLAN_OFFSET) -#define SW_API_EG_FLTR_BYPASS_EN_GET (43 + SW_API_PORTVLAN_OFFSET) -#define SW_API_PT_VRF_ID_SET (44 + SW_API_PORTVLAN_OFFSET) -#define SW_API_PT_VRF_ID_GET (45 + SW_API_PORTVLAN_OFFSET) - -#define SW_API_GLOBAL_QINQ_MODE_SET (46 + SW_API_PORTVLAN_OFFSET) -#define SW_API_GLOBAL_QINQ_MODE_GET (47 + SW_API_PORTVLAN_OFFSET) -#define SW_API_PORT_QINQ_MODE_SET (48 + SW_API_PORTVLAN_OFFSET) -#define SW_API_PORT_QINQ_MODE_GET (49 + SW_API_PORTVLAN_OFFSET) -#define SW_API_TPID_SET (50 + SW_API_PORTVLAN_OFFSET) -#define SW_API_TPID_GET (51 + SW_API_PORTVLAN_OFFSET) -#define SW_API_EGRESS_TPID_SET (52 + SW_API_PORTVLAN_OFFSET) -#define SW_API_EGRESS_TPID_GET (53 + SW_API_PORTVLAN_OFFSET) -#define SW_API_PT_INGRESS_VLAN_FILTER_SET (54 + SW_API_PORTVLAN_OFFSET) -#define SW_API_PT_INGRESS_VLAN_FILTER_GET (55 + SW_API_PORTVLAN_OFFSET) -#define SW_API_PT_DEFAULT_VLANTAG_SET (56 + SW_API_PORTVLAN_OFFSET) -#define SW_API_PT_DEFAULT_VLANTAG_GET (57 + SW_API_PORTVLAN_OFFSET) -#define SW_API_PT_TAG_PROPAGATION_SET (58 + SW_API_PORTVLAN_OFFSET) -#define SW_API_PT_TAG_PROPAGATION_GET (59 + SW_API_PORTVLAN_OFFSET) -#define SW_API_PT_VLANTAG_EGMODE_SET (60 + SW_API_PORTVLAN_OFFSET) -#define SW_API_PT_VLANTAG_EGMODE_GET (61 + SW_API_PORTVLAN_OFFSET) -#define SW_API_PT_VLAN_XLT_MISS_CMD_SET (62 + SW_API_PORTVLAN_OFFSET) -#define SW_API_PT_VLAN_XLT_MISS_CMD_GET (63 + SW_API_PORTVLAN_OFFSET) -#define SW_API_PT_VSI_EGMODE_SET (64 + SW_API_PORTVLAN_OFFSET) -#define SW_API_PT_VSI_EGMODE_GET (65 + SW_API_PORTVLAN_OFFSET) -#define SW_API_PT_VLANTAG_VSI_EGMODE_EN_SET (66 + SW_API_PORTVLAN_OFFSET) -#define SW_API_PT_VLANTAG_VSI_EGMODE_EN_GET (67 + SW_API_PORTVLAN_OFFSET) -#define SW_API_PT_VLAN_TRANS_ADV_ADD (68 + SW_API_PORTVLAN_OFFSET) -#define SW_API_PT_VLAN_TRANS_ADV_DEL (69 + SW_API_PORTVLAN_OFFSET) -#define SW_API_PT_VLAN_TRANS_ADV_GETFIRST (70 + SW_API_PORTVLAN_OFFSET) -#define SW_API_PT_VLAN_TRANS_ADV_GETNEXT (71 + SW_API_PORTVLAN_OFFSET) -#define SW_API_PT_VLAN_COUNTER_GET (72 + SW_API_PORTVLAN_OFFSET) -#define SW_API_PT_VLAN_COUNTER_CLEANUP (73 + SW_API_PORTVLAN_OFFSET) - - - /*fdb*/ -#define SW_API_FDB_OFFSET 300 -#define SW_API_FDB_ADD (0 + SW_API_FDB_OFFSET) -#define SW_API_FDB_DELALL (1 + SW_API_FDB_OFFSET) -#define SW_API_FDB_DELPORT (2 + SW_API_FDB_OFFSET) -#define SW_API_FDB_DELMAC (3 + SW_API_FDB_OFFSET) -#define SW_API_FDB_FIRST (4 + SW_API_FDB_OFFSET) -#define SW_API_FDB_NEXT (5 + SW_API_FDB_OFFSET) -#define SW_API_FDB_FIND (6 + SW_API_FDB_OFFSET) -#define SW_API_FDB_PT_LEARN_SET (7 + SW_API_FDB_OFFSET) -#define SW_API_FDB_PT_LEARN_GET (8 + SW_API_FDB_OFFSET) -#define SW_API_FDB_AGE_CTRL_SET (9 + SW_API_FDB_OFFSET) -#define SW_API_FDB_AGE_CTRL_GET (10 + SW_API_FDB_OFFSET) -#define SW_API_FDB_AGE_TIME_SET (11 + SW_API_FDB_OFFSET) -#define SW_API_FDB_AGE_TIME_GET (12 + SW_API_FDB_OFFSET) -#define SW_API_FDB_ITERATE (13 + SW_API_FDB_OFFSET) -#define SW_API_FDB_EXTEND_NEXT (14 + SW_API_FDB_OFFSET) -#define SW_API_PT_FDB_LEARN_LIMIT_SET (15 + SW_API_FDB_OFFSET) -#define SW_API_PT_FDB_LEARN_LIMIT_GET (16 + SW_API_FDB_OFFSET) -#define SW_API_PT_FDB_LEARN_EXCEED_CMD_SET (17 + SW_API_FDB_OFFSET) -#define SW_API_PT_FDB_LEARN_EXCEED_CMD_GET (18 + SW_API_FDB_OFFSET) -#define SW_API_FDB_LEARN_LIMIT_SET (19 + SW_API_FDB_OFFSET) -#define SW_API_FDB_LEARN_LIMIT_GET (20 + SW_API_FDB_OFFSET) -#define SW_API_FDB_LEARN_EXCEED_CMD_SET (21 + SW_API_FDB_OFFSET) -#define SW_API_FDB_LEARN_EXCEED_CMD_GET (22 + SW_API_FDB_OFFSET) -#define SW_API_FDB_RESV_ADD (23 + SW_API_FDB_OFFSET) -#define SW_API_FDB_RESV_DEL (24 + SW_API_FDB_OFFSET) -#define SW_API_FDB_RESV_FIND (25 + SW_API_FDB_OFFSET) -#define SW_API_FDB_RESV_ITERATE (26 + SW_API_FDB_OFFSET) -#define SW_API_FDB_EXTEND_FIRST (27 + SW_API_FDB_OFFSET) -#define SW_API_FDB_PT_LEARN_STATIC_SET (28 + SW_API_FDB_OFFSET) -#define SW_API_FDB_PT_LEARN_STATIC_GET (29 + SW_API_FDB_OFFSET) -#define SW_API_FDB_TRANSFER (30 + SW_API_FDB_OFFSET) -#define SW_API_FDB_PORT_ADD (31 + SW_API_FDB_OFFSET) -#define SW_API_FDB_PORT_DEL (32 + SW_API_FDB_OFFSET) -#define SW_API_FDB_VLAN_IVL_SVL_SET (33 + SW_API_FDB_OFFSET) -#define SW_API_FDB_VLAN_IVL_SVL_GET (34 + SW_API_FDB_OFFSET) -#define SW_API_FDB_RFS_SET (35 + SW_API_FDB_OFFSET) -#define SW_API_FDB_RFS_DEL (36 + SW_API_FDB_OFFSET) -#define SW_API_FDB_LEARN_CTRL_SET (37 + SW_API_FDB_OFFSET) -#define SW_API_FDB_LEARN_CTRL_GET (38 + SW_API_FDB_OFFSET) -#define SW_API_PT_FDB_LEARN_COUNTER_GET (39 + SW_API_FDB_OFFSET) -#define SW_API_FDB_PT_NEWADDR_LEARN_SET (40 + SW_API_FDB_OFFSET) -#define SW_API_FDB_PT_NEWADDR_LEARN_GET (41 + SW_API_FDB_OFFSET) -#define SW_API_FDB_PT_STAMOVE_SET (42 + SW_API_FDB_OFFSET) -#define SW_API_FDB_PT_STAMOVE_GET (43 + SW_API_FDB_OFFSET) -#define SW_API_FDB_PT_MACLIMIT_CTRL_SET (44 + SW_API_FDB_OFFSET) -#define SW_API_FDB_PT_MACLIMIT_CTRL_GET (45 + SW_API_FDB_OFFSET) -#define SW_API_FDB_DEL_BY_FID (46 + SW_API_FDB_OFFSET) - - - /*acl*/ -#define SW_API_ACL_OFFSET 400 -#define SW_API_ACL_LIST_CREAT (0 + SW_API_ACL_OFFSET) -#define SW_API_ACL_LIST_DESTROY (1 + SW_API_ACL_OFFSET) -#define SW_API_ACL_RULE_ADD (2 + SW_API_ACL_OFFSET) -#define SW_API_ACL_RULE_DELETE (3 + SW_API_ACL_OFFSET) -#define SW_API_ACL_RULE_QUERY (4 + SW_API_ACL_OFFSET) -#define SW_API_ACL_LIST_BIND (5 + SW_API_ACL_OFFSET) -#define SW_API_ACL_LIST_UNBIND (6 + SW_API_ACL_OFFSET) -#define SW_API_ACL_STATUS_SET (7 + SW_API_ACL_OFFSET) -#define SW_API_ACL_STATUS_GET (8 + SW_API_ACL_OFFSET) -#define SW_API_ACL_LIST_DUMP (9 + SW_API_ACL_OFFSET) -#define SW_API_ACL_RULE_DUMP (10 + SW_API_ACL_OFFSET) -#define SW_API_ACL_PT_UDF_PROFILE_SET (11 + SW_API_ACL_OFFSET) -#define SW_API_ACL_PT_UDF_PROFILE_GET (12 + SW_API_ACL_OFFSET) -#define SW_API_ACL_RULE_ACTIVE (13 + SW_API_ACL_OFFSET) -#define SW_API_ACL_RULE_DEACTIVE (14 + SW_API_ACL_OFFSET) -#define SW_API_ACL_RULE_SRC_FILTER_STS_SET (15 + SW_API_ACL_OFFSET) -#define SW_API_ACL_RULE_SRC_FILTER_STS_GET (16 + SW_API_ACL_OFFSET) -#define SW_API_ACL_RULE_GET_OFFSET (17 + SW_API_ACL_OFFSET) -#define SW_API_ACL_UDF_SET (18 + SW_API_ACL_OFFSET) -#define SW_API_ACL_UDF_GET (19 + SW_API_ACL_OFFSET) - - /*qos*/ -#define SW_API_QOS_OFFSET 500 -#define SW_API_QOS_SCH_MODE_SET (0 + SW_API_QOS_OFFSET) -#define SW_API_QOS_SCH_MODE_GET (1 + SW_API_QOS_OFFSET) -#define SW_API_QOS_QU_TX_BUF_ST_SET (2 + SW_API_QOS_OFFSET) -#define SW_API_QOS_QU_TX_BUF_ST_GET (3 + SW_API_QOS_OFFSET) -#define SW_API_QOS_QU_TX_BUF_NR_SET (4 + SW_API_QOS_OFFSET) -#define SW_API_QOS_QU_TX_BUF_NR_GET (5 + SW_API_QOS_OFFSET) -#define SW_API_QOS_PT_TX_BUF_ST_SET (6 + SW_API_QOS_OFFSET) -#define SW_API_QOS_PT_TX_BUF_ST_GET (7 + SW_API_QOS_OFFSET) -#define SW_API_QOS_PT_TX_BUF_NR_SET (8 + SW_API_QOS_OFFSET) -#define SW_API_QOS_PT_TX_BUF_NR_GET (9 + SW_API_QOS_OFFSET) -#define SW_API_QOS_PT_RX_BUF_NR_SET (10 + SW_API_QOS_OFFSET) -#define SW_API_QOS_PT_RX_BUF_NR_GET (11 + SW_API_QOS_OFFSET) -#define SW_API_QOS_PT_MODE_SET (12 + SW_API_QOS_OFFSET) -#define SW_API_QOS_PT_MODE_GET (13 + SW_API_QOS_OFFSET) -#define SW_API_QOS_PT_MODE_PRI_SET (14 + SW_API_QOS_OFFSET) -#define SW_API_QOS_PT_MODE_PRI_GET (15 + SW_API_QOS_OFFSET) -#define SW_API_QOS_PORT_DEF_UP_SET (16 + SW_API_QOS_OFFSET) -#define SW_API_QOS_PORT_DEF_UP_GET (17 + SW_API_QOS_OFFSET) -#define SW_API_QOS_PORT_SCH_MODE_SET (18 + SW_API_QOS_OFFSET) -#define SW_API_QOS_PORT_SCH_MODE_GET (19 + SW_API_QOS_OFFSET) -#define SW_API_QOS_PT_DEF_SPRI_SET (20 + SW_API_QOS_OFFSET) -#define SW_API_QOS_PT_DEF_SPRI_GET (21 + SW_API_QOS_OFFSET) -#define SW_API_QOS_PT_DEF_CPRI_SET (22 + SW_API_QOS_OFFSET) -#define SW_API_QOS_PT_DEF_CPRI_GET (23 + SW_API_QOS_OFFSET) -#define SW_API_QOS_PT_FORCE_SPRI_ST_SET (24 + SW_API_QOS_OFFSET) -#define SW_API_QOS_PT_FORCE_SPRI_ST_GET (25 + SW_API_QOS_OFFSET) -#define SW_API_QOS_PT_FORCE_CPRI_ST_SET (26 + SW_API_QOS_OFFSET) -#define SW_API_QOS_PT_FORCE_CPRI_ST_GET (27 + SW_API_QOS_OFFSET) -#define SW_API_QOS_QUEUE_REMARK_SET (28 + SW_API_QOS_OFFSET) -#define SW_API_QOS_QUEUE_REMARK_GET (29 + SW_API_QOS_OFFSET) -#define SW_API_QOS_PT_RED_EN_SET (30 + SW_API_QOS_OFFSET) -#define SW_API_QOS_PT_RED_EN_GET (31 + SW_API_QOS_OFFSET) -#define SW_API_QOS_PORT_GROUP_GET (32 + SW_API_QOS_OFFSET) -#define SW_API_QOS_PORT_GROUP_SET (33 + SW_API_QOS_OFFSET) -#define SW_API_QOS_PORT_PRI_GET (34 + SW_API_QOS_OFFSET) -#define SW_API_QOS_PORT_PRI_SET (35 + SW_API_QOS_OFFSET) -#define SW_API_QOS_PORT_REMARK_GET (36 + SW_API_QOS_OFFSET) -#define SW_API_QOS_PORT_REMARK_SET (37 + SW_API_QOS_OFFSET) -#define SW_API_QOS_PCP_MAP_GET (38 + SW_API_QOS_OFFSET) -#define SW_API_QOS_PCP_MAP_SET (39 + SW_API_QOS_OFFSET) -#define SW_API_QOS_FLOW_MAP_GET (40 + SW_API_QOS_OFFSET) -#define SW_API_QOS_FLOW_MAP_SET (41 + SW_API_QOS_OFFSET) -#define SW_API_QOS_DSCP_MAP_GET (42 + SW_API_QOS_OFFSET) -#define SW_API_QOS_DSCP_MAP_SET (43 + SW_API_QOS_OFFSET) -#define SW_API_QOS_QUEUE_SCHEDULER_GET (44 + SW_API_QOS_OFFSET) -#define SW_API_QOS_QUEUE_SCHEDULER_SET (45 + SW_API_QOS_OFFSET) -#define SW_API_QOS_RING_QUEUE_MAP_GET (46 + SW_API_QOS_OFFSET) -#define SW_API_QOS_RING_QUEUE_MAP_SET (47 + SW_API_QOS_OFFSET) -#define SW_API_QOS_PORT_QUEUES_GET (48 + SW_API_QOS_OFFSET) -#define SW_API_QOS_SCHEDULER_DEQUEU_CTRL_GET (49 + SW_API_QOS_OFFSET) -#define SW_API_QOS_SCHEDULER_DEQUEU_CTRL_SET (50 + SW_API_QOS_OFFSET) -#define SW_API_QOS_PORT_SCHEDULER_CFG_RESET (51 + SW_API_QOS_OFFSET) -#define SW_API_QOS_PORT_SCHEDULER_RESOURCE_GET (52 + SW_API_QOS_OFFSET) - - /* igmp */ -#define SW_API_IGMP_OFFSET 600 -#define SW_API_PT_IGMPS_MODE_SET (0 + SW_API_IGMP_OFFSET) -#define SW_API_PT_IGMPS_MODE_GET (1 + SW_API_IGMP_OFFSET) -#define SW_API_IGMP_MLD_CMD_SET (2 + SW_API_IGMP_OFFSET) -#define SW_API_IGMP_MLD_CMD_GET (3 + SW_API_IGMP_OFFSET) -#define SW_API_IGMP_PT_JOIN_SET (4 + SW_API_IGMP_OFFSET) -#define SW_API_IGMP_PT_JOIN_GET (5 + SW_API_IGMP_OFFSET) -#define SW_API_IGMP_PT_LEAVE_SET (6 + SW_API_IGMP_OFFSET) -#define SW_API_IGMP_PT_LEAVE_GET (7 + SW_API_IGMP_OFFSET) -#define SW_API_IGMP_RP_SET (8 + SW_API_IGMP_OFFSET) -#define SW_API_IGMP_RP_GET (9 + SW_API_IGMP_OFFSET) -#define SW_API_IGMP_ENTRY_CREAT_SET (10 + SW_API_IGMP_OFFSET) -#define SW_API_IGMP_ENTRY_CREAT_GET (11 + SW_API_IGMP_OFFSET) -#define SW_API_IGMP_ENTRY_STATIC_SET (12 + SW_API_IGMP_OFFSET) -#define SW_API_IGMP_ENTRY_STATIC_GET (13 + SW_API_IGMP_OFFSET) -#define SW_API_IGMP_ENTRY_LEAKY_SET (14 + SW_API_IGMP_OFFSET) -#define SW_API_IGMP_ENTRY_LEAKY_GET (15 + SW_API_IGMP_OFFSET) -#define SW_API_IGMP_ENTRY_V3_SET (16 + SW_API_IGMP_OFFSET) -#define SW_API_IGMP_ENTRY_V3_GET (17 + SW_API_IGMP_OFFSET) -#define SW_API_IGMP_ENTRY_QUEUE_SET (18 + SW_API_IGMP_OFFSET) -#define SW_API_IGMP_ENTRY_QUEUE_GET (19 + SW_API_IGMP_OFFSET) -#define SW_API_PT_IGMP_LEARN_LIMIT_SET (20 + SW_API_IGMP_OFFSET) -#define SW_API_PT_IGMP_LEARN_LIMIT_GET (21 + SW_API_IGMP_OFFSET) -#define SW_API_PT_IGMP_LEARN_EXCEED_CMD_SET (22 + SW_API_IGMP_OFFSET) -#define SW_API_PT_IGMP_LEARN_EXCEED_CMD_GET (23 + SW_API_IGMP_OFFSET) -#define SW_API_IGMP_SG_ENTRY_SET (24 + SW_API_IGMP_OFFSET) -#define SW_API_IGMP_SG_ENTRY_CLEAR (25 + SW_API_IGMP_OFFSET) -#define SW_API_IGMP_SG_ENTRY_SHOW (26 + SW_API_IGMP_OFFSET) -#define SW_API_IGMP_SG_ENTRY_QUERY (27 + SW_API_IGMP_OFFSET) - - /* leaky */ -#define SW_API_LEAKY_OFFSET 700 -#define SW_API_UC_LEAKY_MODE_SET (0 + SW_API_LEAKY_OFFSET) -#define SW_API_UC_LEAKY_MODE_GET (1 + SW_API_LEAKY_OFFSET) -#define SW_API_MC_LEAKY_MODE_SET (2 + SW_API_LEAKY_OFFSET) -#define SW_API_MC_LEAKY_MODE_GET (3 + SW_API_LEAKY_OFFSET) -#define SW_API_ARP_LEAKY_MODE_SET (4 + SW_API_LEAKY_OFFSET) -#define SW_API_ARP_LEAKY_MODE_GET (5 + SW_API_LEAKY_OFFSET) -#define SW_API_PT_UC_LEAKY_MODE_SET (6 + SW_API_LEAKY_OFFSET) -#define SW_API_PT_UC_LEAKY_MODE_GET (7 + SW_API_LEAKY_OFFSET) -#define SW_API_PT_MC_LEAKY_MODE_SET (8 + SW_API_LEAKY_OFFSET) -#define SW_API_PT_MC_LEAKY_MODE_GET (9 + SW_API_LEAKY_OFFSET) - - /*mirror*/ -#define SW_API_MIR_OFFSET 800 -#define SW_API_MIRROR_ANALY_PT_SET (0 + SW_API_MIR_OFFSET) -#define SW_API_MIRROR_ANALY_PT_GET (1 + SW_API_MIR_OFFSET) -#define SW_API_MIRROR_IN_PT_SET (2 + SW_API_MIR_OFFSET) -#define SW_API_MIRROR_IN_PT_GET (3 + SW_API_MIR_OFFSET) -#define SW_API_MIRROR_EG_PT_SET (4 + SW_API_MIR_OFFSET) -#define SW_API_MIRROR_EG_PT_GET (5 + SW_API_MIR_OFFSET) -#define SW_API_MIRROR_ANALYSIS_CONFIG_SET (6 + SW_API_MIR_OFFSET) -#define SW_API_MIRROR_ANALYSIS_CONFIG_GET (7 + SW_API_MIR_OFFSET) - - /*rate*/ -#define SW_API_RATE_OFFSET 900 -#define SW_API_RATE_QU_EGRL_SET (0 + SW_API_RATE_OFFSET) -#define SW_API_RATE_QU_EGRL_GET (1 + SW_API_RATE_OFFSET) -#define SW_API_RATE_PT_EGRL_SET (2 + SW_API_RATE_OFFSET) -#define SW_API_RATE_PT_EGRL_GET (3 + SW_API_RATE_OFFSET) -#define SW_API_RATE_PT_INRL_SET (4 + SW_API_RATE_OFFSET) -#define SW_API_RATE_PT_INRL_GET (5 + SW_API_RATE_OFFSET) -#define SW_API_STORM_CTRL_FRAME_SET (6 + SW_API_RATE_OFFSET) -#define SW_API_STORM_CTRL_FRAME_GET (7 + SW_API_RATE_OFFSET) -#define SW_API_STORM_CTRL_RATE_SET (8 + SW_API_RATE_OFFSET) -#define SW_API_STORM_CTRL_RATE_GET (9 + SW_API_RATE_OFFSET) -#define SW_API_RATE_PORT_POLICER_SET (10 + SW_API_RATE_OFFSET) -#define SW_API_RATE_PORT_POLICER_GET (11 + SW_API_RATE_OFFSET) -#define SW_API_RATE_PORT_SHAPER_SET (12 + SW_API_RATE_OFFSET) -#define SW_API_RATE_PORT_SHAPER_GET (13 + SW_API_RATE_OFFSET) -#define SW_API_RATE_QUEUE_SHAPER_SET (14 + SW_API_RATE_OFFSET) -#define SW_API_RATE_QUEUE_SHAPER_GET (15 + SW_API_RATE_OFFSET) -#define SW_API_RATE_ACL_POLICER_SET (16 + SW_API_RATE_OFFSET) -#define SW_API_RATE_ACL_POLICER_GET (17 + SW_API_RATE_OFFSET) -#define SW_API_RATE_PT_ADDRATEBYTE_SET (18 + SW_API_RATE_OFFSET) -#define SW_API_RATE_PT_ADDRATEBYTE_GET (19 + SW_API_RATE_OFFSET) -#define SW_API_RATE_PT_GOL_FLOW_EN_SET (20 + SW_API_RATE_OFFSET) -#define SW_API_RATE_PT_GOL_FLOW_EN_GET (21 + SW_API_RATE_OFFSET) - - /*stp*/ -#define SW_API_STP_OFFSET 1000 -#define SW_API_STP_PT_STATE_SET (0 + SW_API_STP_OFFSET) -#define SW_API_STP_PT_STATE_GET (1 + SW_API_STP_OFFSET) - - /*mib*/ -#define SW_API_MIB_OFFSET 1100 -#define SW_API_PT_MIB_GET (0 + SW_API_MIB_OFFSET) -#define SW_API_MIB_STATUS_SET (1 + SW_API_MIB_OFFSET) -#define SW_API_MIB_STATUS_GET (2 + SW_API_MIB_OFFSET) -#define SW_API_PT_MIB_FLUSH_COUNTERS (3+ SW_API_MIB_OFFSET) -#define SW_API_MIB_CPU_KEEP_SET (4+ SW_API_MIB_OFFSET) -#define SW_API_MIB_CPU_KEEP_GET (5+ SW_API_MIB_OFFSET) -#define SW_API_PT_XGMIB_GET (6+ SW_API_MIB_OFFSET) -#define SW_API_PT_MIB_COUNTER_GET (7+ SW_API_MIB_OFFSET) - - /*misc*/ -#define SW_API_MISC_OFFSET 1200 -#define SW_API_ARP_STATUS_SET (0 + SW_API_MISC_OFFSET) -#define SW_API_ARP_STATUS_GET (1 + SW_API_MISC_OFFSET) -#define SW_API_FRAME_MAX_SIZE_SET (2 + SW_API_MISC_OFFSET) -#define SW_API_FRAME_MAX_SIZE_GET (3 + SW_API_MISC_OFFSET) -#define SW_API_PT_UNK_SA_CMD_SET (4 + SW_API_MISC_OFFSET) -#define SW_API_PT_UNK_SA_CMD_GET (5 + SW_API_MISC_OFFSET) -#define SW_API_PT_UNK_UC_FILTER_SET (6 + SW_API_MISC_OFFSET) -#define SW_API_PT_UNK_UC_FILTER_GET (7 + SW_API_MISC_OFFSET) -#define SW_API_PT_UNK_MC_FILTER_SET (8 + SW_API_MISC_OFFSET) -#define SW_API_PT_UNK_MC_FILTER_GET (9 + SW_API_MISC_OFFSET) -#define SW_API_PT_BC_FILTER_SET (10 + SW_API_MISC_OFFSET) -#define SW_API_PT_BC_FILTER_GET (11 + SW_API_MISC_OFFSET) -#define SW_API_CPU_PORT_STATUS_SET (12 + SW_API_MISC_OFFSET) -#define SW_API_CPU_PORT_STATUS_GET (13 + SW_API_MISC_OFFSET) -#define SW_API_BC_TO_CPU_PORT_SET (14 + SW_API_MISC_OFFSET) -#define SW_API_BC_TO_CPU_PORT_GET (15 + SW_API_MISC_OFFSET) -#define SW_API_PPPOE_CMD_SET (16 + SW_API_MISC_OFFSET) -#define SW_API_PPPOE_CMD_GET (17 + SW_API_MISC_OFFSET) -#define SW_API_PPPOE_STATUS_SET (18 + SW_API_MISC_OFFSET) -#define SW_API_PPPOE_STATUS_GET (19 + SW_API_MISC_OFFSET) -#define SW_API_PT_DHCP_SET (20 + SW_API_MISC_OFFSET) -#define SW_API_PT_DHCP_GET (21 + SW_API_MISC_OFFSET) -#define SW_API_ARP_CMD_SET (22 + SW_API_MISC_OFFSET) -#define SW_API_ARP_CMD_GET (23 + SW_API_MISC_OFFSET) -#define SW_API_EAPOL_CMD_SET (24 + SW_API_MISC_OFFSET) -#define SW_API_EAPOL_CMD_GET (25 + SW_API_MISC_OFFSET) -#define SW_API_PPPOE_SESSION_ADD (26 + SW_API_MISC_OFFSET) -#define SW_API_PPPOE_SESSION_DEL (27 + SW_API_MISC_OFFSET) -#define SW_API_PPPOE_SESSION_GET (28 + SW_API_MISC_OFFSET) -#define SW_API_EAPOL_STATUS_SET (29 + SW_API_MISC_OFFSET) -#define SW_API_EAPOL_STATUS_GET (30 + SW_API_MISC_OFFSET) -#define SW_API_RIPV1_STATUS_SET (31 + SW_API_MISC_OFFSET) -#define SW_API_RIPV1_STATUS_GET (32 + SW_API_MISC_OFFSET) -#define SW_API_PT_ARP_REQ_STATUS_SET (33 + SW_API_MISC_OFFSET) -#define SW_API_PT_ARP_REQ_STATUS_GET (34 + SW_API_MISC_OFFSET) -#define SW_API_PT_ARP_ACK_STATUS_SET (35 + SW_API_MISC_OFFSET) -#define SW_API_PT_ARP_ACK_STATUS_GET (36 + SW_API_MISC_OFFSET) -#define SW_API_PPPOE_SESSION_TABLE_ADD (37 + SW_API_MISC_OFFSET) -#define SW_API_PPPOE_SESSION_TABLE_DEL (38 + SW_API_MISC_OFFSET) -#define SW_API_PPPOE_SESSION_TABLE_GET (39 + SW_API_MISC_OFFSET) -#define SW_API_PPPOE_SESSION_ID_SET (40 + SW_API_MISC_OFFSET) -#define SW_API_PPPOE_SESSION_ID_GET (41 + SW_API_MISC_OFFSET) -#define SW_API_INTR_MASK_SET (42 + SW_API_MISC_OFFSET) -#define SW_API_INTR_MASK_GET (43 + SW_API_MISC_OFFSET) -#define SW_API_INTR_STATUS_GET (44 + SW_API_MISC_OFFSET) -#define SW_API_INTR_STATUS_CLEAR (45 + SW_API_MISC_OFFSET) -#define SW_API_INTR_PORT_LINK_MASK_SET (46 + SW_API_MISC_OFFSET) -#define SW_API_INTR_PORT_LINK_MASK_GET (47 + SW_API_MISC_OFFSET) -#define SW_API_INTR_PORT_LINK_STATUS_GET (48 + SW_API_MISC_OFFSET) -#define SW_API_INTR_MASK_MAC_LINKCHG_SET (49 + SW_API_MISC_OFFSET) -#define SW_API_INTR_MASK_MAC_LINKCHG_GET (50 + SW_API_MISC_OFFSET) -#define SW_API_INTR_STATUS_MAC_LINKCHG_GET (51 + SW_API_MISC_OFFSET) -#define SW_API_INTR_STATUS_MAC_LINKCHG_CLEAR (52 + SW_API_MISC_OFFSET) -#define SW_API_CPU_VID_EN_SET (53 + SW_API_MISC_OFFSET) -#define SW_API_CPU_VID_EN_GET (54 + SW_API_MISC_OFFSET) -#define SW_API_RTD_PPPOE_EN_SET (55 + SW_API_MISC_OFFSET) -#define SW_API_RTD_PPPOE_EN_GET (56 + SW_API_MISC_OFFSET) -#define SW_API_GLOBAL_MACADDR_SET (57 + SW_API_MISC_OFFSET) -#define SW_API_GLOBAL_MACADDR_GET (58 + SW_API_MISC_OFFSET) -#define SW_API_LLDP_STATUS_SET (59 + SW_API_MISC_OFFSET) -#define SW_API_LLDP_STATUS_GET (60 + SW_API_MISC_OFFSET) -#define SW_API_FRAME_CRC_RESERVE_SET (61 + SW_API_MISC_OFFSET) -#define SW_API_FRAME_CRC_RESERVE_GET (62 + SW_API_MISC_OFFSET) -#define SW_API_PPPOE_EN_SET (63 + SW_API_MISC_OFFSET) -#define SW_API_PPPOE_EN_GET (64 + SW_API_MISC_OFFSET) -#define SW_API_DEBUG_PORT_COUNTER_ENABLE (65 + SW_API_MISC_OFFSET) -#define SW_API_DEBUG_PORT_COUNTER_STATUS_GET (66 + SW_API_MISC_OFFSET) - - /*led*/ -#define SW_API_LED_OFFSET 1300 -#define SW_API_LED_PATTERN_SET (0 + SW_API_LED_OFFSET) -#define SW_API_LED_PATTERN_GET (1 + SW_API_LED_OFFSET) - - /* cosmap */ -#define SW_API_COSMAP_OFFSET 1400 -#define SW_API_COSMAP_UP_QU_SET (0 + SW_API_COSMAP_OFFSET) -#define SW_API_COSMAP_UP_QU_GET (1 + SW_API_COSMAP_OFFSET) -#define SW_API_COSMAP_DSCP_QU_SET (2 + SW_API_COSMAP_OFFSET) -#define SW_API_COSMAP_DSCP_QU_GET (3 + SW_API_COSMAP_OFFSET) -#define SW_API_COSMAP_DSCP_TO_PRI_SET (4 + SW_API_COSMAP_OFFSET) -#define SW_API_COSMAP_DSCP_TO_PRI_GET (5 + SW_API_COSMAP_OFFSET) -#define SW_API_COSMAP_DSCP_TO_DP_SET (6 + SW_API_COSMAP_OFFSET) -#define SW_API_COSMAP_DSCP_TO_DP_GET (7 + SW_API_COSMAP_OFFSET) -#define SW_API_COSMAP_UP_TO_PRI_SET (8 + SW_API_COSMAP_OFFSET) -#define SW_API_COSMAP_UP_TO_PRI_GET (9 + SW_API_COSMAP_OFFSET) -#define SW_API_COSMAP_UP_TO_DP_SET (10 + SW_API_COSMAP_OFFSET) -#define SW_API_COSMAP_UP_TO_DP_GET (11 + SW_API_COSMAP_OFFSET) -#define SW_API_COSMAP_PRI_TO_QU_SET (12 + SW_API_COSMAP_OFFSET) -#define SW_API_COSMAP_PRI_TO_QU_GET (13 + SW_API_COSMAP_OFFSET) -#define SW_API_COSMAP_PRI_TO_EHQU_SET (14 + SW_API_COSMAP_OFFSET) -#define SW_API_COSMAP_PRI_TO_EHQU_GET (15 + SW_API_COSMAP_OFFSET) -#define SW_API_COSMAP_EG_REMARK_SET (16 + SW_API_COSMAP_OFFSET) -#define SW_API_COSMAP_EG_REMARK_GET (17 + SW_API_COSMAP_OFFSET) -#define SW_API_COSMAP_DSCP_TO_EHPRI_SET (18 + SW_API_COSMAP_OFFSET) -#define SW_API_COSMAP_DSCP_TO_EHPRI_GET (19 + SW_API_COSMAP_OFFSET) -#define SW_API_COSMAP_DSCP_TO_EHDP_SET (20 + SW_API_COSMAP_OFFSET) -#define SW_API_COSMAP_DSCP_TO_EHDP_GET (21 + SW_API_COSMAP_OFFSET) -#define SW_API_COSMAP_UP_TO_EHPRI_SET (22 + SW_API_COSMAP_OFFSET) -#define SW_API_COSMAP_UP_TO_EHPRI_GET (23 + SW_API_COSMAP_OFFSET) -#define SW_API_COSMAP_UP_TO_EHDP_SET (24 + SW_API_COSMAP_OFFSET) -#define SW_API_COSMAP_UP_TO_EHDP_GET (25 + SW_API_COSMAP_OFFSET) - - /* sec */ -#define SW_API_SEC_OFFSET 1500 -#define SW_API_SEC_NORM_SET (0 + SW_API_SEC_OFFSET) -#define SW_API_SEC_NORM_GET (1 + SW_API_SEC_OFFSET) -#define SW_API_SEC_MAC_SET (2 + SW_API_SEC_OFFSET) -#define SW_API_SEC_MAC_GET (3 + SW_API_SEC_OFFSET) -#define SW_API_SEC_IP_SET (4 + SW_API_SEC_OFFSET) -#define SW_API_SEC_IP_GET (5 + SW_API_SEC_OFFSET) -#define SW_API_SEC_IP4_SET (6 + SW_API_SEC_OFFSET) -#define SW_API_SEC_IP4_GET (7 + SW_API_SEC_OFFSET) -#define SW_API_SEC_IP6_SET (8 + SW_API_SEC_OFFSET) -#define SW_API_SEC_IP6_GET (9 + SW_API_SEC_OFFSET) -#define SW_API_SEC_TCP_SET (10 + SW_API_SEC_OFFSET) -#define SW_API_SEC_TCP_GET (11 + SW_API_SEC_OFFSET) -#define SW_API_SEC_UDP_SET (12 + SW_API_SEC_OFFSET) -#define SW_API_SEC_UDP_GET (13 + SW_API_SEC_OFFSET) -#define SW_API_SEC_ICMP4_SET (14 + SW_API_SEC_OFFSET) -#define SW_API_SEC_ICMP4_GET (15 + SW_API_SEC_OFFSET) -#define SW_API_SEC_ICMP6_SET (16 + SW_API_SEC_OFFSET) -#define SW_API_SEC_ICMP6_GET (17 + SW_API_SEC_OFFSET) -#define SW_API_SEC_L3_PARSER_CTRL_GET (18 + SW_API_SEC_OFFSET) -#define SW_API_SEC_L3_PARSER_CTRL_SET (19 + SW_API_SEC_OFFSET) -#define SW_API_SEC_L4_PARSER_CTRL_GET (20 + SW_API_SEC_OFFSET) -#define SW_API_SEC_L4_PARSER_CTRL_SET (21 + SW_API_SEC_OFFSET) -#define SW_API_SEC_EXP_CTRL_GET (22 + SW_API_SEC_OFFSET) -#define SW_API_SEC_EXP_CTRL_SET (23 + SW_API_SEC_OFFSET) - - /* ip */ -#define SW_API_IP_OFFSET 1600 -#define SW_API_IP_HOST_ADD (0 + SW_API_IP_OFFSET) -#define SW_API_IP_HOST_DEL (1 + SW_API_IP_OFFSET) -#define SW_API_IP_HOST_GET (2 + SW_API_IP_OFFSET) -#define SW_API_IP_HOST_NEXT (3 + SW_API_IP_OFFSET) -#define SW_API_IP_HOST_COUNTER_BIND (4 + SW_API_IP_OFFSET) -#define SW_API_IP_HOST_PPPOE_BIND (5 + SW_API_IP_OFFSET) -#define SW_API_IP_PT_ARP_LEARN_SET (6 + SW_API_IP_OFFSET) -#define SW_API_IP_PT_ARP_LEARN_GET (7 + SW_API_IP_OFFSET) -#define SW_API_IP_ARP_LEARN_SET (8 + SW_API_IP_OFFSET) -#define SW_API_IP_ARP_LEARN_GET (9 + SW_API_IP_OFFSET) -#define SW_API_IP_SOURCE_GUARD_SET (10 + SW_API_IP_OFFSET) -#define SW_API_IP_SOURCE_GUARD_GET (11 + SW_API_IP_OFFSET) -#define SW_API_IP_ARP_GUARD_SET (12 + SW_API_IP_OFFSET) -#define SW_API_IP_ARP_GUARD_GET (13 + SW_API_IP_OFFSET) -#define SW_API_IP_ROUTE_STATUS_SET (14 + SW_API_IP_OFFSET) -#define SW_API_IP_ROUTE_STATUS_GET (15 + SW_API_IP_OFFSET) -#define SW_API_IP_INTF_ENTRY_ADD (16 + SW_API_IP_OFFSET) -#define SW_API_IP_INTF_ENTRY_DEL (17 + SW_API_IP_OFFSET) -#define SW_API_IP_INTF_ENTRY_NEXT (18 + SW_API_IP_OFFSET) -#define SW_API_IP_UNK_SOURCE_CMD_SET (19 + SW_API_IP_OFFSET) -#define SW_API_IP_UNK_SOURCE_CMD_GET (20 + SW_API_IP_OFFSET) -#define SW_API_ARP_UNK_SOURCE_CMD_SET (21 + SW_API_IP_OFFSET) -#define SW_API_ARP_UNK_SOURCE_CMD_GET (22 + SW_API_IP_OFFSET) -#define SW_API_IP_AGE_TIME_SET (23 + SW_API_IP_OFFSET) -#define SW_API_IP_AGE_TIME_GET (24 + SW_API_IP_OFFSET) -#define SW_API_WCMP_HASH_MODE_SET (25 + SW_API_IP_OFFSET) -#define SW_API_WCMP_HASH_MODE_GET (26 + SW_API_IP_OFFSET) -#define SW_API_IP_VRF_BASE_ADDR_SET (27 + SW_API_IP_OFFSET) -#define SW_API_IP_VRF_BASE_ADDR_GET (28 + SW_API_IP_OFFSET) -#define SW_API_IP_VRF_BASE_MASK_SET (29 + SW_API_IP_OFFSET) -#define SW_API_IP_VRF_BASE_MASK_GET (30 + SW_API_IP_OFFSET) -#define SW_API_IP_DEFAULT_ROUTE_SET (31 + SW_API_IP_OFFSET) -#define SW_API_IP_DEFAULT_ROUTE_GET (32 + SW_API_IP_OFFSET) -#define SW_API_IP_HOST_ROUTE_SET (33 + SW_API_IP_OFFSET) -#define SW_API_IP_HOST_ROUTE_GET (34 + SW_API_IP_OFFSET) -#define SW_API_IP_WCMP_ENTRY_SET (35 + SW_API_IP_OFFSET) -#define SW_API_IP_WCMP_ENTRY_GET (36 + SW_API_IP_OFFSET) -#define SW_API_IP_RFS_IP4_SET (37 + SW_API_IP_OFFSET) -#define SW_API_IP_RFS_IP6_SET (38 + SW_API_IP_OFFSET) -#define SW_API_IP_RFS_IP4_DEL (39 + SW_API_IP_OFFSET) -#define SW_API_IP_RFS_IP6_DEL (40 + SW_API_IP_OFFSET) -#define SW_API_IP_DEFAULT_FLOW_CMD_SET (41 + SW_API_IP_OFFSET) -#define SW_API_IP_DEFAULT_FLOW_CMD_GET (42 + SW_API_IP_OFFSET) -#define SW_API_IP_DEFAULT_RT_FLOW_CMD_SET (43 + SW_API_IP_OFFSET) -#define SW_API_IP_DEFAULT_RT_FLOW_CMD_GET (44 + SW_API_IP_OFFSET) -#define SW_API_IP_VIS_ARP_SG_CFG_GET (45 + SW_API_IP_OFFSET) -#define SW_API_IP_VIS_ARP_SG_CFG_SET (46 + SW_API_IP_OFFSET) -#define SW_API_IP_NETWORK_ROUTE_GET (47 + SW_API_IP_OFFSET) -#define SW_API_IP_NETWORK_ROUTE_ADD (48 + SW_API_IP_OFFSET) -#define SW_API_IP_INTF_GET (49 + SW_API_IP_OFFSET) -#define SW_API_IP_INTF_SET (50 + SW_API_IP_OFFSET) -#define SW_API_IP_VSI_INTF_GET (51 + SW_API_IP_OFFSET) -#define SW_API_IP_VSI_INTF_SET (52 + SW_API_IP_OFFSET) -#define SW_API_IP_NEXTHOP_GET (53 + SW_API_IP_OFFSET) -#define SW_API_IP_NEXTHOP_SET (54 + SW_API_IP_OFFSET) -#define SW_API_IP_VSI_SG_SET (55 + SW_API_IP_OFFSET) -#define SW_API_IP_VSI_SG_GET (56 + SW_API_IP_OFFSET) -#define SW_API_IP_PORT_SG_SET (57 + SW_API_IP_OFFSET) -#define SW_API_IP_PORT_SG_GET (58 + SW_API_IP_OFFSET) -#define SW_API_IP_PUB_IP_SET (59 + SW_API_IP_OFFSET) -#define SW_API_IP_PUB_IP_GET (60 + SW_API_IP_OFFSET) -#define SW_API_IP_NETWORK_ROUTE_DEL (61 + SW_API_IP_OFFSET) -#define SW_API_IP_PORT_INTF_GET (62 + SW_API_IP_OFFSET) -#define SW_API_IP_PORT_INTF_SET (63 + SW_API_IP_OFFSET) -#define SW_API_IP_PORT_MAC_GET (64 + SW_API_IP_OFFSET) -#define SW_API_IP_PORT_MAC_SET (65 + SW_API_IP_OFFSET) -#define SW_API_IP_ROUTE_MISS_GET (66 + SW_API_IP_OFFSET) -#define SW_API_IP_ROUTE_MISS_SET (67 + SW_API_IP_OFFSET) -#define SW_API_IP_PORT_ARP_SG_GET (68 + SW_API_IP_OFFSET) -#define SW_API_IP_PORT_ARP_SG_SET (69 + SW_API_IP_OFFSET) -#define SW_API_IP_VSI_MC_MODE_GET (70 + SW_API_IP_OFFSET) -#define SW_API_IP_VSI_MC_MODE_SET (71 + SW_API_IP_OFFSET) -#define SW_API_GLOBAL_CTRL_GET (72 + SW_API_IP_OFFSET) -#define SW_API_GLOBAL_CTRL_SET (73 + SW_API_IP_OFFSET) - - /* nat */ -#define SW_API_NAT_OFFSET 1700 -#define SW_API_NAT_ADD (0 + SW_API_NAT_OFFSET) -#define SW_API_NAT_DEL (1 + SW_API_NAT_OFFSET) -#define SW_API_NAT_GET (2 + SW_API_NAT_OFFSET) -#define SW_API_NAT_NEXT (3 + SW_API_NAT_OFFSET) -#define SW_API_NAT_COUNTER_BIND (4 + SW_API_NAT_OFFSET) -#define SW_API_NAPT_ADD (5 + SW_API_NAT_OFFSET) -#define SW_API_NAPT_DEL (6 + SW_API_NAT_OFFSET) -#define SW_API_NAPT_GET (7 + SW_API_NAT_OFFSET) -#define SW_API_NAPT_NEXT (8 + SW_API_NAT_OFFSET) -#define SW_API_NAPT_COUNTER_BIND (9 + SW_API_NAT_OFFSET) -#define SW_API_NAT_STATUS_SET (10 + SW_API_NAT_OFFSET) -#define SW_API_NAT_STATUS_GET (11 + SW_API_NAT_OFFSET) -#define SW_API_NAT_HASH_MODE_SET (12 + SW_API_NAT_OFFSET) -#define SW_API_NAT_HASH_MODE_GET (13 + SW_API_NAT_OFFSET) -#define SW_API_NAPT_STATUS_SET (14 + SW_API_NAT_OFFSET) -#define SW_API_NAPT_STATUS_GET (15 + SW_API_NAT_OFFSET) -#define SW_API_NAPT_MODE_SET (16 + SW_API_NAT_OFFSET) -#define SW_API_NAPT_MODE_GET (17 + SW_API_NAT_OFFSET) -#define SW_API_PRV_BASE_ADDR_SET (18 + SW_API_NAT_OFFSET) -#define SW_API_PRV_BASE_ADDR_GET (19 + SW_API_NAT_OFFSET) -#define SW_API_PRV_ADDR_MODE_SET (20 + SW_API_NAT_OFFSET) -#define SW_API_PRV_ADDR_MODE_GET (21 + SW_API_NAT_OFFSET) -#define SW_API_PUB_ADDR_ENTRY_ADD (22 + SW_API_NAT_OFFSET) -#define SW_API_PUB_ADDR_ENTRY_DEL (23 + SW_API_NAT_OFFSET) -#define SW_API_PUB_ADDR_ENTRY_NEXT (24 + SW_API_NAT_OFFSET) -#define SW_API_NAT_UNK_SESSION_CMD_SET (25 + SW_API_NAT_OFFSET) -#define SW_API_NAT_UNK_SESSION_CMD_GET (26 + SW_API_NAT_OFFSET) -#define SW_API_PRV_BASE_MASK_SET (27 + SW_API_NAT_OFFSET) -#define SW_API_PRV_BASE_MASK_GET (28 + SW_API_NAT_OFFSET) -#define SW_API_NAT_GLOBAL_SET (29 + SW_API_NAT_OFFSET) -#define SW_API_FLOW_ADD (30 + SW_API_NAT_OFFSET) -#define SW_API_FLOW_DEL (31 + SW_API_NAT_OFFSET) -#define SW_API_FLOW_GET (32 + SW_API_NAT_OFFSET) -#define SW_API_FLOW_NEXT (33 + SW_API_NAT_OFFSET) -#define SW_API_FLOW_COUNTER_BIND (34 + SW_API_NAT_OFFSET) -#define SW_API_FLOW_COOKIE_SET (35 + SW_API_NAT_OFFSET) -#define SW_API_FLOW_RFS_SET (36 + SW_API_NAT_OFFSET) - - - /* trunk */ -#define SW_API_TRUNK_OFFSET 1800 -#define SW_API_TRUNK_GROUP_SET (0 + SW_API_TRUNK_OFFSET) -#define SW_API_TRUNK_GROUP_GET (1 + SW_API_TRUNK_OFFSET) -#define SW_API_TRUNK_HASH_SET (2 + SW_API_TRUNK_OFFSET) -#define SW_API_TRUNK_HASH_GET (3 + SW_API_TRUNK_OFFSET) -#define SW_API_TRUNK_MAN_SA_SET (4 + SW_API_TRUNK_OFFSET) -#define SW_API_TRUNK_MAN_SA_GET (5 + SW_API_TRUNK_OFFSET) -#define SW_API_TRUNK_FAILOVER_EN_SET (6 + SW_API_TRUNK_OFFSET) -#define SW_API_TRUNK_FAILOVER_EN_GET (7 + SW_API_TRUNK_OFFSET) - - /* Interface Control */ -#define SW_API_INTERFACE_OFFSET 1900 -#define SW_API_MAC_MODE_SET (0 + SW_API_INTERFACE_OFFSET) -#define SW_API_MAC_MODE_GET (1 + SW_API_INTERFACE_OFFSET) -#define SW_API_PORT_3AZ_STATUS_SET (2 + SW_API_INTERFACE_OFFSET) -#define SW_API_PORT_3AZ_STATUS_GET (3 + SW_API_INTERFACE_OFFSET) -#define SW_API_PHY_MODE_SET (4 + SW_API_INTERFACE_OFFSET) -#define SW_API_PHY_MODE_GET (5 + SW_API_INTERFACE_OFFSET) -#define SW_API_FX100_CTRL_SET (6 + SW_API_INTERFACE_OFFSET) -#define SW_API_FX100_CTRL_GET (7 + SW_API_INTERFACE_OFFSET) -#define SW_API_FX100_STATUS_GET (8 + SW_API_INTERFACE_OFFSET) -#define SW_API_MAC06_EXCH_SET (9 + SW_API_INTERFACE_OFFSET) -#define SW_API_MAC06_EXCH_GET (10 + SW_API_INTERFACE_OFFSET) - - /* VSI */ -#define SW_API_VSI_OFFSET 2000 -#define SW_API_VSI_ALLOC (0 + SW_API_VSI_OFFSET) -#define SW_API_VSI_FREE (1 + SW_API_VSI_OFFSET) -#define SW_API_PORT_VSI_SET (2 + SW_API_VSI_OFFSET) -#define SW_API_PORT_VSI_GET (3 + SW_API_VSI_OFFSET) -#define SW_API_PORT_VLAN_VSI_SET (4 + SW_API_VSI_OFFSET) -#define SW_API_PORT_VLAN_VSI_GET (5 + SW_API_VSI_OFFSET) -#define SW_API_VSI_TBL_DUMP (6 + SW_API_VSI_OFFSET) -#define SW_API_VSI_NEWADDR_LRN_SET (7 + SW_API_VSI_OFFSET) -#define SW_API_VSI_NEWADDR_LRN_GET (8 + SW_API_VSI_OFFSET) -#define SW_API_VSI_STAMOVE_SET (9 + SW_API_VSI_OFFSET) -#define SW_API_VSI_STAMOVE_GET (10 + SW_API_VSI_OFFSET) -#define SW_API_VSI_MEMBER_SET (11 + SW_API_VSI_OFFSET) -#define SW_API_VSI_MEMBER_GET (12 + SW_API_VSI_OFFSET) -#define SW_API_VSI_COUNTER_GET (13 + SW_API_VSI_OFFSET) -#define SW_API_VSI_COUNTER_CLEANUP (14 + SW_API_VSI_OFFSET) - - /* qm */ -#define SW_API_QM_OFFSET 2100 -#define SW_API_UCAST_QUEUE_BASE_PROFILE_SET (0 + SW_API_QM_OFFSET) -#define SW_API_UCAST_QUEUE_BASE_PROFILE_GET (1 + SW_API_QM_OFFSET) -#define SW_API_UCAST_PRIORITY_CLASS_SET (2 + SW_API_QM_OFFSET) -#define SW_API_UCAST_PRIORITY_CLASS_GET (3 + SW_API_QM_OFFSET) -#define SW_API_MCAST_PRIORITY_CLASS_SET (4 + SW_API_QM_OFFSET) -#define SW_API_MCAST_PRIORITY_CLASS_GET (5 + SW_API_QM_OFFSET) -#define SW_API_UCAST_HASH_MAP_SET (6 + SW_API_QM_OFFSET) -#define SW_API_UCAST_HASH_MAP_GET (7 + SW_API_QM_OFFSET) -#define SW_API_UCAST_DFLT_HASH_MAP_SET (8 + SW_API_QM_OFFSET) -#define SW_API_UCAST_DFLT_HASH_MAP_GET (9 + SW_API_QM_OFFSET) -#define SW_API_MCAST_CPUCODE_CLASS_SET (10 + SW_API_QM_OFFSET) -#define SW_API_MCAST_CPUCODE_CLASS_GET (11 + SW_API_QM_OFFSET) -#define SW_API_QUEUE_FLUSH (12 + SW_API_QM_OFFSET) -#define SW_API_AC_CTRL_SET (13 + SW_API_QM_OFFSET) -#define SW_API_AC_CTRL_GET (14 + SW_API_QM_OFFSET) -#define SW_API_AC_PRE_BUFFER_SET (15 + SW_API_QM_OFFSET) -#define SW_API_AC_PRE_BUFFER_GET (16 + SW_API_QM_OFFSET) -#define SW_API_QUEUE_GROUP_SET (17 + SW_API_QM_OFFSET) -#define SW_API_QUEUE_GROUP_GET (18 + SW_API_QM_OFFSET) -#define SW_API_STATIC_THRESH_SET (19 + SW_API_QM_OFFSET) -#define SW_API_STATIC_THRESH_GET (20 + SW_API_QM_OFFSET) -#define SW_API_DYNAMIC_THRESH_SET (21 + SW_API_QM_OFFSET) -#define SW_API_DYNAMIC_THRESH_GET (22 + SW_API_QM_OFFSET) -#define SW_API_GOURP_BUFFER_SET (23 + SW_API_QM_OFFSET) -#define SW_API_GOURP_BUFFER_GET (24 + SW_API_QM_OFFSET) -#define SW_API_QUEUE_CNT_CTRL_GET (25 + SW_API_QM_OFFSET) -#define SW_API_QUEUE_CNT_CTRL_SET (26 + SW_API_QM_OFFSET) -#define SW_API_QUEUE_CNT_GET (27 + SW_API_QM_OFFSET) -#define SW_API_QUEUE_CNT_CLEANUP (28 + SW_API_QM_OFFSET) -#define SW_API_QM_ENQUEUE_CTRL_SET (29 + SW_API_QM_OFFSET) -#define SW_API_QM_ENQUEUE_CTRL_GET (30 + SW_API_QM_OFFSET) -#define SW_API_QM_SOURCE_PROFILE_SET (31 + SW_API_QM_OFFSET) -#define SW_API_QM_SOURCE_PROFILE_GET (32 + SW_API_QM_OFFSET) - -/* flow */ -#define SW_API_FLOW_OFFSET 2200 -#define SW_API_FLOW_STATUS_SET (0 + SW_API_FLOW_OFFSET) -#define SW_API_FLOW_STATUS_GET (1 + SW_API_FLOW_OFFSET) -#define SW_API_FLOW_AGE_TIMER_SET (2 + SW_API_FLOW_OFFSET) -#define SW_API_FLOW_AGE_TIMER_GET (3 + SW_API_FLOW_OFFSET) -#define SW_API_FLOW_CTRL_SET (4 + SW_API_FLOW_OFFSET) -#define SW_API_FLOW_CTRL_GET (5 + SW_API_FLOW_OFFSET) -#define SW_API_FLOW_ENTRY_ADD (6 + SW_API_FLOW_OFFSET) -#define SW_API_FLOW_ENTRY_DEL (7 + SW_API_FLOW_OFFSET) -#define SW_API_FLOW_ENTRY_GET (8 + SW_API_FLOW_OFFSET) -#define SW_API_FLOW_GLOBAL_CFG_GET (9 + SW_API_FLOW_OFFSET) -#define SW_API_FLOW_GLOBAL_CFG_SET (10 + SW_API_FLOW_OFFSET) -#define SW_API_FLOWENTRY_NEXT (11 + SW_API_FLOW_OFFSET) - -#define SW_API_FLOW_HOST_ADD (20 + SW_API_FLOW_OFFSET) -#define SW_API_FLOW_HOST_DEL (21 + SW_API_FLOW_OFFSET) -#define SW_API_FLOW_HOST_GET (22 + SW_API_FLOW_OFFSET) - -/* rss hash */ -#define SW_API_RSS_HASH_OFFSET 2400 -#define SW_API_RSS_HASH_CONFIG_SET (0 + SW_API_RSS_HASH_OFFSET) -#define SW_API_RSS_HASH_CONFIG_GET (1 + SW_API_RSS_HASH_OFFSET) - - /* Ctrlpkt Control */ -#define SW_API_CTRLPKT_OFFSET 2500 -#define SW_API_MGMTCTRL_ETHTYPE_PROFILE_SET (0 + SW_API_CTRLPKT_OFFSET) -#define SW_API_MGMTCTRL_ETHTYPE_PROFILE_GET (1 + SW_API_CTRLPKT_OFFSET) -#define SW_API_MGMTCTRL_RFDB_PROFILE_SET (2 + SW_API_CTRLPKT_OFFSET) -#define SW_API_MGMTCTRL_RFDB_PROFILE_GET (3 + SW_API_CTRLPKT_OFFSET) -#define SW_API_MGMTCTRL_CTRLPKT_PROFILE_ADD (4 + SW_API_CTRLPKT_OFFSET) -#define SW_API_MGMTCTRL_CTRLPKT_PROFILE_DEL (5 + SW_API_CTRLPKT_OFFSET) -#define SW_API_MGMTCTRL_CTRLPKT_PROFILE_GETFIRST (6 + SW_API_CTRLPKT_OFFSET) -#define SW_API_MGMTCTRL_CTRLPKT_PROFILE_GETNEXT (7 + SW_API_CTRLPKT_OFFSET) - - /* Service Code */ -#define SW_API_SERVCODE_OFFSET 2600 -#define SW_API_SERVCODE_CONFIG_SET (0 + SW_API_SERVCODE_OFFSET) -#define SW_API_SERVCODE_CONFIG_GET (1 + SW_API_SERVCODE_OFFSET) -#define SW_API_SERVCODE_LOOPCHECK_EN (2 + SW_API_SERVCODE_OFFSET) -#define SW_API_SERVCODE_LOOPCHECK_STATUS_GET (3 + SW_API_SERVCODE_OFFSET) - - /* POLICER */ -#define SW_API_POLICER_OFFSET 2800 -#define SW_API_POLICER_TIMESLOT_SET (0 + SW_API_POLICER_OFFSET) -#define SW_API_POLICER_TIMESLOT_GET (1 + SW_API_POLICER_OFFSET) -#define SW_API_POLICER_PORT_COUNTER_GET (2 + SW_API_POLICER_OFFSET) -#define SW_API_POLICER_ACL_COUNTER_GET (3 + SW_API_POLICER_OFFSET) -#define SW_API_POLICER_COMPENSATION_SET (4 + SW_API_POLICER_OFFSET) -#define SW_API_POLICER_COMPENSATION_GET (5 + SW_API_POLICER_OFFSET) -#define SW_API_POLICER_PORT_ENTRY_SET (6 + SW_API_POLICER_OFFSET) -#define SW_API_POLICER_PORT_ENTRY_GET (7 + SW_API_POLICER_OFFSET) -#define SW_API_POLICER_ACL_ENTRY_SET (8 + SW_API_POLICER_OFFSET) -#define SW_API_POLICER_ACL_ENTRY_GET (9 + SW_API_POLICER_OFFSET) -#define SW_API_POLICER_GLOBAL_COUNTER_GET (10 + SW_API_POLICER_OFFSET) -#define SW_API_POLICER_BYPASS_EN_SET (11 + SW_API_POLICER_OFFSET) -#define SW_API_POLICER_BYPASS_EN_GET (12 + SW_API_POLICER_OFFSET) - - -/* SHAPER */ -#define SW_API_SHAPER_OFFSET 2900 -#define SW_API_PORT_SHAPER_TIMESLOT_SET (0 + SW_API_SHAPER_OFFSET) -#define SW_API_PORT_SHAPER_TIMESLOT_GET (1 + SW_API_SHAPER_OFFSET) -#define SW_API_FLOW_SHAPER_TIMESLOT_SET (2 + SW_API_SHAPER_OFFSET) -#define SW_API_FLOW_SHAPER_TIMESLOT_GET (3 + SW_API_SHAPER_OFFSET) -#define SW_API_QUEUE_SHAPER_TIMESLOT_SET (4 + SW_API_SHAPER_OFFSET) -#define SW_API_QUEUE_SHAPER_TIMESLOT_GET (5 + SW_API_SHAPER_OFFSET) -#define SW_API_PORT_SHAPER_TOKEN_NUMBER_SET (6 + SW_API_SHAPER_OFFSET) -#define SW_API_PORT_SHAPER_TOKEN_NUMBER_GET (7 + SW_API_SHAPER_OFFSET) -#define SW_API_FLOW_SHAPER_TOKEN_NUMBER_SET (8 + SW_API_SHAPER_OFFSET) -#define SW_API_FLOW_SHAPER_TOKEN_NUMBER_GET (9 + SW_API_SHAPER_OFFSET) -#define SW_API_QUEUE_SHAPER_TOKEN_NUMBER_SET (10 + SW_API_SHAPER_OFFSET) -#define SW_API_QUEUE_SHAPER_TOKEN_NUMBER_GET (11 + SW_API_SHAPER_OFFSET) -#define SW_API_PORT_SHAPER_SET (12 + SW_API_SHAPER_OFFSET) -#define SW_API_PORT_SHAPER_GET (13 + SW_API_SHAPER_OFFSET) -#define SW_API_FLOW_SHAPER_SET (14 + SW_API_SHAPER_OFFSET) -#define SW_API_FLOW_SHAPER_GET (15 + SW_API_SHAPER_OFFSET) -#define SW_API_QUEUE_SHAPER_SET (16 + SW_API_SHAPER_OFFSET) -#define SW_API_QUEUE_SHAPER_GET (17 + SW_API_SHAPER_OFFSET) -#define SW_API_SHAPER_IPG_PRE_SET (18 + SW_API_SHAPER_OFFSET) -#define SW_API_SHAPER_IPG_PRE_GET (19 + SW_API_SHAPER_OFFSET) - -/* bm */ -#define SW_API_BM_OFFSET 3000 -#define SW_API_BM_CTRL_SET (0 + SW_API_BM_OFFSET) -#define SW_API_BM_CTRL_GET (1 + SW_API_BM_OFFSET) -#define SW_API_BM_PORTGROUP_MAP_SET (2 + SW_API_BM_OFFSET) -#define SW_API_BM_PORTGROUP_MAP_GET (3 + SW_API_BM_OFFSET) -#define SW_API_BM_GROUP_BUFFER_SET (4 + SW_API_BM_OFFSET) -#define SW_API_BM_GROUP_BUFFER_GET (5 + SW_API_BM_OFFSET) -#define SW_API_BM_PORT_RSVBUFFER_SET (6 + SW_API_BM_OFFSET) -#define SW_API_BM_PORT_RSVBUFFER_GET (7 + SW_API_BM_OFFSET) -#define SW_API_BM_STATIC_THRESH_SET (8 + SW_API_BM_OFFSET) -#define SW_API_BM_STATIC_THRESH_GET (9 + SW_API_BM_OFFSET) -#define SW_API_BM_DYNAMIC_THRESH_SET (10 + SW_API_BM_OFFSET) -#define SW_API_BM_DYNAMIC_THRESH_GET (11 + SW_API_BM_OFFSET) -#define SW_API_BM_PORT_COUNTER_GET (12 + SW_API_BM_OFFSET) - -/* ptp */ -#define SW_API_PTP_OFFSET 3100 -#define SW_API_PTP_CONFIG_SET (0 + SW_API_PTP_OFFSET) -#define SW_API_PTP_CONFIG_GET (1 + SW_API_PTP_OFFSET) -#define SW_API_PTP_REFERENCE_CLOCK_SET (2 + SW_API_PTP_OFFSET) -#define SW_API_PTP_REFERENCE_CLOCK_GET (3 + SW_API_PTP_OFFSET) -#define SW_API_PTP_RX_TIMESTAMP_MODE_SET (4 + SW_API_PTP_OFFSET) -#define SW_API_PTP_RX_TIMESTAMP_MODE_GET (5 + SW_API_PTP_OFFSET) -#define SW_API_PTP_TIMESTAMP_GET (6 + SW_API_PTP_OFFSET) -#define SW_API_PTP_PKT_TIMESTAMP_SET (7 + SW_API_PTP_OFFSET) -#define SW_API_PTP_PKT_TIMESTAMP_GET (8 + SW_API_PTP_OFFSET) -#define SW_API_PTP_GRANDMASTER_MODE_SET (9 + SW_API_PTP_OFFSET) -#define SW_API_PTP_GRANDMASTER_MODE_GET (10 + SW_API_PTP_OFFSET) -#define SW_API_PTP_RTC_TIME_SET (11 + SW_API_PTP_OFFSET) -#define SW_API_PTP_RTC_TIME_GET (12 + SW_API_PTP_OFFSET) -#define SW_API_PTP_RTC_TIME_CLEAR (13 + SW_API_PTP_OFFSET) -#define SW_API_PTP_RTC_ADJTIME_SET (14 + SW_API_PTP_OFFSET) -#define SW_API_PTP_RTC_ADJFREQ_SET (15 + SW_API_PTP_OFFSET) -#define SW_API_PTP_RTC_ADJFREQ_GET (16 + SW_API_PTP_OFFSET) -#define SW_API_PTP_LINK_DELAY_SET (17 + SW_API_PTP_OFFSET) -#define SW_API_PTP_LINK_DELAY_GET (18 + SW_API_PTP_OFFSET) -#define SW_API_PTP_SECURITY_SET (19 + SW_API_PTP_OFFSET) -#define SW_API_PTP_SECURITY_GET (20 + SW_API_PTP_OFFSET) -#define SW_API_PTP_PPS_SIGNAL_CONTROL_SET (21 + SW_API_PTP_OFFSET) -#define SW_API_PTP_PPS_SIGNAL_CONTROL_GET (22 + SW_API_PTP_OFFSET) -#define SW_API_PTP_RX_CRC_RECALC_SET (23 + SW_API_PTP_OFFSET) -#define SW_API_PTP_RX_CRC_RECALC_GET (24 + SW_API_PTP_OFFSET) -#define SW_API_PTP_ASYM_CORRECTION_SET (25 + SW_API_PTP_OFFSET) -#define SW_API_PTP_ASYM_CORRECTION_GET (26 + SW_API_PTP_OFFSET) -#define SW_API_PTP_OUTPUT_WAVEFORM_SET (27 + SW_API_PTP_OFFSET) -#define SW_API_PTP_OUTPUT_WAVEFORM_GET (28 + SW_API_PTP_OFFSET) -#define SW_API_PTP_RTC_TIME_SNAPSHOT_SET (29 + SW_API_PTP_OFFSET) -#define SW_API_PTP_RTC_TIME_SNAPSHOT_GET (30 + SW_API_PTP_OFFSET) -#define SW_API_PTP_INCREMENT_SYNC_FROM_CLOCK_SET (31 + SW_API_PTP_OFFSET) -#define SW_API_PTP_INCREMENT_SYNC_FROM_CLOCK_GET (32 + SW_API_PTP_OFFSET) -#define SW_API_PTP_TOD_UART_SET (33 + SW_API_PTP_OFFSET) -#define SW_API_PTP_TOD_UART_GET (34 + SW_API_PTP_OFFSET) -#define SW_API_PTP_ENHANCED_TIMESTAMP_ENGINE_SET (35 + SW_API_PTP_OFFSET) -#define SW_API_PTP_ENHANCED_TIMESTAMP_ENGINE_GET (36 + SW_API_PTP_OFFSET) -#define SW_API_PTP_TRIGGER_SET (37 + SW_API_PTP_OFFSET) -#define SW_API_PTP_TRIGGER_GET (38 + SW_API_PTP_OFFSET) -#define SW_API_PTP_CAPTURE_SET (39 + SW_API_PTP_OFFSET) -#define SW_API_PTP_CAPTURE_GET (40 + SW_API_PTP_OFFSET) -#define SW_API_PTP_INTERRUPT_SET (41 + SW_API_PTP_OFFSET) -#define SW_API_PTP_INTERRUPT_GET (42 + SW_API_PTP_OFFSET) - -/* sfp */ -#define SW_API_SFP_OFFSET 3200 -#define SW_API_SFP_DATA_GET (0 + SW_API_SFP_OFFSET) -#define SW_API_SFP_DATA_SET (1 + SW_API_SFP_OFFSET) -#define SW_API_SFP_DEV_TYPE_GET (2 + SW_API_SFP_OFFSET) -#define SW_API_SFP_TRANSC_CODE_GET (3 + SW_API_SFP_OFFSET) -#define SW_API_SFP_RATE_ENCODE_GET (4 + SW_API_SFP_OFFSET) -#define SW_API_SFP_LINK_LENGTH_GET (5 + SW_API_SFP_OFFSET) -#define SW_API_SFP_VENDOR_INFO_GET (6 + SW_API_SFP_OFFSET) -#define SW_API_SFP_LASER_WAVELENGTH_GET (7 + SW_API_SFP_OFFSET) -#define SW_API_SFP_OPTION_GET (8 + SW_API_SFP_OFFSET) -#define SW_API_SFP_CTRL_RATE_GET (9 + SW_API_SFP_OFFSET) -#define SW_API_SFP_ENHANCED_CFG_GET (10 + SW_API_SFP_OFFSET) -#define SW_API_SFP_DIAG_THRESHOLD_GET (11 + SW_API_SFP_OFFSET) -#define SW_API_SFP_DIAG_CAL_CONST_GET (12 + SW_API_SFP_OFFSET) -#define SW_API_SFP_DIAG_REALTIME_GET (13 + SW_API_SFP_OFFSET) -#define SW_API_SFP_DIAG_CTRL_STATUS_GET (14 + SW_API_SFP_OFFSET) -#define SW_API_SFP_DIAG_ALARM_WARN_FLAG_GET (15 + SW_API_SFP_OFFSET) -#define SW_API_SFP_CHECKCODE_GET (16 + SW_API_SFP_OFFSET) - -/*qca808x_start*/ - /*debug*/ -#define SW_API_DEBUG_OFFSET 10000 -#define SW_API_PHY_GET (0 + SW_API_DEBUG_OFFSET) -#define SW_API_PHY_SET (1 + SW_API_DEBUG_OFFSET) -/*qca808x_end*/ -#define SW_API_REG_GET (2 + SW_API_DEBUG_OFFSET) -#define SW_API_REG_SET (3 + SW_API_DEBUG_OFFSET) -#define SW_API_REG_ENTRY_GET (4 + SW_API_DEBUG_OFFSET) -#define SW_API_REG_ENTRY_SET (5 + SW_API_DEBUG_OFFSET) -#define SW_API_REG_FIELD_GET (6 + SW_API_DEBUG_OFFSET) -#define SW_API_REG_FIELD_SET (7 + SW_API_DEBUG_OFFSET) -#define SW_API_PSGMII_REG_GET (8 + SW_API_DEBUG_OFFSET) -#define SW_API_PSGMII_REG_SET (9 + SW_API_DEBUG_OFFSET) -#define SW_API_REG_DUMP (10 + SW_API_DEBUG_OFFSET) -#define SW_API_DBG_REG_DUMP (11 + SW_API_DEBUG_OFFSET) -#define SW_API_DBG_PSGMII_SELF_TEST (12 + SW_API_DEBUG_OFFSET) -#define SW_API_PHY_DUMP (13 + SW_API_DEBUG_OFFSET) -#define SW_API_UNIPHY_REG_GET (20 + SW_API_DEBUG_OFFSET) -#define SW_API_UNIPHY_REG_SET (21 + SW_API_DEBUG_OFFSET) -/*qca808x_start*/ -#define SW_API_PHY_I2C_GET (22 + SW_API_DEBUG_OFFSET) -#define SW_API_PHY_I2C_SET (23 + SW_API_DEBUG_OFFSET) - -#define SW_API_MAX 0xffff - -#ifdef __cplusplus -} -#endif /* __cplusplus */ -#endif /* _SW_IOCTL_H_ */ -/*qca808x_end*/ diff --git a/feeds/ipq807x/qca-ssdk/src/include/common/aos_head.h b/feeds/ipq807x/qca-ssdk/src/include/common/aos_head.h deleted file mode 100755 index b4962118b..000000000 --- a/feeds/ipq807x/qca-ssdk/src/include/common/aos_head.h +++ /dev/null @@ -1,19 +0,0 @@ -/* - * Copyright (c) 2012,2018, The Linux Foundation. All rights reserved. - * Permission to use, copy, modify, and/or distribute this software for - * any purpose with or without fee is hereby granted, provided that the - * above copyright notice and this permission notice appear in all copies. - * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES - * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR - * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES - * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN - * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT - * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. - */ - -#include "aos_mem.h" -#include "aos_timer.h" -#include "aos_lock.h" -#include "aos_types.h" - diff --git a/feeds/ipq807x/qca-ssdk/src/include/common/shared_func.h b/feeds/ipq807x/qca-ssdk/src/include/common/shared_func.h deleted file mode 100755 index 729938c32..000000000 --- a/feeds/ipq807x/qca-ssdk/src/include/common/shared_func.h +++ /dev/null @@ -1,120 +0,0 @@ -/* - * Copyright (c) 2012, The Linux Foundation. All rights reserved. - * Permission to use, copy, modify, and/or distribute this software for - * any purpose with or without fee is hereby granted, provided that the - * above copyright notice and this permission notice appear in all copies. - * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES - * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR - * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES - * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN - * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT - * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. - */ - - - -#ifndef _SHARED_FUNC_H -#define _SHARED_FUNC_H - -#ifdef __cplusplus -extern "C" { -#endif /* __cplusplus */ - -#define SW_RTN_ON_ERROR(rtn) \ - do { if (rtn != SW_OK) return(rtn); } while(0); - -#define SW_OUT_ON_ERROR(rtn) \ - do { \ - if (rtn != SW_OK) { \ - rv = rtn; \ - goto out;\ - } \ - } while(0); - -#define SW_CNTU_ON_ERROR_AND_COND1_OR_GOTO_OUT(rtn, cond1) \ - { \ - if ((rtn != SW_OK)) { \ - if (rtn == cond1) \ - continue; \ - else \ - goto out; \ - } \ - } - -#define SW_RTN_ON_ERROR_EXCEPT_COND1(rtn, cond1) \ - do { \ - if ((rtn != SW_OK) && (rtn != cond1)) \ - return rtn; \ - }while(0); - -#define SW_RTN_ON_NULL(op) \ - do { \ - if ((op) == NULL) \ - return SW_NOT_INITIALIZED;\ - }while(0); - - /* register functions */ -#define SW_BIT_MASK_U32(nr) (~(0xFFFFFFFF << (nr))) - -#define SW_FIELD_MASK_U32(offset, len) \ - ((SW_BIT_MASK_U32(len) << (offset))) - -#define SW_FIELD_MASK_NOT_U32(offset,len) \ - (~(SW_BIT_MASK_U32(len) << (offset))) - -#define SW_FIELD_2_REG(field_val, bit_offset) \ - (field_val << (bit_offset) ) - -#define SW_REG_2_FIELD(reg_val, bit_offset, field_len) \ - (((reg_val) >> (bit_offset)) & ((1 << (field_len)) - 1)) - -#define SW_REG_SET_BY_FIELD_U32(reg_value, field_value, bit_offset, field_len)\ - do { \ - (reg_value) = \ - (((reg_value) & SW_FIELD_MASK_NOT_U32((bit_offset),(field_len))) \ - | (((field_value) & SW_BIT_MASK_U32(field_len)) << (bit_offset)));\ - } while (0) - -#define SW_FIELD_GET_BY_REG_U32(reg_value, field_value, bit_offset, field_len)\ - do { \ - (field_value) = \ - (((reg_value) >> (bit_offset)) & SW_BIT_MASK_U32(field_len)); \ - } while (0) - -#define SW_SWAP_BITS_U8(x) \ - ((((x)&0x80)>>7) | (((x)&0x40)>>5) | (((x)&0x20)>>3) | (((x)&0x10)>>1) \ - |(((x)&0x1)<<7) | (((x)&0x2)<<5) | (((x)&0x4)<<3) |(((x)&0x8)<<1) ) - - -#define SW_OFFSET_U8_2_U16(byte_offset) ((byte_offset) >> 1) - -#define SW_OFFSET_U16_2_U8(word16_offset) ((word16_offset) << 1) - -#define SW_OFFSET_BIT_2_U8_ALIGN16(bit_offset) (((bit_offset) / 16) * 2) - -#define SW_SET_REG_BY_FIELD(reg, field, field_value, reg_value) \ - SW_REG_SET_BY_FIELD_U32(reg_value, field_value, reg##_##field##_BOFFSET, \ - reg##_##field##_BLEN) - -#define SW_GET_FIELD_BY_REG(reg, field, field_value, reg_value) \ - SW_FIELD_GET_BY_REG_U32(reg_value, field_value, reg##_##field##_BOFFSET, \ - reg##_##field##_BLEN) - - /* port bitmap functions */ -#define SW_IS_PBMP_MEMBER(pbm, port) ((pbm & (1 << port)) ? A_TRUE: A_FALSE) -#define SW_IS_PBMP_EQ(pbm0, pbm1) ((pbm0 == pbm1) ? A_TRUE: A_FALSE) - -#define SW_PBMP_AND(pbm0, pbm1) ((pbm0) &= (pbm1)) -#define SW_PBMP_OR(pbm0, pbm1) ((pbm0) |= (pbm1)) -#define SW_IS_PBMP_INCLUDE(pbm0, pbm1) \ - ((pbm1 == SW_PBMP_AND(pbm0, pbm1)) ? A_TRUE: A_FALSE) - -#define SW_PBMP_CLEAR(pbm) ((pbm) = 0) -#define SW_PBMP_ADD_PORT(pbm, port) ((pbm) |= (1U << (port))) -#define SW_PBMP_DEL_PORT(pbm,port) ((pbm) &= ~(1U << (port))) - -#ifdef __cplusplus -} -#endif /* __cplusplus */ -#endif /* _SHARED_FUNC_H */ diff --git a/feeds/ipq807x/qca-ssdk/src/include/common/sw.h b/feeds/ipq807x/qca-ssdk/src/include/common/sw.h deleted file mode 100755 index fa82d561a..000000000 --- a/feeds/ipq807x/qca-ssdk/src/include/common/sw.h +++ /dev/null @@ -1,33 +0,0 @@ -/* - * Copyright (c) 2012,2018, The Linux Foundation. All rights reserved. - * Permission to use, copy, modify, and/or distribute this software for - * any purpose with or without fee is hereby granted, provided that the - * above copyright notice and this permission notice appear in all copies. - * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES - * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR - * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES - * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN - * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT - * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. - */ - - - -#ifndef _SW_H_ -#define _SW_H_ - -#ifdef __cplusplus -extern "C" { -#endif /* __cplusplus */ - -#include "sw_config.h" -#include "aos_head.h" -#include "sw_error.h" -#include "shared_func.h" - -#ifdef __cplusplus -} -#endif /* __cplusplus */ -#endif /* _SW_H_ */ - diff --git a/feeds/ipq807x/qca-ssdk/src/include/common/sw_config.h b/feeds/ipq807x/qca-ssdk/src/include/common/sw_config.h deleted file mode 100755 index d1c4f6956..000000000 --- a/feeds/ipq807x/qca-ssdk/src/include/common/sw_config.h +++ /dev/null @@ -1,37 +0,0 @@ -/* - * Copyright (c) 2012, 2017, The Linux Foundation. All rights reserved. - * Permission to use, copy, modify, and/or distribute this software for - * any purpose with or without fee is hereby granted, provided that the - * above copyright notice and this permission notice appear in all copies. - * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES - * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR - * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES - * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN - * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT - * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. - */ - - - -#ifndef _SW_CONFIG_H -#define _SW_CONFIG_H - -#ifdef __cplusplus -extern "C" { -#endif /* __cplusplus */ - -#define SW_MAX_NR_DEV 3 -#define SW_MAX_NR_PORT 16 - -#ifdef HSL_STANDALONG -#define HSL_LOCAL -#else -#define HSL_LOCAL static -#endif - -#ifdef __cplusplus -} -#endif /* __cplusplus */ - -#endif diff --git a/feeds/ipq807x/qca-ssdk/src/include/common/sw_error.h b/feeds/ipq807x/qca-ssdk/src/include/common/sw_error.h deleted file mode 100755 index 7a175173f..000000000 --- a/feeds/ipq807x/qca-ssdk/src/include/common/sw_error.h +++ /dev/null @@ -1,62 +0,0 @@ -/* - * Copyright (c) 2012, The Linux Foundation. All rights reserved. - * Permission to use, copy, modify, and/or distribute this software for - * any purpose with or without fee is hereby granted, provided that the - * above copyright notice and this permission notice appear in all copies. - * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES - * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR - * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES - * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN - * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT - * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. - */ - - - -#ifndef _SW_ERROR_H -#define _SW_ERROR_H - -#ifdef __cplusplus -extern "C" { -#endif /* __cplusplus */ - - typedef enum { - SW_OK = 0, /* Operation succeeded */ - SW_FAIL = -1, /* Operation failed */ - SW_BAD_VALUE = -2, /* Illegal value */ - SW_OUT_OF_RANGE = -3, /* Value is out of range */ - SW_BAD_PARAM = -4, /* Illegal parameter(s) */ - SW_BAD_PTR = -5, /* Illegal pointer value */ - SW_BAD_LEN = -6, /* Wrong length */ - SW_BAD_STATE = -7, /* Wrong state of state machine */ - SW_READ_ERROR = -8, /* Read operation failed */ - SW_WRITE_ERROR = -9, /* Write operation failed */ - SW_CREATE_ERROR = -10, /* Fail in creating an entry */ - SW_DELETE_ERROR = -11, /* Fail in deleteing an entry */ - SW_NOT_FOUND = -12, /* Entry not found */ - SW_NO_CHANGE = -13, /* The parameter(s) is the same */ - SW_NO_MORE = -14, /* No more entry found */ - SW_NO_SUCH = -15, /* No such entry */ - SW_ALREADY_EXIST = -16, /* Tried to create existing entry */ - SW_FULL = -17, /* Table is full */ - SW_EMPTY = -18, /* Table is empty */ - SW_NOT_SUPPORTED = -19, /* This request is not support */ - SW_NOT_IMPLEMENTED = -20, /* This request is not implemented */ - SW_NOT_INITIALIZED = -21, /* The item is not initialized */ - SW_BUSY = -22, /* Operation is still running */ - SW_TIMEOUT = -23, /* Operation Time Out */ - SW_DISABLE = -24, /* Operation is disabled */ - SW_NO_RESOURCE = -25, /* Resource not available (memory ...) */ - SW_INIT_ERROR = -26, /* Error occured while INIT process */ - SW_NOT_READY = -27, /* The other side is not ready yet */ - SW_OUT_OF_MEM = -28, /* Cpu memory allocation failed. */ - SW_ABORTED = -29 /* Operation has been aborted. */ - } sw_error_t; - -#ifdef __cplusplus -} -#endif /* __cplusplus */ - -#endif /* _SW_ERROR_H */ - diff --git a/feeds/ipq807x/qca-ssdk/src/include/common/util.h b/feeds/ipq807x/qca-ssdk/src/include/common/util.h deleted file mode 100755 index 9baa22e9f..000000000 --- a/feeds/ipq807x/qca-ssdk/src/include/common/util.h +++ /dev/null @@ -1,92 +0,0 @@ -/* - * Copyright (c) 2012, The Linux Foundation. All rights reserved. - * Permission to use, copy, modify, and/or distribute this software for - * any purpose with or without fee is hereby granted, provided that the - * above copyright notice and this permission notice appear in all copies. - * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES - * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR - * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES - * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN - * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT - * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. - */ - - - -#ifndef _UTIL_H_ -#define _UTIL_H_ - -#ifdef __cplusplus -extern "C" { -#endif /* __cplusplus */ - -#define LL_IN_ORDER 0x1 -#define LL_FIX_NDNR 0x2 - - typedef enum { - LL_CMP_EQUAL = 0, - LL_CMP_GREATER = 1, - LL_CMP_SMALLER = 2 - } - ll_cmp_rslt_t; - - typedef ll_cmp_rslt_t(*ll_nd_cmp) (void *src, void *dest); - - typedef void (*ll_nd_dump) (void *data); - - typedef struct _sll_node_t - { - struct _sll_node_t *next; - void *data; - } sll_node_t; - - typedef struct - { - sll_node_t *fst_nd; - a_uint32_t nd_nr; - a_uint32_t flag; - ll_nd_cmp nd_cmp; - ll_nd_dump nd_dump; - sll_node_t *free_nd; - } sll_head_t; - - sll_head_t *sll_creat(ll_nd_cmp cmp_func, ll_nd_dump dump_func, - a_uint32_t flag, a_uint32_t nd_nr); - - void sll_destroy(sll_head_t * sll); - - void sll_lock(sll_head_t * sll); - - void sll_unlock(sll_head_t * sll); - - void *sll_nd_find(const sll_head_t * sll, void *data, - a_ulong_t *iterator); - - void *sll_nd_next(const sll_head_t *sll, a_ulong_t *iterator); - - sw_error_t sll_nd_insert(sll_head_t * sll, void *data); - - sw_error_t sll_nd_delete(sll_head_t * sll, void *data); - - typedef struct - { - a_uint32_t id_ptr; - a_uint32_t id_nr; - a_uint32_t id_min; - a_uint32_t id_size; - void *id_pool; - } sid_pool_t; - - sid_pool_t *sid_pool_creat(a_uint32_t id_nr, a_uint32_t min_id); - - void sid_pool_destroy(sid_pool_t * pool); - - sw_error_t sid_pool_id_alloc(sid_pool_t * pool, a_uint32_t * id); - - sw_error_t sid_pool_id_free(sid_pool_t * pool, a_uint32_t id); - -#ifdef __cplusplus -} -#endif /* __cplusplus */ -#endif /* _UTIL_H_ */ diff --git a/feeds/ipq807x/qca-ssdk/src/include/fal/fal.h b/feeds/ipq807x/qca-ssdk/src/include/fal/fal.h deleted file mode 100755 index 09d21ffd6..000000000 --- a/feeds/ipq807x/qca-ssdk/src/include/fal/fal.h +++ /dev/null @@ -1,68 +0,0 @@ -/* - * Copyright (c) 2012, 2017-2019, The Linux Foundation. All rights reserved. - * Permission to use, copy, modify, and/or distribute this software for - * any purpose with or without fee is hereby granted, provided that the - * above copyright notice and this permission notice appear in all copies. - * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES - * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR - * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES - * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN - * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT - * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. - */ - - -/*qca808x_start*/ -#ifndef _FAL_H -#define _FAL_H - -#ifdef __cplusplus -extern "C" { -#endif /* __cplusplus */ -#include "fal_port_ctrl.h" -/*qca808x_end*/ -#include "fal_misc.h" -#include "fal_vlan.h" -#include "fal_fdb.h" -#include "fal_portvlan.h" -#include "fal_qos.h" -#include "fal_stp.h" -#include "fal_rate.h" -#include "fal_mirror.h" -#include "fal_leaky.h" -#include "fal_igmp.h" -#include "fal_mib.h" -#include "fal_acl.h" -#include "fal_led.h" -/*qca808x_start*/ -#include "fal_reg_access.h" -#include "fal_init.h" -/*qca808x_end*/ -#include "fal_cosmap.h" -#include "fal_ip.h" -#include "fal_nat.h" -#include "fal_flow.h" -#include "fal_qm.h" -#include "fal_sec.h" -#include "fal_trunk.h" -#include "fal_interface_ctrl.h" -#include "fal_fdb.h" -#include "fal_multi.h" -#include "fal_ctrlpkt.h" -#include "fal_servcode.h" -#include "fal_rss_hash.h" -#include "fal_vsi.h" -#include "fal_pppoe.h" -#include "fal_bm.h" -#include "fal_shaper.h" -#include "fal_policer.h" -#include "fal_ptp.h" -#include "fal_sfp.h" - -/*qca808x_start*/ -#ifdef __cplusplus -} -#endif /* __cplusplus */ -#endif /* _FAL_H */ -/*qca808x_end*/ diff --git a/feeds/ipq807x/qca-ssdk/src/include/fal/fal_acl.h b/feeds/ipq807x/qca-ssdk/src/include/fal/fal_acl.h deleted file mode 100755 index e9c9f9cf8..000000000 --- a/feeds/ipq807x/qca-ssdk/src/include/fal/fal_acl.h +++ /dev/null @@ -1,616 +0,0 @@ -/* - * Copyright (c) 2014, 2016-2018, The Linux Foundation. All rights reserved. - * Permission to use, copy, modify, and/or distribute this software for - * any purpose with or without fee is hereby granted, provided that the - * above copyright notice and this permission notice appear in all copies. - * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES - * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR - * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES - * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN - * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT - * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. - */ - - -/** - * @defgroup fal_acl FAL_ACL - * @{ - */ -#ifndef _FAL_ACL_H_ -#define _FAL_ACL_H_ - -#ifdef __cplusplus -extern "C" { -#endif /* __cplusplus */ - -#include "sw.h" -#include "fal/fal_type.h" - - - /** - @brief This enum defines the ACL rule type. - */ - typedef enum { - FAL_ACL_RULE_MAC = 0, /**< include MAC, udf fields*/ - FAL_ACL_RULE_IP4, /**< include MAC, IP4 and Tcp/Udp udf fields*/ - FAL_ACL_RULE_IP6, /**< include MAC, IP6 and Tcp/Udp udf fields*/ - FAL_ACL_RULE_UDF, /**< only include user defined fields*/ - FAL_ACL_RULE_BUTT, - } - fal_acl_rule_type_t; - - - /** - @brief This enum defines the ACL field operation type. - */ - typedef enum - { - FAL_ACL_FIELD_MASK = 0, /**< match operation is mask*/ - FAL_ACL_FIELD_RANGE, /**< match operation is range*/ - FAL_ACL_FIELD_LE, /**< match operation is less than equal*/ - FAL_ACL_FIELD_GE, /**< match operation is greater than equal*/ - FAL_ACL_FIELD_NE, /**<- match operation is not equal*/ - FAL_ACL_FIELD_OP_BUTT, - } fal_acl_field_op_t; - - - typedef enum - { - FAL_ACL_POLICY_ROUTE = 0, - FAL_ACL_POLICY_SNAT, - FAL_ACL_POLICY_DNAT, - FAL_ACL_POLICY_RESERVE, - } fal_policy_forward_t; - - typedef enum - { - FAL_ACL_COMBINED_NONE = 0, - FAL_ACL_COMBINED_START, - FAL_ACL_COMBINED_CONTINUE, - FAL_ACL_COMBINED_END, - } fal_combined_t; - - /** - @brief This enum defines the ACL field operation type. - */ - typedef enum - { - FAL_ACL_UDF_TYPE_L2 = 0, /*start from L2 */ - FAL_ACL_UDF_TYPE_L3, /*start from L3 */ - FAL_ACL_UDF_TYPE_L4, /*start from L4 */ - FAL_ACL_UDF_TYPE_L2_SNAP, /*start from SNAP L2 */ - FAL_ACL_UDF_TYPE_L3_PLUS, /*start from SNAP L3 */ - FAL_ACL_UDF_TYPE_BUTT, - } fal_acl_udf_type_t; - - /** - @brief This enum defines the ACL rule type. - */ - typedef enum { - FAL_ACL_UDF_NON_IP = 0, /*UDF for non-ip packets*/ - FAL_ACL_UDF_IP4, /*UDF for IPv4 packets*/ - FAL_ACL_UDF_IP6, /*UDF for IPv6 packets*/ - FAL_ACL_UDF_BUTT, - }fal_acl_udf_pkt_type_t; - -typedef enum { - FAL_ACL_DEST_PORT_BMP = 0, /*dest info is bitmap*/ - FAL_ACL_DEST_NEXTHOP, /*dest info is nexthop*/ - FAL_ACL_DEST_PORT_ID, /*dest info is port id*/ -}fal_acl_dest_type_t; - -#define FAL_ACL_DEST_OFFSET(type,value) (((type)<<24)|(value)) -#define FAL_ACL_DEST_TYPE(dest) (((dest)>>24)&0xff) -#define FAL_ACL_DEST_VALUE(dest) ((dest)&0xffffff) - -#define FAL_ACL_FIELD_MAC_DA 0 -#define FAL_ACL_FIELD_MAC_SA 1 -#define FAL_ACL_FIELD_MAC_ETHTYPE 2 -#define FAL_ACL_FIELD_MAC_TAGGED 3 -#define FAL_ACL_FIELD_MAC_UP 4 -#define FAL_ACL_FIELD_MAC_VID 5 -#define FAL_ACL_FIELD_IP4_SIP 6 -#define FAL_ACL_FIELD_IP4_DIP 7 -#define FAL_ACL_FIELD_IP6_LABEL 8 -#define FAL_ACL_FIELD_IP6_SIP 9 -#define FAL_ACL_FIELD_IP6_DIP 10 -#define FAL_ACL_FIELD_IP_PROTO 11 -#define FAL_ACL_FIELD_IP_DSCP 12 -#define FAL_ACL_FIELD_L4_SPORT 13 -#define FAL_ACL_FIELD_L4_DPORT 14 -#define FAL_ACL_FIELD_UDF 15 -#define FAL_ACL_FIELD_MAC_CFI 16 -#define FAL_ACL_FIELD_ICMP_TYPE 17 -#define FAL_ACL_FIELD_ICMP_CODE 18 -#define FAL_ACL_FIELD_TCP_FLAG 19 -#define FAL_ACL_FIELD_RIPV1 20 -#define FAL_ACL_FIELD_DHCPV4 21 -#define FAL_ACL_FIELD_DHCPV6 22 -#define FAL_ACL_FIELD_MAC_STAG_VID 23 -#define FAL_ACL_FIELD_MAC_STAG_PRI 24 -#define FAL_ACL_FIELD_MAC_STAG_DEI 25 -#define FAL_ACL_FIELD_MAC_STAGGED 26 -#define FAL_ACL_FIELD_MAC_CTAG_VID 27 -#define FAL_ACL_FIELD_MAC_CTAG_PRI 28 -#define FAL_ACL_FIELD_MAC_CTAG_CFI 29 -#define FAL_ACL_FIELD_MAC_CTAGGED 30 -#define FAL_ACL_FIELD_INVERSE_ALL 31 -/*new add for hawkeye*/ -#define FAL_ACL_FIELD_POST_ROURING_EN 32 -#define FAL_ACL_FIELD_RES_CHAIN 33 -#define FAL_ACL_FIELD_FAKE_MAC_HEADER 34 -#define FAL_ACL_FIELD_SNAP 35 -#define FAL_ACL_FIELD_ETHERNET 36 -#define FAL_ACL_FIELD_IPV6 37 -#define FAL_ACL_FIELD_IP 38 -#define FAL_ACL_FIELD_VSI 39 -#define FAL_ACL_FIELD_PPPOE_SESSIONID 40 -#define FAL_ACL_FIELD_L3_FRAGMENT 41 -#define FAL_ACL_FIELD_AH_HEADER 42 -#define FAL_ACL_FIELD_ESP_HEADER 43 -#define FAL_ACL_FIELD_MOBILITY_HEADER 44 -#define FAL_ACL_FIELD_FRAGMENT_HEADER 45 -#define FAL_ACL_FIELD_OTHER_EXT_HEADER 46 -#define FAL_ACL_FIELD_L3_TTL 47 -#define FAL_ACL_FIELD_IPV4_OPTION 48 -#define FAL_ACL_FIELD_FIRST_FRAGMENT 49 -#define FAL_ACL_FIELD_L3_LENGTH 50 -#define FAL_ACL_FIELD_VSI_VALID 51 -#define FAL_ACL_FIELD_IP_PKT_TYPE 52 - -#define FAL_ACL_FIELD_UDF0 53 -#define FAL_ACL_FIELD_UDF1 54 -#define FAL_ACL_FIELD_UDF2 55 -#define FAL_ACL_FIELD_UDF3 56 - -#define FAL_ACL_FIELD_NUM 57 - - -#define FAL_ACL_ACTION_PERMIT 0 -#define FAL_ACL_ACTION_DENY 1 -#define FAL_ACL_ACTION_REDPT 2 -#define FAL_ACL_ACTION_RDTCPU 3 -#define FAL_ACL_ACTION_CPYCPU 4 -#define FAL_ACL_ACTION_MIRROR 5 -#define FAL_ACL_ACTION_MODIFY_VLAN 6 -#define FAL_ACL_ACTION_NEST_VLAN 7 -#define FAL_ACL_ACTION_REMARK_UP 8 -#define FAL_ACL_ACTION_REMARK_QUEUE 9 -#define FAL_ACL_ACTION_REMARK_STAG_VID 10 -#define FAL_ACL_ACTION_REMARK_STAG_PRI 11 -#define FAL_ACL_ACTION_REMARK_STAG_DEI 12 -#define FAL_ACL_ACTION_REMARK_CTAG_VID 13 -#define FAL_ACL_ACTION_REMARK_CTAG_PRI 14 -#define FAL_ACL_ACTION_REMARK_CTAG_CFI 15 -#define FAL_ACL_ACTION_REMARK_LOOKUP_VID 16 -#define FAL_ACL_ACTION_REMARK_DSCP 17 -#define FAL_ACL_ACTION_POLICER_EN 18 -#define FAL_ACL_ACTION_WCMP_EN 19 -#define FAL_ACL_ACTION_ARP_EN 20 -#define FAL_ACL_ACTION_POLICY_FORWARD_EN 21 -#define FAL_ACL_ACTION_BYPASS_EGRESS_TRANS 22 -#define FAL_ACL_ACTION_MATCH_TRIGGER_INTR 23 -/*new add for hawkeye*/ -#define FAL_ACL_ACTION_ENQUEUE_PRI 25 -#define FAL_ACL_ACTION_INT_DP 26 -#define FAL_ACL_ACTION_SERVICE_CODE 27 -#define FAL_ACL_ACTION_CPU_CODE 28 -#define FAL_ACL_ACTION_SYN_TOGGLE 29 -#define FAL_ACL_ACTION_METADATA_EN 30 - - -enum{ - FAL_ACL_BYPASS_IN_VLAN_MISS = 0, - FAL_ACL_BYPASS_SOUCE_GUARD, - FAL_ACL_BYPASS_MRU_MTU_CHECK, - FAL_ACL_BYPASS_EG_VSI_MEMBER_CHECK = 8, - FAL_ACL_BYPASS_EG_VLAN_TRANSLATION, - FAL_ACL_BYPASS_EG_VLAN_TAG_CTRL = 10, - FAL_ACL_BYPASS_FDB_LEARNING, - FAL_ACL_BYPASS_FDB_REFRESH, - FAL_ACL_BYPASS_L2_SECURITY,/*new address, station move, learn limit, hash full*/ - FAL_ACL_BYPASS_MANAGEMENT_FWD, - FAL_ACL_BYPASS_L2_FWD = 15, - FAL_ACL_BYPASS_IN_STP_CHECK, - FAL_ACL_BYPASS_EG_STP_CHECK, - FAL_ACL_BYPASS_SOURCE_FILTER, - FAL_ACL_BYPASS_POLICYER, - FAL_ACL_BYPASS_L2_EDIT = 20,/*VLAN tag edit*/ - FAL_ACL_BYPASS_L3_EDIT,/*Edit MAC address, PPPoE, IP address, TTL, DSCP, L4 port*/ - FAL_ACL_BYPASS_POST_ACL_CHECK_ROUTING, - FAL_ACL_BYPASS_PORT_ISOLATION, -}; - - - /** - * @brief This type defines the action in Acl rule. - * @details Comments: - * It's a bit map type, we can access it through macro FAL_ACTION_FLG_SET, - * FAL_ACTION_FLG_CLR and FAL_ACTION_FLG_TST. - */ - typedef a_uint32_t fal_acl_action_map_t; - -#define FAL_ACTION_FLG_SET(flag, action) \ - (flag) |= (0x1UL << (action)) - -#define FAL_ACTION_FLG_CLR(flag, action) \ - (flag) &= (~(0x1UL << (action))) - -#define FAL_ACTION_FLG_TST(flag, action) \ - ((flag) & (0x1UL << (action))) ? 1 : 0 - - - /** - * @brief This type defines the field in Acl rule. - * @details Comments: - * It's a bit map type, we can access it through macro FAL_FIELD_FLG_SET, - * FAL_FIELD_FLG_CLR and FAL_FIELD_FLG_TST. - */ - typedef a_uint32_t fal_acl_field_map_t[2]; - -#define FAL_FIELD_FLG_SET(flag, field) \ - ((flag[(field) / 32]) |= (0x1UL << ((field) % 32))) - -#define FAL_FIELD_FLG_CLR(flag, field) \ - ((flag[(field) / 32]) &= (~(0x1UL << ((field) % 32)))) - -#define FAL_FIELD_FLG_TST(flag, field) \ - (((flag[(field) / 32]) & (0x1UL << ((field) % 32))) ? 1 : 0) - -#define FAL_ACL_UDF_MAX_LENGTH 16 - - /** - * @brief This structure defines the Acl rule. - * @details Fields description: - * - * - * vid_val - If vid_op equals FAL_ACL_FIELD_MASK it's vlan id field value. - * If vid_op equals FAL_ACL_FIELD_RANGE it's vlan id field low value. If - * vid_op equals other value it's the compared value. - * - * vid_mask - If vid_op equals FAL_ACL_FIELD_MASK it's vlan id field mask. - * If vid_op equals FAL_ACL_FIELD_RANGE it's vlan id field high value. If vid_op - * equals other value it's meaningless. - * - * - * ip_dscp_val - It's eight bits field we can set any value between 0 - 255. - * ip_dscp_mask - It's eight bits field we can set any value between 0 - 255. - * - * - * src_l4port_val - If src_l4port_op equals FAL_ACL_FIELD_MASK it's layer four - * source port field value. If src_l4port_op equals FAL_ACL_FIELD_RANGE it's - * layer four source port field low value. If src_l4port_op equals other value - * it's the compared value. - * - * - * src_l4port_mask - If src_l4port_op equals FAL_ACL_FIELD_MASK it's layer four - * source port field mask. If src_l4port_op equals FAL_ACL_FIELD_RANGE it's - * layer four source port field high value. If src_l4port_op equals other value - * it's meaningless. - * - * - * dest_l4port_val - If dest_l4port_op equals FAL_ACL_FIELD_MASK it's layer four - * destination port field value. If dest_l4port_op equals FAL_ACL_FIELD_RANGE it's - * layer four source port field low value. If dest_l4port_op equals other value - * it's the compared value. - * - * - * dest_l4port_mask - If dest_l4port_op equals FAL_ACL_FIELD_MASK it's layer four - * source port field mask. If dest_l4port_op equals FAL_ACL_FIELD_RANGE it's - * layer four source port field high value. If dest_l4port_op equals other value - * it's meaningless. - * - * - * ports - If FAL_ACL_ACTION_REDPT bit is setted in action_flg it's redirect - * destination ports. - * - * - * dot1p - If FAL_ACL_ACTION_REMARK_DOT1P bit is setted in action_flg it's - * the expected dot1p value. - * - * - * queue - If FAL_ACL_ACTION_REMARK_QUEUE bit is setted in action_flg it's - * the expected queue value. - * - * - * vid - If FAL_ACL_ACTION_MODIFY_VLAN or FAL_ACL_ACTION_NEST_VLAN bit is - * setted in action_flg it's the expected vlan id value. - */ -typedef struct -{ - fal_acl_rule_type_t rule_type;/*mac, IP4, IP6 and UDF*/ - fal_acl_field_map_t field_flg;/*Indicate which fields are selected*/ - - /* fields of mac rule */ - fal_mac_addr_t src_mac_val;/*source mac*/ - fal_mac_addr_t src_mac_mask;/*source mac mask*/ - fal_mac_addr_t dest_mac_val;/*destination mac*/ - fal_mac_addr_t dest_mac_mask;/*destionation mac mask*/ - a_uint16_t ethtype_val;/*ethernet type*/ - a_uint16_t ethtype_mask;/*ethernet type mask*/ - a_uint16_t vid_val;/*vlan id, IPQ807x not support*/ - a_uint16_t vid_mask;/*vlan id mask*/ - fal_acl_field_op_t vid_op;/*vlan id operation, larger than or smaller than or range or mask*/ - a_uint8_t tagged_val;/*tagged or not, IPQ807x not support*/ - a_uint8_t tagged_mask;/*tagged or not mask*/ - a_uint8_t up_val;/*cos priority, IPQ807x not support*/ - a_uint8_t up_mask;/*cos priority mask*/ - a_uint8_t cfi_val;/*CFI value, IPQ807x not support*/ - a_uint8_t cfi_mask;/*CFI value mask*/ - a_uint16_t resv0;/*reserved*/ - - /* fields of enhanced mac rule*/ - a_uint8_t stagged_val; /*for s17c : 0-untag, 1-tag, for hawkeye: 2-pritag, 3-utag+pritag, 4- untag+tag, 5-tag+pritag, 6-all*/ - a_uint8_t stagged_mask; - a_uint8_t ctagged_val;/*same as stagged define*/ - a_uint8_t ctagged_mask; - a_uint16_t stag_vid_val;/*stag vlan id*/ - a_uint16_t stag_vid_mask;/*stag vlan id mask*/ - fal_acl_field_op_t stag_vid_op;/*vlan id operation, larger than or smaller than or range or mask*/ - a_uint16_t ctag_vid_val; - a_uint16_t ctag_vid_mask; - fal_acl_field_op_t ctag_vid_op; - a_uint8_t stag_pri_val;/*stag priority*/ - a_uint8_t stag_pri_mask;/*stag priority mask*/ - a_uint8_t ctag_pri_val; - a_uint8_t ctag_pri_mask; - a_uint8_t stag_dei_val;/*stag dei*/ - a_uint8_t stag_dei_mask;/*stag dei mask*/ - a_uint8_t ctag_cfi_val;/*ctag cfi*/ - a_uint8_t ctag_cfi_mask;/*ctag cfi mask*/ - - /* fields of ip4 rule */ - fal_ip4_addr_t src_ip4_val;/*source ipv4 address*/ - fal_ip4_addr_t src_ip4_mask;/*source ipv4 address mask*/ - fal_ip4_addr_t dest_ip4_val;/*destination ipv4 address*/ - fal_ip4_addr_t dest_ip4_mask;/*destination ipv4 address mask*/ - - /* fields of ip6 rule */ - a_uint32_t ip6_lable_val;/*ipv6 flow lable, IPQ807x not support*/ - a_uint32_t ip6_lable_mask;/*ipv6 flow lable mask*/ - fal_ip6_addr_t src_ip6_val;/*source ipv6 address*/ - fal_ip6_addr_t src_ip6_mask;/*source ipv6 address mask*/ - fal_ip6_addr_t dest_ip6_val;/*destination ipv6 address*/ - fal_ip6_addr_t dest_ip6_mask;/*destination ipv6 address mask*/ - - /* fields of ip rule */ - a_uint8_t ip_proto_val;/*IP protocal*/ - a_uint8_t ip_proto_mask;/*IP protocal mask*/ - a_uint8_t ip_dscp_val;/*IP DSCP*/ - a_uint8_t ip_dscp_mask;/*IP DSCP mask*/ - - /* fields of layer four */ - a_uint16_t src_l4port_val;/*source L4 port*/ - a_uint16_t src_l4port_mask;/*source L4 port mask*/ - fal_acl_field_op_t src_l4port_op;/*source L4 port operation*/ - a_uint16_t dest_l4port_val;/*destination L4 port*/ - a_uint16_t dest_l4port_mask;/*destination L4 mask*/ - fal_acl_field_op_t dest_l4port_op;/*destination L4 operation*/ - a_uint8_t icmp_type_val;/*ICMP type*/ - a_uint8_t icmp_type_mask;/*ICMP type mask*/ - a_uint8_t icmp_code_val;/*ICMP code*/ - a_uint8_t icmp_code_mask;/*ICMP code mask*/ - a_uint8_t tcp_flag_val;/*tcp flags value*/ - a_uint8_t tcp_flag_mask;/*tcp flags mask*/ - a_uint8_t ripv1_val;/*Is RIPv1 or not, IPQ807x not support*/ - a_uint8_t ripv1_mask;/*RIPv1 mask*/ - a_uint8_t dhcpv4_val;/*Is DHCPv4 or not, IPQ807x not support*/ - a_uint8_t dhcpv4_mask; - a_uint8_t dhcpv6_val;/*Is DHCPv6 or not, IPQ807x not support*/ - a_uint8_t dhcpv6_mask; - - /* user defined fields */ - fal_acl_udf_type_t udf_type;/*UDF type, IPQ807x not support*/ - a_uint8_t udf_offset;/*UDF offset, IPQ807x not support*/ - a_uint8_t udf_len;/*UDF length, IPQ807x not support*/ - a_uint8_t udf_val[FAL_ACL_UDF_MAX_LENGTH];/*UDF field value*/ - a_uint8_t udf_mask[FAL_ACL_UDF_MAX_LENGTH];/*UDF field mask*/ - - /* fields of action */ - fal_acl_action_map_t action_flg;/*Indicate which action apply*/ - fal_pbmp_t ports; /*high 8bits, 00-port bitmap, 01-nexthop, 10-vp*/ - a_uint32_t match_cnt;/*rule match frame counter*/ - a_uint16_t vid;/*modify vlan id, IPQ807x not support*/ - a_uint8_t up;/*modify COS priority, IPQ807x not support*/ - a_uint8_t queue;/*modify queue*/ - a_uint16_t stag_vid;/*modify stag vlan id*/ - a_uint8_t stag_pri;/*modify stag priority*/ - a_uint8_t stag_dei;/*modify stag dei*/ - a_uint16_t ctag_vid;/*modify ctag vlan id*/ - a_uint8_t ctag_pri;/*modify ctag priority*/ - a_uint8_t ctag_cfi;/*modify ctag dei*/ - a_uint16_t policer_ptr;/*specify policer index*/ - a_uint16_t arp_ptr;/*specify arp table index, IPQ807x not support*/ - a_uint16_t wcmp_ptr;/*specify wcmp table index, IPQ807x not support*/ - a_uint8_t dscp;/*modify dscp*/ - a_uint8_t rsv; - fal_policy_forward_t policy_fwd;/*SNAT or DNAT or ROUTE, IPQ807x not support*/ - fal_combined_t combined; - - /*Only IPQ807x support start*/ - a_uint8_t pri; /*rule priority 0-7*/ - a_bool_t post_routing;/*post routing or not*/ - a_uint8_t acl_pool;/*acl pool*/ - - a_bool_t is_ip_val;/*is ip or not*/ - a_uint8_t is_ip_mask; - a_bool_t is_ipv6_val;/*is ipv6 or ipv4*/ - a_uint8_t is_ipv6_mask; - a_bool_t is_fake_mac_header_val;/*is fake mac header or not*/ - a_uint8_t is_fake_mac_header_mask; - a_bool_t is_snap_val;/*is snap or not*/ - a_uint8_t is_snap_mask; - a_bool_t is_ethernet_val;/*is ethernet or not*/ - a_uint8_t is_ethernet_mask; - - a_bool_t is_fragement_val;/*is fragment or not*/ - a_uint8_t is_fragement_mask; - - a_bool_t is_ah_header_val;/*is ah header or not*/ - a_uint8_t is_ah_header_mask; - - a_bool_t is_esp_header_val;/*is esp header or not*/ - a_uint8_t is_esp_header_mask; - - a_bool_t is_mobility_header_val;/*is mobility header or not*/ - a_uint8_t is_mobility_header_mask; - - a_bool_t is_fragment_header_val;/*is fragment header or not*/ - a_uint8_t is_fragment_header_mask; - - a_bool_t is_other_header_val;/*is other header or not*/ - a_uint8_t is_other_header_mask; - - a_bool_t is_ipv4_option_val;/*is ipv4 option or not*/ - a_uint8_t is_ipv4_option_mask; - - a_bool_t is_first_frag_val;/*is first fragment or not*/ - a_uint8_t is_first_frag_mask; - - /*fields of VLAN rule*/ - a_bool_t vsi_valid;/*vsi valid or not*/ - a_uint8_t vsi_valid_mask; - a_uint8_t vsi; /*vsi value 0-31*/ - a_uint8_t vsi_mask; /*vsi mask 0-31*/ - /*fields of L2 MISC rule*/ - a_uint16_t pppoe_sessionid;/*pppoe session id*/ - a_uint16_t pppoe_sessionid_mask;/*pppoe session mask*/ - fal_acl_field_op_t icmp_type_code_op;/*icmp type operation*/ - /*fields of IP MISC rule*/ - a_uint8_t l3_ttl;/*L3 TTL,0-ttl 0, 1-ttl 1, 2-ttl 255, 3- ttl other*/ - a_uint8_t l3_ttl_mask;/*L3 TTL mask*/ - fal_acl_field_op_t l3_length_op;/*L3 TTL operation*/ - a_uint16_t l3_length;/*L3 length*/ - a_uint16_t l3_length_mask;/*L3 length mask*/ - a_uint16_t l3_pkt_type;/*l3 packet type, 0-tcp, 1-udp, 3-udp_lite, 5-arp, 7-icmp*/ - a_uint16_t l3_pkt_type_mask; - /*field of udf*/ - fal_acl_field_op_t udf0_op;/*udf operation*/ - a_uint16_t udf0_val;/*udf value, 2bytes*/ - a_uint16_t udf0_mask;/*udf mask, 2bytes*/ - fal_acl_field_op_t udf1_op; - a_uint16_t udf1_val; - a_uint16_t udf1_mask; - a_uint16_t udf2_val; - a_uint16_t udf2_mask; - a_uint16_t udf3_val; - a_uint16_t udf3_mask; - - /*new add acl action for hawkeye*/ - a_uint32_t bypass_bitmap;/*bypass bitmap*/ - a_uint8_t enqueue_pri;/*enqueue priority*/ - a_uint8_t stag_fmt;/*stag format*/ - a_uint8_t ctag_fmt;/*ctag format*/ - a_uint8_t int_dp;/*internal dp*/ - a_uint8_t service_code;/*service code*/ - a_uint8_t cpu_code;/*cpu code*/ - a_uint64_t match_bytes;/*rule match bytes counter*/ - /*Only IPQ807x support End*/ - - /*new add acl action for IPQ60xx*/ - a_uint8_t dscp_mask;/*modify dscp mask,IPQ60xx support*/ - a_uint8_t qos_res_prec;/*qos res prec,IPQ60xx support*/ -} fal_acl_rule_t; - - - /** - @brief This enum defines the ACL will work on which derection traffic. - */ - typedef enum - { - FAL_ACL_DIREC_IN = 0, /**< Acl will work on ingressive traffic */ - FAL_ACL_DIREC_EG, /**< Acl will work on egressive traffic */ - FAL_ACL_DIREC_BOTH, /**< Acl will work on both ingressive and egressive traffic*/ - } fal_acl_direc_t; - - - /** - @brief This enum defines the ACL will work on which partiualr object. - */ - typedef enum - { - FAL_ACL_BIND_PORT = 0, /**< Acl wil work on particular port and virtual port */ - FAL_ACL_BIND_PORTBITMAP = 1, /**< Acl wil work on port bitmap */ - FAL_ACL_BIND_SERVICE_CODE = 2, /**< Acl wil work on service code */ - FAL_ACL_BIND_L3_IF = 3, /**< Acl wil work on l3 interface */ - } fal_acl_bind_obj_t; - -enum -{ - /*acl*/ - FUNC_ACL_LIST_CREAT = 0, - FUNC_ACL_LIST_DESTROY, - FUNC_ACL_RULE_ADD, - FUNC_ACL_RULE_DELETE, - FUNC_ACL_RULE_QUERY, - FUNC_ACL_RULE_DUMP, - FUNC_ACL_LIST_BIND, - FUNC_ACL_LIST_UNBIND, - FUNC_ACL_LIST_DUMP, - FUNC_ACL_UDF_PROFILE_SET, - FUNC_ACL_UDF_PROFILE_GET, -}; - - -sw_error_t -fal_acl_list_creat(a_uint32_t dev_id, a_uint32_t list_id, a_uint32_t list_pri); - -sw_error_t -fal_acl_list_destroy(a_uint32_t dev_id, a_uint32_t list_id); - -sw_error_t -fal_acl_rule_add(a_uint32_t dev_id, a_uint32_t list_id, a_uint32_t rule_id, a_uint32_t rule_nr, fal_acl_rule_t * rule); - -sw_error_t -fal_acl_rule_delete(a_uint32_t dev_id, a_uint32_t list_id, a_uint32_t rule_id, a_uint32_t rule_nr); - -sw_error_t -fal_acl_rule_query(a_uint32_t dev_id, a_uint32_t list_id, a_uint32_t rule_id, fal_acl_rule_t * rule); - -sw_error_t -fal_acl_list_bind(a_uint32_t dev_id, a_uint32_t list_id, fal_acl_direc_t direc, fal_acl_bind_obj_t obj_t, a_uint32_t obj_idx); - -sw_error_t -fal_acl_list_unbind(a_uint32_t dev_id, a_uint32_t list_id, fal_acl_direc_t direc, fal_acl_bind_obj_t obj_t, a_uint32_t obj_idx); - -sw_error_t -fal_acl_status_set(a_uint32_t dev_id, a_bool_t enable); - -sw_error_t -fal_acl_status_get(a_uint32_t dev_id, a_bool_t * enable); - -sw_error_t -fal_acl_list_dump(a_uint32_t dev_id); - -sw_error_t -fal_acl_rule_dump(a_uint32_t dev_id); - -sw_error_t -fal_acl_port_udf_profile_set(a_uint32_t dev_id, fal_port_t port_id, fal_acl_udf_type_t udf_type, a_uint32_t offset, a_uint32_t length); -sw_error_t -fal_acl_port_udf_profile_get(a_uint32_t dev_id, fal_port_t port_id, fal_acl_udf_type_t udf_type, a_uint32_t * offset, a_uint32_t * length); - -sw_error_t -fal_acl_udf_profile_set(a_uint32_t dev_id, fal_acl_udf_pkt_type_t pkt_type,a_uint32_t udf_idx, fal_acl_udf_type_t udf_type, a_uint32_t offset); - -sw_error_t -fal_acl_udf_profile_get(a_uint32_t dev_id, fal_acl_udf_pkt_type_t pkt_type,a_uint32_t udf_idx, fal_acl_udf_type_t *udf_type, a_uint32_t *offset); - -sw_error_t -fal_acl_rule_active(a_uint32_t dev_id, a_uint32_t list_id, a_uint32_t rule_id, a_uint32_t rule_nr); -sw_error_t -fal_acl_rule_deactive(a_uint32_t dev_id, a_uint32_t list_id, a_uint32_t rule_id, a_uint32_t rule_nr); -sw_error_t -fal_acl_rule_src_filter_sts_set(a_uint32_t dev_id, a_uint32_t rule_id, a_bool_t enable); -sw_error_t -fal_acl_rule_src_filter_sts_get(a_uint32_t dev_id, a_uint32_t rule_id, a_bool_t* enable); - - -#ifdef __cplusplus -} -#endif /* __cplusplus */ -#endif /* _FAL_ACL_H_ */ -/** - * @} - */ diff --git a/feeds/ipq807x/qca-ssdk/src/include/fal/fal_api.h b/feeds/ipq807x/qca-ssdk/src/include/fal/fal_api.h deleted file mode 100755 index 51aff5701..000000000 --- a/feeds/ipq807x/qca-ssdk/src/include/fal/fal_api.h +++ /dev/null @@ -1,2428 +0,0 @@ -/* - * Copyright (c) 2012, 2015-2019, 2021, The Linux Foundation. All rights reserved. - * Permission to use, copy, modify, and/or distribute this software for - * any purpose with or without fee is hereby granted, provided that the - * above copyright notice and this permission notice appear in all copies. - * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES - * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR - * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES - * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN - * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT - * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. - */ - - -/*qca808x_start*/ -#ifndef _FAL_API_H_ -#define _FAL_API_H_ - -#ifdef __cplusplus -extern "C" { -#endif /* __cplusplus */ -/*qca808x_end*/ -#ifdef IN_PORTCONTROL -#ifndef IN_PORTCONTROL_MINI -/*qca808x_start*/ -#define PORTCONTROL_API \ - SW_API_DEF(SW_API_PT_DUPLEX_GET, fal_port_duplex_get), \ - SW_API_DEF(SW_API_PT_DUPLEX_SET, fal_port_duplex_set), \ - SW_API_DEF(SW_API_PT_SPEED_GET, fal_port_speed_get), \ - SW_API_DEF(SW_API_PT_SPEED_SET, fal_port_speed_set), \ - SW_API_DEF(SW_API_PT_AN_GET, fal_port_autoneg_status_get), \ - SW_API_DEF(SW_API_PT_AN_ENABLE, fal_port_autoneg_enable), \ - SW_API_DEF(SW_API_PT_AN_RESTART, fal_port_autoneg_restart), \ - SW_API_DEF(SW_API_PT_AN_ADV_GET, fal_port_autoneg_adv_get), \ - SW_API_DEF(SW_API_PT_AN_ADV_SET, fal_port_autoneg_adv_set), \ -/*qca808x_end*/\ - SW_API_DEF(SW_API_PT_HDR_SET, fal_port_hdr_status_set), \ - SW_API_DEF(SW_API_PT_HDR_GET, fal_port_hdr_status_get), \ - SW_API_DEF(SW_API_PT_FLOWCTRL_SET, fal_port_flowctrl_set), \ - SW_API_DEF(SW_API_PT_FLOWCTRL_GET, fal_port_flowctrl_get), \ - SW_API_DEF(SW_API_PT_FLOWCTRL_MODE_SET, fal_port_flowctrl_forcemode_set), \ - SW_API_DEF(SW_API_PT_FLOWCTRL_MODE_GET, fal_port_flowctrl_forcemode_get), \ - SW_API_DEF(SW_API_PT_POWERSAVE_SET, fal_port_powersave_set), \ - SW_API_DEF(SW_API_PT_POWERSAVE_GET, fal_port_powersave_get), \ -/*qca808x_start*/\ - SW_API_DEF(SW_API_PT_HIBERNATE_SET, fal_port_hibernate_set), \ - SW_API_DEF(SW_API_PT_HIBERNATE_GET, fal_port_hibernate_get), \ - SW_API_DEF(SW_API_PT_CDT, fal_port_cdt), \ -/*qca808x_end*/\ - SW_API_DEF(SW_API_PT_TXHDR_SET, fal_port_txhdr_mode_set), \ - SW_API_DEF(SW_API_PT_TXHDR_GET, fal_port_txhdr_mode_get), \ - SW_API_DEF(SW_API_PT_RXHDR_SET, fal_port_rxhdr_mode_set), \ - SW_API_DEF(SW_API_PT_RXHDR_GET, fal_port_rxhdr_mode_get), \ - SW_API_DEF(SW_API_HEADER_TYPE_SET, fal_header_type_set), \ - SW_API_DEF(SW_API_HEADER_TYPE_GET, fal_header_type_get), \ - SW_API_DEF(SW_API_TXMAC_STATUS_SET, fal_port_txmac_status_set), \ - SW_API_DEF(SW_API_TXMAC_STATUS_GET, fal_port_txmac_status_get), \ - SW_API_DEF(SW_API_RXMAC_STATUS_SET, fal_port_rxmac_status_set), \ - SW_API_DEF(SW_API_RXMAC_STATUS_GET, fal_port_rxmac_status_get), \ - SW_API_DEF(SW_API_TXFC_STATUS_SET, fal_port_txfc_status_set), \ - SW_API_DEF(SW_API_TXFC_STATUS_GET, fal_port_txfc_status_get), \ - SW_API_DEF(SW_API_RXFC_STATUS_SET, fal_port_rxfc_status_set), \ - SW_API_DEF(SW_API_RXFC_STATUS_GET, fal_port_rxfc_status_get), \ - SW_API_DEF(SW_API_BP_STATUS_SET, fal_port_bp_status_set), \ - SW_API_DEF(SW_API_BP_STATUS_GET, fal_port_bp_status_get), \ - SW_API_DEF(SW_API_PT_LINK_MODE_SET, fal_port_link_forcemode_set), \ - SW_API_DEF(SW_API_PT_LINK_MODE_GET, fal_port_link_forcemode_get), \ -/*qca808x_start*/\ - SW_API_DEF(SW_API_PT_LINK_STATUS_GET, fal_port_link_status_get), \ -/*qca808x_end*/\ - SW_API_DEF(SW_API_PT_MAC_LOOPBACK_SET, fal_port_mac_loopback_set), \ - SW_API_DEF(SW_API_PT_MAC_LOOPBACK_GET, fal_port_mac_loopback_get), \ - SW_API_DEF(SW_API_PTS_LINK_STATUS_GET, fal_ports_link_status_get), \ - SW_API_DEF(SW_API_PT_CONGESTION_DROP_SET, fal_port_congestion_drop_set), \ - SW_API_DEF(SW_API_PT_CONGESTION_DROP_GET, fal_port_congestion_drop_get), \ - SW_API_DEF(SW_API_PT_RING_FLOW_CTRL_THRES_SET, fal_ring_flow_ctrl_thres_set), \ - SW_API_DEF(SW_API_PT_RING_FLOW_CTRL_THRES_GET, fal_ring_flow_ctrl_thres_get), \ -/*qca808x_start*/\ - SW_API_DEF(SW_API_PT_8023AZ_SET, fal_port_8023az_set), \ - SW_API_DEF(SW_API_PT_8023AZ_GET, fal_port_8023az_get), \ - SW_API_DEF(SW_API_PT_MDIX_SET, fal_port_mdix_set), \ - SW_API_DEF(SW_API_PT_MDIX_GET, fal_port_mdix_get), \ - SW_API_DEF(SW_API_PT_MDIX_STATUS_GET, fal_port_mdix_status_get), \ -/*qca808x_end*/\ - SW_API_DEF(SW_API_PT_COMBO_PREFER_MEDIUM_SET, fal_port_combo_prefer_medium_set), \ - SW_API_DEF(SW_API_PT_COMBO_PREFER_MEDIUM_GET, fal_port_combo_prefer_medium_get), \ - SW_API_DEF(SW_API_PT_COMBO_MEDIUM_STATUS_GET, fal_port_combo_medium_status_get), \ - SW_API_DEF(SW_API_PT_COMBO_FIBER_MODE_SET, fal_port_combo_fiber_mode_set), \ - SW_API_DEF(SW_API_PT_COMBO_FIBER_MODE_GET, fal_port_combo_fiber_mode_get), \ -/*qca808x_start*/\ - SW_API_DEF(SW_API_PT_LOCAL_LOOPBACK_SET, fal_port_local_loopback_set), \ - SW_API_DEF(SW_API_PT_LOCAL_LOOPBACK_GET, fal_port_local_loopback_get), \ - SW_API_DEF(SW_API_PT_REMOTE_LOOPBACK_SET, fal_port_remote_loopback_set), \ - SW_API_DEF(SW_API_PT_REMOTE_LOOPBACK_GET, fal_port_remote_loopback_get), \ - SW_API_DEF(SW_API_PT_RESET, fal_port_reset), \ - SW_API_DEF(SW_API_PT_POWER_OFF, fal_port_power_off), \ - SW_API_DEF(SW_API_PT_POWER_ON, fal_port_power_on), \ - SW_API_DEF(SW_API_PT_MAGIC_FRAME_MAC_SET, fal_port_magic_frame_mac_set), \ - SW_API_DEF(SW_API_PT_MAGIC_FRAME_MAC_GET, fal_port_magic_frame_mac_get), \ - SW_API_DEF(SW_API_PT_PHY_ID_GET, fal_port_phy_id_get), \ - SW_API_DEF(SW_API_PT_WOL_STATUS_SET, fal_port_wol_status_set), \ - SW_API_DEF(SW_API_PT_WOL_STATUS_GET, fal_port_wol_status_get), \ -/*qca808x_end*/\ - SW_API_DEF(SW_API_PT_INTERFACE_MODE_SET, fal_port_interface_mode_set), \ - SW_API_DEF(SW_API_PT_INTERFACE_MODE_APPLY, fal_port_interface_mode_apply), \ - SW_API_DEF(SW_API_PT_INTERFACE_MODE_GET, fal_port_interface_mode_get), \ -/*qca808x_start*/\ - SW_API_DEF(SW_API_PT_INTERFACE_MODE_STATUS_GET, fal_port_interface_mode_status_get), \ - SW_API_DEF(SW_API_DEBUG_PHYCOUNTER_SET, fal_debug_phycounter_set), \ - SW_API_DEF(SW_API_DEBUG_PHYCOUNTER_GET, fal_debug_phycounter_get), \ - SW_API_DEF(SW_API_DEBUG_PHYCOUNTER_SHOW, fal_debug_phycounter_show),\ -/*qca808x_end*/\ - SW_API_DEF(SW_API_PT_MTU_SET, fal_port_mtu_set), \ - SW_API_DEF(SW_API_PT_MTU_GET, fal_port_mtu_get), \ - SW_API_DEF(SW_API_PT_MRU_SET, fal_port_mru_set), \ - SW_API_DEF(SW_API_PT_MRU_GET, fal_port_mru_get), \ - SW_API_DEF(SW_API_PT_SOURCE_FILTER_GET, fal_port_source_filter_status_get), \ - SW_API_DEF(SW_API_PT_SOURCE_FILTER_SET, fal_port_source_filter_enable), \ - SW_API_DEF(SW_API_PT_FRAME_MAX_SIZE_GET, fal_port_max_frame_size_get), \ - SW_API_DEF(SW_API_PT_FRAME_MAX_SIZE_SET, fal_port_max_frame_size_set), \ - SW_API_DEF(SW_API_PT_INTERFACE_3AZ_STATUS_SET, fal_port_interface_3az_status_set), \ - SW_API_DEF(SW_API_PT_INTERFACE_3AZ_STATUS_GET, fal_port_interface_3az_status_get), \ - SW_API_DEF(SW_API_PT_PROMISC_MODE_SET, fal_port_promisc_mode_set), \ - SW_API_DEF(SW_API_PT_PROMISC_MODE_GET, fal_port_promisc_mode_get), \ - SW_API_DEF(SW_API_PT_INTERFACE_EEE_CFG_SET, fal_port_interface_eee_cfg_set), \ - SW_API_DEF(SW_API_PT_INTERFACE_EEE_CFG_GET, fal_port_interface_eee_cfg_get), \ - SW_API_DEF(SW_API_PT_SOURCE_FILTER_CONFIG_GET, fal_port_source_filter_config_get), \ - SW_API_DEF(SW_API_PT_SOURCE_FILTER_CONFIG_SET, fal_port_source_filter_config_set), \ - SW_API_DEF(SW_API_PT_SWITCH_PORT_LOOPBACK_SET, fal_switch_port_loopback_set), \ - SW_API_DEF(SW_API_PT_SWITCH_PORT_LOOPBACK_GET, fal_switch_port_loopback_get), -/*qca808x_start*/ -/*end of PORTCONTROL_API*/ -#define PORTCONTROL_API_PARAM \ - SW_API_DESC(SW_API_PT_DUPLEX_GET) \ - SW_API_DESC(SW_API_PT_DUPLEX_SET) \ - SW_API_DESC(SW_API_PT_SPEED_GET) \ - SW_API_DESC(SW_API_PT_SPEED_SET) \ - SW_API_DESC(SW_API_PT_AN_GET) \ - SW_API_DESC(SW_API_PT_AN_ENABLE) \ - SW_API_DESC(SW_API_PT_AN_RESTART) \ - SW_API_DESC(SW_API_PT_AN_ADV_GET) \ - SW_API_DESC(SW_API_PT_AN_ADV_SET) \ -/*qca808x_end*/\ - SW_API_DESC(SW_API_PT_HDR_SET) \ - SW_API_DESC(SW_API_PT_HDR_GET) \ - SW_API_DESC(SW_API_PT_FLOWCTRL_SET) \ - SW_API_DESC(SW_API_PT_FLOWCTRL_GET) \ - SW_API_DESC(SW_API_PT_FLOWCTRL_MODE_SET) \ - SW_API_DESC(SW_API_PT_FLOWCTRL_MODE_GET) \ - SW_API_DESC(SW_API_PT_POWERSAVE_SET) \ - SW_API_DESC(SW_API_PT_POWERSAVE_GET) \ -/*qca808x_start*/\ - SW_API_DESC(SW_API_PT_HIBERNATE_SET) \ - SW_API_DESC(SW_API_PT_HIBERNATE_GET) \ - SW_API_DESC(SW_API_PT_CDT) \ -/*qca808x_end*/\ - SW_API_DESC(SW_API_PT_TXHDR_SET) \ - SW_API_DESC(SW_API_PT_TXHDR_GET) \ - SW_API_DESC(SW_API_PT_RXHDR_SET) \ - SW_API_DESC(SW_API_PT_RXHDR_GET) \ - SW_API_DESC(SW_API_HEADER_TYPE_SET) \ - SW_API_DESC(SW_API_HEADER_TYPE_GET) \ - SW_API_DESC(SW_API_TXMAC_STATUS_SET) \ - SW_API_DESC(SW_API_TXMAC_STATUS_GET) \ - SW_API_DESC(SW_API_RXMAC_STATUS_SET) \ - SW_API_DESC(SW_API_RXMAC_STATUS_GET) \ - SW_API_DESC(SW_API_TXFC_STATUS_SET) \ - SW_API_DESC(SW_API_TXFC_STATUS_GET) \ - SW_API_DESC(SW_API_RXFC_STATUS_SET) \ - SW_API_DESC(SW_API_RXFC_STATUS_GET) \ - SW_API_DESC(SW_API_BP_STATUS_SET) \ - SW_API_DESC(SW_API_BP_STATUS_GET) \ - SW_API_DESC(SW_API_PT_LINK_MODE_SET) \ - SW_API_DESC(SW_API_PT_LINK_MODE_GET) \ -/*qca808x_start*/\ - SW_API_DESC(SW_API_PT_LINK_STATUS_GET) \ -/*qca808x_end*/\ - SW_API_DESC(SW_API_PT_MAC_LOOPBACK_SET) \ - SW_API_DESC(SW_API_PT_MAC_LOOPBACK_GET) \ - SW_API_DESC(SW_API_PTS_LINK_STATUS_GET) \ - SW_API_DESC(SW_API_PT_CONGESTION_DROP_SET) \ - SW_API_DESC(SW_API_PT_CONGESTION_DROP_GET) \ - SW_API_DESC(SW_API_PT_RING_FLOW_CTRL_THRES_SET) \ - SW_API_DESC(SW_API_PT_RING_FLOW_CTRL_THRES_GET) \ -/*qca808x_start*/\ - SW_API_DESC(SW_API_PT_8023AZ_SET) \ - SW_API_DESC(SW_API_PT_8023AZ_GET) \ - SW_API_DESC(SW_API_PT_MDIX_SET) \ - SW_API_DESC(SW_API_PT_MDIX_GET) \ - SW_API_DESC(SW_API_PT_MDIX_STATUS_GET) \ -/*qca808x_end*/\ - SW_API_DESC(SW_API_PT_COMBO_PREFER_MEDIUM_SET) \ - SW_API_DESC(SW_API_PT_COMBO_PREFER_MEDIUM_GET) \ - SW_API_DESC(SW_API_PT_COMBO_MEDIUM_STATUS_GET) \ - SW_API_DESC(SW_API_PT_COMBO_FIBER_MODE_SET) \ - SW_API_DESC(SW_API_PT_COMBO_FIBER_MODE_GET) \ -/*qca808x_start*/\ - SW_API_DESC(SW_API_PT_LOCAL_LOOPBACK_SET) \ - SW_API_DESC(SW_API_PT_LOCAL_LOOPBACK_GET) \ - SW_API_DESC(SW_API_PT_REMOTE_LOOPBACK_SET) \ - SW_API_DESC(SW_API_PT_REMOTE_LOOPBACK_GET) \ - SW_API_DESC(SW_API_PT_RESET) \ - SW_API_DESC(SW_API_PT_POWER_OFF) \ - SW_API_DESC(SW_API_PT_POWER_ON) \ - SW_API_DESC(SW_API_PT_MAGIC_FRAME_MAC_SET) \ - SW_API_DESC(SW_API_PT_MAGIC_FRAME_MAC_GET) \ - SW_API_DESC(SW_API_PT_PHY_ID_GET) \ - SW_API_DESC(SW_API_PT_WOL_STATUS_SET) \ - SW_API_DESC(SW_API_PT_WOL_STATUS_GET) \ -/*qca808x_end*/\ - SW_API_DESC(SW_API_PT_INTERFACE_MODE_SET) \ - SW_API_DESC(SW_API_PT_INTERFACE_MODE_GET) \ - SW_API_DESC(SW_API_PT_INTERFACE_MODE_APPLY) \ -/*qca808x_start*/\ - SW_API_DESC(SW_API_PT_INTERFACE_MODE_STATUS_GET) \ - SW_API_DESC(SW_API_DEBUG_PHYCOUNTER_SET) \ - SW_API_DESC(SW_API_DEBUG_PHYCOUNTER_GET) \ - SW_API_DESC(SW_API_DEBUG_PHYCOUNTER_SHOW) \ -/*qca808x_end*/\ - SW_API_DESC(SW_API_PT_MTU_SET) \ - SW_API_DESC(SW_API_PT_MTU_GET) \ - SW_API_DESC(SW_API_PT_MRU_SET) \ - SW_API_DESC(SW_API_PT_MRU_GET) \ - SW_API_DESC(SW_API_PT_SOURCE_FILTER_GET) \ - SW_API_DESC(SW_API_PT_SOURCE_FILTER_SET) \ - SW_API_DESC(SW_API_PT_FRAME_MAX_SIZE_GET) \ - SW_API_DESC(SW_API_PT_FRAME_MAX_SIZE_SET) \ - SW_API_DESC(SW_API_PT_INTERFACE_3AZ_STATUS_SET) \ - SW_API_DESC(SW_API_PT_INTERFACE_3AZ_STATUS_GET) \ - SW_API_DESC(SW_API_PT_PROMISC_MODE_SET) \ - SW_API_DESC(SW_API_PT_PROMISC_MODE_GET) \ - SW_API_DESC(SW_API_PT_INTERFACE_EEE_CFG_SET) \ - SW_API_DESC(SW_API_PT_INTERFACE_EEE_CFG_GET) \ - SW_API_DESC(SW_API_PT_SOURCE_FILTER_CONFIG_GET) \ - SW_API_DESC(SW_API_PT_SOURCE_FILTER_CONFIG_SET) \ - SW_API_DESC(SW_API_PT_SWITCH_PORT_LOOPBACK_SET) \ - SW_API_DESC(SW_API_PT_SWITCH_PORT_LOOPBACK_GET) -/*qca808x_start*/ -/*end of PORTCONTROL_API_PARAM*/ -/*qca808x_end*/ -#else -#define PORTCONTROL_API \ - SW_API_DEF(SW_API_PT_DUPLEX_SET, fal_port_duplex_set), \ - SW_API_DEF(SW_API_PT_SPEED_SET, fal_port_speed_set), \ - SW_API_DEF(SW_API_PT_AN_ENABLE, fal_port_autoneg_enable), \ - SW_API_DEF(SW_API_PT_AN_RESTART, fal_port_autoneg_restart), \ - SW_API_DEF(SW_API_PT_AN_ADV_SET, fal_port_autoneg_adv_set), \ - SW_API_DEF(SW_API_PT_LINK_MODE_SET, fal_port_link_forcemode_set), \ - SW_API_DEF(SW_API_PT_TXHDR_SET, fal_port_txhdr_mode_set), \ - SW_API_DEF(SW_API_PT_RXHDR_SET, fal_port_rxhdr_mode_set), \ - SW_API_DEF(SW_API_HEADER_TYPE_SET, fal_header_type_set), \ - SW_API_DEF(SW_API_TXMAC_STATUS_SET, fal_port_txmac_status_set), \ - SW_API_DEF(SW_API_RXMAC_STATUS_SET, fal_port_rxmac_status_set), \ - SW_API_DEF(SW_API_PT_POWER_OFF, fal_port_power_off), \ - SW_API_DEF(SW_API_PT_POWER_ON, fal_port_power_on), \ - SW_API_DEF(SW_API_TXFC_STATUS_SET, fal_port_txfc_status_set), \ - SW_API_DEF(SW_API_RXFC_STATUS_SET, fal_port_rxfc_status_set), \ - SW_API_DEF(SW_API_PT_SWITCH_PORT_LOOPBACK_SET, fal_switch_port_loopback_set), \ - SW_API_DEF(SW_API_PT_SWITCH_PORT_LOOPBACK_GET, fal_switch_port_loopback_get), -/*end of PORTCONTROL_API*/ -#define PORTCONTROL_API_PARAM \ - SW_API_DESC(SW_API_PT_DUPLEX_SET) \ - SW_API_DESC(SW_API_PT_SPEED_SET) \ - SW_API_DESC(SW_API_PT_AN_ENABLE) \ - SW_API_DESC(SW_API_PT_AN_RESTART) \ - SW_API_DESC(SW_API_PT_AN_ADV_SET) \ - SW_API_DESC(SW_API_PT_LINK_MODE_SET) \ - SW_API_DESC(SW_API_PT_TXHDR_SET) \ - SW_API_DESC(SW_API_PT_RXHDR_SET) \ - SW_API_DESC(SW_API_HEADER_TYPE_SET) \ - SW_API_DESC(SW_API_TXMAC_STATUS_SET) \ - SW_API_DESC(SW_API_RXMAC_STATUS_SET) \ - SW_API_DESC(SW_API_PT_POWER_OFF) \ - SW_API_DESC(SW_API_PT_POWER_ON) \ - SW_API_DESC(SW_API_TXFC_STATUS_SET) \ - SW_API_DESC(SW_API_RXFC_STATUS_SET) \ - SW_API_DESC(SW_API_PT_SWITCH_PORT_LOOPBACK_SET) \ - SW_API_DESC(SW_API_PT_SWITCH_PORT_LOOPBACK_GET) -/*end of PORTCONTROL_API_PARAM*/ -#endif - -#else -#define PORTCONTROL_API -#define PORTCONTROL_API_PARAM -#endif -#ifdef IN_VLAN -#define VLAN_API \ - SW_API_DEF(SW_API_VLAN_ADD, fal_vlan_create), \ - SW_API_DEF(SW_API_VLAN_DEL, fal_vlan_delete), \ - SW_API_DEF(SW_API_VLAN_MEM_UPDATE, fal_vlan_member_update), \ - SW_API_DEF(SW_API_VLAN_FIND, fal_vlan_find), \ - SW_API_DEF(SW_API_VLAN_NEXT, fal_vlan_next), \ - SW_API_DEF(SW_API_VLAN_APPEND, fal_vlan_entry_append), \ - SW_API_DEF(SW_API_VLAN_FLUSH, fal_vlan_flush), \ - SW_API_DEF(SW_API_VLAN_FID_SET, fal_vlan_fid_set), \ - SW_API_DEF(SW_API_VLAN_FID_GET, fal_vlan_fid_get), \ - SW_API_DEF(SW_API_VLAN_MEMBER_ADD, fal_vlan_member_add), \ - SW_API_DEF(SW_API_VLAN_MEMBER_DEL, fal_vlan_member_del), \ - SW_API_DEF(SW_API_VLAN_LEARN_STATE_SET, fal_vlan_learning_state_set), \ - SW_API_DEF(SW_API_VLAN_LEARN_STATE_GET, fal_vlan_learning_state_get), - -#define VLAN_API_PARAM \ - SW_API_DESC(SW_API_VLAN_ADD) \ - SW_API_DESC(SW_API_VLAN_DEL) \ - SW_API_DESC(SW_API_VLAN_MEM_UPDATE) \ - SW_API_DESC(SW_API_VLAN_FIND) \ - SW_API_DESC(SW_API_VLAN_NEXT) \ - SW_API_DESC(SW_API_VLAN_APPEND) \ - SW_API_DESC(SW_API_VLAN_FLUSH) \ - SW_API_DESC(SW_API_VLAN_FID_SET) \ - SW_API_DESC(SW_API_VLAN_FID_GET) \ - SW_API_DESC(SW_API_VLAN_MEMBER_ADD) \ - SW_API_DESC(SW_API_VLAN_MEMBER_DEL) \ - SW_API_DESC(SW_API_VLAN_LEARN_STATE_SET) \ - SW_API_DESC(SW_API_VLAN_LEARN_STATE_GET) -#else -#define VLAN_API -#define VLAN_API_PARAM -#endif - -#ifdef IN_PORTVLAN -#ifndef IN_PORTVLAN_MINI -#define PORTVLAN_API \ - SW_API_DEF(SW_API_PT_ING_MODE_GET, fal_port_1qmode_get), \ - SW_API_DEF(SW_API_PT_ING_MODE_SET, fal_port_1qmode_set), \ - SW_API_DEF(SW_API_PT_EG_MODE_GET, fal_port_egvlanmode_get), \ - SW_API_DEF(SW_API_PT_EG_MODE_SET, fal_port_egvlanmode_set), \ - SW_API_DEF(SW_API_PT_VLAN_MEM_ADD, fal_portvlan_member_add), \ - SW_API_DEF(SW_API_PT_VLAN_MEM_DEL, fal_portvlan_member_del), \ - SW_API_DEF(SW_API_PT_VLAN_MEM_UPDATE, fal_portvlan_member_update), \ - SW_API_DEF(SW_API_PT_VLAN_MEM_GET, fal_portvlan_member_get), \ - SW_API_DEF(SW_API_PT_DEF_VID_SET, fal_port_default_vid_set), \ - SW_API_DEF(SW_API_PT_DEF_VID_GET, fal_port_default_vid_get), \ - SW_API_DEF(SW_API_PT_FORCE_DEF_VID_SET, fal_port_force_default_vid_set), \ - SW_API_DEF(SW_API_PT_FORCE_DEF_VID_GET, fal_port_force_default_vid_get), \ - SW_API_DEF(SW_API_PT_FORCE_PORTVLAN_SET, fal_port_force_portvlan_set), \ - SW_API_DEF(SW_API_PT_FORCE_PORTVLAN_GET, fal_port_force_portvlan_get), \ - SW_API_DEF(SW_API_PT_NESTVLAN_SET, fal_port_nestvlan_set), \ - SW_API_DEF(SW_API_PT_NESTVLAN_GET, fal_port_nestvlan_get), \ - SW_API_DEF(SW_API_NESTVLAN_TPID_SET, fal_nestvlan_tpid_set), \ - SW_API_DEF(SW_API_NESTVLAN_TPID_GET, fal_nestvlan_tpid_get), \ - SW_API_DEF(SW_API_PT_IN_VLAN_MODE_SET, fal_port_invlan_mode_set), \ - SW_API_DEF(SW_API_PT_IN_VLAN_MODE_GET, fal_port_invlan_mode_get), \ - SW_API_DEF(SW_API_PT_TLS_SET, fal_port_tls_set), \ - SW_API_DEF(SW_API_PT_TLS_GET, fal_port_tls_get), \ - SW_API_DEF(SW_API_PT_PRI_PROPAGATION_SET, fal_port_pri_propagation_set), \ - SW_API_DEF(SW_API_PT_PRI_PROPAGATION_GET, fal_port_pri_propagation_get), \ - SW_API_DEF(SW_API_PT_DEF_SVID_SET, fal_port_default_svid_set), \ - SW_API_DEF(SW_API_PT_DEF_SVID_GET, fal_port_default_svid_get), \ - SW_API_DEF(SW_API_PT_DEF_CVID_SET, fal_port_default_cvid_set), \ - SW_API_DEF(SW_API_PT_DEF_CVID_GET, fal_port_default_cvid_get), \ - SW_API_DEF(SW_API_PT_VLAN_PROPAGATION_SET, fal_port_vlan_propagation_set), \ - SW_API_DEF(SW_API_PT_VLAN_PROPAGATION_GET, fal_port_vlan_propagation_get), \ - SW_API_DEF(SW_API_PT_VLAN_TRANS_ADD, fal_port_vlan_trans_add), \ - SW_API_DEF(SW_API_PT_VLAN_TRANS_DEL, fal_port_vlan_trans_del), \ - SW_API_DEF(SW_API_PT_VLAN_TRANS_GET, fal_port_vlan_trans_get), \ - SW_API_DEF(SW_API_QINQ_MODE_SET, fal_qinq_mode_set), \ - SW_API_DEF(SW_API_QINQ_MODE_GET, fal_qinq_mode_get), \ - SW_API_DEF(SW_API_PT_QINQ_ROLE_SET, fal_port_qinq_role_set), \ - SW_API_DEF(SW_API_PT_QINQ_ROLE_GET, fal_port_qinq_role_get), \ - SW_API_DEF(SW_API_PT_VLAN_TRANS_ITERATE, fal_port_vlan_trans_iterate), \ - SW_API_DEF(SW_API_PT_MAC_VLAN_XLT_SET, fal_port_mac_vlan_xlt_set), \ - SW_API_DEF(SW_API_PT_MAC_VLAN_XLT_GET, fal_port_mac_vlan_xlt_get), \ - SW_API_DEF(SW_API_NETISOLATE_SET, fal_netisolate_set), \ - SW_API_DEF(SW_API_NETISOLATE_GET, fal_netisolate_get), \ - SW_API_DEF(SW_API_EG_FLTR_BYPASS_EN_SET, fal_eg_trans_filter_bypass_en_set), \ - SW_API_DEF(SW_API_EG_FLTR_BYPASS_EN_GET, fal_eg_trans_filter_bypass_en_get), \ - SW_API_DEF(SW_API_PT_VRF_ID_SET, fal_port_vrf_id_set), \ - SW_API_DEF(SW_API_PT_VRF_ID_GET, fal_port_vrf_id_get), \ - SW_API_DEF(SW_API_GLOBAL_QINQ_MODE_SET, fal_global_qinq_mode_set), \ - SW_API_DEF(SW_API_GLOBAL_QINQ_MODE_GET, fal_global_qinq_mode_get), \ - SW_API_DEF(SW_API_PORT_QINQ_MODE_SET, fal_port_qinq_mode_set), \ - SW_API_DEF(SW_API_PORT_QINQ_MODE_GET, fal_port_qinq_mode_get), \ - SW_API_DEF(SW_API_TPID_SET, fal_ingress_tpid_set), \ - SW_API_DEF(SW_API_TPID_GET, fal_ingress_tpid_get), \ - SW_API_DEF(SW_API_EGRESS_TPID_SET, fal_egress_tpid_set), \ - SW_API_DEF(SW_API_EGRESS_TPID_GET, fal_egress_tpid_get), \ - SW_API_DEF(SW_API_PT_INGRESS_VLAN_FILTER_SET, fal_port_ingress_vlan_filter_set), \ - SW_API_DEF(SW_API_PT_INGRESS_VLAN_FILTER_GET, fal_port_ingress_vlan_filter_get), \ - SW_API_DEF(SW_API_PT_DEFAULT_VLANTAG_SET, fal_port_default_vlantag_set), \ - SW_API_DEF(SW_API_PT_DEFAULT_VLANTAG_GET, fal_port_default_vlantag_get), \ - SW_API_DEF(SW_API_PT_TAG_PROPAGATION_SET, fal_port_tag_propagation_set), \ - SW_API_DEF(SW_API_PT_TAG_PROPAGATION_GET, fal_port_tag_propagation_get), \ - SW_API_DEF(SW_API_PT_VLANTAG_EGMODE_SET, fal_port_vlantag_egmode_set), \ - SW_API_DEF(SW_API_PT_VLANTAG_EGMODE_GET, fal_port_vlantag_egmode_get), \ - SW_API_DEF(SW_API_PT_VLAN_XLT_MISS_CMD_SET, fal_port_vlan_xlt_miss_cmd_set), \ - SW_API_DEF(SW_API_PT_VLAN_XLT_MISS_CMD_GET, fal_port_vlan_xlt_miss_cmd_get), \ - SW_API_DEF(SW_API_PT_VSI_EGMODE_SET, fal_port_vsi_egmode_set), \ - SW_API_DEF(SW_API_PT_VSI_EGMODE_GET, fal_port_vsi_egmode_get), \ - SW_API_DEF(SW_API_PT_VLANTAG_VSI_EGMODE_EN_SET, fal_port_vlantag_vsi_egmode_enable), \ - SW_API_DEF(SW_API_PT_VLANTAG_VSI_EGMODE_EN_GET, fal_port_vlantag_vsi_egmode_status_get), \ - SW_API_DEF(SW_API_PT_VLAN_TRANS_ADV_ADD, fal_port_vlan_trans_adv_add), \ - SW_API_DEF(SW_API_PT_VLAN_TRANS_ADV_DEL, fal_port_vlan_trans_adv_del), \ - SW_API_DEF(SW_API_PT_VLAN_TRANS_ADV_GETFIRST, fal_port_vlan_trans_adv_getfirst), \ - SW_API_DEF(SW_API_PT_VLAN_TRANS_ADV_GETNEXT, fal_port_vlan_trans_adv_getnext), \ - SW_API_DEF(SW_API_PT_VLAN_COUNTER_GET, fal_port_vlan_counter_get), \ - SW_API_DEF(SW_API_PT_VLAN_COUNTER_CLEANUP, fal_port_vlan_counter_cleanup), - -#define PORTVLAN_API_PARAM \ - SW_API_DESC(SW_API_PT_ING_MODE_GET) \ - SW_API_DESC(SW_API_PT_ING_MODE_SET) \ - SW_API_DESC(SW_API_PT_EG_MODE_GET) \ - SW_API_DESC(SW_API_PT_EG_MODE_SET) \ - SW_API_DESC(SW_API_PT_VLAN_MEM_ADD) \ - SW_API_DESC(SW_API_PT_VLAN_MEM_DEL) \ - SW_API_DESC(SW_API_PT_VLAN_MEM_UPDATE) \ - SW_API_DESC(SW_API_PT_VLAN_MEM_GET) \ - SW_API_DESC(SW_API_PT_DEF_VID_SET) \ - SW_API_DESC(SW_API_PT_DEF_VID_GET) \ - SW_API_DESC(SW_API_PT_FORCE_DEF_VID_SET) \ - SW_API_DESC(SW_API_PT_FORCE_DEF_VID_GET) \ - SW_API_DESC(SW_API_PT_FORCE_PORTVLAN_SET) \ - SW_API_DESC(SW_API_PT_FORCE_PORTVLAN_GET) \ - SW_API_DESC(SW_API_PT_NESTVLAN_SET) \ - SW_API_DESC(SW_API_PT_NESTVLAN_GET) \ - SW_API_DESC(SW_API_NESTVLAN_TPID_SET) \ - SW_API_DESC(SW_API_NESTVLAN_TPID_GET) \ - SW_API_DESC(SW_API_PT_IN_VLAN_MODE_SET) \ - SW_API_DESC(SW_API_PT_IN_VLAN_MODE_GET) \ - SW_API_DESC(SW_API_PT_TLS_SET) \ - SW_API_DESC(SW_API_PT_TLS_GET) \ - SW_API_DESC(SW_API_PT_PRI_PROPAGATION_SET) \ - SW_API_DESC(SW_API_PT_PRI_PROPAGATION_GET) \ - SW_API_DESC(SW_API_PT_DEF_SVID_SET) \ - SW_API_DESC(SW_API_PT_DEF_SVID_GET) \ - SW_API_DESC(SW_API_PT_DEF_CVID_SET) \ - SW_API_DESC(SW_API_PT_DEF_CVID_GET) \ - SW_API_DESC(SW_API_PT_VLAN_PROPAGATION_SET) \ - SW_API_DESC(SW_API_PT_VLAN_PROPAGATION_GET) \ - SW_API_DESC(SW_API_PT_VLAN_TRANS_ADD) \ - SW_API_DESC(SW_API_PT_VLAN_TRANS_DEL) \ - SW_API_DESC(SW_API_PT_VLAN_TRANS_GET) \ - SW_API_DESC(SW_API_QINQ_MODE_SET) \ - SW_API_DESC(SW_API_QINQ_MODE_GET) \ - SW_API_DESC(SW_API_PT_QINQ_ROLE_SET) \ - SW_API_DESC(SW_API_PT_QINQ_ROLE_GET) \ - SW_API_DESC(SW_API_PT_VLAN_TRANS_ITERATE) \ - SW_API_DESC(SW_API_PT_MAC_VLAN_XLT_SET) \ - SW_API_DESC(SW_API_PT_MAC_VLAN_XLT_GET) \ - SW_API_DESC(SW_API_NETISOLATE_SET) \ - SW_API_DESC(SW_API_NETISOLATE_GET) \ - SW_API_DESC(SW_API_EG_FLTR_BYPASS_EN_SET) \ - SW_API_DESC(SW_API_EG_FLTR_BYPASS_EN_GET) \ - SW_API_DESC(SW_API_PT_VRF_ID_SET) \ - SW_API_DESC(SW_API_PT_VRF_ID_GET) \ - SW_API_DESC(SW_API_GLOBAL_QINQ_MODE_SET) \ - SW_API_DESC(SW_API_GLOBAL_QINQ_MODE_GET) \ - SW_API_DESC(SW_API_PORT_QINQ_MODE_SET) \ - SW_API_DESC(SW_API_PORT_QINQ_MODE_GET) \ - SW_API_DESC(SW_API_TPID_SET) \ - SW_API_DESC(SW_API_TPID_GET) \ - SW_API_DESC(SW_API_EGRESS_TPID_SET) \ - SW_API_DESC(SW_API_EGRESS_TPID_GET) \ - SW_API_DESC(SW_API_PT_INGRESS_VLAN_FILTER_SET) \ - SW_API_DESC(SW_API_PT_INGRESS_VLAN_FILTER_GET) \ - SW_API_DESC(SW_API_PT_DEFAULT_VLANTAG_SET) \ - SW_API_DESC(SW_API_PT_DEFAULT_VLANTAG_GET) \ - SW_API_DESC(SW_API_PT_TAG_PROPAGATION_SET) \ - SW_API_DESC(SW_API_PT_TAG_PROPAGATION_GET) \ - SW_API_DESC(SW_API_PT_VLANTAG_EGMODE_SET) \ - SW_API_DESC(SW_API_PT_VLANTAG_EGMODE_GET) \ - SW_API_DESC(SW_API_PT_VLAN_XLT_MISS_CMD_SET) \ - SW_API_DESC(SW_API_PT_VLAN_XLT_MISS_CMD_GET) \ - SW_API_DESC(SW_API_PT_VSI_EGMODE_SET) \ - SW_API_DESC(SW_API_PT_VSI_EGMODE_GET) \ - SW_API_DESC(SW_API_PT_VLANTAG_VSI_EGMODE_EN_SET) \ - SW_API_DESC(SW_API_PT_VLANTAG_VSI_EGMODE_EN_GET) \ - SW_API_DESC(SW_API_PT_VLAN_TRANS_ADV_ADD) \ - SW_API_DESC(SW_API_PT_VLAN_TRANS_ADV_DEL) \ - SW_API_DESC(SW_API_PT_VLAN_TRANS_ADV_GETFIRST) \ - SW_API_DESC(SW_API_PT_VLAN_TRANS_ADV_GETNEXT) \ - SW_API_DESC(SW_API_PT_VLAN_COUNTER_GET) \ - SW_API_DESC(SW_API_PT_VLAN_COUNTER_CLEANUP) - -#else -#define PORTVLAN_API \ - SW_API_DEF(SW_API_GLOBAL_QINQ_MODE_SET, fal_global_qinq_mode_set), \ - SW_API_DEF(SW_API_GLOBAL_QINQ_MODE_GET, fal_global_qinq_mode_get), \ - SW_API_DEF(SW_API_PORT_QINQ_MODE_SET, fal_port_qinq_mode_set), \ - SW_API_DEF(SW_API_PORT_QINQ_MODE_GET, fal_port_qinq_mode_get), \ - SW_API_DEF(SW_API_QINQ_MODE_SET, fal_qinq_mode_set), \ - SW_API_DEF(SW_API_PT_QINQ_ROLE_SET, fal_port_qinq_role_set), \ - SW_API_DEF(SW_API_PT_VLAN_TRANS_ADD, fal_port_vlan_trans_add), \ - SW_API_DEF(SW_API_TPID_SET, fal_ingress_tpid_set), \ - SW_API_DEF(SW_API_TPID_GET, fal_ingress_tpid_get), \ - SW_API_DEF(SW_API_EGRESS_TPID_SET, fal_egress_tpid_set), \ - SW_API_DEF(SW_API_EGRESS_TPID_GET, fal_egress_tpid_get), \ - SW_API_DEF(SW_API_PT_INGRESS_VLAN_FILTER_SET, fal_port_ingress_vlan_filter_set), \ - SW_API_DEF(SW_API_PT_INGRESS_VLAN_FILTER_GET, fal_port_ingress_vlan_filter_get), \ - SW_API_DEF(SW_API_PT_DEFAULT_VLANTAG_SET, fal_port_default_vlantag_set), \ - SW_API_DEF(SW_API_PT_DEFAULT_VLANTAG_GET, fal_port_default_vlantag_get), \ - SW_API_DEF(SW_API_PT_TAG_PROPAGATION_SET, fal_port_tag_propagation_set), \ - SW_API_DEF(SW_API_PT_TAG_PROPAGATION_GET, fal_port_tag_propagation_get), \ - SW_API_DEF(SW_API_PT_VLANTAG_EGMODE_SET, fal_port_vlantag_egmode_set), \ - SW_API_DEF(SW_API_PT_VLANTAG_EGMODE_GET, fal_port_vlantag_egmode_get), \ - SW_API_DEF(SW_API_PT_VLAN_XLT_MISS_CMD_SET, fal_port_vlan_xlt_miss_cmd_set), \ - SW_API_DEF(SW_API_PT_VLAN_XLT_MISS_CMD_GET, fal_port_vlan_xlt_miss_cmd_get), \ - SW_API_DEF(SW_API_PT_VSI_EGMODE_SET, fal_port_vsi_egmode_set), \ - SW_API_DEF(SW_API_PT_VSI_EGMODE_GET, fal_port_vsi_egmode_get), \ - SW_API_DEF(SW_API_PT_VLANTAG_VSI_EGMODE_EN_SET, fal_port_vlantag_vsi_egmode_enable), \ - SW_API_DEF(SW_API_PT_VLANTAG_VSI_EGMODE_EN_GET, fal_port_vlantag_vsi_egmode_status_get), \ - SW_API_DEF(SW_API_PT_VLAN_TRANS_ADV_ADD, fal_port_vlan_trans_adv_add), \ - SW_API_DEF(SW_API_PT_VLAN_TRANS_ADV_DEL, fal_port_vlan_trans_adv_del), \ - SW_API_DEF(SW_API_PT_VLAN_TRANS_ADV_GETFIRST, fal_port_vlan_trans_adv_getfirst), \ - SW_API_DEF(SW_API_PT_VLAN_TRANS_ADV_GETNEXT, fal_port_vlan_trans_adv_getnext), \ - SW_API_DEF(SW_API_PT_VLAN_COUNTER_GET, fal_port_vlan_counter_get), \ - SW_API_DEF(SW_API_PT_VLAN_COUNTER_CLEANUP, fal_port_vlan_counter_cleanup), \ - SW_API_DEF(SW_API_PT_ING_MODE_SET, fal_port_1qmode_set), \ - SW_API_DEF(SW_API_PT_EG_MODE_SET, fal_port_egvlanmode_set), \ - SW_API_DEF(SW_API_PT_VLAN_MEM_ADD, fal_portvlan_member_add), \ - SW_API_DEF(SW_API_PT_VLAN_MEM_DEL, fal_portvlan_member_del), \ - SW_API_DEF(SW_API_PT_VLAN_MEM_UPDATE, fal_portvlan_member_update), \ - SW_API_DEF(SW_API_PT_DEF_VID_SET, fal_port_default_vid_set), \ - SW_API_DEF(SW_API_PT_FORCE_DEF_VID_SET, fal_port_force_default_vid_set), \ - SW_API_DEF(SW_API_PT_FORCE_PORTVLAN_SET, fal_port_force_portvlan_set), \ - SW_API_DEF(SW_API_PT_NESTVLAN_SET, fal_port_nestvlan_set), \ - SW_API_DEF(SW_API_NESTVLAN_TPID_SET, fal_nestvlan_tpid_set), \ - SW_API_DEF(SW_API_PT_IN_VLAN_MODE_SET, fal_port_invlan_mode_set), \ - SW_API_DEF(SW_API_PT_DEF_SVID_SET, fal_port_default_svid_set), \ - SW_API_DEF(SW_API_PT_DEF_CVID_SET, fal_port_default_cvid_set), - -#define PORTVLAN_API_PARAM \ - SW_API_DESC(SW_API_GLOBAL_QINQ_MODE_SET) \ - SW_API_DESC(SW_API_GLOBAL_QINQ_MODE_GET) \ - SW_API_DESC(SW_API_PORT_QINQ_MODE_SET) \ - SW_API_DESC(SW_API_PORT_QINQ_MODE_GET) \ - SW_API_DESC(SW_API_QINQ_MODE_SET) \ - SW_API_DESC(SW_API_PT_QINQ_ROLE_SET) \ - SW_API_DESC(SW_API_PT_VLAN_TRANS_ADD) \ - SW_API_DESC(SW_API_TPID_SET) \ - SW_API_DESC(SW_API_TPID_GET) \ - SW_API_DESC(SW_API_EGRESS_TPID_SET) \ - SW_API_DESC(SW_API_EGRESS_TPID_GET) \ - SW_API_DESC(SW_API_PT_INGRESS_VLAN_FILTER_SET) \ - SW_API_DESC(SW_API_PT_INGRESS_VLAN_FILTER_GET) \ - SW_API_DESC(SW_API_PT_DEFAULT_VLANTAG_SET) \ - SW_API_DESC(SW_API_PT_DEFAULT_VLANTAG_GET) \ - SW_API_DESC(SW_API_PT_TAG_PROPAGATION_SET) \ - SW_API_DESC(SW_API_PT_TAG_PROPAGATION_GET) \ - SW_API_DESC(SW_API_PT_VLANTAG_EGMODE_SET) \ - SW_API_DESC(SW_API_PT_VLANTAG_EGMODE_GET) \ - SW_API_DESC(SW_API_PT_VLAN_XLT_MISS_CMD_SET) \ - SW_API_DESC(SW_API_PT_VLAN_XLT_MISS_CMD_GET) \ - SW_API_DESC(SW_API_PT_VSI_EGMODE_SET) \ - SW_API_DESC(SW_API_PT_VSI_EGMODE_GET) \ - SW_API_DESC(SW_API_PT_VLANTAG_VSI_EGMODE_EN_SET) \ - SW_API_DESC(SW_API_PT_VLANTAG_VSI_EGMODE_EN_GET) \ - SW_API_DESC(SW_API_PT_VLAN_TRANS_ADV_ADD) \ - SW_API_DESC(SW_API_PT_VLAN_TRANS_ADV_DEL) \ - SW_API_DESC(SW_API_PT_VLAN_TRANS_ADV_GETFIRST) \ - SW_API_DESC(SW_API_PT_VLAN_TRANS_ADV_GETNEXT) \ - SW_API_DESC(SW_API_PT_VLAN_COUNTER_GET) \ - SW_API_DESC(SW_API_PT_VLAN_COUNTER_CLEANUP) \ - SW_API_DESC(SW_API_PT_ING_MODE_SET) \ - SW_API_DESC(SW_API_PT_EG_MODE_SET) \ - SW_API_DESC(SW_API_PT_VLAN_MEM_ADD) \ - SW_API_DESC(SW_API_PT_VLAN_MEM_DEL) \ - SW_API_DESC(SW_API_PT_VLAN_MEM_UPDATE) \ - SW_API_DESC(SW_API_PT_DEF_VID_SET) \ - SW_API_DESC(SW_API_PT_FORCE_DEF_VID_SET) \ - SW_API_DESC(SW_API_PT_FORCE_PORTVLAN_SET) \ - SW_API_DESC(SW_API_PT_NESTVLAN_SET) \ - SW_API_DESC(SW_API_NESTVLAN_TPID_SET) \ - SW_API_DESC(SW_API_PT_IN_VLAN_MODE_SET) \ - SW_API_DESC(SW_API_PT_DEF_SVID_SET) \ - SW_API_DESC(SW_API_PT_DEF_CVID_SET) - -#endif - -#else -#define PORTVLAN_API -#define PORTVLAN_API_PARAM -#endif - -#ifdef IN_FDB -#ifndef IN_FDB_MINI -#define FDB_API \ - SW_API_DEF(SW_API_FDB_ADD, fal_fdb_entry_add), \ - SW_API_DEF(SW_API_FDB_DELALL, fal_fdb_entry_flush), \ - SW_API_DEF(SW_API_FDB_DELPORT,fal_fdb_entry_del_byport), \ - SW_API_DEF(SW_API_FDB_DELMAC, fal_fdb_entry_del_bymac), \ - SW_API_DEF(SW_API_FDB_FIRST, fal_fdb_entry_getfirst), \ - SW_API_DEF(SW_API_FDB_NEXT, fal_fdb_entry_getnext), \ - SW_API_DEF(SW_API_FDB_FIND, fal_fdb_entry_search), \ - SW_API_DEF(SW_API_FDB_PT_LEARN_SET, fal_fdb_port_learn_set), \ - SW_API_DEF(SW_API_FDB_PT_LEARN_GET, fal_fdb_port_learn_get), \ - SW_API_DEF(SW_API_FDB_PT_NEWADDR_LEARN_SET, fal_fdb_port_learning_ctrl_set), \ - SW_API_DEF(SW_API_FDB_PT_NEWADDR_LEARN_GET, fal_fdb_port_learning_ctrl_get), \ - SW_API_DEF(SW_API_FDB_PT_STAMOVE_SET, fal_fdb_port_stamove_ctrl_set), \ - SW_API_DEF(SW_API_FDB_PT_STAMOVE_GET, fal_fdb_port_stamove_ctrl_get), \ - SW_API_DEF(SW_API_FDB_AGE_CTRL_SET, fal_fdb_aging_ctrl_set), \ - SW_API_DEF(SW_API_FDB_AGE_CTRL_GET, fal_fdb_aging_ctrl_get), \ - SW_API_DEF(SW_API_FDB_LEARN_CTRL_SET, fal_fdb_learning_ctrl_set), \ - SW_API_DEF(SW_API_FDB_LEARN_CTRL_GET, fal_fdb_learning_ctrl_get), \ - SW_API_DEF(SW_API_FDB_VLAN_IVL_SVL_SET, fal_fdb_vlan_ivl_svl_set),\ - SW_API_DEF(SW_API_FDB_VLAN_IVL_SVL_GET, fal_fdb_vlan_ivl_svl_get),\ - SW_API_DEF(SW_API_FDB_AGE_TIME_SET, fal_fdb_aging_time_set), \ - SW_API_DEF(SW_API_FDB_AGE_TIME_GET, fal_fdb_aging_time_get), \ - SW_API_DEF(SW_API_FDB_ITERATE, fal_fdb_entry_getnext_byindex), \ - SW_API_DEF(SW_API_FDB_EXTEND_NEXT, fal_fdb_entry_extend_getnext), \ - SW_API_DEF(SW_API_FDB_EXTEND_FIRST, fal_fdb_entry_extend_getfirst), \ - SW_API_DEF(SW_API_FDB_TRANSFER, fal_fdb_entry_update_byport), \ - SW_API_DEF(SW_API_PT_FDB_LEARN_COUNTER_GET, fal_fdb_port_learned_mac_counter_get), \ - SW_API_DEF(SW_API_PT_FDB_LEARN_LIMIT_SET, fal_port_fdb_learn_limit_set), \ - SW_API_DEF(SW_API_PT_FDB_LEARN_LIMIT_GET, fal_port_fdb_learn_limit_get), \ - SW_API_DEF(SW_API_PT_FDB_LEARN_EXCEED_CMD_SET, fal_port_fdb_learn_exceed_cmd_set), \ - SW_API_DEF(SW_API_PT_FDB_LEARN_EXCEED_CMD_GET, fal_port_fdb_learn_exceed_cmd_get), \ - SW_API_DEF(SW_API_FDB_LEARN_LIMIT_SET, fal_fdb_learn_limit_set), \ - SW_API_DEF(SW_API_FDB_LEARN_LIMIT_GET, fal_fdb_learn_limit_get), \ - SW_API_DEF(SW_API_FDB_LEARN_EXCEED_CMD_SET, fal_fdb_learn_exceed_cmd_set), \ - SW_API_DEF(SW_API_FDB_LEARN_EXCEED_CMD_GET, fal_fdb_learn_exceed_cmd_get), \ - SW_API_DEF(SW_API_FDB_RESV_ADD, fal_fdb_resv_add), \ - SW_API_DEF(SW_API_FDB_RESV_DEL, fal_fdb_resv_del), \ - SW_API_DEF(SW_API_FDB_RESV_FIND, fal_fdb_resv_find), \ - SW_API_DEF(SW_API_FDB_RESV_ITERATE, fal_fdb_resv_iterate), \ - SW_API_DEF(SW_API_FDB_PT_LEARN_STATIC_SET, fal_fdb_port_learn_static_set), \ - SW_API_DEF(SW_API_FDB_PT_LEARN_STATIC_GET, fal_fdb_port_learn_static_get), \ - SW_API_DEF(SW_API_FDB_PORT_ADD, fal_fdb_port_add), \ - SW_API_DEF(SW_API_FDB_PORT_DEL, fal_fdb_port_del), \ - SW_API_DEF(SW_API_FDB_RFS_SET, fal_fdb_rfs_set), \ - SW_API_DEF(SW_API_FDB_RFS_DEL, fal_fdb_rfs_del), \ - SW_API_DEF(SW_API_FDB_PT_MACLIMIT_CTRL_SET, fal_fdb_port_maclimit_ctrl_set), \ - SW_API_DEF(SW_API_FDB_PT_MACLIMIT_CTRL_GET, fal_fdb_port_maclimit_ctrl_get), \ - SW_API_DEF(SW_API_FDB_DEL_BY_FID, fal_fdb_entry_del_byfid), - -#define FDB_API_PARAM \ - SW_API_DESC(SW_API_FDB_ADD) \ - SW_API_DESC(SW_API_FDB_DELALL) \ - SW_API_DESC(SW_API_FDB_DELPORT) \ - SW_API_DESC(SW_API_FDB_DELMAC) \ - SW_API_DESC(SW_API_FDB_FIRST) \ - SW_API_DESC(SW_API_FDB_NEXT) \ - SW_API_DESC(SW_API_FDB_FIND) \ - SW_API_DESC(SW_API_FDB_PT_LEARN_SET) \ - SW_API_DESC(SW_API_FDB_PT_LEARN_GET) \ - SW_API_DESC(SW_API_FDB_PT_NEWADDR_LEARN_SET) \ - SW_API_DESC(SW_API_FDB_PT_NEWADDR_LEARN_GET) \ - SW_API_DESC(SW_API_FDB_PT_STAMOVE_SET) \ - SW_API_DESC(SW_API_FDB_PT_STAMOVE_GET) \ - SW_API_DESC(SW_API_FDB_AGE_CTRL_SET) \ - SW_API_DESC(SW_API_FDB_AGE_CTRL_GET) \ - SW_API_DESC(SW_API_FDB_LEARN_CTRL_SET) \ - SW_API_DESC(SW_API_FDB_LEARN_CTRL_GET) \ - SW_API_DESC(SW_API_FDB_VLAN_IVL_SVL_SET) \ - SW_API_DESC(SW_API_FDB_VLAN_IVL_SVL_GET) \ - SW_API_DESC(SW_API_FDB_AGE_TIME_SET) \ - SW_API_DESC(SW_API_FDB_AGE_TIME_GET) \ - SW_API_DESC(SW_API_FDB_ITERATE) \ - SW_API_DESC(SW_API_FDB_EXTEND_NEXT) \ - SW_API_DESC(SW_API_FDB_EXTEND_FIRST) \ - SW_API_DESC(SW_API_FDB_TRANSFER) \ - SW_API_DESC(SW_API_PT_FDB_LEARN_COUNTER_GET) \ - SW_API_DESC(SW_API_PT_FDB_LEARN_LIMIT_SET) \ - SW_API_DESC(SW_API_PT_FDB_LEARN_LIMIT_GET) \ - SW_API_DESC(SW_API_PT_FDB_LEARN_EXCEED_CMD_SET) \ - SW_API_DESC(SW_API_PT_FDB_LEARN_EXCEED_CMD_GET) \ - SW_API_DESC(SW_API_FDB_LEARN_LIMIT_SET) \ - SW_API_DESC(SW_API_FDB_LEARN_LIMIT_GET) \ - SW_API_DESC(SW_API_FDB_LEARN_EXCEED_CMD_SET) \ - SW_API_DESC(SW_API_FDB_LEARN_EXCEED_CMD_GET) \ - SW_API_DESC(SW_API_FDB_RESV_ADD) \ - SW_API_DESC(SW_API_FDB_RESV_DEL) \ - SW_API_DESC(SW_API_FDB_RESV_FIND) \ - SW_API_DESC(SW_API_FDB_RESV_ITERATE) \ - SW_API_DESC(SW_API_FDB_PT_LEARN_STATIC_SET) \ - SW_API_DESC(SW_API_FDB_PT_LEARN_STATIC_GET) \ - SW_API_DESC(SW_API_FDB_PORT_ADD) \ - SW_API_DESC(SW_API_FDB_PORT_DEL) \ - SW_API_DESC(SW_API_FDB_RFS_SET) \ - SW_API_DESC(SW_API_FDB_RFS_DEL) \ - SW_API_DESC(SW_API_FDB_PT_MACLIMIT_CTRL_SET) \ - SW_API_DESC(SW_API_FDB_PT_MACLIMIT_CTRL_GET) \ - SW_API_DESC(SW_API_FDB_DEL_BY_FID) -#else -#define FDB_API \ - SW_API_DEF(SW_API_FDB_PT_LEARN_SET, fal_fdb_port_learn_set), \ - SW_API_DEF(SW_API_FDB_EXTEND_FIRST, fal_fdb_entry_extend_getfirst), \ - SW_API_DEF(SW_API_FDB_EXTEND_NEXT, fal_fdb_entry_extend_getnext), - -#define FDB_API_PARAM \ - SW_API_DESC(SW_API_FDB_PT_LEARN_SET) \ - SW_API_DESC(SW_API_FDB_EXTEND_FIRST) \ - SW_API_DESC(SW_API_FDB_EXTEND_NEXT) -#endif -#else -#define FDB_API -#define FDB_API_PARAM -#endif - -#ifdef IN_ACL -#define ACL_API \ - SW_API_DEF(SW_API_ACL_LIST_CREAT, fal_acl_list_creat), \ - SW_API_DEF(SW_API_ACL_LIST_DESTROY, fal_acl_list_destroy), \ - SW_API_DEF(SW_API_ACL_RULE_ADD, fal_acl_rule_add), \ - SW_API_DEF(SW_API_ACL_RULE_DELETE, fal_acl_rule_delete), \ - SW_API_DEF(SW_API_ACL_RULE_QUERY, fal_acl_rule_query), \ - SW_API_DEF(SW_API_ACL_LIST_BIND, fal_acl_list_bind), \ - SW_API_DEF(SW_API_ACL_LIST_UNBIND, fal_acl_list_unbind), \ - SW_API_DEF(SW_API_ACL_STATUS_SET, fal_acl_status_set), \ - SW_API_DEF(SW_API_ACL_STATUS_GET, fal_acl_status_get), \ - SW_API_DEF(SW_API_ACL_LIST_DUMP, fal_acl_list_dump), \ - SW_API_DEF(SW_API_ACL_RULE_DUMP, fal_acl_rule_dump), \ - SW_API_DEF(SW_API_ACL_PT_UDF_PROFILE_SET, fal_acl_port_udf_profile_set), \ - SW_API_DEF(SW_API_ACL_PT_UDF_PROFILE_GET, fal_acl_port_udf_profile_get), \ - SW_API_DEF(SW_API_ACL_RULE_ACTIVE, fal_acl_rule_active), \ - SW_API_DEF(SW_API_ACL_RULE_DEACTIVE, fal_acl_rule_deactive),\ - SW_API_DEF(SW_API_ACL_RULE_SRC_FILTER_STS_SET, fal_acl_rule_src_filter_sts_set),\ - SW_API_DEF(SW_API_ACL_RULE_SRC_FILTER_STS_GET, fal_acl_rule_src_filter_sts_get),\ - SW_API_DEF(SW_API_ACL_UDF_SET, fal_acl_udf_profile_set),\ - SW_API_DEF(SW_API_ACL_UDF_GET, fal_acl_udf_profile_get), - -#define ACL_API_PARAM \ - SW_API_DESC(SW_API_ACL_LIST_CREAT) \ - SW_API_DESC(SW_API_ACL_LIST_DESTROY) \ - SW_API_DESC(SW_API_ACL_RULE_ADD) \ - SW_API_DESC(SW_API_ACL_RULE_DELETE) \ - SW_API_DESC(SW_API_ACL_RULE_QUERY) \ - SW_API_DESC(SW_API_ACL_LIST_BIND) \ - SW_API_DESC(SW_API_ACL_LIST_UNBIND) \ - SW_API_DESC(SW_API_ACL_STATUS_SET) \ - SW_API_DESC(SW_API_ACL_STATUS_GET) \ - SW_API_DESC(SW_API_ACL_LIST_DUMP) \ - SW_API_DESC(SW_API_ACL_RULE_DUMP) \ - SW_API_DESC(SW_API_ACL_PT_UDF_PROFILE_SET) \ - SW_API_DESC(SW_API_ACL_PT_UDF_PROFILE_GET) \ - SW_API_DESC(SW_API_ACL_RULE_ACTIVE) \ - SW_API_DESC(SW_API_ACL_RULE_DEACTIVE) \ - SW_API_DESC(SW_API_ACL_RULE_SRC_FILTER_STS_SET)\ - SW_API_DESC(SW_API_ACL_RULE_SRC_FILTER_STS_GET)\ - SW_API_DESC(SW_API_ACL_UDF_SET) \ - SW_API_DESC(SW_API_ACL_UDF_GET) -#else -#define ACL_API -#define ACL_API_PARAM -#endif - -#ifdef IN_QOS -#ifndef IN_QOS_MINI -#define QOS_API \ - SW_API_DEF(SW_API_QOS_SCH_MODE_SET, fal_qos_sch_mode_set), \ - SW_API_DEF(SW_API_QOS_SCH_MODE_GET, fal_qos_sch_mode_get), \ - SW_API_DEF(SW_API_QOS_QU_TX_BUF_ST_SET, fal_qos_queue_tx_buf_status_set), \ - SW_API_DEF(SW_API_QOS_QU_TX_BUF_ST_GET, fal_qos_queue_tx_buf_status_get), \ - SW_API_DEF(SW_API_QOS_QU_TX_BUF_NR_SET, fal_qos_queue_tx_buf_nr_set), \ - SW_API_DEF(SW_API_QOS_QU_TX_BUF_NR_GET, fal_qos_queue_tx_buf_nr_get), \ - SW_API_DEF(SW_API_QOS_PT_TX_BUF_ST_SET, fal_qos_port_tx_buf_status_set), \ - SW_API_DEF(SW_API_QOS_PT_TX_BUF_ST_GET, fal_qos_port_tx_buf_status_get), \ - SW_API_DEF(SW_API_QOS_PT_RED_EN_SET, fal_qos_port_red_en_set), \ - SW_API_DEF(SW_API_QOS_PT_RED_EN_GET, fal_qos_port_red_en_get), \ - SW_API_DEF(SW_API_QOS_PT_TX_BUF_NR_SET, fal_qos_port_tx_buf_nr_set), \ - SW_API_DEF(SW_API_QOS_PT_TX_BUF_NR_GET, fal_qos_port_tx_buf_nr_get), \ - SW_API_DEF(SW_API_QOS_PT_RX_BUF_NR_SET, fal_qos_port_rx_buf_nr_set), \ - SW_API_DEF(SW_API_QOS_PT_RX_BUF_NR_GET, fal_qos_port_rx_buf_nr_get), \ - SW_API_DEF(SW_API_COSMAP_UP_QU_SET, fal_cosmap_up_queue_set), \ - SW_API_DEF(SW_API_COSMAP_UP_QU_GET, fal_cosmap_up_queue_get), \ - SW_API_DEF(SW_API_COSMAP_DSCP_QU_SET, fal_cosmap_dscp_queue_set), \ - SW_API_DEF(SW_API_COSMAP_DSCP_QU_GET, fal_cosmap_dscp_queue_get), \ - SW_API_DEF(SW_API_QOS_PT_MODE_SET, fal_qos_port_mode_set), \ - SW_API_DEF(SW_API_QOS_PT_MODE_GET, fal_qos_port_mode_get), \ - SW_API_DEF(SW_API_QOS_PT_MODE_PRI_SET, fal_qos_port_mode_pri_set), \ - SW_API_DEF(SW_API_QOS_PT_MODE_PRI_GET, fal_qos_port_mode_pri_get), \ - SW_API_DEF(SW_API_QOS_PORT_DEF_UP_SET, fal_qos_port_default_up_set), \ - SW_API_DEF(SW_API_QOS_PORT_DEF_UP_GET, fal_qos_port_default_up_get), \ - SW_API_DEF(SW_API_QOS_PORT_SCH_MODE_SET, fal_qos_port_sch_mode_set), \ - SW_API_DEF(SW_API_QOS_PORT_SCH_MODE_GET, fal_qos_port_sch_mode_get), \ - SW_API_DEF(SW_API_QOS_PT_DEF_SPRI_SET, fal_qos_port_default_spri_set), \ - SW_API_DEF(SW_API_QOS_PT_DEF_SPRI_GET, fal_qos_port_default_spri_get), \ - SW_API_DEF(SW_API_QOS_PT_DEF_CPRI_SET, fal_qos_port_default_cpri_set), \ - SW_API_DEF(SW_API_QOS_PT_DEF_CPRI_GET, fal_qos_port_default_cpri_get), \ - SW_API_DEF(SW_API_QOS_PT_FORCE_SPRI_ST_SET, fal_qos_port_force_spri_status_set), \ - SW_API_DEF(SW_API_QOS_PT_FORCE_SPRI_ST_GET, fal_qos_port_force_spri_status_get), \ - SW_API_DEF(SW_API_QOS_PT_FORCE_CPRI_ST_SET, fal_qos_port_force_cpri_status_set), \ - SW_API_DEF(SW_API_QOS_PT_FORCE_CPRI_ST_GET, fal_qos_port_force_cpri_status_get), \ - SW_API_DEF(SW_API_QOS_QUEUE_REMARK_SET, fal_qos_queue_remark_table_set), \ - SW_API_DEF(SW_API_QOS_QUEUE_REMARK_GET, fal_qos_queue_remark_table_get), \ - SW_API_DEF(SW_API_QOS_PORT_GROUP_GET, fal_qos_port_group_get), \ - SW_API_DEF(SW_API_QOS_PORT_GROUP_SET, fal_qos_port_group_set), \ - SW_API_DEF(SW_API_QOS_PORT_PRI_GET, fal_qos_port_pri_precedence_get), \ - SW_API_DEF(SW_API_QOS_PORT_PRI_SET, fal_qos_port_pri_precedence_set), \ - SW_API_DEF(SW_API_QOS_PORT_REMARK_GET, fal_qos_port_remark_get), \ - SW_API_DEF(SW_API_QOS_PORT_REMARK_SET, fal_qos_port_remark_set), \ - SW_API_DEF(SW_API_QOS_PCP_MAP_GET, fal_qos_cosmap_pcp_get), \ - SW_API_DEF(SW_API_QOS_PCP_MAP_SET, fal_qos_cosmap_pcp_set), \ - SW_API_DEF(SW_API_QOS_FLOW_MAP_GET, fal_qos_cosmap_flow_get), \ - SW_API_DEF(SW_API_QOS_FLOW_MAP_SET, fal_qos_cosmap_flow_set), \ - SW_API_DEF(SW_API_QOS_DSCP_MAP_GET, fal_qos_cosmap_dscp_get), \ - SW_API_DEF(SW_API_QOS_DSCP_MAP_SET, fal_qos_cosmap_dscp_set), \ - SW_API_DEF(SW_API_QOS_QUEUE_SCHEDULER_GET, fal_queue_scheduler_get), \ - SW_API_DEF(SW_API_QOS_QUEUE_SCHEDULER_SET, fal_queue_scheduler_set), \ - SW_API_DEF(SW_API_QOS_RING_QUEUE_MAP_GET, fal_edma_ring_queue_map_get), \ - SW_API_DEF(SW_API_QOS_RING_QUEUE_MAP_SET, fal_edma_ring_queue_map_set), \ - SW_API_DEF(SW_API_QOS_PORT_QUEUES_GET, fal_port_queues_get), \ - SW_API_DEF(SW_API_QOS_SCHEDULER_DEQUEU_CTRL_GET, fal_scheduler_dequeue_ctrl_get), \ - SW_API_DEF(SW_API_QOS_SCHEDULER_DEQUEU_CTRL_SET, fal_scheduler_dequeue_ctrl_set), \ - SW_API_DEF(SW_API_QOS_PORT_SCHEDULER_CFG_RESET, fal_port_scheduler_cfg_reset), \ - SW_API_DEF(SW_API_QOS_PORT_SCHEDULER_RESOURCE_GET, fal_port_scheduler_resource_get), - -#define QOS_API_PARAM \ - SW_API_DESC(SW_API_QOS_SCH_MODE_SET) \ - SW_API_DESC(SW_API_QOS_SCH_MODE_GET) \ - SW_API_DESC(SW_API_QOS_QU_TX_BUF_ST_SET) \ - SW_API_DESC(SW_API_QOS_QU_TX_BUF_ST_GET) \ - SW_API_DESC(SW_API_QOS_QU_TX_BUF_NR_SET) \ - SW_API_DESC(SW_API_QOS_QU_TX_BUF_NR_GET) \ - SW_API_DESC(SW_API_QOS_PT_TX_BUF_ST_SET) \ - SW_API_DESC(SW_API_QOS_PT_TX_BUF_ST_GET) \ - SW_API_DESC(SW_API_QOS_PT_RED_EN_SET)\ - SW_API_DESC(SW_API_QOS_PT_RED_EN_GET)\ - SW_API_DESC(SW_API_QOS_PT_TX_BUF_NR_SET) \ - SW_API_DESC(SW_API_QOS_PT_TX_BUF_NR_GET) \ - SW_API_DESC(SW_API_QOS_PT_RX_BUF_NR_SET) \ - SW_API_DESC(SW_API_QOS_PT_RX_BUF_NR_GET) \ - SW_API_DESC(SW_API_COSMAP_UP_QU_SET) \ - SW_API_DESC(SW_API_COSMAP_UP_QU_GET) \ - SW_API_DESC(SW_API_COSMAP_DSCP_QU_SET) \ - SW_API_DESC(SW_API_COSMAP_DSCP_QU_GET) \ - SW_API_DESC(SW_API_QOS_PT_MODE_SET) \ - SW_API_DESC(SW_API_QOS_PT_MODE_GET) \ - SW_API_DESC(SW_API_QOS_PT_MODE_PRI_SET) \ - SW_API_DESC(SW_API_QOS_PT_MODE_PRI_GET) \ - SW_API_DESC(SW_API_QOS_PORT_DEF_UP_SET) \ - SW_API_DESC(SW_API_QOS_PORT_DEF_UP_GET) \ - SW_API_DESC(SW_API_QOS_PORT_SCH_MODE_SET) \ - SW_API_DESC(SW_API_QOS_PORT_SCH_MODE_GET) \ - SW_API_DESC(SW_API_QOS_PT_DEF_SPRI_SET) \ - SW_API_DESC(SW_API_QOS_PT_DEF_SPRI_GET) \ - SW_API_DESC(SW_API_QOS_PT_DEF_CPRI_SET) \ - SW_API_DESC(SW_API_QOS_PT_DEF_CPRI_GET) \ - SW_API_DESC(SW_API_QOS_PT_FORCE_SPRI_ST_SET) \ - SW_API_DESC(SW_API_QOS_PT_FORCE_SPRI_ST_GET) \ - SW_API_DESC(SW_API_QOS_PT_FORCE_CPRI_ST_SET) \ - SW_API_DESC(SW_API_QOS_PT_FORCE_CPRI_ST_GET) \ - SW_API_DESC(SW_API_QOS_QUEUE_REMARK_SET) \ - SW_API_DESC(SW_API_QOS_QUEUE_REMARK_GET) \ - SW_API_DESC(SW_API_QOS_PORT_GROUP_GET) \ - SW_API_DESC(SW_API_QOS_PORT_GROUP_SET) \ - SW_API_DESC(SW_API_QOS_PORT_PRI_GET) \ - SW_API_DESC(SW_API_QOS_PORT_PRI_SET) \ - SW_API_DESC(SW_API_QOS_PORT_REMARK_GET) \ - SW_API_DESC(SW_API_QOS_PORT_REMARK_SET) \ - SW_API_DESC(SW_API_QOS_PCP_MAP_GET) \ - SW_API_DESC(SW_API_QOS_PCP_MAP_SET) \ - SW_API_DESC(SW_API_QOS_FLOW_MAP_GET) \ - SW_API_DESC(SW_API_QOS_FLOW_MAP_SET) \ - SW_API_DESC(SW_API_QOS_DSCP_MAP_GET) \ - SW_API_DESC(SW_API_QOS_DSCP_MAP_SET) \ - SW_API_DESC(SW_API_QOS_QUEUE_SCHEDULER_GET) \ - SW_API_DESC(SW_API_QOS_QUEUE_SCHEDULER_SET) \ - SW_API_DESC(SW_API_QOS_RING_QUEUE_MAP_GET) \ - SW_API_DESC(SW_API_QOS_RING_QUEUE_MAP_SET) \ - SW_API_DESC(SW_API_QOS_PORT_QUEUES_GET) \ - SW_API_DESC(SW_API_QOS_SCHEDULER_DEQUEU_CTRL_GET) \ - SW_API_DESC(SW_API_QOS_SCHEDULER_DEQUEU_CTRL_SET) \ - SW_API_DESC(SW_API_QOS_PORT_SCHEDULER_CFG_RESET) \ - SW_API_DESC(SW_API_QOS_PORT_SCHEDULER_RESOURCE_GET) -#else -#define QOS_API \ - SW_API_DEF(SW_API_QOS_PT_MODE_SET, fal_qos_port_mode_set), - - -#define QOS_API_PARAM \ - SW_API_DESC(SW_API_QOS_PT_MODE_SET) - -#endif -#else -#define QOS_API -#define QOS_API_PARAM -#endif - -#ifdef IN_IGMP -#define IGMP_API \ - SW_API_DEF(SW_API_PT_IGMPS_MODE_SET, fal_port_igmps_status_set), \ - SW_API_DEF(SW_API_PT_IGMPS_MODE_GET, fal_port_igmps_status_get), \ - SW_API_DEF(SW_API_IGMP_MLD_CMD_SET, fal_igmp_mld_cmd_set), \ - SW_API_DEF(SW_API_IGMP_MLD_CMD_GET, fal_igmp_mld_cmd_get), \ - SW_API_DEF(SW_API_IGMP_PT_JOIN_SET, fal_port_igmp_mld_join_set), \ - SW_API_DEF(SW_API_IGMP_PT_JOIN_GET, fal_port_igmp_mld_join_get), \ - SW_API_DEF(SW_API_IGMP_PT_LEAVE_SET, fal_port_igmp_mld_leave_set), \ - SW_API_DEF(SW_API_IGMP_PT_LEAVE_GET, fal_port_igmp_mld_leave_get), \ - SW_API_DEF(SW_API_IGMP_RP_SET, fal_igmp_mld_rp_set), \ - SW_API_DEF(SW_API_IGMP_RP_GET, fal_igmp_mld_rp_get), \ - SW_API_DEF(SW_API_IGMP_ENTRY_CREAT_SET, fal_igmp_mld_entry_creat_set), \ - SW_API_DEF(SW_API_IGMP_ENTRY_CREAT_GET, fal_igmp_mld_entry_creat_get), \ - SW_API_DEF(SW_API_IGMP_ENTRY_STATIC_SET, fal_igmp_mld_entry_static_set), \ - SW_API_DEF(SW_API_IGMP_ENTRY_STATIC_GET, fal_igmp_mld_entry_static_get), \ - SW_API_DEF(SW_API_IGMP_ENTRY_LEAKY_SET, fal_igmp_mld_entry_leaky_set), \ - SW_API_DEF(SW_API_IGMP_ENTRY_LEAKY_GET, fal_igmp_mld_entry_leaky_get), \ - SW_API_DEF(SW_API_IGMP_ENTRY_V3_SET, fal_igmp_mld_entry_v3_set), \ - SW_API_DEF(SW_API_IGMP_ENTRY_V3_GET, fal_igmp_mld_entry_v3_get), \ - SW_API_DEF(SW_API_IGMP_ENTRY_QUEUE_SET, fal_igmp_mld_entry_queue_set), \ - SW_API_DEF(SW_API_IGMP_ENTRY_QUEUE_GET, fal_igmp_mld_entry_queue_get), \ - SW_API_DEF(SW_API_PT_IGMP_LEARN_LIMIT_SET, fal_port_igmp_mld_learn_limit_set), \ - SW_API_DEF(SW_API_PT_IGMP_LEARN_LIMIT_GET, fal_port_igmp_mld_learn_limit_get), \ - SW_API_DEF(SW_API_PT_IGMP_LEARN_EXCEED_CMD_SET, fal_port_igmp_mld_learn_exceed_cmd_set), \ - SW_API_DEF(SW_API_PT_IGMP_LEARN_EXCEED_CMD_GET, fal_port_igmp_mld_learn_exceed_cmd_get), \ - SW_API_DEF(SW_API_IGMP_SG_ENTRY_SET, fal_igmp_sg_entry_set), \ - SW_API_DEF(SW_API_IGMP_SG_ENTRY_CLEAR, fal_igmp_sg_entry_clear), \ - SW_API_DEF(SW_API_IGMP_SG_ENTRY_SHOW, fal_igmp_sg_entry_show), \ - SW_API_DEF(SW_API_IGMP_SG_ENTRY_QUERY, fal_igmp_sg_entry_query), - -#define IGMP_API_PARAM \ - SW_API_DESC(SW_API_PT_IGMPS_MODE_SET) \ - SW_API_DESC(SW_API_PT_IGMPS_MODE_GET) \ - SW_API_DESC(SW_API_IGMP_MLD_CMD_SET) \ - SW_API_DESC(SW_API_IGMP_MLD_CMD_GET) \ - SW_API_DESC(SW_API_IGMP_PT_JOIN_SET) \ - SW_API_DESC(SW_API_IGMP_PT_JOIN_GET) \ - SW_API_DESC(SW_API_IGMP_PT_LEAVE_SET) \ - SW_API_DESC(SW_API_IGMP_PT_LEAVE_GET) \ - SW_API_DESC(SW_API_IGMP_RP_SET) \ - SW_API_DESC(SW_API_IGMP_RP_GET) \ - SW_API_DESC(SW_API_IGMP_ENTRY_CREAT_SET) \ - SW_API_DESC(SW_API_IGMP_ENTRY_CREAT_GET) \ - SW_API_DESC(SW_API_IGMP_ENTRY_STATIC_SET) \ - SW_API_DESC(SW_API_IGMP_ENTRY_STATIC_GET) \ - SW_API_DESC(SW_API_IGMP_ENTRY_LEAKY_SET) \ - SW_API_DESC(SW_API_IGMP_ENTRY_LEAKY_GET) \ - SW_API_DESC(SW_API_IGMP_ENTRY_V3_SET) \ - SW_API_DESC(SW_API_IGMP_ENTRY_V3_GET) \ - SW_API_DESC(SW_API_IGMP_ENTRY_QUEUE_SET) \ - SW_API_DESC(SW_API_IGMP_ENTRY_QUEUE_GET) \ - SW_API_DESC(SW_API_PT_IGMP_LEARN_LIMIT_SET) \ - SW_API_DESC(SW_API_PT_IGMP_LEARN_LIMIT_GET) \ - SW_API_DESC(SW_API_PT_IGMP_LEARN_EXCEED_CMD_SET) \ - SW_API_DESC(SW_API_PT_IGMP_LEARN_EXCEED_CMD_GET) \ - SW_API_DESC(SW_API_IGMP_SG_ENTRY_SET) \ - SW_API_DESC(SW_API_IGMP_SG_ENTRY_CLEAR) \ - SW_API_DESC(SW_API_IGMP_SG_ENTRY_SHOW) \ - SW_API_DESC(SW_API_IGMP_SG_ENTRY_QUERY) -#else -#define IGMP_API -#define IGMP_API_PARAM -#endif - -#ifdef IN_LEAKY -#define LEAKY_API \ - SW_API_DEF(SW_API_UC_LEAKY_MODE_SET, fal_uc_leaky_mode_set), \ - SW_API_DEF(SW_API_UC_LEAKY_MODE_GET, fal_uc_leaky_mode_get), \ - SW_API_DEF(SW_API_MC_LEAKY_MODE_SET, fal_mc_leaky_mode_set), \ - SW_API_DEF(SW_API_MC_LEAKY_MODE_GET, fal_mc_leaky_mode_get), \ - SW_API_DEF(SW_API_ARP_LEAKY_MODE_SET, fal_port_arp_leaky_set), \ - SW_API_DEF(SW_API_ARP_LEAKY_MODE_GET, fal_port_arp_leaky_get), \ - SW_API_DEF(SW_API_PT_UC_LEAKY_MODE_SET, fal_port_uc_leaky_set), \ - SW_API_DEF(SW_API_PT_UC_LEAKY_MODE_GET, fal_port_uc_leaky_get), \ - SW_API_DEF(SW_API_PT_MC_LEAKY_MODE_SET, fal_port_mc_leaky_set), \ - SW_API_DEF(SW_API_PT_MC_LEAKY_MODE_GET, fal_port_mc_leaky_get), - -#define LEAKY_API_PARAM \ - SW_API_DESC(SW_API_UC_LEAKY_MODE_SET) \ - SW_API_DESC(SW_API_UC_LEAKY_MODE_GET) \ - SW_API_DESC(SW_API_MC_LEAKY_MODE_SET) \ - SW_API_DESC(SW_API_MC_LEAKY_MODE_GET) \ - SW_API_DESC(SW_API_ARP_LEAKY_MODE_SET)\ - SW_API_DESC(SW_API_ARP_LEAKY_MODE_GET) \ - SW_API_DESC(SW_API_PT_UC_LEAKY_MODE_SET) \ - SW_API_DESC(SW_API_PT_UC_LEAKY_MODE_GET) \ - SW_API_DESC(SW_API_PT_MC_LEAKY_MODE_SET) \ - SW_API_DESC(SW_API_PT_MC_LEAKY_MODE_GET) -#else -#define LEAKY_API -#define LEAKY_API_PARAM -#endif - -#ifdef IN_MIRROR -#define MIRROR_API \ - SW_API_DEF(SW_API_MIRROR_ANALY_PT_SET, fal_mirr_analysis_port_set), \ - SW_API_DEF(SW_API_MIRROR_ANALY_PT_GET, fal_mirr_analysis_port_get), \ - SW_API_DEF(SW_API_MIRROR_IN_PT_SET, fal_mirr_port_in_set), \ - SW_API_DEF(SW_API_MIRROR_IN_PT_GET, fal_mirr_port_in_get), \ - SW_API_DEF(SW_API_MIRROR_EG_PT_SET, fal_mirr_port_eg_set), \ - SW_API_DEF(SW_API_MIRROR_EG_PT_GET, fal_mirr_port_eg_get), \ - SW_API_DEF(SW_API_MIRROR_ANALYSIS_CONFIG_SET, fal_mirr_analysis_config_set), \ - SW_API_DEF(SW_API_MIRROR_ANALYSIS_CONFIG_GET, fal_mirr_analysis_config_get), - -#define MIRROR_API_PARAM \ - SW_API_DESC(SW_API_MIRROR_ANALY_PT_SET) \ - SW_API_DESC(SW_API_MIRROR_ANALY_PT_GET) \ - SW_API_DESC(SW_API_MIRROR_IN_PT_SET) \ - SW_API_DESC(SW_API_MIRROR_IN_PT_GET) \ - SW_API_DESC(SW_API_MIRROR_EG_PT_SET) \ - SW_API_DESC(SW_API_MIRROR_EG_PT_GET) \ - SW_API_DESC(SW_API_MIRROR_ANALYSIS_CONFIG_SET) \ - SW_API_DESC(SW_API_MIRROR_ANALYSIS_CONFIG_GET) - -#else -#define MIRROR_API -#define MIRROR_API_PARAM -#endif - -#ifdef IN_RATE -#define RATE_API \ - SW_API_DEF(SW_API_RATE_QU_EGRL_SET, fal_rate_queue_egrl_set), \ - SW_API_DEF(SW_API_RATE_QU_EGRL_GET, fal_rate_queue_egrl_get), \ - SW_API_DEF(SW_API_RATE_PT_EGRL_SET, fal_rate_port_egrl_set), \ - SW_API_DEF(SW_API_RATE_PT_EGRL_GET, fal_rate_port_egrl_get), \ - SW_API_DEF(SW_API_RATE_PT_INRL_SET, fal_rate_port_inrl_set), \ - SW_API_DEF(SW_API_RATE_PT_INRL_GET, fal_rate_port_inrl_get), \ - SW_API_DEF(SW_API_STORM_CTRL_FRAME_SET, fal_storm_ctrl_frame_set), \ - SW_API_DEF(SW_API_STORM_CTRL_FRAME_GET, fal_storm_ctrl_frame_get), \ - SW_API_DEF(SW_API_STORM_CTRL_RATE_SET, fal_storm_ctrl_rate_set), \ - SW_API_DEF(SW_API_STORM_CTRL_RATE_GET, fal_storm_ctrl_rate_get), \ - SW_API_DEF(SW_API_RATE_PORT_POLICER_SET, fal_rate_port_policer_set), \ - SW_API_DEF(SW_API_RATE_PORT_POLICER_GET, fal_rate_port_policer_get), \ - SW_API_DEF(SW_API_RATE_PORT_SHAPER_SET, fal_rate_port_shaper_set), \ - SW_API_DEF(SW_API_RATE_PORT_SHAPER_GET, fal_rate_port_shaper_get), \ - SW_API_DEF(SW_API_RATE_QUEUE_SHAPER_SET, fal_rate_queue_shaper_set), \ - SW_API_DEF(SW_API_RATE_QUEUE_SHAPER_GET, fal_rate_queue_shaper_get), \ - SW_API_DEF(SW_API_RATE_ACL_POLICER_SET, fal_rate_acl_policer_set), \ - SW_API_DEF(SW_API_RATE_ACL_POLICER_GET, fal_rate_acl_policer_get), \ - SW_API_DEF(SW_API_RATE_PT_ADDRATEBYTE_SET, fal_rate_port_add_rate_byte_set), \ - SW_API_DEF(SW_API_RATE_PT_ADDRATEBYTE_GET, fal_rate_port_add_rate_byte_get), \ - SW_API_DEF(SW_API_RATE_PT_GOL_FLOW_EN_SET, fal_rate_port_gol_flow_en_set), \ - SW_API_DEF(SW_API_RATE_PT_GOL_FLOW_EN_GET, fal_rate_port_gol_flow_en_get), - -#define RATE_API_PARAM \ - SW_API_DESC(SW_API_RATE_QU_EGRL_SET) \ - SW_API_DESC(SW_API_RATE_QU_EGRL_GET) \ - SW_API_DESC(SW_API_RATE_PT_EGRL_SET) \ - SW_API_DESC(SW_API_RATE_PT_EGRL_GET) \ - SW_API_DESC(SW_API_RATE_PT_INRL_SET) \ - SW_API_DESC(SW_API_RATE_PT_INRL_GET) \ - SW_API_DESC(SW_API_STORM_CTRL_FRAME_SET) \ - SW_API_DESC(SW_API_STORM_CTRL_FRAME_GET) \ - SW_API_DESC(SW_API_STORM_CTRL_RATE_SET) \ - SW_API_DESC(SW_API_STORM_CTRL_RATE_GET) \ - SW_API_DESC(SW_API_RATE_PORT_POLICER_SET) \ - SW_API_DESC(SW_API_RATE_PORT_POLICER_GET) \ - SW_API_DESC(SW_API_RATE_PORT_SHAPER_SET) \ - SW_API_DESC(SW_API_RATE_PORT_SHAPER_GET) \ - SW_API_DESC(SW_API_RATE_QUEUE_SHAPER_SET) \ - SW_API_DESC(SW_API_RATE_QUEUE_SHAPER_GET) \ - SW_API_DESC(SW_API_RATE_ACL_POLICER_SET) \ - SW_API_DESC(SW_API_RATE_ACL_POLICER_GET) \ - SW_API_DESC(SW_API_RATE_PT_ADDRATEBYTE_SET) \ - SW_API_DESC(SW_API_RATE_PT_ADDRATEBYTE_GET) \ - SW_API_DESC(SW_API_RATE_PT_GOL_FLOW_EN_SET) \ - SW_API_DESC(SW_API_RATE_PT_GOL_FLOW_EN_GET) -#else -#define RATE_API -#define RATE_API_PARAM -#endif - -#ifdef IN_STP -#define STP_API \ - SW_API_DEF(SW_API_STP_PT_STATE_SET, fal_stp_port_state_set), \ - SW_API_DEF(SW_API_STP_PT_STATE_GET, fal_stp_port_state_get), - -#define STP_API_PARAM \ - SW_API_DESC(SW_API_STP_PT_STATE_SET) \ - SW_API_DESC(SW_API_STP_PT_STATE_GET) -#else -#define STP_API -#define STP_API_PARAM -#endif - -#ifdef IN_MIB -#define MIB_API \ - SW_API_DEF(SW_API_PT_MIB_GET, fal_get_mib_info), \ - SW_API_DEF(SW_API_MIB_STATUS_SET, fal_mib_status_set), \ - SW_API_DEF(SW_API_MIB_STATUS_GET, fal_mib_status_get), \ - SW_API_DEF(SW_API_PT_MIB_FLUSH_COUNTERS, fal_mib_port_flush_counters), \ - SW_API_DEF(SW_API_MIB_CPU_KEEP_SET, fal_mib_cpukeep_set), \ - SW_API_DEF(SW_API_MIB_CPU_KEEP_GET, fal_mib_cpukeep_get),\ - SW_API_DEF(SW_API_PT_XGMIB_GET, fal_get_xgmib_info),\ - SW_API_DEF(SW_API_PT_MIB_COUNTER_GET, fal_mib_counter_get), - -#define MIB_API_PARAM \ - SW_API_DESC(SW_API_PT_MIB_GET) \ - SW_API_DESC(SW_API_PT_XGMIB_GET) \ - SW_API_DESC(SW_API_MIB_STATUS_SET) \ - SW_API_DESC(SW_API_MIB_STATUS_GET) \ - SW_API_DESC(SW_API_PT_MIB_FLUSH_COUNTERS) \ - SW_API_DESC(SW_API_MIB_CPU_KEEP_SET) \ - SW_API_DESC(SW_API_MIB_CPU_KEEP_GET) \ - SW_API_DESC(SW_API_PT_MIB_COUNTER_GET) -#else -#define MIB_API -#define MIB_API_PARAM -#endif - -#ifdef IN_MISC -#ifndef IN_MISC_MINI -#define MISC_API \ - SW_API_DEF(SW_API_ARP_STATUS_SET, fal_arp_status_set), \ - SW_API_DEF(SW_API_ARP_STATUS_GET, fal_arp_status_get), \ - SW_API_DEF(SW_API_FRAME_MAX_SIZE_SET, fal_frame_max_size_set), \ - SW_API_DEF(SW_API_FRAME_MAX_SIZE_GET, fal_frame_max_size_get), \ - SW_API_DEF(SW_API_PT_UNK_SA_CMD_SET, fal_port_unk_sa_cmd_set), \ - SW_API_DEF(SW_API_PT_UNK_SA_CMD_GET, fal_port_unk_sa_cmd_get), \ - SW_API_DEF(SW_API_PT_UNK_UC_FILTER_SET, fal_port_unk_uc_filter_set), \ - SW_API_DEF(SW_API_PT_UNK_UC_FILTER_GET, fal_port_unk_uc_filter_get), \ - SW_API_DEF(SW_API_PT_UNK_MC_FILTER_SET, fal_port_unk_mc_filter_set), \ - SW_API_DEF(SW_API_PT_UNK_MC_FILTER_GET, fal_port_unk_mc_filter_get), \ - SW_API_DEF(SW_API_PT_BC_FILTER_SET, fal_port_bc_filter_set), \ - SW_API_DEF(SW_API_PT_BC_FILTER_GET, fal_port_bc_filter_get), \ - SW_API_DEF(SW_API_CPU_PORT_STATUS_SET, fal_cpu_port_status_set), \ - SW_API_DEF(SW_API_CPU_PORT_STATUS_GET, fal_cpu_port_status_get), \ - SW_API_DEF(SW_API_BC_TO_CPU_PORT_SET, fal_bc_to_cpu_port_set), \ - SW_API_DEF(SW_API_BC_TO_CPU_PORT_GET, fal_bc_to_cpu_port_get), \ - SW_API_DEF(SW_API_PT_DHCP_SET, fal_port_dhcp_set), \ - SW_API_DEF(SW_API_PT_DHCP_GET, fal_port_dhcp_get), \ - SW_API_DEF(SW_API_ARP_CMD_SET, fal_arp_cmd_set), \ - SW_API_DEF(SW_API_ARP_CMD_GET, fal_arp_cmd_get), \ - SW_API_DEF(SW_API_EAPOL_CMD_SET, fal_eapol_cmd_set), \ - SW_API_DEF(SW_API_EAPOL_CMD_GET, fal_eapol_cmd_get), \ - SW_API_DEF(SW_API_EAPOL_STATUS_SET, fal_eapol_status_set), \ - SW_API_DEF(SW_API_EAPOL_STATUS_GET, fal_eapol_status_get), \ - SW_API_DEF(SW_API_RIPV1_STATUS_SET, fal_ripv1_status_set), \ - SW_API_DEF(SW_API_RIPV1_STATUS_GET, fal_ripv1_status_get), \ - SW_API_DEF(SW_API_PT_ARP_REQ_STATUS_SET, fal_port_arp_req_status_set), \ - SW_API_DEF(SW_API_PT_ARP_REQ_STATUS_GET, fal_port_arp_req_status_get), \ - SW_API_DEF(SW_API_PT_ARP_ACK_STATUS_SET, fal_port_arp_ack_status_set), \ - SW_API_DEF(SW_API_PT_ARP_ACK_STATUS_GET, fal_port_arp_ack_status_get), \ - SW_API_DEF(SW_API_INTR_MASK_SET, fal_intr_mask_set), \ - SW_API_DEF(SW_API_INTR_MASK_GET, fal_intr_mask_get), \ - SW_API_DEF(SW_API_INTR_STATUS_GET, fal_intr_status_get), \ - SW_API_DEF(SW_API_INTR_STATUS_CLEAR, fal_intr_status_clear), \ - SW_API_DEF(SW_API_INTR_PORT_LINK_MASK_SET, fal_intr_port_link_mask_set), \ - SW_API_DEF(SW_API_INTR_PORT_LINK_MASK_GET, fal_intr_port_link_mask_get), \ - SW_API_DEF(SW_API_INTR_PORT_LINK_STATUS_GET, fal_intr_port_link_status_get), \ - SW_API_DEF(SW_API_INTR_MASK_MAC_LINKCHG_SET, fal_intr_mask_mac_linkchg_set), \ - SW_API_DEF(SW_API_INTR_MASK_MAC_LINKCHG_GET, fal_intr_mask_mac_linkchg_get), \ - SW_API_DEF(SW_API_INTR_STATUS_MAC_LINKCHG_GET, fal_intr_status_mac_linkchg_get), \ - SW_API_DEF(SW_API_INTR_STATUS_MAC_LINKCHG_CLEAR, fal_intr_status_mac_linkchg_clear), \ - SW_API_DEF(SW_API_CPU_VID_EN_SET, fal_cpu_vid_en_set), \ - SW_API_DEF(SW_API_CPU_VID_EN_GET, fal_cpu_vid_en_get), \ - SW_API_DEF(SW_API_GLOBAL_MACADDR_SET, fal_global_macaddr_set), \ - SW_API_DEF(SW_API_GLOBAL_MACADDR_GET, fal_global_macaddr_get), \ - SW_API_DEF(SW_API_LLDP_STATUS_SET, fal_lldp_status_set), \ - SW_API_DEF(SW_API_LLDP_STATUS_GET, fal_lldp_status_get), \ - SW_API_DEF(SW_API_FRAME_CRC_RESERVE_SET, fal_frame_crc_reserve_set), \ - SW_API_DEF(SW_API_FRAME_CRC_RESERVE_GET, fal_frame_crc_reserve_get), \ - SW_API_DEF(SW_API_DEBUG_PORT_COUNTER_ENABLE, fal_debug_port_counter_enable), \ - SW_API_DEF(SW_API_DEBUG_PORT_COUNTER_STATUS_GET, fal_debug_port_counter_status_get), - - - -#define MISC_API_PARAM \ - SW_API_DESC(SW_API_ARP_STATUS_SET) \ - SW_API_DESC(SW_API_ARP_STATUS_GET) \ - SW_API_DESC(SW_API_FRAME_MAX_SIZE_SET) \ - SW_API_DESC(SW_API_FRAME_MAX_SIZE_GET) \ - SW_API_DESC(SW_API_PT_UNK_SA_CMD_SET) \ - SW_API_DESC(SW_API_PT_UNK_SA_CMD_GET) \ - SW_API_DESC(SW_API_PT_UNK_UC_FILTER_SET) \ - SW_API_DESC(SW_API_PT_UNK_UC_FILTER_GET) \ - SW_API_DESC(SW_API_PT_UNK_MC_FILTER_SET) \ - SW_API_DESC(SW_API_PT_UNK_MC_FILTER_GET) \ - SW_API_DESC(SW_API_PT_BC_FILTER_SET) \ - SW_API_DESC(SW_API_PT_BC_FILTER_GET) \ - SW_API_DESC(SW_API_CPU_PORT_STATUS_SET) \ - SW_API_DESC(SW_API_CPU_PORT_STATUS_GET) \ - SW_API_DESC(SW_API_BC_TO_CPU_PORT_SET) \ - SW_API_DESC(SW_API_BC_TO_CPU_PORT_GET) \ - SW_API_DESC(SW_API_PT_DHCP_SET) \ - SW_API_DESC(SW_API_PT_DHCP_GET) \ - SW_API_DESC(SW_API_ARP_CMD_SET) \ - SW_API_DESC(SW_API_ARP_CMD_GET) \ - SW_API_DESC(SW_API_EAPOL_CMD_SET) \ - SW_API_DESC(SW_API_EAPOL_CMD_GET) \ - SW_API_DESC(SW_API_EAPOL_STATUS_SET) \ - SW_API_DESC(SW_API_EAPOL_STATUS_GET) \ - SW_API_DESC(SW_API_RIPV1_STATUS_SET) \ - SW_API_DESC(SW_API_RIPV1_STATUS_GET) \ - SW_API_DESC(SW_API_PT_ARP_REQ_STATUS_SET) \ - SW_API_DESC(SW_API_PT_ARP_REQ_STATUS_GET) \ - SW_API_DESC(SW_API_PT_ARP_ACK_STATUS_SET) \ - SW_API_DESC(SW_API_PT_ARP_ACK_STATUS_GET) \ - SW_API_DESC(SW_API_INTR_MASK_SET) \ - SW_API_DESC(SW_API_INTR_MASK_GET) \ - SW_API_DESC(SW_API_INTR_STATUS_GET) \ - SW_API_DESC(SW_API_INTR_STATUS_CLEAR) \ - SW_API_DESC(SW_API_INTR_PORT_LINK_MASK_SET) \ - SW_API_DESC(SW_API_INTR_PORT_LINK_MASK_GET) \ - SW_API_DESC(SW_API_INTR_PORT_LINK_STATUS_GET) \ - SW_API_DESC(SW_API_INTR_MASK_MAC_LINKCHG_SET) \ - SW_API_DESC(SW_API_INTR_MASK_MAC_LINKCHG_GET) \ - SW_API_DESC(SW_API_INTR_STATUS_MAC_LINKCHG_GET) \ - SW_API_DESC(SW_API_INTR_STATUS_MAC_LINKCHG_CLEAR) \ - SW_API_DESC(SW_API_CPU_VID_EN_SET) \ - SW_API_DESC(SW_API_CPU_VID_EN_GET) \ - SW_API_DESC(SW_API_GLOBAL_MACADDR_SET) \ - SW_API_DESC(SW_API_GLOBAL_MACADDR_GET) \ - SW_API_DESC(SW_API_LLDP_STATUS_SET) \ - SW_API_DESC(SW_API_LLDP_STATUS_GET) \ - SW_API_DESC(SW_API_FRAME_CRC_RESERVE_SET) \ - SW_API_DESC(SW_API_FRAME_CRC_RESERVE_GET) \ - SW_API_DESC(SW_API_DEBUG_PORT_COUNTER_ENABLE) \ - SW_API_DESC(SW_API_DEBUG_PORT_COUNTER_STATUS_GET) -#else -#define MISC_API \ - SW_API_DEF(SW_API_PT_UNK_SA_CMD_SET, fal_port_unk_sa_cmd_set), \ - SW_API_DEF(SW_API_PT_UNK_UC_FILTER_SET, fal_port_unk_uc_filter_set), \ - SW_API_DEF(SW_API_PT_UNK_MC_FILTER_SET, fal_port_unk_mc_filter_set), \ - SW_API_DEF(SW_API_PT_BC_FILTER_SET, fal_port_bc_filter_set), \ - SW_API_DEF(SW_API_EAPOL_STATUS_SET, fal_eapol_status_set), \ - SW_API_DEF(SW_API_EAPOL_CMD_SET, fal_eapol_cmd_set), \ - SW_API_DEF(SW_API_CPU_PORT_STATUS_SET, fal_cpu_port_status_set), - -#define MISC_API_PARAM \ - SW_API_DESC(SW_API_PT_UNK_SA_CMD_SET) \ - SW_API_DESC(SW_API_PT_UNK_UC_FILTER_SET) \ - SW_API_DESC(SW_API_PT_UNK_MC_FILTER_SET) \ - SW_API_DESC(SW_API_PT_BC_FILTER_SET) \ - SW_API_DESC(SW_API_EAPOL_CMD_SET) \ - SW_API_DESC(SW_API_EAPOL_STATUS_SET) \ - SW_API_DESC(SW_API_CPU_PORT_STATUS_SET) - -#endif - -#else -#define MISC_API -#define MISC_API_PARAM -#endif - -#ifdef IN_LED -#define LED_API \ - SW_API_DEF(SW_API_LED_PATTERN_SET, fal_led_ctrl_pattern_set), \ - SW_API_DEF(SW_API_LED_PATTERN_GET, fal_led_ctrl_pattern_get), - -#define LED_API_PARAM \ - SW_API_DESC(SW_API_LED_PATTERN_SET) \ - SW_API_DESC(SW_API_LED_PATTERN_GET) -#else -#define LED_API -#define LED_API_PARAM -#endif - -#ifdef IN_COSMAP -#ifndef IN_COSMAP_MINI -#define COSMAP_API \ - SW_API_DEF(SW_API_COSMAP_DSCP_TO_PRI_SET, fal_cosmap_dscp_to_pri_set), \ - SW_API_DEF(SW_API_COSMAP_DSCP_TO_PRI_GET, fal_cosmap_dscp_to_pri_get), \ - SW_API_DEF(SW_API_COSMAP_DSCP_TO_DP_SET, fal_cosmap_dscp_to_dp_set), \ - SW_API_DEF(SW_API_COSMAP_DSCP_TO_DP_GET, fal_cosmap_dscp_to_dp_get), \ - SW_API_DEF(SW_API_COSMAP_UP_TO_PRI_SET, fal_cosmap_up_to_pri_set), \ - SW_API_DEF(SW_API_COSMAP_UP_TO_PRI_GET, fal_cosmap_up_to_pri_get), \ - SW_API_DEF(SW_API_COSMAP_UP_TO_DP_SET, fal_cosmap_up_to_dp_set), \ - SW_API_DEF(SW_API_COSMAP_UP_TO_DP_GET, fal_cosmap_up_to_dp_get), \ - SW_API_DEF(SW_API_COSMAP_PRI_TO_QU_SET, fal_cosmap_pri_to_queue_set), \ - SW_API_DEF(SW_API_COSMAP_PRI_TO_QU_GET, fal_cosmap_pri_to_queue_get), \ - SW_API_DEF(SW_API_COSMAP_PRI_TO_EHQU_SET, fal_cosmap_pri_to_ehqueue_set), \ - SW_API_DEF(SW_API_COSMAP_PRI_TO_EHQU_GET, fal_cosmap_pri_to_ehqueue_get), \ - SW_API_DEF(SW_API_COSMAP_EG_REMARK_SET, fal_cosmap_egress_remark_set), \ - SW_API_DEF(SW_API_COSMAP_EG_REMARK_GET, fal_cosmap_egress_remark_get), \ - SW_API_DEF(SW_API_COSMAP_DSCP_TO_EHPRI_SET, fal_cosmap_dscp_to_ehpri_set), \ - SW_API_DEF(SW_API_COSMAP_DSCP_TO_EHPRI_GET, fal_cosmap_dscp_to_ehpri_get), \ - SW_API_DEF(SW_API_COSMAP_DSCP_TO_EHDP_SET, fal_cosmap_dscp_to_ehdp_set), \ - SW_API_DEF(SW_API_COSMAP_DSCP_TO_EHDP_GET, fal_cosmap_dscp_to_ehdp_get), \ - SW_API_DEF(SW_API_COSMAP_UP_TO_EHPRI_SET, fal_cosmap_up_to_ehpri_set), \ - SW_API_DEF(SW_API_COSMAP_UP_TO_EHPRI_GET, fal_cosmap_up_to_ehpri_get), \ - SW_API_DEF(SW_API_COSMAP_UP_TO_EHDP_SET, fal_cosmap_up_to_ehdp_set), \ - SW_API_DEF(SW_API_COSMAP_UP_TO_EHDP_GET, fal_cosmap_up_to_ehdp_get), - -#define COSMAP_API_PARAM \ - SW_API_DESC(SW_API_COSMAP_DSCP_TO_PRI_SET) \ - SW_API_DESC(SW_API_COSMAP_DSCP_TO_PRI_GET) \ - SW_API_DESC(SW_API_COSMAP_DSCP_TO_DP_SET) \ - SW_API_DESC(SW_API_COSMAP_DSCP_TO_DP_GET) \ - SW_API_DESC(SW_API_COSMAP_UP_TO_PRI_SET) \ - SW_API_DESC(SW_API_COSMAP_UP_TO_PRI_GET) \ - SW_API_DESC(SW_API_COSMAP_UP_TO_DP_SET) \ - SW_API_DESC(SW_API_COSMAP_UP_TO_DP_GET) \ - SW_API_DESC(SW_API_COSMAP_PRI_TO_QU_SET) \ - SW_API_DESC(SW_API_COSMAP_PRI_TO_QU_GET) \ - SW_API_DESC(SW_API_COSMAP_PRI_TO_EHQU_SET) \ - SW_API_DESC(SW_API_COSMAP_PRI_TO_EHQU_GET) \ - SW_API_DESC(SW_API_COSMAP_EG_REMARK_SET) \ - SW_API_DESC(SW_API_COSMAP_EG_REMARK_GET) \ - SW_API_DESC(SW_API_COSMAP_DSCP_TO_EHPRI_SET) \ - SW_API_DESC(SW_API_COSMAP_DSCP_TO_EHPRI_GET) \ - SW_API_DESC(SW_API_COSMAP_DSCP_TO_EHDP_SET) \ - SW_API_DESC(SW_API_COSMAP_DSCP_TO_EHDP_GET) \ - SW_API_DESC(SW_API_COSMAP_UP_TO_EHPRI_SET) \ - SW_API_DESC(SW_API_COSMAP_UP_TO_EHPRI_GET) \ - SW_API_DESC(SW_API_COSMAP_UP_TO_EHDP_SET) \ - SW_API_DESC(SW_API_COSMAP_UP_TO_EHDP_GET) -#else -#define COSMAP_API \ - SW_API_DEF(SW_API_COSMAP_PRI_TO_QU_SET, fal_cosmap_pri_to_queue_set), \ - SW_API_DEF(SW_API_COSMAP_PRI_TO_EHQU_SET, fal_cosmap_pri_to_ehqueue_set), - -#define COSMAP_API_PARAM \ - SW_API_DESC(SW_API_COSMAP_PRI_TO_QU_SET) \ - SW_API_DESC(SW_API_COSMAP_PRI_TO_EHQU_SET) -#endif -#else -#define COSMAP_API -#define COSMAP_API_PARAM -#endif - -#ifdef IN_SEC -#define SEC_API \ - SW_API_DEF(SW_API_SEC_NORM_SET, fal_sec_norm_item_set), \ - SW_API_DEF(SW_API_SEC_NORM_GET, fal_sec_norm_item_get), \ - SW_API_DEF(SW_API_SEC_MAC_SET, fal_sec_norm_item_set), \ - SW_API_DEF(SW_API_SEC_MAC_GET, fal_sec_norm_item_get), \ - SW_API_DEF(SW_API_SEC_IP_SET, fal_sec_norm_item_set), \ - SW_API_DEF(SW_API_SEC_IP_GET, fal_sec_norm_item_get), \ - SW_API_DEF(SW_API_SEC_IP4_SET, fal_sec_norm_item_set), \ - SW_API_DEF(SW_API_SEC_IP4_GET, fal_sec_norm_item_get), \ - SW_API_DEF(SW_API_SEC_IP6_SET, fal_sec_norm_item_set), \ - SW_API_DEF(SW_API_SEC_IP6_GET, fal_sec_norm_item_get), \ - SW_API_DEF(SW_API_SEC_TCP_SET, fal_sec_norm_item_set), \ - SW_API_DEF(SW_API_SEC_TCP_GET, fal_sec_norm_item_get), \ - SW_API_DEF(SW_API_SEC_UDP_SET, fal_sec_norm_item_set), \ - SW_API_DEF(SW_API_SEC_UDP_GET, fal_sec_norm_item_get), \ - SW_API_DEF(SW_API_SEC_ICMP4_SET, fal_sec_norm_item_set), \ - SW_API_DEF(SW_API_SEC_ICMP4_GET, fal_sec_norm_item_get), \ - SW_API_DEF(SW_API_SEC_ICMP6_SET, fal_sec_norm_item_set), \ - SW_API_DEF(SW_API_SEC_ICMP6_GET, fal_sec_norm_item_get), \ - SW_API_DEF(SW_API_SEC_L3_PARSER_CTRL_GET, fal_sec_l3_excep_parser_ctrl_get), \ - SW_API_DEF(SW_API_SEC_L3_PARSER_CTRL_SET, fal_sec_l3_excep_parser_ctrl_set), \ - SW_API_DEF(SW_API_SEC_L4_PARSER_CTRL_GET, fal_sec_l4_excep_parser_ctrl_get), \ - SW_API_DEF(SW_API_SEC_L4_PARSER_CTRL_SET, fal_sec_l4_excep_parser_ctrl_set), \ - SW_API_DEF(SW_API_SEC_EXP_CTRL_GET, fal_sec_l3_excep_ctrl_get), \ - SW_API_DEF(SW_API_SEC_EXP_CTRL_SET, fal_sec_l3_excep_ctrl_set), - -#define SEC_API_PARAM \ - SW_API_DESC(SW_API_SEC_NORM_SET) \ - SW_API_DESC(SW_API_SEC_NORM_GET) \ - SW_API_DESC(SW_API_SEC_MAC_SET) \ - SW_API_DESC(SW_API_SEC_MAC_GET) \ - SW_API_DESC(SW_API_SEC_IP_SET) \ - SW_API_DESC(SW_API_SEC_IP_GET) \ - SW_API_DESC(SW_API_SEC_IP4_SET) \ - SW_API_DESC(SW_API_SEC_IP4_GET) \ - SW_API_DESC(SW_API_SEC_IP6_SET) \ - SW_API_DESC(SW_API_SEC_IP6_GET) \ - SW_API_DESC(SW_API_SEC_TCP_SET) \ - SW_API_DESC(SW_API_SEC_TCP_GET) \ - SW_API_DESC(SW_API_SEC_UDP_SET) \ - SW_API_DESC(SW_API_SEC_UDP_GET) \ - SW_API_DESC(SW_API_SEC_ICMP4_SET) \ - SW_API_DESC(SW_API_SEC_ICMP4_GET) \ - SW_API_DESC(SW_API_SEC_ICMP6_SET) \ - SW_API_DESC(SW_API_SEC_ICMP6_GET) \ - SW_API_DESC(SW_API_SEC_L3_PARSER_CTRL_GET) \ - SW_API_DESC(SW_API_SEC_L3_PARSER_CTRL_SET) \ - SW_API_DESC(SW_API_SEC_L4_PARSER_CTRL_GET) \ - SW_API_DESC(SW_API_SEC_L4_PARSER_CTRL_SET) \ - SW_API_DESC(SW_API_SEC_EXP_CTRL_GET) \ - SW_API_DESC(SW_API_SEC_EXP_CTRL_SET) -#else -#define SEC_API -#define SEC_API_PARAM -#endif - -#ifdef IN_IP -#ifndef IN_IP_MINI -#define IP_API \ - SW_API_DEF(SW_API_IP_HOST_ADD, fal_ip_host_add), \ - SW_API_DEF(SW_API_IP_HOST_DEL, fal_ip_host_del), \ - SW_API_DEF(SW_API_IP_HOST_GET, fal_ip_host_get), \ - SW_API_DEF(SW_API_IP_HOST_NEXT, fal_ip_host_next), \ - SW_API_DEF(SW_API_IP_HOST_COUNTER_BIND, fal_ip_host_counter_bind), \ - SW_API_DEF(SW_API_IP_HOST_PPPOE_BIND, fal_ip_host_pppoe_bind), \ - SW_API_DEF(SW_API_IP_PT_ARP_LEARN_SET, fal_ip_pt_arp_learn_set), \ - SW_API_DEF(SW_API_IP_PT_ARP_LEARN_GET, fal_ip_pt_arp_learn_get), \ - SW_API_DEF(SW_API_IP_ARP_LEARN_SET, fal_ip_arp_learn_set), \ - SW_API_DEF(SW_API_IP_ARP_LEARN_GET, fal_ip_arp_learn_get), \ - SW_API_DEF(SW_API_IP_SOURCE_GUARD_SET, fal_ip_source_guard_set), \ - SW_API_DEF(SW_API_IP_SOURCE_GUARD_GET, fal_ip_source_guard_get), \ - SW_API_DEF(SW_API_IP_ARP_GUARD_SET, fal_ip_arp_guard_set), \ - SW_API_DEF(SW_API_IP_ARP_GUARD_GET, fal_ip_arp_guard_get), \ - SW_API_DEF(SW_API_IP_ROUTE_STATUS_SET, fal_ip_route_status_set), \ - SW_API_DEF(SW_API_IP_ROUTE_STATUS_GET, fal_ip_route_status_get), \ - SW_API_DEF(SW_API_IP_INTF_ENTRY_ADD, fal_ip_intf_entry_add), \ - SW_API_DEF(SW_API_IP_INTF_ENTRY_DEL, fal_ip_intf_entry_del), \ - SW_API_DEF(SW_API_IP_INTF_ENTRY_NEXT, fal_ip_intf_entry_next), \ - SW_API_DEF(SW_API_IP_UNK_SOURCE_CMD_SET, fal_ip_unk_source_cmd_set), \ - SW_API_DEF(SW_API_IP_UNK_SOURCE_CMD_GET, fal_ip_unk_source_cmd_get), \ - SW_API_DEF(SW_API_ARP_UNK_SOURCE_CMD_SET, fal_arp_unk_source_cmd_set), \ - SW_API_DEF(SW_API_ARP_UNK_SOURCE_CMD_GET, fal_arp_unk_source_cmd_get), \ - SW_API_DEF(SW_API_IP_AGE_TIME_SET, fal_ip_age_time_set), \ - SW_API_DEF(SW_API_IP_AGE_TIME_GET, fal_ip_age_time_get), \ - SW_API_DEF(SW_API_WCMP_HASH_MODE_SET, fal_ip_wcmp_hash_mode_set), \ - SW_API_DEF(SW_API_WCMP_HASH_MODE_GET, fal_ip_wcmp_hash_mode_get), \ - SW_API_DEF(SW_API_IP_VRF_BASE_ADDR_SET, fal_ip_vrf_base_addr_set), \ - SW_API_DEF(SW_API_IP_VRF_BASE_ADDR_GET, fal_ip_vrf_base_addr_get), \ - SW_API_DEF(SW_API_IP_VRF_BASE_MASK_SET, fal_ip_vrf_base_mask_set), \ - SW_API_DEF(SW_API_IP_VRF_BASE_MASK_GET, fal_ip_vrf_base_mask_get), \ - SW_API_DEF(SW_API_IP_DEFAULT_ROUTE_SET, fal_ip_default_route_set), \ - SW_API_DEF(SW_API_IP_DEFAULT_ROUTE_GET, fal_ip_default_route_get), \ - SW_API_DEF(SW_API_IP_HOST_ROUTE_SET, fal_ip_host_route_set), \ - SW_API_DEF(SW_API_IP_HOST_ROUTE_GET, fal_ip_host_route_get), \ - SW_API_DEF(SW_API_IP_WCMP_ENTRY_SET, fal_ip_wcmp_entry_set), \ - SW_API_DEF(SW_API_IP_WCMP_ENTRY_GET, fal_ip_wcmp_entry_get), \ - SW_API_DEF(SW_API_IP_RFS_IP4_SET, fal_ip_rfs_ip4_rule_set), \ - SW_API_DEF(SW_API_IP_RFS_IP6_SET, fal_ip_rfs_ip6_rule_set), \ - SW_API_DEF(SW_API_IP_RFS_IP4_DEL, fal_ip_rfs_ip4_rule_del), \ - SW_API_DEF(SW_API_IP_RFS_IP6_DEL, fal_ip_rfs_ip6_rule_del), \ - SW_API_DEF(SW_API_IP_DEFAULT_FLOW_CMD_SET, fal_default_flow_cmd_set), \ - SW_API_DEF(SW_API_IP_DEFAULT_FLOW_CMD_GET, fal_default_flow_cmd_get), \ - SW_API_DEF(SW_API_IP_DEFAULT_RT_FLOW_CMD_SET, fal_default_rt_flow_cmd_set), \ - SW_API_DEF(SW_API_IP_DEFAULT_RT_FLOW_CMD_GET, fal_default_rt_flow_cmd_get), \ - SW_API_DEF(SW_API_IP_VIS_ARP_SG_CFG_GET, fal_ip_vsi_arp_sg_cfg_get), \ - SW_API_DEF(SW_API_IP_VIS_ARP_SG_CFG_SET, fal_ip_vsi_arp_sg_cfg_set), \ - SW_API_DEF(SW_API_IP_NETWORK_ROUTE_GET, fal_ip_network_route_get), \ - SW_API_DEF(SW_API_IP_NETWORK_ROUTE_ADD, fal_ip_network_route_add), \ - SW_API_DEF(SW_API_IP_INTF_GET, fal_ip_intf_get), \ - SW_API_DEF(SW_API_IP_INTF_SET, fal_ip_intf_set), \ - SW_API_DEF(SW_API_IP_VSI_INTF_GET, fal_ip_vsi_intf_get), \ - SW_API_DEF(SW_API_IP_VSI_INTF_SET, fal_ip_vsi_intf_set), \ - SW_API_DEF(SW_API_IP_NEXTHOP_GET, fal_ip_nexthop_get), \ - SW_API_DEF(SW_API_IP_NEXTHOP_SET, fal_ip_nexthop_set), \ - SW_API_DEF(SW_API_IP_VSI_SG_SET, fal_ip_vsi_sg_cfg_set), \ - SW_API_DEF(SW_API_IP_VSI_SG_GET, fal_ip_vsi_sg_cfg_get), \ - SW_API_DEF(SW_API_IP_PORT_SG_SET, fal_ip_port_sg_cfg_set), \ - SW_API_DEF(SW_API_IP_PORT_SG_GET, fal_ip_port_sg_cfg_get), \ - SW_API_DEF(SW_API_IP_PUB_IP_SET, fal_ip_pub_addr_set), \ - SW_API_DEF(SW_API_IP_PUB_IP_GET, fal_ip_pub_addr_get), \ - SW_API_DEF(SW_API_IP_NETWORK_ROUTE_DEL, fal_ip_network_route_del), \ - SW_API_DEF(SW_API_IP_PORT_INTF_GET, fal_ip_port_intf_get), \ - SW_API_DEF(SW_API_IP_PORT_INTF_SET, fal_ip_port_intf_set), \ - SW_API_DEF(SW_API_IP_PORT_MAC_GET, fal_ip_port_macaddr_get), \ - SW_API_DEF(SW_API_IP_PORT_MAC_SET, fal_ip_port_macaddr_set), \ - SW_API_DEF(SW_API_IP_ROUTE_MISS_GET, fal_ip_route_mismatch_action_get), \ - SW_API_DEF(SW_API_IP_ROUTE_MISS_SET, fal_ip_route_mismatch_action_set), \ - SW_API_DEF(SW_API_IP_PORT_ARP_SG_SET, fal_ip_port_arp_sg_cfg_set), \ - SW_API_DEF(SW_API_IP_PORT_ARP_SG_GET, fal_ip_port_arp_sg_cfg_get), \ - SW_API_DEF(SW_API_IP_VSI_MC_MODE_SET, fal_ip_vsi_mc_mode_set), \ - SW_API_DEF(SW_API_IP_VSI_MC_MODE_GET, fal_ip_vsi_mc_mode_get), \ - SW_API_DEF(SW_API_GLOBAL_CTRL_GET, fal_ip_global_ctrl_get), \ - SW_API_DEF(SW_API_GLOBAL_CTRL_SET, fal_ip_global_ctrl_set), - -#define IP_API_PARAM \ - SW_API_DESC(SW_API_IP_HOST_ADD) \ - SW_API_DESC(SW_API_IP_HOST_DEL) \ - SW_API_DESC(SW_API_IP_HOST_GET) \ - SW_API_DESC(SW_API_IP_HOST_NEXT) \ - SW_API_DESC(SW_API_IP_HOST_COUNTER_BIND) \ - SW_API_DESC(SW_API_IP_HOST_PPPOE_BIND) \ - SW_API_DESC(SW_API_IP_PT_ARP_LEARN_SET) \ - SW_API_DESC(SW_API_IP_PT_ARP_LEARN_GET) \ - SW_API_DESC(SW_API_IP_ARP_LEARN_SET) \ - SW_API_DESC(SW_API_IP_ARP_LEARN_GET) \ - SW_API_DESC(SW_API_IP_SOURCE_GUARD_SET) \ - SW_API_DESC(SW_API_IP_SOURCE_GUARD_GET) \ - SW_API_DESC(SW_API_IP_ARP_GUARD_SET) \ - SW_API_DESC(SW_API_IP_ARP_GUARD_GET) \ - SW_API_DESC(SW_API_IP_ROUTE_STATUS_SET) \ - SW_API_DESC(SW_API_IP_ROUTE_STATUS_GET) \ - SW_API_DESC(SW_API_IP_INTF_ENTRY_ADD) \ - SW_API_DESC(SW_API_IP_INTF_ENTRY_DEL) \ - SW_API_DESC(SW_API_IP_INTF_ENTRY_NEXT) \ - SW_API_DESC(SW_API_IP_UNK_SOURCE_CMD_SET) \ - SW_API_DESC(SW_API_IP_UNK_SOURCE_CMD_GET) \ - SW_API_DESC(SW_API_ARP_UNK_SOURCE_CMD_SET) \ - SW_API_DESC(SW_API_ARP_UNK_SOURCE_CMD_GET) \ - SW_API_DESC(SW_API_IP_AGE_TIME_SET) \ - SW_API_DESC(SW_API_IP_AGE_TIME_GET) \ - SW_API_DESC(SW_API_WCMP_HASH_MODE_SET) \ - SW_API_DESC(SW_API_WCMP_HASH_MODE_GET) \ - SW_API_DESC(SW_API_IP_VRF_BASE_ADDR_SET) \ - SW_API_DESC(SW_API_IP_VRF_BASE_ADDR_GET) \ - SW_API_DESC(SW_API_IP_VRF_BASE_MASK_SET) \ - SW_API_DESC(SW_API_IP_VRF_BASE_MASK_GET) \ - SW_API_DESC(SW_API_IP_DEFAULT_ROUTE_SET) \ - SW_API_DESC(SW_API_IP_DEFAULT_ROUTE_GET) \ - SW_API_DESC(SW_API_IP_HOST_ROUTE_SET) \ - SW_API_DESC(SW_API_IP_HOST_ROUTE_GET) \ - SW_API_DESC(SW_API_IP_WCMP_ENTRY_SET) \ - SW_API_DESC(SW_API_IP_WCMP_ENTRY_GET) \ - SW_API_DESC(SW_API_IP_RFS_IP4_SET) \ - SW_API_DESC(SW_API_IP_RFS_IP6_SET) \ - SW_API_DESC(SW_API_IP_RFS_IP4_DEL) \ - SW_API_DESC(SW_API_IP_RFS_IP6_DEL) \ - SW_API_DESC(SW_API_IP_DEFAULT_FLOW_CMD_SET) \ - SW_API_DESC(SW_API_IP_DEFAULT_FLOW_CMD_GET) \ - SW_API_DESC(SW_API_IP_DEFAULT_RT_FLOW_CMD_SET) \ - SW_API_DESC(SW_API_IP_DEFAULT_RT_FLOW_CMD_GET) \ - SW_API_DESC(SW_API_IP_VIS_ARP_SG_CFG_GET) \ - SW_API_DESC(SW_API_IP_VIS_ARP_SG_CFG_SET) \ - SW_API_DESC(SW_API_IP_NETWORK_ROUTE_GET) \ - SW_API_DESC(SW_API_IP_NETWORK_ROUTE_ADD) \ - SW_API_DESC(SW_API_IP_INTF_GET) \ - SW_API_DESC(SW_API_IP_INTF_SET) \ - SW_API_DESC(SW_API_IP_VSI_INTF_GET) \ - SW_API_DESC(SW_API_IP_VSI_INTF_SET) \ - SW_API_DESC(SW_API_IP_NEXTHOP_GET) \ - SW_API_DESC(SW_API_IP_NEXTHOP_SET) \ - SW_API_DESC(SW_API_IP_VSI_SG_SET) \ - SW_API_DESC(SW_API_IP_VSI_SG_GET) \ - SW_API_DESC(SW_API_IP_PORT_SG_SET) \ - SW_API_DESC(SW_API_IP_PORT_SG_GET) \ - SW_API_DESC(SW_API_IP_PUB_IP_SET) \ - SW_API_DESC(SW_API_IP_PUB_IP_GET) \ - SW_API_DESC(SW_API_IP_NETWORK_ROUTE_DEL) \ - SW_API_DESC(SW_API_IP_PORT_INTF_GET) \ - SW_API_DESC(SW_API_IP_PORT_INTF_SET) \ - SW_API_DESC(SW_API_IP_PORT_MAC_GET) \ - SW_API_DESC(SW_API_IP_PORT_MAC_SET) \ - SW_API_DESC(SW_API_IP_ROUTE_MISS_GET) \ - SW_API_DESC(SW_API_IP_ROUTE_MISS_SET) \ - SW_API_DESC(SW_API_IP_PORT_ARP_SG_SET) \ - SW_API_DESC(SW_API_IP_PORT_ARP_SG_GET) \ - SW_API_DESC(SW_API_IP_VSI_MC_MODE_SET) \ - SW_API_DESC(SW_API_IP_VSI_MC_MODE_GET) \ - SW_API_DESC(SW_API_GLOBAL_CTRL_GET) \ - SW_API_DESC(SW_API_GLOBAL_CTRL_SET) -#else -#define IP_API -#define IP_API_PARAM -#endif -#else -#define IP_API -#define IP_API_PARAM -#endif - -#ifdef IN_FLOW -#ifndef IN_FLOW_MINI -#define FLOW_API \ - SW_API_DEF(SW_API_FLOW_STATUS_SET, fal_flow_status_set), \ - SW_API_DEF(SW_API_FLOW_STATUS_GET, fal_flow_status_get), \ - SW_API_DEF(SW_API_FLOW_AGE_TIMER_SET, fal_flow_age_timer_set), \ - SW_API_DEF(SW_API_FLOW_AGE_TIMER_GET, fal_flow_age_timer_get), \ - SW_API_DEF(SW_API_FLOW_CTRL_SET, fal_flow_mgmt_set), \ - SW_API_DEF(SW_API_FLOW_CTRL_GET, fal_flow_mgmt_get), \ - SW_API_DEF(SW_API_FLOW_ENTRY_ADD, fal_flow_entry_add), \ - SW_API_DEF(SW_API_FLOW_ENTRY_DEL, fal_flow_entry_del), \ - SW_API_DEF(SW_API_FLOW_ENTRY_GET, fal_flow_entry_get), \ - SW_API_DEF(SW_API_FLOW_GLOBAL_CFG_GET, fal_flow_global_cfg_get), \ - SW_API_DEF(SW_API_FLOW_GLOBAL_CFG_SET, fal_flow_global_cfg_set), \ - SW_API_DEF(SW_API_FLOW_HOST_ADD, fal_flow_host_add), \ - SW_API_DEF(SW_API_FLOW_HOST_GET, fal_flow_host_get), \ - SW_API_DEF(SW_API_FLOW_HOST_DEL, fal_flow_host_del), \ - SW_API_DEF(SW_API_FLOWENTRY_NEXT, fal_flow_entry_next), - -#define FLOW_API_PARAM \ - SW_API_DESC(SW_API_FLOW_STATUS_SET) \ - SW_API_DESC(SW_API_FLOW_STATUS_GET) \ - SW_API_DESC(SW_API_FLOW_AGE_TIMER_SET) \ - SW_API_DESC(SW_API_FLOW_AGE_TIMER_GET) \ - SW_API_DESC(SW_API_FLOW_CTRL_SET) \ - SW_API_DESC(SW_API_FLOW_CTRL_GET) \ - SW_API_DESC(SW_API_FLOW_ENTRY_ADD) \ - SW_API_DESC(SW_API_FLOW_ENTRY_DEL) \ - SW_API_DESC(SW_API_FLOW_ENTRY_GET) \ - SW_API_DESC(SW_API_FLOW_GLOBAL_CFG_GET) \ - SW_API_DESC(SW_API_FLOW_GLOBAL_CFG_SET) \ - SW_API_DESC(SW_API_FLOW_HOST_ADD) \ - SW_API_DESC(SW_API_FLOW_HOST_GET) \ - SW_API_DESC(SW_API_FLOW_HOST_DEL) \ - SW_API_DESC(SW_API_FLOWENTRY_NEXT) -#else -#define FLOW_API \ - SW_API_DEF(SW_API_FLOW_CTRL_SET, fal_flow_mgmt_set), \ - SW_API_DEF(SW_API_FLOW_CTRL_GET, fal_flow_mgmt_get), - -#define FLOW_API_PARAM \ - SW_API_DESC(SW_API_FLOW_CTRL_SET) \ - SW_API_DESC(SW_API_FLOW_CTRL_GET) -#endif -#else -#define FLOW_API -#define FLOW_API_PARAM -#endif - - -#ifdef IN_NAT -#define NAT_API \ - SW_API_DEF(SW_API_NAT_ADD, fal_nat_add), \ - SW_API_DEF(SW_API_NAT_DEL, fal_nat_del), \ - SW_API_DEF(SW_API_NAT_GET, fal_nat_get), \ - SW_API_DEF(SW_API_NAT_NEXT, fal_nat_next), \ - SW_API_DEF(SW_API_NAT_COUNTER_BIND, fal_nat_counter_bind), \ - SW_API_DEF(SW_API_NAPT_ADD, fal_napt_add), \ - SW_API_DEF(SW_API_NAPT_DEL, fal_napt_del), \ - SW_API_DEF(SW_API_NAPT_GET, fal_napt_get), \ - SW_API_DEF(SW_API_NAPT_NEXT, fal_napt_next), \ - SW_API_DEF(SW_API_NAPT_COUNTER_BIND, fal_napt_counter_bind), \ - SW_API_DEF(SW_API_FLOW_ADD, fal_flow_add), \ - SW_API_DEF(SW_API_FLOW_DEL, fal_flow_del), \ - SW_API_DEF(SW_API_FLOW_GET, fal_flow_get), \ - SW_API_DEF(SW_API_FLOW_NEXT, fal_flow_next), \ - SW_API_DEF(SW_API_FLOW_COUNTER_BIND, fal_flow_counter_bind), \ - SW_API_DEF(SW_API_NAT_STATUS_SET, fal_nat_status_set), \ - SW_API_DEF(SW_API_NAT_STATUS_GET, fal_nat_status_get), \ - SW_API_DEF(SW_API_NAT_HASH_MODE_SET, fal_nat_hash_mode_set), \ - SW_API_DEF(SW_API_NAT_HASH_MODE_GET, fal_nat_hash_mode_get), \ - SW_API_DEF(SW_API_NAPT_STATUS_SET, fal_napt_status_set), \ - SW_API_DEF(SW_API_NAPT_STATUS_GET, fal_napt_status_get), \ - SW_API_DEF(SW_API_NAPT_MODE_SET, fal_napt_mode_set), \ - SW_API_DEF(SW_API_NAPT_MODE_GET, fal_napt_mode_get), \ - SW_API_DEF(SW_API_PRV_BASE_ADDR_SET, fal_nat_prv_base_addr_set), \ - SW_API_DEF(SW_API_PRV_BASE_ADDR_GET, fal_nat_prv_base_addr_get), \ - SW_API_DEF(SW_API_PRV_ADDR_MODE_SET, fal_nat_prv_addr_mode_set), \ - SW_API_DEF(SW_API_PRV_ADDR_MODE_GET, fal_nat_prv_addr_mode_get), \ - SW_API_DEF(SW_API_PUB_ADDR_ENTRY_ADD, fal_nat_pub_addr_add), \ - SW_API_DEF(SW_API_PUB_ADDR_ENTRY_DEL, fal_nat_pub_addr_del), \ - SW_API_DEF(SW_API_PUB_ADDR_ENTRY_NEXT, fal_nat_pub_addr_next), \ - SW_API_DEF(SW_API_NAT_UNK_SESSION_CMD_SET, fal_nat_unk_session_cmd_set), \ - SW_API_DEF(SW_API_NAT_UNK_SESSION_CMD_GET, fal_nat_unk_session_cmd_get), \ - SW_API_DEF(SW_API_PRV_BASE_MASK_SET, fal_nat_prv_base_mask_set), \ - SW_API_DEF(SW_API_PRV_BASE_MASK_GET, fal_nat_prv_base_mask_get), \ - SW_API_DEF(SW_API_NAT_GLOBAL_SET, fal_nat_global_set), \ - SW_API_DEF(SW_API_FLOW_COOKIE_SET, fal_flow_cookie_set), \ - SW_API_DEF(SW_API_FLOW_RFS_SET, fal_flow_rfs_set), - -#define NAT_API_PARAM \ - SW_API_DESC(SW_API_NAT_ADD) \ - SW_API_DESC(SW_API_NAT_DEL) \ - SW_API_DESC(SW_API_NAT_GET) \ - SW_API_DESC(SW_API_NAT_NEXT) \ - SW_API_DESC(SW_API_NAT_COUNTER_BIND) \ - SW_API_DESC(SW_API_NAPT_ADD) \ - SW_API_DESC(SW_API_NAPT_DEL) \ - SW_API_DESC(SW_API_NAPT_GET) \ - SW_API_DESC(SW_API_NAPT_NEXT) \ - SW_API_DESC(SW_API_NAPT_COUNTER_BIND) \ - SW_API_DESC(SW_API_FLOW_ADD) \ - SW_API_DESC(SW_API_FLOW_DEL) \ - SW_API_DESC(SW_API_FLOW_GET) \ - SW_API_DESC(SW_API_FLOW_NEXT) \ - SW_API_DESC(SW_API_FLOW_COUNTER_BIND) \ - SW_API_DESC(SW_API_NAT_STATUS_SET) \ - SW_API_DESC(SW_API_NAT_STATUS_GET) \ - SW_API_DESC(SW_API_NAT_HASH_MODE_SET) \ - SW_API_DESC(SW_API_NAT_HASH_MODE_GET) \ - SW_API_DESC(SW_API_NAPT_STATUS_SET) \ - SW_API_DESC(SW_API_NAPT_STATUS_GET) \ - SW_API_DESC(SW_API_NAPT_MODE_SET) \ - SW_API_DESC(SW_API_NAPT_MODE_GET) \ - SW_API_DESC(SW_API_PRV_BASE_ADDR_SET) \ - SW_API_DESC(SW_API_PRV_BASE_ADDR_GET) \ - SW_API_DESC(SW_API_PRV_ADDR_MODE_SET) \ - SW_API_DESC(SW_API_PRV_ADDR_MODE_GET) \ - SW_API_DESC(SW_API_PUB_ADDR_ENTRY_ADD) \ - SW_API_DESC(SW_API_PUB_ADDR_ENTRY_DEL) \ - SW_API_DESC(SW_API_PUB_ADDR_ENTRY_NEXT) \ - SW_API_DESC(SW_API_NAT_UNK_SESSION_CMD_SET) \ - SW_API_DESC(SW_API_NAT_UNK_SESSION_CMD_GET) \ - SW_API_DESC(SW_API_PRV_BASE_MASK_SET) \ - SW_API_DESC(SW_API_PRV_BASE_MASK_GET) \ - SW_API_DESC(SW_API_NAT_GLOBAL_SET) \ - SW_API_DESC(SW_API_FLOW_COOKIE_SET) \ - SW_API_DESC(SW_API_FLOW_RFS_SET) -#else -#define NAT_API -#define NAT_API_PARAM -#endif - -#ifdef IN_TRUNK -#define TRUNK_API \ - SW_API_DEF(SW_API_TRUNK_GROUP_SET, fal_trunk_group_set), \ - SW_API_DEF(SW_API_TRUNK_GROUP_GET, fal_trunk_group_get), \ - SW_API_DEF(SW_API_TRUNK_HASH_SET, fal_trunk_hash_mode_set), \ - SW_API_DEF(SW_API_TRUNK_HASH_GET, fal_trunk_hash_mode_get), \ - SW_API_DEF(SW_API_TRUNK_MAN_SA_SET, fal_trunk_manipulate_sa_set), \ - SW_API_DEF(SW_API_TRUNK_MAN_SA_GET, fal_trunk_manipulate_sa_get), \ - SW_API_DEF(SW_API_TRUNK_FAILOVER_EN_SET, fal_trunk_failover_enable), \ - SW_API_DEF(SW_API_TRUNK_FAILOVER_EN_GET, fal_trunk_failover_status_get), - -#define TRUNK_API_PARAM \ - SW_API_DESC(SW_API_TRUNK_GROUP_SET) \ - SW_API_DESC(SW_API_TRUNK_GROUP_GET) \ - SW_API_DESC(SW_API_TRUNK_HASH_SET) \ - SW_API_DESC(SW_API_TRUNK_HASH_GET) \ - SW_API_DESC(SW_API_TRUNK_MAN_SA_SET)\ - SW_API_DESC(SW_API_TRUNK_MAN_SA_GET) \ - SW_API_DESC(SW_API_TRUNK_FAILOVER_EN_SET)\ - SW_API_DESC(SW_API_TRUNK_FAILOVER_EN_GET) -#else -#define TRUNK_API -#define TRUNK_API_PARAM -#endif - -#ifdef IN_INTERFACECONTROL -#define INTERFACECTRL_API \ - SW_API_DEF(SW_API_MAC_MODE_SET, fal_interface_mac_mode_set), \ - SW_API_DEF(SW_API_MAC_MODE_GET, fal_interface_mac_mode_get), \ - SW_API_DEF(SW_API_PORT_3AZ_STATUS_SET, fal_port_3az_status_set), \ - SW_API_DEF(SW_API_PORT_3AZ_STATUS_GET, fal_port_3az_status_get), \ - SW_API_DEF(SW_API_PHY_MODE_SET, fal_interface_phy_mode_set), \ - SW_API_DEF(SW_API_PHY_MODE_GET, fal_interface_phy_mode_get), \ - SW_API_DEF(SW_API_FX100_CTRL_SET, fal_interface_fx100_ctrl_set), \ - SW_API_DEF(SW_API_FX100_CTRL_GET, fal_interface_fx100_ctrl_get), \ - SW_API_DEF(SW_API_FX100_STATUS_GET, fal_interface_fx100_status_get),\ - SW_API_DEF(SW_API_MAC06_EXCH_SET, fal_interface_mac06_exch_set),\ - SW_API_DEF(SW_API_MAC06_EXCH_GET, fal_interface_mac06_exch_get), - -#define INTERFACECTRL_API_PARAM \ - SW_API_DESC(SW_API_MAC_MODE_SET) \ - SW_API_DESC(SW_API_MAC_MODE_GET) \ - SW_API_DESC(SW_API_PORT_3AZ_STATUS_SET) \ - SW_API_DESC(SW_API_PORT_3AZ_STATUS_GET) \ - SW_API_DESC(SW_API_PHY_MODE_SET) \ - SW_API_DESC(SW_API_PHY_MODE_GET) \ - SW_API_DESC(SW_API_FX100_CTRL_SET) \ - SW_API_DESC(SW_API_FX100_CTRL_GET) \ - SW_API_DESC(SW_API_FX100_STATUS_GET) \ - SW_API_DESC(SW_API_MAC06_EXCH_SET) \ - SW_API_DESC(SW_API_MAC06_EXCH_GET) - -#else -#define INTERFACECTRL_API -#define INTERFACECTRL_API_PARAM -#endif - -#ifdef IN_VSI -#ifndef IN_VSI_MINI -#define VSI_API \ - SW_API_DEF(SW_API_VSI_ALLOC, ppe_vsi_alloc), \ - SW_API_DEF(SW_API_VSI_FREE, ppe_vsi_free), \ - SW_API_DEF(SW_API_PORT_VSI_SET, fal_port_vsi_set), \ - SW_API_DEF(SW_API_PORT_VSI_GET, fal_port_vsi_get), \ - SW_API_DEF(SW_API_PORT_VLAN_VSI_SET, ppe_port_vlan_vsi_set), \ - SW_API_DEF(SW_API_PORT_VLAN_VSI_GET, ppe_port_vlan_vsi_get), \ - SW_API_DEF(SW_API_VSI_TBL_DUMP, ppe_vsi_tbl_dump), \ - SW_API_DEF(SW_API_VSI_NEWADDR_LRN_GET, fal_vsi_newaddr_lrn_get), \ - SW_API_DEF(SW_API_VSI_NEWADDR_LRN_SET, fal_vsi_newaddr_lrn_set), \ - SW_API_DEF(SW_API_VSI_STAMOVE_SET, fal_vsi_stamove_set), \ - SW_API_DEF(SW_API_VSI_STAMOVE_GET,fal_vsi_stamove_get), \ - SW_API_DEF(SW_API_VSI_MEMBER_SET, fal_vsi_member_set), \ - SW_API_DEF(SW_API_VSI_MEMBER_GET, fal_vsi_member_get), \ - SW_API_DEF(SW_API_VSI_COUNTER_GET,fal_vsi_counter_get), \ - SW_API_DEF(SW_API_VSI_COUNTER_CLEANUP,fal_vsi_counter_cleanup), - - -#define VSI_API_PARAM \ - SW_API_DESC(SW_API_VSI_ALLOC) \ - SW_API_DESC(SW_API_VSI_FREE) \ - SW_API_DESC(SW_API_PORT_VSI_SET) \ - SW_API_DESC(SW_API_PORT_VSI_GET) \ - SW_API_DESC(SW_API_PORT_VLAN_VSI_SET) \ - SW_API_DESC(SW_API_PORT_VLAN_VSI_GET) \ - SW_API_DESC(SW_API_VSI_TBL_DUMP) \ - SW_API_DESC(SW_API_VSI_NEWADDR_LRN_GET) \ - SW_API_DESC(SW_API_VSI_NEWADDR_LRN_SET) \ - SW_API_DESC(SW_API_VSI_STAMOVE_SET) \ - SW_API_DESC(SW_API_VSI_STAMOVE_GET) \ - SW_API_DESC(SW_API_VSI_MEMBER_SET) \ - SW_API_DESC(SW_API_VSI_MEMBER_GET) \ - SW_API_DESC(SW_API_VSI_COUNTER_GET) \ - SW_API_DESC(SW_API_VSI_COUNTER_CLEANUP) -#else -#define VSI_API \ - SW_API_DEF(SW_API_VSI_ALLOC, ppe_vsi_alloc), \ - SW_API_DEF(SW_API_VSI_FREE, ppe_vsi_free), \ - SW_API_DEF(SW_API_PORT_VSI_SET, fal_port_vsi_set), \ - SW_API_DEF(SW_API_PORT_VLAN_VSI_SET, ppe_port_vlan_vsi_set), \ - SW_API_DEF(SW_API_PORT_VLAN_VSI_GET, ppe_port_vlan_vsi_get), \ - SW_API_DEF(SW_API_VSI_TBL_DUMP, ppe_vsi_tbl_dump), \ - SW_API_DEF(SW_API_VSI_NEWADDR_LRN_SET, fal_vsi_newaddr_lrn_set), \ - SW_API_DEF(SW_API_VSI_STAMOVE_SET, fal_vsi_stamove_set), \ - SW_API_DEF(SW_API_VSI_MEMBER_SET, fal_vsi_member_set), \ - SW_API_DEF(SW_API_VSI_MEMBER_GET, fal_vsi_member_get), - - -#define VSI_API_PARAM \ - SW_API_DESC(SW_API_VSI_ALLOC) \ - SW_API_DESC(SW_API_VSI_FREE) \ - SW_API_DESC(SW_API_PORT_VSI_SET) \ - SW_API_DESC(SW_API_PORT_VLAN_VSI_SET) \ - SW_API_DESC(SW_API_PORT_VLAN_VSI_GET) \ - SW_API_DESC(SW_API_VSI_TBL_DUMP) \ - SW_API_DESC(SW_API_VSI_NEWADDR_LRN_SET) \ - SW_API_DESC(SW_API_VSI_STAMOVE_SET) \ - SW_API_DESC(SW_API_VSI_MEMBER_SET) \ - SW_API_DESC(SW_API_VSI_MEMBER_GET) -#endif -#else -#define VSI_API -#define VSI_API_PARAM -#endif - -#ifdef IN_QM -#ifndef IN_QM_MINI -#define QM_API \ - SW_API_DEF(SW_API_UCAST_QUEUE_BASE_PROFILE_SET, fal_ucast_queue_base_profile_set), \ - SW_API_DEF(SW_API_UCAST_QUEUE_BASE_PROFILE_GET, fal_ucast_queue_base_profile_get), \ - SW_API_DEF(SW_API_UCAST_PRIORITY_CLASS_SET, fal_ucast_priority_class_set), \ - SW_API_DEF(SW_API_UCAST_PRIORITY_CLASS_GET, fal_ucast_priority_class_get), \ - SW_API_DEF(SW_API_MCAST_PRIORITY_CLASS_SET, fal_port_mcast_priority_class_set), \ - SW_API_DEF(SW_API_MCAST_PRIORITY_CLASS_GET, fal_port_mcast_priority_class_get), \ - SW_API_DEF(SW_API_QUEUE_FLUSH, fal_queue_flush), \ - SW_API_DEF(SW_API_UCAST_HASH_MAP_SET, fal_ucast_hash_map_set), \ - SW_API_DEF(SW_API_UCAST_HASH_MAP_GET, fal_ucast_hash_map_get), \ - SW_API_DEF(SW_API_UCAST_DFLT_HASH_MAP_SET, fal_ucast_default_hash_set), \ - SW_API_DEF(SW_API_UCAST_DFLT_HASH_MAP_GET, fal_ucast_default_hash_get), \ - SW_API_DEF(SW_API_MCAST_CPUCODE_CLASS_SET, fal_mcast_cpu_code_class_set), \ - SW_API_DEF(SW_API_MCAST_CPUCODE_CLASS_GET, fal_mcast_cpu_code_class_get), \ - SW_API_DEF(SW_API_AC_CTRL_SET, fal_ac_ctrl_set), \ - SW_API_DEF(SW_API_AC_CTRL_GET, fal_ac_ctrl_get), \ - SW_API_DEF(SW_API_AC_PRE_BUFFER_SET, fal_ac_prealloc_buffer_set), \ - SW_API_DEF(SW_API_AC_PRE_BUFFER_GET, fal_ac_prealloc_buffer_get), \ - SW_API_DEF(SW_API_QUEUE_GROUP_SET, fal_ac_queue_group_set), \ - SW_API_DEF(SW_API_QUEUE_GROUP_GET, fal_ac_queue_group_get), \ - SW_API_DEF(SW_API_STATIC_THRESH_SET, fal_ac_static_threshold_set), \ - SW_API_DEF(SW_API_STATIC_THRESH_GET, fal_ac_static_threshold_get), \ - SW_API_DEF(SW_API_DYNAMIC_THRESH_SET, fal_ac_dynamic_threshold_set), \ - SW_API_DEF(SW_API_DYNAMIC_THRESH_GET, fal_ac_dynamic_threshold_get), \ - SW_API_DEF(SW_API_GOURP_BUFFER_SET, fal_ac_group_buffer_set), \ - SW_API_DEF(SW_API_GOURP_BUFFER_GET, fal_ac_group_buffer_get), \ - SW_API_DEF(SW_API_QUEUE_CNT_CTRL_GET, fal_queue_counter_ctrl_get), \ - SW_API_DEF(SW_API_QUEUE_CNT_CTRL_SET, fal_queue_counter_ctrl_set), \ - SW_API_DEF(SW_API_QUEUE_CNT_GET, fal_queue_counter_get), \ - SW_API_DEF(SW_API_QUEUE_CNT_CLEANUP, fal_queue_counter_cleanup), \ - SW_API_DEF(SW_API_QM_ENQUEUE_CTRL_SET, fal_qm_enqueue_ctrl_set), \ - SW_API_DEF(SW_API_QM_ENQUEUE_CTRL_GET, fal_qm_enqueue_ctrl_get), \ - SW_API_DEF(SW_API_QM_SOURCE_PROFILE_SET, fal_qm_port_source_profile_set), \ - SW_API_DEF(SW_API_QM_SOURCE_PROFILE_GET, fal_qm_port_source_profile_get), - -#define QM_API_PARAM \ - SW_API_DESC(SW_API_UCAST_QUEUE_BASE_PROFILE_SET) \ - SW_API_DESC(SW_API_UCAST_QUEUE_BASE_PROFILE_GET) \ - SW_API_DESC(SW_API_UCAST_PRIORITY_CLASS_SET) \ - SW_API_DESC(SW_API_UCAST_PRIORITY_CLASS_GET) \ - SW_API_DESC(SW_API_MCAST_PRIORITY_CLASS_SET) \ - SW_API_DESC(SW_API_MCAST_PRIORITY_CLASS_GET) \ - SW_API_DESC(SW_API_QUEUE_FLUSH) \ - SW_API_DESC(SW_API_UCAST_HASH_MAP_SET) \ - SW_API_DESC(SW_API_UCAST_HASH_MAP_GET) \ - SW_API_DESC(SW_API_UCAST_DFLT_HASH_MAP_SET) \ - SW_API_DESC(SW_API_UCAST_DFLT_HASH_MAP_GET) \ - SW_API_DESC(SW_API_MCAST_CPUCODE_CLASS_SET) \ - SW_API_DESC(SW_API_MCAST_CPUCODE_CLASS_GET) \ - SW_API_DESC(SW_API_AC_CTRL_SET) \ - SW_API_DESC(SW_API_AC_CTRL_GET) \ - SW_API_DESC(SW_API_AC_PRE_BUFFER_SET) \ - SW_API_DESC(SW_API_AC_PRE_BUFFER_GET) \ - SW_API_DESC(SW_API_QUEUE_GROUP_SET) \ - SW_API_DESC(SW_API_QUEUE_GROUP_GET) \ - SW_API_DESC(SW_API_STATIC_THRESH_SET) \ - SW_API_DESC(SW_API_STATIC_THRESH_GET) \ - SW_API_DESC(SW_API_DYNAMIC_THRESH_SET) \ - SW_API_DESC(SW_API_DYNAMIC_THRESH_GET) \ - SW_API_DESC(SW_API_GOURP_BUFFER_SET) \ - SW_API_DESC(SW_API_GOURP_BUFFER_GET) \ - SW_API_DESC(SW_API_QUEUE_CNT_CTRL_GET) \ - SW_API_DESC(SW_API_QUEUE_CNT_CTRL_SET) \ - SW_API_DESC(SW_API_QUEUE_CNT_GET) \ - SW_API_DESC(SW_API_QUEUE_CNT_CLEANUP) \ - SW_API_DESC(SW_API_QM_ENQUEUE_CTRL_SET) \ - SW_API_DESC(SW_API_QM_ENQUEUE_CTRL_GET) \ - SW_API_DESC(SW_API_QM_SOURCE_PROFILE_SET) \ - SW_API_DESC(SW_API_QM_SOURCE_PROFILE_GET) -#else -#define QM_API \ - SW_API_DEF(SW_API_UCAST_QUEUE_BASE_PROFILE_SET, fal_ucast_queue_base_profile_set), \ - SW_API_DEF(SW_API_QUEUE_FLUSH, fal_queue_flush), \ - SW_API_DEF(SW_API_AC_CTRL_SET, fal_ac_ctrl_set), \ - SW_API_DEF(SW_API_AC_PRE_BUFFER_SET, fal_ac_prealloc_buffer_set), \ - SW_API_DEF(SW_API_QUEUE_GROUP_SET, fal_ac_queue_group_set), \ - SW_API_DEF(SW_API_STATIC_THRESH_SET, fal_ac_static_threshold_set), \ - SW_API_DEF(SW_API_DYNAMIC_THRESH_SET, fal_ac_dynamic_threshold_set), \ - SW_API_DEF(SW_API_GOURP_BUFFER_SET, fal_ac_group_buffer_set), \ - SW_API_DEF(SW_API_QM_ENQUEUE_CTRL_SET, fal_qm_enqueue_ctrl_set), - -#define QM_API_PARAM \ - SW_API_DESC(SW_API_UCAST_QUEUE_BASE_PROFILE_SET) \ - SW_API_DESC(SW_API_QUEUE_FLUSH) \ - SW_API_DESC(SW_API_AC_CTRL_SET) \ - SW_API_DESC(SW_API_AC_PRE_BUFFER_SET) \ - SW_API_DESC(SW_API_QUEUE_GROUP_SET) \ - SW_API_DESC(SW_API_STATIC_THRESH_SET) \ - SW_API_DESC(SW_API_DYNAMIC_THRESH_SET) \ - SW_API_DESC(SW_API_GOURP_BUFFER_SET) \ - SW_API_DESC(SW_API_QM_ENQUEUE_CTRL_SET) -#endif -#else -#define QM_API -#define QM_API_PARAM -#endif - - -#ifdef IN_PPPOE -#define PPPOE_API \ - SW_API_DEF(SW_API_PPPOE_CMD_SET, fal_pppoe_cmd_set), \ - SW_API_DEF(SW_API_PPPOE_CMD_GET, fal_pppoe_cmd_get), \ - SW_API_DEF(SW_API_PPPOE_STATUS_SET, fal_pppoe_status_set), \ - SW_API_DEF(SW_API_PPPOE_STATUS_GET, fal_pppoe_status_get), \ - SW_API_DEF(SW_API_PPPOE_SESSION_ADD, fal_pppoe_session_add), \ - SW_API_DEF(SW_API_PPPOE_SESSION_DEL, fal_pppoe_session_del), \ - SW_API_DEF(SW_API_PPPOE_SESSION_GET, fal_pppoe_session_get), \ - SW_API_DEF(SW_API_PPPOE_SESSION_TABLE_ADD, fal_pppoe_session_table_add), \ - SW_API_DEF(SW_API_PPPOE_SESSION_TABLE_DEL, fal_pppoe_session_table_del), \ - SW_API_DEF(SW_API_PPPOE_SESSION_TABLE_GET, fal_pppoe_session_table_get), \ - SW_API_DEF(SW_API_PPPOE_SESSION_ID_SET, fal_pppoe_session_id_set), \ - SW_API_DEF(SW_API_PPPOE_SESSION_ID_GET, fal_pppoe_session_id_get), \ - SW_API_DEF(SW_API_RTD_PPPOE_EN_SET, fal_rtd_pppoe_en_set), \ - SW_API_DEF(SW_API_RTD_PPPOE_EN_GET, fal_rtd_pppoe_en_get), \ - SW_API_DEF(SW_API_PPPOE_EN_SET, fal_pppoe_l3intf_enable), \ - SW_API_DEF(SW_API_PPPOE_EN_GET, fal_pppoe_l3intf_status_get), - -#define PPPOE_API_PARAM \ - SW_API_DESC(SW_API_PPPOE_CMD_SET) \ - SW_API_DESC(SW_API_PPPOE_CMD_GET) \ - SW_API_DESC(SW_API_PPPOE_STATUS_SET) \ - SW_API_DESC(SW_API_PPPOE_STATUS_GET) \ - SW_API_DESC(SW_API_PPPOE_SESSION_ADD) \ - SW_API_DESC(SW_API_PPPOE_SESSION_DEL) \ - SW_API_DESC(SW_API_PPPOE_SESSION_GET) \ - SW_API_DESC(SW_API_PPPOE_SESSION_TABLE_ADD) \ - SW_API_DESC(SW_API_PPPOE_SESSION_TABLE_DEL) \ - SW_API_DESC(SW_API_PPPOE_SESSION_TABLE_GET) \ - SW_API_DESC(SW_API_PPPOE_SESSION_ID_SET) \ - SW_API_DESC(SW_API_PPPOE_SESSION_ID_GET) \ - SW_API_DESC(SW_API_RTD_PPPOE_EN_SET) \ - SW_API_DESC(SW_API_RTD_PPPOE_EN_GET) \ - SW_API_DESC(SW_API_PPPOE_EN_SET) \ - SW_API_DESC(SW_API_PPPOE_EN_GET) - -#else -#define PPPOE_API -#define PPPOE_API_PARAM -#endif - -#ifdef IN_BM -#ifndef IN_BM_MINI -#define BM_API \ - SW_API_DEF(SW_API_BM_CTRL_SET, fal_port_bm_ctrl_set), \ - SW_API_DEF(SW_API_BM_CTRL_GET, fal_port_bm_ctrl_get), \ - SW_API_DEF(SW_API_BM_PORTGROUP_MAP_SET, fal_port_bufgroup_map_set), \ - SW_API_DEF(SW_API_BM_PORTGROUP_MAP_GET, fal_port_bufgroup_map_get), \ - SW_API_DEF(SW_API_BM_GROUP_BUFFER_SET, fal_bm_bufgroup_buffer_set), \ - SW_API_DEF(SW_API_BM_GROUP_BUFFER_GET, fal_bm_bufgroup_buffer_get), \ - SW_API_DEF(SW_API_BM_PORT_RSVBUFFER_SET, fal_bm_port_reserved_buffer_set), \ - SW_API_DEF(SW_API_BM_PORT_RSVBUFFER_GET, fal_bm_port_reserved_buffer_get), \ - SW_API_DEF(SW_API_BM_STATIC_THRESH_SET, fal_bm_port_static_thresh_set), \ - SW_API_DEF(SW_API_BM_STATIC_THRESH_GET, fal_bm_port_static_thresh_get), \ - SW_API_DEF(SW_API_BM_DYNAMIC_THRESH_SET, fal_bm_port_dynamic_thresh_set), \ - SW_API_DEF(SW_API_BM_DYNAMIC_THRESH_GET, fal_bm_port_dynamic_thresh_get), \ - SW_API_DEF(SW_API_BM_PORT_COUNTER_GET, fal_bm_port_counter_get), - -#define BM_API_PARAM \ - SW_API_DESC(SW_API_BM_CTRL_SET) \ - SW_API_DESC(SW_API_BM_CTRL_GET) \ - SW_API_DESC(SW_API_BM_PORTGROUP_MAP_SET) \ - SW_API_DESC(SW_API_BM_PORTGROUP_MAP_GET) \ - SW_API_DESC(SW_API_BM_GROUP_BUFFER_SET) \ - SW_API_DESC(SW_API_BM_GROUP_BUFFER_GET) \ - SW_API_DESC(SW_API_BM_PORT_RSVBUFFER_SET) \ - SW_API_DESC(SW_API_BM_PORT_RSVBUFFER_GET) \ - SW_API_DESC(SW_API_BM_STATIC_THRESH_SET) \ - SW_API_DESC(SW_API_BM_STATIC_THRESH_GET) \ - SW_API_DESC(SW_API_BM_DYNAMIC_THRESH_SET) \ - SW_API_DESC(SW_API_BM_DYNAMIC_THRESH_GET) \ - SW_API_DESC(SW_API_BM_PORT_COUNTER_GET) -#else -#define BM_API \ - SW_API_DEF(SW_API_BM_CTRL_SET, fal_port_bm_ctrl_set), \ - SW_API_DEF(SW_API_BM_PORTGROUP_MAP_SET, fal_port_bufgroup_map_set), \ - SW_API_DEF(SW_API_BM_GROUP_BUFFER_SET, fal_bm_bufgroup_buffer_set), \ - SW_API_DEF(SW_API_BM_PORT_RSVBUFFER_SET, fal_bm_port_reserved_buffer_set), \ - SW_API_DEF(SW_API_BM_DYNAMIC_THRESH_SET, fal_bm_port_dynamic_thresh_set), - -#define BM_API_PARAM \ - SW_API_DESC(SW_API_BM_CTRL_SET) \ - SW_API_DESC(SW_API_BM_PORTGROUP_MAP_SET) \ - SW_API_DESC(SW_API_BM_GROUP_BUFFER_SET) \ - SW_API_DESC(SW_API_BM_PORT_RSVBUFFER_SET) \ - SW_API_DESC(SW_API_BM_DYNAMIC_THRESH_SET) -#endif -#else -#define BM_API -#define BM_API_PARAM -#endif - -/*qca808x_start*/ -#define REG_API \ - SW_API_DEF(SW_API_PHY_GET, fal_phy_get), \ - SW_API_DEF(SW_API_PHY_SET, fal_phy_set), \ -/*qca808x_end*/\ - SW_API_DEF(SW_API_REG_GET, fal_reg_get), \ - SW_API_DEF(SW_API_REG_SET, fal_reg_set), \ - SW_API_DEF(SW_API_PSGMII_REG_GET, fal_psgmii_reg_get), \ - SW_API_DEF(SW_API_PSGMII_REG_SET, fal_psgmii_reg_set), \ - SW_API_DEF(SW_API_REG_FIELD_GET, fal_reg_field_get), \ - SW_API_DEF(SW_API_REG_FIELD_SET, fal_reg_field_set), \ - SW_API_DEF(SW_API_REG_DUMP, fal_reg_dump), \ - SW_API_DEF(SW_API_DBG_REG_DUMP, fal_debug_reg_dump), \ - SW_API_DEF(SW_API_DBG_PSGMII_SELF_TEST, fal_debug_psgmii_self_test), \ - SW_API_DEF(SW_API_PHY_DUMP, fal_phy_dump), \ - SW_API_DEF(SW_API_UNIPHY_REG_GET, fal_uniphy_reg_get), \ - SW_API_DEF(SW_API_UNIPHY_REG_SET, fal_uniphy_reg_set), -/*qca808x_start*/\ -/*end of REG_API*/ -#define REG_API_PARAM \ - SW_API_DESC(SW_API_PHY_GET) \ - SW_API_DESC(SW_API_PHY_SET) \ -/*qca808x_end*/\ - SW_API_DESC(SW_API_REG_GET) \ - SW_API_DESC(SW_API_REG_SET) \ - SW_API_DESC(SW_API_PSGMII_REG_GET) \ - SW_API_DESC(SW_API_PSGMII_REG_SET) \ - SW_API_DESC(SW_API_REG_FIELD_GET) \ - SW_API_DESC(SW_API_REG_FIELD_SET) \ - SW_API_DESC(SW_API_REG_DUMP) \ - SW_API_DESC(SW_API_DBG_REG_DUMP) \ - SW_API_DESC(SW_API_DBG_PSGMII_SELF_TEST) \ - SW_API_DESC(SW_API_PHY_DUMP) \ - SW_API_DESC(SW_API_UNIPHY_REG_GET) \ - SW_API_DESC(SW_API_UNIPHY_REG_SET) -/*qca808x_start*/\ -/*end of REG_API_PARAM*/ -/*qca808x_end*/ -#ifdef IN_CTRLPKT -#define CTRLPKT_API \ - SW_API_DEF(SW_API_MGMTCTRL_ETHTYPE_PROFILE_SET, fal_mgmtctrl_ethtype_profile_set), \ - SW_API_DEF(SW_API_MGMTCTRL_ETHTYPE_PROFILE_GET, fal_mgmtctrl_ethtype_profile_get), \ - SW_API_DEF(SW_API_MGMTCTRL_RFDB_PROFILE_SET, fal_mgmtctrl_rfdb_profile_set), \ - SW_API_DEF(SW_API_MGMTCTRL_RFDB_PROFILE_GET, fal_mgmtctrl_rfdb_profile_get), \ - SW_API_DEF(SW_API_MGMTCTRL_CTRLPKT_PROFILE_ADD, fal_mgmtctrl_ctrlpkt_profile_add), \ - SW_API_DEF(SW_API_MGMTCTRL_CTRLPKT_PROFILE_DEL, fal_mgmtctrl_ctrlpkt_profile_del), \ - SW_API_DEF(SW_API_MGMTCTRL_CTRLPKT_PROFILE_GETFIRST, fal_mgmtctrl_ctrlpkt_profile_getfirst), \ - SW_API_DEF(SW_API_MGMTCTRL_CTRLPKT_PROFILE_GETNEXT, fal_mgmtctrl_ctrlpkt_profile_getnext), - -#define CTRLPKT_API_PARAM \ - SW_API_DESC(SW_API_MGMTCTRL_ETHTYPE_PROFILE_SET) \ - SW_API_DESC(SW_API_MGMTCTRL_ETHTYPE_PROFILE_GET) \ - SW_API_DESC(SW_API_MGMTCTRL_RFDB_PROFILE_SET) \ - SW_API_DESC(SW_API_MGMTCTRL_RFDB_PROFILE_GET) \ - SW_API_DESC(SW_API_MGMTCTRL_CTRLPKT_PROFILE_ADD) \ - SW_API_DESC(SW_API_MGMTCTRL_CTRLPKT_PROFILE_DEL) \ - SW_API_DESC(SW_API_MGMTCTRL_CTRLPKT_PROFILE_GETFIRST) \ - SW_API_DESC(SW_API_MGMTCTRL_CTRLPKT_PROFILE_GETNEXT) -#else -#define CTRLPKT_API -#define CTRLPKT_API_PARAM -#endif - -#ifdef IN_SERVCODE -#define SERVCODE_API \ - SW_API_DEF(SW_API_SERVCODE_CONFIG_SET, fal_servcode_config_set), \ - SW_API_DEF(SW_API_SERVCODE_CONFIG_GET, fal_servcode_config_get), \ - SW_API_DEF(SW_API_SERVCODE_LOOPCHECK_EN, fal_servcode_loopcheck_en), \ - SW_API_DEF(SW_API_SERVCODE_LOOPCHECK_STATUS_GET, fal_servcode_loopcheck_status_get), - -#define SERVCODE_API_PARAM \ - SW_API_DESC(SW_API_SERVCODE_CONFIG_SET) \ - SW_API_DESC(SW_API_SERVCODE_CONFIG_GET) \ - SW_API_DESC(SW_API_SERVCODE_LOOPCHECK_EN) \ - SW_API_DESC(SW_API_SERVCODE_LOOPCHECK_STATUS_GET) -#else -#define SERVCODE_API -#define SERVCODE_API_PARAM -#endif - -#ifdef IN_RSS_HASH -#define RSS_HASH_API \ - SW_API_DEF(SW_API_RSS_HASH_CONFIG_SET, fal_rss_hash_config_set), \ - SW_API_DEF(SW_API_RSS_HASH_CONFIG_GET, fal_rss_hash_config_get), - -#define RSS_HASH_API_PARAM \ - SW_API_DESC(SW_API_RSS_HASH_CONFIG_SET) \ - SW_API_DESC(SW_API_RSS_HASH_CONFIG_GET) -#else -#define RSS_HASH_API -#define RSS_HASH_API_PARAM -#endif - -#ifdef IN_SHAPER -#ifndef IN_SHAPER_MINI -#define SHAPER_API \ - SW_API_DEF(SW_API_PORT_SHAPER_TIMESLOT_SET, fal_port_shaper_timeslot_set), \ - SW_API_DEF(SW_API_PORT_SHAPER_TIMESLOT_GET, fal_port_shaper_timeslot_get), \ - SW_API_DEF(SW_API_FLOW_SHAPER_TIMESLOT_SET, fal_flow_shaper_timeslot_set), \ - SW_API_DEF(SW_API_FLOW_SHAPER_TIMESLOT_GET, fal_flow_shaper_timeslot_get), \ - SW_API_DEF(SW_API_QUEUE_SHAPER_TIMESLOT_SET, fal_queue_shaper_timeslot_set), \ - SW_API_DEF(SW_API_QUEUE_SHAPER_TIMESLOT_GET, fal_queue_shaper_timeslot_get), \ - SW_API_DEF(SW_API_PORT_SHAPER_TOKEN_NUMBER_SET, fal_port_shaper_token_number_set), \ - SW_API_DEF(SW_API_PORT_SHAPER_TOKEN_NUMBER_GET, fal_port_shaper_token_number_get), \ - SW_API_DEF(SW_API_FLOW_SHAPER_TOKEN_NUMBER_SET, fal_flow_shaper_token_number_set), \ - SW_API_DEF(SW_API_FLOW_SHAPER_TOKEN_NUMBER_GET, fal_flow_shaper_token_number_get), \ - SW_API_DEF(SW_API_QUEUE_SHAPER_TOKEN_NUMBER_SET, fal_queue_shaper_token_number_set), \ - SW_API_DEF(SW_API_QUEUE_SHAPER_TOKEN_NUMBER_GET, fal_queue_shaper_token_number_get), \ - SW_API_DEF(SW_API_PORT_SHAPER_SET, fal_port_shaper_set), \ - SW_API_DEF(SW_API_PORT_SHAPER_GET,fal_port_shaper_get), \ - SW_API_DEF(SW_API_FLOW_SHAPER_SET, fal_flow_shaper_set), \ - SW_API_DEF(SW_API_FLOW_SHAPER_GET,fal_flow_shaper_get), \ - SW_API_DEF(SW_API_QUEUE_SHAPER_SET, fal_queue_shaper_set), \ - SW_API_DEF(SW_API_QUEUE_SHAPER_GET,fal_queue_shaper_get), \ - SW_API_DEF(SW_API_SHAPER_IPG_PRE_SET, fal_shaper_ipg_preamble_length_set), \ - SW_API_DEF(SW_API_SHAPER_IPG_PRE_GET,fal_shaper_ipg_preamble_length_get), - - -#define SHAPER_API_PARAM \ - SW_API_DESC(SW_API_PORT_SHAPER_TIMESLOT_SET) \ - SW_API_DESC(SW_API_PORT_SHAPER_TIMESLOT_GET) \ - SW_API_DESC(SW_API_FLOW_SHAPER_TIMESLOT_SET) \ - SW_API_DESC(SW_API_FLOW_SHAPER_TIMESLOT_GET) \ - SW_API_DESC(SW_API_QUEUE_SHAPER_TIMESLOT_SET) \ - SW_API_DESC(SW_API_QUEUE_SHAPER_TIMESLOT_GET) \ - SW_API_DESC(SW_API_PORT_SHAPER_TOKEN_NUMBER_SET) \ - SW_API_DESC(SW_API_PORT_SHAPER_TOKEN_NUMBER_GET) \ - SW_API_DESC(SW_API_FLOW_SHAPER_TOKEN_NUMBER_SET) \ - SW_API_DESC(SW_API_FLOW_SHAPER_TOKEN_NUMBER_GET) \ - SW_API_DESC(SW_API_QUEUE_SHAPER_TOKEN_NUMBER_SET) \ - SW_API_DESC(SW_API_QUEUE_SHAPER_TOKEN_NUMBER_GET) \ - SW_API_DESC(SW_API_PORT_SHAPER_SET) \ - SW_API_DESC(SW_API_PORT_SHAPER_GET) \ - SW_API_DESC(SW_API_FLOW_SHAPER_SET) \ - SW_API_DESC(SW_API_FLOW_SHAPER_GET) \ - SW_API_DESC(SW_API_QUEUE_SHAPER_SET) \ - SW_API_DESC(SW_API_QUEUE_SHAPER_GET) \ - SW_API_DESC(SW_API_SHAPER_IPG_PRE_SET) \ - SW_API_DESC(SW_API_SHAPER_IPG_PRE_GET) -#else -#define SHAPER_API \ - SW_API_DEF(SW_API_PORT_SHAPER_TIMESLOT_SET, fal_port_shaper_timeslot_set), \ - SW_API_DEF(SW_API_FLOW_SHAPER_TIMESLOT_SET, fal_flow_shaper_timeslot_set), \ - SW_API_DEF(SW_API_QUEUE_SHAPER_TIMESLOT_SET, fal_queue_shaper_timeslot_set), \ - SW_API_DEF(SW_API_PORT_SHAPER_TOKEN_NUMBER_SET, fal_port_shaper_token_number_set), \ - SW_API_DEF(SW_API_FLOW_SHAPER_TOKEN_NUMBER_SET, fal_flow_shaper_token_number_set), \ - SW_API_DEF(SW_API_QUEUE_SHAPER_TOKEN_NUMBER_SET, fal_queue_shaper_token_number_set), \ - SW_API_DEF(SW_API_PORT_SHAPER_SET, fal_port_shaper_set), \ - SW_API_DEF(SW_API_FLOW_SHAPER_SET, fal_flow_shaper_set), \ - SW_API_DEF(SW_API_QUEUE_SHAPER_SET, fal_queue_shaper_set), \ - SW_API_DEF(SW_API_QUEUE_SHAPER_GET,fal_queue_shaper_get), \ - SW_API_DEF(SW_API_SHAPER_IPG_PRE_SET, fal_shaper_ipg_preamble_length_set), - - -#define SHAPER_API_PARAM \ - SW_API_DESC(SW_API_PORT_SHAPER_TIMESLOT_SET) \ - SW_API_DESC(SW_API_FLOW_SHAPER_TIMESLOT_SET) \ - SW_API_DESC(SW_API_QUEUE_SHAPER_TIMESLOT_SET) \ - SW_API_DESC(SW_API_PORT_SHAPER_TOKEN_NUMBER_SET) \ - SW_API_DESC(SW_API_FLOW_SHAPER_TOKEN_NUMBER_SET) \ - SW_API_DESC(SW_API_QUEUE_SHAPER_TOKEN_NUMBER_SET) \ - SW_API_DESC(SW_API_PORT_SHAPER_SET) \ - SW_API_DESC(SW_API_FLOW_SHAPER_SET) \ - SW_API_DESC(SW_API_QUEUE_SHAPER_SET) \ - SW_API_DESC(SW_API_QUEUE_SHAPER_GET) \ - SW_API_DESC(SW_API_SHAPER_IPG_PRE_SET) -#endif -#else -#define SHAPER_API -#define SHAPER_API_PARAM -#endif - -#ifdef IN_POLICER -#ifndef IN_POLICER_MINI -#define POLICER_API \ - SW_API_DEF(SW_API_POLICER_TIMESLOT_SET, fal_policer_timeslot_set), \ - SW_API_DEF(SW_API_POLICER_TIMESLOT_GET, fal_policer_timeslot_get), \ - SW_API_DEF(SW_API_POLICER_PORT_COUNTER_GET, fal_port_policer_counter_get), \ - SW_API_DEF(SW_API_POLICER_ACL_COUNTER_GET, fal_acl_policer_counter_get), \ - SW_API_DEF(SW_API_POLICER_COMPENSATION_SET, fal_port_policer_compensation_byte_set), \ - SW_API_DEF(SW_API_POLICER_COMPENSATION_GET, fal_port_policer_compensation_byte_get), \ - SW_API_DEF(SW_API_POLICER_PORT_ENTRY_SET, fal_port_policer_entry_set), \ - SW_API_DEF(SW_API_POLICER_PORT_ENTRY_GET, fal_port_policer_entry_get), \ - SW_API_DEF(SW_API_POLICER_ACL_ENTRY_SET, fal_acl_policer_entry_set), \ - SW_API_DEF(SW_API_POLICER_ACL_ENTRY_GET,fal_acl_policer_entry_get), \ - SW_API_DEF(SW_API_POLICER_GLOBAL_COUNTER_GET, fal_policer_global_counter_get), \ - SW_API_DEF(SW_API_POLICER_BYPASS_EN_SET, fal_policer_bypass_en_set), \ - SW_API_DEF(SW_API_POLICER_BYPASS_EN_GET, fal_policer_bypass_en_get), - -#define POLICER_API_PARAM \ - SW_API_DESC(SW_API_POLICER_TIMESLOT_SET) \ - SW_API_DESC(SW_API_POLICER_TIMESLOT_GET) \ - SW_API_DESC(SW_API_POLICER_PORT_COUNTER_GET) \ - SW_API_DESC(SW_API_POLICER_ACL_COUNTER_GET) \ - SW_API_DESC(SW_API_POLICER_COMPENSATION_SET) \ - SW_API_DESC(SW_API_POLICER_COMPENSATION_GET) \ - SW_API_DESC(SW_API_POLICER_PORT_ENTRY_SET) \ - SW_API_DESC(SW_API_POLICER_PORT_ENTRY_GET) \ - SW_API_DESC(SW_API_POLICER_ACL_ENTRY_SET) \ - SW_API_DESC(SW_API_POLICER_ACL_ENTRY_GET) \ - SW_API_DESC(SW_API_POLICER_GLOBAL_COUNTER_GET) \ - SW_API_DESC(SW_API_POLICER_BYPASS_EN_SET) \ - SW_API_DESC(SW_API_POLICER_BYPASS_EN_GET) -#else -#define POLICER_API \ - SW_API_DEF(SW_API_POLICER_TIMESLOT_SET, fal_policer_timeslot_set), \ - SW_API_DEF(SW_API_POLICER_COMPENSATION_SET, fal_port_policer_compensation_byte_set), - - -#define POLICER_API_PARAM \ - SW_API_DESC(SW_API_POLICER_TIMESLOT_SET) \ - SW_API_DESC(SW_API_POLICER_COMPENSATION_SET) -#endif -#else -#define POLICER_API -#define POLICER_API_PARAM -#endif - -#ifdef IN_PTP -#define PTP_API \ - SW_API_DEF(SW_API_PTP_CONFIG_SET, fal_ptp_config_set), \ - SW_API_DEF(SW_API_PTP_CONFIG_GET, fal_ptp_config_get), \ - SW_API_DEF(SW_API_PTP_REFERENCE_CLOCK_SET, fal_ptp_reference_clock_set), \ - SW_API_DEF(SW_API_PTP_REFERENCE_CLOCK_GET, fal_ptp_reference_clock_get), \ - SW_API_DEF(SW_API_PTP_RX_TIMESTAMP_MODE_SET, fal_ptp_rx_timestamp_mode_set), \ - SW_API_DEF(SW_API_PTP_RX_TIMESTAMP_MODE_GET, fal_ptp_rx_timestamp_mode_get), \ - SW_API_DEF(SW_API_PTP_TIMESTAMP_GET, fal_ptp_timestamp_get), \ - SW_API_DEF(SW_API_PTP_PKT_TIMESTAMP_SET, fal_ptp_pkt_timestamp_set), \ - SW_API_DEF(SW_API_PTP_PKT_TIMESTAMP_GET, fal_ptp_pkt_timestamp_get), \ - SW_API_DEF(SW_API_PTP_GRANDMASTER_MODE_SET, fal_ptp_grandmaster_mode_set), \ - SW_API_DEF(SW_API_PTP_GRANDMASTER_MODE_GET, fal_ptp_grandmaster_mode_get), \ - SW_API_DEF(SW_API_PTP_RTC_TIME_SET, fal_ptp_rtc_time_set), \ - SW_API_DEF(SW_API_PTP_RTC_TIME_GET, fal_ptp_rtc_time_get), \ - SW_API_DEF(SW_API_PTP_RTC_TIME_CLEAR, fal_ptp_rtc_time_clear), \ - SW_API_DEF(SW_API_PTP_RTC_ADJTIME_SET, fal_ptp_rtc_adjtime_set), \ - SW_API_DEF(SW_API_PTP_RTC_ADJFREQ_SET, fal_ptp_rtc_adjfreq_set), \ - SW_API_DEF(SW_API_PTP_RTC_ADJFREQ_GET, fal_ptp_rtc_adjfreq_get), \ - SW_API_DEF(SW_API_PTP_LINK_DELAY_SET, fal_ptp_link_delay_set), \ - SW_API_DEF(SW_API_PTP_LINK_DELAY_GET, fal_ptp_link_delay_get), \ - SW_API_DEF(SW_API_PTP_SECURITY_SET, fal_ptp_security_set), \ - SW_API_DEF(SW_API_PTP_SECURITY_GET, fal_ptp_security_get), \ - SW_API_DEF(SW_API_PTP_PPS_SIGNAL_CONTROL_SET, fal_ptp_pps_signal_control_set), \ - SW_API_DEF(SW_API_PTP_PPS_SIGNAL_CONTROL_GET, fal_ptp_pps_signal_control_get), \ - SW_API_DEF(SW_API_PTP_RX_CRC_RECALC_SET, fal_ptp_rx_crc_recalc_enable), \ - SW_API_DEF(SW_API_PTP_RX_CRC_RECALC_GET, fal_ptp_rx_crc_recalc_status_get), \ - SW_API_DEF(SW_API_PTP_ASYM_CORRECTION_SET, fal_ptp_asym_correction_set), \ - SW_API_DEF(SW_API_PTP_ASYM_CORRECTION_GET, fal_ptp_asym_correction_get), \ - SW_API_DEF(SW_API_PTP_OUTPUT_WAVEFORM_SET, fal_ptp_output_waveform_set), \ - SW_API_DEF(SW_API_PTP_OUTPUT_WAVEFORM_GET, fal_ptp_output_waveform_get), \ - SW_API_DEF(SW_API_PTP_RTC_TIME_SNAPSHOT_SET, fal_ptp_rtc_time_snapshot_enable), \ - SW_API_DEF(SW_API_PTP_RTC_TIME_SNAPSHOT_GET, fal_ptp_rtc_time_snapshot_status_get), \ - SW_API_DEF(SW_API_PTP_INCREMENT_SYNC_FROM_CLOCK_SET, \ - fal_ptp_increment_sync_from_clock_enable), \ - SW_API_DEF(SW_API_PTP_INCREMENT_SYNC_FROM_CLOCK_GET, \ - fal_ptp_increment_sync_from_clock_status_get), \ - SW_API_DEF(SW_API_PTP_TOD_UART_SET, fal_ptp_tod_uart_set), \ - SW_API_DEF(SW_API_PTP_TOD_UART_GET, fal_ptp_tod_uart_get), \ - SW_API_DEF(SW_API_PTP_ENHANCED_TIMESTAMP_ENGINE_SET, fal_ptp_enhanced_timestamp_engine_set), \ - SW_API_DEF(SW_API_PTP_ENHANCED_TIMESTAMP_ENGINE_GET, fal_ptp_enhanced_timestamp_engine_get), \ - SW_API_DEF(SW_API_PTP_TRIGGER_SET, fal_ptp_trigger_set), \ - SW_API_DEF(SW_API_PTP_TRIGGER_GET, fal_ptp_trigger_get), \ - SW_API_DEF(SW_API_PTP_CAPTURE_SET, fal_ptp_capture_set), \ - SW_API_DEF(SW_API_PTP_CAPTURE_GET, fal_ptp_capture_get), \ - SW_API_DEF(SW_API_PTP_INTERRUPT_SET, fal_ptp_interrupt_set), \ - SW_API_DEF(SW_API_PTP_INTERRUPT_GET, fal_ptp_interrupt_get), - -#define PTP_API_PARAM \ - SW_API_DESC(SW_API_PTP_CONFIG_SET) \ - SW_API_DESC(SW_API_PTP_CONFIG_GET) \ - SW_API_DESC(SW_API_PTP_REFERENCE_CLOCK_SET) \ - SW_API_DESC(SW_API_PTP_REFERENCE_CLOCK_GET) \ - SW_API_DESC(SW_API_PTP_RX_TIMESTAMP_MODE_SET) \ - SW_API_DESC(SW_API_PTP_RX_TIMESTAMP_MODE_GET) \ - SW_API_DESC(SW_API_PTP_TIMESTAMP_GET) \ - SW_API_DESC(SW_API_PTP_PKT_TIMESTAMP_SET) \ - SW_API_DESC(SW_API_PTP_PKT_TIMESTAMP_GET) \ - SW_API_DESC(SW_API_PTP_GRANDMASTER_MODE_SET) \ - SW_API_DESC(SW_API_PTP_GRANDMASTER_MODE_GET) \ - SW_API_DESC(SW_API_PTP_RTC_TIME_SET) \ - SW_API_DESC(SW_API_PTP_RTC_TIME_GET) \ - SW_API_DESC(SW_API_PTP_RTC_TIME_CLEAR) \ - SW_API_DESC(SW_API_PTP_RTC_ADJTIME_SET) \ - SW_API_DESC(SW_API_PTP_RTC_ADJFREQ_SET) \ - SW_API_DESC(SW_API_PTP_RTC_ADJFREQ_GET) \ - SW_API_DESC(SW_API_PTP_LINK_DELAY_SET) \ - SW_API_DESC(SW_API_PTP_LINK_DELAY_GET) \ - SW_API_DESC(SW_API_PTP_SECURITY_SET) \ - SW_API_DESC(SW_API_PTP_SECURITY_GET) \ - SW_API_DESC(SW_API_PTP_PPS_SIGNAL_CONTROL_SET) \ - SW_API_DESC(SW_API_PTP_PPS_SIGNAL_CONTROL_GET) \ - SW_API_DESC(SW_API_PTP_RX_CRC_RECALC_SET) \ - SW_API_DESC(SW_API_PTP_RX_CRC_RECALC_GET) \ - SW_API_DESC(SW_API_PTP_ASYM_CORRECTION_SET) \ - SW_API_DESC(SW_API_PTP_ASYM_CORRECTION_GET) \ - SW_API_DESC(SW_API_PTP_OUTPUT_WAVEFORM_SET) \ - SW_API_DESC(SW_API_PTP_OUTPUT_WAVEFORM_GET) \ - SW_API_DESC(SW_API_PTP_RTC_TIME_SNAPSHOT_SET) \ - SW_API_DESC(SW_API_PTP_RTC_TIME_SNAPSHOT_GET) \ - SW_API_DESC(SW_API_PTP_INCREMENT_SYNC_FROM_CLOCK_SET) \ - SW_API_DESC(SW_API_PTP_INCREMENT_SYNC_FROM_CLOCK_GET) \ - SW_API_DESC(SW_API_PTP_TOD_UART_SET) \ - SW_API_DESC(SW_API_PTP_TOD_UART_GET) \ - SW_API_DESC(SW_API_PTP_ENHANCED_TIMESTAMP_ENGINE_SET) \ - SW_API_DESC(SW_API_PTP_ENHANCED_TIMESTAMP_ENGINE_GET) \ - SW_API_DESC(SW_API_PTP_TRIGGER_SET) \ - SW_API_DESC(SW_API_PTP_TRIGGER_GET) \ - SW_API_DESC(SW_API_PTP_CAPTURE_SET) \ - SW_API_DESC(SW_API_PTP_CAPTURE_GET) \ - SW_API_DESC(SW_API_PTP_INTERRUPT_SET) \ - SW_API_DESC(SW_API_PTP_INTERRUPT_GET) -#else -#define PTP_API -#define PTP_API_PARAM -#endif - -#ifdef IN_SFP -#define SFP_API \ - SW_API_DEF(SW_API_SFP_DATA_GET, fal_sfp_eeprom_data_get), \ - SW_API_DEF(SW_API_SFP_DATA_SET, fal_sfp_eeprom_data_set), \ - SW_API_DEF(SW_API_SFP_DEV_TYPE_GET, fal_sfp_device_type_get), \ - SW_API_DEF(SW_API_SFP_TRANSC_CODE_GET, fal_sfp_transceiver_code_get), \ - SW_API_DEF(SW_API_SFP_RATE_ENCODE_GET, fal_sfp_rate_encode_get), \ - SW_API_DEF(SW_API_SFP_LINK_LENGTH_GET, fal_sfp_link_length_get), \ - SW_API_DEF(SW_API_SFP_VENDOR_INFO_GET, fal_sfp_vendor_info_get), \ - SW_API_DEF(SW_API_SFP_LASER_WAVELENGTH_GET, fal_sfp_laser_wavelength_get), \ - SW_API_DEF(SW_API_SFP_OPTION_GET, fal_sfp_option_get), \ - SW_API_DEF(SW_API_SFP_CTRL_RATE_GET, fal_sfp_ctrl_rate_get), \ - SW_API_DEF(SW_API_SFP_ENHANCED_CFG_GET, fal_sfp_enhanced_cfg_get), \ - SW_API_DEF(SW_API_SFP_DIAG_THRESHOLD_GET, fal_sfp_diag_internal_threshold_get), \ - SW_API_DEF(SW_API_SFP_DIAG_CAL_CONST_GET, fal_sfp_diag_extenal_calibration_const_get), \ - SW_API_DEF(SW_API_SFP_DIAG_REALTIME_GET, fal_sfp_diag_realtime_get), \ - SW_API_DEF(SW_API_SFP_DIAG_CTRL_STATUS_GET, fal_sfp_diag_ctrl_status_get), \ - SW_API_DEF(SW_API_SFP_DIAG_ALARM_WARN_FLAG_GET, fal_sfp_diag_alarm_warning_flag_get), \ - SW_API_DEF(SW_API_SFP_CHECKCODE_GET, fal_sfp_checkcode_get), - -#define SFP_API_PARAM \ - SW_API_DESC(SW_API_SFP_DATA_GET) \ - SW_API_DESC(SW_API_SFP_DATA_SET) \ - SW_API_DESC(SW_API_SFP_DEV_TYPE_GET) \ - SW_API_DESC(SW_API_SFP_TRANSC_CODE_GET) \ - SW_API_DESC(SW_API_SFP_RATE_ENCODE_GET) \ - SW_API_DESC(SW_API_SFP_LINK_LENGTH_GET) \ - SW_API_DESC(SW_API_SFP_VENDOR_INFO_GET) \ - SW_API_DESC(SW_API_SFP_LASER_WAVELENGTH_GET) \ - SW_API_DESC(SW_API_SFP_OPTION_GET) \ - SW_API_DESC(SW_API_SFP_CTRL_RATE_GET) \ - SW_API_DESC(SW_API_SFP_ENHANCED_CFG_GET) \ - SW_API_DESC(SW_API_SFP_DIAG_THRESHOLD_GET) \ - SW_API_DESC(SW_API_SFP_DIAG_CAL_CONST_GET) \ - SW_API_DESC(SW_API_SFP_DIAG_REALTIME_GET) \ - SW_API_DESC(SW_API_SFP_DIAG_CTRL_STATUS_GET) \ - SW_API_DESC(SW_API_SFP_DIAG_ALARM_WARN_FLAG_GET) \ - SW_API_DESC(SW_API_SFP_CHECKCODE_GET) -#else -#define SFP_API -#define SFP_API_PARAM -#endif - -/*qca808x_start*/ -#define SSDK_API \ -/*qca808x_end*/\ - SW_API_DEF(SW_API_SWITCH_RESET, fal_reset), \ - SW_API_DEF(SW_API_SSDK_CFG, fal_ssdk_cfg), \ - SW_API_DEF(SW_API_MODULE_FUNC_CTRL_SET, fal_module_func_ctrl_set), \ - SW_API_DEF(SW_API_MODULE_FUNC_CTRL_GET, fal_module_func_ctrl_get), \ -/*qca808x_start*/\ - PORTCONTROL_API \ -/*qca808x_end*/\ - VLAN_API \ - PORTVLAN_API \ - FDB_API \ - ACL_API \ - QOS_API \ - IGMP_API \ - LEAKY_API \ - MIRROR_API \ - RATE_API \ - STP_API \ - MIB_API \ - MISC_API \ - LED_API \ - COSMAP_API \ - SEC_API \ - IP_API \ - NAT_API \ - FLOW_API \ - TRUNK_API \ - INTERFACECTRL_API \ - VSI_API \ - QM_API \ - BM_API \ - PPPOE_API \ -/*qca808x_start*/\ - REG_API \ -/*qca808x_end*/\ - CTRLPKT_API \ - SERVCODE_API \ - RSS_HASH_API \ - POLICER_API \ - SHAPER_API \ - PTP_API \ - SFP_API \ -/*qca808x_start*/\ - SW_API_DEF(SW_API_MAX, NULL), - - -#define SSDK_PARAM \ -/*qca808x_end*/\ - SW_PARAM_DEF(SW_API_SWITCH_RESET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \ - SW_PARAM_DEF(SW_API_SSDK_CFG, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \ - SW_PARAM_DEF(SW_API_SSDK_CFG, SW_SSDK_CFG, sizeof(ssdk_cfg_t), \ - SW_PARAM_PTR|SW_PARAM_OUT, "ssdk configuration"), \ - SW_PARAM_DEF(SW_API_MODULE_FUNC_CTRL_SET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \ - SW_PARAM_DEF(SW_API_MODULE_FUNC_CTRL_SET, SW_MODULE, 4, SW_PARAM_IN, "Module"), \ - SW_PARAM_DEF(SW_API_MODULE_FUNC_CTRL_SET, SW_FUNC_CTRL, sizeof(fal_func_ctrl_t), \ - SW_PARAM_PTR|SW_PARAM_IN, "Function bitmap"), \ - SW_PARAM_DEF(SW_API_MODULE_FUNC_CTRL_GET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \ - SW_PARAM_DEF(SW_API_MODULE_FUNC_CTRL_GET, SW_MODULE, 4, SW_PARAM_IN, "Module"), \ - SW_PARAM_DEF(SW_API_MODULE_FUNC_CTRL_GET, SW_FUNC_CTRL, sizeof(fal_func_ctrl_t), \ - SW_PARAM_PTR|SW_PARAM_OUT, "Function bitmap"), \ - MIB_API_PARAM \ - LEAKY_API_PARAM \ - MISC_API_PARAM \ - IGMP_API_PARAM \ - MIRROR_API_PARAM \ -/*qca808x_start*/\ - PORTCONTROL_API_PARAM \ -/*qca808x_end*/\ - PORTVLAN_API_PARAM \ - VLAN_API_PARAM \ - FDB_API_PARAM \ - QOS_API_PARAM \ - RATE_API_PARAM \ - STP_API_PARAM \ - ACL_API_PARAM \ - LED_API_PARAM \ - COSMAP_API_PARAM \ - SEC_API_PARAM \ - IP_API_PARAM \ - NAT_API_PARAM \ - FLOW_API_PARAM \ - TRUNK_API_PARAM \ - INTERFACECTRL_API_PARAM \ - VSI_API_PARAM \ - QM_API_PARAM \ - BM_API_PARAM \ - PPPOE_API_PARAM \ -/*qca808x_start*/\ - REG_API_PARAM \ -/*qca808x_end*/\ - CTRLPKT_API_PARAM \ - SERVCODE_API_PARAM \ - RSS_HASH_API_PARAM \ - POLICER_API_PARAM \ - SHAPER_API_PARAM \ - PTP_API_PARAM \ - SFP_API_PARAM \ -/*qca808x_start*/\ - SW_PARAM_DEF(SW_API_MAX, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), - - -#ifdef __cplusplus -} -#endif /* __cplusplus */ - -#endif /* _FAL_API_H_ */ -/*qca808x_end*/ diff --git a/feeds/ipq807x/qca-ssdk/src/include/fal/fal_bm.h b/feeds/ipq807x/qca-ssdk/src/include/fal/fal_bm.h deleted file mode 100755 index 0f75c3b5a..000000000 --- a/feeds/ipq807x/qca-ssdk/src/include/fal/fal_bm.h +++ /dev/null @@ -1,144 +0,0 @@ -/* - * Copyright (c) 2016-2018, The Linux Foundation. All rights reserved. - * Permission to use, copy, modify, and/or distribute this software for - * any purpose with or without fee is hereby granted, provided that the - * above copyright notice and this permission notice appear in all copies. - * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES - * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR - * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES - * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN - * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT - * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. - */ - - -/** - * @defgroup fal_qos FAL_QM - * @{ - */ -#ifndef _FAL_BM_H_ -#define _FAL_BM_H_ - -#ifdef __cplusplus -extern "C" { -#endif /* __cplusplus */ - -#include "sw.h" -#include "fal/fal_type.h" - -typedef struct -{ - a_uint16_t max_thresh; /* Static Maximum threshold */ - a_uint16_t resume_off; /*resume offset */ -} fal_bm_static_cfg_t; - -typedef struct -{ - a_uint8_t weight; /* port weight in the shared group */ - a_uint16_t shared_ceiling; /* Maximum shared buffers */ - a_uint16_t resume_off; /*resume offset */ - a_uint16_t resume_min_thresh; /* Minumum thresh for resume */ -} fal_bm_dynamic_cfg_t; - -typedef struct -{ - a_bool_t enable; - a_uint32_t offset; - a_uint32_t depth; -} fal_port_tdm_ctrl_t; - -typedef struct -{ - a_uint64_t drop_byte_counter; /*drop byte due to overload*/ - a_uint32_t drop_packet_counter; /*drop packet due to overload*/ - a_uint64_t fc_drop_byte_counter; /*drop byte due to fc*/ - a_uint32_t fc_drop_packet_counter; /*drop packet due to fc*/ - a_uint32_t used_counter; /*total used buffer counter for the port*/ - a_uint32_t react_counter; /*react used buffer counter for the port*/ -} fal_bm_port_counter_t; - -#define FAL_PORT_TDB_DIR_INGRESS 0 -#define FAL_PORT_TDB_DIR_EGRESS 1 -typedef struct -{ - a_uint8_t valid; /* 0 for invalid and 1 for valid*/ - a_uint8_t direction; /* 0 for ingreee and 1 for egress */ - fal_port_t port; -} fal_port_tdm_tick_cfg_t; - -enum { - FUNC_PORT_BUFGROUP_MAP_GET = 0, - FUNC_BM_PORT_RESERVED_BUFFER_GET, - FUNC_BM_BUFGROUP_BUFFER_GET, - FUNC_BM_PORT_DYNAMIC_THRESH_GET, - FUNC_PORT_BM_CTRL_GET, - FUNC_BM_BUFGROUP_BUFFER_SET, - FUNC_PORT_BUFGROUP_MAP_SET, - FUNC_BM_PORT_STATIC_THRESH_GET, - FUNC_BM_PORT_RESERVED_BUFFER_SET, - FUNC_BM_PORT_STATIC_THRESH_SET, - FUNC_BM_PORT_DYNAMIC_THRESH_SET, - FUNC_PORT_BM_CTRL_SET, - FUNC_PORT_TDM_CTRL_SET, - FUNC_PORT_TDM_TICK_CFG_SET, - FUNC_BM_PORT_COUNTER_GET, -}; - -sw_error_t -fal_port_bm_ctrl_set(a_uint32_t dev_id, fal_port_t port, a_bool_t enable); - -sw_error_t -fal_port_bufgroup_map_set(a_uint32_t dev_id, fal_port_t port, - a_uint8_t group); - -sw_error_t -fal_bm_port_dynamic_thresh_set(a_uint32_t dev_id, fal_port_t port, - fal_bm_dynamic_cfg_t *cfg); - -sw_error_t -fal_bm_bufgroup_buffer_set(a_uint32_t dev_id, a_uint8_t group, - a_uint16_t buff_num); - -sw_error_t -fal_bm_port_reserved_buffer_set(a_uint32_t dev_id, fal_port_t port, - a_uint16_t prealloc_buff, a_uint16_t react_buff); - -#ifndef IN_BM_MINI -sw_error_t -fal_port_bm_ctrl_get(a_uint32_t dev_id, fal_port_t port, a_bool_t *enable); - -sw_error_t -fal_port_bufgroup_map_get(a_uint32_t dev_id, fal_port_t port, - a_uint8_t *group); -sw_error_t -fal_bm_bufgroup_buffer_get(a_uint32_t dev_id, a_uint8_t group, - a_uint16_t *buff_num); -sw_error_t -fal_bm_port_reserved_buffer_get(a_uint32_t dev_id, fal_port_t port, - a_uint16_t *prealloc_buff, a_uint16_t *react_buff); - -sw_error_t -fal_bm_port_static_thresh_set(a_uint32_t dev_id, fal_port_t port, - fal_bm_static_cfg_t *cfg); - -sw_error_t -fal_bm_port_static_thresh_get(a_uint32_t dev_id, fal_port_t port, - fal_bm_static_cfg_t *cfg); -sw_error_t -fal_bm_port_dynamic_thresh_get(a_uint32_t dev_id, fal_port_t port, - fal_bm_dynamic_cfg_t *cfg); - -sw_error_t -fal_bm_port_counter_get(a_uint32_t dev_id, fal_port_t port, - fal_bm_port_counter_t *counter); -#endif - - -#ifdef __cplusplus -} -#endif /* __cplusplus */ -#endif /* _PORT_BM_H_ */ -/** - * @} - */ diff --git a/feeds/ipq807x/qca-ssdk/src/include/fal/fal_cosmap.h b/feeds/ipq807x/qca-ssdk/src/include/fal/fal_cosmap.h deleted file mode 100755 index 707ce29ad..000000000 --- a/feeds/ipq807x/qca-ssdk/src/include/fal/fal_cosmap.h +++ /dev/null @@ -1,140 +0,0 @@ -/* - * Copyright (c) 2012,2018, The Linux Foundation. All rights reserved. - * Permission to use, copy, modify, and/or distribute this software for - * any purpose with or without fee is hereby granted, provided that the - * above copyright notice and this permission notice appear in all copies. - * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES - * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR - * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES - * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN - * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT - * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. - */ - - -/** - * @defgroup fal_cosmap FAL_COSMAP - * @{ - */ -#ifndef _FAL_COSMAP_H_ -#define _FAL_COSMAP_H_ - -#ifdef __cplusplus -extern "C" { -#endif /* __cplusplus */ - -#include "sw.h" -#include "fal/fal_type.h" - - typedef struct - { - a_bool_t remark_dscp; - a_bool_t remark_up; - a_bool_t remark_dei; - a_uint8_t g_dscp; - a_uint8_t y_dscp; - a_uint8_t g_up; - a_uint8_t y_up; - a_uint8_t g_dei; - a_uint8_t y_dei; - } fal_egress_remark_table_t; - -#ifndef IN_COSMAP_MINI - sw_error_t - fal_cosmap_dscp_to_pri_set(a_uint32_t dev_id, a_uint32_t dscp, - a_uint32_t pri); - - sw_error_t - fal_cosmap_dscp_to_pri_get(a_uint32_t dev_id, a_uint32_t dscp, - a_uint32_t * pri); - - sw_error_t - fal_cosmap_dscp_to_dp_set(a_uint32_t dev_id, a_uint32_t dscp, - a_uint32_t dp); - - sw_error_t - fal_cosmap_dscp_to_dp_get(a_uint32_t dev_id, a_uint32_t dscp, - a_uint32_t * dp); - - sw_error_t - fal_cosmap_up_to_pri_set(a_uint32_t dev_id, a_uint32_t up, - a_uint32_t pri); - - sw_error_t - fal_cosmap_up_to_pri_get(a_uint32_t dev_id, a_uint32_t up, - a_uint32_t * pri); - - sw_error_t - fal_cosmap_up_to_dp_set(a_uint32_t dev_id, a_uint32_t up, - a_uint32_t dp); - - sw_error_t - fal_cosmap_up_to_dp_get(a_uint32_t dev_id, a_uint32_t up, - a_uint32_t * dp); - - sw_error_t - fal_cosmap_dscp_to_ehpri_set(a_uint32_t dev_id, a_uint32_t dscp, - a_uint32_t pri); - - sw_error_t - fal_cosmap_dscp_to_ehpri_get(a_uint32_t dev_id, a_uint32_t dscp, - a_uint32_t * pri); - - sw_error_t - fal_cosmap_dscp_to_ehdp_set(a_uint32_t dev_id, a_uint32_t dscp, - a_uint32_t dp); - - sw_error_t - fal_cosmap_dscp_to_ehdp_get(a_uint32_t dev_id, a_uint32_t dscp, - a_uint32_t * dp); - - sw_error_t - fal_cosmap_up_to_ehpri_set(a_uint32_t dev_id, a_uint32_t up, - a_uint32_t pri); - - sw_error_t - fal_cosmap_up_to_ehpri_get(a_uint32_t dev_id, a_uint32_t up, - a_uint32_t * pri); - - sw_error_t - fal_cosmap_up_to_ehdp_set(a_uint32_t dev_id, a_uint32_t up, - a_uint32_t dp); - - sw_error_t - fal_cosmap_up_to_ehdp_get(a_uint32_t dev_id, a_uint32_t up, - a_uint32_t * dp); -#endif - sw_error_t - fal_cosmap_pri_to_queue_set(a_uint32_t dev_id, a_uint32_t pri, - a_uint32_t queue); - - sw_error_t - fal_cosmap_pri_to_ehqueue_set(a_uint32_t dev_id, a_uint32_t pri, - a_uint32_t queue); -#ifndef IN_COSMAP_MINI - sw_error_t - fal_cosmap_pri_to_queue_get(a_uint32_t dev_id, a_uint32_t pri, - a_uint32_t * queue); - - sw_error_t - fal_cosmap_pri_to_ehqueue_get(a_uint32_t dev_id, a_uint32_t pri, - a_uint32_t * queue); - - sw_error_t - fal_cosmap_egress_remark_set(a_uint32_t dev_id, a_uint32_t tbl_id, - fal_egress_remark_table_t * tbl); - - sw_error_t - fal_cosmap_egress_remark_get(a_uint32_t dev_id, a_uint32_t tbl_id, - fal_egress_remark_table_t * tbl); -#endif -#ifdef __cplusplus -} -#endif /* __cplusplus */ -#endif /* _FAL_COSMAP_H_ */ - -/** - * @} - */ - diff --git a/feeds/ipq807x/qca-ssdk/src/include/fal/fal_ctrlpkt.h b/feeds/ipq807x/qca-ssdk/src/include/fal/fal_ctrlpkt.h deleted file mode 100755 index 0903a2e64..000000000 --- a/feeds/ipq807x/qca-ssdk/src/include/fal/fal_ctrlpkt.h +++ /dev/null @@ -1,100 +0,0 @@ -/* - * Copyright (c) 2016-2018, The Linux Foundation. All rights reserved. - * Permission to use, copy, modify, and/or distribute this software for - * any purpose with or without fee is hereby granted, provided that the - * above copyright notice and this permission notice appear in all copies. - * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES - * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR - * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES - * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN - * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT - * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. - */ - - -/** - * @defgroup fal_gen FAL_CTRLPKT - * @{ - */ -#ifndef _FAL_CTRLPKT_H_ -#define _FAL_CTRLPKT_H_ - -#ifdef __cplusplus -extern "C" { -#endif -/* __cplusplus */ - -#include "sw.h" -#include "fal/fal_type.h" - - -#if defined(SW_API_LOCK) && (!defined(HSL_STANDALONG)) -#define FAL_CTRLPKT_API_LOCK -#define FAL_CTRLPKT_API_UNLOCK -#else -#define FAL_CTRLPKT_API_LOCK -#define FAL_CTRLPKT_API_UNLOCK -#endif - - -typedef struct { - fal_fwd_cmd_t action; /* the action when condition matched */ - a_bool_t sg_bypass; /* check if sg_bypass when condition matched */ - a_bool_t l2_filter_bypass; /* check if l2_filter_bypass when condition matched */ - a_bool_t in_stp_bypass; /* check if in_stp_bypass when condition matched */ - a_bool_t in_vlan_fltr_bypass; /* check if in_vlan_fltr_bypass when condition matched */ -} fal_ctrlpkt_action_t; - -typedef struct -{ - a_bool_t mgt_eapol; /* eapol protocol management type */ - a_bool_t mgt_pppoe; /* pppoe protocol management type */ - a_bool_t mgt_igmp; /* igmp protocol management type */ - a_bool_t mgt_arp_req; /* arp request protocol management type */ - a_bool_t mgt_arp_rep; /* arp response protocol management type */ - a_bool_t mgt_dhcp4; /* dhcp4 protocol management type */ - a_bool_t mgt_mld; /* mld protocol management type */ - a_bool_t mgt_ns; /* ns protocol management type */ - a_bool_t mgt_na; /* na protocol management type */ - a_bool_t mgt_dhcp6; /* dhcp6 protocol management type */ -} fal_ctrlpkt_protocol_type_t; - -typedef struct { - fal_ctrlpkt_action_t action; /* the all action when condition matched */ - fal_pbmp_t port_map; /* the condition port bitmap */ - a_uint32_t ethtype_profile_bitmap; /* the condition ethtype_profile bitmap */ - a_uint32_t rfdb_profile_bitmap; /* the condition rfdb_profile bitmap */ - fal_ctrlpkt_protocol_type_t protocol_types; /* the condition protocol types */ -} fal_ctrlpkt_profile_t; - -enum { - FUNC_MGMTCTRL_ETHTYPE_PROFILE_SET = 0, - FUNC_MGMTCTRL_ETHTYPE_PROFILE_GET, - FUNC_MGMTCTRL_RFDB_PROFILE_SET, - FUNC_MGMTCTRL_RFDB_PROFILE_GET, - FUNC_MGMTCTRL_CTRLPKT_PROFILE_ADD, - FUNC_MGMTCTRL_CTRLPKT_PROFILE_DEL, - FUNC_MGMTCTRL_CTRLPKT_PROFILE_GETFIRST, - FUNC_MGMTCTRL_CTRLPKT_PROFILE_GETNEXT, -}; - -sw_error_t fal_mgmtctrl_ethtype_profile_set(a_uint32_t dev_id, a_uint32_t profile_id, a_uint32_t ethtype); -sw_error_t fal_mgmtctrl_ethtype_profile_get(a_uint32_t dev_id, a_uint32_t profile_id, a_uint32_t * ethtype); - -sw_error_t fal_mgmtctrl_rfdb_profile_set(a_uint32_t dev_id, a_uint32_t profile_id, fal_mac_addr_t *addr); -sw_error_t fal_mgmtctrl_rfdb_profile_get(a_uint32_t dev_id, a_uint32_t profile_id, fal_mac_addr_t *addr); - -sw_error_t fal_mgmtctrl_ctrlpkt_profile_add(a_uint32_t dev_id, fal_ctrlpkt_profile_t *ctrlpkt); -sw_error_t fal_mgmtctrl_ctrlpkt_profile_del(a_uint32_t dev_id, fal_ctrlpkt_profile_t *ctrlpkt); -sw_error_t fal_mgmtctrl_ctrlpkt_profile_getfirst(a_uint32_t dev_id, fal_ctrlpkt_profile_t *ctrlpkt); -sw_error_t fal_mgmtctrl_ctrlpkt_profile_getnext(a_uint32_t dev_id, fal_ctrlpkt_profile_t *ctrlpkt); - -#ifdef __cplusplus -} -#endif /* __cplusplus */ -#endif /* _FAL_CTRLPKT_H_ */ -/** - * @} - */ - diff --git a/feeds/ipq807x/qca-ssdk/src/include/fal/fal_fdb.h b/feeds/ipq807x/qca-ssdk/src/include/fal/fal_fdb.h deleted file mode 100755 index 791dba9eb..000000000 --- a/feeds/ipq807x/qca-ssdk/src/include/fal/fal_fdb.h +++ /dev/null @@ -1,338 +0,0 @@ -/* - * Copyright (c) 2012, 2015-2018, The Linux Foundation. All rights reserved. - * Permission to use, copy, modify, and/or distribute this software for - * any purpose with or without fee is hereby granted, provided that the - * above copyright notice and this permission notice appear in all copies. - * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES - * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR - * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES - * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN - * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT - * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. - */ - - -/** - * @defgroup fal_fdb FAL_FDB - * @{ - */ -#ifndef _FAL_FDB_H_ -#define _FAL_FDB_H_ - -#ifdef __cplusplus -extern "C" { -#endif /* __cplusplus */ - -#include "sw.h" -#include "fal/fal_type.h" - - /** - @details Fields description: - - portmap_en - If value of portmap_en is A_TRUE then port.map is valid - otherwise port.id is valid. - - - leaky_en - If value of leaky_en is A_TRUE then packets which - destination address equals addr in this entry would be leaky. - - - mirror_en - If value of mirror_en is A_TRUE then packets which - destination address equals addr in this entry would be mirrored. - - - clone_en - If value of clone_en is A_TRUE which means this address is - a mac clone address. - @brief This structure defines the Fdb entry. - - */ - typedef struct - { - fal_mac_addr_t addr; /* mac address of fdb entry */ - a_uint16_t fid; /* vlan_id/vsi value of fdb entry */ - fal_fwd_cmd_t dacmd; /* source address command */ - fal_fwd_cmd_t sacmd; /* dest address command */ - union - { - fal_port_t id; /* union value is port id value */ - fal_pbmp_t map; /* union value is bitmap value */ - } port; - a_bool_t portmap_en; /* use port bitmap or not */ - a_bool_t is_multicast; /* if it is a multicast mac fdb entry */ - a_bool_t static_en; /* enable static or not */ - a_bool_t leaky_en; /* enable leaky or not */ - a_bool_t mirror_en; /* enable mirror or not */ - a_bool_t clone_en; /* enable clone or not */ - a_bool_t cross_pt_state; /* cross port state */ - a_bool_t da_pri_en; /* enable da pri or not */ - a_uint8_t da_queue; /* da queue value */ - a_bool_t white_list_en; /* enable white list or not */ - a_bool_t load_balance_en; /* enable load balance value or not */ - a_uint8_t load_balance; /* load balance value */ - a_bool_t entry_valid; /* check if entry is value */ - a_bool_t lookup_valid; /* check if entry is lookup */ - } fal_fdb_entry_t; - - typedef struct - { - fal_mac_addr_t addr; - a_uint16_t fid; - a_uint8_t load_balance; - } fal_fdb_rfs_t; - - typedef struct - { - a_bool_t enable; /* enable port learn limit or not */ - a_uint32_t limit_num; /* port learn limit number */ - fal_fwd_cmd_t action; /* the action when port learn number exceed limit*/ - } fal_maclimit_ctrl_t; - -#define FAL_FDB_DEL_STATIC 0x1 - - typedef struct - { - a_bool_t port_en; /* enable port value matching or not */ - a_bool_t fid_en; /* enable fid value matching or not */ - a_bool_t multicast_en; /* enable multicast value matching or not */ - } fal_fdb_op_t; - - typedef enum - { - INVALID_VLAN_SVL=0, - INVALID_VLAN_IVL - } fal_fdb_smode; - -enum { - FUNC_FDB_ENTRY_ADD = 0, - FUNC_FDB_ENTRY_FLUSH, - FUNC_FDB_ENTRY_DEL_BYPORT, - FUNC_FDB_ENTRY_DEL_BYMAC, - FUNC_FDB_ENTRY_GETFIRST, - FUNC_FDB_ENTRY_GETNEXT, - FUNC_FDB_ENTRY_SEARCH, - FUNC_FDB_PORT_LEARN_SET, - FUNC_FDB_PORT_LEARN_GET, - FUNC_FDB_PORT_LEARNING_CTRL_SET, - FUNC_FDB_PORT_LEARNING_CTRL_GET, - FUNC_FDB_PORT_STAMOVE_CTRL_SET, - FUNC_FDB_PORT_STAMOVE_CTRL_GET, - FUNC_FDB_AGING_CTRL_SET, - FUNC_FDB_AGING_CTRL_GET, - FUNC_FDB_LEARNING_CTRL_SET, - FUNC_FDB_LEARNING_CTRL_GET, - FUNC_FDB_AGING_TIME_SET, - FUNC_FDB_AGING_TIME_GET, - FUNC_FDB_ENTRY_GETNEXT_BYINDEX, - FUNC_FDB_ENTRY_EXTEND_GETNEXT, - FUNC_FDB_ENTRY_EXTEND_GETFIRST, - FUNC_FDB_ENTRY_UPDATE_BYPORT, - FUNC_PORT_FDB_LEARN_LIMIT_SET, - FUNC_PORT_FDB_LEARN_LIMIT_GET, - FUNC_PORT_FDB_LEARN_EXCEED_CMD_SET, - FUNC_PORT_FDB_LEARN_EXCEED_CMD_GET, - FUNC_FDB_PORT_LEARNED_MAC_COUNTER_GET, - FUNC_FDB_PORT_ADD, - FUNC_FDB_PORT_DEL, - FUNC_FDB_PORT_MACLIMIT_CTRL_SET, - FUNC_FDB_PORT_MACLIMIT_CTRL_GET, - FUNC_FDB_DEL_BY_FID, -}; - -#ifndef IN_FDB_MINI - sw_error_t - fal_fdb_entry_add(a_uint32_t dev_id, const fal_fdb_entry_t * entry); - - sw_error_t - fal_fdb_rfs_set(a_uint32_t dev_id, const fal_fdb_rfs_t * entry); - - sw_error_t - fal_fdb_rfs_del(a_uint32_t dev_id, const fal_fdb_rfs_t * entry); -#endif - - sw_error_t - fal_fdb_entry_flush(a_uint32_t dev_id, a_uint32_t flag); - - - sw_error_t - fal_fdb_entry_del_byport(a_uint32_t dev_id, a_uint32_t port_id, a_uint32_t flag); - - sw_error_t - fal_fdb_entry_del_bymac(a_uint32_t dev_id, const fal_fdb_entry_t *entry); - - sw_error_t - fal_fdb_entry_getfirst(a_uint32_t dev_id, fal_fdb_entry_t * entry); - - -#ifndef IN_FDB_MINI - sw_error_t - fal_fdb_entry_getnext(a_uint32_t dev_id, fal_fdb_entry_t * entry); -#endif - - sw_error_t - fal_fdb_entry_search(a_uint32_t dev_id, fal_fdb_entry_t * entry); - - -sw_error_t - fal_fdb_port_learn_set(a_uint32_t dev_id, fal_port_t port_id, a_bool_t enable); - - -#ifndef IN_FDB_MINI - sw_error_t - fal_fdb_port_learn_get(a_uint32_t dev_id, fal_port_t port_id, a_bool_t *enable); -#endif - sw_error_t - fal_fdb_port_learning_ctrl_set(a_uint32_t dev_id, fal_port_t port_id, - a_bool_t enable, fal_fwd_cmd_t cmd); -#ifndef IN_FDB_MINI - sw_error_t - fal_fdb_port_learning_ctrl_get(a_uint32_t dev_id, fal_port_t port_id, - a_bool_t *enable, fal_fwd_cmd_t *cmd); -#endif - - sw_error_t - fal_fdb_port_stamove_ctrl_set(a_uint32_t dev_id, fal_port_t port_id, - a_bool_t enable, fal_fwd_cmd_t cmd); - -#ifndef IN_FDB_MINI - sw_error_t - fal_fdb_port_stamove_ctrl_get(a_uint32_t dev_id, fal_port_t port_id, - a_bool_t *enable, fal_fwd_cmd_t *cmd); -#endif - - sw_error_t - fal_fdb_aging_ctrl_set(a_uint32_t dev_id, a_bool_t enable); - -#ifndef IN_FDB_MINI - sw_error_t - fal_fdb_aging_ctrl_get(a_uint32_t dev_id, a_bool_t * enable); -#endif - - sw_error_t - fal_fdb_learning_ctrl_set(a_uint32_t dev_id, a_bool_t enable); - -#ifndef IN_FDB_MINI - sw_error_t - fal_fdb_learning_ctrl_get(a_uint32_t dev_id, a_bool_t * enable); - - sw_error_t - fal_fdb_vlan_ivl_svl_set(a_uint32_t dev_id, fal_fdb_smode smode); - - sw_error_t - fal_fdb_vlan_ivl_svl_get(a_uint32_t dev_id, fal_fdb_smode * smode); - - sw_error_t - fal_fdb_aging_time_set(a_uint32_t dev_id, a_uint32_t * time); - - - sw_error_t - fal_fdb_aging_time_get(a_uint32_t dev_id, a_uint32_t * time); -#endif - sw_error_t - fal_fdb_entry_getnext_byindex(a_uint32_t dev_id, a_uint32_t * iterator, fal_fdb_entry_t * entry); - - sw_error_t - fal_fdb_entry_extend_getnext(a_uint32_t dev_id, fal_fdb_op_t * option, - fal_fdb_entry_t * entry); - - sw_error_t - fal_fdb_entry_extend_getfirst(a_uint32_t dev_id, fal_fdb_op_t * option, - fal_fdb_entry_t * entry); - -#ifndef IN_FDB_MINI - sw_error_t - fal_fdb_entry_update_byport(a_uint32_t dev_id, fal_port_t old_port, fal_port_t new_port, - a_uint32_t fid, fal_fdb_op_t * option); - - sw_error_t - fal_port_fdb_learn_limit_set(a_uint32_t dev_id, fal_port_t port_id, - a_bool_t enable, a_uint32_t cnt); - - sw_error_t - fal_port_fdb_learn_limit_get(a_uint32_t dev_id, fal_port_t port_id, - a_bool_t * enable, a_uint32_t * cnt); - - sw_error_t - fal_port_fdb_learn_exceed_cmd_set(a_uint32_t dev_id, fal_port_t port_id, - fal_fwd_cmd_t cmd); - - - sw_error_t - fal_port_fdb_learn_exceed_cmd_get(a_uint32_t dev_id, fal_port_t port_id, - fal_fwd_cmd_t * cmd); - - sw_error_t - fal_fdb_port_learned_mac_counter_get(a_uint32_t dev_id, fal_port_t port_id, - a_uint32_t * cnt); - - sw_error_t - fal_fdb_learn_limit_set(a_uint32_t dev_id, a_bool_t enable, a_uint32_t cnt); - - sw_error_t - fal_fdb_learn_limit_get(a_uint32_t dev_id, a_bool_t * enable, a_uint32_t * cnt); - - sw_error_t - fal_fdb_learn_exceed_cmd_set(a_uint32_t dev_id, fal_fwd_cmd_t cmd); - - sw_error_t - fal_fdb_learn_exceed_cmd_get(a_uint32_t dev_id, fal_fwd_cmd_t * cmd); - - sw_error_t - fal_fdb_resv_add(a_uint32_t dev_id, fal_fdb_entry_t * entry); - - sw_error_t - fal_fdb_resv_del(a_uint32_t dev_id, fal_fdb_entry_t * entry); - - sw_error_t - fal_fdb_resv_find(a_uint32_t dev_id, fal_fdb_entry_t * entry); - - sw_error_t - fal_fdb_resv_iterate(a_uint32_t dev_id, a_uint32_t * iterator, fal_fdb_entry_t * entry); - - sw_error_t - fal_fdb_port_learn_static_set(a_uint32_t dev_id, fal_port_t port_id, a_bool_t enable); - - - sw_error_t - fal_fdb_port_learn_static_get(a_uint32_t dev_id, fal_port_t port_id, - a_bool_t * enable); - - sw_error_t - fal_fdb_port_add(a_uint32_t dev_id, a_uint32_t fid, fal_mac_addr_t * addr, fal_port_t port_id); - - sw_error_t - fal_fdb_port_del(a_uint32_t dev_id, a_uint32_t fid, fal_mac_addr_t * addr, fal_port_t port_id); - - sw_error_t - fal_fdb_port_maclimit_ctrl_set(a_uint32_t dev_id, fal_port_t port_id, fal_maclimit_ctrl_t * maclimit_ctrl); - - sw_error_t - fal_fdb_port_maclimit_ctrl_get(a_uint32_t dev_id, fal_port_t port_id, fal_maclimit_ctrl_t * maclimit_ctrl); -#endif - - sw_error_t - fal_fdb_entry_del_byfid(a_uint32_t dev_id, a_uint16_t fid, a_uint32_t flag); - -#define fal_fdb_add fal_fdb_entry_add -#define fal_fdb_del_all fal_fdb_entry_flush -#define fal_fdb_del_by_port fal_fdb_entry_del_byport -#define fal_fdb_del_by_mac fal_fdb_entry_del_bymac -#define fal_fdb_first fal_fdb_entry_getfirst -#define fal_fdb_next fal_fdb_entry_getnext -#define fal_fdb_find fal_fdb_entry_search -#define fal_fdb_age_ctrl_set fal_fdb_aging_ctrl_set -#define fal_fdb_age_ctrl_get fal_fdb_aging_ctrl_get -#define fal_fdb_age_time_set fal_fdb_aging_time_set -#define fal_fdb_age_time_get fal_fdb_aging_time_get -#define fal_fdb_iterate fal_fdb_entry_getnext_byindex -#define fal_fdb_extend_next fal_fdb_entry_extend_getnext -#define fal_fdb_extend_first fal_fdb_entry_extend_getfirst -#define fal_fdb_transfer fal_fdb_entry_update_byport - -#ifdef __cplusplus -} -#endif /* __cplusplus */ -#endif /* _FAL_FDB_H_ */ -/** - * @} - */ diff --git a/feeds/ipq807x/qca-ssdk/src/include/fal/fal_flow.h b/feeds/ipq807x/qca-ssdk/src/include/fal/fal_flow.h deleted file mode 100755 index f8598682d..000000000 --- a/feeds/ipq807x/qca-ssdk/src/include/fal/fal_flow.h +++ /dev/null @@ -1,244 +0,0 @@ -/* - * Copyright (c) 2016-2019, The Linux Foundation. All rights reserved. - * Permission to use, copy, modify, and/or distribute this software for - * any purpose with or without fee is hereby granted, provided that the - * above copyright notice and this permission notice appear in all copies. - * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES - * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR - * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES - * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN - * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT - * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. - */ - - -/** - * @defgroup fal_flow - * @{ - */ -#ifndef _FAL_FLOW_H_ -#define _FAL_FLOW_H_ - -#ifdef __cplusplus -extern "C" { -#endif /* __cplusplus */ - -#include "sw.h" -#include "fal/fal_type.h" -#include "fal/fal_ip.h" - -typedef enum { - FAL_FLOW_L3_UNICAST = 0, - FAL_FLOW_L2_UNICAST, - FAL_FLOW_MCAST, -} fal_flow_pkt_type_t; - -typedef enum { - FAL_FLOW_LAN_TO_LAN_DIR = 0, - FAL_FLOW_LAN_TO_WAN_DIR, - FAL_FLOW_WAN_TO_LAN_DIR, - FAL_FLOW_WAN_TO_WAN_DIR, - FAL_FLOW_UNKOWN_DIR_DIR, -} fal_flow_direction_t; - -typedef enum { - FAL_FLOW_FORWARD = 0, - FAL_FLOW_SNAT, - FAL_FLOW_DNAT, - FAL_FLOW_ROUTE, - FAL_FLOW_BRIDGE, -} fal_flow_fwd_type_t; - -/* FLOW entry type field */ -#define FAL_FLOW_IP4_5TUPLE_ADDR 0x1 -#define FAL_FLOW_IP6_5TUPLE_ADDR 0x2 -#define FAL_FLOW_IP4_3TUPLE_ADDR 0x4 -#define FAL_FLOW_IP6_3TUPLE_ADDR 0x8 - -#define FAL_FLOW_OP_MODE_KEY 0x0 -#define FAL_FLOW_OP_MODE_INDEX 0x1 -#define FAL_FLOW_OP_MODE_FLUSH 0x2 - -#define FAL_FLOW_PROTOCOL_OTHER 0 -#define FAL_FLOW_PROTOCOL_TCP 1 -#define FAL_FLOW_PROTOCOL_UDP 2 -#define FAL_FLOW_PROTOCOL_UDPLITE 3 - - -typedef struct { - fal_fwd_cmd_t miss_action; /* flow mismatch action*/ - a_bool_t frag_bypass_en; /*0 for disable and 1 for enable*/ - a_bool_t tcp_spec_bypass_en; /*0 for disable and 1 for enable*/ - a_bool_t all_bypass_en; /*0 for disable and 1 for enable*/ - a_uint8_t key_sel; /*0 for source ip address and 1 for destination ip address*/ -} fal_flow_mgmt_t; - -typedef struct { - a_uint32_t entry_id; /*entry index*/ - a_uint8_t entry_type; /*1:ipv4 5 tuple, 2:ipv6 5 tuple, 4:ipv4 3 tuple, 8:ipv6 3 tuple*/ - a_uint8_t host_addr_type; /*0:souce ip index, 1:destination ip index*/ - a_uint16_t host_addr_index; /*host table entry index*/ - a_uint8_t protocol; /*1:tcp, 2:udp, 3:udp-lite, 0:other*/ - a_uint8_t age; /*aging value*/ - a_bool_t src_intf_valid; /*source interface check valid*/ - a_uint8_t src_intf_index; /*souce l3 interface*/ - a_uint8_t fwd_type; /*forward type*/ - a_uint16_t snat_nexthop; /*nexthop index for snat*/ - a_uint16_t snat_srcport; /*new source l4 port*/ - a_uint16_t dnat_nexthop; /*nexthop index for dnat*/ - a_uint16_t dnat_dstport; /*new destination l4 port*/ - a_uint16_t route_nexthop; /*nexthop index for route*/ - a_bool_t port_valid; /*route port valid*/ - fal_port_t route_port; /*port for route*/ - fal_port_t bridge_port; /*port for l2 bridge*/ - a_bool_t deacclr_en; /*0 for disable and 1 for enable*/ - a_bool_t copy_tocpu_en; /*0 for disable and 1 for enable*/ - a_uint8_t syn_toggle; /*update by host*/ - a_uint8_t pri_profile; /*flow qos index*/ - a_uint8_t sevice_code; /*service code for bypass*/ - a_uint8_t ip_type; /*0 for ipv4 and 1 for ipv6*/ - union { - fal_ip4_addr_t ipv4; - fal_ip6_addr_t ipv6; - } flow_ip; - a_uint16_t src_port; /*l4 source port*/ - a_uint16_t dst_port; /*l4 destination port*/ - a_uint32_t tree_id; /*for qos*/ - a_uint32_t pkt_counter; /*flow packet counter*/ - a_uint64_t byte_counter; /*flow byte counter*/ -} fal_flow_entry_t; - -typedef struct { - fal_fwd_cmd_t src_if_check_action; /*source inferface check fail action*/ - a_bool_t src_if_check_deacclr_en; /*0 for disable and 1 for enable*/ - a_bool_t service_loop_en; /*0 for disable and 1 for enable*/ - fal_fwd_cmd_t service_loop_action; /*0 for disable and 1 for enable*/ - a_bool_t service_loop_deacclr_en; /*0 for disable and 1 for enable*/ - fal_fwd_cmd_t flow_deacclr_action; /*flow de acceleration action*/ - fal_fwd_cmd_t sync_mismatch_action; /*sync toggle mismatch action*/ - a_bool_t sync_mismatch_deacclr_en; /*0 for disable and 1 for enable*/ - a_uint8_t hash_mode_0; /*0 crc10, 1 xor, 2 crc16*/ - a_uint8_t hash_mode_1; /*0 crc10, 1 xor, 2 crc16*/ - a_bool_t flow_mismatch_copy_escape_en; /*0 for disable and 1 for enable*/ -} fal_flow_global_cfg_t; - -typedef struct { - fal_flow_entry_t flow_entry; - fal_host_entry_t host_entry; -} fal_flow_host_entry_t; - -typedef struct { - a_uint16_t age_time; /* age value*/ - a_uint16_t unit; /*0:second 1:cycle 2:million cycle*/ -} fal_flow_age_timer_t; - -enum { - FUNC_FLOW_HOST_ADD = 0, - FUNC_FLOW_ENTRY_GET, - FUNC_FLOW_ENTRY_DEL, - FUNC_FLOW_STATUS_GET, - FUNC_FLOW_CTRL_SET, - FUNC_FLOW_AGE_TIMER_GET, - FUNC_FLOW_STATUS_SET, - FUNC_FLOW_HOST_GET, - FUNC_FLOW_HOST_DEL, - FUNC_FLOW_CTRL_GET, - FUNC_FLOW_AGE_TIMER_SET, - FUNC_FLOW_ENTRY_ADD, - FUNC_FLOW_GLOBAL_CFG_GET, - FUNC_FLOW_GLOBAL_CFG_SET, - FUNC_FLOW_ENTRY_NEXT -}; - -#ifndef IN_FLOW_MINI -sw_error_t -fal_flow_status_set(a_uint32_t dev_id, a_bool_t enable); - -sw_error_t -fal_flow_status_get(a_uint32_t dev_id, a_bool_t *enable); - -sw_error_t -fal_flow_age_timer_set(a_uint32_t dev_id, fal_flow_age_timer_t *age_timer); - -sw_error_t -fal_flow_age_timer_get(a_uint32_t dev_id, fal_flow_age_timer_t *age_timer); -#endif - -sw_error_t -fal_flow_mgmt_set( - a_uint32_t dev_id, - fal_flow_pkt_type_t type, - fal_flow_direction_t dir, - fal_flow_mgmt_t *mgmt); - -sw_error_t -fal_flow_mgmt_get( - a_uint32_t dev_id, - fal_flow_pkt_type_t type, - fal_flow_direction_t dir, - fal_flow_mgmt_t *mgmt); - -#ifndef IN_FLOW_MINI -sw_error_t -fal_flow_entry_add( - a_uint32_t dev_id, - a_uint32_t add_mode, /*index or hash*/ - fal_flow_entry_t *flow_entry); - -sw_error_t -fal_flow_entry_del( - a_uint32_t dev_id, - a_uint32_t del_mode, - fal_flow_entry_t *flow_entry); - -sw_error_t -fal_flow_entry_get( - a_uint32_t dev_id, - a_uint32_t get_mode, - fal_flow_entry_t *flow_entry); - -sw_error_t -fal_flow_entry_next( - a_uint32_t dev_id, - a_uint32_t next_mode, - fal_flow_entry_t *flow_entry); - -sw_error_t -fal_flow_host_add( - a_uint32_t dev_id, - a_uint32_t add_mode, - fal_flow_host_entry_t *flow_host_entry); - -sw_error_t -fal_flow_host_del( - a_uint32_t dev_id, - a_uint32_t del_mode, - fal_flow_host_entry_t *flow_host_entry); - -sw_error_t -fal_flow_host_get( - a_uint32_t dev_id, - a_uint32_t get_mode, - fal_flow_host_entry_t *flow_host_entry); - -sw_error_t -fal_flow_global_cfg_get( - a_uint32_t dev_id, - fal_flow_global_cfg_t *cfg); - -sw_error_t -fal_flow_global_cfg_set( - a_uint32_t dev_id, - fal_flow_global_cfg_t *cfg); -#endif - -#ifdef __cplusplus -} -#endif /* __cplusplus */ -#endif /* _FAL_FLOW_H_ */ - -/** - * @} - */ - diff --git a/feeds/ipq807x/qca-ssdk/src/include/fal/fal_flowcookie.h b/feeds/ipq807x/qca-ssdk/src/include/fal/fal_flowcookie.h deleted file mode 100755 index 857c5aa4f..000000000 --- a/feeds/ipq807x/qca-ssdk/src/include/fal/fal_flowcookie.h +++ /dev/null @@ -1,43 +0,0 @@ -/* - * Copyright (c) 2015, The Linux Foundation. All rights reserved. - * Permission to use, copy, modify, and/or distribute this software for - * any purpose with or without fee is hereby granted, provided that the - * above copyright notice and this permission notice appear in all copies. - * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES - * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR - * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES - * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN - * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT - * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. - */ - - -/** - * @defgroup - * @{ - */ -#ifndef _FAL_FLOWCOOKIE_H_ -#define _FAL_FLOWCOOKIE_H_ - -#ifdef __cplusplus -extern "C" { -#endif /* __cplusplus */ - -int ssdk_flow_cookie_set( - u32 protocol, __be32 src_ip, - __be16 src_port, __be32 dst_ip, - __be16 dst_port, u16 flowcookie); - - - -#ifdef __cplusplus -} -#endif /* __cplusplus */ -#endif /* _FAL_FLOWCOOKIE_H_ */ - -/** - * @} - */ - - diff --git a/feeds/ipq807x/qca-ssdk/src/include/fal/fal_igmp.h b/feeds/ipq807x/qca-ssdk/src/include/fal/fal_igmp.h deleted file mode 100755 index 36cee4e15..000000000 --- a/feeds/ipq807x/qca-ssdk/src/include/fal/fal_igmp.h +++ /dev/null @@ -1,161 +0,0 @@ -/* - * Copyright (c) 2012,2018, The Linux Foundation. All rights reserved. - * Permission to use, copy, modify, and/or distribute this software for - * any purpose with or without fee is hereby granted, provided that the - * above copyright notice and this permission notice appear in all copies. - * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES - * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR - * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES - * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN - * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT - * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. - */ - - -/** - * @defgroup fal_igmp FAL_IGMP - * @{ - */ -#ifndef _FAL_IGMP_H_ -#define _FAL_IGMP_H_ - -#ifdef __cplusplus -extern "C" { -#endif /* __cplusplus */ - -#include "sw.h" -#include "fal/fal_type.h" -#include "fal/fal_multi.h" - - - sw_error_t - fal_port_igmps_status_set(a_uint32_t dev_id, fal_port_t port_id, a_bool_t enable); - - - - sw_error_t - fal_port_igmps_status_get(a_uint32_t dev_id, fal_port_t port_id, a_bool_t *enable); - - - - sw_error_t - fal_igmp_mld_cmd_set(a_uint32_t dev_id, fal_fwd_cmd_t cmd); - - - - sw_error_t - fal_igmp_mld_cmd_get(a_uint32_t dev_id, fal_fwd_cmd_t * cmd); - - - - sw_error_t - fal_port_igmp_mld_join_set(a_uint32_t dev_id, fal_port_t port_id, a_bool_t enable); - - - - sw_error_t - fal_port_igmp_mld_join_get(a_uint32_t dev_id, fal_port_t port_id, a_bool_t * enable); - - - - sw_error_t - fal_port_igmp_mld_leave_set(a_uint32_t dev_id, fal_port_t port_id, a_bool_t enable); - - - - sw_error_t - fal_port_igmp_mld_leave_get(a_uint32_t dev_id, fal_port_t port_id, a_bool_t * enable); - - - - sw_error_t - fal_igmp_mld_rp_set(a_uint32_t dev_id, fal_pbmp_t pts); - - - - sw_error_t - fal_igmp_mld_rp_get(a_uint32_t dev_id, fal_pbmp_t * pts); - - - - sw_error_t - fal_igmp_mld_entry_creat_set(a_uint32_t dev_id, a_bool_t enable); - - - - sw_error_t - fal_igmp_mld_entry_creat_get(a_uint32_t dev_id, a_bool_t * enable); - - - sw_error_t - fal_igmp_mld_entry_static_set(a_uint32_t dev_id, a_bool_t static_en); - - - sw_error_t - fal_igmp_mld_entry_static_get(a_uint32_t dev_id, a_bool_t * static_en); - - - sw_error_t - fal_igmp_mld_entry_leaky_set(a_uint32_t dev_id, a_bool_t enable); - - - sw_error_t - fal_igmp_mld_entry_leaky_get(a_uint32_t dev_id, a_bool_t * enable); - - - sw_error_t - fal_igmp_mld_entry_v3_set(a_uint32_t dev_id, a_bool_t enable); - - - sw_error_t - fal_igmp_mld_entry_v3_get(a_uint32_t dev_id, a_bool_t * enable); - - - sw_error_t - fal_igmp_mld_entry_queue_set(a_uint32_t dev_id, a_bool_t enable, a_uint32_t queue); - - - sw_error_t - fal_igmp_mld_entry_queue_get(a_uint32_t dev_id, a_bool_t * enable, a_uint32_t * queue); - - - sw_error_t - fal_port_igmp_mld_learn_limit_set(a_uint32_t dev_id, fal_port_t port_id, - a_bool_t enable, a_uint32_t cnt); - - - sw_error_t - fal_port_igmp_mld_learn_limit_get(a_uint32_t dev_id, fal_port_t port_id, - a_bool_t * enable, a_uint32_t * cnt); - - - sw_error_t - fal_port_igmp_mld_learn_exceed_cmd_set(a_uint32_t dev_id, fal_port_t port_id, - fal_fwd_cmd_t cmd); - - - sw_error_t - fal_port_igmp_mld_learn_exceed_cmd_get(a_uint32_t dev_id, fal_port_t port_id, - fal_fwd_cmd_t * cmd); - - sw_error_t - fal_igmp_sg_entry_set(a_uint32_t dev_id, fal_igmp_sg_entry_t * entry); - - sw_error_t - fal_igmp_sg_entry_clear(a_uint32_t dev_id, fal_igmp_sg_entry_t * entry); - - sw_error_t - fal_igmp_sg_entry_show(a_uint32_t dev_id); - - sw_error_t - fal_igmp_sg_entry_query(a_uint32_t dev_id, fal_igmp_sg_info_t * info); - -#ifdef __cplusplus -} -#endif /* __cplusplus */ -#endif /* _FAL_IGMP_H_ */ - -/** - * @} - */ diff --git a/feeds/ipq807x/qca-ssdk/src/include/fal/fal_init.h b/feeds/ipq807x/qca-ssdk/src/include/fal/fal_init.h deleted file mode 100755 index 2d372c56a..000000000 --- a/feeds/ipq807x/qca-ssdk/src/include/fal/fal_init.h +++ /dev/null @@ -1,84 +0,0 @@ -/* - * Copyright (c) 2012, 2016-2019, The Linux Foundation. All rights reserved. - * Permission to use, copy, modify, and/or distribute this software for - * any purpose with or without fee is hereby granted, provided that the - * above copyright notice and this permission notice appear in all copies. - * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES - * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR - * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES - * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN - * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT - * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. - */ - -/*qca808x_start*/ -/** - * @defgroup fal_init FAL_INIT - * @{ - */ -#ifndef _FAL_INIT_H_ -#define _FAL_INIT_H_ - -#ifdef __cplusplus -extern "C" { -#endif /* __cplusplus */ - -#include "ssdk_init.h" -/*qca808x_end*/ -enum{ - FAL_MODULE_ACL, - FAL_MODULE_VSI, - FAL_MODULE_IP, - FAL_MODULE_FLOW, - FAL_MODULE_QM, - FAL_MODULE_QOS, - FAL_MODULE_BM, - FAL_MODULE_SERVCODE, - FAL_MODULE_RSS_HASH, - FAL_MODULE_PPPOE, - FAL_MODULE_SHAPER, - FAL_MODULE_PORTCTRL, - FAL_MODULE_MIB, - FAL_MODULE_MIRROR, - FAL_MODULE_FDB, - FAL_MODULE_STP, - FAL_MODULE_TRUNK, - FAL_MODULE_PORTVLAN, - FAL_MODULE_CTRLPKT, - FAL_MODULE_SEC, - FAL_MODULE_POLICER, - FAL_MODULE_MISC, - FAL_MODULE_PTP, - FAL_MODULE_SFP, - FAL_MODULE_MAX, -}; - -typedef struct -{ - a_uint32_t bitmap[3]; -}fal_func_ctrl_t; -/*qca808x_start*/ -sw_error_t fal_init(a_uint32_t dev_id, ssdk_init_cfg * cfg); -/*qca808x_end*/ -sw_error_t fal_reset(a_uint32_t dev_id); -sw_error_t fal_ssdk_cfg(a_uint32_t dev_id, ssdk_cfg_t *ssdk_cfg); -/*qca808x_start*/ -sw_error_t fal_cleanup(void); -/*qca808x_end*/ -sw_error_t fal_module_func_ctrl_set(a_uint32_t dev_id, - a_uint32_t module, fal_func_ctrl_t *func_ctrl); -sw_error_t fal_module_func_ctrl_get(a_uint32_t dev_id, - a_uint32_t module, fal_func_ctrl_t *func_ctrl); -sw_error_t fal_module_func_init(a_uint32_t dev_id, ssdk_init_cfg *cfg); -sw_error_t fal_switch_devid_get(ssdk_chip_type chip_type, a_uint32_t *pdev_id); - -/*qca808x_start*/ -#ifdef __cplusplus -} -#endif /* __cplusplus */ -#endif /* _FAL_INIT_H_ */ -/** - * @} - */ -/*qca808x_end*/ diff --git a/feeds/ipq807x/qca-ssdk/src/include/fal/fal_interface_ctrl.h b/feeds/ipq807x/qca-ssdk/src/include/fal/fal_interface_ctrl.h deleted file mode 100755 index f4383eed0..000000000 --- a/feeds/ipq807x/qca-ssdk/src/include/fal/fal_interface_ctrl.h +++ /dev/null @@ -1,181 +0,0 @@ -/* - * Copyright (c) 2012,2018, The Linux Foundation. All rights reserved. - * Permission to use, copy, modify, and/or distribute this software for - * any purpose with or without fee is hereby granted, provided that the - * above copyright notice and this permission notice appear in all copies. - * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES - * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR - * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES - * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN - * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT - * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. - */ - - -/** - * @defgroup fal_interface_ctrl FAL_INTERFACE_CONTROL - * @{ - */ -#ifndef _FAL_INTERFACECTRL_H_ -#define _FAL_INTERFACECTRL_H_ - -#ifdef __cplusplus -extern "c" { -#endif - -#include "sw.h" -#include "fal/fal_type.h" - - typedef enum { - FAL_MAC_MODE_RGMII = 0, - FAL_MAC_MODE_GMII, - FAL_MAC_MODE_MII, - FAL_MAC_MODE_SGMII, - FAL_MAC_MODE_FIBER, - FAL_MAC_MODE_RMII, - FAL_MAC_MODE_DEFAULT - } - fal_interface_mac_mode_t; - - typedef enum - { - FAL_INTERFACE_CLOCK_MAC_MODE = 0, - FAL_INTERFACE_CLOCK_PHY_MODE = 1, - } fal_interface_clock_mode_t; - - typedef struct - { - a_bool_t txclk_delay_cmd; - a_bool_t rxclk_delay_cmd; - a_uint32_t txclk_delay_sel; - a_uint32_t rxclk_delay_sel; - } fal_mac_rgmii_config_t; - - typedef struct - { - a_bool_t master_mode; - a_bool_t slave_mode; - a_bool_t clock_inverse; - a_bool_t pipe_rxclk_sel; - } fal_mac_rmii_config_t; - - typedef struct - { - fal_interface_clock_mode_t clock_mode; - a_uint32_t txclk_select; - a_uint32_t rxclk_select; - } fal_mac_gmii_config_t; - - typedef struct - { - fal_interface_clock_mode_t clock_mode; - a_uint32_t txclk_select; - a_uint32_t rxclk_select; - } fal_mac_mii_config_t; - - typedef struct - { - fal_interface_clock_mode_t clock_mode; - a_bool_t auto_neg; - a_bool_t force_speed; - a_bool_t prbs_enable; - a_bool_t rem_phy_lpbk; - } fal_mac_sgmii_config_t; - - typedef struct - { - a_bool_t auto_neg; - a_bool_t fx100_enable; - } fal_mac_fiber_config_t; - - typedef struct - { - fal_interface_mac_mode_t mac_mode; - union - { - fal_mac_rgmii_config_t rgmii; - fal_mac_gmii_config_t gmii; - fal_mac_mii_config_t mii; - fal_mac_sgmii_config_t sgmii; - fal_mac_rmii_config_t rmii; - fal_mac_fiber_config_t fiber; - } config; - } fal_mac_config_t; - - typedef struct - { - fal_interface_mac_mode_t mac_mode; - a_bool_t txclk_delay_cmd; - a_bool_t rxclk_delay_cmd; - a_uint32_t txclk_delay_sel; - a_uint32_t rxclk_delay_sel; - } fal_phy_config_t; - - typedef enum - { - Fx100BASE_MODE = 2, - } fx100_ctrl_link_mode_t; - - typedef enum - { - FX100_SERDS_MODE = 1, - } sgmii_fiber_mode_t; - -#define FX100_HALF_DUPLEX 0 -#define FX100_FULL_DUPLEX 1 - - typedef struct - { - fx100_ctrl_link_mode_t link_mode; - a_bool_t overshoot; - a_bool_t loopback; - a_bool_t fd_mode; - a_bool_t col_test; - sgmii_fiber_mode_t sgmii_fiber_mode; - a_bool_t crs_ctrl; - a_bool_t loopback_ctrl; - a_bool_t crs_col_100_ctrl; - a_bool_t loop_en; - } fal_fx100_ctrl_config_t; - - sw_error_t - fal_port_3az_status_set(a_uint32_t dev_id, fal_port_t port_id, a_bool_t enable); - - sw_error_t - fal_port_3az_status_get(a_uint32_t dev_id, fal_port_t port_id, a_bool_t * enable); - - sw_error_t - fal_interface_mac_mode_set(a_uint32_t dev_id, fal_port_t port_id, fal_mac_config_t * config); - - sw_error_t - fal_interface_mac_mode_get(a_uint32_t dev_id, fal_port_t port_id, fal_mac_config_t * config); - - sw_error_t - fal_interface_phy_mode_set(a_uint32_t dev_id, a_uint32_t phy_id, fal_phy_config_t * config); - - sw_error_t - fal_interface_phy_mode_get(a_uint32_t dev_id, a_uint32_t phy_id, fal_phy_config_t * config); - - sw_error_t - fal_interface_fx100_ctrl_set(a_uint32_t dev_id, fal_fx100_ctrl_config_t * config); - - sw_error_t - fal_interface_fx100_ctrl_get(a_uint32_t dev_id, fal_fx100_ctrl_config_t * config); - - sw_error_t - fal_interface_fx100_status_get(a_uint32_t dev_id, a_uint32_t* status); - - sw_error_t - fal_interface_mac06_exch_set(a_uint32_t dev_id, a_bool_t enable); - - sw_error_t - fal_interface_mac06_exch_get(a_uint32_t dev_id, a_bool_t* enable); - -#ifdef __cplusplus -} -#endif /* __cplusplus */ -#endif /* _FAL_INTERFACECTRL_H_ */ -/** - * @} - */ diff --git a/feeds/ipq807x/qca-ssdk/src/include/fal/fal_ip.h b/feeds/ipq807x/qca-ssdk/src/include/fal/fal_ip.h deleted file mode 100755 index 54eed8953..000000000 --- a/feeds/ipq807x/qca-ssdk/src/include/fal/fal_ip.h +++ /dev/null @@ -1,646 +0,0 @@ -/* - * Copyright (c) 2012, 2015, 2017-2018, The Linux Foundation. All rights reserved. - * Permission to use, copy, modify, and/or distribute this software for - * any purpose with or without fee is hereby granted, provided that the - * above copyright notice and this permission notice appear in all copies. - * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES - * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR - * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES - * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN - * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT - * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. - */ - - -/** - * @defgroup fal_ip FAL_IP - * @{ - */ -#ifndef _FAL_IP_H_ -#define _FAL_IP_H_ - -#ifdef __cplusplus -extern "C" { -#endif /* __cplusplus */ - -#include "sw.h" -#include "fal/fal_type.h" -#include "fal_multi.h" - - -#define FAL_MIN_VRF_ID 0 -#define FAL_MAX_VRF_ID 7 - /* IP WCMP hash key flags */ -#define FAL_WCMP_HASH_KEY_SIP 0x1 -#define FAL_WCMP_HASH_KEY_DIP 0x2 -#define FAL_WCMP_HASH_KEY_SPORT 0x4 -#define FAL_WCMP_HASH_KEY_DPORT 0x8 - - /* IP entry operation flags */ -#define FAL_IP_ENTRY_ID_EN 0x1 -#define FAL_IP_ENTRY_INTF_EN 0x2 -#define FAL_IP_ENTRY_PORT_EN 0x4 -#define FAL_IP_ENTRY_STATUS_EN 0x8 -#define FAL_IP_ENTRY_IPADDR_EN 0x10 -#define FAL_IP_ENTRY_ALL_EN 0x20 - - /* IP host entry structure flags field */ -#define FAL_IP_IP4_ADDR 0x1 -#define FAL_IP_IP6_ADDR 0x2 -#define FAL_IP_CPU_ADDR 0x4 -#define FAL_IP_IP4_ADDR_MCAST 0x8 -#define FAL_IP_IP6_ADDR_MCAST 0x10 - -typedef struct { - a_uint8_t vsi; /*vsi value for l2 multicast*/ - fal_ip4_addr_t sip4_addr; /*source ipv4 address*/ - fal_ip6_addr_t sip6_addr; /*source ipv4 address*/ -} fal_host_mcast_t; - -typedef struct -{ - a_uint32_t rx_pkt_counter; /*rx packet counter*/ - a_uint64_t rx_byte_counter; /*rx byte counter*/ - a_uint32_t rx_drop_pkt_counter; /*rx drop packet counter*/ - a_uint64_t rx_drop_byte_counter; /*rx drop byte counter*/ - a_uint32_t tx_pkt_counter; /*tx packet counter*/ - a_uint64_t tx_byte_counter; /*tx byte counter*/ - a_uint32_t tx_drop_pkt_counter; /*tx drop packet counter*/ - a_uint64_t tx_drop_byte_counter; /*tx drop byte counter*/ -} fal_ip_counter_t; - -typedef struct -{ - a_uint32_t entry_id; /*index for host table*/ - a_uint32_t flags; /*1:ipv4 uni 2:ipv6 uni 8:ipv4 multi 0x10:ipv6 multi*/ - a_uint32_t status; /* valid status: 0 or 1*/ - fal_ip4_addr_t ip4_addr; /* ipv4 address */ - fal_ip6_addr_t ip6_addr; /* ipv6 address */ - fal_mac_addr_t mac_addr; /* unused for ppe */ - a_uint32_t intf_id; /* unused for ppe */ - a_uint32_t lb_num; /* unused for ppe */ - a_uint32_t vrf_id; /* unused for ppe */ - a_uint32_t expect_vid; /* unused for ppe */ - fal_port_t port_id; /* unused for ppe */ - a_bool_t mirror_en; /* unused for ppe */ - a_bool_t counter_en; /* unused for ppe */ - a_uint32_t counter_id; /* unused for ppe */ - a_uint32_t packet; /* unused for ppe */ - a_uint32_t byte; /* unused for ppe */ - a_bool_t pppoe_en; /* unused for ppe */ - a_uint32_t pppoe_id; /* unused for ppe */ - fal_fwd_cmd_t action; /*forward action*/ - a_uint32_t dst_info; /*bit 12:13: 1.nexthop, 2.port id, 3.port bitmap*/ - a_uint8_t syn_toggle; /* sync toggle */ - a_uint8_t lan_wan; /*0: ip over lan side ; 1: ip over wan side*/ - fal_host_mcast_t mcast_info; /* multicast information */ -} fal_host_entry_t; - - typedef enum - { - FAL_MAC_IP_GUARD = 0, - FAL_MAC_IP_PORT_GUARD, - FAL_MAC_IP_VLAN_GUARD, - FAL_MAC_IP_PORT_VLAN_GUARD, - FAL_NO_SOURCE_GUARD, - } fal_source_guard_mode_t; - - typedef enum - { - FAL_DEFAULT_FLOW_FORWARD = 0, - FAL_DEFAULT_FLOW_DROP, - FAL_DEFAULT_FLOW_RDT_TO_CPU, - FAL_DEFAULT_FLOW_ADMIT_ALL, - } fal_default_flow_cmd_t; - - typedef enum - { - FAL_FLOW_LAN_TO_LAN = 0, - FAL_FLOW_WAN_TO_LAN, - FAL_FLOW_LAN_TO_WAN, - FAL_FLOW_WAN_TO_WAN, - } fal_flow_type_t; - - typedef enum - { - FAL_GLB_LOCK_TIME_DISABLE = 0, - FAL_GLB_LOCK_TIME_100US, - FAL_GLB_LOCK_TIME_1MS, - FAL_GLB_LOCK_TIME_10MS, - } fal_glb_lock_time_t; - - typedef enum - { - FAL_ARP_LEARN_LOCAL = 0, - FAL_ARP_LEARN_ALL, - } fal_arp_learn_mode_t; - - /* IP host entry auto learn arp packets type */ -#define FAL_ARP_LEARN_REQ 0x1 -#define FAL_ARP_LEARN_ACK 0x2 - - typedef struct - { - a_uint32_t entry_id; - a_uint32_t vrf_id; - a_uint16_t vid_low; - a_uint16_t vid_high; - fal_mac_addr_t mac_addr; - a_bool_t ip4_route; - a_bool_t ip6_route; - } fal_intf_mac_entry_t; - - typedef struct - { - a_uint32_t nh_nr; - a_uint32_t nh_id[16]; - } fal_ip_wcmp_t; - - typedef struct - { - fal_mac_addr_t mac_addr; - fal_ip4_addr_t ip4_addr; - a_uint32_t vid; - a_uint8_t load_balance; - } fal_ip4_rfs_t; - - typedef struct - { - fal_mac_addr_t mac_addr; - fal_ip6_addr_t ip6_addr; - a_uint32_t vid; - a_uint8_t load_balance; - } fal_ip6_rfs_t; - - typedef struct - { - a_bool_t valid; - a_uint32_t vrf_id; - fal_addr_type_t ip_version; /*0 for IPv4 and 1 for IPv6*/ - a_uint32_t droute_type; /*0 for ARP and 1 for WCMP*/ - a_uint32_t index;/*when droute_type equals 0, means ARP entry index or means WCMP indexs*/ - } fal_default_route_t; - - typedef struct - { - a_bool_t valid; - a_uint32_t vrf_id; - a_uint32_t ip_version; /*0 for IPv4 and 1 for IPv6*/ - union { - fal_ip4_addr_t ip4_addr; - fal_ip6_addr_t ip6_addr; - }route_addr; - a_uint32_t prefix_length;/*For IPv4, up to 32 and for IPv6, up to 128*/ - } fal_host_route_t; - -typedef struct -{ - a_bool_t ipv4_arp_sg_en; /*0 for disable and 1 for enable*/ - fal_fwd_cmd_t ipv4_arp_sg_vio_action; /* check fail action for arp source guard */ - a_bool_t ipv4_arp_sg_port_en; /* source port based arp source guard enable */ - a_bool_t ipv4_arp_sg_svlan_en; /* source svlan based arp source guard enable */ - a_bool_t ipv4_arp_sg_cvlan_en; /* source cvlan based arp source guard enable */ - fal_fwd_cmd_t ipv4_arp_src_unk_action; /* unknown action for arp source guard */ - a_bool_t ip_nd_sg_en; /*0 for disable and 1 for enable*/ - fal_fwd_cmd_t ip_nd_sg_vio_action; /* check fail action for nd source guard */ - a_bool_t ip_nd_sg_port_en; /* source port based nd source guard enable */ - a_bool_t ip_nd_sg_svlan_en; /* source svlan based nd source guard enable */ - a_bool_t ip_nd_sg_cvlan_en; /* source cvlan based nd source guard enable */ - fal_fwd_cmd_t ip_nd_src_unk_action; /* unknown action for nd source guard */ -} fal_arp_sg_cfg_t; - -typedef enum -{ - FAL_MC_MODE_GV = 0, /*not support igmpv3 source filter*/ - FAL_MC_MODE_SGV /*support igmpv3 source filter*/ -} fal_mc_mode_t; - -typedef struct -{ - a_bool_t l2_ipv4_mc_en; /*0 for disable and 1 for enable*/ - fal_mc_mode_t l2_ipv4_mc_mode; /*two modes*/ - a_bool_t l2_ipv6_mc_en; /*0 for disable and 1 for enable*/ - fal_mc_mode_t l2_ipv6_mc_mode; /*same with IPv4*/ -} fal_mc_mode_cfg_t; - -typedef struct -{ - a_uint8_t type; /*0 for IPv4 and 1 for IPv6*/ - fal_fwd_cmd_t action; /* forward action */ - a_uint32_t dst_info; /*bit 12:13: 1.nexthop, 2.port id, 3.port bitmap*/ - a_uint8_t lan_wan; /* 0:ip over lan side; 1:ip over wan side */ - union { - fal_ip4_addr_t ip4_addr; /* ipv4 address */ - fal_ip6_addr_t ip6_addr; /* ipv6 address */ - } route_addr; - union { - fal_ip4_addr_t ip4_addr_mask; /* ipv4 address mask */ - fal_ip6_addr_t ip6_addr_mask; /* ipv6 address mask */ - } route_addr_mask; -} fal_network_route_entry_t; - -typedef struct { - a_uint16_t mru; /* Maximum Receive Unit*/ - a_uint16_t mtu; /* Maximum Transmission Unit*/ - a_bool_t ttl_dec_bypass_en; /* Bypass TTL Decrement enable*/ - a_bool_t ipv4_uc_route_en; /*0 for disble and 1 for enable*/ - a_bool_t ipv6_uc_route_en; /*0 for disble and 1 for enable*/ - a_bool_t icmp_trigger_en; /* ICMP trigger flag enable*/ - fal_fwd_cmd_t ttl_exceed_action; /*action for ttl 0*/ - a_bool_t ttl_exceed_deacclr_en; /*0 for disble and 1 for enable*/ - a_uint8_t mac_addr_bitmap; /* bitmap for mac address*/ - fal_mac_addr_t mac_addr; /* mac address */ - fal_ip_counter_t counter; /* interface related counter */ -} fal_intf_entry_t; - -typedef struct -{ - a_bool_t l3_if_valid; /*0 for disable and 1 for enable*/ - a_uint32_t l3_if_index; /*index for interface table*/ -} fal_intf_id_t; - -typedef enum -{ - FAL_NEXTHOP_L3 = 0, - FAL_NEXTHOP_VP, -} fal_nexthop_type_t; - -typedef struct -{ - fal_nexthop_type_t type; /* 0: L3 1:port*/ - a_uint8_t vsi; /* output vsi value if type is 0 */ - fal_port_t port; /* destination port */ - a_uint32_t if_index; /* egress interface index */ - a_bool_t ip_to_me_en; /* 0 for disable and 1 for enable*/ - a_uint8_t pub_ip_index; /*index to public ip address*/ - a_uint8_t stag_fmt; /* 0: untag 1:tagged*/ - a_uint16_t svid; /*svlan id*/ - a_int8_t ctag_fmt; /* 0: untag 1:tagged*/ - a_uint16_t cvid; /* cvlan id */ - fal_mac_addr_t mac_addr; /* mac address */ - fal_ip4_addr_t dnat_ip; /*dnat ip address*/ -} fal_ip_nexthop_t; - -typedef struct -{ - a_bool_t ipv4_sg_en; /*0 for disable and 1 for enable*/ - fal_fwd_cmd_t ipv4_sg_vio_action; /* check fail action for ipv4 source guard */ - a_bool_t ipv4_sg_port_en; /* source port based ipv4 source guard enable */ - a_bool_t ipv4_sg_svlan_en; /* source svlan based ipv4 source guard enable */ - a_bool_t ipv4_sg_cvlan_en; /* source cvlan based ipv4 source guard enable */ - fal_fwd_cmd_t ipv4_src_unk_action; /* unknown action for ipv4 source guard */ - a_bool_t ipv6_sg_en; /*0 for disable and 1 for enable*/ - fal_fwd_cmd_t ipv6_sg_vio_action; /* check fail action for ipv6 source guard */ - a_bool_t ipv6_sg_port_en; /* source port based ipv6 source guard enable */ - a_bool_t ipv6_sg_svlan_en; /* source svlan based ipv6 source guard enable */ - a_bool_t ipv6_sg_cvlan_en; /* source cvlan based ipv6 source guard enable */ - fal_fwd_cmd_t ipv6_src_unk_action; /* unknown action for ipv6 source guard */ -} fal_sg_cfg_t; - -typedef struct -{ - fal_ip4_addr_t pub_ip_addr; /*public ip address*/ -} fal_ip_pub_addr_t; - -typedef struct { - a_bool_t valid; /* valid flag */ - fal_mac_addr_t mac_addr; /* mac address */ -} fal_macaddr_entry_t; - -typedef struct -{ - fal_fwd_cmd_t mru_fail_action; /*mru check fail action*/ - a_bool_t mru_deacclr_en; /*0 for disable and 1 for enable*/ - fal_fwd_cmd_t mtu_fail_action; /*mtu check fail action*/ - a_bool_t mtu_deacclr_en; /*0 for disable and 1 for enable*/ - fal_fwd_cmd_t mtu_nonfrag_fail_action; /*mtu check fail action for non-fragment */ - a_bool_t mtu_df_deacclr_en; /*0 for disable and 1 for enable*/ - fal_fwd_cmd_t prefix_bc_action; /*0 forward, 1 drop, 2 copy, 3 rdt_cpu*/ - a_bool_t prefix_deacclr_en; /*0 for disable and 1 for enable*/ - fal_fwd_cmd_t icmp_rdt_action; /*0 forward, 1 drop, 2 copy, 3 rdt_cpu*/ - a_bool_t icmp_rdt_deacclr_en; /*0 for disable and 1 for enable*/ - a_uint8_t hash_mode_0; /*0 crc10, 1 xor, 2 crc16*/ - a_uint8_t hash_mode_1; /*0 crc10, 1 xor, 2 crc16*/ -} fal_ip_global_cfg_t; - -enum { - FUNC_IP_NETWORK_ROUTE_GET = 0, - FUNC_IP_HOST_ADD, - FUNC_IP_VSI_SG_CFG_GET, - FUNC_IP_PUB_ADDR_SET, - FUNC_IP_PORT_SG_CFG_SET, - FUNC_IP_PORT_INTF_GET, - FUNC_IP_VSI_ARP_SG_CFG_SET, - FUNC_IP_PUB_ADDR_GET, - FUNC_IP_PORT_INTF_SET, - FUNC_IP_VSI_SG_CFG_SET, - FUNC_IP_HOST_NEXT, - FUNC_IP_PORT_MACADDR_SET, - FUNC_IP_VSI_INTF_GET, - FUNC_IP_NETWORK_ROUTE_ADD, - FUNC_IP_PORT_SG_CFG_GET, - FUNC_IP_INTF_GET, - FUNC_IP_NETWORK_ROUTE_DEL, - FUNC_IP_HOST_DEL, - FUNC_IP_ROUTE_MISMATCH_GET, - FUNC_IP_VSI_ARP_SG_CFG_GET, - FUNC_IP_PORT_ARP_SG_CFG_SET, - FUNC_IP_VSI_MC_MODE_SET, - FUNC_IP_VSI_INTF_SET, - FUNC_IP_NEXTHOP_GET, - FUNC_IP_ROUTE_MISMATCH_SET, - FUNC_IP_HOST_GET, - FUNC_IP_INTF_SET, - FUNC_IP_VSI_MC_MODE_GET, - FUNC_IP_PORT_MACADDR_GET, - FUNC_IP_PORT_ARP_SG_CFG_GET, - FUNC_IP_NEXTHOP_SET, - FUNC_IP_GLOBAL_CTRL_GET, - FUNC_IP_GLOBAL_CTRL_SET, -}; - -#ifndef IN_IP_MINI -sw_error_t -fal_ip_host_add(a_uint32_t dev_id, fal_host_entry_t * host_entry); - -sw_error_t -fal_ip_host_del(a_uint32_t dev_id, a_uint32_t del_mode, - fal_host_entry_t * host_entry); - -sw_error_t -fal_ip_host_get(a_uint32_t dev_id, a_uint32_t get_mode, - fal_host_entry_t * host_entry); - -sw_error_t -fal_ip_host_next(a_uint32_t dev_id, a_uint32_t next_mode, - fal_host_entry_t * host_entry); - -sw_error_t -fal_ip_host_counter_bind(a_uint32_t dev_id, a_uint32_t entry_id, - a_uint32_t cnt_id, a_bool_t enable); - -sw_error_t -fal_ip_host_pppoe_bind(a_uint32_t dev_id, a_uint32_t entry_id, - a_uint32_t pppoe_id, a_bool_t enable); - -sw_error_t -fal_ip_pt_arp_learn_set(a_uint32_t dev_id, fal_port_t port_id, - a_uint32_t flags); - -sw_error_t -fal_ip_pt_arp_learn_get(a_uint32_t dev_id, fal_port_t port_id, - a_uint32_t * flags); - -sw_error_t -fal_ip_arp_learn_set(a_uint32_t dev_id, fal_arp_learn_mode_t mode); - -sw_error_t -fal_ip_arp_learn_get(a_uint32_t dev_id, fal_arp_learn_mode_t * mode); - -sw_error_t -fal_ip_source_guard_set(a_uint32_t dev_id, fal_port_t port_id, - fal_source_guard_mode_t mode); - -sw_error_t -fal_ip_source_guard_get(a_uint32_t dev_id, fal_port_t port_id, - fal_source_guard_mode_t * mode); - -sw_error_t -fal_ip_arp_guard_set(a_uint32_t dev_id, fal_port_t port_id, - fal_source_guard_mode_t mode); - -sw_error_t -fal_ip_arp_guard_get(a_uint32_t dev_id, fal_port_t port_id, - fal_source_guard_mode_t * mode); - -sw_error_t -fal_ip_route_status_set(a_uint32_t dev_id, a_bool_t enable); - -sw_error_t -fal_ip_route_status_get(a_uint32_t dev_id, a_bool_t * enable); - -sw_error_t -fal_ip_intf_entry_add(a_uint32_t dev_id, fal_intf_mac_entry_t * entry); - -sw_error_t -fal_ip_intf_entry_del(a_uint32_t dev_id, a_uint32_t del_mode, - fal_intf_mac_entry_t * entry); - -sw_error_t -fal_ip_intf_entry_next(a_uint32_t dev_id, a_uint32_t next_mode, - fal_intf_mac_entry_t * entry); - -sw_error_t -fal_ip_unk_source_cmd_set(a_uint32_t dev_id, fal_fwd_cmd_t cmd); - -sw_error_t -fal_ip_unk_source_cmd_get(a_uint32_t dev_id, fal_fwd_cmd_t * cmd); - -sw_error_t -fal_arp_unk_source_cmd_set(a_uint32_t dev_id, fal_fwd_cmd_t cmd); - -sw_error_t -fal_arp_unk_source_cmd_get(a_uint32_t dev_id, fal_fwd_cmd_t * cmd); - -sw_error_t -fal_ip_age_time_set(a_uint32_t dev_id, a_uint32_t * time); - -sw_error_t -fal_ip_age_time_get(a_uint32_t dev_id, a_uint32_t * time); - -sw_error_t -fal_ip_wcmp_entry_set(a_uint32_t dev_id, a_uint32_t wcmp_id, fal_ip_wcmp_t * wcmp); - -sw_error_t -fal_ip_wcmp_entry_get(a_uint32_t dev_id, a_uint32_t wcmp_id, fal_ip_wcmp_t * wcmp); - -sw_error_t -fal_ip_wcmp_hash_mode_set(a_uint32_t dev_id, a_uint32_t hash_mode); - -sw_error_t -fal_ip_rfs_ip4_rule_set(a_uint32_t dev_id, fal_ip4_rfs_t * rfs); - -sw_error_t -fal_ip_rfs_ip6_rule_set(a_uint32_t dev_id, fal_ip6_rfs_t * rfs); - -sw_error_t -fal_ip_rfs_ip4_rule_del(a_uint32_t dev_id, fal_ip4_rfs_t * rfs); - -sw_error_t -fal_ip_rfs_ip6_rule_del(a_uint32_t dev_id, fal_ip6_rfs_t * rfs); - -sw_error_t -fal_ip_wcmp_hash_mode_get(a_uint32_t dev_id, a_uint32_t * hash_mode); - -sw_error_t -fal_ip_vrf_base_addr_set(a_uint32_t dev_id, a_uint32_t vrf_id, fal_ip4_addr_t addr); - -sw_error_t -fal_ip_vrf_base_addr_get(a_uint32_t dev_id, a_uint32_t vrf_id, fal_ip4_addr_t * addr); - -sw_error_t -fal_ip_vrf_base_mask_set(a_uint32_t dev_id, a_uint32_t vrf_id, fal_ip4_addr_t addr); - -sw_error_t -fal_ip_vrf_base_mask_get(a_uint32_t dev_id, a_uint32_t vrf_id, fal_ip4_addr_t * addr); - -sw_error_t -fal_ip_default_route_set(a_uint32_t dev_id, a_uint32_t droute_id, - fal_default_route_t * entry); - -sw_error_t -fal_ip_default_route_get(a_uint32_t dev_id, a_uint32_t droute_id, - fal_default_route_t * entry); - -sw_error_t -fal_ip_host_route_set(a_uint32_t dev_id, a_uint32_t hroute_id, - fal_host_route_t * entry); - -sw_error_t -fal_ip_host_route_get(a_uint32_t dev_id, a_uint32_t hroute_id, - fal_host_route_t * entry); - -sw_error_t -fal_ip_wcmp_entry_set(a_uint32_t dev_id, a_uint32_t wcmp_id, - fal_ip_wcmp_t * wcmp); - -sw_error_t -fal_ip_wcmp_entry_get(a_uint32_t dev_id, a_uint32_t wcmp_id, - fal_ip_wcmp_t * wcmp); - -sw_error_t -fal_default_flow_cmd_set(a_uint32_t dev_id, a_uint32_t vrf_id, - fal_flow_type_t type, fal_default_flow_cmd_t cmd); - -sw_error_t -fal_default_flow_cmd_get(a_uint32_t dev_id, a_uint32_t vrf_id, - fal_flow_type_t type, fal_default_flow_cmd_t * cmd); - -sw_error_t -fal_default_rt_flow_cmd_set(a_uint32_t dev_id, a_uint32_t vrf_id, - fal_flow_type_t type, fal_default_flow_cmd_t cmd); - -sw_error_t -fal_default_rt_flow_cmd_get(a_uint32_t dev_id, a_uint32_t vrf_id, - fal_flow_type_t type, fal_default_flow_cmd_t * cmd); - -sw_error_t -fal_ip_vsi_arp_sg_cfg_get(a_uint32_t dev_id, a_uint32_t vsi, - fal_arp_sg_cfg_t *arp_sg_cfg); - -sw_error_t -fal_ip_vsi_arp_sg_cfg_set(a_uint32_t dev_id, a_uint32_t vsi, - fal_arp_sg_cfg_t *arp_sg_cfg); - -sw_error_t -fal_ip_network_route_add(a_uint32_t dev_id, a_uint32_t index, - fal_network_route_entry_t *entry); - -sw_error_t -fal_ip_network_route_get(a_uint32_t dev_id, - a_uint32_t index, a_uint8_t type, - fal_network_route_entry_t *entry); - -sw_error_t -fal_ip_network_route_del(a_uint32_t dev_id, - a_uint32_t index, a_uint8_t type); - -sw_error_t -fal_ip_intf_set(a_uint32_t dev_id, - a_uint32_t index, - fal_intf_entry_t *entry); - -sw_error_t -fal_ip_intf_get(a_uint32_t dev_id, - a_uint32_t index, - fal_intf_entry_t *entry); - -sw_error_t -fal_ip_vsi_intf_set(a_uint32_t dev_id, a_uint32_t vsi, fal_intf_id_t *id); - -sw_error_t -fal_ip_vsi_intf_get(a_uint32_t dev_id, a_uint32_t vsi, fal_intf_id_t *id); - -sw_error_t -fal_ip_port_intf_set(a_uint32_t dev_id, fal_port_t port_id, fal_intf_id_t *id); - -sw_error_t -fal_ip_port_intf_get(a_uint32_t dev_id, fal_port_t port_id, fal_intf_id_t *id); - -sw_error_t -fal_ip_nexthop_set(a_uint32_t dev_id, a_uint32_t index, - fal_ip_nexthop_t *entry); - -sw_error_t -fal_ip_nexthop_get(a_uint32_t dev_id, a_uint32_t index, - fal_ip_nexthop_t *entry); - -sw_error_t -fal_ip_vsi_sg_cfg_get(a_uint32_t dev_id, a_uint32_t vsi, - fal_sg_cfg_t *sg_cfg); - -sw_error_t -fal_ip_vsi_sg_cfg_set(a_uint32_t dev_id, a_uint32_t vsi, - fal_sg_cfg_t *sg_cfg); - -sw_error_t -fal_ip_port_sg_cfg_set(a_uint32_t dev_id, fal_port_t port_id, - fal_sg_cfg_t *sg_cfg); - -sw_error_t -fal_ip_port_sg_cfg_get(a_uint32_t dev_id, fal_port_t port_id, - fal_sg_cfg_t *sg_cfg); - -sw_error_t -fal_ip_pub_addr_set(a_uint32_t dev_id, a_uint32_t index, - fal_ip_pub_addr_t *entry); - -sw_error_t -fal_ip_pub_addr_get(a_uint32_t dev_id, a_uint32_t index, - fal_ip_pub_addr_t *entry); - -sw_error_t -fal_ip_port_macaddr_set(a_uint32_t dev_id, fal_port_t port_id, - fal_macaddr_entry_t *macaddr); - -sw_error_t -fal_ip_port_macaddr_get(a_uint32_t dev_id, fal_port_t port_id, - fal_macaddr_entry_t *macaddr); - -sw_error_t -fal_ip_route_mismatch_action_set(a_uint32_t dev_id, fal_fwd_cmd_t action); - -sw_error_t -fal_ip_route_mismatch_action_get(a_uint32_t dev_id, fal_fwd_cmd_t *action); - -sw_error_t -fal_ip_port_arp_sg_cfg_set(a_uint32_t dev_id, fal_port_t port_id, - fal_arp_sg_cfg_t *arp_sg_cfg); - -sw_error_t -fal_ip_port_arp_sg_cfg_get(a_uint32_t dev_id, fal_port_t port_id, - fal_arp_sg_cfg_t *arp_sg_cfg); - -sw_error_t -fal_ip_vsi_mc_mode_set(a_uint32_t dev_id, a_uint32_t vsi, - fal_mc_mode_cfg_t *cfg); - -sw_error_t -fal_ip_vsi_mc_mode_get(a_uint32_t dev_id, a_uint32_t vsi, - fal_mc_mode_cfg_t *cfg); - -sw_error_t -fal_ip_global_ctrl_get(a_uint32_t dev_id, fal_ip_global_cfg_t *cfg); - -sw_error_t -fal_ip_global_ctrl_set(a_uint32_t dev_id, fal_ip_global_cfg_t *cfg); -#endif - -#ifdef __cplusplus -} -#endif /* __cplusplus */ -#endif /* _FAL_IP_H_ */ -/** - * @} - */ diff --git a/feeds/ipq807x/qca-ssdk/src/include/fal/fal_leaky.h b/feeds/ipq807x/qca-ssdk/src/include/fal/fal_leaky.h deleted file mode 100755 index 01ad94e14..000000000 --- a/feeds/ipq807x/qca-ssdk/src/include/fal/fal_leaky.h +++ /dev/null @@ -1,107 +0,0 @@ -/* - * Copyright (c) 2012,2018, The Linux Foundation. All rights reserved. - * Permission to use, copy, modify, and/or distribute this software for - * any purpose with or without fee is hereby granted, provided that the - * above copyright notice and this permission notice appear in all copies. - * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES - * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR - * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES - * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN - * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT - * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. - */ - - -/** - * @defgroup fal_leaky FAL_LEAKY - * @{ - */ -#ifndef _FAL_LEAKY_H_ -#define _FAL_LEAKY_H_ - -#ifdef __cplusplus -extern "C" { -#endif /* __cplusplus */ - -#include "sw.h" -#include "fal/fal_type.h" - - /** - @brief This enum defines the leaky control mode. - */ - typedef enum { - FAL_LEAKY_PORT_CTRL = 0, /**< control leaky through port which packets received*/ - FAL_LEAKY_FDB_CTRL, /**< control leaky through fdb entry*/ - FAL_LEAKY_CTRL_MODE_BUTT - } - fal_leaky_ctrl_mode_t; - - - - sw_error_t - fal_uc_leaky_mode_set(a_uint32_t dev_id, - fal_leaky_ctrl_mode_t ctrl_mode); - - - - sw_error_t - fal_uc_leaky_mode_get(a_uint32_t dev_id, - fal_leaky_ctrl_mode_t * ctrl_mode); - - - - sw_error_t - fal_mc_leaky_mode_set(a_uint32_t dev_id, - fal_leaky_ctrl_mode_t ctrl_mode); - - - - sw_error_t - fal_mc_leaky_mode_get(a_uint32_t dev_id, - fal_leaky_ctrl_mode_t * ctrl_mode); - - - - sw_error_t - fal_port_arp_leaky_set(a_uint32_t dev_id, fal_port_t port_id, - a_bool_t enable); - - - - sw_error_t - fal_port_arp_leaky_get(a_uint32_t dev_id, fal_port_t port_id, - a_bool_t * enable); - - - - sw_error_t - fal_port_uc_leaky_set(a_uint32_t dev_id, fal_port_t port_id, - a_bool_t enable); - - - - sw_error_t - fal_port_uc_leaky_get(a_uint32_t dev_id, fal_port_t port_id, - a_bool_t * enable); - - - - sw_error_t - fal_port_mc_leaky_set(a_uint32_t dev_id, fal_port_t port_id, - a_bool_t enable); - - - - sw_error_t - fal_port_mc_leaky_get(a_uint32_t dev_id, fal_port_t port_id, - a_bool_t * enable); - - -#ifdef __cplusplus -} -#endif /* __cplusplus */ -#endif /* _FAL_LEAKY_H_ */ -/** - * @} - */ diff --git a/feeds/ipq807x/qca-ssdk/src/include/fal/fal_led.h b/feeds/ipq807x/qca-ssdk/src/include/fal/fal_led.h deleted file mode 100644 index 45d59dfd9..000000000 --- a/feeds/ipq807x/qca-ssdk/src/include/fal/fal_led.h +++ /dev/null @@ -1,142 +0,0 @@ -/* - * Copyright (c) 2012,2018,2020, The Linux Foundation. All rights reserved. - * Permission to use, copy, modify, and/or distribute this software for - * any purpose with or without fee is hereby granted, provided that the - * above copyright notice and this permission notice appear in all copies. - * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES - * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR - * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES - * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN - * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT - * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. - */ - - -/** - * @defgroup fal_led FAL_LED - * @{ - */ -#ifndef _FAL_LED_H_ -#define _FAL_LED_H_ - -#ifdef __cplusplus -extern "C" { -#endif /* __cplusplus */ - -#include "sw.h" -#include "fal/fal_type.h" - - /** - @brief This enum defines the led group. - */ - typedef enum { - LED_LAN_PORT_GROUP = 0, /**< control lan ports*/ - LED_WAN_PORT_GROUP, /**< control wan ports*/ - LED_MAC_PORT_GROUP, /**< control mac ports*/ - LED_GROUP_BUTT - } - led_pattern_group_t; - - /** - @brief This enum defines the led pattern id, each ports has three led - and pattern0 relates to led0, pattern1 relates to led1, pattern2 relates to led2. - */ - typedef a_uint32_t led_pattern_id_t; - - - /** - @brief This enum defines the led control pattern mode. - */ - typedef enum - { - LED_ALWAYS_OFF = 0, - LED_ALWAYS_BLINK, - LED_ALWAYS_ON, - LED_PATTERN_MAP_EN, - LED_PATTERN_MODE_BUTT - } led_pattern_mode_t; - - -#define FULL_DUPLEX_LIGHT_EN 0 -#define HALF_DUPLEX_LIGHT_EN 1 -#define POWER_ON_LIGHT_EN 2 -#define LINK_1000M_LIGHT_EN 3 -#define LINK_100M_LIGHT_EN 4 -#define LINK_10M_LIGHT_EN 5 -#define COLLISION_BLINK_EN 6 -#define RX_TRAFFIC_BLINK_EN 7 -#define TX_TRAFFIC_BLINK_EN 8 -#define LINKUP_OVERRIDE_EN 9 -#define LED_ACTIVE_HIGH 10 -#define LINK_2500M_LIGHT_EN 11 -#define LED_MAP_10M_SPEED \ - (BIT(POWER_ON_LIGHT_EN) | BIT(LINK_10M_LIGHT_EN) | BIT(COLLISION_BLINK_EN) |\ - BIT(RX_TRAFFIC_BLINK_EN) | BIT(TX_TRAFFIC_BLINK_EN) | BIT(LINKUP_OVERRIDE_EN)) -#define LED_MAP_100M_SPEED \ - (BIT(POWER_ON_LIGHT_EN) | BIT(LINK_100M_LIGHT_EN) | BIT(COLLISION_BLINK_EN) |\ - BIT(RX_TRAFFIC_BLINK_EN) | BIT(TX_TRAFFIC_BLINK_EN) | BIT(LINKUP_OVERRIDE_EN)) -#define LED_MAP_1000M_SPEED \ - (BIT(POWER_ON_LIGHT_EN) | BIT(LINK_1000M_LIGHT_EN) | BIT(COLLISION_BLINK_EN) |\ - BIT(RX_TRAFFIC_BLINK_EN) | BIT(TX_TRAFFIC_BLINK_EN) | BIT(LINKUP_OVERRIDE_EN)) -#define LED_MAP_2500M_SPEED \ - (BIT(POWER_ON_LIGHT_EN) | BIT(LINK_2500M_LIGHT_EN) | BIT(COLLISION_BLINK_EN) |\ - BIT(RX_TRAFFIC_BLINK_EN) | BIT(TX_TRAFFIC_BLINK_EN) | BIT(LINKUP_OVERRIDE_EN)) -#define LED_MAP_ALL_SPEED \ - (LED_MAP_10M_SPEED | LED_MAP_100M_SPEED | LED_MAP_1000M_SPEED |\ - LED_MAP_2500M_SPEED) - -#define PORT_LED_SOURCE_MAX 0x3 - - /** - @brief This enum defines the led control pattern map. - */ - typedef a_uint32_t led_pattern_map_t; - - - /** - @brief This enum defines the led control pattern mode. - */ - typedef enum - { - LED_BLINK_2HZ = 0, - LED_BLINK_4HZ, - LED_BLINK_8HZ, - LED_BLINK_TXRX, /**< Frequency relates to speed, 1000M-8HZ,100M->4HZ,10M->2HZ,Others->4HZ */ - LED_BLINK_FREQ_BUTT - } led_blink_freq_t; - - - typedef struct - { - led_pattern_mode_t mode; - led_pattern_map_t map; - led_blink_freq_t freq; - } led_ctrl_pattern_t; - - - - - - sw_error_t - fal_led_ctrl_pattern_set(a_uint32_t dev_id, led_pattern_group_t group, - led_pattern_id_t id, led_ctrl_pattern_t * pattern); - - - - sw_error_t - fal_led_ctrl_pattern_get(a_uint32_t dev_id, led_pattern_group_t group, - led_pattern_id_t id, led_ctrl_pattern_t * pattern); - - sw_error_t - fal_led_source_pattern_set(a_uint32_t dev_id, a_uint32_t source_id, - led_ctrl_pattern_t * pattern); - -#ifdef __cplusplus -} -#endif /* __cplusplus */ -#endif /* _FAL_LED_H_ */ -/** - * @} - */ - diff --git a/feeds/ipq807x/qca-ssdk/src/include/fal/fal_mib.h b/feeds/ipq807x/qca-ssdk/src/include/fal/fal_mib.h deleted file mode 100755 index b4b59ffd2..000000000 --- a/feeds/ipq807x/qca-ssdk/src/include/fal/fal_mib.h +++ /dev/null @@ -1,260 +0,0 @@ -/* - * Copyright (c) 2012, 2017-2018, The Linux Foundation. All rights reserved. - * Permission to use, copy, modify, and/or distribute this software for - * any purpose with or without fee is hereby granted, provided that the - * above copyright notice and this permission notice appear in all copies. - * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES - * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR - * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES - * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN - * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT - * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. - */ - - -/** - * @defgroup fal_mib FAL_MIB - * @{ - */ -#ifndef _FAL_MIB_H -#define _FAL_MIB_H - -#ifdef __cplusplus -extern "C" { -#endif /* __cplusplus */ - -#include "sw.h" -#include "fal/fal_type.h" - - /**@brief This structure defines the mib infomation. - */ - typedef struct - { - a_uint32_t RxBroad; - a_uint32_t RxPause; - a_uint32_t RxMulti; - a_uint32_t RxFcsErr; - a_uint32_t RxAllignErr; - a_uint32_t RxRunt; - a_uint32_t RxFragment; - a_uint32_t Rx64Byte; - a_uint32_t Rx128Byte; - a_uint32_t Rx256Byte; - a_uint32_t Rx512Byte; - a_uint32_t Rx1024Byte; - a_uint32_t Rx1518Byte; - a_uint32_t RxMaxByte; - a_uint32_t RxTooLong; - a_uint32_t RxGoodByte_lo; /**< low 32 bits of RxGoodByte statistc item */ - a_uint32_t RxGoodByte_hi; /**< high 32 bits of RxGoodByte statistc item*/ - a_uint32_t RxBadByte_lo; /**< low 32 bits of RxBadByte statistc item */ - a_uint32_t RxBadByte_hi; /**< high 32 bits of RxBadByte statistc item */ - a_uint32_t RxOverFlow; /* no this counter for Hawkeye*/ - a_uint32_t Filtered; /*no this counter for Hawkeye*/ - a_uint32_t TxBroad; - a_uint32_t TxPause; - a_uint32_t TxMulti; - a_uint32_t TxUnderRun; - a_uint32_t Tx64Byte; - a_uint32_t Tx128Byte; - a_uint32_t Tx256Byte; - a_uint32_t Tx512Byte; - a_uint32_t Tx1024Byte; - a_uint32_t Tx1518Byte; - a_uint32_t TxMaxByte; - a_uint32_t TxOverSize; /*no this counter for Hawkeye*/ - a_uint32_t TxByte_lo; /**< low 32 bits of TxByte statistc item */ - a_uint32_t TxByte_hi; /**< high 32 bits of TxByte statistc item */ - a_uint32_t TxCollision; - a_uint32_t TxAbortCol; - a_uint32_t TxMultiCol; - a_uint32_t TxSingalCol; - a_uint32_t TxExcDefer; - a_uint32_t TxDefer; - a_uint32_t TxLateCol; - a_uint32_t RxUniCast; - a_uint32_t TxUniCast; - a_uint32_t RxJumboFcsErr; /* add for Hawkeye*/ - a_uint32_t RxJumboAligenErr; /* add for Hawkeye*/ - a_uint32_t Rx14To63; /*add for ipq60xx lpbk port*/ - a_uint32_t RxTooLongByte_lo; /*add for ipq60xx lpbk port*/ - a_uint32_t RxTooLongByte_hi; /*add for ipq60xx lpbk port*/ - a_uint32_t RxRuntByte_lo; /*add for ipq60xx lpbk port*/ - a_uint32_t RxRuntByte_hi; /*add for ipq60xx lpbk port*/ - } fal_mib_info_t; - -/*define structure for software with 64bit*/ -typedef struct -{ - a_uint64_t RxBroad; - a_uint64_t RxPause; - a_uint64_t RxMulti; - a_uint64_t RxFcsErr; - a_uint64_t RxAllignErr; - a_uint64_t RxRunt; - a_uint64_t RxFragment; - a_uint64_t Rx64Byte; - a_uint64_t Rx128Byte; - a_uint64_t Rx256Byte; - a_uint64_t Rx512Byte; - a_uint64_t Rx1024Byte; - a_uint64_t Rx1518Byte; - a_uint64_t RxMaxByte; - a_uint64_t RxTooLong; - a_uint64_t RxGoodByte; - a_uint64_t RxBadByte; - a_uint64_t RxOverFlow; /* no this counter for Hawkeye*/ - a_uint64_t Filtered; /*no this counter for Hawkeye*/ - a_uint64_t TxBroad; - a_uint64_t TxPause; - a_uint64_t TxMulti; - a_uint64_t TxUnderRun; - a_uint64_t Tx64Byte; - a_uint64_t Tx128Byte; - a_uint64_t Tx256Byte; - a_uint64_t Tx512Byte; - a_uint64_t Tx1024Byte; - a_uint64_t Tx1518Byte; - a_uint64_t TxMaxByte; - a_uint64_t TxOverSize; /*no this counter for Hawkeye*/ - a_uint64_t TxByte; - a_uint64_t TxCollision; - a_uint64_t TxAbortCol; - a_uint64_t TxMultiCol; - a_uint64_t TxSingalCol; - a_uint64_t TxExcDefer; - a_uint64_t TxDefer; - a_uint64_t TxLateCol; - a_uint64_t RxUniCast; - a_uint64_t TxUniCast; - a_uint64_t RxJumboFcsErr; /* add for Hawkeye*/ - a_uint64_t RxJumboAligenErr; /* add for Hawkeye*/ - a_uint64_t Rx14To63; /*add for ipq60xx lpbk port*/ - a_uint64_t RxTooLongByte; /*add for ipq60xx lpbk port*/ - a_uint64_t RxRuntByte; /*add for ipq60xx lpbk port*/ -} fal_mib_counter_t; - -enum -{ - /*mib*/ - FUNC_GET_MIB_INFO = 0, - FUNC_GET_RX_MIB_INFO, - FUNC_GET_TX_MIB_INFO, - FUNC_GET_XGMIB_INFO, - FUNC_GET_TX_XGMIB_INFO, - FUNC_GET_RX_XGMIB_INFO, - FUNC_MIB_STATUS_SET, - FUNC_MIB_STATUS_GET, - FUNC_MIB_PORT_FLUSH_COUNTERS, - FUNC_MIB_CPUKEEP_SET, - FUNC_MIB_CPUKEEP_GET -}; - -typedef struct -{ - a_uint64_t RxFrame; - a_uint64_t RxByte; - a_uint64_t RxByteGood; - a_uint64_t RxBroadGood; - a_uint64_t RxMultiGood; - a_uint64_t RxFcsErr; - a_uint64_t RxRuntErr ; - a_uint64_t RxJabberError; - a_uint64_t RxUndersizeGood; - a_uint64_t RxOversizeGood; - a_uint64_t Rx64Byte; - a_uint64_t Rx128Byte; - a_uint64_t Rx256Byte; - a_uint64_t Rx512Byte; - a_uint64_t Rx1024Byte; - a_uint64_t RxMaxByte; - a_uint64_t RxUnicastGood; - a_uint64_t RxLengthError; - a_uint64_t RxOutOfRangeError; - a_uint64_t RxPause; - a_uint64_t RxOverFlow; - a_uint64_t RxVLANFrameGoodBad; - a_uint64_t RxWatchDogError; - a_uint64_t RxLPIUsec; - a_uint64_t RxLPITran; - a_uint64_t RxDropFrameGoodBad; - a_uint64_t RxDropByteGoodBad; - - a_uint64_t TxByte; - a_uint64_t TxFrame; - a_uint64_t TxBroadGood; - a_uint64_t TxMultiGood; - a_uint64_t Tx64Byte; - a_uint64_t Tx128Byte; - a_uint64_t Tx256Byte; - a_uint64_t Tx512Byte; - a_uint64_t Tx1024Byte; - a_uint64_t TxMaxByte; - a_uint64_t TxUnicast; - a_uint64_t TxMulti; - a_uint64_t TxBroad; - a_uint64_t TxUnderFlowError; - a_uint64_t TxByteGood; - a_uint64_t TxFrameGood; - a_uint64_t TxPause; - a_uint64_t TxVLANFrameGood; - a_uint64_t TxLPIUsec; - a_uint64_t TxLPITran; -} fal_xgmib_info_t; - -sw_error_t -fal_get_xgmib_info(a_uint32_t dev_id, fal_port_t port_id, - fal_xgmib_info_t * mib_info ); - -sw_error_t -fal_get_rx_xgmib_info(a_uint32_t dev_id, fal_port_t port_id, - fal_xgmib_info_t * mib_info ); - -sw_error_t -fal_get_tx_xgmib_info(a_uint32_t dev_id, fal_port_t port_id, - fal_xgmib_info_t * mib_info ); - -sw_error_t -fal_get_mib_info(a_uint32_t dev_id, fal_port_t port_id, - fal_mib_info_t * mib_info ); - -sw_error_t -fal_get_rx_mib_info(a_uint32_t dev_id, fal_port_t port_id, - fal_mib_info_t * mib_info ); - -sw_error_t -fal_get_tx_mib_info(a_uint32_t dev_id, fal_port_t port_id, - fal_mib_info_t * mib_info ); - -sw_error_t -fal_mib_status_set(a_uint32_t dev_id, a_bool_t enable); - -sw_error_t -fal_mib_status_get(a_uint32_t dev_id, a_bool_t * enable); - -sw_error_t -fal_mib_port_flush_counters(a_uint32_t dev_id, fal_port_t port_id); - -sw_error_t -fal_mib_cpukeep_set(a_uint32_t dev_id, a_bool_t enable); - -sw_error_t -fal_mib_cpukeep_get(a_uint32_t dev_id, a_bool_t * enable); - -sw_error_t -fal_mib_counter_alloc(a_uint32_t dev_id, a_uint64_t **p_mibcounter); - -sw_error_t -fal_mib_counter_get(a_uint32_t dev_id, fal_port_t port_id, - fal_mib_counter_t *mib_counter); - - -#ifdef __cplusplus -} -#endif /* __cplusplus */ - -#endif /* _FAL_MIB_H */ -/** - * @} - */ diff --git a/feeds/ipq807x/qca-ssdk/src/include/fal/fal_mirror.h b/feeds/ipq807x/qca-ssdk/src/include/fal/fal_mirror.h deleted file mode 100755 index 51158d784..000000000 --- a/feeds/ipq807x/qca-ssdk/src/include/fal/fal_mirror.h +++ /dev/null @@ -1,86 +0,0 @@ -/* - * Copyright (c) 2012, 2016-2018, The Linux Foundation. All rights reserved. - * Permission to use, copy, modify, and/or distribute this software for - * any purpose with or without fee is hereby granted, provided that the - * above copyright notice and this permission notice appear in all copies. - * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES - * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR - * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES - * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN - * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT - * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. - */ - - -/** - * @defgroup fal_mirror FAL_MIRROR - * @{ - */ -#ifndef _FAL_MIRROR_H_ -#define _FAL_MIRROR_H_ - -#ifdef __cplusplus -extern "C" { -#endif /* __cplusplus */ - -#include "sw.h" -#include "fal/fal_type.h" - -typedef struct -{ - fal_port_t port_id; - a_uint32_t priority; -} fal_mirr_analysis_config_t; - -typedef enum -{ - FAL_MIRR_INGRESS= 0, - FAL_MIRR_EGRESS, - FAL_MIRR_BOTH, -} fal_mirr_direction_t; - -enum -{ - FUNC_MIRR_ANALYSIS_PORT_SET = 0, - FUNC_MIRR_ANALYSIS_PORT_GET, - FUNC_MIRR_PORT_IN_SET, - FUNC_MIRR_PORT_IN_GET, - FUNC_MIRR_PORT_EG_SET, - FUNC_MIRR_PORT_EG_GET, - FUNC_MIRR_ANALYSIS_CONFIG_SET, - FUNC_MIRR_ANALYSIS_CONFIG_GET, -}; - -sw_error_t -fal_mirr_analysis_port_set(a_uint32_t dev_id, fal_port_t port_id); - -sw_error_t -fal_mirr_analysis_port_get(a_uint32_t dev_id, fal_port_t * port_id); - -sw_error_t -fal_mirr_port_in_set(a_uint32_t dev_id, fal_port_t port_id, - a_bool_t enable); -sw_error_t -fal_mirr_port_in_get(a_uint32_t dev_id, fal_port_t port_id, - a_bool_t * enable); -sw_error_t -fal_mirr_port_eg_set(a_uint32_t dev_id, fal_port_t port_id, - a_bool_t enable); -sw_error_t -fal_mirr_port_eg_get(a_uint32_t dev_id, fal_port_t port_id, - a_bool_t * enable); - -sw_error_t -fal_mirr_analysis_config_set(a_uint32_t dev_id, fal_mirr_direction_t direction, fal_mirr_analysis_config_t * config); - -sw_error_t -fal_mirr_analysis_config_get(a_uint32_t dev_id, fal_mirr_direction_t direction, fal_mirr_analysis_config_t * config); - -#ifdef __cplusplus -} -#endif /* __cplusplus */ -#endif /* _PORT_MIRROR_H_ */ -/** - * @} - */ diff --git a/feeds/ipq807x/qca-ssdk/src/include/fal/fal_misc.h b/feeds/ipq807x/qca-ssdk/src/include/fal/fal_misc.h deleted file mode 100755 index c25d744a0..000000000 --- a/feeds/ipq807x/qca-ssdk/src/include/fal/fal_misc.h +++ /dev/null @@ -1,256 +0,0 @@ -/* - * Copyright (c) 2012, 2017-2018, The Linux Foundation. All rights reserved. - * Permission to use, copy, modify, and/or distribute this software for - * any purpose with or without fee is hereby granted, provided that the - * above copyright notice and this permission notice appear in all copies. - * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES - * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR - * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES - * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN - * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT - * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. - */ - - -/** - * @defgroup fal_gen FAL_MISC - * @{ - */ -#ifndef _FAL_MISC_H_ -#define _FAL_MISC_H_ - -#ifdef __cplusplus -extern "C" { -#endif /* __cplusplus */ - -#include "sw.h" -#include "fal/fal_type.h" - - - typedef enum - { - FAL_LOOP_CHECK_1MS = 0, - FAL_LOOP_CHECK_10MS, - FAL_LOOP_CHECK_100MS, - FAL_LOOP_CHECK_500MS, - } fal_loop_check_time_t; - - typedef struct - { - a_bool_t rx_counter_en; /* Enable/disable virtual port rx counter */ - a_bool_t vp_uni_tx_counter_en; /* Enable/disable virtual port unicast tx counter */ - a_bool_t port_mc_tx_counter_en; /* Enable/disable physical port multicast tx counter */ - a_bool_t port_tx_counter_en; /* Enable/disable physical port tx counter */ - } fal_counter_en_t; - - sw_error_t - fal_debug_port_counter_enable(a_uint32_t dev_id, fal_port_t port_id, fal_counter_en_t * cnt_en); - - sw_error_t - fal_debug_port_counter_status_get(a_uint32_t dev_id, fal_port_t port_id, fal_counter_en_t * cnt_en); - - /* define switch interrupt type bitmap */ -#define FAL_SWITCH_INTR_LINK_STATUS 0x1 /* up/down/speed/duplex status */ -#ifndef IN_MISC_MINI - sw_error_t fal_arp_status_set(a_uint32_t dev_id, a_bool_t enable); - - - - sw_error_t fal_arp_status_get(a_uint32_t dev_id, a_bool_t * enable); -#endif - - - sw_error_t fal_frame_max_size_set(a_uint32_t dev_id, a_uint32_t size); - - - - sw_error_t fal_frame_max_size_get(a_uint32_t dev_id, a_uint32_t * size); - - - - sw_error_t - fal_port_unk_sa_cmd_set(a_uint32_t dev_id, fal_port_t port_id, - fal_fwd_cmd_t cmd); - - sw_error_t - fal_port_unk_uc_filter_set(a_uint32_t dev_id, fal_port_t port_id, - a_bool_t enable); - - sw_error_t - fal_port_unk_mc_filter_set(a_uint32_t dev_id, fal_port_t port_id, - a_bool_t enable); - - sw_error_t - fal_port_bc_filter_set(a_uint32_t dev_id, fal_port_t port_id, - a_bool_t enable); - - sw_error_t - fal_port_unk_sa_cmd_get(a_uint32_t dev_id, fal_port_t port_id, - fal_fwd_cmd_t * cmd); - - sw_error_t - fal_port_unk_uc_filter_get(a_uint32_t dev_id, fal_port_t port_id, - a_bool_t * enable); - - sw_error_t - fal_port_unk_mc_filter_get(a_uint32_t dev_id, fal_port_t port_id, - a_bool_t * enable); - - - sw_error_t - fal_port_bc_filter_get(a_uint32_t dev_id, fal_port_t port_id, - a_bool_t * enable); - - - sw_error_t - fal_cpu_port_status_set(a_uint32_t dev_id, a_bool_t enable); - - -#ifndef IN_MISC_MINI - sw_error_t - fal_cpu_port_status_get(a_uint32_t dev_id, a_bool_t * enable); - - - - sw_error_t - fal_bc_to_cpu_port_set(a_uint32_t dev_id, a_bool_t enable); - - - - sw_error_t - fal_bc_to_cpu_port_get(a_uint32_t dev_id, a_bool_t * enable); - - - - sw_error_t - fal_port_dhcp_set(a_uint32_t dev_id, fal_port_t port_id, a_bool_t enable); - - - - sw_error_t - fal_port_dhcp_get(a_uint32_t dev_id, fal_port_t port_id, a_bool_t * enable); - - - sw_error_t - fal_arp_cmd_set(a_uint32_t dev_id, fal_fwd_cmd_t cmd); - - - sw_error_t - fal_arp_cmd_get(a_uint32_t dev_id, fal_fwd_cmd_t * cmd); -#endif - - sw_error_t - fal_eapol_cmd_set(a_uint32_t dev_id, fal_fwd_cmd_t cmd); - -#ifndef IN_MISC_MINI - sw_error_t - fal_eapol_cmd_get(a_uint32_t dev_id, fal_fwd_cmd_t * cmd); -#endif - sw_error_t - fal_eapol_status_set(a_uint32_t dev_id, a_uint32_t port_id, a_bool_t enable); -#ifndef IN_MISC_MINI - sw_error_t - fal_eapol_status_get(a_uint32_t dev_id, a_uint32_t port_id, a_bool_t * enable); - - sw_error_t - fal_ripv1_status_set(a_uint32_t dev_id, a_bool_t enable); - - sw_error_t - fal_ripv1_status_get(a_uint32_t dev_id, a_bool_t * enable); - - - sw_error_t - fal_port_arp_req_status_set(a_uint32_t dev_id, fal_port_t port_id, a_bool_t enable); - - - sw_error_t - fal_port_arp_req_status_get(a_uint32_t dev_id, fal_port_t port_id, a_bool_t *enable); - - - sw_error_t - fal_port_arp_ack_status_set(a_uint32_t dev_id, fal_port_t port_id, a_bool_t enable); - - - sw_error_t - fal_port_arp_ack_status_get(a_uint32_t dev_id, fal_port_t port_id, a_bool_t *enable); - - - sw_error_t - fal_intr_mask_set(a_uint32_t dev_id, a_uint32_t intr_mask); - - - sw_error_t - fal_intr_mask_get(a_uint32_t dev_id, a_uint32_t * intr_mask); - - - sw_error_t - fal_intr_status_get(a_uint32_t dev_id, a_uint32_t * intr_status); - - - sw_error_t - fal_intr_status_clear(a_uint32_t dev_id, a_uint32_t intr_status); - - - sw_error_t - fal_intr_port_link_mask_set(a_uint32_t dev_id, a_uint32_t port_id, a_uint32_t intr_mask); - - - sw_error_t - fal_intr_port_link_mask_get(a_uint32_t dev_id, a_uint32_t port_id, a_uint32_t * intr_mask); - - - sw_error_t - fal_intr_port_link_status_get(a_uint32_t dev_id, a_uint32_t port_id, a_uint32_t * intr_mask); - - - sw_error_t - fal_intr_mask_mac_linkchg_set(a_uint32_t dev_id, a_uint32_t port_id, a_bool_t enable); - - - sw_error_t - fal_intr_mask_mac_linkchg_get(a_uint32_t dev_id, a_uint32_t port_id, a_bool_t * enable); - - sw_error_t - fal_intr_status_mac_linkchg_get(a_uint32_t dev_id, fal_pbmp_t *port_bitmap); - - sw_error_t - fal_cpu_vid_en_set(a_uint32_t dev_id, a_bool_t enable); - - sw_error_t - fal_cpu_vid_en_get(a_uint32_t dev_id, a_bool_t * enable); - - sw_error_t - fal_intr_status_mac_linkchg_clear(a_uint32_t dev_id); - - sw_error_t - fal_global_macaddr_set(a_uint32_t dev_id, fal_mac_addr_t * addr); - - sw_error_t - fal_global_macaddr_get(a_uint32_t dev_id, fal_mac_addr_t * addr); - - - sw_error_t - fal_lldp_status_set(a_uint32_t dev_id, a_bool_t enable); - - - - sw_error_t - fal_lldp_status_get(a_uint32_t dev_id, a_bool_t * enable); - - sw_error_t - fal_frame_crc_reserve_set(a_uint32_t dev_id, a_bool_t enable); - - - - sw_error_t - fal_frame_crc_reserve_get(a_uint32_t dev_id, a_bool_t * enable); -#endif - -#ifdef __cplusplus -} -#endif /* __cplusplus */ -#endif /* _FAL_MISC_H_ */ -/** - * @} - */ diff --git a/feeds/ipq807x/qca-ssdk/src/include/fal/fal_multi.h b/feeds/ipq807x/qca-ssdk/src/include/fal/fal_multi.h deleted file mode 100755 index 30b727fd6..000000000 --- a/feeds/ipq807x/qca-ssdk/src/include/fal/fal_multi.h +++ /dev/null @@ -1,73 +0,0 @@ -/* - * Copyright (c) 2012, The Linux Foundation. All rights reserved. - * Permission to use, copy, modify, and/or distribute this software for - * any purpose with or without fee is hereby granted, provided that the - * above copyright notice and this permission notice appear in all copies. - * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES - * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR - * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES - * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN - * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT - * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. - */ - - -#ifndef _FAL_MULTI_H_ -#define _FAL_MULTI_H_ - -/*supports 32 entries*/ -#define FAL_IGMP_SG_ENTRY_MAX 32 - -typedef enum -{ - FAL_ADDR_IPV4 = 0, - FAL_ADDR_IPV6 -} fal_addr_type_t; - -typedef struct -{ - fal_addr_type_t type; - union - { - fal_ip4_addr_t ip4_addr; - fal_ip6_addr_t ip6_addr; - } u; -} fal_igmp_sg_addr_t; - -typedef struct -{ - fal_igmp_sg_addr_t source; - fal_igmp_sg_addr_t group; - fal_pbmp_t port_map; - a_uint32_t vlan_id; -} fal_igmp_sg_entry_t; - -//#define MULTI_DEBUG_ -#ifdef MULTI_DEBUG_ -#define MULTI_DEBUG(x...) aos_printk(x) -#else -#define MULTI_DEBUG(x...) -#endif - -#define FAL_ACL_LIST_MULTICAST 55 -#define FAL_MULTICAST_PRI 5 - -#define MULT_ACTION_SET 0 -#define MULT_ACTION_CLEAR 1 - -// static a_uint32_t rule_nr=1; - -typedef struct -{ - a_uint8_t index; //MAX is 32 - fal_igmp_sg_entry_t entry; //Stores the specific ACL rule info -} multi_acl_info_t; - -typedef struct -{ - a_uint8_t cnt; //MAX is 32 - multi_acl_info_t acl_info[FAL_IGMP_SG_ENTRY_MAX]; //Stores the all ACL rule info -} fal_igmp_sg_info_t; - -#endif diff --git a/feeds/ipq807x/qca-ssdk/src/include/fal/fal_nat.h b/feeds/ipq807x/qca-ssdk/src/include/fal/fal_nat.h deleted file mode 100755 index 643919cde..000000000 --- a/feeds/ipq807x/qca-ssdk/src/include/fal/fal_nat.h +++ /dev/null @@ -1,294 +0,0 @@ -/* - * Copyright (c) 2012, 2015,2018, The Linux Foundation. All rights reserved. - * Permission to use, copy, modify, and/or distribute this software for - * any purpose with or without fee is hereby granted, provided that the - * above copyright notice and this permission notice appear in all copies. - * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES - * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR - * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES - * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN - * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT - * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. - */ - - -/** - * @defgroup fal_nat FAL_NAT - * @{ - */ -#ifndef _FAL_NAT_H_ -#define _FAL_NAT_H_ - -#ifdef __cplusplus -extern "C" { -#endif /* __cplusplus */ - -#include "sw.h" -#include "fal/fal_type.h" - - -#define FAL_NAT_ENTRY_PROTOCOL_TCP 0x1 -#define FAL_NAT_ENTRY_PROTOCOL_UDP 0x2 -#define FAL_NAT_ENTRY_PROTOCOL_PPTP 0x4 -#define FAL_NAT_ENTRY_PROTOCOL_ANY 0x8 -#define FAL_NAT_ENTRY_TRANS_IPADDR_INDEX 0x10 -#define FAL_NAT_ENTRY_PORT_CHECK 0x20 -#define FAL_NAT_HASH_KEY_PORT 0x40 -#define FAL_NAT_HASH_KEY_IPADDR 0x80 - - - /* NAT entry operation flags */ -#define FAL_NAT_ENTRY_ID_EN 0x1 -#define FAL_NAT_ENTRY_SRC_IPADDR_EN 0x2 -#define FAL_NAT_ENTRY_TRANS_IPADDR_EN 0x4 -#define FAL_NAT_ENTRY_KEY_EN 0x8 -#define FAL_NAT_ENTRY_PUBLIC_IP_EN 0x10 -#define FAL_NAT_ENTRY_SOURCE_IP_EN 0x20 -#define FAL_NAT_ENTRY_AGE_EN 0x40 -#define FAL_NAT_ENTRY_SYNC_EN 0x80 - - - typedef struct - { - a_uint32_t entry_id; - a_uint32_t flags; - a_uint32_t status; - fal_ip4_addr_t src_addr; - fal_ip4_addr_t dst_addr; - a_uint16_t src_port; - a_uint16_t dst_port; - fal_ip4_addr_t trans_addr; - a_uint16_t trans_port; - a_uint16_t rsv; - a_bool_t mirror_en; - a_bool_t counter_en; - a_uint32_t counter_id; - a_uint32_t ingress_packet; - a_uint32_t ingress_byte; - a_uint32_t egress_packet; - a_uint32_t egress_byte; - fal_fwd_cmd_t action; - a_uint32_t load_balance; - a_uint32_t flow_cookie; - a_uint32_t vrf_id; - a_uint32_t aging_sync; - a_bool_t priority_en; - a_uint32_t priority_val; - } fal_napt_entry_t; - - typedef struct - { - a_uint32_t proto; /*1 tcp; 2 udp*/ - fal_ip4_addr_t src_addr; - fal_ip4_addr_t dst_addr; - a_uint16_t src_port; - a_uint16_t dst_port; - a_uint32_t flow_cookie; - } fal_flow_cookie_t; - - typedef struct - { - a_uint32_t proto; /*1 tcp; 2 udp*/ - fal_ip4_addr_t src_addr; - fal_ip4_addr_t dst_addr; - a_uint16_t src_port; - a_uint16_t dst_port; - a_uint8_t load_balance; - } fal_flow_rfs_t; - - - typedef struct - { - a_uint32_t entry_id; - a_uint32_t flags; - a_uint32_t status; - fal_ip4_addr_t src_addr; - fal_ip4_addr_t trans_addr; - a_uint16_t port_num; - a_uint16_t port_range; - a_uint32_t slct_idx; - a_bool_t mirror_en; - a_bool_t counter_en; - a_uint32_t counter_id; - a_uint32_t ingress_packet; - a_uint32_t ingress_byte; - a_uint32_t egress_packet; - a_uint32_t egress_byte; - fal_fwd_cmd_t action; - a_uint32_t vrf_id; - } fal_nat_entry_t; - - - typedef enum - { - FAL_NAPT_FULL_CONE = 0, - FAL_NAPT_STRICT_CONE, - FAL_NAPT_PORT_STRICT, - FAL_NAPT_SYNMETRIC, - } fal_napt_mode_t; - - - typedef struct - { - a_uint32_t entry_id; - fal_ip4_addr_t pub_addr; - } fal_nat_pub_addr_t; - - - sw_error_t - fal_nat_add(a_uint32_t dev_id, fal_nat_entry_t * nat_entry); - - - sw_error_t - fal_nat_del(a_uint32_t dev_id, a_uint32_t del_mode, fal_nat_entry_t * nat_entry); - - - sw_error_t - fal_nat_get(a_uint32_t dev_id, a_uint32_t get_mode, fal_nat_entry_t * nat_entry); - - - sw_error_t - fal_nat_next(a_uint32_t dev_id, a_uint32_t get_mode, fal_nat_entry_t * nat_entry); - - - sw_error_t - fal_nat_counter_bind(a_uint32_t dev_id, a_uint32_t entry_id, a_uint32_t cnt_id, a_bool_t enable); - - - sw_error_t - fal_napt_add(a_uint32_t dev_id, fal_napt_entry_t * napt_entry); - - - sw_error_t - fal_napt_del(a_uint32_t dev_id, a_uint32_t del_mode, fal_napt_entry_t * napt_entry); - - - sw_error_t - fal_napt_get(a_uint32_t dev_id, a_uint32_t get_mode, fal_napt_entry_t * napt_entry); - - - sw_error_t - fal_napt_next(a_uint32_t dev_id, a_uint32_t next_mode, fal_napt_entry_t * napt_entry); - - - sw_error_t - fal_napt_counter_bind(a_uint32_t dev_id, a_uint32_t entry_id, a_uint32_t cnt_id, a_bool_t enable); - - - sw_error_t - fal_flow_add(a_uint32_t dev_id, fal_napt_entry_t * napt_entry); - - sw_error_t - fal_flow_cookie_set(a_uint32_t dev_id, fal_flow_cookie_t * flow_cookie); - - sw_error_t - fal_flow_rfs_set(a_uint32_t dev_id, a_uint8_t action, fal_flow_rfs_t * rfs); - - sw_error_t - fal_flow_del(a_uint32_t dev_id, a_uint32_t del_mode, fal_napt_entry_t * napt_entry); - - - sw_error_t - fal_flow_get(a_uint32_t dev_id, a_uint32_t get_mode, fal_napt_entry_t * napt_entry); - - - sw_error_t - fal_flow_next(a_uint32_t dev_id, a_uint32_t next_mode, fal_napt_entry_t * napt_entry); - - - sw_error_t - fal_flow_counter_bind(a_uint32_t dev_id, a_uint32_t entry_id, a_uint32_t cnt_id, a_bool_t enable); - - - sw_error_t - fal_nat_status_set(a_uint32_t dev_id, a_bool_t enable); - - - sw_error_t - fal_nat_status_get(a_uint32_t dev_id, a_bool_t * enable); - - - sw_error_t - fal_nat_hash_mode_set(a_uint32_t dev_id, a_uint32_t mode); - - - sw_error_t - fal_nat_hash_mode_get(a_uint32_t dev_id, a_uint32_t * mode); - - - sw_error_t - fal_napt_status_set(a_uint32_t dev_id, a_bool_t enable); - - - sw_error_t - fal_napt_status_get(a_uint32_t dev_id, a_bool_t * enable); - - - sw_error_t - fal_napt_mode_set(a_uint32_t dev_id, fal_napt_mode_t mode); - - - sw_error_t - fal_napt_mode_get(a_uint32_t dev_id, fal_napt_mode_t * mode); - - - sw_error_t - fal_napt_mode_get(a_uint32_t dev_id, fal_napt_mode_t * mode); - - - sw_error_t - fal_nat_prv_base_addr_set(a_uint32_t dev_id, fal_ip4_addr_t addr); - - - sw_error_t - fal_nat_prv_base_addr_get(a_uint32_t dev_id, fal_ip4_addr_t * addr); - - sw_error_t - fal_nat_prv_base_mask_set(a_uint32_t dev_id, fal_ip4_addr_t addr); - - sw_error_t - fal_nat_prv_base_mask_get(a_uint32_t dev_id, fal_ip4_addr_t * addr); - - - sw_error_t - fal_nat_prv_addr_mode_set(a_uint32_t dev_id, a_bool_t map_en); - - - sw_error_t - fal_nat_prv_addr_mode_get(a_uint32_t dev_id, a_bool_t * map_en); - - - sw_error_t - fal_nat_pub_addr_add(a_uint32_t dev_id, fal_nat_pub_addr_t * entry); - - - sw_error_t - fal_nat_pub_addr_del(a_uint32_t dev_id, a_uint32_t del_mode, fal_nat_pub_addr_t * entry); - - - sw_error_t - fal_nat_pub_addr_next(a_uint32_t dev_id, a_uint32_t next_mode, fal_nat_pub_addr_t * entry); - - - sw_error_t - fal_nat_unk_session_cmd_set(a_uint32_t dev_id, fal_fwd_cmd_t cmd); - - - sw_error_t - fal_nat_unk_session_cmd_get(a_uint32_t dev_id, fal_fwd_cmd_t * cmd); - - sw_error_t - fal_nat_global_set(a_uint32_t dev_id, a_bool_t enable, - a_bool_t sync_cnt_enable, a_uint32_t portbmp); - - -#ifdef __cplusplus -} -#endif /* __cplusplus */ -#endif /* _FAL_NAT_H_ */ - -/** - * @} - */ - diff --git a/feeds/ipq807x/qca-ssdk/src/include/fal/fal_policer.h b/feeds/ipq807x/qca-ssdk/src/include/fal/fal_policer.h deleted file mode 100755 index b54092c01..000000000 --- a/feeds/ipq807x/qca-ssdk/src/include/fal/fal_policer.h +++ /dev/null @@ -1,164 +0,0 @@ -/* - * Copyright (c) 2016-2018, 2021, The Linux Foundation. All rights reserved. - * Permission to use, copy, modify, and/or distribute this software for - * any purpose with or without fee is hereby granted, provided that the - * above copyright notice and this permission notice appear in all copies. - * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES - * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR - * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES - * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN - * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT - * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. - */ - - -/** - * @defgroup fal_policer FAL_POLICER - * @{ - */ -#ifndef _FAL_POLICER_H_ -#define _FAL_POLICER_H_ - -#ifdef __cplusplus -extern "C" { -#endif /* __cplusplus */ - -#include "sw.h" -#include "fal/fal_type.h" - -typedef struct -{ - a_bool_t meter_en; /* meter enable or disable */ - a_bool_t couple_en; /* two buckets coupling enable or disable*/ - a_uint32_t color_mode; /* color aware or color blind */ - a_uint32_t frame_type; /* frame type, bit0:unicast;bit1: unkown unicast;bit2:multicast;bit3: unknown multicast; bit4:broadcast */ - a_uint32_t meter_mode; - a_uint32_t meter_unit; /* 0:byte based; 1:packet based*/ - a_uint32_t cir; /* committed information rate */ - a_uint32_t cbs; /* committed burst size */ - a_uint32_t eir; /* excess information rate */ - a_uint32_t ebs; /* excess burst size */ -} fal_policer_config_t; - -typedef struct -{ - a_bool_t yellow_priority_en; /* yellow traffic internal priority change enable*/ - a_bool_t yellow_drop_priority_en; /* yellow traffic internal drop priority change enable*/ - a_bool_t yellow_pcp_en; /* yellow traffic pcp change enable*/ - a_bool_t yellow_dei_en; /* yellow traffic dei change enable*/ - a_uint32_t yellow_priority; /* yellow traffic internal priority value*/ - a_uint32_t yellow_drop_priority; /* yellow traffic internal drop priority value*/ - a_uint32_t yellow_pcp; /* yellow traffic pcp value*/ - a_uint32_t yellow_dei; /* yellow traffic dei value*/ - fal_fwd_cmd_t red_action; /* red traffic drop or forward*/ - a_bool_t red_priority_en; /* red traffic internal priority change enable*/ - a_bool_t red_drop_priority_en; /* red traffic internal drop priority change enable*/ - a_bool_t red_pcp_en; /* red traffic pcp change enable*/ - a_bool_t red_dei_en; /* red traffic dei change enable*/ - a_uint32_t red_priority; /* red traffic internal priority value*/ - a_uint32_t red_drop_priority; /* red traffic internal drop priority value*/ - a_uint32_t red_pcp; /* red traffic pcp value*/ - a_uint32_t red_dei; /* red traffic dei value*/ -}fal_policer_action_t; - -typedef struct -{ - a_uint32_t green_packet_counter; /*green packet counter */ - a_uint64_t green_byte_counter; /*green byte counter */ - a_uint32_t yellow_packet_counter; /*yellow packet counter */ - a_uint64_t yellow_byte_counter; /*yellow byte counter */ - a_uint32_t red_packet_counter; /*red packet counter */ - a_uint64_t red_byte_counter; /*red byte counter */ -} fal_policer_counter_t; - -typedef struct -{ - a_uint32_t policer_drop_packet_counter; /*drop packet counter by policer*/ - a_uint64_t policer_drop_byte_counter; /*drop byte counter by policer */ - a_uint32_t policer_forward_packet_counter; /*forward packet counter by policer*/ - a_uint64_t policer_forward_byte_counter; /*forward byte counter by policer*/ - a_uint32_t policer_bypass_packet_counter; /*bypass packet counter by policer*/ - a_uint64_t policer_bypass_byte_counter; /*bypass byte counter by policer */ -} fal_policer_global_counter_t; - -enum -{ - FUNC_ADPT_ACL_POLICER_COUNTER_GET = 0, - FUNC_ADPT_PORT_POLICER_COUNTER_GET, - FUNC_ADPT_PORT_COMPENSATION_BYTE_GET, - FUNC_ADPT_PORT_POLICER_ENTRY_GET, - FUNC_ADPT_PORT_POLICER_ENTRY_SET, - FUNC_ADPT_ACL_POLICER_ENTRY_GET, - FUNC_ADPT_ACL_POLICER_ENTRY_SET, - FUNC_ADPT_POLICER_TIME_SLOT_GET, - FUNC_ADPT_PORT_COMPENSATION_BYTE_SET, - FUNC_ADPT_POLICER_TIME_SLOT_SET, - FUNC_ADPT_POLICER_GLOBAL_COUNTER_GET, - FUNC_ADPT_POLICER_BYPASS_EN_SET, - FUNC_ADPT_POLICER_BYPASS_EN_GET, -}; - - -typedef enum { - FAL_FRAME_DROPPED = 0, -} fal_policer_frame_type_t; - -#ifndef IN_POLICER_MINI -sw_error_t -fal_port_policer_entry_set(a_uint32_t dev_id, fal_port_t port_id, - fal_policer_config_t *policer, fal_policer_action_t *action); - -sw_error_t -fal_port_policer_entry_get(a_uint32_t dev_id, fal_port_t port_id, - fal_policer_config_t *policer, fal_policer_action_t *atcion); - -sw_error_t -fal_acl_policer_entry_set(a_uint32_t dev_id, a_uint32_t index, - fal_policer_config_t *policer, fal_policer_action_t *action); - -sw_error_t -fal_acl_policer_entry_get(a_uint32_t dev_id, a_uint32_t index, - fal_policer_config_t *policer, fal_policer_action_t *action); - -sw_error_t -fal_port_policer_counter_get(a_uint32_t dev_id, fal_port_t port_id, - fal_policer_counter_t *counter); - -sw_error_t -fal_acl_policer_counter_get(a_uint32_t dev_id, a_uint32_t index, - fal_policer_counter_t *counter); - -sw_error_t -fal_port_policer_compensation_byte_get(a_uint32_t dev_id, fal_port_t port_id, - a_uint32_t *length); - -sw_error_t -fal_policer_timeslot_get(a_uint32_t dev_id, a_uint32_t *timeslot); - -sw_error_t -fal_policer_global_counter_get(a_uint32_t dev_id, - fal_policer_global_counter_t *counter); - -sw_error_t -fal_policer_bypass_en_get(a_uint32_t dev_id, fal_policer_frame_type_t frame_type, - a_bool_t *enable); -#endif - -sw_error_t -fal_port_policer_compensation_byte_set(a_uint32_t dev_id, fal_port_t port_id, - a_uint32_t length); - -sw_error_t -fal_policer_timeslot_set(a_uint32_t dev_id, a_uint32_t timeslot); - -sw_error_t -fal_policer_bypass_en_set(a_uint32_t dev_id, fal_policer_frame_type_t frame_type, - a_bool_t enable); -#ifdef __cplusplus -} -#endif /* __cplusplus */ -#endif /* _FAL_POLICER_H_ */ -/** - * @} - */ diff --git a/feeds/ipq807x/qca-ssdk/src/include/fal/fal_port_ctrl.h b/feeds/ipq807x/qca-ssdk/src/include/fal/fal_port_ctrl.h deleted file mode 100755 index ab7e38259..000000000 --- a/feeds/ipq807x/qca-ssdk/src/include/fal/fal_port_ctrl.h +++ /dev/null @@ -1,801 +0,0 @@ -/* - * Copyright (c) 2012, 2015-2019, The Linux Foundation. All rights reserved. - * Permission to use, copy, modify, and/or distribute this software for - * any purpose with or without fee is hereby granted, provided that the - * above copyright notice and this permission notice appear in all copies. - * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES - * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR - * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES - * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN - * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT - * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. - */ -/*qca808x_start*/ -/** - * @defgroup fal_port_ctrl FAL_PORT_CONTROL - * @{ - */ -#ifndef _FAL_PORTCTRL_H_ -#define _FAL_PORTCTRL_H_ - -#ifdef __cplusplus -extern "c" { -#endif - -#include "sw.h" -#include "fal/fal_type.h" - - typedef enum { - FAL_HALF_DUPLEX = 0, - FAL_FULL_DUPLEX, - FAL_DUPLEX_BUTT = 0xffff - } fal_port_duplex_t; - - typedef enum { - FAL_SPEED_10 = 10, - FAL_SPEED_100 = 100, - FAL_SPEED_1000 = 1000, - FAL_SPEED_2500 = 2500, - FAL_SPEED_5000 = 5000, - FAL_SPEED_10000 = 10000, - FAL_SPEED_BUTT = 0xffff, - } fal_port_speed_t; - - typedef enum { - FAL_CABLE_STATUS_NORMAL = 0, - FAL_CABLE_STATUS_SHORT = 1, - FAL_CABLE_STATUS_OPENED = 2, - FAL_CABLE_STATUS_INVALID = 3, - FAL_CABLE_STATUS_CROSSOVERA = 4, - FAL_CABLE_STATUS_CROSSOVERB = 5, - FAL_CABLE_STATUS_CROSSOVERC = 6, - FAL_CABLE_STATUS_CROSSOVERD = 7, - FAL_CABLE_STATUS_LOW_MISMATCH =8, - FAL_CABLE_STATUS_HIGH_MISMATCH =9, - FAL_CABLE_STATUS_BUTT = 0xffff, - } fal_cable_status_t; - -struct port_phy_status -{ - a_uint32_t link_status; - fal_port_speed_t speed; - fal_port_duplex_t duplex; - a_bool_t tx_flowctrl; - a_bool_t rx_flowctrl; -}; - -#define FAL_ENABLE 1 -#define FAL_DISABLE 0 -#define FAL_MAX_PORT_NUMBER 8 -#define FAL_DEFAULT_LOOPBACK_RATE 14 - -//phy autoneg adv -#define FAL_PHY_ADV_10T_HD 0x01 -#define FAL_PHY_ADV_10T_FD 0x02 -#define FAL_PHY_ADV_100TX_HD 0x04 -#define FAL_PHY_ADV_100TX_FD 0x08 -//#define FAL_PHY_ADV_1000T_HD 0x100 -#define FAL_PHY_ADV_1000T_FD 0x200 -#define FAL_PHY_ADV_1000BX_HD 0x400 -#define FAL_PHY_ADV_1000BX_FD 0x800 -#define FAL_PHY_ADV_2500T_FD 0x1000 -#define FAL_PHY_ADV_5000T_FD 0x2000 -#define FAL_PHY_ADV_10000T_FD 0x4000 -#define FAL_PHY_ADV_10G_R_FD 0x8000 - -#define FAL_DEFAULT_MAX_FRAME_SIZE 0x5ee - -#define FAL_PHY_ADV_FE_SPEED_ALL \ - (FAL_PHY_ADV_10T_HD | FAL_PHY_ADV_10T_FD | FAL_PHY_ADV_100TX_HD |\ - FAL_PHY_ADV_100TX_FD) - -#define FAL_PHY_ADV_GE_SPEED_ALL \ - (FAL_PHY_ADV_10T_HD | FAL_PHY_ADV_10T_FD | FAL_PHY_ADV_100TX_HD |\ - FAL_PHY_ADV_100TX_FD | FAL_PHY_ADV_1000T_FD) - -#define FAL_PHY_ADV_BX_SPEED_ALL \ - (FAL_PHY_ADV_1000BX_HD | FAL_PHY_ADV_1000BX_FD |FAL_PHY_ADV_10G_R_FD) - -#define FAL_PHY_ADV_XGE_SPEED_ALL \ - (FAL_PHY_ADV_2500T_FD | FAL_PHY_ADV_5000T_FD | FAL_PHY_ADV_10000T_FD) - -#define FAL_PHY_ADV_PAUSE 0x10 -#define FAL_PHY_ADV_ASY_PAUSE 0x20 -#define FAL_PHY_FE_ADV_ALL \ - (FAL_PHY_ADV_FE_SPEED_ALL | FAL_PHY_ADV_PAUSE | FAL_PHY_ADV_ASY_PAUSE) -#define FAL_PHY_GE_ADV_ALL \ - (FAL_PHY_ADV_GE_SPEED_ALL | FAL_PHY_ADV_PAUSE | FAL_PHY_ADV_ASY_PAUSE) - -#define FAL_PHY_COMBO_ADV_ALL \ - (FAL_PHY_ADV_BX_SPEED_ALL | FAL_PHY_ADV_GE_SPEED_ALL | FAL_PHY_ADV_XGE_SPEED_ALL|\ -FAL_PHY_ADV_PAUSE | FAL_PHY_ADV_ASY_PAUSE) - -//phy capablity -#define FAL_PHY_AUTONEG_CAPS 0x01 -#define FAL_PHY_100T2_HD_CAPS 0x02 -#define FAL_PHY_100T2_FD_CAPS 0x04 -#define FAL_PHY_10T_HD_CAPS 0x08 -#define FAL_PHY_10T_FD_CAPS 0x10 -#define FAL_PHY_100X_HD_CAPS 0x20 -#define FAL_PHY_100X_FD_CAPS 0x40 -#define FAL_PHY_100T4_CAPS 0x80 -//#define FAL_PHY_1000T_HD_CAPS 0x100 -#define FAL_PHY_1000T_FD_CAPS 0x200 -//#define FAL_PHY_1000X_HD_CAPS 0x400 -#define FAL_PHY_1000X_FD_CAPS 0x800 - -//phy partner capablity -#define FAL_PHY_PART_10T_HD 0x1 -#define FAL_PHY_PART_10T_FD 0x2 -#define FAL_PHY_PART_100TX_HD 0x4 -#define FAL_PHY_PART_100TX_FD 0x8 -//#define FAL_PHY_PART_1000T_HD 0x10 -#define FAL_PHY_PART_1000T_FD 0x20 -#define FAL_PHY_PART_2500T_FD 0x40 -#define FAL_PHY_PART_5000T_FD 0x80 -#define FAL_PHY_PART_10000T_FD 0x100 - -//phy interrupt flag -#define FAL_PHY_INTR_SPEED_CHANGE 0x1 -#define FAL_PHY_INTR_DUPLEX_CHANGE 0x2 -#define FAL_PHY_INTR_STATUS_UP_CHANGE 0x4 -#define FAL_PHY_INTR_STATUS_DOWN_CHANGE 0x8 -#define FAL_PHY_INTR_BX_FX_STATUS_UP_CHANGE 0x10 -#define FAL_PHY_INTR_BX_FX_STATUS_DOWN_CHANGE 0x20 -#define FAL_PHY_INTR_MEDIA_STATUS_CHANGE 0x40 -#define FAL_PHY_INTR_WOL_STATUS 0x80 -#define FAL_PHY_INTR_POE_STATUS 0x100 - -/* phy eee */ -#define FAL_PHY_EEE_10BASE_T 0x1 -#define FAL_PHY_EEE_100BASE_T 0x2 -#define FAL_PHY_EEE_1000BASE_T 0x4 -#define FAL_PHY_EEE_2500BASE_T 0x8 -#define FAL_PHY_EEE_5000BASE_T 0x10 -#define FAL_PHY_EEE_10000BASE_T 0x20 - typedef enum { - FAL_NO_HEADER_EN = 0, - FAL_ONLY_MANAGE_FRAME_EN, - FAL_ALL_TYPE_FRAME_EN - } fal_port_header_mode_t; - - typedef struct { - a_uint16_t pair_a_status; - a_uint16_t pair_b_status; - a_uint16_t pair_c_status; - a_uint16_t pair_d_status; - a_uint32_t pair_a_len; - a_uint32_t pair_b_len; - a_uint32_t pair_c_len; - a_uint32_t pair_d_len; - } fal_port_cdt_t; - -/*below is new add for malibu phy*/ - -/** Phy mdix mode */ - typedef enum { - PHY_MDIX_AUTO = 0, - /**< Auto MDI/MDIX */ - PHY_MDIX_MDI = 1, - /**< Fixed MDI */ - PHY_MDIX_MDIX = 2 - /**< Fixed MDIX */ - } fal_port_mdix_mode_t; - -/** Phy mdix status */ - typedef enum { - PHY_MDIX_STATUS_MDI = 0, - /**< Fixed MDI */ - PHY_MDIX_STATUS_MDIX = 1 - /**< Fixed MDIX */ - } fal_port_mdix_status_t; - -/** Phy master mode */ - typedef enum { - PHY_MASTER_MASTER = 0, - /**< Phy manual MASTER configuration */ - PHY_MASTER_SLAVE = 1, - /**< Phy manual SLAVE configuration */ - PHY_MASTER_AUTO = 2 - /**< Phy automatic MASTER/SLAVE configuration */ - } fal_port_master_t; - -/** Phy preferred medium type */ - typedef enum { - PHY_MEDIUM_COPPER = 0, - /**< Copper */ - PHY_MEDIUM_FIBER = 1, - /**< Fiber */ - - } fal_port_medium_t; - -/** Phy pages */ - typedef enum { - PHY_SGBX_PAGES = 0, - /**< sgbx pages */ - PHY_COPPER_PAGES = 1 - /**< copper pages */ - } fal_port_reg_pages_t; - -/** Phy preferred Fiber mode */ - typedef enum { - PHY_FIBER_100FX = 0, - /**< 100FX fiber mode */ - PHY_FIBER_1000BX = 1, - /**< 1000BX fiber mode */ - PHY_FIBER_10G_R = 2, - } fal_port_fiber_mode_t; - -/** Phy reset status */ - typedef enum { - PHY_RESET_DONE = 0, - /**< Phy reset done */ - PHY_RESET_BUSY = 1 - /**< Phy still in reset process */ - } fal_port_reset_status_t; - -/** Phy auto-negotiation status */ - typedef enum { - PHY_AUTO_NEG_STATUS_BUSY = 0, - /**< Phy still in auto-negotiation process */ - PHY_AUTO_NEG_STATUS_DONE = 1 - /**< Phy auto-negotiation done */ - } fal_port_auto_neg_status_t; - - -/** Phy interface mode */ - typedef enum { - PHY_PSGMII_BASET = 0, - /**< PSGMII mode */ - PHY_PSGMII_BX1000 = 1, - /**< PSGMII BX1000 mode */ - PHY_PSGMII_FX100 = 2, - /**< PSGMII FX100 mode */ - PHY_PSGMII_AMDET = 3, - /**< PSGMII Auto mode */ - PHY_SGMII_BASET = 4, - /**< SGMII mode */ - PORT_QSGMII, - /**= 2.5 G */ - a_uint32_t uart_config_bmp; /* refer to FAL_UART_START_POLARITY_HIGH_EN */ - a_bool_t reset_buf_en; /* reset TOD UART RX/TX buffer, self clearing */ - a_uint32_t buf_status_bmp; /* refer to FAL_UART_RX_BUFFER_DATA_PRESENT */ - a_uint16_t tx_buf_value; /* the uart data to transport */ - a_uint16_t rx_buf_value; /* the uart data received */ -} fal_ptp_tod_uart_t; - -enum { - FAL_ENHANCED_TS_ETH_TYPE_EN = 0, /* timestamp the matched ethernet type */ - FAL_ENHANCED_TS_DMAC_EN, /* timestamp the matched dst mac */ - FAL_ENHANCED_TS_RESV_DMAC_EN, /* timestamp the matched ptp dst mac */ - FAL_ENHANCED_TS_IPV4_L4_PROTO_EN, /* timestamp the matched layer 4 protocol id */ - FAL_ENHANCED_TS_IPV4_DIP_EN, /* timestamp the matched ipv4 dst addr */ - FAL_ENHANCED_TS_RESV_IPV4_DIP_EN, /* timestamp the matched ptp ipv4 dst addr */ - FAL_ENHANCED_TS_IPV6_NEXT_HEADER_EN, /* timestamp the matched ipv6 next header field */ - FAL_ENHANCED_TS_IPV6_DIP_EN, /* timestamp the matched ipv6 dst addr */ - FAL_ENHANCED_TS_RESV_IPV6_DIP_EN, /* timestamp the matched ptp ipv6 dst addr */ - FAL_ENHANCED_TS_UDP_DPORT_EN, /* timestamp the matched udp dport number */ - FAL_ENHANCED_TS_RESV_UDP_DPORT_EN, /* timestamp the matched udp dport number */ - FAL_ENHANCED_TS_Y1731_EN, /* timestamp the received Y1731 frame */ - FAL_ENHANCED_TS_Y1731_TIMESTAMP_INSERT_EN, /* enable inserting RX Y1731 timestamp */ - FAL_ENHANCED_TS_Y1731_MAC_EN /* TX direction check smac, RX direction check dmac */ -}; - -enum { - FAL_ENHANCED_TS_ETH_TYPE_STATUS = 0, /* the MAC type of received packet matches - the filter setting */ - FAL_ENHANCED_TS_DMAC_STATUS, /* the dest MAC of received packet matches - the filter setting */ - FAL_ENHANCED_TS_RESV_PRIM_DMAC_STATUS, /* the dest MAC of received packet matches - PTP primary multicast MAC address */ - FAL_ENHANCED_TS_RESV_PDELAY_DMAC_STATUS, /* the dest MAC of received packet matches - PTP peer delay multicast MAC address */ - FAL_ENHANCED_TS_IPV4_L4_PROTO_STATUS, /* the L4 layer protocol of received packet - matched the filter setting */ - FAL_ENHANCED_TS_IPV4_DIP_STATUS, /* the IPv4 dest address of received packet - matched the filter setting */ - FAL_ENHANCED_TS_RESV_IPV4_PRIM_DIP_STATUS, /* the IPv4 dest address of received packet - matches PTP primary multicast ipv4 addr */ - FAL_ENHANCED_TS_RESV_IPV4_PDELAY_DIP_STATUS,/* the IPv4 dest address of received packet - matches PTP peer delay multicast addr */ - FAL_ENHANCED_TS_IPV6_NEXT_HEADER_STATUS, /* the next header fielf of receviced packet - matches the filter setting */ - FAL_ENHANCED_TS_IPV6_DIP_STATUS, /* the ipv6 dest addr of received packet - matches the filter setting */ - FAL_ENHANCED_TS_RESV_IPV6_PRIM_DIP_STATUS, /* the ipv6 dest address of received packet - matches PTP primary multicast ipv6 addr */ - FAL_ENHANCED_TS_RESV_IPV6_PDELAY_DIP_STATUS,/* the ipv6 dest address of received packet - matches PTP peer delay multicast addr */ - FAL_ENHANCED_TS_UDP_DPORT_STATUS, /* the UDP dest port of received packet - matches the filter setting */ - FAL_ENHANCED_TS_RESV_UDP_DPORT_STATUS, /* the UDP dest port of received packet - matches udp dport of ptp event packet */ - FAL_ENHANCED_TS_Y1731_MATCH_STATUS /* the received frame is Y.1731 OAM frame */ -}; - -typedef struct { - a_bool_t filt_en; /* enable/disable filter feature */ - a_uint32_t enhance_ts_conf_bmp; /* refer to FAL_ENHANCED_TS_ETH_TYPE_EN */ - a_uint32_t eth_type; /* ethernet type value */ - fal_mac_addr_t dmac_addr; /* dest mac address */ - a_uint32_t ipv4_l4_proto; /* ipv4 layer 4 protocol field */ - fal_ip4_addr_t ipv4_dip; /* ipv4 dest ip addr */ - fal_ip6_addr_t ipv6_dip; /* ipv6 dest ip addr */ - a_uint32_t udp_dport; /* udp dest port */ - fal_mac_addr_t y1731_mac_addr; /* TX check smac, RX check dmac */ - a_uint32_t enhance_ts_status_bmp; /* refer to FAL_ENHANCED_TS_ETH_TYPE_STATUS */ - a_uint32_t enhance_ts_status_pre_bmp; /* TX NOT SUPPORT */ - a_uint32_t y1731_identity; /* save Y1731 identify value */ - a_uint32_t y1731_identity_pre; /* TX NOT SUPPORT */ - fal_ptp_time_t timestamp; /* save packet timestamp when matched */ - fal_ptp_time_t timestamp_pre; /* TX NOT SUPPORT */ -} fal_ptp_enhanced_ts_engine_t; - -typedef struct { - a_bool_t trigger_en; /* enable trigger or not */ - a_bool_t output_force_en; /* force trigger output a force value */ - int output_force_value; /* the forced value */ - int patten_select; /* trigger pattern: - 0 single rising edge; - 1 single falling edge; - 2 trigger pulse; - 3 trigger periodic waveform; - 4 toggle mode; - */ - int late_operation; /* if later, trigger immediately */ - int notify; /* report the completion of trigger */ - int trigger_effect; /* write 1 to generate a high pulse when trigger happen */ - fal_ptp_time_t tim; /* the trigger timestamp */ -} fal_ptp_trigger_conf_t; - -typedef struct { - int trigger_finished; /* trigger finished or not */ - int trigger_active; /* trigger is active or not */ - int trigger_error; /* trigger error status - 0 no error - 1 trigger time prior to current time - 2 initial value error for edge trigger - */ -} fal_ptp_trigger_status_t; - -typedef struct { - fal_ptp_trigger_conf_t trigger_conf; - fal_ptp_trigger_status_t trigger_status; -} fal_ptp_trigger_t; - -typedef struct { - int status_clear; /* clear event status register */ - int notify_event; /* notify event through interrupt */ - int single_multi_select; /* 1 for single or 0 for multi event capture */ - a_bool_t fall_edge_en; /* enable falling edge detection */ - a_bool_t rise_edge_en; /* enable rising edge detection */ -} fal_ptp_capture_conf_t; - -typedef struct { - int event_detected; /* event detected or not */ - int fall_rise_edge_detected; /* 0 for rising edge, 1 for falling edge detected */ - int single_multi_detected; /* 0 for single event, 1 for multi event detected */ - int event_missed_cnt; /* the number of events missed */ - fal_ptp_time_t tim; /* event timestamp */ -} fal_ptp_capture_status_t; - -typedef struct { - fal_ptp_capture_conf_t capture_conf; - fal_ptp_capture_status_t capture_status; -} fal_ptp_capture_t; - -enum { - FAL_PTP_INTR_EXPAND = 0,/* expand interrupt, FAL_PTP_INTR_TX_GTSE ~ FAL_PTP_INTR_CAP1 */ - FAL_PTP_INTR_RX, /* ptp pkt rx interrupt */ - FAL_PTP_INTR_TX, /* ptp pkt tx interrupt */ - FAL_PTP_INTR_TX_GTSE, /* gtse pkt tx interrupt */ - FAL_PTP_INTR_RX_GTSE, /* gtse pkt rx interrupt */ - FAL_PTP_INTR_TX_BUF, /* uart tod tx buffer half full interrupt */ - FAL_PTP_INTR_RX_BUF, /* uart tod rx buffer half full interrupt */ - FAL_PTP_INTR_PPS_OUT, /* PPS output interrupt */ - FAL_PTP_INTR_PPS_IN, /* PPS input interrupt */ - FAL_PTP_INTR_10MS, /* each 10ms interrupt */ - FAL_PTP_INTR_TRIG0, /* trigger0 interrupt */ - FAL_PTP_INTR_TRIG1, /* trigger1 interrupt */ - FAL_PTP_INTR_CAP0, /* capture0 interrupt */ - FAL_PTP_INTR_CAP1 /* capture1 interrupt */ -}; - -typedef struct { - a_uint32_t intr_mask; - a_uint32_t intr_status; -} fal_ptp_interrupt_t; - -sw_error_t -fal_ptp_config_set(a_uint32_t dev_id, a_uint32_t port_id, - fal_ptp_config_t *config); - -sw_error_t -fal_ptp_config_get(a_uint32_t dev_id, a_uint32_t port_id, - fal_ptp_config_t *config); - -sw_error_t -fal_ptp_reference_clock_set(a_uint32_t dev_id, a_uint32_t port_id, - fal_ptp_reference_clock_t ref_clock); - -sw_error_t -fal_ptp_reference_clock_get(a_uint32_t dev_id, a_uint32_t port_id, - fal_ptp_reference_clock_t *ref_clock); - -sw_error_t -fal_ptp_rx_timestamp_mode_set(a_uint32_t dev_id, - a_uint32_t port_id, fal_ptp_rx_timestamp_mode_t ts_mode); - -sw_error_t -fal_ptp_rx_timestamp_mode_get(a_uint32_t dev_id, - a_uint32_t port_id, fal_ptp_rx_timestamp_mode_t *ts_mode); - -sw_error_t -fal_ptp_timestamp_get(a_uint32_t dev_id, a_uint32_t port_id, - fal_ptp_direction_t direction, - fal_ptp_pkt_info_t *pkt_info, - fal_ptp_time_t *time); - -sw_error_t -fal_ptp_pkt_timestamp_set(a_uint32_t dev_id, a_uint32_t port_id, - fal_ptp_time_t *time); - -sw_error_t -fal_ptp_pkt_timestamp_get(a_uint32_t dev_id, a_uint32_t port_id, - fal_ptp_time_t *time); - -sw_error_t -fal_ptp_grandmaster_mode_set(a_uint32_t dev_id, a_uint32_t port_id, - fal_ptp_grandmaster_mode_t *gm_mode); - -sw_error_t -fal_ptp_grandmaster_mode_get(a_uint32_t dev_id, a_uint32_t port_id, - fal_ptp_grandmaster_mode_t *gm_mode); - -sw_error_t -fal_ptp_rtc_time_get(a_uint32_t dev_id, a_uint32_t port_id, - fal_ptp_time_t *time); - -sw_error_t -fal_ptp_rtc_time_set(a_uint32_t dev_id, a_uint32_t port_id, - fal_ptp_time_t *time); - -sw_error_t -fal_ptp_rtc_time_clear(a_uint32_t dev_id, a_uint32_t port_id); - -sw_error_t -fal_ptp_rtc_adjtime_set(a_uint32_t dev_id, a_uint32_t port_id, - fal_ptp_time_t *time); - -sw_error_t -fal_ptp_rtc_adjfreq_set(a_uint32_t dev_id, a_uint32_t port_id, - fal_ptp_time_t *time); - -sw_error_t -fal_ptp_rtc_adjfreq_get(a_uint32_t dev_id, a_uint32_t port_id, - fal_ptp_time_t *time); - -sw_error_t -fal_ptp_link_delay_set(a_uint32_t dev_id, a_uint32_t port_id, - fal_ptp_time_t *time); - -sw_error_t -fal_ptp_link_delay_get(a_uint32_t dev_id, a_uint32_t port_id, - fal_ptp_time_t *time); - -sw_error_t -fal_ptp_security_set(a_uint32_t dev_id, a_uint32_t port_id, - fal_ptp_security_t *sec); - -sw_error_t -fal_ptp_security_get(a_uint32_t dev_id, a_uint32_t port_id, - fal_ptp_security_t *sec); - -sw_error_t -fal_ptp_pps_signal_control_set(a_uint32_t dev_id, a_uint32_t port_id, - fal_ptp_pps_signal_control_t *sig_control); - -sw_error_t -fal_ptp_pps_signal_control_get(a_uint32_t dev_id, a_uint32_t port_id, - fal_ptp_pps_signal_control_t *sig_control); - -sw_error_t -fal_ptp_rx_crc_recalc_enable(a_uint32_t dev_id, a_uint32_t port_id, - a_bool_t status); - -sw_error_t -fal_ptp_rx_crc_recalc_status_get(a_uint32_t dev_id, a_uint32_t port_id, - a_bool_t *status); - -sw_error_t -fal_ptp_asym_correction_set(a_uint32_t dev_id, a_uint32_t port_id, - fal_ptp_asym_correction_t *asym_cf); - -sw_error_t -fal_ptp_asym_correction_get(a_uint32_t dev_id, a_uint32_t port_id, - fal_ptp_asym_correction_t* asym_cf); - -sw_error_t -fal_ptp_output_waveform_set(a_uint32_t dev_id, a_uint32_t port_id, - fal_ptp_output_waveform_t *waveform); - -sw_error_t -fal_ptp_output_waveform_get(a_uint32_t dev_id, a_uint32_t port_id, - fal_ptp_output_waveform_t *waveform); - -sw_error_t -fal_ptp_rtc_time_snapshot_enable(a_uint32_t dev_id, a_uint32_t port_id, - a_bool_t status); - -sw_error_t -fal_ptp_rtc_time_snapshot_status_get(a_uint32_t dev_id, a_uint32_t port_id, - a_bool_t *status); - -sw_error_t -fal_ptp_increment_sync_from_clock_enable(a_uint32_t dev_id, - a_uint32_t port_id, a_bool_t status); - -sw_error_t -fal_ptp_increment_sync_from_clock_status_get(a_uint32_t dev_id, - a_uint32_t port_id, a_bool_t *status); - -sw_error_t -fal_ptp_tod_uart_set(a_uint32_t dev_id, a_uint32_t port_id, - fal_ptp_tod_uart_t *tod_uart); - -sw_error_t -fal_ptp_tod_uart_get(a_uint32_t dev_id, a_uint32_t port_id, - fal_ptp_tod_uart_t *tod_uart); - -sw_error_t -fal_ptp_enhanced_timestamp_engine_set(a_uint32_t dev_id, - a_uint32_t port_id, fal_ptp_direction_t direction, - fal_ptp_enhanced_ts_engine_t *ts_engine); - -sw_error_t -fal_ptp_enhanced_timestamp_engine_get(a_uint32_t dev_id, - a_uint32_t port_id, fal_ptp_direction_t direction, - fal_ptp_enhanced_ts_engine_t *ts_engine); - -sw_error_t -fal_ptp_trigger_set(a_uint32_t dev_id, a_uint32_t port_id, - a_uint32_t trigger_id, fal_ptp_trigger_t *triger); - -sw_error_t -fal_ptp_trigger_get(a_uint32_t dev_id, a_uint32_t port_id, - a_uint32_t trigger_id, fal_ptp_trigger_t *triger); - -sw_error_t -fal_ptp_capture_set(a_uint32_t dev_id, a_uint32_t port_id, - a_uint32_t capture_id, fal_ptp_capture_t *capture); - -sw_error_t -fal_ptp_capture_get(a_uint32_t dev_id, a_uint32_t port_id, - a_uint32_t capture_id, fal_ptp_capture_t *capture); - -sw_error_t -fal_ptp_interrupt_set(a_uint32_t dev_id, a_uint32_t port_id, - fal_ptp_interrupt_t *interrupt); - -sw_error_t -fal_ptp_interrupt_get(a_uint32_t dev_id, a_uint32_t port_id, - fal_ptp_interrupt_t *interrupt); - -#ifdef __cplusplus -} -#endif /* __cplusplus */ -#endif /* _FAL_PTP_H_ */ -/** - * @} - */ diff --git a/feeds/ipq807x/qca-ssdk/src/include/fal/fal_qm.h b/feeds/ipq807x/qca-ssdk/src/include/fal/fal_qm.h deleted file mode 100755 index a15f0b5f8..000000000 --- a/feeds/ipq807x/qca-ssdk/src/include/fal/fal_qm.h +++ /dev/null @@ -1,344 +0,0 @@ -/* - * Copyright (c) 2016-2018, The Linux Foundation. All rights reserved. - * Permission to use, copy, modify, and/or distribute this software for - * any purpose with or without fee is hereby granted, provided that the - * above copyright notice and this permission notice appear in all copies. - * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES - * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR - * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES - * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN - * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT - * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. - */ - - -/** - * @defgroup fal_qos FAL_QM - * @{ - */ -#ifndef _FAL_QM_H_ -#define _FAL_QM_H_ - -#ifdef __cplusplus -extern "C" { -#endif /* __cplusplus */ - -#include "sw.h" -#include "fal/fal_type.h" - -typedef enum { - FAL_AC_QUEUE = 0, - FAL_AC_GROUP -} fal_ac_type_t; - -typedef struct { - fal_ac_type_t type; - a_uint32_t obj_id; -} fal_ac_obj_t; - -typedef struct { - a_bool_t ac_en; /* 0 for disable and 1 for enable*/ - a_bool_t ac_fc_en; /* ac for flow control packets */ -} fal_ac_ctrl_t; - -typedef struct { - a_uint16_t prealloc_buffer; /* guareented buffer number */ - a_uint16_t total_buffer; /* total buffer number */ -} fal_ac_group_buffer_t; - -typedef struct { - a_bool_t color_enable; /* 1 for color aware and 0 for color-blind */ - a_bool_t wred_enable; /* 1 for wred and 0 for tail drop */ - a_uint16_t green_max; - a_uint16_t green_min_off; /*gap between green max and green min*/ - a_uint16_t yel_max_off; /*gap between green max and yel max*/ - a_uint16_t yel_min_off; /*gap between green max and yel min*/ - a_uint16_t red_max_off; /*gap between green max and red max*/ - a_uint16_t red_min_off; /*gap between green max and red min*/ - a_uint16_t green_resume_off; /* green resume offset */ - a_uint16_t yel_resume_off; /* yellow resume offset */ - a_uint16_t red_resume_off; /* red resume offset */ -} fal_ac_static_threshold_t; - -typedef struct { - a_bool_t color_enable; /* 1 for color aware and 0 for color-blind */ - a_bool_t wred_enable; /* 1 for wred and 0 for tail drop */ - a_uint8_t shared_weight; /* weight in the shared group */ - a_uint16_t green_min_off; /*gap between green max and green min*/ - a_uint16_t yel_max_off; /*gap between green max and yel max*/ - a_uint16_t yel_min_off; /*gap between green max and yel min*/ - a_uint16_t red_max_off; /*gap between green max and red max*/ - a_uint16_t red_min_off; /*gap between green max and red min*/ - a_uint16_t green_resume_off; /* green resume offset */ - a_uint16_t yel_resume_off; /* yellow resume offset */ - a_uint16_t red_resume_off; /* red resume offset */ - a_uint16_t ceiling; /*shared ceiling*/ -} fal_ac_dynamic_threshold_t; - -typedef struct { - a_uint8_t src_profile; /* queue source profile */ - a_bool_t service_code_en; - a_uint16_t service_code; - a_bool_t cpu_code_en; - a_uint16_t cpu_code; - fal_port_t dst_port; /* destination physical or VP port */ -} fal_ucast_queue_dest_t; - -#define FAL_QM_DROP_ITEMS 6 -typedef struct { - a_uint32_t tx_packets; - a_uint64_t tx_bytes; - a_uint32_t pending_buff_num; - a_uint32_t drop_packets[FAL_QM_DROP_ITEMS]; - a_uint64_t drop_bytes[FAL_QM_DROP_ITEMS]; -} fal_queue_stats_t; - -enum { - FUNC_UCAST_HASH_MAP_SET = 0, - FUNC_AC_DYNAMIC_THRESHOLD_GET, - FUNC_UCAST_QUEUE_BASE_PROFILE_GET, - FUNC_PORT_MCAST_PRIORITY_CLASS_GET, - FUNC_AC_DYNAMIC_THRESHOLD_SET, - FUNC_AC_PREALLOC_BUFFER_SET, - FUNC_UCAST_DEFAULT_HASH_GET, - FUNC_UCAST_DEFAULT_HASH_SET, - FUNC_AC_QUEUE_GROUP_GET, - FUNC_AC_CTRL_GET, - FUNC_AC_PREALLOC_BUFFER_GET, - FUNC_PORT_MCAST_PRIORITY_CLASS_SET, - FUNC_UCAST_HASH_MAP_GET, - FUNC_AC_STATIC_THRESHOLD_SET, - FUNC_AC_QUEUE_GROUP_SET, - FUNC_AC_GROUP_BUFFER_GET, - FUNC_MCAST_CPU_CODE_CLASS_GET, - FUNC_AC_CTRL_SET, - FUNC_UCAST_PRIORITY_CLASS_GET, - FUNC_QUEUE_FLUSH, - FUNC_MCAST_CPU_CODE_CLASS_SET, - FUNC_UCAST_PRIORITY_CLASS_SET, - FUNC_AC_STATIC_THRESHOLD_GET, - FUNC_UCAST_QUEUE_BASE_PROFILE_SET, - FUNC_AC_GROUP_BUFFER_SET, - FUNC_QUEUE_COUNTER_CLEANUP, - FUNC_QUEUE_COUNTER_GET, - FUNC_QUEUE_COUNTER_CTRL_GET, - FUNC_QUEUE_COUNTER_CTRL_SET, - FUNC_QM_ENQUEUE_CTRL_GET, - FUNC_QM_ENQUEUE_CTRL_SET, - FUNC_QM_PORT_SRCPROFILE_GET, - FUNC_QM_PORT_SRCPROFILE_SET, -}; - -sw_error_t -fal_ac_ctrl_set( - a_uint32_t dev_id, - fal_ac_obj_t *obj, - fal_ac_ctrl_t *cfg); - -#ifndef IN_QM_MINI -sw_error_t -fal_ac_ctrl_get( - a_uint32_t dev_id, - fal_ac_obj_t *obj, - fal_ac_ctrl_t *cfg); -#endif - -sw_error_t -fal_ac_prealloc_buffer_set( - a_uint32_t dev_id, - fal_ac_obj_t *obj, - a_uint16_t num); - -#ifndef IN_QM_MINI -sw_error_t -fal_ac_prealloc_buffer_get( - a_uint32_t dev_id, - fal_ac_obj_t *obj, - a_uint16_t *num); -#endif - -sw_error_t -fal_ac_queue_group_set( - a_uint32_t dev_id, - a_uint32_t queue_id, - a_uint8_t group_id); - -#ifndef IN_QM_MINI -sw_error_t -fal_ac_queue_group_get( - a_uint32_t dev_id, - a_uint32_t queue_id, - a_uint8_t *group_id); -#endif - -sw_error_t -fal_ac_static_threshold_set( - a_uint32_t dev_id, - fal_ac_obj_t *obj, - fal_ac_static_threshold_t *cfg); - -#ifndef IN_QM_MINI -sw_error_t -fal_ac_static_threshold_get( - a_uint32_t dev_id, - fal_ac_obj_t *obj, - fal_ac_static_threshold_t *cfg); -#endif - -sw_error_t -fal_ac_dynamic_threshold_set( - a_uint32_t dev_id, - a_uint32_t queue_id, - fal_ac_dynamic_threshold_t *cfg); - -#ifndef IN_QM_MINI -sw_error_t -fal_ac_dynamic_threshold_get( - a_uint32_t dev_id, - a_uint32_t queue_id, - fal_ac_dynamic_threshold_t *cfg); -#endif - -sw_error_t -fal_ac_group_buffer_set( - a_uint32_t dev_id, - a_uint8_t group_id, - fal_ac_group_buffer_t *cfg); - -#ifndef IN_QM_MINI -sw_error_t -fal_ac_group_buffer_get( - a_uint32_t dev_id, - a_uint8_t group_id, - fal_ac_group_buffer_t *cfg); -#endif - -sw_error_t -fal_ucast_queue_base_profile_set( - a_uint32_t dev_id, - fal_ucast_queue_dest_t *queue_dest, - a_uint32_t queue_base, a_uint8_t profile); - -#ifndef IN_QM_MINI -sw_error_t -fal_ucast_queue_base_profile_get( - a_uint32_t dev_id, - fal_ucast_queue_dest_t *queue_dest, - a_uint32_t *queue_base, a_uint8_t *profile); - -sw_error_t -fal_ucast_priority_class_set( - a_uint32_t dev_id, - a_uint8_t profile, - a_uint8_t priority, - a_uint8_t class); - -sw_error_t -fal_ucast_priority_class_get( - a_uint32_t dev_id, - a_uint8_t profile, - a_uint8_t priority, - a_uint8_t *class); - -sw_error_t -fal_ucast_hash_map_set( - a_uint32_t dev_id, - a_uint8_t profile, - a_uint8_t rss_hash, - a_int8_t queue_hash); - -sw_error_t -fal_ucast_hash_map_get( - a_uint32_t dev_id, - a_uint8_t profile, - a_uint8_t rss_hash, - a_int8_t *queue_hash); - -sw_error_t -fal_mcast_cpu_code_class_set( - a_uint32_t dev_id, - a_uint8_t cpu_code, - a_uint8_t queue_class); - -sw_error_t -fal_mcast_cpu_code_class_get( - a_uint32_t dev_id, - a_uint8_t cpu_code, - a_uint8_t *queue_class); - -sw_error_t -fal_port_mcast_priority_class_set( - a_uint32_t dev_id, - fal_port_t port, - a_uint8_t priority, - a_uint8_t queue_class); - -sw_error_t -fal_port_mcast_priority_class_get( - a_uint32_t dev_id, - fal_port_t port, - a_uint8_t priority, - a_uint8_t *queue_class); - -#endif -sw_error_t -fal_queue_flush( - a_uint32_t dev_id, - fal_port_t port, - a_uint16_t queue_id); - -#ifndef IN_QM_MINI -sw_error_t -fal_ucast_default_hash_set( - a_uint32_t dev_id, - a_uint8_t hash_value); - -sw_error_t -fal_ucast_default_hash_get( - a_uint32_t dev_id, - a_uint8_t *hash_value); - -sw_error_t -fal_queue_counter_ctrl_set(a_uint32_t dev_id, a_bool_t cnt_en); - -sw_error_t -fal_queue_counter_ctrl_get(a_uint32_t dev_id, a_bool_t *cnt_en); - -sw_error_t -fal_queue_counter_get(a_uint32_t dev_id, a_uint32_t queue_id, fal_queue_stats_t *info); - -sw_error_t -fal_queue_counter_cleanup(a_uint32_t dev_id, a_uint32_t queue_id); -#endif - -sw_error_t -fal_qm_enqueue_ctrl_set(a_uint32_t dev_id, a_uint32_t queue_id, a_bool_t enable); - -#ifndef IN_QM_MINI -sw_error_t -fal_qm_enqueue_ctrl_get(a_uint32_t dev_id, a_uint32_t queue_id, a_bool_t *enable); - -sw_error_t -fal_qm_port_source_profile_set( - a_uint32_t dev_id, - fal_port_t port, - a_uint32_t src_profile); - -sw_error_t -fal_qm_port_source_profile_get( - a_uint32_t dev_id, - fal_port_t port, - a_uint32_t *src_profile); - -#endif - - -#ifdef __cplusplus -} -#endif /* __cplusplus */ -#endif /* _PORT_QM_H_ */ -/** - * @} - */ - diff --git a/feeds/ipq807x/qca-ssdk/src/include/fal/fal_qos.h b/feeds/ipq807x/qca-ssdk/src/include/fal/fal_qos.h deleted file mode 100644 index 30c894e1b..000000000 --- a/feeds/ipq807x/qca-ssdk/src/include/fal/fal_qos.h +++ /dev/null @@ -1,442 +0,0 @@ -/* - * Copyright (c) 2012, 2016-2018, The Linux Foundation. All rights reserved. - * Permission to use, copy, modify, and/or distribute this software for - * any purpose with or without fee is hereby granted, provided that the - * above copyright notice and this permission notice appear in all copies. - * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES - * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR - * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES - * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN - * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT - * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. - */ - - -/** - * @defgroup fal_qos FAL_QOS - * @{ - */ -#ifndef _FAL_QOS_H_ -#define _FAL_QOS_H_ - -#ifdef __cplusplus -extern "C" { -#endif /* __cplusplus */ - -#include "sw.h" -#include "fal/fal_type.h" - - /** - @brief This enum defines traffic scheduling mode. - */ - typedef enum { - FAL_SCH_SP_MODE = 0, /**< strict priority scheduling mode */ - FAL_SCH_WRR_MODE, /**< weight round robin scheduling mode*/ - FAL_SCH_MIX_MODE, /**< sp and wrr mixed scheduling mode */ - FAL_SCH_MIX_PLUS_MODE, /**< sp and wrr mixed plus scheduling mode */ - FAL_SCH_MODE_BUTT - } - fal_sch_mode_t; - - /** - @brief This enum defines qos assignment mode. - */ - typedef enum - { - FAL_QOS_DA_MODE = 0, /**< qos assignment based on destination mac address*/ - FAL_QOS_UP_MODE, /**< qos assignment based on 802.1p field in vlan tag*/ - FAL_QOS_DSCP_MODE, /**< qos assignment based on dscp field in ip header */ - FAL_QOS_PORT_MODE, /**< qos assignment based on port */ - FAL_QOS_FLOW_MODE, /**< qos assignment based on flow */ - FAL_QOS_MODE_BUTT - } fal_qos_mode_t; - -typedef struct { - a_uint8_t pcp_group; /* 0: group 0 1: group 1 */ - a_uint8_t dscp_group; - a_uint8_t flow_group; -} fal_qos_group_t; - -typedef struct { - a_uint8_t pcp_pri; - a_uint8_t dscp_pri; - a_int8_t preheader_pri; - a_uint8_t flow_pri; - a_uint8_t acl_pri; - a_uint8_t post_acl_pri; - a_bool_t pcp_pri_force; - a_bool_t dscp_pri_force; -} fal_qos_pri_precedence_t; - -typedef struct { - a_bool_t pcp_change_en; - a_bool_t dei_chage_en; - a_bool_t dscp_change_en; -} fal_qos_remark_enable_t; - -typedef struct { - a_uint8_t internal_pcp; - a_uint8_t internal_dei; - a_uint8_t internal_pri; - a_uint8_t internal_dscp; - a_uint8_t internal_dp; - a_uint8_t dscp_mask; - a_bool_t dscp_en; - a_bool_t pcp_en; - a_bool_t dei_en; - a_bool_t pri_en; - a_bool_t dp_en; - a_uint8_t qos_prec; /* resolution precedence */ -} fal_qos_cosmap_t; - -typedef enum { - FAL_DRR_IPG_PREAMBLE_FRAME_CRC = 0, /* IPG + Preamble + Frame + CRC */ - FAL_DRR_FRAME_CRC, /* Frame + CRC */ - FAL_DRR_L3_EXCLUDE_CRC /* after Ethernet type excude CRC*/ -} fal_qos_drr_frame_mode_t; - -typedef struct { - a_uint8_t sp_id; /* SP id L0:0~63 L1:0~7 */ - a_uint8_t e_pri; /*SP priority for E path:0~7 low to high */ - a_uint8_t c_pri; /* SP priority for C path: 0~7 low to high */ - a_uint8_t c_drr_id; /*C DRR ID L0:0~159 L1:0~35*/ - a_uint8_t e_drr_id; /*E DRR ID L0:0~159 L1:0~35*/ - a_uint16_t e_drr_wt; /* DRR weight in E DRR: 0~1023 */ - a_uint16_t c_drr_wt; /* DRR weight in C DRR: 0~1023 */ - a_uint8_t c_drr_unit; /* 0:byte based; 1:packet based */ - a_uint8_t e_drr_unit; /* 0:byte based; 1:packet based */ - fal_qos_drr_frame_mode_t drr_frame_mode; -} fal_qos_scheduler_cfg_t; - -typedef struct { - a_uint32_t en_scheduler_port_bmp; /* port bitmap of en-scheduler */ - a_uint32_t en_scheduler_port; /* port of en-scheduler */ - a_uint32_t de_scheduler_port; /* port of de-shceduler */ -} fal_port_scheduler_cfg_t; - -typedef enum { - FAL_QUEUE_SCHEDULER_LEVEL0 = 0, - FAL_QUEUE_SCHEDULER_LEVEL1, -} fal_queue_scheduler_level_t; - - -typedef struct { - a_uint32_t bmp[10]; -} fal_queue_bmp_t; - -enum { - FUNC_QOS_PORT_PRI_SET = 0, - FUNC_QOS_PORT_PRI_GET, - FUNC_QOS_COSMAP_PCP_GET, - FUNC_QUEUE_SCHEDULER_SET, - FUNC_QUEUE_SCHEDULER_GET, - FUNC_PORT_QUEUES_GET, - FUNC_QOS_COSMAP_PCP_SET, - FUNC_QOS_PORT_REMARK_GET, - FUNC_QOS_COSMAP_DSCP_GET, - FUNC_QOS_COSMAP_FLOW_SET, - FUNC_QOS_PORT_GROUP_SET, - FUNC_RING_QUEUE_MAP_SET, - FUNC_QOS_COSMAP_DSCP_SET, - FUNC_QOS_PORT_REMARK_SET, - FUNC_QOS_COSMAP_FLOW_GET, - FUNC_QOS_PORT_GROUP_GET, - FUNC_RING_QUEUE_MAP_GET, - FUNC_TDM_TICK_NUM_SET, - FUNC_TDM_TICK_NUM_GET, - FUNC_PORT_SCHEDULER_CFG_SET, - FUNC_PORT_SCHEDULER_CFG_GET, - FUNC_SCHEDULER_DEQUEUE_CTRL_GET, - FUNC_SCHEDULER_DEQUEUE_CTRL_SET, - FUNC_QOS_PORT_MODE_PRI_GET, - FUNC_QOS_PORT_MODE_PRI_SET, - FUNC_QOS_PORT_SCHEDULER_CFG_RESET, - FUNC_QOS_PORT_SCHEDULER_RESOURCE_GET, -}; - -typedef struct { - a_uint16_t ucastq_start; - a_uint16_t ucastq_num; - a_uint16_t mcastq_start; - a_uint16_t mcastq_num; - a_uint16_t l0sp_start; - a_uint16_t l0sp_num; - a_uint16_t l0cdrr_start; - a_uint16_t l0cdrr_num; - a_uint16_t l0edrr_start; - a_uint16_t l0edrr_num; - a_uint16_t l1sp_start; - a_uint16_t l1sp_num; - a_uint16_t l1cdrr_start; - a_uint16_t l1cdrr_num; - a_uint16_t l1edrr_start; - a_uint16_t l1edrr_num; -} fal_portscheduler_resource_t; - -#define FAL_DOT1P_MIN 0 -#define FAL_DOT1P_MAX 7 - -#define FAL_DSCP_MIN 0 -#define FAL_DSCP_MAX 63 - -#ifndef IN_QOS_MINI - sw_error_t - fal_qos_sch_mode_set(a_uint32_t dev_id, - fal_sch_mode_t mode, const a_uint32_t weight[]); - - - sw_error_t - fal_qos_sch_mode_get(a_uint32_t dev_id, - fal_sch_mode_t * mode, a_uint32_t weight[]); - - - sw_error_t - fal_qos_queue_tx_buf_status_set(a_uint32_t dev_id, fal_port_t port_id, - a_bool_t enable); - - sw_error_t - fal_qos_queue_tx_buf_status_get(a_uint32_t dev_id, fal_port_t port_id, - a_bool_t * enable); - - - sw_error_t - fal_qos_queue_tx_buf_nr_get(a_uint32_t dev_id, fal_port_t port_id, - fal_queue_t queue_id, a_uint32_t * number); - - - sw_error_t - fal_qos_port_tx_buf_status_set(a_uint32_t dev_id, fal_port_t port_id, - a_bool_t enable); - - - sw_error_t - fal_qos_port_tx_buf_status_get(a_uint32_t dev_id, fal_port_t port_id, - a_bool_t * enable); - - - - sw_error_t - fal_qos_port_red_en_get(a_uint32_t dev_id, fal_port_t port_id, - a_bool_t * enable); - - - - - - sw_error_t - fal_qos_port_tx_buf_nr_get(a_uint32_t dev_id, fal_port_t port_id, - a_uint32_t * number); - - sw_error_t - fal_qos_port_rx_buf_nr_get(a_uint32_t dev_id, fal_port_t port_id, - a_uint32_t * number); - - sw_error_t - fal_cosmap_up_queue_set(a_uint32_t dev_id, a_uint32_t up, - fal_queue_t queue); - - - sw_error_t - fal_cosmap_up_queue_get(a_uint32_t dev_id, a_uint32_t up, - fal_queue_t * queue); - - - sw_error_t - fal_cosmap_dscp_queue_set(a_uint32_t dev_id, a_uint32_t dscp, - fal_queue_t queue); - - - sw_error_t - fal_cosmap_dscp_queue_get(a_uint32_t dev_id, a_uint32_t dscp, - fal_queue_t * queue); -#endif - sw_error_t - fal_qos_port_rx_buf_nr_set(a_uint32_t dev_id, fal_port_t port_id, - a_uint32_t * number); - sw_error_t - fal_qos_port_red_en_set(a_uint32_t dev_id, fal_port_t port_id, - a_bool_t enable); - sw_error_t - fal_qos_port_mode_set(a_uint32_t dev_id, fal_port_t port_id, - fal_qos_mode_t mode, a_bool_t enable); - - sw_error_t - fal_qos_port_tx_buf_nr_set(a_uint32_t dev_id, fal_port_t port_id, - a_uint32_t * number); - - - sw_error_t - fal_qos_queue_tx_buf_nr_set(a_uint32_t dev_id, fal_port_t port_id, - fal_queue_t queue_id, a_uint32_t * number); - -#ifndef IN_QOS_MINI -sw_error_t - fal_qos_port_mode_get(a_uint32_t dev_id, fal_port_t port_id, - fal_qos_mode_t mode, a_bool_t * enable); - - sw_error_t - fal_qos_port_mode_pri_set(a_uint32_t dev_id, fal_port_t port_id, - fal_qos_mode_t mode, a_uint32_t pri); - - - sw_error_t - fal_qos_port_mode_pri_get(a_uint32_t dev_id, fal_port_t port_id, - fal_qos_mode_t mode, a_uint32_t * pri); - - - sw_error_t - fal_qos_port_default_up_set(a_uint32_t dev_id, fal_port_t port_id, - a_uint32_t up); - - - sw_error_t - fal_qos_port_default_up_get(a_uint32_t dev_id, fal_port_t port_id, - a_uint32_t * up); - - sw_error_t - fal_qos_port_sch_mode_set(a_uint32_t dev_id, a_uint32_t port_id, - fal_sch_mode_t mode, const a_uint32_t weight[]); - - sw_error_t - fal_qos_port_sch_mode_get(a_uint32_t dev_id, a_uint32_t port_id, - fal_sch_mode_t * mode, a_uint32_t weight[]); - - sw_error_t - fal_qos_port_default_spri_set(a_uint32_t dev_id, fal_port_t port_id, - a_uint32_t spri); - - sw_error_t - fal_qos_port_default_spri_get(a_uint32_t dev_id, fal_port_t port_id, - a_uint32_t * spri); - - sw_error_t - fal_qos_port_default_cpri_set(a_uint32_t dev_id, fal_port_t port_id, - a_uint32_t cpri); - - sw_error_t - fal_qos_port_default_cpri_get(a_uint32_t dev_id, fal_port_t port_id, - a_uint32_t * cpri); - - sw_error_t - fal_qos_port_force_spri_status_set(a_uint32_t dev_id, fal_port_t port_id, - a_bool_t enable); - - sw_error_t - fal_qos_port_force_spri_status_get(a_uint32_t dev_id, fal_port_t port_id, - a_bool_t* enable); - - sw_error_t - fal_qos_port_force_cpri_status_set(a_uint32_t dev_id, fal_port_t port_id, - a_bool_t enable); - - sw_error_t - fal_qos_port_force_cpri_status_get(a_uint32_t dev_id, fal_port_t port_id, - a_bool_t* enable); - - sw_error_t - fal_qos_queue_remark_table_set(a_uint32_t dev_id, fal_port_t port_id, - fal_queue_t queue_id, a_uint32_t tbl_id, a_bool_t enable); - - - sw_error_t - fal_qos_queue_remark_table_get(a_uint32_t dev_id, fal_port_t port_id, - fal_queue_t queue_id, a_uint32_t * tbl_id, a_bool_t * enable); -#endif - -sw_error_t -fal_qos_port_group_set(a_uint32_t dev_id, fal_port_t port_id, - fal_qos_group_t *group); - -sw_error_t -fal_qos_port_group_get(a_uint32_t dev_id, fal_port_t port_id, - fal_qos_group_t *group); - -sw_error_t -fal_qos_port_pri_precedence_set(a_uint32_t dev_id, fal_port_t port_id, - fal_qos_pri_precedence_t *pri); - -sw_error_t -fal_qos_port_pri_precedence_get(a_uint32_t dev_id, fal_port_t port_id, - fal_qos_pri_precedence_t *pri); - -sw_error_t -fal_qos_port_remark_set(a_uint32_t dev_id, fal_port_t port_id, - fal_qos_remark_enable_t *remark); - -sw_error_t -fal_qos_port_remark_get(a_uint32_t dev_id, fal_port_t port_id, - fal_qos_remark_enable_t *remark); - -sw_error_t -fal_qos_cosmap_pcp_set(a_uint32_t dev_id, a_uint8_t group_id, - a_uint8_t pcp, fal_qos_cosmap_t *cosmap); - -sw_error_t -fal_qos_cosmap_pcp_get(a_uint32_t dev_id, a_uint8_t group_id, - a_uint8_t pcp, fal_qos_cosmap_t *cosmap); - -sw_error_t -fal_qos_cosmap_flow_set(a_uint32_t dev_id, a_uint8_t group_id, - a_uint16_t flow, fal_qos_cosmap_t *cosmap); - -sw_error_t -fal_qos_cosmap_flow_get(a_uint32_t dev_id, a_uint8_t group_id, - a_uint16_t flow, fal_qos_cosmap_t *cosmap); - -sw_error_t -fal_qos_cosmap_dscp_set(a_uint32_t dev_id, a_uint8_t group_id, - a_uint8_t dscp, fal_qos_cosmap_t *cosmap); - -sw_error_t -fal_qos_cosmap_dscp_get(a_uint32_t dev_id, a_uint8_t group_id, - a_uint8_t dscp, fal_qos_cosmap_t *cosmap); - - -sw_error_t -fal_queue_scheduler_set(a_uint32_t dev_id, - a_uint32_t node_id, fal_queue_scheduler_level_t level, - fal_port_t port_id, - fal_qos_scheduler_cfg_t *scheduler_cfg); - -sw_error_t -fal_queue_scheduler_get(a_uint32_t dev_id, - a_uint32_t node_id, fal_queue_scheduler_level_t level, - fal_port_t *port_id, - fal_qos_scheduler_cfg_t *scheduler_cfg); - -sw_error_t -fal_edma_ring_queue_map_get(a_uint32_t dev_id, - a_uint32_t ring_id, fal_queue_bmp_t *queue_bmp); - -sw_error_t -fal_edma_ring_queue_map_set(a_uint32_t dev_id, - a_uint32_t ring_id, fal_queue_bmp_t *queue_bmp); -sw_error_t -fal_port_queues_get(a_uint32_t dev_id, - fal_port_t port_id, fal_queue_bmp_t *queue_bmp); - -sw_error_t -fal_scheduler_dequeue_ctrl_set(a_uint32_t dev_id, a_uint32_t queue_id, a_bool_t enable); - -sw_error_t -fal_scheduler_dequeue_ctrl_get(a_uint32_t dev_id, a_uint32_t queue_id, a_bool_t *enable); - -sw_error_t -fal_port_scheduler_cfg_reset( - a_uint32_t dev_id, - fal_port_t port_id); - -sw_error_t -fal_port_scheduler_resource_get( - a_uint32_t dev_id, - fal_port_t port_id, - fal_portscheduler_resource_t *cfg); - -#ifdef __cplusplus -} -#endif /* __cplusplus */ -#endif /* _PORT_QOS_H_ */ -/** - * @} - */ diff --git a/feeds/ipq807x/qca-ssdk/src/include/fal/fal_rate.h b/feeds/ipq807x/qca-ssdk/src/include/fal/fal_rate.h deleted file mode 100755 index 99c737798..000000000 --- a/feeds/ipq807x/qca-ssdk/src/include/fal/fal_rate.h +++ /dev/null @@ -1,234 +0,0 @@ -/* - * Copyright (c) 2012,2018, The Linux Foundation. All rights reserved. - * Permission to use, copy, modify, and/or distribute this software for - * any purpose with or without fee is hereby granted, provided that the - * above copyright notice and this permission notice appear in all copies. - * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES - * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR - * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES - * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN - * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT - * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. - */ - - -/** - * @defgroup fal_rate FAL_RATE - * @{ - */ -#ifndef _FAL_RATE_H_ -#define _FAL_RATE_H_ - -#ifdef __cplusplus -extern "C" { -#endif /* __cplusplus */ - -#include "sw.h" -#include "fal/fal_type.h" - - /** - @brief This enum defines storm type - */ - typedef enum { - FAL_UNICAST_STORM = 0, /**< storm caused by unknown unicast packets */ - FAL_MULTICAST_STORM, /**< storm caused by unknown multicast packets */ - FAL_BROADCAST_STORM, /**< storm caused by broadcast packets */ - FAL_STORM_TYPE_BUTT - } - fal_storm_type_t; - - - - sw_error_t - fal_rate_queue_egrl_set(a_uint32_t dev_id, fal_port_t port_id, - fal_queue_t queue_id, a_uint32_t * speed, - a_bool_t enable); - - - - sw_error_t - fal_rate_queue_egrl_get(a_uint32_t dev_id, fal_port_t port_id, - fal_queue_t queue_id, a_uint32_t * speed, - a_bool_t * enable); - - - - sw_error_t - fal_rate_port_egrl_set(a_uint32_t dev_id, fal_port_t port_id, - a_uint32_t * speed, a_bool_t enable); - - - - sw_error_t - fal_rate_port_egrl_get(a_uint32_t dev_id, fal_port_t port_id, - a_uint32_t * speed, a_bool_t * enable); - - - - sw_error_t - fal_rate_port_inrl_set(a_uint32_t dev_id, fal_port_t port_id, - a_uint32_t * speed, a_bool_t enable); - - - - sw_error_t - fal_rate_port_inrl_get(a_uint32_t dev_id, fal_port_t port_id, - a_uint32_t * speed, a_bool_t * enable); - - - - sw_error_t - fal_storm_ctrl_frame_set(a_uint32_t dev_id, fal_port_t port_id, - fal_storm_type_t frame_type, a_bool_t enable); - - - - sw_error_t - fal_storm_ctrl_frame_get(a_uint32_t dev_id, fal_port_t port_id, - fal_storm_type_t frame_type, - a_bool_t * enable); - - - - sw_error_t - fal_storm_ctrl_rate_set(a_uint32_t dev_id, fal_port_t port_id, - a_uint32_t * rate); - - - - sw_error_t - fal_storm_ctrl_rate_get(a_uint32_t dev_id, fal_port_t port_id, - a_uint32_t * rate); - - - typedef enum - { - FAL_RATE_MI_100US = 0, - FAL_RATE_MI_1MS, - FAL_RATE_MI_10MS, - FAL_RATE_MI_100MS, - } fal_rate_mt_t; - - - typedef struct - { - fal_traffic_unit_t meter_unit; - a_uint32_t cir; - a_uint32_t eir; - a_uint32_t cbs; - a_uint32_t ebs; - } fal_egress_shaper_t; - - -#define FAL_INGRESS_POLICING_TCP_CTRL 0x2 -#define FAL_INGRESS_POLICING_MANAGEMENT 0x4 -#define FAL_INGRESS_POLICING_BROAD 0x8 -#define FAL_INGRESS_POLICING_UNK_UNI 0x10 -#define FAL_INGRESS_POLICING_UNK_MUL 0x20 -#define FAL_INGRESS_POLICING_UNI 0x40 -#define FAL_INGRESS_POLICING_MUL 0x80 - - - typedef struct - { - a_bool_t c_enable; - a_bool_t e_enable; - a_bool_t combine_mode; - fal_traffic_unit_t meter_unit; - a_bool_t color_mode; - a_bool_t couple_flag; - a_bool_t deficit_en; - a_uint32_t cir; - a_uint32_t eir; - a_uint32_t cbs; - a_uint32_t ebs; - a_uint32_t c_rate_flag; - a_uint32_t e_rate_flag; - fal_rate_mt_t c_meter_interval; - fal_rate_mt_t e_meter_interval; - } fal_port_policer_t; - - - typedef struct - { - a_bool_t counter_mode; - fal_traffic_unit_t meter_unit; - fal_rate_mt_t meter_interval; - a_bool_t color_mode; - a_bool_t couple_flag; - a_bool_t deficit_en; - a_uint32_t cir; - a_uint32_t eir; - a_uint32_t cbs; - a_uint32_t ebs; - a_uint32_t counter_high; - a_uint32_t counter_low; - } fal_acl_policer_t; - - - sw_error_t - fal_rate_port_policer_set(a_uint32_t dev_id, fal_port_t port_id, - fal_port_policer_t * policer); - - - sw_error_t - fal_rate_port_policer_get(a_uint32_t dev_id, fal_port_t port_id, - fal_port_policer_t * policer); - - - sw_error_t - fal_rate_port_shaper_set(a_uint32_t dev_id, fal_port_t port_id, - a_bool_t enable, fal_egress_shaper_t * shaper); - - - sw_error_t - fal_rate_port_shaper_get(a_uint32_t dev_id, fal_port_t port_id, - a_bool_t * enable, fal_egress_shaper_t * shaper); - - - sw_error_t - fal_rate_queue_shaper_set(a_uint32_t dev_id, fal_port_t port_id, - fal_queue_t queue_id, a_bool_t enable, - fal_egress_shaper_t * shaper); - - - sw_error_t - fal_rate_queue_shaper_get(a_uint32_t dev_id, fal_port_t port_id, - fal_queue_t queue_id, a_bool_t * enable, - fal_egress_shaper_t * shaper); - - - sw_error_t - fal_rate_acl_policer_set(a_uint32_t dev_id, a_uint32_t policer_id, - fal_acl_policer_t * policer); - - - sw_error_t - fal_rate_acl_policer_get(a_uint32_t dev_id, a_uint32_t policer_id, - fal_acl_policer_t * policer); - - sw_error_t - fal_rate_port_add_rate_byte_set(a_uint32_t dev_id, fal_port_t port_id, - a_uint32_t number); - - sw_error_t - fal_rate_port_add_rate_byte_get(a_uint32_t dev_id, fal_port_t port_id, - a_uint32_t *number); - - sw_error_t - fal_rate_port_gol_flow_en_set(a_uint32_t dev_id, fal_port_t port_id, - a_bool_t enable); - sw_error_t - fal_rate_port_gol_flow_en_get(a_uint32_t dev_id, fal_port_t port_id, - a_bool_t* enable); - - - -#ifdef __cplusplus -} -#endif /* __cplusplus */ -#endif /* _FAL_RATE_H_ */ -/** - * @} - */ diff --git a/feeds/ipq807x/qca-ssdk/src/include/fal/fal_reg_access.h b/feeds/ipq807x/qca-ssdk/src/include/fal/fal_reg_access.h deleted file mode 100755 index c5389a5e9..000000000 --- a/feeds/ipq807x/qca-ssdk/src/include/fal/fal_reg_access.h +++ /dev/null @@ -1,97 +0,0 @@ -/* - * Copyright (c) 2012, 2017-2018, The Linux Foundation. All rights reserved. - * Permission to use, copy, modify, and/or distribute this software for - * any purpose with or without fee is hereby granted, provided that the - * above copyright notice and this permission notice appear in all copies. - * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES - * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR - * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES - * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN - * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT - * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. - */ - -/*qca808x_start*/ -/** - * @defgroup fal_reg_access FAL_REG_ACCESS - * @{ - */ -#ifndef _FAL_REG_ACCESS_H_ -#define _FAL_REG_ACCESS_H_ - -#ifdef __cplusplus -extern "C" { -#endif /* __cplusplus */ - -#include "sw.h" -#include "fal/fal_type.h" - - sw_error_t - fal_phy_get(a_uint32_t dev_id, a_uint32_t phy_addr, - a_uint32_t reg, a_uint16_t * value); - - sw_error_t - fal_phy_set(a_uint32_t dev_id, a_uint32_t phy_addr, - a_uint32_t reg, a_uint16_t value); -/*qca808x_end*/ - - sw_error_t - fal_reg_get(a_uint32_t dev_id, a_uint32_t reg_addr, a_uint8_t value[], - a_uint32_t value_len); - - sw_error_t - fal_reg_set(a_uint32_t dev_id, a_uint32_t reg_addr, a_uint8_t value[], - a_uint32_t value_len); - - sw_error_t - fal_psgmii_reg_get(a_uint32_t dev_id, a_uint32_t reg_addr, a_uint8_t value[], - a_uint32_t value_len); - - sw_error_t - fal_psgmii_reg_set(a_uint32_t dev_id, a_uint32_t reg_addr, a_uint8_t value[], - a_uint32_t value_len); - - sw_error_t - fal_reg_field_get(a_uint32_t dev_id, a_uint32_t reg_addr, - a_uint32_t bit_offset, a_uint32_t field_len, - a_uint8_t value[], a_uint32_t value_len); - - sw_error_t - fal_reg_field_set(a_uint32_t dev_id, a_uint32_t reg_addr, - a_uint32_t bit_offset, a_uint32_t field_len, - const a_uint8_t value[], a_uint32_t value_len); - - sw_error_t - fal_debug_reg_dump(a_uint32_t dev_id, fal_debug_reg_dump_t *reg_dump); - - sw_error_t - fal_reg_dump(a_uint32_t dev_id, a_uint32_t reg_idx,fal_reg_dump_t *reg_dump); - - sw_error_t - fal_debug_psgmii_self_test(a_uint32_t dev_id, a_bool_t enable, - a_uint32_t times, a_uint32_t *result); - - sw_error_t - fal_phy_dump(a_uint32_t dev_id, a_uint32_t phy_addr, - a_uint32_t idx, fal_phy_dump_t * phy_dump); - - sw_error_t - fal_uniphy_reg_get(a_uint32_t dev_id, a_uint32_t index, a_uint32_t reg_addr, - a_uint8_t value[], a_uint32_t value_len); - - sw_error_t - fal_uniphy_reg_set(a_uint32_t dev_id, a_uint32_t index, a_uint32_t reg_addr, - a_uint8_t value[], a_uint32_t value_len); - -/*qca808x_start*/ -#ifdef __cplusplus -} -#endif /* __cplusplus */ -#endif /* _FAL_REG_ACCESS_H_ */ - -/** - * @} - */ -/*qca808x_end*/ - diff --git a/feeds/ipq807x/qca-ssdk/src/include/fal/fal_rfs.h b/feeds/ipq807x/qca-ssdk/src/include/fal/fal_rfs.h deleted file mode 100755 index 08c64d6db..000000000 --- a/feeds/ipq807x/qca-ssdk/src/include/fal/fal_rfs.h +++ /dev/null @@ -1,90 +0,0 @@ -/* - * Copyright (c) 2015, The Linux Foundation. All rights reserved. - * Permission to use, copy, modify, and/or distribute this software for - * any purpose with or without fee is hereby granted, provided that the - * above copyright notice and this permission notice appear in all copies. - * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES - * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR - * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES - * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN - * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT - * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. - */ - - -/** - * @defgroup fal_rfs FAL_RFS - * @{ - */ -#ifndef _FAL_RFS_H_ -#define _FAL_RFS_H_ - -#ifdef __cplusplus -extern "C" { -#endif /* __cplusplus */ -#if 0 -typedef struct -{ - u8 addr[6]; - u16 fid; - u8 load_balance; -} ssdk_fdb_rfs_t; - -typedef struct -{ - u8 mac_addr[6]; - u32 ip4_addr; - u32 vid; - u8 load_balance; -} ssdk_ip4_rfs_t; - -typedef struct -{ - u8 mac_addr[6]; - u32 ip6_addr[4]; - u32 vid; - u8 load_balance; -} ssdk_ip6_rfs_t; - - - -int ssdk_rfs_ipct_rule_set( - __be32 ip_src, __be32 ip_dst, - __be16 sport, __be16 dport, uint8_t proto, - u16 loadbalance, bool action); - -int ssdk_rfs_mac_rule_set(ssdk_fdb_rfs_t *rfs); -int ssdk_rfs_mac_rule_del(ssdk_fdb_rfs_t *rfs); - -int -ssdk_ip_rfs_ip4_rule_set(ssdk_ip4_rfs_t * rfs); - -int -ssdk_ip_rfs_ip6_rule_set(ssdk_ip6_rfs_t * rfs); - -int -ssdk_ip_rfs_ip4_rule_del(ssdk_ip4_rfs_t * rfs); - -int -ssdk_ip_rfs_ip6_rule_del(ssdk_ip6_rfs_t * rfs); -#endif -int ssdk_rfs_mac_rule_set(u16 vid, u8* mac, u8 ldb, int is_set); -int ssdk_rfs_ip4_rule_set(u16 vid, u32 ip, u8* mac, u8 ldb, int is_set); -int ssdk_rfs_ip6_rule_set(u16 vid, u8* ip, u8* mac, u8 ldb, int is_set); -int ssdk_rfs_ipct_rule_set( - __be32 ip_src, __be32 ip_dst, - __be16 sport, __be16 dport, uint8_t proto, - u16 loadbalance, bool action); - - - -#ifdef __cplusplus -} -#endif /* __cplusplus */ -#endif /* _FAL_RFS_H_ */ - -/** - * @} - */ - diff --git a/feeds/ipq807x/qca-ssdk/src/include/fal/fal_rss_hash.h b/feeds/ipq807x/qca-ssdk/src/include/fal/fal_rss_hash.h deleted file mode 100755 index e11b9b013..000000000 --- a/feeds/ipq807x/qca-ssdk/src/include/fal/fal_rss_hash.h +++ /dev/null @@ -1,77 +0,0 @@ -/* - * Copyright (c) 2017-2018, The Linux Foundation. All rights reserved. - * Permission to use, copy, modify, and/or distribute this software for - * any purpose with or without fee is hereby granted, provided that the - * above copyright notice and this permission notice appear in all copies. - * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES - * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR - * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES - * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN - * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT - * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. - */ - - -/** - * @defgroup fal_gen FAL_RSS_HASH - * @{ - */ -#ifndef _FAL_RSS_HASH_H_ -#define _FAL_RSS_HASH_H_ - -#ifdef __cplusplus -extern "C" { -#endif /* __cplusplus */ - -#include "sw.h" -#include "fal/fal_type.h" - -#if defined(SW_API_LOCK) && (!defined(HSL_STANDALONG)) -#define FAL_RSS_HASH_API_LOCK -#define FAL_RSS_HASH_API_UNLOCK -#else -#define FAL_RSS_HASH_API_LOCK -#define FAL_RSS_HASH_API_UNLOCK -#endif - -typedef enum -{ - FAL_RSS_HASH_IPV4V6 = 0, - FAL_RSS_HASH_IPV4ONLY = 1, - FAL_RSS_HASH_IPV6ONLY = 2, -} fal_rss_hash_mode_t; - -typedef struct -{ - a_uint32_t hash_mask; /* final hash value bits */ - a_bool_t hash_fragment_mode; /* enable fragment mode or not */ - a_uint32_t hash_seed; /* rss hash seed value */ - a_uint32_t hash_sip_mix; /* source ip hash mix */ - a_uint32_t hash_dip_mix; /* dest ip hash mix */ - a_uint8_t hash_protocol_mix; /* L4 protocol hash mix */ - a_uint8_t hash_sport_mix; /* L4 source port hash mix */ - a_uint8_t hash_dport_mix; /* L4 dest port hash mix */ - a_uint32_t hash_fin_inner; /* hash fin inner mix */ - a_uint32_t hash_fin_outer; /* hash fin outer mix */ -} fal_rss_hash_config_t; - -enum { - FUNC_RSS_HASH_CONFIG_SET = 0, - FUNC_RSS_HASH_CONFIG_GET, -}; - -sw_error_t -fal_rss_hash_config_set(a_uint32_t dev_id, fal_rss_hash_mode_t mode, fal_rss_hash_config_t * config); - -sw_error_t -fal_rss_hash_config_get(a_uint32_t dev_id, fal_rss_hash_mode_t mode, fal_rss_hash_config_t * config); - -#ifdef __cplusplus -} -#endif /* __cplusplus */ -#endif /* _FAL_RSS_HASH_H_ */ -/** - * @} - */ - diff --git a/feeds/ipq807x/qca-ssdk/src/include/fal/fal_sec.h b/feeds/ipq807x/qca-ssdk/src/include/fal/fal_sec.h deleted file mode 100755 index eff27fee0..000000000 --- a/feeds/ipq807x/qca-ssdk/src/include/fal/fal_sec.h +++ /dev/null @@ -1,251 +0,0 @@ -/* - * Copyright (c) 2012, 2016-2018, The Linux Foundation. All rights reserved. - * Permission to use, copy, modify, and/or distribute this software for - * any purpose with or without fee is hereby granted, provided that the - * above copyright notice and this permission notice appear in all copies. - * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES - * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR - * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES - * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN - * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT - * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. - */ - - -/** - * @defgroup fal_sec FAL_SEC - * @{ - */ -#ifndef _FAL_SEC_H_ -#define _FAL_SEC_H_ - -#ifdef __cplusplus -extern "C" { -#endif /* __cplusplus */ - -#include "sw.h" -#include "fal/fal_type.h" - -/* Exception: L2 */ -#define FAL_SEC_EXP_UNKNOWN_L2_PROT 1 -#define FAL_SEC_EXP_PPPOE_WRONG_VER_TYPE 2 -#define FAL_SEC_EXP_PPPOE_WRONG_CODE 3 -#define FAL_SEC_EXP_PPPOE_UNSUPPORTED_PPP_PROT 4 -/* Exception: IPv4 */ -#define FAL_SEC_EXP_IPV4_WRONG_VER 5 -#define FAL_SEC_EXP_IPV4_SMALL_IHL 6 -#define FAL_SEC_EXP_IPV4_WITH_OPTION 7 - -#define FAL_SEC_EXP_IPV4_HDR_INCOMPLETE 8 - -#define FAL_SEC_EXP_IPV4_BAD_TOTAL_LEN 9 -#define FAL_SEC_EXP_IPV4_DATA_INCOMPLETE 10 - -#define FAL_SEC_EXP_IPV4_FRAG 11 -#define FAL_SEC_EXP_IPV4_PING_OF_DEATH 12 - -#define FAL_SEC_EXP_IPV4_SNALL_TTL 13 -#define FAL_SEC_EXP_IPV4_UNK_IP_PROT 14 -#define FAL_SEC_EXP_IPV4_CHECKSUM_ERR 15 -#define FAL_SEC_EXP_IPV4_INV_SIP 16 -#define FAL_SEC_EXP_IPV4_INV_DIP 17 -#define FAL_SEC_EXP_IPV4_LAND_ATTACK 18 -#define FAL_SEC_EXP_IPV4_AH_HDR_INCOMPLETE 19 -#define FAL_SEC_EXP_IPV4_AH_HDR_CROSS_BORDER 20 -#define FAL_SEC_EXP_IPV4_ESP_HDR_INCOMPLETE 21 -/* Exception: IPv6 */ -#define FAL_SEC_EXP_IPV6_WRONG_VER 22 -#define FAL_SEC_EXP_IPV6_HDR_INCOMPLETE 23 -#define FAL_SEC_EXP_IPV6_BAD_PAYLOAD_LEN 24 -#define FAL_SEC_EXP_IPV6_DATA_INCOMPLETE 25 -#define FAL_SEC_EXP_IPV6_WITH_EXT_HDR 26 -#define FAL_SEC_EXP_IPV6_SMALL_HOP_LIMIT 27 -#define FAL_SEC_EXP_IPV6_INV_SIP 28 -#define FAL_SEC_EXP_IPV6_INV_DIP 29 -#define FAL_SEC_EXP_IPV6_LAND_ATTACK 30 -#define FAL_SEC_EXP_IPV6_FRAG 31 -#define FAL_SEC_EXP_IPV6_PING_OF_DEATH 32 -#define FAL_SEC_EXP_IPV6_WITH_MORE_EXT_HDR 33 -#define FAL_SEC_EXP_IPV6_UNK_LAST_NEXT_HDR 34 -#define FAL_SEC_EXP_IPV6_MOBILITY_HDR_INCOMPLETE 35 -#define FAL_SEC_EXP_IPV6_MOBILITY_HDR_CROSS_BORDER 36 -#define FAL_SEC_EXP_IPV6_AH_HDR_INCOMPLETE 37 -#define FAL_SEC_EXP_IPV6_AH_HDR_CROSS_BORDER 38 -#define FAL_SEC_EXP_IPV6_ESP_HDR_INCOMPLETE 39 -#define FAL_SEC_EXP_IPV6_ESP_HDR_CROSS_BORDER 40 - -#define FAL_SEC_EXP_IPV6_OTHER_EXT_HDR_INCOMPLETE 41 -#define FAL_SEC_EXP_IPV6_OTHER_EXT_HDR_CROSS_BORDER 42 - -/* Exception: L4 */ -#define FAL_SEC_EXP_TCP_HDR_INCOMPLETE 43 -#define FAL_SEC_EXP_TCP_HDR_CROSS_BORDER 44 -#define FAL_SEC_EXP_TCP_SMAE_SP_DP 45 -#define FAL_SEC_EXP_TCP_SMALL_DATA_OFFSET 46 -#define FAL_SEC_EXP_TCP_FLAGS_0 47 -#define FAL_SEC_EXP_TCP_FLAGS_1 48 -#define FAL_SEC_EXP_TCP_FLAGS_2 49 -#define FAL_SEC_EXP_TCP_FLAGS_3 50 -#define FAL_SEC_EXP_TCP_FLAGS_4 51 -#define FAL_SEC_EXP_TCP_FLAGS_5 52 -#define FAL_SEC_EXP_TCP_FLAGS_6 53 -#define FAL_SEC_EXP_TCP_FLAGS_7 54 -#define FAL_SEC_EXP_TCP_CHECKSUM_ERR 55 -#define FAL_SEC_EXP_UDP_HDR_INCOMPLETE 56 -#define FAL_SEC_EXP_UDP_HDR_CROSS_BORDER 57 - -#define FAL_SEC_EXP_UDP_SMAE_SP_DP 58 -#define FAL_SEC_EXP_UDP_BAD_LEN 59 -#define FAL_SEC_EXP_UDP_DATA_INCOMPLETE 60 - - -#define FAL_SEC_EXP_UDP_CHECKSUM_ERR 61 -#define FAL_SEC_EXP_UDP_LITE_HDR_INCOMPLETE 62 -#define FAL_SEC_EXP_UDP_LITE_HDR_CROSS_BORDER 63 -#define FAL_SEC_EXP_UDP_LITE_SMAE_SP_DP 64 -/* Other exception */ -#define FAL_SEC_EXP_UDP_LITE_CSM_COV_1_TO_7 65 -#define FAL_SEC_EXP_UDP_LITE_CSM_COV_TOO_LONG 66 -#define FAL_SEC_EXP_UDP_LITE_CSM_COV_CROSS_BORDER 67 -#define FAL_SEC_EXP_UDP_LITE_CHECKSUM_ERR 68 - -/**/ - -#define FAL_SEC_EXP_FAKE_L2_PROT_ERR 69 -#define FAL_SEC_EXP_FAKE_MAC_HEADER_ERR 70 - - - typedef enum { - /* define MAC layer related normalization items */ - FAL_NORM_MAC_RESV_VID_CMD = 0, - FAL_NORM_MAC_INVALID_SRC_ADDR_CMD, - - /* define IP layer related normalization items */ - FAL_NORM_IP_INVALID_VER_CMD, - FAL_NROM_IP_SAME_ADDR_CMD, - FAL_NROM_IP_TTL_CHANGE_STATUS, - FAL_NROM_IP_TTL_VALUE, - - /* define IP4 related normalization items */ - FAL_NROM_IP4_INVALID_HL_CMD, - FAL_NROM_IP4_HDR_OPTIONS_CMD, - FAL_NROM_IP4_INVALID_DF_CMD, - FAL_NROM_IP4_FRAG_OFFSET_MIN_LEN_CMD, - FAL_NROM_IP4_FRAG_OFFSET_MAX_LEN_CMD, - FAL_NROM_IP4_INVALID_FRAG_OFFSET_CMD, - FAL_NROM_IP4_INVALID_SIP_CMD, - FAL_NROM_IP4_INVALID_DIP_CMD, - FAL_NROM_IP4_INVALID_CHKSUM_CMD, - FAL_NROM_IP4_INVALID_PL_CMD, - FAL_NROM_IP4_DF_CLEAR_STATUS, - FAL_NROM_IP4_IPID_RANDOM_STATUS, - FAL_NROM_IP4_FRAG_OFFSET_MIN_SIZE, - - /* define IP4 related normalization items */ - FAL_NROM_IP6_INVALID_PL_CMD, - FAL_NROM_IP6_INVALID_SIP_CMD, - FAL_NROM_IP6_INVALID_DIP_CMD, - - /* define TCP related normalization items */ - FAL_NROM_TCP_BLAT_CMD, - FAL_NROM_TCP_INVALID_HL_CMD, - FAL_NROM_TCP_INVALID_SYN_CMD, - FAL_NROM_TCP_SU_BLOCK_CMD, - FAL_NROM_TCP_SP_BLOCK_CMD, - FAL_NROM_TCP_SAP_BLOCK_CMD, - FAL_NROM_TCP_XMAS_SCAN_CMD, - FAL_NROM_TCP_NULL_SCAN_CMD, - FAL_NROM_TCP_SR_BLOCK_CMD, - FAL_NROM_TCP_SF_BLOCK_CMD, - FAL_NROM_TCP_SAR_BLOCK_CMD, - FAL_NROM_TCP_RST_SCAN_CMD, - FAL_NROM_TCP_SYN_WITH_DATA_CMD, - FAL_NROM_TCP_RST_WITH_DATA_CMD, - FAL_NROM_TCP_FA_BLOCK_CMD, - FAL_NROM_TCP_PA_BLOCK_CMD, - FAL_NROM_TCP_UA_BLOCK_CMD, - FAL_NROM_TCP_INVALID_CHKSUM_CMD, - FAL_NROM_TCP_INVALID_URGPTR_CMD, - FAL_NROM_TCP_INVALID_OPTIONS_CMD, - FAL_NROM_TCP_MIN_HDR_SIZE, - - /* define UDP related normalization items */ - FAL_NROM_UDP_BLAT_CMD, - FAL_NROM_UDP_INVALID_LEN_CMD, - FAL_NROM_UDP_INVALID_CHKSUM_CMD, - - /* define ICMP related normalization items */ - FAL_NROM_ICMP4_PING_PL_EXCEED_CMD, - FAL_NROM_ICMP6_PING_PL_EXCEED_CMD, - FAL_NROM_ICMP4_PING_FRAG_CMD, - FAL_NROM_ICMP6_PING_FRAG_CMD, - FAL_NROM_ICMP4_PING_MAX_PL_VALUE, - FAL_NROM_ICMP6_PING_MAX_PL_VALUE, - } - fal_norm_item_t; - - typedef struct { - fal_fwd_cmd_t cmd; /* action for the exception */ - a_bool_t deacclr_en; /* 0 for disable and 1 for disable */ - a_bool_t l3route_only_en; /*host/network route 0: disable and 1: enable*/ - a_bool_t l2fwd_only_en; /*l2 forward 0: disable and 1: enable*/ - a_bool_t l3flow_en; /* 0 for disable and 1 for disable */ - a_bool_t l2flow_en; /* 0 for disable and 1 for disable */ - a_bool_t multicast_en; /* 0 for disable and 1 for disable */ - } fal_l3_excep_ctrl_t; - - typedef struct { - a_uint8_t small_ip4ttl; /* small ttl value checking */ - a_uint8_t small_ip6hoplimit; /*small hoplimit value for check*/ - } fal_l3_excep_parser_ctrl; - -#define TCP_FLAGS_MAX 8 - typedef struct { - a_uint8_t tcp_flags[TCP_FLAGS_MAX]; /*flag for exception*/ - a_uint8_t tcp_flags_mask[TCP_FLAGS_MAX]; /*flag mask*/ - } fal_l4_excep_parser_ctrl; - -enum { - FUNC_SEC_L3_EXCEP_CTRL_SET = 0, - FUNC_SEC_L3_EXCEP_CTRL_GET, - FUNC_SEC_L3_EXCEP_PARSER_CTRL_SET, - FUNC_SEC_L3_EXCEP_PARSER_CTRL_GET, - FUNC_SEC_L4_EXCEP_PARSER_CTRL_SET, - FUNC_SEC_L4_EXCEP_PARSER_CTRL_GET, -}; - - sw_error_t - fal_sec_norm_item_set(a_uint32_t dev_id, fal_norm_item_t item, void *value); - - sw_error_t - fal_sec_norm_item_get(a_uint32_t dev_id, fal_norm_item_t item, void *value); - - sw_error_t - fal_sec_l3_excep_ctrl_set(a_uint32_t dev_id, a_uint32_t excep_type, fal_l3_excep_ctrl_t *ctrl); - - sw_error_t - fal_sec_l3_excep_ctrl_get(a_uint32_t dev_id, a_uint32_t excep_type, fal_l3_excep_ctrl_t *ctrl); - - sw_error_t - fal_sec_l3_excep_parser_ctrl_set(a_uint32_t dev_id, fal_l3_excep_parser_ctrl *ctrl); - - sw_error_t - fal_sec_l3_excep_parser_ctrl_get(a_uint32_t dev_id, fal_l3_excep_parser_ctrl *ctrl); - - sw_error_t - fal_sec_l4_excep_parser_ctrl_set(a_uint32_t dev_id, fal_l4_excep_parser_ctrl *ctrl); - - sw_error_t - fal_sec_l4_excep_parser_ctrl_get(a_uint32_t dev_id, fal_l4_excep_parser_ctrl *ctrl); - - -#ifdef __cplusplus -} -#endif /* __cplusplus */ -#endif /* _FAL_SEC_H_ */ - -/** - * @} - */ - diff --git a/feeds/ipq807x/qca-ssdk/src/include/fal/fal_servcode.h b/feeds/ipq807x/qca-ssdk/src/include/fal/fal_servcode.h deleted file mode 100755 index cf8705bbb..000000000 --- a/feeds/ipq807x/qca-ssdk/src/include/fal/fal_servcode.h +++ /dev/null @@ -1,137 +0,0 @@ -/* - * Copyright (c) 2016-2018, The Linux Foundation. All rights reserved. - * Permission to use, copy, modify, and/or distribute this software for - * any purpose with or without fee is hereby granted, provided that the - * above copyright notice and this permission notice appear in all copies. - * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES - * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR - * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES - * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN - * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT - * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. - */ - - -/** - * @defgroup fal_gen FAL_SERVCODE - * @{ - */ -#ifndef _FAL_SERVCODE_H_ -#define _FAL_SERVCODE_H_ - -#ifdef __cplusplus -extern "C" { -#endif /* __cplusplus */ - -#include "sw.h" -#include "fal/fal_type.h" - -#if defined(SW_API_LOCK) && (!defined(HSL_STANDALONG)) -#define FAL_SERVCODE_API_LOCK -#define FAL_SERVCODE_API_UNLOCK -#else -#define FAL_SERVCODE_API_LOCK -#define FAL_SERVCODE_API_UNLOCK -#endif - -enum { - FLD_UPDATE_CAPWAP_EN = 0, /*only for IP197*/ - FLD_UPDATE_DIRECTION, /*only for IP197*/ - FLD_UPDATE_DEST_INFO, - FLD_UPDATE_SRC_INFO, - FLD_UPDATE_INT_PRI, - FLD_UPDATE_SERVICE_CODE, - FLD_UPDATE_HASH_FLOW_INDEX, - FLD_UPDATE_FAKE_L2_PROT_EN, /*only for IP197*/ -}; - -enum { - IN_VLAN_TAG_FMT_CHECK_BYP = 0, - IN_VLAN_MEMBER_CHECK_BYP, - IN_VLAN_XLT_BYP, - MY_MAC_CHECK_BYP, - DIP_LOOKUP_BYP, - FLOW_LOOKUP_BYP = 5, - FLOW_ACTION_BYP, - ACL_BYP, - FAKE_MAC_HEADER_BYP, - SERVICE_CODE_BYP, - WRONG_PKT_FMT_L2_BYP = 10, - WRONG_PKT_FMT_L3_IPV4_BYP, - WRONG_PKT_FMT_L3_IPV6_BYP, - WRONG_PKT_FMT_L4_BYP, - FLOW_SERVICE_CODE_BYP, - ACL_SERVICE_CODE_BYP = 15, - FAKE_L2_PROTO_BYP, - PPPOE_TERMINATION_BYP, - DEFAULT_VLAN_BYP, - IN_VLAN_ASSIGN_FAIL_BYP = 24, - SOURCE_GUARD_BYP, - MRU_MTU_CHECK_BYP, - FLOW_SRC_CHECK_BYP, - FLOW_QOS_BYP, - - EG_VLAN_MEMBER_CHECK_BYP = 32, - EG_VLAN_XLT_BYP, - EG_VLAN_TAG_FMT_CTRL_BYP, - FDB_LEARN_BYP = 35, - FDB_REFRESH_BYP, - L2_SOURCE_SEC_BYP, - MANAGEMENT_FWD_BYP, - BRIDGING_FWD_BYP, - IN_STP_FLTR_BYP = 40, - EG_STP_FLTR_BYP, - SOURCE_FLTR_BYP, - POLICER_BYP, - L2_PKT_EDIT_BYP, - L3_PKT_EDIT_BYP = 45, - ACL_POST_ROUTING_CHECK_BYP, - PORT_ISOLATION_BYP, - /* for cypress Qos bypass */ - PRE_ACL_QOS_BYP, - POST_ACL_QOS_BYP, - DSCP_QOS_BYP, - PCP_QOS_BYP, - PREHEADER_QOS_BYP, - - RX_VLAN_COUNTER_BYP = 64, - RX_COUNTER_BYP, - TX_VLAN_COUNTER_BYP, - TX_COUNTER_BYP, -}; - -typedef struct { - a_bool_t dest_port_valid; /* dest_port_id valid or not */ - fal_port_t dest_port_id; /* destination physical port id:0-7 */ - a_uint32_t bypass_bitmap[3]; /* refer to enum IN_VLAN_TAG_FMT_CHECK_BYP... */ - a_uint32_t direction; /* if dest is vp, fill it in dest_info or src_info, 0:dest, 1:src */ - - a_uint32_t field_update_bitmap; /* refer to enum FLD_UPDATE_CAPWAP_EN... */ - a_uint32_t next_service_code; /* next service code */ - a_uint32_t hw_services; /* HW_SERVICES to IP-197 */ - a_uint32_t offset_sel; /* Select the offset value to IP-197:0: l3_offset, 1:l4_offset */ -} fal_servcode_config_t; - -enum -{ - /*servcode*/ - FUNC_SERVCODE_CONFIG_SET = 0, - FUNC_SERVCODE_CONFIG_GET, - FUNC_SERVCODE_LOOPCHECK_EN, - FUNC_SERVCODE_LOOPCHECK_STATUS_GET, -}; - -sw_error_t fal_servcode_config_set(a_uint32_t dev_id, a_uint32_t servcode_index, fal_servcode_config_t *entry); -sw_error_t fal_servcode_config_get(a_uint32_t dev_id, a_uint32_t servcode_index, fal_servcode_config_t *entry); -sw_error_t fal_servcode_loopcheck_en(a_uint32_t dev_id, a_bool_t enable); -sw_error_t fal_servcode_loopcheck_status_get(a_uint32_t dev_id, a_bool_t *enable); - -#ifdef __cplusplus -} -#endif /* __cplusplus */ -#endif /* _FAL_SERVCODE_H_ */ -/** - * @} - */ - diff --git a/feeds/ipq807x/qca-ssdk/src/include/fal/fal_sfp.h b/feeds/ipq807x/qca-ssdk/src/include/fal/fal_sfp.h deleted file mode 100755 index 973245c21..000000000 --- a/feeds/ipq807x/qca-ssdk/src/include/fal/fal_sfp.h +++ /dev/null @@ -1,578 +0,0 @@ -/* - * Copyright (c) 2019, The Linux Foundation. All rights reserved. - * Permission to use, copy, modify, and/or distribute this software for - * any purpose with or without fee is hereby granted, provided that the - * above copyright notice and this permission notice appear in all copies. - * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES - * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR - * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES - * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN - * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT - * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. - */ - - -/** - * @defgroup fal_sfp FAL_SFP - * @{ - */ -#ifndef _FAL_SFP_H_ -#define _FAL_SFP_H_ - -#ifdef __cplusplus -extern "C" { -#endif /* __cplusplus */ - -#include "sw.h" -#include "fal/fal_type.h" - -typedef enum { - FAL_SFP_CC_BASE = 0, /* Check code for Base ID Fields (addresses 0 to 62) */ - FAL_SFP_CC_EXT, /* Check code for the Extended ID Fields (addresses 64 to 94) */ - FAL_SFP_CC_DMI, /* Check code for Base Diagnostic Fields (addresses 0 to 94) */ -} fal_sfp_cc_type_t; - -typedef struct { - a_uint32_t addr; /* Addr A0h or A2h */ - a_uint32_t offset; /* offset in eeprom */ - a_uint32_t count; /* data bytes */ - a_uint8_t data[256]; /* data value */ -} fal_sfp_data_t; - -/* A0h offset: 0-2 bytes */ -typedef struct { - a_uint8_t identifier; /* type of transceiver */ - /* - * 00h: Unknown or unspecified - * 01h: GBIC - * 02h: Module soldered to motherboard (ex: SFF) - * 03h: SFP or SFP “Plus” - * 04h: Reserved for “300 pin XBI” devices* - * 05h: Reserved for “Xenpak” devices* - * 06h: Reserved for “XFP” devices* - * 07h: Reserved for “XFF” devices* - * 08h: Reserved for “XFP-E” devices* - * 09h: Reserved for “XPak” devices* - * 0Ah: Reserved for “X2” devices* - * 0Bh: Reserved for “DWDM-SFP” devices* - * 0Ch: Reserved for “QSFP” devices* - * 0D-7Fh: Reserved, unallocated - * 80-FFh: Vendor specific - */ - a_uint8_t ext_indentifier; /* Extended identifier of type of transceiver */ - /* - * 00h: GBIC definition is not specified or not compliant with a defined MOD_DEF. - * 01h: GBIC is compliant with MOD_DEF 1 - * 02h: GBIC is compliant with MOD_DEF 2 - * 03h: GBIC is compliant with MOD_DEF 3 - * 04h: GBIC/SFP function is defined by two-wire interface ID only - * 05h: GBIC is compliant with MOD_DEF 5 - * 06h: GBIC is compliant with MOD_DEF 6 - * 07h: GBIC is compliant with MOD_DEF 7 - * 08-FFh: Unallocated - */ - a_uint8_t connector_type; /* Code for connector type */ - /* - * 00h: Unknown or unspecified - * 01h: SC - * 02h: Fibre Channel Style 1 copper connector - * 03h: Fibre Channel Style 2 copper connector - * 04h: BNC/TNC - * 05h: Fibre Channel coaxial headers - * 06h: FiberJack - * 07h: LC - * 08h: MT-RJ - * 09h: MU - * 0AH: SG - * 0Bh: Optical pigtail - * 0Ch: MPO Parallel Optic - * 0D-1Fh: Unallocated - * 20h: HSSDC II - * 21h: Copper pigtail - * 22h: RJ45 - * 23h-7Fh: Unallocated - * 80h-FFh: Vendor specific - */ -} fal_sfp_dev_type_t; - -/* A0h offset: 3-10 bytes */ -typedef struct { - a_uint8_t eth_10g_ccode; /* 10G Ethernet Compliance Codes */ - /* - * offset 3 bit7: 10G Base-ER - * offset 3 bit6: 10G Base-LRM - * offset 3 bit5: 10G Base-LR - * offset 3 bit4: 10G Base-SR - */ - a_uint8_t infiniband_ccode; /* Infiniband Compliance Codes */ - /* - * offset 3 bit3: 1X SX - * offset 3 bit2: 1X LX - * offset 3 bit1: 1X Copper Active - * offset 3 bit0: 1X Copper Passive - */ - a_uint8_t escon_ccode; /* ESCON Compliance Codes */ - /* - * offset 4 bit7: ESCON MMF, 1310nm LED - * offset 4 bit6: ESCON SMF, 1310nm Laser - */ - a_uint16_t sonet_ccode; /* SONET Compliance Codes */ - /* - * offset 4 bit5: OC-192, short reach - * offset 4 bit4: SONET reach specifier bit 1 - * offset 4 bit3: SONET reach specifier bit 2 - * offset 4 bit2: OC-48, long reach - * offset 4 bit1: OC-48, intermediate reach - * offset 4 bit0: OC-48, short reach - * offset 5 bit7: Unallocated - * offset 5 bit6: OC-12, single mode, long reach - * offset 5 bit5: OC-12, single mode, inter. reach - * offset 5 bit4: OC-12, short reach - * offset 5 bit3: Unallocated - * offset 5 bit2: OC-3, single mode, long reach - * offset 5 bit1: OC-3, single mode, inter. reach - * offset 5 bit0: OC-3, short reach - */ - a_uint8_t eth_ccode; /* Ethernet Compliance Codes */ - /* - * offset 6 bit7: BASE-PX - * offset 6 bit6: BASE-BX10 - * offset 6 bit5: 100BASE-FX - * offset 6 bit4: 100BASE-LX/LX10 - * offset 6 bit3: 1000BASE-T - * offset 6 bit2: 1000BASE-CX - * offset 6 bit1: 1000BASE-LX - * offset 6 bit0: 1000BASE-SX - */ - a_uint8_t fibre_chan_link_length; /* Fibre Channel Link Length */ - /* - * offset 7 bit7: very long distance (V) - * offset 7 bit6: short distance (S) - * offset 7 bit5: intermediate distance (I) - * offset 7 bit4: long distance (L) - * offset 7 bit3: medium distance (M) - */ - a_uint8_t fibre_chan_tech; /* Fibre Channel Technology */ - /* - * offset 7 bit2: Shortwave laser, linear Rx (SA) - * offset 7 bit1: Longwave laser (LC) - * offset 7 bit0: Electrical inter-enclosure (EL) - * offset 8 bit7: Electrical intra-enclosure (EL) - * offset 8 bit6: Shortwave laser w/o OFC (SN) - * offset 8 bit5: Shortwave laser with OFC4 (SL) - * offset 8 bit4: Longwave laser (LL) - */ - a_uint8_t sfp_cable_tech; /* SFP+ Cable Technology */ - /* - * offset 8 bit3: Active Cable - * offset 8 bit2: passive Cable - * offset 8 bit1: unallocated - * offset 8 bit0: unallocated - */ - a_uint8_t fibre_chan_trans_md; /* Fibre Channel Transmission Media */ - /* - * offset 9 bit7: twin axial pair(TW) - * offset 9 bit6: twisted pair(TP) - * offset 9 bit5: miniature coax(MI) - * offset 9 bit4: video coax(TV) - * offset 9 bit3: multimode, 62.5um(M6) - * offset 9 bit2: multimode, 50um(M5,M5E) - * offset 9 bit1: unallocated - * offset 9 bit0: sigle mode(SM) - */ - a_uint8_t fibre_chan_speed; /* Fibre Channel Speed */ - /* - * offset 10 bit7: 1200 MBytes/sec - * offset 10 bit6: 800 MBytes/sec - * offset 10 bit5: 1600 MBytes/sec - * offset 10 bit4: 400 MBytes/sec - * offset 10 bit3: unallocated - * offset 10 bit2: 200 MBytes/sec - * offset 10 bit1: unallocated - * offset 10 bit0: 100 MBytes/sec - */ -} fal_sfp_transc_code_t; - -/* A0h offset: 11-13 bytes */ -typedef struct { - a_uint8_t encode; /* the serial encoding mechanism */ - /* - * 0h: Unspecified - * 1h: 8B/10B - * 2h: 4B/5B - * 3h: NRZ - * 4h: Manchester - * 5h: SONET Scrambled - * 6h： 64B/66B - * 7h-FFh: Unallocated - */ - a_uint8_t nominal_bit_rate; /* the nomial bit rate */ - /* - * these bits necessary to encode and delimit the signal - * as well as those bits carrying data information, - * the actual transfer rate will depend on the encoding - * of the data definded by the encode value above. - */ - a_uint8_t rate_id; /* the selected rate */ - /* - * 0h: Unspecified - * 1h: Defined for SFF-8079 (4/2/1G Rate_Select & AS0/AS1) - * 2h: Defined for SFF-8431 (8/4/2G Rx Rate_Select only) - * 3h: Unspecified * - * 4h: Defined for SFF-8431 (8/4/2G Tx Rate_Select only) - * 5h: Unspecified * - * 6h: Defined for SFF-8431 (8/4/2G Independent Rx & Tx Rate_select) - * 7h-FFh: Unallocated - */ -} fal_sfp_rate_encode_t; - - -/* A0h offset: 14-19 bytes */ -typedef struct { - a_uint8_t single_mode_length_km; /* the link length of km in single mode */ - a_uint8_t single_mode_length_100m; /* the link length of 100m in single mode */ - a_uint8_t om2_mode_length_10m; /* the link length of 10m micron multimode OM2 */ - a_uint8_t om1_mode_length_10m; /* the link length of 10m micron multimode OM1 */ - a_uint8_t copper_mode_length_1m; /* the link length of 1m copper mode */ - a_uint8_t om3_mode_length_1m; /* the link length of 10m micron multimode OM3 */ -} fal_sfp_link_length_t; - -/* A0h offset: 20-35 bytes vendor name*/ -/* A0h offset: 36th byte transceiver code */ -/* A0h offset: 37-39 bytes vendor oui */ -/* A0h offset: 40-55 bytes vendor pn */ -/* A0h offset: 56-59 bytes vendor rev */ -/* A0h offset: 68-83 bytes for the vendor serial number */ -/* A0h offset: 84-91 bytes for the vendor's date code in ascii charaters */ -typedef struct { - a_uint8_t vendor_name[16]; /* vendor name */ - a_uint8_t vendor_oui[3]; /* vendor OUI */ - a_uint8_t vendor_pn[16]; /* vendor PN */ - a_uint8_t vendor_rev[4]; /* vendor Rev */ - a_uint8_t vendor_sn[16]; /* the vendor serial number */ - a_uint8_t vendor_date_code[8]; /* the vendor's date code in ascii charaters */ -} fal_sfp_vendor_info_t; - -/* A0h offset: 60-61 bytes */ -typedef struct { - a_uint16_t laser_wavelength; /* the output laser wave length in nm */ -} fal_sfp_laser_wavelength_t; - -/* A0h offset: 62 byte unallocated */ -/* A0h offset: 63 byte for checksum base */ - -/* A0h offset: 64-65 bytes */ -typedef struct { - /* the implemented options */ - a_uint8_t linear_recv_output:1; - a_uint8_t pwr_level_declar:1; - a_uint8_t cool_transc_declar:1; - a_uint8_t reversed_1:5; - - a_uint8_t reversed_2:1; - a_uint8_t loss_signal:1; - a_uint8_t loss_invert_signal:1; - a_uint8_t tx_fault_signal:1; - a_uint8_t tx_disable:1; - a_uint8_t rate_sel:1; - a_uint8_t reversed_3:2; - /* - * offset 64 bit7-3: Unallocated - * offset 64 bit2: Cooled Transceiver Declaration (see SFF-8431) - * offset 64 bit1: Power Level Declaration (see SFF-8431) - * offset 64 bit0: Linear Receiver Output Implemented (see SFF-8431) - * offset 65 bit7-6: Unallocated - * offset 65 bit5: RATE_SELECT functionality is implemented - * offset 65 bit4: TX_DISABLE is implemented and disables the high speed serial output - * offset 65 bit3: TX_FAULT signal implemented. (See SFP MSA) - * offset 65 bit2: Loss of Signal implemented, signal inverted from standard definition - * offset 65 bit1: Loss of Signal implemented, signal as defined in SFP MSA - * offset 65 bit0: Unallocated - */ -} fal_sfp_option_t; - -/* A0h offset: 66-67 bytes */ -typedef struct { - a_uint8_t upper_rate_limit; /* the upper rate limit */ - a_uint8_t lower_rate_limit; /* the lower rate limit */ -} fal_sfp_rate_t; - -/* A0h offset: 68-83 bytes for the vendor serial number */ -/* A0h offset: 84-91 bytes for the vendor's date code in ascii charaters */ - -/* A0h offset: 92-94 bytes */ -typedef struct { - /* digital diagnostic monitoring type */ - a_uint8_t reserved_type:2; - a_uint8_t addr_mode:1; - a_uint8_t rec_pwr_type:1; - a_uint8_t external_cal:1; - a_uint8_t internal_cal:1; - a_uint8_t diag_mon_flag:1; - a_uint8_t legacy_type:1; - /* - * bit 7: Reserved for legacy diagnostic - * bit 6: Digital diagnostic monitoring implemented - * bit 5: Internally calibrated - * bit 4: Externally calibrated - * bit 3: Received power measurement type - * 0 = OMA, 1 = average power - * bit 2: Address change required “addressing modes” - * bit1~0: unallocated - */ - /* optional digital diagnostic features implemented */ - a_uint8_t reserved_op:1; - a_uint8_t soft_rate_sel_op:1; - a_uint8_t app_sel_op:1; - a_uint8_t soft_rate_ctrl_op:1; - a_uint8_t rx_los_op:1; - a_uint8_t tx_fault_op:1; - a_uint8_t tx_disable_ctrl_op:1; - a_uint8_t alarm_warning_flag_op:1; - /* - * bit 7: Optional Alarm/warning flags implemented for all monitored quantities - * bit 6: Optional soft TX_DISABLE control and monitoring implemented - * bit 5: Optional soft TX_FAULT monitoring implemented - * bit 4: Optional soft RX_LOS monitoring implemented - * bit 3: Optional soft RATE_SELECT control and monitoring implemented - * bit 2: Optional Application Select control implemented per SFF-8079 - * bit 1: Optional soft Rate Select control implemented per SFF-8431 - * bit 0: Unallocated - */ - a_uint8_t compliance_feature; /* the implemented features */ - /* - * 00h: Digital diagnostic functionality not included or undefined - * 01h: Includes functionality described in Rev 9.3 of SFF-8472. - * 02h: Includes functionality described in Rev 9.5 of SFF-8472. - * 03h: Includes functionality described in Rev 10.2 of SFF-8472. - * 04h: Includes functionality described in Rev 10.4 of SFF-8472. - * 05h~FFh: Unallocated - */ -} fal_sfp_enhanced_cfg_t; - -/* A0h offset: 95th byte for checksum extended id field */ - -/* A0h offset: 96-127 bytes Vendor Specific */ -/* A0h offset: 128-255 bytes Reserved */ - -/* A2h offset: 0-39 bytes */ -typedef struct { - a_uint16_t temp_high_alarm; /* the temperature alarm high value */ - a_uint16_t temp_low_alarm; /* the temperature alarm low value */ - a_uint16_t temp_high_warning; /* the temperature warning high value */ - a_uint16_t temp_low_warning; /* the temperature warning low value */ - a_uint16_t vol_high_alarm; /* the voltage alarm high value */ - a_uint16_t vol_low_alarm; /* the voltage alarm low value */ - a_uint16_t vol_high_warning; /* the voltage warning high value */ - a_uint16_t vol_low_warning; /* the voltage warning low value */ - a_uint16_t bias_high_alarm; /* the bias alarm high value */ - a_uint16_t bias_low_alarm; /* the bias alarm low value */ - a_uint16_t bias_high_warning; /* the bias warning high value */ - a_uint16_t bias_low_warning; /* the bias warning low value */ - a_uint16_t tx_power_high_alarm; /* the tx power alarm high value */ - a_uint16_t tx_power_low_alarm; /* the tx power alarm low value */ - a_uint16_t tx_power_high_warning;/* the tx power warning high value */ - a_uint16_t tx_power_low_warning; /* the tx power warning low value */ - a_uint16_t rx_power_high_alarm; /* the rx power alarm high value */ - a_uint16_t rx_power_low_alarm; /* the rx power alarm low value */ - a_uint16_t rx_power_high_warning;/* the rx power warning high value */ - a_uint16_t rx_power_low_warning; /* the rx power warning low value */ -} fal_sfp_internal_threshold_t; - -/* A2h offset: 40-55 bytes Reserved for future monitored quantities */ - -/* A2h offset: 56-91 bytes */ -typedef struct { - a_uint32_t rx_power4; /* Single precision floating point Rx optical power4 */ - a_uint32_t rx_power3; /* Single precision floating point Rx optical power3 */ - a_uint32_t rx_power2; /* Single precision floating point Rx optical power2 */ - a_uint32_t rx_power1; /* Single precision floating point Rx optical power1 */ - a_uint32_t rx_power0; /* Single precision floating point Rx optical power0 */ - a_uint16_t tx_bias_slope; /* Fixed decimal for laser bias current */ - a_uint16_t tx_bias_offset; /* Fixed decimal for laser bias current */ - a_uint16_t tx_power_slope; /* Fixed decimal for transmitter coupled output power */ - a_uint16_t tx_power_offset;/* Fixed decimal for transmitter coupled output power */ - a_uint16_t temp_slope; /* Fixed decimal for internal module temperature */ - a_uint16_t temp_offset; /* Fixed decimal for internal module temperature */ - a_uint16_t vol_slope; /* Fixed decimal for internal module supply voltage */ - a_uint16_t vol_offset; /* Fixed decimal for internal module supply voltage */ -} fal_sfp_cal_const_t; - -/* A2h offset: 92-94 bytes Unallocated */ - -/* A2h offset: 95th byte checsum for Base Diagnostic Fields*/ - -/* A2h offset: 96-105 bytes */ -typedef struct { - a_uint16_t cur_temp; /* Internally measured module temperature */ - a_uint16_t cur_vol; /* Internally measured supply voltage in transceiver */ - a_uint16_t tx_cur_bias; /* Internally measured TX Bias Current */ - a_uint16_t tx_cur_power; /* Measured TX output power */ - a_uint16_t rx_cur_power; /* Measured RX input power */ -} fal_sfp_realtime_diag_t; - -/* A2h offset: 106-109 bytes Unallocated */ - -/* A2h offset: 110th byte for base control/status */ -/* A2h offset: 111th byte Reserved */ -/* A2h offset: 118th byte for extend control/status */ -typedef struct { - /* Optional Status/Control Bits */ - a_uint8_t data_ready:1; - a_uint8_t rx_los:1; - a_uint8_t tx_fault:1; - a_uint8_t soft_rate_sel:1; - a_uint8_t rate_sel:1; - a_uint8_t rs_state:1; - a_uint8_t soft_tx_disable:1; - a_uint8_t tx_disable:1; - - /* - * bit7: tx disable state - * bit6: soft tx disable select - * bit5: rs state - * bit4: rate_select state - * bit3: soft rate_select select - * bit2: tx fault state - * bit1: rx_los state - * bit0: data_ready_bar state - */ - - /* Extended Control/Status Bits */ - a_uint8_t pwr_level_sel:1; - a_uint8_t pwr_level_op_state:1; - a_uint8_t reserved_1:1; - a_uint8_t soft_rs_sel:1; - a_uint8_t reserved_2:4; - /* - * bit7-4: Reserved - * bit3: soft RS select - * bit2: Reserved - * bit1: Power level operation state - * bit0: Power level select - */ -} fal_sfp_ctrl_status_t; - -/* A2h offset: 112-113 byte Alarm flag bits */ -/* A2h offset: 114-115 byte Alarm Reserved */ -/* A2h offset: 116-117 byte Warning flag bits */ -typedef struct { - /* internal diagnose exceeds high alarm level */ - a_uint8_t tx_pwr_low_alarm:1; - a_uint8_t tx_pwr_high_alarm:1; - a_uint8_t tx_bias_low_alarm:1; - a_uint8_t tx_bias_high_alarm:1; - a_uint8_t vcc_low_alarm:1; - a_uint8_t vcc_high_alarm:1; - a_uint8_t tmp_low_alarm:1; - a_uint8_t tmp_high_alarm:1; - a_uint8_t reserved_alarm:6; - a_uint8_t rx_pwr_low_alarm:1; - a_uint8_t rx_pwr_high_alarm:1; - - /* internal diagnose exceeds high warn level */ - a_uint8_t tx_pwr_low_warning:1; - a_uint8_t tx_pwr_high_warning:1; - a_uint8_t tx_bias_low_warning:1; - a_uint8_t tx_bias_high_warning:1; - a_uint8_t vcc_low_warning:1; - a_uint8_t vcc_high_warning:1; - a_uint8_t tmp_low_warning:1; - a_uint8_t tmp_high_warning:1; - a_uint8_t reserved_warning:6; - a_uint8_t rx_pwr_low_warning:1; - a_uint8_t rx_pwr_high_warning:1; - /* - * bit 15: internal temperature exceeds high alarm/warning level - * bit 14: internal temperature is below low alarm/warning level - * bit 13: internal supply voltage exceeds high alarm/warning level - * bit 12: internal supply voltage is below low alarm/warning level - * bit 11: TX Bias current exceeds high alarm/warning level - * bit 10: TX Bias current is below low alarm/warning level - * bit 09: TX output power exceeds high alarm/warning level - * bit 08: TX output power is below low alarm/warning level - * bit 07: Received Power exceeds high alarm/warning level - * bit 06: Received Power is below low alarm/warning level - * bit 05~00: reserved alarm/warning - */ -} fal_sfp_alarm_warn_flag_t; - -/* A2h offset: 119th byte Reserved */ -/* A2h offset: 120-127 byte Vendor Specific locations */ -/* A2h offset: 128-247 byte User EEPROM */ -/* A2h offset: 248-255 byte Vendor Specific locations */ - -sw_error_t -fal_sfp_eeprom_data_get(a_uint32_t dev_id, a_uint32_t port_id, fal_sfp_data_t *entry); - -sw_error_t -fal_sfp_eeprom_data_set(a_uint32_t dev_id, a_uint32_t port_id, fal_sfp_data_t *entry); - -sw_error_t -fal_sfp_device_type_get(a_uint32_t dev_id, a_uint32_t port_id, - fal_sfp_dev_type_t *sfp_id); - -sw_error_t -fal_sfp_transceiver_code_get(a_uint32_t dev_id, a_uint32_t port_id, - fal_sfp_transc_code_t *transc_code); - -sw_error_t -fal_sfp_rate_encode_get(a_uint32_t dev_id, a_uint32_t port_id, - fal_sfp_rate_encode_t *encode); - -sw_error_t -fal_sfp_link_length_get(a_uint32_t dev_id, a_uint32_t port_id, - fal_sfp_link_length_t *link_len); - -sw_error_t -fal_sfp_vendor_info_get(a_uint32_t dev_id, a_uint32_t port_id, - fal_sfp_vendor_info_t *vender_info); - -sw_error_t -fal_sfp_laser_wavelength_get(a_uint32_t dev_id, a_uint32_t port_id, - fal_sfp_laser_wavelength_t *laser_wavelen); - -sw_error_t -fal_sfp_option_get(a_uint32_t dev_id, a_uint32_t port_id, - fal_sfp_option_t *option); - -sw_error_t -fal_sfp_ctrl_rate_get(a_uint32_t dev_id, a_uint32_t port_id, - fal_sfp_rate_t *rate_limit); - -sw_error_t -fal_sfp_enhanced_cfg_get(a_uint32_t dev_id, a_uint32_t port_id, - fal_sfp_enhanced_cfg_t *enhanced_feature); - -sw_error_t -fal_sfp_diag_internal_threshold_get(a_uint32_t dev_id, a_uint32_t port_id, - fal_sfp_internal_threshold_t *threshold); - -sw_error_t -fal_sfp_diag_extenal_calibration_const_get(a_uint32_t dev_id, a_uint32_t port_id, - fal_sfp_cal_const_t *cal_const); - -sw_error_t -fal_sfp_diag_realtime_get(a_uint32_t dev_id, a_uint32_t port_id, - fal_sfp_realtime_diag_t *real_diag); - -sw_error_t -fal_sfp_diag_ctrl_status_get(a_uint32_t dev_id, a_uint32_t port_id, - fal_sfp_ctrl_status_t *ctrl_status); - -sw_error_t -fal_sfp_diag_alarm_warning_flag_get(a_uint32_t dev_id, a_uint32_t port_id, - fal_sfp_alarm_warn_flag_t *alarm_warn_flag); - -sw_error_t -fal_sfp_checkcode_get(a_uint32_t dev_id, a_uint32_t port_id, - fal_sfp_cc_type_t cc_type, a_uint8_t *ccode); - -#ifdef __cplusplus -} -#endif /* __cplusplus */ -#endif /* _FAL_SFP_H_ */ -/** - * @} - */ diff --git a/feeds/ipq807x/qca-ssdk/src/include/fal/fal_shaper.h b/feeds/ipq807x/qca-ssdk/src/include/fal/fal_shaper.h deleted file mode 100755 index e266eeb02..000000000 --- a/feeds/ipq807x/qca-ssdk/src/include/fal/fal_shaper.h +++ /dev/null @@ -1,163 +0,0 @@ -/* - * Copyright (c) 2016-2018, The Linux Foundation. All rights reserved. - * Permission to use, copy, modify, and/or distribute this software for - * any purpose with or without fee is hereby granted, provided that the - * above copyright notice and this permission notice appear in all copies. - * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES - * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR - * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES - * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN - * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT - * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. - */ - - -/** - * @defgroup fal_shaper FAL_SHAPER - * @{ - */ -#ifndef _FAL_SHAPER_H_ -#define _FAL_SHAPER_H_ - -#ifdef __cplusplus -extern "C" { -#endif /* __cplusplus */ - -#include "sw.h" -#include "fal/fal_type.h" - -typedef enum -{ - FAL_IPG_PREAMBLE_FRAME_CRC = 0, /* IPG + Preamble + Frame + CRC */ - FAL_FRAME_CRC, /* Frame + CRC */ - FAL_L3_EXCLUDE_CRC /* after Ethernet type excude CRC*/ -} fal_shaper_frame_mode_t; - -typedef struct -{ - a_bool_t couple_en; /* two buckets coupled enable or disable*/ - a_uint32_t meter_unit; /* 0 byte based, 1 frame based */ - a_bool_t c_shaper_en; /* egress shaer C bucket enable or disable */ - a_uint32_t cbs; /* committed burst size */ - a_uint32_t cir; /* committed information rate */ - a_bool_t e_shaper_en; /* egress shaper E bucket enable or disable */ - a_uint32_t ebs; /* excess burst size */ - a_uint32_t eir; /* excess information rate */ - fal_shaper_frame_mode_t shaper_frame_mode; /* shaper frame mode */ -} fal_shaper_config_t; - -typedef struct -{ - a_bool_t c_token_number_negative_en; /* C token is negative or not */ - a_uint32_t c_token_number; /* C token value */ - a_bool_t e_token_number_negative_en; /* E token is negative or not */ - a_uint32_t e_token_number; /* E token value */ -} fal_shaper_token_number_t; - -enum -{ - FUNC_ADPT_FLOW_SHAPER_SET = 0, - FUNC_ADPT_QUEUE_SHAPER_GET, - FUNC_ADPT_QUEUE_SHAPER_TOKEN_NUMBER_SET, - FUNC_ADPT_PORT_SHAPER_GET, - FUNC_ADPT_FLOW_SHAPER_TIME_SLOT_GET, - FUNC_ADPT_PORT_SHAPER_TIME_SLOT_GET, - FUNC_ADPT_FLOW_SHAPER_TIME_SLOT_SET, - FUNC_ADPT_PORT_SHAPER_TOKEN_NUMBER_SET, - FUNC_ADPT_QUEUE_SHAPER_TOKEN_NUMBER_GET, - FUNC_ADPT_QUEUE_SHAPER_TIME_SLOT_GET, - FUNC_ADPT_PORT_SHAPER_TOKEN_NUMBER_GET, - FUNC_ADPT_FLOW_SHAPER_TOKEN_NUMBER_SET, - FUNC_ADPT_FLOW_SHAPER_TOKEN_NUMBER_GET, - FUNC_ADPT_PORT_SHAPER_SET, - FUNC_ADPT_PORT_SHAPER_TIME_SLOT_SET, - FUNC_ADPT_FLOW_SHAPER_GET, - FUNC_ADPT_QUEUE_SHAPER_SET, - FUNC_ADPT_QUEUE_SHAPER_TIME_SLOT_SET, - FUNC_ADPT_SHAPER_IPG_PREAMBLE_LENGTH_SET, - FUNC_ADPT_SHAPER_IPG_PREAMBLE_LENGTH_GET, -}; - -sw_error_t -fal_queue_shaper_token_number_set(a_uint32_t dev_id,a_uint32_t queue_id, - fal_shaper_token_number_t *token_number); - -sw_error_t -fal_flow_shaper_token_number_set(a_uint32_t dev_id, a_uint32_t flow_id, - fal_shaper_token_number_t *token_number); - -sw_error_t -fal_port_shaper_token_number_set(a_uint32_t dev_id, fal_port_t port_id, - fal_shaper_token_number_t *token_number); - -sw_error_t -fal_port_shaper_timeslot_set(a_uint32_t dev_id, a_uint32_t timeslot); - -sw_error_t -fal_queue_shaper_timeslot_set(a_uint32_t dev_id, a_uint32_t timeslot); - -sw_error_t -fal_flow_shaper_timeslot_set(a_uint32_t dev_id, a_uint32_t timeslot); - -sw_error_t -fal_shaper_ipg_preamble_length_set(a_uint32_t dev_id, a_uint32_t ipg_pre_length); - -sw_error_t -fal_port_shaper_set(a_uint32_t dev_id, fal_port_t port_id, - fal_shaper_config_t * shaper); - -sw_error_t -fal_queue_shaper_set(a_uint32_t dev_id,a_uint32_t queue_id, - fal_shaper_config_t * shaper); - -sw_error_t -fal_queue_shaper_get(a_uint32_t dev_id, a_uint32_t queue_id, - fal_shaper_config_t * shaper); - -sw_error_t -fal_flow_shaper_set(a_uint32_t dev_id, a_uint32_t flow_id, - fal_shaper_config_t * shaper); - -#ifndef IN_SHAPER_MINI -sw_error_t -fal_port_shaper_get(a_uint32_t dev_id, fal_port_t port_id, - fal_shaper_config_t * shaper); - -sw_error_t -fal_flow_shaper_get(a_uint32_t dev_id, a_uint32_t flow_id, - fal_shaper_config_t * shaper); - -sw_error_t -fal_queue_shaper_token_number_get(a_uint32_t dev_id, a_uint32_t queue_id, - fal_shaper_token_number_t *token_number); - -sw_error_t -fal_flow_shaper_token_number_get(a_uint32_t dev_id, a_uint32_t flow_id, - fal_shaper_token_number_t *token_number); - -sw_error_t -fal_port_shaper_token_number_get(a_uint32_t dev_id, fal_port_t port_id, - fal_shaper_token_number_t *token_number); - -sw_error_t -fal_port_shaper_timeslot_get(a_uint32_t dev_id, a_uint32_t *timeslot); - -sw_error_t -fal_queue_shaper_timeslot_get(a_uint32_t dev_id, a_uint32_t *timeslot); - -sw_error_t -fal_flow_shaper_timeslot_get(a_uint32_t dev_id, a_uint32_t *timeslot); - -sw_error_t -fal_shaper_ipg_preamble_length_get(a_uint32_t dev_id, a_uint32_t *ipg_pre_length); -#endif - - -#ifdef __cplusplus -} -#endif /* __cplusplus */ -#endif /* _FAL_SHAPER_H_ */ -/** - * @} - */ diff --git a/feeds/ipq807x/qca-ssdk/src/include/fal/fal_stp.h b/feeds/ipq807x/qca-ssdk/src/include/fal/fal_stp.h deleted file mode 100755 index 9d87a9bdc..000000000 --- a/feeds/ipq807x/qca-ssdk/src/include/fal/fal_stp.h +++ /dev/null @@ -1,75 +0,0 @@ -/* - * Copyright (c) 2012, 2016-2018, The Linux Foundation. All rights reserved. - * Permission to use, copy, modify, and/or distribute this software for - * any purpose with or without fee is hereby granted, provided that the - * above copyright notice and this permission notice appear in all copies. - * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES - * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR - * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES - * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN - * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT - * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. - */ - - -/** - * @defgroup fal_stp FAL_STP - * @{ - */ -#ifndef _FAL_STP_H_ -#define _FAL_STP_H_ - -#ifdef __cplusplus -extern "C" { -#endif /* __cplusplus */ - -#include "sw.h" -#include "fal/fal_type.h" - -#define FAL_SINGLE_STP_ID 0 - - /** - @brief This enum defines port state for spanning tree. - */ - typedef enum { - FAL_STP_DISABLED = 0, /**< disable state*/ - FAL_STP_BLOCKING, /**< blocking state*/ - FAL_STP_LISTENING, /**< listening state*/ - FAL_STP_LEARNING, /**< learning state*/ - FAL_STP_FORWARDING, /**< forwarding state*/ - FAL_STP_STATE_BUTT - } - fal_stp_state_t; - -/* - * These two #define lines are used to keep them for the - * compatibility of previous project. - */ -#define FAL_STP_BLOKING FAL_STP_BLOCKING -#define FAL_STP_FARWARDING FAL_STP_FORWARDING - -enum { - FUNC_STP_PORT_STATE_SET = 0, - FUNC_STP_PORT_STATE_GET, -}; - - sw_error_t - fal_stp_port_state_set(a_uint32_t dev_id, a_uint32_t st_id, - fal_port_t port_id, fal_stp_state_t state); - - - - sw_error_t - fal_stp_port_state_get(a_uint32_t dev_id, a_uint32_t st_id, - fal_port_t port_id, fal_stp_state_t * state); - - -#ifdef __cplusplus -} -#endif /* __cplusplus */ -#endif /* _FAL_STP_H_ */ - -/** - * @} - */ diff --git a/feeds/ipq807x/qca-ssdk/src/include/fal/fal_trunk.h b/feeds/ipq807x/qca-ssdk/src/include/fal/fal_trunk.h deleted file mode 100644 index d25296159..000000000 --- a/feeds/ipq807x/qca-ssdk/src/include/fal/fal_trunk.h +++ /dev/null @@ -1,84 +0,0 @@ -/* - * Copyright (c) 2012, 2016-2018, 2020, The Linux Foundation. All rights reserved. - * Permission to use, copy, modify, and/or distribute this software for - * any purpose with or without fee is hereby granted, provided that the - * above copyright notice and this permission notice appear in all copies. - * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES - * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR - * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES - * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN - * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT - * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. - */ - - -/** - * @defgroup fal_trunk FAL_TRUNK - * @{ - */ -#ifndef _FAL_TRUNK_H_ -#define _FAL_TRUNK_H_ - -#ifdef __cplusplus -extern "C" { -#endif /* __cplusplus */ - -#include "sw.h" -#include "fal/fal_type.h" - - -#define FAL_TRUNK_HASH_KEY_DA 0x1 -#define FAL_TRUNK_HASH_KEY_SA 0x2 -#define FAL_TRUNK_HASH_KEY_DIP 0x4 -#define FAL_TRUNK_HASH_KEY_SIP 0x8 -#define FAL_TRUNK_HASH_KEY_SRC_PORT 0x10 -#define FAL_TRUNK_HASH_KEY_L4_SRC_PORT 0x20 -#define FAL_TRUNK_HASH_KEY_L4_DST_PORT 0x40 -#define FAL_TRUNK_HASH_KEY_UDF0 0x80 -#define FAL_TRUNK_HASH_KEY_UDF1 0x100 -#define FAL_TRUNK_HASH_KEY_UDF2 0x200 -#define FAL_TRUNK_HASH_KEY_UDF3 0x400 -#define FAL_TRUNK_GROUP_MAX_MEMEBER 8 - -enum { - FUNC_TRUNK_GROUP_SET = 0, - FUNC_TRUNK_GROUP_GET, - FUNC_TRUNK_HASH_MODE_SET, - FUNC_TRUNK_HASH_MODE_GET, - FUNC_TRUNK_FAILOVER_ENABLE, - FUNC_TRUNK_FAILOVER_STATUS_GET, -}; - -sw_error_t -fal_trunk_group_set(a_uint32_t dev_id, a_uint32_t trunk_id, - a_bool_t enable, fal_pbmp_t member); -sw_error_t -fal_trunk_group_get(a_uint32_t dev_id, a_uint32_t trunk_id, - a_bool_t * enable, fal_pbmp_t * member); -sw_error_t -fal_trunk_hash_mode_set(a_uint32_t dev_id, a_uint32_t hash_mode); - -sw_error_t -fal_trunk_hash_mode_get(a_uint32_t dev_id, a_uint32_t * hash_mode); - -sw_error_t -fal_trunk_manipulate_sa_set(a_uint32_t dev_id, fal_mac_addr_t * addr); - -sw_error_t -fal_trunk_manipulate_sa_get(a_uint32_t dev_id, fal_mac_addr_t * addr); - -sw_error_t -fal_trunk_failover_enable(a_uint32_t dev_id, a_bool_t failover); - -sw_error_t -fal_trunk_failover_status_get(a_uint32_t dev_id, a_bool_t * failover); - -#ifdef __cplusplus -} -#endif /* __cplusplus */ -#endif /* _FAL_TRUNK_H_ */ - -/** - * @} - */ diff --git a/feeds/ipq807x/qca-ssdk/src/include/fal/fal_type.h b/feeds/ipq807x/qca-ssdk/src/include/fal/fal_type.h deleted file mode 100755 index 0f680a47b..000000000 --- a/feeds/ipq807x/qca-ssdk/src/include/fal/fal_type.h +++ /dev/null @@ -1,137 +0,0 @@ -/* - * Copyright (c) 2012, 2016-2017, The Linux Foundation. All rights reserved. - * Permission to use, copy, modify, and/or distribute this software for - * any purpose with or without fee is hereby granted, provided that the - * above copyright notice and this permission notice appear in all copies. - * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES - * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR - * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES - * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN - * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT - * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. - */ - - -/** - * @defgroup fal_type FAL_TYPE - * @{ - */ -#ifndef _FAL_TYPE_H_ -#define _FAL_TYPE_H_ - -#ifdef __cplusplus -extern "C" { -#endif /* __cplusplus */ - - typedef a_uint32_t fal_port_t; - -/*fal_port_t definition, - bit31-bit24: port_type, 0-physical port, 1-trunk port, 2-virtual port - bit23-bit0: physical port id or trunk id or virtual port id*/ -#define FAL_PORT_TYPE_PPORT 0 -#define FAL_PORT_TYPE_TRUNK 1 -#define FAL_PORT_TYPE_VPORT 2 - -#define FAL_PORT_ID_TYPE(port_id) (((port_id)>>24)&0xff) -#define FAL_PORT_ID_VALUE(port_id) ((port_id)&0xffffff) -#define FAL_PORT_ID(type, value) (((type)<<24)|(value)) - -#define FAL_IS_PPORT(port_id) (((FAL_PORT_ID_TYPE(port_id))==FAL_PORT_TYPE_PPORT)?1:0) -#define FAL_IS_TRUNK(port_id) (((FAL_PORT_ID_TYPE(port_id))==FAL_PORT_TYPE_TRUNK)?1:0) -#define FAL_IS_VPORT(port_id) (((FAL_PORT_ID_TYPE(port_id))==FAL_PORT_TYPE_VPORT)?1:0) - - -#if (SW_MAX_NR_PORT <= 32) - typedef a_uint32_t fal_pbmp_t; -#else - typedef a_uint64_t fal_pbmp_t; -#endif - - typedef struct - { - a_uint8_t uc[6]; - } fal_mac_addr_t; - - typedef a_uint32_t fal_ip4_addr_t; - - typedef struct - { - a_uint32_t ul[4]; - } fal_ip6_addr_t; - - /** - @brief This enum defines several forwarding command type. - * Field description: - FAL_MAC_FRWRD - packets are normally forwarded - FAL_MAC_DROP - packets are dropped - FAL_MAC_CPY_TO_CPU - packets are copyed to cpu - FAL_MAC_RDT_TO_CPU - packets are redirected to cpu - */ - typedef enum - { - FAL_MAC_FRWRD = 0, /**< packets are normally forwarded */ - FAL_MAC_DROP, /**< packets are dropped */ - FAL_MAC_CPY_TO_CPU, /**< packets are copyed to cpu */ - FAL_MAC_RDT_TO_CPU /**< packets are redirected to cpu */ - } fal_fwd_cmd_t; - - typedef enum - { - FAL_BYTE_BASED = 0, - FAL_FRAME_BASED, - FAL_RATE_MODE_BUTT - } fal_traffic_unit_t; - - typedef a_uint32_t fal_queue_t; - -#define FAL_SVL_FID 0xffff - - - /** - @brief This enum defines packets transmitted out vlan tagged mode. - */ - typedef enum - { - FAL_EG_UNMODIFIED = 0, /**< egress transmit packets unmodified */ - FAL_EG_UNTAGGED, /**< egress transmit packets without vlan tag*/ - FAL_EG_TAGGED, /**< egress transmit packets with vlan tag */ - FAL_EG_HYBRID, /**< egress transmit packets in hybrid tag mode */ - FAL_EG_UNTOUCHED, - FAL_EG_MODE_BUTT - } fal_pt_1q_egmode_t; - -#define FAL_NEXT_ENTRY_FIRST_ID 0xffffffff - - typedef struct{ - a_uint32_t reg_count; - a_uint32_t reg_base; - a_uint32_t reg_end; - a_uint32_t reg_value[256]; - a_int8_t reg_name[32]; - }fal_reg_dump_t; - - typedef struct{ - a_uint32_t reg_count; - a_uint32_t reg_addr[32]; - a_uint32_t reg_value[32]; - a_int8_t reg_name[32]; - }fal_debug_reg_dump_t; - -typedef struct{ - a_uint32_t phy_count; - a_uint32_t phy_base; - a_uint32_t phy_end; - a_uint16_t phy_value[256]; - a_int8_t phy_name[32]; -}fal_phy_dump_t; - - - -#ifdef __cplusplus -} -#endif /* __cplusplus */ -#endif /* _FAL_TYPE_H_ */ -/** - * @} - */ diff --git a/feeds/ipq807x/qca-ssdk/src/include/fal/fal_uk_if.h b/feeds/ipq807x/qca-ssdk/src/include/fal/fal_uk_if.h deleted file mode 100755 index faad2f2b1..000000000 --- a/feeds/ipq807x/qca-ssdk/src/include/fal/fal_uk_if.h +++ /dev/null @@ -1,42 +0,0 @@ -/* - * Copyright (c) 2012,2018, The Linux Foundation. All rights reserved. - * Permission to use, copy, modify, and/or distribute this software for - * any purpose with or without fee is hereby granted, provided that the - * above copyright notice and this permission notice appear in all copies. - * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES - * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR - * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES - * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN - * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT - * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. - */ - - - -#ifndef _FAL_UK_IF_H_ -#define _FAL_UK_IF_H_ - -#ifdef __cplusplus -extern "C" { -#endif /* __cplusplus */ - -#include "sw.h" -#include "fal/fal_type.h" -#include "ssdk_init.h" - - sw_error_t - sw_uk_exec(a_uint32_t api_id, ...); - - sw_error_t - ssdk_init(a_uint32_t dev_id, ssdk_init_cfg * cfg); - - sw_error_t - ssdk_cleanup(void); - -#ifdef __cplusplus -} -#endif /* __cplusplus */ -#endif /* _FAL_UK_IF_H_ */ - - diff --git a/feeds/ipq807x/qca-ssdk/src/include/fal/fal_vlan.h b/feeds/ipq807x/qca-ssdk/src/include/fal/fal_vlan.h deleted file mode 100755 index 6386e05e3..000000000 --- a/feeds/ipq807x/qca-ssdk/src/include/fal/fal_vlan.h +++ /dev/null @@ -1,129 +0,0 @@ -/* - * Copyright (c) 2012,2018, The Linux Foundation. All rights reserved. - * Permission to use, copy, modify, and/or distribute this software for - * any purpose with or without fee is hereby granted, provided that the - * above copyright notice and this permission notice appear in all copies. - * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES - * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR - * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES - * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN - * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT - * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. - */ - - -/** - * @defgroup fal_vlan FAL_VLAN - * @{ - */ -#ifndef _FAL_VLAN_H -#define _FAL_VLAN_H - -#ifdef __cplusplus -extern "C" { -#endif /* __cplusplus */ - -#include "sw.h" -#include "fal/fal_type.h" - - /** - @brief This structure defines vlan entry. - */ - typedef struct - { - a_uint16_t vid; /**< vlan entry id */ - a_uint16_t fid; /**< filter data base id*/ - fal_pbmp_t mem_ports; /**< member port bit map */ - fal_pbmp_t tagged_ports; /**< bit map of tagged infomation for member port*/ - fal_pbmp_t untagged_ports; /**< bit map of untagged infomation for member port*/ - fal_pbmp_t unmodify_ports;/**< bit map of unmodified infomation for member port*/ - fal_pbmp_t u_ports; - a_bool_t learn_dis; /**< disable address learning*/ - a_bool_t vid_pri_en; /**< enable 802.1p*/ - a_uint8_t vid_pri; /**< vlaue of 802.1p when enable vid_pri_en*/ - } fal_vlan_t; - - - sw_error_t - fal_vlan_entry_append(a_uint32_t dev_id, fal_vlan_t * vlan_entry); - - - - sw_error_t - fal_vlan_create(a_uint32_t dev_id, a_uint32_t vlan_id); - - - - sw_error_t - fal_vlan_next(a_uint32_t dev_id, a_uint32_t vlan_id, fal_vlan_t * p_vlan); - - - - sw_error_t - fal_vlan_find(a_uint32_t dev_id, a_uint32_t vlan_id, fal_vlan_t * p_vlan); - - - - sw_error_t - fal_vlan_member_update(a_uint32_t dev_id, a_uint32_t vlan_id, - fal_pbmp_t member, fal_pbmp_t u_member); - - - - sw_error_t - fal_vlan_delete(a_uint32_t dev_id, a_uint32_t vlan_id); - - - - sw_error_t - fal_vlan_reset(a_uint32_t dev_id); - - - sw_error_t - fal_vlan_flush(a_uint32_t dev_id); - - - sw_error_t - fal_vlan_init(a_uint32_t dev_id); - - - sw_error_t - fal_vlan_cleanup(void); - - - sw_error_t - fal_vlan_fid_set(a_uint32_t dev_id, a_uint32_t vlan_id, a_uint32_t fid); - - - sw_error_t - fal_vlan_fid_get(a_uint32_t dev_id, a_uint32_t vlan_id, a_uint32_t * fid); - - - sw_error_t - fal_vlan_member_add(a_uint32_t dev_id, a_uint32_t vlan_id, - fal_port_t port_id, fal_pt_1q_egmode_t port_info); - - - sw_error_t - fal_vlan_member_del(a_uint32_t dev_id, a_uint32_t vlan_id, fal_port_t port_id); - - - sw_error_t - fal_vlan_learning_state_set(a_uint32_t dev_id, a_uint32_t vlan_id, - a_bool_t enable); - - - sw_error_t - fal_vlan_learning_state_get(a_uint32_t dev_id, a_uint32_t vlan_id, - a_bool_t * enable); - - -#ifdef __cplusplus -} -#endif /* __cplusplus */ - -#endif /* _FAL_VLAN_H */ -/** - * @} - */ diff --git a/feeds/ipq807x/qca-ssdk/src/include/fal/fal_vsi.h b/feeds/ipq807x/qca-ssdk/src/include/fal/fal_vsi.h deleted file mode 100755 index 2e4a42e59..000000000 --- a/feeds/ipq807x/qca-ssdk/src/include/fal/fal_vsi.h +++ /dev/null @@ -1,137 +0,0 @@ -/* - * Copyright (c) 2016-2018, The Linux Foundation. All rights reserved. - * Permission to use, copy, modify, and/or distribute this software for - * any purpose with or without fee is hereby granted, provided that the - * above copyright notice and this permission notice appear in all copies. - * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES - * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR - * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES - * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN - * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT - * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. - */ - - -/** - * @defgroup fal_stp FAL_VSI - * @{ - */ -#ifndef _FAL_VSI_H_ -#define _FAL_VSI_H_ - -#ifdef __cplusplus -extern "C" { -#endif /* __cplusplus */ - -#include "sw.h" -#include "fal/fal_type.h" - -#define FAL_VSI_INVALID 0xffff -#define FAL_VLAN_INVALID 0xffff -#define FAL_VSI_MAX 31 -#define FAL_VLAN_MAX 4095 - -typedef struct{ - a_uint32_t lrn_en; /*0: disable new address learn, 1: enable new address learn*/ - fal_fwd_cmd_t action;/*0:forward, 1:drop, 2: copy to CPU, 3: redirect to CPU*/ -}fal_vsi_newaddr_lrn_t; - -typedef struct{ - a_uint32_t stamove_en;/*0:disable station move, 1: enable station move*/ - fal_fwd_cmd_t action;/*0:forward, 1:drop, 2: copy to CPU, 3: redirect to CPU*/ -}fal_vsi_stamove_t; - -typedef struct{ - a_uint32_t member_ports;/*VSI member ports for all packets*/ - a_uint32_t uuc_ports;/*VSI member ports for unknown unicast*/ - a_uint32_t umc_ports;/*VSI member ports for unknown multicast*/ - a_uint32_t bc_ports;/*VSI member ports for broadcast*/ -}fal_vsi_member_t; - - -typedef struct -{ - a_uint32_t rx_packet_counter; - a_uint64_t rx_byte_counter; - a_uint32_t tx_packet_counter; - a_uint64_t tx_byte_counter; - a_uint32_t fwd_packet_counter; - a_uint64_t fwd_byte_counter; - a_uint32_t drop_packet_counter; - a_uint64_t drop_byte_counter; -}fal_vsi_counter_t; - - -enum{ - FUNC_PORT_VLAN_VSI_SET, - FUNC_PORT_VLAN_VSI_GET, - FUNC_PORT_VSI_SET, - FUNC_PORT_VSI_GET, - FUNC_VSI_STAMOVE_SET, - FUNC_VSI_STAMOVE_GET, - FUNC_VSI_NEWADDR_LRN_SET, - FUNC_VSI_NEWADDR_LRN_GET, - FUNC_VSI_MEMBER_SET, - FUNC_VSI_MEMBER_GET, - FUNC_VSI_COUNTER_GET, - FUNC_VSI_COUNTER_CLEANUP, -}; - -sw_error_t -fal_vsi_alloc(a_uint32_t dev_id, a_uint32_t *vsi); - -sw_error_t -fal_vsi_free(a_uint32_t dev_id, a_uint32_t vsi); - -sw_error_t -fal_port_vsi_set(a_uint32_t dev_id, fal_port_t port_id, a_uint32_t vsi_id); - -#ifndef IN_VSI_MINI -sw_error_t -fal_port_vsi_get(a_uint32_t dev_id, fal_port_t port_id, a_uint32_t *vsi_id); - -sw_error_t -fal_vsi_stamove_get(a_uint32_t dev_id, a_uint32_t vsi_id, fal_vsi_stamove_t *stamove); - -sw_error_t -fal_vsi_newaddr_lrn_get(a_uint32_t dev_id, a_uint32_t vsi_id, fal_vsi_newaddr_lrn_t *newaddr_lrn); - -sw_error_t -fal_vsi_counter_get(a_uint32_t dev_id, a_uint32_t vsi_id, fal_vsi_counter_t *counter); - -sw_error_t -fal_vsi_counter_cleanup(a_uint32_t dev_id, a_uint32_t vsi_id); -#endif - -sw_error_t -fal_port_vlan_vsi_set(a_uint32_t dev_id, fal_port_t port_id, a_uint32_t stag_vid, a_uint32_t ctag_vid, a_uint32_t vsi_id); - -sw_error_t -fal_port_vlan_vsi_get(a_uint32_t dev_id, fal_port_t port_id, a_uint32_t stag_vid, a_uint32_t ctag_vid, a_uint32_t *vsi_id); - -sw_error_t -fal_vsi_tbl_dump(a_uint32_t dev_id); - -sw_error_t -fal_vsi_newaddr_lrn_set(a_uint32_t dev_id, a_uint32_t vsi_id, fal_vsi_newaddr_lrn_t *newaddr_lrn); - -sw_error_t -fal_vsi_stamove_set(a_uint32_t dev_id, a_uint32_t vsi_id, fal_vsi_stamove_t *stamove); - -sw_error_t -fal_vsi_member_set(a_uint32_t dev_id, a_uint32_t vsi_id, fal_vsi_member_t *vsi_member); - -sw_error_t -fal_vsi_member_get(a_uint32_t dev_id, a_uint32_t vsi_id, fal_vsi_member_t *vsi_member); - - -#ifdef __cplusplus -} -#endif /* __cplusplus */ -#endif /* _FAL_VSI_H_ */ - -/** - * @} - */ - diff --git a/feeds/ipq807x/qca-ssdk/src/include/hsl/athena/athena_api.h b/feeds/ipq807x/qca-ssdk/src/include/hsl/athena/athena_api.h deleted file mode 100755 index 543cab60d..000000000 --- a/feeds/ipq807x/qca-ssdk/src/include/hsl/athena/athena_api.h +++ /dev/null @@ -1,198 +0,0 @@ -/* - * Copyright (c) 2012, The Linux Foundation. All rights reserved. - * Permission to use, copy, modify, and/or distribute this software for - * any purpose with or without fee is hereby granted, provided that the - * above copyright notice and this permission notice appear in all copies. - * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES - * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR - * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES - * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN - * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT - * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. - */ - - - -#ifndef _ATHENA_API_H_ -#define _ATHENA_API_H_ - -#ifdef __cplusplus -extern "C" { -#endif /* __cplusplus */ - -#ifdef IN_PORTCONTROL -#define PORTCONTROL_API \ - SW_API_DEF(SW_API_PT_DUPLEX_GET, athena_port_duplex_get), \ - SW_API_DEF(SW_API_PT_DUPLEX_SET, athena_port_duplex_set), \ - SW_API_DEF(SW_API_PT_SPEED_GET, athena_port_speed_get), \ - SW_API_DEF(SW_API_PT_SPEED_SET, athena_port_speed_set), \ - SW_API_DEF(SW_API_PT_AN_GET, athena_port_autoneg_status_get), \ - SW_API_DEF(SW_API_PT_AN_ENABLE, athena_port_autoneg_enable), \ - SW_API_DEF(SW_API_PT_AN_RESTART, athena_port_autoneg_restart), \ - SW_API_DEF(SW_API_PT_AN_ADV_GET, athena_port_autoneg_adv_get), \ - SW_API_DEF(SW_API_PT_AN_ADV_SET, athena_port_autoneg_adv_set), \ - SW_API_DEF(SW_API_PT_IGMPS_MODE_SET, athena_port_igmps_status_set), \ - SW_API_DEF(SW_API_PT_IGMPS_MODE_GET, athena_port_igmps_status_get), \ - SW_API_DEF(SW_API_PT_POWERSAVE_SET, athena_port_powersave_set), \ - SW_API_DEF(SW_API_PT_POWERSAVE_GET, athena_port_powersave_get), \ - SW_API_DEF(SW_API_PT_HIBERNATE_SET, athena_port_hibernate_set), \ - SW_API_DEF(SW_API_PT_HIBERNATE_GET, athena_port_hibernate_get), - - -#define PORTCONTROL_API_PARAM \ - SW_API_DESC(SW_API_PT_DUPLEX_GET) \ - SW_API_DESC(SW_API_PT_DUPLEX_SET) \ - SW_API_DESC(SW_API_PT_SPEED_GET) \ - SW_API_DESC(SW_API_PT_SPEED_SET) \ - SW_API_DESC(SW_API_PT_AN_GET) \ - SW_API_DESC(SW_API_PT_AN_ENABLE) \ - SW_API_DESC(SW_API_PT_AN_RESTART) \ - SW_API_DESC(SW_API_PT_AN_ADV_GET) \ - SW_API_DESC(SW_API_PT_AN_ADV_SET) \ - SW_API_DESC(SW_API_PT_IGMPS_MODE_SET) \ - SW_API_DESC(SW_API_PT_IGMPS_MODE_GET) \ - SW_API_DESC(SW_API_PT_POWERSAVE_SET) \ - SW_API_DESC(SW_API_PT_POWERSAVE_GET) \ - SW_API_DESC(SW_API_PT_HIBERNATE_SET) \ - SW_API_DESC(SW_API_PT_HIBERNATE_GET) -#else -#define PORTCONTROL_API -#define PORTCONTROL_API_PARAM -#endif - -#ifdef IN_VLAN -#define VLAN_API \ - SW_API_DEF(SW_API_VLAN_ADD, athena_vlan_create), \ - SW_API_DEF(SW_API_VLAN_DEL, athena_vlan_delete), \ - SW_API_DEF(SW_API_VLAN_MEM_UPDATE, athena_vlan_member_update), \ - SW_API_DEF(SW_API_VLAN_FIND, athena_vlan_find), \ - SW_API_DEF(SW_API_VLAN_NEXT, athena_vlan_next), \ - SW_API_DEF(SW_API_VLAN_APPEND, athena_vlan_entry_append), - -#define VLAN_API_PARAM \ - SW_API_DESC(SW_API_VLAN_ADD) \ - SW_API_DESC(SW_API_VLAN_DEL) \ - SW_API_DESC(SW_API_VLAN_MEM_UPDATE) \ - SW_API_DESC(SW_API_VLAN_FIND) \ - SW_API_DESC(SW_API_VLAN_NEXT) \ - SW_API_DESC(SW_API_VLAN_APPEND) -#else -#define VLAN_API -#define VLAN_API_PARAM -#endif - -#ifdef IN_PORTVLAN -#define PORTVLAN_API \ - SW_API_DEF(SW_API_PT_ING_MODE_GET, athena_port_1qmode_get), \ - SW_API_DEF(SW_API_PT_ING_MODE_SET, athena_port_1qmode_set), \ - SW_API_DEF(SW_API_PT_EG_MODE_GET, athena_port_egvlanmode_get), \ - SW_API_DEF(SW_API_PT_EG_MODE_SET, athena_port_egvlanmode_set), \ - SW_API_DEF(SW_API_PT_VLAN_MEM_ADD, athena_portvlan_member_add), \ - SW_API_DEF(SW_API_PT_VLAN_MEM_DEL, athena_portvlan_member_del), \ - SW_API_DEF(SW_API_PT_VLAN_MEM_UPDATE, athena_portvlan_member_update), \ - SW_API_DEF(SW_API_PT_VLAN_MEM_GET, athena_portvlan_member_get), \ - -#define PORTVLAN_API_PARAM \ - SW_API_DESC(SW_API_PT_ING_MODE_GET) \ - SW_API_DESC(SW_API_PT_ING_MODE_SET) \ - SW_API_DESC(SW_API_PT_EG_MODE_GET) \ - SW_API_DESC(SW_API_PT_EG_MODE_SET) \ - SW_API_DESC(SW_API_PT_VLAN_MEM_ADD) \ - SW_API_DESC(SW_API_PT_VLAN_MEM_DEL) \ - SW_API_DESC(SW_API_PT_VLAN_MEM_UPDATE) \ - SW_API_DESC(SW_API_PT_VLAN_MEM_GET) -#else -#define PORTVLAN_API -#define PORTVLAN_API_PARAM -#endif - -#ifdef IN_FDB -#define FDB_API \ - SW_API_DEF(SW_API_FDB_ADD, athena_fdb_add), \ - SW_API_DEF(SW_API_FDB_DELALL, athena_fdb_del_all), \ - SW_API_DEF(SW_API_FDB_DELPORT,athena_fdb_del_by_port), \ - SW_API_DEF(SW_API_FDB_DELMAC, athena_fdb_del_by_mac), \ - SW_API_DEF(SW_API_FDB_FIRST, athena_fdb_first), \ - SW_API_DEF(SW_API_FDB_NEXT, athena_fdb_next), - -#define FDB_API_PARAM \ - SW_API_DESC(SW_API_FDB_ADD) \ - SW_API_DESC(SW_API_FDB_DELALL) \ - SW_API_DESC(SW_API_FDB_DELPORT) \ - SW_API_DESC(SW_API_FDB_DELMAC) \ - SW_API_DESC(SW_API_FDB_FIRST) \ - SW_API_DESC(SW_API_FDB_NEXT) -#else -#define FDB_API -#define FDB_API_PARAM -#endif - -#ifdef IN_MIB -#define MIB_API \ - SW_API_DEF(SW_API_PT_MIB_GET, athena_get_mib_info), - -#define MIB_API_PARAM \ - SW_API_DESC(SW_API_PT_MIB_GET) -#else -#define MIB_API -#define MIB_API_PARAM -#endif - -#define REG_API \ - SW_API_DEF(SW_API_PHY_GET, athena_phy_get), \ - SW_API_DEF(SW_API_PHY_SET, athena_phy_set), \ - SW_API_DEF(SW_API_REG_GET, athena_reg_get), \ - SW_API_DEF(SW_API_REG_SET, athena_reg_set), \ - SW_API_DEF(SW_API_REG_FIELD_GET, athena_reg_field_get), \ - SW_API_DEF(SW_API_REG_FIELD_SET, athena_reg_field_set), - -#define REG_API_PARAM \ - SW_API_DESC(SW_API_PHY_GET) \ - SW_API_DESC(SW_API_PHY_SET) \ - SW_API_DESC(SW_API_REG_GET) \ - SW_API_DESC(SW_API_REG_SET) \ - SW_API_DESC(SW_API_REG_FIELD_GET) \ - SW_API_DESC(SW_API_REG_FIELD_SET) - -#define SSDK_API \ - SW_API_DEF(SW_API_SWITCH_RESET, athena_reset), \ - SW_API_DEF(SW_API_SSDK_CFG, hsl_ssdk_cfg), \ - MIB_API \ - PORTCONTROL_API \ - PORTVLAN_API \ - VLAN_API \ - FDB_API \ - REG_API \ - SW_API_DEF(SW_API_MAX, NULL) - -#define SSDK_PARAM \ - SW_PARAM_DEF(SW_API_SWITCH_RESET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \ - SW_PARAM_DEF(SW_API_SSDK_CFG, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \ - SW_PARAM_DEF(SW_API_SSDK_CFG, SW_SSDK_CFG, sizeof(ssdk_cfg_t), SW_PARAM_PTR|SW_PARAM_OUT, "ssdk configuration"), \ - MIB_API_PARAM \ - PORTCONTROL_API_PARAM \ - PORTVLAN_API_PARAM \ - VLAN_API_PARAM \ - FDB_API_PARAM \ - REG_API_PARAM \ - SW_PARAM_DEF(SW_API_MAX, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), - -#if (defined(USER_MODE) && defined(KERNEL_MODULE)) -#undef SSDK_API -#undef SSDK_PARAM - -#define SSDK_API \ - REG_API \ - SW_API_DEF(SW_API_MAX, NULL), - -#define SSDK_PARAM \ - REG_API_PARAM \ - SW_PARAM_DEF(SW_API_MAX, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), -#endif - -#ifdef __cplusplus -} -#endif /* __cplusplus */ - -#endif /* _ATHENA_API_H_ */ diff --git a/feeds/ipq807x/qca-ssdk/src/include/hsl/athena/athena_fdb.h b/feeds/ipq807x/qca-ssdk/src/include/hsl/athena/athena_fdb.h deleted file mode 100755 index 7a4cb85d1..000000000 --- a/feeds/ipq807x/qca-ssdk/src/include/hsl/athena/athena_fdb.h +++ /dev/null @@ -1,76 +0,0 @@ -/* - * Copyright (c) 2012, The Linux Foundation. All rights reserved. - * Permission to use, copy, modify, and/or distribute this software for - * any purpose with or without fee is hereby granted, provided that the - * above copyright notice and this permission notice appear in all copies. - * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES - * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR - * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES - * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN - * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT - * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. - */ - - - -#ifndef _ATHENA_FDB_H -#define _ATHENA_FDB_H - -#ifdef __cplusplus -extern "C" { -#endif /* __cplusplus */ - -#include "fal/fal_fdb.h" - - sw_error_t athena_fdb_init(a_uint32_t dev_id); - -#ifdef IN_FDB -#define ATHENA_FDB_INIT(rv, dev_id) \ - { \ - rv = athena_fdb_init(dev_id); \ - SW_RTN_ON_ERROR(rv); \ - } -#else -#define ATHENA_FDB_INIT(rv, dev_id) -#endif - -#ifdef HSL_STANDALONG - - - HSL_LOCAL sw_error_t - athena_fdb_add(a_uint32_t dev_id, const fal_fdb_entry_t * entry); - - - - HSL_LOCAL sw_error_t - athena_fdb_del_all(a_uint32_t dev_id, a_uint32_t flag); - - - - HSL_LOCAL sw_error_t - athena_fdb_del_by_port(a_uint32_t dev_id, a_uint32_t port_id, - a_uint32_t flag); - - - - HSL_LOCAL sw_error_t - athena_fdb_del_by_mac(a_uint32_t dev_id, const fal_fdb_entry_t * addr); - - - - HSL_LOCAL sw_error_t - athena_fdb_first(a_uint32_t dev_id, fal_fdb_entry_t * entry); - - - - HSL_LOCAL sw_error_t - athena_fdb_next(a_uint32_t dev_id, fal_fdb_entry_t * entry); - -#endif - -#ifdef __cplusplus -} -#endif /* __cplusplus */ -#endif /* _ATHENA_FDB_H */ - diff --git a/feeds/ipq807x/qca-ssdk/src/include/hsl/athena/athena_init.h b/feeds/ipq807x/qca-ssdk/src/include/hsl/athena/athena_init.h deleted file mode 100755 index 2720961ce..000000000 --- a/feeds/ipq807x/qca-ssdk/src/include/hsl/athena/athena_init.h +++ /dev/null @@ -1,45 +0,0 @@ -/* - * Copyright (c) 2012, The Linux Foundation. All rights reserved. - * Permission to use, copy, modify, and/or distribute this software for - * any purpose with or without fee is hereby granted, provided that the - * above copyright notice and this permission notice appear in all copies. - * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES - * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR - * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES - * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN - * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT - * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. - */ - - - -#ifndef _ATHENA_INIT_H_ -#define _ATHENA_INIT_H_ - -#ifdef __cplusplus -extern "C" { -#endif /* __cplusplus */ - -#include "init/ssdk_init.h" - - sw_error_t - athena_init(a_uint32_t dev_id, ssdk_init_cfg * cfg); - - sw_error_t - athena_cleanup(a_uint32_t dev_id); - -#ifdef HSL_STANDALONG - - HSL_LOCAL sw_error_t - athena_reset(a_uint32_t dev_id); - -#endif - -#ifdef __cplusplus -} -#endif /* __cplusplus */ - -#endif /* _ATHENA_INIT_H_ */ - - diff --git a/feeds/ipq807x/qca-ssdk/src/include/hsl/athena/athena_mib.h b/feeds/ipq807x/qca-ssdk/src/include/hsl/athena/athena_mib.h deleted file mode 100755 index 0e1bc1b22..000000000 --- a/feeds/ipq807x/qca-ssdk/src/include/hsl/athena/athena_mib.h +++ /dev/null @@ -1,51 +0,0 @@ -/* - * Copyright (c) 2012, The Linux Foundation. All rights reserved. - * Permission to use, copy, modify, and/or distribute this software for - * any purpose with or without fee is hereby granted, provided that the - * above copyright notice and this permission notice appear in all copies. - * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES - * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR - * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES - * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN - * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT - * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. - */ - - - -#ifndef _ATHENA_MIB_H -#define _ATHENA_MIB_H - -#ifdef __cplusplus -extern "C" { -#endif /* __cplusplus */ - -#include "fal/fal_mib.h" - - sw_error_t - athena_mib_init(a_uint32_t dev_id); - -#ifdef IN_MIB -#define ATHENA_MIB_INIT(rv, dev_id) \ - { \ - rv = athena_mib_init(dev_id); \ - SW_RTN_ON_ERROR(rv); \ - } -#else -#define ATHENA_MIB_INIT(rv, dev_id) -#endif - -#ifdef HSL_STANDALONG - - - HSL_LOCAL sw_error_t - athena_get_mib_info(a_uint32_t dev_id, fal_port_t port_id, - fal_mib_info_t * mib_info ); -#endif - -#ifdef __cplusplus -} -#endif /* __cplusplus */ - -#endif /* _ATHENA_MIB_H */ diff --git a/feeds/ipq807x/qca-ssdk/src/include/hsl/athena/athena_port_ctrl.h b/feeds/ipq807x/qca-ssdk/src/include/hsl/athena/athena_port_ctrl.h deleted file mode 100755 index 73f677097..000000000 --- a/feeds/ipq807x/qca-ssdk/src/include/hsl/athena/athena_port_ctrl.h +++ /dev/null @@ -1,127 +0,0 @@ -/* - * Copyright (c) 2012, The Linux Foundation. All rights reserved. - * Permission to use, copy, modify, and/or distribute this software for - * any purpose with or without fee is hereby granted, provided that the - * above copyright notice and this permission notice appear in all copies. - * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES - * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR - * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES - * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN - * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT - * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. - */ - - -#ifndef _ATHENA_PORT_CTRL_H -#define _ATHENA_PORT_CTRL_H - -#ifdef __cplusplus -extern "C" { -#endif /* __cplusplus */ - -#include "fal/fal_port_ctrl.h" - - sw_error_t athena_port_ctrl_init(a_uint32_t dev_id); - -#ifdef IN_PORTCONTROL -#define ATHENA_PORT_CTRL_INIT(rv, dev_id) \ - { \ - rv = athena_port_ctrl_init(dev_id); \ - SW_RTN_ON_ERROR(rv); \ - } -#else -#define ATHENA_PORT_CTRL_INIT(rv, dev_id) -#endif - -#ifdef HSL_STANDALONG - - - HSL_LOCAL sw_error_t - athena_port_duplex_set(a_uint32_t dev_id, fal_port_t port_id, - fal_port_duplex_t duplex); - - - - HSL_LOCAL sw_error_t - athena_port_duplex_get(a_uint32_t dev_id, fal_port_t port_id, - fal_port_duplex_t * pduplex); - - - - HSL_LOCAL sw_error_t - athena_port_speed_set(a_uint32_t dev_id, fal_port_t port_id, - fal_port_speed_t speed); - - - - HSL_LOCAL sw_error_t - athena_port_speed_get(a_uint32_t dev_id, fal_port_t port_id, - fal_port_speed_t * pspeed); - - - - HSL_LOCAL sw_error_t - athena_port_autoneg_status_get(a_uint32_t dev_id, fal_port_t port_id, - a_bool_t * status); - - - - HSL_LOCAL sw_error_t - athena_port_autoneg_enable(a_uint32_t dev_id, fal_port_t port_id); - - - - HSL_LOCAL sw_error_t - athena_port_autoneg_restart(a_uint32_t dev_id, fal_port_t port_id); - - - - HSL_LOCAL sw_error_t - athena_port_autoneg_adv_set(a_uint32_t dev_id, fal_port_t port_id, - a_uint32_t autoadv); - - - - HSL_LOCAL sw_error_t - athena_port_autoneg_adv_get(a_uint32_t dev_id, fal_port_t port_id, - a_uint32_t * autoadv); - - - - HSL_LOCAL sw_error_t - athena_port_igmps_status_set(a_uint32_t dev_id, fal_port_t port_id, - a_bool_t enable); - - - - HSL_LOCAL sw_error_t - athena_port_igmps_status_get(a_uint32_t dev_id, fal_port_t port_id, - a_bool_t * enable); - - - HSL_LOCAL sw_error_t - athena_port_powersave_set(a_uint32_t dev_id, fal_port_t port_id, a_bool_t enable); - - - - HSL_LOCAL sw_error_t - athena_port_powersave_get(a_uint32_t dev_id, fal_port_t port_id, a_bool_t *enable); - - - - HSL_LOCAL sw_error_t - athena_port_hibernate_set(a_uint32_t dev_id, fal_port_t port_id, a_bool_t enable); - - - - HSL_LOCAL sw_error_t - athena_port_hibernate_get(a_uint32_t dev_id, fal_port_t port_id, a_bool_t *enable); - - -#endif - -#ifdef __cplusplus -} -#endif /* __cplusplus */ -#endif /* _ATHENA_PORT_CTRL_H */ diff --git a/feeds/ipq807x/qca-ssdk/src/include/hsl/athena/athena_portvlan.h b/feeds/ipq807x/qca-ssdk/src/include/hsl/athena/athena_portvlan.h deleted file mode 100755 index 00385d970..000000000 --- a/feeds/ipq807x/qca-ssdk/src/include/hsl/athena/athena_portvlan.h +++ /dev/null @@ -1,94 +0,0 @@ -/* - * Copyright (c) 2012, The Linux Foundation. All rights reserved. - * Permission to use, copy, modify, and/or distribute this software for - * any purpose with or without fee is hereby granted, provided that the - * above copyright notice and this permission notice appear in all copies. - * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES - * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR - * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES - * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN - * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT - * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. - */ - - - -#ifndef _ATHENA_PORTVLAN_H -#define _ATHENA_PORTVLAN_H - -#ifdef __cplusplus -extern "C" { -#endif /* __cplusplus */ - -#include "fal/fal_portvlan.h" - - sw_error_t - athena_portvlan_init(a_uint32_t dev_id); - -#ifdef IN_PORTVLAN -#define ATHENA_PORTVLAN_INIT(rv, dev_id) \ - { \ - rv = athena_portvlan_init(dev_id); \ - SW_RTN_ON_ERROR(rv); \ - } -#else -#define ATHENA_PORTVLAN_INIT(rv, dev_id) -#endif - -#ifdef HSL_STANDALONG - - - HSL_LOCAL sw_error_t - athena_port_1qmode_set(a_uint32_t dev_id, fal_port_t port_id, - fal_pt_1qmode_t port_1qmode); - - - - HSL_LOCAL sw_error_t - athena_port_1qmode_get(a_uint32_t dev_id, fal_port_t port_id, - fal_pt_1qmode_t * pport_1qmode); - - - - HSL_LOCAL sw_error_t - athena_port_egvlanmode_set(a_uint32_t dev_id, fal_port_t port_id, - fal_pt_1q_egmode_t port_egvlanmode); - - - - HSL_LOCAL sw_error_t - athena_port_egvlanmode_get(a_uint32_t dev_id, fal_port_t port_id, - fal_pt_1q_egmode_t * pport_egvlanmode); - - - - HSL_LOCAL sw_error_t - athena_portvlan_member_add(a_uint32_t dev_id, fal_port_t port_id, - a_uint32_t mem_port_id); - - - - HSL_LOCAL sw_error_t - athena_portvlan_member_del(a_uint32_t dev_id, fal_port_t port_id, - a_uint32_t mem_port_id); - - - - HSL_LOCAL sw_error_t - athena_portvlan_member_update(a_uint32_t dev_id, fal_port_t port_id, - fal_pbmp_t mem_port_map); - - - - HSL_LOCAL sw_error_t - athena_portvlan_member_get(a_uint32_t dev_id, fal_port_t port_id, - fal_pbmp_t *mem_port_map); - -#endif - -#ifdef __cplusplus -} -#endif /* __cplusplus */ - -#endif /* _ATHENA_PORTVLAN_H */ diff --git a/feeds/ipq807x/qca-ssdk/src/include/hsl/athena/athena_reg.h b/feeds/ipq807x/qca-ssdk/src/include/hsl/athena/athena_reg.h deleted file mode 100755 index 3553ce7b6..000000000 --- a/feeds/ipq807x/qca-ssdk/src/include/hsl/athena/athena_reg.h +++ /dev/null @@ -1,2157 +0,0 @@ -/* - * Copyright (c) 2012, The Linux Foundation. All rights reserved. - * Permission to use, copy, modify, and/or distribute this software for - * any purpose with or without fee is hereby granted, provided that the - * above copyright notice and this permission notice appear in all copies. - * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES - * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR - * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES - * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN - * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT - * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. - */ - - - -#ifndef _ATHENA_REG_H -#define _ATHENA_REG_H - -#ifdef __cplusplus -extern "C" { -#endif /* __cplusplus */ - -#define MAX_ENTRY_LEN 128 - -#define HSL_RW 1 -#define HSL_RO 0 - - /** - * Athena Mask Control Register - */ -#define MASK_CTL "mask" -#define MASK_CTL_ID 0 -#define MASK_CTL_OFFSET 0x0000 -#define MASK_CTL_E_LENGTH 4 -#define MASK_CTL_E_OFFSET 0 -#define MASK_CTL_NR_E 0 - -#define SOFT_RST "mask_rst" -#define MASK_CTL_SOFT_RST_BOFFSET 31 -#define MASK_CTL_SOFT_RST_BLEN 1 -#define MASK_CTL_SOFT_RST_FLAG HSL_RW - -#define MII_CLK_SEL "mask_clks" -#define MASK_CTL_MII_CLK_SEL_BOFFSET 24 -#define MASK_CTL_MII_CLK_SEL_BLEN 1 -#define MASK_CTL_MII_CLK_SEL_FLAG HSL_RW - -#define RMII_PHY_RX_SEL "mask_prxs" -#define MASK_CTL_RMII_PHY_RX_SEL_BOFFSET 23 -#define MASK_CTL_RMII_PHY_RX_SEL_BLEN 1 -#define MASK_CTL_RMII_PHY_RX_SEL_FLAG HSL_RW - -#define RMII_PHY_TX_SEL "mask_ptxs" -#define MASK_CTL_RMII_PHY_TX_SEL_BOFFSET 22 -#define MASK_CTL_RMII_PHY_TX_SEL_BLEN 1 -#define MASK_CTL_RMII_PHY_TX_SEL_FLAG HSL_RW - -#define RMII_MAC_RX_SEL "mask_mrxs" -#define MASK_CTL_RMII_MAC_RX_SEL_BOFFSET 21 -#define MASK_CTL_RMII_MAC_RX_SEL_BLEN 1 -#define MASK_CTL_RMII_MAC_RX_SEL_FLAG HSL_RW - -#define RMII_MAC_TX_SEL "mask_mtxs" -#define MASK_CTL_RMII_MAC_TX_SEL_BOFFSET 20 -#define MASK_CTL_RMII_MAC_TX_SEL_BLEN 1 -#define MASK_CTL_RMII_MAC_TX_SEL_FLAG HSL_RW - -#define LOAD_EEPROM "mask_ldro" -#define MASK_CTL_LOAD_EEPROM_BOFFSET 16 -#define MASK_CTL_LOAD_EEPROM_BLEN 1 -#define MASK_CTL_LOAD_EEPROM_FLAG HSL_RW - -#define DEVICE_ID "mask_did" -#define MASK_CTL_DEVICE_ID_BOFFSET 8 -#define MASK_CTL_DEVICE_ID_BLEN 8 -#define MASK_CTL_DEVICE_ID_FLAG HSL_RO - -#define REV_ID "mask_rid" -#define MASK_CTL_REV_ID_BOFFSET 0 -#define MASK_CTL_REV_ID_BLEN 8 -#define MASK_CTL_REV_ID_FLAG HSL_RO - - /** - * Global Interrupt Register - */ -#define GLOBAL_INT "gint" -#define GLOBAL_INT_ID 1 -#define GLOBAL_INT_OFFSET 0x0010 -#define GLOBAL_INT_E_LENGTH 4 -#define GLOBAL_INT_E_OFFSET 0 -#define GLOBAL_INT_NR_E 0 - -#define GLB_QM_ERR_CNT "gint_qmen" -#define GLOBAL_INT_GLB_QM_ERR_CNT_BOFFSET 24 -#define GLOBAL_INT_GLB_QM_ERR_CNT_BLEN 8 -#define GLOBAL_INT_GLB_QM_ERR_CNT_FLAG HSL_RO - -#define GLB_LOOKUP_ERR "gint_glblper" -#define GLOBAL_INT_GLB_LOOKUP_ERR_BOFFSET 17 -#define GLOBAL_INT_GLB_LOOKUP_ERR_BLEN 1 -#define GLOBAL_INT_GLB_LOOKUP_ERR_FLAG HSL_RW - -#define GLB_QM_ERR "gint_glbqmer" -#define GLOBAL_INT_GLB_QM_ERR_BOFFSET 16 -#define GLOBAL_INT_GLB_QM_ERR_BLEN 1 -#define GLOBAL_INT_GLB_QM_ERR_FLAG HSL_RW - -#define GLB_HW_INI_DONE "gint_hwid" -#define GLOBAL_INT_GLB_HW_INI_DONE_BOFFSET 14 -#define GLOBAL_INT_GLB_HW_INI_DONE_BLEN 1 -#define GLOBAL_INT_GLB_HW_INI_DONE_FLAG HSL_RW - -#define GLB_MIB_INI "gint_mibi" -#define GLOBAL_INT_GLB_MIB_INI_BOFFSET 13 -#define GLOBAL_INT_GLB_MIB_INI_BLEN 1 -#define GLOBAL_INT_GLB_MIB_INI_FLAG HSL_RW - -#define GLB_MIB_DONE "gint_mibd" -#define GLOBAL_INT_GLB_MIB_DONE_BOFFSET 12 -#define GLOBAL_INT_GLB_MIB_DONE_BLEN 1 -#define GLOBAL_INT_GLB_MIB_DONE_FLAG HSL_RW - -#define GLB_BIST_DONE "gint_bisd" -#define GLOBAL_INT_GLB_BIST_DONE_BOFFSET 11 -#define GLOBAL_INT_GLB_BIST_DONE_BLEN 1 -#define GLOBAL_INT_GLB_BIST_DONE_FLAG HSL_RW - -#define GLB_VT_MISS_VIO "gint_vtms" -#define GLOBAL_INT_GLB_VT_MISS_VIO_BOFFSET 10 -#define GLOBAL_INT_GLB_VT_MISS_VIO_BLEN 1 -#define GLOBAL_INT_GLB_VT_MISS_VIO_FLAG HSL_RW - -#define GLB_VT_MEM_VIO "gint_vtme" -#define GLOBAL_INT_GLB_VT_MEM_VIO_BOFFSET 9 -#define GLOBAL_INT_GLB_VT_MEM_VIO_BLEN 1 -#define GLOBAL_INT_GLB_VT_MEM_VIO_FLAG HSL_RW - -#define GLB_VT_DONE "gint_vtd" -#define GLOBAL_INT_GLB_VT_DONE_BOFFSET 8 -#define GLOBAL_INT_GLB_VT_DONE_BLEN 1 -#define GLOBAL_INT_GLB_VT_DONE_FLAG HSL_RW - -#define GLB_QM_INI "gint_qmin" -#define GLOBAL_INT_GLB_QM_INI_BOFFSET 7 -#define GLOBAL_INT_GLB_QM_INI_BLEN 1 -#define GLOBAL_INT_GLB_QM_INI_FLAG HSL_RW - -#define GLB_AT_INI "gint_atin" -#define GLOBAL_INT_GLB_AT_INI_BOFFSET 6 -#define GLOBAL_INT_GLB_AT_INI_BLEN 1 -#define GLOBAL_INT_GLB_AT_INI_FLAG HSL_RW - -#define GLB_ARL_FULL "gint_arlf" -#define GLOBAL_INT_GLB_ARL_FULL_BOFFSET 5 -#define GLOBAL_INT_GLB_ARL_FULL_BLEN 1 -#define GLOBAL_INT_GLB_ARL_FULL_FLAG HSL_RW - -#define GLB_ARL_DONE "gint_arld" -#define GLOBAL_INT_GLB_ARL_DONE_BOFFSET 4 -#define GLOBAL_INT_GLB_ARL_DONE_BLEN 1 -#define GLOBAL_INT_GLB_ARL_DONE_FLAG HSL_RW - -#define GLB_MDIO_DONE "gint_mdid" -#define GLOBAL_INT_GLB_MDIO_DONE_BOFFSET 3 -#define GLOBAL_INT_GLB_MDIO_DONE_BLEN 1 -#define GLOBAL_INT_GLB_MDIO_DONE_FLAG HSL_RW - -#define GLB_PHY_INT "gint_phyi" -#define GLOBAL_INT_GLB_PHY_INT_BOFFSET 2 -#define GLOBAL_INT_GLB_PHY_INT_BLEN 1 -#define GLOBAL_INT_GLB_PHY_INT_FLAG HSL_RW - -#define GLB_EEPROM_ERR "gint_epei" -#define GLOBAL_INT_GLB_EEPROM_ERR_BOFFSET 1 -#define GLOBAL_INT_GLB_EEPROM_ERR_BLEN 1 -#define GLOBAL_INT_GLB_EEPROM_ERR_FLAG HSL_RW - -#define GLB_EEPROM_INT "gint_epi" -#define GLOBAL_INT_GLB_EEPROM_INT_BOFFSET 0 -#define GLOBAL_INT_GLB_EEPROM_INT_BLEN 1 -#define GLOBAL_INT_GLB_EEPROM_INT_FLAG HSL_RW - - /** - * Global Interrupt Mask Register - */ -#define GLOBAL_INT_MASK "gintm" -#define GLOBAL_INT_MASK_ID 2 -#define GLOBAL_INT_MASK_OFFSET 0x0014 -#define GLOBAL_INT_MASK_E_LENGTH 4 -#define GLOBAL_INT_MASK_E_OFFSET 0 -#define GLOBAL_INT_MASK_NR_E 0 - -#define GLBM_LOOKUP_ERR "gintm_lpe" -#define GLOBAL_INT_MASK_GLBM_LOOKUP_ERR_BOFFSET 17 -#define GLOBAL_INT_MASK_GLBM_LOOKUP_ERR_BLEN 1 -#define GLOBAL_INT_MASK_GLBM_LOOKUP_ERR_FLAG HSL_RW - -#define GLBM_QM_ERR "gintm_qme" -#define GLOBAL_INT_MASK_GLBM_QM_ERR_BOFFSET 16 -#define GLOBAL_INT_MASK_GLBM_QM_ERR_BLEN 1 -#define GLOBAL_INT_MASK_GLBM_QM_ERR_FLAG HSL_RW - -#define GLBM_HW_INI_DONE "gintm_hwid" -#define GLOBAL_INT_MASK_GLBM_HW_INI_DONE_BOFFSET 14 -#define GLOBAL_INT_MASK_GLBM_HW_INI_DONE_BLEN 1 -#define GLOBAL_INT_MASK_GLBM_HW_INI_DONE_FLAG HSL_RW - -#define GLBM_MIB_INI "gintm_mibi" -#define GLOBAL_INT_MASK_GLBM_MIB_INI_BOFFSET 13 -#define GLOBAL_INT_MASK_GLBM_MIB_INI_BLEN 1 -#define GLOBAL_INT_MASK_GLBM_MIB_INI_FLAG HSL_RW - -#define GLBM_MIB_DONE "gintm_mibd" -#define GLOBAL_INT_MASK_GLBM_MIB_DONE_BOFFSET 12 -#define GLOBAL_INT_MASK_GLBM_MIB_DONE_BLEN 1 -#define GLOBAL_INT_MASK_GLBM_MIB_DONE_FLAG HSL_RW - -#define GLBM_BIST_DONE "gintm_bisd" -#define GLOBAL_INT_MASK_GLBM_BIST_DONE_BOFFSET 11 -#define GLOBAL_INT_MASK_GLBM_BIST_DONE_BLEN 1 -#define GLOBAL_INT_MASK_GLBM_BIST_DONE_FLAG HSL_RW - -#define GLBM_VT_MISS_VIO "gintm_vtms" -#define GLOBAL_INT_MASK_GLBM_VT_MISS_VIO_BOFFSET 10 -#define GLOBAL_INT_MASK_GLBM_VT_MISS_VIO_BLEN 1 -#define GLOBAL_INT_MASK_GLBM_VT_MISS_VIO_FLAG HSL_RW - -#define GLBM_VT_MEM_VIO "gintm_vtme" -#define GLOBAL_INT_MASK_GLBM_VT_MEM_VIO_BOFFSET 9 -#define GLOBAL_INT_MASK_GLBM_VT_MEM_VIO_BLEN 1 -#define GLOBAL_INT_MASK_GLBM_VT_MEM_VIO_FLAG HSL_RW - -#define GLBM_VT_DONE "gintm_vtd" -#define GLOBAL_INT_MASK_GLBM_VT_DONE_BOFFSET 8 -#define GLOBAL_INT_MASK_GLBM_VT_DONE_BLEN 1 -#define GLOBAL_INT_MASK_GLBM_VT_DONE_FLAG HSL_RW - -#define GLBM_QM_INI "gintm_qmin" -#define GLOBAL_INT_MASK_GLBM_QM_INI_BOFFSET 7 -#define GLOBAL_INT_MASK_GLBM_QM_INI_BLEN 1 -#define GLOBAL_INT_MASK_GLBM_QM_INI_FLAG HSL_RW - -#define GLBM_AT_INI "gintm_atin" -#define GLOBAL_INT_MASK_GLBM_AT_INI_BOFFSET 6 -#define GLOBAL_INT_MASK_GLBM_AT_INI_BLEN 1 -#define GLOBAL_INT_MASK_GLBM_AT_INI_FLAG HSL_RW - -#define GLBM_ARL_FULL "gintm_arlf" -#define GLOBAL_INT_MASK_GLBM_ARL_FULL_BOFFSET 5 -#define GLOBAL_INT_MASK_GLBM_ARL_FULL_BLEN 1 -#define GLOBAL_INT_MASK_GLBM_ARL_FULL_FLAG HSL_RW - -#define GLBM_ARL_DONE "gintm_arld" -#define GLOBAL_INT_MASK_GLBM_ARL_DONE_BOFFSET 4 -#define GLOBAL_INT_MASK_GLBM_ARL_DONE_BLEN 1 -#define GLOBAL_INT_MASK_GLBM_ARL_DONE_FLAG HSL_RW - -#define GLBM_MDIO_DONE "gintm_mdid" -#define GLOBAL_INT_MASK_GLBM_MDIO_DONE_BOFFSET 3 -#define GLOBAL_INT_MASK_GLBM_MDIO_DONE_BLEN 1 -#define GLOBAL_INT_MASK_GLBM_MDIO_DONE_FLAG HSL_RW - -#define GLBM_PHY_INT "gintm_phy" -#define GLOBAL_INT_MASK_GLBM_PHY_INT_BOFFSET 2 -#define GLOBAL_INT_MASK_GLBM_PHY_INT_BLEN 1 -#define GLOBAL_INT_MASK_GLBM_PHY_INT_FLAG HSL_RW - -#define GLBM_EEPROM_ERR "gintm_epe" -#define GLOBAL_INT_MASK_GLBM_EEPROM_ERR_BOFFSET 1 -#define GLOBAL_INT_MASK_GLBM_EEPROM_ERR_BLEN 1 -#define GLOBAL_INT_MASK_GLBM_EEPROM_ERR_FLAG HSL_RW - -#define GLBM_EEPROM_INT "gintm_ep" -#define GLOBAL_INT_MASK_GLBM_EEPROM_INT_BOFFSET 0 -#define GLOBAL_INT_MASK_GLBM_EEPROM_INT_BLEN 1 -#define GLOBAL_INT_MASK_GLBM_EEPROM_INT_FLAG HSL_RW - - - /** - * Global MAC Address Register - */ -//high -#define GLOBAL_MAC_ADDR0 "gmac0" -#define GLOBAL_MAC_ADDR0_ID 3 -#define GLOBAL_MAC_ADDR0_OFFSET 0x0020 -#define GLOBAL_MAC_ADDR0_E_LENGTH 4 -#define GLOBAL_MAC_ADDR0_E_OFFSET 0 -#define GLOBAL_MAC_ADDR0_NR_E 0 - -#define GLB_BYTE4 "gmac_b4" -#define GLOBAL_MAC_ADDR0_GLB_BYTE4_BOFFSET 8 -#define GLOBAL_MAC_ADDR0_GLB_BYTE4_BLEN 8 -#define GLOBAL_MAC_ADDR0_GLB_BYTE4_FLAG HSL_RW - -#define GLB_BYTE5 "gmac_b5" -#define GLOBAL_MAC_ADDR0_GLB_BYTE5_BOFFSET 0 -#define GLOBAL_MAC_ADDR0_GLB_BYTE5_BLEN 8 -#define GLOBAL_MAC_ADDR0_GLB_BYTE5_FLAG HSL_RW - - -//low -#define GLOBAL_MAC_ADDR1 "gmac1" -#define GLOBAL_MAC_ADDR1_ID 4 -#define GLOBAL_MAC_ADDR1_OFFSET 0x0024 -#define GLOBAL_MAC_ADDR1_E_LENGTH 4 -#define GLOBAL_MAC_ADDR1_E_OFFSET 0 -#define GLOBAL_MAC_ADDR1_NR_E 0 - -#define GLB_BYTE0 "gmac_b0" -#define GLOBAL_MAC_ADDR1_GLB_BYTE0_BOFFSET 24 -#define GLOBAL_MAC_ADDR1_GLB_BYTE0_BLEN 8 -#define GLOBAL_MAC_ADDR1_GLB_BYTE0_FLAG HSL_RW - -#define GLB_BYTE1 "gmac_b1" -#define GLOBAL_MAC_ADDR1_GLB_BYTE1_BOFFSET 16 -#define GLOBAL_MAC_ADDR1_GLB_BYTE1_BLEN 8 -#define GLOBAL_MAC_ADDR1_GLB_BYTE1_FLAG HSL_RW - -#define GLB_BYTE2 "gmac_b2" -#define GLOBAL_MAC_ADDR1_GLB_BYTE2_BOFFSET 8 -#define GLOBAL_MAC_ADDR1_GLB_BYTE2_BLEN 8 -#define GLOBAL_MAC_ADDR1_GLB_BYTE2_FLAG HSL_RW - -#define GLB_BYTE3 "gmac_b3" -#define GLOBAL_MAC_ADDR1_GLB_BYTE3_BOFFSET 0 -#define GLOBAL_MAC_ADDR1_GLB_BYTE3_BLEN 8 -#define GLOBAL_MAC_ADDR1_GLB_BYTE3_FLAG HSL_RW - - /** - * Global Control Register - */ -#define GLOBAL_CTL "gctl" -#define GLOBAL_CTL_ID 5 -#define GLOBAL_CTL_OFFSET 0x0030 -#define GLOBAL_CTL_E_LENGTH 4 -#define GLOBAL_CTL_E_OFFSET 0 -#define GLOBAL_CTL_NR_E 0 - -#define WEIGHT_PRIORITY "gctl_wpri" -#define GLOBAL_CTL_WEIGHT_PRIORITY_BOFFSET 31 -#define GLOBAL_CTL_WEIGHT_PRIORITY_BLEN 1 -#define GLOBAL_CTL_WEIGHT_PRIORITY_FLAG HSL_RW - -#define RATE_DROP_EN "gctl_rden" -#define GLOBAL_CTL_RATE_DROP_EN_BOFFSET 30 -#define GLOBAL_CTL_RATE_DROP_EN_BLEN 1 -#define GLOBAL_CTL_RATE_DROP_EN_FLAG HSL_RW - -#define QM_PRI_MODE "gctl_qmpm" -#define GLOBAL_CTL_QM_PRI_MODE_BOFFSET 29 -#define GLOBAL_CTL_QM_PRI_MODE_BLEN 1 -#define GLOBAL_CTL_QM_PRI_MODE_FLAG HSL_RW - -#define MIX_PRIORITY "gctl_mpri" -#define GLOBAL_CTL_MIX_PRIORITY_BOFFSET 28 -#define GLOBAL_CTL_MIX_PRIORITY_BLEN 1 -#define GLOBAL_CTL_MIX_PRIORITY_FLAG HSL_RW - -#define RATE_CRE_LIMIT "gctl_rcrl" -#define GLOBAL_CTL_RATE_CRE_LIMIT_BOFFSET 26 -#define GLOBAL_CTL_RATE_CRE_LIMIT_BLEN 2 -#define GLOBAL_CTL_RATE_CRE_LIMIT_FLAG HSL_RW - -#define RATE_TIME_SLOT "gctl_rtms" -#define GLOBAL_CTL_RATE_TIME_SLOT_BOFFSET 24 -#define GLOBAL_CTL_RATE_TIME_SLOT_BLEN 2 -#define GLOBAL_CTL_RATE_TIME_SLOT_FLAG HSL_RW - -#define RELOAD_TIMER "gctl_rdtm" -#define GLOBAL_CTL_RELOAD_TIMER_BOFFSET 20 -#define GLOBAL_CTL_RELOAD_TIMER_BLEN 4 -#define GLOBAL_CTL_RELOAD_TIMER_FLAG HSL_RW - -#define QM_CNT_LOCK "gctl_qmcl" -#define GLOBAL_CTL_QM_CNT_LOCK_BOFFSET 19 -#define GLOBAL_CTL_QM_CNT_LOCK_BLEN 1 -#define GLOBAL_CTL_QM_CNT_LOCK_FLAG HSL_RO - -#define BROAD_DROP_EN "gctl_bden" -#define GLOBAL_CTL_BROAD_DROP_EN_BOFFSET 18 -#define GLOBAL_CTL_BROAD_DROP_EN_BLEN 1 -#define GLOBAL_CTL_BROAD_DROP_EN_FLAG HSL_RW - -#define BROAD_STORM_CTRL "gctl_bsct" -#define GLOBAL_CTL_BROAD_STORM_CTRL_BOFFSET 16 -#define GLOBAL_CTL_BROAD_STORM_CTRL_BLEN 2 -#define GLOBAL_CTL_BROAD_STORM_CTRL_FLAG HSL_RW - -#define BROAD_STORM_EN "gctl_bsen" -#define GLOBAL_CTL_BROAD_STORM_EN_BOFFSET 11 -#define GLOBAL_CTL_BROAD_STORM_EN_BLEN 1 -#define GLOBAL_CTL_BROAD_STORM_EN_FLAG HSL_RW - -#define MAX_FRAME_SIZE "gctl_mfsz" -#define GLOBAL_CTL_MAX_FRAME_SIZE_BOFFSET 0 -#define GLOBAL_CTL_MAX_FRAME_SIZE_BLEN 11 -#define GLOBAL_CTL_MAX_FRAME_SIZE_FLAG HSL_RW - - /** - * Flow Control Register - */ -#define FLOW_CTL "fctl" -#define FLOW_CTL_ID 6 -#define FLOW_CTL_OFFSET 0x0034 -#define FLOW_CTL_E_LENGTH 4 -#define FLOW_CTL_E_OFFSET 0 -#define FLOW_CTL_NR_E 0 - -#define TEST_PAUSE "fctl_tps" -#define FLOW_CTL_TEST_PAUSE_BOFFSET 31 -#define FLOW_CTL_TEST_PAUSE_BLEN 1 -#define FLOW_CTL_TEST_PAUSE_FLAG HSL_RW - -#define PORT_PAUSE_OFF_THRES "fctl_pofft" -#define FLOW_CTL_PORT_PAUSE_OFF_THRES_BOFFSET 24 -#define FLOW_CTL_PORT_PAUSE_OFF_THRES_BLEN 7 -#define FLOW_CTL_PORT_PAUSE_OFF_THRES_FLAG HSL_RW - -#define PORT_PAUSE_ON_THRES "fctl_pont" -#define FLOW_CTL_PORT_PAUSE_ON_THRES_BOFFSET 16 -#define FLOW_CTL_PORT_PAUSE_ON_THRES_BLEN 7 -#define FLOW_CTL_PORT_PAUSE_ON_THRES_FLAG HSL_RW - -#define GOL_PAUSE_OFF_THRES "fctl_gofft" -#define FLOW_CTL_GOL_PAUSE_OFF_THRES_BOFFSET 8 -#define FLOW_CTL_GOL_PAUSE_OFF_THRES_BLEN 8 -#define FLOW_CTL_GOL_PAUSE_OFF_THRES_FLAG HSL_RW - -#define GOL_PAUSE_ON_THRES "fctl_gont" -#define FLOW_CTL_GOL_PAUSE_ON_THRES_BOFFSET 0 -#define FLOW_CTL_GOL_PAUSE_ON_THRES_BLEN 8 -#define FLOW_CTL_GOL_PAUSE_ON_THRES_FLAG HSL_RW - - /** - * QM Control Register - */ -#define QM_CTL "qmct" -#define QM_CTL_ID 7 -#define QM_CTL_OFFSET 0x0038 -#define QM_CTL_E_LENGTH 4 -#define QM_CTL_E_OFFSET 0 -#define QM_CTL_NR_E 0 - -#define QM_ERR_RST_EN "qmct_qeren" -#define QM_CTL_QM_ERR_RST_EN_BOFFSET 31 -#define QM_CTL_QM_ERR_RST_EN_BLEN 1 -#define QM_CTL_QM_ERR_RST_EN_FLAG HSL_RW - -#define LOOKUP_ERR_RST_EN "qmct_lpesen" -#define QM_CTL_LOOKUP_ERR_RST_EN_BOFFSET 30 -#define QM_CTL_LOOKUP_ERR_RST_EN_BLEN 1 -#define QM_CTL_LOOKUP_ERR_RST_EN_FLAG HSL_RW - -#define FLOOD_TO_CPU_EN "qmct_fdcpuen" -#define QM_CTL_FLOOD_TO_CPU_EN_BOFFSET 10 -#define QM_CTL_FLOOD_TO_CPU_EN_BLEN 1 -#define QM_CTL_FLOOD_TO_CPU_EN_FLAG HSL_RW - -#define QM_FUNC_TEST "qmct_qmft" -#define QM_CTL_QM_FUNC_TEST_BOFFSET 9 -#define QM_CTL_QM_FUNC_TEST_BLEN 1 -#define QM_CTL_QM_FUNC_TEST_FLAG HSL_RW - -#define MS_FC_EN "qmct_msfe" -#define QM_CTL_MS_FC_EN_BOFFSET 8 -#define QM_CTL_MS_FC_EN_BLEN 1 -#define QM_CTL_MS_FC_EN_FLAG HSL_RW - -#define FLOW_DROP_EN "qmct_fden" -#define QM_CTL_FLOW_DROP_EN_BOFFSET 7 -#define QM_CTL_FLOW_DROP_EN_BLEN 1 -#define QM_CTL_FLOW_DROP_EN_FLAG HSL_RW - -#define FLOW_DROP_CNT "qmct_fdcn" -#define QM_CTL_FLOW_DROP_CNT_BOFFSET 0 -#define QM_CTL_FLOW_DROP_CNT_BLEN 5 -#define QM_CTL_FLOW_DROP_CNT_FLAG HSL_RW - - /** - * QM Error Register - */ -#define QM_ERR "qmer" -#define QM_ERR_ID 8 -#define QM_ERR_OFFSET 0x003C -#define QM_ERR_E_LENGTH 4 -#define QM_ERR_E_OFFSET 0 -#define QM_ERR_NR_E 0 - -#define QM_ERR_DATA "qmer_data" -#define QM_ERR_QM_ERR_DATA_BOFFSET 0 -#define QM_ERR_QM_ERR_DATA_BLEN 32 -#define QM_ERR_QM_ERR_DATA_FLAG HSL_RO - - /** - * Vlan Table Function Register - */ -//high -#define VLAN_TABLE_FUNC0 "vtbf0" -#define VLAN_TABLE_FUNC0_ID 9 -#define VLAN_TABLE_FUNC0_OFFSET 0x0040 -#define VLAN_TABLE_FUNC0_E_LENGTH 4 -#define VLAN_TABLE_FUNC0_E_OFFSET 0 -#define VLAN_TABLE_FUNC0_NR_E 0 - -#define VT_PRI_EN "vtbf_vtpen" -#define VLAN_TABLE_FUNC0_VT_PRI_EN_BOFFSET 31 -#define VLAN_TABLE_FUNC0_VT_PRI_EN_BLEN 1 -#define VLAN_TABLE_FUNC0_VT_PRI_EN_FLAG HSL_RW - -#define VT_PRI "vtbf_vtpri" -#define VLAN_TABLE_FUNC0_VT_PRI_BOFFSET 28 -#define VLAN_TABLE_FUNC0_VT_PRI_BLEN 3 -#define VLAN_TABLE_FUNC0_VT_PRI_FLAG HSL_RW - -#define VLAN_ID "vtbf_vid" -#define VLAN_TABLE_FUNC0_VLAN_ID_BOFFSET 16 -#define VLAN_TABLE_FUNC0_VLAN_ID_BLEN 12 -#define VLAN_TABLE_FUNC0_VLAN_ID_FLAG HSL_RW - -#define VT_PORT_NUM "vtbf_vtpn" -#define VLAN_TABLE_FUNC0_VT_PORT_NUM_BOFFSET 8 -#define VLAN_TABLE_FUNC0_VT_PORT_NUM_BLEN 4 -#define VLAN_TABLE_FUNC0_VT_PORT_NUM_FLAG HSL_RW - -#define VT_FULL_VIO "vtbf_vtflv" -#define VLAN_TABLE_FUNC0_VT_FULL_VIO_BOFFSET 4 -#define VLAN_TABLE_FUNC0_VT_FULL_VIO_BLEN 1 -#define VLAN_TABLE_FUNC0_VT_FULL_VIO_FLAG HSL_RW - -#define VT_BUSY "vtbf_vtbs" -#define VLAN_TABLE_FUNC0_VT_BUSY_BOFFSET 3 -#define VLAN_TABLE_FUNC0_VT_BUSY_BLEN 1 -#define VLAN_TABLE_FUNC0_VT_BUSY_FLAG HSL_RW - -#define VT_FUNC "vtbf_vtfc" -#define VLAN_TABLE_FUNC0_VT_FUNC_BOFFSET 0 -#define VLAN_TABLE_FUNC0_VT_FUNC_BLEN 3 -#define VLAN_TABLE_FUNC0_VT_FUNC_FLAG HSL_RW - -//low -#define VLAN_TABLE_FUNC1 "vtbf1" -#define VLAN_TABLE_FUNC1_ID 10 -#define VLAN_TABLE_FUNC1_OFFSET 0x0044 -#define VLAN_TABLE_FUNC1_E_LENGTH 4 -#define VLAN_TABLE_FUNC1_E_OFFSET 0 -#define VLAN_TABLE_FUNC1_NR_E 0 - -#define PORT_TAG_EN "vtbf_pgen" -#define VLAN_TABLE_FUNC1_PORT_TAG_EN_BOFFSET 12 -#define VLAN_TABLE_FUNC1_PORT_TAG_EN_BLEN 20 -#define VLAN_TABLE_FUNC1_PORT_TAG_EN_FLAG HSL_RW - -#define VT_VALID "vtbf_vtvd" -#define VLAN_TABLE_FUNC1_VT_VALID_BOFFSET 11 -#define VLAN_TABLE_FUNC1_VT_VALID_BLEN 1 -#define VLAN_TABLE_FUNC1_VT_VALID_FLAG HSL_RW - -#define VID_MEM "vtbf_vidm" -#define VLAN_TABLE_FUNC1_VID_MEM_BOFFSET 0 -#define VLAN_TABLE_FUNC1_VID_MEM_BLEN 10 -#define VLAN_TABLE_FUNC1_VID_MEM_FLAG HSL_RW - - /** - * Address Table Function Register - */ -#define ADDR_TABLE_FUNC0 "atbf0" -#define ADDR_TABLE_FUNC0_ID 11 -#define ADDR_TABLE_FUNC0_OFFSET 0x0050 -#define ADDR_TABLE_FUNC0_E_LENGTH 4 -#define ADDR_TABLE_FUNC0_E_OFFSET 0 -#define ADDR_TABLE_FUNC0_NR_E 0 - -#define AT_ADDR_BYTE4 "atbf_adb4" -#define ADDR_TABLE_FUNC0_AT_ADDR_BYTE4_BOFFSET 24 -#define ADDR_TABLE_FUNC0_AT_ADDR_BYTE4_BLEN 8 -#define ADDR_TABLE_FUNC0_AT_ADDR_BYTE4_FLAG HSL_RW - -#define AT_ADDR_BYTE5 "atbf_adb5" -#define ADDR_TABLE_FUNC0_AT_ADDR_BYTE5_BOFFSET 16 -#define ADDR_TABLE_FUNC0_AT_ADDR_BYTE5_BLEN 8 -#define ADDR_TABLE_FUNC0_AT_ADDR_BYTE5_FLAG HSL_RW - -#define AT_FULL_VIO "atbf_atfv" -#define ADDR_TABLE_FUNC0_AT_FULL_VIO_BOFFSET 12 -#define ADDR_TABLE_FUNC0_AT_FULL_VIO_BLEN 1 -#define ADDR_TABLE_FUNC0_AT_FULL_VIO_FLAG HSL_RW - -#define AT_PORT_NUM "atbf_atpn" -#define ADDR_TABLE_FUNC0_AT_PORT_NUM_BOFFSET 8 -#define ADDR_TABLE_FUNC0_AT_PORT_NUM_BLEN 4 -#define ADDR_TABLE_FUNC0_AT_PORT_NUM_FLAG HSL_RW - -#define AT_BUSY "atbf_atbs" -#define ADDR_TABLE_FUNC0_AT_BUSY_BOFFSET 3 -#define ADDR_TABLE_FUNC0_AT_BUSY_BLEN 1 -#define ADDR_TABLE_FUNC0_AT_BUSY_FLAG HSL_RW - -#define AT_FUNC "atbf_atfc" -#define ADDR_TABLE_FUNC0_AT_FUNC_BOFFSET 0 -#define ADDR_TABLE_FUNC0_AT_FUNC_BLEN 3 -#define ADDR_TABLE_FUNC0_AT_FUNC_FLAG HSL_RW - - -#define ADDR_TABLE_FUNC1 "atbf1" -#define ADDR_TABLE_FUNC1_ID 12 -#define ADDR_TABLE_FUNC1_OFFSET 0x0054 -#define ADDR_TABLE_FUNC1_E_LENGTH 4 -#define ADDR_TABLE_FUNC1_E_OFFSET 0 -#define ADDR_TABLE_FUNC1_NR_E 0 - -#define AT_ADDR_BYTE0 "atbf_adb0" -#define ADDR_TABLE_FUNC1_AT_ADDR_BYTE0_BOFFSET 24 -#define ADDR_TABLE_FUNC1_AT_ADDR_BYTE0_BLEN 8 -#define ADDR_TABLE_FUNC1_AT_ADDR_BYTE0_FLAG HSL_RW - -#define AT_ADDR_BYTE1 "atbf_adb1" -#define ADDR_TABLE_FUNC1_AT_ADDR_BYTE1_BOFFSET 16 -#define ADDR_TABLE_FUNC1_AT_ADDR_BYTE1_BLEN 8 -#define ADDR_TABLE_FUNC1_AT_ADDR_BYTE1_FLAG HSL_RW - -#define AT_ADDR_BYTE2 "atbf_adb2" -#define ADDR_TABLE_FUNC1_AT_ADDR_BYTE2_BOFFSET 8 -#define ADDR_TABLE_FUNC1_AT_ADDR_BYTE2_BLEN 8 -#define ADDR_TABLE_FUNC1_AT_ADDR_BYTE2_FLAG HSL_RW - -#define AT_ADDR_BYTE3 "atbf_adb3" -#define ADDR_TABLE_FUNC1_AT_ADDR_BYTE3_BOFFSET 0 -#define ADDR_TABLE_FUNC1_AT_ADDR_BYTE3_BLEN 8 -#define ADDR_TABLE_FUNC1_AT_ADDR_BYTE3_FLAG HSL_RW - - -#define ADDR_TABLE_FUNC2 "atbf2" -#define ADDR_TABLE_FUNC2_ID 13 -#define ADDR_TABLE_FUNC2_OFFSET 0x0058 -#define ADDR_TABLE_FUNC2_E_LENGTH 4 -#define ADDR_TABLE_FUNC2_E_OFFSET 0 -#define ADDR_TABLE_FUNC2_NR_E 0 - -#define COPY_TO_CPU "atbf_cpcpu" -#define ADDR_TABLE_FUNC2_COPY_TO_CPU_BOFFSET 26 -#define ADDR_TABLE_FUNC2_COPY_TO_CPU_BLEN 1 -#define ADDR_TABLE_FUNC2_COPY_TO_CPU_FLAG HSL_RW - -#define REDRCT_TO_CPU "atbf_rdcpu" -#define ADDR_TABLE_FUNC2_REDRCT_TO_CPU_BOFFSET 25 -#define ADDR_TABLE_FUNC2_REDRCT_TO_CPU_BLEN 1 -#define ADDR_TABLE_FUNC2_REDRCT_TO_CPU_FLAG HSL_RW - -#define SA_DROP_EN "atbf_saden" -#define ADDR_TABLE_FUNC2_SA_DROP_EN_BOFFSET 16 -#define ADDR_TABLE_FUNC2_SA_DROP_EN_BLEN 1 -#define ADDR_TABLE_FUNC2_SA_DROP_EN_FLAG HSL_RW - -#define AT_STATUS "atbf_atsts" -#define ADDR_TABLE_FUNC2_AT_STATUS_BOFFSET 14 -#define ADDR_TABLE_FUNC2_AT_STATUS_BLEN 2 -#define ADDR_TABLE_FUNC2_AT_STATUS_FLAG HSL_RW - -#define MIRROR_EN "atbf_miren" -#define ADDR_TABLE_FUNC2_MIRROR_EN_BOFFSET 13 -#define ADDR_TABLE_FUNC2_MIRROR_EN_BLEN 1 -#define ADDR_TABLE_FUNC2_MIRROR_EN_FLAG HSL_RW - -#define AT_PRI_EN "atbf_atpen" -#define ADDR_TABLE_FUNC2_AT_PRI_EN_BOFFSET 12 -#define ADDR_TABLE_FUNC2_AT_PRI_EN_BLEN 1 -#define ADDR_TABLE_FUNC2_AT_PRI_EN_FLAG HSL_RW - -#define AT_PRI "atbf_atpri" -#define ADDR_TABLE_FUNC2_AT_PRI_BOFFSET 10 -#define ADDR_TABLE_FUNC2_AT_PRI_BLEN 2 -#define ADDR_TABLE_FUNC2_AT_PRI_FLAG HSL_RW - -#define DES_PORT "atbf_desp" -#define ADDR_TABLE_FUNC2_DES_PORT_BOFFSET 0 -#define ADDR_TABLE_FUNC2_DES_PORT_BLEN 10 -#define ADDR_TABLE_FUNC2_DES_PORT_FLAG HSL_RW - - /** - * Address Table Control Register - */ -#define ADDR_TABLE_CTL "atbc" -#define ADDR_TABLE_CTL_ID 14 -#define ADDR_TABLE_CTL_OFFSET 0x005C -#define ADDR_TABLE_CTL_E_LENGTH 4 -#define ADDR_TABLE_CTL_E_OFFSET 0 -#define ADDR_TABLE_CTL_NR_E 0 - -#define ARP_EN "atbc_arpe" -#define ADDR_TABLE_CTL_ARP_EN_BOFFSET 20 -#define ADDR_TABLE_CTL_ARP_EN_BLEN 1 -#define ADDR_TABLE_CTL_ARP_EN_FLAG HSL_RW - -#define ARL_INI_EN "atbc_arlie" -#define ADDR_TABLE_CTL_ARL_INI_EN_BOFFSET 19 -#define ADDR_TABLE_CTL_ARL_INI_EN_BLEN 1 -#define ADDR_TABLE_CTL_ARL_INI_EN_FLAG HSL_RW - -#define BPDU_EN "atbc_bpdue" -#define ADDR_TABLE_CTL_BPDU_EN_BOFFSET 18 -#define ADDR_TABLE_CTL_BPDU_EN_BLEN 1 -#define ADDR_TABLE_CTL_BPDU_EN_FLAG HSL_RW - -#define AGE_EN "atbc_agee" -#define ADDR_TABLE_CTL_AGE_EN_BOFFSET 17 -#define ADDR_TABLE_CTL_AGE_EN_BLEN 1 -#define ADDR_TABLE_CTL_AGE_EN_FLAG HSL_RW - -#define AGE_TIME "atbc_aget" -#define ADDR_TABLE_CTL_AGE_TIME_BOFFSET 0 -#define ADDR_TABLE_CTL_AGE_TIME_BLEN 16 -#define ADDR_TABLE_CTL_AGE_TIME_FLAG HSL_RW - - /** - * IP Priority Mapping Register - */ -#define IP_PRI_MAPPING0 "imap0" -#define IP_PRI_MAPPING0_ID 15 -#define IP_PRI_MAPPING0_OFFSET 0x0060 -#define IP_PRI_MAPPING0_E_LENGTH 4 -#define IP_PRI_MAPPING0_E_OFFSET 0 -#define IP_PRI_MAPPING0_NR_E 0 - -#define IP_0X3C "imap_ip3c" -#define IP_PRI_MAPPING0_IP_0X3C_BOFFSET 30 -#define IP_PRI_MAPPING0_IP_0X3C_BLEN 2 -#define IP_PRI_MAPPING0_IP_0X3C_FLAG HSL_RW - -#define IP_0X38 "imap_ip38" -#define IP_PRI_MAPPING0_IP_0X38_BOFFSET 28 -#define IP_PRI_MAPPING0_IP_0X38_BLEN 2 -#define IP_PRI_MAPPING0_IP_0X38_FLAG HSL_RW - -#define IP_0X34 "imap_ip34" -#define IP_PRI_MAPPING0_IP_0X34_BOFFSET 26 -#define IP_PRI_MAPPING0_IP_0X34_BLEN 2 -#define IP_PRI_MAPPING0_IP_0X34_FLAG HSL_RW - -#define IP_0X30 "imap_ip30" -#define IP_PRI_MAPPING0_IP_0X30_BOFFSET 24 -#define IP_PRI_MAPPING0_IP_0X30_BLEN 2 -#define IP_PRI_MAPPING0_IP_0X30_FLAG HSL_RW - -#define IP_0X2C "imap_ip2c" -#define IP_PRI_MAPPING0_IP_0X2C_BOFFSET 22 -#define IP_PRI_MAPPING0_IP_0X2C_BLEN 2 -#define IP_PRI_MAPPING0_IP_0X2C_FLAG HSL_RW - -#define IP_0X28 "imap_ip28" -#define IP_PRI_MAPPING0_IP_0X28_BOFFSET 20 -#define IP_PRI_MAPPING0_IP_0X28_BLEN 2 -#define IP_PRI_MAPPING0_IP_0X28_FLAG HSL_RW - -#define IP_0X24 "imap_ip24" -#define IP_PRI_MAPPING0_IP_0X24_BOFFSET 18 -#define IP_PRI_MAPPING0_IP_0X24_BLEN 2 -#define IP_PRI_MAPPING0_IP_0X24_FLAG HSL_RW - -#define IP_0X20 "imap_ip20" -#define IP_PRI_MAPPING0_IP_0X20_BOFFSET 16 -#define IP_PRI_MAPPING0_IP_0X20_BLEN 2 -#define IP_PRI_MAPPING0_IP_0X20_FLAG HSL_RW - -#define IP_0X1C "imap_ip1c" -#define IP_PRI_MAPPING0_IP_0X1C_BOFFSET 14 -#define IP_PRI_MAPPING0_IP_0X1C_BLEN 2 -#define IP_PRI_MAPPING0_IP_0X1C_FLAG HSL_RW - -#define IP_0X18 "imap_ip18" -#define IP_PRI_MAPPING0_IP_0X18_BOFFSET 12 -#define IP_PRI_MAPPING0_IP_0X18_BLEN 2 -#define IP_PRI_MAPPING0_IP_0X18_FLAG HSL_RW - -#define IP_0X14 "imap_ip14" -#define IP_PRI_MAPPING0_IP_0X14_BOFFSET 10 -#define IP_PRI_MAPPING0_IP_0X14_BLEN 2 -#define IP_PRI_MAPPING0_IP_0X14_FLAG HSL_RW - -#define IP_0X10 "imap_ip10" -#define IP_PRI_MAPPING0_IP_0X10_BOFFSET 8 -#define IP_PRI_MAPPING0_IP_0X10_BLEN 2 -#define IP_PRI_MAPPING0_IP_0X10_FLAG HSL_RW - -#define IP_0X0C "imap_ip0c" -#define IP_PRI_MAPPING0_IP_0X0C_BOFFSET 6 -#define IP_PRI_MAPPING0_IP_0X0C_BLEN 2 -#define IP_PRI_MAPPING0_IP_0X0C_FLAG HSL_RW - -#define IP_0X08 "imap_ip08" -#define IP_PRI_MAPPING0_IP_0X08_BOFFSET 4 -#define IP_PRI_MAPPING0_IP_0X08_BLEN 2 -#define IP_PRI_MAPPING0_IP_0X08_FLAG HSL_RW - -#define IP_0X04 "imap_ip04" -#define IP_PRI_MAPPING0_IP_0X04_BOFFSET 2 -#define IP_PRI_MAPPING0_IP_0X04_BLEN 2 -#define IP_PRI_MAPPING0_IP_0X04_FLAG HSL_RW - -#define IP_0X00 "imap_ip00" -#define IP_PRI_MAPPING0_IP_0X00_BOFFSET 0 -#define IP_PRI_MAPPING0_IP_0X00_BLEN 2 -#define IP_PRI_MAPPING0_IP_0X00_FLAG HSL_RW - -#define IP_PRI_MAPPING1 "imap1" -#define IP_PRI_MAPPING1_ID 16 -#define IP_PRI_MAPPING1_OFFSET 0x0064 -#define IP_PRI_MAPPING1_E_LENGTH 4 -#define IP_PRI_MAPPING1_E_OFFSET 0 -#define IP_PRI_MAPPING1_NR_E 0 - -#define IP_0X7C "imap_ip7c" -#define IP_PRI_MAPPING1_IP_0X7C_BOFFSET 30 -#define IP_PRI_MAPPING1_IP_0X7C_BLEN 2 -#define IP_PRI_MAPPING1_IP_0X7C_FLAG HSL_RW - -#define IP_0X78 "imap_ip78" -#define IP_PRI_MAPPING1_IP_0X78_BOFFSET 28 -#define IP_PRI_MAPPING1_IP_0X78_BLEN 2 -#define IP_PRI_MAPPING1_IP_0X78_FLAG HSL_RW - -#define IP_0X74 "imap_ip74" -#define IP_PRI_MAPPING1_IP_0X74_BOFFSET 26 -#define IP_PRI_MAPPING1_IP_0X74_BLEN 2 -#define IP_PRI_MAPPING1_IP_0X74_FLAG HSL_RW - -#define IP_0X70 "imap_ip70" -#define IP_PRI_MAPPING1_IP_0X70_BOFFSET 24 -#define IP_PRI_MAPPING1_IP_0X70_BLEN 2 -#define IP_PRI_MAPPING1_IP_0X70_FLAG HSL_RW - -#define IP_0X6C "imap_ip6c" -#define IP_PRI_MAPPING1_IP_0X6C_BOFFSET 22 -#define IP_PRI_MAPPING1_IP_0X6C_BLEN 2 -#define IP_PRI_MAPPING1_IP_0X6C_FLAG HSL_RW - -#define IP_0X68 "imap_ip68" -#define IP_PRI_MAPPING1_IP_0X68_BOFFSET 20 -#define IP_PRI_MAPPING1_IP_0X68_BLEN 2 -#define IP_PRI_MAPPING1_IP_0X68_FLAG HSL_RW - -#define IP_0X64 "imap_ip64" -#define IP_PRI_MAPPING1_IP_0X64_BOFFSET 18 -#define IP_PRI_MAPPING1_IP_0X64_BLEN 2 -#define IP_PRI_MAPPING1_IP_0X64_FLAG HSL_RW - -#define IP_0X60 "imap_ip60" -#define IP_PRI_MAPPING1_IP_0X60_BOFFSET 16 -#define IP_PRI_MAPPING1_IP_0X60_BLEN 2 -#define IP_PRI_MAPPING1_IP_0X60_FLAG HSL_RW - -#define IP_0X5C "imap_ip5c" -#define IP_PRI_MAPPING1_IP_0X5C_BOFFSET 14 -#define IP_PRI_MAPPING1_IP_0X5C_BLEN 2 -#define IP_PRI_MAPPING1_IP_0X5C_FLAG HSL_RW - -#define IP_0X58 "imap_ip58" -#define IP_PRI_MAPPING1_IP_0X58_BOFFSET 12 -#define IP_PRI_MAPPING1_IP_0X58_BLEN 2 -#define IP_PRI_MAPPING1_IP_0X58_FLAG HSL_RW - -#define IP_0X54 "imap_ip54" -#define IP_PRI_MAPPING1_IP_0X54_BOFFSET 10 -#define IP_PRI_MAPPING1_IP_0X54_BLEN 2 -#define IP_PRI_MAPPING1_IP_0X54_FLAG HSL_RW - -#define IP_0X50 "imap_ip50" -#define IP_PRI_MAPPING1_IP_0X50_BOFFSET 8 -#define IP_PRI_MAPPING1_IP_0X50_BLEN 2 -#define IP_PRI_MAPPING1_IP_0X50_FLAG HSL_RW - -#define IP_0X4C "imap_ip4c" -#define IP_PRI_MAPPING1_IP_0X4C_BOFFSET 6 -#define IP_PRI_MAPPING1_IP_0X4C_BLEN 2 -#define IP_PRI_MAPPING1_IP_0X4C_FLAG HSL_RW - -#define IP_0X48 "imap_ip48" -#define IP_PRI_MAPPING1_IP_0X48_BOFFSET 4 -#define IP_PRI_MAPPING1_IP_0X48_BLEN 2 -#define IP_PRI_MAPPING1_IP_0X48_FLAG HSL_RW - -#define IP_0X44 "imap_ip44" -#define IP_PRI_MAPPING1_IP_0X44_BOFFSET 2 -#define IP_PRI_MAPPING1_IP_0X44_BLEN 2 -#define IP_PRI_MAPPING1_IP_0X44_FLAG HSL_RW - -#define IP_0X40 "imap_ip40" -#define IP_PRI_MAPPING1_IP_0X40_BOFFSET 0 -#define IP_PRI_MAPPING1_IP_0X40_BLEN 2 -#define IP_PRI_MAPPING1_IP_0X40_FLAG HSL_RW - - -#define IP_PRI_MAPPING2 "imap2" -#define IP_PRI_MAPPING2_ID 17 -#define IP_PRI_MAPPING2_OFFSET 0x0068 -#define IP_PRI_MAPPING2_E_LENGTH 4 -#define IP_PRI_MAPPING2_E_OFFSET 0 -#define IP_PRI_MAPPING2_NR_E 0 - -#define IP_0XBC "imap_ipbc" -#define IP_PRI_MAPPING2_IP_0XBC_BOFFSET 30 -#define IP_PRI_MAPPING2_IP_0XBC_BLEN 2 -#define IP_PRI_MAPPING2_IP_0XBC_FLAG HSL_RW - -#define IP_0XB8 "imap_ipb8" -#define IP_PRI_MAPPING2_IP_0XB8_BOFFSET 28 -#define IP_PRI_MAPPING2_IP_0XB8_BLEN 2 -#define IP_PRI_MAPPING2_IP_0XB8_FLAG HSL_RW - -#define IP_0XB4 "imap_ipb4" -#define IP_PRI_MAPPING2_IP_0XB4_BOFFSET 26 -#define IP_PRI_MAPPING2_IP_0XB4_BLEN 2 -#define IP_PRI_MAPPING2_IP_0XB4_FLAG HSL_RW - -#define IP_0XB0 "imap_ipb0" -#define IP_PRI_MAPPING2_IP_0XB0_BOFFSET 24 -#define IP_PRI_MAPPING2_IP_0XB0_BLEN 2 -#define IP_PRI_MAPPING2_IP_0XB0_FLAG HSL_RW - -#define IP_0XAC "imap_ipac" -#define IP_PRI_MAPPING2_IP_0XAC_BOFFSET 22 -#define IP_PRI_MAPPING2_IP_0XAC_BLEN 2 -#define IP_PRI_MAPPING2_IP_0XAC_FLAG HSL_RW - -#define IP_0XA8 "imap_ipa8" -#define IP_PRI_MAPPING2_IP_0XA8_BOFFSET 20 -#define IP_PRI_MAPPING2_IP_0XA8_BLEN 2 -#define IP_PRI_MAPPING2_IP_0XA8_FLAG HSL_RW - -#define IP_0XA4 "imap_ipa4" -#define IP_PRI_MAPPING2_IP_0XA4_BOFFSET 18 -#define IP_PRI_MAPPING2_IP_0XA4_BLEN 2 -#define IP_PRI_MAPPING2_IP_0XA4_FLAG HSL_RW - -#define IP_0XA0 "imap_ipa0" -#define IP_PRI_MAPPING2_IP_0XA0_BOFFSET 16 -#define IP_PRI_MAPPING2_IP_0XA0_BLEN 2 -#define IP_PRI_MAPPING2_IP_0XA0_FLAG HSL_RW - -#define IP_0X9C "imap_ip9c" -#define IP_PRI_MAPPING2_IP_0X9C_BOFFSET 14 -#define IP_PRI_MAPPING2_IP_0X9C_BLEN 2 -#define IP_PRI_MAPPING2_IP_0X9C_FLAG HSL_RW - -#define IP_0X98 "imap_ip98" -#define IP_PRI_MAPPING2_IP_0X98_BOFFSET 12 -#define IP_PRI_MAPPING2_IP_0X98_BLEN 2 -#define IP_PRI_MAPPING2_IP_0X98_FLAG HSL_RW - -#define IP_0X94 "imap_ip94" -#define IP_PRI_MAPPING2_IP_0X94_BOFFSET 10 -#define IP_PRI_MAPPING2_IP_0X94_BLEN 2 -#define IP_PRI_MAPPING2_IP_0X94_FLAG HSL_RW - -#define IP_0X90 "imap_ip90" -#define IP_PRI_MAPPING2_IP_0X90_BOFFSET 8 -#define IP_PRI_MAPPING2_IP_0X90_BLEN 2 -#define IP_PRI_MAPPING2_IP_0X90_FLAG HSL_RW - -#define IP_0X8C "imap_ip8c" -#define IP_PRI_MAPPING2_IP_0X8C_BOFFSET 6 -#define IP_PRI_MAPPING2_IP_0X8C_BLEN 2 -#define IP_PRI_MAPPING2_IP_0X8C_FLAG HSL_RW - -#define IP_0X88 "imap_ip88" -#define IP_PRI_MAPPING2_IP_0X88_BOFFSET 4 -#define IP_PRI_MAPPING2_IP_0X88_BLEN 2 -#define IP_PRI_MAPPING2_IP_0X88_FLAG HSL_RW - -#define IP_0X84 "imap_ip84" -#define IP_PRI_MAPPING2_IP_0X84_BOFFSET 2 -#define IP_PRI_MAPPING2_IP_0X84_BLEN 2 -#define IP_PRI_MAPPING2_IP_0X84_FLAG HSL_RW - -#define IP_0X80 "imap_ip80" -#define IP_PRI_MAPPING2_IP_0X80_BOFFSET 0 -#define IP_PRI_MAPPING2_IP_0X80_BLEN 2 -#define IP_PRI_MAPPING2_IP_0X80_FLAG HSL_RW - -#define IP_PRI_MAPPING3 "imap3" -#define IP_PRI_MAPPING3_ID 18 -#define IP_PRI_MAPPING3_OFFSET 0x006C -#define IP_PRI_MAPPING3_E_LENGTH 4 -#define IP_PRI_MAPPING3_E_OFFSET 0 -#define IP_PRI_MAPPING3_NR_E 0 - -#define IP_0XFC "imap_ipfc" -#define IP_PRI_MAPPING3_IP_0XFC_BOFFSET 30 -#define IP_PRI_MAPPING3_IP_0XFC_BLEN 2 -#define IP_PRI_MAPPING3_IP_0XFC_FLAG HSL_RW - -#define IP_0XF8 "imap_ipf8" -#define IP_PRI_MAPPING3_IP_0XF8_BOFFSET 28 -#define IP_PRI_MAPPING3_IP_0XF8_BLEN 2 -#define IP_PRI_MAPPING3_IP_0XF8_FLAG HSL_RW - -#define IP_0XF4 "imap_ipf4" -#define IP_PRI_MAPPING3_IP_0XF4_BOFFSET 26 -#define IP_PRI_MAPPING3_IP_0XF4_BLEN 2 -#define IP_PRI_MAPPING3_IP_0XF4_FLAG HSL_RW - -#define IP_0XF0 "imap_ipf0" -#define IP_PRI_MAPPING3_IP_0XF0_BOFFSET 24 -#define IP_PRI_MAPPING3_IP_0XF0_BLEN 2 -#define IP_PRI_MAPPING3_IP_0XF0_FLAG HSL_RW - -#define IP_0XEC "imap_ipec" -#define IP_PRI_MAPPING3_IP_0XEC_BOFFSET 22 -#define IP_PRI_MAPPING3_IP_0XEC_BLEN 2 -#define IP_PRI_MAPPING3_IP_0XEC_FLAG HSL_RW - -#define IP_0XE8 "imap_ipe8" -#define IP_PRI_MAPPING3_IP_0XE8_BOFFSET 20 -#define IP_PRI_MAPPING3_IP_0XE8_BLEN 2 -#define IP_PRI_MAPPING3_IP_0XE8_FLAG HSL_RW - -#define IP_0XE4 "imap_ipe4" -#define IP_PRI_MAPPING3_IP_0XE4_BOFFSET 18 -#define IP_PRI_MAPPING3_IP_0XE4_BLEN 2 -#define IP_PRI_MAPPING3_IP_0XE4_FLAG HSL_RW - -#define IP_0XE0 "imap_ipe0" -#define IP_PRI_MAPPING3_IP_0XE0_BOFFSET 16 -#define IP_PRI_MAPPING3_IP_0XE0_BLEN 2 -#define IP_PRI_MAPPING3_IP_0XE0_FLAG HSL_RW - -#define IP_0XDC "imap_ipdc" -#define IP_PRI_MAPPING3_IP_0XDC_BOFFSET 14 -#define IP_PRI_MAPPING3_IP_0XDC_BLEN 2 -#define IP_PRI_MAPPING3_IP_0XDC_FLAG HSL_RW - -#define IP_0XD8 "imap_ipd8" -#define IP_PRI_MAPPING3_IP_0XD8_BOFFSET 12 -#define IP_PRI_MAPPING3_IP_0XD8_BLEN 2 -#define IP_PRI_MAPPING3_IP_0XD8_FLAG HSL_RW - -#define IP_0XD4 "imap_ipd4" -#define IP_PRI_MAPPING3_IP_0XD4_BOFFSET 10 -#define IP_PRI_MAPPING3_IP_0XD4_BLEN 2 -#define IP_PRI_MAPPING3_IP_0XD4_FLAG HSL_RW - -#define IP_0XD0 "imap_ipd0" -#define IP_PRI_MAPPING3_IP_0XD0_BOFFSET 8 -#define IP_PRI_MAPPING3_IP_0XD0_BLEN 2 -#define IP_PRI_MAPPING3_IP_0XD0_FLAG HSL_RW - -#define IP_0XCC "imap_ipcc" -#define IP_PRI_MAPPING3_IP_0XCC_BOFFSET 6 -#define IP_PRI_MAPPING3_IP_0XCC_BLEN 2 -#define IP_PRI_MAPPING3_IP_0XCC_FLAG HSL_RW - -#define IP_0XC8 "imap_ipc8" -#define IP_PRI_MAPPING3_IP_0XC8_BOFFSET 4 -#define IP_PRI_MAPPING3_IP_0XC8_BLEN 2 -#define IP_PRI_MAPPING3_IP_0XC8_FLAG HSL_RW - -#define IP_0XC4 "imap_ipc4" -#define IP_PRI_MAPPING3_IP_0XC4_BOFFSET 2 -#define IP_PRI_MAPPING3_IP_0XC4_BLEN 2 -#define IP_PRI_MAPPING3_IP_0XC4_FLAG HSL_RW - -#define IP_0XC0 "imap_ipc0" -#define IP_PRI_MAPPING3_IP_0XC0_BOFFSET 0 -#define IP_PRI_MAPPING3_IP_0XC0_BLEN 2 -#define IP_PRI_MAPPING3_IP_0XC0_FLAG HSL_RW - - /** - * Tag Priority Mapping Register - */ -#define TAG_PRI_MAPPING "tpmap" -#define TAG_PRI_MAPPING_ID 19 -#define TAG_PRI_MAPPING_OFFSET 0x0070 -#define TAG_PRI_MAPPING_E_LENGTH 4 -#define TAG_PRI_MAPPING_E_OFFSET 0 -#define TAG_PRI_MAPPING_NR_E 0 - -#define TAG_0X07 "tpmap_tg07" -#define TAG_PRI_MAPPING_TAG_0X07_BOFFSET 14 -#define TAG_PRI_MAPPING_TAG_0X07_BLEN 2 -#define TAG_PRI_MAPPING_TAG_0X07_FLAG HSL_RW - -#define TAG_0X06 "tpmap_tg06" -#define TAG_PRI_MAPPING_TAG_0X06_BOFFSET 12 -#define TAG_PRI_MAPPING_TAG_0X06_BLEN 2 -#define TAG_PRI_MAPPING_TAG_0X06_FLAG HSL_RW - -#define TAG_0X05 "tpmap_tg05" -#define TAG_PRI_MAPPING_TAG_0X05_BOFFSET 10 -#define TAG_PRI_MAPPING_TAG_0X05_BLEN 2 -#define TAG_PRI_MAPPING_TAG_0X05_FLAG HSL_RW - -#define TAG_0X04 "tpmap_tg04" -#define TAG_PRI_MAPPING_TAG_0X04_BOFFSET 8 -#define TAG_PRI_MAPPING_TAG_0X04_BLEN 2 -#define TAG_PRI_MAPPING_TAG_0X04_FLAG HSL_RW - -#define TAG_0X03 "tpmap_tg03" -#define TAG_PRI_MAPPING_TAG_0X03_BOFFSET 6 -#define TAG_PRI_MAPPING_TAG_0X03_BLEN 2 -#define TAG_PRI_MAPPING_TAG_0X03_FLAG HSL_RW - -#define TAG_0X02 "tpmap_tg02" -#define TAG_PRI_MAPPING_TAG_0X02_BOFFSET 4 -#define TAG_PRI_MAPPING_TAG_0X02_BLEN 2 -#define TAG_PRI_MAPPING_TAG_0X02_FLAG HSL_RW - -#define TAG_0X01 "tpmap_tg01" -#define TAG_PRI_MAPPING_TAG_0X01_BOFFSET 2 -#define TAG_PRI_MAPPING_TAG_0X01_BLEN 2 -#define TAG_PRI_MAPPING_TAG_0X01_FLAG HSL_RW - -#define TAG_0X00 "tpmap_tg00" -#define TAG_PRI_MAPPING_TAG_0X00_BOFFSET 0 -#define TAG_PRI_MAPPING_TAG_0X00_BLEN 2 -#define TAG_PRI_MAPPING_TAG_0X00_FLAG HSL_RW - - /** - * Cpu Port Register - */ -#define CPU_PORT "cpup" -#define CPU_PORT_ID 20 -#define CPU_PORT_OFFSET 0x0078 -#define CPU_PORT_E_LENGTH 4 -#define CPU_PORT_E_OFFSET 0 -#define CPU_PORT_NR_E 0 - -#define CPU_PORT_EN "cpup_cpupe" -#define CPU_PORT_CPU_PORT_EN_BOFFSET 8 -#define CPU_PORT_CPU_PORT_EN_BLEN 1 -#define CPU_PORT_CPU_PORT_EN_FLAG HSL_RW - -#define MIRROR_PORT_NUM "cpup_mirpn" -#define CPU_PORT_MIRROR_PORT_NUM_BOFFSET 4 -#define CPU_PORT_MIRROR_PORT_NUM_BLEN 4 -#define CPU_PORT_MIRROR_PORT_NUM_FLAG HSL_RW - -#define RMII_CUT "cpup_rmcut" -#define CPU_PORT_RMII_CUT_BOFFSET 0 -#define CPU_PORT_RMII_CUT_BLEN 1 -#define CPU_PORT_RMII_CUT_FLAG HSL_RW - - /** - * MIB Function Register - */ -#define MIB_CNT "mibcnt" -#define MIB_CNT_ID 21 -#define MIB_CNT_OFFSET 0x0080 -#define MIB_CNT_E_LENGTH 4 -#define MIB_CNT_E_OFFSET 0 -#define MIB_CNT_NR_E 0 - -#define MIB_FUNC "mibcnt_mibf" -#define MIB_CNT_MIB_FUNC_BOFFSET 24 -#define MIB_CNT_MIB_FUNC_BLEN 3 -#define MIB_CNT_MIB_FUNC_FLAG HSL_RW - -#define MIB_BUSY "mibcnt_mibb" -#define MIB_CNT_MIB_BUSY_BOFFSET 17 -#define MIB_CNT_MIB_BUSY_BLEN 1 -#define MIB_CNT_MIB_BUSY_FLAG HSL_RW - -#define MIB_AT_HALF_EN "mibcnt_mibhe" -#define MIB_CNT_MIB_AT_HALF_EN_BOFFSET 16 -#define MIB_CNT_MIB_AT_HALF_EN_BLEN 1 -#define MIB_CNT_MIB_AT_HALF_EN_FLAG HSL_RW - -#define MIB_TIMER "mibcnt_mibt" -#define MIB_CNT_MIB_TIMER_BOFFSET 0 -#define MIB_CNT_MIB_TIMER_BLEN 16 -#define MIB_CNT_MIB_TIMER_FLAG HSL_RW - - /** - * SPI Interface Register - */ -#define SPI_INTERFACE "spi" -#define SPI_INTERFACE_ID 22 -#define SPI_INTERFACE_OFFSET 0x0090 -#define SPI_INTERFACE_E_LENGTH 4 -#define SPI_INTERFACE_E_OFFSET 0 -#define SPI_INTERFACE_NR_E 0 - -#define DEBUG_OEN "spi_dben" -#define SPI_INTERFACE_DEBUG_OEN_BOFFSET 7 -#define SPI_INTERFACE_DEBUG_OEN_BLEN 25 -#define SPI_INTERFACE_DEBUG_OEN_FLAG HSL_RO - -#define SPI_EN "spi_spien" -#define SPI_INTERFACE_SPI_EN_BOFFSET 5 -#define SPI_INTERFACE_SPI_EN_BLEN 1 -#define SPI_INTERFACE_SPI_EN_FLAG HSL_RO - -#define SPI_SPEED "spi_spisp" -#define SPI_INTERFACE_SPI_SPEED_BOFFSET 4 -#define SPI_INTERFACE_SPI_SPEED_BLEN 1 -#define SPI_INTERFACE_SPI_SPEED_FLAG HSL_RO - -#define UART_SPEED "spi_utsp" -#define SPI_INTERFACE_UART_SPEED_BOFFSET 3 -#define SPI_INTERFACE_UART_SPEED_BLEN 1 -#define SPI_INTERFACE_UART_SPEED_FLAG HSL_RO - -#define RMII_EN "spi_rmen" -#define SPI_INTERFACE_RMII_EN_BOFFSET 2 -#define SPI_INTERFACE_RMII_EN_BLEN 1 -#define SPI_INTERFACE_RMII_EN_FLAG HSL_RO - -#define MII_EN "spi_miien" -#define SPI_INTERFACE_MII_EN_BOFFSET 1 -#define SPI_INTERFACE_MII_EN_BLEN 1 -#define SPI_INTERFACE_MII_EN_FLAG HSL_RO - -#define SPI_SIZE "spi_spisz" -#define SPI_INTERFACE_SPI_SIZE_BOFFSET 0 -#define SPI_INTERFACE_SPI_SIZE_BLEN 1 -#define SPI_INTERFACE_SPI_SIZE_FLAG HSL_RO - - /** - * MDIO High Address Register - */ -#define MDIO_HIGH_ADDR "mdiohd" -#define MDIO_HIGH_ADDR_ID 23 -#define MDIO_HIGH_ADDR_OFFSET 0x0094 -#define MDIO_HIGH_ADDR_E_LENGTH 4 -#define MDIO_HIGH_ADDR_E_OFFSET 0 -#define MDIO_HIGH_ADDR_NR_E 0 - -#define MDIO_HA "mdiohd_ha" -#define MDIO_HIGH_ADDR_MDIO_HA_BOFFSET 0 -#define MDIO_HIGH_ADDR_MDIO_HA_BLEN 9 -#define MDIO_HIGH_ADDR_MDIO_HA_FLAG HSL_RW - - /** - * Destination IP Address Register - */ -#define DIP_ADDR "dip" -#define DIP_ADDR_ID 24 -#define DIP_ADDR_OFFSET 0x0098 -#define DIP_ADDR_E_LENGTH 4 -#define DIP_ADDR_E_OFFSET 0 -#define DIP_ADDR_NR_E 0 - -#define DES_IP_ADDR "dip_addr" -#define DIP_ADDR_DES_IP_ADDR_BOFFSET 0 -#define DIP_ADDR_DES_IP_ADDR_BLEN 32 -#define DIP_ADDR_DES_IP_ADDR_FLAG HSL_RW - - /** - * BIST Control Register - */ -#define BIST_CTL "bctl" -#define BIST_CTL_ID 25 -#define BIST_CTL_OFFSET 0x00A0 -#define BIST_CTL_E_LENGTH 4 -#define BIST_CTL_E_OFFSET 0 -#define BIST_CTL_NR_E 0 - -#define BIST_BUSY "bctl_busy" -#define BIST_CTL_BIST_BUSY_BOFFSET 31 -#define BIST_CTL_BIST_BUSY_BLEN 1 -#define BIST_CTL_BIST_BUSY_FLAG HSL_RW - -#define BIST_ERR_MEM "bctl_errmem" -#define BIST_CTL_BIST_ERR_MEM_BOFFSET 24 -#define BIST_CTL_BIST_ERR_MEM_BLEN 4 -#define BIST_CTL_BIST_ERR_MEM_FLAG HSL_RO - -#define BIST_PTN_EN_2 "bctl_ptnen2" -#define BIST_CTL_BIST_PTN_EN_2_BOFFSET 22 -#define BIST_CTL_BIST_PTN_EN_2_BLEN 1 -#define BIST_CTL_BIST_PTN_EN_2_FLAG HSL_RW - -#define BIST_PTN_EN_1 "bctl_ptnen1" -#define BIST_CTL_BIST_PTN_EN_1_BOFFSET 21 -#define BIST_CTL_BIST_PTN_EN_1_BLEN 1 -#define BIST_CTL_BIST_PTN_EN_1_FLAG HSL_RW - -#define BIST_PTN_EN_0 "bctl_ptnen0" -#define BIST_CTL_BIST_PTN_EN_0_BOFFSET 20 -#define BIST_CTL_BIST_PTN_EN_0_BLEN 1 -#define BIST_CTL_BIST_PTN_EN_0_FLAG HSL_RW - -#define BIST_ERR_PTN "bctl_errptn" -#define BIST_CTL_BIST_ERR_PTN_BOFFSET 16 -#define BIST_CTL_BIST_ERR_PTN_BLEN 2 -#define BIST_CTL_BIST_ERR_PTN_FLAG HSL_RO - -#define BIST_ERR_CNT "bctl_errcnt" -#define BIST_CTL_BIST_ERR_CNT_BOFFSET 13 -#define BIST_CTL_BIST_ERR_CNT_BLEN 3 -#define BIST_CTL_BIST_ERR_CNT_FLAG HSL_RO - -#define BIST_ERR_ADDR "bctl_errad" -#define BIST_CTL_BIST_ERR_ADDR_BOFFSET 0 -#define BIST_CTL_BIST_ERR_ADDR_BLEN 13 -#define BIST_CTL_BIST_ERR_ADDR_FLAG HSL_RO - - /** - * Debug Control Register - */ -#define DEBUG_CTL0 "dctl0" -#define DEBUG_CTL0_ID 26 -#define DEBUG_CTL0_OFFSET 0x00F0 -#define DEBUG_CTL0_E_LENGTH 4 -#define DEBUG_CTL0_E_OFFSET 0 -#define DEBUG_CTL0_NR_E 0 - -#define DEBUG_SEL "dctl_sel" -#define DEBUG_CTL0_DEBUG_SEL_BOFFSET 16 -#define DEBUG_CTL0_DEBUG_SEL_BLEN 8 -#define DEBUG_CTL0_DEBUG_SEL_FLAG HSL_RW - -#define DEBUG_PORT_NUM "dctl_ptnum" -#define DEBUG_CTL0_DEBUG_PORT_NUM_BOFFSET 8 -#define DEBUG_CTL0_DEBUG_PORT_NUM_BLEN 4 -#define DEBUG_CTL0_DEBUG_PORT_NUM_FLAG HSL_RW - -#define DEBUG_ADDR "dctl_addr" -#define DEBUG_CTL0_DEBUG_ADDR_BOFFSET 0 -#define DEBUG_CTL0_DEBUG_ADDR_BLEN 8 -#define DEBUG_CTL0_DEBUG_ADDR_FLAG HSL_RW - - -#define DEBUG_CTL1 "dctl1" -#define DEBUG_CTL1_ID 27 -#define DEBUG_CTL1_OFFSET 0x00F4 -#define DEBUG_CTL1_E_LENGTH 4 -#define DEBUG_CTL1_E_OFFSET 0 -#define DEBUG_CTL1_NR_E 0 - -#define DEBUG_DATA "dctl_data" -#define DEBUG_CTL1_DEBUG_DATA_BOFFSET 0 -#define DEBUG_CTL1_DEBUG_DATA_BLEN 32 -#define DEBUG_CTL1_DEBUG_DATA_FLAG HSL_RO - - /** - * QM Debug Control Register - */ -#define QM_DEBUG_CTL "qmdctl" -#define QM_DEBUG_CTL_ID 28 -#define QM_DEBUG_CTL_OFFSET 0x00F8 -#define QM_DEBUG_CTL_E_LENGTH 4 -#define QM_DEBUG_CTL_E_OFFSET 0 -#define QM_DEBUG_CTL_NR_E 0 - -#define QM_DBG_CTRL "qmdctl_dbgctl" -#define QM_DEBUG_CTL_QM_DBG_CTRL_BOFFSET 0 -#define QM_DEBUG_CTL_QM_DBG_CTRL_BLEN 32 -#define QM_DEBUG_CTL_QM_DBG_CTRL_FLAG HSL_RW - - /** - * Port Status Register - */ -#define PORT_STATUS "ptsts" -#define PORT_STATUS_ID 29 -#define PORT_STATUS_OFFSET 0x0100 -#define PORT_STATUS_E_LENGTH 4 -#define PORT_STATUS_E_OFFSET 0x0100 -#define PORT_STATUS_NR_E 6 - -#define LINK_ASYN_PAUSE "ptsts_lasynp" -#define PORT_STATUS_LINK_ASYN_PAUSE_BOFFSET 11 -#define PORT_STATUS_LINK_ASYN_PAUSE_BLEN 1 -#define PORT_STATUS_LINK_ASYN_PAUSE_FLAG HSL_RO - -#define LINK_PAUSE "ptsts_lpause" -#define PORT_STATUS_LINK_PAUSE_BOFFSET 10 -#define PORT_STATUS_LINK_PAUSE_BLEN 1 -#define PORT_STATUS_LINK_PAUSE_FLAG HSL_RO - -#define LINK_EN "ptsts_linken" -#define PORT_STATUS_LINK_EN_BOFFSET 9 -#define PORT_STATUS_LINK_EN_BLEN 1 -#define PORT_STATUS_LINK_EN_FLAG HSL_RW - -#define LINK "ptsts_ptlink" -#define PORT_STATUS_LINK_BOFFSET 8 -#define PORT_STATUS_LINK_BLEN 1 -#define PORT_STATUS_LINK_FLAG HSL_RO - -#define DUPLEX_MODE "ptsts_dupmod" -#define PORT_STATUS_DUPLEX_MODE_BOFFSET 6 -#define PORT_STATUS_DUPLEX_MODE_BLEN 1 -#define PORT_STATUS_DUPLEX_MODE_FLAG HSL_RW - -#define RX_FLOW_EN "ptsts_rxfwen" -#define PORT_STATUS_RX_FLOW_EN_BOFFSET 5 -#define PORT_STATUS_RX_FLOW_EN_BLEN 1 -#define PORT_STATUS_RX_FLOW_EN_FLAG HSL_RW - -#define TX_FLOW_EN "ptsts_txfwen" -#define PORT_STATUS_TX_FLOW_EN_BOFFSET 4 -#define PORT_STATUS_TX_FLOW_EN_BLEN 1 -#define PORT_STATUS_TX_FLOW_EN_FLAG HSL_RW - -#define RXMAC_EN "ptsts_rxmacen" -#define PORT_STATUS_RXMAC_EN_BOFFSET 3 -#define PORT_STATUS_RXMAC_EN_BLEN 1 -#define PORT_STATUS_RXMAC_EN_FLAG HSL_RW - -#define TXMAC_EN "ptsts_txmacen" -#define PORT_STATUS_TXMAC_EN_BOFFSET 2 -#define PORT_STATUS_TXMAC_EN_BLEN 1 -#define PORT_STATUS_TXMAC_EN_FLAG HSL_RW - -#define SPEED_MODE "ptsts_speed" -#define PORT_STATUS_SPEED_MODE_BOFFSET 0 -#define PORT_STATUS_SPEED_MODE_BLEN 2 -#define PORT_STATUS_SPEED_MODE_FLAG HSL_RW - - /** - * Port Control Register - */ -#define PORT_CTL "pctl" -#define PORT_CTL_ID 30 -#define PORT_CTL_OFFSET 0x0104 -#define PORT_CTL_E_LENGTH 4 -#define PORT_CTL_E_OFFSET 0x0100 -#define PORT_CTL_NR_E 6 - -#define ING_MIRROR_EN "pctl_ingmiren" -#define PORT_CTL_ING_MIRROR_EN_BOFFSET 17 -#define PORT_CTL_ING_MIRROR_EN_BLEN 1 -#define PORT_CTL_ING_MIRROR_EN_FLAG HSL_RW - -#define EG_MIRROR_EN "pctl_egmiren" -#define PORT_CTL_EG_MIRROR_EN_BOFFSET 16 -#define PORT_CTL_EG_MIRROR_EN_BLEN 1 -#define PORT_CTL_EG_MIRROR_EN_FLAG HSL_RW - -#define LEARN_EN "pctl_learnen" -#define PORT_CTL_LEARN_EN_BOFFSET 14 -#define PORT_CTL_LEARN_EN_BLEN 1 -#define PORT_CTL_LEARN_EN_FLAG HSL_RW - -#define SINGLE_VLAN_EN "pctl_svlanen" -#define PORT_CTL_SINGLE_VLAN_EN_BOFFSET 13 -#define PORT_CTL_SINGLE_VLAN_EN_BLEN 1 -#define PORT_CTL_SINGLE_VLAN_EN_FLAG HSL_RW - -#define MAC_LOOP_BACK "pctl_maclp" -#define PORT_CTL_MAC_LOOP_BACK_BOFFSET 12 -#define PORT_CTL_MAC_LOOP_BACK_BLEN 1 -#define PORT_CTL_MAC_LOOP_BACK_FLAG HSL_RW - -#define HEAD_EN "pctl_headen" -#define PORT_CTL_HEAD_EN_BOFFSET 11 -#define PORT_CTL_HEAD_EN_BLEN 1 -#define PORT_CTL_HEAD_EN_FLAG HSL_RW - -#define IGMP_MLD_EN "pctl_imlden" -#define PORT_CTL_IGMP_MLD_EN_BOFFSET 10 -#define PORT_CTL_IGMP_MLD_EN_BLEN 1 -#define PORT_CTL_IGMP_MLD_EN_FLAG HSL_RW - -#define EG_VLAN_MODE "pctl_egvmode" -#define PORT_CTL_EG_VLAN_MODE_BOFFSET 8 -#define PORT_CTL_EG_VLAN_MODE_BLEN 2 -#define PORT_CTL_EG_VLAN_MODE_FLAG HSL_RW - -#define LEARN_ONE_LOCK "pctl_lonelck" -#define PORT_CTL_LEARN_ONE_LOCK_BOFFSET 7 -#define PORT_CTL_LEARN_ONE_LOCK_BLEN 1 -#define PORT_CTL_LEARN_ONE_LOCK_FLAG HSL_RW - -#define PORT_STATE "pctl_pstate" -#define PORT_CTL_PORT_STATE_BOFFSET 0 -#define PORT_CTL_PORT_STATE_BLEN 3 -#define PORT_CTL_PORT_STATE_FLAG HSL_RW - - /** - * Port Based Vlan Register - */ -#define PORT_BASE_VLAN "pbvlan" -#define PORT_BASE_VLAN_ID 31 -#define PORT_BASE_VLAN_OFFSET 0x0108 -#define PORT_BASE_VLAN_E_LENGTH 4 -#define PORT_BASE_VLAN_E_OFFSET 0x0100 -#define PORT_BASE_VLAN_NR_E 6 - -#define DOT1Q_MODE "pbvlan_8021q" -#define PORT_BASE_VLAN_DOT1Q_MODE_BOFFSET 30 -#define PORT_BASE_VLAN_DOT1Q_MODE_BLEN 2 -#define PORT_BASE_VLAN_DOT1Q_MODE_FLAG HSL_RW - -#define ING_PRI "pbvlan_ingpri" -#define PORT_BASE_VLAN_ING_PRI_BOFFSET 28 -#define PORT_BASE_VLAN_ING_PRI_BLEN 2 -#define PORT_BASE_VLAN_ING_PRI_FLAG HSL_RW - -#define EG_TAG_PRI0 "pbvlan_egtpri" -#define PORT_BASE_VLAN_EG_TAG_PRI0_BOFFSET 27 -#define PORT_BASE_VLAN_EG_TAG_PRI0_BLEN 1 -#define PORT_BASE_VLAN_EG_TAG_PRI0_FLAG HSL_RW - -#define PORT_VID_MEM "pbvlan_pvidm" -#define PORT_BASE_VLAN_PORT_VID_MEM_BOFFSET 16 -#define PORT_BASE_VLAN_PORT_VID_MEM_BLEN 6 -#define PORT_BASE_VLAN_PORT_VID_MEM_FLAG HSL_RW - -#define PORT_VID "pbvlan_ptvid" -#define PORT_BASE_VLAN_PORT_VID_BOFFSET 0 -#define PORT_BASE_VLAN_PORT_VID_BLEN 12 -#define PORT_BASE_VLAN_PORT_VID_FLAG HSL_RW - - /** - * Port Rate Limit Register - */ -#define RATE_LIMIT "rlmt" -#define RATE_LIMIT_ID 32 -#define RATE_LIMIT_OFFSET 0x010C -#define RATE_LIMIT_E_LENGTH 4 -#define RATE_LIMIT_E_OFFSET 0x0100 -#define RATE_LIMIT_NR_E 6 - -#define EGRESS_RATE_EN "rlmt_egrateen" -#define RATE_LIMIT_EGRESS_RATE_EN_BOFFSET 25 -#define RATE_LIMIT_EGRESS_RATE_EN_BLEN 1 -#define RATE_LIMIT_EGRESS_RATE_EN_FLAG HSL_RW - -#define INGRESS_RATE_EN "rlmt_ingrateen" -#define RATE_LIMIT_INGRESS_RATE_EN_BOFFSET 24 -#define RATE_LIMIT_INGRESS_RATE_EN_BLEN 1 -#define RATE_LIMIT_INGRESS_RATE_EN_FLAG HSL_RW - -#define EG_RATE "rlmt_egrate" -#define RATE_LIMIT_EG_RATE_BOFFSET 16 -#define RATE_LIMIT_EG_RATE_BLEN 4 -#define RATE_LIMIT_EG_RATE_FLAG HSL_RW - -#define ING_RATE "rlmt_ingrate" -#define RATE_LIMIT_ING_RATE_BOFFSET 0 -#define RATE_LIMIT_ING_RATE_BLEN 4 -#define RATE_LIMIT_ING_RATE_FLAG HSL_RW - - /** - * Priority Control Register - */ -#define PRI_CTL "prctl" -#define PRI_CTL_ID 33 -#define PRI_CTL_OFFSET 0x0110 -#define PRI_CTL_E_LENGTH 4 -#define PRI_CTL_E_OFFSET 0x0100 -#define PRI_CTL_NR_E 6 - -#define PORT_PRI_EN "prctl_ptprien" -#define PRI_CTL_PORT_PRI_EN_BOFFSET 19 -#define PRI_CTL_PORT_PRI_EN_BLEN 1 -#define PRI_CTL_PORT_PRI_EN_FLAG HSL_RW - -#define DA_PRI_EN "prctl_daprien" -#define PRI_CTL_DA_PRI_EN_BOFFSET 18 -#define PRI_CTL_DA_PRI_EN_BLEN 1 -#define PRI_CTL_DA_PRI_EN_FLAG HSL_RW - -#define VLAN_PRI_EN "prctl_vprien" -#define PRI_CTL_VLAN_PRI_EN_BOFFSET 17 -#define PRI_CTL_VLAN_PRI_EN_BLEN 1 -#define PRI_CTL_VLAN_PRI_EN_FLAG HSL_RW - -#define IP_PRI_EN "prctl_ipprien" -#define PRI_CTL_IP_PRI_EN_BOFFSET 16 -#define PRI_CTL_IP_PRI_EN_BLEN 1 -#define PRI_CTL_IP_PRI_EN_FLAG HSL_RW - -#define DA_PRI_SEL "prctl_dapris" -#define PRI_CTL_DA_PRI_SEL_BOFFSET 6 -#define PRI_CTL_DA_PRI_SEL_BLEN 2 -#define PRI_CTL_DA_PRI_SEL_FLAG HSL_RW - -#define VLAN_PRI_SEL "prctl_vpris" -#define PRI_CTL_VLAN_PRI_SEL_BOFFSET 4 -#define PRI_CTL_VLAN_PRI_SEL_BLEN 2 -#define PRI_CTL_VLAN_PRI_SEL_FLAG HSL_RW - -#define IP_PRI_SEL "prctl_ippris" -#define PRI_CTL_IP_PRI_SEL_BOFFSET 2 -#define PRI_CTL_IP_PRI_SEL_BLEN 2 -#define PRI_CTL_IP_PRI_SEL_FLAG HSL_RW - -#define PORT_PRI_SEL "prctl_ptpris" -#define PRI_CTL_PORT_PRI_SEL_BOFFSET 0 -#define PRI_CTL_PORT_PRI_SEL_BLEN 2 -#define PRI_CTL_PORT_PRI_SEL_FLAG HSL_RW - - -//mib memory info -#define MIB_RXBROAD "RxBroad" -#define MIB_RXBROAD_ID 34 -#define MIB_RXBROAD_OFFSET 0x19000 -#define MIB_RXBROAD_E_LENGTH 4 -#define MIB_RXBROAD_E_OFFSET 0xa0 -#define MIB_RXBROAD_NR_E 6 - -#define MIB_RXPAUSE "RxPause" -#define MIB_RXPAUSE_ID 35 -#define MIB_RXPAUSE_OFFSET 0x19004 -#define MIB_RXPAUSE_E_LENGTH 4 -#define MIB_RXPAUSE_E_OFFSET 0xa0 -#define MIB_RXPAUSE_NR_E 6 - -#define MIB_RXMULTI "RxMulti" -#define MIB_RXMULTI_ID 36 -#define MIB_RXMULTI_OFFSET 0x19008 -#define MIB_RXMULTI_E_LENGTH 4 -#define MIB_RXMULTI_E_OFFSET 0xa0 -#define MIB_RXMULTI_NR_E 6 - -#define MIB_RXFCSERR "RxFcsErr" -#define MIB_RXFCSERR_ID 37 -#define MIB_RXFCSERR_OFFSET 0x1900C -#define MIB_RXFCSERR_E_LENGTH 4 -#define MIB_RXFCSERR_E_OFFSET 0xa0 -#define MIB_RXFCSERR_NR_E 6 - -#define MIB_RXALLIGNERR "RxAllignErr" -#define MIB_RXALLIGNERR_ID 38 -#define MIB_RXALLIGNERR_OFFSET 0x19010 -#define MIB_RXALLIGNERR_E_LENGTH 4 -#define MIB_RXALLIGNERR_E_OFFSET 0xa0 -#define MIB_RXALLIGNERR_NR_E 6 - -#define MIB_RXRUNT "RxRunt" -#define MIB_RXRUNT_ID 39 -#define MIB_RXRUNT_OFFSET 0x19014 -#define MIB_RXRUNT_E_LENGTH 4 -#define MIB_RXRUNT_E_OFFSET 0xa0 -#define MIB_RXRUNT_NR_E 6 - -#define MIB_RXFRAGMENT "RxFragment" -#define MIB_RXFRAGMENT_ID 40 -#define MIB_RXFRAGMENT_OFFSET 0x19018 -#define MIB_RXFRAGMENT_E_LENGTH 4 -#define MIB_RXFRAGMENT_E_OFFSET 0xa0 -#define MIB_RXFRAGMENT_NR_E 6 - -#define MIB_RX64BYTE "Rx64Byte" -#define MIB_RX64BYTE_ID 41 -#define MIB_RX64BYTE_OFFSET 0x1901C -#define MIB_RX64BYTE_E_LENGTH 4 -#define MIB_RX64BYTE_E_OFFSET 0xa0 -#define MIB_RX64BYTE_NR_E 6 - -#define MIB_RX128BYTE "Rx128Byte" -#define MIB_RX128BYTE_ID 42 -#define MIB_RX128BYTE_OFFSET 0x19020 -#define MIB_RX128BYTE_E_LENGTH 4 -#define MIB_RX128BYTE_E_OFFSET 0xa0 -#define MIB_RX128BYTE_NR_E 6 - -#define MIB_RX256BYTE "Rx256Byte" -#define MIB_RX256BYTE_ID 43 -#define MIB_RX256BYTE_OFFSET 0x19024 -#define MIB_RX256BYTE_E_LENGTH 4 -#define MIB_RX256BYTE_E_OFFSET 0xa0 -#define MIB_RX256BYTE_NR_E 6 - -#define MIB_RX512BYTE "Rx512Byte" -#define MIB_RX512BYTE_ID 44 -#define MIB_RX512BYTE_OFFSET 0x19028 -#define MIB_RX512BYTE_E_LENGTH 4 -#define MIB_RX512BYTE_E_OFFSET 0xa0 -#define MIB_RX512BYTE_NR_E 6 - -#define MIB_RX1024BYTE "Rx1024Byte" -#define MIB_RX1024BYTE_ID 45 -#define MIB_RX1024BYTE_OFFSET 0x1902C -#define MIB_RX1024BYTE_E_LENGTH 4 -#define MIB_RX1024BYTE_E_OFFSET 0xa0 -#define MIB_RX1024BYTE_NR_E 6 - -#define MIB_RX1518BYTE "Rx1518Byte" //reserved for s16 - -#define MIB_RXMAXBYTE "RxMaxByte" -#define MIB_RXMAXBYTE_ID 46 -#define MIB_RXMAXBYTE_OFFSET 0x19030 -#define MIB_RXMAXBYTE_E_LENGTH 4 -#define MIB_RXMAXBYTE_E_OFFSET 0xa0 -#define MIB_RXMAXBYTE_NR_E 6 - -#define MIB_RXTOOLONG "RxTooLong" -#define MIB_RXTOOLONG_ID 47 -#define MIB_RXTOOLONG_OFFSET 0x19034 -#define MIB_RXTOOLONG_E_LENGTH 4 -#define MIB_RXTOOLONG_E_OFFSET 0xa0 -#define MIB_RXTOOLONG_NR_E 6 - -#define MIB_RXGOODBYTE_LO "RxGoodByteLo" -#define MIB_RXGOODBYTE_LO_ID 48 -#define MIB_RXGOODBYTE_LO_OFFSET 0x19038 -#define MIB_RXGOODBYTE_LO_E_LENGTH 4 -#define MIB_RXGOODBYTE_LO_E_OFFSET 0xa0 -#define MIB_RXGOODBYTE_LO_NR_E 6 - -#define MIB_RXGOODBYTE_HI "RxGoodByteHi" -#define MIB_RXGOODBYTE_HI_ID 49 -#define MIB_RXGOODBYTE_HI_OFFSET 0x1903C -#define MIB_RXGOODBYTE_HI_E_LENGTH 4 -#define MIB_RXGOODBYTE_HI_E_OFFSET 0xa0 -#define MIB_RXGOODBYTE_HI_NR_E 6 - -#define MIB_RXBADBYTE_LO "RxBadByteLo" -#define MIB_RXBADBYTE_LO_ID 50 -#define MIB_RXBADBYTE_LO_OFFSET 0x19040 -#define MIB_RXBADBYTE_LO_E_LENGTH 4 -#define MIB_RXBADBYTE_LO_E_OFFSET 0xa0 -#define MIB_RXBADBYTE_LO_NR_E 6 - -#define MIB_RXBADBYTE_HI "RxBadByteHi" -#define MIB_RXBADBYTE_HI_ID 51 -#define MIB_RXBADBYTE_HI_OFFSET 0x19044 -#define MIB_RXBADBYTE_HI_E_LENGTH 4 -#define MIB_RXBADBYTE_HI_E_OFFSET 0xa0 -#define MIB_RXBADBYTE_HI_NR_E 6 - -#define MIB_RXOVERFLOW "RxOverFlow" -#define MIB_RXOVERFLOW_ID 52 -#define MIB_RXOVERFLOW_OFFSET 0x19048 -#define MIB_RXOVERFLOW_E_LENGTH 4 -#define MIB_RXOVERFLOW_E_OFFSET 0xa0 -#define MIB_RXOVERFLOW_NR_E 6 - -#define MIB_FILTERED "Filtered" -#define MIB_FILTERED_ID 53 -#define MIB_FILTERED_OFFSET 0x1904C -#define MIB_FILTERED_E_LENGTH 4 -#define MIB_FILTERED_E_OFFSET 0xa0 -#define MIB_FILTERED_NR_E 6 - -#define MIB_TXBROAD "TxBroad" -#define MIB_TXBROAD_ID 54 -#define MIB_TXBROAD_OFFSET 0x19050 -#define MIB_TXBROAD_E_LENGTH 4 -#define MIB_TXBROAD_E_OFFSET 0xa0 -#define MIB_TXBROAD_NR_E 6 - -#define MIB_TXPAUSE "TxPause" -#define MIB_TXPAUSE_ID 55 -#define MIB_TXPAUSE_OFFSET 0x19054 -#define MIB_TXPAUSE_E_LENGTH 4 -#define MIB_TXPAUSE_E_OFFSET 0xa0 -#define MIB_TXPAUSE_NR_E 6 - -#define MIB_TXMULTI "TxMulti" -#define MIB_TXMULTI_ID 56 -#define MIB_TXMULTI_OFFSET 0x19058 -#define MIB_TXMULTI_E_LENGTH 4 -#define MIB_TXMULTI_E_OFFSET 0xa0 -#define MIB_TXMULTI_NR_E 6 - -#define MIB_TXUNDERRUN "TxUnderRun" -#define MIB_TXUNDERRUN_ID 57 -#define MIB_TXUNDERRUN_OFFSET 0x1905C -#define MIB_TXUNDERRUN_E_LENGTH 4 -#define MIB_TXUNDERRUN_E_OFFSET 0xa0 -#define MIB_TXUNDERRUN_NR_E 6 - -#define MIB_TX64BYTE "Tx64Byte" -#define MIB_TX64BYTE_ID 58 -#define MIB_TX64BYTE_OFFSET 0x19060 -#define MIB_TX64BYTE_E_LENGTH 4 -#define MIB_TX64BYTE_E_OFFSET 0xa0 -#define MIB_TX64BYTE_NR_E 6 - -#define MIB_TX128BYTE "Tx128Byte" -#define MIB_TX128BYTE_ID 59 -#define MIB_TX128BYTE_OFFSET 0x19064 -#define MIB_TX128BYTE_E_LENGTH 4 -#define MIB_TX128BYTE_E_OFFSET 0xa0 -#define MIB_TX128BYTE_NR_E 6 - -#define MIB_TX256BYTE "Tx256Byte" -#define MIB_TX256BYTE_ID 60 -#define MIB_TX256BYTE_OFFSET 0x19068 -#define MIB_TX256BYTE_E_LENGTH 4 -#define MIB_TX256BYTE_E_OFFSET 0xa0 -#define MIB_TX256BYTE_NR_E 6 - -#define MIB_TX512BYTE "Tx512Byte" -#define MIB_TX512BYTE_ID 61 -#define MIB_TX512BYTE_OFFSET 0x1906C -#define MIB_TX512BYTE_E_LENGTH 4 -#define MIB_TX512BYTE_E_OFFSET 0xa0 -#define MIB_TX512BYTE_NR_E 6 - -#define MIB_TX1024BYTE "Tx1024Byte" -#define MIB_TX1024BYTE_ID 62 -#define MIB_TX1024BYTE_OFFSET 0x19070 -#define MIB_TX1024BYTE_E_LENGTH 4 -#define MIB_TX1024BYTE_E_OFFSET 0xa0 -#define MIB_TX1024BYTE_NR_E 6 - -#define MIB_TX1518BYTE "Tx1518Byte" //reserved for s16 - -#define MIB_TXMAXBYTE "TxMaxByte" -#define MIB_TXMAXBYTE_ID 63 -#define MIB_TXMAXBYTE_OFFSET 0x19074 -#define MIB_TXMAXBYTE_E_LENGTH 4 -#define MIB_TXMAXBYTE_E_OFFSET 0xa0 -#define MIB_TXMAXBYTE_NR_E 6 - -#define MIB_TXOVERSIZE "TxOverSize" -#define MIB_TXOVERSIZE_ID 64 -#define MIB_TXOVERSIZE_OFFSET 0x19078 -#define MIB_TXOVERSIZE_E_LENGTH 4 -#define MIB_TXOVERSIZE_E_OFFSET 0xa0 -#define MIB_TXOVERSIZE_NR_E 6 - -#define MIB_TXBYTE_LO "TxByteLo" -#define MIB_TXBYTE_LO_ID 65 -#define MIB_TXBYTE_LO_OFFSET 0x1907C -#define MIB_TXBYTE_LO_E_LENGTH 4 -#define MIB_TXBYTE_LO_E_OFFSET 0xa0 -#define MIB_TXBYTE_LO_NR_E 6 - -#define MIB_TXBYTE_HI "TxByteHi" -#define MIB_TXBYTE_HI_ID 66 -#define MIB_TXBYTE_HI_OFFSET 0x19080 -#define MIB_TXBYTE_HI_E_LENGTH 4 -#define MIB_TXBYTE_HI_E_OFFSET 0xa0 -#define MIB_TXBYTE_HI_NR_E 6 - -#define MIB_TXCOLLISION "TxCollision" -#define MIB_TXCOLLISION_ID 67 -#define MIB_TXCOLLISION_OFFSET 0x19084 -#define MIB_TXCOLLISION_E_LENGTH 4 -#define MIB_TXCOLLISION_E_OFFSET 0xa0 -#define MIB_TXCOLLISION_NR_E 6 - -#define MIB_TXABORTCOL "TxAbortCol" -#define MIB_TXABORTCOL_ID 68 -#define MIB_TXABORTCOL_OFFSET 0x19088 -#define MIB_TXABORTCOL_E_LENGTH 4 -#define MIB_TXABORTCOL_E_OFFSET 0xa0 -#define MIB_TXABORTCOL_NR_E 6 - -#define MIB_TXMULTICOL "TxMultiCol" -#define MIB_TXMULTICOL_ID 69 -#define MIB_TXMULTICOL_OFFSET 0x1908C -#define MIB_TXMULTICOL_E_LENGTH 4 -#define MIB_TXMULTICOL_E_OFFSET 0xa0 -#define MIB_TXMULTICOL_NR_E 6 - -#define MIB_TXSINGALCOL "TxSingalCol" -#define MIB_TXSINGALCOL_ID 70 -#define MIB_TXSINGALCOL_OFFSET 0x19090 -#define MIB_TXSINGALCOL_E_LENGTH 4 -#define MIB_TXSINGALCOL_E_OFFSET 0xa0 -#define MIB_TXSINGALCOL_NR_E 6 - -#define MIB_TXEXCDEFER "TxExcDefer" -#define MIB_TXEXCDEFER_ID 71 -#define MIB_TXEXCDEFER_OFFSET 0x19094 -#define MIB_TXEXCDEFER_E_LENGTH 4 -#define MIB_TXEXCDEFER_E_OFFSET 0xa0 -#define MIB_TXEXCDEFER_NR_E 6 - -#define MIB_TXDEFER "TxDefer" -#define MIB_TXDEFER_ID 72 -#define MIB_TXDEFER_OFFSET 0x19098 -#define MIB_TXDEFER_E_LENGTH 4 -#define MIB_TXDEFER_E_OFFSET 0xa0 -#define MIB_TXDEFER_NR_E 6 - -#define MIB_TXLATECOL "TxLateCol" -#define MIB_TXLATECOL_ID 73 -#define MIB_TXLATECOL_OFFSET 0x1909C -#define MIB_TXLATECOL_E_LENGTH 4 -#define MIB_TXLATECOL_E_OFFSET 0xa0 -#define MIB_TXLATECOL_NR_E 6 - -//second mem block -#define MIB_RXBROAD_2 "RxBroad_2" -#define MIB_RXBROAD_2_ID 34 -#define MIB_RXBROAD_2_OFFSET (MIB_RXBROAD_OFFSET + 0x400) -#define MIB_RXBROAD_2_E_LENGTH 4 -#define MIB_RXBROAD_2_E_OFFSET 0xa0 -#define MIB_RXBROAD_2_NR_E 6 - -#define MIB_RXPAUSE_2 "RxPause_2" -#define MIB_RXPAUSE_2_ID 35 -#define MIB_RXPAUSE_2_OFFSET (MIB_RXPAUSE_OFFSET + 0x400) -#define MIB_RXPAUSE_2_E_LENGTH 4 -#define MIB_RXPAUSE_2_E_OFFSET 0xa0 -#define MIB_RXPAUSE_2_NR_E 6 - -#define MIB_RXMULTI_2 "RxMulti_2" -#define MIB_RXMULTI_2_ID 36 -#define MIB_RXMULTI_2_OFFSET (MIB_RXMULTI_OFFSET + 0x400) -#define MIB_RXMULTI_2_E_LENGTH 4 -#define MIB_RXMULTI_2_E_OFFSET 0xa0 -#define MIB_RXMULTI_2_NR_E 6 - -#define MIB_RXFCSERR_2 "RxFcsErr_2" -#define MIB_RXFCSERR_2_ID 37 -#define MIB_RXFCSERR_2_OFFSET (MIB_RXFCSERR_OFFSET + 0x400) -#define MIB_RXFCSERR_2_E_LENGTH 4 -#define MIB_RXFCSERR_2_E_OFFSET 0xa0 -#define MIB_RXFCSERR_2_NR_E 6 - -#define MIB_RXALLIGNERR_2 "RxAllignErr_2" -#define MIB_RXALLIGNERR_2_ID 38 -#define MIB_RXALLIGNERR_2_OFFSET (MIB_RXALLIGNERR_OFFSET + 0x400) -#define MIB_RXALLIGNERR_2_E_LENGTH 4 -#define MIB_RXALLIGNERR_2_E_OFFSET 0xa0 -#define MIB_RXALLIGNERR_2_NR_E 6 - -#define MIB_RXRUNT_2 "RxRunt_2" -#define MIB_RXRUNT_2_ID 39 -#define MIB_RXRUNT_2_OFFSET (MIB_RXRUNT_OFFSET + 0x400) -#define MIB_RXRUNT_2_E_LENGTH 4 -#define MIB_RXRUNT_2_E_OFFSET 0xa0 -#define MIB_RXRUNT_2_NR_E 6 - -#define MIB_RXFRAGMENT_2 "RxFragment_2" -#define MIB_RXFRAGMENT_2_ID 40 -#define MIB_RXFRAGMENT_2_OFFSET (MIB_RXFRAGMENT_OFFSET + 0x400) -#define MIB_RXFRAGMENT_2_E_LENGTH 4 -#define MIB_RXFRAGMENT_2_E_OFFSET 0xa0 -#define MIB_RXFRAGMENT_2_NR_E 6 - -#define MIB_RX64BYTE_2 "Rx64Byte_2" -#define MIB_RX64BYTE_2_ID 41 -#define MIB_RX64BYTE_2_OFFSET (MIB_RX64BYTE_OFFSET + 0x400) -#define MIB_RX64BYTE_2_E_LENGTH 4 -#define MIB_RX64BYTE_2_E_OFFSET 0xa0 -#define MIB_RX64BYTE_2_NR_E 6 - -#define MIB_RX128BYTE_2 "Rx128Byte_2" -#define MIB_RX128BYTE_2_ID 42 -#define MIB_RX128BYTE_2_OFFSET (MIB_RX128BYTE_OFFSET + 0x400) -#define MIB_RX128BYTE_2_E_LENGTH 4 -#define MIB_RX128BYTE_2_E_OFFSET 0xa0 -#define MIB_RX128BYTE_2_NR_E 6 - -#define MIB_RX256BYTE_2 "Rx256Byte_2" -#define MIB_RX256BYTE_2_ID 43 -#define MIB_RX256BYTE_2_OFFSET (MIB_RX256BYTE_OFFSET + 0x400) -#define MIB_RX256BYTE_2_E_LENGTH 4 -#define MIB_RX256BYTE_2_E_OFFSET 0xa0 -#define MIB_RX256BYTE_2_NR_E 6 - -#define MIB_RX512BYTE_2 "Rx512Byte_2" -#define MIB_RX512BYTE_2_ID 44 -#define MIB_RX512BYTE_2_OFFSET (MIB_RX512BYTE_OFFSET + 0x400) -#define MIB_RX512BYTE_2_E_LENGTH 4 -#define MIB_RX512BYTE_2_E_OFFSET 0xa0 -#define MIB_RX512BYTE_2_NR_E 6 - -#define MIB_RX1024BYTE_2 "Rx1024Byte_2" -#define MIB_RX1024BYTE_2_ID 45 -#define MIB_RX1024BYTE_2_OFFSET (MIB_RX1024BYTE_OFFSET + 0x400) -#define MIB_RX1024BYTE_2_E_LENGTH 4 -#define MIB_RX1024BYTE_2_E_OFFSET 0xa0 -#define MIB_RX1024BYTE_2_NR_E 6 - -#define MIB_RXMAXBYTE_2 "RxMaxByte_2" -#define MIB_RXMAXBYTE_2_ID 46 -#define MIB_RXMAXBYTE_2_OFFSET (MIB_RXMAXBYTE_OFFSET + 0x400) -#define MIB_RXMAXBYTE_2_E_LENGTH 4 -#define MIB_RXMAXBYTE_2_E_OFFSET 0xa0 -#define MIB_RXMAXBYTE_2_NR_E 6 - -#define MIB_RXTOOLONG_2 "RxTooLong_2" -#define MIB_RXTOOLONG_2_ID 47 -#define MIB_RXTOOLONG_2_OFFSET (MIB_RXTOOLONG_OFFSET + 0x400) -#define MIB_RXTOOLONG_2_E_LENGTH 4 -#define MIB_RXTOOLONG_2_E_OFFSET 0xa0 -#define MIB_RXTOOLONG_2_NR_E 6 - -#define MIB_RXGOODBYTE_LO_2 "RxGoodByteLo_2" -#define MIB_RXGOODBYTE_LO_2_ID 48 -#define MIB_RXGOODBYTE_LO_2_OFFSET (MIB_RXGOODBYTE_LO_OFFSET + 0x400) -#define MIB_RXGOODBYTE_LO_2_E_LENGTH 4 -#define MIB_RXGOODBYTE_LO_2_E_OFFSET 0xa0 -#define MIB_RXGOODBYTE_LO_2_NR_E 6 - -#define MIB_RXGOODBYTE_HI_2 "RxGoodByteHi_2" -#define MIB_RXGOODBYTE_HI_2_ID 49 -#define MIB_RXGOODBYTE_HI_2_OFFSET (MIB_RXGOODBYTE_HI_OFFSET + 0x400) -#define MIB_RXGOODBYTE_HI_2_E_LENGTH 4 -#define MIB_RXGOODBYTE_HI_2_E_OFFSET 0xa0 -#define MIB_RXGOODBYTE_HI_2_NR_E 6 - -#define MIB_RXBADBYTE_LO_2 "RxBadByteLo_2" -#define MIB_RXBADBYTE_LO_2_ID 50 -#define MIB_RXBADBYTE_LO_2_OFFSET (MIB_RXBADBYTE_LO_OFFSET + 0x400) -#define MIB_RXBADBYTE_LO_2_E_LENGTH 4 -#define MIB_RXBADBYTE_LO_2_E_OFFSET 0xa0 -#define MIB_RXBADBYTE_LO_2_NR_E 6 - -#define MIB_RXBADBYTE_HI_2 "RxBadByteHi_2" -#define MIB_RXBADBYTE_HI_2_ID 51 -#define MIB_RXBADBYTE_HI_2_OFFSET (MIB_RXBADBYTE_HI_OFFSET + 0x400) -#define MIB_RXBADBYTE_HI_2_E_LENGTH 4 -#define MIB_RXBADBYTE_HI_2_E_OFFSET 0xa0 -#define MIB_RXBADBYTE_HI_2_NR_E 6 - -#define MIB_RXOVERFLOW_2 "RxOverFlow_2" -#define MIB_RXOVERFLOW_2_ID 52 -#define MIB_RXOVERFLOW_2_OFFSET (MIB_RXOVERFLOW_OFFSET + 0x400) -#define MIB_RXOVERFLOW_2_E_LENGTH 4 -#define MIB_RXOVERFLOW_2_E_OFFSET 0xa0 -#define MIB_RXOVERFLOW_2_NR_E 6 - -#define MIB_FILTERED_2 "Filtered_2" -#define MIB_FILTERED_2_ID 53 -#define MIB_FILTERED_2_OFFSET (MIB_FILTERED_OFFSET + 0x400) -#define MIB_FILTERED_2_E_LENGTH 4 -#define MIB_FILTERED_2_E_OFFSET 0xa0 -#define MIB_FILTERED_2_NR_E 6 - -#define MIB_TXBROAD_2 "TxBroad_2" -#define MIB_TXBROAD_2_ID 54 -#define MIB_TXBROAD_2_OFFSET (MIB_TXBROAD_OFFSET + 0x400) -#define MIB_TXBROAD_2_E_LENGTH 4 -#define MIB_TXBROAD_2_E_OFFSET 0xa0 -#define MIB_TXBROAD_2_NR_E 6 - -#define MIB_TXPAUSE_2 "TxPause_2" -#define MIB_TXPAUSE_2_ID 55 -#define MIB_TXPAUSE_2_OFFSET (MIB_TXPAUSE_OFFSET + 0x400) -#define MIB_TXPAUSE_2_E_LENGTH 4 -#define MIB_TXPAUSE_2_E_OFFSET 0xa0 -#define MIB_TXPAUSE_2_NR_E 6 - -#define MIB_TXMULTI_2 "TxMulti_2" -#define MIB_TXMULTI_2_ID 56 -#define MIB_TXMULTI_2_OFFSET (MIB_TXMULTI_OFFSET + 0x400) -#define MIB_TXMULTI_2_E_LENGTH 4 -#define MIB_TXMULTI_2_E_OFFSET 0xa0 -#define MIB_TXMULTI_2_NR_E 6 - -#define MIB_TXUNDERRUN_2 "TxUnderRun_2" -#define MIB_TXUNDERRUN_2_ID 57 -#define MIB_TXUNDERRUN_2_OFFSET (MIB_TXUNDERRUN_OFFSET + 0x400) -#define MIB_TXUNDERRUN_2_E_LENGTH 4 -#define MIB_TXUNDERRUN_2_E_OFFSET 0xa0 -#define MIB_TXUNDERRUN_2_NR_E 6 - -#define MIB_TX64BYTE_2 "Tx64Byte_2" -#define MIB_TX64BYTE_2_ID 58 -#define MIB_TX64BYTE_2_OFFSET (MIB_TX64BYTE_OFFSET + 0x400) -#define MIB_TX64BYTE_2_E_LENGTH 4 -#define MIB_TX64BYTE_2_E_OFFSET 0xa0 -#define MIB_TX64BYTE_2_NR_E 6 - -#define MIB_TX128BYTE_2 "Tx128Byte_2" -#define MIB_TX128BYTE_2_ID 59 -#define MIB_TX128BYTE_2_OFFSET (MIB_TX128BYTE_OFFSET + 0x400) -#define MIB_TX128BYTE_2_E_LENGTH 4 -#define MIB_TX128BYTE_2_E_OFFSET 0xa0 -#define MIB_TX128BYTE_2_NR_E 6 - -#define MIB_TX256BYTE_2 "Tx256Byte_2" -#define MIB_TX256BYTE_2_ID 60 -#define MIB_TX256BYTE_2_OFFSET (MIB_TX256BYTE_OFFSET + 0x400) -#define MIB_TX256BYTE_2_E_LENGTH 4 -#define MIB_TX256BYTE_2_E_OFFSET 0xa0 -#define MIB_TX256BYTE_2_NR_E 6 - -#define MIB_TX512BYTE_2 "Tx512Byte_2" -#define MIB_TX512BYTE_2_ID 61 -#define MIB_TX512BYTE_2_OFFSET (MIB_TX512BYTE_OFFSET + 0x400) -#define MIB_TX512BYTE_2_E_LENGTH 4 -#define MIB_TX512BYTE_2_E_OFFSET 0xa0 -#define MIB_TX512BYTE_2_NR_E 6 - -#define MIB_TX1024BYTE_2 "Tx1024Byte_2" -#define MIB_TX1024BYTE_2_ID 62 -#define MIB_TX1024BYTE_2_OFFSET (MIB_TX1024BYTE_OFFSET + 0x400) -#define MIB_TX1024BYTE_2_E_LENGTH 4 -#define MIB_TX1024BYTE_2_E_OFFSET 0xa0 -#define MIB_TX1024BYTE_2_NR_E 6 - -#define MIB_TXMAXBYTE_2 "TxMaxByte_2" -#define MIB_TXMAXBYTE_2_ID 63 -#define MIB_TXMAXBYTE_2_OFFSET (MIB_TXMAXBYTE_OFFSET + 0x400) -#define MIB_TXMAXBYTE_2_E_LENGTH 4 -#define MIB_TXMAXBYTE_2_E_OFFSET 0xa0 -#define MIB_TXMAXBYTE_2_NR_E 6 - -#define MIB_TXOVERSIZE_2 "TxOverSize_2" -#define MIB_TXOVERSIZE_2_ID 64 -#define MIB_TXOVERSIZE_2_OFFSET (MIB_TXOVERSIZE_OFFSET + 0x400) -#define MIB_TXOVERSIZE_2_E_LENGTH 4 -#define MIB_TXOVERSIZE_2_E_OFFSET 0xa0 -#define MIB_TXOVERSIZE_2_NR_E 6 - -#define MIB_TXBYTE_LO_2 "TxByteLo_2" -#define MIB_TXBYTE_LO_2_ID 65 -#define MIB_TXBYTE_LO_2_OFFSET (MIB_TXBYTE_LO_OFFSET + 0x400) -#define MIB_TXBYTE_LO_2_E_LENGTH 4 -#define MIB_TXBYTE_LO_2_E_OFFSET 0xa0 -#define MIB_TXBYTE_LO_2_NR_E 6 - -#define MIB_TXBYTE_HI_2 "TxByteHi_2" -#define MIB_TXBYTE_HI_2_ID 66 -#define MIB_TXBYTE_HI_2_OFFSET (MIB_TXBYTE_HI_OFFSET + 0x400) -#define MIB_TXBYTE_HI_2_E_LENGTH 4 -#define MIB_TXBYTE_HI_2_E_OFFSET 0xa0 -#define MIB_TXBYTE_HI_2_NR_E 6 - -#define MIB_TXCOLLISION_2 "TxCollision_2" -#define MIB_TXCOLLISION_2_ID 67 -#define MIB_TXCOLLISION_2_OFFSET (MIB_TXCOLLISION_OFFSET + 0x400) -#define MIB_TXCOLLISION_2_E_LENGTH 4 -#define MIB_TXCOLLISION_2_E_OFFSET 0xa0 -#define MIB_TXCOLLISION_2_NR_E 6 - -#define MIB_TXABORTCOL_2 "TxAbortCol_2" -#define MIB_TXABORTCOL_2_ID 68 -#define MIB_TXABORTCOL_2_OFFSET (MIB_TXABORTCOL_OFFSET + 0x400) -#define MIB_TXABORTCOL_2_E_LENGTH 4 -#define MIB_TXABORTCOL_2_E_OFFSET 0xa0 -#define MIB_TXABORTCOL_2_NR_E 6 - -#define MIB_TXMULTICOL_2 "TxMultiCol_2" -#define MIB_TXMULTICOL_2_ID 69 -#define MIB_TXMULTICOL_2_OFFSET (MIB_TXMULTICOL_OFFSET + 0x400) -#define MIB_TXMULTICOL_2_E_LENGTH 4 -#define MIB_TXMULTICOL_2_E_OFFSET 0xa0 -#define MIB_TXMULTICOL_2_NR_E 6 - -#define MIB_TXSINGALCOL_2 "TxSingalCol_2" -#define MIB_TXSINGALCOL_2_ID 70 -#define MIB_TXSINGALCOL_2_OFFSET (MIB_TXSINGALCOL_OFFSET + 0x400) -#define MIB_TXSINGALCOL_2_E_LENGTH 4 -#define MIB_TXSINGALCOL_2_E_OFFSET 0xa0 -#define MIB_TXSINGALCOL_2_NR_E 6 - -#define MIB_TXEXCDEFER_2 "TxExcDefer_2" -#define MIB_TXEXCDEFER_2_ID 71 -#define MIB_TXEXCDEFER_2_OFFSET (MIB_TXEXCDEFER_OFFSET + 0x400) -#define MIB_TXEXCDEFER_2_E_LENGTH 4 -#define MIB_TXEXCDEFER_2_E_OFFSET 0xa0 -#define MIB_TXEXCDEFER_2_NR_E 6 - -#define MIB_TXDEFER_2 "TxDefer_2" -#define MIB_TXDEFER_2_ID 72 -#define MIB_TXDEFER_2_OFFSET (MIB_TXDEFER_OFFSET + 0x400) -#define MIB_TXDEFER_2_E_LENGTH 4 -#define MIB_TXDEFER_2_E_OFFSET 0xa0 -#define MIB_TXDEFER_2_NR_E 6 - -#define MIB_TXLATECOL_2 "TxLateCol_2" -#define MIB_TXLATECOL_2_ID 73 -#define MIB_TXLATECOL_2_OFFSET (MIB_TXLATECOL_OFFSET + 0x400) -#define MIB_TXLATECOL_2_E_LENGTH 4 -#define MIB_TXLATECOL_2_E_OFFSET 0xa0 -#define MIB_TXLATECOL_2_NR_E 6 - -#ifdef __cplusplus -} -#endif /* __cplusplus */ - -#endif /* _ATHENA_REG_H */ - diff --git a/feeds/ipq807x/qca-ssdk/src/include/hsl/athena/athena_reg_access.h b/feeds/ipq807x/qca-ssdk/src/include/hsl/athena/athena_reg_access.h deleted file mode 100755 index 60f4b2822..000000000 --- a/feeds/ipq807x/qca-ssdk/src/include/hsl/athena/athena_reg_access.h +++ /dev/null @@ -1,63 +0,0 @@ -/* - * Copyright (c) 2012,2018, The Linux Foundation. All rights reserved. - * Permission to use, copy, modify, and/or distribute this software for - * any purpose with or without fee is hereby granted, provided that the - * above copyright notice and this permission notice appear in all copies. - * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES - * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR - * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES - * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN - * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT - * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. - */ - - - -#ifndef _ATHENA_REG_ACCESS_H_ -#define _ATHENA_REG_ACCESS_H_ - -#ifdef __cplusplus -extern "C" { -#endif /* __cplusplus */ - -#include "sw.h" - - sw_error_t - athena_phy_get(a_uint32_t dev_id, a_uint32_t phy_addr, - a_uint32_t reg, a_uint16_t * value); - - sw_error_t - athena_phy_set(a_uint32_t dev_id, a_uint32_t phy_addr, - a_uint32_t reg, a_uint16_t value); - - sw_error_t - athena_reg_get(a_uint32_t dev_id, a_uint32_t reg_addr, a_uint8_t value[], - a_uint32_t value_len); - - sw_error_t - athena_reg_set(a_uint32_t dev_id, a_uint32_t reg_addr, a_uint8_t value[], - a_uint32_t value_len); - - sw_error_t - athena_reg_field_get(a_uint32_t dev_id, a_uint32_t reg_addr, - a_uint32_t bit_offset, a_uint32_t field_len, - a_uint8_t value[], a_uint32_t value_len); - - sw_error_t - athena_reg_field_set(a_uint32_t dev_id, a_uint32_t reg_addr, - a_uint32_t bit_offset, a_uint32_t field_len, - const a_uint8_t value[], a_uint32_t value_len); - - sw_error_t - athena_reg_access_init(a_uint32_t dev_id, hsl_access_mode mode); - - sw_error_t - athena_access_mode_set(a_uint32_t dev_id, hsl_access_mode mode); - -#ifdef __cplusplus -} -#endif /* __cplusplus */ - -#endif /* _ATHENA_REG_ACCESS_H_ */ - diff --git a/feeds/ipq807x/qca-ssdk/src/include/hsl/athena/athena_vlan.h b/feeds/ipq807x/qca-ssdk/src/include/hsl/athena/athena_vlan.h deleted file mode 100755 index 5e97c72ce..000000000 --- a/feeds/ipq807x/qca-ssdk/src/include/hsl/athena/athena_vlan.h +++ /dev/null @@ -1,94 +0,0 @@ -/* - * Copyright (c) 2012, The Linux Foundation. All rights reserved. - * Permission to use, copy, modify, and/or distribute this software for - * any purpose with or without fee is hereby granted, provided that the - * above copyright notice and this permission notice appear in all copies. - * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES - * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR - * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES - * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN - * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT - * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. - */ - - -#ifndef _ATHENA_VLAN_H -#define _ATHENA_VLAN_H - -#ifdef __cplusplus -extern "C" { -#endif /* __cplusplus */ - -#include "fal/fal_vlan.h" - - sw_error_t - athena_vlan_reset(a_uint32_t dev_id); - - sw_error_t - athena_vlan_init(a_uint32_t dev_id); - - sw_error_t - athena_vlan_cleanup(a_uint32_t dev_id); - -#ifdef IN_VLAN -#define ATHENA_VLAN_RESET(rv, dev_id) \ - { \ - rv = athena_vlan_reset(dev_id); \ - SW_RTN_ON_ERROR(rv); \ - } - -#define ATHENA_VLAN_INIT(rv, dev_id) \ - { \ - rv = athena_vlan_init(dev_id); \ - SW_RTN_ON_ERROR(rv); \ - } - -#define ATHENA_VLAN_CLEANUP(rv, dev_id) \ - { \ - rv = athena_vlan_cleanup(dev_id); \ - SW_RTN_ON_ERROR(rv); \ - } -#else -#define ATHENA_VLAN_RESET(rv, dev_id) -#define ATHENA_VLAN_INIT(rv, dev_id) -#define ATHENA_VLAN_CLEANUP(rv, dev_id) -#endif - -#ifdef HSL_STANDALONG - - - HSL_LOCAL sw_error_t - athena_vlan_entry_append(a_uint32_t dev_id, const fal_vlan_t * vlan_entry); - - - - HSL_LOCAL sw_error_t - athena_vlan_create(a_uint32_t dev_id, a_uint32_t vlan_id); - - - - HSL_LOCAL sw_error_t - athena_vlan_next(a_uint32_t dev_id, a_uint32_t vlan_id, fal_vlan_t * p_vlan); - - - - HSL_LOCAL sw_error_t - athena_vlan_find(a_uint32_t dev_id, a_uint32_t vlan_id, fal_vlan_t * p_vlan); - - - - HSL_LOCAL sw_error_t - athena_vlan_member_update(a_uint32_t dev_id, a_uint32_t vlan_id, - fal_pbmp_t member, fal_pbmp_t u_member); - - - HSL_LOCAL sw_error_t - athena_vlan_delete(a_uint32_t dev_id, a_uint32_t vlan_id); -#endif - -#ifdef __cplusplus -} -#endif /* __cplusplus */ - -#endif /* _ATHENA_VLAN_H */ diff --git a/feeds/ipq807x/qca-ssdk/src/include/hsl/cppe/cppe_loopback.h b/feeds/ipq807x/qca-ssdk/src/include/hsl/cppe/cppe_loopback.h deleted file mode 100755 index ed9ff8c2f..000000000 --- a/feeds/ipq807x/qca-ssdk/src/include/hsl/cppe/cppe_loopback.h +++ /dev/null @@ -1,213 +0,0 @@ -/* - * Copyright (c) 2019, The Linux Foundation. All rights reserved. - * Permission to use, copy, modify, and/or distribute this software for - * any purpose with or without fee is hereby granted, provided that the - * above copyright notice and this permission notice appear in all copies. - * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES - * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR - * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES - * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN - * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT - * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. - */ -/** - * @defgroup - * @{ - */ -#ifndef _CPPE_LOOPBACK_H_ -#define _CPPE_LOOPBACK_H_ - -sw_error_t -cppe_lpbk_enable_get( - a_uint32_t dev_id, - a_uint32_t index, - union lpbk_enable_u *value); - -sw_error_t -cppe_lpbk_enable_set( - a_uint32_t dev_id, - a_uint32_t index, - union lpbk_enable_u *value); - -sw_error_t -cppe_lpbk_fifo_1_ctrl_get( - a_uint32_t dev_id, - a_uint32_t index, - union lpbk_fifo_1_ctrl_u *value); - -sw_error_t -cppe_lpbk_fifo_1_ctrl_set( - a_uint32_t dev_id, - a_uint32_t index, - union lpbk_fifo_1_ctrl_u *value); - -sw_error_t -cppe_lpbk_fifo_2_ctrl_get( - a_uint32_t dev_id, - a_uint32_t index, - union lpbk_fifo_2_ctrl_u *value); - -sw_error_t -cppe_lpbk_fifo_2_ctrl_set( - a_uint32_t dev_id, - a_uint32_t index, - union lpbk_fifo_2_ctrl_u *value); - -sw_error_t -cppe_lpbk_pps_ctrl_get( - a_uint32_t dev_id, - a_uint32_t index, - union lpbk_pps_ctrl_u *value); - -sw_error_t -cppe_lpbk_pps_ctrl_set( - a_uint32_t dev_id, - a_uint32_t index, - union lpbk_pps_ctrl_u *value); - -sw_error_t -cppe_lpbk_mac_junmo_size_get( - a_uint32_t dev_id, - a_uint32_t index, - union lpbk_mac_junmo_size_u *value); - -sw_error_t -cppe_lpbk_mac_junmo_size_set( - a_uint32_t dev_id, - a_uint32_t index, - union lpbk_mac_junmo_size_u *value); - -sw_error_t -cppe_lpbk_mib_ctrl_get( - a_uint32_t dev_id, - a_uint32_t index, - union lpbk_mib_ctrl_u *value); - -sw_error_t -cppe_lpbk_mib_ctrl_set( - a_uint32_t dev_id, - a_uint32_t index, - union lpbk_mib_ctrl_u *value); - -sw_error_t -cppe_lpbk_mib_uni_get( - a_uint32_t dev_id, - a_uint32_t index, - union lpbkuni_u *value); - -sw_error_t -cppe_lpbk_mib_multi_get( - a_uint32_t dev_id, - a_uint32_t index, - union lpbkmulti_u *value); - -sw_error_t -cppe_lpbk_mib_broad_get( - a_uint32_t dev_id, - a_uint32_t index, - union lpbkbroad_u *value); - -sw_error_t -cppe_lpbk_mib_pkt64_get( - a_uint32_t dev_id, - a_uint32_t index, - union lpbkpkt64_u *value); - -sw_error_t -cppe_lpbk_mib_pkt65to127_get( - a_uint32_t dev_id, - a_uint32_t index, - union lpbkpkt65to127_u *value); - -sw_error_t -cppe_lpbk_mib_pkt128to255_get( - a_uint32_t dev_id, - a_uint32_t index, - union lpbkpkt128to255_u *value); - -sw_error_t -cppe_lpbk_mib_pkt256to511_get( - a_uint32_t dev_id, - a_uint32_t index, - union lpbkpkt256to511_u *value); - -sw_error_t -cppe_lpbk_mib_pkt512to1023_get( - a_uint32_t dev_id, - a_uint32_t index, - union lpbkpkt512to1023_u *value); - -sw_error_t -cppe_lpbk_mib_pkt1024to1518_get( - a_uint32_t dev_id, - a_uint32_t index, - union lpbkpkt1024to1518_u *value); - -sw_error_t -cppe_lpbk_mib_pkt1519tox_get( - a_uint32_t dev_id, - a_uint32_t index, - union lpbkpkt1519tox_u *value); - -sw_error_t -cppe_lpbk_mib_toolong_get( - a_uint32_t dev_id, - a_uint32_t index, - union lpbkpkttoolong_u *value); - -sw_error_t -cppe_lpbk_mib_byte_l_get( - a_uint32_t dev_id, - a_uint32_t index, - union lpbkbyte_l_u *value); - -sw_error_t -cppe_lpbk_mib_byte_h_get( - a_uint32_t dev_id, - a_uint32_t index, - union lpbkbyte_h_u *value); - -sw_error_t -cppe_lpbk_mib_drop_get( - a_uint32_t dev_id, - a_uint32_t index, - union lpbkdropcounter_u *value); - -sw_error_t -cppe_lpbk_mib_tooshort_get( - a_uint32_t dev_id, - a_uint32_t index, - union lpbkpkttooshort_u *value); - -sw_error_t -cppe_lpbk_mib_pkt14to63_get( - a_uint32_t dev_id, - a_uint32_t index, - union lpbkpkt14to63_u *value); - -sw_error_t -cppe_lpbk_mib_toolongbyte_l_get( - a_uint32_t dev_id, - a_uint32_t index, - union lpbktoolongbyte_l_u *value); - -sw_error_t -cppe_lpbk_mib_toolongbyte_h_get( - a_uint32_t dev_id, - a_uint32_t index, - union lpbktoolongbyte_h_u *value); - - -sw_error_t -cppe_lpbk_mib_tooshortbyte_l_get( - a_uint32_t dev_id, - a_uint32_t index, - union lpbktooshortbyte_l_u *value); - -sw_error_t -cppe_lpbk_mib_tooshortbyte_h_get( - a_uint32_t dev_id, - a_uint32_t index, - union lpbktooshortbyte_h_u *value); -#endif diff --git a/feeds/ipq807x/qca-ssdk/src/include/hsl/cppe/cppe_loopback_reg.h b/feeds/ipq807x/qca-ssdk/src/include/hsl/cppe/cppe_loopback_reg.h deleted file mode 100755 index 899e8cf67..000000000 --- a/feeds/ipq807x/qca-ssdk/src/include/hsl/cppe/cppe_loopback_reg.h +++ /dev/null @@ -1,578 +0,0 @@ -/* - * Copyright (c) 2019, The Linux Foundation. All rights reserved. - * Permission to use, copy, modify, and/or distribute this software for - * any purpose with or without fee is hereby granted, provided that the - * above copyright notice and this permission notice appear in all copies. - * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES - * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR - * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES - * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN - * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT - * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. - */ -/** - * @defgroup - * @{ - */ -#ifndef CPPE_LOOPBACK_REG_H -#define CPPE_LOOPBACK_REG_H - -/*[register] LPBK_ENABLE*/ -#define LPBK_ENABLE -#define LPBK_ENABLE_ADDRESS 0x00 -#define LPBK_ENABLE_NUM 6 -#define LPBK_ENABLEL_INC 0x200 -#define LPBK_ENABLE_TYPE REG_TYPE_RW -#define LPBK_ENABLE_DEFAULT 0x0 - /*[field] LPBK_EN*/ - #define LPBK_EN_LPBK_EN - #define LPBK_EN_LPBK_EN_OFFSET 0 - #define LPBK_EN_LPBK_EN_LEN 1 - #define LLPBK_EN_LPBK_EN_DEFAULT 0x0 - /*[field] FLOWCTRL_EN*/ - #define LPBK_ENABLE_FLOWCTRL_EN - #define LPBK_ENABLE_FLOWCTRL_EN_OFFSET 1 - #define LPBK_ENABLE_FLOWCTRL_EN_LEN 1 - #define LPBK_ENABLE_FLOWCTRL_EN_DEFAULT 0x1 - /*[field] FLOWCTRL_MODE*/ - #define LPBK_EN_FLOWCTRL_MODE - #define LPBK_EN_FLOWCTRL_MODE_OFFSET 2 - #define LPBK_EN_FLOWCTRL_MODE_LEN 1 - #define LPBK_EN_FLOWCTRL_MODE_DEFAULT 0x0 - /*[field] CRC_STRIP_EN*/ - #define LPBK_EN_CRC_STRIP_EN - #define LPBK_EN_CRC_STRIP_EN_OFFSET 2 - #define LPBK_EN_CRC_STRIP_EN_LEN 1 - #define LPBK_EN_CRC_STRIP_EN_DEFAULT 0x1 -struct lpbk_enable { - a_uint32_t lpbk_en:1; - a_uint32_t flowctrl_en :1; - a_uint32_t flowctrl_mode:1; - a_uint32_t crc_strip_en:1; - a_uint32_t _reserved0:28; -}; -union lpbk_enable_u { - a_uint32_t val; - struct lpbk_enable bf; -}; - -/*[register] LPBK_FIFO_1_CTRL*/ -#define LPBK_FIFO_1_CTRL -#define LPBK_FIFO_1_CTRL_ADDRESS 0x04 -#define LPBK_FIFO_1_CTRL_NUM 6 -#define LPBK_FIFO_1_CTRL_INC 0x200 -#define LPBK_FIFO_1_CTRL_TYPE REG_TYPE_RW -#define LPBK_FIFO_1_CTRL_DEFAULT 0x3 - /*[field] LPBK_FIFO_1_THRESHOLD*/ - #define LPBK_FIFO_1_CTRL_LPBK_FIFO_1_THRESHOLD - #define LPBK_FIFO_1_CTRL_LPBK_FIFO_1_THRESHOLD_OFFSET 0 - #define LPBK_FIFO_1_CTRL_LPBK_FIFO_1_THRESHOLD_LEN 3 - #define LPBK_FIFO_1_CTRL_LPBK_FIFO_1_THRESHOLD_DEFAULT 0x0 -struct lpbk_fifo_1_ctrl { - a_uint32_t lpbk_fifo_1_threshold:3; - a_uint32_t _reserved0:29; -}; -union lpbk_fifo_1_ctrl_u { - a_uint32_t val; - struct lpbk_fifo_1_ctrl bf; -}; - -/*[register] LPBK_FIFO_2_CTRL*/ -#define LPBK_FIFO_2_CTRL -#define LPBK_FIFO_2_CTRL_ADDRESS 0x08 -#define LPBK_FIFO_2_CTRL_NUM 6 -#define LPBK_FIFO_2_CTRL_INC 0x200 -#define LPBK_FIFO_2_CTRL_TYPE REG_TYPE_RW -#define LPBK_FIFO_2_CTRL_DEFAULT 0x1 - /*[field] LPBK_FIFO_2_THRESHOLD*/ - #define LPBK_FIFO_2_CTRL_LPBK_FIFO_2_THRESHOLD - #define LPBK_FIFO_2_CTRL_LPBK_FIFO_2_THRESHOLD_OFFSET 0 - #define LPBK_FIFO_2_CTRL_LPBK_FIFO_2_THRESHOLD_LEN 3 - #define LPBK_FIFO_2_CTRL_LPBK_FIFO_2_THRESHOLD_DEFAULT 0x0 -struct lpbk_fifo_2_ctrl { - a_uint32_t lpbk_fifo_2_threshold:3; - a_uint32_t _reserved0:29; -}; -union lpbk_fifo_2_ctrl_u { - a_uint32_t val; - struct lpbk_fifo_2_ctrl bf; -}; - -/*[register] LPBK_PPS_CTRL*/ -#define LPBK_PPS_CTRL -#define LPBK_PPS_CTRL_ADDRESS 0x0c -#define LPBK_PPS_CTRL_NUM 6 -#define LPBK_PPS_CTRL_INC 0x200 -#define LPBK_PPS_CTRL_TYPE REG_TYPE_RW -#define LPBK_PPS_CTRL_DEFAULT 0x0 - /*[field] LPBK_PPS_THRESHOLD*/ - #define LPBK_PPS_CTRL_LPBK_PPS_THRESHOLD - #define LPBK_PPS_CTRL_LPBK_PPS_THRESHOLD_OFFSET 0 - #define LPBK_PPS_CTRL_LPBK_PPS_THRESHOLD_LEN 9 - #define LPBK_PPS_CTRL_LPBK_PPS_THRESHOLD_DEFAULT 0x16 -struct lpbk_pps_ctrl { - a_uint32_t lpbk_pps_threshold:9; - a_uint32_t _reserved0:13; -}; -union lpbk_pps_ctrl_u { - a_uint32_t val; - struct lpbk_pps_ctrl bf; -}; - -/*[register] LPBK_MAC_JUNMO_SIZE*/ -#define LPBK_MAC_JUNMO_SIZE -#define LPBK_MAC_JUNMO_SIZE_ADDRESS 0x10 -#define LPBK_MAC_JUNMO_SIZE_NUM 6 -#define LPBK_MAC_JUNMO_SIZE_INC 0x200 -#define LPBK_MAC_JUNMO_SIZE_TYPE REG_TYPE_RW -#define LPBK_MAC_JUNMO_SIZE_DEFAULT 0x0 - /*[field] LPBK_MAC_JUMBO_SIZE*/ - #define LPBK_MAC_JUNMO_SIZE_LPBK_MAC_JUMBO_SIZE - #define LPBK_MAC_JUNMO_SIZE_LPBK_MAC_JUMBO_SIZE_OFFSET 0 - #define LPBK_MAC_JUNMO_SIZE_LPBK_MAC_JUMBO_SIZE_LEN 14 - #define LPBK_MAC_JUNMO_SIZE_LPBK_MAC_JUMBO_SIZE_DEFAULT 0x5EA -struct lpbk_mac_junmo_size { - a_uint32_t lpbk_mac_jumbo_size:14; - a_uint32_t _reserved0:18; -}; -union lpbk_mac_junmo_size_u { - a_uint32_t val; - struct lpbk_mac_junmo_size bf; -}; - -/*[register] LPBK_MIB_CTRL*/ -#define LPBK_MIB_CTRL -#define LPBK_MIB_CTRL_ADDRESS 0x14 -#define LPBK_MIB_CTRL_NUM 6 -#define LPBK_MIB_CTRL_INC 0x200 -#define LPBK_MIB_CTRL_TYPE REG_TYPE_RW -#define LPBK_MIB_CTRL_DEFAULT 0x0 - /*[field] MIB_EN*/ - #define LPBK_MIB_CTRL_MIB_EN - #define LPBK_MIB_CTRL_MIB_EN_OFFSET 0 - #define LPBK_MIB_CTRL_MIB_EN_LEN 1 - #define LPBK_MIB_CTRL_MIB_EN_DEFAULT 0x1 - /*[field] MIB_RESET*/ - #define LPBK_MIB_CTRL_MIB_RESET - #define LPBK_MIB_CTRL_MIB_RESET_OFFSET 1 - #define LPBK_MIB_CTRL_MIB_RESET_LEN 1 - #define LPBK_MIB_CTRL_MIB_RESET_DEFAULT 0x0 - /*[field] MIB_RD_CLR*/ - #define LPBK_MIB_CTRL_MIB_RD_CLR - #define LPBK_MIB_CTRL_MIB_RD_CLR_OFFSET 2 - #define LPBK_MIB_CTRL_MIB_RD_CLR_LEN 1 - #define LPBK_MIB_CTRL_MIB_RD_CLR_DEFAULT 0x0 -struct lpbk_mib_ctrl { - a_uint32_t mib_en:1; - a_uint32_t mib_reset:1; - a_uint32_t mib_rd_clr:1; - a_uint32_t _reserved0:29; -}; -union lpbk_mib_ctrl_u { - a_uint32_t val; - struct lpbk_mib_ctrl bf; -}; - -/*[register] LPBKUNI*/ -#define LPBKUNI -#define LPBKUNI_ADDRESS 0x20 -#define LPBKUNI_NUM 6 -#define LPBKUNI_INC 0x200 -#define LPBKUNI_TYPE REG_TYPE_RO -#define LPBKUNI_DEFAULT 0x0 - /*[field] LPBKUNI*/ - #define LPBKUNI_LPBKUNI - #define LPBKUNI_LPBKUNI_OFFSET 0 - #define LPBKUNI_LPBKUNI_LEN 32 - #define LPBKUNI_LPBKUNI_DEFAULT 0x0 -struct lpbkuni { - a_uint32_t lpbkuni:32; -}; -union lpbkuni_u { - a_uint32_t val; - struct lpbkuni bf; -}; - -/*[register] LPBKMULTI*/ -#define LPBKMULTI -#define LPBKMULTI_ADDRESS 0x24 -#define LPBKMULTI_NUM 6 -#define LPBKMULTI_INC 0x200 -#define LPBKMULTI_TYPE REG_TYPE_RO -#define LPBKMULTI_DEFAULT 0x0 - /*[field] LPBKMULTI*/ - #define LPBKMULTI_LPBKMULTI - #define LPBKMULTI_LPBKMULTI_OFFSET 0 - #define LPBKMULTI_LPBKMULTI_LEN 32 - #define LPBKMULTI_LPBKMULTI_DEFAULT 0x0 -struct lpbkmulti { - a_uint32_t lpbkmulti:32; -}; -union lpbkmulti_u { - a_uint32_t val; - struct lpbkmulti bf; -}; - -/*[register] LPBKBROAD*/ -#define LPBKBROAD -#define LPBKBROAD_ADDRESS 0x28 -#define LPBKBROAD_NUM 6 -#define LPBKBROAD_INC 0x200 -#define LPBKBROAD_TYPE REG_TYPE_RO -#define LPBKBROAD_DEFAULT 0x0 - /*[field] LPBK_BROAD*/ - #define LPBKBROAD_LPBKBROAD - #define LPBKBROAD_LPBKBROAD_OFFSET 0 - #define LPBKBROAD_LPBKBROAD_LEN 32 - #define LPBKBROAD_LPBKBROAD_DEFAULT 0x0 -struct lpbkbroad { - a_uint32_t lpbkbroad:32; -}; -union lpbkbroad_u { - a_uint32_t val; - struct lpbkbroad bf; -}; - -/*[register] LPBKPKT64*/ -#define LPBKPKT64 -#define LPBKPKT64_ADDRESS 0x2c -#define LPBKPKT64_NUM 6 -#define LPBKPKT64_INC 0x200 -#define LPBKPKT64_TYPE REG_TYPE_RO -#define LPBKPKT64_DEFAULT 0x0 - /*[field] LPBKPKT64*/ - #define LPBKPKT64_LPBKPKT64 - #define LPBKPKT64_LPBKPKT64_OFFSET 0 - #define LPBKPKT64_LPBKPKT64_LEN 32 - #define LPBKPKT64_LPBKPKT64_DEFAULT 0x0 -struct lpbkpkt64 { - a_uint32_t lpbkpkt64:32; -}; -union lpbkpkt64_u { - a_uint32_t val; - struct lpbkpkt64 bf; -}; - -/*[register] LPBKPKT65TO127*/ -#define LPBKPKT65TO127 -#define LPBKPKT65TO127_ADDRESS 0x30 -#define LPBKPKT65TO127_NUM 6 -#define LPBKPKT65TO127_INC 0x200 -#define LPBKPKT65TO127_TYPE REG_TYPE_RO -#define LPBKPKT65TO1277_DEFAULT 0x0 - /*[field] LPBKPKT65TO127*/ - #define LPBKPKT65TO127_LPBKPKT65TO127 - #define LPBKPKT65TO127_LPBKPKT65TO127_OFFSET 0 - #define LPBKPKT65TO127_LPBKPKT65TO127_LEN 32 - #define LPBKPKT65TO127_LPBKPKT65TO127_DEFAULT 0x0 -struct lpbkpkt65to127 { - a_uint32_t lpbkpkt65to127:32; -}; -union lpbkpkt65to127_u { - a_uint32_t val; - struct lpbkpkt65to127 bf; -}; - -/*[register] LPBKPKT128TO255*/ -#define LPBKPKT128TO255 -#define LPBKPKT128TO255_ADDRESS 0x34 -#define LPBKPKT128TO255_NUM 6 -#define LPBKPKT128TO255_INC 0x200 -#define LPBKPKT128TO255_TYPE REG_TYPE_RO -#define LPBKPKT128TO255_DEFAULT 0x0 - /*[field] LPBKPKT128TO255*/ - #define LPBKPKT128TO255_LPBKPKT128TO255 - #define LPBKPKT128TO255_LPBKPKT128TO255_OFFSET 0 - #define LPBKPKT128TO255_LPBKPKT128TO255_LEN 32 - #define LPBKPKT128TO255_LPBKPKT128TO255_DEFAULT 0x0 -struct lpbkpkt128to255 { - a_uint32_t lpbkpkt128to255:32; -}; -union lpbkpkt128to255_u { - a_uint32_t val; - struct lpbkpkt128to255 bf; -}; - -/*[register] LPBKPKT256TO511*/ -#define LPBKPKT256TO511 -#define LPBKPKT256TO511_ADDRESS 0x38 -#define LPBKPKT256TO511_NUM 6 -#define LPBKPKT256TO511_INC 0x200 -#define LPBKPKT256TO511_TYPE REG_TYPE_RO -#define LPBKPKT256TO511_DEFAULT 0x0 - /*[field] LPBKPKT256TO511*/ - #define LPBKPKT256TO511_LPBKPKT256TO511 - #define LPBKPKT256TO511_LPBKPKT256TO511_OFFSET 0 - #define LPBKPKT256TO511_LPBKPKT256TO511_LEN 32 - #define LPBKPKT256TO511_LPBKPKT256TO511_DEFAULT 0x0 -struct lpbkpkt256to511 { - a_uint32_t lpbkpkt256to511:32; -}; -union lpbkpkt256to511_u { - a_uint32_t val; - struct lpbkpkt256to511 bf; -}; - -/*[register] LPBKPKT512TO1023*/ -#define LPBKPKT512TO1023 -#define LPBKPKT512TO1023_ADDRESS 0x3c -#define LPBKPKT512TO1023_NUM 6 -#define LPBKPKT512TO1023_INC 0x200 -#define LPBKPKT512TO1023_TYPE REG_TYPE_RO -#define LPBKPKT512TO1023_DEFAULT 0x0 - /*[field] LPBKPKT512TO1023*/ - #define LPBKPKT512TO1023_LPBKPKT512TO1023 - #define LPBKPKT512TO1023_LPBKPKT512TO1023_OFFSET 0 - #define LPBKPKT512TO1023_LPBKPKT512TO1023_LEN 32 - #define LPBKPKT512TO1023_LPBKPKT512TO1023_DEFAULT 0x0 -struct lpbkpkt512to1023 { - a_uint32_t lpbkpkt512to1023:32; -}; -union lpbkpkt512to1023_u { - a_uint32_t val; - struct lpbkpkt512to1023 bf; -}; - -/*[register] LPBKPKT1024TO1518*/ -#define LPBKPKT1024TO1518 -#define LPBKPKT1024TO1518_ADDRESS 0x40 -#define LPBKPKT1024TO1518_NUM 6 -#define LPBKPKT1024TO1518_INC 0x200 -#define LPBKPKT1024TO1518_TYPE REG_TYPE_RO -#define LPBKPKT1024TO1518_DEFAULT 0x0 - /*[field] RXPKT1024TO1518*/ - #define LPBKPKT1024TO1518_LPBKPKT1024TO1518 - #define LPBKPKT1024TO1518_OFFSET 0 - #define LPBKPKT1024TO1518_LEN 32 - #define LPBKPKT1024TO1518_DEFAULT 0x0 - -struct lpbkpkt1024to1518 { - a_uint32_t lpbkpkt1024to1518:32; -}; -union lpbkpkt1024to1518_u { - a_uint32_t val; - struct lpbkpkt1024to1518 bf; -}; - -/*[register] LPBKPKT1519TOX*/ -#define LPBKPKT1519TOX -#define LPBKPKT1519TOX_ADDRESS 0x44 -#define LPBKPKT1519TOX_NUM 6 -#define LPBKPKT1519TOX_INC 0x200 -#define LPBKPKT1519TOX_TYPE REG_TYPE_RO -#define LPBKPKT1519TOX_DEFAULT 0x0 - /*[field] RXPKT1519TOX*/ - #define LPBKPKT1519TOX_LPBKPKT1519TOX - #define LPBKPKT1519TOX_LPBKPKT1519TOX_OFFSET 0 - #define LPBKPKT1519TOX_LPBKPKT1519TOX_LEN 32 - #define LPBKPKT1519TOX_LPBKPKT1519TOX_DEFAULT 0x0 -struct lpbkpkt1519tox { - a_uint32_t lpbkpkt1519tox:32; -}; -union lpbkpkt1519tox_u { - a_uint32_t val; - struct lpbkpkt1519tox bf; -}; - -/*[register] LPBKPKTTOOLONG*/ -#define LPBKPKTTOOLONG -#define LPBKPKTTOOLONG_ADDRESS 0x48 -#define LPBKPKTTOOLONG_NUM 6 -#define LPBKPKTTOOLONG_INC 0x200 -#define LPBKPKTTOOLONG_TYPE REG_TYPE_RO -#define LPBKPKTTOOLONG_DEFAULT 0x0 - /*[field] RXTOOLONG*/ - #define LPBKPKTTOOLONG_LPBKPKTTOOLONG - #define LPBKPKTTOOLONG_LPBKPKTTOOLONG_OFFSET 0 - #define LPBKPKTTOOLONG_LPBKPKTTOOLONG_LEN 32 - #define LPBKPKTTOOLONG_LPBKPKTTOOLONG_DEFAULT 0x0 -struct lpbkpkttoolong { - a_uint32_t lpbkpkttoolong:32; -}; -union lpbkpkttoolong_u { - a_uint32_t val; - struct lpbkpkttoolong bf; -}; - -/*[register] LPBKBYTE_L*/ -#define LPBKBYTE_L -#define LPBKBYTE_L_ADDRESS 0x4c -#define LPBKBYTE_L_NUM 6 -#define LPBKBYTE_L_INC 0x200 -#define LPBKBYTE_L_TYPE REG_TYPE_RO -#define LPBKBYTE_L_DEFAULT 0x0 - /*[field] LPBKBYTE_L*/ - #define LPBKBYTE_L_LPBKBYTE_L - #define LPBKBYTE_L_LPBKBYTE_L_OFFSET 0 - #define LPBKBYTE_L_LPBKBYTE_L_LEN 32 - #define LPBKBYTE_L_LPBKBYTE_L_DEFAULT 0x0 -struct lpbkbyte_l { - a_uint32_t lpbkbyte_l:32; -}; -union lpbkbyte_l_u { - a_uint32_t val; - struct lpbkbyte_l bf; -}; - -/*[register] LPBKBYTE_H*/ -#define LPBKBYTE_H -#define LPBKBYTE_H_ADDRESS 0x50 -#define LPBKBYTE_H_NUM 6 -#define LPBKBYTE_H_INC 0x200 -#define LPBKBYTE_H_TYPE REG_TYPE_RO -#define LPBKBYTE_H_DEFAULT 0x0 - /*[field] LPBKBYTE_H*/ - #define LPBKBYTE_H_LPBKBYTE_H - #define LPBKBYTE_H_LPBKBYTE_H_OFFSET 0 - #define LPBKBYTE_H_LPBKBYTE_H_LEN 32 - #define LPBKBYTE_H_LPBKBYTE_H_DEFAULT 0x0 - -struct lpbkbyte_h { - a_uint32_t lpbkbyte_h:32; -}; -union lpbkbyte_h_u { - a_uint32_t val; - struct lpbkbyte_h bf; -}; - -/*[register] LPBKDROPCOUNTER*/ -#define LPBKDROPCOUNTER -#define LPBKDROPCOUNTER_ADDRESS 0x54 -#define LPBKDROPCOUNTER_NUM 6 -#define LPBKDROPCOUNTER_INC 0x200 -#define LPBKDROPCOUNTER_TYPE REG_TYPE_RO -#define LPBKDROPCOUNTER_DEFAULT 0x0 - /*[field] LPBKDROPCOUNTER*/ - #define LPBKDROPCOUNTER_LPBKDROPCOUNTER - #define LPBKDROPCOUNTER_OFFSET 0 - #define LPBKDROPCOUNTER_LEN 32 - #define LPBKDROPCOUNTER_DEFAULT 0x0 -struct lpbkdropcounter { - a_uint32_t lpbkdropcounter:32; -}; -union lpbkdropcounter_u { - a_uint32_t val; - struct lpbkdropcounter bf; -}; - -/*[register] LPBKTOOSHORT*/ -#define LPBKPKTTOOSHORT -#define LPBKPKTTOOSHORT_ADDRESS 0x68 -#define LPBKPKTTOOSHORT_NUM 6 -#define LPBKPKTTOOSHORT_INC 0x200 -#define LPBKPKTTOOSHORT_TYPE REG_TYPE_RO -#define LPBKPKTTOOSHORT_DEFAULT 0x0 - /*[field] LPBKPKTTOOSHORT*/ - #define LPBKPKTTOOSHORT_LPBKPKTTOOSHORT - #define LPBKPKTTOOSHORT_OFFSET 0 - #define LPBKPKTTOOSHORT_LEN 32 - #define LPBKPKTTOOSHORT_DEFAULT 0x0 -struct lpbkpkttooshort { - a_uint32_t lpbkpkttooshort:32; -}; -union lpbkpkttooshort_u { - a_uint32_t val; - struct lpbkpkttooshort bf; -}; - -/*[register] LPBKPKT14TO63*/ -#define LPBKPKT14TO63 -#define LPBKPKT14TO63_ADDRESS 0x6c -#define LPBKPKT14TO63_NUM 6 -#define LPBKPKT14TO63_INC 0x200 -#define LPBKPKT14TO63_TYPE REG_TYPE_RO -#define LPBKPKT14TO63_DEFAULT 0x0 - /*[field] LPBKPKT14TO63*/ - #define LPBKPKT14TO63_LPBKPKT14TO63 - #define LPBKPKT14TO63_OFFSET 0 - #define LPBKPKT14TO63_LEN 32 - #define LPBKPKT14TO63_DEFAULT 0x0 -struct lpbkpkt14to63 { - a_uint32_t lpbkpkt14to63:32; -}; -union lpbkpkt14to63_u { - a_uint32_t val; - struct lpbkpkt14to63 bf; -}; - -/*[register] LPBKTOOLONGBYTE_L*/ -#define LPBKTOOLONGBYTE_L -#define LPBKTOOLONGBYTE_L_ADDRESS 0x70 -#define LPBKTOOLONGBYTE_L_NUM 6 -#define LPBKTOOLONGBYTE_L_INC 0x200 -#define LPBKTOOLONGBYTE_L_TYPE REG_TYPE_RO -#define LPBKTOOLONGBYTE_L_DEFAULT 0x0 - /*[field] LPBKTOOLONGBYTE_L*/ - #define LPBKTOOLONGBYTE_L_LPBKTOOLONGBYTE_L - #define LPBKTOOLONGBYTE_L_LPBKTOOLONGBYTE_L_OFFSET 0 - #define LPBKTOOLONGBYTE_L_LPBKTOOLONGBYTE_L_LEN 32 - #define LPBKTOOLONGBYTE_L_LPBKTOOLONGBYTE_L_DEFAULT 0x0 -struct lpbktoolongbyte_l { - a_uint32_t lpbktoolongbyte_l:32; -}; -union lpbktoolongbyte_l_u { - a_uint32_t val; - struct lpbktoolongbyte_l bf; -}; - -/*[register] LPBKTOOLONGBYTE_H*/ -#define LPBKTOOLONGBYTE_H -#define LPBKTOOLONGBYTE_H_ADDRESS 0x74 -#define LPBKTOOLONGBYTE_H_NUM 6 -#define LPBKTOOLONGBYTE_H_INC 0x200 -#define LPBKTOOLONGBYTE_H_TYPE REG_TYPE_RO -#define LPBKTOOLONGBYTE_H_DEFAULT 0x0 - /*[field] LPBKTOOLONGBYTE_L*/ - #define LPBKTOOLONGBYTE_H_LPBKTOOLONGBYTE_H - #define LPBKTOOLONGBYTE_H_LPBKTOOLONGBYTE_H_OFFSET 0 - #define LPBKTOOLONGBYTE_H_LPBKTOOLONGBYTE_H_LEN 32 - #define LPBKTOOLONGBYTE_H_LPBKTOOLONGBYTE_H_DEFAULT 0x0 -struct lpbktoolongbyte_h { - a_uint32_t lpbktoolongbyte_h:32; -}; -union lpbktoolongbyte_h_u { - a_uint32_t val; - struct lpbktoolongbyte_h bf; -}; - -/*[register] LPBKTOOSHORTBYTE_L*/ -#define LPBKTOOSHORTBYTE_L -#define LPBKTOOSHORTBYTE_L_ADDRESS 0x78 -#define LPBKTOOSHORTBYTE_L_NUM 6 -#define LPBKTOOSHORTBYTE_L_INC 0x200 -#define LPBKTOOLONGBYTE_L_TYPE REG_TYPE_RO -#define LPBKTOOLONGBYTE_L_DEFAULT 0x0 - /*[field] LPBKTOOLONGBYTE_L*/ - #define LPBKTOOSHORTBYTE_L_LPBKTOOSHORTBYTE_L - #define LPBKTOOSHORTBYTE_L_LPBKTOOSHORTBYTE_L_OFFSET 0 - #define LPBKTOOSHORTBYTE_L_LPBKTOOSHORTBYTE_L_LEN 32 - #define LPBKTOOSHORTBYTE_L_LPBKTOOSHORTBYTE_L_DEFAULT 0x0 -struct lpbktooshortbyte_l { - a_uint32_t lpbktooshortbyte_l:32; -}; -union lpbktooshortbyte_l_u { - a_uint32_t val; - struct lpbktooshortbyte_l bf; -}; - -/*[register] LPBKTOOSHORTBYTE_H*/ -#define LPBKTOOSHORTBYTE_H -#define LPBKTOOSHORTBYTE_H_ADDRESS 0x7c -#define LPBKTOOSHORTBYTE_H_NUM 6 -#define LPBKTOOSHORTBYTE_H_INC 0x200 -#define LPBKTOOSHORTBYTE_H_TYPE REG_TYPE_RO -#define LPBKTOOSHORTBYTE_H_DEFAULT 0x0 - /*[field] LPBKTOOLONGBYTE_L*/ - #define LPBKTOOSHORTBYTE_H_LPBKTOOSHORTBYTE_H - #define LPBKTOOSHORTBYTE_H_OFFSET 0 - #define LPBKTOOSHORTBYTE_H_LEN 32 - #define LPBKTOOSHORTBYTE_H_DEFAULT 0x0 -struct lpbktooshortbyte_h { - a_uint32_t lpbktooshortbyte_h:32; -}; -union lpbktooshortbyte_h_u { - a_uint32_t val; - struct lpbktooshortbyte_h bf; -}; -#endif diff --git a/feeds/ipq807x/qca-ssdk/src/include/hsl/cppe/cppe_portctrl.h b/feeds/ipq807x/qca-ssdk/src/include/hsl/cppe/cppe_portctrl.h deleted file mode 100755 index b211c8c41..000000000 --- a/feeds/ipq807x/qca-ssdk/src/include/hsl/cppe/cppe_portctrl.h +++ /dev/null @@ -1,204 +0,0 @@ -/* - * Copyright (c) 2018-2019, The Linux Foundation. All rights reserved. - * Permission to use, copy, modify, and/or distribute this software for - * any purpose with or without fee is hereby granted, provided that the - * above copyright notice and this permission notice appear in all copies. - * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES - * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR - * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES - * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN - * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT - * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. - */ - - -/** - * @defgroup - * @{ - */ -#ifndef _CPPE_PORTCTRL_H_ -#define _CPPE_PORTCTRL_H_ -#include "cppe_portctrl_reg.h" - -#define CPPE_MRU_MTU_CTRL_TBL_MAX_ENTRY 256 - -sw_error_t -cppe_mru_mtu_ctrl_tbl_dscp_res_prec_force_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -cppe_mru_mtu_ctrl_tbl_dscp_res_prec_force_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -cppe_mru_mtu_ctrl_tbl_pcp_res_prec_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -cppe_mru_mtu_ctrl_tbl_pcp_res_prec_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -cppe_mru_mtu_ctrl_tbl_pcp_qos_group_id_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -cppe_mru_mtu_ctrl_tbl_pcp_qos_group_id_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -cppe_mru_mtu_ctrl_tbl_pcp_res_prec_force_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -cppe_mru_mtu_ctrl_tbl_pcp_res_prec_force_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -cppe_mru_mtu_ctrl_tbl_post_acl_res_prec_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -cppe_mru_mtu_ctrl_tbl_post_acl_res_prec_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -cppe_mru_mtu_ctrl_tbl_preheader_res_prec_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -cppe_mru_mtu_ctrl_tbl_preheader_res_prec_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -cppe_mru_mtu_ctrl_tbl_dscp_res_prec_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -cppe_mru_mtu_ctrl_tbl_dscp_res_prec_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -cppe_mru_mtu_ctrl_tbl_pre_acl_res_prec_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -cppe_mru_mtu_ctrl_tbl_pre_acl_res_prec_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -cppe_mru_mtu_ctrl_tbl_flow_res_prec_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -cppe_mru_mtu_ctrl_tbl_flow_res_prec_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -cppe_mru_mtu_ctrl_tbl_dscp_qos_group_id_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -cppe_mru_mtu_ctrl_tbl_dscp_qos_group_id_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -cppe_mru_mtu_ctrl_tbl_src_profile_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -cppe_mru_mtu_ctrl_tbl_src_profile_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -cppe_mru_mtu_ctrl_tbl_source_filter_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -cppe_mru_mtu_ctrl_tbl_source_filter_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -cppe_mru_mtu_ctrl_tbl_source_filter_mode_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -cppe_mru_mtu_ctrl_tbl_source_filter_mode_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -cppe_mru_mtu_ctrl_tbl_get( - a_uint32_t dev_id, - a_uint32_t index, - union cppe_mru_mtu_ctrl_tbl_u *value); - -sw_error_t -cppe_mru_mtu_ctrl_tbl_set( - a_uint32_t dev_id, - a_uint32_t index, - union cppe_mru_mtu_ctrl_tbl_u *value); - -sw_error_t -cppe_port_phy_status_1_get( - a_uint32_t dev_id, - union cppe_port_phy_status_1_u *value); - -sw_error_t -cppe_port5_pcs1_phy_status_get( - a_uint32_t dev_id, - unsigned int *value); - -#endif diff --git a/feeds/ipq807x/qca-ssdk/src/include/hsl/cppe/cppe_portctrl_reg.h b/feeds/ipq807x/qca-ssdk/src/include/hsl/cppe/cppe_portctrl_reg.h deleted file mode 100755 index d12d8d0b8..000000000 --- a/feeds/ipq807x/qca-ssdk/src/include/hsl/cppe/cppe_portctrl_reg.h +++ /dev/null @@ -1,166 +0,0 @@ -/* - * Copyright (c) 2018, The Linux Foundation. All rights reserved. - * Permission to use, copy, modify, and/or distribute this software for - * any purpose with or without fee is hereby granted, provided that the - * above copyright notice and this permission notice appear in all copies. - * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES - * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR - * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES - * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN - * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT - * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. - */ - - -/** - * @defgroup - * @{ - */ -#ifndef _CPPE_PORTCTRL_REG_H_ -#define _CPPE_PORTCTRL_REG_H_ - -/*[table] CPPE_MRU_MTU_CTRL_TBL*/ -#define CPPE_MRU_MTU_CTRL_TBL -#define CPPE_MRU_MTU_CTRL_TBL_ADDRESS 0x3000 -#define CPPE_MRU_MTU_CTRL_TBL_NUM 256 -#define CPPE_MRU_MTU_CTRL_TBL_INC 0x10 -#define CPPE_MRU_MTU_CTRL_TBL_TYPE REG_TYPE_RW -#define CPPE_MRU_MTU_CTRL_TBL_DEFAULT 0x0 - /*[field] MRU*/ - #define CPPE_MRU_MTU_CTRL_TBL_MRU - #define CPPE_MRU_MTU_CTRL_TBL_MRU_OFFSET 0 - #define CPPE_MRU_MTU_CTRL_TBL_MRU_LEN 14 - #define CPPE_MRU_MTU_CTRL_TBL_MRU_DEFAULT 0x0 - /*[field] MRU_CMD*/ - #define CPPE_MRU_MTU_CTRL_TBL_MRU_CMD - #define CPPE_MRU_MTU_CTRL_TBL_MRU_CMD_OFFSET 14 - #define CPPE_MRU_MTU_CTRL_TBL_MRU_CMD_LEN 2 - #define CPPE_MRU_MTU_CTRL_TBL_MRU_CMD_DEFAULT 0x0 - /*[field] MTU*/ - #define CPPE_MRU_MTU_CTRL_TBL_MTU - #define CPPE_MRU_MTU_CTRL_TBL_MTU_OFFSET 16 - #define CPPE_MRU_MTU_CTRL_TBL_MTU_LEN 14 - #define CPPE_MRU_MTU_CTRL_TBL_MTU_DEFAULT 0x0 - /*[field] MTU_CMD*/ - #define CPPE_MRU_MTU_CTRL_TBL_MTU_CMD - #define CPPE_MRU_MTU_CTRL_TBL_MTU_CMD_OFFSET 30 - #define CPPE_MRU_MTU_CTRL_TBL_MTU_CMD_LEN 2 - #define CPPE_MRU_MTU_CTRL_TBL_MTU_CMD_DEFAULT 0x0 - /*[field] RX_CNT_EN*/ - #define CPPE_MRU_MTU_CTRL_TBL_RX_CNT_EN - #define CPPE_MRU_MTU_CTRL_TBL_RX_CNT_EN_OFFSET 32 - #define CPPE_MRU_MTU_CTRL_TBL_RX_CNT_EN_LEN 1 - #define CPPE_MRU_MTU_CTRL_TBL_RX_CNT_EN_DEFAULT 0x0 - /*[field] TX_CNT_EN*/ - #define CPPE_MRU_MTU_CTRL_TBL_TX_CNT_EN - #define CPPE_MRU_MTU_CTRL_TBL_TX_CNT_EN_OFFSET 33 - #define CPPE_MRU_MTU_CTRL_TBL_TX_CNT_EN_LEN 1 - #define CPPE_MRU_MTU_CTRL_TBL_TX_CNT_EN_DEFAULT 0x0 - /*[field] SRC_PROFILE*/ - #define CPPE_MRU_MTU_CTRL_TBL_SRC_PROFILE - #define CPPE_MRU_MTU_CTRL_TBL_SRC_PROFILE_OFFSET 34 - #define CPPE_MRU_MTU_CTRL_TBL_SRC_PROFILE_LEN 2 - #define CPPE_MRU_MTU_CTRL_TBL_SRC_PROFILE_DEFAULT 0x0 - /*[field] PCP_QOS_GROUP_ID*/ - #define CPPE_MRU_MTU_CTRL_TBL_PCP_QOS_GROUP_ID - #define CPPE_MRU_MTU_CTRL_TBL_PCP_QOS_GROUP_ID_OFFSET 36 - #define CPPE_MRU_MTU_CTRL_TBL_PCP_QOS_GROUP_ID_LEN 1 - #define CPPE_MRU_MTU_CTRL_TBL_PCP_QOS_GROUP_ID_DEFAULT 0x0 - /*[field] DSCP_QOS_GROUP_ID*/ - #define CPPE_MRU_MTU_CTRL_TBL_DSCP_QOS_GROUP_ID - #define CPPE_MRU_MTU_CTRL_TBL_DSCP_QOS_GROUP_ID_OFFSET 37 - #define CPPE_MRU_MTU_CTRL_TBL_DSCP_QOS_GROUP_ID_LEN 1 - #define CPPE_MRU_MTU_CTRL_TBL_DSCP_QOS_GROUP_ID_DEFAULT 0x0 - /*[field] PCP_RES_PREC_FORCE*/ - #define CPPE_MRU_MTU_CTRL_TBL_PCP_RES_PREC_FORCE - #define CPPE_MRU_MTU_CTRL_TBL_PCP_RES_PREC_FORCE_OFFSET 38 - #define CPPE_MRU_MTU_CTRL_TBL_PCP_RES_PREC_FORCE_LEN 1 - #define CPPE_MRU_MTU_CTRL_TBL_PCP_RES_PREC_FORCE_DEFAULT 0x0 - /*[field] DSCP_RES_PREC_FORCE*/ - #define CPPE_MRU_MTU_CTRL_TBL_DSCP_RES_PREC_FORCE - #define CPPE_MRU_MTU_CTRL_TBL_DSCP_RES_PREC_FORCE_OFFSET 39 - #define CPPE_MRU_MTU_CTRL_TBL_DSCP_RES_PREC_FORCE_LEN 1 - #define CPPE_MRU_MTU_CTRL_TBL_DSCP_RES_PREC_FORCE_DEFAULT 0x0 - /*[field] PREHEADER_RES_PREC*/ - #define CPPE_MRU_MTU_CTRL_TBL_PREHEADER_RES_PREC - #define CPPE_MRU_MTU_CTRL_TBL_PREHEADER_RES_PREC_OFFSET 40 - #define CPPE_MRU_MTU_CTRL_TBL_PREHEADER_RES_PREC_LEN 3 - #define CPPE_MRU_MTU_CTRL_TBL_PREHEADER_RES_PREC_DEFAULT 0x0 - /*[field] PCP_RES_PREC*/ - #define CPPE_MRU_MTU_CTRL_TBL_PCP_RES_PREC - #define CPPE_MRU_MTU_CTRL_TBL_PCP_RES_PREC_OFFSET 43 - #define CPPE_MRU_MTU_CTRL_TBL_PCP_RES_PREC_LEN 3 - #define CPPE_MRU_MTU_CTRL_TBL_PCP_RES_PREC_DEFAULT 0x0 - /*[field] DSCP_RES_PREC*/ - #define CPPE_MRU_MTU_CTRL_TBL_DSCP_RES_PREC - #define CPPE_MRU_MTU_CTRL_TBL_DSCP_RES_PREC_OFFSET 46 - #define CPPE_MRU_MTU_CTRL_TBL_DSCP_RES_PREC_LEN 3 - #define CPPE_MRU_MTU_CTRL_TBL_DSCP_RES_PREC_DEFAULT 0x0 - /*[field] FLOW_RES_PREC*/ - #define CPPE_MRU_MTU_CTRL_TBL_FLOW_RES_PREC - #define CPPE_MRU_MTU_CTRL_TBL_FLOW_RES_PREC_OFFSET 49 - #define CPPE_MRU_MTU_CTRL_TBL_FLOW_RES_PREC_LEN 3 - #define CPPE_MRU_MTU_CTRL_TBL_FLOW_RES_PREC_DEFAULT 0x0 - /*[field] PRE_ACL_RES_PREC*/ - #define CPPE_MRU_MTU_CTRL_TBL_PRE_ACL_RES_PREC - #define CPPE_MRU_MTU_CTRL_TBL_PRE_ACL_RES_PREC_OFFSET 52 - #define CPPE_MRU_MTU_CTRL_TBL_PRE_ACL_RES_PREC_LEN 3 - #define CPPE_MRU_MTU_CTRL_TBL_PRE_ACL_RES_PREC_DEFAULT 0x0 - /*[field] POST_ACL_RES_PREC*/ - #define CPPE_MRU_MTU_CTRL_TBL_POST_ACL_RES_PREC - #define CPPE_MRU_MTU_CTRL_TBL_POST_ACL_RES_PREC_OFFSET 55 - #define CPPE_MRU_MTU_CTRL_TBL_POST_ACL_RES_PREC_LEN 3 - #define CPPE_MRU_MTU_CTRL_TBL_POST_ACL_RES_PREC_DEFAULT 0x0 - /*[field] SOURCE_FILTERING_BYPASS*/ - #define CPPE_MRU_MTU_CTRL_TBL_SOURCE_FILTERING_BYPASS - #define CPPE_MRU_MTU_CTRL_TBL_SOURCE_FILTERING_BYPASS_OFFSET 58 - #define CPPE_MRU_MTU_CTRL_TBL_SOURCE_FILTERING_BYPASS_LEN 1 - #define CPPE_MRU_MTU_CTRL_TBL_SOURCE_FILTERING_BYPASS_DEFAULT 0x0 - /*[field] SOURCE_FILTERING_MODE*/ - #define CPPE_MRU_MTU_CTRL_TBL_SOURCE_FILTERING_MODE - #define CPPE_MRU_MTU_CTRL_TBL_SOURCE_FILTERING_MODE_OFFSET 59 - #define CPPE_MRU_MTU_CTRL_TBL_SOURCE_FILTERING_MODE_LEN 1 - #define CPPE_MRU_MTU_CTRL_TBL_SOURCE_FILTERING_MODE_DEFAULT 0x0 - -struct cppe_mru_mtu_ctrl_tbl { - a_uint32_t mru:14; - a_uint32_t mru_cmd:2; - a_uint32_t mtu:14; - a_uint32_t mtu_cmd:2; - a_uint32_t rx_cnt_en:1; - a_uint32_t tx_cnt_en:1; - a_uint32_t src_profile:2; - a_uint32_t pcp_qos_group_id:1; - a_uint32_t dscp_qos_group_id:1; - a_uint32_t pcp_res_prec_force:1; - a_uint32_t dscp_res_prec_force:1; - a_uint32_t preheader_res_prec:3; - a_uint32_t pcp_res_prec:3; - a_uint32_t dscp_res_prec:3; - a_uint32_t flow_res_prec:3; - a_uint32_t pre_acl_res_prec:3; - a_uint32_t post_acl_res_prec:3; - a_uint32_t source_filtering_bypass:1; - a_uint32_t source_filtering_mode:1; - a_uint32_t _reserved0:4; -}; - -union cppe_mru_mtu_ctrl_tbl_u { - a_uint32_t val[2]; - struct cppe_mru_mtu_ctrl_tbl bf; -}; - -struct cppe_port_phy_status_1 { - a_uint32_t port5_pcs0_phy_status:8; - a_uint32_t port4_pcs0_phy_status:8; - a_uint32_t port5_pcs1_phy_status:8; - a_uint32_t _reserved0:8; -}; - -union cppe_port_phy_status_1_u { - a_uint32_t val; - struct cppe_port_phy_status_1 bf; -}; - -#endif \ No newline at end of file diff --git a/feeds/ipq807x/qca-ssdk/src/include/hsl/cppe/cppe_qos.h b/feeds/ipq807x/qca-ssdk/src/include/hsl/cppe/cppe_qos.h deleted file mode 100755 index ae583960f..000000000 --- a/feeds/ipq807x/qca-ssdk/src/include/hsl/cppe/cppe_qos.h +++ /dev/null @@ -1,186 +0,0 @@ -/* - * Copyright (c) 2018, The Linux Foundation. All rights reserved. - * Permission to use, copy, modify, and/or distribute this software for - * any purpose with or without fee is hereby granted, provided that the - * above copyright notice and this permission notice appear in all copies. - * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES - * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR - * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES - * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN - * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT - * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. - */ - - -/** - * @defgroup - * @{ - */ -#ifndef _CPPE_QOS_H_ -#define _CPPE_QOS_H_ - -#define QOS_MAPPING_TBL_MAX_ENTRY 2592 -#define QOS_MAPPING_FLOW_TBL_MAX_ENTRY 2048 -#define QOS_MAPPING_DSCP_TBL_MAX_ENTRY 256 -#define QOS_MAPPING_PCP_TBL_MAX_ENTRY 16 -#define QOS_MAPPING_TBL_MAX_GROUP 2 - - -sw_error_t -cppe_qos_mapping_tbl_get( - a_uint32_t dev_id, - a_uint32_t index, - union qos_mapping_tbl_u *value); - -sw_error_t -cppe_qos_mapping_tbl_set( - a_uint32_t dev_id, - a_uint32_t index, - union qos_mapping_tbl_u *value); - -sw_error_t -cppe_qos_mapping_tbl_int_pcp_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -cppe_qos_mapping_tbl_int_pcp_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -cppe_qos_mapping_tbl_int_dei_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -cppe_qos_mapping_tbl_int_dei_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -cppe_qos_mapping_tbl_int_dei_en_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -cppe_qos_mapping_tbl_int_dei_en_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -cppe_qos_mapping_tbl_dscp_tc_mask_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -cppe_qos_mapping_tbl_dscp_tc_mask_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -cppe_qos_mapping_tbl_int_dscp_tc_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -cppe_qos_mapping_tbl_int_dscp_tc_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -cppe_qos_mapping_tbl_int_dp_en_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -cppe_qos_mapping_tbl_int_dp_en_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -cppe_qos_mapping_tbl_int_dp_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -cppe_qos_mapping_tbl_int_dp_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -cppe_qos_mapping_tbl_int_pri_en_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -cppe_qos_mapping_tbl_int_pri_en_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -cppe_qos_mapping_tbl_qos_res_prec_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -cppe_qos_mapping_tbl_qos_res_prec_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -cppe_qos_mapping_tbl_int_pcp_en_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -cppe_qos_mapping_tbl_int_pcp_en_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -cppe_qos_mapping_tbl_int_pri_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -cppe_qos_mapping_tbl_int_pri_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -cppe_qos_mapping_tbl_int_dscp_en_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -cppe_qos_mapping_tbl_int_dscp_en_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -#endif \ No newline at end of file diff --git a/feeds/ipq807x/qca-ssdk/src/include/hsl/cppe/cppe_qos_reg.h b/feeds/ipq807x/qca-ssdk/src/include/hsl/cppe/cppe_qos_reg.h deleted file mode 100755 index 92e473bc3..000000000 --- a/feeds/ipq807x/qca-ssdk/src/include/hsl/cppe/cppe_qos_reg.h +++ /dev/null @@ -1,113 +0,0 @@ -/* - * Copyright (c) 2018, The Linux Foundation. All rights reserved. - * Permission to use, copy, modify, and/or distribute this software for - * any purpose with or without fee is hereby granted, provided that the - * above copyright notice and this permission notice appear in all copies. - * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES - * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR - * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES - * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN - * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT - * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. - */ - - -/** - * @defgroup - * @{ - */ -#ifndef _CPPE_QOS_REG_H_ -#define _CPPE_QOS_REG_H_ - -/*[table] QOS_MAPPING_TBL*/ -#define QOS_MAPPING_TBL -#define QOS_MAPPING_TBL_ADDRESS 0x20000 -#define QOS_MAPPING_TBL_NUM 2592 -#define QOS_MAPPING_TBL_INC 0x10 -#define QOS_MAPPING_TBL_TYPE REG_TYPE_RW -#define QOS_MAPPING_TBL_DEFAULT 0x0 - /*[field] INT_DSCP_TC*/ - #define QOS_MAPPING_TBL_INT_DSCP_TC - #define QOS_MAPPING_TBL_INT_DSCP_TC_OFFSET 0 - #define QOS_MAPPING_TBL_INT_DSCP_TC_LEN 8 - #define QOS_MAPPING_TBL_INT_DSCP_TC_DEFAULT 0x0 - /*[field] DSCP_TC_MASK*/ - #define QOS_MAPPING_TBL_DSCP_TC_MASK - #define QOS_MAPPING_TBL_DSCP_TC_MASK_OFFSET 8 - #define QOS_MAPPING_TBL_DSCP_TC_MASK_LEN 8 - #define QOS_MAPPING_TBL_DSCP_TC_MASK_DEFAULT 0x0 - /*[field] INT_DSCP_EN*/ - #define QOS_MAPPING_TBL_INT_DSCP_EN - #define QOS_MAPPING_TBL_INT_DSCP_EN_OFFSET 16 - #define QOS_MAPPING_TBL_INT_DSCP_EN_LEN 1 - #define QOS_MAPPING_TBL_INT_DSCP_EN_DEFAULT 0x0 - /*[field] INT_PCP_EN*/ - #define QOS_MAPPING_TBL_INT_PCP_EN - #define QOS_MAPPING_TBL_INT_PCP_EN_OFFSET 17 - #define QOS_MAPPING_TBL_INT_PCP_EN_LEN 1 - #define QOS_MAPPING_TBL_INT_PCP_EN_DEFAULT 0x0 - /*[field] INT_PCP*/ - #define QOS_MAPPING_TBL_INT_PCP - #define QOS_MAPPING_TBL_INT_PCP_OFFSET 18 - #define QOS_MAPPING_TBL_INT_PCP_LEN 3 - #define QOS_MAPPING_TBL_INT_PCP_DEFAULT 0x0 - /*[field] INT_DEI_EN*/ - #define QOS_MAPPING_TBL_INT_DEI_EN - #define QOS_MAPPING_TBL_INT_DEI_EN_OFFSET 21 - #define QOS_MAPPING_TBL_INT_DEI_EN_LEN 1 - #define QOS_MAPPING_TBL_INT_DEI_EN_DEFAULT 0x0 - /*[field] INT_DEI*/ - #define QOS_MAPPING_TBL_INT_DEI - #define QOS_MAPPING_TBL_INT_DEI_OFFSET 22 - #define QOS_MAPPING_TBL_INT_DEI_LEN 1 - #define QOS_MAPPING_TBL_INT_DEI_DEFAULT 0x0 - /*[field] INT_PRI_EN*/ - #define QOS_MAPPING_TBL_INT_PRI_EN - #define QOS_MAPPING_TBL_INT_PRI_EN_OFFSET 23 - #define QOS_MAPPING_TBL_INT_PRI_EN_LEN 1 - #define QOS_MAPPING_TBL_INT_PRI_EN_DEFAULT 0x0 - /*[field] INT_PRI*/ - #define QOS_MAPPING_TBL_INT_PRI - #define QOS_MAPPING_TBL_INT_PRI_OFFSET 24 - #define QOS_MAPPING_TBL_INT_PRI_LEN 4 - #define QOS_MAPPING_TBL_INT_PRI_DEFAULT 0x0 - /*[field] INT_DP_EN*/ - #define QOS_MAPPING_TBL_INT_DP_EN - #define QOS_MAPPING_TBL_INT_DP_EN_OFFSET 28 - #define QOS_MAPPING_TBL_INT_DP_EN_LEN 1 - #define QOS_MAPPING_TBL_INT_DP_EN_DEFAULT 0x0 - /*[field] INT_DP*/ - #define QOS_MAPPING_TBL_INT_DP - #define QOS_MAPPING_TBL_INT_DP_OFFSET 29 - #define QOS_MAPPING_TBL_INT_DP_LEN 2 - #define QOS_MAPPING_TBL_INT_DP_DEFAULT 0x0 - /*[field] QOS_RES_PREC*/ - #define QOS_MAPPING_TBL_QOS_RES_PREC - #define QOS_MAPPING_TBL_QOS_RES_PREC_OFFSET 31 - #define QOS_MAPPING_TBL_QOS_RES_PREC_LEN 3 - #define QOS_MAPPING_TBL_QOS_RES_PREC_DEFAULT 0x0 - -struct qos_mapping_tbl { - a_uint32_t int_dscp_tc:8; - a_uint32_t dscp_tc_mask:8; - a_uint32_t int_dscp_en:1; - a_uint32_t int_pcp_en:1; - a_uint32_t int_pcp:3; - a_uint32_t int_dei_en:1; - a_uint32_t int_dei:1; - a_uint32_t int_pri_en:1; - a_uint32_t int_pri:4; - a_uint32_t int_dp_en:1; - a_uint32_t int_dp:2; - a_uint32_t qos_res_prec_0:1; - a_uint32_t qos_res_prec_1:2; - a_uint32_t _reserved0:30; -}; - -union qos_mapping_tbl_u { - a_uint32_t val[2]; - struct qos_mapping_tbl bf; -}; - -#endif \ No newline at end of file diff --git a/feeds/ipq807x/qca-ssdk/src/include/hsl/dess/dess_acl.h b/feeds/ipq807x/qca-ssdk/src/include/hsl/dess/dess_acl.h deleted file mode 100755 index 76e8fee9f..000000000 --- a/feeds/ipq807x/qca-ssdk/src/include/hsl/dess/dess_acl.h +++ /dev/null @@ -1,144 +0,0 @@ -/* - * Copyright (c) 2014, The Linux Foundation. All rights reserved. - * Permission to use, copy, modify, and/or distribute this software for - * any purpose with or without fee is hereby granted, provided that the - * above copyright notice and this permission notice appear in all copies. - * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES - * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR - * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES - * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN - * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT - * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. - */ - - -/** - * @defgroup dess_acl DESS_ACL - * @{ - */ -#ifndef _DESS_ACL_H_ -#define _DESS_ACL_H_ - -#ifdef __cplusplus -extern "C" { -#endif /* __cplusplus */ - -#include "fal/fal_acl.h" - - sw_error_t dess_acl_init(a_uint32_t dev_id); - - sw_error_t dess_acl_reset(a_uint32_t dev_id); - - sw_error_t dess_acl_cleanup(a_uint32_t dev_id); - - -#ifdef IN_ACL -#define DESS_ACL_INIT(rv, dev_id) \ - { \ - rv = dess_acl_init(dev_id); \ - SW_RTN_ON_ERROR(rv); \ - } - -#define DESS_ACL_RESET(rv, dev_id) \ - { \ - rv = dess_acl_reset(dev_id); \ - SW_RTN_ON_ERROR(rv); \ - } - -#define DESS_ACL_CLEANUP(rv, dev_id) \ - { \ - rv = dess_acl_cleanup(dev_id); \ - SW_RTN_ON_ERROR(rv); \ - } -#else -#define DESS_ACL_INIT(rv, dev_id) -#define DESS_ACL_RESET(rv, dev_id) -#define DESS_ACL_CLEANUP(rv, dev_id) -#endif - - sw_error_t - dess_acl_list_creat(a_uint32_t dev_id, a_uint32_t list_id, - a_uint32_t list_pri); - - sw_error_t - dess_acl_rule_add(a_uint32_t dev_id, a_uint32_t list_id, - a_uint32_t rule_id, a_uint32_t rule_nr, - fal_acl_rule_t * rule); - - sw_error_t - dess_acl_rule_delete(a_uint32_t dev_id, a_uint32_t list_id, - a_uint32_t rule_id, a_uint32_t rule_nr); - - a_uint32_t - dess_acl_rule_get_offset(a_uint32_t dev_id, a_uint32_t list_id, a_uint32_t rule_id); - - sw_error_t - dess_acl_list_bind(a_uint32_t dev_id, a_uint32_t list_id, - fal_acl_direc_t direc, fal_acl_bind_obj_t obj_t, - a_uint32_t obj_idx); - - sw_error_t - dess_acl_list_unbind(a_uint32_t dev_id, a_uint32_t list_id, - fal_acl_direc_t direc, fal_acl_bind_obj_t obj_t, - a_uint32_t obj_idx); - - sw_error_t - dess_acl_status_set(a_uint32_t dev_id, a_bool_t enable); - - sw_error_t - dess_acl_rule_query(a_uint32_t dev_id, a_uint32_t list_id, - a_uint32_t rule_id, fal_acl_rule_t * rule); - - sw_error_t - dess_acl_rule_sync_multi_portmap(a_uint32_t dev_id, a_uint32_t pos, a_uint32_t *act); - -#ifdef HSL_STANDALONG - - - HSL_LOCAL sw_error_t - dess_acl_list_destroy(a_uint32_t dev_id, a_uint32_t list_id); - - HSL_LOCAL sw_error_t - dess_acl_status_get(a_uint32_t dev_id, a_bool_t * enable); - - HSL_LOCAL sw_error_t - dess_acl_list_dump(a_uint32_t dev_id); - - HSL_LOCAL sw_error_t - dess_acl_rule_dump(a_uint32_t dev_id); - - HSL_LOCAL sw_error_t - dess_acl_port_udf_profile_set(a_uint32_t dev_id, fal_port_t port_id, - fal_acl_udf_type_t udf_type, - a_uint32_t offset, a_uint32_t length); - - HSL_LOCAL sw_error_t - dess_acl_port_udf_profile_get(a_uint32_t dev_id, fal_port_t port_id, - fal_acl_udf_type_t udf_type, - a_uint32_t * offset, a_uint32_t * length); - - HSL_LOCAL sw_error_t - dess_acl_rule_active(a_uint32_t dev_id, a_uint32_t list_id, - a_uint32_t rule_id, a_uint32_t rule_nr); - - HSL_LOCAL sw_error_t - dess_acl_rule_deactive(a_uint32_t dev_id, a_uint32_t list_id, - a_uint32_t rule_id, a_uint32_t rule_nr); - HSL_LOCAL sw_error_t - dess_acl_rule_src_filter_sts_set(a_uint32_t dev_id, - a_uint32_t rule_id, a_bool_t enable); - - HSL_LOCAL sw_error_t - dess_acl_rule_src_filter_sts_get(a_uint32_t dev_id, - a_uint32_t rule_id, a_bool_t* enable); - -#endif - -#ifdef __cplusplus -} -#endif /* __cplusplus */ -#endif /* _DESS_ACL_H_ */ -/** - * @} - */ diff --git a/feeds/ipq807x/qca-ssdk/src/include/hsl/dess/dess_api.h b/feeds/ipq807x/qca-ssdk/src/include/hsl/dess/dess_api.h deleted file mode 100755 index 7b92fbd34..000000000 --- a/feeds/ipq807x/qca-ssdk/src/include/hsl/dess/dess_api.h +++ /dev/null @@ -1,1174 +0,0 @@ -/* - * Copyright (c) 2014, The Linux Foundation. All rights reserved. - * Permission to use, copy, modify, and/or distribute this software for - * any purpose with or without fee is hereby granted, provided that the - * above copyright notice and this permission notice appear in all copies. - * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES - * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR - * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES - * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN - * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT - * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. - */ - - - -#ifndef _DESS_API_H_ -#define _DESS_API_H_ - -#ifdef __cplusplus -extern "C" { -#endif /* __cplusplus */ - -#ifdef IN_PORTCONTROL -#define PORTCONTROL_API \ - SW_API_DEF(SW_API_PT_DUPLEX_GET, dess_port_duplex_get), \ - SW_API_DEF(SW_API_PT_DUPLEX_SET, dess_port_duplex_set), \ - SW_API_DEF(SW_API_PT_SPEED_GET, dess_port_speed_get), \ - SW_API_DEF(SW_API_PT_SPEED_SET, dess_port_speed_set), \ - SW_API_DEF(SW_API_PT_AN_GET, dess_port_autoneg_status_get), \ - SW_API_DEF(SW_API_PT_AN_ENABLE, dess_port_autoneg_enable), \ - SW_API_DEF(SW_API_PT_AN_RESTART, dess_port_autoneg_restart), \ - SW_API_DEF(SW_API_PT_AN_ADV_GET, dess_port_autoneg_adv_get), \ - SW_API_DEF(SW_API_PT_AN_ADV_SET, dess_port_autoneg_adv_set), \ - SW_API_DEF(SW_API_PT_FLOWCTRL_SET, dess_port_flowctrl_set), \ - SW_API_DEF(SW_API_PT_FLOWCTRL_GET, dess_port_flowctrl_get), \ - SW_API_DEF(SW_API_PT_FLOWCTRL_MODE_SET, dess_port_flowctrl_forcemode_set), \ - SW_API_DEF(SW_API_PT_FLOWCTRL_MODE_GET, dess_port_flowctrl_forcemode_get), \ - SW_API_DEF(SW_API_PT_POWERSAVE_SET, dess_port_powersave_set), \ - SW_API_DEF(SW_API_PT_POWERSAVE_GET, dess_port_powersave_get), \ - SW_API_DEF(SW_API_PT_HIBERNATE_SET, dess_port_hibernate_set), \ - SW_API_DEF(SW_API_PT_HIBERNATE_GET, dess_port_hibernate_get), \ - SW_API_DEF(SW_API_PT_CDT, dess_port_cdt), \ - SW_API_DEF(SW_API_PT_TXHDR_SET, dess_port_txhdr_mode_set), \ - SW_API_DEF(SW_API_PT_TXHDR_GET, dess_port_txhdr_mode_get), \ - SW_API_DEF(SW_API_PT_RXHDR_SET, dess_port_rxhdr_mode_set), \ - SW_API_DEF(SW_API_PT_RXHDR_GET, dess_port_rxhdr_mode_get), \ - SW_API_DEF(SW_API_HEADER_TYPE_SET, dess_header_type_set), \ - SW_API_DEF(SW_API_HEADER_TYPE_GET, dess_header_type_get), \ - SW_API_DEF(SW_API_TXMAC_STATUS_SET, dess_port_txmac_status_set), \ - SW_API_DEF(SW_API_TXMAC_STATUS_GET, dess_port_txmac_status_get), \ - SW_API_DEF(SW_API_RXMAC_STATUS_SET, dess_port_rxmac_status_set), \ - SW_API_DEF(SW_API_RXMAC_STATUS_GET, dess_port_rxmac_status_get), \ - SW_API_DEF(SW_API_TXFC_STATUS_SET, dess_port_txfc_status_set), \ - SW_API_DEF(SW_API_TXFC_STATUS_GET, dess_port_txfc_status_get), \ - SW_API_DEF(SW_API_RXFC_STATUS_SET, dess_port_rxfc_status_set), \ - SW_API_DEF(SW_API_RXFC_STATUS_GET, dess_port_rxfc_status_get), \ - SW_API_DEF(SW_API_BP_STATUS_SET, dess_port_bp_status_set), \ - SW_API_DEF(SW_API_BP_STATUS_GET, dess_port_bp_status_get), \ - SW_API_DEF(SW_API_PT_LINK_MODE_SET, dess_port_link_forcemode_set), \ - SW_API_DEF(SW_API_PT_LINK_MODE_GET, dess_port_link_forcemode_get), \ - SW_API_DEF(SW_API_PT_LINK_STATUS_GET, dess_port_link_status_get), \ - SW_API_DEF(SW_API_PT_MAC_LOOPBACK_SET, dess_port_mac_loopback_set), \ - SW_API_DEF(SW_API_PT_MAC_LOOPBACK_GET, dess_port_mac_loopback_get), \ - SW_API_DEF(SW_API_PT_CONGESTION_DROP_SET, dess_port_congestion_drop_set), \ - SW_API_DEF(SW_API_PT_CONGESTION_DROP_GET, dess_port_congestion_drop_get), \ - SW_API_DEF(SW_API_PT_RING_FLOW_CTRL_THRES_SET, dess_ring_flow_ctrl_thres_set), \ - SW_API_DEF(SW_API_PT_RING_FLOW_CTRL_THRES_GET, dess_ring_flow_ctrl_thres_get),\ - SW_API_DEF(SW_API_PT_8023AZ_SET, dess_port_8023az_set), \ - SW_API_DEF(SW_API_PT_8023AZ_GET, dess_port_8023az_get), \ - SW_API_DEF(SW_API_PT_MDIX_SET, dess_port_mdix_set), \ - SW_API_DEF(SW_API_PT_MDIX_GET, dess_port_mdix_get), \ - SW_API_DEF(SW_API_PT_MDIX_STATUS_GET, dess_port_mdix_status_get), \ - SW_API_DEF(SW_API_PT_COMBO_PREFER_MEDIUM_SET, dess_port_combo_prefer_medium_set), \ - SW_API_DEF(SW_API_PT_COMBO_PREFER_MEDIUM_GET, dess_port_combo_prefer_medium_get), \ - SW_API_DEF(SW_API_PT_COMBO_MEDIUM_STATUS_GET, dess_port_combo_medium_status_get), \ - SW_API_DEF(SW_API_PT_COMBO_FIBER_MODE_SET, dess_port_combo_fiber_mode_set), \ - SW_API_DEF(SW_API_PT_COMBO_FIBER_MODE_GET, dess_port_combo_fiber_mode_get), \ - SW_API_DEF(SW_API_PT_LOCAL_LOOPBACK_SET, dess_port_local_loopback_set), \ - SW_API_DEF(SW_API_PT_LOCAL_LOOPBACK_GET, dess_port_local_loopback_get), \ - SW_API_DEF(SW_API_PT_REMOTE_LOOPBACK_SET, dess_port_remote_loopback_set), \ - SW_API_DEF(SW_API_PT_REMOTE_LOOPBACK_GET, dess_port_remote_loopback_get), \ - SW_API_DEF(SW_API_PT_RESET, dess_port_reset), \ - SW_API_DEF(SW_API_PT_POWER_OFF, dess_port_power_off), \ - SW_API_DEF(SW_API_PT_POWER_ON, dess_port_power_on), - -#define PORTCONTROL_API_PARAM \ - SW_API_DESC(SW_API_PT_DUPLEX_GET) \ - SW_API_DESC(SW_API_PT_DUPLEX_SET) \ - SW_API_DESC(SW_API_PT_SPEED_GET) \ - SW_API_DESC(SW_API_PT_SPEED_SET) \ - SW_API_DESC(SW_API_PT_AN_GET) \ - SW_API_DESC(SW_API_PT_AN_ENABLE) \ - SW_API_DESC(SW_API_PT_AN_RESTART) \ - SW_API_DESC(SW_API_PT_AN_ADV_GET) \ - SW_API_DESC(SW_API_PT_AN_ADV_SET) \ - SW_API_DESC(SW_API_PT_FLOWCTRL_SET) \ - SW_API_DESC(SW_API_PT_FLOWCTRL_GET) \ - SW_API_DESC(SW_API_PT_FLOWCTRL_MODE_SET) \ - SW_API_DESC(SW_API_PT_FLOWCTRL_MODE_GET) \ - SW_API_DESC(SW_API_PT_POWERSAVE_SET) \ - SW_API_DESC(SW_API_PT_POWERSAVE_GET) \ - SW_API_DESC(SW_API_PT_HIBERNATE_SET) \ - SW_API_DESC(SW_API_PT_HIBERNATE_GET) \ - SW_API_DESC(SW_API_PT_CDT) \ - SW_API_DESC(SW_API_PT_TXHDR_SET) \ - SW_API_DESC(SW_API_PT_TXHDR_GET) \ - SW_API_DESC(SW_API_PT_RXHDR_SET) \ - SW_API_DESC(SW_API_PT_RXHDR_GET) \ - SW_API_DESC(SW_API_HEADER_TYPE_SET) \ - SW_API_DESC(SW_API_HEADER_TYPE_GET) \ - SW_API_DESC(SW_API_TXMAC_STATUS_SET) \ - SW_API_DESC(SW_API_TXMAC_STATUS_GET) \ - SW_API_DESC(SW_API_RXMAC_STATUS_SET) \ - SW_API_DESC(SW_API_RXMAC_STATUS_GET) \ - SW_API_DESC(SW_API_TXFC_STATUS_SET) \ - SW_API_DESC(SW_API_TXFC_STATUS_GET) \ - SW_API_DESC(SW_API_RXFC_STATUS_SET) \ - SW_API_DESC(SW_API_RXFC_STATUS_GET) \ - SW_API_DESC(SW_API_BP_STATUS_SET) \ - SW_API_DESC(SW_API_BP_STATUS_GET) \ - SW_API_DESC(SW_API_PT_LINK_MODE_SET) \ - SW_API_DESC(SW_API_PT_LINK_MODE_GET) \ - SW_API_DESC(SW_API_PT_LINK_STATUS_GET) \ - SW_API_DESC(SW_API_PT_MAC_LOOPBACK_SET) \ - SW_API_DESC(SW_API_PT_MAC_LOOPBACK_GET) \ - SW_API_DESC(SW_API_PT_CONGESTION_DROP_SET) \ - SW_API_DESC(SW_API_PT_CONGESTION_DROP_GET) \ - SW_API_DESC(SW_API_PT_RING_FLOW_CTRL_THRES_SET) \ - SW_API_DESC(SW_API_PT_RING_FLOW_CTRL_THRES_GET)\ - SW_API_DESC(SW_API_PT_8023AZ_SET) \ - SW_API_DESC(SW_API_PT_8023AZ_GET) \ - SW_API_DESC(SW_API_PT_MDIX_SET) \ - SW_API_DESC(SW_API_PT_MDIX_GET) \ - SW_API_DESC(SW_API_PT_MDIX_STATUS_GET) \ - SW_API_DESC(SW_API_PT_COMBO_PREFER_MEDIUM_SET) \ - SW_API_DESC(SW_API_PT_COMBO_PREFER_MEDIUM_GET) \ - SW_API_DESC(SW_API_PT_COMBO_MEDIUM_STATUS_GET) \ - SW_API_DESC(SW_API_PT_COMBO_FIBER_MODE_SET) \ - SW_API_DESC(SW_API_PT_COMBO_FIBER_MODE_GET) \ - SW_API_DESC(SW_API_PT_LOCAL_LOOPBACK_SET) \ - SW_API_DESC(SW_API_PT_LOCAL_LOOPBACK_GET) \ - SW_API_DESC(SW_API_PT_REMOTE_LOOPBACK_SET) \ - SW_API_DESC(SW_API_PT_REMOTE_LOOPBACK_GET) \ - SW_API_DESC(SW_API_PT_RESET) \ - SW_API_DESC(SW_API_PT_POWER_OFF) \ - SW_API_DESC(SW_API_PT_POWER_ON) - -#else -#define PORTCONTROL_API -#define PORTCONTROL_API_PARAM -#endif - -#ifdef IN_VLAN -#define VLAN_API \ - SW_API_DEF(SW_API_VLAN_ADD, dess_vlan_create), \ - SW_API_DEF(SW_API_VLAN_DEL, dess_vlan_delete), \ - SW_API_DEF(SW_API_VLAN_FIND, dess_vlan_find), \ - SW_API_DEF(SW_API_VLAN_NEXT, dess_vlan_next), \ - SW_API_DEF(SW_API_VLAN_APPEND, dess_vlan_entry_append), \ - SW_API_DEF(SW_API_VLAN_FLUSH, dess_vlan_flush), \ - SW_API_DEF(SW_API_VLAN_FID_SET, dess_vlan_fid_set), \ - SW_API_DEF(SW_API_VLAN_FID_GET, dess_vlan_fid_get), \ - SW_API_DEF(SW_API_VLAN_MEMBER_ADD, dess_vlan_member_add), \ - SW_API_DEF(SW_API_VLAN_MEMBER_DEL, dess_vlan_member_del), \ - SW_API_DEF(SW_API_VLAN_LEARN_STATE_SET, dess_vlan_learning_state_set), \ - SW_API_DEF(SW_API_VLAN_LEARN_STATE_GET, dess_vlan_learning_state_get), - -#define VLAN_API_PARAM \ - SW_API_DESC(SW_API_VLAN_ADD) \ - SW_API_DESC(SW_API_VLAN_DEL) \ - SW_API_DESC(SW_API_VLAN_FIND) \ - SW_API_DESC(SW_API_VLAN_NEXT) \ - SW_API_DESC(SW_API_VLAN_APPEND) \ - SW_API_DESC(SW_API_VLAN_FLUSH) \ - SW_API_DESC(SW_API_VLAN_FID_SET) \ - SW_API_DESC(SW_API_VLAN_FID_GET) \ - SW_API_DESC(SW_API_VLAN_MEMBER_ADD) \ - SW_API_DESC(SW_API_VLAN_MEMBER_DEL) \ - SW_API_DESC(SW_API_VLAN_LEARN_STATE_SET) \ - SW_API_DESC(SW_API_VLAN_LEARN_STATE_GET) -#else -#define VLAN_API -#define VLAN_API_PARAM -#endif - -#ifdef IN_PORTVLAN -#define PORTVLAN_API \ - SW_API_DEF(SW_API_PT_ING_MODE_GET, dess_port_1qmode_get), \ - SW_API_DEF(SW_API_PT_ING_MODE_SET, dess_port_1qmode_set), \ - SW_API_DEF(SW_API_PT_EG_MODE_GET, dess_port_egvlanmode_get), \ - SW_API_DEF(SW_API_PT_EG_MODE_SET, dess_port_egvlanmode_set), \ - SW_API_DEF(SW_API_PT_VLAN_MEM_ADD, dess_portvlan_member_add), \ - SW_API_DEF(SW_API_PT_VLAN_MEM_DEL, dess_portvlan_member_del), \ - SW_API_DEF(SW_API_PT_VLAN_MEM_UPDATE, dess_portvlan_member_update), \ - SW_API_DEF(SW_API_PT_VLAN_MEM_GET, dess_portvlan_member_get), \ - SW_API_DEF(SW_API_PT_FORCE_DEF_VID_SET, dess_port_force_default_vid_set), \ - SW_API_DEF(SW_API_PT_FORCE_DEF_VID_GET, dess_port_force_default_vid_get), \ - SW_API_DEF(SW_API_PT_FORCE_PORTVLAN_SET, dess_port_force_portvlan_set), \ - SW_API_DEF(SW_API_PT_FORCE_PORTVLAN_GET, dess_port_force_portvlan_get), \ - SW_API_DEF(SW_API_NESTVLAN_TPID_SET, dess_nestvlan_tpid_set), \ - SW_API_DEF(SW_API_NESTVLAN_TPID_GET, dess_nestvlan_tpid_get), \ - SW_API_DEF(SW_API_PT_IN_VLAN_MODE_SET, dess_port_invlan_mode_set), \ - SW_API_DEF(SW_API_PT_IN_VLAN_MODE_GET, dess_port_invlan_mode_get), \ - SW_API_DEF(SW_API_PT_TLS_SET, dess_port_tls_set), \ - SW_API_DEF(SW_API_PT_TLS_GET, dess_port_tls_get), \ - SW_API_DEF(SW_API_PT_PRI_PROPAGATION_SET, dess_port_pri_propagation_set), \ - SW_API_DEF(SW_API_PT_PRI_PROPAGATION_GET, dess_port_pri_propagation_get), \ - SW_API_DEF(SW_API_PT_DEF_SVID_SET, dess_port_default_svid_set), \ - SW_API_DEF(SW_API_PT_DEF_SVID_GET, dess_port_default_svid_get), \ - SW_API_DEF(SW_API_PT_DEF_CVID_SET, dess_port_default_cvid_set), \ - SW_API_DEF(SW_API_PT_DEF_CVID_GET, dess_port_default_cvid_get), \ - SW_API_DEF(SW_API_PT_VLAN_PROPAGATION_SET, dess_port_vlan_propagation_set), \ - SW_API_DEF(SW_API_PT_VLAN_PROPAGATION_GET, dess_port_vlan_propagation_get), \ - SW_API_DEF(SW_API_PT_VLAN_TRANS_ADD, dess_port_vlan_trans_add), \ - SW_API_DEF(SW_API_PT_VLAN_TRANS_DEL, dess_port_vlan_trans_del), \ - SW_API_DEF(SW_API_PT_VLAN_TRANS_GET, dess_port_vlan_trans_get), \ - SW_API_DEF(SW_API_QINQ_MODE_SET, dess_qinq_mode_set), \ - SW_API_DEF(SW_API_QINQ_MODE_GET, dess_qinq_mode_get), \ - SW_API_DEF(SW_API_PT_QINQ_ROLE_SET, dess_port_qinq_role_set), \ - SW_API_DEF(SW_API_PT_QINQ_ROLE_GET, dess_port_qinq_role_get), \ - SW_API_DEF(SW_API_PT_VLAN_TRANS_ITERATE, dess_port_vlan_trans_iterate), \ - SW_API_DEF(SW_API_PT_MAC_VLAN_XLT_SET, dess_port_mac_vlan_xlt_set), \ - SW_API_DEF(SW_API_PT_MAC_VLAN_XLT_GET, dess_port_mac_vlan_xlt_get), \ - SW_API_DEF(SW_API_NETISOLATE_SET, dess_netisolate_set), \ - SW_API_DEF(SW_API_NETISOLATE_GET, dess_netisolate_get),\ - SW_API_DEF(SW_API_EG_FLTR_BYPASS_EN_SET, dess_eg_trans_filter_bypass_en_set), \ - SW_API_DEF(SW_API_EG_FLTR_BYPASS_EN_GET, dess_eg_trans_filter_bypass_en_get), - - -#define PORTVLAN_API_PARAM \ - SW_API_DESC(SW_API_PT_ING_MODE_GET) \ - SW_API_DESC(SW_API_PT_ING_MODE_SET) \ - SW_API_DESC(SW_API_PT_EG_MODE_GET) \ - SW_API_DESC(SW_API_PT_EG_MODE_SET) \ - SW_API_DESC(SW_API_PT_VLAN_MEM_ADD) \ - SW_API_DESC(SW_API_PT_VLAN_MEM_DEL) \ - SW_API_DESC(SW_API_PT_VLAN_MEM_UPDATE) \ - SW_API_DESC(SW_API_PT_VLAN_MEM_GET) \ - SW_API_DESC(SW_API_PT_FORCE_DEF_VID_SET) \ - SW_API_DESC(SW_API_PT_FORCE_DEF_VID_GET) \ - SW_API_DESC(SW_API_PT_FORCE_PORTVLAN_SET) \ - SW_API_DESC(SW_API_PT_FORCE_PORTVLAN_GET) \ - SW_API_DESC(SW_API_NESTVLAN_TPID_SET) \ - SW_API_DESC(SW_API_NESTVLAN_TPID_GET) \ - SW_API_DESC(SW_API_PT_IN_VLAN_MODE_SET) \ - SW_API_DESC(SW_API_PT_IN_VLAN_MODE_GET) \ - SW_API_DESC(SW_API_PT_TLS_SET) \ - SW_API_DESC(SW_API_PT_TLS_GET) \ - SW_API_DESC(SW_API_PT_PRI_PROPAGATION_SET) \ - SW_API_DESC(SW_API_PT_PRI_PROPAGATION_GET) \ - SW_API_DESC(SW_API_PT_DEF_SVID_SET) \ - SW_API_DESC(SW_API_PT_DEF_SVID_GET) \ - SW_API_DESC(SW_API_PT_DEF_CVID_SET) \ - SW_API_DESC(SW_API_PT_DEF_CVID_GET) \ - SW_API_DESC(SW_API_PT_VLAN_PROPAGATION_SET) \ - SW_API_DESC(SW_API_PT_VLAN_PROPAGATION_GET) \ - SW_API_DESC(SW_API_PT_VLAN_TRANS_ADD) \ - SW_API_DESC(SW_API_PT_VLAN_TRANS_DEL) \ - SW_API_DESC(SW_API_PT_VLAN_TRANS_GET) \ - SW_API_DESC(SW_API_QINQ_MODE_SET) \ - SW_API_DESC(SW_API_QINQ_MODE_GET) \ - SW_API_DESC(SW_API_PT_QINQ_ROLE_SET) \ - SW_API_DESC(SW_API_PT_QINQ_ROLE_GET) \ - SW_API_DESC(SW_API_PT_VLAN_TRANS_ITERATE) \ - SW_API_DESC(SW_API_PT_MAC_VLAN_XLT_SET) \ - SW_API_DESC(SW_API_PT_MAC_VLAN_XLT_GET) \ - SW_API_DESC(SW_API_NETISOLATE_SET) \ - SW_API_DESC(SW_API_NETISOLATE_GET) \ - SW_API_DESC(SW_API_EG_FLTR_BYPASS_EN_SET) \ - SW_API_DESC(SW_API_EG_FLTR_BYPASS_EN_GET) - -#else -#define PORTVLAN_API -#define PORTVLAN_API_PARAM -#endif - -#ifdef IN_FDB -#define FDB_API \ - SW_API_DEF(SW_API_FDB_ADD, dess_fdb_add), \ - SW_API_DEF(SW_API_FDB_DELALL, dess_fdb_del_all), \ - SW_API_DEF(SW_API_FDB_DELPORT,dess_fdb_del_by_port), \ - SW_API_DEF(SW_API_FDB_DELMAC, dess_fdb_del_by_mac), \ - SW_API_DEF(SW_API_FDB_FIND, dess_fdb_find), \ - SW_API_DEF(SW_API_FDB_EXTEND_NEXT, dess_fdb_extend_next), \ - SW_API_DEF(SW_API_FDB_EXTEND_FIRST, dess_fdb_extend_first), \ - SW_API_DEF(SW_API_FDB_TRANSFER, dess_fdb_transfer), \ - SW_API_DEF(SW_API_FDB_PT_LEARN_SET, dess_fdb_port_learn_set), \ - SW_API_DEF(SW_API_FDB_PT_LEARN_GET, dess_fdb_port_learn_get), \ - SW_API_DEF(SW_API_FDB_AGE_CTRL_SET, dess_fdb_age_ctrl_set), \ - SW_API_DEF(SW_API_FDB_AGE_CTRL_GET, dess_fdb_age_ctrl_get), \ - SW_API_DEF(SW_API_FDB_VLAN_IVL_SVL_SET, dess_fdb_vlan_ivl_svl_set),\ - SW_API_DEF(SW_API_FDB_VLAN_IVL_SVL_GET, dess_fdb_vlan_ivl_svl_get),\ - SW_API_DEF(SW_API_FDB_AGE_TIME_SET, dess_fdb_age_time_set), \ - SW_API_DEF(SW_API_FDB_AGE_TIME_GET, dess_fdb_age_time_get), \ - SW_API_DEF(SW_API_PT_FDB_LEARN_LIMIT_SET, dess_port_fdb_learn_limit_set), \ - SW_API_DEF(SW_API_PT_FDB_LEARN_LIMIT_GET, dess_port_fdb_learn_limit_get), \ - SW_API_DEF(SW_API_PT_FDB_LEARN_EXCEED_CMD_SET, dess_port_fdb_learn_exceed_cmd_set), \ - SW_API_DEF(SW_API_PT_FDB_LEARN_EXCEED_CMD_GET, dess_port_fdb_learn_exceed_cmd_get), \ - SW_API_DEF(SW_API_FDB_LEARN_LIMIT_SET, dess_fdb_learn_limit_set), \ - SW_API_DEF(SW_API_FDB_LEARN_LIMIT_GET, dess_fdb_learn_limit_get), \ - SW_API_DEF(SW_API_FDB_LEARN_EXCEED_CMD_SET, dess_fdb_learn_exceed_cmd_set), \ - SW_API_DEF(SW_API_FDB_LEARN_EXCEED_CMD_GET, dess_fdb_learn_exceed_cmd_get), \ - SW_API_DEF(SW_API_FDB_RESV_ADD, dess_fdb_resv_add), \ - SW_API_DEF(SW_API_FDB_RESV_DEL, dess_fdb_resv_del), \ - SW_API_DEF(SW_API_FDB_RESV_FIND, dess_fdb_resv_find), \ - SW_API_DEF(SW_API_FDB_RESV_ITERATE, dess_fdb_resv_iterate), \ - SW_API_DEF(SW_API_FDB_PT_LEARN_STATIC_SET, dess_fdb_port_learn_static_set), \ - SW_API_DEF(SW_API_FDB_PT_LEARN_STATIC_GET, dess_fdb_port_learn_static_get), \ - SW_API_DEF(SW_API_FDB_PORT_ADD, dess_fdb_port_add), \ - SW_API_DEF(SW_API_FDB_PORT_DEL, dess_fdb_port_del), - -#define FDB_API_PARAM \ - SW_API_DESC(SW_API_FDB_ADD) \ - SW_API_DESC(SW_API_FDB_DELALL) \ - SW_API_DESC(SW_API_FDB_DELPORT) \ - SW_API_DESC(SW_API_FDB_DELMAC) \ - SW_API_DESC(SW_API_FDB_FIND) \ - SW_API_DESC(SW_API_FDB_EXTEND_NEXT) \ - SW_API_DESC(SW_API_FDB_EXTEND_FIRST) \ - SW_API_DESC(SW_API_FDB_TRANSFER) \ - SW_API_DESC(SW_API_FDB_PT_LEARN_SET) \ - SW_API_DESC(SW_API_FDB_PT_LEARN_GET) \ - SW_API_DESC(SW_API_FDB_AGE_CTRL_SET) \ - SW_API_DESC(SW_API_FDB_AGE_CTRL_GET) \ - SW_API_DESC(SW_API_FDB_VLAN_IVL_SVL_SET) \ - SW_API_DESC(SW_API_FDB_VLAN_IVL_SVL_GET) \ - SW_API_DESC(SW_API_FDB_AGE_TIME_SET) \ - SW_API_DESC(SW_API_FDB_AGE_TIME_GET) \ - SW_API_DESC(SW_API_PT_FDB_LEARN_LIMIT_SET) \ - SW_API_DESC(SW_API_PT_FDB_LEARN_LIMIT_GET) \ - SW_API_DESC(SW_API_PT_FDB_LEARN_EXCEED_CMD_SET) \ - SW_API_DESC(SW_API_PT_FDB_LEARN_EXCEED_CMD_GET) \ - SW_API_DESC(SW_API_FDB_LEARN_LIMIT_SET) \ - SW_API_DESC(SW_API_FDB_LEARN_LIMIT_GET) \ - SW_API_DESC(SW_API_FDB_LEARN_EXCEED_CMD_SET) \ - SW_API_DESC(SW_API_FDB_LEARN_EXCEED_CMD_GET) \ - SW_API_DESC(SW_API_FDB_RESV_ADD) \ - SW_API_DESC(SW_API_FDB_RESV_DEL) \ - SW_API_DESC(SW_API_FDB_RESV_FIND) \ - SW_API_DESC(SW_API_FDB_RESV_ITERATE) \ - SW_API_DESC(SW_API_FDB_PT_LEARN_STATIC_SET) \ - SW_API_DESC(SW_API_FDB_PT_LEARN_STATIC_GET) \ - SW_API_DESC(SW_API_FDB_PORT_ADD) \ - SW_API_DESC(SW_API_FDB_PORT_DEL) - -#else -#define FDB_API -#define FDB_API_PARAM -#endif - - -#ifdef IN_ACL -#define ACL_API \ - SW_API_DEF(SW_API_ACL_LIST_CREAT, dess_acl_list_creat), \ - SW_API_DEF(SW_API_ACL_LIST_DESTROY, dess_acl_list_destroy), \ - SW_API_DEF(SW_API_ACL_RULE_ADD, dess_acl_rule_add), \ - SW_API_DEF(SW_API_ACL_RULE_DELETE, dess_acl_rule_delete), \ - SW_API_DEF(SW_API_ACL_RULE_QUERY, dess_acl_rule_query), \ - SW_API_DEF(SW_API_ACL_LIST_BIND, dess_acl_list_bind), \ - SW_API_DEF(SW_API_ACL_LIST_UNBIND, dess_acl_list_unbind), \ - SW_API_DEF(SW_API_ACL_STATUS_SET, dess_acl_status_set), \ - SW_API_DEF(SW_API_ACL_STATUS_GET, dess_acl_status_get), \ - SW_API_DEF(SW_API_ACL_LIST_DUMP, dess_acl_list_dump), \ - SW_API_DEF(SW_API_ACL_RULE_DUMP, dess_acl_rule_dump), \ - SW_API_DEF(SW_API_ACL_PT_UDF_PROFILE_SET, dessort_udf_profile_set), \ - SW_API_DEF(SW_API_ACL_PT_UDF_PROFILE_GET, dess_acl_port_udf_profile_get), \ - SW_API_DEF(SW_API_ACL_RULE_ACTIVE, dess_acl_rule_active), \ - SW_API_DEF(SW_API_ACL_RULE_DEACTIVE, dess_acl_rule_deactive),\ - SW_API_DEF(SW_API_ACL_RULE_SRC_FILTER_STS_SET, dess_acl_rule_src_filter_sts_set),\ - SW_API_DEF(SW_API_ACL_RULE_SRC_FILTER_STS_GET, dess_acl_rule_src_filter_sts_get), \ - SW_API_DEF(SW_API_ACL_RULE_GET_OFFSET, dess_acl_rule_get_offset), - -#define ACL_API_PARAM \ - SW_API_DESC(SW_API_ACL_LIST_CREAT) \ - SW_API_DESC(SW_API_ACL_LIST_DESTROY) \ - SW_API_DESC(SW_API_ACL_RULE_ADD) \ - SW_API_DESC(SW_API_ACL_RULE_DELETE) \ - SW_API_DESC(SW_API_ACL_RULE_QUERY) \ - SW_API_DESC(SW_API_ACL_LIST_BIND) \ - SW_API_DESC(SW_API_ACL_LIST_UNBIND) \ - SW_API_DESC(SW_API_ACL_STATUS_SET) \ - SW_API_DESC(SW_API_ACL_STATUS_GET) \ - SW_API_DESC(SW_API_ACL_LIST_DUMP) \ - SW_API_DESC(SW_API_ACL_RULE_DUMP) \ - SW_API_DESC(SW_API_ACL_PT_UDF_PROFILE_SET) \ - SW_API_DESC(SW_API_ACL_PT_UDF_PROFILE_GET) \ - SW_API_DESC(SW_API_ACL_RULE_ACTIVE) \ - SW_API_DESC(SW_API_ACL_RULE_DEACTIVE) \ - SW_API_DESC(SW_API_ACL_RULE_SRC_FILTER_STS_SET) \ - SW_API_DESC(SW_API_ACL_RULE_SRC_FILTER_STS_GET) -#else -#define ACL_API -#define ACL_API_PARAM -#endif - - -#ifdef IN_QOS -#define QOS_API \ - SW_API_DEF(SW_API_QOS_QU_TX_BUF_ST_SET, dess_qos_queue_tx_buf_status_set), \ - SW_API_DEF(SW_API_QOS_QU_TX_BUF_ST_GET, dess_qos_queue_tx_buf_status_get), \ - SW_API_DEF(SW_API_QOS_QU_TX_BUF_NR_SET, dess_qos_queue_tx_buf_nr_set), \ - SW_API_DEF(SW_API_QOS_QU_TX_BUF_NR_GET, dess_qos_queue_tx_buf_nr_get), \ - SW_API_DEF(SW_API_QOS_PT_TX_BUF_ST_SET, dess_qos_port_tx_buf_status_set), \ - SW_API_DEF(SW_API_QOS_PT_TX_BUF_ST_GET, dess_qos_port_tx_buf_status_get), \ - SW_API_DEF(SW_API_QOS_PT_RED_EN_SET, dess_qos_port_red_en_set),\ - SW_API_DEF(SW_API_QOS_PT_RED_EN_GET, dess_qos_port_red_en_get),\ - SW_API_DEF(SW_API_QOS_PT_TX_BUF_NR_SET, dess_qos_port_tx_buf_nr_set), \ - SW_API_DEF(SW_API_QOS_PT_TX_BUF_NR_GET, dess_qos_port_tx_buf_nr_get), \ - SW_API_DEF(SW_API_QOS_PT_RX_BUF_NR_SET, dess_qos_port_rx_buf_nr_set), \ - SW_API_DEF(SW_API_QOS_PT_RX_BUF_NR_GET, dess_qos_port_rx_buf_nr_get), \ - SW_API_DEF(SW_API_QOS_PT_MODE_SET, dess_qos_port_mode_set), \ - SW_API_DEF(SW_API_QOS_PT_MODE_GET, dess_qos_port_mode_get), \ - SW_API_DEF(SW_API_QOS_PT_MODE_PRI_SET, dess_qos_port_mode_pri_set), \ - SW_API_DEF(SW_API_QOS_PT_MODE_PRI_GET, dess_qos_port_mode_pri_get), \ - SW_API_DEF(SW_API_QOS_PORT_SCH_MODE_SET, dess_qos_port_sch_mode_set), \ - SW_API_DEF(SW_API_QOS_PORT_SCH_MODE_GET, dess_qos_port_sch_mode_get), \ - SW_API_DEF(SW_API_QOS_PT_DEF_SPRI_SET, dess_qos_port_default_spri_set), \ - SW_API_DEF(SW_API_QOS_PT_DEF_SPRI_GET, dess_qos_port_default_spri_get), \ - SW_API_DEF(SW_API_QOS_PT_DEF_CPRI_SET, dess_qos_port_default_cpri_set), \ - SW_API_DEF(SW_API_QOS_PT_DEF_CPRI_GET, dess_qos_port_default_cpri_get), \ - SW_API_DEF(SW_API_QOS_PT_FORCE_SPRI_ST_SET, dess_qos_port_force_spri_status_set), \ - SW_API_DEF(SW_API_QOS_PT_FORCE_SPRI_ST_GET, dess_qos_port_force_spri_status_get), \ - SW_API_DEF(SW_API_QOS_PT_FORCE_CPRI_ST_SET, dess_qos_port_force_cpri_status_set), \ - SW_API_DEF(SW_API_QOS_PT_FORCE_CPRI_ST_GET, dess_qos_port_force_cpri_status_get), \ - SW_API_DEF(SW_API_QOS_QUEUE_REMARK_SET, dess_qos_queue_remark_table_set), \ - SW_API_DEF(SW_API_QOS_QUEUE_REMARK_GET, dess_qos_queue_remark_table_get), - - -#define QOS_API_PARAM \ - SW_API_DESC(SW_API_QOS_QU_TX_BUF_ST_SET) \ - SW_API_DESC(SW_API_QOS_QU_TX_BUF_ST_GET) \ - SW_API_DESC(SW_API_QOS_QU_TX_BUF_NR_SET) \ - SW_API_DESC(SW_API_QOS_QU_TX_BUF_NR_GET) \ - SW_API_DESC(SW_API_QOS_PT_TX_BUF_ST_SET) \ - SW_API_DESC(SW_API_QOS_PT_TX_BUF_ST_GET) \ - SW_API_DESC(SW_API_QOS_PT_RED_EN_SET) \ - SW_API_DESC(SW_API_QOS_PT_RED_EN_GET) \ - SW_API_DESC(SW_API_QOS_PT_TX_BUF_NR_SET) \ - SW_API_DESC(SW_API_QOS_PT_TX_BUF_NR_GET) \ - SW_API_DESC(SW_API_QOS_PT_RX_BUF_NR_SET) \ - SW_API_DESC(SW_API_QOS_PT_RX_BUF_NR_GET) \ - SW_API_DESC(SW_API_QOS_PT_MODE_SET) \ - SW_API_DESC(SW_API_QOS_PT_MODE_GET) \ - SW_API_DESC(SW_API_QOS_PT_MODE_PRI_SET) \ - SW_API_DESC(SW_API_QOS_PT_MODE_PRI_GET) \ - SW_API_DESC(SW_API_QOS_PORT_DEF_UP_SET) \ - SW_API_DESC(SW_API_QOS_PORT_DEF_UP_GET) \ - SW_API_DESC(SW_API_QOS_PORT_SCH_MODE_SET) \ - SW_API_DESC(SW_API_QOS_PORT_SCH_MODE_GET) \ - SW_API_DESC(SW_API_QOS_PT_DEF_SPRI_SET) \ - SW_API_DESC(SW_API_QOS_PT_DEF_SPRI_GET) \ - SW_API_DESC(SW_API_QOS_PT_DEF_CPRI_SET) \ - SW_API_DESC(SW_API_QOS_PT_DEF_CPRI_GET) \ - SW_API_DESC(SW_API_QOS_PT_FORCE_SPRI_ST_SET) \ - SW_API_DESC(SW_API_QOS_PT_FORCE_SPRI_ST_GET) \ - SW_API_DESC(SW_API_QOS_PT_FORCE_CPRI_ST_SET) \ - SW_API_DESC(SW_API_QOS_PT_FORCE_CPRI_ST_GET) \ - SW_API_DESC(SW_API_QOS_QUEUE_REMARK_SET) \ - SW_API_DESC(SW_API_QOS_QUEUE_REMARK_GET) -#else -#define QOS_API -#define QOS_API_PARAM -#endif - - -#ifdef IN_IGMP -#define IGMP_API \ - SW_API_DEF(SW_API_PT_IGMPS_MODE_SET, dess_port_igmps_status_set), \ - SW_API_DEF(SW_API_PT_IGMPS_MODE_GET, dess_port_igmps_status_get), \ - SW_API_DEF(SW_API_IGMP_MLD_CMD_SET, dess_igmp_mld_cmd_set), \ - SW_API_DEF(SW_API_IGMP_MLD_CMD_GET, dess_igmp_mld_cmd_get), \ - SW_API_DEF(SW_API_IGMP_PT_JOIN_SET, dess_port_igmp_mld_join_set), \ - SW_API_DEF(SW_API_IGMP_PT_JOIN_GET, dess_port_igmp_mld_join_get), \ - SW_API_DEF(SW_API_IGMP_PT_LEAVE_SET, dess_port_igmp_mld_leave_set), \ - SW_API_DEF(SW_API_IGMP_PT_LEAVE_GET, dess_port_igmp_mld_leave_get), \ - SW_API_DEF(SW_API_IGMP_RP_SET, dess_igmp_mld_rp_set), \ - SW_API_DEF(SW_API_IGMP_RP_GET, dess_igmp_mld_rp_get), \ - SW_API_DEF(SW_API_IGMP_ENTRY_CREAT_SET, dess_igmp_mld_entry_creat_set), \ - SW_API_DEF(SW_API_IGMP_ENTRY_CREAT_GET, dess_igmp_mld_entry_creat_get), \ - SW_API_DEF(SW_API_IGMP_ENTRY_STATIC_SET, dess_igmp_mld_entry_static_set), \ - SW_API_DEF(SW_API_IGMP_ENTRY_STATIC_GET, dess_igmp_mld_entry_static_get), \ - SW_API_DEF(SW_API_IGMP_ENTRY_LEAKY_SET, dess_igmp_mld_entry_leaky_set), \ - SW_API_DEF(SW_API_IGMP_ENTRY_LEAKY_GET, dess_igmp_mld_entry_leaky_get), \ - SW_API_DEF(SW_API_IGMP_ENTRY_V3_SET, dess_igmp_mld_entry_v3_set), \ - SW_API_DEF(SW_API_IGMP_ENTRY_V3_GET, dess_igmp_mld_entry_v3_get), \ - SW_API_DEF(SW_API_IGMP_ENTRY_QUEUE_SET, dess_igmp_mld_entry_queue_set), \ - SW_API_DEF(SW_API_IGMP_ENTRY_QUEUE_GET, dess_igmp_mld_entry_queue_get), \ - SW_API_DEF(SW_API_PT_IGMP_LEARN_LIMIT_SET, dess_port_igmp_mld_learn_limit_set), \ - SW_API_DEF(SW_API_PT_IGMP_LEARN_LIMIT_GET, dess_port_igmp_mld_learn_limit_get), \ - SW_API_DEF(SW_API_PT_IGMP_LEARN_EXCEED_CMD_SET, dess_port_igmp_mld_learn_exceed_cmd_set), \ - SW_API_DEF(SW_API_PT_IGMP_LEARN_EXCEED_CMD_GET, dess_port_igmp_mld_learn_exceed_cmd_get), \ - SW_API_DEF(SW_API_IGMP_SG_ENTRY_SET, dess_igmp_sg_entry_set), \ - SW_API_DEF(SW_API_IGMP_SG_ENTRY_CLEAR, dess_igmp_sg_entry_clear), \ - SW_API_DEF(SW_API_IGMP_SG_ENTRY_SHOW, dess_igmp_sg_entry_show), - -#define IGMP_API_PARAM \ - SW_API_DESC(SW_API_PT_IGMPS_MODE_SET) \ - SW_API_DESC(SW_API_PT_IGMPS_MODE_GET) \ - SW_API_DESC(SW_API_IGMP_MLD_CMD_SET) \ - SW_API_DESC(SW_API_IGMP_MLD_CMD_GET) \ - SW_API_DESC(SW_API_IGMP_PT_JOIN_SET) \ - SW_API_DESC(SW_API_IGMP_PT_JOIN_GET) \ - SW_API_DESC(SW_API_IGMP_PT_LEAVE_SET) \ - SW_API_DESC(SW_API_IGMP_PT_LEAVE_GET) \ - SW_API_DESC(SW_API_IGMP_RP_SET) \ - SW_API_DESC(SW_API_IGMP_RP_GET) \ - SW_API_DESC(SW_API_IGMP_ENTRY_CREAT_SET) \ - SW_API_DESC(SW_API_IGMP_ENTRY_CREAT_GET) \ - SW_API_DESC(SW_API_IGMP_ENTRY_STATIC_SET) \ - SW_API_DESC(SW_API_IGMP_ENTRY_STATIC_GET) \ - SW_API_DESC(SW_API_IGMP_ENTRY_LEAKY_SET) \ - SW_API_DESC(SW_API_IGMP_ENTRY_LEAKY_GET) \ - SW_API_DESC(SW_API_IGMP_ENTRY_V3_SET) \ - SW_API_DESC(SW_API_IGMP_ENTRY_V3_GET) \ - SW_API_DESC(SW_API_IGMP_ENTRY_QUEUE_SET) \ - SW_API_DESC(SW_API_IGMP_ENTRY_QUEUE_GET) \ - SW_API_DESC(SW_API_PT_IGMP_LEARN_LIMIT_SET) \ - SW_API_DESC(SW_API_PT_IGMP_LEARN_LIMIT_GET) \ - SW_API_DESC(SW_API_PT_IGMP_LEARN_EXCEED_CMD_SET) \ - SW_API_DESC(SW_API_PT_IGMP_LEARN_EXCEED_CMD_GET) \ - SW_API_DESC(SW_API_IGMP_SG_ENTRY_SET) \ - SW_API_DESC(SW_API_IGMP_SG_ENTRY_CLEAR) \ - SW_API_DESC(SW_API_IGMP_SG_ENTRY_SHOW) -#else -#define IGMP_API -#define IGMP_API_PARAM -#endif - - -#ifdef IN_LEAKY -#define LEAKY_API \ - SW_API_DEF(SW_API_UC_LEAKY_MODE_SET, dess_uc_leaky_mode_set), \ - SW_API_DEF(SW_API_UC_LEAKY_MODE_GET, dess_uc_leaky_mode_get), \ - SW_API_DEF(SW_API_MC_LEAKY_MODE_SET, dess_mc_leaky_mode_set), \ - SW_API_DEF(SW_API_MC_LEAKY_MODE_GET, dess_mc_leaky_mode_get), \ - SW_API_DEF(SW_API_ARP_LEAKY_MODE_SET, dess_port_arp_leaky_set), \ - SW_API_DEF(SW_API_ARP_LEAKY_MODE_GET, dess_port_arp_leaky_get), \ - SW_API_DEF(SW_API_PT_UC_LEAKY_MODE_SET, dess_port_uc_leaky_set), \ - SW_API_DEF(SW_API_PT_UC_LEAKY_MODE_GET, dess_port_uc_leaky_get), \ - SW_API_DEF(SW_API_PT_MC_LEAKY_MODE_SET, dess_port_mc_leaky_set), \ - SW_API_DEF(SW_API_PT_MC_LEAKY_MODE_GET, dess_port_mc_leaky_get), - -#define LEAKY_API_PARAM \ - SW_API_DESC(SW_API_UC_LEAKY_MODE_SET) \ - SW_API_DESC(SW_API_UC_LEAKY_MODE_GET) \ - SW_API_DESC(SW_API_MC_LEAKY_MODE_SET) \ - SW_API_DESC(SW_API_MC_LEAKY_MODE_GET) \ - SW_API_DESC(SW_API_ARP_LEAKY_MODE_SET) \ - SW_API_DESC(SW_API_ARP_LEAKY_MODE_GET) \ - SW_API_DESC(SW_API_PT_UC_LEAKY_MODE_SET) \ - SW_API_DESC(SW_API_PT_UC_LEAKY_MODE_GET) \ - SW_API_DESC(SW_API_PT_MC_LEAKY_MODE_SET) \ - SW_API_DESC(SW_API_PT_MC_LEAKY_MODE_GET) -#else -#define LEAKY_API -#define LEAKY_API_PARAM -#endif - - -#ifdef IN_MIRROR -#define MIRROR_API \ - SW_API_DEF(SW_API_MIRROR_ANALY_PT_SET, dess_mirr_analysis_port_set), \ - SW_API_DEF(SW_API_MIRROR_ANALY_PT_GET, dess_mirr_analysis_port_get), \ - SW_API_DEF(SW_API_MIRROR_IN_PT_SET, dess_mirr_port_in_set), \ - SW_API_DEF(SW_API_MIRROR_IN_PT_GET, dess_mirr_port_in_get), \ - SW_API_DEF(SW_API_MIRROR_EG_PT_SET, dess_mirr_port_eg_set), \ - SW_API_DEF(SW_API_MIRROR_EG_PT_GET, dess_mirr_port_eg_get), - -#define MIRROR_API_PARAM \ - SW_API_DESC(SW_API_MIRROR_ANALY_PT_SET) \ - SW_API_DESC(SW_API_MIRROR_ANALY_PT_GET) \ - SW_API_DESC(SW_API_MIRROR_IN_PT_SET) \ - SW_API_DESC(SW_API_MIRROR_IN_PT_GET) \ - SW_API_DESC(SW_API_MIRROR_EG_PT_SET) \ - SW_API_DESC(SW_API_MIRROR_EG_PT_GET) -#else -#define MIRROR_API -#define MIRROR_API_PARAM -#endif - - -#ifdef IN_RATE -#define RATE_API \ - SW_API_DEF(SW_API_RATE_PORT_POLICER_SET, dess_rate_port_policer_set), \ - SW_API_DEF(SW_API_RATE_PORT_POLICER_GET, dess_rate_port_policer_get), \ - SW_API_DEF(SW_API_RATE_PORT_SHAPER_SET, dess_rate_port_shaper_set), \ - SW_API_DEF(SW_API_RATE_PORT_SHAPER_GET, dess_rate_port_shaper_get), \ - SW_API_DEF(SW_API_RATE_QUEUE_SHAPER_SET, dess_rate_queue_shaper_set), \ - SW_API_DEF(SW_API_RATE_QUEUE_SHAPER_GET, dess_rate_queue_shaper_get), \ - SW_API_DEF(SW_API_RATE_ACL_POLICER_SET, dess_rate_acl_policer_set), \ - SW_API_DEF(SW_API_RATE_ACL_POLICER_GET, dess_rate_acl_policer_get), \ - SW_API_DEF(SW_API_RATE_PT_ADDRATEBYTE_SET, dess_rate_port_add_rate_byte_set), \ - SW_API_DEF(SW_API_RATE_PT_ADDRATEBYTE_GET, dess_rate_port_add_rate_byte_get), \ - SW_API_DEF(SW_API_RATE_PT_GOL_FLOW_EN_SET, dess_rate_port_gol_flow_en_set), \ - SW_API_DEF(SW_API_RATE_PT_GOL_FLOW_EN_GET, dess_rate_port_gol_flow_en_get), - -#define RATE_API_PARAM \ - SW_API_DESC(SW_API_RATE_PORT_POLICER_SET) \ - SW_API_DESC(SW_API_RATE_PORT_POLICER_GET) \ - SW_API_DESC(SW_API_RATE_PORT_SHAPER_SET) \ - SW_API_DESC(SW_API_RATE_PORT_SHAPER_GET) \ - SW_API_DESC(SW_API_RATE_QUEUE_SHAPER_SET) \ - SW_API_DESC(SW_API_RATE_QUEUE_SHAPER_GET) \ - SW_API_DESC(SW_API_RATE_ACL_POLICER_SET) \ - SW_API_DESC(SW_API_RATE_ACL_POLICER_GET) \ - SW_API_DESC(SW_API_RATE_PT_ADDRATEBYTE_SET) \ - SW_API_DESC(SW_API_RATE_PT_ADDRATEBYTE_GET) \ - SW_API_DESC(SW_API_RATE_PT_GOL_FLOW_EN_SET) \ - SW_API_DESC(SW_API_RATE_PT_GOL_FLOW_EN_GET) -#else -#define RATE_API -#define RATE_API_PARAM -#endif - - -#ifdef IN_STP -#define STP_API \ - SW_API_DEF(SW_API_STP_PT_STATE_SET, dess_stp_port_state_set), \ - SW_API_DEF(SW_API_STP_PT_STATE_GET, dess_stp_port_state_get), - -#define STP_API_PARAM \ - SW_API_DESC(SW_API_STP_PT_STATE_SET) \ - SW_API_DESC(SW_API_STP_PT_STATE_GET) -#else -#define STP_API -#define STP_API_PARAM -#endif - - -#ifdef IN_MIB -#define MIB_API \ - SW_API_DEF(SW_API_PT_MIB_GET, dess_get_mib_info), \ - SW_API_DEF(SW_API_MIB_STATUS_SET, dess_mib_status_set), \ - SW_API_DEF(SW_API_MIB_STATUS_GET, dess_mib_status_get), \ - SW_API_DEF(SW_API_PT_MIB_FLUSH_COUNTERS, dess_mib_port_flush_counters), \ - SW_API_DEF(SW_API_MIB_CPU_KEEP_SET, dess_mib_cpukeep_set), \ - SW_API_DEF(SW_API_MIB_CPU_KEEP_GET, dess_mib_cpukeep_get), - - -#define MIB_API_PARAM \ - SW_API_DESC(SW_API_PT_MIB_GET) \ - SW_API_DESC(SW_API_MIB_STATUS_SET) \ - SW_API_DESC(SW_API_MIB_STATUS_GET)\ - SW_API_DESC(SW_API_PT_MIB_FLUSH_COUNTERS) \ - SW_API_DESC(SW_API_MIB_CPU_KEEP_SET) \ - SW_API_DESC(SW_API_MIB_CPU_KEEP_GET) -#else -#define MIB_API -#define MIB_API_PARAM -#endif - - -#ifdef IN_MISC -#define MISC_API \ - SW_API_DEF(SW_API_FRAME_MAX_SIZE_SET, dess_frame_max_size_set), \ - SW_API_DEF(SW_API_FRAME_MAX_SIZE_GET, dess_frame_max_size_get), \ - SW_API_DEF(SW_API_PT_UNK_UC_FILTER_SET, dess_port_unk_uc_filter_set), \ - SW_API_DEF(SW_API_PT_UNK_UC_FILTER_GET, dess_port_unk_uc_filter_get), \ - SW_API_DEF(SW_API_PT_UNK_MC_FILTER_SET, dess_port_unk_mc_filter_set), \ - SW_API_DEF(SW_API_PT_UNK_MC_FILTER_GET, dess_port_unk_mc_filter_get), \ - SW_API_DEF(SW_API_PT_BC_FILTER_SET, dess_port_bc_filter_set), \ - SW_API_DEF(SW_API_PT_BC_FILTER_GET, dess_port_bc_filter_get), \ - SW_API_DEF(SW_API_CPU_PORT_STATUS_SET, dess_cpu_port_status_set), \ - SW_API_DEF(SW_API_CPU_PORT_STATUS_GET, dess_cpu_port_status_get), \ - SW_API_DEF(SW_API_PPPOE_CMD_SET, dess_pppoe_cmd_set), \ - SW_API_DEF(SW_API_PPPOE_CMD_GET, dess_pppoe_cmd_get), \ - SW_API_DEF(SW_API_PPPOE_STATUS_SET, dess_pppoe_status_set), \ - SW_API_DEF(SW_API_PPPOE_STATUS_GET, dess_pppoe_status_get), \ - SW_API_DEF(SW_API_PT_DHCP_SET, dess_port_dhcp_set), \ - SW_API_DEF(SW_API_PT_DHCP_GET, dess_port_dhcp_get), \ - SW_API_DEF(SW_API_ARP_CMD_SET, dess_arp_cmd_set), \ - SW_API_DEF(SW_API_ARP_CMD_GET, dess_arp_cmd_get), \ - SW_API_DEF(SW_API_EAPOL_CMD_SET, dess_eapol_cmd_set), \ - SW_API_DEF(SW_API_EAPOL_CMD_GET, dess_eapol_cmd_get), \ - SW_API_DEF(SW_API_EAPOL_STATUS_SET, dess_eapol_status_set), \ - SW_API_DEF(SW_API_EAPOL_STATUS_GET, dess_eapol_status_get), \ - SW_API_DEF(SW_API_RIPV1_STATUS_SET, dess_ripv1_status_set), \ - SW_API_DEF(SW_API_RIPV1_STATUS_GET, dess_ripv1_status_get), \ - SW_API_DEF(SW_API_PT_ARP_REQ_STATUS_SET, dess_port_arp_req_status_set), \ - SW_API_DEF(SW_API_PT_ARP_REQ_STATUS_GET, dess_port_arp_req_status_get), \ - SW_API_DEF(SW_API_PT_ARP_ACK_STATUS_SET, dess_port_arp_ack_status_set), \ - SW_API_DEF(SW_API_PT_ARP_ACK_STATUS_GET, dess_port_arp_ack_status_get), \ - SW_API_DEF(SW_API_PPPOE_SESSION_TABLE_ADD, dess_pppoe_session_table_add), \ - SW_API_DEF(SW_API_PPPOE_SESSION_TABLE_DEL, dess_pppoe_session_table_del), \ - SW_API_DEF(SW_API_PPPOE_SESSION_TABLE_GET, dess_pppoe_session_table_get), \ - SW_API_DEF(SW_API_PPPOE_SESSION_ID_SET, dess_pppoe_session_id_set), \ - SW_API_DEF(SW_API_PPPOE_SESSION_ID_GET, dess_pppoe_session_id_get), \ - SW_API_DEF(SW_API_INTR_MASK_SET, dess_intr_mask_set), \ - SW_API_DEF(SW_API_INTR_MASK_GET, dess_intr_mask_get), \ - SW_API_DEF(SW_API_INTR_STATUS_GET, dess_intr_status_get), \ - SW_API_DEF(SW_API_INTR_STATUS_CLEAR, dess_intr_status_clear), \ - SW_API_DEF(SW_API_INTR_PORT_LINK_MASK_SET, dess_intr_port_link_mask_set), \ - SW_API_DEF(SW_API_INTR_PORT_LINK_MASK_GET, dess_intr_port_link_mask_get), \ - SW_API_DEF(SW_API_INTR_PORT_LINK_STATUS_GET, dess_intr_port_link_status_get),\ - SW_API_DEF(SW_API_INTR_MASK_MAC_LINKCHG_SET, dess_intr_mask_mac_linkchg_set), \ - SW_API_DEF(SW_API_INTR_MASK_MAC_LINKCHG_GET, dess_intr_mask_mac_linkchg_get), \ - SW_API_DEF(SW_API_INTR_STATUS_MAC_LINKCHG_GET, dess_intr_status_mac_linkchg_get), \ - SW_API_DEF(SW_API_INTR_STATUS_MAC_LINKCHG_CLEAR, dess_intr_status_mac_linkchg_clear), \ - SW_API_DEF(SW_API_CPU_VID_EN_SET, dess_cpu_vid_en_set), \ - SW_API_DEF(SW_API_CPU_VID_EN_GET, dess_cpu_vid_en_get), \ - SW_API_DEF(SW_API_RTD_PPPOE_EN_SET, dess_rtd_pppoe_en_set), \ - SW_API_DEF(SW_API_RTD_PPPOE_EN_GET, dess_rtd_pppoe_en_get), \ - SW_API_DEF(SW_API_GLOBAL_MACADDR_SET, dess_global_macaddr_set), \ - SW_API_DEF(SW_API_GLOBAL_MACADDR_GET, dess_global_macaddr_get), \ - SW_API_DEF(SW_API_LLDP_STATUS_SET, dess_lldp_status_set), \ - SW_API_DEF(SW_API_LLDP_STATUS_GET, dess_lldp_status_get), \ - SW_API_DEF(SW_API_FRAME_CRC_RESERVE_SET, dess_frame_crc_reserve_set), \ - SW_API_DEF(SW_API_FRAME_CRC_RESERVE_GET, dess_frame_crc_reserve_get), - -#define MISC_API_PARAM \ - SW_API_DESC(SW_API_FRAME_MAX_SIZE_SET) \ - SW_API_DESC(SW_API_FRAME_MAX_SIZE_GET) \ - SW_API_DESC(SW_API_PT_UNK_UC_FILTER_SET) \ - SW_API_DESC(SW_API_PT_UNK_UC_FILTER_GET) \ - SW_API_DESC(SW_API_PT_UNK_MC_FILTER_SET) \ - SW_API_DESC(SW_API_PT_UNK_MC_FILTER_GET) \ - SW_API_DESC(SW_API_PT_BC_FILTER_SET) \ - SW_API_DESC(SW_API_PT_BC_FILTER_GET) \ - SW_API_DESC(SW_API_CPU_PORT_STATUS_SET) \ - SW_API_DESC(SW_API_CPU_PORT_STATUS_GET) \ - SW_API_DESC(SW_API_PPPOE_CMD_SET) \ - SW_API_DESC(SW_API_PPPOE_CMD_GET) \ - SW_API_DESC(SW_API_PPPOE_STATUS_SET) \ - SW_API_DESC(SW_API_PPPOE_STATUS_GET) \ - SW_API_DESC(SW_API_PT_DHCP_SET) \ - SW_API_DESC(SW_API_PT_DHCP_GET) \ - SW_API_DESC(SW_API_ARP_CMD_SET) \ - SW_API_DESC(SW_API_ARP_CMD_GET) \ - SW_API_DESC(SW_API_EAPOL_CMD_SET) \ - SW_API_DESC(SW_API_EAPOL_CMD_GET) \ - SW_API_DESC(SW_API_PPPOE_SESSION_ADD) \ - SW_API_DESC(SW_API_PPPOE_SESSION_DEL) \ - SW_API_DESC(SW_API_PPPOE_SESSION_GET) \ - SW_API_DESC(SW_API_EAPOL_STATUS_SET) \ - SW_API_DESC(SW_API_EAPOL_STATUS_GET) \ - SW_API_DESC(SW_API_RIPV1_STATUS_SET) \ - SW_API_DESC(SW_API_RIPV1_STATUS_GET) \ - SW_API_DESC(SW_API_PT_ARP_REQ_STATUS_SET) \ - SW_API_DESC(SW_API_PT_ARP_REQ_STATUS_GET) \ - SW_API_DESC(SW_API_PT_ARP_ACK_STATUS_SET) \ - SW_API_DESC(SW_API_PT_ARP_ACK_STATUS_GET) \ - SW_API_DESC(SW_API_PPPOE_SESSION_TABLE_ADD) \ - SW_API_DESC(SW_API_PPPOE_SESSION_TABLE_DEL) \ - SW_API_DESC(SW_API_PPPOE_SESSION_TABLE_GET) \ - SW_API_DESC(SW_API_PPPOE_SESSION_ID_SET) \ - SW_API_DESC(SW_API_PPPOE_SESSION_ID_GET) \ - SW_API_DESC(SW_API_INTR_MASK_SET) \ - SW_API_DESC(SW_API_INTR_MASK_GET) \ - SW_API_DESC(SW_API_INTR_STATUS_GET) \ - SW_API_DESC(SW_API_INTR_STATUS_CLEAR) \ - SW_API_DESC(SW_API_INTR_PORT_LINK_MASK_SET) \ - SW_API_DESC(SW_API_INTR_PORT_LINK_MASK_GET) \ - SW_API_DESC(SW_API_INTR_PORT_LINK_STATUS_GET) \ - SW_API_DESC(SW_API_INTR_MASK_MAC_LINKCHG_SET) \ - SW_API_DESC(SW_API_INTR_MASK_MAC_LINKCHG_GET) \ - SW_API_DESC(SW_API_INTR_STATUS_MAC_LINKCHG_GET) \ - SW_API_DESC(SW_API_INTR_STATUS_MAC_LINKCHG_CLEAR) \ - SW_API_DESC(SW_API_CPU_VID_EN_SET) \ - SW_API_DESC(SW_API_CPU_VID_EN_GET) \ - SW_API_DESC(SW_API_RTD_PPPOE_EN_SET) \ - SW_API_DESC(SW_API_RTD_PPPOE_EN_GET) \ - SW_API_DESC(SW_API_GLOBAL_MACADDR_SET) \ - SW_API_DESC(SW_API_GLOBAL_MACADDR_GET) \ - SW_API_DESC(SW_API_LLDP_STATUS_SET) \ - SW_API_DESC(SW_API_LLDP_STATUS_GET) \ - SW_API_DESC(SW_API_FRAME_CRC_RESERVE_SET) \ - SW_API_DESC(SW_API_FRAME_CRC_RESERVE_GET) - -#else -#define MISC_API -#define MISC_API_PARAM -#endif - - -#ifdef IN_LED -#define LED_API \ - SW_API_DEF(SW_API_LED_PATTERN_SET, dess_led_ctrl_pattern_set), \ - SW_API_DEF(SW_API_LED_PATTERN_GET, dess_led_ctrl_pattern_get), - -#define LED_API_PARAM \ - SW_API_DESC(SW_API_LED_PATTERN_SET) \ - SW_API_DESC(SW_API_LED_PATTERN_GET) -#else -#define LED_API -#define LED_API_PARAM -#endif - -#ifdef IN_COSMAP -#define COSMAP_API \ - SW_API_DEF(SW_API_COSMAP_DSCP_TO_PRI_SET, dess_cosmap_dscp_to_pri_set), \ - SW_API_DEF(SW_API_COSMAP_DSCP_TO_PRI_GET, dess_cosmap_dscp_to_pri_get), \ - SW_API_DEF(SW_API_COSMAP_DSCP_TO_DP_SET, dess_cosmap_dscp_to_dp_set), \ - SW_API_DEF(SW_API_COSMAP_DSCP_TO_DP_GET, dess_cosmap_dscp_to_dp_get), \ - SW_API_DEF(SW_API_COSMAP_UP_TO_PRI_SET, dess_cosmap_up_to_pri_set), \ - SW_API_DEF(SW_API_COSMAP_UP_TO_PRI_GET, dess_cosmap_up_to_pri_get), \ - SW_API_DEF(SW_API_COSMAP_UP_TO_DP_SET, dess_cosmap_up_to_dp_set), \ - SW_API_DEF(SW_API_COSMAP_UP_TO_DP_GET, dess_cosmap_up_to_dp_get), \ - SW_API_DEF(SW_API_COSMAP_PRI_TO_QU_SET, dess_cosmap_pri_to_queue_set), \ - SW_API_DEF(SW_API_COSMAP_PRI_TO_QU_GET, dess_cosmap_pri_to_queue_get), \ - SW_API_DEF(SW_API_COSMAP_PRI_TO_EHQU_SET, dess_cosmap_pri_to_ehqueue_set), \ - SW_API_DEF(SW_API_COSMAP_PRI_TO_EHQU_GET, dess_cosmap_pri_to_ehqueue_get), \ - SW_API_DEF(SW_API_COSMAP_EG_REMARK_SET, dess_cosmap_egress_remark_set), \ - SW_API_DEF(SW_API_COSMAP_EG_REMARK_GET, dess_cosmap_egress_remark_get), - -#define COSMAP_API_PARAM \ - SW_API_DESC(SW_API_COSMAP_DSCP_TO_PRI_SET) \ - SW_API_DESC(SW_API_COSMAP_DSCP_TO_PRI_GET) \ - SW_API_DESC(SW_API_COSMAP_DSCP_TO_DP_SET) \ - SW_API_DESC(SW_API_COSMAP_DSCP_TO_DP_GET) \ - SW_API_DESC(SW_API_COSMAP_UP_TO_PRI_SET) \ - SW_API_DESC(SW_API_COSMAP_UP_TO_PRI_GET) \ - SW_API_DESC(SW_API_COSMAP_UP_TO_DP_SET) \ - SW_API_DESC(SW_API_COSMAP_UP_TO_DP_GET) \ - SW_API_DESC(SW_API_COSMAP_PRI_TO_QU_SET) \ - SW_API_DESC(SW_API_COSMAP_PRI_TO_QU_GET) \ - SW_API_DESC(SW_API_COSMAP_PRI_TO_EHQU_SET) \ - SW_API_DESC(SW_API_COSMAP_PRI_TO_EHQU_GET) \ - SW_API_DESC(SW_API_COSMAP_EG_REMARK_SET) \ - SW_API_DESC(SW_API_COSMAP_EG_REMARK_GET) -#else -#define COSMAP_API -#define COSMAP_API_PARAM -#endif - -#ifdef IN_SEC -#define SEC_API \ - SW_API_DEF(SW_API_SEC_NORM_SET, dess_sec_norm_item_set), \ - SW_API_DEF(SW_API_SEC_NORM_GET, dess_sec_norm_item_get), \ - SW_API_DEF(SW_API_SEC_MAC_SET, dess_sec_norm_item_set), \ - SW_API_DEF(SW_API_SEC_MAC_GET, dess_sec_norm_item_get), \ - SW_API_DEF(SW_API_SEC_IP_SET, dess_sec_norm_item_set), \ - SW_API_DEF(SW_API_SEC_IP_GET, dess_sec_norm_item_get), \ - SW_API_DEF(SW_API_SEC_IP4_SET, dess_sec_norm_item_set), \ - SW_API_DEF(SW_API_SEC_IP4_GET, dess_sec_norm_item_get), \ - SW_API_DEF(SW_API_SEC_IP6_SET, dess_sec_norm_item_set), \ - SW_API_DEF(SW_API_SEC_IP6_GET, dess_sec_norm_item_get), \ - SW_API_DEF(SW_API_SEC_TCP_SET, dess_sec_norm_item_set), \ - SW_API_DEF(SW_API_SEC_TCP_GET, dess_sec_norm_item_get), \ - SW_API_DEF(SW_API_SEC_UDP_SET, dess_sec_norm_item_set), \ - SW_API_DEF(SW_API_SEC_UDP_GET, dess_sec_norm_item_get), \ - SW_API_DEF(SW_API_SEC_ICMP4_SET, dess_sec_norm_item_set), \ - SW_API_DEF(SW_API_SEC_ICMP4_GET, dess_sec_norm_item_get), \ - SW_API_DEF(SW_API_SEC_ICMP6_SET, dess_sec_norm_item_set), \ - SW_API_DEF(SW_API_SEC_ICMP6_GET, dess_sec_norm_item_get), - -#define SEC_API_PARAM \ - SW_API_DESC(SW_API_SEC_NORM_SET) \ - SW_API_DESC(SW_API_SEC_NORM_GET) \ - SW_API_DESC(SW_API_SEC_MAC_SET) \ - SW_API_DESC(SW_API_SEC_MAC_GET) \ - SW_API_DESC(SW_API_SEC_IP_SET) \ - SW_API_DESC(SW_API_SEC_IP_GET) \ - SW_API_DESC(SW_API_SEC_IP4_SET) \ - SW_API_DESC(SW_API_SEC_IP4_GET) \ - SW_API_DESC(SW_API_SEC_IP6_SET) \ - SW_API_DESC(SW_API_SEC_IP6_GET) \ - SW_API_DESC(SW_API_SEC_TCP_SET) \ - SW_API_DESC(SW_API_SEC_TCP_GET) \ - SW_API_DESC(SW_API_SEC_UDP_SET) \ - SW_API_DESC(SW_API_SEC_UDP_GET) \ - SW_API_DESC(SW_API_SEC_ICMP4_SET) \ - SW_API_DESC(SW_API_SEC_ICMP4_GET) \ - SW_API_DESC(SW_API_SEC_ICMP6_SET) \ - SW_API_DESC(SW_API_SEC_ICMP6_GET) -#else -#define SEC_API -#define SEC_API_PARAM -#endif - -#ifdef IN_IP -#define IP_API \ - SW_API_DEF(SW_API_IP_HOST_ADD, dess_ip_host_add), \ - SW_API_DEF(SW_API_IP_HOST_DEL, dess_ip_host_del), \ - SW_API_DEF(SW_API_IP_HOST_GET, dess_ip_host_get), \ - SW_API_DEF(SW_API_IP_HOST_NEXT, dess_ip_host_next), \ - SW_API_DEF(SW_API_IP_HOST_COUNTER_BIND, dess_ip_host_counter_bind), \ - SW_API_DEF(SW_API_IP_HOST_PPPOE_BIND, dess_ip_host_pppoe_bind), \ - SW_API_DEF(SW_API_IP_PT_ARP_LEARN_SET, dess_ip_pt_arp_learn_set), \ - SW_API_DEF(SW_API_IP_PT_ARP_LEARN_GET, dess_ip_pt_arp_learn_get), \ - SW_API_DEF(SW_API_IP_ARP_LEARN_SET, dess_ip_arp_learn_set), \ - SW_API_DEF(SW_API_IP_ARP_LEARN_GET, dess_ip_arp_learn_get), \ - SW_API_DEF(SW_API_IP_SOURCE_GUARD_SET, dess_ip_source_guard_set), \ - SW_API_DEF(SW_API_IP_SOURCE_GUARD_GET, dess_ip_source_guard_get), \ - SW_API_DEF(SW_API_IP_ARP_GUARD_SET, dess_ip_arp_guard_set), \ - SW_API_DEF(SW_API_IP_ARP_GUARD_GET, dess_ip_arp_guard_get), \ - SW_API_DEF(SW_API_IP_ROUTE_STATUS_SET, dess_ip_route_status_set), \ - SW_API_DEF(SW_API_IP_ROUTE_STATUS_GET, dess_ip_route_status_get), \ - SW_API_DEF(SW_API_IP_INTF_ENTRY_ADD, dess_ip_intf_entry_add), \ - SW_API_DEF(SW_API_IP_INTF_ENTRY_DEL, dess_ip_intf_entry_del), \ - SW_API_DEF(SW_API_IP_INTF_ENTRY_NEXT, dess_ip_intf_entry_next), \ - SW_API_DEF(SW_API_IP_UNK_SOURCE_CMD_SET, dess_ip_unk_source_cmd_set), \ - SW_API_DEF(SW_API_IP_UNK_SOURCE_CMD_GET, dess_ip_unk_source_cmd_get), \ - SW_API_DEF(SW_API_ARP_UNK_SOURCE_CMD_SET, dess_arp_unk_source_cmd_set), \ - SW_API_DEF(SW_API_ARP_UNK_SOURCE_CMD_GET, dess_arp_unk_source_cmd_get), \ - SW_API_DEF(SW_API_IP_AGE_TIME_SET, dess_ip_age_time_set), \ - SW_API_DEF(SW_API_IP_AGE_TIME_GET, dess_ip_age_time_get), \ - SW_API_DEF(SW_API_WCMP_HASH_MODE_SET, dess_ip_wcmp_hash_mode_set), \ - SW_API_DEF(SW_API_WCMP_HASH_MODE_GET, dess_ip_wcmp_hash_mode_get), \ - SW_API_DEF(SW_API_IP_DEFAULT_FLOW_CMD_SET, dess_default_flow_cmd_set), \ - SW_API_DEF(SW_API_IP_DEFAULT_FLOW_CMD_GET, dess_default_flow_cmd_get), \ - SW_API_DEF(SW_API_IP_DEFAULT_RT_FLOW_CMD_SET, dess_default_rt_flow_cmd_set), \ - SW_API_DEF(SW_API_IP_DEFAULT_RT_FLOW_CMD_GET, dess_default_rt_flow_cmd_get), - -#define IP_API_PARAM \ - SW_API_DESC(SW_API_IP_HOST_ADD) \ - SW_API_DESC(SW_API_IP_HOST_DEL) \ - SW_API_DESC(SW_API_IP_HOST_GET) \ - SW_API_DESC(SW_API_IP_HOST_NEXT) \ - SW_API_DESC(SW_API_IP_HOST_COUNTER_BIND) \ - SW_API_DESC(SW_API_IP_HOST_PPPOE_BIND) \ - SW_API_DESC(SW_API_IP_PT_ARP_LEARN_SET) \ - SW_API_DESC(SW_API_IP_PT_ARP_LEARN_GET) \ - SW_API_DESC(SW_API_IP_ARP_LEARN_SET) \ - SW_API_DESC(SW_API_IP_ARP_LEARN_GET) \ - SW_API_DESC(SW_API_IP_SOURCE_GUARD_SET) \ - SW_API_DESC(SW_API_IP_SOURCE_GUARD_GET) \ - SW_API_DESC(SW_API_IP_ARP_GUARD_SET) \ - SW_API_DESC(SW_API_IP_ARP_GUARD_GET) \ - SW_API_DESC(SW_API_IP_ROUTE_STATUS_SET) \ - SW_API_DESC(SW_API_IP_ROUTE_STATUS_GET) \ - SW_API_DESC(SW_API_IP_INTF_ENTRY_ADD) \ - SW_API_DESC(SW_API_IP_INTF_ENTRY_DEL) \ - SW_API_DESC(SW_API_IP_INTF_ENTRY_NEXT) \ - SW_API_DESC(SW_API_IP_UNK_SOURCE_CMD_SET) \ - SW_API_DESC(SW_API_IP_UNK_SOURCE_CMD_GET) \ - SW_API_DESC(SW_API_ARP_UNK_SOURCE_CMD_SET) \ - SW_API_DESC(SW_API_ARP_UNK_SOURCE_CMD_GET) \ - SW_API_DESC(SW_API_IP_AGE_TIME_SET) \ - SW_API_DESC(SW_API_IP_AGE_TIME_GET) \ - SW_API_DESC(SW_API_WCMP_HASH_MODE_SET) \ - SW_API_DESC(SW_API_WCMP_HASH_MODE_GET) \ - SW_API_DESC(SW_API_IP_DEFAULT_FLOW_CMD_SET) \ - SW_API_DESC(SW_API_IP_DEFAULT_FLOW_CMD_GET) \ - SW_API_DESC(SW_API_IP_DEFAULT_RT_FLOW_CMD_SET) \ - SW_API_DESC(SW_API_IP_DEFAULT_RT_FLOW_CMD_GET) - -#else -#define IP_API -#define IP_API_PARAM -#endif - -#ifdef IN_NAT -#define NAT_API \ - SW_API_DEF(SW_API_NAT_ADD, dess_nat_add), \ - SW_API_DEF(SW_API_NAT_DEL, dess_nat_del), \ - SW_API_DEF(SW_API_NAT_GET, dess_nat_get), \ - SW_API_DEF(SW_API_NAT_NEXT, dess_nat_next), \ - SW_API_DEF(SW_API_NAT_COUNTER_BIND, dess_nat_counter_bind), \ - SW_API_DEF(SW_API_NAPT_ADD, dess_napt_add), \ - SW_API_DEF(SW_API_NAPT_DEL, dess_napt_del), \ - SW_API_DEF(SW_API_NAPT_GET, dess_napt_get), \ - SW_API_DEF(SW_API_NAPT_NEXT, dess_napt_next), \ - SW_API_DEF(SW_API_NAPT_COUNTER_BIND, dess_napt_counter_bind), \ - SW_API_DEF(SW_API_FLOW_ADD, dess_flow_add), \ - SW_API_DEF(SW_API_FLOW_DEL, dess_flow_del), \ - SW_API_DEF(SW_API_FLOW_GET, dess_flow_get), \ - SW_API_DEF(SW_API_FLOW_NEXT, dess_flow_next), \ - SW_API_DEF(SW_API_FLOW_COUNTER_BIND, dess_flow_counter_bind), \ - SW_API_DEF(SW_API_NAT_STATUS_SET, dess_nat_status_set), \ - SW_API_DEF(SW_API_NAT_STATUS_GET, dess_nat_status_get), \ - SW_API_DEF(SW_API_NAT_HASH_MODE_SET, dess_nat_hash_mode_set), \ - SW_API_DEF(SW_API_NAT_HASH_MODE_GET, dess_nat_hash_mode_get), \ - SW_API_DEF(SW_API_NAPT_STATUS_SET, dess_napt_status_set), \ - SW_API_DEF(SW_API_NAPT_STATUS_GET, dess_napt_status_get), \ - SW_API_DEF(SW_API_NAPT_MODE_SET, dess_napt_mode_set), \ - SW_API_DEF(SW_API_NAPT_MODE_GET, dess_napt_mode_get), \ - SW_API_DEF(SW_API_PRV_BASE_ADDR_SET, dess_nat_prv_base_addr_set), \ - SW_API_DEF(SW_API_PRV_BASE_ADDR_GET, dess_nat_prv_base_addr_get), \ - SW_API_DEF(SW_API_PUB_ADDR_ENTRY_ADD, dess_nat_pub_addr_add), \ - SW_API_DEF(SW_API_PUB_ADDR_ENTRY_DEL, dess_nat_pub_addr_del), \ - SW_API_DEF(SW_API_PUB_ADDR_ENTRY_NEXT, dess_nat_pub_addr_next), \ - SW_API_DEF(SW_API_NAT_UNK_SESSION_CMD_SET, dess_nat_unk_session_cmd_set), \ - SW_API_DEF(SW_API_NAT_UNK_SESSION_CMD_GET, dess_nat_unk_session_cmd_get), \ - SW_API_DEF(SW_API_PRV_BASE_MASK_SET, dess_nat_prv_base_mask_set), \ - SW_API_DEF(SW_API_PRV_BASE_MASK_GET, dess_nat_prv_base_mask_get), \ - SW_API_DEF(SW_API_NAT_GLOBAL_SET, dess_nat_global_set), - -#define NAT_API_PARAM \ - SW_API_DESC(SW_API_NAT_ADD) \ - SW_API_DESC(SW_API_NAT_DEL) \ - SW_API_DESC(SW_API_NAT_GET) \ - SW_API_DESC(SW_API_NAT_NEXT) \ - SW_API_DESC(SW_API_NAT_COUNTER_BIND) \ - SW_API_DESC(SW_API_NAPT_ADD) \ - SW_API_DESC(SW_API_NAPT_DEL) \ - SW_API_DESC(SW_API_NAPT_GET) \ - SW_API_DESC(SW_API_NAPT_NEXT) \ - SW_API_DESC(SW_API_NAPT_COUNTER_BIND) \ - SW_API_DESC(SW_API_FLOW_ADD) \ - SW_API_DESC(SW_API_FLOW_DEL) \ - SW_API_DESC(SW_API_FLOW_GET) \ - SW_API_DESC(SW_API_FLOW_NEXT) \ - SW_API_DESC(SW_API_FLOW_COUNTER_BIND) \ - SW_API_DESC(SW_API_NAT_STATUS_SET) \ - SW_API_DESC(SW_API_NAT_STATUS_GET) \ - SW_API_DESC(SW_API_NAT_HASH_MODE_SET) \ - SW_API_DESC(SW_API_NAT_HASH_MODE_GET) \ - SW_API_DESC(SW_API_NAPT_STATUS_SET) \ - SW_API_DESC(SW_API_NAPT_STATUS_GET) \ - SW_API_DESC(SW_API_NAPT_MODE_SET) \ - SW_API_DESC(SW_API_NAPT_MODE_GET) \ - SW_API_DESC(SW_API_PRV_BASE_ADDR_SET) \ - SW_API_DESC(SW_API_PRV_BASE_ADDR_GET) \ - SW_API_DESC(SW_API_PUB_ADDR_ENTRY_ADD) \ - SW_API_DESC(SW_API_PUB_ADDR_ENTRY_DEL) \ - SW_API_DESC(SW_API_PUB_ADDR_ENTRY_NEXT) \ - SW_API_DESC(SW_API_NAT_UNK_SESSION_CMD_SET) \ - SW_API_DESC(SW_API_NAT_UNK_SESSION_CMD_GET) \ - SW_API_DESC(SW_API_PRV_BASE_MASK_SET) \ - SW_API_DESC(SW_API_PRV_BASE_MASK_GET) \ - SW_API_DESC(SW_API_NAT_GLOBAL_SET) -#else -#define NAT_API -#define NAT_API_PARAM -#endif - -#ifdef IN_TRUNK -#define TRUNK_API \ - SW_API_DEF(SW_API_TRUNK_GROUP_SET, dess_trunk_group_set), \ - SW_API_DEF(SW_API_TRUNK_GROUP_GET, dess_trunk_group_get), \ - SW_API_DEF(SW_API_TRUNK_HASH_SET, dess_trunk_hash_mode_set), \ - SW_API_DEF(SW_API_TRUNK_HASH_GET, dess_trunk_hash_mode_get), \ - SW_API_DEF(SW_API_TRUNK_MAN_SA_SET, dess_trunk_manipulate_sa_set), \ - SW_API_DEF(SW_API_TRUNK_MAN_SA_GET, dess_trunk_manipulate_sa_get), - -#define TRUNK_API_PARAM \ - SW_API_DESC(SW_API_TRUNK_GROUP_SET) \ - SW_API_DESC(SW_API_TRUNK_GROUP_GET) \ - SW_API_DESC(SW_API_TRUNK_HASH_SET) \ - SW_API_DESC(SW_API_TRUNK_HASH_GET) \ - SW_API_DESC(SW_API_TRUNK_MAN_SA_SET)\ - SW_API_DESC(SW_API_TRUNK_MAN_SA_GET) -#else -#define TRUNK_API -#define TRUNK_API_PARAM -#endif - -#ifdef IN_INTERFACECONTROL -#define INTERFACECTRL_API \ - SW_API_DEF(SW_API_MAC_MODE_SET, dess_interface_mac_mode_set), \ - SW_API_DEF(SW_API_MAC_MODE_GET, dess_interface_mac_mode_get), \ - SW_API_DEF(SW_API_PORT_3AZ_STATUS_SET, dess_port_3az_status_set), \ - SW_API_DEF(SW_API_PORT_3AZ_STATUS_GET, dess_port_3az_status_get), \ - SW_API_DEF(SW_API_PHY_MODE_SET, dess_interface_phy_mode_set), \ - SW_API_DEF(SW_API_PHY_MODE_GET, dess_interface_phy_mode_get), \ - SW_API_DEF(SW_API_FX100_CTRL_SET, dess_interface_fx100_ctrl_set), \ - SW_API_DEF(SW_API_FX100_CTRL_GET, dess_interface_fx100_ctrl_get), \ - SW_API_DEF(SW_API_FX100_STATUS_GET, dess_interface_fx100_status_get), \ - SW_API_DEF(SW_API_MAC06_EXCH_SET, dess_interface_mac06_exch_set), \ - SW_API_DEF(SW_API_MAC06_EXCH_GET, dess_interface_mac06_exch_get), - -#define INTERFACECTRL_API_PARAM \ - SW_API_DESC(SW_API_MAC_MODE_SET) \ - SW_API_DESC(SW_API_MAC_MODE_GET) \ - SW_API_DESC(SW_API_PORT_3AZ_STATUS_SET) \ - SW_API_DESC(SW_API_PORT_3AZ_STATUS_GET) \ - SW_API_DESC(SW_API_PHY_MODE_SET) \ - SW_API_DESC(SW_API_PHY_MODE_GET) \ - SW_API_DESC(SW_API_FX100_CTRL_SET) \ - SW_API_DESC(SW_API_FX100_CTRL_GET) \ - SW_API_DESC(SW_API_FX100_STATUS_GET) \ - SW_API_DESC(SW_API_MAC06_EXCH_SET) \ - SW_API_DESC(SW_API_MAC06_EXCH_GET) - -#else -#define INTERFACECTRL_API -#define INTERFACECTRL_API_PARAM -#endif - -#define REG_API \ - SW_API_DEF(SW_API_PHY_GET, dess_phy_get), \ - SW_API_DEF(SW_API_PHY_SET, dess_phy_set), \ - SW_API_DEF(SW_API_REG_GET, dess_reg_get), \ - SW_API_DEF(SW_API_PSGMII_REG_SET, dess_psgmii_reg_set), \ - SW_API_DEF(SW_API_PSGMII_REG_GET, dess_psgmii_reg_get), \ - SW_API_DEF(SW_API_REG_SET, dess_reg_set), \ - SW_API_DEF(SW_API_REG_FIELD_GET, dess_reg_field_get), \ - SW_API_DEF(SW_API_REG_FIELD_SET, dess_reg_field_set), \ - SW_API_DEF(SW_API_REG_DUMP, dess_regsiter_dump), \ - SW_API_DEF(SW_API_DBG_REG_DUMP, dess_debug_regsiter_dump), \ - SW_API_DEF(SW_API_DBG_PSGMII_SELF_TEST, fal_debug_psgmii_self_test), \ - SW_API_DEF(SW_API_PHY_DUMP, fal_phy_dump), - - -#define REG_API_PARAM \ - SW_API_DESC(SW_API_PHY_GET) \ - SW_API_DESC(SW_API_PHY_SET) \ - SW_API_DESC(SW_API_REG_GET) \ - SW_API_DESC(SW_API_REG_SET) \ - SW_API_DESC(SW_API_PSGMII_REG_GET) \ - SW_API_DESC(SW_API_PSGMII_REG_SET) \ - SW_API_DESC(SW_API_REG_FIELD_GET) \ - SW_API_DESC(SW_API_REG_FIELD_SET) \ - SW_API_DESC(SW_API_REG_DUMP) \ - SW_API_DESC(SW_API_DBG_REG_DUMP) \ - SW_API_DESC(SW_API_DBG_PSGMII_SELF_TEST) \ - SW_API_DESC(SW_API_PHY_DUMP) - - - -#define SSDK_API \ - SW_API_DEF(SW_API_SWITCH_RESET, dess_reset), \ - SW_API_DEF(SW_API_SSDK_CFG, hsl_ssdk_cfg), \ - PORTCONTROL_API \ - VLAN_API \ - PORTVLAN_API \ - FDB_API \ - ACL_API \ - QOS_API \ - IGMP_API \ - LEAKY_API \ - MIRROR_API \ - RATE_API \ - STP_API \ - MIB_API \ - MISC_API \ - LED_API \ - COSMAP_API \ - SEC_API \ - IP_API \ - NAT_API \ - TRUNK_API \ - INTERFACECTRL_API \ - REG_API \ - SW_API_DEF(SW_API_MAX, NULL), - - -#define SSDK_PARAM \ - SW_PARAM_DEF(SW_API_SWITCH_RESET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \ - SW_PARAM_DEF(SW_API_SSDK_CFG, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \ - SW_PARAM_DEF(SW_API_SSDK_CFG, SW_SSDK_CFG, sizeof(ssdk_cfg_t), SW_PARAM_PTR|SW_PARAM_OUT, "ssdk configuration"), \ - MIB_API_PARAM \ - LEAKY_API_PARAM \ - MISC_API_PARAM \ - IGMP_API_PARAM \ - MIRROR_API_PARAM \ - PORTCONTROL_API_PARAM \ - PORTVLAN_API_PARAM \ - VLAN_API_PARAM \ - FDB_API_PARAM \ - QOS_API_PARAM \ - RATE_API_PARAM \ - STP_API_PARAM \ - ACL_API_PARAM \ - LED_API_PARAM \ - COSMAP_API_PARAM \ - SEC_API_PARAM \ - IP_API_PARAM \ - NAT_API_PARAM \ - TRUNK_API_PARAM \ - INTERFACECTRL_API_PARAM \ - REG_API_PARAM \ - SW_PARAM_DEF(SW_API_MAX, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), - -#if (defined(USER_MODE) && defined(KERNEL_MODULE)) -#undef SSDK_API -#undef SSDK_PARAM - -#define SSDK_API \ - REG_API \ - SW_API_DEF(SW_API_MAX, NULL), - -#define SSDK_PARAM \ - REG_API_PARAM \ - SW_PARAM_DEF(SW_API_MAX, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), -#endif - -#ifdef __cplusplus -} -#endif /* __cplusplus */ - -#endif /* _DESS_API_H_ */ -_ */ diff --git a/feeds/ipq807x/qca-ssdk/src/include/hsl/dess/dess_cosmap.h b/feeds/ipq807x/qca-ssdk/src/include/hsl/dess/dess_cosmap.h deleted file mode 100755 index 5ab114121..000000000 --- a/feeds/ipq807x/qca-ssdk/src/include/hsl/dess/dess_cosmap.h +++ /dev/null @@ -1,141 +0,0 @@ -/* - * Copyright (c) 2014, The Linux Foundation. All rights reserved. - * Permission to use, copy, modify, and/or distribute this software for - * any purpose with or without fee is hereby granted, provided that the - * above copyright notice and this permission notice appear in all copies. - * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES - * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR - * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES - * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN - * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT - * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. - */ - - -/** - * @defgroup dess_cosmap DESS_COSMAP - * @{ - */ -#ifndef _DESS_COSMAP_H_ -#define _DESS_COSMAP_H_ - -#ifdef __cplusplus -extern "C" { -#endif /* __cplusplus */ - -#include "fal/fal_cosmap.h" - - sw_error_t dess_cosmap_init(a_uint32_t dev_id); - -#ifdef IN_COSMAP -#define DESS_COSMAP_INIT(rv, dev_id) \ - { \ - rv = dess_cosmap_init(dev_id); \ - SW_RTN_ON_ERROR(rv); \ - } -#else -#define DESS_COSMAP_INIT(rv, dev_id) -#endif - -#ifdef HSL_STANDALONG - - HSL_LOCAL sw_error_t - dess_cosmap_dscp_to_pri_set(a_uint32_t dev_id, a_uint32_t dscp, - a_uint32_t pri); - - HSL_LOCAL sw_error_t - dess_cosmap_dscp_to_pri_get(a_uint32_t dev_id, a_uint32_t dscp, - a_uint32_t * pri); - - HSL_LOCAL sw_error_t - dess_cosmap_dscp_to_dp_set(a_uint32_t dev_id, a_uint32_t dscp, - a_uint32_t dp); - - HSL_LOCAL sw_error_t - dess_cosmap_dscp_to_dp_get(a_uint32_t dev_id, a_uint32_t dscp, - a_uint32_t * dp); - - HSL_LOCAL sw_error_t - dess_cosmap_up_to_pri_set(a_uint32_t dev_id, a_uint32_t up, - a_uint32_t pri); - - HSL_LOCAL sw_error_t - dess_cosmap_up_to_pri_get(a_uint32_t dev_id, a_uint32_t up, - a_uint32_t * pri); - - HSL_LOCAL sw_error_t - dess_cosmap_up_to_dp_set(a_uint32_t dev_id, a_uint32_t up, - a_uint32_t dp); - - HSL_LOCAL sw_error_t - dess_cosmap_up_to_dp_get(a_uint32_t dev_id, a_uint32_t up, - a_uint32_t * dp); - - HSL_LOCAL sw_error_t - dess_cosmap_dscp_to_ehpri_set(a_uint32_t dev_id, a_uint32_t dscp, - a_uint32_t pri); - - HSL_LOCAL sw_error_t - dess_cosmap_dscp_to_ehpri_get(a_uint32_t dev_id, a_uint32_t dscp, - a_uint32_t * pri); - - HSL_LOCAL sw_error_t - dess_cosmap_dscp_to_ehdp_set(a_uint32_t dev_id, a_uint32_t dscp, - a_uint32_t dp); - - HSL_LOCAL sw_error_t - dess_cosmap_dscp_to_ehdp_get(a_uint32_t dev_id, a_uint32_t dscp, - a_uint32_t * dp); - - HSL_LOCAL sw_error_t - dess_cosmap_up_to_ehpri_set(a_uint32_t dev_id, a_uint32_t up, - a_uint32_t pri); - - HSL_LOCAL sw_error_t - dess_cosmap_up_to_ehpri_get(a_uint32_t dev_id, a_uint32_t up, - a_uint32_t * pri); - - HSL_LOCAL sw_error_t - dess_cosmap_up_to_ehdp_set(a_uint32_t dev_id, a_uint32_t up, - a_uint32_t dp); - - HSL_LOCAL sw_error_t - dess_cosmap_up_to_ehdp_get(a_uint32_t dev_id, a_uint32_t up, - a_uint32_t * dp); - - HSL_LOCAL sw_error_t - dess_cosmap_pri_to_queue_set(a_uint32_t dev_id, a_uint32_t pri, - a_uint32_t queue); - - HSL_LOCAL sw_error_t - dess_cosmap_pri_to_queue_get(a_uint32_t dev_id, a_uint32_t pri, - a_uint32_t * queue); - - HSL_LOCAL sw_error_t - dess_cosmap_pri_to_ehqueue_set(a_uint32_t dev_id, a_uint32_t pri, - a_uint32_t queue); - - HSL_LOCAL sw_error_t - dess_cosmap_pri_to_ehqueue_get(a_uint32_t dev_id, a_uint32_t pri, - a_uint32_t * queue); - - HSL_LOCAL sw_error_t - dess_cosmap_egress_remark_set(a_uint32_t dev_id, a_uint32_t tbl_id, - fal_egress_remark_table_t * tbl); - - HSL_LOCAL sw_error_t - dess_cosmap_egress_remark_get(a_uint32_t dev_id, a_uint32_t tbl_id, - fal_egress_remark_table_t * tbl); - -#endif - -#ifdef __cplusplus -} -#endif /* __cplusplus */ -#endif /* _DESS_COSMAP_H_ */ - -/** - * @} - */ - diff --git a/feeds/ipq807x/qca-ssdk/src/include/hsl/dess/dess_fdb.h b/feeds/ipq807x/qca-ssdk/src/include/hsl/dess/dess_fdb.h deleted file mode 100755 index 801c9c363..000000000 --- a/feeds/ipq807x/qca-ssdk/src/include/hsl/dess/dess_fdb.h +++ /dev/null @@ -1,168 +0,0 @@ -/* - * Copyright (c) 2014, The Linux Foundation. All rights reserved. - * Permission to use, copy, modify, and/or distribute this software for - * any purpose with or without fee is hereby granted, provided that the - * above copyright notice and this permission notice appear in all copies. - * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES - * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR - * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES - * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN - * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT - * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. - */ - - -/** - * @defgroup dess_fdb DESS_FDB - * @{ - */ -#ifndef _DESS_FDB_H_ -#define _DESS_FDB_H_ - -#ifdef __cplusplus -extern "C" { -#endif /* __cplusplus */ - -#include "fal/fal_fdb.h" - - sw_error_t dess_fdb_init(a_uint32_t dev_id); - -#ifdef IN_FDB -#define DESS_FDB_INIT(rv, dev_id) \ - { \ - rv = dess_fdb_init(dev_id); \ - SW_RTN_ON_ERROR(rv); \ - } -#else -#define DESS_FDB_INIT(rv, dev_id) -#endif - -#ifdef HSL_STANDALONG - - HSL_LOCAL sw_error_t - dess_fdb_add(a_uint32_t dev_id, const fal_fdb_entry_t * entry); - - HSL_LOCAL sw_error_t - dess_fdb_find(a_uint32_t dev_id, fal_fdb_entry_t * entry); - - HSL_LOCAL sw_error_t - dess_fdb_del_all(a_uint32_t dev_id, a_uint32_t flag); - - HSL_LOCAL sw_error_t - dess_fdb_del_by_port(a_uint32_t dev_id, fal_port_t port_id, - a_uint32_t flag); - - HSL_LOCAL sw_error_t - dess_fdb_del_by_mac(a_uint32_t dev_id, const fal_fdb_entry_t * entry); - - HSL_LOCAL sw_error_t - dess_fdb_extend_next(a_uint32_t dev_id, fal_fdb_op_t * op, - fal_fdb_entry_t * entry); - - HSL_LOCAL sw_error_t - dess_fdb_extend_first(a_uint32_t dev_id, fal_fdb_op_t * option, - fal_fdb_entry_t * entry); - - HSL_LOCAL sw_error_t - dess_fdb_transfer(a_uint32_t dev_id, fal_port_t old_port, - fal_port_t new_port, a_uint32_t fid, - fal_fdb_op_t * option); - - HSL_LOCAL sw_error_t - dess_fdb_port_learn_set(a_uint32_t dev_id, fal_port_t port_id, - a_bool_t enable); - - HSL_LOCAL sw_error_t - dess_fdb_port_learn_get(a_uint32_t dev_id, fal_port_t port_id, - a_bool_t * enable); - - HSL_LOCAL sw_error_t - dess_fdb_age_ctrl_set(a_uint32_t dev_id, a_bool_t enable); - - HSL_LOCAL sw_error_t - dess_fdb_age_ctrl_get(a_uint32_t dev_id, a_bool_t * enable); - - HSL_LOCAL sw_error_t - dess_fdb_vlan_ivl_svl_set(a_uint32_t dev_id, fal_fdb_smode smode); - - HSL_LOCAL sw_error_t - dess_fdb_vlan_ivl_svl_get(a_uint32_t dev_id, fal_fdb_smode * smode); - - HSL_LOCAL sw_error_t - dess_fdb_age_time_set(a_uint32_t dev_id, a_uint32_t * time); - - HSL_LOCAL sw_error_t - dess_fdb_age_time_get(a_uint32_t dev_id, a_uint32_t * time); - - HSL_LOCAL sw_error_t - dess_port_fdb_learn_limit_set(a_uint32_t dev_id, fal_port_t port_id, - a_bool_t enable, a_uint32_t cnt); - - HSL_LOCAL sw_error_t - dess_port_fdb_learn_limit_get(a_uint32_t dev_id, fal_port_t port_id, - a_bool_t * enable, a_uint32_t * cnt); - - HSL_LOCAL sw_error_t - dess_port_fdb_learn_exceed_cmd_set(a_uint32_t dev_id, - fal_port_t port_id, - fal_fwd_cmd_t cmd); - - HSL_LOCAL sw_error_t - dess_port_fdb_learn_exceed_cmd_get(a_uint32_t dev_id, - fal_port_t port_id, - fal_fwd_cmd_t * cmd); - - HSL_LOCAL sw_error_t - dess_fdb_learn_limit_set(a_uint32_t dev_id, a_bool_t enable, - a_uint32_t cnt); - - HSL_LOCAL sw_error_t - dess_fdb_learn_limit_get(a_uint32_t dev_id, a_bool_t * enable, - a_uint32_t * cnt); - - HSL_LOCAL sw_error_t - dess_fdb_learn_exceed_cmd_set(a_uint32_t dev_id, fal_fwd_cmd_t cmd); - - HSL_LOCAL sw_error_t - dess_fdb_learn_exceed_cmd_get(a_uint32_t dev_id, fal_fwd_cmd_t * cmd); - - HSL_LOCAL sw_error_t - dess_fdb_resv_add(a_uint32_t dev_id, fal_fdb_entry_t * entry); - - HSL_LOCAL sw_error_t - dess_fdb_resv_del(a_uint32_t dev_id, fal_fdb_entry_t * entry); - - HSL_LOCAL sw_error_t - dess_fdb_resv_find(a_uint32_t dev_id, fal_fdb_entry_t * entry); - - HSL_LOCAL sw_error_t - dess_fdb_resv_iterate(a_uint32_t dev_id, a_uint32_t * iterator, - fal_fdb_entry_t * entry); - - HSL_LOCAL sw_error_t - dess_fdb_port_learn_static_set(a_uint32_t dev_id, fal_port_t port_id, - a_bool_t enable); - - HSL_LOCAL sw_error_t - dess_fdb_port_learn_static_get(a_uint32_t dev_id, fal_port_t port_id, - a_bool_t * enable); - - HSL_LOCAL sw_error_t - dess_fdb_port_add(a_uint32_t dev_id, a_uint32_t fid, fal_mac_addr_t * addr, fal_port_t port_id); - - HSL_LOCAL sw_error_t - dess_fdb_port_del(a_uint32_t dev_id, a_uint32_t fid, fal_mac_addr_t * addr, fal_port_t port_id); - - -#endif - -#ifdef __cplusplus -} -#endif /* __cplusplus */ -#endif /* _DESS_FDB_H_ */ - -/** - * @} - */ - diff --git a/feeds/ipq807x/qca-ssdk/src/include/hsl/dess/dess_fdb_prv.h b/feeds/ipq807x/qca-ssdk/src/include/hsl/dess/dess_fdb_prv.h deleted file mode 100755 index e0f4f0a83..000000000 --- a/feeds/ipq807x/qca-ssdk/src/include/hsl/dess/dess_fdb_prv.h +++ /dev/null @@ -1,49 +0,0 @@ -/* - * Copyright (c) 2014, The Linux Foundation. All rights reserved. - * Permission to use, copy, modify, and/or distribute this software for - * any purpose with or without fee is hereby granted, provided that the - * above copyright notice and this permission notice appear in all copies. - * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES - * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR - * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES - * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN - * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT - * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. - */ - - -#ifndef _DESS_FDB_PRV_H_ -#define _DESS_FDB_PRV_H_ - -#ifdef __cplusplus -extern "C" { -#endif /* __cplusplus */ - - -#define ARL_FLUSH_ALL 1 -#define ARL_LOAD_ENTRY 2 -#define ARL_PURGE_ENTRY 3 -#define ARL_FLUSH_ALL_UNLOCK 4 -#define ARL_FLUSH_PORT_UNICAST 5 -#define ARL_NEXT_ENTRY 6 -#define ARL_FIND_ENTRY 7 -#define ARL_TRANSFER_ENTRY 8 - -#define ARL_FIRST_ENTRY 1001 -#define ARL_FLUSH_PORT_NO_STATIC 1002 -#define ARL_FLUSH_PORT_AND_STATIC 1003 - -#define DESS_MAX_FID 4095 -#define DESS_MAX_LEARN_LIMIT_CNT 2048 -#define DESS_MAX_PORT_LEARN_LIMIT_CNT 1024 - - sw_error_t - inter_dess_fdb_flush(a_uint32_t dev_id, a_uint32_t flag); - - -#ifdef __cplusplus -} -#endif /* __cplusplus */ -#endif /* _DESS_FDB_PRV_H_ */ - diff --git a/feeds/ipq807x/qca-ssdk/src/include/hsl/dess/dess_igmp.h b/feeds/ipq807x/qca-ssdk/src/include/hsl/dess/dess_igmp.h deleted file mode 100755 index bc808814e..000000000 --- a/feeds/ipq807x/qca-ssdk/src/include/hsl/dess/dess_igmp.h +++ /dev/null @@ -1,165 +0,0 @@ -/* - * Copyright (c) 2014 The Linux Foundation. All rights reserved. - * Permission to use, copy, modify, and/or distribute this software for - * any purpose with or without fee is hereby granted, provided that the - * above copyright notice and this permission notice appear in all copies. - * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES - * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR - * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES - * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN - * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT - * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. - */ - - -/** - * @defgroup dess_igmp DESS_IGMP - * @{ - */ -#ifndef _DESS_IGMP_H_ -#define _DESS_IGMP_H_ - -#ifdef __cplusplus -extern "C" { -#endif /* __cplusplus */ - -#include "fal/fal_igmp.h" -#include "fal/fal_multi.h" - - sw_error_t - dess_igmp_init(a_uint32_t dev_id); - -#ifdef IN_IGMP -#define DESS_IGMP_INIT(rv, dev_id) \ - { \ - rv = dess_igmp_init(dev_id); \ - SW_RTN_ON_ERROR(rv); \ - } -#else -#define DESS_IGMP_INIT(rv, dev_id) -#endif - -#ifdef HSL_STANDALONG - - HSL_LOCAL sw_error_t - dess_port_igmps_status_set(a_uint32_t dev_id, fal_port_t port_id, a_bool_t enable); - - - HSL_LOCAL sw_error_t - dess_port_igmps_status_get(a_uint32_t dev_id, fal_port_t port_id, a_bool_t *enable); - - - HSL_LOCAL sw_error_t - dess_igmp_mld_cmd_set(a_uint32_t dev_id, fal_fwd_cmd_t cmd); - - - HSL_LOCAL sw_error_t - dess_igmp_mld_cmd_get(a_uint32_t dev_id, fal_fwd_cmd_t * cmd); - - - HSL_LOCAL sw_error_t - dess_port_igmp_mld_join_set(a_uint32_t dev_id, fal_port_t port_id, a_bool_t enable); - - - HSL_LOCAL sw_error_t - dess_port_igmp_mld_join_get(a_uint32_t dev_id, fal_port_t port_id, a_bool_t * enable); - - - HSL_LOCAL sw_error_t - dess_port_igmp_mld_leave_set(a_uint32_t dev_id, fal_port_t port_id, a_bool_t enable); - - - HSL_LOCAL sw_error_t - dess_port_igmp_mld_leave_get(a_uint32_t dev_id, fal_port_t port_id, a_bool_t * enable); - - - HSL_LOCAL sw_error_t - dess_igmp_mld_rp_set(a_uint32_t dev_id, fal_pbmp_t pts); - - - HSL_LOCAL sw_error_t - dess_igmp_mld_rp_get(a_uint32_t dev_id, fal_pbmp_t * pts); - - - HSL_LOCAL sw_error_t - dess_igmp_mld_entry_creat_set(a_uint32_t dev_id, a_bool_t enable); - - - HSL_LOCAL sw_error_t - dess_igmp_mld_entry_creat_get(a_uint32_t dev_id, a_bool_t * enable); - - - HSL_LOCAL sw_error_t - dess_igmp_mld_entry_static_set(a_uint32_t dev_id, a_bool_t enable); - - - HSL_LOCAL sw_error_t - dess_igmp_mld_entry_static_get(a_uint32_t dev_id, a_bool_t * enable); - - - HSL_LOCAL sw_error_t - dess_igmp_mld_entry_leaky_set(a_uint32_t dev_id, a_bool_t enable); - - - HSL_LOCAL sw_error_t - dess_igmp_mld_entry_leaky_get(a_uint32_t dev_id, a_bool_t * enable); - - - HSL_LOCAL sw_error_t - dess_igmp_mld_entry_v3_set(a_uint32_t dev_id, a_bool_t enable); - - - HSL_LOCAL sw_error_t - dess_igmp_mld_entry_v3_get(a_uint32_t dev_id, a_bool_t * enable); - - - HSL_LOCAL sw_error_t - dess_igmp_mld_entry_queue_set(a_uint32_t dev_id, a_bool_t enable, a_uint32_t queue); - - - HSL_LOCAL sw_error_t - dess_igmp_mld_entry_queue_get(a_uint32_t dev_id, a_bool_t * enable, a_uint32_t * queue); - - - HSL_LOCAL sw_error_t - dess_port_igmp_mld_learn_limit_set(a_uint32_t dev_id, fal_port_t port_id, - a_bool_t enable, a_uint32_t cnt); - - - HSL_LOCAL sw_error_t - dess_port_igmp_mld_learn_limit_get(a_uint32_t dev_id, fal_port_t port_id, - a_bool_t * enable, a_uint32_t * cnt); - - - HSL_LOCAL sw_error_t - dess_port_igmp_mld_learn_exceed_cmd_set(a_uint32_t dev_id, fal_port_t port_id, - fal_fwd_cmd_t cmd); - - - HSL_LOCAL sw_error_t - dess_port_igmp_mld_learn_exceed_cmd_get(a_uint32_t dev_id, fal_port_t port_id, - fal_fwd_cmd_t * cmd); - - HSL_LOCAL sw_error_t - dess_igmp_sg_entry_set(a_uint32_t dev_id, fal_igmp_sg_entry_t * entry); - - HSL_LOCAL sw_error_t - dess_igmp_sg_entry_clear(a_uint32_t dev_id, fal_igmp_sg_entry_t * entry); - - HSL_LOCAL sw_error_t - dess_igmp_sg_entry_show(a_uint32_t dev_id); - - HSL_LOCAL sw_error_t - dess_igmp_sg_entry_query(a_uint32_t dev_id, fal_igmp_sg_info_t * info); - -#endif - -#ifdef __cplusplus -} -#endif /* __cplusplus */ - -#endif /* _DESS_IGMP_H_ */ -/** - * @} - */ diff --git a/feeds/ipq807x/qca-ssdk/src/include/hsl/dess/dess_init.h b/feeds/ipq807x/qca-ssdk/src/include/hsl/dess/dess_init.h deleted file mode 100755 index 77671512a..000000000 --- a/feeds/ipq807x/qca-ssdk/src/include/hsl/dess/dess_init.h +++ /dev/null @@ -1,44 +0,0 @@ -/* - * Copyright (c) 2014, The Linux Foundation. All rights reserved. - * Permission to use, copy, modify, and/or distribute this software for - * any purpose with or without fee is hereby granted, provided that the - * above copyright notice and this permission notice appear in all copies. - * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES - * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR - * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES - * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN - * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT - * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. - */ - - -/** - * @defgroup dess_init DESS_INIT - * @{ - */ -#ifndef _DESS_INIT_H_ -#define _DESS_INIT_H_ - -#ifdef __cplusplus -extern "C" { -#endif /* __cplusplus */ - -#include "init/ssdk_init.h" - - - sw_error_t - dess_init(a_uint32_t dev_id, ssdk_init_cfg *cfg); - - - sw_error_t - dess_cleanup(a_uint32_t dev_id); - -#ifdef __cplusplus -} -#endif /* __cplusplus */ - -#endif /* _DESS_INIT_H_ */ -/** - * @} - */ diff --git a/feeds/ipq807x/qca-ssdk/src/include/hsl/dess/dess_interface_ctrl.h b/feeds/ipq807x/qca-ssdk/src/include/hsl/dess/dess_interface_ctrl.h deleted file mode 100755 index 08f313434..000000000 --- a/feeds/ipq807x/qca-ssdk/src/include/hsl/dess/dess_interface_ctrl.h +++ /dev/null @@ -1,58 +0,0 @@ -/* - * Copyright (c) 2014, The Linux Foundation. All rights reserved. - * Permission to use, copy, modify, and/or distribute this software for - * any purpose with or without fee is hereby granted, provided that the - * above copyright notice and this permission notice appear in all copies. - * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES - * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR - * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES - * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN - * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT - * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. - */ - - -#ifndef _DESS_INTERFACE_CTRL_H_ -#define _DESS_INTERFACE_CTRL_H_ - -#ifdef __cplusplus -extern "C" { -#endif /* __cplusplus */ - -#include "fal/fal_interface_ctrl.h" - - sw_error_t dess_interface_ctrl_init(a_uint32_t dev_id); - -#ifdef IN_INTERFACECONTROL -#define DESS_INTERFACE_CTRL_INIT(rv, dev_id) \ - { \ - rv = dess_interface_ctrl_init(dev_id); \ - SW_RTN_ON_ERROR(rv); \ - } -#else -#define DESS_INTERFACE_CTRL_INIT(rv, dev_id) -#endif - -#ifdef HSL_STANDALONG - - HSL_LOCAL sw_error_t - dess_port_3az_status_set(a_uint32_t dev_id, fal_port_t port_id, a_bool_t enable); - - HSL_LOCAL sw_error_t - dess_port_3az_status_get(a_uint32_t dev_id, fal_port_t port_id, a_bool_t * enable); - - - HSL_LOCAL sw_error_t - dess_interface_mac_mode_get(a_uint32_t dev_id, fal_port_t port_id, fal_mac_config_t * config); - - HSL_LOCAL sw_error_t - dess_interface_mac_mode_set(a_uint32_t dev_id, fal_port_t port_id, fal_mac_config_t * config); - -#endif - -#ifdef __cplusplus -} -#endif /* __cplusplus */ -#endif /* _DESS_INTERFACE_CTRL_H_ */ - diff --git a/feeds/ipq807x/qca-ssdk/src/include/hsl/dess/dess_ip.h b/feeds/ipq807x/qca-ssdk/src/include/hsl/dess/dess_ip.h deleted file mode 100755 index 339bd83c6..000000000 --- a/feeds/ipq807x/qca-ssdk/src/include/hsl/dess/dess_ip.h +++ /dev/null @@ -1,201 +0,0 @@ -/* - * Copyright (c) 2014-2015, The Linux Foundation. All rights reserved. - * Permission to use, copy, modify, and/or distribute this software for - * any purpose with or without fee is hereby granted, provided that the - * above copyright notice and this permission notice appear in all copies. - * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES - * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR - * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES - * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN - * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT - * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. - */ - - -#ifndef _DESS_IP_H_ -#define _DESS_IP_H_ - -#ifdef __cplusplus -extern "C" { -#endif /* __cplusplus */ - -#include "fal/fal_ip.h" - - sw_error_t dess_ip_init(a_uint32_t dev_id); - - sw_error_t dess_ip_reset(a_uint32_t dev_id); - -#ifdef IN_IP -#define DESS_IP_INIT(rv, dev_id) \ - { \ - rv = dess_ip_init(dev_id); \ - SW_RTN_ON_ERROR(rv); \ - } - -#define DESS_IP_RESET(rv, dev_id) \ - { \ - rv = dess_ip_reset(dev_id); \ - SW_RTN_ON_ERROR(rv); \ - } -#else -#define DESS_IP_INIT(rv, dev_id) -#define DESS_IP_RESET(rv, dev_id) -#endif - -#ifdef HSL_STANDALONG - - HSL_LOCAL sw_error_t - dess_ip_host_add(a_uint32_t dev_id, fal_host_entry_t * host_entry); - - HSL_LOCAL sw_error_t - dess_ip_intf_entry_add(a_uint32_t dev_id, fal_intf_mac_entry_t * entry); - - HSL_LOCAL sw_error_t - dess_ip_host_del(a_uint32_t dev_id, a_uint32_t del_mode, - fal_host_entry_t * host_entry); - - HSL_LOCAL sw_error_t - dess_ip_host_get(a_uint32_t dev_id, a_uint32_t get_mode, - fal_host_entry_t * host_entry); - - HSL_LOCAL sw_error_t - dess_ip_host_next(a_uint32_t dev_id, a_uint32_t next_mode, - fal_host_entry_t * host_entry); - - HSL_LOCAL sw_error_t - dess_ip_host_counter_bind(a_uint32_t dev_id, a_uint32_t entry_id, - a_uint32_t cnt_id, a_bool_t enable); - - HSL_LOCAL sw_error_t - dess_ip_host_pppoe_bind(a_uint32_t dev_id, a_uint32_t entry_id, - a_uint32_t pppoe_id, a_bool_t enable); - - HSL_LOCAL sw_error_t - dess_ip_pt_arp_learn_set(a_uint32_t dev_id, fal_port_t port_id, - a_uint32_t flags); - - HSL_LOCAL sw_error_t - dess_ip_pt_arp_learn_get(a_uint32_t dev_id, fal_port_t port_id, - a_uint32_t * flags); - - HSL_LOCAL sw_error_t - dess_ip_arp_learn_set(a_uint32_t dev_id, fal_arp_learn_mode_t mode); - - HSL_LOCAL sw_error_t - dess_ip_arp_learn_get(a_uint32_t dev_id, fal_arp_learn_mode_t * mode); - - HSL_LOCAL sw_error_t - dess_ip_source_guard_set(a_uint32_t dev_id, fal_port_t port_id, - fal_source_guard_mode_t mode); - - HSL_LOCAL sw_error_t - dess_ip_source_guard_get(a_uint32_t dev_id, fal_port_t port_id, - fal_source_guard_mode_t * mode); - - HSL_LOCAL sw_error_t - dess_ip_unk_source_cmd_set(a_uint32_t dev_id, fal_fwd_cmd_t cmd); - - HSL_LOCAL sw_error_t - dess_ip_unk_source_cmd_get(a_uint32_t dev_id, fal_fwd_cmd_t * cmd); - - HSL_LOCAL sw_error_t - dess_ip_arp_guard_set(a_uint32_t dev_id, fal_port_t port_id, - fal_source_guard_mode_t mode); - - HSL_LOCAL sw_error_t - dess_ip_arp_guard_get(a_uint32_t dev_id, fal_port_t port_id, - fal_source_guard_mode_t * mode); - - HSL_LOCAL sw_error_t - dess_arp_unk_source_cmd_set(a_uint32_t dev_id, fal_fwd_cmd_t cmd); - - HSL_LOCAL sw_error_t - dess_arp_unk_source_cmd_get(a_uint32_t dev_id, fal_fwd_cmd_t * cmd); - - HSL_LOCAL sw_error_t - dess_ip_route_status_set(a_uint32_t dev_id, a_bool_t enable); - - HSL_LOCAL sw_error_t - dess_ip_route_status_get(a_uint32_t dev_id, a_bool_t * enable); - - HSL_LOCAL sw_error_t - dess_ip_intf_entry_del(a_uint32_t dev_id, a_uint32_t del_mode, - fal_intf_mac_entry_t * entry); - - HSL_LOCAL sw_error_t - dess_ip_intf_entry_next(a_uint32_t dev_id, a_uint32_t next_mode, - fal_intf_mac_entry_t * entry); - - HSL_LOCAL sw_error_t - dess_ip_age_time_set(a_uint32_t dev_id, a_uint32_t * time); - - HSL_LOCAL sw_error_t - dess_ip_age_time_get(a_uint32_t dev_id, a_uint32_t * time); - - HSL_LOCAL sw_error_t - dess_ip_wcmp_entry_set(a_uint32_t dev_id, a_uint32_t wcmp_id, fal_ip_wcmp_t * wcmp); - - HSL_LOCAL sw_error_t - dess_ip_wcmp_entry_get(a_uint32_t dev_id, a_uint32_t wcmp_id, fal_ip_wcmp_t * wcmp); - - HSL_LOCAL sw_error_t - dess_ip_rfs_ip4_set(a_uint32_t dev_id, fal_ip4_rfs_t * rfs); - - HSL_LOCAL sw_error_t - dess_ip_rfs_ip6_set(a_uint32_t dev_id, fal_ip6_rfs_t * rfs); - - HSL_LOCAL sw_error_t - dess_ip_rfs_ip4_del(a_uint32_t dev_id, fal_ip4_rfs_t * rfs); - - HSL_LOCAL sw_error_t - dess_ip_rfs_ip6_del(a_uint32_t dev_id, fal_ip6_rfs_t * rfs); - - HSL_LOCAL sw_error_t - dess_ip_wcmp_hash_mode_set(a_uint32_t dev_id, a_uint32_t hash_mode); - - HSL_LOCAL sw_error_t - dess_ip_wcmp_hash_mode_get(a_uint32_t dev_id, a_uint32_t * hash_mode); - - HSL_LOCAL sw_error_t - dess_ip_vrf_base_addr_set(a_uint32_t dev_id, a_uint32_t vrf_id, fal_ip4_addr_t addr); - - HSL_LOCAL sw_error_t - dess_ip_vrf_base_addr_get(a_uint32_t dev_id, a_uint32_t vrf_id, fal_ip4_addr_t * addr); - - HSL_LOCAL sw_error_t - dess_ip_vrf_base_mask_set(a_uint32_t dev_id, a_uint32_t vrf_id, fal_ip4_addr_t addr); - - HSL_LOCAL sw_error_t - dess_ip_vrf_base_mask_get(a_uint32_t dev_id, a_uint32_t vrf_id, fal_ip4_addr_t * addr); - - HSL_LOCAL sw_error_t - dess_ip_default_route_set(a_uint32_t dev_id, a_uint32_t droute_id, fal_default_route_t * entry); - - HSL_LOCAL sw_error_t - dess_ip_default_route_get(a_uint32_t dev_id, a_uint32_t droute_id, fal_default_route_t * entry); - - HSL_LOCAL sw_error_t - dess_ip_host_route_set(a_uint32_t dev_id, a_uint32_t hroute_id, fal_host_route_t * entry); - - HSL_LOCAL sw_error_t - dess_ip_host_route_get(a_uint32_t dev_id, a_uint32_t hroute_id, fal_host_route_t * entry); - - HSL_LOCAL sw_error_t - dess_default_flow_cmd_set(a_uint32_t dev_id, a_uint32_t vrf_id, fal_flow_type_t type, fal_default_flow_cmd_t cmd); - - HSL_LOCAL sw_error_t - dess_default_flow_cmd_get(a_uint32_t dev_id, a_uint32_t vrf_id, fal_flow_type_t type, fal_default_flow_cmd_t * cmd); - - HSL_LOCAL sw_error_t - dess_default_rt_flow_cmd_set(a_uint32_t dev_id, a_uint32_t vrf_id, fal_flow_type_t type, fal_default_flow_cmd_t cmd); - - HSL_LOCAL sw_error_t - dess_default_rt_flow_cmd_get(a_uint32_t dev_id, a_uint32_t vrf_id, fal_flow_type_t type, fal_default_flow_cmd_t * cmd); - -#endif - -#ifdef __cplusplus -} -#endif /* __cplusplus */ -#endif /* _DESS_IP_H_ */ diff --git a/feeds/ipq807x/qca-ssdk/src/include/hsl/dess/dess_leaky.h b/feeds/ipq807x/qca-ssdk/src/include/hsl/dess/dess_leaky.h deleted file mode 100755 index a4d3fdaed..000000000 --- a/feeds/ipq807x/qca-ssdk/src/include/hsl/dess/dess_leaky.h +++ /dev/null @@ -1,94 +0,0 @@ -/* - * Copyright (c) 2014, The Linux Foundation. All rights reserved. - * Permission to use, copy, modify, and/or distribute this software for - * any purpose with or without fee is hereby granted, provided that the - * above copyright notice and this permission notice appear in all copies. - * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES - * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR - * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES - * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN - * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT - * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. - */ - - -#ifndef _DESS_LEAKY_H_ -#define _DESS_LEAKY_H_ - -#ifdef __cplusplus -extern "C" { -#endif /* __cplusplus */ - -#include "fal/fal_leaky.h" - - sw_error_t dess_leaky_init(a_uint32_t dev_id); - -#ifdef IN_LEAKY -#define DESS_LEAKY_INIT(rv, dev_id) \ - { \ - rv = dess_leaky_init(dev_id); \ - SW_RTN_ON_ERROR(rv); \ - } -#else -#define DESS_LEAKY_INIT(rv, dev_id) -#endif - -#ifdef HSL_STANDALONG - - - HSL_LOCAL sw_error_t - dess_uc_leaky_mode_set(a_uint32_t dev_id, - fal_leaky_ctrl_mode_t ctrl_mode); - - - HSL_LOCAL sw_error_t - dess_uc_leaky_mode_get(a_uint32_t dev_id, - fal_leaky_ctrl_mode_t * ctrl_mode); - - - HSL_LOCAL sw_error_t - dess_mc_leaky_mode_set(a_uint32_t dev_id, - fal_leaky_ctrl_mode_t ctrl_mode); - - - HSL_LOCAL sw_error_t - dess_mc_leaky_mode_get(a_uint32_t dev_id, - fal_leaky_ctrl_mode_t * ctrl_mode); - - - HSL_LOCAL sw_error_t - dess_port_arp_leaky_set(a_uint32_t dev_id, fal_port_t port_id, - a_bool_t enable); - - - HSL_LOCAL sw_error_t - dess_port_arp_leaky_get(a_uint32_t dev_id, fal_port_t port_id, - a_bool_t * enable); - - - HSL_LOCAL sw_error_t - dess_port_uc_leaky_set(a_uint32_t dev_id, fal_port_t port_id, - a_bool_t enable); - - - HSL_LOCAL sw_error_t - dess_port_uc_leaky_get(a_uint32_t dev_id, fal_port_t port_id, - a_bool_t * enable); - - - HSL_LOCAL sw_error_t - dess_port_mc_leaky_set(a_uint32_t dev_id, fal_port_t port_id, - a_bool_t enable); - - - HSL_LOCAL sw_error_t - dess_port_mc_leaky_get(a_uint32_t dev_id, fal_port_t port_id, - a_bool_t * enable); -#endif - -#ifdef __cplusplus -} -#endif /* __cplusplus */ -#endif /* _DESS_LEAKY_H_ */ - diff --git a/feeds/ipq807x/qca-ssdk/src/include/hsl/dess/dess_led.h b/feeds/ipq807x/qca-ssdk/src/include/hsl/dess/dess_led.h deleted file mode 100755 index 77da266a8..000000000 --- a/feeds/ipq807x/qca-ssdk/src/include/hsl/dess/dess_led.h +++ /dev/null @@ -1,61 +0,0 @@ -/* - * Copyright (c) 2014, The Linux Foundation. All rights reserved. - * Permission to use, copy, modify, and/or distribute this software for - * any purpose with or without fee is hereby granted, provided that the - * above copyright notice and this permission notice appear in all copies. - * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES - * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR - * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES - * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN - * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT - * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. - */ - - -#ifndef _DESS_LED_H_ -#define _DESS_LED_H_ - -#ifdef __cplusplus -extern "C" { -#endif /* __cplusplus */ - -#include "fal/fal_led.h" - - sw_error_t - dess_led_init(a_uint32_t dev_id); - -#ifdef IN_LED -#define DESS_LED_INIT(rv, dev_id) \ - { \ - rv = dess_led_init(dev_id); \ - SW_RTN_ON_ERROR(rv); \ - } -#else -#define DESS_LED_INIT(rv, dev_id) -#endif - -#ifdef HSL_STANDALONG - - - HSL_LOCAL sw_error_t - dess_led_ctrl_pattern_set(a_uint32_t dev_id, led_pattern_group_t group, - led_pattern_id_t id, led_ctrl_pattern_t * pattern); - - - HSL_LOCAL sw_error_t - dess_led_ctrl_pattern_get(a_uint32_t dev_id, led_pattern_group_t group, - led_pattern_id_t id, led_ctrl_pattern_t * pattern); - - HSL_LOCAL sw_error_t - dess_led_source_pattern_set(a_uint32_t dev_id, a_uint32_t source_id, led_ctrl_pattern_t * pattern); - - -#endif - -#ifdef __cplusplus -} -#endif /* __cplusplus */ - -#endif /* _DESS_LED_H_ */ - diff --git a/feeds/ipq807x/qca-ssdk/src/include/hsl/dess/dess_mib.h b/feeds/ipq807x/qca-ssdk/src/include/hsl/dess/dess_mib.h deleted file mode 100755 index 12dfb299f..000000000 --- a/feeds/ipq807x/qca-ssdk/src/include/hsl/dess/dess_mib.h +++ /dev/null @@ -1,69 +0,0 @@ -/* - * Copyright (c) 2014, The Linux Foundation. All rights reserved. - * Permission to use, copy, modify, and/or distribute this software for - * any purpose with or without fee is hereby granted, provided that the - * above copyright notice and this permission notice appear in all copies. - * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES - * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR - * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES - * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN - * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT - * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. - */ - - -#ifndef _DESS_MIB_H_ -#define _DESS_MIB_H_ - -#ifdef __cplusplus -extern "C" { -#endif /* __cplusplus */ - -#include "fal/fal_mib.h" - - sw_error_t - dess_mib_init(a_uint32_t dev_id); - -#ifdef IN_MIB -#define DESS_MIB_INIT(rv, dev_id) \ - { \ - rv = dess_mib_init(dev_id); \ - SW_RTN_ON_ERROR(rv); \ - } -#else -#define DESS_MIB_INIT(rv, dev_id) -#endif - -#ifdef HSL_STANDALONG - - HSL_LOCAL sw_error_t - dess_get_mib_info(a_uint32_t dev_id, fal_port_t port_id, - fal_mib_info_t * mib_info ); - - - HSL_LOCAL sw_error_t - dess_mib_status_set(a_uint32_t dev_id, a_bool_t enable); - - - HSL_LOCAL sw_error_t - dess_mib_status_get(a_uint32_t dev_id, a_bool_t * enable); - - HSL_LOCAL sw_error_t - dess_mib_port_flush_counters(a_uint32_t dev_id, fal_port_t port_id); - - HSL_LOCAL sw_error_t - dess_mib_cpukeep_set(a_uint32_t dev_id, a_bool_t enable); - - - HSL_LOCAL sw_error_t - dess_mib_cpukeep_get(a_uint32_t dev_id, a_bool_t * enable); - -#endif - -#ifdef __cplusplus -} -#endif /* __cplusplus */ - -#endif /* _DESS_MIB_H_ */ - diff --git a/feeds/ipq807x/qca-ssdk/src/include/hsl/dess/dess_mirror.h b/feeds/ipq807x/qca-ssdk/src/include/hsl/dess/dess_mirror.h deleted file mode 100755 index 88c1e4fdf..000000000 --- a/feeds/ipq807x/qca-ssdk/src/include/hsl/dess/dess_mirror.h +++ /dev/null @@ -1,73 +0,0 @@ -/* - * Copyright (c) 2014, The Linux Foundation. All rights reserved. - * Permission to use, copy, modify, and/or distribute this software for - * any purpose with or without fee is hereby granted, provided that the - * above copyright notice and this permission notice appear in all copies. - * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES - * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR - * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES - * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN - * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT - * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. - */ - - -#ifndef _DESS_MIRROR_H_ -#define _DESS_MIRROR_H_ - -#ifdef __cplusplus -extern "C" { -#endif /* __cplusplus */ - -#include "fal/fal_mirror.h" -#define MIRROR_ANALYZER_NONE 0xf - - sw_error_t dess_mirr_init(a_uint32_t dev_id); - -#ifdef IN_MIRROR -#define DESS_MIRR_INIT(rv, dev_id) \ - { \ - rv = dess_mirr_init(dev_id); \ - SW_RTN_ON_ERROR(rv); \ - } -#else -#define DESS_MIRR_INIT(rv, dev_id) -#endif - -#ifdef HSL_STANDALONG - - HSL_LOCAL sw_error_t - dess_mirr_analysis_port_set(a_uint32_t dev_id, fal_port_t port_id); - - - HSL_LOCAL sw_error_t - dess_mirr_analysis_port_get(a_uint32_t dev_id, fal_port_t * port_id); - - - HSL_LOCAL sw_error_t - dess_mirr_port_in_set(a_uint32_t dev_id, fal_port_t port_id, - a_bool_t enable); - - - HSL_LOCAL sw_error_t - dess_mirr_port_in_get(a_uint32_t dev_id, fal_port_t port_id, - a_bool_t * enable); - - - HSL_LOCAL sw_error_t - dess_mirr_port_eg_set(a_uint32_t dev_id, fal_port_t port_id, - a_bool_t enable); - - - HSL_LOCAL sw_error_t - dess_mirr_port_eg_get(a_uint32_t dev_id, fal_port_t port_id, - a_bool_t * enable); - -#endif - -#ifdef __cplusplus -} -#endif /* __cplusplus */ -#endif /* _DESS_MIRROR_H_ */ - diff --git a/feeds/ipq807x/qca-ssdk/src/include/hsl/dess/dess_misc.h b/feeds/ipq807x/qca-ssdk/src/include/hsl/dess/dess_misc.h deleted file mode 100755 index 961e812b2..000000000 --- a/feeds/ipq807x/qca-ssdk/src/include/hsl/dess/dess_misc.h +++ /dev/null @@ -1,258 +0,0 @@ -/* - * Copyright (c) 2014, The Linux Foundation. All rights reserved. - * Permission to use, copy, modify, and/or distribute this software for - * any purpose with or without fee is hereby granted, provided that the - * above copyright notice and this permission notice appear in all copies. - * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES - * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR - * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES - * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN - * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT - * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. - */ - - -#ifndef _DESS_MISC_H_ -#define _DESS_MISC_H_ - -#ifdef __cplusplus -extern "C" { -#endif /* __cplusplus */ - -#include "fal/fal_misc.h" - - sw_error_t dess_misc_init(a_uint32_t dev_id); - -#ifdef IN_MISC -#define DESS_MISC_INIT(rv, dev_id) \ - { \ - rv = dess_misc_init(dev_id); \ - SW_RTN_ON_ERROR(rv); \ - } -#else -#define DESS_MISC_INIT(rv, dev_id) -#endif - -#ifdef HSL_STANDALONG - - - HSL_LOCAL sw_error_t - dess_frame_max_size_set(a_uint32_t dev_id, a_uint32_t size); - - - HSL_LOCAL sw_error_t - dess_frame_max_size_get(a_uint32_t dev_id, a_uint32_t * size); - - - HSL_LOCAL sw_error_t - dess_port_unk_uc_filter_set(a_uint32_t dev_id, fal_port_t port_id, - a_bool_t enable); - - - HSL_LOCAL sw_error_t - dess_port_unk_uc_filter_get(a_uint32_t dev_id, fal_port_t port_id, - a_bool_t * enable); - - - HSL_LOCAL sw_error_t - dess_port_unk_mc_filter_set(a_uint32_t dev_id, fal_port_t port_id, - a_bool_t enable); - - - HSL_LOCAL sw_error_t - dess_port_unk_mc_filter_get(a_uint32_t dev_id, fal_port_t port_id, - a_bool_t * enable); - - - HSL_LOCAL sw_error_t - dess_port_bc_filter_set(a_uint32_t dev_id, fal_port_t port_id, - a_bool_t enable); - - - HSL_LOCAL sw_error_t - dess_port_bc_filter_get(a_uint32_t dev_id, fal_port_t port_id, - a_bool_t * enable); - - - HSL_LOCAL sw_error_t - dess_cpu_port_status_set(a_uint32_t dev_id, a_bool_t enable); - - - HSL_LOCAL sw_error_t - dess_cpu_port_status_get(a_uint32_t dev_id, a_bool_t * enable); - - - HSL_LOCAL sw_error_t - dess_pppoe_cmd_set(a_uint32_t dev_id, fal_fwd_cmd_t cmd); - - - HSL_LOCAL sw_error_t - dess_pppoe_cmd_get(a_uint32_t dev_id, fal_fwd_cmd_t * cmd); - - - HSL_LOCAL sw_error_t - dess_pppoe_status_set(a_uint32_t dev_id, a_bool_t enable); - - - HSL_LOCAL sw_error_t - dess_pppoe_status_get(a_uint32_t dev_id, a_bool_t * enable); - - - HSL_LOCAL sw_error_t - dess_port_dhcp_set(a_uint32_t dev_id, fal_port_t port_id, a_bool_t enable); - - - HSL_LOCAL sw_error_t - dess_port_dhcp_get(a_uint32_t dev_id, fal_port_t port_id, a_bool_t * enable); - - - HSL_LOCAL sw_error_t - dess_arp_cmd_set(a_uint32_t dev_id, fal_fwd_cmd_t cmd); - - - HSL_LOCAL sw_error_t - dess_arp_cmd_get(a_uint32_t dev_id, fal_fwd_cmd_t * cmd); - - - HSL_LOCAL sw_error_t - dess_eapol_cmd_set(a_uint32_t dev_id, fal_fwd_cmd_t cmd); - - - HSL_LOCAL sw_error_t - dess_eapol_cmd_get(a_uint32_t dev_id, fal_fwd_cmd_t * cmd); - - - HSL_LOCAL sw_error_t - dess_pppoe_session_table_add(a_uint32_t dev_id, fal_pppoe_session_t * session_tbl); - - - HSL_LOCAL sw_error_t - dess_pppoe_session_table_del(a_uint32_t dev_id, fal_pppoe_session_t * session_tbl); - - - HSL_LOCAL sw_error_t - dess_pppoe_session_table_get(a_uint32_t dev_id, fal_pppoe_session_t * session_tbl); - - - HSL_LOCAL sw_error_t - dess_pppoe_session_id_set(a_uint32_t dev_id, a_uint32_t index, - a_uint32_t id); - - - HSL_LOCAL sw_error_t - dess_pppoe_session_id_get(a_uint32_t dev_id, a_uint32_t index, - a_uint32_t * id); - - - HSL_LOCAL sw_error_t - dess_eapol_status_set(a_uint32_t dev_id, a_uint32_t port_id, a_bool_t enable); - - HSL_LOCAL sw_error_t - dess_eapol_status_get(a_uint32_t dev_id, a_uint32_t port_id, a_bool_t * enable); - - HSL_LOCAL sw_error_t - dess_ripv1_status_set(a_uint32_t dev_id, a_bool_t enable); - - HSL_LOCAL sw_error_t - dess_ripv1_status_get(a_uint32_t dev_id, a_bool_t * enable); - - - HSL_LOCAL sw_error_t - dess_port_arp_req_status_set(a_uint32_t dev_id, fal_port_t port_id, a_bool_t enable); - - - HSL_LOCAL sw_error_t - dess_port_arp_req_status_get(a_uint32_t dev_id, fal_port_t port_id, a_bool_t *enable); - - - HSL_LOCAL sw_error_t - dess_port_arp_ack_status_set(a_uint32_t dev_id, fal_port_t port_id, a_bool_t enable); - - - HSL_LOCAL sw_error_t - dess_port_arp_ack_status_get(a_uint32_t dev_id, fal_port_t port_id, a_bool_t *enable); - - - HSL_LOCAL sw_error_t - dess_intr_mask_set(a_uint32_t dev_id, a_uint32_t intr_mask); - - - HSL_LOCAL sw_error_t - dess_intr_mask_get(a_uint32_t dev_id, a_uint32_t * intr_mask); - - - HSL_LOCAL sw_error_t - dess_intr_status_get(a_uint32_t dev_id, a_uint32_t * intr_status); - - - HSL_LOCAL sw_error_t - dess_intr_status_clear(a_uint32_t dev_id, a_uint32_t intr_status); - - - HSL_LOCAL sw_error_t - dess_intr_port_link_mask_set(a_uint32_t dev_id, a_uint32_t port_id, a_uint32_t intr_mask_flag); - - - HSL_LOCAL sw_error_t - dess_intr_port_link_mask_get(a_uint32_t dev_id, a_uint32_t port_id, a_uint32_t * intr_mask_flag); - - - HSL_LOCAL sw_error_t - dess_intr_port_link_status_get(a_uint32_t dev_id, a_uint32_t port_id, a_uint32_t * intr_mask_flag); - - HSL_LOCAL sw_error_t - dess_intr_mask_mac_linkchg_set(a_uint32_t dev_id, a_uint32_t port_id, a_bool_t enable); - - - HSL_LOCAL sw_error_t - dess_intr_mask_mac_linkchg_get(a_uint32_t dev_id, a_uint32_t port_id, a_bool_t * enable); - - HSL_LOCAL sw_error_t - dess_intr_status_mac_linkchg_get(a_uint32_t dev_id, fal_pbmp_t *port_bitmap); - - HSL_LOCAL sw_error_t - dess_cpu_vid_en_set(a_uint32_t dev_id, a_bool_t enable); - - - HSL_LOCAL sw_error_t - dess_cpu_vid_en_get(a_uint32_t dev_id, a_bool_t * enable); - - HSL_LOCAL sw_error_t - dess_rtd_pppoe_en_set(a_uint32_t dev_id, a_bool_t enable); - - - HSL_LOCAL sw_error_t - dess_rtd_pppoe_en_get(a_uint32_t dev_id, a_bool_t * enable); - - HSL_LOCAL sw_error_t - dess_intr_status_mac_linkchg_clear(a_uint32_t dev_id); - - HSL_LOCAL sw_error_t - dess_global_macaddr_set(a_uint32_t dev_id, fal_mac_addr_t * addr); - - HSL_LOCAL sw_error_t - dess_global_macaddr_get(a_uint32_t dev_id, fal_mac_addr_t * addr); - - HSL_LOCAL sw_error_t - dess_lldp_status_set(a_uint32_t dev_id, a_bool_t enable); - - - HSL_LOCAL sw_error_t - dess_lldp_status_get(a_uint32_t dev_id, a_bool_t * enable); - - HSL_LOCAL sw_error_t - dess_frame_crc_reserve_set(a_uint32_t dev_id, a_bool_t enable); - - - HSL_LOCAL sw_error_t - dess_frame_crc_reserve_get(a_uint32_t dev_id, a_bool_t * enable); - -#endif - -#ifdef __cplusplus -} -#endif /* __cplusplus */ - -#endif - diff --git a/feeds/ipq807x/qca-ssdk/src/include/hsl/dess/dess_nat.h b/feeds/ipq807x/qca-ssdk/src/include/hsl/dess/dess_nat.h deleted file mode 100755 index 57156fca6..000000000 --- a/feeds/ipq807x/qca-ssdk/src/include/hsl/dess/dess_nat.h +++ /dev/null @@ -1,147 +0,0 @@ -/* - * Copyright (c) 2014, The Linux Foundation. All rights reserved. - * Permission to use, copy, modify, and/or distribute this software for - * any purpose with or without fee is hereby granted, provided that the - * above copyright notice and this permission notice appear in all copies. - * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES - * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR - * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES - * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN - * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT - * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. - */ - - -#ifndef _DESS_NAT_H_ -#define _DESS_NAT_H_ - -#ifdef __cplusplus -extern "C" { -#endif /* __cplusplus */ - -#include "fal/fal_nat.h" - - sw_error_t dess_nat_init(a_uint32_t dev_id); - - sw_error_t dess_nat_reset(a_uint32_t dev_id); - -#ifdef IN_NAT -#define DESS_NAT_INIT(rv, dev_id) \ - { \ - rv = dess_nat_init(dev_id); \ - SW_RTN_ON_ERROR(rv); \ - } - -#define DESS_NAT_RESET(rv, dev_id) \ - { \ - rv = dess_nat_reset(dev_id); \ - SW_RTN_ON_ERROR(rv); \ - } -#else -#define DESS_NAT_INIT(rv, dev_id) -#define DESS_NAT_RESET(rv, dev_id) -#endif - -#ifdef HSL_STANDALONG - - HSL_LOCAL sw_error_t - dess_napt_add(a_uint32_t dev_id, fal_napt_entry_t * napt_entry); - - HSL_LOCAL sw_error_t - dess_nat_pub_addr_add(a_uint32_t dev_id, fal_nat_pub_addr_t * entry); - - HSL_LOCAL sw_error_t - dess_napt_next(a_uint32_t dev_id, a_uint32_t next_mode, - fal_napt_entry_t * napt_entry); - - HSL_LOCAL sw_error_t - dess_nat_prv_base_addr_set(a_uint32_t dev_id, fal_ip4_addr_t addr); - - HSL_LOCAL sw_error_t - dess_napt_del(a_uint32_t dev_id, a_uint32_t del_mode, - fal_napt_entry_t * napt_entry); - - HSL_LOCAL sw_error_t - dess_nat_del(a_uint32_t dev_id, a_uint32_t del_mode, - fal_nat_entry_t * nat_entry); - - HSL_LOCAL sw_error_t - dess_nat_pub_addr_del(a_uint32_t dev_id, a_uint32_t del_mode, - fal_nat_pub_addr_t * entry); - - HSL_LOCAL sw_error_t - dess_nat_add(a_uint32_t dev_id, fal_nat_entry_t * nat_entry); - - HSL_LOCAL sw_error_t - dess_nat_get(a_uint32_t dev_id, a_uint32_t get_mode, - fal_nat_entry_t * nat_entry); - - HSL_LOCAL sw_error_t - dess_nat_next(a_uint32_t dev_id, a_uint32_t next_mode, - fal_nat_entry_t * nat_entry); - - HSL_LOCAL sw_error_t - dess_nat_counter_bind(a_uint32_t dev_id, a_uint32_t entry_id, - a_uint32_t cnt_id, a_bool_t enable); - - HSL_LOCAL sw_error_t - dess_napt_get(a_uint32_t dev_id, a_uint32_t get_mode, - fal_napt_entry_t * napt_entry); - - HSL_LOCAL sw_error_t - dess_napt_counter_bind(a_uint32_t dev_id, a_uint32_t entry_id, - a_uint32_t cnt_id, a_bool_t enable); - - HSL_LOCAL sw_error_t - dess_nat_status_set(a_uint32_t dev_id, a_bool_t enable); - - HSL_LOCAL sw_error_t - dess_nat_status_get(a_uint32_t dev_id, a_bool_t * enable); - - HSL_LOCAL sw_error_t - dess_nat_hash_mode_set(a_uint32_t dev_id, a_uint32_t mode); - - HSL_LOCAL sw_error_t - dess_nat_hash_mode_get(a_uint32_t dev_id, a_uint32_t * mode); - - HSL_LOCAL sw_error_t - dess_napt_status_set(a_uint32_t dev_id, a_bool_t enable); - - HSL_LOCAL sw_error_t - dess_napt_status_get(a_uint32_t dev_id, a_bool_t * enable); - - HSL_LOCAL sw_error_t - dess_napt_mode_set(a_uint32_t dev_id, fal_napt_mode_t mode); - - HSL_LOCAL sw_error_t - dess_napt_mode_get(a_uint32_t dev_id, fal_napt_mode_t * mode); - - HSL_LOCAL sw_error_t - dess_nat_prv_base_addr_get(a_uint32_t dev_id, fal_ip4_addr_t * addr); - - HSL_LOCAL sw_error_t - dess_nat_prv_base_mask_set(a_uint32_t dev_id, fal_ip4_addr_t addr); - - HSL_LOCAL sw_error_t - dess_nat_prv_base_mask_get(a_uint32_t dev_id, fal_ip4_addr_t * addr); - - HSL_LOCAL sw_error_t - dess_nat_pub_addr_next(a_uint32_t dev_id, a_uint32_t next_mode, - fal_nat_pub_addr_t * entry); - - HSL_LOCAL sw_error_t - dess_nat_unk_session_cmd_set(a_uint32_t dev_id, fal_fwd_cmd_t cmd); - - HSL_LOCAL sw_error_t - dess_nat_unk_session_cmd_get(a_uint32_t dev_id, fal_fwd_cmd_t * cmd); - - HSL_LOCAL sw_error_t - dess_nat_global_set(a_uint32_t dev_id, a_bool_t enable); - -#endif - -#ifdef __cplusplus -} -#endif /* __cplusplus */ -#endif /* _DESS_NAT_H_ */ diff --git a/feeds/ipq807x/qca-ssdk/src/include/hsl/dess/dess_nat_helper.h b/feeds/ipq807x/qca-ssdk/src/include/hsl/dess/dess_nat_helper.h deleted file mode 100755 index 13c0fb18e..000000000 --- a/feeds/ipq807x/qca-ssdk/src/include/hsl/dess/dess_nat_helper.h +++ /dev/null @@ -1,50 +0,0 @@ -/* - * Copyright (c) 2014, The Linux Foundation. All rights reserved. - * Permission to use, copy, modify, and/or distribute this software for - * any purpose with or without fee is hereby granted, provided that the - * above copyright notice and this permission notice appear in all copies. - * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES - * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR - * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES - * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN - * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT - * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. - */ - - -#ifndef _DESS_NAT_HELPER_H_ -#define _DESS_NAT_HELPER_H_ - -#ifdef __cplusplus -extern "C" { -#endif /* __cplusplus */ - -#include "fal/fal_nat.h" - - sw_error_t nat_helper_init(a_uint32_t dev_id, a_uint32_t portbmp); - - sw_error_t nat_helper_cleanup(a_uint32_t dev_id); - -#ifdef IN_NAT_HELPER -#define DESS_NAT_HELPER_INIT(rv, dev_id, portbmp) \ - { \ - rv = nat_helper_init(dev_id, portbmp); \ - SW_RTN_ON_ERROR(rv); \ - } - -#define DESS_NAT_HELPER_CLEANUP(rv, dev_id) \ - { \ - rv = nat_helper_cleanup(dev_id); \ - SW_RTN_ON_ERROR(rv); \ - } -#else -#define DESS_NAT_HELPER_INIT(rv, dev_id, portbmp) -#define DESS_NAT_HELPER_CLEANUP(rv, dev_id) -#endif - - -#ifdef __cplusplus -} -#endif /* __cplusplus */ -#endif /* _DESS_NAT_HELPER_H_ */ diff --git a/feeds/ipq807x/qca-ssdk/src/include/hsl/dess/dess_port_ctrl.h b/feeds/ipq807x/qca-ssdk/src/include/hsl/dess/dess_port_ctrl.h deleted file mode 100755 index b08b0b59d..000000000 --- a/feeds/ipq807x/qca-ssdk/src/include/hsl/dess/dess_port_ctrl.h +++ /dev/null @@ -1,360 +0,0 @@ -/* - * Copyright (c) 2014-2015, The Linux Foundation. All rights reserved. - * Permission to use, copy, modify, and/or distribute this software for - * any purpose with or without fee is hereby granted, provided that the - * above copyright notice and this permission notice appear in all copies. - * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES - * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR - * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES - * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN - * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT - * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. - */ - - -#ifndef _DESS_PORT_CTRL_H_ -#define _DESS_PORT_CTRL_H_ - -#ifdef __cplusplus -extern "C" -{ -#endif /* __cplusplus */ - -#include "fal/fal_port_ctrl.h" - - sw_error_t dess_port_ctrl_init (a_uint32_t dev_id); - -#ifdef IN_PORTCONTROL -#define DESS_PORT_CTRL_INIT(rv, dev_id) \ - { \ - rv = dess_port_ctrl_init(dev_id); \ - SW_RTN_ON_ERROR(rv); \ - } -#else -#define DESS_PORT_CTRL_INIT(rv, dev_id) -#endif - -#ifdef HSL_STANDALONG - - - HSL_LOCAL sw_error_t - dess_port_duplex_set (a_uint32_t dev_id, fal_port_t port_id, - fal_port_duplex_t duplex); - - - HSL_LOCAL sw_error_t - dess_port_duplex_get (a_uint32_t dev_id, fal_port_t port_id, - fal_port_duplex_t * pduplex); - - - HSL_LOCAL sw_error_t - dess_port_speed_set (a_uint32_t dev_id, fal_port_t port_id, - fal_port_speed_t speed); - - - HSL_LOCAL sw_error_t - dess_port_speed_get (a_uint32_t dev_id, fal_port_t port_id, - fal_port_speed_t * pspeed); - - - HSL_LOCAL sw_error_t - dess_port_autoneg_status_get (a_uint32_t dev_id, fal_port_t port_id, - a_bool_t * status); - - - HSL_LOCAL sw_error_t - dess_port_autoneg_enable (a_uint32_t dev_id, fal_port_t port_id); - - - HSL_LOCAL sw_error_t - dess_port_autoneg_restart (a_uint32_t dev_id, fal_port_t port_id); - - - HSL_LOCAL sw_error_t - dess_port_autoneg_adv_set (a_uint32_t dev_id, fal_port_t port_id, - a_uint32_t autoadv); - - - HSL_LOCAL sw_error_t - dess_port_autoneg_adv_get (a_uint32_t dev_id, fal_port_t port_id, - a_uint32_t * autoadv); - - - HSL_LOCAL sw_error_t - dess_port_flowctrl_set (a_uint32_t dev_id, fal_port_t port_id, - a_bool_t enable); - - - HSL_LOCAL sw_error_t - dess_port_flowctrl_get (a_uint32_t dev_id, fal_port_t port_id, - a_bool_t * enable); - - - HSL_LOCAL sw_error_t - dess_port_flowctrl_forcemode_set (a_uint32_t dev_id, - fal_port_t port_id, a_bool_t enable); - - - HSL_LOCAL sw_error_t - dess_port_flowctrl_forcemode_get (a_uint32_t dev_id, - fal_port_t port_id, a_bool_t * enable); - - - HSL_LOCAL sw_error_t - dess_port_powersave_set (a_uint32_t dev_id, fal_port_t port_id, - a_bool_t enable); - - - HSL_LOCAL sw_error_t - dess_port_powersave_get (a_uint32_t dev_id, fal_port_t port_id, - a_bool_t * enable); - - - HSL_LOCAL sw_error_t - dess_port_hibernate_set (a_uint32_t dev_id, fal_port_t port_id, - a_bool_t enable); - - - HSL_LOCAL sw_error_t - dess_port_hibernate_get (a_uint32_t dev_id, fal_port_t port_id, - a_bool_t * enable); - - - HSL_LOCAL sw_error_t - dess_port_cdt (a_uint32_t dev_id, fal_port_t port_id, a_uint32_t mdi_pair, - fal_cable_status_t * cable_status, a_uint32_t * cable_len); - - - HSL_LOCAL sw_error_t - dess_port_rxhdr_mode_set (a_uint32_t dev_id, fal_port_t port_id, - fal_port_header_mode_t mode); - - - HSL_LOCAL sw_error_t - dess_port_rxhdr_mode_get (a_uint32_t dev_id, fal_port_t port_id, - fal_port_header_mode_t * mode); - - - HSL_LOCAL sw_error_t - dess_port_txhdr_mode_set (a_uint32_t dev_id, fal_port_t port_id, - fal_port_header_mode_t mode); - - - HSL_LOCAL sw_error_t - dess_port_txhdr_mode_get (a_uint32_t dev_id, fal_port_t port_id, - fal_port_header_mode_t * mode); - - - HSL_LOCAL sw_error_t - dess_header_type_set (a_uint32_t dev_id, a_bool_t enable, - a_uint32_t type); - - - HSL_LOCAL sw_error_t - dess_header_type_get (a_uint32_t dev_id, a_bool_t * enable, - a_uint32_t * type); - - - HSL_LOCAL sw_error_t - dess_port_txmac_status_set (a_uint32_t dev_id, fal_port_t port_id, - a_bool_t enable); - - - HSL_LOCAL sw_error_t - dess_port_txmac_status_get (a_uint32_t dev_id, fal_port_t port_id, - a_bool_t * enable); - - - HSL_LOCAL sw_error_t - dess_port_rxmac_status_set (a_uint32_t dev_id, fal_port_t port_id, - a_bool_t enable); - - - HSL_LOCAL sw_error_t - dess_port_rxmac_status_get (a_uint32_t dev_id, fal_port_t port_id, - a_bool_t * enable); - - - HSL_LOCAL sw_error_t - dess_port_txfc_status_set (a_uint32_t dev_id, fal_port_t port_id, - a_bool_t enable); - - - HSL_LOCAL sw_error_t - dess_port_txfc_status_get (a_uint32_t dev_id, fal_port_t port_id, - a_bool_t * enable); - - - HSL_LOCAL sw_error_t - dess_port_rxfc_status_set (a_uint32_t dev_id, fal_port_t port_id, - a_bool_t enable); - - - HSL_LOCAL sw_error_t - dess_port_rxfc_status_get (a_uint32_t dev_id, fal_port_t port_id, - a_bool_t * enable); - - - HSL_LOCAL sw_error_t - dess_port_bp_status_set (a_uint32_t dev_id, fal_port_t port_id, - a_bool_t enable); - - - HSL_LOCAL sw_error_t - dess_port_bp_status_get (a_uint32_t dev_id, fal_port_t port_id, - a_bool_t * enable); - - - HSL_LOCAL sw_error_t - dess_port_link_forcemode_set (a_uint32_t dev_id, fal_port_t port_id, - a_bool_t enable); - - - HSL_LOCAL sw_error_t - dess_port_link_forcemode_get (a_uint32_t dev_id, fal_port_t port_id, - a_bool_t * enable); - - - HSL_LOCAL sw_error_t - dess_port_link_status_get (a_uint32_t dev_id, fal_port_t port_id, - a_bool_t * status); - - HSL_LOCAL sw_error_t - dess_port_mac_loopback_set (a_uint32_t dev_id, fal_port_t port_id, - a_bool_t enable); - - - HSL_LOCAL sw_error_t - dess_port_mac_loopback_get (a_uint32_t dev_id, fal_port_t port_id, - a_bool_t * enable); - - HSL_LOCAL sw_error_t - dess_port_congestion_drop_set (a_uint32_t dev_id, fal_port_t port_id, - a_uint32_t queue_id, a_bool_t enable); - - HSL_LOCAL sw_error_t - dess_port_congestion_drop_get (a_uint32_t dev_id, fal_port_t port_id, - a_uint32_t queue_id, a_bool_t * enable); - - HSL_LOCAL sw_error_t - dess_ring_flow_ctrl_thres_set (a_uint32_t dev_id, a_uint32_t ring_id, - a_uint8_t on_thres, a_uint8_t off_thres); - - HSL_LOCAL sw_error_t - dess_ring_flow_ctrl_thres_get (a_uint32_t dev_id, a_uint32_t ring_id, - a_uint8_t * on_thres, - a_uint8_t * off_thres); - - HSL_LOCAL sw_error_t - dess_port_8023az_set (a_uint32_t dev_id, fal_port_t port_id, - a_bool_t enable); - - HSL_LOCAL sw_error_t - dess_port_8023az_get (a_uint32_t dev_id, fal_port_t port_id, - a_bool_t * enable); - - HSL_LOCAL sw_error_t - dess_port_mdix_set (a_uint32_t dev_id, a_uint32_t phy_id, - fal_port_mdix_mode_t mode); - - HSL_LOCAL sw_error_t - dess_port_mdix_get (a_uint32_t dev_id, fal_port_t port_id, - fal_port_mdix_mode_t * mode); - - HSL_LOCAL sw_error_t - dess_port_mdix_status_get (a_uint32_t dev_id, fal_port_t port_id, - fal_port_mdix_status_t * mode); - - HSL_LOCAL sw_error_t - dess_port_combo_prefer_medium_set (a_uint32_t dev_id, a_uint32_t phy_id, - fal_port_medium_t phy_medium); - - HSL_LOCAL sw_error_t - dess_port_combo_prefer_medium_get (a_uint32_t dev_id, a_uint32_t phy_id, - fal_port_medium_t * phy_medium); - - HSL_LOCAL sw_error_t - dess_port_combo_medium_status_get (a_uint32_t dev_id, a_uint32_t phy_id, - fal_port_medium_t * phy_medium); - - HSL_LOCAL sw_error_t - dess_port_combo_fiber_mode_set (a_uint32_t dev_id, a_uint32_t phy_id, - fal_port_fiber_mode_t fiber_mode); - - HSL_LOCAL sw_error_t - dess_port_combo_fiber_mode_get (a_uint32_t dev_id, a_uint32_t phy_id, - fal_port_fiber_mode_t * fiber_mode); - - HSL_LOCAL sw_error_t - dess_port_local_loopback_set (a_uint32_t dev_id, fal_port_t port_id, - a_bool_t enable); - - HSL_LOCAL sw_error_t - dess_port_local_loopback_get (a_uint32_t dev_id, fal_port_t port_id, - a_bool_t * enable); - - HSL_LOCAL sw_error_t - dess_port_remote_loopback_set (a_uint32_t dev_id, fal_port_t port_id, - a_bool_t enable); - - HSL_LOCAL sw_error_t - dess_port_remote_loopback_get (a_uint32_t dev_id, fal_port_t port_id, - a_bool_t * enable); - - HSL_LOCAL sw_error_t - dess_port_magic_frame_mac_set (a_uint32_t dev_id, fal_port_t port_id, - fal_mac_addr_t * mac); - - HSL_LOCAL sw_error_t - dess_port_magic_frame_mac_get (a_uint32_t dev_id, fal_port_t port_id, - fal_mac_addr_t * mac); - - HSL_LOCAL sw_error_t - dess_port_phy_id_get (a_uint32_t dev_id, fal_port_t port_id, - a_uint16_t * org_id, a_uint16_t * rev_id); - - HSL_LOCAL sw_error_t - dess_port_wol_status_set (a_uint32_t dev_id, fal_port_t port_id, - a_bool_t enable); - - HSL_LOCAL sw_error_t - dess_port_wol_status_get (a_uint32_t dev_id, fal_port_t port_id, - a_bool_t * enable); - - HSL_LOCAL sw_error_t - dess_port_reset (a_uint32_t dev_id, fal_port_t port_id); - - HSL_LOCAL sw_error_t - dess_port_power_off (a_uint32_t dev_id, fal_port_t port_id); - - HSL_LOCAL sw_error_t - dess_port_power_on (a_uint32_t dev_id, fal_port_t port_id); - - HSL_LOCAL sw_error_t - dess_port_interface_mode_set (a_uint32_t dev_id, fal_port_t port_id, - fal_port_interface_mode_t mode); - - HSL_LOCAL sw_error_t - dess_port_interface_mode_get (a_uint32_t dev_id, fal_port_t port_id, - fal_port_interface_mode_t * mode); - - HSL_LOCAL sw_error_t - dess_port_interface_mode_status_get (a_uint32_t dev_id, fal_port_t port_id, - fal_port_interface_mode_t * mode); - HSL_LOCAL sw_error_t - dess_port_counter_set (a_uint32_t dev_id, fal_port_t port_id, - a_bool_t enable); - - HSL_LOCAL sw_error_t - dess_port_counter_get (a_uint32_t dev_id, fal_port_t port_id, - a_bool_t * enable); - HSL_LOCAL sw_error_t - dess_port_counter_show (a_uint32_t dev_id, fal_port_t port_id, - fal_port_counter_info_t * counter_info); -#endif - -#ifdef __cplusplus -} -#endif /* __cplusplus */ -#endif /* _DESS_PORT_CTRL_H_ */ diff --git a/feeds/ipq807x/qca-ssdk/src/include/hsl/dess/dess_portvlan.h b/feeds/ipq807x/qca-ssdk/src/include/hsl/dess/dess_portvlan.h deleted file mode 100755 index e68e12724..000000000 --- a/feeds/ipq807x/qca-ssdk/src/include/hsl/dess/dess_portvlan.h +++ /dev/null @@ -1,228 +0,0 @@ -/* - * Copyright (c) 2014, The Linux Foundation. All rights reserved. - * Permission to use, copy, modify, and/or distribute this software for - * any purpose with or without fee is hereby granted, provided that the - * above copyright notice and this permission notice appear in all copies. - * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES - * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR - * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES - * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN - * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT - * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. - */ - - -#ifndef _DESS_PORTVLAN_H_ -#define _DESS_PORTVLAN_H_ - -#ifdef __cplusplus -extern "C" { -#endif /* __cplusplus */ - -#include "fal/fal_portvlan.h" - - sw_error_t dess_portvlan_init(a_uint32_t dev_id); - -#ifdef IN_PORTVLAN -#define DESS_PORTVLAN_INIT(rv, dev_id) \ - { \ - rv = dess_portvlan_init(dev_id); \ - SW_RTN_ON_ERROR(rv); \ - } -#else -#define DESS_PORTVLAN_INIT(rv, dev_id) -#endif - -#ifdef HSL_STANDALONG - - - HSL_LOCAL sw_error_t - dess_port_1qmode_set(a_uint32_t dev_id, fal_port_t port_id, - fal_pt_1qmode_t port_1qmode); - - - HSL_LOCAL sw_error_t - dess_port_1qmode_get(a_uint32_t dev_id, fal_port_t port_id, - fal_pt_1qmode_t * pport_1qmode); - - - HSL_LOCAL sw_error_t - dess_port_egvlanmode_set(a_uint32_t dev_id, fal_port_t port_id, - fal_pt_1q_egmode_t port_egvlanmode); - - - HSL_LOCAL sw_error_t - dess_port_egvlanmode_get(a_uint32_t dev_id, fal_port_t port_id, - fal_pt_1q_egmode_t * pport_egvlanmode); - - - HSL_LOCAL sw_error_t - dess_portvlan_member_add(a_uint32_t dev_id, fal_port_t port_id, - a_uint32_t mem_port_id); - - - HSL_LOCAL sw_error_t - dess_portvlan_member_del(a_uint32_t dev_id, fal_port_t port_id, - a_uint32_t mem_port_id); - - - HSL_LOCAL sw_error_t - dess_portvlan_member_update(a_uint32_t dev_id, fal_port_t port_id, - fal_pbmp_t mem_port_map); - - - HSL_LOCAL sw_error_t - dess_portvlan_member_get(a_uint32_t dev_id, fal_port_t port_id, - fal_pbmp_t * mem_port_map); - - - HSL_LOCAL sw_error_t - dess_port_force_default_vid_set(a_uint32_t dev_id, fal_port_t port_id, - a_bool_t enable); - - - HSL_LOCAL sw_error_t - dess_port_force_default_vid_get(a_uint32_t dev_id, fal_port_t port_id, a_bool_t * enable); - - - HSL_LOCAL sw_error_t - dess_port_force_portvlan_set(a_uint32_t dev_id, fal_port_t port_id, - a_bool_t enable); - - - HSL_LOCAL sw_error_t - dess_port_force_portvlan_get(a_uint32_t dev_id, fal_port_t port_id, a_bool_t * enable); - - - HSL_LOCAL sw_error_t - dess_nestvlan_tpid_set(a_uint32_t dev_id, a_uint32_t tpid); - - - HSL_LOCAL sw_error_t - dess_nestvlan_tpid_get(a_uint32_t dev_id, a_uint32_t * tpid); - - - HSL_LOCAL sw_error_t - dess_port_invlan_mode_set(a_uint32_t dev_id, fal_port_t port_id, - fal_pt_invlan_mode_t mode); - - - HSL_LOCAL sw_error_t - dess_port_invlan_mode_get(a_uint32_t dev_id, fal_port_t port_id, - fal_pt_invlan_mode_t * mode); - - - HSL_LOCAL sw_error_t - dess_port_tls_set(a_uint32_t dev_id, fal_port_t port_id, - a_bool_t enable); - - - HSL_LOCAL sw_error_t - dess_port_tls_get(a_uint32_t dev_id, fal_port_t port_id, - a_bool_t * enable); - - - HSL_LOCAL sw_error_t - dess_port_pri_propagation_set(a_uint32_t dev_id, fal_port_t port_id, - a_bool_t enable); - - - HSL_LOCAL sw_error_t - dess_port_pri_propagation_get(a_uint32_t dev_id, fal_port_t port_id, - a_bool_t * enable); - - - HSL_LOCAL sw_error_t - dess_port_default_svid_set(a_uint32_t dev_id, fal_port_t port_id, - a_uint32_t vid); - - - HSL_LOCAL sw_error_t - dess_port_default_svid_get(a_uint32_t dev_id, fal_port_t port_id, - a_uint32_t * vid); - - HSL_LOCAL sw_error_t - dess_port_default_cvid_set(a_uint32_t dev_id, fal_port_t port_id, - a_uint32_t vid); - - - HSL_LOCAL sw_error_t - dess_port_default_cvid_get(a_uint32_t dev_id, fal_port_t port_id, - a_uint32_t * vid); - - - HSL_LOCAL sw_error_t - dess_port_vlan_propagation_set(a_uint32_t dev_id, fal_port_t port_id, - fal_vlan_propagation_mode_t mode); - - - HSL_LOCAL sw_error_t - dess_port_vlan_propagation_get(a_uint32_t dev_id, fal_port_t port_id, - fal_vlan_propagation_mode_t * mode); - - - HSL_LOCAL sw_error_t - dess_port_vlan_trans_add(a_uint32_t dev_id, fal_port_t port_id, fal_vlan_trans_entry_t *entry); - - - HSL_LOCAL sw_error_t - dess_port_vlan_trans_del(a_uint32_t dev_id, fal_port_t port_id, fal_vlan_trans_entry_t *entry); - - - HSL_LOCAL sw_error_t - dess_port_vlan_trans_get(a_uint32_t dev_id, fal_port_t port_id, fal_vlan_trans_entry_t *entry); - - - HSL_LOCAL sw_error_t - dess_qinq_mode_set(a_uint32_t dev_id, fal_qinq_mode_t mode); - - - HSL_LOCAL sw_error_t - dess_qinq_mode_get(a_uint32_t dev_id, fal_qinq_mode_t * mode); - - - HSL_LOCAL sw_error_t - dess_port_qinq_role_set(a_uint32_t dev_id, fal_port_t port_id, fal_qinq_port_role_t role); - - - HSL_LOCAL sw_error_t - dess_port_qinq_role_get(a_uint32_t dev_id, fal_port_t port_id, fal_qinq_port_role_t * role); - - - HSL_LOCAL sw_error_t - dess_port_vlan_trans_iterate(a_uint32_t dev_id, fal_port_t port_id, - a_uint32_t * iterator, fal_vlan_trans_entry_t * entry); - - - HSL_LOCAL sw_error_t - dess_port_mac_vlan_xlt_set(a_uint32_t dev_id, fal_port_t port_id, - a_bool_t enable); - - - HSL_LOCAL sw_error_t - dess_port_mac_vlan_xlt_get(a_uint32_t dev_id, fal_port_t port_id, - a_bool_t * enable); - - HSL_LOCAL sw_error_t - dess_netisolate_set(a_uint32_t dev_id, a_bool_t enable); - - HSL_LOCAL sw_error_t - dess_netisolate_get(a_uint32_t dev_id, a_bool_t * enable); - - HSL_LOCAL sw_error_t - dess_eg_trans_filter_bypass_en_set(a_uint32_t dev_id, a_bool_t enable); - - HSL_LOCAL sw_error_t - dess_eg_trans_filter_bypass_en_get(a_uint32_t dev_id, a_bool_t * enable); - - HSL_LOCAL sw_error_t - dess_port_route_defv_set(a_uint32_t dev_id, fal_port_t port_id); - -#endif - -#ifdef __cplusplus -} -#endif /* __cplusplus */ -#endif /* _DESS_PORTVLAN_H */ - diff --git a/feeds/ipq807x/qca-ssdk/src/include/hsl/dess/dess_psgmii.h b/feeds/ipq807x/qca-ssdk/src/include/hsl/dess/dess_psgmii.h deleted file mode 100755 index 7c9b580c3..000000000 --- a/feeds/ipq807x/qca-ssdk/src/include/hsl/dess/dess_psgmii.h +++ /dev/null @@ -1,310 +0,0 @@ -/* - * Copyright (c) 2015, The Linux Foundation. All rights reserved. - * Permission to use, copy, modify, and/or distribute this software for - * any purpose with or without fee is hereby granted, provided that the - * above copyright notice and this permission notice appear in all copies. - * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES - * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR - * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES - * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN - * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT - * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. - */ - - - -#ifndef _DESS_PSGMII_H_ -#define _DESS_PSGMII_H_ - -#ifdef __cplusplus -extern "C" { -#endif /* __cplusplus */ - -/*PSGMII Registers*/ -#define PSGMIIPHY_MODECFG_1 0xcc -#define PSGMIIPHY_PHY_INTERFACE 0x10C -#define PSGMIIPHY_EEE_CH0_1 0x168 -#define PSGMIIPHY_EEE_CH0_2 0x16C -#define PSGMIIPHY_EEE_CH0_3 0x170 -#define PSGMIIPHY_EEE_CH0_4 0x174 -#define PSGMIIPHY_EEE_CH0_5 0x178 -#define PSGMIIPHY_EEE_CH0_6 0x17C -#define PSGMIIPHY_EEE_CH0_7 0x180 -#define PSGMIIPHY_EEE_CH1_1 0x184 -#define PSGMIIPHY_EEE_CH1_2 0x188 -#define PSGMIIPHY_EEE_CH1_3 0x18C -#define PSGMIIPHY_EEE_CH2_1 0x190 -#define PSGMIIPHY_EEE_CH2_2 0x194 -#define PSGMIIPHY_EEE_CH2_3 0x198 -#define PSGMIIPHY_EEE_CH3_1 0x19C -#define PSGMIIPHY_EEE_CH3_2 0x1A0 -#define PSGMIIPHY_EEE_CH3_3 0x1A4 -#define PSGMIIPHY_EEE_CH4_1 0x1A8 -#define PSGMIIPHY_EEE_CH4_2 0x1AC -#define PSGMIIPHY_EEE_CH4_3 0x1B0 - -#define PSGMIIPHY_MODE_CONTROL 0x1b4 -#define PSGMIIPHY_FIFO 0x1b8 - -#define PSGMIIPHY_CHANNEL_0_INPUT_OUTPUT_1 0x1BC -#define PSGMIIPHY_CHANNEL_0_INPUT_OUTPUT_4 0x1C8 -#define PSGMIIPHY_CHANNEL_0_INPUT_OUTPUT_5 0x1CC -#define PSGMIIPHY_CHANNEL_1_INPUT_OUTPUT_4 0x1e0 -#define PSGMIIPHY_CHANNEL_1_INPUT_OUTPUT_5 0x1e4 -#define PSGMIIPHY_CHANNEL_2_INPUT_OUTPUT_4 0x1f8 -#define PSGMIIPHY_CHANNEL_2_INPUT_OUTPUT_5 0x1fC -#define PSGMIIPHY_CHANNEL_3_INPUT_OUTPUT_4 0x210 -#define PSGMIIPHY_CHANNEL_3_INPUT_OUTPUT_5 0x214 -#define PSGMIIPHY_CHANNEL_4_INPUT_OUTPUT_4 0x228 -#define PSGMIIPHY_CHANNEL_4_INPUT_OUTPUT_5 0x22C - -#define PSGMIIPHY_CHANNEL0TXSTATE 0x248 -#define PSGMIIPHY_CHANNEL0RXSTATES 0x24c -#define PSGMIIPHY_CHANNEL1TXSTATE 0x250 -#define PSGMIIPHY_CHANNEL1RXSTATES 0x254 -#define PSGMIIPHY_CHANNEL2TXSTATE 0x258 -#define PSGMIIPHY_CHANNEL2RXSTATES 0x25c -#define PSGMIIPHY_CHANNEL3TXSTATE 0x260 -#define PSGMIIPHY_CHANNEL3RXSTATES 0x264 -#define PSGMIIPHY_CHANNEL4TXSTATE 0x268 -#define PSGMIIPHY_CHANNEL4RXSTATES 0x26c - -/* PSGMII Registers Field*/ - -/*PSGMIIPHY_EEE_CH0_1 register field*/ -#define PSGMIIPHY_EEE_DIS_LPI 0x2 -#define PSGMIIPHY_EEE_EN_LPI 0x1 - -/*PSGMIIPHY_MODE_CONTROL register field*/ -#define PSGMIIPHY_MODE_SW_V17_V18 0x8000 -/* Interface Mode, bits 12:14 */ -#define PSGMIIPHY_MODE_CH0_MODE_1000BASEX 0x0000 -#define PSGMIIPHY_MODE_CH0_MODE_PSGMII_PHY 0x1000 -#define PSGMIIPHY_MODE_CH0_MODE_PSGMII_MAC 0x2000 -#define PSGMIIPHY_MODE_CH0_PSGMII_QSGMII 0x200 -#define PSGMIIPHY_MODE_CH0_QSGMII_SGMII 0x100 -#define PSGMIIPHY_MODE_SGMII_EVEN_LOW 0x0008 -#define PSGMIIPHY_MODE_CH4_CH1_0_SGMII 0x0004 -#define PSGMIIPHY_MODE_CH1_CH0_SGMII 0x0002 -#define PSGMIIPHY_MODE_CH0_ATHR_CSCO_MODE_25M 0x0001 - -/*CHANNEL_0_INPUT_OUTPUT_1 register field*/ -#define PSGMIIPHY_CHANNEL_0_INPUT_OUTPUT_1_MR_AN_COMPLETE 0x800 - -/*CHANNEL_0_INPUT_OUTPUT_4 register field*/ -#define PSGMIIPHY_CHANNEL_0_INPUT_OUTPUT_4_POWER_ON_25M 0x400 -#define PSGMIIPHY_CHANNEL_0_INPUT_OUTPUT_4_MR_MAIN_RESET_25M 0x200 -#define PSGMIIPHY_CHANNEL_0_INPUT_OUTPUT_4_MR_MR_LOOPBACK_25M 0x100 -#define PSGMIIPHY_CHANNEL_0_INPUT_OUTPUT_4_MR_RESTART_AN_25M 0x80 -#define PSGMIIPHY_CHANNEL_0_INPUT_OUTPUT_4_MR_AN_ENABLE_25M 0x40 -#define PSGMIIPHY_CHANNEL_0_INPUT_OUTPUT_4_MR_MR_REG4_CH_25M 0x20 -#define PSGMIIPHY_CHANNEL_0_INPUT_OUTPUT_4_MR_MR_NP_LOADED_25M 0x10 -#define PSGMIIPHY_CHANNEL_0_INPUT_OUTPUT_4_FORCE_SPEED_25M 0x08 -#define PSGMIIPHY_CHANNEL_0_INPUT_OUTPUT_4_SPEED_25M_10M 0x02 -#define PSGMIIPHY_CHANNEL_0_INPUT_OUTPUT_4_SPEED_25M_100M 0x04 -#define PSGMIIPHY_CHANNEL_0_INPUT_OUTPUT_4_SPEED_25M_1000M 0x06 -#define PSGMIIPHY_CHANNEL_0_INPUT_OUTPUT_4_REM_PHY_LPBK 0x00 - -/*CHANNEL_0_INPUT_OUTPUT_5 register field*/ -#define PSGMIIPHY_CHANNEL_0_INPUT_OUTPUT_5_FULL_DUPLEX_25M 0x800 -#define PSGMIIPHY_CHANNEL_0_INPUT_OUTPUT_5_HALF_DUPLEX_25M 0x400 -#define PSGMIIPHY_CHANNEL_0_INPUT_OUTPUT_5_REMOTE_FAULT_25M 0x300 -#define PSGMIIPHY_CHANNEL_0_INPUT_OUTPUT_5_LINK_25M 0x80 -#define PSGMIIPHY_CHANNEL_0_INPUT_OUTPUT_5_DUPLEX_MODE_25M 0x40 -#define PSGMIIPHY_CHANNEL_0_INPUT_OUTPUT_5_SPEED_MODE_25M 0x30 -#define PSGMIIPHY_CHANNEL_0_INPUT_OUTPUT_5_PAUSE_SG_TX_EN_25M 0x08 -#define PSGMIIPHY_CHANNEL_0_INPUT_OUTPUT_5_NEXT_PAGE_25M 0x04 -#define PSGMIIPHY_CHANNEL_0_INPUT_OUTPUT_5_PAUSE_25M 0x02 -#define PSGMIIPHY_CHANNEL_0_INPUT_OUTPUT_5_ASYM_PAUSE_25M 0x01 - -/*CHANNEL_1_INPUT_OUTPUT_4 register field*/ -#define PSGMIIPHY_CHANNEL_1_INPUT_OUTPUT_4_POWER_ON_25M 0x400 -#define PSGMIIPHY_CHANNEL_1_INPUT_OUTPUT_4_MR_MAIN_RESET_25M 0x200 -#define PSGMIIPHY_CHANNEL_1_INPUT_OUTPUT_4_MR_MR_LOOPBACK_25M 0x100 -#define PSGMIIPHY_CHANNEL_1_INPUT_OUTPUT_4_MR_RESTART_AN_25M 0x80 -#define PSGMIIPHY_CHANNEL_1_INPUT_OUTPUT_4_MR_AN_ENABLE_25M 0x40 -#define PSGMIIPHY_CHANNEL_1_INPUT_OUTPUT_4_MR_MR_REG4_CH_25M 0x20 -#define PSGMIIPHY_CHANNEL_1_INPUT_OUTPUT_4_MR_MR_NP_LOADED_25M 0x10 -#define PSGMIIPHY_CHANNEL_1_INPUT_OUTPUT_4_FORCE_SPEED_25M 0x08 -#define PSGMIIPHY_CHANNEL_1_INPUT_OUTPUT_4_SPEED_25M_10M 0x02 -#define PSGMIIPHY_CHANNEL_1_INPUT_OUTPUT_4_SPEED_25M_100M 0x04 -#define PSGMIIPHY_CHANNEL_1_INPUT_OUTPUT_4_SPEED_25M_1000M 0x06 -#define PSGMIIPHY_CHANNEL_1_INPUT_OUTPUT_4_REM_PHY_LPBK 0x00 - -/*CHANNEL_1_INPUT_OUTPUT_5 register field*/ -#define PSGMIIPHY_CHANNEL_1_INPUT_OUTPUT_5_FULL_DUPLEX_25M 0x800 -#define PSGMIIPHY_CHANNEL_1_INPUT_OUTPUT_5_HALF_DUPLEX_25M 0x400 -#define PSGMIIPHY_CHANNEL_1_INPUT_OUTPUT_5_REMOTE_FAULT_25M 0x300 -#define PSGMIIPHY_CHANNEL_1_INPUT_OUTPUT_5_LINK_25M 0x80 -#define PSGMIIPHY_CHANNEL_1_INPUT_OUTPUT_5_DUPLEX_MODE_25M 0x40 -#define PSGMIIPHY_CHANNEL_1_INPUT_OUTPUT_5_SPEED_MODE_25M 0x30 -#define PSGMIIPHY_CHANNEL_1_INPUT_OUTPUT_5_PAUSE_SG_TX_EN_25M 0x08 -#define PSGMIIPHY_CHANNEL_1_INPUT_OUTPUT_5_NEXT_PAGE_25M 0x04 -#define PSGMIIPHY_CHANNEL_1_INPUT_OUTPUT_5_PAUSE_25M 0x02 -#define PSGMIIPHY_CHANNEL_1_INPUT_OUTPUT_5_ASYM_PAUSE_25M 0x01 - -/*CHANNEL_2_INPUT_OUTPUT_4 register field*/ -#define PSGMIIPHY_CHANNEL_2_INPUT_OUTPUT_4_POWER_ON_25M 0x400 -#define PSGMIIPHY_CHANNEL_2_INPUT_OUTPUT_4_MR_MAIN_RESET_25M 0x200 -#define PSGMIIPHY_CHANNEL_2_INPUT_OUTPUT_4_MR_MR_LOOPBACK_25M 0x100 -#define PSGMIIPHY_CHANNEL_2_INPUT_OUTPUT_4_MR_RESTART_AN_25M 0x80 -#define PSGMIIPHY_CHANNEL_2_INPUT_OUTPUT_4_MR_AN_ENABLE_25M 0x40 -#define PSGMIIPHY_CHANNEL_2_INPUT_OUTPUT_4_MR_MR_REG4_CH_25M 0x20 -#define PSGMIIPHY_CHANNEL_2_INPUT_OUTPUT_4_MR_MR_NP_LOADED_25M 0x10 -#define PSGMIIPHY_CHANNEL_2_INPUT_OUTPUT_4_FORCE_SPEED_25M 0x08 -#define PSGMIIPHY_CHANNEL_2_INPUT_OUTPUT_4_SPEED_25M_10M 0x02 -#define PSGMIIPHY_CHANNEL_2_INPUT_OUTPUT_4_SPEED_25M_100M 0x04 -#define PSGMIIPHY_CHANNEL_2_INPUT_OUTPUT_4_SPEED_25M_1000M 0x06 -#define PSGMIIPHY_CHANNEL_2_INPUT_OUTPUT_4_REM_PHY_LPBK 0x00 - -/*CHANNEL_2_INPUT_OUTPUT_5 register field*/ -#define PSGMIIPHY_CHANNEL_2_INPUT_OUTPUT_5_FULL_DUPLEX_25M 0x800 -#define PSGMIIPHY_CHANNEL_2_INPUT_OUTPUT_5_HALF_DUPLEX_25M 0x400 -#define PSGMIIPHY_CHANNEL_2_INPUT_OUTPUT_5_REMOTE_FAULT_25M 0x300 -#define PSGMIIPHY_CHANNEL_2_INPUT_OUTPUT_5_LINK_25M 0x80 -#define PSGMIIPHY_CHANNEL_2_INPUT_OUTPUT_5_DUPLEX_MODE_25M 0x40 -#define PSGMIIPHY_CHANNEL_2_INPUT_OUTPUT_5_SPEED_MODE_25M 0x30 -#define PSGMIIPHY_CHANNEL_2_INPUT_OUTPUT_5_PAUSE_SG_TX_EN_25M 0x08 -#define PSGMIIPHY_CHANNEL_2_INPUT_OUTPUT_5_NEXT_PAGE_25M 0x04 -#define PSGMIIPHY_CHANNEL_2_INPUT_OUTPUT_5_PAUSE_25M 0x02 -#define PSGMIIPHY_CHANNEL_2_INPUT_OUTPUT_5_ASYM_PAUSE_25M 0x01 - -/*CHANNEL_3_INPUT_OUTPUT_4 register field*/ -#define PSGMIIPHY_CHANNEL_3_INPUT_OUTPUT_4_POWER_ON_25M 0x400 -#define PSGMIIPHY_CHANNEL_3_INPUT_OUTPUT_4_MR_MAIN_RESET_25M 0x200 -#define PSGMIIPHY_CHANNEL_3_INPUT_OUTPUT_4_MR_MR_LOOPBACK_25M 0x100 -#define PSGMIIPHY_CHANNEL_3_INPUT_OUTPUT_4_MR_RESTART_AN_25M 0x80 -#define PSGMIIPHY_CHANNEL_3_INPUT_OUTPUT_4_MR_AN_ENABLE_25M 0x40 -#define PSGMIIPHY_CHANNEL_3_INPUT_OUTPUT_4_MR_MR_REG4_CH_25M 0x20 -#define PSGMIIPHY_CHANNEL_3_INPUT_OUTPUT_4_MR_MR_NP_LOADED_25M 0x10 -#define PSGMIIPHY_CHANNEL_3_INPUT_OUTPUT_4_FORCE_SPEED_25M 0x08 - -#define PSGMIIPHY_CHANNEL_3_INPUT_OUTPUT_4_SPEED_25M_MASK 0x06 -#define PSGMIIPHY_CHANNEL_3_INPUT_OUTPUT_4_SPEED_25M_10M 0x0 -#define PSGMIIPHY_CHANNEL_3_INPUT_OUTPUT_4_SPEED_25M_100M 0x02 -#define PSGMIIPHY_CHANNEL_3_INPUT_OUTPUT_4_SPEED_25M_1000M 0x04 -#define PSGMIIPHY_CHANNEL_3_INPUT_OUTPUT_4_REM_PHY_LPBK 0x00 - -/*CHANNEL_3_INPUT_OUTPUT_5 register field*/ -#define PSGMIIPHY_CHANNEL_3_INPUT_OUTPUT_5_FULL_DUPLEX_25M 0x800 -#define PSGMIIPHY_CHANNEL_3_INPUT_OUTPUT_5_HALF_DUPLEX_25M 0x400 -#define PSGMIIPHY_CHANNEL_3_INPUT_OUTPUT_5_REMOTE_FAULT_25M 0x300 -#define PSGMIIPHY_CHANNEL_3_INPUT_OUTPUT_5_LINK_25M 0x80 -#define PSGMIIPHY_CHANNEL_3_INPUT_OUTPUT_5_DUPLEX_MODE_25M 0x40 -#define PSGMIIPHY_CHANNEL_3_INPUT_OUTPUT_5_SPEED_MODE_25M 0x30 -#define PSGMIIPHY_CHANNEL_3_INPUT_OUTPUT_5_SPEED_25M_10M 0x00 -#define PSGMIIPHY_CHANNEL_3_INPUT_OUTPUT_5_SPEED_25M_100M 0x10 -#define PSGMIIPHY_CHANNEL_3_INPUT_OUTPUT_5_SPEED_25M_1000M 0x20 -#define PSGMIIPHY_CHANNEL_3_INPUT_OUTPUT_5_PAUSE_SG_TX_EN_25M 0x08 -#define PSGMIIPHY_CHANNEL_3_INPUT_OUTPUT_5_NEXT_PAGE_25M 0x04 -#define PSGMIIPHY_CHANNEL_3_INPUT_OUTPUT_5_PAUSE_25M 0x02 -#define PSGMIIPHY_CHANNEL_3_INPUT_OUTPUT_5_ASYM_PAUSE_25M 0x01 - -/*CHANNEL_4_INPUT_OUTPUT_4 register field*/ -#define PSGMIIPHY_CHANNEL_4_INPUT_OUTPUT_4_POWER_ON_25M 0x400 -#define PSGMIIPHY_CHANNEL_4_INPUT_OUTPUT_4_MR_MAIN_RESET_25M 0x200 -#define PSGMIIPHY_CHANNEL_4_INPUT_OUTPUT_4_MR_MR_LOOPBACK_25M 0x100 -#define PSGMIIPHY_CHANNEL_4_INPUT_OUTPUT_4_MR_RESTART_AN_25M 0x80 -#define PSGMIIPHY_CHANNEL_4_INPUT_OUTPUT_4_MR_AN_ENABLE_25M 0x40 -#define PSGMIIPHY_CHANNEL_4_INPUT_OUTPUT_4_MR_MR_REG4_CH_25M 0x20 -#define PSGMIIPHY_CHANNEL_4_INPUT_OUTPUT_4_MR_MR_NP_LOADED_25M 0x10 -#define PSGMIIPHY_CHANNEL_4_INPUT_OUTPUT_4_FORCE_SPEED_25M 0x08 -#define PSGMIIPHY_CHANNEL_4_INPUT_OUTPUT_4_SPEED_25M_10M 0x02 -#define PSGMIIPHY_CHANNEL_4_INPUT_OUTPUT_4_SPEED_25M_100M 0x04 -#define PSGMIIPHY_CHANNEL_4_INPUT_OUTPUT_4_SPEED_25M_1000M 0x06 -#define PSGMIIPHY_CHANNEL_4_INPUT_OUTPUT_4_REM_PHY_LPBK 0x00 - -/*CHANNEL_4_INPUT_OUTPUT_5 register field*/ -#define PSGMIIPHY_CHANNEL_4_INPUT_OUTPUT_5_FULL_DUPLEX_25M 0x800 -#define PSGMIIPHY_CHANNEL_4_INPUT_OUTPUT_5_HALF_DUPLEX_25M 0x400 -#define PSGMIIPHY_CHANNEL_4_INPUT_OUTPUT_5_REMOTE_FAULT_25M 0x300 -#define PSGMIIPHY_CHANNEL_4_INPUT_OUTPUT_5_LINK_25M 0x80 -#define PSGMIIPHY_CHANNEL_4_INPUT_OUTPUT_5_DUPLEX_MODE_25M 0x40 -#define PSGMIIPHY_CHANNEL_4_INPUT_OUTPUT_5_SPEED_MODE_25M 0x30 -#define PSGMIIPHY_CHANNEL_4_INPUT_OUTPUT_5_PAUSE_SG_TX_EN_25M 0x08 -#define PSGMIIPHY_CHANNEL_4_INPUT_OUTPUT_5_NEXT_PAGE_25M 0x04 -#define PSGMIIPHY_CHANNEL_4_INPUT_OUTPUT_5_PAUSE_25M 0x02 -#define PSGMIIPHY_CHANNEL_4_INPUT_OUTPUT_5_ASYM_PAUSE_25M 0x01 - -typedef enum { - PSGMII_MAC_MODE_PSGMII = 0, - PSGMII_MAC_MODE_QSGMII, - PSGMII_MAC_MODE_SGMII, - PSGMII_MAC_MODE_DEFAULT -}psgmii_interface_mac_mode_t; - - sw_error_t - dess_psgmii_reg_get(a_uint32_t dev_id, a_uint32_t reg_addr, a_uint8_t value[], - a_uint32_t value_len); - - sw_error_t - dess_psgmii_reg_set(a_uint32_t dev_id, a_uint32_t reg_addr, a_uint8_t value[], - a_uint32_t value_len); - - sw_error_t - dess_psgmii_set_lpi(a_uint32_t dev_id, a_uint32_t phy_id, a_bool_t enable); - - sw_error_t - dess_psgmii_get_lpi(a_uint32_t dev_id, a_uint32_t phy_id, a_bool_t *enable); - - sw_error_t - dess_psgmii_set_interface_type(a_uint32_t dev_id, a_uint32_t phy_id, - psgmii_interface_mac_mode_t mode); - - sw_error_t - dess_psgmii_get_interface_type(a_uint32_t dev_id, a_uint32_t * phy_id, - psgmii_interface_mac_mode_t * mode); - - a_bool_t - dess_psgmii_autoneg_done(a_uint32_t dev_id, a_uint32_t phy_id); - - sw_error_t - dess_psgmii_reset(a_uint32_t dev_id, a_uint32_t phy_id); - - sw_error_t - dess_psgmii_poweroff(a_uint32_t dev_id, a_uint32_t phy_id); - - sw_error_t - dess_psgmii_poweron(a_uint32_t dev_id, a_uint32_t phy_id); - - a_bool_t - dess_psgmii_get_link_status(a_uint32_t dev_id, a_uint32_t phy_id); - - sw_error_t - dess_psgmii_set_loopback(a_uint32_t dev_id, a_uint32_t phy_id, - a_bool_t enable); - - sw_error_t - dess_psgmii_get_loopback(a_uint32_t dev_id, a_uint32_t phy_id, - a_bool_t * enable); - - a_bool_t dess_psgmii_autoneg_status(a_uint32_t dev_id, a_uint32_t phy_id); - - sw_error_t - dess_psgmii_restart_autoneg(a_uint32_t dev_id, a_uint32_t phy_id); - - sw_error_t - dess_psgmii_enable_autoneg(a_uint32_t dev_id, a_uint32_t phy_id); - - sw_error_t - dess_psgmii_set_duplex(a_uint32_t dev_id, a_uint32_t phy_id, - fal_port_duplex_t duplex); - - sw_error_t - dess_psgmii_get_duplex(a_uint32_t dev_id, a_uint32_t phy_id, - fal_port_duplex_t * duplex); - - sw_error_t - dess_psgmii_set_speed(a_uint32_t dev_id, a_uint32_t phy_id, - fal_port_speed_t speed); - - sw_error_t - dess_psgmii_get_speed(a_uint32_t dev_id, a_uint32_t phy_id, - fal_port_speed_t * speed); - - -#ifdef __cplusplus -} -#endif /* __cplusplus */ -#endif /* _DESS_PSGMII_H_ */ diff --git a/feeds/ipq807x/qca-ssdk/src/include/hsl/dess/dess_qos.h b/feeds/ipq807x/qca-ssdk/src/include/hsl/dess/dess_qos.h deleted file mode 100755 index 083e3a874..000000000 --- a/feeds/ipq807x/qca-ssdk/src/include/hsl/dess/dess_qos.h +++ /dev/null @@ -1,180 +0,0 @@ -/* - * Copyright (c) 2014, The Linux Foundation. All rights reserved. - * Permission to use, copy, modify, and/or distribute this software for - * any purpose with or without fee is hereby granted, provided that the - * above copyright notice and this permission notice appear in all copies. - * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES - * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR - * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES - * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN - * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT - * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. - */ - - -#ifndef _DESS_QOS_H_ -#define _DESS_QOS_H_ - -#ifdef __cplusplus -extern "C" { -#endif /* __cplusplus */ - -#include "fal/fal_qos.h" - - sw_error_t dess_qos_init(a_uint32_t dev_id); - -#ifdef IN_QOS -#define DESS_QOS_INIT(rv, dev_id) \ - { \ - rv = dess_qos_init(dev_id); \ - SW_RTN_ON_ERROR(rv); \ - } -#else -#define DESS_QOS_INIT(rv, dev_id) -#endif - -#ifdef HSL_STANDALONG - - - HSL_LOCAL sw_error_t - dess_qos_queue_tx_buf_status_set(a_uint32_t dev_id, - fal_port_t port_id, a_bool_t enable); - - - HSL_LOCAL sw_error_t - dess_qos_queue_tx_buf_status_get(a_uint32_t dev_id, - fal_port_t port_id, - a_bool_t * enable); - - HSL_LOCAL sw_error_t - dess_qos_port_tx_buf_status_set(a_uint32_t dev_id, fal_port_t port_id, - a_bool_t enable); - - - HSL_LOCAL sw_error_t - dess_qos_port_tx_buf_status_get(a_uint32_t dev_id, fal_port_t port_id, - a_bool_t * enable); - - HSL_LOCAL sw_error_t - dess_qos_port_red_en_set(a_uint32_t dev_id, fal_port_t port_id, - a_bool_t enable); - - HSL_LOCAL sw_error_t - dess_qos_port_red_en_get(a_uint32_t dev_id, fal_port_t port_id, - a_bool_t* enable); - - - HSL_LOCAL sw_error_t - dess_qos_queue_tx_buf_nr_set(a_uint32_t dev_id, fal_port_t port_id, - fal_queue_t queue_id, - a_uint32_t * number); - - - HSL_LOCAL sw_error_t - dess_qos_queue_tx_buf_nr_get(a_uint32_t dev_id, fal_port_t port_id, - fal_queue_t queue_id, - a_uint32_t * number); - - - HSL_LOCAL sw_error_t - dess_qos_port_tx_buf_nr_set(a_uint32_t dev_id, fal_port_t port_id, - a_uint32_t * number); - - - HSL_LOCAL sw_error_t - dess_qos_port_tx_buf_nr_get(a_uint32_t dev_id, fal_port_t port_id, - a_uint32_t * number); - - - HSL_LOCAL sw_error_t - dess_qos_port_rx_buf_nr_set(a_uint32_t dev_id, fal_port_t port_id, - a_uint32_t * number); - - - HSL_LOCAL sw_error_t - dess_qos_port_rx_buf_nr_get(a_uint32_t dev_id, fal_port_t port_id, - a_uint32_t * number); - - - HSL_LOCAL sw_error_t - dess_qos_port_mode_set(a_uint32_t dev_id, fal_port_t port_id, - fal_qos_mode_t mode, a_bool_t enable); - - - HSL_LOCAL sw_error_t - dess_qos_port_mode_get(a_uint32_t dev_id, fal_port_t port_id, - fal_qos_mode_t mode, a_bool_t * enable); - - - HSL_LOCAL sw_error_t - dess_qos_port_mode_pri_set(a_uint32_t dev_id, fal_port_t port_id, - fal_qos_mode_t mode, a_uint32_t pri); - - - HSL_LOCAL sw_error_t - dess_qos_port_mode_pri_get(a_uint32_t dev_id, fal_port_t port_id, - fal_qos_mode_t mode, a_uint32_t * pri); - - - HSL_LOCAL sw_error_t - dess_qos_port_sch_mode_set(a_uint32_t dev_id, a_uint32_t port_id, - fal_sch_mode_t mode, const a_uint32_t weight[]); - - - HSL_LOCAL sw_error_t - dess_qos_port_sch_mode_get(a_uint32_t dev_id, a_uint32_t port_id, - fal_sch_mode_t * mode, a_uint32_t weight[]); - - HSL_LOCAL sw_error_t - dess_qos_port_default_spri_set(a_uint32_t dev_id, fal_port_t port_id, - a_uint32_t spri); - - - HSL_LOCAL sw_error_t - dess_qos_port_default_spri_get(a_uint32_t dev_id, fal_port_t port_id, - a_uint32_t * spri); - - - HSL_LOCAL sw_error_t - dess_qos_port_default_cpri_set(a_uint32_t dev_id, fal_port_t port_id, - a_uint32_t cpri); - - - HSL_LOCAL sw_error_t - dess_qos_port_default_cpri_get(a_uint32_t dev_id, fal_port_t port_id, - a_uint32_t * cpri); - - sw_error_t - dess_qos_port_force_spri_status_set(a_uint32_t dev_id, fal_port_t port_id, - a_bool_t enable); - - sw_error_t - dess_qos_port_force_spri_status_get(a_uint32_t dev_id, fal_port_t port_id, - a_bool_t* enable); - - sw_error_t - dess_qos_port_force_cpri_status_set(a_uint32_t dev_id, fal_port_t port_id, - a_bool_t enable); - - sw_error_t - dess_qos_port_force_cpri_status_get(a_uint32_t dev_id, fal_port_t port_id, - a_bool_t* enable); - - HSL_LOCAL sw_error_t - dess_qos_queue_remark_table_set(a_uint32_t dev_id, fal_port_t port_id, - fal_queue_t queue_id, a_uint32_t tbl_id, a_bool_t enable); - - - HSL_LOCAL sw_error_t - dess_qos_queue_remark_table_get(a_uint32_t dev_id, fal_port_t port_id, - fal_queue_t queue_id, a_uint32_t * tbl_id, a_bool_t * enable); - - -#endif - -#ifdef __cplusplus -} -#endif /* __cplusplus */ -#endif /* _DESS_QOS_H_ */ - diff --git a/feeds/ipq807x/qca-ssdk/src/include/hsl/dess/dess_rate.h b/feeds/ipq807x/qca-ssdk/src/include/hsl/dess/dess_rate.h deleted file mode 100755 index d5316f989..000000000 --- a/feeds/ipq807x/qca-ssdk/src/include/hsl/dess/dess_rate.h +++ /dev/null @@ -1,96 +0,0 @@ -/* - * Copyright (c) 2014, The Linux Foundation. All rights reserved. - * Permission to use, copy, modify, and/or distribute this software for - * any purpose with or without fee is hereby granted, provided that the - * above copyright notice and this permission notice appear in all copies. - * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES - * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR - * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES - * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN - * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT - * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. - */ - - -#ifndef _DESS_RATE_H_ -#define _DESS_RATE_H_ - -#ifdef __cplusplus -extern "C" { -#endif /* __cplusplus */ - -#include "fal/fal_rate.h" - - sw_error_t dess_rate_init(a_uint32_t dev_id); - -#ifdef IN_RATE -#define DESS_RATE_INIT(rv, dev_id) \ - { \ - rv = dess_rate_init(dev_id); \ - SW_RTN_ON_ERROR(rv); \ - } -#else -#define DESS_RATE_INIT(rv, dev_id) -#endif - -#ifdef HSL_STANDALONG - - HSL_LOCAL sw_error_t - dess_rate_port_policer_set(a_uint32_t dev_id, fal_port_t port_id, - fal_port_policer_t * policer); - - HSL_LOCAL sw_error_t - dess_rate_port_policer_get(a_uint32_t dev_id, fal_port_t port_id, - fal_port_policer_t * policer); - - HSL_LOCAL sw_error_t - dess_rate_port_shaper_set(a_uint32_t dev_id, fal_port_t port_id, - a_bool_t enable, - fal_egress_shaper_t * shaper); - - HSL_LOCAL sw_error_t - dess_rate_port_shaper_get(a_uint32_t dev_id, fal_port_t port_id, - a_bool_t * enable, - fal_egress_shaper_t * shaper); - - HSL_LOCAL sw_error_t - dess_rate_queue_shaper_set(a_uint32_t dev_id, fal_port_t port_id, - fal_queue_t queue_id, a_bool_t enable, - fal_egress_shaper_t * shaper); - - HSL_LOCAL sw_error_t - dess_rate_queue_shaper_get(a_uint32_t dev_id, fal_port_t port_id, - fal_queue_t queue_id, a_bool_t * enable, - fal_egress_shaper_t * shaper); - - HSL_LOCAL sw_error_t - dess_rate_acl_policer_set(a_uint32_t dev_id, a_uint32_t policer_id, - fal_acl_policer_t * policer); - - HSL_LOCAL sw_error_t - dess_rate_acl_policer_get(a_uint32_t dev_id, a_uint32_t policer_id, - fal_acl_policer_t * policer); - - HSL_LOCAL sw_error_t - dess_rate_port_add_rate_byte_set(a_uint32_t dev_id, fal_port_t port_id, - a_uint32_t number); - - HSL_LOCAL sw_error_t - dess_rate_port_add_rate_byte_get(a_uint32_t dev_id, fal_port_t port_id, - a_uint32_t *number); - - HSL_LOCAL sw_error_t - dess_rate_port_gol_flow_en_set(a_uint32_t dev_id, fal_port_t port_id, - a_bool_t enable); - - HSL_LOCAL sw_error_t - dess_rate_port_gol_flow_en_get(a_uint32_t dev_id, fal_port_t port_id, - a_bool_t* enable); -#endif - -#ifdef __cplusplus -} -#endif /* __cplusplus */ -#endif /* _DESS_RATE_H_ */ - diff --git a/feeds/ipq807x/qca-ssdk/src/include/hsl/dess/dess_reg.h b/feeds/ipq807x/qca-ssdk/src/include/hsl/dess/dess_reg.h deleted file mode 100755 index 89b67d144..000000000 --- a/feeds/ipq807x/qca-ssdk/src/include/hsl/dess/dess_reg.h +++ /dev/null @@ -1,5011 +0,0 @@ -/* - * Copyright (c) 2014, The Linux Foundation. All rights reserved. - * Permission to use, copy, modify, and/or distribute this software for - * any purpose with or without fee is hereby granted, provided that the - * above copyright notice and this permission notice appear in all copies. - * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES - * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR - * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES - * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN - * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT - * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. - */ - - - -#ifndef _DESS_REG_H_ -#define _DESS_REG_H_ - -#ifdef __cplusplus -extern "C" { -#endif /* __cplusplus */ - -#define DESS_DEVICE_ID 0x14 /* TBD */ - -#define MAX_ENTRY_LEN 128 - -#define HSL_RW 1 -#define HSL_RO 0 - - - /* DESS Mask Control Register */ -#define MASK_CTL -#define MASK_CTL_ID 0 -#define MASK_CTL_OFFSET 0x0000 -#define MASK_CTL_E_LENGTH 4 -#define MASK_CTL_E_OFFSET 0 -#define MASK_CTL_NR_E 1 - -#define DEVICE_ID -#define MASK_CTL_DEVICE_ID_BOFFSET 8 -#define MASK_CTL_DEVICE_ID_BLEN 8 -#define MASK_CTL_DEVICE_ID_FLAG HSL_RO - -#define REV_ID -#define MASK_CTL_REV_ID_BOFFSET 0 -#define MASK_CTL_REV_ID_BLEN 8 -#define MASK_CTL_REV_ID_FLAG HSL_RO - - -/* RGMII Control Register */ -#define RGMII_CTRL -#define RGMII_CTRL_ID 0 -#define RGMII_CTRL_OFFSET 0x0004 -#define RGMII_CTRL_E_LENGTH 4 -#define RGMII_CTRL_E_OFFSET 0 -#define RGMII_CTRL_NR_E 1 - -#define RMII1_MASTER_EN -#define RGMII_CTRL_RMII1_MASTER_EN_BOFFSET 25 -#define RGMII_CTRL_RMII1_MASTER_EN_BLEN 1 -#define RGMII_CTRL_RMII1_MASTER_EN_FLAG HSL_RW - -#define RMII0_MASTER_EN -#define RGMII_CTRL_RMII0_MASTER_EN_BOFFSET 24 -#define RGMII_CTRL_RMII0_MASTER_EN_BLEN 1 -#define RGMII_CTRL_RMII0_MASTER_EN_FLAG HSL_RW - - -/* Global Interrupt Status Register1 */ -#define GBL_INT_STATUS1 -#define GBL_INT_STATUS1_ID 1 -#define GBL_INT_STATUS1_OFFSET 0x0024 -#define GBL_INT_STATUS1_E_LENGTH 4 -#define GBL_INT_STATUS1_E_OFFSET 0 -#define GBL_INT_STATUS1_NR_E 1 - -#define LINK_CHG_INT_S -#define GBL_INT_STATUS1_LINK_CHG_INT_S_BOFFSET 1 -#define GBL_INT_STATUS1_LINK_CHG_INT_S_BLEN 7 -#define GBL_INT_STATUS1_LINK_CHG_INT_S_FLAG HSL_RW - -#define PHY_INT_S -#define GBL_INT_STATUS1_PHY_INT_S_BOFFSET 15 -#define GBL_INT_STATUS1_PHY_INT_S_BLEN 1 -#define GBL_INT_STATUS1_PHY_INT_S_FLAG HSL_RO - - - /* Global Interrupt Mask Register1 */ -#define GBL_INT_MASK1 -#define GBL_INT_MASK1_ID 1 -#define GBL_INT_MASK1_OFFSET 0x002c -#define GBL_INT_MASK1_E_LENGTH 4 -#define GBL_INT_MASK1_E_OFFSET 0 -#define GBL_INT_MASK1_NR_E 1 - -#define LINK_CHG_INT_M -#define GBL_INT_MASK1_LINK_CHG_INT_M_BOFFSET 1 -#define GBL_INT_MASK1_LINK_CHG_INT_M_BLEN 7 -#define GBL_INT_MASK1_LINK_CHG_INT_M_FLAG HSL_RW - -#define PHY_INT_M -#define GBL_INT_MASK1_PHY_INT_M_BOFFSET 15 -#define GBL_INT_MASK1_PHY_INT_M_BLEN 1 -#define GBL_INT_MASK1_PHY_INT_M_FLAG HSL_RO - - - - - /* Module Enable Register */ -#define MOD_ENABLE -#define MOD_ENABLE_OFFSET 0x0030 -#define MOD_ENABLE_E_LENGTH 4 -#define MOD_ENABLE_E_OFFSET 0 -#define MOD_ENABLE_NR_E 1 - -#define L3_EN -#define MOD_ENABLE_L3_EN_BOFFSET 2 -#define MOD_ENABLE_L3_EN_BLEN 1 -#define MOD_ENABLE_L3_EN_FLAG HSL_RW - -#define ACL_EN -#define MOD_ENABLE_ACL_EN_BOFFSET 1 -#define MOD_ENABLE_ACL_EN_BLEN 1 -#define MOD_ENABLE_ACL_EN_FLAG HSL_RW - -#define MIB_EN -#define MOD_ENABLE_MIB_EN_BOFFSET 0 -#define MOD_ENABLE_MIB_EN_BLEN 1 -#define MOD_ENABLE_MIB_EN_FLAG HSL_RW - - - - - /* MIB Function Register */ -#define MIB_FUNC -#define MIB_FUNC_OFFSET 0x0034 -#define MIB_FUNC_E_LENGTH 4 -#define MIB_FUNC_E_OFFSET 0 -#define MIB_FUNC_NR_E 1 - -#define MIB_FUN -#define MIB_FUNC_MIB_FUN_BOFFSET 24 -#define MIB_FUNC_MIB_FUN_BLEN 3 -#define MIB_FUNC_MIB_FUN_FLAG HSL_RW - -#define MIB_FLUSH_PORT -#define MIB_FUNC_MIB_FLUSH_PORT_BOFFSET 21 -#define MIB_FUNC_MIB_FLUSH_PORT_BLEN 3 -#define MIB_FUNC_MIB_FLUSH_PORT_FLAG HSL_RW - -#define MIB_CPU_KEEP -#define MIB_FUNC_MIB_CPU_KEEP_BOFFSET 20 -#define MIB_FUNC_MIB_CPU_KEEP_BLEN 1 -#define MIB_FUNC_MIB_CPU_KEEP_FLAG HSL_RW - -#define MIB_BUSY -#define MIB_FUNC_MIB_BUSY_BOFFSET 17 -#define MIB_FUNC_MIB_BUSY_BLEN 1 -#define MIB_FUNC_MIB_BUSY_FLAG HSL_RW - -#define MIB_AT_HALF_EN -#define MIB_FUNC_MIB_AT_HALF_EN_BOFFSET 16 -#define MIB_FUNC_MIB_AT_HALF_EN_BLEN 1 -#define MIB_FUNC_MIB_AT_HALF_EN_FLAG HSL_RW - -#define MIB_TIMER -#define MIB_FUNC_MIB_TIMER_BOFFSET 0 -#define MIB_FUNC_MIB_TIMER_BLEN 16 -#define MIB_FUNC_MIB_TIMER_FLAG HSL_RW - - - - - /* Service tag Register */ -#define SERVICE_TAG -#define SERVICE_TAG_OFFSET 0x0048 -#define SERVICE_TAG_E_LENGTH 4 -#define SERVICE_TAG_E_OFFSET 0 -#define SERVICE_TAG_NR_E 1 - -#define STAG_MODE -#define SERVICE_TAG_STAG_MODE_BOFFSET 17 -#define SERVICE_TAG_STAG_MODE_BLEN 1 -#define SERVICE_TAG_STAG_MODE_FLAG HSL_RW - -#define TAG_VALUE -#define SERVICE_TAG_TAG_VALUE_BOFFSET 0 -#define SERVICE_TAG_TAG_VALUE_BLEN 16 -#define SERVICE_TAG_TAG_VALUE_FLAG HSL_RW - - - - - /* Global MAC Address Register */ -#define GLOBAL_MAC_ADDR0 -#define GLOBAL_MAC_ADDR0_OFFSET 0x0060 -#define GLOBAL_MAC_ADDR0_E_LENGTH 4 -#define GLOBAL_MAC_ADDR0_E_OFFSET 0 -#define GLOBAL_MAC_ADDR0_NR_E 1 - -#define GLB_BYTE4 -#define GLOBAL_MAC_ADDR0_GLB_BYTE4_BOFFSET 8 -#define GLOBAL_MAC_ADDR0_GLB_BYTE4_BLEN 8 -#define GLOBAL_MAC_ADDR0_GLB_BYTE4_FLAG HSL_RW - -#define GLB_BYTE5 -#define GLOBAL_MAC_ADDR0_GLB_BYTE5_BOFFSET 0 -#define GLOBAL_MAC_ADDR0_GLB_BYTE5_BLEN 8 -#define GLOBAL_MAC_ADDR0_GLB_BYTE5_FLAG HSL_RW - -#define GLOBAL_MAC_ADDR1 -#define GLOBAL_MAC_ADDR1_ID 4 -#define GLOBAL_MAC_ADDR1_OFFSET 0x0064 -#define GLOBAL_MAC_ADDR1_E_LENGTH 4 -#define GLOBAL_MAC_ADDR1_E_OFFSET 0 -#define GLOBAL_MAC_ADDR1_NR_E 1 - -#define GLB_BYTE0 -#define GLOBAL_MAC_ADDR1_GLB_BYTE0_BOFFSET 24 -#define GLOBAL_MAC_ADDR1_GLB_BYTE0_BLEN 8 -#define GLOBAL_MAC_ADDR1_GLB_BYTE0_FLAG HSL_RW - -#define GLB_BYTE1 -#define GLOBAL_MAC_ADDR1_GLB_BYTE1_BOFFSET 16 -#define GLOBAL_MAC_ADDR1_GLB_BYTE1_BLEN 8 -#define GLOBAL_MAC_ADDR1_GLB_BYTE1_FLAG HSL_RW - -#define GLB_BYTE2 -#define GLOBAL_MAC_ADDR1_GLB_BYTE2_BOFFSET 8 -#define GLOBAL_MAC_ADDR1_GLB_BYTE2_BLEN 8 -#define GLOBAL_MAC_ADDR1_GLB_BYTE2_FLAG HSL_RW - -#define GLB_BYTE3 -#define GLOBAL_MAC_ADDR1_GLB_BYTE3_BOFFSET 0 -#define GLOBAL_MAC_ADDR1_GLB_BYTE3_BLEN 8 -#define GLOBAL_MAC_ADDR1_GLB_BYTE3_FLAG HSL_RW - - - - - /* Max Size Register */ -#define MAX_SIZE -#define MAX_SIZE_OFFSET 0x0078 -#define MAX_SIZE_E_LENGTH 4 -#define MAX_SIZE_E_OFFSET 0 -#define MAX_SIZE_NR_E 1 - -#define CRC_RESERVE -#define MAX_SIZE_CRC_RESERVE_BOFFSET 16 -#define MAX_SIZE_CRC_RESERVE_BLEN 1 -#define MAX_SIZE_CRC_RESERVE_FLAG HSL_RW - -#define MAX_FRAME_SIZE -#define MAX_SIZE_MAX_FRAME_SIZE_BOFFSET 0 -#define MAX_SIZE_MAX_FRAME_SIZE_BLEN 14 -#define MAX_SIZE_MAX_FRAME_SIZE_FLAG HSL_RW - - - - - - - - - - - - - /* Port Status Register */ -#define PORT_STATUS -#define PORT_STATUS_OFFSET 0x007c -#define PORT_STATUS_E_LENGTH 4 -#define PORT_STATUS_E_OFFSET 0x0004 -#define PORT_STATUS_NR_E 7 - -#define FLOW_LINK_EN -#define PORT_STATUS_FLOW_LINK_EN_BOFFSET 12 -#define PORT_STATUS_FLOW_LINK_EN_BLEN 1 -#define PORT_STATUS_FLOW_LINK_EN_FLAG HSL_RW - -#define AUTO_RX_FLOW -#define PORT_STATUS_AUTO_RX_FLOW_BOFFSET 11 -#define PORT_STATUS_AUTO_RX_FLOW_BLEN 1 -#define PORT_STATUS_AUTO_RX_FLOW_FLAG HSL_RO - -#define AUTO_TX_FLOW -#define PORT_STATUS_AUTO_TX_FLOW_BOFFSET 10 -#define PORT_STATUS_AUTO_TX_FLOW_BLEN 1 -#define PORT_STATUS_AUTO_TX_FLOW_FLAG HSL_RO - -#define LINK_EN -#define PORT_STATUS_LINK_EN_BOFFSET 9 -#define PORT_STATUS_LINK_EN_BLEN 1 -#define PORT_STATUS_LINK_EN_FLAG HSL_RW - -#define LINK -#define PORT_STATUS_LINK_BOFFSET 8 -#define PORT_STATUS_LINK_BLEN 1 -#define PORT_STATUS_LINK_FLAG HSL_RO - -#define TX_HALF_FLOW_EN -#define PORT_STATUS_TX_HALF_FLOW_EN_BOFFSET 7 -#define PORT_STATUS_TX_HALF_FLOW_EN_BLEN 1 -#define PORT_STATUS_TX_HALF_FLOW_EN_FLAG HSL_RW - -#define DUPLEX_MODE -#define PORT_STATUS_DUPLEX_MODE_BOFFSET 6 -#define PORT_STATUS_DUPLEX_MODE_BLEN 1 -#define PORT_STATUS_DUPLEX_MODE_FLAG HSL_RW - -#define RX_FLOW_EN -#define PORT_STATUS_RX_FLOW_EN_BOFFSET 5 -#define PORT_STATUS_RX_FLOW_EN_BLEN 1 -#define PORT_STATUS_RX_FLOW_EN_FLAG HSL_RW - -#define TX_FLOW_EN -#define PORT_STATUS_TX_FLOW_EN_BOFFSET 4 -#define PORT_STATUS_TX_FLOW_EN_BLEN 1 -#define PORT_STATUS_TX_FLOW_EN_FLAG HSL_RW - -#define RXMAC_EN -#define PORT_STATUS_RXMAC_EN_BOFFSET 3 -#define PORT_STATUS_RXMAC_EN_BLEN 1 -#define PORT_STATUS_RXMAC_EN_FLAG HSL_RW - -#define TXMAC_EN -#define PORT_STATUS_TXMAC_EN_BOFFSET 2 -#define PORT_STATUS_TXMAC_EN_BLEN 1 -#define PORT_STATUS_TXMAC_EN_FLAG HSL_RW - -#define SPEED_MODE -#define PORT_STATUS_SPEED_MODE_BOFFSET 0 -#define PORT_STATUS_SPEED_MODE_BLEN 2 -#define PORT_STATUS_SPEED_MODE_FLAG HSL_RW - - - - - /* Header Ctl Register */ -#define HEADER_CTL -#define HEADER_CTL_OFFSET 0x0098 -#define HEADER_CTL_E_LENGTH 4 -#define HEADER_CTL_E_OFFSET 0x0004 -#define HEADER_CTL_NR_E 1 - -#define TYPE_LEN -#define HEADER_CTL_TYPE_LEN_BOFFSET 16 -#define HEADER_CTL_TYPE_LEN_BLEN 1 -#define HEADER_CTL_TYPE_LEN_FLAG HSL_RW - -#define TYPE_VAL -#define HEADER_CTL_TYPE_VAL_BOFFSET 0 -#define HEADER_CTL_TYPE_VAL_BLEN 16 -#define HEADER_CTL_TYPE_VAL_FLAG HSL_RW - - - - - /* Port Header Ctl Register */ -#define PORT_HDR_CTL -#define PORT_HDR_CTL_OFFSET 0x009c -#define PORT_HDR_CTL_E_LENGTH 4 -#define PORT_HDR_CTL_E_OFFSET 0x0004 -#define PORT_HDR_CTL_NR_E 7 - -#define IPG_DEC_EN -#define PORT_HDR_CTL_IPG_DEC_EN_BOFFSET 5 -#define PORT_HDR_CTL_IPG_DEC_EN_BLEN 1 -#define PORT_HDR_CTL_IPG_DEC_EN_FLAG HSL_RW - -#define LOOPBACK_EN -#define PORT_HDR_CTL_LOOPBACK_EN_BOFFSET 4 -#define PORT_HDR_CTL_LOOPBACK_EN_BLEN 1 -#define PORT_HDR_CTL_LOOPBACK_EN_FLAG HSL_RW - -#define RXHDR_MODE -#define PORT_HDR_CTL_RXHDR_MODE_BOFFSET 2 -#define PORT_HDR_CTL_RXHDR_MODE_BLEN 2 -#define PORT_HDR_CTL_RXHDR_MODE_FLAG HSL_RW - -#define TXHDR_MODE -#define PORT_HDR_CTL_TXHDR_MODE_BOFFSET 0 -#define PORT_HDR_CTL_TXHDR_MODE_BLEN 2 -#define PORT_HDR_CTL_TXHDR_MODE_FLAG HSL_RW - - - - - /* EEE control Register */ -#define EEE_CTL -#define EEE_CTL_OFFSET 0x0100 -#define EEE_CTL_E_LENGTH 4 -#define EEE_CTL_E_OFFSET 0 -#define EEE_CTL_NR_E 1 - -#define LPI_STATE_REMAP_EN_5 -#define EEE_CTL_LPI_STATE_REMAP_EN_5_BOFFSET 13 -#define EEE_CTL_LPI_STATE_REMAP_EN_5_BLEN 1 -#define EEE_CTL_LPI_STATE_REMAP_EN_5_FLAG HSL_RW - -#define LPI_EN_5 -#define EEE_CTL_LPI_EN_5_BOFFSET 12 -#define EEE_CTL_LPI_EN_5_BLEN 1 -#define EEE_CTL_LPI_EN_5_FLAG HSL_RW - -#define LPI_STATE_REMAP_EN_4 -#define EEE_CTL_LPI_STATE_REMAP_EN_4_BOFFSET 11 -#define EEE_CTL_LPI_STATE_REMAP_EN_4_BLEN 1 -#define EEE_CTL_LPI_STATE_REMAP_EN_4_FLAG HSL_RW - -#define LPI_EN_4 -#define EEE_CTL_LPI_EN_4_BOFFSET 10 -#define EEE_CTL_LPI_EN_4_BLEN 1 -#define EEE_CTL_LPI_EN_4_FLAG HSL_RW - -#define LPI_STATE_REMAP_EN_3 -#define EEE_CTL_LPI_STATE_REMAP_EN_3_BOFFSET 9 -#define EEE_CTL_LPI_STATE_REMAP_EN_3_BLEN 1 -#define EEE_CTL_LPI_STATE_REMAP_EN_3_FLAG HSL_RW - -#define LPI_EN_3 -#define EEE_CTL_LPI_EN_3_BOFFSET 8 -#define EEE_CTL_LPI_EN_3_BLEN 1 -#define EEE_CTL_LPI_EN_3_FLAG HSL_RW - -#define LPI_STATE_REMAP_EN_2 -#define EEE_CTL_LPI_STATE_REMAP_EN_2_BOFFSET 7 -#define EEE_CTL_LPI_STATE_REMAP_EN_2_BLEN 1 -#define EEE_CTL_LPI_STATE_REMAP_EN_2_FLAG HSL_RW - -#define LPI_EN_2 -#define EEE_CTL_LPI_EN_2_BOFFSET 6 -#define EEE_CTL_LPI_EN_2_BLEN 1 -#define EEE_CTL_LPI_EN_2_FLAG HSL_RW - -#define LPI_STATE_REMAP_EN_1 -#define EEE_CTL_LPI_STATE_REMAP_EN_1_BOFFSET 5 -#define EEE_CTL_LPI_STATE_REMAP_EN_1_BLEN 1 -#define EEE_CTL_LPI_STATE_REMAP_EN_1_FLAG HSL_RW - -#define LPI_EN_1 -#define EEE_CTL_LPI_EN_1_BOFFSET 4 -#define EEE_CTL_LPI_EN_1_BLEN 1 -#define EEE_CTL_LPI_EN_1_FLAG HSL_RW - - - - - /* Frame Ack Ctl0 Register */ -#define FRAME_ACK_CTL0 -#define FRAME_ACK_CTL0_OFFSET 0x0210 -#define FRAME_ACK_CTL0_E_LENGTH 4 -#define FRAME_ACK_CTL0_E_OFFSET 0 -#define FRAME_ACK_CTL0_NR_E 1 - -#define ARP_REQ_EN -#define FRAME_ACK_CTL0_ARP_REQ_EN_BOFFSET 6 -#define FRAME_ACK_CTL0_ARP_REQ_EN_BLEN 1 -#define FRAME_ACK_CTL0_ARP_REQ_EN_FLAG HSL_RW - -#define ARP_REP_EN -#define FRAME_ACK_CTL0_ARP_REP_EN_BOFFSET 5 -#define FRAME_ACK_CTL0_ARP_REP_EN_BLEN 1 -#define FRAME_ACK_CTL0_ARP_REP_EN_FLAG HSL_RW - -#define DHCP_EN -#define FRAME_ACK_CTL0_DHCP_EN_BOFFSET 4 -#define FRAME_ACK_CTL0_DHCP_EN_BLEN 1 -#define FRAME_ACK_CTL0_DHCP_EN_FLAG HSL_RW - -#define EAPOL_EN -#define FRAME_ACK_CTL0_EAPOL_EN_BOFFSET 3 -#define FRAME_ACK_CTL0_EAPOL_EN_BLEN 1 -#define FRAME_ACK_CTL0_EAPOL_EN_FLAG HSL_RW - -#define LEAVE_EN -#define FRAME_ACK_CTL0_LEAVE_EN_BOFFSET 2 -#define FRAME_ACK_CTL0_LEAVE_EN_BLEN 1 -#define FRAME_ACK_CTL0_LEAVE_EN_FLAG HSL_RW - -#define JOIN_EN -#define FRAME_ACK_CTL0_JOIN_EN_BOFFSET 1 -#define FRAME_ACK_CTL0_JOIN_EN_BLEN 1 -#define FRAME_ACK_CTL0_JOIN_EN_FLAG HSL_RW - -#define IGMP_MLD_EN -#define FRAME_ACK_CTL0_IGMP_MLD_EN_BOFFSET 0 -#define FRAME_ACK_CTL0_IGMP_MLD_EN_BLEN 1 -#define FRAME_ACK_CTL0_IGMP_MLD_EN_FLAG HSL_RW - - - - - /* Frame Ack Ctl1 Register */ -#define FRAME_ACK_CTL1 -#define FRAME_ACK_CTL1_OFFSET 0x0214 -#define FRAME_ACK_CTL1_E_LENGTH 4 -#define FRAME_ACK_CTL1_E_OFFSET 0 -#define FRAME_ACK_CTL1_NR_E 1 - -#define LLDP_EN -#define FRAME_ACK_CTL1_LLDP_EN_BOFFSET 26 -#define FRAME_ACK_CTL1_LLDP_EN_BLEN 1 -#define FRAME_ACK_CTL1_LLDP_EN_FLAG HSL_RW - - -#define PPPOE_EN -#define FRAME_ACK_CTL1_PPPOE_EN_BOFFSET 25 -#define FRAME_ACK_CTL1_PPPOE_EN_BLEN 1 -#define FRAME_ACK_CTL1_PPPOE_EN_FLAG HSL_RW - -#define IGMP_V3_EN -#define FRAME_ACK_CTL1_IGMP_V3_EN_BOFFSET 24 -#define FRAME_ACK_CTL1_IGMP_V3_EN_BLEN 1 -#define FRAME_ACK_CTL1_IGMP_V3_EN_FLAG HSL_RW - - - - - /* Window Rule Ctl0 Register */ -#define WIN_RULE_CTL0 -#define WIN_RULE_CTL0_OFFSET 0x0218 -#define WIN_RULE_CTL0_E_LENGTH 4 -#define WIN_RULE_CTL0_E_OFFSET 0x4 -#define WIN_RULE_CTL0_NR_E 7 - -#define L4_LENGTH -#define WIN_RULE_CTL0_L4_LENGTH_BOFFSET 24 -#define WIN_RULE_CTL0_L4_LENGTH_BLEN 4 -#define WIN_RULE_CTL0_L4_LENGTH_FLAG HSL_RW - -#define L3_LENGTH -#define WIN_RULE_CTL0_L3_LENGTH_BOFFSET 20 -#define WIN_RULE_CTL0_L3_LENGTH_BLEN 4 -#define WIN_RULE_CTL0_L3_LENGTH_FLAG HSL_RW - -#define L2_LENGTH -#define WIN_RULE_CTL0_L2_LENGTH_BOFFSET 16 -#define WIN_RULE_CTL0_L2_LENGTH_BLEN 4 -#define WIN_RULE_CTL0_L2_LENGTH_FLAG HSL_RW - -#define L4_OFFSET -#define WIN_RULE_CTL0_L4_OFFSET_BOFFSET 10 -#define WIN_RULE_CTL0_L4_OFFSET_BLEN 5 -#define WIN_RULE_CTL0_L4_OFFSET_FLAG HSL_RW - -#define L3_OFFSET -#define WIN_RULE_CTL0_L3_OFFSET_BOFFSET 5 -#define WIN_RULE_CTL0_L3_OFFSET_BLEN 5 -#define WIN_RULE_CTL0_L3_OFFSET_FLAG HSL_RW - -#define L2_OFFSET -#define WIN_RULE_CTL0_L2_OFFSET_BOFFSET 0 -#define WIN_RULE_CTL0_L2_OFFSET_BLEN 5 -#define WIN_RULE_CTL0_L2_OFFSET_FLAG HSL_RW - - - - - /* Window Rule Ctl1 Register */ -#define WIN_RULE_CTL1 -#define WIN_RULE_CTL1_OFFSET 0x0234 -#define WIN_RULE_CTL1_E_LENGTH 4 -#define WIN_RULE_CTL1_E_OFFSET 0x4 -#define WIN_RULE_CTL1_NR_E 7 - -#define L3P_LENGTH -#define WIN_RULE_CTL1_L3P_LENGTH_BOFFSET 20 -#define WIN_RULE_CTL1_L3P_LENGTH_BLEN 4 -#define WIN_RULE_CTL1_L3P_LENGTH_FLAG HSL_RW - -#define L2S_LENGTH -#define WIN_RULE_CTL1_L2S_LENGTH_BOFFSET 16 -#define WIN_RULE_CTL1_L2S_LENGTH_BLEN 4 -#define WIN_RULE_CTL1_L2S_LENGTH_FLAG HSL_RW - -#define L3P_OFFSET -#define WIN_RULE_CTL1_L3P_OFFSET_BOFFSET 5 -#define WIN_RULE_CTL1_L3P_OFFSET_BLEN 5 -#define WIN_RULE_CTL1_L3P_OFFSET_FLAG HSL_RW - -#define L2S_OFFSET -#define WIN_RULE_CTL1_L2S_OFFSET_BOFFSET 0 -#define WIN_RULE_CTL1_L2S_OFFSET_BLEN 5 -#define WIN_RULE_CTL1_L2S_OFFSET_FLAG HSL_RW - - - - - /* Trunk Hash Mode Register */ -#define TRUNK_HASH_MODE -#define TRUNK_HASH_MODE_OFFSET 0x0270 -#define TRUNK_HASH_MODE_E_LENGTH 4 -#define TRUNK_HASH_MODE_E_OFFSET 0x4 -#define TRUNK_HASH_MODE_NR_E 1 - -#define DIP_EN -#define TRUNK_HASH_MODE_DIP_EN_BOFFSET 3 -#define TRUNK_HASH_MODE_DIP_EN_BLEN 1 -#define TRUNK_HASH_MODE_DIP_EN_FLAG HSL_RW - -#define SIP_EN -#define TRUNK_HASH_MODE_SIP_EN_BOFFSET 2 -#define TRUNK_HASH_MODE_SIP_EN_BLEN 1 -#define TRUNK_HASH_MODE_SIP_EN_FLAG HSL_RW - -#define SA_EN -#define TRUNK_HASH_MODE_SA_EN_BOFFSET 1 -#define TRUNK_HASH_MODE_SA_EN_BLEN 1 -#define TRUNK_HASH_MODE_SA_EN_FLAG HSL_RW - -#define DA_EN -#define TRUNK_HASH_MODE_DA_EN_BOFFSET 0 -#define TRUNK_HASH_MODE_DA_EN_BLEN 1 -#define TRUNK_HASH_MODE_DA_EN_FLAG HSL_RW - - - - - /* Vlan Table Function0 Register */ -#define VLAN_TABLE_FUNC0 -#define VLAN_TABLE_FUNC0_OFFSET 0x0610 -#define VLAN_TABLE_FUNC0_E_LENGTH 4 -#define VLAN_TABLE_FUNC0_E_OFFSET 0 -#define VLAN_TABLE_FUNC0_NR_E 1 - -#define VT_VALID -#define VLAN_TABLE_FUNC0_VT_VALID_BOFFSET 20 -#define VLAN_TABLE_FUNC0_VT_VALID_BLEN 1 -#define VLAN_TABLE_FUNC0_VT_VALID_FLAG HSL_RW - -#define IVL_EN -#define VLAN_TABLE_FUNC0_IVL_EN_BOFFSET 19 -#define VLAN_TABLE_FUNC0_IVL_EN_BLEN 1 -#define VLAN_TABLE_FUNC0_IVL_EN_FLAG HSL_RW - -#define LEARN_DIS -#define VLAN_TABLE_FUNC0_LEARN_DIS_BOFFSET 18 -#define VLAN_TABLE_FUNC0_LEARN_DIS_BLEN 1 -#define VLAN_TABLE_FUNC0_LEARN_DIS_FLAG HSL_RW - -#define VID_MEM -#define VLAN_TABLE_FUNC0_VID_MEM_BOFFSET 4 -#define VLAN_TABLE_FUNC0_VID_MEM_BLEN 14 -#define VLAN_TABLE_FUNC0_VID_MEM_FLAG HSL_RW - -#define VT_PRI_EN -#define VLAN_TABLE_FUNC0_VT_PRI_EN_BOFFSET 3 -#define VLAN_TABLE_FUNC0_VT_PRI_EN_BLEN 1 -#define VLAN_TABLE_FUNC0_VT_PRI_EN_FLAG HSL_RW - -#define VT_PRI -#define VLAN_TABLE_FUNC0_VT_PRI_BOFFSET 0 -#define VLAN_TABLE_FUNC0_VT_PRI_BLEN 3 -#define VLAN_TABLE_FUNC0_VT_PRI_FLAG HSL_RW - - /* Vlan Table Function1 Register */ -#define VLAN_TABLE_FUNC1 -#define VLAN_TABLE_FUNC1_OFFSET 0x0614 -#define VLAN_TABLE_FUNC1_E_LENGTH 4 -#define VLAN_TABLE_FUNC1_E_OFFSET 0 -#define VLAN_TABLE_FUNC1_NR_E 1 - -#define VT_BUSY -#define VLAN_TABLE_FUNC1_VT_BUSY_BOFFSET 31 -#define VLAN_TABLE_FUNC1_VT_BUSY_BLEN 1 -#define VLAN_TABLE_FUNC1_VT_BUSY_FLAG HSL_RW - -#define VLAN_ID -#define VLAN_TABLE_FUNC1_VLAN_ID_BOFFSET 16 -#define VLAN_TABLE_FUNC1_VLAN_ID_BLEN 12 -#define VLAN_TABLE_FUNC1_VLAN_ID_FLAG HSL_RW - -#define VT_PORT_NUM -#define VLAN_TABLE_FUNC1_VT_PORT_NUM_BOFFSET 8 -#define VLAN_TABLE_FUNC1_VT_PORT_NUM_BLEN 4 -#define VLAN_TABLE_FUNC1_VT_PORT_NUM_FLAG HSL_RW - -#define VT_FULL_VIO -#define VLAN_TABLE_FUNC1_VT_FULL_VIO_BOFFSET 4 -#define VLAN_TABLE_FUNC1_VT_FULL_VIO_BLEN 1 -#define VLAN_TABLE_FUNC1_VT_FULL_VIO_FLAG HSL_RW - -#define VT_FUNC -#define VLAN_TABLE_FUNC1_VT_FUNC_BOFFSET 0 -#define VLAN_TABLE_FUNC1_VT_FUNC_BLEN 3 -#define VLAN_TABLE_FUNC1_VT_FUNC_FLAG HSL_RW - - - - - /* Address Table Function0 Register */ -#define ADDR_TABLE_FUNC0 -#define ADDR_TABLE_FUNC0_OFFSET 0x0600 -#define ADDR_TABLE_FUNC0_E_LENGTH 4 -#define ADDR_TABLE_FUNC0_E_OFFSET 0 -#define ADDR_TABLE_FUNC0_NR_E 1 - - -#define AT_ADDR_BYTE2 -#define ADDR_TABLE_FUNC0_AT_ADDR_BYTE2_BOFFSET 24 -#define ADDR_TABLE_FUNC0_AT_ADDR_BYTE2_BLEN 8 -#define ADDR_TABLE_FUNC0_AT_ADDR_BYTE2_FLAG HSL_RW - -#define AT_ADDR_BYTE3 -#define ADDR_TABLE_FUNC0_AT_ADDR_BYTE3_BOFFSET 16 -#define ADDR_TABLE_FUNC0_AT_ADDR_BYTE3_BLEN 8 -#define ADDR_TABLE_FUNC0_AT_ADDR_BYTE3_FLAG HSL_RW - -#define AT_ADDR_BYTE4 -#define ADDR_TABLE_FUNC0_AT_ADDR_BYTE4_BOFFSET 8 -#define ADDR_TABLE_FUNC0_AT_ADDR_BYTE4_BLEN 8 -#define ADDR_TABLE_FUNC0_AT_ADDR_BYTE4_FLAG HSL_RW - -#define AT_ADDR_BYTE5 -#define ADDR_TABLE_FUNC0_AT_ADDR_BYTE5_BOFFSET 0 -#define ADDR_TABLE_FUNC0_AT_ADDR_BYTE5_BLEN 8 -#define ADDR_TABLE_FUNC0_AT_ADDR_BYTE5_FLAG HSL_RW - - /* Address Table Function1 Register */ -#define ADDR_TABLE_FUNC1 -#define ADDR_TABLE_FUNC1_OFFSET 0x0604 -#define ADDR_TABLE_FUNC1_E_LENGTH 4 -#define ADDR_TABLE_FUNC1_E_OFFSET 0 -#define ADDR_TABLE_FUNC1_NR_E 1 - -#define SA_DROP_EN -#define ADDR_TABLE_FUNC1_SA_DROP_EN_BOFFSET 30 -#define ADDR_TABLE_FUNC1_SA_DROP_EN_BLEN 1 -#define ADDR_TABLE_FUNC1_SA_DROP_EN_FLAG HSL_RW - -#define MIRROR_EN -#define ADDR_TABLE_FUNC1_MIRROR_EN_BOFFSET 29 -#define ADDR_TABLE_FUNC1_MIRROR_EN_BLEN 1 -#define ADDR_TABLE_FUNC1_MIRROR_EN_FLAG HSL_RW - -#define AT_PRI_EN -#define ADDR_TABLE_FUNC1_AT_PRI_EN_BOFFSET 28 -#define ADDR_TABLE_FUNC1_AT_PRI_EN_BLEN 1 -#define ADDR_TABLE_FUNC1_AT_PRI_EN_FLAG HSL_RW - -#define AT_SVL_EN -#define ADDR_TABLE_FUNC1_AT_SVL_EN_BOFFSET 27 -#define ADDR_TABLE_FUNC1_AT_SVL_EN_BLEN 1 -#define ADDR_TABLE_FUNC1_AT_SVL_EN_FLAG HSL_RW - -#define AT_PRI -#define ADDR_TABLE_FUNC1_AT_PRI_BOFFSET 24 -#define ADDR_TABLE_FUNC1_AT_PRI_BLEN 3 -#define ADDR_TABLE_FUNC1_AT_PRI_FLAG HSL_RW - -#define CROSS_PT -#define ADDR_TABLE_FUNC1_CROSS_PT_BOFFSET 23 -#define ADDR_TABLE_FUNC1_CROSS_PT_BLEN 1 -#define ADDR_TABLE_FUNC1_CROSS_PT_FLAG HSL_RW - -#define DES_PORT -#define ADDR_TABLE_FUNC1_DES_PORT_BOFFSET 16 -#define ADDR_TABLE_FUNC1_DES_PORT_BLEN 7 -#define ADDR_TABLE_FUNC1_DES_PORT_FLAG HSL_RW - -#define AT_ADDR_BYTE0 -#define ADDR_TABLE_FUNC1_AT_ADDR_BYTE0_BOFFSET 8 -#define ADDR_TABLE_FUNC1_AT_ADDR_BYTE0_BLEN 8 -#define ADDR_TABLE_FUNC1_AT_ADDR_BYTE0_FLAG HSL_RW - -#define AT_ADDR_BYTE1 -#define ADDR_TABLE_FUNC1_AT_ADDR_BYTE1_BOFFSET 0 -#define ADDR_TABLE_FUNC1_AT_ADDR_BYTE1_BLEN 8 -#define ADDR_TABLE_FUNC1_AT_ADDR_BYTE1_FLAG HSL_RW - - /* Address Table Function2 Register */ -#define ADDR_TABLE_FUNC2 -#define ADDR_TABLE_FUNC2_OFFSET 0x0608 -#define ADDR_TABLE_FUNC2_E_LENGTH 4 -#define ADDR_TABLE_FUNC2_E_OFFSET 0 -#define ADDR_TABLE_FUNC2_NR_E 1 - - -#define LOAD_BALANCE_EN -#define ADDR_TABLE_FUNC2_LOAD_BALANCE_EN_BOFFSET 23 -#define ADDR_TABLE_FUNC2_LOAD_BALANCE_EN_BLEN 1 -#define ADDR_TABLE_FUNC2_LOAD_BALANCE_EN_FLAG HSL_RW - -#define LOAD_BALANCE -#define ADDR_TABLE_FUNC2_LOAD_BALANCE_BOFFSET 21 -#define ADDR_TABLE_FUNC2_LOAD_BALANCE_BLEN 2 -#define ADDR_TABLE_FUNC2_LOAD_BALANCE_FLAG HSL_RW - -#define WL_EN -#define ADDR_TABLE_FUNC2_WL_EN_BOFFSET 20 -#define ADDR_TABLE_FUNC2_WL_EN_BLEN 1 -#define ADDR_TABLE_FUNC2_WL_EN_FLAG HSL_RW - -#define AT_VID -#define ADDR_TABLE_FUNC2_AT_VID_BOFFSET 8 -#define ADDR_TABLE_FUNC2_AT_VID_BLEN 12 -#define ADDR_TABLE_FUNC2_AT_VID_FLAG HSL_RW - -#define SHORT_LOOP -#define ADDR_TABLE_FUNC2_SHORT_LOOP_BOFFSET 7 -#define ADDR_TABLE_FUNC2_SHORT_LOOP_BLEN 1 -#define ADDR_TABLE_FUNC2_SHORT_LOOP_FLAG HSL_RW - -#define COPY_TO_CPU -#define ADDR_TABLE_FUNC2_COPY_TO_CPU_BOFFSET 6 -#define ADDR_TABLE_FUNC2_COPY_TO_CPU_BLEN 1 -#define ADDR_TABLE_FUNC2_COPY_TO_CPU_FLAG HSL_RW - -#define REDRCT_TO_CPU -#define ADDR_TABLE_FUNC2_REDRCT_TO_CPU_BOFFSET 5 -#define ADDR_TABLE_FUNC2_REDRCT_TO_CPU_BLEN 1 -#define ADDR_TABLE_FUNC2_REDRCT_TO_CPU_FLAG HSL_RW - -#define LEAKY_EN -#define ADDR_TABLE_FUNC2_LEAKY_EN_BOFFSET 4 -#define ADDR_TABLE_FUNC2_LEAKY_EN_BLEN 1 -#define ADDR_TABLE_FUNC2_LEAKY_EN_FLAG HSL_RW - -#define AT_STATUS -#define ADDR_TABLE_FUNC2_AT_STATUS_BOFFSET 0 -#define ADDR_TABLE_FUNC2_AT_STATUS_BLEN 4 -#define ADDR_TABLE_FUNC2_AT_STATUS_FLAG HSL_RW - - /* Address Table Function3 Register */ -#define ADDR_TABLE_FUNC3 -#define ADDR_TABLE_FUNC3_OFFSET 0x060c -#define ADDR_TABLE_FUNC3_E_LENGTH 4 -#define ADDR_TABLE_FUNC3_E_OFFSET 0 -#define ADDR_TABLE_FUNC3_NR_E 1 - -#define AT_BUSY -#define ADDR_TABLE_FUNC3_AT_BUSY_BOFFSET 31 -#define ADDR_TABLE_FUNC3_AT_BUSY_BLEN 1 -#define ADDR_TABLE_FUNC3_AT_BUSY_FLAG HSL_RW - -#define NEW_PORT_NUM -#define ADDR_TABLE_FUNC3_NEW_PORT_NUM_BOFFSET 22 -#define ADDR_TABLE_FUNC3_NEW_PORT_NUM_BLEN 3 -#define ADDR_TABLE_FUNC3_NEW_PORT_NUM_FLAG HSL_RW - -#define AT_INDEX -#define ADDR_TABLE_FUNC3_AT_INDEX_BOFFSET 16 -#define ADDR_TABLE_FUNC3_AT_INDEX_BLEN 5 -#define ADDR_TABLE_FUNC3_AT_INDEX_FLAG HSL_RW - -#define AT_VID_EN -#define ADDR_TABLE_FUNC3_AT_VID_EN_BOFFSET 15 -#define ADDR_TABLE_FUNC3_AT_VID_EN_BLEN 1 -#define ADDR_TABLE_FUNC3_AT_VID_EN_FLAG HSL_RW - -#define AT_PORT_EN -#define ADDR_TABLE_FUNC3_AT_PORT_EN_BOFFSET 14 -#define ADDR_TABLE_FUNC3_AT_PORT_EN_BLEN 1 -#define ADDR_TABLE_FUNC3_AT_PORT_EN_FLAG HSL_RW - -#define AT_MULTI_EN -#define ADDR_TABLE_FUNC3_AT_MULTI_EN_BOFFSET 13 -#define ADDR_TABLE_FUNC3_AT_MULTI_EN_BLEN 1 -#define ADDR_TABLE_FUNC3_AT_MULTI_EN_FLAG HSL_RW - -#define AT_FULL_VIO -#define ADDR_TABLE_FUNC3_AT_FULL_VIO_BOFFSET 12 -#define ADDR_TABLE_FUNC3_AT_FULL_VIO_BLEN 1 -#define ADDR_TABLE_FUNC3_AT_FULL_VIO_FLAG HSL_RW - -#define AT_PORT_NUM -#define ADDR_TABLE_FUNC3_AT_PORT_NUM_BOFFSET 8 -#define ADDR_TABLE_FUNC3_AT_PORT_NUM_BLEN 4 -#define ADDR_TABLE_FUNC3_AT_PORT_NUM_FLAG HSL_RW - -#define FLUSH_ST_EN -#define ADDR_TABLE_FUNC3_FLUSH_ST_EN_BOFFSET 4 -#define ADDR_TABLE_FUNC3_FLUSH_ST_EN_BLEN 1 -#define ADDR_TABLE_FUNC3_FLUSH_ST_EN_FLAG HSL_RW - -#define AT_FUNC -#define ADDR_TABLE_FUNC3_AT_FUNC_BOFFSET 0 -#define ADDR_TABLE_FUNC3_AT_FUNC_BLEN 4 -#define ADDR_TABLE_FUNC3_AT_FUNC_FLAG HSL_RW - - - - - /* Reserve Address Table0 Register */ -#define RESV_ADDR_TBL0 -#define RESV_ADDR_TBL0_OFFSET 0x3c000 -#define RESV_ADDR_TBL0_E_LENGTH 4 -#define RESV_ADDR_TBL0_E_OFFSET 0 -#define RESV_ADDR_TBL0_NR_E 1 - -#define RESV_ADDR_BYTE2 -#define RESV_ADDR_TBL0_RESV_ADDR_BYTE2_BOFFSET 24 -#define RESV_ADDR_TBL0_RESV_ADDR_BYTE2_BLEN 8 -#define RESV_ADDR_TBL0_RESV_ADDR_BYTE2_FLAG HSL_RW - -#define RESV_ADDR_BYTE3 -#define RESV_ADDR_TBL0_RESV_ADDR_BYTE3_BOFFSET 16 -#define RESV_ADDR_TBL0_RESV_ADDR_BYTE3_BLEN 8 -#define RESV_ADDR_TBL0_RESV_ADDR_BYTE3_FLAG HSL_RW - -#define RESV_ADDR_BYTE4 -#define RESV_ADDR_TBL0_RESV_ADDR_BYTE4_BOFFSET 8 -#define RESV_ADDR_TBL0_RESV_ADDR_BYTE4_BLEN 8 -#define RESV_ADDR_TBL0_RESV_ADDR_BYTE4_FLAG HSL_RW - -#define RESV_ADDR_BYTE5 -#define RESV_ADDR_TBL0_RESV_ADDR_BYTE5_BOFFSET 0 -#define RESV_ADDR_TBL0_RESV_ADDR_BYTE5_BLEN 8 -#define RESV_ADDR_TBL0_RESV_ADDR_BYTE5_FLAG HSL_RW - - /* Reserve Address Table1 Register */ -#define RESV_ADDR_TBL1 -#define RESV_ADDR_TBL1_OFFSET 0x3c004 -#define RESV_ADDR_TBL1_E_LENGTH 4 -#define RESV_ADDR_TBL1_E_OFFSET 0 -#define RESV_ADDR_TBL1_NR_E 1 - -#define RESV_COPY_TO_CPU -#define RESV_ADDR_TBL1_RESV_COPY_TO_CPU_BOFFSET 31 -#define RESV_ADDR_TBL1_RESV_COPY_TO_CPU_BLEN 1 -#define RESV_ADDR_TBL1_RESV_COPY_TO_CPU_FLAG HSL_RW - -#define RESV_REDRCT_TO_CPU -#define RESV_ADDR_TBL1_RESV_REDRCT_TO_CPU_BOFFSET 30 -#define RESV_ADDR_TBL1_RESV_REDRCT_TO_CPU_BLEN 1 -#define RESV_ADDR_TBL1_RESV_REDRCT_TO_CPU_FLAG HSL_RW - -#define RESV_LEAKY_EN -#define RESV_ADDR_TBL1_RESV_LEAKY_EN_BOFFSET 29 -#define RESV_ADDR_TBL1_RESV_LEAKY_EN_BLEN 1 -#define RESV_ADDR_TBL1_RESV_LEAKY_EN_FLAG HSL_RW - -#define RESV_MIRROR_EN -#define RESV_ADDR_TBL1_RESV_MIRROR_EN_BOFFSET 28 -#define RESV_ADDR_TBL1_RESV_MIRROR_EN_BLEN 1 -#define RESV_ADDR_TBL1_RESV_MIRROR_EN_FLAG HSL_RW - -#define RESV_PRI_EN -#define RESV_ADDR_TBL1_RESV_PRI_EN_BOFFSET 27 -#define RESV_ADDR_TBL1_RESV_PRI_EN_BLEN 1 -#define RESV_ADDR_TBL1_RESV_PRI_EN_FLAG HSL_RW - -#define RESV_PRI -#define RESV_ADDR_TBL1_RESV_PRI_BOFFSET 24 -#define RESV_ADDR_TBL1_RESV_PRI_BLEN 3 -#define RESV_ADDR_TBL1_RESV_PRI_FLAG HSL_RW - -#define RESV_CROSS_PT -#define RESV_ADDR_TBL1_RESV_CROSS_PT_BOFFSET 23 -#define RESV_ADDR_TBL1_RESV_CROSS_PT_BLEN 1 -#define RESV_ADDR_TBL1_RESV_CROSS_PT_FLAG HSL_RW - -#define RESV_DES_PORT -#define RESV_ADDR_TBL1_RESV_DES_PORT_BOFFSET 16 -#define RESV_ADDR_TBL1_RESV_DES_PORT_BLEN 7 -#define RESV_ADDR_TBL1_RESV_DES_PORT_FLAG HSL_RW - -#define RESV_ADDR_BYTE0 -#define RESV_ADDR_TBL1_RESV_ADDR_BYTE0_BOFFSET 8 -#define RESV_ADDR_TBL1_RESV_ADDR_BYTE0_BLEN 8 -#define RESV_ADDR_TBL1_RESV_ADDR_BYTE0_FLAG HSL_RW - -#define RESV_ADDR_BYTE1 -#define RESV_ADDR_TBL1_RESV_ADDR_BYTE1_BOFFSET 0 -#define RESV_ADDR_TBL1_RESV_ADDR_BYTE1_BLEN 8 -#define RESV_ADDR_TBL1_RESV_ADDR_BYTE1_FLAG HSL_RW - - /* Reserve Address Table2 Register */ -#define RESV_ADDR_TBL2 -#define RESV_ADDR_TBL2_OFFSET 0x3c008 -#define RESV_ADDR_TBL2_E_LENGTH 4 -#define RESV_ADDR_TBL2_E_OFFSET 0 -#define RESV_ADDR_TBL2_NR_E 1 - -#define RESV_STATUS -#define RESV_ADDR_TBL2_RESV_STATUS_BOFFSET 0 -#define RESV_ADDR_TBL2_RESV_STATUS_BLEN 1 -#define RESV_ADDR_TBL2_RESV_STATUS_FLAG HSL_RW - - - - - /* Address Table Control Register */ -#define ADDR_TABLE_CTL -#define ADDR_TABLE_CTL_OFFSET 0x0618 -#define ADDR_TABLE_CTL_E_LENGTH 4 -#define ADDR_TABLE_CTL_E_OFFSET 0 -#define ADDR_TABLE_CTL_NR_E 1 - -#define ARL_INI_EN -#define ADDR_TABLE_CTL_ARL_INI_EN_BOFFSET 31 -#define ADDR_TABLE_CTL_ARL_INI_EN_BLEN 1 -#define ADDR_TABLE_CTL_ARL_INI_EN_FLAG HSL_RW - -#define LEARN_CHANGE_EN -#define ADDR_TABLE_CTL_LEARN_CHANGE_EN_BOFFSET 30 -#define ADDR_TABLE_CTL_LEARN_CHANGE_EN_BLEN 1 -#define ADDR_TABLE_CTL_LEARN_CHANGE_EN_FLAG HSL_RW - -#define IGMP_JOIN_LEAKY -#define ADDR_TABLE_CTL_IGMP_JOIN_LEAKY_BOFFSET 29 -#define ADDR_TABLE_CTL_IGMP_JOIN_LEAKY_BLEN 1 -#define ADDR_TABLE_CTL_IGMP_JOIN_LEAKY_FLAG HSL_RW - -#define IGMP_CREAT_EN -#define ADDR_TABLE_CTL_IGMP_CREAT_EN_BOFFSET 28 -#define ADDR_TABLE_CTL_IGMP_CREAT_EN_BLEN 1 -#define ADDR_TABLE_CTL_IGMP_CREAT_EN_FLAG HSL_RW - -#define IGMP_PRI_EN -#define ADDR_TABLE_CTL_IGMP_PRI_EN_BOFFSET 27 -#define ADDR_TABLE_CTL_IGMP_PRI_EN_BLEN 1 -#define ADDR_TABLE_CTL_IGMP_PRI_EN_FLAG HSL_RW - -#define IGMP_PRI -#define ADDR_TABLE_CTL_IGMP_PRI_BOFFSET 24 -#define ADDR_TABLE_CTL_IGMP_PRI_BLEN 3 -#define ADDR_TABLE_CTL_IGMP_PRI_FLAG HSL_RW - -#define IGMP_JOIN_STATIC -#define ADDR_TABLE_CTL_IGMP_JOIN_STATIC_BOFFSET 20 -#define ADDR_TABLE_CTL_IGMP_JOIN_STATIC_BLEN 4 -#define ADDR_TABLE_CTL_IGMP_JOIN_STATIC_FLAG HSL_RW - -#define AGE_EN -#define ADDR_TABLE_CTL_AGE_EN_BOFFSET 19 -#define ADDR_TABLE_CTL_AGE_EN_BLEN 1 -#define ADDR_TABLE_CTL_AGE_EN_FLAG HSL_RW - -#define LOOP_CHECK_TIMER -#define ADDR_TABLE_CTL_LOOP_CHECK_TIMER_BOFFSET 16 -#define ADDR_TABLE_CTL_LOOP_CHECK_TIMER_BLEN 3 -#define ADDR_TABLE_CTL_LOOP_CHECK_TIMER_FLAG HSL_RW - -#define AGE_TIME -#define ADDR_TABLE_CTL_AGE_TIME_BOFFSET 0 -#define ADDR_TABLE_CTL_AGE_TIME_BLEN 16 -#define ADDR_TABLE_CTL_AGE_TIME_FLAG HSL_RW - - - - - /* Global Forward Control0 Register */ -#define FORWARD_CTL0 -#define FORWARD_CTL0_OFFSET 0x0620 -#define FORWARD_CTL0_E_LENGTH 4 -#define FORWARD_CTL0_E_OFFSET 0 -#define FORWARD_CTL0_NR_E 1 - -#define ARP_CMD -#define FORWARD_CTL0_ARP_CMD_BOFFSET 26 -#define FORWARD_CTL0_ARP_CMD_BLEN 2 -#define FORWARD_CTL0_ARP_CMD_FLAG HSL_RW - -#define IP_NOT_FOUND -#define FORWARD_CTL0_IP_NOT_FOUND_BOFFSET 24 -#define FORWARD_CTL0_IP_NOT_FOUND_BLEN 2 -#define FORWARD_CTL0_IP_NOT_FOUND_FLAG HSL_RW - -#define ARP_NOT_FOUND -#define FORWARD_CTL0_ARP_NOT_FOUND_BOFFSET 22 -#define FORWARD_CTL0_ARP_NOT_FOUND_BLEN 2 -#define FORWARD_CTL0_ARP_NOT_FOUND_FLAG HSL_RW - -#define HASH_MODE -#define FORWARD_CTL0_HASH_MODE_BOFFSET 20 -#define FORWARD_CTL0_HASH_MODE_BLEN 2 -#define FORWARD_CTL0_HASH_MODE_FLAG HSL_RW - -#define NAT_NOT_FOUND_DROP -#define FORWARD_CTL0_NAT_NOT_FOUND_DROP_BOFFSET 17 -#define FORWARD_CTL0_NAT_NOT_FOUND_DROP_BLEN 1 -#define FORWARD_CTL0_NAT_NOT_FOUND_DROP_FLAG HSL_RW - -#define SP_NOT_FOUND_DROP -#define FORWARD_CTL0_SP_NOT_FOUND_DROP_BOFFSET 16 -#define FORWARD_CTL0_SP_NOT_FOUND_DROP_BLEN 1 -#define FORWARD_CTL0_SP_NOT_FOUND_DROP_FLAG HSL_RW - -#define IGMP_LEAVE_DROP -#define FORWARD_CTL0_IGMP_LEAVE_DROP_BOFFSET 14 -#define FORWARD_CTL0_IGMP_LEAVE_DROP_BLEN 1 -#define FORWARD_CTL0_IGMP_LEAVE_DROP_FLAG HSL_RW - -#define ARL_UNI_LEAKY -#define FORWARD_CTL0_ARL_UNI_LEAKY_BOFFSET 13 -#define FORWARD_CTL0_ARL_UNI_LEAKY_BLEN 1 -#define FORWARD_CTL0_ARL_UNI_LEAKY_FLAG HSL_RW - -#define ARL_MUL_LEAKY -#define FORWARD_CTL0_ARL_MUL_LEAKY_BOFFSET 12 -#define FORWARD_CTL0_ARL_MUL_LEAKY_BLEN 1 -#define FORWARD_CTL0_ARL_MUL_LEAKY_FLAG HSL_RW - -#define MANAGE_VID_VIO_DROP_EN -#define FORWARD_CTL0_MANAGE_VID_VIO_DROP_EN_BOFFSET 11 -#define FORWARD_CTL0_MANAGE_VID_VIO_DROP_EN_BLEN 1 -#define FORWARD_CTL0_MANAGE_VID_VIO_DROP_EN_FLAG HSL_RW - -#define CPU_PORT_EN -#define FORWARD_CTL0_CPU_PORT_EN_BOFFSET 10 -#define FORWARD_CTL0_CPU_PORT_EN_BLEN 1 -#define FORWARD_CTL0_CPU_PORT_EN_FLAG HSL_RW - -#define PPPOE_RDT_EN -#define FORWARD_CTL0_PPPOE_RDT_EN_BOFFSET 8 -#define FORWARD_CTL0_PPPOE_RDT_EN_BLEN 1 -#define FORWARD_CTL0_PPPOE_RDT_EN_FLAG HSL_RW - -#define MIRROR_PORT_NUM -#define FORWARD_CTL0_MIRROR_PORT_NUM_BOFFSET 4 -#define FORWARD_CTL0_MIRROR_PORT_NUM_BLEN 4 -#define FORWARD_CTL0_MIRROR_PORT_NUM_FLAG HSL_RW - -#define IGMP_COPY_EN -#define FORWARD_CTL0_IGMP_COPY_EN_BOFFSET 3 -#define FORWARD_CTL0_IGMP_COPY_EN_BLEN 1 -#define FORWARD_CTL0_IGMP_COPY_EN_FLAG HSL_RW - -#define RIP_CPY_EN -#define FORWARD_CTL0_RIP_CPY_EN_BOFFSET 2 -#define FORWARD_CTL0_RIP_CPY_EN_BLEN 1 -#define FORWARD_CTL0_RIP_CPY_EN_FLAG HSL_RW - -#define EAPOL_CMD -#define FORWARD_CTL0_EAPOL_CMD_BOFFSET 0 -#define FORWARD_CTL0_EAPOL_CMD_BLEN 1 -#define FORWARD_CTL0_EAPOL_CMD_FLAG HSL_RW - - /* Global Forward Control1 Register */ -#define FORWARD_CTL1 -#define FORWARD_CTL1_OFFSET 0x0624 -#define FORWARD_CTL1_E_LENGTH 4 -#define FORWARD_CTL1_E_OFFSET 0 -#define FORWARD_CTL1_NR_E 1 - -#define IGMP_DP -#define FORWARD_CTL1_IGMP_DP_BOFFSET 24 -#define FORWARD_CTL1_IGMP_DP_BLEN 7 -#define FORWARD_CTL1_IGMP_DP_FLAG HSL_RW - -#define BC_FLOOD_DP -#define FORWARD_CTL1_BC_FLOOD_DP_BOFFSET 16 -#define FORWARD_CTL1_BC_FLOOD_DP_BLEN 7 -#define FORWARD_CTL1_BC_FLOOD_DP_FLAG HSL_RW - -#define MUL_FLOOD_DP -#define FORWARD_CTL1_MUL_FLOOD_DP_BOFFSET 8 -#define FORWARD_CTL1_MUL_FLOOD_DP_BLEN 7 -#define FORWARD_CTL1_MUL_FLOOD_DP_FLAG HSL_RW - -#define UNI_FLOOD_DP -#define FORWARD_CTL1_UNI_FLOOD_DP_BOFFSET 0 -#define FORWARD_CTL1_UNI_FLOOD_DP_BLEN 7 -#define FORWARD_CTL1_UNI_FLOOD_DP_FLAG HSL_RW - - - - - /* Global Learn Limit Ctl Register */ -#define GLOBAL_LEARN_LIMIT_CTL -#define GLOBAL_LEARN_LIMIT_CTL_OFFSET 0x0628 -#define GLOBAL_LEARN_LIMIT_CTL_E_LENGTH 4 -#define GLOBAL_LEARN_LIMIT_CTL_E_OFFSET 0 -#define GLOBAL_LEARN_LIMIT_CTL_NR_E 1 - -#define GOL_SA_LEARN_LIMIT_EN -#define GLOBAL_LEARN_LIMIT_CTL_GOL_SA_LEARN_LIMIT_EN_BOFFSET 12 -#define GLOBAL_LEARN_LIMIT_CTL_GOL_SA_LEARN_LIMIT_EN_BLEN 1 -#define GLOBAL_LEARN_LIMIT_CTL_GOL_SA_LEARN_LIMIT_EN_FLAG HSL_RW - -#define GOL_SA_LEARN_LIMIT_DROP_EN -#define GLOBAL_LEARN_LIMIT_CTL_GOL_SA_LEARN_LIMIT_DROP_EN_BOFFSET 13 -#define GLOBAL_LEARN_LIMIT_CTL_GOL_SA_LEARN_LIMIT_DROP_EN_BLEN 1 -#define GLOBAL_LEARN_LIMIT_CTL_GOL_SA_LEARN_LIMIT_DROP_EN_FLAG HSL_RW - -#define GOL_SA_LEARN_CNT -#define GLOBAL_LEARN_LIMIT_CTL_GOL_SA_LEARN_CNT_BOFFSET 0 -#define GLOBAL_LEARN_LIMIT_CTL_GOL_SA_LEARN_CNT_BLEN 12 -#define GLOBAL_LEARN_LIMIT_CTL_GOL_SA_LEARN_CNT_FLAG HSL_RW - - - - - /* DSCP To Priority Register */ -#define DSCP_TO_PRI -#define DSCP_TO_PRI_OFFSET 0x0630 -#define DSCP_TO_PRI_E_LENGTH 4 -#define DSCP_TO_PRI_E_OFFSET 0x0004 -#define DSCP_TO_PRI_NR_E 8 - - - - - /* UP To Priority Register */ -#define UP_TO_PRI -#define UP_TO_PRI_OFFSET 0x0650 -#define UP_TO_PRI_E_LENGTH 4 -#define UP_TO_PRI_E_OFFSET 0x0004 -#define UP_TO_PRI_NR_E 1 - - - - - /* WAN DSCP To Priority Register */ -#define DSCP_TO_EHPRI -#define DSCP_TO_EHPRI_OFFSET 0x0730 -#define DSCP_TO_EHPRI_E_LENGTH 4 -#define DSCP_TO_EHPRI_E_OFFSET 0x0004 -#define DSCP_TO_EHPRI_NR_E 8 - - - - - /* WAN UP To Priority Register */ -#define UP_TO_EHPRI -#define UP_TO_EHPRI_OFFSET 0x0750 -#define UP_TO_EHPRI_E_LENGTH 4 -#define UP_TO_EHPRI_E_OFFSET 0x0004 -#define UP_TO_EHPRI_NR_E 1 - - - - - /* Port Lookup control Register */ -#define PORT_LOOKUP_CTL -#define PORT_LOOKUP_CTL_OFFSET 0x0660 -#define PORT_LOOKUP_CTL_E_LENGTH 4 -#define PORT_LOOKUP_CTL_E_OFFSET 0x000c -#define PORT_LOOKUP_CTL_NR_E 7 - -#define MULTI_DROP_EN -#define PORT_LOOKUP_CTL_MULTI_DROP_EN_BOFFSET 31 -#define PORT_LOOKUP_CTL_MULTI_DROP_EN_BLEN 1 -#define PORT_LOOKUP_CTL_MULTI_DROP_EN_FLAG HSL_RW - -#define UNI_LEAKY_EN -#define PORT_LOOKUP_CTL_UNI_LEAKY_EN_BOFFSET 28 -#define PORT_LOOKUP_CTL_UNI_LEAKY_EN_BLEN 1 -#define PORT_LOOKUP_CTL_UNI_LEAKY_EN_FLAG HSL_RW - -#define MUL_LEAKY_EN -#define PORT_LOOKUP_CTL_MUL_LEAKY_EN_BOFFSET 27 -#define PORT_LOOKUP_CTL_MUL_LEAKY_EN_BLEN 1 -#define PORT_LOOKUP_CTL_MUL_LEAKY_EN_FLAG HSL_RW - -#define ARP_LEAKY_EN -#define PORT_LOOKUP_CTL_ARP_LEAKY_EN_BOFFSET 26 -#define PORT_LOOKUP_CTL_ARP_LEAKY_EN_BLEN 1 -#define PORT_LOOKUP_CTL_ARP_LEAKY_EN_FLAG HSL_RW - -#define ING_MIRROR_EN -#define PORT_LOOKUP_CTL_ING_MIRROR_EN_BOFFSET 25 -#define PORT_LOOKUP_CTL_ING_MIRROR_EN_BLEN 1 -#define PORT_LOOKUP_CTL_ING_MIRROR_EN_FLAG HSL_RW - -#define PORT_LOOP_BACK -#define PORT_LOOKUP_CTL_PORT_LOOP_BACK_BOFFSET 21 -#define PORT_LOOKUP_CTL_PORT_LOOP_BACK_BLEN 1 -#define PORT_LOOKUP_CTL_PORT_LOOP_BACK_FLAG HSL_RW - -#define LEARN_EN -#define PORT_LOOKUP_CTL_LEARN_EN_BOFFSET 20 -#define PORT_LOOKUP_CTL_LEARN_EN_BLEN 1 -#define PORT_LOOKUP_CTL_LEARN_EN_FLAG HSL_RW - -#define PORT_STATE -#define PORT_LOOKUP_CTL_PORT_STATE_BOFFSET 16 -#define PORT_LOOKUP_CTL_PORT_STATE_BLEN 3 -#define PORT_LOOKUP_CTL_PORT_STATE_FLAG HSL_RW - -#define FORCE_PVLAN -#define PORT_LOOKUP_CTL_FORCE_PVLAN_BOFFSET 10 -#define PORT_LOOKUP_CTL_FORCE_PVLAN_BLEN 1 -#define PORT_LOOKUP_CTL_FORCE_PVLAN_FLAG HSL_RW - -#define DOT1Q_MODE -#define PORT_LOOKUP_CTL_DOT1Q_MODE_BOFFSET 8 -#define PORT_LOOKUP_CTL_DOT1Q_MODE_BLEN 2 -#define PORT_LOOKUP_CTL_DOT1Q_MODE_FLAG HSL_RW - -#define PORT_VID_MEM -#define PORT_LOOKUP_CTL_PORT_VID_MEM_BOFFSET 0 -#define PORT_LOOKUP_CTL_PORT_VID_MEM_BLEN 7 -#define PORT_LOOKUP_CTL_PORT_VID_MEM_FLAG HSL_RW - - - - - /* Priority Control Register */ -#define PRI_CTL -#define PRI_CTL_OFFSET 0x0664 -#define PRI_CTL_E_LENGTH 4 -#define PRI_CTL_E_OFFSET 0x000c -#define PRI_CTL_NR_E 7 - -#define EG_MAC_BASE_VLAN_EN -#define PRI_CTL_EG_MAC_BASE_VLAN_EN_BOFFSET 20 -#define PRI_CTL_EG_MAC_BASE_VLAN_EN_BLEN 1 -#define PRI_CTL_EG_MAC_BASE_VLAN_EN_FLAG HSL_RW - -#define FLOW_PRI_EN -#define PRI_CTL_FLOW_PRI_EN_BOFFSET 19 -#define PRI_CTL_FLOW_PRI_EN_BLEN 1 -#define PRI_CTL_FLOW_PRI_EN_FLAG HSL_RW - -#define DA_PRI_EN -#define PRI_CTL_DA_PRI_EN_BOFFSET 18 -#define PRI_CTL_DA_PRI_EN_BLEN 1 -#define PRI_CTL_DA_PRI_EN_FLAG HSL_RW - -#define VLAN_PRI_EN -#define PRI_CTL_VLAN_PRI_EN_BOFFSET 17 -#define PRI_CTL_VLAN_PRI_EN_BLEN 1 -#define PRI_CTL_VLAN_PRI_EN_FLAG HSL_RW - -#define IP_PRI_EN -#define PRI_CTL_IP_PRI_EN_BOFFSET 16 -#define PRI_CTL_IP_PRI_EN_BLEN 1 -#define PRI_CTL_IP_PRI_EN_FLAG HSL_RW - -#define FLOW_PRI_SEL -#define PRI_CTL_FLOW_PRI_SEL_BOFFSET 8 -#define PRI_CTL_FLOW_PRI_SEL_BLEN 2 -#define PRI_CTL_FLOW_PRI_SEL_FLAG HSL_RW - -#define DA_PRI_SEL -#define PRI_CTL_DA_PRI_SEL_BOFFSET 6 -#define PRI_CTL_DA_PRI_SEL_BLEN 2 -#define PRI_CTL_DA_PRI_SEL_FLAG HSL_RW - -#define VLAN_PRI_SEL -#define PRI_CTL_VLAN_PRI_SEL_BOFFSET 4 -#define PRI_CTL_VLAN_PRI_SEL_BLEN 2 -#define PRI_CTL_VLAN_PRI_SEL_FLAG HSL_RW - -#define IP_PRI_SEL -#define PRI_CTL_IP_PRI_SEL_BOFFSET 2 -#define PRI_CTL_IP_PRI_SEL_BLEN 2 -#define PRI_CTL_IP_PRI_SEL_FLAG HSL_RW - - - - /* Port Learn Limit Ctl Register */ -#define PORT_LEARN_LIMIT_CTL -#define PORT_LEARN_LIMIT_CTL_OFFSET 0x0668 -#define PORT_LEARN_LIMIT_CTL_E_LENGTH 4 -#define PORT_LEARN_LIMIT_CTL_E_OFFSET 0x000c -#define PORT_LEARN_LIMIT_CTL_NR_E 7 - -#define IGMP_JOIN_LIMIT_DROP_EN -#define PORT_LEARN_LIMIT_CTL_IGMP_JOIN_LIMIT_DROP_EN_BOFFSET 29 -#define PORT_LEARN_LIMIT_CTL_IGMP_JOIN_LIMIT_DROP_EN_BLEN 1 -#define PORT_LEARN_LIMIT_CTL_IGMP_JOIN_LIMIT_DROP_EN_FLAG HSL_RW - -#define SA_LEARN_LIMIT_DROP_EN -#define PORT_LEARN_LIMIT_CTL_SA_LEARN_LIMIT_DROP_EN_BOFFSET 28 -#define PORT_LEARN_LIMIT_CTL_SA_LEARN_LIMIT_DROP_EN_BLEN 1 -#define PORT_LEARN_LIMIT_CTL_SA_LEARN_LIMIT_DROP_EN_FLAG HSL_RW - -#define IGMP_JOIN_LIMIT_EN -#define PORT_LEARN_LIMIT_CTL_IGMP_JOIN_LIMIT_EN_BOFFSET 27 -#define PORT_LEARN_LIMIT_CTL_IGMP_JOIN_LIMIT_EN_BLEN 1 -#define PORT_LEARN_LIMIT_CTL_IGMP_JOIN_LIMIT_EN_FLAG HSL_RW - -#define IGMP_JOIN_CNT -#define PORT_LEARN_LIMIT_CTL_IGMP_JOIN_CNT_BOFFSET 16 -#define PORT_LEARN_LIMIT_CTL_IGMP_JOIN_CNT_BLEN 11 -#define PORT_LEARN_LIMIT_CTL_IGMP_JOIN_CNT_FLAG HSL_RW - -#define SA_LEARN_STATUS -#define PORT_LEARN_LIMIT_CTL_SA_LEARN_STATUS_BOFFSET 12 -#define PORT_LEARN_LIMIT_CTL_SA_LEARN_STATUS_BLEN 4 -#define PORT_LEARN_LIMIT_CTL_SA_LEARN_STATUS_FLAG HSL_RW - -#define SA_LEARN_LIMIT_EN -#define PORT_LEARN_LIMIT_CTL_SA_LEARN_LIMIT_EN_BOFFSET 11 -#define PORT_LEARN_LIMIT_CTL_SA_LEARN_LIMIT_EN_BLEN 1 -#define PORT_LEARN_LIMIT_CTL_SA_LEARN_LIMIT_EN_FLAG HSL_RW - -#define SA_LEARN_CNT -#define PORT_LEARN_LIMIT_CTL_SA_LEARN_CNT_BOFFSET 0 -#define PORT_LEARN_LIMIT_CTL_SA_LEARN_CNT_BLEN 11 -#define PORT_LEARN_LIMIT_CTL_SA_LEARN_CNT_FLAG HSL_RW - - - - /* Global Trunk Ctl0 Register */ -#define GOL_TRUNK_CTL0 -#define GOL_TRUNK_CTL0_OFFSET 0x0700 -#define GOL_TRUNK_CTL0_E_LENGTH 4 -#define GOL_TRUNK_CTL0_E_OFFSET 0x4 -#define GOL_TRUNK_CTL0_NR_E 1 - - - /* Global Trunk Ctl1 Register */ -#define GOL_TRUNK_CTL1 -#define GOL_TRUNK_CTL1_OFFSET 0x0704 -#define GOL_TRUNK_CTL1_E_LENGTH 4 -#define GOL_TRUNK_CTL1_E_OFFSET 0x4 -#define GOL_TRUNK_CTL1_NR_E 2 - - - /* ACL Forward source filter Register */ -#define ACL_FWD_SRC_FILTER_CTL0 -#define ACL_FWD_SRC_FILTER_CTL0_OFFSET 0x0710 -#define ACL_FWD_SRC_FILTER_CTL0_E_LENGTH 4 -#define ACL_FWD_SRC_FILTER_CTL0_E_OFFSET 0x4 -#define ACL_FWD_SRC_FILTER_CTL0_NR_E 3 - - - /* VLAN translation register */ -#define VLAN_TRANS -#define VLAN_TRANS_OFFSET 0x0418 -#define VLAN_TRANS_E_LENGTH 4 -#define VLAN_TRANS_E_OFFSET 0 -#define VLAN_TRANS_NR_E 7 - -#define EG_FLTR_BYPASS_EN -#define VLAN_TRANS_EG_FLTR_BYPASS_EN_BOFFSET 1 -#define VLAN_TRANS_EG_FLTR_BYPASS_EN_BLEN 1 -#define VLAN_TRANS_EG_FLTR_BYPASS_EN_FLAG HSL_RW - -#define NET_ISO -#define VLAN_TRANS_NET_ISO_BOFFSET 0 -#define VLAN_TRANS_NET_ISO_BLEN 1 -#define VLAN_TRANS_NET_ISO_FLAG HSL_RW - - - /* Port vlan0 Register */ -#define PORT_VLAN0 -#define PORT_VLAN0_OFFSET 0x0420 -#define PORT_VLAN0_E_LENGTH 4 -#define PORT_VLAN0_E_OFFSET 0x0008 -#define PORT_VLAN0_NR_E 7 - -#define ING_CPRI -#define PORT_VLAN0_ING_CPRI_BOFFSET 29 -#define PORT_VLAN0_ING_CPRI_BLEN 3 -#define PORT_VLAN0_ING_CPRI_FLAG HSL_RW - -#define ING_FORCE_CPRI -#define PORT_VLAN0_ING_FORCE_CPRI_BOFFSET 28 -#define PORT_VLAN0_ING_FORCE_CPRI_BLEN 1 -#define PORT_VLAN0_ING_FORCE_CPRI_FLAG HSL_RW - -#define DEF_CVID -#define PORT_VLAN0_DEF_CVID_BOFFSET 16 -#define PORT_VLAN0_DEF_CVID_BLEN 12 -#define PORT_VLAN0_DEF_CVID_FLAG HSL_RW - -#define ING_SPRI -#define PORT_VLAN0_ING_SPRI_BOFFSET 13 -#define PORT_VLAN0_ING_SPRI_BLEN 3 -#define PORT_VLAN0_ING_SPRI_FLAG HSL_RW - -#define ING_FORCE_SPRI -#define PORT_VLAN0_ING_FORCE_SPRI_BOFFSET 12 -#define PORT_VLAN0_ING_FORCE_SPRI_BLEN 1 -#define PORT_VLAN0_ING_FORCE_SPRI_FLAG HSL_RW - -#define DEF_SVID -#define PORT_VLAN0_DEF_SVID_BOFFSET 0 -#define PORT_VLAN0_DEF_SVID_BLEN 12 -#define PORT_VLAN0_DEF_SVID_FLAG HSL_RW - - /* Port vlan1 Register */ -#define PORT_VLAN1 -#define PORT_VLAN1_OFFSET 0x0424 -#define PORT_VLAN1_E_LENGTH 4 -#define PORT_VLAN1_E_OFFSET 0x0008 -#define PORT_VLAN1_NR_E 7 - -#define VRF_ID -#define PORT_VLAN1_VRF_ID_BOFFSET 15 -#define PORT_VLAN1_VRF_ID_BLEN 3 -#define PORT_VLAN1_VRF_ID_FLAG HSL_RW - -#define EG_VLAN_MODE -#define PORT_VLAN1_EG_VLAN_MODE_BOFFSET 12 -#define PORT_VLAN1_EG_VLAN_MODE_BLEN 2 -#define PORT_VLAN1_EG_VLAN_MODE_FLAG HSL_RW - -#define VLAN_DIS -#define PORT_VLAN1_VLAN_DIS_BOFFSET 11 -#define PORT_VLAN1_VLAN_DIS_BLEN 1 -#define PORT_VLAN1_VLAN_DIS_FLAG HSL_RW - -#define SP_CHECK_EN -#define PORT_VLAN1_SP_CHECK_EN_BOFFSET 10 -#define PORT_VLAN1_SP_CHECK_EN_BLEN 1 -#define PORT_VLAN1_SP_CHECK_EN_FLAG HSL_RW - -#define COREP_EN -#define PORT_VLAN1_COREP_EN_BOFFSET 9 -#define PORT_VLAN1_COREP_EN_BLEN 1 -#define PORT_VLAN1_COREP_EN_FLAG HSL_RW - -#define FORCE_DEF_VID -#define PORT_VLAN1_FORCE_DEF_VID_BOFFSET 8 -#define PORT_VLAN1_FORCE_DEF_VID_BLEN 1 -#define PORT_VLAN1_FORCE_DEF_VID_FLAG HSL_RW - -#define TLS_EN -#define PORT_VLAN1_TLS_EN_BOFFSET 7 -#define PORT_VLAN1_TLS_EN_BLEN 1 -#define PORT_VLAN1_TLS_EN_FLAG HSL_RW - -#define PROPAGATION_EN -#define PORT_VLAN1_PROPAGATION_EN_BOFFSET 6 -#define PORT_VLAN1_PROPAGATION_EN_BLEN 1 -#define PORT_VLAN1_PROPAGATION_EN_FLAG HSL_RW - -#define CLONE -#define PORT_VLAN1_CLONE_BOFFSET 5 -#define PORT_VLAN1_CLONE_BLEN 1 -#define PORT_VLAN1_CLONE_FLAG HSL_RW - -#define PRI_PROPAGATION -#define PORT_VLAN1_PRI_PROPAGATION_BOFFSET 4 -#define PORT_VLAN1_PRI_PROPAGATION_BLEN 1 -#define PORT_VLAN1_VLAN_PRI_PROPAGATION_FLAG HSL_RW - -#define IN_VLAN_MODE -#define PORT_VLAN1_IN_VLAN_MODE_BOFFSET 2 -#define PORT_VLAN1_IN_VLAN_MODE_BLEN 2 -#define PORT_VLAN1_IN_VLAN_MODE_FLAG HSL_RW - - - /* Route Default VID Register */ -#define ROUTER_DEFV -#define ROUTER_DEFV_OFFSET 0x0c70 -#define ROUTER_DEFV_E_LENGTH 4 -#define ROUTER_DEFV_E_OFFSET 0x0004 -#define ROUTER_DEFV_NR_E 4 - - - /* Route Egress VLAN Mode Register */ -#define ROUTER_EG -#define ROUTER_EG_OFFSET 0x0c80 -#define ROUTER_EG_E_LENGTH 4 -#define ROUTER_EG_E_OFFSET 0x0004 -#define ROUTER_EG_NR_E 1 - -/* port flow control threshold Register */ -#define PORT_FLOC_CTRL_THRESH -#define PORT_FLOC_CTRL_THRESH_OFFSET 0x9b0 -#define PORT_FLOC_CTRL_THRESH_E_LENGTH 4 -#define PORT_FLOC_CTRL_THRESH_E_OFFSET 0x0004 -#define PORT_FLOC_CTRL_THRESH_NR_E 7 - - - /* LED control Register */ -#define LED_CTRL "ledctrl" -#define LED_CTRL_ID 25 -#define LED_CTRL_OFFSET 0x0050 -#define LED_CTRL_E_LENGTH 4 -#define LED_CTRL_E_OFFSET 0 -#define LED_CTRL_NR_E 3 - -#define PATTERN_EN "lctrl_pen" -#define LED_CTRL_PATTERN_EN_BOFFSET 14 -#define LED_CTRL_PATTERN_EN_BLEN 2 -#define LED_CTRL_PATTERN_EN_FLAG HSL_RW - -#define FULL_LIGHT_EN "lctrl_fen" -#define LED_CTRL_FULL_LIGHT_EN_BOFFSET 13 -#define LED_CTRL_FULL_LIGHT_EN_BLEN 1 -#define LED_CTRL_FULL_LIGHT_EN_FLAG HSL_RW - -#define HALF_LIGHT_EN "lctrl_hen" -#define LED_CTRL_HALF_LIGHT_EN_BOFFSET 12 -#define LED_CTRL_HALF_LIGHT_EN_BLEN 1 -#define LED_CTRL_HALF_LIGHT_EN_FLAG HSL_RW - -#define POWERON_LIGHT_EN "lctrl_poen" -#define LED_CTRL_POWERON_LIGHT_EN_BOFFSET 11 -#define LED_CTRL_POWERON_LIGHT_EN_BLEN 1 -#define LED_CTRL_POWERON_LIGHT_EN_FLAG HSL_RW - -#define GE_LIGHT_EN "lctrl_geen" -#define LED_CTRL_GE_LIGHT_EN_BOFFSET 10 -#define LED_CTRL_GE_LIGHT_EN_BLEN 1 -#define LED_CTRL_GE_LIGHT_EN_FLAG HSL_RW - -#define FE_LIGHT_EN "lctrl_feen" -#define LED_CTRL_FE_LIGHT_EN_BOFFSET 9 -#define LED_CTRL_FE_LIGHT_EN_BLEN 1 -#define LED_CTRL_FE_LIGHT_EN_FLAG HSL_RW - -#define ETH_LIGHT_EN "lctrl_ethen" -#define LED_CTRL_ETH_LIGHT_EN_BOFFSET 8 -#define LED_CTRL_ETH_LIGHT_EN_BLEN 1 -#define LED_CTRL_ETH_LIGHT_EN_FLAG HSL_RW - -#define COL_BLINK_EN "lctrl_cen" -#define LED_CTRL_COL_BLINK_EN_BOFFSET 7 -#define LED_CTRL_COL_BLINK_EN_BLEN 1 -#define LED_CTRL_COL_BLINK_EN_FLAG HSL_RW - -#define RX_BLINK_EN "lctrl_rxen" -#define LED_CTRL_RX_BLINK_EN_BOFFSET 5 -#define LED_CTRL_RX_BLINK_EN_BLEN 1 -#define LED_CTRL_RX_BLINK_EN_FLAG HSL_RW - -#define TX_BLINK_EN "lctrl_txen" -#define LED_CTRL_TX_BLINK_EN_BOFFSET 4 -#define LED_CTRL_TX_BLINK_EN_BLEN 1 -#define LED_CTRL_TX_BLINK_EN_FLAG HSL_RW - -#define LINKUP_OVER_EN "lctrl_loen" -#define LED_CTRL_LINKUP_OVER_EN_BOFFSET 2 -#define LED_CTRL_LINKUP_OVER_EN_BLEN 1 -#define LED_CTRL_LINKUP_OVER_EN_FLAG HSL_RW - -#define BLINK_FREQ "lctrl_bfreq" -#define LED_CTRL_BLINK_FREQ_BOFFSET 0 -#define LED_CTRL_BLINK_FREQ_BLEN 2 -#define LED_CTRL_BLINK_FREQ_FLAG HSL_RW - - /* LED control Register */ -#define LED_PATTERN "ledpatten" -#define LED_PATTERN_ID 25 -#define LED_PATTERN_OFFSET 0x005c -#define LED_PATTERN_E_LENGTH 4 -#define LED_PATTERN_E_OFFSET 0 -#define LED_PATTERN_NR_E 1 - - -#define P3L2_MODE -#define LED_PATTERN_P3L2_MODE_BOFFSET 24 -#define LED_PATTERN_P3L2_MODE_BLEN 2 -#define LED_PATTERN_P3L2_MODE_FLAG HSL_RW - -#define P3L1_MODE -#define LED_PATTERN_P3L1_MODE_BOFFSET 22 -#define LED_PATTERN_P3L1_MODE_BLEN 2 -#define LED_PATTERN_P3L1_MODE_FLAG HSL_RW - -#define P3L0_MODE -#define LED_PATTERN_P3L0_MODE_BOFFSET 20 -#define LED_PATTERN_P3L0_MODE_BLEN 2 -#define LED_PATTERN_P3L0_MODE_FLAG HSL_RW - -#define P2L2_MODE -#define LED_PATTERN_P2L2_MODE_BOFFSET 18 -#define LED_PATTERN_P2L2_MODE_BLEN 2 -#define LED_PATTERN_P2L2_MODE_FLAG HSL_RW - -#define P2L1_MODE -#define LED_PATTERN_P2L1_MODE_BOFFSET 16 -#define LED_PATTERN_P2L1_MODE_BLEN 2 -#define LED_PATTERN_P2L1_MODE_FLAG HSL_RW - -#define P2L0_MODE -#define LED_PATTERN_P2L0_MODE_BOFFSET 14 -#define LED_PATTERN_P2L0_MODE_BLEN 2 -#define LED_PATTERN_P2L0_MODE_FLAG HSL_RW - -#define P1L2_MODE -#define LED_PATTERN_P1L2_MODE_BOFFSET 12 -#define LED_PATTERN_P1L2_MODE_BLEN 2 -#define LED_PATTERN_P1L2_MODE_FLAG HSL_RW - -#define P1L1_MODE -#define LED_PATTERN_P1L1_MODE_BOFFSET 10 -#define LED_PATTERN_P1L1_MODE_BLEN 2 -#define LED_PATTERN_P1L1_MODE_FLAG HSL_RW - -#define P1L0_MODE -#define LED_PATTERN_P1L0_MODE_BOFFSET 8 -#define LED_PATTERN_P1L0_MODE_BLEN 2 -#define LED_PATTERN_P1L0_MODE_FLAG HSL_RW - - - - - /* Pri To Queue Register */ -#define PRI_TO_QUEUE -#define PRI_TO_QUEUE_OFFSET 0x0814 -#define PRI_TO_QUEUE_E_LENGTH 4 -#define PRI_TO_QUEUE_E_OFFSET 0x0004 -#define PRI_TO_QUEUE_NR_E 1 - - - - - /* Pri To EhQueue Register */ -#define PRI_TO_EHQUEUE -#define PRI_TO_EHQUEUE_OFFSET 0x0810 -#define PRI_TO_EHQUEUE_E_LENGTH 4 -#define PRI_TO_EHQUEUE_E_OFFSET 0x0004 -#define PRI_TO_EHQUEUE_NR_E 1 - - - - - /*Global Flow Control Register*/ -#define QM_CTRL_REG -#define QM_CTRL_REG_OFFSET 0X0808 -#define QM_CTRL_REG_E_LENGTH 4 -#define QM_CTRL_REG_E_OFFSET 0x0004 -#define QM_CTRL_REG_NR_E 1 - -#define GOL_FLOW_EN -#define QM_CTRL_REG_GOL_FLOW_EN_BOFFSET 16 -#define QM_CTRL_REG_GOL_FLOW_EN_BLEN 7 -#define QM_CTRL_REG_GOL_FLOW_EN_FLAG HSL_RW - -#define QM_FUNC_TEST -#define QM_CTRL_REG_QM_FUNC_TEST_BOFFSET 10 -#define QM_CTRL_REG_QM_FUNC_TEST_BLEN 1 -#define QM_CTRL_REG_QM_FUNC_TEST_FLAG HSL_RW - -#define RATE_DROP_EN -#define QM_CTRL_REG_RATE_DROP_EN_BOFFSET 7 -#define QM_CTRL_REG_RATE_DROP_EN_BLEN 1 -#define QM_CTRL_REG_RATE_DROP_EN_FLAG HSL_RW - -#define FLOW_DROP_EN -#define QM_CTRL_REG_FLOW_DROP_EN_BOFFSET 6 -#define QM_CTRL_REG_FLOW_DROP_EN_BLEN 1 -#define QM_CTRL_REG_FLOW_DROP_EN_FLAG HSL_RW - -#define FLOW_DROP_CNT -#define QM_CTRL_REG_FLOW_DROP_CNT_BOFFSET 0 -#define QM_CTRL_REG_FLOW_DROP_CNT_BLEN 6 -#define QM_CTRL_REG_FLOW_DROP_CNT_FLAG HSL_RW - - - - - /* Port HOL CTL0 Register */ -#define PORT_HOL_CTL0 -#define PORT_HOL_CTL0_OFFSET 0x0970 -#define PORT_HOL_CTL0_E_LENGTH 4 -#define PORT_HOL_CTL0_E_OFFSET 0x0008 -#define PORT_HOL_CTL0_NR_E 7 - -#define PORT_DESC_NR -#define PORT_HOL_CTL0_PORT_DESC_NR_BOFFSET 24 -#define PORT_HOL_CTL0_PORT_DESC_NR_BLEN 6 -#define PORT_HOL_CTL0_PORT_DESC_NR_FLAG HSL_RW - -#define QUEUE5_DESC_NR -#define PORT_HOL_CTL0_QUEUE5_DESC_NR_BOFFSET 20 -#define PORT_HOL_CTL0_QUEUE5_DESC_NR_BLEN 4 -#define PORT_HOL_CTL0_QUEUE5_DESC_NR_FLAG HSL_RW - -#define QUEUE4_DESC_NR -#define PORT_HOL_CTL0_QUEUE4_DESC_NR_BOFFSET 16 -#define PORT_HOL_CTL0_QUEUE4_DESC_NR_BLEN 4 -#define PORT_HOL_CTL0_QUEUE4_DESC_NR_FLAG HSL_RW - -#define QUEUE3_DESC_NR -#define PORT_HOL_CTL0_QUEUE3_DESC_NR_BOFFSET 12 -#define PORT_HOL_CTL0_QUEUE3_DESC_NR_BLEN 4 -#define PORT_HOL_CTL0_QUEUE3_DESC_NR_FLAG HSL_RW - -#define QUEUE2_DESC_NR -#define PORT_HOL_CTL0_QUEUE2_DESC_NR_BOFFSET 8 -#define PORT_HOL_CTL0_QUEUE2_DESC_NR_BLEN 4 -#define PORT_HOL_CTL0_QUEUE2_DESC_NR_FLAG HSL_RW - -#define QUEUE1_DESC_NR -#define PORT_HOL_CTL0_QUEUE1_DESC_NR_BOFFSET 4 -#define PORT_HOL_CTL0_QUEUE1_DESC_NR_BLEN 4 -#define PORT_HOL_CTL0_QUEUE1_DESC_NR_FLAG HSL_RW - -#define QUEUE0_DESC_NR -#define PORT_HOL_CTL0_QUEUE0_DESC_NR_BOFFSET 0 -#define PORT_HOL_CTL0_QUEUE0_DESC_NR_BLEN 4 -#define PORT_HOL_CTL0_QUEUE0_DESC_NR_FLAG HSL_RW - - /* Port HOL CTL1 Register */ -#define PORT_HOL_CTL1 -#define PORT_HOL_CTL1_OFFSET 0x0974 -#define PORT_HOL_CTL1_E_LENGTH 4 -#define PORT_HOL_CTL1_E_OFFSET 0x0008 -#define PORT_HOL_CTL1_NR_E 7 - -#define EG_MIRROR_EN -#define PORT_HOL_CTL1_EG_MIRROR_EN_BOFFSET 16 -#define PORT_HOL_CTL1_EG_MIRROR_EN_BLEN 1 -#define PORT_HOL_CTL1_EG_MIRROR_EN_FLAG HSL_RW - -#define PORT_RED_EN -#define PORT_HOL_CTL1_PORT_RED_EN_BOFFSET 8 -#define PORT_HOL_CTL1_PORT_RED_EN_BLEN 1 -#define PORT_HOL_CTL1_PORT_RED_EN_FLAG HSL_RW - -#define PORT_DESC_EN -#define PORT_HOL_CTL1_PORT_DESC_EN_BOFFSET 7 -#define PORT_HOL_CTL1_PORT_DESC_EN_BLEN 1 -#define PORT_HOL_CTL1_PORT_DESC_EN_FLAG HSL_RW - -#define QUEUE_DESC_EN -#define PORT_HOL_CTL1_QUEUE_DESC_EN_BOFFSET 6 -#define PORT_HOL_CTL1_QUEUE_DESC_EN_BLEN 1 -#define PORT_HOL_CTL1_QUEUE_DESC_EN_FLAG HSL_RW - -#define PORT_IN_DESC_EN -#define PORT_HOL_CTL1_PORT_IN_DESC_EN_BOFFSET 0 -#define PORT_HOL_CTL1_PORT_IN_DESC_EN_BLEN 4 -#define PORT_HOL_CTL1_PORT_IN_DESC_EN_FLAG HSL_RW - - - /* PKT edit control register */ -#define PKT_CTRL -#define PKT_CTRL_OFFSET 0x0c00 -#define PKT_CTRL_E_LENGTH 4 -#define PKT_CTRL_E_OFFSET 0 -#define PKT_CTRL_NR_E 7 - -#define CPU_VID_EN -#define PKT_CTRL_CPU_VID_EN_BOFFSET 1 -#define PKT_CTRL_CPU_VID_EN_BLEN 1 -#define PKT_CTRL_CPU_VID_EN_FLAG HSL_RW - - -#define RTD_PPPOE_EN -#define PKT_CTRL_RTD_PPPOE_EN_BOFFSET 0 -#define PKT_CTRL_RTD_PPPOE_EN_BLEN 1 -#define PKT_CTRL_RTD_PPPOE_EN_FLAG HSL_RW - - - - - /* mib memory info */ -#define MIB_RXBROAD -#define MIB_RXBROAD_OFFSET 0x01000 -#define MIB_RXBROAD_E_LENGTH 4 -#define MIB_RXBROAD_E_OFFSET 0x100 -#define MIB_RXBROAD_NR_E 7 - -#define MIB_RXPAUSE -#define MIB_RXPAUSE_OFFSET 0x01004 -#define MIB_RXPAUSE_E_LENGTH 4 -#define MIB_RXPAUSE_E_OFFSET 0x100 -#define MIB_RXPAUSE_NR_E 7 - -#define MIB_RXMULTI -#define MIB_RXMULTI_OFFSET 0x01008 -#define MIB_RXMULTI_E_LENGTH 4 -#define MIB_RXMULTI_E_OFFSET 0x100 -#define MIB_RXMULTI_NR_E 7 - -#define MIB_RXFCSERR -#define MIB_RXFCSERR_OFFSET 0x0100c -#define MIB_RXFCSERR_E_LENGTH 4 -#define MIB_RXFCSERR_E_OFFSET 0x100 -#define MIB_RXFCSERR_NR_E 7 - -#define MIB_RXALLIGNERR -#define MIB_RXALLIGNERR_OFFSET 0x01010 -#define MIB_RXALLIGNERR_E_LENGTH 4 -#define MIB_RXALLIGNERR_E_OFFSET 0x100 -#define MIB_RXALLIGNERR_NR_E 7 - -#define MIB_RXRUNT -#define MIB_RXRUNT_OFFSET 0x01014 -#define MIB_RXRUNT_E_LENGTH 4 -#define MIB_RXRUNT_E_OFFSET 0x100 -#define MIB_RXRUNT_NR_E 7 - -#define MIB_RXFRAGMENT -#define MIB_RXFRAGMENT_OFFSET 0x01018 -#define MIB_RXFRAGMENT_E_LENGTH 4 -#define MIB_RXFRAGMENT_E_OFFSET 0x100 -#define MIB_RXFRAGMENT_NR_E 7 - -#define MIB_RX64BYTE -#define MIB_RX64BYTE_OFFSET 0x0101c -#define MIB_RX64BYTE_E_LENGTH 4 -#define MIB_RX64BYTE_E_OFFSET 0x100 -#define MIB_RX64BYTE_NR_E 7 - -#define MIB_RX128BYTE -#define MIB_RX128BYTE_OFFSET 0x01020 -#define MIB_RX128BYTE_E_LENGTH 4 -#define MIB_RX128BYTE_E_OFFSET 0x100 -#define MIB_RX128BYTE_NR_E 7 - -#define MIB_RX256BYTE -#define MIB_RX256BYTE_OFFSET 0x01024 -#define MIB_RX256BYTE_E_LENGTH 4 -#define MIB_RX256BYTE_E_OFFSET 0x100 -#define MIB_RX256BYTE_NR_E 7 - -#define MIB_RX512BYTE -#define MIB_RX512BYTE_OFFSET 0x01028 -#define MIB_RX512BYTE_E_LENGTH 4 -#define MIB_RX512BYTE_E_OFFSET 0x100 -#define MIB_RX512BYTE_NR_E 7 - -#define MIB_RX1024BYTE -#define MIB_RX1024BYTE_OFFSET 0x0102c -#define MIB_RX1024BYTE_E_LENGTH 4 -#define MIB_RX1024BYTE_E_OFFSET 0x100 -#define MIB_RX1024BYTE_NR_E 7 - -#define MIB_RX1518BYTE -#define MIB_RX1518BYTE_OFFSET 0x01030 -#define MIB_RX1518BYTE_E_LENGTH 4 -#define MIB_RX1518BYTE_E_OFFSET 0x100 -#define MIB_RX1518BYTE_NR_E 7 - -#define MIB_RXMAXBYTE -#define MIB_RXMAXBYTE_OFFSET 0x01034 -#define MIB_RXMAXBYTE_E_LENGTH 4 -#define MIB_RXMAXBYTE_E_OFFSET 0x100 -#define MIB_RXMAXBYTE_NR_E 7 - -#define MIB_RXTOOLONG -#define MIB_RXTOOLONG_OFFSET 0x01038 -#define MIB_RXTOOLONG_E_LENGTH 4 -#define MIB_RXTOOLONG_E_OFFSET 0x100 -#define MIB_RXTOOLONG_NR_E 7 - -#define MIB_RXGOODBYTE_LO -#define MIB_RXGOODBYTE_LO_OFFSET 0x0103c -#define MIB_RXGOODBYTE_LO_E_LENGTH 4 -#define MIB_RXGOODBYTE_LO_E_OFFSET 0x100 -#define MIB_RXGOODBYTE_LO_NR_E 7 - -#define MIB_RXGOODBYTE_HI -#define MIB_RXGOODBYTE_HI_OFFSET 0x01040 -#define MIB_RXGOODBYTE_HI_E_LENGTH 4 -#define MIB_RXGOODBYTE_HI_E_OFFSET 0x100 -#define MIB_RXGOODBYTE_HI_NR_E 7 - -#define MIB_RXBADBYTE_LO -#define MIB_RXBADBYTE_LO_OFFSET 0x01044 -#define MIB_RXBADBYTE_LO_E_LENGTH 4 -#define MIB_RXBADBYTE_LO_E_OFFSET 0x100 -#define MIB_RXBADBYTE_LO_NR_E 7 - -#define MIB_RXBADBYTE_HI -#define MIB_RXBADBYTE_HI_OFFSET 0x01048 -#define MIB_RXBADBYTE_HI_E_LENGTH 4 -#define MIB_RXBADBYTE_HI_E_OFFSET 0x100 -#define MIB_RXBADBYTE_HI_NR_E 7 - -#define MIB_RXOVERFLOW -#define MIB_RXOVERFLOW_OFFSET 0x0104c -#define MIB_RXOVERFLOW_E_LENGTH 4 -#define MIB_RXOVERFLOW_E_OFFSET 0x100 -#define MIB_RXOVERFLOW_NR_E 7 - -#define MIB_FILTERED -#define MIB_FILTERED_OFFSET 0x01050 -#define MIB_FILTERED_E_LENGTH 4 -#define MIB_FILTERED_E_OFFSET 0x100 -#define MIB_FILTERED_NR_E 7 - -#define MIB_TXBROAD -#define MIB_TXBROAD_OFFSET 0x01054 -#define MIB_TXBROAD_E_LENGTH 4 -#define MIB_TXBROAD_E_OFFSET 0x100 -#define MIB_TXBROAD_NR_E 7 - -#define MIB_TXPAUSE -#define MIB_TXPAUSE_OFFSET 0x01058 -#define MIB_TXPAUSE_E_LENGTH 4 -#define MIB_TXPAUSE_E_OFFSET 0x100 -#define MIB_TXPAUSE_NR_E 7 - -#define MIB_TXMULTI -#define MIB_TXMULTI_OFFSET 0x0105c -#define MIB_TXMULTI_E_LENGTH 4 -#define MIB_TXMULTI_E_OFFSET 0x100 -#define MIB_TXMULTI_NR_E 7 - -#define MIB_TXUNDERRUN -#define MIB_TXUNDERRUN_OFFSET 0x01060 -#define MIB_TXUNDERRUN_E_LENGTH 4 -#define MIB_TXUNDERRUN_E_OFFSET 0x100 -#define MIB_TXUNDERRUN_NR_E 7 - -#define MIB_TX64BYTE -#define MIB_TX64BYTE_OFFSET 0x01064 -#define MIB_TX64BYTE_E_LENGTH 4 -#define MIB_TX64BYTE_E_OFFSET 0x100 -#define MIB_TX64BYTE_NR_E 7 - -#define MIB_TX128BYTE -#define MIB_TX128BYTE_OFFSET 0x01068 -#define MIB_TX128BYTE_E_LENGTH 4 -#define MIB_TX128BYTE_E_OFFSET 0x100 -#define MIB_TX128BYTE_NR_E 7 - -#define MIB_TX256BYTE -#define MIB_TX256BYTE_OFFSET 0x0106c -#define MIB_TX256BYTE_E_LENGTH 4 -#define MIB_TX256BYTE_E_OFFSET 0x100 -#define MIB_TX256BYTE_NR_E 7 - -#define MIB_TX512BYTE -#define MIB_TX512BYTE_OFFSET 0x01070 -#define MIB_TX512BYTE_E_LENGTH 4 -#define MIB_TX512BYTE_E_OFFSET 0x100 -#define MIB_TX512BYTE_NR_E 7 - -#define MIB_TX1024BYTE -#define MIB_TX1024BYTE_OFFSET 0x01074 -#define MIB_TX1024BYTE_E_LENGTH 4 -#define MIB_TX1024BYTE_E_OFFSET 0x100 -#define MIB_TX1024BYTE_NR_E 7 - -#define MIB_TX1518BYTE -#define MIB_TX1518BYTE_OFFSET 0x01078 -#define MIB_TX1518BYTE_E_LENGTH 4 -#define MIB_TX1518BYTE_E_OFFSET 0x100 -#define MIB_TX1518BYTE_NR_E 7 - -#define MIB_TXMAXBYTE -#define MIB_TXMAXBYTE_OFFSET 0x0107c -#define MIB_TXMAXBYTE_E_LENGTH 4 -#define MIB_TXMAXBYTE_E_OFFSET 0x100 -#define MIB_TXMAXBYTE_NR_E 7 - -#define MIB_TXOVERSIZE -#define MIB_TXOVERSIZE_OFFSET 0x01080 -#define MIB_TXOVERSIZE_E_LENGTH 4 -#define MIB_TXOVERSIZE_E_OFFSET 0x100 -#define MIB_TXOVERSIZE_NR_E 7 - -#define MIB_TXBYTE_LO -#define MIB_TXBYTE_LO_OFFSET 0x01084 -#define MIB_TXBYTE_LO_E_LENGTH 4 -#define MIB_TXBYTE_LO_E_OFFSET 0x100 -#define MIB_TXBYTE_LO_NR_E 7 - -#define MIB_TXBYTE_HI -#define MIB_TXBYTE_HI_OFFSET 0x01088 -#define MIB_TXBYTE_HI_E_LENGTH 4 -#define MIB_TXBYTE_HI_E_OFFSET 0x100 -#define MIB_TXBYTE_HI_NR_E 7 - -#define MIB_TXCOLLISION -#define MIB_TXCOLLISION_OFFSET 0x0108c -#define MIB_TXCOLLISION_E_LENGTH 4 -#define MIB_TXCOLLISION_E_OFFSET 0x100 -#define MIB_TXCOLLISION_NR_E 7 - -#define MIB_TXABORTCOL -#define MIB_TXABORTCOL_OFFSET 0x01090 -#define MIB_TXABORTCOL_E_LENGTH 4 -#define MIB_TXABORTCOL_E_OFFSET 0x100 -#define MIB_TXABORTCOL_NR_E 7 - -#define MIB_TXMULTICOL -#define MIB_TXMULTICOL_OFFSET 0x01094 -#define MIB_TXMULTICOL_E_LENGTH 4 -#define MIB_TXMULTICOL_E_OFFSET 0x100 -#define MIB_TXMULTICOL_NR_E 7 - -#define MIB_TXSINGALCOL -#define MIB_TXSINGALCOL_OFFSET 0x01098 -#define MIB_TXSINGALCOL_E_LENGTH 4 -#define MIB_TXSINGALCOL_E_OFFSET 0x100 -#define MIB_TXSINGALCOL_NR_E 7 - -#define MIB_TXEXCDEFER -#define MIB_TXEXCDEFER_OFFSET 0x0109c -#define MIB_TXEXCDEFER_E_LENGTH 4 -#define MIB_TXEXCDEFER_E_OFFSET 0x100 -#define MIB_TXEXCDEFER_NR_E 7 - -#define MIB_TXDEFER -#define MIB_TXDEFER_OFFSET 0x010a0 -#define MIB_TXDEFER_E_LENGTH 4 -#define MIB_TXDEFER_E_OFFSET 0x100 -#define MIB_TXDEFER_NR_E 7 - -#define MIB_TXLATECOL -#define MIB_TXLATECOL_OFFSET 0x010a4 -#define MIB_TXLATECOL_E_LENGTH 4 -#define MIB_TXLATECOL_E_OFFSET 0x100 -#define MIB_TXLATECOL_NR_E 7 - -#define MIB_RXUNICAST -#define MIB_RXUNICAST_OFFSET 0x010a8 -#define MIB_RXUNICAST_E_LENGTH 4 -#define MIB_RXUNICAST_E_OFFSET 0x100 -#define MIB_RXUNICAST_NR_E 7 - -#define MIB_TXUNICAST -#define MIB_TXUNICAST_OFFSET 0x010ac -#define MIB_TXUNICAST_E_LENGTH 4 -#define MIB_TXUNICAST_E_OFFSET 0x100 -#define MIB_TXUNICAST_NR_E 7 - - /* ACL Action Register */ -#define ACL_RSLT0 10 -#define ACL_RSLT0_OFFSET 0x5a000 -#define ACL_RSLT0_E_LENGTH 4 -#define ACL_RSLT0_E_OFFSET 0x10 -#define ACL_RSLT0_NR_E 96 - -#define CTAGPRI -#define ACL_RSLT0_CTAGPRI_BOFFSET 29 -#define ACL_RSLT0_CTAGPRI_BLEN 3 -#define ACL_RSLT0_CTAGPRI_FLAG HSL_RW - -#define CTAGCFI -#define ACL_RSLT0_CTAGCFI_BOFFSET 28 -#define ACL_RSLT0_CTAGCFI_BLEN 1 -#define ACL_RSLT0_CTAGCFI_FLAG HSL_RW - -#define CTAGVID -#define ACL_RSLT0_CTAGVID_BOFFSET 16 -#define ACL_RSLT0_CTAGVID_BLEN 12 -#define ACL_RSLT0_CTAGVID_FLAG HSL_RW - -#define STAGPRI -#define ACL_RSLT0_STAGPRI_BOFFSET 13 -#define ACL_RSLT0_STAGPRI_BLEN 3 -#define ACL_RSLT0_STAGPRI_FLAG HSL_RW - -#define STAGDEI -#define ACL_RSLT0_STAGDEI_BOFFSET 12 -#define ACL_RSLT0_STAGDEI_BLEN 1 -#define ACL_RSLT0_STAGDEI_FLAG HSL_RW - -#define STAGVID -#define ACL_RSLT0_STAGVID_BOFFSET 0 -#define ACL_RSLT0_STAGVID_BLEN 12 -#define ACL_RSLT0_STAGVID_FLAG HSL_RW - - -#define ACL_RSLT1 11 -#define ACL_RSLT1_OFFSET 0x5a004 -#define ACL_RSLT1_E_LENGTH 4 -#define ACL_RSLT1_E_OFFSET 0x10 -#define ACL_RSLT1_NR_E 96 - -#define DES_PORT0 -#define ACL_RSLT1_DES_PORT0_BOFFSET 29 -#define ACL_RSLT1_DES_PORT0_BLEN 3 -#define ACL_RSLT1_DES_PORT0_FLAG HSL_RW - -#define PRI_QU_EN -#define ACL_RSLT1_PRI_QU_EN_BOFFSET 28 -#define ACL_RSLT1_PRI_QU_EN_BLEN 1 -#define ACL_RSLT1_PRI_QU_EN_FLAG HSL_RW - -#define PRI_QU -#define ACL_RSLT1_PRI_QU_BOFFSET 25 -#define ACL_RSLT1_PRI_QU_BLEN 3 -#define ACL_RSLT1_PRI_QU_FLAG HSL_RW - -#define WCMP_EN -#define ACL_RSLT1_WCMP_EN_BOFFSET 24 -#define ACL_RSLT1_WCMP_EN_BLEN 1 -#define ACL_RSLT1_WCMP_EN_FLAG HSL_RW - -#define ARP_PTR -#define ACL_RSLT1_ARP_PTR_BOFFSET 17 -#define ACL_RSLT1_ARP_PTR_BLEN 7 -#define ACL_RSLT1_ARP_PTR_FLAG HSL_RW - -#define ARP_PTR_EN -#define ACL_RSLT1_ARP_PTR_EN_BOFFSET 16 -#define ACL_RSLT1_ARP_PTR_EN_BLEN 1 -#define ACL_RSLT1_ARP_PTR_EN_FLAG HSL_RW - -#define FORCE_L3_MODE -#define ACL_RSLT1_FORCE_L3_MODE_BOFFSET 14 -#define ACL_RSLT1_FORCE_L3_MODE_BLEN 2 -#define ACL_RSLT1_FORCE_L3_MODE_FLAG HSL_RW - -#define LOOK_VID_CHG -#define ACL_RSLT1_LOOK_VID_CHG_BOFFSET 13 -#define ACL_RSLT1_LOOK_VID_CHG_BLEN 1 -#define ACL_RSLT1_LOOK_VID_CHG_FLAG HSL_RW - -#define TRANS_CVID_CHG -#define ACL_RSLT1_TRANS_CVID_CHG_BOFFSET 12 -#define ACL_RSLT1_TRANS_CVID_CHG_BLEN 1 -#define ACL_RSLT1_TRANS_CVID_CHG_FLAG HSL_RW - -#define TRANS_SVID_CHG -#define ACL_RSLT1_TRANS_SVID_CHG_BOFFSET 11 -#define ACL_RSLT1_TRANS_SVID_CHG_BLEN 1 -#define ACL_RSLT1_TRANS_SVID_CHG_FLAG HSL_RW - -#define CTAG_CFI_CHG -#define ACL_RSLT1_CTAG_CFI_CHG_BOFFSET 10 -#define ACL_RSLT1_CTAG_CFI_CHG_BLEN 1 -#define ACL_RSLT1_CTAG_CFI_CHG_FLAG HSL_RW - -#define CTAG_PRI_REMAP -#define ACL_RSLT1_CTAG_PRI_REMAP_BOFFSET 9 -#define ACL_RSLT1_CTAG_PRI_REMAP_BLEN 1 -#define ACL_RSLT1_CTAG_PRI_REMAP_FLAG HSL_RW - -#define STAG_DEI_CHG -#define ACL_RSLT1_STAG_DEI_CHG_BOFFSET 8 -#define ACL_RSLT1_STAG_DEI_CHG_BLEN 1 -#define ACL_RSLT1_STAG_DEI_CHG_FLAG HSL_RW - -#define STAG_PRI_REMAP -#define ACL_RSLT1_STAG_PRI_REMAP_BOFFSET 7 -#define ACL_RSLT1_STAG_PRI_REMAP_BLEN 1 -#define ACL_RSLT1_STAG_PRI_REMAP_FLAG HSL_RW - -#define DSCP_REMAP -#define ACL_RSLT1_DSCP_REMAP_BOFFSET 6 -#define ACL_RSLT1_DSCP_REMAP_BLEN 1 -#define ACL_RSLT1_DSCP_REMAP_FLAG HSL_RW - -#define DSCPV -#define ACL_RSLT1_DSCPV_BOFFSET 0 -#define ACL_RSLT1_DSCPV_BLEN 6 -#define ACL_RSLT1_DSCPV_FLAG HSL_RW - -#define ACL_RSLT2 12 -#define ACL_RSLT2_OFFSET 0x5a008 -#define ACL_RSLT2_E_LENGTH 4 -#define ACL_RSLT2_E_OFFSET 0x10 -#define ACL_RSLT2_NR_E 96 - -#define TRIGGER_INTR -#define ACL_RSLT2_TRIGGER_INTR_BOFFSET 16 -#define ACL_RSLT2_TRIGGER_INTR_BLEN 1 -#define ACL_RSLT2_TRIGGER_INTR_FLAG HSL_RW - -#define EG_BYPASS -#define ACL_RSLT2_EG_BYPASS_BOFFSET 15 -#define ACL_RSLT2_EG_BYPASS_BLEN 1 -#define ACL_RSLT2_EG_BYPASS_FLAG HSL_RW - -#define POLICER_EN -#define ACL_RSLT2_POLICER_EN_BOFFSET 14 -#define ACL_RSLT2_POLICER_EN_BLEN 1 -#define ACL_RSLT2_POLICER_EN_FLAG HSL_RW - -#define POLICER_PTR -#define ACL_RSLT2_POLICER_PTR_BOFFSET 9 -#define ACL_RSLT2_POLICER_PTR_BLEN 5 -#define ACL_RSLT2_POLICER_PTR_FLAG HSL_RW - -#define FWD_CMD -#define ACL_RSLT2_FWD_CMD_BOFFSET 6 -#define ACL_RSLT2_FWD_CMD_BLEN 3 -#define ACL_RSLT2_FWD_CMD_FLAG HSL_RW - -#define MIRR_EN -#define ACL_RSLT2_MIRR_EN_BOFFSET 5 -#define ACL_RSLT2_MIRR_EN_BLEN 1 -#define ACL_RSLT2_MIRR_EN_FLAG HSL_RW - -#define DES_PORT_EN -#define ACL_RSLT2_DES_PORT_EN_BOFFSET 4 -#define ACL_RSLT2_DES_PORT_EN_BLEN 1 -#define ACL_RSLT2_DES_PORT_EN_FLAG HSL_RW - -#define DES_PORT1 -#define ACL_RSLT2_DES_PORT1_BOFFSET 0 -#define ACL_RSLT2_DES_PORT1_BLEN 4 -#define ACL_RSLT2_DES_PORT1_FLAG HSL_RW - - - - - /* MAC Type Rule Field Define */ -#define MAC_RUL_V0 0 -#define MAC_RUL_V0_OFFSET 0x58000 -#define MAC_RUL_V0_E_LENGTH 4 -#define MAC_RUL_V0_E_OFFSET 0x20 -#define MAC_RUL_V0_NR_E 96 - -#define DAV_BYTE2 -#define MAC_RUL_V0_DAV_BYTE2_BOFFSET 24 -#define MAC_RUL_V0_DAV_BYTE2_BLEN 8 -#define MAC_RUL_V0_DAV_BYTE2_FLAG HSL_RW - -#define DAV_BYTE3 -#define MAC_RUL_V0_DAV_BYTE3_BOFFSET 16 -#define MAC_RUL_V0_DAV_BYTE3_BLEN 8 -#define MAC_RUL_V0_DAV_BYTE3_FLAG HSL_RW - -#define DAV_BYTE4 -#define MAC_RUL_V0_DAV_BYTE4_BOFFSET 8 -#define MAC_RUL_V0_DAV_BYTE4_BLEN 8 -#define MAC_RUL_V0_DAV_BYTE4_FLAG HSL_RW - -#define DAV_BYTE5 -#define MAC_RUL_V0_DAV_BYTE5_BOFFSET 0 -#define MAC_RUL_V0_DAV_BYTE5_BLEN 8 -#define MAC_RUL_V0_DAV_BYTE5_FLAG HSL_RW - - -#define MAC_RUL_V1 1 -#define MAC_RUL_V1_OFFSET 0x58004 -#define MAC_RUL_V1_E_LENGTH 4 -#define MAC_RUL_V1_E_OFFSET 0x20 -#define MAC_RUL_V1_NR_E 96 - -#define SAV_BYTE4 -#define MAC_RUL_V1_SAV_BYTE4_BOFFSET 24 -#define MAC_RUL_V1_SAV_BYTE4_BLEN 8 -#define MAC_RUL_V1_SAV_BYTE4_FLAG HSL_RW - -#define SAV_BYTE5 -#define MAC_RUL_V1_SAV_BYTE5_BOFFSET 16 -#define MAC_RUL_V1_SAV_BYTE5_BLEN 8 -#define MAC_RUL_V1_SAV_BYTE5_FLAG HSL_RW - -#define DAV_BYTE0 -#define MAC_RUL_V1_DAV_BYTE0_BOFFSET 8 -#define MAC_RUL_V1_DAV_BYTE0_BLEN 8 -#define MAC_RUL_V1_DAV_BYTE0_FLAG HSL_RW - -#define DAV_BYTE1 -#define MAC_RUL_V1_DAV_BYTE1_BOFFSET 0 -#define MAC_RUL_V1_DAV_BYTE1_BLEN 8 -#define MAC_RUL_V1_DAV_BYTE1_FLAG HSL_RW - - -#define MAC_RUL_V2 2 -#define MAC_RUL_V2_OFFSET 0x58008 -#define MAC_RUL_V2_E_LENGTH 4 -#define MAC_RUL_V2_E_OFFSET 0x20 -#define MAC_RUL_V2_NR_E 96 - -#define SAV_BYTE0 -#define MAC_RUL_V2_SAV_BYTE0_BOFFSET 24 -#define MAC_RUL_V2_SAV_BYTE0_BLEN 8 -#define MAC_RUL_V2_SAV_BYTE0_FLAG HSL_RW - -#define SAV_BYTE1 -#define MAC_RUL_V2_SAV_BYTE1_BOFFSET 16 -#define MAC_RUL_V2_SAV_BYTE1_BLEN 8 -#define MAC_RUL_V2_SAV_BYTE1_FLAG HSL_RW - -#define SAV_BYTE2 -#define MAC_RUL_V2_SAV_BYTE2_BOFFSET 8 -#define MAC_RUL_V2_SAV_BYTE2_BLEN 8 -#define MAC_RUL_V2_SAV_BYTE2_FLAG HSL_RW - -#define SAV_BYTE3 -#define MAC_RUL_V2_SAV_BYTE3_BOFFSET 0 -#define MAC_RUL_V2_SAV_BYTE3_BLEN 8 -#define MAC_RUL_V2_SAV_BYTE3_FLAG HSL_RW - - -#define MAC_RUL_V3 3 -#define MAC_RUL_V3_ID 13 -#define MAC_RUL_V3_OFFSET 0x5800c -#define MAC_RUL_V3_E_LENGTH 4 -#define MAC_RUL_V3_E_OFFSET 0x20 -#define MAC_RUL_V3_NR_E 96 - -#define ETHTYPV -#define MAC_RUL_V3_ETHTYPV_BOFFSET 16 -#define MAC_RUL_V3_ETHTYPV_BLEN 16 -#define MAC_RUL_V3_ETHTYPV_FLAG HSL_RW - -#define VLANPRIV -#define MAC_RUL_V3_VLANPRIV_BOFFSET 13 -#define MAC_RUL_V3_VLANPRIV_BLEN 3 -#define MAC_RUL_V3_VLANPRIV_FLAG HSL_RW - -#define VLANCFIV -#define MAC_RUL_V3_VLANCFIV_BOFFSET 12 -#define MAC_RUL_V3_VLANCFIV_BLEN 1 -#define MAC_RUL_V3_VLANCFIV_FLAG HSL_RW - -#define VLANIDV -#define MAC_RUL_V3_VLANIDV_BOFFSET 0 -#define MAC_RUL_V3_VLANIDV_BLEN 12 -#define MAC_RUL_V3_VLANIDV_FLAG HSL_RW - - -#define MAC_RUL_V4 4 -#define MAC_RUL_V4_OFFSET 0x58010 -#define MAC_RUL_V4_E_LENGTH 4 -#define MAC_RUL_V4_E_OFFSET 0x20 -#define MAC_RUL_V4_NR_E 96 - -#define RULE_INV -#define MAC_RUL_V4_RULE_INV_BOFFSET 7 -#define MAC_RUL_V4_RULE_INV_BLEN 1 -#define MAC_RUL_V4_RULE_INV_FLAG HSL_RW - -#define SRC_PT -#define MAC_RUL_V4_SRC_PT_BOFFSET 0 -#define MAC_RUL_V4_SRC_PT_BLEN 7 -#define MAC_RUL_V4_SRC_PT_FLAG HSL_RW - - -#define MAC_RUL_M0 5 -#define MAC_RUL_M0_OFFSET 0x59000 -#define MAC_RUL_M0_E_LENGTH 4 -#define MAC_RUL_M0_E_OFFSET 0x20 -#define MAC_RUL_M0_NR_E 96 - -#define DAM_BYTE2 -#define MAC_RUL_M0_DAM_BYTE2_BOFFSET 24 -#define MAC_RUL_M0_DAM_BYTE2_BLEN 8 -#define MAC_RUL_M0_DAM_BYTE2_FLAG HSL_RW - -#define DAM_BYTE3 -#define MAC_RUL_M0_DAM_BYTE3_BOFFSET 16 -#define MAC_RUL_M0_DAM_BYTE3_BLEN 8 -#define MAC_RUL_M0_DAM_BYTE3_FLAG HSL_RW - -#define DAM_BYTE4 -#define MAC_RUL_M0_DAM_BYTE4_BOFFSET 8 -#define MAC_RUL_M0_DAM_BYTE4_BLEN 8 -#define MAC_RUL_M0_DAM_BYTE4_FLAG HSL_RW - -#define DAM_BYTE5 -#define MAC_RUL_M0_DAM_BYTE5_BOFFSET 0 -#define MAC_RUL_M0_DAM_BYTE5_BLEN 8 -#define MAC_RUL_M0_DAM_BYTE5_FLAG HSL_RW - - -#define MAC_RUL_M1 6 -#define MAC_RUL_M1_OFFSET 0x59004 -#define MAC_RUL_M1_E_LENGTH 4 -#define MAC_RUL_M1_E_OFFSET 0x20 -#define MAC_RUL_M1_NR_E 96 - -#define SAM_BYTE4 -#define MAC_RUL_M1_SAM_BYTE4_BOFFSET 24 -#define MAC_RUL_M1_SAM_BYTE4_BLEN 8 -#define MAC_RUL_M1_SAM_BYTE4_FLAG HSL_RW - -#define SAM_BYTE5 -#define MAC_RUL_M1_SAM_BYTE5_BOFFSET 16 -#define MAC_RUL_M1_SAM_BYTE5_BLEN 8 -#define MAC_RUL_M1_SAM_BYTE5_FLAG HSL_RW - -#define DAM_BYTE0 -#define MAC_RUL_M1_DAM_BYTE0_BOFFSET 8 -#define MAC_RUL_M1_DAM_BYTE0_BLEN 8 -#define MAC_RUL_M1_DAM_BYTE0_FLAG HSL_RW - -#define DAM_BYTE1 -#define MAC_RUL_M1_DAM_BYTE1_BOFFSET 0 -#define MAC_RUL_M1_DAM_BYTE1_BLEN 8 -#define MAC_RUL_M1_DAM_BYTE1_FLAG HSL_RW - - -#define MAC_RUL_M2 7 -#define MAC_RUL_M2_OFFSET 0x59008 -#define MAC_RUL_M2_E_LENGTH 4 -#define MAC_RUL_M2_E_OFFSET 0x20 -#define MAC_RUL_M2_NR_E 96 - -#define SAM_BYTE0 -#define MAC_RUL_M2_SAM_BYTE0_BOFFSET 24 -#define MAC_RUL_M2_SAM_BYTE0_BLEN 8 -#define MAC_RUL_M2_SAM_BYTE0_FLAG HSL_RW - -#define SAM_BYTE1 -#define MAC_RUL_M2_SAM_BYTE1_BOFFSET 16 -#define MAC_RUL_M2_SAM_BYTE1_BLEN 8 -#define MAC_RUL_M2_SAM_BYTE1_FLAG HSL_RW - -#define SAM_BYTE2 -#define MAC_RUL_M2_SAM_BYTE2_BOFFSET 8 -#define MAC_RUL_M2_SAM_BYTE2_BLEN 8 -#define MAC_RUL_M2_SAM_BYTE2_FLAG HSL_RW - -#define SAM_BYTE3 -#define MAC_RUL_M2_SAM_BYTE3_BOFFSET 0 -#define MAC_RUL_M2_SAM_BYTE3_BLEN 8 -#define MAC_RUL_M2_SAM_BYTE3_FLAG HSL_RW - - -#define MAC_RUL_M3 8 -#define MAC_RUL_M3_OFFSET 0x5900c -#define MAC_RUL_M3_E_LENGTH 4 -#define MAC_RUL_M3_E_OFFSET 0x20 -#define MAC_RUL_M3_NR_E 96 - -#define ETHTYPM -#define MAC_RUL_M3_ETHTYPM_BOFFSET 16 -#define MAC_RUL_M3_ETHTYPM_BLEN 16 -#define MAC_RUL_M3_ETHTYPM_FLAG HSL_RW - -#define VLANPRIM -#define MAC_RUL_M3_VLANPRIM_BOFFSET 13 -#define MAC_RUL_M3_VLANPRIM_BLEN 3 -#define MAC_RUL_M3_VLANPRIM_FLAG HSL_RW - -#define VLANCFIM -#define MAC_RUL_M3_VLANCFIM_BOFFSET 12 -#define MAC_RUL_M3_VLANCFIM_BLEN 1 -#define MAC_RUL_M3_VLANCFIM_FLAG HSL_RW - -#define VLANIDM -#define MAC_RUL_M3_VLANIDM_BOFFSET 0 -#define MAC_RUL_M3_VLANIDM_BLEN 12 -#define MAC_RUL_M3_VLANIDM_FLAG HSL_RW - - -#define MAC_RUL_M4 9 -#define MAC_RUL_M4_OFFSET 0x59010 -#define MAC_RUL_M4_E_LENGTH 4 -#define MAC_RUL_M4_E_OFFSET 0x20 -#define MAC_RUL_M4_NR_E 96 - -#define RULE_VALID -#define MAC_RUL_M4_RULE_VALID_BOFFSET 6 -#define MAC_RUL_M4_RULE_VALID_BLEN 2 -#define MAC_RUL_M4_RULE_VALID_FLAG HSL_RW - -#define TAGGEDM -#define MAC_RUL_M4_TAGGEDM_BOFFSET 5 -#define MAC_RUL_M4_TAGGEDM_BLEN 1 -#define MAC_RUL_M4_TAGGEDM_FLAG HSL_RW - -#define TAGGEDV -#define MAC_RUL_M4_TAGGEDV_BOFFSET 4 -#define MAC_RUL_M4_TAGGEDV_BLEN 1 -#define MAC_RUL_M4_TAGGEDV_FLAG HSL_RW - -#define VIDMSK -#define MAC_RUL_M4_VIDMSK_BOFFSET 3 -#define MAC_RUL_M4_VIDMSK_BLEN 1 -#define MAC_RUL_M4_VIDMSK_FLAG HSL_RW - -#define RULE_TYP -#define MAC_RUL_M4_RULE_TYP_BOFFSET 0 -#define MAC_RUL_M4_RULE_TYP_BLEN 3 -#define MAC_RUL_M4_RULE_TYP_FLAG HSL_RW - - - - - /* IP4 Type Rule Field Define */ -#define IP4_RUL_V0 0 -#define IP4_RUL_V0_OFFSET 0x58000 -#define IP4_RUL_V0_E_LENGTH 4 -#define IP4_RUL_V0_E_OFFSET 0x20 -#define IP4_RUL_V0_NR_E 96 - -#define DIPV -#define IP4_RUL_V0_DIPV_BOFFSET 0 -#define IP4_RUL_V0_DIPV_BLEN 32 -#define IP4_RUL_V0_DIPV_FLAG HSL_RW - - -#define IP4_RUL_V1 1 -#define IP4_RUL_V1_OFFSET 0x58004 -#define IP4_RUL_V1_E_LENGTH 4 -#define IP4_RUL_V1_E_OFFSET 0x20 -#define IP4_RUL_V1_NR_E 96 - -#define SIPV -#define IP4_RUL_V1_SIPV_BOFFSET 0 -#define IP4_RUL_V1_SIPV_BLEN 32 -#define IP4_RUL_V1_SIPV_FLAG HSL_RW - - -#define IP4_RUL_V2 2 -#define IP4_RUL_V2_OFFSET 0x58008 -#define IP4_RUL_V2_E_LENGTH 4 -#define IP4_RUL_V2_E_OFFSET 0x20 -#define IP4_RUL_V2_NR_E 96 - -#define IP4PROTV -#define IP4_RUL_V2_IP4PROTV_BOFFSET 0 -#define IP4_RUL_V2_IP4PROTV_BLEN 8 -#define IP4_RUL_V2_IP4PROTV_FLAG HSL_RW - -#define IP4DSCPV -#define IP4_RUL_V2_IP4DSCPV_BOFFSET 8 -#define IP4_RUL_V2_IP4DSCPV_BLEN 8 -#define IP4_RUL_V2_IP4DSCPV_FLAG HSL_RW - -#define IP4DPORTV -#define IP4_RUL_V2_IP4DPORTV_BOFFSET 16 -#define IP4_RUL_V2_IP4DPORTV_BLEN 16 -#define IP4_RUL_V2_IP4DPORTV_FLAG HSL_RW - - -#define IP4_RUL_V3 3 -#define IP4_RUL_V3_OFFSET 0x5800c -#define IP4_RUL_V3_E_LENGTH 4 -#define IP4_RUL_V3_E_OFFSET 0x20 -#define IP4_RUL_V3_NR_E 96 - -#define IP4TCPFLAGV -#define IP4_RUL_V3_IP4TCPFLAGV_BOFFSET 24 -#define IP4_RUL_V3_IP4TCPFLAGV_BLEN 6 -#define IP4_RUL_V3_IP4TCPFLAGV_FLAG HSL_RW - -#define IP4DHCPV -#define IP4_RUL_V3_IP4DHCPV_BOFFSET 22 -#define IP4_RUL_V3_IP4DHCPV_BLEN 1 -#define IP4_RUL_V3_IP4DHCPV_FLAG HSL_RW - -#define IP4RIPV -#define IP4_RUL_V3_IP4RIPV_BOFFSET 21 -#define IP4_RUL_V3_IP4RIPV_BLEN 1 -#define IP4_RUL_V3_IP4RIPV_FLAG HSL_RW - -#define ICMP_EN -#define IP4_RUL_V3_ICMP_EN_BOFFSET 20 -#define IP4_RUL_V3_ICMP_EN_BLEN 1 -#define IP4_RUL_V3_ICMP_EN_FLAG HSL_RW - -#define IP4SPORTV -#define IP4_RUL_V3_IP4SPORTV_BOFFSET 0 -#define IP4_RUL_V3_IP4SPORTV_BLEN 16 -#define IP4_RUL_V3_IP4SPORTV_FLAG HSL_RW - -#define IP4ICMPTYPV -#define IP4_RUL_V3_IP4ICMPTYPV_BOFFSET 8 -#define IP4_RUL_V3_IP4ICMPTYPV_BLEN 8 -#define IP4_RUL_V3_IP4ICMPTYPV_FLAG HSL_RW - -#define IP4ICMPCODEV -#define IP4_RUL_V3_IP4ICMPCODEV_BOFFSET 0 -#define IP4_RUL_V3_IP4ICMPCODEV_BLEN 8 -#define IP4_RUL_V3_IP4ICMPCODEV_FLAG HSL_RW - - -#define IP4_RUL_V4 4 -#define IP4_RUL_V4_OFFSET 0x58010 -#define IP4_RUL_V4_E_LENGTH 4 -#define IP4_RUL_V4_E_OFFSET 0x20 -#define IP4_RUL_V4_NR_E 96 - - -#define IP4_RUL_M0 5 -#define IP4_RUL_M0_OFFSET 0x59000 -#define IP4_RUL_M0_E_LENGTH 4 -#define IP4_RUL_M0_E_OFFSET 0x20 -#define IP4_RUL_M0_NR_E 96 - -#define DIPM -#define IP4_RUL_M0_DIPM_BOFFSET 0 -#define IP4_RUL_M0_DIPM_BLEN 32 -#define IP4_RUL_M0_DIPM_FLAG HSL_RW - - -#define IP4_RUL_M1 6 -#define IP4_RUL_M1_OFFSET 0x59004 -#define IP4_RUL_M1_E_LENGTH 4 -#define IP4_RUL_M1_E_OFFSET 0x20 -#define IP4_RUL_M1_NR_E 96 - -#define SIPM -#define IP4_RUL_M1_SIPM_BOFFSET 0 -#define IP4_RUL_M1_SIPM_BLEN 32 -#define IP4_RUL_M1_SIPM_FLAG HSL_RW - - -#define IP4_RUL_M2 7 -#define IP4_RUL_M2_OFFSET 0x59008 -#define IP4_RUL_M2_E_LENGTH 4 -#define IP4_RUL_M2_E_OFFSET 0x20 -#define IP4_RUL_M2_NR_E 96 - -#define IP4PROTM -#define IP4_RUL_M2_IP4PROTM_BOFFSET 0 -#define IP4_RUL_M2_IP4PROTM_BLEN 8 -#define IP4_RUL_M2_IP4PROTM_FLAG HSL_RW - -#define IP4DSCPM -#define IP4_RUL_M2_IP4DSCPM_BOFFSET 8 -#define IP4_RUL_M2_IP4DSCPM_BLEN 8 -#define IP4_RUL_M2_IP4DSCPM_FLAG HSL_RW - -#define IP4DPORTM -#define IP4_RUL_M2_IP4DPORTM_BOFFSET 16 -#define IP4_RUL_M2_IP4DPORTM_BLEN 16 -#define IP4_RUL_M2_IP4DPORTM_FLAG HSL_RW - - -#define IP4_RUL_M3 8 -#define IP4_RUL_M3_OFFSET 0x5900c -#define IP4_RUL_M3_E_LENGTH 4 -#define IP4_RUL_M3_E_OFFSET 0x20 -#define IP4_RUL_M3_NR_E 96 - -#define IP4TCPFLAGM -#define IP4_RUL_M3_IP4TCPFLAGM_BOFFSET 24 -#define IP4_RUL_M3_IP4TCPFLAGM_BLEN 6 -#define IP4_RUL_M3_IP4TCPFLAGM_FLAG HSL_RW - -#define IP4DHCPM -#define IP4_RUL_M3_IP4DHCPM_BOFFSET 22 -#define IP4_RUL_M3_IP4DHCPM_BLEN 1 -#define IP4_RUL_M3_IP4DHCPM_FLAG HSL_RW - -#define IP4RIPM -#define IP4_RUL_M3_IP4RIPM_BOFFSET 21 -#define IP4_RUL_M3_IP4RIPM_BLEN 1 -#define IP4_RUL_M3_IP4RIPM_FLAG HSL_RW - -#define IP4DPORTM_EN -#define IP4_RUL_M3_IP4DPORTM_EN_BOFFSET 17 -#define IP4_RUL_M3_IP4DPORTM_EN_BLEN 1 -#define IP4_RUL_M3_IP4DPORTM_EN_FLAG HSL_RW - -#define IP4SPORTM_EN -#define IP4_RUL_M3_IP4SPORTM_EN_BOFFSET 16 -#define IP4_RUL_M3_IP4SPORTM_EN_BLEN 1 -#define IP4_RUL_M3_IP4SPORTM_EN_FLAG HSL_RW - -#define IP4SPORTM -#define IP4_RUL_M3_IP4SPORTM_BOFFSET 0 -#define IP4_RUL_M3_IP4SPORTM_BLEN 16 -#define IP4_RUL_M3_IP4SPORTM_FLAG HSL_RW - -#define IP4ICMPTYPM -#define IP4_RUL_M3_IP4ICMPTYPM_BOFFSET 8 -#define IP4_RUL_M3_IP4ICMPTYPM_BLEN 8 -#define IP4_RUL_M3_IP4ICMPTYPM_FLAG HSL_RW - -#define IP4ICMPCODEM -#define IP4_RUL_M3_IP4ICMPCODEM_BOFFSET 0 -#define IP4_RUL_M3_IP4ICMPCODEM_BLEN 8 -#define IP4_RUL_M3_IP4ICMPCODEM_FLAG HSL_RW - - -#define IP4_RUL_M4 9 -#define IP4_RUL_M4_OFFSET 0x59010 -#define IP4_RUL_M4_E_LENGTH 4 -#define IP4_RUL_M4_E_OFFSET 0x20 -#define IP4_RUL_M4_NR_E 32 - - - - - /* IP6 Type1 Rule Field Define */ -#define IP6_RUL1_V0 0 -#define IP6_RUL1_V0_OFFSET 0x58000 -#define IP6_RUL1_V0_E_LENGTH 4 -#define IP6_RUL1_V0_E_OFFSET 0x20 -#define IP6_RUL1_V0_NR_E 96 - -#define IP6_DIPV0 -#define IP6_RUL1_V0_IP6_DIPV0_BOFFSET 0 -#define IP6_RUL1_V0_IP6_DIPV0_BLEN 32 -#define IP6_RUL1_V0_IP6_DIPV0_FLAG HSL_RW - - -#define IP6_RUL1_V1 1 -#define IP6_RUL1_V1_OFFSET 0x58004 -#define IP6_RUL1_V1_E_LENGTH 4 -#define IP6_RUL1_V1_E_OFFSET 0x20 -#define IP6_RUL1_V1_NR_E 96 - -#define IP6_DIPV1 -#define IP6_RUL1_V1_IP6_DIPV1_BOFFSET 0 -#define IP6_RUL1_V1_IP6_DIPv1_BLEN 32 -#define IP6_RUL1_V1_IP6_DIPV1_FLAG HSL_RW - - -#define IP6_RUL1_V2 2 -#define IP6_RUL1_V2_OFFSET 0x58008 -#define IP6_RUL1_V2_E_LENGTH 4 -#define IP6_RUL1_V2_E_OFFSET 0x20 -#define IP6_RUL1_V2_NR_E 96 - -#define IP6_DIPV2 -#define IP6_RUL1_V2_IP6_DIPV2_BOFFSET 0 -#define IP6_RUL1_V2_IP6_DIPv2_BLEN 32 -#define IP6_RUL1_V2_IP6_DIPV2_FLAG HSL_RW - - -#define IP6_RUL1_V3 3 -#define IP6_RUL1_V3_OFFSET 0x5800c -#define IP6_RUL1_V3_E_LENGTH 4 -#define IP6_RUL1_V3_E_OFFSET 0x20 -#define IP6_RUL1_V3_NR_E 96 - -#define IP6_DIPV3 -#define IP6_RUL1_V3_IP6_DIPV3_BOFFSET 0 -#define IP6_RUL1_V3_IP6_DIPv3_BLEN 32 -#define IP6_RUL1_V3_IP6_DIPV3_FLAG HSL_RW - - -#define IP6_RUL1_V4 4 -#define IP6_RUL1_V4_OFFSET 0x58010 -#define IP6_RUL1_V4_E_LENGTH 4 -#define IP6_RUL1_V4_E_OFFSET 0x20 -#define IP6_RUL1_V4_NR_E 96 - - -#define IP6_RUL1_M0 5 -#define IP6_RUL1_M0_OFFSET 0x59000 -#define IP6_RUL1_M0_E_LENGTH 4 -#define IP6_RUL1_M0_E_OFFSET 0x20 -#define IP6_RUL1_M0_NR_E 96 - -#define IP6_DIPM0 -#define IP6_RUL1_M0_IP6_DIPM0_BOFFSET 0 -#define IP6_RUL1_M0_IP6_DIPM0_BLEN 32 -#define IP6_RUL1_M0_IP6_DIPM0_FLAG HSL_RW - - -#define IP6_RUL1_M1 6 -#define IP6_RUL1_M1_OFFSET 0x59004 -#define IP6_RUL1_M1_E_LENGTH 4 -#define IP6_RUL1_M1_E_OFFSET 0x20 -#define IP6_RUL1_M1_NR_E 96 - -#define IP6_DIPM1 -#define IP6_RUL1_M1_IP6_DIPM1_BOFFSET 0 -#define IP6_RUL1_M1_IP6_DIPM1_BLEN 32 -#define IP6_RUL1_M1_IP6_DIPM1_FLAG HSL_RW - - -#define IP6_RUL1_M2 7 -#define IP6_RUL1_M2_OFFSET 0x59008 -#define IP6_RUL1_M2_E_LENGTH 4 -#define IP6_RUL1_M2_E_OFFSET 0x20 -#define IP6_RUL1_M2_NR_E 96 - -#define IP6_DIPM2 -#define IP6_RUL1_M2_IP6_DIPM2_BOFFSET 0 -#define IP6_RUL1_M2_IP6_DIPM2_BLEN 32 -#define IP6_RUL1_M2_IP6_DIPM2_FLAG HSL_RW - - -#define IP6_RUL1_M3 8 -#define IP6_RUL1_M3_OFFSET 0x5900c -#define IP6_RUL1_M3_E_LENGTH 4 -#define IP6_RUL1_M3_E_OFFSET 0x20 -#define IP6_RUL1_M3_NR_E 96 - -#define IP6_DIPM3 -#define IP6_RUL1_M3_IP6_DIPM3_BOFFSET 0 -#define IP6_RUL1_M3_IP6_DIPM3_BLEN 32 -#define IP6_RUL1_M3_IP6_DIPM3_FLAG HSL_RW - - -#define IP6_RUL1_M4 9 -#define IP6_RUL1_M4_OFFSET 0x59010 -#define IP6_RUL1_M4_E_LENGTH 4 -#define IP6_RUL1_M4_E_OFFSET 0x20 -#define IP6_RUL1_M4_NR_E 96 - - - - - /* IP6 Type2 Rule Field Define */ -#define IP6_RUL2_V0 0 -#define IP6_RUL2_V0_OFFSET 0x58000 -#define IP6_RUL2_V0_E_LENGTH 4 -#define IP6_RUL2_V0_E_OFFSET 0x20 -#define IP6_RUL2_V0_NR_E 96 - -#define IP6_SIPV0 -#define IP6_RUL2_V0_IP6_SIPV0_BOFFSET 0 -#define IP6_RUL2_V0_IP6_SIPv0_BLEN 32 -#define IP6_RUL2_V0_IP6_SIPV0_FLAG HSL_RW - - -#define IP6_RUL2_V1 1 -#define IP6_RUL2_V1_OFFSET 0x58004 -#define IP6_RUL2_V1_E_LENGTH 4 -#define IP6_RUL2_V1_E_OFFSET 0x20 -#define IP6_RUL2_V1_NR_E 96 - -#define IP6_SIPV1 -#define IP6_RUL2_V1_IP6_SIPV1_BOFFSET 0 -#define IP6_RUL2_V1_IP6_SIPv1_BLEN 32 -#define IP6_RUL2_V1_IP6_SIPV1_FLAG HSL_RW - - -#define IP6_RUL2_V2 2 -#define IP6_RUL2_V2_OFFSET 0x58008 -#define IP6_RUL2_V2_E_LENGTH 4 -#define IP6_RUL2_V2_E_OFFSET 0x20 -#define IP6_RUL2_V2_NR_E 96 - -#define IP6_SIPV2 -#define IP6_RUL2_V2_IP6_SIPV2_BOFFSET 0 -#define IP6_RUL2_V2_IP6_SIPv2_BLEN 32 -#define IP6_RUL2_V2_IP6_SIPV2_FLAG HSL_RW - - -#define IP6_RUL2_V3 3 -#define IP6_RUL2_V3_OFFSET 0x5800c -#define IP6_RUL2_V3_E_LENGTH 4 -#define IP6_RUL2_V3_E_OFFSET 0x20 -#define IP6_RUL2_V3_NR_E 96 - -#define IP6_SIPV3 -#define IP6_RUL2_V3_IP6_SIPV3_BOFFSET 0 -#define IP6_RUL2_V3_IP6_SIPv3_BLEN 32 -#define IP6_RUL2_V3_IP6_SIPV3_FLAG HSL_RW - - -#define IP6_RUL2_V4 4 -#define IP6_RUL2_V4_OFFSET 0x58010 -#define IP6_RUL2_V4_E_LENGTH 4 -#define IP6_RUL2_V4_E_OFFSET 0x20 -#define IP6_RUL2_V4_NR_E 96 - - -#define IP6_RUL2_M0 5 -#define IP6_RUL2_M0_OFFSET 0x59000 -#define IP6_RUL2_M0_E_LENGTH 4 -#define IP6_RUL2_M0_E_OFFSET 0x20 -#define IP6_RUL2_M0_NR_E 96 - -#define IP6_SIPM0 -#define IP6_RUL2_M0_IP6_SIPM0_BOFFSET 0 -#define IP6_RUL2_M0_IP6_SIPM0_BLEN 32 -#define IP6_RUL2_M0_IP6_SIPM0_FLAG HSL_RW - - -#define IP6_RUL2_M1 6 -#define IP6_RUL2_M1_OFFSET 0x59004 -#define IP6_RUL2_M1_E_LENGTH 4 -#define IP6_RUL2_M1_E_OFFSET 0x20 -#define IP6_RUL2_M1_NR_E 96 - -#define IP6_SIPM1 -#define IP6_RUL2_M1_IP6_DIPM1_BOFFSET 0 -#define IP6_RUL2_M1_IP6_DIPM1_BLEN 32 -#define IP6_RUL2_M1_IP6_DIPM1_FLAG HSL_RW - - -#define IP6_RUL2_M2 7 -#define IP6_RUL2_M2_OFFSET 0x59008 -#define IP6_RUL2_M2_E_LENGTH 4 -#define IP6_RUL2_M2_E_OFFSET 0x20 -#define IP6_RUL2_M2_NR_E 96 - -#define IP6_SIPM2 -#define IP6_RUL2_M2_IP6_DIPM2_BOFFSET 0 -#define IP6_RUL2_M2_IP6_DIPM2_BLEN 32 -#define IP6_RUL2_M2_IP6_DIPM2_FLAG HSL_RW - - -#define IP6_RUL2_M3 8 -#define IP6_RUL2_M3_OFFSET 0x5900c -#define IP6_RUL2_M3_E_LENGTH 4 -#define IP6_RUL2_M3_E_OFFSET 0x20 -#define IP6_RUL2_M3_NR_E 96 - -#define IP6_SIPM3 -#define IP6_RUL2_M3_IP6_SIPM3_BOFFSET 0 -#define IP6_RUL2_M3_IP6_SIPM3_BLEN 32 -#define IP6_RUL2_M3_IP6_SIPM3_FLAG HSL_RW - - -#define IP6_RUL2_M4 9 -#define IP6_RUL2_M4_OFFSET 0x59010 -#define IP6_RUL2_M4_E_LENGTH 4 -#define IP6_RUL2_M4_E_OFFSET 0x20 -#define IP6_RUL2_M4_NR_E 96 - - - - - /* IP6 Type3 Rule Field Define */ -#define IP6_RUL3_V0 0 -#define IP6_RUL3_V0_OFFSET 0x58000 -#define IP6_RUL3_V0_E_LENGTH 4 -#define IP6_RUL3_V0_E_OFFSET 0x20 -#define IP6_RUL3_V0_NR_E 96 - -#define IP6PROTV -#define IP6_RUL3_V0_IP6PROTV_BOFFSET 0 -#define IP6_RUL3_V0_IP6PROTV_BLEN 8 -#define IP6_RUL3_V0_IP6PROTV_FLAG HSL_RW - -#define IP6DSCPV -#define IP6_RUL3_V0_IP6DSCPV_BOFFSET 8 -#define IP6_RUL3_V0_IP6DSCPV_BLEN 8 -#define IP6_RUL3_V0_IP6DSCPV_FLAG HSL_RW - - -#define IP6_RUL3_V1 1 -#define IP6_RUL3_V1_OFFSET 0x58004 -#define IP6_RUL3_V1_E_LENGTH 4 -#define IP6_RUL3_V1_E_OFFSET 0x20 -#define IP6_RUL3_V1_NR_E 96 - -#define IP6LABEL1V -#define IP6_RUL3_V1_IP6LABEL1V_BOFFSET 16 -#define IP6_RUL3_V1_IP6LABEL1V_BLEN 16 -#define IP6_RUL3_V1_IP6LABEL1V_FLAG HSL_RW - - -#define IP6_RUL3_V2 2 -#define IP6_RUL3_V2_OFFSET 0x58008 -#define IP6_RUL3_V2_E_LENGTH 4 -#define IP6_RUL3_V2_E_OFFSET 0x20 -#define IP6_RUL3_V2_NR_E 96 - -#define IP6LABEL2V -#define IP6_RUL3_V2_IP6LABEL2V_BOFFSET 0 -#define IP6_RUL3_V2_IP6LABEL2V_BLEN 4 -#define IP6_RUL3_V2_IP6LABEL2V_FLAG HSL_RW - -#define IP6DPORTV -#define IP6_RUL3_V2_IP6DPORTV_BOFFSET 16 -#define IP6_RUL3_V2_IP6DPORTV_BLEN 16 -#define IP6_RUL3_V2_IP6DPORTV_FLAG HSL_RW - - -#define IP6_RUL3_V3 3 -#define IP6_RUL3_V3_OFFSET 0x5800c -#define IP6_RUL3_V3_E_LENGTH 4 -#define IP6_RUL3_V3_E_OFFSET 0x20 -#define IP6_RUL3_V3_NR_E 96 - -#define IP6TCPFLAGV -#define IP6_RUL3_V3_IP6TCPFLAGV_BOFFSET 24 -#define IP6_RUL3_V3_IP6TCPFLAGV_BLEN 6 -#define IP6_RUL3_V3_IP6TCPFLAGV_FLAG HSL_RW - -#define IP6FWDTYPV -#define IP6_RUL3_V3_IP6FWDTYPV_BOFFSET 23 -#define IP6_RUL3_V3_IP6FWDTYPV_BLEN 1 -#define IP6_RUL3_V3_IP6FWDTYPV_FLAG HSL_RW - -#define IP6DHCPV -#define IP6_RUL3_V3_IP6DHCPV_BOFFSET 22 -#define IP6_RUL3_V3_IP6DHCPV_BLEN 1 -#define IP6_RUL3_V3_IP6DHCPV_FLAG HSL_RW - -#define ICMP6_EN -#define IP6_RUL3_V3_ICMP6_EN_BOFFSET 20 -#define IP6_RUL3_V3_ICMP6_EN_BLEN 1 -#define IP6_RUL3_V3_ICMP6_EN_FLAG HSL_RW - -#define IP6SPORTV -#define IP6_RUL3_V3_IP6SPORTV_BOFFSET 0 -#define IP6_RUL3_V3_IP6SPORTV_BLEN 16 -#define IP6_RUL3_V3_IP6SPORTV_FLAG HSL_RW - -#define IP6ICMPTYPV -#define IP6_RUL3_V3_IP6ICMPTYPV_BOFFSET 8 -#define IP6_RUL3_V3_IP6ICMPTYPV_BLEN 8 -#define IP6_RUL3_V3_IP6ICMPTYPV_FLAG HSL_RW - -#define IP6ICMPCODEV -#define IP6_RUL3_V3_IP6ICMPCODEV_BOFFSET 0 -#define IP6_RUL3_V3_IP6ICMPCODEV_BLEN 8 -#define IP6_RUL3_V3_IP6ICMPCODEV_FLAG HSL_RW - - -#define IP6_RUL3_V4 4 -#define IP6_RUL3_V4_OFFSET 0x58010 -#define IP6_RUL3_V4_E_LENGTH 4 -#define IP6_RUL3_V4_E_OFFSET 0x20 -#define IP6_RUL3_V4_NR_E 96 - - -#define IP6_RUL3_M0 5 -#define IP6_RUL3_M0_OFFSET 0x59000 -#define IP6_RUL3_M0_E_LENGTH 4 -#define IP6_RUL3_M0_E_OFFSET 0x20 -#define IP6_RUL3_M0_NR_E 96 - -#define IP6PROTM -#define IP6_RUL3_M0_IP6PROTM_BOFFSET 0 -#define IP6_RUL3_M0_IP6PROTM_BLEN 8 -#define IP6_RUL3_M0_IP6PROTM_FLAG HSL_RW - -#define IP6DSCPM -#define IP6_RUL3_M0_IP6DSCPM_BOFFSET 8 -#define IP6_RUL3_M0_IP6DSCPM_BLEN 8 -#define IP6_RUL3_M0_IP6DSCPM_FLAG HSL_RW - - -#define IP6_RUL3_M1 6 -#define IP6_RUL3_M1_OFFSET 0x59004 -#define IP6_RUL3_M1_E_LENGTH 4 -#define IP6_RUL3_M1_E_OFFSET 0x20 -#define IP6_RUL3_M1_NR_E 96 - -#define IP6LABEL1M -#define IP6_RUL3_M1_IP6LABEL1M_BOFFSET 16 -#define IP6_RUL3_M1_IP6LABEL1M_BLEN 16 -#define IP6_RUL3_M1_IP6LABEL1M_FLAG HSL_RW - - -#define IP6_RUL3_M2 7 -#define IP6_RUL3_M2_OFFSET 0x59008 -#define IP6_RUL3_M2_E_LENGTH 4 -#define IP6_RUL3_M2_E_OFFSET 0x20 -#define IP6_RUL3_M2_NR_E 96 - -#define IP6LABEL2M -#define IP6_RUL3_M2_IP6LABEL2M_BOFFSET 0 -#define IP6_RUL3_M2_IP6LABEL2M_BLEN 4 -#define IP6_RUL3_M2_IP6LABEL21M_FLAG HSL_RW - -#define IP6DPORTM -#define IP6_RUL3_M2_IP6DPORTM_BOFFSET 16 -#define IP6_RUL3_M2_IP6DPORTM_BLEN 16 -#define IP6_RUL3_M2_IP6DPORTM_FLAG HSL_RW - - -#define IP6_RUL3_M3 8 -#define IP6_RUL3_M3_OFFSET 0x5900c -#define IP6_RUL3_M3_E_LENGTH 4 -#define IP6_RUL3_M3_E_OFFSET 0x20 -#define IP6_RUL3_M3_NR_E 96 - -#define IP6TCPFLAGM -#define IP6_RUL3_M3_IP6TCPFLAGM_BOFFSET 24 -#define IP6_RUL3_M3_IP6TCPFLAGM_BLEN 6 -#define IP6_RUL3_M3_IP6TCPFLAGM_FLAG HSL_RW - -#define IP6RWDTYPM -#define IP6_RUL3_M3_IP6RWDTYPV_BOFFSET 23 -#define IP6_RUL3_M3_IP6RWDTYPV_BLEN 1 -#define IP6_RUL3_M3_IP6RWDTYPV_FLAG HSL_RW - -#define IP6DHCPM -#define IP6_RUL3_M3_IP6DHCPM_BOFFSET 22 -#define IP6_RUL3_M3_IP6DHCPM_BLEN 1 -#define IP6_RUL3_M3_IP6DHCPM_FLAG HSL_RW - -#define IP6DPORTM_EN -#define IP6_RUL3_M3_IP6DPORTM_EN_BOFFSET 17 -#define IP6_RUL3_M3_IP6DPORTM_EN_BLEN 1 -#define IP6_RUL3_M3_IP6DPORTM_EN_FLAG HSL_RW - -#define IP6SPORTM_EN -#define IP6_RUL3_M3_IP6SPORTM_EN_BOFFSET 16 -#define IP6_RUL3_M3_IP6SPORTM_EN_BLEN 1 -#define IP6_RUL3_M3_IP6SPORTM_EN_FLAG HSL_RW - -#define IP6SPORTM -#define IP6_RUL3_M3_IP6SPORTM_BOFFSET 0 -#define IP6_RUL3_M3_IP6SPORTM_BLEN 16 -#define IP6_RUL3_M3_IP6SPORTM_FLAG HSL_RW - -#define IP6ICMPTYPM -#define IP6_RUL3_M3_IP6ICMPTYPM_BOFFSET 8 -#define IP6_RUL3_M3_IP6ICMPTYPM_BLEN 8 -#define IP6_RUL3_M3_IP6ICMPTYPM_FLAG HSL_RW - -#define IP6ICMPCODEM -#define IP6_RUL3_M3_IP6ICMPCODEM_BOFFSET 0 -#define IP6_RUL3_M3_IP6ICMPCODEM_BLEN 8 -#define IP6_RUL3_M3_IP6ICMPCODEM_FLAG HSL_RW - - -#define IP6_RUL3_M4 9 -#define IP6_RUL3_M4_OFFSET 0x59010 -#define IP6_RUL3_M4_E_LENGTH 4 -#define IP6_RUL3_M4_E_OFFSET 0x20 -#define IP6_RUL3_M4_NR_E 96 - - - - - /* Enhanced MAC Type Rule Field Define */ -#define EHMAC_RUL_V0 0 -#define EHMAC_RUL_V0_OFFSET 0x58000 -#define EHMAC_RUL_V0_E_LENGTH 4 -#define EHMAC_RUL_V0_E_OFFSET 0x20 -#define EHMAC_RUL_V0_NR_E 96 - -#define DAV_BYTE2 -#define EHMAC_RUL_V0_DAV_BYTE2_BOFFSET 24 -#define EHMAC_RUL_V0_DAV_BYTE2_BLEN 8 -#define EHMAC_RUL_V0_DAV_BYTE2_FLAG HSL_RW - -#define DAV_BYTE3 -#define EHMAC_RUL_V0_DAV_BYTE3_BOFFSET 16 -#define EHMAC_RUL_V0_DAV_BYTE3_BLEN 8 -#define EHMAC_RUL_V0_DAV_BYTE3_FLAG HSL_RW - -#define DAV_BYTE4 -#define EHMAC_RUL_V0_DAV_BYTE4_BOFFSET 8 -#define EHMAC_RUL_V0_DAV_BYTE4_BLEN 8 -#define EHMAC_RUL_V0_DAV_BYTE4_FLAG HSL_RW - -#define DAV_BYTE5 -#define EHMAC_RUL_V0_DAV_BYTE5_BOFFSET 0 -#define EHMAC_RUL_V0_DAV_BYTE5_BLEN 8 -#define EHMAC_RUL_V0_DAV_BYTE5_FLAG HSL_RW - - -#define EHMAC_RUL_V1 1 -#define EHMAC_RUL_V1_OFFSET 0x58004 -#define EHMAC_RUL_V1_E_LENGTH 4 -#define EHMAC_RUL_V1_E_OFFSET 0x20 -#define EHMAC_RUL_V1_NR_E 96 - -#define SAV_BYTE4 -#define EHMAC_RUL_V1_SAV_BYTE4_BOFFSET 24 -#define EHMAC_RUL_V1_SAV_BYTE4_BLEN 8 -#define EHMAC_RUL_V1_SAV_BYTE4_FLAG HSL_RW - -#define SAV_BYTE5 -#define EHMAC_RUL_V1_SAV_BYTE5_BOFFSET 16 -#define EHMAC_RUL_V1_SAV_BYTE5_BLEN 8 -#define EHMAC_RUL_V1_SAV_BYTE5_FLAG HSL_RW - -#define DAV_BYTE0 -#define EHMAC_RUL_V1_DAV_BYTE0_BOFFSET 8 -#define EHMAC_RUL_V1_DAV_BYTE0_BLEN 8 -#define EHMAC_RUL_V1_DAV_BYTE0_FLAG HSL_RW - -#define DAV_BYTE1 -#define EHMAC_RUL_V1_DAV_BYTE1_BOFFSET 0 -#define EHMAC_RUL_V1_DAV_BYTE1_BLEN 8 -#define EHMAC_RUL_V1_DAV_BYTE1_FLAG HSL_RW - - -#define EHMAC_RUL_V2 2 -#define EHMAC_RUL_V2_OFFSET 0x58008 -#define EHMAC_RUL_V2_E_LENGTH 4 -#define EHMAC_RUL_V2_E_OFFSET 0x20 -#define EHMAC_RUL_V2_NR_E 96 - -#define CTAG_VIDLV -#define EHMAC_RUL_V2_CTAG_VIDLV_BOFFSET 24 -#define EHMAC_RUL_V2_CTAG_VIDLV_BLEN 8 -#define EHMAC_RUL_V2_CTAG_VIDLV_FLAG HSL_RW - -#define STAG_PRIV -#define EHMAC_RUL_V2_STAG_PRIV_BOFFSET 21 -#define EHMAC_RUL_V2_STAG_PRIV_BLEN 3 -#define EHMAC_RUL_V2_STAG_PRIV_FLAG HSL_RW - -#define STAG_DEIV -#define EHMAC_RUL_V2_STAG_DEIV_BOFFSET 20 -#define EHMAC_RUL_V2_STAG_DEIV_BLEN 1 -#define EHMAC_RUL_V2_STAG_DEIV_FLAG HSL_RW - -#define STAG_VIDV -#define EHMAC_RUL_V2_STAG_VIDV_BOFFSET 8 -#define EHMAC_RUL_V2_STAG_VIDV_BLEN 12 -#define EHMAC_RUL_V2_STAG_VIDV_FLAG HSL_RW - -#define SAV_BYTE3 -#define EHMAC_RUL_V2_SAV_BYTE3_BOFFSET 0 -#define EHMAC_RUL_V2_SAV_BYTE3_BLEN 8 -#define EHMAC_RUL_V2_SAV_BYTE3_FLAG HSL_RW - - -#define EHMAC_RUL_V3 3 -#define EHMAC_RUL_V3_ID 13 -#define EHMAC_RUL_V3_OFFSET 0x5800c -#define EHMAC_RUL_V3_E_LENGTH 4 -#define EHMAC_RUL_V3_E_OFFSET 0x20 -#define EHMAC_RUL_V3_NR_E 96 - -#define STAGGEDM -#define EHMAC_RUL_V3_STAGGEDM_BOFFSET 31 -#define EHMAC_RUL_V3_STAGGEDM_BLEN 1 -#define EHMAC_RUL_V3_STAGGEDM_FLAG HSL_RW - -#define STAGGEDV -#define EHMAC_RUL_V3_STAGGEDV_BOFFSET 30 -#define EHMAC_RUL_V3_STAGGEDV_BLEN 1 -#define EHMAC_RUL_V3_STAGGEDV_FLAG HSL_RW - -#define DA_EN -#define EHMAC_RUL_V3_DA_EN_BOFFSET 25 -#define EHMAC_RUL_V3_DA_EN_BLEN 1 -#define EHMAC_RUL_V3_DA_EN_FLAG HSL_RW - -#define SVIDMSK -#define EHMAC_RUL_V3_SVIDMSK_BOFFSET 24 -#define EHMAC_RUL_V3_SVIDMSK_BLEN 1 -#define EHMAC_RUL_V3_SVIDMSK_FLAG HSL_RW - -#define ETHTYPV -#define EHMAC_RUL_V3_ETHTYPV_BOFFSET 8 -#define EHMAC_RUL_V3_ETHTYPV_BLEN 16 -#define EHMAC_RUL_V3_ETHTYPV_FLAG HSL_RW - -#define CTAG_PRIV -#define EHMAC_RUL_V3_CTAG_PRIV_BOFFSET 5 -#define EHMAC_RUL_V3_CTAG_PRIV_BLEN 3 -#define EHMAC_RUL_V3_CTAG_PRIV_FLAG HSL_RW - -#define CTAG_CFIV -#define EHMAC_RUL_V3_CTAG_CFIV_BOFFSET 4 -#define EHMAC_RUL_V3_CTAG_CFIV_BLEN 1 -#define EHMAC_RUL_V3_CTAG_CFIV_FLAG HSL_RW - -#define CTAG_VIDHV -#define EHMAC_RUL_V3_CTAG_VIDHV_BOFFSET 0 -#define EHMAC_RUL_V3_CTAG_VIDHV_BLEN 4 -#define EHMAC_RUL_V3_CTAG_VIDHV_FLAG HSL_RW - - -#define EHMAC_RUL_V4 4 -#define EHMAC_RUL_V4_OFFSET 0x58010 -#define EHMAC_RUL_V4_E_LENGTH 4 -#define EHMAC_RUL_V4_E_OFFSET 0x20 -#define EHMAC_RUL_V4_NR_E 96 - - -#define EHMAC_RUL_M0 5 -#define EHMAC_RUL_M0_OFFSET 0x59000 -#define EHMAC_RUL_M0_E_LENGTH 4 -#define EHMAC_RUL_M0_E_OFFSET 0x20 -#define EHMAC_RUL_M0_NR_E 96 - -#define DAM_BYTE2 -#define EHMAC_RUL_M0_DAM_BYTE2_BOFFSET 24 -#define EHMAC_RUL_M0_DAM_BYTE2_BLEN 8 -#define EHMAC_RUL_M0_DAM_BYTE2_FLAG HSL_RW - -#define DAM_BYTE3 -#define EHMAC_RUL_M0_DAM_BYTE3_BOFFSET 16 -#define EHMAC_RUL_M0_DAM_BYTE3_BLEN 8 -#define EHMAC_RUL_M0_DAM_BYTE3_FLAG HSL_RW - -#define DAM_BYTE4 -#define EHMAC_RUL_M0_DAM_BYTE4_BOFFSET 8 -#define EHMAC_RUL_M0_DAM_BYTE4_BLEN 8 -#define EHMAC_RUL_M0_DAM_BYTE4_FLAG HSL_RW - -#define DAM_BYTE5 -#define EHMAC_RUL_M0_DAM_BYTE5_BOFFSET 0 -#define EHMAC_RUL_M0_DAM_BYTE5_BLEN 8 -#define EHMAC_RUL_M0_DAM_BYTE5_FLAG HSL_RW - - -#define EHMAC_RUL_M1 6 -#define EHMAC_RUL_M1_OFFSET 0x59004 -#define EHMAC_RUL_M1_E_LENGTH 4 -#define EHMAC_RUL_M1_E_OFFSET 0x20 -#define EHMAC_RUL_M1_NR_E 96 - -#define SAM_BYTE4 -#define EHMAC_RUL_M1_SAM_BYTE4_BOFFSET 24 -#define EHMAC_RUL_M1_SAM_BYTE4_BLEN 8 -#define EHMAC_RUL_M1_SAM_BYTE4_FLAG HSL_RW - -#define SAM_BYTE5 -#define EHMAC_RUL_M1_SAM_BYTE5_BOFFSET 16 -#define EHMAC_RUL_M1_SAM_BYTE5_BLEN 8 -#define EHMAC_RUL_M1_SAM_BYTE5_FLAG HSL_RW - -#define DAM_BYTE0 -#define EHMAC_RUL_M1_DAM_BYTE0_BOFFSET 8 -#define EHMAC_RUL_M1_DAM_BYTE0_BLEN 8 -#define EHMAC_RUL_M1_DAM_BYTE0_FLAG HSL_RW - -#define DAM_BYTE1 -#define EHMAC_RUL_M1_DAM_BYTE1_BOFFSET 0 -#define EHMAC_RUL_M1_DAM_BYTE1_BLEN 8 -#define EHMAC_RUL_M1_DAM_BYTE1_FLAG HSL_RW - - -#define EHMAC_RUL_M2 7 -#define EHMAC_RUL_M2_OFFSET 0x59008 -#define EHMAC_RUL_M2_E_LENGTH 4 -#define EHMAC_RUL_M2_E_OFFSET 0x20 -#define EHMAC_RUL_M2_NR_E 96 - -#define CTAG_VIDLM -#define EHMAC_RUL_M2_CTAG_VIDLM_BOFFSET 24 -#define EHMAC_RUL_M2_CTAG_VIDLM_BLEN 8 -#define EHMAC_RUL_M2_CTAG_VIDLM_FLAG HSL_RW - -#define STAG_PRIM -#define EHMAC_RUL_M2_STAG_PRIM_BOFFSET 21 -#define EHMAC_RUL_M2_STAG_PRIM_BLEN 3 -#define EHMAC_RUL_M2_STAG_PRIM_FLAG HSL_RW - -#define STAG_DEIM -#define EHMAC_RUL_M2_STAG_DEIM_BOFFSET 20 -#define EHMAC_RUL_M2_STAG_DEIM_BLEN 1 -#define EHMAC_RUL_M2_STAG_DEIM_FLAG HSL_RW - -#define STAG_VIDM -#define EHMAC_RUL_M2_STAG_VIDM_BOFFSET 8 -#define EHMAC_RUL_M2_STAG_VIDM_BLEN 12 -#define EHMAC_RUL_M2_STAG_VIDM_FLAG HSL_RW - -#define SAM_BYTE3 -#define EHMAC_RUL_M2_SAM_BYTE3_BOFFSET 0 -#define EHMAC_RUL_M2_SAM_BYTE3_BLEN 8 -#define EHMAC_RUL_M2_SAM_BYTE3_FLAG HSL_RW - - -#define EHMAC_RUL_M3 8 -#define EHMAC_RUL_M3_OFFSET 0x5900c -#define EHMAC_RUL_M3_E_LENGTH 4 -#define EHMAC_RUL_M3_E_OFFSET 0x20 -#define EHMAC_RUL_M3_NR_E 96 - -#define ETHTYPM -#define EHMAC_RUL_M3_ETHTYPM_BOFFSET 8 -#define EHMAC_RUL_M3_ETHTYPM_BLEN 16 -#define EHMAC_RUL_M3_ETHTYPM_FLAG HSL_RW - -#define CTAG_PRIM -#define EHMAC_RUL_M3_CTAG_PRIM_BOFFSET 5 -#define EHMAC_RUL_M3_CTAG_PRIM_BLEN 3 -#define EHMAC_RUL_M3_CTAG_PRIM_FLAG HSL_RW - -#define CTAG_CFIM -#define EHMAC_RUL_M3_CTAG_CFIM_BOFFSET 4 -#define EHMAC_RUL_M3_CTAG_CFIM_BLEN 1 -#define EHMAC_RUL_M3_CTAG_CFIM_FLAG HSL_RW - -#define CTAG_VIDHM -#define EHMAC_RUL_M3_CTAG_VIDHM_BOFFSET 0 -#define EHMAC_RUL_M3_CTAG_VIDHM_BLEN 4 -#define EHMAC_RUL_M3_CTAG_VIDHM_FLAG HSL_RW - - -#define EHMAC_RUL_M4 9 -#define EHMAC_RUL_M4_OFFSET 0x59010 -#define EHMAC_RUL_M4_E_LENGTH 4 -#define EHMAC_RUL_M4_E_OFFSET 0x20 -#define EHMAC_RUL_M4_NR_E 96 - -#define CTAGGEDM -#define EHMAC_RUL_M4_CTAGGEDM_BOFFSET 5 -#define EHMAC_RUL_M4_CTAGGEDM_BLEN 1 -#define EHMAC_RUL_M4_CTAGGEDM_FLAG HSL_RW - -#define CTAGGEDV -#define EHMAC_RUL_M4_CTAGGEDV_BOFFSET 4 -#define EHMAC_RUL_M4_CTAGGEDV_BLEN 1 -#define EHMAC_RUL_M4_CTAGGEDV_FLAG HSL_RW - -#define CVIDMSK -#define EHMAC_RUL_M4_CVIDMSK_BOFFSET 3 -#define EHMAC_RUL_M4_CVIDMSK_BLEN 1 -#define EHMAC_RUL_M4_CVIDMSK_FLAG HSL_RW - - - - - /* PPPoE Session Table Define */ -#define PPPOE_SESSION -#define PPPOE_SESSION_OFFSET 0x5f000 -#define PPPOE_SESSION_E_LENGTH 4 -#define PPPOE_SESSION_E_OFFSET 0x4 -#define PPPOE_SESSION_NR_E 16 - -#define VRF_ID -#define PPPOE_SESSION_VRF_ID_BOFFSET 18 -#define PPPOE_SESSION_VRF_ID_BLEN 3 -#define PPPOE_SESSION_VRF_ID_FLAG HSL_RW - -#define ENTRY_VALID -#define PPPOE_SESSION_ENTRY_VALID_BOFFSET 16 -#define PPPOE_SESSION_ENTRY_VALID_BLEN 2 -#define PPPOE_SESSION_ENTRY_VALID_FLAG HSL_RW - -#define SEESION_ID -#define PPPOE_SESSION_SEESION_ID_BOFFSET 0 -#define PPPOE_SESSION_SEESION_ID_BLEN 16 -#define PPPOE_SESSION_SEESION_ID_FLAG HSL_RW - - - -#define PPPOE_EDIT -#define PPPOE_EDIT_OFFSET 0x02200 -#define PPPOE_EDIT_E_LENGTH 4 -#define PPPOE_EDIT_E_OFFSET 0x10 -#define PPPOE_EDIT_NR_E 16 - -#define EDIT_ID -#define PPPOE_EDIT_EDIT_ID_BOFFSET 0 -#define PPPOE_EDIT_EDIT_ID_BLEN 16 -#define PPPOE_EDIT_EDIT_ID_FLAG HSL_RW - - - - - /* L3 Host Entry Define */ -#define HOST_ENTRY0 -#define HOST_ENTRY0_OFFSET 0x0e80 -#define HOST_ENTRY0_E_LENGTH 4 -#define HOST_ENTRY0_E_OFFSET 0x0 -#define HOST_ENTRY0_NR_E 1 - -#define IP_ADDR -#define HOST_ENTRY0_IP_ADDR_BOFFSET 0 -#define HOST_ENTRY0_IP_ADDR_BLEN 32 -#define HOST_ENTRY0_IP_ADDR_FLAG HSL_RW - - -#define HOST_ENTRY1 -#define HOST_ENTRY1_OFFSET 0x0e84 -#define HOST_ENTRY1_E_LENGTH 4 -#define HOST_ENTRY1_E_OFFSET 0x0 -#define HOST_ENTRY1_NR_E 1 - - -#define HOST_ENTRY2 -#define HOST_ENTRY2_OFFSET 0x0e88 -#define HOST_ENTRY2_E_LENGTH 4 -#define HOST_ENTRY2_E_OFFSET 0x0 -#define HOST_ENTRY2_NR_E 1 - - -#define HOST_ENTRY3 -#define HOST_ENTRY3_OFFSET 0x0e8c -#define HOST_ENTRY3_E_LENGTH 4 -#define HOST_ENTRY3_E_OFFSET 0x0 -#define HOST_ENTRY3_NR_E 1 - - -#define HOST_ENTRY4 -#define HOST_ENTRY4_OFFSET 0x0e90 -#define HOST_ENTRY4_E_LENGTH 4 -#define HOST_ENTRY4_E_OFFSET 0x0 -#define HOST_ENTRY4_NR_E 1 - -#define MAC_ADDR2 -#define HOST_ENTRY4_MAC_ADDR2_BOFFSET 24 -#define HOST_ENTRY4_MAC_ADDR2_BLEN 8 -#define HOST_ENTRY4_MAC_ADDR2_FLAG HSL_RW - -#define MAC_ADDR3 -#define HOST_ENTRY4_MAC_ADDR3_BOFFSET 16 -#define HOST_ENTRY4_MAC_ADDR3_BLEN 8 -#define HOST_ENTRY4_MAC_ADDR3_FLAG HSL_RW - -#define MAC_ADDR4 -#define HOST_ENTRY4_MAC_ADDR4_BOFFSET 8 -#define HOST_ENTRY4_MAC_ADDR4_BLEN 8 -#define HOST_ENTRY4_MAC_ADDR4_FLAG HSL_RW - -#define MAC_ADDR5 -#define HOST_ENTRY4_MAC_ADDR5_BOFFSET 0 -#define HOST_ENTRY4_MAC_ADDR5_BLEN 8 -#define HOST_ENTRY4_MAC_ADDR5_FLAG HSL_RW - -#define HOST_ENTRY5 -#define HOST_ENTRY5_OFFSET 0x0e94 -#define HOST_ENTRY5_E_LENGTH 4 -#define HOST_ENTRY5_E_OFFSET 0x0 -#define HOST_ENTRY5_NR_E 1 - -#define CPU_ADDR -#define HOST_ENTRY5_CPU_ADDR_BOFFSET 31 -#define HOST_ENTRY5_CPU_ADDR_BLEN 1 -#define HOST_ENTRY5_CPU_ADDR_FLAG HSL_RW - -#define SRC_PORT -#define HOST_ENTRY5_SRC_PORT_BOFFSET 28 -#define HOST_ENTRY5_SRC_PORT_BLEN 3 -#define HOST_ENTRY5_SRC_PORT_FLAG HSL_RW - -#define INTF_ID -#define HOST_ENTRY5_INTF_ID_BOFFSET 16 -#define HOST_ENTRY5_INTF_ID_BLEN 12 -#define HOST_ENTRY5_INTF_ID_FLAG HSL_RW - -#define MAC_ADDR0 -#define HOST_ENTRY5_MAC_ADDR0_BOFFSET 8 -#define HOST_ENTRY5_MAC_ADDR0_BLEN 8 -#define HOST_ENTRY5_MAC_ADDR0_FLAG HSL_RW - -#define MAC_ADDR1 -#define HOST_ENTRY5_MAC_ADDR1_BOFFSET 0 -#define HOST_ENTRY5_MAC_ADDR1_BLEN 8 -#define HOST_ENTRY5_MAC_ADDR1_FLAG HSL_RW - - -#define HOST_ENTRY6 -#define HOST_ENTRY6_OFFSET 0x0e98 -#define HOST_ENTRY6_E_LENGTH 4 -#define HOST_ENTRY6_E_OFFSET 0x0 -#define HOST_ENTRY6_NR_E 1 - -#define LB_BIT -#define HOST_ENTRY6_LB_BIT_BOFFSET 19 -#define HOST_ENTRY6_LB_BIT_BLEN 3 -#define HOST_ENTRY6_LB_BIT_FLAG HSL_RW - -#define VRF_ID -#define HOST_ENTRY6_VRF_ID_BOFFSET 16 -#define HOST_ENTRY6_VRF_ID_BLEN 3 -#define HOST_ENTRY6_VRF_ID_FLAG HSL_RW - -#define IP_VER -#define HOST_ENTRY6_IP_VER_BOFFSET 15 -#define HOST_ENTRY6_IP_VER_BLEN 1 -#define HOST_ENTRY6_IP_VER_FLAG HSL_RW - -#define AGE_FLAG -#define HOST_ENTRY6_AGE_FLAG_BOFFSET 12 -#define HOST_ENTRY6_AGE_FLAG_BLEN 3 -#define HOST_ENTRY6_AGE_FLAG_FLAG HSL_RW - -#define PPPOE_EN -#define HOST_ENTRY6_PPPOE_EN_BOFFSET 11 -#define HOST_ENTRY6_PPPOE_EN_BLEN 1 -#define HOST_ENTRY6_PPPOE_EN_FLAG HSL_RW - -#define PPPOE_IDX -#define HOST_ENTRY6_PPPOE_IDX_BOFFSET 7 -#define HOST_ENTRY6_PPPOE_IDX_BLEN 4 -#define HOST_ENTRY6_PPPOE_IDX_FLAG HSL_RW - -#define CNT_EN -#define HOST_ENTRY6_CNT_EN_BOFFSET 6 -#define HOST_ENTRY6_CNT_EN_BLEN 1 -#define HOST_ENTRY6_CNT_EN_FLAG HSL_RW - -#define CNT_IDX -#define HOST_ENTRY6_CNT_IDX_BOFFSET 2 -#define HOST_ENTRY6_CNT_IDX_BLEN 4 -#define HOST_ENTRY6_CNT_IDX_FLAG HSL_RW - -#define ACTION -#define HOST_ENTRY6_ACTION_BOFFSET 0 -#define HOST_ENTRY6_ACTION_BLEN 2 -#define HOST_ENTRY6_ACTION_FLAG HSL_RW - - -#define HOST_ENTRY7 -#define HOST_ENTRY7_OFFSET 0x0e58 -#define HOST_ENTRY7_E_LENGTH 4 -#define HOST_ENTRY7_E_OFFSET 0x0 -#define HOST_ENTRY7_NR_E 1 - -#define TBL_BUSY -#define HOST_ENTRY7_TBL_BUSY_BOFFSET 31 -#define HOST_ENTRY7_TBL_BUSY_BLEN 1 -#define HOST_ENTRY7_TBL_BUSY_FLAG HSL_RW - -#define SPEC_SYNC -#define HOST_ENTRY7_SPEC_SYNC_BOFFSET 23 -#define HOST_ENTRY7_SPEC_SYNC_BLEN 1 -#define HOST_ENTRY7_SPEC_SYNC_FLAG HSL_RW - -#define SPEC_SP -#define HOST_ENTRY7_SPEC_SP_BOFFSET 22 -#define HOST_ENTRY7_SPEC_SP_BLEN 1 -#define HOST_ENTRY7_SPEC_SP_FLAG HSL_RW - -#define SPEC_VID -#define HOST_ENTRY7_SPEC_VID_BOFFSET 21 -#define HOST_ENTRY7_SPEC_VID_BLEN 1 -#define HOST_ENTRY7_SPEC_VID_FLAG HSL_RW - -#define SPEC_PIP -#define HOST_ENTRY7_SPEC_PIP_BOFFSET 20 -#define HOST_ENTRY7_SPEC_PIP_BLEN 1 -#define HOST_ENTRY7_SPEC_PIP_FLAG HSL_RW - -#define SPEC_SIP -#define HOST_ENTRY7_SPEC_SIP_BOFFSET 19 -#define HOST_ENTRY7_SPEC_SIP_BLEN 1 -#define HOST_ENTRY7_SPEC_SIP_FLAG HSL_RW - -#define SPEC_STATUS -#define HOST_ENTRY7_SPEC_STATUS_BOFFSET 18 -#define HOST_ENTRY7_SPEC_STATUS_BLEN 1 -#define HOST_ENTRY7_SPEC_STATUS_FLAG HSL_RW - -#define TBL_IDX -#define HOST_ENTRY7_TBL_IDX_BOFFSET 8 -#define HOST_ENTRY7_TBL_IDX_BLEN 10 -#define HOST_ENTRY7_TBL_IDX_FLAG HSL_RW - -#define TBL_STAUS -#define HOST_ENTRY7_TBL_STAUS_BOFFSET 7 -#define HOST_ENTRY7_TBL_STAUS_BLEN 1 -#define HOST_ENTRY7_TBL_STAUS_FLAG HSL_RW - -#define TBL_SEL -#define HOST_ENTRY7_TBL_SEL_BOFFSET 4 -#define HOST_ENTRY7_TBL_SEL_BLEN 2 -#define HOST_ENTRY7_TBL_SEL_FLAG HSL_RW - -#define ENTRY_FUNC -#define HOST_ENTRY7_ENTRY_FUNC_BOFFSET 0 -#define HOST_ENTRY7_ENTRY_FUNC_BLEN 3 -#define HOST_ENTRY7_ENTRY_FUNC_FLAG HSL_RW - - - - -#define NAT_ENTRY0 -#define NAT_ENTRY0_OFFSET 0x0e80 -#define NAT_ENTRY0_E_LENGTH 4 -#define NAT_ENTRY0_E_OFFSET 0x0 -#define NAT_ENTRY0_NR_E 1 - -#define IP_ADDR -#define NAT_ENTRY0_IP_ADDR_BOFFSET 0 -#define NAT_ENTRY0_IP_ADDR_BLEN 32 -#define NAT_ENTRY0_IP_ADDR_FLAG HSL_RW - - -#define NAT_ENTRY1 -#define NAT_ENTRY1_OFFSET 0x0e84 -#define NAT_ENTRY1_E_LENGTH 4 -#define NAT_ENTRY1_E_OFFSET 0x0 -#define NAT_ENTRY1_NR_E 1 - -#define PRV_IPADDR0 -#define NAT_ENTRY1_PRV_IPADDR0_BOFFSET 24 -#define NAT_ENTRY1_PRV_IPADDR0_BLEN 8 -#define NAT_ENTRY1_PRV_IPADDR0_FLAG HSL_RW - -#define PORT_RANGE -#define NAT_ENTRY1_PORT_RANGE_BOFFSET 16 -#define NAT_ENTRY1_PORT_RANGE_BLEN 8 -#define NAT_ENTRY1_PORT_RANGE_FLAG HSL_RW - -#define PORT_NUM -#define NAT_ENTRY1_PORT_NUM_BOFFSET 0 -#define NAT_ENTRY1_PORT_NUM_BLEN 16 -#define NAT_ENTRY1_PORT_NUM_FLAG HSL_RW - - -#define NAT_ENTRY2 -#define NAT_ENTRY2_OFFSET 0x0e88 -#define NAT_ENTRY2_E_LENGTH 4 -#define NAT_ENTRY2_E_OFFSET 0x0 -#define NAT_ENTRY2_NR_E 1 - -#define HASH_KEY -#define NAT_ENTRY2_HASH_KEY_BOFFSET 30 -#define NAT_ENTRY2_HASH_KEY_BLEN 2 -#define NAT_ENTRY2_HASH_KEY_FLAG HSL_RW - -#define ACTION -#define NAT_ENTRY2_ACTION_BOFFSET 28 -#define NAT_ENTRY2_ACTION_BLEN 2 -#define NAT_ENTRY2_ACTION_FLAG HSL_RW - -#define CNT_EN -#define NAT_ENTRY2_CNT_EN_BOFFSET 27 -#define NAT_ENTRY2_CNT_EN_BLEN 1 -#define NAT_ENTRY2_CNT_EN_FLAG HSL_RW - -#define CNT_IDX -#define NAT_ENTRY2_CNT_IDX_BOFFSET 24 -#define NAT_ENTRY2_CNT_IDX_BLEN 3 -#define NAT_ENTRY2_CNT_IDX_FLAG HSL_RW - -#define PRV_IPADDR1 -#define NAT_ENTRY2_PRV_IPADDR1_BOFFSET 0 -#define NAT_ENTRY2_PRV_IPADDR1_BLEN 24 -#define NAT_ENTRY2_PRV_IPADDR1_FLAG HSL_RW - - -#define NAT_ENTRY3 -#define NAT_ENTRY3_OFFSET 0x0e8c -#define NAT_ENTRY3_E_LENGTH 4 -#define NAT_ENTRY3_E_OFFSET 0x0 -#define NAT_ENTRY3_NR_E 1 - -#define VRF_ID -#define NAT_ENTRY3_VRF_ID_BOFFSET 4 -#define NAT_ENTRY3_VRF_ID_BLEN 3 -#define NAT_ENTRY3_VRF_ID_FLAG HSL_RW - -#define ENTRY_VALID -#define NAT_ENTRY3_ENTRY_VALID_BOFFSET 3 -#define NAT_ENTRY3_ENTRY_VALID_BLEN 1 -#define NAT_ENTRY3_ENTRY_VALID_FLAG HSL_RW - -#define PORT_EN -#define NAT_ENTRY3_PORT_EN_BOFFSET 2 -#define NAT_ENTRY3_PORT_EN_BLEN 1 -#define NAT_ENTRY3_PORT_EN_FLAG HSL_RW - -#define PRO_TYP -#define NAT_ENTRY3_PRO_TYP_BOFFSET 0 -#define NAT_ENTRY3_PRO_TYP_BLEN 2 -#define NAT_ENTRY3_PRO_TYP_FLAG HSL_RW - - -#define NAPT_ENTRY0 -#define NAPT_ENTRY0_OFFSET 0x0e80 -#define NAPT_ENTRY0_E_LENGTH 4 -#define NAPT_ENTRY0_E_OFFSET 0x0 -#define NAPT_ENTRY0_NR_E 1 - -#define DST_IPADDR -#define NAPT_ENTRY0_DST_IPADDR_BOFFSET 0 -#define NAPT_ENTRY0_DST_IPADDR_BLEN 32 -#define NAPT_ENTRY0_DST_IPADDR_FLAG HSL_RW - - -#define NAPT_ENTRY1 -#define NAPT_ENTRY1_OFFSET 0x0e84 -#define NAPT_ENTRY1_E_LENGTH 4 -#define NAPT_ENTRY1_E_OFFSET 0x0 -#define NAPT_ENTRY1_NR_E 1 - -#define SRC_PORT -#define NAPT_ENTRY1_SRC_PORT_BOFFSET 16 -#define NAPT_ENTRY1_SRC_PORT_BLEN 16 -#define NAPT_ENTRY1_SRC_PORT_FLAG HSL_RW - -#define DST_PORT -#define NAPT_ENTRY1_DST_PORT_BOFFSET 0 -#define NAPT_ENTRY1_DST_PORT_BLEN 16 -#define NAPT_ENTRY1_DST_PORT_FLAG HSL_RW - - -#define NAPT_ENTRY2 -#define NAPT_ENTRY2_OFFSET 0x0e88 -#define NAPT_ENTRY2_E_LENGTH 4 -#define NAPT_ENTRY2_E_OFFSET 0x0 -#define NAPT_ENTRY2_NR_E 1 - -#define SRC_IPADDR0 -#define NAPT_ENTRY2_SRC_IPADDR0_BOFFSET 20 -#define NAPT_ENTRY2_SRC_IPADDR0_BLEN 12 -#define NAPT_ENTRY2_SRC_IPADDR0_FLAG HSL_RW - -#define TRANS_IPADDR -#define NAPT_ENTRY2_TRANS_IPADDR_BOFFSET 16 -#define NAPT_ENTRY2_TRANS_IPADDR_BLEN 4 -#define NAPT_ENTRY2_TRANS_IPADDR_FLAG HSL_RW - -#define TRANS_PORT -#define NAPT_ENTRY2_TRANS_PORT_BOFFSET 0 -#define NAPT_ENTRY2_TRANS_PORT_BLEN 16 -#define NAPT_ENTRY2_TRANS_PORT_FLAG HSL_RW - - -#define NAPT_ENTRY3 -#define NAPT_ENTRY3_OFFSET 0x0e8c -#define NAPT_ENTRY3_E_LENGTH 4 -#define NAPT_ENTRY3_E_OFFSET 0x0 -#define NAPT_ENTRY3_NR_E 1 - -#define PRIORITY_EN -#define NAPT_ENTRY3_PRIORITY_EN_BOFFSET 31 -#define NAPT_ENTRY3_PRIORITY_EN_BLEN 1 -#define NAPT_ENTRY3_PRIORITY_EN_FLAG HSL_RW - -#define PRIORITY_VAL -#define NAPT_ENTRY3_PRIORITY_VAL_BOFFSET 28 -#define NAPT_ENTRY3_PRIORITY_VAL_BLEN 3 -#define NAPT_ENTRY3_PRIORITY_VAL_FLAG HSL_RW - -#define CNT_EN -#define NAPT_ENTRY3_CNT_EN_BOFFSET 27 -#define NAPT_ENTRY3_CNT_EN_BLEN 1 -#define NAPT_ENTRY3_CNT_EN_FLAG HSL_RW - -#define CNT_IDX -#define NAPT_ENTRY3_CNT_IDX_BOFFSET 24 -#define NAPT_ENTRY3_CNT_IDX_BLEN 3 -#define NAPT_ENTRY3_CNT_IDX_FLAG HSL_RW - -#define PROT_TYP -#define NAPT_ENTRY3_PROT_TYP_BOFFSET 22 -#define NAPT_ENTRY3_PROT_TYP_BLEN 2 -#define NAPT_ENTRY3_PROT_TYP_FLAG HSL_RW - -#define ACTION -#define NAPT_ENTRY3_ACTION_BOFFSET 20 -#define NAPT_ENTRY3_ACTION_BLEN 2 -#define NAPT_ENTRY3_ACTION_FLAG HSL_RW - -#define SRC_IPADDR1 -#define NAPT_ENTRY3_SRC_IPADDR1_BOFFSET 0 -#define NAPT_ENTRY3_SRC_IPADDR1_BLEN 20 -#define NAPT_ENTRY3_SRC_IPADDR1_FLAG HSL_RW - - -#define NAPT_ENTRY4 -#define NAPT_ENTRY4_OFFSET 0x0e90 -#define NAPT_ENTRY4_E_LENGTH 4 -#define NAPT_ENTRY4_E_OFFSET 0x0 -#define NAPT_ENTRY4_NR_E 1 - -#define LOAD_BALANCE -#define NAPT_ENTRY4_LOAD_BALANCE_BOFFSET 19 -#define NAPT_ENTRY4_LOAD_BALANCE_BLEN 3 -#define NAPT_ENTRY4_LOAD_BALANCE_FLAG HSL_RW - -#define FLOW_COOKIE -#define NAPT_ENTRY4_FLOW_COOKIE_BOFFSET 8 -#define NAPT_ENTRY4_FLOW_COOKIE_BLEN 11 -#define NAPT_ENTRY4_FLOW_COOKIE_FLAG HSL_RW - -#define VRF_ID -#define NAPT_ENTRY4_VRF_ID_BOFFSET 5 -#define NAPT_ENTRY4_VRF_ID_BLEN 3 -#define NAPT_ENTRY4_VRF_ID_FLAG HSL_RW - -#define AGE_SYNC -#define NAPT_ENTRY4_AGE_SYNC_BOFFSET 4 -#define NAPT_ENTRY4_AGE_SYNC_BLEN 1 -#define NAPT_ENTRY4_AGE_SYNC_FLAG HSL_RO - -#define AGE_FLAG -#define NAPT_ENTRY4_AGE_FLAG_BOFFSET 0 -#define NAPT_ENTRY4_AGE_FLAG_BLEN 4 -#define NAPT_ENTRY4_AGE_FLAG_FLAG HSL_RW - - -#define ROUTER_CTRL -#define ROUTER_CTRL_OFFSET 0x0e00 -#define ROUTER_CTRL_E_LENGTH 4 -#define ROUTER_CTRL_E_OFFSET 0x0 -#define ROUTER_CTRL_NR_E 1 - -#define ARP_LEARN_MODE -#define ROUTER_CTRL_ARP_LEARN_MODE_BOFFSET 19 -#define ROUTER_CTRL_ARP_LEARN_MODE_BLEN 1 -#define ROUTER_CTRL_ARP_LEARN_MODE_FLAG HSL_RW - -#define GLB_LOCKTIME -#define ROUTER_CTRL_GLB_LOCKTIME_BOFFSET 16 -#define ROUTER_CTRL_GLB_LOCKTIME_BLEN 2 -#define ROUTER_CTRL_GLB_LOCKTIME_FLAG HSL_RW - -#define ARP_AGE_TIME -#define ROUTER_CTRL_ARP_AGE_TIME_BOFFSET 8 -#define ROUTER_CTRL_ARP_AGE_TIME_BLEN 8 -#define ROUTER_CTRL_ARP_AGE_TIME_FLAG HSL_RW - -#define WCMP_HAHS_DP -#define ROUTER_CTRL_WCMP_HAHS_DP_BOFFSET 7 -#define ROUTER_CTRL_WCMP_HAHS_DP_BLEN 1 -#define ROUTER_CTRL_WCMP_HAHS_DP_FLAG HSL_RW - -#define WCMP_HAHS_DIP -#define ROUTER_CTRL_WCMP_HAHS_DIP_BOFFSET 6 -#define ROUTER_CTRL_WCMP_HAHS_DIP_BLEN 1 -#define ROUTER_CTRL_WCMP_HAHS_DIP_FLAG HSL_RW - -#define WCMP_HAHS_SP -#define ROUTER_CTRL_WCMP_HAHS_SP_BOFFSET 5 -#define ROUTER_CTRL_WCMP_HAHS_SP_BLEN 1 -#define ROUTER_CTRL_WCMP_HAHS_SP_FLAG HSL_RW - -#define WCMP_HAHS_SIP -#define ROUTER_CTRL_WCMP_HAHS_SIP_BOFFSET 4 -#define ROUTER_CTRL_WCMP_HAHS_SIP_BLEN 1 -#define ROUTER_CTRL_WCMP_HAHS_SIP_FLAG HSL_RW - -#define ARP_AGE_MODE -#define ROUTER_CTRL_ARP_AGE_MODE_BOFFSET 1 -#define ROUTER_CTRL_ARP_AGE_MODE_BLEN 1 -#define ROUTER_CTRL_ARP_AGE_MODE_FLAG HSL_RW - -#define ROUTER_EN -#define ROUTER_CTRL_ROUTER_EN_BOFFSET 0 -#define ROUTER_CTRL_ROUTER_EN_BLEN 1 -#define ROUTER_CTRL_ROUTER_EN_FLAG HSL_RW - - - - -#define ROUTER_PTCTRL0 -#define ROUTER_PTCTRL0_OFFSET 0x0e04 -#define ROUTER_PTCTRL0_E_LENGTH 4 -#define ROUTER_PTCTRL0_E_OFFSET 0x0 -#define ROUTER_PTCTRL0_NR_E 1 - - - - -#define ROUTER_PTCTRL1 -#define ROUTER_PTCTRL1_OFFSET 0x0e08 -#define ROUTER_PTCTRL1_E_LENGTH 4 -#define ROUTER_PTCTRL1_E_OFFSET 0x0 -#define ROUTER_PTCTRL1_NR_E 1 - - - -#define ROUTER_PTCTRL2 -#define ROUTER_PTCTRL2_OFFSET 0x0e0c -#define ROUTER_PTCTRL2_E_LENGTH 4 -#define ROUTER_PTCTRL2_E_OFFSET 0x0 -#define ROUTER_PTCTRL2_NR_E 1 - -#define ARP_PT_UP -#define ROUTER_PTCTRL2_ARP_PT_UP_BOFFSET 16 -#define ROUTER_PTCTRL2_ARP_PT_UP_BLEN 7 -#define ROUTER_PTCTRL2_ARP_PT_UP_FLAG HSL_RW - -#define ARP_LEARN_ACK -#define ROUTER_PTCTRL2_ARP_LEARN_ACK_BOFFSET 8 -#define ROUTER_PTCTRL2_ARP_LEARN_ACK_BLEN 7 -#define ROUTER_PTCTRL2_ARP_LEARN_ACK_FLAG HSL_RW - -#define ARP_LEARN_REQ -#define ROUTER_PTCTRL2_ARP_LEARN_REQ_BOFFSET 0 -#define ROUTER_PTCTRL2_ARP_LEARN_REQ_BLEN 7 -#define ROUTER_PTCTRL2_ARP_LEARN_REQ_FLAG HSL_RW - - - - -#define NAT_CTRL -#define NAT_CTRL_OFFSET 0x0e38 -#define NAT_CTRL_E_LENGTH 4 -#define NAT_CTRL_E_OFFSET 0x0 -#define NAT_CTRL_NR_E 1 - -#define NAT_HASH_MODE -#define NAT_CTRL_NAT_HASH_MODE_BOFFSET 5 -#define NAT_CTRL_NAT_HASH_MODE_BLEN 2 -#define NAT_CTRL_NAT_HASH_MODE_FLAG HSL_RW - -#define NAPT_OVERRIDE -#define NAT_CTRL_NAPT_OVERRIDE_BOFFSET 4 -#define NAT_CTRL_NAPT_OVERRIDE_BLEN 1 -#define NAT_CTRL_NAPT_OVERRIDE_FLAG HSL_RW - -#define NAPT_MODE -#define NAT_CTRL_NAPT_MODE_BOFFSET 2 -#define NAT_CTRL_NAPT_MODE_BLEN 2 -#define NAT_CTRL_NAPT_MODE_FLAG HSL_RW - -#define NAT_EN -#define NAT_CTRL_NAT_EN_BOFFSET 1 -#define NAT_CTRL_NAT_EN_BLEN 1 -#define NAT_CTRL_NAT_EN_FLAG HSL_RW - -#define NAPT_EN -#define NAT_CTRL_NAPT_EN_BOFFSET 0 -#define NAT_CTRL_NAPT_EN_BLEN 1 -#define NAT_CTRL_NAPT_EN_FLAG HSL_RW - - - -#define FlOW_CMD_CTL -#define FlOW_CMD_CTL_OFFSET 0x0ea0 -#define FlOW_CMD_CTL_E_LENGTH 4 -#define FlOW_CMD_CTL_E_OFFSET 0x4 -#define FlOW_CMD_CTL_NR_E 8 - -#define LAN_2_LAN_DEFAULT -#define FlOW_CMD_CTL_LAN_2_LAN_DEFAULT_BOFFSET 26 -#define FlOW_CMD_CTL_LAN_2_LAN_DEFAULT_BLEN 2 -#define FlOW_CMD_CTL_LAN_2_LAN_DEFAULT_FLAG HSL_RW - -#define WAN_2_LAN_DEFAULT -#define FlOW_CMD_CTL_WAN_2_LAN_DEFAULT_BOFFSET 24 -#define FlOW_CMD_CTL_WAN_2_LAN_DEFAULT_BLEN 2 -#define FlOW_CMD_CTL_WAN_2_LAN_DEFAULT_FLAG HSL_RW - -#define LAN_2_WAN_DEFAULT -#define FlOW_CMD_CTL_LAN_2_WAN_DEFAULT_BOFFSET 22 -#define FlOW_CMD_CTL_LAN_2_WAN_DEFAULT_BLEN 2 -#define FlOW_CMD_CTL_LAN_2_WAN_DEFAULT_FLAG HSL_RW - -#define WAN_2_WAN_DEFAULT -#define FlOW_CMD_CTL_WAN_2_WAN_DEFAULT_BOFFSET 20 -#define FlOW_CMD_CTL_WAN_2_WAN_DEFAULT_BLEN 2 -#define FlOW_CMD_CTL_WAN_2_WAN_DEFAULT_FLAG HSL_RW - - -#define FlOW_RT_CMD_CTL -#define FlOW_RT_CMD_CTL_OFFSET 0x0ec0 -#define FlOW_RT_CMD_CTL_E_LENGTH 4 -#define FlOW_RT_CMD_CTL_E_OFFSET 0x4 -#define FlOW_RT_CMD_CTL_NR_E 8 - -#define LAN_2_LAN_DEFAULT -#define FlOW_RT_CMD_CTL_LAN_2_LAN_DEFAULT_BOFFSET 26 -#define FlOW_RT_CMD_CTL_LAN_2_LAN_DEFAULT_BLEN 2 -#define FlOW_RT_CMD_CTL_LAN_2_LAN_DEFAULT_FLAG HSL_RW - -#define WAN_2_LAN_DEFAULT -#define FlOW_RT_CMD_CTL_WAN_2_LAN_DEFAULT_BOFFSET 24 -#define FlOW_RT_CMD_CTL_WAN_2_LAN_DEFAULT_BLEN 2 -#define FlOW_RT_CMD_CTL_WAN_2_LAN_DEFAULT_FLAG HSL_RW - -#define LAN_2_WAN_DEFAULT -#define FlOW_RT_CMD_CTL_LAN_2_WAN_DEFAULT_BOFFSET 22 -#define FlOW_RT_CMD_CTL_LAN_2_WAN_DEFAULT_BLEN 2 -#define FlOW_RT_CMD_CTL_LAN_2_WAN_DEFAULT_FLAG HSL_RW - -#define WAN_2_WAN_DEFAULT -#define FlOW_RT_CMD_CTL_WAN_2_WAN_DEFAULT_BOFFSET 20 -#define FlOW_RT_CMD_CTL_WAN_2_WAN_DEFAULT_BLEN 2 -#define FlOW_RT_CMD_CTL_WAN_2_WAN_DEFAULT_FLAG HSL_RW - - - -#define PRV_BASEADDR -#define PRV_BASEADDR_OFFSET 0x0e5c -#define PRV_BASEADDR_E_LENGTH 4 -#define PRV_BASEADDR_E_OFFSET 0x0 -#define PRV_BASEADDR_NR_E 1 - -#define IP4_ADDR -#define PRV_BASEADDR_IP4_ADDR_BOFFSET 0 -#define PRV_BASEADDR_IP4_ADDR_BLEN 20 -#define PRV_BASEADDR_IP4_ADDR_FLAG HSL_RW - - - - -#define PRVIP_ADDR -#define PRVIP_ADDR_OFFSET 0x0470 -#define PRVIP_ADDR_E_LENGTH 4 -#define PRVIP_ADDR_E_OFFSET 0x0 -#define PRVIP_ADDR_NR_E 1 - -#define IP4_BASEADDR -#define PRVIP_ADDR_IP4_BASEADDR_BOFFSET 0 -#define PRVIP_ADDR_IP4_BASEADDR_BLEN 32 -#define PRVIP_ADDR_IP4_BASEADDR_FLAG HSL_RW - - -#define PRVIP_MASK -#define PRVIP_MASK_OFFSET 0x0474 -#define PRVIP_MASK_E_LENGTH 4 -#define PRVIP_MASK_E_OFFSET 0x0 -#define PRVIP_MASK_NR_E 1 - -#define IP4_BASEMASK -#define PRVIP_MASK_IP4_BASEMASK_BOFFSET 0 -#define PRVIP_MASK_IP4_BASEMASK_BLEN 32 -#define PRVIP_MASK_IP4_BASEMASK_FLAG HSL_RW - - - - -#define PUB_ADDR0 -#define PUB_ADDR0_OFFSET 0x5aa00 -#define PUB_ADDR0_E_LENGTH 4 -#define PUB_ADDR0_E_OFFSET 0x0 -#define PUB_ADDR0_NR_E 1 - -#define IP4_ADDR -#define PUB_ADDR0_IP4_ADDR_BOFFSET 0 -#define PUB_ADDR0_IP4_ADDR_BLEN 32 -#define PUB_ADDR0_IP4_ADDR_FLAG HSL_RW - - -#define PUB_ADDR1 -#define PUB_ADDR1_OFFSET 0x5aa04 -#define PUB_ADDR1_E_LENGTH 4 -#define PUB_ADDR1_E_OFFSET 0x0 -#define PUB_ADDR1_NR_E 1 - -#define ADDR_VALID -#define PUB_ADDR1_ADDR_VALID_BOFFSET 0 -#define PUB_ADDR1_ADDR_VALID_BLEN 1 -#define PUB_ADDR1_ADDR_VALID_FLAG HSL_RW - - - - -#define INTF_ADDR_ENTRY0 -#define INTF_ADDR_ENTRY0_OFFSET 0x5aa00 -#define INTF_ADDR_ENTRY0_E_LENGTH 4 -#define INTF_ADDR_ENTRY0_E_OFFSET 0x0 -#define INTF_ADDR_ENTRY0_NR_E 8 - -#define MAC_ADDR2 -#define INTF_ADDR_ENTRY0_MAC_ADDR2_BOFFSET 24 -#define INTF_ADDR_ENTRY0_MAC_ADDR2_BLEN 8 -#define INTF_ADDR_ENTRY0_MAC_ADDR2_FLAG HSL_RW - -#define MAC_ADDR3 -#define INTF_ADDR_ENTRY0_MAC_ADDR3_BOFFSET 16 -#define INTF_ADDR_ENTRY0_MAC_ADDR3_BLEN 8 -#define INTF_ADDR_ENTRY0_MAC_ADDR3_FLAG HSL_RW - -#define MAC_ADDR4 -#define INTF_ADDR_ENTRY0_MAC_ADDR4_BOFFSET 8 -#define INTF_ADDR_ENTRY0_MAC_ADDR4_BLEN 8 -#define INTF_ADDR_ENTRY0_MAC_ADDR4_FLAG HSL_RW - -#define MAC_ADDR5 -#define INTF_ADDR_ENTRY0_MAC_ADDR5_BOFFSET 0 -#define INTF_ADDR_ENTRY0_MAC_ADDR5_BLEN 8 -#define INTF_ADDR_ENTRY0_MAC_ADDR5_FLAG HSL_RW - - -#define INTF_ADDR_ENTRY1 -#define INTF_ADDR_ENTRY1_OFFSET 0x5aa04 -#define INTF_ADDR_ENTRY1_E_LENGTH 4 -#define INTF_ADDR_ENTRY1_E_OFFSET 0x0 -#define INTF_ADDR_ENTRY1_NR_E 8 - -#define VID_HIGH0 -#define INTF_ADDR_ENTRY1_VID_HIGH0_BOFFSET 28 -#define INTF_ADDR_ENTRY1_VID_HIGH0_BLEN 4 -#define INTF_ADDR_ENTRY1_VID_HIGH0_FLAG HSL_RW - -#define VID_LOW -#define INTF_ADDR_ENTRY1_VID_LOW_BOFFSET 16 -#define INTF_ADDR_ENTRY1_VID_LOW_BLEN 12 -#define INTF_ADDR_ENTRY1_VID_LOW_FLAG HSL_RW - -#define MAC_ADDR0 -#define INTF_ADDR_ENTRY1_MAC_ADDR0_BOFFSET 8 -#define INTF_ADDR_ENTRY1_MAC_ADDR0_BLEN 8 -#define INTF_ADDR_ENTRY1_MAC_ADDR0_FLAG HSL_RW - -#define MAC_ADDR1 -#define INTF_ADDR_ENTRY1_MAC_ADDR1_BOFFSET 0 -#define INTF_ADDR_ENTRY1_MAC_ADDR1_BLEN 8 -#define INTF_ADDR_ENTRY1_MAC_ADDR1_FLAG HSL_RW - - -#define INTF_ADDR_ENTRY2 -#define INTF_ADDR_ENTRY2_OFFSET 0x5aa08 -#define INTF_ADDR_ENTRY2_E_LENGTH 4 -#define INTF_ADDR_ENTRY2_E_OFFSET 0x0 -#define INTF_ADDR_ENTRY2_NR_E 8 - -#define VRF_ID -#define INTF_ADDR_ENTRY2_VRF_ID_BOFFSET 10 -#define INTF_ADDR_ENTRY2_VRF_ID_BLEN 3 -#define INTF_ADDR_ENTRY2_VRF_ID_FLAG HSL_RW - -#define IP6_ROUTE -#define INTF_ADDR_ENTRY2_IP6_ROUTE_BOFFSET 9 -#define INTF_ADDR_ENTRY2_IP6_ROUTE_BLEN 1 -#define INTF_ADDR_ENTRY2_IP6_ROUTE_FLAG HSL_RW - -#define IP4_ROUTE -#define INTF_ADDR_ENTRY2_IP4_ROUTE_BOFFSET 8 -#define INTF_ADDR_ENTRY2_IP4_ROUTE_BLEN 1 -#define INTF_ADDR_ENTRY2_IP4_ROUTE_FLAG HSL_RW - -#define VID_HIGH1 -#define INTF_ADDR_ENTRY2_VID_HIGH1_BOFFSET 0 -#define INTF_ADDR_ENTRY2_VID_HIGH1_BLEN 8 -#define INTF_ADDR_ENTRY2_VID_HIGH1_FLAG HSL_RW - - -#define IP4_DEFAULT_ROUTE_ENTRY -#define IP4_DEFAULT_ROUTE_ENTRY_OFFSET 0x004c4 -#define IP4_DEFAULT_ROUTE_ENTRY_E_LENGTH 4 -#define IP4_DEFAULT_ROUTE_ENTRY_E_OFFSET 0x0 -#define IP4_DEFAULT_ROUTE_ENTRY_NR_E 8 - -#define VALID -#define IP4_DEFAULT_ROUTE_ENTRY_VALID_BOFFSET 11 -#define IP4_DEFAULT_ROUTE_ENTRY_VALID_BLEN 1 -#define IP4_DEFAULT_ROUTE_ENTRY_VALID_FLAG HSL_RW - -#define VRF -#define IP4_DEFAULT_ROUTE_ENTRY_VRF_BOFFSET 8 -#define IP4_DEFAULT_ROUTE_ENTRY_VRF_BLEN 3 -#define IP4_DEFAULT_ROUTE_ENTRY_VRF_FLAG HSL_RW - -#define ARP_WCMP_TYPE -#define IP4_DEFAULT_ROUTE_ENTRY_ARP_WCMP_TYPE_BOFFSET 7 -#define IP4_DEFAULT_ROUTE_ENTRY_ARP_WCMP_TYPE_BLEN 1 -#define IP4_DEFAULT_ROUTE_ENTRY_ARP_WCMP_TYPE_FLAG HSL_RW - -#define ARP_WCMP_INDEX -#define IP4_DEFAULT_ROUTE_ENTRY_ARP_WCMP_INDEX_BOFFSET 0 -#define IP4_DEFAULT_ROUTE_ENTRY_ARP_WCMP_INDEX_BLEN 7 -#define IP4_DEFAULT_ROUTE_ENTRY_ARP_WCMP_INDEX_FLAG HSL_RW - -#define IP6_DEFAULT_ROUTE_ENTRY -#define IP6_DEFAULT_ROUTE_ENTRY_OFFSET 0x004c4 -#define IP6_DEFAULT_ROUTE_ENTRY_E_LENGTH 4 -#define IP6_DEFAULT_ROUTE_ENTRY_E_OFFSET 0x0 -#define IP6_DEFAULT_ROUTE_ENTRY_NR_E 8 - -#define VALID -#define IP6_DEFAULT_ROUTE_ENTRY_VALID_BOFFSET 11 -#define IP6_DEFAULT_ROUTE_ENTRY_VALID_BLEN 1 -#define IP6_DEFAULT_ROUTE_ENTRY_VALID_FLAG HSL_RW - -#define VRF -#define IP6_DEFAULT_ROUTE_ENTRY_VRF_BOFFSET 8 -#define IP6_DEFAULT_ROUTE_ENTRY_VRF_BLEN 3 -#define IP6_DEFAULT_ROUTE_ENTRY_VRF_FLAG HSL_RW - -#define ARP_WCMP_TYPE -#define IP6_DEFAULT_ROUTE_ENTRY_ARP_WCMP_TYPE_BOFFSET 7 -#define IP6_DEFAULT_ROUTE_ENTRY_ARP_WCMP_TYPE_BLEN 1 -#define IP6_DEFAULT_ROUTE_ENTRY_ARP_WCMP_TYPE_FLAG HSL_RW - -#define ARP_WCMP_INDEX -#define IP6_DEFAULT_ROUTE_ENTRY_ARP_WCMP_INDEX_BOFFSET 0 -#define IP6_DEFAULT_ROUTE_ENTRY_ARP_WCMP_INDEX_BLEN 7 -#define IP6_DEFAULT_ROUTE_ENTRY_ARP_WCMP_INDEX_FLAG HSL_RW - -#define IP4_HOST_ROUTE_ENTRY0 -#define IP4_HOST_ROUTE_ENTRY0_OFFSET 0x5b000 -#define IP4_HOST_ROUTE_ENTRY0_E_LENGTH 4 -#define IP4_HOST_ROUTE_ENTRY0_E_OFFSET 0x0 -#define IP4_HOST_ROUTE_ENTRY0_NR_E 16 - -#define IP4_ADDRL -#define IP4_HOST_ROUTE_ENTRY0_IP4_ADDRL_BOFFSET 5 -#define IP4_HOST_ROUTE_ENTRY0_IP4_ADDRL_BLEN 27 -#define IP4_HOST_ROUTE_ENTRY0_IP4_ADDRL_FLAG HSL_RW - -#define PREFIX_LENGTH -#define IP4_HOST_ROUTE_ENTRY0_PREFIX_LENGTH_BOFFSET 0 -#define IP4_HOST_ROUTE_ENTRY0_PREFIX_LENGTH_BLEN 5 -#define IP4_HOST_ROUTE_ENTRY0_PREFIX_LENGTH_FLAG HSL_RW - -#define IP4_HOST_ROUTE_ENTRY1 -#define IP4_HOST_ROUTE_ENTRY1_OFFSET 0x5b004 -#define IP4_HOST_ROUTE_ENTRY1_E_LENGTH 4 -#define IP4_HOST_ROUTE_ENTRY1_E_OFFSET 0x0 -#define IP4_HOST_ROUTE_ENTRY1_NR_E 16 - -#define VALID -#define IP4_HOST_ROUTE_ENTRY1_VALID_BOFFSET 8 -#define IP4_HOST_ROUTE_ENTRY1_VALID_BLEN 1 -#define IP4_HOST_ROUTE_ENTRY1_VALID_FLAG HSL_RW - -#define VRF -#define IP4_HOST_ROUTE_ENTRY1_VRF_BOFFSET 5 -#define IP4_HOST_ROUTE_ENTRY1_VRF_BLEN 3 -#define IP4_HOST_ROUTE_ENTRY1_VRF_FLAG HSL_RW - -#define IP4_ADDRH -#define IP4_HOST_ROUTE_ENTRY1_IP4_ADDRH_BOFFSET 0 -#define IP4_HOST_ROUTE_ENTRY1_IP4_ADDRH_BLEN 5 -#define IP4_HOST_ROUTE_ENTRY1_IP4_ADDRH_FLAG HSL_RW - -#define IP6_HOST_ROUTE_ENTRY0 -#define IP6_HOST_ROUTE_ENTRY0_OFFSET 0x5b100 -#define IP6_HOST_ROUTE_ENTRY0_E_LENGTH 4 -#define IP6_HOST_ROUTE_ENTRY0_E_OFFSET 0x0 -#define IP6_HOST_ROUTE_ENTRY0_NR_E 16 - -#define PREFIX_LENGTH -#define IP6_HOST_ROUTE_ENTRY0_PREFIX_LENGTH_BOFFSET 0 -#define IP6_HOST_ROUTE_ENTRY0_PREFIX_LENGTH_BLEN 7 -#define IP6_HOST_ROUTE_ENTRY0_PREFIX_LENGTH_FLAG HSL_RW - -#define IP6_ADDR0L -#define IP6_HOST_ROUTE_ENTRY0_IP6_ADDR0L_BOFFSET 7 -#define IP6_HOST_ROUTE_ENTRY0_IP6_ADDR0L_BLEN 25 -#define IP6_HOST_ROUTE_ENTRY0_IP6_ADDR0L_FLAG HSL_RW - -#define IP6_HOST_ROUTE_ENTRY1 -#define IP6_HOST_ROUTE_ENTRY1_OFFSET 0x5b104 -#define IP6_HOST_ROUTE_ENTRY1_E_LENGTH 4 -#define IP6_HOST_ROUTE_ENTRY1_E_OFFSET 0x0 -#define IP6_HOST_ROUTE_ENTRY1_NR_E 16 - -#define IP6_ADDR0H -#define IP6_HOST_ROUTE_ENTRY1_IP6_ADDR0H_BOFFSET 0 -#define IP6_HOST_ROUTE_ENTRY1_IP6_ADDR0H_BLEN 7 -#define IP6_HOST_ROUTE_ENTRY1_IP6_ADDR0H_FLAG HSL_RW - -#define IP6_ADDR1L -#define IP6_HOST_ROUTE_ENTRY1_IP6_ADDR1L_BOFFSET 7 -#define IP6_HOST_ROUTE_ENTRY1_IP6_ADDR1L_BLEN 25 -#define IP6_HOST_ROUTE_ENTRY1_IP6_ADDR1L_FLAG HSL_RW - -#define IP6_HOST_ROUTE_ENTRY2 -#define IP6_HOST_ROUTE_ENTRY2_OFFSET 0x5b108 -#define IP6_HOST_ROUTE_ENTRY2_E_LENGTH 4 -#define IP6_HOST_ROUTE_ENTRY2_E_OFFSET 0x0 -#define IP6_HOST_ROUTE_ENTRY2_NR_E 16 - -#define IP6_ADDR1H -#define IP6_HOST_ROUTE_ENTRY2_IP6_ADDR1H_BOFFSET 0 -#define IP6_HOST_ROUTE_ENTRY2_IP6_ADDR1H_BLEN 7 -#define IP6_HOST_ROUTE_ENTRY2_IP6_ADDR1H_FLAG HSL_RW - -#define IP6_ADDR2L -#define IP6_HOST_ROUTE_ENTRY2_IP6_ADDR2L_BOFFSET 7 -#define IP6_HOST_ROUTE_ENTRY2_IP6_ADDR2L_BLEN 25 -#define IP6_HOST_ROUTE_ENTRY2_IP6_ADDR2L_FLAG HSL_RW - -#define IP6_HOST_ROUTE_ENTRY3 -#define IP6_HOST_ROUTE_ENTRY3_OFFSET 0x5b10c -#define IP6_HOST_ROUTE_ENTRY3_E_LENGTH 4 -#define IP6_HOST_ROUTE_ENTRY3_E_OFFSET 0x0 -#define IP6_HOST_ROUTE_ENTRY3_NR_E 16 - -#define IP6_ADDR2H -#define IP6_HOST_ROUTE_ENTRY3_IP6_ADDR2H_BOFFSET 0 -#define IP6_HOST_ROUTE_ENTRY3_IP6_ADDR2H_BLEN 7 -#define IP6_HOST_ROUTE_ENTRY3_IP6_ADDR2H_FLAG HSL_RW - -#define IP6_ADDR3L -#define IP6_HOST_ROUTE_ENTRY3_IP6_ADDR3L_BOFFSET 7 -#define IP6_HOST_ROUTE_ENTRY3_IP6_ADDR3L_BLEN 25 -#define IP6_HOST_ROUTE_ENTRY3_IP6_ADDR3L_FLAG HSL_RW - -#define IP6_HOST_ROUTE_ENTRY4 -#define IP6_HOST_ROUTE_ENTRY4_OFFSET 0x5b110 -#define IP6_HOST_ROUTE_ENTRY4_E_LENGTH 4 -#define IP6_HOST_ROUTE_ENTRY4_E_OFFSET 0x0 -#define IP6_HOST_ROUTE_ENTRY4_NR_E 16 - -#define IP6_ADDR3H -#define IP6_HOST_ROUTE_ENTRY4_IP6_ADDR3H_BOFFSET 0 -#define IP6_HOST_ROUTE_ENTRY4_IP6_ADDR3H_BLEN 7 -#define IP6_HOST_ROUTE_ENTRY4_IP6_ADDR3H_FLAG HSL_RW - -#define VRF -#define IP6_HOST_ROUTE_ENTRY4_VRF_BOFFSET 7 -#define IP6_HOST_ROUTE_ENTRY4_VRF_BLEN 3 -#define IP6_HOST_ROUTE_ENTRY4_VRF_FLAG HSL_RW - -#define VALID -#define IP6_HOST_ROUTE_ENTRY4_VALID_BOFFSET 10 -#define IP6_HOST_ROUTE_ENTRY4_VALID_BLEN 1 -#define IP6_HOST_ROUTE_ENTRY4_VALID_FLAG HSL_RW - - - /* Port Shaper Register0 */ -#define EG_SHAPER0 -#define EG_SHAPER0_OFFSET 0x0890 -#define EG_SHAPER0_E_LENGTH 4 -#define EG_SHAPER0_E_OFFSET 0x0020 -#define EG_SHAPER0_NR_E 7 - -#define EG_Q1_CIR -#define EG_SHAPER0_EG_Q1_CIR_BOFFSET 16 -#define EG_SHAPER0_EG_Q1_CIR_BLEN 15 -#define EG_SHAPER0_EG_Q1_CIR_FLAG HSL_RW - -#define EG_Q0_CIR -#define EG_SHAPER0_EG_Q0_CIR_BOFFSET 0 -#define EG_SHAPER0_EG_Q0_CIR_BLEN 15 -#define EG_SHAPER0_EG_Q0_CIR_FLAG HSL_RW - - - /* Port Shaper Register1 */ -#define EG_SHAPER1 -#define EG_SHAPER1_OFFSET 0x0894 -#define EG_SHAPER1_E_LENGTH 4 -#define EG_SHAPER1_E_OFFSET 0x0020 -#define EG_SHAPER1_NR_E 7 - -#define EG_Q3_CIR -#define EG_SHAPER1_EG_Q3_CIR_BOFFSET 16 -#define EG_SHAPER1_EG_Q3_CIR_BLEN 15 -#define EG_SHAPER1_EG_Q3_CIR_FLAG HSL_RW - -#define EG_Q2_CIR -#define EG_SHAPER1_EG_Q2_CIR_BOFFSET 0 -#define EG_SHAPER1_EG_Q2_CIR_BLEN 15 -#define EG_SHAPER1_EG_Q2_CIR_FLAG HSL_RW - - - /* Port Shaper Register2 */ -#define EG_SHAPER2 -#define EG_SHAPER2_OFFSET 0x0898 -#define EG_SHAPER2_E_LENGTH 4 -#define EG_SHAPER2_E_OFFSET 0x0020 -#define EG_SHAPER2_NR_E 7 - -#define EG_Q5_CIR -#define EG_SHAPER2_EG_Q5_CIR_BOFFSET 16 -#define EG_SHAPER2_EG_Q5_CIR_BLEN 15 -#define EG_SHAPER2_EG_Q5_CIR_FLAG HSL_RW - -#define EG_Q4_CIR -#define EG_SHAPER2_EG_Q4_CIR_BOFFSET 0 -#define EG_SHAPER2_EG_Q4_CIR_BLEN 15 -#define EG_SHAPER2_EG_Q4_CIR_FLAG HSL_RW - - - /* Port Shaper Register3 */ -#define EG_SHAPER3 -#define EG_SHAPER3_OFFSET 0x089c -#define EG_SHAPER3_E_LENGTH 4 -#define EG_SHAPER3_E_OFFSET 0x0020 -#define EG_SHAPER3_NR_E 7 - -#define EG_Q1_EIR -#define EG_SHAPER3_EG_Q1_EIR_BOFFSET 16 -#define EG_SHAPER3_EG_Q1_EIR_BLEN 15 -#define EG_SHAPER3_EG_Q1_EIR_FLAG HSL_RW - -#define EG_Q0_EIR -#define EG_SHAPER3_EG_Q0_EIR_BOFFSET 0 -#define EG_SHAPER3_EG_Q0_EIR_BLEN 15 -#define EG_SHAPER3_EG_Q0_EIR_FLAG HSL_RW - - - /* Port Shaper Register4 */ -#define EG_SHAPER4 -#define EG_SHAPER4_OFFSET 0x08a0 -#define EG_SHAPER4_E_LENGTH 4 -#define EG_SHAPER4_E_OFFSET 0x0020 -#define EG_SHAPER4_NR_E 7 - -#define EG_Q3_EIR -#define EG_SHAPER4_EG_Q3_EIR_BOFFSET 16 -#define EG_SHAPER4_EG_Q3_EIR_BLEN 15 -#define EG_SHAPER4_EG_Q3_EIR_FLAG HSL_RW - -#define EG_Q2_EIR -#define EG_SHAPER4_EG_Q2_EIR_BOFFSET 0 -#define EG_SHAPER4_EG_Q2_EIR_BLEN 15 -#define EG_SHAPER4_EG_Q2_EIR_FLAG HSL_RW - - - /* Port Shaper Register5 */ -#define EG_SHAPER5 -#define EG_SHAPER5_OFFSET 0x08a4 -#define EG_SHAPER5_E_LENGTH 4 -#define EG_SHAPER5_E_OFFSET 0x0020 -#define EG_SHAPER5_NR_E 7 - -#define EG_Q5_EIR -#define EG_SHAPER5_EG_Q5_EIR_BOFFSET 16 -#define EG_SHAPER5_EG_Q5_EIR_BLEN 15 -#define EG_SHAPER5_EG_Q5_EIR_FLAG HSL_RW - -#define EG_Q4_EIR -#define EG_SHAPER5_EG_Q4_EIR_BOFFSET 0 -#define EG_SHAPER5_EG_Q4_EIR_BLEN 15 -#define EG_SHAPER5_EG_Q4_EIR_FLAG HSL_RW - - - /* Port Shaper Register6 */ -#define EG_SHAPER6 -#define EG_SHAPER6_OFFSET 0x08a8 -#define EG_SHAPER6_E_LENGTH 4 -#define EG_SHAPER6_E_OFFSET 0x0020 -#define EG_SHAPER6_NR_E 7 - -#define EG_Q3_CBS -#define EG_SHAPER6_EG_Q3_CBS_BOFFSET 28 -#define EG_SHAPER6_EG_Q3_CBS_BLEN 3 -#define EG_SHAPER6_EG_Q3_CBS_FLAG HSL_RW - -#define EG_Q3_EBS -#define EG_SHAPER6_EG_Q3_EBS_BOFFSET 24 -#define EG_SHAPER6_EG_Q3_EBS_BLEN 3 -#define EG_SHAPER6_EG_Q3_EBS_FLAG HSL_RW - -#define EG_Q2_CBS -#define EG_SHAPER6_EG_Q2_CBS_BOFFSET 20 -#define EG_SHAPER6_EG_Q2_CBS_BLEN 3 -#define EG_SHAPER6_EG_Q2_CBS_FLAG HSL_RW - -#define EG_Q2_EBS -#define EG_SHAPER6_EG_Q2_EBS_BOFFSET 16 -#define EG_SHAPER6_EG_Q2_EBS_BLEN 3 -#define EG_SHAPER6_EG_Q2_EBS_FLAG HSL_RW - -#define EG_Q1_CBS -#define EG_SHAPER6_EG_Q1_CBS_BOFFSET 12 -#define EG_SHAPER6_EG_Q1_CBS_BLEN 3 -#define EG_SHAPER6_EG_Q1_CBS_FLAG HSL_RW - -#define EG_Q1_EBS -#define EG_SHAPER6_EG_Q1_EBS_BOFFSET 8 -#define EG_SHAPER6_EG_Q1_EBS_BLEN 3 -#define EG_SHAPER6_EG_Q1_EBS_FLAG HSL_RW - -#define EG_Q0_CBS -#define EG_SHAPER6_EG_Q0_CBS_BOFFSET 4 -#define EG_SHAPER6_EG_Q0_CBS_BLEN 3 -#define EG_SHAPER6_EG_Q0_CBS_FLAG HSL_RW - -#define EG_Q0_EBS -#define EG_SHAPER6_EG_Q0_EBS_BOFFSET 0 -#define EG_SHAPER6_EG_Q0_EBS_BLEN 3 -#define EG_SHAPER6_EG_Q0_EBS_FLAG HSL_RW - - - /* Port Shaper Register7 */ -#define EG_SHAPER7 -#define EG_SHAPER7_OFFSET 0x08ac -#define EG_SHAPER7_E_LENGTH 4 -#define EG_SHAPER7_E_OFFSET 0x0020 -#define EG_SHAPER7_NR_E 7 - -#define EG_Q5_CBS -#define EG_SHAPER7_EG_Q5_CBS_BOFFSET 28 -#define EG_SHAPER7_EG_Q5_CBS_BLEN 3 -#define EG_SHAPER7_EG_Q5_CBS_FLAG HSL_RW - -#define EG_Q5_EBS -#define EG_SHAPER7_EG_Q5_EBS_BOFFSET 24 -#define EG_SHAPER7_EG_Q5_EBS_BLEN 3 -#define EG_SHAPER7_EG_Q5_EBS_FLAG HSL_RW - -#define EG_Q4_CBS -#define EG_SHAPER7_EG_Q4_CBS_BOFFSET 20 -#define EG_SHAPER7_EG_Q4_CBS_BLEN 3 -#define EG_SHAPER7_EG_Q4_CBS_FLAG HSL_RW - -#define EG_Q4_EBS -#define EG_SHAPER7_EG_Q4_EBS_BOFFSET 16 -#define EG_SHAPER7_EG_Q4_EBS_BLEN 3 -#define EG_SHAPER7_EG_Q4_EBS_FLAG HSL_RW - -#define EG_Q5_UNIT -#define EG_SHAPER7_EG_Q5_UNIT_BOFFSET 13 -#define EG_SHAPER7_EG_Q5_UNIT_BLEN 1 -#define EG_SHAPER7_EG_Q5_UNIT_FLAG HSL_RW - -#define EG_Q4_UNIT -#define EG_SHAPER7_EG_Q4_UNIT_BOFFSET 12 -#define EG_SHAPER7_EG_Q4_UNIT_BLEN 1 -#define EG_SHAPER7_EG_Q4_UNIT_FLAG HSL_RW - -#define EG_Q3_UNIT -#define EG_SHAPER7_EG_Q3_UNIT_BOFFSET 11 -#define EG_SHAPER7_EG_Q3_UNIT_BLEN 1 -#define EG_SHAPER7_EG_Q3_UNIT_FLAG HSL_RW - -#define EG_Q2_UNIT -#define EG_SHAPER7_EG_Q2_UNIT_BOFFSET 10 -#define EG_SHAPER7_EG_Q2_UNIT_BLEN 1 -#define EG_SHAPER7_EG_Q2_UNIT_FLAG HSL_RW - -#define EG_Q1_UNIT -#define EG_SHAPER7_EG_Q1_UNIT_BOFFSET 9 -#define EG_SHAPER7_EG_Q1_UNIT_BLEN 1 -#define EG_SHAPER7_EG_Q1_UNIT_FLAG HSL_RW - -#define EG_Q0_UNIT -#define EG_SHAPER7_EG_Q0_UNIT_BOFFSET 8 -#define EG_SHAPER7_EG_Q0_UNIT_BLEN 1 -#define EG_SHAPER7_EG_Q0_UNIT_FLAG HSL_RW - -#define EG_PT -#define EG_SHAPER7_EG_PT_BOFFSET 3 -#define EG_SHAPER7_EG_PT_BLEN 1 -#define EG_SHAPER7_EG_PT_FLAG HSL_RW - -#define EG_TS -#define EG_SHAPER7_EG_TS_BOFFSET 0 -#define EG_SHAPER7_EG_TS_BLEN 3 -#define EG_SHAPER7_EG_TS_FLAG HSL_RW - - - - /* ACL Policer Register0 */ -#define ACL_POLICER0 -#define ACL_POLICER0_OFFSET 0x0a00 -#define ACL_POLICER0_E_LENGTH 4 -#define ACL_POLICER0_E_OFFSET 0x0008 -#define ACL_POLICER0_NR_E 32 - -#define ACL_CBS -#define ACL_POLICER0_ACL_CBS_BOFFSET 15 -#define ACL_POLICER0_ACL_CBS_BLEN 3 -#define ACL_POLICER0_ACL_CBS_FLAG HSL_RW - -#define ACL_CIR -#define ACL_POLICER0_ACL_CIR_BOFFSET 0 -#define ACL_POLICER0_ACL_CIR_BLEN 15 -#define ACL_POLICER0_ACL_CIR_FLAG HSL_RW - - - /* ACL Policer Register1 */ -#define ACL_POLICER1 -#define ACL_POLICER1_OFFSET 0x0a04 -#define ACL_POLICER1_E_LENGTH 4 -#define ACL_POLICER1_E_OFFSET 0x0008 -#define ACL_POLICER1_NR_E 32 - -#define ACL_BORROW -#define ACL_POLICER1_ACL_BORROW_BOFFSET 23 -#define ACL_POLICER1_ACL_BORROW_BLEN 1 -#define ACL_POLICER1_ACL_BORROW_FLAG HSL_RW - -#define ACL_UNIT -#define ACL_POLICER1_ACL_UNIT_BOFFSET 22 -#define ACL_POLICER1_ACL_UNIT_BLEN 1 -#define ACL_POLICER1_ACL_UNIT_FLAG HSL_RW - -#define ACL_CF -#define ACL_POLICER1_ACL_CF_BOFFSET 21 -#define ACL_POLICER1_ACL_CF_BLEN 1 -#define ACL_POLICER1_ACL_CF_FLAG HSL_RW - -#define ACL_CM -#define ACL_POLICER1_ACL_CM_BOFFSET 20 -#define ACL_POLICER1_ACL_CM_BLEN 1 -#define ACL_POLICER1_ACL_CM_FLAG HSL_RW - -#define ACL_TS -#define ACL_POLICER1_ACL_TS_BOFFSET 18 -#define ACL_POLICER1_ACL_TS_BLEN 2 -#define ACL_POLICER1_ACL_TS_FLAG HSL_RW - -#define ACL_EBS -#define ACL_POLICER1_ACL_EBS_BOFFSET 15 -#define ACL_POLICER1_ACL_EBS_BLEN 3 -#define ACL_POLICER1_ACL_EBS_FLAG HSL_RW - -#define ACL_EIR -#define ACL_POLICER1_ACL_EIR_BOFFSET 0 -#define ACL_POLICER1_ACL_EIR_BLEN 15 -#define ACL_POLICER1_ACL_EIR_FLAG HSL_RW - - - /* Flow Congestion Drop CTRL0 */ -#define FLOW_CONGE_DROP_CTRL0 -#define FLOW_CONGE_DROP_CTRL0_OFFSET 0x0b74 -#define FLOW_CONGE_DROP_CTRL0_E_LENGTH 4 -#define FLOW_CONGE_DROP_CTRL0_E_OFFSET 4 -#define FLOW_CONGE_DROP_CTRL0_NR_E 1 - -#define EN5 -#define FLOW_CONGE_DROP_CTRL0_EN5_BOFFSET 22 -#define FLOW_CONGE_DROP_CTRL0_EN5_BLEN 6 -#define FLOW_CONGE_DROP_CTRL0_EN5_FLAG HSL_RW - -#define EN4 -#define FLOW_CONGE_DROP_CTRL0_EN4_BOFFSET 18 -#define FLOW_CONGE_DROP_CTRL0_EN4_BLEN 4 -#define FLOW_CONGE_DROP_CTRL0_EN4_FLAG HSL_RW - -#define EN3 -#define FLOW_CONGE_DROP_CTRL0_EN3_BOFFSET 14 -#define FLOW_CONGE_DROP_CTRL0_EN3_BLEN 4 -#define FLOW_CONGE_DROP_CTRL0_EN3_FLAG HSL_RW - -#define EN2 -#define FLOW_CONGE_DROP_CTRL0_EN2_BOFFSET 10 -#define FLOW_CONGE_DROP_CTRL0_EN2_BLEN 4 -#define FLOW_CONGE_DROP_CTRL0_EN2_FLAG HSL_RW - -#define EN1 -#define FLOW_CONGE_DROP_CTRL0_EN1_BOFFSET 6 -#define FLOW_CONGE_DROP_CTRL0_EN1_BLEN 4 -#define FLOW_CONGE_DROP_CTRL0_EN1_FLAG HSL_RW - -#define EN0 -#define FLOW_CONGE_DROP_CTRL0_EN0_BOFFSET 0 -#define FLOW_CONGE_DROP_CTRL0_EN0_BLEN 6 -#define FLOW_CONGE_DROP_CTRL0_EN0_FLAG HSL_RW - - /* Ring Flow Control Threshold Register*/ -#define RING_FLOW_CTRL_THRES -#define RING_FLOW_CTRL_THRES_OFFSET 0x0b80 -#define RING_FLOW_CTRL_THRES_E_LENGTH 4 -#define RING_FLOW_CTRL_THRES_E_OFFSET 4 -#define RING_FLOW_CTRL_THRES_NR_E 8 - -#define XON -#define RING_FLOW_CTRL_THRES_XON_BOFFSET 16 -#define RING_FLOW_CTRL_THRES_XON_BLEN 8 -#define RING_FLOW_CTRL_THRES_XON_FLAG HSL_RW - -#define XOFF -#define RING_FLOW_CTRL_THRES_XOFF_BOFFSET 0 -#define RING_FLOW_CTRL_THRES_XOFF_BLEN 8 -#define RING_FLOW_CTRL_THRES_XOFF_FLAG HSL_RW - - - - - /* ACL Counter Register0 */ -#define ACL_COUNTER0 -#define ACL_COUNTER0_OFFSET 0x1c000 -#define ACL_COUNTER0_E_LENGTH 4 -#define ACL_COUNTER0_E_OFFSET 0x0008 -#define ACL_COUNTER0_NR_E 32 - - /* ACL Counter Register1 */ -#define ACL_COUNTER1 -#define ACL_COUNTER1_OFFSET 0x1c004 -#define ACL_COUNTER1_E_LENGTH 4 -#define ACL_COUNTER1_E_OFFSET 0x0008 -#define ACL_COUNTER1_NR_E 32 - - - - - /* INGRESS Policer Register0 */ -#define INGRESS_POLICER0 -#define INGRESS_POLICER0_OFFSET 0x0b00 -#define INGRESS_POLICER0_E_LENGTH 4 -#define INGRESS_POLICER0_E_OFFSET 0x0010 -#define INGRESS_POLICER0_NR_E 7 - -#define ADD_RATE_BYTE -#define INGRESS_POLICER0_ADD_RATE_BYTE_BOFFSET 24 -#define INGRESS_POLICER0_ADD_RATE_BYTE_BLEN 8 -#define INGRESS_POLICER0_ADD_RATE_BYTE_FLAG HSL_RW - -#define C_ING_TS -#define INGRESS_POLICER0_C_ING_TS_BOFFSET 22 -#define INGRESS_POLICER0_C_ING_TS_BLEN 2 -#define INGRESS_POLICER0_C_ING_TS_FLAG HSL_RW - -#define RATE_MODE -#define INGRESS_POLICER0_RATE_MODE_BOFFSET 20 -#define INGRESS_POLICER0_RATE_MODE_BLEN 1 -#define INGRESS_POLICER0_RATE_MODE_FLAG HSL_RW - -#define INGRESS_CBS -#define INGRESS_POLICER0_INGRESS_CBS_BOFFSET 15 -#define INGRESS_POLICER0_INGRESS_CBS_BLEN 3 -#define INGRESS_POLICER0_INGRESS_CBS_FLAG HSL_RW - -#define INGRESS_CIR -#define INGRESS_POLICER0_INGRESS_CIR_BOFFSET 0 -#define INGRESS_POLICER0_INGRESS_CIR_BLEN 15 -#define INGRESS_POLICER0_INGRESS_CIR_FLAG HSL_RW - - - /* INGRESS Policer Register1 */ -#define INGRESS_POLICER1 -#define INGRESS_POLICER1_OFFSET 0x0b04 -#define INGRESS_POLICER1_E_LENGTH 4 -#define INGRESS_POLICER1_E_OFFSET 0x0010 -#define INGRESS_POLICER1_NR_E 7 - -#define INGRESS_BORROW -#define INGRESS_POLICER1_INGRESS_BORROW_BOFFSET 23 -#define INGRESS_POLICER1_INGRESS_BORROW_BLEN 1 -#define INGRESS_POLICER1_INGRESS_BORROW_FLAG HSL_RW - -#define INGRESS_UNIT -#define INGRESS_POLICER1_INGRESS_UNIT_BOFFSET 22 -#define INGRESS_POLICER1_INGRESS_UNIT_BLEN 1 -#define INGRESS_POLICER1_INGRESS_UNIT_FLAG HSL_RW - -#define INGRESS_CF -#define INGRESS_POLICER1_INGRESS_CF_BOFFSET 21 -#define INGRESS_POLICER1_INGRESS_CF_BLEN 1 -#define INGRESS_POLICER1_INGRESS_CF_FLAG HSL_RW - -#define INGRESS_CM -#define INGRESS_POLICER1_INGRESS_CM_BOFFSET 20 -#define INGRESS_POLICER1_INGRESS_CM_BLEN 1 -#define INGRESS_POLICER1_INGRESS_CM_FLAG HSL_RW - -#define E_ING_TS -#define INGRESS_POLICER1_E_ING_TS_BOFFSET 18 -#define INGRESS_POLICER1_E_ING_TS_BLEN 2 -#define INGRESS_POLICER1_E_ING_TS_FLAG HSL_RW - -#define INGRESS_EBS -#define INGRESS_POLICER1_INGRESS_EBS_BOFFSET 15 -#define INGRESS_POLICER1_INGRESS_EBS_BLEN 3 -#define INGRESS_POLICER1_INGRESS_EBS_FLAG HSL_RW - -#define INGRESS_EIR -#define INGRESS_POLICER1_INGRESS_EIR_BOFFSET 0 -#define INGRESS_POLICER1_INGRESS_EIR_BLEN 15 -#define INGRESS_POLICER1_INGRESS_EIR_FLAG HSL_RW - - - /* INGRESS Policer Register2 */ -#define INGRESS_POLICER2 -#define INGRESS_POLICER2_OFFSET 0x0b08 -#define INGRESS_POLICER2_E_LENGTH 4 -#define INGRESS_POLICER2_E_OFFSET 0x0010 -#define INGRESS_POLICER2_NR_E 7 - -#define C_MUL -#define INGRESS_POLICER2_C_MUL_BOFFSET 15 -#define INGRESS_POLICER2_C_MUL_BLEN 1 -#define INGRESS_POLICER2_C_UNK_MUL_FLAG HSL_RW - -#define C_UNI -#define INGRESS_POLICER2_C_UNI_BOFFSET 14 -#define INGRESS_POLICER2_C_UNI_BLEN 1 -#define INGRESS_POLICER2_C_UNI_FLAG HSL_RW - -#define C_UNK_MUL -#define INGRESS_POLICER2_C_UNK_MUL_BOFFSET 13 -#define INGRESS_POLICER2_C_UNK_MUL_BLEN 1 -#define INGRESS_POLICER2_C_UNK_MUL_FLAG HSL_RW - -#define C_UNK_UNI -#define INGRESS_POLICER2_C_UNK_UNI_BOFFSET 12 -#define INGRESS_POLICER2_C_UNK_UNI_BLEN 1 -#define INGRESS_POLICER2_C_UNK_UNI_FLAG HSL_RW - -#define C_BROAD -#define INGRESS_POLICER2_C_BROAD_BOFFSET 11 -#define INGRESS_POLICER2_C_BROAD_BLEN 1 -#define INGRESS_POLICER2_C_BROAD_FLAG HSL_RW - -#define C_MANAGE -#define INGRESS_POLICER2_C_MANAGC_BOFFSET 10 -#define INGRESS_POLICER2_C_MANAGC_BLEN 1 -#define INGRESS_POLICER2_C_MANAGC_FLAG HSL_RW - -#define C_TCP -#define INGRESS_POLICER2_C_TCP_BOFFSET 9 -#define INGRESS_POLICER2_C_TCP_BLEN 1 -#define INGRESS_POLICER2_C_TCP_FLAG HSL_RW - -#define C_MIRR -#define INGRESS_POLICER2_C_MIRR_BOFFSET 8 -#define INGRESS_POLICER2_C_MIRR_BLEN 1 -#define INGRESS_POLICER2_C_MIRR_FLAG HSL_RW - -#define E_MUL -#define INGRESS_POLICER2_E_MUL_BOFFSET 7 -#define INGRESS_POLICER2_E_MUL_BLEN 1 -#define INGRESS_POLICER2_E_UNK_MUL_FLAG HSL_RW - -#define E_UNI -#define INGRESS_POLICER2_E_UNI_BOFFSET 6 -#define INGRESS_POLICER2_E_UNI_BLEN 1 -#define INGRESS_POLICER2_E_UNI_FLAG HSL_RW - -#define E_UNK_MUL -#define INGRESS_POLICER2_E_UNK_MUL_BOFFSET 5 -#define INGRESS_POLICER2_E_UNK_MUL_BLEN 1 -#define INGRESS_POLICER2_E_UNK_MUL_FLAG HSL_RW - -#define E_UNK_UNI -#define INGRESS_POLICER2_E_UNK_UNI_BOFFSET 4 -#define INGRESS_POLICER2_E_UNK_UNI_BLEN 1 -#define INGRESS_POLICER2_E_UNK_UNI_FLAG HSL_RW - -#define E_BROAD -#define INGRESS_POLICER2_E_BROAD_BOFFSET 3 -#define INGRESS_POLICER2_E_BROAD_BLEN 1 -#define INGRESS_POLICER2_E_BROAD_FLAG HSL_RW - -#define E_MANAGE -#define INGRESS_POLICER2_E_MANAGE_BOFFSET 2 -#define INGRESS_POLICER2_E_MANAGE_BLEN 1 -#define INGRESS_POLICER2_E_MANAGE_FLAG HSL_RW - -#define E_TCP -#define INGRESS_POLICER2_E_TCP_BOFFSET 1 -#define INGRESS_POLICER2_E_TCP_BLEN 1 -#define INGRESS_POLICER2_E_TCP_FLAG HSL_RW - -#define E_MIRR -#define INGRESS_POLICER2_E_MIRR_BOFFSET 0 -#define INGRESS_POLICER2_E_MIRR_BLEN 1 -#define INGRESS_POLICER2_E_MIRR_FLAG HSL_RW - - - - - /* Port Rate Limit2 Register */ -#define WRR_CTRL -#define WRR_CTRL_OFFSET 0x0830 -#define WRR_CTRL_E_LENGTH 4 -#define WRR_CTRL_E_OFFSET 0x0004 -#define WRR_CTRL_NR_E 7 - -#define SCH_MODE -#define WRR_CTRL_SCH_MODE_BOFFSET 30 -#define WRR_CTRL_SCH_MODE_BLEN 2 -#define WRR_CTRL_SCH_MODE_FLAG HSL_RW - -#define Q5_W -#define WRR_CTRL_Q5_W_BOFFSET 25 -#define WRR_CTRL_Q5_W_BLEN 5 -#define WRR_CTRL_Q5_W_FLAG HSL_RW - -#define Q4_W -#define WRR_CTRL_Q4_W_BOFFSET 20 -#define WRR_CTRL_Q4_W_BLEN 5 -#define WRR_CTRL_Q4_W_FLAG HSL_RW - -#define Q3_W -#define WRR_CTRL_Q3_W_BOFFSET 15 -#define WRR_CTRL_Q3_W_BLEN 5 -#define WRR_CTRL_Q3_W_FLAG HSL_RW - -#define Q2_W -#define WRR_CTRL_Q2_W_BOFFSET 10 -#define WRR_CTRL_Q2_W_BLEN 5 -#define WRR_CTRL_Q2_W_FLAG HSL_RW - -#define Q1_W -#define WRR_CTRL_Q1_W_BOFFSET 5 -#define WRR_CTRL_Q1_W_BLEN 5 -#define WRR_CTRL_Q1_W_FLAG HSL_RW - -#define Q0_W -#define WRR_CTRL_Q0_W_BOFFSET 0 -#define WRR_CTRL_Q0_W_BLEN 5 -#define WRR_CTRL_Q0_W_FLAG HSL_RW - -/* Global Interrupt Register0 */ -#define GLOBAL_INT0 -#define GLOBAL_INT0_OFFSET 0x0020 -#define GLOBAL_INT0_E_LENGTH 4 -#define GLOBAL_INT0_E_OFFSET 0 -#define GLOBAL_INT0_NR_E 1 - -/* Global Interrupt Register1 */ -#define GLOBAL_INT1 -#define GLOBAL_INT1_OFFSET 0x0024 -#define GLOBAL_INT1_E_LENGTH 4 -#define GLOBAL_INT1_E_OFFSET 0 -#define GLOBAL_INT1_NR_E 1 - -/* Global Interrupt Mask Register0 */ -#define GLOBAL_INT0_MASK -#define GLOBAL_INT0_MASK_OFFSET 0x0028 -#define GLOBAL_INT0_MASK_E_LENGTH 4 -#define GLOBAL_INT0_MASK_E_OFFSET 0 -#define GLOBAL_INT0_MASK_NR_E 1 - -/* Global Interrupt Mask Register1 */ -#define GLOBAL_INT1_MASK -#define GLOBAL_INT1_MASK_OFFSET 0x002c -#define GLOBAL_INT1_MASK_E_LENGTH 4 -#define GLOBAL_INT1_MASK_E_OFFSET 0 -#define GLOBAL_INT1_MASK_NR_E 1 - - - - -#ifdef __cplusplus -} -#endif /* __cplusplus */ -#endif /* _DESS_REG_H_ */ - diff --git a/feeds/ipq807x/qca-ssdk/src/include/hsl/dess/dess_reg_access.h b/feeds/ipq807x/qca-ssdk/src/include/hsl/dess/dess_reg_access.h deleted file mode 100755 index 5eb04369a..000000000 --- a/feeds/ipq807x/qca-ssdk/src/include/hsl/dess/dess_reg_access.h +++ /dev/null @@ -1,78 +0,0 @@ -/* - * Copyright (c) 2014,2018, The Linux Foundation. All rights reserved. - * Permission to use, copy, modify, and/or distribute this software for - * any purpose with or without fee is hereby granted, provided that the - * above copyright notice and this permission notice appear in all copies. - * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES - * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR - * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES - * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN - * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT - * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. - */ - - - -#ifndef _DESS_REG_ACCESS_H_ -#define _DESS_REG_ACCESS_H_ - -#ifdef __cplusplus -extern "C" { -#endif /* __cplusplus */ - -#include "sw.h" - - sw_error_t - dess_phy_get(a_uint32_t dev_id, a_uint32_t phy_addr, - a_uint32_t reg, a_uint16_t * value); - - sw_error_t - dess_phy_set(a_uint32_t dev_id, a_uint32_t phy_addr, - a_uint32_t reg, a_uint16_t value); - - sw_error_t - dess_reg_get(a_uint32_t dev_id, a_uint32_t reg_addr, a_uint8_t value[], - a_uint32_t value_len); - - sw_error_t - dess_reg_set(a_uint32_t dev_id, a_uint32_t reg_addr, a_uint8_t value[], - a_uint32_t value_len); - - sw_error_t - dess_reg_field_get(a_uint32_t dev_id, a_uint32_t reg_addr, - a_uint32_t bit_offset, a_uint32_t field_len, - a_uint8_t value[], a_uint32_t value_len); - - sw_error_t - dess_reg_field_set(a_uint32_t dev_id, a_uint32_t reg_addr, - a_uint32_t bit_offset, a_uint32_t field_len, - const a_uint8_t value[], a_uint32_t value_len); - - sw_error_t - dess_regsiter_dump(a_uint32_t dev_id,a_uint32_t register_idx, fal_reg_dump_t * reg_dump); - - sw_error_t - dess_debug_regsiter_dump(a_uint32_t dev_id, fal_debug_reg_dump_t * dbg_reg_dump); - - - sw_error_t - dess_reg_access_init(a_uint32_t dev_id, hsl_access_mode mode); - - sw_error_t - dess_access_mode_set(a_uint32_t dev_id, hsl_access_mode mode); - - sw_error_t - dess_phy_dump(a_uint32_t dev_id, a_uint32_t phy_addr, - a_uint32_t idx, fal_phy_dump_t * phy_dump); - - sw_error_t - dess_debug_psgmii_self_test(a_uint32_t dev_id, a_bool_t enable, - a_uint32_t times, a_uint32_t * result); - -#ifdef __cplusplus -} -#endif /* __cplusplus */ - -#endif /* _DESS_REG_ACCESS_H_ */ - diff --git a/feeds/ipq807x/qca-ssdk/src/include/hsl/dess/dess_sec.h b/feeds/ipq807x/qca-ssdk/src/include/hsl/dess/dess_sec.h deleted file mode 100755 index 1ef340a61..000000000 --- a/feeds/ipq807x/qca-ssdk/src/include/hsl/dess/dess_sec.h +++ /dev/null @@ -1,53 +0,0 @@ -/* - * Copyright (c) 2014, The Linux Foundation. All rights reserved. - * Permission to use, copy, modify, and/or distribute this software for - * any purpose with or without fee is hereby granted, provided that the - * above copyright notice and this permission notice appear in all copies. - * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES - * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR - * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES - * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN - * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT - * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. - */ - - -#ifndef _DESS_SEC_H_ -#define _DESS_SEC_H_ - -#ifdef __cplusplus -extern "C" { -#endif /* __cplusplus */ - -#include "fal/fal_sec.h" - - sw_error_t dess_sec_init(a_uint32_t dev_id); - -#ifdef IN_SEC -#define DESS_SEC_INIT(rv, dev_id) \ - { \ - rv = dess_sec_init(dev_id); \ - SW_RTN_ON_ERROR(rv); \ - } -#else -#define DESS_SEC_INIT(rv, dev_id) -#endif - -#ifdef HSL_STANDALONG - - HSL_LOCAL sw_error_t - dess_sec_norm_item_set(a_uint32_t dev_id, fal_norm_item_t item, - void *value); - - HSL_LOCAL sw_error_t - dess_sec_norm_item_get(a_uint32_t dev_id, fal_norm_item_t item, - void *value); - -#endif - -#ifdef __cplusplus -} -#endif /* __cplusplus */ -#endif /* _DESS_SEC_H_ */ - diff --git a/feeds/ipq807x/qca-ssdk/src/include/hsl/dess/dess_stp.h b/feeds/ipq807x/qca-ssdk/src/include/hsl/dess/dess_stp.h deleted file mode 100755 index c1450cd85..000000000 --- a/feeds/ipq807x/qca-ssdk/src/include/hsl/dess/dess_stp.h +++ /dev/null @@ -1,55 +0,0 @@ -/* - * Copyright (c) 2014, The Linux Foundation. All rights reserved. - * Permission to use, copy, modify, and/or distribute this software for - * any purpose with or without fee is hereby granted, provided that the - * above copyright notice and this permission notice appear in all copies. - * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES - * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR - * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES - * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN - * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT - * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. - */ - - -#ifndef _DESS_STP_H_ -#define _DESS_STP_H_ - -#ifdef __cplusplus -extern "C" { -#endif /* __cplusplus */ - -#include "fal/fal_stp.h" - - sw_error_t dess_stp_init(a_uint32_t dev_id); - -#ifdef IN_STP -#define DESS_STP_INIT(rv, dev_id) \ - { \ - rv = dess_stp_init(dev_id); \ - SW_RTN_ON_ERROR(rv); \ - } -#else -#define DESS_STP_INIT(rv, dev_id) -#endif - -#ifdef HSL_STANDALONG - - - HSL_LOCAL sw_error_t - dess_stp_port_state_set(a_uint32_t dev_id, a_uint32_t st_id, - fal_port_t port_id, fal_stp_state_t state); - - - HSL_LOCAL sw_error_t - dess_stp_port_state_get(a_uint32_t dev_id, a_uint32_t st_id, - fal_port_t port_id, fal_stp_state_t * state); - -#endif - -#ifdef __cplusplus -} -#endif /* __cplusplus */ -#endif /* _DESS_STP_H_ */ - diff --git a/feeds/ipq807x/qca-ssdk/src/include/hsl/dess/dess_trunk.h b/feeds/ipq807x/qca-ssdk/src/include/hsl/dess/dess_trunk.h deleted file mode 100755 index 60e751a8d..000000000 --- a/feeds/ipq807x/qca-ssdk/src/include/hsl/dess/dess_trunk.h +++ /dev/null @@ -1,59 +0,0 @@ -/* - * Copyright (c) 2014, The Linux Foundation. All rights reserved. - * Permission to use, copy, modify, and/or distribute this software for - * any purpose with or without fee is hereby granted, provided that the - * above copyright notice and this permission notice appear in all copies. - * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES - * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR - * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES - * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN - * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT - * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. - */ - - -#ifndef _DESS_TRUNK_H_ -#define _DESS_TRUNK_H_ - -#ifdef __cplusplus -extern "C" { -#endif /* __cplusplus */ - -#include "fal/fal_trunk.h" - - sw_error_t dess_trunk_init(a_uint32_t dev_id); - -#ifdef IN_TRUNK -#define DESS_TRUNK_INIT(rv, dev_id) \ - { \ - rv = dess_trunk_init(dev_id); \ - SW_RTN_ON_ERROR(rv); \ - } -#else -#define DESS_TRUNK_INIT(rv, dev_id) -#endif - -#ifdef HSL_STANDALONG - - HSL_LOCAL sw_error_t - dess_trunk_group_set(a_uint32_t dev_id, a_uint32_t trunk_id, - a_bool_t enable, fal_pbmp_t member); - - HSL_LOCAL sw_error_t - dess_trunk_group_get(a_uint32_t dev_id, a_uint32_t trunk_id, - a_bool_t * enable, fal_pbmp_t * member); - - HSL_LOCAL sw_error_t - dess_trunk_hash_mode_set(a_uint32_t dev_id, a_uint32_t hash_mode); - - HSL_LOCAL sw_error_t - dess_trunk_hash_mode_get(a_uint32_t dev_id, a_uint32_t * hash_mode); - -#endif - -#ifdef __cplusplus -} -#endif /* __cplusplus */ -#endif /* _DESS_TRUNK_H_ */ - diff --git a/feeds/ipq807x/qca-ssdk/src/include/hsl/dess/dess_vlan.h b/feeds/ipq807x/qca-ssdk/src/include/hsl/dess/dess_vlan.h deleted file mode 100755 index efe099219..000000000 --- a/feeds/ipq807x/qca-ssdk/src/include/hsl/dess/dess_vlan.h +++ /dev/null @@ -1,99 +0,0 @@ -/* - * Copyright (c) 2014, The Linux Foundation. All rights reserved. - * Permission to use, copy, modify, and/or distribute this software for - * any purpose with or without fee is hereby granted, provided that the - * above copyright notice and this permission notice appear in all copies. - * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES - * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR - * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES - * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN - * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT - * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. - */ - - -#ifndef _DESS_VLAN_H_ -#define _DESS_VLAN_H_ - -#ifdef __cplusplus -extern "C" { -#endif /* __cplusplus */ - -#include "fal/fal_vlan.h" - - sw_error_t - dess_vlan_init(a_uint32_t dev_id); - -#ifdef IN_VLAN -#define DESS_VLAN_INIT(rv, dev_id) \ - { \ - rv = dess_vlan_init(dev_id); \ - SW_RTN_ON_ERROR(rv); \ - } -#else -#define DESS_VLAN_INIT(rv, dev_id) -#endif - -#ifdef HSL_STANDALONG - - - HSL_LOCAL sw_error_t - dess_vlan_entry_append(a_uint32_t dev_id, const fal_vlan_t * vlan_entry); - - - HSL_LOCAL sw_error_t - dess_vlan_create(a_uint32_t dev_id, a_uint32_t vlan_id); - - - HSL_LOCAL sw_error_t - dess_vlan_next(a_uint32_t dev_id, a_uint32_t vlan_id, fal_vlan_t * p_vlan); - - - HSL_LOCAL sw_error_t - dess_vlan_find(a_uint32_t dev_id, a_uint32_t vlan_id, fal_vlan_t * p_vlan); - - - HSL_LOCAL sw_error_t - dess_vlan_delete(a_uint32_t dev_id, a_uint32_t vlan_id); - - - HSL_LOCAL sw_error_t - dess_vlan_flush(a_uint32_t dev_id); - - - HSL_LOCAL sw_error_t - dess_vlan_fid_set(a_uint32_t dev_id, a_uint32_t vlan_id, a_uint32_t fid); - - - HSL_LOCAL sw_error_t - dess_vlan_fid_get(a_uint32_t dev_id, a_uint32_t vlan_id, a_uint32_t * fid); - - - HSL_LOCAL sw_error_t - dess_vlan_member_add(a_uint32_t dev_id, a_uint32_t vlan_id, - fal_port_t port_id, fal_pt_1q_egmode_t port_info); - - - HSL_LOCAL sw_error_t - dess_vlan_member_del(a_uint32_t dev_id, a_uint32_t vlan_id, fal_port_t port_id); - - - HSL_LOCAL sw_error_t - dess_vlan_learning_state_set(a_uint32_t dev_id, a_uint32_t vlan_id, - a_bool_t enable); - - - HSL_LOCAL sw_error_t - dess_vlan_learning_state_get(a_uint32_t dev_id, a_uint32_t vlan_id, - a_bool_t * enable); - - -#endif - -#ifdef __cplusplus -} -#endif /* __cplusplus */ - -#endif /* _DESS_VLAN_H_ */ - diff --git a/feeds/ipq807x/qca-ssdk/src/include/hsl/garuda/garuda_acl.h b/feeds/ipq807x/qca-ssdk/src/include/hsl/garuda/garuda_acl.h deleted file mode 100755 index 2e6794a7a..000000000 --- a/feeds/ipq807x/qca-ssdk/src/include/hsl/garuda/garuda_acl.h +++ /dev/null @@ -1,120 +0,0 @@ -/* - * Copyright (c) 2012, The Linux Foundation. All rights reserved. - * Permission to use, copy, modify, and/or distribute this software for - * any purpose with or without fee is hereby granted, provided that the - * above copyright notice and this permission notice appear in all copies. - * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES - * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR - * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES - * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN - * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT - * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. - */ - - -/** - * @defgroup garuda_acl GARUDA_ACL - * @{ - */ -#ifndef _GARUDA_ACL_H_ -#define _GARUDA_ACL_H_ - -#ifdef __cplusplus -extern "C" { -#endif /* __cplusplus */ - -#include "fal/fal_acl.h" - - sw_error_t - garuda_acl_init(a_uint32_t dev_id); - - sw_error_t - garuda_acl_reset(a_uint32_t dev_id); - -#ifdef IN_ACL -#define GARUDA_ACL_INIT(rv, dev_id) \ - { \ - rv = garuda_acl_init(dev_id); \ - SW_RTN_ON_ERROR(rv); \ - } - -#define GARUDA_ACL_RESET(rv, dev_id) \ - { \ - rv = garuda_acl_reset(dev_id); \ - SW_RTN_ON_ERROR(rv); \ - } -#else -#define GARUDA_ACL_INIT(rv, dev_id) -#define GARUDA_ACL_RESET(rv, dev_id) -#endif - -#ifdef HSL_STANDALONG - - - HSL_LOCAL sw_error_t - garuda_acl_list_creat(a_uint32_t dev_id, a_uint32_t list_id, - a_uint32_t list_pri); - - - - HSL_LOCAL sw_error_t - garuda_acl_list_destroy(a_uint32_t dev_id, a_uint32_t list_id); - - - - HSL_LOCAL sw_error_t - garuda_acl_rule_add(a_uint32_t dev_id, a_uint32_t list_id, - a_uint32_t rule_id, a_uint32_t rule_nr, - fal_acl_rule_t * rule); - - - - HSL_LOCAL sw_error_t - garuda_acl_rule_delete(a_uint32_t dev_id, a_uint32_t list_id, - a_uint32_t rule_id, a_uint32_t rule_nr); - - - - HSL_LOCAL sw_error_t - garuda_acl_rule_query(a_uint32_t dev_id, a_uint32_t list_id, - a_uint32_t rule_id, fal_acl_rule_t * rule); - - - - HSL_LOCAL sw_error_t - garuda_acl_list_bind(a_uint32_t dev_id, a_uint32_t list_id, - fal_acl_direc_t direc, fal_acl_bind_obj_t obj_t, - a_uint32_t obj_idx); - - - HSL_LOCAL sw_error_t - garuda_acl_list_unbind(a_uint32_t dev_id, a_uint32_t list_id, - fal_acl_direc_t direc, fal_acl_bind_obj_t obj_t, - a_uint32_t obj_idx); - - - - HSL_LOCAL sw_error_t - garuda_acl_status_set(a_uint32_t dev_id, a_bool_t enable); - - - - HSL_LOCAL sw_error_t - garuda_acl_status_get(a_uint32_t dev_id, a_bool_t * enable); - - HSL_LOCAL sw_error_t - garuda_acl_list_dump(a_uint32_t dev_id); - - HSL_LOCAL sw_error_t - garuda_acl_rule_dump(a_uint32_t dev_id); - -#endif - -#ifdef __cplusplus -} -#endif /* __cplusplus */ -#endif /* _GARUDA_ACL_H_ */ -/** - * @} - */ diff --git a/feeds/ipq807x/qca-ssdk/src/include/hsl/garuda/garuda_api.h b/feeds/ipq807x/qca-ssdk/src/include/hsl/garuda/garuda_api.h deleted file mode 100755 index d5cd0cab8..000000000 --- a/feeds/ipq807x/qca-ssdk/src/include/hsl/garuda/garuda_api.h +++ /dev/null @@ -1,531 +0,0 @@ -/* - * Copyright (c) 2012, The Linux Foundation. All rights reserved. - * Permission to use, copy, modify, and/or distribute this software for - * any purpose with or without fee is hereby granted, provided that the - * above copyright notice and this permission notice appear in all copies. - * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES - * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR - * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES - * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN - * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT - * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. - */ - - - -#ifndef _GARUDA_API_H_ -#define _GARUDA_API_H_ - -#ifdef __cplusplus -extern "C" { -#endif /* __cplusplus */ - -#ifdef IN_PORTCONTROL -#define PORTCONTROL_API \ - SW_API_DEF(SW_API_PT_DUPLEX_GET, garuda_port_duplex_get), \ - SW_API_DEF(SW_API_PT_DUPLEX_SET, garuda_port_duplex_set), \ - SW_API_DEF(SW_API_PT_SPEED_GET, garuda_port_speed_get), \ - SW_API_DEF(SW_API_PT_SPEED_SET, garuda_port_speed_set), \ - SW_API_DEF(SW_API_PT_AN_GET, garuda_port_autoneg_status_get), \ - SW_API_DEF(SW_API_PT_AN_ENABLE, garuda_port_autoneg_enable), \ - SW_API_DEF(SW_API_PT_AN_RESTART, garuda_port_autoneg_restart), \ - SW_API_DEF(SW_API_PT_AN_ADV_GET, garuda_port_autoneg_adv_get), \ - SW_API_DEF(SW_API_PT_AN_ADV_SET, garuda_port_autoneg_adv_set), \ - SW_API_DEF(SW_API_PT_HDR_SET, garuda_port_hdr_status_set), \ - SW_API_DEF(SW_API_PT_HDR_GET, garuda_port_hdr_status_get), \ - SW_API_DEF(SW_API_PT_FLOWCTRL_SET, garuda_port_flowctrl_set), \ - SW_API_DEF(SW_API_PT_FLOWCTRL_GET, garuda_port_flowctrl_get), \ - SW_API_DEF(SW_API_PT_FLOWCTRL_MODE_SET, garuda_port_flowctrl_forcemode_set), \ - SW_API_DEF(SW_API_PT_FLOWCTRL_MODE_GET, garuda_port_flowctrl_forcemode_get),\ - SW_API_DEF(SW_API_PT_POWERSAVE_SET, garuda_port_powersave_set), \ - SW_API_DEF(SW_API_PT_POWERSAVE_GET, garuda_port_powersave_get), \ - SW_API_DEF(SW_API_PT_HIBERNATE_SET, garuda_port_hibernate_set), \ - SW_API_DEF(SW_API_PT_HIBERNATE_GET, garuda_port_hibernate_get), \ - SW_API_DEF(SW_API_PT_CDT, garuda_port_cdt), - -#define PORTCONTROL_API_PARAM \ - SW_API_DESC(SW_API_PT_DUPLEX_GET) \ - SW_API_DESC(SW_API_PT_DUPLEX_SET) \ - SW_API_DESC(SW_API_PT_SPEED_GET) \ - SW_API_DESC(SW_API_PT_SPEED_SET) \ - SW_API_DESC(SW_API_PT_AN_GET) \ - SW_API_DESC(SW_API_PT_AN_ENABLE) \ - SW_API_DESC(SW_API_PT_AN_RESTART) \ - SW_API_DESC(SW_API_PT_AN_ADV_GET) \ - SW_API_DESC(SW_API_PT_AN_ADV_SET) \ - SW_API_DESC(SW_API_PT_HDR_SET) \ - SW_API_DESC(SW_API_PT_HDR_GET) \ - SW_API_DESC(SW_API_PT_FLOWCTRL_SET) \ - SW_API_DESC(SW_API_PT_FLOWCTRL_GET) \ - SW_API_DESC(SW_API_PT_FLOWCTRL_MODE_SET) \ - SW_API_DESC(SW_API_PT_FLOWCTRL_MODE_GET)\ - SW_API_DESC(SW_API_PT_POWERSAVE_SET) \ - SW_API_DESC(SW_API_PT_POWERSAVE_GET) \ - SW_API_DESC(SW_API_PT_HIBERNATE_SET) \ - SW_API_DESC(SW_API_PT_HIBERNATE_GET) \ - SW_API_DESC(SW_API_PT_CDT) - -#else -#define PORTCONTROL_API -#define PORTCONTROL_API_PARAM -#endif - -#ifdef IN_VLAN -#define VLAN_API \ - SW_API_DEF(SW_API_VLAN_ADD, garuda_vlan_create), \ - SW_API_DEF(SW_API_VLAN_DEL, garuda_vlan_delete), \ - SW_API_DEF(SW_API_VLAN_MEM_UPDATE, garuda_vlan_member_update), \ - SW_API_DEF(SW_API_VLAN_FIND, garuda_vlan_find), \ - SW_API_DEF(SW_API_VLAN_NEXT, garuda_vlan_next), \ - SW_API_DEF(SW_API_VLAN_APPEND, garuda_vlan_entry_append), - -#define VLAN_API_PARAM \ - SW_API_DESC(SW_API_VLAN_ADD) \ - SW_API_DESC(SW_API_VLAN_DEL) \ - SW_API_DESC(SW_API_VLAN_MEM_UPDATE) \ - SW_API_DESC(SW_API_VLAN_FIND) \ - SW_API_DESC(SW_API_VLAN_NEXT) \ - SW_API_DESC(SW_API_VLAN_APPEND) -#else -#define VLAN_API -#define VLAN_API_PARAM -#endif - -#ifdef IN_PORTVLAN -#define PORTVLAN_API \ - SW_API_DEF(SW_API_PT_ING_MODE_GET, garuda_port_1qmode_get), \ - SW_API_DEF(SW_API_PT_ING_MODE_SET, garuda_port_1qmode_set), \ - SW_API_DEF(SW_API_PT_EG_MODE_GET, garuda_port_egvlanmode_get), \ - SW_API_DEF(SW_API_PT_EG_MODE_SET, garuda_port_egvlanmode_set), \ - SW_API_DEF(SW_API_PT_VLAN_MEM_ADD, garuda_portvlan_member_add), \ - SW_API_DEF(SW_API_PT_VLAN_MEM_DEL, garuda_portvlan_member_del), \ - SW_API_DEF(SW_API_PT_VLAN_MEM_UPDATE, garuda_portvlan_member_update), \ - SW_API_DEF(SW_API_PT_VLAN_MEM_GET, garuda_portvlan_member_get), \ - SW_API_DEF(SW_API_PT_DEF_VID_SET, garuda_port_default_vid_set), \ - SW_API_DEF(SW_API_PT_DEF_VID_GET, garuda_port_default_vid_get), \ - SW_API_DEF(SW_API_PT_FORCE_DEF_VID_SET, garuda_port_force_default_vid_set), \ - SW_API_DEF(SW_API_PT_FORCE_DEF_VID_GET, garuda_port_force_default_vid_get), \ - SW_API_DEF(SW_API_PT_FORCE_PORTVLAN_SET, garuda_port_force_portvlan_set), \ - SW_API_DEF(SW_API_PT_FORCE_PORTVLAN_GET, garuda_port_force_portvlan_get), \ - SW_API_DEF(SW_API_PT_NESTVLAN_SET, garuda_port_nestvlan_set), \ - SW_API_DEF(SW_API_PT_NESTVLAN_GET, garuda_port_nestvlan_get), \ - SW_API_DEF(SW_API_NESTVLAN_TPID_SET, garuda_nestvlan_tpid_set), \ - SW_API_DEF(SW_API_NESTVLAN_TPID_GET, garuda_nestvlan_tpid_get), - -#define PORTVLAN_API_PARAM \ - SW_API_DESC(SW_API_PT_ING_MODE_GET) \ - SW_API_DESC(SW_API_PT_ING_MODE_SET) \ - SW_API_DESC(SW_API_PT_EG_MODE_GET) \ - SW_API_DESC(SW_API_PT_EG_MODE_SET) \ - SW_API_DESC(SW_API_PT_VLAN_MEM_ADD) \ - SW_API_DESC(SW_API_PT_VLAN_MEM_DEL) \ - SW_API_DESC(SW_API_PT_VLAN_MEM_UPDATE) \ - SW_API_DESC(SW_API_PT_VLAN_MEM_GET) \ - SW_API_DESC(SW_API_PT_DEF_VID_SET) \ - SW_API_DESC(SW_API_PT_DEF_VID_GET) \ - SW_API_DESC(SW_API_PT_FORCE_DEF_VID_SET) \ - SW_API_DESC(SW_API_PT_FORCE_DEF_VID_GET) \ - SW_API_DESC(SW_API_PT_FORCE_PORTVLAN_SET) \ - SW_API_DESC(SW_API_PT_FORCE_PORTVLAN_GET) \ - SW_API_DESC(SW_API_PT_NESTVLAN_SET) \ - SW_API_DESC(SW_API_PT_NESTVLAN_GET) \ - SW_API_DESC(SW_API_NESTVLAN_TPID_SET) \ - SW_API_DESC(SW_API_NESTVLAN_TPID_GET) -#else -#define PORTVLAN_API -#define PORTVLAN_API_PARAM -#endif - -#ifdef IN_FDB -#define FDB_API \ - SW_API_DEF(SW_API_FDB_ADD, garuda_fdb_add), \ - SW_API_DEF(SW_API_FDB_DELALL, garuda_fdb_del_all), \ - SW_API_DEF(SW_API_FDB_DELPORT,garuda_fdb_del_by_port), \ - SW_API_DEF(SW_API_FDB_DELMAC, garuda_fdb_del_by_mac), \ - SW_API_DEF(SW_API_FDB_FIRST, garuda_fdb_first), \ - SW_API_DEF(SW_API_FDB_NEXT, garuda_fdb_next), \ - SW_API_DEF(SW_API_FDB_FIND, garuda_fdb_find), \ - SW_API_DEF(SW_API_FDB_PT_LEARN_SET, garuda_fdb_port_learn_set), \ - SW_API_DEF(SW_API_FDB_PT_LEARN_GET, garuda_fdb_port_learn_get), \ - SW_API_DEF(SW_API_FDB_AGE_CTRL_SET, garuda_fdb_age_ctrl_set), \ - SW_API_DEF(SW_API_FDB_AGE_CTRL_GET, garuda_fdb_age_ctrl_get), \ - SW_API_DEF(SW_API_FDB_AGE_TIME_SET, garuda_fdb_age_time_set), \ - SW_API_DEF(SW_API_FDB_AGE_TIME_GET, garuda_fdb_age_time_get), - -#define FDB_API_PARAM \ - SW_API_DESC(SW_API_FDB_ADD) \ - SW_API_DESC(SW_API_FDB_DELALL) \ - SW_API_DESC(SW_API_FDB_DELPORT) \ - SW_API_DESC(SW_API_FDB_DELMAC) \ - SW_API_DESC(SW_API_FDB_FIRST) \ - SW_API_DESC(SW_API_FDB_NEXT) \ - SW_API_DESC(SW_API_FDB_FIND) \ - SW_API_DESC(SW_API_FDB_PT_LEARN_SET) \ - SW_API_DESC(SW_API_FDB_PT_LEARN_GET) \ - SW_API_DESC(SW_API_FDB_AGE_CTRL_SET) \ - SW_API_DESC(SW_API_FDB_AGE_CTRL_GET) \ - SW_API_DESC(SW_API_FDB_AGE_TIME_SET) \ - SW_API_DESC(SW_API_FDB_AGE_TIME_GET) -#else -#define FDB_API -#define FDB_API_PARAM -#endif - -#ifdef IN_ACL -#define ACL_API \ - SW_API_DEF(SW_API_ACL_LIST_CREAT, garuda_acl_list_creat), \ - SW_API_DEF(SW_API_ACL_LIST_DESTROY, garuda_acl_list_destroy), \ - SW_API_DEF(SW_API_ACL_RULE_ADD, garuda_acl_rule_add), \ - SW_API_DEF(SW_API_ACL_RULE_DELETE, garuda_acl_rule_delete), \ - SW_API_DEF(SW_API_ACL_RULE_QUERY, garuda_acl_rule_query), \ - SW_API_DEF(SW_API_ACL_LIST_BIND, garuda_acl_list_bind), \ - SW_API_DEF(SW_API_ACL_LIST_UNBIND, garuda_acl_list_unbind), \ - SW_API_DEF(SW_API_ACL_STATUS_SET, garuda_acl_status_set), \ - SW_API_DEF(SW_API_ACL_STATUS_GET, garuda_acl_status_get), \ - SW_API_DEF(SW_API_ACL_LIST_DUMP, garuda_acl_list_dump), \ - SW_API_DEF(SW_API_ACL_RULE_DUMP, garuda_acl_rule_dump), - -#define ACL_API_PARAM \ - SW_API_DESC(SW_API_ACL_LIST_CREAT) \ - SW_API_DESC(SW_API_ACL_LIST_DESTROY) \ - SW_API_DESC(SW_API_ACL_RULE_ADD) \ - SW_API_DESC(SW_API_ACL_RULE_DELETE) \ - SW_API_DESC(SW_API_ACL_RULE_QUERY) \ - SW_API_DESC(SW_API_ACL_LIST_BIND) \ - SW_API_DESC(SW_API_ACL_LIST_UNBIND) \ - SW_API_DESC(SW_API_ACL_STATUS_SET) \ - SW_API_DESC(SW_API_ACL_STATUS_GET) \ - SW_API_DESC(SW_API_ACL_LIST_DUMP) \ - SW_API_DESC(SW_API_ACL_RULE_DUMP) -#else -#define ACL_API -#define ACL_API_PARAM -#endif - -#ifdef IN_QOS -#define QOS_API \ - SW_API_DEF(SW_API_QOS_SCH_MODE_SET, garuda_qos_sch_mode_set), \ - SW_API_DEF(SW_API_QOS_SCH_MODE_GET, garuda_qos_sch_mode_get), \ - SW_API_DEF(SW_API_QOS_QU_TX_BUF_ST_SET, garuda_qos_queue_tx_buf_status_set), \ - SW_API_DEF(SW_API_QOS_QU_TX_BUF_ST_GET, garuda_qos_queue_tx_buf_status_get), \ - SW_API_DEF(SW_API_QOS_QU_TX_BUF_NR_SET, garuda_qos_queue_tx_buf_nr_set), \ - SW_API_DEF(SW_API_QOS_QU_TX_BUF_NR_GET, garuda_qos_queue_tx_buf_nr_get), \ - SW_API_DEF(SW_API_QOS_PT_TX_BUF_ST_SET, garuda_qos_port_tx_buf_status_set), \ - SW_API_DEF(SW_API_QOS_PT_TX_BUF_ST_GET, garuda_qos_port_tx_buf_status_get), \ - SW_API_DEF(SW_API_QOS_PT_TX_BUF_NR_SET, garuda_qos_port_tx_buf_nr_set), \ - SW_API_DEF(SW_API_QOS_PT_TX_BUF_NR_GET, garuda_qos_port_tx_buf_nr_get), \ - SW_API_DEF(SW_API_COSMAP_UP_QU_SET, garuda_cosmap_up_queue_set), \ - SW_API_DEF(SW_API_COSMAP_UP_QU_GET, garuda_cosmap_up_queue_get), \ - SW_API_DEF(SW_API_COSMAP_DSCP_QU_SET, garuda_cosmap_dscp_queue_set), \ - SW_API_DEF(SW_API_COSMAP_DSCP_QU_GET, garuda_cosmap_dscp_queue_get), \ - SW_API_DEF(SW_API_QOS_PT_MODE_SET, garuda_qos_port_mode_set), \ - SW_API_DEF(SW_API_QOS_PT_MODE_GET, garuda_qos_port_mode_get), \ - SW_API_DEF(SW_API_QOS_PT_MODE_PRI_SET, garuda_qos_port_mode_pri_set), \ - SW_API_DEF(SW_API_QOS_PT_MODE_PRI_GET, garuda_qos_port_mode_pri_get), \ - SW_API_DEF(SW_API_QOS_PORT_DEF_UP_SET, garuda_qos_port_default_up_set), \ - SW_API_DEF(SW_API_QOS_PORT_DEF_UP_GET, garuda_qos_port_default_up_get), - -#define QOS_API_PARAM \ - SW_API_DESC(SW_API_QOS_SCH_MODE_SET) \ - SW_API_DESC(SW_API_QOS_SCH_MODE_GET) \ - SW_API_DESC(SW_API_QOS_QU_TX_BUF_ST_SET) \ - SW_API_DESC(SW_API_QOS_QU_TX_BUF_ST_GET) \ - SW_API_DESC(SW_API_QOS_QU_TX_BUF_NR_SET) \ - SW_API_DESC(SW_API_QOS_QU_TX_BUF_NR_GET) \ - SW_API_DESC(SW_API_QOS_PT_TX_BUF_ST_SET) \ - SW_API_DESC(SW_API_QOS_PT_TX_BUF_ST_GET) \ - SW_API_DESC(SW_API_QOS_PT_TX_BUF_NR_SET) \ - SW_API_DESC(SW_API_QOS_PT_TX_BUF_NR_GET) \ - SW_API_DESC(SW_API_COSMAP_UP_QU_SET) \ - SW_API_DESC(SW_API_COSMAP_UP_QU_GET) \ - SW_API_DESC(SW_API_COSMAP_DSCP_QU_SET) \ - SW_API_DESC(SW_API_COSMAP_DSCP_QU_GET) \ - SW_API_DESC(SW_API_QOS_PT_MODE_SET) \ - SW_API_DESC(SW_API_QOS_PT_MODE_GET) \ - SW_API_DESC(SW_API_QOS_PT_MODE_PRI_SET) \ - SW_API_DESC(SW_API_QOS_PT_MODE_PRI_GET) \ - SW_API_DESC(SW_API_QOS_PORT_DEF_UP_SET) \ - SW_API_DESC(SW_API_QOS_PORT_DEF_UP_GET) -#else -#define QOS_API -#define QOS_API_PARAM -#endif - -#ifdef IN_IGMP -#define IGMP_API \ - SW_API_DEF(SW_API_PT_IGMPS_MODE_SET, garuda_port_igmps_status_set), \ - SW_API_DEF(SW_API_PT_IGMPS_MODE_GET, garuda_port_igmps_status_get), \ - SW_API_DEF(SW_API_IGMP_MLD_CMD_SET, garuda_igmp_mld_cmd_set), \ - SW_API_DEF(SW_API_IGMP_MLD_CMD_GET, garuda_igmp_mld_cmd_get), \ - SW_API_DEF(SW_API_IGMP_PT_JOIN_SET, garuda_port_igmp_mld_join_set), \ - SW_API_DEF(SW_API_IGMP_PT_JOIN_GET, garuda_port_igmp_mld_join_get), \ - SW_API_DEF(SW_API_IGMP_PT_LEAVE_SET, garuda_port_igmp_mld_leave_set), \ - SW_API_DEF(SW_API_IGMP_PT_LEAVE_GET, garuda_port_igmp_mld_leave_get), \ - SW_API_DEF(SW_API_IGMP_RP_SET, garuda_igmp_mld_rp_set), \ - SW_API_DEF(SW_API_IGMP_RP_GET, garuda_igmp_mld_rp_get), \ - SW_API_DEF(SW_API_IGMP_ENTRY_CREAT_SET, garuda_igmp_mld_entry_creat_set), \ - SW_API_DEF(SW_API_IGMP_ENTRY_CREAT_GET, garuda_igmp_mld_entry_creat_get), - -#define IGMP_API_PARAM \ - SW_API_DESC(SW_API_PT_IGMPS_MODE_SET) \ - SW_API_DESC(SW_API_PT_IGMPS_MODE_GET) \ - SW_API_DESC(SW_API_IGMP_MLD_CMD_SET) \ - SW_API_DESC(SW_API_IGMP_MLD_CMD_GET) \ - SW_API_DESC(SW_API_IGMP_PT_JOIN_SET) \ - SW_API_DESC(SW_API_IGMP_PT_JOIN_GET) \ - SW_API_DESC(SW_API_IGMP_PT_LEAVE_SET) \ - SW_API_DESC(SW_API_IGMP_PT_LEAVE_GET) \ - SW_API_DESC(SW_API_IGMP_RP_SET) \ - SW_API_DESC(SW_API_IGMP_RP_GET) \ - SW_API_DESC(SW_API_IGMP_ENTRY_CREAT_SET) \ - SW_API_DESC(SW_API_IGMP_ENTRY_CREAT_GET) -#else -#define IGMP_API -#define IGMP_API_PARAM -#endif - -#ifdef IN_LEAKY -#define LEAKY_API \ - SW_API_DEF(SW_API_UC_LEAKY_MODE_SET, garuda_uc_leaky_mode_set), \ - SW_API_DEF(SW_API_UC_LEAKY_MODE_GET, garuda_uc_leaky_mode_get), \ - SW_API_DEF(SW_API_MC_LEAKY_MODE_SET, garuda_mc_leaky_mode_set), \ - SW_API_DEF(SW_API_MC_LEAKY_MODE_GET, garuda_mc_leaky_mode_get), \ - SW_API_DEF(SW_API_ARP_LEAKY_MODE_SET, garuda_port_arp_leaky_set), \ - SW_API_DEF(SW_API_ARP_LEAKY_MODE_GET, garuda_port_arp_leaky_get), \ - SW_API_DEF(SW_API_PT_UC_LEAKY_MODE_SET, garuda_port_uc_leaky_set), \ - SW_API_DEF(SW_API_PT_UC_LEAKY_MODE_GET, garuda_port_uc_leaky_get), \ - SW_API_DEF(SW_API_PT_MC_LEAKY_MODE_SET, garuda_port_mc_leaky_set), \ - SW_API_DEF(SW_API_PT_MC_LEAKY_MODE_GET, garuda_port_mc_leaky_get), - -#define LEAKY_API_PARAM \ - SW_API_DESC(SW_API_UC_LEAKY_MODE_SET) \ - SW_API_DESC(SW_API_UC_LEAKY_MODE_GET) \ - SW_API_DESC(SW_API_MC_LEAKY_MODE_SET) \ - SW_API_DESC(SW_API_MC_LEAKY_MODE_GET) \ - SW_API_DESC(SW_API_ARP_LEAKY_MODE_SET) \ - SW_API_DESC(SW_API_ARP_LEAKY_MODE_GET) \ - SW_API_DESC(SW_API_PT_UC_LEAKY_MODE_SET) \ - SW_API_DESC(SW_API_PT_UC_LEAKY_MODE_GET) \ - SW_API_DESC(SW_API_PT_MC_LEAKY_MODE_SET) \ - SW_API_DESC(SW_API_PT_MC_LEAKY_MODE_GET) -#else -#define LEAKY_API -#define LEAKY_API_PARAM -#endif - -#ifdef IN_MIRROR -#define MIRROR_API \ - SW_API_DEF(SW_API_MIRROR_ANALY_PT_SET, garuda_mirr_analysis_port_set), \ - SW_API_DEF(SW_API_MIRROR_ANALY_PT_GET, garuda_mirr_analysis_port_get), \ - SW_API_DEF(SW_API_MIRROR_IN_PT_SET, garuda_mirr_port_in_set), \ - SW_API_DEF(SW_API_MIRROR_IN_PT_GET, garuda_mirr_port_in_get), \ - SW_API_DEF(SW_API_MIRROR_EG_PT_SET, garuda_mirr_port_eg_set), \ - SW_API_DEF(SW_API_MIRROR_EG_PT_GET, garuda_mirr_port_eg_get), - -#define MIRROR_API_PARAM \ - SW_API_DESC(SW_API_MIRROR_ANALY_PT_SET) \ - SW_API_DESC(SW_API_MIRROR_ANALY_PT_GET) \ - SW_API_DESC(SW_API_MIRROR_IN_PT_SET) \ - SW_API_DESC(SW_API_MIRROR_IN_PT_GET) \ - SW_API_DESC(SW_API_MIRROR_EG_PT_SET) \ - SW_API_DESC(SW_API_MIRROR_EG_PT_GET) -#else -#define MIRROR_API -#define MIRROR_API_PARAM -#endif - -#ifdef IN_RATE -#define RATE_API \ - SW_API_DEF(SW_API_RATE_QU_EGRL_SET, garuda_rate_queue_egrl_set), \ - SW_API_DEF(SW_API_RATE_QU_EGRL_GET, garuda_rate_queue_egrl_get), \ - SW_API_DEF(SW_API_RATE_PT_EGRL_SET, garuda_rate_port_egrl_set), \ - SW_API_DEF(SW_API_RATE_PT_EGRL_GET, garuda_rate_port_egrl_get), \ - SW_API_DEF(SW_API_RATE_PT_INRL_SET, garuda_rate_port_inrl_set), \ - SW_API_DEF(SW_API_RATE_PT_INRL_GET, garuda_rate_port_inrl_get), \ - SW_API_DEF(SW_API_STORM_CTRL_FRAME_SET, garuda_storm_ctrl_frame_set), \ - SW_API_DEF(SW_API_STORM_CTRL_FRAME_GET, garuda_storm_ctrl_frame_get), \ - SW_API_DEF(SW_API_STORM_CTRL_RATE_SET, garuda_storm_ctrl_rate_set), \ - SW_API_DEF(SW_API_STORM_CTRL_RATE_GET, garuda_storm_ctrl_rate_get), - -#define RATE_API_PARAM \ - SW_API_DESC(SW_API_RATE_QU_EGRL_SET) \ - SW_API_DESC(SW_API_RATE_QU_EGRL_GET) \ - SW_API_DESC(SW_API_RATE_PT_EGRL_SET) \ - SW_API_DESC(SW_API_RATE_PT_EGRL_GET) \ - SW_API_DESC(SW_API_RATE_PT_INRL_SET) \ - SW_API_DESC(SW_API_RATE_PT_INRL_GET) \ - SW_API_DESC(SW_API_STORM_CTRL_FRAME_SET) \ - SW_API_DESC(SW_API_STORM_CTRL_FRAME_GET) \ - SW_API_DESC(SW_API_STORM_CTRL_RATE_SET) \ - SW_API_DESC(SW_API_STORM_CTRL_RATE_GET) -#else -#define RATE_API -#define RATE_API_PARAM -#endif - -#ifdef IN_STP -#define STP_API \ - SW_API_DEF(SW_API_STP_PT_STATE_SET, garuda_stp_port_state_set), \ - SW_API_DEF(SW_API_STP_PT_STATE_GET, garuda_stp_port_state_get), - -#define STP_API_PARAM \ - SW_API_DESC(SW_API_STP_PT_STATE_SET) \ - SW_API_DESC(SW_API_STP_PT_STATE_GET) -#else -#define STP_API -#define STP_API_PARAM -#endif - -#ifdef IN_MIB -#define MIB_API \ - SW_API_DEF(SW_API_PT_MIB_GET, garuda_get_mib_info), \ - SW_API_DEF(SW_API_MIB_STATUS_SET, garuda_mib_status_set), \ - SW_API_DEF(SW_API_MIB_STATUS_GET, garuda_mib_status_get), - -#define MIB_API_PARAM \ - SW_API_DESC(SW_API_PT_MIB_GET) \ - SW_API_DESC(SW_API_MIB_STATUS_SET) \ - SW_API_DESC(SW_API_MIB_STATUS_GET) -#else -#define MIB_API -#define MIB_API_PARAM -#endif - -#ifdef IN_MISC -#define MISC_API \ - SW_API_DEF(SW_API_ARP_STATUS_SET, garuda_arp_status_set), \ - SW_API_DEF(SW_API_ARP_STATUS_GET, garuda_arp_status_get), \ - SW_API_DEF(SW_API_FRAME_MAX_SIZE_SET, garuda_frame_max_size_set), \ - SW_API_DEF(SW_API_FRAME_MAX_SIZE_GET, garuda_frame_max_size_get), \ - SW_API_DEF(SW_API_PT_UNK_SA_CMD_SET, garuda_port_unk_sa_cmd_set), \ - SW_API_DEF(SW_API_PT_UNK_SA_CMD_GET, garuda_port_unk_sa_cmd_get), \ - SW_API_DEF(SW_API_PT_UNK_UC_FILTER_SET, garuda_port_unk_uc_filter_set), \ - SW_API_DEF(SW_API_PT_UNK_UC_FILTER_GET, garuda_port_unk_uc_filter_get), \ - SW_API_DEF(SW_API_PT_UNK_MC_FILTER_SET, garuda_port_unk_mc_filter_set), \ - SW_API_DEF(SW_API_PT_UNK_MC_FILTER_GET, garuda_port_unk_mc_filter_get), \ - SW_API_DEF(SW_API_CPU_PORT_STATUS_SET, garuda_cpu_port_status_set), \ - SW_API_DEF(SW_API_CPU_PORT_STATUS_GET, garuda_cpu_port_status_get), \ - SW_API_DEF(SW_API_BC_TO_CPU_PORT_SET, garuda_bc_to_cpu_port_set), \ - SW_API_DEF(SW_API_BC_TO_CPU_PORT_GET, garuda_bc_to_cpu_port_get), \ - SW_API_DEF(SW_API_PPPOE_CMD_SET, garuda_pppoe_cmd_set), \ - SW_API_DEF(SW_API_PPPOE_CMD_GET, garuda_pppoe_cmd_get), \ - SW_API_DEF(SW_API_PPPOE_STATUS_SET, garuda_pppoe_status_set), \ - SW_API_DEF(SW_API_PPPOE_STATUS_GET, garuda_pppoe_status_get), \ - SW_API_DEF(SW_API_PT_DHCP_SET, garuda_port_dhcp_set), \ - SW_API_DEF(SW_API_PT_DHCP_GET, garuda_port_dhcp_get), - -#define MISC_API_PARAM \ - SW_API_DESC(SW_API_ARP_STATUS_SET) \ - SW_API_DESC(SW_API_ARP_STATUS_GET) \ - SW_API_DESC(SW_API_FRAME_MAX_SIZE_SET) \ - SW_API_DESC(SW_API_FRAME_MAX_SIZE_GET) \ - SW_API_DESC(SW_API_PT_UNK_SA_CMD_SET) \ - SW_API_DESC(SW_API_PT_UNK_SA_CMD_GET) \ - SW_API_DESC(SW_API_PT_UNK_UC_FILTER_SET) \ - SW_API_DESC(SW_API_PT_UNK_UC_FILTER_GET) \ - SW_API_DESC(SW_API_PT_UNK_MC_FILTER_SET) \ - SW_API_DESC(SW_API_PT_UNK_MC_FILTER_GET) \ - SW_API_DESC(SW_API_CPU_PORT_STATUS_SET) \ - SW_API_DESC(SW_API_CPU_PORT_STATUS_GET) \ - SW_API_DESC(SW_API_BC_TO_CPU_PORT_SET) \ - SW_API_DESC(SW_API_BC_TO_CPU_PORT_GET) \ - SW_API_DESC(SW_API_PPPOE_CMD_SET) \ - SW_API_DESC(SW_API_PPPOE_CMD_GET) \ - SW_API_DESC(SW_API_PPPOE_STATUS_SET) \ - SW_API_DESC(SW_API_PPPOE_STATUS_GET) \ - SW_API_DESC(SW_API_PT_DHCP_SET) \ - SW_API_DESC(SW_API_PT_DHCP_GET) -#else -#define MISC_API -#define MISC_API_PARAM -#endif - -#ifdef IN_LED -#define LED_API \ - SW_API_DEF(SW_API_LED_PATTERN_SET, garuda_led_ctrl_pattern_set), \ - SW_API_DEF(SW_API_LED_PATTERN_GET, garuda_led_ctrl_pattern_get), - -#define LED_API_PARAM \ - SW_API_DESC(SW_API_LED_PATTERN_SET) \ - SW_API_DESC(SW_API_LED_PATTERN_GET) -#else -#define LED_API -#define LED_API_PARAM -#endif - -#define REG_API \ - SW_API_DEF(SW_API_PHY_GET, garuda_phy_get), \ - SW_API_DEF(SW_API_PHY_SET, garuda_phy_set), \ - SW_API_DEF(SW_API_REG_GET, garuda_reg_get), \ - SW_API_DEF(SW_API_REG_SET, garuda_reg_set), \ - SW_API_DEF(SW_API_REG_FIELD_GET, garuda_reg_field_get), \ - SW_API_DEF(SW_API_REG_FIELD_SET, garuda_reg_field_set), - -#define REG_API_PARAM \ - SW_API_DESC(SW_API_PHY_GET) \ - SW_API_DESC(SW_API_PHY_SET) \ - SW_API_DESC(SW_API_REG_GET) \ - SW_API_DESC(SW_API_REG_SET) \ - SW_API_DESC(SW_API_REG_FIELD_GET) \ - SW_API_DESC(SW_API_REG_FIELD_SET) - -#define SSDK_API \ - SW_API_DEF(SW_API_SWITCH_RESET, garuda_reset), \ - SW_API_DEF(SW_API_SSDK_CFG, hsl_ssdk_cfg), \ - PORTCONTROL_API \ - VLAN_API \ - PORTVLAN_API \ - FDB_API \ - ACL_API \ - QOS_API \ - IGMP_API \ - LEAKY_API \ - MIRROR_API \ - RATE_API \ - STP_API \ - MIB_API \ - MISC_API \ - LED_API \ - REG_API \ - SW_API_DEF(SW_API_MAX, NULL), - -#define SSDK_PARAM \ - SW_PARAM_DEF(SW_API_SWITCH_RESET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \ - SW_PARAM_DEF(SW_API_SSDK_CFG, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \ - SW_PARAM_DEF(SW_API_SSDK_CFG, SW_SSDK_CFG, sizeof(ssdk_cfg_t), SW_PARAM_PTR|SW_PARAM_OUT, "ssdk configuration"), \ - MIB_API_PARAM \ - LEAKY_API_PARAM \ - MISC_API_PARAM \ - IGMP_API_PARAM \ - MIRROR_API_PARAM \ - PORTCONTROL_API_PARAM \ - PORTVLAN_API_PARAM \ - VLAN_API_PARAM \ - FDB_API_PARAM \ - QOS_API_PARAM \ - RATE_API_PARAM \ - STP_API_PARAM \ - ACL_API_PARAM \ - LED_API_PARAM \ - REG_API_PARAM \ - SW_PARAM_DEF(SW_API_MAX, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), - -#if (defined(USER_MODE) && defined(KERNEL_MODULE)) -#undef SSDK_API -#undef SSDK_PARAM - -#define SSDK_API \ - REG_API \ - SW_API_DEF(SW_API_MAX, NULL), - -#define SSDK_PARAM \ - REG_API_PARAM \ - SW_PARAM_DEF(SW_API_MAX, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), -#endif - -#ifdef __cplusplus -} -#endif /* __cplusplus */ - -#endif /* _GARUDA_API_H_ */ diff --git a/feeds/ipq807x/qca-ssdk/src/include/hsl/garuda/garuda_fdb.h b/feeds/ipq807x/qca-ssdk/src/include/hsl/garuda/garuda_fdb.h deleted file mode 100755 index b50d2fc67..000000000 --- a/feeds/ipq807x/qca-ssdk/src/include/hsl/garuda/garuda_fdb.h +++ /dev/null @@ -1,120 +0,0 @@ -/* - * Copyright (c) 2012, The Linux Foundation. All rights reserved. - * Permission to use, copy, modify, and/or distribute this software for - * any purpose with or without fee is hereby granted, provided that the - * above copyright notice and this permission notice appear in all copies. - * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES - * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR - * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES - * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN - * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT - * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. - */ - - -/** - * @defgroup garuda_fdb GARUDA_FDB - * @{ - */ -#ifndef _GARUDA_FDB_H_ -#define _GARUDA_FDB_H_ - -#ifdef __cplusplus -extern "C" { -#endif /* __cplusplus */ - -#include "fal/fal_fdb.h" - - sw_error_t - garuda_fdb_init(a_uint32_t dev_id); - -#ifdef IN_FDB -#define GARUDA_FDB_INIT(rv, dev_id) \ - { \ - rv = garuda_fdb_init(dev_id); \ - SW_RTN_ON_ERROR(rv); \ - } -#else -#define GARUDA_FDB_INIT(rv, dev_id) -#endif - -#ifdef HSL_STANDALONG - - - HSL_LOCAL sw_error_t - garuda_fdb_add(a_uint32_t dev_id, const fal_fdb_entry_t * entry); - - - - HSL_LOCAL sw_error_t - garuda_fdb_del_all(a_uint32_t dev_id, a_uint32_t flag); - - - - HSL_LOCAL sw_error_t - garuda_fdb_del_by_port(a_uint32_t dev_id, a_uint32_t port_id, a_uint32_t flag); - - - - HSL_LOCAL sw_error_t - garuda_fdb_del_by_mac(a_uint32_t dev_id, - const fal_fdb_entry_t *entry); - - - - HSL_LOCAL sw_error_t - garuda_fdb_first(a_uint32_t dev_id, fal_fdb_entry_t * entry); - - - - HSL_LOCAL sw_error_t - garuda_fdb_next(a_uint32_t dev_id, fal_fdb_entry_t * entry); - - - - HSL_LOCAL sw_error_t - garuda_fdb_find(a_uint32_t dev_id, fal_fdb_entry_t * entry); - - - - HSL_LOCAL sw_error_t - garuda_fdb_port_learn_set(a_uint32_t dev_id, fal_port_t port_id, - a_bool_t enable); - - - - HSL_LOCAL sw_error_t - garuda_fdb_port_learn_get(a_uint32_t dev_id, fal_port_t port_id, - a_bool_t *enable); - - - - HSL_LOCAL sw_error_t - garuda_fdb_age_ctrl_set(a_uint32_t dev_id, a_bool_t enable); - - - - HSL_LOCAL sw_error_t - garuda_fdb_age_ctrl_get(a_uint32_t dev_id, a_bool_t *enable); - - - - HSL_LOCAL sw_error_t - garuda_fdb_age_time_set(a_uint32_t dev_id, a_uint32_t * time); - - - - HSL_LOCAL sw_error_t - garuda_fdb_age_time_get(a_uint32_t dev_id, a_uint32_t * time); - -#endif - -#ifdef __cplusplus -} -#endif /* __cplusplus */ - -#endif /* _GARUDA_FDB_H_ */ -/** - * @} - */ diff --git a/feeds/ipq807x/qca-ssdk/src/include/hsl/garuda/garuda_igmp.h b/feeds/ipq807x/qca-ssdk/src/include/hsl/garuda/garuda_igmp.h deleted file mode 100755 index 487230418..000000000 --- a/feeds/ipq807x/qca-ssdk/src/include/hsl/garuda/garuda_igmp.h +++ /dev/null @@ -1,111 +0,0 @@ -/* - * Copyright (c) 2012, The Linux Foundation. All rights reserved. - * Permission to use, copy, modify, and/or distribute this software for - * any purpose with or without fee is hereby granted, provided that the - * above copyright notice and this permission notice appear in all copies. - * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES - * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR - * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES - * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN - * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT - * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. - */ - - -/** - * @defgroup garuda_igmp GARUDA_IGMP - * @{ - */ -#ifndef _GARUDA_IGMP_H_ -#define _GARUDA_IGMP_H_ - -#ifdef __cplusplus -extern "C" { -#endif /* __cplusplus */ - -#include "fal/fal_igmp.h" - - sw_error_t - garuda_igmp_init(a_uint32_t dev_id); - -#ifdef IN_IGMP -#define GARUDA_IGMP_INIT(rv, dev_id) \ - { \ - rv = garuda_igmp_init(dev_id); \ - SW_RTN_ON_ERROR(rv); \ - } -#else -#define GARUDA_IGMP_INIT(rv, dev_id) -#endif - -#ifdef HSL_STANDALONG - - - HSL_LOCAL sw_error_t - garuda_port_igmps_status_set(a_uint32_t dev_id, fal_port_t port_id, a_bool_t enable); - - - - HSL_LOCAL sw_error_t - garuda_port_igmps_status_get(a_uint32_t dev_id, fal_port_t port_id, a_bool_t *enable); - - - - HSL_LOCAL sw_error_t - garuda_igmp_mld_cmd_set(a_uint32_t dev_id, fal_fwd_cmd_t cmd); - - - - HSL_LOCAL sw_error_t - garuda_igmp_mld_cmd_get(a_uint32_t dev_id, fal_fwd_cmd_t * cmd); - - - - HSL_LOCAL sw_error_t - garuda_port_igmp_mld_join_set(a_uint32_t dev_id, fal_port_t port_id, a_bool_t enable); - - - - HSL_LOCAL sw_error_t - garuda_port_igmp_mld_join_get(a_uint32_t dev_id, fal_port_t port_id, a_bool_t * enable); - - - - HSL_LOCAL sw_error_t - garuda_port_igmp_mld_leave_set(a_uint32_t dev_id, fal_port_t port_id, a_bool_t enable); - - - - HSL_LOCAL sw_error_t - garuda_port_igmp_mld_leave_get(a_uint32_t dev_id, fal_port_t port_id, a_bool_t * enable); - - - - HSL_LOCAL sw_error_t - garuda_igmp_mld_rp_set(a_uint32_t dev_id, fal_pbmp_t pts); - - - - HSL_LOCAL sw_error_t - garuda_igmp_mld_rp_get(a_uint32_t dev_id, fal_pbmp_t * pts); - - - - HSL_LOCAL sw_error_t - garuda_igmp_mld_entry_creat_set(a_uint32_t dev_id, a_bool_t enable); - - - - HSL_LOCAL sw_error_t - garuda_igmp_mld_entry_creat_get(a_uint32_t dev_id, a_bool_t * enable); -#endif - -#ifdef __cplusplus -} -#endif /* __cplusplus */ - -#endif /* _GARUDA_IGMP_H_ */ -/** - * @} - */ diff --git a/feeds/ipq807x/qca-ssdk/src/include/hsl/garuda/garuda_init.h b/feeds/ipq807x/qca-ssdk/src/include/hsl/garuda/garuda_init.h deleted file mode 100755 index b72450115..000000000 --- a/feeds/ipq807x/qca-ssdk/src/include/hsl/garuda/garuda_init.h +++ /dev/null @@ -1,47 +0,0 @@ -/* - * Copyright (c) 2012, The Linux Foundation. All rights reserved. - * Permission to use, copy, modify, and/or distribute this software for - * any purpose with or without fee is hereby granted, provided that the - * above copyright notice and this permission notice appear in all copies. - * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES - * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR - * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES - * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN - * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT - * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. - */ - - -/** - * @defgroup garuda_init GARUDA_INIT - * @{ - */ -#ifndef _GARUDA_INIT_H_ -#define _GARUDA_INIT_H_ - -#ifdef __cplusplus -extern "C" { -#endif /* __cplusplus */ - -#include "init/ssdk_init.h" - - sw_error_t - garuda_init(a_uint32_t dev_id, ssdk_init_cfg *cfg); - - sw_error_t - garuda_cleanup(a_uint32_t dev_id); - -#ifdef HSL_STANDALONG - - HSL_LOCAL sw_error_t - garuda_reset(a_uint32_t dev_id); - -#endif - -#ifdef __cplusplus -} -#endif /* __cplusplus */ - -#endif /* _GARUDA_INIT_H_ */ - diff --git a/feeds/ipq807x/qca-ssdk/src/include/hsl/garuda/garuda_leaky.h b/feeds/ipq807x/qca-ssdk/src/include/hsl/garuda/garuda_leaky.h deleted file mode 100755 index dfd95ec7f..000000000 --- a/feeds/ipq807x/qca-ssdk/src/include/hsl/garuda/garuda_leaky.h +++ /dev/null @@ -1,107 +0,0 @@ -/* - * Copyright (c) 2012, The Linux Foundation. All rights reserved. - * Permission to use, copy, modify, and/or distribute this software for - * any purpose with or without fee is hereby granted, provided that the - * above copyright notice and this permission notice appear in all copies. - * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES - * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR - * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES - * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN - * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT - * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. - */ - - -/** - * @defgroup garuda_leaky GARUDA_LEAKY - * @{ - */ -#ifndef _GARUDA_LEAKY_H_ -#define _GARUDA_LEAKY_H_ - -#ifdef __cplusplus -extern "C" { -#endif /* __cplusplus */ - -#include "fal/fal_leaky.h" - - sw_error_t garuda_leaky_init(a_uint32_t dev_id); - -#ifdef IN_LEAKY -#define GARUDA_LEAKY_INIT(rv, dev_id) \ - { \ - rv = garuda_leaky_init(dev_id); \ - SW_RTN_ON_ERROR(rv); \ - } -#else -#define GARUDA_LEAKY_INIT(rv, dev_id) -#endif - -#ifdef HSL_STANDALONG - - - HSL_LOCAL sw_error_t - garuda_uc_leaky_mode_set(a_uint32_t dev_id, - fal_leaky_ctrl_mode_t ctrl_mode); - - - - HSL_LOCAL sw_error_t - garuda_uc_leaky_mode_get(a_uint32_t dev_id, - fal_leaky_ctrl_mode_t * ctrl_mode); - - - - HSL_LOCAL sw_error_t - garuda_mc_leaky_mode_set(a_uint32_t dev_id, - fal_leaky_ctrl_mode_t ctrl_mode); - - - HSL_LOCAL sw_error_t - garuda_mc_leaky_mode_get(a_uint32_t dev_id, - fal_leaky_ctrl_mode_t * ctrl_mode); - - - - HSL_LOCAL sw_error_t - garuda_port_arp_leaky_set(a_uint32_t dev_id, fal_port_t port_id, - a_bool_t enable); - - - - HSL_LOCAL sw_error_t - garuda_port_arp_leaky_get(a_uint32_t dev_id, fal_port_t port_id, - a_bool_t * enable); - - - - HSL_LOCAL sw_error_t - garuda_port_uc_leaky_set(a_uint32_t dev_id, fal_port_t port_id, - a_bool_t enable); - - - - HSL_LOCAL sw_error_t - garuda_port_uc_leaky_get(a_uint32_t dev_id, fal_port_t port_id, - a_bool_t * enable); - - - HSL_LOCAL sw_error_t - garuda_port_mc_leaky_set(a_uint32_t dev_id, fal_port_t port_id, - a_bool_t enable); - - - - HSL_LOCAL sw_error_t - garuda_port_mc_leaky_get(a_uint32_t dev_id, fal_port_t port_id, - a_bool_t * enable); -#endif - -#ifdef __cplusplus -} -#endif /* __cplusplus */ -#endif /* _GARUDA_LEAKY_H_ */ -/** - * @} - */ diff --git a/feeds/ipq807x/qca-ssdk/src/include/hsl/garuda/garuda_led.h b/feeds/ipq807x/qca-ssdk/src/include/hsl/garuda/garuda_led.h deleted file mode 100755 index 16340bf96..000000000 --- a/feeds/ipq807x/qca-ssdk/src/include/hsl/garuda/garuda_led.h +++ /dev/null @@ -1,57 +0,0 @@ -/* - * Copyright (c) 2012, The Linux Foundation. All rights reserved. - * Permission to use, copy, modify, and/or distribute this software for - * any purpose with or without fee is hereby granted, provided that the - * above copyright notice and this permission notice appear in all copies. - * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES - * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR - * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES - * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN - * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT - * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. - */ - - -#ifndef _GARUDA_LED_H_ -#define _GARUDA_LED_H_ - -#ifdef __cplusplus -extern "C" { -#endif /* __cplusplus */ - -#include "fal/fal_led.h" - - sw_error_t - garuda_led_init(a_uint32_t dev_id); - -#ifdef IN_LED -#define GARUDA_LED_INIT(rv, dev_id) \ - { \ - rv = garuda_led_init(dev_id); \ - SW_RTN_ON_ERROR(rv); \ - } -#else -#define GARUDA_LED_INIT(rv, dev_id) -#endif - -#ifdef HSL_STANDALONG - - - HSL_LOCAL sw_error_t - garuda_led_ctrl_pattern_set(a_uint32_t dev_id, led_pattern_group_t group, - led_pattern_id_t id, led_ctrl_pattern_t * pattern); - - - - HSL_LOCAL sw_error_t - garuda_led_ctrl_pattern_get(a_uint32_t dev_id, led_pattern_group_t group, - led_pattern_id_t id, led_ctrl_pattern_t * pattern); - -#endif - -#ifdef __cplusplus -} -#endif /* __cplusplus */ - -#endif /* _GARUDA_LED_H_ */ diff --git a/feeds/ipq807x/qca-ssdk/src/include/hsl/garuda/garuda_mib.h b/feeds/ipq807x/qca-ssdk/src/include/hsl/garuda/garuda_mib.h deleted file mode 100755 index 3fc578a90..000000000 --- a/feeds/ipq807x/qca-ssdk/src/include/hsl/garuda/garuda_mib.h +++ /dev/null @@ -1,68 +0,0 @@ -/* - * Copyright (c) 2012, The Linux Foundation. All rights reserved. - * Permission to use, copy, modify, and/or distribute this software for - * any purpose with or without fee is hereby granted, provided that the - * above copyright notice and this permission notice appear in all copies. - * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES - * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR - * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES - * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN - * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT - * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. - */ - - -/** - * @defgroup garuda_mib GARUDA_MIB - * @{ - */ -#ifndef _GARUDA_MIB_H_ -#define _GARUDA_MIB_H_ - -#ifdef __cplusplus -extern "C" { -#endif /* __cplusplus */ - -#include "fal/fal_mib.h" - - sw_error_t - garuda_mib_init(a_uint32_t dev_id); - -#ifdef IN_MIB -#define GARUDA_MIB_INIT(rv, dev_id) \ - { \ - rv = garuda_mib_init(dev_id); \ - SW_RTN_ON_ERROR(rv); \ - } -#else -#define GARUDA_MIB_INIT(rv, dev_id) -#endif - -#ifdef HSL_STANDALONG - - - HSL_LOCAL sw_error_t - garuda_get_mib_info(a_uint32_t dev_id, fal_port_t port_id, - fal_mib_info_t * mib_info ); - - - - HSL_LOCAL sw_error_t - garuda_mib_status_set(a_uint32_t dev_id, a_bool_t enable); - - - - HSL_LOCAL sw_error_t - garuda_mib_status_get(a_uint32_t dev_id, a_bool_t * enable); - -#endif - -#ifdef __cplusplus -} -#endif /* __cplusplus */ - -#endif /* _GARUDA_MIB_H_ */ -/** - * @} - */ diff --git a/feeds/ipq807x/qca-ssdk/src/include/hsl/garuda/garuda_mirror.h b/feeds/ipq807x/qca-ssdk/src/include/hsl/garuda/garuda_mirror.h deleted file mode 100755 index 00f390165..000000000 --- a/feeds/ipq807x/qca-ssdk/src/include/hsl/garuda/garuda_mirror.h +++ /dev/null @@ -1,84 +0,0 @@ -/* - * Copyright (c) 2012, The Linux Foundation. All rights reserved. - * Permission to use, copy, modify, and/or distribute this software for - * any purpose with or without fee is hereby granted, provided that the - * above copyright notice and this permission notice appear in all copies. - * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES - * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR - * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES - * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN - * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT - * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. - */ - - -/** - * @defgroup garuda_mirror GARUDA_MIRROR - * @{ - */ -#ifndef _GARUDA_MIRROR_H_ -#define _GARUDA_MIRROR_H_ - -#ifdef __cplusplus -extern "C" { -#endif /* __cplusplus */ - -#include "fal/fal_mirror.h" - - sw_error_t garuda_mirr_init(a_uint32_t dev_id); - -#ifdef IN_MIRROR -#define GARUDA_MIRR_INIT(rv, dev_id) \ - { \ - rv = garuda_mirr_init(dev_id); \ - SW_RTN_ON_ERROR(rv); \ - } -#else -#define GARUDA_MIRR_INIT(rv, dev_id) -#endif - -#ifdef HSL_STANDALONG - - - HSL_LOCAL sw_error_t - garuda_mirr_analysis_port_set(a_uint32_t dev_id, fal_port_t port_id); - - - - HSL_LOCAL sw_error_t - garuda_mirr_analysis_port_get(a_uint32_t dev_id, fal_port_t * port_id); - - - - HSL_LOCAL sw_error_t - garuda_mirr_port_in_set(a_uint32_t dev_id, fal_port_t port_id, - a_bool_t enable); - - - - HSL_LOCAL sw_error_t - garuda_mirr_port_in_get(a_uint32_t dev_id, fal_port_t port_id, - a_bool_t * enable); - - - - HSL_LOCAL sw_error_t - garuda_mirr_port_eg_set(a_uint32_t dev_id, fal_port_t port_id, - a_bool_t enable); - - - - HSL_LOCAL sw_error_t - garuda_mirr_port_eg_get(a_uint32_t dev_id, fal_port_t port_id, - a_bool_t * enable); - -#endif - -#ifdef __cplusplus -} -#endif /* __cplusplus */ -#endif /* _GARUDA_MIRROR_H_ */ -/** - * @} - */ diff --git a/feeds/ipq807x/qca-ssdk/src/include/hsl/garuda/garuda_misc.h b/feeds/ipq807x/qca-ssdk/src/include/hsl/garuda/garuda_misc.h deleted file mode 100755 index 26ee61936..000000000 --- a/feeds/ipq807x/qca-ssdk/src/include/hsl/garuda/garuda_misc.h +++ /dev/null @@ -1,147 +0,0 @@ -/* - * Copyright (c) 2012, The Linux Foundation. All rights reserved. - * Permission to use, copy, modify, and/or distribute this software for - * any purpose with or without fee is hereby granted, provided that the - * above copyright notice and this permission notice appear in all copies. - * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES - * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR - * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES - * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN - * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT - * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. - */ - - - -#ifndef _GARUDA_MISC_H_ -#define _GARUDA_MISC_H_ - -#ifdef __cplusplus -extern "C" { -#endif /* __cplusplus */ - -#include "fal/fal_misc.h" - - sw_error_t garuda_misc_init(a_uint32_t dev_id); - -#ifdef IN_MISC -#define GARUDA_MISC_INIT(rv, dev_id) \ - { \ - rv = garuda_misc_init(dev_id); \ - SW_RTN_ON_ERROR(rv); \ - } -#else -#define GARUDA_MISC_INIT(rv, dev_id) -#endif - -#ifdef HSL_STANDALONG - - - HSL_LOCAL sw_error_t - garuda_arp_status_set(a_uint32_t dev_id, a_bool_t enable); - - - - HSL_LOCAL sw_error_t - garuda_arp_status_get(a_uint32_t dev_id, a_bool_t * enable); - - - - HSL_LOCAL sw_error_t - garuda_frame_max_size_set(a_uint32_t dev_id, a_uint32_t size); - - - - HSL_LOCAL sw_error_t - garuda_frame_max_size_get(a_uint32_t dev_id, a_uint32_t * size); - - - - HSL_LOCAL sw_error_t - garuda_port_unk_sa_cmd_set(a_uint32_t dev_id, fal_port_t port_id, - fal_fwd_cmd_t cmd); - - - - HSL_LOCAL sw_error_t - garuda_port_unk_sa_cmd_get(a_uint32_t dev_id, fal_port_t port_id, - fal_fwd_cmd_t * cmd); - - - - HSL_LOCAL sw_error_t - garuda_port_unk_uc_filter_set(a_uint32_t dev_id, fal_port_t port_id, - a_bool_t enable); - - - - HSL_LOCAL sw_error_t - garuda_port_unk_uc_filter_get(a_uint32_t dev_id, fal_port_t port_id, - a_bool_t * enable); - - - - HSL_LOCAL sw_error_t - garuda_port_unk_mc_filter_set(a_uint32_t dev_id, fal_port_t port_id, - a_bool_t enable); - - - - HSL_LOCAL sw_error_t - garuda_port_unk_mc_filter_get(a_uint32_t dev_id, fal_port_t port_id, - a_bool_t * enable); - - - - HSL_LOCAL sw_error_t - garuda_cpu_port_status_set(a_uint32_t dev_id, a_bool_t enable); - - - - HSL_LOCAL sw_error_t - garuda_cpu_port_status_get(a_uint32_t dev_id, a_bool_t * enable); - - - - HSL_LOCAL sw_error_t - garuda_bc_to_cpu_port_set(a_uint32_t dev_id, a_bool_t enable); - - - - HSL_LOCAL sw_error_t - garuda_bc_to_cpu_port_get(a_uint32_t dev_id, a_bool_t * enable); - - - - HSL_LOCAL sw_error_t - garuda_pppoe_cmd_set(a_uint32_t dev_id, fal_fwd_cmd_t cmd); - - - - HSL_LOCAL sw_error_t - garuda_pppoe_cmd_get(a_uint32_t dev_id, fal_fwd_cmd_t * cmd); - - - HSL_LOCAL sw_error_t - garuda_pppoe_status_set(a_uint32_t dev_id, a_bool_t enable); - - - - HSL_LOCAL sw_error_t - garuda_pppoe_status_get(a_uint32_t dev_id, a_bool_t * enable); - - - HSL_LOCAL sw_error_t - garuda_port_dhcp_set(a_uint32_t dev_id, fal_port_t port_id, a_bool_t enable); - - - - HSL_LOCAL sw_error_t - garuda_port_dhcp_get(a_uint32_t dev_id, fal_port_t port_id, a_bool_t * enable); -#endif - -#ifdef __cplusplus -} -#endif /* __cplusplus */ -#endif /* _GARUDA_MISC_H_ */ diff --git a/feeds/ipq807x/qca-ssdk/src/include/hsl/garuda/garuda_port_ctrl.h b/feeds/ipq807x/qca-ssdk/src/include/hsl/garuda/garuda_port_ctrl.h deleted file mode 100755 index ebfec946e..000000000 --- a/feeds/ipq807x/qca-ssdk/src/include/hsl/garuda/garuda_port_ctrl.h +++ /dev/null @@ -1,145 +0,0 @@ -/* - * Copyright (c) 2012, The Linux Foundation. All rights reserved. - * Permission to use, copy, modify, and/or distribute this software for - * any purpose with or without fee is hereby granted, provided that the - * above copyright notice and this permission notice appear in all copies. - * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES - * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR - * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES - * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN - * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT - * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. - */ - - -/** - * @defgroup garuda_port_ctrl GARUDA_PORT_CONTROL - * @{ - */ -#ifndef _GARUDA_PORT_CTRL_H_ -#define _GARUDA_PORT_CTRL_H_ - -#ifdef __cplusplus -extern "C" { -#endif /* __cplusplus */ - -#include "fal/fal_port_ctrl.h" - - sw_error_t garuda_port_ctrl_init(a_uint32_t dev_id); - -#ifdef IN_PORTCONTROL -#define GARUDA_PORT_CTRL_INIT(rv, dev_id) \ - { \ - rv = garuda_port_ctrl_init(dev_id); \ - SW_RTN_ON_ERROR(rv); \ - } -#else -#define GARUDA_PORT_CTRL_INIT(rv, dev_id) -#endif - -#ifdef HSL_STANDALONG - - - HSL_LOCAL sw_error_t - garuda_port_duplex_set(a_uint32_t dev_id, fal_port_t port_id, - fal_port_duplex_t duplex); - - - HSL_LOCAL sw_error_t - garuda_port_duplex_get(a_uint32_t dev_id, fal_port_t port_id, - fal_port_duplex_t * pduplex); - - - HSL_LOCAL sw_error_t - garuda_port_speed_set(a_uint32_t dev_id, fal_port_t port_id, - fal_port_speed_t speed); - - - HSL_LOCAL sw_error_t - garuda_port_speed_get(a_uint32_t dev_id, fal_port_t port_id, - fal_port_speed_t * pspeed); - - - HSL_LOCAL sw_error_t - garuda_port_autoneg_status_get(a_uint32_t dev_id, fal_port_t port_id, - a_bool_t * status); - - - HSL_LOCAL sw_error_t - garuda_port_autoneg_enable(a_uint32_t dev_id, fal_port_t port_id); - - - HSL_LOCAL sw_error_t - garuda_port_autoneg_restart(a_uint32_t dev_id, fal_port_t port_id); - - HSL_LOCAL sw_error_t - garuda_port_autoneg_adv_set(a_uint32_t dev_id, fal_port_t port_id, - a_uint32_t autoadv); - - - HSL_LOCAL sw_error_t - garuda_port_autoneg_adv_get(a_uint32_t dev_id, fal_port_t port_id, - a_uint32_t * autoadv); - - - HSL_LOCAL sw_error_t - garuda_port_hdr_status_set(a_uint32_t dev_id, fal_port_t port_id, - a_bool_t enable); - - - HSL_LOCAL sw_error_t - garuda_port_hdr_status_get(a_uint32_t dev_id, fal_port_t port_id, - a_bool_t * enable); - - - HSL_LOCAL sw_error_t - garuda_port_flowctrl_set(a_uint32_t dev_id, fal_port_t port_id, - a_bool_t enable); - - - HSL_LOCAL sw_error_t - garuda_port_flowctrl_get(a_uint32_t dev_id, fal_port_t port_id, - a_bool_t * enable); - - - HSL_LOCAL sw_error_t - garuda_port_flowctrl_forcemode_set(a_uint32_t dev_id, - fal_port_t port_id, a_bool_t enable); - - - HSL_LOCAL sw_error_t - garuda_port_flowctrl_forcemode_get(a_uint32_t dev_id, - fal_port_t port_id, - a_bool_t * enable); - - HSL_LOCAL sw_error_t - garuda_port_powersave_set(a_uint32_t dev_id, fal_port_t port_id, a_bool_t enable); - - - HSL_LOCAL sw_error_t - garuda_port_powersave_get(a_uint32_t dev_id, fal_port_t port_id, a_bool_t *enable); - - - HSL_LOCAL sw_error_t - garuda_port_hibernate_set(a_uint32_t dev_id, fal_port_t port_id, a_bool_t enable); - - - HSL_LOCAL sw_error_t - garuda_port_hibernate_get(a_uint32_t dev_id, fal_port_t port_id, a_bool_t *enable); - - - HSL_LOCAL sw_error_t - garuda_port_cdt(a_uint32_t dev_id, fal_port_t port_id, a_uint32_t mdi_pair, - fal_cable_status_t *cable_status, a_uint32_t *cable_len); - - -#endif - -#ifdef __cplusplus -} -#endif /* __cplusplus */ -#endif /* _GARUDA_PORT_CTRL_H_ */ -/** - * @} - */ diff --git a/feeds/ipq807x/qca-ssdk/src/include/hsl/garuda/garuda_portvlan.h b/feeds/ipq807x/qca-ssdk/src/include/hsl/garuda/garuda_portvlan.h deleted file mode 100755 index 9fa278b3c..000000000 --- a/feeds/ipq807x/qca-ssdk/src/include/hsl/garuda/garuda_portvlan.h +++ /dev/null @@ -1,151 +0,0 @@ -/* - * Copyright (c) 2012, The Linux Foundation. All rights reserved. - * Permission to use, copy, modify, and/or distribute this software for - * any purpose with or without fee is hereby granted, provided that the - * above copyright notice and this permission notice appear in all copies. - * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES - * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR - * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES - * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN - * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT - * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. - */ - - - -/** - * @defgroup garuda_port_vlan GARUDA_PORT_VLAN - * @{ - */ -#ifndef _GARUDA_PORTVLAN_H_ -#define _GARUDA_PORTVLAN_H_ - -#ifdef __cplusplus -extern "C" { -#endif /* __cplusplus */ - -#include "fal/fal_portvlan.h" - - sw_error_t garuda_portvlan_init(a_uint32_t dev_id); - -#ifdef IN_PORTVLAN -#define GARUDA_PORTVLAN_INIT(rv, dev_id) \ - { \ - rv = garuda_portvlan_init(dev_id); \ - SW_RTN_ON_ERROR(rv); \ - } -#else -#define GARUDA_PORTVLAN_INIT(rv, dev_id) -#endif - -#ifdef HSL_STANDALONG - - - HSL_LOCAL sw_error_t - garuda_port_1qmode_set(a_uint32_t dev_id, fal_port_t port_id, - fal_pt_1qmode_t port_1qmode); - - - - HSL_LOCAL sw_error_t - garuda_port_1qmode_get(a_uint32_t dev_id, fal_port_t port_id, - fal_pt_1qmode_t * pport_1qmode); - - - - HSL_LOCAL sw_error_t - garuda_port_egvlanmode_set(a_uint32_t dev_id, fal_port_t port_id, - fal_pt_1q_egmode_t port_egvlanmode); - - - - HSL_LOCAL sw_error_t - garuda_port_egvlanmode_get(a_uint32_t dev_id, fal_port_t port_id, - fal_pt_1q_egmode_t * pport_egvlanmode); - - - - HSL_LOCAL sw_error_t - garuda_portvlan_member_add(a_uint32_t dev_id, fal_port_t port_id, - a_uint32_t mem_port_id); - - - - HSL_LOCAL sw_error_t - garuda_portvlan_member_del(a_uint32_t dev_id, fal_port_t port_id, - a_uint32_t mem_port_id); - - - - HSL_LOCAL sw_error_t - garuda_portvlan_member_update(a_uint32_t dev_id, fal_port_t port_id, - fal_pbmp_t mem_port_map); - - - - HSL_LOCAL sw_error_t - garuda_portvlan_member_get(a_uint32_t dev_id, fal_port_t port_id, - fal_pbmp_t * mem_port_map); - - - - HSL_LOCAL sw_error_t - garuda_port_default_vid_set(a_uint32_t dev_id, fal_port_t port_id, - a_uint32_t vid); - - - - HSL_LOCAL sw_error_t - garuda_port_default_vid_get(a_uint32_t dev_id, fal_port_t port_id, - a_uint32_t * vid); - - - - HSL_LOCAL sw_error_t - garuda_port_force_default_vid_set(a_uint32_t dev_id, fal_port_t port_id, - a_bool_t enable); - - - - HSL_LOCAL sw_error_t - garuda_port_force_default_vid_get(a_uint32_t dev_id, fal_port_t port_id, a_bool_t * enable); - - - - HSL_LOCAL sw_error_t - garuda_port_force_portvlan_set(a_uint32_t dev_id, fal_port_t port_id, - a_bool_t enable); - - - HSL_LOCAL sw_error_t - garuda_port_force_portvlan_get(a_uint32_t dev_id, fal_port_t port_id, a_bool_t * enable); - - - - HSL_LOCAL sw_error_t - garuda_port_nestvlan_set(a_uint32_t dev_id, fal_port_t port_id, - a_bool_t enable); - - - - HSL_LOCAL sw_error_t - garuda_port_nestvlan_get(a_uint32_t dev_id, fal_port_t port_id, - a_bool_t * enable); - - HSL_LOCAL sw_error_t - garuda_nestvlan_tpid_set(a_uint32_t dev_id, a_uint32_t tpid); - - - HSL_LOCAL sw_error_t - garuda_nestvlan_tpid_get(a_uint32_t dev_id, a_uint32_t * tpid); - -#endif - -#ifdef __cplusplus -} -#endif /* __cplusplus */ -#endif /* _ATHENA_PORTVLAN_H */ -/** - * @} - */ diff --git a/feeds/ipq807x/qca-ssdk/src/include/hsl/garuda/garuda_qos.h b/feeds/ipq807x/qca-ssdk/src/include/hsl/garuda/garuda_qos.h deleted file mode 100755 index 2b60f50a3..000000000 --- a/feeds/ipq807x/qca-ssdk/src/include/hsl/garuda/garuda_qos.h +++ /dev/null @@ -1,169 +0,0 @@ -/* - * Copyright (c) 2012, The Linux Foundation. All rights reserved. - * Permission to use, copy, modify, and/or distribute this software for - * any purpose with or without fee is hereby granted, provided that the - * above copyright notice and this permission notice appear in all copies. - * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES - * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR - * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES - * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN - * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT - * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. - */ - - -/** - * @defgroup garuda_qos GARUDA_QOS - * @{ - */ -#ifndef _GARUDA_QOS_H_ -#define _GARUDA_QOS_H_ - -#ifdef __cplusplus -extern "C" { -#endif /* __cplusplus */ - -#include "fal/fal_qos.h" - - sw_error_t garuda_qos_init(a_uint32_t dev_id); - -#ifdef IN_QOS -#define GARUDA_QOS_INIT(rv, dev_id) \ - { \ - rv = garuda_qos_init(dev_id); \ - SW_RTN_ON_ERROR(rv); \ - } -#else -#define GARUDA_QOS_INIT(rv, dev_id) -#endif - -#ifdef HSL_STANDALONG - - - HSL_LOCAL sw_error_t - garuda_qos_sch_mode_set(a_uint32_t dev_id, - fal_sch_mode_t mode, const a_uint32_t weight[]); - - - - HSL_LOCAL sw_error_t - garuda_qos_sch_mode_get(a_uint32_t dev_id, - fal_sch_mode_t * mode, a_uint32_t weight[]); - - - - HSL_LOCAL sw_error_t - garuda_qos_queue_tx_buf_status_set(a_uint32_t dev_id, - fal_port_t port_id, a_bool_t enable); - - - - HSL_LOCAL sw_error_t - garuda_qos_queue_tx_buf_status_get(a_uint32_t dev_id, - fal_port_t port_id, - a_bool_t * enable); - - - HSL_LOCAL sw_error_t - garuda_qos_port_tx_buf_status_set(a_uint32_t dev_id, fal_port_t port_id, - a_bool_t enable); - - - - HSL_LOCAL sw_error_t - garuda_qos_port_tx_buf_status_get(a_uint32_t dev_id, fal_port_t port_id, - a_bool_t * enable); - - - - HSL_LOCAL sw_error_t - garuda_qos_queue_tx_buf_nr_set(a_uint32_t dev_id, fal_port_t port_id, - fal_queue_t queue_id, - a_uint32_t * number); - - - - HSL_LOCAL sw_error_t - garuda_qos_queue_tx_buf_nr_get(a_uint32_t dev_id, fal_port_t port_id, - fal_queue_t queue_id, - a_uint32_t * number); - - - - HSL_LOCAL sw_error_t - garuda_qos_port_tx_buf_nr_set(a_uint32_t dev_id, fal_port_t port_id, - a_uint32_t * number); - - - - HSL_LOCAL sw_error_t - garuda_qos_port_tx_buf_nr_get(a_uint32_t dev_id, fal_port_t port_id, - a_uint32_t * number); - - - - HSL_LOCAL sw_error_t - garuda_cosmap_up_queue_set(a_uint32_t dev_id, a_uint32_t up, - fal_queue_t queue); - - - HSL_LOCAL sw_error_t - garuda_cosmap_up_queue_get(a_uint32_t dev_id, a_uint32_t up, - fal_queue_t * queue); - - - - HSL_LOCAL sw_error_t - garuda_cosmap_dscp_queue_set(a_uint32_t dev_id, a_uint32_t dscp, - fal_queue_t queue); - - - - HSL_LOCAL sw_error_t - garuda_cosmap_dscp_queue_get(a_uint32_t dev_id, a_uint32_t dscp, - fal_queue_t * queue); - - - - HSL_LOCAL sw_error_t - garuda_qos_port_mode_set(a_uint32_t dev_id, fal_port_t port_id, - fal_qos_mode_t mode, a_bool_t enable); - - - - HSL_LOCAL sw_error_t - garuda_qos_port_mode_get(a_uint32_t dev_id, fal_port_t port_id, - fal_qos_mode_t mode, a_bool_t * enable); - - - - HSL_LOCAL sw_error_t - garuda_qos_port_mode_pri_set(a_uint32_t dev_id, fal_port_t port_id, - fal_qos_mode_t mode, a_uint32_t pri); - - - HSL_LOCAL sw_error_t - garuda_qos_port_mode_pri_get(a_uint32_t dev_id, fal_port_t port_id, - fal_qos_mode_t mode, a_uint32_t * pri); - - - - HSL_LOCAL sw_error_t - garuda_qos_port_default_up_set(a_uint32_t dev_id, fal_port_t port_id, - a_uint32_t up); - - - - HSL_LOCAL sw_error_t - garuda_qos_port_default_up_get(a_uint32_t dev_id, fal_port_t port_id, - a_uint32_t * up); -#endif - -#ifdef __cplusplus -} -#endif /* __cplusplus */ -#endif /* _GARUDA_QOS_H_ */ -/** - * @} - */ diff --git a/feeds/ipq807x/qca-ssdk/src/include/hsl/garuda/garuda_rate.h b/feeds/ipq807x/qca-ssdk/src/include/hsl/garuda/garuda_rate.h deleted file mode 100755 index eb76efa50..000000000 --- a/feeds/ipq807x/qca-ssdk/src/include/hsl/garuda/garuda_rate.h +++ /dev/null @@ -1,111 +0,0 @@ -/* - * Copyright (c) 2012, The Linux Foundation. All rights reserved. - * Permission to use, copy, modify, and/or distribute this software for - * any purpose with or without fee is hereby granted, provided that the - * above copyright notice and this permission notice appear in all copies. - * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES - * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR - * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES - * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN - * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT - * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. - */ - - -/** - * @defgroup garuda_rate GARUDA_RATE - * @{ - */ -#ifndef _GARUDA_RATE_H_ -#define _GARUDA_RATE_H_ - -#ifdef __cplusplus -extern "C" { -#endif /* __cplusplus */ - -#include "fal/fal_rate.h" - - sw_error_t garuda_rate_init(a_uint32_t dev_id); - -#ifdef IN_RATE -#define GARUDA_RATE_INIT(rv, dev_id) \ - { \ - rv = garuda_rate_init(dev_id); \ - SW_RTN_ON_ERROR(rv); \ - } -#else -#define GARUDA_RATE_INIT(rv, dev_id) -#endif - -#ifdef HSL_STANDALONG - - - HSL_LOCAL sw_error_t - garuda_rate_queue_egrl_set(a_uint32_t dev_id, fal_port_t port_id, - fal_queue_t queue_id, a_uint32_t * speed, - a_bool_t enable); - - - - HSL_LOCAL sw_error_t - garuda_rate_queue_egrl_get(a_uint32_t dev_id, fal_port_t port_id, - fal_queue_t queue_id, a_uint32_t * speed, - a_bool_t * enable); - - - - HSL_LOCAL sw_error_t - garuda_rate_port_egrl_set(a_uint32_t dev_id, fal_port_t port_id, - a_uint32_t * speed, a_bool_t enable); - - - - HSL_LOCAL sw_error_t - garuda_rate_port_egrl_get(a_uint32_t dev_id, fal_port_t port_id, - a_uint32_t * speed, a_bool_t * enable); - - - - HSL_LOCAL sw_error_t - garuda_rate_port_inrl_set(a_uint32_t dev_id, fal_port_t port_id, - a_uint32_t * speed, a_bool_t enable); - - - - HSL_LOCAL sw_error_t - garuda_rate_port_inrl_get(a_uint32_t dev_id, fal_port_t port_id, - a_uint32_t * speed, a_bool_t * enable); - - - - HSL_LOCAL sw_error_t - garuda_storm_ctrl_frame_set(a_uint32_t dev_id, fal_port_t port_id, - fal_storm_type_t storm_type, a_bool_t enable); - - - - HSL_LOCAL sw_error_t - garuda_storm_ctrl_frame_get(a_uint32_t dev_id, fal_port_t port_id, - fal_storm_type_t storm_type, a_bool_t * enable); - - - - HSL_LOCAL sw_error_t - garuda_storm_ctrl_rate_set(a_uint32_t dev_id, fal_port_t port_id, - a_uint32_t * rate_in_pps); - - - - HSL_LOCAL sw_error_t - garuda_storm_ctrl_rate_get(a_uint32_t dev_id, fal_port_t port_id, - a_uint32_t * rate_in_pps); -#endif - -#ifdef __cplusplus -} -#endif /* __cplusplus */ -#endif /* _GARUDA_RATE_H_ */ -/** - * @} - */ diff --git a/feeds/ipq807x/qca-ssdk/src/include/hsl/garuda/garuda_reduced_acl.h b/feeds/ipq807x/qca-ssdk/src/include/hsl/garuda/garuda_reduced_acl.h deleted file mode 100755 index 08be79484..000000000 --- a/feeds/ipq807x/qca-ssdk/src/include/hsl/garuda/garuda_reduced_acl.h +++ /dev/null @@ -1,54 +0,0 @@ -/* - * Copyright (c) 2012,2018, The Linux Foundation. All rights reserved. - * Permission to use, copy, modify, and/or distribute this software for - * any purpose with or without fee is hereby granted, provided that the - * above copyright notice and this permission notice appear in all copies. - * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES - * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR - * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES - * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN - * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT - * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. - */ - - - -#ifndef _GARUDA_REDUCED_ACL_H_ -#define _GARUDA_REDUCED_ACL_H_ - -#ifdef __cplusplus -extern "C" { -#endif /* __cplusplus */ - -#include "sw.h" - - sw_error_t - garuda_acl_rule_write(a_uint32_t dev_id, a_uint32_t rule_idx, a_uint32_t vlu[8], - a_uint32_t msk[8]); - - sw_error_t - garuda_acl_action_write(a_uint32_t dev_id, a_uint32_t act_idx, - a_uint32_t act); - - sw_error_t - garuda_acl_slct_write(a_uint32_t dev_id, a_uint32_t slct_idx, - a_uint32_t slct[8]); - - sw_error_t - garuda_acl_rule_read(a_uint32_t dev_id, a_uint32_t rule_idx, a_uint32_t vlu[8], - a_uint32_t msk[8]); - - sw_error_t - garuda_acl_action_read(a_uint32_t dev_id, a_uint32_t act_idx, - a_uint32_t * act); - - sw_error_t - garuda_acl_slct_read(a_uint32_t dev_id, a_uint32_t slct_idx, - a_uint32_t slct[8]); - -#ifdef __cplusplus -} -#endif /* __cplusplus */ -#endif /* _GARUDA_REDUCED_ACL_H_ */ - diff --git a/feeds/ipq807x/qca-ssdk/src/include/hsl/garuda/garuda_reg.h b/feeds/ipq807x/qca-ssdk/src/include/hsl/garuda/garuda_reg.h deleted file mode 100755 index 32169706c..000000000 --- a/feeds/ipq807x/qca-ssdk/src/include/hsl/garuda/garuda_reg.h +++ /dev/null @@ -1,3614 +0,0 @@ -/* - * Copyright (c) 2012, The Linux Foundation. All rights reserved. - * Permission to use, copy, modify, and/or distribute this software for - * any purpose with or without fee is hereby granted, provided that the - * above copyright notice and this permission notice appear in all copies. - * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES - * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR - * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES - * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN - * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT - * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. - */ - - - -#ifndef _GARUDA_REG_H_ -#define _GARUDA_REG_H_ - -#ifdef __cplusplus -extern "C" { -#endif /* __cplusplus */ - -#define MAX_ENTRY_LEN 128 - -#define HSL_RW 1 -#define HSL_RO 0 - - - /* GARUDA Mask Control Register */ -#define MASK_CTL "mask" -#define MASK_CTL_ID 0 -#define MASK_CTL_OFFSET 0x0000 -#define MASK_CTL_E_LENGTH 4 -#define MASK_CTL_E_OFFSET 0 -#define MASK_CTL_NR_E 1 - -#define SOFT_RST "mask_rst" -#define MASK_CTL_SOFT_RST_BOFFSET 31 -#define MASK_CTL_SOFT_RST_BLEN 1 -#define MASK_CTL_SOFT_RST_FLAG HSL_RW - -#define MII_CLK5_SEL "mask_clk5s" -#define MASK_CTL_MII_CLK5_SEL_BOFFSET 21 -#define MASK_CTL_MII_CLK5_SEL_BLEN 1 -#define MASK_CTL_MII_CLK5_SEL_FLAG HSL_RW - -#define MII_CLK0_SEL "mask_clk0s" -#define MASK_CTL_MII_CLK0_SEL_BOFFSET 20 -#define MASK_CTL_MII_CLK0_SEL_BLEN 1 -#define MASK_CTL_MII_CLK0_SEL_FLAG HSL_RW - -#define LOAD_EEPROM "mask_ldro" -#define MASK_CTL_LOAD_EEPROM_BOFFSET 16 -#define MASK_CTL_LOAD_EEPROM_BLEN 1 -#define MASK_CTL_LOAD_EEPROM_FLAG HSL_RW - -#define DEVICE_ID "mask_did" -#define MASK_CTL_DEVICE_ID_BOFFSET 8 -#define MASK_CTL_DEVICE_ID_BLEN 8 -#define MASK_CTL_DEVICE_ID_FLAG HSL_RO - -#define REV_ID "mask_rid" -#define MASK_CTL_REV_ID_BOFFSET 0 -#define MASK_CTL_REV_ID_BLEN 8 -#define MASK_CTL_REV_ID_FLAG HSL_RO - - - /* GARUDA Mask Control Register */ -#define POSTRIP "postrip" -#define POSTRIP_ID 0 -#define POSTRIP_OFFSET 0x0008 -#define POSTRIP_E_LENGTH 4 -#define POSTRIP_E_OFFSET 0 -#define POSTRIP_NR_E 1 - -#define POWER_ON_SEL "postrip_sel" -#define POSTRIP_POWER_ON_SEL_BOFFSET 31 -#define POSTRIP_POWER_ON_SEL_BLEN 1 -#define POSTRIP_POWER_ON_SEL_FLAG HSL_RW - -#define RXDELAY_S1 "postrip_rx_s1" -#define POSTRIP_RXDELAY_S1_BOFFSET 26 -#define POSTRIP_RXDELAY_S1_BLEN 1 -#define POSTRIP_RXDELAY_S1_FLAG HSL_RW - -#define SPI_EN "postrip_spi" -#define POSTRIP_SPI_EN_BOFFSET 25 -#define POSTRIP_SPI_EN_BLEN 1 -#define POSTRIP_SPI_EN_FLAG HSL_RW - -#define LED_OPEN_EN "postrip_led" -#define POSTRIP_LED_OPEN_EN_BOFFSET 24 -#define POSTRIP_LED_OPEN_EN_BLEN 1 -#define POSTRIP_LED_OPEN_EN_FLAG HSL_RW - -#define RXDELAY_S0 "postrip_rx_s0" -#define POSTRIP_RXDELAY_S0_BOFFSET 23 -#define POSTRIP_RXDELAY_S0_BLEN 1 -#define POSTRIP_RXDELAY_S0_FLAG HSL_RW - -#define TXDELAY_S1 "postrip_tx_s1" -#define POSTRIP_TXDELAY_S1_BOFFSET 22 -#define POSTRIP_TXDELAY_S1_BLEN 1 -#define POSTRIP_TXDELAY_S1_FLAG HSL_RW - -#define TXDELAY_S0 "postrip_tx_s0" -#define POSTRIP_TXDELAY_S0_BOFFSET 21 -#define POSTRIP_TXDELAY_S0_BLEN 1 -#define POSTRIP_TXDELAY_S0_FLAG HSL_RW - -#define LPW_EXIT "postrip_lpw_exit" -#define POSTRIP_LPW_EXIT_BOFFSET 20 -#define POSTRIP_LPW_EXIT_BLEN 1 -#define POSTRIP_LPW_EXIT_FLAG HSL_RW - -#define PHY_PLL_ON "postrip_phy_pll" -#define POSTRIP_PHY_PLL_ON_BOFFSET 19 -#define POSTRIP_PHY_PLL_ON_BLEN 1 -#define POSTRIP_PHY_PLL_ON_FLAG HSL_RW - -#define MAN_ENABLE "postrip_man_en" -#define POSTRIP_MAN_ENABLE_BOFFSET 18 -#define POSTRIP_MAN_ENABLE_BLEN 1 -#define POSTRIP_MAN_ENABLE_FLAG HSL_RW - -#define LPW_STATE_EN "postrip_lpw_state" -#define POSTRIP_LPW_STATE_EN_BOFFSET 17 -#define POSTRIP_LPW_STATE_EN_BLEN 1 -#define POSTRIP_LPW_STATE_EN_FLAG HSL_RW - -#define POWER_DOWN_HW "postrip_power_down" -#define POSTRIP_POWER_DOWN_HW_BOFFSET 16 -#define POSTRIP_POWER_DOWN_HW_BLEN 1 -#define POSTRIP_POWER_DOWN_HW_FLAG HSL_RW - -#define MAC5_PHY_MODE "postrip_mac5_phy" -#define POSTRIP_MAC5_PHY_MODE_BOFFSET 15 -#define POSTRIP_MAC5_PHY_MODE_BLEN 1 -#define POSTRIP_MAC5_PHY_MODE_FLAG HSL_RW - -#define MAC5_MAC_MODE "postrip_mac5_mac" -#define POSTRIP_MAC5_MAC_MODE_BOFFSET 14 -#define POSTRIP_MAC5_MAC_MODE_BLEN 1 -#define POSTRIP_MAC5_MAC_MODE_FLAG HSL_RW - -#define DBG_MODE_I "postrip_dbg" -#define POSTRIP_DBG_MODE_I_BOFFSET 13 -#define POSTRIP_DBG_MODE_I_BLEN 1 -#define POSTRIP_DBG_MODE_I_FLAG HSL_RW - -#define HIB_PULSE_HW "postrip_hib" -#define POSTRIP_HIB_PULSE_HW_BOFFSET 12 -#define POSTRIP_HIB_PULSE_HW_BLEN 1 -#define POSTRIP_HIB_PULSE_HW_FLAG HSL_RW - -#define SEL_CLK25M "postrip_clk25" -#define POSTRIP_SEL_CLK25M_BOFFSET 11 -#define POSTRIP_SEL_CLK25M_BLEN 1 -#define POSTRIP_SEL_CLK25M_FLAG HSL_RW - -#define GATE_25M_EN "postrip_gate25" -#define POSTRIP_GATE_25M_EN_BOFFSET 10 -#define POSTRIP_GATE_25M_EN_BLEN 1 -#define POSTRIP_GATE_25M_EN_FLAG HSL_RW - -#define SEL_ANA_RST "postrip_sel_ana" -#define POSTRIP_SEL_ANA_RST_BOFFSET 9 -#define POSTRIP_SEL_ANA_RST_BLEN 1 -#define POSTRIP_SEL_ANA_RST_FLAG HSL_RW - -#define SERDES_EN "postrip_serdes_en" -#define POSTRIP_SERDES_EN_BOFFSET 8 -#define POSTRIP_SERDES_EN_BLEN 1 -#define POSTRIP_SERDES_EN_FLAG HSL_RW - -#define RGMII_TXCLK_DELAY_EN "postrip_tx_delay" -#define POSTRIP_RGMII_TXCLK_DELAY_EN_BOFFSET 7 -#define POSTRIP_RGMII_TXCLK_DELAY_EN_BLEN 1 -#define POSTRIP_RGMII_TXCLK_DELAY_EN_FLAG HSL_RW - -#define RGMII_RXCLK_DELAY_EN "postrip_rx_delay" -#define POSTRIP_RGMII_RXCLK_DELAY_EN_BOFFSET 6 -#define POSTRIP_RGMII_RXCLK_DELAY_EN_BLEN 1 -#define POSTRIP_RGMII_RXCLK_DELAY_EN_FLAG HSL_RW - -#define RTL_MODE "postrip_rtl" -#define POSTRIP_RTL_MODE_BOFFSET 5 -#define POSTRIP_RTL_MODE_BLEN 1 -#define POSTRIP_RTL_MODE_FLAG HSL_RW - -#define MAC0_MAC_MODE "postrip_mac0_mac" -#define POSTRIP_MAC0_MAC_MODE_BOFFSET 4 -#define POSTRIP_MAC0_MAC_MODE_BLEN 1 -#define POSTRIP_MAC0_MAC_MODE_FLAG HSL_RW - -#define PHY4_RGMII_EN "postrip_phy4_rgmii" -#define POSTRIP_PHY4_RGMII_EN_BOFFSET 3 -#define POSTRIP_PHY4_RGMII_EN_BLEN 1 -#define POSTRIP_PHY4_RGMII_EN_FLAG HSL_RW - -#define PHY4_GMII_EN "postrip_phy4_gmii" -#define POSTRIP_PHY4_GMII_EN_BOFFSET 2 -#define POSTRIP_PHY4_GMII_EN_BLEN 1 -#define POSTRIP_PHY4_GMII_EN_FLAG HSL_RW - -#define MAC0_RGMII_EN "postrip_mac0_rgmii" -#define POSTRIP_MAC0_RGMII_EN_BOFFSET 1 -#define POSTRIP_MAC0_RGMII_EN_BLEN 1 -#define POSTRIP_MAC0_RGMII_EN_FLAG HSL_RW - -#define MAC0_GMII_EN "postrip_mac0_gmii" -#define POSTRIP_MAC0_GMII_EN_BOFFSET 0 -#define POSTRIP_MAC0_GMII_EN_BLEN 1 -#define POSTRIP_MAC0_GMII_EN_FLAG HSL_RW - - - - /* Global Interrupt Register */ -#define GLOBAL_INT "gint" -#define GLOBAL_INT_ID 1 -#define GLOBAL_INT_OFFSET 0x0010 -#define GLOBAL_INT_E_LENGTH 4 -#define GLOBAL_INT_E_OFFSET 0 -#define GLOBAL_INT_NR_E 1 - -#define GLB_QM_ERR_CNT "gint_qmen" -#define GLOBAL_INT_GLB_QM_ERR_CNT_BOFFSET 24 -#define GLOBAL_INT_GLB_QM_ERR_CNT_BLEN 8 -#define GLOBAL_INT_GLB_QM_ERR_CNT_FLAG HSL_RO - -#define GLB_LOOKUP_ERR "gint_glblper" -#define GLOBAL_INT_GLB_LOOKUP_ERR_BOFFSET 17 -#define GLOBAL_INT_GLB_LOOKUP_ERR_BLEN 1 -#define GLOBAL_INT_GLB_LOOKUP_ERR_FLAG HSL_RW - -#define GLB_QM_ERR "gint_glbqmer" -#define GLOBAL_INT_GLB_QM_ERR_BOFFSET 16 -#define GLOBAL_INT_GLB_QM_ERR_BLEN 1 -#define GLOBAL_INT_GLB_QM_ERR_FLAG HSL_RW - -#define GLB_HW_INI_DONE "gint_hwid" -#define GLOBAL_INT_GLB_HW_INI_DONE_BOFFSET 14 -#define GLOBAL_INT_GLB_HW_INI_DONE_BLEN 1 -#define GLOBAL_INT_GLB_HW_INI_DONE_FLAG HSL_RW - -#define GLB_MIB_INI "gint_mibi" -#define GLOBAL_INT_GLB_MIB_INI_BOFFSET 13 -#define GLOBAL_INT_GLB_MIB_INI_BLEN 1 -#define GLOBAL_INT_GLB_MIB_INI_FLAG HSL_RW - -#define GLB_MIB_DONE "gint_mibd" -#define GLOBAL_INT_GLB_MIB_DONE_BOFFSET 12 -#define GLOBAL_INT_GLB_MIB_DONE_BLEN 1 -#define GLOBAL_INT_GLB_MIB_DONE_FLAG HSL_RW - -#define GLB_BIST_DONE "gint_bisd" -#define GLOBAL_INT_GLB_BIST_DONE_BOFFSET 11 -#define GLOBAL_INT_GLB_BIST_DONE_BLEN 1 -#define GLOBAL_INT_GLB_BIST_DONE_FLAG HSL_RW - -#define GLB_VT_MISS_VIO "gint_vtms" -#define GLOBAL_INT_GLB_VT_MISS_VIO_BOFFSET 10 -#define GLOBAL_INT_GLB_VT_MISS_VIO_BLEN 1 -#define GLOBAL_INT_GLB_VT_MISS_VIO_FLAG HSL_RW - -#define GLB_VT_MEM_VIO "gint_vtme" -#define GLOBAL_INT_GLB_VT_MEM_VIO_BOFFSET 9 -#define GLOBAL_INT_GLB_VT_MEM_VIO_BLEN 1 -#define GLOBAL_INT_GLB_VT_MEM_VIO_FLAG HSL_RW - -#define GLB_VT_DONE "gint_vtd" -#define GLOBAL_INT_GLB_VT_DONE_BOFFSET 8 -#define GLOBAL_INT_GLB_VT_DONE_BLEN 1 -#define GLOBAL_INT_GLB_VT_DONE_FLAG HSL_RW - -#define GLB_QM_INI "gint_qmin" -#define GLOBAL_INT_GLB_QM_INI_BOFFSET 7 -#define GLOBAL_INT_GLB_QM_INI_BLEN 1 -#define GLOBAL_INT_GLB_QM_INI_FLAG HSL_RW - -#define GLB_AT_INI "gint_atin" -#define GLOBAL_INT_GLB_AT_INI_BOFFSET 6 -#define GLOBAL_INT_GLB_AT_INI_BLEN 1 -#define GLOBAL_INT_GLB_AT_INI_FLAG HSL_RW - -#define GLB_ARL_FULL "gint_arlf" -#define GLOBAL_INT_GLB_ARL_FULL_BOFFSET 5 -#define GLOBAL_INT_GLB_ARL_FULL_BLEN 1 -#define GLOBAL_INT_GLB_ARL_FULL_FLAG HSL_RW - -#define GLB_ARL_DONE "gint_arld" -#define GLOBAL_INT_GLB_ARL_DONE_BOFFSET 4 -#define GLOBAL_INT_GLB_ARL_DONE_BLEN 1 -#define GLOBAL_INT_GLB_ARL_DONE_FLAG HSL_RW - -#define GLB_MDIO_DONE "gint_mdid" -#define GLOBAL_INT_GLB_MDIO_DONE_BOFFSET 3 -#define GLOBAL_INT_GLB_MDIO_DONE_BLEN 1 -#define GLOBAL_INT_GLB_MDIO_DONE_FLAG HSL_RW - -#define GLB_PHY_INT "gint_phyi" -#define GLOBAL_INT_GLB_PHY_INT_BOFFSET 2 -#define GLOBAL_INT_GLB_PHY_INT_BLEN 1 -#define GLOBAL_INT_GLB_PHY_INT_FLAG HSL_RW - -#define GLB_EEPROM_ERR "gint_epei" -#define GLOBAL_INT_GLB_EEPROM_ERR_BOFFSET 1 -#define GLOBAL_INT_GLB_EEPROM_ERR_BLEN 1 -#define GLOBAL_INT_GLB_EEPROM_ERR_FLAG HSL_RW - -#define GLB_EEPROM_INT "gint_epi" -#define GLOBAL_INT_GLB_EEPROM_INT_BOFFSET 0 -#define GLOBAL_INT_GLB_EEPROM_INT_BLEN 1 -#define GLOBAL_INT_GLB_EEPROM_INT_FLAG HSL_RW - - - /* Global Interrupt Mask Register */ -#define GLOBAL_INT_MASK "gintm" -#define GLOBAL_INT_MASK_ID 2 -#define GLOBAL_INT_MASK_OFFSET 0x0014 -#define GLOBAL_INT_MASK_E_LENGTH 4 -#define GLOBAL_INT_MASK_E_OFFSET 0 -#define GLOBAL_INT_MASK_NR_E 1 - -#define GLBM_LOOKUP_ERR "gintm_lpe" -#define GLOBAL_INT_MASK_GLBM_LOOKUP_ERR_BOFFSET 17 -#define GLOBAL_INT_MASK_GLBM_LOOKUP_ERR_BLEN 1 -#define GLOBAL_INT_MASK_GLBM_LOOKUP_ERR_FLAG HSL_RW - -#define GLBM_QM_ERR "gintm_qme" -#define GLOBAL_INT_MASK_GLBM_QM_ERR_BOFFSET 16 -#define GLOBAL_INT_MASK_GLBM_QM_ERR_BLEN 1 -#define GLOBAL_INT_MASK_GLBM_QM_ERR_FLAG HSL_RW - -#define GLBM_HW_INI_DONE "gintm_hwid" -#define GLOBAL_INT_MASK_GLBM_HW_INI_DONE_BOFFSET 14 -#define GLOBAL_INT_MASK_GLBM_HW_INI_DONE_BLEN 1 -#define GLOBAL_INT_MASK_GLBM_HW_INI_DONE_FLAG HSL_RW - -#define GLBM_MIB_INI "gintm_mibi" -#define GLOBAL_INT_MASK_GLBM_MIB_INI_BOFFSET 13 -#define GLOBAL_INT_MASK_GLBM_MIB_INI_BLEN 1 -#define GLOBAL_INT_MASK_GLBM_MIB_INI_FLAG HSL_RW - -#define GLBM_MIB_DONE "gintm_mibd" -#define GLOBAL_INT_MASK_GLBM_MIB_DONE_BOFFSET 12 -#define GLOBAL_INT_MASK_GLBM_MIB_DONE_BLEN 1 -#define GLOBAL_INT_MASK_GLBM_MIB_DONE_FLAG HSL_RW - -#define GLBM_BIST_DONE "gintm_bisd" -#define GLOBAL_INT_MASK_GLBM_BIST_DONE_BOFFSET 11 -#define GLOBAL_INT_MASK_GLBM_BIST_DONE_BLEN 1 -#define GLOBAL_INT_MASK_GLBM_BIST_DONE_FLAG HSL_RW - -#define GLBM_VT_MISS_VIO "gintm_vtms" -#define GLOBAL_INT_MASK_GLBM_VT_MISS_VIO_BOFFSET 10 -#define GLOBAL_INT_MASK_GLBM_VT_MISS_VIO_BLEN 1 -#define GLOBAL_INT_MASK_GLBM_VT_MISS_VIO_FLAG HSL_RW - -#define GLBM_VT_MEM_VIO "gintm_vtme" -#define GLOBAL_INT_MASK_GLBM_VT_MEM_VIO_BOFFSET 9 -#define GLOBAL_INT_MASK_GLBM_VT_MEM_VIO_BLEN 1 -#define GLOBAL_INT_MASK_GLBM_VT_MEM_VIO_FLAG HSL_RW - -#define GLBM_VT_DONE "gintm_vtd" -#define GLOBAL_INT_MASK_GLBM_VT_DONE_BOFFSET 8 -#define GLOBAL_INT_MASK_GLBM_VT_DONE_BLEN 1 -#define GLOBAL_INT_MASK_GLBM_VT_DONE_FLAG HSL_RW - -#define GLBM_QM_INI "gintm_qmin" -#define GLOBAL_INT_MASK_GLBM_QM_INI_BOFFSET 7 -#define GLOBAL_INT_MASK_GLBM_QM_INI_BLEN 1 -#define GLOBAL_INT_MASK_GLBM_QM_INI_FLAG HSL_RW - -#define GLBM_AT_INI "gintm_atin" -#define GLOBAL_INT_MASK_GLBM_AT_INI_BOFFSET 6 -#define GLOBAL_INT_MASK_GLBM_AT_INI_BLEN 1 -#define GLOBAL_INT_MASK_GLBM_AT_INI_FLAG HSL_RW - -#define GLBM_ARL_FULL "gintm_arlf" -#define GLOBAL_INT_MASK_GLBM_ARL_FULL_BOFFSET 5 -#define GLOBAL_INT_MASK_GLBM_ARL_FULL_BLEN 1 -#define GLOBAL_INT_MASK_GLBM_ARL_FULL_FLAG HSL_RW - -#define GLBM_ARL_DONE "gintm_arld" -#define GLOBAL_INT_MASK_GLBM_ARL_DONE_BOFFSET 4 -#define GLOBAL_INT_MASK_GLBM_ARL_DONE_BLEN 1 -#define GLOBAL_INT_MASK_GLBM_ARL_DONE_FLAG HSL_RW - -#define GLBM_MDIO_DONE "gintm_mdid" -#define GLOBAL_INT_MASK_GLBM_MDIO_DONE_BOFFSET 3 -#define GLOBAL_INT_MASK_GLBM_MDIO_DONE_BLEN 1 -#define GLOBAL_INT_MASK_GLBM_MDIO_DONE_FLAG HSL_RW - -#define GLBM_PHY_INT "gintm_phy" -#define GLOBAL_INT_MASK_GLBM_PHY_INT_BOFFSET 2 -#define GLOBAL_INT_MASK_GLBM_PHY_INT_BLEN 1 -#define GLOBAL_INT_MASK_GLBM_PHY_INT_FLAG HSL_RW - -#define GLBM_EEPROM_ERR "gintm_epe" -#define GLOBAL_INT_MASK_GLBM_EEPROM_ERR_BOFFSET 1 -#define GLOBAL_INT_MASK_GLBM_EEPROM_ERR_BLEN 1 -#define GLOBAL_INT_MASK_GLBM_EEPROM_ERR_FLAG HSL_RW - -#define GLBM_EEPROM_INT "gintm_ep" -#define GLOBAL_INT_MASK_GLBM_EEPROM_INT_BOFFSET 0 -#define GLOBAL_INT_MASK_GLBM_EEPROM_INT_BLEN 1 -#define GLOBAL_INT_MASK_GLBM_EEPROM_INT_FLAG HSL_RW - - - /* Global MAC Address Register */ -#define GLOBAL_MAC_ADDR0 "gmac0" -#define GLOBAL_MAC_ADDR0_ID 3 -#define GLOBAL_MAC_ADDR0_OFFSET 0x0020 -#define GLOBAL_MAC_ADDR0_E_LENGTH 4 -#define GLOBAL_MAC_ADDR0_E_OFFSET 0 -#define GLOBAL_MAC_ADDR0_NR_E 1 - -#define GLB_BYTE4 "gmac_b4" -#define GLOBAL_MAC_ADDR0_GLB_BYTE4_BOFFSET 8 -#define GLOBAL_MAC_ADDR0_GLB_BYTE4_BLEN 8 -#define GLOBAL_MAC_ADDR0_GLB_BYTE4_FLAG HSL_RW - -#define GLB_BYTE5 "gmac_b5" -#define GLOBAL_MAC_ADDR0_GLB_BYTE5_BOFFSET 0 -#define GLOBAL_MAC_ADDR0_GLB_BYTE5_BLEN 8 -#define GLOBAL_MAC_ADDR0_GLB_BYTE5_FLAG HSL_RW - -#define GLOBAL_MAC_ADDR1 "gmac1" -#define GLOBAL_MAC_ADDR1_ID 4 -#define GLOBAL_MAC_ADDR1_OFFSET 0x0024 -#define GLOBAL_MAC_ADDR1_E_LENGTH 4 -#define GLOBAL_MAC_ADDR1_E_OFFSET 0 -#define GLOBAL_MAC_ADDR1_NR_E 1 - -#define GLB_BYTE0 "gmac_b0" -#define GLOBAL_MAC_ADDR1_GLB_BYTE0_BOFFSET 24 -#define GLOBAL_MAC_ADDR1_GLB_BYTE0_BLEN 8 -#define GLOBAL_MAC_ADDR1_GLB_BYTE0_FLAG HSL_RW - -#define GLB_BYTE1 "gmac_b1" -#define GLOBAL_MAC_ADDR1_GLB_BYTE1_BOFFSET 16 -#define GLOBAL_MAC_ADDR1_GLB_BYTE1_BLEN 8 -#define GLOBAL_MAC_ADDR1_GLB_BYTE1_FLAG HSL_RW - -#define GLB_BYTE2 "gmac_b2" -#define GLOBAL_MAC_ADDR1_GLB_BYTE2_BOFFSET 8 -#define GLOBAL_MAC_ADDR1_GLB_BYTE2_BLEN 8 -#define GLOBAL_MAC_ADDR1_GLB_BYTE2_FLAG HSL_RW - -#define GLB_BYTE3 "gmac_b3" -#define GLOBAL_MAC_ADDR1_GLB_BYTE3_BOFFSET 0 -#define GLOBAL_MAC_ADDR1_GLB_BYTE3_BLEN 8 -#define GLOBAL_MAC_ADDR1_GLB_BYTE3_FLAG HSL_RW - - - /* Flood Mask Register */ -#define FLOOD_MASK "fmask" -#define FLOOD_MASK_ID 5 -#define FLOOD_MASK_OFFSET 0x002c -#define FLOOD_MASK_E_LENGTH 4 -#define FLOOD_MASK_E_OFFSET 0 -#define FLOOD_MASK_NR_E 1 - -#define BROAD_TO_CPU "fmask_btocpu" -#define FLOOD_MASK_BROAD_TO_CPU_BOFFSET 26 -#define FLOOD_MASK_BROAD_TO_CPU_BLEN 1 -#define FLOOD_MASK_BROAD_TO_CPU_FLAG HSL_RW - -#define ARL_MUL_LEAKY "fmask_amlky" -#define FLOOD_MASK_ARL_MUL_LEAKY_BOFFSET 25 -#define FLOOD_MASK_ARL_MUL_LEAKY_BLEN 1 -#define FLOOD_MASK_ARL_MUL_LEAKY_FLAG HSL_RW - -#define ARL_UNI_LEAKY "fmask_aulky" -#define FLOOD_MASK_ARL_UNI_LEAKY_BOFFSET 24 -#define FLOOD_MASK_ARL_UNI_LEAKY_BLEN 1 -#define FLOOD_MASK_ARL_UNI_LEAKY_FLAG HSL_RW - -#define MUL_FLOOD_DP "fmask_mfdp" -#define FLOOD_MASK_MUL_FLOOD_DP_BOFFSET 16 -#define FLOOD_MASK_MUL_FLOOD_DP_BLEN 6 -#define FLOOD_MASK_MUL_FLOOD_DP_FLAG HSL_RW - -#define IGMP_DP "fmask_igmpdp" -#define FLOOD_MASK_IGMP_DP_BOFFSET 8 -#define FLOOD_MASK_IGMP_DP_BLEN 6 -#define FLOOD_MASK_IGMP_DP_FLAG HSL_RW - -#define UNI_FLOOD_DP "fmask_ufdp" -#define FLOOD_MASK_UNI_FLOOD_DP_BOFFSET 0 -#define FLOOD_MASK_UNI_FLOOD_DP_BLEN 6 -#define FLOOD_MASK_UNI_FLOOD_DP_FLAG HSL_RW - - - /* Global Control Register */ -#define GLOBAL_CTL "gctl" -#define GLOBAL_CTL_ID 5 -#define GLOBAL_CTL_OFFSET 0x0030 -#define GLOBAL_CTL_E_LENGTH 4 -#define GLOBAL_CTL_E_OFFSET 0 -#define GLOBAL_CTL_NR_E 1 - -#define WEIGHT_PRIORITY "gctl_wpri" -#define GLOBAL_CTL_WEIGHT_PRIORITY_BOFFSET 31 -#define GLOBAL_CTL_WEIGHT_PRIORITY_BLEN 1 -#define GLOBAL_CTL_WEIGHT_PRIORITY_FLAG HSL_RW - -#define RATE_DROP_EN "gctl_rden" -#define GLOBAL_CTL_RATE_DROP_EN_BOFFSET 30 -#define GLOBAL_CTL_RATE_DROP_EN_BLEN 1 -#define GLOBAL_CTL_RATE_DROP_EN_FLAG HSL_RW - -#define QM_PRI_MODE "gctl_qmpm" -#define GLOBAL_CTL_QM_PRI_MODE_BOFFSET 29 -#define GLOBAL_CTL_QM_PRI_MODE_BLEN 1 -#define GLOBAL_CTL_QM_PRI_MODE_FLAG HSL_RW - -#define MIX_PRIORITY "gctl_mpri" -#define GLOBAL_CTL_MIX_PRIORITY_BOFFSET 28 -#define GLOBAL_CTL_MIX_PRIORITY_BLEN 1 -#define GLOBAL_CTL_MIX_PRIORITY_FLAG HSL_RW - -#define RATE_CRE_LIMIT "gctl_rcrl" -#define GLOBAL_CTL_RATE_CRE_LIMIT_BOFFSET 26 -#define GLOBAL_CTL_RATE_CRE_LIMIT_BLEN 2 -#define GLOBAL_CTL_RATE_CRE_LIMIT_FLAG HSL_RW - -#define RATE_TIME_SLOT "gctl_rtms" -#define GLOBAL_CTL_RATE_TIME_SLOT_BOFFSET 24 -#define GLOBAL_CTL_RATE_TIME_SLOT_BLEN 2 -#define GLOBAL_CTL_RATE_TIME_SLOT_FLAG HSL_RW - -#define RELOAD_TIMER "gctl_rdtm" -#define GLOBAL_CTL_RELOAD_TIMER_BOFFSET 20 -#define GLOBAL_CTL_RELOAD_TIMER_BLEN 4 -#define GLOBAL_CTL_RELOAD_TIMER_FLAG HSL_RW - -#define QM_CNT_LOCK "gctl_qmcl" -#define GLOBAL_CTL_QM_CNT_LOCK_BOFFSET 19 -#define GLOBAL_CTL_QM_CNT_LOCK_BLEN 1 -#define GLOBAL_CTL_QM_CNT_LOCK_FLAG HSL_RO - -#define BROAD_DROP_EN "gctl_bden" -#define GLOBAL_CTL_BROAD_DROP_EN_BOFFSET 18 -#define GLOBAL_CTL_BROAD_DROP_EN_BLEN 1 -#define GLOBAL_CTL_BROAD_DROP_EN_FLAG HSL_RW - -#define MAX_FRAME_SIZE "gctl_mfsz" -#define GLOBAL_CTL_MAX_FRAME_SIZE_BOFFSET 0 -#define GLOBAL_CTL_MAX_FRAME_SIZE_BLEN 14 -#define GLOBAL_CTL_MAX_FRAME_SIZE_FLAG HSL_RW - - - /* Flow Control Register */ -#define FLOW_CTL "fctl" -#define FLOW_CTL_ID 6 -#define FLOW_CTL_OFFSET 0x0034 -#define FLOW_CTL_E_LENGTH 4 -#define FLOW_CTL_E_OFFSET 0 -#define FLOW_CTL_NR_E 1 - -#define TEST_PAUSE "fctl_tps" -#define FLOW_CTL_TEST_PAUSE_BOFFSET 31 -#define FLOW_CTL_TEST_PAUSE_BLEN 1 -#define FLOW_CTL_TEST_PAUSE_FLAG HSL_RW - -#define PORT_PAUSE_OFF_THRES "fctl_pofft" -#define FLOW_CTL_PORT_PAUSE_OFF_THRES_BOFFSET 24 -#define FLOW_CTL_PORT_PAUSE_OFF_THRES_BLEN 7 -#define FLOW_CTL_PORT_PAUSE_OFF_THRES_FLAG HSL_RW - -#define PORT_PAUSE_ON_THRES "fctl_pont" -#define FLOW_CTL_PORT_PAUSE_ON_THRES_BOFFSET 16 -#define FLOW_CTL_PORT_PAUSE_ON_THRES_BLEN 7 -#define FLOW_CTL_PORT_PAUSE_ON_THRES_FLAG HSL_RW - -#define GOL_PAUSE_OFF_THRES "fctl_gofft" -#define FLOW_CTL_GOL_PAUSE_OFF_THRES_BOFFSET 8 -#define FLOW_CTL_GOL_PAUSE_OFF_THRES_BLEN 8 -#define FLOW_CTL_GOL_PAUSE_OFF_THRES_FLAG HSL_RW - -#define GOL_PAUSE_ON_THRES "fctl_gont" -#define FLOW_CTL_GOL_PAUSE_ON_THRES_BOFFSET 0 -#define FLOW_CTL_GOL_PAUSE_ON_THRES_BLEN 8 -#define FLOW_CTL_GOL_PAUSE_ON_THRES_FLAG HSL_RW - - - /* QM Control Register */ -#define QM_CTL "qmct" -#define QM_CTL_ID 7 -#define QM_CTL_OFFSET 0x003c -#define QM_CTL_E_LENGTH 4 -#define QM_CTL_E_OFFSET 0 -#define QM_CTL_NR_E 1 - -#define QM_ERR_RST_EN "qmct_qeren" -#define QM_CTL_QM_ERR_RST_EN_BOFFSET 31 -#define QM_CTL_QM_ERR_RST_EN_BLEN 1 -#define QM_CTL_QM_ERR_RST_EN_FLAG HSL_RW - -#define LOOKUP_ERR_RST_EN "qmct_lpesen" -#define QM_CTL_LOOKUP_ERR_RST_EN_BOFFSET 30 -#define QM_CTL_LOOKUP_ERR_RST_EN_BLEN 1 -#define QM_CTL_LOOKUP_ERR_RST_EN_FLAG HSL_RW - -#define IGMP_CREAT_EN "qmct_igmpcrt" -#define QM_CTL_IGMP_CREAT_EN_BOFFSET 22 -#define QM_CTL_IGMP_CREAT_EN_BLEN 1 -#define QM_CTL_IGMP_CREAT_EN_FLAG HSL_RW - -#define ACL_EN "qmct_aclen" -#define QM_CTL_ACL_EN_BOFFSET 21 -#define QM_CTL_ACL_EN_BLEN 1 -#define QM_CTL_ACL_EN_FLAG HSL_RW - -#define PPPOE_RDT_EN "qmct_pppoerdten" -#define QM_CTL_PPPOE_RDT_EN_BOFFSET 20 -#define QM_CTL_PPPOE_RDT_EN_BLEN 1 -#define QM_CTL_PPPOE_RDT_EN_FLAG HSL_RW - -#define IGMP_COPY_EN "qmct_igmpcpy" -#define QM_CTL_IGMP_COPY_EN_BOFFSET 11 -#define QM_CTL_IGMP_COPY_EN_BLEN 1 -#define QM_CTL_IGMP_COPY_EN_FLAG HSL_RW - -#define PPPOE_EN "qmct_pppoeen" -#define QM_CTL_PPPOE_EN_BOFFSET 10 -#define QM_CTL_PPPOE_EN_BLEN 1 -#define QM_CTL_PPPOE_EN_FLAG HSL_RW - -#define QM_FUNC_TEST "qmct_qmft" -#define QM_CTL_QM_FUNC_TEST_BOFFSET 9 -#define QM_CTL_QM_FUNC_TEST_BLEN 1 -#define QM_CTL_QM_FUNC_TEST_FLAG HSL_RW - -#define MS_FC_EN "qmct_msfe" -#define QM_CTL_MS_FC_EN_BOFFSET 8 -#define QM_CTL_MS_FC_EN_BLEN 1 -#define QM_CTL_MS_FC_EN_FLAG HSL_RW - -#define FLOW_DROP_EN "qmct_fden" -#define QM_CTL_FLOW_DROP_EN_BOFFSET 7 -#define QM_CTL_FLOW_DROP_EN_BLEN 1 -#define QM_CTL_FLOW_DROP_EN_FLAG HSL_RW - -#define MANAGE_VID_VIO_DROP_EN "qmct_mden" -#define QM_CTL_MANAGE_VID_VIO_DROP_EN_BOFFSET 6 -#define QM_CTL_MANAGE_VID_VIO_DROP_EN_BLEN 1 -#define QM_CTL_MANAGE_VID_VIO_DROP_EN_FLAG HSL_RW - -#define FLOW_DROP_CNT "qmct_fdcn" -#define QM_CTL_FLOW_DROP_CNT_BOFFSET 0 -#define QM_CTL_FLOW_DROP_CNT_BLEN 6 -#define QM_CTL_FLOW_DROP_CNT_FLAG HSL_RW - - - /* Vlan Table Function Register */ -#define VLAN_TABLE_FUNC0 "vtbf0" -#define VLAN_TABLE_FUNC0_ID 9 -#define VLAN_TABLE_FUNC0_OFFSET 0x0040 -#define VLAN_TABLE_FUNC0_E_LENGTH 4 -#define VLAN_TABLE_FUNC0_E_OFFSET 0 -#define VLAN_TABLE_FUNC0_NR_E 1 - -#define VT_PRI_EN "vtbf_vtpen" -#define VLAN_TABLE_FUNC0_VT_PRI_EN_BOFFSET 31 -#define VLAN_TABLE_FUNC0_VT_PRI_EN_BLEN 1 -#define VLAN_TABLE_FUNC0_VT_PRI_EN_FLAG HSL_RW - -#define VT_PRI "vtbf_vtpri" -#define VLAN_TABLE_FUNC0_VT_PRI_BOFFSET 28 -#define VLAN_TABLE_FUNC0_VT_PRI_BLEN 3 -#define VLAN_TABLE_FUNC0_VT_PRI_FLAG HSL_RW - -#define VLAN_ID "vtbf_vid" -#define VLAN_TABLE_FUNC0_VLAN_ID_BOFFSET 16 -#define VLAN_TABLE_FUNC0_VLAN_ID_BLEN 12 -#define VLAN_TABLE_FUNC0_VLAN_ID_FLAG HSL_RW - -#define VT_PORT_NUM "vtbf_vtpn" -#define VLAN_TABLE_FUNC0_VT_PORT_NUM_BOFFSET 8 -#define VLAN_TABLE_FUNC0_VT_PORT_NUM_BLEN 4 -#define VLAN_TABLE_FUNC0_VT_PORT_NUM_FLAG HSL_RW - -#define VT_FULL_VIO "vtbf_vtflv" -#define VLAN_TABLE_FUNC0_VT_FULL_VIO_BOFFSET 4 -#define VLAN_TABLE_FUNC0_VT_FULL_VIO_BLEN 1 -#define VLAN_TABLE_FUNC0_VT_FULL_VIO_FLAG HSL_RW - -#define VT_BUSY "vtbf_vtbs" -#define VLAN_TABLE_FUNC0_VT_BUSY_BOFFSET 3 -#define VLAN_TABLE_FUNC0_VT_BUSY_BLEN 1 -#define VLAN_TABLE_FUNC0_VT_BUSY_FLAG HSL_RW - -#define VT_FUNC "vtbf_vtfc" -#define VLAN_TABLE_FUNC0_VT_FUNC_BOFFSET 0 -#define VLAN_TABLE_FUNC0_VT_FUNC_BLEN 3 -#define VLAN_TABLE_FUNC0_VT_FUNC_FLAG HSL_RW - -#define VLAN_TABLE_FUNC1 "vtbf1" -#define VLAN_TABLE_FUNC1_ID 10 -#define VLAN_TABLE_FUNC1_OFFSET 0x0044 -#define VLAN_TABLE_FUNC1_E_LENGTH 4 -#define VLAN_TABLE_FUNC1_E_OFFSET 0 -#define VLAN_TABLE_FUNC1_NR_E 1 - -#define VT_VALID "vtbf_vtvd" -#define VLAN_TABLE_FUNC1_VT_VALID_BOFFSET 11 -#define VLAN_TABLE_FUNC1_VT_VALID_BLEN 1 -#define VLAN_TABLE_FUNC1_VT_VALID_FLAG HSL_RW - -#define VID_MEM "vtbf_vidm" -#define VLAN_TABLE_FUNC1_VID_MEM_BOFFSET 0 -#define VLAN_TABLE_FUNC1_VID_MEM_BLEN 10 -#define VLAN_TABLE_FUNC1_VID_MEM_FLAG HSL_RW - - - /* Address Table Function Register */ -#define ADDR_TABLE_FUNC0 "atbf0" -#define ADDR_TABLE_FUNC0_ID 11 -#define ADDR_TABLE_FUNC0_OFFSET 0x0050 -#define ADDR_TABLE_FUNC0_E_LENGTH 4 -#define ADDR_TABLE_FUNC0_E_OFFSET 0 -#define ADDR_TABLE_FUNC0_NR_E 1 - -#define AT_ADDR_BYTE4 "atbf_adb4" -#define ADDR_TABLE_FUNC0_AT_ADDR_BYTE4_BOFFSET 24 -#define ADDR_TABLE_FUNC0_AT_ADDR_BYTE4_BLEN 8 -#define ADDR_TABLE_FUNC0_AT_ADDR_BYTE4_FLAG HSL_RW - -#define AT_ADDR_BYTE5 "atbf_adb5" -#define ADDR_TABLE_FUNC0_AT_ADDR_BYTE5_BOFFSET 16 -#define ADDR_TABLE_FUNC0_AT_ADDR_BYTE5_BLEN 8 -#define ADDR_TABLE_FUNC0_AT_ADDR_BYTE5_FLAG HSL_RW - -#define AT_FULL_VIO "atbf_atfv" -#define ADDR_TABLE_FUNC0_AT_FULL_VIO_BOFFSET 12 -#define ADDR_TABLE_FUNC0_AT_FULL_VIO_BLEN 1 -#define ADDR_TABLE_FUNC0_AT_FULL_VIO_FLAG HSL_RW - -#define AT_PORT_NUM "atbf_atpn" -#define ADDR_TABLE_FUNC0_AT_PORT_NUM_BOFFSET 8 -#define ADDR_TABLE_FUNC0_AT_PORT_NUM_BLEN 4 -#define ADDR_TABLE_FUNC0_AT_PORT_NUM_FLAG HSL_RW - -#define FLUSH_ST_EN "atbf_fsen" -#define ADDR_TABLE_FUNC0_FLUSH_ST_EN_BOFFSET 4 -#define ADDR_TABLE_FUNC0_FLUSH_ST_EN_BLEN 1 -#define ADDR_TABLE_FUNC0_FLUSH_ST_EN_FLAG HSL_RW - -#define AT_BUSY "atbf_atbs" -#define ADDR_TABLE_FUNC0_AT_BUSY_BOFFSET 3 -#define ADDR_TABLE_FUNC0_AT_BUSY_BLEN 1 -#define ADDR_TABLE_FUNC0_AT_BUSY_FLAG HSL_RW - -#define AT_FUNC "atbf_atfc" -#define ADDR_TABLE_FUNC0_AT_FUNC_BOFFSET 0 -#define ADDR_TABLE_FUNC0_AT_FUNC_BLEN 3 -#define ADDR_TABLE_FUNC0_AT_FUNC_FLAG HSL_RW - -#define ADDR_TABLE_FUNC1 "atbf1" -#define ADDR_TABLE_FUNC1_ID 12 -#define ADDR_TABLE_FUNC1_OFFSET 0x0054 -#define ADDR_TABLE_FUNC1_E_LENGTH 4 -#define ADDR_TABLE_FUNC1_E_OFFSET 0 -#define ADDR_TABLE_FUNC1_NR_E 0 - -#define AT_ADDR_BYTE0 "atbf_adb0" -#define ADDR_TABLE_FUNC1_AT_ADDR_BYTE0_BOFFSET 24 -#define ADDR_TABLE_FUNC1_AT_ADDR_BYTE0_BLEN 8 -#define ADDR_TABLE_FUNC1_AT_ADDR_BYTE0_FLAG HSL_RW - -#define AT_ADDR_BYTE1 "atbf_adb1" -#define ADDR_TABLE_FUNC1_AT_ADDR_BYTE1_BOFFSET 16 -#define ADDR_TABLE_FUNC1_AT_ADDR_BYTE1_BLEN 8 -#define ADDR_TABLE_FUNC1_AT_ADDR_BYTE1_FLAG HSL_RW - -#define AT_ADDR_BYTE2 "atbf_adb2" -#define ADDR_TABLE_FUNC1_AT_ADDR_BYTE2_BOFFSET 8 -#define ADDR_TABLE_FUNC1_AT_ADDR_BYTE2_BLEN 8 -#define ADDR_TABLE_FUNC1_AT_ADDR_BYTE2_FLAG HSL_RW - -#define AT_ADDR_BYTE3 "atbf_adb3" -#define ADDR_TABLE_FUNC1_AT_ADDR_BYTE3_BOFFSET 0 -#define ADDR_TABLE_FUNC1_AT_ADDR_BYTE3_BLEN 8 -#define ADDR_TABLE_FUNC1_AT_ADDR_BYTE3_FLAG HSL_RW - -#define ADDR_TABLE_FUNC2 "atbf2" -#define ADDR_TABLE_FUNC2_ID 13 -#define ADDR_TABLE_FUNC2_OFFSET 0x0058 -#define ADDR_TABLE_FUNC2_E_LENGTH 4 -#define ADDR_TABLE_FUNC2_E_OFFSET 0 -#define ADDR_TABLE_FUNC2_NR_E 0 - -#define COPY_TO_CPU "atbf_cpcpu" -#define ADDR_TABLE_FUNC2_COPY_TO_CPU_BOFFSET 26 -#define ADDR_TABLE_FUNC2_COPY_TO_CPU_BLEN 1 -#define ADDR_TABLE_FUNC2_COPY_TO_CPU_FLAG HSL_RW - -#define REDRCT_TO_CPU "atbf_rdcpu" -#define ADDR_TABLE_FUNC2_REDRCT_TO_CPU_BOFFSET 25 -#define ADDR_TABLE_FUNC2_REDRCT_TO_CPU_BLEN 1 -#define ADDR_TABLE_FUNC2_REDRCT_TO_CPU_FLAG HSL_RW - -#define LEAKY_EN "atbf_lkyen" -#define ADDR_TABLE_FUNC2_LEAKY_EN_BOFFSET 24 -#define ADDR_TABLE_FUNC2_LEAKY_EN_BLEN 1 -#define ADDR_TABLE_FUNC2_LEAKY_EN_FLAG HSL_RW - -#define AT_STATUS "atbf_atsts" -#define ADDR_TABLE_FUNC2_AT_STATUS_BOFFSET 16 -#define ADDR_TABLE_FUNC2_AT_STATUS_BLEN 4 -#define ADDR_TABLE_FUNC2_AT_STATUS_FLAG HSL_RW - -#define CLONE_EN "atbf_clone" -#define ADDR_TABLE_FUNC2_CLONE_EN_BOFFSET 15 -#define ADDR_TABLE_FUNC2_CLONE_EN_BLEN 1 -#define ADDR_TABLE_FUNC2_CLONE_EN_FLAG HSL_RW - -#define SA_DROP_EN "atbf_saden" -#define ADDR_TABLE_FUNC2_SA_DROP_EN_BOFFSET 14 -#define ADDR_TABLE_FUNC2_SA_DROP_EN_BLEN 1 -#define ADDR_TABLE_FUNC2_SA_DROP_EN_FLAG HSL_RW - -#define MIRROR_EN "atbf_miren" -#define ADDR_TABLE_FUNC2_MIRROR_EN_BOFFSET 13 -#define ADDR_TABLE_FUNC2_MIRROR_EN_BLEN 1 -#define ADDR_TABLE_FUNC2_MIRROR_EN_FLAG HSL_RW - -#define AT_PRI_EN "atbf_atpen" -#define ADDR_TABLE_FUNC2_AT_PRI_EN_BOFFSET 12 -#define ADDR_TABLE_FUNC2_AT_PRI_EN_BLEN 1 -#define ADDR_TABLE_FUNC2_AT_PRI_EN_FLAG HSL_RW - -#define AT_PRI "atbf_atpri" -#define ADDR_TABLE_FUNC2_AT_PRI_BOFFSET 10 -#define ADDR_TABLE_FUNC2_AT_PRI_BLEN 2 -#define ADDR_TABLE_FUNC2_AT_PRI_FLAG HSL_RW - -#define DES_PORT "atbf_desp" -#define ADDR_TABLE_FUNC2_DES_PORT_BOFFSET 0 -#define ADDR_TABLE_FUNC2_DES_PORT_BLEN 6 -#define ADDR_TABLE_FUNC2_DES_PORT_FLAG HSL_RW - - - /* Address Table Control Register */ -#define ADDR_TABLE_CTL "atbc" -#define ADDR_TABLE_CTL_ID 14 -#define ADDR_TABLE_CTL_OFFSET 0x005C -#define ADDR_TABLE_CTL_E_LENGTH 4 -#define ADDR_TABLE_CTL_E_OFFSET 0 -#define ADDR_TABLE_CTL_NR_E 1 - -#define ARP_EN "atbc_arpe" -#define ADDR_TABLE_CTL_ARP_EN_BOFFSET 20 -#define ADDR_TABLE_CTL_ARP_EN_BLEN 1 -#define ADDR_TABLE_CTL_ARP_EN_FLAG HSL_RW - -#define ARL_INI_EN "atbc_arlie" -#define ADDR_TABLE_CTL_ARL_INI_EN_BOFFSET 19 -#define ADDR_TABLE_CTL_ARL_INI_EN_BLEN 1 -#define ADDR_TABLE_CTL_ARL_INI_EN_FLAG HSL_RW - -#define LEARN_CHANGE_EN "atbc_lcen" -#define ADDR_TABLE_CTL_LEARN_CHANGE_EN_BOFFSET 18 -#define ADDR_TABLE_CTL_LEARN_CHANGE_EN_BLEN 1 -#define ADDR_TABLE_CTL_LEARN_CHANGE_EN_FLAG HSL_RW - -#define AGE_EN "atbc_agee" -#define ADDR_TABLE_CTL_AGE_EN_BOFFSET 17 -#define ADDR_TABLE_CTL_AGE_EN_BLEN 1 -#define ADDR_TABLE_CTL_AGE_EN_FLAG HSL_RW - -#define AGE_TIME "atbc_aget" -#define ADDR_TABLE_CTL_AGE_TIME_BOFFSET 0 -#define ADDR_TABLE_CTL_AGE_TIME_BLEN 16 -#define ADDR_TABLE_CTL_AGE_TIME_FLAG HSL_RW - - - /* IP Priority Mapping Register */ -#define IP_PRI_MAPPING "imap" -#define IP_PRI_MAPPING_ID 15 -#define IP_PRI_MAPPING_OFFSET 0x0060 -#define IP_PRI_MAPPING_E_LENGTH 4 -#define IP_PRI_MAPPING_E_OFFSET 0 -#define IP_PRI_MAPPING_NR_E 1 - - - /* IP Priority Mapping Register */ -#define IP_PRI_MAPPING0 "imap0" -#define IP_PRI_MAPPING0_ID 15 -#define IP_PRI_MAPPING0_OFFSET 0x0060 -#define IP_PRI_MAPPING0_E_LENGTH 4 -#define IP_PRI_MAPPING0_E_OFFSET 0 -#define IP_PRI_MAPPING0_NR_E 0 - -#define IP_0X3C "imap_ip3c" -#define IP_PRI_MAPPING0_IP_0X3C_BOFFSET 30 -#define IP_PRI_MAPPING0_IP_0X3C_BLEN 2 -#define IP_PRI_MAPPING0_IP_0X3C_FLAG HSL_RW - -#define IP_0X38 "imap_ip38" -#define IP_PRI_MAPPING0_IP_0X38_BOFFSET 28 -#define IP_PRI_MAPPING0_IP_0X38_BLEN 2 -#define IP_PRI_MAPPING0_IP_0X38_FLAG HSL_RW - -#define IP_0X34 "imap_ip34" -#define IP_PRI_MAPPING0_IP_0X34_BOFFSET 26 -#define IP_PRI_MAPPING0_IP_0X34_BLEN 2 -#define IP_PRI_MAPPING0_IP_0X34_FLAG HSL_RW - -#define IP_0X30 "imap_ip30" -#define IP_PRI_MAPPING0_IP_0X30_BOFFSET 24 -#define IP_PRI_MAPPING0_IP_0X30_BLEN 2 -#define IP_PRI_MAPPING0_IP_0X30_FLAG HSL_RW - -#define IP_0X2C "imap_ip2c" -#define IP_PRI_MAPPING0_IP_0X2C_BOFFSET 22 -#define IP_PRI_MAPPING0_IP_0X2C_BLEN 2 -#define IP_PRI_MAPPING0_IP_0X2C_FLAG HSL_RW - -#define IP_0X28 "imap_ip28" -#define IP_PRI_MAPPING0_IP_0X28_BOFFSET 20 -#define IP_PRI_MAPPING0_IP_0X28_BLEN 2 -#define IP_PRI_MAPPING0_IP_0X28_FLAG HSL_RW - -#define IP_0X24 "imap_ip24" -#define IP_PRI_MAPPING0_IP_0X24_BOFFSET 18 -#define IP_PRI_MAPPING0_IP_0X24_BLEN 2 -#define IP_PRI_MAPPING0_IP_0X24_FLAG HSL_RW - -#define IP_0X20 "imap_ip20" -#define IP_PRI_MAPPING0_IP_0X20_BOFFSET 16 -#define IP_PRI_MAPPING0_IP_0X20_BLEN 2 -#define IP_PRI_MAPPING0_IP_0X20_FLAG HSL_RW - -#define IP_0X1C "imap_ip1c" -#define IP_PRI_MAPPING0_IP_0X1C_BOFFSET 14 -#define IP_PRI_MAPPING0_IP_0X1C_BLEN 2 -#define IP_PRI_MAPPING0_IP_0X1C_FLAG HSL_RW - -#define IP_0X18 "imap_ip18" -#define IP_PRI_MAPPING0_IP_0X18_BOFFSET 12 -#define IP_PRI_MAPPING0_IP_0X18_BLEN 2 -#define IP_PRI_MAPPING0_IP_0X18_FLAG HSL_RW - -#define IP_0X14 "imap_ip14" -#define IP_PRI_MAPPING0_IP_0X14_BOFFSET 10 -#define IP_PRI_MAPPING0_IP_0X14_BLEN 2 -#define IP_PRI_MAPPING0_IP_0X14_FLAG HSL_RW - -#define IP_0X10 "imap_ip10" -#define IP_PRI_MAPPING0_IP_0X10_BOFFSET 8 -#define IP_PRI_MAPPING0_IP_0X10_BLEN 2 -#define IP_PRI_MAPPING0_IP_0X10_FLAG HSL_RW - -#define IP_0X0C "imap_ip0c" -#define IP_PRI_MAPPING0_IP_0X0C_BOFFSET 6 -#define IP_PRI_MAPPING0_IP_0X0C_BLEN 2 -#define IP_PRI_MAPPING0_IP_0X0C_FLAG HSL_RW - -#define IP_0X08 "imap_ip08" -#define IP_PRI_MAPPING0_IP_0X08_BOFFSET 4 -#define IP_PRI_MAPPING0_IP_0X08_BLEN 2 -#define IP_PRI_MAPPING0_IP_0X08_FLAG HSL_RW - -#define IP_0X04 "imap_ip04" -#define IP_PRI_MAPPING0_IP_0X04_BOFFSET 2 -#define IP_PRI_MAPPING0_IP_0X04_BLEN 2 -#define IP_PRI_MAPPING0_IP_0X04_FLAG HSL_RW - -#define IP_0X00 "imap_ip00" -#define IP_PRI_MAPPING0_IP_0X00_BOFFSET 0 -#define IP_PRI_MAPPING0_IP_0X00_BLEN 2 -#define IP_PRI_MAPPING0_IP_0X00_FLAG HSL_RW - -#define IP_PRI_MAPPING1 "imap1" -#define IP_PRI_MAPPING1_ID 16 -#define IP_PRI_MAPPING1_OFFSET 0x0064 -#define IP_PRI_MAPPING1_E_LENGTH 4 -#define IP_PRI_MAPPING1_E_OFFSET 0 -#define IP_PRI_MAPPING1_NR_E 0 - -#define IP_0X7C "imap_ip7c" -#define IP_PRI_MAPPING1_IP_0X7C_BOFFSET 30 -#define IP_PRI_MAPPING1_IP_0X7C_BLEN 2 -#define IP_PRI_MAPPING1_IP_0X7C_FLAG HSL_RW - -#define IP_0X78 "imap_ip78" -#define IP_PRI_MAPPING1_IP_0X78_BOFFSET 28 -#define IP_PRI_MAPPING1_IP_0X78_BLEN 2 -#define IP_PRI_MAPPING1_IP_0X78_FLAG HSL_RW - -#define IP_0X74 "imap_ip74" -#define IP_PRI_MAPPING1_IP_0X74_BOFFSET 26 -#define IP_PRI_MAPPING1_IP_0X74_BLEN 2 -#define IP_PRI_MAPPING1_IP_0X74_FLAG HSL_RW - -#define IP_0X70 "imap_ip70" -#define IP_PRI_MAPPING1_IP_0X70_BOFFSET 24 -#define IP_PRI_MAPPING1_IP_0X70_BLEN 2 -#define IP_PRI_MAPPING1_IP_0X70_FLAG HSL_RW - -#define IP_0X6C "imap_ip6c" -#define IP_PRI_MAPPING1_IP_0X6C_BOFFSET 22 -#define IP_PRI_MAPPING1_IP_0X6C_BLEN 2 -#define IP_PRI_MAPPING1_IP_0X6C_FLAG HSL_RW - -#define IP_0X68 "imap_ip68" -#define IP_PRI_MAPPING1_IP_0X68_BOFFSET 20 -#define IP_PRI_MAPPING1_IP_0X68_BLEN 2 -#define IP_PRI_MAPPING1_IP_0X68_FLAG HSL_RW - -#define IP_0X64 "imap_ip64" -#define IP_PRI_MAPPING1_IP_0X64_BOFFSET 18 -#define IP_PRI_MAPPING1_IP_0X64_BLEN 2 -#define IP_PRI_MAPPING1_IP_0X64_FLAG HSL_RW - -#define IP_0X60 "imap_ip60" -#define IP_PRI_MAPPING1_IP_0X60_BOFFSET 16 -#define IP_PRI_MAPPING1_IP_0X60_BLEN 2 -#define IP_PRI_MAPPING1_IP_0X60_FLAG HSL_RW - -#define IP_0X5C "imap_ip5c" -#define IP_PRI_MAPPING1_IP_0X5C_BOFFSET 14 -#define IP_PRI_MAPPING1_IP_0X5C_BLEN 2 -#define IP_PRI_MAPPING1_IP_0X5C_FLAG HSL_RW - -#define IP_0X58 "imap_ip58" -#define IP_PRI_MAPPING1_IP_0X58_BOFFSET 12 -#define IP_PRI_MAPPING1_IP_0X58_BLEN 2 -#define IP_PRI_MAPPING1_IP_0X58_FLAG HSL_RW - -#define IP_0X54 "imap_ip54" -#define IP_PRI_MAPPING1_IP_0X54_BOFFSET 10 -#define IP_PRI_MAPPING1_IP_0X54_BLEN 2 -#define IP_PRI_MAPPING1_IP_0X54_FLAG HSL_RW - -#define IP_0X50 "imap_ip50" -#define IP_PRI_MAPPING1_IP_0X50_BOFFSET 8 -#define IP_PRI_MAPPING1_IP_0X50_BLEN 2 -#define IP_PRI_MAPPING1_IP_0X50_FLAG HSL_RW - -#define IP_0X4C "imap_ip4c" -#define IP_PRI_MAPPING1_IP_0X4C_BOFFSET 6 -#define IP_PRI_MAPPING1_IP_0X4C_BLEN 2 -#define IP_PRI_MAPPING1_IP_0X4C_FLAG HSL_RW - -#define IP_0X48 "imap_ip48" -#define IP_PRI_MAPPING1_IP_0X48_BOFFSET 4 -#define IP_PRI_MAPPING1_IP_0X48_BLEN 2 -#define IP_PRI_MAPPING1_IP_0X48_FLAG HSL_RW - -#define IP_0X44 "imap_ip44" -#define IP_PRI_MAPPING1_IP_0X44_BOFFSET 2 -#define IP_PRI_MAPPING1_IP_0X44_BLEN 2 -#define IP_PRI_MAPPING1_IP_0X44_FLAG HSL_RW - -#define IP_0X40 "imap_ip40" -#define IP_PRI_MAPPING1_IP_0X40_BOFFSET 0 -#define IP_PRI_MAPPING1_IP_0X40_BLEN 2 -#define IP_PRI_MAPPING1_IP_0X40_FLAG HSL_RW - - -#define IP_PRI_MAPPING2 "imap2" -#define IP_PRI_MAPPING2_ID 17 -#define IP_PRI_MAPPING2_OFFSET 0x0068 -#define IP_PRI_MAPPING2_E_LENGTH 4 -#define IP_PRI_MAPPING2_E_OFFSET 0 -#define IP_PRI_MAPPING2_NR_E 0 - -#define IP_0XBC "imap_ipbc" -#define IP_PRI_MAPPING2_IP_0XBC_BOFFSET 30 -#define IP_PRI_MAPPING2_IP_0XBC_BLEN 2 -#define IP_PRI_MAPPING2_IP_0XBC_FLAG HSL_RW - -#define IP_0XB8 "imap_ipb8" -#define IP_PRI_MAPPING2_IP_0XB8_BOFFSET 28 -#define IP_PRI_MAPPING2_IP_0XB8_BLEN 2 -#define IP_PRI_MAPPING2_IP_0XB8_FLAG HSL_RW - -#define IP_0XB4 "imap_ipb4" -#define IP_PRI_MAPPING2_IP_0XB4_BOFFSET 26 -#define IP_PRI_MAPPING2_IP_0XB4_BLEN 2 -#define IP_PRI_MAPPING2_IP_0XB4_FLAG HSL_RW - -#define IP_0XB0 "imap_ipb0" -#define IP_PRI_MAPPING2_IP_0XB0_BOFFSET 24 -#define IP_PRI_MAPPING2_IP_0XB0_BLEN 2 -#define IP_PRI_MAPPING2_IP_0XB0_FLAG HSL_RW - -#define IP_0XAC "imap_ipac" -#define IP_PRI_MAPPING2_IP_0XAC_BOFFSET 22 -#define IP_PRI_MAPPING2_IP_0XAC_BLEN 2 -#define IP_PRI_MAPPING2_IP_0XAC_FLAG HSL_RW - -#define IP_0XA8 "imap_ipa8" -#define IP_PRI_MAPPING2_IP_0XA8_BOFFSET 20 -#define IP_PRI_MAPPING2_IP_0XA8_BLEN 2 -#define IP_PRI_MAPPING2_IP_0XA8_FLAG HSL_RW - -#define IP_0XA4 "imap_ipa4" -#define IP_PRI_MAPPING2_IP_0XA4_BOFFSET 18 -#define IP_PRI_MAPPING2_IP_0XA4_BLEN 2 -#define IP_PRI_MAPPING2_IP_0XA4_FLAG HSL_RW - -#define IP_0XA0 "imap_ipa0" -#define IP_PRI_MAPPING2_IP_0XA0_BOFFSET 16 -#define IP_PRI_MAPPING2_IP_0XA0_BLEN 2 -#define IP_PRI_MAPPING2_IP_0XA0_FLAG HSL_RW - -#define IP_0X9C "imap_ip9c" -#define IP_PRI_MAPPING2_IP_0X9C_BOFFSET 14 -#define IP_PRI_MAPPING2_IP_0X9C_BLEN 2 -#define IP_PRI_MAPPING2_IP_0X9C_FLAG HSL_RW - -#define IP_0X98 "imap_ip98" -#define IP_PRI_MAPPING2_IP_0X98_BOFFSET 12 -#define IP_PRI_MAPPING2_IP_0X98_BLEN 2 -#define IP_PRI_MAPPING2_IP_0X98_FLAG HSL_RW - -#define IP_0X94 "imap_ip94" -#define IP_PRI_MAPPING2_IP_0X94_BOFFSET 10 -#define IP_PRI_MAPPING2_IP_0X94_BLEN 2 -#define IP_PRI_MAPPING2_IP_0X94_FLAG HSL_RW - -#define IP_0X90 "imap_ip90" -#define IP_PRI_MAPPING2_IP_0X90_BOFFSET 8 -#define IP_PRI_MAPPING2_IP_0X90_BLEN 2 -#define IP_PRI_MAPPING2_IP_0X90_FLAG HSL_RW - -#define IP_0X8C "imap_ip8c" -#define IP_PRI_MAPPING2_IP_0X8C_BOFFSET 6 -#define IP_PRI_MAPPING2_IP_0X8C_BLEN 2 -#define IP_PRI_MAPPING2_IP_0X8C_FLAG HSL_RW - -#define IP_0X88 "imap_ip88" -#define IP_PRI_MAPPING2_IP_0X88_BOFFSET 4 -#define IP_PRI_MAPPING2_IP_0X88_BLEN 2 -#define IP_PRI_MAPPING2_IP_0X88_FLAG HSL_RW - -#define IP_0X84 "imap_ip84" -#define IP_PRI_MAPPING2_IP_0X84_BOFFSET 2 -#define IP_PRI_MAPPING2_IP_0X84_BLEN 2 -#define IP_PRI_MAPPING2_IP_0X84_FLAG HSL_RW - -#define IP_0X80 "imap_ip80" -#define IP_PRI_MAPPING2_IP_0X80_BOFFSET 0 -#define IP_PRI_MAPPING2_IP_0X80_BLEN 2 -#define IP_PRI_MAPPING2_IP_0X80_FLAG HSL_RW - -#define IP_PRI_MAPPING3 "imap3" -#define IP_PRI_MAPPING3_ID 18 -#define IP_PRI_MAPPING3_OFFSET 0x006C -#define IP_PRI_MAPPING3_E_LENGTH 4 -#define IP_PRI_MAPPING3_E_OFFSET 0 -#define IP_PRI_MAPPING3_NR_E 0 - -#define IP_0XFC "imap_ipfc" -#define IP_PRI_MAPPING3_IP_0XFC_BOFFSET 30 -#define IP_PRI_MAPPING3_IP_0XFC_BLEN 2 -#define IP_PRI_MAPPING3_IP_0XFC_FLAG HSL_RW - -#define IP_0XF8 "imap_ipf8" -#define IP_PRI_MAPPING3_IP_0XF8_BOFFSET 28 -#define IP_PRI_MAPPING3_IP_0XF8_BLEN 2 -#define IP_PRI_MAPPING3_IP_0XF8_FLAG HSL_RW - -#define IP_0XF4 "imap_ipf4" -#define IP_PRI_MAPPING3_IP_0XF4_BOFFSET 26 -#define IP_PRI_MAPPING3_IP_0XF4_BLEN 2 -#define IP_PRI_MAPPING3_IP_0XF4_FLAG HSL_RW - -#define IP_0XF0 "imap_ipf0" -#define IP_PRI_MAPPING3_IP_0XF0_BOFFSET 24 -#define IP_PRI_MAPPING3_IP_0XF0_BLEN 2 -#define IP_PRI_MAPPING3_IP_0XF0_FLAG HSL_RW - -#define IP_0XEC "imap_ipec" -#define IP_PRI_MAPPING3_IP_0XEC_BOFFSET 22 -#define IP_PRI_MAPPING3_IP_0XEC_BLEN 2 -#define IP_PRI_MAPPING3_IP_0XEC_FLAG HSL_RW - -#define IP_0XE8 "imap_ipe8" -#define IP_PRI_MAPPING3_IP_0XE8_BOFFSET 20 -#define IP_PRI_MAPPING3_IP_0XE8_BLEN 2 -#define IP_PRI_MAPPING3_IP_0XE8_FLAG HSL_RW - -#define IP_0XE4 "imap_ipe4" -#define IP_PRI_MAPPING3_IP_0XE4_BOFFSET 18 -#define IP_PRI_MAPPING3_IP_0XE4_BLEN 2 -#define IP_PRI_MAPPING3_IP_0XE4_FLAG HSL_RW - -#define IP_0XE0 "imap_ipe0" -#define IP_PRI_MAPPING3_IP_0XE0_BOFFSET 16 -#define IP_PRI_MAPPING3_IP_0XE0_BLEN 2 -#define IP_PRI_MAPPING3_IP_0XE0_FLAG HSL_RW - -#define IP_0XDC "imap_ipdc" -#define IP_PRI_MAPPING3_IP_0XDC_BOFFSET 14 -#define IP_PRI_MAPPING3_IP_0XDC_BLEN 2 -#define IP_PRI_MAPPING3_IP_0XDC_FLAG HSL_RW - -#define IP_0XD8 "imap_ipd8" -#define IP_PRI_MAPPING3_IP_0XD8_BOFFSET 12 -#define IP_PRI_MAPPING3_IP_0XD8_BLEN 2 -#define IP_PRI_MAPPING3_IP_0XD8_FLAG HSL_RW - -#define IP_0XD4 "imap_ipd4" -#define IP_PRI_MAPPING3_IP_0XD4_BOFFSET 10 -#define IP_PRI_MAPPING3_IP_0XD4_BLEN 2 -#define IP_PRI_MAPPING3_IP_0XD4_FLAG HSL_RW - -#define IP_0XD0 "imap_ipd0" -#define IP_PRI_MAPPING3_IP_0XD0_BOFFSET 8 -#define IP_PRI_MAPPING3_IP_0XD0_BLEN 2 -#define IP_PRI_MAPPING3_IP_0XD0_FLAG HSL_RW - -#define IP_0XCC "imap_ipcc" -#define IP_PRI_MAPPING3_IP_0XCC_BOFFSET 6 -#define IP_PRI_MAPPING3_IP_0XCC_BLEN 2 -#define IP_PRI_MAPPING3_IP_0XCC_FLAG HSL_RW - -#define IP_0XC8 "imap_ipc8" -#define IP_PRI_MAPPING3_IP_0XC8_BOFFSET 4 -#define IP_PRI_MAPPING3_IP_0XC8_BLEN 2 -#define IP_PRI_MAPPING3_IP_0XC8_FLAG HSL_RW - -#define IP_0XC4 "imap_ipc4" -#define IP_PRI_MAPPING3_IP_0XC4_BOFFSET 2 -#define IP_PRI_MAPPING3_IP_0XC4_BLEN 2 -#define IP_PRI_MAPPING3_IP_0XC4_FLAG HSL_RW - -#define IP_0XC0 "imap_ipc0" -#define IP_PRI_MAPPING3_IP_0XC0_BOFFSET 0 -#define IP_PRI_MAPPING3_IP_0XC0_BLEN 2 -#define IP_PRI_MAPPING3_IP_0XC0_FLAG HSL_RW - - - /* Tag Priority Mapping Register */ -#define TAG_PRI_MAPPING "tpmap" -#define TAG_PRI_MAPPING_ID 19 -#define TAG_PRI_MAPPING_OFFSET 0x0070 -#define TAG_PRI_MAPPING_E_LENGTH 4 -#define TAG_PRI_MAPPING_E_OFFSET 0 -#define TAG_PRI_MAPPING_NR_E 1 - -#define TAG_0X07 "tpmap_tg07" -#define TAG_PRI_MAPPING_TAG_0X07_BOFFSET 14 -#define TAG_PRI_MAPPING_TAG_0X07_BLEN 2 -#define TAG_PRI_MAPPING_TAG_0X07_FLAG HSL_RW - -#define TAG_0X06 "tpmap_tg06" -#define TAG_PRI_MAPPING_TAG_0X06_BOFFSET 12 -#define TAG_PRI_MAPPING_TAG_0X06_BLEN 2 -#define TAG_PRI_MAPPING_TAG_0X06_FLAG HSL_RW - -#define TAG_0X05 "tpmap_tg05" -#define TAG_PRI_MAPPING_TAG_0X05_BOFFSET 10 -#define TAG_PRI_MAPPING_TAG_0X05_BLEN 2 -#define TAG_PRI_MAPPING_TAG_0X05_FLAG HSL_RW - -#define TAG_0X04 "tpmap_tg04" -#define TAG_PRI_MAPPING_TAG_0X04_BOFFSET 8 -#define TAG_PRI_MAPPING_TAG_0X04_BLEN 2 -#define TAG_PRI_MAPPING_TAG_0X04_FLAG HSL_RW - -#define TAG_0X03 "tpmap_tg03" -#define TAG_PRI_MAPPING_TAG_0X03_BOFFSET 6 -#define TAG_PRI_MAPPING_TAG_0X03_BLEN 2 -#define TAG_PRI_MAPPING_TAG_0X03_FLAG HSL_RW - -#define TAG_0X02 "tpmap_tg02" -#define TAG_PRI_MAPPING_TAG_0X02_BOFFSET 4 -#define TAG_PRI_MAPPING_TAG_0X02_BLEN 2 -#define TAG_PRI_MAPPING_TAG_0X02_FLAG HSL_RW - -#define TAG_0X01 "tpmap_tg01" -#define TAG_PRI_MAPPING_TAG_0X01_BOFFSET 2 -#define TAG_PRI_MAPPING_TAG_0X01_BLEN 2 -#define TAG_PRI_MAPPING_TAG_0X01_FLAG HSL_RW - -#define TAG_0X00 "tpmap_tg00" -#define TAG_PRI_MAPPING_TAG_0X00_BOFFSET 0 -#define TAG_PRI_MAPPING_TAG_0X00_BLEN 2 -#define TAG_PRI_MAPPING_TAG_0X00_FLAG HSL_RW - - - /* Service tag Register */ -#define SERVICE_TAG "servicetag" -#define SERVICE_TAG_ID 20 -#define SERVICE_TAG_OFFSET 0x0074 -#define SERVICE_TAG_E_LENGTH 4 -#define SERVICE_TAG_E_OFFSET 0 -#define SERVICE_TAG_NR_E 1 - -#define TAG_VALUE "servicetag_val" -#define SERVICE_TAG_TAG_VALUE_BOFFSET 0 -#define SERVICE_TAG_TAG_VALUE_BLEN 16 -#define SERVICE_TAG_TAG_VALUE_FLAG HSL_RW - - - /* Cpu Port Register */ -#define CPU_PORT "cpup" -#define CPU_PORT_ID 20 -#define CPU_PORT_OFFSET 0x0078 -#define CPU_PORT_E_LENGTH 4 -#define CPU_PORT_E_OFFSET 0 -#define CPU_PORT_NR_E 0 - -#define CPU_PORT_EN "cpup_cpupe" -#define CPU_PORT_CPU_PORT_EN_BOFFSET 8 -#define CPU_PORT_CPU_PORT_EN_BLEN 1 -#define CPU_PORT_CPU_PORT_EN_FLAG HSL_RW - -#define MIRROR_PORT_NUM "cpup_mirpn" -#define CPU_PORT_MIRROR_PORT_NUM_BOFFSET 4 -#define CPU_PORT_MIRROR_PORT_NUM_BLEN 4 -#define CPU_PORT_MIRROR_PORT_NUM_FLAG HSL_RW - - - /* MIB Function Register */ -#define MIB_FUNC "mibfunc" -#define MIB_FUNC_ID 21 -#define MIB_FUNC_OFFSET 0x0080 -#define MIB_FUNC_E_LENGTH 4 -#define MIB_FUNC_E_OFFSET 0 -#define MIB_FUNC_NR_E 1 - -#define MAC_CRC_EN "mibfunc_crcen" -#define MIB_FUNC_MAC_CRC_EN_BOFFSET 31 -#define MIB_FUNC_MAC_CRC_EN_BLEN 1 -#define MIB_FUNC_MAC_CRC_EN_FLAG HSL_RW - -#define MIB_EN "mib_en" -#define MIB_FUNC_MIB_EN_BOFFSET 30 -#define MIB_FUNC_MIB_EN_BLEN 1 -#define MIB_FUNC_MIB_EN_FLAG HSL_RW - -#define MIB_FUN "mibfunc_mibf" -#define MIB_FUNC_MIB_FUN_BOFFSET 24 -#define MIB_FUNC_MIB_FUN_BLEN 3 -#define MIB_FUNC_MIB_FUN_FLAG HSL_RW - -#define MIB_BUSY "mibfunc_mibb" -#define MIB_FUNC_MIB_BUSY_BOFFSET 17 -#define MIB_FUNC_MIB_BUSY_BLEN 1 -#define MIB_FUNC_MIB_BUSY_FLAG HSL_RW - -#define MIB_AT_HALF_EN "mibfunc_mibhe" -#define MIB_FUNC_MIB_AT_HALF_EN_BOFFSET 16 -#define MIB_FUNC_MIB_AT_HALF_EN_BLEN 1 -#define MIB_FUNC_MIB_AT_HALF_EN_FLAG HSL_RW - -#define MIB_TIMER "mibfunc_mibt" -#define MIB_FUNC_MIB_TIMER_BOFFSET 0 -#define MIB_FUNC_MIB_TIMER_BLEN 16 -#define MIB_FUNC_MIB_TIMER_FLAG HSL_RW - - - /* Mdio control Register */ -#define MDIO_CTRL "mctrl" -#define MDIO_CTRL_ID 24 -#define MDIO_CTRL_OFFSET 0x0098 -#define MDIO_CTRL_E_LENGTH 4 -#define MDIO_CTRL_E_OFFSET 0 -#define MDIO_CTRL_NR_E 1 - -#define MSTER_EN "mctrl_msteren" -#define MDIO_CTRL_MSTER_EN_BOFFSET 30 -#define MDIO_CTRL_MSTER_EN_BLEN 1 -#define MDIO_CTRL_MSTER_EN_FLAG HSL_RW - -#define MSTER_EN "mctrl_msteren" -#define MDIO_CTRL_MSTER_EN_BOFFSET 30 -#define MDIO_CTRL_MSTER_EN_BLEN 1 -#define MDIO_CTRL_MSTER_EN_FLAG HSL_RW - -#define CMD "mctrl_cmd" -#define MDIO_CTRL_CMD_BOFFSET 27 -#define MDIO_CTRL_CMD_BLEN 1 -#define MDIO_CTRL_CMD_FLAG HSL_RW - -#define SUP_PRE "mctrl_spre" -#define MDIO_CTRL_SUP_PRE_BOFFSET 26 -#define MDIO_CTRL_SUP_PRE_BLEN 1 -#define MDIO_CTRL_SUP_PRE_FLAG HSL_RW - -#define PHY_ADDR "mctrl_phyaddr" -#define MDIO_CTRL_PHY_ADDR_BOFFSET 21 -#define MDIO_CTRL_PHY_ADDR_BLEN 5 -#define MDIO_CTRL_PHY_ADDR_FLAG HSL_RW - -#define REG_ADDR "mctrl_regaddr" -#define MDIO_CTRL_REG_ADDR_BOFFSET 16 -#define MDIO_CTRL_REG_ADDR_BLEN 5 -#define MDIO_CTRL_REG_ADDR_FLAG HSL_RW - -#define DATA "mctrl_data" -#define MDIO_CTRL_DATA_BOFFSET 0 -#define MDIO_CTRL_DATA_BLEN 16 -#define MDIO_CTRL_DATA_FLAG HSL_RW - - - - - /* BIST control Register */ -#define BIST_CTRL "bctrl" -#define BIST_CTRL_ID 24 -#define BIST_CTRL_OFFSET 0x00a0 -#define BIST_CTRL_E_LENGTH 4 -#define BIST_CTRL_E_OFFSET 0 -#define BIST_CTRL_NR_E 1 - -#define BIST_BUSY "bctrl_bb" -#define BIST_CTRL_BIST_BUSY_BOFFSET 31 -#define BIST_CTRL_BIST_BUSY_BLEN 1 -#define BIST_CTRL_BIST_BUSY_FLAG HSL_RW - -#define ONE_ERR "bctrl_oe" -#define BIST_CTRL_ONE_ERR_BOFFSET 30 -#define BIST_CTRL_ONE_ERR_BLEN 1 -#define BIST_CTRL_ONE_ERR_FLAG HSL_RO - -#define ERR_MEM "bctrl_em" -#define BIST_CTRL_ERR_MEM_BOFFSET 24 -#define BIST_CTRL_ERR_MEM_BLEN 4 -#define BIST_CTRL_ERR_MEM_FLAG HSL_RO - -#define PTN_EN2 "bctrl_pe2" -#define BIST_CTRL_PTN_EN2_BOFFSET 22 -#define BIST_CTRL_PTN_EN2_BLEN 1 -#define BIST_CTRL_PTN_EN2_FLAG HSL_RW - -#define PTN_EN1 "bctrl_pe1" -#define BIST_CTRL_PTN_EN1_BOFFSET 21 -#define BIST_CTRL_PTN_EN1_BLEN 1 -#define BIST_CTRL_PTN_EN1_FLAG HSL_RW - -#define PTN_EN0 "bctrl_pe0" -#define BIST_CTRL_PTN_EN0_BOFFSET 20 -#define BIST_CTRL_PTN_EN0_BLEN 1 -#define BIST_CTRL_PTN_EN0_FLAG HSL_RW - -#define ERR_PTN "bctrl_ep" -#define BIST_CTRL_ERR_PTN_BOFFSET 16 -#define BIST_CTRL_ERR_PTN_BLEN 2 -#define BIST_CTRL_ERR_PTN_FLAG HSL_RO - -#define ERR_CNT "bctrl_ec" -#define BIST_CTRL_ERR_CNT_BOFFSET 13 -#define BIST_CTRL_ERR_CNT_BLEN 3 -#define BIST_CTRL_ERR_CNT_FLAG HSL_RO - -#define ERR_ADDR "bctrl_ea" -#define BIST_CTRL_ERR_ADDR_BOFFSET 0 -#define BIST_CTRL_ERR_ADDR_BLEN 13 -#define BIST_CTRL_ERR_ADDR_FLAG HSL_RO - - - - - /* BIST recover Register */ -#define BIST_RCV "brcv" -#define BIST_RCV_ID 24 -#define BIST_RCV_OFFSET 0x00a4 -#define BIST_RCV_E_LENGTH 4 -#define BIST_RCV_E_OFFSET 0 -#define BIST_RCV_NR_E 1 - -#define RCV_EN "brcv_en" -#define BIST_RCV_RCV_EN_BOFFSET 31 -#define BIST_RCV_RCV_EN_BLEN 1 -#define BIST_RCV_RCV_EN_FLAG HSL_RW - -#define RCV_ADDR "brcv_addr" -#define BIST_RCV_RCV_ADDR_BOFFSET 0 -#define BIST_RCV_RCV_ADDR_BLEN 13 -#define BIST_RCV_RCV_ADDR_FLAG HSL_RW - - - - - /* LED control Register */ -#define LED_CTRL "ledctrl" -#define LED_CTRL_ID 25 -#define LED_CTRL_OFFSET 0x00b0 -#define LED_CTRL_E_LENGTH 4 -#define LED_CTRL_E_OFFSET 0 -#define LED_CTRL_NR_E 1 - -#define PATTERN_EN "lctrl_pen" -#define LED_CTRL_PATTERN_EN_BOFFSET 14 -#define LED_CTRL_PATTERN_EN_BLEN 2 -#define LED_CTRL_PATTERN_EN_FLAG HSL_RW - -#define FULL_LIGHT_EN "lctrl_fen" -#define LED_CTRL_FULL_LIGHT_EN_BOFFSET 13 -#define LED_CTRL_FULL_LIGHT_EN_BLEN 1 -#define LED_CTRL_FULL_LIGHT_EN_FLAG HSL_RW - -#define HALF_LIGHT_EN "lctrl_hen" -#define LED_CTRL_HALF_LIGHT_EN_BOFFSET 12 -#define LED_CTRL_HALF_LIGHT_EN_BLEN 1 -#define LED_CTRL_HALF_LIGHT_EN_FLAG HSL_RW - -#define POWERON_LIGHT_EN "lctrl_poen" -#define LED_CTRL_POWERON_LIGHT_EN_BOFFSET 11 -#define LED_CTRL_POWERON_LIGHT_EN_BLEN 1 -#define LED_CTRL_POWERON_LIGHT_EN_FLAG HSL_RW - -#define GE_LIGHT_EN "lctrl_geen" -#define LED_CTRL_GE_LIGHT_EN_BOFFSET 10 -#define LED_CTRL_GE_LIGHT_EN_BLEN 1 -#define LED_CTRL_GE_LIGHT_EN_FLAG HSL_RW - -#define FE_LIGHT_EN "lctrl_feen" -#define LED_CTRL_FE_LIGHT_EN_BOFFSET 9 -#define LED_CTRL_FE_LIGHT_EN_BLEN 1 -#define LED_CTRL_FE_LIGHT_EN_FLAG HSL_RW - -#define ETH_LIGHT_EN "lctrl_ethen" -#define LED_CTRL_ETH_LIGHT_EN_BOFFSET 8 -#define LED_CTRL_ETH_LIGHT_EN_BLEN 1 -#define LED_CTRL_ETH_LIGHT_EN_FLAG HSL_RW - -#define COL_BLINK_EN "lctrl_cen" -#define LED_CTRL_COL_BLINK_EN_BOFFSET 7 -#define LED_CTRL_COL_BLINK_EN_BLEN 1 -#define LED_CTRL_COL_BLINK_EN_FLAG HSL_RW - -#define RX_BLINK_EN "lctrl_rxen" -#define LED_CTRL_RX_BLINK_EN_BOFFSET 5 -#define LED_CTRL_RX_BLINK_EN_BLEN 1 -#define LED_CTRL_RX_BLINK_EN_FLAG HSL_RW - -#define TX_BLINK_EN "lctrl_txen" -#define LED_CTRL_TX_BLINK_EN_BOFFSET 4 -#define LED_CTRL_TX_BLINK_EN_BLEN 1 -#define LED_CTRL_TX_BLINK_EN_FLAG HSL_RW - -#define LINKUP_OVER_EN "lctrl_loen" -#define LED_CTRL_LINKUP_OVER_EN_BOFFSET 2 -#define LED_CTRL_LINKUP_OVER_EN_BLEN 1 -#define LED_CTRL_LINKUP_OVER_EN_FLAG HSL_RW - -#define BLINK_FREQ "lctrl_bfreq" -#define LED_CTRL_BLINK_FREQ_BOFFSET 0 -#define LED_CTRL_BLINK_FREQ_BLEN 2 -#define LED_CTRL_BLINK_FREQ_FLAG HSL_RW - - - /* Port Status Register */ -#define PORT_STATUS "ptsts" -#define PORT_STATUS_ID 29 -#define PORT_STATUS_OFFSET 0x0100 -#define PORT_STATUS_E_LENGTH 4 -#define PORT_STATUS_E_OFFSET 0x0100 -#define PORT_STATUS_NR_E 6 - -#define FLOW_LINK_EN "ptsts_flen" -#define PORT_STATUS_FLOW_LINK_EN_BOFFSET 12 -#define PORT_STATUS_FLOW_LINK_EN_BLEN 1 -#define PORT_STATUS_FLOW_LINK_EN_FLAG HSL_RW - - -#define LINK_ASYN_PAUSE "ptsts_lasynp" -#define PORT_STATUS_LINK_ASYN_PAUSE_BOFFSET 11 -#define PORT_STATUS_LINK_ASYN_PAUSE_BLEN 1 -#define PORT_STATUS_LINK_ASYN_PAUSE_FLAG HSL_RO - -#define LINK_PAUSE "ptsts_lpause" -#define PORT_STATUS_LINK_PAUSE_BOFFSET 10 -#define PORT_STATUS_LINK_PAUSE_BLEN 1 -#define PORT_STATUS_LINK_PAUSE_FLAG HSL_RO - -#define LINK_EN "ptsts_linken" -#define PORT_STATUS_LINK_EN_BOFFSET 9 -#define PORT_STATUS_LINK_EN_BLEN 1 -#define PORT_STATUS_LINK_EN_FLAG HSL_RW - -#define LINK "ptsts_ptlink" -#define PORT_STATUS_LINK_BOFFSET 8 -#define PORT_STATUS_LINK_BLEN 1 -#define PORT_STATUS_LINK_FLAG HSL_RO - -#define TX_HALF_FLOW_EN -#define PORT_STATUS_TX_HALF_FLOW_EN_BOFFSET 7 -#define PORT_STATUS_TX_HALF_FLOW_EN_BLEN 1 -#define PORT_STATUS_TX_HALF_FLOW_EN_FLAG HSL_RW - -#define DUPLEX_MODE "ptsts_dupmod" -#define PORT_STATUS_DUPLEX_MODE_BOFFSET 6 -#define PORT_STATUS_DUPLEX_MODE_BLEN 1 -#define PORT_STATUS_DUPLEX_MODE_FLAG HSL_RW - -#define RX_FLOW_EN "ptsts_rxfwen" -#define PORT_STATUS_RX_FLOW_EN_BOFFSET 5 -#define PORT_STATUS_RX_FLOW_EN_BLEN 1 -#define PORT_STATUS_RX_FLOW_EN_FLAG HSL_RW - -#define TX_FLOW_EN "ptsts_txfwen" -#define PORT_STATUS_TX_FLOW_EN_BOFFSET 4 -#define PORT_STATUS_TX_FLOW_EN_BLEN 1 -#define PORT_STATUS_TX_FLOW_EN_FLAG HSL_RW - -#define RXMAC_EN "ptsts_rxmacen" -#define PORT_STATUS_RXMAC_EN_BOFFSET 3 -#define PORT_STATUS_RXMAC_EN_BLEN 1 -#define PORT_STATUS_RXMAC_EN_FLAG HSL_RW - -#define TXMAC_EN "ptsts_txmacen" -#define PORT_STATUS_TXMAC_EN_BOFFSET 2 -#define PORT_STATUS_TXMAC_EN_BLEN 1 -#define PORT_STATUS_TXMAC_EN_FLAG HSL_RW - -#define SPEED_MODE "ptsts_speed" -#define PORT_STATUS_SPEED_MODE_BOFFSET 0 -#define PORT_STATUS_SPEED_MODE_BLEN 2 -#define PORT_STATUS_SPEED_MODE_FLAG HSL_RW - - - /* Port Control Register */ -#define PORT_CTL "pctl" -#define PORT_CTL_ID 30 -#define PORT_CTL_OFFSET 0x0104 -#define PORT_CTL_E_LENGTH 4 -#define PORT_CTL_E_OFFSET 0x0100 -#define PORT_CTL_NR_E 6 - -#define LEAVE_EN "pctl_leaveen" -#define PORT_CTL_LEAVE_EN_BOFFSET 21 -#define PORT_CTL_LEAVE_EN_BLEN 1 -#define PORT_CTL_LEAVE_EN_FLAG HSL_RW - -#define JOIN_EN "pctl_joinen" -#define PORT_CTL_JOIN_EN_BOFFSET 20 -#define PORT_CTL_JOIN_EN_BLEN 1 -#define PORT_CTL_JOIN_EN_FLAG HSL_RW - -#define DHCP_EN "pctl_dhcpen" -#define PORT_CTL_DHCP_EN_BOFFSET 19 -#define PORT_CTL_DHCP_EN_BLEN 1 -#define PORT_CTL_DHCP_EN_FLAG HSL_RW - -#define ING_MIRROR_EN "pctl_ingmiren" -#define PORT_CTL_ING_MIRROR_EN_BOFFSET 17 -#define PORT_CTL_ING_MIRROR_EN_BLEN 1 -#define PORT_CTL_ING_MIRROR_EN_FLAG HSL_RW - -#define EG_MIRROR_EN "pctl_egmiren" -#define PORT_CTL_EG_MIRROR_EN_BOFFSET 16 -#define PORT_CTL_EG_MIRROR_EN_BLEN 1 -#define PORT_CTL_EG_MIRROR_EN_FLAG HSL_RW - -#define DTAG_EN "pctl_dtagen" -#define PORT_CTL_DTAG_EN_BOFFSET 15 -#define PORT_CTL_DTAG_EN_BLEN 1 -#define PORT_CTL_DTAG_EN_FLAG HSL_RW - -#define LEARN_EN "pctl_learnen" -#define PORT_CTL_LEARN_EN_BOFFSET 14 -#define PORT_CTL_LEARN_EN_BLEN 1 -#define PORT_CTL_LEARN_EN_FLAG HSL_RW - -#define SINGLE_VLAN_EN "pctl_svlanen" -#define PORT_CTL_SINGLE_VLAN_EN_BOFFSET 13 -#define PORT_CTL_SINGLE_VLAN_EN_BLEN 1 -#define PORT_CTL_SINGLE_VLAN_EN_FLAG HSL_RW - -#define MAC_LOOP_BACK "pctl_maclp" -#define PORT_CTL_MAC_LOOP_BACK_BOFFSET 12 -#define PORT_CTL_MAC_LOOP_BACK_BLEN 1 -#define PORT_CTL_MAC_LOOP_BACK_FLAG HSL_RW - -#define HEAD_EN "pctl_headen" -#define PORT_CTL_HEAD_EN_BOFFSET 11 -#define PORT_CTL_HEAD_EN_BLEN 1 -#define PORT_CTL_HEAD_EN_FLAG HSL_RW - -#define IGMP_MLD_EN "pctl_imlden" -#define PORT_CTL_IGMP_MLD_EN_BOFFSET 10 -#define PORT_CTL_IGMP_MLD_EN_BLEN 1 -#define PORT_CTL_IGMP_MLD_EN_FLAG HSL_RW - -#define EG_VLAN_MODE "pctl_egvmode" -#define PORT_CTL_EG_VLAN_MODE_BOFFSET 8 -#define PORT_CTL_EG_VLAN_MODE_BLEN 2 -#define PORT_CTL_EG_VLAN_MODE_FLAG HSL_RW - -#define LEARN_ONE_LOCK "pctl_lonelck" -#define PORT_CTL_LEARN_ONE_LOCK_BOFFSET 7 -#define PORT_CTL_LEARN_ONE_LOCK_BLEN 1 -#define PORT_CTL_LEARN_ONE_LOCK_FLAG HSL_RW - -#define PORT_LOCK_EN "pctl_locken" -#define PORT_CTL_PORT_LOCK_EN_BOFFSET 6 -#define PORT_CTL_PORT_LOCK_EN_BLEN 1 -#define PORT_CTL_PORT_LOCK_EN_FLAG HSL_RW - -#define LOCK_DROP_EN "pctl_dropen" -#define PORT_CTL_LOCK_DROP_EN_BOFFSET 5 -#define PORT_CTL_LOCK_DROP_EN_BLEN 1 -#define PORT_CTL_LOCK_DROP_EN_FLAG HSL_RW - -#define PORT_STATE "pctl_pstate" -#define PORT_CTL_PORT_STATE_BOFFSET 0 -#define PORT_CTL_PORT_STATE_BLEN 3 -#define PORT_CTL_PORT_STATE_FLAG HSL_RW - - - /* Port Based Vlan Register */ -#define PORT_BASE_VLAN "pbvlan" -#define PORT_BASE_VLAN_ID 31 -#define PORT_BASE_VLAN_OFFSET 0x0108 -#define PORT_BASE_VLAN_E_LENGTH 4 -#define PORT_BASE_VLAN_E_OFFSET 0x0100 -#define PORT_BASE_VLAN_NR_E 6 - -#define DOT1Q_MODE "pbvlan_8021q" -#define PORT_BASE_VLAN_DOT1Q_MODE_BOFFSET 30 -#define PORT_BASE_VLAN_DOT1Q_MODE_BLEN 2 -#define PORT_BASE_VLAN_DOT1Q_MODE_FLAG HSL_RW - -#define ING_PRI "pbvlan_ingpri" -#define PORT_BASE_VLAN_ING_PRI_BOFFSET 27 -#define PORT_BASE_VLAN_ING_PRI_BLEN 3 -#define PORT_BASE_VLAN_ING_PRI_FLAG HSL_RW - -#define FORCE_PVLAN "pbvlan_fpvlan" -#define PORT_BASE_VLAN_FORCE_PVLAN_BOFFSET 26 -#define PORT_BASE_VLAN_FORCE_PVLAN_BLEN 1 -#define PORT_BASE_VLAN_FORCE_PVLAN_FLAG HSL_RW - -#define PORT_VID_MEM "pbvlan_pvidm" -#define PORT_BASE_VLAN_PORT_VID_MEM_BOFFSET 16 -#define PORT_BASE_VLAN_PORT_VID_MEM_BLEN 6 -#define PORT_BASE_VLAN_PORT_VID_MEM_FLAG HSL_RW - -#define ARP_LEAKY_EN "pbvlan_alen" -#define PORT_BASE_VLAN_ARP_LEAKY_EN_BOFFSET 15 -#define PORT_BASE_VLAN_ARP_LEAKY_EN_BLEN 1 -#define PORT_BASE_VLAN_ARP_LEAKY_EN_FLAG HSL_RW - -#define UNI_LEAKY_EN "pbvlan_ulen" -#define PORT_BASE_VLAN_UNI_LEAKY_EN_BOFFSET 14 -#define PORT_BASE_VLAN_UNI_LEAKY_EN_BLEN 1 -#define PORT_BASE_VLAN_UNI_LEAKY_EN_FLAG HSL_RW - -#define MUL_LEAKY_EN "pbvlan_mlen" -#define PORT_BASE_VLAN_MUL_LEAKY_EN_BOFFSET 13 -#define PORT_BASE_VLAN_MUL_LEAKY_EN_BLEN 1 -#define PORT_BASE_VLAN_MUL_LEAKY_EN_FLAG HSL_RW - -#define FORCE_DEF_VID "pbvlan_fdvid" -#define PORT_BASE_VLAN_FORCE_DEF_VID_BOFFSET 12 -#define PORT_BASE_VLAN_FORCE_DEF_VID_BLEN 1 -#define PORT_BASE_VLAN_FORCE_DEF_VID_FLAG HSL_RW - -#define PORT_VID "pbvlan_ptvid" -#define PORT_BASE_VLAN_PORT_VID_BOFFSET 0 -#define PORT_BASE_VLAN_PORT_VID_BLEN 12 -#define PORT_BASE_VLAN_PORT_VID_FLAG HSL_RW - - - /* Port Rate Limit0 Register */ -#define RATE_LIMIT0 "rlmt0" -#define RATE_LIMIT0_ID 32 -#define RATE_LIMIT0_OFFSET 0x010C -#define RATE_LIMIT0_E_LENGTH 4 -#define RATE_LIMIT0_E_OFFSET 0x0100 -#define RATE_LIMIT0_NR_E 6 - -#define ADD_RATE_BYTE "rlmt_addbyte" -#define RATE_LIMIT0_ADD_RATE_BYTE_BOFFSET 24 -#define RATE_LIMIT0_ADD_RATE_BYTE_BLEN 8 -#define RATE_LIMIT0_ADD_RATE_BYTE_FLAG HSL_RW - -#define EG_RATE_EN "rlmt_egen" -#define RATE_LIMIT0_EG_RATE_EN_BOFFSET 23 -#define RATE_LIMIT0_EG_RATE_EN_BLEN 1 -#define RATE_LIMIT0_EG_RATE_EN_FLAG HSL_RW - -#define EG_MNG_RATE_EN "rlmt_egmngen" -#define RATE_LIMIT0_EG_MNG_RATE_EN_BOFFSET 22 -#define RATE_LIMIT0_EG_MNG_RATE_EN_BLEN 1 -#define RATE_LIMIT0_EG_MNG_RATE_EN_FLAG HSL_RW - -#define IN_MNG_RATE_EN "rlmt_inmngen" -#define RATE_LIMIT0_IN_MNG_RATE_EN_BOFFSET 21 -#define RATE_LIMIT0_IN_MNG_RATE_EN_BLEN 1 -#define RATE_LIMIT0_IN_MNG_RATE_EN_FLAG HSL_RW - -#define IN_MUL_RATE_EN "rlmt_inmulen" -#define RATE_LIMIT0_IN_MUL_RATE_EN_BOFFSET 20 -#define RATE_LIMIT0_IN_MUL_RATE_EN_BLEN 1 -#define RATE_LIMIT0_IN_MUL_RATE_EN_FLAG HSL_RW - -#define ING_RATE "rlmt_ingrate" -#define RATE_LIMIT0_ING_RATE_BOFFSET 0 -#define RATE_LIMIT0_ING_RATE_BLEN 15 -#define RATE_LIMIT0_ING_RATE_FLAG HSL_RW - - - /* Priority Control Register */ -#define PRI_CTL "prctl" -#define PRI_CTL_ID 33 -#define PRI_CTL_OFFSET 0x0110 -#define PRI_CTL_E_LENGTH 4 -#define PRI_CTL_E_OFFSET 0x0100 -#define PRI_CTL_NR_E 6 - -#define PORT_PRI_EN "prctl_ptprien" -#define PRI_CTL_PORT_PRI_EN_BOFFSET 19 -#define PRI_CTL_PORT_PRI_EN_BLEN 1 -#define PRI_CTL_PORT_PRI_EN_FLAG HSL_RW - -#define DA_PRI_EN "prctl_daprien" -#define PRI_CTL_DA_PRI_EN_BOFFSET 18 -#define PRI_CTL_DA_PRI_EN_BLEN 1 -#define PRI_CTL_DA_PRI_EN_FLAG HSL_RW - -#define VLAN_PRI_EN "prctl_vprien" -#define PRI_CTL_VLAN_PRI_EN_BOFFSET 17 -#define PRI_CTL_VLAN_PRI_EN_BLEN 1 -#define PRI_CTL_VLAN_PRI_EN_FLAG HSL_RW - -#define IP_PRI_EN "prctl_ipprien" -#define PRI_CTL_IP_PRI_EN_BOFFSET 16 -#define PRI_CTL_IP_PRI_EN_BLEN 1 -#define PRI_CTL_IP_PRI_EN_FLAG HSL_RW - -#define DA_PRI_SEL "prctl_dapris" -#define PRI_CTL_DA_PRI_SEL_BOFFSET 6 -#define PRI_CTL_DA_PRI_SEL_BLEN 2 -#define PRI_CTL_DA_PRI_SEL_FLAG HSL_RW - -#define VLAN_PRI_SEL "prctl_vpris" -#define PRI_CTL_VLAN_PRI_SEL_BOFFSET 4 -#define PRI_CTL_VLAN_PRI_SEL_BLEN 2 -#define PRI_CTL_VLAN_PRI_SEL_FLAG HSL_RW - -#define IP_PRI_SEL "prctl_ippris" -#define PRI_CTL_IP_PRI_SEL_BOFFSET 2 -#define PRI_CTL_IP_PRI_SEL_BLEN 2 -#define PRI_CTL_IP_PRI_SEL_FLAG HSL_RW - -#define PORT_PRI_SEL "prctl_ptpris" -#define PRI_CTL_PORT_PRI_SEL_BOFFSET 0 -#define PRI_CTL_PORT_PRI_SEL_BLEN 2 -#define PRI_CTL_PORT_PRI_SEL_FLAG HSL_RW - - - /* Storm Control Register */ -#define STORM_CTL "sctrl" -#define STORM_CTL_ID 33 -#define STORM_CTL_OFFSET 0x0114 -#define STORM_CTL_E_LENGTH 4 -#define STORM_CTL_E_OFFSET 0x0100 -#define STORM_CTL_NR_E 6 - -#define UNIT "sctrl_unit" -#define STORM_CTL_UNIT_BOFFSET 24 -#define STORM_CTL_UNIT_BLEN 2 -#define STORM_CTL_UNIT_FLAG HSL_RW - -#define MUL_EN "sctrl_mulen" -#define STORM_CTL_MUL_EN_BOFFSET 10 -#define STORM_CTL_MUL_EN_BLEN 1 -#define STORM_CTL_MUL_EN_FLAG HSL_RW - -#define UNI_EN "sctrl_unien" -#define STORM_CTL_UNI_EN_BOFFSET 9 -#define STORM_CTL_UNI_EN_BLEN 1 -#define STORM_CTL_UNI_EN_FLAG HSL_RW - -#define BRO_EN "sctrl_broen" -#define STORM_CTL_BRO_EN_BOFFSET 8 -#define STORM_CTL_BRO_EN_BLEN 1 -#define STORM_CTL_BRO_EN_FLAG HSL_RW - -#define RATE "sctrl_rate" -#define STORM_CTL_RATE_BOFFSET 0 -#define STORM_CTL_RATE_BLEN 4 -#define STORM_CTL_RATE_FLAG HSL_RW - - - /* Queue Control Register */ -#define QUEUE_CTL "qctl" -#define QUEUE_CTL_ID 34 -#define QUEUE_CTL_OFFSET 0x0118 -#define QUEUE_CTL_E_LENGTH 4 -#define QUEUE_CTL_E_OFFSET 0x0100 -#define QUEUE_CTL_NR_E 6 - -#define PORT_DESC_EN "qctl_pdescen" -#define QUEUE_CTL_PORT_DESC_EN_BOFFSET 25 -#define QUEUE_CTL_PORT_DESC_EN_BLEN 1 -#define QUEUE_CTL_PORT_DESC_EN_FLAG HSL_RW - -#define QUEUE_DESC_EN "qctl_qdescen" -#define QUEUE_CTL_QUEUE_DESC_EN_BOFFSET 24 -#define QUEUE_CTL_QUEUE_DESC_EN_BLEN 1 -#define QUEUE_CTL_QUEUE_DESC_EN_FLAG HSL_RW - -#define PORT_DESC_NR "qctl_pdscpnr" -#define QUEUE_CTL_PORT_DESC_NR_BOFFSET 16 -#define QUEUE_CTL_PORT_DESC_NR_BLEN 6 -#define QUEUE_CTL_PORT_DESC_NR_FLAG HSL_RW - -#define QUEUE3_DESC_NR "qctl_q3dscpnr" -#define QUEUE_CTL_QUEUE3_DESC_NR_BOFFSET 12 -#define QUEUE_CTL_QUEUE3_DESC_NR_BLEN 4 -#define QUEUE_CTL_QUEUE3_DESC_NR_FLAG HSL_RW - -#define QUEUE2_DESC_NR "qctl_q2dscpnr" -#define QUEUE_CTL_QUEUE2_DESC_NR_BOFFSET 8 -#define QUEUE_CTL_QUEUE2_DESC_NR_BLEN 4 -#define QUEUE_CTL_QUEUE2_DESC_NR_FLAG HSL_RW - -#define QUEUE1_DESC_NR "qctl_q1dscpnr" -#define QUEUE_CTL_QUEUE1_DESC_NR_BOFFSET 4 -#define QUEUE_CTL_QUEUE1_DESC_NR_BLEN 4 -#define QUEUE_CTL_QUEUE1_DESC_NR_FLAG HSL_RW - -#define QUEUE0_DESC_NR "qctl_q0dscpnr" -#define QUEUE_CTL_QUEUE0_DESC_NR_BOFFSET 0 -#define QUEUE_CTL_QUEUE0_DESC_NR_BLEN 4 -#define QUEUE_CTL_QUEUE0_DESC_NR_FLAG HSL_RW - - - /* Port Rate Limit1 Register */ -#define RATE_LIMIT1 "rlmt1" -#define RATE_LIMIT1_ID 32 -#define RATE_LIMIT1_OFFSET 0x011C -#define RATE_LIMIT1_E_LENGTH 4 -#define RATE_LIMIT1_E_OFFSET 0x0100 -#define RATE_LIMIT1_NR_E 6 - -#define EG_Q1_RATE "rlmt_egq1rate" -#define RATE_LIMIT1_EG_Q1_RATE_BOFFSET 16 -#define RATE_LIMIT1_EG_Q1_RATE_BLEN 15 -#define RATE_LIMIT1_EG_Q1_RATE_FLAG HSL_RW - -#define EG_Q0_RATE "rlmt_egq0rate" -#define RATE_LIMIT1_EG_Q0_RATE_BOFFSET 0 -#define RATE_LIMIT1_EG_Q0_RATE_BLEN 15 -#define RATE_LIMIT1_EG_Q0_RATE_FLAG HSL_RW - - - /* Port Rate Limit2 Register */ -#define RATE_LIMIT2 "rlmt2" -#define RATE_LIMIT2_ID 32 -#define RATE_LIMIT2_OFFSET 0x0120 -#define RATE_LIMIT2_E_LENGTH 4 -#define RATE_LIMIT2_E_OFFSET 0x0100 -#define RATE_LIMIT2_NR_E 6 - -#define EG_Q3_RATE "rlmt_egq3rate" -#define RATE_LIMIT2_EG_Q3_RATE_BOFFSET 16 -#define RATE_LIMIT2_EG_Q3_RATE_BLEN 15 -#define RATE_LIMIT2_EG_Q3_RATE_FLAG HSL_RW - -#define EG_Q2_RATE "rlmt_egq2rate" -#define RATE_LIMIT2_EG_Q2_RATE_BOFFSET 0 -#define RATE_LIMIT2_EG_Q2_RATE_BLEN 15 -#define RATE_LIMIT2_EG_Q2_RATE_FLAG HSL_RW - - - /* mib memory info */ -#define MIB_RXBROAD "RxBroad" -#define MIB_RXBROAD_ID 34 -#define MIB_RXBROAD_OFFSET 0x20000 -#define MIB_RXBROAD_E_LENGTH 4 -#define MIB_RXBROAD_E_OFFSET 0x100 -#define MIB_RXBROAD_NR_E 6 - -#define MIB_RXPAUSE "RxPause" -#define MIB_RXPAUSE_ID 35 -#define MIB_RXPAUSE_OFFSET 0x20004 -#define MIB_RXPAUSE_E_LENGTH 4 -#define MIB_RXPAUSE_E_OFFSET 0x100 -#define MIB_RXPAUSE_NR_E 6 - -#define MIB_RXMULTI "RxMulti" -#define MIB_RXMULTI_ID 36 -#define MIB_RXMULTI_OFFSET 0x20008 -#define MIB_RXMULTI_E_LENGTH 4 -#define MIB_RXMULTI_E_OFFSET 0x100 -#define MIB_RXMULTI_NR_E 6 - -#define MIB_RXFCSERR "RxFcsErr" -#define MIB_RXFCSERR_ID 37 -#define MIB_RXFCSERR_OFFSET 0x2000c -#define MIB_RXFCSERR_E_LENGTH 4 -#define MIB_RXFCSERR_E_OFFSET 0x100 -#define MIB_RXFCSERR_NR_E 6 - -#define MIB_RXALLIGNERR "RxAllignErr" -#define MIB_RXALLIGNERR_ID 38 -#define MIB_RXALLIGNERR_OFFSET 0x20010 -#define MIB_RXALLIGNERR_E_LENGTH 4 -#define MIB_RXALLIGNERR_E_OFFSET 0x100 -#define MIB_RXALLIGNERR_NR_E 6 - -#define MIB_RXRUNT "RxRunt" -#define MIB_RXRUNT_ID 39 -#define MIB_RXRUNT_OFFSET 0x20014 -#define MIB_RXRUNT_E_LENGTH 4 -#define MIB_RXRUNT_E_OFFSET 0x100 -#define MIB_RXRUNT_NR_E 6 - -#define MIB_RXFRAGMENT "RxFragment" -#define MIB_RXFRAGMENT_ID 40 -#define MIB_RXFRAGMENT_OFFSET 0x20018 -#define MIB_RXFRAGMENT_E_LENGTH 4 -#define MIB_RXFRAGMENT_E_OFFSET 0x100 -#define MIB_RXFRAGMENT_NR_E 6 - -#define MIB_RX64BYTE "Rx64Byte" -#define MIB_RX64BYTE_ID 41 -#define MIB_RX64BYTE_OFFSET 0x2001c -#define MIB_RX64BYTE_E_LENGTH 4 -#define MIB_RX64BYTE_E_OFFSET 0x100 -#define MIB_RX64BYTE_NR_E 6 - -#define MIB_RX128BYTE "Rx128Byte" -#define MIB_RX128BYTE_ID 42 -#define MIB_RX128BYTE_OFFSET 0x20020 -#define MIB_RX128BYTE_E_LENGTH 4 -#define MIB_RX128BYTE_E_OFFSET 0x100 -#define MIB_RX128BYTE_NR_E 6 - -#define MIB_RX256BYTE "Rx256Byte" -#define MIB_RX256BYTE_ID 43 -#define MIB_RX256BYTE_OFFSET 0x20024 -#define MIB_RX256BYTE_E_LENGTH 4 -#define MIB_RX256BYTE_E_OFFSET 0x100 -#define MIB_RX256BYTE_NR_E 6 - -#define MIB_RX512BYTE "Rx512Byte" -#define MIB_RX512BYTE_ID 44 -#define MIB_RX512BYTE_OFFSET 0x20028 -#define MIB_RX512BYTE_E_LENGTH 4 -#define MIB_RX512BYTE_E_OFFSET 0x100 -#define MIB_RX512BYTE_NR_E 6 - -#define MIB_RX1024BYTE "Rx1024Byte" -#define MIB_RX1024BYTE_ID 45 -#define MIB_RX1024BYTE_OFFSET 0x2002c -#define MIB_RX1024BYTE_E_LENGTH 4 -#define MIB_RX1024BYTE_E_OFFSET 0x100 -#define MIB_RX1024BYTE_NR_E 6 - -#define MIB_RX1518BYTE "Rx1518Byte" -#define MIB_RX1518BYTE_ID 45 -#define MIB_RX1518BYTE_OFFSET 0x20030 -#define MIB_RX1518BYTE_E_LENGTH 4 -#define MIB_RX1518BYTE_E_OFFSET 0x100 -#define MIB_RX1518BYTE_NR_E 6 - -#define MIB_RXMAXBYTE "RxMaxByte" -#define MIB_RXMAXBYTE_ID 46 -#define MIB_RXMAXBYTE_OFFSET 0x20034 -#define MIB_RXMAXBYTE_E_LENGTH 4 -#define MIB_RXMAXBYTE_E_OFFSET 0x100 -#define MIB_RXMAXBYTE_NR_E 6 - -#define MIB_RXTOOLONG "RxTooLong" -#define MIB_RXTOOLONG_ID 47 -#define MIB_RXTOOLONG_OFFSET 0x20038 -#define MIB_RXTOOLONG_E_LENGTH 4 -#define MIB_RXTOOLONG_E_OFFSET 0x100 -#define MIB_RXTOOLONG_NR_E 6 - -#define MIB_RXGOODBYTE_LO "RxGoodByteLo" -#define MIB_RXGOODBYTE_LO_ID 48 -#define MIB_RXGOODBYTE_LO_OFFSET 0x2003c -#define MIB_RXGOODBYTE_LO_E_LENGTH 4 -#define MIB_RXGOODBYTE_LO_E_OFFSET 0x100 -#define MIB_RXGOODBYTE_LO_NR_E 6 - -#define MIB_RXGOODBYTE_HI "RxGoodByteHi" -#define MIB_RXGOODBYTE_HI_ID 49 -#define MIB_RXGOODBYTE_HI_OFFSET 0x20040 -#define MIB_RXGOODBYTE_HI_E_LENGTH 4 -#define MIB_RXGOODBYTE_HI_E_OFFSET 0x100 -#define MIB_RXGOODBYTE_HI_NR_E 6 - -#define MIB_RXBADBYTE_LO "RxBadByteLo" -#define MIB_RXBADBYTE_LO_ID 50 -#define MIB_RXBADBYTE_LO_OFFSET 0x20044 -#define MIB_RXBADBYTE_LO_E_LENGTH 4 -#define MIB_RXBADBYTE_LO_E_OFFSET 0x100 -#define MIB_RXBADBYTE_LO_NR_E 6 - -#define MIB_RXBADBYTE_HI "RxBadByteHi" -#define MIB_RXBADBYTE_HI_ID 51 -#define MIB_RXBADBYTE_HI_OFFSET 0x20048 -#define MIB_RXBADBYTE_HI_E_LENGTH 4 -#define MIB_RXBADBYTE_HI_E_OFFSET 0x100 -#define MIB_RXBADBYTE_HI_NR_E 6 - -#define MIB_RXOVERFLOW "RxOverFlow" -#define MIB_RXOVERFLOW_ID 52 -#define MIB_RXOVERFLOW_OFFSET 0x2004c -#define MIB_RXOVERFLOW_E_LENGTH 4 -#define MIB_RXOVERFLOW_E_OFFSET 0x100 -#define MIB_RXOVERFLOW_NR_E 6 - -#define MIB_FILTERED "Filtered" -#define MIB_FILTERED_ID 53 -#define MIB_FILTERED_OFFSET 0x20050 -#define MIB_FILTERED_E_LENGTH 4 -#define MIB_FILTERED_E_OFFSET 0x100 -#define MIB_FILTERED_NR_E 6 - -#define MIB_TXBROAD "TxBroad" -#define MIB_TXBROAD_ID 54 -#define MIB_TXBROAD_OFFSET 0x20054 -#define MIB_TXBROAD_E_LENGTH 4 -#define MIB_TXBROAD_E_OFFSET 0x100 -#define MIB_TXBROAD_NR_E 6 - -#define MIB_TXPAUSE "TxPause" -#define MIB_TXPAUSE_ID 55 -#define MIB_TXPAUSE_OFFSET 0x20058 -#define MIB_TXPAUSE_E_LENGTH 4 -#define MIB_TXPAUSE_E_OFFSET 0x100 -#define MIB_TXPAUSE_NR_E 6 - -#define MIB_TXMULTI "TxMulti" -#define MIB_TXMULTI_ID 56 -#define MIB_TXMULTI_OFFSET 0x2005c -#define MIB_TXMULTI_E_LENGTH 4 -#define MIB_TXMULTI_E_OFFSET 0x100 -#define MIB_TXMULTI_NR_E 6 - -#define MIB_TXUNDERRUN "TxUnderRun" -#define MIB_TXUNDERRUN_ID 57 -#define MIB_TXUNDERRUN_OFFSET 0x20060 -#define MIB_TXUNDERRUN_E_LENGTH 4 -#define MIB_TXUNDERRUN_E_OFFSET 0x100 -#define MIB_TXUNDERRUN_NR_E 6 - -#define MIB_TX64BYTE "Tx64Byte" -#define MIB_TX64BYTE_ID 58 -#define MIB_TX64BYTE_OFFSET 0x20064 -#define MIB_TX64BYTE_E_LENGTH 4 -#define MIB_TX64BYTE_E_OFFSET 0x100 -#define MIB_TX64BYTE_NR_E 6 - -#define MIB_TX128BYTE "Tx128Byte" -#define MIB_TX128BYTE_ID 59 -#define MIB_TX128BYTE_OFFSET 0x20068 -#define MIB_TX128BYTE_E_LENGTH 4 -#define MIB_TX128BYTE_E_OFFSET 0x100 -#define MIB_TX128BYTE_NR_E 6 - -#define MIB_TX256BYTE "Tx256Byte" -#define MIB_TX256BYTE_ID 60 -#define MIB_TX256BYTE_OFFSET 0x2006c -#define MIB_TX256BYTE_E_LENGTH 4 -#define MIB_TX256BYTE_E_OFFSET 0x100 -#define MIB_TX256BYTE_NR_E 6 - -#define MIB_TX512BYTE "Tx512Byte" -#define MIB_TX512BYTE_ID 61 -#define MIB_TX512BYTE_OFFSET 0x20070 -#define MIB_TX512BYTE_E_LENGTH 4 -#define MIB_TX512BYTE_E_OFFSET 0x100 -#define MIB_TX512BYTE_NR_E 6 - -#define MIB_TX1024BYTE "Tx1024Byte" -#define MIB_TX1024BYTE_ID 62 -#define MIB_TX1024BYTE_OFFSET 0x20074 -#define MIB_TX1024BYTE_E_LENGTH 4 -#define MIB_TX1024BYTE_E_OFFSET 0x100 -#define MIB_TX1024BYTE_NR_E 6 - -#define MIB_TX1518BYTE "Tx1518Byte" -#define MIB_TX1518BYTE_ID 62 -#define MIB_TX1518BYTE_OFFSET 0x20078 -#define MIB_TX1518BYTE_E_LENGTH 4 -#define MIB_TX1518BYTE_E_OFFSET 0x100 -#define MIB_TX1518BYTE_NR_E 6 - -#define MIB_TXMAXBYTE "TxMaxByte" -#define MIB_TXMAXBYTE_ID 63 -#define MIB_TXMAXBYTE_OFFSET 0x2007c -#define MIB_TXMAXBYTE_E_LENGTH 4 -#define MIB_TXMAXBYTE_E_OFFSET 0x100 -#define MIB_TXMAXBYTE_NR_E 6 - -#define MIB_TXOVERSIZE "TxOverSize" -#define MIB_TXOVERSIZE_ID 64 -#define MIB_TXOVERSIZE_OFFSET 0x20080 -#define MIB_TXOVERSIZE_E_LENGTH 4 -#define MIB_TXOVERSIZE_E_OFFSET 0x100 -#define MIB_TXOVERSIZE_NR_E 6 - -#define MIB_TXBYTE_LO "TxByteLo" -#define MIB_TXBYTE_LO_ID 65 -#define MIB_TXBYTE_LO_OFFSET 0x20084 -#define MIB_TXBYTE_LO_E_LENGTH 4 -#define MIB_TXBYTE_LO_E_OFFSET 0x100 -#define MIB_TXBYTE_LO_NR_E 6 - -#define MIB_TXBYTE_HI "TxByteHi" -#define MIB_TXBYTE_HI_ID 66 -#define MIB_TXBYTE_HI_OFFSET 0x20088 -#define MIB_TXBYTE_HI_E_LENGTH 4 -#define MIB_TXBYTE_HI_E_OFFSET 0x100 -#define MIB_TXBYTE_HI_NR_E 6 - -#define MIB_TXCOLLISION "TxCollision" -#define MIB_TXCOLLISION_ID 67 -#define MIB_TXCOLLISION_OFFSET 0x2008c -#define MIB_TXCOLLISION_E_LENGTH 4 -#define MIB_TXCOLLISION_E_OFFSET 0x100 -#define MIB_TXCOLLISION_NR_E 6 - -#define MIB_TXABORTCOL "TxAbortCol" -#define MIB_TXABORTCOL_ID 68 -#define MIB_TXABORTCOL_OFFSET 0x20090 -#define MIB_TXABORTCOL_E_LENGTH 4 -#define MIB_TXABORTCOL_E_OFFSET 0x100 -#define MIB_TXABORTCOL_NR_E 6 - -#define MIB_TXMULTICOL "TxMultiCol" -#define MIB_TXMULTICOL_ID 69 -#define MIB_TXMULTICOL_OFFSET 0x20094 -#define MIB_TXMULTICOL_E_LENGTH 4 -#define MIB_TXMULTICOL_E_OFFSET 0x100 -#define MIB_TXMULTICOL_NR_E 6 - -#define MIB_TXSINGALCOL "TxSingalCol" -#define MIB_TXSINGALCOL_ID 70 -#define MIB_TXSINGALCOL_OFFSET 0x20098 -#define MIB_TXSINGALCOL_E_LENGTH 4 -#define MIB_TXSINGALCOL_E_OFFSET 0x100 -#define MIB_TXSINGALCOL_NR_E 6 - -#define MIB_TXEXCDEFER "TxExcDefer" -#define MIB_TXEXCDEFER_ID 71 -#define MIB_TXEXCDEFER_OFFSET 0x2009c -#define MIB_TXEXCDEFER_E_LENGTH 4 -#define MIB_TXEXCDEFER_E_OFFSET 0x100 -#define MIB_TXEXCDEFER_NR_E 6 - -#define MIB_TXDEFER "TxDefer" -#define MIB_TXDEFER_ID 72 -#define MIB_TXDEFER_OFFSET 0x200a0 -#define MIB_TXDEFER_E_LENGTH 4 -#define MIB_TXDEFER_E_OFFSET 0x100 -#define MIB_TXDEFER_NR_E 6 - -#define MIB_TXLATECOL "TxLateCol" -#define MIB_TXLATECOL_ID 73 -#define MIB_TXLATECOL_OFFSET 0x200a4 -#define MIB_TXLATECOL_E_LENGTH 4 -#define MIB_TXLATECOL_E_OFFSET 0x100 -#define MIB_TXLATECOL_NR_E 6 - -#if 0 - /* mib info second mem block */ -#define MIB_RXBROAD_2 "RxBroad_2" -#define MIB_RXBROAD_2_ID 34 -#define MIB_RXBROAD_2_OFFSET (MIB_RXBROAD_OFFSET + 0x400) -#define MIB_RXBROAD_2_E_LENGTH 4 -#define MIB_RXBROAD_2_E_OFFSET 0xa8 -#define MIB_RXBROAD_2_NR_E 6 - -#define MIB_RXPAUSE_2 "RxPause_2" -#define MIB_RXPAUSE_2_ID 35 -#define MIB_RXPAUSE_2_OFFSET (MIB_RXPAUSE_OFFSET + 0x400) -#define MIB_RXPAUSE_2_E_LENGTH 4 -#define MIB_RXPAUSE_2_E_OFFSET 0xa8 -#define MIB_RXPAUSE_2_NR_E 6 - -#define MIB_RXMULTI_2 "RxMulti_2" -#define MIB_RXMULTI_2_ID 36 -#define MIB_RXMULTI_2_OFFSET (MIB_RXMULTI_OFFSET + 0x400) -#define MIB_RXMULTI_2_E_LENGTH 4 -#define MIB_RXMULTI_2_E_OFFSET 0xa8 -#define MIB_RXMULTI_2_NR_E 6 - -#define MIB_RXFCSERR_2 "RxFcsErr_2" -#define MIB_RXFCSERR_2_ID 37 -#define MIB_RXFCSERR_2_OFFSET (MIB_RXFCSERR_OFFSET + 0x400) -#define MIB_RXFCSERR_2_E_LENGTH 4 -#define MIB_RXFCSERR_2_E_OFFSET 0xa8 -#define MIB_RXFCSERR_2_NR_E 6 - -#define MIB_RXALLIGNERR_2 "RxAllignErr_2" -#define MIB_RXALLIGNERR_2_ID 38 -#define MIB_RXALLIGNERR_2_OFFSET (MIB_RXALLIGNERR_OFFSET + 0x400) -#define MIB_RXALLIGNERR_2_E_LENGTH 4 -#define MIB_RXALLIGNERR_2_E_OFFSET 0xa8 -#define MIB_RXALLIGNERR_2_NR_E 6 - -#define MIB_RXRUNT_2 "RxRunt_2" -#define MIB_RXRUNT_2_ID 39 -#define MIB_RXRUNT_2_OFFSET (MIB_RXRUNT_OFFSET + 0x400) -#define MIB_RXRUNT_2_E_LENGTH 4 -#define MIB_RXRUNT_2_E_OFFSET 0xa8 -#define MIB_RXRUNT_2_NR_E 6 - -#define MIB_RXFRAGMENT_2 "RxFragment_2" -#define MIB_RXFRAGMENT_2_ID 40 -#define MIB_RXFRAGMENT_2_OFFSET (MIB_RXFRAGMENT_OFFSET + 0x400) -#define MIB_RXFRAGMENT_2_E_LENGTH 4 -#define MIB_RXFRAGMENT_2_E_OFFSET 0xa8 -#define MIB_RXFRAGMENT_2_NR_E 6 - -#define MIB_RX64BYTE_2 "Rx64Byte_2" -#define MIB_RX64BYTE_2_ID 41 -#define MIB_RX64BYTE_2_OFFSET (MIB_RX64BYTE_OFFSET + 0x400) -#define MIB_RX64BYTE_2_E_LENGTH 4 -#define MIB_RX64BYTE_2_E_OFFSET 0xa8 -#define MIB_RX64BYTE_2_NR_E 6 - -#define MIB_RX128BYTE_2 "Rx128Byte_2" -#define MIB_RX128BYTE_2_ID 42 -#define MIB_RX128BYTE_2_OFFSET (MIB_RX128BYTE_OFFSET + 0x400) -#define MIB_RX128BYTE_2_E_LENGTH 4 -#define MIB_RX128BYTE_2_E_OFFSET 0xa8 -#define MIB_RX128BYTE_2_NR_E 6 - -#define MIB_RX256BYTE_2 "Rx256Byte_2" -#define MIB_RX256BYTE_2_ID 43 -#define MIB_RX256BYTE_2_OFFSET (MIB_RX256BYTE_OFFSET + 0x400) -#define MIB_RX256BYTE_2_E_LENGTH 4 -#define MIB_RX256BYTE_2_E_OFFSET 0xa8 -#define MIB_RX256BYTE_2_NR_E 6 - -#define MIB_RX512BYTE_2 "Rx512Byte_2" -#define MIB_RX512BYTE_2_ID 44 -#define MIB_RX512BYTE_2_OFFSET (MIB_RX512BYTE_OFFSET + 0x400) -#define MIB_RX512BYTE_2_E_LENGTH 4 -#define MIB_RX512BYTE_2_E_OFFSET 0xa8 -#define MIB_RX512BYTE_2_NR_E 6 - -#define MIB_RX1024BYTE_2 "Rx1024Byte_2" -#define MIB_RX1024BYTE_2_ID 45 -#define MIB_RX1024BYTE_2_OFFSET (MIB_RX1024BYTE_OFFSET + 0x400) -#define MIB_RX1024BYTE_2_E_LENGTH 4 -#define MIB_RX1024BYTE_2_E_OFFSET 0xa8 -#define MIB_RX1024BYTE_2_NR_E 6 - -#define MIB_RX1518BYTE_2 "Rx1518Byte_2" -#define MIB_RX1518BYTE_2_ID 45 -#define MIB_RX1518BYTE_2_OFFSET (MIB_RX1518BYTE_OFFSET + 0x400) -#define MIB_RX1518BYTE_2_E_LENGTH 4 -#define MIB_RX1518BYTE_2_E_OFFSET 0xa8 -#define MIB_RX1518BYTE_2_NR_E 6 - -#define MIB_RXMAXBYTE_2 "RxMaxByte_2" -#define MIB_RXMAXBYTE_2_ID 46 -#define MIB_RXMAXBYTE_2_OFFSET (MIB_RXMAXBYTE_OFFSET + 0x400) -#define MIB_RXMAXBYTE_2_E_LENGTH 4 -#define MIB_RXMAXBYTE_2_E_OFFSET 0xa8 -#define MIB_RXMAXBYTE_2_NR_E 6 - -#define MIB_RXTOOLONG_2 "RxTooLong_2" -#define MIB_RXTOOLONG_2_ID 47 -#define MIB_RXTOOLONG_2_OFFSET (MIB_RXTOOLONG_OFFSET + 0x400) -#define MIB_RXTOOLONG_2_E_LENGTH 4 -#define MIB_RXTOOLONG_2_E_OFFSET 0xa8 -#define MIB_RXTOOLONG_2_NR_E 6 - -#define MIB_RXGOODBYTE_LO_2 "RxGoodByteLo_2" -#define MIB_RXGOODBYTE_LO_2_ID 48 -#define MIB_RXGOODBYTE_LO_2_OFFSET (MIB_RXGOODBYTE_LO_OFFSET + 0x400) -#define MIB_RXGOODBYTE_LO_2_E_LENGTH 4 -#define MIB_RXGOODBYTE_LO_2_E_OFFSET 0xa8 -#define MIB_RXGOODBYTE_LO_2_NR_E 6 - -#define MIB_RXGOODBYTE_HI_2 "RxGoodByteHi_2" -#define MIB_RXGOODBYTE_HI_2_ID 49 -#define MIB_RXGOODBYTE_HI_2_OFFSET (MIB_RXGOODBYTE_HI_OFFSET + 0x400) -#define MIB_RXGOODBYTE_HI_2_E_LENGTH 4 -#define MIB_RXGOODBYTE_HI_2_E_OFFSET 0xa8 -#define MIB_RXGOODBYTE_HI_2_NR_E 6 - -#define MIB_RXBADBYTE_LO_2 "RxBadByteLo_2" -#define MIB_RXBADBYTE_LO_2_ID 50 -#define MIB_RXBADBYTE_LO_2_OFFSET (MIB_RXBADBYTE_LO_OFFSET + 0x400) -#define MIB_RXBADBYTE_LO_2_E_LENGTH 4 -#define MIB_RXBADBYTE_LO_2_E_OFFSET 0xa8 -#define MIB_RXBADBYTE_LO_2_NR_E 6 - -#define MIB_RXBADBYTE_HI_2 "RxBadByteHi_2" -#define MIB_RXBADBYTE_HI_2_ID 51 -#define MIB_RXBADBYTE_HI_2_OFFSET (MIB_RXBADBYTE_HI_OFFSET + 0x400) -#define MIB_RXBADBYTE_HI_2_E_LENGTH 4 -#define MIB_RXBADBYTE_HI_2_E_OFFSET 0xa8 -#define MIB_RXBADBYTE_HI_2_NR_E 6 - -#define MIB_RXOVERFLOW_2 "RxOverFlow_2" -#define MIB_RXOVERFLOW_2_ID 52 -#define MIB_RXOVERFLOW_2_OFFSET (MIB_RXOVERFLOW_OFFSET + 0x400) -#define MIB_RXOVERFLOW_2_E_LENGTH 4 -#define MIB_RXOVERFLOW_2_E_OFFSET 0xa8 -#define MIB_RXOVERFLOW_2_NR_E 6 - -#define MIB_FILTERED_2 "Filtered_2" -#define MIB_FILTERED_2_ID 53 -#define MIB_FILTERED_2_OFFSET (MIB_FILTERED_OFFSET + 0x400) -#define MIB_FILTERED_2_E_LENGTH 4 -#define MIB_FILTERED_2_E_OFFSET 0xa8 -#define MIB_FILTERED_2_NR_E 6 - -#define MIB_TXBROAD_2 "TxBroad_2" -#define MIB_TXBROAD_2_ID 54 -#define MIB_TXBROAD_2_OFFSET (MIB_TXBROAD_OFFSET + 0x400) -#define MIB_TXBROAD_2_E_LENGTH 4 -#define MIB_TXBROAD_2_E_OFFSET 0xa8 -#define MIB_TXBROAD_2_NR_E 6 - -#define MIB_TXPAUSE_2 "TxPause_2" -#define MIB_TXPAUSE_2_ID 55 -#define MIB_TXPAUSE_2_OFFSET (MIB_TXPAUSE_OFFSET + 0x400) -#define MIB_TXPAUSE_2_E_LENGTH 4 -#define MIB_TXPAUSE_2_E_OFFSET 0xa8 -#define MIB_TXPAUSE_2_NR_E 6 - -#define MIB_TXMULTI_2 "TxMulti_2" -#define MIB_TXMULTI_2_ID 56 -#define MIB_TXMULTI_2_OFFSET (MIB_TXMULTI_OFFSET + 0x400) -#define MIB_TXMULTI_2_E_LENGTH 4 -#define MIB_TXMULTI_2_E_OFFSET 0xa8 -#define MIB_TXMULTI_2_NR_E 6 - -#define MIB_TXUNDERRUN_2 "TxUnderRun_2" -#define MIB_TXUNDERRUN_2_ID 57 -#define MIB_TXUNDERRUN_2_OFFSET (MIB_TXUNDERRUN_OFFSET + 0x400) -#define MIB_TXUNDERRUN_2_E_LENGTH 4 -#define MIB_TXUNDERRUN_2_E_OFFSET 0xa8 -#define MIB_TXUNDERRUN_2_NR_E 6 - -#define MIB_TX64BYTE_2 "Tx64Byte_2" -#define MIB_TX64BYTE_2_ID 58 -#define MIB_TX64BYTE_2_OFFSET (MIB_TX64BYTE_OFFSET + 0x400) -#define MIB_TX64BYTE_2_E_LENGTH 4 -#define MIB_TX64BYTE_2_E_OFFSET 0xa8 -#define MIB_TX64BYTE_2_NR_E 6 - -#define MIB_TX128BYTE_2 "Tx128Byte_2" -#define MIB_TX128BYTE_2_ID 59 -#define MIB_TX128BYTE_2_OFFSET (MIB_TX128BYTE_OFFSET + 0x400) -#define MIB_TX128BYTE_2_E_LENGTH 4 -#define MIB_TX128BYTE_2_E_OFFSET 0xa8 -#define MIB_TX128BYTE_2_NR_E 6 - -#define MIB_TX256BYTE_2 "Tx256Byte_2" -#define MIB_TX256BYTE_2_ID 60 -#define MIB_TX256BYTE_2_OFFSET (MIB_TX256BYTE_OFFSET + 0x400) -#define MIB_TX256BYTE_2_E_LENGTH 4 -#define MIB_TX256BYTE_2_E_OFFSET 0xa8 -#define MIB_TX256BYTE_2_NR_E 6 - -#define MIB_TX512BYTE_2 "Tx512Byte_2" -#define MIB_TX512BYTE_2_ID 61 -#define MIB_TX512BYTE_2_OFFSET (MIB_TX512BYTE_OFFSET + 0x400) -#define MIB_TX512BYTE_2_E_LENGTH 4 -#define MIB_TX512BYTE_2_E_OFFSET 0xa8 -#define MIB_TX512BYTE_2_NR_E 6 - -#define MIB_TX1024BYTE_2 "Tx1024Byte_2" -#define MIB_TX1024BYTE_2_ID 62 -#define MIB_TX1024BYTE_2_OFFSET (MIB_TX1024BYTE_OFFSET + 0x400) -#define MIB_TX1024BYTE_2_E_LENGTH 4 -#define MIB_TX1024BYTE_2_E_OFFSET 0xa8 -#define MIB_TX1024BYTE_2_NR_E 6 - -#define MIB_TX1518BYTE_2 "Tx1518Byte_2" -#define MIB_TX1518BYTE_2_ID 62 -#define MIB_TX1518BYTE_2_OFFSET (MIB_TX1518BYTE_OFFSET + 0x400) -#define MIB_TX1518BYTE_2_E_LENGTH 4 -#define MIB_TX1518BYTE_2_E_OFFSET 0xa8 -#define MIB_TX1518BYTE_2_NR_E 6 - -#define MIB_TXMAXBYTE_2 "TxMaxByte_2" -#define MIB_TXMAXBYTE_2_ID 63 -#define MIB_TXMAXBYTE_2_OFFSET (MIB_TXMAXBYTE_OFFSET + 0x400) -#define MIB_TXMAXBYTE_2_E_LENGTH 4 -#define MIB_TXMAXBYTE_2_E_OFFSET 0xa8 -#define MIB_TXMAXBYTE_2_NR_E 6 - -#define MIB_TXOVERSIZE_2 "TxOverSize_2" -#define MIB_TXOVERSIZE_2_ID 64 -#define MIB_TXOVERSIZE_2_OFFSET (MIB_TXOVERSIZE_OFFSET + 0x400) -#define MIB_TXOVERSIZE_2_E_LENGTH 4 -#define MIB_TXOVERSIZE_2_E_OFFSET 0xa8 -#define MIB_TXOVERSIZE_2_NR_E 6 - -#define MIB_TXBYTE_LO_2 "TxByteLo_2" -#define MIB_TXBYTE_LO_2_ID 65 -#define MIB_TXBYTE_LO_2_OFFSET (MIB_TXBYTE_LO_OFFSET + 0x400) -#define MIB_TXBYTE_LO_2_E_LENGTH 4 -#define MIB_TXBYTE_LO_2_E_OFFSET 0xa8 -#define MIB_TXBYTE_LO_2_NR_E 6 - -#define MIB_TXBYTE_HI_2 "TxByteHi_2" -#define MIB_TXBYTE_HI_2_ID 66 -#define MIB_TXBYTE_HI_2_OFFSET (MIB_TXBYTE_HI_OFFSET + 0x400) -#define MIB_TXBYTE_HI_2_E_LENGTH 4 -#define MIB_TXBYTE_HI_2_E_OFFSET 0xa8 -#define MIB_TXBYTE_HI_2_NR_E 6 - -#define MIB_TXCOLLISION_2 "TxCollision_2" -#define MIB_TXCOLLISION_2_ID 67 -#define MIB_TXCOLLISION_2_OFFSET (MIB_TXCOLLISION_OFFSET + 0x400) -#define MIB_TXCOLLISION_2_E_LENGTH 4 -#define MIB_TXCOLLISION_2_E_OFFSET 0xa8 -#define MIB_TXCOLLISION_2_NR_E 6 - -#define MIB_TXABORTCOL_2 "TxAbortCol_2" -#define MIB_TXABORTCOL_2_ID 68 -#define MIB_TXABORTCOL_2_OFFSET (MIB_TXABORTCOL_OFFSET + 0x400) -#define MIB_TXABORTCOL_2_E_LENGTH 4 -#define MIB_TXABORTCOL_2_E_OFFSET 0xa8 -#define MIB_TXABORTCOL_2_NR_E 6 - -#define MIB_TXMULTICOL_2 "TxMultiCol_2" -#define MIB_TXMULTICOL_2_ID 69 -#define MIB_TXMULTICOL_2_OFFSET (MIB_TXMULTICOL_OFFSET + 0x400) -#define MIB_TXMULTICOL_2_E_LENGTH 4 -#define MIB_TXMULTICOL_2_E_OFFSET 0xa8 -#define MIB_TXMULTICOL_2_NR_E 6 - -#define MIB_TXSINGALCOL_2 "TxSingalCol_2" -#define MIB_TXSINGALCOL_2_ID 70 -#define MIB_TXSINGALCOL_2_OFFSET (MIB_TXSINGALCOL_OFFSET + 0x400) -#define MIB_TXSINGALCOL_2_E_LENGTH 4 -#define MIB_TXSINGALCOL_2_E_OFFSET 0xa8 -#define MIB_TXSINGALCOL_2_NR_E 6 - -#define MIB_TXEXCDEFER_2 "TxExcDefer_2" -#define MIB_TXEXCDEFER_2_ID 71 -#define MIB_TXEXCDEFER_2_OFFSET (MIB_TXEXCDEFER_OFFSET + 0x400) -#define MIB_TXEXCDEFER_2_E_LENGTH 4 -#define MIB_TXEXCDEFER_2_E_OFFSET 0xa8 -#define MIB_TXEXCDEFER_2_NR_E 6 - -#define MIB_TXDEFER_2 "TxDefer_2" -#define MIB_TXDEFER_2_ID 72 -#define MIB_TXDEFER_2_OFFSET (MIB_TXDEFER_OFFSET + 0x400) -#define MIB_TXDEFER_2_E_LENGTH 4 -#define MIB_TXDEFER_2_E_OFFSET 0xa8 -#define MIB_TXDEFER_2_NR_E 6 - -#define MIB_TXLATECOL_2 "TxLateCol_2" -#define MIB_TXLATECOL_2_ID 73 -#define MIB_TXLATECOL_2_OFFSET (MIB_TXLATECOL_OFFSET + 0x400) -#define MIB_TXLATECOL_2_E_LENGTH 4 -#define MIB_TXLATECOL_2_E_OFFSET 0xa8 -#define MIB_TXLATECOL_2_NR_E 6 -#endif - -#define ACL_RSLT "aclact" -#define ACL_RSLT_ID 13 -#define ACL_RSLT_OFFSET 0x58000 -#define ACL_RSLT_E_LENGTH 4 -#define ACL_RSLT_E_OFFSET 0x20 -#define ACL_RSLT_NR_E 32 - -#define RDTCPU "aclact_rdtpu" -#define ACL_RSLT_RDTCPU_BOFFSET 31 -#define ACL_RSLT_RDTCPU_BLEN 1 -#define ACL_RSLT_RDTCPU_FLAG HSL_RW - -#define CPYCPU "aclact_cpcpu" -#define ACL_RSLT_CPYCPU_BOFFSET 30 -#define ACL_RSLT_CPYCPU_BLEN 1 -#define ACL_RSLT_CPYCPU_FLAG HSL_RW - -#define MIRR_EN "aclact_mirr" -#define ACL_RSLT_MIRR_EN_BOFFSET 29 -#define ACL_RSLT_MIRR_EN_BLEN 1 -#define ACL_RSLT_MIRR_EN_FLAG HSL_RW - -#define STAG_CHG_EN "aclact_rdcpu" -#define ACL_RSLT_STAG_CHG_EN_BOFFSET 28 -#define ACL_RSLT_STAG_CHG_EN_BLEN 1 -#define ACL_RSLT_STAG_CHG_EN_FLAG HSL_RW - -#define VID_MEM_EN "aclact_rdcpu" -#define ACL_RSLT_VID_MEM_EN_BOFFSET 27 -#define ACL_RSLT_VID_MEM_EN_BLEN 1 -#define ACL_RSLT_VID_MEM_EN_FLAG HSL_RW - -#define DES_PORT_EN "aclact_rdcpu" -#define ACL_RSLT_DES_PORT_EN_BOFFSET 26 -#define ACL_RSLT_DES_PORT_EN_BLEN 1 -#define ACL_RSLT_DES_PORT_EN_FLAG HSL_RW - -#define PORT_MEM "aclact_rdcpu" -#define ACL_RSLT_PORT_MEM_BOFFSET 20 -#define ACL_RSLT_PORT_MEM_BLEN 6 -#define ACL_RSLT_PORT_MEM_FLAG HSL_RW - -#define REMARK_PRI_QU "aclact_rdcpu" -#define ACL_RSLT_REMARK_PRI_QU_BOFFSET 19 -#define ACL_RSLT_REMARK_PRI_QU_BLEN 1 -#define ACL_RSLT_REMARK_PRI_QU_FLAG HSL_RW - -#define DOT1P "aclact_rdcpu" -#define ACL_RSLT_DOT1P_BOFFSET 16 -#define ACL_RSLT_DOT1P_BLEN 3 -#define ACL_RSLT_DOT1P_FLAG HSL_RW - -#define PRI_QU "aclact_rdcpu" -#define ACL_RSLT_PRI_QU_BOFFSET 14 -#define ACL_RSLT_PRI_QU_BLEN 2 -#define ACL_RSLT_PRI_QU_FLAG HSL_RW - -#define REMARK_DOT1P "aclact_rdcpu" -#define ACL_RSLT_REMARK_DOT1P_BOFFSET 13 -#define ACL_RSLT_REMARK_DOT1P_BLEN 1 -#define ACL_RSLT_REMARK_DOT1P_FLAG HSL_RW - -#define CHG_VID_EN "aclact_rdcpu" -#define ACL_RSLT_CHG_VID_EN_BOFFSET 12 -#define ACL_RSLT_CHG_VID_EN_BLEN 1 -#define ACL_RSLT_CHG_VID_EN_FLAG HSL_RW - -#define VID "aclact_rdcpu" -#define ACL_RSLT_VID_BOFFSET 0 -#define ACL_RSLT_VID_BLEN 12 -#define ACL_RSLT_VID_FLAG HSL_RW - - - - -#define RUL_SLCT0 "rulslct0" -#define RUL_SLCT0_ID 13 -#define RUL_SLCT0_OFFSET 0x58800 -#define RUL_SLCT0_E_LENGTH 4 -#define RUL_SLCT0_E_OFFSET 0x20 -#define RUL_SLCT0_NR_E 32 - -#define ADDR3_EN "rulslct_addr3en" -#define RUL_SLCT0_ADDR3_EN_BOFFSET 3 -#define RUL_SLCT0_ADDR3_EN_BLEN 1 -#define RUL_SLCT0_ADDR3_EN_FLAG HSL_RW - -#define ADDR2_EN "rulslct_addr2en" -#define RUL_SLCT0_ADDR2_EN_BOFFSET 2 -#define RUL_SLCT0_ADDR2_EN_BLEN 1 -#define RUL_SLCT0_ADDR2_EN_FLAG HSL_RW - -#define ADDR1_EN "rulslct_addr1en" -#define RUL_SLCT0_ADDR1_EN_BOFFSET 1 -#define RUL_SLCT0_ADDR1_EN_BLEN 1 -#define RUL_SLCT0_ADDR1_EN_FLAG HSL_RW - -#define ADDR0_EN "rulslct_addr0en" -#define RUL_SLCT0_ADDR0_EN_BOFFSET 0 -#define RUL_SLCT0_ADDR0_EN_BLEN 1 -#define RUL_SLCT0_ADDR0_EN_FLAG HSL_RW - - - - -#define RUL_SLCT1 "rulslct1" -#define RUL_SLCT1_ID 13 -#define RUL_SLCT1_OFFSET 0x58804 -#define RUL_SLCT1_E_LENGTH 4 -#define RUL_SLCT1_E_OFFSET 0x20 -#define RUL_SLCT1_NR_E 32 - -#define ADDR0 "rulslct1_addr0" -#define RUL_SLCT1_ADDR0_BOFFSET 0 -#define RUL_SLCT1_ADDR0_BLEN 5 -#define RUL_SLCT1_ADDR0_FLAG HSL_RW - - - - -#define RUL_SLCT2 "rulslct2" -#define RUL_SLCT2_ID 13 -#define RUL_SLCT2_OFFSET 0x58808 -#define RUL_SLCT2_E_LENGTH 4 -#define RUL_SLCT2_E_OFFSET 0x20 -#define RUL_SLCT2_NR_E 32 - -#define ADDR1 "rulslct2_addr1" -#define RUL_SLCT2_ADDR1_BOFFSET 0 -#define RUL_SLCT2_ADDR1_BLEN 5 -#define RUL_SLCT2_ADDR1_FLAG HSL_RW - - - - -#define RUL_SLCT3 "rulslct3" -#define RUL_SLCT3_ID 13 -#define RUL_SLCT3_OFFSET 0x5880c -#define RUL_SLCT3_E_LENGTH 4 -#define RUL_SLCT3_E_OFFSET 0x20 -#define RUL_SLCT3_NR_E 32 - -#define ADDR2 "rulslct3_addr2" -#define RUL_SLCT3_ADDR2_BOFFSET 0 -#define RUL_SLCT3_ADDR2_BLEN 5 -#define RUL_SLCT3_ADDR2_FLAG HSL_RW - - - - -#define RUL_SLCT4 "rulslct4" -#define RUL_SLCT4_ID 13 -#define RUL_SLCT4_OFFSET 0x58810 -#define RUL_SLCT4_E_LENGTH 4 -#define RUL_SLCT4_E_OFFSET 0x20 -#define RUL_SLCT4_NR_E 32 - -#define ADDR3 "rulslct4_addr3" -#define RUL_SLCT4_ADDR3_BOFFSET 0 -#define RUL_SLCT4_ADDR3_BLEN 5 -#define RUL_SLCT4_ADDR3_FLAG HSL_RW - - - - -#define RUL_SLCT6 "rulslct6" -#define RUL_SLCT6_ID 13 -#define RUL_SLCT6_OFFSET 0x58818 -#define RUL_SLCT6_E_LENGTH 4 -#define RUL_SLCT6_E_OFFSET 0x20 -#define RUL_SLCT6_NR_E 32 - -#define RULE_LEN "rulslct6_rulelen" -#define RUL_SLCT6_RULE_LEN_BOFFSET 0 -#define RUL_SLCT6_RULE_LEN_BLEN 6 -#define RUL_SLCT6_RULE_LEN_FLAG HSL_RW - - - - -#define RUL_TYPE "ruletype" -#define RUL_TYPE_ID 13 -#define RUL_TYPE_OFFSET 0x5881c -#define RUL_TYPE_E_LENGTH 4 -#define RUL_TYPE_E_OFFSET 0x20 -#define RUL_TYPE_NR_E 32 - -#define TYP "ruletype_typ" -#define RUL_TYPE_TYP_BOFFSET 0 -#define RUL_TYPE_TYP_BLEN 3 -#define RUL_TYPE_TYP_FLAG HSL_RW - - - - -#define MAC_RUL_V0 "macrv0" -#define MAC_RUL_V0_ID 13 -#define MAC_RUL_V0_OFFSET 0x58400 -#define MAC_RUL_V0_E_LENGTH 4 -#define MAC_RUL_V0_E_OFFSET 0x20 -#define MAC_RUL_V0_NR_E 32 - -#define DAV_BYTE2 "macrv0_dav2" -#define MAC_RUL_V0_DAV_BYTE2_BOFFSET 24 -#define MAC_RUL_V0_DAV_BYTE2_BLEN 8 -#define MAC_RUL_V0_DAV_BYTE2_FLAG HSL_RW - -#define DAV_BYTE3 "macrv0_dav3" -#define MAC_RUL_V0_DAV_BYTE3_BOFFSET 16 -#define MAC_RUL_V0_DAV_BYTE3_BLEN 8 -#define MAC_RUL_V0_DAV_BYTE3_FLAG HSL_RW - -#define DAV_BYTE4 "macrv0_dav4" -#define MAC_RUL_V0_DAV_BYTE4_BOFFSET 8 -#define MAC_RUL_V0_DAV_BYTE4_BLEN 8 -#define MAC_RUL_V0_DAV_BYTE4_FLAG HSL_RW - -#define DAV_BYTE5 "macrv0_dav5" -#define MAC_RUL_V0_DAV_BYTE5_BOFFSET 0 -#define MAC_RUL_V0_DAV_BYTE5_BLEN 8 -#define MAC_RUL_V0_DAV_BYTE5_FLAG HSL_RW - - - - -#define MAC_RUL_V1 "macrv1" -#define MAC_RUL_V1_ID 13 -#define MAC_RUL_V1_OFFSET 0x58404 -#define MAC_RUL_V1_E_LENGTH 4 -#define MAC_RUL_V1_E_OFFSET 0x20 -#define MAC_RUL_V1_NR_E 32 - -#define SAV_BYTE4 "macrv1_sav4" -#define MAC_RUL_V1_SAV_BYTE4_BOFFSET 24 -#define MAC_RUL_V1_SAV_BYTE4_BLEN 8 -#define MAC_RUL_V1_SAV_BYTE4_FLAG HSL_RW - -#define SAV_BYTE5 "macrv1_sav5" -#define MAC_RUL_V1_SAV_BYTE5_BOFFSET 16 -#define MAC_RUL_V1_SAV_BYTE5_BLEN 8 -#define MAC_RUL_V1_SAV_BYTE5_FLAG HSL_RW - -#define DAV_BYTE0 "macrv1_dav0" -#define MAC_RUL_V1_DAV_BYTE0_BOFFSET 8 -#define MAC_RUL_V1_DAV_BYTE0_BLEN 8 -#define MAC_RUL_V1_DAV_BYTE0_FLAG HSL_RW - -#define DAV_BYTE1 "macrv1_dav1" -#define MAC_RUL_V1_DAV_BYTE1_BOFFSET 0 -#define MAC_RUL_V1_DAV_BYTE1_BLEN 8 -#define MAC_RUL_V1_DAV_BYTE1_FLAG HSL_RW - - - - -#define MAC_RUL_V2 "macrv2" -#define MAC_RUL_V2_ID 13 -#define MAC_RUL_V2_OFFSET 0x58408 -#define MAC_RUL_V2_E_LENGTH 4 -#define MAC_RUL_V2_E_OFFSET 0x20 -#define MAC_RUL_V2_NR_E 32 - -#define SAV_BYTE0 "macrv2_sav0" -#define MAC_RUL_V2_SAV_BYTE0_BOFFSET 24 -#define MAC_RUL_V2_SAV_BYTE0_BLEN 8 -#define MAC_RUL_V2_SAV_BYTE0_FLAG HSL_RW - -#define SAV_BYTE1 "macrv2_sav1" -#define MAC_RUL_V2_SAV_BYTE1_BOFFSET 16 -#define MAC_RUL_V2_SAV_BYTE1_BLEN 8 -#define MAC_RUL_V2_SAV_BYTE1_FLAG HSL_RW - -#define SAV_BYTE2 "macrv2_sav2" -#define MAC_RUL_V2_SAV_BYTE2_BOFFSET 8 -#define MAC_RUL_V2_SAV_BYTE2_BLEN 8 -#define MAC_RUL_V2_SAV_BYTE2_FLAG HSL_RW - -#define SAV_BYTE3 "macrv2_sav3" -#define MAC_RUL_V2_SAV_BYTE3_BOFFSET 0 -#define MAC_RUL_V2_SAV_BYTE3_BLEN 8 -#define MAC_RUL_V2_SAV_BYTE3_FLAG HSL_RW - - - - -#define MAC_RUL_V3 "macrv3" -#define MAC_RUL_V3_ID 13 -#define MAC_RUL_V3_OFFSET 0x5840c -#define MAC_RUL_V3_E_LENGTH 4 -#define MAC_RUL_V3_E_OFFSET 0x20 -#define MAC_RUL_V3_NR_E 32 - -#define ETHTYPV "macrv3_ethtypv" -#define MAC_RUL_V3_ETHTYPV_BOFFSET 16 -#define MAC_RUL_V3_ETHTYPV_BLEN 16 -#define MAC_RUL_V3_ETHTYPV_FLAG HSL_RW - -#define VLANPRIV "macrv3_vlanpriv" -#define MAC_RUL_V3_VLANPRIV_BOFFSET 13 -#define MAC_RUL_V3_VLANPRIV_BLEN 3 -#define MAC_RUL_V3_VLANPRIV_FLAG HSL_RW - -#define VLANIDV "macrv3_vlanidv" -#define MAC_RUL_V3_VLANIDV_BOFFSET 0 -#define MAC_RUL_V3_VLANIDV_BLEN 12 -#define MAC_RUL_V3_VLANIDV_FLAG HSL_RW - - - - -#define MAC_RUL_V4 "macrv4" -#define MAC_RUL_V4_ID 13 -#define MAC_RUL_V4_OFFSET 0x58410 -#define MAC_RUL_V4_E_LENGTH 4 -#define MAC_RUL_V4_E_OFFSET 0x20 -#define MAC_RUL_V4_NR_E 32 - -#define TAGGEDM "macrv4_vlanid" -#define MAC_RUL_V4_TAGGEDM_BOFFSET 7 -#define MAC_RUL_V4_TAGGEDM_BLEN 1 -#define MAC_RUL_V4_TAGGEDM_FLAG HSL_RW - -#define TAGGEDV "macrv4_vlanid" -#define MAC_RUL_V4_TAGGEDV_BOFFSET 6 -#define MAC_RUL_V4_TAGGEDV_BLEN 1 -#define MAC_RUL_V4_TAGGEDV_FLAG HSL_RW - -#define MAC_INPT "macrv4_vlanid" -#define MAC_RUL_V4_MAC_INPT_BOFFSET 0 -#define MAC_RUL_V4_MAC_INPT_BLEN 6 -#define MAC_RUL_V4_MAC_INPT_FLAG HSL_RW - - - - - -#define MAC_RUL_M0 "macrv0" -#define MAC_RUL_M0_ID 13 -#define MAC_RUL_M0_OFFSET 0x58c00 -#define MAC_RUL_M0_E_LENGTH 4 -#define MAC_RUL_M0_E_OFFSET 0x20 -#define MAC_RUL_M0_NR_E 32 - -#define DAM_BYTE2 "macrv0_dam2" -#define MAC_RUL_M0_DAM_BYTE2_BOFFSET 24 -#define MAC_RUL_M0_DAM_BYTE2_BLEN 8 -#define MAC_RUL_M0_DAM_BYTE2_FLAG HSL_RW - -#define DAM_BYTE3 "macrv0_dam3" -#define MAC_RUL_M0_DAM_BYTE3_BOFFSET 16 -#define MAC_RUL_M0_DAM_BYTE3_BLEN 8 -#define MAC_RUL_M0_DAM_BYTE3_FLAG HSL_RW - -#define DAM_BYTE4 "macrv0_dam4" -#define MAC_RUL_M0_DAM_BYTE4_BOFFSET 8 -#define MAC_RUL_M0_DAM_BYTE4_BLEN 8 -#define MAC_RUL_M0_DAM_BYTE4_FLAG HSL_RW - -#define DAM_BYTE5 "macrv0_dam5" -#define MAC_RUL_M0_DAM_BYTE5_BOFFSET 0 -#define MAC_RUL_M0_DAM_BYTE5_BLEN 8 -#define MAC_RUL_M0_DAM_BYTE5_FLAG HSL_RW - - - - -#define MAC_RUL_M1 "macrm1" -#define MAC_RUL_M1_ID 13 -#define MAC_RUL_M1_OFFSET 0x58c04 -#define MAC_RUL_M1_E_LENGTH 4 -#define MAC_RUL_M1_E_OFFSET 0x20 -#define MAC_RUL_M1_NR_E 32 - -#define SAM_BYTE4 "macrm1_sam4" -#define MAC_RUL_M1_SAM_BYTE4_BOFFSET 24 -#define MAC_RUL_M1_SAM_BYTE4_BLEN 8 -#define MAC_RUL_M1_SAM_BYTE4_FLAG HSL_RW - -#define SAM_BYTE5 "macrm1_sam5" -#define MAC_RUL_M1_SAM_BYTE5_BOFFSET 16 -#define MAC_RUL_M1_SAM_BYTE5_BLEN 8 -#define MAC_RUL_M1_SAM_BYTE5_FLAG HSL_RW - -#define DAM_BYTE0 "macrm1_dam0" -#define MAC_RUL_M1_DAM_BYTE0_BOFFSET 8 -#define MAC_RUL_M1_DAM_BYTE0_BLEN 8 -#define MAC_RUL_M1_DAM_BYTE0_FLAG HSL_RW - -#define DAM_BYTE1 "macrm1_dam1" -#define MAC_RUL_M1_DAM_BYTE1_BOFFSET 0 -#define MAC_RUL_M1_DAM_BYTE1_BLEN 8 -#define MAC_RUL_M1_DAM_BYTE1_FLAG HSL_RW - - - - -#define MAC_RUL_M2 "macrm2" -#define MAC_RUL_M2_ID 13 -#define MAC_RUL_M2_OFFSET 0x58c08 -#define MAC_RUL_M2_E_LENGTH 4 -#define MAC_RUL_M2_E_OFFSET 0x20 -#define MAC_RUL_M2_NR_E 32 - -#define SAM_BYTE0 "macrm2_sam0" -#define MAC_RUL_M2_SAM_BYTE0_BOFFSET 24 -#define MAC_RUL_M2_SAM_BYTE0_BLEN 8 -#define MAC_RUL_M2_SAM_BYTE0_FLAG HSL_RW - -#define SAM_BYTE1 "macrm2_samv1" -#define MAC_RUL_M2_SAM_BYTE1_BOFFSET 16 -#define MAC_RUL_M2_SAM_BYTE1_BLEN 8 -#define MAC_RUL_M2_SAM_BYTE1_FLAG HSL_RW - -#define SAM_BYTE2 "macrm2_sam2" -#define MAC_RUL_M2_SAM_BYTE2_BOFFSET 8 -#define MAC_RUL_M2_SAM_BYTE2_BLEN 8 -#define MAC_RUL_M2_SAM_BYTE2_FLAG HSL_RW - -#define SAM_BYTE3 "macrm2_sam3" -#define MAC_RUL_M2_SAM_BYTE3_BOFFSET 0 -#define MAC_RUL_M2_SAM_BYTE3_BLEN 8 -#define MAC_RUL_M2_SAM_BYTE3_FLAG HSL_RW - - - - -#define MAC_RUL_M3 "macrv3" -#define MAC_RUL_M3_ID 13 -#define MAC_RUL_M3_OFFSET 0x58c0c -#define MAC_RUL_M3_E_LENGTH 4 -#define MAC_RUL_M3_E_OFFSET 0x20 -#define MAC_RUL_M3_NR_E 32 - -#define ETHTYPM "macrm3_ethtypm" -#define MAC_RUL_M3_ETHTYPM_BOFFSET 16 -#define MAC_RUL_M3_ETHTYPM_BLEN 16 -#define MAC_RUL_M3_ETHTYPM_FLAG HSL_RW - -#define VLANPRIM "macrm3_vlanprim" -#define MAC_RUL_M3_VLANPRIM_BOFFSET 13 -#define MAC_RUL_M3_VLANPRIM_BLEN 3 -#define MAC_RUL_M3_VLANPRIM_FLAG HSL_RW - -#define VIDMSK "macrm3_vidmsk" -#define MAC_RUL_M3_VIDMSK_BOFFSET 12 -#define MAC_RUL_M3_VIDMSK_BLEN 1 -#define MAC_RUL_M3_VIDMSK_FLAG HSL_RW - -#define VLANIDM "macrm3_vlanidm" -#define MAC_RUL_M3_VLANIDM_BOFFSET 0 -#define MAC_RUL_M3_VLANIDM_BLEN 12 -#define MAC_RUL_M3_VLANIDM_FLAG HSL_RW - - - - -#define IP4_RUL_V0 "ip4v0" -#define IP4_RUL_V0_ID 13 -#define IP4_RUL_V0_OFFSET 0x58400 -#define IP4_RUL_V0_E_LENGTH 4 -#define IP4_RUL_V0_E_OFFSET 0x20 -#define IP4_RUL_V0_NR_E 32 - -#define DIPV "ip4v0_dipv" -#define IP4_RUL_V0_DIPV_BOFFSET 0 -#define IP4_RUL_V0_DIPV_BLEN 32 -#define IP4_RUL_V0_DIPV_FLAG HSL_RW - - - - -#define IP4_RUL_V1 "ip4v1" -#define IP4_RUL_V1_ID 13 -#define IP4_RUL_V1_OFFSET 0x58404 -#define IP4_RUL_V1_E_LENGTH 4 -#define IP4_RUL_V1_E_OFFSET 0x20 -#define IP4_RUL_V1_NR_E 32 - -#define SIPV "ip4v1_sipv" -#define IP4_RUL_V1_SIPV_BOFFSET 0 -#define IP4_RUL_V1_SIPV_BLEN 32 -#define IP4_RUL_V1_SIPV_FLAG HSL_RW - - - - -#define IP4_RUL_V2 "ip4v2" -#define IP4_RUL_V2_ID 13 -#define IP4_RUL_V2_OFFSET 0x58408 -#define IP4_RUL_V2_E_LENGTH 4 -#define IP4_RUL_V2_E_OFFSET 0x20 -#define IP4_RUL_V2_NR_E 32 - -#define IP4PROTV "ip4v2_protv" -#define IP4_RUL_V2_IP4PROTV_BOFFSET 0 -#define IP4_RUL_V2_IP4PROTV_BLEN 8 -#define IP4_RUL_V2_IP4PROTV_FLAG HSL_RW - -#define IP4DSCPV "ip4v2_dscpv" -#define IP4_RUL_V2_IP4DSCPV_BOFFSET 8 -#define IP4_RUL_V2_IP4DSCPV_BLEN 8 -#define IP4_RUL_V2_IP4DSCPV_FLAG HSL_RW - -#define IP4DPORTV "ip4v2_dportv" -#define IP4_RUL_V2_IP4DPORTV_BOFFSET 16 -#define IP4_RUL_V2_IP4DPORTV_BLEN 16 -#define IP4_RUL_V2_IP4DPORTV_FLAG HSL_RW - - - - -#define IP4_RUL_V3 "ip4v3" -#define IP4_RUL_V3_ID 13 -#define IP4_RUL_V3_OFFSET 0x5840c -#define IP4_RUL_V3_E_LENGTH 4 -#define IP4_RUL_V3_E_OFFSET 0x20 -#define IP4_RUL_V3_NR_E 32 - -#define IP4SPORTV "ip4v3_sportv" -#define IP4_RUL_V3_IP4SPORTV_BOFFSET 0 -#define IP4_RUL_V3_IP4SPORTV_BLEN 16 -#define IP4_RUL_V3_IP4SPORTV_FLAG HSL_RW - - -#define IP4_RUL_V4 "ip4v2" -#define IP4_RUL_V4_ID 13 -#define IP4_RUL_V4_OFFSET 0x58410 -#define IP4_RUL_V4_E_LENGTH 4 -#define IP4_RUL_V4_E_OFFSET 0x20 -#define IP4_RUL_V4_NR_E 32 - -#define IP4_INPT "ip4rv4_inpt" -#define IP4_RUL_V4_IP4_INPT_BOFFSET 0 -#define IP4_RUL_V4_IP4_INPT_BLEN 6 -#define IP4_RUL_V4_IP4_INPT_FLAG HSL_RW - - - - - - -#define IP4_RUL_M0 "ip4m0" -#define IP4_RUL_M0_ID 13 -#define IP4_RUL_M0_OFFSET 0x58c00 -#define IP4_RUL_M0_E_LENGTH 4 -#define IP4_RUL_M0_E_OFFSET 0x20 -#define IP4_RUL_M0_NR_E 32 - -#define DIPM "ip4m0_dipm" -#define IP4_RUL_M0_DIPM_BOFFSET 0 -#define IP4_RUL_M0_DIPM_BLEN 32 -#define IP4_RUL_M0_DIPM_FLAG HSL_RW - - - - -#define IP4_RUL_M1 "ip4m1" -#define IP4_RUL_M1_ID 13 -#define IP4_RUL_M1_OFFSET 0x58c04 -#define IP4_RUL_M1_E_LENGTH 4 -#define IP4_RUL_M1_E_OFFSET 0x20 -#define IP4_RUL_M1_NR_E 32 - -#define SIPM "ip4m1_sipm" -#define IP4_RUL_M1_SIPM_BOFFSET 0 -#define IP4_RUL_M1_SIPM_BLEN 32 -#define IP4_RUL_M1_SIPM_FLAG HSL_RW - - - - -#define IP4_RUL_M2 "ip4m2" -#define IP4_RUL_M2_ID 13 -#define IP4_RUL_M2_OFFSET 0x58c08 -#define IP4_RUL_M2_E_LENGTH 4 -#define IP4_RUL_M2_E_OFFSET 0x20 -#define IP4_RUL_M2_NR_E 32 - -#define IP4PROTM "ip4m2_protm" -#define IP4_RUL_M2_IP4PROTM_BOFFSET 0 -#define IP4_RUL_M2_IP4PROTM_BLEN 8 -#define IP4_RUL_M2_IP4PROTM_FLAG HSL_RW - -#define IP4DSCPM "ip4m2_dscpm" -#define IP4_RUL_M2_IP4DSCPM_BOFFSET 8 -#define IP4_RUL_M2_IP4DSCPM_BLEN 8 -#define IP4_RUL_M2_IP4DSCPM_FLAG HSL_RW - -#define IP4DPORTM "ip4m2_dportm" -#define IP4_RUL_M2_IP4DPORTM_BOFFSET 16 -#define IP4_RUL_M2_IP4DPORTM_BLEN 16 -#define IP4_RUL_M2_IP4DPORTM_FLAG HSL_RW - - - - -#define IP4_RUL_M3 "ip4m3" -#define IP4_RUL_M3_ID 13 -#define IP4_RUL_M3_OFFSET 0x58c0c -#define IP4_RUL_M3_E_LENGTH 4 -#define IP4_RUL_M3_E_OFFSET 0x20 -#define IP4_RUL_M3_NR_E 32 - -#define IP4SPORTM "ip4m3_sportm" -#define IP4_RUL_M3_IP4SPORTM_BOFFSET 0 -#define IP4_RUL_M3_IP4SPORTM_BLEN 16 -#define IP4_RUL_M3_IP4SPORTM_FLAG HSL_RW - -#define IP4SPORTM_EN "ip4m3_sportmen" -#define IP4_RUL_M3_IP4SPORTM_EN_BOFFSET 16 -#define IP4_RUL_M3_IP4SPORTM_EN_BLEN 1 -#define IP4_RUL_M3_IP4SPORTM_EN_FLAG HSL_RW - -#define IP4DPORTM_EN "ip4m3_dportmen" -#define IP4_RUL_M3_IP4DPORTM_EN_BOFFSET 17 -#define IP4_RUL_M3_IP4DPORTM_EN_BLEN 1 -#define IP4_RUL_M3_IP4DPORTM_EN_FLAG HSL_RW - - - - -#define IP6_RUL1_V0 "ip6r1v0" -#define IP6_RUL1_V0_ID 13 -#define IP6_RUL1_V0_OFFSET 0x58400 -#define IP6_RUL1_V0_E_LENGTH 4 -#define IP6_RUL1_V0_E_OFFSET 0x20 -#define IP6_RUL1_V0_NR_E 32 - -#define IP6_DIPV0 "ip6r1v0_dipv0" -#define IP6_RUL1_V0_IP6_DIPV0_BOFFSET 0 -#define IP6_RUL1_V0_IP6_DIPV0_BLEN 32 -#define IP6_RUL1_V0_IP6_DIPV0_FLAG HSL_RW - - - - -#define IP6_RUL1_V1 "ip6r1v1" -#define IP6_RUL1_V1_ID 13 -#define IP6_RUL1_V1_OFFSET 0x58404 -#define IP6_RUL1_V1_E_LENGTH 4 -#define IP6_RUL1_V1_E_OFFSET 0x20 -#define IP6_RUL1_V1_NR_E 32 - -#define IP6_DIPV1 "ip6r1v1_dipv1" -#define IP6_RUL1_V1_IP6_DIPV1_BOFFSET 0 -#define IP6_RUL1_V1_IP6_DIPv1_BLEN 32 -#define IP6_RUL1_V1_IP6_DIPV1_FLAG HSL_RW - - - -#define IP6_RUL1_V2 "ip6r1v2" -#define IP6_RUL1_V2_ID 13 -#define IP6_RUL1_V2_OFFSET 0x58408 -#define IP6_RUL1_V2_E_LENGTH 4 -#define IP6_RUL1_V2_E_OFFSET 0x20 -#define IP6_RUL1_V2_NR_E 32 - -#define IP6_DIPV2 "ip6r1v2_dipv2" -#define IP6_RUL1_V2_IP6_DIPV2_BOFFSET 0 -#define IP6_RUL1_V2_IP6_DIPv2_BLEN 32 -#define IP6_RUL1_V2_IP6_DIPV2_FLAG HSL_RW - - - - -#define IP6_RUL1_V3 "ip6r1v3" -#define IP6_RUL1_V3_ID 13 -#define IP6_RUL1_V3_OFFSET 0x5840c -#define IP6_RUL1_V3_E_LENGTH 4 -#define IP6_RUL1_V3_E_OFFSET 0x20 -#define IP6_RUL1_V3_NR_E 32 - -#define IP6_DIPV3 "ip6r1v3_dipv3" -#define IP6_RUL1_V3_IP6_DIPV3_BOFFSET 0 -#define IP6_RUL1_V3_IP6_DIPv3_BLEN 32 -#define IP6_RUL1_V3_IP6_DIPV3_FLAG HSL_RW - - - - -#define IP6_RUL1_V4 "ip6r1v4" -#define IP6_RUL1_V4_ID 13 -#define IP6_RUL1_V4_OFFSET 0x58410 -#define IP6_RUL1_V4_E_LENGTH 4 -#define IP6_RUL1_V4_E_OFFSET 0x20 -#define IP6_RUL1_V4_NR_E 32 - -#define IP6_RUL1_INPT "ip6r1v4_inpt" -#define IP6_RUL1_V4_IP6_RUL1_INPT_BOFFSET 0 -#define IP6_RUL1_V4_IP6_RUL1_INPT_BLEN 6 -#define IP6_RUL1_V4_IP6_RUL1_INPT_FLAG HSL_RW - - - - - -#define IP6_RUL1_M0 "ip6r1m0" -#define IP6_RUL1_M0_ID 13 -#define IP6_RUL1_M0_OFFSET 0x58c00 -#define IP6_RUL1_M0_E_LENGTH 4 -#define IP6_RUL1_M0_E_OFFSET 0x20 -#define IP6_RUL1_M0_NR_E 32 - -#define IP6_DIPM0 "ip6r1m0_dipm0" -#define IP6_RUL1_M0_IP6_DIPM0_BOFFSET 0 -#define IP6_RUL1_M0_IP6_DIPM0_BLEN 32 -#define IP6_RUL1_M0_IP6_DIPM0_FLAG HSL_RW - - - - -#define IP6_RUL1_M1 "ip6r1m1" -#define IP6_RUL1_M1_ID 13 -#define IP6_RUL1_M1_OFFSET 0x58c04 -#define IP6_RUL1_M1_E_LENGTH 4 -#define IP6_RUL1_M1_E_OFFSET 0x20 -#define IP6_RUL1_M1_NR_E 32 - -#define IP6_DIPM1 "ip6r1m1_dipm1" -#define IP6_RUL1_M1_IP6_DIPM1_BOFFSET 0 -#define IP6_RUL1_M1_IP6_DIPM1_BLEN 32 -#define IP6_RUL1_M1_IP6_DIPM1_FLAG HSL_RW - - - -#define IP6_RUL1_M2 "ip6r1m2" -#define IP6_RUL1_M2_ID 13 -#define IP6_RUL1_M2_OFFSET 0x58c08 -#define IP6_RUL1_M2_E_LENGTH 4 -#define IP6_RUL1_M2_E_OFFSET 0x20 -#define IP6_RUL1_M2_NR_E 32 - -#define IP6_DIPM2 "ip6r1m2_dipm2" -#define IP6_RUL1_M2_IP6_DIPM2_BOFFSET 0 -#define IP6_RUL1_M2_IP6_DIPM2_BLEN 32 -#define IP6_RUL1_M2_IP6_DIPM2_FLAG HSL_RW - - - - -#define IP6_RUL1_M3 "ip6r1m3" -#define IP6_RUL1_M3_ID 13 -#define IP6_RUL1_M3_OFFSET 0x58c0c -#define IP6_RUL1_M3_E_LENGTH 4 -#define IP6_RUL1_M3_E_OFFSET 0x20 -#define IP6_RUL1_M3_NR_E 32 - -#define IP6_DIPM3 "ip6r1m3_dipm3" -#define IP6_RUL1_M3_IP6_DIPM3_BOFFSET 0 -#define IP6_RUL1_M3_IP6_DIPM3_BLEN 32 -#define IP6_RUL1_M3_IP6_DIPM3_FLAG HSL_RW - - - - - -#define IP6_RUL2_V0 "ip6r2v0" -#define IP6_RUL2_V0_ID 13 -#define IP6_RUL2_V0_OFFSET 0x58400 -#define IP6_RUL2_V0_E_LENGTH 4 -#define IP6_RUL2_V0_E_OFFSET 0x20 -#define IP6_RUL2_V0_NR_E 32 - -#define IP6_SIPV0 "ip6r2v0_sipv0" -#define IP6_RUL2_V0_IP6_SIPV0_BOFFSET 0 -#define IP6_RUL2_V0_IP6_SIPv0_BLEN 32 -#define IP6_RUL2_V0_IP6_SIPV0_FLAG HSL_RW - - - - -#define IP6_RUL2_V1 "ip6r2v1" -#define IP6_RUL2_V1_ID 13 -#define IP6_RUL2_V1_OFFSET 0x58404 -#define IP6_RUL2_V1_E_LENGTH 4 -#define IP6_RUL2_V1_E_OFFSET 0x20 -#define IP6_RUL2_V1_NR_E 32 - -#define IP6_SIPV1 "ip6r2v1_sipv1" -#define IP6_RUL2_V1_IP6_SIPV1_BOFFSET 0 -#define IP6_RUL2_V1_IP6_SIPv1_BLEN 32 -#define IP6_RUL2_V1_IP6_SIPV1_FLAG HSL_RW - - - -#define IP6_RUL2_V2 "ip6r2v2" -#define IP6_RUL2_V2_ID 13 -#define IP6_RUL2_V2_OFFSET 0x58408 -#define IP6_RUL2_V2_E_LENGTH 4 -#define IP6_RUL2_V2_E_OFFSET 0x20 -#define IP6_RUL2_V2_NR_E 32 - -#define IP6_SIPV2 "ip6r2v2_sipv2" -#define IP6_RUL2_V2_IP6_SIPV2_BOFFSET 0 -#define IP6_RUL2_V2_IP6_SIPv2_BLEN 32 -#define IP6_RUL2_V2_IP6_SIPV2_FLAG HSL_RW - - - - -#define IP6_RUL2_V3 "ip6r2v3" -#define IP6_RUL2_V3_ID 13 -#define IP6_RUL2_V3_OFFSET 0x5840c -#define IP6_RUL2_V3_E_LENGTH 4 -#define IP6_RUL2_V3_E_OFFSET 0x20 -#define IP6_RUL2_V3_NR_E 32 - -#define IP6_SIPV3 "ip6r2v3_sipv3" -#define IP6_RUL2_V3_IP6_SIPV3_BOFFSET 0 -#define IP6_RUL2_V3_IP6_SIPv3_BLEN 32 -#define IP6_RUL2_V3_IP6_SIPV3_FLAG HSL_RW - - - - -#define IP6_RUL2_V4 "ip6r2v4" -#define IP6_RUL2_V4_ID 13 -#define IP6_RUL2_V4_OFFSET 0x58410 -#define IP6_RUL2_V4_E_LENGTH 4 -#define IP6_RUL2_V4_E_OFFSET 0x20 -#define IP6_RUL2_V4_NR_E 32 - -#define IP6_RUL2_INPT "ip6r2v4_inptm" -#define IP6_RUL2_V4_IP6_RUL2_INPT_BOFFSET 0 -#define IP6_RUL2_V4_IP6_RUL2_INPT_BLEN 6 -#define IP6_RUL2_V4_IP6_RUL2_INPT_FLAG HSL_RW - - - - -#define IP6_RUL2_M0 "ip6r2m0" -#define IP6_RUL2_M0_ID 13 -#define IP6_RUL2_M0_OFFSET 0x58c00 -#define IP6_RUL2_M0_E_LENGTH 4 -#define IP6_RUL2_M0_E_OFFSET 0x20 -#define IP6_RUL2_M0_NR_E 32 - -#define IP6_SIPM0 "ip6r2m0_sipm0" -#define IP6_RUL2_M0_IP6_SIPM0_BOFFSET 0 -#define IP6_RUL2_M0_IP6_SIPM0_BLEN 32 -#define IP6_RUL2_M0_IP6_SIPM0_FLAG HSL_RW - - - - -#define IP6_RUL2_M1 "ip6r2m1" -#define IP6_RUL2_M1_ID 13 -#define IP6_RUL2_M1_OFFSET 0x58c04 -#define IP6_RUL2_M1_E_LENGTH 4 -#define IP6_RUL2_M1_E_OFFSET 0x20 -#define IP6_RUL2_M1_NR_E 32 - -#define IP6_SIPM1 "ip6r2m1_sipm1" -#define IP6_RUL2_M1_IP6_DIPM1_BOFFSET 0 -#define IP6_RUL2_M1_IP6_DIPM1_BLEN 32 -#define IP6_RUL2_M1_IP6_DIPM1_FLAG HSL_RW - - - -#define IP6_RUL2_M2 "ip6r2m2" -#define IP6_RUL2_M2_ID 13 -#define IP6_RUL2_M2_OFFSET 0x58c08 -#define IP6_RUL2_M2_E_LENGTH 4 -#define IP6_RUL2_M2_E_OFFSET 0x20 -#define IP6_RUL2_M2_NR_E 32 - -#define IP6_SIPM2 "ip6r2m2_sipm2" -#define IP6_RUL2_M2_IP6_DIPM2_BOFFSET 0 -#define IP6_RUL2_M2_IP6_DIPM2_BLEN 32 -#define IP6_RUL2_M2_IP6_DIPM2_FLAG HSL_RW - - - - -#define IP6_RUL2_M3 "ip6r2m3" -#define IP6_RUL2_M3_ID 13 -#define IP6_RUL2_M3_OFFSET 0x58c0c -#define IP6_RUL2_M3_E_LENGTH 4 -#define IP6_RUL2_M3_E_OFFSET 0x20 -#define IP6_RUL2_M3_NR_E 32 - -#define IP6_SIPM3 "ip6r2m3_sipm3" -#define IP6_RUL2_M3_IP6_SIPM3_BOFFSET 0 -#define IP6_RUL2_M3_IP6_SIPM3_BLEN 32 -#define IP6_RUL2_M3_IP6_SIPM3_FLAG HSL_RW - - - - - -#define IP6_RUL3_V0 "ip6r3v0" -#define IP6_RUL3_V0_ID 13 -#define IP6_RUL3_V0_OFFSET 0x58400 -#define IP6_RUL3_V0_E_LENGTH 4 -#define IP6_RUL3_V0_E_OFFSET 0x20 -#define IP6_RUL3_V0_NR_E 32 - -#define IP6PROTV "ip6r3v0_protv" -#define IP6_RUL3_V0_IP6PROTV_BOFFSET 0 -#define IP6_RUL3_V0_IP6PROTV_BLEN 8 -#define IP6_RUL3_V0_IP6PROTV_FLAG HSL_RW - -#define IP6DSCPV "ip6r3v0_dscpv" -#define IP6_RUL3_V0_IP6DSCPV_BOFFSET 8 -#define IP6_RUL3_V0_IP6DSCPV_BLEN 8 -#define IP6_RUL3_V0_IP6DSCPV_FLAG HSL_RW - -#define IP6DPORTV "ip6r3v0_dportv" -#define IP6_RUL3_V0_IP6DPORTV_BOFFSET 16 -#define IP6_RUL3_V0_IP6DPORTV_BLEN 16 -#define IP6_RUL3_V0_IP6DPORTV_FLAG HSL_RW - - - - -#define IP6_RUL3_V1 "ip6r3v1" -#define IP6_RUL3_V1_ID 13 -#define IP6_RUL3_V1_OFFSET 0x58404 -#define IP6_RUL3_V1_E_LENGTH 4 -#define IP6_RUL3_V1_E_OFFSET 0x20 -#define IP6_RUL3_V1_NR_E 32 - -#define IP6SPORTV "ip6r3v1_sportv" -#define IP6_RUL3_V1_IP6SPORTV_BOFFSET 0 -#define IP6_RUL3_V1_IP6SPORTV_BLEN 16 -#define IP6_RUL3_V1_IP6SPORTV_FLAG HSL_RW - -#define IP6LABEL1V "ip6r3v1_label1v" -#define IP6_RUL3_V1_IP6LABEL1V_BOFFSET 16 -#define IP6_RUL3_V1_IP6LABEL1V_BLEN 16 -#define IP6_RUL3_V1_IP6LABEL1V_FLAG HSL_RW - - - - -#define IP6_RUL3_V2 "ip6r3v2" -#define IP6_RUL3_V2_ID 13 -#define IP6_RUL3_V2_OFFSET 0x58408 -#define IP6_RUL3_V2_E_LENGTH 4 -#define IP6_RUL3_V2_E_OFFSET 0x20 -#define IP6_RUL3_V2_NR_E 32 - -#define IP6LABEL2V "ip6r3v2_label2v" -#define IP6_RUL3_V2_IP6LABEL2V_BOFFSET 0 -#define IP6_RUL3_V2_IP6LABEL2V_BLEN 4 -#define IP6_RUL3_V2_IP6LABEL2V_FLAG HSL_RW - - - - -#define IP6_RUL3_V4 "ip6r3v4" -#define IP6_RUL3_V4_ID 13 -#define IP6_RUL3_V4_OFFSET 0x58410 -#define IP6_RUL3_V4_E_LENGTH 4 -#define IP6_RUL3_V4_E_OFFSET 0x20 -#define IP6_RUL3_V4_NR_E 32 - -#define IP6_RUL3_INPT "ip6r3v4_inpt" -#define IP6_RUL3_V4_IP6_RUL3_INPT_BOFFSET 0 -#define IP6_RUL3_V4_IP6_RUL3_INPT_BLEN 6 -#define IP6_RUL3_V4_IP6_RUL3_INPT_FLAG HSL_RW - - - - -#define IP6_RUL3_M0 "ip6r3m0" -#define IP6_RUL3_M0_ID 13 -#define IP6_RUL3_M0_OFFSET 0x58c00 -#define IP6_RUL3_M0_E_LENGTH 4 -#define IP6_RUL3_M0_E_OFFSET 0x20 -#define IP6_RUL3_M0_NR_E 32 - -#define IP6PROTM "ip6r3m0_protm" -#define IP6_RUL3_M0_IP6PROTM_BOFFSET 0 -#define IP6_RUL3_M0_IP6PROTM_BLEN 8 -#define IP6_RUL3_M0_IP6PROTM_FLAG HSL_RW - -#define IP6DSCPM "ip6r3m0_dscpm" -#define IP6_RUL3_M0_IP6DSCPM_BOFFSET 8 -#define IP6_RUL3_M0_IP6DSCPM_BLEN 8 -#define IP6_RUL3_M0_IP6DSCPM_FLAG HSL_RW - -#define IP6DPORTM "ip6r3m0_dportm" -#define IP6_RUL3_M0_IP6DPORTM_BOFFSET 16 -#define IP6_RUL3_M0_IP6DPORTM_BLEN 16 -#define IP6_RUL3_M0_IP6DPORTM_FLAG HSL_RW - - - - -#define IP6_RUL3_M1 "ip6r3m1" -#define IP6_RUL3_M1_ID 13 -#define IP6_RUL3_M1_OFFSET 0x58c04 -#define IP6_RUL3_M1_E_LENGTH 4 -#define IP6_RUL3_M1_E_OFFSET 0x20 -#define IP6_RUL3_M1_NR_E 32 - -#define IP6SPORTM "ip6r3m1_sportm" -#define IP6_RUL3_M1_IP6SPORTM_BOFFSET 0 -#define IP6_RUL3_M1_IP6SPORTM_BLEN 16 -#define IP6_RUL3_M1_IP6SPORTM_FLAG HSL_RW - -#define IP6LABEL1M "ip6r3m1_label1m" -#define IP6_RUL3_M1_IP6LABEL1M_BOFFSET 16 -#define IP6_RUL3_M1_IP6LABEL1M_BLEN 16 -#define IP6_RUL3_M1_IP6LABEL1M_FLAG HSL_RW - - - - -#define IP6_RUL3_M2 "ip6r3m2" -#define IP6_RUL3_M2_ID 13 -#define IP6_RUL3_M2_OFFSET 0x58c08 -#define IP6_RUL3_M2_E_LENGTH 4 -#define IP6_RUL3_M2_E_OFFSET 0x20 -#define IP6_RUL3_M2_NR_E 32 - -#define IP6LABEL2M "ip6r3m2_label2m" -#define IP6_RUL3_M2_IP6LABEL2M_BOFFSET 0 -#define IP6_RUL3_M2_IP6LABEL2M_BLEN 4 -#define IP6_RUL3_M2_IP6LABEL21M_FLAG HSL_RW - - - - -#define IP6_RUL3_M3 "ip6r3m3" -#define IP6_RUL3_M3_ID 13 -#define IP6_RUL3_M3_OFFSET 0x58c0c -#define IP6_RUL3_M3_E_LENGTH 4 -#define IP6_RUL3_M3_E_OFFSET 0x20 -#define IP6_RUL3_M3_NR_E 32 - - -#define IP6DPORTM_EN "ip6r3m3_dportmen" -#define IP6_RUL3_M3_IP6DPORTM_EN_BOFFSET 25 -#define IP6_RUL3_M3_IP6DPORTM_EN_BLEN 1 -#define IP6_RUL3_M3_IP6DPORTM_EN_FLAG HSL_RW - -#define IP6SPORTM_EN "ip6r3m3_sportmen" -#define IP6_RUL3_M3_IP6SPORTM_EN_BOFFSET 24 -#define IP6_RUL3_M3_IP6SPORTM_EN_BLEN 1 -#define IP6_RUL3_M3_IP6SPORTM_EN_FLAG HSL_RW - - - - -#ifdef __cplusplus -} -#endif /* __cplusplus */ -#endif /* _GARUDA_REG_H_ */ - diff --git a/feeds/ipq807x/qca-ssdk/src/include/hsl/garuda/garuda_reg_access.h b/feeds/ipq807x/qca-ssdk/src/include/hsl/garuda/garuda_reg_access.h deleted file mode 100755 index 3325e9fd2..000000000 --- a/feeds/ipq807x/qca-ssdk/src/include/hsl/garuda/garuda_reg_access.h +++ /dev/null @@ -1,63 +0,0 @@ -/* - * Copyright (c) 2012,2018, The Linux Foundation. All rights reserved. - * Permission to use, copy, modify, and/or distribute this software for - * any purpose with or without fee is hereby granted, provided that the - * above copyright notice and this permission notice appear in all copies. - * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES - * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR - * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES - * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN - * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT - * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. - */ - - - -#ifndef _GARUDA_REG_ACCESS_H_ -#define _GARUDA_REG_ACCESS_H_ - -#ifdef __cplusplus -extern "C" { -#endif /* __cplusplus */ - -#include "sw.h" - - sw_error_t - garuda_phy_get(a_uint32_t dev_id, a_uint32_t phy_addr, - a_uint32_t reg, a_uint16_t * value); - - sw_error_t - garuda_phy_set(a_uint32_t dev_id, a_uint32_t phy_addr, - a_uint32_t reg, a_uint16_t value); - - sw_error_t - garuda_reg_get(a_uint32_t dev_id, a_uint32_t reg_addr, a_uint8_t value[], - a_uint32_t value_len); - - sw_error_t - garuda_reg_set(a_uint32_t dev_id, a_uint32_t reg_addr, a_uint8_t value[], - a_uint32_t value_len); - - sw_error_t - garuda_reg_field_get(a_uint32_t dev_id, a_uint32_t reg_addr, - a_uint32_t bit_offset, a_uint32_t field_len, - a_uint8_t value[], a_uint32_t value_len); - - sw_error_t - garuda_reg_field_set(a_uint32_t dev_id, a_uint32_t reg_addr, - a_uint32_t bit_offset, a_uint32_t field_len, - const a_uint8_t value[], a_uint32_t value_len); - - sw_error_t - garuda_reg_access_init(a_uint32_t dev_id, hsl_access_mode mode); - - sw_error_t - garuda_access_mode_set(a_uint32_t dev_id, hsl_access_mode mode); - -#ifdef __cplusplus -} -#endif /* __cplusplus */ - -#endif /* _GARUDA_REG_ACCESS_H_ */ - diff --git a/feeds/ipq807x/qca-ssdk/src/include/hsl/garuda/garuda_stp.h b/feeds/ipq807x/qca-ssdk/src/include/hsl/garuda/garuda_stp.h deleted file mode 100755 index c81129182..000000000 --- a/feeds/ipq807x/qca-ssdk/src/include/hsl/garuda/garuda_stp.h +++ /dev/null @@ -1,62 +0,0 @@ -/* - * Copyright (c) 2012, The Linux Foundation. All rights reserved. - * Permission to use, copy, modify, and/or distribute this software for - * any purpose with or without fee is hereby granted, provided that the - * above copyright notice and this permission notice appear in all copies. - * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES - * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR - * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES - * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN - * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT - * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. - */ - - -/** - * @defgroup garuda_stp GARUDA_STP - * @{ - */ -#ifndef _GARUDA_STP_H_ -#define _GARUDA_STP_H_ - -#ifdef __cplusplus -extern "C" { -#endif /* __cplusplus */ - -#include "fal/fal_stp.h" - - sw_error_t garuda_stp_init(a_uint32_t dev_id); - -#ifdef IN_STP -#define GARUDA_STP_INIT(rv, dev_id) \ - { \ - rv = garuda_stp_init(dev_id); \ - SW_RTN_ON_ERROR(rv); \ - } -#else -#define GARUDA_STP_INIT(rv, dev_id) -#endif - -#ifdef HSL_STANDALONG - - - HSL_LOCAL sw_error_t - garuda_stp_port_state_set(a_uint32_t dev_id, a_uint32_t st_id, - fal_port_t port_id, fal_stp_state_t state); - - - - HSL_LOCAL sw_error_t - garuda_stp_port_state_get(a_uint32_t dev_id, a_uint32_t st_id, - fal_port_t port_id, fal_stp_state_t * state); - -#endif - -#ifdef __cplusplus -} -#endif /* __cplusplus */ -#endif /* _GARUDA_STP_H_ */ -/** - * @} - */ diff --git a/feeds/ipq807x/qca-ssdk/src/include/hsl/garuda/garuda_vlan.h b/feeds/ipq807x/qca-ssdk/src/include/hsl/garuda/garuda_vlan.h deleted file mode 100755 index 9eff4331b..000000000 --- a/feeds/ipq807x/qca-ssdk/src/include/hsl/garuda/garuda_vlan.h +++ /dev/null @@ -1,82 +0,0 @@ -/* - * Copyright (c) 2012, The Linux Foundation. All rights reserved. - * Permission to use, copy, modify, and/or distribute this software for - * any purpose with or without fee is hereby granted, provided that the - * above copyright notice and this permission notice appear in all copies. - * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES - * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR - * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES - * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN - * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT - * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. - */ - - -/** - * @defgroup garuda_vlan GARUDA_VLAN - * @{ - */ -#ifndef _GARUDA_VLAN_H_ -#define _GARUDA_VLAN_H_ - -#ifdef __cplusplus -extern "C" { -#endif /* __cplusplus */ - -#include "fal/fal_vlan.h" - - sw_error_t - garuda_vlan_init(a_uint32_t dev_id); - -#ifdef IN_VLAN -#define GARUDA_VLAN_INIT(rv, dev_id) \ - { \ - rv = garuda_vlan_init(dev_id); \ - SW_RTN_ON_ERROR(rv); \ - } -#else -#define GARUDA_VLAN_INIT(rv, dev_id) -#endif - -#ifdef HSL_STANDALONG - - - HSL_LOCAL sw_error_t - garuda_vlan_entry_append(a_uint32_t dev_id, const fal_vlan_t * vlan_entry); - - - - HSL_LOCAL sw_error_t - garuda_vlan_create(a_uint32_t dev_id, a_uint32_t vlan_id); - - - - HSL_LOCAL sw_error_t - garuda_vlan_next(a_uint32_t dev_id, a_uint32_t vlan_id, fal_vlan_t * p_vlan); - - - - HSL_LOCAL sw_error_t - garuda_vlan_find(a_uint32_t dev_id, a_uint32_t vlan_id, fal_vlan_t * p_vlan); - - - - HSL_LOCAL sw_error_t - garuda_vlan_member_update(a_uint32_t dev_id, a_uint32_t vlan_id, - fal_pbmp_t member, fal_pbmp_t u_member); - - - - HSL_LOCAL sw_error_t - garuda_vlan_delete(a_uint32_t dev_id, a_uint32_t vlan_id); -#endif - -#ifdef __cplusplus -} -#endif /* __cplusplus */ - -#endif /* _GARUDA_VLAN_H_ */ -/** - * @} - */ diff --git a/feeds/ipq807x/qca-ssdk/src/include/hsl/horus/horus_api.h b/feeds/ipq807x/qca-ssdk/src/include/hsl/horus/horus_api.h deleted file mode 100755 index aed76d285..000000000 --- a/feeds/ipq807x/qca-ssdk/src/include/hsl/horus/horus_api.h +++ /dev/null @@ -1,559 +0,0 @@ -/* - * Copyright (c) 2012, The Linux Foundation. All rights reserved. - * Permission to use, copy, modify, and/or distribute this software for - * any purpose with or without fee is hereby granted, provided that the - * above copyright notice and this permission notice appear in all copies. - * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES - * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR - * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES - * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN - * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT - * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. - */ - - - -#ifndef _HORUS_API_H_ -#define _HORUS_API_H_ - -#ifdef __cplusplus -extern "C" { -#endif /* __cplusplus */ - -#ifdef IN_PORTCONTROL -#define PORTCONTROL_API \ - SW_API_DEF(SW_API_PT_DUPLEX_GET, horus_port_duplex_get), \ - SW_API_DEF(SW_API_PT_DUPLEX_SET, horus_port_duplex_set), \ - SW_API_DEF(SW_API_PT_SPEED_GET, horus_port_speed_get), \ - SW_API_DEF(SW_API_PT_SPEED_SET, horus_port_speed_set), \ - SW_API_DEF(SW_API_PT_AN_GET, horus_port_autoneg_status_get), \ - SW_API_DEF(SW_API_PT_AN_ENABLE, horus_port_autoneg_enable), \ - SW_API_DEF(SW_API_PT_AN_RESTART, horus_port_autoneg_restart), \ - SW_API_DEF(SW_API_PT_AN_ADV_GET, horus_port_autoneg_adv_get), \ - SW_API_DEF(SW_API_PT_AN_ADV_SET, horus_port_autoneg_adv_set), \ - SW_API_DEF(SW_API_PT_HDR_SET, horus_port_hdr_status_set), \ - SW_API_DEF(SW_API_PT_HDR_GET, horus_port_hdr_status_get), \ - SW_API_DEF(SW_API_PT_FLOWCTRL_SET, horus_port_flowctrl_set), \ - SW_API_DEF(SW_API_PT_FLOWCTRL_GET, horus_port_flowctrl_get), \ - SW_API_DEF(SW_API_PT_FLOWCTRL_MODE_SET, horus_port_flowctrl_forcemode_set), \ - SW_API_DEF(SW_API_PT_FLOWCTRL_MODE_GET, horus_port_flowctrl_forcemode_get), \ - SW_API_DEF(SW_API_PT_POWERSAVE_SET, horus_port_powersave_set), \ - SW_API_DEF(SW_API_PT_POWERSAVE_GET, horus_port_powersave_get), \ - SW_API_DEF(SW_API_PT_HIBERNATE_SET, horus_port_hibernate_set), \ - SW_API_DEF(SW_API_PT_HIBERNATE_GET, horus_port_hibernate_get), \ - SW_API_DEF(SW_API_PT_CDT, horus_port_cdt), - -#define PORTCONTROL_API_PARAM \ - SW_API_DESC(SW_API_PT_DUPLEX_GET) \ - SW_API_DESC(SW_API_PT_DUPLEX_SET) \ - SW_API_DESC(SW_API_PT_SPEED_GET) \ - SW_API_DESC(SW_API_PT_SPEED_SET) \ - SW_API_DESC(SW_API_PT_AN_GET) \ - SW_API_DESC(SW_API_PT_AN_ENABLE) \ - SW_API_DESC(SW_API_PT_AN_RESTART) \ - SW_API_DESC(SW_API_PT_AN_ADV_GET) \ - SW_API_DESC(SW_API_PT_AN_ADV_SET) \ - SW_API_DESC(SW_API_PT_HDR_SET) \ - SW_API_DESC(SW_API_PT_HDR_GET) \ - SW_API_DESC(SW_API_PT_FLOWCTRL_SET) \ - SW_API_DESC(SW_API_PT_FLOWCTRL_GET) \ - SW_API_DESC(SW_API_PT_FLOWCTRL_MODE_SET) \ - SW_API_DESC(SW_API_PT_FLOWCTRL_MODE_GET) \ - SW_API_DESC(SW_API_PT_POWERSAVE_SET) \ - SW_API_DESC(SW_API_PT_POWERSAVE_GET) \ - SW_API_DESC(SW_API_PT_HIBERNATE_SET) \ - SW_API_DESC(SW_API_PT_HIBERNATE_GET) \ - SW_API_DESC(SW_API_PT_CDT) -#else -#define PORTCONTROL_API -#define PORTCONTROL_API_PARAM -#endif - - -#ifdef IN_VLAN -#define VLAN_API \ - SW_API_DEF(SW_API_VLAN_ADD, horus_vlan_create), \ - SW_API_DEF(SW_API_VLAN_DEL, horus_vlan_delete), \ - SW_API_DEF(SW_API_VLAN_MEM_UPDATE, horus_vlan_member_update), \ - SW_API_DEF(SW_API_VLAN_FIND, horus_vlan_find), \ - SW_API_DEF(SW_API_VLAN_NEXT, horus_vlan_next), \ - SW_API_DEF(SW_API_VLAN_APPEND, horus_vlan_entry_append), - -#define VLAN_API_PARAM \ - SW_API_DESC(SW_API_VLAN_ADD) \ - SW_API_DESC(SW_API_VLAN_DEL) \ - SW_API_DESC(SW_API_VLAN_MEM_UPDATE) \ - SW_API_DESC(SW_API_VLAN_FIND) \ - SW_API_DESC(SW_API_VLAN_NEXT) \ - SW_API_DESC(SW_API_VLAN_APPEND) -#else -#define VLAN_API -#define VLAN_API_PARAM -#endif - - -#ifdef IN_PORTVLAN -#define PORTVLAN_API \ - SW_API_DEF(SW_API_PT_ING_MODE_GET, horus_port_1qmode_get), \ - SW_API_DEF(SW_API_PT_ING_MODE_SET, horus_port_1qmode_set), \ - SW_API_DEF(SW_API_PT_EG_MODE_GET, horus_port_egvlanmode_get), \ - SW_API_DEF(SW_API_PT_EG_MODE_SET, horus_port_egvlanmode_set), \ - SW_API_DEF(SW_API_PT_VLAN_MEM_ADD, horus_portvlan_member_add), \ - SW_API_DEF(SW_API_PT_VLAN_MEM_DEL, horus_portvlan_member_del), \ - SW_API_DEF(SW_API_PT_VLAN_MEM_UPDATE, horus_portvlan_member_update), \ - SW_API_DEF(SW_API_PT_VLAN_MEM_GET, horus_portvlan_member_get), \ - SW_API_DEF(SW_API_PT_DEF_VID_SET, horus_port_default_vid_set), \ - SW_API_DEF(SW_API_PT_DEF_VID_GET, horus_port_default_vid_get), \ - SW_API_DEF(SW_API_PT_FORCE_DEF_VID_SET, horus_port_force_default_vid_set), \ - SW_API_DEF(SW_API_PT_FORCE_DEF_VID_GET, horus_port_force_default_vid_get), \ - SW_API_DEF(SW_API_PT_FORCE_PORTVLAN_SET, horus_port_force_portvlan_set), \ - SW_API_DEF(SW_API_PT_FORCE_PORTVLAN_GET, horus_port_force_portvlan_get), \ - SW_API_DEF(SW_API_NESTVLAN_TPID_SET, horus_nestvlan_tpid_set), \ - SW_API_DEF(SW_API_NESTVLAN_TPID_GET, horus_nestvlan_tpid_get), \ - SW_API_DEF(SW_API_PT_IN_VLAN_MODE_SET, horus_port_invlan_mode_set), \ - SW_API_DEF(SW_API_PT_IN_VLAN_MODE_GET, horus_port_invlan_mode_get), \ - SW_API_DEF(SW_API_PT_PRI_PROPAGATION_SET, horus_port_pri_propagation_set), \ - SW_API_DEF(SW_API_PT_PRI_PROPAGATION_GET, horus_port_pri_propagation_get), \ - SW_API_DEF(SW_API_QINQ_MODE_SET, horus_qinq_mode_set), \ - SW_API_DEF(SW_API_QINQ_MODE_GET, horus_qinq_mode_get), \ - SW_API_DEF(SW_API_PT_QINQ_ROLE_SET, horus_port_qinq_role_set), \ - SW_API_DEF(SW_API_PT_QINQ_ROLE_GET, horus_port_qinq_role_get), - -#define PORTVLAN_API_PARAM \ - SW_API_DESC(SW_API_PT_ING_MODE_GET) \ - SW_API_DESC(SW_API_PT_ING_MODE_SET) \ - SW_API_DESC(SW_API_PT_EG_MODE_GET) \ - SW_API_DESC(SW_API_PT_EG_MODE_SET) \ - SW_API_DESC(SW_API_PT_VLAN_MEM_ADD) \ - SW_API_DESC(SW_API_PT_VLAN_MEM_DEL) \ - SW_API_DESC(SW_API_PT_VLAN_MEM_UPDATE) \ - SW_API_DESC(SW_API_PT_VLAN_MEM_GET) \ - SW_API_DESC(SW_API_PT_DEF_VID_SET) \ - SW_API_DESC(SW_API_PT_DEF_VID_GET) \ - SW_API_DESC(SW_API_PT_FORCE_DEF_VID_SET) \ - SW_API_DESC(SW_API_PT_FORCE_DEF_VID_GET) \ - SW_API_DESC(SW_API_PT_FORCE_PORTVLAN_SET) \ - SW_API_DESC(SW_API_PT_FORCE_PORTVLAN_GET) \ - SW_API_DESC(SW_API_NESTVLAN_TPID_SET) \ - SW_API_DESC(SW_API_NESTVLAN_TPID_GET) \ - SW_API_DESC(SW_API_PT_IN_VLAN_MODE_SET) \ - SW_API_DESC(SW_API_PT_IN_VLAN_MODE_GET) \ - SW_API_DESC(SW_API_PT_PRI_PROPAGATION_SET) \ - SW_API_DESC(SW_API_PT_PRI_PROPAGATION_GET) \ - SW_API_DESC(SW_API_QINQ_MODE_SET) \ - SW_API_DESC(SW_API_QINQ_MODE_GET) \ - SW_API_DESC(SW_API_PT_QINQ_ROLE_SET) \ - SW_API_DESC(SW_API_PT_QINQ_ROLE_GET) -#else -#define PORTVLAN_API -#define PORTVLAN_API_PARAM -#endif - - -#ifdef IN_FDB -#define FDB_API \ - SW_API_DEF(SW_API_FDB_ADD, horus_fdb_add), \ - SW_API_DEF(SW_API_FDB_DELALL, horus_fdb_del_all), \ - SW_API_DEF(SW_API_FDB_DELPORT,horus_fdb_del_by_port), \ - SW_API_DEF(SW_API_FDB_DELMAC, horus_fdb_del_by_mac), \ - SW_API_DEF(SW_API_FDB_FIRST, horus_fdb_first), \ - SW_API_DEF(SW_API_FDB_NEXT, horus_fdb_next), \ - SW_API_DEF(SW_API_FDB_FIND, horus_fdb_find), \ - SW_API_DEF(SW_API_FDB_PT_LEARN_SET, horus_fdb_port_learn_set), \ - SW_API_DEF(SW_API_FDB_PT_LEARN_GET, horus_fdb_port_learn_get), \ - SW_API_DEF(SW_API_FDB_AGE_CTRL_SET, horus_fdb_age_ctrl_set), \ - SW_API_DEF(SW_API_FDB_AGE_CTRL_GET, horus_fdb_age_ctrl_get), \ - SW_API_DEF(SW_API_FDB_AGE_TIME_SET, horus_fdb_age_time_set), \ - SW_API_DEF(SW_API_FDB_AGE_TIME_GET, horus_fdb_age_time_get), - -#define FDB_API_PARAM \ - SW_API_DESC(SW_API_FDB_ADD) \ - SW_API_DESC(SW_API_FDB_DELALL) \ - SW_API_DESC(SW_API_FDB_DELPORT) \ - SW_API_DESC(SW_API_FDB_DELMAC) \ - SW_API_DESC(SW_API_FDB_FIRST) \ - SW_API_DESC(SW_API_FDB_NEXT) \ - SW_API_DESC(SW_API_FDB_FIND) \ - SW_API_DESC(SW_API_FDB_PT_LEARN_SET) \ - SW_API_DESC(SW_API_FDB_PT_LEARN_GET) \ - SW_API_DESC(SW_API_FDB_AGE_CTRL_SET) \ - SW_API_DESC(SW_API_FDB_AGE_CTRL_GET) \ - SW_API_DESC(SW_API_FDB_AGE_TIME_SET) \ - SW_API_DESC(SW_API_FDB_AGE_TIME_GET) -#else -#define FDB_API -#define FDB_API_PARAM -#endif - - -#ifdef IN_QOS -#define QOS_API \ - SW_API_DEF(SW_API_QOS_QU_TX_BUF_ST_SET, horus_qos_queue_tx_buf_status_set), \ - SW_API_DEF(SW_API_QOS_QU_TX_BUF_ST_GET, horus_qos_queue_tx_buf_status_get), \ - SW_API_DEF(SW_API_QOS_QU_TX_BUF_NR_SET, horus_qos_queue_tx_buf_nr_set), \ - SW_API_DEF(SW_API_QOS_QU_TX_BUF_NR_GET, horus_qos_queue_tx_buf_nr_get), \ - SW_API_DEF(SW_API_QOS_PT_TX_BUF_ST_SET, horus_qos_port_tx_buf_status_set), \ - SW_API_DEF(SW_API_QOS_PT_TX_BUF_ST_GET, horus_qos_port_tx_buf_status_get), \ - SW_API_DEF(SW_API_QOS_PT_TX_BUF_NR_SET, horus_qos_port_tx_buf_nr_set), \ - SW_API_DEF(SW_API_QOS_PT_TX_BUF_NR_GET, horus_qos_port_tx_buf_nr_get), \ - SW_API_DEF(SW_API_QOS_PT_RX_BUF_NR_SET, horus_qos_port_rx_buf_nr_set), \ - SW_API_DEF(SW_API_QOS_PT_RX_BUF_NR_GET, horus_qos_port_rx_buf_nr_get), \ - SW_API_DEF(SW_API_COSMAP_UP_QU_SET, horus_cosmap_up_queue_set), \ - SW_API_DEF(SW_API_COSMAP_UP_QU_GET, horus_cosmap_up_queue_get), \ - SW_API_DEF(SW_API_COSMAP_DSCP_QU_SET, horus_cosmap_dscp_queue_set), \ - SW_API_DEF(SW_API_COSMAP_DSCP_QU_GET, horus_cosmap_dscp_queue_get), \ - SW_API_DEF(SW_API_QOS_PT_MODE_SET, horus_qos_port_mode_set), \ - SW_API_DEF(SW_API_QOS_PT_MODE_GET, horus_qos_port_mode_get), \ - SW_API_DEF(SW_API_QOS_PT_MODE_PRI_SET, horus_qos_port_mode_pri_set), \ - SW_API_DEF(SW_API_QOS_PT_MODE_PRI_GET, horus_qos_port_mode_pri_get), \ - SW_API_DEF(SW_API_QOS_PORT_DEF_UP_SET, horus_qos_port_default_up_set), \ - SW_API_DEF(SW_API_QOS_PORT_DEF_UP_GET, horus_qos_port_default_up_get), \ - SW_API_DEF(SW_API_QOS_PORT_SCH_MODE_SET, horus_qos_port_sch_mode_set), \ - SW_API_DEF(SW_API_QOS_PORT_SCH_MODE_GET, horus_qos_port_sch_mode_get), - -#define QOS_API_PARAM \ - SW_API_DESC(SW_API_QOS_QU_TX_BUF_ST_SET) \ - SW_API_DESC(SW_API_QOS_QU_TX_BUF_ST_GET) \ - SW_API_DESC(SW_API_QOS_QU_TX_BUF_NR_SET) \ - SW_API_DESC(SW_API_QOS_QU_TX_BUF_NR_GET) \ - SW_API_DESC(SW_API_QOS_PT_TX_BUF_ST_SET) \ - SW_API_DESC(SW_API_QOS_PT_TX_BUF_ST_GET) \ - SW_API_DESC(SW_API_QOS_PT_TX_BUF_NR_SET) \ - SW_API_DESC(SW_API_QOS_PT_TX_BUF_NR_GET) \ - SW_API_DESC(SW_API_QOS_PT_RX_BUF_NR_SET) \ - SW_API_DESC(SW_API_QOS_PT_RX_BUF_NR_GET) \ - SW_API_DESC(SW_API_COSMAP_UP_QU_SET) \ - SW_API_DESC(SW_API_COSMAP_UP_QU_GET) \ - SW_API_DESC(SW_API_COSMAP_DSCP_QU_SET) \ - SW_API_DESC(SW_API_COSMAP_DSCP_QU_GET) \ - SW_API_DESC(SW_API_QOS_PT_MODE_SET) \ - SW_API_DESC(SW_API_QOS_PT_MODE_GET) \ - SW_API_DESC(SW_API_QOS_PT_MODE_PRI_SET) \ - SW_API_DESC(SW_API_QOS_PT_MODE_PRI_GET) \ - SW_API_DESC(SW_API_QOS_PORT_DEF_UP_SET) \ - SW_API_DESC(SW_API_QOS_PORT_DEF_UP_GET) \ - SW_API_DESC(SW_API_QOS_PORT_SCH_MODE_SET) \ - SW_API_DESC(SW_API_QOS_PORT_SCH_MODE_GET) -#else -#define QOS_API -#define QOS_API_PARAM -#endif - - -#ifdef IN_IGMP -#define IGMP_API \ - SW_API_DEF(SW_API_PT_IGMPS_MODE_SET, horus_port_igmps_status_set), \ - SW_API_DEF(SW_API_PT_IGMPS_MODE_GET, horus_port_igmps_status_get), \ - SW_API_DEF(SW_API_IGMP_MLD_CMD_SET, horus_igmp_mld_cmd_set), \ - SW_API_DEF(SW_API_IGMP_MLD_CMD_GET, horus_igmp_mld_cmd_get), \ - SW_API_DEF(SW_API_IGMP_PT_JOIN_SET, horus_port_igmp_mld_join_set), \ - SW_API_DEF(SW_API_IGMP_PT_JOIN_GET, horus_port_igmp_mld_join_get), \ - SW_API_DEF(SW_API_IGMP_PT_LEAVE_SET, horus_port_igmp_mld_leave_set), \ - SW_API_DEF(SW_API_IGMP_PT_LEAVE_GET, horus_port_igmp_mld_leave_get), \ - SW_API_DEF(SW_API_IGMP_RP_SET, horus_igmp_mld_rp_set), \ - SW_API_DEF(SW_API_IGMP_RP_GET, horus_igmp_mld_rp_get), \ - SW_API_DEF(SW_API_IGMP_ENTRY_CREAT_SET, horus_igmp_mld_entry_creat_set), \ - SW_API_DEF(SW_API_IGMP_ENTRY_CREAT_GET, horus_igmp_mld_entry_creat_get), \ - SW_API_DEF(SW_API_IGMP_ENTRY_STATIC_SET, horus_igmp_mld_entry_static_set), \ - SW_API_DEF(SW_API_IGMP_ENTRY_STATIC_GET, horus_igmp_mld_entry_static_get), \ - SW_API_DEF(SW_API_IGMP_ENTRY_LEAKY_SET, horus_igmp_mld_entry_leaky_set), \ - SW_API_DEF(SW_API_IGMP_ENTRY_LEAKY_GET, horus_igmp_mld_entry_leaky_get), \ - SW_API_DEF(SW_API_IGMP_ENTRY_V3_SET, horus_igmp_mld_entry_v3_set), \ - SW_API_DEF(SW_API_IGMP_ENTRY_V3_GET, horus_igmp_mld_entry_v3_get), \ - SW_API_DEF(SW_API_IGMP_ENTRY_QUEUE_SET, horus_igmp_mld_entry_queue_set), \ - SW_API_DEF(SW_API_IGMP_ENTRY_QUEUE_GET, horus_igmp_mld_entry_queue_get), \ - -#define IGMP_API_PARAM \ - SW_API_DESC(SW_API_PT_IGMPS_MODE_SET) \ - SW_API_DESC(SW_API_PT_IGMPS_MODE_GET) \ - SW_API_DESC(SW_API_IGMP_MLD_CMD_SET) \ - SW_API_DESC(SW_API_IGMP_MLD_CMD_GET) \ - SW_API_DESC(SW_API_IGMP_PT_JOIN_SET) \ - SW_API_DESC(SW_API_IGMP_PT_JOIN_GET) \ - SW_API_DESC(SW_API_IGMP_PT_LEAVE_SET) \ - SW_API_DESC(SW_API_IGMP_PT_LEAVE_GET) \ - SW_API_DESC(SW_API_IGMP_RP_SET) \ - SW_API_DESC(SW_API_IGMP_RP_GET) \ - SW_API_DESC(SW_API_IGMP_ENTRY_CREAT_SET) \ - SW_API_DESC(SW_API_IGMP_ENTRY_CREAT_GET) \ - SW_API_DESC(SW_API_IGMP_ENTRY_STATIC_SET) \ - SW_API_DESC(SW_API_IGMP_ENTRY_STATIC_GET) \ - SW_API_DESC(SW_API_IGMP_ENTRY_LEAKY_SET) \ - SW_API_DESC(SW_API_IGMP_ENTRY_LEAKY_GET) \ - SW_API_DESC(SW_API_IGMP_ENTRY_V3_SET) \ - SW_API_DESC(SW_API_IGMP_ENTRY_V3_GET) \ - SW_API_DESC(SW_API_IGMP_ENTRY_QUEUE_SET) \ - SW_API_DESC(SW_API_IGMP_ENTRY_QUEUE_GET) -#else -#define IGMP_API -#define IGMP_API_PARAM -#endif - - -#ifdef IN_LEAKY -#define LEAKY_API \ - SW_API_DEF(SW_API_UC_LEAKY_MODE_SET, horus_uc_leaky_mode_set), \ - SW_API_DEF(SW_API_UC_LEAKY_MODE_GET, horus_uc_leaky_mode_get), \ - SW_API_DEF(SW_API_MC_LEAKY_MODE_SET, horus_mc_leaky_mode_set), \ - SW_API_DEF(SW_API_MC_LEAKY_MODE_GET, horus_mc_leaky_mode_get), \ - SW_API_DEF(SW_API_ARP_LEAKY_MODE_SET, horus_port_arp_leaky_set), \ - SW_API_DEF(SW_API_ARP_LEAKY_MODE_GET, horus_port_arp_leaky_get), \ - SW_API_DEF(SW_API_PT_UC_LEAKY_MODE_SET, horus_port_uc_leaky_set), \ - SW_API_DEF(SW_API_PT_UC_LEAKY_MODE_GET, horus_port_uc_leaky_get), \ - SW_API_DEF(SW_API_PT_MC_LEAKY_MODE_SET, horus_port_mc_leaky_set), \ - SW_API_DEF(SW_API_PT_MC_LEAKY_MODE_GET, horus_port_mc_leaky_get), - -#define LEAKY_API_PARAM \ - SW_API_DESC(SW_API_UC_LEAKY_MODE_SET) \ - SW_API_DESC(SW_API_UC_LEAKY_MODE_GET) \ - SW_API_DESC(SW_API_MC_LEAKY_MODE_SET) \ - SW_API_DESC(SW_API_MC_LEAKY_MODE_GET) \ - SW_API_DESC(SW_API_ARP_LEAKY_MODE_SET) \ - SW_API_DESC(SW_API_ARP_LEAKY_MODE_GET) \ - SW_API_DESC(SW_API_PT_UC_LEAKY_MODE_SET) \ - SW_API_DESC(SW_API_PT_UC_LEAKY_MODE_GET) \ - SW_API_DESC(SW_API_PT_MC_LEAKY_MODE_SET) \ - SW_API_DESC(SW_API_PT_MC_LEAKY_MODE_GET) -#else -#define LEAKY_API -#define LEAKY_API_PARAM -#endif - - -#ifdef IN_MIRROR -#define MIRROR_API \ - SW_API_DEF(SW_API_MIRROR_ANALY_PT_SET, horus_mirr_analysis_port_set), \ - SW_API_DEF(SW_API_MIRROR_ANALY_PT_GET, horus_mirr_analysis_port_get), \ - SW_API_DEF(SW_API_MIRROR_IN_PT_SET, horus_mirr_port_in_set), \ - SW_API_DEF(SW_API_MIRROR_IN_PT_GET, horus_mirr_port_in_get), \ - SW_API_DEF(SW_API_MIRROR_EG_PT_SET, horus_mirr_port_eg_set), \ - SW_API_DEF(SW_API_MIRROR_EG_PT_GET, horus_mirr_port_eg_get), - -#define MIRROR_API_PARAM \ - SW_API_DESC(SW_API_MIRROR_ANALY_PT_SET) \ - SW_API_DESC(SW_API_MIRROR_ANALY_PT_GET) \ - SW_API_DESC(SW_API_MIRROR_IN_PT_SET) \ - SW_API_DESC(SW_API_MIRROR_IN_PT_GET) \ - SW_API_DESC(SW_API_MIRROR_EG_PT_SET) \ - SW_API_DESC(SW_API_MIRROR_EG_PT_GET) -#else -#define MIRROR_API -#define MIRROR_API_PARAM -#endif - - - -#ifdef IN_RATE -#define RATE_API \ - SW_API_DEF(SW_API_RATE_PT_EGRL_SET, horus_rate_port_egrl_set), \ - SW_API_DEF(SW_API_RATE_PT_EGRL_GET, horus_rate_port_egrl_get), \ - SW_API_DEF(SW_API_RATE_PT_INRL_SET, horus_rate_port_inrl_set), \ - SW_API_DEF(SW_API_RATE_PT_INRL_GET, horus_rate_port_inrl_get), \ - SW_API_DEF(SW_API_STORM_CTRL_FRAME_SET, horus_storm_ctrl_frame_set), \ - SW_API_DEF(SW_API_STORM_CTRL_FRAME_GET, horus_storm_ctrl_frame_get), \ - SW_API_DEF(SW_API_STORM_CTRL_RATE_SET, horus_storm_ctrl_rate_set), \ - SW_API_DEF(SW_API_STORM_CTRL_RATE_GET, horus_storm_ctrl_rate_get), - -#define RATE_API_PARAM \ - SW_API_DESC(SW_API_RATE_PT_EGRL_SET) \ - SW_API_DESC(SW_API_RATE_PT_EGRL_GET) \ - SW_API_DESC(SW_API_RATE_PT_INRL_SET) \ - SW_API_DESC(SW_API_RATE_PT_INRL_GET) \ - SW_API_DESC(SW_API_STORM_CTRL_FRAME_SET) \ - SW_API_DESC(SW_API_STORM_CTRL_FRAME_GET) \ - SW_API_DESC(SW_API_STORM_CTRL_RATE_SET) \ - SW_API_DESC(SW_API_STORM_CTRL_RATE_GET) -#else -#define RATE_API -#define RATE_API_PARAM -#endif - - -#ifdef IN_STP -#define STP_API \ - SW_API_DEF(SW_API_STP_PT_STATE_SET, horus_stp_port_state_set), \ - SW_API_DEF(SW_API_STP_PT_STATE_GET, horus_stp_port_state_get), - -#define STP_API_PARAM \ - SW_API_DESC(SW_API_STP_PT_STATE_SET) \ - SW_API_DESC(SW_API_STP_PT_STATE_GET) -#else -#define STP_API -#define STP_API_PARAM -#endif - - -#ifdef IN_MIB -#define MIB_API \ - SW_API_DEF(SW_API_PT_MIB_GET, horus_get_mib_info), \ - SW_API_DEF(SW_API_MIB_STATUS_SET, horus_mib_status_set), \ - SW_API_DEF(SW_API_MIB_STATUS_GET, horus_mib_status_get), - -#define MIB_API_PARAM \ - SW_API_DESC(SW_API_PT_MIB_GET) \ - SW_API_DESC(SW_API_MIB_STATUS_SET) \ - SW_API_DESC(SW_API_MIB_STATUS_GET) -#else -#define MIB_API -#define MIB_API_PARAM -#endif - - -#ifdef IN_MISC -#define MISC_API \ - SW_API_DEF(SW_API_ARP_STATUS_SET, horus_arp_status_set), \ - SW_API_DEF(SW_API_ARP_STATUS_GET, horus_arp_status_get), \ - SW_API_DEF(SW_API_FRAME_MAX_SIZE_SET, horus_frame_max_size_set), \ - SW_API_DEF(SW_API_FRAME_MAX_SIZE_GET, horus_frame_max_size_get), \ - SW_API_DEF(SW_API_PT_UNK_SA_CMD_SET, horus_port_unk_sa_cmd_set), \ - SW_API_DEF(SW_API_PT_UNK_SA_CMD_GET, horus_port_unk_sa_cmd_get), \ - SW_API_DEF(SW_API_PT_UNK_UC_FILTER_SET, horus_port_unk_uc_filter_set), \ - SW_API_DEF(SW_API_PT_UNK_UC_FILTER_GET, horus_port_unk_uc_filter_get), \ - SW_API_DEF(SW_API_PT_UNK_MC_FILTER_SET, horus_port_unk_mc_filter_set), \ - SW_API_DEF(SW_API_PT_UNK_MC_FILTER_GET, horus_port_unk_mc_filter_get), \ - SW_API_DEF(SW_API_PT_BC_FILTER_SET, horus_port_bc_filter_set), \ - SW_API_DEF(SW_API_PT_BC_FILTER_GET, horus_port_bc_filter_get), \ - SW_API_DEF(SW_API_CPU_PORT_STATUS_SET, horus_cpu_port_status_set), \ - SW_API_DEF(SW_API_CPU_PORT_STATUS_GET, horus_cpu_port_status_get), \ - SW_API_DEF(SW_API_PPPOE_CMD_SET, horus_pppoe_cmd_set), \ - SW_API_DEF(SW_API_PPPOE_CMD_GET, horus_pppoe_cmd_get), \ - SW_API_DEF(SW_API_PPPOE_STATUS_SET, horus_pppoe_status_set), \ - SW_API_DEF(SW_API_PPPOE_STATUS_GET, horus_pppoe_status_get), \ - SW_API_DEF(SW_API_PT_DHCP_SET, horus_port_dhcp_set), \ - SW_API_DEF(SW_API_PT_DHCP_GET, horus_port_dhcp_get), \ - SW_API_DEF(SW_API_ARP_CMD_SET, horus_arp_cmd_set), \ - SW_API_DEF(SW_API_ARP_CMD_GET, horus_arp_cmd_get), \ - SW_API_DEF(SW_API_EAPOL_CMD_SET, horus_eapol_cmd_set), \ - SW_API_DEF(SW_API_EAPOL_CMD_GET, horus_eapol_cmd_get), \ - SW_API_DEF(SW_API_EAPOL_STATUS_SET, horus_eapol_status_set), \ - SW_API_DEF(SW_API_EAPOL_STATUS_GET, horus_eapol_status_get), \ - SW_API_DEF(SW_API_RIPV1_STATUS_SET, horus_ripv1_status_set), \ - SW_API_DEF(SW_API_RIPV1_STATUS_GET, horus_ripv1_status_get), - -#define MISC_API_PARAM \ - SW_API_DESC(SW_API_ARP_STATUS_SET) \ - SW_API_DESC(SW_API_ARP_STATUS_GET) \ - SW_API_DESC(SW_API_FRAME_MAX_SIZE_SET) \ - SW_API_DESC(SW_API_FRAME_MAX_SIZE_GET) \ - SW_API_DESC(SW_API_PT_UNK_SA_CMD_SET) \ - SW_API_DESC(SW_API_PT_UNK_SA_CMD_GET) \ - SW_API_DESC(SW_API_PT_UNK_UC_FILTER_SET) \ - SW_API_DESC(SW_API_PT_UNK_UC_FILTER_GET) \ - SW_API_DESC(SW_API_PT_UNK_MC_FILTER_SET) \ - SW_API_DESC(SW_API_PT_UNK_MC_FILTER_GET) \ - SW_API_DESC(SW_API_PT_BC_FILTER_SET) \ - SW_API_DESC(SW_API_PT_BC_FILTER_GET) \ - SW_API_DESC(SW_API_CPU_PORT_STATUS_SET) \ - SW_API_DESC(SW_API_CPU_PORT_STATUS_GET) \ - SW_API_DESC(SW_API_PPPOE_CMD_SET) \ - SW_API_DESC(SW_API_PPPOE_CMD_GET) \ - SW_API_DESC(SW_API_PPPOE_STATUS_SET) \ - SW_API_DESC(SW_API_PPPOE_STATUS_GET) \ - SW_API_DESC(SW_API_PT_DHCP_SET) \ - SW_API_DESC(SW_API_PT_DHCP_GET) \ - SW_API_DESC(SW_API_ARP_CMD_SET) \ - SW_API_DESC(SW_API_ARP_CMD_GET) \ - SW_API_DESC(SW_API_EAPOL_CMD_SET) \ - SW_API_DESC(SW_API_EAPOL_CMD_GET) \ - SW_API_DESC(SW_API_EAPOL_STATUS_SET) \ - SW_API_DESC(SW_API_EAPOL_STATUS_GET) \ - SW_API_DESC(SW_API_RIPV1_STATUS_SET) \ - SW_API_DESC(SW_API_RIPV1_STATUS_GET) -#else -#define MISC_API -#define MISC_API_PARAM -#endif - - -#ifdef IN_LED -#define LED_API \ - SW_API_DEF(SW_API_LED_PATTERN_SET, horus_led_ctrl_pattern_set), \ - SW_API_DEF(SW_API_LED_PATTERN_GET, horus_led_ctrl_pattern_get), - -#define LED_API_PARAM \ - SW_API_DESC(SW_API_LED_PATTERN_SET) \ - SW_API_DESC(SW_API_LED_PATTERN_GET) -#else -#define LED_API -#define LED_API_PARAM -#endif - - -#define REG_API \ - SW_API_DEF(SW_API_PHY_GET, horus_phy_get), \ - SW_API_DEF(SW_API_PHY_SET, horus_phy_set), \ - SW_API_DEF(SW_API_REG_GET, horus_reg_get), \ - SW_API_DEF(SW_API_REG_SET, horus_reg_set), \ - SW_API_DEF(SW_API_REG_FIELD_GET, horus_reg_field_get), \ - SW_API_DEF(SW_API_REG_FIELD_SET, horus_reg_field_set), - -#define REG_API_PARAM \ - SW_API_DESC(SW_API_PHY_GET) \ - SW_API_DESC(SW_API_PHY_SET) \ - SW_API_DESC(SW_API_REG_GET) \ - SW_API_DESC(SW_API_REG_SET) \ - SW_API_DESC(SW_API_REG_FIELD_GET) \ - SW_API_DESC(SW_API_REG_FIELD_SET) - - -#define SSDK_API \ - SW_API_DEF(SW_API_SWITCH_RESET, horus_reset), \ - SW_API_DEF(SW_API_SSDK_CFG, hsl_ssdk_cfg), \ - PORTCONTROL_API \ - VLAN_API \ - PORTVLAN_API \ - FDB_API \ - QOS_API \ - IGMP_API \ - LEAKY_API \ - MIRROR_API \ - RATE_API \ - STP_API \ - MIB_API \ - MISC_API \ - LED_API \ - REG_API \ - SW_API_DEF(SW_API_MAX, NULL), - - -#define SSDK_PARAM \ - SW_PARAM_DEF(SW_API_SWITCH_RESET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \ - SW_PARAM_DEF(SW_API_SSDK_CFG, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \ - SW_PARAM_DEF(SW_API_SSDK_CFG, SW_SSDK_CFG, sizeof(ssdk_cfg_t), SW_PARAM_PTR|SW_PARAM_OUT, "ssdk configuration"), \ - MIB_API_PARAM \ - LEAKY_API_PARAM \ - MISC_API_PARAM \ - IGMP_API_PARAM \ - MIRROR_API_PARAM \ - PORTCONTROL_API_PARAM \ - PORTVLAN_API_PARAM \ - VLAN_API_PARAM \ - FDB_API_PARAM \ - QOS_API_PARAM \ - RATE_API_PARAM \ - STP_API_PARAM \ - LED_API_PARAM \ - REG_API_PARAM \ - SW_PARAM_DEF(SW_API_MAX, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), - - -#if (defined(USER_MODE) && defined(KERNEL_MODULE)) -#undef SSDK_API -#undef SSDK_PARAM - -#define SSDK_API \ - REG_API \ - SW_API_DEF(SW_API_MAX, NULL), - -#define SSDK_PARAM \ - REG_API_PARAM \ - SW_PARAM_DEF(SW_API_MAX, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), -#endif - - -#ifdef __cplusplus -} -#endif /* __cplusplus */ - -#endif /* _HORUS_API_H_ */ diff --git a/feeds/ipq807x/qca-ssdk/src/include/hsl/horus/horus_fdb.h b/feeds/ipq807x/qca-ssdk/src/include/hsl/horus/horus_fdb.h deleted file mode 100755 index 3097bab00..000000000 --- a/feeds/ipq807x/qca-ssdk/src/include/hsl/horus/horus_fdb.h +++ /dev/null @@ -1,108 +0,0 @@ -/* - * Copyright (c) 2012, The Linux Foundation. All rights reserved. - * Permission to use, copy, modify, and/or distribute this software for - * any purpose with or without fee is hereby granted, provided that the - * above copyright notice and this permission notice appear in all copies. - * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES - * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR - * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES - * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN - * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT - * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. - */ - - -/** - * @defgroup horus_fdb HORUS_FDB - * @{ - */ -#ifndef _HORUS_FDB_H_ -#define _HORUS_FDB_H_ - -#ifdef __cplusplus -extern "C" { -#endif /* __cplusplus */ - -#include "fal/fal_fdb.h" - - sw_error_t - horus_fdb_init(a_uint32_t dev_id); - -#ifdef IN_FDB -#define HORUS_FDB_INIT(rv, dev_id) \ - { \ - rv = horus_fdb_init(dev_id); \ - SW_RTN_ON_ERROR(rv); \ - } -#else -#define HORUS_FDB_INIT(rv, dev_id) -#endif - -#ifdef HSL_STANDALONG - - - HSL_LOCAL sw_error_t - horus_fdb_add(a_uint32_t dev_id, const fal_fdb_entry_t * entry); - - - HSL_LOCAL sw_error_t - horus_fdb_del_all(a_uint32_t dev_id, a_uint32_t flag); - - - HSL_LOCAL sw_error_t - horus_fdb_del_by_port(a_uint32_t dev_id, a_uint32_t port_id, a_uint32_t flag); - - - HSL_LOCAL sw_error_t - horus_fdb_del_by_mac(a_uint32_t dev_id, - const fal_fdb_entry_t *entry); - - - HSL_LOCAL sw_error_t - horus_fdb_first(a_uint32_t dev_id, fal_fdb_entry_t * entry); - - - HSL_LOCAL sw_error_t - horus_fdb_next(a_uint32_t dev_id, fal_fdb_entry_t * entry); - - - HSL_LOCAL sw_error_t - horus_fdb_find(a_uint32_t dev_id, fal_fdb_entry_t * entry); - - - HSL_LOCAL sw_error_t - horus_fdb_port_learn_set(a_uint32_t dev_id, fal_port_t port_id, - a_bool_t enable); - - - HSL_LOCAL sw_error_t - horus_fdb_port_learn_get(a_uint32_t dev_id, fal_port_t port_id, - a_bool_t *enable); - - - HSL_LOCAL sw_error_t - horus_fdb_age_ctrl_set(a_uint32_t dev_id, a_bool_t enable); - - - HSL_LOCAL sw_error_t - horus_fdb_age_ctrl_get(a_uint32_t dev_id, a_bool_t *enable); - - - HSL_LOCAL sw_error_t - horus_fdb_age_time_set(a_uint32_t dev_id, a_uint32_t * time); - - - HSL_LOCAL sw_error_t - horus_fdb_age_time_get(a_uint32_t dev_id, a_uint32_t * time); - -#endif - -#ifdef __cplusplus -} -#endif /* __cplusplus */ - -#endif /* _HORUS_FDB_H_ */ -/** - * @} - */ diff --git a/feeds/ipq807x/qca-ssdk/src/include/hsl/horus/horus_igmp.h b/feeds/ipq807x/qca-ssdk/src/include/hsl/horus/horus_igmp.h deleted file mode 100755 index e17b67a08..000000000 --- a/feeds/ipq807x/qca-ssdk/src/include/hsl/horus/horus_igmp.h +++ /dev/null @@ -1,133 +0,0 @@ -/* - * Copyright (c) 2012, The Linux Foundation. All rights reserved. - * Permission to use, copy, modify, and/or distribute this software for - * any purpose with or without fee is hereby granted, provided that the - * above copyright notice and this permission notice appear in all copies. - * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES - * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR - * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES - * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN - * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT - * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. - */ - - -/** - * @defgroup horus_igmp HORUS_IGMP - * @{ - */ -#ifndef _HORUS_IGMP_H_ -#define _HORUS_IGMP_H_ - -#ifdef __cplusplus -extern "C" { -#endif /* __cplusplus */ - -#include "fal/fal_igmp.h" - - sw_error_t - horus_igmp_init(a_uint32_t dev_id); - -#ifdef IN_IGMP -#define HORUS_IGMP_INIT(rv, dev_id) \ - { \ - rv = horus_igmp_init(dev_id); \ - SW_RTN_ON_ERROR(rv); \ - } -#else -#define HORUS_IGMP_INIT(rv, dev_id) -#endif - -#ifdef HSL_STANDALONG - - HSL_LOCAL sw_error_t - horus_port_igmps_status_set(a_uint32_t dev_id, fal_port_t port_id, a_bool_t enable); - - - HSL_LOCAL sw_error_t - horus_port_igmps_status_get(a_uint32_t dev_id, fal_port_t port_id, a_bool_t *enable); - - - HSL_LOCAL sw_error_t - horus_igmp_mld_cmd_set(a_uint32_t dev_id, fal_fwd_cmd_t cmd); - - - HSL_LOCAL sw_error_t - horus_igmp_mld_cmd_get(a_uint32_t dev_id, fal_fwd_cmd_t * cmd); - - - HSL_LOCAL sw_error_t - horus_port_igmp_mld_join_set(a_uint32_t dev_id, fal_port_t port_id, a_bool_t enable); - - - HSL_LOCAL sw_error_t - horus_port_igmp_mld_join_get(a_uint32_t dev_id, fal_port_t port_id, a_bool_t * enable); - - - HSL_LOCAL sw_error_t - horus_port_igmp_mld_leave_set(a_uint32_t dev_id, fal_port_t port_id, a_bool_t enable); - - - HSL_LOCAL sw_error_t - horus_port_igmp_mld_leave_get(a_uint32_t dev_id, fal_port_t port_id, a_bool_t * enable); - - - HSL_LOCAL sw_error_t - horus_igmp_mld_rp_set(a_uint32_t dev_id, fal_pbmp_t pts); - - - HSL_LOCAL sw_error_t - horus_igmp_mld_rp_get(a_uint32_t dev_id, fal_pbmp_t * pts); - - - HSL_LOCAL sw_error_t - horus_igmp_mld_entry_creat_set(a_uint32_t dev_id, a_bool_t enable); - - - HSL_LOCAL sw_error_t - horus_igmp_mld_entry_creat_get(a_uint32_t dev_id, a_bool_t * enable); - - - HSL_LOCAL sw_error_t - horus_igmp_mld_entry_static_set(a_uint32_t dev_id, a_bool_t enable); - - - HSL_LOCAL sw_error_t - horus_igmp_mld_entry_static_get(a_uint32_t dev_id, a_bool_t * enable); - - - HSL_LOCAL sw_error_t - horus_igmp_mld_entry_leaky_set(a_uint32_t dev_id, a_bool_t enable); - - - HSL_LOCAL sw_error_t - horus_igmp_mld_entry_leaky_get(a_uint32_t dev_id, a_bool_t * enable); - - - HSL_LOCAL sw_error_t - horus_igmp_mld_entry_v3_set(a_uint32_t dev_id, a_bool_t enable); - - - HSL_LOCAL sw_error_t - horus_igmp_mld_entry_v3_get(a_uint32_t dev_id, a_bool_t * enable); - - - HSL_LOCAL sw_error_t - horus_igmp_mld_entry_queue_set(a_uint32_t dev_id, a_bool_t enable, a_uint32_t queue); - - - HSL_LOCAL sw_error_t - horus_igmp_mld_entry_queue_get(a_uint32_t dev_id, a_bool_t * enable, a_uint32_t * queue); - - -#endif - -#ifdef __cplusplus -} -#endif /* __cplusplus */ - -#endif /* _HORUS_IGMP_H_ */ -/** - * @} - */ diff --git a/feeds/ipq807x/qca-ssdk/src/include/hsl/horus/horus_init.h b/feeds/ipq807x/qca-ssdk/src/include/hsl/horus/horus_init.h deleted file mode 100755 index 388876480..000000000 --- a/feeds/ipq807x/qca-ssdk/src/include/hsl/horus/horus_init.h +++ /dev/null @@ -1,49 +0,0 @@ -/* - * Copyright (c) 2012, The Linux Foundation. All rights reserved. - * Permission to use, copy, modify, and/or distribute this software for - * any purpose with or without fee is hereby granted, provided that the - * above copyright notice and this permission notice appear in all copies. - * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES - * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR - * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES - * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN - * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT - * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. - */ - - -/** - * @defgroup horus_init HORUS_INIT - * @{ - */ -#ifndef _HORUS_INIT_H_ -#define _HORUS_INIT_H_ - -#ifdef __cplusplus -extern "C" { -#endif /* __cplusplus */ - -#include "init/ssdk_init.h" - - - sw_error_t - horus_init(a_uint32_t dev_id, ssdk_init_cfg *cfg); - - - sw_error_t - horus_reset(a_uint32_t dev_id); - - - sw_error_t - horus_cleanup(a_uint32_t dev_id); - - -#ifdef __cplusplus -} -#endif /* __cplusplus */ - -#endif /* _HORUS_INIT_H_ */ -/** - * @} - */ diff --git a/feeds/ipq807x/qca-ssdk/src/include/hsl/horus/horus_leaky.h b/feeds/ipq807x/qca-ssdk/src/include/hsl/horus/horus_leaky.h deleted file mode 100755 index eb669995d..000000000 --- a/feeds/ipq807x/qca-ssdk/src/include/hsl/horus/horus_leaky.h +++ /dev/null @@ -1,100 +0,0 @@ -/* - * Copyright (c) 2012, The Linux Foundation. All rights reserved. - * Permission to use, copy, modify, and/or distribute this software for - * any purpose with or without fee is hereby granted, provided that the - * above copyright notice and this permission notice appear in all copies. - * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES - * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR - * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES - * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN - * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT - * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. - */ - - -/** - * @defgroup horus_leaky HORUS_LEAKY - * @{ - */ -#ifndef _HORUS_LEAKY_H_ -#define _HORUS_LEAKY_H_ - -#ifdef __cplusplus -extern "C" { -#endif /* __cplusplus */ - -#include "fal/fal_leaky.h" - - sw_error_t horus_leaky_init(a_uint32_t dev_id); - -#ifdef IN_LEAKY -#define HORUS_LEAKY_INIT(rv, dev_id) \ - { \ - rv = horus_leaky_init(dev_id); \ - SW_RTN_ON_ERROR(rv); \ - } -#else -#define HORUS_LEAKY_INIT(rv, dev_id) -#endif - -#ifdef HSL_STANDALONG - - - HSL_LOCAL sw_error_t - horus_uc_leaky_mode_set(a_uint32_t dev_id, - fal_leaky_ctrl_mode_t ctrl_mode); - - - HSL_LOCAL sw_error_t - horus_uc_leaky_mode_get(a_uint32_t dev_id, - fal_leaky_ctrl_mode_t * ctrl_mode); - - - HSL_LOCAL sw_error_t - horus_mc_leaky_mode_set(a_uint32_t dev_id, - fal_leaky_ctrl_mode_t ctrl_mode); - - - HSL_LOCAL sw_error_t - horus_mc_leaky_mode_get(a_uint32_t dev_id, - fal_leaky_ctrl_mode_t * ctrl_mode); - - - HSL_LOCAL sw_error_t - horus_port_arp_leaky_set(a_uint32_t dev_id, fal_port_t port_id, - a_bool_t enable); - - - HSL_LOCAL sw_error_t - horus_port_arp_leaky_get(a_uint32_t dev_id, fal_port_t port_id, - a_bool_t * enable); - - - HSL_LOCAL sw_error_t - horus_port_uc_leaky_set(a_uint32_t dev_id, fal_port_t port_id, - a_bool_t enable); - - - HSL_LOCAL sw_error_t - horus_port_uc_leaky_get(a_uint32_t dev_id, fal_port_t port_id, - a_bool_t * enable); - - - HSL_LOCAL sw_error_t - horus_port_mc_leaky_set(a_uint32_t dev_id, fal_port_t port_id, - a_bool_t enable); - - - HSL_LOCAL sw_error_t - horus_port_mc_leaky_get(a_uint32_t dev_id, fal_port_t port_id, - a_bool_t * enable); -#endif - -#ifdef __cplusplus -} -#endif /* __cplusplus */ -#endif /* _HORUS_LEAKY_H_ */ -/** - * @} - */ diff --git a/feeds/ipq807x/qca-ssdk/src/include/hsl/horus/horus_led.h b/feeds/ipq807x/qca-ssdk/src/include/hsl/horus/horus_led.h deleted file mode 100755 index c7d8a92cf..000000000 --- a/feeds/ipq807x/qca-ssdk/src/include/hsl/horus/horus_led.h +++ /dev/null @@ -1,55 +0,0 @@ -/* - * Copyright (c) 2012, The Linux Foundation. All rights reserved. - * Permission to use, copy, modify, and/or distribute this software for - * any purpose with or without fee is hereby granted, provided that the - * above copyright notice and this permission notice appear in all copies. - * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES - * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR - * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES - * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN - * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT - * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. - */ - - -#ifndef _HORUS_LED_H_ -#define _HORUS_LED_H_ - -#ifdef __cplusplus -extern "C" { -#endif /* __cplusplus */ - -#include "fal/fal_led.h" - - sw_error_t - horus_led_init(a_uint32_t dev_id); - -#ifdef IN_LED -#define HORUS_LED_INIT(rv, dev_id) \ - { \ - rv = horus_led_init(dev_id); \ - SW_RTN_ON_ERROR(rv); \ - } -#else -#define HORUS_LED_INIT(rv, dev_id) -#endif - -#ifdef HSL_STANDALONG - - HSL_LOCAL sw_error_t - horus_led_ctrl_pattern_set(a_uint32_t dev_id, led_pattern_group_t group, - led_pattern_id_t id, led_ctrl_pattern_t * pattern); - - - HSL_LOCAL sw_error_t - horus_led_ctrl_pattern_get(a_uint32_t dev_id, led_pattern_group_t group, - led_pattern_id_t id, led_ctrl_pattern_t * pattern); - -#endif - -#ifdef __cplusplus -} -#endif /* __cplusplus */ - -#endif /* _HORUS_LED_H_ */ diff --git a/feeds/ipq807x/qca-ssdk/src/include/hsl/horus/horus_mib.h b/feeds/ipq807x/qca-ssdk/src/include/hsl/horus/horus_mib.h deleted file mode 100755 index 6f1963e16..000000000 --- a/feeds/ipq807x/qca-ssdk/src/include/hsl/horus/horus_mib.h +++ /dev/null @@ -1,65 +0,0 @@ -/* - * Copyright (c) 2012, The Linux Foundation. All rights reserved. - * Permission to use, copy, modify, and/or distribute this software for - * any purpose with or without fee is hereby granted, provided that the - * above copyright notice and this permission notice appear in all copies. - * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES - * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR - * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES - * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN - * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT - * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. - */ - - -/** - * @defgroup horus_mib HORUS_MIB - * @{ - */ -#ifndef _HORUS_MIB_H_ -#define _HORUS_MIB_H_ - -#ifdef __cplusplus -extern "C" { -#endif /* __cplusplus */ - -#include "fal/fal_mib.h" - - sw_error_t - horus_mib_init(a_uint32_t dev_id); - -#ifdef IN_MIB -#define HORUS_MIB_INIT(rv, dev_id) \ - { \ - rv = horus_mib_init(dev_id); \ - SW_RTN_ON_ERROR(rv); \ - } -#else -#define HORUS_MIB_INIT(rv, dev_id) -#endif - -#ifdef HSL_STANDALONG - - HSL_LOCAL sw_error_t - horus_get_mib_info(a_uint32_t dev_id, fal_port_t port_id, - fal_mib_info_t * mib_info ); - - - HSL_LOCAL sw_error_t - horus_mib_status_set(a_uint32_t dev_id, a_bool_t enable); - - - HSL_LOCAL sw_error_t - horus_mib_status_get(a_uint32_t dev_id, a_bool_t * enable); - -#endif - -#ifdef __cplusplus -} -#endif /* __cplusplus */ - -#endif /* _HORUS_MIB_H_ */ -/** - * @} - */ diff --git a/feeds/ipq807x/qca-ssdk/src/include/hsl/horus/horus_mirror.h b/feeds/ipq807x/qca-ssdk/src/include/hsl/horus/horus_mirror.h deleted file mode 100755 index ae51f7e21..000000000 --- a/feeds/ipq807x/qca-ssdk/src/include/hsl/horus/horus_mirror.h +++ /dev/null @@ -1,78 +0,0 @@ -/* - * Copyright (c) 2012, The Linux Foundation. All rights reserved. - * Permission to use, copy, modify, and/or distribute this software for - * any purpose with or without fee is hereby granted, provided that the - * above copyright notice and this permission notice appear in all copies. - * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES - * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR - * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES - * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN - * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT - * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. - */ - - -/** - * @defgroup horus_mirror HORUS_MIRROR - * @{ - */ -#ifndef _HORUS_MIRROR_H_ -#define _HORUS_MIRROR_H_ - -#ifdef __cplusplus -extern "C" { -#endif /* __cplusplus */ - -#include "fal/fal_mirror.h" - - sw_error_t horus_mirr_init(a_uint32_t dev_id); - -#ifdef IN_MIRROR -#define HORUS_MIRR_INIT(rv, dev_id) \ - { \ - rv = horus_mirr_init(dev_id); \ - SW_RTN_ON_ERROR(rv); \ - } -#else -#define HORUS_MIRR_INIT(rv, dev_id) -#endif - -#ifdef HSL_STANDALONG - - HSL_LOCAL sw_error_t - horus_mirr_analysis_port_set(a_uint32_t dev_id, fal_port_t port_id); - - - HSL_LOCAL sw_error_t - horus_mirr_analysis_port_get(a_uint32_t dev_id, fal_port_t * port_id); - - - HSL_LOCAL sw_error_t - horus_mirr_port_in_set(a_uint32_t dev_id, fal_port_t port_id, - a_bool_t enable); - - - HSL_LOCAL sw_error_t - horus_mirr_port_in_get(a_uint32_t dev_id, fal_port_t port_id, - a_bool_t * enable); - - - HSL_LOCAL sw_error_t - horus_mirr_port_eg_set(a_uint32_t dev_id, fal_port_t port_id, - a_bool_t enable); - - - HSL_LOCAL sw_error_t - horus_mirr_port_eg_get(a_uint32_t dev_id, fal_port_t port_id, - a_bool_t * enable); - -#endif - -#ifdef __cplusplus -} -#endif /* __cplusplus */ -#endif /* _HORUS_MIRROR_H_ */ -/** - * @} - */ diff --git a/feeds/ipq807x/qca-ssdk/src/include/hsl/horus/horus_misc.h b/feeds/ipq807x/qca-ssdk/src/include/hsl/horus/horus_misc.h deleted file mode 100755 index 557244412..000000000 --- a/feeds/ipq807x/qca-ssdk/src/include/hsl/horus/horus_misc.h +++ /dev/null @@ -1,167 +0,0 @@ -/* - * Copyright (c) 2012, The Linux Foundation. All rights reserved. - * Permission to use, copy, modify, and/or distribute this software for - * any purpose with or without fee is hereby granted, provided that the - * above copyright notice and this permission notice appear in all copies. - * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES - * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR - * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES - * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN - * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT - * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. - */ - - -/** - * @defgroup horus_misc HORUS_MISC - * @{ - */ -#ifndef _HORUS_MISC_H_ -#define _HORUS_MISC_H_ - -#ifdef __cplusplus -extern "C" { -#endif /* __cplusplus */ - -#include "fal/fal_misc.h" - - sw_error_t horus_misc_init(a_uint32_t dev_id); - -#ifdef IN_MISC -#define HORUS_MISC_INIT(rv, dev_id) \ - { \ - rv = horus_misc_init(dev_id); \ - SW_RTN_ON_ERROR(rv); \ - } -#else -#define HORUS_MISC_INIT(rv, dev_id) -#endif - -#ifdef HSL_STANDALONG - - HSL_LOCAL sw_error_t - horus_arp_status_set(a_uint32_t dev_id, a_bool_t enable); - - - HSL_LOCAL sw_error_t - horus_arp_status_get(a_uint32_t dev_id, a_bool_t * enable); - - - HSL_LOCAL sw_error_t - horus_frame_max_size_set(a_uint32_t dev_id, a_uint32_t size); - - - HSL_LOCAL sw_error_t - horus_frame_max_size_get(a_uint32_t dev_id, a_uint32_t * size); - - - HSL_LOCAL sw_error_t - horus_port_unk_sa_cmd_set(a_uint32_t dev_id, fal_port_t port_id, - fal_fwd_cmd_t cmd); - - - HSL_LOCAL sw_error_t - horus_port_unk_sa_cmd_get(a_uint32_t dev_id, fal_port_t port_id, - fal_fwd_cmd_t * cmd); - - - HSL_LOCAL sw_error_t - horus_port_unk_uc_filter_set(a_uint32_t dev_id, fal_port_t port_id, - a_bool_t enable); - - - HSL_LOCAL sw_error_t - horus_port_unk_uc_filter_get(a_uint32_t dev_id, fal_port_t port_id, - a_bool_t * enable); - - - HSL_LOCAL sw_error_t - horus_port_unk_mc_filter_set(a_uint32_t dev_id, fal_port_t port_id, - a_bool_t enable); - - - HSL_LOCAL sw_error_t - horus_port_unk_mc_filter_get(a_uint32_t dev_id, fal_port_t port_id, - a_bool_t * enable); - - - HSL_LOCAL sw_error_t - horus_port_bc_filter_set(a_uint32_t dev_id, fal_port_t port_id, - a_bool_t enable); - - - HSL_LOCAL sw_error_t - horus_port_bc_filter_get(a_uint32_t dev_id, fal_port_t port_id, - a_bool_t * enable); - - - HSL_LOCAL sw_error_t - horus_cpu_port_status_set(a_uint32_t dev_id, a_bool_t enable); - - - HSL_LOCAL sw_error_t - horus_cpu_port_status_get(a_uint32_t dev_id, a_bool_t * enable); - - - HSL_LOCAL sw_error_t - horus_pppoe_cmd_set(a_uint32_t dev_id, fal_fwd_cmd_t cmd); - - - HSL_LOCAL sw_error_t - horus_pppoe_cmd_get(a_uint32_t dev_id, fal_fwd_cmd_t * cmd); - - - HSL_LOCAL sw_error_t - horus_pppoe_status_set(a_uint32_t dev_id, a_bool_t enable); - - - HSL_LOCAL sw_error_t - horus_pppoe_status_get(a_uint32_t dev_id, a_bool_t * enable); - - - HSL_LOCAL sw_error_t - horus_port_dhcp_set(a_uint32_t dev_id, fal_port_t port_id, a_bool_t enable); - - - HSL_LOCAL sw_error_t - horus_port_dhcp_get(a_uint32_t dev_id, fal_port_t port_id, a_bool_t * enable); - - - HSL_LOCAL sw_error_t - horus_arp_cmd_set(a_uint32_t dev_id, fal_fwd_cmd_t cmd); - - - HSL_LOCAL sw_error_t - horus_arp_cmd_get(a_uint32_t dev_id, fal_fwd_cmd_t * cmd); - - - HSL_LOCAL sw_error_t - horus_eapol_cmd_set(a_uint32_t dev_id, fal_fwd_cmd_t cmd); - - - HSL_LOCAL sw_error_t - horus_eapol_cmd_get(a_uint32_t dev_id, fal_fwd_cmd_t * cmd); - - HSL_LOCAL sw_error_t - horus_eapol_status_set(a_uint32_t dev_id, a_uint32_t port_id, a_bool_t enable); - - HSL_LOCAL sw_error_t - horus_eapol_status_get(a_uint32_t dev_id, a_uint32_t port_id, a_bool_t * enable); - - HSL_LOCAL sw_error_t - horus_ripv1_status_set(a_uint32_t dev_id, a_bool_t enable); - - HSL_LOCAL sw_error_t - horus_ripv1_status_get(a_uint32_t dev_id, a_bool_t * enable); - - -#endif - -#ifdef __cplusplus -} -#endif /* __cplusplus */ -#endif /* _HORUS_GEN_H_ */ -/** - * @} - */ diff --git a/feeds/ipq807x/qca-ssdk/src/include/hsl/horus/horus_port_ctrl.h b/feeds/ipq807x/qca-ssdk/src/include/hsl/horus/horus_port_ctrl.h deleted file mode 100755 index 580f49e61..000000000 --- a/feeds/ipq807x/qca-ssdk/src/include/hsl/horus/horus_port_ctrl.h +++ /dev/null @@ -1,145 +0,0 @@ -/* - * Copyright (c) 2012, The Linux Foundation. All rights reserved. - * Permission to use, copy, modify, and/or distribute this software for - * any purpose with or without fee is hereby granted, provided that the - * above copyright notice and this permission notice appear in all copies. - * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES - * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR - * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES - * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN - * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT - * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. - */ - - -/** - * @defgroup horus_port_ctrl HORUS_PORT_CONTROL - * @{ - */ -#ifndef _HORUS_PORT_CTRL_H_ -#define _HORUS_PORT_CTRL_H_ - -#ifdef __cplusplus -extern "C" { -#endif /* __cplusplus */ - -#include "fal/fal_port_ctrl.h" - - sw_error_t horus_port_ctrl_init(a_uint32_t dev_id); - -#ifdef IN_PORTCONTROL -#define HORUS_PORT_CTRL_INIT(rv, dev_id) \ - { \ - rv = horus_port_ctrl_init(dev_id); \ - SW_RTN_ON_ERROR(rv); \ - } -#else -#define HORUS_PORT_CTRL_INIT(rv, dev_id) -#endif - -#ifdef HSL_STANDALONG - - - HSL_LOCAL sw_error_t - horus_port_duplex_set(a_uint32_t dev_id, fal_port_t port_id, - fal_port_duplex_t duplex); - - - HSL_LOCAL sw_error_t - horus_port_duplex_get(a_uint32_t dev_id, fal_port_t port_id, - fal_port_duplex_t * pduplex); - - - HSL_LOCAL sw_error_t - horus_port_speed_set(a_uint32_t dev_id, fal_port_t port_id, - fal_port_speed_t speed); - - - HSL_LOCAL sw_error_t - horus_port_speed_get(a_uint32_t dev_id, fal_port_t port_id, - fal_port_speed_t * pspeed); - - - HSL_LOCAL sw_error_t - horus_port_autoneg_status_get(a_uint32_t dev_id, fal_port_t port_id, - a_bool_t * status); - - - HSL_LOCAL sw_error_t - horus_port_autoneg_enable(a_uint32_t dev_id, fal_port_t port_id); - - - HSL_LOCAL sw_error_t - horus_port_autoneg_restart(a_uint32_t dev_id, fal_port_t port_id); - - - HSL_LOCAL sw_error_t - horus_port_autoneg_adv_set(a_uint32_t dev_id, fal_port_t port_id, - a_uint32_t autoadv); - - - HSL_LOCAL sw_error_t - horus_port_autoneg_adv_get(a_uint32_t dev_id, fal_port_t port_id, - a_uint32_t * autoadv); - - - HSL_LOCAL sw_error_t - horus_port_hdr_status_set(a_uint32_t dev_id, fal_port_t port_id, - a_bool_t enable); - - - HSL_LOCAL sw_error_t - horus_port_hdr_status_get(a_uint32_t dev_id, fal_port_t port_id, - a_bool_t * enable); - - - HSL_LOCAL sw_error_t - horus_port_flowctrl_set(a_uint32_t dev_id, fal_port_t port_id, - a_bool_t enable); - - - HSL_LOCAL sw_error_t - horus_port_flowctrl_get(a_uint32_t dev_id, fal_port_t port_id, - a_bool_t * enable); - - - HSL_LOCAL sw_error_t - horus_port_flowctrl_forcemode_set(a_uint32_t dev_id, - fal_port_t port_id, a_bool_t enable); - - - HSL_LOCAL sw_error_t - horus_port_flowctrl_forcemode_get(a_uint32_t dev_id, - fal_port_t port_id, - a_bool_t * enable); - - HSL_LOCAL sw_error_t - horus_port_powersave_set(a_uint32_t dev_id, fal_port_t port_id, a_bool_t enable); - - - HSL_LOCAL sw_error_t - horus_port_powersave_get(a_uint32_t dev_id, fal_port_t port_id, a_bool_t *enable); - - - HSL_LOCAL sw_error_t - horus_port_hibernate_set(a_uint32_t dev_id, fal_port_t port_id, a_bool_t enable); - - - HSL_LOCAL sw_error_t - horus_port_hibernate_get(a_uint32_t dev_id, fal_port_t port_id, a_bool_t *enable); - - - HSL_LOCAL sw_error_t - horus_port_cdt(a_uint32_t dev_id, fal_port_t port_id, a_uint32_t mdi_pair, - fal_cable_status_t *cable_status, a_uint32_t *cable_len); - -#endif - -#ifdef __cplusplus -} -#endif /* __cplusplus */ -#endif /* _HORUS_PORT_CTRL_H_ */ -/** - * @} - */ diff --git a/feeds/ipq807x/qca-ssdk/src/include/hsl/horus/horus_portvlan.h b/feeds/ipq807x/qca-ssdk/src/include/hsl/horus/horus_portvlan.h deleted file mode 100755 index d1237f99c..000000000 --- a/feeds/ipq807x/qca-ssdk/src/include/hsl/horus/horus_portvlan.h +++ /dev/null @@ -1,160 +0,0 @@ -/* - * Copyright (c) 2012, The Linux Foundation. All rights reserved. - * Permission to use, copy, modify, and/or distribute this software for - * any purpose with or without fee is hereby granted, provided that the - * above copyright notice and this permission notice appear in all copies. - * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES - * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR - * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES - * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN - * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT - * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. - */ - - - -/** - * @defgroup horus_port_vlan HORUS_PORT_VLAN - * @{ - */ -#ifndef _HORUS_PORTVLAN_H_ -#define _HORUS_PORTVLAN_H_ - -#ifdef __cplusplus -extern "C" { -#endif /* __cplusplus */ - -#include "fal/fal_portvlan.h" - - sw_error_t horus_portvlan_init(a_uint32_t dev_id); - -#ifdef IN_PORTVLAN -#define HORUS_PORTVLAN_INIT(rv, dev_id) \ - { \ - rv = horus_portvlan_init(dev_id); \ - SW_RTN_ON_ERROR(rv); \ - } -#else -#define HORUS_PORTVLAN_INIT(rv, dev_id) -#endif - -#ifdef HSL_STANDALONG - - - HSL_LOCAL sw_error_t - horus_port_1qmode_set(a_uint32_t dev_id, fal_port_t port_id, - fal_pt_1qmode_t port_1qmode); - - - HSL_LOCAL sw_error_t - horus_port_1qmode_get(a_uint32_t dev_id, fal_port_t port_id, - fal_pt_1qmode_t * pport_1qmode); - - - HSL_LOCAL sw_error_t - horus_port_egvlanmode_set(a_uint32_t dev_id, fal_port_t port_id, - fal_pt_1q_egmode_t port_egvlanmode); - - - HSL_LOCAL sw_error_t - horus_port_egvlanmode_get(a_uint32_t dev_id, fal_port_t port_id, - fal_pt_1q_egmode_t * pport_egvlanmode); - - - HSL_LOCAL sw_error_t - horus_portvlan_member_add(a_uint32_t dev_id, fal_port_t port_id, - a_uint32_t mem_port_id); - - - HSL_LOCAL sw_error_t - horus_portvlan_member_del(a_uint32_t dev_id, fal_port_t port_id, - a_uint32_t mem_port_id); - - - HSL_LOCAL sw_error_t - horus_portvlan_member_update(a_uint32_t dev_id, fal_port_t port_id, - fal_pbmp_t mem_port_map); - - - HSL_LOCAL sw_error_t - horus_portvlan_member_get(a_uint32_t dev_id, fal_port_t port_id, - fal_pbmp_t * mem_port_map); - - HSL_LOCAL sw_error_t - horus_port_default_vid_set(a_uint32_t dev_id, fal_port_t port_id, a_uint32_t vid); - - HSL_LOCAL sw_error_t - horus_port_default_vid_get(a_uint32_t dev_id, fal_port_t port_id, a_uint32_t *vid); - - HSL_LOCAL sw_error_t - horus_port_force_default_vid_set(a_uint32_t dev_id, fal_port_t port_id, - a_bool_t enable); - - - HSL_LOCAL sw_error_t - horus_port_force_default_vid_get(a_uint32_t dev_id, fal_port_t port_id, a_bool_t * enable); - - - HSL_LOCAL sw_error_t - horus_port_force_portvlan_set(a_uint32_t dev_id, fal_port_t port_id, - a_bool_t enable); - - - HSL_LOCAL sw_error_t - horus_port_force_portvlan_get(a_uint32_t dev_id, fal_port_t port_id, a_bool_t * enable); - - - HSL_LOCAL sw_error_t - horus_nestvlan_tpid_set(a_uint32_t dev_id, a_uint32_t tpid); - - - HSL_LOCAL sw_error_t - horus_nestvlan_tpid_get(a_uint32_t dev_id, a_uint32_t * tpid); - - - HSL_LOCAL sw_error_t - horus_port_invlan_mode_set(a_uint32_t dev_id, fal_port_t port_id, - fal_pt_invlan_mode_t mode); - - - HSL_LOCAL sw_error_t - horus_port_invlan_mode_get(a_uint32_t dev_id, fal_port_t port_id, - fal_pt_invlan_mode_t * mode); - - HSL_LOCAL sw_error_t - horus_port_pri_propagation_set(a_uint32_t dev_id, fal_port_t port_id, - a_bool_t enable); - - - HSL_LOCAL sw_error_t - horus_port_pri_propagation_get(a_uint32_t dev_id, fal_port_t port_id, - a_bool_t * enable); - - HSL_LOCAL sw_error_t - horus_qinq_mode_set(a_uint32_t dev_id, fal_qinq_mode_t mode); - - - HSL_LOCAL sw_error_t - horus_qinq_mode_get(a_uint32_t dev_id, fal_qinq_mode_t * mode); - - - HSL_LOCAL sw_error_t - horus_port_qinq_role_set(a_uint32_t dev_id, fal_port_t port_id, fal_qinq_port_role_t role); - - - HSL_LOCAL sw_error_t - horus_port_qinq_role_get(a_uint32_t dev_id, fal_port_t port_id, fal_qinq_port_role_t * role); - - - - -#endif - -#ifdef __cplusplus -} -#endif /* __cplusplus */ -#endif /* _ATHENA_PORTVLAN_H */ -/** - * @} - */ diff --git a/feeds/ipq807x/qca-ssdk/src/include/hsl/horus/horus_qos.h b/feeds/ipq807x/qca-ssdk/src/include/hsl/horus/horus_qos.h deleted file mode 100755 index f3cf75d0e..000000000 --- a/feeds/ipq807x/qca-ssdk/src/include/hsl/horus/horus_qos.h +++ /dev/null @@ -1,164 +0,0 @@ -/* - * Copyright (c) 2012, The Linux Foundation. All rights reserved. - * Permission to use, copy, modify, and/or distribute this software for - * any purpose with or without fee is hereby granted, provided that the - * above copyright notice and this permission notice appear in all copies. - * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES - * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR - * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES - * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN - * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT - * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. - */ - - -/** - * @defgroup horus_qos HORUS_QOS - * @{ - */ -#ifndef _HORUS_QOS_H_ -#define _HORUS_QOS_H_ - -#ifdef __cplusplus -extern "C" { -#endif /* __cplusplus */ - -#include "fal/fal_qos.h" - - sw_error_t horus_qos_init(a_uint32_t dev_id); - -#ifdef IN_QOS -#define HORUS_QOS_INIT(rv, dev_id) \ - { \ - rv = horus_qos_init(dev_id); \ - SW_RTN_ON_ERROR(rv); \ - } -#else -#define HORUS_QOS_INIT(rv, dev_id) -#endif - -#ifdef HSL_STANDALONG - - - HSL_LOCAL sw_error_t - horus_qos_queue_tx_buf_status_set(a_uint32_t dev_id, - fal_port_t port_id, a_bool_t enable); - - - HSL_LOCAL sw_error_t - horus_qos_queue_tx_buf_status_get(a_uint32_t dev_id, - fal_port_t port_id, - a_bool_t * enable); - - HSL_LOCAL sw_error_t - horus_qos_port_tx_buf_status_set(a_uint32_t dev_id, fal_port_t port_id, - a_bool_t enable); - - - HSL_LOCAL sw_error_t - horus_qos_port_tx_buf_status_get(a_uint32_t dev_id, fal_port_t port_id, - a_bool_t * enable); - - - HSL_LOCAL sw_error_t - horus_qos_queue_tx_buf_nr_set(a_uint32_t dev_id, fal_port_t port_id, - fal_queue_t queue_id, - a_uint32_t * number); - - - HSL_LOCAL sw_error_t - horus_qos_queue_tx_buf_nr_get(a_uint32_t dev_id, fal_port_t port_id, - fal_queue_t queue_id, - a_uint32_t * number); - - - HSL_LOCAL sw_error_t - horus_qos_port_tx_buf_nr_set(a_uint32_t dev_id, fal_port_t port_id, - a_uint32_t * number); - - - HSL_LOCAL sw_error_t - horus_qos_port_tx_buf_nr_get(a_uint32_t dev_id, fal_port_t port_id, - a_uint32_t * number); - - - HSL_LOCAL sw_error_t - horus_qos_port_rx_buf_nr_set(a_uint32_t dev_id, fal_port_t port_id, - a_uint32_t * number); - - - HSL_LOCAL sw_error_t - horus_qos_port_rx_buf_nr_get(a_uint32_t dev_id, fal_port_t port_id, - a_uint32_t * number); - - - HSL_LOCAL sw_error_t - horus_cosmap_up_queue_set(a_uint32_t dev_id, a_uint32_t up, - fal_queue_t queue); - - - HSL_LOCAL sw_error_t - horus_cosmap_up_queue_get(a_uint32_t dev_id, a_uint32_t up, - fal_queue_t * queue); - - - HSL_LOCAL sw_error_t - horus_cosmap_dscp_queue_set(a_uint32_t dev_id, a_uint32_t dscp, - fal_queue_t queue); - - - HSL_LOCAL sw_error_t - horus_cosmap_dscp_queue_get(a_uint32_t dev_id, a_uint32_t dscp, - fal_queue_t * queue); - - - HSL_LOCAL sw_error_t - horus_qos_port_mode_set(a_uint32_t dev_id, fal_port_t port_id, - fal_qos_mode_t mode, a_bool_t enable); - - - HSL_LOCAL sw_error_t - horus_qos_port_mode_get(a_uint32_t dev_id, fal_port_t port_id, - fal_qos_mode_t mode, a_bool_t * enable); - - - HSL_LOCAL sw_error_t - horus_qos_port_mode_pri_set(a_uint32_t dev_id, fal_port_t port_id, - fal_qos_mode_t mode, a_uint32_t pri); - - - HSL_LOCAL sw_error_t - horus_qos_port_mode_pri_get(a_uint32_t dev_id, fal_port_t port_id, - fal_qos_mode_t mode, a_uint32_t * pri); - - - HSL_LOCAL sw_error_t - horus_qos_port_default_up_set(a_uint32_t dev_id, fal_port_t port_id, - a_uint32_t up); - - - HSL_LOCAL sw_error_t - horus_qos_port_default_up_get(a_uint32_t dev_id, fal_port_t port_id, - a_uint32_t * up); - - - HSL_LOCAL sw_error_t - horus_qos_port_sch_mode_set(a_uint32_t dev_id, a_uint32_t port_id, - fal_sch_mode_t mode, const a_uint32_t weight[]); - - - HSL_LOCAL sw_error_t - horus_qos_port_sch_mode_get(a_uint32_t dev_id, a_uint32_t port_id, - fal_sch_mode_t * mode, a_uint32_t weight[]); - - -#endif - -#ifdef __cplusplus -} -#endif /* __cplusplus */ -#endif /* _HORUS_QOS_H_ */ -/** - * @} - */ diff --git a/feeds/ipq807x/qca-ssdk/src/include/hsl/horus/horus_rate.h b/feeds/ipq807x/qca-ssdk/src/include/hsl/horus/horus_rate.h deleted file mode 100755 index 84b04d73f..000000000 --- a/feeds/ipq807x/qca-ssdk/src/include/hsl/horus/horus_rate.h +++ /dev/null @@ -1,89 +0,0 @@ -/* - * Copyright (c) 2012, The Linux Foundation. All rights reserved. - * Permission to use, copy, modify, and/or distribute this software for - * any purpose with or without fee is hereby granted, provided that the - * above copyright notice and this permission notice appear in all copies. - * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES - * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR - * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES - * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN - * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT - * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. - */ - - -/** - * @defgroup horus_rate HORUS_RATE - * @{ - */ -#ifndef _HORUS_RATE_H_ -#define _HORUS_RATE_H_ - -#ifdef __cplusplus -extern "C" { -#endif /* __cplusplus */ - -#include "fal/fal_rate.h" - - sw_error_t horus_rate_init(a_uint32_t dev_id); - -#ifdef IN_RATE -#define HORUS_RATE_INIT(rv, dev_id) \ - { \ - rv = horus_rate_init(dev_id); \ - SW_RTN_ON_ERROR(rv); \ - } -#else -#define HORUS_RATE_INIT(rv, dev_id) -#endif - -#ifdef HSL_STANDALONG - - HSL_LOCAL sw_error_t - horus_rate_port_egrl_set(a_uint32_t dev_id, fal_port_t port_id, - a_uint32_t * speed, a_bool_t enable); - - - HSL_LOCAL sw_error_t - horus_rate_port_egrl_get(a_uint32_t dev_id, fal_port_t port_id, - a_uint32_t * speed, a_bool_t * enable); - - - HSL_LOCAL sw_error_t - horus_rate_port_inrl_set(a_uint32_t dev_id, fal_port_t port_id, - a_uint32_t * speed, a_bool_t enable); - - - HSL_LOCAL sw_error_t - horus_rate_port_inrl_get(a_uint32_t dev_id, fal_port_t port_id, - a_uint32_t * speed, a_bool_t * enable); - - - HSL_LOCAL sw_error_t - horus_storm_ctrl_frame_set(a_uint32_t dev_id, fal_port_t port_id, - fal_storm_type_t storm_type, a_bool_t enable); - - - HSL_LOCAL sw_error_t - horus_storm_ctrl_frame_get(a_uint32_t dev_id, fal_port_t port_id, - fal_storm_type_t storm_type, a_bool_t * enable); - - - HSL_LOCAL sw_error_t - horus_storm_ctrl_rate_set(a_uint32_t dev_id, fal_port_t port_id, - a_uint32_t * rate_in_pps); - - - HSL_LOCAL sw_error_t - horus_storm_ctrl_rate_get(a_uint32_t dev_id, fal_port_t port_id, - a_uint32_t * rate_in_pps); -#endif - -#ifdef __cplusplus -} -#endif /* __cplusplus */ -#endif /* _HORUS_RATE_H_ */ -/** - * @} - */ diff --git a/feeds/ipq807x/qca-ssdk/src/include/hsl/horus/horus_reg.h b/feeds/ipq807x/qca-ssdk/src/include/hsl/horus/horus_reg.h deleted file mode 100755 index 891e2c46b..000000000 --- a/feeds/ipq807x/qca-ssdk/src/include/hsl/horus/horus_reg.h +++ /dev/null @@ -1,2431 +0,0 @@ -/* - * Copyright (c) 2012, The Linux Foundation. All rights reserved. - * Permission to use, copy, modify, and/or distribute this software for - * any purpose with or without fee is hereby granted, provided that the - * above copyright notice and this permission notice appear in all copies. - * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES - * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR - * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES - * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN - * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT - * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. - */ - - - -#ifndef _HORUS_REG_H_ -#define _HORUS_REG_H_ - -#ifdef __cplusplus -extern "C" { -#endif /* __cplusplus */ - -#define MAX_ENTRY_LEN 128 - -#define HSL_RW 1 -#define HSL_RO 0 - - - /* Garuda Mask Control Register */ -#define MASK_CTL "mask" -#define MASK_CTL_ID 0 -#define MASK_CTL_OFFSET 0x0000 -#define MASK_CTL_E_LENGTH 4 -#define MASK_CTL_E_OFFSET 0 -#define MASK_CTL_NR_E 1 - -#define SOFT_RST "mask_rst" -#define MASK_CTL_SOFT_RST_BOFFSET 31 -#define MASK_CTL_SOFT_RST_BLEN 1 -#define MASK_CTL_SOFT_RST_FLAG HSL_RW - -#define MII_CLK5_SEL "mask_clk5s" -#define MASK_CTL_MII_CLK5_SEL_BOFFSET 21 -#define MASK_CTL_MII_CLK5_SEL_BLEN 1 -#define MASK_CTL_MII_CLK5_SEL_FLAG HSL_RW - -#define MII_CLK0_SEL "mask_clk0s" -#define MASK_CTL_MII_CLK0_SEL_BOFFSET 20 -#define MASK_CTL_MII_CLK0_SEL_BLEN 1 -#define MASK_CTL_MII_CLK0_SEL_FLAG HSL_RW - -#define LOAD_EEPROM "mask_ldro" -#define MASK_CTL_LOAD_EEPROM_BOFFSET 16 -#define MASK_CTL_LOAD_EEPROM_BLEN 1 -#define MASK_CTL_LOAD_EEPROM_FLAG HSL_RW - -#define DEVICE_ID "mask_did" -#define MASK_CTL_DEVICE_ID_BOFFSET 8 -#define MASK_CTL_DEVICE_ID_BLEN 8 -#define MASK_CTL_DEVICE_ID_FLAG HSL_RO - -#define REV_ID "mask_rid" -#define MASK_CTL_REV_ID_BOFFSET 0 -#define MASK_CTL_REV_ID_BLEN 8 -#define MASK_CTL_REV_ID_FLAG HSL_RO - - - /* Garuda Mask Control Register */ -#define POSTRIP "postrip" -#define POSTRIP_ID 0 -#define POSTRIP_OFFSET 0x0008 -#define POSTRIP_E_LENGTH 4 -#define POSTRIP_E_OFFSET 0 -#define POSTRIP_NR_E 1 - -#define POWER_ON_SEL "postrip_sel" -#define POSTRIP_POWER_ON_SEL_BOFFSET 31 -#define POSTRIP_POWER_ON_SEL_BLEN 1 -#define POSTRIP_POWER_ON_SEL_FLAG HSL_RW - -#define RXDELAY_S1 "postrip_rx_s1" -#define POSTRIP_RXDELAY_S1_BOFFSET 26 -#define POSTRIP_RXDELAY_S1_BLEN 1 -#define POSTRIP_RXDELAY_S1_FLAG HSL_RW - -#define SPI_EN "postrip_spi" -#define POSTRIP_SPI_EN_BOFFSET 25 -#define POSTRIP_SPI_EN_BLEN 1 -#define POSTRIP_SPI_EN_FLAG HSL_RW - -#define LED_OPEN_EN "postrip_led" -#define POSTRIP_LED_OPEN_EN_BOFFSET 24 -#define POSTRIP_LED_OPEN_EN_BLEN 1 -#define POSTRIP_LED_OPEN_EN_FLAG HSL_RW - -#define RXDELAY_S0 "postrip_rx_s0" -#define POSTRIP_RXDELAY_S0_BOFFSET 23 -#define POSTRIP_RXDELAY_S0_BLEN 1 -#define POSTRIP_RXDELAY_S0_FLAG HSL_RW - -#define TXDELAY_S1 "postrip_tx_s1" -#define POSTRIP_TXDELAY_S1_BOFFSET 22 -#define POSTRIP_TXDELAY_S1_BLEN 1 -#define POSTRIP_TXDELAY_S1_FLAG HSL_RW - -#define TXDELAY_S0 "postrip_tx_s0" -#define POSTRIP_TXDELAY_S0_BOFFSET 21 -#define POSTRIP_TXDELAY_S0_BLEN 1 -#define POSTRIP_TXDELAY_S0_FLAG HSL_RW - -#define LPW_EXIT "postrip_lpw_exit" -#define POSTRIP_LPW_EXIT_BOFFSET 20 -#define POSTRIP_LPW_EXIT_BLEN 1 -#define POSTRIP_LPW_EXIT_FLAG HSL_RW - -#define PHY_PLL_ON "postrip_phy_pll" -#define POSTRIP_PHY_PLL_ON_BOFFSET 19 -#define POSTRIP_PHY_PLL_ON_BLEN 1 -#define POSTRIP_PHY_PLL_ON_FLAG HSL_RW - -#define MAN_ENABLE "postrip_man_en" -#define POSTRIP_MAN_ENABLE_BOFFSET 18 -#define POSTRIP_MAN_ENABLE_BLEN 1 -#define POSTRIP_MAN_ENABLE_FLAG HSL_RW - -#define LPW_STATE_EN "postrip_lpw_state" -#define POSTRIP_LPW_STATE_EN_BOFFSET 17 -#define POSTRIP_LPW_STATE_EN_BLEN 1 -#define POSTRIP_LPW_STATE_EN_FLAG HSL_RW - -#define POWER_DOWN_HW "postrip_power_down" -#define POSTRIP_POWER_DOWN_HW_BOFFSET 16 -#define POSTRIP_POWER_DOWN_HW_BLEN 1 -#define POSTRIP_POWER_DOWN_HW_FLAG HSL_RW - -#define MAC5_PHY_MODE "postrip_mac5_phy" -#define POSTRIP_MAC5_PHY_MODE_BOFFSET 15 -#define POSTRIP_MAC5_PHY_MODE_BLEN 1 -#define POSTRIP_MAC5_PHY_MODE_FLAG HSL_RW - -#define MAC5_MAC_MODE "postrip_mac5_mac" -#define POSTRIP_MAC5_MAC_MODE_BOFFSET 14 -#define POSTRIP_MAC5_MAC_MODE_BLEN 1 -#define POSTRIP_MAC5_MAC_MODE_FLAG HSL_RW - -#define DBG_MODE_I "postrip_dbg" -#define POSTRIP_DBG_MODE_I_BOFFSET 13 -#define POSTRIP_DBG_MODE_I_BLEN 1 -#define POSTRIP_DBG_MODE_I_FLAG HSL_RW - -#define HIB_PULSE_HW "postrip_hib" -#define POSTRIP_HIB_PULSE_HW_BOFFSET 12 -#define POSTRIP_HIB_PULSE_HW_BLEN 1 -#define POSTRIP_HIB_PULSE_HW_FLAG HSL_RW - -#define SEL_CLK25M "postrip_clk25" -#define POSTRIP_SEL_CLK25M_BOFFSET 11 -#define POSTRIP_SEL_CLK25M_BLEN 1 -#define POSTRIP_SEL_CLK25M_FLAG HSL_RW - -#define GATE_25M_EN "postrip_gate25" -#define POSTRIP_GATE_25M_EN_BOFFSET 10 -#define POSTRIP_GATE_25M_EN_BLEN 1 -#define POSTRIP_GATE_25M_EN_FLAG HSL_RW - -#define SEL_ANA_RST "postrip_sel_ana" -#define POSTRIP_SEL_ANA_RST_BOFFSET 9 -#define POSTRIP_SEL_ANA_RST_BLEN 1 -#define POSTRIP_SEL_ANA_RST_FLAG HSL_RW - -#define SERDES_EN "postrip_serdes_en" -#define POSTRIP_SERDES_EN_BOFFSET 8 -#define POSTRIP_SERDES_EN_BLEN 1 -#define POSTRIP_SERDES_EN_FLAG HSL_RW - -#define RGMII_TXCLK_DELAY_EN "postrip_tx_delay" -#define POSTRIP_RGMII_TXCLK_DELAY_EN_BOFFSET 7 -#define POSTRIP_RGMII_TXCLK_DELAY_EN_BLEN 1 -#define POSTRIP_RGMII_TXCLK_DELAY_EN_FLAG HSL_RW - -#define RGMII_RXCLK_DELAY_EN "postrip_rx_delay" -#define POSTRIP_RGMII_RXCLK_DELAY_EN_BOFFSET 6 -#define POSTRIP_RGMII_RXCLK_DELAY_EN_BLEN 1 -#define POSTRIP_RGMII_RXCLK_DELAY_EN_FLAG HSL_RW - -#define RTL_MODE "postrip_rtl" -#define POSTRIP_RTL_MODE_BOFFSET 5 -#define POSTRIP_RTL_MODE_BLEN 1 -#define POSTRIP_RTL_MODE_FLAG HSL_RW - -#define MAC0_MAC_MODE "postrip_mac0_mac" -#define POSTRIP_MAC0_MAC_MODE_BOFFSET 4 -#define POSTRIP_MAC0_MAC_MODE_BLEN 1 -#define POSTRIP_MAC0_MAC_MODE_FLAG HSL_RW - -#define PHY4_RGMII_EN "postrip_phy4_rgmii" -#define POSTRIP_PHY4_RGMII_EN_BOFFSET 3 -#define POSTRIP_PHY4_RGMII_EN_BLEN 1 -#define POSTRIP_PHY4_RGMII_EN_FLAG HSL_RW - -#define PHY4_GMII_EN "postrip_phy4_gmii" -#define POSTRIP_PHY4_GMII_EN_BOFFSET 2 -#define POSTRIP_PHY4_GMII_EN_BLEN 1 -#define POSTRIP_PHY4_GMII_EN_FLAG HSL_RW - -#define MAC0_RGMII_EN "postrip_mac0_rgmii" -#define POSTRIP_MAC0_RGMII_EN_BOFFSET 1 -#define POSTRIP_MAC0_RGMII_EN_BLEN 1 -#define POSTRIP_MAC0_RGMII_EN_FLAG HSL_RW - -#define MAC0_GMII_EN "postrip_mac0_gmii" -#define POSTRIP_MAC0_GMII_EN_BOFFSET 0 -#define POSTRIP_MAC0_GMII_EN_BLEN 1 -#define POSTRIP_MAC0_GMII_EN_FLAG HSL_RW - - - - /* Global Interrupt Register */ -#define GLOBAL_INT "gint" -#define GLOBAL_INT_ID 1 -#define GLOBAL_INT_OFFSET 0x0014 -#define GLOBAL_INT_E_LENGTH 4 -#define GLOBAL_INT_E_OFFSET 0 -#define GLOBAL_INT_NR_E 1 - -#define GLB_QM_ERR_CNT "gint_qmen" -#define GLOBAL_INT_GLB_QM_ERR_CNT_BOFFSET 24 -#define GLOBAL_INT_GLB_QM_ERR_CNT_BLEN 8 -#define GLOBAL_INT_GLB_QM_ERR_CNT_FLAG HSL_RO - -#define GLB_LOOKUP_ERR "gint_glblper" -#define GLOBAL_INT_GLB_LOOKUP_ERR_BOFFSET 17 -#define GLOBAL_INT_GLB_LOOKUP_ERR_BLEN 1 -#define GLOBAL_INT_GLB_LOOKUP_ERR_FLAG HSL_RW - -#define GLB_QM_ERR "gint_glbqmer" -#define GLOBAL_INT_GLB_QM_ERR_BOFFSET 16 -#define GLOBAL_INT_GLB_QM_ERR_BLEN 1 -#define GLOBAL_INT_GLB_QM_ERR_FLAG HSL_RW - -#define GLB_HW_INI_DONE "gint_hwid" -#define GLOBAL_INT_GLB_HW_INI_DONE_BOFFSET 14 -#define GLOBAL_INT_GLB_HW_INI_DONE_BLEN 1 -#define GLOBAL_INT_GLB_HW_INI_DONE_FLAG HSL_RW - -#define GLB_MIB_INI "gint_mibi" -#define GLOBAL_INT_GLB_MIB_INI_BOFFSET 13 -#define GLOBAL_INT_GLB_MIB_INI_BLEN 1 -#define GLOBAL_INT_GLB_MIB_INI_FLAG HSL_RW - -#define GLB_MIB_DONE "gint_mibd" -#define GLOBAL_INT_GLB_MIB_DONE_BOFFSET 12 -#define GLOBAL_INT_GLB_MIB_DONE_BLEN 1 -#define GLOBAL_INT_GLB_MIB_DONE_FLAG HSL_RW - -#define GLB_BIST_DONE "gint_bisd" -#define GLOBAL_INT_GLB_BIST_DONE_BOFFSET 11 -#define GLOBAL_INT_GLB_BIST_DONE_BLEN 1 -#define GLOBAL_INT_GLB_BIST_DONE_FLAG HSL_RW - -#define GLB_VT_MISS_VIO "gint_vtms" -#define GLOBAL_INT_GLB_VT_MISS_VIO_BOFFSET 10 -#define GLOBAL_INT_GLB_VT_MISS_VIO_BLEN 1 -#define GLOBAL_INT_GLB_VT_MISS_VIO_FLAG HSL_RW - -#define GLB_VT_MEM_VIO "gint_vtme" -#define GLOBAL_INT_GLB_VT_MEM_VIO_BOFFSET 9 -#define GLOBAL_INT_GLB_VT_MEM_VIO_BLEN 1 -#define GLOBAL_INT_GLB_VT_MEM_VIO_FLAG HSL_RW - -#define GLB_VT_DONE "gint_vtd" -#define GLOBAL_INT_GLB_VT_DONE_BOFFSET 8 -#define GLOBAL_INT_GLB_VT_DONE_BLEN 1 -#define GLOBAL_INT_GLB_VT_DONE_FLAG HSL_RW - -#define GLB_QM_INI "gint_qmin" -#define GLOBAL_INT_GLB_QM_INI_BOFFSET 7 -#define GLOBAL_INT_GLB_QM_INI_BLEN 1 -#define GLOBAL_INT_GLB_QM_INI_FLAG HSL_RW - -#define GLB_AT_INI "gint_atin" -#define GLOBAL_INT_GLB_AT_INI_BOFFSET 6 -#define GLOBAL_INT_GLB_AT_INI_BLEN 1 -#define GLOBAL_INT_GLB_AT_INI_FLAG HSL_RW - -#define GLB_ARL_FULL "gint_arlf" -#define GLOBAL_INT_GLB_ARL_FULL_BOFFSET 5 -#define GLOBAL_INT_GLB_ARL_FULL_BLEN 1 -#define GLOBAL_INT_GLB_ARL_FULL_FLAG HSL_RW - -#define GLB_ARL_DONE "gint_arld" -#define GLOBAL_INT_GLB_ARL_DONE_BOFFSET 4 -#define GLOBAL_INT_GLB_ARL_DONE_BLEN 1 -#define GLOBAL_INT_GLB_ARL_DONE_FLAG HSL_RW - -#define GLB_MDIO_DONE "gint_mdid" -#define GLOBAL_INT_GLB_MDIO_DONE_BOFFSET 3 -#define GLOBAL_INT_GLB_MDIO_DONE_BLEN 1 -#define GLOBAL_INT_GLB_MDIO_DONE_FLAG HSL_RW - -#define GLB_PHY_INT "gint_phyi" -#define GLOBAL_INT_GLB_PHY_INT_BOFFSET 2 -#define GLOBAL_INT_GLB_PHY_INT_BLEN 1 -#define GLOBAL_INT_GLB_PHY_INT_FLAG HSL_RW - -#define GLB_EEPROM_ERR "gint_epei" -#define GLOBAL_INT_GLB_EEPROM_ERR_BOFFSET 1 -#define GLOBAL_INT_GLB_EEPROM_ERR_BLEN 1 -#define GLOBAL_INT_GLB_EEPROM_ERR_FLAG HSL_RW - -#define GLB_EEPROM_INT "gint_epi" -#define GLOBAL_INT_GLB_EEPROM_INT_BOFFSET 0 -#define GLOBAL_INT_GLB_EEPROM_INT_BLEN 1 -#define GLOBAL_INT_GLB_EEPROM_INT_FLAG HSL_RW - - - /* Global Interrupt Mask Register */ -#define GLOBAL_INT_MASK "gintm" -#define GLOBAL_INT_MASK_ID 2 -#define GLOBAL_INT_MASK_OFFSET 0x0018 -#define GLOBAL_INT_MASK_E_LENGTH 4 -#define GLOBAL_INT_MASK_E_OFFSET 0 -#define GLOBAL_INT_MASK_NR_E 1 - -#define GLBM_LOOKUP_ERR "gintm_lpe" -#define GLOBAL_INT_MASK_GLBM_LOOKUP_ERR_BOFFSET 17 -#define GLOBAL_INT_MASK_GLBM_LOOKUP_ERR_BLEN 1 -#define GLOBAL_INT_MASK_GLBM_LOOKUP_ERR_FLAG HSL_RW - -#define GLBM_QM_ERR "gintm_qme" -#define GLOBAL_INT_MASK_GLBM_QM_ERR_BOFFSET 16 -#define GLOBAL_INT_MASK_GLBM_QM_ERR_BLEN 1 -#define GLOBAL_INT_MASK_GLBM_QM_ERR_FLAG HSL_RW - -#define GLBM_HW_INI_DONE "gintm_hwid" -#define GLOBAL_INT_MASK_GLBM_HW_INI_DONE_BOFFSET 14 -#define GLOBAL_INT_MASK_GLBM_HW_INI_DONE_BLEN 1 -#define GLOBAL_INT_MASK_GLBM_HW_INI_DONE_FLAG HSL_RW - -#define GLBM_MIB_INI "gintm_mibi" -#define GLOBAL_INT_MASK_GLBM_MIB_INI_BOFFSET 13 -#define GLOBAL_INT_MASK_GLBM_MIB_INI_BLEN 1 -#define GLOBAL_INT_MASK_GLBM_MIB_INI_FLAG HSL_RW - -#define GLBM_MIB_DONE "gintm_mibd" -#define GLOBAL_INT_MASK_GLBM_MIB_DONE_BOFFSET 12 -#define GLOBAL_INT_MASK_GLBM_MIB_DONE_BLEN 1 -#define GLOBAL_INT_MASK_GLBM_MIB_DONE_FLAG HSL_RW - -#define GLBM_BIST_DONE "gintm_bisd" -#define GLOBAL_INT_MASK_GLBM_BIST_DONE_BOFFSET 11 -#define GLOBAL_INT_MASK_GLBM_BIST_DONE_BLEN 1 -#define GLOBAL_INT_MASK_GLBM_BIST_DONE_FLAG HSL_RW - -#define GLBM_VT_MISS_VIO "gintm_vtms" -#define GLOBAL_INT_MASK_GLBM_VT_MISS_VIO_BOFFSET 10 -#define GLOBAL_INT_MASK_GLBM_VT_MISS_VIO_BLEN 1 -#define GLOBAL_INT_MASK_GLBM_VT_MISS_VIO_FLAG HSL_RW - -#define GLBM_VT_MEM_VIO "gintm_vtme" -#define GLOBAL_INT_MASK_GLBM_VT_MEM_VIO_BOFFSET 9 -#define GLOBAL_INT_MASK_GLBM_VT_MEM_VIO_BLEN 1 -#define GLOBAL_INT_MASK_GLBM_VT_MEM_VIO_FLAG HSL_RW - -#define GLBM_VT_DONE "gintm_vtd" -#define GLOBAL_INT_MASK_GLBM_VT_DONE_BOFFSET 8 -#define GLOBAL_INT_MASK_GLBM_VT_DONE_BLEN 1 -#define GLOBAL_INT_MASK_GLBM_VT_DONE_FLAG HSL_RW - -#define GLBM_QM_INI "gintm_qmin" -#define GLOBAL_INT_MASK_GLBM_QM_INI_BOFFSET 7 -#define GLOBAL_INT_MASK_GLBM_QM_INI_BLEN 1 -#define GLOBAL_INT_MASK_GLBM_QM_INI_FLAG HSL_RW - -#define GLBM_AT_INI "gintm_atin" -#define GLOBAL_INT_MASK_GLBM_AT_INI_BOFFSET 6 -#define GLOBAL_INT_MASK_GLBM_AT_INI_BLEN 1 -#define GLOBAL_INT_MASK_GLBM_AT_INI_FLAG HSL_RW - -#define GLBM_ARL_FULL "gintm_arlf" -#define GLOBAL_INT_MASK_GLBM_ARL_FULL_BOFFSET 5 -#define GLOBAL_INT_MASK_GLBM_ARL_FULL_BLEN 1 -#define GLOBAL_INT_MASK_GLBM_ARL_FULL_FLAG HSL_RW - -#define GLBM_ARL_DONE "gintm_arld" -#define GLOBAL_INT_MASK_GLBM_ARL_DONE_BOFFSET 4 -#define GLOBAL_INT_MASK_GLBM_ARL_DONE_BLEN 1 -#define GLOBAL_INT_MASK_GLBM_ARL_DONE_FLAG HSL_RW - -#define GLBM_MDIO_DONE "gintm_mdid" -#define GLOBAL_INT_MASK_GLBM_MDIO_DONE_BOFFSET 3 -#define GLOBAL_INT_MASK_GLBM_MDIO_DONE_BLEN 1 -#define GLOBAL_INT_MASK_GLBM_MDIO_DONE_FLAG HSL_RW - -#define GLBM_PHY_INT "gintm_phy" -#define GLOBAL_INT_MASK_GLBM_PHY_INT_BOFFSET 2 -#define GLOBAL_INT_MASK_GLBM_PHY_INT_BLEN 1 -#define GLOBAL_INT_MASK_GLBM_PHY_INT_FLAG HSL_RW - -#define GLBM_EEPROM_ERR "gintm_epe" -#define GLOBAL_INT_MASK_GLBM_EEPROM_ERR_BOFFSET 1 -#define GLOBAL_INT_MASK_GLBM_EEPROM_ERR_BLEN 1 -#define GLOBAL_INT_MASK_GLBM_EEPROM_ERR_FLAG HSL_RW - -#define GLBM_EEPROM_INT "gintm_ep" -#define GLOBAL_INT_MASK_GLBM_EEPROM_INT_BOFFSET 0 -#define GLOBAL_INT_MASK_GLBM_EEPROM_INT_BLEN 1 -#define GLOBAL_INT_MASK_GLBM_EEPROM_INT_FLAG HSL_RW - - - /* Global MAC Address Register */ -#define GLOBAL_MAC_ADDR0 "gmac0" -#define GLOBAL_MAC_ADDR0_ID 3 -#define GLOBAL_MAC_ADDR0_OFFSET 0x0020 -#define GLOBAL_MAC_ADDR0_E_LENGTH 4 -#define GLOBAL_MAC_ADDR0_E_OFFSET 0 -#define GLOBAL_MAC_ADDR0_NR_E 1 - -#define GLB_BYTE4 "gmac_b4" -#define GLOBAL_MAC_ADDR0_GLB_BYTE4_BOFFSET 8 -#define GLOBAL_MAC_ADDR0_GLB_BYTE4_BLEN 8 -#define GLOBAL_MAC_ADDR0_GLB_BYTE4_FLAG HSL_RW - -#define GLB_BYTE5 "gmac_b5" -#define GLOBAL_MAC_ADDR0_GLB_BYTE5_BOFFSET 0 -#define GLOBAL_MAC_ADDR0_GLB_BYTE5_BLEN 8 -#define GLOBAL_MAC_ADDR0_GLB_BYTE5_FLAG HSL_RW - -#define GLOBAL_MAC_ADDR1 "gmac1" -#define GLOBAL_MAC_ADDR1_ID 4 -#define GLOBAL_MAC_ADDR1_OFFSET 0x0024 -#define GLOBAL_MAC_ADDR1_E_LENGTH 4 -#define GLOBAL_MAC_ADDR1_E_OFFSET 0 -#define GLOBAL_MAC_ADDR1_NR_E 1 - -#define GLB_BYTE0 "gmac_b0" -#define GLOBAL_MAC_ADDR1_GLB_BYTE0_BOFFSET 24 -#define GLOBAL_MAC_ADDR1_GLB_BYTE0_BLEN 8 -#define GLOBAL_MAC_ADDR1_GLB_BYTE0_FLAG HSL_RW - -#define GLB_BYTE1 "gmac_b1" -#define GLOBAL_MAC_ADDR1_GLB_BYTE1_BOFFSET 16 -#define GLOBAL_MAC_ADDR1_GLB_BYTE1_BLEN 8 -#define GLOBAL_MAC_ADDR1_GLB_BYTE1_FLAG HSL_RW - -#define GLB_BYTE2 "gmac_b2" -#define GLOBAL_MAC_ADDR1_GLB_BYTE2_BOFFSET 8 -#define GLOBAL_MAC_ADDR1_GLB_BYTE2_BLEN 8 -#define GLOBAL_MAC_ADDR1_GLB_BYTE2_FLAG HSL_RW - -#define GLB_BYTE3 "gmac_b3" -#define GLOBAL_MAC_ADDR1_GLB_BYTE3_BOFFSET 0 -#define GLOBAL_MAC_ADDR1_GLB_BYTE3_BLEN 8 -#define GLOBAL_MAC_ADDR1_GLB_BYTE3_FLAG HSL_RW - - - /* Flood Mask Register */ -#define FLOOD_MASK "fmask" -#define FLOOD_MASK_ID 5 -#define FLOOD_MASK_OFFSET 0x002c -#define FLOOD_MASK_E_LENGTH 4 -#define FLOOD_MASK_E_OFFSET 0 -#define FLOOD_MASK_NR_E 1 - -#define BC_FLOOD_DP "fmask_bfdp" -#define FLOOD_MASK_BC_FLOOD_DP_BOFFSET 25 -#define FLOOD_MASK_BC_FLOOD_DP_BLEN 6 -#define FLOOD_MASK_BC_FLOOD_DP_FLAG HSL_RW - -#define ARL_UNI_LEAKY "fmask_aulky" -#define FLOOD_MASK_ARL_UNI_LEAKY_BOFFSET 24 -#define FLOOD_MASK_ARL_UNI_LEAKY_BLEN 1 -#define FLOOD_MASK_ARL_UNI_LEAKY_FLAG HSL_RW - -#define ARL_MUL_LEAKY "fmask_amlky" -#define FLOOD_MASK_ARL_MUL_LEAKY_BOFFSET 23 -#define FLOOD_MASK_ARL_MUL_LEAKY_BLEN 1 -#define FLOOD_MASK_ARL_MUL_LEAKY_FLAG HSL_RW - -#define MUL_FLOOD_DP "fmask_mfdp" -#define FLOOD_MASK_MUL_FLOOD_DP_BOFFSET 16 -#define FLOOD_MASK_MUL_FLOOD_DP_BLEN 6 -#define FLOOD_MASK_MUL_FLOOD_DP_FLAG HSL_RW - -#define IGMP_DP "fmask_igmpdp" -#define FLOOD_MASK_IGMP_DP_BOFFSET 8 -#define FLOOD_MASK_IGMP_DP_BLEN 6 -#define FLOOD_MASK_IGMP_DP_FLAG HSL_RW - -#define UNI_FLOOD_DP "fmask_ufdp" -#define FLOOD_MASK_UNI_FLOOD_DP_BOFFSET 0 -#define FLOOD_MASK_UNI_FLOOD_DP_BLEN 6 -#define FLOOD_MASK_UNI_FLOOD_DP_FLAG HSL_RW - - - /* Global Control Register */ -#define GLOBAL_CTL "gctl" -#define GLOBAL_CTL_ID 5 -#define GLOBAL_CTL_OFFSET 0x0030 -#define GLOBAL_CTL_E_LENGTH 4 -#define GLOBAL_CTL_E_OFFSET 0 -#define GLOBAL_CTL_NR_E 1 - -#define RATE_DROP_EN "gctl_rden" -#define GLOBAL_CTL_RATE_DROP_EN_BOFFSET 29 -#define GLOBAL_CTL_RATE_DROP_EN_BLEN 1 -#define GLOBAL_CTL_RATE_DROP_EN_FLAG HSL_RW - -#define QM_PRI_MODE "gctl_qmpm" -#define GLOBAL_CTL_QM_PRI_MODE_BOFFSET 28 -#define GLOBAL_CTL_QM_PRI_MODE_BLEN 1 -#define GLOBAL_CTL_QM_PRI_MODE_FLAG HSL_RW - -#define RATE_CRE_LIMIT "gctl_rcrl" -#define GLOBAL_CTL_RATE_CRE_LIMIT_BOFFSET 26 -#define GLOBAL_CTL_RATE_CRE_LIMIT_BLEN 2 -#define GLOBAL_CTL_RATE_CRE_LIMIT_FLAG HSL_RW - -#define RATE_TIME_SLOT "gctl_rtms" -#define GLOBAL_CTL_RATE_TIME_SLOT_BOFFSET 24 -#define GLOBAL_CTL_RATE_TIME_SLOT_BLEN 2 -#define GLOBAL_CTL_RATE_TIME_SLOT_FLAG HSL_RW - -#define RELOAD_TIMER "gctl_rdtm" -#define GLOBAL_CTL_RELOAD_TIMER_BOFFSET 20 -#define GLOBAL_CTL_RELOAD_TIMER_BLEN 4 -#define GLOBAL_CTL_RELOAD_TIMER_FLAG HSL_RW - -#define QM_CNT_LOCK "gctl_qmcl" -#define GLOBAL_CTL_QM_CNT_LOCK_BOFFSET 19 -#define GLOBAL_CTL_QM_CNT_LOCK_BLEN 1 -#define GLOBAL_CTL_QM_CNT_LOCK_FLAG HSL_RO - -#define BROAD_DROP_EN "gctl_bden" -#define GLOBAL_CTL_BROAD_DROP_EN_BOFFSET 18 -#define GLOBAL_CTL_BROAD_DROP_EN_BLEN 1 -#define GLOBAL_CTL_BROAD_DROP_EN_FLAG HSL_RW - -#define MAX_FRAME_SIZE "gctl_mfsz" -#define GLOBAL_CTL_MAX_FRAME_SIZE_BOFFSET 0 -#define GLOBAL_CTL_MAX_FRAME_SIZE_BLEN 14 -#define GLOBAL_CTL_MAX_FRAME_SIZE_FLAG HSL_RW - - - /* Flow Control Register */ -#define FLOW_CTL0 "fctl" -#define FLOW_CTL0_ID 6 -#define FLOW_CTL0_OFFSET 0x0034 -#define FLOW_CTL0_E_LENGTH 4 -#define FLOW_CTL0_E_OFFSET 0 -#define FLOW_CTL0_NR_E 1 - -#define TEST_PAUSE "fctl_tps" -#define FLOW_CTL0_TEST_PAUSE_BOFFSET 31 -#define FLOW_CTL0_TEST_PAUSE_BLEN 1 -#define FLOW_CTL0_TEST_PAUSE_FLAG HSL_RW - - -#define GOL_PAUSE_ON_THRES "fctl_gont" -#define FLOW_CTL0_GOL_PAUSE_ON_THRES_BOFFSET 16 -#define FLOW_CTL0_GOL_PAUSE_ON_THRES_BLEN 8 -#define FLOW_CTL0_GOL_PAUSE_ON_THRES_FLAG HSL_RW - -#define GOL_PAUSE_OFF_THRES "fctl_gofft" -#define FLOW_CTL0_GOL_PAUSE_OFF_THRES_BOFFSET 0 -#define FLOW_CTL0_GOL_PAUSE_OFF_THRES_BLEN 8 -#define FLOW_CTL0_GOL_PAUSE_OFF_THRES_FLAG HSL_RW - - - - - /* Flow Control1 Register */ -#define FLOW_CTL1 "fctl1" -#define FLOW_CTL1_ID 6 -#define FLOW_CTL1_OFFSET 0x0038 -#define FLOW_CTL1_E_LENGTH 4 -#define FLOW_CTL1_E_OFFSET 0 -#define FLOW_CTL1_NR_E 1 - -#define PORT_PAUSE_ON_THRES "fctl1_pont" -#define FLOW_CTL1_PORT_PAUSE_ON_THRES_BOFFSET 16 -#define FLOW_CTL1_PORT_PAUSE_ON_THRES_BLEN 8 -#define FLOW_CTL1_PORT_PAUSE_ON_THRES_FLAG HSL_RW - -#define PORT_PAUSE_OFF_THRES "fctl1_pofft" -#define FLOW_CTL1_PORT_PAUSE_OFF_THRES_BOFFSET 0 -#define FLOW_CTL1_PORT_PAUSE_OFF_THRES_BLEN 8 -#define FLOW_CTL1_PORT_PAUSE_OFF_THRES_FLAG HSL_RW - - - - - /* QM Control Register */ -#define QM_CTL "qmct" -#define QM_CTL_ID 7 -#define QM_CTL_OFFSET 0x003c -#define QM_CTL_E_LENGTH 4 -#define QM_CTL_E_OFFSET 0 -#define QM_CTL_NR_E 1 - -#define QM_ERR_RST_EN "qmct_qeren" -#define QM_CTL_QM_ERR_RST_EN_BOFFSET 31 -#define QM_CTL_QM_ERR_RST_EN_BLEN 1 -#define QM_CTL_QM_ERR_RST_EN_FLAG HSL_RW - -#define LOOKUP_ERR_RST_EN "qmct_lpesen" -#define QM_CTL_LOOKUP_ERR_RST_EN_BOFFSET 30 -#define QM_CTL_LOOKUP_ERR_RST_EN_BLEN 1 -#define QM_CTL_LOOKUP_ERR_RST_EN_FLAG HSL_RW - -#define IGMP_JOIN_STATIC "qmct_igmpjs" -#define QM_CTL_IGMP_JOIN_STATIC_BOFFSET 24 -#define QM_CTL_IGMP_JOIN_STATIC_BLEN 4 -#define QM_CTL_IGMP_JOIN_STATIC_FLAG HSL_RW - -#define IGMP_JOIN_LEAKY "qmct_igmpjl" -#define QM_CTL_IGMP_JOIN_LEAKY_BOFFSET 23 -#define QM_CTL_IGMP_JOIN_LEAKY_BLEN 1 -#define QM_CTL_IGMP_JOIN_LEAKY_FLAG HSL_RW - -#define IGMP_CREAT_EN "qmct_igmpcrt" -#define QM_CTL_IGMP_CREAT_EN_BOFFSET 22 -#define QM_CTL_IGMP_CREAT_EN_BLEN 1 -#define QM_CTL_IGMP_CREAT_EN_FLAG HSL_RW - -#define PPPOE_RDT_EN "qmct_pppoerdten" -#define QM_CTL_PPPOE_RDT_EN_BOFFSET 20 -#define QM_CTL_PPPOE_RDT_EN_BLEN 1 -#define QM_CTL_PPPOE_RDT_EN_FLAG HSL_RW - -#define IGMP_V3_EN "qmct_igmpv3e" -#define QM_CTL_IGMP_V3_EN_BOFFSET 19 -#define QM_CTL_IGMP_V3_EN_BLEN 1 -#define QM_CTL_IGMP_V3_EN_FLAG HSL_RW - -#define IGMP_PRI_EN "qmct_igmpprie" -#define QM_CTL_IGMP_PRI_EN_BOFFSET 18 -#define QM_CTL_IGMP_PRI_EN_BLEN 1 -#define QM_CTL_IGMP_PRI_EN_FLAG HSL_RW - -#define IGMP_PRI "qmct_igmppri" -#define QM_CTL_IGMP_PRI_BOFFSET 16 -#define QM_CTL_IGMP_PRI_BLEN 2 -#define QM_CTL_IGMP_PRI_FLAG HSL_RW - -#define ARP_EN "qmct_arpe" -#define QM_CTL_ARP_EN_BOFFSET 15 -#define QM_CTL_ARP_EN_BLEN 1 -#define QM_CTL_ARP_EN_FLAG HSL_RW - -#define ARP_CMD "qmct_arpc" -#define QM_CTL_ARP_CMD_BOFFSET 14 -#define QM_CTL_ARP_CMD_BLEN 1 -#define QM_CTL_ARP_CMD_FLAG HSL_RW - -#define RIP_CPY_EN "qmct_ripcpyen" -#define QM_CTL_RIP_CPY_EN_BOFFSET 13 -#define QM_CTL_RIP_CPY_EN_BLEN 1 -#define QM_CTL_RIP_CPY_EN_FLAG HSL_RW - -#define EAPOL_CMD "qmct_eapolc" -#define QM_CTL_EAPOL_CMD_BOFFSET 12 -#define QM_CTL_EAPOL_CMD_BLEN 1 -#define QM_CTL_EAPOL_CMD_FLAG HSL_RW - -#define IGMP_COPY_EN "qmct_igmpcpy" -#define QM_CTL_IGMP_COPY_EN_BOFFSET 11 -#define QM_CTL_IGMP_COPY_EN_BLEN 1 -#define QM_CTL_IGMP_COPY_EN_FLAG HSL_RW - -#define PPPOE_EN "qmct_pppoeen" -#define QM_CTL_PPPOE_EN_BOFFSET 10 -#define QM_CTL_PPPOE_EN_BLEN 1 -#define QM_CTL_PPPOE_EN_FLAG HSL_RW - -#define QM_FUNC_TEST "qmct_qmft" -#define QM_CTL_QM_FUNC_TEST_BOFFSET 9 -#define QM_CTL_QM_FUNC_TEST_BLEN 1 -#define QM_CTL_QM_FUNC_TEST_FLAG HSL_RW - -#define MS_FC_EN "qmct_msfe" -#define QM_CTL_MS_FC_EN_BOFFSET 8 -#define QM_CTL_MS_FC_EN_BLEN 1 -#define QM_CTL_MS_FC_EN_FLAG HSL_RW - -#define FLOW_DROP_EN "qmct_fden" -#define QM_CTL_FLOW_DROP_EN_BOFFSET 7 -#define QM_CTL_FLOW_DROP_EN_BLEN 1 -#define QM_CTL_FLOW_DROP_EN_FLAG HSL_RW - -#define MANAGE_VID_VIO_DROP_EN "qmct_mden" -#define QM_CTL_MANAGE_VID_VIO_DROP_EN_BOFFSET 6 -#define QM_CTL_MANAGE_VID_VIO_DROP_EN_BLEN 1 -#define QM_CTL_MANAGE_VID_VIO_DROP_EN_FLAG HSL_RW - -#define FLOW_DROP_CNT "qmct_fdcn" -#define QM_CTL_FLOW_DROP_CNT_BOFFSET 0 -#define QM_CTL_FLOW_DROP_CNT_BLEN 6 -#define QM_CTL_FLOW_DROP_CNT_FLAG HSL_RW - - - /* Vlan Table Function Register */ -#define VLAN_TABLE_FUNC0 "vtbf0" -#define VLAN_TABLE_FUNC0_ID 9 -#define VLAN_TABLE_FUNC0_OFFSET 0x0040 -#define VLAN_TABLE_FUNC0_E_LENGTH 4 -#define VLAN_TABLE_FUNC0_E_OFFSET 0 -#define VLAN_TABLE_FUNC0_NR_E 1 - -#define VT_PRI_EN "vtbf_vtpen" -#define VLAN_TABLE_FUNC0_VT_PRI_EN_BOFFSET 31 -#define VLAN_TABLE_FUNC0_VT_PRI_EN_BLEN 1 -#define VLAN_TABLE_FUNC0_VT_PRI_EN_FLAG HSL_RW - -#define VT_PRI "vtbf_vtpri" -#define VLAN_TABLE_FUNC0_VT_PRI_BOFFSET 28 -#define VLAN_TABLE_FUNC0_VT_PRI_BLEN 3 -#define VLAN_TABLE_FUNC0_VT_PRI_FLAG HSL_RW - -#define VLAN_ID "vtbf_vid" -#define VLAN_TABLE_FUNC0_VLAN_ID_BOFFSET 16 -#define VLAN_TABLE_FUNC0_VLAN_ID_BLEN 12 -#define VLAN_TABLE_FUNC0_VLAN_ID_FLAG HSL_RW - -#define VT_PORT_NUM "vtbf_vtpn" -#define VLAN_TABLE_FUNC0_VT_PORT_NUM_BOFFSET 8 -#define VLAN_TABLE_FUNC0_VT_PORT_NUM_BLEN 4 -#define VLAN_TABLE_FUNC0_VT_PORT_NUM_FLAG HSL_RW - -#define VT_FULL_VIO "vtbf_vtflv" -#define VLAN_TABLE_FUNC0_VT_FULL_VIO_BOFFSET 4 -#define VLAN_TABLE_FUNC0_VT_FULL_VIO_BLEN 1 -#define VLAN_TABLE_FUNC0_VT_FULL_VIO_FLAG HSL_RW - -#define VT_BUSY "vtbf_vtbs" -#define VLAN_TABLE_FUNC0_VT_BUSY_BOFFSET 3 -#define VLAN_TABLE_FUNC0_VT_BUSY_BLEN 1 -#define VLAN_TABLE_FUNC0_VT_BUSY_FLAG HSL_RW - -#define VT_FUNC "vtbf_vtfc" -#define VLAN_TABLE_FUNC0_VT_FUNC_BOFFSET 0 -#define VLAN_TABLE_FUNC0_VT_FUNC_BLEN 3 -#define VLAN_TABLE_FUNC0_VT_FUNC_FLAG HSL_RW - -#define VLAN_TABLE_FUNC1 "vtbf1" -#define VLAN_TABLE_FUNC1_ID 10 -#define VLAN_TABLE_FUNC1_OFFSET 0x0044 -#define VLAN_TABLE_FUNC1_E_LENGTH 4 -#define VLAN_TABLE_FUNC1_E_OFFSET 0 -#define VLAN_TABLE_FUNC1_NR_E 1 - -#define VT_VALID "vtbf_vtvd" -#define VLAN_TABLE_FUNC1_VT_VALID_BOFFSET 11 -#define VLAN_TABLE_FUNC1_VT_VALID_BLEN 1 -#define VLAN_TABLE_FUNC1_VT_VALID_FLAG HSL_RW - -#define LEARN_DIS "vtbf_ldis" -#define VLAN_TABLE_FUNC1_LEARN_DIS_BOFFSET 10 -#define VLAN_TABLE_FUNC1_LEARN_DIS_BLEN 1 -#define VLAN_TABLE_FUNC1_LEARN_DIS_FLAG HSL_RW - -#define VID_MEM "vtbf_vidm" -#define VLAN_TABLE_FUNC1_VID_MEM_BOFFSET 0 -#define VLAN_TABLE_FUNC1_VID_MEM_BLEN 6 -#define VLAN_TABLE_FUNC1_VID_MEM_FLAG HSL_RW - - - /* Address Table Function Register */ -#define ADDR_TABLE_FUNC0 "atbf0" -#define ADDR_TABLE_FUNC0_ID 11 -#define ADDR_TABLE_FUNC0_OFFSET 0x0050 -#define ADDR_TABLE_FUNC0_E_LENGTH 4 -#define ADDR_TABLE_FUNC0_E_OFFSET 0 -#define ADDR_TABLE_FUNC0_NR_E 1 - -#define AT_ADDR_BYTE4 "atbf_adb4" -#define ADDR_TABLE_FUNC0_AT_ADDR_BYTE4_BOFFSET 24 -#define ADDR_TABLE_FUNC0_AT_ADDR_BYTE4_BLEN 8 -#define ADDR_TABLE_FUNC0_AT_ADDR_BYTE4_FLAG HSL_RW - -#define AT_ADDR_BYTE5 "atbf_adb5" -#define ADDR_TABLE_FUNC0_AT_ADDR_BYTE5_BOFFSET 16 -#define ADDR_TABLE_FUNC0_AT_ADDR_BYTE5_BLEN 8 -#define ADDR_TABLE_FUNC0_AT_ADDR_BYTE5_FLAG HSL_RW - -#define AT_FULL_VIO "atbf_atfv" -#define ADDR_TABLE_FUNC0_AT_FULL_VIO_BOFFSET 12 -#define ADDR_TABLE_FUNC0_AT_FULL_VIO_BLEN 1 -#define ADDR_TABLE_FUNC0_AT_FULL_VIO_FLAG HSL_RW - -#define AT_PORT_NUM "atbf_atpn" -#define ADDR_TABLE_FUNC0_AT_PORT_NUM_BOFFSET 8 -#define ADDR_TABLE_FUNC0_AT_PORT_NUM_BLEN 4 -#define ADDR_TABLE_FUNC0_AT_PORT_NUM_FLAG HSL_RW - -#define FLUSH_ST_EN "atbf_fsen" -#define ADDR_TABLE_FUNC0_FLUSH_ST_EN_BOFFSET 4 -#define ADDR_TABLE_FUNC0_FLUSH_ST_EN_BLEN 1 -#define ADDR_TABLE_FUNC0_FLUSH_ST_EN_FLAG HSL_RW - -#define AT_BUSY "atbf_atbs" -#define ADDR_TABLE_FUNC0_AT_BUSY_BOFFSET 3 -#define ADDR_TABLE_FUNC0_AT_BUSY_BLEN 1 -#define ADDR_TABLE_FUNC0_AT_BUSY_FLAG HSL_RW - -#define AT_FUNC "atbf_atfc" -#define ADDR_TABLE_FUNC0_AT_FUNC_BOFFSET 0 -#define ADDR_TABLE_FUNC0_AT_FUNC_BLEN 3 -#define ADDR_TABLE_FUNC0_AT_FUNC_FLAG HSL_RW - -#define ADDR_TABLE_FUNC1 "atbf1" -#define ADDR_TABLE_FUNC1_ID 12 -#define ADDR_TABLE_FUNC1_OFFSET 0x0054 -#define ADDR_TABLE_FUNC1_E_LENGTH 4 -#define ADDR_TABLE_FUNC1_E_OFFSET 0 -#define ADDR_TABLE_FUNC1_NR_E 0 - -#define AT_ADDR_BYTE0 "atbf_adb0" -#define ADDR_TABLE_FUNC1_AT_ADDR_BYTE0_BOFFSET 24 -#define ADDR_TABLE_FUNC1_AT_ADDR_BYTE0_BLEN 8 -#define ADDR_TABLE_FUNC1_AT_ADDR_BYTE0_FLAG HSL_RW - -#define AT_ADDR_BYTE1 "atbf_adb1" -#define ADDR_TABLE_FUNC1_AT_ADDR_BYTE1_BOFFSET 16 -#define ADDR_TABLE_FUNC1_AT_ADDR_BYTE1_BLEN 8 -#define ADDR_TABLE_FUNC1_AT_ADDR_BYTE1_FLAG HSL_RW - -#define AT_ADDR_BYTE2 "atbf_adb2" -#define ADDR_TABLE_FUNC1_AT_ADDR_BYTE2_BOFFSET 8 -#define ADDR_TABLE_FUNC1_AT_ADDR_BYTE2_BLEN 8 -#define ADDR_TABLE_FUNC1_AT_ADDR_BYTE2_FLAG HSL_RW - -#define AT_ADDR_BYTE3 "atbf_adb3" -#define ADDR_TABLE_FUNC1_AT_ADDR_BYTE3_BOFFSET 0 -#define ADDR_TABLE_FUNC1_AT_ADDR_BYTE3_BLEN 8 -#define ADDR_TABLE_FUNC1_AT_ADDR_BYTE3_FLAG HSL_RW - -#define ADDR_TABLE_FUNC2 "atbf2" -#define ADDR_TABLE_FUNC2_ID 13 -#define ADDR_TABLE_FUNC2_OFFSET 0x0058 -#define ADDR_TABLE_FUNC2_E_LENGTH 4 -#define ADDR_TABLE_FUNC2_E_OFFSET 0 -#define ADDR_TABLE_FUNC2_NR_E 0 - -#define COPY_TO_CPU "atbf_cpcpu" -#define ADDR_TABLE_FUNC2_COPY_TO_CPU_BOFFSET 26 -#define ADDR_TABLE_FUNC2_COPY_TO_CPU_BLEN 1 -#define ADDR_TABLE_FUNC2_COPY_TO_CPU_FLAG HSL_RW - -#define REDRCT_TO_CPU "atbf_rdcpu" -#define ADDR_TABLE_FUNC2_REDRCT_TO_CPU_BOFFSET 25 -#define ADDR_TABLE_FUNC2_REDRCT_TO_CPU_BLEN 1 -#define ADDR_TABLE_FUNC2_REDRCT_TO_CPU_FLAG HSL_RW - -#define LEAKY_EN "atbf_lkyen" -#define ADDR_TABLE_FUNC2_LEAKY_EN_BOFFSET 24 -#define ADDR_TABLE_FUNC2_LEAKY_EN_BLEN 1 -#define ADDR_TABLE_FUNC2_LEAKY_EN_FLAG HSL_RW - -#define AT_STATUS "atbf_atsts" -#define ADDR_TABLE_FUNC2_AT_STATUS_BOFFSET 16 -#define ADDR_TABLE_FUNC2_AT_STATUS_BLEN 4 -#define ADDR_TABLE_FUNC2_AT_STATUS_FLAG HSL_RW - -#define CLONE_EN "atbf_clone" -#define ADDR_TABLE_FUNC2_CLONE_EN_BOFFSET 15 -#define ADDR_TABLE_FUNC2_CLONE_EN_BLEN 1 -#define ADDR_TABLE_FUNC2_CLONE_EN_FLAG HSL_RW - -#define SA_DROP_EN "atbf_saden" -#define ADDR_TABLE_FUNC2_SA_DROP_EN_BOFFSET 14 -#define ADDR_TABLE_FUNC2_SA_DROP_EN_BLEN 1 -#define ADDR_TABLE_FUNC2_SA_DROP_EN_FLAG HSL_RW - -#define MIRROR_EN "atbf_miren" -#define ADDR_TABLE_FUNC2_MIRROR_EN_BOFFSET 13 -#define ADDR_TABLE_FUNC2_MIRROR_EN_BLEN 1 -#define ADDR_TABLE_FUNC2_MIRROR_EN_FLAG HSL_RW - -#define AT_PRI_EN "atbf_atpen" -#define ADDR_TABLE_FUNC2_AT_PRI_EN_BOFFSET 12 -#define ADDR_TABLE_FUNC2_AT_PRI_EN_BLEN 1 -#define ADDR_TABLE_FUNC2_AT_PRI_EN_FLAG HSL_RW - -#define AT_PRI "atbf_atpri" -#define ADDR_TABLE_FUNC2_AT_PRI_BOFFSET 10 -#define ADDR_TABLE_FUNC2_AT_PRI_BLEN 2 -#define ADDR_TABLE_FUNC2_AT_PRI_FLAG HSL_RW - -#define CROSS_PT "atbf_cpt" -#define ADDR_TABLE_FUNC2_CROSS_PT_BOFFSET 8 -#define ADDR_TABLE_FUNC2_CROSS_PT_BLEN 1 -#define ADDR_TABLE_FUNC2_CROSS_PT_FLAG HSL_RW - -#define DES_PORT "atbf_desp" -#define ADDR_TABLE_FUNC2_DES_PORT_BOFFSET 0 -#define ADDR_TABLE_FUNC2_DES_PORT_BLEN 6 -#define ADDR_TABLE_FUNC2_DES_PORT_FLAG HSL_RW - - - /* Address Table Control Register */ -#define ADDR_TABLE_CTL "atbc" -#define ADDR_TABLE_CTL_ID 14 -#define ADDR_TABLE_CTL_OFFSET 0x005C -#define ADDR_TABLE_CTL_E_LENGTH 4 -#define ADDR_TABLE_CTL_E_OFFSET 0 -#define ADDR_TABLE_CTL_NR_E 1 - -#define LOOP_CH_TIME "atbc_lct" -#define ADDR_TABLE_CTL_LOOP_CH_TIME_BOFFSET 24 -#define ADDR_TABLE_CTL_LOOP_CH_TIMEP_BLEN 3 -#define ADDR_TABLE_CTL_LOOP_CH_TIME_FLAG HSL_RW - -#define RESVID_DROP "atbc_rviddrop" -#define ADDR_TABLE_CTL_RESVID_DROP_BOFFSET 22 -#define ADDR_TABLE_CTL_RESVID_DROP_BLEN 1 -#define ADDR_TABLE_CTL_RESVID_DROP_FLAG HSL_RW - -#define STAG_MODE "atbc_stag" -#define ADDR_TABLE_CTL_STAG_MODE_BOFFSET 21 -#define ADDR_TABLE_CTL_STAG_MODE_BLEN 1 -#define ADDR_TABLE_CTL_STAG_MODE_FLAG HSL_RW - -#define ARL_INI_EN "atbc_arlie" -#define ADDR_TABLE_CTL_ARL_INI_EN_BOFFSET 19 -#define ADDR_TABLE_CTL_ARL_INI_EN_BLEN 1 -#define ADDR_TABLE_CTL_ARL_INI_EN_FLAG HSL_RW - -#define LEARN_CHANGE_EN "atbc_lcen" -#define ADDR_TABLE_CTL_LEARN_CHANGE_EN_BOFFSET 18 -#define ADDR_TABLE_CTL_LEARN_CHANGE_EN_BLEN 1 -#define ADDR_TABLE_CTL_LEARN_CHANGE_EN_FLAG HSL_RW - -#define AGE_EN "atbc_agee" -#define ADDR_TABLE_CTL_AGE_EN_BOFFSET 17 -#define ADDR_TABLE_CTL_AGE_EN_BLEN 1 -#define ADDR_TABLE_CTL_AGE_EN_FLAG HSL_RW - -#define AGE_TIME "atbc_aget" -#define ADDR_TABLE_CTL_AGE_TIME_BOFFSET 0 -#define ADDR_TABLE_CTL_AGE_TIME_BLEN 16 -#define ADDR_TABLE_CTL_AGE_TIME_FLAG HSL_RW - - - /* IP Priority Mapping Register */ -#define IP_PRI_MAPPING "imap" -#define IP_PRI_MAPPING_ID 15 -#define IP_PRI_MAPPING_OFFSET 0x0060 -#define IP_PRI_MAPPING_E_LENGTH 4 -#define IP_PRI_MAPPING_E_OFFSET 0 -#define IP_PRI_MAPPING_NR_E 1 - - - /* IP Priority Mapping Register */ -#define IP_PRI_MAPPING0 "imap0" -#define IP_PRI_MAPPING0_ID 15 -#define IP_PRI_MAPPING0_OFFSET 0x0060 -#define IP_PRI_MAPPING0_E_LENGTH 4 -#define IP_PRI_MAPPING0_E_OFFSET 0 -#define IP_PRI_MAPPING0_NR_E 0 - -#define IP_0X3C "imap_ip3c" -#define IP_PRI_MAPPING0_IP_0X3C_BOFFSET 30 -#define IP_PRI_MAPPING0_IP_0X3C_BLEN 2 -#define IP_PRI_MAPPING0_IP_0X3C_FLAG HSL_RW - -#define IP_0X38 "imap_ip38" -#define IP_PRI_MAPPING0_IP_0X38_BOFFSET 28 -#define IP_PRI_MAPPING0_IP_0X38_BLEN 2 -#define IP_PRI_MAPPING0_IP_0X38_FLAG HSL_RW - -#define IP_0X34 "imap_ip34" -#define IP_PRI_MAPPING0_IP_0X34_BOFFSET 26 -#define IP_PRI_MAPPING0_IP_0X34_BLEN 2 -#define IP_PRI_MAPPING0_IP_0X34_FLAG HSL_RW - -#define IP_0X30 "imap_ip30" -#define IP_PRI_MAPPING0_IP_0X30_BOFFSET 24 -#define IP_PRI_MAPPING0_IP_0X30_BLEN 2 -#define IP_PRI_MAPPING0_IP_0X30_FLAG HSL_RW - -#define IP_0X2C "imap_ip2c" -#define IP_PRI_MAPPING0_IP_0X2C_BOFFSET 22 -#define IP_PRI_MAPPING0_IP_0X2C_BLEN 2 -#define IP_PRI_MAPPING0_IP_0X2C_FLAG HSL_RW - -#define IP_0X28 "imap_ip28" -#define IP_PRI_MAPPING0_IP_0X28_BOFFSET 20 -#define IP_PRI_MAPPING0_IP_0X28_BLEN 2 -#define IP_PRI_MAPPING0_IP_0X28_FLAG HSL_RW - -#define IP_0X24 "imap_ip24" -#define IP_PRI_MAPPING0_IP_0X24_BOFFSET 18 -#define IP_PRI_MAPPING0_IP_0X24_BLEN 2 -#define IP_PRI_MAPPING0_IP_0X24_FLAG HSL_RW - -#define IP_0X20 "imap_ip20" -#define IP_PRI_MAPPING0_IP_0X20_BOFFSET 16 -#define IP_PRI_MAPPING0_IP_0X20_BLEN 2 -#define IP_PRI_MAPPING0_IP_0X20_FLAG HSL_RW - -#define IP_0X1C "imap_ip1c" -#define IP_PRI_MAPPING0_IP_0X1C_BOFFSET 14 -#define IP_PRI_MAPPING0_IP_0X1C_BLEN 2 -#define IP_PRI_MAPPING0_IP_0X1C_FLAG HSL_RW - -#define IP_0X18 "imap_ip18" -#define IP_PRI_MAPPING0_IP_0X18_BOFFSET 12 -#define IP_PRI_MAPPING0_IP_0X18_BLEN 2 -#define IP_PRI_MAPPING0_IP_0X18_FLAG HSL_RW - -#define IP_0X14 "imap_ip14" -#define IP_PRI_MAPPING0_IP_0X14_BOFFSET 10 -#define IP_PRI_MAPPING0_IP_0X14_BLEN 2 -#define IP_PRI_MAPPING0_IP_0X14_FLAG HSL_RW - -#define IP_0X10 "imap_ip10" -#define IP_PRI_MAPPING0_IP_0X10_BOFFSET 8 -#define IP_PRI_MAPPING0_IP_0X10_BLEN 2 -#define IP_PRI_MAPPING0_IP_0X10_FLAG HSL_RW - -#define IP_0X0C "imap_ip0c" -#define IP_PRI_MAPPING0_IP_0X0C_BOFFSET 6 -#define IP_PRI_MAPPING0_IP_0X0C_BLEN 2 -#define IP_PRI_MAPPING0_IP_0X0C_FLAG HSL_RW - -#define IP_0X08 "imap_ip08" -#define IP_PRI_MAPPING0_IP_0X08_BOFFSET 4 -#define IP_PRI_MAPPING0_IP_0X08_BLEN 2 -#define IP_PRI_MAPPING0_IP_0X08_FLAG HSL_RW - -#define IP_0X04 "imap_ip04" -#define IP_PRI_MAPPING0_IP_0X04_BOFFSET 2 -#define IP_PRI_MAPPING0_IP_0X04_BLEN 2 -#define IP_PRI_MAPPING0_IP_0X04_FLAG HSL_RW - -#define IP_0X00 "imap_ip00" -#define IP_PRI_MAPPING0_IP_0X00_BOFFSET 0 -#define IP_PRI_MAPPING0_IP_0X00_BLEN 2 -#define IP_PRI_MAPPING0_IP_0X00_FLAG HSL_RW - -#define IP_PRI_MAPPING1 "imap1" -#define IP_PRI_MAPPING1_ID 16 -#define IP_PRI_MAPPING1_OFFSET 0x0064 -#define IP_PRI_MAPPING1_E_LENGTH 4 -#define IP_PRI_MAPPING1_E_OFFSET 0 -#define IP_PRI_MAPPING1_NR_E 0 - -#define IP_0X7C "imap_ip7c" -#define IP_PRI_MAPPING1_IP_0X7C_BOFFSET 30 -#define IP_PRI_MAPPING1_IP_0X7C_BLEN 2 -#define IP_PRI_MAPPING1_IP_0X7C_FLAG HSL_RW - -#define IP_0X78 "imap_ip78" -#define IP_PRI_MAPPING1_IP_0X78_BOFFSET 28 -#define IP_PRI_MAPPING1_IP_0X78_BLEN 2 -#define IP_PRI_MAPPING1_IP_0X78_FLAG HSL_RW - -#define IP_0X74 "imap_ip74" -#define IP_PRI_MAPPING1_IP_0X74_BOFFSET 26 -#define IP_PRI_MAPPING1_IP_0X74_BLEN 2 -#define IP_PRI_MAPPING1_IP_0X74_FLAG HSL_RW - -#define IP_0X70 "imap_ip70" -#define IP_PRI_MAPPING1_IP_0X70_BOFFSET 24 -#define IP_PRI_MAPPING1_IP_0X70_BLEN 2 -#define IP_PRI_MAPPING1_IP_0X70_FLAG HSL_RW - -#define IP_0X6C "imap_ip6c" -#define IP_PRI_MAPPING1_IP_0X6C_BOFFSET 22 -#define IP_PRI_MAPPING1_IP_0X6C_BLEN 2 -#define IP_PRI_MAPPING1_IP_0X6C_FLAG HSL_RW - -#define IP_0X68 "imap_ip68" -#define IP_PRI_MAPPING1_IP_0X68_BOFFSET 20 -#define IP_PRI_MAPPING1_IP_0X68_BLEN 2 -#define IP_PRI_MAPPING1_IP_0X68_FLAG HSL_RW - -#define IP_0X64 "imap_ip64" -#define IP_PRI_MAPPING1_IP_0X64_BOFFSET 18 -#define IP_PRI_MAPPING1_IP_0X64_BLEN 2 -#define IP_PRI_MAPPING1_IP_0X64_FLAG HSL_RW - -#define IP_0X60 "imap_ip60" -#define IP_PRI_MAPPING1_IP_0X60_BOFFSET 16 -#define IP_PRI_MAPPING1_IP_0X60_BLEN 2 -#define IP_PRI_MAPPING1_IP_0X60_FLAG HSL_RW - -#define IP_0X5C "imap_ip5c" -#define IP_PRI_MAPPING1_IP_0X5C_BOFFSET 14 -#define IP_PRI_MAPPING1_IP_0X5C_BLEN 2 -#define IP_PRI_MAPPING1_IP_0X5C_FLAG HSL_RW - -#define IP_0X58 "imap_ip58" -#define IP_PRI_MAPPING1_IP_0X58_BOFFSET 12 -#define IP_PRI_MAPPING1_IP_0X58_BLEN 2 -#define IP_PRI_MAPPING1_IP_0X58_FLAG HSL_RW - -#define IP_0X54 "imap_ip54" -#define IP_PRI_MAPPING1_IP_0X54_BOFFSET 10 -#define IP_PRI_MAPPING1_IP_0X54_BLEN 2 -#define IP_PRI_MAPPING1_IP_0X54_FLAG HSL_RW - -#define IP_0X50 "imap_ip50" -#define IP_PRI_MAPPING1_IP_0X50_BOFFSET 8 -#define IP_PRI_MAPPING1_IP_0X50_BLEN 2 -#define IP_PRI_MAPPING1_IP_0X50_FLAG HSL_RW - -#define IP_0X4C "imap_ip4c" -#define IP_PRI_MAPPING1_IP_0X4C_BOFFSET 6 -#define IP_PRI_MAPPING1_IP_0X4C_BLEN 2 -#define IP_PRI_MAPPING1_IP_0X4C_FLAG HSL_RW - -#define IP_0X48 "imap_ip48" -#define IP_PRI_MAPPING1_IP_0X48_BOFFSET 4 -#define IP_PRI_MAPPING1_IP_0X48_BLEN 2 -#define IP_PRI_MAPPING1_IP_0X48_FLAG HSL_RW - -#define IP_0X44 "imap_ip44" -#define IP_PRI_MAPPING1_IP_0X44_BOFFSET 2 -#define IP_PRI_MAPPING1_IP_0X44_BLEN 2 -#define IP_PRI_MAPPING1_IP_0X44_FLAG HSL_RW - -#define IP_0X40 "imap_ip40" -#define IP_PRI_MAPPING1_IP_0X40_BOFFSET 0 -#define IP_PRI_MAPPING1_IP_0X40_BLEN 2 -#define IP_PRI_MAPPING1_IP_0X40_FLAG HSL_RW - - -#define IP_PRI_MAPPING2 "imap2" -#define IP_PRI_MAPPING2_ID 17 -#define IP_PRI_MAPPING2_OFFSET 0x0068 -#define IP_PRI_MAPPING2_E_LENGTH 4 -#define IP_PRI_MAPPING2_E_OFFSET 0 -#define IP_PRI_MAPPING2_NR_E 0 - -#define IP_0XBC "imap_ipbc" -#define IP_PRI_MAPPING2_IP_0XBC_BOFFSET 30 -#define IP_PRI_MAPPING2_IP_0XBC_BLEN 2 -#define IP_PRI_MAPPING2_IP_0XBC_FLAG HSL_RW - -#define IP_0XB8 "imap_ipb8" -#define IP_PRI_MAPPING2_IP_0XB8_BOFFSET 28 -#define IP_PRI_MAPPING2_IP_0XB8_BLEN 2 -#define IP_PRI_MAPPING2_IP_0XB8_FLAG HSL_RW - -#define IP_0XB4 "imap_ipb4" -#define IP_PRI_MAPPING2_IP_0XB4_BOFFSET 26 -#define IP_PRI_MAPPING2_IP_0XB4_BLEN 2 -#define IP_PRI_MAPPING2_IP_0XB4_FLAG HSL_RW - -#define IP_0XB0 "imap_ipb0" -#define IP_PRI_MAPPING2_IP_0XB0_BOFFSET 24 -#define IP_PRI_MAPPING2_IP_0XB0_BLEN 2 -#define IP_PRI_MAPPING2_IP_0XB0_FLAG HSL_RW - -#define IP_0XAC "imap_ipac" -#define IP_PRI_MAPPING2_IP_0XAC_BOFFSET 22 -#define IP_PRI_MAPPING2_IP_0XAC_BLEN 2 -#define IP_PRI_MAPPING2_IP_0XAC_FLAG HSL_RW - -#define IP_0XA8 "imap_ipa8" -#define IP_PRI_MAPPING2_IP_0XA8_BOFFSET 20 -#define IP_PRI_MAPPING2_IP_0XA8_BLEN 2 -#define IP_PRI_MAPPING2_IP_0XA8_FLAG HSL_RW - -#define IP_0XA4 "imap_ipa4" -#define IP_PRI_MAPPING2_IP_0XA4_BOFFSET 18 -#define IP_PRI_MAPPING2_IP_0XA4_BLEN 2 -#define IP_PRI_MAPPING2_IP_0XA4_FLAG HSL_RW - -#define IP_0XA0 "imap_ipa0" -#define IP_PRI_MAPPING2_IP_0XA0_BOFFSET 16 -#define IP_PRI_MAPPING2_IP_0XA0_BLEN 2 -#define IP_PRI_MAPPING2_IP_0XA0_FLAG HSL_RW - -#define IP_0X9C "imap_ip9c" -#define IP_PRI_MAPPING2_IP_0X9C_BOFFSET 14 -#define IP_PRI_MAPPING2_IP_0X9C_BLEN 2 -#define IP_PRI_MAPPING2_IP_0X9C_FLAG HSL_RW - -#define IP_0X98 "imap_ip98" -#define IP_PRI_MAPPING2_IP_0X98_BOFFSET 12 -#define IP_PRI_MAPPING2_IP_0X98_BLEN 2 -#define IP_PRI_MAPPING2_IP_0X98_FLAG HSL_RW - -#define IP_0X94 "imap_ip94" -#define IP_PRI_MAPPING2_IP_0X94_BOFFSET 10 -#define IP_PRI_MAPPING2_IP_0X94_BLEN 2 -#define IP_PRI_MAPPING2_IP_0X94_FLAG HSL_RW - -#define IP_0X90 "imap_ip90" -#define IP_PRI_MAPPING2_IP_0X90_BOFFSET 8 -#define IP_PRI_MAPPING2_IP_0X90_BLEN 2 -#define IP_PRI_MAPPING2_IP_0X90_FLAG HSL_RW - -#define IP_0X8C "imap_ip8c" -#define IP_PRI_MAPPING2_IP_0X8C_BOFFSET 6 -#define IP_PRI_MAPPING2_IP_0X8C_BLEN 2 -#define IP_PRI_MAPPING2_IP_0X8C_FLAG HSL_RW - -#define IP_0X88 "imap_ip88" -#define IP_PRI_MAPPING2_IP_0X88_BOFFSET 4 -#define IP_PRI_MAPPING2_IP_0X88_BLEN 2 -#define IP_PRI_MAPPING2_IP_0X88_FLAG HSL_RW - -#define IP_0X84 "imap_ip84" -#define IP_PRI_MAPPING2_IP_0X84_BOFFSET 2 -#define IP_PRI_MAPPING2_IP_0X84_BLEN 2 -#define IP_PRI_MAPPING2_IP_0X84_FLAG HSL_RW - -#define IP_0X80 "imap_ip80" -#define IP_PRI_MAPPING2_IP_0X80_BOFFSET 0 -#define IP_PRI_MAPPING2_IP_0X80_BLEN 2 -#define IP_PRI_MAPPING2_IP_0X80_FLAG HSL_RW - -#define IP_PRI_MAPPING3 "imap3" -#define IP_PRI_MAPPING3_ID 18 -#define IP_PRI_MAPPING3_OFFSET 0x006C -#define IP_PRI_MAPPING3_E_LENGTH 4 -#define IP_PRI_MAPPING3_E_OFFSET 0 -#define IP_PRI_MAPPING3_NR_E 0 - -#define IP_0XFC "imap_ipfc" -#define IP_PRI_MAPPING3_IP_0XFC_BOFFSET 30 -#define IP_PRI_MAPPING3_IP_0XFC_BLEN 2 -#define IP_PRI_MAPPING3_IP_0XFC_FLAG HSL_RW - -#define IP_0XF8 "imap_ipf8" -#define IP_PRI_MAPPING3_IP_0XF8_BOFFSET 28 -#define IP_PRI_MAPPING3_IP_0XF8_BLEN 2 -#define IP_PRI_MAPPING3_IP_0XF8_FLAG HSL_RW - -#define IP_0XF4 "imap_ipf4" -#define IP_PRI_MAPPING3_IP_0XF4_BOFFSET 26 -#define IP_PRI_MAPPING3_IP_0XF4_BLEN 2 -#define IP_PRI_MAPPING3_IP_0XF4_FLAG HSL_RW - -#define IP_0XF0 "imap_ipf0" -#define IP_PRI_MAPPING3_IP_0XF0_BOFFSET 24 -#define IP_PRI_MAPPING3_IP_0XF0_BLEN 2 -#define IP_PRI_MAPPING3_IP_0XF0_FLAG HSL_RW - -#define IP_0XEC "imap_ipec" -#define IP_PRI_MAPPING3_IP_0XEC_BOFFSET 22 -#define IP_PRI_MAPPING3_IP_0XEC_BLEN 2 -#define IP_PRI_MAPPING3_IP_0XEC_FLAG HSL_RW - -#define IP_0XE8 "imap_ipe8" -#define IP_PRI_MAPPING3_IP_0XE8_BOFFSET 20 -#define IP_PRI_MAPPING3_IP_0XE8_BLEN 2 -#define IP_PRI_MAPPING3_IP_0XE8_FLAG HSL_RW - -#define IP_0XE4 "imap_ipe4" -#define IP_PRI_MAPPING3_IP_0XE4_BOFFSET 18 -#define IP_PRI_MAPPING3_IP_0XE4_BLEN 2 -#define IP_PRI_MAPPING3_IP_0XE4_FLAG HSL_RW - -#define IP_0XE0 "imap_ipe0" -#define IP_PRI_MAPPING3_IP_0XE0_BOFFSET 16 -#define IP_PRI_MAPPING3_IP_0XE0_BLEN 2 -#define IP_PRI_MAPPING3_IP_0XE0_FLAG HSL_RW - -#define IP_0XDC "imap_ipdc" -#define IP_PRI_MAPPING3_IP_0XDC_BOFFSET 14 -#define IP_PRI_MAPPING3_IP_0XDC_BLEN 2 -#define IP_PRI_MAPPING3_IP_0XDC_FLAG HSL_RW - -#define IP_0XD8 "imap_ipd8" -#define IP_PRI_MAPPING3_IP_0XD8_BOFFSET 12 -#define IP_PRI_MAPPING3_IP_0XD8_BLEN 2 -#define IP_PRI_MAPPING3_IP_0XD8_FLAG HSL_RW - -#define IP_0XD4 "imap_ipd4" -#define IP_PRI_MAPPING3_IP_0XD4_BOFFSET 10 -#define IP_PRI_MAPPING3_IP_0XD4_BLEN 2 -#define IP_PRI_MAPPING3_IP_0XD4_FLAG HSL_RW - -#define IP_0XD0 "imap_ipd0" -#define IP_PRI_MAPPING3_IP_0XD0_BOFFSET 8 -#define IP_PRI_MAPPING3_IP_0XD0_BLEN 2 -#define IP_PRI_MAPPING3_IP_0XD0_FLAG HSL_RW - -#define IP_0XCC "imap_ipcc" -#define IP_PRI_MAPPING3_IP_0XCC_BOFFSET 6 -#define IP_PRI_MAPPING3_IP_0XCC_BLEN 2 -#define IP_PRI_MAPPING3_IP_0XCC_FLAG HSL_RW - -#define IP_0XC8 "imap_ipc8" -#define IP_PRI_MAPPING3_IP_0XC8_BOFFSET 4 -#define IP_PRI_MAPPING3_IP_0XC8_BLEN 2 -#define IP_PRI_MAPPING3_IP_0XC8_FLAG HSL_RW - -#define IP_0XC4 "imap_ipc4" -#define IP_PRI_MAPPING3_IP_0XC4_BOFFSET 2 -#define IP_PRI_MAPPING3_IP_0XC4_BLEN 2 -#define IP_PRI_MAPPING3_IP_0XC4_FLAG HSL_RW - -#define IP_0XC0 "imap_ipc0" -#define IP_PRI_MAPPING3_IP_0XC0_BOFFSET 0 -#define IP_PRI_MAPPING3_IP_0XC0_BLEN 2 -#define IP_PRI_MAPPING3_IP_0XC0_FLAG HSL_RW - - - /* Tag Priority Mapping Register */ -#define TAG_PRI_MAPPING "tpmap" -#define TAG_PRI_MAPPING_ID 19 -#define TAG_PRI_MAPPING_OFFSET 0x0070 -#define TAG_PRI_MAPPING_E_LENGTH 4 -#define TAG_PRI_MAPPING_E_OFFSET 0 -#define TAG_PRI_MAPPING_NR_E 1 - -#define TAG_0X07 "tpmap_tg07" -#define TAG_PRI_MAPPING_TAG_0X07_BOFFSET 14 -#define TAG_PRI_MAPPING_TAG_0X07_BLEN 2 -#define TAG_PRI_MAPPING_TAG_0X07_FLAG HSL_RW - -#define TAG_0X06 "tpmap_tg06" -#define TAG_PRI_MAPPING_TAG_0X06_BOFFSET 12 -#define TAG_PRI_MAPPING_TAG_0X06_BLEN 2 -#define TAG_PRI_MAPPING_TAG_0X06_FLAG HSL_RW - -#define TAG_0X05 "tpmap_tg05" -#define TAG_PRI_MAPPING_TAG_0X05_BOFFSET 10 -#define TAG_PRI_MAPPING_TAG_0X05_BLEN 2 -#define TAG_PRI_MAPPING_TAG_0X05_FLAG HSL_RW - -#define TAG_0X04 "tpmap_tg04" -#define TAG_PRI_MAPPING_TAG_0X04_BOFFSET 8 -#define TAG_PRI_MAPPING_TAG_0X04_BLEN 2 -#define TAG_PRI_MAPPING_TAG_0X04_FLAG HSL_RW - -#define TAG_0X03 "tpmap_tg03" -#define TAG_PRI_MAPPING_TAG_0X03_BOFFSET 6 -#define TAG_PRI_MAPPING_TAG_0X03_BLEN 2 -#define TAG_PRI_MAPPING_TAG_0X03_FLAG HSL_RW - -#define TAG_0X02 "tpmap_tg02" -#define TAG_PRI_MAPPING_TAG_0X02_BOFFSET 4 -#define TAG_PRI_MAPPING_TAG_0X02_BLEN 2 -#define TAG_PRI_MAPPING_TAG_0X02_FLAG HSL_RW - -#define TAG_0X01 "tpmap_tg01" -#define TAG_PRI_MAPPING_TAG_0X01_BOFFSET 2 -#define TAG_PRI_MAPPING_TAG_0X01_BLEN 2 -#define TAG_PRI_MAPPING_TAG_0X01_FLAG HSL_RW - -#define TAG_0X00 "tpmap_tg00" -#define TAG_PRI_MAPPING_TAG_0X00_BOFFSET 0 -#define TAG_PRI_MAPPING_TAG_0X00_BLEN 2 -#define TAG_PRI_MAPPING_TAG_0X00_FLAG HSL_RW - - - /* Service tag Register */ -#define SERVICE_TAG "servicetag" -#define SERVICE_TAG_ID 20 -#define SERVICE_TAG_OFFSET 0x0074 -#define SERVICE_TAG_E_LENGTH 4 -#define SERVICE_TAG_E_OFFSET 0 -#define SERVICE_TAG_NR_E 1 - -#define TAG_VALUE "servicetag_val" -#define SERVICE_TAG_TAG_VALUE_BOFFSET 0 -#define SERVICE_TAG_TAG_VALUE_BLEN 16 -#define SERVICE_TAG_TAG_VALUE_FLAG HSL_RW - - - /* Cpu Port Register */ -#define CPU_PORT "cpup" -#define CPU_PORT_ID 20 -#define CPU_PORT_OFFSET 0x0078 -#define CPU_PORT_E_LENGTH 4 -#define CPU_PORT_E_OFFSET 0 -#define CPU_PORT_NR_E 0 - -#define CPU_PORT_EN "cpup_cpupe" -#define CPU_PORT_CPU_PORT_EN_BOFFSET 8 -#define CPU_PORT_CPU_PORT_EN_BLEN 1 -#define CPU_PORT_CPU_PORT_EN_FLAG HSL_RW - -#define MIRROR_PORT_NUM "cpup_mirpn" -#define CPU_PORT_MIRROR_PORT_NUM_BOFFSET 4 -#define CPU_PORT_MIRROR_PORT_NUM_BLEN 4 -#define CPU_PORT_MIRROR_PORT_NUM_FLAG HSL_RW - - - /* MIB Function Register */ -#define MIB_FUNC "mibfunc" -#define MIB_FUNC_ID 21 -#define MIB_FUNC_OFFSET 0x0080 -#define MIB_FUNC_E_LENGTH 4 -#define MIB_FUNC_E_OFFSET 0 -#define MIB_FUNC_NR_E 1 - -#define MAC_CRC_EN "mibfunc_crcen" -#define MIB_FUNC_MAC_CRC_EN_BOFFSET 31 -#define MIB_FUNC_MAC_CRC_EN_BLEN 1 -#define MIB_FUNC_MAC_CRC_EN_FLAG HSL_RW - -#define MIB_EN "mib_en" -#define MIB_FUNC_MIB_EN_BOFFSET 30 -#define MIB_FUNC_MIB_EN_BLEN 1 -#define MIB_FUNC_MIB_EN_FLAG HSL_RW - -#define MIB_FUN "mibfunc_mibf" -#define MIB_FUNC_MIB_FUN_BOFFSET 24 -#define MIB_FUNC_MIB_FUN_BLEN 3 -#define MIB_FUNC_MIB_FUN_FLAG HSL_RW - -#define MIB_BUSY "mibfunc_mibb" -#define MIB_FUNC_MIB_BUSY_BOFFSET 17 -#define MIB_FUNC_MIB_BUSY_BLEN 1 -#define MIB_FUNC_MIB_BUSY_FLAG HSL_RW - -#define MIB_AT_HALF_EN "mibfunc_mibhe" -#define MIB_FUNC_MIB_AT_HALF_EN_BOFFSET 16 -#define MIB_FUNC_MIB_AT_HALF_EN_BLEN 1 -#define MIB_FUNC_MIB_AT_HALF_EN_FLAG HSL_RW - -#define MIB_TIMER "mibfunc_mibt" -#define MIB_FUNC_MIB_TIMER_BOFFSET 0 -#define MIB_FUNC_MIB_TIMER_BLEN 16 -#define MIB_FUNC_MIB_TIMER_FLAG HSL_RW - - - /* Mdio control Register */ -#define MDIO_CTRL "mctrl" -#define MDIO_CTRL_ID 24 -#define MDIO_CTRL_OFFSET 0x0098 -#define MDIO_CTRL_E_LENGTH 4 -#define MDIO_CTRL_E_OFFSET 0 -#define MDIO_CTRL_NR_E 1 - -#define MSTER_EN "mctrl_msteren" -#define MDIO_CTRL_MSTER_EN_BOFFSET 30 -#define MDIO_CTRL_MSTER_EN_BLEN 1 -#define MDIO_CTRL_MSTER_EN_FLAG HSL_RW - -#define MSTER_EN "mctrl_msteren" -#define MDIO_CTRL_MSTER_EN_BOFFSET 30 -#define MDIO_CTRL_MSTER_EN_BLEN 1 -#define MDIO_CTRL_MSTER_EN_FLAG HSL_RW - -#define CMD "mctrl_cmd" -#define MDIO_CTRL_CMD_BOFFSET 27 -#define MDIO_CTRL_CMD_BLEN 1 -#define MDIO_CTRL_CMD_FLAG HSL_RW - -#define SUP_PRE "mctrl_spre" -#define MDIO_CTRL_SUP_PRE_BOFFSET 26 -#define MDIO_CTRL_SUP_PRE_BLEN 1 -#define MDIO_CTRL_SUP_PRE_FLAG HSL_RW - -#define PHY_ADDR "mctrl_phyaddr" -#define MDIO_CTRL_PHY_ADDR_BOFFSET 21 -#define MDIO_CTRL_PHY_ADDR_BLEN 5 -#define MDIO_CTRL_PHY_ADDR_FLAG HSL_RW - -#define REG_ADDR "mctrl_regaddr" -#define MDIO_CTRL_REG_ADDR_BOFFSET 16 -#define MDIO_CTRL_REG_ADDR_BLEN 5 -#define MDIO_CTRL_REG_ADDR_FLAG HSL_RW - -#define DATA "mctrl_data" -#define MDIO_CTRL_DATA_BOFFSET 0 -#define MDIO_CTRL_DATA_BLEN 16 -#define MDIO_CTRL_DATA_FLAG HSL_RW - - - - - /* BIST control Register */ -#define BIST_CTRL "bctrl" -#define BIST_CTRL_ID 24 -#define BIST_CTRL_OFFSET 0x00a0 -#define BIST_CTRL_E_LENGTH 4 -#define BIST_CTRL_E_OFFSET 0 -#define BIST_CTRL_NR_E 1 - -#define BIST_BUSY "bctrl_bb" -#define BIST_CTRL_BIST_BUSY_BOFFSET 31 -#define BIST_CTRL_BIST_BUSY_BLEN 1 -#define BIST_CTRL_BIST_BUSY_FLAG HSL_RW - -#define ONE_ERR "bctrl_oe" -#define BIST_CTRL_ONE_ERR_BOFFSET 30 -#define BIST_CTRL_ONE_ERR_BLEN 1 -#define BIST_CTRL_ONE_ERR_FLAG HSL_RO - -#define ERR_MEM "bctrl_em" -#define BIST_CTRL_ERR_MEM_BOFFSET 24 -#define BIST_CTRL_ERR_MEM_BLEN 4 -#define BIST_CTRL_ERR_MEM_FLAG HSL_RO - -#define PTN_EN2 "bctrl_pe2" -#define BIST_CTRL_PTN_EN2_BOFFSET 22 -#define BIST_CTRL_PTN_EN2_BLEN 1 -#define BIST_CTRL_PTN_EN2_FLAG HSL_RW - -#define PTN_EN1 "bctrl_pe1" -#define BIST_CTRL_PTN_EN1_BOFFSET 21 -#define BIST_CTRL_PTN_EN1_BLEN 1 -#define BIST_CTRL_PTN_EN1_FLAG HSL_RW - -#define PTN_EN0 "bctrl_pe0" -#define BIST_CTRL_PTN_EN0_BOFFSET 20 -#define BIST_CTRL_PTN_EN0_BLEN 1 -#define BIST_CTRL_PTN_EN0_FLAG HSL_RW - -#define ERR_PTN "bctrl_ep" -#define BIST_CTRL_ERR_PTN_BOFFSET 16 -#define BIST_CTRL_ERR_PTN_BLEN 2 -#define BIST_CTRL_ERR_PTN_FLAG HSL_RO - -#define ERR_CNT "bctrl_ec" -#define BIST_CTRL_ERR_CNT_BOFFSET 13 -#define BIST_CTRL_ERR_CNT_BLEN 2 -#define BIST_CTRL_ERR_CNT_FLAG HSL_RO - -#define ERR_ADDR "bctrl_ea" -#define BIST_CTRL_ERR_ADDR_BOFFSET 0 -#define BIST_CTRL_ERR_ADDR_BLEN 12 -#define BIST_CTRL_ERR_ADDR_FLAG HSL_RO - - - - - /* BIST recover Register */ -#define BIST_RCV "brcv" -#define BIST_RCV_ID 24 -#define BIST_RCV_OFFSET 0x00a4 -#define BIST_RCV_E_LENGTH 4 -#define BIST_RCV_E_OFFSET 0 -#define BIST_RCV_NR_E 1 - -#define RCV_EN "brcv_en" -#define BIST_RCV_RCV_EN_BOFFSET 31 -#define BIST_RCV_RCV_EN_BLEN 1 -#define BIST_RCV_RCV_EN_FLAG HSL_RW - -#define RCV_ADDR "brcv_addr" -#define BIST_RCV_RCV_ADDR_BOFFSET 0 -#define BIST_RCV_RCV_ADDR_BLEN 12 -#define BIST_RCV_RCV_ADDR_FLAG HSL_RW - - - - - /* LED control Register */ -#define LED_CTRL "ledctrl" -#define LED_CTRL_ID 25 -#define LED_CTRL_OFFSET 0x00b0 -#define LED_CTRL_E_LENGTH 4 -#define LED_CTRL_E_OFFSET 0 -#define LED_CTRL_NR_E 1 - -#define PATTERN_EN "lctrl_pen" -#define LED_CTRL_PATTERN_EN_BOFFSET 14 -#define LED_CTRL_PATTERN_EN_BLEN 2 -#define LED_CTRL_PATTERN_EN_FLAG HSL_RW - -#define FULL_LIGHT_EN "lctrl_fen" -#define LED_CTRL_FULL_LIGHT_EN_BOFFSET 13 -#define LED_CTRL_FULL_LIGHT_EN_BLEN 1 -#define LED_CTRL_FULL_LIGHT_EN_FLAG HSL_RW - -#define HALF_LIGHT_EN "lctrl_hen" -#define LED_CTRL_HALF_LIGHT_EN_BOFFSET 12 -#define LED_CTRL_HALF_LIGHT_EN_BLEN 1 -#define LED_CTRL_HALF_LIGHT_EN_FLAG HSL_RW - -#define POWERON_LIGHT_EN "lctrl_poen" -#define LED_CTRL_POWERON_LIGHT_EN_BOFFSET 11 -#define LED_CTRL_POWERON_LIGHT_EN_BLEN 1 -#define LED_CTRL_POWERON_LIGHT_EN_FLAG HSL_RW - -#define GE_LIGHT_EN "lctrl_geen" -#define LED_CTRL_GE_LIGHT_EN_BOFFSET 10 -#define LED_CTRL_GE_LIGHT_EN_BLEN 1 -#define LED_CTRL_GE_LIGHT_EN_FLAG HSL_RW - -#define FE_LIGHT_EN "lctrl_feen" -#define LED_CTRL_FE_LIGHT_EN_BOFFSET 9 -#define LED_CTRL_FE_LIGHT_EN_BLEN 1 -#define LED_CTRL_FE_LIGHT_EN_FLAG HSL_RW - -#define ETH_LIGHT_EN "lctrl_ethen" -#define LED_CTRL_ETH_LIGHT_EN_BOFFSET 8 -#define LED_CTRL_ETH_LIGHT_EN_BLEN 1 -#define LED_CTRL_ETH_LIGHT_EN_FLAG HSL_RW - -#define COL_BLINK_EN "lctrl_cen" -#define LED_CTRL_COL_BLINK_EN_BOFFSET 7 -#define LED_CTRL_COL_BLINK_EN_BLEN 1 -#define LED_CTRL_COL_BLINK_EN_FLAG HSL_RW - -#define RX_BLINK_EN "lctrl_rxen" -#define LED_CTRL_RX_BLINK_EN_BOFFSET 5 -#define LED_CTRL_RX_BLINK_EN_BLEN 1 -#define LED_CTRL_RX_BLINK_EN_FLAG HSL_RW - -#define TX_BLINK_EN "lctrl_txen" -#define LED_CTRL_TX_BLINK_EN_BOFFSET 4 -#define LED_CTRL_TX_BLINK_EN_BLEN 1 -#define LED_CTRL_TX_BLINK_EN_FLAG HSL_RW - -#define LINKUP_OVER_EN "lctrl_loen" -#define LED_CTRL_LINKUP_OVER_EN_BOFFSET 2 -#define LED_CTRL_LINKUP_OVER_EN_BLEN 1 -#define LED_CTRL_LINKUP_OVER_EN_FLAG HSL_RW - -#define BLINK_FREQ "lctrl_bfreq" -#define LED_CTRL_BLINK_FREQ_BOFFSET 0 -#define LED_CTRL_BLINK_FREQ_BLEN 2 -#define LED_CTRL_BLINK_FREQ_FLAG HSL_RW - - /* LED control Register */ -#define LED_PATTERN "ledpatten" -#define LED_PATTERN_ID 25 -#define LED_PATTERN_OFFSET 0x00bc -#define LED_PATTERN_E_LENGTH 4 -#define LED_PATTERN_E_OFFSET 0 -#define LED_PATTERN_NR_E 1 - -#define P3L1_MODE "p3l1_mode" -#define LED_PATTERN_P3L1_MODE_BOFFSET 24 -#define LED_PATTERN_P3L1_MODE_BLEN 2 -#define LED_PATTERN_P3L1_MODE_FLAG HSL_RW - -#define P3L0_MODE "p3l0_mode" -#define LED_PATTERN_P3L0_MODE_BOFFSET 22 -#define LED_PATTERN_P3L0_MODE_BLEN 2 -#define LED_PATTERN_P3L0_MODE_FLAG HSL_RW - -#define P2L1_MODE "p2l1_mode" -#define LED_PATTERN_P2L1_MODE_BOFFSET 20 -#define LED_PATTERN_P2L1_MODE_BLEN 2 -#define LED_PATTERN_P2L1_MODE_FLAG HSL_RW - -#define P2L0_MODE "p2l0_mode" -#define LED_PATTERN_P2L0_MODE_BOFFSET 18 -#define LED_PATTERN_P2L0_MODE_BLEN 2 -#define LED_PATTERN_P2L0_MODE_FLAG HSL_RW - -#define P1L1_MODE "p1l1_mode" -#define LED_PATTERN_P1L1_MODE_BOFFSET 16 -#define LED_PATTERN_P1L1_MODE_BLEN 2 -#define LED_PATTERN_P1L1_MODE_FLAG HSL_RW - -#define P1L0_MODE "p1l0_mode" -#define LED_PATTERN_P1L0_MODE_BOFFSET 14 -#define LED_PATTERN_P1L0_MODE_BLEN 2 -#define LED_PATTERN_P1L0_MODE_FLAG HSL_RW - -#define M5_MODE "m5_mode" -#define LED_PATTERN_M5_MODE_BOFFSET 10 -#define LED_PATTERN_M5_MODE_BLEN 2 -#define LED_PATTERN_M5_MODE_FLAG HSL_RW - - - /* Port Status Register */ -#define PORT_STATUS "ptsts" -#define PORT_STATUS_ID 29 -#define PORT_STATUS_OFFSET 0x0100 -#define PORT_STATUS_E_LENGTH 4 -#define PORT_STATUS_E_OFFSET 0x0100 -#define PORT_STATUS_NR_E 6 - -#define FLOW_LINK_EN "ptsts_flen" -#define PORT_STATUS_FLOW_LINK_EN_BOFFSET 12 -#define PORT_STATUS_FLOW_LINK_EN_BLEN 1 -#define PORT_STATUS_FLOW_LINK_EN_FLAG HSL_RW - - -#define LINK_ASYN_PAUSE "ptsts_lasynp" -#define PORT_STATUS_LINK_ASYN_PAUSE_BOFFSET 11 -#define PORT_STATUS_LINK_ASYN_PAUSE_BLEN 1 -#define PORT_STATUS_LINK_ASYN_PAUSE_FLAG HSL_RO - -#define LINK_PAUSE "ptsts_lpause" -#define PORT_STATUS_LINK_PAUSE_BOFFSET 10 -#define PORT_STATUS_LINK_PAUSE_BLEN 1 -#define PORT_STATUS_LINK_PAUSE_FLAG HSL_RO - -#define LINK_EN "ptsts_linken" -#define PORT_STATUS_LINK_EN_BOFFSET 9 -#define PORT_STATUS_LINK_EN_BLEN 1 -#define PORT_STATUS_LINK_EN_FLAG HSL_RW - -#define LINK "ptsts_ptlink" -#define PORT_STATUS_LINK_BOFFSET 8 -#define PORT_STATUS_LINK_BLEN 1 -#define PORT_STATUS_LINK_FLAG HSL_RO - -#define TX_HALF_FLOW_EN -#define PORT_STATUS_TX_HALF_FLOW_EN_BOFFSET 7 -#define PORT_STATUS_TX_HALF_FLOW_EN_BLEN 1 -#define PORT_STATUS_TX_HALF_FLOW_EN_FLAG HSL_RW - -#define DUPLEX_MODE "ptsts_dupmod" -#define PORT_STATUS_DUPLEX_MODE_BOFFSET 6 -#define PORT_STATUS_DUPLEX_MODE_BLEN 1 -#define PORT_STATUS_DUPLEX_MODE_FLAG HSL_RW - -#define RX_FLOW_EN "ptsts_rxfwen" -#define PORT_STATUS_RX_FLOW_EN_BOFFSET 5 -#define PORT_STATUS_RX_FLOW_EN_BLEN 1 -#define PORT_STATUS_RX_FLOW_EN_FLAG HSL_RW - -#define TX_FLOW_EN "ptsts_txfwen" -#define PORT_STATUS_TX_FLOW_EN_BOFFSET 4 -#define PORT_STATUS_TX_FLOW_EN_BLEN 1 -#define PORT_STATUS_TX_FLOW_EN_FLAG HSL_RW - -#define RXMAC_EN "ptsts_rxmacen" -#define PORT_STATUS_RXMAC_EN_BOFFSET 3 -#define PORT_STATUS_RXMAC_EN_BLEN 1 -#define PORT_STATUS_RXMAC_EN_FLAG HSL_RW - -#define TXMAC_EN "ptsts_txmacen" -#define PORT_STATUS_TXMAC_EN_BOFFSET 2 -#define PORT_STATUS_TXMAC_EN_BLEN 1 -#define PORT_STATUS_TXMAC_EN_FLAG HSL_RW - -#define SPEED_MODE "ptsts_speed" -#define PORT_STATUS_SPEED_MODE_BOFFSET 0 -#define PORT_STATUS_SPEED_MODE_BLEN 2 -#define PORT_STATUS_SPEED_MODE_FLAG HSL_RW - - - /* Port Control Register */ -#define PORT_CTL "pctl" -#define PORT_CTL_ID 30 -#define PORT_CTL_OFFSET 0x0104 -#define PORT_CTL_E_LENGTH 4 -#define PORT_CTL_E_OFFSET 0x0100 -#define PORT_CTL_NR_E 6 - -#define EAPOL_EN "pctl_eapolen" -#define PORT_CTL_EAPOL_EN_BOFFSET 23 -#define PORT_CTL_EAPOL_EN_BLEN 1 -#define PORT_CTL_EAPOL_EN_FLAG HSL_RW - -#define ARP_LEAKY_EN "pbvlan_alen" -#define PORT_CTL_ARP_LEAKY_EN_BOFFSET 22 -#define PORT_CTL_ARP_LEAKY_EN_BLEN 1 -#define PORT_CTL_ARP_LEAKY_EN_FLAG HSL_RW - -#define LEAVE_EN "pctl_leaveen" -#define PORT_CTL_LEAVE_EN_BOFFSET 21 -#define PORT_CTL_LEAVE_EN_BLEN 1 -#define PORT_CTL_LEAVE_EN_FLAG HSL_RW - -#define JOIN_EN "pctl_joinen" -#define PORT_CTL_JOIN_EN_BOFFSET 20 -#define PORT_CTL_JOIN_EN_BLEN 1 -#define PORT_CTL_JOIN_EN_FLAG HSL_RW - -#define DHCP_EN "pctl_dhcpen" -#define PORT_CTL_DHCP_EN_BOFFSET 19 -#define PORT_CTL_DHCP_EN_BLEN 1 -#define PORT_CTL_DHCP_EN_FLAG HSL_RW - -#define ING_MIRROR_EN "pctl_ingmiren" -#define PORT_CTL_ING_MIRROR_EN_BOFFSET 17 -#define PORT_CTL_ING_MIRROR_EN_BLEN 1 -#define PORT_CTL_ING_MIRROR_EN_FLAG HSL_RW - -#define EG_MIRROR_EN "pctl_egmiren" -#define PORT_CTL_EG_MIRROR_EN_BOFFSET 16 -#define PORT_CTL_EG_MIRROR_EN_BLEN 1 -#define PORT_CTL_EG_MIRROR_EN_FLAG HSL_RW - -#define LEARN_EN "pctl_learnen" -#define PORT_CTL_LEARN_EN_BOFFSET 14 -#define PORT_CTL_LEARN_EN_BLEN 1 -#define PORT_CTL_LEARN_EN_FLAG HSL_RW - -#define MAC_LOOP_BACK "pctl_maclp" -#define PORT_CTL_MAC_LOOP_BACK_BOFFSET 12 -#define PORT_CTL_MAC_LOOP_BACK_BLEN 1 -#define PORT_CTL_MAC_LOOP_BACK_FLAG HSL_RW - -#define HEAD_EN "pctl_headen" -#define PORT_CTL_HEAD_EN_BOFFSET 11 -#define PORT_CTL_HEAD_EN_BLEN 1 -#define PORT_CTL_HEAD_EN_FLAG HSL_RW - -#define IGMP_MLD_EN "pctl_imlden" -#define PORT_CTL_IGMP_MLD_EN_BOFFSET 10 -#define PORT_CTL_IGMP_MLD_EN_BLEN 1 -#define PORT_CTL_IGMP_MLD_EN_FLAG HSL_RW - -#define EG_VLAN_MODE "pctl_egvmode" -#define PORT_CTL_EG_VLAN_MODE_BOFFSET 8 -#define PORT_CTL_EG_VLAN_MODE_BLEN 2 -#define PORT_CTL_EG_VLAN_MODE_FLAG HSL_RW - -#define LEARN_ONE_LOCK "pctl_lonelck" -#define PORT_CTL_LEARN_ONE_LOCK_BOFFSET 7 -#define PORT_CTL_LEARN_ONE_LOCK_BLEN 1 -#define PORT_CTL_LEARN_ONE_LOCK_FLAG HSL_RW - -#define PORT_LOCK_EN "pctl_locken" -#define PORT_CTL_PORT_LOCK_EN_BOFFSET 6 -#define PORT_CTL_PORT_LOCK_EN_BLEN 1 -#define PORT_CTL_PORT_LOCK_EN_FLAG HSL_RW - -#define LOCK_DROP_EN "pctl_dropen" -#define PORT_CTL_LOCK_DROP_EN_BOFFSET 5 -#define PORT_CTL_LOCK_DROP_EN_BLEN 1 -#define PORT_CTL_LOCK_DROP_EN_FLAG HSL_RW - -#define PORT_STATE "pctl_pstate" -#define PORT_CTL_PORT_STATE_BOFFSET 0 -#define PORT_CTL_PORT_STATE_BLEN 3 -#define PORT_CTL_PORT_STATE_FLAG HSL_RW - - - /* Port dot1q Register */ -#define PORT_DOT1Q "pdot1Q" -#define PORT_DOT1Q_ID 31 -#define PORT_DOT1Q_OFFSET 0x0108 -#define PORT_DOT1Q_E_LENGTH 4 -#define PORT_DOT1Q_E_OFFSET 0x0100 -#define PORT_DOT1Q_NR_E 6 - -#define ING_PRI "pdot1q_ingpri" -#define PORT_DOT1Q_ING_PRI_BOFFSET 29 -#define PORT_DOT1Q_ING_PRI_BLEN 3 -#define PORT_DOT1Q_ING_PRI_FLAG HSL_RW - -#define FORCE_PVLAN "pdot1q_fpvlan" -#define PORT_DOT1Q_FORCE_PVLAN_BOFFSET 28 -#define PORT_DOT1Q_FORCE_PVLAN_BLEN 1 -#define PORT_DOT1Q_FORCE_PVLAN_FLAG HSL_RW - -#define DEF_VID "pdot1q_dcvid" -#define PORT_DOT1Q_DEF_VID_BOFFSET 16 -#define PORT_DOT1Q_DEF_VID_BLEN 12 -#define PORT_DOT1Q_DEF_VID_FLAG HSL_RW - -#define FORCE_DEF_VID "pbot1q_fdvid" -#define PORT_DOT1Q_FORCE_DEF_VID_BOFFSET 12 -#define PORT_DOT1Q_FORCE_DEF_VID_BLEN 1 -#define PORT_DOT1Q_FORCE_DEF_VID_FLAG HSL_RW - - - /* Port Based Vlan Register */ -#define PORT_BASE_VLAN "pbvlan" -#define PORT_BASE_VLAN_ID 31 -#define PORT_BASE_VLAN_OFFSET 0x010c -#define PORT_BASE_VLAN_E_LENGTH 4 -#define PORT_BASE_VLAN_E_OFFSET 0x0100 -#define PORT_BASE_VLAN_NR_E 6 - -#define DOT1Q_MODE "pbvlan_8021q" -#define PORT_BASE_VLAN_DOT1Q_MODE_BOFFSET 30 -#define PORT_BASE_VLAN_DOT1Q_MODE_BLEN 2 -#define PORT_BASE_VLAN_DOT1Q_MODE_FLAG HSL_RW - -#define COREP_EN "pbvlan_corepen" -#define PORT_BASE_VLAN_COREP_EN_BOFFSET 29 -#define PORT_BASE_VLAN_COREP_EN_BLEN 1 -#define PORT_BASE_VLAN_COREP_EN_FLAG HSL_RW - -#define IN_VLAN_MODE "pbvlan_imode" -#define PORT_BASE_VLAN_IN_VLAN_MODE_BOFFSET 27 -#define PORT_BASE_VLAN_IN_VLAN_MODE_BLEN 2 -#define PORT_BASE_VLAN_IN_VLAN_MODE_FLAG HSL_RW - -#define PRI_PROPAGATION "pbvlan_prip" -#define PORT_BASE_VLAN_PRI_PROPAGATION_BOFFSET 23 -#define PORT_BASE_VLAN_PRI_PROPAGATION_BLEN 1 -#define PORT_BASE_VLAN_PRI_PROPAGATION_FLAG HSL_RW - -#define PORT_VID_MEM "pbvlan_pvidm" -#define PORT_BASE_VLAN_PORT_VID_MEM_BOFFSET 16 -#define PORT_BASE_VLAN_PORT_VID_MEM_BLEN 6 -#define PORT_BASE_VLAN_PORT_VID_MEM_FLAG HSL_RW - -#define UNI_LEAKY_EN "pbvlan_ulen" -#define PORT_BASE_VLAN_UNI_LEAKY_EN_BOFFSET 14 -#define PORT_BASE_VLAN_UNI_LEAKY_EN_BLEN 1 -#define PORT_BASE_VLAN_UNI_LEAKY_EN_FLAG HSL_RW - -#define MUL_LEAKY_EN "pbvlan_mlen" -#define PORT_BASE_VLAN_MUL_LEAKY_EN_BOFFSET 13 -#define PORT_BASE_VLAN_MUL_LEAKY_EN_BLEN 1 -#define PORT_BASE_VLAN_MUL_LEAKY_EN_FLAG HSL_RW - - - /* Port Rate Limit0 Register */ -#define RATE_LIMIT0 "rlmt0" -#define RATE_LIMIT0_ID 32 -#define RATE_LIMIT0_OFFSET 0x0110 -#define RATE_LIMIT0_E_LENGTH 4 -#define RATE_LIMIT0_E_OFFSET 0x0100 -#define RATE_LIMIT0_NR_E 6 - -#define ADD_RATE_BYTE "rlmt_addbyte" -#define RATE_LIMIT0_ADD_RATE_BYTE_BOFFSET 24 -#define RATE_LIMIT0_ADD_RATE_BYTE_BLEN 8 -#define RATE_LIMIT0_ADD_RATE_BYTE_FLAG HSL_RW - -#define EG_MNG_RATE_EN "rlmt_egmngen" -#define RATE_LIMIT0_EG_MNG_RATE_EN_BOFFSET 22 -#define RATE_LIMIT0_EG_MNG_RATE_EN_BLEN 1 -#define RATE_LIMIT0_EG_MNG_RATE_EN_FLAG HSL_RW - -#define IN_MNG_RATE_EN "rlmt_inmngen" -#define RATE_LIMIT0_IN_MNG_RATE_EN_BOFFSET 21 -#define RATE_LIMIT0_IN_MNG_RATE_EN_BLEN 1 -#define RATE_LIMIT0_IN_MNG_RATE_EN_FLAG HSL_RW - -#define IN_MUL_RATE_EN "rlmt_inmulen" -#define RATE_LIMIT0_IN_MUL_RATE_EN_BOFFSET 20 -#define RATE_LIMIT0_IN_MUL_RATE_EN_BLEN 1 -#define RATE_LIMIT0_IN_MUL_RATE_EN_FLAG HSL_RW - -#define ING_RATE "rlmt_ingrate" -#define RATE_LIMIT0_ING_RATE_BOFFSET 0 -#define RATE_LIMIT0_ING_RATE_BLEN 13 -#define RATE_LIMIT0_ING_RATE_FLAG HSL_RW - - - /* Priority Control Register */ -#define PRI_CTL "prctl" -#define PRI_CTL_ID 33 -#define PRI_CTL_OFFSET 0x0114 -#define PRI_CTL_E_LENGTH 4 -#define PRI_CTL_E_OFFSET 0x0100 -#define PRI_CTL_NR_E 6 - -#define PORT_PRI_EN "prctl_ptprien" -#define PRI_CTL_PORT_PRI_EN_BOFFSET 19 -#define PRI_CTL_PORT_PRI_EN_BLEN 1 -#define PRI_CTL_PORT_PRI_EN_FLAG HSL_RW - -#define DA_PRI_EN "prctl_daprien" -#define PRI_CTL_DA_PRI_EN_BOFFSET 18 -#define PRI_CTL_DA_PRI_EN_BLEN 1 -#define PRI_CTL_DA_PRI_EN_FLAG HSL_RW - -#define VLAN_PRI_EN "prctl_vprien" -#define PRI_CTL_VLAN_PRI_EN_BOFFSET 17 -#define PRI_CTL_VLAN_PRI_EN_BLEN 1 -#define PRI_CTL_VLAN_PRI_EN_FLAG HSL_RW - -#define IP_PRI_EN "prctl_ipprien" -#define PRI_CTL_IP_PRI_EN_BOFFSET 16 -#define PRI_CTL_IP_PRI_EN_BLEN 1 -#define PRI_CTL_IP_PRI_EN_FLAG HSL_RW - -#define DA_PRI_SEL "prctl_dapris" -#define PRI_CTL_DA_PRI_SEL_BOFFSET 6 -#define PRI_CTL_DA_PRI_SEL_BLEN 2 -#define PRI_CTL_DA_PRI_SEL_FLAG HSL_RW - -#define VLAN_PRI_SEL "prctl_vpris" -#define PRI_CTL_VLAN_PRI_SEL_BOFFSET 4 -#define PRI_CTL_VLAN_PRI_SEL_BLEN 2 -#define PRI_CTL_VLAN_PRI_SEL_FLAG HSL_RW - -#define IP_PRI_SEL "prctl_ippris" -#define PRI_CTL_IP_PRI_SEL_BOFFSET 2 -#define PRI_CTL_IP_PRI_SEL_BLEN 2 -#define PRI_CTL_IP_PRI_SEL_FLAG HSL_RW - -#define PORT_PRI_SEL "prctl_ptpris" -#define PRI_CTL_PORT_PRI_SEL_BOFFSET 0 -#define PRI_CTL_PORT_PRI_SEL_BLEN 2 -#define PRI_CTL_PORT_PRI_SEL_FLAG HSL_RW - - - /* Storm Control Register */ -#define STORM_CTL "sctrl" -#define STORM_CTL_ID 33 -#define STORM_CTL_OFFSET 0x0118 -#define STORM_CTL_E_LENGTH 4 -#define STORM_CTL_E_OFFSET 0x0100 -#define STORM_CTL_NR_E 6 - -#define UNIT "sctrl_unit" -#define STORM_CTL_UNIT_BOFFSET 24 -#define STORM_CTL_UNIT_BLEN 2 -#define STORM_CTL_UNIT_FLAG HSL_RW - -#define MUL_EN "sctrl_mulen" -#define STORM_CTL_MUL_EN_BOFFSET 10 -#define STORM_CTL_MUL_EN_BLEN 1 -#define STORM_CTL_MUL_EN_FLAG HSL_RW - -#define UNI_EN "sctrl_unien" -#define STORM_CTL_UNI_EN_BOFFSET 9 -#define STORM_CTL_UNI_EN_BLEN 1 -#define STORM_CTL_UNI_EN_FLAG HSL_RW - -#define BRO_EN "sctrl_broen" -#define STORM_CTL_BRO_EN_BOFFSET 8 -#define STORM_CTL_BRO_EN_BLEN 1 -#define STORM_CTL_BRO_EN_FLAG HSL_RW - -#define RATE "sctrl_rate" -#define STORM_CTL_RATE_BOFFSET 0 -#define STORM_CTL_RATE_BLEN 4 -#define STORM_CTL_RATE_FLAG HSL_RW - - - /* Queue Control Register */ -#define QUEUE_CTL "qctl" -#define QUEUE_CTL_ID 34 -#define QUEUE_CTL_OFFSET 0x011c -#define QUEUE_CTL_E_LENGTH 4 -#define QUEUE_CTL_E_OFFSET 0x0100 -#define QUEUE_CTL_NR_E 6 - -#define PORT_IN_DESC_EN "qctl_pdescen" -#define QUEUE_CTL_PORT_IN_DESC_EN_BOFFSET 28 -#define QUEUE_CTL_PORT_IN_DESC_EN_BLEN 4 -#define QUEUE_CTL_PORT_IN_DESC_EN_FLAG HSL_RW - -#define PORT_DESC_EN "qctl_pdescen" -#define QUEUE_CTL_PORT_DESC_EN_BOFFSET 25 -#define QUEUE_CTL_PORT_DESC_EN_BLEN 1 -#define QUEUE_CTL_PORT_DESC_EN_FLAG HSL_RW - -#define QUEUE_DESC_EN "qctl_qdescen" -#define QUEUE_CTL_QUEUE_DESC_EN_BOFFSET 24 -#define QUEUE_CTL_QUEUE_DESC_EN_BLEN 1 -#define QUEUE_CTL_QUEUE_DESC_EN_FLAG HSL_RW - -#define PORT_DESC_NR "qctl_pdscpnr" -#define QUEUE_CTL_PORT_DESC_NR_BOFFSET 16 -#define QUEUE_CTL_PORT_DESC_NR_BLEN 6 -#define QUEUE_CTL_PORT_DESC_NR_FLAG HSL_RW - -#define QUEUE3_DESC_NR "qctl_q3dscpnr" -#define QUEUE_CTL_QUEUE3_DESC_NR_BOFFSET 12 -#define QUEUE_CTL_QUEUE3_DESC_NR_BLEN 4 -#define QUEUE_CTL_QUEUE3_DESC_NR_FLAG HSL_RW - -#define QUEUE2_DESC_NR "qctl_q2dscpnr" -#define QUEUE_CTL_QUEUE2_DESC_NR_BOFFSET 8 -#define QUEUE_CTL_QUEUE2_DESC_NR_BLEN 4 -#define QUEUE_CTL_QUEUE2_DESC_NR_FLAG HSL_RW - -#define QUEUE1_DESC_NR "qctl_q1dscpnr" -#define QUEUE_CTL_QUEUE1_DESC_NR_BOFFSET 4 -#define QUEUE_CTL_QUEUE1_DESC_NR_BLEN 4 -#define QUEUE_CTL_QUEUE1_DESC_NR_FLAG HSL_RW - -#define QUEUE0_DESC_NR "qctl_q0dscpnr" -#define QUEUE_CTL_QUEUE0_DESC_NR_BOFFSET 0 -#define QUEUE_CTL_QUEUE0_DESC_NR_BLEN 4 -#define QUEUE_CTL_QUEUE0_DESC_NR_FLAG HSL_RW - - - /* Port Rate Limit1 Register */ -#define RATE_LIMIT1 "rlmt1" -#define RATE_LIMIT1_ID 32 -#define RATE_LIMIT1_OFFSET 0x0120 -#define RATE_LIMIT1_E_LENGTH 4 -#define RATE_LIMIT1_E_OFFSET 0x0100 -#define RATE_LIMIT1_NR_E 6 - -#define EG_RATE "rlmt_egrate" -#define RATE_LIMIT1_EG_RATE_BOFFSET 0 -#define RATE_LIMIT1_EG_RATE_BLEN 13 -#define RATE_LIMIT1_EG_RATE_FLAG HSL_RW - - - /* Port Rate Limit3 Register */ -#define RATE_LIMIT3 "rlmt3" -#define RATE_LIMIT3_ID 32 -#define RATE_LIMIT3_OFFSET 0x0128 -#define RATE_LIMIT3_E_LENGTH 4 -#define RATE_LIMIT3_E_OFFSET 0x0100 -#define RATE_LIMIT3_NR_E 6 - -#define EG_CBS "rlmt_egcbs" -#define RATE_LIMIT3_EG_CBS_BOFFSET 16 -#define RATE_LIMIT3_EG_CBS_BLEN 2 -#define RATE_LIMIT3_EG_CBS_FLAG HSL_RW - -#define EG_TS "rlmt_egts" -#define RATE_LIMIT3_EG_TS_BOFFSET 0 -#define RATE_LIMIT3_EG_TS_BLEN 3 -#define RATE_LIMIT3_EG_TS_FLAG HSL_RW - - - /* Weight Round Robin Register */ -#define WRR_CTRL "wrrc" -#define WRR_CTRL_ID 32 -#define WRR_CTRL_OFFSET 0x012c -#define WRR_CTRL_E_LENGTH 4 -#define WRR_CTRL_E_OFFSET 0x0100 -#define WRR_CTRL_NR_E 6 - -#define SCH_MODE "wrrc_mode" -#define WRR_CTRL_SCH_MODE_BOFFSET 29 -#define WRR_CTRL_SCH_MODE_BLEN 2 -#define WRR_CTRL_SCH_MODE_FLAG HSL_RW - - - /* mib memory info */ -#define MIB_RXBROAD "RxBroad" -#define MIB_RXBROAD_ID 34 -#define MIB_RXBROAD_OFFSET 0x20000 -#define MIB_RXBROAD_E_LENGTH 4 -#define MIB_RXBROAD_E_OFFSET 0x100 -#define MIB_RXBROAD_NR_E 6 - -#define MIB_RXPAUSE "RxPause" -#define MIB_RXPAUSE_ID 35 -#define MIB_RXPAUSE_OFFSET 0x20004 -#define MIB_RXPAUSE_E_LENGTH 4 -#define MIB_RXPAUSE_E_OFFSET 0x100 -#define MIB_RXPAUSE_NR_E 6 - -#define MIB_RXMULTI "RxMulti" -#define MIB_RXMULTI_ID 36 -#define MIB_RXMULTI_OFFSET 0x20008 -#define MIB_RXMULTI_E_LENGTH 4 -#define MIB_RXMULTI_E_OFFSET 0x100 -#define MIB_RXMULTI_NR_E 6 - -#define MIB_RXFCSERR "RxFcsErr" -#define MIB_RXFCSERR_ID 37 -#define MIB_RXFCSERR_OFFSET 0x2000c -#define MIB_RXFCSERR_E_LENGTH 4 -#define MIB_RXFCSERR_E_OFFSET 0x100 -#define MIB_RXFCSERR_NR_E 6 - -#define MIB_RXALLIGNERR "RxAllignErr" -#define MIB_RXALLIGNERR_ID 38 -#define MIB_RXALLIGNERR_OFFSET 0x20010 -#define MIB_RXALLIGNERR_E_LENGTH 4 -#define MIB_RXALLIGNERR_E_OFFSET 0x100 -#define MIB_RXALLIGNERR_NR_E 6 - -#define MIB_RXRUNT "RxRunt" -#define MIB_RXRUNT_ID 39 -#define MIB_RXRUNT_OFFSET 0x20014 -#define MIB_RXRUNT_E_LENGTH 4 -#define MIB_RXRUNT_E_OFFSET 0x100 -#define MIB_RXRUNT_NR_E 6 - -#define MIB_RXFRAGMENT "RxFragment" -#define MIB_RXFRAGMENT_ID 40 -#define MIB_RXFRAGMENT_OFFSET 0x20018 -#define MIB_RXFRAGMENT_E_LENGTH 4 -#define MIB_RXFRAGMENT_E_OFFSET 0x100 -#define MIB_RXFRAGMENT_NR_E 6 - -#define MIB_RX64BYTE "Rx64Byte" -#define MIB_RX64BYTE_ID 41 -#define MIB_RX64BYTE_OFFSET 0x2001c -#define MIB_RX64BYTE_E_LENGTH 4 -#define MIB_RX64BYTE_E_OFFSET 0x100 -#define MIB_RX64BYTE_NR_E 6 - -#define MIB_RX128BYTE "Rx128Byte" -#define MIB_RX128BYTE_ID 42 -#define MIB_RX128BYTE_OFFSET 0x20020 -#define MIB_RX128BYTE_E_LENGTH 4 -#define MIB_RX128BYTE_E_OFFSET 0x100 -#define MIB_RX128BYTE_NR_E 6 - -#define MIB_RX256BYTE "Rx256Byte" -#define MIB_RX256BYTE_ID 43 -#define MIB_RX256BYTE_OFFSET 0x20024 -#define MIB_RX256BYTE_E_LENGTH 4 -#define MIB_RX256BYTE_E_OFFSET 0x100 -#define MIB_RX256BYTE_NR_E 6 - -#define MIB_RX512BYTE "Rx512Byte" -#define MIB_RX512BYTE_ID 44 -#define MIB_RX512BYTE_OFFSET 0x20028 -#define MIB_RX512BYTE_E_LENGTH 4 -#define MIB_RX512BYTE_E_OFFSET 0x100 -#define MIB_RX512BYTE_NR_E 6 - -#define MIB_RX1024BYTE "Rx1024Byte" -#define MIB_RX1024BYTE_ID 45 -#define MIB_RX1024BYTE_OFFSET 0x2002c -#define MIB_RX1024BYTE_E_LENGTH 4 -#define MIB_RX1024BYTE_E_OFFSET 0x100 -#define MIB_RX1024BYTE_NR_E 6 - -#define MIB_RX1518BYTE "Rx1518Byte" -#define MIB_RX1518BYTE_ID 45 -#define MIB_RX1518BYTE_OFFSET 0x20030 -#define MIB_RX1518BYTE_E_LENGTH 4 -#define MIB_RX1518BYTE_E_OFFSET 0x100 -#define MIB_RX1518BYTE_NR_E 6 - -#define MIB_RXMAXBYTE "RxMaxByte" -#define MIB_RXMAXBYTE_ID 46 -#define MIB_RXMAXBYTE_OFFSET 0x20034 -#define MIB_RXMAXBYTE_E_LENGTH 4 -#define MIB_RXMAXBYTE_E_OFFSET 0x100 -#define MIB_RXMAXBYTE_NR_E 6 - -#define MIB_RXTOOLONG "RxTooLong" -#define MIB_RXTOOLONG_ID 47 -#define MIB_RXTOOLONG_OFFSET 0x20038 -#define MIB_RXTOOLONG_E_LENGTH 4 -#define MIB_RXTOOLONG_E_OFFSET 0x100 -#define MIB_RXTOOLONG_NR_E 6 - -#define MIB_RXGOODBYTE_LO "RxGoodByteLo" -#define MIB_RXGOODBYTE_LO_ID 48 -#define MIB_RXGOODBYTE_LO_OFFSET 0x2003c -#define MIB_RXGOODBYTE_LO_E_LENGTH 4 -#define MIB_RXGOODBYTE_LO_E_OFFSET 0x100 -#define MIB_RXGOODBYTE_LO_NR_E 6 - -#define MIB_RXGOODBYTE_HI "RxGoodByteHi" -#define MIB_RXGOODBYTE_HI_ID 49 -#define MIB_RXGOODBYTE_HI_OFFSET 0x20040 -#define MIB_RXGOODBYTE_HI_E_LENGTH 4 -#define MIB_RXGOODBYTE_HI_E_OFFSET 0x100 -#define MIB_RXGOODBYTE_HI_NR_E 6 - -#define MIB_RXBADBYTE_LO "RxBadByteLo" -#define MIB_RXBADBYTE_LO_ID 50 -#define MIB_RXBADBYTE_LO_OFFSET 0x20044 -#define MIB_RXBADBYTE_LO_E_LENGTH 4 -#define MIB_RXBADBYTE_LO_E_OFFSET 0x100 -#define MIB_RXBADBYTE_LO_NR_E 6 - -#define MIB_RXBADBYTE_HI "RxBadByteHi" -#define MIB_RXBADBYTE_HI_ID 51 -#define MIB_RXBADBYTE_HI_OFFSET 0x20048 -#define MIB_RXBADBYTE_HI_E_LENGTH 4 -#define MIB_RXBADBYTE_HI_E_OFFSET 0x100 -#define MIB_RXBADBYTE_HI_NR_E 6 - -#define MIB_RXOVERFLOW "RxOverFlow" -#define MIB_RXOVERFLOW_ID 52 -#define MIB_RXOVERFLOW_OFFSET 0x2004c -#define MIB_RXOVERFLOW_E_LENGTH 4 -#define MIB_RXOVERFLOW_E_OFFSET 0x100 -#define MIB_RXOVERFLOW_NR_E 6 - -#define MIB_FILTERED "Filtered" -#define MIB_FILTERED_ID 53 -#define MIB_FILTERED_OFFSET 0x20050 -#define MIB_FILTERED_E_LENGTH 4 -#define MIB_FILTERED_E_OFFSET 0x100 -#define MIB_FILTERED_NR_E 6 - -#define MIB_TXBROAD "TxBroad" -#define MIB_TXBROAD_ID 54 -#define MIB_TXBROAD_OFFSET 0x20054 -#define MIB_TXBROAD_E_LENGTH 4 -#define MIB_TXBROAD_E_OFFSET 0x100 -#define MIB_TXBROAD_NR_E 6 - -#define MIB_TXPAUSE "TxPause" -#define MIB_TXPAUSE_ID 55 -#define MIB_TXPAUSE_OFFSET 0x20058 -#define MIB_TXPAUSE_E_LENGTH 4 -#define MIB_TXPAUSE_E_OFFSET 0x100 -#define MIB_TXPAUSE_NR_E 6 - -#define MIB_TXMULTI "TxMulti" -#define MIB_TXMULTI_ID 56 -#define MIB_TXMULTI_OFFSET 0x2005c -#define MIB_TXMULTI_E_LENGTH 4 -#define MIB_TXMULTI_E_OFFSET 0x100 -#define MIB_TXMULTI_NR_E 6 - -#define MIB_TXUNDERRUN "TxUnderRun" -#define MIB_TXUNDERRUN_ID 57 -#define MIB_TXUNDERRUN_OFFSET 0x20060 -#define MIB_TXUNDERRUN_E_LENGTH 4 -#define MIB_TXUNDERRUN_E_OFFSET 0x100 -#define MIB_TXUNDERRUN_NR_E 6 - -#define MIB_TX64BYTE "Tx64Byte" -#define MIB_TX64BYTE_ID 58 -#define MIB_TX64BYTE_OFFSET 0x20064 -#define MIB_TX64BYTE_E_LENGTH 4 -#define MIB_TX64BYTE_E_OFFSET 0x100 -#define MIB_TX64BYTE_NR_E 6 - -#define MIB_TX128BYTE "Tx128Byte" -#define MIB_TX128BYTE_ID 59 -#define MIB_TX128BYTE_OFFSET 0x20068 -#define MIB_TX128BYTE_E_LENGTH 4 -#define MIB_TX128BYTE_E_OFFSET 0x100 -#define MIB_TX128BYTE_NR_E 6 - -#define MIB_TX256BYTE "Tx256Byte" -#define MIB_TX256BYTE_ID 60 -#define MIB_TX256BYTE_OFFSET 0x2006c -#define MIB_TX256BYTE_E_LENGTH 4 -#define MIB_TX256BYTE_E_OFFSET 0x100 -#define MIB_TX256BYTE_NR_E 6 - -#define MIB_TX512BYTE "Tx512Byte" -#define MIB_TX512BYTE_ID 61 -#define MIB_TX512BYTE_OFFSET 0x20070 -#define MIB_TX512BYTE_E_LENGTH 4 -#define MIB_TX512BYTE_E_OFFSET 0x100 -#define MIB_TX512BYTE_NR_E 6 - -#define MIB_TX1024BYTE "Tx1024Byte" -#define MIB_TX1024BYTE_ID 62 -#define MIB_TX1024BYTE_OFFSET 0x20074 -#define MIB_TX1024BYTE_E_LENGTH 4 -#define MIB_TX1024BYTE_E_OFFSET 0x100 -#define MIB_TX1024BYTE_NR_E 6 - -#define MIB_TX1518BYTE "Tx1518Byte" -#define MIB_TX1518BYTE_ID 62 -#define MIB_TX1518BYTE_OFFSET 0x20078 -#define MIB_TX1518BYTE_E_LENGTH 4 -#define MIB_TX1518BYTE_E_OFFSET 0x100 -#define MIB_TX1518BYTE_NR_E 6 - -#define MIB_TXMAXBYTE "TxMaxByte" -#define MIB_TXMAXBYTE_ID 63 -#define MIB_TXMAXBYTE_OFFSET 0x2007c -#define MIB_TXMAXBYTE_E_LENGTH 4 -#define MIB_TXMAXBYTE_E_OFFSET 0x100 -#define MIB_TXMAXBYTE_NR_E 6 - -#define MIB_TXOVERSIZE "TxOverSize" -#define MIB_TXOVERSIZE_ID 64 -#define MIB_TXOVERSIZE_OFFSET 0x20080 -#define MIB_TXOVERSIZE_E_LENGTH 4 -#define MIB_TXOVERSIZE_E_OFFSET 0x100 -#define MIB_TXOVERSIZE_NR_E 6 - -#define MIB_TXBYTE_LO "TxByteLo" -#define MIB_TXBYTE_LO_ID 65 -#define MIB_TXBYTE_LO_OFFSET 0x20084 -#define MIB_TXBYTE_LO_E_LENGTH 4 -#define MIB_TXBYTE_LO_E_OFFSET 0x100 -#define MIB_TXBYTE_LO_NR_E 6 - -#define MIB_TXBYTE_HI "TxByteHi" -#define MIB_TXBYTE_HI_ID 66 -#define MIB_TXBYTE_HI_OFFSET 0x20088 -#define MIB_TXBYTE_HI_E_LENGTH 4 -#define MIB_TXBYTE_HI_E_OFFSET 0x100 -#define MIB_TXBYTE_HI_NR_E 6 - -#define MIB_TXCOLLISION "TxCollision" -#define MIB_TXCOLLISION_ID 67 -#define MIB_TXCOLLISION_OFFSET 0x2008c -#define MIB_TXCOLLISION_E_LENGTH 4 -#define MIB_TXCOLLISION_E_OFFSET 0x100 -#define MIB_TXCOLLISION_NR_E 6 - -#define MIB_TXABORTCOL "TxAbortCol" -#define MIB_TXABORTCOL_ID 68 -#define MIB_TXABORTCOL_OFFSET 0x20090 -#define MIB_TXABORTCOL_E_LENGTH 4 -#define MIB_TXABORTCOL_E_OFFSET 0x100 -#define MIB_TXABORTCOL_NR_E 6 - -#define MIB_TXMULTICOL "TxMultiCol" -#define MIB_TXMULTICOL_ID 69 -#define MIB_TXMULTICOL_OFFSET 0x20094 -#define MIB_TXMULTICOL_E_LENGTH 4 -#define MIB_TXMULTICOL_E_OFFSET 0x100 -#define MIB_TXMULTICOL_NR_E 6 - -#define MIB_TXSINGALCOL "TxSingalCol" -#define MIB_TXSINGALCOL_ID 70 -#define MIB_TXSINGALCOL_OFFSET 0x20098 -#define MIB_TXSINGALCOL_E_LENGTH 4 -#define MIB_TXSINGALCOL_E_OFFSET 0x100 -#define MIB_TXSINGALCOL_NR_E 6 - -#define MIB_TXEXCDEFER "TxExcDefer" -#define MIB_TXEXCDEFER_ID 71 -#define MIB_TXEXCDEFER_OFFSET 0x2009c -#define MIB_TXEXCDEFER_E_LENGTH 4 -#define MIB_TXEXCDEFER_E_OFFSET 0x100 -#define MIB_TXEXCDEFER_NR_E 6 - -#define MIB_TXDEFER "TxDefer" -#define MIB_TXDEFER_ID 72 -#define MIB_TXDEFER_OFFSET 0x200a0 -#define MIB_TXDEFER_E_LENGTH 4 -#define MIB_TXDEFER_E_OFFSET 0x100 -#define MIB_TXDEFER_NR_E 6 - -#define MIB_TXLATECOL "TxLateCol" -#define MIB_TXLATECOL_ID 73 -#define MIB_TXLATECOL_OFFSET 0x200a4 -#define MIB_TXLATECOL_E_LENGTH 4 -#define MIB_TXLATECOL_E_OFFSET 0x100 -#define MIB_TXLATECOL_NR_E 6 - - -#define PPPOE_SESSION "pppoes" -#define PPPOE_SESSION_ID 13 -#define PPPOE_SESSION_OFFSET 0x59100 -#define PPPOE_SESSION_E_LENGTH 4 -#define PPPOE_SESSION_E_OFFSET 0x4 -#define PPPOE_SESSION_NR_E 16 - -#define ENTRY_VALID "pppoes_v" -#define PPPOE_SESSION_ENTRY_VALID_BOFFSET 19 -#define PPPOE_SESSION_ENTRY_VALID_BLEN 1 -#define PPPOE_SESSION_ENTRY_VALID_FLAG HSL_RW - -#define STRIP_EN "pppoes_s" -#define PPPOE_SESSION_STRIP_EN_BOFFSET 16 -#define PPPOE_SESSION_STRIP_EN_BLEN 1 -#define PPPOE_SESSION_STRIP_EN_FLAG HSL_RW - -#define SEESION_ID "pppoes_id" -#define PPPOE_SESSION_SEESION_ID_BOFFSET 0 -#define PPPOE_SESSION_SEESION_ID_BLEN 16 -#define PPPOE_SESSION_SEESION_ID_FLAG HSL_RW - - - -#ifdef __cplusplus -} -#endif /* __cplusplus */ -#endif /* _HORUS_REG_H_ */ - diff --git a/feeds/ipq807x/qca-ssdk/src/include/hsl/horus/horus_reg_access.h b/feeds/ipq807x/qca-ssdk/src/include/hsl/horus/horus_reg_access.h deleted file mode 100755 index a41ef6c03..000000000 --- a/feeds/ipq807x/qca-ssdk/src/include/hsl/horus/horus_reg_access.h +++ /dev/null @@ -1,63 +0,0 @@ -/* - * Copyright (c) 2012,2018, The Linux Foundation. All rights reserved. - * Permission to use, copy, modify, and/or distribute this software for - * any purpose with or without fee is hereby granted, provided that the - * above copyright notice and this permission notice appear in all copies. - * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES - * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR - * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES - * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN - * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT - * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. - */ - - - -#ifndef _HORUS_REG_ACCESS_H_ -#define _HORUS_REG_ACCESS_H_ - -#ifdef __cplusplus -extern "C" { -#endif /* __cplusplus */ - -#include "sw.h" - - sw_error_t - horus_phy_get(a_uint32_t dev_id, a_uint32_t phy_addr, - a_uint32_t reg, a_uint16_t * value); - - sw_error_t - horus_phy_set(a_uint32_t dev_id, a_uint32_t phy_addr, - a_uint32_t reg, a_uint16_t value); - - sw_error_t - horus_reg_get(a_uint32_t dev_id, a_uint32_t reg_addr, a_uint8_t value[], - a_uint32_t value_len); - - sw_error_t - horus_reg_set(a_uint32_t dev_id, a_uint32_t reg_addr, a_uint8_t value[], - a_uint32_t value_len); - - sw_error_t - horus_reg_field_get(a_uint32_t dev_id, a_uint32_t reg_addr, - a_uint32_t bit_offset, a_uint32_t field_len, - a_uint8_t value[], a_uint32_t value_len); - - sw_error_t - horus_reg_field_set(a_uint32_t dev_id, a_uint32_t reg_addr, - a_uint32_t bit_offset, a_uint32_t field_len, - const a_uint8_t value[], a_uint32_t value_len); - - sw_error_t - horus_reg_access_init(a_uint32_t dev_id, hsl_access_mode mode); - - sw_error_t - horus_access_mode_set(a_uint32_t dev_id, hsl_access_mode mode); - -#ifdef __cplusplus -} -#endif /* __cplusplus */ - -#endif /* _HORUS_REG_ACCESS_H_ */ - diff --git a/feeds/ipq807x/qca-ssdk/src/include/hsl/horus/horus_stp.h b/feeds/ipq807x/qca-ssdk/src/include/hsl/horus/horus_stp.h deleted file mode 100755 index ed228147e..000000000 --- a/feeds/ipq807x/qca-ssdk/src/include/hsl/horus/horus_stp.h +++ /dev/null @@ -1,61 +0,0 @@ -/* - * Copyright (c) 2012, The Linux Foundation. All rights reserved. - * Permission to use, copy, modify, and/or distribute this software for - * any purpose with or without fee is hereby granted, provided that the - * above copyright notice and this permission notice appear in all copies. - * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES - * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR - * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES - * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN - * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT - * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. - */ - - -/** - * @defgroup horus_stp HORUS_STP - * @{ - */ -#ifndef _HORUS_STP_H_ -#define _HORUS_STP_H_ - -#ifdef __cplusplus -extern "C" { -#endif /* __cplusplus */ - -#include "fal/fal_stp.h" - - sw_error_t horus_stp_init(a_uint32_t dev_id); - -#ifdef IN_STP -#define HORUS_STP_INIT(rv, dev_id) \ - { \ - rv = horus_stp_init(dev_id); \ - SW_RTN_ON_ERROR(rv); \ - } -#else -#define HORUS_STP_INIT(rv, dev_id) -#endif - -#ifdef HSL_STANDALONG - - - HSL_LOCAL sw_error_t - horus_stp_port_state_set(a_uint32_t dev_id, a_uint32_t st_id, - fal_port_t port_id, fal_stp_state_t state); - - - HSL_LOCAL sw_error_t - horus_stp_port_state_get(a_uint32_t dev_id, a_uint32_t st_id, - fal_port_t port_id, fal_stp_state_t * state); - -#endif - -#ifdef __cplusplus -} -#endif /* __cplusplus */ -#endif /* _HORUS_STP_H_ */ -/** - * @} - */ diff --git a/feeds/ipq807x/qca-ssdk/src/include/hsl/horus/horus_vlan.h b/feeds/ipq807x/qca-ssdk/src/include/hsl/horus/horus_vlan.h deleted file mode 100755 index 9429131b0..000000000 --- a/feeds/ipq807x/qca-ssdk/src/include/hsl/horus/horus_vlan.h +++ /dev/null @@ -1,78 +0,0 @@ -/* - * Copyright (c) 2012, The Linux Foundation. All rights reserved. - * Permission to use, copy, modify, and/or distribute this software for - * any purpose with or without fee is hereby granted, provided that the - * above copyright notice and this permission notice appear in all copies. - * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES - * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR - * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES - * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN - * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT - * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. - */ - - -/** - * @defgroup horus_vlan HORUS_VLAN - * @{ - */ -#ifndef _HORUS_VLAN_H_ -#define _HORUS_VLAN_H_ - -#ifdef __cplusplus -extern "C" { -#endif /* __cplusplus */ - -#include "fal/fal_vlan.h" - - sw_error_t - horus_vlan_init(a_uint32_t dev_id); - -#ifdef IN_VLAN -#define HORUS_VLAN_INIT(rv, dev_id) \ - { \ - rv = horus_vlan_init(dev_id); \ - SW_RTN_ON_ERROR(rv); \ - } -#else -#define HORUS_VLAN_INIT(rv, dev_id) -#endif - -#ifdef HSL_STANDALONG - - - HSL_LOCAL sw_error_t - horus_vlan_entry_append(a_uint32_t dev_id, const fal_vlan_t * vlan_entry); - - - HSL_LOCAL sw_error_t - horus_vlan_create(a_uint32_t dev_id, a_uint32_t vlan_id); - - - HSL_LOCAL sw_error_t - horus_vlan_next(a_uint32_t dev_id, a_uint32_t vlan_id, fal_vlan_t * p_vlan); - - - HSL_LOCAL sw_error_t - horus_vlan_find(a_uint32_t dev_id, a_uint32_t vlan_id, fal_vlan_t * p_vlan); - - - HSL_LOCAL sw_error_t - horus_vlan_member_update(a_uint32_t dev_id, a_uint32_t vlan_id, - fal_pbmp_t member, fal_pbmp_t u_member); - - - HSL_LOCAL sw_error_t - horus_vlan_delete(a_uint32_t dev_id, a_uint32_t vlan_id); - -#endif - -#ifdef __cplusplus -} -#endif /* __cplusplus */ - -#endif /* _HORUS_VLAN_H_ */ -/** - * @} - */ diff --git a/feeds/ipq807x/qca-ssdk/src/include/hsl/hppe/hppe_acl.h b/feeds/ipq807x/qca-ssdk/src/include/hsl/hppe/hppe_acl.h deleted file mode 100755 index ec2bb1332..000000000 --- a/feeds/ipq807x/qca-ssdk/src/include/hsl/hppe/hppe_acl.h +++ /dev/null @@ -1,1256 +0,0 @@ -/* - * Copyright (c) 2016-2017, The Linux Foundation. All rights reserved. - * Permission to use, copy, modify, and/or distribute this software for - * any purpose with or without fee is hereby granted, provided that the - * above copyright notice and this permission notice appear in all copies. - * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES - * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR - * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES - * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN - * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT - * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. - */ - - -/** - * @defgroup - * @{ - */ -#ifndef _HPPE_ACL_H_ -#define _HPPE_ACL_H_ - -#define IPO_RULE_REG_MAX_ENTRY 512 -#define IPO_MASK_REG_MAX_ENTRY 512 -#define RULE_EXT_1_REG_MAX_ENTRY 64 -#define RULE_EXT_2_REG_MAX_ENTRY 64 -#define RULE_EXT_4_REG_MAX_ENTRY 64 -#define IPO_ACTION_MAX_ENTRY 512 -#define IPO_CNT_TBL_MAX_ENTRY 512 - -sw_error_t -hppe_non_ip_udf0_ctrl_reg_get( - a_uint32_t dev_id, - union udf_ctrl_reg_u *value); - -sw_error_t -hppe_non_ip_udf0_ctrl_reg_set( - a_uint32_t dev_id, - union udf_ctrl_reg_u *value); - -sw_error_t -hppe_non_ip_udf1_ctrl_reg_get( - a_uint32_t dev_id, - union udf_ctrl_reg_u *value); - -sw_error_t -hppe_non_ip_udf1_ctrl_reg_set( - a_uint32_t dev_id, - union udf_ctrl_reg_u *value); - -sw_error_t -hppe_non_ip_udf2_ctrl_reg_get( - a_uint32_t dev_id, - union udf_ctrl_reg_u *value); - -sw_error_t -hppe_non_ip_udf2_ctrl_reg_set( - a_uint32_t dev_id, - union udf_ctrl_reg_u *value); - -sw_error_t -hppe_non_ip_udf3_ctrl_reg_get( - a_uint32_t dev_id, - union udf_ctrl_reg_u *value); - -sw_error_t -hppe_non_ip_udf3_ctrl_reg_set( - a_uint32_t dev_id, - union udf_ctrl_reg_u *value); - -sw_error_t -hppe_ipv4_udf0_ctrl_reg_get( - a_uint32_t dev_id, - union udf_ctrl_reg_u *value); - -sw_error_t -hppe_ipv4_udf0_ctrl_reg_set( - a_uint32_t dev_id, - union udf_ctrl_reg_u *value); - -sw_error_t -hppe_ipv4_udf1_ctrl_reg_get( - a_uint32_t dev_id, - union udf_ctrl_reg_u *value); - -sw_error_t -hppe_ipv4_udf1_ctrl_reg_set( - a_uint32_t dev_id, - union udf_ctrl_reg_u *value); - -sw_error_t -hppe_ipv4_udf2_ctrl_reg_get( - a_uint32_t dev_id, - union udf_ctrl_reg_u *value); - -sw_error_t -hppe_ipv4_udf2_ctrl_reg_set( - a_uint32_t dev_id, - union udf_ctrl_reg_u *value); - -sw_error_t -hppe_ipv4_udf3_ctrl_reg_get( - a_uint32_t dev_id, - union udf_ctrl_reg_u *value); - -sw_error_t -hppe_ipv4_udf3_ctrl_reg_set( - a_uint32_t dev_id, - union udf_ctrl_reg_u *value); - -sw_error_t -hppe_ipv6_udf0_ctrl_reg_get( - a_uint32_t dev_id, - union udf_ctrl_reg_u *value); - -sw_error_t -hppe_ipv6_udf0_ctrl_reg_set( - a_uint32_t dev_id, - union udf_ctrl_reg_u *value); - -sw_error_t -hppe_ipv6_udf1_ctrl_reg_get( - a_uint32_t dev_id, - union udf_ctrl_reg_u *value); - -sw_error_t -hppe_ipv6_udf1_ctrl_reg_set( - a_uint32_t dev_id, - union udf_ctrl_reg_u *value); - -sw_error_t -hppe_ipv6_udf2_ctrl_reg_get( - a_uint32_t dev_id, - union udf_ctrl_reg_u *value); - -sw_error_t -hppe_ipv6_udf2_ctrl_reg_set( - a_uint32_t dev_id, - union udf_ctrl_reg_u *value); - -sw_error_t -hppe_ipv6_udf3_ctrl_reg_get( - a_uint32_t dev_id, - union udf_ctrl_reg_u *value); - -sw_error_t -hppe_ipv6_udf3_ctrl_reg_set( - a_uint32_t dev_id, - union udf_ctrl_reg_u *value); - -sw_error_t -hppe_non_ip_udf0_ctrl_reg_udf0_base_get( - a_uint32_t dev_id, - unsigned int *value); - -sw_error_t -hppe_non_ip_udf0_ctrl_reg_udf0_base_set( - a_uint32_t dev_id, - unsigned int value); - -sw_error_t -hppe_non_ip_udf0_ctrl_reg_udf0_offset_get( - a_uint32_t dev_id, - unsigned int *value); - -sw_error_t -hppe_non_ip_udf0_ctrl_reg_udf0_offset_set( - a_uint32_t dev_id, - unsigned int value); - -sw_error_t -hppe_non_ip_udf1_ctrl_reg_udf1_base_get( - a_uint32_t dev_id, - unsigned int *value); - -sw_error_t -hppe_non_ip_udf1_ctrl_reg_udf1_base_set( - a_uint32_t dev_id, - unsigned int value); - -sw_error_t -hppe_non_ip_udf1_ctrl_reg_udf1_offset_get( - a_uint32_t dev_id, - unsigned int *value); - -sw_error_t -hppe_non_ip_udf1_ctrl_reg_udf1_offset_set( - a_uint32_t dev_id, - unsigned int value); - -sw_error_t -hppe_non_ip_udf2_ctrl_reg_udf2_offset_get( - a_uint32_t dev_id, - unsigned int *value); - -sw_error_t -hppe_non_ip_udf2_ctrl_reg_udf2_offset_set( - a_uint32_t dev_id, - unsigned int value); - -sw_error_t -hppe_non_ip_udf2_ctrl_reg_udf2_base_get( - a_uint32_t dev_id, - unsigned int *value); - -sw_error_t -hppe_non_ip_udf2_ctrl_reg_udf2_base_set( - a_uint32_t dev_id, - unsigned int value); - -sw_error_t -hppe_non_ip_udf3_ctrl_reg_udf3_base_get( - a_uint32_t dev_id, - unsigned int *value); - -sw_error_t -hppe_non_ip_udf3_ctrl_reg_udf3_base_set( - a_uint32_t dev_id, - unsigned int value); - -sw_error_t -hppe_non_ip_udf3_ctrl_reg_udf3_offset_get( - a_uint32_t dev_id, - unsigned int *value); - -sw_error_t -hppe_non_ip_udf3_ctrl_reg_udf3_offset_set( - a_uint32_t dev_id, - unsigned int value); - -sw_error_t -hppe_ipv4_udf0_ctrl_reg_udf0_base_get( - a_uint32_t dev_id, - unsigned int *value); - -sw_error_t -hppe_ipv4_udf0_ctrl_reg_udf0_base_set( - a_uint32_t dev_id, - unsigned int value); - -sw_error_t -hppe_ipv4_udf0_ctrl_reg_udf0_offset_get( - a_uint32_t dev_id, - unsigned int *value); - -sw_error_t -hppe_ipv4_udf0_ctrl_reg_udf0_offset_set( - a_uint32_t dev_id, - unsigned int value); - -sw_error_t -hppe_ipv4_udf1_ctrl_reg_udf1_base_get( - a_uint32_t dev_id, - unsigned int *value); - -sw_error_t -hppe_ipv4_udf1_ctrl_reg_udf1_base_set( - a_uint32_t dev_id, - unsigned int value); - -sw_error_t -hppe_ipv4_udf1_ctrl_reg_udf1_offset_get( - a_uint32_t dev_id, - unsigned int *value); - -sw_error_t -hppe_ipv4_udf1_ctrl_reg_udf1_offset_set( - a_uint32_t dev_id, - unsigned int value); - -sw_error_t -hppe_ipv4_udf2_ctrl_reg_udf2_offset_get( - a_uint32_t dev_id, - unsigned int *value); - -sw_error_t -hppe_ipv4_udf2_ctrl_reg_udf2_offset_set( - a_uint32_t dev_id, - unsigned int value); - -sw_error_t -hppe_ipv4_udf2_ctrl_reg_udf2_base_get( - a_uint32_t dev_id, - unsigned int *value); - -sw_error_t -hppe_ipv4_udf2_ctrl_reg_udf2_base_set( - a_uint32_t dev_id, - unsigned int value); - -sw_error_t -hppe_ipv4_udf3_ctrl_reg_udf3_base_get( - a_uint32_t dev_id, - unsigned int *value); - -sw_error_t -hppe_ipv4_udf3_ctrl_reg_udf3_base_set( - a_uint32_t dev_id, - unsigned int value); - -sw_error_t -hppe_ipv4_udf3_ctrl_reg_udf3_offset_get( - a_uint32_t dev_id, - unsigned int *value); - -sw_error_t -hppe_ipv4_udf3_ctrl_reg_udf3_offset_set( - a_uint32_t dev_id, - unsigned int value); - -sw_error_t -hppe_ipv6_udf0_ctrl_reg_udf0_base_get( - a_uint32_t dev_id, - unsigned int *value); - -sw_error_t -hppe_ipv6_udf0_ctrl_reg_udf0_base_set( - a_uint32_t dev_id, - unsigned int value); - -sw_error_t -hppe_ipv6_udf0_ctrl_reg_udf0_offset_get( - a_uint32_t dev_id, - unsigned int *value); - -sw_error_t -hppe_ipv6_udf0_ctrl_reg_udf0_offset_set( - a_uint32_t dev_id, - unsigned int value); - -sw_error_t -hppe_ipv6_udf1_ctrl_reg_udf1_base_get( - a_uint32_t dev_id, - unsigned int *value); - -sw_error_t -hppe_ipv6_udf1_ctrl_reg_udf1_base_set( - a_uint32_t dev_id, - unsigned int value); - -sw_error_t -hppe_ipv6_udf1_ctrl_reg_udf1_offset_get( - a_uint32_t dev_id, - unsigned int *value); - -sw_error_t -hppe_ipv6_udf1_ctrl_reg_udf1_offset_set( - a_uint32_t dev_id, - unsigned int value); - -sw_error_t -hppe_ipv6_udf2_ctrl_reg_udf2_offset_get( - a_uint32_t dev_id, - unsigned int *value); - -sw_error_t -hppe_ipv6_udf2_ctrl_reg_udf2_offset_set( - a_uint32_t dev_id, - unsigned int value); - -sw_error_t -hppe_ipv6_udf2_ctrl_reg_udf2_base_get( - a_uint32_t dev_id, - unsigned int *value); - -sw_error_t -hppe_ipv6_udf2_ctrl_reg_udf2_base_set( - a_uint32_t dev_id, - unsigned int value); - -sw_error_t -hppe_ipv6_udf3_ctrl_reg_udf3_base_get( - a_uint32_t dev_id, - unsigned int *value); - -sw_error_t -hppe_ipv6_udf3_ctrl_reg_udf3_base_set( - a_uint32_t dev_id, - unsigned int value); - -sw_error_t -hppe_ipv6_udf3_ctrl_reg_udf3_offset_get( - a_uint32_t dev_id, - unsigned int *value); - -sw_error_t -hppe_ipv6_udf3_ctrl_reg_udf3_offset_set( - a_uint32_t dev_id, - unsigned int value); - -sw_error_t -hppe_ipo_rule_reg_get( - a_uint32_t dev_id, - a_uint32_t index, - union ipo_rule_reg_u *value); - -sw_error_t -hppe_ipo_rule_reg_set( - a_uint32_t dev_id, - a_uint32_t index, - union ipo_rule_reg_u *value); - -sw_error_t -hppe_ipo_mask_reg_get( - a_uint32_t dev_id, - a_uint32_t index, - union ipo_mask_reg_u *value); - -sw_error_t -hppe_ipo_mask_reg_set( - a_uint32_t dev_id, - a_uint32_t index, - union ipo_mask_reg_u *value); - -sw_error_t -hppe_rule_ext_1_reg_get( - a_uint32_t dev_id, - a_uint32_t index, - union rule_ext_1_reg_u *value); - -sw_error_t -hppe_rule_ext_1_reg_set( - a_uint32_t dev_id, - a_uint32_t index, - union rule_ext_1_reg_u *value); - -sw_error_t -hppe_rule_ext_2_reg_get( - a_uint32_t dev_id, - a_uint32_t index, - union rule_ext_2_reg_u *value); - -sw_error_t -hppe_rule_ext_2_reg_set( - a_uint32_t dev_id, - a_uint32_t index, - union rule_ext_2_reg_u *value); - -sw_error_t -hppe_rule_ext_4_reg_get( - a_uint32_t dev_id, - a_uint32_t index, - union rule_ext_4_reg_u *value); - -sw_error_t -hppe_rule_ext_4_reg_set( - a_uint32_t dev_id, - a_uint32_t index, - union rule_ext_4_reg_u *value); - -sw_error_t -hppe_ipo_dbg_addr_reg_get( - a_uint32_t dev_id, - union ipo_dbg_addr_reg_u *value); - -sw_error_t -hppe_ipo_dbg_addr_reg_set( - a_uint32_t dev_id, - union ipo_dbg_addr_reg_u *value); - -sw_error_t -hppe_ipo_dbg_data_reg_get( - a_uint32_t dev_id, - union ipo_dbg_data_reg_u *value); - -sw_error_t -hppe_ipo_dbg_data_reg_set( - a_uint32_t dev_id, - union ipo_dbg_data_reg_u *value); - -sw_error_t -hppe_ipo_spare_reg_reg_get( - a_uint32_t dev_id, - union ipo_spare_reg_reg_u *value); - -sw_error_t -hppe_ipo_spare_reg_reg_set( - a_uint32_t dev_id, - union ipo_spare_reg_reg_u *value); - -sw_error_t -hppe_ipo_glb_hit_counter_reg_get( - a_uint32_t dev_id, - union ipo_glb_hit_counter_reg_u *value); - -sw_error_t -hppe_ipo_glb_hit_counter_reg_set( - a_uint32_t dev_id, - union ipo_glb_hit_counter_reg_u *value); - -sw_error_t -hppe_ipo_glb_miss_counter_reg_get( - a_uint32_t dev_id, - union ipo_glb_miss_counter_reg_u *value); - -sw_error_t -hppe_ipo_glb_miss_counter_reg_set( - a_uint32_t dev_id, - union ipo_glb_miss_counter_reg_u *value); - -sw_error_t -hppe_ipo_glb_bypass_counter_reg_get( - a_uint32_t dev_id, - union ipo_glb_bypass_counter_reg_u *value); - -sw_error_t -hppe_ipo_glb_bypass_counter_reg_set( - a_uint32_t dev_id, - union ipo_glb_bypass_counter_reg_u *value); - -sw_error_t -hppe_ipo_cnt_tbl_get( - a_uint32_t dev_id, - a_uint32_t index, - union ipo_cnt_tbl_u *value); - -sw_error_t -hppe_ipo_cnt_tbl_set( - a_uint32_t dev_id, - a_uint32_t index, - union ipo_cnt_tbl_u *value); - -sw_error_t -hppe_ipo_cnt_tbl_hit_byte_cnt_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint64_t *value); - -sw_error_t -hppe_ipo_cnt_tbl_hit_byte_cnt_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint64_t value); - -sw_error_t -hppe_ipo_cnt_tbl_hit_pkt_cnt_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_ipo_cnt_tbl_hit_pkt_cnt_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); -sw_error_t -hppe_ipo_rule_reg_src_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_ipo_rule_reg_src_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_ipo_rule_reg_inverse_en_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_ipo_rule_reg_inverse_en_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_ipo_rule_reg_rule_type_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_ipo_rule_reg_rule_type_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_ipo_rule_reg_src_type_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_ipo_rule_reg_src_type_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_ipo_rule_reg_range_en_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_ipo_rule_reg_range_en_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_ipo_rule_reg_post_routing_en_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_ipo_rule_reg_post_routing_en_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_ipo_rule_reg_fake_mac_header_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_ipo_rule_reg_fake_mac_header_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_ipo_rule_reg_res_chain_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_ipo_rule_reg_res_chain_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_ipo_rule_reg_pri_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_ipo_rule_reg_pri_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_ipo_rule_reg_rule_field_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint64_t *value); - -sw_error_t -hppe_ipo_rule_reg_rule_field_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint64_t value); - -sw_error_t -hppe_ipo_mask_reg_maskfield_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint64_t *value); - -sw_error_t -hppe_ipo_mask_reg_maskfield_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint64_t value); - -sw_error_t -hppe_rule_ext_1_reg_ext2_2_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_rule_ext_1_reg_ext2_2_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_rule_ext_1_reg_ext2_0_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_rule_ext_1_reg_ext2_0_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_rule_ext_1_reg_ext2_3_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_rule_ext_1_reg_ext2_3_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_rule_ext_1_reg_ext2_1_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_rule_ext_1_reg_ext2_1_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_rule_ext_2_reg_ext4_0_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_rule_ext_2_reg_ext4_0_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_rule_ext_2_reg_ext4_1_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_rule_ext_2_reg_ext4_1_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_rule_ext_4_reg_ext8_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_rule_ext_4_reg_ext8_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_ipo_dbg_addr_reg_ipo_dbg_addr_get( - a_uint32_t dev_id, - unsigned int *value); - -sw_error_t -hppe_ipo_dbg_addr_reg_ipo_dbg_addr_set( - a_uint32_t dev_id, - unsigned int value); - -sw_error_t -hppe_ipo_dbg_data_reg_ipo_dbg_data_get( - a_uint32_t dev_id, - unsigned int *value); - -sw_error_t -hppe_ipo_dbg_data_reg_ipo_dbg_data_set( - a_uint32_t dev_id, - unsigned int value); - -sw_error_t -hppe_ipo_spare_reg_reg_spare_reg_get( - a_uint32_t dev_id, - unsigned int *value); - -sw_error_t -hppe_ipo_spare_reg_reg_spare_reg_set( - a_uint32_t dev_id, - unsigned int value); - -sw_error_t -hppe_ipo_glb_hit_counter_reg_hit_count_get( - a_uint32_t dev_id, - unsigned int *value); - -sw_error_t -hppe_ipo_glb_hit_counter_reg_hit_count_set( - a_uint32_t dev_id, - unsigned int value); - -sw_error_t -hppe_ipo_glb_miss_counter_reg_miss_count_get( - a_uint32_t dev_id, - unsigned int *value); - -sw_error_t -hppe_ipo_glb_miss_counter_reg_miss_count_set( - a_uint32_t dev_id, - unsigned int value); - -sw_error_t -hppe_ipo_glb_bypass_counter_reg_bypass_count_get( - a_uint32_t dev_id, - unsigned int *value); - -sw_error_t -hppe_ipo_glb_bypass_counter_reg_bypass_count_set( - a_uint32_t dev_id, - unsigned int value); - -sw_error_t -hppe_ipo_action_get( - a_uint32_t dev_id, - a_uint32_t index, - union ipo_action_u *value); - -sw_error_t -hppe_ipo_action_set( - a_uint32_t dev_id, - a_uint32_t index, - union ipo_action_u *value); - -sw_error_t -hppe_ipo_action_mirror_en_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_ipo_action_mirror_en_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_ipo_action_ctag_pcp_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_ipo_action_ctag_pcp_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_ipo_action_int_dp_change_en_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_ipo_action_int_dp_change_en_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_ipo_action_enqueue_pri_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_ipo_action_enqueue_pri_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_ipo_action_stag_pcp_change_en_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_ipo_action_stag_pcp_change_en_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_ipo_action_dscp_tc_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_ipo_action_dscp_tc_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_ipo_action_cpu_code_en_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_ipo_action_cpu_code_en_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_ipo_action_stag_dei_change_en_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_ipo_action_stag_dei_change_en_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_ipo_action_ctag_fmt_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_ipo_action_ctag_fmt_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_ipo_action_dest_info_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_ipo_action_dest_info_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_ipo_action_svid_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_ipo_action_svid_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_ipo_action_dest_info_change_en_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_ipo_action_dest_info_change_en_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_ipo_action_policer_en_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_ipo_action_policer_en_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_ipo_action_int_dp_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_ipo_action_int_dp_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_ipo_action_ctag_pcp_change_en_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_ipo_action_ctag_pcp_change_en_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_ipo_action_metadata_en_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_ipo_action_metadata_en_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_ipo_action_enqueue_pri_change_en_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_ipo_action_enqueue_pri_change_en_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_ipo_action_stag_dei_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_ipo_action_stag_dei_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_ipo_action_fwd_cmd_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_ipo_action_fwd_cmd_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_ipo_action_bypass_bitmap_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_ipo_action_bypass_bitmap_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_ipo_action_ctag_dei_change_en_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_ipo_action_ctag_dei_change_en_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_ipo_action_policer_index_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_ipo_action_policer_index_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_ipo_action_ctag_dei_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_ipo_action_ctag_dei_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_ipo_action_stag_pcp_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_ipo_action_stag_pcp_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_ipo_action_syn_toggle_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_ipo_action_syn_toggle_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_ipo_action_service_code_en_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_ipo_action_service_code_en_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_ipo_action_qid_en_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_ipo_action_qid_en_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_ipo_action_service_code_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_ipo_action_service_code_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_ipo_action_cvid_change_en_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_ipo_action_cvid_change_en_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_ipo_action_cvid_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_ipo_action_cvid_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_ipo_action_svid_change_en_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_ipo_action_svid_change_en_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_ipo_action_cpu_code_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_ipo_action_cpu_code_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_ipo_action_dscp_tc_change_en_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_ipo_action_dscp_tc_change_en_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_ipo_action_qid_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_ipo_action_qid_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_ipo_action_stag_fmt_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_ipo_action_stag_fmt_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - - -#endif - diff --git a/feeds/ipq807x/qca-ssdk/src/include/hsl/hppe/hppe_acl_reg.h b/feeds/ipq807x/qca-ssdk/src/include/hsl/hppe/hppe_acl_reg.h deleted file mode 100755 index db18ea4e7..000000000 --- a/feeds/ipq807x/qca-ssdk/src/include/hsl/hppe/hppe_acl_reg.h +++ /dev/null @@ -1,842 +0,0 @@ -/* - * Copyright (c) 2016-2017, The Linux Foundation. All rights reserved. - * Permission to use, copy, modify, and/or distribute this software for - * any purpose with or without fee is hereby granted, provided that the - * above copyright notice and this permission notice appear in all copies. - * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES - * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR - * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES - * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN - * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT - * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. - */ - - -/** - * @defgroup - * @{ - */ -#ifndef HPPE_ACL_REG_H -#define HPPE_ACL_REG_H - -/*[register] NON_IP_UDF0_CTRL_REG*/ -#define NON_IP_UDF0_CTRL_REG -#define NON_IP_UDF0_CTRL_REG_ADDRESS 0x38 -#define NON_IP_UDF0_CTRL_REG_NUM 1 -#define NON_IP_UDF0_CTRL_REG_INC 0x4 -#define NON_IP_UDF0_CTRL_REG_TYPE REG_TYPE_RW -#define NON_IP_UDF0_CTRL_REG_DEFAULT 0x0 - /*[field] UDF0_BASE*/ - #define NON_IP_UDF0_CTRL_REG_UDF0_BASE - #define NON_IP_UDF0_CTRL_REG_UDF0_BASE_OFFSET 0 - #define NON_IP_UDF0_CTRL_REG_UDF0_BASE_LEN 2 - #define NON_IP_UDF0_CTRL_REG_UDF0_BASE_DEFAULT 0x0 - /*[field] UDF0_OFFSET*/ - #define NON_IP_UDF0_CTRL_REG_UDF0_OFFSET - #define NON_IP_UDF0_CTRL_REG_UDF0_OFFSET_OFFSET 8 - #define NON_IP_UDF0_CTRL_REG_UDF0_OFFSET_LEN 6 - #define NON_IP_UDF0_CTRL_REG_UDF0_OFFSET_DEFAULT 0x0 - -struct udf_ctrl_reg { - a_uint32_t udf_base:2; - a_uint32_t _reserved0:6; - a_uint32_t udf_offset:6; - a_uint32_t _reserved1:18; -}; - -union udf_ctrl_reg_u { - a_uint32_t val; - struct udf_ctrl_reg bf; -}; - -/*[register] NON_IP_UDF1_CTRL_REG*/ -#define NON_IP_UDF1_CTRL_REG -#define NON_IP_UDF1_CTRL_REG_ADDRESS 0x3c -#define NON_IP_UDF1_CTRL_REG_NUM 1 -#define NON_IP_UDF1_CTRL_REG_INC 0x4 -#define NON_IP_UDF1_CTRL_REG_TYPE REG_TYPE_RW -#define NON_IP_UDF1_CTRL_REG_DEFAULT 0x0 - /*[field] UDF1_BASE*/ - #define NON_IP_UDF1_CTRL_REG_UDF1_BASE - #define NON_IP_UDF1_CTRL_REG_UDF1_BASE_OFFSET 0 - #define NON_IP_UDF1_CTRL_REG_UDF1_BASE_LEN 2 - #define NON_IP_UDF1_CTRL_REG_UDF1_BASE_DEFAULT 0x0 - /*[field] UDF1_OFFSET*/ - #define NON_IP_UDF1_CTRL_REG_UDF1_OFFSET - #define NON_IP_UDF1_CTRL_REG_UDF1_OFFSET_OFFSET 8 - #define NON_IP_UDF1_CTRL_REG_UDF1_OFFSET_LEN 6 - #define NON_IP_UDF1_CTRL_REG_UDF1_OFFSET_DEFAULT 0x0 - -/*[register] NON_IP_UDF2_CTRL_REG*/ -#define NON_IP_UDF2_CTRL_REG -#define NON_IP_UDF2_CTRL_REG_ADDRESS 0x40 -#define NON_IP_UDF2_CTRL_REG_NUM 1 -#define NON_IP_UDF2_CTRL_REG_INC 0x4 -#define NON_IP_UDF2_CTRL_REG_TYPE REG_TYPE_RW -#define NON_IP_UDF2_CTRL_REG_DEFAULT 0x0 - /*[field] UDF2_BASE*/ - #define NON_IP_UDF2_CTRL_REG_UDF2_BASE - #define NON_IP_UDF2_CTRL_REG_UDF2_BASE_OFFSET 0 - #define NON_IP_UDF2_CTRL_REG_UDF2_BASE_LEN 2 - #define NON_IP_UDF2_CTRL_REG_UDF2_BASE_DEFAULT 0x0 - /*[field] UDF2_OFFSET*/ - #define NON_IP_UDF2_CTRL_REG_UDF2_OFFSET - #define NON_IP_UDF2_CTRL_REG_UDF2_OFFSET_OFFSET 8 - #define NON_IP_UDF2_CTRL_REG_UDF2_OFFSET_LEN 6 - #define NON_IP_UDF2_CTRL_REG_UDF2_OFFSET_DEFAULT 0x0 - -/*[register] NON_IP_UDF3_CTRL_REG*/ -#define NON_IP_UDF3_CTRL_REG -#define NON_IP_UDF3_CTRL_REG_ADDRESS 0x44 -#define NON_IP_UDF3_CTRL_REG_NUM 1 -#define NON_IP_UDF3_CTRL_REG_INC 0x4 -#define NON_IP_UDF3_CTRL_REG_TYPE REG_TYPE_RW -#define NON_IP_UDF3_CTRL_REG_DEFAULT 0x0 - /*[field] UDF3_BASE*/ - #define NON_IP_UDF3_CTRL_REG_UDF3_BASE - #define NON_IP_UDF3_CTRL_REG_UDF3_BASE_OFFSET 0 - #define NON_IP_UDF3_CTRL_REG_UDF3_BASE_LEN 2 - #define NON_IP_UDF3_CTRL_REG_UDF3_BASE_DEFAULT 0x0 - /*[field] UDF3_OFFSET*/ - #define NON_IP_UDF3_CTRL_REG_UDF3_OFFSET - #define NON_IP_UDF3_CTRL_REG_UDF3_OFFSET_OFFSET 8 - #define NON_IP_UDF3_CTRL_REG_UDF3_OFFSET_LEN 6 - #define NON_IP_UDF3_CTRL_REG_UDF3_OFFSET_DEFAULT 0x0 - -/*[register] IPV4_UDF0_CTRL_REG*/ -#define IPV4_UDF0_CTRL_REG -#define IPV4_UDF0_CTRL_REG_ADDRESS 0x48 -#define IPV4_UDF0_CTRL_REG_NUM 1 -#define IPV4_UDF0_CTRL_REG_INC 0x4 -#define IPV4_UDF0_CTRL_REG_TYPE REG_TYPE_RW -#define IPV4_UDF0_CTRL_REG_DEFAULT 0x0 - /*[field] UDF0_BASE*/ - #define IPV4_UDF0_CTRL_REG_UDF0_BASE - #define IPV4_UDF0_CTRL_REG_UDF0_BASE_OFFSET 0 - #define IPV4_UDF0_CTRL_REG_UDF0_BASE_LEN 2 - #define IPV4_UDF0_CTRL_REG_UDF0_BASE_DEFAULT 0x0 - /*[field] UDF0_OFFSET*/ - #define IPV4_UDF0_CTRL_REG_UDF0_OFFSET - #define IPV4_UDF0_CTRL_REG_UDF0_OFFSET_OFFSET 8 - #define IPV4_UDF0_CTRL_REG_UDF0_OFFSET_LEN 6 - #define IPV4_UDF0_CTRL_REG_UDF0_OFFSET_DEFAULT 0x0 - -/*[register] IPV4_UDF1_CTRL_REG*/ -#define IPV4_UDF1_CTRL_REG -#define IPV4_UDF1_CTRL_REG_ADDRESS 0x4c -#define IPV4_UDF1_CTRL_REG_NUM 1 -#define IPV4_UDF1_CTRL_REG_INC 0x4 -#define IPV4_UDF1_CTRL_REG_TYPE REG_TYPE_RW -#define IPV4_UDF1_CTRL_REG_DEFAULT 0x0 - /*[field] UDF1_BASE*/ - #define IPV4_UDF1_CTRL_REG_UDF1_BASE - #define IPV4_UDF1_CTRL_REG_UDF1_BASE_OFFSET 0 - #define IPV4_UDF1_CTRL_REG_UDF1_BASE_LEN 2 - #define IPV4_UDF1_CTRL_REG_UDF1_BASE_DEFAULT 0x0 - /*[field] UDF1_OFFSET*/ - #define IPV4_UDF1_CTRL_REG_UDF1_OFFSET - #define IPV4_UDF1_CTRL_REG_UDF1_OFFSET_OFFSET 8 - #define IPV4_UDF1_CTRL_REG_UDF1_OFFSET_LEN 6 - #define IPV4_UDF1_CTRL_REG_UDF1_OFFSET_DEFAULT 0x0 - -/*[register] IPV4_UDF2_CTRL_REG*/ -#define IPV4_UDF2_CTRL_REG -#define IPV4_UDF2_CTRL_REG_ADDRESS 0x50 -#define IPV4_UDF2_CTRL_REG_NUM 1 -#define IPV4_UDF2_CTRL_REG_INC 0x4 -#define IPV4_UDF2_CTRL_REG_TYPE REG_TYPE_RW -#define IPV4_UDF2_CTRL_REG_DEFAULT 0x0 - /*[field] UDF2_BASE*/ - #define IPV4_UDF2_CTRL_REG_UDF2_BASE - #define IPV4_UDF2_CTRL_REG_UDF2_BASE_OFFSET 0 - #define IPV4_UDF2_CTRL_REG_UDF2_BASE_LEN 2 - #define IPV4_UDF2_CTRL_REG_UDF2_BASE_DEFAULT 0x0 - /*[field] UDF2_OFFSET*/ - #define IPV4_UDF2_CTRL_REG_UDF2_OFFSET - #define IPV4_UDF2_CTRL_REG_UDF2_OFFSET_OFFSET 8 - #define IPV4_UDF2_CTRL_REG_UDF2_OFFSET_LEN 6 - #define IPV4_UDF2_CTRL_REG_UDF2_OFFSET_DEFAULT 0x0 - -/*[register] IPV4_UDF3_CTRL_REG*/ -#define IPV4_UDF3_CTRL_REG -#define IPV4_UDF3_CTRL_REG_ADDRESS 0x54 -#define IPV4_UDF3_CTRL_REG_NUM 1 -#define IPV4_UDF3_CTRL_REG_INC 0x4 -#define IPV4_UDF3_CTRL_REG_TYPE REG_TYPE_RW -#define IPV4_UDF3_CTRL_REG_DEFAULT 0x0 - /*[field] UDF3_BASE*/ - #define IPV4_UDF3_CTRL_REG_UDF3_BASE - #define IPV4_UDF3_CTRL_REG_UDF3_BASE_OFFSET 0 - #define IPV4_UDF3_CTRL_REG_UDF3_BASE_LEN 2 - #define IPV4_UDF3_CTRL_REG_UDF3_BASE_DEFAULT 0x0 - /*[field] UDF3_OFFSET*/ - #define IPV4_UDF3_CTRL_REG_UDF3_OFFSET - #define IPV4_UDF3_CTRL_REG_UDF3_OFFSET_OFFSET 8 - #define IPV4_UDF3_CTRL_REG_UDF3_OFFSET_LEN 6 - #define IPV4_UDF3_CTRL_REG_UDF3_OFFSET_DEFAULT 0x0 - -/*[register] IPV6_UDF0_CTRL_REG*/ -#define IPV6_UDF0_CTRL_REG -#define IPV6_UDF0_CTRL_REG_ADDRESS 0x58 -#define IPV6_UDF0_CTRL_REG_NUM 1 -#define IPV6_UDF0_CTRL_REG_INC 0x4 -#define IPV6_UDF0_CTRL_REG_TYPE REG_TYPE_RW -#define IPV6_UDF0_CTRL_REG_DEFAULT 0x0 - /*[field] UDF0_BASE*/ - #define IPV6_UDF0_CTRL_REG_UDF0_BASE - #define IPV6_UDF0_CTRL_REG_UDF0_BASE_OFFSET 0 - #define IPV6_UDF0_CTRL_REG_UDF0_BASE_LEN 2 - #define IPV6_UDF0_CTRL_REG_UDF0_BASE_DEFAULT 0x0 - /*[field] UDF0_OFFSET*/ - #define IPV6_UDF0_CTRL_REG_UDF0_OFFSET - #define IPV6_UDF0_CTRL_REG_UDF0_OFFSET_OFFSET 8 - #define IPV6_UDF0_CTRL_REG_UDF0_OFFSET_LEN 6 - #define IPV6_UDF0_CTRL_REG_UDF0_OFFSET_DEFAULT 0x0 - -/*[register] IPV6_UDF1_CTRL_REG*/ -#define IPV6_UDF1_CTRL_REG -#define IPV6_UDF1_CTRL_REG_ADDRESS 0x5c -#define IPV6_UDF1_CTRL_REG_NUM 1 -#define IPV6_UDF1_CTRL_REG_INC 0x4 -#define IPV6_UDF1_CTRL_REG_TYPE REG_TYPE_RW -#define IPV6_UDF1_CTRL_REG_DEFAULT 0x0 - /*[field] UDF1_BASE*/ - #define IPV6_UDF1_CTRL_REG_UDF1_BASE - #define IPV6_UDF1_CTRL_REG_UDF1_BASE_OFFSET 0 - #define IPV6_UDF1_CTRL_REG_UDF1_BASE_LEN 2 - #define IPV6_UDF1_CTRL_REG_UDF1_BASE_DEFAULT 0x0 - /*[field] UDF1_OFFSET*/ - #define IPV6_UDF1_CTRL_REG_UDF1_OFFSET - #define IPV6_UDF1_CTRL_REG_UDF1_OFFSET_OFFSET 8 - #define IPV6_UDF1_CTRL_REG_UDF1_OFFSET_LEN 6 - #define IPV6_UDF1_CTRL_REG_UDF1_OFFSET_DEFAULT 0x0 - -/*[register] IPV6_UDF2_CTRL_REG*/ -#define IPV6_UDF2_CTRL_REG -#define IPV6_UDF2_CTRL_REG_ADDRESS 0x60 -#define IPV6_UDF2_CTRL_REG_NUM 1 -#define IPV6_UDF2_CTRL_REG_INC 0x4 -#define IPV6_UDF2_CTRL_REG_TYPE REG_TYPE_RW -#define IPV6_UDF2_CTRL_REG_DEFAULT 0x0 - /*[field] UDF2_BASE*/ - #define IPV6_UDF2_CTRL_REG_UDF2_BASE - #define IPV6_UDF2_CTRL_REG_UDF2_BASE_OFFSET 0 - #define IPV6_UDF2_CTRL_REG_UDF2_BASE_LEN 2 - #define IPV6_UDF2_CTRL_REG_UDF2_BASE_DEFAULT 0x0 - /*[field] UDF2_OFFSET*/ - #define IPV6_UDF2_CTRL_REG_UDF2_OFFSET - #define IPV6_UDF2_CTRL_REG_UDF2_OFFSET_OFFSET 8 - #define IPV6_UDF2_CTRL_REG_UDF2_OFFSET_LEN 6 - #define IPV6_UDF2_CTRL_REG_UDF2_OFFSET_DEFAULT 0x0 - -/*[register] IPV6_UDF3_CTRL_REG*/ -#define IPV6_UDF3_CTRL_REG -#define IPV6_UDF3_CTRL_REG_ADDRESS 0x64 -#define IPV6_UDF3_CTRL_REG_NUM 1 -#define IPV6_UDF3_CTRL_REG_INC 0x4 -#define IPV6_UDF3_CTRL_REG_TYPE REG_TYPE_RW -#define IPV6_UDF3_CTRL_REG_DEFAULT 0x0 - /*[field] UDF3_BASE*/ - #define IPV6_UDF3_CTRL_REG_UDF3_BASE - #define IPV6_UDF3_CTRL_REG_UDF3_BASE_OFFSET 0 - #define IPV6_UDF3_CTRL_REG_UDF3_BASE_LEN 2 - #define IPV6_UDF3_CTRL_REG_UDF3_BASE_DEFAULT 0x0 - /*[field] UDF3_OFFSET*/ - #define IPV6_UDF3_CTRL_REG_UDF3_OFFSET - #define IPV6_UDF3_CTRL_REG_UDF3_OFFSET_OFFSET 8 - #define IPV6_UDF3_CTRL_REG_UDF3_OFFSET_LEN 6 - #define IPV6_UDF3_CTRL_REG_UDF3_OFFSET_DEFAULT 0x0 - -/*[table] IPO_RULE_REG*/ -#define IPO_RULE_REG -#define IPO_RULE_REG_ADDRESS 0x0 -#define IPO_RULE_REG_NUM 512 -#define IPO_RULE_REG_INC 0x10 -#define IPO_RULE_REG_TYPE REG_TYPE_RW -#define IPO_RULE_REG_DEFAULT 0x0 - /*[field] RULE_FIELD*/ - #define IPO_RULE_REG_RULE_FIELD - #define IPO_RULE_REG_RULE_FIELD_OFFSET 0 - #define IPO_RULE_REG_RULE_FIELD_LEN 52 - #define IPO_RULE_REG_RULE_FIELD_DEFAULT 0x0 - /*[field] FAKE_MAC_HEADER*/ - #define IPO_RULE_REG_FAKE_MAC_HEADER - #define IPO_RULE_REG_FAKE_MAC_HEADER_OFFSET 52 - #define IPO_RULE_REG_FAKE_MAC_HEADER_LEN 1 - #define IPO_RULE_REG_FAKE_MAC_HEADER_DEFAULT 0x0 - /*[field] RANGE_EN*/ - #define IPO_RULE_REG_RANGE_EN - #define IPO_RULE_REG_RANGE_EN_OFFSET 53 - #define IPO_RULE_REG_RANGE_EN_LEN 1 - #define IPO_RULE_REG_RANGE_EN_DEFAULT 0x0 - /*[field] INVERSE_EN*/ - #define IPO_RULE_REG_INVERSE_EN - #define IPO_RULE_REG_INVERSE_EN_OFFSET 54 - #define IPO_RULE_REG_INVERSE_EN_LEN 1 - #define IPO_RULE_REG_INVERSE_EN_DEFAULT 0x0 - /*[field] RULE_TYPE*/ - #define IPO_RULE_REG_RULE_TYPE - #define IPO_RULE_REG_RULE_TYPE_OFFSET 55 - #define IPO_RULE_REG_RULE_TYPE_LEN 4 - #define IPO_RULE_REG_RULE_TYPE_DEFAULT 0x0 - /*[field] SRC_TYPE*/ - #define IPO_RULE_REG_SRC_TYPE - #define IPO_RULE_REG_SRC_TYPE_OFFSET 59 - #define IPO_RULE_REG_SRC_TYPE_LEN 2 - #define IPO_RULE_REG_SRC_TYPE_DEFAULT 0x0 - /*[field] SRC*/ - #define IPO_RULE_REG_SRC - #define IPO_RULE_REG_SRC_OFFSET 61 - #define IPO_RULE_REG_SRC_LEN 8 - #define IPO_RULE_REG_SRC_DEFAULT 0x0 - /*[field] PRI*/ - #define IPO_RULE_REG_PRI - #define IPO_RULE_REG_PRI_OFFSET 69 - #define IPO_RULE_REG_PRI_LEN 9 - #define IPO_RULE_REG_PRI_DEFAULT 0x0 - /*[field] RES_CHAIN*/ - #define IPO_RULE_REG_RES_CHAIN - #define IPO_RULE_REG_RES_CHAIN_OFFSET 78 - #define IPO_RULE_REG_RES_CHAIN_LEN 1 - #define IPO_RULE_REG_RES_CHAIN_DEFAULT 0x0 - /*[field] POST_ROUTING_EN*/ - #define IPO_RULE_REG_POST_ROUTING_EN - #define IPO_RULE_REG_POST_ROUTING_EN_OFFSET 79 - #define IPO_RULE_REG_POST_ROUTING_EN_LEN 1 - #define IPO_RULE_REG_POST_ROUTING_EN_DEFAULT 0x0 - -struct ipo_rule_reg { - a_uint32_t rule_field_0:32; - a_uint32_t rule_field_1:20; - a_uint32_t fake_mac_header:1; - a_uint32_t range_en:1; - a_uint32_t inverse_en:1; - a_uint32_t rule_type:4; - a_uint32_t src_type:2; - a_uint32_t src_0:3; - a_uint32_t src_1:5; - a_uint32_t pri:9; - a_uint32_t res_chain:1; - a_uint32_t post_routing_en:1; - a_uint32_t _reserved0:16; -}; - -union ipo_rule_reg_u { - a_uint32_t val[3]; - struct ipo_rule_reg bf; -}; - -/*[table] IPO_MASK_REG*/ -#define IPO_MASK_REG -#define IPO_MASK_REG_ADDRESS 0x2000 -#define IPO_MASK_REG_NUM 512 -#define IPO_MASK_REG_INC 0x10 -#define IPO_MASK_REG_TYPE REG_TYPE_RW -#define IPO_MASK_REG_DEFAULT 0x0 - /*[field] MASKFIELD*/ - #define IPO_MASK_REG_MASKFIELD - #define IPO_MASK_REG_MASKFIELD_OFFSET 0 - #define IPO_MASK_REG_MASKFIELD_LEN 53 - #define IPO_MASK_REG_MASKFIELD_DEFAULT 0x0 - -struct ipo_mask_reg { - a_uint32_t maskfield_0:32; - a_uint32_t maskfield_1:21; - a_uint32_t _reserved0:11; -}; - -union ipo_mask_reg_u { - a_uint32_t val[2]; - struct ipo_mask_reg bf; -}; - -/*[register] RULE_EXT_1_REG*/ -#define RULE_EXT_1_REG -#define RULE_EXT_1_REG_ADDRESS 0x4000 -#define RULE_EXT_1_REG_NUM 64 -#define RULE_EXT_1_REG_INC 0x4 -#define RULE_EXT_1_REG_TYPE REG_TYPE_RW -#define RULE_EXT_1_REG_DEFAULT 0x0 - /*[field] EXT2_0*/ - #define RULE_EXT_1_REG_EXT2_0 - #define RULE_EXT_1_REG_EXT2_0_OFFSET 0 - #define RULE_EXT_1_REG_EXT2_0_LEN 1 - #define RULE_EXT_1_REG_EXT2_0_DEFAULT 0x0 - /*[field] EXT2_1*/ - #define RULE_EXT_1_REG_EXT2_1 - #define RULE_EXT_1_REG_EXT2_1_OFFSET 1 - #define RULE_EXT_1_REG_EXT2_1_LEN 1 - #define RULE_EXT_1_REG_EXT2_1_DEFAULT 0x0 - /*[field] EXT2_2*/ - #define RULE_EXT_1_REG_EXT2_2 - #define RULE_EXT_1_REG_EXT2_2_OFFSET 2 - #define RULE_EXT_1_REG_EXT2_2_LEN 1 - #define RULE_EXT_1_REG_EXT2_2_DEFAULT 0x0 - /*[field] EXT2_3*/ - #define RULE_EXT_1_REG_EXT2_3 - #define RULE_EXT_1_REG_EXT2_3_OFFSET 3 - #define RULE_EXT_1_REG_EXT2_3_LEN 1 - #define RULE_EXT_1_REG_EXT2_3_DEFAULT 0x0 - -struct rule_ext_1_reg { - a_uint32_t ext2_0:1; - a_uint32_t ext2_1:1; - a_uint32_t ext2_2:1; - a_uint32_t ext2_3:1; - a_uint32_t _reserved0:28; -}; - -union rule_ext_1_reg_u { - a_uint32_t val; - struct rule_ext_1_reg bf; -}; - -/*[register] RULE_EXT_2_REG*/ -#define RULE_EXT_2_REG -#define RULE_EXT_2_REG_ADDRESS 0x4100 -#define RULE_EXT_2_REG_NUM 64 -#define RULE_EXT_2_REG_INC 0x4 -#define RULE_EXT_2_REG_TYPE REG_TYPE_RW -#define RULE_EXT_2_REG_DEFAULT 0x0 - /*[field] EXT4_0*/ - #define RULE_EXT_2_REG_EXT4_0 - #define RULE_EXT_2_REG_EXT4_0_OFFSET 0 - #define RULE_EXT_2_REG_EXT4_0_LEN 1 - #define RULE_EXT_2_REG_EXT4_0_DEFAULT 0x0 - /*[field] EXT4_1*/ - #define RULE_EXT_2_REG_EXT4_1 - #define RULE_EXT_2_REG_EXT4_1_OFFSET 1 - #define RULE_EXT_2_REG_EXT4_1_LEN 1 - #define RULE_EXT_2_REG_EXT4_1_DEFAULT 0x0 - -struct rule_ext_2_reg { - a_uint32_t ext4_0:1; - a_uint32_t ext4_1:1; - a_uint32_t _reserved0:30; -}; - -union rule_ext_2_reg_u { - a_uint32_t val; - struct rule_ext_2_reg bf; -}; - -/*[register] RULE_EXT_4_REG*/ -#define RULE_EXT_4_REG -#define RULE_EXT_4_REG_ADDRESS 0x4200 -#define RULE_EXT_4_REG_NUM 64 -#define RULE_EXT_4_REG_INC 0x4 -#define RULE_EXT_4_REG_TYPE REG_TYPE_RW -#define RULE_EXT_4_REG_DEFAULT 0x0 - /*[field] EXT8*/ - #define RULE_EXT_4_REG_EXT8 - #define RULE_EXT_4_REG_EXT8_OFFSET 0 - #define RULE_EXT_4_REG_EXT8_LEN 1 - #define RULE_EXT_4_REG_EXT8_DEFAULT 0x0 - -struct rule_ext_4_reg { - a_uint32_t ext8:1; - a_uint32_t _reserved0:31; -}; - -union rule_ext_4_reg_u { - a_uint32_t val; - struct rule_ext_4_reg bf; -}; - -/*[register] IPO_DBG_ADDR_REG*/ -#define IPO_DBG_ADDR_REG -#define IPO_DBG_ADDR_REG_ADDRESS 0x4300 -#define IPO_DBG_ADDR_REG_NUM 1 -#define IPO_DBG_ADDR_REG_INC 0x4 -#define IPO_DBG_ADDR_REG_TYPE REG_TYPE_RW -#define IPO_DBG_ADDR_REG_DEFAULT 0x0 - /*[field] IPO_DBG_ADDR*/ - #define IPO_DBG_ADDR_REG_IPO_DBG_ADDR - #define IPO_DBG_ADDR_REG_IPO_DBG_ADDR_OFFSET 0 - #define IPO_DBG_ADDR_REG_IPO_DBG_ADDR_LEN 32 - #define IPO_DBG_ADDR_REG_IPO_DBG_ADDR_DEFAULT 0x0 - -struct ipo_dbg_addr_reg { - a_uint32_t ipo_dbg_addr:32; -}; - -union ipo_dbg_addr_reg_u { - a_uint32_t val; - struct ipo_dbg_addr_reg bf; -}; - -/*[register] IPO_DBG_DATA_REG*/ -#define IPO_DBG_DATA_REG -#define IPO_DBG_DATA_REG_ADDRESS 0x4304 -#define IPO_DBG_DATA_REG_NUM 1 -#define IPO_DBG_DATA_REG_INC 0x4 -#define IPO_DBG_DATA_REG_TYPE REG_TYPE_RO -#define IPO_DBG_DATA_REG_DEFAULT 0x0 - /*[field] IPO_DBG_DATA*/ - #define IPO_DBG_DATA_REG_IPO_DBG_DATA - #define IPO_DBG_DATA_REG_IPO_DBG_DATA_OFFSET 0 - #define IPO_DBG_DATA_REG_IPO_DBG_DATA_LEN 32 - #define IPO_DBG_DATA_REG_IPO_DBG_DATA_DEFAULT 0x0 - -struct ipo_dbg_data_reg { - a_uint32_t ipo_dbg_data:32; -}; - -union ipo_dbg_data_reg_u { - a_uint32_t val; - struct ipo_dbg_data_reg bf; -}; - -/*[register] IPO_SPARE_REG_REG*/ -#define IPO_SPARE_REG_REG -#define IPO_SPARE_REG_REG_ADDRESS 0x4308 -#define IPO_SPARE_REG_REG_NUM 1 -#define IPO_SPARE_REG_REG_INC 0x4 -#define IPO_SPARE_REG_REG_TYPE REG_TYPE_RW -#define IPO_SPARE_REG_REG_DEFAULT 0x0 - /*[field] SPARE_REG*/ - #define IPO_SPARE_REG_REG_SPARE_REG - #define IPO_SPARE_REG_REG_SPARE_REG_OFFSET 0 - #define IPO_SPARE_REG_REG_SPARE_REG_LEN 32 - #define IPO_SPARE_REG_REG_SPARE_REG_DEFAULT 0x0 - -struct ipo_spare_reg_reg { - a_uint32_t spare_reg:32; -}; - -union ipo_spare_reg_reg_u { - a_uint32_t val; - struct ipo_spare_reg_reg bf; -}; - -/*[register] IPO_GLB_HIT_COUNTER_REG*/ -#define IPO_GLB_HIT_COUNTER_REG -#define IPO_GLB_HIT_COUNTER_REG_ADDRESS 0x430c -#define IPO_GLB_HIT_COUNTER_REG_NUM 1 -#define IPO_GLB_HIT_COUNTER_REG_INC 0x4 -#define IPO_GLB_HIT_COUNTER_REG_TYPE REG_TYPE_RO -#define IPO_GLB_HIT_COUNTER_REG_DEFAULT 0x0 - /*[field] HIT_COUNT*/ - #define IPO_GLB_HIT_COUNTER_REG_HIT_COUNT - #define IPO_GLB_HIT_COUNTER_REG_HIT_COUNT_OFFSET 0 - #define IPO_GLB_HIT_COUNTER_REG_HIT_COUNT_LEN 32 - #define IPO_GLB_HIT_COUNTER_REG_HIT_COUNT_DEFAULT 0x0 - -struct ipo_glb_hit_counter_reg { - a_uint32_t hit_count:32; -}; - -union ipo_glb_hit_counter_reg_u { - a_uint32_t val; - struct ipo_glb_hit_counter_reg bf; -}; - -/*[register] IPO_GLB_MISS_COUNTER_REG*/ -#define IPO_GLB_MISS_COUNTER_REG -#define IPO_GLB_MISS_COUNTER_REG_ADDRESS 0x4310 -#define IPO_GLB_MISS_COUNTER_REG_NUM 1 -#define IPO_GLB_MISS_COUNTER_REG_INC 0x4 -#define IPO_GLB_MISS_COUNTER_REG_TYPE REG_TYPE_RO -#define IPO_GLB_MISS_COUNTER_REG_DEFAULT 0x0 - /*[field] MISS_COUNT*/ - #define IPO_GLB_MISS_COUNTER_REG_MISS_COUNT - #define IPO_GLB_MISS_COUNTER_REG_MISS_COUNT_OFFSET 0 - #define IPO_GLB_MISS_COUNTER_REG_MISS_COUNT_LEN 32 - #define IPO_GLB_MISS_COUNTER_REG_MISS_COUNT_DEFAULT 0x0 - -struct ipo_glb_miss_counter_reg { - a_uint32_t miss_count:32; -}; - -union ipo_glb_miss_counter_reg_u { - a_uint32_t val; - struct ipo_glb_miss_counter_reg bf; -}; - -/*[register] IPO_GLB_BYPASS_COUNTER_REG*/ -#define IPO_GLB_BYPASS_COUNTER_REG -#define IPO_GLB_BYPASS_COUNTER_REG_ADDRESS 0x4314 -#define IPO_GLB_BYPASS_COUNTER_REG_NUM 1 -#define IPO_GLB_BYPASS_COUNTER_REG_INC 0x4 -#define IPO_GLB_BYPASS_COUNTER_REG_TYPE REG_TYPE_RO -#define IPO_GLB_BYPASS_COUNTER_REG_DEFAULT 0x0 - /*[field] BYPASS_COUNT*/ - #define IPO_GLB_BYPASS_COUNTER_REG_BYPASS_COUNT - #define IPO_GLB_BYPASS_COUNTER_REG_BYPASS_COUNT_OFFSET 0 - #define IPO_GLB_BYPASS_COUNTER_REG_BYPASS_COUNT_LEN 32 - #define IPO_GLB_BYPASS_COUNTER_REG_BYPASS_COUNT_DEFAULT 0x0 - -struct ipo_glb_bypass_counter_reg { - a_uint32_t bypass_count:32; -}; - -union ipo_glb_bypass_counter_reg_u { - a_uint32_t val; - struct ipo_glb_bypass_counter_reg bf; -}; - -/*[table] IPO_CNT_TBL*/ -#define IPO_CNT_TBL -#define IPO_CNT_TBL_ADDRESS 0x74000 -#define IPO_CNT_TBL_NUM 512 -#define IPO_CNT_TBL_INC 0x10 -#define IPO_CNT_TBL_TYPE REG_TYPE_RW -#define IPO_CNT_TBL_DEFAULT 0x0 - /*[field] HIT_PKT_CNT*/ - #define IPO_CNT_TBL_HIT_PKT_CNT - #define IPO_CNT_TBL_HIT_PKT_CNT_OFFSET 0 - #define IPO_CNT_TBL_HIT_PKT_CNT_LEN 32 - #define IPO_CNT_TBL_HIT_PKT_CNT_DEFAULT 0x0 - /*[field] HIT_BYTE_CNT*/ - #define IPO_CNT_TBL_HIT_BYTE_CNT - #define IPO_CNT_TBL_HIT_BYTE_CNT_OFFSET 32 - #define IPO_CNT_TBL_HIT_BYTE_CNT_LEN 40 - #define IPO_CNT_TBL_HIT_BYTE_CNT_DEFAULT 0x0 - -struct ipo_cnt_tbl { - a_uint32_t hit_pkt_cnt:32; - a_uint32_t hit_byte_cnt_0:32; - a_uint32_t hit_byte_cnt_1:8; - a_uint32_t _reserved0:24; -}; - -union ipo_cnt_tbl_u { - a_uint32_t val[3]; - struct ipo_cnt_tbl bf; -}; - -/*[table] IPO_ACTION*/ -#define IPO_ACTION -#define IPO_ACTION_ADDRESS 0x8000 -#define IPO_ACTION_NUM 512 -#define IPO_ACTION_INC 0x20 -#define IPO_ACTION_TYPE REG_TYPE_RW -#define IPO_ACTION_DEFAULT 0x0 - /*[field] DEST_INFO_CHANGE_EN*/ - #define IPO_ACTION_DEST_INFO_CHANGE_EN - #define IPO_ACTION_DEST_INFO_CHANGE_EN_OFFSET 0 - #define IPO_ACTION_DEST_INFO_CHANGE_EN_LEN 1 - #define IPO_ACTION_DEST_INFO_CHANGE_EN_DEFAULT 0x0 - /*[field] FWD_CMD*/ - #define IPO_ACTION_FWD_CMD - #define IPO_ACTION_FWD_CMD_OFFSET 1 - #define IPO_ACTION_FWD_CMD_LEN 2 - #define IPO_ACTION_FWD_CMD_DEFAULT 0x0 - /*[field] DEST_INFO*/ - #define IPO_ACTION_DEST_INFO - #define IPO_ACTION_DEST_INFO_OFFSET 3 - #define IPO_ACTION_DEST_INFO_LEN 14 - #define IPO_ACTION_DEST_INFO_DEFAULT 0x0 - /*[field] MIRROR_EN*/ - #define IPO_ACTION_MIRROR_EN - #define IPO_ACTION_MIRROR_EN_OFFSET 17 - #define IPO_ACTION_MIRROR_EN_LEN 1 - #define IPO_ACTION_MIRROR_EN_DEFAULT 0x0 - /*[field] BYPASS_BITMAP*/ - #define IPO_ACTION_BYPASS_BITMAP - #define IPO_ACTION_BYPASS_BITMAP_OFFSET 18 - #define IPO_ACTION_BYPASS_BITMAP_LEN 32 - #define IPO_ACTION_BYPASS_BITMAP_DEFAULT 0x0 - /*[field] SVID_CHANGE_EN*/ - #define IPO_ACTION_SVID_CHANGE_EN - #define IPO_ACTION_SVID_CHANGE_EN_OFFSET 50 - #define IPO_ACTION_SVID_CHANGE_EN_LEN 1 - #define IPO_ACTION_SVID_CHANGE_EN_DEFAULT 0x0 - /*[field] STAG_FMT*/ - #define IPO_ACTION_STAG_FMT - #define IPO_ACTION_STAG_FMT_OFFSET 51 - #define IPO_ACTION_STAG_FMT_LEN 1 - #define IPO_ACTION_STAG_FMT_DEFAULT 0x0 - /*[field] SVID*/ - #define IPO_ACTION_SVID - #define IPO_ACTION_SVID_OFFSET 52 - #define IPO_ACTION_SVID_LEN 12 - #define IPO_ACTION_SVID_DEFAULT 0x0 - /*[field] CVID_CHANGE_EN*/ - #define IPO_ACTION_CVID_CHANGE_EN - #define IPO_ACTION_CVID_CHANGE_EN_OFFSET 64 - #define IPO_ACTION_CVID_CHANGE_EN_LEN 1 - #define IPO_ACTION_CVID_CHANGE_EN_DEFAULT 0x0 - /*[field] CTAG_FMT*/ - #define IPO_ACTION_CTAG_FMT - #define IPO_ACTION_CTAG_FMT_OFFSET 65 - #define IPO_ACTION_CTAG_FMT_LEN 1 - #define IPO_ACTION_CTAG_FMT_DEFAULT 0x0 - /*[field] CVID*/ - #define IPO_ACTION_CVID - #define IPO_ACTION_CVID_OFFSET 66 - #define IPO_ACTION_CVID_LEN 12 - #define IPO_ACTION_CVID_DEFAULT 0x0 - /*[field] DSCP_TC_CHANGE_EN*/ - #define IPO_ACTION_DSCP_TC_CHANGE_EN - #define IPO_ACTION_DSCP_TC_CHANGE_EN_OFFSET 78 - #define IPO_ACTION_DSCP_TC_CHANGE_EN_LEN 1 - #define IPO_ACTION_DSCP_TC_CHANGE_EN_DEFAULT 0x0 - /*[field] DSCP_TC*/ - #define IPO_ACTION_DSCP_TC - #define IPO_ACTION_DSCP_TC_OFFSET 79 - #define IPO_ACTION_DSCP_TC_LEN 8 - #define IPO_ACTION_DSCP_TC_DEFAULT 0x0 - /*[field] STAG_PCP_CHANGE_EN*/ - #define IPO_ACTION_STAG_PCP_CHANGE_EN - #define IPO_ACTION_STAG_PCP_CHANGE_EN_OFFSET 87 - #define IPO_ACTION_STAG_PCP_CHANGE_EN_LEN 1 - #define IPO_ACTION_STAG_PCP_CHANGE_EN_DEFAULT 0x0 - /*[field] STAG_PCP*/ - #define IPO_ACTION_STAG_PCP - #define IPO_ACTION_STAG_PCP_OFFSET 88 - #define IPO_ACTION_STAG_PCP_LEN 3 - #define IPO_ACTION_STAG_PCP_DEFAULT 0x0 - /*[field] STAG_DEI_CHANGE_EN*/ - #define IPO_ACTION_STAG_DEI_CHANGE_EN - #define IPO_ACTION_STAG_DEI_CHANGE_EN_OFFSET 91 - #define IPO_ACTION_STAG_DEI_CHANGE_EN_LEN 1 - #define IPO_ACTION_STAG_DEI_CHANGE_EN_DEFAULT 0x0 - /*[field] STAG_DEI*/ - #define IPO_ACTION_STAG_DEI - #define IPO_ACTION_STAG_DEI_OFFSET 92 - #define IPO_ACTION_STAG_DEI_LEN 1 - #define IPO_ACTION_STAG_DEI_DEFAULT 0x0 - /*[field] CTAG_PCP_CHANGE_EN*/ - #define IPO_ACTION_CTAG_PCP_CHANGE_EN - #define IPO_ACTION_CTAG_PCP_CHANGE_EN_OFFSET 93 - #define IPO_ACTION_CTAG_PCP_CHANGE_EN_LEN 1 - #define IPO_ACTION_CTAG_PCP_CHANGE_EN_DEFAULT 0x0 - /*[field] CTAG_PCP*/ - #define IPO_ACTION_CTAG_PCP - #define IPO_ACTION_CTAG_PCP_OFFSET 94 - #define IPO_ACTION_CTAG_PCP_LEN 3 - #define IPO_ACTION_CTAG_PCP_DEFAULT 0x0 - /*[field] CTAG_DEI_CHANGE_EN*/ - #define IPO_ACTION_CTAG_DEI_CHANGE_EN - #define IPO_ACTION_CTAG_DEI_CHANGE_EN_OFFSET 97 - #define IPO_ACTION_CTAG_DEI_CHANGE_EN_LEN 1 - #define IPO_ACTION_CTAG_DEI_CHANGE_EN_DEFAULT 0x0 - /*[field] CTAG_DEI*/ - #define IPO_ACTION_CTAG_DEI - #define IPO_ACTION_CTAG_DEI_OFFSET 98 - #define IPO_ACTION_CTAG_DEI_LEN 1 - #define IPO_ACTION_CTAG_DEI_DEFAULT 0x0 - /*[field] ENQUEUE_PRI_CHANGE_EN*/ - #define IPO_ACTION_ENQUEUE_PRI_CHANGE_EN - #define IPO_ACTION_ENQUEUE_PRI_CHANGE_EN_OFFSET 99 - #define IPO_ACTION_ENQUEUE_PRI_CHANGE_EN_LEN 1 - #define IPO_ACTION_ENQUEUE_PRI_CHANGE_EN_DEFAULT 0x0 - /*[field] ENQUEUE_PRI*/ - #define IPO_ACTION_ENQUEUE_PRI - #define IPO_ACTION_ENQUEUE_PRI_OFFSET 100 - #define IPO_ACTION_ENQUEUE_PRI_LEN 4 - #define IPO_ACTION_ENQUEUE_PRI_DEFAULT 0x0 - /*[field] INT_DP_CHANGE_EN*/ - #define IPO_ACTION_INT_DP_CHANGE_EN - #define IPO_ACTION_INT_DP_CHANGE_EN_OFFSET 104 - #define IPO_ACTION_INT_DP_CHANGE_EN_LEN 1 - #define IPO_ACTION_INT_DP_CHANGE_EN_DEFAULT 0x0 - /*[field] INT_DP*/ - #define IPO_ACTION_INT_DP - #define IPO_ACTION_INT_DP_OFFSET 105 - #define IPO_ACTION_INT_DP_LEN 2 - #define IPO_ACTION_INT_DP_DEFAULT 0x0 - /*[field] POLICER_EN*/ - #define IPO_ACTION_POLICER_EN - #define IPO_ACTION_POLICER_EN_OFFSET 107 - #define IPO_ACTION_POLICER_EN_LEN 1 - #define IPO_ACTION_POLICER_EN_DEFAULT 0x0 - /*[field] POLICER_INDEX*/ - #define IPO_ACTION_POLICER_INDEX - #define IPO_ACTION_POLICER_INDEX_OFFSET 108 - #define IPO_ACTION_POLICER_INDEX_LEN 9 - #define IPO_ACTION_POLICER_INDEX_DEFAULT 0x0 - /*[field] QID_EN*/ - #define IPO_ACTION_QID_EN - #define IPO_ACTION_QID_EN_OFFSET 117 - #define IPO_ACTION_QID_EN_LEN 1 - #define IPO_ACTION_QID_EN_DEFAULT 0x0 - /*[field] QID*/ - #define IPO_ACTION_QID - #define IPO_ACTION_QID_OFFSET 118 - #define IPO_ACTION_QID_LEN 8 - #define IPO_ACTION_QID_DEFAULT 0x0 - /*[field] SERVICE_CODE_EN*/ - #define IPO_ACTION_SERVICE_CODE_EN - #define IPO_ACTION_SERVICE_CODE_EN_OFFSET 126 - #define IPO_ACTION_SERVICE_CODE_EN_LEN 1 - #define IPO_ACTION_SERVICE_CODE_EN_DEFAULT 0x0 - /*[field] SERVICE_CODE*/ - #define IPO_ACTION_SERVICE_CODE - #define IPO_ACTION_SERVICE_CODE_OFFSET 127 - #define IPO_ACTION_SERVICE_CODE_LEN 8 - #define IPO_ACTION_SERVICE_CODE_DEFAULT 0x0 - /*[field] SYN_TOGGLE*/ - #define IPO_ACTION_SYN_TOGGLE - #define IPO_ACTION_SYN_TOGGLE_OFFSET 135 - #define IPO_ACTION_SYN_TOGGLE_LEN 1 - #define IPO_ACTION_SYN_TOGGLE_DEFAULT 0x0 - /*[field] CPU_CODE_EN*/ - #define IPO_ACTION_CPU_CODE_EN - #define IPO_ACTION_CPU_CODE_EN_OFFSET 136 - #define IPO_ACTION_CPU_CODE_EN_LEN 1 - #define IPO_ACTION_CPU_CODE_EN_DEFAULT 0x0 - /*[field] CPU_CODE*/ - #define IPO_ACTION_CPU_CODE - #define IPO_ACTION_CPU_CODE_OFFSET 137 - #define IPO_ACTION_CPU_CODE_LEN 8 - #define IPO_ACTION_CPU_CODE_DEFAULT 0x0 - /*[field] METADATA_EN*/ - #define IPO_ACTION_METADATA_EN - #define IPO_ACTION_METADATA_EN_OFFSET 145 - #define IPO_ACTION_METADATA_EN_LEN 1 - #define IPO_ACTION_METADATA_EN_DEFAULT 0x0 - -struct ipo_action { - a_uint32_t dest_info_change_en:1; - a_uint32_t fwd_cmd:2; - a_uint32_t dest_info:14; - a_uint32_t mirror_en:1; - a_uint32_t bypass_bitmap_0:14; - a_uint32_t bypass_bitmap_1:18; - a_uint32_t svid_change_en:1; - a_uint32_t stag_fmt:1; - a_uint32_t svid:12; - a_uint32_t cvid_change_en:1; - a_uint32_t ctag_fmt:1; - a_uint32_t cvid:12; - a_uint32_t dscp_tc_change_en:1; - a_uint32_t dscp_tc:8; - a_uint32_t stag_pcp_change_en:1; - a_uint32_t stag_pcp:3; - a_uint32_t stag_dei_change_en:1; - a_uint32_t stag_dei:1; - a_uint32_t ctag_pcp_change_en:1; - a_uint32_t ctag_pcp_0:2; - a_uint32_t ctag_pcp_1:1; - a_uint32_t ctag_dei_change_en:1; - a_uint32_t ctag_dei:1; - a_uint32_t enqueue_pri_change_en:1; - a_uint32_t enqueue_pri:4; - a_uint32_t int_dp_change_en:1; - a_uint32_t int_dp:2; - a_uint32_t policer_en:1; - a_uint32_t policer_index:9; - a_uint32_t qid_en:1; - a_uint32_t qid:8; - a_uint32_t service_code_en:1; - a_uint32_t service_code_0:1; - a_uint32_t service_code_1:7; - a_uint32_t syn_toggle:1; - a_uint32_t cpu_code_en:1; - a_uint32_t cpu_code:8; - a_uint32_t metadata_en:1; - a_uint32_t dscp_tc_mask:8; - a_uint32_t qos_res_prec:3; - a_uint32_t _reserved0:3; -}; - -union ipo_action_u { - a_uint32_t val[5]; - struct ipo_action bf; -}; - - -#endif diff --git a/feeds/ipq807x/qca-ssdk/src/include/hsl/hppe/hppe_bm.h b/feeds/ipq807x/qca-ssdk/src/include/hsl/hppe/hppe_bm.h deleted file mode 100755 index d48f44187..000000000 --- a/feeds/ipq807x/qca-ssdk/src/include/hsl/hppe/hppe_bm.h +++ /dev/null @@ -1,1218 +0,0 @@ -/* - * Copyright (c) 2016-2017, The Linux Foundation. All rights reserved. - * Permission to use, copy, modify, and/or distribute this software for - * any purpose with or without fee is hereby granted, provided that the - * above copyright notice and this permission notice appear in all copies. - * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES - * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR - * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES - * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN - * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT - * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. - */ - - -/** - * @defgroup - * @{ - */ -#ifndef _HPPE_BM_H_ -#define _HPPE_BM_H_ - -#define DEQ_FIFO_CFG_MAX_ENTRY 9 -#define PORT_FC_MODE_MAX_ENTRY 15 -#define PORT_FC_STATUS_MAX_ENTRY 15 -#define PORT_GROUP_ID_MAX_ENTRY 15 -#define PORT_CNT_MAX_ENTRY 15 -#define PORT_REACTED_CNT_MAX_ENTRY 15 -#define SHARED_GROUP_CNT_MAX_ENTRY 4 -#define SHARED_GROUP_CFG_MAX_ENTRY 4 -#define PORT_PROFILE_TH_CFG_MAX_ENTRY 15 -#define REACT_PROFILE_TH_CFG_MAX_ENTRY 15 -#define GRP_PROFILE_TH_CFG_MAX_ENTRY 4 -#define PORT_OUT_PROFILE_CNT_MAX_ENTRY 15 -#define PORT_IN_PROFILE_CNT_MAX_ENTRY 15 -#define REACT_OUT_PROFILE_CNT_MAX_ENTRY 15 -#define REACT_IN_PROFILE_CNT_MAX_ENTRY 15 -#define GRP_OUT_PROFILE_CNT_MAX_ENTRY 4 -#define GRP_IN_PROFILE_CNT_MAX_ENTRY 4 -#define PORT_FC_CFG_MAX_ENTRY 15 -#define LLM_MAX_ENTRY 2048 -#define RCM_MAX_ENTRY 2048 -#define DM_MAX_ENTRY 8192 - - -sw_error_t -hppe_fb_fifo_cfg_get( - a_uint32_t dev_id, - union fb_fifo_cfg_u *value); - -sw_error_t -hppe_fb_fifo_cfg_set( - a_uint32_t dev_id, - union fb_fifo_cfg_u *value); - -sw_error_t -hppe_fp_fifo_cfg_get( - a_uint32_t dev_id, - union fp_fifo_cfg_u *value); - -sw_error_t -hppe_fp_fifo_cfg_set( - a_uint32_t dev_id, - union fp_fifo_cfg_u *value); - -sw_error_t -hppe_deq_fifo_cfg_get( - a_uint32_t dev_id, - a_uint32_t index, - union deq_fifo_cfg_u *value); - -sw_error_t -hppe_deq_fifo_cfg_set( - a_uint32_t dev_id, - a_uint32_t index, - union deq_fifo_cfg_u *value); - -sw_error_t -hppe_tick_dly_cfg_get( - a_uint32_t dev_id, - union tick_dly_cfg_u *value); - -sw_error_t -hppe_tick_dly_cfg_set( - a_uint32_t dev_id, - union tick_dly_cfg_u *value); - -sw_error_t -hppe_bm_rsv_0_get( - a_uint32_t dev_id, - union bm_rsv_0_u *value); - -sw_error_t -hppe_bm_rsv_0_set( - a_uint32_t dev_id, - union bm_rsv_0_u *value); - -sw_error_t -hppe_bm_rsv_1_get( - a_uint32_t dev_id, - union bm_rsv_1_u *value); - -sw_error_t -hppe_bm_rsv_1_set( - a_uint32_t dev_id, - union bm_rsv_1_u *value); - -sw_error_t -hppe_bm_dbg_addr_get( - a_uint32_t dev_id, - union bm_dbg_addr_u *value); - -sw_error_t -hppe_bm_dbg_addr_set( - a_uint32_t dev_id, - union bm_dbg_addr_u *value); - -sw_error_t -hppe_bm_dbg_data_get( - a_uint32_t dev_id, - union bm_dbg_data_u *value); - -sw_error_t -hppe_bm_dbg_data_set( - a_uint32_t dev_id, - union bm_dbg_data_u *value); - -sw_error_t -hppe_port_fc_mode_get( - a_uint32_t dev_id, - a_uint32_t index, - union port_fc_mode_u *value); - -sw_error_t -hppe_port_fc_mode_set( - a_uint32_t dev_id, - a_uint32_t index, - union port_fc_mode_u *value); - -sw_error_t -hppe_port_fc_status_get( - a_uint32_t dev_id, - a_uint32_t index, - union port_fc_status_u *value); - -sw_error_t -hppe_port_fc_status_set( - a_uint32_t dev_id, - a_uint32_t index, - union port_fc_status_u *value); - -sw_error_t -hppe_port_group_id_get( - a_uint32_t dev_id, - a_uint32_t index, - union port_group_id_u *value); - -sw_error_t -hppe_port_group_id_set( - a_uint32_t dev_id, - a_uint32_t index, - union port_group_id_u *value); - -sw_error_t -hppe_port_cnt_get( - a_uint32_t dev_id, - a_uint32_t index, - union port_cnt_u *value); - -sw_error_t -hppe_port_cnt_set( - a_uint32_t dev_id, - a_uint32_t index, - union port_cnt_u *value); - -sw_error_t -hppe_port_reacted_cnt_get( - a_uint32_t dev_id, - a_uint32_t index, - union port_reacted_cnt_u *value); - -sw_error_t -hppe_port_reacted_cnt_set( - a_uint32_t dev_id, - a_uint32_t index, - union port_reacted_cnt_u *value); - -sw_error_t -hppe_shared_group_cnt_get( - a_uint32_t dev_id, - a_uint32_t index, - union shared_group_cnt_u *value); - -sw_error_t -hppe_shared_group_cnt_set( - a_uint32_t dev_id, - a_uint32_t index, - union shared_group_cnt_u *value); - -sw_error_t -hppe_shared_group_cfg_get( - a_uint32_t dev_id, - a_uint32_t index, - union shared_group_cfg_u *value); - -sw_error_t -hppe_shared_group_cfg_set( - a_uint32_t dev_id, - a_uint32_t index, - union shared_group_cfg_u *value); - -sw_error_t -hppe_port_profile_cnt_en_get( - a_uint32_t dev_id, - union port_profile_cnt_en_u *value); - -sw_error_t -hppe_port_profile_cnt_en_set( - a_uint32_t dev_id, - union port_profile_cnt_en_u *value); - -sw_error_t -hppe_grp_profile_cnt_en_get( - a_uint32_t dev_id, - union grp_profile_cnt_en_u *value); - -sw_error_t -hppe_grp_profile_cnt_en_set( - a_uint32_t dev_id, - union grp_profile_cnt_en_u *value); - -sw_error_t -hppe_port_profile_th_cfg_get( - a_uint32_t dev_id, - a_uint32_t index, - union port_profile_th_cfg_u *value); - -sw_error_t -hppe_port_profile_th_cfg_set( - a_uint32_t dev_id, - a_uint32_t index, - union port_profile_th_cfg_u *value); - -sw_error_t -hppe_react_profile_th_cfg_get( - a_uint32_t dev_id, - a_uint32_t index, - union react_profile_th_cfg_u *value); - -sw_error_t -hppe_react_profile_th_cfg_set( - a_uint32_t dev_id, - a_uint32_t index, - union react_profile_th_cfg_u *value); - -sw_error_t -hppe_grp_profile_th_cfg_get( - a_uint32_t dev_id, - a_uint32_t index, - union grp_profile_th_cfg_u *value); - -sw_error_t -hppe_grp_profile_th_cfg_set( - a_uint32_t dev_id, - a_uint32_t index, - union grp_profile_th_cfg_u *value); - -sw_error_t -hppe_tot_react_profile_th_cfg_get( - a_uint32_t dev_id, - union tot_react_profile_th_cfg_u *value); - -sw_error_t -hppe_tot_react_profile_th_cfg_set( - a_uint32_t dev_id, - union tot_react_profile_th_cfg_u *value); - -sw_error_t -hppe_port_out_profile_cnt_get( - a_uint32_t dev_id, - a_uint32_t index, - union port_out_profile_cnt_u *value); - -sw_error_t -hppe_port_out_profile_cnt_set( - a_uint32_t dev_id, - a_uint32_t index, - union port_out_profile_cnt_u *value); - -sw_error_t -hppe_port_in_profile_cnt_get( - a_uint32_t dev_id, - a_uint32_t index, - union port_in_profile_cnt_u *value); - -sw_error_t -hppe_port_in_profile_cnt_set( - a_uint32_t dev_id, - a_uint32_t index, - union port_in_profile_cnt_u *value); - -sw_error_t -hppe_react_out_profile_cnt_get( - a_uint32_t dev_id, - a_uint32_t index, - union react_out_profile_cnt_u *value); - -sw_error_t -hppe_react_out_profile_cnt_set( - a_uint32_t dev_id, - a_uint32_t index, - union react_out_profile_cnt_u *value); - -sw_error_t -hppe_react_in_profile_cnt_get( - a_uint32_t dev_id, - a_uint32_t index, - union react_in_profile_cnt_u *value); - -sw_error_t -hppe_react_in_profile_cnt_set( - a_uint32_t dev_id, - a_uint32_t index, - union react_in_profile_cnt_u *value); - -sw_error_t -hppe_grp_out_profile_cnt_get( - a_uint32_t dev_id, - a_uint32_t index, - union grp_out_profile_cnt_u *value); - -sw_error_t -hppe_grp_out_profile_cnt_set( - a_uint32_t dev_id, - a_uint32_t index, - union grp_out_profile_cnt_u *value); - -sw_error_t -hppe_grp_in_profile_cnt_get( - a_uint32_t dev_id, - a_uint32_t index, - union grp_in_profile_cnt_u *value); - -sw_error_t -hppe_grp_in_profile_cnt_set( - a_uint32_t dev_id, - a_uint32_t index, - union grp_in_profile_cnt_u *value); - -sw_error_t -hppe_tot_react_out_profile_cnt_get( - a_uint32_t dev_id, - union tot_react_out_profile_cnt_u *value); - -sw_error_t -hppe_tot_react_out_profile_cnt_set( - a_uint32_t dev_id, - union tot_react_out_profile_cnt_u *value); - -sw_error_t -hppe_tot_react_in_profile_cnt_get( - a_uint32_t dev_id, - union tot_react_in_profile_cnt_u *value); - -sw_error_t -hppe_tot_react_in_profile_cnt_set( - a_uint32_t dev_id, - union tot_react_in_profile_cnt_u *value); - -sw_error_t -hppe_port_fc_cfg_get( - a_uint32_t dev_id, - a_uint32_t index, - union port_fc_cfg_u *value); - -sw_error_t -hppe_port_fc_cfg_set( - a_uint32_t dev_id, - a_uint32_t index, - union port_fc_cfg_u *value); - -sw_error_t -hppe_llm_get( - a_uint32_t dev_id, - a_uint32_t index, - union llm_u *value); - -sw_error_t -hppe_llm_set( - a_uint32_t dev_id, - a_uint32_t index, - union llm_u *value); - -sw_error_t -hppe_rcm_get( - a_uint32_t dev_id, - a_uint32_t index, - union rcm_u *value); - -sw_error_t -hppe_rcm_set( - a_uint32_t dev_id, - a_uint32_t index, - union rcm_u *value); - -sw_error_t -hppe_dm_get( - a_uint32_t dev_id, - a_uint32_t index, - union dm_u *value); - -sw_error_t -hppe_dm_set( - a_uint32_t dev_id, - a_uint32_t index, - union dm_u *value); - -sw_error_t -hppe_fb_fifo_cfg_fb_fifo_thres_get( - a_uint32_t dev_id, - unsigned int *value); - -sw_error_t -hppe_fb_fifo_cfg_fb_fifo_thres_set( - a_uint32_t dev_id, - unsigned int value); - -sw_error_t -hppe_fp_fifo_cfg_fp_fifo_thres_get( - a_uint32_t dev_id, - unsigned int *value); - -sw_error_t -hppe_fp_fifo_cfg_fp_fifo_thres_set( - a_uint32_t dev_id, - unsigned int value); - -sw_error_t -hppe_deq_fifo_cfg_deq_fifo_thres_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_deq_fifo_cfg_deq_fifo_thres_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_tick_dly_cfg_tick_dly_get( - a_uint32_t dev_id, - unsigned int *value); - -sw_error_t -hppe_tick_dly_cfg_tick_dly_set( - a_uint32_t dev_id, - unsigned int value); - -sw_error_t -hppe_bm_rsv_0_rsv_0_get( - a_uint32_t dev_id, - unsigned int *value); - -sw_error_t -hppe_bm_rsv_0_rsv_0_set( - a_uint32_t dev_id, - unsigned int value); - -sw_error_t -hppe_bm_rsv_1_rsv_1_get( - a_uint32_t dev_id, - unsigned int *value); - -sw_error_t -hppe_bm_rsv_1_rsv_1_set( - a_uint32_t dev_id, - unsigned int value); - -sw_error_t -hppe_bm_dbg_addr_dbg_addr_get( - a_uint32_t dev_id, - unsigned int *value); - -sw_error_t -hppe_bm_dbg_addr_dbg_addr_set( - a_uint32_t dev_id, - unsigned int value); - -sw_error_t -hppe_bm_dbg_data_dbg_data_get( - a_uint32_t dev_id, - unsigned int *value); - -sw_error_t -hppe_bm_dbg_data_dbg_data_set( - a_uint32_t dev_id, - unsigned int value); - -sw_error_t -hppe_port_fc_mode_fc_en_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_port_fc_mode_fc_en_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_port_fc_status_port_fc_status_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_port_fc_status_port_fc_status_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_port_fc_status_port_xon_th_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_port_fc_status_port_xon_th_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_port_group_id_port_shared_group_id_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_port_group_id_port_shared_group_id_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_port_cnt_port_cnt_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_port_cnt_port_cnt_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_port_reacted_cnt_port_reacted_cnt_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_port_reacted_cnt_port_reacted_cnt_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_shared_group_cnt_shared_group_cnt_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_shared_group_cnt_shared_group_cnt_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_shared_group_cfg_shared_group_limit_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_shared_group_cfg_shared_group_limit_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_port_profile_cnt_en_react_cnt_en_8_get( - a_uint32_t dev_id, - unsigned int *value); - -sw_error_t -hppe_port_profile_cnt_en_react_cnt_en_8_set( - a_uint32_t dev_id, - unsigned int value); - -sw_error_t -hppe_port_profile_cnt_en_react_cnt_en_7_get( - a_uint32_t dev_id, - unsigned int *value); - -sw_error_t -hppe_port_profile_cnt_en_react_cnt_en_7_set( - a_uint32_t dev_id, - unsigned int value); - -sw_error_t -hppe_port_profile_cnt_en_port_cnt_en_6_get( - a_uint32_t dev_id, - unsigned int *value); - -sw_error_t -hppe_port_profile_cnt_en_port_cnt_en_6_set( - a_uint32_t dev_id, - unsigned int value); - -sw_error_t -hppe_port_profile_cnt_en_react_cnt_en_2_get( - a_uint32_t dev_id, - unsigned int *value); - -sw_error_t -hppe_port_profile_cnt_en_react_cnt_en_2_set( - a_uint32_t dev_id, - unsigned int value); - -sw_error_t -hppe_port_profile_cnt_en_port_cnt_en_8_get( - a_uint32_t dev_id, - unsigned int *value); - -sw_error_t -hppe_port_profile_cnt_en_port_cnt_en_8_set( - a_uint32_t dev_id, - unsigned int value); - -sw_error_t -hppe_port_profile_cnt_en_port_cnt_en_5_get( - a_uint32_t dev_id, - unsigned int *value); - -sw_error_t -hppe_port_profile_cnt_en_port_cnt_en_5_set( - a_uint32_t dev_id, - unsigned int value); - -sw_error_t -hppe_port_profile_cnt_en_port_cnt_en_12_get( - a_uint32_t dev_id, - unsigned int *value); - -sw_error_t -hppe_port_profile_cnt_en_port_cnt_en_12_set( - a_uint32_t dev_id, - unsigned int value); - -sw_error_t -hppe_port_profile_cnt_en_react_cnt_en_4_get( - a_uint32_t dev_id, - unsigned int *value); - -sw_error_t -hppe_port_profile_cnt_en_react_cnt_en_4_set( - a_uint32_t dev_id, - unsigned int value); - -sw_error_t -hppe_port_profile_cnt_en_port_cnt_en_3_get( - a_uint32_t dev_id, - unsigned int *value); - -sw_error_t -hppe_port_profile_cnt_en_port_cnt_en_3_set( - a_uint32_t dev_id, - unsigned int value); - -sw_error_t -hppe_port_profile_cnt_en_port_cnt_en_10_get( - a_uint32_t dev_id, - unsigned int *value); - -sw_error_t -hppe_port_profile_cnt_en_port_cnt_en_10_set( - a_uint32_t dev_id, - unsigned int value); - -sw_error_t -hppe_port_profile_cnt_en_port_cnt_en_4_get( - a_uint32_t dev_id, - unsigned int *value); - -sw_error_t -hppe_port_profile_cnt_en_port_cnt_en_4_set( - a_uint32_t dev_id, - unsigned int value); - -sw_error_t -hppe_port_profile_cnt_en_react_cnt_en_5_get( - a_uint32_t dev_id, - unsigned int *value); - -sw_error_t -hppe_port_profile_cnt_en_react_cnt_en_5_set( - a_uint32_t dev_id, - unsigned int value); - -sw_error_t -hppe_port_profile_cnt_en_port_cnt_en_14_get( - a_uint32_t dev_id, - unsigned int *value); - -sw_error_t -hppe_port_profile_cnt_en_port_cnt_en_14_set( - a_uint32_t dev_id, - unsigned int value); - -sw_error_t -hppe_port_profile_cnt_en_react_cnt_en_14_get( - a_uint32_t dev_id, - unsigned int *value); - -sw_error_t -hppe_port_profile_cnt_en_react_cnt_en_14_set( - a_uint32_t dev_id, - unsigned int value); - -sw_error_t -hppe_port_profile_cnt_en_react_cnt_en_3_get( - a_uint32_t dev_id, - unsigned int *value); - -sw_error_t -hppe_port_profile_cnt_en_react_cnt_en_3_set( - a_uint32_t dev_id, - unsigned int value); - -sw_error_t -hppe_port_profile_cnt_en_port_cnt_en_1_get( - a_uint32_t dev_id, - unsigned int *value); - -sw_error_t -hppe_port_profile_cnt_en_port_cnt_en_1_set( - a_uint32_t dev_id, - unsigned int value); - -sw_error_t -hppe_port_profile_cnt_en_port_cnt_en_0_get( - a_uint32_t dev_id, - unsigned int *value); - -sw_error_t -hppe_port_profile_cnt_en_port_cnt_en_0_set( - a_uint32_t dev_id, - unsigned int value); - -sw_error_t -hppe_port_profile_cnt_en_port_cnt_en_7_get( - a_uint32_t dev_id, - unsigned int *value); - -sw_error_t -hppe_port_profile_cnt_en_port_cnt_en_7_set( - a_uint32_t dev_id, - unsigned int value); - -sw_error_t -hppe_port_profile_cnt_en_port_cnt_en_13_get( - a_uint32_t dev_id, - unsigned int *value); - -sw_error_t -hppe_port_profile_cnt_en_port_cnt_en_13_set( - a_uint32_t dev_id, - unsigned int value); - -sw_error_t -hppe_port_profile_cnt_en_react_cnt_en_6_get( - a_uint32_t dev_id, - unsigned int *value); - -sw_error_t -hppe_port_profile_cnt_en_react_cnt_en_6_set( - a_uint32_t dev_id, - unsigned int value); - -sw_error_t -hppe_port_profile_cnt_en_react_cnt_en_0_get( - a_uint32_t dev_id, - unsigned int *value); - -sw_error_t -hppe_port_profile_cnt_en_react_cnt_en_0_set( - a_uint32_t dev_id, - unsigned int value); - -sw_error_t -hppe_port_profile_cnt_en_react_cnt_en_13_get( - a_uint32_t dev_id, - unsigned int *value); - -sw_error_t -hppe_port_profile_cnt_en_react_cnt_en_13_set( - a_uint32_t dev_id, - unsigned int value); - -sw_error_t -hppe_port_profile_cnt_en_port_cnt_en_11_get( - a_uint32_t dev_id, - unsigned int *value); - -sw_error_t -hppe_port_profile_cnt_en_port_cnt_en_11_set( - a_uint32_t dev_id, - unsigned int value); - -sw_error_t -hppe_port_profile_cnt_en_react_cnt_en_1_get( - a_uint32_t dev_id, - unsigned int *value); - -sw_error_t -hppe_port_profile_cnt_en_react_cnt_en_1_set( - a_uint32_t dev_id, - unsigned int value); - -sw_error_t -hppe_port_profile_cnt_en_react_cnt_en_12_get( - a_uint32_t dev_id, - unsigned int *value); - -sw_error_t -hppe_port_profile_cnt_en_react_cnt_en_12_set( - a_uint32_t dev_id, - unsigned int value); - -sw_error_t -hppe_port_profile_cnt_en_react_cnt_en_11_get( - a_uint32_t dev_id, - unsigned int *value); - -sw_error_t -hppe_port_profile_cnt_en_react_cnt_en_11_set( - a_uint32_t dev_id, - unsigned int value); - -sw_error_t -hppe_port_profile_cnt_en_react_cnt_en_10_get( - a_uint32_t dev_id, - unsigned int *value); - -sw_error_t -hppe_port_profile_cnt_en_react_cnt_en_10_set( - a_uint32_t dev_id, - unsigned int value); - -sw_error_t -hppe_port_profile_cnt_en_port_cnt_en_9_get( - a_uint32_t dev_id, - unsigned int *value); - -sw_error_t -hppe_port_profile_cnt_en_port_cnt_en_9_set( - a_uint32_t dev_id, - unsigned int value); - -sw_error_t -hppe_port_profile_cnt_en_port_cnt_en_2_get( - a_uint32_t dev_id, - unsigned int *value); - -sw_error_t -hppe_port_profile_cnt_en_port_cnt_en_2_set( - a_uint32_t dev_id, - unsigned int value); - -sw_error_t -hppe_port_profile_cnt_en_react_cnt_en_9_get( - a_uint32_t dev_id, - unsigned int *value); - -sw_error_t -hppe_port_profile_cnt_en_react_cnt_en_9_set( - a_uint32_t dev_id, - unsigned int value); - -sw_error_t -hppe_grp_profile_cnt_en_grp_cnt_en_3_get( - a_uint32_t dev_id, - unsigned int *value); - -sw_error_t -hppe_grp_profile_cnt_en_grp_cnt_en_3_set( - a_uint32_t dev_id, - unsigned int value); - -sw_error_t -hppe_grp_profile_cnt_en_tot_rect_cnt_en_get( - a_uint32_t dev_id, - unsigned int *value); - -sw_error_t -hppe_grp_profile_cnt_en_tot_rect_cnt_en_set( - a_uint32_t dev_id, - unsigned int value); - -sw_error_t -hppe_grp_profile_cnt_en_grp_cnt_en_1_get( - a_uint32_t dev_id, - unsigned int *value); - -sw_error_t -hppe_grp_profile_cnt_en_grp_cnt_en_1_set( - a_uint32_t dev_id, - unsigned int value); - -sw_error_t -hppe_grp_profile_cnt_en_grp_cnt_en_0_get( - a_uint32_t dev_id, - unsigned int *value); - -sw_error_t -hppe_grp_profile_cnt_en_grp_cnt_en_0_set( - a_uint32_t dev_id, - unsigned int value); - -sw_error_t -hppe_grp_profile_cnt_en_grp_cnt_en_2_get( - a_uint32_t dev_id, - unsigned int *value); - -sw_error_t -hppe_grp_profile_cnt_en_grp_cnt_en_2_set( - a_uint32_t dev_id, - unsigned int value); - -sw_error_t -hppe_port_profile_th_cfg_port_profile_th_cfg_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_port_profile_th_cfg_port_profile_th_cfg_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_react_profile_th_cfg_react_profile_th_cfg_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_react_profile_th_cfg_react_profile_th_cfg_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_grp_profile_th_cfg_grp_profile_th_cfg_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_grp_profile_th_cfg_grp_profile_th_cfg_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_tot_react_profile_th_cfg_tot_react_profile_th_cfg_get( - a_uint32_t dev_id, - unsigned int *value); - -sw_error_t -hppe_tot_react_profile_th_cfg_tot_react_profile_th_cfg_set( - a_uint32_t dev_id, - unsigned int value); - -sw_error_t -hppe_port_out_profile_cnt_port_out_profile_cnt_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_port_out_profile_cnt_port_out_profile_cnt_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_port_in_profile_cnt_port_in_profile_cnt_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_port_in_profile_cnt_port_in_profile_cnt_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_react_out_profile_cnt_react_out_profile_cnt_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_react_out_profile_cnt_react_out_profile_cnt_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_react_in_profile_cnt_react_in_profile_cnt_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_react_in_profile_cnt_react_in_profile_cnt_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_grp_out_profile_cnt_grp_out_profile_cnt_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_grp_out_profile_cnt_grp_out_profile_cnt_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_grp_in_profile_cnt_grp_in_profile_cnt_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_grp_in_profile_cnt_grp_in_profile_cnt_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_tot_react_out_profile_cnt_tot_react_out_profile_cnt_get( - a_uint32_t dev_id, - unsigned int *value); - -sw_error_t -hppe_tot_react_out_profile_cnt_tot_react_out_profile_cnt_set( - a_uint32_t dev_id, - unsigned int value); - -sw_error_t -hppe_tot_react_in_profile_cnt_tot_react_in_profile_cnt_get( - a_uint32_t dev_id, - unsigned int *value); - -sw_error_t -hppe_tot_react_in_profile_cnt_tot_react_in_profile_cnt_set( - a_uint32_t dev_id, - unsigned int value); - -sw_error_t -hppe_port_fc_cfg_port_pre_alloc_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_port_fc_cfg_port_pre_alloc_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_port_fc_cfg_port_resume_offset_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_port_fc_cfg_port_resume_offset_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_port_fc_cfg_port_shared_dynamic_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_port_fc_cfg_port_shared_dynamic_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_port_fc_cfg_port_shared_weight_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_port_fc_cfg_port_shared_weight_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_port_fc_cfg_port_resume_floor_th_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_port_fc_cfg_port_resume_floor_th_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_port_fc_cfg_port_react_limit_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_port_fc_cfg_port_react_limit_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_port_fc_cfg_port_shared_ceiling_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_port_fc_cfg_port_shared_ceiling_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_llm_eop_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_llm_eop_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_llm_nxt_ptr_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_llm_nxt_ptr_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_rcm_ref_cnt_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_rcm_ref_cnt_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_dm_pkt_data_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint64_t *value); - -sw_error_t -hppe_dm_pkt_data_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint64_t value); - -#endif - - diff --git a/feeds/ipq807x/qca-ssdk/src/include/hsl/hppe/hppe_bm_reg.h b/feeds/ipq807x/qca-ssdk/src/include/hsl/hppe/hppe_bm_reg.h deleted file mode 100755 index 8b4d98f75..000000000 --- a/feeds/ipq807x/qca-ssdk/src/include/hsl/hppe/hppe_bm_reg.h +++ /dev/null @@ -1,1036 +0,0 @@ -/* - * Copyright (c) 2016-2017, The Linux Foundation. All rights reserved. - * Permission to use, copy, modify, and/or distribute this software for - * any purpose with or without fee is hereby granted, provided that the - * above copyright notice and this permission notice appear in all copies. - * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES - * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR - * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES - * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN - * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT - * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. - */ - - -/** - * @defgroup - * @{ - */ -#ifndef HPPE_BM_REG_H -#define HPPE_BM_REG_H - -/*[register] FB_FIFO_CFG*/ -#define FB_FIFO_CFG -#define FB_FIFO_CFG_ADDRESS 0x0 -#define FB_FIFO_CFG_NUM 1 -#define FB_FIFO_CFG_INC 0x4 -#define FB_FIFO_CFG_TYPE REG_TYPE_RW -#define FB_FIFO_CFG_DEFAULT 0x10 - /*[field] FB_FIFO_THRES*/ - #define FB_FIFO_CFG_FB_FIFO_THRES - #define FB_FIFO_CFG_FB_FIFO_THRES_OFFSET 0 - #define FB_FIFO_CFG_FB_FIFO_THRES_LEN 5 - #define FB_FIFO_CFG_FB_FIFO_THRES_DEFAULT 0x10 - -struct fb_fifo_cfg { - a_uint32_t fb_fifo_thres:5; - a_uint32_t _reserved0:27; -}; - -union fb_fifo_cfg_u { - a_uint32_t val; - struct fb_fifo_cfg bf; -}; - -/*[register] FP_FIFO_CFG*/ -#define FP_FIFO_CFG -#define FP_FIFO_CFG_ADDRESS 0x4 -#define FP_FIFO_CFG_NUM 1 -#define FP_FIFO_CFG_INC 0x4 -#define FP_FIFO_CFG_TYPE REG_TYPE_RW -#define FP_FIFO_CFG_DEFAULT 0x10 - /*[field] FP_FIFO_THRES*/ - #define FP_FIFO_CFG_FP_FIFO_THRES - #define FP_FIFO_CFG_FP_FIFO_THRES_OFFSET 0 - #define FP_FIFO_CFG_FP_FIFO_THRES_LEN 5 - #define FP_FIFO_CFG_FP_FIFO_THRES_DEFAULT 0x10 - -struct fp_fifo_cfg { - a_uint32_t fp_fifo_thres:5; - a_uint32_t _reserved0:27; -}; - -union fp_fifo_cfg_u { - a_uint32_t val; - struct fp_fifo_cfg bf; -}; - -/*[register] DEQ_FIFO_CFG*/ -#define DEQ_FIFO_CFG -#define DEQ_FIFO_CFG_ADDRESS 0x8 -#define DEQ_FIFO_CFG_NUM 9 -#define DEQ_FIFO_CFG_INC 0x4 -#define DEQ_FIFO_CFG_TYPE REG_TYPE_RW -#define DEQ_FIFO_CFG_DEFAULT 0x2 - /*[field] DEQ_FIFO_THRES*/ - #define DEQ_FIFO_CFG_DEQ_FIFO_THRES - #define DEQ_FIFO_CFG_DEQ_FIFO_THRES_OFFSET 0 - #define DEQ_FIFO_CFG_DEQ_FIFO_THRES_LEN 3 - #define DEQ_FIFO_CFG_DEQ_FIFO_THRES_DEFAULT 0x2 - -struct deq_fifo_cfg { - a_uint32_t deq_fifo_thres:3; - a_uint32_t _reserved0:29; -}; - -union deq_fifo_cfg_u { - a_uint32_t val; - struct deq_fifo_cfg bf; -}; - -/*[register] TICK_DLY_CFG*/ -#define TICK_DLY_CFG -#define TICK_DLY_CFG_ADDRESS 0x2c -#define TICK_DLY_CFG_NUM 1 -#define TICK_DLY_CFG_INC 0x4 -#define TICK_DLY_CFG_TYPE REG_TYPE_RW -#define TICK_DLY_CFG_DEFAULT 0x0 - /*[field] TICK_DLY*/ - #define TICK_DLY_CFG_TICK_DLY - #define TICK_DLY_CFG_TICK_DLY_OFFSET 0 - #define TICK_DLY_CFG_TICK_DLY_LEN 1 - #define TICK_DLY_CFG_TICK_DLY_DEFAULT 0x0 - -struct tick_dly_cfg { - a_uint32_t tick_dly:1; - a_uint32_t _reserved0:31; -}; - -union tick_dly_cfg_u { - a_uint32_t val; - struct tick_dly_cfg bf; -}; - -/*[register] BM_RSV_0*/ -#define BM_RSV_0 -#define BM_RSV_0_ADDRESS 0x30 -#define BM_RSV_0_NUM 1 -#define BM_RSV_0_INC 0x4 -#define BM_RSV_0_TYPE REG_TYPE_RW -#define BM_RSV_0_DEFAULT 0x0 - /*[field] RSV_0*/ - #define BM_RSV_0_RSV_0 - #define BM_RSV_0_RSV_0_OFFSET 0 - #define BM_RSV_0_RSV_0_LEN 32 - #define BM_RSV_0_RSV_0_DEFAULT 0x0 - -struct bm_rsv_0 { - a_uint32_t rsv_0:32; -}; - -union bm_rsv_0_u { - a_uint32_t val; - struct bm_rsv_0 bf; -}; - -/*[register] BM_RSV_1*/ -#define BM_RSV_1 -#define BM_RSV_1_ADDRESS 0x34 -#define BM_RSV_1_NUM 1 -#define BM_RSV_1_INC 0x4 -#define BM_RSV_1_TYPE REG_TYPE_RW -#define BM_RSV_1_DEFAULT 0x0 - /*[field] RSV_1*/ - #define BM_RSV_1_RSV_1 - #define BM_RSV_1_RSV_1_OFFSET 0 - #define BM_RSV_1_RSV_1_LEN 32 - #define BM_RSV_1_RSV_1_DEFAULT 0x0 - -struct bm_rsv_1 { - a_uint32_t rsv_1:32; -}; - -union bm_rsv_1_u { - a_uint32_t val; - struct bm_rsv_1 bf; -}; - -/*[register] BM_DBG_ADDR*/ -#define BM_DBG_ADDR -#define BM_DBG_ADDR_ADDRESS 0x80 -#define BM_DBG_ADDR_NUM 1 -#define BM_DBG_ADDR_INC 0x4 -#define BM_DBG_ADDR_TYPE REG_TYPE_RW -#define BM_DBG_ADDR_DEFAULT 0x0 - /*[field] DBG_ADDR*/ - #define BM_DBG_ADDR_DBG_ADDR - #define BM_DBG_ADDR_DBG_ADDR_OFFSET 0 - #define BM_DBG_ADDR_DBG_ADDR_LEN 8 - #define BM_DBG_ADDR_DBG_ADDR_DEFAULT 0x0 - -struct bm_dbg_addr { - a_uint32_t dbg_addr:8; - a_uint32_t _reserved0:24; -}; - -union bm_dbg_addr_u { - a_uint32_t val; - struct bm_dbg_addr bf; -}; - -/*[register] BM_DBG_DATA*/ -#define BM_DBG_DATA -#define BM_DBG_DATA_ADDRESS 0x84 -#define BM_DBG_DATA_NUM 1 -#define BM_DBG_DATA_INC 0x4 -#define BM_DBG_DATA_TYPE REG_TYPE_RO -#define BM_DBG_DATA_DEFAULT 0x0 - /*[field] DBG_DATA*/ - #define BM_DBG_DATA_DBG_DATA - #define BM_DBG_DATA_DBG_DATA_OFFSET 0 - #define BM_DBG_DATA_DBG_DATA_LEN 32 - #define BM_DBG_DATA_DBG_DATA_DEFAULT 0x0 - -struct bm_dbg_data { - a_uint32_t dbg_data:32; -}; - -union bm_dbg_data_u { - a_uint32_t val; - struct bm_dbg_data bf; -}; - -/*[register] PORT_FC_MODE*/ -#define PORT_FC_MODE -#define PORT_FC_MODE_ADDRESS 0x100 -#define PORT_FC_MODE_NUM 15 -#define PORT_FC_MODE_INC 0x4 -#define PORT_FC_MODE_TYPE REG_TYPE_RW -#define PORT_FC_MODE_DEFAULT 0x0 - /*[field] FC_EN*/ - #define PORT_FC_MODE_FC_EN - #define PORT_FC_MODE_FC_EN_OFFSET 0 - #define PORT_FC_MODE_FC_EN_LEN 1 - #define PORT_FC_MODE_FC_EN_DEFAULT 0x0 - -struct port_fc_mode { - a_uint32_t fc_en:1; - a_uint32_t _reserved0:31; -}; - -union port_fc_mode_u { - a_uint32_t val; - struct port_fc_mode bf; -}; - -/*[register] PORT_FC_STATUS*/ -#define PORT_FC_STATUS -#define PORT_FC_STATUS_ADDRESS 0x140 -#define PORT_FC_STATUS_NUM 15 -#define PORT_FC_STATUS_INC 0x4 -#define PORT_FC_STATUS_TYPE REG_TYPE_RO -#define PORT_FC_STATUS_DEFAULT 0x0 - /*[field] PORT_XON_TH*/ - #define PORT_FC_STATUS_PORT_XON_TH - #define PORT_FC_STATUS_PORT_XON_TH_OFFSET 0 - #define PORT_FC_STATUS_PORT_XON_TH_LEN 11 - #define PORT_FC_STATUS_PORT_XON_TH_DEFAULT 0x0 - /*[field] PORT_FC_STATUS*/ - #define PORT_FC_STATUS_PORT_FC_STATUS - #define PORT_FC_STATUS_PORT_FC_STATUS_OFFSET 16 - #define PORT_FC_STATUS_PORT_FC_STATUS_LEN 2 - #define PORT_FC_STATUS_PORT_FC_STATUS_DEFAULT 0x0 - -struct port_fc_status { - a_uint32_t port_xon_th:11; - a_uint32_t _reserved0:5; - a_uint32_t port_fc_status:2; - a_uint32_t _reserved1:14; -}; - -union port_fc_status_u { - a_uint32_t val; - struct port_fc_status bf; -}; - -/*[register] PORT_GROUP_ID*/ -#define PORT_GROUP_ID -#define PORT_GROUP_ID_ADDRESS 0x180 -#define PORT_GROUP_ID_NUM 15 -#define PORT_GROUP_ID_INC 0x4 -#define PORT_GROUP_ID_TYPE REG_TYPE_RW -#define PORT_GROUP_ID_DEFAULT 0x0 - /*[field] PORT_SHARED_GROUP_ID*/ - #define PORT_GROUP_ID_PORT_SHARED_GROUP_ID - #define PORT_GROUP_ID_PORT_SHARED_GROUP_ID_OFFSET 0 - #define PORT_GROUP_ID_PORT_SHARED_GROUP_ID_LEN 2 - #define PORT_GROUP_ID_PORT_SHARED_GROUP_ID_DEFAULT 0x0 - -struct port_group_id { - a_uint32_t port_shared_group_id:2; - a_uint32_t _reserved0:30; -}; - -union port_group_id_u { - a_uint32_t val; - struct port_group_id bf; -}; - -/*[register] PORT_CNT*/ -#define PORT_CNT -#define PORT_CNT_ADDRESS 0x1c0 -#define PORT_CNT_NUM 15 -#define PORT_CNT_INC 0x4 -#define PORT_CNT_TYPE REG_TYPE_RO -#define PORT_CNT_DEFAULT 0x0 - /*[field] PORT_CNT*/ - #define PORT_CNT_PORT_CNT - #define PORT_CNT_PORT_CNT_OFFSET 0 - #define PORT_CNT_PORT_CNT_LEN 11 - #define PORT_CNT_PORT_CNT_DEFAULT 0x0 - -struct port_cnt { - a_uint32_t port_cnt:11; - a_uint32_t _reserved0:21; -}; - -union port_cnt_u { - a_uint32_t val; - struct port_cnt bf; -}; - -/*[register] PORT_REACTED_CNT*/ -#define PORT_REACTED_CNT -#define PORT_REACTED_CNT_ADDRESS 0x240 -#define PORT_REACTED_CNT_NUM 15 -#define PORT_REACTED_CNT_INC 0x4 -#define PORT_REACTED_CNT_TYPE REG_TYPE_RO -#define PORT_REACTED_CNT_DEFAULT 0x0 - /*[field] PORT_REACTED_CNT*/ - #define PORT_REACTED_CNT_PORT_REACTED_CNT - #define PORT_REACTED_CNT_PORT_REACTED_CNT_OFFSET 0 - #define PORT_REACTED_CNT_PORT_REACTED_CNT_LEN 9 - #define PORT_REACTED_CNT_PORT_REACTED_CNT_DEFAULT 0x0 - -struct port_reacted_cnt { - a_uint32_t port_reacted_cnt:9; - a_uint32_t _reserved0:23; -}; - -union port_reacted_cnt_u { - a_uint32_t val; - struct port_reacted_cnt bf; -}; - -/*[register] SHARED_GROUP_CNT*/ -#define SHARED_GROUP_CNT -#define SHARED_GROUP_CNT_ADDRESS 0x280 -#define SHARED_GROUP_CNT_NUM 4 -#define SHARED_GROUP_CNT_INC 0x4 -#define SHARED_GROUP_CNT_TYPE REG_TYPE_RO -#define SHARED_GROUP_CNT_DEFAULT 0x0 - /*[field] SHARED_GROUP_CNT*/ - #define SHARED_GROUP_CNT_SHARED_GROUP_CNT - #define SHARED_GROUP_CNT_SHARED_GROUP_CNT_OFFSET 0 - #define SHARED_GROUP_CNT_SHARED_GROUP_CNT_LEN 11 - #define SHARED_GROUP_CNT_SHARED_GROUP_CNT_DEFAULT 0x0 - -struct shared_group_cnt { - a_uint32_t shared_group_cnt:11; - a_uint32_t _reserved0:21; -}; - -union shared_group_cnt_u { - a_uint32_t val; - struct shared_group_cnt bf; -}; - -/*[register] SHARED_GROUP_CFG*/ -#define SHARED_GROUP_CFG -#define SHARED_GROUP_CFG_ADDRESS 0x290 -#define SHARED_GROUP_CFG_NUM 4 -#define SHARED_GROUP_CFG_INC 0x4 -#define SHARED_GROUP_CFG_TYPE REG_TYPE_RW -#define SHARED_GROUP_CFG_DEFAULT 0x0 - /*[field] SHARED_GROUP_LIMIT*/ - #define SHARED_GROUP_CFG_SHARED_GROUP_LIMIT - #define SHARED_GROUP_CFG_SHARED_GROUP_LIMIT_OFFSET 0 - #define SHARED_GROUP_CFG_SHARED_GROUP_LIMIT_LEN 11 - #define SHARED_GROUP_CFG_SHARED_GROUP_LIMIT_DEFAULT 0x0 - -struct shared_group_cfg { - a_uint32_t shared_group_limit:11; - a_uint32_t _reserved0:21; -}; - -union shared_group_cfg_u { - a_uint32_t val; - struct shared_group_cfg bf; -}; - -/*[register] PORT_PROFILE_CNT_EN*/ -#define PORT_PROFILE_CNT_EN -#define PORT_PROFILE_CNT_EN_ADDRESS 0x300 -#define PORT_PROFILE_CNT_EN_NUM 1 -#define PORT_PROFILE_CNT_EN_INC 0x4 -#define PORT_PROFILE_CNT_EN_TYPE REG_TYPE_RW -#define PORT_PROFILE_CNT_EN_DEFAULT 0x0 - /*[field] PORT_CNT_EN_0*/ - #define PORT_PROFILE_CNT_EN_PORT_CNT_EN_0 - #define PORT_PROFILE_CNT_EN_PORT_CNT_EN_0_OFFSET 0 - #define PORT_PROFILE_CNT_EN_PORT_CNT_EN_0_LEN 1 - #define PORT_PROFILE_CNT_EN_PORT_CNT_EN_0_DEFAULT 0x0 - /*[field] PORT_CNT_EN_1*/ - #define PORT_PROFILE_CNT_EN_PORT_CNT_EN_1 - #define PORT_PROFILE_CNT_EN_PORT_CNT_EN_1_OFFSET 1 - #define PORT_PROFILE_CNT_EN_PORT_CNT_EN_1_LEN 1 - #define PORT_PROFILE_CNT_EN_PORT_CNT_EN_1_DEFAULT 0x0 - /*[field] PORT_CNT_EN_2*/ - #define PORT_PROFILE_CNT_EN_PORT_CNT_EN_2 - #define PORT_PROFILE_CNT_EN_PORT_CNT_EN_2_OFFSET 2 - #define PORT_PROFILE_CNT_EN_PORT_CNT_EN_2_LEN 1 - #define PORT_PROFILE_CNT_EN_PORT_CNT_EN_2_DEFAULT 0x0 - /*[field] PORT_CNT_EN_3*/ - #define PORT_PROFILE_CNT_EN_PORT_CNT_EN_3 - #define PORT_PROFILE_CNT_EN_PORT_CNT_EN_3_OFFSET 3 - #define PORT_PROFILE_CNT_EN_PORT_CNT_EN_3_LEN 1 - #define PORT_PROFILE_CNT_EN_PORT_CNT_EN_3_DEFAULT 0x0 - /*[field] PORT_CNT_EN_4*/ - #define PORT_PROFILE_CNT_EN_PORT_CNT_EN_4 - #define PORT_PROFILE_CNT_EN_PORT_CNT_EN_4_OFFSET 4 - #define PORT_PROFILE_CNT_EN_PORT_CNT_EN_4_LEN 1 - #define PORT_PROFILE_CNT_EN_PORT_CNT_EN_4_DEFAULT 0x0 - /*[field] PORT_CNT_EN_5*/ - #define PORT_PROFILE_CNT_EN_PORT_CNT_EN_5 - #define PORT_PROFILE_CNT_EN_PORT_CNT_EN_5_OFFSET 5 - #define PORT_PROFILE_CNT_EN_PORT_CNT_EN_5_LEN 1 - #define PORT_PROFILE_CNT_EN_PORT_CNT_EN_5_DEFAULT 0x0 - /*[field] PORT_CNT_EN_6*/ - #define PORT_PROFILE_CNT_EN_PORT_CNT_EN_6 - #define PORT_PROFILE_CNT_EN_PORT_CNT_EN_6_OFFSET 6 - #define PORT_PROFILE_CNT_EN_PORT_CNT_EN_6_LEN 1 - #define PORT_PROFILE_CNT_EN_PORT_CNT_EN_6_DEFAULT 0x0 - /*[field] PORT_CNT_EN_7*/ - #define PORT_PROFILE_CNT_EN_PORT_CNT_EN_7 - #define PORT_PROFILE_CNT_EN_PORT_CNT_EN_7_OFFSET 7 - #define PORT_PROFILE_CNT_EN_PORT_CNT_EN_7_LEN 1 - #define PORT_PROFILE_CNT_EN_PORT_CNT_EN_7_DEFAULT 0x0 - /*[field] PORT_CNT_EN_8*/ - #define PORT_PROFILE_CNT_EN_PORT_CNT_EN_8 - #define PORT_PROFILE_CNT_EN_PORT_CNT_EN_8_OFFSET 8 - #define PORT_PROFILE_CNT_EN_PORT_CNT_EN_8_LEN 1 - #define PORT_PROFILE_CNT_EN_PORT_CNT_EN_8_DEFAULT 0x0 - /*[field] PORT_CNT_EN_9*/ - #define PORT_PROFILE_CNT_EN_PORT_CNT_EN_9 - #define PORT_PROFILE_CNT_EN_PORT_CNT_EN_9_OFFSET 9 - #define PORT_PROFILE_CNT_EN_PORT_CNT_EN_9_LEN 1 - #define PORT_PROFILE_CNT_EN_PORT_CNT_EN_9_DEFAULT 0x0 - /*[field] PORT_CNT_EN_10*/ - #define PORT_PROFILE_CNT_EN_PORT_CNT_EN_10 - #define PORT_PROFILE_CNT_EN_PORT_CNT_EN_10_OFFSET 10 - #define PORT_PROFILE_CNT_EN_PORT_CNT_EN_10_LEN 1 - #define PORT_PROFILE_CNT_EN_PORT_CNT_EN_10_DEFAULT 0x0 - /*[field] PORT_CNT_EN_11*/ - #define PORT_PROFILE_CNT_EN_PORT_CNT_EN_11 - #define PORT_PROFILE_CNT_EN_PORT_CNT_EN_11_OFFSET 11 - #define PORT_PROFILE_CNT_EN_PORT_CNT_EN_11_LEN 1 - #define PORT_PROFILE_CNT_EN_PORT_CNT_EN_11_DEFAULT 0x0 - /*[field] PORT_CNT_EN_12*/ - #define PORT_PROFILE_CNT_EN_PORT_CNT_EN_12 - #define PORT_PROFILE_CNT_EN_PORT_CNT_EN_12_OFFSET 12 - #define PORT_PROFILE_CNT_EN_PORT_CNT_EN_12_LEN 1 - #define PORT_PROFILE_CNT_EN_PORT_CNT_EN_12_DEFAULT 0x0 - /*[field] PORT_CNT_EN_13*/ - #define PORT_PROFILE_CNT_EN_PORT_CNT_EN_13 - #define PORT_PROFILE_CNT_EN_PORT_CNT_EN_13_OFFSET 13 - #define PORT_PROFILE_CNT_EN_PORT_CNT_EN_13_LEN 1 - #define PORT_PROFILE_CNT_EN_PORT_CNT_EN_13_DEFAULT 0x0 - /*[field] PORT_CNT_EN_14*/ - #define PORT_PROFILE_CNT_EN_PORT_CNT_EN_14 - #define PORT_PROFILE_CNT_EN_PORT_CNT_EN_14_OFFSET 14 - #define PORT_PROFILE_CNT_EN_PORT_CNT_EN_14_LEN 1 - #define PORT_PROFILE_CNT_EN_PORT_CNT_EN_14_DEFAULT 0x0 - /*[field] REACT_CNT_EN_0*/ - #define PORT_PROFILE_CNT_EN_REACT_CNT_EN_0 - #define PORT_PROFILE_CNT_EN_REACT_CNT_EN_0_OFFSET 16 - #define PORT_PROFILE_CNT_EN_REACT_CNT_EN_0_LEN 1 - #define PORT_PROFILE_CNT_EN_REACT_CNT_EN_0_DEFAULT 0x0 - /*[field] REACT_CNT_EN_1*/ - #define PORT_PROFILE_CNT_EN_REACT_CNT_EN_1 - #define PORT_PROFILE_CNT_EN_REACT_CNT_EN_1_OFFSET 17 - #define PORT_PROFILE_CNT_EN_REACT_CNT_EN_1_LEN 1 - #define PORT_PROFILE_CNT_EN_REACT_CNT_EN_1_DEFAULT 0x0 - /*[field] REACT_CNT_EN_2*/ - #define PORT_PROFILE_CNT_EN_REACT_CNT_EN_2 - #define PORT_PROFILE_CNT_EN_REACT_CNT_EN_2_OFFSET 18 - #define PORT_PROFILE_CNT_EN_REACT_CNT_EN_2_LEN 1 - #define PORT_PROFILE_CNT_EN_REACT_CNT_EN_2_DEFAULT 0x0 - /*[field] REACT_CNT_EN_3*/ - #define PORT_PROFILE_CNT_EN_REACT_CNT_EN_3 - #define PORT_PROFILE_CNT_EN_REACT_CNT_EN_3_OFFSET 19 - #define PORT_PROFILE_CNT_EN_REACT_CNT_EN_3_LEN 1 - #define PORT_PROFILE_CNT_EN_REACT_CNT_EN_3_DEFAULT 0x0 - /*[field] REACT_CNT_EN_4*/ - #define PORT_PROFILE_CNT_EN_REACT_CNT_EN_4 - #define PORT_PROFILE_CNT_EN_REACT_CNT_EN_4_OFFSET 20 - #define PORT_PROFILE_CNT_EN_REACT_CNT_EN_4_LEN 1 - #define PORT_PROFILE_CNT_EN_REACT_CNT_EN_4_DEFAULT 0x0 - /*[field] REACT_CNT_EN_5*/ - #define PORT_PROFILE_CNT_EN_REACT_CNT_EN_5 - #define PORT_PROFILE_CNT_EN_REACT_CNT_EN_5_OFFSET 21 - #define PORT_PROFILE_CNT_EN_REACT_CNT_EN_5_LEN 1 - #define PORT_PROFILE_CNT_EN_REACT_CNT_EN_5_DEFAULT 0x0 - /*[field] REACT_CNT_EN_6*/ - #define PORT_PROFILE_CNT_EN_REACT_CNT_EN_6 - #define PORT_PROFILE_CNT_EN_REACT_CNT_EN_6_OFFSET 22 - #define PORT_PROFILE_CNT_EN_REACT_CNT_EN_6_LEN 1 - #define PORT_PROFILE_CNT_EN_REACT_CNT_EN_6_DEFAULT 0x0 - /*[field] REACT_CNT_EN_7*/ - #define PORT_PROFILE_CNT_EN_REACT_CNT_EN_7 - #define PORT_PROFILE_CNT_EN_REACT_CNT_EN_7_OFFSET 23 - #define PORT_PROFILE_CNT_EN_REACT_CNT_EN_7_LEN 1 - #define PORT_PROFILE_CNT_EN_REACT_CNT_EN_7_DEFAULT 0x0 - /*[field] REACT_CNT_EN_8*/ - #define PORT_PROFILE_CNT_EN_REACT_CNT_EN_8 - #define PORT_PROFILE_CNT_EN_REACT_CNT_EN_8_OFFSET 24 - #define PORT_PROFILE_CNT_EN_REACT_CNT_EN_8_LEN 1 - #define PORT_PROFILE_CNT_EN_REACT_CNT_EN_8_DEFAULT 0x0 - /*[field] REACT_CNT_EN_9*/ - #define PORT_PROFILE_CNT_EN_REACT_CNT_EN_9 - #define PORT_PROFILE_CNT_EN_REACT_CNT_EN_9_OFFSET 25 - #define PORT_PROFILE_CNT_EN_REACT_CNT_EN_9_LEN 1 - #define PORT_PROFILE_CNT_EN_REACT_CNT_EN_9_DEFAULT 0x0 - /*[field] REACT_CNT_EN_10*/ - #define PORT_PROFILE_CNT_EN_REACT_CNT_EN_10 - #define PORT_PROFILE_CNT_EN_REACT_CNT_EN_10_OFFSET 26 - #define PORT_PROFILE_CNT_EN_REACT_CNT_EN_10_LEN 1 - #define PORT_PROFILE_CNT_EN_REACT_CNT_EN_10_DEFAULT 0x0 - /*[field] REACT_CNT_EN_11*/ - #define PORT_PROFILE_CNT_EN_REACT_CNT_EN_11 - #define PORT_PROFILE_CNT_EN_REACT_CNT_EN_11_OFFSET 27 - #define PORT_PROFILE_CNT_EN_REACT_CNT_EN_11_LEN 1 - #define PORT_PROFILE_CNT_EN_REACT_CNT_EN_11_DEFAULT 0x0 - /*[field] REACT_CNT_EN_12*/ - #define PORT_PROFILE_CNT_EN_REACT_CNT_EN_12 - #define PORT_PROFILE_CNT_EN_REACT_CNT_EN_12_OFFSET 28 - #define PORT_PROFILE_CNT_EN_REACT_CNT_EN_12_LEN 1 - #define PORT_PROFILE_CNT_EN_REACT_CNT_EN_12_DEFAULT 0x0 - /*[field] REACT_CNT_EN_13*/ - #define PORT_PROFILE_CNT_EN_REACT_CNT_EN_13 - #define PORT_PROFILE_CNT_EN_REACT_CNT_EN_13_OFFSET 29 - #define PORT_PROFILE_CNT_EN_REACT_CNT_EN_13_LEN 1 - #define PORT_PROFILE_CNT_EN_REACT_CNT_EN_13_DEFAULT 0x0 - /*[field] REACT_CNT_EN_14*/ - #define PORT_PROFILE_CNT_EN_REACT_CNT_EN_14 - #define PORT_PROFILE_CNT_EN_REACT_CNT_EN_14_OFFSET 30 - #define PORT_PROFILE_CNT_EN_REACT_CNT_EN_14_LEN 1 - #define PORT_PROFILE_CNT_EN_REACT_CNT_EN_14_DEFAULT 0x0 - -struct port_profile_cnt_en { - a_uint32_t port_cnt_en_0:1; - a_uint32_t port_cnt_en_1:1; - a_uint32_t port_cnt_en_2:1; - a_uint32_t port_cnt_en_3:1; - a_uint32_t port_cnt_en_4:1; - a_uint32_t port_cnt_en_5:1; - a_uint32_t port_cnt_en_6:1; - a_uint32_t port_cnt_en_7:1; - a_uint32_t port_cnt_en_8:1; - a_uint32_t port_cnt_en_9:1; - a_uint32_t port_cnt_en_10:1; - a_uint32_t port_cnt_en_11:1; - a_uint32_t port_cnt_en_12:1; - a_uint32_t port_cnt_en_13:1; - a_uint32_t port_cnt_en_14:1; - a_uint32_t _reserved0:1; - a_uint32_t react_cnt_en_0:1; - a_uint32_t react_cnt_en_1:1; - a_uint32_t react_cnt_en_2:1; - a_uint32_t react_cnt_en_3:1; - a_uint32_t react_cnt_en_4:1; - a_uint32_t react_cnt_en_5:1; - a_uint32_t react_cnt_en_6:1; - a_uint32_t react_cnt_en_7:1; - a_uint32_t react_cnt_en_8:1; - a_uint32_t react_cnt_en_9:1; - a_uint32_t react_cnt_en_10:1; - a_uint32_t react_cnt_en_11:1; - a_uint32_t react_cnt_en_12:1; - a_uint32_t react_cnt_en_13:1; - a_uint32_t react_cnt_en_14:1; - a_uint32_t _reserved1:1; -}; - -union port_profile_cnt_en_u { - a_uint32_t val; - struct port_profile_cnt_en bf; -}; - -/*[register] GRP_PROFILE_CNT_EN*/ -#define GRP_PROFILE_CNT_EN -#define GRP_PROFILE_CNT_EN_ADDRESS 0x304 -#define GRP_PROFILE_CNT_EN_NUM 1 -#define GRP_PROFILE_CNT_EN_INC 0x4 -#define GRP_PROFILE_CNT_EN_TYPE REG_TYPE_RW -#define GRP_PROFILE_CNT_EN_DEFAULT 0x0 - /*[field] GRP_CNT_EN_0*/ - #define GRP_PROFILE_CNT_EN_GRP_CNT_EN_0 - #define GRP_PROFILE_CNT_EN_GRP_CNT_EN_0_OFFSET 0 - #define GRP_PROFILE_CNT_EN_GRP_CNT_EN_0_LEN 1 - #define GRP_PROFILE_CNT_EN_GRP_CNT_EN_0_DEFAULT 0x0 - /*[field] GRP_CNT_EN_1*/ - #define GRP_PROFILE_CNT_EN_GRP_CNT_EN_1 - #define GRP_PROFILE_CNT_EN_GRP_CNT_EN_1_OFFSET 1 - #define GRP_PROFILE_CNT_EN_GRP_CNT_EN_1_LEN 1 - #define GRP_PROFILE_CNT_EN_GRP_CNT_EN_1_DEFAULT 0x0 - /*[field] GRP_CNT_EN_2*/ - #define GRP_PROFILE_CNT_EN_GRP_CNT_EN_2 - #define GRP_PROFILE_CNT_EN_GRP_CNT_EN_2_OFFSET 2 - #define GRP_PROFILE_CNT_EN_GRP_CNT_EN_2_LEN 1 - #define GRP_PROFILE_CNT_EN_GRP_CNT_EN_2_DEFAULT 0x0 - /*[field] GRP_CNT_EN_3*/ - #define GRP_PROFILE_CNT_EN_GRP_CNT_EN_3 - #define GRP_PROFILE_CNT_EN_GRP_CNT_EN_3_OFFSET 3 - #define GRP_PROFILE_CNT_EN_GRP_CNT_EN_3_LEN 1 - #define GRP_PROFILE_CNT_EN_GRP_CNT_EN_3_DEFAULT 0x0 - /*[field] TOT_RECT_CNT_EN*/ - #define GRP_PROFILE_CNT_EN_TOT_RECT_CNT_EN - #define GRP_PROFILE_CNT_EN_TOT_RECT_CNT_EN_OFFSET 4 - #define GRP_PROFILE_CNT_EN_TOT_RECT_CNT_EN_LEN 1 - #define GRP_PROFILE_CNT_EN_TOT_RECT_CNT_EN_DEFAULT 0x0 - -struct grp_profile_cnt_en { - a_uint32_t grp_cnt_en_0:1; - a_uint32_t grp_cnt_en_1:1; - a_uint32_t grp_cnt_en_2:1; - a_uint32_t grp_cnt_en_3:1; - a_uint32_t tot_rect_cnt_en:1; - a_uint32_t _reserved0:27; -}; - -union grp_profile_cnt_en_u { - a_uint32_t val; - struct grp_profile_cnt_en bf; -}; - -/*[register] PORT_PROFILE_TH_CFG*/ -#define PORT_PROFILE_TH_CFG -#define PORT_PROFILE_TH_CFG_ADDRESS 0x308 -#define PORT_PROFILE_TH_CFG_NUM 15 -#define PORT_PROFILE_TH_CFG_INC 0x4 -#define PORT_PROFILE_TH_CFG_TYPE REG_TYPE_RW -#define PORT_PROFILE_TH_CFG_DEFAULT 0x0 - /*[field] PORT_PROFILE_TH_CFG*/ - #define PORT_PROFILE_TH_CFG_PORT_PROFILE_TH_CFG - #define PORT_PROFILE_TH_CFG_PORT_PROFILE_TH_CFG_OFFSET 0 - #define PORT_PROFILE_TH_CFG_PORT_PROFILE_TH_CFG_LEN 11 - #define PORT_PROFILE_TH_CFG_PORT_PROFILE_TH_CFG_DEFAULT 0x0 - -struct port_profile_th_cfg { - a_uint32_t port_profile_th_cfg:11; - a_uint32_t _reserved0:21; -}; - -union port_profile_th_cfg_u { - a_uint32_t val; - struct port_profile_th_cfg bf; -}; - -/*[register] REACT_PROFILE_TH_CFG*/ -#define REACT_PROFILE_TH_CFG -#define REACT_PROFILE_TH_CFG_ADDRESS 0x348 -#define REACT_PROFILE_TH_CFG_NUM 15 -#define REACT_PROFILE_TH_CFG_INC 0x4 -#define REACT_PROFILE_TH_CFG_TYPE REG_TYPE_RW -#define REACT_PROFILE_TH_CFG_DEFAULT 0x0 - /*[field] REACT_PROFILE_TH_CFG*/ - #define REACT_PROFILE_TH_CFG_REACT_PROFILE_TH_CFG - #define REACT_PROFILE_TH_CFG_REACT_PROFILE_TH_CFG_OFFSET 0 - #define REACT_PROFILE_TH_CFG_REACT_PROFILE_TH_CFG_LEN 9 - #define REACT_PROFILE_TH_CFG_REACT_PROFILE_TH_CFG_DEFAULT 0x0 - -struct react_profile_th_cfg { - a_uint32_t react_profile_th_cfg:9; - a_uint32_t _reserved0:23; -}; - -union react_profile_th_cfg_u { - a_uint32_t val; - struct react_profile_th_cfg bf; -}; - -/*[register] GRP_PROFILE_TH_CFG*/ -#define GRP_PROFILE_TH_CFG -#define GRP_PROFILE_TH_CFG_ADDRESS 0x388 -#define GRP_PROFILE_TH_CFG_NUM 4 -#define GRP_PROFILE_TH_CFG_INC 0x4 -#define GRP_PROFILE_TH_CFG_TYPE REG_TYPE_RW -#define GRP_PROFILE_TH_CFG_DEFAULT 0x0 - /*[field] GRP_PROFILE_TH_CFG*/ - #define GRP_PROFILE_TH_CFG_GRP_PROFILE_TH_CFG - #define GRP_PROFILE_TH_CFG_GRP_PROFILE_TH_CFG_OFFSET 0 - #define GRP_PROFILE_TH_CFG_GRP_PROFILE_TH_CFG_LEN 11 - #define GRP_PROFILE_TH_CFG_GRP_PROFILE_TH_CFG_DEFAULT 0x0 - -struct grp_profile_th_cfg { - a_uint32_t grp_profile_th_cfg:11; - a_uint32_t _reserved0:21; -}; - -union grp_profile_th_cfg_u { - a_uint32_t val; - struct grp_profile_th_cfg bf; -}; - -/*[register] TOT_REACT_PROFILE_TH_CFG*/ -#define TOT_REACT_PROFILE_TH_CFG -#define TOT_REACT_PROFILE_TH_CFG_ADDRESS 0x398 -#define TOT_REACT_PROFILE_TH_CFG_NUM 1 -#define TOT_REACT_PROFILE_TH_CFG_INC 0x4 -#define TOT_REACT_PROFILE_TH_CFG_TYPE REG_TYPE_RW -#define TOT_REACT_PROFILE_TH_CFG_DEFAULT 0x0 - /*[field] TOT_REACT_PROFILE_TH_CFG*/ - #define TOT_REACT_PROFILE_TH_CFG_TOT_REACT_PROFILE_TH_CFG - #define TOT_REACT_PROFILE_TH_CFG_TOT_REACT_PROFILE_TH_CFG_OFFSET 0 - #define TOT_REACT_PROFILE_TH_CFG_TOT_REACT_PROFILE_TH_CFG_LEN 11 - #define TOT_REACT_PROFILE_TH_CFG_TOT_REACT_PROFILE_TH_CFG_DEFAULT 0x0 - -struct tot_react_profile_th_cfg { - a_uint32_t tot_react_profile_th_cfg:11; - a_uint32_t _reserved0:21; -}; - -union tot_react_profile_th_cfg_u { - a_uint32_t val; - struct tot_react_profile_th_cfg bf; -}; - -/*[register] PORT_OUT_PROFILE_CNT*/ -#define PORT_OUT_PROFILE_CNT -#define PORT_OUT_PROFILE_CNT_ADDRESS 0x3a0 -#define PORT_OUT_PROFILE_CNT_NUM 15 -#define PORT_OUT_PROFILE_CNT_INC 0x4 -#define PORT_OUT_PROFILE_CNT_TYPE REG_TYPE_RW -#define PORT_OUT_PROFILE_CNT_DEFAULT 0x0 - /*[field] PORT_OUT_PROFILE_CNT*/ - #define PORT_OUT_PROFILE_CNT_PORT_OUT_PROFILE_CNT - #define PORT_OUT_PROFILE_CNT_PORT_OUT_PROFILE_CNT_OFFSET 0 - #define PORT_OUT_PROFILE_CNT_PORT_OUT_PROFILE_CNT_LEN 32 - #define PORT_OUT_PROFILE_CNT_PORT_OUT_PROFILE_CNT_DEFAULT 0x0 - -struct port_out_profile_cnt { - a_uint32_t port_out_profile_cnt:32; -}; - -union port_out_profile_cnt_u { - a_uint32_t val; - struct port_out_profile_cnt bf; -}; - -/*[register] PORT_IN_PROFILE_CNT*/ -#define PORT_IN_PROFILE_CNT -#define PORT_IN_PROFILE_CNT_ADDRESS 0x3e0 -#define PORT_IN_PROFILE_CNT_NUM 15 -#define PORT_IN_PROFILE_CNT_INC 0x4 -#define PORT_IN_PROFILE_CNT_TYPE REG_TYPE_RW -#define PORT_IN_PROFILE_CNT_DEFAULT 0x0 - /*[field] PORT_IN_PROFILE_CNT*/ - #define PORT_IN_PROFILE_CNT_PORT_IN_PROFILE_CNT - #define PORT_IN_PROFILE_CNT_PORT_IN_PROFILE_CNT_OFFSET 0 - #define PORT_IN_PROFILE_CNT_PORT_IN_PROFILE_CNT_LEN 32 - #define PORT_IN_PROFILE_CNT_PORT_IN_PROFILE_CNT_DEFAULT 0x0 - -struct port_in_profile_cnt { - a_uint32_t port_in_profile_cnt:32; -}; - -union port_in_profile_cnt_u { - a_uint32_t val; - struct port_in_profile_cnt bf; -}; - -/*[register] REACT_OUT_PROFILE_CNT*/ -#define REACT_OUT_PROFILE_CNT -#define REACT_OUT_PROFILE_CNT_ADDRESS 0x420 -#define REACT_OUT_PROFILE_CNT_NUM 15 -#define REACT_OUT_PROFILE_CNT_INC 0x4 -#define REACT_OUT_PROFILE_CNT_TYPE REG_TYPE_RW -#define REACT_OUT_PROFILE_CNT_DEFAULT 0x0 - /*[field] REACT_OUT_PROFILE_CNT*/ - #define REACT_OUT_PROFILE_CNT_REACT_OUT_PROFILE_CNT - #define REACT_OUT_PROFILE_CNT_REACT_OUT_PROFILE_CNT_OFFSET 0 - #define REACT_OUT_PROFILE_CNT_REACT_OUT_PROFILE_CNT_LEN 32 - #define REACT_OUT_PROFILE_CNT_REACT_OUT_PROFILE_CNT_DEFAULT 0x0 - -struct react_out_profile_cnt { - a_uint32_t react_out_profile_cnt:32; -}; - -union react_out_profile_cnt_u { - a_uint32_t val; - struct react_out_profile_cnt bf; -}; - -/*[register] REACT_IN_PROFILE_CNT*/ -#define REACT_IN_PROFILE_CNT -#define REACT_IN_PROFILE_CNT_ADDRESS 0x460 -#define REACT_IN_PROFILE_CNT_NUM 15 -#define REACT_IN_PROFILE_CNT_INC 0x4 -#define REACT_IN_PROFILE_CNT_TYPE REG_TYPE_RW -#define REACT_IN_PROFILE_CNT_DEFAULT 0x0 - /*[field] REACT_IN_PROFILE_CNT*/ - #define REACT_IN_PROFILE_CNT_REACT_IN_PROFILE_CNT - #define REACT_IN_PROFILE_CNT_REACT_IN_PROFILE_CNT_OFFSET 0 - #define REACT_IN_PROFILE_CNT_REACT_IN_PROFILE_CNT_LEN 32 - #define REACT_IN_PROFILE_CNT_REACT_IN_PROFILE_CNT_DEFAULT 0x0 - -struct react_in_profile_cnt { - a_uint32_t react_in_profile_cnt:32; -}; - -union react_in_profile_cnt_u { - a_uint32_t val; - struct react_in_profile_cnt bf; -}; - -/*[register] GRP_OUT_PROFILE_CNT*/ -#define GRP_OUT_PROFILE_CNT -#define GRP_OUT_PROFILE_CNT_ADDRESS 0x4a0 -#define GRP_OUT_PROFILE_CNT_NUM 4 -#define GRP_OUT_PROFILE_CNT_INC 0x4 -#define GRP_OUT_PROFILE_CNT_TYPE REG_TYPE_RW -#define GRP_OUT_PROFILE_CNT_DEFAULT 0x0 - /*[field] GRP_OUT_PROFILE_CNT*/ - #define GRP_OUT_PROFILE_CNT_GRP_OUT_PROFILE_CNT - #define GRP_OUT_PROFILE_CNT_GRP_OUT_PROFILE_CNT_OFFSET 0 - #define GRP_OUT_PROFILE_CNT_GRP_OUT_PROFILE_CNT_LEN 32 - #define GRP_OUT_PROFILE_CNT_GRP_OUT_PROFILE_CNT_DEFAULT 0x0 - -struct grp_out_profile_cnt { - a_uint32_t grp_out_profile_cnt:32; -}; - -union grp_out_profile_cnt_u { - a_uint32_t val; - struct grp_out_profile_cnt bf; -}; - -/*[register] GRP_IN_PROFILE_CNT*/ -#define GRP_IN_PROFILE_CNT -#define GRP_IN_PROFILE_CNT_ADDRESS 0x4b0 -#define GRP_IN_PROFILE_CNT_NUM 4 -#define GRP_IN_PROFILE_CNT_INC 0x4 -#define GRP_IN_PROFILE_CNT_TYPE REG_TYPE_RW -#define GRP_IN_PROFILE_CNT_DEFAULT 0x0 - /*[field] GRP_IN_PROFILE_CNT*/ - #define GRP_IN_PROFILE_CNT_GRP_IN_PROFILE_CNT - #define GRP_IN_PROFILE_CNT_GRP_IN_PROFILE_CNT_OFFSET 0 - #define GRP_IN_PROFILE_CNT_GRP_IN_PROFILE_CNT_LEN 32 - #define GRP_IN_PROFILE_CNT_GRP_IN_PROFILE_CNT_DEFAULT 0x0 - -struct grp_in_profile_cnt { - a_uint32_t grp_in_profile_cnt:32; -}; - -union grp_in_profile_cnt_u { - a_uint32_t val; - struct grp_in_profile_cnt bf; -}; - -/*[register] TOT_REACT_OUT_PROFILE_CNT*/ -#define TOT_REACT_OUT_PROFILE_CNT -#define TOT_REACT_OUT_PROFILE_CNT_ADDRESS 0x4c0 -#define TOT_REACT_OUT_PROFILE_CNT_NUM 1 -#define TOT_REACT_OUT_PROFILE_CNT_INC 0x4 -#define TOT_REACT_OUT_PROFILE_CNT_TYPE REG_TYPE_RW -#define TOT_REACT_OUT_PROFILE_CNT_DEFAULT 0x0 - /*[field] TOT_REACT_OUT_PROFILE_CNT*/ - #define TOT_REACT_OUT_PROFILE_CNT_TOT_REACT_OUT_PROFILE_CNT - #define TOT_REACT_OUT_PROFILE_CNT_TOT_REACT_OUT_PROFILE_CNT_OFFSET 0 - #define TOT_REACT_OUT_PROFILE_CNT_TOT_REACT_OUT_PROFILE_CNT_LEN 32 - #define TOT_REACT_OUT_PROFILE_CNT_TOT_REACT_OUT_PROFILE_CNT_DEFAULT 0x0 - -struct tot_react_out_profile_cnt { - a_uint32_t tot_react_out_profile_cnt:32; -}; - -union tot_react_out_profile_cnt_u { - a_uint32_t val; - struct tot_react_out_profile_cnt bf; -}; - -/*[register] TOT_REACT_IN_PROFILE_CNT*/ -#define TOT_REACT_IN_PROFILE_CNT -#define TOT_REACT_IN_PROFILE_CNT_ADDRESS 0x4c4 -#define TOT_REACT_IN_PROFILE_CNT_NUM 1 -#define TOT_REACT_IN_PROFILE_CNT_INC 0x4 -#define TOT_REACT_IN_PROFILE_CNT_TYPE REG_TYPE_RW -#define TOT_REACT_IN_PROFILE_CNT_DEFAULT 0x0 - /*[field] TOT_REACT_IN_PROFILE_CNT*/ - #define TOT_REACT_IN_PROFILE_CNT_TOT_REACT_IN_PROFILE_CNT - #define TOT_REACT_IN_PROFILE_CNT_TOT_REACT_IN_PROFILE_CNT_OFFSET 0 - #define TOT_REACT_IN_PROFILE_CNT_TOT_REACT_IN_PROFILE_CNT_LEN 32 - #define TOT_REACT_IN_PROFILE_CNT_TOT_REACT_IN_PROFILE_CNT_DEFAULT 0x0 - -struct tot_react_in_profile_cnt { - a_uint32_t tot_react_in_profile_cnt:32; -}; - -union tot_react_in_profile_cnt_u { - a_uint32_t val; - struct tot_react_in_profile_cnt bf; -}; - -/*[table] PORT_FC_CFG*/ -#define PORT_FC_CFG -#define PORT_FC_CFG_ADDRESS 0x1000 -#define PORT_FC_CFG_NUM 15 -#define PORT_FC_CFG_INC 0x10 -#define PORT_FC_CFG_TYPE REG_TYPE_RW -#define PORT_FC_CFG_DEFAULT 0x0 - /*[field] PORT_REACT_LIMIT*/ - #define PORT_FC_CFG_PORT_REACT_LIMIT - #define PORT_FC_CFG_PORT_REACT_LIMIT_OFFSET 0 - #define PORT_FC_CFG_PORT_REACT_LIMIT_LEN 9 - #define PORT_FC_CFG_PORT_REACT_LIMIT_DEFAULT 0x0 - /*[field] PORT_RESUME_FLOOR_TH*/ - #define PORT_FC_CFG_PORT_RESUME_FLOOR_TH - #define PORT_FC_CFG_PORT_RESUME_FLOOR_TH_OFFSET 9 - #define PORT_FC_CFG_PORT_RESUME_FLOOR_TH_LEN 9 - #define PORT_FC_CFG_PORT_RESUME_FLOOR_TH_DEFAULT 0x0 - /*[field] PORT_RESUME_OFFSET*/ - #define PORT_FC_CFG_PORT_RESUME_OFFSET - #define PORT_FC_CFG_PORT_RESUME_OFFSET_OFFSET 18 - #define PORT_FC_CFG_PORT_RESUME_OFFSET_LEN 11 - #define PORT_FC_CFG_PORT_RESUME_OFFSET_DEFAULT 0x0 - /*[field] PORT_SHARED_CEILING*/ - #define PORT_FC_CFG_PORT_SHARED_CEILING - #define PORT_FC_CFG_PORT_SHARED_CEILING_OFFSET 29 - #define PORT_FC_CFG_PORT_SHARED_CEILING_LEN 11 - #define PORT_FC_CFG_PORT_SHARED_CEILING_DEFAULT 0x0 - /*[field] PORT_SHARED_WEIGHT*/ - #define PORT_FC_CFG_PORT_SHARED_WEIGHT - #define PORT_FC_CFG_PORT_SHARED_WEIGHT_OFFSET 40 - #define PORT_FC_CFG_PORT_SHARED_WEIGHT_LEN 3 - #define PORT_FC_CFG_PORT_SHARED_WEIGHT_DEFAULT 0x0 - /*[field] PORT_SHARED_DYNAMIC*/ - #define PORT_FC_CFG_PORT_SHARED_DYNAMIC - #define PORT_FC_CFG_PORT_SHARED_DYNAMIC_OFFSET 43 - #define PORT_FC_CFG_PORT_SHARED_DYNAMIC_LEN 1 - #define PORT_FC_CFG_PORT_SHARED_DYNAMIC_DEFAULT 0x0 - /*[field] PORT_PRE_ALLOC*/ - #define PORT_FC_CFG_PORT_PRE_ALLOC - #define PORT_FC_CFG_PORT_PRE_ALLOC_OFFSET 44 - #define PORT_FC_CFG_PORT_PRE_ALLOC_LEN 11 - #define PORT_FC_CFG_PORT_PRE_ALLOC_DEFAULT 0x0 - -struct port_fc_cfg { - a_uint32_t port_react_limit:9; - a_uint32_t port_resume_floor_th:9; - a_uint32_t port_resume_offset:11; - a_uint32_t port_shared_ceiling_0:3; - a_uint32_t port_shared_ceiling_1:8; - a_uint32_t port_shared_weight:3; - a_uint32_t port_shared_dynamic:1; - a_uint32_t port_pre_alloc:11; - a_uint32_t _reserved0:9; -}; - -union port_fc_cfg_u { - a_uint32_t val[2]; - struct port_fc_cfg bf; -}; - -/*[table] LLM*/ -#define LLM -#define LLM_ADDRESS 0x10000 -#define LLM_NUM 2048 -#define LLM_INC 0x10 -#define LLM_TYPE REG_TYPE_RW -#define LLM_DEFAULT 0x0 - /*[field] NXT_PTR*/ - #define LLM_NXT_PTR - #define LLM_NXT_PTR_OFFSET 0 - #define LLM_NXT_PTR_LEN 11 - #define LLM_NXT_PTR_DEFAULT 0x0 - /*[field] EOP*/ - #define LLM_EOP - #define LLM_EOP_OFFSET 11 - #define LLM_EOP_LEN 1 - #define LLM_EOP_DEFAULT 0x0 - -struct llm { - a_uint32_t nxt_ptr:11; - a_uint32_t eop:1; - a_uint32_t _reserved0:20; -}; - -union llm_u { - a_uint32_t val; - struct llm bf; -}; - -/*[table] RCM*/ -#define RCM -#define RCM_ADDRESS 0x20000 -#define RCM_NUM 2048 -#define RCM_INC 0x10 -#define RCM_TYPE REG_TYPE_RW -#define RCM_DEFAULT 0x0 - /*[field] REF_CNT*/ - #define RCM_REF_CNT - #define RCM_REF_CNT_OFFSET 0 - #define RCM_REF_CNT_LEN 4 - #define RCM_REF_CNT_DEFAULT 0x0 - -struct rcm { - a_uint32_t ref_cnt:4; - a_uint32_t _reserved0:28; -}; - -union rcm_u { - a_uint32_t val; - struct rcm bf; -}; - -/*[table] DM*/ -#define DM -#define DM_ADDRESS 0x80000 -#define DM_NUM 8192 -#define DM_INC 0x40 -#define DM_TYPE REG_TYPE_RW -#define DM_DEFAULT 0x0 - /*[field] PKT_DATA*/ - #define DM_PKT_DATA - #define DM_PKT_DATA_OFFSET 0 - #define DM_PKT_DATA_LEN 512 - #define DM_PKT_DATA_DEFAULT 0x0 - -struct dm { - a_uint32_t pkt_data_0:32; - a_uint32_t pkt_data_1:32; - a_uint32_t pkt_data_2:32; - a_uint32_t pkt_data_3:32; - a_uint32_t pkt_data_4:32; - a_uint32_t pkt_data_5:32; - a_uint32_t pkt_data_6:32; - a_uint32_t pkt_data_7:32; - a_uint32_t pkt_data_8:32; - a_uint32_t pkt_data_9:32; - a_uint32_t pkt_data_10:32; - a_uint32_t pkt_data_11:32; - a_uint32_t pkt_data_12:32; - a_uint32_t pkt_data_13:32; - a_uint32_t pkt_data_14:32; - a_uint32_t pkt_data_15:32; -}; - -union dm_u { - a_uint32_t val[16]; - struct dm bf; -}; - - -#endif - diff --git a/feeds/ipq807x/qca-ssdk/src/include/hsl/hppe/hppe_ctrlpkt.h b/feeds/ipq807x/qca-ssdk/src/include/hsl/hppe/hppe_ctrlpkt.h deleted file mode 100755 index 83503a3e6..000000000 --- a/feeds/ipq807x/qca-ssdk/src/include/hsl/hppe/hppe_ctrlpkt.h +++ /dev/null @@ -1,245 +0,0 @@ -/* - * Copyright (c) 2016-2017, The Linux Foundation. All rights reserved. - * Permission to use, copy, modify, and/or distribute this software for - * any purpose with or without fee is hereby granted, provided that the - * above copyright notice and this permission notice appear in all copies. - * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES - * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR - * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES - * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN - * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT - * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. - */ - - -/** - * @defgroup - * @{ - */ -#ifndef _HPPE_CTRLPKT_H_ -#define _HPPE_CTRLPKT_H_ - -#define ETHERTYPE_CTRL_MAX_ENTRY 4 -#define RFDB_TBL_MAX_ENTRY 32 -#define APP_CTRL_MAX_ENTRY 32 - - -sw_error_t -hppe_ethertype_ctrl_get( - a_uint32_t dev_id, - a_uint32_t index, - union ethertype_ctrl_u *value); - -sw_error_t -hppe_ethertype_ctrl_set( - a_uint32_t dev_id, - a_uint32_t index, - union ethertype_ctrl_u *value); - -sw_error_t -hppe_app_ctrl_get( - a_uint32_t dev_id, - a_uint32_t index, - union app_ctrl_u *value); - -sw_error_t -hppe_app_ctrl_set( - a_uint32_t dev_id, - a_uint32_t index, - union app_ctrl_u *value); - -sw_error_t -hppe_ethertype_ctrl_ethertype_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_ethertype_ctrl_ethertype_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_ethertype_ctrl_ethertype_en_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_ethertype_ctrl_ethertype_en_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_app_ctrl_portbitmap_include_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_app_ctrl_portbitmap_include_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_app_ctrl_cmd_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_app_ctrl_cmd_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_app_ctrl_portbitmap_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_app_ctrl_portbitmap_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_app_ctrl_rfdb_index_bitmap_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_app_ctrl_rfdb_index_bitmap_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_app_ctrl_protocol_bitmap_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_app_ctrl_protocol_bitmap_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_app_ctrl_in_stg_byp_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_app_ctrl_in_stg_byp_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_app_ctrl_valid_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_app_ctrl_valid_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_app_ctrl_l2_sec_byp_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_app_ctrl_l2_sec_byp_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_app_ctrl_protocol_include_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_app_ctrl_protocol_include_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_app_ctrl_ethertype_include_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_app_ctrl_ethertype_include_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_app_ctrl_sg_byp_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_app_ctrl_sg_byp_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_app_ctrl_rfdb_include_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_app_ctrl_rfdb_include_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_app_ctrl_ethertype_index_bitmap_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_app_ctrl_ethertype_index_bitmap_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_app_ctrl_in_vlan_fltr_byp_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_app_ctrl_in_vlan_fltr_byp_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -#endif - diff --git a/feeds/ipq807x/qca-ssdk/src/include/hsl/hppe/hppe_ctrlpkt_reg.h b/feeds/ipq807x/qca-ssdk/src/include/hsl/hppe/hppe_ctrlpkt_reg.h deleted file mode 100755 index 943157f06..000000000 --- a/feeds/ipq807x/qca-ssdk/src/include/hsl/hppe/hppe_ctrlpkt_reg.h +++ /dev/null @@ -1,154 +0,0 @@ -/* - * Copyright (c) 2016-2017, The Linux Foundation. All rights reserved. - * Permission to use, copy, modify, and/or distribute this software for - * any purpose with or without fee is hereby granted, provided that the - * above copyright notice and this permission notice appear in all copies. - * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES - * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR - * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES - * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN - * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT - * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. - */ - -#ifndef HPPE_CTRLPKT_REG_H -#define HPPE_CTRLPKT_REG_H - -/** - * @defgroup - * @{ - */ -/*[register] ETHERTYPE_CTRL*/ -#define ETHERTYPE_CTRL -#define ETHERTYPE_CTRL_ADDRESS 0x80 -#define ETHERTYPE_CTRL_NUM 4 -#define ETHERTYPE_CTRL_INC 0x4 -#define ETHERTYPE_CTRL_TYPE REG_TYPE_RW -#define ETHERTYPE_CTRL_DEFAULT 0x0 - /*[field] ETHERTYPE_EN*/ - #define ETHERTYPE_CTRL_ETHERTYPE_EN - #define ETHERTYPE_CTRL_ETHERTYPE_EN_OFFSET 0 - #define ETHERTYPE_CTRL_ETHERTYPE_EN_LEN 1 - #define ETHERTYPE_CTRL_ETHERTYPE_EN_DEFAULT 0x0 - /*[field] ETHERTYPE*/ - #define ETHERTYPE_CTRL_ETHERTYPE - #define ETHERTYPE_CTRL_ETHERTYPE_OFFSET 16 - #define ETHERTYPE_CTRL_ETHERTYPE_LEN 16 - #define ETHERTYPE_CTRL_ETHERTYPE_DEFAULT 0x0 - -struct ethertype_ctrl { - a_uint32_t ethertype_en:1; - a_uint32_t _reserved0:15; - a_uint32_t ethertype:16; -}; - -union ethertype_ctrl_u { - a_uint32_t val; - struct ethertype_ctrl bf; -}; - -/*[table] APP_CTRL*/ -#define APP_CTRL -#define APP_CTRL_ADDRESS 0x1400 -#define APP_CTRL_NUM 32 -#define APP_CTRL_INC 0x10 -#define APP_CTRL_TYPE REG_TYPE_RW -#define APP_CTRL_DEFAULT 0x0 - /*[field] VALID*/ - #define APP_CTRL_VALID - #define APP_CTRL_VALID_OFFSET 0 - #define APP_CTRL_VALID_LEN 1 - #define APP_CTRL_VALID_DEFAULT 0x0 - /*[field] RFDB_INCLUDE*/ - #define APP_CTRL_RFDB_INCLUDE - #define APP_CTRL_RFDB_INCLUDE_OFFSET 1 - #define APP_CTRL_RFDB_INCLUDE_LEN 1 - #define APP_CTRL_RFDB_INCLUDE_DEFAULT 0x0 - /*[field] RFDB_INDEX_BITMAP*/ - #define APP_CTRL_RFDB_INDEX_BITMAP - #define APP_CTRL_RFDB_INDEX_BITMAP_OFFSET 2 - #define APP_CTRL_RFDB_INDEX_BITMAP_LEN 32 - #define APP_CTRL_RFDB_INDEX_BITMAP_DEFAULT 0x0 - /*[field] PROTOCOL_INCLUDE*/ - #define APP_CTRL_PROTOCOL_INCLUDE - #define APP_CTRL_PROTOCOL_INCLUDE_OFFSET 34 - #define APP_CTRL_PROTOCOL_INCLUDE_LEN 1 - #define APP_CTRL_PROTOCOL_INCLUDE_DEFAULT 0x0 - /*[field] PROTOCOL_BITMAP*/ - #define APP_CTRL_PROTOCOL_BITMAP - #define APP_CTRL_PROTOCOL_BITMAP_OFFSET 35 - #define APP_CTRL_PROTOCOL_BITMAP_LEN 26 - #define APP_CTRL_PROTOCOL_BITMAP_DEFAULT 0x0 - /*[field] ETHERTYPE_INCLUDE*/ - #define APP_CTRL_ETHERTYPE_INCLUDE - #define APP_CTRL_ETHERTYPE_INCLUDE_OFFSET 61 - #define APP_CTRL_ETHERTYPE_INCLUDE_LEN 1 - #define APP_CTRL_ETHERTYPE_INCLUDE_DEFAULT 0x0 - /*[field] ETHERTYPE_INDEX_BITMAP*/ - #define APP_CTRL_ETHERTYPE_INDEX_BITMAP - #define APP_CTRL_ETHERTYPE_INDEX_BITMAP_OFFSET 62 - #define APP_CTRL_ETHERTYPE_INDEX_BITMAP_LEN 4 - #define APP_CTRL_ETHERTYPE_INDEX_BITMAP_DEFAULT 0x0 - /*[field] PORTBITMAP_INCLUDE*/ - #define APP_CTRL_PORTBITMAP_INCLUDE - #define APP_CTRL_PORTBITMAP_INCLUDE_OFFSET 66 - #define APP_CTRL_PORTBITMAP_INCLUDE_LEN 1 - #define APP_CTRL_PORTBITMAP_INCLUDE_DEFAULT 0x0 - /*[field] PORTBITMAP*/ - #define APP_CTRL_PORTBITMAP - #define APP_CTRL_PORTBITMAP_OFFSET 67 - #define APP_CTRL_PORTBITMAP_LEN 8 - #define APP_CTRL_PORTBITMAP_DEFAULT 0x0 - /*[field] IN_VLAN_FLTR_BYP*/ - #define APP_CTRL_IN_VLAN_FLTR_BYP - #define APP_CTRL_IN_VLAN_FLTR_BYP_OFFSET 75 - #define APP_CTRL_IN_VLAN_FLTR_BYP_LEN 1 - #define APP_CTRL_IN_VLAN_FLTR_BYP_DEFAULT 0x0 - /*[field] IN_STG_BYP*/ - #define APP_CTRL_IN_STG_BYP - #define APP_CTRL_IN_STG_BYP_OFFSET 76 - #define APP_CTRL_IN_STG_BYP_LEN 1 - #define APP_CTRL_IN_STG_BYP_DEFAULT 0x0 - /*[field] L2_SEC_BYP*/ - #define APP_CTRL_L2_SEC_BYP - #define APP_CTRL_L2_SEC_BYP_OFFSET 77 - #define APP_CTRL_L2_SEC_BYP_LEN 1 - #define APP_CTRL_L2_SEC_BYP_DEFAULT 0x0 - /*[field] SG_BYP*/ - #define APP_CTRL_SG_BYP - #define APP_CTRL_SG_BYP_OFFSET 78 - #define APP_CTRL_SG_BYP_LEN 1 - #define APP_CTRL_SG_BYP_DEFAULT 0x0 - /*[field] CMD*/ - #define APP_CTRL_CMD - #define APP_CTRL_CMD_OFFSET 79 - #define APP_CTRL_CMD_LEN 2 - #define APP_CTRL_CMD_DEFAULT 0x0 - -struct app_ctrl { - a_uint32_t valid:1; - a_uint32_t rfdb_include:1; - a_uint32_t rfdb_index_bitmap_0:30; - a_uint32_t rfdb_index_bitmap_1:2; - a_uint32_t protocol_include:1; - a_uint32_t protocol_bitmap:26; - a_uint32_t ethertype_include:1; - a_uint32_t ethertype_index_bitmap_0:2; - a_uint32_t ethertype_index_bitmap_1:2; - a_uint32_t portbitmap_include:1; - a_uint32_t portbitmap:8; - a_uint32_t in_vlan_fltr_byp:1; - a_uint32_t in_stg_byp:1; - a_uint32_t l2_sec_byp:1; - a_uint32_t sg_byp:1; - a_uint32_t cmd:2; - a_uint32_t _reserved0:15; -}; - -union app_ctrl_u { - a_uint32_t val[3]; - struct app_ctrl bf; -}; - -#endif diff --git a/feeds/ipq807x/qca-ssdk/src/include/hsl/hppe/hppe_fdb.h b/feeds/ipq807x/qca-ssdk/src/include/hsl/hppe/hppe_fdb.h deleted file mode 100755 index d99bfd6ba..000000000 --- a/feeds/ipq807x/qca-ssdk/src/include/hsl/hppe/hppe_fdb.h +++ /dev/null @@ -1,900 +0,0 @@ -/* - * Copyright (c) 2016-2017, The Linux Foundation. All rights reserved. - * Permission to use, copy, modify, and/or distribute this software for - * any purpose with or without fee is hereby granted, provided that the - * above copyright notice and this permission notice appear in all copies. - * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES - * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR - * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES - * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN - * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT - * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. - */ - - -/** - * @defgroup - * @{ - */ -#ifndef _HPPE_FDB_H_ -#define _HPPE_FDB_H_ - -#define PRE_L2_CNT_TBL_MAX_ENTRY 32 -#define PORT_BRIDGE_CTRL_MAX_ENTRY 8 -#define PORT_LRN_LIMIT_CTRL_MAX_ENTRY 8 -#define PORT_LRN_LIMIT_COUNTER_MAX_ENTRY 8 -#define RFDB_TBL_MAX_ENTRY 32 -#define FDB_TBL_MAX_ENTRY 2048 - - -sw_error_t -hppe_l2_dbg_addr_get( - a_uint32_t dev_id, - union l2_dbg_addr_u *value); - -sw_error_t -hppe_l2_dbg_addr_set( - a_uint32_t dev_id, - union l2_dbg_addr_u *value); - -sw_error_t -hppe_l2_dbg_data_get( - a_uint32_t dev_id, - union l2_dbg_data_u *value); - -sw_error_t -hppe_l2_dbg_data_set( - a_uint32_t dev_id, - union l2_dbg_data_u *value); - -sw_error_t -hppe_fdb_tbl_op_get( - a_uint32_t dev_id, - union fdb_tbl_op_u *value); - -sw_error_t -hppe_fdb_tbl_op_set( - a_uint32_t dev_id, - union fdb_tbl_op_u *value); - -sw_error_t -hppe_fdb_tbl_rd_op_get( - a_uint32_t dev_id, - union fdb_tbl_rd_op_u *value); - -sw_error_t -hppe_fdb_tbl_rd_op_set( - a_uint32_t dev_id, - union fdb_tbl_rd_op_u *value); - -sw_error_t -hppe_fdb_tbl_op_rslt_get( - a_uint32_t dev_id, - union fdb_tbl_op_rslt_u *value); - -sw_error_t -hppe_fdb_tbl_op_rslt_set( - a_uint32_t dev_id, - union fdb_tbl_op_rslt_u *value); - -sw_error_t -hppe_fdb_tbl_rd_op_rslt_get( - a_uint32_t dev_id, - union fdb_tbl_rd_op_rslt_u *value); - -sw_error_t -hppe_fdb_tbl_rd_op_rslt_set( - a_uint32_t dev_id, - union fdb_tbl_rd_op_rslt_u *value); - -sw_error_t -hppe_age_timer_get( - a_uint32_t dev_id, - union age_timer_u *value); - -sw_error_t -hppe_age_timer_set( - a_uint32_t dev_id, - union age_timer_u *value); - -sw_error_t -hppe_l2_global_conf_get( - a_uint32_t dev_id, - union l2_global_conf_u *value); - -sw_error_t -hppe_l2_global_conf_set( - a_uint32_t dev_id, - union l2_global_conf_u *value); - -sw_error_t -hppe_l2_dbgcnt_cmd_get( - a_uint32_t dev_id, - union l2_dbgcnt_cmd_u *value); - -sw_error_t -hppe_l2_dbgcnt_cmd_set( - a_uint32_t dev_id, - union l2_dbgcnt_cmd_u *value); - -sw_error_t -hppe_l2_dbgcnt_rdata_get( - a_uint32_t dev_id, - union l2_dbgcnt_rdata_u *value); - -sw_error_t -hppe_l2_dbgcnt_rdata_set( - a_uint32_t dev_id, - union l2_dbgcnt_rdata_u *value); - -sw_error_t -hppe_l2_dbgcnt_wdata_get( - a_uint32_t dev_id, - union l2_dbgcnt_wdata_u *value); - -sw_error_t -hppe_l2_dbgcnt_wdata_set( - a_uint32_t dev_id, - union l2_dbgcnt_wdata_u *value); - -sw_error_t -hppe_fdb_tbl_rd_op_rslt_data0_get( - a_uint32_t dev_id, - union fdb_tbl_rd_op_rslt_data0_u *value); - -sw_error_t -hppe_fdb_tbl_rd_op_rslt_data0_set( - a_uint32_t dev_id, - union fdb_tbl_rd_op_rslt_data0_u *value); - -sw_error_t -hppe_fdb_tbl_rd_op_rslt_data1_get( - a_uint32_t dev_id, - union fdb_tbl_rd_op_rslt_data1_u *value); - -sw_error_t -hppe_fdb_tbl_rd_op_rslt_data1_set( - a_uint32_t dev_id, - union fdb_tbl_rd_op_rslt_data1_u *value); - -sw_error_t -hppe_fdb_tbl_rd_op_rslt_data2_get( - a_uint32_t dev_id, - union fdb_tbl_rd_op_rslt_data2_u *value); - -sw_error_t -hppe_fdb_tbl_rd_op_rslt_data2_set( - a_uint32_t dev_id, - union fdb_tbl_rd_op_rslt_data2_u *value); - -sw_error_t -hppe_fdb_tbl_op_data0_get( - a_uint32_t dev_id, - union fdb_tbl_op_data0_u *value); - -sw_error_t -hppe_fdb_tbl_op_data0_set( - a_uint32_t dev_id, - union fdb_tbl_op_data0_u *value); - -sw_error_t -hppe_fdb_tbl_op_data1_get( - a_uint32_t dev_id, - union fdb_tbl_op_data1_u *value); - -sw_error_t -hppe_fdb_tbl_op_data1_set( - a_uint32_t dev_id, - union fdb_tbl_op_data1_u *value); - -sw_error_t -hppe_fdb_tbl_op_data2_get( - a_uint32_t dev_id, - union fdb_tbl_op_data2_u *value); - -sw_error_t -hppe_fdb_tbl_op_data2_set( - a_uint32_t dev_id, - union fdb_tbl_op_data2_u *value); - -sw_error_t -hppe_fdb_tbl_rd_op_data0_get( - a_uint32_t dev_id, - union fdb_tbl_rd_op_data0_u *value); - -sw_error_t -hppe_fdb_tbl_rd_op_data0_set( - a_uint32_t dev_id, - union fdb_tbl_rd_op_data0_u *value); - -sw_error_t -hppe_fdb_tbl_rd_op_data1_get( - a_uint32_t dev_id, - union fdb_tbl_rd_op_data1_u *value); - -sw_error_t -hppe_fdb_tbl_rd_op_data1_set( - a_uint32_t dev_id, - union fdb_tbl_rd_op_data1_u *value); - -sw_error_t -hppe_fdb_tbl_rd_op_data2_get( - a_uint32_t dev_id, - union fdb_tbl_rd_op_data2_u *value); - -sw_error_t -hppe_fdb_tbl_rd_op_data2_set( - a_uint32_t dev_id, - union fdb_tbl_rd_op_data2_u *value); - -sw_error_t -hppe_port_bridge_ctrl_get( - a_uint32_t dev_id, - a_uint32_t index, - union port_bridge_ctrl_u *value); - -sw_error_t -hppe_port_bridge_ctrl_set( - a_uint32_t dev_id, - a_uint32_t index, - union port_bridge_ctrl_u *value); - -sw_error_t -hppe_port_lrn_limit_ctrl_get( - a_uint32_t dev_id, - a_uint32_t index, - union port_lrn_limit_ctrl_u *value); - -sw_error_t -hppe_port_lrn_limit_ctrl_set( - a_uint32_t dev_id, - a_uint32_t index, - union port_lrn_limit_ctrl_u *value); - -sw_error_t -hppe_port_lrn_limit_counter_get( - a_uint32_t dev_id, - a_uint32_t index, - union port_lrn_limit_counter_u *value); - -sw_error_t -hppe_port_lrn_limit_counter_set( - a_uint32_t dev_id, - a_uint32_t index, - union port_lrn_limit_counter_u *value); - -sw_error_t -hppe_rfdb_tbl_get( - a_uint32_t dev_id, - a_uint32_t index, - union rfdb_tbl_u *value); - -sw_error_t -hppe_rfdb_tbl_set( - a_uint32_t dev_id, - a_uint32_t index, - union rfdb_tbl_u *value); - -sw_error_t -hppe_fdb_tbl_get( - a_uint32_t dev_id, - a_uint32_t index, - union fdb_tbl_u *value); - -sw_error_t -hppe_fdb_tbl_set( - a_uint32_t dev_id, - a_uint32_t index, - union fdb_tbl_u *value); - -sw_error_t -hppe_l2_dbg_addr_l2_dbg_addr_get( - a_uint32_t dev_id, - unsigned int *value); - -sw_error_t -hppe_l2_dbg_addr_l2_dbg_addr_set( - a_uint32_t dev_id, - unsigned int value); - -sw_error_t -hppe_l2_dbg_data_l2_dbg_data_get( - a_uint32_t dev_id, - unsigned int *value); - -sw_error_t -hppe_l2_dbg_data_l2_dbg_data_set( - a_uint32_t dev_id, - unsigned int value); - -sw_error_t -hppe_fdb_tbl_op_op_mode_get( - a_uint32_t dev_id, - unsigned int *value); - -sw_error_t -hppe_fdb_tbl_op_op_mode_set( - a_uint32_t dev_id, - unsigned int value); - -sw_error_t -hppe_fdb_tbl_op_op_type_get( - a_uint32_t dev_id, - unsigned int *value); - -sw_error_t -hppe_fdb_tbl_op_op_type_set( - a_uint32_t dev_id, - unsigned int value); - -sw_error_t -hppe_fdb_tbl_op_entry_index_get( - a_uint32_t dev_id, - unsigned int *value); - -sw_error_t -hppe_fdb_tbl_op_entry_index_set( - a_uint32_t dev_id, - unsigned int value); - -sw_error_t -hppe_fdb_tbl_op_cmd_id_get( - a_uint32_t dev_id, - unsigned int *value); - -sw_error_t -hppe_fdb_tbl_op_cmd_id_set( - a_uint32_t dev_id, - unsigned int value); - -sw_error_t -hppe_fdb_tbl_op_hash_block_bitmap_get( - a_uint32_t dev_id, - unsigned int *value); - -sw_error_t -hppe_fdb_tbl_op_hash_block_bitmap_set( - a_uint32_t dev_id, - unsigned int value); - -sw_error_t -hppe_fdb_tbl_op_byp_rslt_en_get( - a_uint32_t dev_id, - unsigned int *value); - -sw_error_t -hppe_fdb_tbl_op_byp_rslt_en_set( - a_uint32_t dev_id, - unsigned int value); - -sw_error_t -hppe_fdb_tbl_rd_op_op_mode_get( - a_uint32_t dev_id, - unsigned int *value); - -sw_error_t -hppe_fdb_tbl_rd_op_op_mode_set( - a_uint32_t dev_id, - unsigned int value); - -sw_error_t -hppe_fdb_tbl_rd_op_op_type_get( - a_uint32_t dev_id, - unsigned int *value); - -sw_error_t -hppe_fdb_tbl_rd_op_op_type_set( - a_uint32_t dev_id, - unsigned int value); - -sw_error_t -hppe_fdb_tbl_rd_op_entry_index_get( - a_uint32_t dev_id, - unsigned int *value); - -sw_error_t -hppe_fdb_tbl_rd_op_entry_index_set( - a_uint32_t dev_id, - unsigned int value); - -sw_error_t -hppe_fdb_tbl_rd_op_cmd_id_get( - a_uint32_t dev_id, - unsigned int *value); - -sw_error_t -hppe_fdb_tbl_rd_op_cmd_id_set( - a_uint32_t dev_id, - unsigned int value); - -sw_error_t -hppe_fdb_tbl_rd_op_hash_block_bitmap_get( - a_uint32_t dev_id, - unsigned int *value); - -sw_error_t -hppe_fdb_tbl_rd_op_hash_block_bitmap_set( - a_uint32_t dev_id, - unsigned int value); - -sw_error_t -hppe_fdb_tbl_rd_op_byp_rslt_en_get( - a_uint32_t dev_id, - unsigned int *value); - -sw_error_t -hppe_fdb_tbl_rd_op_byp_rslt_en_set( - a_uint32_t dev_id, - unsigned int value); - -sw_error_t -hppe_fdb_tbl_op_rslt_op_rslt_get( - a_uint32_t dev_id, - unsigned int *value); - -sw_error_t -hppe_fdb_tbl_op_rslt_op_rslt_set( - a_uint32_t dev_id, - unsigned int value); - -sw_error_t -hppe_fdb_tbl_op_rslt_valid_cnt_get( - a_uint32_t dev_id, - unsigned int *value); - -sw_error_t -hppe_fdb_tbl_op_rslt_valid_cnt_set( - a_uint32_t dev_id, - unsigned int value); - -sw_error_t -hppe_fdb_tbl_op_rslt_entry_index_get( - a_uint32_t dev_id, - unsigned int *value); - -sw_error_t -hppe_fdb_tbl_op_rslt_entry_index_set( - a_uint32_t dev_id, - unsigned int value); - -sw_error_t -hppe_fdb_tbl_op_rslt_cmd_id_get( - a_uint32_t dev_id, - unsigned int *value); - -sw_error_t -hppe_fdb_tbl_op_rslt_cmd_id_set( - a_uint32_t dev_id, - unsigned int value); - -sw_error_t -hppe_fdb_tbl_rd_op_rslt_op_rslt_get( - a_uint32_t dev_id, - unsigned int *value); - -sw_error_t -hppe_fdb_tbl_rd_op_rslt_op_rslt_set( - a_uint32_t dev_id, - unsigned int value); - -sw_error_t -hppe_fdb_tbl_rd_op_rslt_valid_cnt_get( - a_uint32_t dev_id, - unsigned int *value); - -sw_error_t -hppe_fdb_tbl_rd_op_rslt_valid_cnt_set( - a_uint32_t dev_id, - unsigned int value); - -sw_error_t -hppe_fdb_tbl_rd_op_rslt_entry_index_get( - a_uint32_t dev_id, - unsigned int *value); - -sw_error_t -hppe_fdb_tbl_rd_op_rslt_entry_index_set( - a_uint32_t dev_id, - unsigned int value); - -sw_error_t -hppe_fdb_tbl_rd_op_rslt_cmd_id_get( - a_uint32_t dev_id, - unsigned int *value); - -sw_error_t -hppe_fdb_tbl_rd_op_rslt_cmd_id_set( - a_uint32_t dev_id, - unsigned int value); - -sw_error_t -hppe_age_timer_age_val_get( - a_uint32_t dev_id, - unsigned int *value); - -sw_error_t -hppe_age_timer_age_val_set( - a_uint32_t dev_id, - unsigned int value); - -sw_error_t -hppe_l2_global_conf_fdb_hash_full_fwd_cmd_get( - a_uint32_t dev_id, - unsigned int *value); - -sw_error_t -hppe_l2_global_conf_fdb_hash_full_fwd_cmd_set( - a_uint32_t dev_id, - unsigned int value); - -sw_error_t -hppe_l2_global_conf_failover_en_get( - a_uint32_t dev_id, - unsigned int *value); - -sw_error_t -hppe_l2_global_conf_failover_en_set( - a_uint32_t dev_id, - unsigned int value); - -sw_error_t -hppe_l2_global_conf_lrn_ctrl_mode_get( - a_uint32_t dev_id, - unsigned int *value); - -sw_error_t -hppe_l2_global_conf_lrn_ctrl_mode_set( - a_uint32_t dev_id, - unsigned int value); - -sw_error_t -hppe_l2_global_conf_age_en_get( - a_uint32_t dev_id, - unsigned int *value); - -sw_error_t -hppe_l2_global_conf_age_en_set( - a_uint32_t dev_id, - unsigned int value); - -sw_error_t -hppe_l2_global_conf_fdb_hash_mode_1_get( - a_uint32_t dev_id, - unsigned int *value); - -sw_error_t -hppe_l2_global_conf_fdb_hash_mode_1_set( - a_uint32_t dev_id, - unsigned int value); - -sw_error_t -hppe_l2_global_conf_lrn_en_get( - a_uint32_t dev_id, - unsigned int *value); - -sw_error_t -hppe_l2_global_conf_lrn_en_set( - a_uint32_t dev_id, - unsigned int value); - -sw_error_t -hppe_l2_global_conf_fdb_hash_mode_0_get( - a_uint32_t dev_id, - unsigned int *value); - -sw_error_t -hppe_l2_global_conf_fdb_hash_mode_0_set( - a_uint32_t dev_id, - unsigned int value); - -sw_error_t -hppe_l2_global_conf_age_ctrl_mode_get( - a_uint32_t dev_id, - unsigned int *value); - -sw_error_t -hppe_l2_global_conf_age_ctrl_mode_set( - a_uint32_t dev_id, - unsigned int value); - -#ifndef IN_FDB_MINI -sw_error_t -hppe_l2_global_conf_service_code_loop_get( - a_uint32_t dev_id, - unsigned int *value); - -sw_error_t -hppe_l2_global_conf_service_code_loop_set( - a_uint32_t dev_id, - unsigned int value); -#endif - -sw_error_t -hppe_l2_dbgcnt_cmd_type_get( - a_uint32_t dev_id, - unsigned int *value); - -sw_error_t -hppe_l2_dbgcnt_cmd_type_set( - a_uint32_t dev_id, - unsigned int value); - -sw_error_t -hppe_l2_dbgcnt_cmd_addr_get( - a_uint32_t dev_id, - unsigned int *value); - -sw_error_t -hppe_l2_dbgcnt_cmd_addr_set( - a_uint32_t dev_id, - unsigned int value); - -sw_error_t -hppe_l2_dbgcnt_rdata_data_get( - a_uint32_t dev_id, - unsigned int *value); - -sw_error_t -hppe_l2_dbgcnt_rdata_data_set( - a_uint32_t dev_id, - unsigned int value); - -sw_error_t -hppe_l2_dbgcnt_wdata_data_get( - a_uint32_t dev_id, - unsigned int *value); - -sw_error_t -hppe_l2_dbgcnt_wdata_data_set( - a_uint32_t dev_id, - unsigned int value); - -sw_error_t -hppe_fdb_tbl_rd_op_rslt_data0_data_get( - a_uint32_t dev_id, - unsigned int *value); - -sw_error_t -hppe_fdb_tbl_rd_op_rslt_data0_data_set( - a_uint32_t dev_id, - unsigned int value); - -sw_error_t -hppe_fdb_tbl_rd_op_rslt_data1_data_get( - a_uint32_t dev_id, - unsigned int *value); - -sw_error_t -hppe_fdb_tbl_rd_op_rslt_data1_data_set( - a_uint32_t dev_id, - unsigned int value); - -sw_error_t -hppe_fdb_tbl_rd_op_rslt_data2_data_get( - a_uint32_t dev_id, - unsigned int *value); - -sw_error_t -hppe_fdb_tbl_rd_op_rslt_data2_data_set( - a_uint32_t dev_id, - unsigned int value); - -sw_error_t -hppe_fdb_tbl_op_data0_data_get( - a_uint32_t dev_id, - unsigned int *value); - -sw_error_t -hppe_fdb_tbl_op_data0_data_set( - a_uint32_t dev_id, - unsigned int value); - -sw_error_t -hppe_fdb_tbl_op_data1_data_get( - a_uint32_t dev_id, - unsigned int *value); - -sw_error_t -hppe_fdb_tbl_op_data1_data_set( - a_uint32_t dev_id, - unsigned int value); - -sw_error_t -hppe_fdb_tbl_op_data2_data_get( - a_uint32_t dev_id, - unsigned int *value); - -sw_error_t -hppe_fdb_tbl_op_data2_data_set( - a_uint32_t dev_id, - unsigned int value); - -sw_error_t -hppe_fdb_tbl_rd_op_data0_data_get( - a_uint32_t dev_id, - unsigned int *value); - -sw_error_t -hppe_fdb_tbl_rd_op_data0_data_set( - a_uint32_t dev_id, - unsigned int value); - -sw_error_t -hppe_fdb_tbl_rd_op_data1_data_get( - a_uint32_t dev_id, - unsigned int *value); - -sw_error_t -hppe_fdb_tbl_rd_op_data1_data_set( - a_uint32_t dev_id, - unsigned int value); - -sw_error_t -hppe_fdb_tbl_rd_op_data2_data_get( - a_uint32_t dev_id, - unsigned int *value); - -sw_error_t -hppe_fdb_tbl_rd_op_data2_data_set( - a_uint32_t dev_id, - unsigned int value); - -sw_error_t -hppe_port_bridge_ctrl_txmac_en_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_port_bridge_ctrl_txmac_en_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_port_bridge_ctrl_port_isolation_bitmap_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_port_bridge_ctrl_port_isolation_bitmap_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_port_bridge_ctrl_station_move_lrn_en_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_port_bridge_ctrl_station_move_lrn_en_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_port_bridge_ctrl_new_addr_fwd_cmd_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_port_bridge_ctrl_new_addr_fwd_cmd_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_port_bridge_ctrl_promisc_en_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_port_bridge_ctrl_promisc_en_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_port_bridge_ctrl_new_addr_lrn_en_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_port_bridge_ctrl_new_addr_lrn_en_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_port_bridge_ctrl_station_move_fwd_cmd_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_port_bridge_ctrl_station_move_fwd_cmd_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_port_lrn_limit_ctrl_lrn_lmt_en_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_port_lrn_limit_ctrl_lrn_lmt_en_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_port_lrn_limit_ctrl_lrn_lmt_cnt_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_port_lrn_limit_ctrl_lrn_lmt_cnt_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_port_lrn_limit_ctrl_lrn_lmt_exceed_fwd_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_port_lrn_limit_ctrl_lrn_lmt_exceed_fwd_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_port_lrn_limit_counter_lrn_cnt_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_port_lrn_limit_counter_lrn_cnt_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_rfdb_tbl_mac_addr_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint64_t *value); - -sw_error_t -hppe_rfdb_tbl_mac_addr_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint64_t value); - -sw_error_t -hppe_rfdb_tbl_valid_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_rfdb_tbl_valid_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -#endif - diff --git a/feeds/ipq807x/qca-ssdk/src/include/hsl/hppe/hppe_fdb_reg.h b/feeds/ipq807x/qca-ssdk/src/include/hsl/hppe/hppe_fdb_reg.h deleted file mode 100755 index 1bbc37f15..000000000 --- a/feeds/ipq807x/qca-ssdk/src/include/hsl/hppe/hppe_fdb_reg.h +++ /dev/null @@ -1,838 +0,0 @@ -/* - * Copyright (c) 2016-2017, 2019, The Linux Foundation. All rights reserved. - * Permission to use, copy, modify, and/or distribute this software for - * any purpose with or without fee is hereby granted, provided that the - * above copyright notice and this permission notice appear in all copies. - * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES - * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR - * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES - * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN - * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT - * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. - */ - - -/** - * @defgroup - * @{ - */ -#ifndef HPPE_FDB_REG_H -#define HPPE_FDB_REG_H - -/*[register] L2_DBG_ADDR*/ -#define L2_DBG_ADDR -#define L2_DBG_ADDR_ADDRESS 0x0 -#define L2_DBG_ADDR_NUM 1 -#define L2_DBG_ADDR_INC 0x4 -#define L2_DBG_ADDR_TYPE REG_TYPE_RW -#define L2_DBG_ADDR_DEFAULT 0x0 - /*[field] L2_DBG_ADDR*/ - #define L2_DBG_ADDR_L2_DBG_ADDR - #define L2_DBG_ADDR_L2_DBG_ADDR_OFFSET 0 - #define L2_DBG_ADDR_L2_DBG_ADDR_LEN 32 - #define L2_DBG_ADDR_L2_DBG_ADDR_DEFAULT 0x0 - -struct l2_dbg_addr { - a_uint32_t l2_dbg_addr:32; -}; - -union l2_dbg_addr_u { - a_uint32_t val; - struct l2_dbg_addr bf; -}; - -/*[register] L2_DBG_DATA*/ -#define L2_DBG_DATA -#define L2_DBG_DATA_ADDRESS 0x4 -#define L2_DBG_DATA_NUM 1 -#define L2_DBG_DATA_INC 0x4 -#define L2_DBG_DATA_TYPE REG_TYPE_RO -#define L2_DBG_DATA_DEFAULT 0x0 - /*[field] L2_DBG_DATA*/ - #define L2_DBG_DATA_L2_DBG_DATA - #define L2_DBG_DATA_L2_DBG_DATA_OFFSET 0 - #define L2_DBG_DATA_L2_DBG_DATA_LEN 32 - #define L2_DBG_DATA_L2_DBG_DATA_DEFAULT 0x0 - -struct l2_dbg_data { - a_uint32_t l2_dbg_data:32; -}; - -union l2_dbg_data_u { - a_uint32_t val; - struct l2_dbg_data bf; -}; - -/*[register] FDB_TBL_OP*/ -#define FDB_TBL_OP -#define FDB_TBL_OP_ADDRESS 0x8 -#define FDB_TBL_OP_NUM 1 -#define FDB_TBL_OP_INC 0x4 -#define FDB_TBL_OP_TYPE REG_TYPE_RW -#define FDB_TBL_OP_DEFAULT 0x0 - /*[field] CMD_ID*/ - #define FDB_TBL_OP_CMD_ID - #define FDB_TBL_OP_CMD_ID_OFFSET 0 - #define FDB_TBL_OP_CMD_ID_LEN 4 - #define FDB_TBL_OP_CMD_ID_DEFAULT 0x0 - /*[field] BYP_RSLT_EN*/ - #define FDB_TBL_OP_BYP_RSLT_EN - #define FDB_TBL_OP_BYP_RSLT_EN_OFFSET 4 - #define FDB_TBL_OP_BYP_RSLT_EN_LEN 1 - #define FDB_TBL_OP_BYP_RSLT_EN_DEFAULT 0x0 - /*[field] OP_TYPE*/ - #define FDB_TBL_OP_OP_TYPE - #define FDB_TBL_OP_OP_TYPE_OFFSET 5 - #define FDB_TBL_OP_OP_TYPE_LEN 3 - #define FDB_TBL_OP_OP_TYPE_DEFAULT 0x0 - /*[field] HASH_BLOCK_BITMAP*/ - #define FDB_TBL_OP_HASH_BLOCK_BITMAP - #define FDB_TBL_OP_HASH_BLOCK_BITMAP_OFFSET 8 - #define FDB_TBL_OP_HASH_BLOCK_BITMAP_LEN 2 - #define FDB_TBL_OP_HASH_BLOCK_BITMAP_DEFAULT 0x0 - /*[field] OP_MODE*/ - #define FDB_TBL_OP_OP_MODE - #define FDB_TBL_OP_OP_MODE_OFFSET 10 - #define FDB_TBL_OP_OP_MODE_LEN 1 - #define FDB_TBL_OP_OP_MODE_DEFAULT 0x0 - /*[field] ENTRY_INDEX*/ - #define FDB_TBL_OP_ENTRY_INDEX - #define FDB_TBL_OP_ENTRY_INDEX_OFFSET 11 - #define FDB_TBL_OP_ENTRY_INDEX_LEN 11 - #define FDB_TBL_OP_ENTRY_INDEX_DEFAULT 0x0 - -struct fdb_tbl_op { - a_uint32_t cmd_id:4; - a_uint32_t byp_rslt_en:1; - a_uint32_t op_type:3; - a_uint32_t hash_block_bitmap:2; - a_uint32_t op_mode:1; - a_uint32_t entry_index:11; - a_uint32_t _reserved0:10; -}; - -union fdb_tbl_op_u { - a_uint32_t val; - struct fdb_tbl_op bf; -}; - -/*[register] FDB_TBL_RD_OP*/ -#define FDB_TBL_RD_OP -#define FDB_TBL_RD_OP_ADDRESS 0x10 -#define FDB_TBL_RD_OP_NUM 1 -#define FDB_TBL_RD_OP_INC 0x4 -#define FDB_TBL_RD_OP_TYPE REG_TYPE_RW -#define FDB_TBL_RD_OP_DEFAULT 0x0 - /*[field] CMD_ID*/ - #define FDB_TBL_RD_OP_CMD_ID - #define FDB_TBL_RD_OP_CMD_ID_OFFSET 0 - #define FDB_TBL_RD_OP_CMD_ID_LEN 4 - #define FDB_TBL_RD_OP_CMD_ID_DEFAULT 0x0 - /*[field] BYP_RSLT_EN*/ - #define FDB_TBL_RD_OP_BYP_RSLT_EN - #define FDB_TBL_RD_OP_BYP_RSLT_EN_OFFSET 4 - #define FDB_TBL_RD_OP_BYP_RSLT_EN_LEN 1 - #define FDB_TBL_RD_OP_BYP_RSLT_EN_DEFAULT 0x0 - /*[field] OP_TYPE*/ - #define FDB_TBL_RD_OP_OP_TYPE - #define FDB_TBL_RD_OP_OP_TYPE_OFFSET 5 - #define FDB_TBL_RD_OP_OP_TYPE_LEN 3 - #define FDB_TBL_RD_OP_OP_TYPE_DEFAULT 0x0 - /*[field] HASH_BLOCK_BITMAP*/ - #define FDB_TBL_RD_OP_HASH_BLOCK_BITMAP - #define FDB_TBL_RD_OP_HASH_BLOCK_BITMAP_OFFSET 8 - #define FDB_TBL_RD_OP_HASH_BLOCK_BITMAP_LEN 2 - #define FDB_TBL_RD_OP_HASH_BLOCK_BITMAP_DEFAULT 0x0 - /*[field] OP_MODE*/ - #define FDB_TBL_RD_OP_OP_MODE - #define FDB_TBL_RD_OP_OP_MODE_OFFSET 10 - #define FDB_TBL_RD_OP_OP_MODE_LEN 1 - #define FDB_TBL_RD_OP_OP_MODE_DEFAULT 0x0 - /*[field] ENTRY_INDEX*/ - #define FDB_TBL_RD_OP_ENTRY_INDEX - #define FDB_TBL_RD_OP_ENTRY_INDEX_OFFSET 11 - #define FDB_TBL_RD_OP_ENTRY_INDEX_LEN 11 - #define FDB_TBL_RD_OP_ENTRY_INDEX_DEFAULT 0x0 - -struct fdb_tbl_rd_op { - a_uint32_t cmd_id:4; - a_uint32_t byp_rslt_en:1; - a_uint32_t op_type:3; - a_uint32_t hash_block_bitmap:2; - a_uint32_t op_mode:1; - a_uint32_t entry_index:11; - a_uint32_t _reserved0:10; -}; - -union fdb_tbl_rd_op_u { - a_uint32_t val; - struct fdb_tbl_rd_op bf; -}; - -/*[register] FDB_TBL_OP_RSLT*/ -#define FDB_TBL_OP_RSLT -#define FDB_TBL_OP_RSLT_ADDRESS 0x20 -#define FDB_TBL_OP_RSLT_NUM 1 -#define FDB_TBL_OP_RSLT_INC 0x4 -#define FDB_TBL_OP_RSLT_TYPE REG_TYPE_RO -#define FDB_TBL_OP_RSLT_DEFAULT 0x0 - /*[field] CMD_ID*/ - #define FDB_TBL_OP_RSLT_CMD_ID - #define FDB_TBL_OP_RSLT_CMD_ID_OFFSET 0 - #define FDB_TBL_OP_RSLT_CMD_ID_LEN 4 - #define FDB_TBL_OP_RSLT_CMD_ID_DEFAULT 0x0 - /*[field] OP_RSLT*/ - #define FDB_TBL_OP_RSLT_OP_RSLT - #define FDB_TBL_OP_RSLT_OP_RSLT_OFFSET 4 - #define FDB_TBL_OP_RSLT_OP_RSLT_LEN 1 - #define FDB_TBL_OP_RSLT_OP_RSLT_DEFAULT 0x0 - /*[field] VALID_CNT*/ - #define FDB_TBL_OP_RSLT_VALID_CNT - #define FDB_TBL_OP_RSLT_VALID_CNT_OFFSET 5 - #define FDB_TBL_OP_RSLT_VALID_CNT_LEN 4 - #define FDB_TBL_OP_RSLT_VALID_CNT_DEFAULT 0x0 - /*[field] ENTRY_INDEX*/ - #define FDB_TBL_OP_RSLT_ENTRY_INDEX - #define FDB_TBL_OP_RSLT_ENTRY_INDEX_OFFSET 9 - #define FDB_TBL_OP_RSLT_ENTRY_INDEX_LEN 11 - #define FDB_TBL_OP_RSLT_ENTRY_INDEX_DEFAULT 0x0 - -struct fdb_tbl_op_rslt { - a_uint32_t cmd_id:4; - a_uint32_t op_rslt:1; - a_uint32_t valid_cnt:4; - a_uint32_t entry_index:11; - a_uint32_t _reserved0:12; -}; - -union fdb_tbl_op_rslt_u { - a_uint32_t val; - struct fdb_tbl_op_rslt bf; -}; - -/*[register] FDB_TBL_RD_OP_RSLT*/ -#define FDB_TBL_RD_OP_RSLT -#define FDB_TBL_RD_OP_RSLT_ADDRESS 0x30 -#define FDB_TBL_RD_OP_RSLT_NUM 1 -#define FDB_TBL_RD_OP_RSLT_INC 0x4 -#define FDB_TBL_RD_OP_RSLT_TYPE REG_TYPE_RO -#define FDB_TBL_RD_OP_RSLT_DEFAULT 0x0 - /*[field] CMD_ID*/ - #define FDB_TBL_RD_OP_RSLT_CMD_ID - #define FDB_TBL_RD_OP_RSLT_CMD_ID_OFFSET 0 - #define FDB_TBL_RD_OP_RSLT_CMD_ID_LEN 4 - #define FDB_TBL_RD_OP_RSLT_CMD_ID_DEFAULT 0x0 - /*[field] OP_RSLT*/ - #define FDB_TBL_RD_OP_RSLT_OP_RSLT - #define FDB_TBL_RD_OP_RSLT_OP_RSLT_OFFSET 4 - #define FDB_TBL_RD_OP_RSLT_OP_RSLT_LEN 1 - #define FDB_TBL_RD_OP_RSLT_OP_RSLT_DEFAULT 0x0 - /*[field] VALID_CNT*/ - #define FDB_TBL_RD_OP_RSLT_VALID_CNT - #define FDB_TBL_RD_OP_RSLT_VALID_CNT_OFFSET 5 - #define FDB_TBL_RD_OP_RSLT_VALID_CNT_LEN 4 - #define FDB_TBL_RD_OP_RSLT_VALID_CNT_DEFAULT 0x0 - /*[field] ENTRY_INDEX*/ - #define FDB_TBL_RD_OP_RSLT_ENTRY_INDEX - #define FDB_TBL_RD_OP_RSLT_ENTRY_INDEX_OFFSET 9 - #define FDB_TBL_RD_OP_RSLT_ENTRY_INDEX_LEN 11 - #define FDB_TBL_RD_OP_RSLT_ENTRY_INDEX_DEFAULT 0x0 - -struct fdb_tbl_rd_op_rslt { - a_uint32_t cmd_id:4; - a_uint32_t op_rslt:1; - a_uint32_t valid_cnt:4; - a_uint32_t entry_index:11; - a_uint32_t _reserved0:12; -}; - -union fdb_tbl_rd_op_rslt_u { - a_uint32_t val; - struct fdb_tbl_rd_op_rslt bf; -}; - -/*[register] AGE_TIMER*/ -#define AGE_TIMER -#define AGE_TIMER_ADDRESS 0x34 -#define AGE_TIMER_NUM 1 -#define AGE_TIMER_INC 0x4 -#define AGE_TIMER_TYPE REG_TYPE_RW -#define AGE_TIMER_DEFAULT 0x0 - /*[field] AGE_VAL*/ - #define AGE_TIMER_AGE_VAL - #define AGE_TIMER_AGE_VAL_OFFSET 0 - #define AGE_TIMER_AGE_VAL_LEN 20 - #define AGE_TIMER_AGE_VAL_DEFAULT 0x0 - -struct age_timer { - a_uint32_t age_val:20; - a_uint32_t _reserved0:12; -}; - -union age_timer_u { - a_uint32_t val; - struct age_timer bf; -}; - -/*[register] L2_GLOBAL_CONF*/ -#define L2_GLOBAL_CONF -#define L2_GLOBAL_CONF_ADDRESS 0x38 -#define L2_GLOBAL_CONF_NUM 1 -#define L2_GLOBAL_CONF_INC 0x4 -#define L2_GLOBAL_CONF_TYPE REG_TYPE_RW -#define L2_GLOBAL_CONF_DEFAULT 0xc0 - /*[field] FDB_HASH_MODE_0*/ - #define L2_GLOBAL_CONF_FDB_HASH_MODE_0 - #define L2_GLOBAL_CONF_FDB_HASH_MODE_0_OFFSET 0 - #define L2_GLOBAL_CONF_FDB_HASH_MODE_0_LEN 2 - #define L2_GLOBAL_CONF_FDB_HASH_MODE_0_DEFAULT 0x0 - /*[field] FDB_HASH_MODE_1*/ - #define L2_GLOBAL_CONF_FDB_HASH_MODE_1 - #define L2_GLOBAL_CONF_FDB_HASH_MODE_1_OFFSET 2 - #define L2_GLOBAL_CONF_FDB_HASH_MODE_1_LEN 2 - #define L2_GLOBAL_CONF_FDB_HASH_MODE_1_DEFAULT 0x0 - /*[field] FDB_HASH_FULL_FWD_CMD*/ - #define L2_GLOBAL_CONF_FDB_HASH_FULL_FWD_CMD - #define L2_GLOBAL_CONF_FDB_HASH_FULL_FWD_CMD_OFFSET 4 - #define L2_GLOBAL_CONF_FDB_HASH_FULL_FWD_CMD_LEN 2 - #define L2_GLOBAL_CONF_FDB_HASH_FULL_FWD_CMD_DEFAULT 0x0 - /*[field] LRN_EN*/ - #define L2_GLOBAL_CONF_LRN_EN - #define L2_GLOBAL_CONF_LRN_EN_OFFSET 6 - #define L2_GLOBAL_CONF_LRN_EN_LEN 1 - #define L2_GLOBAL_CONF_LRN_EN_DEFAULT 0x1 - /*[field] AGE_EN*/ - #define L2_GLOBAL_CONF_AGE_EN - #define L2_GLOBAL_CONF_AGE_EN_OFFSET 7 - #define L2_GLOBAL_CONF_AGE_EN_LEN 1 - #define L2_GLOBAL_CONF_AGE_EN_DEFAULT 0x1 - /*[field] LRN_CTRL_MODE*/ - #define L2_GLOBAL_CONF_LRN_CTRL_MODE - #define L2_GLOBAL_CONF_LRN_CTRL_MODE_OFFSET 8 - #define L2_GLOBAL_CONF_LRN_CTRL_MODE_LEN 1 - #define L2_GLOBAL_CONF_LRN_CTRL_MODE_DEFAULT 0x0 - /*[field] AGE_CTRL_MODE*/ - #define L2_GLOBAL_CONF_AGE_CTRL_MODE - #define L2_GLOBAL_CONF_AGE_CTRL_MODE_OFFSET 9 - #define L2_GLOBAL_CONF_AGE_CTRL_MODE_LEN 1 - #define L2_GLOBAL_CONF_AGE_CTRL_MODE_DEFAULT 0x0 - /*[field] FAILOVER_EN*/ - #define L2_GLOBAL_CONF_FAILOVER_EN - #define L2_GLOBAL_CONF_FAILOVER_EN_OFFSET 10 - #define L2_GLOBAL_CONF_FAILOVER_EN_LEN 1 - #define L2_GLOBAL_CONF_FAILOVER_EN_DEFAULT 0x0 - /*[field] SERVICE_CODE_LOOP*/ - #define L2_GLOBAL_CONF_SERVICE_CODE_LOOP - #define L2_GLOBAL_CONF_SERVICE_CODE_LOOP_OFFSET 11 - #define L2_GLOBAL_CONF_SERVICE_CODE_LOOP_LEN 1 - #define L2_GLOBAL_CONF_SERVICE_CODE_LOOP_DEFAULT 0x0 - -struct l2_global_conf { - a_uint32_t fdb_hash_mode_0:2; - a_uint32_t fdb_hash_mode_1:2; - a_uint32_t fdb_hash_full_fwd_cmd:2; - a_uint32_t lrn_en:1; - a_uint32_t age_en:1; - a_uint32_t lrn_ctrl_mode:1; - a_uint32_t age_ctrl_mode:1; - a_uint32_t failover_en:1; - a_uint32_t service_code_loop:1; - a_uint32_t l2_flow_copy_escape:1; - a_uint32_t _reserved0:19; -}; - -union l2_global_conf_u { - a_uint32_t val; - struct l2_global_conf bf; -}; - -/*[register] L2_DBGCNT_CMD*/ -#define L2_DBGCNT_CMD -#define L2_DBGCNT_CMD_ADDRESS 0x44 -#define L2_DBGCNT_CMD_NUM 1 -#define L2_DBGCNT_CMD_INC 0x4 -#define L2_DBGCNT_CMD_TYPE REG_TYPE_RW -#define L2_DBGCNT_CMD_DEFAULT 0x0 - /*[field] ADDR*/ - #define L2_DBGCNT_CMD_ADDR - #define L2_DBGCNT_CMD_ADDR_OFFSET 0 - #define L2_DBGCNT_CMD_ADDR_LEN 8 - #define L2_DBGCNT_CMD_ADDR_DEFAULT 0x0 - /*[field] TYPE*/ - #define L2_DBGCNT_CMD_TYPE_F - #define L2_DBGCNT_CMD_TYPE_F_OFFSET 8 - #define L2_DBGCNT_CMD_TYPE_F_LEN 2 - #define L2_DBGCNT_CMD_TYPE_F_DEFAULT 0x0 - -struct l2_dbgcnt_cmd { - a_uint32_t addr:8; - a_uint32_t type:2; - a_uint32_t _reserved0:22; -}; - -union l2_dbgcnt_cmd_u { - a_uint32_t val; - struct l2_dbgcnt_cmd bf; -}; - -/*[register] L2_DBGCNT_RDATA*/ -#define L2_DBGCNT_RDATA -#define L2_DBGCNT_RDATA_ADDRESS 0x48 -#define L2_DBGCNT_RDATA_NUM 1 -#define L2_DBGCNT_RDATA_INC 0x4 -#define L2_DBGCNT_RDATA_TYPE REG_TYPE_RO -#define L2_DBGCNT_RDATA_DEFAULT 0x0 - /*[field] DATA*/ - #define L2_DBGCNT_RDATA_DATA - #define L2_DBGCNT_RDATA_DATA_OFFSET 0 - #define L2_DBGCNT_RDATA_DATA_LEN 32 - #define L2_DBGCNT_RDATA_DATA_DEFAULT 0x0 - -struct l2_dbgcnt_rdata { - a_uint32_t data:32; -}; - -union l2_dbgcnt_rdata_u { - a_uint32_t val; - struct l2_dbgcnt_rdata bf; -}; - -/*[register] L2_DBGCNT_WDATA*/ -#define L2_DBGCNT_WDATA -#define L2_DBGCNT_WDATA_ADDRESS 0x4c -#define L2_DBGCNT_WDATA_NUM 1 -#define L2_DBGCNT_WDATA_INC 0x4 -#define L2_DBGCNT_WDATA_TYPE REG_TYPE_RW -#define L2_DBGCNT_WDATA_DEFAULT 0x0 - /*[field] DATA*/ - #define L2_DBGCNT_WDATA_DATA - #define L2_DBGCNT_WDATA_DATA_OFFSET 0 - #define L2_DBGCNT_WDATA_DATA_LEN 32 - #define L2_DBGCNT_WDATA_DATA_DEFAULT 0x0 - -struct l2_dbgcnt_wdata { - a_uint32_t data:32; -}; - -union l2_dbgcnt_wdata_u { - a_uint32_t val; - struct l2_dbgcnt_wdata bf; -}; - -/*[register] FDB_TBL_RD_OP_RSLT_DATA0*/ -#define FDB_TBL_RD_OP_RSLT_DATA0 -#define FDB_TBL_RD_OP_RSLT_DATA0_ADDRESS 0x200 -#define FDB_TBL_RD_OP_RSLT_DATA0_NUM 1 -#define FDB_TBL_RD_OP_RSLT_DATA0_INC 0x10 -#define FDB_TBL_RD_OP_RSLT_DATA0_TYPE REG_TYPE_RO -#define FDB_TBL_RD_OP_RSLT_DATA0_DEFAULT 0x0 - /*[field] DATA*/ - #define FDB_TBL_RD_OP_RSLT_DATA0_DATA - #define FDB_TBL_RD_OP_RSLT_DATA0_DATA_OFFSET 0 - #define FDB_TBL_RD_OP_RSLT_DATA0_DATA_LEN 32 - #define FDB_TBL_RD_OP_RSLT_DATA0_DATA_DEFAULT 0x0 - -struct fdb_tbl_rd_op_rslt_data0 { - a_uint32_t data:32; -}; - -union fdb_tbl_rd_op_rslt_data0_u { - a_uint32_t val; - struct fdb_tbl_rd_op_rslt_data0 bf; -}; - -/*[register] FDB_TBL_RD_OP_RSLT_DATA1*/ -#define FDB_TBL_RD_OP_RSLT_DATA1 -#define FDB_TBL_RD_OP_RSLT_DATA1_ADDRESS 0x204 -#define FDB_TBL_RD_OP_RSLT_DATA1_NUM 1 -#define FDB_TBL_RD_OP_RSLT_DATA1_INC 0x10 -#define FDB_TBL_RD_OP_RSLT_DATA1_TYPE REG_TYPE_RO -#define FDB_TBL_RD_OP_RSLT_DATA1_DEFAULT 0x0 - /*[field] DATA*/ - #define FDB_TBL_RD_OP_RSLT_DATA1_DATA - #define FDB_TBL_RD_OP_RSLT_DATA1_DATA_OFFSET 0 - #define FDB_TBL_RD_OP_RSLT_DATA1_DATA_LEN 32 - #define FDB_TBL_RD_OP_RSLT_DATA1_DATA_DEFAULT 0x0 - -struct fdb_tbl_rd_op_rslt_data1 { - a_uint32_t data:32; -}; - -union fdb_tbl_rd_op_rslt_data1_u { - a_uint32_t val; - struct fdb_tbl_rd_op_rslt_data1 bf; -}; - -/*[register] FDB_TBL_RD_OP_RSLT_DATA2*/ -#define FDB_TBL_RD_OP_RSLT_DATA2 -#define FDB_TBL_RD_OP_RSLT_DATA2_ADDRESS 0x208 -#define FDB_TBL_RD_OP_RSLT_DATA2_NUM 1 -#define FDB_TBL_RD_OP_RSLT_DATA2_INC 0x10 -#define FDB_TBL_RD_OP_RSLT_DATA2_TYPE REG_TYPE_RO -#define FDB_TBL_RD_OP_RSLT_DATA2_DEFAULT 0x0 - /*[field] DATA*/ - #define FDB_TBL_RD_OP_RSLT_DATA2_DATA - #define FDB_TBL_RD_OP_RSLT_DATA2_DATA_OFFSET 0 - #define FDB_TBL_RD_OP_RSLT_DATA2_DATA_LEN 32 - #define FDB_TBL_RD_OP_RSLT_DATA2_DATA_DEFAULT 0x0 - -struct fdb_tbl_rd_op_rslt_data2 { - a_uint32_t data:32; -}; - -union fdb_tbl_rd_op_rslt_data2_u { - a_uint32_t val; - struct fdb_tbl_rd_op_rslt_data2 bf; -}; - -/*[register] FDB_TBL_OP_DATA0*/ -#define FDB_TBL_OP_DATA0 -#define FDB_TBL_OP_DATA0_ADDRESS 0x230 -#define FDB_TBL_OP_DATA0_NUM 1 -#define FDB_TBL_OP_DATA0_INC 0x10 -#define FDB_TBL_OP_DATA0_TYPE REG_TYPE_RW -#define FDB_TBL_OP_DATA0_DEFAULT 0x0 - /*[field] DATA*/ - #define FDB_TBL_OP_DATA0_DATA - #define FDB_TBL_OP_DATA0_DATA_OFFSET 0 - #define FDB_TBL_OP_DATA0_DATA_LEN 32 - #define FDB_TBL_OP_DATA0_DATA_DEFAULT 0x0 - -struct fdb_tbl_op_data0 { - a_uint32_t data:32; -}; - -union fdb_tbl_op_data0_u { - a_uint32_t val; - struct fdb_tbl_op_data0 bf; -}; - -/*[register] FDB_TBL_OP_DATA1*/ -#define FDB_TBL_OP_DATA1 -#define FDB_TBL_OP_DATA1_ADDRESS 0x234 -#define FDB_TBL_OP_DATA1_NUM 1 -#define FDB_TBL_OP_DATA1_INC 0x10 -#define FDB_TBL_OP_DATA1_TYPE REG_TYPE_RW -#define FDB_TBL_OP_DATA1_DEFAULT 0x0 - /*[field] DATA*/ - #define FDB_TBL_OP_DATA1_DATA - #define FDB_TBL_OP_DATA1_DATA_OFFSET 0 - #define FDB_TBL_OP_DATA1_DATA_LEN 32 - #define FDB_TBL_OP_DATA1_DATA_DEFAULT 0x0 - -struct fdb_tbl_op_data1 { - a_uint32_t data:32; -}; - -union fdb_tbl_op_data1_u { - a_uint32_t val; - struct fdb_tbl_op_data1 bf; -}; - -/*[register] FDB_TBL_OP_DATA2*/ -#define FDB_TBL_OP_DATA2 -#define FDB_TBL_OP_DATA2_ADDRESS 0x238 -#define FDB_TBL_OP_DATA2_NUM 1 -#define FDB_TBL_OP_DATA2_INC 0x10 -#define FDB_TBL_OP_DATA2_TYPE REG_TYPE_RW -#define FDB_TBL_OP_DATA2_DEFAULT 0x0 - /*[field] DATA*/ - #define FDB_TBL_OP_DATA2_DATA - #define FDB_TBL_OP_DATA2_DATA_OFFSET 0 - #define FDB_TBL_OP_DATA2_DATA_LEN 32 - #define FDB_TBL_OP_DATA2_DATA_DEFAULT 0x0 - -struct fdb_tbl_op_data2 { - a_uint32_t data:32; -}; - -union fdb_tbl_op_data2_u { - a_uint32_t val; - struct fdb_tbl_op_data2 bf; -}; - -/*[register] FDB_TBL_RD_OP_DATA0*/ -#define FDB_TBL_RD_OP_DATA0 -#define FDB_TBL_RD_OP_DATA0_ADDRESS 0x260 -#define FDB_TBL_RD_OP_DATA0_NUM 1 -#define FDB_TBL_RD_OP_DATA0_INC 0x10 -#define FDB_TBL_RD_OP_DATA0_TYPE REG_TYPE_RW -#define FDB_TBL_RD_OP_DATA0_DEFAULT 0x0 - /*[field] DATA*/ - #define FDB_TBL_RD_OP_DATA0_DATA - #define FDB_TBL_RD_OP_DATA0_DATA_OFFSET 0 - #define FDB_TBL_RD_OP_DATA0_DATA_LEN 32 - #define FDB_TBL_RD_OP_DATA0_DATA_DEFAULT 0x0 - -struct fdb_tbl_rd_op_data0 { - a_uint32_t data:32; -}; - -union fdb_tbl_rd_op_data0_u { - a_uint32_t val; - struct fdb_tbl_rd_op_data0 bf; -}; - -/*[register] FDB_TBL_RD_OP_DATA1*/ -#define FDB_TBL_RD_OP_DATA1 -#define FDB_TBL_RD_OP_DATA1_ADDRESS 0x264 -#define FDB_TBL_RD_OP_DATA1_NUM 1 -#define FDB_TBL_RD_OP_DATA1_INC 0x10 -#define FDB_TBL_RD_OP_DATA1_TYPE REG_TYPE_RW -#define FDB_TBL_RD_OP_DATA1_DEFAULT 0x0 - /*[field] DATA*/ - #define FDB_TBL_RD_OP_DATA1_DATA - #define FDB_TBL_RD_OP_DATA1_DATA_OFFSET 0 - #define FDB_TBL_RD_OP_DATA1_DATA_LEN 32 - #define FDB_TBL_RD_OP_DATA1_DATA_DEFAULT 0x0 - -struct fdb_tbl_rd_op_data1 { - a_uint32_t data:32; -}; - -union fdb_tbl_rd_op_data1_u { - a_uint32_t val; - struct fdb_tbl_rd_op_data1 bf; -}; - -/*[register] FDB_TBL_RD_OP_DATA2*/ -#define FDB_TBL_RD_OP_DATA2 -#define FDB_TBL_RD_OP_DATA2_ADDRESS 0x268 -#define FDB_TBL_RD_OP_DATA2_NUM 1 -#define FDB_TBL_RD_OP_DATA2_INC 0x10 -#define FDB_TBL_RD_OP_DATA2_TYPE REG_TYPE_RW -#define FDB_TBL_RD_OP_DATA2_DEFAULT 0x0 - /*[field] DATA*/ - #define FDB_TBL_RD_OP_DATA2_DATA - #define FDB_TBL_RD_OP_DATA2_DATA_OFFSET 0 - #define FDB_TBL_RD_OP_DATA2_DATA_LEN 32 - #define FDB_TBL_RD_OP_DATA2_DATA_DEFAULT 0x0 - -struct fdb_tbl_rd_op_data2 { - a_uint32_t data:32; -}; - -union fdb_tbl_rd_op_data2_u { - a_uint32_t val; - struct fdb_tbl_rd_op_data2 bf; -}; - -/*[register] PORT_BRIDGE_CTRL*/ -#define PORT_BRIDGE_CTRL -#define PORT_BRIDGE_CTRL_ADDRESS 0x300 -#define PORT_BRIDGE_CTRL_NUM 8 -#define PORT_BRIDGE_CTRL_INC 0x4 -#define PORT_BRIDGE_CTRL_TYPE REG_TYPE_RW -#define PORT_BRIDGE_CTRL_DEFAULT 0x2ff09 - /*[field] NEW_ADDR_LRN_EN*/ - #define PORT_BRIDGE_CTRL_NEW_ADDR_LRN_EN - #define PORT_BRIDGE_CTRL_NEW_ADDR_LRN_EN_OFFSET 0 - #define PORT_BRIDGE_CTRL_NEW_ADDR_LRN_EN_LEN 1 - #define PORT_BRIDGE_CTRL_NEW_ADDR_LRN_EN_DEFAULT 0x1 - /*[field] NEW_ADDR_FWD_CMD*/ - #define PORT_BRIDGE_CTRL_NEW_ADDR_FWD_CMD - #define PORT_BRIDGE_CTRL_NEW_ADDR_FWD_CMD_OFFSET 1 - #define PORT_BRIDGE_CTRL_NEW_ADDR_FWD_CMD_LEN 2 - #define PORT_BRIDGE_CTRL_NEW_ADDR_FWD_CMD_DEFAULT 0x0 - /*[field] STATION_MOVE_LRN_EN*/ - #define PORT_BRIDGE_CTRL_STATION_MOVE_LRN_EN - #define PORT_BRIDGE_CTRL_STATION_MOVE_LRN_EN_OFFSET 3 - #define PORT_BRIDGE_CTRL_STATION_MOVE_LRN_EN_LEN 1 - #define PORT_BRIDGE_CTRL_STATION_MOVE_LRN_EN_DEFAULT 0x1 - /*[field] STATION_MOVE_FWD_CMD*/ - #define PORT_BRIDGE_CTRL_STATION_MOVE_FWD_CMD - #define PORT_BRIDGE_CTRL_STATION_MOVE_FWD_CMD_OFFSET 4 - #define PORT_BRIDGE_CTRL_STATION_MOVE_FWD_CMD_LEN 2 - #define PORT_BRIDGE_CTRL_STATION_MOVE_FWD_CMD_DEFAULT 0x0 - /*[field] PORT_ISOLATION_BITMAP*/ - #define PORT_BRIDGE_CTRL_PORT_ISOLATION_BITMAP - #define PORT_BRIDGE_CTRL_PORT_ISOLATION_BITMAP_OFFSET 8 - #define PORT_BRIDGE_CTRL_PORT_ISOLATION_BITMAP_LEN 8 - #define PORT_BRIDGE_CTRL_PORT_ISOLATION_BITMAP_DEFAULT 0xff - /*[field] TXMAC_EN*/ - #define PORT_BRIDGE_CTRL_TXMAC_EN - #define PORT_BRIDGE_CTRL_TXMAC_EN_OFFSET 16 - #define PORT_BRIDGE_CTRL_TXMAC_EN_LEN 1 - #define PORT_BRIDGE_CTRL_TXMAC_EN_DEFAULT 0x0 - /*[field] PROMISC_EN*/ - #define PORT_BRIDGE_CTRL_PROMISC_EN - #define PORT_BRIDGE_CTRL_PROMISC_EN_OFFSET 17 - #define PORT_BRIDGE_CTRL_PROMISC_EN_LEN 1 - #define PORT_BRIDGE_CTRL_PROMISC_EN_DEFAULT 0x1 - -struct port_bridge_ctrl { - a_uint32_t new_addr_lrn_en:1; - a_uint32_t new_addr_fwd_cmd:2; - a_uint32_t station_move_lrn_en:1; - a_uint32_t station_move_fwd_cmd:2; - a_uint32_t _reserved0:2; - a_uint32_t port_isolation_bitmap:8; - a_uint32_t txmac_en:1; - a_uint32_t promisc_en:1; - a_uint32_t _reserved1:14; -}; - -union port_bridge_ctrl_u { - a_uint32_t val; - struct port_bridge_ctrl bf; -}; - -/*[register] PORT_LRN_LIMIT_CTRL*/ -#define PORT_LRN_LIMIT_CTRL -#define PORT_LRN_LIMIT_CTRL_ADDRESS 0x400 -#define PORT_LRN_LIMIT_CTRL_NUM 8 -#define PORT_LRN_LIMIT_CTRL_INC 0x4 -#define PORT_LRN_LIMIT_CTRL_TYPE REG_TYPE_RW -#define PORT_LRN_LIMIT_CTRL_DEFAULT 0x1800 - /*[field] LRN_LMT_CNT*/ - #define PORT_LRN_LIMIT_CTRL_LRN_LMT_CNT - #define PORT_LRN_LIMIT_CTRL_LRN_LMT_CNT_OFFSET 0 - #define PORT_LRN_LIMIT_CTRL_LRN_LMT_CNT_LEN 12 - #define PORT_LRN_LIMIT_CTRL_LRN_LMT_CNT_DEFAULT 0x800 - /*[field] LRN_LMT_EN*/ - #define PORT_LRN_LIMIT_CTRL_LRN_LMT_EN - #define PORT_LRN_LIMIT_CTRL_LRN_LMT_EN_OFFSET 12 - #define PORT_LRN_LIMIT_CTRL_LRN_LMT_EN_LEN 1 - #define PORT_LRN_LIMIT_CTRL_LRN_LMT_EN_DEFAULT 0x1 - /*[field] LRN_LMT_EXCEED_FWD*/ - #define PORT_LRN_LIMIT_CTRL_LRN_LMT_EXCEED_FWD - #define PORT_LRN_LIMIT_CTRL_LRN_LMT_EXCEED_FWD_OFFSET 13 - #define PORT_LRN_LIMIT_CTRL_LRN_LMT_EXCEED_FWD_LEN 2 - #define PORT_LRN_LIMIT_CTRL_LRN_LMT_EXCEED_FWD_DEFAULT 0x0 - -struct port_lrn_limit_ctrl { - a_uint32_t lrn_lmt_cnt:12; - a_uint32_t lrn_lmt_en:1; - a_uint32_t lrn_lmt_exceed_fwd:2; - a_uint32_t _reserved0:17; -}; - -union port_lrn_limit_ctrl_u { - a_uint32_t val; - struct port_lrn_limit_ctrl bf; -}; - -/*[register] PORT_LRN_LIMIT_COUNTER*/ -#define PORT_LRN_LIMIT_COUNTER -#define PORT_LRN_LIMIT_COUNTER_ADDRESS 0x500 -#define PORT_LRN_LIMIT_COUNTER_NUM 8 -#define PORT_LRN_LIMIT_COUNTER_INC 0x4 -#define PORT_LRN_LIMIT_COUNTER_TYPE REG_TYPE_RO -#define PORT_LRN_LIMIT_COUNTER_DEFAULT 0x0 - /*[field] LRN_CNT*/ - #define PORT_LRN_LIMIT_COUNTER_LRN_CNT - #define PORT_LRN_LIMIT_COUNTER_LRN_CNT_OFFSET 0 - #define PORT_LRN_LIMIT_COUNTER_LRN_CNT_LEN 12 - #define PORT_LRN_LIMIT_COUNTER_LRN_CNT_DEFAULT 0x0 - -struct port_lrn_limit_counter { - a_uint32_t lrn_cnt:12; - a_uint32_t _reserved0:20; -}; - -union port_lrn_limit_counter_u { - a_uint32_t val; - struct port_lrn_limit_counter bf; -}; - -/*[table] RFDB_TBL*/ -#define RFDB_TBL -#define RFDB_TBL_ADDRESS 0x1000 -#define RFDB_TBL_NUM 32 -#define RFDB_TBL_INC 0x8 -#define RFDB_TBL_TYPE REG_TYPE_RW -#define RFDB_TBL_DEFAULT 0x0 - /*[field] MAC_ADDR*/ - #define RFDB_TBL_MAC_ADDR - #define RFDB_TBL_MAC_ADDR_OFFSET 0 - #define RFDB_TBL_MAC_ADDR_LEN 48 - #define RFDB_TBL_MAC_ADDR_DEFAULT 0x0 - /*[field] VALID*/ - #define RFDB_TBL_VALID - #define RFDB_TBL_VALID_OFFSET 48 - #define RFDB_TBL_VALID_LEN 1 - #define RFDB_TBL_VALID_DEFAULT 0x0 - -struct rfdb_tbl { - a_uint32_t mac_addr_0:32; - a_uint32_t mac_addr_1:16; - a_uint32_t valid:1; - a_uint32_t _reserved0:15; -}; - -union rfdb_tbl_u { - a_uint32_t val[2]; - struct rfdb_tbl bf; -}; - -/*[table] FDB_TBL*/ -#define FDB_TBL -#define FDB_TBL_ADDRESS 0x10000 -#define FDB_TBL_NUM 2048 -#define FDB_TBL_INC 0x10 -#define FDB_TBL_TYPE REG_TYPE_RW -#define FDB_TBL_DEFAULT 0x0 - /*[field] MAC_ADDR*/ - #define FDB_TBL_MAC_ADDR - #define FDB_TBL_MAC_ADDR_OFFSET 0 - #define FDB_TBL_MAC_ADDR_LEN 48 - #define FDB_TBL_MAC_ADDR_DEFAULT 0x0 - /*[field] ENTRY_VALID*/ - #define FDB_TBL_ENTRY_VALID - #define FDB_TBL_ENTRY_VALID_OFFSET 48 - #define FDB_TBL_ENTRY_VALID_LEN 1 - #define FDB_TBL_ENTRY_VALID_DEFAULT 0x0 - /*[field] LOOKUP_VALID*/ - #define FDB_TBL_LOOKUP_VALID - #define FDB_TBL_LOOKUP_VALID_OFFSET 49 - #define FDB_TBL_LOOKUP_VALID_LEN 1 - #define FDB_TBL_LOOKUP_VALID_DEFAULT 0x0 - /*[field] VSI*/ - #define FDB_TBL_VSI - #define FDB_TBL_VSI_OFFSET 50 - #define FDB_TBL_VSI_LEN 5 - #define FDB_TBL_VSI_DEFAULT 0x0 - /*[field] DST_INFO*/ - #define FDB_TBL_DST_INFO - #define FDB_TBL_DST_INFO_OFFSET 55 - #define FDB_TBL_DST_INFO_LEN 14 - #define FDB_TBL_DST_INFO_DEFAULT 0x0 - /*[field] SA_CMD*/ - #define FDB_TBL_SA_CMD - #define FDB_TBL_SA_CMD_OFFSET 69 - #define FDB_TBL_SA_CMD_LEN 2 - #define FDB_TBL_SA_CMD_DEFAULT 0x0 - /*[field] DA_CMD*/ - #define FDB_TBL_DA_CMD - #define FDB_TBL_DA_CMD_OFFSET 71 - #define FDB_TBL_DA_CMD_LEN 2 - #define FDB_TBL_DA_CMD_DEFAULT 0x0 - /*[field] HIT_AGE*/ - #define FDB_TBL_HIT_AGE - #define FDB_TBL_HIT_AGE_OFFSET 73 - #define FDB_TBL_HIT_AGE_LEN 2 - #define FDB_TBL_HIT_AGE_DEFAULT 0x0 - -struct fdb_tbl { - a_uint32_t mac_addr_0:32; - a_uint32_t mac_addr_1:16; - a_uint32_t entry_valid:1; - a_uint32_t lookup_valid:1; - a_uint32_t vsi:5; - a_uint32_t dst_info_0:9; - a_uint32_t dst_info_1:5; - a_uint32_t sa_cmd:2; - a_uint32_t da_cmd:2; - a_uint32_t hit_age:2; - a_uint32_t _reserved0:21; -}; - -union fdb_tbl_u { - a_uint32_t val[3]; - struct fdb_tbl bf; -}; - - - -#endif diff --git a/feeds/ipq807x/qca-ssdk/src/include/hsl/hppe/hppe_flow.h b/feeds/ipq807x/qca-ssdk/src/include/hsl/hppe/hppe_flow.h deleted file mode 100755 index 437b7200c..000000000 --- a/feeds/ipq807x/qca-ssdk/src/include/hsl/hppe/hppe_flow.h +++ /dev/null @@ -1,2264 +0,0 @@ -/* - * Copyright (c) 2016-2017, The Linux Foundation. All rights reserved. - * Permission to use, copy, modify, and/or distribute this software for - * any purpose with or without fee is hereby granted, provided that the - * above copyright notice and this permission notice appear in all copies. - * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES - * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR - * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES - * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN - * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT - * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. - */ - - -/** - * @defgroup - * @{ - */ -#ifndef _HPPE_FLOW_H_ -#define _HPPE_FLOW_H_ - -#define FLOW_CTRL1_MAX_ENTRY 3 -#define IN_FLOW_3TUPLE_TBL_MAX_ENTRY 4096 -#define IN_FLOW_IPV6_3TUPLE_TBL_MAX_ENTRY 2048 -#define IN_FLOW_IPV6_5TUPLE_TBL_MAX_ENTRY 2048 -#define IN_FLOW_TBL_MAX_ENTRY 4096 -#define EG_FLOW_TREE_MAP_TBL_MAX_ENTRY 4096 -#define IN_FLOW_CNT_TBL_MAX_ENTRY 4096 - -sw_error_t -hppe_in_flow_cnt_tbl_get( - a_uint32_t dev_id, - a_uint32_t index, - union in_flow_cnt_tbl_u *value); - -sw_error_t -hppe_in_flow_cnt_tbl_set( - a_uint32_t dev_id, - a_uint32_t index, - union in_flow_cnt_tbl_u *value); - -sw_error_t -hppe_flow_ctrl0_get( - a_uint32_t dev_id, - union flow_ctrl0_u *value); - -sw_error_t -hppe_flow_ctrl0_set( - a_uint32_t dev_id, - union flow_ctrl0_u *value); - -sw_error_t -hppe_flow_ctrl1_get( - a_uint32_t dev_id, - a_uint32_t index, - union flow_ctrl1_u *value); - -sw_error_t -hppe_flow_ctrl1_set( - a_uint32_t dev_id, - a_uint32_t index, - union flow_ctrl1_u *value); - - -sw_error_t -hppe_in_flow_tbl_op_get( - a_uint32_t dev_id, - union in_flow_tbl_op_u *value); - -sw_error_t -hppe_in_flow_tbl_op_set( - a_uint32_t dev_id, - union in_flow_tbl_op_u *value); - -sw_error_t -hppe_in_flow_host_tbl_op_get( - a_uint32_t dev_id, - union in_flow_host_tbl_op_u *value); - -sw_error_t -hppe_in_flow_host_tbl_op_set( - a_uint32_t dev_id, - union in_flow_host_tbl_op_u *value); - -sw_error_t -hppe_in_flow_tbl_op_data0_get( - a_uint32_t dev_id, - union in_flow_tbl_op_data0_u *value); - -sw_error_t -hppe_in_flow_tbl_op_data0_set( - a_uint32_t dev_id, - union in_flow_tbl_op_data0_u *value); - -sw_error_t -hppe_in_flow_tbl_op_data1_get( - a_uint32_t dev_id, - union in_flow_tbl_op_data1_u *value); - -sw_error_t -hppe_in_flow_tbl_op_data1_set( - a_uint32_t dev_id, - union in_flow_tbl_op_data1_u *value); - -sw_error_t -hppe_in_flow_tbl_op_data2_get( - a_uint32_t dev_id, - union in_flow_tbl_op_data2_u *value); - -sw_error_t -hppe_in_flow_tbl_op_data2_set( - a_uint32_t dev_id, - union in_flow_tbl_op_data2_u *value); - -sw_error_t -hppe_in_flow_tbl_op_data3_get( - a_uint32_t dev_id, - union in_flow_tbl_op_data3_u *value); - -sw_error_t -hppe_in_flow_tbl_op_data3_set( - a_uint32_t dev_id, - union in_flow_tbl_op_data3_u *value); - -sw_error_t -hppe_in_flow_tbl_op_data4_get( - a_uint32_t dev_id, - union in_flow_tbl_op_data4_u *value); - -sw_error_t -hppe_in_flow_tbl_op_data4_set( - a_uint32_t dev_id, - union in_flow_tbl_op_data4_u *value); - -sw_error_t -hppe_in_flow_tbl_op_data5_get( - a_uint32_t dev_id, - union in_flow_tbl_op_data5_u *value); - -sw_error_t -hppe_in_flow_tbl_op_data5_set( - a_uint32_t dev_id, - union in_flow_tbl_op_data5_u *value); - -sw_error_t -hppe_in_flow_tbl_op_data6_get( - a_uint32_t dev_id, - union in_flow_tbl_op_data6_u *value); - -sw_error_t -hppe_in_flow_tbl_op_data6_set( - a_uint32_t dev_id, - union in_flow_tbl_op_data6_u *value); - -sw_error_t -hppe_in_flow_tbl_op_data7_get( - a_uint32_t dev_id, - union in_flow_tbl_op_data7_u *value); - -sw_error_t -hppe_in_flow_tbl_op_data7_set( - a_uint32_t dev_id, - union in_flow_tbl_op_data7_u *value); - -sw_error_t -hppe_in_flow_tbl_op_data8_get( - a_uint32_t dev_id, - union in_flow_tbl_op_data8_u *value); - -sw_error_t -hppe_in_flow_tbl_op_data8_set( - a_uint32_t dev_id, - union in_flow_tbl_op_data8_u *value); - -sw_error_t -hppe_flow_host_tbl_op_data0_get( - a_uint32_t dev_id, - union flow_host_tbl_op_data0_u *value); - -sw_error_t -hppe_flow_host_tbl_op_data0_set( - a_uint32_t dev_id, - union flow_host_tbl_op_data0_u *value); - -sw_error_t -hppe_flow_host_tbl_op_data1_get( - a_uint32_t dev_id, - union flow_host_tbl_op_data1_u *value); - -sw_error_t -hppe_flow_host_tbl_op_data1_set( - a_uint32_t dev_id, - union flow_host_tbl_op_data1_u *value); - -sw_error_t -hppe_flow_host_tbl_op_data2_get( - a_uint32_t dev_id, - union flow_host_tbl_op_data2_u *value); - -sw_error_t -hppe_flow_host_tbl_op_data2_set( - a_uint32_t dev_id, - union flow_host_tbl_op_data2_u *value); - -sw_error_t -hppe_flow_host_tbl_op_data3_get( - a_uint32_t dev_id, - union flow_host_tbl_op_data3_u *value); - -sw_error_t -hppe_flow_host_tbl_op_data3_set( - a_uint32_t dev_id, - union flow_host_tbl_op_data3_u *value); - -sw_error_t -hppe_flow_host_tbl_op_data4_get( - a_uint32_t dev_id, - union flow_host_tbl_op_data4_u *value); - -sw_error_t -hppe_flow_host_tbl_op_data4_set( - a_uint32_t dev_id, - union flow_host_tbl_op_data4_u *value); - -sw_error_t -hppe_flow_host_tbl_op_data5_get( - a_uint32_t dev_id, - union flow_host_tbl_op_data5_u *value); - -sw_error_t -hppe_flow_host_tbl_op_data5_set( - a_uint32_t dev_id, - union flow_host_tbl_op_data5_u *value); - -sw_error_t -hppe_flow_host_tbl_op_data6_get( - a_uint32_t dev_id, - union flow_host_tbl_op_data6_u *value); - -sw_error_t -hppe_flow_host_tbl_op_data6_set( - a_uint32_t dev_id, - union flow_host_tbl_op_data6_u *value); - -sw_error_t -hppe_flow_host_tbl_op_data7_get( - a_uint32_t dev_id, - union flow_host_tbl_op_data7_u *value); - -sw_error_t -hppe_flow_host_tbl_op_data7_set( - a_uint32_t dev_id, - union flow_host_tbl_op_data7_u *value); - -sw_error_t -hppe_flow_host_tbl_op_data8_get( - a_uint32_t dev_id, - union flow_host_tbl_op_data8_u *value); - -sw_error_t -hppe_flow_host_tbl_op_data8_set( - a_uint32_t dev_id, - union flow_host_tbl_op_data8_u *value); - -sw_error_t -hppe_flow_host_tbl_op_data9_get( - a_uint32_t dev_id, - union flow_host_tbl_op_data9_u *value); - -sw_error_t -hppe_flow_host_tbl_op_data9_set( - a_uint32_t dev_id, - union flow_host_tbl_op_data9_u *value); - -sw_error_t -hppe_in_flow_tbl_op_rslt_get( - a_uint32_t dev_id, - union in_flow_tbl_op_rslt_u *value); - -sw_error_t -hppe_in_flow_tbl_op_rslt_set( - a_uint32_t dev_id, - union in_flow_tbl_op_rslt_u *value); - -sw_error_t -hppe_flow_host_tbl_op_rslt_get( - a_uint32_t dev_id, - union flow_host_tbl_op_rslt_u *value); - -sw_error_t -hppe_flow_host_tbl_op_rslt_set( - a_uint32_t dev_id, - union flow_host_tbl_op_rslt_u *value); - -sw_error_t -hppe_in_flow_tbl_rd_op_get( - a_uint32_t dev_id, - union in_flow_tbl_rd_op_u *value); - -sw_error_t -hppe_in_flow_tbl_rd_op_set( - a_uint32_t dev_id, - union in_flow_tbl_rd_op_u *value); - -sw_error_t -hppe_in_flow_host_tbl_rd_op_get( - a_uint32_t dev_id, - union in_flow_host_tbl_rd_op_u *value); - -sw_error_t -hppe_in_flow_host_tbl_rd_op_set( - a_uint32_t dev_id, - union in_flow_host_tbl_rd_op_u *value); - -sw_error_t -hppe_in_flow_tbl_rd_op_data0_get( - a_uint32_t dev_id, - union in_flow_tbl_rd_op_data0_u *value); - -sw_error_t -hppe_in_flow_tbl_rd_op_data0_set( - a_uint32_t dev_id, - union in_flow_tbl_rd_op_data0_u *value); - -sw_error_t -hppe_in_flow_tbl_rd_op_data1_get( - a_uint32_t dev_id, - union in_flow_tbl_rd_op_data1_u *value); - -sw_error_t -hppe_in_flow_tbl_rd_op_data1_set( - a_uint32_t dev_id, - union in_flow_tbl_rd_op_data1_u *value); - -sw_error_t -hppe_in_flow_tbl_rd_op_data2_get( - a_uint32_t dev_id, - union in_flow_tbl_rd_op_data2_u *value); - -sw_error_t -hppe_in_flow_tbl_rd_op_data2_set( - a_uint32_t dev_id, - union in_flow_tbl_rd_op_data2_u *value); - -sw_error_t -hppe_in_flow_tbl_rd_op_data3_get( - a_uint32_t dev_id, - union in_flow_tbl_rd_op_data3_u *value); - -sw_error_t -hppe_in_flow_tbl_rd_op_data3_set( - a_uint32_t dev_id, - union in_flow_tbl_rd_op_data3_u *value); - -sw_error_t -hppe_in_flow_tbl_rd_op_data4_get( - a_uint32_t dev_id, - union in_flow_tbl_rd_op_data4_u *value); - -sw_error_t -hppe_in_flow_tbl_rd_op_data4_set( - a_uint32_t dev_id, - union in_flow_tbl_rd_op_data4_u *value); - -sw_error_t -hppe_in_flow_tbl_rd_op_data5_get( - a_uint32_t dev_id, - union in_flow_tbl_rd_op_data5_u *value); - -sw_error_t -hppe_in_flow_tbl_rd_op_data5_set( - a_uint32_t dev_id, - union in_flow_tbl_rd_op_data5_u *value); - -sw_error_t -hppe_in_flow_tbl_rd_op_data6_get( - a_uint32_t dev_id, - union in_flow_tbl_rd_op_data6_u *value); - -sw_error_t -hppe_in_flow_tbl_rd_op_data6_set( - a_uint32_t dev_id, - union in_flow_tbl_rd_op_data6_u *value); - -sw_error_t -hppe_in_flow_tbl_rd_op_data7_get( - a_uint32_t dev_id, - union in_flow_tbl_rd_op_data7_u *value); - -sw_error_t -hppe_in_flow_tbl_rd_op_data7_set( - a_uint32_t dev_id, - union in_flow_tbl_rd_op_data7_u *value); - -sw_error_t -hppe_in_flow_tbl_rd_op_data8_get( - a_uint32_t dev_id, - union in_flow_tbl_rd_op_data8_u *value); - -sw_error_t -hppe_in_flow_tbl_rd_op_data8_set( - a_uint32_t dev_id, - union in_flow_tbl_rd_op_data8_u *value); - -sw_error_t -hppe_flow_host_tbl_rd_op_data0_get( - a_uint32_t dev_id, - union flow_host_tbl_rd_op_data0_u *value); - -sw_error_t -hppe_flow_host_tbl_rd_op_data0_set( - a_uint32_t dev_id, - union flow_host_tbl_rd_op_data0_u *value); - -sw_error_t -hppe_flow_host_tbl_rd_op_data1_get( - a_uint32_t dev_id, - union flow_host_tbl_rd_op_data1_u *value); - -sw_error_t -hppe_flow_host_tbl_rd_op_data1_set( - a_uint32_t dev_id, - union flow_host_tbl_rd_op_data1_u *value); - -sw_error_t -hppe_flow_host_tbl_rd_op_data2_get( - a_uint32_t dev_id, - union flow_host_tbl_rd_op_data2_u *value); - -sw_error_t -hppe_flow_host_tbl_rd_op_data2_set( - a_uint32_t dev_id, - union flow_host_tbl_rd_op_data2_u *value); - -sw_error_t -hppe_flow_host_tbl_rd_op_data3_get( - a_uint32_t dev_id, - union flow_host_tbl_rd_op_data3_u *value); - -sw_error_t -hppe_flow_host_tbl_rd_op_data3_set( - a_uint32_t dev_id, - union flow_host_tbl_rd_op_data3_u *value); - -sw_error_t -hppe_flow_host_tbl_rd_op_data4_get( - a_uint32_t dev_id, - union flow_host_tbl_rd_op_data4_u *value); - -sw_error_t -hppe_flow_host_tbl_rd_op_data4_set( - a_uint32_t dev_id, - union flow_host_tbl_rd_op_data4_u *value); - -sw_error_t -hppe_flow_host_tbl_rd_op_data5_get( - a_uint32_t dev_id, - union flow_host_tbl_rd_op_data5_u *value); - -sw_error_t -hppe_flow_host_tbl_rd_op_data5_set( - a_uint32_t dev_id, - union flow_host_tbl_rd_op_data5_u *value); - -sw_error_t -hppe_flow_host_tbl_rd_op_data6_get( - a_uint32_t dev_id, - union flow_host_tbl_rd_op_data6_u *value); - -sw_error_t -hppe_flow_host_tbl_rd_op_data6_set( - a_uint32_t dev_id, - union flow_host_tbl_rd_op_data6_u *value); - -sw_error_t -hppe_flow_host_tbl_rd_op_data7_get( - a_uint32_t dev_id, - union flow_host_tbl_rd_op_data7_u *value); - -sw_error_t -hppe_flow_host_tbl_rd_op_data7_set( - a_uint32_t dev_id, - union flow_host_tbl_rd_op_data7_u *value); - -sw_error_t -hppe_flow_host_tbl_rd_op_data8_get( - a_uint32_t dev_id, - union flow_host_tbl_rd_op_data8_u *value); - -sw_error_t -hppe_flow_host_tbl_rd_op_data8_set( - a_uint32_t dev_id, - union flow_host_tbl_rd_op_data8_u *value); - -sw_error_t -hppe_flow_host_tbl_rd_op_data9_get( - a_uint32_t dev_id, - union flow_host_tbl_rd_op_data9_u *value); - -sw_error_t -hppe_flow_host_tbl_rd_op_data9_set( - a_uint32_t dev_id, - union flow_host_tbl_rd_op_data9_u *value); - -sw_error_t -hppe_in_flow_tbl_rd_op_rslt_get( - a_uint32_t dev_id, - union in_flow_tbl_rd_op_rslt_u *value); - -sw_error_t -hppe_in_flow_tbl_rd_op_rslt_set( - a_uint32_t dev_id, - union in_flow_tbl_rd_op_rslt_u *value); - -sw_error_t -hppe_flow_host_tbl_rd_op_rslt_get( - a_uint32_t dev_id, - union flow_host_tbl_rd_op_rslt_u *value); - -sw_error_t -hppe_flow_host_tbl_rd_op_rslt_set( - a_uint32_t dev_id, - union flow_host_tbl_rd_op_rslt_u *value); - -sw_error_t -hppe_in_flow_tbl_rd_rslt_data0_get( - a_uint32_t dev_id, - union in_flow_tbl_rd_rslt_data0_u *value); - -sw_error_t -hppe_in_flow_tbl_rd_rslt_data0_set( - a_uint32_t dev_id, - union in_flow_tbl_rd_rslt_data0_u *value); - -sw_error_t -hppe_in_flow_tbl_rd_rslt_data1_get( - a_uint32_t dev_id, - union in_flow_tbl_rd_rslt_data1_u *value); - -sw_error_t -hppe_in_flow_tbl_rd_rslt_data1_set( - a_uint32_t dev_id, - union in_flow_tbl_rd_rslt_data1_u *value); - -sw_error_t -hppe_in_flow_tbl_rd_rslt_data2_get( - a_uint32_t dev_id, - union in_flow_tbl_rd_rslt_data2_u *value); - -sw_error_t -hppe_in_flow_tbl_rd_rslt_data2_set( - a_uint32_t dev_id, - union in_flow_tbl_rd_rslt_data2_u *value); - -sw_error_t -hppe_in_flow_tbl_rd_rslt_data3_get( - a_uint32_t dev_id, - union in_flow_tbl_rd_rslt_data3_u *value); - -sw_error_t -hppe_in_flow_tbl_rd_rslt_data3_set( - a_uint32_t dev_id, - union in_flow_tbl_rd_rslt_data3_u *value); - -sw_error_t -hppe_in_flow_tbl_rd_rslt_data4_get( - a_uint32_t dev_id, - union in_flow_tbl_rd_rslt_data4_u *value); - -sw_error_t -hppe_in_flow_tbl_rd_rslt_data4_set( - a_uint32_t dev_id, - union in_flow_tbl_rd_rslt_data4_u *value); - -sw_error_t -hppe_in_flow_tbl_rd_rslt_data5_get( - a_uint32_t dev_id, - union in_flow_tbl_rd_rslt_data5_u *value); - -sw_error_t -hppe_in_flow_tbl_rd_rslt_data5_set( - a_uint32_t dev_id, - union in_flow_tbl_rd_rslt_data5_u *value); - -sw_error_t -hppe_in_flow_tbl_rd_rslt_data6_get( - a_uint32_t dev_id, - union in_flow_tbl_rd_rslt_data6_u *value); - -sw_error_t -hppe_in_flow_tbl_rd_rslt_data6_set( - a_uint32_t dev_id, - union in_flow_tbl_rd_rslt_data6_u *value); - -sw_error_t -hppe_in_flow_tbl_rd_rslt_data7_get( - a_uint32_t dev_id, - union in_flow_tbl_rd_rslt_data7_u *value); - -sw_error_t -hppe_in_flow_tbl_rd_rslt_data7_set( - a_uint32_t dev_id, - union in_flow_tbl_rd_rslt_data7_u *value); - -sw_error_t -hppe_in_flow_tbl_rd_rslt_data8_get( - a_uint32_t dev_id, - union in_flow_tbl_rd_rslt_data8_u *value); - -sw_error_t -hppe_in_flow_tbl_rd_rslt_data8_set( - a_uint32_t dev_id, - union in_flow_tbl_rd_rslt_data8_u *value); - -sw_error_t -hppe_flow_host_tbl_rd_rslt_data0_get( - a_uint32_t dev_id, - union flow_host_tbl_rd_rslt_data0_u *value); - -sw_error_t -hppe_flow_host_tbl_rd_rslt_data0_set( - a_uint32_t dev_id, - union flow_host_tbl_rd_rslt_data0_u *value); - -sw_error_t -hppe_flow_host_tbl_rd_rslt_data1_get( - a_uint32_t dev_id, - union flow_host_tbl_rd_rslt_data1_u *value); - -sw_error_t -hppe_flow_host_tbl_rd_rslt_data1_set( - a_uint32_t dev_id, - union flow_host_tbl_rd_rslt_data1_u *value); - -sw_error_t -hppe_flow_host_tbl_rd_rslt_data2_get( - a_uint32_t dev_id, - union flow_host_tbl_rd_rslt_data2_u *value); - -sw_error_t -hppe_flow_host_tbl_rd_rslt_data2_set( - a_uint32_t dev_id, - union flow_host_tbl_rd_rslt_data2_u *value); - -sw_error_t -hppe_flow_host_tbl_rd_rslt_data3_get( - a_uint32_t dev_id, - union flow_host_tbl_rd_rslt_data3_u *value); - -sw_error_t -hppe_flow_host_tbl_rd_rslt_data3_set( - a_uint32_t dev_id, - union flow_host_tbl_rd_rslt_data3_u *value); - -sw_error_t -hppe_flow_host_tbl_rd_rslt_data4_get( - a_uint32_t dev_id, - union flow_host_tbl_rd_rslt_data4_u *value); - -sw_error_t -hppe_flow_host_tbl_rd_rslt_data4_set( - a_uint32_t dev_id, - union flow_host_tbl_rd_rslt_data4_u *value); - -sw_error_t -hppe_flow_host_tbl_rd_rslt_data5_get( - a_uint32_t dev_id, - union flow_host_tbl_rd_rslt_data5_u *value); - -sw_error_t -hppe_flow_host_tbl_rd_rslt_data5_set( - a_uint32_t dev_id, - union flow_host_tbl_rd_rslt_data5_u *value); - -sw_error_t -hppe_flow_host_tbl_rd_rslt_data6_get( - a_uint32_t dev_id, - union flow_host_tbl_rd_rslt_data6_u *value); - -sw_error_t -hppe_flow_host_tbl_rd_rslt_data6_set( - a_uint32_t dev_id, - union flow_host_tbl_rd_rslt_data6_u *value); - -sw_error_t -hppe_flow_host_tbl_rd_rslt_data7_get( - a_uint32_t dev_id, - union flow_host_tbl_rd_rslt_data7_u *value); - -sw_error_t -hppe_flow_host_tbl_rd_rslt_data7_set( - a_uint32_t dev_id, - union flow_host_tbl_rd_rslt_data7_u *value); - -sw_error_t -hppe_flow_host_tbl_rd_rslt_data8_get( - a_uint32_t dev_id, - union flow_host_tbl_rd_rslt_data8_u *value); - -sw_error_t -hppe_flow_host_tbl_rd_rslt_data8_set( - a_uint32_t dev_id, - union flow_host_tbl_rd_rslt_data8_u *value); - -sw_error_t -hppe_flow_host_tbl_rd_rslt_data9_get( - a_uint32_t dev_id, - union flow_host_tbl_rd_rslt_data9_u *value); - -sw_error_t -hppe_flow_host_tbl_rd_rslt_data9_set( - a_uint32_t dev_id, - union flow_host_tbl_rd_rslt_data9_u *value); - -sw_error_t -hppe_in_flow_3tuple_tbl_get( - a_uint32_t dev_id, - a_uint32_t index, - union in_flow_3tuple_tbl_u *value); - -sw_error_t -hppe_in_flow_3tuple_tbl_set( - a_uint32_t dev_id, - a_uint32_t index, - union in_flow_3tuple_tbl_u *value); - -sw_error_t -hppe_in_flow_ipv6_3tuple_tbl_get( - a_uint32_t dev_id, - a_uint32_t index, - union in_flow_ipv6_3tuple_tbl_u *value); - -sw_error_t -hppe_in_flow_ipv6_3tuple_tbl_set( - a_uint32_t dev_id, - a_uint32_t index, - union in_flow_ipv6_3tuple_tbl_u *value); - -sw_error_t -hppe_in_flow_ipv6_5tuple_tbl_get( - a_uint32_t dev_id, - a_uint32_t index, - union in_flow_ipv6_5tuple_tbl_u *value); - -sw_error_t -hppe_in_flow_ipv6_5tuple_tbl_set( - a_uint32_t dev_id, - a_uint32_t index, - union in_flow_ipv6_5tuple_tbl_u *value); - -sw_error_t -hppe_in_flow_tbl_get( - a_uint32_t dev_id, - a_uint32_t index, - union in_flow_tbl_u *value); - -sw_error_t -hppe_in_flow_tbl_set( - a_uint32_t dev_id, - a_uint32_t index, - union in_flow_tbl_u *value); - -sw_error_t -hppe_eg_flow_tree_map_tbl_get( - a_uint32_t dev_id, - a_uint32_t index, - union eg_flow_tree_map_tbl_u *value); - -sw_error_t -hppe_eg_flow_tree_map_tbl_set( - a_uint32_t dev_id, - a_uint32_t index, - union eg_flow_tree_map_tbl_u *value); - -sw_error_t -hppe_flow_ctrl0_flow_hash_mode_0_get( - a_uint32_t dev_id, - unsigned int *value); - -sw_error_t -hppe_flow_ctrl0_flow_hash_mode_0_set( - a_uint32_t dev_id, - unsigned int value); - -sw_error_t -hppe_flow_ctrl0_flow_age_timer_unit_get( - a_uint32_t dev_id, - unsigned int *value); - -sw_error_t -hppe_flow_ctrl0_flow_age_timer_unit_set( - a_uint32_t dev_id, - unsigned int value); - -sw_error_t -hppe_flow_ctrl0_flow_hash_mode_1_get( - a_uint32_t dev_id, - unsigned int *value); - -sw_error_t -hppe_flow_ctrl0_flow_hash_mode_1_set( - a_uint32_t dev_id, - unsigned int value); - -sw_error_t -hppe_flow_ctrl0_flow_age_timer_get( - a_uint32_t dev_id, - unsigned int *value); - -sw_error_t -hppe_flow_ctrl0_flow_age_timer_set( - a_uint32_t dev_id, - unsigned int value); - -sw_error_t -hppe_flow_ctrl0_flow_en_get( - a_uint32_t dev_id, - unsigned int *value); - -sw_error_t -hppe_flow_ctrl0_flow_en_set( - a_uint32_t dev_id, - unsigned int value); - -sw_error_t -hppe_flow_ctrl1_flow_ctl1_frag_bypass_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_flow_ctrl1_flow_ctl1_frag_bypass_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_flow_ctrl1_flow_ctl4_key_sel_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_flow_ctrl1_flow_ctl4_key_sel_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_flow_ctrl1_flow_ctl1_key_sel_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_flow_ctrl1_flow_ctl1_key_sel_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_flow_ctrl1_flow_ctl0_frag_bypass_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_flow_ctrl1_flow_ctl0_frag_bypass_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_flow_ctrl1_flow_ctl0_miss_action_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_flow_ctrl1_flow_ctl0_miss_action_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_flow_ctrl1_flow_ctl0_key_sel_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_flow_ctrl1_flow_ctl0_key_sel_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_flow_ctrl1_flow_ctl1_bypass_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_flow_ctrl1_flow_ctl1_bypass_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_flow_ctrl1_flow_ctl0_bypass_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_flow_ctrl1_flow_ctl0_bypass_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_flow_ctrl1_flow_ctl2_tcp_special_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_flow_ctrl1_flow_ctl2_tcp_special_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_flow_ctrl1_flow_ctl4_tcp_special_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_flow_ctrl1_flow_ctl4_tcp_special_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_flow_ctrl1_flow_ctl3_frag_bypass_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_flow_ctrl1_flow_ctl3_frag_bypass_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_flow_ctrl1_flow_ctl3_bypass_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_flow_ctrl1_flow_ctl3_bypass_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_flow_ctrl1_flow_ctl3_tcp_special_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_flow_ctrl1_flow_ctl3_tcp_special_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_flow_ctrl1_flow_ctl1_miss_action_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_flow_ctrl1_flow_ctl1_miss_action_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_flow_ctrl1_flow_ctl4_frag_bypass_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_flow_ctrl1_flow_ctl4_frag_bypass_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_flow_ctrl1_flow_ctl1_tcp_special_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_flow_ctrl1_flow_ctl1_tcp_special_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_flow_ctrl1_flow_ctl2_key_sel_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_flow_ctrl1_flow_ctl2_key_sel_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_flow_ctrl1_flow_ctl2_miss_action_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_flow_ctrl1_flow_ctl2_miss_action_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_flow_ctrl1_flow_ctl2_bypass_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_flow_ctrl1_flow_ctl2_bypass_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_flow_ctrl1_flow_ctl4_bypass_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_flow_ctrl1_flow_ctl4_bypass_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_flow_ctrl1_flow_ctl3_key_sel_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_flow_ctrl1_flow_ctl3_key_sel_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_flow_ctrl1_flow_ctl0_tcp_special_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_flow_ctrl1_flow_ctl0_tcp_special_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_flow_ctrl1_flow_ctl2_frag_bypass_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_flow_ctrl1_flow_ctl2_frag_bypass_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_flow_ctrl1_flow_ctl3_miss_action_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_flow_ctrl1_flow_ctl3_miss_action_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_flow_ctrl1_flow_ctl4_miss_action_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_flow_ctrl1_flow_ctl4_miss_action_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_in_flow_tbl_op_entry_index_get( - a_uint32_t dev_id, - unsigned int *value); - -sw_error_t -hppe_in_flow_tbl_op_entry_index_set( - a_uint32_t dev_id, - unsigned int value); - -sw_error_t -hppe_in_flow_tbl_op_cmd_id_get( - a_uint32_t dev_id, - unsigned int *value); - -sw_error_t -hppe_in_flow_tbl_op_cmd_id_set( - a_uint32_t dev_id, - unsigned int value); - -sw_error_t -hppe_in_flow_tbl_op_byp_rslt_en_get( - a_uint32_t dev_id, - unsigned int *value); - -sw_error_t -hppe_in_flow_tbl_op_byp_rslt_en_set( - a_uint32_t dev_id, - unsigned int value); - -sw_error_t -hppe_in_flow_tbl_op_op_mode_get( - a_uint32_t dev_id, - unsigned int *value); - -sw_error_t -hppe_in_flow_tbl_op_op_mode_set( - a_uint32_t dev_id, - unsigned int value); - -sw_error_t -hppe_in_flow_tbl_op_op_type_get( - a_uint32_t dev_id, - unsigned int *value); - -sw_error_t -hppe_in_flow_tbl_op_op_type_set( - a_uint32_t dev_id, - unsigned int value); - -sw_error_t -hppe_in_flow_tbl_op_op_host_en_get( - a_uint32_t dev_id, - unsigned int *value); - -sw_error_t -hppe_in_flow_tbl_op_op_host_en_set( - a_uint32_t dev_id, - unsigned int value); - -sw_error_t -hppe_in_flow_tbl_op_op_result_get( - a_uint32_t dev_id, - unsigned int *value); - -sw_error_t -hppe_in_flow_tbl_op_op_result_set( - a_uint32_t dev_id, - unsigned int value); - -sw_error_t -hppe_in_flow_tbl_op_busy_get( - a_uint32_t dev_id, - unsigned int *value); - -sw_error_t -hppe_in_flow_tbl_op_busy_set( - a_uint32_t dev_id, - unsigned int value); - -sw_error_t -hppe_in_flow_tbl_op_hash_block_bitmap_get( - a_uint32_t dev_id, - unsigned int *value); - -sw_error_t -hppe_in_flow_tbl_op_hash_block_bitmap_set( - a_uint32_t dev_id, - unsigned int value); - -sw_error_t -hppe_in_flow_host_tbl_op_host_entry_index_get( - a_uint32_t dev_id, - unsigned int *value); - -sw_error_t -hppe_in_flow_host_tbl_op_host_entry_index_set( - a_uint32_t dev_id, - unsigned int value); - -sw_error_t -hppe_in_flow_host_tbl_op_hash_block_bitmap_get( - a_uint32_t dev_id, - unsigned int *value); - -sw_error_t -hppe_in_flow_host_tbl_op_hash_block_bitmap_set( - a_uint32_t dev_id, - unsigned int value); - -sw_error_t -hppe_in_flow_tbl_op_data0_data_get( - a_uint32_t dev_id, - unsigned int *value); - -sw_error_t -hppe_in_flow_tbl_op_data0_data_set( - a_uint32_t dev_id, - unsigned int value); - -sw_error_t -hppe_in_flow_tbl_op_data1_data_get( - a_uint32_t dev_id, - unsigned int *value); - -sw_error_t -hppe_in_flow_tbl_op_data1_data_set( - a_uint32_t dev_id, - unsigned int value); - -sw_error_t -hppe_in_flow_tbl_op_data2_data_get( - a_uint32_t dev_id, - unsigned int *value); - -sw_error_t -hppe_in_flow_tbl_op_data2_data_set( - a_uint32_t dev_id, - unsigned int value); - -sw_error_t -hppe_in_flow_tbl_op_data3_data_get( - a_uint32_t dev_id, - unsigned int *value); - -sw_error_t -hppe_in_flow_tbl_op_data3_data_set( - a_uint32_t dev_id, - unsigned int value); - -sw_error_t -hppe_in_flow_tbl_op_data4_data_get( - a_uint32_t dev_id, - unsigned int *value); - -sw_error_t -hppe_in_flow_tbl_op_data4_data_set( - a_uint32_t dev_id, - unsigned int value); - -sw_error_t -hppe_in_flow_tbl_op_data5_data_get( - a_uint32_t dev_id, - unsigned int *value); - -sw_error_t -hppe_in_flow_tbl_op_data5_data_set( - a_uint32_t dev_id, - unsigned int value); - -sw_error_t -hppe_in_flow_tbl_op_data6_data_get( - a_uint32_t dev_id, - unsigned int *value); - -sw_error_t -hppe_in_flow_tbl_op_data6_data_set( - a_uint32_t dev_id, - unsigned int value); - -sw_error_t -hppe_in_flow_tbl_op_data7_data_get( - a_uint32_t dev_id, - unsigned int *value); - -sw_error_t -hppe_in_flow_tbl_op_data7_data_set( - a_uint32_t dev_id, - unsigned int value); - -sw_error_t -hppe_in_flow_tbl_op_data8_data_get( - a_uint32_t dev_id, - unsigned int *value); - -sw_error_t -hppe_in_flow_tbl_op_data8_data_set( - a_uint32_t dev_id, - unsigned int value); - -sw_error_t -hppe_flow_host_tbl_op_data0_data_get( - a_uint32_t dev_id, - unsigned int *value); - -sw_error_t -hppe_flow_host_tbl_op_data0_data_set( - a_uint32_t dev_id, - unsigned int value); - -sw_error_t -hppe_flow_host_tbl_op_data1_data_get( - a_uint32_t dev_id, - unsigned int *value); - -sw_error_t -hppe_flow_host_tbl_op_data1_data_set( - a_uint32_t dev_id, - unsigned int value); - -sw_error_t -hppe_flow_host_tbl_op_data2_data_get( - a_uint32_t dev_id, - unsigned int *value); - -sw_error_t -hppe_flow_host_tbl_op_data2_data_set( - a_uint32_t dev_id, - unsigned int value); - -sw_error_t -hppe_flow_host_tbl_op_data3_data_get( - a_uint32_t dev_id, - unsigned int *value); - -sw_error_t -hppe_flow_host_tbl_op_data3_data_set( - a_uint32_t dev_id, - unsigned int value); - -sw_error_t -hppe_flow_host_tbl_op_data4_data_get( - a_uint32_t dev_id, - unsigned int *value); - -sw_error_t -hppe_flow_host_tbl_op_data4_data_set( - a_uint32_t dev_id, - unsigned int value); - -sw_error_t -hppe_flow_host_tbl_op_data5_data_get( - a_uint32_t dev_id, - unsigned int *value); - -sw_error_t -hppe_flow_host_tbl_op_data5_data_set( - a_uint32_t dev_id, - unsigned int value); - -sw_error_t -hppe_flow_host_tbl_op_data6_data_get( - a_uint32_t dev_id, - unsigned int *value); - -sw_error_t -hppe_flow_host_tbl_op_data6_data_set( - a_uint32_t dev_id, - unsigned int value); - -sw_error_t -hppe_flow_host_tbl_op_data7_data_get( - a_uint32_t dev_id, - unsigned int *value); - -sw_error_t -hppe_flow_host_tbl_op_data7_data_set( - a_uint32_t dev_id, - unsigned int value); - -sw_error_t -hppe_flow_host_tbl_op_data8_data_get( - a_uint32_t dev_id, - unsigned int *value); - -sw_error_t -hppe_flow_host_tbl_op_data8_data_set( - a_uint32_t dev_id, - unsigned int value); - -sw_error_t -hppe_flow_host_tbl_op_data9_data_get( - a_uint32_t dev_id, - unsigned int *value); - -sw_error_t -hppe_flow_host_tbl_op_data9_data_set( - a_uint32_t dev_id, - unsigned int value); - -sw_error_t -hppe_in_flow_tbl_op_rslt_op_rslt_get( - a_uint32_t dev_id, - unsigned int *value); - -sw_error_t -hppe_in_flow_tbl_op_rslt_op_rslt_set( - a_uint32_t dev_id, - unsigned int value); - -sw_error_t -hppe_in_flow_tbl_op_rslt_valid_cnt_get( - a_uint32_t dev_id, - unsigned int *value); - -sw_error_t -hppe_in_flow_tbl_op_rslt_valid_cnt_set( - a_uint32_t dev_id, - unsigned int value); - -sw_error_t -hppe_in_flow_tbl_op_rslt_flow_entry_index_get( - a_uint32_t dev_id, - unsigned int *value); - -sw_error_t -hppe_in_flow_tbl_op_rslt_flow_entry_index_set( - a_uint32_t dev_id, - unsigned int value); - -sw_error_t -hppe_in_flow_tbl_op_rslt_cmd_id_get( - a_uint32_t dev_id, - unsigned int *value); - -sw_error_t -hppe_in_flow_tbl_op_rslt_cmd_id_set( - a_uint32_t dev_id, - unsigned int value); - -sw_error_t -hppe_flow_host_tbl_op_rslt_host_entry_index_get( - a_uint32_t dev_id, - unsigned int *value); - -sw_error_t -hppe_flow_host_tbl_op_rslt_host_entry_index_set( - a_uint32_t dev_id, - unsigned int value); - -sw_error_t -hppe_in_flow_tbl_rd_op_entry_index_get( - a_uint32_t dev_id, - unsigned int *value); - -sw_error_t -hppe_in_flow_tbl_rd_op_entry_index_set( - a_uint32_t dev_id, - unsigned int value); - -sw_error_t -hppe_in_flow_tbl_rd_op_cmd_id_get( - a_uint32_t dev_id, - unsigned int *value); - -sw_error_t -hppe_in_flow_tbl_rd_op_cmd_id_set( - a_uint32_t dev_id, - unsigned int value); - -sw_error_t -hppe_in_flow_tbl_rd_op_byp_rslt_en_get( - a_uint32_t dev_id, - unsigned int *value); - -sw_error_t -hppe_in_flow_tbl_rd_op_byp_rslt_en_set( - a_uint32_t dev_id, - unsigned int value); - -sw_error_t -hppe_in_flow_tbl_rd_op_op_mode_get( - a_uint32_t dev_id, - unsigned int *value); - -sw_error_t -hppe_in_flow_tbl_rd_op_op_mode_set( - a_uint32_t dev_id, - unsigned int value); - -sw_error_t -hppe_in_flow_tbl_rd_op_op_type_get( - a_uint32_t dev_id, - unsigned int *value); - -sw_error_t -hppe_in_flow_tbl_rd_op_op_type_set( - a_uint32_t dev_id, - unsigned int value); - -sw_error_t -hppe_in_flow_tbl_rd_op_op_host_en_get( - a_uint32_t dev_id, - unsigned int *value); - -sw_error_t -hppe_in_flow_tbl_rd_op_op_host_en_set( - a_uint32_t dev_id, - unsigned int value); - -sw_error_t -hppe_in_flow_tbl_rd_op_op_result_get( - a_uint32_t dev_id, - unsigned int *value); - -sw_error_t -hppe_in_flow_tbl_rd_op_op_result_set( - a_uint32_t dev_id, - unsigned int value); - -sw_error_t -hppe_in_flow_tbl_rd_op_busy_get( - a_uint32_t dev_id, - unsigned int *value); - -sw_error_t -hppe_in_flow_tbl_rd_op_busy_set( - a_uint32_t dev_id, - unsigned int value); - -sw_error_t -hppe_in_flow_tbl_rd_op_hash_block_bitmap_get( - a_uint32_t dev_id, - unsigned int *value); - -sw_error_t -hppe_in_flow_tbl_rd_op_hash_block_bitmap_set( - a_uint32_t dev_id, - unsigned int value); - -sw_error_t -hppe_in_flow_host_tbl_rd_op_host_entry_index_get( - a_uint32_t dev_id, - unsigned int *value); - -sw_error_t -hppe_in_flow_host_tbl_rd_op_host_entry_index_set( - a_uint32_t dev_id, - unsigned int value); - -sw_error_t -hppe_in_flow_host_tbl_rd_op_hash_block_bitmap_get( - a_uint32_t dev_id, - unsigned int *value); - -sw_error_t -hppe_in_flow_host_tbl_rd_op_hash_block_bitmap_set( - a_uint32_t dev_id, - unsigned int value); - -sw_error_t -hppe_in_flow_tbl_rd_op_data0_data_get( - a_uint32_t dev_id, - unsigned int *value); - -sw_error_t -hppe_in_flow_tbl_rd_op_data0_data_set( - a_uint32_t dev_id, - unsigned int value); - -sw_error_t -hppe_in_flow_tbl_rd_op_data1_data_get( - a_uint32_t dev_id, - unsigned int *value); - -sw_error_t -hppe_in_flow_tbl_rd_op_data1_data_set( - a_uint32_t dev_id, - unsigned int value); - -sw_error_t -hppe_in_flow_tbl_rd_op_data2_data_get( - a_uint32_t dev_id, - unsigned int *value); - -sw_error_t -hppe_in_flow_tbl_rd_op_data2_data_set( - a_uint32_t dev_id, - unsigned int value); - -sw_error_t -hppe_in_flow_tbl_rd_op_data3_data_get( - a_uint32_t dev_id, - unsigned int *value); - -sw_error_t -hppe_in_flow_tbl_rd_op_data3_data_set( - a_uint32_t dev_id, - unsigned int value); - -sw_error_t -hppe_in_flow_tbl_rd_op_data4_data_get( - a_uint32_t dev_id, - unsigned int *value); - -sw_error_t -hppe_in_flow_tbl_rd_op_data4_data_set( - a_uint32_t dev_id, - unsigned int value); - -sw_error_t -hppe_in_flow_tbl_rd_op_data5_data_get( - a_uint32_t dev_id, - unsigned int *value); - -sw_error_t -hppe_in_flow_tbl_rd_op_data5_data_set( - a_uint32_t dev_id, - unsigned int value); - -sw_error_t -hppe_in_flow_tbl_rd_op_data6_data_get( - a_uint32_t dev_id, - unsigned int *value); - -sw_error_t -hppe_in_flow_tbl_rd_op_data6_data_set( - a_uint32_t dev_id, - unsigned int value); - -sw_error_t -hppe_in_flow_tbl_rd_op_data7_data_get( - a_uint32_t dev_id, - unsigned int *value); - -sw_error_t -hppe_in_flow_tbl_rd_op_data7_data_set( - a_uint32_t dev_id, - unsigned int value); - -sw_error_t -hppe_in_flow_tbl_rd_op_data8_data_get( - a_uint32_t dev_id, - unsigned int *value); - -sw_error_t -hppe_in_flow_tbl_rd_op_data8_data_set( - a_uint32_t dev_id, - unsigned int value); - -sw_error_t -hppe_flow_host_tbl_rd_op_data0_data_get( - a_uint32_t dev_id, - unsigned int *value); - -sw_error_t -hppe_flow_host_tbl_rd_op_data0_data_set( - a_uint32_t dev_id, - unsigned int value); - -sw_error_t -hppe_flow_host_tbl_rd_op_data1_data_get( - a_uint32_t dev_id, - unsigned int *value); - -sw_error_t -hppe_flow_host_tbl_rd_op_data1_data_set( - a_uint32_t dev_id, - unsigned int value); - -sw_error_t -hppe_flow_host_tbl_rd_op_data2_data_get( - a_uint32_t dev_id, - unsigned int *value); - -sw_error_t -hppe_flow_host_tbl_rd_op_data2_data_set( - a_uint32_t dev_id, - unsigned int value); - -sw_error_t -hppe_flow_host_tbl_rd_op_data3_data_get( - a_uint32_t dev_id, - unsigned int *value); - -sw_error_t -hppe_flow_host_tbl_rd_op_data3_data_set( - a_uint32_t dev_id, - unsigned int value); - -sw_error_t -hppe_flow_host_tbl_rd_op_data4_data_get( - a_uint32_t dev_id, - unsigned int *value); - -sw_error_t -hppe_flow_host_tbl_rd_op_data4_data_set( - a_uint32_t dev_id, - unsigned int value); - -sw_error_t -hppe_flow_host_tbl_rd_op_data5_data_get( - a_uint32_t dev_id, - unsigned int *value); - -sw_error_t -hppe_flow_host_tbl_rd_op_data5_data_set( - a_uint32_t dev_id, - unsigned int value); - -sw_error_t -hppe_flow_host_tbl_rd_op_data6_data_get( - a_uint32_t dev_id, - unsigned int *value); - -sw_error_t -hppe_flow_host_tbl_rd_op_data6_data_set( - a_uint32_t dev_id, - unsigned int value); - -sw_error_t -hppe_flow_host_tbl_rd_op_data7_data_get( - a_uint32_t dev_id, - unsigned int *value); - -sw_error_t -hppe_flow_host_tbl_rd_op_data7_data_set( - a_uint32_t dev_id, - unsigned int value); - -sw_error_t -hppe_flow_host_tbl_rd_op_data8_data_get( - a_uint32_t dev_id, - unsigned int *value); - -sw_error_t -hppe_flow_host_tbl_rd_op_data8_data_set( - a_uint32_t dev_id, - unsigned int value); - -sw_error_t -hppe_flow_host_tbl_rd_op_data9_data_get( - a_uint32_t dev_id, - unsigned int *value); - -sw_error_t -hppe_flow_host_tbl_rd_op_data9_data_set( - a_uint32_t dev_id, - unsigned int value); - -sw_error_t -hppe_in_flow_tbl_rd_op_rslt_op_rslt_get( - a_uint32_t dev_id, - unsigned int *value); - -sw_error_t -hppe_in_flow_tbl_rd_op_rslt_op_rslt_set( - a_uint32_t dev_id, - unsigned int value); - -sw_error_t -hppe_in_flow_tbl_rd_op_rslt_valid_cnt_get( - a_uint32_t dev_id, - unsigned int *value); - -sw_error_t -hppe_in_flow_tbl_rd_op_rslt_valid_cnt_set( - a_uint32_t dev_id, - unsigned int value); - -sw_error_t -hppe_in_flow_tbl_rd_op_rslt_flow_entry_index_get( - a_uint32_t dev_id, - unsigned int *value); - -sw_error_t -hppe_in_flow_tbl_rd_op_rslt_flow_entry_index_set( - a_uint32_t dev_id, - unsigned int value); - -sw_error_t -hppe_in_flow_tbl_rd_op_rslt_cmd_id_get( - a_uint32_t dev_id, - unsigned int *value); - -sw_error_t -hppe_in_flow_tbl_rd_op_rslt_cmd_id_set( - a_uint32_t dev_id, - unsigned int value); - -sw_error_t -hppe_flow_host_tbl_rd_op_rslt_host_entry_index_get( - a_uint32_t dev_id, - unsigned int *value); - -sw_error_t -hppe_flow_host_tbl_rd_op_rslt_host_entry_index_set( - a_uint32_t dev_id, - unsigned int value); - -sw_error_t -hppe_in_flow_tbl_rd_rslt_data0_data_get( - a_uint32_t dev_id, - unsigned int *value); - -sw_error_t -hppe_in_flow_tbl_rd_rslt_data0_data_set( - a_uint32_t dev_id, - unsigned int value); - -sw_error_t -hppe_in_flow_tbl_rd_rslt_data1_data_get( - a_uint32_t dev_id, - unsigned int *value); - -sw_error_t -hppe_in_flow_tbl_rd_rslt_data1_data_set( - a_uint32_t dev_id, - unsigned int value); - -sw_error_t -hppe_in_flow_tbl_rd_rslt_data2_data_get( - a_uint32_t dev_id, - unsigned int *value); - -sw_error_t -hppe_in_flow_tbl_rd_rslt_data2_data_set( - a_uint32_t dev_id, - unsigned int value); - -sw_error_t -hppe_in_flow_tbl_rd_rslt_data3_data_get( - a_uint32_t dev_id, - unsigned int *value); - -sw_error_t -hppe_in_flow_tbl_rd_rslt_data3_data_set( - a_uint32_t dev_id, - unsigned int value); - -sw_error_t -hppe_in_flow_tbl_rd_rslt_data4_data_get( - a_uint32_t dev_id, - unsigned int *value); - -sw_error_t -hppe_in_flow_tbl_rd_rslt_data4_data_set( - a_uint32_t dev_id, - unsigned int value); - -sw_error_t -hppe_in_flow_tbl_rd_rslt_data5_data_get( - a_uint32_t dev_id, - unsigned int *value); - -sw_error_t -hppe_in_flow_tbl_rd_rslt_data5_data_set( - a_uint32_t dev_id, - unsigned int value); - -sw_error_t -hppe_in_flow_tbl_rd_rslt_data6_data_get( - a_uint32_t dev_id, - unsigned int *value); - -sw_error_t -hppe_in_flow_tbl_rd_rslt_data6_data_set( - a_uint32_t dev_id, - unsigned int value); - -sw_error_t -hppe_in_flow_tbl_rd_rslt_data7_data_get( - a_uint32_t dev_id, - unsigned int *value); - -sw_error_t -hppe_in_flow_tbl_rd_rslt_data7_data_set( - a_uint32_t dev_id, - unsigned int value); - -sw_error_t -hppe_in_flow_tbl_rd_rslt_data8_data_get( - a_uint32_t dev_id, - unsigned int *value); - -sw_error_t -hppe_in_flow_tbl_rd_rslt_data8_data_set( - a_uint32_t dev_id, - unsigned int value); - -sw_error_t -hppe_flow_host_tbl_rd_rslt_data0_data_get( - a_uint32_t dev_id, - unsigned int *value); - -sw_error_t -hppe_flow_host_tbl_rd_rslt_data0_data_set( - a_uint32_t dev_id, - unsigned int value); - -sw_error_t -hppe_flow_host_tbl_rd_rslt_data1_data_get( - a_uint32_t dev_id, - unsigned int *value); - -sw_error_t -hppe_flow_host_tbl_rd_rslt_data1_data_set( - a_uint32_t dev_id, - unsigned int value); - -sw_error_t -hppe_flow_host_tbl_rd_rslt_data2_data_get( - a_uint32_t dev_id, - unsigned int *value); - -sw_error_t -hppe_flow_host_tbl_rd_rslt_data2_data_set( - a_uint32_t dev_id, - unsigned int value); - -sw_error_t -hppe_flow_host_tbl_rd_rslt_data3_data_get( - a_uint32_t dev_id, - unsigned int *value); - -sw_error_t -hppe_flow_host_tbl_rd_rslt_data3_data_set( - a_uint32_t dev_id, - unsigned int value); - -sw_error_t -hppe_flow_host_tbl_rd_rslt_data4_data_get( - a_uint32_t dev_id, - unsigned int *value); - -sw_error_t -hppe_flow_host_tbl_rd_rslt_data4_data_set( - a_uint32_t dev_id, - unsigned int value); - -sw_error_t -hppe_flow_host_tbl_rd_rslt_data5_data_get( - a_uint32_t dev_id, - unsigned int *value); - -sw_error_t -hppe_flow_host_tbl_rd_rslt_data5_data_set( - a_uint32_t dev_id, - unsigned int value); - -sw_error_t -hppe_flow_host_tbl_rd_rslt_data6_data_get( - a_uint32_t dev_id, - unsigned int *value); - -sw_error_t -hppe_flow_host_tbl_rd_rslt_data6_data_set( - a_uint32_t dev_id, - unsigned int value); - -sw_error_t -hppe_flow_host_tbl_rd_rslt_data7_data_get( - a_uint32_t dev_id, - unsigned int *value); - -sw_error_t -hppe_flow_host_tbl_rd_rslt_data7_data_set( - a_uint32_t dev_id, - unsigned int value); - -sw_error_t -hppe_flow_host_tbl_rd_rslt_data8_data_get( - a_uint32_t dev_id, - unsigned int *value); - -sw_error_t -hppe_flow_host_tbl_rd_rslt_data8_data_set( - a_uint32_t dev_id, - unsigned int value); - -sw_error_t -hppe_flow_host_tbl_rd_rslt_data9_data_get( - a_uint32_t dev_id, - unsigned int *value); - -sw_error_t -hppe_flow_host_tbl_rd_rslt_data9_data_set( - a_uint32_t dev_id, - unsigned int value); - -sw_error_t -hppe_eg_flow_tree_map_tbl_tree_id_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_eg_flow_tree_map_tbl_tree_id_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_in_flow_cnt_tbl_hit_byte_counter_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint64_t *value); - -sw_error_t -hppe_in_flow_cnt_tbl_hit_byte_counter_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint64_t value); - -sw_error_t -hppe_in_flow_cnt_tbl_hit_pkt_counter_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_in_flow_cnt_tbl_hit_pkt_counter_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_flow_ipv4_5tuple_add( - a_uint32_t dev_id, a_uint32_t op_mode, - a_uint32_t *index, union in_flow_tbl_u *entry); - -sw_error_t -hppe_flow_ipv4_3tuple_add( - a_uint32_t dev_id, a_uint32_t op_mode, - a_uint32_t *index, union in_flow_3tuple_tbl_u *entry); - -sw_error_t -hppe_flow_ipv6_5tuple_add( - a_uint32_t dev_id, a_uint32_t op_mode, - a_uint32_t *index, union in_flow_ipv6_5tuple_tbl_u *entry); - -sw_error_t -hppe_flow_ipv6_3tuple_add( - a_uint32_t dev_id, a_uint32_t op_mode, - a_uint32_t *index, union in_flow_ipv6_3tuple_tbl_u *entry); - -sw_error_t -hppe_flow_flush_common(a_uint32_t dev_id); - -sw_error_t -hppe_flow_ipv4_5tuple_del( - a_uint32_t dev_id, a_uint32_t op_mode, - a_uint32_t *index, union in_flow_tbl_u *entry); - -sw_error_t -hppe_flow_ipv4_3tuple_del( - a_uint32_t dev_id, a_uint32_t op_mode, - a_uint32_t *index, union in_flow_3tuple_tbl_u *entry); - -sw_error_t -hppe_flow_ipv6_5tuple_del( - a_uint32_t dev_id, a_uint32_t op_mode, - a_uint32_t *index, union in_flow_ipv6_5tuple_tbl_u *entry); - -sw_error_t -hppe_flow_ipv6_3tuple_del( - a_uint32_t dev_id, a_uint32_t op_mode, - a_uint32_t *index, union in_flow_ipv6_3tuple_tbl_u *entry); - -sw_error_t -hppe_flow_ipv4_5tuple_get( - a_uint32_t dev_id, a_uint32_t op_mode, - a_uint32_t *index, union in_flow_tbl_u *entry); - -sw_error_t -hppe_flow_ipv4_3tuple_get( - a_uint32_t dev_id, a_uint32_t op_mode, - a_uint32_t *index, union in_flow_3tuple_tbl_u *entry); - -sw_error_t -hppe_flow_ipv6_5tuple_get( - a_uint32_t dev_id, a_uint32_t op_mode, - a_uint32_t *index, union in_flow_ipv6_5tuple_tbl_u *entry); - -sw_error_t -hppe_flow_ipv6_3tuple_get( - a_uint32_t dev_id, a_uint32_t op_mode, - a_uint32_t *index, union in_flow_ipv6_3tuple_tbl_u *entry); - - -#include "hppe_ip_reg.h" - -sw_error_t -hppe_flow_host_get_common( - a_uint32_t dev_id, - a_uint32_t op_mode, - a_uint32_t *index, - a_uint32_t *data, - a_uint32_t num); - - -sw_error_t -hppe_flow_host_flush_common(a_uint32_t dev_id); - - -sw_error_t -hppe_flow_host_op_both_common( - a_uint32_t dev_id, - a_uint32_t op_type, - a_uint32_t op_mode, - a_uint32_t *index); - - -sw_error_t -hppe_flow_entry_host_op_ipv4_5tuple_add( - a_uint32_t dev_id, a_uint32_t op_mode, - a_uint32_t *index, union in_flow_tbl_u *entry); - - -sw_error_t -hppe_flow_entry_host_op_ipv4_3tuple_add( - a_uint32_t dev_id, a_uint32_t op_mode, - a_uint32_t *index, union in_flow_3tuple_tbl_u *entry); - - -sw_error_t -hppe_flow_entry_host_op_ipv6_5tuple_add( - a_uint32_t dev_id, a_uint32_t op_mode, - a_uint32_t *index, union in_flow_ipv6_5tuple_tbl_u *entry); - - -sw_error_t -hppe_flow_entry_host_op_ipv6_3tuple_add( - a_uint32_t dev_id, a_uint32_t op_mode, - a_uint32_t *index, union in_flow_ipv6_3tuple_tbl_u *entry); - - -sw_error_t -hppe_flow_entry_host_op_ipv4_5tuple_del( - a_uint32_t dev_id, a_uint32_t op_mode, - a_uint32_t *index, union in_flow_tbl_u *entry); - - -sw_error_t -hppe_flow_entry_host_op_ipv4_3tuple_del( - a_uint32_t dev_id, a_uint32_t op_mode, - a_uint32_t *index, union in_flow_3tuple_tbl_u *entry); - - -sw_error_t -hppe_flow_entry_host_op_ipv6_5tuple_del( - a_uint32_t dev_id, a_uint32_t op_mode, - a_uint32_t *index, union in_flow_ipv6_5tuple_tbl_u *entry); - - -sw_error_t -hppe_flow_entry_host_op_ipv6_3tuple_del( - a_uint32_t dev_id, a_uint32_t op_mode, - a_uint32_t *index, union in_flow_ipv6_3tuple_tbl_u *entry); - - -sw_error_t -hppe_flow_entry_host_op_ipv4_5tuple_get( - a_uint32_t dev_id, a_uint32_t op_mode, - a_uint32_t *index, union in_flow_tbl_u *entry); - - -sw_error_t -hppe_flow_entry_host_op_ipv4_3tuple_get( - a_uint32_t dev_id, a_uint32_t op_mode, - a_uint32_t *index, union in_flow_3tuple_tbl_u *entry); - - -sw_error_t -hppe_flow_entry_host_op_ipv6_5tuple_get( - a_uint32_t dev_id, a_uint32_t op_mode, - a_uint32_t *index, union in_flow_ipv6_5tuple_tbl_u *entry); - - -sw_error_t -hppe_flow_entry_host_op_ipv6_3tuple_get( - a_uint32_t dev_id, a_uint32_t op_mode, - a_uint32_t *index, union in_flow_ipv6_3tuple_tbl_u *entry); - - -sw_error_t -hppe_flow_host_data_op_common( - a_uint32_t dev_id, - a_uint32_t op_type, - a_uint32_t op_mode, - a_uint32_t *index); - - -sw_error_t -hppe_flow_host_ipv4_data_add( - a_uint32_t dev_id, a_uint32_t op_mode, - a_uint32_t *index, union host_tbl_u *entry); - - -sw_error_t -hppe_flow_host_ipv6_data_add( - a_uint32_t dev_id, a_uint32_t op_mode, - a_uint32_t *index, union host_ipv6_tbl_u *entry); - - -sw_error_t -hppe_flow_host_ipv4_data_get( - a_uint32_t dev_id, a_uint32_t op_mode, - a_uint32_t *index, union host_tbl_u *entry); - - -sw_error_t -hppe_flow_host_ipv6_data_get( - a_uint32_t dev_id, a_uint32_t op_mode, - a_uint32_t *index, union host_ipv6_tbl_u *entry); - - -sw_error_t -hppe_flow_host_ipv4_data_del( - a_uint32_t dev_id, a_uint32_t op_mode, - a_uint32_t *index, union host_tbl_u *entry); - - -sw_error_t -hppe_flow_host_ipv6_data_del( - a_uint32_t dev_id, a_uint32_t op_mode, - a_uint32_t *index, union host_ipv6_tbl_u *entry); - -sw_error_t -hppe_flow_host_ipv4_data_rd_add( - a_uint32_t dev_id, a_uint32_t op_mode, - a_uint32_t *index, union host_tbl_u *entry); - -sw_error_t -hppe_flow_host_ipv6_data_rd_add( - a_uint32_t dev_id, a_uint32_t op_mode, - a_uint32_t *index, union host_ipv6_tbl_u *entry); - -#endif diff --git a/feeds/ipq807x/qca-ssdk/src/include/hsl/hppe/hppe_flow_reg.h b/feeds/ipq807x/qca-ssdk/src/include/hsl/hppe/hppe_flow_reg.h deleted file mode 100755 index 41b9c445b..000000000 --- a/feeds/ipq807x/qca-ssdk/src/include/hsl/hppe/hppe_flow_reg.h +++ /dev/null @@ -1,2856 +0,0 @@ -/* - * Copyright (c) 2016-2017, The Linux Foundation. All rights reserved. - * Permission to use, copy, modify, and/or distribute this software for - * any purpose with or without fee is hereby granted, provided that the - * above copyright notice and this permission notice appear in all copies. - * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES - * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR - * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES - * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN - * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT - * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. - */ - - -/** - * @defgroup - * @{ - */ -#ifndef _HPPE_FLOW_REG_H_ -#define _HPPE_FLOW_REG_H_ - -/*[register] FLOW_CTRL0*/ -#define FLOW_CTRL0 -#define FLOW_CTRL0_ADDRESS 0x368 -#define FLOW_CTRL0_NUM 1 -#define FLOW_CTRL0_INC 0x4 -#define FLOW_CTRL0_TYPE REG_TYPE_RW -#define FLOW_CTRL0_DEFAULT 0xc89 - /*[field] FLOW_EN*/ - #define FLOW_CTRL0_FLOW_EN - #define FLOW_CTRL0_FLOW_EN_OFFSET 0 - #define FLOW_CTRL0_FLOW_EN_LEN 1 - #define FLOW_CTRL0_FLOW_EN_DEFAULT 0x1 - /*[field] FLOW_HASH_MODE_0*/ - #define FLOW_CTRL0_FLOW_HASH_MODE_0 - #define FLOW_CTRL0_FLOW_HASH_MODE_0_OFFSET 1 - #define FLOW_CTRL0_FLOW_HASH_MODE_0_LEN 2 - #define FLOW_CTRL0_FLOW_HASH_MODE_0_DEFAULT 0x0 - /*[field] FLOW_HASH_MODE_1*/ - #define FLOW_CTRL0_FLOW_HASH_MODE_1 - #define FLOW_CTRL0_FLOW_HASH_MODE_1_OFFSET 3 - #define FLOW_CTRL0_FLOW_HASH_MODE_1_LEN 2 - #define FLOW_CTRL0_FLOW_HASH_MODE_1_DEFAULT 0x1 - /*[field] FLOW_AGE_TIMER*/ - #define FLOW_CTRL0_FLOW_AGE_TIMER - #define FLOW_CTRL0_FLOW_AGE_TIMER_OFFSET 5 - #define FLOW_CTRL0_FLOW_AGE_TIMER_LEN 16 - #define FLOW_CTRL0_FLOW_AGE_TIMER_DEFAULT 0x64 - /*[field] FLOW_AGE_TIMER_UNIT*/ - #define FLOW_CTRL0_FLOW_AGE_TIMER_UNIT - #define FLOW_CTRL0_FLOW_AGE_TIMER_UNIT_OFFSET 21 - #define FLOW_CTRL0_FLOW_AGE_TIMER_UNIT_LEN 2 - #define FLOW_CTRL0_FLOW_AGE_TIMER_UNIT_DEFAULT 0x0 - -struct flow_ctrl0 { - a_uint32_t flow_en:1; - a_uint32_t flow_hash_mode_0:2; - a_uint32_t flow_hash_mode_1:2; - a_uint32_t flow_age_timer:16; - a_uint32_t flow_age_timer_unit:2; - a_uint32_t _reserved0:9; -}; - -union flow_ctrl0_u { - a_uint32_t val; - struct flow_ctrl0 bf; -}; - -/*[register] FLOW_CTRL1*/ -#define FLOW_CTRL1 -#define FLOW_CTRL1_ADDRESS 0x36c -#define FLOW_CTRL1_NUM 3 -#define FLOW_CTRL1_INC 0x4 -#define FLOW_CTRL1_TYPE REG_TYPE_RW -#define FLOW_CTRL1_DEFAULT 0x20000 - /*[field] FLOW_CTL0_MISS_ACTION*/ - #define FLOW_CTRL1_FLOW_CTL0_MISS_ACTION - #define FLOW_CTRL1_FLOW_CTL0_MISS_ACTION_OFFSET 0 - #define FLOW_CTRL1_FLOW_CTL0_MISS_ACTION_LEN 2 - #define FLOW_CTRL1_FLOW_CTL0_MISS_ACTION_DEFAULT 0x0 - /*[field] FLOW_CTL0_FRAG_BYPASS*/ - #define FLOW_CTRL1_FLOW_CTL0_FRAG_BYPASS - #define FLOW_CTRL1_FLOW_CTL0_FRAG_BYPASS_OFFSET 2 - #define FLOW_CTRL1_FLOW_CTL0_FRAG_BYPASS_LEN 1 - #define FLOW_CTRL1_FLOW_CTL0_FRAG_BYPASS_DEFAULT 0x0 - /*[field] FLOW_CTL0_TCP_SPECIAL*/ - #define FLOW_CTRL1_FLOW_CTL0_TCP_SPECIAL - #define FLOW_CTRL1_FLOW_CTL0_TCP_SPECIAL_OFFSET 3 - #define FLOW_CTRL1_FLOW_CTL0_TCP_SPECIAL_LEN 1 - #define FLOW_CTRL1_FLOW_CTL0_TCP_SPECIAL_DEFAULT 0x0 - /*[field] FLOW_CTL0_BYPASS*/ - #define FLOW_CTRL1_FLOW_CTL0_BYPASS - #define FLOW_CTRL1_FLOW_CTL0_BYPASS_OFFSET 4 - #define FLOW_CTRL1_FLOW_CTL0_BYPASS_LEN 1 - #define FLOW_CTRL1_FLOW_CTL0_BYPASS_DEFAULT 0x0 - /*[field] FLOW_CTL0_KEY_SEL*/ - #define FLOW_CTRL1_FLOW_CTL0_KEY_SEL - #define FLOW_CTRL1_FLOW_CTL0_KEY_SEL_OFFSET 5 - #define FLOW_CTRL1_FLOW_CTL0_KEY_SEL_LEN 1 - #define FLOW_CTRL1_FLOW_CTL0_KEY_SEL_DEFAULT 0x0 - /*[field] FLOW_CTL1_MISS_ACTION*/ - #define FLOW_CTRL1_FLOW_CTL1_MISS_ACTION - #define FLOW_CTRL1_FLOW_CTL1_MISS_ACTION_OFFSET 6 - #define FLOW_CTRL1_FLOW_CTL1_MISS_ACTION_LEN 2 - #define FLOW_CTRL1_FLOW_CTL1_MISS_ACTION_DEFAULT 0x0 - /*[field] FLOW_CTL1_FRAG_BYPASS*/ - #define FLOW_CTRL1_FLOW_CTL1_FRAG_BYPASS - #define FLOW_CTRL1_FLOW_CTL1_FRAG_BYPASS_OFFSET 8 - #define FLOW_CTRL1_FLOW_CTL1_FRAG_BYPASS_LEN 1 - #define FLOW_CTRL1_FLOW_CTL1_FRAG_BYPASS_DEFAULT 0x0 - /*[field] FLOW_CTL1_TCP_SPECIAL*/ - #define FLOW_CTRL1_FLOW_CTL1_TCP_SPECIAL - #define FLOW_CTRL1_FLOW_CTL1_TCP_SPECIAL_OFFSET 9 - #define FLOW_CTRL1_FLOW_CTL1_TCP_SPECIAL_LEN 1 - #define FLOW_CTRL1_FLOW_CTL1_TCP_SPECIAL_DEFAULT 0x0 - /*[field] FLOW_CTL1_BYPASS*/ - #define FLOW_CTRL1_FLOW_CTL1_BYPASS - #define FLOW_CTRL1_FLOW_CTL1_BYPASS_OFFSET 10 - #define FLOW_CTRL1_FLOW_CTL1_BYPASS_LEN 1 - #define FLOW_CTRL1_FLOW_CTL1_BYPASS_DEFAULT 0x0 - /*[field] FLOW_CTL1_KEY_SEL*/ - #define FLOW_CTRL1_FLOW_CTL1_KEY_SEL - #define FLOW_CTRL1_FLOW_CTL1_KEY_SEL_OFFSET 11 - #define FLOW_CTRL1_FLOW_CTL1_KEY_SEL_LEN 1 - #define FLOW_CTRL1_FLOW_CTL1_KEY_SEL_DEFAULT 0x0 - /*[field] FLOW_CTL2_MISS_ACTION*/ - #define FLOW_CTRL1_FLOW_CTL2_MISS_ACTION - #define FLOW_CTRL1_FLOW_CTL2_MISS_ACTION_OFFSET 12 - #define FLOW_CTRL1_FLOW_CTL2_MISS_ACTION_LEN 2 - #define FLOW_CTRL1_FLOW_CTL2_MISS_ACTION_DEFAULT 0x0 - /*[field] FLOW_CTL2_FRAG_BYPASS*/ - #define FLOW_CTRL1_FLOW_CTL2_FRAG_BYPASS - #define FLOW_CTRL1_FLOW_CTL2_FRAG_BYPASS_OFFSET 14 - #define FLOW_CTRL1_FLOW_CTL2_FRAG_BYPASS_LEN 1 - #define FLOW_CTRL1_FLOW_CTL2_FRAG_BYPASS_DEFAULT 0x0 - /*[field] FLOW_CTL2_TCP_SPECIAL*/ - #define FLOW_CTRL1_FLOW_CTL2_TCP_SPECIAL - #define FLOW_CTRL1_FLOW_CTL2_TCP_SPECIAL_OFFSET 15 - #define FLOW_CTRL1_FLOW_CTL2_TCP_SPECIAL_LEN 1 - #define FLOW_CTRL1_FLOW_CTL2_TCP_SPECIAL_DEFAULT 0x0 - /*[field] FLOW_CTL2_BYPASS*/ - #define FLOW_CTRL1_FLOW_CTL2_BYPASS - #define FLOW_CTRL1_FLOW_CTL2_BYPASS_OFFSET 16 - #define FLOW_CTRL1_FLOW_CTL2_BYPASS_LEN 1 - #define FLOW_CTRL1_FLOW_CTL2_BYPASS_DEFAULT 0x0 - /*[field] FLOW_CTL2_KEY_SEL*/ - #define FLOW_CTRL1_FLOW_CTL2_KEY_SEL - #define FLOW_CTRL1_FLOW_CTL2_KEY_SEL_OFFSET 17 - #define FLOW_CTRL1_FLOW_CTL2_KEY_SEL_LEN 1 - #define FLOW_CTRL1_FLOW_CTL2_KEY_SEL_DEFAULT 0x1 - /*[field] FLOW_CTL3_MISS_ACTION*/ - #define FLOW_CTRL1_FLOW_CTL3_MISS_ACTION - #define FLOW_CTRL1_FLOW_CTL3_MISS_ACTION_OFFSET 18 - #define FLOW_CTRL1_FLOW_CTL3_MISS_ACTION_LEN 2 - #define FLOW_CTRL1_FLOW_CTL3_MISS_ACTION_DEFAULT 0x0 - /*[field] FLOW_CTL3_FRAG_BYPASS*/ - #define FLOW_CTRL1_FLOW_CTL3_FRAG_BYPASS - #define FLOW_CTRL1_FLOW_CTL3_FRAG_BYPASS_OFFSET 20 - #define FLOW_CTRL1_FLOW_CTL3_FRAG_BYPASS_LEN 1 - #define FLOW_CTRL1_FLOW_CTL3_FRAG_BYPASS_DEFAULT 0x0 - /*[field] FLOW_CTL3_TCP_SPECIAL*/ - #define FLOW_CTRL1_FLOW_CTL3_TCP_SPECIAL - #define FLOW_CTRL1_FLOW_CTL3_TCP_SPECIAL_OFFSET 21 - #define FLOW_CTRL1_FLOW_CTL3_TCP_SPECIAL_LEN 1 - #define FLOW_CTRL1_FLOW_CTL3_TCP_SPECIAL_DEFAULT 0x0 - /*[field] FLOW_CTL3_BYPASS*/ - #define FLOW_CTRL1_FLOW_CTL3_BYPASS - #define FLOW_CTRL1_FLOW_CTL3_BYPASS_OFFSET 22 - #define FLOW_CTRL1_FLOW_CTL3_BYPASS_LEN 1 - #define FLOW_CTRL1_FLOW_CTL3_BYPASS_DEFAULT 0x0 - /*[field] FLOW_CTL3_KEY_SEL*/ - #define FLOW_CTRL1_FLOW_CTL3_KEY_SEL - #define FLOW_CTRL1_FLOW_CTL3_KEY_SEL_OFFSET 23 - #define FLOW_CTRL1_FLOW_CTL3_KEY_SEL_LEN 1 - #define FLOW_CTRL1_FLOW_CTL3_KEY_SEL_DEFAULT 0x0 - /*[field] FLOW_CTL4_MISS_ACTION*/ - #define FLOW_CTRL1_FLOW_CTL4_MISS_ACTION - #define FLOW_CTRL1_FLOW_CTL4_MISS_ACTION_OFFSET 24 - #define FLOW_CTRL1_FLOW_CTL4_MISS_ACTION_LEN 2 - #define FLOW_CTRL1_FLOW_CTL4_MISS_ACTION_DEFAULT 0x0 - /*[field] FLOW_CTL4_FRAG_BYPASS*/ - #define FLOW_CTRL1_FLOW_CTL4_FRAG_BYPASS - #define FLOW_CTRL1_FLOW_CTL4_FRAG_BYPASS_OFFSET 26 - #define FLOW_CTRL1_FLOW_CTL4_FRAG_BYPASS_LEN 1 - #define FLOW_CTRL1_FLOW_CTL4_FRAG_BYPASS_DEFAULT 0x0 - /*[field] FLOW_CTL4_TCP_SPECIAL*/ - #define FLOW_CTRL1_FLOW_CTL4_TCP_SPECIAL - #define FLOW_CTRL1_FLOW_CTL4_TCP_SPECIAL_OFFSET 27 - #define FLOW_CTRL1_FLOW_CTL4_TCP_SPECIAL_LEN 1 - #define FLOW_CTRL1_FLOW_CTL4_TCP_SPECIAL_DEFAULT 0x0 - /*[field] FLOW_CTL4_BYPASS*/ - #define FLOW_CTRL1_FLOW_CTL4_BYPASS - #define FLOW_CTRL1_FLOW_CTL4_BYPASS_OFFSET 28 - #define FLOW_CTRL1_FLOW_CTL4_BYPASS_LEN 1 - #define FLOW_CTRL1_FLOW_CTL4_BYPASS_DEFAULT 0x0 - /*[field] FLOW_CTL4_KEY_SEL*/ - #define FLOW_CTRL1_FLOW_CTL4_KEY_SEL - #define FLOW_CTRL1_FLOW_CTL4_KEY_SEL_OFFSET 29 - #define FLOW_CTRL1_FLOW_CTL4_KEY_SEL_LEN 1 - #define FLOW_CTRL1_FLOW_CTL4_KEY_SEL_DEFAULT 0x0 - -struct flow_ctrl1 { - a_uint32_t flow_ctl0_miss_action:2; - a_uint32_t flow_ctl0_frag_bypass:1; - a_uint32_t flow_ctl0_tcp_special:1; - a_uint32_t flow_ctl0_bypass:1; - a_uint32_t flow_ctl0_key_sel:1; - a_uint32_t flow_ctl1_miss_action:2; - a_uint32_t flow_ctl1_frag_bypass:1; - a_uint32_t flow_ctl1_tcp_special:1; - a_uint32_t flow_ctl1_bypass:1; - a_uint32_t flow_ctl1_key_sel:1; - a_uint32_t flow_ctl2_miss_action:2; - a_uint32_t flow_ctl2_frag_bypass:1; - a_uint32_t flow_ctl2_tcp_special:1; - a_uint32_t flow_ctl2_bypass:1; - a_uint32_t flow_ctl2_key_sel:1; - a_uint32_t flow_ctl3_miss_action:2; - a_uint32_t flow_ctl3_frag_bypass:1; - a_uint32_t flow_ctl3_tcp_special:1; - a_uint32_t flow_ctl3_bypass:1; - a_uint32_t flow_ctl3_key_sel:1; - a_uint32_t flow_ctl4_miss_action:2; - a_uint32_t flow_ctl4_frag_bypass:1; - a_uint32_t flow_ctl4_tcp_special:1; - a_uint32_t flow_ctl4_bypass:1; - a_uint32_t flow_ctl4_key_sel:1; - a_uint32_t _reserved0:2; -}; - -union flow_ctrl1_u { - a_uint32_t val; - struct flow_ctrl1 bf; -}; - -/*[register] IN_FLOW_TBL_OP*/ -#define IN_FLOW_TBL_OP -#define IN_FLOW_TBL_OP_ADDRESS 0x3b8 -#define IN_FLOW_TBL_OP_NUM 1 -#define IN_FLOW_TBL_OP_INC 0x4 -#define IN_FLOW_TBL_OP_TYPE REG_TYPE_RW -#define IN_FLOW_TBL_OP_DEFAULT 0x0 - /*[field] CMD_ID*/ - #define IN_FLOW_TBL_OP_CMD_ID - #define IN_FLOW_TBL_OP_CMD_ID_OFFSET 0 - #define IN_FLOW_TBL_OP_CMD_ID_LEN 4 - #define IN_FLOW_TBL_OP_CMD_ID_DEFAULT 0x0 - /*[field] BYP_RSLT_EN*/ - #define IN_FLOW_TBL_OP_BYP_RSLT_EN - #define IN_FLOW_TBL_OP_BYP_RSLT_EN_OFFSET 4 - #define IN_FLOW_TBL_OP_BYP_RSLT_EN_LEN 1 - #define IN_FLOW_TBL_OP_BYP_RSLT_EN_DEFAULT 0x0 - /*[field] OP_TYPE*/ - #define IN_FLOW_TBL_OP_OP_TYPE - #define IN_FLOW_TBL_OP_OP_TYPE_OFFSET 5 - #define IN_FLOW_TBL_OP_OP_TYPE_LEN 3 - #define IN_FLOW_TBL_OP_OP_TYPE_DEFAULT 0x0 - /*[field] HASH_BLOCK_BITMAP*/ - #define IN_FLOW_TBL_OP_HASH_BLOCK_BITMAP - #define IN_FLOW_TBL_OP_HASH_BLOCK_BITMAP_OFFSET 8 - #define IN_FLOW_TBL_OP_HASH_BLOCK_BITMAP_LEN 2 - #define IN_FLOW_TBL_OP_HASH_BLOCK_BITMAP_DEFAULT 0x0 - /*[field] OP_MODE*/ - #define IN_FLOW_TBL_OP_OP_MODE - #define IN_FLOW_TBL_OP_OP_MODE_OFFSET 10 - #define IN_FLOW_TBL_OP_OP_MODE_LEN 1 - #define IN_FLOW_TBL_OP_OP_MODE_DEFAULT 0x0 - /*[field] OP_HOST_EN*/ - #define IN_FLOW_TBL_OP_OP_HOST_EN - #define IN_FLOW_TBL_OP_OP_HOST_EN_OFFSET 11 - #define IN_FLOW_TBL_OP_OP_HOST_EN_LEN 1 - #define IN_FLOW_TBL_OP_OP_HOST_EN_DEFAULT 0x0 - /*[field] ENTRY_INDEX*/ - #define IN_FLOW_TBL_OP_ENTRY_INDEX - #define IN_FLOW_TBL_OP_ENTRY_INDEX_OFFSET 12 - #define IN_FLOW_TBL_OP_ENTRY_INDEX_LEN 12 - #define IN_FLOW_TBL_OP_ENTRY_INDEX_DEFAULT 0x0 - /*[field] OP_RESULT*/ - #define IN_FLOW_TBL_OP_OP_RESULT - #define IN_FLOW_TBL_OP_OP_RESULT_OFFSET 24 - #define IN_FLOW_TBL_OP_OP_RESULT_LEN 1 - #define IN_FLOW_TBL_OP_OP_RESULT_DEFAULT 0x0 - /*[field] BUSY*/ - #define IN_FLOW_TBL_OP_BUSY - #define IN_FLOW_TBL_OP_BUSY_OFFSET 25 - #define IN_FLOW_TBL_OP_BUSY_LEN 1 - #define IN_FLOW_TBL_OP_BUSY_DEFAULT 0x0 - -struct in_flow_tbl_op { - a_uint32_t cmd_id:4; - a_uint32_t byp_rslt_en:1; - a_uint32_t op_type:3; - a_uint32_t hash_block_bitmap:2; - a_uint32_t op_mode:1; - a_uint32_t op_host_en:1; - a_uint32_t entry_index:12; - a_uint32_t op_result:1; - a_uint32_t busy:1; - a_uint32_t _reserved0:6; -}; - -union in_flow_tbl_op_u { - a_uint32_t val; - struct in_flow_tbl_op bf; -}; - -/*[register] IN_FLOW_HOST_TBL_OP*/ -#define IN_FLOW_HOST_TBL_OP -#define IN_FLOW_HOST_TBL_OP_ADDRESS 0x3bc -#define IN_FLOW_HOST_TBL_OP_NUM 1 -#define IN_FLOW_HOST_TBL_OP_INC 0x4 -#define IN_FLOW_HOST_TBL_OP_TYPE REG_TYPE_RW -#define IN_FLOW_HOST_TBL_OP_DEFAULT 0x0 - /*[field] HASH_BLOCK_BITMAP*/ - #define IN_FLOW_HOST_TBL_OP_HASH_BLOCK_BITMAP - #define IN_FLOW_HOST_TBL_OP_HASH_BLOCK_BITMAP_OFFSET 0 - #define IN_FLOW_HOST_TBL_OP_HASH_BLOCK_BITMAP_LEN 2 - #define IN_FLOW_HOST_TBL_OP_HASH_BLOCK_BITMAP_DEFAULT 0x0 - /*[field] HOST_ENTRY_INDEX*/ - #define IN_FLOW_HOST_TBL_OP_HOST_ENTRY_INDEX - #define IN_FLOW_HOST_TBL_OP_HOST_ENTRY_INDEX_OFFSET 2 - #define IN_FLOW_HOST_TBL_OP_HOST_ENTRY_INDEX_LEN 13 - #define IN_FLOW_HOST_TBL_OP_HOST_ENTRY_INDEX_DEFAULT 0x0 - -struct in_flow_host_tbl_op { - a_uint32_t hash_block_bitmap:2; - a_uint32_t host_entry_index:13; - a_uint32_t _reserved0:17; -}; - -union in_flow_host_tbl_op_u { - a_uint32_t val; - struct in_flow_host_tbl_op bf; -}; - -/*[register] IN_FLOW_TBL_OP_DATA0*/ -#define IN_FLOW_TBL_OP_DATA0 -#define IN_FLOW_TBL_OP_DATA0_ADDRESS 0x3c0 -#define IN_FLOW_TBL_OP_DATA0_NUM 1 -#define IN_FLOW_TBL_OP_DATA0_INC 0x4 -#define IN_FLOW_TBL_OP_DATA0_TYPE REG_TYPE_RW -#define IN_FLOW_TBL_OP_DATA0_DEFAULT 0x0 - /*[field] DATA*/ - #define IN_FLOW_TBL_OP_DATA0_DATA - #define IN_FLOW_TBL_OP_DATA0_DATA_OFFSET 0 - #define IN_FLOW_TBL_OP_DATA0_DATA_LEN 32 - #define IN_FLOW_TBL_OP_DATA0_DATA_DEFAULT 0x0 - -struct in_flow_tbl_op_data0 { - a_uint32_t data:32; -}; - -union in_flow_tbl_op_data0_u { - a_uint32_t val; - struct in_flow_tbl_op_data0 bf; -}; - -/*[register] IN_FLOW_TBL_OP_DATA1*/ -#define IN_FLOW_TBL_OP_DATA1 -#define IN_FLOW_TBL_OP_DATA1_ADDRESS 0x3c4 -#define IN_FLOW_TBL_OP_DATA1_NUM 1 -#define IN_FLOW_TBL_OP_DATA1_INC 0x4 -#define IN_FLOW_TBL_OP_DATA1_TYPE REG_TYPE_RW -#define IN_FLOW_TBL_OP_DATA1_DEFAULT 0x0 - /*[field] DATA*/ - #define IN_FLOW_TBL_OP_DATA1_DATA - #define IN_FLOW_TBL_OP_DATA1_DATA_OFFSET 0 - #define IN_FLOW_TBL_OP_DATA1_DATA_LEN 32 - #define IN_FLOW_TBL_OP_DATA1_DATA_DEFAULT 0x0 - -struct in_flow_tbl_op_data1 { - a_uint32_t data:32; -}; - -union in_flow_tbl_op_data1_u { - a_uint32_t val; - struct in_flow_tbl_op_data1 bf; -}; - -/*[register] IN_FLOW_TBL_OP_DATA2*/ -#define IN_FLOW_TBL_OP_DATA2 -#define IN_FLOW_TBL_OP_DATA2_ADDRESS 0x3c8 -#define IN_FLOW_TBL_OP_DATA2_NUM 1 -#define IN_FLOW_TBL_OP_DATA2_INC 0x4 -#define IN_FLOW_TBL_OP_DATA2_TYPE REG_TYPE_RW -#define IN_FLOW_TBL_OP_DATA2_DEFAULT 0x0 - /*[field] DATA*/ - #define IN_FLOW_TBL_OP_DATA2_DATA - #define IN_FLOW_TBL_OP_DATA2_DATA_OFFSET 0 - #define IN_FLOW_TBL_OP_DATA2_DATA_LEN 32 - #define IN_FLOW_TBL_OP_DATA2_DATA_DEFAULT 0x0 - -struct in_flow_tbl_op_data2 { - a_uint32_t data:32; -}; - -union in_flow_tbl_op_data2_u { - a_uint32_t val; - struct in_flow_tbl_op_data2 bf; -}; - -/*[register] IN_FLOW_TBL_OP_DATA3*/ -#define IN_FLOW_TBL_OP_DATA3 -#define IN_FLOW_TBL_OP_DATA3_ADDRESS 0x3cc -#define IN_FLOW_TBL_OP_DATA3_NUM 1 -#define IN_FLOW_TBL_OP_DATA3_INC 0x4 -#define IN_FLOW_TBL_OP_DATA3_TYPE REG_TYPE_RW -#define IN_FLOW_TBL_OP_DATA3_DEFAULT 0x0 - /*[field] DATA*/ - #define IN_FLOW_TBL_OP_DATA3_DATA - #define IN_FLOW_TBL_OP_DATA3_DATA_OFFSET 0 - #define IN_FLOW_TBL_OP_DATA3_DATA_LEN 32 - #define IN_FLOW_TBL_OP_DATA3_DATA_DEFAULT 0x0 - -struct in_flow_tbl_op_data3 { - a_uint32_t data:32; -}; - -union in_flow_tbl_op_data3_u { - a_uint32_t val; - struct in_flow_tbl_op_data3 bf; -}; - -/*[register] IN_FLOW_TBL_OP_DATA4*/ -#define IN_FLOW_TBL_OP_DATA4 -#define IN_FLOW_TBL_OP_DATA4_ADDRESS 0x3d0 -#define IN_FLOW_TBL_OP_DATA4_NUM 1 -#define IN_FLOW_TBL_OP_DATA4_INC 0x4 -#define IN_FLOW_TBL_OP_DATA4_TYPE REG_TYPE_RW -#define IN_FLOW_TBL_OP_DATA4_DEFAULT 0x0 - /*[field] DATA*/ - #define IN_FLOW_TBL_OP_DATA4_DATA - #define IN_FLOW_TBL_OP_DATA4_DATA_OFFSET 0 - #define IN_FLOW_TBL_OP_DATA4_DATA_LEN 32 - #define IN_FLOW_TBL_OP_DATA4_DATA_DEFAULT 0x0 - -struct in_flow_tbl_op_data4 { - a_uint32_t data:32; -}; - -union in_flow_tbl_op_data4_u { - a_uint32_t val; - struct in_flow_tbl_op_data4 bf; -}; - -/*[register] IN_FLOW_TBL_OP_DATA5*/ -#define IN_FLOW_TBL_OP_DATA5 -#define IN_FLOW_TBL_OP_DATA5_ADDRESS 0x3d4 -#define IN_FLOW_TBL_OP_DATA5_NUM 1 -#define IN_FLOW_TBL_OP_DATA5_INC 0x4 -#define IN_FLOW_TBL_OP_DATA5_TYPE REG_TYPE_RW -#define IN_FLOW_TBL_OP_DATA5_DEFAULT 0x0 - /*[field] DATA*/ - #define IN_FLOW_TBL_OP_DATA5_DATA - #define IN_FLOW_TBL_OP_DATA5_DATA_OFFSET 0 - #define IN_FLOW_TBL_OP_DATA5_DATA_LEN 32 - #define IN_FLOW_TBL_OP_DATA5_DATA_DEFAULT 0x0 - -struct in_flow_tbl_op_data5 { - a_uint32_t data:32; -}; - -union in_flow_tbl_op_data5_u { - a_uint32_t val; - struct in_flow_tbl_op_data5 bf; -}; - -/*[register] IN_FLOW_TBL_OP_DATA6*/ -#define IN_FLOW_TBL_OP_DATA6 -#define IN_FLOW_TBL_OP_DATA6_ADDRESS 0x3d8 -#define IN_FLOW_TBL_OP_DATA6_NUM 1 -#define IN_FLOW_TBL_OP_DATA6_INC 0x4 -#define IN_FLOW_TBL_OP_DATA6_TYPE REG_TYPE_RW -#define IN_FLOW_TBL_OP_DATA6_DEFAULT 0x0 - /*[field] DATA*/ - #define IN_FLOW_TBL_OP_DATA6_DATA - #define IN_FLOW_TBL_OP_DATA6_DATA_OFFSET 0 - #define IN_FLOW_TBL_OP_DATA6_DATA_LEN 32 - #define IN_FLOW_TBL_OP_DATA6_DATA_DEFAULT 0x0 - -struct in_flow_tbl_op_data6 { - a_uint32_t data:32; -}; - -union in_flow_tbl_op_data6_u { - a_uint32_t val; - struct in_flow_tbl_op_data6 bf; -}; - -/*[register] IN_FLOW_TBL_OP_DATA7*/ -#define IN_FLOW_TBL_OP_DATA7 -#define IN_FLOW_TBL_OP_DATA7_ADDRESS 0x3dc -#define IN_FLOW_TBL_OP_DATA7_NUM 1 -#define IN_FLOW_TBL_OP_DATA7_INC 0x4 -#define IN_FLOW_TBL_OP_DATA7_TYPE REG_TYPE_RW -#define IN_FLOW_TBL_OP_DATA7_DEFAULT 0x0 - /*[field] DATA*/ - #define IN_FLOW_TBL_OP_DATA7_DATA - #define IN_FLOW_TBL_OP_DATA7_DATA_OFFSET 0 - #define IN_FLOW_TBL_OP_DATA7_DATA_LEN 32 - #define IN_FLOW_TBL_OP_DATA7_DATA_DEFAULT 0x0 - -struct in_flow_tbl_op_data7 { - a_uint32_t data:32; -}; - -union in_flow_tbl_op_data7_u { - a_uint32_t val; - struct in_flow_tbl_op_data7 bf; -}; - -/*[register] IN_FLOW_TBL_OP_DATA8*/ -#define IN_FLOW_TBL_OP_DATA8 -#define IN_FLOW_TBL_OP_DATA8_ADDRESS 0x3e0 -#define IN_FLOW_TBL_OP_DATA8_NUM 1 -#define IN_FLOW_TBL_OP_DATA8_INC 0x4 -#define IN_FLOW_TBL_OP_DATA8_TYPE REG_TYPE_RW -#define IN_FLOW_TBL_OP_DATA8_DEFAULT 0x0 - /*[field] DATA*/ - #define IN_FLOW_TBL_OP_DATA8_DATA - #define IN_FLOW_TBL_OP_DATA8_DATA_OFFSET 0 - #define IN_FLOW_TBL_OP_DATA8_DATA_LEN 32 - #define IN_FLOW_TBL_OP_DATA8_DATA_DEFAULT 0x0 - -struct in_flow_tbl_op_data8 { - a_uint32_t data:32; -}; - -union in_flow_tbl_op_data8_u { - a_uint32_t val; - struct in_flow_tbl_op_data8 bf; -}; - -/*[register] FLOW_HOST_TBL_OP_DATA0*/ -#define FLOW_HOST_TBL_OP_DATA0 -#define FLOW_HOST_TBL_OP_DATA0_ADDRESS 0x3e4 -#define FLOW_HOST_TBL_OP_DATA0_NUM 1 -#define FLOW_HOST_TBL_OP_DATA0_INC 0x4 -#define FLOW_HOST_TBL_OP_DATA0_TYPE REG_TYPE_RW -#define FLOW_HOST_TBL_OP_DATA0_DEFAULT 0x0 - /*[field] DATA*/ - #define FLOW_HOST_TBL_OP_DATA0_DATA - #define FLOW_HOST_TBL_OP_DATA0_DATA_OFFSET 0 - #define FLOW_HOST_TBL_OP_DATA0_DATA_LEN 32 - #define FLOW_HOST_TBL_OP_DATA0_DATA_DEFAULT 0x0 - -struct flow_host_tbl_op_data0 { - a_uint32_t data:32; -}; - -union flow_host_tbl_op_data0_u { - a_uint32_t val; - struct flow_host_tbl_op_data0 bf; -}; - -/*[register] FLOW_HOST_TBL_OP_DATA1*/ -#define FLOW_HOST_TBL_OP_DATA1 -#define FLOW_HOST_TBL_OP_DATA1_ADDRESS 0x3e8 -#define FLOW_HOST_TBL_OP_DATA1_NUM 1 -#define FLOW_HOST_TBL_OP_DATA1_INC 0x4 -#define FLOW_HOST_TBL_OP_DATA1_TYPE REG_TYPE_RW -#define FLOW_HOST_TBL_OP_DATA1_DEFAULT 0x0 - /*[field] DATA*/ - #define FLOW_HOST_TBL_OP_DATA1_DATA - #define FLOW_HOST_TBL_OP_DATA1_DATA_OFFSET 0 - #define FLOW_HOST_TBL_OP_DATA1_DATA_LEN 32 - #define FLOW_HOST_TBL_OP_DATA1_DATA_DEFAULT 0x0 - -struct flow_host_tbl_op_data1 { - a_uint32_t data:32; -}; - -union flow_host_tbl_op_data1_u { - a_uint32_t val; - struct flow_host_tbl_op_data1 bf; -}; - -/*[register] FLOW_HOST_TBL_OP_DATA2*/ -#define FLOW_HOST_TBL_OP_DATA2 -#define FLOW_HOST_TBL_OP_DATA2_ADDRESS 0x3ec -#define FLOW_HOST_TBL_OP_DATA2_NUM 1 -#define FLOW_HOST_TBL_OP_DATA2_INC 0x4 -#define FLOW_HOST_TBL_OP_DATA2_TYPE REG_TYPE_RW -#define FLOW_HOST_TBL_OP_DATA2_DEFAULT 0x0 - /*[field] DATA*/ - #define FLOW_HOST_TBL_OP_DATA2_DATA - #define FLOW_HOST_TBL_OP_DATA2_DATA_OFFSET 0 - #define FLOW_HOST_TBL_OP_DATA2_DATA_LEN 32 - #define FLOW_HOST_TBL_OP_DATA2_DATA_DEFAULT 0x0 - -struct flow_host_tbl_op_data2 { - a_uint32_t data:32; -}; - -union flow_host_tbl_op_data2_u { - a_uint32_t val; - struct flow_host_tbl_op_data2 bf; -}; - -/*[register] FLOW_HOST_TBL_OP_DATA3*/ -#define FLOW_HOST_TBL_OP_DATA3 -#define FLOW_HOST_TBL_OP_DATA3_ADDRESS 0x3f0 -#define FLOW_HOST_TBL_OP_DATA3_NUM 1 -#define FLOW_HOST_TBL_OP_DATA3_INC 0x4 -#define FLOW_HOST_TBL_OP_DATA3_TYPE REG_TYPE_RW -#define FLOW_HOST_TBL_OP_DATA3_DEFAULT 0x0 - /*[field] DATA*/ - #define FLOW_HOST_TBL_OP_DATA3_DATA - #define FLOW_HOST_TBL_OP_DATA3_DATA_OFFSET 0 - #define FLOW_HOST_TBL_OP_DATA3_DATA_LEN 32 - #define FLOW_HOST_TBL_OP_DATA3_DATA_DEFAULT 0x0 - -struct flow_host_tbl_op_data3 { - a_uint32_t data:32; -}; - -union flow_host_tbl_op_data3_u { - a_uint32_t val; - struct flow_host_tbl_op_data3 bf; -}; - -/*[register] FLOW_HOST_TBL_OP_DATA4*/ -#define FLOW_HOST_TBL_OP_DATA4 -#define FLOW_HOST_TBL_OP_DATA4_ADDRESS 0x3f4 -#define FLOW_HOST_TBL_OP_DATA4_NUM 1 -#define FLOW_HOST_TBL_OP_DATA4_INC 0x4 -#define FLOW_HOST_TBL_OP_DATA4_TYPE REG_TYPE_RW -#define FLOW_HOST_TBL_OP_DATA4_DEFAULT 0x0 - /*[field] DATA*/ - #define FLOW_HOST_TBL_OP_DATA4_DATA - #define FLOW_HOST_TBL_OP_DATA4_DATA_OFFSET 0 - #define FLOW_HOST_TBL_OP_DATA4_DATA_LEN 32 - #define FLOW_HOST_TBL_OP_DATA4_DATA_DEFAULT 0x0 - -struct flow_host_tbl_op_data4 { - a_uint32_t data:32; -}; - -union flow_host_tbl_op_data4_u { - a_uint32_t val; - struct flow_host_tbl_op_data4 bf; -}; - -/*[register] FLOW_HOST_TBL_OP_DATA5*/ -#define FLOW_HOST_TBL_OP_DATA5 -#define FLOW_HOST_TBL_OP_DATA5_ADDRESS 0x3f8 -#define FLOW_HOST_TBL_OP_DATA5_NUM 1 -#define FLOW_HOST_TBL_OP_DATA5_INC 0x4 -#define FLOW_HOST_TBL_OP_DATA5_TYPE REG_TYPE_RW -#define FLOW_HOST_TBL_OP_DATA5_DEFAULT 0x0 - /*[field] DATA*/ - #define FLOW_HOST_TBL_OP_DATA5_DATA - #define FLOW_HOST_TBL_OP_DATA5_DATA_OFFSET 0 - #define FLOW_HOST_TBL_OP_DATA5_DATA_LEN 32 - #define FLOW_HOST_TBL_OP_DATA5_DATA_DEFAULT 0x0 - -struct flow_host_tbl_op_data5 { - a_uint32_t data:32; -}; - -union flow_host_tbl_op_data5_u { - a_uint32_t val; - struct flow_host_tbl_op_data5 bf; -}; - -/*[register] FLOW_HOST_TBL_OP_DATA6*/ -#define FLOW_HOST_TBL_OP_DATA6 -#define FLOW_HOST_TBL_OP_DATA6_ADDRESS 0x3fc -#define FLOW_HOST_TBL_OP_DATA6_NUM 1 -#define FLOW_HOST_TBL_OP_DATA6_INC 0x4 -#define FLOW_HOST_TBL_OP_DATA6_TYPE REG_TYPE_RW -#define FLOW_HOST_TBL_OP_DATA6_DEFAULT 0x0 - /*[field] DATA*/ - #define FLOW_HOST_TBL_OP_DATA6_DATA - #define FLOW_HOST_TBL_OP_DATA6_DATA_OFFSET 0 - #define FLOW_HOST_TBL_OP_DATA6_DATA_LEN 32 - #define FLOW_HOST_TBL_OP_DATA6_DATA_DEFAULT 0x0 - -struct flow_host_tbl_op_data6 { - a_uint32_t data:32; -}; - -union flow_host_tbl_op_data6_u { - a_uint32_t val; - struct flow_host_tbl_op_data6 bf; -}; - -/*[register] FLOW_HOST_TBL_OP_DATA7*/ -#define FLOW_HOST_TBL_OP_DATA7 -#define FLOW_HOST_TBL_OP_DATA7_ADDRESS 0x400 -#define FLOW_HOST_TBL_OP_DATA7_NUM 1 -#define FLOW_HOST_TBL_OP_DATA7_INC 0x4 -#define FLOW_HOST_TBL_OP_DATA7_TYPE REG_TYPE_RW -#define FLOW_HOST_TBL_OP_DATA7_DEFAULT 0x0 - /*[field] DATA*/ - #define FLOW_HOST_TBL_OP_DATA7_DATA - #define FLOW_HOST_TBL_OP_DATA7_DATA_OFFSET 0 - #define FLOW_HOST_TBL_OP_DATA7_DATA_LEN 32 - #define FLOW_HOST_TBL_OP_DATA7_DATA_DEFAULT 0x0 - -struct flow_host_tbl_op_data7 { - a_uint32_t data:32; -}; - -union flow_host_tbl_op_data7_u { - a_uint32_t val; - struct flow_host_tbl_op_data7 bf; -}; - -/*[register] FLOW_HOST_TBL_OP_DATA8*/ -#define FLOW_HOST_TBL_OP_DATA8 -#define FLOW_HOST_TBL_OP_DATA8_ADDRESS 0x404 -#define FLOW_HOST_TBL_OP_DATA8_NUM 1 -#define FLOW_HOST_TBL_OP_DATA8_INC 0x4 -#define FLOW_HOST_TBL_OP_DATA8_TYPE REG_TYPE_RW -#define FLOW_HOST_TBL_OP_DATA8_DEFAULT 0x0 - /*[field] DATA*/ - #define FLOW_HOST_TBL_OP_DATA8_DATA - #define FLOW_HOST_TBL_OP_DATA8_DATA_OFFSET 0 - #define FLOW_HOST_TBL_OP_DATA8_DATA_LEN 32 - #define FLOW_HOST_TBL_OP_DATA8_DATA_DEFAULT 0x0 - -struct flow_host_tbl_op_data8 { - a_uint32_t data:32; -}; - -union flow_host_tbl_op_data8_u { - a_uint32_t val; - struct flow_host_tbl_op_data8 bf; -}; - -/*[register] FLOW_HOST_TBL_OP_DATA9*/ -#define FLOW_HOST_TBL_OP_DATA9 -#define FLOW_HOST_TBL_OP_DATA9_ADDRESS 0x408 -#define FLOW_HOST_TBL_OP_DATA9_NUM 1 -#define FLOW_HOST_TBL_OP_DATA9_INC 0x4 -#define FLOW_HOST_TBL_OP_DATA9_TYPE REG_TYPE_RW -#define FLOW_HOST_TBL_OP_DATA9_DEFAULT 0x0 - /*[field] DATA*/ - #define FLOW_HOST_TBL_OP_DATA9_DATA - #define FLOW_HOST_TBL_OP_DATA9_DATA_OFFSET 0 - #define FLOW_HOST_TBL_OP_DATA9_DATA_LEN 32 - #define FLOW_HOST_TBL_OP_DATA9_DATA_DEFAULT 0x0 - -struct flow_host_tbl_op_data9 { - a_uint32_t data:32; -}; - -union flow_host_tbl_op_data9_u { - a_uint32_t val; - struct flow_host_tbl_op_data9 bf; -}; - -/*[register] IN_FLOW_TBL_OP_RSLT*/ -#define IN_FLOW_TBL_OP_RSLT -#define IN_FLOW_TBL_OP_RSLT_ADDRESS 0x40c -#define IN_FLOW_TBL_OP_RSLT_NUM 1 -#define IN_FLOW_TBL_OP_RSLT_INC 0x4 -#define IN_FLOW_TBL_OP_RSLT_TYPE REG_TYPE_RO -#define IN_FLOW_TBL_OP_RSLT_DEFAULT 0x0 - /*[field] CMD_ID*/ - #define IN_FLOW_TBL_OP_RSLT_CMD_ID - #define IN_FLOW_TBL_OP_RSLT_CMD_ID_OFFSET 0 - #define IN_FLOW_TBL_OP_RSLT_CMD_ID_LEN 4 - #define IN_FLOW_TBL_OP_RSLT_CMD_ID_DEFAULT 0x0 - /*[field] OP_RSLT*/ - #define IN_FLOW_TBL_OP_RSLT_OP_RSLT - #define IN_FLOW_TBL_OP_RSLT_OP_RSLT_OFFSET 4 - #define IN_FLOW_TBL_OP_RSLT_OP_RSLT_LEN 1 - #define IN_FLOW_TBL_OP_RSLT_OP_RSLT_DEFAULT 0x0 - /*[field] FLOW_ENTRY_INDEX*/ - #define IN_FLOW_TBL_OP_RSLT_FLOW_ENTRY_INDEX - #define IN_FLOW_TBL_OP_RSLT_FLOW_ENTRY_INDEX_OFFSET 5 - #define IN_FLOW_TBL_OP_RSLT_FLOW_ENTRY_INDEX_LEN 12 - #define IN_FLOW_TBL_OP_RSLT_FLOW_ENTRY_INDEX_DEFAULT 0x0 - /*[field] VALID_CNT*/ - #define IN_FLOW_TBL_OP_RSLT_VALID_CNT - #define IN_FLOW_TBL_OP_RSLT_VALID_CNT_OFFSET 17 - #define IN_FLOW_TBL_OP_RSLT_VALID_CNT_LEN 4 - #define IN_FLOW_TBL_OP_RSLT_VALID_CNT_DEFAULT 0x0 - -struct in_flow_tbl_op_rslt { - a_uint32_t cmd_id:4; - a_uint32_t op_rslt:1; - a_uint32_t flow_entry_index:12; - a_uint32_t valid_cnt:4; - a_uint32_t _reserved0:11; -}; - -union in_flow_tbl_op_rslt_u { - a_uint32_t val; - struct in_flow_tbl_op_rslt bf; -}; - -/*[register] FLOW_HOST_TBL_OP_RSLT*/ -#define FLOW_HOST_TBL_OP_RSLT -#define FLOW_HOST_TBL_OP_RSLT_ADDRESS 0x410 -#define FLOW_HOST_TBL_OP_RSLT_NUM 1 -#define FLOW_HOST_TBL_OP_RSLT_INC 0x4 -#define FLOW_HOST_TBL_OP_RSLT_TYPE REG_TYPE_RO -#define FLOW_HOST_TBL_OP_RSLT_DEFAULT 0x0 - /*[field] HOST_ENTRY_INDEX*/ - #define FLOW_HOST_TBL_OP_RSLT_HOST_ENTRY_INDEX - #define FLOW_HOST_TBL_OP_RSLT_HOST_ENTRY_INDEX_OFFSET 0 - #define FLOW_HOST_TBL_OP_RSLT_HOST_ENTRY_INDEX_LEN 13 - #define FLOW_HOST_TBL_OP_RSLT_HOST_ENTRY_INDEX_DEFAULT 0x0 - -struct flow_host_tbl_op_rslt { - a_uint32_t host_entry_index:13; - a_uint32_t _reserved0:19; -}; - -union flow_host_tbl_op_rslt_u { - a_uint32_t val; - struct flow_host_tbl_op_rslt bf; -}; - -/*[register] IN_FLOW_TBL_RD_OP*/ -#define IN_FLOW_TBL_RD_OP -#define IN_FLOW_TBL_RD_OP_ADDRESS 0x414 -#define IN_FLOW_TBL_RD_OP_NUM 1 -#define IN_FLOW_TBL_RD_OP_INC 0x4 -#define IN_FLOW_TBL_RD_OP_TYPE REG_TYPE_RW -#define IN_FLOW_TBL_RD_OP_DEFAULT 0x0 - /*[field] CMD_ID*/ - #define IN_FLOW_TBL_RD_OP_CMD_ID - #define IN_FLOW_TBL_RD_OP_CMD_ID_OFFSET 0 - #define IN_FLOW_TBL_RD_OP_CMD_ID_LEN 4 - #define IN_FLOW_TBL_RD_OP_CMD_ID_DEFAULT 0x0 - /*[field] BYP_RSLT_EN*/ - #define IN_FLOW_TBL_RD_OP_BYP_RSLT_EN - #define IN_FLOW_TBL_RD_OP_BYP_RSLT_EN_OFFSET 4 - #define IN_FLOW_TBL_RD_OP_BYP_RSLT_EN_LEN 1 - #define IN_FLOW_TBL_RD_OP_BYP_RSLT_EN_DEFAULT 0x0 - /*[field] OP_TYPE*/ - #define IN_FLOW_TBL_RD_OP_OP_TYPE - #define IN_FLOW_TBL_RD_OP_OP_TYPE_OFFSET 5 - #define IN_FLOW_TBL_RD_OP_OP_TYPE_LEN 3 - #define IN_FLOW_TBL_RD_OP_OP_TYPE_DEFAULT 0x0 - /*[field] HASH_BLOCK_BITMAP*/ - #define IN_FLOW_TBL_RD_OP_HASH_BLOCK_BITMAP - #define IN_FLOW_TBL_RD_OP_HASH_BLOCK_BITMAP_OFFSET 8 - #define IN_FLOW_TBL_RD_OP_HASH_BLOCK_BITMAP_LEN 2 - #define IN_FLOW_TBL_RD_OP_HASH_BLOCK_BITMAP_DEFAULT 0x0 - /*[field] OP_MODE*/ - #define IN_FLOW_TBL_RD_OP_OP_MODE - #define IN_FLOW_TBL_RD_OP_OP_MODE_OFFSET 10 - #define IN_FLOW_TBL_RD_OP_OP_MODE_LEN 1 - #define IN_FLOW_TBL_RD_OP_OP_MODE_DEFAULT 0x0 - /*[field] OP_HOST_EN*/ - #define IN_FLOW_TBL_RD_OP_OP_HOST_EN - #define IN_FLOW_TBL_RD_OP_OP_HOST_EN_OFFSET 11 - #define IN_FLOW_TBL_RD_OP_OP_HOST_EN_LEN 1 - #define IN_FLOW_TBL_RD_OP_OP_HOST_EN_DEFAULT 0x0 - /*[field] ENTRY_INDEX*/ - #define IN_FLOW_TBL_RD_OP_ENTRY_INDEX - #define IN_FLOW_TBL_RD_OP_ENTRY_INDEX_OFFSET 12 - #define IN_FLOW_TBL_RD_OP_ENTRY_INDEX_LEN 12 - #define IN_FLOW_TBL_RD_OP_ENTRY_INDEX_DEFAULT 0x0 - /*[field] OP_RESULT*/ - #define IN_FLOW_TBL_RD_OP_OP_RESULT - #define IN_FLOW_TBL_RD_OP_OP_RESULT_OFFSET 24 - #define IN_FLOW_TBL_RD_OP_OP_RESULT_LEN 1 - #define IN_FLOW_TBL_RD_OP_OP_RESULT_DEFAULT 0x0 - /*[field] BUSY*/ - #define IN_FLOW_TBL_RD_OP_BUSY - #define IN_FLOW_TBL_RD_OP_BUSY_OFFSET 25 - #define IN_FLOW_TBL_RD_OP_BUSY_LEN 1 - #define IN_FLOW_TBL_RD_OP_BUSY_DEFAULT 0x0 - -struct in_flow_tbl_rd_op { - a_uint32_t cmd_id:4; - a_uint32_t byp_rslt_en:1; - a_uint32_t op_type:3; - a_uint32_t hash_block_bitmap:2; - a_uint32_t op_mode:1; - a_uint32_t op_host_en:1; - a_uint32_t entry_index:12; - a_uint32_t op_result:1; - a_uint32_t busy:1; - a_uint32_t _reserved0:6; -}; - -union in_flow_tbl_rd_op_u { - a_uint32_t val; - struct in_flow_tbl_rd_op bf; -}; - -/*[register] IN_FLOW_HOST_TBL_RD_OP*/ -#define IN_FLOW_HOST_TBL_RD_OP -#define IN_FLOW_HOST_TBL_RD_OP_ADDRESS 0x418 -#define IN_FLOW_HOST_TBL_RD_OP_NUM 1 -#define IN_FLOW_HOST_TBL_RD_OP_INC 0x4 -#define IN_FLOW_HOST_TBL_RD_OP_TYPE REG_TYPE_RW -#define IN_FLOW_HOST_TBL_RD_OP_DEFAULT 0x0 - /*[field] HASH_BLOCK_BITMAP*/ - #define IN_FLOW_HOST_TBL_RD_OP_HASH_BLOCK_BITMAP - #define IN_FLOW_HOST_TBL_RD_OP_HASH_BLOCK_BITMAP_OFFSET 0 - #define IN_FLOW_HOST_TBL_RD_OP_HASH_BLOCK_BITMAP_LEN 2 - #define IN_FLOW_HOST_TBL_RD_OP_HASH_BLOCK_BITMAP_DEFAULT 0x0 - /*[field] HOST_ENTRY_INDEX*/ - #define IN_FLOW_HOST_TBL_RD_OP_HOST_ENTRY_INDEX - #define IN_FLOW_HOST_TBL_RD_OP_HOST_ENTRY_INDEX_OFFSET 2 - #define IN_FLOW_HOST_TBL_RD_OP_HOST_ENTRY_INDEX_LEN 13 - #define IN_FLOW_HOST_TBL_RD_OP_HOST_ENTRY_INDEX_DEFAULT 0x0 - -struct in_flow_host_tbl_rd_op { - a_uint32_t hash_block_bitmap:2; - a_uint32_t host_entry_index:13; - a_uint32_t _reserved0:17; -}; - -union in_flow_host_tbl_rd_op_u { - a_uint32_t val; - struct in_flow_host_tbl_rd_op bf; -}; - -/*[register] IN_FLOW_TBL_RD_OP_DATA0*/ -#define IN_FLOW_TBL_RD_OP_DATA0 -#define IN_FLOW_TBL_RD_OP_DATA0_ADDRESS 0x41c -#define IN_FLOW_TBL_RD_OP_DATA0_NUM 1 -#define IN_FLOW_TBL_RD_OP_DATA0_INC 0x4 -#define IN_FLOW_TBL_RD_OP_DATA0_TYPE REG_TYPE_RW -#define IN_FLOW_TBL_RD_OP_DATA0_DEFAULT 0x0 - /*[field] DATA*/ - #define IN_FLOW_TBL_RD_OP_DATA0_DATA - #define IN_FLOW_TBL_RD_OP_DATA0_DATA_OFFSET 0 - #define IN_FLOW_TBL_RD_OP_DATA0_DATA_LEN 32 - #define IN_FLOW_TBL_RD_OP_DATA0_DATA_DEFAULT 0x0 - -struct in_flow_tbl_rd_op_data0 { - a_uint32_t data:32; -}; - -union in_flow_tbl_rd_op_data0_u { - a_uint32_t val; - struct in_flow_tbl_rd_op_data0 bf; -}; - -/*[register] IN_FLOW_TBL_RD_OP_DATA1*/ -#define IN_FLOW_TBL_RD_OP_DATA1 -#define IN_FLOW_TBL_RD_OP_DATA1_ADDRESS 0x420 -#define IN_FLOW_TBL_RD_OP_DATA1_NUM 1 -#define IN_FLOW_TBL_RD_OP_DATA1_INC 0x4 -#define IN_FLOW_TBL_RD_OP_DATA1_TYPE REG_TYPE_RW -#define IN_FLOW_TBL_RD_OP_DATA1_DEFAULT 0x0 - /*[field] DATA*/ - #define IN_FLOW_TBL_RD_OP_DATA1_DATA - #define IN_FLOW_TBL_RD_OP_DATA1_DATA_OFFSET 0 - #define IN_FLOW_TBL_RD_OP_DATA1_DATA_LEN 32 - #define IN_FLOW_TBL_RD_OP_DATA1_DATA_DEFAULT 0x0 - -struct in_flow_tbl_rd_op_data1 { - a_uint32_t data:32; -}; - -union in_flow_tbl_rd_op_data1_u { - a_uint32_t val; - struct in_flow_tbl_rd_op_data1 bf; -}; - -/*[register] IN_FLOW_TBL_RD_OP_DATA2*/ -#define IN_FLOW_TBL_RD_OP_DATA2 -#define IN_FLOW_TBL_RD_OP_DATA2_ADDRESS 0x424 -#define IN_FLOW_TBL_RD_OP_DATA2_NUM 1 -#define IN_FLOW_TBL_RD_OP_DATA2_INC 0x4 -#define IN_FLOW_TBL_RD_OP_DATA2_TYPE REG_TYPE_RW -#define IN_FLOW_TBL_RD_OP_DATA2_DEFAULT 0x0 - /*[field] DATA*/ - #define IN_FLOW_TBL_RD_OP_DATA2_DATA - #define IN_FLOW_TBL_RD_OP_DATA2_DATA_OFFSET 0 - #define IN_FLOW_TBL_RD_OP_DATA2_DATA_LEN 32 - #define IN_FLOW_TBL_RD_OP_DATA2_DATA_DEFAULT 0x0 - -struct in_flow_tbl_rd_op_data2 { - a_uint32_t data:32; -}; - -union in_flow_tbl_rd_op_data2_u { - a_uint32_t val; - struct in_flow_tbl_rd_op_data2 bf; -}; - -/*[register] IN_FLOW_TBL_RD_OP_DATA3*/ -#define IN_FLOW_TBL_RD_OP_DATA3 -#define IN_FLOW_TBL_RD_OP_DATA3_ADDRESS 0x428 -#define IN_FLOW_TBL_RD_OP_DATA3_NUM 1 -#define IN_FLOW_TBL_RD_OP_DATA3_INC 0x4 -#define IN_FLOW_TBL_RD_OP_DATA3_TYPE REG_TYPE_RW -#define IN_FLOW_TBL_RD_OP_DATA3_DEFAULT 0x0 - /*[field] DATA*/ - #define IN_FLOW_TBL_RD_OP_DATA3_DATA - #define IN_FLOW_TBL_RD_OP_DATA3_DATA_OFFSET 0 - #define IN_FLOW_TBL_RD_OP_DATA3_DATA_LEN 32 - #define IN_FLOW_TBL_RD_OP_DATA3_DATA_DEFAULT 0x0 - -struct in_flow_tbl_rd_op_data3 { - a_uint32_t data:32; -}; - -union in_flow_tbl_rd_op_data3_u { - a_uint32_t val; - struct in_flow_tbl_rd_op_data3 bf; -}; - -/*[register] IN_FLOW_TBL_RD_OP_DATA4*/ -#define IN_FLOW_TBL_RD_OP_DATA4 -#define IN_FLOW_TBL_RD_OP_DATA4_ADDRESS 0x42c -#define IN_FLOW_TBL_RD_OP_DATA4_NUM 1 -#define IN_FLOW_TBL_RD_OP_DATA4_INC 0x4 -#define IN_FLOW_TBL_RD_OP_DATA4_TYPE REG_TYPE_RW -#define IN_FLOW_TBL_RD_OP_DATA4_DEFAULT 0x0 - /*[field] DATA*/ - #define IN_FLOW_TBL_RD_OP_DATA4_DATA - #define IN_FLOW_TBL_RD_OP_DATA4_DATA_OFFSET 0 - #define IN_FLOW_TBL_RD_OP_DATA4_DATA_LEN 32 - #define IN_FLOW_TBL_RD_OP_DATA4_DATA_DEFAULT 0x0 - -struct in_flow_tbl_rd_op_data4 { - a_uint32_t data:32; -}; - -union in_flow_tbl_rd_op_data4_u { - a_uint32_t val; - struct in_flow_tbl_rd_op_data4 bf; -}; - -/*[register] IN_FLOW_TBL_RD_OP_DATA5*/ -#define IN_FLOW_TBL_RD_OP_DATA5 -#define IN_FLOW_TBL_RD_OP_DATA5_ADDRESS 0x430 -#define IN_FLOW_TBL_RD_OP_DATA5_NUM 1 -#define IN_FLOW_TBL_RD_OP_DATA5_INC 0x4 -#define IN_FLOW_TBL_RD_OP_DATA5_TYPE REG_TYPE_RW -#define IN_FLOW_TBL_RD_OP_DATA5_DEFAULT 0x0 - /*[field] DATA*/ - #define IN_FLOW_TBL_RD_OP_DATA5_DATA - #define IN_FLOW_TBL_RD_OP_DATA5_DATA_OFFSET 0 - #define IN_FLOW_TBL_RD_OP_DATA5_DATA_LEN 32 - #define IN_FLOW_TBL_RD_OP_DATA5_DATA_DEFAULT 0x0 - -struct in_flow_tbl_rd_op_data5 { - a_uint32_t data:32; -}; - -union in_flow_tbl_rd_op_data5_u { - a_uint32_t val; - struct in_flow_tbl_rd_op_data5 bf; -}; - -/*[register] IN_FLOW_TBL_RD_OP_DATA6*/ -#define IN_FLOW_TBL_RD_OP_DATA6 -#define IN_FLOW_TBL_RD_OP_DATA6_ADDRESS 0x434 -#define IN_FLOW_TBL_RD_OP_DATA6_NUM 1 -#define IN_FLOW_TBL_RD_OP_DATA6_INC 0x4 -#define IN_FLOW_TBL_RD_OP_DATA6_TYPE REG_TYPE_RW -#define IN_FLOW_TBL_RD_OP_DATA6_DEFAULT 0x0 - /*[field] DATA*/ - #define IN_FLOW_TBL_RD_OP_DATA6_DATA - #define IN_FLOW_TBL_RD_OP_DATA6_DATA_OFFSET 0 - #define IN_FLOW_TBL_RD_OP_DATA6_DATA_LEN 32 - #define IN_FLOW_TBL_RD_OP_DATA6_DATA_DEFAULT 0x0 - -struct in_flow_tbl_rd_op_data6 { - a_uint32_t data:32; -}; - -union in_flow_tbl_rd_op_data6_u { - a_uint32_t val; - struct in_flow_tbl_rd_op_data6 bf; -}; - -/*[register] IN_FLOW_TBL_RD_OP_DATA7*/ -#define IN_FLOW_TBL_RD_OP_DATA7 -#define IN_FLOW_TBL_RD_OP_DATA7_ADDRESS 0x438 -#define IN_FLOW_TBL_RD_OP_DATA7_NUM 1 -#define IN_FLOW_TBL_RD_OP_DATA7_INC 0x4 -#define IN_FLOW_TBL_RD_OP_DATA7_TYPE REG_TYPE_RW -#define IN_FLOW_TBL_RD_OP_DATA7_DEFAULT 0x0 - /*[field] DATA*/ - #define IN_FLOW_TBL_RD_OP_DATA7_DATA - #define IN_FLOW_TBL_RD_OP_DATA7_DATA_OFFSET 0 - #define IN_FLOW_TBL_RD_OP_DATA7_DATA_LEN 32 - #define IN_FLOW_TBL_RD_OP_DATA7_DATA_DEFAULT 0x0 - -struct in_flow_tbl_rd_op_data7 { - a_uint32_t data:32; -}; - -union in_flow_tbl_rd_op_data7_u { - a_uint32_t val; - struct in_flow_tbl_rd_op_data7 bf; -}; - -/*[register] IN_FLOW_TBL_RD_OP_DATA8*/ -#define IN_FLOW_TBL_RD_OP_DATA8 -#define IN_FLOW_TBL_RD_OP_DATA8_ADDRESS 0x43c -#define IN_FLOW_TBL_RD_OP_DATA8_NUM 1 -#define IN_FLOW_TBL_RD_OP_DATA8_INC 0x4 -#define IN_FLOW_TBL_RD_OP_DATA8_TYPE REG_TYPE_RW -#define IN_FLOW_TBL_RD_OP_DATA8_DEFAULT 0x0 - /*[field] DATA*/ - #define IN_FLOW_TBL_RD_OP_DATA8_DATA - #define IN_FLOW_TBL_RD_OP_DATA8_DATA_OFFSET 0 - #define IN_FLOW_TBL_RD_OP_DATA8_DATA_LEN 32 - #define IN_FLOW_TBL_RD_OP_DATA8_DATA_DEFAULT 0x0 - -struct in_flow_tbl_rd_op_data8 { - a_uint32_t data:32; -}; - -union in_flow_tbl_rd_op_data8_u { - a_uint32_t val; - struct in_flow_tbl_rd_op_data8 bf; -}; - -/*[register] FLOW_HOST_TBL_RD_OP_DATA0*/ -#define FLOW_HOST_TBL_RD_OP_DATA0 -#define FLOW_HOST_TBL_RD_OP_DATA0_ADDRESS 0x440 -#define FLOW_HOST_TBL_RD_OP_DATA0_NUM 1 -#define FLOW_HOST_TBL_RD_OP_DATA0_INC 0x4 -#define FLOW_HOST_TBL_RD_OP_DATA0_TYPE REG_TYPE_RW -#define FLOW_HOST_TBL_RD_OP_DATA0_DEFAULT 0x0 - /*[field] DATA*/ - #define FLOW_HOST_TBL_RD_OP_DATA0_DATA - #define FLOW_HOST_TBL_RD_OP_DATA0_DATA_OFFSET 0 - #define FLOW_HOST_TBL_RD_OP_DATA0_DATA_LEN 32 - #define FLOW_HOST_TBL_RD_OP_DATA0_DATA_DEFAULT 0x0 - -struct flow_host_tbl_rd_op_data0 { - a_uint32_t data:32; -}; - -union flow_host_tbl_rd_op_data0_u { - a_uint32_t val; - struct flow_host_tbl_rd_op_data0 bf; -}; - -/*[register] FLOW_HOST_TBL_RD_OP_DATA1*/ -#define FLOW_HOST_TBL_RD_OP_DATA1 -#define FLOW_HOST_TBL_RD_OP_DATA1_ADDRESS 0x444 -#define FLOW_HOST_TBL_RD_OP_DATA1_NUM 1 -#define FLOW_HOST_TBL_RD_OP_DATA1_INC 0x4 -#define FLOW_HOST_TBL_RD_OP_DATA1_TYPE REG_TYPE_RW -#define FLOW_HOST_TBL_RD_OP_DATA1_DEFAULT 0x0 - /*[field] DATA*/ - #define FLOW_HOST_TBL_RD_OP_DATA1_DATA - #define FLOW_HOST_TBL_RD_OP_DATA1_DATA_OFFSET 0 - #define FLOW_HOST_TBL_RD_OP_DATA1_DATA_LEN 32 - #define FLOW_HOST_TBL_RD_OP_DATA1_DATA_DEFAULT 0x0 - -struct flow_host_tbl_rd_op_data1 { - a_uint32_t data:32; -}; - -union flow_host_tbl_rd_op_data1_u { - a_uint32_t val; - struct flow_host_tbl_rd_op_data1 bf; -}; - -/*[register] FLOW_HOST_TBL_RD_OP_DATA2*/ -#define FLOW_HOST_TBL_RD_OP_DATA2 -#define FLOW_HOST_TBL_RD_OP_DATA2_ADDRESS 0x448 -#define FLOW_HOST_TBL_RD_OP_DATA2_NUM 1 -#define FLOW_HOST_TBL_RD_OP_DATA2_INC 0x4 -#define FLOW_HOST_TBL_RD_OP_DATA2_TYPE REG_TYPE_RW -#define FLOW_HOST_TBL_RD_OP_DATA2_DEFAULT 0x0 - /*[field] DATA*/ - #define FLOW_HOST_TBL_RD_OP_DATA2_DATA - #define FLOW_HOST_TBL_RD_OP_DATA2_DATA_OFFSET 0 - #define FLOW_HOST_TBL_RD_OP_DATA2_DATA_LEN 32 - #define FLOW_HOST_TBL_RD_OP_DATA2_DATA_DEFAULT 0x0 - -struct flow_host_tbl_rd_op_data2 { - a_uint32_t data:32; -}; - -union flow_host_tbl_rd_op_data2_u { - a_uint32_t val; - struct flow_host_tbl_rd_op_data2 bf; -}; - -/*[register] FLOW_HOST_TBL_RD_OP_DATA3*/ -#define FLOW_HOST_TBL_RD_OP_DATA3 -#define FLOW_HOST_TBL_RD_OP_DATA3_ADDRESS 0x44c -#define FLOW_HOST_TBL_RD_OP_DATA3_NUM 1 -#define FLOW_HOST_TBL_RD_OP_DATA3_INC 0x4 -#define FLOW_HOST_TBL_RD_OP_DATA3_TYPE REG_TYPE_RW -#define FLOW_HOST_TBL_RD_OP_DATA3_DEFAULT 0x0 - /*[field] DATA*/ - #define FLOW_HOST_TBL_RD_OP_DATA3_DATA - #define FLOW_HOST_TBL_RD_OP_DATA3_DATA_OFFSET 0 - #define FLOW_HOST_TBL_RD_OP_DATA3_DATA_LEN 32 - #define FLOW_HOST_TBL_RD_OP_DATA3_DATA_DEFAULT 0x0 - -struct flow_host_tbl_rd_op_data3 { - a_uint32_t data:32; -}; - -union flow_host_tbl_rd_op_data3_u { - a_uint32_t val; - struct flow_host_tbl_rd_op_data3 bf; -}; - -/*[register] FLOW_HOST_TBL_RD_OP_DATA4*/ -#define FLOW_HOST_TBL_RD_OP_DATA4 -#define FLOW_HOST_TBL_RD_OP_DATA4_ADDRESS 0x450 -#define FLOW_HOST_TBL_RD_OP_DATA4_NUM 1 -#define FLOW_HOST_TBL_RD_OP_DATA4_INC 0x4 -#define FLOW_HOST_TBL_RD_OP_DATA4_TYPE REG_TYPE_RW -#define FLOW_HOST_TBL_RD_OP_DATA4_DEFAULT 0x0 - /*[field] DATA*/ - #define FLOW_HOST_TBL_RD_OP_DATA4_DATA - #define FLOW_HOST_TBL_RD_OP_DATA4_DATA_OFFSET 0 - #define FLOW_HOST_TBL_RD_OP_DATA4_DATA_LEN 32 - #define FLOW_HOST_TBL_RD_OP_DATA4_DATA_DEFAULT 0x0 - -struct flow_host_tbl_rd_op_data4 { - a_uint32_t data:32; -}; - -union flow_host_tbl_rd_op_data4_u { - a_uint32_t val; - struct flow_host_tbl_rd_op_data4 bf; -}; - -/*[register] FLOW_HOST_TBL_RD_OP_DATA5*/ -#define FLOW_HOST_TBL_RD_OP_DATA5 -#define FLOW_HOST_TBL_RD_OP_DATA5_ADDRESS 0x454 -#define FLOW_HOST_TBL_RD_OP_DATA5_NUM 1 -#define FLOW_HOST_TBL_RD_OP_DATA5_INC 0x4 -#define FLOW_HOST_TBL_RD_OP_DATA5_TYPE REG_TYPE_RW -#define FLOW_HOST_TBL_RD_OP_DATA5_DEFAULT 0x0 - /*[field] DATA*/ - #define FLOW_HOST_TBL_RD_OP_DATA5_DATA - #define FLOW_HOST_TBL_RD_OP_DATA5_DATA_OFFSET 0 - #define FLOW_HOST_TBL_RD_OP_DATA5_DATA_LEN 32 - #define FLOW_HOST_TBL_RD_OP_DATA5_DATA_DEFAULT 0x0 - -struct flow_host_tbl_rd_op_data5 { - a_uint32_t data:32; -}; - -union flow_host_tbl_rd_op_data5_u { - a_uint32_t val; - struct flow_host_tbl_rd_op_data5 bf; -}; - -/*[register] FLOW_HOST_TBL_RD_OP_DATA6*/ -#define FLOW_HOST_TBL_RD_OP_DATA6 -#define FLOW_HOST_TBL_RD_OP_DATA6_ADDRESS 0x458 -#define FLOW_HOST_TBL_RD_OP_DATA6_NUM 1 -#define FLOW_HOST_TBL_RD_OP_DATA6_INC 0x4 -#define FLOW_HOST_TBL_RD_OP_DATA6_TYPE REG_TYPE_RW -#define FLOW_HOST_TBL_RD_OP_DATA6_DEFAULT 0x0 - /*[field] DATA*/ - #define FLOW_HOST_TBL_RD_OP_DATA6_DATA - #define FLOW_HOST_TBL_RD_OP_DATA6_DATA_OFFSET 0 - #define FLOW_HOST_TBL_RD_OP_DATA6_DATA_LEN 32 - #define FLOW_HOST_TBL_RD_OP_DATA6_DATA_DEFAULT 0x0 - -struct flow_host_tbl_rd_op_data6 { - a_uint32_t data:32; -}; - -union flow_host_tbl_rd_op_data6_u { - a_uint32_t val; - struct flow_host_tbl_rd_op_data6 bf; -}; - -/*[register] FLOW_HOST_TBL_RD_OP_DATA7*/ -#define FLOW_HOST_TBL_RD_OP_DATA7 -#define FLOW_HOST_TBL_RD_OP_DATA7_ADDRESS 0x45c -#define FLOW_HOST_TBL_RD_OP_DATA7_NUM 1 -#define FLOW_HOST_TBL_RD_OP_DATA7_INC 0x4 -#define FLOW_HOST_TBL_RD_OP_DATA7_TYPE REG_TYPE_RW -#define FLOW_HOST_TBL_RD_OP_DATA7_DEFAULT 0x0 - /*[field] DATA*/ - #define FLOW_HOST_TBL_RD_OP_DATA7_DATA - #define FLOW_HOST_TBL_RD_OP_DATA7_DATA_OFFSET 0 - #define FLOW_HOST_TBL_RD_OP_DATA7_DATA_LEN 32 - #define FLOW_HOST_TBL_RD_OP_DATA7_DATA_DEFAULT 0x0 - -struct flow_host_tbl_rd_op_data7 { - a_uint32_t data:32; -}; - -union flow_host_tbl_rd_op_data7_u { - a_uint32_t val; - struct flow_host_tbl_rd_op_data7 bf; -}; - -/*[register] FLOW_HOST_TBL_RD_OP_DATA8*/ -#define FLOW_HOST_TBL_RD_OP_DATA8 -#define FLOW_HOST_TBL_RD_OP_DATA8_ADDRESS 0x460 -#define FLOW_HOST_TBL_RD_OP_DATA8_NUM 1 -#define FLOW_HOST_TBL_RD_OP_DATA8_INC 0x4 -#define FLOW_HOST_TBL_RD_OP_DATA8_TYPE REG_TYPE_RW -#define FLOW_HOST_TBL_RD_OP_DATA8_DEFAULT 0x0 - /*[field] DATA*/ - #define FLOW_HOST_TBL_RD_OP_DATA8_DATA - #define FLOW_HOST_TBL_RD_OP_DATA8_DATA_OFFSET 0 - #define FLOW_HOST_TBL_RD_OP_DATA8_DATA_LEN 32 - #define FLOW_HOST_TBL_RD_OP_DATA8_DATA_DEFAULT 0x0 - -struct flow_host_tbl_rd_op_data8 { - a_uint32_t data:32; -}; - -union flow_host_tbl_rd_op_data8_u { - a_uint32_t val; - struct flow_host_tbl_rd_op_data8 bf; -}; - -/*[register] FLOW_HOST_TBL_RD_OP_DATA9*/ -#define FLOW_HOST_TBL_RD_OP_DATA9 -#define FLOW_HOST_TBL_RD_OP_DATA9_ADDRESS 0x464 -#define FLOW_HOST_TBL_RD_OP_DATA9_NUM 1 -#define FLOW_HOST_TBL_RD_OP_DATA9_INC 0x4 -#define FLOW_HOST_TBL_RD_OP_DATA9_TYPE REG_TYPE_RW -#define FLOW_HOST_TBL_RD_OP_DATA9_DEFAULT 0x0 - /*[field] DATA*/ - #define FLOW_HOST_TBL_RD_OP_DATA9_DATA - #define FLOW_HOST_TBL_RD_OP_DATA9_DATA_OFFSET 0 - #define FLOW_HOST_TBL_RD_OP_DATA9_DATA_LEN 32 - #define FLOW_HOST_TBL_RD_OP_DATA9_DATA_DEFAULT 0x0 - -struct flow_host_tbl_rd_op_data9 { - a_uint32_t data:32; -}; - -union flow_host_tbl_rd_op_data9_u { - a_uint32_t val; - struct flow_host_tbl_rd_op_data9 bf; -}; - -/*[register] IN_FLOW_TBL_RD_OP_RSLT*/ -#define IN_FLOW_TBL_RD_OP_RSLT -#define IN_FLOW_TBL_RD_OP_RSLT_ADDRESS 0x468 -#define IN_FLOW_TBL_RD_OP_RSLT_NUM 1 -#define IN_FLOW_TBL_RD_OP_RSLT_INC 0x4 -#define IN_FLOW_TBL_RD_OP_RSLT_TYPE REG_TYPE_RO -#define IN_FLOW_TBL_RD_OP_RSLT_DEFAULT 0x0 - /*[field] CMD_ID*/ - #define IN_FLOW_TBL_RD_OP_RSLT_CMD_ID - #define IN_FLOW_TBL_RD_OP_RSLT_CMD_ID_OFFSET 0 - #define IN_FLOW_TBL_RD_OP_RSLT_CMD_ID_LEN 4 - #define IN_FLOW_TBL_RD_OP_RSLT_CMD_ID_DEFAULT 0x0 - /*[field] OP_RSLT*/ - #define IN_FLOW_TBL_RD_OP_RSLT_OP_RSLT - #define IN_FLOW_TBL_RD_OP_RSLT_OP_RSLT_OFFSET 4 - #define IN_FLOW_TBL_RD_OP_RSLT_OP_RSLT_LEN 1 - #define IN_FLOW_TBL_RD_OP_RSLT_OP_RSLT_DEFAULT 0x0 - /*[field] FLOW_ENTRY_INDEX*/ - #define IN_FLOW_TBL_RD_OP_RSLT_FLOW_ENTRY_INDEX - #define IN_FLOW_TBL_RD_OP_RSLT_FLOW_ENTRY_INDEX_OFFSET 5 - #define IN_FLOW_TBL_RD_OP_RSLT_FLOW_ENTRY_INDEX_LEN 12 - #define IN_FLOW_TBL_RD_OP_RSLT_FLOW_ENTRY_INDEX_DEFAULT 0x0 - /*[field] VALID_CNT*/ - #define IN_FLOW_TBL_RD_OP_RSLT_VALID_CNT - #define IN_FLOW_TBL_RD_OP_RSLT_VALID_CNT_OFFSET 17 - #define IN_FLOW_TBL_RD_OP_RSLT_VALID_CNT_LEN 4 - #define IN_FLOW_TBL_RD_OP_RSLT_VALID_CNT_DEFAULT 0x0 - -struct in_flow_tbl_rd_op_rslt { - a_uint32_t cmd_id:4; - a_uint32_t op_rslt:1; - a_uint32_t flow_entry_index:12; - a_uint32_t valid_cnt:4; - a_uint32_t _reserved0:11; -}; - -union in_flow_tbl_rd_op_rslt_u { - a_uint32_t val; - struct in_flow_tbl_rd_op_rslt bf; -}; - -/*[register] FLOW_HOST_TBL_RD_OP_RSLT*/ -#define FLOW_HOST_TBL_RD_OP_RSLT -#define FLOW_HOST_TBL_RD_OP_RSLT_ADDRESS 0x46c -#define FLOW_HOST_TBL_RD_OP_RSLT_NUM 1 -#define FLOW_HOST_TBL_RD_OP_RSLT_INC 0x4 -#define FLOW_HOST_TBL_RD_OP_RSLT_TYPE REG_TYPE_RO -#define FLOW_HOST_TBL_RD_OP_RSLT_DEFAULT 0x0 - /*[field] HOST_ENTRY_INDEX*/ - #define FLOW_HOST_TBL_RD_OP_RSLT_HOST_ENTRY_INDEX - #define FLOW_HOST_TBL_RD_OP_RSLT_HOST_ENTRY_INDEX_OFFSET 0 - #define FLOW_HOST_TBL_RD_OP_RSLT_HOST_ENTRY_INDEX_LEN 13 - #define FLOW_HOST_TBL_RD_OP_RSLT_HOST_ENTRY_INDEX_DEFAULT 0x0 - -struct flow_host_tbl_rd_op_rslt { - a_uint32_t host_entry_index:13; - a_uint32_t _reserved0:19; -}; - -union flow_host_tbl_rd_op_rslt_u { - a_uint32_t val; - struct flow_host_tbl_rd_op_rslt bf; -}; - -/*[register] IN_FLOW_TBL_RD_RSLT_DATA0*/ -#define IN_FLOW_TBL_RD_RSLT_DATA0 -#define IN_FLOW_TBL_RD_RSLT_DATA0_ADDRESS 0x470 -#define IN_FLOW_TBL_RD_RSLT_DATA0_NUM 1 -#define IN_FLOW_TBL_RD_RSLT_DATA0_INC 0x4 -#define IN_FLOW_TBL_RD_RSLT_DATA0_TYPE REG_TYPE_RO -#define IN_FLOW_TBL_RD_RSLT_DATA0_DEFAULT 0x0 - /*[field] DATA*/ - #define IN_FLOW_TBL_RD_RSLT_DATA0_DATA - #define IN_FLOW_TBL_RD_RSLT_DATA0_DATA_OFFSET 0 - #define IN_FLOW_TBL_RD_RSLT_DATA0_DATA_LEN 32 - #define IN_FLOW_TBL_RD_RSLT_DATA0_DATA_DEFAULT 0x0 - -struct in_flow_tbl_rd_rslt_data0 { - a_uint32_t data:32; -}; - -union in_flow_tbl_rd_rslt_data0_u { - a_uint32_t val; - struct in_flow_tbl_rd_rslt_data0 bf; -}; - -/*[register] IN_FLOW_TBL_RD_RSLT_DATA1*/ -#define IN_FLOW_TBL_RD_RSLT_DATA1 -#define IN_FLOW_TBL_RD_RSLT_DATA1_ADDRESS 0x474 -#define IN_FLOW_TBL_RD_RSLT_DATA1_NUM 1 -#define IN_FLOW_TBL_RD_RSLT_DATA1_INC 0x4 -#define IN_FLOW_TBL_RD_RSLT_DATA1_TYPE REG_TYPE_RO -#define IN_FLOW_TBL_RD_RSLT_DATA1_DEFAULT 0x0 - /*[field] DATA*/ - #define IN_FLOW_TBL_RD_RSLT_DATA1_DATA - #define IN_FLOW_TBL_RD_RSLT_DATA1_DATA_OFFSET 0 - #define IN_FLOW_TBL_RD_RSLT_DATA1_DATA_LEN 32 - #define IN_FLOW_TBL_RD_RSLT_DATA1_DATA_DEFAULT 0x0 - -struct in_flow_tbl_rd_rslt_data1 { - a_uint32_t data:32; -}; - -union in_flow_tbl_rd_rslt_data1_u { - a_uint32_t val; - struct in_flow_tbl_rd_rslt_data1 bf; -}; - -/*[register] IN_FLOW_TBL_RD_RSLT_DATA2*/ -#define IN_FLOW_TBL_RD_RSLT_DATA2 -#define IN_FLOW_TBL_RD_RSLT_DATA2_ADDRESS 0x478 -#define IN_FLOW_TBL_RD_RSLT_DATA2_NUM 1 -#define IN_FLOW_TBL_RD_RSLT_DATA2_INC 0x4 -#define IN_FLOW_TBL_RD_RSLT_DATA2_TYPE REG_TYPE_RO -#define IN_FLOW_TBL_RD_RSLT_DATA2_DEFAULT 0x0 - /*[field] DATA*/ - #define IN_FLOW_TBL_RD_RSLT_DATA2_DATA - #define IN_FLOW_TBL_RD_RSLT_DATA2_DATA_OFFSET 0 - #define IN_FLOW_TBL_RD_RSLT_DATA2_DATA_LEN 32 - #define IN_FLOW_TBL_RD_RSLT_DATA2_DATA_DEFAULT 0x0 - -struct in_flow_tbl_rd_rslt_data2 { - a_uint32_t data:32; -}; - -union in_flow_tbl_rd_rslt_data2_u { - a_uint32_t val; - struct in_flow_tbl_rd_rslt_data2 bf; -}; - -/*[register] IN_FLOW_TBL_RD_RSLT_DATA3*/ -#define IN_FLOW_TBL_RD_RSLT_DATA3 -#define IN_FLOW_TBL_RD_RSLT_DATA3_ADDRESS 0x47c -#define IN_FLOW_TBL_RD_RSLT_DATA3_NUM 1 -#define IN_FLOW_TBL_RD_RSLT_DATA3_INC 0x4 -#define IN_FLOW_TBL_RD_RSLT_DATA3_TYPE REG_TYPE_RO -#define IN_FLOW_TBL_RD_RSLT_DATA3_DEFAULT 0x0 - /*[field] DATA*/ - #define IN_FLOW_TBL_RD_RSLT_DATA3_DATA - #define IN_FLOW_TBL_RD_RSLT_DATA3_DATA_OFFSET 0 - #define IN_FLOW_TBL_RD_RSLT_DATA3_DATA_LEN 32 - #define IN_FLOW_TBL_RD_RSLT_DATA3_DATA_DEFAULT 0x0 - -struct in_flow_tbl_rd_rslt_data3 { - a_uint32_t data:32; -}; - -union in_flow_tbl_rd_rslt_data3_u { - a_uint32_t val; - struct in_flow_tbl_rd_rslt_data3 bf; -}; - -/*[register] IN_FLOW_TBL_RD_RSLT_DATA4*/ -#define IN_FLOW_TBL_RD_RSLT_DATA4 -#define IN_FLOW_TBL_RD_RSLT_DATA4_ADDRESS 0x480 -#define IN_FLOW_TBL_RD_RSLT_DATA4_NUM 1 -#define IN_FLOW_TBL_RD_RSLT_DATA4_INC 0x4 -#define IN_FLOW_TBL_RD_RSLT_DATA4_TYPE REG_TYPE_RO -#define IN_FLOW_TBL_RD_RSLT_DATA4_DEFAULT 0x0 - /*[field] DATA*/ - #define IN_FLOW_TBL_RD_RSLT_DATA4_DATA - #define IN_FLOW_TBL_RD_RSLT_DATA4_DATA_OFFSET 0 - #define IN_FLOW_TBL_RD_RSLT_DATA4_DATA_LEN 32 - #define IN_FLOW_TBL_RD_RSLT_DATA4_DATA_DEFAULT 0x0 - -struct in_flow_tbl_rd_rslt_data4 { - a_uint32_t data:32; -}; - -union in_flow_tbl_rd_rslt_data4_u { - a_uint32_t val; - struct in_flow_tbl_rd_rslt_data4 bf; -}; - -/*[register] IN_FLOW_TBL_RD_RSLT_DATA5*/ -#define IN_FLOW_TBL_RD_RSLT_DATA5 -#define IN_FLOW_TBL_RD_RSLT_DATA5_ADDRESS 0x484 -#define IN_FLOW_TBL_RD_RSLT_DATA5_NUM 1 -#define IN_FLOW_TBL_RD_RSLT_DATA5_INC 0x4 -#define IN_FLOW_TBL_RD_RSLT_DATA5_TYPE REG_TYPE_RO -#define IN_FLOW_TBL_RD_RSLT_DATA5_DEFAULT 0x0 - /*[field] DATA*/ - #define IN_FLOW_TBL_RD_RSLT_DATA5_DATA - #define IN_FLOW_TBL_RD_RSLT_DATA5_DATA_OFFSET 0 - #define IN_FLOW_TBL_RD_RSLT_DATA5_DATA_LEN 32 - #define IN_FLOW_TBL_RD_RSLT_DATA5_DATA_DEFAULT 0x0 - -struct in_flow_tbl_rd_rslt_data5 { - a_uint32_t data:32; -}; - -union in_flow_tbl_rd_rslt_data5_u { - a_uint32_t val; - struct in_flow_tbl_rd_rslt_data5 bf; -}; - -/*[register] IN_FLOW_TBL_RD_RSLT_DATA6*/ -#define IN_FLOW_TBL_RD_RSLT_DATA6 -#define IN_FLOW_TBL_RD_RSLT_DATA6_ADDRESS 0x488 -#define IN_FLOW_TBL_RD_RSLT_DATA6_NUM 1 -#define IN_FLOW_TBL_RD_RSLT_DATA6_INC 0x4 -#define IN_FLOW_TBL_RD_RSLT_DATA6_TYPE REG_TYPE_RO -#define IN_FLOW_TBL_RD_RSLT_DATA6_DEFAULT 0x0 - /*[field] DATA*/ - #define IN_FLOW_TBL_RD_RSLT_DATA6_DATA - #define IN_FLOW_TBL_RD_RSLT_DATA6_DATA_OFFSET 0 - #define IN_FLOW_TBL_RD_RSLT_DATA6_DATA_LEN 32 - #define IN_FLOW_TBL_RD_RSLT_DATA6_DATA_DEFAULT 0x0 - -struct in_flow_tbl_rd_rslt_data6 { - a_uint32_t data:32; -}; - -union in_flow_tbl_rd_rslt_data6_u { - a_uint32_t val; - struct in_flow_tbl_rd_rslt_data6 bf; -}; - -/*[register] IN_FLOW_TBL_RD_RSLT_DATA7*/ -#define IN_FLOW_TBL_RD_RSLT_DATA7 -#define IN_FLOW_TBL_RD_RSLT_DATA7_ADDRESS 0x48c -#define IN_FLOW_TBL_RD_RSLT_DATA7_NUM 1 -#define IN_FLOW_TBL_RD_RSLT_DATA7_INC 0x4 -#define IN_FLOW_TBL_RD_RSLT_DATA7_TYPE REG_TYPE_RO -#define IN_FLOW_TBL_RD_RSLT_DATA7_DEFAULT 0x0 - /*[field] DATA*/ - #define IN_FLOW_TBL_RD_RSLT_DATA7_DATA - #define IN_FLOW_TBL_RD_RSLT_DATA7_DATA_OFFSET 0 - #define IN_FLOW_TBL_RD_RSLT_DATA7_DATA_LEN 32 - #define IN_FLOW_TBL_RD_RSLT_DATA7_DATA_DEFAULT 0x0 - -struct in_flow_tbl_rd_rslt_data7 { - a_uint32_t data:32; -}; - -union in_flow_tbl_rd_rslt_data7_u { - a_uint32_t val; - struct in_flow_tbl_rd_rslt_data7 bf; -}; - -/*[register] IN_FLOW_TBL_RD_RSLT_DATA8*/ -#define IN_FLOW_TBL_RD_RSLT_DATA8 -#define IN_FLOW_TBL_RD_RSLT_DATA8_ADDRESS 0x490 -#define IN_FLOW_TBL_RD_RSLT_DATA8_NUM 1 -#define IN_FLOW_TBL_RD_RSLT_DATA8_INC 0x4 -#define IN_FLOW_TBL_RD_RSLT_DATA8_TYPE REG_TYPE_RO -#define IN_FLOW_TBL_RD_RSLT_DATA8_DEFAULT 0x0 - /*[field] DATA*/ - #define IN_FLOW_TBL_RD_RSLT_DATA8_DATA - #define IN_FLOW_TBL_RD_RSLT_DATA8_DATA_OFFSET 0 - #define IN_FLOW_TBL_RD_RSLT_DATA8_DATA_LEN 32 - #define IN_FLOW_TBL_RD_RSLT_DATA8_DATA_DEFAULT 0x0 - -struct in_flow_tbl_rd_rslt_data8 { - a_uint32_t data:32; -}; - -union in_flow_tbl_rd_rslt_data8_u { - a_uint32_t val; - struct in_flow_tbl_rd_rslt_data8 bf; -}; - -/*[register] FLOW_HOST_TBL_RD_RSLT_DATA0*/ -#define FLOW_HOST_TBL_RD_RSLT_DATA0 -#define FLOW_HOST_TBL_RD_RSLT_DATA0_ADDRESS 0x494 -#define FLOW_HOST_TBL_RD_RSLT_DATA0_NUM 1 -#define FLOW_HOST_TBL_RD_RSLT_DATA0_INC 0x4 -#define FLOW_HOST_TBL_RD_RSLT_DATA0_TYPE REG_TYPE_RO -#define FLOW_HOST_TBL_RD_RSLT_DATA0_DEFAULT 0x0 - /*[field] DATA*/ - #define FLOW_HOST_TBL_RD_RSLT_DATA0_DATA - #define FLOW_HOST_TBL_RD_RSLT_DATA0_DATA_OFFSET 0 - #define FLOW_HOST_TBL_RD_RSLT_DATA0_DATA_LEN 32 - #define FLOW_HOST_TBL_RD_RSLT_DATA0_DATA_DEFAULT 0x0 - -struct flow_host_tbl_rd_rslt_data0 { - a_uint32_t data:32; -}; - -union flow_host_tbl_rd_rslt_data0_u { - a_uint32_t val; - struct flow_host_tbl_rd_rslt_data0 bf; -}; - -/*[register] FLOW_HOST_TBL_RD_RSLT_DATA1*/ -#define FLOW_HOST_TBL_RD_RSLT_DATA1 -#define FLOW_HOST_TBL_RD_RSLT_DATA1_ADDRESS 0x498 -#define FLOW_HOST_TBL_RD_RSLT_DATA1_NUM 1 -#define FLOW_HOST_TBL_RD_RSLT_DATA1_INC 0x4 -#define FLOW_HOST_TBL_RD_RSLT_DATA1_TYPE REG_TYPE_RO -#define FLOW_HOST_TBL_RD_RSLT_DATA1_DEFAULT 0x0 - /*[field] DATA*/ - #define FLOW_HOST_TBL_RD_RSLT_DATA1_DATA - #define FLOW_HOST_TBL_RD_RSLT_DATA1_DATA_OFFSET 0 - #define FLOW_HOST_TBL_RD_RSLT_DATA1_DATA_LEN 32 - #define FLOW_HOST_TBL_RD_RSLT_DATA1_DATA_DEFAULT 0x0 - -struct flow_host_tbl_rd_rslt_data1 { - a_uint32_t data:32; -}; - -union flow_host_tbl_rd_rslt_data1_u { - a_uint32_t val; - struct flow_host_tbl_rd_rslt_data1 bf; -}; - -/*[register] FLOW_HOST_TBL_RD_RSLT_DATA2*/ -#define FLOW_HOST_TBL_RD_RSLT_DATA2 -#define FLOW_HOST_TBL_RD_RSLT_DATA2_ADDRESS 0x49c -#define FLOW_HOST_TBL_RD_RSLT_DATA2_NUM 1 -#define FLOW_HOST_TBL_RD_RSLT_DATA2_INC 0x4 -#define FLOW_HOST_TBL_RD_RSLT_DATA2_TYPE REG_TYPE_RO -#define FLOW_HOST_TBL_RD_RSLT_DATA2_DEFAULT 0x0 - /*[field] DATA*/ - #define FLOW_HOST_TBL_RD_RSLT_DATA2_DATA - #define FLOW_HOST_TBL_RD_RSLT_DATA2_DATA_OFFSET 0 - #define FLOW_HOST_TBL_RD_RSLT_DATA2_DATA_LEN 32 - #define FLOW_HOST_TBL_RD_RSLT_DATA2_DATA_DEFAULT 0x0 - -struct flow_host_tbl_rd_rslt_data2 { - a_uint32_t data:32; -}; - -union flow_host_tbl_rd_rslt_data2_u { - a_uint32_t val; - struct flow_host_tbl_rd_rslt_data2 bf; -}; - -/*[register] FLOW_HOST_TBL_RD_RSLT_DATA3*/ -#define FLOW_HOST_TBL_RD_RSLT_DATA3 -#define FLOW_HOST_TBL_RD_RSLT_DATA3_ADDRESS 0x4a0 -#define FLOW_HOST_TBL_RD_RSLT_DATA3_NUM 1 -#define FLOW_HOST_TBL_RD_RSLT_DATA3_INC 0x4 -#define FLOW_HOST_TBL_RD_RSLT_DATA3_TYPE REG_TYPE_RO -#define FLOW_HOST_TBL_RD_RSLT_DATA3_DEFAULT 0x0 - /*[field] DATA*/ - #define FLOW_HOST_TBL_RD_RSLT_DATA3_DATA - #define FLOW_HOST_TBL_RD_RSLT_DATA3_DATA_OFFSET 0 - #define FLOW_HOST_TBL_RD_RSLT_DATA3_DATA_LEN 32 - #define FLOW_HOST_TBL_RD_RSLT_DATA3_DATA_DEFAULT 0x0 - -struct flow_host_tbl_rd_rslt_data3 { - a_uint32_t data:32; -}; - -union flow_host_tbl_rd_rslt_data3_u { - a_uint32_t val; - struct flow_host_tbl_rd_rslt_data3 bf; -}; - -/*[register] FLOW_HOST_TBL_RD_RSLT_DATA4*/ -#define FLOW_HOST_TBL_RD_RSLT_DATA4 -#define FLOW_HOST_TBL_RD_RSLT_DATA4_ADDRESS 0x4a4 -#define FLOW_HOST_TBL_RD_RSLT_DATA4_NUM 1 -#define FLOW_HOST_TBL_RD_RSLT_DATA4_INC 0x4 -#define FLOW_HOST_TBL_RD_RSLT_DATA4_TYPE REG_TYPE_RO -#define FLOW_HOST_TBL_RD_RSLT_DATA4_DEFAULT 0x0 - /*[field] DATA*/ - #define FLOW_HOST_TBL_RD_RSLT_DATA4_DATA - #define FLOW_HOST_TBL_RD_RSLT_DATA4_DATA_OFFSET 0 - #define FLOW_HOST_TBL_RD_RSLT_DATA4_DATA_LEN 32 - #define FLOW_HOST_TBL_RD_RSLT_DATA4_DATA_DEFAULT 0x0 - -struct flow_host_tbl_rd_rslt_data4 { - a_uint32_t data:32; -}; - -union flow_host_tbl_rd_rslt_data4_u { - a_uint32_t val; - struct flow_host_tbl_rd_rslt_data4 bf; -}; - -/*[register] FLOW_HOST_TBL_RD_RSLT_DATA5*/ -#define FLOW_HOST_TBL_RD_RSLT_DATA5 -#define FLOW_HOST_TBL_RD_RSLT_DATA5_ADDRESS 0x4a8 -#define FLOW_HOST_TBL_RD_RSLT_DATA5_NUM 1 -#define FLOW_HOST_TBL_RD_RSLT_DATA5_INC 0x4 -#define FLOW_HOST_TBL_RD_RSLT_DATA5_TYPE REG_TYPE_RO -#define FLOW_HOST_TBL_RD_RSLT_DATA5_DEFAULT 0x0 - /*[field] DATA*/ - #define FLOW_HOST_TBL_RD_RSLT_DATA5_DATA - #define FLOW_HOST_TBL_RD_RSLT_DATA5_DATA_OFFSET 0 - #define FLOW_HOST_TBL_RD_RSLT_DATA5_DATA_LEN 32 - #define FLOW_HOST_TBL_RD_RSLT_DATA5_DATA_DEFAULT 0x0 - -struct flow_host_tbl_rd_rslt_data5 { - a_uint32_t data:32; -}; - -union flow_host_tbl_rd_rslt_data5_u { - a_uint32_t val; - struct flow_host_tbl_rd_rslt_data5 bf; -}; - -/*[register] FLOW_HOST_TBL_RD_RSLT_DATA6*/ -#define FLOW_HOST_TBL_RD_RSLT_DATA6 -#define FLOW_HOST_TBL_RD_RSLT_DATA6_ADDRESS 0x4ac -#define FLOW_HOST_TBL_RD_RSLT_DATA6_NUM 1 -#define FLOW_HOST_TBL_RD_RSLT_DATA6_INC 0x4 -#define FLOW_HOST_TBL_RD_RSLT_DATA6_TYPE REG_TYPE_RO -#define FLOW_HOST_TBL_RD_RSLT_DATA6_DEFAULT 0x0 - /*[field] DATA*/ - #define FLOW_HOST_TBL_RD_RSLT_DATA6_DATA - #define FLOW_HOST_TBL_RD_RSLT_DATA6_DATA_OFFSET 0 - #define FLOW_HOST_TBL_RD_RSLT_DATA6_DATA_LEN 32 - #define FLOW_HOST_TBL_RD_RSLT_DATA6_DATA_DEFAULT 0x0 - -struct flow_host_tbl_rd_rslt_data6 { - a_uint32_t data:32; -}; - -union flow_host_tbl_rd_rslt_data6_u { - a_uint32_t val; - struct flow_host_tbl_rd_rslt_data6 bf; -}; - -/*[register] FLOW_HOST_TBL_RD_RSLT_DATA7*/ -#define FLOW_HOST_TBL_RD_RSLT_DATA7 -#define FLOW_HOST_TBL_RD_RSLT_DATA7_ADDRESS 0x4b0 -#define FLOW_HOST_TBL_RD_RSLT_DATA7_NUM 1 -#define FLOW_HOST_TBL_RD_RSLT_DATA7_INC 0x4 -#define FLOW_HOST_TBL_RD_RSLT_DATA7_TYPE REG_TYPE_RO -#define FLOW_HOST_TBL_RD_RSLT_DATA7_DEFAULT 0x0 - /*[field] DATA*/ - #define FLOW_HOST_TBL_RD_RSLT_DATA7_DATA - #define FLOW_HOST_TBL_RD_RSLT_DATA7_DATA_OFFSET 0 - #define FLOW_HOST_TBL_RD_RSLT_DATA7_DATA_LEN 32 - #define FLOW_HOST_TBL_RD_RSLT_DATA7_DATA_DEFAULT 0x0 - -struct flow_host_tbl_rd_rslt_data7 { - a_uint32_t data:32; -}; - -union flow_host_tbl_rd_rslt_data7_u { - a_uint32_t val; - struct flow_host_tbl_rd_rslt_data7 bf; -}; - -/*[register] FLOW_HOST_TBL_RD_RSLT_DATA8*/ -#define FLOW_HOST_TBL_RD_RSLT_DATA8 -#define FLOW_HOST_TBL_RD_RSLT_DATA8_ADDRESS 0x4b4 -#define FLOW_HOST_TBL_RD_RSLT_DATA8_NUM 1 -#define FLOW_HOST_TBL_RD_RSLT_DATA8_INC 0x4 -#define FLOW_HOST_TBL_RD_RSLT_DATA8_TYPE REG_TYPE_RO -#define FLOW_HOST_TBL_RD_RSLT_DATA8_DEFAULT 0x0 - /*[field] DATA*/ - #define FLOW_HOST_TBL_RD_RSLT_DATA8_DATA - #define FLOW_HOST_TBL_RD_RSLT_DATA8_DATA_OFFSET 0 - #define FLOW_HOST_TBL_RD_RSLT_DATA8_DATA_LEN 32 - #define FLOW_HOST_TBL_RD_RSLT_DATA8_DATA_DEFAULT 0x0 - -struct flow_host_tbl_rd_rslt_data8 { - a_uint32_t data:32; -}; - -union flow_host_tbl_rd_rslt_data8_u { - a_uint32_t val; - struct flow_host_tbl_rd_rslt_data8 bf; -}; - -/*[register] FLOW_HOST_TBL_RD_RSLT_DATA9*/ -#define FLOW_HOST_TBL_RD_RSLT_DATA9 -#define FLOW_HOST_TBL_RD_RSLT_DATA9_ADDRESS 0x4b8 -#define FLOW_HOST_TBL_RD_RSLT_DATA9_NUM 1 -#define FLOW_HOST_TBL_RD_RSLT_DATA9_INC 0x4 -#define FLOW_HOST_TBL_RD_RSLT_DATA9_TYPE REG_TYPE_RO -#define FLOW_HOST_TBL_RD_RSLT_DATA9_DEFAULT 0x0 - /*[field] DATA*/ - #define FLOW_HOST_TBL_RD_RSLT_DATA9_DATA - #define FLOW_HOST_TBL_RD_RSLT_DATA9_DATA_OFFSET 0 - #define FLOW_HOST_TBL_RD_RSLT_DATA9_DATA_LEN 32 - #define FLOW_HOST_TBL_RD_RSLT_DATA9_DATA_DEFAULT 0x0 - -struct flow_host_tbl_rd_rslt_data9 { - a_uint32_t data:32; -}; - -union flow_host_tbl_rd_rslt_data9_u { - a_uint32_t val; - struct flow_host_tbl_rd_rslt_data9 bf; -}; - -/*[table] IN_FLOW_3TUPLE_TBL*/ -#define IN_FLOW_3TUPLE_TBL -#define IN_FLOW_3TUPLE_TBL_ADDRESS 0x40000 -#define IN_FLOW_3TUPLE_TBL_NUM 4096 -#define IN_FLOW_3TUPLE_TBL_INC 0x20 -#define IN_FLOW_3TUPLE_TBL_TYPE REG_TYPE_RW -#define IN_FLOW_3TUPLE_TBL_DEFAULT 0x0 - /*[field] VALID*/ - #define IN_FLOW_3TUPLE_TBL_VALID - #define IN_FLOW_3TUPLE_TBL_VALID_OFFSET 0 - #define IN_FLOW_3TUPLE_TBL_VALID_LEN 1 - #define IN_FLOW_3TUPLE_TBL_VALID_DEFAULT 0x0 - /*[field] ENTRY_TYPE*/ - #define IN_FLOW_3TUPLE_TBL_ENTRY_TYPE - #define IN_FLOW_3TUPLE_TBL_ENTRY_TYPE_OFFSET 1 - #define IN_FLOW_3TUPLE_TBL_ENTRY_TYPE_LEN 1 - #define IN_FLOW_3TUPLE_TBL_ENTRY_TYPE_DEFAULT 0x0 - /*[field] HOST_ADDR_INDEX_TYPE*/ - #define IN_FLOW_3TUPLE_TBL_HOST_ADDR_INDEX_TYPE - #define IN_FLOW_3TUPLE_TBL_HOST_ADDR_INDEX_TYPE_OFFSET 2 - #define IN_FLOW_3TUPLE_TBL_HOST_ADDR_INDEX_TYPE_LEN 1 - #define IN_FLOW_3TUPLE_TBL_HOST_ADDR_INDEX_TYPE_DEFAULT 0x0 - /*[field] HOST_ADDR_INDEX*/ - #define IN_FLOW_3TUPLE_TBL_HOST_ADDR_INDEX - #define IN_FLOW_3TUPLE_TBL_HOST_ADDR_INDEX_OFFSET 3 - #define IN_FLOW_3TUPLE_TBL_HOST_ADDR_INDEX_LEN 13 - #define IN_FLOW_3TUPLE_TBL_HOST_ADDR_INDEX_DEFAULT 0x0 - /*[field] PROTOCOL_TYPE*/ - #define IN_FLOW_3TUPLE_TBL_PROTOCOL_TYPE - #define IN_FLOW_3TUPLE_TBL_PROTOCOL_TYPE_OFFSET 16 - #define IN_FLOW_3TUPLE_TBL_PROTOCOL_TYPE_LEN 2 - #define IN_FLOW_3TUPLE_TBL_PROTOCOL_TYPE_DEFAULT 0x0 - /*[field] AGE*/ - #define IN_FLOW_3TUPLE_TBL_AGE - #define IN_FLOW_3TUPLE_TBL_AGE_OFFSET 18 - #define IN_FLOW_3TUPLE_TBL_AGE_LEN 2 - #define IN_FLOW_3TUPLE_TBL_AGE_DEFAULT 0x0 - /*[field] SRC_L3_IF_VALID*/ - #define IN_FLOW_3TUPLE_TBL_SRC_L3_IF_VALID - #define IN_FLOW_3TUPLE_TBL_SRC_L3_IF_VALID_OFFSET 20 - #define IN_FLOW_3TUPLE_TBL_SRC_L3_IF_VALID_LEN 1 - #define IN_FLOW_3TUPLE_TBL_SRC_L3_IF_VALID_DEFAULT 0x0 - /*[field] SRC_L3_IF*/ - #define IN_FLOW_3TUPLE_TBL_SRC_L3_IF - #define IN_FLOW_3TUPLE_TBL_SRC_L3_IF_OFFSET 21 - #define IN_FLOW_3TUPLE_TBL_SRC_L3_IF_LEN 8 - #define IN_FLOW_3TUPLE_TBL_SRC_L3_IF_DEFAULT 0x0 - /*[field] FWD_TYPE*/ - #define IN_FLOW_3TUPLE_TBL_FWD_TYPE - #define IN_FLOW_3TUPLE_TBL_FWD_TYPE_OFFSET 29 - #define IN_FLOW_3TUPLE_TBL_FWD_TYPE_LEN 3 - #define IN_FLOW_3TUPLE_TBL_FWD_TYPE_DEFAULT 0x0 - /*[field] PORT_VP2 reuse FWD_TYPE[1]*/ - #define IN_FLOW_3TUPLE_TBL_PORT_VP2 - #define IN_FLOW_3TUPLE_TBL_PORT_VP2_OFFSET 32 - #define IN_FLOW_3TUPLE_TBL_PORT_VP2_LEN 8 - #define IN_FLOW_3TUPLE_TBL_PORT_VP2_DEFAULT 0x0 - /*[field] NEXT_HOP3 reuse FWD_TYPE[2]*/ - #define IN_FLOW_3TUPLE_TBL_NEXT_HOP3 - #define IN_FLOW_3TUPLE_TBL_NEXT_HOP3_OFFSET 32 - #define IN_FLOW_3TUPLE_TBL_NEXT_HOP3_LEN 12 - #define IN_FLOW_3TUPLE_TBL_NEXT_HOP3_DEFAULT 0x0 - /*[field] NEXT_HOP1 reuse FWD_TYPE[0]*/ - #define IN_FLOW_3TUPLE_TBL_NEXT_HOP1 - #define IN_FLOW_3TUPLE_TBL_NEXT_HOP1_OFFSET 32 - #define IN_FLOW_3TUPLE_TBL_NEXT_HOP1_LEN 12 - #define IN_FLOW_3TUPLE_TBL_NEXT_HOP1_DEFAULT 0x0 - /*[field] NEXT_HOP2 reuse FWD_TYPE[3]*/ - #define IN_FLOW_3TUPLE_TBL_NEXT_HOP2 - #define IN_FLOW_3TUPLE_TBL_NEXT_HOP2_OFFSET 32 - #define IN_FLOW_3TUPLE_TBL_NEXT_HOP2_LEN 12 - #define IN_FLOW_3TUPLE_TBL_NEXT_HOP2_DEFAULT 0x0 - /*[field] PORT_VP_VALID1 reuse FWD_TYPE[2]*/ - #define IN_FLOW_3TUPLE_TBL_PORT_VP_VALID1 - #define IN_FLOW_3TUPLE_TBL_PORT_VP_VALID1_OFFSET 44 - #define IN_FLOW_3TUPLE_TBL_PORT_VP_VALID1_LEN 1 - #define IN_FLOW_3TUPLE_TBL_PORT_VP_VALID1_DEFAULT 0x0 - /*[field] PORT_VP1 reuse FWD_TYPE[2]*/ - #define IN_FLOW_3TUPLE_TBL_PORT_VP1 - #define IN_FLOW_3TUPLE_TBL_PORT_VP1_OFFSET 45 - #define IN_FLOW_3TUPLE_TBL_PORT_VP1_LEN 8 - #define IN_FLOW_3TUPLE_TBL_PORT_VP1_DEFAULT 0x0 - /*[field] DE_ACCE*/ - #define IN_FLOW_3TUPLE_TBL_DE_ACCE - #define IN_FLOW_3TUPLE_TBL_DE_ACCE_OFFSET 60 - #define IN_FLOW_3TUPLE_TBL_DE_ACCE_LEN 1 - #define IN_FLOW_3TUPLE_TBL_DE_ACCE_DEFAULT 0x0 - /*[field] COPY_TO_CPU_EN*/ - #define IN_FLOW_3TUPLE_TBL_COPY_TO_CPU_EN - #define IN_FLOW_3TUPLE_TBL_COPY_TO_CPU_EN_OFFSET 61 - #define IN_FLOW_3TUPLE_TBL_COPY_TO_CPU_EN_LEN 1 - #define IN_FLOW_3TUPLE_TBL_COPY_TO_CPU_EN_DEFAULT 0x0 - /*[field] SYN_TOGGLE*/ - #define IN_FLOW_3TUPLE_TBL_SYN_TOGGLE - #define IN_FLOW_3TUPLE_TBL_SYN_TOGGLE_OFFSET 62 - #define IN_FLOW_3TUPLE_TBL_SYN_TOGGLE_LEN 1 - #define IN_FLOW_3TUPLE_TBL_SYN_TOGGLE_DEFAULT 0x0 - /*[field] PRI_PROFILE*/ - #define IN_FLOW_3TUPLE_TBL_PRI_PROFILE - #define IN_FLOW_3TUPLE_TBL_PRI_PROFILE_OFFSET 63 - #define IN_FLOW_3TUPLE_TBL_PRI_PROFILE_LEN 5 - #define IN_FLOW_3TUPLE_TBL_PRI_PROFILE_DEFAULT 0x0 - /*[field] SERVICE_CODE*/ - #define IN_FLOW_3TUPLE_TBL_SERVICE_CODE - #define IN_FLOW_3TUPLE_TBL_SERVICE_CODE_OFFSET 68 - #define IN_FLOW_3TUPLE_TBL_SERVICE_CODE_LEN 8 - #define IN_FLOW_3TUPLE_TBL_SERVICE_CODE_DEFAULT 0x0 - /*[field] IP_ADDR*/ - #define IN_FLOW_3TUPLE_TBL_IP_ADDR - #define IN_FLOW_3TUPLE_TBL_IP_ADDR_OFFSET 76 - #define IN_FLOW_3TUPLE_TBL_IP_ADDR_LEN 32 - #define IN_FLOW_3TUPLE_TBL_IP_ADDR_DEFAULT 0x0 - /*[field] IP_PROTOCOL*/ - #define IN_FLOW_3TUPLE_TBL_IP_PROTOCOL - #define IN_FLOW_3TUPLE_TBL_IP_PROTOCOL_OFFSET 108 - #define IN_FLOW_3TUPLE_TBL_IP_PROTOCOL_LEN 8 - #define IN_FLOW_3TUPLE_TBL_IP_PROTOCOL_DEFAULT 0x0 - -struct in_flow_tbl_1 { - a_uint32_t valid:1; - a_uint32_t entry_type:1; - a_uint32_t host_addr_index_type:1; - a_uint32_t host_addr_index:13; - a_uint32_t protocol_type:2; - a_uint32_t age:2; - a_uint32_t src_l3_if_valid:1; - a_uint32_t src_l3_if:8; - a_uint32_t fwd_type:3; - a_uint32_t port_vp2:8; - a_uint32_t _reserved0:20; - a_uint32_t de_acce:1; - a_uint32_t copy_to_cpu_en:1; - a_uint32_t syn_toggle:1; - a_uint32_t pri_profile_0:1; - a_uint32_t pri_profile_1:4; - a_uint32_t service_code:8; - a_uint32_t ip_addr_0:20; - a_uint32_t ip_addr_1:12; - a_uint32_t l4_sport:16; - a_uint32_t l4_dport_0:4; - a_uint32_t l4_dport_1:12; - a_uint32_t _reserved1:20; -}; - -struct in_flow_tbl_3 { - a_uint32_t valid:1; - a_uint32_t entry_type:1; - a_uint32_t host_addr_index_type:1; - a_uint32_t host_addr_index:13; - a_uint32_t protocol_type:2; - a_uint32_t age:2; - a_uint32_t src_l3_if_valid:1; - a_uint32_t src_l3_if:8; - a_uint32_t fwd_type:3; - a_uint32_t next_hop2:12; - a_uint32_t l4_port2:16; - a_uint32_t de_acce:1; - a_uint32_t copy_to_cpu_en:1; - a_uint32_t syn_toggle:1; - a_uint32_t pri_profile_0:1; - a_uint32_t pri_profile_1:4; - a_uint32_t service_code:8; - a_uint32_t ip_addr_0:20; - a_uint32_t ip_addr_1:12; - a_uint32_t l4_sport:16; - a_uint32_t l4_dport_0:4; - a_uint32_t l4_dport_1:12; - a_uint32_t _reserved0:20; -}; - -struct in_flow_tbl_0 { - a_uint32_t valid:1; - a_uint32_t entry_type:1; - a_uint32_t host_addr_index_type:1; - a_uint32_t host_addr_index:13; - a_uint32_t protocol_type:2; - a_uint32_t age:2; - a_uint32_t src_l3_if_valid:1; - a_uint32_t src_l3_if:8; - a_uint32_t fwd_type:3; - a_uint32_t next_hop1:12; - a_uint32_t l4_port1:16; - a_uint32_t de_acce:1; - a_uint32_t copy_to_cpu_en:1; - a_uint32_t syn_toggle:1; - a_uint32_t pri_profile_0:1; - a_uint32_t pri_profile_1:4; - a_uint32_t service_code:8; - a_uint32_t ip_addr_0:20; - a_uint32_t ip_addr_1:12; - a_uint32_t l4_sport:16; - a_uint32_t l4_dport_0:4; - a_uint32_t l4_dport_1:12; - a_uint32_t _reserved0:20; -}; - -struct in_flow_tbl_2 { - a_uint32_t valid:1; - a_uint32_t entry_type:1; - a_uint32_t host_addr_index_type:1; - a_uint32_t host_addr_index:13; - a_uint32_t protocol_type:2; - a_uint32_t age:2; - a_uint32_t src_l3_if_valid:1; - a_uint32_t src_l3_if:8; - a_uint32_t fwd_type:3; - a_uint32_t next_hop3:12; - a_uint32_t port_vp_valid1:1; - a_uint32_t port_vp1:8; - a_uint32_t _reserved0:7; - a_uint32_t de_acce:1; - a_uint32_t copy_to_cpu_en:1; - a_uint32_t syn_toggle:1; - a_uint32_t pri_profile_0:1; - a_uint32_t pri_profile_1:4; - a_uint32_t service_code:8; - a_uint32_t ip_addr_0:20; - a_uint32_t ip_addr_1:12; - a_uint32_t l4_sport:16; - a_uint32_t l4_dport_0:4; - a_uint32_t l4_dport_1:12; - a_uint32_t _reserved1:20; -}; - -union in_flow_tbl_u { - a_uint32_t val[5]; - struct in_flow_tbl_0 bf0; - struct in_flow_tbl_1 bf1; - struct in_flow_tbl_2 bf2; - struct in_flow_tbl_3 bf3; -}; - -/*[table] IN_FLOW_IPV6_3TUPLE_TBL*/ -#define IN_FLOW_IPV6_3TUPLE_TBL -#define IN_FLOW_IPV6_3TUPLE_TBL_ADDRESS 0x40000 -#define IN_FLOW_IPV6_3TUPLE_TBL_NUM 2048 -#define IN_FLOW_IPV6_3TUPLE_TBL_INC 0x40 -#define IN_FLOW_IPV6_3TUPLE_TBL_TYPE REG_TYPE_RW -#define IN_FLOW_IPV6_3TUPLE_TBL_DEFAULT 0x0 - /*[field] VALID*/ - #define IN_FLOW_IPV6_3TUPLE_TBL_VALID - #define IN_FLOW_IPV6_3TUPLE_TBL_VALID_OFFSET 0 - #define IN_FLOW_IPV6_3TUPLE_TBL_VALID_LEN 1 - #define IN_FLOW_IPV6_3TUPLE_TBL_VALID_DEFAULT 0x0 - /*[field] ENTRY_TYPE*/ - #define IN_FLOW_IPV6_3TUPLE_TBL_ENTRY_TYPE - #define IN_FLOW_IPV6_3TUPLE_TBL_ENTRY_TYPE_OFFSET 1 - #define IN_FLOW_IPV6_3TUPLE_TBL_ENTRY_TYPE_LEN 1 - #define IN_FLOW_IPV6_3TUPLE_TBL_ENTRY_TYPE_DEFAULT 0x0 - /*[field] HOST_ADDR_INDEX_TYPE*/ - #define IN_FLOW_IPV6_3TUPLE_TBL_HOST_ADDR_INDEX_TYPE - #define IN_FLOW_IPV6_3TUPLE_TBL_HOST_ADDR_INDEX_TYPE_OFFSET 2 - #define IN_FLOW_IPV6_3TUPLE_TBL_HOST_ADDR_INDEX_TYPE_LEN 1 - #define IN_FLOW_IPV6_3TUPLE_TBL_HOST_ADDR_INDEX_TYPE_DEFAULT 0x0 - /*[field] HOST_ADDR_INDEX*/ - #define IN_FLOW_IPV6_3TUPLE_TBL_HOST_ADDR_INDEX - #define IN_FLOW_IPV6_3TUPLE_TBL_HOST_ADDR_INDEX_OFFSET 3 - #define IN_FLOW_IPV6_3TUPLE_TBL_HOST_ADDR_INDEX_LEN 13 - #define IN_FLOW_IPV6_3TUPLE_TBL_HOST_ADDR_INDEX_DEFAULT 0x0 - /*[field] PROTOCOL_TYPE*/ - #define IN_FLOW_IPV6_3TUPLE_TBL_PROTOCOL_TYPE - #define IN_FLOW_IPV6_3TUPLE_TBL_PROTOCOL_TYPE_OFFSET 16 - #define IN_FLOW_IPV6_3TUPLE_TBL_PROTOCOL_TYPE_LEN 2 - #define IN_FLOW_IPV6_3TUPLE_TBL_PROTOCOL_TYPE_DEFAULT 0x0 - /*[field] AGE*/ - #define IN_FLOW_IPV6_3TUPLE_TBL_AGE - #define IN_FLOW_IPV6_3TUPLE_TBL_AGE_OFFSET 18 - #define IN_FLOW_IPV6_3TUPLE_TBL_AGE_LEN 2 - #define IN_FLOW_IPV6_3TUPLE_TBL_AGE_DEFAULT 0x0 - /*[field] SRC_L3_IF_VALID*/ - #define IN_FLOW_IPV6_3TUPLE_TBL_SRC_L3_IF_VALID - #define IN_FLOW_IPV6_3TUPLE_TBL_SRC_L3_IF_VALID_OFFSET 20 - #define IN_FLOW_IPV6_3TUPLE_TBL_SRC_L3_IF_VALID_LEN 1 - #define IN_FLOW_IPV6_3TUPLE_TBL_SRC_L3_IF_VALID_DEFAULT 0x0 - /*[field] SRC_L3_IF*/ - #define IN_FLOW_IPV6_3TUPLE_TBL_SRC_L3_IF - #define IN_FLOW_IPV6_3TUPLE_TBL_SRC_L3_IF_OFFSET 21 - #define IN_FLOW_IPV6_3TUPLE_TBL_SRC_L3_IF_LEN 8 - #define IN_FLOW_IPV6_3TUPLE_TBL_SRC_L3_IF_DEFAULT 0x0 - /*[field] FWD_TYPE*/ - #define IN_FLOW_IPV6_3TUPLE_TBL_FWD_TYPE - #define IN_FLOW_IPV6_3TUPLE_TBL_FWD_TYPE_OFFSET 29 - #define IN_FLOW_IPV6_3TUPLE_TBL_FWD_TYPE_LEN 3 - #define IN_FLOW_IPV6_3TUPLE_TBL_FWD_TYPE_DEFAULT 0x0 - /*[field] NEXT_HOP3 reuse FWD_TYPE[2]*/ - #define IN_FLOW_IPV6_3TUPLE_TBL_NEXT_HOP3 - #define IN_FLOW_IPV6_3TUPLE_TBL_NEXT_HOP3_OFFSET 32 - #define IN_FLOW_IPV6_3TUPLE_TBL_NEXT_HOP3_LEN 12 - #define IN_FLOW_IPV6_3TUPLE_TBL_NEXT_HOP3_DEFAULT 0x0 - /*[field] NEXT_HOP1 reuse FWD_TYPE[1]*/ - #define IN_FLOW_IPV6_3TUPLE_TBL_NEXT_HOP1 - #define IN_FLOW_IPV6_3TUPLE_TBL_NEXT_HOP1_OFFSET 32 - #define IN_FLOW_IPV6_3TUPLE_TBL_NEXT_HOP1_LEN 12 - #define IN_FLOW_IPV6_3TUPLE_TBL_NEXT_HOP1_DEFAULT 0x0 - /*[field] NEXT_HOP2 reuse FWD_TYPE[3]*/ - #define IN_FLOW_IPV6_3TUPLE_TBL_NEXT_HOP2 - #define IN_FLOW_IPV6_3TUPLE_TBL_NEXT_HOP2_OFFSET 32 - #define IN_FLOW_IPV6_3TUPLE_TBL_NEXT_HOP2_LEN 12 - #define IN_FLOW_IPV6_3TUPLE_TBL_NEXT_HOP2_DEFAULT 0x0 - /*[field] PORT_VP2 reuse FWD_TYPE[0]*/ - #define IN_FLOW_IPV6_3TUPLE_TBL_PORT_VP2 - #define IN_FLOW_IPV6_3TUPLE_TBL_PORT_VP2_OFFSET 32 - #define IN_FLOW_IPV6_3TUPLE_TBL_PORT_VP2_LEN 8 - #define IN_FLOW_IPV6_3TUPLE_TBL_PORT_VP2_DEFAULT 0x0 - /*[field] PORT_VP_VALID1 reuse FWD_TYPE[2]*/ - #define IN_FLOW_IPV6_3TUPLE_TBL_PORT_VP_VALID1 - #define IN_FLOW_IPV6_3TUPLE_TBL_PORT_VP_VALID1_OFFSET 44 - #define IN_FLOW_IPV6_3TUPLE_TBL_PORT_VP_VALID1_LEN 1 - #define IN_FLOW_IPV6_3TUPLE_TBL_PORT_VP_VALID1_DEFAULT 0x0 - /*[field] PORT_VP1 reuse FWD_TYPE[2]*/ - #define IN_FLOW_IPV6_3TUPLE_TBL_PORT_VP1 - #define IN_FLOW_IPV6_3TUPLE_TBL_PORT_VP1_OFFSET 45 - #define IN_FLOW_IPV6_3TUPLE_TBL_PORT_VP1_LEN 8 - #define IN_FLOW_IPV6_3TUPLE_TBL_PORT_VP1_DEFAULT 0x0 - /*[field] DE_ACCE*/ - #define IN_FLOW_IPV6_3TUPLE_TBL_DE_ACCE - #define IN_FLOW_IPV6_3TUPLE_TBL_DE_ACCE_OFFSET 60 - #define IN_FLOW_IPV6_3TUPLE_TBL_DE_ACCE_LEN 1 - #define IN_FLOW_IPV6_3TUPLE_TBL_DE_ACCE_DEFAULT 0x0 - /*[field] COPY_TO_CPU_EN*/ - #define IN_FLOW_IPV6_3TUPLE_TBL_COPY_TO_CPU_EN - #define IN_FLOW_IPV6_3TUPLE_TBL_COPY_TO_CPU_EN_OFFSET 61 - #define IN_FLOW_IPV6_3TUPLE_TBL_COPY_TO_CPU_EN_LEN 1 - #define IN_FLOW_IPV6_3TUPLE_TBL_COPY_TO_CPU_EN_DEFAULT 0x0 - /*[field] SYN_TOGGLE*/ - #define IN_FLOW_IPV6_3TUPLE_TBL_SYN_TOGGLE - #define IN_FLOW_IPV6_3TUPLE_TBL_SYN_TOGGLE_OFFSET 62 - #define IN_FLOW_IPV6_3TUPLE_TBL_SYN_TOGGLE_LEN 1 - #define IN_FLOW_IPV6_3TUPLE_TBL_SYN_TOGGLE_DEFAULT 0x0 - /*[field] PRI_PROFILE*/ - #define IN_FLOW_IPV6_3TUPLE_TBL_PRI_PROFILE - #define IN_FLOW_IPV6_3TUPLE_TBL_PRI_PROFILE_OFFSET 63 - #define IN_FLOW_IPV6_3TUPLE_TBL_PRI_PROFILE_LEN 5 - #define IN_FLOW_IPV6_3TUPLE_TBL_PRI_PROFILE_DEFAULT 0x0 - /*[field] SERVICE_CODE*/ - #define IN_FLOW_IPV6_3TUPLE_TBL_SERVICE_CODE - #define IN_FLOW_IPV6_3TUPLE_TBL_SERVICE_CODE_OFFSET 68 - #define IN_FLOW_IPV6_3TUPLE_TBL_SERVICE_CODE_LEN 8 - #define IN_FLOW_IPV6_3TUPLE_TBL_SERVICE_CODE_DEFAULT 0x0 - /*[field] IP_PROTOCOL*/ - #define IN_FLOW_IPV6_3TUPLE_TBL_IP_PROTOCOL - #define IN_FLOW_IPV6_3TUPLE_TBL_IP_PROTOCOL_OFFSET 108 - #define IN_FLOW_IPV6_3TUPLE_TBL_IP_PROTOCOL_LEN 8 - #define IN_FLOW_IPV6_3TUPLE_TBL_IP_PROTOCOL_DEFAULT 0x0 - /*[field] IP_ADDR*/ - #define IN_FLOW_IPV6_3TUPLE_TBL_IP_ADDR - #define IN_FLOW_IPV6_3TUPLE_TBL_IP_ADDR_OFFSET 140 - #define IN_FLOW_IPV6_3TUPLE_TBL_IP_ADDR_LEN 128 - #define IN_FLOW_IPV6_3TUPLE_TBL_IP_ADDR_DEFAULT 0x0 - -struct in_flow_3tuple_tbl_3 { - a_uint32_t valid:1; - a_uint32_t entry_type:1; - a_uint32_t host_addr_index_type:1; - a_uint32_t host_addr_index:13; - a_uint32_t protocol_type:2; - a_uint32_t age:2; - a_uint32_t src_l3_if_valid:1; - a_uint32_t src_l3_if:8; - a_uint32_t fwd_type:3; - a_uint32_t next_hop2:12; - a_uint32_t _reserved0:16; - a_uint32_t de_acce:1; - a_uint32_t copy_to_cpu_en:1; - a_uint32_t syn_toggle:1; - a_uint32_t pri_profile_0:1; - a_uint32_t pri_profile_1:4; - a_uint32_t service_code:8; - a_uint32_t ip_addr_0:20; - a_uint32_t ip_addr_1:12; - a_uint32_t ip_protocol:8; - a_uint32_t _reserved1_0:12; - a_uint32_t _reserved1_1:32; -}; - -struct in_flow_3tuple_tbl_1 { - a_uint32_t valid:1; - a_uint32_t entry_type:1; - a_uint32_t host_addr_index_type:1; - a_uint32_t host_addr_index:13; - a_uint32_t protocol_type:2; - a_uint32_t age:2; - a_uint32_t src_l3_if_valid:1; - a_uint32_t src_l3_if:8; - a_uint32_t fwd_type:3; - a_uint32_t port_vp2:8; - a_uint32_t _reserved0:20; - a_uint32_t de_acce:1; - a_uint32_t copy_to_cpu_en:1; - a_uint32_t syn_toggle:1; - a_uint32_t pri_profile_0:1; - a_uint32_t pri_profile_1:4; - a_uint32_t service_code:8; - a_uint32_t ip_addr_0:20; - a_uint32_t ip_addr_1:12; - a_uint32_t ip_protocol:8; - a_uint32_t _reserved1_0:12; - a_uint32_t _reserved1_1:32; -}; - -struct in_flow_3tuple_tbl_2 { - a_uint32_t valid:1; - a_uint32_t entry_type:1; - a_uint32_t host_addr_index_type:1; - a_uint32_t host_addr_index:13; - a_uint32_t protocol_type:2; - a_uint32_t age:2; - a_uint32_t src_l3_if_valid:1; - a_uint32_t src_l3_if:8; - a_uint32_t fwd_type:3; - a_uint32_t next_hop3:12; - a_uint32_t port_vp_valid1:1; - a_uint32_t port_vp1:8; - a_uint32_t _reserved0:7; - a_uint32_t de_acce:1; - a_uint32_t copy_to_cpu_en:1; - a_uint32_t syn_toggle:1; - a_uint32_t pri_profile_0:1; - a_uint32_t pri_profile_1:4; - a_uint32_t service_code:8; - a_uint32_t ip_addr_0:20; - a_uint32_t ip_addr_1:12; - a_uint32_t ip_protocol:8; - a_uint32_t _reserved1_0:12; - a_uint32_t _reserved1_1:32; -}; - -struct in_flow_3tuple_tbl_0 { - a_uint32_t valid:1; - a_uint32_t entry_type:1; - a_uint32_t host_addr_index_type:1; - a_uint32_t host_addr_index:13; - a_uint32_t protocol_type:2; - a_uint32_t age:2; - a_uint32_t src_l3_if_valid:1; - a_uint32_t src_l3_if:8; - a_uint32_t fwd_type:3; - a_uint32_t next_hop1:12; - a_uint32_t _reserved0:16; - a_uint32_t de_acce:1; - a_uint32_t copy_to_cpu_en:1; - a_uint32_t syn_toggle:1; - a_uint32_t pri_profile_0:1; - a_uint32_t pri_profile_1:4; - a_uint32_t service_code:8; - a_uint32_t ip_addr_0:20; - a_uint32_t ip_addr_1:12; - a_uint32_t ip_protocol:8; - a_uint32_t _reserved1_0:12; - a_uint32_t _reserved1_1:32; -}; - -union in_flow_3tuple_tbl_u { - a_uint32_t val[5]; - struct in_flow_3tuple_tbl_0 bf0; - struct in_flow_3tuple_tbl_1 bf1; - struct in_flow_3tuple_tbl_2 bf2; - struct in_flow_3tuple_tbl_3 bf3; -}; - -/*[table] IN_FLOW_IPV6_5TUPLE_TBL*/ -#define IN_FLOW_IPV6_5TUPLE_TBL -#define IN_FLOW_IPV6_5TUPLE_TBL_ADDRESS 0x40000 -#define IN_FLOW_IPV6_5TUPLE_TBL_NUM 2048 -#define IN_FLOW_IPV6_5TUPLE_TBL_INC 0x40 -#define IN_FLOW_IPV6_5TUPLE_TBL_TYPE REG_TYPE_RW -#define IN_FLOW_IPV6_5TUPLE_TBL_DEFAULT 0x0 - /*[field] VALID*/ - #define IN_FLOW_IPV6_5TUPLE_TBL_VALID - #define IN_FLOW_IPV6_5TUPLE_TBL_VALID_OFFSET 0 - #define IN_FLOW_IPV6_5TUPLE_TBL_VALID_LEN 1 - #define IN_FLOW_IPV6_5TUPLE_TBL_VALID_DEFAULT 0x0 - /*[field] ENTRY_TYPE*/ - #define IN_FLOW_IPV6_5TUPLE_TBL_ENTRY_TYPE - #define IN_FLOW_IPV6_5TUPLE_TBL_ENTRY_TYPE_OFFSET 1 - #define IN_FLOW_IPV6_5TUPLE_TBL_ENTRY_TYPE_LEN 1 - #define IN_FLOW_IPV6_5TUPLE_TBL_ENTRY_TYPE_DEFAULT 0x0 - /*[field] HOST_ADDR_INDEX_TYPE*/ - #define IN_FLOW_IPV6_5TUPLE_TBL_HOST_ADDR_INDEX_TYPE - #define IN_FLOW_IPV6_5TUPLE_TBL_HOST_ADDR_INDEX_TYPE_OFFSET 2 - #define IN_FLOW_IPV6_5TUPLE_TBL_HOST_ADDR_INDEX_TYPE_LEN 1 - #define IN_FLOW_IPV6_5TUPLE_TBL_HOST_ADDR_INDEX_TYPE_DEFAULT 0x0 - /*[field] HOST_ADDR_INDEX*/ - #define IN_FLOW_IPV6_5TUPLE_TBL_HOST_ADDR_INDEX - #define IN_FLOW_IPV6_5TUPLE_TBL_HOST_ADDR_INDEX_OFFSET 3 - #define IN_FLOW_IPV6_5TUPLE_TBL_HOST_ADDR_INDEX_LEN 13 - #define IN_FLOW_IPV6_5TUPLE_TBL_HOST_ADDR_INDEX_DEFAULT 0x0 - /*[field] PROTOCOL_TYPE*/ - #define IN_FLOW_IPV6_5TUPLE_TBL_PROTOCOL_TYPE - #define IN_FLOW_IPV6_5TUPLE_TBL_PROTOCOL_TYPE_OFFSET 16 - #define IN_FLOW_IPV6_5TUPLE_TBL_PROTOCOL_TYPE_LEN 2 - #define IN_FLOW_IPV6_5TUPLE_TBL_PROTOCOL_TYPE_DEFAULT 0x0 - /*[field] AGE*/ - #define IN_FLOW_IPV6_5TUPLE_TBL_AGE - #define IN_FLOW_IPV6_5TUPLE_TBL_AGE_OFFSET 18 - #define IN_FLOW_IPV6_5TUPLE_TBL_AGE_LEN 2 - #define IN_FLOW_IPV6_5TUPLE_TBL_AGE_DEFAULT 0x0 - /*[field] SRC_L3_IF_VALID*/ - #define IN_FLOW_IPV6_5TUPLE_TBL_SRC_L3_IF_VALID - #define IN_FLOW_IPV6_5TUPLE_TBL_SRC_L3_IF_VALID_OFFSET 20 - #define IN_FLOW_IPV6_5TUPLE_TBL_SRC_L3_IF_VALID_LEN 1 - #define IN_FLOW_IPV6_5TUPLE_TBL_SRC_L3_IF_VALID_DEFAULT 0x0 - /*[field] SRC_L3_IF*/ - #define IN_FLOW_IPV6_5TUPLE_TBL_SRC_L3_IF - #define IN_FLOW_IPV6_5TUPLE_TBL_SRC_L3_IF_OFFSET 21 - #define IN_FLOW_IPV6_5TUPLE_TBL_SRC_L3_IF_LEN 8 - #define IN_FLOW_IPV6_5TUPLE_TBL_SRC_L3_IF_DEFAULT 0x0 - /*[field] FWD_TYPE*/ - #define IN_FLOW_IPV6_5TUPLE_TBL_FWD_TYPE - #define IN_FLOW_IPV6_5TUPLE_TBL_FWD_TYPE_OFFSET 29 - #define IN_FLOW_IPV6_5TUPLE_TBL_FWD_TYPE_LEN 3 - #define IN_FLOW_IPV6_5TUPLE_TBL_FWD_TYPE_DEFAULT 0x0 - /*[field] NEXT_HOP2 reuse FWD_TYPE[3]*/ - #define IN_FLOW_IPV6_5TUPLE_TBL_NEXT_HOP2 - #define IN_FLOW_IPV6_5TUPLE_TBL_NEXT_HOP2_OFFSET 32 - #define IN_FLOW_IPV6_5TUPLE_TBL_NEXT_HOP2_LEN 12 - #define IN_FLOW_IPV6_5TUPLE_TBL_NEXT_HOP2_DEFAULT 0x0 - /*[field] PORT_VP2 reuse FWD_TYPE[1]*/ - #define IN_FLOW_IPV6_5TUPLE_TBL_PORT_VP2 - #define IN_FLOW_IPV6_5TUPLE_TBL_PORT_VP2_OFFSET 32 - #define IN_FLOW_IPV6_5TUPLE_TBL_PORT_VP2_LEN 8 - #define IN_FLOW_IPV6_5TUPLE_TBL_PORT_VP2_DEFAULT 0x0 - /*[field] NEXT_HOP3 reuse FWD_TYPE[2]*/ - #define IN_FLOW_IPV6_5TUPLE_TBL_NEXT_HOP3 - #define IN_FLOW_IPV6_5TUPLE_TBL_NEXT_HOP3_OFFSET 32 - #define IN_FLOW_IPV6_5TUPLE_TBL_NEXT_HOP3_LEN 12 - #define IN_FLOW_IPV6_5TUPLE_TBL_NEXT_HOP3_DEFAULT 0x0 - /*[field] NEXT_HOP1 reuse FWD_TYPE[0]*/ - #define IN_FLOW_IPV6_5TUPLE_TBL_NEXT_HOP1 - #define IN_FLOW_IPV6_5TUPLE_TBL_NEXT_HOP1_OFFSET 32 - #define IN_FLOW_IPV6_5TUPLE_TBL_NEXT_HOP1_LEN 12 - #define IN_FLOW_IPV6_5TUPLE_TBL_NEXT_HOP1_DEFAULT 0x0 - /*[field] PORT_VP_VALID1 reuse FWD_TYPE[2]*/ - #define IN_FLOW_IPV6_5TUPLE_TBL_PORT_VP_VALID1 - #define IN_FLOW_IPV6_5TUPLE_TBL_PORT_VP_VALID1_OFFSET 44 - #define IN_FLOW_IPV6_5TUPLE_TBL_PORT_VP_VALID1_LEN 1 - #define IN_FLOW_IPV6_5TUPLE_TBL_PORT_VP_VALID1_DEFAULT 0x0 - /*[field] PORT_VP1 reuse FWD_TYPE[2]*/ - #define IN_FLOW_IPV6_5TUPLE_TBL_PORT_VP1 - #define IN_FLOW_IPV6_5TUPLE_TBL_PORT_VP1_OFFSET 45 - #define IN_FLOW_IPV6_5TUPLE_TBL_PORT_VP1_LEN 8 - #define IN_FLOW_IPV6_5TUPLE_TBL_PORT_VP1_DEFAULT 0x0 - /*[field] DE_ACCE*/ - #define IN_FLOW_IPV6_5TUPLE_TBL_DE_ACCE - #define IN_FLOW_IPV6_5TUPLE_TBL_DE_ACCE_OFFSET 60 - #define IN_FLOW_IPV6_5TUPLE_TBL_DE_ACCE_LEN 1 - #define IN_FLOW_IPV6_5TUPLE_TBL_DE_ACCE_DEFAULT 0x0 - /*[field] COPY_TO_CPU_EN*/ - #define IN_FLOW_IPV6_5TUPLE_TBL_COPY_TO_CPU_EN - #define IN_FLOW_IPV6_5TUPLE_TBL_COPY_TO_CPU_EN_OFFSET 61 - #define IN_FLOW_IPV6_5TUPLE_TBL_COPY_TO_CPU_EN_LEN 1 - #define IN_FLOW_IPV6_5TUPLE_TBL_COPY_TO_CPU_EN_DEFAULT 0x0 - /*[field] SYN_TOGGLE*/ - #define IN_FLOW_IPV6_5TUPLE_TBL_SYN_TOGGLE - #define IN_FLOW_IPV6_5TUPLE_TBL_SYN_TOGGLE_OFFSET 62 - #define IN_FLOW_IPV6_5TUPLE_TBL_SYN_TOGGLE_LEN 1 - #define IN_FLOW_IPV6_5TUPLE_TBL_SYN_TOGGLE_DEFAULT 0x0 - /*[field] PRI_PROFILE*/ - #define IN_FLOW_IPV6_5TUPLE_TBL_PRI_PROFILE - #define IN_FLOW_IPV6_5TUPLE_TBL_PRI_PROFILE_OFFSET 63 - #define IN_FLOW_IPV6_5TUPLE_TBL_PRI_PROFILE_LEN 5 - #define IN_FLOW_IPV6_5TUPLE_TBL_PRI_PROFILE_DEFAULT 0x0 - /*[field] SERVICE_CODE*/ - #define IN_FLOW_IPV6_5TUPLE_TBL_SERVICE_CODE - #define IN_FLOW_IPV6_5TUPLE_TBL_SERVICE_CODE_OFFSET 68 - #define IN_FLOW_IPV6_5TUPLE_TBL_SERVICE_CODE_LEN 8 - #define IN_FLOW_IPV6_5TUPLE_TBL_SERVICE_CODE_DEFAULT 0x0 - /*[field] L4_SPORT*/ - #define IN_FLOW_IPV6_5TUPLE_TBL_L4_SPORT - #define IN_FLOW_IPV6_5TUPLE_TBL_L4_SPORT_OFFSET 108 - #define IN_FLOW_IPV6_5TUPLE_TBL_L4_SPORT_LEN 16 - #define IN_FLOW_IPV6_5TUPLE_TBL_L4_SPORT_DEFAULT 0x0 - /*[field] L4_DPORT*/ - #define IN_FLOW_IPV6_5TUPLE_TBL_L4_DPORT - #define IN_FLOW_IPV6_5TUPLE_TBL_L4_DPORT_OFFSET 124 - #define IN_FLOW_IPV6_5TUPLE_TBL_L4_DPORT_LEN 16 - #define IN_FLOW_IPV6_5TUPLE_TBL_L4_DPORT_DEFAULT 0x0 - /*[field] IP_ADDR*/ - #define IN_FLOW_IPV6_5TUPLE_TBL_IP_ADDR - #define IN_FLOW_IPV6_5TUPLE_TBL_IP_ADDR_OFFSET 140 - #define IN_FLOW_IPV6_5TUPLE_TBL_IP_ADDR_LEN 128 - #define IN_FLOW_IPV6_5TUPLE_TBL_IP_ADDR_DEFAULT 0x0 - -struct in_flow_ipv6_5tuple_tbl_1 { - a_uint32_t valid:1; - a_uint32_t entry_type:1; - a_uint32_t host_addr_index_type:1; - a_uint32_t host_addr_index:13; - a_uint32_t protocol_type:2; - a_uint32_t age:2; - a_uint32_t src_l3_if_valid:1; - a_uint32_t src_l3_if:8; - a_uint32_t fwd_type:3; - a_uint32_t port_vp2:8; - a_uint32_t _reserved0:20; - a_uint32_t de_acce:1; - a_uint32_t copy_to_cpu_en:1; - a_uint32_t syn_toggle:1; - a_uint32_t pri_profile_0:1; - a_uint32_t pri_profile_1:4; - a_uint32_t service_code:8; - a_uint32_t _reserved1_0:20; - a_uint32_t _reserved1_1:12; - a_uint32_t l4_sport:16; - a_uint32_t l4_dport_0:4; - a_uint32_t l4_dport_1:12; - a_uint32_t ip_addr_0:20; - a_uint32_t ip_addr_1:32; - a_uint32_t ip_addr_2:32; - a_uint32_t ip_addr_3:32; - a_uint32_t ip_addr_4:12; - a_uint32_t _reserved2:20; -}; - -struct in_flow_ipv6_5tuple_tbl_0 { - a_uint32_t valid:1; - a_uint32_t entry_type:1; - a_uint32_t host_addr_index_type:1; - a_uint32_t host_addr_index:13; - a_uint32_t protocol_type:2; - a_uint32_t age:2; - a_uint32_t src_l3_if_valid:1; - a_uint32_t src_l3_if:8; - a_uint32_t fwd_type:3; - a_uint32_t next_hop1:12; - a_uint32_t _reserved0:16; - a_uint32_t de_acce:1; - a_uint32_t copy_to_cpu_en:1; - a_uint32_t syn_toggle:1; - a_uint32_t pri_profile_0:1; - a_uint32_t pri_profile_1:4; - a_uint32_t service_code:8; - a_uint32_t _reserved1_0:20; - a_uint32_t _reserved1_1:12; - a_uint32_t l4_sport:16; - a_uint32_t l4_dport_0:4; - a_uint32_t l4_dport_1:12; - a_uint32_t ip_addr_0:20; - a_uint32_t ip_addr_1:32; - a_uint32_t ip_addr_2:32; - a_uint32_t ip_addr_3:32; - a_uint32_t ip_addr_4:12; - a_uint32_t _reserved2:20; -}; - -struct in_flow_ipv6_5tuple_tbl_2 { - a_uint32_t valid:1; - a_uint32_t entry_type:1; - a_uint32_t host_addr_index_type:1; - a_uint32_t host_addr_index:13; - a_uint32_t protocol_type:2; - a_uint32_t age:2; - a_uint32_t src_l3_if_valid:1; - a_uint32_t src_l3_if:8; - a_uint32_t fwd_type:3; - a_uint32_t next_hop3:12; - a_uint32_t port_vp_valid1:1; - a_uint32_t port_vp1:8; - a_uint32_t _reserved0:7; - a_uint32_t de_acce:1; - a_uint32_t copy_to_cpu_en:1; - a_uint32_t syn_toggle:1; - a_uint32_t pri_profile_0:1; - a_uint32_t pri_profile_1:4; - a_uint32_t service_code:8; - a_uint32_t _reserved1_0:20; - a_uint32_t _reserved1_1:12; - a_uint32_t l4_sport:16; - a_uint32_t l4_dport_0:4; - a_uint32_t l4_dport_1:12; - a_uint32_t ip_addr_0:20; - a_uint32_t ip_addr_1:32; - a_uint32_t ip_addr_2:32; - a_uint32_t ip_addr_3:32; - a_uint32_t ip_addr_4:12; - a_uint32_t _reserved2:20; -}; - -struct in_flow_ipv6_5tuple_tbl_3 { - a_uint32_t valid:1; - a_uint32_t entry_type:1; - a_uint32_t host_addr_index_type:1; - a_uint32_t host_addr_index:13; - a_uint32_t protocol_type:2; - a_uint32_t age:2; - a_uint32_t src_l3_if_valid:1; - a_uint32_t src_l3_if:8; - a_uint32_t fwd_type:3; - a_uint32_t next_hop2:12; - a_uint32_t _reserved0:16; - a_uint32_t de_acce:1; - a_uint32_t copy_to_cpu_en:1; - a_uint32_t syn_toggle:1; - a_uint32_t pri_profile_0:1; - a_uint32_t pri_profile_1:4; - a_uint32_t service_code:8; - a_uint32_t _reserved1_0:20; - a_uint32_t _reserved1_1:12; - a_uint32_t l4_sport:16; - a_uint32_t l4_dport_0:4; - a_uint32_t l4_dport_1:12; - a_uint32_t ip_addr_0:20; - a_uint32_t ip_addr_1:32; - a_uint32_t ip_addr_2:32; - a_uint32_t ip_addr_3:32; - a_uint32_t ip_addr_4:12; - a_uint32_t _reserved2:20; -}; - -union in_flow_ipv6_5tuple_tbl_u { - a_uint32_t val[9]; - struct in_flow_ipv6_5tuple_tbl_0 bf0; - struct in_flow_ipv6_5tuple_tbl_1 bf1; - struct in_flow_ipv6_5tuple_tbl_2 bf2; - struct in_flow_ipv6_5tuple_tbl_3 bf3; -}; - -/*[table] IN_FLOW_TBL*/ -#define IN_FLOW_TBL -#define IN_FLOW_TBL_ADDRESS 0x40000 -#define IN_FLOW_TBL_NUM 4096 -#define IN_FLOW_TBL_INC 0x20 -#define IN_FLOW_TBL_TYPE REG_TYPE_RW -#define IN_FLOW_TBL_DEFAULT 0x0 - /*[field] VALID*/ - #define IN_FLOW_TBL_VALID - #define IN_FLOW_TBL_VALID_OFFSET 0 - #define IN_FLOW_TBL_VALID_LEN 1 - #define IN_FLOW_TBL_VALID_DEFAULT 0x0 - /*[field] ENTRY_TYPE*/ - #define IN_FLOW_TBL_ENTRY_TYPE - #define IN_FLOW_TBL_ENTRY_TYPE_OFFSET 1 - #define IN_FLOW_TBL_ENTRY_TYPE_LEN 1 - #define IN_FLOW_TBL_ENTRY_TYPE_DEFAULT 0x0 - /*[field] HOST_ADDR_INDEX_TYPE*/ - #define IN_FLOW_TBL_HOST_ADDR_INDEX_TYPE - #define IN_FLOW_TBL_HOST_ADDR_INDEX_TYPE_OFFSET 2 - #define IN_FLOW_TBL_HOST_ADDR_INDEX_TYPE_LEN 1 - #define IN_FLOW_TBL_HOST_ADDR_INDEX_TYPE_DEFAULT 0x0 - /*[field] HOST_ADDR_INDEX*/ - #define IN_FLOW_TBL_HOST_ADDR_INDEX - #define IN_FLOW_TBL_HOST_ADDR_INDEX_OFFSET 3 - #define IN_FLOW_TBL_HOST_ADDR_INDEX_LEN 13 - #define IN_FLOW_TBL_HOST_ADDR_INDEX_DEFAULT 0x0 - /*[field] PROTOCOL_TYPE*/ - #define IN_FLOW_TBL_PROTOCOL_TYPE - #define IN_FLOW_TBL_PROTOCOL_TYPE_OFFSET 16 - #define IN_FLOW_TBL_PROTOCOL_TYPE_LEN 2 - #define IN_FLOW_TBL_PROTOCOL_TYPE_DEFAULT 0x0 - /*[field] AGE*/ - #define IN_FLOW_TBL_AGE - #define IN_FLOW_TBL_AGE_OFFSET 18 - #define IN_FLOW_TBL_AGE_LEN 2 - #define IN_FLOW_TBL_AGE_DEFAULT 0x0 - /*[field] SRC_L3_IF_VALID*/ - #define IN_FLOW_TBL_SRC_L3_IF_VALID - #define IN_FLOW_TBL_SRC_L3_IF_VALID_OFFSET 20 - #define IN_FLOW_TBL_SRC_L3_IF_VALID_LEN 1 - #define IN_FLOW_TBL_SRC_L3_IF_VALID_DEFAULT 0x0 - /*[field] SRC_L3_IF*/ - #define IN_FLOW_TBL_SRC_L3_IF - #define IN_FLOW_TBL_SRC_L3_IF_OFFSET 21 - #define IN_FLOW_TBL_SRC_L3_IF_LEN 8 - #define IN_FLOW_TBL_SRC_L3_IF_DEFAULT 0x0 - /*[field] FWD_TYPE*/ - #define IN_FLOW_TBL_FWD_TYPE - #define IN_FLOW_TBL_FWD_TYPE_OFFSET 29 - #define IN_FLOW_TBL_FWD_TYPE_LEN 3 - #define IN_FLOW_TBL_FWD_TYPE_DEFAULT 0x0 - /*[field] PORT_VP2 reuse FWD_TYPE[1]*/ - #define IN_FLOW_TBL_PORT_VP2 - #define IN_FLOW_TBL_PORT_VP2_OFFSET 32 - #define IN_FLOW_TBL_PORT_VP2_LEN 8 - #define IN_FLOW_TBL_PORT_VP2_DEFAULT 0x0 - /*[field] NEXT_HOP2 reuse FWD_TYPE[3]*/ - #define IN_FLOW_TBL_NEXT_HOP2 - #define IN_FLOW_TBL_NEXT_HOP2_OFFSET 32 - #define IN_FLOW_TBL_NEXT_HOP2_LEN 12 - #define IN_FLOW_TBL_NEXT_HOP2_DEFAULT 0x0 - /*[field] NEXT_HOP3 reuse FWD_TYPE[2]*/ - #define IN_FLOW_TBL_NEXT_HOP3 - #define IN_FLOW_TBL_NEXT_HOP3_OFFSET 32 - #define IN_FLOW_TBL_NEXT_HOP3_LEN 12 - #define IN_FLOW_TBL_NEXT_HOP3_DEFAULT 0x0 - /*[field] NEXT_HOP1 reuse FWD_TYPE[0]*/ - #define IN_FLOW_TBL_NEXT_HOP1 - #define IN_FLOW_TBL_NEXT_HOP1_OFFSET 32 - #define IN_FLOW_TBL_NEXT_HOP1_LEN 12 - #define IN_FLOW_TBL_NEXT_HOP1_DEFAULT 0x0 - /*[field] L4_PORT2 reuse FWD_TYPE[3]*/ - #define IN_FLOW_TBL_L4_PORT2 - #define IN_FLOW_TBL_L4_PORT2_OFFSET 44 - #define IN_FLOW_TBL_L4_PORT2_LEN 16 - #define IN_FLOW_TBL_L4_PORT2_DEFAULT 0x0 - /*[field] PORT_VP_VALID1 reuse FWD_TYPE[2]*/ - #define IN_FLOW_TBL_PORT_VP_VALID1 - #define IN_FLOW_TBL_PORT_VP_VALID1_OFFSET 44 - #define IN_FLOW_TBL_PORT_VP_VALID1_LEN 1 - #define IN_FLOW_TBL_PORT_VP_VALID1_DEFAULT 0x0 - /*[field] L4_PORT1 reuse FWD_TYPE[0]*/ - #define IN_FLOW_TBL_L4_PORT1 - #define IN_FLOW_TBL_L4_PORT1_OFFSET 44 - #define IN_FLOW_TBL_L4_PORT1_LEN 16 - #define IN_FLOW_TBL_L4_PORT1_DEFAULT 0x0 - /*[field] PORT_VP1 reuse FWD_TYPE[2]*/ - #define IN_FLOW_TBL_PORT_VP1 - #define IN_FLOW_TBL_PORT_VP1_OFFSET 45 - #define IN_FLOW_TBL_PORT_VP1_LEN 8 - #define IN_FLOW_TBL_PORT_VP1_DEFAULT 0x0 - /*[field] DE_ACCE*/ - #define IN_FLOW_TBL_DE_ACCE - #define IN_FLOW_TBL_DE_ACCE_OFFSET 60 - #define IN_FLOW_TBL_DE_ACCE_LEN 1 - #define IN_FLOW_TBL_DE_ACCE_DEFAULT 0x0 - /*[field] COPY_TO_CPU_EN*/ - #define IN_FLOW_TBL_COPY_TO_CPU_EN - #define IN_FLOW_TBL_COPY_TO_CPU_EN_OFFSET 61 - #define IN_FLOW_TBL_COPY_TO_CPU_EN_LEN 1 - #define IN_FLOW_TBL_COPY_TO_CPU_EN_DEFAULT 0x0 - /*[field] SYN_TOGGLE*/ - #define IN_FLOW_TBL_SYN_TOGGLE - #define IN_FLOW_TBL_SYN_TOGGLE_OFFSET 62 - #define IN_FLOW_TBL_SYN_TOGGLE_LEN 1 - #define IN_FLOW_TBL_SYN_TOGGLE_DEFAULT 0x0 - /*[field] PRI_PROFILE*/ - #define IN_FLOW_TBL_PRI_PROFILE - #define IN_FLOW_TBL_PRI_PROFILE_OFFSET 63 - #define IN_FLOW_TBL_PRI_PROFILE_LEN 5 - #define IN_FLOW_TBL_PRI_PROFILE_DEFAULT 0x0 - /*[field] SERVICE_CODE*/ - #define IN_FLOW_TBL_SERVICE_CODE - #define IN_FLOW_TBL_SERVICE_CODE_OFFSET 68 - #define IN_FLOW_TBL_SERVICE_CODE_LEN 8 - #define IN_FLOW_TBL_SERVICE_CODE_DEFAULT 0x0 - /*[field] IP_ADDR*/ - #define IN_FLOW_TBL_IP_ADDR - #define IN_FLOW_TBL_IP_ADDR_OFFSET 76 - #define IN_FLOW_TBL_IP_ADDR_LEN 32 - #define IN_FLOW_TBL_IP_ADDR_DEFAULT 0x0 - /*[field] L4_SPORT*/ - #define IN_FLOW_TBL_L4_SPORT - #define IN_FLOW_TBL_L4_SPORT_OFFSET 108 - #define IN_FLOW_TBL_L4_SPORT_LEN 16 - #define IN_FLOW_TBL_L4_SPORT_DEFAULT 0x0 - /*[field] L4_DPORT*/ - #define IN_FLOW_TBL_L4_DPORT - #define IN_FLOW_TBL_L4_DPORT_OFFSET 124 - #define IN_FLOW_TBL_L4_DPORT_LEN 16 - #define IN_FLOW_TBL_L4_DPORT_DEFAULT 0x0 - -struct in_flow_ipv6_3tuple_tbl_3 { - a_uint32_t valid:1; - a_uint32_t entry_type:1; - a_uint32_t host_addr_index_type:1; - a_uint32_t host_addr_index:13; - a_uint32_t protocol_type:2; - a_uint32_t age:2; - a_uint32_t src_l3_if_valid:1; - a_uint32_t src_l3_if:8; - a_uint32_t fwd_type:3; - a_uint32_t next_hop2:12; - a_uint32_t _reserved0:16; - a_uint32_t de_acce:1; - a_uint32_t copy_to_cpu_en:1; - a_uint32_t syn_toggle:1; - a_uint32_t pri_profile_0:1; - a_uint32_t pri_profile_1:4; - a_uint32_t service_code:8; - a_uint32_t _reserved1_0:20; - a_uint32_t _reserved1_1:12; - a_uint32_t ip_protocol:8; - a_uint32_t _reserved2_0:12; - a_uint32_t _reserved2_1:12; - a_uint32_t ip_addr_0:20; - a_uint32_t ip_addr_1:32; - a_uint32_t ip_addr_2:32; - a_uint32_t ip_addr_3:32; - a_uint32_t ip_addr_4:12; - a_uint32_t _reserved3:20; -}; - -struct in_flow_ipv6_3tuple_tbl_1 { - a_uint32_t valid:1; - a_uint32_t entry_type:1; - a_uint32_t host_addr_index_type:1; - a_uint32_t host_addr_index:13; - a_uint32_t protocol_type:2; - a_uint32_t age:2; - a_uint32_t src_l3_if_valid:1; - a_uint32_t src_l3_if:8; - a_uint32_t fwd_type:3; - a_uint32_t next_hop1:12; - a_uint32_t _reserved0:16; - a_uint32_t de_acce:1; - a_uint32_t copy_to_cpu_en:1; - a_uint32_t syn_toggle:1; - a_uint32_t pri_profile_0:1; - a_uint32_t pri_profile_1:4; - a_uint32_t service_code:8; - a_uint32_t _reserved1_0:20; - a_uint32_t _reserved1_1:12; - a_uint32_t ip_protocol:8; - a_uint32_t _reserved2_0:12; - a_uint32_t _reserved2_1:12; - a_uint32_t ip_addr_0:20; - a_uint32_t ip_addr_1:32; - a_uint32_t ip_addr_2:32; - a_uint32_t ip_addr_3:32; - a_uint32_t ip_addr_4:12; - a_uint32_t _reserved3:20; -}; - -struct in_flow_ipv6_3tuple_tbl_0 { - a_uint32_t valid:1; - a_uint32_t entry_type:1; - a_uint32_t host_addr_index_type:1; - a_uint32_t host_addr_index:13; - a_uint32_t protocol_type:2; - a_uint32_t age:2; - a_uint32_t src_l3_if_valid:1; - a_uint32_t src_l3_if:8; - a_uint32_t fwd_type:3; - a_uint32_t port_vp2:8; - a_uint32_t _reserved0:20; - a_uint32_t de_acce:1; - a_uint32_t copy_to_cpu_en:1; - a_uint32_t syn_toggle:1; - a_uint32_t pri_profile_0:1; - a_uint32_t pri_profile_1:4; - a_uint32_t service_code:8; - a_uint32_t _reserved1_0:20; - a_uint32_t _reserved1_1:12; - a_uint32_t ip_protocol:8; - a_uint32_t _reserved2_0:12; - a_uint32_t _reserved2_1:12; - a_uint32_t ip_addr_0:20; - a_uint32_t ip_addr_1:32; - a_uint32_t ip_addr_2:32; - a_uint32_t ip_addr_3:32; - a_uint32_t ip_addr_4:12; - a_uint32_t _reserved3:20; -}; - -struct in_flow_ipv6_3tuple_tbl_2 { - a_uint32_t valid:1; - a_uint32_t entry_type:1; - a_uint32_t host_addr_index_type:1; - a_uint32_t host_addr_index:13; - a_uint32_t protocol_type:2; - a_uint32_t age:2; - a_uint32_t src_l3_if_valid:1; - a_uint32_t src_l3_if:8; - a_uint32_t fwd_type:3; - a_uint32_t next_hop3:12; - a_uint32_t port_vp_valid1:1; - a_uint32_t port_vp1:8; - a_uint32_t _reserved0:7; - a_uint32_t de_acce:1; - a_uint32_t copy_to_cpu_en:1; - a_uint32_t syn_toggle:1; - a_uint32_t pri_profile_0:1; - a_uint32_t pri_profile_1:4; - a_uint32_t service_code:8; - a_uint32_t _reserved1_0:20; - a_uint32_t _reserved1_1:12; - a_uint32_t ip_protocol:8; - a_uint32_t _reserved2_0:12; - a_uint32_t _reserved2_1:12; - a_uint32_t ip_addr_0:20; - a_uint32_t ip_addr_1:32; - a_uint32_t ip_addr_2:32; - a_uint32_t ip_addr_3:32; - a_uint32_t ip_addr_4:12; - a_uint32_t _reserved3:20; -}; - -union in_flow_ipv6_3tuple_tbl_u { - a_uint32_t val[9]; - struct in_flow_ipv6_3tuple_tbl_0 bf0; - struct in_flow_ipv6_3tuple_tbl_1 bf1; - struct in_flow_ipv6_3tuple_tbl_2 bf2; - struct in_flow_ipv6_3tuple_tbl_3 bf3; -}; - -/*[table] EG_FLOW_TREE_MAP_TBL*/ -#define EG_FLOW_TREE_MAP_TBL -#define EG_FLOW_TREE_MAP_TBL_ADDRESS 0x8000 -#define EG_FLOW_TREE_MAP_TBL_NUM 4096 -#define EG_FLOW_TREE_MAP_TBL_INC 0x4 -#define EG_FLOW_TREE_MAP_TBL_TYPE REG_TYPE_RW -#define EG_FLOW_TREE_MAP_TBL_DEFAULT 0x0 - /*[field] TREE_ID*/ - #define EG_FLOW_TREE_MAP_TBL_TREE_ID - #define EG_FLOW_TREE_MAP_TBL_TREE_ID_OFFSET 0 - #define EG_FLOW_TREE_MAP_TBL_TREE_ID_LEN 24 - #define EG_FLOW_TREE_MAP_TBL_TREE_ID_DEFAULT 0x0 - -struct eg_flow_tree_map_tbl { - a_uint32_t tree_id:24; - a_uint32_t _reserved0:8; -}; - -union eg_flow_tree_map_tbl_u { - a_uint32_t val; - struct eg_flow_tree_map_tbl bf; -}; - -/*[table] IN_FLOW_CNT_TBL*/ -#define IN_FLOW_CNT_TBL -#define IN_FLOW_CNT_TBL_ADDRESS 0x20000 -#define IN_FLOW_CNT_TBL_NUM 4096 -#define IN_FLOW_CNT_TBL_INC 0x10 -#define IN_FLOW_CNT_TBL_TYPE REG_TYPE_RW -#define IN_FLOW_CNT_TBL_DEFAULT 0x0 - /*[field] HIT_PKT_COUNTER*/ - #define IN_FLOW_CNT_TBL_HIT_PKT_COUNTER - #define IN_FLOW_CNT_TBL_HIT_PKT_COUNTER_OFFSET 0 - #define IN_FLOW_CNT_TBL_HIT_PKT_COUNTER_LEN 32 - #define IN_FLOW_CNT_TBL_HIT_PKT_COUNTER_DEFAULT 0x0 - /*[field] HIT_BYTE_COUNTER*/ - #define IN_FLOW_CNT_TBL_HIT_BYTE_COUNTER - #define IN_FLOW_CNT_TBL_HIT_BYTE_COUNTER_OFFSET 32 - #define IN_FLOW_CNT_TBL_HIT_BYTE_COUNTER_LEN 40 - #define IN_FLOW_CNT_TBL_HIT_BYTE_COUNTER_DEFAULT 0x0 - -struct in_flow_cnt_tbl { - a_uint32_t hit_pkt_counter:32; - a_uint32_t hit_byte_counter_0:32; - a_uint32_t hit_byte_counter_1:8; - a_uint32_t _reserved0:24; -}; - -union in_flow_cnt_tbl_u { - a_uint32_t val[3]; - struct in_flow_cnt_tbl bf; -}; - -#endif \ No newline at end of file diff --git a/feeds/ipq807x/qca-ssdk/src/include/hsl/hppe/hppe_global.h b/feeds/ipq807x/qca-ssdk/src/include/hsl/hppe/hppe_global.h deleted file mode 100755 index def29f93e..000000000 --- a/feeds/ipq807x/qca-ssdk/src/include/hsl/hppe/hppe_global.h +++ /dev/null @@ -1,1204 +0,0 @@ -/* - * Copyright (c) 2016-2017, The Linux Foundation. All rights reserved. - * Permission to use, copy, modify, and/or distribute this software for - * any purpose with or without fee is hereby granted, provided that the - * above copyright notice and this permission notice appear in all copies. - * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES - * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR - * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES - * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN - * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT - * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. - */ - - -/** - * @defgroup - * @{ - */ -#ifndef _HPPE_GLOBAL_H_ -#define _HPPE_GLOBAL_H_ - -sw_error_t -hppe_switch_id_get( - a_uint32_t dev_id, - union switch_id_u *value); - -sw_error_t -hppe_switch_id_set( - a_uint32_t dev_id, - union switch_id_u *value); - -sw_error_t -hppe_rgmii_ctrl_get( - a_uint32_t dev_id, - union rgmii_ctrl_u *value); - -sw_error_t -hppe_rgmii_ctrl_set( - a_uint32_t dev_id, - union rgmii_ctrl_u *value); - -sw_error_t -hppe_clk_gating_ctrl_get( - a_uint32_t dev_id, - union clk_gating_ctrl_u *value); - -sw_error_t -hppe_clk_gating_ctrl_set( - a_uint32_t dev_id, - union clk_gating_ctrl_u *value); - -sw_error_t -hppe_port_mux_ctrl_get( - a_uint32_t dev_id, - union port_mux_ctrl_u *value); - -sw_error_t -hppe_port_mux_ctrl_set( - a_uint32_t dev_id, - union port_mux_ctrl_u *value); - -sw_error_t -cppe_port_mux_ctrl_get( - a_uint32_t dev_id, - union cppe_port_mux_ctrl_u *value); - -sw_error_t -cppe_port_mux_ctrl_set( - a_uint32_t dev_id, - union cppe_port_mux_ctrl_u *value); - -sw_error_t -hppe_module_ini_done_int_get( - a_uint32_t dev_id, - union module_ini_done_int_u *value); - -sw_error_t -hppe_module_ini_done_int_set( - a_uint32_t dev_id, - union module_ini_done_int_u *value); - -sw_error_t -hppe_module_cpu_done_int_get( - a_uint32_t dev_id, - union module_cpu_done_int_u *value); - -sw_error_t -hppe_module_cpu_done_int_set( - a_uint32_t dev_id, - union module_cpu_done_int_u *value); - -sw_error_t -hppe_port_link_int_get( - a_uint32_t dev_id, - union port_link_int_u *value); - -sw_error_t -hppe_port_link_int_set( - a_uint32_t dev_id, - union port_link_int_u *value); - -sw_error_t -hppe_module_ini_done_int_mask_get( - a_uint32_t dev_id, - union module_ini_done_int_mask_u *value); - -sw_error_t -hppe_module_ini_done_int_mask_set( - a_uint32_t dev_id, - union module_ini_done_int_mask_u *value); - -sw_error_t -hppe_module_cpu_done_int_mask_get( - a_uint32_t dev_id, - union module_cpu_done_int_mask_u *value); - -sw_error_t -hppe_module_cpu_done_int_mask_set( - a_uint32_t dev_id, - union module_cpu_done_int_mask_u *value); - -sw_error_t -hppe_port_link_int_mask_get( - a_uint32_t dev_id, - union port_link_int_mask_u *value); - -sw_error_t -hppe_port_link_int_mask_set( - a_uint32_t dev_id, - union port_link_int_mask_u *value); - -sw_error_t -hppe_port_phy_status_0_get( - a_uint32_t dev_id, - union port_phy_status_0_u *value); - -sw_error_t -hppe_port_phy_status_0_set( - a_uint32_t dev_id, - union port_phy_status_0_u *value); - -sw_error_t -hppe_port_phy_status_1_get( - a_uint32_t dev_id, - union port_phy_status_1_u *value); - -sw_error_t -hppe_port_phy_status_1_set( - a_uint32_t dev_id, - union port_phy_status_1_u *value); - -sw_error_t -hppe_port1_status_get( - a_uint32_t dev_id, - union port1_status_u *value); - -sw_error_t -hppe_port1_status_set( - a_uint32_t dev_id, - union port1_status_u *value); - -sw_error_t -hppe_port2_status_get( - a_uint32_t dev_id, - union port2_status_u *value); - -sw_error_t -hppe_port2_status_set( - a_uint32_t dev_id, - union port2_status_u *value); - -sw_error_t -hppe_port3_status_get( - a_uint32_t dev_id, - union port3_status_u *value); - -sw_error_t -hppe_port3_status_set( - a_uint32_t dev_id, - union port3_status_u *value); - -sw_error_t -hppe_port4_status_get( - a_uint32_t dev_id, - union port4_status_u *value); - -sw_error_t -hppe_port4_status_set( - a_uint32_t dev_id, - union port4_status_u *value); - -sw_error_t -hppe_port5_status_get( - a_uint32_t dev_id, - union port5_status_u *value); - -sw_error_t -hppe_port5_status_set( - a_uint32_t dev_id, - union port5_status_u *value); - -sw_error_t -hppe_port6_status_get( - a_uint32_t dev_id, - union port6_status_u *value); - -sw_error_t -hppe_port6_status_set( - a_uint32_t dev_id, - union port6_status_u *value); - -sw_error_t -hppe_reserved_regs_0_get( - a_uint32_t dev_id, - union reserved_regs_0_u *value); - -sw_error_t -hppe_reserved_regs_0_set( - a_uint32_t dev_id, - union reserved_regs_0_u *value); - -sw_error_t -hppe_reserved_regs_1_get( - a_uint32_t dev_id, - union reserved_regs_1_u *value); - -sw_error_t -hppe_reserved_regs_1_set( - a_uint32_t dev_id, - union reserved_regs_1_u *value); - -sw_error_t -hppe_reserved_regs_2_get( - a_uint32_t dev_id, - union reserved_regs_2_u *value); - -sw_error_t -hppe_reserved_regs_2_set( - a_uint32_t dev_id, - union reserved_regs_2_u *value); - -sw_error_t -hppe_reserved_regs_3_get( - a_uint32_t dev_id, - union reserved_regs_3_u *value); - -sw_error_t -hppe_reserved_regs_3_set( - a_uint32_t dev_id, - union reserved_regs_3_u *value); - -sw_error_t -hppe_dbg_data_sel_get( - a_uint32_t dev_id, - union dbg_data_sel_u *value); - -sw_error_t -hppe_dbg_data_sel_set( - a_uint32_t dev_id, - union dbg_data_sel_u *value); - -sw_error_t -hppe_switch_id_dev_id_get( - a_uint32_t dev_id, - unsigned int *value); - -sw_error_t -hppe_switch_id_dev_id_set( - a_uint32_t dev_id, - unsigned int value); - -sw_error_t -hppe_switch_id_rev_id_get( - a_uint32_t dev_id, - unsigned int *value); - -sw_error_t -hppe_switch_id_rev_id_set( - a_uint32_t dev_id, - unsigned int value); - -sw_error_t -hppe_rgmii_ctrl_rgmii_ctrl_get( - a_uint32_t dev_id, - unsigned int *value); - -sw_error_t -hppe_rgmii_ctrl_rgmii_ctrl_set( - a_uint32_t dev_id, - unsigned int value); - -sw_error_t -hppe_clk_gating_ctrl_clk_gating_ctrl_get( - a_uint32_t dev_id, - unsigned int *value); - -sw_error_t -hppe_clk_gating_ctrl_clk_gating_ctrl_set( - a_uint32_t dev_id, - unsigned int value); - -sw_error_t -hppe_port_mux_ctrl_port6_pcs_sel_get( - a_uint32_t dev_id, - unsigned int *value); - -sw_error_t -hppe_port_mux_ctrl_port6_pcs_sel_set( - a_uint32_t dev_id, - unsigned int value); - -sw_error_t -hppe_port_mux_ctrl_port5_gmac_sel_get( - a_uint32_t dev_id, - unsigned int *value); - -sw_error_t -hppe_port_mux_ctrl_port5_gmac_sel_set( - a_uint32_t dev_id, - unsigned int value); - -sw_error_t -hppe_port_mux_ctrl_port5_pcs_sel_get( - a_uint32_t dev_id, - unsigned int *value); - -sw_error_t -hppe_port_mux_ctrl_port5_pcs_sel_set( - a_uint32_t dev_id, - unsigned int value); - -sw_error_t -hppe_port_mux_ctrl_port4_pcs_sel_get( - a_uint32_t dev_id, - unsigned int *value); - -sw_error_t -hppe_port_mux_ctrl_port4_pcs_sel_set( - a_uint32_t dev_id, - unsigned int value); - -sw_error_t -hppe_port_mux_ctrl_port6_gmac_sel_get( - a_uint32_t dev_id, - unsigned int *value); - -sw_error_t -hppe_port_mux_ctrl_port6_gmac_sel_set( - a_uint32_t dev_id, - unsigned int value); - -sw_error_t -hppe_module_ini_done_int_iv_ini_done_int_get( - a_uint32_t dev_id, - unsigned int *value); - -sw_error_t -hppe_module_ini_done_int_iv_ini_done_int_set( - a_uint32_t dev_id, - unsigned int value); - -sw_error_t -hppe_module_ini_done_int_qm_ini_done_int_get( - a_uint32_t dev_id, - unsigned int *value); - -sw_error_t -hppe_module_ini_done_int_qm_ini_done_int_set( - a_uint32_t dev_id, - unsigned int value); - -sw_error_t -hppe_module_ini_done_int_l3_ini_done_int_get( - a_uint32_t dev_id, - unsigned int *value); - -sw_error_t -hppe_module_ini_done_int_l3_ini_done_int_set( - a_uint32_t dev_id, - unsigned int value); - -sw_error_t -hppe_module_ini_done_int_bm_ini_done_int_get( - a_uint32_t dev_id, - unsigned int *value); - -sw_error_t -hppe_module_ini_done_int_bm_ini_done_int_set( - a_uint32_t dev_id, - unsigned int value); - -sw_error_t -hppe_module_ini_done_int_ptx_ini_done_int_get( - a_uint32_t dev_id, - unsigned int *value); - -sw_error_t -hppe_module_ini_done_int_ptx_ini_done_int_set( - a_uint32_t dev_id, - unsigned int value); - -sw_error_t -hppe_module_ini_done_int_tm_ini_done_int_get( - a_uint32_t dev_id, - unsigned int *value); - -sw_error_t -hppe_module_ini_done_int_tm_ini_done_int_set( - a_uint32_t dev_id, - unsigned int value); - -sw_error_t -hppe_module_ini_done_int_l2_ini_done_int_get( - a_uint32_t dev_id, - unsigned int *value); - -sw_error_t -hppe_module_ini_done_int_l2_ini_done_int_set( - a_uint32_t dev_id, - unsigned int value); - -sw_error_t -hppe_module_ini_done_int_acl_ini_done_int_get( - a_uint32_t dev_id, - unsigned int *value); - -sw_error_t -hppe_module_ini_done_int_acl_ini_done_int_set( - a_uint32_t dev_id, - unsigned int value); - -sw_error_t -hppe_module_ini_done_int_ing_rate_ini_done_int_get( - a_uint32_t dev_id, - unsigned int *value); - -sw_error_t -hppe_module_ini_done_int_ing_rate_ini_done_int_set( - a_uint32_t dev_id, - unsigned int value); - -sw_error_t -hppe_module_cpu_done_int_l3_flow_wr_cmd_overflow_int_get( - a_uint32_t dev_id, - unsigned int *value); - -sw_error_t -hppe_module_cpu_done_int_l3_flow_wr_cmd_overflow_int_set( - a_uint32_t dev_id, - unsigned int value); - -sw_error_t -hppe_module_cpu_done_int_l2_fdb_rd_cmd_overflow_int_get( - a_uint32_t dev_id, - unsigned int *value); - -sw_error_t -hppe_module_cpu_done_int_l2_fdb_rd_cmd_overflow_int_set( - a_uint32_t dev_id, - unsigned int value); - -sw_error_t -hppe_module_cpu_done_int_qm_cpu_op_done_int_get( - a_uint32_t dev_id, - unsigned int *value); - -sw_error_t -hppe_module_cpu_done_int_qm_cpu_op_done_int_set( - a_uint32_t dev_id, - unsigned int value); - -sw_error_t -hppe_module_cpu_done_int_l3_flow_rd_cmd_overflow_int_get( - a_uint32_t dev_id, - unsigned int *value); - -sw_error_t -hppe_module_cpu_done_int_l3_flow_rd_cmd_overflow_int_set( - a_uint32_t dev_id, - unsigned int value); - -sw_error_t -hppe_module_cpu_done_int_l2_fdb_wr_result_vld_int_get( - a_uint32_t dev_id, - unsigned int *value); - -sw_error_t -hppe_module_cpu_done_int_l2_fdb_wr_result_vld_int_set( - a_uint32_t dev_id, - unsigned int value); - -sw_error_t -hppe_module_cpu_done_int_l2_fdb_rd_result_vld_int_get( - a_uint32_t dev_id, - unsigned int *value); - -sw_error_t -hppe_module_cpu_done_int_l2_fdb_rd_result_vld_int_set( - a_uint32_t dev_id, - unsigned int value); - -sw_error_t -hppe_module_cpu_done_int_l2_fdb_wr_cmd_overflow_int_get( - a_uint32_t dev_id, - unsigned int *value); - -sw_error_t -hppe_module_cpu_done_int_l2_fdb_wr_cmd_overflow_int_set( - a_uint32_t dev_id, - unsigned int value); - -sw_error_t -hppe_module_cpu_done_int_l3_flow_rd_result_vld_int_get( - a_uint32_t dev_id, - unsigned int *value); - -sw_error_t -hppe_module_cpu_done_int_l3_flow_rd_result_vld_int_set( - a_uint32_t dev_id, - unsigned int value); - -sw_error_t -hppe_module_cpu_done_int_l3_host_wr_cmd_overflow_int_get( - a_uint32_t dev_id, - unsigned int *value); - -sw_error_t -hppe_module_cpu_done_int_l3_host_wr_cmd_overflow_int_set( - a_uint32_t dev_id, - unsigned int value); - -sw_error_t -hppe_module_cpu_done_int_l3_host_rd_cmd_overflow_int_get( - a_uint32_t dev_id, - unsigned int *value); - -sw_error_t -hppe_module_cpu_done_int_l3_host_rd_cmd_overflow_int_set( - a_uint32_t dev_id, - unsigned int value); - -sw_error_t -hppe_module_cpu_done_int_l3_host_rd_result_vld_int_get( - a_uint32_t dev_id, - unsigned int *value); - -sw_error_t -hppe_module_cpu_done_int_l3_host_rd_result_vld_int_set( - a_uint32_t dev_id, - unsigned int value); - -sw_error_t -hppe_module_cpu_done_int_l3_host_wr_result_vld_int_get( - a_uint32_t dev_id, - unsigned int *value); - -sw_error_t -hppe_module_cpu_done_int_l3_host_wr_result_vld_int_set( - a_uint32_t dev_id, - unsigned int value); - -sw_error_t -hppe_module_cpu_done_int_l3_flow_wr_result_vld_int_get( - a_uint32_t dev_id, - unsigned int *value); - -sw_error_t -hppe_module_cpu_done_int_l3_flow_wr_result_vld_int_set( - a_uint32_t dev_id, - unsigned int value); - -sw_error_t -hppe_port_link_int_port6_link_chg_int_get( - a_uint32_t dev_id, - unsigned int *value); - -sw_error_t -hppe_port_link_int_port6_link_chg_int_set( - a_uint32_t dev_id, - unsigned int value); - -sw_error_t -hppe_port_link_int_xgmac0_an_done_int_get( - a_uint32_t dev_id, - unsigned int *value); - -sw_error_t -hppe_port_link_int_xgmac0_an_done_int_set( - a_uint32_t dev_id, - unsigned int value); - -sw_error_t -hppe_port_link_int_port5_1_link_chg_int_get( - a_uint32_t dev_id, - unsigned int *value); - -sw_error_t -hppe_port_link_int_port5_1_link_chg_int_set( - a_uint32_t dev_id, - unsigned int value); - -sw_error_t -hppe_port_link_int_port5_0_link_chg_int_get( - a_uint32_t dev_id, - unsigned int *value); - -sw_error_t -hppe_port_link_int_port5_0_link_chg_int_set( - a_uint32_t dev_id, - unsigned int value); - -sw_error_t -hppe_port_link_int_port4_link_chg_int_get( - a_uint32_t dev_id, - unsigned int *value); - -sw_error_t -hppe_port_link_int_port4_link_chg_int_set( - a_uint32_t dev_id, - unsigned int value); - -sw_error_t -hppe_port_link_int_port3_link_chg_int_get( - a_uint32_t dev_id, - unsigned int *value); - -sw_error_t -hppe_port_link_int_port3_link_chg_int_set( - a_uint32_t dev_id, - unsigned int value); - -sw_error_t -hppe_port_link_int_port2_link_chg_int_get( - a_uint32_t dev_id, - unsigned int *value); - -sw_error_t -hppe_port_link_int_port2_link_chg_int_set( - a_uint32_t dev_id, - unsigned int value); - -sw_error_t -hppe_port_link_int_xgmac1_an_done_int_get( - a_uint32_t dev_id, - unsigned int *value); - -sw_error_t -hppe_port_link_int_xgmac1_an_done_int_set( - a_uint32_t dev_id, - unsigned int value); - -sw_error_t -hppe_port_link_int_port1_link_chg_int_get( - a_uint32_t dev_id, - unsigned int *value); - -sw_error_t -hppe_port_link_int_port1_link_chg_int_set( - a_uint32_t dev_id, - unsigned int value); - -sw_error_t -hppe_module_ini_done_int_mask_tm_ini_done_int_mask_get( - a_uint32_t dev_id, - unsigned int *value); - -sw_error_t -hppe_module_ini_done_int_mask_tm_ini_done_int_mask_set( - a_uint32_t dev_id, - unsigned int value); - -sw_error_t -hppe_module_ini_done_int_mask_bm_ini_done_int_mask_get( - a_uint32_t dev_id, - unsigned int *value); - -sw_error_t -hppe_module_ini_done_int_mask_bm_ini_done_int_mask_set( - a_uint32_t dev_id, - unsigned int value); - -sw_error_t -hppe_module_ini_done_int_mask_iv_ini_done_int_mask_get( - a_uint32_t dev_id, - unsigned int *value); - -sw_error_t -hppe_module_ini_done_int_mask_iv_ini_done_int_mask_set( - a_uint32_t dev_id, - unsigned int value); - -sw_error_t -hppe_module_ini_done_int_mask_acl_ini_done_int_mask_get( - a_uint32_t dev_id, - unsigned int *value); - -sw_error_t -hppe_module_ini_done_int_mask_acl_ini_done_int_mask_set( - a_uint32_t dev_id, - unsigned int value); - -sw_error_t -hppe_module_ini_done_int_mask_qm_ini_done_int_mask_get( - a_uint32_t dev_id, - unsigned int *value); - -sw_error_t -hppe_module_ini_done_int_mask_qm_ini_done_int_mask_set( - a_uint32_t dev_id, - unsigned int value); - -sw_error_t -hppe_module_ini_done_int_mask_l2_ini_done_int_mask_get( - a_uint32_t dev_id, - unsigned int *value); - -sw_error_t -hppe_module_ini_done_int_mask_l2_ini_done_int_mask_set( - a_uint32_t dev_id, - unsigned int value); - -sw_error_t -hppe_module_ini_done_int_mask_ptx_ini_done_int_mask_get( - a_uint32_t dev_id, - unsigned int *value); - -sw_error_t -hppe_module_ini_done_int_mask_ptx_ini_done_int_mask_set( - a_uint32_t dev_id, - unsigned int value); - -sw_error_t -hppe_module_ini_done_int_mask_ing_rate_ini_done_int_mask_get( - a_uint32_t dev_id, - unsigned int *value); - -sw_error_t -hppe_module_ini_done_int_mask_ing_rate_ini_done_int_mask_set( - a_uint32_t dev_id, - unsigned int value); - -sw_error_t -hppe_module_ini_done_int_mask_l3_ini_done_int_mask_get( - a_uint32_t dev_id, - unsigned int *value); - -sw_error_t -hppe_module_ini_done_int_mask_l3_ini_done_int_mask_set( - a_uint32_t dev_id, - unsigned int value); - -sw_error_t -hppe_module_cpu_done_int_mask_l3_host_wr_result_vld_int_mask_get( - a_uint32_t dev_id, - unsigned int *value); - -sw_error_t -hppe_module_cpu_done_int_mask_l3_host_wr_result_vld_int_mask_set( - a_uint32_t dev_id, - unsigned int value); - -sw_error_t -hppe_module_cpu_done_int_mask_l3_flow_wr_result_vld_int_mask_get( - a_uint32_t dev_id, - unsigned int *value); - -sw_error_t -hppe_module_cpu_done_int_mask_l3_flow_wr_result_vld_int_mask_set( - a_uint32_t dev_id, - unsigned int value); - -sw_error_t -hppe_module_cpu_done_int_mask_l3_host_rd_cmd_overflow_int_mask_get( - a_uint32_t dev_id, - unsigned int *value); - -sw_error_t -hppe_module_cpu_done_int_mask_l3_host_rd_cmd_overflow_int_mask_set( - a_uint32_t dev_id, - unsigned int value); - -sw_error_t -hppe_module_cpu_done_int_mask_l3_flow_wr_cmd_overflow_int_mask_get( - a_uint32_t dev_id, - unsigned int *value); - -sw_error_t -hppe_module_cpu_done_int_mask_l3_flow_wr_cmd_overflow_int_mask_set( - a_uint32_t dev_id, - unsigned int value); - -sw_error_t -hppe_module_cpu_done_int_mask_l3_host_rd_result_vld_int_mask_get( - a_uint32_t dev_id, - unsigned int *value); - -sw_error_t -hppe_module_cpu_done_int_mask_l3_host_rd_result_vld_int_mask_set( - a_uint32_t dev_id, - unsigned int value); - -sw_error_t -hppe_module_cpu_done_int_mask_l2_fdb_rd_cmd_overflow_int_mask_get( - a_uint32_t dev_id, - unsigned int *value); - -sw_error_t -hppe_module_cpu_done_int_mask_l2_fdb_rd_cmd_overflow_int_mask_set( - a_uint32_t dev_id, - unsigned int value); - -sw_error_t -hppe_module_cpu_done_int_mask_l2_fdb_wr_cmd_overflow_int_mask_get( - a_uint32_t dev_id, - unsigned int *value); - -sw_error_t -hppe_module_cpu_done_int_mask_l2_fdb_wr_cmd_overflow_int_mask_set( - a_uint32_t dev_id, - unsigned int value); - -sw_error_t -hppe_module_cpu_done_int_mask_l3_host_wr_cmd_overflow_int_mask_get( - a_uint32_t dev_id, - unsigned int *value); - -sw_error_t -hppe_module_cpu_done_int_mask_l3_host_wr_cmd_overflow_int_mask_set( - a_uint32_t dev_id, - unsigned int value); - -sw_error_t -hppe_module_cpu_done_int_mask_l2_fdb_rd_result_vld_int_mask_get( - a_uint32_t dev_id, - unsigned int *value); - -sw_error_t -hppe_module_cpu_done_int_mask_l2_fdb_rd_result_vld_int_mask_set( - a_uint32_t dev_id, - unsigned int value); - -sw_error_t -hppe_module_cpu_done_int_mask_l2_fdb_wr_result_vld_int_mask_get( - a_uint32_t dev_id, - unsigned int *value); - -sw_error_t -hppe_module_cpu_done_int_mask_l2_fdb_wr_result_vld_int_mask_set( - a_uint32_t dev_id, - unsigned int value); - -sw_error_t -hppe_module_cpu_done_int_mask_qm_cpu_op_done_int_mask_get( - a_uint32_t dev_id, - unsigned int *value); - -sw_error_t -hppe_module_cpu_done_int_mask_qm_cpu_op_done_int_mask_set( - a_uint32_t dev_id, - unsigned int value); - -sw_error_t -hppe_module_cpu_done_int_mask_l3_flow_rd_result_vld_int_mask_get( - a_uint32_t dev_id, - unsigned int *value); - -sw_error_t -hppe_module_cpu_done_int_mask_l3_flow_rd_result_vld_int_mask_set( - a_uint32_t dev_id, - unsigned int value); - -sw_error_t -hppe_module_cpu_done_int_mask_l3_flow_rd_cmd_overflow_int_mask_get( - a_uint32_t dev_id, - unsigned int *value); - -sw_error_t -hppe_module_cpu_done_int_mask_l3_flow_rd_cmd_overflow_int_mask_set( - a_uint32_t dev_id, - unsigned int value); - -sw_error_t -hppe_port_link_int_mask_xgmac0_an_done_int_mask_get( - a_uint32_t dev_id, - unsigned int *value); - -sw_error_t -hppe_port_link_int_mask_xgmac0_an_done_int_mask_set( - a_uint32_t dev_id, - unsigned int value); - -sw_error_t -hppe_port_link_int_mask_port2_link_chg_int_mask_get( - a_uint32_t dev_id, - unsigned int *value); - -sw_error_t -hppe_port_link_int_mask_port2_link_chg_int_mask_set( - a_uint32_t dev_id, - unsigned int value); - -sw_error_t -hppe_port_link_int_mask_port4_link_chg_int_mask_get( - a_uint32_t dev_id, - unsigned int *value); - -sw_error_t -hppe_port_link_int_mask_port4_link_chg_int_mask_set( - a_uint32_t dev_id, - unsigned int value); - -sw_error_t -hppe_port_link_int_mask_port3_link_chg_int_mask_get( - a_uint32_t dev_id, - unsigned int *value); - -sw_error_t -hppe_port_link_int_mask_port3_link_chg_int_mask_set( - a_uint32_t dev_id, - unsigned int value); - -sw_error_t -hppe_port_link_int_mask_port5_1_link_chg_int_mask_get( - a_uint32_t dev_id, - unsigned int *value); - -sw_error_t -hppe_port_link_int_mask_port5_1_link_chg_int_mask_set( - a_uint32_t dev_id, - unsigned int value); - -sw_error_t -hppe_port_link_int_mask_xgmac1_an_done_int_mask_get( - a_uint32_t dev_id, - unsigned int *value); - -sw_error_t -hppe_port_link_int_mask_xgmac1_an_done_int_mask_set( - a_uint32_t dev_id, - unsigned int value); - -sw_error_t -hppe_port_link_int_mask_port1_link_chg_int_mask_get( - a_uint32_t dev_id, - unsigned int *value); - -sw_error_t -hppe_port_link_int_mask_port1_link_chg_int_mask_set( - a_uint32_t dev_id, - unsigned int value); - -sw_error_t -hppe_port_link_int_mask_port5_0_link_chg_int_mask_get( - a_uint32_t dev_id, - unsigned int *value); - -sw_error_t -hppe_port_link_int_mask_port5_0_link_chg_int_mask_set( - a_uint32_t dev_id, - unsigned int value); - -sw_error_t -hppe_port_link_int_mask_port6_link_chg_int_mask_get( - a_uint32_t dev_id, - unsigned int *value); - -sw_error_t -hppe_port_link_int_mask_port6_link_chg_int_mask_set( - a_uint32_t dev_id, - unsigned int value); - -sw_error_t -hppe_port_phy_status_0_port3_phy_status_get( - a_uint32_t dev_id, - unsigned int *value); - -sw_error_t -hppe_port_phy_status_0_port3_phy_status_set( - a_uint32_t dev_id, - unsigned int value); - -sw_error_t -hppe_port_phy_status_0_port4_phy_status_get( - a_uint32_t dev_id, - unsigned int *value); - -sw_error_t -hppe_port_phy_status_0_port4_phy_status_set( - a_uint32_t dev_id, - unsigned int value); - -sw_error_t -hppe_port_phy_status_0_port2_phy_status_get( - a_uint32_t dev_id, - unsigned int *value); - -sw_error_t -hppe_port_phy_status_0_port2_phy_status_set( - a_uint32_t dev_id, - unsigned int value); - -sw_error_t -hppe_port_phy_status_0_port1_phy_status_get( - a_uint32_t dev_id, - unsigned int *value); - -sw_error_t -hppe_port_phy_status_0_port1_phy_status_set( - a_uint32_t dev_id, - unsigned int value); - -sw_error_t -hppe_port_phy_status_1_port6_phy_status_get( - a_uint32_t dev_id, - unsigned int *value); - -sw_error_t -hppe_port_phy_status_1_port6_phy_status_set( - a_uint32_t dev_id, - unsigned int value); - -sw_error_t -hppe_port_phy_status_1_port5_0_phy_status_get( - a_uint32_t dev_id, - unsigned int *value); - -sw_error_t -hppe_port_phy_status_1_port5_0_phy_status_set( - a_uint32_t dev_id, - unsigned int value); - -sw_error_t -hppe_port_phy_status_1_port5_1_phy_status_get( - a_uint32_t dev_id, - unsigned int *value); - -sw_error_t -hppe_port_phy_status_1_port5_1_phy_status_set( - a_uint32_t dev_id, - unsigned int value); - -sw_error_t -hppe_port1_status_port1_status_get( - a_uint32_t dev_id, - unsigned int *value); - -sw_error_t -hppe_port1_status_port1_status_set( - a_uint32_t dev_id, - unsigned int value); - -sw_error_t -hppe_port2_status_port2_status_get( - a_uint32_t dev_id, - unsigned int *value); - -sw_error_t -hppe_port2_status_port2_status_set( - a_uint32_t dev_id, - unsigned int value); - -sw_error_t -hppe_port3_status_port3_status_get( - a_uint32_t dev_id, - unsigned int *value); - -sw_error_t -hppe_port3_status_port3_status_set( - a_uint32_t dev_id, - unsigned int value); - -sw_error_t -hppe_port4_status_port4_status_get( - a_uint32_t dev_id, - unsigned int *value); - -sw_error_t -hppe_port4_status_port4_status_set( - a_uint32_t dev_id, - unsigned int value); - -sw_error_t -hppe_port5_status_port3_mac_speed_get( - a_uint32_t dev_id, - unsigned int *value); - -sw_error_t -hppe_port5_status_port3_mac_speed_set( - a_uint32_t dev_id, - unsigned int value); - -sw_error_t -hppe_port5_status_port2_mac_speed_get( - a_uint32_t dev_id, - unsigned int *value); - -sw_error_t -hppe_port5_status_port2_mac_speed_set( - a_uint32_t dev_id, - unsigned int value); - -sw_error_t -hppe_port5_status_port1_mac_speed_get( - a_uint32_t dev_id, - unsigned int *value); - -sw_error_t -hppe_port5_status_port1_mac_speed_set( - a_uint32_t dev_id, - unsigned int value); - -sw_error_t -hppe_port5_status_port5_status_get( - a_uint32_t dev_id, - unsigned int *value); - -sw_error_t -hppe_port5_status_port5_status_set( - a_uint32_t dev_id, - unsigned int value); - -sw_error_t -hppe_port5_status_port4_mac_speed_get( - a_uint32_t dev_id, - unsigned int *value); - -sw_error_t -hppe_port5_status_port4_mac_speed_set( - a_uint32_t dev_id, - unsigned int value); - -sw_error_t -hppe_port6_status_port6_status_get( - a_uint32_t dev_id, - unsigned int *value); - -sw_error_t -hppe_port6_status_port6_status_set( - a_uint32_t dev_id, - unsigned int value); - -sw_error_t -hppe_reserved_regs_0_spare_regs_0_get( - a_uint32_t dev_id, - unsigned int *value); - -sw_error_t -hppe_reserved_regs_0_spare_regs_0_set( - a_uint32_t dev_id, - unsigned int value); - -sw_error_t -hppe_reserved_regs_1_spare_regs_1_get( - a_uint32_t dev_id, - unsigned int *value); - -sw_error_t -hppe_reserved_regs_1_spare_regs_1_set( - a_uint32_t dev_id, - unsigned int value); - -sw_error_t -hppe_reserved_regs_2_spare_regs_2_get( - a_uint32_t dev_id, - unsigned int *value); - -sw_error_t -hppe_reserved_regs_2_spare_regs_2_set( - a_uint32_t dev_id, - unsigned int value); - -sw_error_t -hppe_reserved_regs_3_spare_regs_3_get( - a_uint32_t dev_id, - unsigned int *value); - -sw_error_t -hppe_reserved_regs_3_spare_regs_3_set( - a_uint32_t dev_id, - unsigned int value); - -sw_error_t -hppe_dbg_data_sel_dbg_data_sel_desp_get( - a_uint32_t dev_id, - unsigned int *value); - -sw_error_t -hppe_dbg_data_sel_dbg_data_sel_desp_set( - a_uint32_t dev_id, - unsigned int value); - -sw_error_t -hppe_dbg_data_sel_dbg_data_sel_switch_get( - a_uint32_t dev_id, - unsigned int *value); - -sw_error_t -hppe_dbg_data_sel_dbg_data_sel_switch_set( - a_uint32_t dev_id, - unsigned int value); - -#endif - diff --git a/feeds/ipq807x/qca-ssdk/src/include/hsl/hppe/hppe_global_reg.h b/feeds/ipq807x/qca-ssdk/src/include/hsl/hppe/hppe_global_reg.h deleted file mode 100755 index 904f4f15a..000000000 --- a/feeds/ipq807x/qca-ssdk/src/include/hsl/hppe/hppe_global_reg.h +++ /dev/null @@ -1,988 +0,0 @@ -/* - * Copyright (c) 2016-2017, 2019, The Linux Foundation. All rights reserved. - * Permission to use, copy, modify, and/or distribute this software for - * any purpose with or without fee is hereby granted, provided that the - * above copyright notice and this permission notice appear in all copies. - * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES - * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR - * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES - * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN - * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT - * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. - */ - - -/** - * @defgroup - * @{ - */ -#ifndef HPPE_GLOBAL_REG_H -#define HPPE_GLOBAL_REG_H - -/*[register] SWITCH_ID*/ -#define SWITCH_ID -#define SWITCH_ID_ADDRESS 0x0 -#define SWITCH_ID_NUM 1 -#define SWITCH_ID_INC 0x4 -#define SWITCH_ID_TYPE REG_TYPE_RW -#define SWITCH_ID_DEFAULT 0x1500 - /*[field] REV_ID*/ - #define SWITCH_ID_REV_ID - #define SWITCH_ID_REV_ID_OFFSET 0 - #define SWITCH_ID_REV_ID_LEN 8 - #define SWITCH_ID_REV_ID_DEFAULT 0x0 - /*[field] DEV_ID*/ - #define SWITCH_ID_DEV_ID - #define SWITCH_ID_DEV_ID_OFFSET 8 - #define SWITCH_ID_DEV_ID_LEN 8 - #define SWITCH_ID_DEV_ID_DEFAULT 0x15 - -struct switch_id { - a_uint32_t rev_id:8; - a_uint32_t dev_id:8; - a_uint32_t _reserved0:16; -}; - -union switch_id_u { - a_uint32_t val; - struct switch_id bf; -}; - -/*[register] RGMII_CTRL*/ -#define RGMII_CTRL -#define RGMII_CTRL_ADDRESS 0x4 -#define RGMII_CTRL_NUM 1 -#define RGMII_CTRL_INC 0x4 -#define RGMII_CTRL_TYPE REG_TYPE_RW -#define RGMII_CTRL_DEFAULT 0x0 - /*[field] RGMII_CTRL*/ - #define RGMII_CTRL_RGMII_CTRL - #define RGMII_CTRL_RGMII_CTRL_OFFSET 0 - #define RGMII_CTRL_RGMII_CTRL_LEN 32 - #define RGMII_CTRL_RGMII_CTRL_DEFAULT 0x0 - -struct rgmii_ctrl { - a_uint32_t rgmii_ctrl:32; -}; - -union rgmii_ctrl_u { - a_uint32_t val; - struct rgmii_ctrl bf; -}; - -/*[register] CLK_GATING_CTRL*/ -#define CLK_GATING_CTRL -#define CLK_GATING_CTRL_ADDRESS 0x8 -#define CLK_GATING_CTRL_NUM 1 -#define CLK_GATING_CTRL_INC 0x4 -#define CLK_GATING_CTRL_TYPE REG_TYPE_RW -#define CLK_GATING_CTRL_DEFAULT 0xffffffff - /*[field] CLK_GATING_CTRL*/ - #define CLK_GATING_CTRL_CLK_GATING_CTRL - #define CLK_GATING_CTRL_CLK_GATING_CTRL_OFFSET 0 - #define CLK_GATING_CTRL_CLK_GATING_CTRL_LEN 32 - #define CLK_GATING_CTRL_CLK_GATING_CTRL_DEFAULT 0xffffffff - -struct clk_gating_ctrl { - a_uint32_t clk_gating_ctrl:32; -}; - -union clk_gating_ctrl_u { - a_uint32_t val; - struct clk_gating_ctrl bf; -}; - -/*[register] PORT_MUX_CTRL*/ -#define PORT_MUX_CTRL -#define PORT_MUX_CTRL_ADDRESS 0x10 -#define PORT_MUX_CTRL_NUM 1 -#define PORT_MUX_CTRL_INC 0x4 -#define PORT_MUX_CTRL_TYPE REG_TYPE_RW -#define PORT_MUX_CTRL_DEFAULT 0x0 - /*[field] PORT4_PCS_SEL*/ - #define PORT_MUX_CTRL_PORT4_PCS_SEL - #define PORT_MUX_CTRL_PORT4_PCS_SEL_OFFSET 0 - #define PORT_MUX_CTRL_PORT4_PCS_SEL_LEN 1 - #define PORT_MUX_CTRL_PORT4_PCS_SEL_DEFAULT 0x0 - /*[field] PORT5_PCS_SEL*/ - #define PORT_MUX_CTRL_PORT5_PCS_SEL - #define PORT_MUX_CTRL_PORT5_PCS_SEL_OFFSET 1 - #define PORT_MUX_CTRL_PORT5_PCS_SEL_LEN 2 - #define PORT_MUX_CTRL_PORT5_PCS_SEL_DEFAULT 0x0 - /*[field] PORT5_GMAC_SEL*/ - #define PORT_MUX_CTRL_PORT5_GMAC_SEL - #define PORT_MUX_CTRL_PORT5_GMAC_SEL_OFFSET 3 - #define PORT_MUX_CTRL_PORT5_GMAC_SEL_LEN 1 - #define PORT_MUX_CTRL_PORT5_GMAC_SEL_DEFAULT 0x0 - /*[field] PORT6_PCS_SEL*/ - #define PORT_MUX_CTRL_PORT6_PCS_SEL - #define PORT_MUX_CTRL_PORT6_PCS_SEL_OFFSET 4 - #define PORT_MUX_CTRL_PORT6_PCS_SEL_LEN 1 - #define PORT_MUX_CTRL_PORT6_PCS_SEL_DEFAULT 0x0 - /*[field] PORT6_GMAC_SEL*/ - #define PORT_MUX_CTRL_PORT6_GMAC_SEL - #define PORT_MUX_CTRL_PORT6_GMAC_SEL_OFFSET 5 - #define PORT_MUX_CTRL_PORT6_GMAC_SEL_LEN 1 - #define PORT_MUX_CTRL_PORT6_GMAC_SEL_DEFAULT 0x0 - -struct port_mux_ctrl { - a_uint32_t port4_pcs_sel:1; - a_uint32_t port5_pcs_sel:2; - a_uint32_t port5_gmac_sel:1; - a_uint32_t port6_pcs_sel:1; - a_uint32_t port6_gmac_sel:1; - a_uint32_t _reserved0:26; -}; - -union port_mux_ctrl_u { - a_uint32_t val; - struct port_mux_ctrl bf; -}; -struct cppe_port_mux_ctrl { - a_uint32_t port3_pcs_sel:2; - a_uint32_t port4_pcs_sel:2; - a_uint32_t port5_pcs_sel:2; - a_uint32_t port5_gmac_sel:1; - a_uint32_t pcs0_ch4_sel:1; - a_uint32_t pcs0_ch0_sel:1; - a_uint32_t _reserved0:23; -}; - -union cppe_port_mux_ctrl_u { - a_uint32_t val; - struct cppe_port_mux_ctrl bf; -}; - -/*[register] MODULE_INI_DONE_INT*/ -#define MODULE_INI_DONE_INT -#define MODULE_INI_DONE_INT_ADDRESS 0x20 -#define MODULE_INI_DONE_INT_NUM 1 -#define MODULE_INI_DONE_INT_INC 0x4 -#define MODULE_INI_DONE_INT_TYPE REG_TYPE_RW -#define MODULE_INI_DONE_INT_DEFAULT 0x0 - /*[field] L3_INI_DONE_INT*/ - #define MODULE_INI_DONE_INT_L3_INI_DONE_INT - #define MODULE_INI_DONE_INT_L3_INI_DONE_INT_OFFSET 0 - #define MODULE_INI_DONE_INT_L3_INI_DONE_INT_LEN 1 - #define MODULE_INI_DONE_INT_L3_INI_DONE_INT_DEFAULT 0x0 - /*[field] ACL_INI_DONE_INT*/ - #define MODULE_INI_DONE_INT_ACL_INI_DONE_INT - #define MODULE_INI_DONE_INT_ACL_INI_DONE_INT_OFFSET 1 - #define MODULE_INI_DONE_INT_ACL_INI_DONE_INT_LEN 1 - #define MODULE_INI_DONE_INT_ACL_INI_DONE_INT_DEFAULT 0x0 - /*[field] L2_INI_DONE_INT*/ - #define MODULE_INI_DONE_INT_L2_INI_DONE_INT - #define MODULE_INI_DONE_INT_L2_INI_DONE_INT_OFFSET 2 - #define MODULE_INI_DONE_INT_L2_INI_DONE_INT_LEN 1 - #define MODULE_INI_DONE_INT_L2_INI_DONE_INT_DEFAULT 0x0 - /*[field] ING_RATE_INI_DONE_INT*/ - #define MODULE_INI_DONE_INT_ING_RATE_INI_DONE_INT - #define MODULE_INI_DONE_INT_ING_RATE_INI_DONE_INT_OFFSET 3 - #define MODULE_INI_DONE_INT_ING_RATE_INI_DONE_INT_LEN 1 - #define MODULE_INI_DONE_INT_ING_RATE_INI_DONE_INT_DEFAULT 0x0 - /*[field] BM_INI_DONE_INT*/ - #define MODULE_INI_DONE_INT_BM_INI_DONE_INT - #define MODULE_INI_DONE_INT_BM_INI_DONE_INT_OFFSET 4 - #define MODULE_INI_DONE_INT_BM_INI_DONE_INT_LEN 1 - #define MODULE_INI_DONE_INT_BM_INI_DONE_INT_DEFAULT 0x0 - /*[field] TM_INI_DONE_INT*/ - #define MODULE_INI_DONE_INT_TM_INI_DONE_INT - #define MODULE_INI_DONE_INT_TM_INI_DONE_INT_OFFSET 5 - #define MODULE_INI_DONE_INT_TM_INI_DONE_INT_LEN 1 - #define MODULE_INI_DONE_INT_TM_INI_DONE_INT_DEFAULT 0x0 - /*[field] QM_INI_DONE_INT*/ - #define MODULE_INI_DONE_INT_QM_INI_DONE_INT - #define MODULE_INI_DONE_INT_QM_INI_DONE_INT_OFFSET 6 - #define MODULE_INI_DONE_INT_QM_INI_DONE_INT_LEN 1 - #define MODULE_INI_DONE_INT_QM_INI_DONE_INT_DEFAULT 0x0 - /*[field] IV_INI_DONE_INT*/ - #define MODULE_INI_DONE_INT_IV_INI_DONE_INT - #define MODULE_INI_DONE_INT_IV_INI_DONE_INT_OFFSET 7 - #define MODULE_INI_DONE_INT_IV_INI_DONE_INT_LEN 1 - #define MODULE_INI_DONE_INT_IV_INI_DONE_INT_DEFAULT 0x0 - /*[field] PTX_INI_DONE_INT*/ - #define MODULE_INI_DONE_INT_PTX_INI_DONE_INT - #define MODULE_INI_DONE_INT_PTX_INI_DONE_INT_OFFSET 8 - #define MODULE_INI_DONE_INT_PTX_INI_DONE_INT_LEN 1 - #define MODULE_INI_DONE_INT_PTX_INI_DONE_INT_DEFAULT 0x0 - -struct module_ini_done_int { - a_uint32_t l3_ini_done_int:1; - a_uint32_t acl_ini_done_int:1; - a_uint32_t l2_ini_done_int:1; - a_uint32_t ing_rate_ini_done_int:1; - a_uint32_t bm_ini_done_int:1; - a_uint32_t tm_ini_done_int:1; - a_uint32_t qm_ini_done_int:1; - a_uint32_t iv_ini_done_int:1; - a_uint32_t ptx_ini_done_int:1; - a_uint32_t _reserved0:23; -}; - -union module_ini_done_int_u { - a_uint32_t val; - struct module_ini_done_int bf; -}; - -/*[register] MODULE_CPU_DONE_INT*/ -#define MODULE_CPU_DONE_INT -#define MODULE_CPU_DONE_INT_ADDRESS 0x24 -#define MODULE_CPU_DONE_INT_NUM 1 -#define MODULE_CPU_DONE_INT_INC 0x4 -#define MODULE_CPU_DONE_INT_TYPE REG_TYPE_RW -#define MODULE_CPU_DONE_INT_DEFAULT 0x0 - /*[field] QM_CPU_OP_DONE_INT*/ - #define MODULE_CPU_DONE_INT_QM_CPU_OP_DONE_INT - #define MODULE_CPU_DONE_INT_QM_CPU_OP_DONE_INT_OFFSET 0 - #define MODULE_CPU_DONE_INT_QM_CPU_OP_DONE_INT_LEN 1 - #define MODULE_CPU_DONE_INT_QM_CPU_OP_DONE_INT_DEFAULT 0x0 - /*[field] L2_FDB_RD_RESULT_VLD_INT*/ - #define MODULE_CPU_DONE_INT_L2_FDB_RD_RESULT_VLD_INT - #define MODULE_CPU_DONE_INT_L2_FDB_RD_RESULT_VLD_INT_OFFSET 1 - #define MODULE_CPU_DONE_INT_L2_FDB_RD_RESULT_VLD_INT_LEN 1 - #define MODULE_CPU_DONE_INT_L2_FDB_RD_RESULT_VLD_INT_DEFAULT 0x0 - /*[field] L2_FDB_WR_RESULT_VLD_INT*/ - #define MODULE_CPU_DONE_INT_L2_FDB_WR_RESULT_VLD_INT - #define MODULE_CPU_DONE_INT_L2_FDB_WR_RESULT_VLD_INT_OFFSET 2 - #define MODULE_CPU_DONE_INT_L2_FDB_WR_RESULT_VLD_INT_LEN 1 - #define MODULE_CPU_DONE_INT_L2_FDB_WR_RESULT_VLD_INT_DEFAULT 0x0 - /*[field] L2_FDB_RD_CMD_OVERFLOW_INT*/ - #define MODULE_CPU_DONE_INT_L2_FDB_RD_CMD_OVERFLOW_INT - #define MODULE_CPU_DONE_INT_L2_FDB_RD_CMD_OVERFLOW_INT_OFFSET 3 - #define MODULE_CPU_DONE_INT_L2_FDB_RD_CMD_OVERFLOW_INT_LEN 1 - #define MODULE_CPU_DONE_INT_L2_FDB_RD_CMD_OVERFLOW_INT_DEFAULT 0x0 - /*[field] L2_FDB_WR_CMD_OVERFLOW_INT*/ - #define MODULE_CPU_DONE_INT_L2_FDB_WR_CMD_OVERFLOW_INT - #define MODULE_CPU_DONE_INT_L2_FDB_WR_CMD_OVERFLOW_INT_OFFSET 4 - #define MODULE_CPU_DONE_INT_L2_FDB_WR_CMD_OVERFLOW_INT_LEN 1 - #define MODULE_CPU_DONE_INT_L2_FDB_WR_CMD_OVERFLOW_INT_DEFAULT 0x0 - /*[field] L3_HOST_WR_CMD_OVERFLOW_INT*/ - #define MODULE_CPU_DONE_INT_L3_HOST_WR_CMD_OVERFLOW_INT - #define MODULE_CPU_DONE_INT_L3_HOST_WR_CMD_OVERFLOW_INT_OFFSET 8 - #define MODULE_CPU_DONE_INT_L3_HOST_WR_CMD_OVERFLOW_INT_LEN 1 - #define MODULE_CPU_DONE_INT_L3_HOST_WR_CMD_OVERFLOW_INT_DEFAULT 0x0 - /*[field] L3_HOST_RD_CMD_OVERFLOW_INT*/ - #define MODULE_CPU_DONE_INT_L3_HOST_RD_CMD_OVERFLOW_INT - #define MODULE_CPU_DONE_INT_L3_HOST_RD_CMD_OVERFLOW_INT_OFFSET 9 - #define MODULE_CPU_DONE_INT_L3_HOST_RD_CMD_OVERFLOW_INT_LEN 1 - #define MODULE_CPU_DONE_INT_L3_HOST_RD_CMD_OVERFLOW_INT_DEFAULT 0x0 - /*[field] L3_HOST_WR_RESULT_VLD_INT*/ - #define MODULE_CPU_DONE_INT_L3_HOST_WR_RESULT_VLD_INT - #define MODULE_CPU_DONE_INT_L3_HOST_WR_RESULT_VLD_INT_OFFSET 10 - #define MODULE_CPU_DONE_INT_L3_HOST_WR_RESULT_VLD_INT_LEN 1 - #define MODULE_CPU_DONE_INT_L3_HOST_WR_RESULT_VLD_INT_DEFAULT 0x0 - /*[field] L3_HOST_RD_RESULT_VLD_INT*/ - #define MODULE_CPU_DONE_INT_L3_HOST_RD_RESULT_VLD_INT - #define MODULE_CPU_DONE_INT_L3_HOST_RD_RESULT_VLD_INT_OFFSET 11 - #define MODULE_CPU_DONE_INT_L3_HOST_RD_RESULT_VLD_INT_LEN 1 - #define MODULE_CPU_DONE_INT_L3_HOST_RD_RESULT_VLD_INT_DEFAULT 0x0 - /*[field] L3_FLOW_WR_CMD_OVERFLOW_INT*/ - #define MODULE_CPU_DONE_INT_L3_FLOW_WR_CMD_OVERFLOW_INT - #define MODULE_CPU_DONE_INT_L3_FLOW_WR_CMD_OVERFLOW_INT_OFFSET 12 - #define MODULE_CPU_DONE_INT_L3_FLOW_WR_CMD_OVERFLOW_INT_LEN 1 - #define MODULE_CPU_DONE_INT_L3_FLOW_WR_CMD_OVERFLOW_INT_DEFAULT 0x0 - /*[field] L3_FLOW_RD_CMD_OVERFLOW_INT*/ - #define MODULE_CPU_DONE_INT_L3_FLOW_RD_CMD_OVERFLOW_INT - #define MODULE_CPU_DONE_INT_L3_FLOW_RD_CMD_OVERFLOW_INT_OFFSET 13 - #define MODULE_CPU_DONE_INT_L3_FLOW_RD_CMD_OVERFLOW_INT_LEN 1 - #define MODULE_CPU_DONE_INT_L3_FLOW_RD_CMD_OVERFLOW_INT_DEFAULT 0x0 - /*[field] L3_FLOW_WR_RESULT_VLD_INT*/ - #define MODULE_CPU_DONE_INT_L3_FLOW_WR_RESULT_VLD_INT - #define MODULE_CPU_DONE_INT_L3_FLOW_WR_RESULT_VLD_INT_OFFSET 14 - #define MODULE_CPU_DONE_INT_L3_FLOW_WR_RESULT_VLD_INT_LEN 1 - #define MODULE_CPU_DONE_INT_L3_FLOW_WR_RESULT_VLD_INT_DEFAULT 0x0 - /*[field] L3_FLOW_RD_RESULT_VLD_INT*/ - #define MODULE_CPU_DONE_INT_L3_FLOW_RD_RESULT_VLD_INT - #define MODULE_CPU_DONE_INT_L3_FLOW_RD_RESULT_VLD_INT_OFFSET 15 - #define MODULE_CPU_DONE_INT_L3_FLOW_RD_RESULT_VLD_INT_LEN 1 - #define MODULE_CPU_DONE_INT_L3_FLOW_RD_RESULT_VLD_INT_DEFAULT 0x0 - -struct module_cpu_done_int { - a_uint32_t qm_cpu_op_done_int:1; - a_uint32_t l2_fdb_rd_result_vld_int:1; - a_uint32_t l2_fdb_wr_result_vld_int:1; - a_uint32_t l2_fdb_rd_cmd_overflow_int:1; - a_uint32_t l2_fdb_wr_cmd_overflow_int:1; - a_uint32_t _reserved0:3; - a_uint32_t l3_host_wr_cmd_overflow_int:1; - a_uint32_t l3_host_rd_cmd_overflow_int:1; - a_uint32_t l3_host_wr_result_vld_int:1; - a_uint32_t l3_host_rd_result_vld_int:1; - a_uint32_t l3_flow_wr_cmd_overflow_int:1; - a_uint32_t l3_flow_rd_cmd_overflow_int:1; - a_uint32_t l3_flow_wr_result_vld_int:1; - a_uint32_t l3_flow_rd_result_vld_int:1; - a_uint32_t _reserved1:16; -}; - -union module_cpu_done_int_u { - a_uint32_t val; - struct module_cpu_done_int bf; -}; - -/*[register] PORT_LINK_INT*/ -#define PORT_LINK_INT -#define PORT_LINK_INT_ADDRESS 0x28 -#define PORT_LINK_INT_NUM 1 -#define PORT_LINK_INT_INC 0x4 -#define PORT_LINK_INT_TYPE REG_TYPE_RW -#define PORT_LINK_INT_DEFAULT 0x0 - /*[field] PORT1_LINK_CHG_INT*/ - #define PORT_LINK_INT_PORT1_LINK_CHG_INT - #define PORT_LINK_INT_PORT1_LINK_CHG_INT_OFFSET 0 - #define PORT_LINK_INT_PORT1_LINK_CHG_INT_LEN 1 - #define PORT_LINK_INT_PORT1_LINK_CHG_INT_DEFAULT 0x0 - /*[field] PORT2_LINK_CHG_INT*/ - #define PORT_LINK_INT_PORT2_LINK_CHG_INT - #define PORT_LINK_INT_PORT2_LINK_CHG_INT_OFFSET 1 - #define PORT_LINK_INT_PORT2_LINK_CHG_INT_LEN 1 - #define PORT_LINK_INT_PORT2_LINK_CHG_INT_DEFAULT 0x0 - /*[field] PORT3_LINK_CHG_INT*/ - #define PORT_LINK_INT_PORT3_LINK_CHG_INT - #define PORT_LINK_INT_PORT3_LINK_CHG_INT_OFFSET 2 - #define PORT_LINK_INT_PORT3_LINK_CHG_INT_LEN 1 - #define PORT_LINK_INT_PORT3_LINK_CHG_INT_DEFAULT 0x0 - /*[field] PORT4_LINK_CHG_INT*/ - #define PORT_LINK_INT_PORT4_LINK_CHG_INT - #define PORT_LINK_INT_PORT4_LINK_CHG_INT_OFFSET 3 - #define PORT_LINK_INT_PORT4_LINK_CHG_INT_LEN 1 - #define PORT_LINK_INT_PORT4_LINK_CHG_INT_DEFAULT 0x0 - /*[field] PORT5_0_LINK_CHG_INT*/ - #define PORT_LINK_INT_PORT5_0_LINK_CHG_INT - #define PORT_LINK_INT_PORT5_0_LINK_CHG_INT_OFFSET 4 - #define PORT_LINK_INT_PORT5_0_LINK_CHG_INT_LEN 1 - #define PORT_LINK_INT_PORT5_0_LINK_CHG_INT_DEFAULT 0x0 - /*[field] PORT5_1_LINK_CHG_INT*/ - #define PORT_LINK_INT_PORT5_1_LINK_CHG_INT - #define PORT_LINK_INT_PORT5_1_LINK_CHG_INT_OFFSET 5 - #define PORT_LINK_INT_PORT5_1_LINK_CHG_INT_LEN 1 - #define PORT_LINK_INT_PORT5_1_LINK_CHG_INT_DEFAULT 0x0 - /*[field] PORT6_LINK_CHG_INT*/ - #define PORT_LINK_INT_PORT6_LINK_CHG_INT - #define PORT_LINK_INT_PORT6_LINK_CHG_INT_OFFSET 6 - #define PORT_LINK_INT_PORT6_LINK_CHG_INT_LEN 1 - #define PORT_LINK_INT_PORT6_LINK_CHG_INT_DEFAULT 0x0 - /*[field] XGMAC0_AN_DONE_INT*/ - #define PORT_LINK_INT_XGMAC0_AN_DONE_INT - #define PORT_LINK_INT_XGMAC0_AN_DONE_INT_OFFSET 8 - #define PORT_LINK_INT_XGMAC0_AN_DONE_INT_LEN 1 - #define PORT_LINK_INT_XGMAC0_AN_DONE_INT_DEFAULT 0x0 - /*[field] XGMAC1_AN_DONE_INT*/ - #define PORT_LINK_INT_XGMAC1_AN_DONE_INT - #define PORT_LINK_INT_XGMAC1_AN_DONE_INT_OFFSET 9 - #define PORT_LINK_INT_XGMAC1_AN_DONE_INT_LEN 1 - #define PORT_LINK_INT_XGMAC1_AN_DONE_INT_DEFAULT 0x0 - -struct port_link_int { - a_uint32_t port1_link_chg_int:1; - a_uint32_t port2_link_chg_int:1; - a_uint32_t port3_link_chg_int:1; - a_uint32_t port4_link_chg_int:1; - a_uint32_t port5_0_link_chg_int:1; - a_uint32_t port5_1_link_chg_int:1; - a_uint32_t port6_link_chg_int:1; - a_uint32_t _reserved0:1; - a_uint32_t xgmac0_an_done_int:1; - a_uint32_t xgmac1_an_done_int:1; - a_uint32_t _reserved1:22; -}; - -union port_link_int_u { - a_uint32_t val; - struct port_link_int bf; -}; - -/*[register] MODULE_INI_DONE_INT_MASK*/ -#define MODULE_INI_DONE_INT_MASK -#define MODULE_INI_DONE_INT_MASK_ADDRESS 0x30 -#define MODULE_INI_DONE_INT_MASK_NUM 1 -#define MODULE_INI_DONE_INT_MASK_INC 0x4 -#define MODULE_INI_DONE_INT_MASK_TYPE REG_TYPE_RW -#define MODULE_INI_DONE_INT_MASK_DEFAULT 0x1ff - /*[field] L3_INI_DONE_INT_MASK*/ - #define MODULE_INI_DONE_INT_MASK_L3_INI_DONE_INT_MASK - #define MODULE_INI_DONE_INT_MASK_L3_INI_DONE_INT_MASK_OFFSET 0 - #define MODULE_INI_DONE_INT_MASK_L3_INI_DONE_INT_MASK_LEN 1 - #define MODULE_INI_DONE_INT_MASK_L3_INI_DONE_INT_MASK_DEFAULT 0x1 - /*[field] ACL_INI_DONE_INT_MASK*/ - #define MODULE_INI_DONE_INT_MASK_ACL_INI_DONE_INT_MASK - #define MODULE_INI_DONE_INT_MASK_ACL_INI_DONE_INT_MASK_OFFSET 1 - #define MODULE_INI_DONE_INT_MASK_ACL_INI_DONE_INT_MASK_LEN 1 - #define MODULE_INI_DONE_INT_MASK_ACL_INI_DONE_INT_MASK_DEFAULT 0x1 - /*[field] L2_INI_DONE_INT_MASK*/ - #define MODULE_INI_DONE_INT_MASK_L2_INI_DONE_INT_MASK - #define MODULE_INI_DONE_INT_MASK_L2_INI_DONE_INT_MASK_OFFSET 2 - #define MODULE_INI_DONE_INT_MASK_L2_INI_DONE_INT_MASK_LEN 1 - #define MODULE_INI_DONE_INT_MASK_L2_INI_DONE_INT_MASK_DEFAULT 0x1 - /*[field] ING_RATE_INI_DONE_INT_MASK*/ - #define MODULE_INI_DONE_INT_MASK_ING_RATE_INI_DONE_INT_MASK - #define MODULE_INI_DONE_INT_MASK_ING_RATE_INI_DONE_INT_MASK_OFFSET 3 - #define MODULE_INI_DONE_INT_MASK_ING_RATE_INI_DONE_INT_MASK_LEN 1 - #define MODULE_INI_DONE_INT_MASK_ING_RATE_INI_DONE_INT_MASK_DEFAULT 0x1 - /*[field] BM_INI_DONE_INT_MASK*/ - #define MODULE_INI_DONE_INT_MASK_BM_INI_DONE_INT_MASK - #define MODULE_INI_DONE_INT_MASK_BM_INI_DONE_INT_MASK_OFFSET 4 - #define MODULE_INI_DONE_INT_MASK_BM_INI_DONE_INT_MASK_LEN 1 - #define MODULE_INI_DONE_INT_MASK_BM_INI_DONE_INT_MASK_DEFAULT 0x1 - /*[field] TM_INI_DONE_INT_MASK*/ - #define MODULE_INI_DONE_INT_MASK_TM_INI_DONE_INT_MASK - #define MODULE_INI_DONE_INT_MASK_TM_INI_DONE_INT_MASK_OFFSET 5 - #define MODULE_INI_DONE_INT_MASK_TM_INI_DONE_INT_MASK_LEN 1 - #define MODULE_INI_DONE_INT_MASK_TM_INI_DONE_INT_MASK_DEFAULT 0x1 - /*[field] QM_INI_DONE_INT_MASK*/ - #define MODULE_INI_DONE_INT_MASK_QM_INI_DONE_INT_MASK - #define MODULE_INI_DONE_INT_MASK_QM_INI_DONE_INT_MASK_OFFSET 6 - #define MODULE_INI_DONE_INT_MASK_QM_INI_DONE_INT_MASK_LEN 1 - #define MODULE_INI_DONE_INT_MASK_QM_INI_DONE_INT_MASK_DEFAULT 0x1 - /*[field] IV_INI_DONE_INT_MASK*/ - #define MODULE_INI_DONE_INT_MASK_IV_INI_DONE_INT_MASK - #define MODULE_INI_DONE_INT_MASK_IV_INI_DONE_INT_MASK_OFFSET 7 - #define MODULE_INI_DONE_INT_MASK_IV_INI_DONE_INT_MASK_LEN 1 - #define MODULE_INI_DONE_INT_MASK_IV_INI_DONE_INT_MASK_DEFAULT 0x1 - /*[field] PTX_INI_DONE_INT_MASK*/ - #define MODULE_INI_DONE_INT_MASK_PTX_INI_DONE_INT_MASK - #define MODULE_INI_DONE_INT_MASK_PTX_INI_DONE_INT_MASK_OFFSET 8 - #define MODULE_INI_DONE_INT_MASK_PTX_INI_DONE_INT_MASK_LEN 1 - #define MODULE_INI_DONE_INT_MASK_PTX_INI_DONE_INT_MASK_DEFAULT 0x1 - -struct module_ini_done_int_mask { - a_uint32_t l3_ini_done_int_mask:1; - a_uint32_t acl_ini_done_int_mask:1; - a_uint32_t l2_ini_done_int_mask:1; - a_uint32_t ing_rate_ini_done_int_mask:1; - a_uint32_t bm_ini_done_int_mask:1; - a_uint32_t tm_ini_done_int_mask:1; - a_uint32_t qm_ini_done_int_mask:1; - a_uint32_t iv_ini_done_int_mask:1; - a_uint32_t ptx_ini_done_int_mask:1; - a_uint32_t _reserved0:23; -}; - -union module_ini_done_int_mask_u { - a_uint32_t val; - struct module_ini_done_int_mask bf; -}; - -/*[register] MODULE_CPU_DONE_INT_MASK*/ -#define MODULE_CPU_DONE_INT_MASK -#define MODULE_CPU_DONE_INT_MASK_ADDRESS 0x34 -#define MODULE_CPU_DONE_INT_MASK_NUM 1 -#define MODULE_CPU_DONE_INT_MASK_INC 0x4 -#define MODULE_CPU_DONE_INT_MASK_TYPE REG_TYPE_RW -#define MODULE_CPU_DONE_INT_MASK_DEFAULT 0xff1f - /*[field] QM_CPU_OP_DONE_INT_MASK*/ - #define MODULE_CPU_DONE_INT_MASK_QM_CPU_OP_DONE_INT_MASK - #define MODULE_CPU_DONE_INT_MASK_QM_CPU_OP_DONE_INT_MASK_OFFSET 0 - #define MODULE_CPU_DONE_INT_MASK_QM_CPU_OP_DONE_INT_MASK_LEN 1 - #define MODULE_CPU_DONE_INT_MASK_QM_CPU_OP_DONE_INT_MASK_DEFAULT 0x1 - /*[field] L2_FDB_RD_RESULT_VLD_INT_MASK*/ - #define MODULE_CPU_DONE_INT_MASK_L2_FDB_RD_RESULT_VLD_INT_MASK - #define MODULE_CPU_DONE_INT_MASK_L2_FDB_RD_RESULT_VLD_INT_MASK_OFFSET 1 - #define MODULE_CPU_DONE_INT_MASK_L2_FDB_RD_RESULT_VLD_INT_MASK_LEN 1 - #define MODULE_CPU_DONE_INT_MASK_L2_FDB_RD_RESULT_VLD_INT_MASK_DEFAULT 0x1 - /*[field] L2_FDB_WR_RESULT_VLD_INT_MASK*/ - #define MODULE_CPU_DONE_INT_MASK_L2_FDB_WR_RESULT_VLD_INT_MASK - #define MODULE_CPU_DONE_INT_MASK_L2_FDB_WR_RESULT_VLD_INT_MASK_OFFSET 2 - #define MODULE_CPU_DONE_INT_MASK_L2_FDB_WR_RESULT_VLD_INT_MASK_LEN 1 - #define MODULE_CPU_DONE_INT_MASK_L2_FDB_WR_RESULT_VLD_INT_MASK_DEFAULT 0x1 - /*[field] L2_FDB_RD_CMD_OVERFLOW_INT_MASK*/ - #define MODULE_CPU_DONE_INT_MASK_L2_FDB_RD_CMD_OVERFLOW_INT_MASK - #define MODULE_CPU_DONE_INT_MASK_L2_FDB_RD_CMD_OVERFLOW_INT_MASK_OFFSET 3 - #define MODULE_CPU_DONE_INT_MASK_L2_FDB_RD_CMD_OVERFLOW_INT_MASK_LEN 1 - #define MODULE_CPU_DONE_INT_MASK_L2_FDB_RD_CMD_OVERFLOW_INT_MASK_DEFAULT 0x1 - /*[field] L2_FDB_WR_CMD_OVERFLOW_INT_MASK*/ - #define MODULE_CPU_DONE_INT_MASK_L2_FDB_WR_CMD_OVERFLOW_INT_MASK - #define MODULE_CPU_DONE_INT_MASK_L2_FDB_WR_CMD_OVERFLOW_INT_MASK_OFFSET 4 - #define MODULE_CPU_DONE_INT_MASK_L2_FDB_WR_CMD_OVERFLOW_INT_MASK_LEN 1 - #define MODULE_CPU_DONE_INT_MASK_L2_FDB_WR_CMD_OVERFLOW_INT_MASK_DEFAULT 0x1 - /*[field] L3_HOST_WR_CMD_OVERFLOW_INT_MASK*/ - #define MODULE_CPU_DONE_INT_MASK_L3_HOST_WR_CMD_OVERFLOW_INT_MASK - #define MODULE_CPU_DONE_INT_MASK_L3_HOST_WR_CMD_OVERFLOW_INT_MASK_OFFSET 8 - #define MODULE_CPU_DONE_INT_MASK_L3_HOST_WR_CMD_OVERFLOW_INT_MASK_LEN 1 - #define MODULE_CPU_DONE_INT_MASK_L3_HOST_WR_CMD_OVERFLOW_INT_MASK_DEFAULT 0x1 - /*[field] L3_HOST_RD_CMD_OVERFLOW_INT_MASK*/ - #define MODULE_CPU_DONE_INT_MASK_L3_HOST_RD_CMD_OVERFLOW_INT_MASK - #define MODULE_CPU_DONE_INT_MASK_L3_HOST_RD_CMD_OVERFLOW_INT_MASK_OFFSET 9 - #define MODULE_CPU_DONE_INT_MASK_L3_HOST_RD_CMD_OVERFLOW_INT_MASK_LEN 1 - #define MODULE_CPU_DONE_INT_MASK_L3_HOST_RD_CMD_OVERFLOW_INT_MASK_DEFAULT 0x1 - /*[field] L3_HOST_WR_RESULT_VLD_INT_MASK*/ - #define MODULE_CPU_DONE_INT_MASK_L3_HOST_WR_RESULT_VLD_INT_MASK - #define MODULE_CPU_DONE_INT_MASK_L3_HOST_WR_RESULT_VLD_INT_MASK_OFFSET 10 - #define MODULE_CPU_DONE_INT_MASK_L3_HOST_WR_RESULT_VLD_INT_MASK_LEN 1 - #define MODULE_CPU_DONE_INT_MASK_L3_HOST_WR_RESULT_VLD_INT_MASK_DEFAULT 0x1 - /*[field] L3_HOST_RD_RESULT_VLD_INT_MASK*/ - #define MODULE_CPU_DONE_INT_MASK_L3_HOST_RD_RESULT_VLD_INT_MASK - #define MODULE_CPU_DONE_INT_MASK_L3_HOST_RD_RESULT_VLD_INT_MASK_OFFSET 11 - #define MODULE_CPU_DONE_INT_MASK_L3_HOST_RD_RESULT_VLD_INT_MASK_LEN 1 - #define MODULE_CPU_DONE_INT_MASK_L3_HOST_RD_RESULT_VLD_INT_MASK_DEFAULT 0x1 - /*[field] L3_FLOW_WR_CMD_OVERFLOW_INT_MASK*/ - #define MODULE_CPU_DONE_INT_MASK_L3_FLOW_WR_CMD_OVERFLOW_INT_MASK - #define MODULE_CPU_DONE_INT_MASK_L3_FLOW_WR_CMD_OVERFLOW_INT_MASK_OFFSET 12 - #define MODULE_CPU_DONE_INT_MASK_L3_FLOW_WR_CMD_OVERFLOW_INT_MASK_LEN 1 - #define MODULE_CPU_DONE_INT_MASK_L3_FLOW_WR_CMD_OVERFLOW_INT_MASK_DEFAULT 0x1 - /*[field] L3_FLOW_RD_CMD_OVERFLOW_INT_MASK*/ - #define MODULE_CPU_DONE_INT_MASK_L3_FLOW_RD_CMD_OVERFLOW_INT_MASK - #define MODULE_CPU_DONE_INT_MASK_L3_FLOW_RD_CMD_OVERFLOW_INT_MASK_OFFSET 13 - #define MODULE_CPU_DONE_INT_MASK_L3_FLOW_RD_CMD_OVERFLOW_INT_MASK_LEN 1 - #define MODULE_CPU_DONE_INT_MASK_L3_FLOW_RD_CMD_OVERFLOW_INT_MASK_DEFAULT 0x1 - /*[field] L3_FLOW_WR_RESULT_VLD_INT_MASK*/ - #define MODULE_CPU_DONE_INT_MASK_L3_FLOW_WR_RESULT_VLD_INT_MASK - #define MODULE_CPU_DONE_INT_MASK_L3_FLOW_WR_RESULT_VLD_INT_MASK_OFFSET 14 - #define MODULE_CPU_DONE_INT_MASK_L3_FLOW_WR_RESULT_VLD_INT_MASK_LEN 1 - #define MODULE_CPU_DONE_INT_MASK_L3_FLOW_WR_RESULT_VLD_INT_MASK_DEFAULT 0x1 - /*[field] L3_FLOW_RD_RESULT_VLD_INT_MASK*/ - #define MODULE_CPU_DONE_INT_MASK_L3_FLOW_RD_RESULT_VLD_INT_MASK - #define MODULE_CPU_DONE_INT_MASK_L3_FLOW_RD_RESULT_VLD_INT_MASK_OFFSET 15 - #define MODULE_CPU_DONE_INT_MASK_L3_FLOW_RD_RESULT_VLD_INT_MASK_LEN 1 - #define MODULE_CPU_DONE_INT_MASK_L3_FLOW_RD_RESULT_VLD_INT_MASK_DEFAULT 0x1 - -struct module_cpu_done_int_mask { - a_uint32_t qm_cpu_op_done_int_mask:1; - a_uint32_t l2_fdb_rd_result_vld_int_mask:1; - a_uint32_t l2_fdb_wr_result_vld_int_mask:1; - a_uint32_t l2_fdb_rd_cmd_overflow_int_mask:1; - a_uint32_t l2_fdb_wr_cmd_overflow_int_mask:1; - a_uint32_t _reserved0:3; - a_uint32_t l3_host_wr_cmd_overflow_int_mask:1; - a_uint32_t l3_host_rd_cmd_overflow_int_mask:1; - a_uint32_t l3_host_wr_result_vld_int_mask:1; - a_uint32_t l3_host_rd_result_vld_int_mask:1; - a_uint32_t l3_flow_wr_cmd_overflow_int_mask:1; - a_uint32_t l3_flow_rd_cmd_overflow_int_mask:1; - a_uint32_t l3_flow_wr_result_vld_int_mask:1; - a_uint32_t l3_flow_rd_result_vld_int_mask:1; - a_uint32_t _reserved1:16; -}; - -union module_cpu_done_int_mask_u { - a_uint32_t val; - struct module_cpu_done_int_mask bf; -}; - -/*[register] PORT_LINK_INT_MASK*/ -#define PORT_LINK_INT_MASK -#define PORT_LINK_INT_MASK_ADDRESS 0x38 -#define PORT_LINK_INT_MASK_NUM 1 -#define PORT_LINK_INT_MASK_INC 0x4 -#define PORT_LINK_INT_MASK_TYPE REG_TYPE_RW -#define PORT_LINK_INT_MASK_DEFAULT 0x37f - /*[field] PORT1_LINK_CHG_INT_MASK*/ - #define PORT_LINK_INT_MASK_PORT1_LINK_CHG_INT_MASK - #define PORT_LINK_INT_MASK_PORT1_LINK_CHG_INT_MASK_OFFSET 0 - #define PORT_LINK_INT_MASK_PORT1_LINK_CHG_INT_MASK_LEN 1 - #define PORT_LINK_INT_MASK_PORT1_LINK_CHG_INT_MASK_DEFAULT 0x1 - /*[field] PORT2_LINK_CHG_INT_MASK*/ - #define PORT_LINK_INT_MASK_PORT2_LINK_CHG_INT_MASK - #define PORT_LINK_INT_MASK_PORT2_LINK_CHG_INT_MASK_OFFSET 1 - #define PORT_LINK_INT_MASK_PORT2_LINK_CHG_INT_MASK_LEN 1 - #define PORT_LINK_INT_MASK_PORT2_LINK_CHG_INT_MASK_DEFAULT 0x1 - /*[field] PORT3_LINK_CHG_INT_MASK*/ - #define PORT_LINK_INT_MASK_PORT3_LINK_CHG_INT_MASK - #define PORT_LINK_INT_MASK_PORT3_LINK_CHG_INT_MASK_OFFSET 2 - #define PORT_LINK_INT_MASK_PORT3_LINK_CHG_INT_MASK_LEN 1 - #define PORT_LINK_INT_MASK_PORT3_LINK_CHG_INT_MASK_DEFAULT 0x1 - /*[field] PORT4_LINK_CHG_INT_MASK*/ - #define PORT_LINK_INT_MASK_PORT4_LINK_CHG_INT_MASK - #define PORT_LINK_INT_MASK_PORT4_LINK_CHG_INT_MASK_OFFSET 3 - #define PORT_LINK_INT_MASK_PORT4_LINK_CHG_INT_MASK_LEN 1 - #define PORT_LINK_INT_MASK_PORT4_LINK_CHG_INT_MASK_DEFAULT 0x1 - /*[field] PORT5_0_LINK_CHG_INT_MASK*/ - #define PORT_LINK_INT_MASK_PORT5_0_LINK_CHG_INT_MASK - #define PORT_LINK_INT_MASK_PORT5_0_LINK_CHG_INT_MASK_OFFSET 4 - #define PORT_LINK_INT_MASK_PORT5_0_LINK_CHG_INT_MASK_LEN 1 - #define PORT_LINK_INT_MASK_PORT5_0_LINK_CHG_INT_MASK_DEFAULT 0x1 - /*[field] PORT5_1_LINK_CHG_INT_MASK*/ - #define PORT_LINK_INT_MASK_PORT5_1_LINK_CHG_INT_MASK - #define PORT_LINK_INT_MASK_PORT5_1_LINK_CHG_INT_MASK_OFFSET 5 - #define PORT_LINK_INT_MASK_PORT5_1_LINK_CHG_INT_MASK_LEN 1 - #define PORT_LINK_INT_MASK_PORT5_1_LINK_CHG_INT_MASK_DEFAULT 0x1 - /*[field] PORT6_LINK_CHG_INT_MASK*/ - #define PORT_LINK_INT_MASK_PORT6_LINK_CHG_INT_MASK - #define PORT_LINK_INT_MASK_PORT6_LINK_CHG_INT_MASK_OFFSET 6 - #define PORT_LINK_INT_MASK_PORT6_LINK_CHG_INT_MASK_LEN 1 - #define PORT_LINK_INT_MASK_PORT6_LINK_CHG_INT_MASK_DEFAULT 0x1 - /*[field] XGMAC0_AN_DONE_INT_MASK*/ - #define PORT_LINK_INT_MASK_XGMAC0_AN_DONE_INT_MASK - #define PORT_LINK_INT_MASK_XGMAC0_AN_DONE_INT_MASK_OFFSET 8 - #define PORT_LINK_INT_MASK_XGMAC0_AN_DONE_INT_MASK_LEN 1 - #define PORT_LINK_INT_MASK_XGMAC0_AN_DONE_INT_MASK_DEFAULT 0x1 - /*[field] XGMAC1_AN_DONE_INT_MASK*/ - #define PORT_LINK_INT_MASK_XGMAC1_AN_DONE_INT_MASK - #define PORT_LINK_INT_MASK_XGMAC1_AN_DONE_INT_MASK_OFFSET 9 - #define PORT_LINK_INT_MASK_XGMAC1_AN_DONE_INT_MASK_LEN 1 - #define PORT_LINK_INT_MASK_XGMAC1_AN_DONE_INT_MASK_DEFAULT 0x1 - -struct port_link_int_mask { - a_uint32_t port1_link_chg_int_mask:1; - a_uint32_t port2_link_chg_int_mask:1; - a_uint32_t port3_link_chg_int_mask:1; - a_uint32_t port4_link_chg_int_mask:1; - a_uint32_t port5_0_link_chg_int_mask:1; - a_uint32_t port5_1_link_chg_int_mask:1; - a_uint32_t port6_link_chg_int_mask:1; - a_uint32_t _reserved0:1; - a_uint32_t xgmac0_an_done_int_mask:1; - a_uint32_t xgmac1_an_done_int_mask:1; - a_uint32_t _reserved1:22; -}; - -union port_link_int_mask_u { - a_uint32_t val; - struct port_link_int_mask bf; -}; - -/*[register] PORT_PHY_STATUS_0*/ -#define PORT_PHY_STATUS_0 -#define PORT_PHY_STATUS_0_ADDRESS 0x40 -#define PORT_PHY_STATUS_0_NUM 1 -#define PORT_PHY_STATUS_0_INC 0x4 -#define PORT_PHY_STATUS_0_TYPE REG_TYPE_RO -#define PORT_PHY_STATUS_0_DEFAULT 0x0 - /*[field] PORT1_PHY_STATUS*/ - #define PORT_PHY_STATUS_0_PORT1_PHY_STATUS - #define PORT_PHY_STATUS_0_PORT1_PHY_STATUS_OFFSET 0 - #define PORT_PHY_STATUS_0_PORT1_PHY_STATUS_LEN 8 - #define PORT_PHY_STATUS_0_PORT1_PHY_STATUS_DEFAULT 0x0 - /*[field] PORT2_PHY_STATUS*/ - #define PORT_PHY_STATUS_0_PORT2_PHY_STATUS - #define PORT_PHY_STATUS_0_PORT2_PHY_STATUS_OFFSET 8 - #define PORT_PHY_STATUS_0_PORT2_PHY_STATUS_LEN 8 - #define PORT_PHY_STATUS_0_PORT2_PHY_STATUS_DEFAULT 0x0 - /*[field] PORT3_PHY_STATUS*/ - #define PORT_PHY_STATUS_0_PORT3_PHY_STATUS - #define PORT_PHY_STATUS_0_PORT3_PHY_STATUS_OFFSET 16 - #define PORT_PHY_STATUS_0_PORT3_PHY_STATUS_LEN 8 - #define PORT_PHY_STATUS_0_PORT3_PHY_STATUS_DEFAULT 0x0 - /*[field] PORT4_PHY_STATUS*/ - #define PORT_PHY_STATUS_0_PORT4_PHY_STATUS - #define PORT_PHY_STATUS_0_PORT4_PHY_STATUS_OFFSET 24 - #define PORT_PHY_STATUS_0_PORT4_PHY_STATUS_LEN 8 - #define PORT_PHY_STATUS_0_PORT4_PHY_STATUS_DEFAULT 0x0 - -struct port_phy_status_0 { - a_uint32_t port1_phy_status:8; - a_uint32_t port2_phy_status:8; - a_uint32_t port3_phy_status:8; - a_uint32_t port4_phy_status:8; -}; - -union port_phy_status_0_u { - a_uint32_t val; - struct port_phy_status_0 bf; -}; - -/*[register] PORT_PHY_STATUS_1*/ -#define PORT_PHY_STATUS_1 -#define PORT_PHY_STATUS_1_ADDRESS 0x44 -#define PORT_PHY_STATUS_1_NUM 1 -#define PORT_PHY_STATUS_1_INC 0x4 -#define PORT_PHY_STATUS_1_TYPE REG_TYPE_RO -#define PORT_PHY_STATUS_1_DEFAULT 0x0 - /*[field] PORT5_0_PHY_STATUS*/ - #define PORT_PHY_STATUS_1_PORT5_0_PHY_STATUS - #define PORT_PHY_STATUS_1_PORT5_0_PHY_STATUS_OFFSET 0 - #define PORT_PHY_STATUS_1_PORT5_0_PHY_STATUS_LEN 8 - #define PORT_PHY_STATUS_1_PORT5_0_PHY_STATUS_DEFAULT 0x0 - /*[field] PORT5_1_PHY_STATUS*/ - #define PORT_PHY_STATUS_1_PORT5_1_PHY_STATUS - #define PORT_PHY_STATUS_1_PORT5_1_PHY_STATUS_OFFSET 8 - #define PORT_PHY_STATUS_1_PORT5_1_PHY_STATUS_LEN 8 - #define PORT_PHY_STATUS_1_PORT5_1_PHY_STATUS_DEFAULT 0x0 - /*[field] PORT6_PHY_STATUS*/ - #define PORT_PHY_STATUS_1_PORT6_PHY_STATUS - #define PORT_PHY_STATUS_1_PORT6_PHY_STATUS_OFFSET 16 - #define PORT_PHY_STATUS_1_PORT6_PHY_STATUS_LEN 8 - #define PORT_PHY_STATUS_1_PORT6_PHY_STATUS_DEFAULT 0x0 - -struct port_phy_status_1 { - a_uint32_t port5_0_phy_status:8; - a_uint32_t port5_1_phy_status:8; - a_uint32_t port6_phy_status:8; - a_uint32_t _reserved0:8; -}; - -union port_phy_status_1_u { - a_uint32_t val; - struct port_phy_status_1 bf; -}; - -/*[register] PORT1_STATUS*/ -#define PORT1_STATUS -#define PORT1_STATUS_ADDRESS 0x50 -#define PORT1_STATUS_NUM 1 -#define PORT1_STATUS_INC 0x4 -#define PORT1_STATUS_TYPE REG_TYPE_RO -#define PORT1_STATUS_DEFAULT 0x0 - /*[field] PORT1_STATUS*/ - #define PORT1_STATUS_PORT1_STATUS - #define PORT1_STATUS_PORT1_STATUS_OFFSET 0 - #define PORT1_STATUS_PORT1_STATUS_LEN 32 - #define PORT1_STATUS_PORT1_STATUS_DEFAULT 0x0 - -struct port1_status { - a_uint32_t port1_status:32; -}; - -union port1_status_u { - a_uint32_t val; - struct port1_status bf; -}; - -/*[register] PORT2_STATUS*/ -#define PORT2_STATUS -#define PORT2_STATUS_ADDRESS 0x54 -#define PORT2_STATUS_NUM 1 -#define PORT2_STATUS_INC 0x4 -#define PORT2_STATUS_TYPE REG_TYPE_RO -#define PORT2_STATUS_DEFAULT 0x0 - /*[field] PORT2_STATUS*/ - #define PORT2_STATUS_PORT2_STATUS - #define PORT2_STATUS_PORT2_STATUS_OFFSET 0 - #define PORT2_STATUS_PORT2_STATUS_LEN 32 - #define PORT2_STATUS_PORT2_STATUS_DEFAULT 0x0 - -struct port2_status { - a_uint32_t port2_status:32; -}; - -union port2_status_u { - a_uint32_t val; - struct port2_status bf; -}; - -/*[register] PORT3_STATUS*/ -#define PORT3_STATUS -#define PORT3_STATUS_ADDRESS 0x58 -#define PORT3_STATUS_NUM 1 -#define PORT3_STATUS_INC 0x4 -#define PORT3_STATUS_TYPE REG_TYPE_RO -#define PORT3_STATUS_DEFAULT 0x0 - /*[field] PORT3_STATUS*/ - #define PORT3_STATUS_PORT3_STATUS - #define PORT3_STATUS_PORT3_STATUS_OFFSET 0 - #define PORT3_STATUS_PORT3_STATUS_LEN 32 - #define PORT3_STATUS_PORT3_STATUS_DEFAULT 0x0 - -struct port3_status { - a_uint32_t port3_status:32; -}; - -union port3_status_u { - a_uint32_t val; - struct port3_status bf; -}; - -/*[register] PORT4_STATUS*/ -#define PORT4_STATUS -#define PORT4_STATUS_ADDRESS 0x5c -#define PORT4_STATUS_NUM 1 -#define PORT4_STATUS_INC 0x4 -#define PORT4_STATUS_TYPE REG_TYPE_RO -#define PORT4_STATUS_DEFAULT 0x0 - /*[field] PORT4_STATUS*/ - #define PORT4_STATUS_PORT4_STATUS - #define PORT4_STATUS_PORT4_STATUS_OFFSET 0 - #define PORT4_STATUS_PORT4_STATUS_LEN 32 - #define PORT4_STATUS_PORT4_STATUS_DEFAULT 0x0 - -struct port4_status { - a_uint32_t port4_status:32; -}; - -union port4_status_u { - a_uint32_t val; - struct port4_status bf; -}; - -/*[register] PORT5_STATUS*/ -#define PORT5_STATUS -#define PORT5_STATUS_ADDRESS 0x60 -#define PORT5_STATUS_NUM 1 -#define PORT5_STATUS_INC 0x4 -#define PORT5_STATUS_TYPE REG_TYPE_RO -#define PORT5_STATUS_DEFAULT 0x0 - /*[field] PORT5_STATUS*/ - #define PORT5_STATUS_PORT5_STATUS - #define PORT5_STATUS_PORT5_STATUS_OFFSET 0 - #define PORT5_STATUS_PORT5_STATUS_LEN 8 - #define PORT5_STATUS_PORT5_STATUS_DEFAULT 0x0 - /*[field] PORT1_MAC_SPEED*/ - #define PORT5_STATUS_PORT1_MAC_SPEED - #define PORT5_STATUS_PORT1_MAC_SPEED_OFFSET 16 - #define PORT5_STATUS_PORT1_MAC_SPEED_LEN 2 - #define PORT5_STATUS_PORT1_MAC_SPEED_DEFAULT 0x0 - /*[field] PORT2_MAC_SPEED*/ - #define PORT5_STATUS_PORT2_MAC_SPEED - #define PORT5_STATUS_PORT2_MAC_SPEED_OFFSET 18 - #define PORT5_STATUS_PORT2_MAC_SPEED_LEN 2 - #define PORT5_STATUS_PORT2_MAC_SPEED_DEFAULT 0x0 - /*[field] PORT3_MAC_SPEED*/ - #define PORT5_STATUS_PORT3_MAC_SPEED - #define PORT5_STATUS_PORT3_MAC_SPEED_OFFSET 20 - #define PORT5_STATUS_PORT3_MAC_SPEED_LEN 2 - #define PORT5_STATUS_PORT3_MAC_SPEED_DEFAULT 0x0 - /*[field] PORT4_MAC_SPEED*/ - #define PORT5_STATUS_PORT4_MAC_SPEED - #define PORT5_STATUS_PORT4_MAC_SPEED_OFFSET 22 - #define PORT5_STATUS_PORT4_MAC_SPEED_LEN 2 - #define PORT5_STATUS_PORT4_MAC_SPEED_DEFAULT 0x0 - -struct port5_status { - a_uint32_t port5_status:8; - a_uint32_t _reserved0:8; - a_uint32_t port1_mac_speed:2; - a_uint32_t port2_mac_speed:2; - a_uint32_t port3_mac_speed:2; - a_uint32_t port4_mac_speed:2; - a_uint32_t _reserved1:8; -}; - -union port5_status_u { - a_uint32_t val; - struct port5_status bf; -}; - -/*[register] PORT6_STATUS*/ -#define PORT6_STATUS -#define PORT6_STATUS_ADDRESS 0x64 -#define PORT6_STATUS_NUM 1 -#define PORT6_STATUS_INC 0x4 -#define PORT6_STATUS_TYPE REG_TYPE_RO -#define PORT6_STATUS_DEFAULT 0x0 - /*[field] PORT6_STATUS*/ - #define PORT6_STATUS_PORT6_STATUS - #define PORT6_STATUS_PORT6_STATUS_OFFSET 0 - #define PORT6_STATUS_PORT6_STATUS_LEN 8 - #define PORT6_STATUS_PORT6_STATUS_DEFAULT 0x0 - -struct port6_status { - a_uint32_t port6_status:8; - a_uint32_t _reserved0:24; -}; - -union port6_status_u { - a_uint32_t val; - struct port6_status bf; -}; - -/*[register] RESERVED_REGS_0*/ -#define RESERVED_REGS_0 -#define RESERVED_REGS_0_ADDRESS 0x70 -#define RESERVED_REGS_0_NUM 1 -#define RESERVED_REGS_0_INC 0x4 -#define RESERVED_REGS_0_TYPE REG_TYPE_RW -#define RESERVED_REGS_0_DEFAULT 0x0 - /*[field] SPARE_REGS_0*/ - #define RESERVED_REGS_0_SPARE_REGS_0 - #define RESERVED_REGS_0_SPARE_REGS_0_OFFSET 0 - #define RESERVED_REGS_0_SPARE_REGS_0_LEN 32 - #define RESERVED_REGS_0_SPARE_REGS_0_DEFAULT 0x0 - -struct reserved_regs_0 { - a_uint32_t spare_regs_0:32; -}; - -union reserved_regs_0_u { - a_uint32_t val; - struct reserved_regs_0 bf; -}; - -/*[register] RESERVED_REGS_1*/ -#define RESERVED_REGS_1 -#define RESERVED_REGS_1_ADDRESS 0x74 -#define RESERVED_REGS_1_NUM 1 -#define RESERVED_REGS_1_INC 0x4 -#define RESERVED_REGS_1_TYPE REG_TYPE_RW -#define RESERVED_REGS_1_DEFAULT 0x0 - /*[field] SPARE_REGS_1*/ - #define RESERVED_REGS_1_SPARE_REGS_1 - #define RESERVED_REGS_1_SPARE_REGS_1_OFFSET 0 - #define RESERVED_REGS_1_SPARE_REGS_1_LEN 32 - #define RESERVED_REGS_1_SPARE_REGS_1_DEFAULT 0x0 - -struct reserved_regs_1 { - a_uint32_t spare_regs_1:32; -}; - -union reserved_regs_1_u { - a_uint32_t val; - struct reserved_regs_1 bf; -}; - -/*[register] RESERVED_REGS_2*/ -#define RESERVED_REGS_2 -#define RESERVED_REGS_2_ADDRESS 0x78 -#define RESERVED_REGS_2_NUM 1 -#define RESERVED_REGS_2_INC 0x4 -#define RESERVED_REGS_2_TYPE REG_TYPE_RW -#define RESERVED_REGS_2_DEFAULT 0x0 - /*[field] SPARE_REGS_2*/ - #define RESERVED_REGS_2_SPARE_REGS_2 - #define RESERVED_REGS_2_SPARE_REGS_2_OFFSET 0 - #define RESERVED_REGS_2_SPARE_REGS_2_LEN 32 - #define RESERVED_REGS_2_SPARE_REGS_2_DEFAULT 0x0 - -struct reserved_regs_2 { - a_uint32_t spare_regs_2:32; -}; - -union reserved_regs_2_u { - a_uint32_t val; - struct reserved_regs_2 bf; -}; - -/*[register] RESERVED_REGS_3*/ -#define RESERVED_REGS_3 -#define RESERVED_REGS_3_ADDRESS 0x7c -#define RESERVED_REGS_3_NUM 1 -#define RESERVED_REGS_3_INC 0x4 -#define RESERVED_REGS_3_TYPE REG_TYPE_RW -#define RESERVED_REGS_3_DEFAULT 0x0 - /*[field] SPARE_REGS_3*/ - #define RESERVED_REGS_3_SPARE_REGS_3 - #define RESERVED_REGS_3_SPARE_REGS_3_OFFSET 0 - #define RESERVED_REGS_3_SPARE_REGS_3_LEN 32 - #define RESERVED_REGS_3_SPARE_REGS_3_DEFAULT 0x0 - -struct reserved_regs_3 { - a_uint32_t spare_regs_3:32; -}; - -union reserved_regs_3_u { - a_uint32_t val; - struct reserved_regs_3 bf; -}; - -/*[register] DBG_DATA_SEL*/ -#define DBG_DATA_SEL -#define DBG_DATA_SEL_ADDRESS 0x80 -#define DBG_DATA_SEL_NUM 1 -#define DBG_DATA_SEL_INC 0x4 -#define DBG_DATA_SEL_TYPE REG_TYPE_RW -#define DBG_DATA_SEL_DEFAULT 0x0 - /*[field] DBG_DATA_SEL_DESP*/ - #define DBG_DATA_SEL_DBG_DATA_SEL_DESP - #define DBG_DATA_SEL_DBG_DATA_SEL_DESP_OFFSET 0 - #define DBG_DATA_SEL_DBG_DATA_SEL_DESP_LEN 5 - #define DBG_DATA_SEL_DBG_DATA_SEL_DESP_DEFAULT 0x0 - /*[field] DBG_DATA_SEL_SWITCH*/ - #define DBG_DATA_SEL_DBG_DATA_SEL_SWITCH - #define DBG_DATA_SEL_DBG_DATA_SEL_SWITCH_OFFSET 5 - #define DBG_DATA_SEL_DBG_DATA_SEL_SWITCH_LEN 1 - #define DBG_DATA_SEL_DBG_DATA_SEL_SWITCH_DEFAULT 0x0 - -struct dbg_data_sel { - a_uint32_t dbg_data_sel_desp:5; - a_uint32_t dbg_data_sel_switch:1; - a_uint32_t _reserved0:26; -}; - -union dbg_data_sel_u { - a_uint32_t val; - struct dbg_data_sel bf; -}; - - - -#endif diff --git a/feeds/ipq807x/qca-ssdk/src/include/hsl/hppe/hppe_init.h b/feeds/ipq807x/qca-ssdk/src/include/hsl/hppe/hppe_init.h deleted file mode 100755 index 0ec05ff5e..000000000 --- a/feeds/ipq807x/qca-ssdk/src/include/hsl/hppe/hppe_init.h +++ /dev/null @@ -1,117 +0,0 @@ -/* - * Copyright (c) 2016-2017, 2019-2020, The Linux Foundation. All rights reserved. - * Permission to use, copy, modify, and/or distribute this software for - * any purpose with or without fee is hereby granted, provided that the - * above copyright notice and this permission notice appear in all copies. - * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES - * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR - * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES - * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN - * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT - * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. - */ - - -/** - * @defgroup hppe_init _HPPE_INIT_H_ - * @{ - */ -#ifndef _HPPE_INIT_H_ -#define _HPPE_INIT_H_ - -#ifdef __cplusplus -extern "C" { -#endif /* __cplusplus */ - -#include "init/ssdk_init.h" - -#define HPPE_GCC_UNIPHY_REG_INC 0x100 -#define HPPE_TO_XGMAC_PORT_ID(port_id) (port_id - 5) -#define HPPE_TO_GMAC_PORT_ID(port_id) (port_id -1) -#define HPPE_FCS_LEN 4 - -#define HPPE_MUX_PORT1 5 -#define HPPE_MUX_PORT2 6 - -#define HPPE_GCC_UNIPHY_PSGMII_SOFT_RESET 0x3ff2 -#define HPPE_GCC_UNIPHY_USXGMII_SOFT_RESET 0x36 -#define HPPE_MAX_PORT_NUM 6 -#define HPPE_GCC_UNIPHY_USXGMII_XPCS_RESET 0x4 -#define HPPE_GCC_UNIPHY_USXGMII_XPCS_RELEASE_RESET 0x0 - - -#define HPPE_UNIPHY_BASE1 0x10000 -#define HPPE_UNIPHY_BASE2 0x20000 -#define HPPE_UNIPHY_MAX_DIRECT_ACCESS_REG 0x7fff -#define HPPE_UNIPHY_INDIRECT_REG_ADDR 0x83fc -#define HPPE_UNIPHY_INDIRECT_HIGH_ADDR 0x1fff00 -#define HPPE_UNIPHY_INDIRECT_LOW_ADDR 0xff -#define HPPE_UNIPHY_INDIRECT_DATA 0x20 -#define UNIPHY_CALIBRATION_DONE 0x1 -#define UNIPHY_10GR_LINKUP 0x1 -#define UNIPHY_10GR_LINK_LOSS 0x7 -#define UNIPHY_ATHEROS_NEGOTIATION 0x0 -#define UNIPHY_STANDARD_NEGOTIATION 0x1 -#define UNIPHY_CH0_QSGMII_SGMII_MODE 0x0 -#define UNIPHY_CH0_PSGMII_MODE 0x1 -#define UNIPHY_CH0_SGMII_MODE 0x0 -#define UNIPHY_CH0_QSGMII_MODE 0x1 -#define UNIPHY_SGMII_MODE_ENABLE 0x1 -#define UNIPHY_SGMII_MODE_DISABLE 0x0 -#define UNIPHY_SGMIIPLUS_MODE_ENABLE 0x1 -#define UNIPHY_SGMIIPLUS_MODE_DISABLE 0x0 -#define UNIPHY_XPCS_MODE_ENABLE 0x1 -#define UNIPHY_XPCS_MODE_DISABLE 0x0 -#define UNIPHY_PHY_SGMII_MODE 0x3 -#define UNIPHY_PHY_SGMIIPLUS_MODE 0x5 -#define UNIPHY_SGMII_CHANNEL1_DISABLE 0x0 -#define UNIPHY_SGMII_CHANNEL1_ENABLE 0x1 -#define UNIPHY_SGMII_CHANNEL4_DISABLE 0x0 -#define UNIPHY_SGMII_CHANNEL4_ENABLE 0x1 -#define UNIPHY_FORCE_SPEED_ENABLE 0x1 - -#define SGMII_1000M_SOURCE1_CLOCK1 0x101 -#define SGMII_100M_SOURCE1_CLOCK1 0x109 -#define SGMII_10M_SOURCE1_CLOCK1 0x109 -#define SGMII_1000M_SOURCE2_CLOCK1 0x301 -#define SGMII_100M_SOURCE2_CLOCK1 0x309 -#define SGMII_10M_SOURCE2_CLOCK1 0x309 -#define SGMII_1000M_CLOCK2 0x0 -#define SGMII_100M_CLOCK2 0x0 -#define SGMII_10M_CLOCK2 0x9 -#define UNIPHY_MISC2_REG_OFFSET 0x218 -#define UNIPHY_PLL_RESET_REG_OFFSET 0x780 -#define UNIPHY_MISC2_REG_VALUE 0x70 -#define UNIPHY_MISC2_REG_SGMII_PLUS_MODE 0x50 -#define UNIPHY_PLL_RESET_REG_VALUE 0x02bf -#define UNIPHY_PLL_RESET_REG_DEFAULT_VALUE 0x02ff -#define UNIPHY_MISC2_REG_SGMII_MODE 0x30 -#define UNIPHY_FORCE_SPEED_MODE_ENABLE 0x1 - -#define AQ_PHY_AUTO_STATUS_REG 0x70001 -#define AQ_PHY_LINK_STATUS_REG 0x7c800 -#define AQ_PHY_FLOWCTRL_STATUS_REG 0x7c810 -#define PHY_MII_STATUS_REG 0x11 - - -#define MALIBU_PHY_QSGMII 0x8504 -#define MALIBU_PHY_MODE_REG 0x1f -#define MALIBU_PSGMII_PHY_ADDR 0x5 -#define MALIBU_MODE_CHANAGE_RESET 0x0 -#define MALIBU_MODE_RESET_DEFAULT_VALUE 0x5f -#define MALIBU_MODE_RESET_REG 0x0 - -sw_error_t hppe_init(a_uint32_t dev_id, ssdk_init_cfg *cfg); -a_bool_t hppe_mac_port_valid_check(a_uint32_t dev_id, fal_port_t port_id); -a_bool_t hppe_xgmac_port_check(fal_port_t port_id); -sw_error_t hppe_cleanup(a_uint32_t dev_id); - -#ifdef __cplusplus -} -#endif /* __cplusplus */ - -#endif /* _HPPE_INIT_H_ */ -/** - * @} - */ diff --git a/feeds/ipq807x/qca-ssdk/src/include/hsl/hppe/hppe_ip.h b/feeds/ipq807x/qca-ssdk/src/include/hsl/hppe/hppe_ip.h deleted file mode 100755 index e3f17fba8..000000000 --- a/feeds/ipq807x/qca-ssdk/src/include/hsl/hppe/hppe_ip.h +++ /dev/null @@ -1,2696 +0,0 @@ -/* - * Copyright (c) 2016-2017, The Linux Foundation. All rights reserved. - * Permission to use, copy, modify, and/or distribute this software for - * any purpose with or without fee is hereby granted, provided that the - * above copyright notice and this permission notice appear in all copies. - * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES - * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR - * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES - * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN - * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT - * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. - */ - - -/** - * @defgroup - * @{ - */ -#ifndef _HPPE_IP_H_ -#define _HPPE_IP_H_ - -#define MY_MAC_TBL_MAX_ENTRY 8 -#define L3_VSI_MAX_ENTRY 32 -#define L3_VSI_EXT_MAX_ENTRY 32 -#define NETWORK_ROUTE_IP_MAX_ENTRY 32 -#define NETWORK_ROUTE_IP_EXT_MAX_ENTRY 32 -#define NETWORK_ROUTE_ACTION_MAX_ENTRY 32 -#define L3_VP_PORT_TBL_MAX_ENTRY 256 -#define IN_L3_IF_TBL_MAX_ENTRY 256 -#define HOST_IPV6_MCAST_TBL_MAX_ENTRY 1536 -#define HOST_IPV4_MCAST_TBL_MAX_ENTRY 3072 -#define HOST_TBL_MAX_ENTRY 6144 -#define HOST_IPV6_TBL_MAX_ENTRY 3072 -#define IN_NEXTHOP_TBL_MAX_ENTRY 2560 -#define EG_L3_IF_TBL_MAX_ENTRY 256 -#define IN_PUB_IP_ADDR_TBL_MAX_ENTRY 16 -#define RT_INTERFACE_CNT_TBL_MAX_ENTRY 512 - -#ifndef IP_MINI -sw_error_t -hppe_rt_interface_cnt_tbl_get( - a_uint32_t dev_id, - a_uint32_t index, - union rt_interface_cnt_tbl_u *value); - -sw_error_t -hppe_rt_interface_cnt_tbl_set( - a_uint32_t dev_id, - a_uint32_t index, - union rt_interface_cnt_tbl_u *value); - -sw_error_t -hppe_my_mac_tbl_get( - a_uint32_t dev_id, - a_uint32_t index, - union my_mac_tbl_u *value); - -sw_error_t -hppe_my_mac_tbl_set( - a_uint32_t dev_id, - a_uint32_t index, - union my_mac_tbl_u *value); - -sw_error_t -hppe_l3_vsi_get( - a_uint32_t dev_id, - a_uint32_t index, - union l3_vsi_u *value); - -sw_error_t -hppe_l3_vsi_set( - a_uint32_t dev_id, - a_uint32_t index, - union l3_vsi_u *value); - -sw_error_t -hppe_l3_vsi_ext_get( - a_uint32_t dev_id, - a_uint32_t index, - union l3_vsi_ext_u *value); - -sw_error_t -hppe_l3_vsi_ext_set( - a_uint32_t dev_id, - a_uint32_t index, - union l3_vsi_ext_u *value); - -sw_error_t -hppe_in_pub_ip_addr_tbl_set( - a_uint32_t dev_id, - a_uint32_t index, - union in_pub_ip_addr_tbl_u *value); - -sw_error_t -hppe_in_pub_ip_addr_tbl_get( - a_uint32_t dev_id, - a_uint32_t index, - union in_pub_ip_addr_tbl_u *value); - -sw_error_t -hppe_network_route_ip_get( - a_uint32_t dev_id, - a_uint32_t index, - union network_route_ip_u *value); - -sw_error_t -hppe_network_route_ip_set( - a_uint32_t dev_id, - a_uint32_t index, - union network_route_ip_u *value); - -sw_error_t -hppe_network_route_ip_ext_get( - a_uint32_t dev_id, - a_uint32_t index, - union network_route_ip_ext_u *value); - -sw_error_t -hppe_network_route_ip_ext_set( - a_uint32_t dev_id, - a_uint32_t index, - union network_route_ip_ext_u *value); - -sw_error_t -hppe_network_route_action_get( - a_uint32_t dev_id, - a_uint32_t index, - union network_route_action_u *value); - -sw_error_t -hppe_network_route_action_set( - a_uint32_t dev_id, - a_uint32_t index, - union network_route_action_u *value); -#endif -#if ((!defined IN_IP_MINI) || (!defined IN_FLOW_MINI)) -sw_error_t -hppe_l3_route_ctrl_get( - a_uint32_t dev_id, - union l3_route_ctrl_u *value); - -sw_error_t -hppe_l3_route_ctrl_set( - a_uint32_t dev_id, - union l3_route_ctrl_u *value); - -sw_error_t -hppe_l3_route_ctrl_ext_get( - a_uint32_t dev_id, - union l3_route_ctrl_ext_u *value); - -sw_error_t -hppe_l3_route_ctrl_ext_set( - a_uint32_t dev_id, - union l3_route_ctrl_ext_u *value); -#endif -#ifndef IN_IP_MINI -sw_error_t -hppe_host_tbl_op_get( - a_uint32_t dev_id, - union host_tbl_op_u *value); - -sw_error_t -hppe_host_tbl_op_set( - a_uint32_t dev_id, - union host_tbl_op_u *value); -#endif -#if ((!defined IN_IP_MINI) || (!defined IN_FLOW_MINI)) -sw_error_t -hppe_host_tbl_op_data0_get( - a_uint32_t dev_id, - union host_tbl_op_data0_u *value); - -sw_error_t -hppe_host_tbl_op_data0_set( - a_uint32_t dev_id, - union host_tbl_op_data0_u *value); - -sw_error_t -hppe_host_tbl_op_data1_get( - a_uint32_t dev_id, - union host_tbl_op_data1_u *value); - -sw_error_t -hppe_host_tbl_op_data1_set( - a_uint32_t dev_id, - union host_tbl_op_data1_u *value); - -sw_error_t -hppe_host_tbl_op_data2_get( - a_uint32_t dev_id, - union host_tbl_op_data2_u *value); - -sw_error_t -hppe_host_tbl_op_data2_set( - a_uint32_t dev_id, - union host_tbl_op_data2_u *value); - -sw_error_t -hppe_host_tbl_op_data3_get( - a_uint32_t dev_id, - union host_tbl_op_data3_u *value); - -sw_error_t -hppe_host_tbl_op_data3_set( - a_uint32_t dev_id, - union host_tbl_op_data3_u *value); - -sw_error_t -hppe_host_tbl_op_data4_get( - a_uint32_t dev_id, - union host_tbl_op_data4_u *value); - -sw_error_t -hppe_host_tbl_op_data4_set( - a_uint32_t dev_id, - union host_tbl_op_data4_u *value); -#endif -#ifndef IN_IP_MINI -sw_error_t -hppe_host_tbl_op_data5_get( - a_uint32_t dev_id, - union host_tbl_op_data5_u *value); - -sw_error_t -hppe_host_tbl_op_data5_set( - a_uint32_t dev_id, - union host_tbl_op_data5_u *value); - -sw_error_t -hppe_host_tbl_op_data6_get( - a_uint32_t dev_id, - union host_tbl_op_data6_u *value); - -sw_error_t -hppe_host_tbl_op_data6_set( - a_uint32_t dev_id, - union host_tbl_op_data6_u *value); - -sw_error_t -hppe_host_tbl_op_data7_get( - a_uint32_t dev_id, - union host_tbl_op_data7_u *value); - -sw_error_t -hppe_host_tbl_op_data7_set( - a_uint32_t dev_id, - union host_tbl_op_data7_u *value); - -sw_error_t -hppe_host_tbl_op_data8_get( - a_uint32_t dev_id, - union host_tbl_op_data8_u *value); - -sw_error_t -hppe_host_tbl_op_data8_set( - a_uint32_t dev_id, - union host_tbl_op_data8_u *value); - -sw_error_t -hppe_host_tbl_op_data9_get( - a_uint32_t dev_id, - union host_tbl_op_data9_u *value); - -sw_error_t -hppe_host_tbl_op_data9_set( - a_uint32_t dev_id, - union host_tbl_op_data9_u *value); - -sw_error_t -hppe_host_tbl_op_rslt_get( - a_uint32_t dev_id, - union host_tbl_op_rslt_u *value); - -sw_error_t -hppe_host_tbl_op_rslt_set( - a_uint32_t dev_id, - union host_tbl_op_rslt_u *value); - -sw_error_t -hppe_host_tbl_rd_op_get( - a_uint32_t dev_id, - union host_tbl_rd_op_u *value); - -sw_error_t -hppe_host_tbl_rd_op_set( - a_uint32_t dev_id, - union host_tbl_rd_op_u *value); -#endif -#if ((!defined IN_IP_MINI) || (!defined IN_FLOW_MINI)) -sw_error_t -hppe_host_tbl_rd_op_data0_get( - a_uint32_t dev_id, - union host_tbl_rd_op_data0_u *value); - -sw_error_t -hppe_host_tbl_rd_op_data0_set( - a_uint32_t dev_id, - union host_tbl_rd_op_data0_u *value); - -sw_error_t -hppe_host_tbl_rd_op_data1_get( - a_uint32_t dev_id, - union host_tbl_rd_op_data1_u *value); - -sw_error_t -hppe_host_tbl_rd_op_data1_set( - a_uint32_t dev_id, - union host_tbl_rd_op_data1_u *value); - -sw_error_t -hppe_host_tbl_rd_op_data2_get( - a_uint32_t dev_id, - union host_tbl_rd_op_data2_u *value); - -sw_error_t -hppe_host_tbl_rd_op_data2_set( - a_uint32_t dev_id, - union host_tbl_rd_op_data2_u *value); - -sw_error_t -hppe_host_tbl_rd_op_data3_get( - a_uint32_t dev_id, - union host_tbl_rd_op_data3_u *value); - -sw_error_t -hppe_host_tbl_rd_op_data3_set( - a_uint32_t dev_id, - union host_tbl_rd_op_data3_u *value); - -sw_error_t -hppe_host_tbl_rd_op_data4_get( - a_uint32_t dev_id, - union host_tbl_rd_op_data4_u *value); - -sw_error_t -hppe_host_tbl_rd_op_data4_set( - a_uint32_t dev_id, - union host_tbl_rd_op_data4_u *value); -#endif -#ifndef IN_IP_MINI -sw_error_t -hppe_host_tbl_rd_op_data5_get( - a_uint32_t dev_id, - union host_tbl_rd_op_data5_u *value); - -sw_error_t -hppe_host_tbl_rd_op_data5_set( - a_uint32_t dev_id, - union host_tbl_rd_op_data5_u *value); - -sw_error_t -hppe_host_tbl_rd_op_data6_get( - a_uint32_t dev_id, - union host_tbl_rd_op_data6_u *value); - -sw_error_t -hppe_host_tbl_rd_op_data6_set( - a_uint32_t dev_id, - union host_tbl_rd_op_data6_u *value); - -sw_error_t -hppe_host_tbl_rd_op_data7_get( - a_uint32_t dev_id, - union host_tbl_rd_op_data7_u *value); - -sw_error_t -hppe_host_tbl_rd_op_data7_set( - a_uint32_t dev_id, - union host_tbl_rd_op_data7_u *value); - -sw_error_t -hppe_host_tbl_rd_op_data8_get( - a_uint32_t dev_id, - union host_tbl_rd_op_data8_u *value); - -sw_error_t -hppe_host_tbl_rd_op_data8_set( - a_uint32_t dev_id, - union host_tbl_rd_op_data8_u *value); - -sw_error_t -hppe_host_tbl_rd_op_data9_get( - a_uint32_t dev_id, - union host_tbl_rd_op_data9_u *value); - -sw_error_t -hppe_host_tbl_rd_op_data9_set( - a_uint32_t dev_id, - union host_tbl_rd_op_data9_u *value); - -sw_error_t -hppe_host_tbl_rd_op_rslt_get( - a_uint32_t dev_id, - union host_tbl_rd_op_rslt_u *value); - -sw_error_t -hppe_host_tbl_rd_op_rslt_set( - a_uint32_t dev_id, - union host_tbl_rd_op_rslt_u *value); - -sw_error_t -hppe_host_tbl_rd_rslt_data0_get( - a_uint32_t dev_id, - union host_tbl_rd_rslt_data0_u *value); - -sw_error_t -hppe_host_tbl_rd_rslt_data0_set( - a_uint32_t dev_id, - union host_tbl_rd_rslt_data0_u *value); - -sw_error_t -hppe_host_tbl_rd_rslt_data1_get( - a_uint32_t dev_id, - union host_tbl_rd_rslt_data1_u *value); - -sw_error_t -hppe_host_tbl_rd_rslt_data1_set( - a_uint32_t dev_id, - union host_tbl_rd_rslt_data1_u *value); - -sw_error_t -hppe_host_tbl_rd_rslt_data2_get( - a_uint32_t dev_id, - union host_tbl_rd_rslt_data2_u *value); - -sw_error_t -hppe_host_tbl_rd_rslt_data2_set( - a_uint32_t dev_id, - union host_tbl_rd_rslt_data2_u *value); - -sw_error_t -hppe_host_tbl_rd_rslt_data3_get( - a_uint32_t dev_id, - union host_tbl_rd_rslt_data3_u *value); - -sw_error_t -hppe_host_tbl_rd_rslt_data3_set( - a_uint32_t dev_id, - union host_tbl_rd_rslt_data3_u *value); - -sw_error_t -hppe_host_tbl_rd_rslt_data4_get( - a_uint32_t dev_id, - union host_tbl_rd_rslt_data4_u *value); - -sw_error_t -hppe_host_tbl_rd_rslt_data4_set( - a_uint32_t dev_id, - union host_tbl_rd_rslt_data4_u *value); - -sw_error_t -hppe_host_tbl_rd_rslt_data5_get( - a_uint32_t dev_id, - union host_tbl_rd_rslt_data5_u *value); - -sw_error_t -hppe_host_tbl_rd_rslt_data5_set( - a_uint32_t dev_id, - union host_tbl_rd_rslt_data5_u *value); - -sw_error_t -hppe_host_tbl_rd_rslt_data6_get( - a_uint32_t dev_id, - union host_tbl_rd_rslt_data6_u *value); - -sw_error_t -hppe_host_tbl_rd_rslt_data6_set( - a_uint32_t dev_id, - union host_tbl_rd_rslt_data6_u *value); - -sw_error_t -hppe_host_tbl_rd_rslt_data7_get( - a_uint32_t dev_id, - union host_tbl_rd_rslt_data7_u *value); - -sw_error_t -hppe_host_tbl_rd_rslt_data7_set( - a_uint32_t dev_id, - union host_tbl_rd_rslt_data7_u *value); - -sw_error_t -hppe_host_tbl_rd_rslt_data8_get( - a_uint32_t dev_id, - union host_tbl_rd_rslt_data8_u *value); - -sw_error_t -hppe_host_tbl_rd_rslt_data8_set( - a_uint32_t dev_id, - union host_tbl_rd_rslt_data8_u *value); - -sw_error_t -hppe_host_tbl_rd_rslt_data9_get( - a_uint32_t dev_id, - union host_tbl_rd_rslt_data9_u *value); - -sw_error_t -hppe_host_tbl_rd_rslt_data9_set( - a_uint32_t dev_id, - union host_tbl_rd_rslt_data9_u *value); - -sw_error_t -hppe_l3_dbg_cmd_get( - a_uint32_t dev_id, - union l3_dbg_cmd_u *value); - -sw_error_t -hppe_l3_dbg_cmd_set( - a_uint32_t dev_id, - union l3_dbg_cmd_u *value); - -sw_error_t -hppe_l3_dbg_wr_data_get( - a_uint32_t dev_id, - union l3_dbg_wr_data_u *value); - -sw_error_t -hppe_l3_dbg_wr_data_set( - a_uint32_t dev_id, - union l3_dbg_wr_data_u *value); - -sw_error_t -hppe_l3_dbg_rd_data_get( - a_uint32_t dev_id, - union l3_dbg_rd_data_u *value); - -sw_error_t -hppe_l3_dbg_rd_data_set( - a_uint32_t dev_id, - union l3_dbg_rd_data_u *value); -#endif -sw_error_t -hppe_l3_vp_port_tbl_get( - a_uint32_t dev_id, - a_uint32_t index, - union l3_vp_port_tbl_u *value); - -sw_error_t -hppe_l3_vp_port_tbl_set( - a_uint32_t dev_id, - a_uint32_t index, - union l3_vp_port_tbl_u *value); -#if ((!defined IN_IP_MINI) || (defined IN_PPPOE)) -sw_error_t -hppe_in_l3_if_tbl_get( - a_uint32_t dev_id, - a_uint32_t index, - union in_l3_if_tbl_u *value); - -sw_error_t -hppe_in_l3_if_tbl_set( - a_uint32_t dev_id, - a_uint32_t index, - union in_l3_if_tbl_u *value); -#endif -#ifndef IN_IP_MINI -sw_error_t -hppe_host_ipv6_mcast_tbl_get( - a_uint32_t dev_id, - a_uint32_t index, - union host_ipv6_mcast_tbl_u *value); - -sw_error_t -hppe_host_ipv6_mcast_tbl_set( - a_uint32_t dev_id, - a_uint32_t index, - union host_ipv6_mcast_tbl_u *value); - -sw_error_t -hppe_host_ipv4_mcast_tbl_get( - a_uint32_t dev_id, - a_uint32_t index, - union host_ipv4_mcast_tbl_u *value); - -sw_error_t -hppe_host_ipv4_mcast_tbl_set( - a_uint32_t dev_id, - a_uint32_t index, - union host_ipv4_mcast_tbl_u *value); - -sw_error_t -hppe_host_tbl_get( - a_uint32_t dev_id, - a_uint32_t index, - union host_tbl_u *value); - -sw_error_t -hppe_host_tbl_set( - a_uint32_t dev_id, - a_uint32_t index, - union host_tbl_u *value); - -sw_error_t -hppe_host_ipv6_tbl_get( - a_uint32_t dev_id, - a_uint32_t index, - union host_ipv6_tbl_u *value); - -sw_error_t -hppe_host_ipv6_tbl_set( - a_uint32_t dev_id, - a_uint32_t index, - union host_ipv6_tbl_u *value); - -sw_error_t -hppe_in_nexthop_tbl_get( - a_uint32_t dev_id, - a_uint32_t index, - union in_nexthop_tbl_u *value); - -sw_error_t -hppe_in_nexthop_tbl_set( - a_uint32_t dev_id, - a_uint32_t index, - union in_nexthop_tbl_u *value); -#endif -#if ((!defined IN_IP_MINI) || (defined IN_PPPOE)) -sw_error_t -hppe_eg_l3_if_tbl_get( - a_uint32_t dev_id, - a_uint32_t index, - union eg_l3_if_tbl_u *value); - -sw_error_t -hppe_eg_l3_if_tbl_set( - a_uint32_t dev_id, - a_uint32_t index, - union eg_l3_if_tbl_u *value); -#endif -#ifndef IN_IP_MINI -sw_error_t -hppe_my_mac_tbl_mac_da_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint64_t *value); - -sw_error_t -hppe_my_mac_tbl_mac_da_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint64_t value); - -sw_error_t -hppe_my_mac_tbl_valid_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_my_mac_tbl_valid_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_l3_vsi_l3_if_index_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_l3_vsi_l3_if_index_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_l3_vsi_l2_ipv6_mc_mode_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_l3_vsi_l2_ipv6_mc_mode_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_l3_vsi_l3_if_valid_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_l3_vsi_l3_if_valid_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_l3_vsi_l2_ipv6_mc_en_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_l3_vsi_l2_ipv6_mc_en_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_l3_vsi_l2_ipv4_mc_en_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_l3_vsi_l2_ipv4_mc_en_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_l3_vsi_l2_ipv4_mc_mode_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_l3_vsi_l2_ipv4_mc_mode_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_l3_vsi_ext_ip_arp_sg_en_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_l3_vsi_ext_ip_arp_sg_en_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_l3_vsi_ext_ipv6_sg_svlan_en_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_l3_vsi_ext_ipv6_sg_svlan_en_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_l3_vsi_ext_ip_nd_sg_cvlan_en_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_l3_vsi_ext_ip_nd_sg_cvlan_en_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_l3_vsi_ext_ip_nd_sg_vio_cmd_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_l3_vsi_ext_ip_nd_sg_vio_cmd_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_l3_vsi_ext_ipv4_sg_port_en_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_l3_vsi_ext_ipv4_sg_port_en_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_l3_vsi_ext_ip_nd_sg_en_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_l3_vsi_ext_ip_nd_sg_en_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_l3_vsi_ext_ipv4_sg_svlan_en_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_l3_vsi_ext_ipv4_sg_svlan_en_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_l3_vsi_ext_ipv4_sg_cvlan_en_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_l3_vsi_ext_ipv4_sg_cvlan_en_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_l3_vsi_ext_ip_arp_sg_svlan_en_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_l3_vsi_ext_ip_arp_sg_svlan_en_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_l3_vsi_ext_ip_nd_sg_svlan_en_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_l3_vsi_ext_ip_nd_sg_svlan_en_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_l3_vsi_ext_ipv6_sg_vio_cmd_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_l3_vsi_ext_ipv6_sg_vio_cmd_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_l3_vsi_ext_ip_nd_sg_port_en_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_l3_vsi_ext_ip_nd_sg_port_en_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_l3_vsi_ext_ip_arp_src_unk_cmd_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_l3_vsi_ext_ip_arp_src_unk_cmd_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_l3_vsi_ext_ipv6_sg_port_en_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_l3_vsi_ext_ipv6_sg_port_en_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_l3_vsi_ext_ipv4_src_unk_cmd_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_l3_vsi_ext_ipv4_src_unk_cmd_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_l3_vsi_ext_ip_arp_sg_vio_cmd_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_l3_vsi_ext_ip_arp_sg_vio_cmd_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_l3_vsi_ext_ip_arp_sg_port_en_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_l3_vsi_ext_ip_arp_sg_port_en_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_l3_vsi_ext_ipv4_sg_vio_cmd_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_l3_vsi_ext_ipv4_sg_vio_cmd_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_l3_vsi_ext_ipv6_src_unk_cmd_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_l3_vsi_ext_ipv6_src_unk_cmd_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_l3_vsi_ext_ipv6_sg_en_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_l3_vsi_ext_ipv6_sg_en_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_l3_vsi_ext_ip_arp_sg_cvlan_en_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_l3_vsi_ext_ip_arp_sg_cvlan_en_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_l3_vsi_ext_ip_nd_src_unk_cmd_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_l3_vsi_ext_ip_nd_src_unk_cmd_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_l3_vsi_ext_ipv4_sg_en_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_l3_vsi_ext_ipv4_sg_en_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_l3_vsi_ext_ipv6_sg_cvlan_en_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_l3_vsi_ext_ipv6_sg_cvlan_en_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_network_route_ip_ip_addr_mask_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_network_route_ip_ip_addr_mask_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_network_route_ip_ip_addr_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_network_route_ip_ip_addr_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_network_route_ip_ext_entry_type_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_network_route_ip_ext_entry_type_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_network_route_ip_ext_valid_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_network_route_ip_ext_valid_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_network_route_action_lan_wan_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_network_route_action_lan_wan_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_network_route_action_fwd_cmd_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_network_route_action_fwd_cmd_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_network_route_action_dst_info_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_network_route_action_dst_info_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_l3_route_ctrl_flow_src_if_check_de_acce_get( - a_uint32_t dev_id, - unsigned int *value); - -sw_error_t -hppe_l3_route_ctrl_flow_src_if_check_de_acce_set( - a_uint32_t dev_id, - unsigned int value); - -sw_error_t -hppe_l3_route_ctrl_pppoe_multicast_cmd_get( - a_uint32_t dev_id, - unsigned int *value); - -sw_error_t -hppe_l3_route_ctrl_pppoe_multicast_cmd_set( - a_uint32_t dev_id, - unsigned int value); - -sw_error_t -hppe_l3_route_ctrl_ip_mtu_fail_get( - a_uint32_t dev_id, - unsigned int *value); - -sw_error_t -hppe_l3_route_ctrl_ip_mtu_fail_set( - a_uint32_t dev_id, - unsigned int value); - -sw_error_t -hppe_l3_route_ctrl_flow_src_if_check_cmd_get( - a_uint32_t dev_id, - unsigned int *value); - -sw_error_t -hppe_l3_route_ctrl_flow_src_if_check_cmd_set( - a_uint32_t dev_id, - unsigned int value); - -sw_error_t -hppe_l3_route_ctrl_icmp_rdt_de_acce_get( - a_uint32_t dev_id, - unsigned int *value); - -sw_error_t -hppe_l3_route_ctrl_icmp_rdt_de_acce_set( - a_uint32_t dev_id, - unsigned int value); - -sw_error_t -hppe_l3_route_ctrl_flow_de_acce_cmd_get( - a_uint32_t dev_id, - unsigned int *value); - -sw_error_t -hppe_l3_route_ctrl_flow_de_acce_cmd_set( - a_uint32_t dev_id, - unsigned int value); - -sw_error_t -hppe_l3_route_ctrl_ip_mtu_fail_de_acce_get( - a_uint32_t dev_id, - unsigned int *value); - -sw_error_t -hppe_l3_route_ctrl_ip_mtu_fail_de_acce_set( - a_uint32_t dev_id, - unsigned int value); - -sw_error_t -hppe_l3_route_ctrl_flow_sync_mismatch_cmd_get( - a_uint32_t dev_id, - unsigned int *value); - -sw_error_t -hppe_l3_route_ctrl_flow_sync_mismatch_cmd_set( - a_uint32_t dev_id, - unsigned int value); - -sw_error_t -hppe_l3_route_ctrl_flow_service_code_loop_de_acce_get( - a_uint32_t dev_id, - unsigned int *value); - -sw_error_t -hppe_l3_route_ctrl_flow_service_code_loop_de_acce_set( - a_uint32_t dev_id, - unsigned int value); - -sw_error_t -hppe_l3_route_ctrl_flow_sync_mismatch_de_acce_get( - a_uint32_t dev_id, - unsigned int *value); - -sw_error_t -hppe_l3_route_ctrl_flow_sync_mismatch_de_acce_set( - a_uint32_t dev_id, - unsigned int value); - -sw_error_t -hppe_l3_route_ctrl_ip_mtu_df_fail_get( - a_uint32_t dev_id, - unsigned int *value); - -sw_error_t -hppe_l3_route_ctrl_ip_mtu_df_fail_set( - a_uint32_t dev_id, - unsigned int value); - -sw_error_t -hppe_l3_route_ctrl_flow_service_code_loop_get( - a_uint32_t dev_id, - unsigned int *value); - -sw_error_t -hppe_l3_route_ctrl_flow_service_code_loop_set( - a_uint32_t dev_id, - unsigned int value); - -sw_error_t -hppe_l3_route_ctrl_ip_mru_check_fail_de_acce_get( - a_uint32_t dev_id, - unsigned int *value); - -sw_error_t -hppe_l3_route_ctrl_ip_mru_check_fail_de_acce_set( - a_uint32_t dev_id, - unsigned int value); - -sw_error_t -hppe_l3_route_ctrl_ip_prefix_bc_cmd_get( - a_uint32_t dev_id, - unsigned int *value); - -sw_error_t -hppe_l3_route_ctrl_ip_prefix_bc_cmd_set( - a_uint32_t dev_id, - unsigned int value); - -sw_error_t -hppe_l3_route_ctrl_ip_mtu_df_fail_de_acce_get( - a_uint32_t dev_id, - unsigned int *value); - -sw_error_t -hppe_l3_route_ctrl_ip_mtu_df_fail_de_acce_set( - a_uint32_t dev_id, - unsigned int value); - -sw_error_t -hppe_l3_route_ctrl_pppoe_multicast_de_acce_get( - a_uint32_t dev_id, - unsigned int *value); - -sw_error_t -hppe_l3_route_ctrl_pppoe_multicast_de_acce_set( - a_uint32_t dev_id, - unsigned int value); - -sw_error_t -hppe_l3_route_ctrl_ip_mru_check_fail_get( - a_uint32_t dev_id, - unsigned int *value); - -sw_error_t -hppe_l3_route_ctrl_ip_mru_check_fail_set( - a_uint32_t dev_id, - unsigned int value); - -sw_error_t -hppe_l3_route_ctrl_icmp_rdt_cmd_get( - a_uint32_t dev_id, - unsigned int *value); - -sw_error_t -hppe_l3_route_ctrl_icmp_rdt_cmd_set( - a_uint32_t dev_id, - unsigned int value); - -sw_error_t -hppe_l3_route_ctrl_ip_prefix_bc_de_acce_get( - a_uint32_t dev_id, - unsigned int *value); - -sw_error_t -hppe_l3_route_ctrl_ip_prefix_bc_de_acce_set( - a_uint32_t dev_id, - unsigned int value); - -sw_error_t -hppe_l3_route_ctrl_ext_flow_service_code_loop_en_get( - a_uint32_t dev_id, - unsigned int *value); - -sw_error_t -hppe_l3_route_ctrl_ext_flow_service_code_loop_en_set( - a_uint32_t dev_id, - unsigned int value); - -sw_error_t -hppe_l3_route_ctrl_ext_host_hash_mode_0_get( - a_uint32_t dev_id, - unsigned int *value); - -sw_error_t -hppe_l3_route_ctrl_ext_host_hash_mode_0_set( - a_uint32_t dev_id, - unsigned int value); - -sw_error_t -hppe_l3_route_ctrl_ext_host_hash_mode_1_get( - a_uint32_t dev_id, - unsigned int *value); - -sw_error_t -hppe_l3_route_ctrl_ext_host_hash_mode_1_set( - a_uint32_t dev_id, - unsigned int value); - -sw_error_t -hppe_l3_route_ctrl_ext_ip_route_mismatch_get( - a_uint32_t dev_id, - unsigned int *value); - -sw_error_t -hppe_l3_route_ctrl_ext_ip_route_mismatch_set( - a_uint32_t dev_id, - unsigned int value); - - -sw_error_t -hppe_host_tbl_op_entry_index_get( - a_uint32_t dev_id, - unsigned int *value); - -sw_error_t -hppe_host_tbl_op_entry_index_set( - a_uint32_t dev_id, - unsigned int value); - -sw_error_t -hppe_host_tbl_op_cmd_id_get( - a_uint32_t dev_id, - unsigned int *value); - -sw_error_t -hppe_host_tbl_op_cmd_id_set( - a_uint32_t dev_id, - unsigned int value); - -sw_error_t -hppe_host_tbl_op_byp_rslt_en_get( - a_uint32_t dev_id, - unsigned int *value); - -sw_error_t -hppe_host_tbl_op_byp_rslt_en_set( - a_uint32_t dev_id, - unsigned int value); - -sw_error_t -hppe_host_tbl_op_op_mode_get( - a_uint32_t dev_id, - unsigned int *value); - -sw_error_t -hppe_host_tbl_op_op_mode_set( - a_uint32_t dev_id, - unsigned int value); - -sw_error_t -hppe_host_tbl_op_op_type_get( - a_uint32_t dev_id, - unsigned int *value); - -sw_error_t -hppe_host_tbl_op_op_type_set( - a_uint32_t dev_id, - unsigned int value); - -sw_error_t -hppe_host_tbl_op_op_result_get( - a_uint32_t dev_id, - unsigned int *value); - -sw_error_t -hppe_host_tbl_op_op_result_set( - a_uint32_t dev_id, - unsigned int value); - -sw_error_t -hppe_host_tbl_op_busy_get( - a_uint32_t dev_id, - unsigned int *value); - -sw_error_t -hppe_host_tbl_op_busy_set( - a_uint32_t dev_id, - unsigned int value); - -sw_error_t -hppe_host_tbl_op_hash_block_bitmap_get( - a_uint32_t dev_id, - unsigned int *value); - -sw_error_t -hppe_host_tbl_op_hash_block_bitmap_set( - a_uint32_t dev_id, - unsigned int value); - -sw_error_t -hppe_host_tbl_op_data0_data_get( - a_uint32_t dev_id, - unsigned int *value); - -sw_error_t -hppe_host_tbl_op_data0_data_set( - a_uint32_t dev_id, - unsigned int value); - -sw_error_t -hppe_host_tbl_op_data1_data_get( - a_uint32_t dev_id, - unsigned int *value); - -sw_error_t -hppe_host_tbl_op_data1_data_set( - a_uint32_t dev_id, - unsigned int value); - -sw_error_t -hppe_host_tbl_op_data2_data_get( - a_uint32_t dev_id, - unsigned int *value); - -sw_error_t -hppe_host_tbl_op_data2_data_set( - a_uint32_t dev_id, - unsigned int value); - -sw_error_t -hppe_host_tbl_op_data3_data_get( - a_uint32_t dev_id, - unsigned int *value); - -sw_error_t -hppe_host_tbl_op_data3_data_set( - a_uint32_t dev_id, - unsigned int value); - -sw_error_t -hppe_host_tbl_op_data4_data_get( - a_uint32_t dev_id, - unsigned int *value); - -sw_error_t -hppe_host_tbl_op_data4_data_set( - a_uint32_t dev_id, - unsigned int value); - -sw_error_t -hppe_host_tbl_op_data5_data_get( - a_uint32_t dev_id, - unsigned int *value); - -sw_error_t -hppe_host_tbl_op_data5_data_set( - a_uint32_t dev_id, - unsigned int value); - -sw_error_t -hppe_host_tbl_op_data6_data_get( - a_uint32_t dev_id, - unsigned int *value); - -sw_error_t -hppe_host_tbl_op_data6_data_set( - a_uint32_t dev_id, - unsigned int value); - -sw_error_t -hppe_host_tbl_op_data7_data_get( - a_uint32_t dev_id, - unsigned int *value); - -sw_error_t -hppe_host_tbl_op_data7_data_set( - a_uint32_t dev_id, - unsigned int value); - -sw_error_t -hppe_host_tbl_op_data8_data_get( - a_uint32_t dev_id, - unsigned int *value); - -sw_error_t -hppe_host_tbl_op_data8_data_set( - a_uint32_t dev_id, - unsigned int value); - -sw_error_t -hppe_host_tbl_op_data9_data_get( - a_uint32_t dev_id, - unsigned int *value); - -sw_error_t -hppe_host_tbl_op_data9_data_set( - a_uint32_t dev_id, - unsigned int value); - -sw_error_t -hppe_host_tbl_op_rslt_op_rslt_get( - a_uint32_t dev_id, - unsigned int *value); - -sw_error_t -hppe_host_tbl_op_rslt_op_rslt_set( - a_uint32_t dev_id, - unsigned int value); - -sw_error_t -hppe_host_tbl_op_rslt_valid_cnt_get( - a_uint32_t dev_id, - unsigned int *value); - -sw_error_t -hppe_host_tbl_op_rslt_valid_cnt_set( - a_uint32_t dev_id, - unsigned int value); - -sw_error_t -hppe_host_tbl_op_rslt_entry_index_get( - a_uint32_t dev_id, - unsigned int *value); - -sw_error_t -hppe_host_tbl_op_rslt_entry_index_set( - a_uint32_t dev_id, - unsigned int value); - -sw_error_t -hppe_host_tbl_op_rslt_cmd_id_get( - a_uint32_t dev_id, - unsigned int *value); - -sw_error_t -hppe_host_tbl_op_rslt_cmd_id_set( - a_uint32_t dev_id, - unsigned int value); - -sw_error_t -hppe_host_tbl_rd_op_entry_index_get( - a_uint32_t dev_id, - unsigned int *value); - -sw_error_t -hppe_host_tbl_rd_op_entry_index_set( - a_uint32_t dev_id, - unsigned int value); - -sw_error_t -hppe_host_tbl_rd_op_cmd_id_get( - a_uint32_t dev_id, - unsigned int *value); - -sw_error_t -hppe_host_tbl_rd_op_cmd_id_set( - a_uint32_t dev_id, - unsigned int value); - -sw_error_t -hppe_host_tbl_rd_op_byp_rslt_en_get( - a_uint32_t dev_id, - unsigned int *value); - -sw_error_t -hppe_host_tbl_rd_op_byp_rslt_en_set( - a_uint32_t dev_id, - unsigned int value); - -sw_error_t -hppe_host_tbl_rd_op_op_mode_get( - a_uint32_t dev_id, - unsigned int *value); - -sw_error_t -hppe_host_tbl_rd_op_op_mode_set( - a_uint32_t dev_id, - unsigned int value); - -sw_error_t -hppe_host_tbl_rd_op_op_type_get( - a_uint32_t dev_id, - unsigned int *value); - -sw_error_t -hppe_host_tbl_rd_op_op_type_set( - a_uint32_t dev_id, - unsigned int value); - -sw_error_t -hppe_host_tbl_rd_op_op_result_get( - a_uint32_t dev_id, - unsigned int *value); - -sw_error_t -hppe_host_tbl_rd_op_op_result_set( - a_uint32_t dev_id, - unsigned int value); - -sw_error_t -hppe_host_tbl_rd_op_busy_get( - a_uint32_t dev_id, - unsigned int *value); - -sw_error_t -hppe_host_tbl_rd_op_busy_set( - a_uint32_t dev_id, - unsigned int value); - -sw_error_t -hppe_host_tbl_rd_op_hash_block_bitmap_get( - a_uint32_t dev_id, - unsigned int *value); - -sw_error_t -hppe_host_tbl_rd_op_hash_block_bitmap_set( - a_uint32_t dev_id, - unsigned int value); - -sw_error_t -hppe_host_tbl_rd_op_data0_data_get( - a_uint32_t dev_id, - unsigned int *value); - -sw_error_t -hppe_host_tbl_rd_op_data0_data_set( - a_uint32_t dev_id, - unsigned int value); - -sw_error_t -hppe_host_tbl_rd_op_data1_data_get( - a_uint32_t dev_id, - unsigned int *value); - -sw_error_t -hppe_host_tbl_rd_op_data1_data_set( - a_uint32_t dev_id, - unsigned int value); - -sw_error_t -hppe_host_tbl_rd_op_data2_data_get( - a_uint32_t dev_id, - unsigned int *value); - -sw_error_t -hppe_host_tbl_rd_op_data2_data_set( - a_uint32_t dev_id, - unsigned int value); - -sw_error_t -hppe_host_tbl_rd_op_data3_data_get( - a_uint32_t dev_id, - unsigned int *value); - -sw_error_t -hppe_host_tbl_rd_op_data3_data_set( - a_uint32_t dev_id, - unsigned int value); - -sw_error_t -hppe_host_tbl_rd_op_data4_data_get( - a_uint32_t dev_id, - unsigned int *value); - -sw_error_t -hppe_host_tbl_rd_op_data4_data_set( - a_uint32_t dev_id, - unsigned int value); - -sw_error_t -hppe_host_tbl_rd_op_data5_data_get( - a_uint32_t dev_id, - unsigned int *value); - -sw_error_t -hppe_host_tbl_rd_op_data5_data_set( - a_uint32_t dev_id, - unsigned int value); - -sw_error_t -hppe_host_tbl_rd_op_data6_data_get( - a_uint32_t dev_id, - unsigned int *value); - -sw_error_t -hppe_host_tbl_rd_op_data6_data_set( - a_uint32_t dev_id, - unsigned int value); - -sw_error_t -hppe_host_tbl_rd_op_data7_data_get( - a_uint32_t dev_id, - unsigned int *value); - -sw_error_t -hppe_host_tbl_rd_op_data7_data_set( - a_uint32_t dev_id, - unsigned int value); - -sw_error_t -hppe_host_tbl_rd_op_data8_data_get( - a_uint32_t dev_id, - unsigned int *value); - -sw_error_t -hppe_host_tbl_rd_op_data8_data_set( - a_uint32_t dev_id, - unsigned int value); - -sw_error_t -hppe_host_tbl_rd_op_data9_data_get( - a_uint32_t dev_id, - unsigned int *value); - -sw_error_t -hppe_host_tbl_rd_op_data9_data_set( - a_uint32_t dev_id, - unsigned int value); - -sw_error_t -hppe_host_tbl_rd_op_rslt_op_rslt_get( - a_uint32_t dev_id, - unsigned int *value); - -sw_error_t -hppe_host_tbl_rd_op_rslt_op_rslt_set( - a_uint32_t dev_id, - unsigned int value); - -sw_error_t -hppe_host_tbl_rd_op_rslt_valid_cnt_get( - a_uint32_t dev_id, - unsigned int *value); - -sw_error_t -hppe_host_tbl_rd_op_rslt_valid_cnt_set( - a_uint32_t dev_id, - unsigned int value); - -sw_error_t -hppe_host_tbl_rd_op_rslt_entry_index_get( - a_uint32_t dev_id, - unsigned int *value); - -sw_error_t -hppe_host_tbl_rd_op_rslt_entry_index_set( - a_uint32_t dev_id, - unsigned int value); - -sw_error_t -hppe_host_tbl_rd_op_rslt_cmd_id_get( - a_uint32_t dev_id, - unsigned int *value); - -sw_error_t -hppe_host_tbl_rd_op_rslt_cmd_id_set( - a_uint32_t dev_id, - unsigned int value); - -sw_error_t -hppe_host_tbl_rd_rslt_data0_data_get( - a_uint32_t dev_id, - unsigned int *value); - -sw_error_t -hppe_host_tbl_rd_rslt_data0_data_set( - a_uint32_t dev_id, - unsigned int value); - -sw_error_t -hppe_host_tbl_rd_rslt_data1_data_get( - a_uint32_t dev_id, - unsigned int *value); - -sw_error_t -hppe_host_tbl_rd_rslt_data1_data_set( - a_uint32_t dev_id, - unsigned int value); - -sw_error_t -hppe_host_tbl_rd_rslt_data2_data_get( - a_uint32_t dev_id, - unsigned int *value); - -sw_error_t -hppe_host_tbl_rd_rslt_data2_data_set( - a_uint32_t dev_id, - unsigned int value); - -sw_error_t -hppe_host_tbl_rd_rslt_data3_data_get( - a_uint32_t dev_id, - unsigned int *value); - -sw_error_t -hppe_host_tbl_rd_rslt_data3_data_set( - a_uint32_t dev_id, - unsigned int value); - -sw_error_t -hppe_host_tbl_rd_rslt_data4_data_get( - a_uint32_t dev_id, - unsigned int *value); - -sw_error_t -hppe_host_tbl_rd_rslt_data4_data_set( - a_uint32_t dev_id, - unsigned int value); - -sw_error_t -hppe_host_tbl_rd_rslt_data5_data_get( - a_uint32_t dev_id, - unsigned int *value); - -sw_error_t -hppe_host_tbl_rd_rslt_data5_data_set( - a_uint32_t dev_id, - unsigned int value); - -sw_error_t -hppe_host_tbl_rd_rslt_data6_data_get( - a_uint32_t dev_id, - unsigned int *value); - -sw_error_t -hppe_host_tbl_rd_rslt_data6_data_set( - a_uint32_t dev_id, - unsigned int value); - -sw_error_t -hppe_host_tbl_rd_rslt_data7_data_get( - a_uint32_t dev_id, - unsigned int *value); - -sw_error_t -hppe_host_tbl_rd_rslt_data7_data_set( - a_uint32_t dev_id, - unsigned int value); - -sw_error_t -hppe_host_tbl_rd_rslt_data8_data_get( - a_uint32_t dev_id, - unsigned int *value); - -sw_error_t -hppe_host_tbl_rd_rslt_data8_data_set( - a_uint32_t dev_id, - unsigned int value); - -sw_error_t -hppe_host_tbl_rd_rslt_data9_data_get( - a_uint32_t dev_id, - unsigned int *value); - -sw_error_t -hppe_host_tbl_rd_rslt_data9_data_set( - a_uint32_t dev_id, - unsigned int value); - -sw_error_t -hppe_l3_dbg_cmd_type_get( - a_uint32_t dev_id, - unsigned int *value); - -sw_error_t -hppe_l3_dbg_cmd_type_set( - a_uint32_t dev_id, - unsigned int value); - -sw_error_t -hppe_l3_dbg_cmd_addr_get( - a_uint32_t dev_id, - unsigned int *value); - -sw_error_t -hppe_l3_dbg_cmd_addr_set( - a_uint32_t dev_id, - unsigned int value); - -sw_error_t -hppe_l3_dbg_wr_data_data_get( - a_uint32_t dev_id, - unsigned int *value); - -sw_error_t -hppe_l3_dbg_wr_data_data_set( - a_uint32_t dev_id, - unsigned int value); - -sw_error_t -hppe_l3_dbg_rd_data_data_get( - a_uint32_t dev_id, - unsigned int *value); - -sw_error_t -hppe_l3_dbg_rd_data_data_set( - a_uint32_t dev_id, - unsigned int value); - -sw_error_t -hppe_l3_vp_port_tbl_ip_arp_sg_en_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_l3_vp_port_tbl_ip_arp_sg_en_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_l3_vp_port_tbl_ipv6_sg_svlan_en_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_l3_vp_port_tbl_ipv6_sg_svlan_en_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_l3_vp_port_tbl_ip_nd_sg_cvlan_en_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_l3_vp_port_tbl_ip_nd_sg_cvlan_en_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_l3_vp_port_tbl_l3_if_valid_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_l3_vp_port_tbl_l3_if_valid_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_l3_vp_port_tbl_ip_nd_sg_vio_cmd_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_l3_vp_port_tbl_ip_nd_sg_vio_cmd_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_l3_vp_port_tbl_ipv4_sg_port_en_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_l3_vp_port_tbl_ipv4_sg_port_en_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_l3_vp_port_tbl_ip_nd_sg_en_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_l3_vp_port_tbl_ip_nd_sg_en_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_l3_vp_port_tbl_l3_if_index_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_l3_vp_port_tbl_l3_if_index_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_l3_vp_port_tbl_ipv4_sg_svlan_en_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_l3_vp_port_tbl_ipv4_sg_svlan_en_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_l3_vp_port_tbl_ipv4_sg_cvlan_en_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_l3_vp_port_tbl_ipv4_sg_cvlan_en_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_l3_vp_port_tbl_ip_arp_sg_svlan_en_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_l3_vp_port_tbl_ip_arp_sg_svlan_en_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_l3_vp_port_tbl_mac_valid_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_l3_vp_port_tbl_mac_valid_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_l3_vp_port_tbl_ip_nd_sg_svlan_en_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_l3_vp_port_tbl_ip_nd_sg_svlan_en_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_l3_vp_port_tbl_vsi_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_l3_vp_port_tbl_vsi_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_l3_vp_port_tbl_mac_da_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint64_t *value); - -sw_error_t -hppe_l3_vp_port_tbl_mac_da_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint64_t value); - -sw_error_t -hppe_l3_vp_port_tbl_ipv6_sg_vio_cmd_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_l3_vp_port_tbl_ipv6_sg_vio_cmd_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_l3_vp_port_tbl_ip_nd_sg_port_en_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_l3_vp_port_tbl_ip_nd_sg_port_en_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_l3_vp_port_tbl_ip_arp_src_unk_cmd_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_l3_vp_port_tbl_ip_arp_src_unk_cmd_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_l3_vp_port_tbl_ipv6_sg_port_en_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_l3_vp_port_tbl_ipv6_sg_port_en_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_l3_vp_port_tbl_ipv4_src_unk_cmd_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_l3_vp_port_tbl_ipv4_src_unk_cmd_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_l3_vp_port_tbl_ip_arp_sg_port_en_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_l3_vp_port_tbl_ip_arp_sg_port_en_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_l3_vp_port_tbl_ip_arp_sg_vio_cmd_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_l3_vp_port_tbl_ip_arp_sg_vio_cmd_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_l3_vp_port_tbl_ipv4_sg_vio_cmd_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_l3_vp_port_tbl_ipv4_sg_vio_cmd_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_l3_vp_port_tbl_ipv6_src_unk_cmd_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_l3_vp_port_tbl_ipv6_src_unk_cmd_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_l3_vp_port_tbl_ip_arp_sg_cvlan_en_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_l3_vp_port_tbl_ip_arp_sg_cvlan_en_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_l3_vp_port_tbl_ipv6_sg_en_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_l3_vp_port_tbl_ipv6_sg_en_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_l3_vp_port_tbl_vsi_valid_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_l3_vp_port_tbl_vsi_valid_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_l3_vp_port_tbl_ip_nd_src_unk_cmd_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_l3_vp_port_tbl_ip_nd_src_unk_cmd_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_l3_vp_port_tbl_ipv4_sg_en_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_l3_vp_port_tbl_ipv4_sg_en_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_l3_vp_port_tbl_ipv6_sg_cvlan_en_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_l3_vp_port_tbl_ipv6_sg_cvlan_en_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_in_l3_if_tbl_ttl_dec_bypass_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_in_l3_if_tbl_ttl_dec_bypass_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_in_l3_if_tbl_ttl_exceed_cmd_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_in_l3_if_tbl_ttl_exceed_cmd_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_in_l3_if_tbl_mru_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_in_l3_if_tbl_mru_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_in_l3_if_tbl_ipv4_uc_route_en_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_in_l3_if_tbl_ipv4_uc_route_en_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_in_l3_if_tbl_ipv6_uc_route_en_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_in_l3_if_tbl_ipv6_uc_route_en_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_in_l3_if_tbl_ttl_exceed_de_acce_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_in_l3_if_tbl_ttl_exceed_de_acce_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_in_l3_if_tbl_icmp_trigger_en_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_in_l3_if_tbl_icmp_trigger_en_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_in_l3_if_tbl_mac_bitmap_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_in_l3_if_tbl_mac_bitmap_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_in_l3_if_tbl_pppoe_en_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_in_l3_if_tbl_pppoe_en_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_in_l3_if_tbl_mtu_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_in_l3_if_tbl_mtu_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_in_nexthop_tbl_ip_pub_addr_index_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_in_nexthop_tbl_ip_pub_addr_index_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_in_nexthop_tbl_cvid_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_in_nexthop_tbl_cvid_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_in_nexthop_tbl_post_l3_if_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_in_nexthop_tbl_post_l3_if_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_in_nexthop_tbl_mac_addr_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint64_t *value); - -sw_error_t -hppe_in_nexthop_tbl_mac_addr_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint64_t value); - -sw_error_t -hppe_in_nexthop_tbl_port_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_in_nexthop_tbl_port_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_in_nexthop_tbl_ip_to_me_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_in_nexthop_tbl_ip_to_me_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_in_nexthop_tbl_ip_addr_dnat_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_in_nexthop_tbl_ip_addr_dnat_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_in_nexthop_tbl_type_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_in_nexthop_tbl_type_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_in_nexthop_tbl_stag_fmt_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_in_nexthop_tbl_stag_fmt_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_in_nexthop_tbl_vsi_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_in_nexthop_tbl_vsi_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_in_nexthop_tbl_svid_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_in_nexthop_tbl_svid_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_in_nexthop_tbl_ctag_fmt_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_in_nexthop_tbl_ctag_fmt_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_eg_l3_if_tbl_session_id_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_eg_l3_if_tbl_session_id_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_eg_l3_if_tbl_mac_addr_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint64_t *value); - -sw_error_t -hppe_eg_l3_if_tbl_mac_addr_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint64_t value); - -sw_error_t -hppe_eg_l3_if_tbl_pppoe_en_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_eg_l3_if_tbl_pppoe_en_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_in_pub_ip_addr_tbl_ip_addr_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_in_pub_ip_addr_tbl_ip_addr_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_rt_interface_cnt_tbl_byte_cnt_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint64_t *value); - -sw_error_t -hppe_rt_interface_cnt_tbl_byte_cnt_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint64_t value); - -sw_error_t -hppe_rt_interface_cnt_tbl_pkt_cnt_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_rt_interface_cnt_tbl_pkt_cnt_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_rt_interface_cnt_tbl_drop_byte_cnt_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint64_t *value); - -sw_error_t -hppe_rt_interface_cnt_tbl_drop_byte_cnt_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint64_t value); - -sw_error_t -hppe_rt_interface_cnt_tbl_drop_pkt_cnt_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_rt_interface_cnt_tbl_drop_pkt_cnt_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - - -sw_error_t -hppe_host_ipv4_add( - a_uint32_t dev_id, a_uint32_t op_mode, - a_uint32_t *index, union host_tbl_u *entry); - -sw_error_t -hppe_host_ipv6_add( - a_uint32_t dev_id, a_uint32_t op_mode, - a_uint32_t *index, union host_ipv6_tbl_u *entry); - -sw_error_t -hppe_host_ipv4_mcast_add( - a_uint32_t dev_id, a_uint32_t op_mode, - a_uint32_t *index, union host_ipv4_mcast_tbl_u *entry); - -sw_error_t -hppe_host_ipv6_mcast_add( - a_uint32_t dev_id, a_uint32_t op_mode, - a_uint32_t *index, union host_ipv6_mcast_tbl_u *entry); - -sw_error_t -hppe_host_ipv4_del( - a_uint32_t dev_id, a_uint32_t op_mode, - a_uint32_t *index, union host_tbl_u *entry); - -sw_error_t -hppe_host_ipv6_del( - a_uint32_t dev_id, a_uint32_t op_mode, - a_uint32_t *index, union host_ipv6_tbl_u *entry); - -sw_error_t -hppe_host_ipv4_mcast_del( - a_uint32_t dev_id, a_uint32_t op_mode, - a_uint32_t *index, union host_ipv4_mcast_tbl_u *entry); - -sw_error_t -hppe_host_ipv6_mcast_del( - a_uint32_t dev_id, a_uint32_t op_mode, - a_uint32_t *index, union host_ipv6_mcast_tbl_u *entry); - -sw_error_t -hppe_host_ipv4_get( - a_uint32_t dev_id, a_uint32_t op_mode, - a_uint32_t *index, union host_tbl_u *entry); - -sw_error_t -hppe_host_ipv6_get( - a_uint32_t dev_id, a_uint32_t op_mode, - a_uint32_t *index, union host_ipv6_tbl_u *entry); - -sw_error_t -hppe_host_ipv4_mcast_get( - a_uint32_t dev_id, a_uint32_t op_mode, - a_uint32_t *index, union host_ipv4_mcast_tbl_u *entry); - -sw_error_t -hppe_host_ipv6_mcast_get( - a_uint32_t dev_id, a_uint32_t op_mode, - a_uint32_t *index, union host_ipv6_mcast_tbl_u *entry); - -sw_error_t -hppe_host_flush_common(a_uint32_t dev_id); -#endif - -#endif diff --git a/feeds/ipq807x/qca-ssdk/src/include/hsl/hppe/hppe_ip_reg.h b/feeds/ipq807x/qca-ssdk/src/include/hsl/hppe/hppe_ip_reg.h deleted file mode 100755 index 31be3c355..000000000 --- a/feeds/ipq807x/qca-ssdk/src/include/hsl/hppe/hppe_ip_reg.h +++ /dev/null @@ -1,2240 +0,0 @@ -/* - * Copyright (c) 2016-2017, 2019, The Linux Foundation. All rights reserved. - * Permission to use, copy, modify, and/or distribute this software for - * any purpose with or without fee is hereby granted, provided that the - * above copyright notice and this permission notice appear in all copies. - * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES - * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR - * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES - * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN - * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT - * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. - */ - - -/** - * @defgroup - * @{ - */ -#ifndef _HPPE_IP_REG_H_ -#define _HPPE_IP_REG_H_ - -/*[table] MY_MAC_TBL*/ -#define MY_MAC_TBL -#define MY_MAC_TBL_ADDRESS 0x0 -#define MY_MAC_TBL_NUM 8 -#define MY_MAC_TBL_INC 0x8 -#define MY_MAC_TBL_TYPE REG_TYPE_RW -#define MY_MAC_TBL_DEFAULT 0x0 - /*[field] MAC_DA*/ - #define MY_MAC_TBL_MAC_DA - #define MY_MAC_TBL_MAC_DA_OFFSET 0 - #define MY_MAC_TBL_MAC_DA_LEN 48 - #define MY_MAC_TBL_MAC_DA_DEFAULT 0x0 - /*[field] VALID*/ - #define MY_MAC_TBL_VALID - #define MY_MAC_TBL_VALID_OFFSET 48 - #define MY_MAC_TBL_VALID_LEN 1 - #define MY_MAC_TBL_VALID_DEFAULT 0x0 - -struct my_mac_tbl { - a_uint32_t mac_da_0:32; - a_uint32_t mac_da_1:16; - a_uint32_t valid:1; - a_uint32_t _reserved0:15; -}; - -union my_mac_tbl_u { - a_uint32_t val[2]; - struct my_mac_tbl bf; -}; - -/*[register] L3_VSI*/ -#define L3_VSI -#define L3_VSI_ADDRESS 0x40 -#define L3_VSI_NUM 32 -#define L3_VSI_INC 0x4 -#define L3_VSI_TYPE REG_TYPE_RW -#define L3_VSI_DEFAULT 0x0 - /*[field] L3_IF_VALID*/ - #define L3_VSI_L3_IF_VALID - #define L3_VSI_L3_IF_VALID_OFFSET 0 - #define L3_VSI_L3_IF_VALID_LEN 1 - #define L3_VSI_L3_IF_VALID_DEFAULT 0x0 - /*[field] L3_IF_INDEX*/ - #define L3_VSI_L3_IF_INDEX - #define L3_VSI_L3_IF_INDEX_OFFSET 1 - #define L3_VSI_L3_IF_INDEX_LEN 8 - #define L3_VSI_L3_IF_INDEX_DEFAULT 0x0 - /*[field] L2_IPV4_MC_EN*/ - #define L3_VSI_L2_IPV4_MC_EN - #define L3_VSI_L2_IPV4_MC_EN_OFFSET 9 - #define L3_VSI_L2_IPV4_MC_EN_LEN 1 - #define L3_VSI_L2_IPV4_MC_EN_DEFAULT 0x0 - /*[field] L2_IPV4_MC_MODE*/ - #define L3_VSI_L2_IPV4_MC_MODE - #define L3_VSI_L2_IPV4_MC_MODE_OFFSET 10 - #define L3_VSI_L2_IPV4_MC_MODE_LEN 1 - #define L3_VSI_L2_IPV4_MC_MODE_DEFAULT 0x0 - /*[field] L2_IPV6_MC_EN*/ - #define L3_VSI_L2_IPV6_MC_EN - #define L3_VSI_L2_IPV6_MC_EN_OFFSET 11 - #define L3_VSI_L2_IPV6_MC_EN_LEN 1 - #define L3_VSI_L2_IPV6_MC_EN_DEFAULT 0x0 - /*[field] L2_IPV6_MC_MODE*/ - #define L3_VSI_L2_IPV6_MC_MODE - #define L3_VSI_L2_IPV6_MC_MODE_OFFSET 12 - #define L3_VSI_L2_IPV6_MC_MODE_LEN 1 - #define L3_VSI_L2_IPV6_MC_MODE_DEFAULT 0x0 - -struct l3_vsi { - a_uint32_t l3_if_valid:1; - a_uint32_t l3_if_index:8; - a_uint32_t l2_ipv4_mc_en:1; - a_uint32_t l2_ipv4_mc_mode:1; - a_uint32_t l2_ipv6_mc_en:1; - a_uint32_t l2_ipv6_mc_mode:1; - a_uint32_t _reserved0:19; -}; - -union l3_vsi_u { - a_uint32_t val; - struct l3_vsi bf; -}; - -/*[register] L3_VSI_EXT*/ -#define L3_VSI_EXT -#define L3_VSI_EXT_ADDRESS 0xc0 -#define L3_VSI_EXT_NUM 32 -#define L3_VSI_EXT_INC 0x4 -#define L3_VSI_EXT_TYPE REG_TYPE_RW -#define L3_VSI_EXT_DEFAULT 0x0 - /*[field] IPV4_SG_EN*/ - #define L3_VSI_EXT_IPV4_SG_EN - #define L3_VSI_EXT_IPV4_SG_EN_OFFSET 0 - #define L3_VSI_EXT_IPV4_SG_EN_LEN 1 - #define L3_VSI_EXT_IPV4_SG_EN_DEFAULT 0x0 - /*[field] IPV4_SG_VIO_CMD*/ - #define L3_VSI_EXT_IPV4_SG_VIO_CMD - #define L3_VSI_EXT_IPV4_SG_VIO_CMD_OFFSET 1 - #define L3_VSI_EXT_IPV4_SG_VIO_CMD_LEN 2 - #define L3_VSI_EXT_IPV4_SG_VIO_CMD_DEFAULT 0x0 - /*[field] IPV4_SG_PORT_EN*/ - #define L3_VSI_EXT_IPV4_SG_PORT_EN - #define L3_VSI_EXT_IPV4_SG_PORT_EN_OFFSET 3 - #define L3_VSI_EXT_IPV4_SG_PORT_EN_LEN 1 - #define L3_VSI_EXT_IPV4_SG_PORT_EN_DEFAULT 0x0 - /*[field] IPV4_SG_SVLAN_EN*/ - #define L3_VSI_EXT_IPV4_SG_SVLAN_EN - #define L3_VSI_EXT_IPV4_SG_SVLAN_EN_OFFSET 4 - #define L3_VSI_EXT_IPV4_SG_SVLAN_EN_LEN 1 - #define L3_VSI_EXT_IPV4_SG_SVLAN_EN_DEFAULT 0x0 - /*[field] IPV4_SG_CVLAN_EN*/ - #define L3_VSI_EXT_IPV4_SG_CVLAN_EN - #define L3_VSI_EXT_IPV4_SG_CVLAN_EN_OFFSET 5 - #define L3_VSI_EXT_IPV4_SG_CVLAN_EN_LEN 1 - #define L3_VSI_EXT_IPV4_SG_CVLAN_EN_DEFAULT 0x0 - /*[field] IPV4_SRC_UNK_CMD*/ - #define L3_VSI_EXT_IPV4_SRC_UNK_CMD - #define L3_VSI_EXT_IPV4_SRC_UNK_CMD_OFFSET 6 - #define L3_VSI_EXT_IPV4_SRC_UNK_CMD_LEN 2 - #define L3_VSI_EXT_IPV4_SRC_UNK_CMD_DEFAULT 0x0 - /*[field] IPV6_SG_EN*/ - #define L3_VSI_EXT_IPV6_SG_EN - #define L3_VSI_EXT_IPV6_SG_EN_OFFSET 8 - #define L3_VSI_EXT_IPV6_SG_EN_LEN 1 - #define L3_VSI_EXT_IPV6_SG_EN_DEFAULT 0x0 - /*[field] IPV6_SG_VIO_CMD*/ - #define L3_VSI_EXT_IPV6_SG_VIO_CMD - #define L3_VSI_EXT_IPV6_SG_VIO_CMD_OFFSET 9 - #define L3_VSI_EXT_IPV6_SG_VIO_CMD_LEN 2 - #define L3_VSI_EXT_IPV6_SG_VIO_CMD_DEFAULT 0x0 - /*[field] IPV6_SG_PORT_EN*/ - #define L3_VSI_EXT_IPV6_SG_PORT_EN - #define L3_VSI_EXT_IPV6_SG_PORT_EN_OFFSET 11 - #define L3_VSI_EXT_IPV6_SG_PORT_EN_LEN 1 - #define L3_VSI_EXT_IPV6_SG_PORT_EN_DEFAULT 0x0 - /*[field] IPV6_SG_SVLAN_EN*/ - #define L3_VSI_EXT_IPV6_SG_SVLAN_EN - #define L3_VSI_EXT_IPV6_SG_SVLAN_EN_OFFSET 12 - #define L3_VSI_EXT_IPV6_SG_SVLAN_EN_LEN 1 - #define L3_VSI_EXT_IPV6_SG_SVLAN_EN_DEFAULT 0x0 - /*[field] IPV6_SG_CVLAN_EN*/ - #define L3_VSI_EXT_IPV6_SG_CVLAN_EN - #define L3_VSI_EXT_IPV6_SG_CVLAN_EN_OFFSET 13 - #define L3_VSI_EXT_IPV6_SG_CVLAN_EN_LEN 1 - #define L3_VSI_EXT_IPV6_SG_CVLAN_EN_DEFAULT 0x0 - /*[field] IPV6_SRC_UNK_CMD*/ - #define L3_VSI_EXT_IPV6_SRC_UNK_CMD - #define L3_VSI_EXT_IPV6_SRC_UNK_CMD_OFFSET 14 - #define L3_VSI_EXT_IPV6_SRC_UNK_CMD_LEN 2 - #define L3_VSI_EXT_IPV6_SRC_UNK_CMD_DEFAULT 0x0 - /*[field] IP_ARP_SG_EN*/ - #define L3_VSI_EXT_IP_ARP_SG_EN - #define L3_VSI_EXT_IP_ARP_SG_EN_OFFSET 16 - #define L3_VSI_EXT_IP_ARP_SG_EN_LEN 1 - #define L3_VSI_EXT_IP_ARP_SG_EN_DEFAULT 0x0 - /*[field] IP_ARP_SG_VIO_CMD*/ - #define L3_VSI_EXT_IP_ARP_SG_VIO_CMD - #define L3_VSI_EXT_IP_ARP_SG_VIO_CMD_OFFSET 17 - #define L3_VSI_EXT_IP_ARP_SG_VIO_CMD_LEN 2 - #define L3_VSI_EXT_IP_ARP_SG_VIO_CMD_DEFAULT 0x0 - /*[field] IP_ARP_SG_PORT_EN*/ - #define L3_VSI_EXT_IP_ARP_SG_PORT_EN - #define L3_VSI_EXT_IP_ARP_SG_PORT_EN_OFFSET 19 - #define L3_VSI_EXT_IP_ARP_SG_PORT_EN_LEN 1 - #define L3_VSI_EXT_IP_ARP_SG_PORT_EN_DEFAULT 0x0 - /*[field] IP_ARP_SG_SVLAN_EN*/ - #define L3_VSI_EXT_IP_ARP_SG_SVLAN_EN - #define L3_VSI_EXT_IP_ARP_SG_SVLAN_EN_OFFSET 20 - #define L3_VSI_EXT_IP_ARP_SG_SVLAN_EN_LEN 1 - #define L3_VSI_EXT_IP_ARP_SG_SVLAN_EN_DEFAULT 0x0 - /*[field] IP_ARP_SG_CVLAN_EN*/ - #define L3_VSI_EXT_IP_ARP_SG_CVLAN_EN - #define L3_VSI_EXT_IP_ARP_SG_CVLAN_EN_OFFSET 21 - #define L3_VSI_EXT_IP_ARP_SG_CVLAN_EN_LEN 1 - #define L3_VSI_EXT_IP_ARP_SG_CVLAN_EN_DEFAULT 0x0 - /*[field] IP_ARP_SRC_UNK_CMD*/ - #define L3_VSI_EXT_IP_ARP_SRC_UNK_CMD - #define L3_VSI_EXT_IP_ARP_SRC_UNK_CMD_OFFSET 22 - #define L3_VSI_EXT_IP_ARP_SRC_UNK_CMD_LEN 2 - #define L3_VSI_EXT_IP_ARP_SRC_UNK_CMD_DEFAULT 0x0 - /*[field] IP_ND_SG_EN*/ - #define L3_VSI_EXT_IP_ND_SG_EN - #define L3_VSI_EXT_IP_ND_SG_EN_OFFSET 24 - #define L3_VSI_EXT_IP_ND_SG_EN_LEN 1 - #define L3_VSI_EXT_IP_ND_SG_EN_DEFAULT 0x0 - /*[field] IP_ND_SG_VIO_CMD*/ - #define L3_VSI_EXT_IP_ND_SG_VIO_CMD - #define L3_VSI_EXT_IP_ND_SG_VIO_CMD_OFFSET 25 - #define L3_VSI_EXT_IP_ND_SG_VIO_CMD_LEN 2 - #define L3_VSI_EXT_IP_ND_SG_VIO_CMD_DEFAULT 0x0 - /*[field] IP_ND_SG_PORT_EN*/ - #define L3_VSI_EXT_IP_ND_SG_PORT_EN - #define L3_VSI_EXT_IP_ND_SG_PORT_EN_OFFSET 27 - #define L3_VSI_EXT_IP_ND_SG_PORT_EN_LEN 1 - #define L3_VSI_EXT_IP_ND_SG_PORT_EN_DEFAULT 0x0 - /*[field] IP_ND_SG_SVLAN_EN*/ - #define L3_VSI_EXT_IP_ND_SG_SVLAN_EN - #define L3_VSI_EXT_IP_ND_SG_SVLAN_EN_OFFSET 28 - #define L3_VSI_EXT_IP_ND_SG_SVLAN_EN_LEN 1 - #define L3_VSI_EXT_IP_ND_SG_SVLAN_EN_DEFAULT 0x0 - /*[field] IP_ND_SG_CVLAN_EN*/ - #define L3_VSI_EXT_IP_ND_SG_CVLAN_EN - #define L3_VSI_EXT_IP_ND_SG_CVLAN_EN_OFFSET 29 - #define L3_VSI_EXT_IP_ND_SG_CVLAN_EN_LEN 1 - #define L3_VSI_EXT_IP_ND_SG_CVLAN_EN_DEFAULT 0x0 - /*[field] IP_ND_SRC_UNK_CMD*/ - #define L3_VSI_EXT_IP_ND_SRC_UNK_CMD - #define L3_VSI_EXT_IP_ND_SRC_UNK_CMD_OFFSET 30 - #define L3_VSI_EXT_IP_ND_SRC_UNK_CMD_LEN 2 - #define L3_VSI_EXT_IP_ND_SRC_UNK_CMD_DEFAULT 0x0 - -struct l3_vsi_ext { - a_uint32_t ipv4_sg_en:1; - a_uint32_t ipv4_sg_vio_cmd:2; - a_uint32_t ipv4_sg_port_en:1; - a_uint32_t ipv4_sg_svlan_en:1; - a_uint32_t ipv4_sg_cvlan_en:1; - a_uint32_t ipv4_src_unk_cmd:2; - a_uint32_t ipv6_sg_en:1; - a_uint32_t ipv6_sg_vio_cmd:2; - a_uint32_t ipv6_sg_port_en:1; - a_uint32_t ipv6_sg_svlan_en:1; - a_uint32_t ipv6_sg_cvlan_en:1; - a_uint32_t ipv6_src_unk_cmd:2; - a_uint32_t ip_arp_sg_en:1; - a_uint32_t ip_arp_sg_vio_cmd:2; - a_uint32_t ip_arp_sg_port_en:1; - a_uint32_t ip_arp_sg_svlan_en:1; - a_uint32_t ip_arp_sg_cvlan_en:1; - a_uint32_t ip_arp_src_unk_cmd:2; - a_uint32_t ip_nd_sg_en:1; - a_uint32_t ip_nd_sg_vio_cmd:2; - a_uint32_t ip_nd_sg_port_en:1; - a_uint32_t ip_nd_sg_svlan_en:1; - a_uint32_t ip_nd_sg_cvlan_en:1; - a_uint32_t ip_nd_src_unk_cmd:2; -}; - -union l3_vsi_ext_u { - a_uint32_t val; - struct l3_vsi_ext bf; -}; - -/*[register] NETWORK_ROUTE_IP*/ -#define NETWORK_ROUTE_IP -#define NETWORK_ROUTE_IP_ADDRESS 0x140 -#define NETWORK_ROUTE_IP_NUM 32 -#define NETWORK_ROUTE_IP_INC 0x8 -#define NETWORK_ROUTE_IP_TYPE REG_TYPE_RW -#define NETWORK_ROUTE_IP_DEFAULT 0x0 - /*[field] IP_ADDR*/ - #define NETWORK_ROUTE_IP_IP_ADDR - #define NETWORK_ROUTE_IP_IP_ADDR_OFFSET 0 - #define NETWORK_ROUTE_IP_IP_ADDR_LEN 32 - #define NETWORK_ROUTE_IP_IP_ADDR_DEFAULT 0x0 - /*[field] IP_ADDR_MASK*/ - #define NETWORK_ROUTE_IP_IP_ADDR_MASK - #define NETWORK_ROUTE_IP_IP_ADDR_MASK_OFFSET 32 - #define NETWORK_ROUTE_IP_IP_ADDR_MASK_LEN 32 - #define NETWORK_ROUTE_IP_IP_ADDR_MASK_DEFAULT 0x0 - -struct network_route_ip { - a_uint32_t ip_addr:32; - a_uint32_t ip_addr_mask:32; -}; - -union network_route_ip_u { - a_uint32_t val[2]; - struct network_route_ip bf; -}; - -/*[register] NETWORK_ROUTE_IP_EXT*/ -#define NETWORK_ROUTE_IP_EXT -#define NETWORK_ROUTE_IP_EXT_ADDRESS 0x240 -#define NETWORK_ROUTE_IP_EXT_NUM 32 -#define NETWORK_ROUTE_IP_EXT_INC 0x4 -#define NETWORK_ROUTE_IP_EXT_TYPE REG_TYPE_RW -#define NETWORK_ROUTE_IP_EXT_DEFAULT 0x0 - /*[field] VALID*/ - #define NETWORK_ROUTE_IP_EXT_VALID - #define NETWORK_ROUTE_IP_EXT_VALID_OFFSET 0 - #define NETWORK_ROUTE_IP_EXT_VALID_LEN 1 - #define NETWORK_ROUTE_IP_EXT_VALID_DEFAULT 0x0 - /*[field] ENTRY_TYPE*/ - #define NETWORK_ROUTE_IP_EXT_ENTRY_TYPE - #define NETWORK_ROUTE_IP_EXT_ENTRY_TYPE_OFFSET 1 - #define NETWORK_ROUTE_IP_EXT_ENTRY_TYPE_LEN 1 - #define NETWORK_ROUTE_IP_EXT_ENTRY_TYPE_DEFAULT 0x0 - -struct network_route_ip_ext { - a_uint32_t valid:1; - a_uint32_t entry_type:1; - a_uint32_t _reserved0:30; -}; - -union network_route_ip_ext_u { - a_uint32_t val; - struct network_route_ip_ext bf; -}; - -/*[register] NETWORK_ROUTE_ACTION*/ -#define NETWORK_ROUTE_ACTION -#define NETWORK_ROUTE_ACTION_ADDRESS 0x2c0 -#define NETWORK_ROUTE_ACTION_NUM 32 -#define NETWORK_ROUTE_ACTION_INC 0x4 -#define NETWORK_ROUTE_ACTION_TYPE REG_TYPE_RW -#define NETWORK_ROUTE_ACTION_DEFAULT 0x0 - /*[field] FWD_CMD*/ - #define NETWORK_ROUTE_ACTION_FWD_CMD - #define NETWORK_ROUTE_ACTION_FWD_CMD_OFFSET 0 - #define NETWORK_ROUTE_ACTION_FWD_CMD_LEN 2 - #define NETWORK_ROUTE_ACTION_FWD_CMD_DEFAULT 0x0 - /*[field] DST_INFO*/ - #define NETWORK_ROUTE_ACTION_DST_INFO - #define NETWORK_ROUTE_ACTION_DST_INFO_OFFSET 2 - #define NETWORK_ROUTE_ACTION_DST_INFO_LEN 14 - #define NETWORK_ROUTE_ACTION_DST_INFO_DEFAULT 0x0 - /*[field] LAN_WAN*/ - #define NETWORK_ROUTE_ACTION_LAN_WAN - #define NETWORK_ROUTE_ACTION_LAN_WAN_OFFSET 16 - #define NETWORK_ROUTE_ACTION_LAN_WAN_LEN 1 - #define NETWORK_ROUTE_ACTION_LAN_WAN_DEFAULT 0x0 - -struct network_route_action { - a_uint32_t fwd_cmd:2; - a_uint32_t dst_info:14; - a_uint32_t lan_wan:1; - a_uint32_t _reserved0:15; -}; - -union network_route_action_u { - a_uint32_t val; - struct network_route_action bf; -}; - -/*[register] L3_ROUTE_CTRL*/ -#define L3_ROUTE_CTRL -#define L3_ROUTE_CTRL_ADDRESS 0x340 -#define L3_ROUTE_CTRL_NUM 1 -#define L3_ROUTE_CTRL_INC 0x4 -#define L3_ROUTE_CTRL_TYPE REG_TYPE_RW -#define L3_ROUTE_CTRL_DEFAULT 0xdbc36db - /*[field] IP_MRU_CHECK_FAIL*/ - #define L3_ROUTE_CTRL_IP_MRU_CHECK_FAIL - #define L3_ROUTE_CTRL_IP_MRU_CHECK_FAIL_OFFSET 0 - #define L3_ROUTE_CTRL_IP_MRU_CHECK_FAIL_LEN 2 - #define L3_ROUTE_CTRL_IP_MRU_CHECK_FAIL_DEFAULT 0x3 - /*[field] IP_MRU_CHECK_FAIL_DE_ACCE*/ - #define L3_ROUTE_CTRL_IP_MRU_CHECK_FAIL_DE_ACCE - #define L3_ROUTE_CTRL_IP_MRU_CHECK_FAIL_DE_ACCE_OFFSET 2 - #define L3_ROUTE_CTRL_IP_MRU_CHECK_FAIL_DE_ACCE_LEN 1 - #define L3_ROUTE_CTRL_IP_MRU_CHECK_FAIL_DE_ACCE_DEFAULT 0x0 - /*[field] IP_MTU_FAIL*/ - #define L3_ROUTE_CTRL_IP_MTU_FAIL - #define L3_ROUTE_CTRL_IP_MTU_FAIL_OFFSET 3 - #define L3_ROUTE_CTRL_IP_MTU_FAIL_LEN 2 - #define L3_ROUTE_CTRL_IP_MTU_FAIL_DEFAULT 0x3 - /*[field] IP_MTU_FAIL_DE_ACCE*/ - #define L3_ROUTE_CTRL_IP_MTU_FAIL_DE_ACCE - #define L3_ROUTE_CTRL_IP_MTU_FAIL_DE_ACCE_OFFSET 5 - #define L3_ROUTE_CTRL_IP_MTU_FAIL_DE_ACCE_LEN 1 - #define L3_ROUTE_CTRL_IP_MTU_FAIL_DE_ACCE_DEFAULT 0x0 - /*[field] IP_MTU_DF_FAIL*/ - #define L3_ROUTE_CTRL_IP_MTU_DF_FAIL - #define L3_ROUTE_CTRL_IP_MTU_DF_FAIL_OFFSET 6 - #define L3_ROUTE_CTRL_IP_MTU_DF_FAIL_LEN 2 - #define L3_ROUTE_CTRL_IP_MTU_DF_FAIL_DEFAULT 0x3 - /*[field] IP_MTU_DF_FAIL_DE_ACCE*/ - #define L3_ROUTE_CTRL_IP_MTU_DF_FAIL_DE_ACCE - #define L3_ROUTE_CTRL_IP_MTU_DF_FAIL_DE_ACCE_OFFSET 8 - #define L3_ROUTE_CTRL_IP_MTU_DF_FAIL_DE_ACCE_LEN 1 - #define L3_ROUTE_CTRL_IP_MTU_DF_FAIL_DE_ACCE_DEFAULT 0x0 - /*[field] IP_PREFIX_BC_CMD*/ - #define L3_ROUTE_CTRL_IP_PREFIX_BC_CMD - #define L3_ROUTE_CTRL_IP_PREFIX_BC_CMD_OFFSET 9 - #define L3_ROUTE_CTRL_IP_PREFIX_BC_CMD_LEN 2 - #define L3_ROUTE_CTRL_IP_PREFIX_BC_CMD_DEFAULT 0x3 - /*[field] IP_PREFIX_BC_DE_ACCE*/ - #define L3_ROUTE_CTRL_IP_PREFIX_BC_DE_ACCE - #define L3_ROUTE_CTRL_IP_PREFIX_BC_DE_ACCE_OFFSET 11 - #define L3_ROUTE_CTRL_IP_PREFIX_BC_DE_ACCE_LEN 1 - #define L3_ROUTE_CTRL_IP_PREFIX_BC_DE_ACCE_DEFAULT 0x0 - /*[field] FLOW_SRC_IF_CHECK_CMD*/ - #define L3_ROUTE_CTRL_FLOW_SRC_IF_CHECK_CMD - #define L3_ROUTE_CTRL_FLOW_SRC_IF_CHECK_CMD_OFFSET 12 - #define L3_ROUTE_CTRL_FLOW_SRC_IF_CHECK_CMD_LEN 2 - #define L3_ROUTE_CTRL_FLOW_SRC_IF_CHECK_CMD_DEFAULT 0x3 - /*[field] FLOW_SRC_IF_CHECK_DE_ACCE*/ - #define L3_ROUTE_CTRL_FLOW_SRC_IF_CHECK_DE_ACCE - #define L3_ROUTE_CTRL_FLOW_SRC_IF_CHECK_DE_ACCE_OFFSET 14 - #define L3_ROUTE_CTRL_FLOW_SRC_IF_CHECK_DE_ACCE_LEN 1 - #define L3_ROUTE_CTRL_FLOW_SRC_IF_CHECK_DE_ACCE_DEFAULT 0x0 - /*[field] FLOW_SERVICE_CODE_LOOP*/ - #define L3_ROUTE_CTRL_FLOW_SERVICE_CODE_LOOP - #define L3_ROUTE_CTRL_FLOW_SERVICE_CODE_LOOP_OFFSET 15 - #define L3_ROUTE_CTRL_FLOW_SERVICE_CODE_LOOP_LEN 2 - #define L3_ROUTE_CTRL_FLOW_SERVICE_CODE_LOOP_DEFAULT 0x0 - /*[field] FLOW_SERVICE_CODE_LOOP_DE_ACCE*/ - #define L3_ROUTE_CTRL_FLOW_SERVICE_CODE_LOOP_DE_ACCE - #define L3_ROUTE_CTRL_FLOW_SERVICE_CODE_LOOP_DE_ACCE_OFFSET 17 - #define L3_ROUTE_CTRL_FLOW_SERVICE_CODE_LOOP_DE_ACCE_LEN 1 - #define L3_ROUTE_CTRL_FLOW_SERVICE_CODE_LOOP_DE_ACCE_DEFAULT 0x0 - /*[field] FLOW_DE_ACCE_CMD*/ - #define L3_ROUTE_CTRL_FLOW_DE_ACCE_CMD - #define L3_ROUTE_CTRL_FLOW_DE_ACCE_CMD_OFFSET 18 - #define L3_ROUTE_CTRL_FLOW_DE_ACCE_CMD_LEN 2 - #define L3_ROUTE_CTRL_FLOW_DE_ACCE_CMD_DEFAULT 0x3 - /*[field] FLOW_SYNC_MISMATCH_CMD*/ - #define L3_ROUTE_CTRL_FLOW_SYNC_MISMATCH_CMD - #define L3_ROUTE_CTRL_FLOW_SYNC_MISMATCH_CMD_OFFSET 20 - #define L3_ROUTE_CTRL_FLOW_SYNC_MISMATCH_CMD_LEN 2 - #define L3_ROUTE_CTRL_FLOW_SYNC_MISMATCH_CMD_DEFAULT 0x3 - /*[field] FLOW_SYNC_MISMATCH_DE_ACCE*/ - #define L3_ROUTE_CTRL_FLOW_SYNC_MISMATCH_DE_ACCE - #define L3_ROUTE_CTRL_FLOW_SYNC_MISMATCH_DE_ACCE_OFFSET 22 - #define L3_ROUTE_CTRL_FLOW_SYNC_MISMATCH_DE_ACCE_LEN 1 - #define L3_ROUTE_CTRL_FLOW_SYNC_MISMATCH_DE_ACCE_DEFAULT 0x0 - /*[field] ICMP_RDT_CMD*/ - #define L3_ROUTE_CTRL_ICMP_RDT_CMD - #define L3_ROUTE_CTRL_ICMP_RDT_CMD_OFFSET 23 - #define L3_ROUTE_CTRL_ICMP_RDT_CMD_LEN 2 - #define L3_ROUTE_CTRL_ICMP_RDT_CMD_DEFAULT 0x3 - /*[field] ICMP_RDT_DE_ACCE*/ - #define L3_ROUTE_CTRL_ICMP_RDT_DE_ACCE - #define L3_ROUTE_CTRL_ICMP_RDT_DE_ACCE_OFFSET 25 - #define L3_ROUTE_CTRL_ICMP_RDT_DE_ACCE_LEN 1 - #define L3_ROUTE_CTRL_ICMP_RDT_DE_ACCE_DEFAULT 0x0 - /*[field] PPPOE_MULTICAST_CMD*/ - #define L3_ROUTE_CTRL_PPPOE_MULTICAST_CMD - #define L3_ROUTE_CTRL_PPPOE_MULTICAST_CMD_OFFSET 26 - #define L3_ROUTE_CTRL_PPPOE_MULTICAST_CMD_LEN 2 - #define L3_ROUTE_CTRL_PPPOE_MULTICAST_CMD_DEFAULT 0x3 - /*[field] PPPOE_MULTICAST_DE_ACCE*/ - #define L3_ROUTE_CTRL_PPPOE_MULTICAST_DE_ACCE - #define L3_ROUTE_CTRL_PPPOE_MULTICAST_DE_ACCE_OFFSET 28 - #define L3_ROUTE_CTRL_PPPOE_MULTICAST_DE_ACCE_LEN 1 - #define L3_ROUTE_CTRL_PPPOE_MULTICAST_DE_ACCE_DEFAULT 0x0 - -struct l3_route_ctrl { - a_uint32_t ip_mru_check_fail:2; - a_uint32_t ip_mru_check_fail_de_acce:1; - a_uint32_t ip_mtu_fail:2; - a_uint32_t ip_mtu_fail_de_acce:1; - a_uint32_t ip_mtu_df_fail:2; - a_uint32_t ip_mtu_df_fail_de_acce:1; - a_uint32_t ip_prefix_bc_cmd:2; - a_uint32_t ip_prefix_bc_de_acce:1; - a_uint32_t flow_src_if_check_cmd:2; - a_uint32_t flow_src_if_check_de_acce:1; - a_uint32_t flow_service_code_loop:2; - a_uint32_t flow_service_code_loop_de_acce:1; - a_uint32_t flow_de_acce_cmd:2; - a_uint32_t flow_sync_mismatch_cmd:2; - a_uint32_t flow_sync_mismatch_de_acce:1; - a_uint32_t icmp_rdt_cmd:2; - a_uint32_t icmp_rdt_de_acce:1; - a_uint32_t pppoe_multicast_cmd:2; - a_uint32_t pppoe_multicast_de_acce:1; - a_uint32_t _reserved0:3; -}; - -union l3_route_ctrl_u { - a_uint32_t val; - struct l3_route_ctrl bf; -}; - -/*[register] L3_ROUTE_CTRL_EXT*/ -#define L3_ROUTE_CTRL_EXT -#define L3_ROUTE_CTRL_EXT_ADDRESS 0x344 -#define L3_ROUTE_CTRL_EXT_NUM 1 -#define L3_ROUTE_CTRL_EXT_INC 0x4 -#define L3_ROUTE_CTRL_EXT_TYPE REG_TYPE_RW -#define L3_ROUTE_CTRL_EXT_DEFAULT 0x23 - /*[field] IP_ROUTE_MISMATCH*/ - #define L3_ROUTE_CTRL_EXT_IP_ROUTE_MISMATCH - #define L3_ROUTE_CTRL_EXT_IP_ROUTE_MISMATCH_OFFSET 0 - #define L3_ROUTE_CTRL_EXT_IP_ROUTE_MISMATCH_LEN 2 - #define L3_ROUTE_CTRL_EXT_IP_ROUTE_MISMATCH_DEFAULT 0x3 - /*[field] FLOW_SERVICE_CODE_LOOP_EN*/ - #define L3_ROUTE_CTRL_EXT_FLOW_SERVICE_CODE_LOOP_EN - #define L3_ROUTE_CTRL_EXT_FLOW_SERVICE_CODE_LOOP_EN_OFFSET 2 - #define L3_ROUTE_CTRL_EXT_FLOW_SERVICE_CODE_LOOP_EN_LEN 1 - #define L3_ROUTE_CTRL_EXT_FLOW_SERVICE_CODE_LOOP_EN_DEFAULT 0x0 - /*[field] HOST_HASH_MODE_0*/ - #define L3_ROUTE_CTRL_EXT_HOST_HASH_MODE_0 - #define L3_ROUTE_CTRL_EXT_HOST_HASH_MODE_0_OFFSET 3 - #define L3_ROUTE_CTRL_EXT_HOST_HASH_MODE_0_LEN 2 - #define L3_ROUTE_CTRL_EXT_HOST_HASH_MODE_0_DEFAULT 0x0 - /*[field] HOST_HASH_MODE_1*/ - #define L3_ROUTE_CTRL_EXT_HOST_HASH_MODE_1 - #define L3_ROUTE_CTRL_EXT_HOST_HASH_MODE_1_OFFSET 5 - #define L3_ROUTE_CTRL_EXT_HOST_HASH_MODE_1_LEN 2 - #define L3_ROUTE_CTRL_EXT_HOST_HASH_MODE_1_DEFAULT 0x1 - -struct l3_route_ctrl_ext { - a_uint32_t ip_route_mismatch:2; - a_uint32_t flow_service_code_loop_en:1; - a_uint32_t host_hash_mode_0:2; - a_uint32_t host_hash_mode_1:2; - a_uint32_t l3_flow_copy_escape:1; - a_uint32_t _reserved0:24; -}; - -union l3_route_ctrl_ext_u { - a_uint32_t val; - struct l3_route_ctrl_ext bf; -}; - -/*[register] HOST_TBL_OP*/ -#define HOST_TBL_OP -#define HOST_TBL_OP_ADDRESS 0x4bc -#define HOST_TBL_OP_NUM 1 -#define HOST_TBL_OP_INC 0x4 -#define HOST_TBL_OP_TYPE REG_TYPE_RW -#define HOST_TBL_OP_DEFAULT 0x0 - /*[field] CMD_ID*/ - #define HOST_TBL_OP_CMD_ID - #define HOST_TBL_OP_CMD_ID_OFFSET 0 - #define HOST_TBL_OP_CMD_ID_LEN 4 - #define HOST_TBL_OP_CMD_ID_DEFAULT 0x0 - /*[field] BYP_RSLT_EN*/ - #define HOST_TBL_OP_BYP_RSLT_EN - #define HOST_TBL_OP_BYP_RSLT_EN_OFFSET 4 - #define HOST_TBL_OP_BYP_RSLT_EN_LEN 1 - #define HOST_TBL_OP_BYP_RSLT_EN_DEFAULT 0x0 - /*[field] OP_TYPE*/ - #define HOST_TBL_OP_OP_TYPE - #define HOST_TBL_OP_OP_TYPE_OFFSET 5 - #define HOST_TBL_OP_OP_TYPE_LEN 3 - #define HOST_TBL_OP_OP_TYPE_DEFAULT 0x0 - /*[field] HASH_BLOCK_BITMAP*/ - #define HOST_TBL_OP_HASH_BLOCK_BITMAP - #define HOST_TBL_OP_HASH_BLOCK_BITMAP_OFFSET 8 - #define HOST_TBL_OP_HASH_BLOCK_BITMAP_LEN 2 - #define HOST_TBL_OP_HASH_BLOCK_BITMAP_DEFAULT 0x0 - /*[field] OP_MODE*/ - #define HOST_TBL_OP_OP_MODE - #define HOST_TBL_OP_OP_MODE_OFFSET 10 - #define HOST_TBL_OP_OP_MODE_LEN 1 - #define HOST_TBL_OP_OP_MODE_DEFAULT 0x0 - /*[field] ENTRY_INDEX*/ - #define HOST_TBL_OP_ENTRY_INDEX - #define HOST_TBL_OP_ENTRY_INDEX_OFFSET 11 - #define HOST_TBL_OP_ENTRY_INDEX_LEN 13 - #define HOST_TBL_OP_ENTRY_INDEX_DEFAULT 0x0 - /*[field] OP_RESULT*/ - #define HOST_TBL_OP_OP_RESULT - #define HOST_TBL_OP_OP_RESULT_OFFSET 24 - #define HOST_TBL_OP_OP_RESULT_LEN 1 - #define HOST_TBL_OP_OP_RESULT_DEFAULT 0x0 - /*[field] BUSY*/ - #define HOST_TBL_OP_BUSY - #define HOST_TBL_OP_BUSY_OFFSET 25 - #define HOST_TBL_OP_BUSY_LEN 1 - #define HOST_TBL_OP_BUSY_DEFAULT 0x0 - -struct host_tbl_op { - a_uint32_t cmd_id:4; - a_uint32_t byp_rslt_en:1; - a_uint32_t op_type:3; - a_uint32_t hash_block_bitmap:2; - a_uint32_t op_mode:1; - a_uint32_t entry_index:13; - a_uint32_t op_result:1; - a_uint32_t busy:1; - a_uint32_t _reserved0:6; -}; - -union host_tbl_op_u { - a_uint32_t val; - struct host_tbl_op bf; -}; - -/*[register] HOST_TBL_OP_DATA0*/ -#define HOST_TBL_OP_DATA0 -#define HOST_TBL_OP_DATA0_ADDRESS 0x4c0 -#define HOST_TBL_OP_DATA0_NUM 1 -#define HOST_TBL_OP_DATA0_INC 0x4 -#define HOST_TBL_OP_DATA0_TYPE REG_TYPE_RW -#define HOST_TBL_OP_DATA0_DEFAULT 0x0 - /*[field] DATA*/ - #define HOST_TBL_OP_DATA0_DATA - #define HOST_TBL_OP_DATA0_DATA_OFFSET 0 - #define HOST_TBL_OP_DATA0_DATA_LEN 32 - #define HOST_TBL_OP_DATA0_DATA_DEFAULT 0x0 - -struct host_tbl_op_data0 { - a_uint32_t data:32; -}; - -union host_tbl_op_data0_u { - a_uint32_t val; - struct host_tbl_op_data0 bf; -}; - -/*[register] HOST_TBL_OP_DATA1*/ -#define HOST_TBL_OP_DATA1 -#define HOST_TBL_OP_DATA1_ADDRESS 0x4c4 -#define HOST_TBL_OP_DATA1_NUM 1 -#define HOST_TBL_OP_DATA1_INC 0x4 -#define HOST_TBL_OP_DATA1_TYPE REG_TYPE_RW -#define HOST_TBL_OP_DATA1_DEFAULT 0x0 - /*[field] DATA*/ - #define HOST_TBL_OP_DATA1_DATA - #define HOST_TBL_OP_DATA1_DATA_OFFSET 0 - #define HOST_TBL_OP_DATA1_DATA_LEN 32 - #define HOST_TBL_OP_DATA1_DATA_DEFAULT 0x0 - -struct host_tbl_op_data1 { - a_uint32_t data:32; -}; - -union host_tbl_op_data1_u { - a_uint32_t val; - struct host_tbl_op_data1 bf; -}; - -/*[register] HOST_TBL_OP_DATA2*/ -#define HOST_TBL_OP_DATA2 -#define HOST_TBL_OP_DATA2_ADDRESS 0x4c8 -#define HOST_TBL_OP_DATA2_NUM 1 -#define HOST_TBL_OP_DATA2_INC 0x4 -#define HOST_TBL_OP_DATA2_TYPE REG_TYPE_RW -#define HOST_TBL_OP_DATA2_DEFAULT 0x0 - /*[field] DATA*/ - #define HOST_TBL_OP_DATA2_DATA - #define HOST_TBL_OP_DATA2_DATA_OFFSET 0 - #define HOST_TBL_OP_DATA2_DATA_LEN 32 - #define HOST_TBL_OP_DATA2_DATA_DEFAULT 0x0 - -struct host_tbl_op_data2 { - a_uint32_t data:32; -}; - -union host_tbl_op_data2_u { - a_uint32_t val; - struct host_tbl_op_data2 bf; -}; - -/*[register] HOST_TBL_OP_DATA3*/ -#define HOST_TBL_OP_DATA3 -#define HOST_TBL_OP_DATA3_ADDRESS 0x4cc -#define HOST_TBL_OP_DATA3_NUM 1 -#define HOST_TBL_OP_DATA3_INC 0x4 -#define HOST_TBL_OP_DATA3_TYPE REG_TYPE_RW -#define HOST_TBL_OP_DATA3_DEFAULT 0x0 - /*[field] DATA*/ - #define HOST_TBL_OP_DATA3_DATA - #define HOST_TBL_OP_DATA3_DATA_OFFSET 0 - #define HOST_TBL_OP_DATA3_DATA_LEN 32 - #define HOST_TBL_OP_DATA3_DATA_DEFAULT 0x0 - -struct host_tbl_op_data3 { - a_uint32_t data:32; -}; - -union host_tbl_op_data3_u { - a_uint32_t val; - struct host_tbl_op_data3 bf; -}; - -/*[register] HOST_TBL_OP_DATA4*/ -#define HOST_TBL_OP_DATA4 -#define HOST_TBL_OP_DATA4_ADDRESS 0x4d0 -#define HOST_TBL_OP_DATA4_NUM 1 -#define HOST_TBL_OP_DATA4_INC 0x4 -#define HOST_TBL_OP_DATA4_TYPE REG_TYPE_RW -#define HOST_TBL_OP_DATA4_DEFAULT 0x0 - /*[field] DATA*/ - #define HOST_TBL_OP_DATA4_DATA - #define HOST_TBL_OP_DATA4_DATA_OFFSET 0 - #define HOST_TBL_OP_DATA4_DATA_LEN 32 - #define HOST_TBL_OP_DATA4_DATA_DEFAULT 0x0 - -struct host_tbl_op_data4 { - a_uint32_t data:32; -}; - -union host_tbl_op_data4_u { - a_uint32_t val; - struct host_tbl_op_data4 bf; -}; - -/*[register] HOST_TBL_OP_DATA5*/ -#define HOST_TBL_OP_DATA5 -#define HOST_TBL_OP_DATA5_ADDRESS 0x4d4 -#define HOST_TBL_OP_DATA5_NUM 1 -#define HOST_TBL_OP_DATA5_INC 0x4 -#define HOST_TBL_OP_DATA5_TYPE REG_TYPE_RW -#define HOST_TBL_OP_DATA5_DEFAULT 0x0 - /*[field] DATA*/ - #define HOST_TBL_OP_DATA5_DATA - #define HOST_TBL_OP_DATA5_DATA_OFFSET 0 - #define HOST_TBL_OP_DATA5_DATA_LEN 32 - #define HOST_TBL_OP_DATA5_DATA_DEFAULT 0x0 - -struct host_tbl_op_data5 { - a_uint32_t data:32; -}; - -union host_tbl_op_data5_u { - a_uint32_t val; - struct host_tbl_op_data5 bf; -}; - -/*[register] HOST_TBL_OP_DATA6*/ -#define HOST_TBL_OP_DATA6 -#define HOST_TBL_OP_DATA6_ADDRESS 0x4d8 -#define HOST_TBL_OP_DATA6_NUM 1 -#define HOST_TBL_OP_DATA6_INC 0x4 -#define HOST_TBL_OP_DATA6_TYPE REG_TYPE_RW -#define HOST_TBL_OP_DATA6_DEFAULT 0x0 - /*[field] DATA*/ - #define HOST_TBL_OP_DATA6_DATA - #define HOST_TBL_OP_DATA6_DATA_OFFSET 0 - #define HOST_TBL_OP_DATA6_DATA_LEN 32 - #define HOST_TBL_OP_DATA6_DATA_DEFAULT 0x0 - -struct host_tbl_op_data6 { - a_uint32_t data:32; -}; - -union host_tbl_op_data6_u { - a_uint32_t val; - struct host_tbl_op_data6 bf; -}; - -/*[register] HOST_TBL_OP_DATA7*/ -#define HOST_TBL_OP_DATA7 -#define HOST_TBL_OP_DATA7_ADDRESS 0x4dc -#define HOST_TBL_OP_DATA7_NUM 1 -#define HOST_TBL_OP_DATA7_INC 0x4 -#define HOST_TBL_OP_DATA7_TYPE REG_TYPE_RW -#define HOST_TBL_OP_DATA7_DEFAULT 0x0 - /*[field] DATA*/ - #define HOST_TBL_OP_DATA7_DATA - #define HOST_TBL_OP_DATA7_DATA_OFFSET 0 - #define HOST_TBL_OP_DATA7_DATA_LEN 32 - #define HOST_TBL_OP_DATA7_DATA_DEFAULT 0x0 - -struct host_tbl_op_data7 { - a_uint32_t data:32; -}; - -union host_tbl_op_data7_u { - a_uint32_t val; - struct host_tbl_op_data7 bf; -}; - -/*[register] HOST_TBL_OP_DATA8*/ -#define HOST_TBL_OP_DATA8 -#define HOST_TBL_OP_DATA8_ADDRESS 0x4e0 -#define HOST_TBL_OP_DATA8_NUM 1 -#define HOST_TBL_OP_DATA8_INC 0x4 -#define HOST_TBL_OP_DATA8_TYPE REG_TYPE_RW -#define HOST_TBL_OP_DATA8_DEFAULT 0x0 - /*[field] DATA*/ - #define HOST_TBL_OP_DATA8_DATA - #define HOST_TBL_OP_DATA8_DATA_OFFSET 0 - #define HOST_TBL_OP_DATA8_DATA_LEN 32 - #define HOST_TBL_OP_DATA8_DATA_DEFAULT 0x0 - -struct host_tbl_op_data8 { - a_uint32_t data:32; -}; - -union host_tbl_op_data8_u { - a_uint32_t val; - struct host_tbl_op_data8 bf; -}; - -/*[register] HOST_TBL_OP_DATA9*/ -#define HOST_TBL_OP_DATA9 -#define HOST_TBL_OP_DATA9_ADDRESS 0x4e4 -#define HOST_TBL_OP_DATA9_NUM 1 -#define HOST_TBL_OP_DATA9_INC 0x4 -#define HOST_TBL_OP_DATA9_TYPE REG_TYPE_RW -#define HOST_TBL_OP_DATA9_DEFAULT 0x0 - /*[field] DATA*/ - #define HOST_TBL_OP_DATA9_DATA - #define HOST_TBL_OP_DATA9_DATA_OFFSET 0 - #define HOST_TBL_OP_DATA9_DATA_LEN 32 - #define HOST_TBL_OP_DATA9_DATA_DEFAULT 0x0 - -struct host_tbl_op_data9 { - a_uint32_t data:32; -}; - -union host_tbl_op_data9_u { - a_uint32_t val; - struct host_tbl_op_data9 bf; -}; - -/*[register] HOST_TBL_OP_RSLT*/ -#define HOST_TBL_OP_RSLT -#define HOST_TBL_OP_RSLT_ADDRESS 0x4e8 -#define HOST_TBL_OP_RSLT_NUM 1 -#define HOST_TBL_OP_RSLT_INC 0x4 -#define HOST_TBL_OP_RSLT_TYPE REG_TYPE_RO -#define HOST_TBL_OP_RSLT_DEFAULT 0x0 - /*[field] CMD_ID*/ - #define HOST_TBL_OP_RSLT_CMD_ID - #define HOST_TBL_OP_RSLT_CMD_ID_OFFSET 0 - #define HOST_TBL_OP_RSLT_CMD_ID_LEN 4 - #define HOST_TBL_OP_RSLT_CMD_ID_DEFAULT 0x0 - /*[field] OP_RSLT*/ - #define HOST_TBL_OP_RSLT_OP_RSLT - #define HOST_TBL_OP_RSLT_OP_RSLT_OFFSET 4 - #define HOST_TBL_OP_RSLT_OP_RSLT_LEN 1 - #define HOST_TBL_OP_RSLT_OP_RSLT_DEFAULT 0x0 - /*[field] ENTRY_INDEX*/ - #define HOST_TBL_OP_RSLT_ENTRY_INDEX - #define HOST_TBL_OP_RSLT_ENTRY_INDEX_OFFSET 5 - #define HOST_TBL_OP_RSLT_ENTRY_INDEX_LEN 13 - #define HOST_TBL_OP_RSLT_ENTRY_INDEX_DEFAULT 0x0 - /*[field] VALID_CNT*/ - #define HOST_TBL_OP_RSLT_VALID_CNT - #define HOST_TBL_OP_RSLT_VALID_CNT_OFFSET 18 - #define HOST_TBL_OP_RSLT_VALID_CNT_LEN 4 - #define HOST_TBL_OP_RSLT_VALID_CNT_DEFAULT 0x0 - -struct host_tbl_op_rslt { - a_uint32_t cmd_id:4; - a_uint32_t op_rslt:1; - a_uint32_t entry_index:13; - a_uint32_t valid_cnt:4; - a_uint32_t _reserved0:10; -}; - -union host_tbl_op_rslt_u { - a_uint32_t val; - struct host_tbl_op_rslt bf; -}; - -/*[register] HOST_TBL_RD_OP*/ -#define HOST_TBL_RD_OP -#define HOST_TBL_RD_OP_ADDRESS 0x4ec -#define HOST_TBL_RD_OP_NUM 1 -#define HOST_TBL_RD_OP_INC 0x4 -#define HOST_TBL_RD_OP_TYPE REG_TYPE_RW -#define HOST_TBL_RD_OP_DEFAULT 0x0 - /*[field] CMD_ID*/ - #define HOST_TBL_RD_OP_CMD_ID - #define HOST_TBL_RD_OP_CMD_ID_OFFSET 0 - #define HOST_TBL_RD_OP_CMD_ID_LEN 4 - #define HOST_TBL_RD_OP_CMD_ID_DEFAULT 0x0 - /*[field] BYP_RSLT_EN*/ - #define HOST_TBL_RD_OP_BYP_RSLT_EN - #define HOST_TBL_RD_OP_BYP_RSLT_EN_OFFSET 4 - #define HOST_TBL_RD_OP_BYP_RSLT_EN_LEN 1 - #define HOST_TBL_RD_OP_BYP_RSLT_EN_DEFAULT 0x0 - /*[field] OP_TYPE*/ - #define HOST_TBL_RD_OP_OP_TYPE - #define HOST_TBL_RD_OP_OP_TYPE_OFFSET 5 - #define HOST_TBL_RD_OP_OP_TYPE_LEN 3 - #define HOST_TBL_RD_OP_OP_TYPE_DEFAULT 0x0 - /*[field] HASH_BLOCK_BITMAP*/ - #define HOST_TBL_RD_OP_HASH_BLOCK_BITMAP - #define HOST_TBL_RD_OP_HASH_BLOCK_BITMAP_OFFSET 8 - #define HOST_TBL_RD_OP_HASH_BLOCK_BITMAP_LEN 2 - #define HOST_TBL_RD_OP_HASH_BLOCK_BITMAP_DEFAULT 0x0 - /*[field] OP_MODE*/ - #define HOST_TBL_RD_OP_OP_MODE - #define HOST_TBL_RD_OP_OP_MODE_OFFSET 10 - #define HOST_TBL_RD_OP_OP_MODE_LEN 1 - #define HOST_TBL_RD_OP_OP_MODE_DEFAULT 0x0 - /*[field] ENTRY_INDEX*/ - #define HOST_TBL_RD_OP_ENTRY_INDEX - #define HOST_TBL_RD_OP_ENTRY_INDEX_OFFSET 11 - #define HOST_TBL_RD_OP_ENTRY_INDEX_LEN 13 - #define HOST_TBL_RD_OP_ENTRY_INDEX_DEFAULT 0x0 - /*[field] OP_RESULT*/ - #define HOST_TBL_RD_OP_OP_RESULT - #define HOST_TBL_RD_OP_OP_RESULT_OFFSET 24 - #define HOST_TBL_RD_OP_OP_RESULT_LEN 1 - #define HOST_TBL_RD_OP_OP_RESULT_DEFAULT 0x0 - /*[field] BUSY*/ - #define HOST_TBL_RD_OP_BUSY - #define HOST_TBL_RD_OP_BUSY_OFFSET 25 - #define HOST_TBL_RD_OP_BUSY_LEN 1 - #define HOST_TBL_RD_OP_BUSY_DEFAULT 0x0 - -struct host_tbl_rd_op { - a_uint32_t cmd_id:4; - a_uint32_t byp_rslt_en:1; - a_uint32_t op_type:3; - a_uint32_t hash_block_bitmap:2; - a_uint32_t op_mode:1; - a_uint32_t entry_index:13; - a_uint32_t op_result:1; - a_uint32_t busy:1; - a_uint32_t _reserved0:6; -}; - -union host_tbl_rd_op_u { - a_uint32_t val; - struct host_tbl_rd_op bf; -}; - -/*[register] HOST_TBL_RD_OP_DATA0*/ -#define HOST_TBL_RD_OP_DATA0 -#define HOST_TBL_RD_OP_DATA0_ADDRESS 0x4f0 -#define HOST_TBL_RD_OP_DATA0_NUM 1 -#define HOST_TBL_RD_OP_DATA0_INC 0x4 -#define HOST_TBL_RD_OP_DATA0_TYPE REG_TYPE_RW -#define HOST_TBL_RD_OP_DATA0_DEFAULT 0x0 - /*[field] DATA*/ - #define HOST_TBL_RD_OP_DATA0_DATA - #define HOST_TBL_RD_OP_DATA0_DATA_OFFSET 0 - #define HOST_TBL_RD_OP_DATA0_DATA_LEN 32 - #define HOST_TBL_RD_OP_DATA0_DATA_DEFAULT 0x0 - -struct host_tbl_rd_op_data0 { - a_uint32_t data:32; -}; - -union host_tbl_rd_op_data0_u { - a_uint32_t val; - struct host_tbl_rd_op_data0 bf; -}; - -/*[register] HOST_TBL_RD_OP_DATA1*/ -#define HOST_TBL_RD_OP_DATA1 -#define HOST_TBL_RD_OP_DATA1_ADDRESS 0x4f4 -#define HOST_TBL_RD_OP_DATA1_NUM 1 -#define HOST_TBL_RD_OP_DATA1_INC 0x4 -#define HOST_TBL_RD_OP_DATA1_TYPE REG_TYPE_RW -#define HOST_TBL_RD_OP_DATA1_DEFAULT 0x0 - /*[field] DATA*/ - #define HOST_TBL_RD_OP_DATA1_DATA - #define HOST_TBL_RD_OP_DATA1_DATA_OFFSET 0 - #define HOST_TBL_RD_OP_DATA1_DATA_LEN 32 - #define HOST_TBL_RD_OP_DATA1_DATA_DEFAULT 0x0 - -struct host_tbl_rd_op_data1 { - a_uint32_t data:32; -}; - -union host_tbl_rd_op_data1_u { - a_uint32_t val; - struct host_tbl_rd_op_data1 bf; -}; - -/*[register] HOST_TBL_RD_OP_DATA2*/ -#define HOST_TBL_RD_OP_DATA2 -#define HOST_TBL_RD_OP_DATA2_ADDRESS 0x4f8 -#define HOST_TBL_RD_OP_DATA2_NUM 1 -#define HOST_TBL_RD_OP_DATA2_INC 0x4 -#define HOST_TBL_RD_OP_DATA2_TYPE REG_TYPE_RW -#define HOST_TBL_RD_OP_DATA2_DEFAULT 0x0 - /*[field] DATA*/ - #define HOST_TBL_RD_OP_DATA2_DATA - #define HOST_TBL_RD_OP_DATA2_DATA_OFFSET 0 - #define HOST_TBL_RD_OP_DATA2_DATA_LEN 32 - #define HOST_TBL_RD_OP_DATA2_DATA_DEFAULT 0x0 - -struct host_tbl_rd_op_data2 { - a_uint32_t data:32; -}; - -union host_tbl_rd_op_data2_u { - a_uint32_t val; - struct host_tbl_rd_op_data2 bf; -}; - -/*[register] HOST_TBL_RD_OP_DATA3*/ -#define HOST_TBL_RD_OP_DATA3 -#define HOST_TBL_RD_OP_DATA3_ADDRESS 0x4fc -#define HOST_TBL_RD_OP_DATA3_NUM 1 -#define HOST_TBL_RD_OP_DATA3_INC 0x4 -#define HOST_TBL_RD_OP_DATA3_TYPE REG_TYPE_RW -#define HOST_TBL_RD_OP_DATA3_DEFAULT 0x0 - /*[field] DATA*/ - #define HOST_TBL_RD_OP_DATA3_DATA - #define HOST_TBL_RD_OP_DATA3_DATA_OFFSET 0 - #define HOST_TBL_RD_OP_DATA3_DATA_LEN 32 - #define HOST_TBL_RD_OP_DATA3_DATA_DEFAULT 0x0 - -struct host_tbl_rd_op_data3 { - a_uint32_t data:32; -}; - -union host_tbl_rd_op_data3_u { - a_uint32_t val; - struct host_tbl_rd_op_data3 bf; -}; - -/*[register] HOST_TBL_RD_OP_DATA4*/ -#define HOST_TBL_RD_OP_DATA4 -#define HOST_TBL_RD_OP_DATA4_ADDRESS 0x500 -#define HOST_TBL_RD_OP_DATA4_NUM 1 -#define HOST_TBL_RD_OP_DATA4_INC 0x4 -#define HOST_TBL_RD_OP_DATA4_TYPE REG_TYPE_RW -#define HOST_TBL_RD_OP_DATA4_DEFAULT 0x0 - /*[field] DATA*/ - #define HOST_TBL_RD_OP_DATA4_DATA - #define HOST_TBL_RD_OP_DATA4_DATA_OFFSET 0 - #define HOST_TBL_RD_OP_DATA4_DATA_LEN 32 - #define HOST_TBL_RD_OP_DATA4_DATA_DEFAULT 0x0 - -struct host_tbl_rd_op_data4 { - a_uint32_t data:32; -}; - -union host_tbl_rd_op_data4_u { - a_uint32_t val; - struct host_tbl_rd_op_data4 bf; -}; - -/*[register] HOST_TBL_RD_OP_DATA5*/ -#define HOST_TBL_RD_OP_DATA5 -#define HOST_TBL_RD_OP_DATA5_ADDRESS 0x504 -#define HOST_TBL_RD_OP_DATA5_NUM 1 -#define HOST_TBL_RD_OP_DATA5_INC 0x4 -#define HOST_TBL_RD_OP_DATA5_TYPE REG_TYPE_RW -#define HOST_TBL_RD_OP_DATA5_DEFAULT 0x0 - /*[field] DATA*/ - #define HOST_TBL_RD_OP_DATA5_DATA - #define HOST_TBL_RD_OP_DATA5_DATA_OFFSET 0 - #define HOST_TBL_RD_OP_DATA5_DATA_LEN 32 - #define HOST_TBL_RD_OP_DATA5_DATA_DEFAULT 0x0 - -struct host_tbl_rd_op_data5 { - a_uint32_t data:32; -}; - -union host_tbl_rd_op_data5_u { - a_uint32_t val; - struct host_tbl_rd_op_data5 bf; -}; - -/*[register] HOST_TBL_RD_OP_DATA6*/ -#define HOST_TBL_RD_OP_DATA6 -#define HOST_TBL_RD_OP_DATA6_ADDRESS 0x508 -#define HOST_TBL_RD_OP_DATA6_NUM 1 -#define HOST_TBL_RD_OP_DATA6_INC 0x4 -#define HOST_TBL_RD_OP_DATA6_TYPE REG_TYPE_RW -#define HOST_TBL_RD_OP_DATA6_DEFAULT 0x0 - /*[field] DATA*/ - #define HOST_TBL_RD_OP_DATA6_DATA - #define HOST_TBL_RD_OP_DATA6_DATA_OFFSET 0 - #define HOST_TBL_RD_OP_DATA6_DATA_LEN 32 - #define HOST_TBL_RD_OP_DATA6_DATA_DEFAULT 0x0 - -struct host_tbl_rd_op_data6 { - a_uint32_t data:32; -}; - -union host_tbl_rd_op_data6_u { - a_uint32_t val; - struct host_tbl_rd_op_data6 bf; -}; - -/*[register] HOST_TBL_RD_OP_DATA7*/ -#define HOST_TBL_RD_OP_DATA7 -#define HOST_TBL_RD_OP_DATA7_ADDRESS 0x50c -#define HOST_TBL_RD_OP_DATA7_NUM 1 -#define HOST_TBL_RD_OP_DATA7_INC 0x4 -#define HOST_TBL_RD_OP_DATA7_TYPE REG_TYPE_RW -#define HOST_TBL_RD_OP_DATA7_DEFAULT 0x0 - /*[field] DATA*/ - #define HOST_TBL_RD_OP_DATA7_DATA - #define HOST_TBL_RD_OP_DATA7_DATA_OFFSET 0 - #define HOST_TBL_RD_OP_DATA7_DATA_LEN 32 - #define HOST_TBL_RD_OP_DATA7_DATA_DEFAULT 0x0 - -struct host_tbl_rd_op_data7 { - a_uint32_t data:32; -}; - -union host_tbl_rd_op_data7_u { - a_uint32_t val; - struct host_tbl_rd_op_data7 bf; -}; - -/*[register] HOST_TBL_RD_OP_DATA8*/ -#define HOST_TBL_RD_OP_DATA8 -#define HOST_TBL_RD_OP_DATA8_ADDRESS 0x510 -#define HOST_TBL_RD_OP_DATA8_NUM 1 -#define HOST_TBL_RD_OP_DATA8_INC 0x4 -#define HOST_TBL_RD_OP_DATA8_TYPE REG_TYPE_RW -#define HOST_TBL_RD_OP_DATA8_DEFAULT 0x0 - /*[field] DATA*/ - #define HOST_TBL_RD_OP_DATA8_DATA - #define HOST_TBL_RD_OP_DATA8_DATA_OFFSET 0 - #define HOST_TBL_RD_OP_DATA8_DATA_LEN 32 - #define HOST_TBL_RD_OP_DATA8_DATA_DEFAULT 0x0 - -struct host_tbl_rd_op_data8 { - a_uint32_t data:32; -}; - -union host_tbl_rd_op_data8_u { - a_uint32_t val; - struct host_tbl_rd_op_data8 bf; -}; - -/*[register] HOST_TBL_RD_OP_DATA9*/ -#define HOST_TBL_RD_OP_DATA9 -#define HOST_TBL_RD_OP_DATA9_ADDRESS 0x514 -#define HOST_TBL_RD_OP_DATA9_NUM 1 -#define HOST_TBL_RD_OP_DATA9_INC 0x4 -#define HOST_TBL_RD_OP_DATA9_TYPE REG_TYPE_RW -#define HOST_TBL_RD_OP_DATA9_DEFAULT 0x0 - /*[field] DATA*/ - #define HOST_TBL_RD_OP_DATA9_DATA - #define HOST_TBL_RD_OP_DATA9_DATA_OFFSET 0 - #define HOST_TBL_RD_OP_DATA9_DATA_LEN 32 - #define HOST_TBL_RD_OP_DATA9_DATA_DEFAULT 0x0 - -struct host_tbl_rd_op_data9 { - a_uint32_t data:32; -}; - -union host_tbl_rd_op_data9_u { - a_uint32_t val; - struct host_tbl_rd_op_data9 bf; -}; - -/*[register] HOST_TBL_RD_OP_RSLT*/ -#define HOST_TBL_RD_OP_RSLT -#define HOST_TBL_RD_OP_RSLT_ADDRESS 0x518 -#define HOST_TBL_RD_OP_RSLT_NUM 1 -#define HOST_TBL_RD_OP_RSLT_INC 0x4 -#define HOST_TBL_RD_OP_RSLT_TYPE REG_TYPE_RO -#define HOST_TBL_RD_OP_RSLT_DEFAULT 0x0 - /*[field] CMD_ID*/ - #define HOST_TBL_RD_OP_RSLT_CMD_ID - #define HOST_TBL_RD_OP_RSLT_CMD_ID_OFFSET 0 - #define HOST_TBL_RD_OP_RSLT_CMD_ID_LEN 4 - #define HOST_TBL_RD_OP_RSLT_CMD_ID_DEFAULT 0x0 - /*[field] OP_RSLT*/ - #define HOST_TBL_RD_OP_RSLT_OP_RSLT - #define HOST_TBL_RD_OP_RSLT_OP_RSLT_OFFSET 4 - #define HOST_TBL_RD_OP_RSLT_OP_RSLT_LEN 1 - #define HOST_TBL_RD_OP_RSLT_OP_RSLT_DEFAULT 0x0 - /*[field] ENTRY_INDEX*/ - #define HOST_TBL_RD_OP_RSLT_ENTRY_INDEX - #define HOST_TBL_RD_OP_RSLT_ENTRY_INDEX_OFFSET 5 - #define HOST_TBL_RD_OP_RSLT_ENTRY_INDEX_LEN 13 - #define HOST_TBL_RD_OP_RSLT_ENTRY_INDEX_DEFAULT 0x0 - /*[field] VALID_CNT*/ - #define HOST_TBL_RD_OP_RSLT_VALID_CNT - #define HOST_TBL_RD_OP_RSLT_VALID_CNT_OFFSET 18 - #define HOST_TBL_RD_OP_RSLT_VALID_CNT_LEN 4 - #define HOST_TBL_RD_OP_RSLT_VALID_CNT_DEFAULT 0x0 - -struct host_tbl_rd_op_rslt { - a_uint32_t cmd_id:4; - a_uint32_t op_rslt:1; - a_uint32_t entry_index:13; - a_uint32_t valid_cnt:4; - a_uint32_t _reserved0:10; -}; - -union host_tbl_rd_op_rslt_u { - a_uint32_t val; - struct host_tbl_rd_op_rslt bf; -}; - -/*[register] HOST_TBL_RD_RSLT_DATA0*/ -#define HOST_TBL_RD_RSLT_DATA0 -#define HOST_TBL_RD_RSLT_DATA0_ADDRESS 0x51c -#define HOST_TBL_RD_RSLT_DATA0_NUM 1 -#define HOST_TBL_RD_RSLT_DATA0_INC 0x4 -#define HOST_TBL_RD_RSLT_DATA0_TYPE REG_TYPE_RO -#define HOST_TBL_RD_RSLT_DATA0_DEFAULT 0x0 - /*[field] DATA*/ - #define HOST_TBL_RD_RSLT_DATA0_DATA - #define HOST_TBL_RD_RSLT_DATA0_DATA_OFFSET 0 - #define HOST_TBL_RD_RSLT_DATA0_DATA_LEN 32 - #define HOST_TBL_RD_RSLT_DATA0_DATA_DEFAULT 0x0 - -struct host_tbl_rd_rslt_data0 { - a_uint32_t data:32; -}; - -union host_tbl_rd_rslt_data0_u { - a_uint32_t val; - struct host_tbl_rd_rslt_data0 bf; -}; - -/*[register] HOST_TBL_RD_RSLT_DATA1*/ -#define HOST_TBL_RD_RSLT_DATA1 -#define HOST_TBL_RD_RSLT_DATA1_ADDRESS 0x520 -#define HOST_TBL_RD_RSLT_DATA1_NUM 1 -#define HOST_TBL_RD_RSLT_DATA1_INC 0x4 -#define HOST_TBL_RD_RSLT_DATA1_TYPE REG_TYPE_RO -#define HOST_TBL_RD_RSLT_DATA1_DEFAULT 0x0 - /*[field] DATA*/ - #define HOST_TBL_RD_RSLT_DATA1_DATA - #define HOST_TBL_RD_RSLT_DATA1_DATA_OFFSET 0 - #define HOST_TBL_RD_RSLT_DATA1_DATA_LEN 32 - #define HOST_TBL_RD_RSLT_DATA1_DATA_DEFAULT 0x0 - -struct host_tbl_rd_rslt_data1 { - a_uint32_t data:32; -}; - -union host_tbl_rd_rslt_data1_u { - a_uint32_t val; - struct host_tbl_rd_rslt_data1 bf; -}; - -/*[register] HOST_TBL_RD_RSLT_DATA2*/ -#define HOST_TBL_RD_RSLT_DATA2 -#define HOST_TBL_RD_RSLT_DATA2_ADDRESS 0x524 -#define HOST_TBL_RD_RSLT_DATA2_NUM 1 -#define HOST_TBL_RD_RSLT_DATA2_INC 0x4 -#define HOST_TBL_RD_RSLT_DATA2_TYPE REG_TYPE_RO -#define HOST_TBL_RD_RSLT_DATA2_DEFAULT 0x0 - /*[field] DATA*/ - #define HOST_TBL_RD_RSLT_DATA2_DATA - #define HOST_TBL_RD_RSLT_DATA2_DATA_OFFSET 0 - #define HOST_TBL_RD_RSLT_DATA2_DATA_LEN 32 - #define HOST_TBL_RD_RSLT_DATA2_DATA_DEFAULT 0x0 - -struct host_tbl_rd_rslt_data2 { - a_uint32_t data:32; -}; - -union host_tbl_rd_rslt_data2_u { - a_uint32_t val; - struct host_tbl_rd_rslt_data2 bf; -}; - -/*[register] HOST_TBL_RD_RSLT_DATA3*/ -#define HOST_TBL_RD_RSLT_DATA3 -#define HOST_TBL_RD_RSLT_DATA3_ADDRESS 0x528 -#define HOST_TBL_RD_RSLT_DATA3_NUM 1 -#define HOST_TBL_RD_RSLT_DATA3_INC 0x4 -#define HOST_TBL_RD_RSLT_DATA3_TYPE REG_TYPE_RO -#define HOST_TBL_RD_RSLT_DATA3_DEFAULT 0x0 - /*[field] DATA*/ - #define HOST_TBL_RD_RSLT_DATA3_DATA - #define HOST_TBL_RD_RSLT_DATA3_DATA_OFFSET 0 - #define HOST_TBL_RD_RSLT_DATA3_DATA_LEN 32 - #define HOST_TBL_RD_RSLT_DATA3_DATA_DEFAULT 0x0 - -struct host_tbl_rd_rslt_data3 { - a_uint32_t data:32; -}; - -union host_tbl_rd_rslt_data3_u { - a_uint32_t val; - struct host_tbl_rd_rslt_data3 bf; -}; - -/*[register] HOST_TBL_RD_RSLT_DATA4*/ -#define HOST_TBL_RD_RSLT_DATA4 -#define HOST_TBL_RD_RSLT_DATA4_ADDRESS 0x52c -#define HOST_TBL_RD_RSLT_DATA4_NUM 1 -#define HOST_TBL_RD_RSLT_DATA4_INC 0x4 -#define HOST_TBL_RD_RSLT_DATA4_TYPE REG_TYPE_RO -#define HOST_TBL_RD_RSLT_DATA4_DEFAULT 0x0 - /*[field] DATA*/ - #define HOST_TBL_RD_RSLT_DATA4_DATA - #define HOST_TBL_RD_RSLT_DATA4_DATA_OFFSET 0 - #define HOST_TBL_RD_RSLT_DATA4_DATA_LEN 32 - #define HOST_TBL_RD_RSLT_DATA4_DATA_DEFAULT 0x0 - -struct host_tbl_rd_rslt_data4 { - a_uint32_t data:32; -}; - -union host_tbl_rd_rslt_data4_u { - a_uint32_t val; - struct host_tbl_rd_rslt_data4 bf; -}; - -/*[register] HOST_TBL_RD_RSLT_DATA5*/ -#define HOST_TBL_RD_RSLT_DATA5 -#define HOST_TBL_RD_RSLT_DATA5_ADDRESS 0x530 -#define HOST_TBL_RD_RSLT_DATA5_NUM 1 -#define HOST_TBL_RD_RSLT_DATA5_INC 0x4 -#define HOST_TBL_RD_RSLT_DATA5_TYPE REG_TYPE_RO -#define HOST_TBL_RD_RSLT_DATA5_DEFAULT 0x0 - /*[field] DATA*/ - #define HOST_TBL_RD_RSLT_DATA5_DATA - #define HOST_TBL_RD_RSLT_DATA5_DATA_OFFSET 0 - #define HOST_TBL_RD_RSLT_DATA5_DATA_LEN 32 - #define HOST_TBL_RD_RSLT_DATA5_DATA_DEFAULT 0x0 - -struct host_tbl_rd_rslt_data5 { - a_uint32_t data:32; -}; - -union host_tbl_rd_rslt_data5_u { - a_uint32_t val; - struct host_tbl_rd_rslt_data5 bf; -}; - -/*[register] HOST_TBL_RD_RSLT_DATA6*/ -#define HOST_TBL_RD_RSLT_DATA6 -#define HOST_TBL_RD_RSLT_DATA6_ADDRESS 0x534 -#define HOST_TBL_RD_RSLT_DATA6_NUM 1 -#define HOST_TBL_RD_RSLT_DATA6_INC 0x4 -#define HOST_TBL_RD_RSLT_DATA6_TYPE REG_TYPE_RO -#define HOST_TBL_RD_RSLT_DATA6_DEFAULT 0x0 - /*[field] DATA*/ - #define HOST_TBL_RD_RSLT_DATA6_DATA - #define HOST_TBL_RD_RSLT_DATA6_DATA_OFFSET 0 - #define HOST_TBL_RD_RSLT_DATA6_DATA_LEN 32 - #define HOST_TBL_RD_RSLT_DATA6_DATA_DEFAULT 0x0 - -struct host_tbl_rd_rslt_data6 { - a_uint32_t data:32; -}; - -union host_tbl_rd_rslt_data6_u { - a_uint32_t val; - struct host_tbl_rd_rslt_data6 bf; -}; - -/*[register] HOST_TBL_RD_RSLT_DATA7*/ -#define HOST_TBL_RD_RSLT_DATA7 -#define HOST_TBL_RD_RSLT_DATA7_ADDRESS 0x538 -#define HOST_TBL_RD_RSLT_DATA7_NUM 1 -#define HOST_TBL_RD_RSLT_DATA7_INC 0x4 -#define HOST_TBL_RD_RSLT_DATA7_TYPE REG_TYPE_RO -#define HOST_TBL_RD_RSLT_DATA7_DEFAULT 0x0 - /*[field] DATA*/ - #define HOST_TBL_RD_RSLT_DATA7_DATA - #define HOST_TBL_RD_RSLT_DATA7_DATA_OFFSET 0 - #define HOST_TBL_RD_RSLT_DATA7_DATA_LEN 32 - #define HOST_TBL_RD_RSLT_DATA7_DATA_DEFAULT 0x0 - -struct host_tbl_rd_rslt_data7 { - a_uint32_t data:32; -}; - -union host_tbl_rd_rslt_data7_u { - a_uint32_t val; - struct host_tbl_rd_rslt_data7 bf; -}; - -/*[register] HOST_TBL_RD_RSLT_DATA8*/ -#define HOST_TBL_RD_RSLT_DATA8 -#define HOST_TBL_RD_RSLT_DATA8_ADDRESS 0x53c -#define HOST_TBL_RD_RSLT_DATA8_NUM 1 -#define HOST_TBL_RD_RSLT_DATA8_INC 0x4 -#define HOST_TBL_RD_RSLT_DATA8_TYPE REG_TYPE_RO -#define HOST_TBL_RD_RSLT_DATA8_DEFAULT 0x0 - /*[field] DATA*/ - #define HOST_TBL_RD_RSLT_DATA8_DATA - #define HOST_TBL_RD_RSLT_DATA8_DATA_OFFSET 0 - #define HOST_TBL_RD_RSLT_DATA8_DATA_LEN 32 - #define HOST_TBL_RD_RSLT_DATA8_DATA_DEFAULT 0x0 - -struct host_tbl_rd_rslt_data8 { - a_uint32_t data:32; -}; - -union host_tbl_rd_rslt_data8_u { - a_uint32_t val; - struct host_tbl_rd_rslt_data8 bf; -}; - -/*[register] HOST_TBL_RD_RSLT_DATA9*/ -#define HOST_TBL_RD_RSLT_DATA9 -#define HOST_TBL_RD_RSLT_DATA9_ADDRESS 0x540 -#define HOST_TBL_RD_RSLT_DATA9_NUM 1 -#define HOST_TBL_RD_RSLT_DATA9_INC 0x4 -#define HOST_TBL_RD_RSLT_DATA9_TYPE REG_TYPE_RO -#define HOST_TBL_RD_RSLT_DATA9_DEFAULT 0x0 - /*[field] DATA*/ - #define HOST_TBL_RD_RSLT_DATA9_DATA - #define HOST_TBL_RD_RSLT_DATA9_DATA_OFFSET 0 - #define HOST_TBL_RD_RSLT_DATA9_DATA_LEN 32 - #define HOST_TBL_RD_RSLT_DATA9_DATA_DEFAULT 0x0 - -struct host_tbl_rd_rslt_data9 { - a_uint32_t data:32; -}; - -union host_tbl_rd_rslt_data9_u { - a_uint32_t val; - struct host_tbl_rd_rslt_data9 bf; -}; - -/*[register] L3_DBG_CMD*/ -#define L3_DBG_CMD -#define L3_DBG_CMD_ADDRESS 0xc04 -#define L3_DBG_CMD_NUM 1 -#define L3_DBG_CMD_INC 0x4 -#define L3_DBG_CMD_TYPE REG_TYPE_RW -#define L3_DBG_CMD_DEFAULT 0x0 - /*[field] ADDR*/ - #define L3_DBG_CMD_ADDR - #define L3_DBG_CMD_ADDR_OFFSET 0 - #define L3_DBG_CMD_ADDR_LEN 8 - #define L3_DBG_CMD_ADDR_DEFAULT 0x0 - /*[field] TYPE*/ - #define L3_DBG_CMD_TYPE_F - #define L3_DBG_CMD_TYPE_F_OFFSET 8 - #define L3_DBG_CMD_TYPE_F_LEN 2 - #define L3_DBG_CMD_TYPE_F_DEFAULT 0x0 - -struct l3_dbg_cmd { - a_uint32_t addr:8; - a_uint32_t type:2; - a_uint32_t _reserved0:22; -}; - -union l3_dbg_cmd_u { - a_uint32_t val; - struct l3_dbg_cmd bf; -}; - -/*[register] L3_DBG_WR_DATA*/ -#define L3_DBG_WR_DATA -#define L3_DBG_WR_DATA_ADDRESS 0xc08 -#define L3_DBG_WR_DATA_NUM 1 -#define L3_DBG_WR_DATA_INC 0x4 -#define L3_DBG_WR_DATA_TYPE REG_TYPE_RW -#define L3_DBG_WR_DATA_DEFAULT 0x0 - /*[field] DATA*/ - #define L3_DBG_WR_DATA_DATA - #define L3_DBG_WR_DATA_DATA_OFFSET 0 - #define L3_DBG_WR_DATA_DATA_LEN 32 - #define L3_DBG_WR_DATA_DATA_DEFAULT 0x0 - -struct l3_dbg_wr_data { - a_uint32_t data:32; -}; - -union l3_dbg_wr_data_u { - a_uint32_t val; - struct l3_dbg_wr_data bf; -}; - -/*[register] L3_DBG_RD_DATA*/ -#define L3_DBG_RD_DATA -#define L3_DBG_RD_DATA_ADDRESS 0xc0c -#define L3_DBG_RD_DATA_NUM 1 -#define L3_DBG_RD_DATA_INC 0x4 -#define L3_DBG_RD_DATA_TYPE REG_TYPE_RO -#define L3_DBG_RD_DATA_DEFAULT 0x0 - /*[field] DATA*/ - #define L3_DBG_RD_DATA_DATA - #define L3_DBG_RD_DATA_DATA_OFFSET 0 - #define L3_DBG_RD_DATA_DATA_LEN 32 - #define L3_DBG_RD_DATA_DATA_DEFAULT 0x0 - -struct l3_dbg_rd_data { - a_uint32_t data:32; -}; - -union l3_dbg_rd_data_u { - a_uint32_t val; - struct l3_dbg_rd_data bf; -}; - -/*[register] IN_PUB_IP_ADDR_TBL*/ -#define IN_PUB_IP_ADDR_TBL -#define IN_PUB_IP_ADDR_TBL_ADDRESS 0x378 -#define IN_PUB_IP_ADDR_TBL_NUM 16 -#define IN_PUB_IP_ADDR_TBL_INC 0x4 -#define IN_PUB_IP_ADDR_TBL_TYPE REG_TYPE_RW -#define IN_PUB_IP_ADDR_TBL_DEFAULT 0x0 - /*[field] IP_ADDR*/ - #define IN_PUB_IP_ADDR_TBL_IP_ADDR - #define IN_PUB_IP_ADDR_TBL_IP_ADDR_OFFSET 0 - #define IN_PUB_IP_ADDR_TBL_IP_ADDR_LEN 32 - #define IN_PUB_IP_ADDR_TBL_IP_ADDR_DEFAULT 0x0 - -struct in_pub_ip_addr_tbl { - a_uint32_t ip_addr:32; -}; - -union in_pub_ip_addr_tbl_u { - a_uint32_t val; - struct in_pub_ip_addr_tbl bf; -}; - -/*[table] L3_VP_PORT_TBL*/ -#define L3_VP_PORT_TBL -#define L3_VP_PORT_TBL_ADDRESS 0x1000 -#define L3_VP_PORT_TBL_NUM 256 -#define L3_VP_PORT_TBL_INC 0x10 -#define L3_VP_PORT_TBL_TYPE REG_TYPE_RW -#define L3_VP_PORT_TBL_DEFAULT 0x0 - /*[field] L3_IF_VALID*/ - #define L3_VP_PORT_TBL_L3_IF_VALID - #define L3_VP_PORT_TBL_L3_IF_VALID_OFFSET 0 - #define L3_VP_PORT_TBL_L3_IF_VALID_LEN 1 - #define L3_VP_PORT_TBL_L3_IF_VALID_DEFAULT 0x0 - /*[field] L3_IF_INDEX*/ - #define L3_VP_PORT_TBL_L3_IF_INDEX - #define L3_VP_PORT_TBL_L3_IF_INDEX_OFFSET 1 - #define L3_VP_PORT_TBL_L3_IF_INDEX_LEN 8 - #define L3_VP_PORT_TBL_L3_IF_INDEX_DEFAULT 0x0 - /*[field] IPV4_SG_EN*/ - #define L3_VP_PORT_TBL_IPV4_SG_EN - #define L3_VP_PORT_TBL_IPV4_SG_EN_OFFSET 9 - #define L3_VP_PORT_TBL_IPV4_SG_EN_LEN 1 - #define L3_VP_PORT_TBL_IPV4_SG_EN_DEFAULT 0x0 - /*[field] IPV4_SG_VIO_CMD*/ - #define L3_VP_PORT_TBL_IPV4_SG_VIO_CMD - #define L3_VP_PORT_TBL_IPV4_SG_VIO_CMD_OFFSET 10 - #define L3_VP_PORT_TBL_IPV4_SG_VIO_CMD_LEN 2 - #define L3_VP_PORT_TBL_IPV4_SG_VIO_CMD_DEFAULT 0x0 - /*[field] IPV4_SG_PORT_EN*/ - #define L3_VP_PORT_TBL_IPV4_SG_PORT_EN - #define L3_VP_PORT_TBL_IPV4_SG_PORT_EN_OFFSET 12 - #define L3_VP_PORT_TBL_IPV4_SG_PORT_EN_LEN 1 - #define L3_VP_PORT_TBL_IPV4_SG_PORT_EN_DEFAULT 0x0 - /*[field] IPV4_SG_SVLAN_EN*/ - #define L3_VP_PORT_TBL_IPV4_SG_SVLAN_EN - #define L3_VP_PORT_TBL_IPV4_SG_SVLAN_EN_OFFSET 13 - #define L3_VP_PORT_TBL_IPV4_SG_SVLAN_EN_LEN 1 - #define L3_VP_PORT_TBL_IPV4_SG_SVLAN_EN_DEFAULT 0x0 - /*[field] IPV4_SG_CVLAN_EN*/ - #define L3_VP_PORT_TBL_IPV4_SG_CVLAN_EN - #define L3_VP_PORT_TBL_IPV4_SG_CVLAN_EN_OFFSET 14 - #define L3_VP_PORT_TBL_IPV4_SG_CVLAN_EN_LEN 1 - #define L3_VP_PORT_TBL_IPV4_SG_CVLAN_EN_DEFAULT 0x0 - /*[field] IPV4_SRC_UNK_CMD*/ - #define L3_VP_PORT_TBL_IPV4_SRC_UNK_CMD - #define L3_VP_PORT_TBL_IPV4_SRC_UNK_CMD_OFFSET 15 - #define L3_VP_PORT_TBL_IPV4_SRC_UNK_CMD_LEN 2 - #define L3_VP_PORT_TBL_IPV4_SRC_UNK_CMD_DEFAULT 0x0 - /*[field] IPV6_SG_EN*/ - #define L3_VP_PORT_TBL_IPV6_SG_EN - #define L3_VP_PORT_TBL_IPV6_SG_EN_OFFSET 17 - #define L3_VP_PORT_TBL_IPV6_SG_EN_LEN 1 - #define L3_VP_PORT_TBL_IPV6_SG_EN_DEFAULT 0x0 - /*[field] IPV6_SG_VIO_CMD*/ - #define L3_VP_PORT_TBL_IPV6_SG_VIO_CMD - #define L3_VP_PORT_TBL_IPV6_SG_VIO_CMD_OFFSET 18 - #define L3_VP_PORT_TBL_IPV6_SG_VIO_CMD_LEN 2 - #define L3_VP_PORT_TBL_IPV6_SG_VIO_CMD_DEFAULT 0x0 - /*[field] IPV6_SG_PORT_EN*/ - #define L3_VP_PORT_TBL_IPV6_SG_PORT_EN - #define L3_VP_PORT_TBL_IPV6_SG_PORT_EN_OFFSET 20 - #define L3_VP_PORT_TBL_IPV6_SG_PORT_EN_LEN 1 - #define L3_VP_PORT_TBL_IPV6_SG_PORT_EN_DEFAULT 0x0 - /*[field] IPV6_SG_SVLAN_EN*/ - #define L3_VP_PORT_TBL_IPV6_SG_SVLAN_EN - #define L3_VP_PORT_TBL_IPV6_SG_SVLAN_EN_OFFSET 21 - #define L3_VP_PORT_TBL_IPV6_SG_SVLAN_EN_LEN 1 - #define L3_VP_PORT_TBL_IPV6_SG_SVLAN_EN_DEFAULT 0x0 - /*[field] IPV6_SG_CVLAN_EN*/ - #define L3_VP_PORT_TBL_IPV6_SG_CVLAN_EN - #define L3_VP_PORT_TBL_IPV6_SG_CVLAN_EN_OFFSET 22 - #define L3_VP_PORT_TBL_IPV6_SG_CVLAN_EN_LEN 1 - #define L3_VP_PORT_TBL_IPV6_SG_CVLAN_EN_DEFAULT 0x0 - /*[field] IPV6_SRC_UNK_CMD*/ - #define L3_VP_PORT_TBL_IPV6_SRC_UNK_CMD - #define L3_VP_PORT_TBL_IPV6_SRC_UNK_CMD_OFFSET 23 - #define L3_VP_PORT_TBL_IPV6_SRC_UNK_CMD_LEN 2 - #define L3_VP_PORT_TBL_IPV6_SRC_UNK_CMD_DEFAULT 0x0 - /*[field] IP_ARP_SG_EN*/ - #define L3_VP_PORT_TBL_IP_ARP_SG_EN - #define L3_VP_PORT_TBL_IP_ARP_SG_EN_OFFSET 25 - #define L3_VP_PORT_TBL_IP_ARP_SG_EN_LEN 1 - #define L3_VP_PORT_TBL_IP_ARP_SG_EN_DEFAULT 0x0 - /*[field] IP_ARP_SG_VIO_CMD*/ - #define L3_VP_PORT_TBL_IP_ARP_SG_VIO_CMD - #define L3_VP_PORT_TBL_IP_ARP_SG_VIO_CMD_OFFSET 26 - #define L3_VP_PORT_TBL_IP_ARP_SG_VIO_CMD_LEN 2 - #define L3_VP_PORT_TBL_IP_ARP_SG_VIO_CMD_DEFAULT 0x0 - /*[field] IP_ARP_SG_PORT_EN*/ - #define L3_VP_PORT_TBL_IP_ARP_SG_PORT_EN - #define L3_VP_PORT_TBL_IP_ARP_SG_PORT_EN_OFFSET 28 - #define L3_VP_PORT_TBL_IP_ARP_SG_PORT_EN_LEN 1 - #define L3_VP_PORT_TBL_IP_ARP_SG_PORT_EN_DEFAULT 0x0 - /*[field] IP_ARP_SG_SVLAN_EN*/ - #define L3_VP_PORT_TBL_IP_ARP_SG_SVLAN_EN - #define L3_VP_PORT_TBL_IP_ARP_SG_SVLAN_EN_OFFSET 29 - #define L3_VP_PORT_TBL_IP_ARP_SG_SVLAN_EN_LEN 1 - #define L3_VP_PORT_TBL_IP_ARP_SG_SVLAN_EN_DEFAULT 0x0 - /*[field] IP_ARP_SRC_UNK_CMD*/ - #define L3_VP_PORT_TBL_IP_ARP_SRC_UNK_CMD - #define L3_VP_PORT_TBL_IP_ARP_SRC_UNK_CMD_OFFSET 30 - #define L3_VP_PORT_TBL_IP_ARP_SRC_UNK_CMD_LEN 2 - #define L3_VP_PORT_TBL_IP_ARP_SRC_UNK_CMD_DEFAULT 0x0 - /*[field] IP_ARP_SG_CVLAN_EN*/ - #define L3_VP_PORT_TBL_IP_ARP_SG_CVLAN_EN - #define L3_VP_PORT_TBL_IP_ARP_SG_CVLAN_EN_OFFSET 32 - #define L3_VP_PORT_TBL_IP_ARP_SG_CVLAN_EN_LEN 1 - #define L3_VP_PORT_TBL_IP_ARP_SG_CVLAN_EN_DEFAULT 0x0 - /*[field] IP_ND_SG_EN*/ - #define L3_VP_PORT_TBL_IP_ND_SG_EN - #define L3_VP_PORT_TBL_IP_ND_SG_EN_OFFSET 33 - #define L3_VP_PORT_TBL_IP_ND_SG_EN_LEN 1 - #define L3_VP_PORT_TBL_IP_ND_SG_EN_DEFAULT 0x0 - /*[field] IP_ND_SG_VIO_CMD*/ - #define L3_VP_PORT_TBL_IP_ND_SG_VIO_CMD - #define L3_VP_PORT_TBL_IP_ND_SG_VIO_CMD_OFFSET 34 - #define L3_VP_PORT_TBL_IP_ND_SG_VIO_CMD_LEN 2 - #define L3_VP_PORT_TBL_IP_ND_SG_VIO_CMD_DEFAULT 0x0 - /*[field] IP_ND_SG_PORT_EN*/ - #define L3_VP_PORT_TBL_IP_ND_SG_PORT_EN - #define L3_VP_PORT_TBL_IP_ND_SG_PORT_EN_OFFSET 36 - #define L3_VP_PORT_TBL_IP_ND_SG_PORT_EN_LEN 1 - #define L3_VP_PORT_TBL_IP_ND_SG_PORT_EN_DEFAULT 0x0 - /*[field] IP_ND_SG_SVLAN_EN*/ - #define L3_VP_PORT_TBL_IP_ND_SG_SVLAN_EN - #define L3_VP_PORT_TBL_IP_ND_SG_SVLAN_EN_OFFSET 37 - #define L3_VP_PORT_TBL_IP_ND_SG_SVLAN_EN_LEN 1 - #define L3_VP_PORT_TBL_IP_ND_SG_SVLAN_EN_DEFAULT 0x0 - /*[field] IP_ND_SG_CVLAN_EN*/ - #define L3_VP_PORT_TBL_IP_ND_SG_CVLAN_EN - #define L3_VP_PORT_TBL_IP_ND_SG_CVLAN_EN_OFFSET 38 - #define L3_VP_PORT_TBL_IP_ND_SG_CVLAN_EN_LEN 1 - #define L3_VP_PORT_TBL_IP_ND_SG_CVLAN_EN_DEFAULT 0x0 - /*[field] IP_ND_SRC_UNK_CMD*/ - #define L3_VP_PORT_TBL_IP_ND_SRC_UNK_CMD - #define L3_VP_PORT_TBL_IP_ND_SRC_UNK_CMD_OFFSET 39 - #define L3_VP_PORT_TBL_IP_ND_SRC_UNK_CMD_LEN 2 - #define L3_VP_PORT_TBL_IP_ND_SRC_UNK_CMD_DEFAULT 0x0 - /*[field] VSI_VALID*/ - #define L3_VP_PORT_TBL_VSI_VALID - #define L3_VP_PORT_TBL_VSI_VALID_OFFSET 41 - #define L3_VP_PORT_TBL_VSI_VALID_LEN 1 - #define L3_VP_PORT_TBL_VSI_VALID_DEFAULT 0x0 - /*[field] VSI*/ - #define L3_VP_PORT_TBL_VSI - #define L3_VP_PORT_TBL_VSI_OFFSET 42 - #define L3_VP_PORT_TBL_VSI_LEN 5 - #define L3_VP_PORT_TBL_VSI_DEFAULT 0x0 - /*[field] MAC_VALID*/ - #define L3_VP_PORT_TBL_MAC_VALID - #define L3_VP_PORT_TBL_MAC_VALID_OFFSET 47 - #define L3_VP_PORT_TBL_MAC_VALID_LEN 1 - #define L3_VP_PORT_TBL_MAC_VALID_DEFAULT 0x0 - /*[field] MAC_DA*/ - #define L3_VP_PORT_TBL_MAC_DA - #define L3_VP_PORT_TBL_MAC_DA_OFFSET 48 - #define L3_VP_PORT_TBL_MAC_DA_LEN 48 - #define L3_VP_PORT_TBL_MAC_DA_DEFAULT 0x0 - -struct l3_vp_port_tbl { - a_uint32_t l3_if_valid:1; - a_uint32_t l3_if_index:8; - a_uint32_t ipv4_sg_en:1; - a_uint32_t ipv4_sg_vio_cmd:2; - a_uint32_t ipv4_sg_port_en:1; - a_uint32_t ipv4_sg_svlan_en:1; - a_uint32_t ipv4_sg_cvlan_en:1; - a_uint32_t ipv4_src_unk_cmd:2; - a_uint32_t ipv6_sg_en:1; - a_uint32_t ipv6_sg_vio_cmd:2; - a_uint32_t ipv6_sg_port_en:1; - a_uint32_t ipv6_sg_svlan_en:1; - a_uint32_t ipv6_sg_cvlan_en:1; - a_uint32_t ipv6_src_unk_cmd:2; - a_uint32_t ip_arp_sg_en:1; - a_uint32_t ip_arp_sg_vio_cmd:2; - a_uint32_t ip_arp_sg_port_en:1; - a_uint32_t ip_arp_sg_svlan_en:1; - a_uint32_t ip_arp_src_unk_cmd:2; - a_uint32_t ip_arp_sg_cvlan_en:1; - a_uint32_t ip_nd_sg_en:1; - a_uint32_t ip_nd_sg_vio_cmd:2; - a_uint32_t ip_nd_sg_port_en:1; - a_uint32_t ip_nd_sg_svlan_en:1; - a_uint32_t ip_nd_sg_cvlan_en:1; - a_uint32_t ip_nd_src_unk_cmd:2; - a_uint32_t vsi_valid:1; - a_uint32_t vsi:5; - a_uint32_t mac_valid:1; - a_uint32_t mac_da_0:16; - a_uint32_t mac_da_1:32; -}; - -union l3_vp_port_tbl_u { - a_uint32_t val[3]; - struct l3_vp_port_tbl bf; -}; - -/*[table] IN_L3_IF_TBL*/ -#define IN_L3_IF_TBL -#define IN_L3_IF_TBL_ADDRESS 0x2000 -#define IN_L3_IF_TBL_NUM 256 -#define IN_L3_IF_TBL_INC 0x8 -#define IN_L3_IF_TBL_TYPE REG_TYPE_RW -#define IN_L3_IF_TBL_DEFAULT 0x0 - /*[field] MRU*/ - #define IN_L3_IF_TBL_MRU - #define IN_L3_IF_TBL_MRU_OFFSET 0 - #define IN_L3_IF_TBL_MRU_LEN 14 - #define IN_L3_IF_TBL_MRU_DEFAULT 0x0 - /*[field] MTU*/ - #define IN_L3_IF_TBL_MTU - #define IN_L3_IF_TBL_MTU_OFFSET 14 - #define IN_L3_IF_TBL_MTU_LEN 14 - #define IN_L3_IF_TBL_MTU_DEFAULT 0x0 - /*[field] TTL_DEC_BYPASS*/ - #define IN_L3_IF_TBL_TTL_DEC_BYPASS - #define IN_L3_IF_TBL_TTL_DEC_BYPASS_OFFSET 28 - #define IN_L3_IF_TBL_TTL_DEC_BYPASS_LEN 1 - #define IN_L3_IF_TBL_TTL_DEC_BYPASS_DEFAULT 0x0 - /*[field] IPV4_UC_ROUTE_EN*/ - #define IN_L3_IF_TBL_IPV4_UC_ROUTE_EN - #define IN_L3_IF_TBL_IPV4_UC_ROUTE_EN_OFFSET 29 - #define IN_L3_IF_TBL_IPV4_UC_ROUTE_EN_LEN 1 - #define IN_L3_IF_TBL_IPV4_UC_ROUTE_EN_DEFAULT 0x0 - /*[field] IPV6_UC_ROUTE_EN*/ - #define IN_L3_IF_TBL_IPV6_UC_ROUTE_EN - #define IN_L3_IF_TBL_IPV6_UC_ROUTE_EN_OFFSET 30 - #define IN_L3_IF_TBL_IPV6_UC_ROUTE_EN_LEN 1 - #define IN_L3_IF_TBL_IPV6_UC_ROUTE_EN_DEFAULT 0x0 - /*[field] ICMP_TRIGGER_EN*/ - #define IN_L3_IF_TBL_ICMP_TRIGGER_EN - #define IN_L3_IF_TBL_ICMP_TRIGGER_EN_OFFSET 31 - #define IN_L3_IF_TBL_ICMP_TRIGGER_EN_LEN 1 - #define IN_L3_IF_TBL_ICMP_TRIGGER_EN_DEFAULT 0x0 - /*[field] TTL_EXCEED_CMD*/ - #define IN_L3_IF_TBL_TTL_EXCEED_CMD - #define IN_L3_IF_TBL_TTL_EXCEED_CMD_OFFSET 32 - #define IN_L3_IF_TBL_TTL_EXCEED_CMD_LEN 2 - #define IN_L3_IF_TBL_TTL_EXCEED_CMD_DEFAULT 0x0 - /*[field] TTL_EXCEED_DE_ACCE*/ - #define IN_L3_IF_TBL_TTL_EXCEED_DE_ACCE - #define IN_L3_IF_TBL_TTL_EXCEED_DE_ACCE_OFFSET 34 - #define IN_L3_IF_TBL_TTL_EXCEED_DE_ACCE_LEN 1 - #define IN_L3_IF_TBL_TTL_EXCEED_DE_ACCE_DEFAULT 0x0 - /*[field] MAC_BITMAP*/ - #define IN_L3_IF_TBL_MAC_BITMAP - #define IN_L3_IF_TBL_MAC_BITMAP_OFFSET 35 - #define IN_L3_IF_TBL_MAC_BITMAP_LEN 8 - #define IN_L3_IF_TBL_MAC_BITMAP_DEFAULT 0x0 - /*[field] PPPOE_EN*/ - #define IN_L3_IF_TBL_PPPOE_EN - #define IN_L3_IF_TBL_PPPOE_EN_OFFSET 43 - #define IN_L3_IF_TBL_PPPOE_EN_LEN 1 - #define IN_L3_IF_TBL_PPPOE_EN_DEFAULT 0x0 - -struct in_l3_if_tbl { - a_uint32_t mru:14; - a_uint32_t mtu:14; - a_uint32_t ttl_dec_bypass:1; - a_uint32_t ipv4_uc_route_en:1; - a_uint32_t ipv6_uc_route_en:1; - a_uint32_t icmp_trigger_en:1; - a_uint32_t ttl_exceed_cmd:2; - a_uint32_t ttl_exceed_de_acce:1; - a_uint32_t mac_bitmap:8; - a_uint32_t pppoe_en:1; - a_uint32_t _reserved0:20; -}; - -union in_l3_if_tbl_u { - a_uint32_t val[2]; - struct in_l3_if_tbl bf; -}; - -/*[table] HOST_IPV6_MCAST_TBL*/ -#define HOST_IPV6_MCAST_TBL -#define HOST_IPV6_MCAST_TBL_ADDRESS 0x20000 -#define HOST_IPV6_MCAST_TBL_NUM 1536 -#define HOST_IPV6_MCAST_TBL_INC 0x40 -#define HOST_IPV6_MCAST_TBL_TYPE REG_TYPE_RW -#define HOST_IPV6_MCAST_TBL_DEFAULT 0x0 - /*[field] VALID*/ - #define HOST_IPV6_MCAST_TBL_VALID - #define HOST_IPV6_MCAST_TBL_VALID_OFFSET 0 - #define HOST_IPV6_MCAST_TBL_VALID_LEN 1 - #define HOST_IPV6_MCAST_TBL_VALID_DEFAULT 0x0 - /*[field] KEY_TYPE*/ - #define HOST_IPV6_MCAST_TBL_KEY_TYPE - #define HOST_IPV6_MCAST_TBL_KEY_TYPE_OFFSET 1 - #define HOST_IPV6_MCAST_TBL_KEY_TYPE_LEN 2 - #define HOST_IPV6_MCAST_TBL_KEY_TYPE_DEFAULT 0x0 - /*[field] FWD_CMD*/ - #define HOST_IPV6_MCAST_TBL_FWD_CMD - #define HOST_IPV6_MCAST_TBL_FWD_CMD_OFFSET 3 - #define HOST_IPV6_MCAST_TBL_FWD_CMD_LEN 2 - #define HOST_IPV6_MCAST_TBL_FWD_CMD_DEFAULT 0x0 - /*[field] SYN_TOGGLE*/ - #define HOST_IPV6_MCAST_TBL_SYN_TOGGLE - #define HOST_IPV6_MCAST_TBL_SYN_TOGGLE_OFFSET 5 - #define HOST_IPV6_MCAST_TBL_SYN_TOGGLE_LEN 1 - #define HOST_IPV6_MCAST_TBL_SYN_TOGGLE_DEFAULT 0x0 - /*[field] DST_INFO*/ - #define HOST_IPV6_MCAST_TBL_DST_INFO - #define HOST_IPV6_MCAST_TBL_DST_INFO_OFFSET 6 - #define HOST_IPV6_MCAST_TBL_DST_INFO_LEN 14 - #define HOST_IPV6_MCAST_TBL_DST_INFO_DEFAULT 0x0 - /*[field] LAN_WAN*/ - #define HOST_IPV6_MCAST_TBL_LAN_WAN - #define HOST_IPV6_MCAST_TBL_LAN_WAN_OFFSET 20 - #define HOST_IPV6_MCAST_TBL_LAN_WAN_LEN 1 - #define HOST_IPV6_MCAST_TBL_LAN_WAN_DEFAULT 0x0 - /*[field] VSI*/ - #define HOST_IPV6_MCAST_TBL_VSI - #define HOST_IPV6_MCAST_TBL_VSI_OFFSET 21 - #define HOST_IPV6_MCAST_TBL_VSI_LEN 5 - #define HOST_IPV6_MCAST_TBL_VSI_DEFAULT 0x0 - /*[field] SIPV6_ADDR*/ - #define HOST_IPV6_MCAST_TBL_SIPV6_ADDR - #define HOST_IPV6_MCAST_TBL_SIPV6_ADDR_OFFSET 44 - #define HOST_IPV6_MCAST_TBL_SIPV6_ADDR_LEN 128 - #define HOST_IPV6_MCAST_TBL_SIPV6_ADDR_DEFAULT 0x0 - /*[field] GIPV6_ADDR*/ - #define HOST_IPV6_MCAST_TBL_GIPV6_ADDR - #define HOST_IPV6_MCAST_TBL_GIPV6_ADDR_OFFSET 172 - #define HOST_IPV6_MCAST_TBL_GIPV6_ADDR_LEN 128 - #define HOST_IPV6_MCAST_TBL_GIPV6_ADDR_DEFAULT 0x0 - -struct host_tbl { - a_uint32_t valid:1; - a_uint32_t key_type:2; - a_uint32_t fwd_cmd:2; - a_uint32_t syn_toggle:1; - a_uint32_t dst_info:14; - a_uint32_t lan_wan:1; - a_uint32_t _reserved0:11; - a_uint32_t ip_addr:32; - a_uint32_t _reserved1:32; -}; - -union host_tbl_u { - a_uint32_t val[3]; - struct host_tbl bf; -}; - -/*[table] HOST_IPV4_MCAST_TBL*/ -#define HOST_IPV4_MCAST_TBL -#define HOST_IPV4_MCAST_TBL_ADDRESS 0x20000 -#define HOST_IPV4_MCAST_TBL_NUM 3072 -#define HOST_IPV4_MCAST_TBL_INC 0x20 -#define HOST_IPV4_MCAST_TBL_TYPE REG_TYPE_RW -#define HOST_IPV4_MCAST_TBL_DEFAULT 0x0 - /*[field] VALID*/ - #define HOST_IPV4_MCAST_TBL_VALID - #define HOST_IPV4_MCAST_TBL_VALID_OFFSET 0 - #define HOST_IPV4_MCAST_TBL_VALID_LEN 1 - #define HOST_IPV4_MCAST_TBL_VALID_DEFAULT 0x0 - /*[field] KEY_TYPE*/ - #define HOST_IPV4_MCAST_TBL_KEY_TYPE - #define HOST_IPV4_MCAST_TBL_KEY_TYPE_OFFSET 1 - #define HOST_IPV4_MCAST_TBL_KEY_TYPE_LEN 2 - #define HOST_IPV4_MCAST_TBL_KEY_TYPE_DEFAULT 0x0 - /*[field] FWD_CMD*/ - #define HOST_IPV4_MCAST_TBL_FWD_CMD - #define HOST_IPV4_MCAST_TBL_FWD_CMD_OFFSET 3 - #define HOST_IPV4_MCAST_TBL_FWD_CMD_LEN 2 - #define HOST_IPV4_MCAST_TBL_FWD_CMD_DEFAULT 0x0 - /*[field] SYN_TOGGLE*/ - #define HOST_IPV4_MCAST_TBL_SYN_TOGGLE - #define HOST_IPV4_MCAST_TBL_SYN_TOGGLE_OFFSET 5 - #define HOST_IPV4_MCAST_TBL_SYN_TOGGLE_LEN 1 - #define HOST_IPV4_MCAST_TBL_SYN_TOGGLE_DEFAULT 0x0 - /*[field] DST_INFO*/ - #define HOST_IPV4_MCAST_TBL_DST_INFO - #define HOST_IPV4_MCAST_TBL_DST_INFO_OFFSET 6 - #define HOST_IPV4_MCAST_TBL_DST_INFO_LEN 14 - #define HOST_IPV4_MCAST_TBL_DST_INFO_DEFAULT 0x0 - /*[field] LAN_WAN*/ - #define HOST_IPV4_MCAST_TBL_LAN_WAN - #define HOST_IPV4_MCAST_TBL_LAN_WAN_OFFSET 20 - #define HOST_IPV4_MCAST_TBL_LAN_WAN_LEN 1 - #define HOST_IPV4_MCAST_TBL_LAN_WAN_DEFAULT 0x0 - /*[field] VSI*/ - #define HOST_IPV4_MCAST_TBL_VSI - #define HOST_IPV4_MCAST_TBL_VSI_OFFSET 21 - #define HOST_IPV4_MCAST_TBL_VSI_LEN 5 - #define HOST_IPV4_MCAST_TBL_VSI_DEFAULT 0x0 - /*[field] SIP_ADDR*/ - #define HOST_IPV4_MCAST_TBL_SIP_ADDR - #define HOST_IPV4_MCAST_TBL_SIP_ADDR_OFFSET 85 - #define HOST_IPV4_MCAST_TBL_SIP_ADDR_LEN 32 - #define HOST_IPV4_MCAST_TBL_SIP_ADDR_DEFAULT 0x0 - /*[field] GIP_ADDR*/ - #define HOST_IPV4_MCAST_TBL_GIP_ADDR - #define HOST_IPV4_MCAST_TBL_GIP_ADDR_OFFSET 117 - #define HOST_IPV4_MCAST_TBL_GIP_ADDR_LEN 32 - #define HOST_IPV4_MCAST_TBL_GIP_ADDR_DEFAULT 0x0 - -struct host_ipv6_tbl { - a_uint32_t valid:1; - a_uint32_t key_type:2; - a_uint32_t fwd_cmd:2; - a_uint32_t syn_toggle:1; - a_uint32_t dst_info:14; - a_uint32_t lan_wan:1; - a_uint32_t _reserved0:1; - a_uint32_t ipv6_addr_0:10; - a_uint32_t ipv6_addr_1:32; - a_uint32_t ipv6_addr_2:32; - a_uint32_t ipv6_addr_3:32; - a_uint32_t ipv6_addr_4:22; - a_uint32_t _reserved1:10; -}; - -union host_ipv6_tbl_u { - a_uint32_t val[5]; - struct host_ipv6_tbl bf; -}; - -/*[table] HOST_TBL*/ -#define HOST_TBL -#define HOST_TBL_ADDRESS 0x20000 -#define HOST_TBL_NUM 6144 -#define HOST_TBL_INC 0x10 -#define HOST_TBL_TYPE REG_TYPE_RW -#define HOST_TBL_DEFAULT 0x0 - /*[field] VALID*/ - #define HOST_TBL_VALID - #define HOST_TBL_VALID_OFFSET 0 - #define HOST_TBL_VALID_LEN 1 - #define HOST_TBL_VALID_DEFAULT 0x0 - /*[field] KEY_TYPE*/ - #define HOST_TBL_KEY_TYPE - #define HOST_TBL_KEY_TYPE_OFFSET 1 - #define HOST_TBL_KEY_TYPE_LEN 2 - #define HOST_TBL_KEY_TYPE_DEFAULT 0x0 - /*[field] FWD_CMD*/ - #define HOST_TBL_FWD_CMD - #define HOST_TBL_FWD_CMD_OFFSET 3 - #define HOST_TBL_FWD_CMD_LEN 2 - #define HOST_TBL_FWD_CMD_DEFAULT 0x0 - /*[field] SYN_TOGGLE*/ - #define HOST_TBL_SYN_TOGGLE - #define HOST_TBL_SYN_TOGGLE_OFFSET 5 - #define HOST_TBL_SYN_TOGGLE_LEN 1 - #define HOST_TBL_SYN_TOGGLE_DEFAULT 0x0 - /*[field] DST_INFO*/ - #define HOST_TBL_DST_INFO - #define HOST_TBL_DST_INFO_OFFSET 6 - #define HOST_TBL_DST_INFO_LEN 14 - #define HOST_TBL_DST_INFO_DEFAULT 0x0 - /*[field] LAN_WAN*/ - #define HOST_TBL_LAN_WAN - #define HOST_TBL_LAN_WAN_OFFSET 20 - #define HOST_TBL_LAN_WAN_LEN 1 - #define HOST_TBL_LAN_WAN_DEFAULT 0x0 - /*[field] IP_ADDR*/ - #define HOST_TBL_IP_ADDR - #define HOST_TBL_IP_ADDR_OFFSET 32 - #define HOST_TBL_IP_ADDR_LEN 32 - #define HOST_TBL_IP_ADDR_DEFAULT 0x0 - -struct host_ipv4_mcast_tbl { - a_uint32_t valid:1; - a_uint32_t key_type:2; - a_uint32_t fwd_cmd:2; - a_uint32_t syn_toggle:1; - a_uint32_t dst_info:14; - a_uint32_t lan_wan:1; - a_uint32_t vsi:5; - a_uint32_t _reserved0_0:6; - a_uint32_t _reserved0_1:32; - a_uint32_t _reserved0_2:21; - a_uint32_t sip_addr_0:11; - a_uint32_t sip_addr_1:21; - a_uint32_t gip_addr_0:11; - a_uint32_t gip_addr_1:21; - a_uint32_t _reserved1:11; -}; - -union host_ipv4_mcast_tbl_u { - a_uint32_t val[5]; - struct host_ipv4_mcast_tbl bf; -}; - -/*[table] HOST_IPV6_TBL*/ -#define HOST_IPV6_TBL -#define HOST_IPV6_TBL_ADDRESS 0x20000 -#define HOST_IPV6_TBL_NUM 3072 -#define HOST_IPV6_TBL_INC 0x20 -#define HOST_IPV6_TBL_TYPE REG_TYPE_RW -#define HOST_IPV6_TBL_DEFAULT 0x0 - /*[field] VALID*/ - #define HOST_IPV6_TBL_VALID - #define HOST_IPV6_TBL_VALID_OFFSET 0 - #define HOST_IPV6_TBL_VALID_LEN 1 - #define HOST_IPV6_TBL_VALID_DEFAULT 0x0 - /*[field] KEY_TYPE*/ - #define HOST_IPV6_TBL_KEY_TYPE - #define HOST_IPV6_TBL_KEY_TYPE_OFFSET 1 - #define HOST_IPV6_TBL_KEY_TYPE_LEN 2 - #define HOST_IPV6_TBL_KEY_TYPE_DEFAULT 0x0 - /*[field] FWD_CMD*/ - #define HOST_IPV6_TBL_FWD_CMD - #define HOST_IPV6_TBL_FWD_CMD_OFFSET 3 - #define HOST_IPV6_TBL_FWD_CMD_LEN 2 - #define HOST_IPV6_TBL_FWD_CMD_DEFAULT 0x0 - /*[field] SYN_TOGGLE*/ - #define HOST_IPV6_TBL_SYN_TOGGLE - #define HOST_IPV6_TBL_SYN_TOGGLE_OFFSET 5 - #define HOST_IPV6_TBL_SYN_TOGGLE_LEN 1 - #define HOST_IPV6_TBL_SYN_TOGGLE_DEFAULT 0x0 - /*[field] DST_INFO*/ - #define HOST_IPV6_TBL_DST_INFO - #define HOST_IPV6_TBL_DST_INFO_OFFSET 6 - #define HOST_IPV6_TBL_DST_INFO_LEN 14 - #define HOST_IPV6_TBL_DST_INFO_DEFAULT 0x0 - /*[field] LAN_WAN*/ - #define HOST_IPV6_TBL_LAN_WAN - #define HOST_IPV6_TBL_LAN_WAN_OFFSET 20 - #define HOST_IPV6_TBL_LAN_WAN_LEN 1 - #define HOST_IPV6_TBL_LAN_WAN_DEFAULT 0x0 - /*[field] IPV6_ADDR*/ - #define HOST_IPV6_TBL_IPV6_ADDR - #define HOST_IPV6_TBL_IPV6_ADDR_OFFSET 22 - #define HOST_IPV6_TBL_IPV6_ADDR_LEN 128 - #define HOST_IPV6_TBL_IPV6_ADDR_DEFAULT 0x0 - -struct host_ipv6_mcast_tbl { - a_uint32_t valid:1; - a_uint32_t key_type:2; - a_uint32_t fwd_cmd:2; - a_uint32_t syn_toggle:1; - a_uint32_t dst_info:14; - a_uint32_t lan_wan:1; - a_uint32_t vsi:5; - a_uint32_t _reserved0_0:6; - a_uint32_t _reserved0_1:12; - a_uint32_t sipv6_addr_0:20; - a_uint32_t sipv6_addr_1:32; - a_uint32_t sipv6_addr_2:32; - a_uint32_t sipv6_addr_3:32; - a_uint32_t sipv6_addr_4:12; - a_uint32_t gipv6_addr_0:20; - a_uint32_t gipv6_addr_1:32; - a_uint32_t gipv6_addr_2:32; - a_uint32_t gipv6_addr_3:32; - a_uint32_t gipv6_addr_4:12; - a_uint32_t _reserved1:20; -}; - -union host_ipv6_mcast_tbl_u { - a_uint32_t val[10]; - struct host_ipv6_mcast_tbl bf; -}; - -/*[table] IN_NEXTHOP_TBL*/ -#define IN_NEXTHOP_TBL -#define IN_NEXTHOP_TBL_ADDRESS 0x60000 -#define IN_NEXTHOP_TBL_NUM 2560 -#define IN_NEXTHOP_TBL_INC 0x10 -#define IN_NEXTHOP_TBL_TYPE REG_TYPE_RW -#define IN_NEXTHOP_TBL_DEFAULT 0x0 - /*[field] TYPE*/ - #define IN_NEXTHOP_TBL_TYPE_F - #define IN_NEXTHOP_TBL_TYPE_F_OFFSET 0 - #define IN_NEXTHOP_TBL_TYPE_F_LEN 1 - #define IN_NEXTHOP_TBL_TYPE_F_DEFAULT 0x0 - /*[field] PORT reuse TYPE[0]*/ - #define IN_NEXTHOP_TBL_PORT - #define IN_NEXTHOP_TBL_PORT_OFFSET 1 - #define IN_NEXTHOP_TBL_PORT_LEN 8 - #define IN_NEXTHOP_TBL_PORT_DEFAULT 0x0 - /*[field] VSI reuse TYPE[1]*/ - #define IN_NEXTHOP_TBL_VSI - #define IN_NEXTHOP_TBL_VSI_OFFSET 1 - #define IN_NEXTHOP_TBL_VSI_LEN 5 - #define IN_NEXTHOP_TBL_VSI_DEFAULT 0x0 - /*[field] POST_L3_IF*/ - #define IN_NEXTHOP_TBL_POST_L3_IF - #define IN_NEXTHOP_TBL_POST_L3_IF_OFFSET 9 - #define IN_NEXTHOP_TBL_POST_L3_IF_LEN 8 - #define IN_NEXTHOP_TBL_POST_L3_IF_DEFAULT 0x0 - /*[field] IP_TO_ME*/ - #define IN_NEXTHOP_TBL_IP_TO_ME - #define IN_NEXTHOP_TBL_IP_TO_ME_OFFSET 17 - #define IN_NEXTHOP_TBL_IP_TO_ME_LEN 1 - #define IN_NEXTHOP_TBL_IP_TO_ME_DEFAULT 0x0 - /*[field] STAG_FMT*/ - #define IN_NEXTHOP_TBL_STAG_FMT - #define IN_NEXTHOP_TBL_STAG_FMT_OFFSET 18 - #define IN_NEXTHOP_TBL_STAG_FMT_LEN 1 - #define IN_NEXTHOP_TBL_STAG_FMT_DEFAULT 0x0 - /*[field] SVID*/ - #define IN_NEXTHOP_TBL_SVID - #define IN_NEXTHOP_TBL_SVID_OFFSET 19 - #define IN_NEXTHOP_TBL_SVID_LEN 12 - #define IN_NEXTHOP_TBL_SVID_DEFAULT 0x0 - /*[field] CTAG_FMT*/ - #define IN_NEXTHOP_TBL_CTAG_FMT - #define IN_NEXTHOP_TBL_CTAG_FMT_OFFSET 31 - #define IN_NEXTHOP_TBL_CTAG_FMT_LEN 1 - #define IN_NEXTHOP_TBL_CTAG_FMT_DEFAULT 0x0 - /*[field] CVID*/ - #define IN_NEXTHOP_TBL_CVID - #define IN_NEXTHOP_TBL_CVID_OFFSET 32 - #define IN_NEXTHOP_TBL_CVID_LEN 12 - #define IN_NEXTHOP_TBL_CVID_DEFAULT 0x0 - /*[field] IP_PUB_ADDR_INDEX*/ - #define IN_NEXTHOP_TBL_IP_PUB_ADDR_INDEX - #define IN_NEXTHOP_TBL_IP_PUB_ADDR_INDEX_OFFSET 44 - #define IN_NEXTHOP_TBL_IP_PUB_ADDR_INDEX_LEN 4 - #define IN_NEXTHOP_TBL_IP_PUB_ADDR_INDEX_DEFAULT 0x0 - /*[field] MAC_ADDR*/ - #define IN_NEXTHOP_TBL_MAC_ADDR - #define IN_NEXTHOP_TBL_MAC_ADDR_OFFSET 48 - #define IN_NEXTHOP_TBL_MAC_ADDR_LEN 48 - #define IN_NEXTHOP_TBL_MAC_ADDR_DEFAULT 0x0 - /*[field] IP_ADDR_DNAT*/ - #define IN_NEXTHOP_TBL_IP_ADDR_DNAT - #define IN_NEXTHOP_TBL_IP_ADDR_DNAT_OFFSET 96 - #define IN_NEXTHOP_TBL_IP_ADDR_DNAT_LEN 32 - #define IN_NEXTHOP_TBL_IP_ADDR_DNAT_DEFAULT 0x0 - -struct in_nexthop_tbl_1 { - a_uint32_t type:1; - a_uint32_t vsi:5; - a_uint32_t _reserved0:3; - a_uint32_t post_l3_if:8; - a_uint32_t ip_to_me:1; - a_uint32_t stag_fmt:1; - a_uint32_t svid:12; - a_uint32_t ctag_fmt:1; - a_uint32_t cvid:12; - a_uint32_t ip_pub_addr_index:4; - a_uint32_t mac_addr_0:16; - a_uint32_t mac_addr_1:32; - a_uint32_t ip_addr_dnat:32; -}; - -struct in_nexthop_tbl_0 { - a_uint32_t type:1; - a_uint32_t port:8; - a_uint32_t post_l3_if:8; - a_uint32_t ip_to_me:1; - a_uint32_t stag_fmt:1; - a_uint32_t svid:12; - a_uint32_t ctag_fmt:1; - a_uint32_t cvid:12; - a_uint32_t ip_pub_addr_index:4; - a_uint32_t mac_addr_0:16; - a_uint32_t mac_addr_1:32; - a_uint32_t ip_addr_dnat:32; -}; - -union in_nexthop_tbl_u { - a_uint32_t val[4]; - struct in_nexthop_tbl_0 bf0; - struct in_nexthop_tbl_1 bf1; -}; - -/*[table] EG_L3_IF_TBL*/ -#define EG_L3_IF_TBL -#define EG_L3_IF_TBL_ADDRESS 0xe000 -#define EG_L3_IF_TBL_NUM 256 -#define EG_L3_IF_TBL_INC 0x10 -#define EG_L3_IF_TBL_TYPE REG_TYPE_RW -#define EG_L3_IF_TBL_DEFAULT 0x0 - /*[field] MAC_ADDR*/ - #define EG_L3_IF_TBL_MAC_ADDR - #define EG_L3_IF_TBL_MAC_ADDR_OFFSET 0 - #define EG_L3_IF_TBL_MAC_ADDR_LEN 48 - #define EG_L3_IF_TBL_MAC_ADDR_DEFAULT 0x0 - /*[field] SESSION_ID*/ - #define EG_L3_IF_TBL_SESSION_ID - #define EG_L3_IF_TBL_SESSION_ID_OFFSET 48 - #define EG_L3_IF_TBL_SESSION_ID_LEN 16 - #define EG_L3_IF_TBL_SESSION_ID_DEFAULT 0x0 - /*[field] PPPOE_EN*/ - #define EG_L3_IF_TBL_PPPOE_EN - #define EG_L3_IF_TBL_PPPOE_EN_OFFSET 64 - #define EG_L3_IF_TBL_PPPOE_EN_LEN 1 - #define EG_L3_IF_TBL_PPPOE_EN_DEFAULT 0x0 - -struct eg_l3_if_tbl { - a_uint32_t mac_addr_0:32; - a_uint32_t mac_addr_1:16; - a_uint32_t session_id:16; - a_uint32_t pppoe_en:1; - a_uint32_t _reserved0:31; -}; - -union eg_l3_if_tbl_u { - a_uint32_t val[3]; - struct eg_l3_if_tbl bf; -}; - -/*[table] RT_INTERFACE_CNT_TBL*/ -#define RT_INTERFACE_CNT_TBL -#define RT_INTERFACE_CNT_TBL_ADDRESS 0x40000 -#define RT_INTERFACE_CNT_TBL_NUM 512 -#define RT_INTERFACE_CNT_TBL_INC 0x20 -#define RT_INTERFACE_CNT_TBL_TYPE REG_TYPE_RW -#define RT_INTERFACE_CNT_TBL_DEFAULT 0x0 - /*[field] PKT_CNT*/ - #define RT_INTERFACE_CNT_TBL_PKT_CNT - #define RT_INTERFACE_CNT_TBL_PKT_CNT_OFFSET 0 - #define RT_INTERFACE_CNT_TBL_PKT_CNT_LEN 32 - #define RT_INTERFACE_CNT_TBL_PKT_CNT_DEFAULT 0x0 - /*[field] BYTE_CNT*/ - #define RT_INTERFACE_CNT_TBL_BYTE_CNT - #define RT_INTERFACE_CNT_TBL_BYTE_CNT_OFFSET 32 - #define RT_INTERFACE_CNT_TBL_BYTE_CNT_LEN 40 - #define RT_INTERFACE_CNT_TBL_BYTE_CNT_DEFAULT 0x0 - /*[field] DROP_PKT_CNT*/ - #define RT_INTERFACE_CNT_TBL_DROP_PKT_CNT - #define RT_INTERFACE_CNT_TBL_DROP_PKT_CNT_OFFSET 72 - #define RT_INTERFACE_CNT_TBL_DROP_PKT_CNT_LEN 32 - #define RT_INTERFACE_CNT_TBL_DROP_PKT_CNT_DEFAULT 0x0 - /*[field] DROP_BYTE_CNT*/ - #define RT_INTERFACE_CNT_TBL_DROP_BYTE_CNT - #define RT_INTERFACE_CNT_TBL_DROP_BYTE_CNT_OFFSET 104 - #define RT_INTERFACE_CNT_TBL_DROP_BYTE_CNT_LEN 40 - #define RT_INTERFACE_CNT_TBL_DROP_BYTE_CNT_DEFAULT 0x0 - -struct rt_interface_cnt_tbl { - a_uint32_t pkt_cnt:32; - a_uint32_t byte_cnt_0:32; - a_uint32_t byte_cnt_1:8; - a_uint32_t drop_pkt_cnt_0:24; - a_uint32_t drop_pkt_cnt_1:8; - a_uint32_t drop_byte_cnt_0:24; - a_uint32_t drop_byte_cnt_1:16; - a_uint32_t _reserved0:16; -}; - -union rt_interface_cnt_tbl_u { - a_uint32_t val[5]; - struct rt_interface_cnt_tbl bf; -}; - - - -#endif diff --git a/feeds/ipq807x/qca-ssdk/src/include/hsl/hppe/hppe_mib.h b/feeds/ipq807x/qca-ssdk/src/include/hsl/hppe/hppe_mib.h deleted file mode 100755 index a80dd304d..000000000 --- a/feeds/ipq807x/qca-ssdk/src/include/hsl/hppe/hppe_mib.h +++ /dev/null @@ -1,1150 +0,0 @@ -/* - * Copyright (c) 2016-2017, The Linux Foundation. All rights reserved. - * Permission to use, copy, modify, and/or distribute this software for - * any purpose with or without fee is hereby granted, provided that the - * above copyright notice and this permission notice appear in all copies. - * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES - * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR - * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES - * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN - * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT - * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. - */ - - -/** - * @defgroup - * @{ - */ -#ifndef _HPPE_MIB_H_ -#define _HPPE_MIB_H_ - -#define MAC_MIB_CTRL_MAX_ENTRY 6 -#define RXBROAD_MAX_ENTRY 6 -#define RXPAUSE_MAX_ENTRY 6 -#define RXMULTI_MAX_ENTRY 6 -#define RXFCSERR_MAX_ENTRY 6 -#define RXALIGNERR_MAX_ENTRY 6 -#define RXRUNT_MAX_ENTRY 6 -#define RXFRAG_MAX_ENTRY 6 -#define RXJUMBOFCSERR_MAX_ENTRY 6 -#define RXJUMBOALIGNERR_MAX_ENTRY 6 -#define RXPKT64_MAX_ENTRY 6 -#define RXPKT65TO127_MAX_ENTRY 6 -#define RXPKT128TO255_MAX_ENTRY 6 -#define RXPKT256TO511_MAX_ENTRY 6 -#define RXPKT512TO1023_MAX_ENTRY 6 -#define RXPKT1024TO1518_MAX_ENTRY 6 -#define RXPKT1519TOX_MAX_ENTRY 6 -#define RXTOOLONG_MAX_ENTRY 6 -#define RXGOODBYTE_L_MAX_ENTRY 6 -#define RXGOODBYTE_H_MAX_ENTRY 6 -#define RXBADBYTE_L_MAX_ENTRY 6 -#define RXBADBYTE_H_MAX_ENTRY 6 -#define RXUNI_MAX_ENTRY 6 -#define TXBROAD_MAX_ENTRY 6 -#define TXPAUSE_MAX_ENTRY 6 -#define TXMULTI_MAX_ENTRY 6 -#define TXUNDERRUN_MAX_ENTRY 6 -#define TXPKT64_MAX_ENTRY 6 -#define TXPKT65TO127_MAX_ENTRY 6 -#define TXPKT128TO255_MAX_ENTRY 6 -#define TXPKT256TO511_MAX_ENTRY 6 -#define TXPKT512TO1023_MAX_ENTRY 6 -#define TXPKT1024TO1518_MAX_ENTRY 6 -#define TXPKT1519TOX_MAX_ENTRY 6 -#define TXBYTE_L_MAX_ENTRY 6 -#define TXBYTE_H_MAX_ENTRY 6 -#define TXCOLLISIONS_MAX_ENTRY 6 -#define TXABORTCOL_MAX_ENTRY 6 -#define TXMULTICOL_MAX_ENTRY 6 -#define TXSINGLECOL_MAX_ENTRY 6 -#define TXEXCESSIVEDEFER_MAX_ENTRY 6 -#define TXDEFER_MAX_ENTRY 6 -#define TXLATECOL_MAX_ENTRY 6 -#define TXUNI_MAX_ENTRY 6 - - -sw_error_t -hppe_mac_mib_ctrl_get( - a_uint32_t dev_id, - a_uint32_t index, - union mac_mib_ctrl_u *value); - -sw_error_t -hppe_mac_mib_ctrl_set( - a_uint32_t dev_id, - a_uint32_t index, - union mac_mib_ctrl_u *value); - -sw_error_t -hppe_rxbroad_get( - a_uint32_t dev_id, - a_uint32_t index, - union rxbroad_u *value); - -sw_error_t -hppe_rxbroad_set( - a_uint32_t dev_id, - a_uint32_t index, - union rxbroad_u *value); - -sw_error_t -hppe_rxpause_get( - a_uint32_t dev_id, - a_uint32_t index, - union rxpause_u *value); - -sw_error_t -hppe_rxpause_set( - a_uint32_t dev_id, - a_uint32_t index, - union rxpause_u *value); - -sw_error_t -hppe_rxmulti_get( - a_uint32_t dev_id, - a_uint32_t index, - union rxmulti_u *value); - -sw_error_t -hppe_rxmulti_set( - a_uint32_t dev_id, - a_uint32_t index, - union rxmulti_u *value); - -sw_error_t -hppe_rxfcserr_get( - a_uint32_t dev_id, - a_uint32_t index, - union rxfcserr_u *value); - -sw_error_t -hppe_rxfcserr_set( - a_uint32_t dev_id, - a_uint32_t index, - union rxfcserr_u *value); - -sw_error_t -hppe_rxalignerr_get( - a_uint32_t dev_id, - a_uint32_t index, - union rxalignerr_u *value); - -sw_error_t -hppe_rxalignerr_set( - a_uint32_t dev_id, - a_uint32_t index, - union rxalignerr_u *value); - -sw_error_t -hppe_rxrunt_get( - a_uint32_t dev_id, - a_uint32_t index, - union rxrunt_u *value); - -sw_error_t -hppe_rxrunt_set( - a_uint32_t dev_id, - a_uint32_t index, - union rxrunt_u *value); - -sw_error_t -hppe_rxfrag_get( - a_uint32_t dev_id, - a_uint32_t index, - union rxfrag_u *value); - -sw_error_t -hppe_rxfrag_set( - a_uint32_t dev_id, - a_uint32_t index, - union rxfrag_u *value); - -sw_error_t -hppe_rxjumbofcserr_get( - a_uint32_t dev_id, - a_uint32_t index, - union rxjumbofcserr_u *value); - -sw_error_t -hppe_rxjumbofcserr_set( - a_uint32_t dev_id, - a_uint32_t index, - union rxjumbofcserr_u *value); - -sw_error_t -hppe_rxjumboalignerr_get( - a_uint32_t dev_id, - a_uint32_t index, - union rxjumboalignerr_u *value); - -sw_error_t -hppe_rxjumboalignerr_set( - a_uint32_t dev_id, - a_uint32_t index, - union rxjumboalignerr_u *value); - -sw_error_t -hppe_rxpkt64_get( - a_uint32_t dev_id, - a_uint32_t index, - union rxpkt64_u *value); - -sw_error_t -hppe_rxpkt64_set( - a_uint32_t dev_id, - a_uint32_t index, - union rxpkt64_u *value); - -sw_error_t -hppe_rxpkt65to127_get( - a_uint32_t dev_id, - a_uint32_t index, - union rxpkt65to127_u *value); - -sw_error_t -hppe_rxpkt65to127_set( - a_uint32_t dev_id, - a_uint32_t index, - union rxpkt65to127_u *value); - -sw_error_t -hppe_rxpkt128to255_get( - a_uint32_t dev_id, - a_uint32_t index, - union rxpkt128to255_u *value); - -sw_error_t -hppe_rxpkt128to255_set( - a_uint32_t dev_id, - a_uint32_t index, - union rxpkt128to255_u *value); - -sw_error_t -hppe_rxpkt256to511_get( - a_uint32_t dev_id, - a_uint32_t index, - union rxpkt256to511_u *value); - -sw_error_t -hppe_rxpkt256to511_set( - a_uint32_t dev_id, - a_uint32_t index, - union rxpkt256to511_u *value); - -sw_error_t -hppe_rxpkt512to1023_get( - a_uint32_t dev_id, - a_uint32_t index, - union rxpkt512to1023_u *value); - -sw_error_t -hppe_rxpkt512to1023_set( - a_uint32_t dev_id, - a_uint32_t index, - union rxpkt512to1023_u *value); - -sw_error_t -hppe_rxpkt1024to1518_get( - a_uint32_t dev_id, - a_uint32_t index, - union rxpkt1024to1518_u *value); - -sw_error_t -hppe_rxpkt1024to1518_set( - a_uint32_t dev_id, - a_uint32_t index, - union rxpkt1024to1518_u *value); - -sw_error_t -hppe_rxpkt1519tox_get( - a_uint32_t dev_id, - a_uint32_t index, - union rxpkt1519tox_u *value); - -sw_error_t -hppe_rxpkt1519tox_set( - a_uint32_t dev_id, - a_uint32_t index, - union rxpkt1519tox_u *value); - -sw_error_t -hppe_rxtoolong_get( - a_uint32_t dev_id, - a_uint32_t index, - union rxtoolong_u *value); - -sw_error_t -hppe_rxtoolong_set( - a_uint32_t dev_id, - a_uint32_t index, - union rxtoolong_u *value); - -sw_error_t -hppe_rxgoodbyte_l_get( - a_uint32_t dev_id, - a_uint32_t index, - union rxgoodbyte_l_u *value); - -sw_error_t -hppe_rxgoodbyte_l_set( - a_uint32_t dev_id, - a_uint32_t index, - union rxgoodbyte_l_u *value); - -sw_error_t -hppe_rxgoodbyte_h_get( - a_uint32_t dev_id, - a_uint32_t index, - union rxgoodbyte_h_u *value); - -sw_error_t -hppe_rxgoodbyte_h_set( - a_uint32_t dev_id, - a_uint32_t index, - union rxgoodbyte_h_u *value); - -sw_error_t -hppe_rxbadbyte_l_get( - a_uint32_t dev_id, - a_uint32_t index, - union rxbadbyte_l_u *value); - -sw_error_t -hppe_rxbadbyte_l_set( - a_uint32_t dev_id, - a_uint32_t index, - union rxbadbyte_l_u *value); - -sw_error_t -hppe_rxbadbyte_h_get( - a_uint32_t dev_id, - a_uint32_t index, - union rxbadbyte_h_u *value); - -sw_error_t -hppe_rxbadbyte_h_set( - a_uint32_t dev_id, - a_uint32_t index, - union rxbadbyte_h_u *value); - -sw_error_t -hppe_rxuni_get( - a_uint32_t dev_id, - a_uint32_t index, - union rxuni_u *value); - -sw_error_t -hppe_rxuni_set( - a_uint32_t dev_id, - a_uint32_t index, - union rxuni_u *value); - -sw_error_t -hppe_txbroad_get( - a_uint32_t dev_id, - a_uint32_t index, - union txbroad_u *value); - -sw_error_t -hppe_txbroad_set( - a_uint32_t dev_id, - a_uint32_t index, - union txbroad_u *value); - -sw_error_t -hppe_txpause_get( - a_uint32_t dev_id, - a_uint32_t index, - union txpause_u *value); - -sw_error_t -hppe_txpause_set( - a_uint32_t dev_id, - a_uint32_t index, - union txpause_u *value); - -sw_error_t -hppe_txmulti_get( - a_uint32_t dev_id, - a_uint32_t index, - union txmulti_u *value); - -sw_error_t -hppe_txmulti_set( - a_uint32_t dev_id, - a_uint32_t index, - union txmulti_u *value); - -sw_error_t -hppe_txunderrun_get( - a_uint32_t dev_id, - a_uint32_t index, - union txunderrun_u *value); - -sw_error_t -hppe_txunderrun_set( - a_uint32_t dev_id, - a_uint32_t index, - union txunderrun_u *value); - -sw_error_t -hppe_txpkt64_get( - a_uint32_t dev_id, - a_uint32_t index, - union txpkt64_u *value); - -sw_error_t -hppe_txpkt64_set( - a_uint32_t dev_id, - a_uint32_t index, - union txpkt64_u *value); - -sw_error_t -hppe_txpkt65to127_get( - a_uint32_t dev_id, - a_uint32_t index, - union txpkt65to127_u *value); - -sw_error_t -hppe_txpkt65to127_set( - a_uint32_t dev_id, - a_uint32_t index, - union txpkt65to127_u *value); - -sw_error_t -hppe_txpkt128to255_get( - a_uint32_t dev_id, - a_uint32_t index, - union txpkt128to255_u *value); - -sw_error_t -hppe_txpkt128to255_set( - a_uint32_t dev_id, - a_uint32_t index, - union txpkt128to255_u *value); - -sw_error_t -hppe_txpkt256to511_get( - a_uint32_t dev_id, - a_uint32_t index, - union txpkt256to511_u *value); - -sw_error_t -hppe_txpkt256to511_set( - a_uint32_t dev_id, - a_uint32_t index, - union txpkt256to511_u *value); - -sw_error_t -hppe_txpkt512to1023_get( - a_uint32_t dev_id, - a_uint32_t index, - union txpkt512to1023_u *value); - -sw_error_t -hppe_txpkt512to1023_set( - a_uint32_t dev_id, - a_uint32_t index, - union txpkt512to1023_u *value); - -sw_error_t -hppe_txpkt1024to1518_get( - a_uint32_t dev_id, - a_uint32_t index, - union txpkt1024to1518_u *value); - -sw_error_t -hppe_txpkt1024to1518_set( - a_uint32_t dev_id, - a_uint32_t index, - union txpkt1024to1518_u *value); - -sw_error_t -hppe_txpkt1519tox_get( - a_uint32_t dev_id, - a_uint32_t index, - union txpkt1519tox_u *value); - -sw_error_t -hppe_txpkt1519tox_set( - a_uint32_t dev_id, - a_uint32_t index, - union txpkt1519tox_u *value); - -sw_error_t -hppe_txbyte_l_get( - a_uint32_t dev_id, - a_uint32_t index, - union txbyte_l_u *value); - -sw_error_t -hppe_txbyte_l_set( - a_uint32_t dev_id, - a_uint32_t index, - union txbyte_l_u *value); - -sw_error_t -hppe_txbyte_h_get( - a_uint32_t dev_id, - a_uint32_t index, - union txbyte_h_u *value); - -sw_error_t -hppe_txbyte_h_set( - a_uint32_t dev_id, - a_uint32_t index, - union txbyte_h_u *value); - -sw_error_t -hppe_txcollisions_get( - a_uint32_t dev_id, - a_uint32_t index, - union txcollisions_u *value); - -sw_error_t -hppe_txcollisions_set( - a_uint32_t dev_id, - a_uint32_t index, - union txcollisions_u *value); - -sw_error_t -hppe_txabortcol_get( - a_uint32_t dev_id, - a_uint32_t index, - union txabortcol_u *value); - -sw_error_t -hppe_txabortcol_set( - a_uint32_t dev_id, - a_uint32_t index, - union txabortcol_u *value); - -sw_error_t -hppe_txmulticol_get( - a_uint32_t dev_id, - a_uint32_t index, - union txmulticol_u *value); - -sw_error_t -hppe_txmulticol_set( - a_uint32_t dev_id, - a_uint32_t index, - union txmulticol_u *value); - -sw_error_t -hppe_txsinglecol_get( - a_uint32_t dev_id, - a_uint32_t index, - union txsinglecol_u *value); - -sw_error_t -hppe_txsinglecol_set( - a_uint32_t dev_id, - a_uint32_t index, - union txsinglecol_u *value); - -sw_error_t -hppe_txexcessivedefer_get( - a_uint32_t dev_id, - a_uint32_t index, - union txexcessivedefer_u *value); - -sw_error_t -hppe_txexcessivedefer_set( - a_uint32_t dev_id, - a_uint32_t index, - union txexcessivedefer_u *value); - -sw_error_t -hppe_txdefer_get( - a_uint32_t dev_id, - a_uint32_t index, - union txdefer_u *value); - -sw_error_t -hppe_txdefer_set( - a_uint32_t dev_id, - a_uint32_t index, - union txdefer_u *value); - -sw_error_t -hppe_txlatecol_get( - a_uint32_t dev_id, - a_uint32_t index, - union txlatecol_u *value); - -sw_error_t -hppe_txlatecol_set( - a_uint32_t dev_id, - a_uint32_t index, - union txlatecol_u *value); - -sw_error_t -hppe_txuni_get( - a_uint32_t dev_id, - a_uint32_t index, - union txuni_u *value); - -sw_error_t -hppe_txuni_set( - a_uint32_t dev_id, - a_uint32_t index, - union txuni_u *value); - -sw_error_t -hppe_mac_mib_ctrl_mib_reset_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_mac_mib_ctrl_mib_reset_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_mac_mib_ctrl_mib_en_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_mac_mib_ctrl_mib_en_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_mac_mib_ctrl_mib_rd_clr_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_mac_mib_ctrl_mib_rd_clr_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_rxbroad_rxbroad_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_rxbroad_rxbroad_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_rxpause_rxpause_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_rxpause_rxpause_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_rxmulti_rxmulti_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_rxmulti_rxmulti_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_rxfcserr_rxfcserr_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_rxfcserr_rxfcserr_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_rxalignerr_rxalignerr_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_rxalignerr_rxalignerr_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_rxrunt_rxrunt_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_rxrunt_rxrunt_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_rxfrag_rxfrag_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_rxfrag_rxfrag_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_rxjumbofcserr_rxjumbofcserr_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_rxjumbofcserr_rxjumbofcserr_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_rxjumboalignerr_rxjumboalignerr_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_rxjumboalignerr_rxjumboalignerr_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_rxpkt64_rxpkt64_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_rxpkt64_rxpkt64_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_rxpkt65to127_rxpkt65to127_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_rxpkt65to127_rxpkt65to127_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_rxpkt128to255_rxpkt128to255_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_rxpkt128to255_rxpkt128to255_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_rxpkt256to511_rxpkt256to511_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_rxpkt256to511_rxpkt256to511_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_rxpkt512to1023_rxpkt512to1023_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_rxpkt512to1023_rxpkt512to1023_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_rxpkt1024to1518_rxpkt1024to1518_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_rxpkt1024to1518_rxpkt1024to1518_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_rxpkt1519tox_rxpkt1519tox_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_rxpkt1519tox_rxpkt1519tox_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_rxtoolong_rxtoolong_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_rxtoolong_rxtoolong_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_rxgoodbyte_l_rxgoodbyte_l_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_rxgoodbyte_l_rxgoodbyte_l_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_rxgoodbyte_h_rxgoodbyte_h_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_rxgoodbyte_h_rxgoodbyte_h_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_rxbadbyte_l_rxbadbyte_l_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_rxbadbyte_l_rxbadbyte_l_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_rxbadbyte_h_rxbadbyte_h_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_rxbadbyte_h_rxbadbyte_h_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_rxuni_rxuni_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_rxuni_rxuni_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_txbroad_txbroad_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_txbroad_txbroad_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_txpause_txpause_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_txpause_txpause_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_txmulti_txmulti_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_txmulti_txmulti_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_txunderrun_txunderrun_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_txunderrun_txunderrun_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_txpkt64_txpkt64_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_txpkt64_txpkt64_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_txpkt65to127_txpkt65to127_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_txpkt65to127_txpkt65to127_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_txpkt128to255_txpkt128to255_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_txpkt128to255_txpkt128to255_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_txpkt256to511_txpkt256to511_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_txpkt256to511_txpkt256to511_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_txpkt512to1023_txpkt512to1023_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_txpkt512to1023_txpkt512to1023_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_txpkt1024to1518_txpkt1024to1518_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_txpkt1024to1518_txpkt1024to1518_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_txpkt1519tox_txpkt1519tox_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_txpkt1519tox_txpkt1519tox_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_txbyte_l_txbyte_l_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_txbyte_l_txbyte_l_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_txbyte_h_txbyte_h_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_txbyte_h_txbyte_h_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_txcollisions_txcollisions_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_txcollisions_txcollisions_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_txabortcol_txabortcol_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_txabortcol_txabortcol_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_txmulticol_txmulticol_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_txmulticol_txmulticol_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_txsinglecol_txsinglecol_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_txsinglecol_txsinglecol_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_txexcessivedefer_txexcessivedefer_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_txexcessivedefer_txexcessivedefer_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_txdefer_txdefer_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_txdefer_txdefer_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_txlatecol_txlatecol_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_txlatecol_txlatecol_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_txuni_txuni_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_txuni_txuni_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -#endif - diff --git a/feeds/ipq807x/qca-ssdk/src/include/hsl/hppe/hppe_mib_reg.h b/feeds/ipq807x/qca-ssdk/src/include/hsl/hppe/hppe_mib_reg.h deleted file mode 100755 index 476d5e805..000000000 --- a/feeds/ipq807x/qca-ssdk/src/include/hsl/hppe/hppe_mib_reg.h +++ /dev/null @@ -1,1006 +0,0 @@ -/* - * Copyright (c) 2016-2017, The Linux Foundation. All rights reserved. - * Permission to use, copy, modify, and/or distribute this software for - * any purpose with or without fee is hereby granted, provided that the - * above copyright notice and this permission notice appear in all copies. - * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES - * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR - * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES - * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN - * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT - * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. - */ - - -/** - * @defgroup - * @{ - */ -#ifndef HPPE_MIB_REG_H -#define HPPE_MIB_REG_H - -/*[register] MAC_MIB_CTRL*/ -#define MAC_MIB_CTRL -#define MAC_MIB_CTRL_ADDRESS 0x34 -#define MAC_MIB_CTRL_NUM 6 -#define MAC_MIB_CTRL_INC 0x200 -#define MAC_MIB_CTRL_TYPE REG_TYPE_RW -#define MAC_MIB_CTRL_DEFAULT 0x0 - /*[field] MIB_EN*/ - #define MAC_MIB_CTRL_MIB_EN - #define MAC_MIB_CTRL_MIB_EN_OFFSET 0 - #define MAC_MIB_CTRL_MIB_EN_LEN 1 - #define MAC_MIB_CTRL_MIB_EN_DEFAULT 0x0 - /*[field] MIB_RESET*/ - #define MAC_MIB_CTRL_MIB_RESET - #define MAC_MIB_CTRL_MIB_RESET_OFFSET 1 - #define MAC_MIB_CTRL_MIB_RESET_LEN 1 - #define MAC_MIB_CTRL_MIB_RESET_DEFAULT 0x0 - /*[field] MIB_RD_CLR*/ - #define MAC_MIB_CTRL_MIB_RD_CLR - #define MAC_MIB_CTRL_MIB_RD_CLR_OFFSET 2 - #define MAC_MIB_CTRL_MIB_RD_CLR_LEN 1 - #define MAC_MIB_CTRL_MIB_RD_CLR_DEFAULT 0x0 - -struct mac_mib_ctrl { - a_uint32_t mib_en:1; - a_uint32_t mib_reset:1; - a_uint32_t mib_rd_clr:1; - a_uint32_t _reserved0:29; -}; - -union mac_mib_ctrl_u { - a_uint32_t val; - struct mac_mib_ctrl bf; -}; - -/*[register] RXBROAD*/ -#define RXBROAD -#define RXBROAD_ADDRESS 0x40 -#define RXBROAD_NUM 6 -#define RXBROAD_INC 0x200 -#define RXBROAD_TYPE REG_TYPE_RO -#define RXBROAD_DEFAULT 0x0 - /*[field] RXBROAD*/ - #define RXBROAD_RXBROAD - #define RXBROAD_RXBROAD_OFFSET 0 - #define RXBROAD_RXBROAD_LEN 32 - #define RXBROAD_RXBROAD_DEFAULT 0x0 - -struct rxbroad { - a_uint32_t rxbroad:32; -}; - -union rxbroad_u { - a_uint32_t val; - struct rxbroad bf; -}; - -/*[register] RXPAUSE*/ -#define RXPAUSE -#define RXPAUSE_ADDRESS 0x44 -#define RXPAUSE_NUM 6 -#define RXPAUSE_INC 0x200 -#define RXPAUSE_TYPE REG_TYPE_RO -#define RXPAUSE_DEFAULT 0x0 - /*[field] RXPAUSE*/ - #define RXPAUSE_RXPAUSE - #define RXPAUSE_RXPAUSE_OFFSET 0 - #define RXPAUSE_RXPAUSE_LEN 32 - #define RXPAUSE_RXPAUSE_DEFAULT 0x0 - -struct rxpause { - a_uint32_t rxpause:32; -}; - -union rxpause_u { - a_uint32_t val; - struct rxpause bf; -}; - -/*[register] RXMULTI*/ -#define RXMULTI -#define RXMULTI_ADDRESS 0x48 -#define RXMULTI_NUM 6 -#define RXMULTI_INC 0x200 -#define RXMULTI_TYPE REG_TYPE_RO -#define RXMULTI_DEFAULT 0x0 - /*[field] RXMULTI*/ - #define RXMULTI_RXMULTI - #define RXMULTI_RXMULTI_OFFSET 0 - #define RXMULTI_RXMULTI_LEN 32 - #define RXMULTI_RXMULTI_DEFAULT 0x0 - -struct rxmulti { - a_uint32_t rxmulti:32; -}; - -union rxmulti_u { - a_uint32_t val; - struct rxmulti bf; -}; - -/*[register] RXFCSERR*/ -#define RXFCSERR -#define RXFCSERR_ADDRESS 0x4c -#define RXFCSERR_NUM 6 -#define RXFCSERR_INC 0x200 -#define RXFCSERR_TYPE REG_TYPE_RO -#define RXFCSERR_DEFAULT 0x0 - /*[field] RXFCSERR*/ - #define RXFCSERR_RXFCSERR - #define RXFCSERR_RXFCSERR_OFFSET 0 - #define RXFCSERR_RXFCSERR_LEN 32 - #define RXFCSERR_RXFCSERR_DEFAULT 0x0 - -struct rxfcserr { - a_uint32_t rxfcserr:32; -}; - -union rxfcserr_u { - a_uint32_t val; - struct rxfcserr bf; -}; - -/*[register] RXALIGNERR*/ -#define RXALIGNERR -#define RXALIGNERR_ADDRESS 0x50 -#define RXALIGNERR_NUM 6 -#define RXALIGNERR_INC 0x200 -#define RXALIGNERR_TYPE REG_TYPE_RO -#define RXALIGNERR_DEFAULT 0x0 - /*[field] RXALIGNERR*/ - #define RXALIGNERR_RXALIGNERR - #define RXALIGNERR_RXALIGNERR_OFFSET 0 - #define RXALIGNERR_RXALIGNERR_LEN 32 - #define RXALIGNERR_RXALIGNERR_DEFAULT 0x0 - -struct rxalignerr { - a_uint32_t rxalignerr:32; -}; - -union rxalignerr_u { - a_uint32_t val; - struct rxalignerr bf; -}; - -/*[register] RXRUNT*/ -#define RXRUNT -#define RXRUNT_ADDRESS 0x54 -#define RXRUNT_NUM 6 -#define RXRUNT_INC 0x200 -#define RXRUNT_TYPE REG_TYPE_RO -#define RXRUNT_DEFAULT 0x0 - /*[field] RXRUNT*/ - #define RXRUNT_RXRUNT - #define RXRUNT_RXRUNT_OFFSET 0 - #define RXRUNT_RXRUNT_LEN 32 - #define RXRUNT_RXRUNT_DEFAULT 0x0 - -struct rxrunt { - a_uint32_t rxrunt:32; -}; - -union rxrunt_u { - a_uint32_t val; - struct rxrunt bf; -}; - -/*[register] RXFRAG*/ -#define RXFRAG -#define RXFRAG_ADDRESS 0x58 -#define RXFRAG_NUM 6 -#define RXFRAG_INC 0x200 -#define RXFRAG_TYPE REG_TYPE_RO -#define RXFRAG_DEFAULT 0x0 - /*[field] RXFRAG*/ - #define RXFRAG_RXFRAG - #define RXFRAG_RXFRAG_OFFSET 0 - #define RXFRAG_RXFRAG_LEN 32 - #define RXFRAG_RXFRAG_DEFAULT 0x0 - -struct rxfrag { - a_uint32_t rxfrag:32; -}; - -union rxfrag_u { - a_uint32_t val; - struct rxfrag bf; -}; - -/*[register] RXJUMBOFCSERR*/ -#define RXJUMBOFCSERR -#define RXJUMBOFCSERR_ADDRESS 0x5c -#define RXJUMBOFCSERR_NUM 6 -#define RXJUMBOFCSERR_INC 0x200 -#define RXJUMBOFCSERR_TYPE REG_TYPE_RO -#define RXJUMBOFCSERR_DEFAULT 0x0 - /*[field] RXJUMBOFCSERR*/ - #define RXJUMBOFCSERR_RXJUMBOFCSERR - #define RXJUMBOFCSERR_RXJUMBOFCSERR_OFFSET 0 - #define RXJUMBOFCSERR_RXJUMBOFCSERR_LEN 32 - #define RXJUMBOFCSERR_RXJUMBOFCSERR_DEFAULT 0x0 - -struct rxjumbofcserr { - a_uint32_t rxjumbofcserr:32; -}; - -union rxjumbofcserr_u { - a_uint32_t val; - struct rxjumbofcserr bf; -}; - -/*[register] RXJUMBOALIGNERR*/ -#define RXJUMBOALIGNERR -#define RXJUMBOALIGNERR_ADDRESS 0x60 -#define RXJUMBOALIGNERR_NUM 6 -#define RXJUMBOALIGNERR_INC 0x200 -#define RXJUMBOALIGNERR_TYPE REG_TYPE_RO -#define RXJUMBOALIGNERR_DEFAULT 0x0 - /*[field] RXJUMBOALIGNERR*/ - #define RXJUMBOALIGNERR_RXJUMBOALIGNERR - #define RXJUMBOALIGNERR_RXJUMBOALIGNERR_OFFSET 0 - #define RXJUMBOALIGNERR_RXJUMBOALIGNERR_LEN 32 - #define RXJUMBOALIGNERR_RXJUMBOALIGNERR_DEFAULT 0x0 - -struct rxjumboalignerr { - a_uint32_t rxjumboalignerr:32; -}; - -union rxjumboalignerr_u { - a_uint32_t val; - struct rxjumboalignerr bf; -}; - -/*[register] RXPKT64*/ -#define RXPKT64 -#define RXPKT64_ADDRESS 0x64 -#define RXPKT64_NUM 6 -#define RXPKT64_INC 0x200 -#define RXPKT64_TYPE REG_TYPE_RO -#define RXPKT64_DEFAULT 0x0 - /*[field] RXPKT64*/ - #define RXPKT64_RXPKT64 - #define RXPKT64_RXPKT64_OFFSET 0 - #define RXPKT64_RXPKT64_LEN 32 - #define RXPKT64_RXPKT64_DEFAULT 0x0 - -struct rxpkt64 { - a_uint32_t rxpkt64:32; -}; - -union rxpkt64_u { - a_uint32_t val; - struct rxpkt64 bf; -}; - -/*[register] RXPKT65TO127*/ -#define RXPKT65TO127 -#define RXPKT65TO127_ADDRESS 0x68 -#define RXPKT65TO127_NUM 6 -#define RXPKT65TO127_INC 0x200 -#define RXPKT65TO127_TYPE REG_TYPE_RO -#define RXPKT65TO127_DEFAULT 0x0 - /*[field] RXPKT65TO127*/ - #define RXPKT65TO127_RXPKT65TO127 - #define RXPKT65TO127_RXPKT65TO127_OFFSET 0 - #define RXPKT65TO127_RXPKT65TO127_LEN 32 - #define RXPKT65TO127_RXPKT65TO127_DEFAULT 0x0 - -struct rxpkt65to127 { - a_uint32_t rxpkt65to127:32; -}; - -union rxpkt65to127_u { - a_uint32_t val; - struct rxpkt65to127 bf; -}; - -/*[register] RXPKT128TO255*/ -#define RXPKT128TO255 -#define RXPKT128TO255_ADDRESS 0x6c -#define RXPKT128TO255_NUM 6 -#define RXPKT128TO255_INC 0x200 -#define RXPKT128TO255_TYPE REG_TYPE_RO -#define RXPKT128TO255_DEFAULT 0x0 - /*[field] RXPKT128TO255*/ - #define RXPKT128TO255_RXPKT128TO255 - #define RXPKT128TO255_RXPKT128TO255_OFFSET 0 - #define RXPKT128TO255_RXPKT128TO255_LEN 32 - #define RXPKT128TO255_RXPKT128TO255_DEFAULT 0x0 - -struct rxpkt128to255 { - a_uint32_t rxpkt128to255:32; -}; - -union rxpkt128to255_u { - a_uint32_t val; - struct rxpkt128to255 bf; -}; - -/*[register] RXPKT256TO511*/ -#define RXPKT256TO511 -#define RXPKT256TO511_ADDRESS 0x70 -#define RXPKT256TO511_NUM 6 -#define RXPKT256TO511_INC 0x200 -#define RXPKT256TO511_TYPE REG_TYPE_RO -#define RXPKT256TO511_DEFAULT 0x0 - /*[field] RXPKT256TO511*/ - #define RXPKT256TO511_RXPKT256TO511 - #define RXPKT256TO511_RXPKT256TO511_OFFSET 0 - #define RXPKT256TO511_RXPKT256TO511_LEN 32 - #define RXPKT256TO511_RXPKT256TO511_DEFAULT 0x0 - -struct rxpkt256to511 { - a_uint32_t rxpkt256to511:32; -}; - -union rxpkt256to511_u { - a_uint32_t val; - struct rxpkt256to511 bf; -}; - -/*[register] RXPKT512TO1023*/ -#define RXPKT512TO1023 -#define RXPKT512TO1023_ADDRESS 0x74 -#define RXPKT512TO1023_NUM 6 -#define RXPKT512TO1023_INC 0x200 -#define RXPKT512TO1023_TYPE REG_TYPE_RO -#define RXPKT512TO1023_DEFAULT 0x0 - /*[field] RXPKT512TO1023*/ - #define RXPKT512TO1023_RXPKT512TO1023 - #define RXPKT512TO1023_RXPKT512TO1023_OFFSET 0 - #define RXPKT512TO1023_RXPKT512TO1023_LEN 32 - #define RXPKT512TO1023_RXPKT512TO1023_DEFAULT 0x0 - -struct rxpkt512to1023 { - a_uint32_t rxpkt512to1023:32; -}; - -union rxpkt512to1023_u { - a_uint32_t val; - struct rxpkt512to1023 bf; -}; - -/*[register] RXPKT1024TO1518*/ -#define RXPKT1024TO1518 -#define RXPKT1024TO1518_ADDRESS 0x78 -#define RXPKT1024TO1518_NUM 6 -#define RXPKT1024TO1518_INC 0x200 -#define RXPKT1024TO1518_TYPE REG_TYPE_RO -#define RXPKT1024TO1518_DEFAULT 0x0 - /*[field] RXPKT1024TO1518*/ - #define RXPKT1024TO1518_RXPKT1024TO1518 - #define RXPKT1024TO1518_RXPKT1024TO1518_OFFSET 0 - #define RXPKT1024TO1518_RXPKT1024TO1518_LEN 32 - #define RXPKT1024TO1518_RXPKT1024TO1518_DEFAULT 0x0 - -struct rxpkt1024to1518 { - a_uint32_t rxpkt1024to1518:32; -}; - -union rxpkt1024to1518_u { - a_uint32_t val; - struct rxpkt1024to1518 bf; -}; - -/*[register] RXPKT1519TOX*/ -#define RXPKT1519TOX -#define RXPKT1519TOX_ADDRESS 0x7c -#define RXPKT1519TOX_NUM 6 -#define RXPKT1519TOX_INC 0x200 -#define RXPKT1519TOX_TYPE REG_TYPE_RO -#define RXPKT1519TOX_DEFAULT 0x0 - /*[field] RXPKT1519TOX*/ - #define RXPKT1519TOX_RXPKT1519TOX - #define RXPKT1519TOX_RXPKT1519TOX_OFFSET 0 - #define RXPKT1519TOX_RXPKT1519TOX_LEN 32 - #define RXPKT1519TOX_RXPKT1519TOX_DEFAULT 0x0 - -struct rxpkt1519tox { - a_uint32_t rxpkt1519tox:32; -}; - -union rxpkt1519tox_u { - a_uint32_t val; - struct rxpkt1519tox bf; -}; - -/*[register] RXTOOLONG*/ -#define RXTOOLONG -#define RXTOOLONG_ADDRESS 0x80 -#define RXTOOLONG_NUM 6 -#define RXTOOLONG_INC 0x200 -#define RXTOOLONG_TYPE REG_TYPE_RO -#define RXTOOLONG_DEFAULT 0x0 - /*[field] RXTOOLONG*/ - #define RXTOOLONG_RXTOOLONG - #define RXTOOLONG_RXTOOLONG_OFFSET 0 - #define RXTOOLONG_RXTOOLONG_LEN 32 - #define RXTOOLONG_RXTOOLONG_DEFAULT 0x0 - -struct rxtoolong { - a_uint32_t rxtoolong:32; -}; - -union rxtoolong_u { - a_uint32_t val; - struct rxtoolong bf; -}; - -/*[register] RXGOODBYTE_L*/ -#define RXGOODBYTE_L -#define RXGOODBYTE_L_ADDRESS 0x84 -#define RXGOODBYTE_L_NUM 6 -#define RXGOODBYTE_L_INC 0x200 -#define RXGOODBYTE_L_TYPE REG_TYPE_RO -#define RXGOODBYTE_L_DEFAULT 0x0 - /*[field] RXGOODBYTE_L*/ - #define RXGOODBYTE_L_RXGOODBYTE_L - #define RXGOODBYTE_L_RXGOODBYTE_L_OFFSET 0 - #define RXGOODBYTE_L_RXGOODBYTE_L_LEN 32 - #define RXGOODBYTE_L_RXGOODBYTE_L_DEFAULT 0x0 - -struct rxgoodbyte_l { - a_uint32_t rxgoodbyte_l:32; -}; - -union rxgoodbyte_l_u { - a_uint32_t val; - struct rxgoodbyte_l bf; -}; - -/*[register] RXGOODBYTE_H*/ -#define RXGOODBYTE_H -#define RXGOODBYTE_H_ADDRESS 0x88 -#define RXGOODBYTE_H_NUM 6 -#define RXGOODBYTE_H_INC 0x200 -#define RXGOODBYTE_H_TYPE REG_TYPE_RO -#define RXGOODBYTE_H_DEFAULT 0x0 - /*[field] RXGOODBYTE_H*/ - #define RXGOODBYTE_H_RXGOODBYTE_H - #define RXGOODBYTE_H_RXGOODBYTE_H_OFFSET 0 - #define RXGOODBYTE_H_RXGOODBYTE_H_LEN 32 - #define RXGOODBYTE_H_RXGOODBYTE_H_DEFAULT 0x0 - -struct rxgoodbyte_h { - a_uint32_t rxgoodbyte_h:32; -}; - -union rxgoodbyte_h_u { - a_uint32_t val; - struct rxgoodbyte_h bf; -}; - -/*[register] RXBADBYTE_L*/ -#define RXBADBYTE_L -#define RXBADBYTE_L_ADDRESS 0x8c -#define RXBADBYTE_L_NUM 6 -#define RXBADBYTE_L_INC 0x200 -#define RXBADBYTE_L_TYPE REG_TYPE_RO -#define RXBADBYTE_L_DEFAULT 0x0 - /*[field] RXBADBYTE_L*/ - #define RXBADBYTE_L_RXBADBYTE_L - #define RXBADBYTE_L_RXBADBYTE_L_OFFSET 0 - #define RXBADBYTE_L_RXBADBYTE_L_LEN 32 - #define RXBADBYTE_L_RXBADBYTE_L_DEFAULT 0x0 - -struct rxbadbyte_l { - a_uint32_t rxbadbyte_l:32; -}; - -union rxbadbyte_l_u { - a_uint32_t val; - struct rxbadbyte_l bf; -}; - -/*[register] RXBADBYTE_H*/ -#define RXBADBYTE_H -#define RXBADBYTE_H_ADDRESS 0x90 -#define RXBADBYTE_H_NUM 6 -#define RXBADBYTE_H_INC 0x200 -#define RXBADBYTE_H_TYPE REG_TYPE_RO -#define RXBADBYTE_H_DEFAULT 0x0 - /*[field] RXBADBYTE_H*/ - #define RXBADBYTE_H_RXBADBYTE_H - #define RXBADBYTE_H_RXBADBYTE_H_OFFSET 0 - #define RXBADBYTE_H_RXBADBYTE_H_LEN 32 - #define RXBADBYTE_H_RXBADBYTE_H_DEFAULT 0x0 - -struct rxbadbyte_h { - a_uint32_t rxbadbyte_h:32; -}; - -union rxbadbyte_h_u { - a_uint32_t val; - struct rxbadbyte_h bf; -}; - -/*[register] RXUNI*/ -#define RXUNI -#define RXUNI_ADDRESS 0x94 -#define RXUNI_NUM 6 -#define RXUNI_INC 0x200 -#define RXUNI_TYPE REG_TYPE_RO -#define RXUNI_DEFAULT 0x0 - /*[field] RXUNI*/ - #define RXUNI_RXUNI - #define RXUNI_RXUNI_OFFSET 0 - #define RXUNI_RXUNI_LEN 32 - #define RXUNI_RXUNI_DEFAULT 0x0 - -struct rxuni { - a_uint32_t rxuni:32; -}; - -union rxuni_u { - a_uint32_t val; - struct rxuni bf; -}; - -/*[register] TXBROAD*/ -#define TXBROAD -#define TXBROAD_ADDRESS 0xa0 -#define TXBROAD_NUM 6 -#define TXBROAD_INC 0x200 -#define TXBROAD_TYPE REG_TYPE_RO -#define TXBROAD_DEFAULT 0x0 - /*[field] TXBROAD*/ - #define TXBROAD_TXBROAD - #define TXBROAD_TXBROAD_OFFSET 0 - #define TXBROAD_TXBROAD_LEN 32 - #define TXBROAD_TXBROAD_DEFAULT 0x0 - -struct txbroad { - a_uint32_t txbroad:32; -}; - -union txbroad_u { - a_uint32_t val; - struct txbroad bf; -}; - -/*[register] TXPAUSE*/ -#define TXPAUSE -#define TXPAUSE_ADDRESS 0xa4 -#define TXPAUSE_NUM 6 -#define TXPAUSE_INC 0x200 -#define TXPAUSE_TYPE REG_TYPE_RO -#define TXPAUSE_DEFAULT 0x0 - /*[field] TXPAUSE*/ - #define TXPAUSE_TXPAUSE - #define TXPAUSE_TXPAUSE_OFFSET 0 - #define TXPAUSE_TXPAUSE_LEN 32 - #define TXPAUSE_TXPAUSE_DEFAULT 0x0 - -struct txpause { - a_uint32_t txpause:32; -}; - -union txpause_u { - a_uint32_t val; - struct txpause bf; -}; - -/*[register] TXMULTI*/ -#define TXMULTI -#define TXMULTI_ADDRESS 0xa8 -#define TXMULTI_NUM 6 -#define TXMULTI_INC 0x200 -#define TXMULTI_TYPE REG_TYPE_RO -#define TXMULTI_DEFAULT 0x0 - /*[field] TXMULTI*/ - #define TXMULTI_TXMULTI - #define TXMULTI_TXMULTI_OFFSET 0 - #define TXMULTI_TXMULTI_LEN 32 - #define TXMULTI_TXMULTI_DEFAULT 0x0 - -struct txmulti { - a_uint32_t txmulti:32; -}; - -union txmulti_u { - a_uint32_t val; - struct txmulti bf; -}; - -/*[register] TXUNDERRUN*/ -#define TXUNDERRUN -#define TXUNDERRUN_ADDRESS 0xac -#define TXUNDERRUN_NUM 6 -#define TXUNDERRUN_INC 0x200 -#define TXUNDERRUN_TYPE REG_TYPE_RO -#define TXUNDERRUN_DEFAULT 0x0 - /*[field] TXUNDERRUN*/ - #define TXUNDERRUN_TXUNDERRUN - #define TXUNDERRUN_TXUNDERRUN_OFFSET 0 - #define TXUNDERRUN_TXUNDERRUN_LEN 32 - #define TXUNDERRUN_TXUNDERRUN_DEFAULT 0x0 - -struct txunderrun { - a_uint32_t txunderrun:32; -}; - -union txunderrun_u { - a_uint32_t val; - struct txunderrun bf; -}; - -/*[register] TXPKT64*/ -#define TXPKT64 -#define TXPKT64_ADDRESS 0xb0 -#define TXPKT64_NUM 6 -#define TXPKT64_INC 0x200 -#define TXPKT64_TYPE REG_TYPE_RO -#define TXPKT64_DEFAULT 0x0 - /*[field] TXPKT64*/ - #define TXPKT64_TXPKT64 - #define TXPKT64_TXPKT64_OFFSET 0 - #define TXPKT64_TXPKT64_LEN 32 - #define TXPKT64_TXPKT64_DEFAULT 0x0 - -struct txpkt64 { - a_uint32_t txpkt64:32; -}; - -union txpkt64_u { - a_uint32_t val; - struct txpkt64 bf; -}; - -/*[register] TXPKT65TO127*/ -#define TXPKT65TO127 -#define TXPKT65TO127_ADDRESS 0xb4 -#define TXPKT65TO127_NUM 6 -#define TXPKT65TO127_INC 0x200 -#define TXPKT65TO127_TYPE REG_TYPE_RO -#define TXPKT65TO127_DEFAULT 0x0 - /*[field] TXPKT65TO127*/ - #define TXPKT65TO127_TXPKT65TO127 - #define TXPKT65TO127_TXPKT65TO127_OFFSET 0 - #define TXPKT65TO127_TXPKT65TO127_LEN 32 - #define TXPKT65TO127_TXPKT65TO127_DEFAULT 0x0 - -struct txpkt65to127 { - a_uint32_t txpkt65to127:32; -}; - -union txpkt65to127_u { - a_uint32_t val; - struct txpkt65to127 bf; -}; - -/*[register] TXPKT128TO255*/ -#define TXPKT128TO255 -#define TXPKT128TO255_ADDRESS 0xb8 -#define TXPKT128TO255_NUM 6 -#define TXPKT128TO255_INC 0x200 -#define TXPKT128TO255_TYPE REG_TYPE_RO -#define TXPKT128TO255_DEFAULT 0x0 - /*[field] TXPKT128TO255*/ - #define TXPKT128TO255_TXPKT128TO255 - #define TXPKT128TO255_TXPKT128TO255_OFFSET 0 - #define TXPKT128TO255_TXPKT128TO255_LEN 32 - #define TXPKT128TO255_TXPKT128TO255_DEFAULT 0x0 - -struct txpkt128to255 { - a_uint32_t txpkt128to255:32; -}; - -union txpkt128to255_u { - a_uint32_t val; - struct txpkt128to255 bf; -}; - -/*[register] TXPKT256TO511*/ -#define TXPKT256TO511 -#define TXPKT256TO511_ADDRESS 0xbc -#define TXPKT256TO511_NUM 6 -#define TXPKT256TO511_INC 0x200 -#define TXPKT256TO511_TYPE REG_TYPE_RO -#define TXPKT256TO511_DEFAULT 0x0 - /*[field] TXPKT256TO511*/ - #define TXPKT256TO511_TXPKT256TO511 - #define TXPKT256TO511_TXPKT256TO511_OFFSET 0 - #define TXPKT256TO511_TXPKT256TO511_LEN 32 - #define TXPKT256TO511_TXPKT256TO511_DEFAULT 0x0 - -struct txpkt256to511 { - a_uint32_t txpkt256to511:32; -}; - -union txpkt256to511_u { - a_uint32_t val; - struct txpkt256to511 bf; -}; - -/*[register] TXPKT512TO1023*/ -#define TXPKT512TO1023 -#define TXPKT512TO1023_ADDRESS 0xc0 -#define TXPKT512TO1023_NUM 6 -#define TXPKT512TO1023_INC 0x200 -#define TXPKT512TO1023_TYPE REG_TYPE_RO -#define TXPKT512TO1023_DEFAULT 0x0 - /*[field] TXPKT512TO1023*/ - #define TXPKT512TO1023_TXPKT512TO1023 - #define TXPKT512TO1023_TXPKT512TO1023_OFFSET 0 - #define TXPKT512TO1023_TXPKT512TO1023_LEN 32 - #define TXPKT512TO1023_TXPKT512TO1023_DEFAULT 0x0 - -struct txpkt512to1023 { - a_uint32_t txpkt512to1023:32; -}; - -union txpkt512to1023_u { - a_uint32_t val; - struct txpkt512to1023 bf; -}; - -/*[register] TXPKT1024TO1518*/ -#define TXPKT1024TO1518 -#define TXPKT1024TO1518_ADDRESS 0xc4 -#define TXPKT1024TO1518_NUM 6 -#define TXPKT1024TO1518_INC 0x200 -#define TXPKT1024TO1518_TYPE REG_TYPE_RO -#define TXPKT1024TO1518_DEFAULT 0x0 - /*[field] TXPKT1024TO1518*/ - #define TXPKT1024TO1518_TXPKT1024TO1518 - #define TXPKT1024TO1518_TXPKT1024TO1518_OFFSET 0 - #define TXPKT1024TO1518_TXPKT1024TO1518_LEN 32 - #define TXPKT1024TO1518_TXPKT1024TO1518_DEFAULT 0x0 - -struct txpkt1024to1518 { - a_uint32_t txpkt1024to1518:32; -}; - -union txpkt1024to1518_u { - a_uint32_t val; - struct txpkt1024to1518 bf; -}; - -/*[register] TXPKT1519TOX*/ -#define TXPKT1519TOX -#define TXPKT1519TOX_ADDRESS 0xc8 -#define TXPKT1519TOX_NUM 6 -#define TXPKT1519TOX_INC 0x200 -#define TXPKT1519TOX_TYPE REG_TYPE_RO -#define TXPKT1519TOX_DEFAULT 0x0 - /*[field] TXPKT1519TOX*/ - #define TXPKT1519TOX_TXPKT1519TOX - #define TXPKT1519TOX_TXPKT1519TOX_OFFSET 0 - #define TXPKT1519TOX_TXPKT1519TOX_LEN 32 - #define TXPKT1519TOX_TXPKT1519TOX_DEFAULT 0x0 - -struct txpkt1519tox { - a_uint32_t txpkt1519tox:32; -}; - -union txpkt1519tox_u { - a_uint32_t val; - struct txpkt1519tox bf; -}; - -/*[register] TXBYTE_L*/ -#define TXBYTE_L -#define TXBYTE_L_ADDRESS 0xcc -#define TXBYTE_L_NUM 6 -#define TXBYTE_L_INC 0x200 -#define TXBYTE_L_TYPE REG_TYPE_RO -#define TXBYTE_L_DEFAULT 0x0 - /*[field] TXBYTE_L*/ - #define TXBYTE_L_TXBYTE_L - #define TXBYTE_L_TXBYTE_L_OFFSET 0 - #define TXBYTE_L_TXBYTE_L_LEN 32 - #define TXBYTE_L_TXBYTE_L_DEFAULT 0x0 - -struct txbyte_l { - a_uint32_t txbyte_l:32; -}; - -union txbyte_l_u { - a_uint32_t val; - struct txbyte_l bf; -}; - -/*[register] TXBYTE_H*/ -#define TXBYTE_H -#define TXBYTE_H_ADDRESS 0xd0 -#define TXBYTE_H_NUM 6 -#define TXBYTE_H_INC 0x200 -#define TXBYTE_H_TYPE REG_TYPE_RO -#define TXBYTE_H_DEFAULT 0x0 - /*[field] TXBYTE_H*/ - #define TXBYTE_H_TXBYTE_H - #define TXBYTE_H_TXBYTE_H_OFFSET 0 - #define TXBYTE_H_TXBYTE_H_LEN 32 - #define TXBYTE_H_TXBYTE_H_DEFAULT 0x0 - -struct txbyte_h { - a_uint32_t txbyte_h:32; -}; - -union txbyte_h_u { - a_uint32_t val; - struct txbyte_h bf; -}; - -/*[register] TXCOLLISIONS*/ -#define TXCOLLISIONS -#define TXCOLLISIONS_ADDRESS 0xd4 -#define TXCOLLISIONS_NUM 6 -#define TXCOLLISIONS_INC 0x200 -#define TXCOLLISIONS_TYPE REG_TYPE_RO -#define TXCOLLISIONS_DEFAULT 0x0 - /*[field] TXCOLLISIONS*/ - #define TXCOLLISIONS_TXCOLLISIONS - #define TXCOLLISIONS_TXCOLLISIONS_OFFSET 0 - #define TXCOLLISIONS_TXCOLLISIONS_LEN 32 - #define TXCOLLISIONS_TXCOLLISIONS_DEFAULT 0x0 - -struct txcollisions { - a_uint32_t txcollisions:32; -}; - -union txcollisions_u { - a_uint32_t val; - struct txcollisions bf; -}; - -/*[register] TXABORTCOL*/ -#define TXABORTCOL -#define TXABORTCOL_ADDRESS 0xd8 -#define TXABORTCOL_NUM 6 -#define TXABORTCOL_INC 0x200 -#define TXABORTCOL_TYPE REG_TYPE_RO -#define TXABORTCOL_DEFAULT 0x0 - /*[field] TXABORTCOL*/ - #define TXABORTCOL_TXABORTCOL - #define TXABORTCOL_TXABORTCOL_OFFSET 0 - #define TXABORTCOL_TXABORTCOL_LEN 32 - #define TXABORTCOL_TXABORTCOL_DEFAULT 0x0 - -struct txabortcol { - a_uint32_t txabortcol:32; -}; - -union txabortcol_u { - a_uint32_t val; - struct txabortcol bf; -}; - -/*[register] TXMULTICOL*/ -#define TXMULTICOL -#define TXMULTICOL_ADDRESS 0xdc -#define TXMULTICOL_NUM 6 -#define TXMULTICOL_INC 0x200 -#define TXMULTICOL_TYPE REG_TYPE_RO -#define TXMULTICOL_DEFAULT 0x0 - /*[field] TXMULTICOL*/ - #define TXMULTICOL_TXMULTICOL - #define TXMULTICOL_TXMULTICOL_OFFSET 0 - #define TXMULTICOL_TXMULTICOL_LEN 32 - #define TXMULTICOL_TXMULTICOL_DEFAULT 0x0 - -struct txmulticol { - a_uint32_t txmulticol:32; -}; - -union txmulticol_u { - a_uint32_t val; - struct txmulticol bf; -}; - -/*[register] TXSINGLECOL*/ -#define TXSINGLECOL -#define TXSINGLECOL_ADDRESS 0xe0 -#define TXSINGLECOL_NUM 6 -#define TXSINGLECOL_INC 0x200 -#define TXSINGLECOL_TYPE REG_TYPE_RO -#define TXSINGLECOL_DEFAULT 0x0 - /*[field] TXSINGLECOL*/ - #define TXSINGLECOL_TXSINGLECOL - #define TXSINGLECOL_TXSINGLECOL_OFFSET 0 - #define TXSINGLECOL_TXSINGLECOL_LEN 32 - #define TXSINGLECOL_TXSINGLECOL_DEFAULT 0x0 - -struct txsinglecol { - a_uint32_t txsinglecol:32; -}; - -union txsinglecol_u { - a_uint32_t val; - struct txsinglecol bf; -}; - -/*[register] TXEXCESSIVEDEFER*/ -#define TXEXCESSIVEDEFER -#define TXEXCESSIVEDEFER_ADDRESS 0xe4 -#define TXEXCESSIVEDEFER_NUM 6 -#define TXEXCESSIVEDEFER_INC 0x200 -#define TXEXCESSIVEDEFER_TYPE REG_TYPE_RO -#define TXEXCESSIVEDEFER_DEFAULT 0x0 - /*[field] TXEXCESSIVEDEFER*/ - #define TXEXCESSIVEDEFER_TXEXCESSIVEDEFER - #define TXEXCESSIVEDEFER_TXEXCESSIVEDEFER_OFFSET 0 - #define TXEXCESSIVEDEFER_TXEXCESSIVEDEFER_LEN 32 - #define TXEXCESSIVEDEFER_TXEXCESSIVEDEFER_DEFAULT 0x0 - -struct txexcessivedefer { - a_uint32_t txexcessivedefer:32; -}; - -union txexcessivedefer_u { - a_uint32_t val; - struct txexcessivedefer bf; -}; - -/*[register] TXDEFER*/ -#define TXDEFER -#define TXDEFER_ADDRESS 0xe8 -#define TXDEFER_NUM 6 -#define TXDEFER_INC 0x200 -#define TXDEFER_TYPE REG_TYPE_RO -#define TXDEFER_DEFAULT 0x0 - /*[field] TXDEFER*/ - #define TXDEFER_TXDEFER - #define TXDEFER_TXDEFER_OFFSET 0 - #define TXDEFER_TXDEFER_LEN 32 - #define TXDEFER_TXDEFER_DEFAULT 0x0 - -struct txdefer { - a_uint32_t txdefer:32; -}; - -union txdefer_u { - a_uint32_t val; - struct txdefer bf; -}; - -/*[register] TXLATECOL*/ -#define TXLATECOL -#define TXLATECOL_ADDRESS 0xec -#define TXLATECOL_NUM 6 -#define TXLATECOL_INC 0x200 -#define TXLATECOL_TYPE REG_TYPE_RO -#define TXLATECOL_DEFAULT 0x0 - /*[field] TXLATECOL*/ - #define TXLATECOL_TXLATECOL - #define TXLATECOL_TXLATECOL_OFFSET 0 - #define TXLATECOL_TXLATECOL_LEN 32 - #define TXLATECOL_TXLATECOL_DEFAULT 0x0 - -struct txlatecol { - a_uint32_t txlatecol:32; -}; - -union txlatecol_u { - a_uint32_t val; - struct txlatecol bf; -}; - -/*[register] TXUNI*/ -#define TXUNI -#define TXUNI_ADDRESS 0xf0 -#define TXUNI_NUM 6 -#define TXUNI_INC 0x200 -#define TXUNI_TYPE REG_TYPE_RO -#define TXUNI_DEFAULT 0x0 - /*[field] TXUNI*/ - #define TXUNI_TXUNI - #define TXUNI_TXUNI_OFFSET 0 - #define TXUNI_TXUNI_LEN 32 - #define TXUNI_TXUNI_DEFAULT 0x0 - -struct txuni { - a_uint32_t txuni:32; -}; - -union txuni_u { - a_uint32_t val; - struct txuni bf; -}; - - - -#endif diff --git a/feeds/ipq807x/qca-ssdk/src/include/hsl/hppe/hppe_mirror.h b/feeds/ipq807x/qca-ssdk/src/include/hsl/hppe/hppe_mirror.h deleted file mode 100755 index c8f3994f3..000000000 --- a/feeds/ipq807x/qca-ssdk/src/include/hsl/hppe/hppe_mirror.h +++ /dev/null @@ -1,92 +0,0 @@ -/* - * Copyright (c) 2016-2017, The Linux Foundation. All rights reserved. - * Permission to use, copy, modify, and/or distribute this software for - * any purpose with or without fee is hereby granted, provided that the - * above copyright notice and this permission notice appear in all copies. - * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES - * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR - * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES - * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN - * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT - * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. - */ - - -/** - * @defgroup - * @{ - */ -#ifndef _HPPE_MIRROR_H_ -#define _HPPE_MIRROR_H_ - -#define PORT_MIRROR_MAX_ENTRY 8 - -sw_error_t -hppe_mirror_analyzer_get( - a_uint32_t dev_id, - union mirror_analyzer_u *value); - -sw_error_t -hppe_mirror_analyzer_set( - a_uint32_t dev_id, - union mirror_analyzer_u *value); - -sw_error_t -hppe_port_mirror_get( - a_uint32_t dev_id, - a_uint32_t index, - union port_mirror_u *value); - -sw_error_t -hppe_port_mirror_set( - a_uint32_t dev_id, - a_uint32_t index, - union port_mirror_u *value); - -sw_error_t -hppe_mirror_analyzer_in_analyzer_port_get( - a_uint32_t dev_id, - unsigned int *value); - -sw_error_t -hppe_mirror_analyzer_in_analyzer_port_set( - a_uint32_t dev_id, - unsigned int value); - -sw_error_t -hppe_mirror_analyzer_eg_analyzer_port_get( - a_uint32_t dev_id, - unsigned int *value); - -sw_error_t -hppe_mirror_analyzer_eg_analyzer_port_set( - a_uint32_t dev_id, - unsigned int value); - -sw_error_t -hppe_port_mirror_in_mirr_en_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_port_mirror_in_mirr_en_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_port_mirror_eg_mirr_en_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_port_mirror_eg_mirr_en_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -#endif - diff --git a/feeds/ipq807x/qca-ssdk/src/include/hsl/hppe/hppe_mirror_reg.h b/feeds/ipq807x/qca-ssdk/src/include/hsl/hppe/hppe_mirror_reg.h deleted file mode 100755 index 45b69a7ce..000000000 --- a/feeds/ipq807x/qca-ssdk/src/include/hsl/hppe/hppe_mirror_reg.h +++ /dev/null @@ -1,83 +0,0 @@ -/* - * Copyright (c) 2016-2017, The Linux Foundation. All rights reserved. - * Permission to use, copy, modify, and/or distribute this software for - * any purpose with or without fee is hereby granted, provided that the - * above copyright notice and this permission notice appear in all copies. - * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES - * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR - * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES - * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN - * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT - * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. - */ - - -/** - * @defgroup - * @{ - */ -#ifndef HPPE_MIRROR_REG_H -#define HPPE_MIRROR_REG_H - -/*[register] MIRROR_ANALYZER*/ -#define MIRROR_ANALYZER -#define MIRROR_ANALYZER_ADDRESS 0x40 -#define MIRROR_ANALYZER_NUM 1 -#define MIRROR_ANALYZER_INC 0x4 -#define MIRROR_ANALYZER_TYPE REG_TYPE_RW -#define MIRROR_ANALYZER_DEFAULT 0x0 - /*[field] IN_ANALYZER_PORT*/ - #define MIRROR_ANALYZER_IN_ANALYZER_PORT - #define MIRROR_ANALYZER_IN_ANALYZER_PORT_OFFSET 0 - #define MIRROR_ANALYZER_IN_ANALYZER_PORT_LEN 6 - #define MIRROR_ANALYZER_IN_ANALYZER_PORT_DEFAULT 0x0 - /*[field] EG_ANALYZER_PORT*/ - #define MIRROR_ANALYZER_EG_ANALYZER_PORT - #define MIRROR_ANALYZER_EG_ANALYZER_PORT_OFFSET 8 - #define MIRROR_ANALYZER_EG_ANALYZER_PORT_LEN 6 - #define MIRROR_ANALYZER_EG_ANALYZER_PORT_DEFAULT 0x0 - -struct mirror_analyzer { - a_uint32_t in_analyzer_port:6; - a_uint32_t _reserved0:2; - a_uint32_t eg_analyzer_port:6; - a_uint32_t _reserved1:18; -}; - -union mirror_analyzer_u { - a_uint32_t val; - struct mirror_analyzer bf; -}; - -/*[register] PORT_MIRROR*/ -#define PORT_MIRROR -#define PORT_MIRROR_ADDRESS 0x800 -#define PORT_MIRROR_NUM 8 -#define PORT_MIRROR_INC 0x4 -#define PORT_MIRROR_TYPE REG_TYPE_RW -#define PORT_MIRROR_DEFAULT 0x0 - /*[field] IN_MIRR_EN*/ - #define PORT_MIRROR_IN_MIRR_EN - #define PORT_MIRROR_IN_MIRR_EN_OFFSET 0 - #define PORT_MIRROR_IN_MIRR_EN_LEN 1 - #define PORT_MIRROR_IN_MIRR_EN_DEFAULT 0x0 - /*[field] EG_MIRR_EN*/ - #define PORT_MIRROR_EG_MIRR_EN - #define PORT_MIRROR_EG_MIRR_EN_OFFSET 1 - #define PORT_MIRROR_EG_MIRR_EN_LEN 1 - #define PORT_MIRROR_EG_MIRR_EN_DEFAULT 0x0 - -struct port_mirror { - a_uint32_t in_mirr_en:1; - a_uint32_t eg_mirr_en:1; - a_uint32_t _reserved0:30; -}; - -union port_mirror_u { - a_uint32_t val; - struct port_mirror bf; -}; - - -#endif diff --git a/feeds/ipq807x/qca-ssdk/src/include/hsl/hppe/hppe_policer.h b/feeds/ipq807x/qca-ssdk/src/include/hsl/hppe/hppe_policer.h deleted file mode 100755 index 92ca03675..000000000 --- a/feeds/ipq807x/qca-ssdk/src/include/hsl/hppe/hppe_policer.h +++ /dev/null @@ -1,1173 +0,0 @@ -/* - * Copyright (c) 2016-2017, The Linux Foundation. All rights reserved. - * Permission to use, copy, modify, and/or distribute this software for - * any purpose with or without fee is hereby granted, provided that the - * above copyright notice and this permission notice appear in all copies. - * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES - * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR - * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES - * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN - * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT - * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. - */ - - -/** - * @defgroup - * @{ - */ -#ifndef _HPPE_POLICER_H_ -#define _HPPE_POLICER_H_ - -#define METER_CMPST_LENGTH_REG_MAX_ENTRY 8 -#define IN_ACL_METER_CFG_TBL_MAX_ENTRY 512 -#define IN_ACL_METER_CRDT_TBL_MAX_ENTRY 512 -#define IN_PORT_METER_CFG_TBL_MAX_ENTRY 8 -#define IN_PORT_METER_CRDT_TBL_MAX_ENTRY 8 -#define IN_PORT_METER_CNT_TBL_MAX_ENTRY 24 -#define IN_ACL_METER_CNT_TBL_MAX_ENTRY 1536 -#define PC_GLOBAL_CNT_TBL_MAX_ENTRY 3 -#define DROP_CPU_CNT_TBL_MAX_ENTRY 1280 -#define CPU_CODE_CNT_TBL_MAX_ENTRY 256 -#define PORT_TX_DROP_CNT_TBL_MAX_ENTRY 8 -#define VP_TX_DROP_CNT_TBL_MAX_ENTRY 256 -#define VLAN_DEV_CNT_TBL_MAX_ENTRY 64 - - -sw_error_t -hppe_meter_cmpst_length_reg_get( - a_uint32_t dev_id, - a_uint32_t index, - union meter_cmpst_length_reg_u *value); - -sw_error_t -hppe_meter_cmpst_length_reg_set( - a_uint32_t dev_id, - a_uint32_t index, - union meter_cmpst_length_reg_u *value); - -sw_error_t -hppe_pc_drop_bypass_reg_get( - a_uint32_t dev_id, - union pc_drop_bypass_reg_u *value); - -sw_error_t -hppe_pc_drop_bypass_reg_set( - a_uint32_t dev_id, - union pc_drop_bypass_reg_u *value); - -sw_error_t -hppe_pc_spare_reg_get( - a_uint32_t dev_id, - union pc_spare_reg_u *value); - -sw_error_t -hppe_pc_spare_reg_set( - a_uint32_t dev_id, - union pc_spare_reg_u *value); - -sw_error_t -hppe_time_slot_reg_get( - a_uint32_t dev_id, - union time_slot_reg_u *value); - -sw_error_t -hppe_time_slot_reg_set( - a_uint32_t dev_id, - union time_slot_reg_u *value); - -sw_error_t -hppe_pc_dbg_addr_reg_get( - a_uint32_t dev_id, - union pc_dbg_addr_reg_u *value); - -sw_error_t -hppe_pc_dbg_addr_reg_set( - a_uint32_t dev_id, - union pc_dbg_addr_reg_u *value); - -sw_error_t -hppe_pc_dbg_data_reg_get( - a_uint32_t dev_id, - union pc_dbg_data_reg_u *value); - -sw_error_t -hppe_pc_dbg_data_reg_set( - a_uint32_t dev_id, - union pc_dbg_data_reg_u *value); - -sw_error_t -hppe_in_acl_meter_cfg_tbl_get( - a_uint32_t dev_id, - a_uint32_t index, - union in_acl_meter_cfg_tbl_u *value); - -sw_error_t -hppe_in_acl_meter_cfg_tbl_set( - a_uint32_t dev_id, - a_uint32_t index, - union in_acl_meter_cfg_tbl_u *value); - -sw_error_t -hppe_in_acl_meter_crdt_tbl_get( - a_uint32_t dev_id, - a_uint32_t index, - union in_acl_meter_crdt_tbl_u *value); - -sw_error_t -hppe_in_acl_meter_crdt_tbl_set( - a_uint32_t dev_id, - a_uint32_t index, - union in_acl_meter_crdt_tbl_u *value); - -sw_error_t -hppe_in_port_meter_cfg_tbl_get( - a_uint32_t dev_id, - a_uint32_t index, - union in_port_meter_cfg_tbl_u *value); - -sw_error_t -hppe_in_port_meter_cfg_tbl_set( - a_uint32_t dev_id, - a_uint32_t index, - union in_port_meter_cfg_tbl_u *value); - -sw_error_t -hppe_in_port_meter_crdt_tbl_get( - a_uint32_t dev_id, - a_uint32_t index, - union in_port_meter_crdt_tbl_u *value); - -sw_error_t -hppe_in_port_meter_crdt_tbl_set( - a_uint32_t dev_id, - a_uint32_t index, - union in_port_meter_crdt_tbl_u *value); - -sw_error_t -hppe_in_port_meter_cnt_tbl_get( - a_uint32_t dev_id, - a_uint32_t index, - union in_port_meter_cnt_tbl_u *value); - -sw_error_t -hppe_in_port_meter_cnt_tbl_set( - a_uint32_t dev_id, - a_uint32_t index, - union in_port_meter_cnt_tbl_u *value); - -sw_error_t -hppe_in_acl_meter_cnt_tbl_get( - a_uint32_t dev_id, - a_uint32_t index, - union in_acl_meter_cnt_tbl_u *value); - -sw_error_t -hppe_in_acl_meter_cnt_tbl_set( - a_uint32_t dev_id, - a_uint32_t index, - union in_acl_meter_cnt_tbl_u *value); - - -sw_error_t -hppe_pc_global_cnt_tbl_get( - a_uint32_t dev_id, - a_uint32_t index, - union pc_global_cnt_tbl_u *value); - -sw_error_t -hppe_pc_global_cnt_tbl_set( - a_uint32_t dev_id, - a_uint32_t index, - union pc_global_cnt_tbl_u *value); - -sw_error_t -hppe_drop_cpu_cnt_tbl_get( - a_uint32_t dev_id, - a_uint32_t index, - union drop_cpu_cnt_tbl_u *value); - -sw_error_t -hppe_drop_cpu_cnt_tbl_set( - a_uint32_t dev_id, - a_uint32_t index, - union drop_cpu_cnt_tbl_u *value); - -sw_error_t -hppe_port_tx_drop_cnt_tbl_get( - a_uint32_t dev_id, - a_uint32_t index, - union port_tx_drop_cnt_tbl_u *value); - -sw_error_t -hppe_port_tx_drop_cnt_tbl_set( - a_uint32_t dev_id, - a_uint32_t index, - union port_tx_drop_cnt_tbl_u *value); - -sw_error_t -hppe_vp_tx_drop_cnt_tbl_get( - a_uint32_t dev_id, - a_uint32_t index, - union vp_tx_drop_cnt_tbl_u *value); - -sw_error_t -hppe_vp_tx_drop_cnt_tbl_set( - a_uint32_t dev_id, - a_uint32_t index, - union vp_tx_drop_cnt_tbl_u *value); - -sw_error_t -hppe_vlan_dev_cnt_tbl_get( - a_uint32_t dev_id, - a_uint32_t index, - union vlan_dev_cnt_tbl_u *value); - -sw_error_t -hppe_vlan_dev_cnt_tbl_set( - a_uint32_t dev_id, - a_uint32_t index, - union vlan_dev_cnt_tbl_u *value); - -sw_error_t -hppe_meter_cmpst_length_reg_cmpst_length_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_meter_cmpst_length_reg_cmpst_length_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_pc_drop_bypass_reg_drop_bypass_en_get( - a_uint32_t dev_id, - unsigned int *value); - -sw_error_t -hppe_pc_drop_bypass_reg_drop_bypass_en_set( - a_uint32_t dev_id, - unsigned int value); - -sw_error_t -hppe_pc_spare_reg_spare_reg_get( - a_uint32_t dev_id, - unsigned int *value); - -sw_error_t -hppe_pc_spare_reg_spare_reg_set( - a_uint32_t dev_id, - unsigned int value); - -sw_error_t -hppe_time_slot_reg_time_slot_get( - a_uint32_t dev_id, - unsigned int *value); - -sw_error_t -hppe_time_slot_reg_time_slot_set( - a_uint32_t dev_id, - unsigned int value); - -sw_error_t -hppe_pc_dbg_addr_reg_dbg_addr_get( - a_uint32_t dev_id, - unsigned int *value); - -sw_error_t -hppe_pc_dbg_addr_reg_dbg_addr_set( - a_uint32_t dev_id, - unsigned int value); - -sw_error_t -hppe_pc_dbg_data_reg_dbg_data_get( - a_uint32_t dev_id, - unsigned int *value); - -sw_error_t -hppe_pc_dbg_data_reg_dbg_data_set( - a_uint32_t dev_id, - unsigned int value); - -sw_error_t -hppe_in_acl_meter_cfg_tbl_meter_mode_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_in_acl_meter_cfg_tbl_meter_mode_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_in_acl_meter_cfg_tbl_color_mode_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_in_acl_meter_cfg_tbl_color_mode_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_in_acl_meter_cfg_tbl_exceed_chg_pcp_cmd_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_in_acl_meter_cfg_tbl_exceed_chg_pcp_cmd_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_in_acl_meter_cfg_tbl_exceed_pri_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_in_acl_meter_cfg_tbl_exceed_pri_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_in_acl_meter_cfg_tbl_exceed_chg_pri_cmd_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_in_acl_meter_cfg_tbl_exceed_chg_pri_cmd_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_in_acl_meter_cfg_tbl_exceed_dp_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_in_acl_meter_cfg_tbl_exceed_dp_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_in_acl_meter_cfg_tbl_violate_dp_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_in_acl_meter_cfg_tbl_violate_dp_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_in_acl_meter_cfg_tbl_exceed_dei_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_in_acl_meter_cfg_tbl_exceed_dei_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_in_acl_meter_cfg_tbl_violate_pri_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_in_acl_meter_cfg_tbl_violate_pri_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_in_acl_meter_cfg_tbl_cbs_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_in_acl_meter_cfg_tbl_cbs_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_in_acl_meter_cfg_tbl_violate_chg_dei_cmd_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_in_acl_meter_cfg_tbl_violate_chg_dei_cmd_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_in_acl_meter_cfg_tbl_violate_chg_pcp_cmd_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_in_acl_meter_cfg_tbl_violate_chg_pcp_cmd_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_in_acl_meter_cfg_tbl_cir_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_in_acl_meter_cfg_tbl_cir_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_in_acl_meter_cfg_tbl_violate_dei_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_in_acl_meter_cfg_tbl_violate_dei_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_in_acl_meter_cfg_tbl_violate_chg_pri_cmd_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_in_acl_meter_cfg_tbl_violate_chg_pri_cmd_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_in_acl_meter_cfg_tbl_meter_unit_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_in_acl_meter_cfg_tbl_meter_unit_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_in_acl_meter_cfg_tbl_meter_en_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_in_acl_meter_cfg_tbl_meter_en_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_in_acl_meter_cfg_tbl_violate_cmd_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_in_acl_meter_cfg_tbl_violate_cmd_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_in_acl_meter_cfg_tbl_violate_chg_dp_cmd_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_in_acl_meter_cfg_tbl_violate_chg_dp_cmd_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_in_acl_meter_cfg_tbl_eir_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_in_acl_meter_cfg_tbl_eir_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_in_acl_meter_cfg_tbl_exceed_chg_dp_cmd_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_in_acl_meter_cfg_tbl_exceed_chg_dp_cmd_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_in_acl_meter_cfg_tbl_exceed_chg_dei_cmd_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_in_acl_meter_cfg_tbl_exceed_chg_dei_cmd_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_in_acl_meter_cfg_tbl_exceed_pcp_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_in_acl_meter_cfg_tbl_exceed_pcp_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_in_acl_meter_cfg_tbl_violate_pcp_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_in_acl_meter_cfg_tbl_violate_pcp_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_in_acl_meter_cfg_tbl_token_unit_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_in_acl_meter_cfg_tbl_token_unit_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_in_acl_meter_cfg_tbl_coupling_flag_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_in_acl_meter_cfg_tbl_coupling_flag_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_in_acl_meter_cfg_tbl_ebs_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_in_acl_meter_cfg_tbl_ebs_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_in_acl_meter_crdt_tbl_c_crdt_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_in_acl_meter_crdt_tbl_c_crdt_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_in_acl_meter_crdt_tbl_e_crdt_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_in_acl_meter_crdt_tbl_e_crdt_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_in_port_meter_cfg_tbl_meter_mode_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_in_port_meter_cfg_tbl_meter_mode_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_in_port_meter_cfg_tbl_color_mode_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_in_port_meter_cfg_tbl_color_mode_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_in_port_meter_cfg_tbl_exceed_chg_pcp_cmd_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_in_port_meter_cfg_tbl_exceed_chg_pcp_cmd_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_in_port_meter_cfg_tbl_exceed_pri_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_in_port_meter_cfg_tbl_exceed_pri_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_in_port_meter_cfg_tbl_exceed_chg_pri_cmd_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_in_port_meter_cfg_tbl_exceed_chg_pri_cmd_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_in_port_meter_cfg_tbl_exceed_dp_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_in_port_meter_cfg_tbl_exceed_dp_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_in_port_meter_cfg_tbl_violate_dp_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_in_port_meter_cfg_tbl_violate_dp_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_in_port_meter_cfg_tbl_exceed_dei_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_in_port_meter_cfg_tbl_exceed_dei_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_in_port_meter_cfg_tbl_violate_pri_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_in_port_meter_cfg_tbl_violate_pri_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_in_port_meter_cfg_tbl_cbs_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_in_port_meter_cfg_tbl_cbs_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_in_port_meter_cfg_tbl_violate_chg_dei_cmd_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_in_port_meter_cfg_tbl_violate_chg_dei_cmd_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_in_port_meter_cfg_tbl_violate_chg_pcp_cmd_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_in_port_meter_cfg_tbl_violate_chg_pcp_cmd_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_in_port_meter_cfg_tbl_cir_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_in_port_meter_cfg_tbl_cir_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_in_port_meter_cfg_tbl_violate_dei_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_in_port_meter_cfg_tbl_violate_dei_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_in_port_meter_cfg_tbl_violate_chg_pri_cmd_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_in_port_meter_cfg_tbl_violate_chg_pri_cmd_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_in_port_meter_cfg_tbl_meter_unit_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_in_port_meter_cfg_tbl_meter_unit_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_in_port_meter_cfg_tbl_meter_en_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_in_port_meter_cfg_tbl_meter_en_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_in_port_meter_cfg_tbl_violate_cmd_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_in_port_meter_cfg_tbl_violate_cmd_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_in_port_meter_cfg_tbl_violate_chg_dp_cmd_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_in_port_meter_cfg_tbl_violate_chg_dp_cmd_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_in_port_meter_cfg_tbl_eir_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_in_port_meter_cfg_tbl_eir_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_in_port_meter_cfg_tbl_exceed_chg_dp_cmd_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_in_port_meter_cfg_tbl_exceed_chg_dp_cmd_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_in_port_meter_cfg_tbl_exceed_chg_dei_cmd_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_in_port_meter_cfg_tbl_exceed_chg_dei_cmd_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_in_port_meter_cfg_tbl_exceed_pcp_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_in_port_meter_cfg_tbl_exceed_pcp_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_in_port_meter_cfg_tbl_violate_pcp_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_in_port_meter_cfg_tbl_violate_pcp_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_in_port_meter_cfg_tbl_token_unit_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_in_port_meter_cfg_tbl_token_unit_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_in_port_meter_cfg_tbl_coupling_flag_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_in_port_meter_cfg_tbl_coupling_flag_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_in_port_meter_cfg_tbl_meter_flag_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_in_port_meter_cfg_tbl_meter_flag_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_in_port_meter_cfg_tbl_ebs_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_in_port_meter_cfg_tbl_ebs_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_in_port_meter_crdt_tbl_c_crdt_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_in_port_meter_crdt_tbl_c_crdt_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_in_port_meter_crdt_tbl_e_crdt_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_in_port_meter_crdt_tbl_e_crdt_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_in_port_meter_cnt_tbl_byte_cnt_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint64_t *value); - -sw_error_t -hppe_in_port_meter_cnt_tbl_byte_cnt_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint64_t value); - -sw_error_t -hppe_in_port_meter_cnt_tbl_pkt_cnt_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_in_port_meter_cnt_tbl_pkt_cnt_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_in_acl_meter_cnt_tbl_byte_cnt_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint64_t *value); - -sw_error_t -hppe_in_acl_meter_cnt_tbl_byte_cnt_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint64_t value); - -sw_error_t -hppe_in_acl_meter_cnt_tbl_pkt_cnt_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_in_acl_meter_cnt_tbl_pkt_cnt_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - - -sw_error_t -hppe_pc_global_cnt_tbl_byte_cnt_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint64_t *value); - -sw_error_t -hppe_pc_global_cnt_tbl_byte_cnt_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint64_t value); - -sw_error_t -hppe_pc_global_cnt_tbl_pkt_cnt_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_pc_global_cnt_tbl_pkt_cnt_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_drop_cpu_cnt_tbl_byte_cnt_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint64_t *value); - -sw_error_t -hppe_drop_cpu_cnt_tbl_byte_cnt_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint64_t value); - -sw_error_t -hppe_drop_cpu_cnt_tbl_pkt_cnt_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_drop_cpu_cnt_tbl_pkt_cnt_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_port_tx_drop_cnt_tbl_tx_drop_byte_cnt_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint64_t *value); - -sw_error_t -hppe_port_tx_drop_cnt_tbl_tx_drop_byte_cnt_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint64_t value); - -sw_error_t -hppe_port_tx_drop_cnt_tbl_tx_drop_pkt_cnt_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_port_tx_drop_cnt_tbl_tx_drop_pkt_cnt_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_vp_tx_drop_cnt_tbl_tx_drop_byte_cnt_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint64_t *value); - -sw_error_t -hppe_vp_tx_drop_cnt_tbl_tx_drop_byte_cnt_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint64_t value); - -sw_error_t -hppe_vp_tx_drop_cnt_tbl_tx_drop_pkt_cnt_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_vp_tx_drop_cnt_tbl_tx_drop_pkt_cnt_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_vlan_dev_cnt_tbl_rx_byte_cnt_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint64_t *value); - -sw_error_t -hppe_vlan_dev_cnt_tbl_rx_byte_cnt_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint64_t value); - -sw_error_t -hppe_vlan_dev_cnt_tbl_rx_pkt_cnt_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_vlan_dev_cnt_tbl_rx_pkt_cnt_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -#endif - diff --git a/feeds/ipq807x/qca-ssdk/src/include/hsl/hppe/hppe_policer_reg.h b/feeds/ipq807x/qca-ssdk/src/include/hsl/hppe/hppe_policer_reg.h deleted file mode 100755 index bcd4ba439..000000000 --- a/feeds/ipq807x/qca-ssdk/src/include/hsl/hppe/hppe_policer_reg.h +++ /dev/null @@ -1,795 +0,0 @@ -/* - * Copyright (c) 2016-2017, The Linux Foundation. All rights reserved. - * Permission to use, copy, modify, and/or distribute this software for - * any purpose with or without fee is hereby granted, provided that the - * above copyright notice and this permission notice appear in all copies. - * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES - * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR - * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES - * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN - * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT - * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. - */ - - -/** - * @defgroup - * @{ - */ -#ifndef HPPE_POLICER_REG_H -#define HPPE_POLICER_REG_H - -/*[register] METER_CMPST_LENGTH_REG*/ -#define METER_CMPST_LENGTH_REG -#define METER_CMPST_LENGTH_REG_ADDRESS 0x0 -#define METER_CMPST_LENGTH_REG_NUM 8 -#define METER_CMPST_LENGTH_REG_INC 0x4 -#define METER_CMPST_LENGTH_REG_TYPE REG_TYPE_RW -#define METER_CMPST_LENGTH_REG_DEFAULT 0x0 - /*[field] CMPST_LENGTH*/ - #define METER_CMPST_LENGTH_REG_CMPST_LENGTH - #define METER_CMPST_LENGTH_REG_CMPST_LENGTH_OFFSET 0 - #define METER_CMPST_LENGTH_REG_CMPST_LENGTH_LEN 5 - #define METER_CMPST_LENGTH_REG_CMPST_LENGTH_DEFAULT 0x0 - -struct meter_cmpst_length_reg { - a_uint32_t cmpst_length:5; - a_uint32_t _reserved0:27; -}; - -union meter_cmpst_length_reg_u { - a_uint32_t val; - struct meter_cmpst_length_reg bf; -}; - -/*[register] PC_DROP_BYPASS_REG*/ -#define PC_DROP_BYPASS_REG -#define PC_DROP_BYPASS_REG_ADDRESS 0x20 -#define PC_DROP_BYPASS_REG_NUM 1 -#define PC_DROP_BYPASS_REG_INC 0x4 -#define PC_DROP_BYPASS_REG_TYPE REG_TYPE_RW -#define PC_DROP_BYPASS_REG_DEFAULT 0x0 - /*[field] DROP_BYPASS_EN*/ - #define PC_DROP_BYPASS_REG_DROP_BYPASS_EN - #define PC_DROP_BYPASS_REG_DROP_BYPASS_EN_OFFSET 0 - #define PC_DROP_BYPASS_REG_DROP_BYPASS_EN_LEN 1 - #define PC_DROP_BYPASS_REG_DROP_BYPASS_EN_DEFAULT 0x0 - -struct pc_drop_bypass_reg { - a_uint32_t drop_bypass_en:1; - a_uint32_t _reserved0:31; -}; - -union pc_drop_bypass_reg_u { - a_uint32_t val; - struct pc_drop_bypass_reg bf; -}; - -/*[register] PC_SPARE_REG*/ -#define PC_SPARE_REG -#define PC_SPARE_REG_ADDRESS 0x30 -#define PC_SPARE_REG_NUM 1 -#define PC_SPARE_REG_INC 0x4 -#define PC_SPARE_REG_TYPE REG_TYPE_RW -#define PC_SPARE_REG_DEFAULT 0x0 - /*[field] SPARE_REG*/ - #define PC_SPARE_REG_SPARE_REG - #define PC_SPARE_REG_SPARE_REG_OFFSET 0 - #define PC_SPARE_REG_SPARE_REG_LEN 32 - #define PC_SPARE_REG_SPARE_REG_DEFAULT 0x0 - -struct pc_spare_reg { - a_uint32_t spare_reg:32; -}; - -union pc_spare_reg_u { - a_uint32_t val; - struct pc_spare_reg bf; -}; - -/*[register] TIME_SLOT_REG*/ -#define TIME_SLOT_REG -#define TIME_SLOT_REG_ADDRESS 0x40 -#define TIME_SLOT_REG_NUM 1 -#define TIME_SLOT_REG_INC 0x4 -#define TIME_SLOT_REG_TYPE REG_TYPE_RW -#define TIME_SLOT_REG_DEFAULT 0x0 - /*[field] TIME_SLOT*/ - #define TIME_SLOT_REG_TIME_SLOT - #define TIME_SLOT_REG_TIME_SLOT_OFFSET 0 - #define TIME_SLOT_REG_TIME_SLOT_LEN 10 - #define TIME_SLOT_REG_TIME_SLOT_DEFAULT 0x0 - -struct time_slot_reg { - a_uint32_t time_slot:10; - a_uint32_t _reserved0:22; -}; - -union time_slot_reg_u { - a_uint32_t val; - struct time_slot_reg bf; -}; - -/*[register] PC_DBG_ADDR_REG*/ -#define PC_DBG_ADDR_REG -#define PC_DBG_ADDR_REG_ADDRESS 0x80 -#define PC_DBG_ADDR_REG_NUM 1 -#define PC_DBG_ADDR_REG_INC 0x4 -#define PC_DBG_ADDR_REG_TYPE REG_TYPE_RW -#define PC_DBG_ADDR_REG_DEFAULT 0x0 - /*[field] DBG_ADDR*/ - #define PC_DBG_ADDR_REG_DBG_ADDR - #define PC_DBG_ADDR_REG_DBG_ADDR_OFFSET 24 - #define PC_DBG_ADDR_REG_DBG_ADDR_LEN 8 - #define PC_DBG_ADDR_REG_DBG_ADDR_DEFAULT 0x0 - -struct pc_dbg_addr_reg { - a_uint32_t dbg_addr:8; -}; - -union pc_dbg_addr_reg_u { - a_uint32_t val; - struct pc_dbg_addr_reg bf; -}; - -/*[register] PC_DBG_DATA_REG*/ -#define PC_DBG_DATA_REG -#define PC_DBG_DATA_REG_ADDRESS 0x84 -#define PC_DBG_DATA_REG_NUM 1 -#define PC_DBG_DATA_REG_INC 0x4 -#define PC_DBG_DATA_REG_TYPE REG_TYPE_RO -#define PC_DBG_DATA_REG_DEFAULT 0x0 - /*[field] DBG_DATA*/ - #define PC_DBG_DATA_REG_DBG_DATA - #define PC_DBG_DATA_REG_DBG_DATA_OFFSET 0 - #define PC_DBG_DATA_REG_DBG_DATA_LEN 32 - #define PC_DBG_DATA_REG_DBG_DATA_DEFAULT 0x0 - -struct pc_dbg_data_reg { - a_uint32_t dbg_data:32; -}; - -union pc_dbg_data_reg_u { - a_uint32_t val; - struct pc_dbg_data_reg bf; -}; - -/*[table] IN_ACL_METER_CFG_TBL*/ -#define IN_ACL_METER_CFG_TBL -#define IN_ACL_METER_CFG_TBL_ADDRESS 0x4000 -#define IN_ACL_METER_CFG_TBL_NUM 512 -#define IN_ACL_METER_CFG_TBL_INC 0x10 -#define IN_ACL_METER_CFG_TBL_TYPE REG_TYPE_RW -#define IN_ACL_METER_CFG_TBL_DEFAULT 0x0 - /*[field] METER_EN*/ - #define IN_ACL_METER_CFG_TBL_METER_EN - #define IN_ACL_METER_CFG_TBL_METER_EN_OFFSET 0 - #define IN_ACL_METER_CFG_TBL_METER_EN_LEN 1 - #define IN_ACL_METER_CFG_TBL_METER_EN_DEFAULT 0x0 - /*[field] COLOR_MODE*/ - #define IN_ACL_METER_CFG_TBL_COLOR_MODE - #define IN_ACL_METER_CFG_TBL_COLOR_MODE_OFFSET 1 - #define IN_ACL_METER_CFG_TBL_COLOR_MODE_LEN 1 - #define IN_ACL_METER_CFG_TBL_COLOR_MODE_DEFAULT 0x0 - /*[field] COUPLING_FLAG*/ - #define IN_ACL_METER_CFG_TBL_COUPLING_FLAG - #define IN_ACL_METER_CFG_TBL_COUPLING_FLAG_OFFSET 2 - #define IN_ACL_METER_CFG_TBL_COUPLING_FLAG_LEN 1 - #define IN_ACL_METER_CFG_TBL_COUPLING_FLAG_DEFAULT 0x0 - /*[field] METER_MODE*/ - #define IN_ACL_METER_CFG_TBL_METER_MODE - #define IN_ACL_METER_CFG_TBL_METER_MODE_OFFSET 3 - #define IN_ACL_METER_CFG_TBL_METER_MODE_LEN 1 - #define IN_ACL_METER_CFG_TBL_METER_MODE_DEFAULT 0x0 - /*[field] TOKEN_UNIT*/ - #define IN_ACL_METER_CFG_TBL_TOKEN_UNIT - #define IN_ACL_METER_CFG_TBL_TOKEN_UNIT_OFFSET 4 - #define IN_ACL_METER_CFG_TBL_TOKEN_UNIT_LEN 3 - #define IN_ACL_METER_CFG_TBL_TOKEN_UNIT_DEFAULT 0x0 - /*[field] METER_UNIT*/ - #define IN_ACL_METER_CFG_TBL_METER_UNIT - #define IN_ACL_METER_CFG_TBL_METER_UNIT_OFFSET 7 - #define IN_ACL_METER_CFG_TBL_METER_UNIT_LEN 1 - #define IN_ACL_METER_CFG_TBL_METER_UNIT_DEFAULT 0x0 - /*[field] CBS*/ - #define IN_ACL_METER_CFG_TBL_CBS - #define IN_ACL_METER_CFG_TBL_CBS_OFFSET 8 - #define IN_ACL_METER_CFG_TBL_CBS_LEN 16 - #define IN_ACL_METER_CFG_TBL_CBS_DEFAULT 0x0 - /*[field] CIR*/ - #define IN_ACL_METER_CFG_TBL_CIR - #define IN_ACL_METER_CFG_TBL_CIR_OFFSET 24 - #define IN_ACL_METER_CFG_TBL_CIR_LEN 18 - #define IN_ACL_METER_CFG_TBL_CIR_DEFAULT 0x0 - /*[field] EBS*/ - #define IN_ACL_METER_CFG_TBL_EBS - #define IN_ACL_METER_CFG_TBL_EBS_OFFSET 42 - #define IN_ACL_METER_CFG_TBL_EBS_LEN 16 - #define IN_ACL_METER_CFG_TBL_EBS_DEFAULT 0x0 - /*[field] EIR*/ - #define IN_ACL_METER_CFG_TBL_EIR - #define IN_ACL_METER_CFG_TBL_EIR_OFFSET 58 - #define IN_ACL_METER_CFG_TBL_EIR_LEN 18 - #define IN_ACL_METER_CFG_TBL_EIR_DEFAULT 0x0 - /*[field] EXCEED_CHG_PRI_CMD*/ - #define IN_ACL_METER_CFG_TBL_EXCEED_CHG_PRI_CMD - #define IN_ACL_METER_CFG_TBL_EXCEED_CHG_PRI_CMD_OFFSET 76 - #define IN_ACL_METER_CFG_TBL_EXCEED_CHG_PRI_CMD_LEN 1 - #define IN_ACL_METER_CFG_TBL_EXCEED_CHG_PRI_CMD_DEFAULT 0x0 - /*[field] EXCEED_CHG_DP_CMD*/ - #define IN_ACL_METER_CFG_TBL_EXCEED_CHG_DP_CMD - #define IN_ACL_METER_CFG_TBL_EXCEED_CHG_DP_CMD_OFFSET 77 - #define IN_ACL_METER_CFG_TBL_EXCEED_CHG_DP_CMD_LEN 1 - #define IN_ACL_METER_CFG_TBL_EXCEED_CHG_DP_CMD_DEFAULT 0x0 - /*[field] EXCEED_CHG_PCP_CMD*/ - #define IN_ACL_METER_CFG_TBL_EXCEED_CHG_PCP_CMD - #define IN_ACL_METER_CFG_TBL_EXCEED_CHG_PCP_CMD_OFFSET 78 - #define IN_ACL_METER_CFG_TBL_EXCEED_CHG_PCP_CMD_LEN 1 - #define IN_ACL_METER_CFG_TBL_EXCEED_CHG_PCP_CMD_DEFAULT 0x0 - /*[field] EXCEED_CHG_DEI_CMD*/ - #define IN_ACL_METER_CFG_TBL_EXCEED_CHG_DEI_CMD - #define IN_ACL_METER_CFG_TBL_EXCEED_CHG_DEI_CMD_OFFSET 79 - #define IN_ACL_METER_CFG_TBL_EXCEED_CHG_DEI_CMD_LEN 1 - #define IN_ACL_METER_CFG_TBL_EXCEED_CHG_DEI_CMD_DEFAULT 0x0 - /*[field] EXCEED_PRI*/ - #define IN_ACL_METER_CFG_TBL_EXCEED_PRI - #define IN_ACL_METER_CFG_TBL_EXCEED_PRI_OFFSET 80 - #define IN_ACL_METER_CFG_TBL_EXCEED_PRI_LEN 4 - #define IN_ACL_METER_CFG_TBL_EXCEED_PRI_DEFAULT 0x0 - /*[field] EXCEED_DP*/ - #define IN_ACL_METER_CFG_TBL_EXCEED_DP - #define IN_ACL_METER_CFG_TBL_EXCEED_DP_OFFSET 84 - #define IN_ACL_METER_CFG_TBL_EXCEED_DP_LEN 2 - #define IN_ACL_METER_CFG_TBL_EXCEED_DP_DEFAULT 0x0 - /*[field] EXCEED_PCP*/ - #define IN_ACL_METER_CFG_TBL_EXCEED_PCP - #define IN_ACL_METER_CFG_TBL_EXCEED_PCP_OFFSET 86 - #define IN_ACL_METER_CFG_TBL_EXCEED_PCP_LEN 3 - #define IN_ACL_METER_CFG_TBL_EXCEED_PCP_DEFAULT 0x0 - /*[field] EXCEED_DEI*/ - #define IN_ACL_METER_CFG_TBL_EXCEED_DEI - #define IN_ACL_METER_CFG_TBL_EXCEED_DEI_OFFSET 89 - #define IN_ACL_METER_CFG_TBL_EXCEED_DEI_LEN 1 - #define IN_ACL_METER_CFG_TBL_EXCEED_DEI_DEFAULT 0x0 - /*[field] VIOLATE_CMD*/ - #define IN_ACL_METER_CFG_TBL_VIOLATE_CMD - #define IN_ACL_METER_CFG_TBL_VIOLATE_CMD_OFFSET 90 - #define IN_ACL_METER_CFG_TBL_VIOLATE_CMD_LEN 1 - #define IN_ACL_METER_CFG_TBL_VIOLATE_CMD_DEFAULT 0x0 - /*[field] VIOLATE_CHG_PRI_CMD*/ - #define IN_ACL_METER_CFG_TBL_VIOLATE_CHG_PRI_CMD - #define IN_ACL_METER_CFG_TBL_VIOLATE_CHG_PRI_CMD_OFFSET 91 - #define IN_ACL_METER_CFG_TBL_VIOLATE_CHG_PRI_CMD_LEN 1 - #define IN_ACL_METER_CFG_TBL_VIOLATE_CHG_PRI_CMD_DEFAULT 0x0 - /*[field] VIOLATE_CHG_DP_CMD*/ - #define IN_ACL_METER_CFG_TBL_VIOLATE_CHG_DP_CMD - #define IN_ACL_METER_CFG_TBL_VIOLATE_CHG_DP_CMD_OFFSET 92 - #define IN_ACL_METER_CFG_TBL_VIOLATE_CHG_DP_CMD_LEN 1 - #define IN_ACL_METER_CFG_TBL_VIOLATE_CHG_DP_CMD_DEFAULT 0x0 - /*[field] VIOLATE_CHG_PCP_CMD*/ - #define IN_ACL_METER_CFG_TBL_VIOLATE_CHG_PCP_CMD - #define IN_ACL_METER_CFG_TBL_VIOLATE_CHG_PCP_CMD_OFFSET 93 - #define IN_ACL_METER_CFG_TBL_VIOLATE_CHG_PCP_CMD_LEN 1 - #define IN_ACL_METER_CFG_TBL_VIOLATE_CHG_PCP_CMD_DEFAULT 0x0 - /*[field] VIOLATE_CHG_DEI_CMD*/ - #define IN_ACL_METER_CFG_TBL_VIOLATE_CHG_DEI_CMD - #define IN_ACL_METER_CFG_TBL_VIOLATE_CHG_DEI_CMD_OFFSET 94 - #define IN_ACL_METER_CFG_TBL_VIOLATE_CHG_DEI_CMD_LEN 1 - #define IN_ACL_METER_CFG_TBL_VIOLATE_CHG_DEI_CMD_DEFAULT 0x0 - /*[field] VIOLATE_PRI*/ - #define IN_ACL_METER_CFG_TBL_VIOLATE_PRI - #define IN_ACL_METER_CFG_TBL_VIOLATE_PRI_OFFSET 95 - #define IN_ACL_METER_CFG_TBL_VIOLATE_PRI_LEN 4 - #define IN_ACL_METER_CFG_TBL_VIOLATE_PRI_DEFAULT 0x0 - /*[field] VIOLATE_DP*/ - #define IN_ACL_METER_CFG_TBL_VIOLATE_DP - #define IN_ACL_METER_CFG_TBL_VIOLATE_DP_OFFSET 99 - #define IN_ACL_METER_CFG_TBL_VIOLATE_DP_LEN 2 - #define IN_ACL_METER_CFG_TBL_VIOLATE_DP_DEFAULT 0x0 - /*[field] VIOLATE_PCP*/ - #define IN_ACL_METER_CFG_TBL_VIOLATE_PCP - #define IN_ACL_METER_CFG_TBL_VIOLATE_PCP_OFFSET 101 - #define IN_ACL_METER_CFG_TBL_VIOLATE_PCP_LEN 3 - #define IN_ACL_METER_CFG_TBL_VIOLATE_PCP_DEFAULT 0x0 - /*[field] VIOLATE_DEI*/ - #define IN_ACL_METER_CFG_TBL_VIOLATE_DEI - #define IN_ACL_METER_CFG_TBL_VIOLATE_DEI_OFFSET 104 - #define IN_ACL_METER_CFG_TBL_VIOLATE_DEI_LEN 1 - #define IN_ACL_METER_CFG_TBL_VIOLATE_DEI_DEFAULT 0x0 - -struct in_acl_meter_cfg_tbl { - a_uint32_t meter_en:1; - a_uint32_t color_mode:1; - a_uint32_t coupling_flag:1; - a_uint32_t meter_mode:1; - a_uint32_t token_unit:3; - a_uint32_t meter_unit:1; - a_uint32_t cbs:16; - a_uint32_t cir_0:8; - a_uint32_t cir_1:10; - a_uint32_t ebs:16; - a_uint32_t eir_0:6; - a_uint32_t eir_1:12; - a_uint32_t exceed_chg_pri_cmd:1; - a_uint32_t exceed_chg_dp_cmd:1; - a_uint32_t exceed_chg_pcp_cmd:1; - a_uint32_t exceed_chg_dei_cmd:1; - a_uint32_t exceed_pri:4; - a_uint32_t exceed_dp:2; - a_uint32_t exceed_pcp:3; - a_uint32_t exceed_dei:1; - a_uint32_t violate_cmd:1; - a_uint32_t violate_chg_pri_cmd:1; - a_uint32_t violate_chg_dp_cmd:1; - a_uint32_t violate_chg_pcp_cmd:1; - a_uint32_t violate_chg_dei_cmd:1; - a_uint32_t violate_pri_0:1; - a_uint32_t violate_pri_1:3; - a_uint32_t violate_dp:2; - a_uint32_t violate_pcp:3; - a_uint32_t violate_dei:1; - a_uint32_t _reserved0:23; -}; - -union in_acl_meter_cfg_tbl_u { - a_uint32_t val[4]; - struct in_acl_meter_cfg_tbl bf; -}; - -/*[table] IN_ACL_METER_CRDT_TBL*/ -#define IN_ACL_METER_CRDT_TBL -#define IN_ACL_METER_CRDT_TBL_ADDRESS 0x8000 -#define IN_ACL_METER_CRDT_TBL_NUM 512 -#define IN_ACL_METER_CRDT_TBL_INC 0x10 -#define IN_ACL_METER_CRDT_TBL_TYPE REG_TYPE_RW -#define IN_ACL_METER_CRDT_TBL_DEFAULT 0x0 - /*[field] C_CRDT*/ - #define IN_ACL_METER_CRDT_TBL_C_CRDT - #define IN_ACL_METER_CRDT_TBL_C_CRDT_OFFSET 0 - #define IN_ACL_METER_CRDT_TBL_C_CRDT_LEN 32 - #define IN_ACL_METER_CRDT_TBL_C_CRDT_DEFAULT 0x0 - /*[field] E_CRDT*/ - #define IN_ACL_METER_CRDT_TBL_E_CRDT - #define IN_ACL_METER_CRDT_TBL_E_CRDT_OFFSET 32 - #define IN_ACL_METER_CRDT_TBL_E_CRDT_LEN 32 - #define IN_ACL_METER_CRDT_TBL_E_CRDT_DEFAULT 0x0 - -struct in_acl_meter_crdt_tbl { - a_uint32_t c_crdt:32; - a_uint32_t e_crdt:32; -}; - -union in_acl_meter_crdt_tbl_u { - a_uint32_t val[2]; - struct in_acl_meter_crdt_tbl bf; -}; - -/*[table] IN_PORT_METER_CFG_TBL*/ -#define IN_PORT_METER_CFG_TBL -#define IN_PORT_METER_CFG_TBL_ADDRESS 0xc000 -#define IN_PORT_METER_CFG_TBL_NUM 8 -#define IN_PORT_METER_CFG_TBL_INC 0x10 -#define IN_PORT_METER_CFG_TBL_TYPE REG_TYPE_RW -#define IN_PORT_METER_CFG_TBL_DEFAULT 0x0 - /*[field] METER_EN*/ - #define IN_PORT_METER_CFG_TBL_METER_EN - #define IN_PORT_METER_CFG_TBL_METER_EN_OFFSET 0 - #define IN_PORT_METER_CFG_TBL_METER_EN_LEN 1 - #define IN_PORT_METER_CFG_TBL_METER_EN_DEFAULT 0x0 - /*[field] COLOR_MODE*/ - #define IN_PORT_METER_CFG_TBL_COLOR_MODE - #define IN_PORT_METER_CFG_TBL_COLOR_MODE_OFFSET 1 - #define IN_PORT_METER_CFG_TBL_COLOR_MODE_LEN 1 - #define IN_PORT_METER_CFG_TBL_COLOR_MODE_DEFAULT 0x0 - /*[field] METER_FLAG*/ - #define IN_PORT_METER_CFG_TBL_METER_FLAG - #define IN_PORT_METER_CFG_TBL_METER_FLAG_OFFSET 2 - #define IN_PORT_METER_CFG_TBL_METER_FLAG_LEN 5 - #define IN_PORT_METER_CFG_TBL_METER_FLAG_DEFAULT 0x0 - /*[field] COUPLING_FLAG*/ - #define IN_PORT_METER_CFG_TBL_COUPLING_FLAG - #define IN_PORT_METER_CFG_TBL_COUPLING_FLAG_OFFSET 7 - #define IN_PORT_METER_CFG_TBL_COUPLING_FLAG_LEN 1 - #define IN_PORT_METER_CFG_TBL_COUPLING_FLAG_DEFAULT 0x0 - /*[field] METER_MODE*/ - #define IN_PORT_METER_CFG_TBL_METER_MODE - #define IN_PORT_METER_CFG_TBL_METER_MODE_OFFSET 8 - #define IN_PORT_METER_CFG_TBL_METER_MODE_LEN 1 - #define IN_PORT_METER_CFG_TBL_METER_MODE_DEFAULT 0x0 - /*[field] TOKEN_UNIT*/ - #define IN_PORT_METER_CFG_TBL_TOKEN_UNIT - #define IN_PORT_METER_CFG_TBL_TOKEN_UNIT_OFFSET 9 - #define IN_PORT_METER_CFG_TBL_TOKEN_UNIT_LEN 3 - #define IN_PORT_METER_CFG_TBL_TOKEN_UNIT_DEFAULT 0x0 - /*[field] METER_UNIT*/ - #define IN_PORT_METER_CFG_TBL_METER_UNIT - #define IN_PORT_METER_CFG_TBL_METER_UNIT_OFFSET 12 - #define IN_PORT_METER_CFG_TBL_METER_UNIT_LEN 1 - #define IN_PORT_METER_CFG_TBL_METER_UNIT_DEFAULT 0x0 - /*[field] CBS*/ - #define IN_PORT_METER_CFG_TBL_CBS - #define IN_PORT_METER_CFG_TBL_CBS_OFFSET 13 - #define IN_PORT_METER_CFG_TBL_CBS_LEN 16 - #define IN_PORT_METER_CFG_TBL_CBS_DEFAULT 0x0 - /*[field] CIR*/ - #define IN_PORT_METER_CFG_TBL_CIR - #define IN_PORT_METER_CFG_TBL_CIR_OFFSET 29 - #define IN_PORT_METER_CFG_TBL_CIR_LEN 18 - #define IN_PORT_METER_CFG_TBL_CIR_DEFAULT 0x0 - /*[field] EBS*/ - #define IN_PORT_METER_CFG_TBL_EBS - #define IN_PORT_METER_CFG_TBL_EBS_OFFSET 47 - #define IN_PORT_METER_CFG_TBL_EBS_LEN 16 - #define IN_PORT_METER_CFG_TBL_EBS_DEFAULT 0x0 - /*[field] EIR*/ - #define IN_PORT_METER_CFG_TBL_EIR - #define IN_PORT_METER_CFG_TBL_EIR_OFFSET 63 - #define IN_PORT_METER_CFG_TBL_EIR_LEN 18 - #define IN_PORT_METER_CFG_TBL_EIR_DEFAULT 0x0 - /*[field] EXCEED_CHG_PRI_CMD*/ - #define IN_PORT_METER_CFG_TBL_EXCEED_CHG_PRI_CMD - #define IN_PORT_METER_CFG_TBL_EXCEED_CHG_PRI_CMD_OFFSET 81 - #define IN_PORT_METER_CFG_TBL_EXCEED_CHG_PRI_CMD_LEN 1 - #define IN_PORT_METER_CFG_TBL_EXCEED_CHG_PRI_CMD_DEFAULT 0x0 - /*[field] EXCEED_CHG_DP_CMD*/ - #define IN_PORT_METER_CFG_TBL_EXCEED_CHG_DP_CMD - #define IN_PORT_METER_CFG_TBL_EXCEED_CHG_DP_CMD_OFFSET 82 - #define IN_PORT_METER_CFG_TBL_EXCEED_CHG_DP_CMD_LEN 1 - #define IN_PORT_METER_CFG_TBL_EXCEED_CHG_DP_CMD_DEFAULT 0x0 - /*[field] EXCEED_CHG_PCP_CMD*/ - #define IN_PORT_METER_CFG_TBL_EXCEED_CHG_PCP_CMD - #define IN_PORT_METER_CFG_TBL_EXCEED_CHG_PCP_CMD_OFFSET 83 - #define IN_PORT_METER_CFG_TBL_EXCEED_CHG_PCP_CMD_LEN 1 - #define IN_PORT_METER_CFG_TBL_EXCEED_CHG_PCP_CMD_DEFAULT 0x0 - /*[field] EXCEED_CHG_DEI_CMD*/ - #define IN_PORT_METER_CFG_TBL_EXCEED_CHG_DEI_CMD - #define IN_PORT_METER_CFG_TBL_EXCEED_CHG_DEI_CMD_OFFSET 84 - #define IN_PORT_METER_CFG_TBL_EXCEED_CHG_DEI_CMD_LEN 1 - #define IN_PORT_METER_CFG_TBL_EXCEED_CHG_DEI_CMD_DEFAULT 0x0 - /*[field] EXCEED_PRI*/ - #define IN_PORT_METER_CFG_TBL_EXCEED_PRI - #define IN_PORT_METER_CFG_TBL_EXCEED_PRI_OFFSET 85 - #define IN_PORT_METER_CFG_TBL_EXCEED_PRI_LEN 4 - #define IN_PORT_METER_CFG_TBL_EXCEED_PRI_DEFAULT 0x0 - /*[field] EXCEED_DP*/ - #define IN_PORT_METER_CFG_TBL_EXCEED_DP - #define IN_PORT_METER_CFG_TBL_EXCEED_DP_OFFSET 89 - #define IN_PORT_METER_CFG_TBL_EXCEED_DP_LEN 2 - #define IN_PORT_METER_CFG_TBL_EXCEED_DP_DEFAULT 0x0 - /*[field] EXCEED_PCP*/ - #define IN_PORT_METER_CFG_TBL_EXCEED_PCP - #define IN_PORT_METER_CFG_TBL_EXCEED_PCP_OFFSET 91 - #define IN_PORT_METER_CFG_TBL_EXCEED_PCP_LEN 3 - #define IN_PORT_METER_CFG_TBL_EXCEED_PCP_DEFAULT 0x0 - /*[field] EXCEED_DEI*/ - #define IN_PORT_METER_CFG_TBL_EXCEED_DEI - #define IN_PORT_METER_CFG_TBL_EXCEED_DEI_OFFSET 94 - #define IN_PORT_METER_CFG_TBL_EXCEED_DEI_LEN 1 - #define IN_PORT_METER_CFG_TBL_EXCEED_DEI_DEFAULT 0x0 - /*[field] VIOLATE_CMD*/ - #define IN_PORT_METER_CFG_TBL_VIOLATE_CMD - #define IN_PORT_METER_CFG_TBL_VIOLATE_CMD_OFFSET 95 - #define IN_PORT_METER_CFG_TBL_VIOLATE_CMD_LEN 1 - #define IN_PORT_METER_CFG_TBL_VIOLATE_CMD_DEFAULT 0x0 - /*[field] VIOLATE_CHG_PRI_CMD*/ - #define IN_PORT_METER_CFG_TBL_VIOLATE_CHG_PRI_CMD - #define IN_PORT_METER_CFG_TBL_VIOLATE_CHG_PRI_CMD_OFFSET 96 - #define IN_PORT_METER_CFG_TBL_VIOLATE_CHG_PRI_CMD_LEN 1 - #define IN_PORT_METER_CFG_TBL_VIOLATE_CHG_PRI_CMD_DEFAULT 0x0 - /*[field] VIOLATE_CHG_DP_CMD*/ - #define IN_PORT_METER_CFG_TBL_VIOLATE_CHG_DP_CMD - #define IN_PORT_METER_CFG_TBL_VIOLATE_CHG_DP_CMD_OFFSET 97 - #define IN_PORT_METER_CFG_TBL_VIOLATE_CHG_DP_CMD_LEN 1 - #define IN_PORT_METER_CFG_TBL_VIOLATE_CHG_DP_CMD_DEFAULT 0x0 - /*[field] VIOLATE_CHG_PCP_CMD*/ - #define IN_PORT_METER_CFG_TBL_VIOLATE_CHG_PCP_CMD - #define IN_PORT_METER_CFG_TBL_VIOLATE_CHG_PCP_CMD_OFFSET 98 - #define IN_PORT_METER_CFG_TBL_VIOLATE_CHG_PCP_CMD_LEN 1 - #define IN_PORT_METER_CFG_TBL_VIOLATE_CHG_PCP_CMD_DEFAULT 0x0 - /*[field] VIOLATE_CHG_DEI_CMD*/ - #define IN_PORT_METER_CFG_TBL_VIOLATE_CHG_DEI_CMD - #define IN_PORT_METER_CFG_TBL_VIOLATE_CHG_DEI_CMD_OFFSET 99 - #define IN_PORT_METER_CFG_TBL_VIOLATE_CHG_DEI_CMD_LEN 1 - #define IN_PORT_METER_CFG_TBL_VIOLATE_CHG_DEI_CMD_DEFAULT 0x0 - /*[field] VIOLATE_PRI*/ - #define IN_PORT_METER_CFG_TBL_VIOLATE_PRI - #define IN_PORT_METER_CFG_TBL_VIOLATE_PRI_OFFSET 100 - #define IN_PORT_METER_CFG_TBL_VIOLATE_PRI_LEN 4 - #define IN_PORT_METER_CFG_TBL_VIOLATE_PRI_DEFAULT 0x0 - /*[field] VIOLATE_DP*/ - #define IN_PORT_METER_CFG_TBL_VIOLATE_DP - #define IN_PORT_METER_CFG_TBL_VIOLATE_DP_OFFSET 104 - #define IN_PORT_METER_CFG_TBL_VIOLATE_DP_LEN 2 - #define IN_PORT_METER_CFG_TBL_VIOLATE_DP_DEFAULT 0x0 - /*[field] VIOLATE_PCP*/ - #define IN_PORT_METER_CFG_TBL_VIOLATE_PCP - #define IN_PORT_METER_CFG_TBL_VIOLATE_PCP_OFFSET 106 - #define IN_PORT_METER_CFG_TBL_VIOLATE_PCP_LEN 3 - #define IN_PORT_METER_CFG_TBL_VIOLATE_PCP_DEFAULT 0x0 - /*[field] VIOLATE_DEI*/ - #define IN_PORT_METER_CFG_TBL_VIOLATE_DEI - #define IN_PORT_METER_CFG_TBL_VIOLATE_DEI_OFFSET 109 - #define IN_PORT_METER_CFG_TBL_VIOLATE_DEI_LEN 1 - #define IN_PORT_METER_CFG_TBL_VIOLATE_DEI_DEFAULT 0x0 - -struct in_port_meter_cfg_tbl { - a_uint32_t meter_en:1; - a_uint32_t color_mode:1; - a_uint32_t meter_flag:5; - a_uint32_t coupling_flag:1; - a_uint32_t meter_mode:1; - a_uint32_t token_unit:3; - a_uint32_t meter_unit:1; - a_uint32_t cbs:16; - a_uint32_t cir_0:3; - a_uint32_t cir_1:15; - a_uint32_t ebs:16; - a_uint32_t eir_0:1; - a_uint32_t eir_1:17; - a_uint32_t exceed_chg_pri_cmd:1; - a_uint32_t exceed_chg_dp_cmd:1; - a_uint32_t exceed_chg_pcp_cmd:1; - a_uint32_t exceed_chg_dei_cmd:1; - a_uint32_t exceed_pri:4; - a_uint32_t exceed_dp:2; - a_uint32_t exceed_pcp:3; - a_uint32_t exceed_dei:1; - a_uint32_t violate_cmd:1; - a_uint32_t violate_chg_pri_cmd:1; - a_uint32_t violate_chg_dp_cmd:1; - a_uint32_t violate_chg_pcp_cmd:1; - a_uint32_t violate_chg_dei_cmd:1; - a_uint32_t violate_pri:4; - a_uint32_t violate_dp:2; - a_uint32_t violate_pcp:3; - a_uint32_t violate_dei:1; - a_uint32_t _reserved0:18; -}; - -union in_port_meter_cfg_tbl_u { - a_uint32_t val[4]; - struct in_port_meter_cfg_tbl bf; -}; - -/*[table] IN_PORT_METER_CRDT_TBL*/ -#define IN_PORT_METER_CRDT_TBL -#define IN_PORT_METER_CRDT_TBL_ADDRESS 0xd000 -#define IN_PORT_METER_CRDT_TBL_NUM 8 -#define IN_PORT_METER_CRDT_TBL_INC 0x10 -#define IN_PORT_METER_CRDT_TBL_TYPE REG_TYPE_RW -#define IN_PORT_METER_CRDT_TBL_DEFAULT 0x0 - /*[field] C_CRDT*/ - #define IN_PORT_METER_CRDT_TBL_C_CRDT - #define IN_PORT_METER_CRDT_TBL_C_CRDT_OFFSET 0 - #define IN_PORT_METER_CRDT_TBL_C_CRDT_LEN 32 - #define IN_PORT_METER_CRDT_TBL_C_CRDT_DEFAULT 0x0 - /*[field] E_CRDT*/ - #define IN_PORT_METER_CRDT_TBL_E_CRDT - #define IN_PORT_METER_CRDT_TBL_E_CRDT_OFFSET 32 - #define IN_PORT_METER_CRDT_TBL_E_CRDT_LEN 32 - #define IN_PORT_METER_CRDT_TBL_E_CRDT_DEFAULT 0x0 - -struct in_port_meter_crdt_tbl { - a_uint32_t c_crdt:32; - a_uint32_t e_crdt:32; -}; - -union in_port_meter_crdt_tbl_u { - a_uint32_t val[2]; - struct in_port_meter_crdt_tbl bf; -}; - -/*[table] IN_PORT_METER_CNT_TBL*/ -#define IN_PORT_METER_CNT_TBL -#define IN_PORT_METER_CNT_TBL_ADDRESS 0xe000 -#define IN_PORT_METER_CNT_TBL_NUM 24 -#define IN_PORT_METER_CNT_TBL_INC 0x10 -#define IN_PORT_METER_CNT_TBL_TYPE REG_TYPE_RW -#define IN_PORT_METER_CNT_TBL_DEFAULT 0x0 - /*[field] PKT_CNT*/ - #define IN_PORT_METER_CNT_TBL_PKT_CNT - #define IN_PORT_METER_CNT_TBL_PKT_CNT_OFFSET 0 - #define IN_PORT_METER_CNT_TBL_PKT_CNT_LEN 32 - #define IN_PORT_METER_CNT_TBL_PKT_CNT_DEFAULT 0x0 - /*[field] BYTE_CNT*/ - #define IN_PORT_METER_CNT_TBL_BYTE_CNT - #define IN_PORT_METER_CNT_TBL_BYTE_CNT_OFFSET 32 - #define IN_PORT_METER_CNT_TBL_BYTE_CNT_LEN 40 - #define IN_PORT_METER_CNT_TBL_BYTE_CNT_DEFAULT 0x0 - -struct in_port_meter_cnt_tbl { - a_uint32_t pkt_cnt:32; - a_uint32_t byte_cnt_0:32; - a_uint32_t byte_cnt_1:8; - a_uint32_t _reserved0:24; -}; - -union in_port_meter_cnt_tbl_u { - a_uint32_t val[3]; - struct in_port_meter_cnt_tbl bf; -}; - -/*[table] IN_ACL_METER_CNT_TBL*/ -#define IN_ACL_METER_CNT_TBL -#define IN_ACL_METER_CNT_TBL_ADDRESS 0x10000 -#define IN_ACL_METER_CNT_TBL_NUM 1536 -#define IN_ACL_METER_CNT_TBL_INC 0x10 -#define IN_ACL_METER_CNT_TBL_TYPE REG_TYPE_RW -#define IN_ACL_METER_CNT_TBL_DEFAULT 0x0 - /*[field] PKT_CNT*/ - #define IN_ACL_METER_CNT_TBL_PKT_CNT - #define IN_ACL_METER_CNT_TBL_PKT_CNT_OFFSET 0 - #define IN_ACL_METER_CNT_TBL_PKT_CNT_LEN 32 - #define IN_ACL_METER_CNT_TBL_PKT_CNT_DEFAULT 0x0 - /*[field] BYTE_CNT*/ - #define IN_ACL_METER_CNT_TBL_BYTE_CNT - #define IN_ACL_METER_CNT_TBL_BYTE_CNT_OFFSET 32 - #define IN_ACL_METER_CNT_TBL_BYTE_CNT_LEN 40 - #define IN_ACL_METER_CNT_TBL_BYTE_CNT_DEFAULT 0x0 - -struct in_acl_meter_cnt_tbl { - a_uint32_t pkt_cnt:32; - a_uint32_t byte_cnt_0:32; - a_uint32_t byte_cnt_1:8; - a_uint32_t _reserved0:24; -}; - -union in_acl_meter_cnt_tbl_u { - a_uint32_t val[3]; - struct in_acl_meter_cnt_tbl bf; -}; - -/*[table] PC_GLOBAL_CNT_TBL*/ -#define PC_GLOBAL_CNT_TBL -#define PC_GLOBAL_CNT_TBL_ADDRESS 0x58000 -#define PC_GLOBAL_CNT_TBL_NUM 3 -#define PC_GLOBAL_CNT_TBL_INC 0x10 -#define PC_GLOBAL_CNT_TBL_TYPE REG_TYPE_RW -#define PC_GLOBAL_CNT_TBL_DEFAULT 0x0 - /*[field] PKT_CNT*/ - #define PC_GLOBAL_CNT_TBL_PKT_CNT - #define PC_GLOBAL_CNT_TBL_PKT_CNT_OFFSET 0 - #define PC_GLOBAL_CNT_TBL_PKT_CNT_LEN 32 - #define PC_GLOBAL_CNT_TBL_PKT_CNT_DEFAULT 0x0 - /*[field] BYTE_CNT*/ - #define PC_GLOBAL_CNT_TBL_BYTE_CNT - #define PC_GLOBAL_CNT_TBL_BYTE_CNT_OFFSET 32 - #define PC_GLOBAL_CNT_TBL_BYTE_CNT_LEN 40 - #define PC_GLOBAL_CNT_TBL_BYTE_CNT_DEFAULT 0x0 - -struct pc_global_cnt_tbl { - a_uint32_t pkt_cnt:32; - a_uint32_t byte_cnt_0:32; - a_uint32_t byte_cnt_1:8; - a_uint32_t _reserved0:24; -}; - -union pc_global_cnt_tbl_u { - a_uint32_t val[3]; - struct pc_global_cnt_tbl bf; -}; - -/*[table] DROP_CPU_CNT_TBL*/ -#define DROP_CPU_CNT_TBL -#define DROP_CPU_CNT_TBL_ADDRESS 0x60000 -#define DROP_CPU_CNT_TBL_NUM 1280 -#define DROP_CPU_CNT_TBL_INC 0x10 -#define DROP_CPU_CNT_TBL_TYPE REG_TYPE_RW -#define DROP_CPU_CNT_TBL_DEFAULT 0x0 - /*[field] PKT_CNT*/ - #define DROP_CPU_CNT_TBL_PKT_CNT - #define DROP_CPU_CNT_TBL_PKT_CNT_OFFSET 0 - #define DROP_CPU_CNT_TBL_PKT_CNT_LEN 32 - #define DROP_CPU_CNT_TBL_PKT_CNT_DEFAULT 0x0 - /*[field] BYTE_CNT*/ - #define DROP_CPU_CNT_TBL_BYTE_CNT - #define DROP_CPU_CNT_TBL_BYTE_CNT_OFFSET 32 - #define DROP_CPU_CNT_TBL_BYTE_CNT_LEN 40 - #define DROP_CPU_CNT_TBL_BYTE_CNT_DEFAULT 0x0 - -struct drop_cpu_cnt_tbl { - a_uint32_t pkt_cnt:32; - a_uint32_t byte_cnt_0:32; - a_uint32_t byte_cnt_1:8; - a_uint32_t _reserved0:24; -}; - -union drop_cpu_cnt_tbl_u { - a_uint32_t val[3]; - struct drop_cpu_cnt_tbl bf; -}; - -/*[table] PORT_TX_DROP_CNT_TBL*/ -#define PORT_TX_DROP_CNT_TBL -#define PORT_TX_DROP_CNT_TBL_ADDRESS 0x7d000 -#define PORT_TX_DROP_CNT_TBL_NUM 8 -#define PORT_TX_DROP_CNT_TBL_INC 0x10 -#define PORT_TX_DROP_CNT_TBL_TYPE REG_TYPE_RW -#define PORT_TX_DROP_CNT_TBL_DEFAULT 0x0 - /*[field] TX_DROP_PKT_CNT*/ - #define PORT_TX_DROP_CNT_TBL_TX_DROP_PKT_CNT - #define PORT_TX_DROP_CNT_TBL_TX_DROP_PKT_CNT_OFFSET 0 - #define PORT_TX_DROP_CNT_TBL_TX_DROP_PKT_CNT_LEN 32 - #define PORT_TX_DROP_CNT_TBL_TX_DROP_PKT_CNT_DEFAULT 0x0 - /*[field] TX_DROP_BYTE_CNT*/ - #define PORT_TX_DROP_CNT_TBL_TX_DROP_BYTE_CNT - #define PORT_TX_DROP_CNT_TBL_TX_DROP_BYTE_CNT_OFFSET 32 - #define PORT_TX_DROP_CNT_TBL_TX_DROP_BYTE_CNT_LEN 40 - #define PORT_TX_DROP_CNT_TBL_TX_DROP_BYTE_CNT_DEFAULT 0x0 - -struct port_tx_drop_cnt_tbl { - a_uint32_t tx_drop_pkt_cnt:32; - a_uint32_t tx_drop_byte_cnt_0:32; - a_uint32_t tx_drop_byte_cnt_1:8; - a_uint32_t _reserved0:24; -}; - -union port_tx_drop_cnt_tbl_u { - a_uint32_t val[3]; - struct port_tx_drop_cnt_tbl bf; -}; - -/*[table] VP_TX_DROP_CNT_TBL*/ -#define VP_TX_DROP_CNT_TBL -#define VP_TX_DROP_CNT_TBL_ADDRESS 0x7e000 -#define VP_TX_DROP_CNT_TBL_NUM 256 -#define VP_TX_DROP_CNT_TBL_INC 0x10 -#define VP_TX_DROP_CNT_TBL_TYPE REG_TYPE_RW -#define VP_TX_DROP_CNT_TBL_DEFAULT 0x0 - /*[field] TX_DROP_PKT_CNT*/ - #define VP_TX_DROP_CNT_TBL_TX_DROP_PKT_CNT - #define VP_TX_DROP_CNT_TBL_TX_DROP_PKT_CNT_OFFSET 0 - #define VP_TX_DROP_CNT_TBL_TX_DROP_PKT_CNT_LEN 32 - #define VP_TX_DROP_CNT_TBL_TX_DROP_PKT_CNT_DEFAULT 0x0 - /*[field] TX_DROP_BYTE_CNT*/ - #define VP_TX_DROP_CNT_TBL_TX_DROP_BYTE_CNT - #define VP_TX_DROP_CNT_TBL_TX_DROP_BYTE_CNT_OFFSET 32 - #define VP_TX_DROP_CNT_TBL_TX_DROP_BYTE_CNT_LEN 40 - #define VP_TX_DROP_CNT_TBL_TX_DROP_BYTE_CNT_DEFAULT 0x0 - -struct vp_tx_drop_cnt_tbl { - a_uint32_t tx_drop_pkt_cnt:32; - a_uint32_t tx_drop_byte_cnt_0:32; - a_uint32_t tx_drop_byte_cnt_1:8; - a_uint32_t _reserved0:24; -}; - -union vp_tx_drop_cnt_tbl_u { - a_uint32_t val[3]; - struct vp_tx_drop_cnt_tbl bf; -}; - -/*[table] VLAN_DEV_CNT_TBL*/ -#define VLAN_DEV_CNT_TBL -#define VLAN_DEV_CNT_TBL_ADDRESS 0x7f000 -#define VLAN_DEV_CNT_TBL_NUM 64 -#define VLAN_DEV_CNT_TBL_INC 0x10 -#define VLAN_DEV_CNT_TBL_TYPE REG_TYPE_RW -#define VLAN_DEV_CNT_TBL_DEFAULT 0x0 - /*[field] RX_PKT_CNT*/ - #define VLAN_DEV_CNT_TBL_RX_PKT_CNT - #define VLAN_DEV_CNT_TBL_RX_PKT_CNT_OFFSET 0 - #define VLAN_DEV_CNT_TBL_RX_PKT_CNT_LEN 32 - #define VLAN_DEV_CNT_TBL_RX_PKT_CNT_DEFAULT 0x0 - /*[field] RX_BYTE_CNT*/ - #define VLAN_DEV_CNT_TBL_RX_BYTE_CNT - #define VLAN_DEV_CNT_TBL_RX_BYTE_CNT_OFFSET 32 - #define VLAN_DEV_CNT_TBL_RX_BYTE_CNT_LEN 40 - #define VLAN_DEV_CNT_TBL_RX_BYTE_CNT_DEFAULT 0x0 - -struct vlan_dev_cnt_tbl { - a_uint32_t rx_pkt_cnt:32; - a_uint32_t rx_byte_cnt_0:32; - a_uint32_t rx_byte_cnt_1:8; - a_uint32_t _reserved0:24; -}; - -union vlan_dev_cnt_tbl_u { - a_uint32_t val[3]; - struct vlan_dev_cnt_tbl bf; -}; - - - -#endif diff --git a/feeds/ipq807x/qca-ssdk/src/include/hsl/hppe/hppe_portctrl.h b/feeds/ipq807x/qca-ssdk/src/include/hsl/hppe/hppe_portctrl.h deleted file mode 100755 index e14ed3106..000000000 --- a/feeds/ipq807x/qca-ssdk/src/include/hsl/hppe/hppe_portctrl.h +++ /dev/null @@ -1,1413 +0,0 @@ -/* - * Copyright (c) 2016-2017, The Linux Foundation. All rights reserved. - * Permission to use, copy, modify, and/or distribute this software for - * any purpose with or without fee is hereby granted, provided that the - * above copyright notice and this permission notice appear in all copies. - * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES - * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR - * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES - * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN - * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT - * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. - */ - - -/** - * @defgroup - * @{ - */ -#ifndef _HPPE_PORTCTRL_H_ -#define _HPPE_PORTCTRL_H_ - - -#define MAC_ENABLE_MAX_ENTRY 6 -#define MAC_SPEED_MAX_ENTRY 6 -#define GOL_MAC_ADDR0_MAX_ENTRY 6 -#define GOL_MAC_ADDR1_MAX_ENTRY 6 -#define MAC_CTRL0_MAX_ENTRY 6 -#define MAC_CTRL1_MAX_ENTRY 6 -#define MAC_CTRL2_MAX_ENTRY 6 -#define MAC_DBG_CTRL_MAX_ENTRY 6 -#define MAC_DBG_ADDR_MAX_ENTRY 6 -#define MAC_DBG_DATA_MAX_ENTRY 6 -#define MAC_JUMBO_SIZE_MAX_ENTRY 6 -#define MC_MTU_CTRL_TBL_MAX_ENTRY 8 -#define MRU_MTU_CTRL_TBL_MAX_ENTRY 256 -#define RX_FIFO_CFG_MAX_ENTRY 8 -#define TDM_CFG_MAX_ENTRY 128 -#define PORT_IN_FORWARD_MAX_ENTRY 8 -#define PORT_TX_COUNTER_TBL_REG_MAX_ENTRY 8 -#define VP_TX_COUNTER_TBL_REG_MAX_ENTRY 256 -#define IPR_PKT_NUM_TBL_REG_MAX_ENTRY 8 -#define IPR_BYTE_LOW_REG_REG_MAX_ENTRY 8 -#define IPR_BYTE_HIGH_REG_MAX_ENTRY 8 -#define DROP_CNT_MAX_ENTRY 8 -#define DROP_PKT_STAT_MAX_ENTRY 30 - - -sw_error_t -hppe_mac_enable_get( - a_uint32_t dev_id, - a_uint32_t index, - union mac_enable_u *value); - -sw_error_t -hppe_mac_enable_set( - a_uint32_t dev_id, - a_uint32_t index, - union mac_enable_u *value); - -sw_error_t -hppe_mac_speed_get( - a_uint32_t dev_id, - a_uint32_t index, - union mac_speed_u *value); - -sw_error_t -hppe_mac_speed_set( - a_uint32_t dev_id, - a_uint32_t index, - union mac_speed_u *value); - -sw_error_t -hppe_gol_mac_addr0_get( - a_uint32_t dev_id, - a_uint32_t index, - union gol_mac_addr0_u *value); - -sw_error_t -hppe_gol_mac_addr0_set( - a_uint32_t dev_id, - a_uint32_t index, - union gol_mac_addr0_u *value); - -sw_error_t -hppe_gol_mac_addr1_get( - a_uint32_t dev_id, - a_uint32_t index, - union gol_mac_addr1_u *value); - -sw_error_t -hppe_gol_mac_addr1_set( - a_uint32_t dev_id, - a_uint32_t index, - union gol_mac_addr1_u *value); - -sw_error_t -hppe_mac_ctrl0_get( - a_uint32_t dev_id, - a_uint32_t index, - union mac_ctrl0_u *value); - -sw_error_t -hppe_mac_ctrl0_set( - a_uint32_t dev_id, - a_uint32_t index, - union mac_ctrl0_u *value); - -sw_error_t -hppe_mac_ctrl1_get( - a_uint32_t dev_id, - a_uint32_t index, - union mac_ctrl1_u *value); - -sw_error_t -hppe_mac_ctrl1_set( - a_uint32_t dev_id, - a_uint32_t index, - union mac_ctrl1_u *value); - -sw_error_t -hppe_mac_ctrl2_get( - a_uint32_t dev_id, - a_uint32_t index, - union mac_ctrl2_u *value); - -sw_error_t -hppe_mac_ctrl2_set( - a_uint32_t dev_id, - a_uint32_t index, - union mac_ctrl2_u *value); - -sw_error_t -hppe_mac_dbg_ctrl_get( - a_uint32_t dev_id, - a_uint32_t index, - union mac_dbg_ctrl_u *value); - -sw_error_t -hppe_mac_dbg_ctrl_set( - a_uint32_t dev_id, - a_uint32_t index, - union mac_dbg_ctrl_u *value); - -sw_error_t -hppe_mac_dbg_addr_get( - a_uint32_t dev_id, - a_uint32_t index, - union mac_dbg_addr_u *value); - -sw_error_t -hppe_mac_dbg_addr_set( - a_uint32_t dev_id, - a_uint32_t index, - union mac_dbg_addr_u *value); - -sw_error_t -hppe_mac_dbg_data_get( - a_uint32_t dev_id, - a_uint32_t index, - union mac_dbg_data_u *value); - -sw_error_t -hppe_mac_dbg_data_set( - a_uint32_t dev_id, - a_uint32_t index, - union mac_dbg_data_u *value); - -sw_error_t -hppe_mac_jumbo_size_get( - a_uint32_t dev_id, - a_uint32_t index, - union mac_jumbo_size_u *value); - -sw_error_t -hppe_mac_jumbo_size_set( - a_uint32_t dev_id, - a_uint32_t index, - union mac_jumbo_size_u *value); - -sw_error_t -hppe_mru_mtu_ctrl_tbl_get( - a_uint32_t dev_id, - a_uint32_t index, - union mru_mtu_ctrl_tbl_u *value); - -sw_error_t -hppe_mru_mtu_ctrl_tbl_set( - a_uint32_t dev_id, - a_uint32_t index, - union mru_mtu_ctrl_tbl_u *value); - -sw_error_t -hppe_mc_mtu_ctrl_tbl_get( - a_uint32_t dev_id, - a_uint32_t index, - union mc_mtu_ctrl_tbl_u *value); - -sw_error_t -hppe_mc_mtu_ctrl_tbl_set( - a_uint32_t dev_id, - a_uint32_t index, - union mc_mtu_ctrl_tbl_u *value); - -sw_error_t -hppe_tdm_ctrl_get( - a_uint32_t dev_id, - union tdm_ctrl_u *value); - -sw_error_t -hppe_tdm_ctrl_set( - a_uint32_t dev_id, - union tdm_ctrl_u *value); - -sw_error_t -hppe_rx_fifo_cfg_get( - a_uint32_t dev_id, - a_uint32_t index, - union rx_fifo_cfg_u *value); - -sw_error_t -hppe_rx_fifo_cfg_set( - a_uint32_t dev_id, - a_uint32_t index, - union rx_fifo_cfg_u *value); - -sw_error_t -hppe_tdm_cfg_get( - a_uint32_t dev_id, - a_uint32_t index, - union tdm_cfg_u *value); - -sw_error_t -hppe_tdm_cfg_set( - a_uint32_t dev_id, - a_uint32_t index, - union tdm_cfg_u *value); - -sw_error_t -hppe_drop_stat_get( - a_uint32_t dev_id, - a_uint32_t index, - union drop_stat_u *value); - -sw_error_t -hppe_drop_stat_set( - a_uint32_t dev_id, - a_uint32_t index, - union drop_stat_u *value); - -sw_error_t -hppe_mac_enable_txmac_en_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_mac_enable_txmac_en_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_mac_enable_rxmac_en_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_mac_enable_rxmac_en_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_mac_enable_tx_flow_en_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_mac_enable_tx_flow_en_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_mac_enable_rx_flow_en_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_mac_enable_rx_flow_en_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_mac_enable_duplex_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_mac_enable_duplex_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_mac_speed_mac_speed_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_mac_speed_mac_speed_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_gol_mac_addr0_mac_addr_byte4_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_gol_mac_addr0_mac_addr_byte4_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_gol_mac_addr0_mac_addr_byte5_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_gol_mac_addr0_mac_addr_byte5_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_gol_mac_addr1_mac_addr_byte1_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_gol_mac_addr1_mac_addr_byte1_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_gol_mac_addr1_mac_addr_byte2_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_gol_mac_addr1_mac_addr_byte2_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_gol_mac_addr1_mac_addr_byte0_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_gol_mac_addr1_mac_addr_byte0_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_gol_mac_addr1_mac_addr_byte3_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_gol_mac_addr1_mac_addr_byte3_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_mac_ctrl0_amaxc_en_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_mac_ctrl0_amaxc_en_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_mac_ctrl0_ipgt_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_mac_ctrl0_ipgt_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_mac_ctrl0_nobo_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_mac_ctrl0_nobo_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_mac_ctrl0_half_thdf_ctrl_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_mac_ctrl0_half_thdf_ctrl_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_mac_ctrl0_hugen_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_mac_ctrl0_hugen_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_mac_ctrl0_bpnb_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_mac_ctrl0_bpnb_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_mac_ctrl0_flchk_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_mac_ctrl0_flchk_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_mac_ctrl0_ipgr2_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_mac_ctrl0_ipgr2_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_mac_ctrl0_drbnib_rxok_en_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_mac_ctrl0_drbnib_rxok_en_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_mac_ctrl0_huge_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_mac_ctrl0_huge_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_mac_ctrl0_abebe_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_mac_ctrl0_abebe_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_mac_ctrl1_povr_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_mac_ctrl1_povr_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_mac_ctrl1_simr_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_mac_ctrl1_simr_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_mac_ctrl1_jam_ipg_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_mac_ctrl1_jam_ipg_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_mac_ctrl1_lcol_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_mac_ctrl1_lcol_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_mac_ctrl1_tctl_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_mac_ctrl1_tctl_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_mac_ctrl1_retry_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_mac_ctrl1_retry_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_mac_ctrl1_prlen_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_mac_ctrl1_prlen_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_mac_ctrl1_ppad_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_mac_ctrl1_ppad_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_mac_ctrl1_long_jam_en_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_mac_ctrl1_long_jam_en_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_mac_ctrl1_phug_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_mac_ctrl1_phug_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_mac_ctrl1_sstct_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_mac_ctrl1_sstct_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_mac_ctrl1_mbof_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_mac_ctrl1_mbof_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_mac_ctrl1_tpause_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_mac_ctrl1_tpause_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_mac_ctrl2_ipg_dec_en_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_mac_ctrl2_ipg_dec_en_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_mac_ctrl2_mac_rsv_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_mac_ctrl2_mac_rsv_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_mac_ctrl2_mac_tx_thd_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_mac_ctrl2_mac_tx_thd_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_mac_ctrl2_crc_rsv_en_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_mac_ctrl2_crc_rsv_en_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_mac_ctrl2_crs_sel_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_mac_ctrl2_crs_sel_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_mac_ctrl2_ipg_dec_len_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_mac_ctrl2_ipg_dec_len_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_mac_ctrl2_maxfr_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_mac_ctrl2_maxfr_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_mac_ctrl2_mac_lpi_tx_idle_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_mac_ctrl2_mac_lpi_tx_idle_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_mac_ctrl2_mac_loop_back_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_mac_ctrl2_mac_loop_back_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_mac_ctrl2_test_pause_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_mac_ctrl2_test_pause_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_mac_dbg_ctrl_edxsdfr_transmit_en_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_mac_dbg_ctrl_edxsdfr_transmit_en_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_mac_dbg_ctrl_hihg_ipg_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_mac_dbg_ctrl_hihg_ipg_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_mac_dbg_ctrl_mac_ipg_ctrl_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_mac_dbg_ctrl_mac_ipg_ctrl_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_mac_dbg_ctrl_mac_len_ctrl_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_mac_dbg_ctrl_mac_len_ctrl_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_mac_dbg_ctrl_ipgr1_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_mac_dbg_ctrl_ipgr1_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_mac_dbg_addr_mac_debug_addr_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_mac_dbg_addr_mac_debug_addr_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_mac_dbg_data_mac_debug_data_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_mac_dbg_data_mac_debug_data_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_mac_jumbo_size_mac_jumbo_size_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_mac_jumbo_size_mac_jumbo_size_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_mru_mtu_ctrl_tbl_mtu_cmd_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_mru_mtu_ctrl_tbl_mtu_cmd_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_mru_mtu_ctrl_tbl_rx_cnt_en_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_mru_mtu_ctrl_tbl_rx_cnt_en_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_mru_mtu_ctrl_tbl_tx_cnt_en_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_mru_mtu_ctrl_tbl_tx_cnt_en_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_mru_mtu_ctrl_tbl_mru_cmd_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_mru_mtu_ctrl_tbl_mru_cmd_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_mru_mtu_ctrl_tbl_mru_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_mru_mtu_ctrl_tbl_mru_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_mru_mtu_ctrl_tbl_src_profile_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_mru_mtu_ctrl_tbl_src_profile_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_mru_mtu_ctrl_tbl_mtu_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_mru_mtu_ctrl_tbl_mtu_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_mc_mtu_ctrl_tbl_mtu_cmd_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_mc_mtu_ctrl_tbl_mtu_cmd_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_mc_mtu_ctrl_tbl_tx_cnt_en_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_mc_mtu_ctrl_tbl_tx_cnt_en_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_mc_mtu_ctrl_tbl_mtu_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_mc_mtu_ctrl_tbl_mtu_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); -sw_error_t -hppe_tdm_ctrl_tdm_en_get( - a_uint32_t dev_id, - unsigned int *value); - -sw_error_t -hppe_tdm_ctrl_tdm_en_set( - a_uint32_t dev_id, - unsigned int value); - -sw_error_t -hppe_tdm_ctrl_tdm_offset_get( - a_uint32_t dev_id, - unsigned int *value); - -sw_error_t -hppe_tdm_ctrl_tdm_offset_set( - a_uint32_t dev_id, - unsigned int value); - -sw_error_t -hppe_tdm_ctrl_tdm_depth_get( - a_uint32_t dev_id, - unsigned int *value); - -sw_error_t -hppe_tdm_ctrl_tdm_depth_set( - a_uint32_t dev_id, - unsigned int value); - -sw_error_t -hppe_rx_fifo_cfg_rx_fifo_thres_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_rx_fifo_cfg_rx_fifo_thres_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_tdm_cfg_port_num_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_tdm_cfg_port_num_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_tdm_cfg_valid_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_tdm_cfg_valid_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_tdm_cfg_dir_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_tdm_cfg_dir_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_port_in_forward_get( - a_uint32_t dev_id, - a_uint32_t index, - union port_in_forward_u *value); - -sw_error_t -hppe_port_in_forward_set( - a_uint32_t dev_id, - a_uint32_t index, - union port_in_forward_u *value); - -sw_error_t -hppe_port_in_forward_source_filtering_bypass_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_port_in_forward_source_filtering_bypass_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); -sw_error_t -hppe_port_tx_counter_tbl_reg_get( - a_uint32_t dev_id, - a_uint32_t index, - union port_tx_counter_tbl_reg_u *value); - -sw_error_t -hppe_port_tx_counter_tbl_reg_set( - a_uint32_t dev_id, - a_uint32_t index, - union port_tx_counter_tbl_reg_u *value); - -sw_error_t -hppe_vp_tx_counter_tbl_reg_get( - a_uint32_t dev_id, - a_uint32_t index, - union vp_tx_counter_tbl_reg_u *value); - -sw_error_t -hppe_vp_tx_counter_tbl_reg_set( - a_uint32_t dev_id, - a_uint32_t index, - union vp_tx_counter_tbl_reg_u *value); - -sw_error_t -hppe_epe_dbg_in_cnt_reg_get( - a_uint32_t dev_id, - union epe_dbg_in_cnt_reg_u *value); - -sw_error_t -hppe_epe_dbg_in_cnt_reg_set( - a_uint32_t dev_id, - union epe_dbg_in_cnt_reg_u *value); - -sw_error_t -hppe_epe_dbg_out_cnt_reg_get( - a_uint32_t dev_id, - union epe_dbg_out_cnt_reg_u *value); - -sw_error_t -hppe_epe_dbg_out_cnt_reg_set( - a_uint32_t dev_id, - union epe_dbg_out_cnt_reg_u *value); - -sw_error_t -hppe_port_tx_counter_tbl_reg_tx_bytes_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint64_t *value); - -sw_error_t -hppe_port_tx_counter_tbl_reg_tx_bytes_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint64_t value); - -sw_error_t -hppe_port_tx_counter_tbl_reg_tx_packets_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_port_tx_counter_tbl_reg_tx_packets_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_vp_tx_counter_tbl_reg_tx_bytes_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint64_t *value); - -sw_error_t -hppe_vp_tx_counter_tbl_reg_tx_bytes_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint64_t value); - -sw_error_t -hppe_vp_tx_counter_tbl_reg_tx_packets_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_vp_tx_counter_tbl_reg_tx_packets_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_epe_dbg_in_cnt_reg_counter_get( - a_uint32_t dev_id, - unsigned int *value); - -sw_error_t -hppe_epe_dbg_in_cnt_reg_counter_set( - a_uint32_t dev_id, - unsigned int value); - -sw_error_t -hppe_epe_dbg_out_cnt_reg_counter_get( - a_uint32_t dev_id, - unsigned int *value); - -sw_error_t -hppe_epe_dbg_out_cnt_reg_counter_set( - a_uint32_t dev_id, - unsigned int value); - -sw_error_t -hppe_drop_stat_bytes_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint64_t *value); - -sw_error_t -hppe_drop_stat_bytes_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint64_t value); - -sw_error_t -hppe_drop_stat_pkts_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_drop_stat_pkts_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_lpi_enable_get( - a_uint32_t dev_id, - a_uint32_t index, - union lpi_enable_u *value); - -sw_error_t -hppe_lpi_enable_set( - a_uint32_t dev_id, - a_uint32_t index, - union lpi_enable_u *value); - -sw_error_t -hppe_lpi_timer_get( - a_uint32_t dev_id, - a_uint32_t index, - union lpi_port_timer_u *value); - -sw_error_t -hppe_lpi_timer_set( - a_uint32_t dev_id, - a_uint32_t index, - union lpi_port_timer_u *value); - -sw_error_t -hppe_lpi_dbg_addr_get( - a_uint32_t dev_id, - a_uint32_t index, - union lpi_dbg_addr_u *value); - -sw_error_t -hppe_lpi_adb_addr_set( - a_uint32_t dev_id, - a_uint32_t index, - union lpi_dbg_addr_u *value); - -sw_error_t -hppe_lpi_dbg_data_get( - a_uint32_t dev_id, - a_uint32_t index, - union lpi_dbg_data_u *value); - -sw_error_t -hppe_lpi_adb_data_set( - a_uint32_t dev_id, - a_uint32_t index, - union lpi_dbg_data_u *value); - -sw_error_t -hppe_lpi_cnt_get( - a_uint32_t dev_id, - a_uint32_t index, - union lpi_cnt_u *value); - -sw_error_t -hppe_lpi_cnt_set( - a_uint32_t dev_id, - a_uint32_t index, - union lpi_cnt_u *value); - -sw_error_t -hppe_drop_cnt_get( - a_uint32_t dev_id, - a_uint32_t index, - union drop_cnt_u *value); - -sw_error_t -hppe_drop_cnt_set( - a_uint32_t dev_id, - a_uint32_t index, - union drop_cnt_u *value); - -sw_error_t -hppe_drop_cnt_drop_cnt_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_drop_cnt_drop_cnt_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_ipr_pkt_num_tbl_reg_get( - a_uint32_t dev_id, - a_uint32_t index, - union ipr_pkt_num_tbl_reg_u *value); - -sw_error_t -hppe_ipr_pkt_num_tbl_reg_set( - a_uint32_t dev_id, - a_uint32_t index, - union ipr_pkt_num_tbl_reg_u *value); - -sw_error_t -hppe_ipr_byte_low_reg_reg_get( - a_uint32_t dev_id, - a_uint32_t index, - union ipr_byte_low_reg_reg_u *value); - -sw_error_t -hppe_ipr_byte_low_reg_reg_set( - a_uint32_t dev_id, - a_uint32_t index, - union ipr_byte_low_reg_reg_u *value); - -sw_error_t -hppe_ipr_byte_high_reg_get( - a_uint32_t dev_id, - a_uint32_t index, - union ipr_byte_high_reg_u *value); - -sw_error_t -hppe_ipr_byte_high_reg_set( - a_uint32_t dev_id, - a_uint32_t index, - union ipr_byte_high_reg_u *value); - -sw_error_t -hppe_ipr_pkt_num_tbl_reg_packets_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_ipr_pkt_num_tbl_reg_packets_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_ipr_byte_low_reg_reg_bytes_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_ipr_byte_low_reg_reg_bytes_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_ipr_byte_high_reg_bytes_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_ipr_byte_high_reg_bytes_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - - -#endif - diff --git a/feeds/ipq807x/qca-ssdk/src/include/hsl/hppe/hppe_portctrl_reg.h b/feeds/ipq807x/qca-ssdk/src/include/hsl/hppe/hppe_portctrl_reg.h deleted file mode 100755 index ecef92a42..000000000 --- a/feeds/ipq807x/qca-ssdk/src/include/hsl/hppe/hppe_portctrl_reg.h +++ /dev/null @@ -1,1119 +0,0 @@ -/* - * Copyright (c) 2016-2017, The Linux Foundation. All rights reserved. - * Permission to use, copy, modify, and/or distribute this software for - * any purpose with or without fee is hereby granted, provided that the - * above copyright notice and this permission notice appear in all copies. - * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES - * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR - * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES - * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN - * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT - * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. - */ - - -/** - * @defgroup - * @{ - */ -#ifndef HPPE_PORTCTRL_REG_H -#define HPPE_PORTCTRL_REG_H - -/*[register] MAC_ENABLE*/ -#define MAC_ENABLE -#define MAC_ENABLE_ADDRESS 0x0 -#define MAC_ENABLE_NUM 6 -#define MAC_ENABLE_INC 0x200 -#define MAC_ENABLE_TYPE REG_TYPE_RW -#define MAC_ENABLE_DEFAULT 0x10 - /*[field] RXMAC_EN*/ - #define MAC_ENABLE_RXMAC_EN - #define MAC_ENABLE_RXMAC_EN_OFFSET 0 - #define MAC_ENABLE_RXMAC_EN_LEN 1 - #define MAC_ENABLE_RXMAC_EN_DEFAULT 0x0 - /*[field] TXMAC_EN*/ - #define MAC_ENABLE_TXMAC_EN - #define MAC_ENABLE_TXMAC_EN_OFFSET 1 - #define MAC_ENABLE_TXMAC_EN_LEN 1 - #define MAC_ENABLE_TXMAC_EN_DEFAULT 0x0 - /*[field] DUPLEX*/ - #define MAC_ENABLE_DUPLEX - #define MAC_ENABLE_DUPLEX_OFFSET 4 - #define MAC_ENABLE_DUPLEX_LEN 1 - #define MAC_ENABLE_DUPLEX_DEFAULT 0x1 - /*[field] RX_FLOW_EN*/ - #define MAC_ENABLE_RX_FLOW_EN - #define MAC_ENABLE_RX_FLOW_EN_OFFSET 5 - #define MAC_ENABLE_RX_FLOW_EN_LEN 1 - #define MAC_ENABLE_RX_FLOW_EN_DEFAULT 0x0 - /*[field] TX_FLOW_EN*/ - #define MAC_ENABLE_TX_FLOW_EN - #define MAC_ENABLE_TX_FLOW_EN_OFFSET 6 - #define MAC_ENABLE_TX_FLOW_EN_LEN 1 - #define MAC_ENABLE_TX_FLOW_EN_DEFAULT 0x0 - -struct mac_enable { - a_uint32_t rxmac_en:1; - a_uint32_t txmac_en:1; - a_uint32_t _reserved0:2; - a_uint32_t duplex:1; - a_uint32_t rx_flow_en:1; - a_uint32_t tx_flow_en:1; - a_uint32_t _reserved1:25; -}; - -union mac_enable_u { - a_uint32_t val; - struct mac_enable bf; -}; - -/*[register] MAC_SPEED*/ -#define MAC_SPEED -#define MAC_SPEED_ADDRESS 0x4 -#define MAC_SPEED_NUM 6 -#define MAC_SPEED_INC 0x200 -#define MAC_SPEED_TYPE REG_TYPE_RW -#define MAC_SPEED_DEFAULT 0x0 - /*[field] MAC_SPEED*/ - #define MAC_SPEED_MAC_SPEED - #define MAC_SPEED_MAC_SPEED_OFFSET 0 - #define MAC_SPEED_MAC_SPEED_LEN 2 - #define MAC_SPEED_MAC_SPEED_DEFAULT 0x0 - -struct mac_speed { - a_uint32_t mac_speed:2; - a_uint32_t _reserved0:30; -}; - -union mac_speed_u { - a_uint32_t val; - struct mac_speed bf; -}; - -/*[register] GOL_MAC_ADDR0*/ -#define GOL_MAC_ADDR0 -#define GOL_MAC_ADDR0_ADDRESS 0x8 -#define GOL_MAC_ADDR0_NUM 6 -#define GOL_MAC_ADDR0_INC 0x200 -#define GOL_MAC_ADDR0_TYPE REG_TYPE_RW -#define GOL_MAC_ADDR0_DEFAULT 0x1 - /*[field] MAC_ADDR_BYTE4*/ - #define GOL_MAC_ADDR0_MAC_ADDR_BYTE4 - #define GOL_MAC_ADDR0_MAC_ADDR_BYTE4_OFFSET 0 - #define GOL_MAC_ADDR0_MAC_ADDR_BYTE4_LEN 8 - #define GOL_MAC_ADDR0_MAC_ADDR_BYTE4_DEFAULT 0x1 - /*[field] MAC_ADDR_BYTE5*/ - #define GOL_MAC_ADDR0_MAC_ADDR_BYTE5 - #define GOL_MAC_ADDR0_MAC_ADDR_BYTE5_OFFSET 8 - #define GOL_MAC_ADDR0_MAC_ADDR_BYTE5_LEN 8 - #define GOL_MAC_ADDR0_MAC_ADDR_BYTE5_DEFAULT 0x0 - -struct gol_mac_addr0 { - a_uint32_t mac_addr_byte4:8; - a_uint32_t mac_addr_byte5:8; - a_uint32_t _reserved0:16; -}; - -union gol_mac_addr0_u { - a_uint32_t val; - struct gol_mac_addr0 bf; -}; - -/*[register] GOL_MAC_ADDR1*/ -#define GOL_MAC_ADDR1 -#define GOL_MAC_ADDR1_ADDRESS 0xc -#define GOL_MAC_ADDR1_NUM 6 -#define GOL_MAC_ADDR1_INC 0x200 -#define GOL_MAC_ADDR1_TYPE REG_TYPE_RW -#define GOL_MAC_ADDR1_DEFAULT 0x0 - /*[field] MAC_ADDR_BYTE3*/ - #define GOL_MAC_ADDR1_MAC_ADDR_BYTE3 - #define GOL_MAC_ADDR1_MAC_ADDR_BYTE3_OFFSET 0 - #define GOL_MAC_ADDR1_MAC_ADDR_BYTE3_LEN 8 - #define GOL_MAC_ADDR1_MAC_ADDR_BYTE3_DEFAULT 0x0 - /*[field] MAC_ADDR_BYTE2*/ - #define GOL_MAC_ADDR1_MAC_ADDR_BYTE2 - #define GOL_MAC_ADDR1_MAC_ADDR_BYTE2_OFFSET 8 - #define GOL_MAC_ADDR1_MAC_ADDR_BYTE2_LEN 8 - #define GOL_MAC_ADDR1_MAC_ADDR_BYTE2_DEFAULT 0x0 - /*[field] MAC_ADDR_BYTE1*/ - #define GOL_MAC_ADDR1_MAC_ADDR_BYTE1 - #define GOL_MAC_ADDR1_MAC_ADDR_BYTE1_OFFSET 16 - #define GOL_MAC_ADDR1_MAC_ADDR_BYTE1_LEN 8 - #define GOL_MAC_ADDR1_MAC_ADDR_BYTE1_DEFAULT 0x0 - /*[field] MAC_ADDR_BYTE0*/ - #define GOL_MAC_ADDR1_MAC_ADDR_BYTE0 - #define GOL_MAC_ADDR1_MAC_ADDR_BYTE0_OFFSET 24 - #define GOL_MAC_ADDR1_MAC_ADDR_BYTE0_LEN 8 - #define GOL_MAC_ADDR1_MAC_ADDR_BYTE0_DEFAULT 0x0 - -struct gol_mac_addr1 { - a_uint32_t mac_addr_byte3:8; - a_uint32_t mac_addr_byte2:8; - a_uint32_t mac_addr_byte1:8; - a_uint32_t mac_addr_byte0:8; -}; - -union gol_mac_addr1_u { - a_uint32_t val; - struct gol_mac_addr1 bf; -}; - -/*[register] MAC_CTRL0*/ -#define MAC_CTRL0 -#define MAC_CTRL0_ADDRESS 0x10 -#define MAC_CTRL0_NUM 6 -#define MAC_CTRL0_INC 0x200 -#define MAC_CTRL0_TYPE REG_TYPE_RW -#define MAC_CTRL0_DEFAULT 0xb00e6060 - /*[field] IPGT*/ - #define MAC_CTRL0_IPGT - #define MAC_CTRL0_IPGT_OFFSET 0 - #define MAC_CTRL0_IPGT_LEN 7 - #define MAC_CTRL0_IPGT_DEFAULT 0x60 - /*[field] IPGR2*/ - #define MAC_CTRL0_IPGR2 - #define MAC_CTRL0_IPGR2_OFFSET 8 - #define MAC_CTRL0_IPGR2_LEN 7 - #define MAC_CTRL0_IPGR2_DEFAULT 0x60 - /*[field] HALF_THDF_CTRL*/ - #define MAC_CTRL0_HALF_THDF_CTRL - #define MAC_CTRL0_HALF_THDF_CTRL_OFFSET 15 - #define MAC_CTRL0_HALF_THDF_CTRL_LEN 1 - #define MAC_CTRL0_HALF_THDF_CTRL_DEFAULT 0x0 - /*[field] HUGEN*/ - #define MAC_CTRL0_HUGEN - #define MAC_CTRL0_HUGEN_OFFSET 16 - #define MAC_CTRL0_HUGEN_LEN 1 - #define MAC_CTRL0_HUGEN_DEFAULT 0x0 - /*[field] HUGE*/ - #define MAC_CTRL0_HUGE - #define MAC_CTRL0_HUGE_OFFSET 17 - #define MAC_CTRL0_HUGE_LEN 1 - #define MAC_CTRL0_HUGE_DEFAULT 0x1 - /*[field] FLCHK*/ - #define MAC_CTRL0_FLCHK - #define MAC_CTRL0_FLCHK_OFFSET 18 - #define MAC_CTRL0_FLCHK_LEN 1 - #define MAC_CTRL0_FLCHK_DEFAULT 0x1 - /*[field] ABEBE*/ - #define MAC_CTRL0_ABEBE - #define MAC_CTRL0_ABEBE_OFFSET 19 - #define MAC_CTRL0_ABEBE_LEN 1 - #define MAC_CTRL0_ABEBE_DEFAULT 0x1 - /*[field] AMAXC_EN*/ - #define MAC_CTRL0_AMAXC_EN - #define MAC_CTRL0_AMAXC_EN_OFFSET 28 - #define MAC_CTRL0_AMAXC_EN_LEN 1 - #define MAC_CTRL0_AMAXC_EN_DEFAULT 0x1 - /*[field] BPNB*/ - #define MAC_CTRL0_BPNB - #define MAC_CTRL0_BPNB_OFFSET 29 - #define MAC_CTRL0_BPNB_LEN 1 - #define MAC_CTRL0_BPNB_DEFAULT 0x1 - /*[field] NOBO*/ - #define MAC_CTRL0_NOBO - #define MAC_CTRL0_NOBO_OFFSET 30 - #define MAC_CTRL0_NOBO_LEN 1 - #define MAC_CTRL0_NOBO_DEFAULT 0x0 - /*[field] DRBNIB_RXOK_EN*/ - #define MAC_CTRL0_DRBNIB_RXOK_EN - #define MAC_CTRL0_DRBNIB_RXOK_EN_OFFSET 31 - #define MAC_CTRL0_DRBNIB_RXOK_EN_LEN 1 - #define MAC_CTRL0_DRBNIB_RXOK_EN_DEFAULT 0x1 - -struct mac_ctrl0 { - a_uint32_t ipgt:7; - a_uint32_t _reserved0:1; - a_uint32_t ipgr2:7; - a_uint32_t half_thdf_ctrl:1; - a_uint32_t hugen:1; - a_uint32_t huge:1; - a_uint32_t flchk:1; - a_uint32_t abebe:1; - a_uint32_t _reserved1:8; - a_uint32_t amaxc_en:1; - a_uint32_t bpnb:1; - a_uint32_t nobo:1; - a_uint32_t drbnib_rxok_en:1; -}; - -union mac_ctrl0_u { - a_uint32_t val; - struct mac_ctrl0 bf; -}; - -/*[register] MAC_CTRL1*/ -#define MAC_CTRL1 -#define MAC_CTRL1_ADDRESS 0x14 -#define MAC_CTRL1_NUM 6 -#define MAC_CTRL1_INC 0x200 -#define MAC_CTRL1_TYPE REG_TYPE_RW -#define MAC_CTRL1_DEFAULT 0x3707f07 - /*[field] JAM_IPG*/ - #define MAC_CTRL1_JAM_IPG - #define MAC_CTRL1_JAM_IPG_OFFSET 0 - #define MAC_CTRL1_JAM_IPG_LEN 4 - #define MAC_CTRL1_JAM_IPG_DEFAULT 0x7 - /*[field] TPAUSE*/ - #define MAC_CTRL1_TPAUSE - #define MAC_CTRL1_TPAUSE_OFFSET 4 - #define MAC_CTRL1_TPAUSE_LEN 1 - #define MAC_CTRL1_TPAUSE_DEFAULT 0x0 - /*[field] TCTL*/ - #define MAC_CTRL1_TCTL - #define MAC_CTRL1_TCTL_OFFSET 5 - #define MAC_CTRL1_TCTL_LEN 1 - #define MAC_CTRL1_TCTL_DEFAULT 0x0 - /*[field] SSTCT*/ - #define MAC_CTRL1_SSTCT - #define MAC_CTRL1_SSTCT_OFFSET 6 - #define MAC_CTRL1_SSTCT_LEN 1 - #define MAC_CTRL1_SSTCT_DEFAULT 0x0 - /*[field] SIMR*/ - #define MAC_CTRL1_SIMR - #define MAC_CTRL1_SIMR_OFFSET 7 - #define MAC_CTRL1_SIMR_LEN 1 - #define MAC_CTRL1_SIMR_DEFAULT 0x0 - /*[field] RETRY*/ - #define MAC_CTRL1_RETRY - #define MAC_CTRL1_RETRY_OFFSET 8 - #define MAC_CTRL1_RETRY_LEN 4 - #define MAC_CTRL1_RETRY_DEFAULT 0xf - /*[field] PRLEN*/ - #define MAC_CTRL1_PRLEN - #define MAC_CTRL1_PRLEN_OFFSET 12 - #define MAC_CTRL1_PRLEN_LEN 4 - #define MAC_CTRL1_PRLEN_DEFAULT 0x7 - /*[field] PPAD*/ - #define MAC_CTRL1_PPAD - #define MAC_CTRL1_PPAD_OFFSET 16 - #define MAC_CTRL1_PPAD_LEN 1 - #define MAC_CTRL1_PPAD_DEFAULT 0x0 - /*[field] POVR*/ - #define MAC_CTRL1_POVR - #define MAC_CTRL1_POVR_OFFSET 17 - #define MAC_CTRL1_POVR_LEN 1 - #define MAC_CTRL1_POVR_DEFAULT 0x0 - /*[field] PHUG*/ - #define MAC_CTRL1_PHUG - #define MAC_CTRL1_PHUG_OFFSET 18 - #define MAC_CTRL1_PHUG_LEN 1 - #define MAC_CTRL1_PHUG_DEFAULT 0x0 - /*[field] MBOF*/ - #define MAC_CTRL1_MBOF - #define MAC_CTRL1_MBOF_OFFSET 19 - #define MAC_CTRL1_MBOF_LEN 1 - #define MAC_CTRL1_MBOF_DEFAULT 0x0 - /*[field] LCOL*/ - #define MAC_CTRL1_LCOL - #define MAC_CTRL1_LCOL_OFFSET 20 - #define MAC_CTRL1_LCOL_LEN 8 - #define MAC_CTRL1_LCOL_DEFAULT 0x37 - /*[field] LONG_JAM_EN*/ - #define MAC_CTRL1_LONG_JAM_EN - #define MAC_CTRL1_LONG_JAM_EN_OFFSET 28 - #define MAC_CTRL1_LONG_JAM_EN_LEN 1 - #define MAC_CTRL1_LONG_JAM_EN_DEFAULT 0x0 - -struct mac_ctrl1 { - a_uint32_t jam_ipg:4; - a_uint32_t tpause:1; - a_uint32_t tctl:1; - a_uint32_t sstct:1; - a_uint32_t simr:1; - a_uint32_t retry:4; - a_uint32_t prlen:4; - a_uint32_t ppad:1; - a_uint32_t povr:1; - a_uint32_t phug:1; - a_uint32_t mbof:1; - a_uint32_t lcol:8; - a_uint32_t long_jam_en:1; - a_uint32_t _reserved0:3; -}; - -union mac_ctrl1_u { - a_uint32_t val; - struct mac_ctrl1 bf; -}; - -/*[register] MAC_CTRL2*/ -#define MAC_CTRL2 -#define MAC_CTRL2_ADDRESS 0x18 -#define MAC_CTRL2_NUM 6 -#define MAC_CTRL2_INC 0x200 -#define MAC_CTRL2_TYPE REG_TYPE_RW -#define MAC_CTRL2_DEFAULT 0xc271c40 - /*[field] IPG_DEC_LEN*/ - #define MAC_CTRL2_IPG_DEC_LEN - #define MAC_CTRL2_IPG_DEC_LEN_OFFSET 1 - #define MAC_CTRL2_IPG_DEC_LEN_LEN 1 - #define MAC_CTRL2_IPG_DEC_LEN_DEFAULT 0x0 - /*[field] TEST_PAUSE*/ - #define MAC_CTRL2_TEST_PAUSE - #define MAC_CTRL2_TEST_PAUSE_OFFSET 2 - #define MAC_CTRL2_TEST_PAUSE_LEN 1 - #define MAC_CTRL2_TEST_PAUSE_DEFAULT 0x0 - /*[field] MAC_LPI_TX_IDLE*/ - #define MAC_CTRL2_MAC_LPI_TX_IDLE - #define MAC_CTRL2_MAC_LPI_TX_IDLE_OFFSET 3 - #define MAC_CTRL2_MAC_LPI_TX_IDLE_LEN 1 - #define MAC_CTRL2_MAC_LPI_TX_IDLE_DEFAULT 0x0 - /*[field] MAC_LOOP_BACK*/ - #define MAC_CTRL2_MAC_LOOP_BACK - #define MAC_CTRL2_MAC_LOOP_BACK_OFFSET 4 - #define MAC_CTRL2_MAC_LOOP_BACK_LEN 1 - #define MAC_CTRL2_MAC_LOOP_BACK_DEFAULT 0x0 - /*[field] IPG_DEC_EN*/ - #define MAC_CTRL2_IPG_DEC_EN - #define MAC_CTRL2_IPG_DEC_EN_OFFSET 5 - #define MAC_CTRL2_IPG_DEC_EN_LEN 1 - #define MAC_CTRL2_IPG_DEC_EN_DEFAULT 0x0 - /*[field] CRS_SEL*/ - #define MAC_CTRL2_CRS_SEL - #define MAC_CTRL2_CRS_SEL_OFFSET 6 - #define MAC_CTRL2_CRS_SEL_LEN 1 - #define MAC_CTRL2_CRS_SEL_DEFAULT 0x1 - /*[field] CRC_RSV_EN*/ - #define MAC_CTRL2_CRC_RSV_EN - #define MAC_CTRL2_CRC_RSV_EN_OFFSET 7 - #define MAC_CTRL2_CRC_RSV_EN_LEN 1 - #define MAC_CTRL2_CRC_RSV_EN_DEFAULT 0x0 - /*[field] MAXFR*/ - #define MAC_CTRL2_MAXFR - #define MAC_CTRL2_MAXFR_OFFSET 8 - #define MAC_CTRL2_MAXFR_LEN 14 - #define MAC_CTRL2_MAXFR_DEFAULT 0x271c - /*[field] MAC_TX_THD*/ - #define MAC_CTRL2_MAC_TX_THD - #define MAC_CTRL2_MAC_TX_THD_OFFSET 24 - #define MAC_CTRL2_MAC_TX_THD_LEN 4 - #define MAC_CTRL2_MAC_TX_THD_DEFAULT 0xc - /*[field] MAC_RSV*/ - #define MAC_CTRL2_MAC_RSV - #define MAC_CTRL2_MAC_RSV_OFFSET 28 - #define MAC_CTRL2_MAC_RSV_LEN 4 - #define MAC_CTRL2_MAC_RSV_DEFAULT 0x0 - -struct mac_ctrl2 { - a_uint32_t _reserved0:1; - a_uint32_t ipg_dec_len:1; - a_uint32_t test_pause:1; - a_uint32_t mac_lpi_tx_idle:1; - a_uint32_t mac_loop_back:1; - a_uint32_t ipg_dec_en:1; - a_uint32_t crs_sel:1; - a_uint32_t crc_rsv_en:1; - a_uint32_t maxfr:14; - a_uint32_t _reserved1:2; - a_uint32_t mac_tx_thd:4; - a_uint32_t mac_rsv:4; -}; - -union mac_ctrl2_u { - a_uint32_t val; - struct mac_ctrl2 bf; -}; - -/*[register] MAC_DBG_CTRL*/ -#define MAC_DBG_CTRL -#define MAC_DBG_CTRL_ADDRESS 0x1c -#define MAC_DBG_CTRL_NUM 6 -#define MAC_DBG_CTRL_INC 0x200 -#define MAC_DBG_CTRL_TYPE REG_TYPE_RW -#define MAC_DBG_CTRL_DEFAULT 0x80701040 - /*[field] IPGR1*/ - #define MAC_DBG_CTRL_IPGR1 - #define MAC_DBG_CTRL_IPGR1_OFFSET 0 - #define MAC_DBG_CTRL_IPGR1_LEN 7 - #define MAC_DBG_CTRL_IPGR1_DEFAULT 0x40 - /*[field] HIHG_IPG*/ - #define MAC_DBG_CTRL_HIHG_IPG - #define MAC_DBG_CTRL_HIHG_IPG_OFFSET 8 - #define MAC_DBG_CTRL_HIHG_IPG_LEN 8 - #define MAC_DBG_CTRL_HIHG_IPG_DEFAULT 0x10 - /*[field] MAC_IPG_CTRL*/ - #define MAC_DBG_CTRL_MAC_IPG_CTRL - #define MAC_DBG_CTRL_MAC_IPG_CTRL_OFFSET 20 - #define MAC_DBG_CTRL_MAC_IPG_CTRL_LEN 4 - #define MAC_DBG_CTRL_MAC_IPG_CTRL_DEFAULT 0x7 - /*[field] MAC_LEN_CTRL*/ - #define MAC_DBG_CTRL_MAC_LEN_CTRL - #define MAC_DBG_CTRL_MAC_LEN_CTRL_OFFSET 30 - #define MAC_DBG_CTRL_MAC_LEN_CTRL_LEN 1 - #define MAC_DBG_CTRL_MAC_LEN_CTRL_DEFAULT 0x0 - /*[field] EDXSDFR_TRANSMIT_EN*/ - #define MAC_DBG_CTRL_EDXSDFR_TRANSMIT_EN - #define MAC_DBG_CTRL_EDXSDFR_TRANSMIT_EN_OFFSET 31 - #define MAC_DBG_CTRL_EDXSDFR_TRANSMIT_EN_LEN 1 - #define MAC_DBG_CTRL_EDXSDFR_TRANSMIT_EN_DEFAULT 0x1 - -struct mac_dbg_ctrl { - a_uint32_t ipgr1:7; - a_uint32_t _reserved0:1; - a_uint32_t hihg_ipg:8; - a_uint32_t _reserved1:4; - a_uint32_t mac_ipg_ctrl:4; - a_uint32_t _reserved2:6; - a_uint32_t mac_len_ctrl:1; - a_uint32_t edxsdfr_transmit_en:1; -}; - -union mac_dbg_ctrl_u { - a_uint32_t val; - struct mac_dbg_ctrl bf; -}; - -/*[register] MAC_DBG_ADDR*/ -#define MAC_DBG_ADDR -#define MAC_DBG_ADDR_ADDRESS 0x20 -#define MAC_DBG_ADDR_NUM 6 -#define MAC_DBG_ADDR_INC 0x200 -#define MAC_DBG_ADDR_TYPE REG_TYPE_RW -#define MAC_DBG_ADDR_DEFAULT 0x0 - /*[field] MAC_DEBUG_ADDR*/ - #define MAC_DBG_ADDR_MAC_DEBUG_ADDR - #define MAC_DBG_ADDR_MAC_DEBUG_ADDR_OFFSET 0 - #define MAC_DBG_ADDR_MAC_DEBUG_ADDR_LEN 8 - #define MAC_DBG_ADDR_MAC_DEBUG_ADDR_DEFAULT 0x0 - -struct mac_dbg_addr { - a_uint32_t mac_debug_addr:8; - a_uint32_t _reserved0:24; -}; - -union mac_dbg_addr_u { - a_uint32_t val; - struct mac_dbg_addr bf; -}; - -/*[register] MAC_DBG_DATA*/ -#define MAC_DBG_DATA -#define MAC_DBG_DATA_ADDRESS 0x24 -#define MAC_DBG_DATA_NUM 6 -#define MAC_DBG_DATA_INC 0x200 -#define MAC_DBG_DATA_TYPE REG_TYPE_RO -#define MAC_DBG_DATA_DEFAULT 0x0 - /*[field] MAC_DEBUG_DATA*/ - #define MAC_DBG_DATA_MAC_DEBUG_DATA - #define MAC_DBG_DATA_MAC_DEBUG_DATA_OFFSET 0 - #define MAC_DBG_DATA_MAC_DEBUG_DATA_LEN 32 - #define MAC_DBG_DATA_MAC_DEBUG_DATA_DEFAULT 0x0 - -struct mac_dbg_data { - a_uint32_t mac_debug_data:32; -}; - -union mac_dbg_data_u { - a_uint32_t val; - struct mac_dbg_data bf; -}; - -/*[register] MAC_JUMBO_SIZE*/ -#define MAC_JUMBO_SIZE -#define MAC_JUMBO_SIZE_ADDRESS 0x30 -#define MAC_JUMBO_SIZE_NUM 6 -#define MAC_JUMBO_SIZE_INC 0x200 -#define MAC_JUMBO_SIZE_TYPE REG_TYPE_RW -#define MAC_JUMBO_SIZE_DEFAULT 0x271c - /*[field] MAC_JUMBO_SIZE*/ - #define MAC_JUMBO_SIZE_MAC_JUMBO_SIZE - #define MAC_JUMBO_SIZE_MAC_JUMBO_SIZE_OFFSET 0 - #define MAC_JUMBO_SIZE_MAC_JUMBO_SIZE_LEN 14 - #define MAC_JUMBO_SIZE_MAC_JUMBO_SIZE_DEFAULT 0x271c - -struct mac_jumbo_size { - a_uint32_t mac_jumbo_size:14; - a_uint32_t _reserved0:18; -}; - -union mac_jumbo_size_u { - a_uint32_t val; - struct mac_jumbo_size bf; -}; - -/*[register] PORT_IN_FORWARD*/ -#define PORT_IN_FORWARD -#define PORT_IN_FORWARD_ADDRESS 0x700 -#define PORT_IN_FORWARD_NUM 8 -#define PORT_IN_FORWARD_INC 0x4 -#define PORT_IN_FORWARD_TYPE REG_TYPE_RW -#define PORT_IN_FORWARD_DEFAULT 0x0 - /*[field] SOURCE_FILTERING_BYPASS*/ - #define PORT_IN_FORWARD_SOURCE_FILTERING_BYPASS - #define PORT_IN_FORWARD_SOURCE_FILTERING_BYPASS_OFFSET 0 - #define PORT_IN_FORWARD_SOURCE_FILTERING_BYPASS_LEN 1 - #define PORT_IN_FORWARD_SOURCE_FILTERING_BYPASS_DEFAULT 0x0 - -struct port_in_forward { - a_uint32_t source_filtering_bypass:1; - a_uint32_t _reserved0:31; -}; - -union port_in_forward_u { - a_uint32_t val; - struct port_in_forward bf; -}; - -/*[table] MRU_MTU_CTRL_TBL*/ -#define MRU_MTU_CTRL_TBL -#define MRU_MTU_CTRL_TBL_ADDRESS 0x3000 -#define MRU_MTU_CTRL_TBL_NUM 256 -#define MRU_MTU_CTRL_TBL_INC 0x8 -#define MRU_MTU_CTRL_TBL_TYPE REG_TYPE_RW -#define MRU_MTU_CTRL_TBL_DEFAULT 0x0 - /*[field] MRU*/ - #define MRU_MTU_CTRL_TBL_MRU - #define MRU_MTU_CTRL_TBL_MRU_OFFSET 0 - #define MRU_MTU_CTRL_TBL_MRU_LEN 14 - #define MRU_MTU_CTRL_TBL_MRU_DEFAULT 0x0 - /*[field] MRU_CMD*/ - #define MRU_MTU_CTRL_TBL_MRU_CMD - #define MRU_MTU_CTRL_TBL_MRU_CMD_OFFSET 14 - #define MRU_MTU_CTRL_TBL_MRU_CMD_LEN 2 - #define MRU_MTU_CTRL_TBL_MRU_CMD_DEFAULT 0x0 - /*[field] MTU*/ - #define MRU_MTU_CTRL_TBL_MTU - #define MRU_MTU_CTRL_TBL_MTU_OFFSET 16 - #define MRU_MTU_CTRL_TBL_MTU_LEN 14 - #define MRU_MTU_CTRL_TBL_MTU_DEFAULT 0x0 - /*[field] MTU_CMD*/ - #define MRU_MTU_CTRL_TBL_MTU_CMD - #define MRU_MTU_CTRL_TBL_MTU_CMD_OFFSET 30 - #define MRU_MTU_CTRL_TBL_MTU_CMD_LEN 2 - #define MRU_MTU_CTRL_TBL_MTU_CMD_DEFAULT 0x0 - /*[field] RX_CNT_EN*/ - #define MRU_MTU_CTRL_TBL_RX_CNT_EN - #define MRU_MTU_CTRL_TBL_RX_CNT_EN_OFFSET 32 - #define MRU_MTU_CTRL_TBL_RX_CNT_EN_LEN 1 - #define MRU_MTU_CTRL_TBL_RX_CNT_EN_DEFAULT 0x0 - /*[field] TX_CNT_EN*/ - #define MRU_MTU_CTRL_TBL_TX_CNT_EN - #define MRU_MTU_CTRL_TBL_TX_CNT_EN_OFFSET 33 - #define MRU_MTU_CTRL_TBL_TX_CNT_EN_LEN 1 - #define MRU_MTU_CTRL_TBL_TX_CNT_EN_DEFAULT 0x0 - /*[field] SRC_PROFILE*/ - #define MRU_MTU_CTRL_TBL_SRC_PROFILE - #define MRU_MTU_CTRL_TBL_SRC_PROFILE_OFFSET 34 - #define MRU_MTU_CTRL_TBL_SRC_PROFILE_LEN 2 - #define MRU_MTU_CTRL_TBL_SRC_PROFILE_DEFAULT 0x0 - -struct mru_mtu_ctrl_tbl { - a_uint32_t mru:14; - a_uint32_t mru_cmd:2; - a_uint32_t mtu:14; - a_uint32_t mtu_cmd:2; - a_uint32_t rx_cnt_en:1; - a_uint32_t tx_cnt_en:1; - a_uint32_t src_profile:2; - a_uint32_t _reserved0:28; -}; - -union mru_mtu_ctrl_tbl_u { - a_uint32_t val[2]; - struct mru_mtu_ctrl_tbl bf; -}; - -/*[register] MC_MTU_CTRL_TBL*/ -#define MC_MTU_CTRL_TBL -#define MC_MTU_CTRL_TBL_ADDRESS 0xa00 -#define MC_MTU_CTRL_TBL_NUM 8 -#define MC_MTU_CTRL_TBL_INC 0x4 -#define MC_MTU_CTRL_TBL_TYPE REG_TYPE_RW -#define MC_MTU_CTRL_TBL_DEFAULT 0x5ea - /*[field] MTU*/ - #define MC_MTU_CTRL_TBL_MTU - #define MC_MTU_CTRL_TBL_MTU_OFFSET 0 - #define MC_MTU_CTRL_TBL_MTU_LEN 14 - #define MC_MTU_CTRL_TBL_MTU_DEFAULT 0x5ea - /*[field] MTU_CMD*/ - #define MC_MTU_CTRL_TBL_MTU_CMD - #define MC_MTU_CTRL_TBL_MTU_CMD_OFFSET 14 - #define MC_MTU_CTRL_TBL_MTU_CMD_LEN 2 - #define MC_MTU_CTRL_TBL_MTU_CMD_DEFAULT 0x0 - /*[field] TX_CNT_EN*/ - #define MC_MTU_CTRL_TBL_TX_CNT_EN - #define MC_MTU_CTRL_TBL_TX_CNT_EN_OFFSET 16 - #define MC_MTU_CTRL_TBL_TX_CNT_EN_LEN 1 - #define MC_MTU_CTRL_TBL_TX_CNT_EN_DEFAULT 0x0 - -struct mc_mtu_ctrl_tbl { - a_uint32_t mtu:14; - a_uint32_t mtu_cmd:2; - a_uint32_t tx_cnt_en:1; - a_uint32_t _reserved0:15; -}; - -union mc_mtu_ctrl_tbl_u { - a_uint32_t val; - struct mc_mtu_ctrl_tbl bf; -}; - -/*[register] TDM_CTRL*/ -#define TDM_CTRL -#define TDM_CTRL_ADDRESS 0x0 -#define TDM_CTRL_NUM 1 -#define TDM_CTRL_INC 0x4 -#define TDM_CTRL_TYPE REG_TYPE_RW -#define TDM_CTRL_DEFAULT 0x80000050 - /*[field] TDM_DEPTH*/ - #define TDM_CTRL_TDM_DEPTH - #define TDM_CTRL_TDM_DEPTH_OFFSET 0 - #define TDM_CTRL_TDM_DEPTH_LEN 8 - #define TDM_CTRL_TDM_DEPTH_DEFAULT 0x50 - /*[field] TDM_OFFSET*/ - #define TDM_CTRL_TDM_OFFSET - #define TDM_CTRL_TDM_OFFSET_OFFSET 8 - #define TDM_CTRL_TDM_OFFSET_LEN 7 - #define TDM_CTRL_TDM_OFFSET_DEFAULT 0x0 - /*[field] TDM_EN*/ - #define TDM_CTRL_TDM_EN - #define TDM_CTRL_TDM_EN_OFFSET 31 - #define TDM_CTRL_TDM_EN_LEN 1 - #define TDM_CTRL_TDM_EN_DEFAULT 0x1 - -struct tdm_ctrl { - a_uint32_t tdm_depth:8; - a_uint32_t tdm_offset:7; - a_uint32_t _reserved0:16; - a_uint32_t tdm_en:1; -}; - -union tdm_ctrl_u { - a_uint32_t val; - struct tdm_ctrl bf; -}; - -/*[register] RX_FIFO_CFG*/ -#define RX_FIFO_CFG -#define RX_FIFO_CFG_ADDRESS 0x4 -#define RX_FIFO_CFG_NUM 8 -#define RX_FIFO_CFG_INC 0x4 -#define RX_FIFO_CFG_TYPE REG_TYPE_RW -#define RX_FIFO_CFG_DEFAULT 0x4 - /*[field] RX_FIFO_THRES*/ - #define RX_FIFO_CFG_RX_FIFO_THRES - #define RX_FIFO_CFG_RX_FIFO_THRES_OFFSET 0 - #define RX_FIFO_CFG_RX_FIFO_THRES_LEN 3 - #define RX_FIFO_CFG_RX_FIFO_THRES_DEFAULT 0x4 - -struct rx_fifo_cfg { - a_uint32_t rx_fifo_thres:3; - a_uint32_t _reserved0:29; -}; - -union rx_fifo_cfg_u { - a_uint32_t val; - struct rx_fifo_cfg bf; -}; - -/*[table] TDM_CFG*/ -#define TDM_CFG -#define TDM_CFG_ADDRESS 0x1000 -#define TDM_CFG_NUM 128 -#define TDM_CFG_INC 0x10 -#define TDM_CFG_TYPE REG_TYPE_RW -#define TDM_CFG_DEFAULT 0x0 - /*[field] PORT_NUM*/ - #define TDM_CFG_PORT_NUM - #define TDM_CFG_PORT_NUM_OFFSET 0 - #define TDM_CFG_PORT_NUM_LEN 4 - #define TDM_CFG_PORT_NUM_DEFAULT 0x0 - /*[field] DIR*/ - #define TDM_CFG_DIR - #define TDM_CFG_DIR_OFFSET 4 - #define TDM_CFG_DIR_LEN 1 - #define TDM_CFG_DIR_DEFAULT 0x0 - /*[field] VALID*/ - #define TDM_CFG_VALID - #define TDM_CFG_VALID_OFFSET 5 - #define TDM_CFG_VALID_LEN 1 - #define TDM_CFG_VALID_DEFAULT 0x0 - -struct tdm_cfg { - a_uint32_t port_num:4; - a_uint32_t dir:1; - a_uint32_t valid:1; - a_uint32_t _reserved0:26; -}; - -union tdm_cfg_u { - a_uint32_t val; - struct tdm_cfg bf; -}; - -/*[table] DROP_STAT*/ -#define DROP_STAT -#define DROP_STAT_ADDRESS 0x3000 -#define DROP_STAT_NUM 30 -#define DROP_STAT_INC 0x10 -#define DROP_STAT_TYPE REG_TYPE_RW -#define DROP_STAT_DEFAULT 0x0 - /*[field] PKTS*/ - #define DROP_STAT_PKTS - #define DROP_STAT_PKTS_OFFSET 0 - #define DROP_STAT_PKTS_LEN 32 - #define DROP_STAT_PKTS_DEFAULT 0x0 - /*[field] BYTES*/ - #define DROP_STAT_BYTES - #define DROP_STAT_BYTES_OFFSET 32 - #define DROP_STAT_BYTES_LEN 40 - #define DROP_STAT_BYTES_DEFAULT 0x0 - -struct drop_stat { - a_uint32_t pkts:32; - a_uint32_t bytes_0:32; - a_uint32_t bytes_1:8; - a_uint32_t _reserved0:24; -}; - -union drop_stat_u { - a_uint32_t val[3]; - struct drop_stat bf; -}; - -/*[register] PORT_TX_COUNTER_TBL_REG*/ -#define PORT_TX_COUNTER_TBL_REG -#define PORT_TX_COUNTER_TBL_REG_ADDRESS 0x900 -#define PORT_TX_COUNTER_TBL_REG_NUM 8 -#define PORT_TX_COUNTER_TBL_REG_INC 0x10 -#define PORT_TX_COUNTER_TBL_REG_TYPE REG_TYPE_RW -#define PORT_TX_COUNTER_TBL_REG_DEFAULT 0x0 - /*[field] TX_PACKETS*/ - #define PORT_TX_COUNTER_TBL_REG_TX_PACKETS - #define PORT_TX_COUNTER_TBL_REG_TX_PACKETS_OFFSET 0 - #define PORT_TX_COUNTER_TBL_REG_TX_PACKETS_LEN 32 - #define PORT_TX_COUNTER_TBL_REG_TX_PACKETS_DEFAULT 0x0 - /*[field] TX_BYTES*/ - #define PORT_TX_COUNTER_TBL_REG_TX_BYTES - #define PORT_TX_COUNTER_TBL_REG_TX_BYTES_OFFSET 32 - #define PORT_TX_COUNTER_TBL_REG_TX_BYTES_LEN 40 - #define PORT_TX_COUNTER_TBL_REG_TX_BYTES_DEFAULT 0x0 - -struct port_tx_counter_tbl_reg { - a_uint32_t tx_packets:32; - a_uint32_t tx_bytes_0:32; - a_uint32_t tx_bytes_1:8; - a_uint32_t _reserved0:24; -}; - -union port_tx_counter_tbl_reg_u { - a_uint32_t val[3]; - struct port_tx_counter_tbl_reg bf; -}; - -/*[register] VP_TX_COUNTER_TBL_REG*/ -#define VP_TX_COUNTER_TBL_REG -#define VP_TX_COUNTER_TBL_REG_ADDRESS 0x1000 -#define VP_TX_COUNTER_TBL_REG_NUM 256 -#define VP_TX_COUNTER_TBL_REG_INC 0x10 -#define VP_TX_COUNTER_TBL_REG_TYPE REG_TYPE_RW -#define VP_TX_COUNTER_TBL_REG_DEFAULT 0x0 - /*[field] TX_PACKETS*/ - #define VP_TX_COUNTER_TBL_REG_TX_PACKETS - #define VP_TX_COUNTER_TBL_REG_TX_PACKETS_OFFSET 0 - #define VP_TX_COUNTER_TBL_REG_TX_PACKETS_LEN 32 - #define VP_TX_COUNTER_TBL_REG_TX_PACKETS_DEFAULT 0x0 - /*[field] TX_BYTES*/ - #define VP_TX_COUNTER_TBL_REG_TX_BYTES - #define VP_TX_COUNTER_TBL_REG_TX_BYTES_OFFSET 32 - #define VP_TX_COUNTER_TBL_REG_TX_BYTES_LEN 40 - #define VP_TX_COUNTER_TBL_REG_TX_BYTES_DEFAULT 0x0 - -struct vp_tx_counter_tbl_reg { - a_uint32_t tx_packets:32; - a_uint32_t tx_bytes_0:32; - a_uint32_t tx_bytes_1:8; - a_uint32_t _reserved0:24; -}; - -union vp_tx_counter_tbl_reg_u { - a_uint32_t val[3]; - struct vp_tx_counter_tbl_reg bf; -}; - -/*[register] EPE_DBG_IN_CNT_REG*/ -#define EPE_DBG_IN_CNT_REG -#define EPE_DBG_IN_CNT_REG_ADDRESS 0x6054 -#define EPE_DBG_IN_CNT_REG_NUM 1 -#define EPE_DBG_IN_CNT_REG_INC 0x4 -#define EPE_DBG_IN_CNT_REG_TYPE REG_TYPE_RW -#define EPE_DBG_IN_CNT_REG_DEFAULT 0x0 - /*[field] COUNTER*/ - #define EPE_DBG_IN_CNT_REG_COUNTER - #define EPE_DBG_IN_CNT_REG_COUNTER_OFFSET 0 - #define EPE_DBG_IN_CNT_REG_COUNTER_LEN 32 - #define EPE_DBG_IN_CNT_REG_COUNTER_DEFAULT 0x0 - -struct epe_dbg_in_cnt_reg { - a_uint32_t counter:32; -}; - -union epe_dbg_in_cnt_reg_u { - a_uint32_t val; - struct epe_dbg_in_cnt_reg bf; -}; - -/*[register] EPE_DBG_OUT_CNT_REG*/ -#define EPE_DBG_OUT_CNT_REG -#define EPE_DBG_OUT_CNT_REG_ADDRESS 0x6070 -#define EPE_DBG_OUT_CNT_REG_NUM 1 -#define EPE_DBG_OUT_CNT_REG_INC 0x4 -#define EPE_DBG_OUT_CNT_REG_TYPE REG_TYPE_RW -#define EPE_DBG_OUT_CNT_REG_DEFAULT 0x0 - /*[field] COUNTER*/ - #define EPE_DBG_OUT_CNT_REG_COUNTER - #define EPE_DBG_OUT_CNT_REG_COUNTER_OFFSET 0 - #define EPE_DBG_OUT_CNT_REG_COUNTER_LEN 32 - #define EPE_DBG_OUT_CNT_REG_COUNTER_DEFAULT 0x0 - -struct epe_dbg_out_cnt_reg { - a_uint32_t counter:32; -}; - -union epe_dbg_out_cnt_reg_u { - a_uint32_t val; - struct epe_dbg_out_cnt_reg bf; -}; - -/*[register] LPI_ENABLE*/ -#define LPI_ENABLE -#define LPI_ENABLE_ADDRESS 0x0 -#define LPI_ENABLE_NUM 1 -#define LPI_ENABLE_INC 0x0 -#define LPI_ENABLE_TYPE REG_TYPE_RW -#define LPI_ENABLE_DEFAULT 0x0 - /*[field] LPI_PORT1_EN*/ - #define LPI_PORT1_EN - #define LPI_PORT1_EN_OFFSET 0 - #define LPI_PORT1_EN_LEN 1 - #define LPI_PORT1_EN_DEFAULT 0x0 - /*[field] LPI_PORT2_EN*/ - #define LPI_PORT2_EN - #define LPI_PORT2_EN_OFFSET 1 - #define LPI_PORT2_EN_LEN 1 - #define LPI_PORT2_EN_DEFAULT 0x0 - /*[field] LPI_PORT3_EN*/ - #define LPI_PORT3_EN - #define LPI_PORT3_EN_OFFSET 2 - #define LPI_PORT3_EN_LEN 1 - #define LPI_PORT3_EN_DEFAULT 0x0 - /*[field] LPI_PORT4_EN*/ - #define LPI_PORT4_EN - #define LPI_PORT4_EN_OFFSET 3 - #define LPI_PORT4_EN_LEN 1 - #define LPI_PORT4_EN_DEFAULT 0x0 - /*[field] LPI_PORT5_EN*/ - #define LPI_PORT5_EN - #define LPI_PORT5_EN_OFFSET 4 - #define LPI_PORT5_EN_LEN 1 - #define LPI_PORT5_EN_DEFAULT 0x0 - /*[field] LPI_LPI_PORT6_EN*/ - #define LPI_PORT6_EN - #define LPI_PORT6_EN_OFFSET 5 - #define LPI_PORT6_EN_LEN 1 - #define LPI_LPI_PORT6_EN_DEFAULT 0x0 -struct lpi_enable { - a_uint32_t lpi_port1_en:1; - a_uint32_t lpi_port2_en:1; - a_uint32_t lpi_port3_en:1; - a_uint32_t lpi_port4_en:1; - a_uint32_t lpi_port5_en:1; - a_uint32_t lpi_port6_en:1; - a_uint32_t _reserved0:26; -}; - -union lpi_enable_u { - a_uint32_t val; - struct lpi_enable bf; -}; - -/*[register] LPI_PORT_TIMER*/ -#define LPI_PORT_TIMER_ENABLE -#define LPI_PORT_TIMER_ADDRESS 0x0 -#define LPI_PORT_TIMER_NUM 6 -#define LPI_PORT_TIMER_INC 0x4 -#define LPI_PORT_TIMER_TYPE REG_TYPE_RW -#define LPI_PORT_TIMER_DEFAULT 0x0 - /*[field] LPI_PORT_WAKEUP_TIMER*/ - #define LPI_PORT_WAKEUP_TIMER - #define LPI_PORT_WAKEUP_TIMER_OFFSET 0 - #define LPI_PORT_WAKEUP_TIMER_LEN 16 - #define LPI_PORT_WAKEUP_TIMER_DEFAULT 0x0 - /*[field] LPI_PORT_SLEEP_TIMER*/ - #define LPI_PORT_SLEEP_TIMER - #define LPI_PORT_SLEEP_TIMER_OFFSET 16 - #define LPI_PORT_SLEEP_TIMER_LEN 16 - #define LPI_PORT_SLEEP_TIMER_DEFAULT 0x0 - -struct lpi_port_timer { - a_uint32_t lpi_port_wakeup_timer:16; - a_uint32_t lpi_port_sleep_timer:16; -}; - -union lpi_port_timer_u { - a_uint32_t val; - struct lpi_port_timer bf; -}; - -/*[register] LPI_DBG_ADDR*/ -#define LPI_DBG_ADDR -#define LPI_DBG_ADDR_ADDRESS 0x1C -#define LPI_DBG_ADDR_NUM 1 -#define LPI_DBG_ADDR_INC 0x1 -#define LPI_DBG_ADDR_TYPE REG_TYPE_RW -#define LPI_DBG_ADDR_DEFAULT 0x0 - /*[field] LPI_DBG_ADDR*/ - #define LPI_DBG_ADDR - #define IIP_DBG_ADDR_OFFSET 0 - #define LPI_DBG_ADDR_LEN 8 - #define LPI_DBG_ADDR_DEFAULT 0x0 - -struct lpi_dbg_addr { - a_uint32_t lpi_debug_addr:8; - a_uint32_t _reserved0:24; -}; - -union lpi_dbg_addr_u { - a_uint32_t val; - struct lpi_dbg_addr bf; -}; - -/*[register] LPI_DBG_DATA*/ -#define LPI_DBG_DATA -#define LPI_DBG_DATA_ADDRESS 0x20 -#define LPI_DBG_DATA_NUM 1 -#define LPI_DBG_DATA_INC 0x1 -#define LPI_DBG_DATA_TYPE REG_TYPE_RW -#define LPI_DBG_DATA_DEFAULT 0x0 - /*[field] LPI_DBG_DATA*/ - #define LPI_DBG_DATA - #define LPI_DBG_DATA_OFFSET 0 - #define LPI_DBG_DATA_LEN 32 - #define LPI_DBG_DATA_DEFAULT 0x0 - -struct lpi_dbg_data { - a_uint32_t lpi_debug_data:8; - a_uint32_t _reserved0:24; -}; - -union lpi_dbg_data_u { - a_uint32_t val; - struct lpi_dbg_data bf; -}; - -/*[register] LPI_CNT*/ -#define LPI_CNT -#define LPI_CNT_ADDRESS 0x30 -#define LPI_CNT_NUM 1 -#define LPI_CNT_INC 0x1 -#define LPI_CNT_TYPE REG_TYPE_RW -#define LPI_CNT_DEFAULT 0x0 - /*[field] LPI_CNT*/ - #define LPI_CNT - #define LPI_CNT_OFFSET 0 - #define LPI_CNT_LEN 9 - #define LPI_CNT_DEFAULT 0x0 - -struct lpi_cnt { - a_uint32_t lpi_cnt_val:9; - a_uint32_t _reserved0:23; -}; - -union lpi_cnt_u { - a_uint32_t val; - struct lpi_cnt bf; -}; - -/*[register] DROP_CNT*/ -#define DROP_CNT -#define DROP_CNT_ADDRESS 0x24 -#define DROP_CNT_NUM 8 -#define DROP_CNT_INC 0x4 -#define DROP_CNT_TYPE REG_TYPE_RW -#define DROP_CNT_DEFAULT 0x0 - /*[field] DROP_CNT*/ - #define DROP_CNT_DROP_CNT - #define DROP_CNT_DROP_CNT_OFFSET 0 - #define DROP_CNT_DROP_CNT_LEN 32 - #define DROP_CNT_DROP_CNT_DEFAULT 0x0 - -struct drop_cnt { - a_uint32_t drop_cnt:32; -}; - -union drop_cnt_u { - a_uint32_t val; - struct drop_cnt bf; -}; - -/*[register] IPR_PKT_NUM_TBL_REG*/ -#define IPR_PKT_NUM_TBL_REG -#define IPR_PKT_NUM_TBL_REG_ADDRESS 0x80 -#define IPR_PKT_NUM_TBL_REG_NUM 8 -#define IPR_PKT_NUM_TBL_REG_INC 0x4 -#define IPR_PKT_NUM_TBL_REG_TYPE REG_TYPE_RW -#define IPR_PKT_NUM_TBL_REG_DEFAULT 0x0 - /*[field] PACKETS*/ - #define IPR_PKT_NUM_TBL_REG_PACKETS - #define IPR_PKT_NUM_TBL_REG_PACKETS_OFFSET 0 - #define IPR_PKT_NUM_TBL_REG_PACKETS_LEN 32 - #define IPR_PKT_NUM_TBL_REG_PACKETS_DEFAULT 0x0 - -struct ipr_pkt_num_tbl_reg { - a_uint32_t packets:32; -}; - -union ipr_pkt_num_tbl_reg_u { - a_uint32_t val; - struct ipr_pkt_num_tbl_reg bf; -}; - -/*[register] IPR_BYTE_LOW_REG_REG*/ -#define IPR_BYTE_LOW_REG_REG -#define IPR_BYTE_LOW_REG_REG_ADDRESS 0xa0 -#define IPR_BYTE_LOW_REG_REG_NUM 8 -#define IPR_BYTE_LOW_REG_REG_INC 0x4 -#define IPR_BYTE_LOW_REG_REG_TYPE REG_TYPE_RW -#define IPR_BYTE_LOW_REG_REG_DEFAULT 0x0 - /*[field] BYTES*/ - #define IPR_BYTE_LOW_REG_REG_BYTES - #define IPR_BYTE_LOW_REG_REG_BYTES_OFFSET 0 - #define IPR_BYTE_LOW_REG_REG_BYTES_LEN 32 - #define IPR_BYTE_LOW_REG_REG_BYTES_DEFAULT 0x0 - -struct ipr_byte_low_reg_reg { - a_uint32_t bytes:32; -}; - -union ipr_byte_low_reg_reg_u { - a_uint32_t val; - struct ipr_byte_low_reg_reg bf; -}; - -/*[register] IPR_BYTE_HIGH_REG*/ -#define IPR_BYTE_HIGH_REG -#define IPR_BYTE_HIGH_REG_ADDRESS 0xc0 -#define IPR_BYTE_HIGH_REG_NUM 8 -#define IPR_BYTE_HIGH_REG_INC 0x4 -#define IPR_BYTE_HIGH_REG_TYPE REG_TYPE_RW -#define IPR_BYTE_HIGH_REG_DEFAULT 0x0 - /*[field] BYTES*/ - #define IPR_BYTE_HIGH_REG_BYTES - #define IPR_BYTE_HIGH_REG_BYTES_OFFSET 0 - #define IPR_BYTE_HIGH_REG_BYTES_LEN 32 - #define IPR_BYTE_HIGH_REG_BYTES_DEFAULT 0x0 - -struct ipr_byte_high_reg { - a_uint32_t bytes:32; -}; - -union ipr_byte_high_reg_u { - a_uint32_t val; - struct ipr_byte_high_reg bf; -}; - - -#endif diff --git a/feeds/ipq807x/qca-ssdk/src/include/hsl/hppe/hppe_portvlan.h b/feeds/ipq807x/qca-ssdk/src/include/hsl/hppe/hppe_portvlan.h deleted file mode 100755 index 2a4a77959..000000000 --- a/feeds/ipq807x/qca-ssdk/src/include/hsl/hppe/hppe_portvlan.h +++ /dev/null @@ -1,1627 +0,0 @@ -/* - * Copyright (c) 2016-2017, The Linux Foundation. All rights reserved. - * Permission to use, copy, modify, and/or distribute this software for - * any purpose with or without fee is hereby granted, provided that the - * above copyright notice and this permission notice appear in all copies. - * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES - * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR - * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES - * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN - * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT - * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. - */ - - -/** - * @defgroup - * @{ - */ -#ifndef _HPPE_PORTVLAN_H_ -#define _HPPE_PORTVLAN_H_ - -#include "hppe_portvlan_reg.h" - -#define XLT_RULE_TBL_MAX_ENTRY 64 -#define XLT_ACTION_TBL_MAX_ENTRY 64 -#define PORT_PARSING_REG_MAX_ENTRY 8 -#define EG_VLAN_XLT_RULE_MAX_ENTRY 64 -#define PORT_EG_DEF_VID_MAX_ENTRY 8 -#define PORT_EG_VLAN_MAX_ENTRY 8 -#define EG_VLAN_XLT_ACTION_MAX_ENTRY 64 - - -sw_error_t -hppe_port_parsing_reg_get( - a_uint32_t dev_id, - a_uint32_t index, - union port_parsing_reg_u *value); - -sw_error_t -hppe_port_parsing_reg_set( - a_uint32_t dev_id, - a_uint32_t index, - union port_parsing_reg_u *value); - -sw_error_t -hppe_edma_vlan_tpid_reg_get( - a_uint32_t dev_id, - union edma_vlan_tpid_reg_u *value); - -sw_error_t -hppe_edma_vlan_tpid_reg_set( - a_uint32_t dev_id, - union edma_vlan_tpid_reg_u *value); - -sw_error_t -hppe_vlan_tpid_reg_get( - a_uint32_t dev_id, - union vlan_tpid_reg_u *value); - -sw_error_t -hppe_vlan_tpid_reg_set( - a_uint32_t dev_id, - union vlan_tpid_reg_u *value); - -sw_error_t -hppe_port_parsing_reg_port_role_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_port_parsing_reg_port_role_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_vlan_tpid_reg_stag_tpid_get( - a_uint32_t dev_id, - unsigned int *value); - -sw_error_t -hppe_vlan_tpid_reg_stag_tpid_set( - a_uint32_t dev_id, - unsigned int value); - -sw_error_t -hppe_vlan_tpid_reg_ctag_tpid_get( - a_uint32_t dev_id, - unsigned int *value); - -sw_error_t -hppe_vlan_tpid_reg_ctag_tpid_set( - a_uint32_t dev_id, - unsigned int value); - -sw_error_t -hppe_bridge_config_get( - a_uint32_t dev_id, - union bridge_config_u *value); - -sw_error_t -hppe_bridge_config_set( - a_uint32_t dev_id, - union bridge_config_u *value); - -sw_error_t -hppe_port_def_vid_get( - a_uint32_t dev_id, - a_uint32_t port_id, - union port_def_vid_u *value); - -sw_error_t -hppe_port_def_vid_set( - a_uint32_t dev_id, - a_uint32_t port_id, - union port_def_vid_u *value); - -sw_error_t -hppe_port_def_pcp_get( - a_uint32_t dev_id, - a_uint32_t port_id, - union port_def_pcp_u *value); - -sw_error_t -hppe_port_def_pcp_set( - a_uint32_t dev_id, - a_uint32_t port_id, - union port_def_pcp_u *value); - -sw_error_t -hppe_port_vlan_config_get( - a_uint32_t dev_id, - a_uint32_t port_id, - union port_vlan_config_u *value); - -sw_error_t -hppe_port_vlan_config_set( - a_uint32_t dev_id, - a_uint32_t port_id, - union port_vlan_config_u *value); - -sw_error_t -hppe_iv_dbg_addr_get( - a_uint32_t dev_id, - union iv_dbg_addr_u *value); - -sw_error_t -hppe_iv_dbg_addr_set( - a_uint32_t dev_id, - union iv_dbg_addr_u *value); - -sw_error_t -hppe_iv_dbg_data_get( - a_uint32_t dev_id, - union iv_dbg_data_u *value); - -sw_error_t -hppe_iv_dbg_data_set( - a_uint32_t dev_id, - union iv_dbg_data_u *value); - -sw_error_t -hppe_eco_reserve_get( - a_uint32_t dev_id, - union eco_reserve_u *value); - -sw_error_t -hppe_eco_reserve_set( - a_uint32_t dev_id, - union eco_reserve_u *value); - -sw_error_t -hppe_xlt_rule_tbl_get( - a_uint32_t dev_id, - a_uint32_t index, - union xlt_rule_tbl_u *value); - -sw_error_t -hppe_xlt_rule_tbl_set( - a_uint32_t dev_id, - a_uint32_t index, - union xlt_rule_tbl_u *value); - -sw_error_t -hppe_xlt_action_tbl_get( - a_uint32_t dev_id, - a_uint32_t index, - union xlt_action_tbl_u *value); - -sw_error_t -hppe_xlt_action_tbl_set( - a_uint32_t dev_id, - a_uint32_t index, - union xlt_action_tbl_u *value); - -sw_error_t -hppe_bridge_config_bridge_type_get( - a_uint32_t dev_id, - unsigned int *value); - -sw_error_t -hppe_bridge_config_bridge_type_set( - a_uint32_t dev_id, - unsigned int value); - -sw_error_t -hppe_port_def_vid_port_def_cvid_en_get( - a_uint32_t dev_id, - a_uint32_t port_id, - unsigned int *value); - -sw_error_t -hppe_port_def_vid_port_def_cvid_en_set( - a_uint32_t dev_id, - a_uint32_t port_id, - unsigned int value); - -sw_error_t -hppe_port_def_vid_port_def_svid_en_get( - a_uint32_t dev_id, - a_uint32_t port_id, - unsigned int *value); - -sw_error_t -hppe_port_def_vid_port_def_svid_en_set( - a_uint32_t dev_id, - a_uint32_t port_id, - unsigned int value); - -sw_error_t -hppe_port_def_vid_port_def_cvid_get( - a_uint32_t dev_id, - a_uint32_t port_id, - unsigned int *value); - -sw_error_t -hppe_port_def_vid_port_def_cvid_set( - a_uint32_t dev_id, - a_uint32_t port_id, - unsigned int value); - -sw_error_t -hppe_port_def_vid_port_def_svid_get( - a_uint32_t dev_id, - a_uint32_t port_id, - unsigned int *value); - -sw_error_t -hppe_port_def_vid_port_def_svid_set( - a_uint32_t dev_id, - a_uint32_t port_id, - unsigned int value); - -sw_error_t -hppe_port_def_pcp_port_def_sdei_get( - a_uint32_t dev_id, - a_uint32_t port_id, - unsigned int *value); - -sw_error_t -hppe_port_def_pcp_port_def_sdei_set( - a_uint32_t dev_id, - a_uint32_t port_id, - unsigned int value); - -sw_error_t -hppe_port_def_pcp_port_def_spcp_get( - a_uint32_t dev_id, - a_uint32_t port_id, - unsigned int *value); - -sw_error_t -hppe_port_def_pcp_port_def_spcp_set( - a_uint32_t dev_id, - a_uint32_t port_id, - unsigned int value); - -sw_error_t -hppe_port_def_pcp_port_def_cdei_get( - a_uint32_t dev_id, - a_uint32_t port_id, - unsigned int *value); - -sw_error_t -hppe_port_def_pcp_port_def_cdei_set( - a_uint32_t dev_id, - a_uint32_t port_id, - unsigned int value); - -sw_error_t -hppe_port_def_pcp_port_def_cpcp_get( - a_uint32_t dev_id, - a_uint32_t port_id, - unsigned int *value); - -sw_error_t -hppe_port_def_pcp_port_def_cpcp_set( - a_uint32_t dev_id, - a_uint32_t port_id, - unsigned int value); - -sw_error_t -hppe_port_vlan_config_port_in_dei_prop_cmd_get( - a_uint32_t dev_id, - a_uint32_t port_id, - unsigned int *value); - -sw_error_t -hppe_port_vlan_config_port_in_dei_prop_cmd_set( - a_uint32_t dev_id, - a_uint32_t port_id, - unsigned int value); - -sw_error_t -hppe_port_vlan_config_port_in_pcp_prop_cmd_get( - a_uint32_t dev_id, - a_uint32_t port_id, - unsigned int *value); - -sw_error_t -hppe_port_vlan_config_port_in_pcp_prop_cmd_set( - a_uint32_t dev_id, - a_uint32_t port_id, - unsigned int value); - -sw_error_t -hppe_port_vlan_config_port_untag_fltr_cmd_get( - a_uint32_t dev_id, - a_uint32_t port_id, - unsigned int *value); - -sw_error_t -hppe_port_vlan_config_port_untag_fltr_cmd_set( - a_uint32_t dev_id, - a_uint32_t port_id, - unsigned int value); - -sw_error_t -hppe_port_vlan_config_port_in_vlan_fltr_cmd_get( - a_uint32_t dev_id, - a_uint32_t port_id, - unsigned int *value); - -sw_error_t -hppe_port_vlan_config_port_in_vlan_fltr_cmd_set( - a_uint32_t dev_id, - a_uint32_t port_id, - unsigned int value); - -sw_error_t -hppe_port_vlan_config_port_pri_tag_fltr_cmd_get( - a_uint32_t dev_id, - a_uint32_t port_id, - unsigned int *value); - -sw_error_t -hppe_port_vlan_config_port_pri_tag_fltr_cmd_set( - a_uint32_t dev_id, - a_uint32_t port_id, - unsigned int value); - -sw_error_t -hppe_port_vlan_config_port_vlan_xlt_miss_fwd_cmd_get( - a_uint32_t dev_id, - a_uint32_t port_id, - unsigned int *value); - -sw_error_t -hppe_port_vlan_config_port_vlan_xlt_miss_fwd_cmd_set( - a_uint32_t dev_id, - a_uint32_t port_id, - unsigned int value); - -sw_error_t -hppe_port_vlan_config_port_tag_fltr_cmd_get( - a_uint32_t dev_id, - a_uint32_t port_id, - unsigned int *value); - -sw_error_t -hppe_port_vlan_config_port_tag_fltr_cmd_set( - a_uint32_t dev_id, - a_uint32_t port_id, - unsigned int value); - -sw_error_t -hppe_iv_dbg_addr_dbg_addr_get( - a_uint32_t dev_id, - unsigned int *value); - -sw_error_t -hppe_iv_dbg_addr_dbg_addr_set( - a_uint32_t dev_id, - unsigned int value); - -sw_error_t -hppe_iv_dbg_data_dbg_data_get( - a_uint32_t dev_id, - unsigned int *value); - -sw_error_t -hppe_iv_dbg_data_dbg_data_set( - a_uint32_t dev_id, - unsigned int value); - -sw_error_t -hppe_eco_reserve_eco_res_get( - a_uint32_t dev_id, - unsigned int *value); - -sw_error_t -hppe_eco_reserve_eco_res_set( - a_uint32_t dev_id, - unsigned int value); - -sw_error_t -hppe_xlt_rule_tbl_ckey_vid_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_xlt_rule_tbl_ckey_vid_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_xlt_rule_tbl_frm_type_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_xlt_rule_tbl_frm_type_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_xlt_rule_tbl_prot_value_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_xlt_rule_tbl_prot_value_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_xlt_rule_tbl_valid_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_xlt_rule_tbl_valid_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_xlt_rule_tbl_frm_type_incl_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_xlt_rule_tbl_frm_type_incl_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_xlt_rule_tbl_ckey_dei_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_xlt_rule_tbl_ckey_dei_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_xlt_rule_tbl_skey_dei_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_xlt_rule_tbl_skey_dei_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_xlt_rule_tbl_skey_pcp_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_xlt_rule_tbl_skey_pcp_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_xlt_rule_tbl_ckey_pcp_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_xlt_rule_tbl_ckey_pcp_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_xlt_rule_tbl_ckey_vid_incl_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_xlt_rule_tbl_ckey_vid_incl_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_xlt_rule_tbl_ckey_dei_incl_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_xlt_rule_tbl_ckey_dei_incl_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_xlt_rule_tbl_port_bitmap_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_xlt_rule_tbl_port_bitmap_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_xlt_rule_tbl_prot_incl_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_xlt_rule_tbl_prot_incl_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_xlt_rule_tbl_skey_pcp_incl_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_xlt_rule_tbl_skey_pcp_incl_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_xlt_rule_tbl_ckey_fmt_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_xlt_rule_tbl_ckey_fmt_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_xlt_rule_tbl_skey_vid_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_xlt_rule_tbl_skey_vid_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_xlt_rule_tbl_skey_fmt_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_xlt_rule_tbl_skey_fmt_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_xlt_rule_tbl_ckey_pcp_incl_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_xlt_rule_tbl_ckey_pcp_incl_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_xlt_rule_tbl_skey_dei_incl_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_xlt_rule_tbl_skey_dei_incl_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_xlt_rule_tbl_skey_vid_incl_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_xlt_rule_tbl_skey_vid_incl_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_xlt_action_tbl_dei_swap_cmd_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_xlt_action_tbl_dei_swap_cmd_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_xlt_action_tbl_xlt_cvid_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_xlt_action_tbl_xlt_cvid_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_xlt_action_tbl_xlt_cpcp_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_xlt_action_tbl_xlt_cpcp_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_xlt_action_tbl_xlt_spcp_cmd_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_xlt_action_tbl_xlt_spcp_cmd_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_xlt_action_tbl_xlt_sdei_cmd_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_xlt_action_tbl_xlt_sdei_cmd_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_xlt_action_tbl_xlt_cvid_cmd_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_xlt_action_tbl_xlt_cvid_cmd_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_xlt_action_tbl_vsi_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_xlt_action_tbl_vsi_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_xlt_action_tbl_xlt_spcp_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_xlt_action_tbl_xlt_spcp_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_xlt_action_tbl_counter_id_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_xlt_action_tbl_counter_id_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_xlt_action_tbl_vid_swap_cmd_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_xlt_action_tbl_vid_swap_cmd_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_xlt_action_tbl_xlt_sdei_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_xlt_action_tbl_xlt_sdei_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_xlt_action_tbl_counter_en_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_xlt_action_tbl_counter_en_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_xlt_action_tbl_xlt_svid_cmd_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_xlt_action_tbl_xlt_svid_cmd_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_xlt_action_tbl_xlt_svid_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_xlt_action_tbl_xlt_svid_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_xlt_action_tbl_vsi_cmd_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_xlt_action_tbl_vsi_cmd_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_xlt_action_tbl_xlt_cpcp_cmd_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_xlt_action_tbl_xlt_cpcp_cmd_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_xlt_action_tbl_xlt_cdei_cmd_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_xlt_action_tbl_xlt_cdei_cmd_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_xlt_action_tbl_pcp_swap_cmd_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_xlt_action_tbl_pcp_swap_cmd_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_xlt_action_tbl_xlt_cdei_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_xlt_action_tbl_xlt_cdei_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_eg_vlan_xlt_rule_get( - a_uint32_t dev_id, - a_uint32_t index, - union eg_vlan_xlt_rule_u *value); - -sw_error_t -hppe_eg_vlan_xlt_rule_set( - a_uint32_t dev_id, - a_uint32_t index, - union eg_vlan_xlt_rule_u *value); - -sw_error_t -hppe_eg_vsi_tag_get( - a_uint32_t dev_id, - a_uint32_t index, - union eg_vsi_tag_u *value); - -sw_error_t -hppe_eg_vsi_tag_set( - a_uint32_t dev_id, - a_uint32_t index, - union eg_vsi_tag_u *value); - -sw_error_t -hppe_port_eg_def_vid_get( - a_uint32_t dev_id, - a_uint32_t index, - union port_eg_def_vid_u *value); - -sw_error_t -hppe_port_eg_def_vid_set( - a_uint32_t dev_id, - a_uint32_t index, - union port_eg_def_vid_u *value); - -sw_error_t -hppe_port_eg_vlan_get( - a_uint32_t dev_id, - a_uint32_t index, - union port_eg_vlan_u *value); - -sw_error_t -hppe_port_eg_vlan_set( - a_uint32_t dev_id, - a_uint32_t index, - union port_eg_vlan_u *value); - -sw_error_t -hppe_eg_vlan_tpid_get( - a_uint32_t dev_id, - union eg_vlan_tpid_u *value); - -sw_error_t -hppe_eg_vlan_tpid_set( - a_uint32_t dev_id, - union eg_vlan_tpid_u *value); - -sw_error_t -hppe_eg_bridge_config_get( - a_uint32_t dev_id, - union eg_bridge_config_u *value); - -sw_error_t -hppe_eg_bridge_config_set( - a_uint32_t dev_id, - union eg_bridge_config_u *value); - -sw_error_t -hppe_eg_vlan_xlt_action_get( - a_uint32_t dev_id, - a_uint32_t index, - union eg_vlan_xlt_action_u *value); - -sw_error_t -hppe_eg_vlan_xlt_action_set( - a_uint32_t dev_id, - a_uint32_t index, - union eg_vlan_xlt_action_u *value); - -sw_error_t -hppe_eg_vlan_xlt_rule_ckey_vid_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_eg_vlan_xlt_rule_ckey_vid_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_eg_vlan_xlt_rule_valid_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_eg_vlan_xlt_rule_valid_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_eg_vlan_xlt_rule_ckey_dei_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_eg_vlan_xlt_rule_ckey_dei_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_eg_vlan_xlt_rule_skey_dei_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_eg_vlan_xlt_rule_skey_dei_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_eg_vlan_xlt_rule_skey_pcp_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_eg_vlan_xlt_rule_skey_pcp_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_eg_vlan_xlt_rule_ckey_pcp_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_eg_vlan_xlt_rule_ckey_pcp_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_eg_vlan_xlt_rule_vsi_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_eg_vlan_xlt_rule_vsi_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_eg_vlan_xlt_rule_ckey_vid_incl_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_eg_vlan_xlt_rule_ckey_vid_incl_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_eg_vlan_xlt_rule_ckey_dei_incl_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_eg_vlan_xlt_rule_ckey_dei_incl_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_eg_vlan_xlt_rule_vsi_incl_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_eg_vlan_xlt_rule_vsi_incl_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_eg_vlan_xlt_rule_port_bitmap_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_eg_vlan_xlt_rule_port_bitmap_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_eg_vlan_xlt_rule_skey_pcp_incl_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_eg_vlan_xlt_rule_skey_pcp_incl_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_eg_vlan_xlt_rule_ckey_fmt_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_eg_vlan_xlt_rule_ckey_fmt_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_eg_vlan_xlt_rule_skey_vid_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_eg_vlan_xlt_rule_skey_vid_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_eg_vlan_xlt_rule_skey_fmt_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_eg_vlan_xlt_rule_skey_fmt_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_eg_vlan_xlt_rule_ckey_pcp_incl_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_eg_vlan_xlt_rule_ckey_pcp_incl_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_eg_vlan_xlt_rule_skey_vid_incl_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_eg_vlan_xlt_rule_skey_vid_incl_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_eg_vlan_xlt_rule_skey_dei_incl_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_eg_vlan_xlt_rule_skey_dei_incl_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_eg_vlan_xlt_rule_vsi_valid_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_eg_vlan_xlt_rule_vsi_valid_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_eg_vsi_tag_tagged_mode_port_bitmap_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_eg_vsi_tag_tagged_mode_port_bitmap_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_port_eg_def_vid_port_def_svid_en_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_port_eg_def_vid_port_def_svid_en_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_port_eg_def_vid_port_def_svid_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_port_eg_def_vid_port_def_svid_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_port_eg_def_vid_port_def_cvid_en_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_port_eg_def_vid_port_def_cvid_en_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_port_eg_def_vid_port_def_cvid_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_port_eg_def_vid_port_def_cvid_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_port_eg_vlan_tx_counting_en_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_port_eg_vlan_tx_counting_en_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_port_eg_vlan_port_eg_vlan_ctag_mode_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_port_eg_vlan_port_eg_vlan_ctag_mode_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_port_eg_vlan_port_eg_pcp_prop_cmd_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_port_eg_vlan_port_eg_pcp_prop_cmd_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_port_eg_vlan_vsi_tag_mode_en_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_port_eg_vlan_vsi_tag_mode_en_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_port_eg_vlan_port_eg_vlan_stag_mode_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_port_eg_vlan_port_eg_vlan_stag_mode_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_port_eg_vlan_port_eg_dei_prop_cmd_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_port_eg_vlan_port_eg_dei_prop_cmd_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_port_eg_vlan_port_vlan_type_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_port_eg_vlan_port_vlan_type_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_eg_vlan_tpid_ctpid_get( - a_uint32_t dev_id, - unsigned int *value); - -sw_error_t -hppe_eg_vlan_tpid_ctpid_set( - a_uint32_t dev_id, - unsigned int value); - -sw_error_t -hppe_eg_vlan_tpid_stpid_get( - a_uint32_t dev_id, - unsigned int *value); - -sw_error_t -hppe_eg_vlan_tpid_stpid_set( - a_uint32_t dev_id, - unsigned int value); - -sw_error_t -hppe_eg_bridge_config_bridge_type_get( - a_uint32_t dev_id, - unsigned int *value); - -sw_error_t -hppe_eg_bridge_config_bridge_type_set( - a_uint32_t dev_id, - unsigned int value); - -sw_error_t -hppe_eg_bridge_config_pkt_l2_edit_en_get( - a_uint32_t dev_id, - a_uint32_t *value); -sw_error_t -hppe_eg_bridge_config_pkt_l2_edit_en_set( - a_uint32_t dev_id, - a_uint32_t value); -sw_error_t -hppe_eg_bridge_config_queue_cnt_en_get( - a_uint32_t dev_id, - unsigned int *value); - -sw_error_t -hppe_eg_bridge_config_queue_cnt_en_set( - a_uint32_t dev_id, - unsigned int value); - -sw_error_t -hppe_eg_vlan_xlt_action_dei_swap_cmd_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_eg_vlan_xlt_action_dei_swap_cmd_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_eg_vlan_xlt_action_xlt_cvid_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_eg_vlan_xlt_action_xlt_cvid_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_eg_vlan_xlt_action_xlt_cpcp_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_eg_vlan_xlt_action_xlt_cpcp_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_eg_vlan_xlt_action_xlt_spcp_cmd_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_eg_vlan_xlt_action_xlt_spcp_cmd_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_eg_vlan_xlt_action_xlt_sdei_cmd_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_eg_vlan_xlt_action_xlt_sdei_cmd_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_eg_vlan_xlt_action_xlt_cvid_cmd_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_eg_vlan_xlt_action_xlt_cvid_cmd_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_eg_vlan_xlt_action_xlt_spcp_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_eg_vlan_xlt_action_xlt_spcp_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_eg_vlan_xlt_action_counter_id_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_eg_vlan_xlt_action_counter_id_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_eg_vlan_xlt_action_vid_swap_cmd_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_eg_vlan_xlt_action_vid_swap_cmd_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_eg_vlan_xlt_action_xlt_sdei_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_eg_vlan_xlt_action_xlt_sdei_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_eg_vlan_xlt_action_counter_en_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_eg_vlan_xlt_action_counter_en_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_eg_vlan_xlt_action_xlt_svid_cmd_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_eg_vlan_xlt_action_xlt_svid_cmd_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_eg_vlan_xlt_action_xlt_svid_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_eg_vlan_xlt_action_xlt_svid_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_eg_vlan_xlt_action_xlt_cpcp_cmd_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_eg_vlan_xlt_action_xlt_cpcp_cmd_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_eg_vlan_xlt_action_xlt_cdei_cmd_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_eg_vlan_xlt_action_xlt_cdei_cmd_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_eg_vlan_xlt_action_pcp_swap_cmd_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_eg_vlan_xlt_action_pcp_swap_cmd_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_eg_vlan_xlt_action_xlt_cdei_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_eg_vlan_xlt_action_xlt_cdei_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_vlan_dev_tx_counter_tbl_get( - a_uint32_t dev_id, - a_uint32_t index, - union vlan_dev_tx_counter_tbl_u *value); - -sw_error_t -hppe_vlan_dev_tx_counter_tbl_set( - a_uint32_t dev_id, - a_uint32_t index, - union vlan_dev_tx_counter_tbl_u *value); - -sw_error_t -hppe_vlan_dev_tx_counter_tbl_tx_byte_cnt_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint64_t *value); - -sw_error_t -hppe_vlan_dev_tx_counter_tbl_tx_byte_cnt_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint64_t value); - -sw_error_t -hppe_vlan_dev_tx_counter_tbl_tx_pkt_cnt_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_vlan_dev_tx_counter_tbl_tx_pkt_cnt_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -#endif - diff --git a/feeds/ipq807x/qca-ssdk/src/include/hsl/hppe/hppe_portvlan_reg.h b/feeds/ipq807x/qca-ssdk/src/include/hsl/hppe/hppe_portvlan_reg.h deleted file mode 100755 index 1a79643bb..000000000 --- a/feeds/ipq807x/qca-ssdk/src/include/hsl/hppe/hppe_portvlan_reg.h +++ /dev/null @@ -1,1073 +0,0 @@ -/* - * Copyright (c) 2016-2017, The Linux Foundation. All rights reserved. - * Permission to use, copy, modify, and/or distribute this software for - * any purpose with or without fee is hereby granted, provided that the - * above copyright notice and this permission notice appear in all copies. - * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES - * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR - * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES - * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN - * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT - * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. - */ - - -/** - * @defgroup - * @{ - */ -#ifndef HPPE_PORTVLAN_REG_H -#define HPPE_PORTVLAN_REG_H - -/*[register] PORT_PARSING_REG*/ -#define PORT_PARSING_REG -#define PORT_PARSING_REG_ADDRESS 0x0 -#define PORT_PARSING_REG_NUM 8 -#define PORT_PARSING_REG_INC 0x4 -#define PORT_PARSING_REG_TYPE REG_TYPE_RW -#define PORT_PARSING_REG_DEFAULT 0x0 - /*[field] PORT_ROLE*/ - #define PORT_PARSING_REG_PORT_ROLE - #define PORT_PARSING_REG_PORT_ROLE_OFFSET 0 - #define PORT_PARSING_REG_PORT_ROLE_LEN 1 - #define PORT_PARSING_REG_PORT_ROLE_DEFAULT 0x0 - -struct port_parsing_reg { - a_uint32_t port_role:1; - a_uint32_t _reserved0:31; -}; - -union port_parsing_reg_u { - a_uint32_t val; - struct port_parsing_reg bf; -}; - -/*[register] EDMA_VLAN_TPID_REG*/ -#define EDMA_VLAN_TPID_REG -#define EDMA_VLAN_TPID_REG_ADDRESS 0x8 -#define EDMA_VLAN_TPID_REG_NUM 1 -#define EDMA_VLAN_TPID_REG_INC 0x4 -#define EDMA_VLAN_TPID_REG_TYPE REG_TYPE_RW -#define EDMA_VLAN_TPID_REG_DEFAULT 0x810088a8 - /*[field] STAG_TPID*/ - #define EDMA_VLAN_TPID_REG_STAG_TPID - #define EDMA_VLAN_TPID_REG_STAG_TPID_OFFSET 0 - #define EDMA_VLAN_TPID_REG_STAG_TPID_LEN 16 - #define EDMA_VLAN_TPID_REG_STAG_TPID_DEFAULT 0x88a8 - /*[field] CTAG_TPID*/ - #define EDMA_VLAN_TPID_REG_CTAG_TPID - #define EDMA_VLAN_TPID_REG_CTAG_TPID_OFFSET 16 - #define EDMA_VLAN_TPID_REG_CTAG_TPID_LEN 16 - #define EDMA_VLAN_TPID_REG_CTAG_TPID_DEFAULT 0x8100 - -struct edma_vlan_tpid_reg { - a_uint32_t stag_tpid:16; - a_uint32_t ctag_tpid:16; -}; - -union edma_vlan_tpid_reg_u { - a_uint32_t val; - struct edma_vlan_tpid_reg bf; -}; - -/*[register] VLAN_TPID_REG*/ -#define VLAN_TPID_REG -#define VLAN_TPID_REG_ADDRESS 0x20 -#define VLAN_TPID_REG_NUM 1 -#define VLAN_TPID_REG_INC 0x4 -#define VLAN_TPID_REG_TYPE REG_TYPE_RW -#define VLAN_TPID_REG_DEFAULT 0x88a88100 - /*[field] CTAG_TPID*/ - #define VLAN_TPID_REG_CTAG_TPID - #define VLAN_TPID_REG_CTAG_TPID_OFFSET 0 - #define VLAN_TPID_REG_CTAG_TPID_LEN 16 - #define VLAN_TPID_REG_CTAG_TPID_DEFAULT 0x8100 - /*[field] STAG_TPID*/ - #define VLAN_TPID_REG_STAG_TPID - #define VLAN_TPID_REG_STAG_TPID_OFFSET 16 - #define VLAN_TPID_REG_STAG_TPID_LEN 16 - #define VLAN_TPID_REG_STAG_TPID_DEFAULT 0x88a8 - -struct vlan_tpid_reg { - a_uint32_t ctag_tpid:16; - a_uint32_t stag_tpid:16; -}; - -union vlan_tpid_reg_u { - a_uint32_t val; - struct vlan_tpid_reg bf; -}; - -/*[register] BRIDGE_CONFIG*/ -#define BRIDGE_CONFIG -#define BRIDGE_CONFIG_ADDRESS 0x0 -#define BRIDGE_CONFIG_NUM 1 -#define BRIDGE_CONFIG_INC 0x4 -#define BRIDGE_CONFIG_TYPE REG_TYPE_RW -#define BRIDGE_CONFIG_DEFAULT 0x0 - /*[field] BRIDGE_TYPE*/ - #define BRIDGE_CONFIG_BRIDGE_TYPE - #define BRIDGE_CONFIG_BRIDGE_TYPE_OFFSET 0 - #define BRIDGE_CONFIG_BRIDGE_TYPE_LEN 1 - #define BRIDGE_CONFIG_BRIDGE_TYPE_DEFAULT 0x0 - -struct bridge_config { - a_uint32_t bridge_type:1; - a_uint32_t _reserved0:31; -}; - -union bridge_config_u { - a_uint32_t val; - struct bridge_config bf; -}; - -/*[register] PORT_DEF_VID*/ -#define PORT_DEF_VID -#define PORT_DEF_VID_ADDRESS 0x10 -#define PORT_DEF_VID_NUM 1 -#define PORT_DEF_VID_INC 0x4 -#define PORT_DEF_VID_TYPE REG_TYPE_RW -#define PORT_DEF_VID_DEFAULT 0x0 - /*[field] PORT_DEF_SVID*/ - #define PORT_DEF_VID_PORT_DEF_SVID - #define PORT_DEF_VID_PORT_DEF_SVID_OFFSET 0 - #define PORT_DEF_VID_PORT_DEF_SVID_LEN 12 - #define PORT_DEF_VID_PORT_DEF_SVID_DEFAULT 0x0 - /*[field] PORT_DEF_SVID_EN*/ - #define PORT_DEF_VID_PORT_DEF_SVID_EN - #define PORT_DEF_VID_PORT_DEF_SVID_EN_OFFSET 12 - #define PORT_DEF_VID_PORT_DEF_SVID_EN_LEN 1 - #define PORT_DEF_VID_PORT_DEF_SVID_EN_DEFAULT 0x0 - /*[field] PORT_DEF_CVID*/ - #define PORT_DEF_VID_PORT_DEF_CVID - #define PORT_DEF_VID_PORT_DEF_CVID_OFFSET 16 - #define PORT_DEF_VID_PORT_DEF_CVID_LEN 12 - #define PORT_DEF_VID_PORT_DEF_CVID_DEFAULT 0x0 - /*[field] PORT_DEF_CVID_EN*/ - #define PORT_DEF_VID_PORT_DEF_CVID_EN - #define PORT_DEF_VID_PORT_DEF_CVID_EN_OFFSET 28 - #define PORT_DEF_VID_PORT_DEF_CVID_EN_LEN 1 - #define PORT_DEF_VID_PORT_DEF_CVID_EN_DEFAULT 0x0 - -struct port_def_vid { - a_uint32_t port_def_svid:12; - a_uint32_t port_def_svid_en:1; - a_uint32_t _reserved0:3; - a_uint32_t port_def_cvid:12; - a_uint32_t port_def_cvid_en:1; - a_uint32_t _reserved1:3; -}; - -union port_def_vid_u { - a_uint32_t val; - struct port_def_vid bf; -}; - -/*[register] PORT_DEF_PCP*/ -#define PORT_DEF_PCP -#define PORT_DEF_PCP_ADDRESS 0x30 -#define PORT_DEF_PCP_NUM 1 -#define PORT_DEF_PCP_INC 0x4 -#define PORT_DEF_PCP_TYPE REG_TYPE_RW -#define PORT_DEF_PCP_DEFAULT 0x0 - /*[field] PORT_DEF_SPCP*/ - #define PORT_DEF_PCP_PORT_DEF_SPCP - #define PORT_DEF_PCP_PORT_DEF_SPCP_OFFSET 0 - #define PORT_DEF_PCP_PORT_DEF_SPCP_LEN 3 - #define PORT_DEF_PCP_PORT_DEF_SPCP_DEFAULT 0x0 - /*[field] PORT_DEF_SDEI*/ - #define PORT_DEF_PCP_PORT_DEF_SDEI - #define PORT_DEF_PCP_PORT_DEF_SDEI_OFFSET 3 - #define PORT_DEF_PCP_PORT_DEF_SDEI_LEN 1 - #define PORT_DEF_PCP_PORT_DEF_SDEI_DEFAULT 0x0 - /*[field] PORT_DEF_CPCP*/ - #define PORT_DEF_PCP_PORT_DEF_CPCP - #define PORT_DEF_PCP_PORT_DEF_CPCP_OFFSET 4 - #define PORT_DEF_PCP_PORT_DEF_CPCP_LEN 3 - #define PORT_DEF_PCP_PORT_DEF_CPCP_DEFAULT 0x0 - /*[field] PORT_DEF_CDEI*/ - #define PORT_DEF_PCP_PORT_DEF_CDEI - #define PORT_DEF_PCP_PORT_DEF_CDEI_OFFSET 7 - #define PORT_DEF_PCP_PORT_DEF_CDEI_LEN 1 - #define PORT_DEF_PCP_PORT_DEF_CDEI_DEFAULT 0x0 - -struct port_def_pcp { - a_uint32_t port_def_spcp:3; - a_uint32_t port_def_sdei:1; - a_uint32_t port_def_cpcp:3; - a_uint32_t port_def_cdei:1; - a_uint32_t _reserved0:24; -}; - -union port_def_pcp_u { - a_uint32_t val; - struct port_def_pcp bf; -}; - -/*[register] PORT_VLAN_CONFIG*/ -#define PORT_VLAN_CONFIG -#define PORT_VLAN_CONFIG_ADDRESS 0x50 -#define PORT_VLAN_CONFIG_NUM 1 -#define PORT_VLAN_CONFIG_INC 0x4 -#define PORT_VLAN_CONFIG_TYPE REG_TYPE_RW -#define PORT_VLAN_CONFIG_DEFAULT 0x0 - /*[field] PORT_IN_PCP_PROP_CMD*/ - #define PORT_VLAN_CONFIG_PORT_IN_PCP_PROP_CMD - #define PORT_VLAN_CONFIG_PORT_IN_PCP_PROP_CMD_OFFSET 0 - #define PORT_VLAN_CONFIG_PORT_IN_PCP_PROP_CMD_LEN 1 - #define PORT_VLAN_CONFIG_PORT_IN_PCP_PROP_CMD_DEFAULT 0x0 - /*[field] PORT_IN_DEI_PROP_CMD*/ - #define PORT_VLAN_CONFIG_PORT_IN_DEI_PROP_CMD - #define PORT_VLAN_CONFIG_PORT_IN_DEI_PROP_CMD_OFFSET 1 - #define PORT_VLAN_CONFIG_PORT_IN_DEI_PROP_CMD_LEN 1 - #define PORT_VLAN_CONFIG_PORT_IN_DEI_PROP_CMD_DEFAULT 0x0 - /*[field] PORT_UNTAG_FLTR_CMD*/ - #define PORT_VLAN_CONFIG_PORT_UNTAG_FLTR_CMD - #define PORT_VLAN_CONFIG_PORT_UNTAG_FLTR_CMD_OFFSET 2 - #define PORT_VLAN_CONFIG_PORT_UNTAG_FLTR_CMD_LEN 1 - #define PORT_VLAN_CONFIG_PORT_UNTAG_FLTR_CMD_DEFAULT 0x0 - /*[field] PORT_PRI_TAG_FLTR_CMD*/ - #define PORT_VLAN_CONFIG_PORT_PRI_TAG_FLTR_CMD - #define PORT_VLAN_CONFIG_PORT_PRI_TAG_FLTR_CMD_OFFSET 3 - #define PORT_VLAN_CONFIG_PORT_PRI_TAG_FLTR_CMD_LEN 1 - #define PORT_VLAN_CONFIG_PORT_PRI_TAG_FLTR_CMD_DEFAULT 0x0 - /*[field] PORT_TAG_FLTR_CMD*/ - #define PORT_VLAN_CONFIG_PORT_TAG_FLTR_CMD - #define PORT_VLAN_CONFIG_PORT_TAG_FLTR_CMD_OFFSET 4 - #define PORT_VLAN_CONFIG_PORT_TAG_FLTR_CMD_LEN 1 - #define PORT_VLAN_CONFIG_PORT_TAG_FLTR_CMD_DEFAULT 0x0 - /*[field] PORT_VLAN_XLT_MISS_FWD_CMD*/ - #define PORT_VLAN_CONFIG_PORT_VLAN_XLT_MISS_FWD_CMD - #define PORT_VLAN_CONFIG_PORT_VLAN_XLT_MISS_FWD_CMD_OFFSET 5 - #define PORT_VLAN_CONFIG_PORT_VLAN_XLT_MISS_FWD_CMD_LEN 2 - #define PORT_VLAN_CONFIG_PORT_VLAN_XLT_MISS_FWD_CMD_DEFAULT 0x0 - /*[field] PORT_IN_VLAN_FLTR_CMD*/ - #define PORT_VLAN_CONFIG_PORT_IN_VLAN_FLTR_CMD - #define PORT_VLAN_CONFIG_PORT_IN_VLAN_FLTR_CMD_OFFSET 7 - #define PORT_VLAN_CONFIG_PORT_IN_VLAN_FLTR_CMD_LEN 1 - #define PORT_VLAN_CONFIG_PORT_IN_VLAN_FLTR_CMD_DEFAULT 0x0 - -struct port_vlan_config { - a_uint32_t port_in_pcp_prop_cmd:1; - a_uint32_t port_in_dei_prop_cmd:1; - a_uint32_t port_untag_fltr_cmd:1; - a_uint32_t port_pri_tag_fltr_cmd:1; - a_uint32_t port_tag_fltr_cmd:1; - a_uint32_t port_vlan_xlt_miss_fwd_cmd:2; - a_uint32_t port_in_vlan_fltr_cmd:1; - a_uint32_t _reserved0:24; -}; - -union port_vlan_config_u { - a_uint32_t val; - struct port_vlan_config bf; -}; - -/*[register] IV_DBG_ADDR*/ -#define IV_DBG_ADDR -#define IV_DBG_ADDR_ADDRESS 0x70 -#define IV_DBG_ADDR_NUM 1 -#define IV_DBG_ADDR_INC 0x4 -#define IV_DBG_ADDR_TYPE REG_TYPE_RW -#define IV_DBG_ADDR_DEFAULT 0x0 - /*[field] DBG_ADDR*/ - #define IV_DBG_ADDR_DBG_ADDR - #define IV_DBG_ADDR_DBG_ADDR_OFFSET 0 - #define IV_DBG_ADDR_DBG_ADDR_LEN 8 - #define IV_DBG_ADDR_DBG_ADDR_DEFAULT 0x0 - -struct iv_dbg_addr { - a_uint32_t dbg_addr:8; - a_uint32_t _reserved0:24; -}; - -union iv_dbg_addr_u { - a_uint32_t val; - struct iv_dbg_addr bf; -}; - -/*[register] IV_DBG_DATA*/ -#define IV_DBG_DATA -#define IV_DBG_DATA_ADDRESS 0x74 -#define IV_DBG_DATA_NUM 1 -#define IV_DBG_DATA_INC 0x4 -#define IV_DBG_DATA_TYPE REG_TYPE_RO -#define IV_DBG_DATA_DEFAULT 0x0 - /*[field] DBG_DATA*/ - #define IV_DBG_DATA_DBG_DATA - #define IV_DBG_DATA_DBG_DATA_OFFSET 0 - #define IV_DBG_DATA_DBG_DATA_LEN 32 - #define IV_DBG_DATA_DBG_DATA_DEFAULT 0x0 - -struct iv_dbg_data { - a_uint32_t dbg_data:32; -}; - -union iv_dbg_data_u { - a_uint32_t val; - struct iv_dbg_data bf; -}; - -/*[register] ECO_RESERVE*/ -#define ECO_RESERVE -#define ECO_RESERVE_ADDRESS 0x78 -#define ECO_RESERVE_NUM 1 -#define ECO_RESERVE_INC 0x4 -#define ECO_RESERVE_TYPE REG_TYPE_RW -#define ECO_RESERVE_DEFAULT 0x0 - /*[field] ECO_RES*/ - #define ECO_RESERVE_ECO_RES - #define ECO_RESERVE_ECO_RES_OFFSET 0 - #define ECO_RESERVE_ECO_RES_LEN 32 - #define ECO_RESERVE_ECO_RES_DEFAULT 0x0 - -struct eco_reserve { - a_uint32_t eco_res:32; -}; - -union eco_reserve_u { - a_uint32_t val; - struct eco_reserve bf; -}; - -/*[table] XLT_RULE_TBL*/ -#define XLT_RULE_TBL -#define XLT_RULE_TBL_ADDRESS 0x2000 -#define XLT_RULE_TBL_NUM 64 -#define XLT_RULE_TBL_INC 0x10 -#define XLT_RULE_TBL_TYPE REG_TYPE_RW -#define XLT_RULE_TBL_DEFAULT 0x0 - /*[field] VALID*/ - #define XLT_RULE_TBL_VALID - #define XLT_RULE_TBL_VALID_OFFSET 0 - #define XLT_RULE_TBL_VALID_LEN 1 - #define XLT_RULE_TBL_VALID_DEFAULT 0x0 - /*[field] PORT_BITMAP*/ - #define XLT_RULE_TBL_PORT_BITMAP - #define XLT_RULE_TBL_PORT_BITMAP_OFFSET 1 - #define XLT_RULE_TBL_PORT_BITMAP_LEN 8 - #define XLT_RULE_TBL_PORT_BITMAP_DEFAULT 0x0 - /*[field] SKEY_FMT*/ - #define XLT_RULE_TBL_SKEY_FMT - #define XLT_RULE_TBL_SKEY_FMT_OFFSET 9 - #define XLT_RULE_TBL_SKEY_FMT_LEN 3 - #define XLT_RULE_TBL_SKEY_FMT_DEFAULT 0x0 - /*[field] SKEY_VID_INCL*/ - #define XLT_RULE_TBL_SKEY_VID_INCL - #define XLT_RULE_TBL_SKEY_VID_INCL_OFFSET 12 - #define XLT_RULE_TBL_SKEY_VID_INCL_LEN 1 - #define XLT_RULE_TBL_SKEY_VID_INCL_DEFAULT 0x0 - /*[field] SKEY_VID*/ - #define XLT_RULE_TBL_SKEY_VID - #define XLT_RULE_TBL_SKEY_VID_OFFSET 13 - #define XLT_RULE_TBL_SKEY_VID_LEN 12 - #define XLT_RULE_TBL_SKEY_VID_DEFAULT 0x0 - /*[field] SKEY_PCP_INCL*/ - #define XLT_RULE_TBL_SKEY_PCP_INCL - #define XLT_RULE_TBL_SKEY_PCP_INCL_OFFSET 25 - #define XLT_RULE_TBL_SKEY_PCP_INCL_LEN 1 - #define XLT_RULE_TBL_SKEY_PCP_INCL_DEFAULT 0x0 - /*[field] SKEY_PCP*/ - #define XLT_RULE_TBL_SKEY_PCP - #define XLT_RULE_TBL_SKEY_PCP_OFFSET 26 - #define XLT_RULE_TBL_SKEY_PCP_LEN 3 - #define XLT_RULE_TBL_SKEY_PCP_DEFAULT 0x0 - /*[field] SKEY_DEI_INCL*/ - #define XLT_RULE_TBL_SKEY_DEI_INCL - #define XLT_RULE_TBL_SKEY_DEI_INCL_OFFSET 29 - #define XLT_RULE_TBL_SKEY_DEI_INCL_LEN 1 - #define XLT_RULE_TBL_SKEY_DEI_INCL_DEFAULT 0x0 - /*[field] SKEY_DEI*/ - #define XLT_RULE_TBL_SKEY_DEI - #define XLT_RULE_TBL_SKEY_DEI_OFFSET 30 - #define XLT_RULE_TBL_SKEY_DEI_LEN 1 - #define XLT_RULE_TBL_SKEY_DEI_DEFAULT 0x0 - /*[field] CKEY_FMT*/ - #define XLT_RULE_TBL_CKEY_FMT - #define XLT_RULE_TBL_CKEY_FMT_OFFSET 31 - #define XLT_RULE_TBL_CKEY_FMT_LEN 3 - #define XLT_RULE_TBL_CKEY_FMT_DEFAULT 0x0 - /*[field] CKEY_VID_INCL*/ - #define XLT_RULE_TBL_CKEY_VID_INCL - #define XLT_RULE_TBL_CKEY_VID_INCL_OFFSET 34 - #define XLT_RULE_TBL_CKEY_VID_INCL_LEN 1 - #define XLT_RULE_TBL_CKEY_VID_INCL_DEFAULT 0x0 - /*[field] CKEY_VID*/ - #define XLT_RULE_TBL_CKEY_VID - #define XLT_RULE_TBL_CKEY_VID_OFFSET 35 - #define XLT_RULE_TBL_CKEY_VID_LEN 12 - #define XLT_RULE_TBL_CKEY_VID_DEFAULT 0x0 - /*[field] CKEY_PCP_INCL*/ - #define XLT_RULE_TBL_CKEY_PCP_INCL - #define XLT_RULE_TBL_CKEY_PCP_INCL_OFFSET 47 - #define XLT_RULE_TBL_CKEY_PCP_INCL_LEN 1 - #define XLT_RULE_TBL_CKEY_PCP_INCL_DEFAULT 0x0 - /*[field] CKEY_PCP*/ - #define XLT_RULE_TBL_CKEY_PCP - #define XLT_RULE_TBL_CKEY_PCP_OFFSET 48 - #define XLT_RULE_TBL_CKEY_PCP_LEN 3 - #define XLT_RULE_TBL_CKEY_PCP_DEFAULT 0x0 - /*[field] CKEY_DEI_INCL*/ - #define XLT_RULE_TBL_CKEY_DEI_INCL - #define XLT_RULE_TBL_CKEY_DEI_INCL_OFFSET 51 - #define XLT_RULE_TBL_CKEY_DEI_INCL_LEN 1 - #define XLT_RULE_TBL_CKEY_DEI_INCL_DEFAULT 0x0 - /*[field] CKEY_DEI*/ - #define XLT_RULE_TBL_CKEY_DEI - #define XLT_RULE_TBL_CKEY_DEI_OFFSET 52 - #define XLT_RULE_TBL_CKEY_DEI_LEN 1 - #define XLT_RULE_TBL_CKEY_DEI_DEFAULT 0x0 - /*[field] FRM_TYPE_INCL*/ - #define XLT_RULE_TBL_FRM_TYPE_INCL - #define XLT_RULE_TBL_FRM_TYPE_INCL_OFFSET 53 - #define XLT_RULE_TBL_FRM_TYPE_INCL_LEN 1 - #define XLT_RULE_TBL_FRM_TYPE_INCL_DEFAULT 0x0 - /*[field] FRM_TYPE*/ - #define XLT_RULE_TBL_FRM_TYPE - #define XLT_RULE_TBL_FRM_TYPE_OFFSET 54 - #define XLT_RULE_TBL_FRM_TYPE_LEN 2 - #define XLT_RULE_TBL_FRM_TYPE_DEFAULT 0x0 - /*[field] PROT_INCL*/ - #define XLT_RULE_TBL_PROT_INCL - #define XLT_RULE_TBL_PROT_INCL_OFFSET 56 - #define XLT_RULE_TBL_PROT_INCL_LEN 1 - #define XLT_RULE_TBL_PROT_INCL_DEFAULT 0x0 - /*[field] PROT_VALUE*/ - #define XLT_RULE_TBL_PROT_VALUE - #define XLT_RULE_TBL_PROT_VALUE_OFFSET 57 - #define XLT_RULE_TBL_PROT_VALUE_LEN 16 - #define XLT_RULE_TBL_PROT_VALUE_DEFAULT 0x0 - -struct xlt_rule_tbl { - a_uint32_t valid:1; - a_uint32_t port_bitmap:8; - a_uint32_t skey_fmt:3; - a_uint32_t skey_vid_incl:1; - a_uint32_t skey_vid:12; - a_uint32_t skey_pcp_incl:1; - a_uint32_t skey_pcp:3; - a_uint32_t skey_dei_incl:1; - a_uint32_t skey_dei:1; - a_uint32_t ckey_fmt_0:1; - a_uint32_t ckey_fmt_1:2; - a_uint32_t ckey_vid_incl:1; - a_uint32_t ckey_vid:12; - a_uint32_t ckey_pcp_incl:1; - a_uint32_t ckey_pcp:3; - a_uint32_t ckey_dei_incl:1; - a_uint32_t ckey_dei:1; - a_uint32_t frm_type_incl:1; - a_uint32_t frm_type:2; - a_uint32_t prot_incl:1; - a_uint32_t prot_value_0:7; - a_uint32_t prot_value_1:9; - a_uint32_t _reserved0:23; -}; - -union xlt_rule_tbl_u { - a_uint32_t val[3]; - struct xlt_rule_tbl bf; -}; - -/*[table] XLT_ACTION_TBL*/ -#define XLT_ACTION_TBL -#define XLT_ACTION_TBL_ADDRESS 0x4000 -#define XLT_ACTION_TBL_NUM 64 -#define XLT_ACTION_TBL_INC 0x10 -#define XLT_ACTION_TBL_TYPE REG_TYPE_RW -#define XLT_ACTION_TBL_DEFAULT 0x0 - /*[field] VID_SWAP_CMD*/ - #define XLT_ACTION_TBL_VID_SWAP_CMD - #define XLT_ACTION_TBL_VID_SWAP_CMD_OFFSET 0 - #define XLT_ACTION_TBL_VID_SWAP_CMD_LEN 1 - #define XLT_ACTION_TBL_VID_SWAP_CMD_DEFAULT 0x0 - /*[field] XLT_SVID_CMD*/ - #define XLT_ACTION_TBL_XLT_SVID_CMD - #define XLT_ACTION_TBL_XLT_SVID_CMD_OFFSET 1 - #define XLT_ACTION_TBL_XLT_SVID_CMD_LEN 2 - #define XLT_ACTION_TBL_XLT_SVID_CMD_DEFAULT 0x0 - /*[field] XLT_SVID*/ - #define XLT_ACTION_TBL_XLT_SVID - #define XLT_ACTION_TBL_XLT_SVID_OFFSET 3 - #define XLT_ACTION_TBL_XLT_SVID_LEN 12 - #define XLT_ACTION_TBL_XLT_SVID_DEFAULT 0x0 - /*[field] XLT_CVID_CMD*/ - #define XLT_ACTION_TBL_XLT_CVID_CMD - #define XLT_ACTION_TBL_XLT_CVID_CMD_OFFSET 15 - #define XLT_ACTION_TBL_XLT_CVID_CMD_LEN 2 - #define XLT_ACTION_TBL_XLT_CVID_CMD_DEFAULT 0x0 - /*[field] XLT_CVID*/ - #define XLT_ACTION_TBL_XLT_CVID - #define XLT_ACTION_TBL_XLT_CVID_OFFSET 17 - #define XLT_ACTION_TBL_XLT_CVID_LEN 12 - #define XLT_ACTION_TBL_XLT_CVID_DEFAULT 0x0 - /*[field] PCP_SWAP_CMD*/ - #define XLT_ACTION_TBL_PCP_SWAP_CMD - #define XLT_ACTION_TBL_PCP_SWAP_CMD_OFFSET 29 - #define XLT_ACTION_TBL_PCP_SWAP_CMD_LEN 1 - #define XLT_ACTION_TBL_PCP_SWAP_CMD_DEFAULT 0x0 - /*[field] XLT_SPCP_CMD*/ - #define XLT_ACTION_TBL_XLT_SPCP_CMD - #define XLT_ACTION_TBL_XLT_SPCP_CMD_OFFSET 30 - #define XLT_ACTION_TBL_XLT_SPCP_CMD_LEN 1 - #define XLT_ACTION_TBL_XLT_SPCP_CMD_DEFAULT 0x0 - /*[field] XLT_SPCP*/ - #define XLT_ACTION_TBL_XLT_SPCP - #define XLT_ACTION_TBL_XLT_SPCP_OFFSET 31 - #define XLT_ACTION_TBL_XLT_SPCP_LEN 3 - #define XLT_ACTION_TBL_XLT_SPCP_DEFAULT 0x0 - /*[field] XLT_CPCP_CMD*/ - #define XLT_ACTION_TBL_XLT_CPCP_CMD - #define XLT_ACTION_TBL_XLT_CPCP_CMD_OFFSET 34 - #define XLT_ACTION_TBL_XLT_CPCP_CMD_LEN 1 - #define XLT_ACTION_TBL_XLT_CPCP_CMD_DEFAULT 0x0 - /*[field] XLT_CPCP*/ - #define XLT_ACTION_TBL_XLT_CPCP - #define XLT_ACTION_TBL_XLT_CPCP_OFFSET 35 - #define XLT_ACTION_TBL_XLT_CPCP_LEN 3 - #define XLT_ACTION_TBL_XLT_CPCP_DEFAULT 0x0 - /*[field] DEI_SWAP_CMD*/ - #define XLT_ACTION_TBL_DEI_SWAP_CMD - #define XLT_ACTION_TBL_DEI_SWAP_CMD_OFFSET 38 - #define XLT_ACTION_TBL_DEI_SWAP_CMD_LEN 1 - #define XLT_ACTION_TBL_DEI_SWAP_CMD_DEFAULT 0x0 - /*[field] XLT_SDEI_CMD*/ - #define XLT_ACTION_TBL_XLT_SDEI_CMD - #define XLT_ACTION_TBL_XLT_SDEI_CMD_OFFSET 39 - #define XLT_ACTION_TBL_XLT_SDEI_CMD_LEN 1 - #define XLT_ACTION_TBL_XLT_SDEI_CMD_DEFAULT 0x0 - /*[field] XLT_SDEI*/ - #define XLT_ACTION_TBL_XLT_SDEI - #define XLT_ACTION_TBL_XLT_SDEI_OFFSET 40 - #define XLT_ACTION_TBL_XLT_SDEI_LEN 1 - #define XLT_ACTION_TBL_XLT_SDEI_DEFAULT 0x0 - /*[field] XLT_CDEI_CMD*/ - #define XLT_ACTION_TBL_XLT_CDEI_CMD - #define XLT_ACTION_TBL_XLT_CDEI_CMD_OFFSET 41 - #define XLT_ACTION_TBL_XLT_CDEI_CMD_LEN 1 - #define XLT_ACTION_TBL_XLT_CDEI_CMD_DEFAULT 0x0 - /*[field] XLT_CDEI*/ - #define XLT_ACTION_TBL_XLT_CDEI - #define XLT_ACTION_TBL_XLT_CDEI_OFFSET 42 - #define XLT_ACTION_TBL_XLT_CDEI_LEN 1 - #define XLT_ACTION_TBL_XLT_CDEI_DEFAULT 0x0 - /*[field] VSI_CMD*/ - #define XLT_ACTION_TBL_VSI_CMD - #define XLT_ACTION_TBL_VSI_CMD_OFFSET 43 - #define XLT_ACTION_TBL_VSI_CMD_LEN 1 - #define XLT_ACTION_TBL_VSI_CMD_DEFAULT 0x0 - /*[field] VSI*/ - #define XLT_ACTION_TBL_VSI - #define XLT_ACTION_TBL_VSI_OFFSET 44 - #define XLT_ACTION_TBL_VSI_LEN 5 - #define XLT_ACTION_TBL_VSI_DEFAULT 0x0 - /*[field] COUNTER_EN*/ - #define XLT_ACTION_TBL_COUNTER_EN - #define XLT_ACTION_TBL_COUNTER_EN_OFFSET 49 - #define XLT_ACTION_TBL_COUNTER_EN_LEN 1 - #define XLT_ACTION_TBL_COUNTER_EN_DEFAULT 0x0 - /*[field] COUNTER_ID*/ - #define XLT_ACTION_TBL_COUNTER_ID - #define XLT_ACTION_TBL_COUNTER_ID_OFFSET 50 - #define XLT_ACTION_TBL_COUNTER_ID_LEN 6 - #define XLT_ACTION_TBL_COUNTER_ID_DEFAULT 0x0 - -struct xlt_action_tbl { - a_uint32_t vid_swap_cmd:1; - a_uint32_t xlt_svid_cmd:2; - a_uint32_t xlt_svid:12; - a_uint32_t xlt_cvid_cmd:2; - a_uint32_t xlt_cvid:12; - a_uint32_t pcp_swap_cmd:1; - a_uint32_t xlt_spcp_cmd:1; - a_uint32_t xlt_spcp_0:1; - a_uint32_t xlt_spcp_1:2; - a_uint32_t xlt_cpcp_cmd:1; - a_uint32_t xlt_cpcp:3; - a_uint32_t dei_swap_cmd:1; - a_uint32_t xlt_sdei_cmd:1; - a_uint32_t xlt_sdei:1; - a_uint32_t xlt_cdei_cmd:1; - a_uint32_t xlt_cdei:1; - a_uint32_t vsi_cmd:1; - a_uint32_t vsi:5; - a_uint32_t counter_en:1; - a_uint32_t counter_id:6; - a_uint32_t _reserved0:8; -}; - -union xlt_action_tbl_u { - a_uint32_t val[2]; - struct xlt_action_tbl bf; -}; - -/*[table] EG_VLAN_XLT_RULE*/ -#define EG_VLAN_XLT_RULE -#define EG_VLAN_XLT_RULE_ADDRESS 0x200 -#define EG_VLAN_XLT_RULE_NUM 64 -#define EG_VLAN_XLT_RULE_INC 0x8 -#define EG_VLAN_XLT_RULE_TYPE REG_TYPE_RW -#define EG_VLAN_XLT_RULE_DEFAULT 0x0 - /*[field] VALID*/ - #define EG_VLAN_XLT_RULE_VALID - #define EG_VLAN_XLT_RULE_VALID_OFFSET 0 - #define EG_VLAN_XLT_RULE_VALID_LEN 1 - #define EG_VLAN_XLT_RULE_VALID_DEFAULT 0x0 - /*[field] PORT_BITMAP*/ - #define EG_VLAN_XLT_RULE_PORT_BITMAP - #define EG_VLAN_XLT_RULE_PORT_BITMAP_OFFSET 1 - #define EG_VLAN_XLT_RULE_PORT_BITMAP_LEN 8 - #define EG_VLAN_XLT_RULE_PORT_BITMAP_DEFAULT 0x0 - /*[field] VSI_INCL*/ - #define EG_VLAN_XLT_RULE_VSI_INCL - #define EG_VLAN_XLT_RULE_VSI_INCL_OFFSET 9 - #define EG_VLAN_XLT_RULE_VSI_INCL_LEN 1 - #define EG_VLAN_XLT_RULE_VSI_INCL_DEFAULT 0x0 - /*[field] VSI*/ - #define EG_VLAN_XLT_RULE_VSI - #define EG_VLAN_XLT_RULE_VSI_OFFSET 10 - #define EG_VLAN_XLT_RULE_VSI_LEN 5 - #define EG_VLAN_XLT_RULE_VSI_DEFAULT 0x0 - /*[field] VSI_VALID*/ - #define EG_VLAN_XLT_RULE_VSI_VALID - #define EG_VLAN_XLT_RULE_VSI_VALID_OFFSET 15 - #define EG_VLAN_XLT_RULE_VSI_VALID_LEN 1 - #define EG_VLAN_XLT_RULE_VSI_VALID_DEFAULT 0x0 - /*[field] SKEY_FMT*/ - #define EG_VLAN_XLT_RULE_SKEY_FMT - #define EG_VLAN_XLT_RULE_SKEY_FMT_OFFSET 16 - #define EG_VLAN_XLT_RULE_SKEY_FMT_LEN 3 - #define EG_VLAN_XLT_RULE_SKEY_FMT_DEFAULT 0x0 - /*[field] SKEY_VID_INCL*/ - #define EG_VLAN_XLT_RULE_SKEY_VID_INCL - #define EG_VLAN_XLT_RULE_SKEY_VID_INCL_OFFSET 19 - #define EG_VLAN_XLT_RULE_SKEY_VID_INCL_LEN 1 - #define EG_VLAN_XLT_RULE_SKEY_VID_INCL_DEFAULT 0x0 - /*[field] SKEY_VID*/ - #define EG_VLAN_XLT_RULE_SKEY_VID - #define EG_VLAN_XLT_RULE_SKEY_VID_OFFSET 20 - #define EG_VLAN_XLT_RULE_SKEY_VID_LEN 12 - #define EG_VLAN_XLT_RULE_SKEY_VID_DEFAULT 0x0 - /*[field] SKEY_PCP_INCL*/ - #define EG_VLAN_XLT_RULE_SKEY_PCP_INCL - #define EG_VLAN_XLT_RULE_SKEY_PCP_INCL_OFFSET 32 - #define EG_VLAN_XLT_RULE_SKEY_PCP_INCL_LEN 1 - #define EG_VLAN_XLT_RULE_SKEY_PCP_INCL_DEFAULT 0x0 - /*[field] SKEY_PCP*/ - #define EG_VLAN_XLT_RULE_SKEY_PCP - #define EG_VLAN_XLT_RULE_SKEY_PCP_OFFSET 33 - #define EG_VLAN_XLT_RULE_SKEY_PCP_LEN 3 - #define EG_VLAN_XLT_RULE_SKEY_PCP_DEFAULT 0x0 - /*[field] SKEY_DEI_INCL*/ - #define EG_VLAN_XLT_RULE_SKEY_DEI_INCL - #define EG_VLAN_XLT_RULE_SKEY_DEI_INCL_OFFSET 36 - #define EG_VLAN_XLT_RULE_SKEY_DEI_INCL_LEN 1 - #define EG_VLAN_XLT_RULE_SKEY_DEI_INCL_DEFAULT 0x0 - /*[field] SKEY_DEI*/ - #define EG_VLAN_XLT_RULE_SKEY_DEI - #define EG_VLAN_XLT_RULE_SKEY_DEI_OFFSET 37 - #define EG_VLAN_XLT_RULE_SKEY_DEI_LEN 1 - #define EG_VLAN_XLT_RULE_SKEY_DEI_DEFAULT 0x0 - /*[field] CKEY_FMT*/ - #define EG_VLAN_XLT_RULE_CKEY_FMT - #define EG_VLAN_XLT_RULE_CKEY_FMT_OFFSET 38 - #define EG_VLAN_XLT_RULE_CKEY_FMT_LEN 3 - #define EG_VLAN_XLT_RULE_CKEY_FMT_DEFAULT 0x0 - /*[field] CKEY_VID_INCL*/ - #define EG_VLAN_XLT_RULE_CKEY_VID_INCL - #define EG_VLAN_XLT_RULE_CKEY_VID_INCL_OFFSET 41 - #define EG_VLAN_XLT_RULE_CKEY_VID_INCL_LEN 1 - #define EG_VLAN_XLT_RULE_CKEY_VID_INCL_DEFAULT 0x0 - /*[field] CKEY_VID*/ - #define EG_VLAN_XLT_RULE_CKEY_VID - #define EG_VLAN_XLT_RULE_CKEY_VID_OFFSET 42 - #define EG_VLAN_XLT_RULE_CKEY_VID_LEN 12 - #define EG_VLAN_XLT_RULE_CKEY_VID_DEFAULT 0x0 - /*[field] CKEY_PCP_INCL*/ - #define EG_VLAN_XLT_RULE_CKEY_PCP_INCL - #define EG_VLAN_XLT_RULE_CKEY_PCP_INCL_OFFSET 54 - #define EG_VLAN_XLT_RULE_CKEY_PCP_INCL_LEN 1 - #define EG_VLAN_XLT_RULE_CKEY_PCP_INCL_DEFAULT 0x0 - /*[field] CKEY_PCP*/ - #define EG_VLAN_XLT_RULE_CKEY_PCP - #define EG_VLAN_XLT_RULE_CKEY_PCP_OFFSET 55 - #define EG_VLAN_XLT_RULE_CKEY_PCP_LEN 3 - #define EG_VLAN_XLT_RULE_CKEY_PCP_DEFAULT 0x0 - /*[field] CKEY_DEI_INCL*/ - #define EG_VLAN_XLT_RULE_CKEY_DEI_INCL - #define EG_VLAN_XLT_RULE_CKEY_DEI_INCL_OFFSET 58 - #define EG_VLAN_XLT_RULE_CKEY_DEI_INCL_LEN 1 - #define EG_VLAN_XLT_RULE_CKEY_DEI_INCL_DEFAULT 0x0 - /*[field] CKEY_DEI*/ - #define EG_VLAN_XLT_RULE_CKEY_DEI - #define EG_VLAN_XLT_RULE_CKEY_DEI_OFFSET 59 - #define EG_VLAN_XLT_RULE_CKEY_DEI_LEN 1 - #define EG_VLAN_XLT_RULE_CKEY_DEI_DEFAULT 0x0 - -struct eg_vlan_xlt_rule { - a_uint32_t valid:1; - a_uint32_t port_bitmap:8; - a_uint32_t vsi_incl:1; - a_uint32_t vsi:5; - a_uint32_t vsi_valid:1; - a_uint32_t skey_fmt:3; - a_uint32_t skey_vid_incl:1; - a_uint32_t skey_vid:12; - a_uint32_t skey_pcp_incl:1; - a_uint32_t skey_pcp:3; - a_uint32_t skey_dei_incl:1; - a_uint32_t skey_dei:1; - a_uint32_t ckey_fmt:3; - a_uint32_t ckey_vid_incl:1; - a_uint32_t ckey_vid:12; - a_uint32_t ckey_pcp_incl:1; - a_uint32_t ckey_pcp:3; - a_uint32_t ckey_dei_incl:1; - a_uint32_t ckey_dei:1; - a_uint32_t _reserved0:4; -}; - -union eg_vlan_xlt_rule_u { - a_uint32_t val[2]; - struct eg_vlan_xlt_rule bf; -}; - -/*[register] EG_VSI_TAG*/ -#define EG_VSI_TAG -#define EG_VSI_TAG_ADDRESS 0x0 -#define EG_VSI_TAG_NUM 32 -#define EG_VSI_TAG_INC 0x4 -#define EG_VSI_TAG_TYPE REG_TYPE_RW -#define EG_VSI_TAG_DEFAULT 0xaaaa - /*[field] TAGGED_MODE_PORT_BITMAP*/ - #define EG_VSI_TAG_TAGGED_MODE_PORT_BITMAP - #define EG_VSI_TAG_TAGGED_MODE_PORT_BITMAP_OFFSET 0 - #define EG_VSI_TAG_TAGGED_MODE_PORT_BITMAP_LEN 16 - #define EG_VSI_TAG_TAGGED_MODE_PORT_BITMAP_DEFAULT 0xaaaa - -struct eg_vsi_tag { - a_uint32_t tagged_mode_port_bitmap:16; - a_uint32_t _reserved0:16; -}; - -union eg_vsi_tag_u { - a_uint32_t val; - struct eg_vsi_tag bf; -}; - -/*[register] PORT_EG_DEF_VID*/ -#define PORT_EG_DEF_VID -#define PORT_EG_DEF_VID_ADDRESS 0x400 -#define PORT_EG_DEF_VID_NUM 8 -#define PORT_EG_DEF_VID_INC 0x4 -#define PORT_EG_DEF_VID_TYPE REG_TYPE_RW -#define PORT_EG_DEF_VID_DEFAULT 0x0 - /*[field] PORT_DEF_SVID*/ - #define PORT_EG_DEF_VID_PORT_DEF_SVID - #define PORT_EG_DEF_VID_PORT_DEF_SVID_OFFSET 0 - #define PORT_EG_DEF_VID_PORT_DEF_SVID_LEN 12 - #define PORT_EG_DEF_VID_PORT_DEF_SVID_DEFAULT 0x0 - /*[field] PORT_DEF_SVID_EN*/ - #define PORT_EG_DEF_VID_PORT_DEF_SVID_EN - #define PORT_EG_DEF_VID_PORT_DEF_SVID_EN_OFFSET 12 - #define PORT_EG_DEF_VID_PORT_DEF_SVID_EN_LEN 1 - #define PORT_EG_DEF_VID_PORT_DEF_SVID_EN_DEFAULT 0x0 - /*[field] PORT_DEF_CVID*/ - #define PORT_EG_DEF_VID_PORT_DEF_CVID - #define PORT_EG_DEF_VID_PORT_DEF_CVID_OFFSET 16 - #define PORT_EG_DEF_VID_PORT_DEF_CVID_LEN 12 - #define PORT_EG_DEF_VID_PORT_DEF_CVID_DEFAULT 0x0 - /*[field] PORT_DEF_CVID_EN*/ - #define PORT_EG_DEF_VID_PORT_DEF_CVID_EN - #define PORT_EG_DEF_VID_PORT_DEF_CVID_EN_OFFSET 28 - #define PORT_EG_DEF_VID_PORT_DEF_CVID_EN_LEN 1 - #define PORT_EG_DEF_VID_PORT_DEF_CVID_EN_DEFAULT 0x0 - -struct port_eg_def_vid { - a_uint32_t port_def_svid:12; - a_uint32_t port_def_svid_en:1; - a_uint32_t _reserved0:3; - a_uint32_t port_def_cvid:12; - a_uint32_t port_def_cvid_en:1; - a_uint32_t _reserved1:3; -}; - -union port_eg_def_vid_u { - a_uint32_t val; - struct port_eg_def_vid bf; -}; - -/*[register] PORT_EG_VLAN*/ -#define PORT_EG_VLAN -#define PORT_EG_VLAN_ADDRESS 0x420 -#define PORT_EG_VLAN_NUM 8 -#define PORT_EG_VLAN_INC 0x4 -#define PORT_EG_VLAN_TYPE REG_TYPE_RW -#define PORT_EG_VLAN_DEFAULT 0x14 - /*[field] PORT_VLAN_TYPE*/ - #define PORT_EG_VLAN_PORT_VLAN_TYPE - #define PORT_EG_VLAN_PORT_VLAN_TYPE_OFFSET 0 - #define PORT_EG_VLAN_PORT_VLAN_TYPE_LEN 1 - #define PORT_EG_VLAN_PORT_VLAN_TYPE_DEFAULT 0x0 - /*[field] PORT_EG_VLAN_CTAG_MODE*/ - #define PORT_EG_VLAN_PORT_EG_VLAN_CTAG_MODE - #define PORT_EG_VLAN_PORT_EG_VLAN_CTAG_MODE_OFFSET 1 - #define PORT_EG_VLAN_PORT_EG_VLAN_CTAG_MODE_LEN 2 - #define PORT_EG_VLAN_PORT_EG_VLAN_CTAG_MODE_DEFAULT 0x2 - /*[field] PORT_EG_VLAN_STAG_MODE*/ - #define PORT_EG_VLAN_PORT_EG_VLAN_STAG_MODE - #define PORT_EG_VLAN_PORT_EG_VLAN_STAG_MODE_OFFSET 3 - #define PORT_EG_VLAN_PORT_EG_VLAN_STAG_MODE_LEN 2 - #define PORT_EG_VLAN_PORT_EG_VLAN_STAG_MODE_DEFAULT 0x2 - /*[field] VSI_TAG_MODE_EN*/ - #define PORT_EG_VLAN_VSI_TAG_MODE_EN - #define PORT_EG_VLAN_VSI_TAG_MODE_EN_OFFSET 5 - #define PORT_EG_VLAN_VSI_TAG_MODE_EN_LEN 1 - #define PORT_EG_VLAN_VSI_TAG_MODE_EN_DEFAULT 0x0 - /*[field] PORT_EG_PCP_PROP_CMD*/ - #define PORT_EG_VLAN_PORT_EG_PCP_PROP_CMD - #define PORT_EG_VLAN_PORT_EG_PCP_PROP_CMD_OFFSET 6 - #define PORT_EG_VLAN_PORT_EG_PCP_PROP_CMD_LEN 1 - #define PORT_EG_VLAN_PORT_EG_PCP_PROP_CMD_DEFAULT 0x0 - /*[field] PORT_EG_DEI_PROP_CMD*/ - #define PORT_EG_VLAN_PORT_EG_DEI_PROP_CMD - #define PORT_EG_VLAN_PORT_EG_DEI_PROP_CMD_OFFSET 7 - #define PORT_EG_VLAN_PORT_EG_DEI_PROP_CMD_LEN 1 - #define PORT_EG_VLAN_PORT_EG_DEI_PROP_CMD_DEFAULT 0x0 - /*[field] TX_COUNTING_EN*/ - #define PORT_EG_VLAN_TX_COUNTING_EN - #define PORT_EG_VLAN_TX_COUNTING_EN_OFFSET 8 - #define PORT_EG_VLAN_TX_COUNTING_EN_LEN 1 - #define PORT_EG_VLAN_TX_COUNTING_EN_DEFAULT 0x0 - -struct port_eg_vlan { - a_uint32_t port_vlan_type:1; - a_uint32_t port_eg_vlan_ctag_mode:2; - a_uint32_t port_eg_vlan_stag_mode:2; - a_uint32_t vsi_tag_mode_en:1; - a_uint32_t port_eg_pcp_prop_cmd:1; - a_uint32_t port_eg_dei_prop_cmd:1; - a_uint32_t tx_counting_en:1; - a_uint32_t _reserved0:23; -}; - -union port_eg_vlan_u { - a_uint32_t val; - struct port_eg_vlan bf; -}; - -/*[register] EG_VLAN_TPID*/ -#define EG_VLAN_TPID -#define EG_VLAN_TPID_ADDRESS 0x440 -#define EG_VLAN_TPID_NUM 1 -#define EG_VLAN_TPID_INC 0x4 -#define EG_VLAN_TPID_TYPE REG_TYPE_RW -#define EG_VLAN_TPID_DEFAULT 0x810088a8 - /*[field] STPID*/ - #define EG_VLAN_TPID_STPID - #define EG_VLAN_TPID_STPID_OFFSET 0 - #define EG_VLAN_TPID_STPID_LEN 16 - #define EG_VLAN_TPID_STPID_DEFAULT 0x88a8 - /*[field] CTPID*/ - #define EG_VLAN_TPID_CTPID - #define EG_VLAN_TPID_CTPID_OFFSET 16 - #define EG_VLAN_TPID_CTPID_LEN 16 - #define EG_VLAN_TPID_CTPID_DEFAULT 0x8100 - -struct eg_vlan_tpid { - a_uint32_t stpid:16; - a_uint32_t ctpid:16; -}; - -union eg_vlan_tpid_u { - a_uint32_t val; - struct eg_vlan_tpid bf; -}; - -/*[register] EG_BRIDGE_CONFIG*/ -#define EG_BRIDGE_CONFIG -#define EG_BRIDGE_CONFIG_ADDRESS 0x6000 -#define EG_BRIDGE_CONFIG_NUM 1 -#define EG_BRIDGE_CONFIG_INC 0x4 -#define EG_BRIDGE_CONFIG_TYPE REG_TYPE_RW -#define EG_BRIDGE_CONFIG_DEFAULT 0x0 - /*[field] BRIDGE_TYPE*/ - #define EG_BRIDGE_CONFIG_BRIDGE_TYPE - #define EG_BRIDGE_CONFIG_BRIDGE_TYPE_OFFSET 0 - #define EG_BRIDGE_CONFIG_BRIDGE_TYPE_LEN 1 - #define EG_BRIDGE_CONFIG_BRIDGE_TYPE_DEFAULT 0x0 - /*[field] PKT_L2_EDIT_EN*/ - #define EG_BRIDGE_CONFIG_PKT_L2_EDIT_EN - #define EG_BRIDGE_CONFIG_PKT_L2_EDIT_EN_OFFSET 1 - #define EG_BRIDGE_CONFIG_PKT_L2_EDIT_EN_LEN 1 - #define EG_BRIDGE_CONFIG_PKT_L2_EDIT_EN_DEFAULT 0x0 - /*[field] QUEUE_CNT_EN*/ - #define EG_BRIDGE_CONFIG_QUEUE_CNT_EN - #define EG_BRIDGE_CONFIG_QUEUE_CNT_EN_OFFSET 2 - #define EG_BRIDGE_CONFIG_QUEUE_CNT_EN_LEN 1 - #define EG_BRIDGE_CONFIG_QUEUE_CNT_EN_DEFAULT 0x0 - -struct eg_bridge_config { - a_uint32_t bridge_type:1; - a_uint32_t pkt_l2_edit_en:1; - a_uint32_t queue_cnt_en:1; - a_uint32_t _reserved0:29; -}; - -union eg_bridge_config_u { - a_uint32_t val; - struct eg_bridge_config bf; -}; - -/*[table] EG_VLAN_XLT_ACTION*/ -#define EG_VLAN_XLT_ACTION -#define EG_VLAN_XLT_ACTION_ADDRESS 0xd000 -#define EG_VLAN_XLT_ACTION_NUM 64 -#define EG_VLAN_XLT_ACTION_INC 0x8 -#define EG_VLAN_XLT_ACTION_TYPE REG_TYPE_RW -#define EG_VLAN_XLT_ACTION_DEFAULT 0x0 - /*[field] VID_SWAP_CMD*/ - #define EG_VLAN_XLT_ACTION_VID_SWAP_CMD - #define EG_VLAN_XLT_ACTION_VID_SWAP_CMD_OFFSET 0 - #define EG_VLAN_XLT_ACTION_VID_SWAP_CMD_LEN 1 - #define EG_VLAN_XLT_ACTION_VID_SWAP_CMD_DEFAULT 0x0 - /*[field] XLT_SVID_CMD*/ - #define EG_VLAN_XLT_ACTION_XLT_SVID_CMD - #define EG_VLAN_XLT_ACTION_XLT_SVID_CMD_OFFSET 1 - #define EG_VLAN_XLT_ACTION_XLT_SVID_CMD_LEN 2 - #define EG_VLAN_XLT_ACTION_XLT_SVID_CMD_DEFAULT 0x0 - /*[field] XLT_SVID*/ - #define EG_VLAN_XLT_ACTION_XLT_SVID - #define EG_VLAN_XLT_ACTION_XLT_SVID_OFFSET 3 - #define EG_VLAN_XLT_ACTION_XLT_SVID_LEN 12 - #define EG_VLAN_XLT_ACTION_XLT_SVID_DEFAULT 0x0 - /*[field] XLT_CVID_CMD*/ - #define EG_VLAN_XLT_ACTION_XLT_CVID_CMD - #define EG_VLAN_XLT_ACTION_XLT_CVID_CMD_OFFSET 15 - #define EG_VLAN_XLT_ACTION_XLT_CVID_CMD_LEN 2 - #define EG_VLAN_XLT_ACTION_XLT_CVID_CMD_DEFAULT 0x0 - /*[field] XLT_CVID*/ - #define EG_VLAN_XLT_ACTION_XLT_CVID - #define EG_VLAN_XLT_ACTION_XLT_CVID_OFFSET 17 - #define EG_VLAN_XLT_ACTION_XLT_CVID_LEN 12 - #define EG_VLAN_XLT_ACTION_XLT_CVID_DEFAULT 0x0 - /*[field] PCP_SWAP_CMD*/ - #define EG_VLAN_XLT_ACTION_PCP_SWAP_CMD - #define EG_VLAN_XLT_ACTION_PCP_SWAP_CMD_OFFSET 29 - #define EG_VLAN_XLT_ACTION_PCP_SWAP_CMD_LEN 1 - #define EG_VLAN_XLT_ACTION_PCP_SWAP_CMD_DEFAULT 0x0 - /*[field] XLT_SPCP_CMD*/ - #define EG_VLAN_XLT_ACTION_XLT_SPCP_CMD - #define EG_VLAN_XLT_ACTION_XLT_SPCP_CMD_OFFSET 30 - #define EG_VLAN_XLT_ACTION_XLT_SPCP_CMD_LEN 1 - #define EG_VLAN_XLT_ACTION_XLT_SPCP_CMD_DEFAULT 0x0 - /*[field] XLT_SPCP*/ - #define EG_VLAN_XLT_ACTION_XLT_SPCP - #define EG_VLAN_XLT_ACTION_XLT_SPCP_OFFSET 31 - #define EG_VLAN_XLT_ACTION_XLT_SPCP_LEN 3 - #define EG_VLAN_XLT_ACTION_XLT_SPCP_DEFAULT 0x0 - /*[field] XLT_CPCP_CMD*/ - #define EG_VLAN_XLT_ACTION_XLT_CPCP_CMD - #define EG_VLAN_XLT_ACTION_XLT_CPCP_CMD_OFFSET 34 - #define EG_VLAN_XLT_ACTION_XLT_CPCP_CMD_LEN 1 - #define EG_VLAN_XLT_ACTION_XLT_CPCP_CMD_DEFAULT 0x0 - /*[field] XLT_CPCP*/ - #define EG_VLAN_XLT_ACTION_XLT_CPCP - #define EG_VLAN_XLT_ACTION_XLT_CPCP_OFFSET 35 - #define EG_VLAN_XLT_ACTION_XLT_CPCP_LEN 3 - #define EG_VLAN_XLT_ACTION_XLT_CPCP_DEFAULT 0x0 - /*[field] DEI_SWAP_CMD*/ - #define EG_VLAN_XLT_ACTION_DEI_SWAP_CMD - #define EG_VLAN_XLT_ACTION_DEI_SWAP_CMD_OFFSET 38 - #define EG_VLAN_XLT_ACTION_DEI_SWAP_CMD_LEN 1 - #define EG_VLAN_XLT_ACTION_DEI_SWAP_CMD_DEFAULT 0x0 - /*[field] XLT_SDEI_CMD*/ - #define EG_VLAN_XLT_ACTION_XLT_SDEI_CMD - #define EG_VLAN_XLT_ACTION_XLT_SDEI_CMD_OFFSET 39 - #define EG_VLAN_XLT_ACTION_XLT_SDEI_CMD_LEN 1 - #define EG_VLAN_XLT_ACTION_XLT_SDEI_CMD_DEFAULT 0x0 - /*[field] XLT_SDEI*/ - #define EG_VLAN_XLT_ACTION_XLT_SDEI - #define EG_VLAN_XLT_ACTION_XLT_SDEI_OFFSET 40 - #define EG_VLAN_XLT_ACTION_XLT_SDEI_LEN 1 - #define EG_VLAN_XLT_ACTION_XLT_SDEI_DEFAULT 0x0 - /*[field] XLT_CDEI_CMD*/ - #define EG_VLAN_XLT_ACTION_XLT_CDEI_CMD - #define EG_VLAN_XLT_ACTION_XLT_CDEI_CMD_OFFSET 41 - #define EG_VLAN_XLT_ACTION_XLT_CDEI_CMD_LEN 1 - #define EG_VLAN_XLT_ACTION_XLT_CDEI_CMD_DEFAULT 0x0 - /*[field] XLT_CDEI*/ - #define EG_VLAN_XLT_ACTION_XLT_CDEI - #define EG_VLAN_XLT_ACTION_XLT_CDEI_OFFSET 42 - #define EG_VLAN_XLT_ACTION_XLT_CDEI_LEN 1 - #define EG_VLAN_XLT_ACTION_XLT_CDEI_DEFAULT 0x0 - /*[field] COUNTER_EN*/ - #define EG_VLAN_XLT_ACTION_COUNTER_EN - #define EG_VLAN_XLT_ACTION_COUNTER_EN_OFFSET 43 - #define EG_VLAN_XLT_ACTION_COUNTER_EN_LEN 1 - #define EG_VLAN_XLT_ACTION_COUNTER_EN_DEFAULT 0x0 - /*[field] COUNTER_ID*/ - #define EG_VLAN_XLT_ACTION_COUNTER_ID - #define EG_VLAN_XLT_ACTION_COUNTER_ID_OFFSET 44 - #define EG_VLAN_XLT_ACTION_COUNTER_ID_LEN 6 - #define EG_VLAN_XLT_ACTION_COUNTER_ID_DEFAULT 0x0 - -struct eg_vlan_xlt_action { - a_uint32_t vid_swap_cmd:1; - a_uint32_t xlt_svid_cmd:2; - a_uint32_t xlt_svid:12; - a_uint32_t xlt_cvid_cmd:2; - a_uint32_t xlt_cvid:12; - a_uint32_t pcp_swap_cmd:1; - a_uint32_t xlt_spcp_cmd:1; - a_uint32_t xlt_spcp_0:1; - a_uint32_t xlt_spcp_1:2; - a_uint32_t xlt_cpcp_cmd:1; - a_uint32_t xlt_cpcp:3; - a_uint32_t dei_swap_cmd:1; - a_uint32_t xlt_sdei_cmd:1; - a_uint32_t xlt_sdei:1; - a_uint32_t xlt_cdei_cmd:1; - a_uint32_t xlt_cdei:1; - a_uint32_t counter_en:1; - a_uint32_t counter_id:6; - a_uint32_t _reserved0:14; -}; - -union eg_vlan_xlt_action_u { - a_uint32_t val[2]; - struct eg_vlan_xlt_action bf; -}; - -/*[table] VLAN_DEV_TX_COUNTER_TBL*/ -#define VLAN_DEV_TX_COUNTER_TBL -#define VLAN_DEV_TX_COUNTER_TBL_ADDRESS 0x2000 -#define VLAN_DEV_TX_COUNTER_TBL_NUM 64 -#define VLAN_DEV_TX_COUNTER_TBL_INC 0x10 -#define VLAN_DEV_TX_COUNTER_TBL_TYPE REG_TYPE_RW -#define VLAN_DEV_TX_COUNTER_TBL_DEFAULT 0x0 - /*[field] TX_PKT_CNT*/ - #define VLAN_DEV_TX_COUNTER_TBL_TX_PKT_CNT - #define VLAN_DEV_TX_COUNTER_TBL_TX_PKT_CNT_OFFSET 0 - #define VLAN_DEV_TX_COUNTER_TBL_TX_PKT_CNT_LEN 32 - #define VLAN_DEV_TX_COUNTER_TBL_TX_PKT_CNT_DEFAULT 0x0 - /*[field] TX_BYTE_CNT*/ - #define VLAN_DEV_TX_COUNTER_TBL_TX_BYTE_CNT - #define VLAN_DEV_TX_COUNTER_TBL_TX_BYTE_CNT_OFFSET 32 - #define VLAN_DEV_TX_COUNTER_TBL_TX_BYTE_CNT_LEN 40 - #define VLAN_DEV_TX_COUNTER_TBL_TX_BYTE_CNT_DEFAULT 0x0 - -struct vlan_dev_tx_counter_tbl { - a_uint32_t tx_pkt_cnt:32; - a_uint32_t tx_byte_cnt_0:32; - a_uint32_t tx_byte_cnt_1:8; - a_uint32_t _reserved0:24; -}; - -union vlan_dev_tx_counter_tbl_u { - a_uint32_t val[3]; - struct vlan_dev_tx_counter_tbl bf; -}; - -#endif diff --git a/feeds/ipq807x/qca-ssdk/src/include/hsl/hppe/hppe_pppoe.h b/feeds/ipq807x/qca-ssdk/src/include/hsl/hppe/hppe_pppoe.h deleted file mode 100755 index 051e596bc..000000000 --- a/feeds/ipq807x/qca-ssdk/src/include/hsl/hppe/hppe_pppoe.h +++ /dev/null @@ -1,173 +0,0 @@ -/* - * Copyright (c) 2016-2017, The Linux Foundation. All rights reserved. - * Permission to use, copy, modify, and/or distribute this software for - * any purpose with or without fee is hereby granted, provided that the - * above copyright notice and this permission notice appear in all copies. - * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES - * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR - * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES - * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN - * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT - * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. - */ - - -/** - * @defgroup - * @{ - */ -#ifndef _HPPE_PPPOE_H_ -#define _HPPE_PPPOE_H_ - -#define PPPOE_SESSION_MAX_ENTRY 16 -#define PPPOE_SESSION_EXT_MAX_ENTRY 16 -#define PPPOE_SESSION_EXT1_MAX_ENTRY 16 - -sw_error_t -hppe_pppoe_session_get( - a_uint32_t dev_id, - a_uint32_t index, - union pppoe_session_u *value); - -sw_error_t -hppe_pppoe_session_set( - a_uint32_t dev_id, - a_uint32_t index, - union pppoe_session_u *value); - -sw_error_t -hppe_pppoe_session_ext_get( - a_uint32_t dev_id, - a_uint32_t index, - union pppoe_session_ext_u *value); - -sw_error_t -hppe_pppoe_session_ext_set( - a_uint32_t dev_id, - a_uint32_t index, - union pppoe_session_ext_u *value); - -sw_error_t -hppe_pppoe_session_ext1_get( - a_uint32_t dev_id, - a_uint32_t index, - union pppoe_session_ext1_u *value); - -sw_error_t -hppe_pppoe_session_ext1_set( - a_uint32_t dev_id, - a_uint32_t index, - union pppoe_session_ext1_u *value); - -sw_error_t -hppe_pppoe_session_session_id_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_pppoe_session_session_id_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_pppoe_session_l3_if_index_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_pppoe_session_l3_if_index_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_pppoe_session_port_bitmap_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_pppoe_session_port_bitmap_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_pppoe_session_ext_uc_valid_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_pppoe_session_ext_uc_valid_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_pppoe_session_ext_mc_valid_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_pppoe_session_ext_mc_valid_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_pppoe_session_ext_smac_valid_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_pppoe_session_ext_smac_valid_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_pppoe_session_ext_l3_if_valid_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_pppoe_session_ext_l3_if_valid_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_pppoe_session_ext_smac_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_pppoe_session_ext_smac_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_pppoe_session_ext1_smac_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_pppoe_session_ext1_smac_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - - -#endif - diff --git a/feeds/ipq807x/qca-ssdk/src/include/hsl/hppe/hppe_pppoe_reg.h b/feeds/ipq807x/qca-ssdk/src/include/hsl/hppe/hppe_pppoe_reg.h deleted file mode 100755 index 715c8287c..000000000 --- a/feeds/ipq807x/qca-ssdk/src/include/hsl/hppe/hppe_pppoe_reg.h +++ /dev/null @@ -1,127 +0,0 @@ -/* - * Copyright (c) 2016-2017, The Linux Foundation. All rights reserved. - * Permission to use, copy, modify, and/or distribute this software for - * any purpose with or without fee is hereby granted, provided that the - * above copyright notice and this permission notice appear in all copies. - * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES - * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR - * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES - * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN - * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT - * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. - */ - - -/** - * @defgroup - * @{ - */ -#ifndef HPPE_PPPOE_REG_H -#define HPPE_PPPOE_REG_H - - -/*[register] PPPOE_SESSION*/ -#define PPPOE_SESSION -#define PPPOE_SESSION_ADDRESS 0xc20 -#define PPPOE_SESSION_NUM 16 -#define PPPOE_SESSION_INC 0x4 -#define PPPOE_SESSION_TYPE REG_TYPE_RW -#define PPPOE_SESSION_DEFAULT 0x0 - /*[field] SESSION_ID*/ - #define PPPOE_SESSION_SESSION_ID - #define PPPOE_SESSION_SESSION_ID_OFFSET 0 - #define PPPOE_SESSION_SESSION_ID_LEN 16 - #define PPPOE_SESSION_SESSION_ID_DEFAULT 0x0 - /*[field] PORT_BITMAP*/ - #define PPPOE_SESSION_PORT_BITMAP - #define PPPOE_SESSION_PORT_BITMAP_OFFSET 16 - #define PPPOE_SESSION_PORT_BITMAP_LEN 8 - #define PPPOE_SESSION_PORT_BITMAP_DEFAULT 0x0 - /*[field] L3_IF_INDEX*/ - #define PPPOE_SESSION_L3_IF_INDEX - #define PPPOE_SESSION_L3_IF_INDEX_OFFSET 24 - #define PPPOE_SESSION_L3_IF_INDEX_LEN 8 - #define PPPOE_SESSION_L3_IF_INDEX_DEFAULT 0x0 - -struct pppoe_session { - a_uint32_t session_id:16; - a_uint32_t port_bitmap:8; - a_uint32_t l3_if_index:8; -}; - -union pppoe_session_u { - a_uint32_t val; - struct pppoe_session bf; -}; - -/*[register] PPPOE_SESSION_EXT*/ -#define PPPOE_SESSION_EXT -#define PPPOE_SESSION_EXT_ADDRESS 0xc60 -#define PPPOE_SESSION_EXT_NUM 16 -#define PPPOE_SESSION_EXT_INC 0x4 -#define PPPOE_SESSION_EXT_TYPE REG_TYPE_RW -#define PPPOE_SESSION_EXT_DEFAULT 0x0 - /*[field] L3_IF_VALID*/ - #define PPPOE_SESSION_EXT_L3_IF_VALID - #define PPPOE_SESSION_EXT_L3_IF_VALID_OFFSET 0 - #define PPPOE_SESSION_EXT_L3_IF_VALID_LEN 1 - #define PPPOE_SESSION_EXT_L3_IF_VALID_DEFAULT 0x0 - /*[field] MC_VALID*/ - #define PPPOE_SESSION_EXT_MC_VALID - #define PPPOE_SESSION_EXT_MC_VALID_OFFSET 1 - #define PPPOE_SESSION_EXT_MC_VALID_LEN 1 - #define PPPOE_SESSION_EXT_MC_VALID_DEFAULT 0x0 - /*[field] UC_VALID*/ - #define PPPOE_SESSION_EXT_UC_VALID - #define PPPOE_SESSION_EXT_UC_VALID_OFFSET 2 - #define PPPOE_SESSION_EXT_UC_VALID_LEN 1 - #define PPPOE_SESSION_EXT_UC_VALID_DEFAULT 0x0 - /*[field] SMAC_VALID*/ - #define PPPOE_SESSION_EXT_SMAC_VALID - #define PPPOE_SESSION_EXT_SMAC_VALID_OFFSET 3 - #define PPPOE_SESSION_EXT_SMAC_VALID_LEN 1 - #define PPPOE_SESSION_EXT_SMAC_VALID_DEFAULT 0x0 - /*[field] SMAC*/ - #define PPPOE_SESSION_EXT_SMAC - #define PPPOE_SESSION_EXT_SMAC_OFFSET 16 - #define PPPOE_SESSION_EXT_SMAC_LEN 16 - #define PPPOE_SESSION_EXT_SMAC_DEFAULT 0x0 - -struct pppoe_session_ext { - a_uint32_t l3_if_valid:1; - a_uint32_t mc_valid:1; - a_uint32_t uc_valid:1; - a_uint32_t smac_valid:1; - a_uint32_t _reserved0:12; - a_uint32_t smac:16; -}; - -union pppoe_session_ext_u { - a_uint32_t val; - struct pppoe_session_ext bf; -}; - -/*[register] PPPOE_SESSION_EXT1*/ -#define PPPOE_SESSION_EXT1 -#define PPPOE_SESSION_EXT1_ADDRESS 0xca0 -#define PPPOE_SESSION_EXT1_NUM 16 -#define PPPOE_SESSION_EXT1_INC 0x4 -#define PPPOE_SESSION_EXT1_TYPE REG_TYPE_RW -#define PPPOE_SESSION_EXT1_DEFAULT 0x0 - /*[field] SMAC*/ - #define PPPOE_SESSION_EXT1_SMAC - #define PPPOE_SESSION_EXT1_SMAC_OFFSET 0 - #define PPPOE_SESSION_EXT1_SMAC_LEN 32 - #define PPPOE_SESSION_EXT1_SMAC_DEFAULT 0x0 - -struct pppoe_session_ext1 { - a_uint32_t smac:32; -}; - -union pppoe_session_ext1_u { - a_uint32_t val; - struct pppoe_session_ext1 bf; -}; - -#endif diff --git a/feeds/ipq807x/qca-ssdk/src/include/hsl/hppe/hppe_qm.h b/feeds/ipq807x/qca-ssdk/src/include/hsl/hppe/hppe_qm.h deleted file mode 100755 index 383a07cc6..000000000 --- a/feeds/ipq807x/qca-ssdk/src/include/hsl/hppe/hppe_qm.h +++ /dev/null @@ -1,3811 +0,0 @@ -/* - * Copyright (c) 2016-2017, The Linux Foundation. All rights reserved. - * Permission to use, copy, modify, and/or distribute this software for - * any purpose with or without fee is hereby granted, provided that the - * above copyright notice and this permission notice appear in all copies. - * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES - * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR - * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES - * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN - * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT - * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. - */ - - -/** - * @defgroup - * @{ - */ -#ifndef _HPPE_QM_H_ -#define _HPPE_QM_H_ - -#define MCAST_PRIORITY_MAP0_MAX_ENTRY 16 -#define MCAST_PRIORITY_MAP1_MAX_ENTRY 16 -#define MCAST_PRIORITY_MAP2_MAX_ENTRY 16 -#define MCAST_PRIORITY_MAP3_MAX_ENTRY 16 -#define MCAST_PRIORITY_MAP4_MAX_ENTRY 16 -#define MCAST_PRIORITY_MAP5_MAX_ENTRY 16 -#define MCAST_PRIORITY_MAP6_MAX_ENTRY 16 -#define MCAST_PRIORITY_MAP7_MAX_ENTRY 16 -#define UQ_AGG_PROFILE_CFG_MAX_ENTRY 8 -#define MQ_AGG_PROFILE_CFG_MAX_ENTRY 8 -#define GRP_AGG_PROFILE_CFG_MAX_ENTRY 4 -#define UQ_AGG_IN_PROFILE_CNT_MAX_ENTRY 8 -#define UQ_AGG_OUT_PROFILE_CNT_MAX_ENTRY 8 -#define MQ_AGG_IN_PROFILE_CNT_MAX_ENTRY 8 -#define MQ_AGG_OUT_PROFILE_CNT_MAX_ENTRY 8 -#define GRP_AGG_IN_PROFILE_CNT_MAX_ENTRY 4 -#define GRP_AGG_OUT_PROFILE_CNT_MAX_ENTRY 4 -#define UCAST_QUEUE_MAP_TBL_MAX_ENTRY 3072 -#define UCAST_HASH_MAP_TBL_MAX_ENTRY 4096 -#define UCAST_PRIORITY_MAP_TBL_MAX_ENTRY 256 -#define MCAST_QUEUE_MAP_TBL_MAX_ENTRY 256 -#define AC_MSEQ_TBL_MAX_ENTRY 256 -#define AC_UNI_QUEUE_CFG_TBL_MAX_ENTRY 256 -#define AC_MUL_QUEUE_CFG_TBL_MAX_ENTRY 44 -#define AC_GRP_CFG_TBL_MAX_ENTRY 4 -#define AC_UNI_QUEUE_CNT_TBL_MAX_ENTRY 256 -#define AC_MUL_QUEUE_CNT_TBL_MAX_ENTRY 44 -#define AC_GRP_CNT_TBL_MAX_ENTRY 4 -#define AC_UNI_QUEUE_DROP_STATE_TBL_MAX_ENTRY 256 -#define AC_MUL_QUEUE_DROP_STATE_TBL_MAX_ENTRY 44 -#define AC_GRP_DROP_STATE_TBL_MAX_ENTRY 4 -#define OQ_ENQ_OPR_TBL_MAX_ENTRY 300 -#define OQ_DEQ_OPR_TBL_MAX_ENTRY 300 -#define OQ_HEAD_UNI_TBL_MAX_ENTRY 256 -#define OQ_HEAD_MUL_TBL_MAX_ENTRY 44 -#define OQ_LL_UNI_TBL_MAX_ENTRY 2048 -#define OQ_LL_MUL_P0_TBL_MAX_ENTRY 2048 -#define OQ_LL_MUL_P1_TBL_MAX_ENTRY 2048 -#define OQ_LL_MUL_P2_TBL_MAX_ENTRY 2048 -#define OQ_LL_MUL_P3_TBL_MAX_ENTRY 2048 -#define OQ_LL_MUL_P4_TBL_MAX_ENTRY 2048 -#define OQ_LL_MUL_P5_TBL_MAX_ENTRY 2048 -#define OQ_LL_MUL_P6_TBL_MAX_ENTRY 2048 -#define OQ_LL_MUL_P7_TBL_MAX_ENTRY 2048 -#define PKT_DESP_TBL_MAX_ENTRY 2048 -#define UNI_DROP_CNT_TBL_MAX_ENTRY 1536 -#define MUL_P0_DROP_CNT_TBL_MAX_ENTRY 48 -#define MUL_P1_DROP_CNT_TBL_MAX_ENTRY 12 -#define MUL_P2_DROP_CNT_TBL_MAX_ENTRY 12 -#define MUL_P3_DROP_CNT_TBL_MAX_ENTRY 12 -#define MUL_P4_DROP_CNT_TBL_MAX_ENTRY 12 -#define MUL_P5_DROP_CNT_TBL_MAX_ENTRY 12 -#define MUL_P6_DROP_CNT_TBL_MAX_ENTRY 12 -#define MUL_P7_DROP_CNT_TBL_MAX_ENTRY 12 -#define UQ_AGG_PROFILE_MAP_MAX_ENTRY 256 -#define QUEUE_TX_COUNTER_TBL_MAX_ENTRY 300 - -sw_error_t -hppe_queue_tx_counter_tbl_get( - a_uint32_t dev_id, - a_uint32_t index, - union queue_tx_counter_tbl_u *value); - -sw_error_t -hppe_queue_tx_counter_tbl_set( - a_uint32_t dev_id, - a_uint32_t index, - union queue_tx_counter_tbl_u *value); - -sw_error_t -hppe_flush_cfg_get( - a_uint32_t dev_id, - union flush_cfg_u *value); - -sw_error_t -hppe_flush_cfg_set( - a_uint32_t dev_id, - union flush_cfg_u *value); - -sw_error_t -hppe_in_mirror_priority_ctrl_get( - a_uint32_t dev_id, - union in_mirror_priority_ctrl_u *value); - -sw_error_t -hppe_in_mirror_priority_ctrl_set( - a_uint32_t dev_id, - union in_mirror_priority_ctrl_u *value); - -sw_error_t -hppe_eg_mirror_priority_ctrl_get( - a_uint32_t dev_id, - union eg_mirror_priority_ctrl_u *value); - -sw_error_t -hppe_eg_mirror_priority_ctrl_set( - a_uint32_t dev_id, - union eg_mirror_priority_ctrl_u *value); - -sw_error_t -hppe_ucast_default_hash_get( - a_uint32_t dev_id, - union ucast_default_hash_u *value); - -sw_error_t -hppe_ucast_default_hash_set( - a_uint32_t dev_id, - union ucast_default_hash_u *value); - -sw_error_t -hppe_spare_reg0_get( - a_uint32_t dev_id, - union spare_reg0_u *value); - -sw_error_t -hppe_spare_reg0_set( - a_uint32_t dev_id, - union spare_reg0_u *value); - -sw_error_t -hppe_spare_reg1_get( - a_uint32_t dev_id, - union spare_reg1_u *value); - -sw_error_t -hppe_spare_reg1_set( - a_uint32_t dev_id, - union spare_reg1_u *value); - -sw_error_t -hppe_qm_dbg_addr_get( - a_uint32_t dev_id, - union qm_dbg_addr_u *value); - -sw_error_t -hppe_qm_dbg_addr_set( - a_uint32_t dev_id, - union qm_dbg_addr_u *value); - -sw_error_t -hppe_qm_dbg_data_get( - a_uint32_t dev_id, - union qm_dbg_data_u *value); - -sw_error_t -hppe_qm_dbg_data_set( - a_uint32_t dev_id, - union qm_dbg_data_u *value); - -sw_error_t -hppe_mcast_priority_map0_get( - a_uint32_t dev_id, - a_uint32_t index, - union mcast_priority_map0_u *value); - -sw_error_t -hppe_mcast_priority_map0_set( - a_uint32_t dev_id, - a_uint32_t index, - union mcast_priority_map0_u *value); - -sw_error_t -hppe_mcast_priority_map1_get( - a_uint32_t dev_id, - a_uint32_t index, - union mcast_priority_map1_u *value); - -sw_error_t -hppe_mcast_priority_map1_set( - a_uint32_t dev_id, - a_uint32_t index, - union mcast_priority_map1_u *value); - -sw_error_t -hppe_mcast_priority_map2_get( - a_uint32_t dev_id, - a_uint32_t index, - union mcast_priority_map2_u *value); - -sw_error_t -hppe_mcast_priority_map2_set( - a_uint32_t dev_id, - a_uint32_t index, - union mcast_priority_map2_u *value); - -sw_error_t -hppe_mcast_priority_map3_get( - a_uint32_t dev_id, - a_uint32_t index, - union mcast_priority_map3_u *value); - -sw_error_t -hppe_mcast_priority_map3_set( - a_uint32_t dev_id, - a_uint32_t index, - union mcast_priority_map3_u *value); - -sw_error_t -hppe_mcast_priority_map4_get( - a_uint32_t dev_id, - a_uint32_t index, - union mcast_priority_map4_u *value); - -sw_error_t -hppe_mcast_priority_map4_set( - a_uint32_t dev_id, - a_uint32_t index, - union mcast_priority_map4_u *value); - -sw_error_t -hppe_mcast_priority_map5_get( - a_uint32_t dev_id, - a_uint32_t index, - union mcast_priority_map5_u *value); - -sw_error_t -hppe_mcast_priority_map5_set( - a_uint32_t dev_id, - a_uint32_t index, - union mcast_priority_map5_u *value); - -sw_error_t -hppe_mcast_priority_map6_get( - a_uint32_t dev_id, - a_uint32_t index, - union mcast_priority_map6_u *value); - -sw_error_t -hppe_mcast_priority_map6_set( - a_uint32_t dev_id, - a_uint32_t index, - union mcast_priority_map6_u *value); - -sw_error_t -hppe_mcast_priority_map7_get( - a_uint32_t dev_id, - a_uint32_t index, - union mcast_priority_map7_u *value); - -sw_error_t -hppe_mcast_priority_map7_set( - a_uint32_t dev_id, - a_uint32_t index, - union mcast_priority_map7_u *value); - -sw_error_t -hppe_agg_profile_cnt_en_get( - a_uint32_t dev_id, - union agg_profile_cnt_en_u *value); - -sw_error_t -hppe_agg_profile_cnt_en_set( - a_uint32_t dev_id, - union agg_profile_cnt_en_u *value); - -sw_error_t -hppe_uq_agg_profile_cfg_get( - a_uint32_t dev_id, - a_uint32_t index, - union uq_agg_profile_cfg_u *value); - -sw_error_t -hppe_uq_agg_profile_cfg_set( - a_uint32_t dev_id, - a_uint32_t index, - union uq_agg_profile_cfg_u *value); - -sw_error_t -hppe_mq_agg_profile_cfg_get( - a_uint32_t dev_id, - a_uint32_t index, - union mq_agg_profile_cfg_u *value); - -sw_error_t -hppe_mq_agg_profile_cfg_set( - a_uint32_t dev_id, - a_uint32_t index, - union mq_agg_profile_cfg_u *value); - -sw_error_t -hppe_grp_agg_profile_cfg_get( - a_uint32_t dev_id, - a_uint32_t index, - union grp_agg_profile_cfg_u *value); - -sw_error_t -hppe_grp_agg_profile_cfg_set( - a_uint32_t dev_id, - a_uint32_t index, - union grp_agg_profile_cfg_u *value); - -sw_error_t -hppe_uq_agg_in_profile_cnt_get( - a_uint32_t dev_id, - a_uint32_t index, - union uq_agg_in_profile_cnt_u *value); - -sw_error_t -hppe_uq_agg_in_profile_cnt_set( - a_uint32_t dev_id, - a_uint32_t index, - union uq_agg_in_profile_cnt_u *value); - -sw_error_t -hppe_uq_agg_out_profile_cnt_get( - a_uint32_t dev_id, - a_uint32_t index, - union uq_agg_out_profile_cnt_u *value); - -sw_error_t -hppe_uq_agg_out_profile_cnt_set( - a_uint32_t dev_id, - a_uint32_t index, - union uq_agg_out_profile_cnt_u *value); - -sw_error_t -hppe_mq_agg_in_profile_cnt_get( - a_uint32_t dev_id, - a_uint32_t index, - union mq_agg_in_profile_cnt_u *value); - -sw_error_t -hppe_mq_agg_in_profile_cnt_set( - a_uint32_t dev_id, - a_uint32_t index, - union mq_agg_in_profile_cnt_u *value); - -sw_error_t -hppe_mq_agg_out_profile_cnt_get( - a_uint32_t dev_id, - a_uint32_t index, - union mq_agg_out_profile_cnt_u *value); - -sw_error_t -hppe_mq_agg_out_profile_cnt_set( - a_uint32_t dev_id, - a_uint32_t index, - union mq_agg_out_profile_cnt_u *value); - -sw_error_t -hppe_grp_agg_in_profile_cnt_get( - a_uint32_t dev_id, - a_uint32_t index, - union grp_agg_in_profile_cnt_u *value); - -sw_error_t -hppe_grp_agg_in_profile_cnt_set( - a_uint32_t dev_id, - a_uint32_t index, - union grp_agg_in_profile_cnt_u *value); - -sw_error_t -hppe_grp_agg_out_profile_cnt_get( - a_uint32_t dev_id, - a_uint32_t index, - union grp_agg_out_profile_cnt_u *value); - -sw_error_t -hppe_grp_agg_out_profile_cnt_set( - a_uint32_t dev_id, - a_uint32_t index, - union grp_agg_out_profile_cnt_u *value); - -sw_error_t -hppe_ucast_queue_map_tbl_get( - a_uint32_t dev_id, - a_uint32_t index, - union ucast_queue_map_tbl_u *value); - -sw_error_t -hppe_ucast_queue_map_tbl_set( - a_uint32_t dev_id, - a_uint32_t index, - union ucast_queue_map_tbl_u *value); - -sw_error_t -hppe_ucast_hash_map_tbl_get( - a_uint32_t dev_id, - a_uint32_t index, - union ucast_hash_map_tbl_u *value); - -sw_error_t -hppe_ucast_hash_map_tbl_set( - a_uint32_t dev_id, - a_uint32_t index, - union ucast_hash_map_tbl_u *value); - -sw_error_t -hppe_ucast_priority_map_tbl_get( - a_uint32_t dev_id, - a_uint32_t index, - union ucast_priority_map_tbl_u *value); - -sw_error_t -hppe_ucast_priority_map_tbl_set( - a_uint32_t dev_id, - a_uint32_t index, - union ucast_priority_map_tbl_u *value); - -sw_error_t -hppe_mcast_queue_map_tbl_get( - a_uint32_t dev_id, - a_uint32_t index, - union mcast_queue_map_tbl_u *value); - -sw_error_t -hppe_mcast_queue_map_tbl_set( - a_uint32_t dev_id, - a_uint32_t index, - union mcast_queue_map_tbl_u *value); - -sw_error_t -hppe_ac_mseq_tbl_get( - a_uint32_t dev_id, - a_uint32_t index, - union ac_mseq_tbl_u *value); - -sw_error_t -hppe_ac_mseq_tbl_set( - a_uint32_t dev_id, - a_uint32_t index, - union ac_mseq_tbl_u *value); - -sw_error_t -hppe_ac_uni_queue_cfg_tbl_get( - a_uint32_t dev_id, - a_uint32_t index, - union ac_uni_queue_cfg_tbl_u *value); - -sw_error_t -hppe_ac_uni_queue_cfg_tbl_set( - a_uint32_t dev_id, - a_uint32_t index, - union ac_uni_queue_cfg_tbl_u *value); - -sw_error_t -hppe_ac_mul_queue_cfg_tbl_get( - a_uint32_t dev_id, - a_uint32_t index, - union ac_mul_queue_cfg_tbl_u *value); - -sw_error_t -hppe_ac_mul_queue_cfg_tbl_set( - a_uint32_t dev_id, - a_uint32_t index, - union ac_mul_queue_cfg_tbl_u *value); - -sw_error_t -hppe_ac_grp_cfg_tbl_get( - a_uint32_t dev_id, - a_uint32_t index, - union ac_grp_cfg_tbl_u *value); - -sw_error_t -hppe_ac_grp_cfg_tbl_set( - a_uint32_t dev_id, - a_uint32_t index, - union ac_grp_cfg_tbl_u *value); - -sw_error_t -hppe_ac_uni_queue_cnt_tbl_get( - a_uint32_t dev_id, - a_uint32_t index, - union ac_uni_queue_cnt_tbl_u *value); - -sw_error_t -hppe_ac_uni_queue_cnt_tbl_set( - a_uint32_t dev_id, - a_uint32_t index, - union ac_uni_queue_cnt_tbl_u *value); - -sw_error_t -hppe_ac_mul_queue_cnt_tbl_get( - a_uint32_t dev_id, - a_uint32_t index, - union ac_mul_queue_cnt_tbl_u *value); - -sw_error_t -hppe_ac_mul_queue_cnt_tbl_set( - a_uint32_t dev_id, - a_uint32_t index, - union ac_mul_queue_cnt_tbl_u *value); - -sw_error_t -hppe_ac_grp_cnt_tbl_get( - a_uint32_t dev_id, - a_uint32_t index, - union ac_grp_cnt_tbl_u *value); - -sw_error_t -hppe_ac_grp_cnt_tbl_set( - a_uint32_t dev_id, - a_uint32_t index, - union ac_grp_cnt_tbl_u *value); - -sw_error_t -hppe_ac_uni_queue_drop_state_tbl_get( - a_uint32_t dev_id, - a_uint32_t index, - union ac_uni_queue_drop_state_tbl_u *value); - -sw_error_t -hppe_ac_uni_queue_drop_state_tbl_set( - a_uint32_t dev_id, - a_uint32_t index, - union ac_uni_queue_drop_state_tbl_u *value); - -sw_error_t -hppe_ac_mul_queue_drop_state_tbl_get( - a_uint32_t dev_id, - a_uint32_t index, - union ac_mul_queue_drop_state_tbl_u *value); - -sw_error_t -hppe_ac_mul_queue_drop_state_tbl_set( - a_uint32_t dev_id, - a_uint32_t index, - union ac_mul_queue_drop_state_tbl_u *value); - -sw_error_t -hppe_ac_grp_drop_state_tbl_get( - a_uint32_t dev_id, - a_uint32_t index, - union ac_grp_drop_state_tbl_u *value); - -sw_error_t -hppe_ac_grp_drop_state_tbl_set( - a_uint32_t dev_id, - a_uint32_t index, - union ac_grp_drop_state_tbl_u *value); - -sw_error_t -hppe_oq_enq_opr_tbl_get( - a_uint32_t dev_id, - a_uint32_t index, - union oq_enq_opr_tbl_u *value); - -sw_error_t -hppe_oq_enq_opr_tbl_set( - a_uint32_t dev_id, - a_uint32_t index, - union oq_enq_opr_tbl_u *value); - -sw_error_t -hppe_oq_deq_opr_tbl_get( - a_uint32_t dev_id, - a_uint32_t index, - union oq_deq_opr_tbl_u *value); - -sw_error_t -hppe_oq_deq_opr_tbl_set( - a_uint32_t dev_id, - a_uint32_t index, - union oq_deq_opr_tbl_u *value); - -sw_error_t -hppe_oq_head_uni_tbl_get( - a_uint32_t dev_id, - a_uint32_t index, - union oq_head_uni_tbl_u *value); - -sw_error_t -hppe_oq_head_uni_tbl_set( - a_uint32_t dev_id, - a_uint32_t index, - union oq_head_uni_tbl_u *value); - -sw_error_t -hppe_oq_head_mul_tbl_get( - a_uint32_t dev_id, - a_uint32_t index, - union oq_head_mul_tbl_u *value); - -sw_error_t -hppe_oq_head_mul_tbl_set( - a_uint32_t dev_id, - a_uint32_t index, - union oq_head_mul_tbl_u *value); - -sw_error_t -hppe_oq_ll_uni_tbl_get( - a_uint32_t dev_id, - a_uint32_t index, - union oq_ll_uni_tbl_u *value); - -sw_error_t -hppe_oq_ll_uni_tbl_set( - a_uint32_t dev_id, - a_uint32_t index, - union oq_ll_uni_tbl_u *value); - -sw_error_t -hppe_oq_ll_mul_p0_tbl_get( - a_uint32_t dev_id, - a_uint32_t index, - union oq_ll_mul_p0_tbl_u *value); - -sw_error_t -hppe_oq_ll_mul_p0_tbl_set( - a_uint32_t dev_id, - a_uint32_t index, - union oq_ll_mul_p0_tbl_u *value); - -sw_error_t -hppe_oq_ll_mul_p1_tbl_get( - a_uint32_t dev_id, - a_uint32_t index, - union oq_ll_mul_p1_tbl_u *value); - -sw_error_t -hppe_oq_ll_mul_p1_tbl_set( - a_uint32_t dev_id, - a_uint32_t index, - union oq_ll_mul_p1_tbl_u *value); - -sw_error_t -hppe_oq_ll_mul_p2_tbl_get( - a_uint32_t dev_id, - a_uint32_t index, - union oq_ll_mul_p2_tbl_u *value); - -sw_error_t -hppe_oq_ll_mul_p2_tbl_set( - a_uint32_t dev_id, - a_uint32_t index, - union oq_ll_mul_p2_tbl_u *value); - -sw_error_t -hppe_oq_ll_mul_p3_tbl_get( - a_uint32_t dev_id, - a_uint32_t index, - union oq_ll_mul_p3_tbl_u *value); - -sw_error_t -hppe_oq_ll_mul_p3_tbl_set( - a_uint32_t dev_id, - a_uint32_t index, - union oq_ll_mul_p3_tbl_u *value); - -sw_error_t -hppe_oq_ll_mul_p4_tbl_get( - a_uint32_t dev_id, - a_uint32_t index, - union oq_ll_mul_p4_tbl_u *value); - -sw_error_t -hppe_oq_ll_mul_p4_tbl_set( - a_uint32_t dev_id, - a_uint32_t index, - union oq_ll_mul_p4_tbl_u *value); - -sw_error_t -hppe_oq_ll_mul_p5_tbl_get( - a_uint32_t dev_id, - a_uint32_t index, - union oq_ll_mul_p5_tbl_u *value); - -sw_error_t -hppe_oq_ll_mul_p5_tbl_set( - a_uint32_t dev_id, - a_uint32_t index, - union oq_ll_mul_p5_tbl_u *value); - -sw_error_t -hppe_oq_ll_mul_p6_tbl_get( - a_uint32_t dev_id, - a_uint32_t index, - union oq_ll_mul_p6_tbl_u *value); - -sw_error_t -hppe_oq_ll_mul_p6_tbl_set( - a_uint32_t dev_id, - a_uint32_t index, - union oq_ll_mul_p6_tbl_u *value); - -sw_error_t -hppe_oq_ll_mul_p7_tbl_get( - a_uint32_t dev_id, - a_uint32_t index, - union oq_ll_mul_p7_tbl_u *value); - -sw_error_t -hppe_oq_ll_mul_p7_tbl_set( - a_uint32_t dev_id, - a_uint32_t index, - union oq_ll_mul_p7_tbl_u *value); - -sw_error_t -hppe_pkt_desp_tbl_get( - a_uint32_t dev_id, - a_uint32_t index, - union pkt_desp_tbl_u *value); - -sw_error_t -hppe_pkt_desp_tbl_set( - a_uint32_t dev_id, - a_uint32_t index, - union pkt_desp_tbl_u *value); - -sw_error_t -hppe_uni_drop_cnt_tbl_get( - a_uint32_t dev_id, - a_uint32_t index, - union uni_drop_cnt_tbl_u *value); - -sw_error_t -hppe_uni_drop_cnt_tbl_set( - a_uint32_t dev_id, - a_uint32_t index, - union uni_drop_cnt_tbl_u *value); - -sw_error_t -hppe_mul_p0_drop_cnt_tbl_get( - a_uint32_t dev_id, - a_uint32_t index, - union mul_p0_drop_cnt_tbl_u *value); - -sw_error_t -hppe_mul_p0_drop_cnt_tbl_set( - a_uint32_t dev_id, - a_uint32_t index, - union mul_p0_drop_cnt_tbl_u *value); - -sw_error_t -hppe_mul_p1_drop_cnt_tbl_get( - a_uint32_t dev_id, - a_uint32_t index, - union mul_p1_drop_cnt_tbl_u *value); - -sw_error_t -hppe_mul_p1_drop_cnt_tbl_set( - a_uint32_t dev_id, - a_uint32_t index, - union mul_p1_drop_cnt_tbl_u *value); - -sw_error_t -hppe_mul_p2_drop_cnt_tbl_get( - a_uint32_t dev_id, - a_uint32_t index, - union mul_p2_drop_cnt_tbl_u *value); - -sw_error_t -hppe_mul_p2_drop_cnt_tbl_set( - a_uint32_t dev_id, - a_uint32_t index, - union mul_p2_drop_cnt_tbl_u *value); - -sw_error_t -hppe_mul_p3_drop_cnt_tbl_get( - a_uint32_t dev_id, - a_uint32_t index, - union mul_p3_drop_cnt_tbl_u *value); - -sw_error_t -hppe_mul_p3_drop_cnt_tbl_set( - a_uint32_t dev_id, - a_uint32_t index, - union mul_p3_drop_cnt_tbl_u *value); - -sw_error_t -hppe_mul_p4_drop_cnt_tbl_get( - a_uint32_t dev_id, - a_uint32_t index, - union mul_p4_drop_cnt_tbl_u *value); - -sw_error_t -hppe_mul_p4_drop_cnt_tbl_set( - a_uint32_t dev_id, - a_uint32_t index, - union mul_p4_drop_cnt_tbl_u *value); - -sw_error_t -hppe_mul_p5_drop_cnt_tbl_get( - a_uint32_t dev_id, - a_uint32_t index, - union mul_p5_drop_cnt_tbl_u *value); - -sw_error_t -hppe_mul_p5_drop_cnt_tbl_set( - a_uint32_t dev_id, - a_uint32_t index, - union mul_p5_drop_cnt_tbl_u *value); - -sw_error_t -hppe_mul_p6_drop_cnt_tbl_get( - a_uint32_t dev_id, - a_uint32_t index, - union mul_p6_drop_cnt_tbl_u *value); - -sw_error_t -hppe_mul_p6_drop_cnt_tbl_set( - a_uint32_t dev_id, - a_uint32_t index, - union mul_p6_drop_cnt_tbl_u *value); - -sw_error_t -hppe_mul_p7_drop_cnt_tbl_get( - a_uint32_t dev_id, - a_uint32_t index, - union mul_p7_drop_cnt_tbl_u *value); - -sw_error_t -hppe_mul_p7_drop_cnt_tbl_set( - a_uint32_t dev_id, - a_uint32_t index, - union mul_p7_drop_cnt_tbl_u *value); - -sw_error_t -hppe_uq_agg_profile_map_get( - a_uint32_t dev_id, - a_uint32_t index, - union uq_agg_profile_map_u *value); - -sw_error_t -hppe_uq_agg_profile_map_set( - a_uint32_t dev_id, - a_uint32_t index, - union uq_agg_profile_map_u *value); - -sw_error_t -hppe_flush_cfg_flush_busy_get( - a_uint32_t dev_id, - unsigned int *value); - -sw_error_t -hppe_flush_cfg_flush_busy_set( - a_uint32_t dev_id, - unsigned int value); - -sw_error_t -hppe_flush_cfg_flush_qid_get( - a_uint32_t dev_id, - unsigned int *value); - -sw_error_t -hppe_flush_cfg_flush_qid_set( - a_uint32_t dev_id, - unsigned int value); - -sw_error_t -hppe_flush_cfg_flush_dst_port_get( - a_uint32_t dev_id, - unsigned int *value); - -sw_error_t -hppe_flush_cfg_flush_dst_port_set( - a_uint32_t dev_id, - unsigned int value); - -sw_error_t -hppe_flush_cfg_flush_all_queues_get( - a_uint32_t dev_id, - unsigned int *value); - -sw_error_t -hppe_flush_cfg_flush_all_queues_set( - a_uint32_t dev_id, - unsigned int value); - -sw_error_t -hppe_flush_cfg_flush_wt_time_get( - a_uint32_t dev_id, - unsigned int *value); - -sw_error_t -hppe_flush_cfg_flush_wt_time_set( - a_uint32_t dev_id, - unsigned int value); - -sw_error_t -hppe_flush_cfg_flush_status_get( - a_uint32_t dev_id, - unsigned int *value); - -sw_error_t -hppe_flush_cfg_flush_status_set( - a_uint32_t dev_id, - unsigned int value); - -sw_error_t -hppe_in_mirror_priority_ctrl_priority_get( - a_uint32_t dev_id, - unsigned int *value); - -sw_error_t -hppe_in_mirror_priority_ctrl_priority_set( - a_uint32_t dev_id, - unsigned int value); - -sw_error_t -hppe_eg_mirror_priority_ctrl_priority_get( - a_uint32_t dev_id, - unsigned int *value); - -sw_error_t -hppe_eg_mirror_priority_ctrl_priority_set( - a_uint32_t dev_id, - unsigned int value); - -sw_error_t -hppe_ucast_default_hash_hash_get( - a_uint32_t dev_id, - unsigned int *value); - -sw_error_t -hppe_ucast_default_hash_hash_set( - a_uint32_t dev_id, - unsigned int value); - -sw_error_t -hppe_spare_reg0_spare_reg0_get( - a_uint32_t dev_id, - unsigned int *value); - -sw_error_t -hppe_spare_reg0_spare_reg0_set( - a_uint32_t dev_id, - unsigned int value); - -sw_error_t -hppe_spare_reg1_spare_reg1_get( - a_uint32_t dev_id, - unsigned int *value); - -sw_error_t -hppe_spare_reg1_spare_reg1_set( - a_uint32_t dev_id, - unsigned int value); - -sw_error_t -hppe_qm_dbg_addr_dbg_addr_get( - a_uint32_t dev_id, - unsigned int *value); - -sw_error_t -hppe_qm_dbg_addr_dbg_addr_set( - a_uint32_t dev_id, - unsigned int value); - -sw_error_t -hppe_qm_dbg_data_dbg_data_get( - a_uint32_t dev_id, - unsigned int *value); - -sw_error_t -hppe_qm_dbg_data_dbg_data_set( - a_uint32_t dev_id, - unsigned int value); - -sw_error_t -hppe_mcast_priority_map0_class_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_mcast_priority_map0_class_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_mcast_priority_map1_class_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_mcast_priority_map1_class_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_mcast_priority_map2_class_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_mcast_priority_map2_class_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_mcast_priority_map3_class_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_mcast_priority_map3_class_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_mcast_priority_map4_class_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_mcast_priority_map4_class_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_mcast_priority_map5_class_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_mcast_priority_map5_class_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_mcast_priority_map6_class_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_mcast_priority_map6_class_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_mcast_priority_map7_class_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_mcast_priority_map7_class_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_agg_profile_cnt_en_mq_p2_en_get( - a_uint32_t dev_id, - unsigned int *value); - -sw_error_t -hppe_agg_profile_cnt_en_mq_p2_en_set( - a_uint32_t dev_id, - unsigned int value); - -sw_error_t -hppe_agg_profile_cnt_en_uq_en_1_get( - a_uint32_t dev_id, - unsigned int *value); - -sw_error_t -hppe_agg_profile_cnt_en_uq_en_1_set( - a_uint32_t dev_id, - unsigned int value); - -sw_error_t -hppe_agg_profile_cnt_en_mq_p0_en_get( - a_uint32_t dev_id, - unsigned int *value); - -sw_error_t -hppe_agg_profile_cnt_en_mq_p0_en_set( - a_uint32_t dev_id, - unsigned int value); - -sw_error_t -hppe_agg_profile_cnt_en_grp_1_en_get( - a_uint32_t dev_id, - unsigned int *value); - -sw_error_t -hppe_agg_profile_cnt_en_grp_1_en_set( - a_uint32_t dev_id, - unsigned int value); - -sw_error_t -hppe_agg_profile_cnt_en_grp_0_en_get( - a_uint32_t dev_id, - unsigned int *value); - -sw_error_t -hppe_agg_profile_cnt_en_grp_0_en_set( - a_uint32_t dev_id, - unsigned int value); - -sw_error_t -hppe_agg_profile_cnt_en_mq_p6_en_get( - a_uint32_t dev_id, - unsigned int *value); - -sw_error_t -hppe_agg_profile_cnt_en_mq_p6_en_set( - a_uint32_t dev_id, - unsigned int value); - -sw_error_t -hppe_agg_profile_cnt_en_uq_en_3_get( - a_uint32_t dev_id, - unsigned int *value); - -sw_error_t -hppe_agg_profile_cnt_en_uq_en_3_set( - a_uint32_t dev_id, - unsigned int value); - -sw_error_t -hppe_agg_profile_cnt_en_mq_p4_en_get( - a_uint32_t dev_id, - unsigned int *value); - -sw_error_t -hppe_agg_profile_cnt_en_mq_p4_en_set( - a_uint32_t dev_id, - unsigned int value); - -sw_error_t -hppe_agg_profile_cnt_en_uq_en_2_get( - a_uint32_t dev_id, - unsigned int *value); - -sw_error_t -hppe_agg_profile_cnt_en_uq_en_2_set( - a_uint32_t dev_id, - unsigned int value); - -sw_error_t -hppe_agg_profile_cnt_en_uq_en_5_get( - a_uint32_t dev_id, - unsigned int *value); - -sw_error_t -hppe_agg_profile_cnt_en_uq_en_5_set( - a_uint32_t dev_id, - unsigned int value); - -sw_error_t -hppe_agg_profile_cnt_en_uq_en_6_get( - a_uint32_t dev_id, - unsigned int *value); - -sw_error_t -hppe_agg_profile_cnt_en_uq_en_6_set( - a_uint32_t dev_id, - unsigned int value); - -sw_error_t -hppe_agg_profile_cnt_en_grp_3_en_get( - a_uint32_t dev_id, - unsigned int *value); - -sw_error_t -hppe_agg_profile_cnt_en_grp_3_en_set( - a_uint32_t dev_id, - unsigned int value); - -sw_error_t -hppe_agg_profile_cnt_en_grp_2_en_get( - a_uint32_t dev_id, - unsigned int *value); - -sw_error_t -hppe_agg_profile_cnt_en_grp_2_en_set( - a_uint32_t dev_id, - unsigned int value); - -sw_error_t -hppe_agg_profile_cnt_en_uq_en_4_get( - a_uint32_t dev_id, - unsigned int *value); - -sw_error_t -hppe_agg_profile_cnt_en_uq_en_4_set( - a_uint32_t dev_id, - unsigned int value); - -sw_error_t -hppe_agg_profile_cnt_en_mq_p7_en_get( - a_uint32_t dev_id, - unsigned int *value); - -sw_error_t -hppe_agg_profile_cnt_en_mq_p7_en_set( - a_uint32_t dev_id, - unsigned int value); - -sw_error_t -hppe_agg_profile_cnt_en_uq_en_7_get( - a_uint32_t dev_id, - unsigned int *value); - -sw_error_t -hppe_agg_profile_cnt_en_uq_en_7_set( - a_uint32_t dev_id, - unsigned int value); - -sw_error_t -hppe_agg_profile_cnt_en_global_en_get( - a_uint32_t dev_id, - unsigned int *value); - -sw_error_t -hppe_agg_profile_cnt_en_global_en_set( - a_uint32_t dev_id, - unsigned int value); - -sw_error_t -hppe_agg_profile_cnt_en_mq_p5_en_get( - a_uint32_t dev_id, - unsigned int *value); - -sw_error_t -hppe_agg_profile_cnt_en_mq_p5_en_set( - a_uint32_t dev_id, - unsigned int value); - -sw_error_t -hppe_agg_profile_cnt_en_mq_p1_en_get( - a_uint32_t dev_id, - unsigned int *value); - -sw_error_t -hppe_agg_profile_cnt_en_mq_p1_en_set( - a_uint32_t dev_id, - unsigned int value); - -sw_error_t -hppe_agg_profile_cnt_en_uq_en_0_get( - a_uint32_t dev_id, - unsigned int *value); - -sw_error_t -hppe_agg_profile_cnt_en_uq_en_0_set( - a_uint32_t dev_id, - unsigned int value); - -sw_error_t -hppe_agg_profile_cnt_en_mq_p3_en_get( - a_uint32_t dev_id, - unsigned int *value); - -sw_error_t -hppe_agg_profile_cnt_en_mq_p3_en_set( - a_uint32_t dev_id, - unsigned int value); - -sw_error_t -hppe_uq_agg_profile_cfg_th_cfg_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_uq_agg_profile_cfg_th_cfg_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_mq_agg_profile_cfg_th_cfg_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_mq_agg_profile_cfg_th_cfg_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_grp_agg_profile_cfg_th_cfg_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_grp_agg_profile_cfg_th_cfg_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_uq_agg_in_profile_cnt_cnt_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_uq_agg_in_profile_cnt_cnt_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_uq_agg_out_profile_cnt_cnt_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_uq_agg_out_profile_cnt_cnt_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_mq_agg_in_profile_cnt_cnt_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_mq_agg_in_profile_cnt_cnt_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_mq_agg_out_profile_cnt_cnt_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_mq_agg_out_profile_cnt_cnt_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_grp_agg_in_profile_cnt_cnt_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_grp_agg_in_profile_cnt_cnt_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_grp_agg_out_profile_cnt_cnt_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_grp_agg_out_profile_cnt_cnt_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_ucast_queue_map_tbl_profile_id_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_ucast_queue_map_tbl_profile_id_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_ucast_queue_map_tbl_queue_id_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_ucast_queue_map_tbl_queue_id_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_ucast_hash_map_tbl_hash_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_ucast_hash_map_tbl_hash_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_ucast_priority_map_tbl_class_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_ucast_priority_map_tbl_class_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_mcast_queue_map_tbl_class_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_mcast_queue_map_tbl_class_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_ac_mseq_tbl_ac_mseq_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_ac_mseq_tbl_ac_mseq_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_ac_uni_queue_cfg_tbl_ac_cfg_gap_grn_yel_max_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_ac_uni_queue_cfg_tbl_ac_cfg_gap_grn_yel_max_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_ac_uni_queue_cfg_tbl_ac_cfg_wred_en_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_ac_uni_queue_cfg_tbl_ac_cfg_wred_en_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_ac_uni_queue_cfg_tbl_ac_cfg_ac_en_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_ac_uni_queue_cfg_tbl_ac_cfg_ac_en_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_ac_uni_queue_cfg_tbl_ac_cfg_red_resume_offset_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_ac_uni_queue_cfg_tbl_ac_cfg_red_resume_offset_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_ac_uni_queue_cfg_tbl_ac_cfg_grp_id_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_ac_uni_queue_cfg_tbl_ac_cfg_grp_id_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_ac_uni_queue_cfg_tbl_ac_cfg_color_aware_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_ac_uni_queue_cfg_tbl_ac_cfg_color_aware_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_ac_uni_queue_cfg_tbl_ac_cfg_yel_resume_offset_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_ac_uni_queue_cfg_tbl_ac_cfg_yel_resume_offset_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_ac_uni_queue_cfg_tbl_ac_cfg_gap_grn_yel_min_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_ac_uni_queue_cfg_tbl_ac_cfg_gap_grn_yel_min_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_ac_uni_queue_cfg_tbl_ac_cfg_shared_weight_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_ac_uni_queue_cfg_tbl_ac_cfg_shared_weight_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_ac_uni_queue_cfg_tbl_ac_cfg_shared_dynamic_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_ac_uni_queue_cfg_tbl_ac_cfg_shared_dynamic_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_ac_uni_queue_cfg_tbl_ac_cfg_gap_grn_red_max_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_ac_uni_queue_cfg_tbl_ac_cfg_gap_grn_red_max_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_ac_uni_queue_cfg_tbl_ac_cfg_pre_alloc_limit_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_ac_uni_queue_cfg_tbl_ac_cfg_pre_alloc_limit_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_ac_uni_queue_cfg_tbl_ac_cfg_force_ac_en_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_ac_uni_queue_cfg_tbl_ac_cfg_force_ac_en_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_ac_uni_queue_cfg_tbl_ac_cfg_gap_grn_red_min_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_ac_uni_queue_cfg_tbl_ac_cfg_gap_grn_red_min_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_ac_uni_queue_cfg_tbl_ac_cfg_gap_grn_grn_min_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_ac_uni_queue_cfg_tbl_ac_cfg_gap_grn_grn_min_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_ac_uni_queue_cfg_tbl_ac_cfg_shared_ceiling_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_ac_uni_queue_cfg_tbl_ac_cfg_shared_ceiling_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_ac_uni_queue_cfg_tbl_ac_cfg_grn_resume_offset_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_ac_uni_queue_cfg_tbl_ac_cfg_grn_resume_offset_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_ac_mul_queue_cfg_tbl_ac_cfg_ac_en_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_ac_mul_queue_cfg_tbl_ac_cfg_ac_en_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_ac_mul_queue_cfg_tbl_ac_cfg_red_resume_offset_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_ac_mul_queue_cfg_tbl_ac_cfg_red_resume_offset_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_ac_mul_queue_cfg_tbl_ac_cfg_grp_id_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_ac_mul_queue_cfg_tbl_ac_cfg_grp_id_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_ac_mul_queue_cfg_tbl_ac_cfg_color_aware_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_ac_mul_queue_cfg_tbl_ac_cfg_color_aware_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_ac_mul_queue_cfg_tbl_ac_cfg_yel_resume_offset_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_ac_mul_queue_cfg_tbl_ac_cfg_yel_resume_offset_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_ac_mul_queue_cfg_tbl_ac_cfg_pre_alloc_limit_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_ac_mul_queue_cfg_tbl_ac_cfg_pre_alloc_limit_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_ac_mul_queue_cfg_tbl_ac_cfg_force_ac_en_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_ac_mul_queue_cfg_tbl_ac_cfg_force_ac_en_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_ac_mul_queue_cfg_tbl_ac_cfg_shared_ceiling_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_ac_mul_queue_cfg_tbl_ac_cfg_shared_ceiling_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_ac_mul_queue_cfg_tbl_ac_cfg_grn_resume_offset_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_ac_mul_queue_cfg_tbl_ac_cfg_grn_resume_offset_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_ac_mul_queue_cfg_tbl_ac_cfg_gap_grn_yel_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_ac_mul_queue_cfg_tbl_ac_cfg_gap_grn_yel_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_ac_mul_queue_cfg_tbl_ac_cfg_gap_grn_red_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_ac_mul_queue_cfg_tbl_ac_cfg_gap_grn_red_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_ac_grp_cfg_tbl_ac_grp_grn_resume_offset_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_ac_grp_cfg_tbl_ac_grp_grn_resume_offset_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_ac_grp_cfg_tbl_ac_grp_dp_thrd_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_ac_grp_cfg_tbl_ac_grp_dp_thrd_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_ac_grp_cfg_tbl_ac_cfg_ac_en_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_ac_grp_cfg_tbl_ac_cfg_ac_en_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_ac_grp_cfg_tbl_ac_grp_palloc_limit_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_ac_grp_cfg_tbl_ac_grp_palloc_limit_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_ac_grp_cfg_tbl_ac_cfg_color_aware_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_ac_grp_cfg_tbl_ac_cfg_color_aware_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_ac_grp_cfg_tbl_ac_grp_red_resume_offset_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_ac_grp_cfg_tbl_ac_grp_red_resume_offset_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_ac_grp_cfg_tbl_ac_grp_gap_grn_yel_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_ac_grp_cfg_tbl_ac_grp_gap_grn_yel_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_ac_grp_cfg_tbl_ac_cfg_force_ac_en_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_ac_grp_cfg_tbl_ac_cfg_force_ac_en_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_ac_grp_cfg_tbl_ac_grp_yel_resume_offset_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_ac_grp_cfg_tbl_ac_grp_yel_resume_offset_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_ac_grp_cfg_tbl_ac_grp_gap_grn_red_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_ac_grp_cfg_tbl_ac_grp_gap_grn_red_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_ac_grp_cfg_tbl_ac_grp_limit_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_ac_grp_cfg_tbl_ac_grp_limit_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_ac_uni_queue_cnt_tbl_ac_uni_queue_cnt_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_ac_uni_queue_cnt_tbl_ac_uni_queue_cnt_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_ac_mul_queue_cnt_tbl_ac_mul_queue_cnt_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_ac_mul_queue_cnt_tbl_ac_mul_queue_cnt_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_ac_grp_cnt_tbl_ac_grp_alloc_used_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_ac_grp_cnt_tbl_ac_grp_alloc_used_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_ac_grp_cnt_tbl_ac_grp_cnt_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_ac_grp_cnt_tbl_ac_grp_cnt_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_ac_uni_queue_drop_state_tbl_red_resume_thrd_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_ac_uni_queue_drop_state_tbl_red_resume_thrd_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_ac_uni_queue_drop_state_tbl_red_drop_state_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_ac_uni_queue_drop_state_tbl_red_drop_state_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_ac_uni_queue_drop_state_tbl_yel_resume_thrd_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_ac_uni_queue_drop_state_tbl_yel_resume_thrd_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_ac_uni_queue_drop_state_tbl_grn_drop_state_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_ac_uni_queue_drop_state_tbl_grn_drop_state_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_ac_uni_queue_drop_state_tbl_yel_drop_state_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_ac_uni_queue_drop_state_tbl_yel_drop_state_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_ac_uni_queue_drop_state_tbl_grn_resume_thrd_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_ac_uni_queue_drop_state_tbl_grn_resume_thrd_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_ac_mul_queue_drop_state_tbl_red_resume_thrd_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_ac_mul_queue_drop_state_tbl_red_resume_thrd_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_ac_mul_queue_drop_state_tbl_red_drop_state_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_ac_mul_queue_drop_state_tbl_red_drop_state_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_ac_mul_queue_drop_state_tbl_yel_resume_thrd_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_ac_mul_queue_drop_state_tbl_yel_resume_thrd_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_ac_mul_queue_drop_state_tbl_grn_drop_state_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_ac_mul_queue_drop_state_tbl_grn_drop_state_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_ac_mul_queue_drop_state_tbl_yel_drop_state_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_ac_mul_queue_drop_state_tbl_yel_drop_state_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_ac_mul_queue_drop_state_tbl_grn_resume_thrd_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_ac_mul_queue_drop_state_tbl_grn_resume_thrd_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_ac_grp_drop_state_tbl_red_resume_thrd_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_ac_grp_drop_state_tbl_red_resume_thrd_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_ac_grp_drop_state_tbl_red_drop_state_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_ac_grp_drop_state_tbl_red_drop_state_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_ac_grp_drop_state_tbl_yel_resume_thrd_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_ac_grp_drop_state_tbl_yel_resume_thrd_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_ac_grp_drop_state_tbl_grn_drop_state_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_ac_grp_drop_state_tbl_grn_drop_state_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_ac_grp_drop_state_tbl_yel_drop_state_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_ac_grp_drop_state_tbl_yel_drop_state_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_ac_grp_drop_state_tbl_grn_resume_thrd_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_ac_grp_drop_state_tbl_grn_resume_thrd_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_oq_enq_opr_tbl_enq_disable_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_oq_enq_opr_tbl_enq_disable_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_oq_deq_opr_tbl_deq_drop_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_oq_deq_opr_tbl_deq_drop_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_oq_head_uni_tbl_head_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_oq_head_uni_tbl_head_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_oq_head_uni_tbl_tail_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_oq_head_uni_tbl_tail_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_oq_head_uni_tbl_empty_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_oq_head_uni_tbl_empty_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_oq_head_mul_tbl_head_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_oq_head_mul_tbl_head_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_oq_head_mul_tbl_tail_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_oq_head_mul_tbl_tail_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_oq_head_mul_tbl_ingress_mirr_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_oq_head_mul_tbl_ingress_mirr_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_oq_head_mul_tbl_empty_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_oq_head_mul_tbl_empty_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_oq_head_mul_tbl_egress_mirr_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_oq_head_mul_tbl_egress_mirr_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_oq_head_mul_tbl_normal_fwd_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_oq_head_mul_tbl_normal_fwd_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_oq_ll_uni_tbl_next_pointer_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_oq_ll_uni_tbl_next_pointer_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_oq_ll_mul_p0_tbl_next_pointer_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_oq_ll_mul_p0_tbl_next_pointer_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_oq_ll_mul_p0_tbl_ingress_mirr_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_oq_ll_mul_p0_tbl_ingress_mirr_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_oq_ll_mul_p0_tbl_egress_mirr_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_oq_ll_mul_p0_tbl_egress_mirr_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_oq_ll_mul_p0_tbl_normal_fwd_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_oq_ll_mul_p0_tbl_normal_fwd_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_oq_ll_mul_p1_tbl_next_pointer_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_oq_ll_mul_p1_tbl_next_pointer_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_oq_ll_mul_p1_tbl_ingress_mirr_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_oq_ll_mul_p1_tbl_ingress_mirr_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_oq_ll_mul_p1_tbl_egress_mirr_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_oq_ll_mul_p1_tbl_egress_mirr_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_oq_ll_mul_p1_tbl_normal_fwd_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_oq_ll_mul_p1_tbl_normal_fwd_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_oq_ll_mul_p2_tbl_next_pointer_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_oq_ll_mul_p2_tbl_next_pointer_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_oq_ll_mul_p2_tbl_ingress_mirr_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_oq_ll_mul_p2_tbl_ingress_mirr_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_oq_ll_mul_p2_tbl_egress_mirr_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_oq_ll_mul_p2_tbl_egress_mirr_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_oq_ll_mul_p2_tbl_normal_fwd_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_oq_ll_mul_p2_tbl_normal_fwd_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_oq_ll_mul_p3_tbl_next_pointer_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_oq_ll_mul_p3_tbl_next_pointer_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_oq_ll_mul_p3_tbl_ingress_mirr_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_oq_ll_mul_p3_tbl_ingress_mirr_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_oq_ll_mul_p3_tbl_egress_mirr_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_oq_ll_mul_p3_tbl_egress_mirr_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_oq_ll_mul_p3_tbl_normal_fwd_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_oq_ll_mul_p3_tbl_normal_fwd_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_oq_ll_mul_p4_tbl_next_pointer_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_oq_ll_mul_p4_tbl_next_pointer_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_oq_ll_mul_p4_tbl_ingress_mirr_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_oq_ll_mul_p4_tbl_ingress_mirr_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_oq_ll_mul_p4_tbl_egress_mirr_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_oq_ll_mul_p4_tbl_egress_mirr_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_oq_ll_mul_p4_tbl_normal_fwd_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_oq_ll_mul_p4_tbl_normal_fwd_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_oq_ll_mul_p5_tbl_next_pointer_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_oq_ll_mul_p5_tbl_next_pointer_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_oq_ll_mul_p5_tbl_ingress_mirr_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_oq_ll_mul_p5_tbl_ingress_mirr_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_oq_ll_mul_p5_tbl_egress_mirr_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_oq_ll_mul_p5_tbl_egress_mirr_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_oq_ll_mul_p5_tbl_normal_fwd_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_oq_ll_mul_p5_tbl_normal_fwd_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_oq_ll_mul_p6_tbl_next_pointer_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_oq_ll_mul_p6_tbl_next_pointer_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_oq_ll_mul_p6_tbl_ingress_mirr_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_oq_ll_mul_p6_tbl_ingress_mirr_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_oq_ll_mul_p6_tbl_egress_mirr_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_oq_ll_mul_p6_tbl_egress_mirr_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_oq_ll_mul_p6_tbl_normal_fwd_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_oq_ll_mul_p6_tbl_normal_fwd_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_oq_ll_mul_p7_tbl_next_pointer_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_oq_ll_mul_p7_tbl_next_pointer_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_oq_ll_mul_p7_tbl_ingress_mirr_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_oq_ll_mul_p7_tbl_ingress_mirr_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_oq_ll_mul_p7_tbl_egress_mirr_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_oq_ll_mul_p7_tbl_egress_mirr_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_oq_ll_mul_p7_tbl_normal_fwd_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_oq_ll_mul_p7_tbl_normal_fwd_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_pkt_desp_tbl_ip_addr_index_valid_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_pkt_desp_tbl_ip_addr_index_valid_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_pkt_desp_tbl_route_flag_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_pkt_desp_tbl_route_flag_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_pkt_desp_tbl_int_cpcp_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_pkt_desp_tbl_int_cpcp_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_pkt_desp_tbl_pkt_l3_edit_bypass_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_pkt_desp_tbl_pkt_l3_edit_bypass_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_pkt_desp_tbl_int_ctag_fmt_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_pkt_desp_tbl_int_ctag_fmt_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_pkt_desp_tbl_fake_mac_header_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_pkt_desp_tbl_fake_mac_header_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_pkt_desp_tbl_acl_index_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_pkt_desp_tbl_acl_index_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_pkt_desp_tbl_l4_type_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_pkt_desp_tbl_l4_type_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_pkt_desp_tbl_int_svid_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_pkt_desp_tbl_int_svid_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_pkt_desp_tbl_int_sdei_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_pkt_desp_tbl_int_sdei_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_pkt_desp_tbl_fc_en_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_pkt_desp_tbl_fc_en_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_pkt_desp_tbl_packet_length_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_pkt_desp_tbl_packet_length_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_pkt_desp_tbl_rx_ts_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint64_t *value); - -sw_error_t -hppe_pkt_desp_tbl_rx_ts_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint64_t value); - -sw_error_t -hppe_pkt_desp_tbl_ts_dir_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_pkt_desp_tbl_ts_dir_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_pkt_desp_tbl_chg_port_vp_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_pkt_desp_tbl_chg_port_vp_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_pkt_desp_tbl_int_pri_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_pkt_desp_tbl_int_pri_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_pkt_desp_tbl_one_enq_flag_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_pkt_desp_tbl_one_enq_flag_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_pkt_desp_tbl_fc_grp_id_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_pkt_desp_tbl_fc_grp_id_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_pkt_desp_tbl_fake_l2_prot_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_pkt_desp_tbl_fake_l2_prot_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_pkt_desp_tbl_org_src_port_vp_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_pkt_desp_tbl_org_src_port_vp_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_pkt_desp_tbl_hash_flag_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_pkt_desp_tbl_hash_flag_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_pkt_desp_tbl_int_stag_fmt_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_pkt_desp_tbl_int_stag_fmt_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_pkt_desp_tbl_service_code_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_pkt_desp_tbl_service_code_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_pkt_desp_tbl_rx_ptp_type_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_pkt_desp_tbl_rx_ptp_type_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_pkt_desp_tbl_mac_da_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint64_t *value); - -sw_error_t -hppe_pkt_desp_tbl_mac_da_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint64_t value); - -sw_error_t -hppe_pkt_desp_tbl_cpu_code_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_pkt_desp_tbl_cpu_code_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_pkt_desp_tbl_eg_vlan_tag_fmt_bypass_en_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_pkt_desp_tbl_eg_vlan_tag_fmt_bypass_en_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_pkt_desp_tbl_ip_addr_index_type_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_pkt_desp_tbl_ip_addr_index_type_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_pkt_desp_tbl_int_cvid_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_pkt_desp_tbl_int_cvid_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_pkt_desp_tbl_eg_vlan_xlt_bypass_en_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_pkt_desp_tbl_eg_vlan_xlt_bypass_en_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_pkt_desp_tbl_hash_value_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_pkt_desp_tbl_hash_value_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_pkt_desp_tbl_stag_flag_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_pkt_desp_tbl_stag_flag_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_pkt_desp_tbl_dst_l3_if_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_pkt_desp_tbl_dst_l3_if_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_pkt_desp_tbl_int_cdei_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_pkt_desp_tbl_int_cdei_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_pkt_desp_tbl_edma_vp_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_pkt_desp_tbl_edma_vp_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_pkt_desp_tbl_ac_group_bitmap_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_pkt_desp_tbl_ac_group_bitmap_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_pkt_desp_tbl_vp_tx_cnt_en_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_pkt_desp_tbl_vp_tx_cnt_en_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_pkt_desp_tbl_src_port_vp_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_pkt_desp_tbl_src_port_vp_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_pkt_desp_tbl_nat_action_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_pkt_desp_tbl_nat_action_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_pkt_desp_tbl_dscp_update_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_pkt_desp_tbl_dscp_update_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_pkt_desp_tbl_pppoe_strip_flag_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_pkt_desp_tbl_pppoe_strip_flag_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_pkt_desp_tbl_snap_flag_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_pkt_desp_tbl_snap_flag_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_pkt_desp_tbl_vsi_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_pkt_desp_tbl_vsi_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_pkt_desp_tbl_pkt_l2_edit_bypass_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_pkt_desp_tbl_pkt_l2_edit_bypass_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_pkt_desp_tbl_tx_ptp_tag_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_pkt_desp_tbl_tx_ptp_tag_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_pkt_desp_tbl_ip_addr_index_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_pkt_desp_tbl_ip_addr_index_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_pkt_desp_tbl_int_dp_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_pkt_desp_tbl_int_dp_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_pkt_desp_tbl_src_pn_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_pkt_desp_tbl_src_pn_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_pkt_desp_tbl_tx_ts_en_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_pkt_desp_tbl_tx_ts_en_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_pkt_desp_tbl_l4_offset_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_pkt_desp_tbl_l4_offset_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_pkt_desp_tbl_ttl_update_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_pkt_desp_tbl_ttl_update_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_pkt_desp_tbl_napt_port_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_pkt_desp_tbl_napt_port_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_pkt_desp_tbl_napt_addr_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_pkt_desp_tbl_napt_addr_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_pkt_desp_tbl_copy_cpu_flag_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_pkt_desp_tbl_copy_cpu_flag_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_pkt_desp_tbl_ttl_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_pkt_desp_tbl_ttl_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_pkt_desp_tbl_l3_offset_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_pkt_desp_tbl_l3_offset_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_pkt_desp_tbl_rsv0_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_pkt_desp_tbl_rsv0_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_pkt_desp_tbl_next_header_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_pkt_desp_tbl_next_header_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_pkt_desp_tbl_acl_index_valid_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_pkt_desp_tbl_acl_index_valid_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_pkt_desp_tbl_rx_ts_valid_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_pkt_desp_tbl_rx_ts_valid_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_pkt_desp_tbl_dscp_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_pkt_desp_tbl_dscp_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_pkt_desp_tbl_acl_index_toggle_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_pkt_desp_tbl_acl_index_toggle_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_pkt_desp_tbl_ctag_flag_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_pkt_desp_tbl_ctag_flag_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_pkt_desp_tbl_ip_addr_index_toggle_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_pkt_desp_tbl_ip_addr_index_toggle_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_pkt_desp_tbl_tx_os_correction_en_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_pkt_desp_tbl_tx_os_correction_en_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_pkt_desp_tbl_int_spcp_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_pkt_desp_tbl_int_spcp_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_pkt_desp_tbl_pppoe_flag_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_pkt_desp_tbl_pppoe_flag_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_pkt_desp_tbl_l3_type_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_pkt_desp_tbl_l3_type_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_pkt_desp_tbl_vsi_valid_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_pkt_desp_tbl_vsi_valid_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_uni_drop_cnt_tbl_uni_drop_byte_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint64_t *value); - -sw_error_t -hppe_uni_drop_cnt_tbl_uni_drop_byte_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint64_t value); - -sw_error_t -hppe_uni_drop_cnt_tbl_uni_drop_pkt_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_uni_drop_cnt_tbl_uni_drop_pkt_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_mul_p0_drop_cnt_tbl_mul_p0_drop_pkt_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_mul_p0_drop_cnt_tbl_mul_p0_drop_pkt_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_mul_p0_drop_cnt_tbl_mul_p0_drop_byte_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint64_t *value); - -sw_error_t -hppe_mul_p0_drop_cnt_tbl_mul_p0_drop_byte_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint64_t value); - -sw_error_t -hppe_mul_p1_drop_cnt_tbl_mul_p1_drop_byte_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint64_t *value); - -sw_error_t -hppe_mul_p1_drop_cnt_tbl_mul_p1_drop_byte_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint64_t value); - -sw_error_t -hppe_mul_p1_drop_cnt_tbl_mul_p1_drop_pkt_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_mul_p1_drop_cnt_tbl_mul_p1_drop_pkt_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_mul_p2_drop_cnt_tbl_mul_p2_drop_pkt_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_mul_p2_drop_cnt_tbl_mul_p2_drop_pkt_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_mul_p2_drop_cnt_tbl_mul_p2_drop_byte_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint64_t *value); - -sw_error_t -hppe_mul_p2_drop_cnt_tbl_mul_p2_drop_byte_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint64_t value); - -sw_error_t -hppe_mul_p3_drop_cnt_tbl_mul_p3_drop_pkt_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_mul_p3_drop_cnt_tbl_mul_p3_drop_pkt_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_mul_p3_drop_cnt_tbl_mul_p3_drop_byte_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint64_t *value); - -sw_error_t -hppe_mul_p3_drop_cnt_tbl_mul_p3_drop_byte_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint64_t value); - -sw_error_t -hppe_mul_p4_drop_cnt_tbl_mul_p4_drop_pkt_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_mul_p4_drop_cnt_tbl_mul_p4_drop_pkt_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_mul_p4_drop_cnt_tbl_mul_p4_drop_byte_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint64_t *value); - -sw_error_t -hppe_mul_p4_drop_cnt_tbl_mul_p4_drop_byte_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint64_t value); - -sw_error_t -hppe_mul_p5_drop_cnt_tbl_mul_p5_drop_byte_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint64_t *value); - -sw_error_t -hppe_mul_p5_drop_cnt_tbl_mul_p5_drop_byte_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint64_t value); - -sw_error_t -hppe_mul_p5_drop_cnt_tbl_mul_p5_drop_pkt_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_mul_p5_drop_cnt_tbl_mul_p5_drop_pkt_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_mul_p6_drop_cnt_tbl_mul_p6_drop_byte_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint64_t *value); - -sw_error_t -hppe_mul_p6_drop_cnt_tbl_mul_p6_drop_byte_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint64_t value); - -sw_error_t -hppe_mul_p6_drop_cnt_tbl_mul_p6_drop_pkt_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_mul_p6_drop_cnt_tbl_mul_p6_drop_pkt_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_mul_p7_drop_cnt_tbl_mul_p7_drop_pkt_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_mul_p7_drop_cnt_tbl_mul_p7_drop_pkt_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_mul_p7_drop_cnt_tbl_mul_p7_drop_byte_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint64_t *value); - -sw_error_t -hppe_mul_p7_drop_cnt_tbl_mul_p7_drop_byte_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint64_t value); - -sw_error_t -hppe_uq_agg_profile_map_qid_2_agg_id_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_uq_agg_profile_map_qid_2_agg_id_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_uq_agg_profile_map_enable_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_uq_agg_profile_map_enable_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_queue_tx_counter_tbl_tx_bytes_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint64_t *value); - -sw_error_t -hppe_queue_tx_counter_tbl_tx_bytes_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint64_t value); - -sw_error_t -hppe_queue_tx_counter_tbl_tx_packets_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_queue_tx_counter_tbl_tx_packets_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -#endif - diff --git a/feeds/ipq807x/qca-ssdk/src/include/hsl/hppe/hppe_qm_reg.h b/feeds/ipq807x/qca-ssdk/src/include/hsl/hppe/hppe_qm_reg.h deleted file mode 100755 index 504d3c2d0..000000000 --- a/feeds/ipq807x/qca-ssdk/src/include/hsl/hppe/hppe_qm_reg.h +++ /dev/null @@ -1,2748 +0,0 @@ -/* - * Copyright (c) 2016-2017, The Linux Foundation. All rights reserved. - * Permission to use, copy, modify, and/or distribute this software for - * any purpose with or without fee is hereby granted, provided that the - * above copyright notice and this permission notice appear in all copies. - * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES - * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR - * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES - * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN - * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT - * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. - */ - - -/** - * @defgroup - * @{ - */ -#ifndef HPPE_QM_REG_H -#define HPPE_QM_REG_H - -/*[register] FLUSH_CFG*/ -#define FLUSH_CFG -#define FLUSH_CFG_ADDRESS 0x0 -#define FLUSH_CFG_NUM 1 -#define FLUSH_CFG_INC 0x4 -#define FLUSH_CFG_TYPE REG_TYPE_RW -#define FLUSH_CFG_DEFAULT 0x80000 - /*[field] FLUSH_QID*/ - #define FLUSH_CFG_FLUSH_QID - #define FLUSH_CFG_FLUSH_QID_OFFSET 0 - #define FLUSH_CFG_FLUSH_QID_LEN 9 - #define FLUSH_CFG_FLUSH_QID_DEFAULT 0x0 - /*[field] FLUSH_STATUS*/ - #define FLUSH_CFG_FLUSH_STATUS - #define FLUSH_CFG_FLUSH_STATUS_OFFSET 10 - #define FLUSH_CFG_FLUSH_STATUS_LEN 1 - #define FLUSH_CFG_FLUSH_STATUS_DEFAULT 0x0 - /*[field] FLUSH_WT_TIME*/ - #define FLUSH_CFG_FLUSH_WT_TIME - #define FLUSH_CFG_FLUSH_WT_TIME_OFFSET 11 - #define FLUSH_CFG_FLUSH_WT_TIME_LEN 10 - #define FLUSH_CFG_FLUSH_WT_TIME_DEFAULT 0x100 - /*[field] FLUSH_DST_PORT*/ - #define FLUSH_CFG_FLUSH_DST_PORT - #define FLUSH_CFG_FLUSH_DST_PORT_OFFSET 21 - #define FLUSH_CFG_FLUSH_DST_PORT_LEN 3 - #define FLUSH_CFG_FLUSH_DST_PORT_DEFAULT 0x0 - /*[field] FLUSH_ALL_QUEUES*/ - #define FLUSH_CFG_FLUSH_ALL_QUEUES - #define FLUSH_CFG_FLUSH_ALL_QUEUES_OFFSET 24 - #define FLUSH_CFG_FLUSH_ALL_QUEUES_LEN 1 - #define FLUSH_CFG_FLUSH_ALL_QUEUES_DEFAULT 0x0 - /*[field] FLUSH_BUSY*/ - #define FLUSH_CFG_FLUSH_BUSY - #define FLUSH_CFG_FLUSH_BUSY_OFFSET 31 - #define FLUSH_CFG_FLUSH_BUSY_LEN 1 - #define FLUSH_CFG_FLUSH_BUSY_DEFAULT 0x0 - -struct flush_cfg { - a_uint32_t flush_qid:9; - a_uint32_t _reserved0:1; - a_uint32_t flush_status:1; - a_uint32_t flush_wt_time:10; - a_uint32_t flush_dst_port:3; - a_uint32_t flush_all_queues:1; - a_uint32_t _reserved1:6; - a_uint32_t flush_busy:1; -}; - -union flush_cfg_u { - a_uint32_t val; - struct flush_cfg bf; -}; - -/*[register] IN_MIRROR_PRIORITY_CTRL*/ -#define IN_MIRROR_PRIORITY_CTRL -#define IN_MIRROR_PRIORITY_CTRL_ADDRESS 0x4 -#define IN_MIRROR_PRIORITY_CTRL_NUM 1 -#define IN_MIRROR_PRIORITY_CTRL_INC 0x4 -#define IN_MIRROR_PRIORITY_CTRL_TYPE REG_TYPE_RW -#define IN_MIRROR_PRIORITY_CTRL_DEFAULT 0x0 - /*[field] PRIORITY*/ - #define IN_MIRROR_PRIORITY_CTRL_PRIORITY - #define IN_MIRROR_PRIORITY_CTRL_PRIORITY_OFFSET 0 - #define IN_MIRROR_PRIORITY_CTRL_PRIORITY_LEN 4 - #define IN_MIRROR_PRIORITY_CTRL_PRIORITY_DEFAULT 0x0 - -struct in_mirror_priority_ctrl { - a_uint32_t priority:4; - a_uint32_t _reserved0:28; -}; - -union in_mirror_priority_ctrl_u { - a_uint32_t val; - struct in_mirror_priority_ctrl bf; -}; - -/*[register] EG_MIRROR_PRIORITY_CTRL*/ -#define EG_MIRROR_PRIORITY_CTRL -#define EG_MIRROR_PRIORITY_CTRL_ADDRESS 0x8 -#define EG_MIRROR_PRIORITY_CTRL_NUM 1 -#define EG_MIRROR_PRIORITY_CTRL_INC 0x4 -#define EG_MIRROR_PRIORITY_CTRL_TYPE REG_TYPE_RW -#define EG_MIRROR_PRIORITY_CTRL_DEFAULT 0x0 - /*[field] PRIORITY*/ - #define EG_MIRROR_PRIORITY_CTRL_PRIORITY - #define EG_MIRROR_PRIORITY_CTRL_PRIORITY_OFFSET 0 - #define EG_MIRROR_PRIORITY_CTRL_PRIORITY_LEN 4 - #define EG_MIRROR_PRIORITY_CTRL_PRIORITY_DEFAULT 0x0 - -struct eg_mirror_priority_ctrl { - a_uint32_t priority:4; - a_uint32_t _reserved0:28; -}; - -union eg_mirror_priority_ctrl_u { - a_uint32_t val; - struct eg_mirror_priority_ctrl bf; -}; - -/*[register] UCAST_DEFAULT_HASH*/ -#define UCAST_DEFAULT_HASH -#define UCAST_DEFAULT_HASH_ADDRESS 0x60 -#define UCAST_DEFAULT_HASH_NUM 1 -#define UCAST_DEFAULT_HASH_INC 0x4 -#define UCAST_DEFAULT_HASH_TYPE REG_TYPE_RW -#define UCAST_DEFAULT_HASH_DEFAULT 0x0 - /*[field] HASH*/ - #define UCAST_DEFAULT_HASH_HASH - #define UCAST_DEFAULT_HASH_HASH_OFFSET 0 - #define UCAST_DEFAULT_HASH_HASH_LEN 8 - #define UCAST_DEFAULT_HASH_HASH_DEFAULT 0x0 - -struct ucast_default_hash { - a_uint32_t hash:8; - a_uint32_t _reserved0:24; -}; - -union ucast_default_hash_u { - a_uint32_t val; - struct ucast_default_hash bf; -}; - -/*[register] SPARE_REG0*/ -#define SPARE_REG0 -#define SPARE_REG0_ADDRESS 0x70 -#define SPARE_REG0_NUM 1 -#define SPARE_REG0_INC 0x4 -#define SPARE_REG0_TYPE REG_TYPE_RW -#define SPARE_REG0_DEFAULT 0x0 - /*[field] SPARE_REG0*/ - #define SPARE_REG0_SPARE_REG0 - #define SPARE_REG0_SPARE_REG0_OFFSET 0 - #define SPARE_REG0_SPARE_REG0_LEN 32 - #define SPARE_REG0_SPARE_REG0_DEFAULT 0x0 - -struct spare_reg0 { - a_uint32_t spare_reg0:32; -}; - -union spare_reg0_u { - a_uint32_t val; - struct spare_reg0 bf; -}; - -/*[register] SPARE_REG1*/ -#define SPARE_REG1 -#define SPARE_REG1_ADDRESS 0x74 -#define SPARE_REG1_NUM 1 -#define SPARE_REG1_INC 0x4 -#define SPARE_REG1_TYPE REG_TYPE_RW -#define SPARE_REG1_DEFAULT 0x0 - /*[field] SPARE_REG1*/ - #define SPARE_REG1_SPARE_REG1 - #define SPARE_REG1_SPARE_REG1_OFFSET 0 - #define SPARE_REG1_SPARE_REG1_LEN 32 - #define SPARE_REG1_SPARE_REG1_DEFAULT 0x0 - -struct spare_reg1 { - a_uint32_t spare_reg1:32; -}; - -union spare_reg1_u { - a_uint32_t val; - struct spare_reg1 bf; -}; - -/*[register] QM_DBG_ADDR*/ -#define QM_DBG_ADDR -#define QM_DBG_ADDR_ADDRESS 0x80 -#define QM_DBG_ADDR_NUM 1 -#define QM_DBG_ADDR_INC 0x4 -#define QM_DBG_ADDR_TYPE REG_TYPE_RW -#define QM_DBG_ADDR_DEFAULT 0x0 - /*[field] DBG_ADDR*/ - #define QM_DBG_ADDR_DBG_ADDR - #define QM_DBG_ADDR_DBG_ADDR_OFFSET 0 - #define QM_DBG_ADDR_DBG_ADDR_LEN 8 - #define QM_DBG_ADDR_DBG_ADDR_DEFAULT 0x0 - -struct qm_dbg_addr { - a_uint32_t dbg_addr:8; - a_uint32_t _reserved0:24; -}; - -union qm_dbg_addr_u { - a_uint32_t val; - struct qm_dbg_addr bf; -}; - -/*[register] QM_DBG_DATA*/ -#define QM_DBG_DATA -#define QM_DBG_DATA_ADDRESS 0x84 -#define QM_DBG_DATA_NUM 1 -#define QM_DBG_DATA_INC 0x4 -#define QM_DBG_DATA_TYPE REG_TYPE_RO -#define QM_DBG_DATA_DEFAULT 0x0 - /*[field] DBG_DATA*/ - #define QM_DBG_DATA_DBG_DATA - #define QM_DBG_DATA_DBG_DATA_OFFSET 0 - #define QM_DBG_DATA_DBG_DATA_LEN 32 - #define QM_DBG_DATA_DBG_DATA_DEFAULT 0x0 - -struct qm_dbg_data { - a_uint32_t dbg_data:32; -}; - -union qm_dbg_data_u { - a_uint32_t val; - struct qm_dbg_data bf; -}; - -/*[register] MCAST_PRIORITY_MAP0*/ -#define MCAST_PRIORITY_MAP0 -#define MCAST_PRIORITY_MAP0_ADDRESS 0x100 -#define MCAST_PRIORITY_MAP0_NUM 16 -#define MCAST_PRIORITY_MAP0_INC 0x4 -#define MCAST_PRIORITY_MAP0_TYPE REG_TYPE_RW -#define MCAST_PRIORITY_MAP0_DEFAULT 0x0 - /*[field] CLASS*/ - #define MCAST_PRIORITY_MAP0_CLASS - #define MCAST_PRIORITY_MAP0_CLASS_OFFSET 0 - #define MCAST_PRIORITY_MAP0_CLASS_LEN 4 - #define MCAST_PRIORITY_MAP0_CLASS_DEFAULT 0x0 - -struct mcast_priority_map0 { - a_uint32_t class:4; - a_uint32_t _reserved0:28; -}; - -union mcast_priority_map0_u { - a_uint32_t val; - struct mcast_priority_map0 bf; -}; - -/*[register] MCAST_PRIORITY_MAP1*/ -#define MCAST_PRIORITY_MAP1 -#define MCAST_PRIORITY_MAP1_ADDRESS 0x140 -#define MCAST_PRIORITY_MAP1_NUM 16 -#define MCAST_PRIORITY_MAP1_INC 0x4 -#define MCAST_PRIORITY_MAP1_TYPE REG_TYPE_RW -#define MCAST_PRIORITY_MAP1_DEFAULT 0x0 - /*[field] CLASS*/ - #define MCAST_PRIORITY_MAP1_CLASS - #define MCAST_PRIORITY_MAP1_CLASS_OFFSET 0 - #define MCAST_PRIORITY_MAP1_CLASS_LEN 2 - #define MCAST_PRIORITY_MAP1_CLASS_DEFAULT 0x0 - -struct mcast_priority_map1 { - a_uint32_t class:2; - a_uint32_t _reserved0:30; -}; - -union mcast_priority_map1_u { - a_uint32_t val; - struct mcast_priority_map1 bf; -}; - -/*[register] MCAST_PRIORITY_MAP2*/ -#define MCAST_PRIORITY_MAP2 -#define MCAST_PRIORITY_MAP2_ADDRESS 0x180 -#define MCAST_PRIORITY_MAP2_NUM 16 -#define MCAST_PRIORITY_MAP2_INC 0x4 -#define MCAST_PRIORITY_MAP2_TYPE REG_TYPE_RW -#define MCAST_PRIORITY_MAP2_DEFAULT 0x0 - /*[field] CLASS*/ - #define MCAST_PRIORITY_MAP2_CLASS - #define MCAST_PRIORITY_MAP2_CLASS_OFFSET 0 - #define MCAST_PRIORITY_MAP2_CLASS_LEN 2 - #define MCAST_PRIORITY_MAP2_CLASS_DEFAULT 0x0 - -struct mcast_priority_map2 { - a_uint32_t class:2; - a_uint32_t _reserved0:30; -}; - -union mcast_priority_map2_u { - a_uint32_t val; - struct mcast_priority_map2 bf; -}; - -/*[register] MCAST_PRIORITY_MAP3*/ -#define MCAST_PRIORITY_MAP3 -#define MCAST_PRIORITY_MAP3_ADDRESS 0x1c0 -#define MCAST_PRIORITY_MAP3_NUM 16 -#define MCAST_PRIORITY_MAP3_INC 0x4 -#define MCAST_PRIORITY_MAP3_TYPE REG_TYPE_RW -#define MCAST_PRIORITY_MAP3_DEFAULT 0x0 - /*[field] CLASS*/ - #define MCAST_PRIORITY_MAP3_CLASS - #define MCAST_PRIORITY_MAP3_CLASS_OFFSET 0 - #define MCAST_PRIORITY_MAP3_CLASS_LEN 2 - #define MCAST_PRIORITY_MAP3_CLASS_DEFAULT 0x0 - -struct mcast_priority_map3 { - a_uint32_t class:2; - a_uint32_t _reserved0:30; -}; - -union mcast_priority_map3_u { - a_uint32_t val; - struct mcast_priority_map3 bf; -}; - -/*[register] MCAST_PRIORITY_MAP4*/ -#define MCAST_PRIORITY_MAP4 -#define MCAST_PRIORITY_MAP4_ADDRESS 0x200 -#define MCAST_PRIORITY_MAP4_NUM 16 -#define MCAST_PRIORITY_MAP4_INC 0x4 -#define MCAST_PRIORITY_MAP4_TYPE REG_TYPE_RW -#define MCAST_PRIORITY_MAP4_DEFAULT 0x0 - /*[field] CLASS*/ - #define MCAST_PRIORITY_MAP4_CLASS - #define MCAST_PRIORITY_MAP4_CLASS_OFFSET 0 - #define MCAST_PRIORITY_MAP4_CLASS_LEN 2 - #define MCAST_PRIORITY_MAP4_CLASS_DEFAULT 0x0 - -struct mcast_priority_map4 { - a_uint32_t class:2; - a_uint32_t _reserved0:30; -}; - -union mcast_priority_map4_u { - a_uint32_t val; - struct mcast_priority_map4 bf; -}; - -/*[register] MCAST_PRIORITY_MAP5*/ -#define MCAST_PRIORITY_MAP5 -#define MCAST_PRIORITY_MAP5_ADDRESS 0x240 -#define MCAST_PRIORITY_MAP5_NUM 16 -#define MCAST_PRIORITY_MAP5_INC 0x4 -#define MCAST_PRIORITY_MAP5_TYPE REG_TYPE_RW -#define MCAST_PRIORITY_MAP5_DEFAULT 0x0 - /*[field] CLASS*/ - #define MCAST_PRIORITY_MAP5_CLASS - #define MCAST_PRIORITY_MAP5_CLASS_OFFSET 0 - #define MCAST_PRIORITY_MAP5_CLASS_LEN 2 - #define MCAST_PRIORITY_MAP5_CLASS_DEFAULT 0x0 - -struct mcast_priority_map5 { - a_uint32_t class:2; - a_uint32_t _reserved0:30; -}; - -union mcast_priority_map5_u { - a_uint32_t val; - struct mcast_priority_map5 bf; -}; - -/*[register] MCAST_PRIORITY_MAP6*/ -#define MCAST_PRIORITY_MAP6 -#define MCAST_PRIORITY_MAP6_ADDRESS 0x280 -#define MCAST_PRIORITY_MAP6_NUM 16 -#define MCAST_PRIORITY_MAP6_INC 0x4 -#define MCAST_PRIORITY_MAP6_TYPE REG_TYPE_RW -#define MCAST_PRIORITY_MAP6_DEFAULT 0x0 - /*[field] CLASS*/ - #define MCAST_PRIORITY_MAP6_CLASS - #define MCAST_PRIORITY_MAP6_CLASS_OFFSET 0 - #define MCAST_PRIORITY_MAP6_CLASS_LEN 2 - #define MCAST_PRIORITY_MAP6_CLASS_DEFAULT 0x0 - -struct mcast_priority_map6 { - a_uint32_t class:2; - a_uint32_t _reserved0:30; -}; - -union mcast_priority_map6_u { - a_uint32_t val; - struct mcast_priority_map6 bf; -}; - -/*[register] MCAST_PRIORITY_MAP7*/ -#define MCAST_PRIORITY_MAP7 -#define MCAST_PRIORITY_MAP7_ADDRESS 0x2c0 -#define MCAST_PRIORITY_MAP7_NUM 16 -#define MCAST_PRIORITY_MAP7_INC 0x4 -#define MCAST_PRIORITY_MAP7_TYPE REG_TYPE_RW -#define MCAST_PRIORITY_MAP7_DEFAULT 0x0 - /*[field] CLASS*/ - #define MCAST_PRIORITY_MAP7_CLASS - #define MCAST_PRIORITY_MAP7_CLASS_OFFSET 0 - #define MCAST_PRIORITY_MAP7_CLASS_LEN 2 - #define MCAST_PRIORITY_MAP7_CLASS_DEFAULT 0x0 - -struct mcast_priority_map7 { - a_uint32_t class:2; - a_uint32_t _reserved0:30; -}; - -union mcast_priority_map7_u { - a_uint32_t val; - struct mcast_priority_map7 bf; -}; - -/*[register] AGG_PROFILE_CNT_EN*/ -#define AGG_PROFILE_CNT_EN -#define AGG_PROFILE_CNT_EN_ADDRESS 0x300 -#define AGG_PROFILE_CNT_EN_NUM 1 -#define AGG_PROFILE_CNT_EN_INC 0x4 -#define AGG_PROFILE_CNT_EN_TYPE REG_TYPE_RW -#define AGG_PROFILE_CNT_EN_DEFAULT 0xfffff - /*[field] UQ_EN_0*/ - #define AGG_PROFILE_CNT_EN_UQ_EN_0 - #define AGG_PROFILE_CNT_EN_UQ_EN_0_OFFSET 0 - #define AGG_PROFILE_CNT_EN_UQ_EN_0_LEN 1 - #define AGG_PROFILE_CNT_EN_UQ_EN_0_DEFAULT 0x1 - /*[field] UQ_EN_1*/ - #define AGG_PROFILE_CNT_EN_UQ_EN_1 - #define AGG_PROFILE_CNT_EN_UQ_EN_1_OFFSET 1 - #define AGG_PROFILE_CNT_EN_UQ_EN_1_LEN 1 - #define AGG_PROFILE_CNT_EN_UQ_EN_1_DEFAULT 0x1 - /*[field] UQ_EN_2*/ - #define AGG_PROFILE_CNT_EN_UQ_EN_2 - #define AGG_PROFILE_CNT_EN_UQ_EN_2_OFFSET 2 - #define AGG_PROFILE_CNT_EN_UQ_EN_2_LEN 1 - #define AGG_PROFILE_CNT_EN_UQ_EN_2_DEFAULT 0x1 - /*[field] UQ_EN_3*/ - #define AGG_PROFILE_CNT_EN_UQ_EN_3 - #define AGG_PROFILE_CNT_EN_UQ_EN_3_OFFSET 3 - #define AGG_PROFILE_CNT_EN_UQ_EN_3_LEN 1 - #define AGG_PROFILE_CNT_EN_UQ_EN_3_DEFAULT 0x1 - /*[field] UQ_EN_4*/ - #define AGG_PROFILE_CNT_EN_UQ_EN_4 - #define AGG_PROFILE_CNT_EN_UQ_EN_4_OFFSET 4 - #define AGG_PROFILE_CNT_EN_UQ_EN_4_LEN 1 - #define AGG_PROFILE_CNT_EN_UQ_EN_4_DEFAULT 0x1 - /*[field] UQ_EN_5*/ - #define AGG_PROFILE_CNT_EN_UQ_EN_5 - #define AGG_PROFILE_CNT_EN_UQ_EN_5_OFFSET 5 - #define AGG_PROFILE_CNT_EN_UQ_EN_5_LEN 1 - #define AGG_PROFILE_CNT_EN_UQ_EN_5_DEFAULT 0x1 - /*[field] UQ_EN_6*/ - #define AGG_PROFILE_CNT_EN_UQ_EN_6 - #define AGG_PROFILE_CNT_EN_UQ_EN_6_OFFSET 6 - #define AGG_PROFILE_CNT_EN_UQ_EN_6_LEN 1 - #define AGG_PROFILE_CNT_EN_UQ_EN_6_DEFAULT 0x1 - /*[field] UQ_EN_7*/ - #define AGG_PROFILE_CNT_EN_UQ_EN_7 - #define AGG_PROFILE_CNT_EN_UQ_EN_7_OFFSET 7 - #define AGG_PROFILE_CNT_EN_UQ_EN_7_LEN 1 - #define AGG_PROFILE_CNT_EN_UQ_EN_7_DEFAULT 0x1 - /*[field] MQ_P0_EN*/ - #define AGG_PROFILE_CNT_EN_MQ_P0_EN - #define AGG_PROFILE_CNT_EN_MQ_P0_EN_OFFSET 8 - #define AGG_PROFILE_CNT_EN_MQ_P0_EN_LEN 1 - #define AGG_PROFILE_CNT_EN_MQ_P0_EN_DEFAULT 0x1 - /*[field] MQ_P1_EN*/ - #define AGG_PROFILE_CNT_EN_MQ_P1_EN - #define AGG_PROFILE_CNT_EN_MQ_P1_EN_OFFSET 9 - #define AGG_PROFILE_CNT_EN_MQ_P1_EN_LEN 1 - #define AGG_PROFILE_CNT_EN_MQ_P1_EN_DEFAULT 0x1 - /*[field] MQ_P2_EN*/ - #define AGG_PROFILE_CNT_EN_MQ_P2_EN - #define AGG_PROFILE_CNT_EN_MQ_P2_EN_OFFSET 10 - #define AGG_PROFILE_CNT_EN_MQ_P2_EN_LEN 1 - #define AGG_PROFILE_CNT_EN_MQ_P2_EN_DEFAULT 0x1 - /*[field] MQ_P3_EN*/ - #define AGG_PROFILE_CNT_EN_MQ_P3_EN - #define AGG_PROFILE_CNT_EN_MQ_P3_EN_OFFSET 11 - #define AGG_PROFILE_CNT_EN_MQ_P3_EN_LEN 1 - #define AGG_PROFILE_CNT_EN_MQ_P3_EN_DEFAULT 0x1 - /*[field] MQ_P4_EN*/ - #define AGG_PROFILE_CNT_EN_MQ_P4_EN - #define AGG_PROFILE_CNT_EN_MQ_P4_EN_OFFSET 12 - #define AGG_PROFILE_CNT_EN_MQ_P4_EN_LEN 1 - #define AGG_PROFILE_CNT_EN_MQ_P4_EN_DEFAULT 0x1 - /*[field] MQ_P5_EN*/ - #define AGG_PROFILE_CNT_EN_MQ_P5_EN - #define AGG_PROFILE_CNT_EN_MQ_P5_EN_OFFSET 13 - #define AGG_PROFILE_CNT_EN_MQ_P5_EN_LEN 1 - #define AGG_PROFILE_CNT_EN_MQ_P5_EN_DEFAULT 0x1 - /*[field] MQ_P6_EN*/ - #define AGG_PROFILE_CNT_EN_MQ_P6_EN - #define AGG_PROFILE_CNT_EN_MQ_P6_EN_OFFSET 14 - #define AGG_PROFILE_CNT_EN_MQ_P6_EN_LEN 1 - #define AGG_PROFILE_CNT_EN_MQ_P6_EN_DEFAULT 0x1 - /*[field] MQ_P7_EN*/ - #define AGG_PROFILE_CNT_EN_MQ_P7_EN - #define AGG_PROFILE_CNT_EN_MQ_P7_EN_OFFSET 15 - #define AGG_PROFILE_CNT_EN_MQ_P7_EN_LEN 1 - #define AGG_PROFILE_CNT_EN_MQ_P7_EN_DEFAULT 0x1 - /*[field] GRP_0_EN*/ - #define AGG_PROFILE_CNT_EN_GRP_0_EN - #define AGG_PROFILE_CNT_EN_GRP_0_EN_OFFSET 16 - #define AGG_PROFILE_CNT_EN_GRP_0_EN_LEN 1 - #define AGG_PROFILE_CNT_EN_GRP_0_EN_DEFAULT 0x1 - /*[field] GRP_1_EN*/ - #define AGG_PROFILE_CNT_EN_GRP_1_EN - #define AGG_PROFILE_CNT_EN_GRP_1_EN_OFFSET 17 - #define AGG_PROFILE_CNT_EN_GRP_1_EN_LEN 1 - #define AGG_PROFILE_CNT_EN_GRP_1_EN_DEFAULT 0x1 - /*[field] GRP_2_EN*/ - #define AGG_PROFILE_CNT_EN_GRP_2_EN - #define AGG_PROFILE_CNT_EN_GRP_2_EN_OFFSET 18 - #define AGG_PROFILE_CNT_EN_GRP_2_EN_LEN 1 - #define AGG_PROFILE_CNT_EN_GRP_2_EN_DEFAULT 0x1 - /*[field] GRP_3_EN*/ - #define AGG_PROFILE_CNT_EN_GRP_3_EN - #define AGG_PROFILE_CNT_EN_GRP_3_EN_OFFSET 19 - #define AGG_PROFILE_CNT_EN_GRP_3_EN_LEN 1 - #define AGG_PROFILE_CNT_EN_GRP_3_EN_DEFAULT 0x1 - /*[field] GLOBAL_EN*/ - #define AGG_PROFILE_CNT_EN_GLOBAL_EN - #define AGG_PROFILE_CNT_EN_GLOBAL_EN_OFFSET 31 - #define AGG_PROFILE_CNT_EN_GLOBAL_EN_LEN 1 - #define AGG_PROFILE_CNT_EN_GLOBAL_EN_DEFAULT 0x0 - -struct agg_profile_cnt_en { - a_uint32_t uq_en_0:1; - a_uint32_t uq_en_1:1; - a_uint32_t uq_en_2:1; - a_uint32_t uq_en_3:1; - a_uint32_t uq_en_4:1; - a_uint32_t uq_en_5:1; - a_uint32_t uq_en_6:1; - a_uint32_t uq_en_7:1; - a_uint32_t mq_p0_en:1; - a_uint32_t mq_p1_en:1; - a_uint32_t mq_p2_en:1; - a_uint32_t mq_p3_en:1; - a_uint32_t mq_p4_en:1; - a_uint32_t mq_p5_en:1; - a_uint32_t mq_p6_en:1; - a_uint32_t mq_p7_en:1; - a_uint32_t grp_0_en:1; - a_uint32_t grp_1_en:1; - a_uint32_t grp_2_en:1; - a_uint32_t grp_3_en:1; - a_uint32_t _reserved0:11; - a_uint32_t global_en:1; -}; - -union agg_profile_cnt_en_u { - a_uint32_t val; - struct agg_profile_cnt_en bf; -}; - -/*[register] UQ_AGG_PROFILE_CFG*/ -#define UQ_AGG_PROFILE_CFG -#define UQ_AGG_PROFILE_CFG_ADDRESS 0x320 -#define UQ_AGG_PROFILE_CFG_NUM 8 -#define UQ_AGG_PROFILE_CFG_INC 0x4 -#define UQ_AGG_PROFILE_CFG_TYPE REG_TYPE_RW -#define UQ_AGG_PROFILE_CFG_DEFAULT 0x0 - /*[field] TH_CFG*/ - #define UQ_AGG_PROFILE_CFG_TH_CFG - #define UQ_AGG_PROFILE_CFG_TH_CFG_OFFSET 0 - #define UQ_AGG_PROFILE_CFG_TH_CFG_LEN 11 - #define UQ_AGG_PROFILE_CFG_TH_CFG_DEFAULT 0x0 - -struct uq_agg_profile_cfg { - a_uint32_t th_cfg:11; - a_uint32_t _reserved0:21; -}; - -union uq_agg_profile_cfg_u { - a_uint32_t val; - struct uq_agg_profile_cfg bf; -}; - -/*[register] MQ_AGG_PROFILE_CFG*/ -#define MQ_AGG_PROFILE_CFG -#define MQ_AGG_PROFILE_CFG_ADDRESS 0x340 -#define MQ_AGG_PROFILE_CFG_NUM 8 -#define MQ_AGG_PROFILE_CFG_INC 0x4 -#define MQ_AGG_PROFILE_CFG_TYPE REG_TYPE_RW -#define MQ_AGG_PROFILE_CFG_DEFAULT 0x0 - /*[field] TH_CFG*/ - #define MQ_AGG_PROFILE_CFG_TH_CFG - #define MQ_AGG_PROFILE_CFG_TH_CFG_OFFSET 0 - #define MQ_AGG_PROFILE_CFG_TH_CFG_LEN 11 - #define MQ_AGG_PROFILE_CFG_TH_CFG_DEFAULT 0x0 - -struct mq_agg_profile_cfg { - a_uint32_t th_cfg:11; - a_uint32_t _reserved0:21; -}; - -union mq_agg_profile_cfg_u { - a_uint32_t val; - struct mq_agg_profile_cfg bf; -}; - -/*[register] GRP_AGG_PROFILE_CFG*/ -#define GRP_AGG_PROFILE_CFG -#define GRP_AGG_PROFILE_CFG_ADDRESS 0x360 -#define GRP_AGG_PROFILE_CFG_NUM 4 -#define GRP_AGG_PROFILE_CFG_INC 0x4 -#define GRP_AGG_PROFILE_CFG_TYPE REG_TYPE_RW -#define GRP_AGG_PROFILE_CFG_DEFAULT 0x0 - /*[field] TH_CFG*/ - #define GRP_AGG_PROFILE_CFG_TH_CFG - #define GRP_AGG_PROFILE_CFG_TH_CFG_OFFSET 0 - #define GRP_AGG_PROFILE_CFG_TH_CFG_LEN 11 - #define GRP_AGG_PROFILE_CFG_TH_CFG_DEFAULT 0x0 - -struct grp_agg_profile_cfg { - a_uint32_t th_cfg:11; - a_uint32_t _reserved0:21; -}; - -union grp_agg_profile_cfg_u { - a_uint32_t val; - struct grp_agg_profile_cfg bf; -}; - -/*[register] UQ_AGG_IN_PROFILE_CNT*/ -#define UQ_AGG_IN_PROFILE_CNT -#define UQ_AGG_IN_PROFILE_CNT_ADDRESS 0x380 -#define UQ_AGG_IN_PROFILE_CNT_NUM 8 -#define UQ_AGG_IN_PROFILE_CNT_INC 0x4 -#define UQ_AGG_IN_PROFILE_CNT_TYPE REG_TYPE_RW -#define UQ_AGG_IN_PROFILE_CNT_DEFAULT 0x0 - /*[field] CNT*/ - #define UQ_AGG_IN_PROFILE_CNT_CNT - #define UQ_AGG_IN_PROFILE_CNT_CNT_OFFSET 0 - #define UQ_AGG_IN_PROFILE_CNT_CNT_LEN 32 - #define UQ_AGG_IN_PROFILE_CNT_CNT_DEFAULT 0x0 - -struct uq_agg_in_profile_cnt { - a_uint32_t cnt:32; -}; - -union uq_agg_in_profile_cnt_u { - a_uint32_t val; - struct uq_agg_in_profile_cnt bf; -}; - -/*[register] UQ_AGG_OUT_PROFILE_CNT*/ -#define UQ_AGG_OUT_PROFILE_CNT -#define UQ_AGG_OUT_PROFILE_CNT_ADDRESS 0x3a0 -#define UQ_AGG_OUT_PROFILE_CNT_NUM 8 -#define UQ_AGG_OUT_PROFILE_CNT_INC 0x4 -#define UQ_AGG_OUT_PROFILE_CNT_TYPE REG_TYPE_RW -#define UQ_AGG_OUT_PROFILE_CNT_DEFAULT 0x0 - /*[field] CNT*/ - #define UQ_AGG_OUT_PROFILE_CNT_CNT - #define UQ_AGG_OUT_PROFILE_CNT_CNT_OFFSET 0 - #define UQ_AGG_OUT_PROFILE_CNT_CNT_LEN 32 - #define UQ_AGG_OUT_PROFILE_CNT_CNT_DEFAULT 0x0 - -struct uq_agg_out_profile_cnt { - a_uint32_t cnt:32; -}; - -union uq_agg_out_profile_cnt_u { - a_uint32_t val; - struct uq_agg_out_profile_cnt bf; -}; - -/*[register] MQ_AGG_IN_PROFILE_CNT*/ -#define MQ_AGG_IN_PROFILE_CNT -#define MQ_AGG_IN_PROFILE_CNT_ADDRESS 0x3c0 -#define MQ_AGG_IN_PROFILE_CNT_NUM 8 -#define MQ_AGG_IN_PROFILE_CNT_INC 0x4 -#define MQ_AGG_IN_PROFILE_CNT_TYPE REG_TYPE_RW -#define MQ_AGG_IN_PROFILE_CNT_DEFAULT 0x0 - /*[field] CNT*/ - #define MQ_AGG_IN_PROFILE_CNT_CNT - #define MQ_AGG_IN_PROFILE_CNT_CNT_OFFSET 0 - #define MQ_AGG_IN_PROFILE_CNT_CNT_LEN 32 - #define MQ_AGG_IN_PROFILE_CNT_CNT_DEFAULT 0x0 - -struct mq_agg_in_profile_cnt { - a_uint32_t cnt:32; -}; - -union mq_agg_in_profile_cnt_u { - a_uint32_t val; - struct mq_agg_in_profile_cnt bf; -}; - -/*[register] MQ_AGG_OUT_PROFILE_CNT*/ -#define MQ_AGG_OUT_PROFILE_CNT -#define MQ_AGG_OUT_PROFILE_CNT_ADDRESS 0x3e0 -#define MQ_AGG_OUT_PROFILE_CNT_NUM 8 -#define MQ_AGG_OUT_PROFILE_CNT_INC 0x4 -#define MQ_AGG_OUT_PROFILE_CNT_TYPE REG_TYPE_RW -#define MQ_AGG_OUT_PROFILE_CNT_DEFAULT 0x0 - /*[field] CNT*/ - #define MQ_AGG_OUT_PROFILE_CNT_CNT - #define MQ_AGG_OUT_PROFILE_CNT_CNT_OFFSET 0 - #define MQ_AGG_OUT_PROFILE_CNT_CNT_LEN 32 - #define MQ_AGG_OUT_PROFILE_CNT_CNT_DEFAULT 0x0 - -struct mq_agg_out_profile_cnt { - a_uint32_t cnt:32; -}; - -union mq_agg_out_profile_cnt_u { - a_uint32_t val; - struct mq_agg_out_profile_cnt bf; -}; - -/*[register] GRP_AGG_IN_PROFILE_CNT*/ -#define GRP_AGG_IN_PROFILE_CNT -#define GRP_AGG_IN_PROFILE_CNT_ADDRESS 0x400 -#define GRP_AGG_IN_PROFILE_CNT_NUM 4 -#define GRP_AGG_IN_PROFILE_CNT_INC 0x4 -#define GRP_AGG_IN_PROFILE_CNT_TYPE REG_TYPE_RW -#define GRP_AGG_IN_PROFILE_CNT_DEFAULT 0x0 - /*[field] CNT*/ - #define GRP_AGG_IN_PROFILE_CNT_CNT - #define GRP_AGG_IN_PROFILE_CNT_CNT_OFFSET 0 - #define GRP_AGG_IN_PROFILE_CNT_CNT_LEN 32 - #define GRP_AGG_IN_PROFILE_CNT_CNT_DEFAULT 0x0 - -struct grp_agg_in_profile_cnt { - a_uint32_t cnt:32; -}; - -union grp_agg_in_profile_cnt_u { - a_uint32_t val; - struct grp_agg_in_profile_cnt bf; -}; - -/*[register] GRP_AGG_OUT_PROFILE_CNT*/ -#define GRP_AGG_OUT_PROFILE_CNT -#define GRP_AGG_OUT_PROFILE_CNT_ADDRESS 0x410 -#define GRP_AGG_OUT_PROFILE_CNT_NUM 4 -#define GRP_AGG_OUT_PROFILE_CNT_INC 0x4 -#define GRP_AGG_OUT_PROFILE_CNT_TYPE REG_TYPE_RW -#define GRP_AGG_OUT_PROFILE_CNT_DEFAULT 0x0 - /*[field] CNT*/ - #define GRP_AGG_OUT_PROFILE_CNT_CNT - #define GRP_AGG_OUT_PROFILE_CNT_CNT_OFFSET 0 - #define GRP_AGG_OUT_PROFILE_CNT_CNT_LEN 32 - #define GRP_AGG_OUT_PROFILE_CNT_CNT_DEFAULT 0x0 - -struct grp_agg_out_profile_cnt { - a_uint32_t cnt:32; -}; - -union grp_agg_out_profile_cnt_u { - a_uint32_t val; - struct grp_agg_out_profile_cnt bf; -}; - -/*[table] UCAST_QUEUE_MAP_TBL*/ -#define UCAST_QUEUE_MAP_TBL -#define UCAST_QUEUE_MAP_TBL_ADDRESS 0x10000 -#define UCAST_QUEUE_MAP_TBL_NUM 3072 -#define UCAST_QUEUE_MAP_TBL_INC 0x10 -#define UCAST_QUEUE_MAP_TBL_TYPE REG_TYPE_RW -#define UCAST_QUEUE_MAP_TBL_DEFAULT 0x0 - /*[field] PROFILE_ID*/ - #define UCAST_QUEUE_MAP_TBL_PROFILE_ID - #define UCAST_QUEUE_MAP_TBL_PROFILE_ID_OFFSET 0 - #define UCAST_QUEUE_MAP_TBL_PROFILE_ID_LEN 4 - #define UCAST_QUEUE_MAP_TBL_PROFILE_ID_DEFAULT 0x0 - /*[field] QUEUE_ID*/ - #define UCAST_QUEUE_MAP_TBL_QUEUE_ID - #define UCAST_QUEUE_MAP_TBL_QUEUE_ID_OFFSET 4 - #define UCAST_QUEUE_MAP_TBL_QUEUE_ID_LEN 8 - #define UCAST_QUEUE_MAP_TBL_QUEUE_ID_DEFAULT 0x0 - -struct ucast_queue_map_tbl { - a_uint32_t profile_id:4; - a_uint32_t queue_id:8; - a_uint32_t _reserved0:20; -}; - -union ucast_queue_map_tbl_u { - a_uint32_t val; - struct ucast_queue_map_tbl bf; -}; - -/*[table] UCAST_HASH_MAP_TBL*/ -#define UCAST_HASH_MAP_TBL -#define UCAST_HASH_MAP_TBL_ADDRESS 0x30000 -#define UCAST_HASH_MAP_TBL_NUM 4096 -#define UCAST_HASH_MAP_TBL_INC 0x10 -#define UCAST_HASH_MAP_TBL_TYPE REG_TYPE_RW -#define UCAST_HASH_MAP_TBL_DEFAULT 0x0 - /*[field] HASH*/ - #define UCAST_HASH_MAP_TBL_HASH - #define UCAST_HASH_MAP_TBL_HASH_OFFSET 0 - #define UCAST_HASH_MAP_TBL_HASH_LEN 8 - #define UCAST_HASH_MAP_TBL_HASH_DEFAULT 0x0 - -struct ucast_hash_map_tbl { - a_uint32_t hash:8; - a_uint32_t _reserved0:24; -}; - -union ucast_hash_map_tbl_u { - a_uint32_t val; - struct ucast_hash_map_tbl bf; -}; - -/*[table] UCAST_PRIORITY_MAP_TBL*/ -#define UCAST_PRIORITY_MAP_TBL -#define UCAST_PRIORITY_MAP_TBL_ADDRESS 0x42000 -#define UCAST_PRIORITY_MAP_TBL_NUM 256 -#define UCAST_PRIORITY_MAP_TBL_INC 0x10 -#define UCAST_PRIORITY_MAP_TBL_TYPE REG_TYPE_RW -#define UCAST_PRIORITY_MAP_TBL_DEFAULT 0x0 - /*[field] CLASS*/ - #define UCAST_PRIORITY_MAP_TBL_CLASS - #define UCAST_PRIORITY_MAP_TBL_CLASS_OFFSET 0 - #define UCAST_PRIORITY_MAP_TBL_CLASS_LEN 4 - #define UCAST_PRIORITY_MAP_TBL_CLASS_DEFAULT 0x0 - -struct ucast_priority_map_tbl { - a_uint32_t class:4; - a_uint32_t _reserved0:28; -}; - -union ucast_priority_map_tbl_u { - a_uint32_t val; - struct ucast_priority_map_tbl bf; -}; - -/*[table] MCAST_QUEUE_MAP_TBL*/ -#define MCAST_QUEUE_MAP_TBL -#define MCAST_QUEUE_MAP_TBL_ADDRESS 0x44000 -#define MCAST_QUEUE_MAP_TBL_NUM 256 -#define MCAST_QUEUE_MAP_TBL_INC 0x10 -#define MCAST_QUEUE_MAP_TBL_TYPE REG_TYPE_RW -#define MCAST_QUEUE_MAP_TBL_DEFAULT 0x0 - /*[field] CLASS*/ - #define MCAST_QUEUE_MAP_TBL_CLASS - #define MCAST_QUEUE_MAP_TBL_CLASS_OFFSET 0 - #define MCAST_QUEUE_MAP_TBL_CLASS_LEN 4 - #define MCAST_QUEUE_MAP_TBL_CLASS_DEFAULT 0x0 - -struct mcast_queue_map_tbl { - a_uint32_t class:4; - a_uint32_t _reserved0:28; -}; - -union mcast_queue_map_tbl_u { - a_uint32_t val; - struct mcast_queue_map_tbl bf; -}; - -/*[table] AC_MSEQ_TBL*/ -#define AC_MSEQ_TBL -#define AC_MSEQ_TBL_ADDRESS 0x46000 -#define AC_MSEQ_TBL_NUM 256 -#define AC_MSEQ_TBL_INC 0x10 -#define AC_MSEQ_TBL_TYPE REG_TYPE_RW -#define AC_MSEQ_TBL_DEFAULT 0x0 - /*[field] AC_MSEQ*/ - #define AC_MSEQ_TBL_AC_MSEQ - #define AC_MSEQ_TBL_AC_MSEQ_OFFSET 0 - #define AC_MSEQ_TBL_AC_MSEQ_LEN 15 - #define AC_MSEQ_TBL_AC_MSEQ_DEFAULT 0x0 - -struct ac_mseq_tbl { - a_uint32_t ac_mseq:15; - a_uint32_t _reserved0:17; -}; - -union ac_mseq_tbl_u { - a_uint32_t val; - struct ac_mseq_tbl bf; -}; - -/*[table] AC_UNI_QUEUE_CFG_TBL*/ -#define AC_UNI_QUEUE_CFG_TBL -#define AC_UNI_QUEUE_CFG_TBL_ADDRESS 0x48000 -#define AC_UNI_QUEUE_CFG_TBL_NUM 256 -#define AC_UNI_QUEUE_CFG_TBL_INC 0x10 -#define AC_UNI_QUEUE_CFG_TBL_TYPE REG_TYPE_RW -#define AC_UNI_QUEUE_CFG_TBL_DEFAULT 0x0 - /*[field] AC_CFG_AC_EN*/ - #define AC_UNI_QUEUE_CFG_TBL_AC_CFG_AC_EN - #define AC_UNI_QUEUE_CFG_TBL_AC_CFG_AC_EN_OFFSET 0 - #define AC_UNI_QUEUE_CFG_TBL_AC_CFG_AC_EN_LEN 1 - #define AC_UNI_QUEUE_CFG_TBL_AC_CFG_AC_EN_DEFAULT 0x0 - /*[field] AC_CFG_WRED_EN*/ - #define AC_UNI_QUEUE_CFG_TBL_AC_CFG_WRED_EN - #define AC_UNI_QUEUE_CFG_TBL_AC_CFG_WRED_EN_OFFSET 1 - #define AC_UNI_QUEUE_CFG_TBL_AC_CFG_WRED_EN_LEN 1 - #define AC_UNI_QUEUE_CFG_TBL_AC_CFG_WRED_EN_DEFAULT 0x0 - /*[field] AC_CFG_FORCE_AC_EN*/ - #define AC_UNI_QUEUE_CFG_TBL_AC_CFG_FORCE_AC_EN - #define AC_UNI_QUEUE_CFG_TBL_AC_CFG_FORCE_AC_EN_OFFSET 2 - #define AC_UNI_QUEUE_CFG_TBL_AC_CFG_FORCE_AC_EN_LEN 1 - #define AC_UNI_QUEUE_CFG_TBL_AC_CFG_FORCE_AC_EN_DEFAULT 0x0 - /*[field] AC_CFG_COLOR_AWARE*/ - #define AC_UNI_QUEUE_CFG_TBL_AC_CFG_COLOR_AWARE - #define AC_UNI_QUEUE_CFG_TBL_AC_CFG_COLOR_AWARE_OFFSET 3 - #define AC_UNI_QUEUE_CFG_TBL_AC_CFG_COLOR_AWARE_LEN 1 - #define AC_UNI_QUEUE_CFG_TBL_AC_CFG_COLOR_AWARE_DEFAULT 0x0 - /*[field] AC_CFG_GRP_ID*/ - #define AC_UNI_QUEUE_CFG_TBL_AC_CFG_GRP_ID - #define AC_UNI_QUEUE_CFG_TBL_AC_CFG_GRP_ID_OFFSET 4 - #define AC_UNI_QUEUE_CFG_TBL_AC_CFG_GRP_ID_LEN 2 - #define AC_UNI_QUEUE_CFG_TBL_AC_CFG_GRP_ID_DEFAULT 0x0 - /*[field] AC_CFG_PRE_ALLOC_LIMIT*/ - #define AC_UNI_QUEUE_CFG_TBL_AC_CFG_PRE_ALLOC_LIMIT - #define AC_UNI_QUEUE_CFG_TBL_AC_CFG_PRE_ALLOC_LIMIT_OFFSET 6 - #define AC_UNI_QUEUE_CFG_TBL_AC_CFG_PRE_ALLOC_LIMIT_LEN 11 - #define AC_UNI_QUEUE_CFG_TBL_AC_CFG_PRE_ALLOC_LIMIT_DEFAULT 0x0 - /*[field] AC_CFG_SHARED_DYNAMIC*/ - #define AC_UNI_QUEUE_CFG_TBL_AC_CFG_SHARED_DYNAMIC - #define AC_UNI_QUEUE_CFG_TBL_AC_CFG_SHARED_DYNAMIC_OFFSET 17 - #define AC_UNI_QUEUE_CFG_TBL_AC_CFG_SHARED_DYNAMIC_LEN 1 - #define AC_UNI_QUEUE_CFG_TBL_AC_CFG_SHARED_DYNAMIC_DEFAULT 0x0 - /*[field] AC_CFG_SHARED_WEIGHT*/ - #define AC_UNI_QUEUE_CFG_TBL_AC_CFG_SHARED_WEIGHT - #define AC_UNI_QUEUE_CFG_TBL_AC_CFG_SHARED_WEIGHT_OFFSET 18 - #define AC_UNI_QUEUE_CFG_TBL_AC_CFG_SHARED_WEIGHT_LEN 3 - #define AC_UNI_QUEUE_CFG_TBL_AC_CFG_SHARED_WEIGHT_DEFAULT 0x0 - /*[field] AC_CFG_SHARED_CEILING*/ - #define AC_UNI_QUEUE_CFG_TBL_AC_CFG_SHARED_CEILING - #define AC_UNI_QUEUE_CFG_TBL_AC_CFG_SHARED_CEILING_OFFSET 21 - #define AC_UNI_QUEUE_CFG_TBL_AC_CFG_SHARED_CEILING_LEN 11 - #define AC_UNI_QUEUE_CFG_TBL_AC_CFG_SHARED_CEILING_DEFAULT 0x0 - /*[field] AC_CFG_GAP_GRN_GRN_MIN*/ - #define AC_UNI_QUEUE_CFG_TBL_AC_CFG_GAP_GRN_GRN_MIN - #define AC_UNI_QUEUE_CFG_TBL_AC_CFG_GAP_GRN_GRN_MIN_OFFSET 32 - #define AC_UNI_QUEUE_CFG_TBL_AC_CFG_GAP_GRN_GRN_MIN_LEN 11 - #define AC_UNI_QUEUE_CFG_TBL_AC_CFG_GAP_GRN_GRN_MIN_DEFAULT 0x0 - /*[field] AC_CFG_GAP_GRN_YEL_MAX*/ - #define AC_UNI_QUEUE_CFG_TBL_AC_CFG_GAP_GRN_YEL_MAX - #define AC_UNI_QUEUE_CFG_TBL_AC_CFG_GAP_GRN_YEL_MAX_OFFSET 43 - #define AC_UNI_QUEUE_CFG_TBL_AC_CFG_GAP_GRN_YEL_MAX_LEN 11 - #define AC_UNI_QUEUE_CFG_TBL_AC_CFG_GAP_GRN_YEL_MAX_DEFAULT 0x0 - /*[field] AC_CFG_GAP_GRN_YEL_MIN*/ - #define AC_UNI_QUEUE_CFG_TBL_AC_CFG_GAP_GRN_YEL_MIN - #define AC_UNI_QUEUE_CFG_TBL_AC_CFG_GAP_GRN_YEL_MIN_OFFSET 54 - #define AC_UNI_QUEUE_CFG_TBL_AC_CFG_GAP_GRN_YEL_MIN_LEN 11 - #define AC_UNI_QUEUE_CFG_TBL_AC_CFG_GAP_GRN_YEL_MIN_DEFAULT 0x0 - /*[field] AC_CFG_GAP_GRN_RED_MAX*/ - #define AC_UNI_QUEUE_CFG_TBL_AC_CFG_GAP_GRN_RED_MAX - #define AC_UNI_QUEUE_CFG_TBL_AC_CFG_GAP_GRN_RED_MAX_OFFSET 65 - #define AC_UNI_QUEUE_CFG_TBL_AC_CFG_GAP_GRN_RED_MAX_LEN 11 - #define AC_UNI_QUEUE_CFG_TBL_AC_CFG_GAP_GRN_RED_MAX_DEFAULT 0x0 - /*[field] AC_CFG_GAP_GRN_RED_MIN*/ - #define AC_UNI_QUEUE_CFG_TBL_AC_CFG_GAP_GRN_RED_MIN - #define AC_UNI_QUEUE_CFG_TBL_AC_CFG_GAP_GRN_RED_MIN_OFFSET 76 - #define AC_UNI_QUEUE_CFG_TBL_AC_CFG_GAP_GRN_RED_MIN_LEN 11 - #define AC_UNI_QUEUE_CFG_TBL_AC_CFG_GAP_GRN_RED_MIN_DEFAULT 0x0 - /*[field] AC_CFG_RED_RESUME_OFFSET*/ - #define AC_UNI_QUEUE_CFG_TBL_AC_CFG_RED_RESUME_OFFSET - #define AC_UNI_QUEUE_CFG_TBL_AC_CFG_RED_RESUME_OFFSET_OFFSET 87 - #define AC_UNI_QUEUE_CFG_TBL_AC_CFG_RED_RESUME_OFFSET_LEN 11 - #define AC_UNI_QUEUE_CFG_TBL_AC_CFG_RED_RESUME_OFFSET_DEFAULT 0x0 - /*[field] AC_CFG_YEL_RESUME_OFFSET*/ - #define AC_UNI_QUEUE_CFG_TBL_AC_CFG_YEL_RESUME_OFFSET - #define AC_UNI_QUEUE_CFG_TBL_AC_CFG_YEL_RESUME_OFFSET_OFFSET 98 - #define AC_UNI_QUEUE_CFG_TBL_AC_CFG_YEL_RESUME_OFFSET_LEN 11 - #define AC_UNI_QUEUE_CFG_TBL_AC_CFG_YEL_RESUME_OFFSET_DEFAULT 0x0 - /*[field] AC_CFG_GRN_RESUME_OFFSET*/ - #define AC_UNI_QUEUE_CFG_TBL_AC_CFG_GRN_RESUME_OFFSET - #define AC_UNI_QUEUE_CFG_TBL_AC_CFG_GRN_RESUME_OFFSET_OFFSET 109 - #define AC_UNI_QUEUE_CFG_TBL_AC_CFG_GRN_RESUME_OFFSET_LEN 11 - #define AC_UNI_QUEUE_CFG_TBL_AC_CFG_GRN_RESUME_OFFSET_DEFAULT 0x0 - -struct ac_uni_queue_cfg_tbl { - a_uint32_t ac_cfg_ac_en:1; - a_uint32_t ac_cfg_wred_en:1; - a_uint32_t ac_cfg_force_ac_en:1; - a_uint32_t ac_cfg_color_aware:1; - a_uint32_t ac_cfg_grp_id:2; - a_uint32_t ac_cfg_pre_alloc_limit:11; - a_uint32_t ac_cfg_shared_dynamic:1; - a_uint32_t ac_cfg_shared_weight:3; - a_uint32_t ac_cfg_shared_ceiling:11; - a_uint32_t ac_cfg_gap_grn_grn_min:11; - a_uint32_t ac_cfg_gap_grn_yel_max:11; - a_uint32_t ac_cfg_gap_grn_yel_min_0:10; - a_uint32_t ac_cfg_gap_grn_yel_min_1:1; - a_uint32_t ac_cfg_gap_grn_red_max:11; - a_uint32_t ac_cfg_gap_grn_red_min:11; - a_uint32_t ac_cfg_red_resume_offset_0:9; - a_uint32_t ac_cfg_red_resume_offset_1:2; - a_uint32_t ac_cfg_yel_resume_offset:11; - a_uint32_t ac_cfg_grn_resume_offset:11; - a_uint32_t _reserved0:8; -}; - -union ac_uni_queue_cfg_tbl_u { - a_uint32_t val[4]; - struct ac_uni_queue_cfg_tbl bf; -}; - -/*[table] AC_MUL_QUEUE_CFG_TBL*/ -#define AC_MUL_QUEUE_CFG_TBL -#define AC_MUL_QUEUE_CFG_TBL_ADDRESS 0x4a000 -#define AC_MUL_QUEUE_CFG_TBL_NUM 44 -#define AC_MUL_QUEUE_CFG_TBL_INC 0x10 -#define AC_MUL_QUEUE_CFG_TBL_TYPE REG_TYPE_RW -#define AC_MUL_QUEUE_CFG_TBL_DEFAULT 0x0 - /*[field] AC_CFG_AC_EN*/ - #define AC_MUL_QUEUE_CFG_TBL_AC_CFG_AC_EN - #define AC_MUL_QUEUE_CFG_TBL_AC_CFG_AC_EN_OFFSET 0 - #define AC_MUL_QUEUE_CFG_TBL_AC_CFG_AC_EN_LEN 1 - #define AC_MUL_QUEUE_CFG_TBL_AC_CFG_AC_EN_DEFAULT 0x0 - /*[field] AC_CFG_FORCE_AC_EN*/ - #define AC_MUL_QUEUE_CFG_TBL_AC_CFG_FORCE_AC_EN - #define AC_MUL_QUEUE_CFG_TBL_AC_CFG_FORCE_AC_EN_OFFSET 1 - #define AC_MUL_QUEUE_CFG_TBL_AC_CFG_FORCE_AC_EN_LEN 1 - #define AC_MUL_QUEUE_CFG_TBL_AC_CFG_FORCE_AC_EN_DEFAULT 0x0 - /*[field] AC_CFG_COLOR_AWARE*/ - #define AC_MUL_QUEUE_CFG_TBL_AC_CFG_COLOR_AWARE - #define AC_MUL_QUEUE_CFG_TBL_AC_CFG_COLOR_AWARE_OFFSET 2 - #define AC_MUL_QUEUE_CFG_TBL_AC_CFG_COLOR_AWARE_LEN 1 - #define AC_MUL_QUEUE_CFG_TBL_AC_CFG_COLOR_AWARE_DEFAULT 0x0 - /*[field] AC_CFG_GRP_ID*/ - #define AC_MUL_QUEUE_CFG_TBL_AC_CFG_GRP_ID - #define AC_MUL_QUEUE_CFG_TBL_AC_CFG_GRP_ID_OFFSET 3 - #define AC_MUL_QUEUE_CFG_TBL_AC_CFG_GRP_ID_LEN 2 - #define AC_MUL_QUEUE_CFG_TBL_AC_CFG_GRP_ID_DEFAULT 0x0 - /*[field] AC_CFG_PRE_ALLOC_LIMIT*/ - #define AC_MUL_QUEUE_CFG_TBL_AC_CFG_PRE_ALLOC_LIMIT - #define AC_MUL_QUEUE_CFG_TBL_AC_CFG_PRE_ALLOC_LIMIT_OFFSET 5 - #define AC_MUL_QUEUE_CFG_TBL_AC_CFG_PRE_ALLOC_LIMIT_LEN 11 - #define AC_MUL_QUEUE_CFG_TBL_AC_CFG_PRE_ALLOC_LIMIT_DEFAULT 0x0 - /*[field] AC_CFG_SHARED_CEILING*/ - #define AC_MUL_QUEUE_CFG_TBL_AC_CFG_SHARED_CEILING - #define AC_MUL_QUEUE_CFG_TBL_AC_CFG_SHARED_CEILING_OFFSET 16 - #define AC_MUL_QUEUE_CFG_TBL_AC_CFG_SHARED_CEILING_LEN 11 - #define AC_MUL_QUEUE_CFG_TBL_AC_CFG_SHARED_CEILING_DEFAULT 0x0 - /*[field] AC_CFG_GAP_GRN_YEL*/ - #define AC_MUL_QUEUE_CFG_TBL_AC_CFG_GAP_GRN_YEL - #define AC_MUL_QUEUE_CFG_TBL_AC_CFG_GAP_GRN_YEL_OFFSET 27 - #define AC_MUL_QUEUE_CFG_TBL_AC_CFG_GAP_GRN_YEL_LEN 11 - #define AC_MUL_QUEUE_CFG_TBL_AC_CFG_GAP_GRN_YEL_DEFAULT 0x0 - /*[field] AC_CFG_GAP_GRN_RED*/ - #define AC_MUL_QUEUE_CFG_TBL_AC_CFG_GAP_GRN_RED - #define AC_MUL_QUEUE_CFG_TBL_AC_CFG_GAP_GRN_RED_OFFSET 38 - #define AC_MUL_QUEUE_CFG_TBL_AC_CFG_GAP_GRN_RED_LEN 11 - #define AC_MUL_QUEUE_CFG_TBL_AC_CFG_GAP_GRN_RED_DEFAULT 0x0 - /*[field] AC_CFG_RED_RESUME_OFFSET*/ - #define AC_MUL_QUEUE_CFG_TBL_AC_CFG_RED_RESUME_OFFSET - #define AC_MUL_QUEUE_CFG_TBL_AC_CFG_RED_RESUME_OFFSET_OFFSET 49 - #define AC_MUL_QUEUE_CFG_TBL_AC_CFG_RED_RESUME_OFFSET_LEN 11 - #define AC_MUL_QUEUE_CFG_TBL_AC_CFG_RED_RESUME_OFFSET_DEFAULT 0x0 - /*[field] AC_CFG_YEL_RESUME_OFFSET*/ - #define AC_MUL_QUEUE_CFG_TBL_AC_CFG_YEL_RESUME_OFFSET - #define AC_MUL_QUEUE_CFG_TBL_AC_CFG_YEL_RESUME_OFFSET_OFFSET 60 - #define AC_MUL_QUEUE_CFG_TBL_AC_CFG_YEL_RESUME_OFFSET_LEN 11 - #define AC_MUL_QUEUE_CFG_TBL_AC_CFG_YEL_RESUME_OFFSET_DEFAULT 0x0 - /*[field] AC_CFG_GRN_RESUME_OFFSET*/ - #define AC_MUL_QUEUE_CFG_TBL_AC_CFG_GRN_RESUME_OFFSET - #define AC_MUL_QUEUE_CFG_TBL_AC_CFG_GRN_RESUME_OFFSET_OFFSET 71 - #define AC_MUL_QUEUE_CFG_TBL_AC_CFG_GRN_RESUME_OFFSET_LEN 11 - #define AC_MUL_QUEUE_CFG_TBL_AC_CFG_GRN_RESUME_OFFSET_DEFAULT 0x0 - -struct ac_mul_queue_cfg_tbl { - a_uint32_t ac_cfg_ac_en:1; - a_uint32_t ac_cfg_force_ac_en:1; - a_uint32_t ac_cfg_color_aware:1; - a_uint32_t ac_cfg_grp_id:2; - a_uint32_t ac_cfg_pre_alloc_limit:11; - a_uint32_t ac_cfg_shared_ceiling:11; - a_uint32_t ac_cfg_gap_grn_yel_0:5; - a_uint32_t ac_cfg_gap_grn_yel_1:6; - a_uint32_t ac_cfg_gap_grn_red:11; - a_uint32_t ac_cfg_red_resume_offset:11; - a_uint32_t ac_cfg_yel_resume_offset_0:4; - a_uint32_t ac_cfg_yel_resume_offset_1:7; - a_uint32_t ac_cfg_grn_resume_offset:11; - a_uint32_t _reserved0:14; -}; - -union ac_mul_queue_cfg_tbl_u { - a_uint32_t val[3]; - struct ac_mul_queue_cfg_tbl bf; -}; - -/*[table] AC_GRP_CFG_TBL*/ -#define AC_GRP_CFG_TBL -#define AC_GRP_CFG_TBL_ADDRESS 0x4c000 -#define AC_GRP_CFG_TBL_NUM 4 -#define AC_GRP_CFG_TBL_INC 0x10 -#define AC_GRP_CFG_TBL_TYPE REG_TYPE_RW -#define AC_GRP_CFG_TBL_DEFAULT 0x0 - /*[field] AC_CFG_AC_EN*/ - #define AC_GRP_CFG_TBL_AC_CFG_AC_EN - #define AC_GRP_CFG_TBL_AC_CFG_AC_EN_OFFSET 0 - #define AC_GRP_CFG_TBL_AC_CFG_AC_EN_LEN 1 - #define AC_GRP_CFG_TBL_AC_CFG_AC_EN_DEFAULT 0x0 - /*[field] AC_CFG_FORCE_AC_EN*/ - #define AC_GRP_CFG_TBL_AC_CFG_FORCE_AC_EN - #define AC_GRP_CFG_TBL_AC_CFG_FORCE_AC_EN_OFFSET 1 - #define AC_GRP_CFG_TBL_AC_CFG_FORCE_AC_EN_LEN 1 - #define AC_GRP_CFG_TBL_AC_CFG_FORCE_AC_EN_DEFAULT 0x0 - /*[field] AC_CFG_COLOR_AWARE*/ - #define AC_GRP_CFG_TBL_AC_CFG_COLOR_AWARE - #define AC_GRP_CFG_TBL_AC_CFG_COLOR_AWARE_OFFSET 2 - #define AC_GRP_CFG_TBL_AC_CFG_COLOR_AWARE_LEN 1 - #define AC_GRP_CFG_TBL_AC_CFG_COLOR_AWARE_DEFAULT 0x0 - /*[field] AC_GRP_GAP_GRN_RED*/ - #define AC_GRP_CFG_TBL_AC_GRP_GAP_GRN_RED - #define AC_GRP_CFG_TBL_AC_GRP_GAP_GRN_RED_OFFSET 3 - #define AC_GRP_CFG_TBL_AC_GRP_GAP_GRN_RED_LEN 11 - #define AC_GRP_CFG_TBL_AC_GRP_GAP_GRN_RED_DEFAULT 0x0 - /*[field] AC_GRP_GAP_GRN_YEL*/ - #define AC_GRP_CFG_TBL_AC_GRP_GAP_GRN_YEL - #define AC_GRP_CFG_TBL_AC_GRP_GAP_GRN_YEL_OFFSET 14 - #define AC_GRP_CFG_TBL_AC_GRP_GAP_GRN_YEL_LEN 11 - #define AC_GRP_CFG_TBL_AC_GRP_GAP_GRN_YEL_DEFAULT 0x0 - /*[field] AC_GRP_DP_THRD*/ - #define AC_GRP_CFG_TBL_AC_GRP_DP_THRD - #define AC_GRP_CFG_TBL_AC_GRP_DP_THRD_OFFSET 25 - #define AC_GRP_CFG_TBL_AC_GRP_DP_THRD_LEN 11 - #define AC_GRP_CFG_TBL_AC_GRP_DP_THRD_DEFAULT 0x0 - /*[field] AC_GRP_LIMIT*/ - #define AC_GRP_CFG_TBL_AC_GRP_LIMIT - #define AC_GRP_CFG_TBL_AC_GRP_LIMIT_OFFSET 36 - #define AC_GRP_CFG_TBL_AC_GRP_LIMIT_LEN 11 - #define AC_GRP_CFG_TBL_AC_GRP_LIMIT_DEFAULT 0x0 - /*[field] AC_GRP_RED_RESUME_OFFSET*/ - #define AC_GRP_CFG_TBL_AC_GRP_RED_RESUME_OFFSET - #define AC_GRP_CFG_TBL_AC_GRP_RED_RESUME_OFFSET_OFFSET 47 - #define AC_GRP_CFG_TBL_AC_GRP_RED_RESUME_OFFSET_LEN 11 - #define AC_GRP_CFG_TBL_AC_GRP_RED_RESUME_OFFSET_DEFAULT 0x0 - /*[field] AC_GRP_YEL_RESUME_OFFSET*/ - #define AC_GRP_CFG_TBL_AC_GRP_YEL_RESUME_OFFSET - #define AC_GRP_CFG_TBL_AC_GRP_YEL_RESUME_OFFSET_OFFSET 58 - #define AC_GRP_CFG_TBL_AC_GRP_YEL_RESUME_OFFSET_LEN 11 - #define AC_GRP_CFG_TBL_AC_GRP_YEL_RESUME_OFFSET_DEFAULT 0x0 - /*[field] AC_GRP_GRN_RESUME_OFFSET*/ - #define AC_GRP_CFG_TBL_AC_GRP_GRN_RESUME_OFFSET - #define AC_GRP_CFG_TBL_AC_GRP_GRN_RESUME_OFFSET_OFFSET 69 - #define AC_GRP_CFG_TBL_AC_GRP_GRN_RESUME_OFFSET_LEN 11 - #define AC_GRP_CFG_TBL_AC_GRP_GRN_RESUME_OFFSET_DEFAULT 0x0 - /*[field] AC_GRP_PALLOC_LIMIT*/ - #define AC_GRP_CFG_TBL_AC_GRP_PALLOC_LIMIT - #define AC_GRP_CFG_TBL_AC_GRP_PALLOC_LIMIT_OFFSET 80 - #define AC_GRP_CFG_TBL_AC_GRP_PALLOC_LIMIT_LEN 11 - #define AC_GRP_CFG_TBL_AC_GRP_PALLOC_LIMIT_DEFAULT 0x0 - -struct ac_grp_cfg_tbl { - a_uint32_t ac_cfg_ac_en:1; - a_uint32_t ac_cfg_force_ac_en:1; - a_uint32_t ac_cfg_color_aware:1; - a_uint32_t ac_grp_gap_grn_red:11; - a_uint32_t ac_grp_gap_grn_yel:11; - a_uint32_t ac_grp_dp_thrd_0:7; - a_uint32_t ac_grp_dp_thrd_1:4; - a_uint32_t ac_grp_limit:11; - a_uint32_t ac_grp_red_resume_offset:11; - a_uint32_t ac_grp_yel_resume_offset_0:6; - a_uint32_t ac_grp_yel_resume_offset_1:5; - a_uint32_t ac_grp_grn_resume_offset:11; - a_uint32_t ac_grp_palloc_limit:11; - a_uint32_t _reserved0:5; -}; - -union ac_grp_cfg_tbl_u { - a_uint32_t val[3]; - struct ac_grp_cfg_tbl bf; -}; - -/*[table] AC_UNI_QUEUE_CNT_TBL*/ -#define AC_UNI_QUEUE_CNT_TBL -#define AC_UNI_QUEUE_CNT_TBL_ADDRESS 0x4e000 -#define AC_UNI_QUEUE_CNT_TBL_NUM 256 -#define AC_UNI_QUEUE_CNT_TBL_INC 0x10 -#define AC_UNI_QUEUE_CNT_TBL_TYPE REG_TYPE_RW -#define AC_UNI_QUEUE_CNT_TBL_DEFAULT 0x0 - /*[field] AC_UNI_QUEUE_CNT*/ - #define AC_UNI_QUEUE_CNT_TBL_AC_UNI_QUEUE_CNT - #define AC_UNI_QUEUE_CNT_TBL_AC_UNI_QUEUE_CNT_OFFSET 0 - #define AC_UNI_QUEUE_CNT_TBL_AC_UNI_QUEUE_CNT_LEN 12 - #define AC_UNI_QUEUE_CNT_TBL_AC_UNI_QUEUE_CNT_DEFAULT 0x0 - -struct ac_uni_queue_cnt_tbl { - a_uint32_t ac_uni_queue_cnt:12; - a_uint32_t _reserved0:20; -}; - -union ac_uni_queue_cnt_tbl_u { - a_uint32_t val; - struct ac_uni_queue_cnt_tbl bf; -}; - -/*[table] AC_MUL_QUEUE_CNT_TBL*/ -#define AC_MUL_QUEUE_CNT_TBL -#define AC_MUL_QUEUE_CNT_TBL_ADDRESS 0x52000 -#define AC_MUL_QUEUE_CNT_TBL_NUM 44 -#define AC_MUL_QUEUE_CNT_TBL_INC 0x10 -#define AC_MUL_QUEUE_CNT_TBL_TYPE REG_TYPE_RW -#define AC_MUL_QUEUE_CNT_TBL_DEFAULT 0x0 - /*[field] AC_MUL_QUEUE_CNT*/ - #define AC_MUL_QUEUE_CNT_TBL_AC_MUL_QUEUE_CNT - #define AC_MUL_QUEUE_CNT_TBL_AC_MUL_QUEUE_CNT_OFFSET 0 - #define AC_MUL_QUEUE_CNT_TBL_AC_MUL_QUEUE_CNT_LEN 13 - #define AC_MUL_QUEUE_CNT_TBL_AC_MUL_QUEUE_CNT_DEFAULT 0x0 - -struct ac_mul_queue_cnt_tbl { - a_uint32_t ac_mul_queue_cnt:13; - a_uint32_t _reserved0:19; -}; - -union ac_mul_queue_cnt_tbl_u { - a_uint32_t val; - struct ac_mul_queue_cnt_tbl bf; -}; - -/*[table] AC_GRP_CNT_TBL*/ -#define AC_GRP_CNT_TBL -#define AC_GRP_CNT_TBL_ADDRESS 0x54000 -#define AC_GRP_CNT_TBL_NUM 4 -#define AC_GRP_CNT_TBL_INC 0x10 -#define AC_GRP_CNT_TBL_TYPE REG_TYPE_RW -#define AC_GRP_CNT_TBL_DEFAULT 0x0 - /*[field] AC_GRP_CNT*/ - #define AC_GRP_CNT_TBL_AC_GRP_CNT - #define AC_GRP_CNT_TBL_AC_GRP_CNT_OFFSET 0 - #define AC_GRP_CNT_TBL_AC_GRP_CNT_LEN 16 - #define AC_GRP_CNT_TBL_AC_GRP_CNT_DEFAULT 0x0 - /*[field] AC_GRP_ALLOC_USED*/ - #define AC_GRP_CNT_TBL_AC_GRP_ALLOC_USED - #define AC_GRP_CNT_TBL_AC_GRP_ALLOC_USED_OFFSET 16 - #define AC_GRP_CNT_TBL_AC_GRP_ALLOC_USED_LEN 16 - #define AC_GRP_CNT_TBL_AC_GRP_ALLOC_USED_DEFAULT 0x0 - -struct ac_grp_cnt_tbl { - a_uint32_t ac_grp_cnt:16; - a_uint32_t ac_grp_alloc_used:16; -}; - -union ac_grp_cnt_tbl_u { - a_uint32_t val; - struct ac_grp_cnt_tbl bf; -}; - -/*[table] AC_UNI_QUEUE_DROP_STATE_TBL*/ -#define AC_UNI_QUEUE_DROP_STATE_TBL -#define AC_UNI_QUEUE_DROP_STATE_TBL_ADDRESS 0x56000 -#define AC_UNI_QUEUE_DROP_STATE_TBL_NUM 256 -#define AC_UNI_QUEUE_DROP_STATE_TBL_INC 0x10 -#define AC_UNI_QUEUE_DROP_STATE_TBL_TYPE REG_TYPE_RW -#define AC_UNI_QUEUE_DROP_STATE_TBL_DEFAULT 0x0 - /*[field] RED_RESUME_THRD*/ - #define AC_UNI_QUEUE_DROP_STATE_TBL_RED_RESUME_THRD - #define AC_UNI_QUEUE_DROP_STATE_TBL_RED_RESUME_THRD_OFFSET 0 - #define AC_UNI_QUEUE_DROP_STATE_TBL_RED_RESUME_THRD_LEN 11 - #define AC_UNI_QUEUE_DROP_STATE_TBL_RED_RESUME_THRD_DEFAULT 0x0 - /*[field] YEL_RESUME_THRD*/ - #define AC_UNI_QUEUE_DROP_STATE_TBL_YEL_RESUME_THRD - #define AC_UNI_QUEUE_DROP_STATE_TBL_YEL_RESUME_THRD_OFFSET 11 - #define AC_UNI_QUEUE_DROP_STATE_TBL_YEL_RESUME_THRD_LEN 11 - #define AC_UNI_QUEUE_DROP_STATE_TBL_YEL_RESUME_THRD_DEFAULT 0x0 - /*[field] GRN_RESUME_THRD*/ - #define AC_UNI_QUEUE_DROP_STATE_TBL_GRN_RESUME_THRD - #define AC_UNI_QUEUE_DROP_STATE_TBL_GRN_RESUME_THRD_OFFSET 22 - #define AC_UNI_QUEUE_DROP_STATE_TBL_GRN_RESUME_THRD_LEN 11 - #define AC_UNI_QUEUE_DROP_STATE_TBL_GRN_RESUME_THRD_DEFAULT 0x0 - /*[field] RED_DROP_STATE*/ - #define AC_UNI_QUEUE_DROP_STATE_TBL_RED_DROP_STATE - #define AC_UNI_QUEUE_DROP_STATE_TBL_RED_DROP_STATE_OFFSET 33 - #define AC_UNI_QUEUE_DROP_STATE_TBL_RED_DROP_STATE_LEN 4 - #define AC_UNI_QUEUE_DROP_STATE_TBL_RED_DROP_STATE_DEFAULT 0x0 - /*[field] YEL_DROP_STATE*/ - #define AC_UNI_QUEUE_DROP_STATE_TBL_YEL_DROP_STATE - #define AC_UNI_QUEUE_DROP_STATE_TBL_YEL_DROP_STATE_OFFSET 37 - #define AC_UNI_QUEUE_DROP_STATE_TBL_YEL_DROP_STATE_LEN 4 - #define AC_UNI_QUEUE_DROP_STATE_TBL_YEL_DROP_STATE_DEFAULT 0x0 - /*[field] GRN_DROP_STATE*/ - #define AC_UNI_QUEUE_DROP_STATE_TBL_GRN_DROP_STATE - #define AC_UNI_QUEUE_DROP_STATE_TBL_GRN_DROP_STATE_OFFSET 41 - #define AC_UNI_QUEUE_DROP_STATE_TBL_GRN_DROP_STATE_LEN 4 - #define AC_UNI_QUEUE_DROP_STATE_TBL_GRN_DROP_STATE_DEFAULT 0x0 - -struct ac_uni_queue_drop_state_tbl { - a_uint32_t red_resume_thrd:11; - a_uint32_t yel_resume_thrd:11; - a_uint32_t grn_resume_thrd_0:10; - a_uint32_t grn_resume_thrd_1:1; - a_uint32_t red_drop_state:4; - a_uint32_t yel_drop_state:4; - a_uint32_t grn_drop_state:4; - a_uint32_t _reserved0:19; -}; - -union ac_uni_queue_drop_state_tbl_u { - a_uint32_t val[2]; - struct ac_uni_queue_drop_state_tbl bf; -}; - -/*[table] AC_MUL_QUEUE_DROP_STATE_TBL*/ -#define AC_MUL_QUEUE_DROP_STATE_TBL -#define AC_MUL_QUEUE_DROP_STATE_TBL_ADDRESS 0x58000 -#define AC_MUL_QUEUE_DROP_STATE_TBL_NUM 44 -#define AC_MUL_QUEUE_DROP_STATE_TBL_INC 0x10 -#define AC_MUL_QUEUE_DROP_STATE_TBL_TYPE REG_TYPE_RW -#define AC_MUL_QUEUE_DROP_STATE_TBL_DEFAULT 0x0 - /*[field] RED_RESUME_THRD*/ - #define AC_MUL_QUEUE_DROP_STATE_TBL_RED_RESUME_THRD - #define AC_MUL_QUEUE_DROP_STATE_TBL_RED_RESUME_THRD_OFFSET 0 - #define AC_MUL_QUEUE_DROP_STATE_TBL_RED_RESUME_THRD_LEN 11 - #define AC_MUL_QUEUE_DROP_STATE_TBL_RED_RESUME_THRD_DEFAULT 0x0 - /*[field] YEL_RESUME_THRD*/ - #define AC_MUL_QUEUE_DROP_STATE_TBL_YEL_RESUME_THRD - #define AC_MUL_QUEUE_DROP_STATE_TBL_YEL_RESUME_THRD_OFFSET 11 - #define AC_MUL_QUEUE_DROP_STATE_TBL_YEL_RESUME_THRD_LEN 11 - #define AC_MUL_QUEUE_DROP_STATE_TBL_YEL_RESUME_THRD_DEFAULT 0x0 - /*[field] GRN_RESUME_THRD*/ - #define AC_MUL_QUEUE_DROP_STATE_TBL_GRN_RESUME_THRD - #define AC_MUL_QUEUE_DROP_STATE_TBL_GRN_RESUME_THRD_OFFSET 22 - #define AC_MUL_QUEUE_DROP_STATE_TBL_GRN_RESUME_THRD_LEN 11 - #define AC_MUL_QUEUE_DROP_STATE_TBL_GRN_RESUME_THRD_DEFAULT 0x0 - /*[field] RED_DROP_STATE*/ - #define AC_MUL_QUEUE_DROP_STATE_TBL_RED_DROP_STATE - #define AC_MUL_QUEUE_DROP_STATE_TBL_RED_DROP_STATE_OFFSET 33 - #define AC_MUL_QUEUE_DROP_STATE_TBL_RED_DROP_STATE_LEN 1 - #define AC_MUL_QUEUE_DROP_STATE_TBL_RED_DROP_STATE_DEFAULT 0x0 - /*[field] YEL_DROP_STATE*/ - #define AC_MUL_QUEUE_DROP_STATE_TBL_YEL_DROP_STATE - #define AC_MUL_QUEUE_DROP_STATE_TBL_YEL_DROP_STATE_OFFSET 34 - #define AC_MUL_QUEUE_DROP_STATE_TBL_YEL_DROP_STATE_LEN 1 - #define AC_MUL_QUEUE_DROP_STATE_TBL_YEL_DROP_STATE_DEFAULT 0x0 - /*[field] GRN_DROP_STATE*/ - #define AC_MUL_QUEUE_DROP_STATE_TBL_GRN_DROP_STATE - #define AC_MUL_QUEUE_DROP_STATE_TBL_GRN_DROP_STATE_OFFSET 35 - #define AC_MUL_QUEUE_DROP_STATE_TBL_GRN_DROP_STATE_LEN 1 - #define AC_MUL_QUEUE_DROP_STATE_TBL_GRN_DROP_STATE_DEFAULT 0x0 - -struct ac_mul_queue_drop_state_tbl { - a_uint32_t red_resume_thrd:11; - a_uint32_t yel_resume_thrd:11; - a_uint32_t grn_resume_thrd_0:10; - a_uint32_t grn_resume_thrd_1:1; - a_uint32_t red_drop_state:1; - a_uint32_t yel_drop_state:1; - a_uint32_t grn_drop_state:1; - a_uint32_t _reserved0:28; -}; - -union ac_mul_queue_drop_state_tbl_u { - a_uint32_t val[2]; - struct ac_mul_queue_drop_state_tbl bf; -}; - -/*[table] AC_GRP_DROP_STATE_TBL*/ -#define AC_GRP_DROP_STATE_TBL -#define AC_GRP_DROP_STATE_TBL_ADDRESS 0x5a000 -#define AC_GRP_DROP_STATE_TBL_NUM 4 -#define AC_GRP_DROP_STATE_TBL_INC 0x10 -#define AC_GRP_DROP_STATE_TBL_TYPE REG_TYPE_RW -#define AC_GRP_DROP_STATE_TBL_DEFAULT 0x0 - /*[field] RED_RESUME_THRD*/ - #define AC_GRP_DROP_STATE_TBL_RED_RESUME_THRD - #define AC_GRP_DROP_STATE_TBL_RED_RESUME_THRD_OFFSET 0 - #define AC_GRP_DROP_STATE_TBL_RED_RESUME_THRD_LEN 11 - #define AC_GRP_DROP_STATE_TBL_RED_RESUME_THRD_DEFAULT 0x0 - /*[field] YEL_RESUME_THRD*/ - #define AC_GRP_DROP_STATE_TBL_YEL_RESUME_THRD - #define AC_GRP_DROP_STATE_TBL_YEL_RESUME_THRD_OFFSET 11 - #define AC_GRP_DROP_STATE_TBL_YEL_RESUME_THRD_LEN 11 - #define AC_GRP_DROP_STATE_TBL_YEL_RESUME_THRD_DEFAULT 0x0 - /*[field] GRN_RESUME_THRD*/ - #define AC_GRP_DROP_STATE_TBL_GRN_RESUME_THRD - #define AC_GRP_DROP_STATE_TBL_GRN_RESUME_THRD_OFFSET 22 - #define AC_GRP_DROP_STATE_TBL_GRN_RESUME_THRD_LEN 11 - #define AC_GRP_DROP_STATE_TBL_GRN_RESUME_THRD_DEFAULT 0x0 - /*[field] RED_DROP_STATE*/ - #define AC_GRP_DROP_STATE_TBL_RED_DROP_STATE - #define AC_GRP_DROP_STATE_TBL_RED_DROP_STATE_OFFSET 33 - #define AC_GRP_DROP_STATE_TBL_RED_DROP_STATE_LEN 1 - #define AC_GRP_DROP_STATE_TBL_RED_DROP_STATE_DEFAULT 0x0 - /*[field] YEL_DROP_STATE*/ - #define AC_GRP_DROP_STATE_TBL_YEL_DROP_STATE - #define AC_GRP_DROP_STATE_TBL_YEL_DROP_STATE_OFFSET 34 - #define AC_GRP_DROP_STATE_TBL_YEL_DROP_STATE_LEN 1 - #define AC_GRP_DROP_STATE_TBL_YEL_DROP_STATE_DEFAULT 0x0 - /*[field] GRN_DROP_STATE*/ - #define AC_GRP_DROP_STATE_TBL_GRN_DROP_STATE - #define AC_GRP_DROP_STATE_TBL_GRN_DROP_STATE_OFFSET 35 - #define AC_GRP_DROP_STATE_TBL_GRN_DROP_STATE_LEN 1 - #define AC_GRP_DROP_STATE_TBL_GRN_DROP_STATE_DEFAULT 0x0 - -struct ac_grp_drop_state_tbl { - a_uint32_t red_resume_thrd:11; - a_uint32_t yel_resume_thrd:11; - a_uint32_t grn_resume_thrd_0:10; - a_uint32_t grn_resume_thrd_1:1; - a_uint32_t red_drop_state:1; - a_uint32_t yel_drop_state:1; - a_uint32_t grn_drop_state:1; - a_uint32_t _reserved0:28; -}; - -union ac_grp_drop_state_tbl_u { - a_uint32_t val[2]; - struct ac_grp_drop_state_tbl bf; -}; - -/*[table] OQ_ENQ_OPR_TBL*/ -#define OQ_ENQ_OPR_TBL -#define OQ_ENQ_OPR_TBL_ADDRESS 0x5c000 -#define OQ_ENQ_OPR_TBL_NUM 300 -#define OQ_ENQ_OPR_TBL_INC 0x10 -#define OQ_ENQ_OPR_TBL_TYPE REG_TYPE_RW -#define OQ_ENQ_OPR_TBL_DEFAULT 0x0 - /*[field] ENQ_DISABLE*/ - #define OQ_ENQ_OPR_TBL_ENQ_DISABLE - #define OQ_ENQ_OPR_TBL_ENQ_DISABLE_OFFSET 0 - #define OQ_ENQ_OPR_TBL_ENQ_DISABLE_LEN 1 - #define OQ_ENQ_OPR_TBL_ENQ_DISABLE_DEFAULT 0x0 - -struct oq_enq_opr_tbl { - a_uint32_t enq_disable:1; - a_uint32_t _reserved0:31; -}; - -union oq_enq_opr_tbl_u { - a_uint32_t val; - struct oq_enq_opr_tbl bf; -}; - -/*[table] OQ_DEQ_OPR_TBL*/ -#define OQ_DEQ_OPR_TBL -#define OQ_DEQ_OPR_TBL_ADDRESS 0x64000 -#define OQ_DEQ_OPR_TBL_NUM 300 -#define OQ_DEQ_OPR_TBL_INC 0x10 -#define OQ_DEQ_OPR_TBL_TYPE REG_TYPE_RW -#define OQ_DEQ_OPR_TBL_DEFAULT 0x0 - /*[field] DEQ_DROP*/ - #define OQ_DEQ_OPR_TBL_DEQ_DROP - #define OQ_DEQ_OPR_TBL_DEQ_DROP_OFFSET 0 - #define OQ_DEQ_OPR_TBL_DEQ_DROP_LEN 1 - #define OQ_DEQ_OPR_TBL_DEQ_DROP_DEFAULT 0x0 - -struct oq_deq_opr_tbl { - a_uint32_t deq_drop:1; - a_uint32_t _reserved0:31; -}; - -union oq_deq_opr_tbl_u { - a_uint32_t val; - struct oq_deq_opr_tbl bf; -}; - -/*[table] OQ_HEAD_UNI_TBL*/ -#define OQ_HEAD_UNI_TBL -#define OQ_HEAD_UNI_TBL_ADDRESS 0x6c000 -#define OQ_HEAD_UNI_TBL_NUM 256 -#define OQ_HEAD_UNI_TBL_INC 0x10 -#define OQ_HEAD_UNI_TBL_TYPE REG_TYPE_RW -#define OQ_HEAD_UNI_TBL_DEFAULT 0x0 - /*[field] EMPTY*/ - #define OQ_HEAD_UNI_TBL_EMPTY - #define OQ_HEAD_UNI_TBL_EMPTY_OFFSET 0 - #define OQ_HEAD_UNI_TBL_EMPTY_LEN 1 - #define OQ_HEAD_UNI_TBL_EMPTY_DEFAULT 0x0 - /*[field] TAIL*/ - #define OQ_HEAD_UNI_TBL_TAIL - #define OQ_HEAD_UNI_TBL_TAIL_OFFSET 1 - #define OQ_HEAD_UNI_TBL_TAIL_LEN 11 - #define OQ_HEAD_UNI_TBL_TAIL_DEFAULT 0x0 - /*[field] HEAD*/ - #define OQ_HEAD_UNI_TBL_HEAD - #define OQ_HEAD_UNI_TBL_HEAD_OFFSET 12 - #define OQ_HEAD_UNI_TBL_HEAD_LEN 11 - #define OQ_HEAD_UNI_TBL_HEAD_DEFAULT 0x0 - -struct oq_head_uni_tbl { - a_uint32_t empty:1; - a_uint32_t tail:11; - a_uint32_t head:11; - a_uint32_t _reserved0:9; -}; - -union oq_head_uni_tbl_u { - a_uint32_t val; - struct oq_head_uni_tbl bf; -}; - -/*[table] OQ_HEAD_MUL_TBL*/ -#define OQ_HEAD_MUL_TBL -#define OQ_HEAD_MUL_TBL_ADDRESS 0x74000 -#define OQ_HEAD_MUL_TBL_NUM 44 -#define OQ_HEAD_MUL_TBL_INC 0x10 -#define OQ_HEAD_MUL_TBL_TYPE REG_TYPE_RW -#define OQ_HEAD_MUL_TBL_DEFAULT 0x0 - /*[field] NORMAL_FWD*/ - #define OQ_HEAD_MUL_TBL_NORMAL_FWD - #define OQ_HEAD_MUL_TBL_NORMAL_FWD_OFFSET 0 - #define OQ_HEAD_MUL_TBL_NORMAL_FWD_LEN 1 - #define OQ_HEAD_MUL_TBL_NORMAL_FWD_DEFAULT 0x0 - /*[field] EGRESS_MIRR*/ - #define OQ_HEAD_MUL_TBL_EGRESS_MIRR - #define OQ_HEAD_MUL_TBL_EGRESS_MIRR_OFFSET 1 - #define OQ_HEAD_MUL_TBL_EGRESS_MIRR_LEN 1 - #define OQ_HEAD_MUL_TBL_EGRESS_MIRR_DEFAULT 0x0 - /*[field] INGRESS_MIRR*/ - #define OQ_HEAD_MUL_TBL_INGRESS_MIRR - #define OQ_HEAD_MUL_TBL_INGRESS_MIRR_OFFSET 2 - #define OQ_HEAD_MUL_TBL_INGRESS_MIRR_LEN 1 - #define OQ_HEAD_MUL_TBL_INGRESS_MIRR_DEFAULT 0x0 - /*[field] EMPTY*/ - #define OQ_HEAD_MUL_TBL_EMPTY - #define OQ_HEAD_MUL_TBL_EMPTY_OFFSET 3 - #define OQ_HEAD_MUL_TBL_EMPTY_LEN 1 - #define OQ_HEAD_MUL_TBL_EMPTY_DEFAULT 0x0 - /*[field] TAIL*/ - #define OQ_HEAD_MUL_TBL_TAIL - #define OQ_HEAD_MUL_TBL_TAIL_OFFSET 4 - #define OQ_HEAD_MUL_TBL_TAIL_LEN 11 - #define OQ_HEAD_MUL_TBL_TAIL_DEFAULT 0x0 - /*[field] HEAD*/ - #define OQ_HEAD_MUL_TBL_HEAD - #define OQ_HEAD_MUL_TBL_HEAD_OFFSET 15 - #define OQ_HEAD_MUL_TBL_HEAD_LEN 11 - #define OQ_HEAD_MUL_TBL_HEAD_DEFAULT 0x0 - -struct oq_head_mul_tbl { - a_uint32_t normal_fwd:1; - a_uint32_t egress_mirr:1; - a_uint32_t ingress_mirr:1; - a_uint32_t empty:1; - a_uint32_t tail:11; - a_uint32_t head:11; - a_uint32_t _reserved0:6; -}; - -union oq_head_mul_tbl_u { - a_uint32_t val; - struct oq_head_mul_tbl bf; -}; - -/*[table] OQ_LL_UNI_TBL*/ -#define OQ_LL_UNI_TBL -#define OQ_LL_UNI_TBL_ADDRESS 0x90000 -#define OQ_LL_UNI_TBL_NUM 2048 -#define OQ_LL_UNI_TBL_INC 0x10 -#define OQ_LL_UNI_TBL_TYPE REG_TYPE_RW -#define OQ_LL_UNI_TBL_DEFAULT 0x0 - /*[field] NEXT_POINTER*/ - #define OQ_LL_UNI_TBL_NEXT_POINTER - #define OQ_LL_UNI_TBL_NEXT_POINTER_OFFSET 0 - #define OQ_LL_UNI_TBL_NEXT_POINTER_LEN 11 - #define OQ_LL_UNI_TBL_NEXT_POINTER_DEFAULT 0x0 - -struct oq_ll_uni_tbl { - a_uint32_t next_pointer:11; - a_uint32_t _reserved0:21; -}; - -union oq_ll_uni_tbl_u { - a_uint32_t val; - struct oq_ll_uni_tbl bf; -}; - -/*[table] OQ_LL_MUL_P0_TBL*/ -#define OQ_LL_MUL_P0_TBL -#define OQ_LL_MUL_P0_TBL_ADDRESS 0xb0000 -#define OQ_LL_MUL_P0_TBL_NUM 2048 -#define OQ_LL_MUL_P0_TBL_INC 0x10 -#define OQ_LL_MUL_P0_TBL_TYPE REG_TYPE_RW -#define OQ_LL_MUL_P0_TBL_DEFAULT 0x0 - /*[field] NORMAL_FWD*/ - #define OQ_LL_MUL_P0_TBL_NORMAL_FWD - #define OQ_LL_MUL_P0_TBL_NORMAL_FWD_OFFSET 0 - #define OQ_LL_MUL_P0_TBL_NORMAL_FWD_LEN 1 - #define OQ_LL_MUL_P0_TBL_NORMAL_FWD_DEFAULT 0x0 - /*[field] EGRESS_MIRR*/ - #define OQ_LL_MUL_P0_TBL_EGRESS_MIRR - #define OQ_LL_MUL_P0_TBL_EGRESS_MIRR_OFFSET 1 - #define OQ_LL_MUL_P0_TBL_EGRESS_MIRR_LEN 1 - #define OQ_LL_MUL_P0_TBL_EGRESS_MIRR_DEFAULT 0x0 - /*[field] INGRESS_MIRR*/ - #define OQ_LL_MUL_P0_TBL_INGRESS_MIRR - #define OQ_LL_MUL_P0_TBL_INGRESS_MIRR_OFFSET 2 - #define OQ_LL_MUL_P0_TBL_INGRESS_MIRR_LEN 1 - #define OQ_LL_MUL_P0_TBL_INGRESS_MIRR_DEFAULT 0x0 - /*[field] NEXT_POINTER*/ - #define OQ_LL_MUL_P0_TBL_NEXT_POINTER - #define OQ_LL_MUL_P0_TBL_NEXT_POINTER_OFFSET 3 - #define OQ_LL_MUL_P0_TBL_NEXT_POINTER_LEN 11 - #define OQ_LL_MUL_P0_TBL_NEXT_POINTER_DEFAULT 0x0 - -struct oq_ll_mul_p0_tbl { - a_uint32_t normal_fwd:1; - a_uint32_t egress_mirr:1; - a_uint32_t ingress_mirr:1; - a_uint32_t next_pointer:11; - a_uint32_t _reserved0:18; -}; - -union oq_ll_mul_p0_tbl_u { - a_uint32_t val; - struct oq_ll_mul_p0_tbl bf; -}; - -/*[table] OQ_LL_MUL_P1_TBL*/ -#define OQ_LL_MUL_P1_TBL -#define OQ_LL_MUL_P1_TBL_ADDRESS 0xd0000 -#define OQ_LL_MUL_P1_TBL_NUM 2048 -#define OQ_LL_MUL_P1_TBL_INC 0x10 -#define OQ_LL_MUL_P1_TBL_TYPE REG_TYPE_RW -#define OQ_LL_MUL_P1_TBL_DEFAULT 0x0 - /*[field] NORMAL_FWD*/ - #define OQ_LL_MUL_P1_TBL_NORMAL_FWD - #define OQ_LL_MUL_P1_TBL_NORMAL_FWD_OFFSET 0 - #define OQ_LL_MUL_P1_TBL_NORMAL_FWD_LEN 1 - #define OQ_LL_MUL_P1_TBL_NORMAL_FWD_DEFAULT 0x0 - /*[field] EGRESS_MIRR*/ - #define OQ_LL_MUL_P1_TBL_EGRESS_MIRR - #define OQ_LL_MUL_P1_TBL_EGRESS_MIRR_OFFSET 1 - #define OQ_LL_MUL_P1_TBL_EGRESS_MIRR_LEN 1 - #define OQ_LL_MUL_P1_TBL_EGRESS_MIRR_DEFAULT 0x0 - /*[field] INGRESS_MIRR*/ - #define OQ_LL_MUL_P1_TBL_INGRESS_MIRR - #define OQ_LL_MUL_P1_TBL_INGRESS_MIRR_OFFSET 2 - #define OQ_LL_MUL_P1_TBL_INGRESS_MIRR_LEN 1 - #define OQ_LL_MUL_P1_TBL_INGRESS_MIRR_DEFAULT 0x0 - /*[field] NEXT_POINTER*/ - #define OQ_LL_MUL_P1_TBL_NEXT_POINTER - #define OQ_LL_MUL_P1_TBL_NEXT_POINTER_OFFSET 3 - #define OQ_LL_MUL_P1_TBL_NEXT_POINTER_LEN 11 - #define OQ_LL_MUL_P1_TBL_NEXT_POINTER_DEFAULT 0x0 - -struct oq_ll_mul_p1_tbl { - a_uint32_t normal_fwd:1; - a_uint32_t egress_mirr:1; - a_uint32_t ingress_mirr:1; - a_uint32_t next_pointer:11; - a_uint32_t _reserved0:18; -}; - -union oq_ll_mul_p1_tbl_u { - a_uint32_t val; - struct oq_ll_mul_p1_tbl bf; -}; - -/*[table] OQ_LL_MUL_P2_TBL*/ -#define OQ_LL_MUL_P2_TBL -#define OQ_LL_MUL_P2_TBL_ADDRESS 0x110000 -#define OQ_LL_MUL_P2_TBL_NUM 2048 -#define OQ_LL_MUL_P2_TBL_INC 0x10 -#define OQ_LL_MUL_P2_TBL_TYPE REG_TYPE_RW -#define OQ_LL_MUL_P2_TBL_DEFAULT 0x0 - /*[field] NORMAL_FWD*/ - #define OQ_LL_MUL_P2_TBL_NORMAL_FWD - #define OQ_LL_MUL_P2_TBL_NORMAL_FWD_OFFSET 0 - #define OQ_LL_MUL_P2_TBL_NORMAL_FWD_LEN 1 - #define OQ_LL_MUL_P2_TBL_NORMAL_FWD_DEFAULT 0x0 - /*[field] EGRESS_MIRR*/ - #define OQ_LL_MUL_P2_TBL_EGRESS_MIRR - #define OQ_LL_MUL_P2_TBL_EGRESS_MIRR_OFFSET 1 - #define OQ_LL_MUL_P2_TBL_EGRESS_MIRR_LEN 1 - #define OQ_LL_MUL_P2_TBL_EGRESS_MIRR_DEFAULT 0x0 - /*[field] INGRESS_MIRR*/ - #define OQ_LL_MUL_P2_TBL_INGRESS_MIRR - #define OQ_LL_MUL_P2_TBL_INGRESS_MIRR_OFFSET 2 - #define OQ_LL_MUL_P2_TBL_INGRESS_MIRR_LEN 1 - #define OQ_LL_MUL_P2_TBL_INGRESS_MIRR_DEFAULT 0x0 - /*[field] NEXT_POINTER*/ - #define OQ_LL_MUL_P2_TBL_NEXT_POINTER - #define OQ_LL_MUL_P2_TBL_NEXT_POINTER_OFFSET 3 - #define OQ_LL_MUL_P2_TBL_NEXT_POINTER_LEN 11 - #define OQ_LL_MUL_P2_TBL_NEXT_POINTER_DEFAULT 0x0 - -struct oq_ll_mul_p2_tbl { - a_uint32_t normal_fwd:1; - a_uint32_t egress_mirr:1; - a_uint32_t ingress_mirr:1; - a_uint32_t next_pointer:11; - a_uint32_t _reserved0:18; -}; - -union oq_ll_mul_p2_tbl_u { - a_uint32_t val; - struct oq_ll_mul_p2_tbl bf; -}; - -/*[table] OQ_LL_MUL_P3_TBL*/ -#define OQ_LL_MUL_P3_TBL -#define OQ_LL_MUL_P3_TBL_ADDRESS 0x130000 -#define OQ_LL_MUL_P3_TBL_NUM 2048 -#define OQ_LL_MUL_P3_TBL_INC 0x10 -#define OQ_LL_MUL_P3_TBL_TYPE REG_TYPE_RW -#define OQ_LL_MUL_P3_TBL_DEFAULT 0x0 - /*[field] NORMAL_FWD*/ - #define OQ_LL_MUL_P3_TBL_NORMAL_FWD - #define OQ_LL_MUL_P3_TBL_NORMAL_FWD_OFFSET 0 - #define OQ_LL_MUL_P3_TBL_NORMAL_FWD_LEN 1 - #define OQ_LL_MUL_P3_TBL_NORMAL_FWD_DEFAULT 0x0 - /*[field] EGRESS_MIRR*/ - #define OQ_LL_MUL_P3_TBL_EGRESS_MIRR - #define OQ_LL_MUL_P3_TBL_EGRESS_MIRR_OFFSET 1 - #define OQ_LL_MUL_P3_TBL_EGRESS_MIRR_LEN 1 - #define OQ_LL_MUL_P3_TBL_EGRESS_MIRR_DEFAULT 0x0 - /*[field] INGRESS_MIRR*/ - #define OQ_LL_MUL_P3_TBL_INGRESS_MIRR - #define OQ_LL_MUL_P3_TBL_INGRESS_MIRR_OFFSET 2 - #define OQ_LL_MUL_P3_TBL_INGRESS_MIRR_LEN 1 - #define OQ_LL_MUL_P3_TBL_INGRESS_MIRR_DEFAULT 0x0 - /*[field] NEXT_POINTER*/ - #define OQ_LL_MUL_P3_TBL_NEXT_POINTER - #define OQ_LL_MUL_P3_TBL_NEXT_POINTER_OFFSET 3 - #define OQ_LL_MUL_P3_TBL_NEXT_POINTER_LEN 11 - #define OQ_LL_MUL_P3_TBL_NEXT_POINTER_DEFAULT 0x0 - -struct oq_ll_mul_p3_tbl { - a_uint32_t normal_fwd:1; - a_uint32_t egress_mirr:1; - a_uint32_t ingress_mirr:1; - a_uint32_t next_pointer:11; - a_uint32_t _reserved0:18; -}; - -union oq_ll_mul_p3_tbl_u { - a_uint32_t val; - struct oq_ll_mul_p3_tbl bf; -}; - -/*[table] OQ_LL_MUL_P4_TBL*/ -#define OQ_LL_MUL_P4_TBL -#define OQ_LL_MUL_P4_TBL_ADDRESS 0x150000 -#define OQ_LL_MUL_P4_TBL_NUM 2048 -#define OQ_LL_MUL_P4_TBL_INC 0x10 -#define OQ_LL_MUL_P4_TBL_TYPE REG_TYPE_RW -#define OQ_LL_MUL_P4_TBL_DEFAULT 0x0 - /*[field] NORMAL_FWD*/ - #define OQ_LL_MUL_P4_TBL_NORMAL_FWD - #define OQ_LL_MUL_P4_TBL_NORMAL_FWD_OFFSET 0 - #define OQ_LL_MUL_P4_TBL_NORMAL_FWD_LEN 1 - #define OQ_LL_MUL_P4_TBL_NORMAL_FWD_DEFAULT 0x0 - /*[field] EGRESS_MIRR*/ - #define OQ_LL_MUL_P4_TBL_EGRESS_MIRR - #define OQ_LL_MUL_P4_TBL_EGRESS_MIRR_OFFSET 1 - #define OQ_LL_MUL_P4_TBL_EGRESS_MIRR_LEN 1 - #define OQ_LL_MUL_P4_TBL_EGRESS_MIRR_DEFAULT 0x0 - /*[field] INGRESS_MIRR*/ - #define OQ_LL_MUL_P4_TBL_INGRESS_MIRR - #define OQ_LL_MUL_P4_TBL_INGRESS_MIRR_OFFSET 2 - #define OQ_LL_MUL_P4_TBL_INGRESS_MIRR_LEN 1 - #define OQ_LL_MUL_P4_TBL_INGRESS_MIRR_DEFAULT 0x0 - /*[field] NEXT_POINTER*/ - #define OQ_LL_MUL_P4_TBL_NEXT_POINTER - #define OQ_LL_MUL_P4_TBL_NEXT_POINTER_OFFSET 3 - #define OQ_LL_MUL_P4_TBL_NEXT_POINTER_LEN 11 - #define OQ_LL_MUL_P4_TBL_NEXT_POINTER_DEFAULT 0x0 - -struct oq_ll_mul_p4_tbl { - a_uint32_t normal_fwd:1; - a_uint32_t egress_mirr:1; - a_uint32_t ingress_mirr:1; - a_uint32_t next_pointer:11; - a_uint32_t _reserved0:18; -}; - -union oq_ll_mul_p4_tbl_u { - a_uint32_t val; - struct oq_ll_mul_p4_tbl bf; -}; - -/*[table] OQ_LL_MUL_P5_TBL*/ -#define OQ_LL_MUL_P5_TBL -#define OQ_LL_MUL_P5_TBL_ADDRESS 0x170000 -#define OQ_LL_MUL_P5_TBL_NUM 2048 -#define OQ_LL_MUL_P5_TBL_INC 0x10 -#define OQ_LL_MUL_P5_TBL_TYPE REG_TYPE_RW -#define OQ_LL_MUL_P5_TBL_DEFAULT 0x0 - /*[field] NORMAL_FWD*/ - #define OQ_LL_MUL_P5_TBL_NORMAL_FWD - #define OQ_LL_MUL_P5_TBL_NORMAL_FWD_OFFSET 0 - #define OQ_LL_MUL_P5_TBL_NORMAL_FWD_LEN 1 - #define OQ_LL_MUL_P5_TBL_NORMAL_FWD_DEFAULT 0x0 - /*[field] EGRESS_MIRR*/ - #define OQ_LL_MUL_P5_TBL_EGRESS_MIRR - #define OQ_LL_MUL_P5_TBL_EGRESS_MIRR_OFFSET 1 - #define OQ_LL_MUL_P5_TBL_EGRESS_MIRR_LEN 1 - #define OQ_LL_MUL_P5_TBL_EGRESS_MIRR_DEFAULT 0x0 - /*[field] INGRESS_MIRR*/ - #define OQ_LL_MUL_P5_TBL_INGRESS_MIRR - #define OQ_LL_MUL_P5_TBL_INGRESS_MIRR_OFFSET 2 - #define OQ_LL_MUL_P5_TBL_INGRESS_MIRR_LEN 1 - #define OQ_LL_MUL_P5_TBL_INGRESS_MIRR_DEFAULT 0x0 - /*[field] NEXT_POINTER*/ - #define OQ_LL_MUL_P5_TBL_NEXT_POINTER - #define OQ_LL_MUL_P5_TBL_NEXT_POINTER_OFFSET 3 - #define OQ_LL_MUL_P5_TBL_NEXT_POINTER_LEN 11 - #define OQ_LL_MUL_P5_TBL_NEXT_POINTER_DEFAULT 0x0 - -struct oq_ll_mul_p5_tbl { - a_uint32_t normal_fwd:1; - a_uint32_t egress_mirr:1; - a_uint32_t ingress_mirr:1; - a_uint32_t next_pointer:11; - a_uint32_t _reserved0:18; -}; - -union oq_ll_mul_p5_tbl_u { - a_uint32_t val; - struct oq_ll_mul_p5_tbl bf; -}; - -/*[table] OQ_LL_MUL_P6_TBL*/ -#define OQ_LL_MUL_P6_TBL -#define OQ_LL_MUL_P6_TBL_ADDRESS 0x190000 -#define OQ_LL_MUL_P6_TBL_NUM 2048 -#define OQ_LL_MUL_P6_TBL_INC 0x10 -#define OQ_LL_MUL_P6_TBL_TYPE REG_TYPE_RW -#define OQ_LL_MUL_P6_TBL_DEFAULT 0x0 - /*[field] NORMAL_FWD*/ - #define OQ_LL_MUL_P6_TBL_NORMAL_FWD - #define OQ_LL_MUL_P6_TBL_NORMAL_FWD_OFFSET 0 - #define OQ_LL_MUL_P6_TBL_NORMAL_FWD_LEN 1 - #define OQ_LL_MUL_P6_TBL_NORMAL_FWD_DEFAULT 0x0 - /*[field] EGRESS_MIRR*/ - #define OQ_LL_MUL_P6_TBL_EGRESS_MIRR - #define OQ_LL_MUL_P6_TBL_EGRESS_MIRR_OFFSET 1 - #define OQ_LL_MUL_P6_TBL_EGRESS_MIRR_LEN 1 - #define OQ_LL_MUL_P6_TBL_EGRESS_MIRR_DEFAULT 0x0 - /*[field] INGRESS_MIRR*/ - #define OQ_LL_MUL_P6_TBL_INGRESS_MIRR - #define OQ_LL_MUL_P6_TBL_INGRESS_MIRR_OFFSET 2 - #define OQ_LL_MUL_P6_TBL_INGRESS_MIRR_LEN 1 - #define OQ_LL_MUL_P6_TBL_INGRESS_MIRR_DEFAULT 0x0 - /*[field] NEXT_POINTER*/ - #define OQ_LL_MUL_P6_TBL_NEXT_POINTER - #define OQ_LL_MUL_P6_TBL_NEXT_POINTER_OFFSET 3 - #define OQ_LL_MUL_P6_TBL_NEXT_POINTER_LEN 11 - #define OQ_LL_MUL_P6_TBL_NEXT_POINTER_DEFAULT 0x0 - -struct oq_ll_mul_p6_tbl { - a_uint32_t normal_fwd:1; - a_uint32_t egress_mirr:1; - a_uint32_t ingress_mirr:1; - a_uint32_t next_pointer:11; - a_uint32_t _reserved0:18; -}; - -union oq_ll_mul_p6_tbl_u { - a_uint32_t val; - struct oq_ll_mul_p6_tbl bf; -}; - -/*[table] OQ_LL_MUL_P7_TBL*/ -#define OQ_LL_MUL_P7_TBL -#define OQ_LL_MUL_P7_TBL_ADDRESS 0x1b0000 -#define OQ_LL_MUL_P7_TBL_NUM 2048 -#define OQ_LL_MUL_P7_TBL_INC 0x10 -#define OQ_LL_MUL_P7_TBL_TYPE REG_TYPE_RW -#define OQ_LL_MUL_P7_TBL_DEFAULT 0x0 - /*[field] NORMAL_FWD*/ - #define OQ_LL_MUL_P7_TBL_NORMAL_FWD - #define OQ_LL_MUL_P7_TBL_NORMAL_FWD_OFFSET 0 - #define OQ_LL_MUL_P7_TBL_NORMAL_FWD_LEN 1 - #define OQ_LL_MUL_P7_TBL_NORMAL_FWD_DEFAULT 0x0 - /*[field] EGRESS_MIRR*/ - #define OQ_LL_MUL_P7_TBL_EGRESS_MIRR - #define OQ_LL_MUL_P7_TBL_EGRESS_MIRR_OFFSET 1 - #define OQ_LL_MUL_P7_TBL_EGRESS_MIRR_LEN 1 - #define OQ_LL_MUL_P7_TBL_EGRESS_MIRR_DEFAULT 0x0 - /*[field] INGRESS_MIRR*/ - #define OQ_LL_MUL_P7_TBL_INGRESS_MIRR - #define OQ_LL_MUL_P7_TBL_INGRESS_MIRR_OFFSET 2 - #define OQ_LL_MUL_P7_TBL_INGRESS_MIRR_LEN 1 - #define OQ_LL_MUL_P7_TBL_INGRESS_MIRR_DEFAULT 0x0 - /*[field] NEXT_POINTER*/ - #define OQ_LL_MUL_P7_TBL_NEXT_POINTER - #define OQ_LL_MUL_P7_TBL_NEXT_POINTER_OFFSET 3 - #define OQ_LL_MUL_P7_TBL_NEXT_POINTER_LEN 11 - #define OQ_LL_MUL_P7_TBL_NEXT_POINTER_DEFAULT 0x0 - -struct oq_ll_mul_p7_tbl { - a_uint32_t normal_fwd:1; - a_uint32_t egress_mirr:1; - a_uint32_t ingress_mirr:1; - a_uint32_t next_pointer:11; - a_uint32_t _reserved0:18; -}; - -union oq_ll_mul_p7_tbl_u { - a_uint32_t val; - struct oq_ll_mul_p7_tbl bf; -}; - -/*[table] PKT_DESP_TBL*/ -#define PKT_DESP_TBL -#define PKT_DESP_TBL_ADDRESS 0x1c0000 -#define PKT_DESP_TBL_NUM 2048 -#define PKT_DESP_TBL_INC 0x40 -#define PKT_DESP_TBL_TYPE REG_TYPE_RW -#define PKT_DESP_TBL_DEFAULT 0x0 - /*[field] ORG_SRC_PORT_VP*/ - #define PKT_DESP_TBL_ORG_SRC_PORT_VP - #define PKT_DESP_TBL_ORG_SRC_PORT_VP_OFFSET 0 - #define PKT_DESP_TBL_ORG_SRC_PORT_VP_LEN 12 - #define PKT_DESP_TBL_ORG_SRC_PORT_VP_DEFAULT 0x0 - /*[field] SRC_PORT_VP*/ - #define PKT_DESP_TBL_SRC_PORT_VP - #define PKT_DESP_TBL_SRC_PORT_VP_OFFSET 12 - #define PKT_DESP_TBL_SRC_PORT_VP_LEN 12 - #define PKT_DESP_TBL_SRC_PORT_VP_DEFAULT 0x0 - /*[field] PACKET_LENGTH*/ - #define PKT_DESP_TBL_PACKET_LENGTH - #define PKT_DESP_TBL_PACKET_LENGTH_OFFSET 24 - #define PKT_DESP_TBL_PACKET_LENGTH_LEN 14 - #define PKT_DESP_TBL_PACKET_LENGTH_DEFAULT 0x0 - /*[field] TS_DIR*/ - #define PKT_DESP_TBL_TS_DIR - #define PKT_DESP_TBL_TS_DIR_OFFSET 38 - #define PKT_DESP_TBL_TS_DIR_LEN 1 - #define PKT_DESP_TBL_TS_DIR_DEFAULT 0x0 - /*[field] TX_TS_EN reuse TS_DIR[0]*/ - #define PKT_DESP_TBL_TX_TS_EN - #define PKT_DESP_TBL_TX_TS_EN_OFFSET 39 - #define PKT_DESP_TBL_TX_TS_EN_LEN 1 - #define PKT_DESP_TBL_TX_TS_EN_DEFAULT 0x0 - /*[field] RX_TS_VALID reuse TS_DIR[1]*/ - #define PKT_DESP_TBL_RX_TS_VALID - #define PKT_DESP_TBL_RX_TS_VALID_OFFSET 39 - #define PKT_DESP_TBL_RX_TS_VALID_LEN 1 - #define PKT_DESP_TBL_RX_TS_VALID_DEFAULT 0x0 - /*[field] RX_TS reuse TS_DIR[1]*/ - #define PKT_DESP_TBL_RX_TS - #define PKT_DESP_TBL_RX_TS_OFFSET 40 - #define PKT_DESP_TBL_RX_TS_LEN 40 - #define PKT_DESP_TBL_RX_TS_DEFAULT 0x0 - /*[field] TX_OS_CORRECTION_EN reuse TS_DIR[0]*/ - #define PKT_DESP_TBL_TX_OS_CORRECTION_EN - #define PKT_DESP_TBL_TX_OS_CORRECTION_EN_OFFSET 40 - #define PKT_DESP_TBL_TX_OS_CORRECTION_EN_LEN 1 - #define PKT_DESP_TBL_TX_OS_CORRECTION_EN_DEFAULT 0x0 - /*[field] TX_PTP_TAG reuse TS_DIR[0]*/ - #define PKT_DESP_TBL_TX_PTP_TAG - #define PKT_DESP_TBL_TX_PTP_TAG_OFFSET 41 - #define PKT_DESP_TBL_TX_PTP_TAG_LEN 10 - #define PKT_DESP_TBL_TX_PTP_TAG_DEFAULT 0x0 - /*[field] INT_PRI*/ - #define PKT_DESP_TBL_INT_PRI - #define PKT_DESP_TBL_INT_PRI_OFFSET 80 - #define PKT_DESP_TBL_INT_PRI_LEN 4 - #define PKT_DESP_TBL_INT_PRI_DEFAULT 0x0 - /*[field] INT_DP*/ - #define PKT_DESP_TBL_INT_DP - #define PKT_DESP_TBL_INT_DP_OFFSET 84 - #define PKT_DESP_TBL_INT_DP_LEN 2 - #define PKT_DESP_TBL_INT_DP_DEFAULT 0x0 - /*[field] CPU_CODE*/ - #define PKT_DESP_TBL_CPU_CODE - #define PKT_DESP_TBL_CPU_CODE_OFFSET 86 - #define PKT_DESP_TBL_CPU_CODE_LEN 8 - #define PKT_DESP_TBL_CPU_CODE_DEFAULT 0x0 - /*[field] SERVICE_CODE*/ - #define PKT_DESP_TBL_SERVICE_CODE - #define PKT_DESP_TBL_SERVICE_CODE_OFFSET 94 - #define PKT_DESP_TBL_SERVICE_CODE_LEN 8 - #define PKT_DESP_TBL_SERVICE_CODE_DEFAULT 0x0 - /*[field] DST_L3_IF*/ - #define PKT_DESP_TBL_DST_L3_IF - #define PKT_DESP_TBL_DST_L3_IF_OFFSET 102 - #define PKT_DESP_TBL_DST_L3_IF_LEN 8 - #define PKT_DESP_TBL_DST_L3_IF_DEFAULT 0x0 - /*[field] MAC_DA*/ - #define PKT_DESP_TBL_MAC_DA - #define PKT_DESP_TBL_MAC_DA_OFFSET 110 - #define PKT_DESP_TBL_MAC_DA_LEN 48 - #define PKT_DESP_TBL_MAC_DA_DEFAULT 0x0 - /*[field] ROUTE_FLAG*/ - #define PKT_DESP_TBL_ROUTE_FLAG - #define PKT_DESP_TBL_ROUTE_FLAG_OFFSET 158 - #define PKT_DESP_TBL_ROUTE_FLAG_LEN 1 - #define PKT_DESP_TBL_ROUTE_FLAG_DEFAULT 0x0 - /*[field] PPPOE_STRIP_FLAG*/ - #define PKT_DESP_TBL_PPPOE_STRIP_FLAG - #define PKT_DESP_TBL_PPPOE_STRIP_FLAG_OFFSET 159 - #define PKT_DESP_TBL_PPPOE_STRIP_FLAG_LEN 1 - #define PKT_DESP_TBL_PPPOE_STRIP_FLAG_DEFAULT 0x0 - /*[field] NAT_ACTION*/ - #define PKT_DESP_TBL_NAT_ACTION - #define PKT_DESP_TBL_NAT_ACTION_OFFSET 160 - #define PKT_DESP_TBL_NAT_ACTION_LEN 3 - #define PKT_DESP_TBL_NAT_ACTION_DEFAULT 0x0 - /*[field] NAPT_PORT*/ - #define PKT_DESP_TBL_NAPT_PORT - #define PKT_DESP_TBL_NAPT_PORT_OFFSET 163 - #define PKT_DESP_TBL_NAPT_PORT_LEN 16 - #define PKT_DESP_TBL_NAPT_PORT_DEFAULT 0x0 - /*[field] NAPT_ADDR*/ - #define PKT_DESP_TBL_NAPT_ADDR - #define PKT_DESP_TBL_NAPT_ADDR_OFFSET 179 - #define PKT_DESP_TBL_NAPT_ADDR_LEN 32 - #define PKT_DESP_TBL_NAPT_ADDR_DEFAULT 0x0 - /*[field] DSCP_UPDATE*/ - #define PKT_DESP_TBL_DSCP_UPDATE - #define PKT_DESP_TBL_DSCP_UPDATE_OFFSET 211 - #define PKT_DESP_TBL_DSCP_UPDATE_LEN 1 - #define PKT_DESP_TBL_DSCP_UPDATE_DEFAULT 0x0 - /*[field] DSCP*/ - #define PKT_DESP_TBL_DSCP - #define PKT_DESP_TBL_DSCP_OFFSET 212 - #define PKT_DESP_TBL_DSCP_LEN 8 - #define PKT_DESP_TBL_DSCP_DEFAULT 0x0 - /*[field] TTL_UPDATE*/ - #define PKT_DESP_TBL_TTL_UPDATE - #define PKT_DESP_TBL_TTL_UPDATE_OFFSET 220 - #define PKT_DESP_TBL_TTL_UPDATE_LEN 1 - #define PKT_DESP_TBL_TTL_UPDATE_DEFAULT 0x0 - /*[field] TTL*/ - #define PKT_DESP_TBL_TTL - #define PKT_DESP_TBL_TTL_OFFSET 221 - #define PKT_DESP_TBL_TTL_LEN 8 - #define PKT_DESP_TBL_TTL_DEFAULT 0x0 - /*[field] STAG_FLAG*/ - #define PKT_DESP_TBL_STAG_FLAG - #define PKT_DESP_TBL_STAG_FLAG_OFFSET 229 - #define PKT_DESP_TBL_STAG_FLAG_LEN 1 - #define PKT_DESP_TBL_STAG_FLAG_DEFAULT 0x0 - /*[field] CTAG_FLAG*/ - #define PKT_DESP_TBL_CTAG_FLAG - #define PKT_DESP_TBL_CTAG_FLAG_OFFSET 230 - #define PKT_DESP_TBL_CTAG_FLAG_LEN 1 - #define PKT_DESP_TBL_CTAG_FLAG_DEFAULT 0x0 - /*[field] SNAP_FLAG*/ - #define PKT_DESP_TBL_SNAP_FLAG - #define PKT_DESP_TBL_SNAP_FLAG_OFFSET 231 - #define PKT_DESP_TBL_SNAP_FLAG_LEN 1 - #define PKT_DESP_TBL_SNAP_FLAG_DEFAULT 0x0 - /*[field] PPPOE_FLAG*/ - #define PKT_DESP_TBL_PPPOE_FLAG - #define PKT_DESP_TBL_PPPOE_FLAG_OFFSET 232 - #define PKT_DESP_TBL_PPPOE_FLAG_LEN 1 - #define PKT_DESP_TBL_PPPOE_FLAG_DEFAULT 0x0 - /*[field] INT_STAG_FMT*/ - #define PKT_DESP_TBL_INT_STAG_FMT - #define PKT_DESP_TBL_INT_STAG_FMT_OFFSET 233 - #define PKT_DESP_TBL_INT_STAG_FMT_LEN 1 - #define PKT_DESP_TBL_INT_STAG_FMT_DEFAULT 0x0 - /*[field] INT_CTAG_FMT*/ - #define PKT_DESP_TBL_INT_CTAG_FMT - #define PKT_DESP_TBL_INT_CTAG_FMT_OFFSET 234 - #define PKT_DESP_TBL_INT_CTAG_FMT_LEN 1 - #define PKT_DESP_TBL_INT_CTAG_FMT_DEFAULT 0x0 - /*[field] INT_SVID*/ - #define PKT_DESP_TBL_INT_SVID - #define PKT_DESP_TBL_INT_SVID_OFFSET 235 - #define PKT_DESP_TBL_INT_SVID_LEN 12 - #define PKT_DESP_TBL_INT_SVID_DEFAULT 0x0 - /*[field] INT_CVID*/ - #define PKT_DESP_TBL_INT_CVID - #define PKT_DESP_TBL_INT_CVID_OFFSET 247 - #define PKT_DESP_TBL_INT_CVID_LEN 12 - #define PKT_DESP_TBL_INT_CVID_DEFAULT 0x0 - /*[field] INT_SPCP*/ - #define PKT_DESP_TBL_INT_SPCP - #define PKT_DESP_TBL_INT_SPCP_OFFSET 259 - #define PKT_DESP_TBL_INT_SPCP_LEN 3 - #define PKT_DESP_TBL_INT_SPCP_DEFAULT 0x0 - /*[field] INT_CPCP*/ - #define PKT_DESP_TBL_INT_CPCP - #define PKT_DESP_TBL_INT_CPCP_OFFSET 262 - #define PKT_DESP_TBL_INT_CPCP_LEN 3 - #define PKT_DESP_TBL_INT_CPCP_DEFAULT 0x0 - /*[field] INT_SDEI*/ - #define PKT_DESP_TBL_INT_SDEI - #define PKT_DESP_TBL_INT_SDEI_OFFSET 265 - #define PKT_DESP_TBL_INT_SDEI_LEN 1 - #define PKT_DESP_TBL_INT_SDEI_DEFAULT 0x0 - /*[field] INT_CDEI*/ - #define PKT_DESP_TBL_INT_CDEI - #define PKT_DESP_TBL_INT_CDEI_OFFSET 266 - #define PKT_DESP_TBL_INT_CDEI_LEN 1 - #define PKT_DESP_TBL_INT_CDEI_DEFAULT 0x0 - /*[field] VSI*/ - #define PKT_DESP_TBL_VSI - #define PKT_DESP_TBL_VSI_OFFSET 267 - #define PKT_DESP_TBL_VSI_LEN 5 - #define PKT_DESP_TBL_VSI_DEFAULT 0x0 - /*[field] L3_OFFSET*/ - #define PKT_DESP_TBL_L3_OFFSET - #define PKT_DESP_TBL_L3_OFFSET_OFFSET 272 - #define PKT_DESP_TBL_L3_OFFSET_LEN 8 - #define PKT_DESP_TBL_L3_OFFSET_DEFAULT 0x0 - /*[field] L3_TYPE*/ - #define PKT_DESP_TBL_L3_TYPE - #define PKT_DESP_TBL_L3_TYPE_OFFSET 280 - #define PKT_DESP_TBL_L3_TYPE_LEN 2 - #define PKT_DESP_TBL_L3_TYPE_DEFAULT 0x0 - /*[field] L4_OFFSET*/ - #define PKT_DESP_TBL_L4_OFFSET - #define PKT_DESP_TBL_L4_OFFSET_OFFSET 282 - #define PKT_DESP_TBL_L4_OFFSET_LEN 8 - #define PKT_DESP_TBL_L4_OFFSET_DEFAULT 0x0 - /*[field] L4_TYPE*/ - #define PKT_DESP_TBL_L4_TYPE - #define PKT_DESP_TBL_L4_TYPE_OFFSET 290 - #define PKT_DESP_TBL_L4_TYPE_LEN 3 - #define PKT_DESP_TBL_L4_TYPE_DEFAULT 0x0 - /*[field] NEXT_HEADER*/ - #define PKT_DESP_TBL_NEXT_HEADER - #define PKT_DESP_TBL_NEXT_HEADER_OFFSET 293 - #define PKT_DESP_TBL_NEXT_HEADER_LEN 8 - #define PKT_DESP_TBL_NEXT_HEADER_DEFAULT 0x0 - /*[field] EG_VLAN_TAG_FMT_BYPASS_EN*/ - #define PKT_DESP_TBL_EG_VLAN_TAG_FMT_BYPASS_EN - #define PKT_DESP_TBL_EG_VLAN_TAG_FMT_BYPASS_EN_OFFSET 301 - #define PKT_DESP_TBL_EG_VLAN_TAG_FMT_BYPASS_EN_LEN 1 - #define PKT_DESP_TBL_EG_VLAN_TAG_FMT_BYPASS_EN_DEFAULT 0x0 - /*[field] EG_VLAN_XLT_BYPASS_EN*/ - #define PKT_DESP_TBL_EG_VLAN_XLT_BYPASS_EN - #define PKT_DESP_TBL_EG_VLAN_XLT_BYPASS_EN_OFFSET 302 - #define PKT_DESP_TBL_EG_VLAN_XLT_BYPASS_EN_LEN 1 - #define PKT_DESP_TBL_EG_VLAN_XLT_BYPASS_EN_DEFAULT 0x0 - /*[field] PKT_L2_EDIT_BYPASS*/ - #define PKT_DESP_TBL_PKT_L2_EDIT_BYPASS - #define PKT_DESP_TBL_PKT_L2_EDIT_BYPASS_OFFSET 303 - #define PKT_DESP_TBL_PKT_L2_EDIT_BYPASS_LEN 1 - #define PKT_DESP_TBL_PKT_L2_EDIT_BYPASS_DEFAULT 0x0 - /*[field] PKT_L3_EDIT_BYPASS*/ - #define PKT_DESP_TBL_PKT_L3_EDIT_BYPASS - #define PKT_DESP_TBL_PKT_L3_EDIT_BYPASS_OFFSET 304 - #define PKT_DESP_TBL_PKT_L3_EDIT_BYPASS_LEN 1 - #define PKT_DESP_TBL_PKT_L3_EDIT_BYPASS_DEFAULT 0x0 - /*[field] ACL_INDEX_TOGGLE*/ - #define PKT_DESP_TBL_ACL_INDEX_TOGGLE - #define PKT_DESP_TBL_ACL_INDEX_TOGGLE_OFFSET 305 - #define PKT_DESP_TBL_ACL_INDEX_TOGGLE_LEN 1 - #define PKT_DESP_TBL_ACL_INDEX_TOGGLE_DEFAULT 0x0 - /*[field] ACL_INDEX_VALID*/ - #define PKT_DESP_TBL_ACL_INDEX_VALID - #define PKT_DESP_TBL_ACL_INDEX_VALID_OFFSET 306 - #define PKT_DESP_TBL_ACL_INDEX_VALID_LEN 1 - #define PKT_DESP_TBL_ACL_INDEX_VALID_DEFAULT 0x0 - /*[field] ACL_INDEX*/ - #define PKT_DESP_TBL_ACL_INDEX - #define PKT_DESP_TBL_ACL_INDEX_OFFSET 307 - #define PKT_DESP_TBL_ACL_INDEX_LEN 9 - #define PKT_DESP_TBL_ACL_INDEX_DEFAULT 0x0 - /*[field] IP_ADDR_INDEX_TYPE*/ - #define PKT_DESP_TBL_IP_ADDR_INDEX_TYPE - #define PKT_DESP_TBL_IP_ADDR_INDEX_TYPE_OFFSET 316 - #define PKT_DESP_TBL_IP_ADDR_INDEX_TYPE_LEN 1 - #define PKT_DESP_TBL_IP_ADDR_INDEX_TYPE_DEFAULT 0x0 - /*[field] IP_ADDR_INDEX_TOGGLE*/ - #define PKT_DESP_TBL_IP_ADDR_INDEX_TOGGLE - #define PKT_DESP_TBL_IP_ADDR_INDEX_TOGGLE_OFFSET 317 - #define PKT_DESP_TBL_IP_ADDR_INDEX_TOGGLE_LEN 1 - #define PKT_DESP_TBL_IP_ADDR_INDEX_TOGGLE_DEFAULT 0x0 - /*[field] IP_ADDR_INDEX_VALID*/ - #define PKT_DESP_TBL_IP_ADDR_INDEX_VALID - #define PKT_DESP_TBL_IP_ADDR_INDEX_VALID_OFFSET 318 - #define PKT_DESP_TBL_IP_ADDR_INDEX_VALID_LEN 1 - #define PKT_DESP_TBL_IP_ADDR_INDEX_VALID_DEFAULT 0x0 - /*[field] IP_ADDR_INDEX*/ - #define PKT_DESP_TBL_IP_ADDR_INDEX - #define PKT_DESP_TBL_IP_ADDR_INDEX_OFFSET 319 - #define PKT_DESP_TBL_IP_ADDR_INDEX_LEN 13 - #define PKT_DESP_TBL_IP_ADDR_INDEX_DEFAULT 0x0 - /*[field] CHG_PORT_VP*/ - #define PKT_DESP_TBL_CHG_PORT_VP - #define PKT_DESP_TBL_CHG_PORT_VP_OFFSET 332 - #define PKT_DESP_TBL_CHG_PORT_VP_LEN 12 - #define PKT_DESP_TBL_CHG_PORT_VP_DEFAULT 0x0 - /*[field] HASH_FLAG*/ - #define PKT_DESP_TBL_HASH_FLAG - #define PKT_DESP_TBL_HASH_FLAG_OFFSET 344 - #define PKT_DESP_TBL_HASH_FLAG_LEN 3 - #define PKT_DESP_TBL_HASH_FLAG_DEFAULT 0x0 - /*[field] HASH_VALUE*/ - #define PKT_DESP_TBL_HASH_VALUE - #define PKT_DESP_TBL_HASH_VALUE_OFFSET 347 - #define PKT_DESP_TBL_HASH_VALUE_LEN 21 - #define PKT_DESP_TBL_HASH_VALUE_DEFAULT 0x0 - /*[field] COPY_CPU_FLAG*/ - #define PKT_DESP_TBL_COPY_CPU_FLAG - #define PKT_DESP_TBL_COPY_CPU_FLAG_OFFSET 368 - #define PKT_DESP_TBL_COPY_CPU_FLAG_LEN 1 - #define PKT_DESP_TBL_COPY_CPU_FLAG_DEFAULT 0x0 - /*[field] SRC_PN*/ - #define PKT_DESP_TBL_SRC_PN - #define PKT_DESP_TBL_SRC_PN_OFFSET 369 - #define PKT_DESP_TBL_SRC_PN_LEN 4 - #define PKT_DESP_TBL_SRC_PN_DEFAULT 0x0 - /*[field] RX_PTP_TYPE*/ - #define PKT_DESP_TBL_RX_PTP_TYPE - #define PKT_DESP_TBL_RX_PTP_TYPE_OFFSET 373 - #define PKT_DESP_TBL_RX_PTP_TYPE_LEN 4 - #define PKT_DESP_TBL_RX_PTP_TYPE_DEFAULT 0x0 - /*[field] FAKE_L2_PROT*/ - #define PKT_DESP_TBL_FAKE_L2_PROT - #define PKT_DESP_TBL_FAKE_L2_PROT_OFFSET 377 - #define PKT_DESP_TBL_FAKE_L2_PROT_LEN 1 - #define PKT_DESP_TBL_FAKE_L2_PROT_DEFAULT 0x0 - /*[field] FAKE_MAC_HEADER*/ - #define PKT_DESP_TBL_FAKE_MAC_HEADER - #define PKT_DESP_TBL_FAKE_MAC_HEADER_OFFSET 378 - #define PKT_DESP_TBL_FAKE_MAC_HEADER_LEN 1 - #define PKT_DESP_TBL_FAKE_MAC_HEADER_DEFAULT 0x0 - /*[field] VSI_VALID*/ - #define PKT_DESP_TBL_VSI_VALID - #define PKT_DESP_TBL_VSI_VALID_OFFSET 379 - #define PKT_DESP_TBL_VSI_VALID_LEN 1 - #define PKT_DESP_TBL_VSI_VALID_DEFAULT 0x0 - /*[field] VP_TX_CNT_EN*/ - #define PKT_DESP_TBL_VP_TX_CNT_EN - #define PKT_DESP_TBL_VP_TX_CNT_EN_OFFSET 380 - #define PKT_DESP_TBL_VP_TX_CNT_EN_LEN 1 - #define PKT_DESP_TBL_VP_TX_CNT_EN_DEFAULT 0x0 - /*[field] RSV0*/ - #define PKT_DESP_TBL_RSV0 - #define PKT_DESP_TBL_RSV0_OFFSET 381 - #define PKT_DESP_TBL_RSV0_LEN 7 - #define PKT_DESP_TBL_RSV0_DEFAULT 0x0 - /*[field] AC_GROUP_BITMAP*/ - #define PKT_DESP_TBL_AC_GROUP_BITMAP - #define PKT_DESP_TBL_AC_GROUP_BITMAP_OFFSET 388 - #define PKT_DESP_TBL_AC_GROUP_BITMAP_LEN 4 - #define PKT_DESP_TBL_AC_GROUP_BITMAP_DEFAULT 0x0 - /*[field] ONE_ENQ_FLAG*/ - #define PKT_DESP_TBL_ONE_ENQ_FLAG - #define PKT_DESP_TBL_ONE_ENQ_FLAG_OFFSET 392 - #define PKT_DESP_TBL_ONE_ENQ_FLAG_LEN 1 - #define PKT_DESP_TBL_ONE_ENQ_FLAG_DEFAULT 0x0 - /*[field] EDMA_VP*/ - #define PKT_DESP_TBL_EDMA_VP - #define PKT_DESP_TBL_EDMA_VP_OFFSET 393 - #define PKT_DESP_TBL_EDMA_VP_LEN 3 - #define PKT_DESP_TBL_EDMA_VP_DEFAULT 0x0 - /*[field] FC_GRP_ID*/ - #define PKT_DESP_TBL_FC_GRP_ID - #define PKT_DESP_TBL_FC_GRP_ID_OFFSET 396 - #define PKT_DESP_TBL_FC_GRP_ID_LEN 3 - #define PKT_DESP_TBL_FC_GRP_ID_DEFAULT 0x0 - /*[field] FC_EN*/ - #define PKT_DESP_TBL_FC_EN - #define PKT_DESP_TBL_FC_EN_OFFSET 399 - #define PKT_DESP_TBL_FC_EN_LEN 1 - #define PKT_DESP_TBL_FC_EN_DEFAULT 0x0 - -struct pkt_desp_tbl_0 { - a_uint32_t org_src_port_vp:12; - a_uint32_t src_port_vp:12; - a_uint32_t packet_length_0:8; - a_uint32_t packet_length_1:6; - a_uint32_t ts_dir:1; - a_uint32_t tx_ts_en:1; - a_uint32_t tx_os_correction_en:1; - a_uint32_t tx_ptp_tag:10; - a_uint32_t _reserved0_0:13; - a_uint32_t _reserved0_1:16; - a_uint32_t int_pri:4; - a_uint32_t int_dp:2; - a_uint32_t cpu_code:8; - a_uint32_t service_code_0:2; - a_uint32_t service_code_1:6; - a_uint32_t dst_l3_if:8; - a_uint32_t mac_da_0:18; - a_uint32_t mac_da_1:30; - a_uint32_t route_flag:1; - a_uint32_t pppoe_strip_flag:1; - a_uint32_t nat_action:3; - a_uint32_t napt_port:16; - a_uint32_t napt_addr_0:13; - a_uint32_t napt_addr_1:19; - a_uint32_t dscp_update:1; - a_uint32_t dscp:8; - a_uint32_t ttl_update:1; - a_uint32_t ttl_0:3; - a_uint32_t ttl_1:5; - a_uint32_t stag_flag:1; - a_uint32_t ctag_flag:1; - a_uint32_t snap_flag:1; - a_uint32_t pppoe_flag:1; - a_uint32_t int_stag_fmt:1; - a_uint32_t int_ctag_fmt:1; - a_uint32_t int_svid:12; - a_uint32_t int_cvid_0:9; - a_uint32_t int_cvid_1:3; - a_uint32_t int_spcp:3; - a_uint32_t int_cpcp:3; - a_uint32_t int_sdei:1; - a_uint32_t int_cdei:1; - a_uint32_t vsi:5; - a_uint32_t l3_offset:8; - a_uint32_t l3_type:2; - a_uint32_t l4_offset_0:6; - a_uint32_t l4_offset_1:2; - a_uint32_t l4_type:3; - a_uint32_t next_header:8; - a_uint32_t eg_vlan_tag_fmt_bypass_en:1; - a_uint32_t eg_vlan_xlt_bypass_en:1; - a_uint32_t pkt_l2_edit_bypass:1; - a_uint32_t pkt_l3_edit_bypass:1; - a_uint32_t acl_index_toggle:1; - a_uint32_t acl_index_valid:1; - a_uint32_t acl_index:9; - a_uint32_t ip_addr_index_type:1; - a_uint32_t ip_addr_index_toggle:1; - a_uint32_t ip_addr_index_valid:1; - a_uint32_t ip_addr_index_0:1; - a_uint32_t ip_addr_index_1:12; - a_uint32_t chg_port_vp:12; - a_uint32_t hash_flag:3; - a_uint32_t hash_value_0:5; - a_uint32_t hash_value_1:16; - a_uint32_t copy_cpu_flag:1; - a_uint32_t src_pn:4; - a_uint32_t rx_ptp_type:4; - a_uint32_t fake_l2_prot:1; - a_uint32_t fake_mac_header:1; - a_uint32_t vsi_valid:1; - a_uint32_t vp_tx_cnt_en:1; - a_uint32_t rsv0_0:3; - a_uint32_t rsv0_1:4; - a_uint32_t ac_group_bitmap:4; - a_uint32_t one_enq_flag:1; - a_uint32_t edma_vp:3; - a_uint32_t fc_grp_id:3; - a_uint32_t fc_en:1; - a_uint32_t _reserved1:16; -}; - -struct pkt_desp_tbl_1 { - a_uint32_t org_src_port_vp:12; - a_uint32_t src_port_vp:12; - a_uint32_t packet_length_0:8; - a_uint32_t packet_length_1:6; - a_uint32_t ts_dir:1; - a_uint32_t rx_ts_valid:1; - a_uint32_t rx_ts_0:24; - a_uint32_t rx_ts_1:16; - a_uint32_t int_pri:4; - a_uint32_t int_dp:2; - a_uint32_t cpu_code:8; - a_uint32_t service_code_0:2; - a_uint32_t service_code_1:6; - a_uint32_t dst_l3_if:8; - a_uint32_t mac_da_0:18; - a_uint32_t mac_da_1:30; - a_uint32_t route_flag:1; - a_uint32_t pppoe_strip_flag:1; - a_uint32_t nat_action:3; - a_uint32_t napt_port:16; - a_uint32_t napt_addr_0:13; - a_uint32_t napt_addr_1:19; - a_uint32_t dscp_update:1; - a_uint32_t dscp:8; - a_uint32_t ttl_update:1; - a_uint32_t ttl_0:3; - a_uint32_t ttl_1:5; - a_uint32_t stag_flag:1; - a_uint32_t ctag_flag:1; - a_uint32_t snap_flag:1; - a_uint32_t pppoe_flag:1; - a_uint32_t int_stag_fmt:1; - a_uint32_t int_ctag_fmt:1; - a_uint32_t int_svid:12; - a_uint32_t int_cvid_0:9; - a_uint32_t int_cvid_1:3; - a_uint32_t int_spcp:3; - a_uint32_t int_cpcp:3; - a_uint32_t int_sdei:1; - a_uint32_t int_cdei:1; - a_uint32_t vsi:5; - a_uint32_t l3_offset:8; - a_uint32_t l3_type:2; - a_uint32_t l4_offset_0:6; - a_uint32_t l4_offset_1:2; - a_uint32_t l4_type:3; - a_uint32_t next_header:8; - a_uint32_t eg_vlan_tag_fmt_bypass_en:1; - a_uint32_t eg_vlan_xlt_bypass_en:1; - a_uint32_t pkt_l2_edit_bypass:1; - a_uint32_t pkt_l3_edit_bypass:1; - a_uint32_t acl_index_toggle:1; - a_uint32_t acl_index_valid:1; - a_uint32_t acl_index:9; - a_uint32_t ip_addr_index_type:1; - a_uint32_t ip_addr_index_toggle:1; - a_uint32_t ip_addr_index_valid:1; - a_uint32_t ip_addr_index_0:1; - a_uint32_t ip_addr_index_1:12; - a_uint32_t chg_port_vp:12; - a_uint32_t hash_flag:3; - a_uint32_t hash_value_0:5; - a_uint32_t hash_value_1:16; - a_uint32_t copy_cpu_flag:1; - a_uint32_t src_pn:4; - a_uint32_t rx_ptp_type:4; - a_uint32_t fake_l2_prot:1; - a_uint32_t fake_mac_header:1; - a_uint32_t vsi_valid:1; - a_uint32_t vp_tx_cnt_en:1; - a_uint32_t rsv0_0:3; - a_uint32_t rsv0_1:4; - a_uint32_t ac_group_bitmap:4; - a_uint32_t one_enq_flag:1; - a_uint32_t edma_vp:3; - a_uint32_t fc_grp_id:3; - a_uint32_t fc_en:1; - a_uint32_t _reserved0:16; -}; - -union pkt_desp_tbl_u { - a_uint32_t val[13]; - struct pkt_desp_tbl_0 bf0; - struct pkt_desp_tbl_1 bf1; -}; - -/*[table] UNI_DROP_CNT_TBL*/ -#define UNI_DROP_CNT_TBL -#define UNI_DROP_CNT_TBL_ADDRESS 0x1e0000 -#define UNI_DROP_CNT_TBL_NUM 1536 -#define UNI_DROP_CNT_TBL_INC 0x10 -#define UNI_DROP_CNT_TBL_TYPE REG_TYPE_RW -#define UNI_DROP_CNT_TBL_DEFAULT 0x0 - /*[field] UNI_DROP_PKT*/ - #define UNI_DROP_CNT_TBL_UNI_DROP_PKT - #define UNI_DROP_CNT_TBL_UNI_DROP_PKT_OFFSET 0 - #define UNI_DROP_CNT_TBL_UNI_DROP_PKT_LEN 32 - #define UNI_DROP_CNT_TBL_UNI_DROP_PKT_DEFAULT 0x0 - /*[field] UNI_DROP_BYTE*/ - #define UNI_DROP_CNT_TBL_UNI_DROP_BYTE - #define UNI_DROP_CNT_TBL_UNI_DROP_BYTE_OFFSET 32 - #define UNI_DROP_CNT_TBL_UNI_DROP_BYTE_LEN 40 - #define UNI_DROP_CNT_TBL_UNI_DROP_BYTE_DEFAULT 0x0 - -struct uni_drop_cnt_tbl { - a_uint32_t uni_drop_pkt:32; - a_uint32_t uni_drop_byte_0:32; - a_uint32_t uni_drop_byte_1:8; - a_uint32_t _reserved0:24; -}; - -union uni_drop_cnt_tbl_u { - a_uint32_t val[3]; - struct uni_drop_cnt_tbl bf; -}; - -/*[table] MUL_P0_DROP_CNT_TBL*/ -#define MUL_P0_DROP_CNT_TBL -#define MUL_P0_DROP_CNT_TBL_ADDRESS 0x1f0000 -#define MUL_P0_DROP_CNT_TBL_NUM 48 -#define MUL_P0_DROP_CNT_TBL_INC 0x10 -#define MUL_P0_DROP_CNT_TBL_TYPE REG_TYPE_RW -#define MUL_P0_DROP_CNT_TBL_DEFAULT 0x0 - /*[field] MUL_P0_DROP_PKT*/ - #define MUL_P0_DROP_CNT_TBL_MUL_P0_DROP_PKT - #define MUL_P0_DROP_CNT_TBL_MUL_P0_DROP_PKT_OFFSET 0 - #define MUL_P0_DROP_CNT_TBL_MUL_P0_DROP_PKT_LEN 32 - #define MUL_P0_DROP_CNT_TBL_MUL_P0_DROP_PKT_DEFAULT 0x0 - /*[field] MUL_P0_DROP_BYTE*/ - #define MUL_P0_DROP_CNT_TBL_MUL_P0_DROP_BYTE - #define MUL_P0_DROP_CNT_TBL_MUL_P0_DROP_BYTE_OFFSET 32 - #define MUL_P0_DROP_CNT_TBL_MUL_P0_DROP_BYTE_LEN 40 - #define MUL_P0_DROP_CNT_TBL_MUL_P0_DROP_BYTE_DEFAULT 0x0 - -struct mul_p0_drop_cnt_tbl { - a_uint32_t mul_p0_drop_pkt:32; - a_uint32_t mul_p0_drop_byte_0:32; - a_uint32_t mul_p0_drop_byte_1:8; - a_uint32_t _reserved0:24; -}; - -union mul_p0_drop_cnt_tbl_u { - a_uint32_t val[3]; - struct mul_p0_drop_cnt_tbl bf; -}; - -/*[table] MUL_P1_DROP_CNT_TBL*/ -#define MUL_P1_DROP_CNT_TBL -#define MUL_P1_DROP_CNT_TBL_ADDRESS 0x1f1000 -#define MUL_P1_DROP_CNT_TBL_NUM 12 -#define MUL_P1_DROP_CNT_TBL_INC 0x10 -#define MUL_P1_DROP_CNT_TBL_TYPE REG_TYPE_RW -#define MUL_P1_DROP_CNT_TBL_DEFAULT 0x0 - /*[field] MUL_P1_DROP_PKT*/ - #define MUL_P1_DROP_CNT_TBL_MUL_P1_DROP_PKT - #define MUL_P1_DROP_CNT_TBL_MUL_P1_DROP_PKT_OFFSET 0 - #define MUL_P1_DROP_CNT_TBL_MUL_P1_DROP_PKT_LEN 32 - #define MUL_P1_DROP_CNT_TBL_MUL_P1_DROP_PKT_DEFAULT 0x0 - /*[field] MUL_P1_DROP_BYTE*/ - #define MUL_P1_DROP_CNT_TBL_MUL_P1_DROP_BYTE - #define MUL_P1_DROP_CNT_TBL_MUL_P1_DROP_BYTE_OFFSET 32 - #define MUL_P1_DROP_CNT_TBL_MUL_P1_DROP_BYTE_LEN 40 - #define MUL_P1_DROP_CNT_TBL_MUL_P1_DROP_BYTE_DEFAULT 0x0 - -struct mul_p1_drop_cnt_tbl { - a_uint32_t mul_p1_drop_pkt:32; - a_uint32_t mul_p1_drop_byte_0:32; - a_uint32_t mul_p1_drop_byte_1:8; - a_uint32_t _reserved0:24; -}; - -union mul_p1_drop_cnt_tbl_u { - a_uint32_t val[3]; - struct mul_p1_drop_cnt_tbl bf; -}; - -/*[table] MUL_P2_DROP_CNT_TBL*/ -#define MUL_P2_DROP_CNT_TBL -#define MUL_P2_DROP_CNT_TBL_ADDRESS 0x1f2000 -#define MUL_P2_DROP_CNT_TBL_NUM 12 -#define MUL_P2_DROP_CNT_TBL_INC 0x10 -#define MUL_P2_DROP_CNT_TBL_TYPE REG_TYPE_RW -#define MUL_P2_DROP_CNT_TBL_DEFAULT 0x0 - /*[field] MUL_P2_DROP_PKT*/ - #define MUL_P2_DROP_CNT_TBL_MUL_P2_DROP_PKT - #define MUL_P2_DROP_CNT_TBL_MUL_P2_DROP_PKT_OFFSET 0 - #define MUL_P2_DROP_CNT_TBL_MUL_P2_DROP_PKT_LEN 32 - #define MUL_P2_DROP_CNT_TBL_MUL_P2_DROP_PKT_DEFAULT 0x0 - /*[field] MUL_P2_DROP_BYTE*/ - #define MUL_P2_DROP_CNT_TBL_MUL_P2_DROP_BYTE - #define MUL_P2_DROP_CNT_TBL_MUL_P2_DROP_BYTE_OFFSET 32 - #define MUL_P2_DROP_CNT_TBL_MUL_P2_DROP_BYTE_LEN 40 - #define MUL_P2_DROP_CNT_TBL_MUL_P2_DROP_BYTE_DEFAULT 0x0 - -struct mul_p2_drop_cnt_tbl { - a_uint32_t mul_p2_drop_pkt:32; - a_uint32_t mul_p2_drop_byte_0:32; - a_uint32_t mul_p2_drop_byte_1:8; - a_uint32_t _reserved0:24; -}; - -union mul_p2_drop_cnt_tbl_u { - a_uint32_t val[3]; - struct mul_p2_drop_cnt_tbl bf; -}; - -/*[table] MUL_P3_DROP_CNT_TBL*/ -#define MUL_P3_DROP_CNT_TBL -#define MUL_P3_DROP_CNT_TBL_ADDRESS 0x1f3000 -#define MUL_P3_DROP_CNT_TBL_NUM 12 -#define MUL_P3_DROP_CNT_TBL_INC 0x10 -#define MUL_P3_DROP_CNT_TBL_TYPE REG_TYPE_RW -#define MUL_P3_DROP_CNT_TBL_DEFAULT 0x0 - /*[field] MUL_P3_DROP_PKT*/ - #define MUL_P3_DROP_CNT_TBL_MUL_P3_DROP_PKT - #define MUL_P3_DROP_CNT_TBL_MUL_P3_DROP_PKT_OFFSET 0 - #define MUL_P3_DROP_CNT_TBL_MUL_P3_DROP_PKT_LEN 32 - #define MUL_P3_DROP_CNT_TBL_MUL_P3_DROP_PKT_DEFAULT 0x0 - /*[field] MUL_P3_DROP_BYTE*/ - #define MUL_P3_DROP_CNT_TBL_MUL_P3_DROP_BYTE - #define MUL_P3_DROP_CNT_TBL_MUL_P3_DROP_BYTE_OFFSET 32 - #define MUL_P3_DROP_CNT_TBL_MUL_P3_DROP_BYTE_LEN 40 - #define MUL_P3_DROP_CNT_TBL_MUL_P3_DROP_BYTE_DEFAULT 0x0 - -struct mul_p3_drop_cnt_tbl { - a_uint32_t mul_p3_drop_pkt:32; - a_uint32_t mul_p3_drop_byte_0:32; - a_uint32_t mul_p3_drop_byte_1:8; - a_uint32_t _reserved0:24; -}; - -union mul_p3_drop_cnt_tbl_u { - a_uint32_t val[3]; - struct mul_p3_drop_cnt_tbl bf; -}; - -/*[table] MUL_P4_DROP_CNT_TBL*/ -#define MUL_P4_DROP_CNT_TBL -#define MUL_P4_DROP_CNT_TBL_ADDRESS 0x1f4000 -#define MUL_P4_DROP_CNT_TBL_NUM 12 -#define MUL_P4_DROP_CNT_TBL_INC 0x10 -#define MUL_P4_DROP_CNT_TBL_TYPE REG_TYPE_RW -#define MUL_P4_DROP_CNT_TBL_DEFAULT 0x0 - /*[field] MUL_P4_DROP_PKT*/ - #define MUL_P4_DROP_CNT_TBL_MUL_P4_DROP_PKT - #define MUL_P4_DROP_CNT_TBL_MUL_P4_DROP_PKT_OFFSET 0 - #define MUL_P4_DROP_CNT_TBL_MUL_P4_DROP_PKT_LEN 32 - #define MUL_P4_DROP_CNT_TBL_MUL_P4_DROP_PKT_DEFAULT 0x0 - /*[field] MUL_P4_DROP_BYTE*/ - #define MUL_P4_DROP_CNT_TBL_MUL_P4_DROP_BYTE - #define MUL_P4_DROP_CNT_TBL_MUL_P4_DROP_BYTE_OFFSET 32 - #define MUL_P4_DROP_CNT_TBL_MUL_P4_DROP_BYTE_LEN 40 - #define MUL_P4_DROP_CNT_TBL_MUL_P4_DROP_BYTE_DEFAULT 0x0 - -struct mul_p4_drop_cnt_tbl { - a_uint32_t mul_p4_drop_pkt:32; - a_uint32_t mul_p4_drop_byte_0:32; - a_uint32_t mul_p4_drop_byte_1:8; - a_uint32_t _reserved0:24; -}; - -union mul_p4_drop_cnt_tbl_u { - a_uint32_t val[3]; - struct mul_p4_drop_cnt_tbl bf; -}; - -/*[table] MUL_P5_DROP_CNT_TBL*/ -#define MUL_P5_DROP_CNT_TBL -#define MUL_P5_DROP_CNT_TBL_ADDRESS 0x1f5000 -#define MUL_P5_DROP_CNT_TBL_NUM 12 -#define MUL_P5_DROP_CNT_TBL_INC 0x10 -#define MUL_P5_DROP_CNT_TBL_TYPE REG_TYPE_RW -#define MUL_P5_DROP_CNT_TBL_DEFAULT 0x0 - /*[field] MUL_P5_DROP_PKT*/ - #define MUL_P5_DROP_CNT_TBL_MUL_P5_DROP_PKT - #define MUL_P5_DROP_CNT_TBL_MUL_P5_DROP_PKT_OFFSET 0 - #define MUL_P5_DROP_CNT_TBL_MUL_P5_DROP_PKT_LEN 32 - #define MUL_P5_DROP_CNT_TBL_MUL_P5_DROP_PKT_DEFAULT 0x0 - /*[field] MUL_P5_DROP_BYTE*/ - #define MUL_P5_DROP_CNT_TBL_MUL_P5_DROP_BYTE - #define MUL_P5_DROP_CNT_TBL_MUL_P5_DROP_BYTE_OFFSET 32 - #define MUL_P5_DROP_CNT_TBL_MUL_P5_DROP_BYTE_LEN 40 - #define MUL_P5_DROP_CNT_TBL_MUL_P5_DROP_BYTE_DEFAULT 0x0 - -struct mul_p5_drop_cnt_tbl { - a_uint32_t mul_p5_drop_pkt:32; - a_uint32_t mul_p5_drop_byte_0:32; - a_uint32_t mul_p5_drop_byte_1:8; - a_uint32_t _reserved0:24; -}; - -union mul_p5_drop_cnt_tbl_u { - a_uint32_t val[3]; - struct mul_p5_drop_cnt_tbl bf; -}; - -/*[table] MUL_P6_DROP_CNT_TBL*/ -#define MUL_P6_DROP_CNT_TBL -#define MUL_P6_DROP_CNT_TBL_ADDRESS 0x1f6000 -#define MUL_P6_DROP_CNT_TBL_NUM 12 -#define MUL_P6_DROP_CNT_TBL_INC 0x10 -#define MUL_P6_DROP_CNT_TBL_TYPE REG_TYPE_RW -#define MUL_P6_DROP_CNT_TBL_DEFAULT 0x0 - /*[field] MUL_P6_DROP_PKT*/ - #define MUL_P6_DROP_CNT_TBL_MUL_P6_DROP_PKT - #define MUL_P6_DROP_CNT_TBL_MUL_P6_DROP_PKT_OFFSET 0 - #define MUL_P6_DROP_CNT_TBL_MUL_P6_DROP_PKT_LEN 32 - #define MUL_P6_DROP_CNT_TBL_MUL_P6_DROP_PKT_DEFAULT 0x0 - /*[field] MUL_P6_DROP_BYTE*/ - #define MUL_P6_DROP_CNT_TBL_MUL_P6_DROP_BYTE - #define MUL_P6_DROP_CNT_TBL_MUL_P6_DROP_BYTE_OFFSET 32 - #define MUL_P6_DROP_CNT_TBL_MUL_P6_DROP_BYTE_LEN 40 - #define MUL_P6_DROP_CNT_TBL_MUL_P6_DROP_BYTE_DEFAULT 0x0 - -struct mul_p6_drop_cnt_tbl { - a_uint32_t mul_p6_drop_pkt:32; - a_uint32_t mul_p6_drop_byte_0:32; - a_uint32_t mul_p6_drop_byte_1:8; - a_uint32_t _reserved0:24; -}; - -union mul_p6_drop_cnt_tbl_u { - a_uint32_t val[3]; - struct mul_p6_drop_cnt_tbl bf; -}; - -/*[table] MUL_P7_DROP_CNT_TBL*/ -#define MUL_P7_DROP_CNT_TBL -#define MUL_P7_DROP_CNT_TBL_ADDRESS 0x1f7000 -#define MUL_P7_DROP_CNT_TBL_NUM 12 -#define MUL_P7_DROP_CNT_TBL_INC 0x10 -#define MUL_P7_DROP_CNT_TBL_TYPE REG_TYPE_RW -#define MUL_P7_DROP_CNT_TBL_DEFAULT 0x0 - /*[field] MUL_P7_DROP_PKT*/ - #define MUL_P7_DROP_CNT_TBL_MUL_P7_DROP_PKT - #define MUL_P7_DROP_CNT_TBL_MUL_P7_DROP_PKT_OFFSET 0 - #define MUL_P7_DROP_CNT_TBL_MUL_P7_DROP_PKT_LEN 32 - #define MUL_P7_DROP_CNT_TBL_MUL_P7_DROP_PKT_DEFAULT 0x0 - /*[field] MUL_P7_DROP_BYTE*/ - #define MUL_P7_DROP_CNT_TBL_MUL_P7_DROP_BYTE - #define MUL_P7_DROP_CNT_TBL_MUL_P7_DROP_BYTE_OFFSET 32 - #define MUL_P7_DROP_CNT_TBL_MUL_P7_DROP_BYTE_LEN 40 - #define MUL_P7_DROP_CNT_TBL_MUL_P7_DROP_BYTE_DEFAULT 0x0 - -struct mul_p7_drop_cnt_tbl { - a_uint32_t mul_p7_drop_pkt:32; - a_uint32_t mul_p7_drop_byte_0:32; - a_uint32_t mul_p7_drop_byte_1:8; - a_uint32_t _reserved0:24; -}; - -union mul_p7_drop_cnt_tbl_u { - a_uint32_t val[3]; - struct mul_p7_drop_cnt_tbl bf; -}; - -/*[table] UQ_AGG_PROFILE_MAP*/ -#define UQ_AGG_PROFILE_MAP -#define UQ_AGG_PROFILE_MAP_ADDRESS 0x1f8000 -#define UQ_AGG_PROFILE_MAP_NUM 256 -#define UQ_AGG_PROFILE_MAP_INC 0x10 -#define UQ_AGG_PROFILE_MAP_TYPE REG_TYPE_RW -#define UQ_AGG_PROFILE_MAP_DEFAULT 0x0 - /*[field] QID_2_AGG_ID*/ - #define UQ_AGG_PROFILE_MAP_QID_2_AGG_ID - #define UQ_AGG_PROFILE_MAP_QID_2_AGG_ID_OFFSET 0 - #define UQ_AGG_PROFILE_MAP_QID_2_AGG_ID_LEN 3 - #define UQ_AGG_PROFILE_MAP_QID_2_AGG_ID_DEFAULT 0x0 - /*[field] ENABLE*/ - #define UQ_AGG_PROFILE_MAP_ENABLE - #define UQ_AGG_PROFILE_MAP_ENABLE_OFFSET 3 - #define UQ_AGG_PROFILE_MAP_ENABLE_LEN 1 - #define UQ_AGG_PROFILE_MAP_ENABLE_DEFAULT 0x0 - -struct uq_agg_profile_map { - a_uint32_t qid_2_agg_id:3; - a_uint32_t enable:1; - a_uint32_t _reserved0:28; -}; - -union uq_agg_profile_map_u { - a_uint32_t val; - struct uq_agg_profile_map bf; -}; - -/*[table] QUEUE_TX_COUNTER_TBL*/ -#define QUEUE_TX_COUNTER_TBL -#define QUEUE_TX_COUNTER_TBL_ADDRESS 0x4000 -#define QUEUE_TX_COUNTER_TBL_NUM 300 -#define QUEUE_TX_COUNTER_TBL_INC 0x10 -#define QUEUE_TX_COUNTER_TBL_TYPE REG_TYPE_RW -#define QUEUE_TX_COUNTER_TBL_DEFAULT 0x0 - /*[field] TX_PACKETS*/ - #define QUEUE_TX_COUNTER_TBL_TX_PACKETS - #define QUEUE_TX_COUNTER_TBL_TX_PACKETS_OFFSET 0 - #define QUEUE_TX_COUNTER_TBL_TX_PACKETS_LEN 32 - #define QUEUE_TX_COUNTER_TBL_TX_PACKETS_DEFAULT 0x0 - /*[field] TX_BYTES*/ - #define QUEUE_TX_COUNTER_TBL_TX_BYTES - #define QUEUE_TX_COUNTER_TBL_TX_BYTES_OFFSET 32 - #define QUEUE_TX_COUNTER_TBL_TX_BYTES_LEN 40 - #define QUEUE_TX_COUNTER_TBL_TX_BYTES_DEFAULT 0x0 - -struct queue_tx_counter_tbl { - a_uint32_t tx_packets:32; - a_uint32_t tx_bytes_0:32; - a_uint32_t tx_bytes_1:8; - a_uint32_t _reserved0:24; -}; - -union queue_tx_counter_tbl_u { - a_uint32_t val[3]; - struct queue_tx_counter_tbl bf; -}; - -#endif diff --git a/feeds/ipq807x/qca-ssdk/src/include/hsl/hppe/hppe_qos.h b/feeds/ipq807x/qca-ssdk/src/include/hsl/hppe/hppe_qos.h deleted file mode 100755 index 353290b75..000000000 --- a/feeds/ipq807x/qca-ssdk/src/include/hsl/hppe/hppe_qos.h +++ /dev/null @@ -1,2163 +0,0 @@ -/* - * Copyright (c) 2016-2017, The Linux Foundation. All rights reserved. - * Permission to use, copy, modify, and/or distribute this software for - * any purpose with or without fee is hereby granted, provided that the - * above copyright notice and this permission notice appear in all copies. - * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES - * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR - * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES - * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN - * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT - * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. - */ - - -/** - * @defgroup - * @{ - */ -#ifndef _HPPE_QOS_H_ -#define _HPPE_QOS_H_ - -#define L0_FLOW_MAP_TBL_MAX_ENTRY 300 -#define L0_C_SP_CFG_TBL_MAX_ENTRY 512 -#define L0_E_SP_CFG_TBL_MAX_ENTRY 512 -#define L0_FLOW_PORT_MAP_TBL_MAX_ENTRY 300 -#define L0_C_DRR_HEAD_TBL_MAX_ENTRY 160 -#define L0_E_DRR_HEAD_TBL_MAX_ENTRY 160 -#define L0_DRR_CREDIT_TBL_MAX_ENTRY 300 -#define L0_C_DRR_LL_TBL_MAX_ENTRY 300 -#define L0_C_DRR_REVERSE_LL_TBL_MAX_ENTRY 300 -#define L0_E_DRR_LL_TBL_MAX_ENTRY 300 -#define L0_E_DRR_REVERSE_LL_TBL_MAX_ENTRY 300 -#define L0_SP_ENTRY_TBL_MAX_ENTRY 64 -#define L0_ENS_Q_LL_TBL_MAX_ENTRY 300 -#define L0_ENS_Q_HEAD_TBL_MAX_ENTRY 8 -#define L0_ENS_Q_ENTRY_TBL_MAX_ENTRY 300 -#define L0_FLOW_STATUS_TBL_MAX_ENTRY 300 -#define RING_Q_MAP_TBL_MAX_ENTRY 16 -#define RFC_BLOCK_TBL_MAX_ENTRY 300 -#define RFC_STATUS_TBL_MAX_ENTRY 300 -#define DEQ_DIS_TBL_MAX_ENTRY 300 -#define L1_FLOW_MAP_TBL_MAX_ENTRY 64 -#define L1_C_SP_CFG_TBL_MAX_ENTRY 64 -#define L1_E_SP_CFG_TBL_MAX_ENTRY 64 -#define L1_FLOW_PORT_MAP_TBL_MAX_ENTRY 64 -#define L1_C_DRR_HEAD_TBL_MAX_ENTRY 36 -#define L1_E_DRR_HEAD_TBL_MAX_ENTRY 36 -#define L1_DRR_CREDIT_TBL_MAX_ENTRY 64 -#define L1_C_DRR_LL_TBL_MAX_ENTRY 64 -#define L1_C_DRR_REVERSE_LL_TBL_MAX_ENTRY 64 -#define L1_E_DRR_LL_TBL_MAX_ENTRY 64 -#define L1_E_DRR_REVERSE_LL_TBL_MAX_ENTRY 64 -#define L1_A_FLOW_ENTRY_TBL_MAX_ENTRY 64 -#define L1_B_FLOW_ENTRY_TBL_MAX_ENTRY 64 -#define L1_SP_ENTRY_TBL_MAX_ENTRY 8 - -#define L1_ENS_Q_LL_TBL_MAX_ENTRY 64 -#define L1_ENS_Q_HEAD_TBL_MAX_ENTRY 8 -#define L1_ENS_Q_ENTRY_TBL_MAX_ENTRY 64 -#define L1_FLOW_STATUS_TBL_MAX_ENTRY 64 -#define PSCH_TDM_CFG_TBL_MAX_ENTRY 128 - -#define PORT_QOS_CTRL_MAX_ENTRY 8 -#define PCP_QOS_GROUP_0_MAX_ENTRY 16 -#define PCP_QOS_GROUP_1_MAX_ENTRY 16 -#define FLOW_QOS_GROUP_0_MAX_ENTRY 32 -#define FLOW_QOS_GROUP_1_MAX_ENTRY 32 -#define DSCP_QOS_GROUP_0_MAX_ENTRY 64 -#define DSCP_QOS_GROUP_1_MAX_ENTRY 64 - -sw_error_t -hppe_dscp_qos_group_0_get( - a_uint32_t dev_id, - a_uint32_t index, - union dscp_qos_group_0_u *value); - -sw_error_t -hppe_dscp_qos_group_0_set( - a_uint32_t dev_id, - a_uint32_t index, - union dscp_qos_group_0_u *value); - -sw_error_t -hppe_dscp_qos_group_1_get( - a_uint32_t dev_id, - a_uint32_t index, - union dscp_qos_group_1_u *value); - -sw_error_t -hppe_dscp_qos_group_1_set( - a_uint32_t dev_id, - a_uint32_t index, - union dscp_qos_group_1_u *value); - - -sw_error_t -hppe_pcp_qos_group_0_get( - a_uint32_t dev_id, - a_uint32_t index, - union pcp_qos_group_0_u *value); - -sw_error_t -hppe_pcp_qos_group_0_set( - a_uint32_t dev_id, - a_uint32_t index, - union pcp_qos_group_0_u *value); - -sw_error_t -hppe_pcp_qos_group_1_get( - a_uint32_t dev_id, - a_uint32_t index, - union pcp_qos_group_1_u *value); - -sw_error_t -hppe_pcp_qos_group_1_set( - a_uint32_t dev_id, - a_uint32_t index, - union pcp_qos_group_1_u *value); - -sw_error_t -hppe_flow_qos_group_0_get( - a_uint32_t dev_id, - a_uint32_t index, - union flow_qos_group_0_u *value); - -sw_error_t -hppe_flow_qos_group_0_set( - a_uint32_t dev_id, - a_uint32_t index, - union flow_qos_group_0_u *value); - -sw_error_t -hppe_flow_qos_group_1_get( - a_uint32_t dev_id, - a_uint32_t index, - union flow_qos_group_1_u *value); - -sw_error_t -hppe_flow_qos_group_1_set( - a_uint32_t dev_id, - a_uint32_t index, - union flow_qos_group_1_u *value); - -sw_error_t -hppe_port_qos_ctrl_get( - a_uint32_t dev_id, - a_uint32_t index, - union port_qos_ctrl_u *value); - -sw_error_t -hppe_port_qos_ctrl_set( - a_uint32_t dev_id, - a_uint32_t index, - union port_qos_ctrl_u *value); - -sw_error_t -hppe_tdm_depth_cfg_get( - a_uint32_t dev_id, - union tdm_depth_cfg_u *value); - -sw_error_t -hppe_tdm_depth_cfg_set( - a_uint32_t dev_id, - union tdm_depth_cfg_u *value); - -sw_error_t -hppe_min_max_mode_cfg_get( - a_uint32_t dev_id, - union min_max_mode_cfg_u *value); - -sw_error_t -hppe_min_max_mode_cfg_set( - a_uint32_t dev_id, - union min_max_mode_cfg_u *value); - -sw_error_t -hppe_tm_dbg_addr_get( - a_uint32_t dev_id, - union tm_dbg_addr_u *value); - -sw_error_t -hppe_tm_dbg_addr_set( - a_uint32_t dev_id, - union tm_dbg_addr_u *value); - -sw_error_t -hppe_tm_dbg_data_get( - a_uint32_t dev_id, - union tm_dbg_data_u *value); - -sw_error_t -hppe_tm_dbg_data_set( - a_uint32_t dev_id, - union tm_dbg_data_u *value); - -sw_error_t -hppe_eco_reserve_0_get( - a_uint32_t dev_id, - union eco_reserve_0_u *value); - -sw_error_t -hppe_eco_reserve_0_set( - a_uint32_t dev_id, - union eco_reserve_0_u *value); - -sw_error_t -hppe_eco_reserve_1_get( - a_uint32_t dev_id, - union eco_reserve_1_u *value); - -sw_error_t -hppe_eco_reserve_1_set( - a_uint32_t dev_id, - union eco_reserve_1_u *value); - -sw_error_t -hppe_l0_flow_map_tbl_get( - a_uint32_t dev_id, - a_uint32_t index, - union l0_flow_map_tbl_u *value); - -sw_error_t -hppe_l0_flow_map_tbl_set( - a_uint32_t dev_id, - a_uint32_t index, - union l0_flow_map_tbl_u *value); - -sw_error_t -hppe_l0_c_sp_cfg_tbl_get( - a_uint32_t dev_id, - a_uint32_t index, - union l0_c_sp_cfg_tbl_u *value); - -sw_error_t -hppe_l0_c_sp_cfg_tbl_set( - a_uint32_t dev_id, - a_uint32_t index, - union l0_c_sp_cfg_tbl_u *value); - -sw_error_t -hppe_l0_e_sp_cfg_tbl_get( - a_uint32_t dev_id, - a_uint32_t index, - union l0_e_sp_cfg_tbl_u *value); - -sw_error_t -hppe_l0_e_sp_cfg_tbl_set( - a_uint32_t dev_id, - a_uint32_t index, - union l0_e_sp_cfg_tbl_u *value); - -sw_error_t -hppe_l0_flow_port_map_tbl_get( - a_uint32_t dev_id, - a_uint32_t index, - union l0_flow_port_map_tbl_u *value); - -sw_error_t -hppe_l0_flow_port_map_tbl_set( - a_uint32_t dev_id, - a_uint32_t index, - union l0_flow_port_map_tbl_u *value); - -sw_error_t -hppe_l0_c_drr_head_tbl_get( - a_uint32_t dev_id, - a_uint32_t index, - union l0_c_drr_head_tbl_u *value); - -sw_error_t -hppe_l0_c_drr_head_tbl_set( - a_uint32_t dev_id, - a_uint32_t index, - union l0_c_drr_head_tbl_u *value); - -sw_error_t -hppe_l0_e_drr_head_tbl_get( - a_uint32_t dev_id, - a_uint32_t index, - union l0_e_drr_head_tbl_u *value); - -sw_error_t -hppe_l0_e_drr_head_tbl_set( - a_uint32_t dev_id, - a_uint32_t index, - union l0_e_drr_head_tbl_u *value); - -sw_error_t -hppe_l0_drr_credit_tbl_get( - a_uint32_t dev_id, - a_uint32_t index, - union l0_drr_credit_tbl_u *value); - -sw_error_t -hppe_l0_drr_credit_tbl_set( - a_uint32_t dev_id, - a_uint32_t index, - union l0_drr_credit_tbl_u *value); - -sw_error_t -hppe_l0_c_drr_ll_tbl_get( - a_uint32_t dev_id, - a_uint32_t index, - union l0_c_drr_ll_tbl_u *value); - -sw_error_t -hppe_l0_c_drr_ll_tbl_set( - a_uint32_t dev_id, - a_uint32_t index, - union l0_c_drr_ll_tbl_u *value); - -sw_error_t -hppe_l0_c_drr_reverse_ll_tbl_get( - a_uint32_t dev_id, - a_uint32_t index, - union l0_c_drr_reverse_ll_tbl_u *value); - -sw_error_t -hppe_l0_c_drr_reverse_ll_tbl_set( - a_uint32_t dev_id, - a_uint32_t index, - union l0_c_drr_reverse_ll_tbl_u *value); - -sw_error_t -hppe_l0_e_drr_ll_tbl_get( - a_uint32_t dev_id, - a_uint32_t index, - union l0_e_drr_ll_tbl_u *value); - -sw_error_t -hppe_l0_e_drr_ll_tbl_set( - a_uint32_t dev_id, - a_uint32_t index, - union l0_e_drr_ll_tbl_u *value); - -sw_error_t -hppe_l0_e_drr_reverse_ll_tbl_get( - a_uint32_t dev_id, - a_uint32_t index, - union l0_e_drr_reverse_ll_tbl_u *value); - -sw_error_t -hppe_l0_e_drr_reverse_ll_tbl_set( - a_uint32_t dev_id, - a_uint32_t index, - union l0_e_drr_reverse_ll_tbl_u *value); - -sw_error_t -hppe_l0_sp_entry_tbl_get( - a_uint32_t dev_id, - a_uint32_t index, - union l0_sp_entry_tbl_u *value); - -sw_error_t -hppe_l0_sp_entry_tbl_set( - a_uint32_t dev_id, - a_uint32_t index, - union l0_sp_entry_tbl_u *value); - -sw_error_t -hppe_l0_ens_q_ll_tbl_get( - a_uint32_t dev_id, - a_uint32_t index, - union l0_ens_q_ll_tbl_u *value); - -sw_error_t -hppe_l0_ens_q_ll_tbl_set( - a_uint32_t dev_id, - a_uint32_t index, - union l0_ens_q_ll_tbl_u *value); - -sw_error_t -hppe_l0_ens_q_head_tbl_get( - a_uint32_t dev_id, - a_uint32_t index, - union l0_ens_q_head_tbl_u *value); - -sw_error_t -hppe_l0_ens_q_head_tbl_set( - a_uint32_t dev_id, - a_uint32_t index, - union l0_ens_q_head_tbl_u *value); - -sw_error_t -hppe_l0_ens_q_entry_tbl_get( - a_uint32_t dev_id, - a_uint32_t index, - union l0_ens_q_entry_tbl_u *value); - -sw_error_t -hppe_l0_ens_q_entry_tbl_set( - a_uint32_t dev_id, - a_uint32_t index, - union l0_ens_q_entry_tbl_u *value); - -sw_error_t -hppe_l0_flow_status_tbl_get( - a_uint32_t dev_id, - a_uint32_t index, - union l0_flow_status_tbl_u *value); - -sw_error_t -hppe_l0_flow_status_tbl_set( - a_uint32_t dev_id, - a_uint32_t index, - union l0_flow_status_tbl_u *value); - -sw_error_t -hppe_ring_q_map_tbl_get( - a_uint32_t dev_id, - a_uint32_t index, - union ring_q_map_tbl_u *value); - -sw_error_t -hppe_ring_q_map_tbl_set( - a_uint32_t dev_id, - a_uint32_t index, - union ring_q_map_tbl_u *value); - -sw_error_t -hppe_rfc_block_tbl_get( - a_uint32_t dev_id, - a_uint32_t index, - union rfc_block_tbl_u *value); - -sw_error_t -hppe_rfc_block_tbl_set( - a_uint32_t dev_id, - a_uint32_t index, - union rfc_block_tbl_u *value); - -sw_error_t -hppe_rfc_status_tbl_get( - a_uint32_t dev_id, - a_uint32_t index, - union rfc_status_tbl_u *value); - -sw_error_t -hppe_rfc_status_tbl_set( - a_uint32_t dev_id, - a_uint32_t index, - union rfc_status_tbl_u *value); - -sw_error_t -hppe_deq_dis_tbl_get( - a_uint32_t dev_id, - a_uint32_t index, - union deq_dis_tbl_u *value); - -sw_error_t -hppe_deq_dis_tbl_set( - a_uint32_t dev_id, - a_uint32_t index, - union deq_dis_tbl_u *value); - -sw_error_t -hppe_l1_flow_map_tbl_get( - a_uint32_t dev_id, - a_uint32_t index, - union l1_flow_map_tbl_u *value); - -sw_error_t -hppe_l1_flow_map_tbl_set( - a_uint32_t dev_id, - a_uint32_t index, - union l1_flow_map_tbl_u *value); - -sw_error_t -hppe_l1_c_sp_cfg_tbl_get( - a_uint32_t dev_id, - a_uint32_t index, - union l1_c_sp_cfg_tbl_u *value); - -sw_error_t -hppe_l1_c_sp_cfg_tbl_set( - a_uint32_t dev_id, - a_uint32_t index, - union l1_c_sp_cfg_tbl_u *value); - -sw_error_t -hppe_l1_e_sp_cfg_tbl_get( - a_uint32_t dev_id, - a_uint32_t index, - union l1_e_sp_cfg_tbl_u *value); - -sw_error_t -hppe_l1_e_sp_cfg_tbl_set( - a_uint32_t dev_id, - a_uint32_t index, - union l1_e_sp_cfg_tbl_u *value); - -sw_error_t -hppe_l1_flow_port_map_tbl_get( - a_uint32_t dev_id, - a_uint32_t index, - union l1_flow_port_map_tbl_u *value); - -sw_error_t -hppe_l1_flow_port_map_tbl_set( - a_uint32_t dev_id, - a_uint32_t index, - union l1_flow_port_map_tbl_u *value); - -sw_error_t -hppe_l1_c_drr_head_tbl_get( - a_uint32_t dev_id, - a_uint32_t index, - union l1_c_drr_head_tbl_u *value); - -sw_error_t -hppe_l1_c_drr_head_tbl_set( - a_uint32_t dev_id, - a_uint32_t index, - union l1_c_drr_head_tbl_u *value); - -sw_error_t -hppe_l1_e_drr_head_tbl_get( - a_uint32_t dev_id, - a_uint32_t index, - union l1_e_drr_head_tbl_u *value); - -sw_error_t -hppe_l1_e_drr_head_tbl_set( - a_uint32_t dev_id, - a_uint32_t index, - union l1_e_drr_head_tbl_u *value); - -sw_error_t -hppe_l1_drr_credit_tbl_get( - a_uint32_t dev_id, - a_uint32_t index, - union l1_drr_credit_tbl_u *value); - -sw_error_t -hppe_l1_drr_credit_tbl_set( - a_uint32_t dev_id, - a_uint32_t index, - union l1_drr_credit_tbl_u *value); - -sw_error_t -hppe_l1_c_drr_ll_tbl_get( - a_uint32_t dev_id, - a_uint32_t index, - union l1_c_drr_ll_tbl_u *value); - -sw_error_t -hppe_l1_c_drr_ll_tbl_set( - a_uint32_t dev_id, - a_uint32_t index, - union l1_c_drr_ll_tbl_u *value); - -sw_error_t -hppe_l1_c_drr_reverse_ll_tbl_get( - a_uint32_t dev_id, - a_uint32_t index, - union l1_c_drr_reverse_ll_tbl_u *value); - -sw_error_t -hppe_l1_c_drr_reverse_ll_tbl_set( - a_uint32_t dev_id, - a_uint32_t index, - union l1_c_drr_reverse_ll_tbl_u *value); - -sw_error_t -hppe_l1_e_drr_ll_tbl_get( - a_uint32_t dev_id, - a_uint32_t index, - union l1_e_drr_ll_tbl_u *value); - -sw_error_t -hppe_l1_e_drr_ll_tbl_set( - a_uint32_t dev_id, - a_uint32_t index, - union l1_e_drr_ll_tbl_u *value); - -sw_error_t -hppe_l1_e_drr_reverse_ll_tbl_get( - a_uint32_t dev_id, - a_uint32_t index, - union l1_e_drr_reverse_ll_tbl_u *value); - -sw_error_t -hppe_l1_e_drr_reverse_ll_tbl_set( - a_uint32_t dev_id, - a_uint32_t index, - union l1_e_drr_reverse_ll_tbl_u *value); - -sw_error_t -hppe_l1_a_flow_entry_tbl_get( - a_uint32_t dev_id, - a_uint32_t index, - union l1_a_flow_entry_tbl_u *value); - -sw_error_t -hppe_l1_a_flow_entry_tbl_set( - a_uint32_t dev_id, - a_uint32_t index, - union l1_a_flow_entry_tbl_u *value); - -sw_error_t -hppe_l1_b_flow_entry_tbl_get( - a_uint32_t dev_id, - a_uint32_t index, - union l1_b_flow_entry_tbl_u *value); - -sw_error_t -hppe_l1_b_flow_entry_tbl_set( - a_uint32_t dev_id, - a_uint32_t index, - union l1_b_flow_entry_tbl_u *value); - -sw_error_t -hppe_l1_sp_entry_tbl_get( - a_uint32_t dev_id, - a_uint32_t index, - union l1_sp_entry_tbl_u *value); - -sw_error_t -hppe_l1_sp_entry_tbl_set( - a_uint32_t dev_id, - a_uint32_t index, - union l1_sp_entry_tbl_u *value); - -sw_error_t -hppe_l1_ens_q_ll_tbl_get( - a_uint32_t dev_id, - a_uint32_t index, - union l1_ens_q_ll_tbl_u *value); - -sw_error_t -hppe_l1_ens_q_ll_tbl_set( - a_uint32_t dev_id, - a_uint32_t index, - union l1_ens_q_ll_tbl_u *value); - -sw_error_t -hppe_l1_ens_q_head_tbl_get( - a_uint32_t dev_id, - a_uint32_t index, - union l1_ens_q_head_tbl_u *value); - -sw_error_t -hppe_l1_ens_q_head_tbl_set( - a_uint32_t dev_id, - a_uint32_t index, - union l1_ens_q_head_tbl_u *value); - -sw_error_t -hppe_l1_ens_q_entry_tbl_get( - a_uint32_t dev_id, - a_uint32_t index, - union l1_ens_q_entry_tbl_u *value); - -sw_error_t -hppe_l1_ens_q_entry_tbl_set( - a_uint32_t dev_id, - a_uint32_t index, - union l1_ens_q_entry_tbl_u *value); - -sw_error_t -hppe_l1_flow_status_tbl_get( - a_uint32_t dev_id, - a_uint32_t index, - union l1_flow_status_tbl_u *value); - -sw_error_t -hppe_l1_flow_status_tbl_set( - a_uint32_t dev_id, - a_uint32_t index, - union l1_flow_status_tbl_u *value); - -sw_error_t -hppe_psch_tdm_cfg_tbl_get( - a_uint32_t dev_id, - a_uint32_t index, - union psch_tdm_cfg_tbl_u *value); - -sw_error_t -hppe_psch_tdm_cfg_tbl_set( - a_uint32_t dev_id, - a_uint32_t index, - union psch_tdm_cfg_tbl_u *value); - -sw_error_t -hppe_tdm_depth_cfg_tdm_depth_get( - a_uint32_t dev_id, - unsigned int *value); - -sw_error_t -hppe_tdm_depth_cfg_tdm_depth_set( - a_uint32_t dev_id, - unsigned int value); - -sw_error_t -hppe_min_max_mode_cfg_min_max_mode_get( - a_uint32_t dev_id, - unsigned int *value); - -sw_error_t -hppe_min_max_mode_cfg_min_max_mode_set( - a_uint32_t dev_id, - unsigned int value); - -sw_error_t -hppe_tm_dbg_addr_dbg_addr_get( - a_uint32_t dev_id, - unsigned int *value); - -sw_error_t -hppe_tm_dbg_addr_dbg_addr_set( - a_uint32_t dev_id, - unsigned int value); - -sw_error_t -hppe_tm_dbg_data_dbg_data_get( - a_uint32_t dev_id, - unsigned int *value); - -sw_error_t -hppe_tm_dbg_data_dbg_data_set( - a_uint32_t dev_id, - unsigned int value); - -sw_error_t -hppe_eco_reserve_0_eco_res_0_get( - a_uint32_t dev_id, - unsigned int *value); - -sw_error_t -hppe_eco_reserve_0_eco_res_0_set( - a_uint32_t dev_id, - unsigned int value); - -sw_error_t -hppe_eco_reserve_1_eco_res_1_get( - a_uint32_t dev_id, - unsigned int *value); - -sw_error_t -hppe_eco_reserve_1_eco_res_1_set( - a_uint32_t dev_id, - unsigned int value); - -sw_error_t -hppe_l0_flow_map_tbl_e_pri_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_l0_flow_map_tbl_e_pri_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_l0_flow_map_tbl_c_pri_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_l0_flow_map_tbl_c_pri_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_l0_flow_map_tbl_e_drr_wt_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_l0_flow_map_tbl_e_drr_wt_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_l0_flow_map_tbl_c_drr_wt_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_l0_flow_map_tbl_c_drr_wt_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_l0_flow_map_tbl_sp_id_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_l0_flow_map_tbl_sp_id_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_l0_c_sp_cfg_tbl_drr_credit_unit_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_l0_c_sp_cfg_tbl_drr_credit_unit_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_l0_c_sp_cfg_tbl_drr_id_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_l0_c_sp_cfg_tbl_drr_id_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_l0_e_sp_cfg_tbl_drr_credit_unit_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_l0_e_sp_cfg_tbl_drr_credit_unit_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_l0_e_sp_cfg_tbl_drr_id_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_l0_e_sp_cfg_tbl_drr_id_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_l0_flow_port_map_tbl_port_num_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_l0_flow_port_map_tbl_port_num_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_l0_c_drr_head_tbl_backup_head_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_l0_c_drr_head_tbl_backup_head_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_l0_c_drr_head_tbl_active_vld_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_l0_c_drr_head_tbl_active_vld_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_l0_c_drr_head_tbl_backup_max_n_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_l0_c_drr_head_tbl_backup_max_n_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_l0_c_drr_head_tbl_active_tail_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_l0_c_drr_head_tbl_active_tail_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_l0_c_drr_head_tbl_active_head_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_l0_c_drr_head_tbl_active_head_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_l0_c_drr_head_tbl_backup_vld_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_l0_c_drr_head_tbl_backup_vld_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_l0_c_drr_head_tbl_active_max_n_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_l0_c_drr_head_tbl_active_max_n_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_l0_c_drr_head_tbl_backup_tail_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_l0_c_drr_head_tbl_backup_tail_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_l0_e_drr_head_tbl_backup_head_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_l0_e_drr_head_tbl_backup_head_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_l0_e_drr_head_tbl_active_vld_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_l0_e_drr_head_tbl_active_vld_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_l0_e_drr_head_tbl_backup_max_n_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_l0_e_drr_head_tbl_backup_max_n_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_l0_e_drr_head_tbl_active_tail_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_l0_e_drr_head_tbl_active_tail_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_l0_e_drr_head_tbl_active_head_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_l0_e_drr_head_tbl_active_head_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_l0_e_drr_head_tbl_backup_vld_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_l0_e_drr_head_tbl_backup_vld_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_l0_e_drr_head_tbl_active_max_n_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_l0_e_drr_head_tbl_active_max_n_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_l0_e_drr_head_tbl_backup_tail_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_l0_e_drr_head_tbl_backup_tail_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_l0_drr_credit_tbl_e_drr_credit_neg_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_l0_drr_credit_tbl_e_drr_credit_neg_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_l0_drr_credit_tbl_c_drr_credit_neg_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_l0_drr_credit_tbl_c_drr_credit_neg_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_l0_drr_credit_tbl_c_drr_credit_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_l0_drr_credit_tbl_c_drr_credit_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_l0_drr_credit_tbl_e_drr_credit_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_l0_drr_credit_tbl_e_drr_credit_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_l0_c_drr_ll_tbl_next_ptr_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_l0_c_drr_ll_tbl_next_ptr_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_l0_c_drr_reverse_ll_tbl_pre_ptr_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_l0_c_drr_reverse_ll_tbl_pre_ptr_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_l0_e_drr_ll_tbl_next_ptr_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_l0_e_drr_ll_tbl_next_ptr_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_l0_e_drr_reverse_ll_tbl_pre_ptr_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_l0_e_drr_reverse_ll_tbl_pre_ptr_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_l0_sp_entry_tbl_entry_vld_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_l0_sp_entry_tbl_entry_vld_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_l0_sp_entry_tbl_entry_path_id_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint64_t *value); - -sw_error_t -hppe_l0_sp_entry_tbl_entry_path_id_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint64_t value); - -sw_error_t -hppe_l0_ens_q_ll_tbl_next_ptr_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_l0_ens_q_ll_tbl_next_ptr_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_l0_ens_q_head_tbl_vld_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_l0_ens_q_head_tbl_vld_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_l0_ens_q_head_tbl_head_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_l0_ens_q_head_tbl_head_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_l0_ens_q_head_tbl_tail_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_l0_ens_q_head_tbl_tail_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_l0_ens_q_entry_tbl_entry_ens_in_q_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_l0_ens_q_entry_tbl_entry_ens_in_q_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_l0_ens_q_entry_tbl_entry_ens_vld_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_l0_ens_q_entry_tbl_entry_ens_vld_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_l0_ens_q_entry_tbl_entry_ens_type_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_l0_ens_q_entry_tbl_entry_ens_type_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_l0_flow_status_tbl_en_cdrr_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_l0_flow_status_tbl_en_cdrr_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_l0_flow_status_tbl_en_edrr_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_l0_flow_status_tbl_en_edrr_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_l0_flow_status_tbl_en_level_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_l0_flow_status_tbl_en_level_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_ring_q_map_tbl_queue_bitmap_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint64_t *value); - -sw_error_t -hppe_ring_q_map_tbl_queue_bitmap_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint64_t value); - -sw_error_t -hppe_rfc_block_tbl_rfc_block_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_rfc_block_tbl_rfc_block_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_rfc_status_tbl_rfc_status_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_rfc_status_tbl_rfc_status_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_deq_dis_tbl_deq_dis_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_deq_dis_tbl_deq_dis_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_l1_flow_map_tbl_e_pri_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_l1_flow_map_tbl_e_pri_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_l1_flow_map_tbl_c_pri_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_l1_flow_map_tbl_c_pri_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_l1_flow_map_tbl_e_drr_wt_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_l1_flow_map_tbl_e_drr_wt_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_l1_flow_map_tbl_c_drr_wt_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_l1_flow_map_tbl_c_drr_wt_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_l1_flow_map_tbl_sp_id_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_l1_flow_map_tbl_sp_id_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_l1_c_sp_cfg_tbl_drr_credit_unit_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_l1_c_sp_cfg_tbl_drr_credit_unit_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_l1_c_sp_cfg_tbl_drr_id_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_l1_c_sp_cfg_tbl_drr_id_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_l1_e_sp_cfg_tbl_drr_credit_unit_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_l1_e_sp_cfg_tbl_drr_credit_unit_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_l1_e_sp_cfg_tbl_drr_id_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_l1_e_sp_cfg_tbl_drr_id_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_l1_flow_port_map_tbl_port_num_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_l1_flow_port_map_tbl_port_num_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_l1_c_drr_head_tbl_backup_head_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_l1_c_drr_head_tbl_backup_head_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_l1_c_drr_head_tbl_active_vld_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_l1_c_drr_head_tbl_active_vld_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_l1_c_drr_head_tbl_backup_max_n_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_l1_c_drr_head_tbl_backup_max_n_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_l1_c_drr_head_tbl_active_tail_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_l1_c_drr_head_tbl_active_tail_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_l1_c_drr_head_tbl_active_head_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_l1_c_drr_head_tbl_active_head_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_l1_c_drr_head_tbl_backup_vld_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_l1_c_drr_head_tbl_backup_vld_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_l1_c_drr_head_tbl_active_max_n_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_l1_c_drr_head_tbl_active_max_n_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_l1_c_drr_head_tbl_backup_tail_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_l1_c_drr_head_tbl_backup_tail_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_l1_e_drr_head_tbl_backup_head_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_l1_e_drr_head_tbl_backup_head_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_l1_e_drr_head_tbl_active_vld_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_l1_e_drr_head_tbl_active_vld_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_l1_e_drr_head_tbl_backup_max_n_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_l1_e_drr_head_tbl_backup_max_n_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_l1_e_drr_head_tbl_active_tail_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_l1_e_drr_head_tbl_active_tail_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_l1_e_drr_head_tbl_active_head_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_l1_e_drr_head_tbl_active_head_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_l1_e_drr_head_tbl_backup_vld_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_l1_e_drr_head_tbl_backup_vld_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_l1_e_drr_head_tbl_active_max_n_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_l1_e_drr_head_tbl_active_max_n_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_l1_e_drr_head_tbl_backup_tail_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_l1_e_drr_head_tbl_backup_tail_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_l1_drr_credit_tbl_e_drr_credit_neg_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_l1_drr_credit_tbl_e_drr_credit_neg_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_l1_drr_credit_tbl_c_drr_credit_neg_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_l1_drr_credit_tbl_c_drr_credit_neg_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_l1_drr_credit_tbl_c_drr_credit_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_l1_drr_credit_tbl_c_drr_credit_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_l1_drr_credit_tbl_e_drr_credit_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_l1_drr_credit_tbl_e_drr_credit_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_l1_c_drr_ll_tbl_next_ptr_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_l1_c_drr_ll_tbl_next_ptr_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_l1_c_drr_reverse_ll_tbl_pre_ptr_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_l1_c_drr_reverse_ll_tbl_pre_ptr_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_l1_e_drr_ll_tbl_next_ptr_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_l1_e_drr_ll_tbl_next_ptr_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_l1_e_drr_reverse_ll_tbl_pre_ptr_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_l1_e_drr_reverse_ll_tbl_pre_ptr_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_l1_a_flow_entry_tbl_entry_path_id_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_l1_a_flow_entry_tbl_entry_path_id_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_l1_b_flow_entry_tbl_entry_path_id_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_l1_b_flow_entry_tbl_entry_path_id_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_l1_sp_entry_tbl_entry_vld_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_l1_sp_entry_tbl_entry_vld_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_l1_sp_entry_tbl_entry_path_id_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint64_t *value); - -sw_error_t -hppe_l1_sp_entry_tbl_entry_path_id_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint64_t value); - -sw_error_t -hppe_l1_ens_q_ll_tbl_next_ptr_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_l1_ens_q_ll_tbl_next_ptr_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_l1_ens_q_head_tbl_vld_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_l1_ens_q_head_tbl_vld_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_l1_ens_q_head_tbl_head_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_l1_ens_q_head_tbl_head_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_l1_ens_q_head_tbl_tail_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_l1_ens_q_head_tbl_tail_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_l1_ens_q_entry_tbl_entry_ens_in_q_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_l1_ens_q_entry_tbl_entry_ens_in_q_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_l1_ens_q_entry_tbl_entry_ens_vld_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_l1_ens_q_entry_tbl_entry_ens_vld_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_l1_ens_q_entry_tbl_entry_ens_type_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_l1_ens_q_entry_tbl_entry_ens_type_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_l1_flow_status_tbl_en_cdrr_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_l1_flow_status_tbl_en_cdrr_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_l1_flow_status_tbl_en_edrr_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_l1_flow_status_tbl_en_edrr_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_l1_flow_status_tbl_en_level_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_l1_flow_status_tbl_en_level_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_psch_tdm_cfg_tbl_ens_port_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_psch_tdm_cfg_tbl_ens_port_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_psch_tdm_cfg_tbl_des_port_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_psch_tdm_cfg_tbl_des_port_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_psch_tdm_cfg_tbl_ens_port_bitmap_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_psch_tdm_cfg_tbl_ens_port_bitmap_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_port_qos_ctrl_port_flow_qos_pri_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_port_qos_ctrl_port_flow_qos_pri_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_port_qos_ctrl_port_dscp_qos_pri_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_port_qos_ctrl_port_dscp_qos_pri_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_port_qos_ctrl_port_dscp_change_en_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_port_qos_ctrl_port_dscp_change_en_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_port_qos_ctrl_port_pcp_change_en_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_port_qos_ctrl_port_pcp_change_en_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_port_qos_ctrl_port_acl_qos_pri_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_port_qos_ctrl_port_acl_qos_pri_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_port_qos_ctrl_flow_qos_group_id_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_port_qos_ctrl_flow_qos_group_id_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_port_qos_ctrl_port_preheader_qos_pri_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_port_qos_ctrl_port_preheader_qos_pri_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_port_qos_ctrl_pcp_qos_group_id_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_port_qos_ctrl_pcp_qos_group_id_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_port_qos_ctrl_dscp_qos_group_id_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_port_qos_ctrl_dscp_qos_group_id_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_port_qos_ctrl_port_pcp_qos_pri_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_port_qos_ctrl_port_pcp_qos_pri_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_port_qos_ctrl_port_dei_change_en_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_port_qos_ctrl_port_dei_change_en_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_pcp_qos_group_0_qos_info_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_pcp_qos_group_0_qos_info_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_pcp_qos_group_1_qos_info_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_pcp_qos_group_1_qos_info_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_flow_qos_group_0_qos_info_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_flow_qos_group_0_qos_info_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_flow_qos_group_1_qos_info_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_flow_qos_group_1_qos_info_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_dscp_qos_group_0_qos_info_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_dscp_qos_group_0_qos_info_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_dscp_qos_group_1_qos_info_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_dscp_qos_group_1_qos_info_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - - -#endif - diff --git a/feeds/ipq807x/qca-ssdk/src/include/hsl/hppe/hppe_qos_reg.h b/feeds/ipq807x/qca-ssdk/src/include/hsl/hppe/hppe_qos_reg.h deleted file mode 100755 index 59decb6d5..000000000 --- a/feeds/ipq807x/qca-ssdk/src/include/hsl/hppe/hppe_qos_reg.h +++ /dev/null @@ -1,1676 +0,0 @@ -/* - * Copyright (c) 2016-2017, The Linux Foundation. All rights reserved. - * Permission to use, copy, modify, and/or distribute this software for - * any purpose with or without fee is hereby granted, provided that the - * above copyright notice and this permission notice appear in all copies. - * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES - * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR - * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES - * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN - * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT - * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. - */ - - -/** - * @defgroup - * @{ - */ -#ifndef HPPE_QOS_REG_H -#define HPPE_QOS_REG_H - -/*[register] TDM_DEPTH_CFG*/ -#define TDM_DEPTH_CFG -#define TDM_DEPTH_CFG_ADDRESS 0x0 -#define TDM_DEPTH_CFG_NUM 1 -#define TDM_DEPTH_CFG_INC 0x4 -#define TDM_DEPTH_CFG_TYPE REG_TYPE_RW -#define TDM_DEPTH_CFG_DEFAULT 0x28 - /*[field] TDM_DEPTH*/ - #define TDM_DEPTH_CFG_TDM_DEPTH - #define TDM_DEPTH_CFG_TDM_DEPTH_OFFSET 0 - #define TDM_DEPTH_CFG_TDM_DEPTH_LEN 8 - #define TDM_DEPTH_CFG_TDM_DEPTH_DEFAULT 0x28 - -struct tdm_depth_cfg { - a_uint32_t tdm_depth:8; - a_uint32_t _reserved0:24; -}; - -union tdm_depth_cfg_u { - a_uint32_t val; - struct tdm_depth_cfg bf; -}; - -/*[register] MIN_MAX_MODE_CFG*/ -#define MIN_MAX_MODE_CFG -#define MIN_MAX_MODE_CFG_ADDRESS 0x4 -#define MIN_MAX_MODE_CFG_NUM 1 -#define MIN_MAX_MODE_CFG_INC 0x4 -#define MIN_MAX_MODE_CFG_TYPE REG_TYPE_RW -#define MIN_MAX_MODE_CFG_DEFAULT 0x0 - /*[field] MIN_MAX_MODE*/ - #define MIN_MAX_MODE_CFG_MIN_MAX_MODE - #define MIN_MAX_MODE_CFG_MIN_MAX_MODE_OFFSET 0 - #define MIN_MAX_MODE_CFG_MIN_MAX_MODE_LEN 1 - #define MIN_MAX_MODE_CFG_MIN_MAX_MODE_DEFAULT 0x0 - -struct min_max_mode_cfg { - a_uint32_t min_max_mode:1; - a_uint32_t _reserved0:31; -}; - -union min_max_mode_cfg_u { - a_uint32_t val; - struct min_max_mode_cfg bf; -}; - - -/*[register] TM_DBG_ADDR*/ -#define TM_DBG_ADDR -#define TM_DBG_ADDR_ADDRESS 0x20 -#define TM_DBG_ADDR_NUM 1 -#define TM_DBG_ADDR_INC 0x4 -#define TM_DBG_ADDR_TYPE REG_TYPE_RW -#define TM_DBG_ADDR_DEFAULT 0x0 - /*[field] DBG_ADDR*/ - #define TM_DBG_ADDR_DBG_ADDR - #define TM_DBG_ADDR_DBG_ADDR_OFFSET 0 - #define TM_DBG_ADDR_DBG_ADDR_LEN 8 - #define TM_DBG_ADDR_DBG_ADDR_DEFAULT 0x0 - -struct tm_dbg_addr { - a_uint32_t dbg_addr:8; - a_uint32_t _reserved0:24; -}; - -union tm_dbg_addr_u { - a_uint32_t val; - struct tm_dbg_addr bf; -}; - -/*[register] TM_DBG_DATA*/ -#define TM_DBG_DATA -#define TM_DBG_DATA_ADDRESS 0x24 -#define TM_DBG_DATA_NUM 1 -#define TM_DBG_DATA_INC 0x4 -#define TM_DBG_DATA_TYPE REG_TYPE_RO -#define TM_DBG_DATA_DEFAULT 0x0 - /*[field] DBG_DATA*/ - #define TM_DBG_DATA_DBG_DATA - #define TM_DBG_DATA_DBG_DATA_OFFSET 0 - #define TM_DBG_DATA_DBG_DATA_LEN 32 - #define TM_DBG_DATA_DBG_DATA_DEFAULT 0x0 - -struct tm_dbg_data { - a_uint32_t dbg_data:32; -}; - -union tm_dbg_data_u { - a_uint32_t val; - struct tm_dbg_data bf; -}; - -/*[register] ECO_RESERVE_0*/ -#define ECO_RESERVE_0 -#define ECO_RESERVE_0_ADDRESS 0x28 -#define ECO_RESERVE_0_NUM 1 -#define ECO_RESERVE_0_INC 0x4 -#define ECO_RESERVE_0_TYPE REG_TYPE_RW -#define ECO_RESERVE_0_DEFAULT 0x0 - /*[field] ECO_RES_0*/ - #define ECO_RESERVE_0_ECO_RES_0 - #define ECO_RESERVE_0_ECO_RES_0_OFFSET 0 - #define ECO_RESERVE_0_ECO_RES_0_LEN 32 - #define ECO_RESERVE_0_ECO_RES_0_DEFAULT 0x0 - -struct eco_reserve_0 { - a_uint32_t eco_res_0:32; -}; - -union eco_reserve_0_u { - a_uint32_t val; - struct eco_reserve_0 bf; -}; - -/*[register] ECO_RESERVE_1*/ -#define ECO_RESERVE_1 -#define ECO_RESERVE_1_ADDRESS 0x2c -#define ECO_RESERVE_1_NUM 1 -#define ECO_RESERVE_1_INC 0x4 -#define ECO_RESERVE_1_TYPE REG_TYPE_RW -#define ECO_RESERVE_1_DEFAULT 0x0 - /*[field] ECO_RES_1*/ - #define ECO_RESERVE_1_ECO_RES_1 - #define ECO_RESERVE_1_ECO_RES_1_OFFSET 0 - #define ECO_RESERVE_1_ECO_RES_1_LEN 32 - #define ECO_RESERVE_1_ECO_RES_1_DEFAULT 0x0 - -struct eco_reserve_1 { - a_uint32_t eco_res_1:32; -}; - -union eco_reserve_1_u { - a_uint32_t val; - struct eco_reserve_1 bf; -}; - -/*[table] L0_FLOW_MAP_TBL*/ -#define L0_FLOW_MAP_TBL -#define L0_FLOW_MAP_TBL_ADDRESS 0x2000 -#define L0_FLOW_MAP_TBL_NUM 300 -#define L0_FLOW_MAP_TBL_INC 0x10 -#define L0_FLOW_MAP_TBL_TYPE REG_TYPE_RW -#define L0_FLOW_MAP_TBL_DEFAULT 0x0 - /*[field] SP_ID*/ - #define L0_FLOW_MAP_TBL_SP_ID - #define L0_FLOW_MAP_TBL_SP_ID_OFFSET 0 - #define L0_FLOW_MAP_TBL_SP_ID_LEN 6 - #define L0_FLOW_MAP_TBL_SP_ID_DEFAULT 0x0 - /*[field] C_PRI*/ - #define L0_FLOW_MAP_TBL_C_PRI - #define L0_FLOW_MAP_TBL_C_PRI_OFFSET 6 - #define L0_FLOW_MAP_TBL_C_PRI_LEN 3 - #define L0_FLOW_MAP_TBL_C_PRI_DEFAULT 0x0 - /*[field] E_PRI*/ - #define L0_FLOW_MAP_TBL_E_PRI - #define L0_FLOW_MAP_TBL_E_PRI_OFFSET 9 - #define L0_FLOW_MAP_TBL_E_PRI_LEN 3 - #define L0_FLOW_MAP_TBL_E_PRI_DEFAULT 0x0 - /*[field] C_DRR_WT*/ - #define L0_FLOW_MAP_TBL_C_DRR_WT - #define L0_FLOW_MAP_TBL_C_DRR_WT_OFFSET 12 - #define L0_FLOW_MAP_TBL_C_DRR_WT_LEN 10 - #define L0_FLOW_MAP_TBL_C_DRR_WT_DEFAULT 0x0 - /*[field] E_DRR_WT*/ - #define L0_FLOW_MAP_TBL_E_DRR_WT - #define L0_FLOW_MAP_TBL_E_DRR_WT_OFFSET 22 - #define L0_FLOW_MAP_TBL_E_DRR_WT_LEN 10 - #define L0_FLOW_MAP_TBL_E_DRR_WT_DEFAULT 0x0 - -struct l0_flow_map_tbl { - a_uint32_t sp_id:6; - a_uint32_t c_pri:3; - a_uint32_t e_pri:3; - a_uint32_t c_drr_wt:10; - a_uint32_t e_drr_wt:10; -}; - -union l0_flow_map_tbl_u { - a_uint32_t val; - struct l0_flow_map_tbl bf; -}; - -/*[table] L0_C_SP_CFG_TBL*/ -#define L0_C_SP_CFG_TBL -#define L0_C_SP_CFG_TBL_ADDRESS 0x4000 -#define L0_C_SP_CFG_TBL_NUM 512 -#define L0_C_SP_CFG_TBL_INC 0x10 -#define L0_C_SP_CFG_TBL_TYPE REG_TYPE_RW -#define L0_C_SP_CFG_TBL_DEFAULT 0x0 - /*[field] DRR_ID*/ - #define L0_C_SP_CFG_TBL_DRR_ID - #define L0_C_SP_CFG_TBL_DRR_ID_OFFSET 0 - #define L0_C_SP_CFG_TBL_DRR_ID_LEN 8 - #define L0_C_SP_CFG_TBL_DRR_ID_DEFAULT 0x0 - /*[field] DRR_CREDIT_UNIT*/ - #define L0_C_SP_CFG_TBL_DRR_CREDIT_UNIT - #define L0_C_SP_CFG_TBL_DRR_CREDIT_UNIT_OFFSET 8 - #define L0_C_SP_CFG_TBL_DRR_CREDIT_UNIT_LEN 1 - #define L0_C_SP_CFG_TBL_DRR_CREDIT_UNIT_DEFAULT 0x0 - -struct l0_c_sp_cfg_tbl { - a_uint32_t drr_id:8; - a_uint32_t drr_credit_unit:1; - a_uint32_t _reserved0:23; -}; - -union l0_c_sp_cfg_tbl_u { - a_uint32_t val; - struct l0_c_sp_cfg_tbl bf; -}; - -/*[table] L0_E_SP_CFG_TBL*/ -#define L0_E_SP_CFG_TBL -#define L0_E_SP_CFG_TBL_ADDRESS 0x6000 -#define L0_E_SP_CFG_TBL_NUM 512 -#define L0_E_SP_CFG_TBL_INC 0x10 -#define L0_E_SP_CFG_TBL_TYPE REG_TYPE_RW -#define L0_E_SP_CFG_TBL_DEFAULT 0x0 - /*[field] DRR_ID*/ - #define L0_E_SP_CFG_TBL_DRR_ID - #define L0_E_SP_CFG_TBL_DRR_ID_OFFSET 0 - #define L0_E_SP_CFG_TBL_DRR_ID_LEN 8 - #define L0_E_SP_CFG_TBL_DRR_ID_DEFAULT 0x0 - /*[field] DRR_CREDIT_UNIT*/ - #define L0_E_SP_CFG_TBL_DRR_CREDIT_UNIT - #define L0_E_SP_CFG_TBL_DRR_CREDIT_UNIT_OFFSET 8 - #define L0_E_SP_CFG_TBL_DRR_CREDIT_UNIT_LEN 1 - #define L0_E_SP_CFG_TBL_DRR_CREDIT_UNIT_DEFAULT 0x0 - -struct l0_e_sp_cfg_tbl { - a_uint32_t drr_id:8; - a_uint32_t drr_credit_unit:1; - a_uint32_t _reserved0:23; -}; - -union l0_e_sp_cfg_tbl_u { - a_uint32_t val; - struct l0_e_sp_cfg_tbl bf; -}; - -/*[table] L0_FLOW_PORT_MAP_TBL*/ -#define L0_FLOW_PORT_MAP_TBL -#define L0_FLOW_PORT_MAP_TBL_ADDRESS 0x8000 -#define L0_FLOW_PORT_MAP_TBL_NUM 300 -#define L0_FLOW_PORT_MAP_TBL_INC 0x10 -#define L0_FLOW_PORT_MAP_TBL_TYPE REG_TYPE_RW -#define L0_FLOW_PORT_MAP_TBL_DEFAULT 0x0 - /*[field] PORT_NUM*/ - #define L0_FLOW_PORT_MAP_TBL_PORT_NUM - #define L0_FLOW_PORT_MAP_TBL_PORT_NUM_OFFSET 0 - #define L0_FLOW_PORT_MAP_TBL_PORT_NUM_LEN 4 - #define L0_FLOW_PORT_MAP_TBL_PORT_NUM_DEFAULT 0x0 - -struct l0_flow_port_map_tbl { - a_uint32_t port_num:4; - a_uint32_t _reserved0:28; -}; - -union l0_flow_port_map_tbl_u { - a_uint32_t val; - struct l0_flow_port_map_tbl bf; -}; - -/*[table] L0_C_DRR_HEAD_TBL*/ -#define L0_C_DRR_HEAD_TBL -#define L0_C_DRR_HEAD_TBL_ADDRESS 0xa000 -#define L0_C_DRR_HEAD_TBL_NUM 160 -#define L0_C_DRR_HEAD_TBL_INC 0x10 -#define L0_C_DRR_HEAD_TBL_TYPE REG_TYPE_RO -#define L0_C_DRR_HEAD_TBL_DEFAULT 0x0 - /*[field] BACKUP_TAIL*/ - #define L0_C_DRR_HEAD_TBL_BACKUP_TAIL - #define L0_C_DRR_HEAD_TBL_BACKUP_TAIL_OFFSET 0 - #define L0_C_DRR_HEAD_TBL_BACKUP_TAIL_LEN 9 - #define L0_C_DRR_HEAD_TBL_BACKUP_TAIL_DEFAULT 0x0 - /*[field] BACKUP_HEAD*/ - #define L0_C_DRR_HEAD_TBL_BACKUP_HEAD - #define L0_C_DRR_HEAD_TBL_BACKUP_HEAD_OFFSET 9 - #define L0_C_DRR_HEAD_TBL_BACKUP_HEAD_LEN 9 - #define L0_C_DRR_HEAD_TBL_BACKUP_HEAD_DEFAULT 0x0 - /*[field] BACKUP_VLD*/ - #define L0_C_DRR_HEAD_TBL_BACKUP_VLD - #define L0_C_DRR_HEAD_TBL_BACKUP_VLD_OFFSET 18 - #define L0_C_DRR_HEAD_TBL_BACKUP_VLD_LEN 1 - #define L0_C_DRR_HEAD_TBL_BACKUP_VLD_DEFAULT 0x0 - /*[field] BACKUP_MAX_N*/ - #define L0_C_DRR_HEAD_TBL_BACKUP_MAX_N - #define L0_C_DRR_HEAD_TBL_BACKUP_MAX_N_OFFSET 19 - #define L0_C_DRR_HEAD_TBL_BACKUP_MAX_N_LEN 5 - #define L0_C_DRR_HEAD_TBL_BACKUP_MAX_N_DEFAULT 0x0 - /*[field] ACTIVE_TAIL*/ - #define L0_C_DRR_HEAD_TBL_ACTIVE_TAIL - #define L0_C_DRR_HEAD_TBL_ACTIVE_TAIL_OFFSET 24 - #define L0_C_DRR_HEAD_TBL_ACTIVE_TAIL_LEN 9 - #define L0_C_DRR_HEAD_TBL_ACTIVE_TAIL_DEFAULT 0x0 - /*[field] ACTIVE_HEAD*/ - #define L0_C_DRR_HEAD_TBL_ACTIVE_HEAD - #define L0_C_DRR_HEAD_TBL_ACTIVE_HEAD_OFFSET 33 - #define L0_C_DRR_HEAD_TBL_ACTIVE_HEAD_LEN 9 - #define L0_C_DRR_HEAD_TBL_ACTIVE_HEAD_DEFAULT 0x0 - /*[field] ACTIVE_VLD*/ - #define L0_C_DRR_HEAD_TBL_ACTIVE_VLD - #define L0_C_DRR_HEAD_TBL_ACTIVE_VLD_OFFSET 42 - #define L0_C_DRR_HEAD_TBL_ACTIVE_VLD_LEN 1 - #define L0_C_DRR_HEAD_TBL_ACTIVE_VLD_DEFAULT 0x0 - /*[field] ACTIVE_MAX_N*/ - #define L0_C_DRR_HEAD_TBL_ACTIVE_MAX_N - #define L0_C_DRR_HEAD_TBL_ACTIVE_MAX_N_OFFSET 43 - #define L0_C_DRR_HEAD_TBL_ACTIVE_MAX_N_LEN 5 - #define L0_C_DRR_HEAD_TBL_ACTIVE_MAX_N_DEFAULT 0x0 - -struct l0_c_drr_head_tbl { - a_uint32_t backup_tail:9; - a_uint32_t backup_head:9; - a_uint32_t backup_vld:1; - a_uint32_t backup_max_n:5; - a_uint32_t active_tail_0:8; - a_uint32_t active_tail_1:1; - a_uint32_t active_head:9; - a_uint32_t active_vld:1; - a_uint32_t active_max_n:5; - a_uint32_t _reserved0:16; -}; - -union l0_c_drr_head_tbl_u { - a_uint32_t val[2]; - struct l0_c_drr_head_tbl bf; -}; - -/*[table] L0_E_DRR_HEAD_TBL*/ -#define L0_E_DRR_HEAD_TBL -#define L0_E_DRR_HEAD_TBL_ADDRESS 0xc000 -#define L0_E_DRR_HEAD_TBL_NUM 160 -#define L0_E_DRR_HEAD_TBL_INC 0x10 -#define L0_E_DRR_HEAD_TBL_TYPE REG_TYPE_RO -#define L0_E_DRR_HEAD_TBL_DEFAULT 0x0 - /*[field] BACKUP_TAIL*/ - #define L0_E_DRR_HEAD_TBL_BACKUP_TAIL - #define L0_E_DRR_HEAD_TBL_BACKUP_TAIL_OFFSET 0 - #define L0_E_DRR_HEAD_TBL_BACKUP_TAIL_LEN 9 - #define L0_E_DRR_HEAD_TBL_BACKUP_TAIL_DEFAULT 0x0 - /*[field] BACKUP_HEAD*/ - #define L0_E_DRR_HEAD_TBL_BACKUP_HEAD - #define L0_E_DRR_HEAD_TBL_BACKUP_HEAD_OFFSET 9 - #define L0_E_DRR_HEAD_TBL_BACKUP_HEAD_LEN 9 - #define L0_E_DRR_HEAD_TBL_BACKUP_HEAD_DEFAULT 0x0 - /*[field] BACKUP_VLD*/ - #define L0_E_DRR_HEAD_TBL_BACKUP_VLD - #define L0_E_DRR_HEAD_TBL_BACKUP_VLD_OFFSET 18 - #define L0_E_DRR_HEAD_TBL_BACKUP_VLD_LEN 1 - #define L0_E_DRR_HEAD_TBL_BACKUP_VLD_DEFAULT 0x0 - /*[field] BACKUP_MAX_N*/ - #define L0_E_DRR_HEAD_TBL_BACKUP_MAX_N - #define L0_E_DRR_HEAD_TBL_BACKUP_MAX_N_OFFSET 19 - #define L0_E_DRR_HEAD_TBL_BACKUP_MAX_N_LEN 5 - #define L0_E_DRR_HEAD_TBL_BACKUP_MAX_N_DEFAULT 0x0 - /*[field] ACTIVE_TAIL*/ - #define L0_E_DRR_HEAD_TBL_ACTIVE_TAIL - #define L0_E_DRR_HEAD_TBL_ACTIVE_TAIL_OFFSET 24 - #define L0_E_DRR_HEAD_TBL_ACTIVE_TAIL_LEN 9 - #define L0_E_DRR_HEAD_TBL_ACTIVE_TAIL_DEFAULT 0x0 - /*[field] ACTIVE_HEAD*/ - #define L0_E_DRR_HEAD_TBL_ACTIVE_HEAD - #define L0_E_DRR_HEAD_TBL_ACTIVE_HEAD_OFFSET 33 - #define L0_E_DRR_HEAD_TBL_ACTIVE_HEAD_LEN 9 - #define L0_E_DRR_HEAD_TBL_ACTIVE_HEAD_DEFAULT 0x0 - /*[field] ACTIVE_VLD*/ - #define L0_E_DRR_HEAD_TBL_ACTIVE_VLD - #define L0_E_DRR_HEAD_TBL_ACTIVE_VLD_OFFSET 42 - #define L0_E_DRR_HEAD_TBL_ACTIVE_VLD_LEN 1 - #define L0_E_DRR_HEAD_TBL_ACTIVE_VLD_DEFAULT 0x0 - /*[field] ACTIVE_MAX_N*/ - #define L0_E_DRR_HEAD_TBL_ACTIVE_MAX_N - #define L0_E_DRR_HEAD_TBL_ACTIVE_MAX_N_OFFSET 43 - #define L0_E_DRR_HEAD_TBL_ACTIVE_MAX_N_LEN 5 - #define L0_E_DRR_HEAD_TBL_ACTIVE_MAX_N_DEFAULT 0x0 - -struct l0_e_drr_head_tbl { - a_uint32_t backup_tail:9; - a_uint32_t backup_head:9; - a_uint32_t backup_vld:1; - a_uint32_t backup_max_n:5; - a_uint32_t active_tail_0:8; - a_uint32_t active_tail_1:1; - a_uint32_t active_head:9; - a_uint32_t active_vld:1; - a_uint32_t active_max_n:5; - a_uint32_t _reserved0:16; -}; - -union l0_e_drr_head_tbl_u { - a_uint32_t val[2]; - struct l0_e_drr_head_tbl bf; -}; - -/*[table] L0_DRR_CREDIT_TBL*/ -#define L0_DRR_CREDIT_TBL -#define L0_DRR_CREDIT_TBL_ADDRESS 0xe000 -#define L0_DRR_CREDIT_TBL_NUM 300 -#define L0_DRR_CREDIT_TBL_INC 0x10 -#define L0_DRR_CREDIT_TBL_TYPE REG_TYPE_RO -#define L0_DRR_CREDIT_TBL_DEFAULT 0x0 - /*[field] C_DRR_CREDIT*/ - #define L0_DRR_CREDIT_TBL_C_DRR_CREDIT - #define L0_DRR_CREDIT_TBL_C_DRR_CREDIT_OFFSET 0 - #define L0_DRR_CREDIT_TBL_C_DRR_CREDIT_LEN 24 - #define L0_DRR_CREDIT_TBL_C_DRR_CREDIT_DEFAULT 0x0 - /*[field] C_DRR_CREDIT_NEG*/ - #define L0_DRR_CREDIT_TBL_C_DRR_CREDIT_NEG - #define L0_DRR_CREDIT_TBL_C_DRR_CREDIT_NEG_OFFSET 24 - #define L0_DRR_CREDIT_TBL_C_DRR_CREDIT_NEG_LEN 1 - #define L0_DRR_CREDIT_TBL_C_DRR_CREDIT_NEG_DEFAULT 0x0 - /*[field] E_DRR_CREDIT*/ - #define L0_DRR_CREDIT_TBL_E_DRR_CREDIT - #define L0_DRR_CREDIT_TBL_E_DRR_CREDIT_OFFSET 25 - #define L0_DRR_CREDIT_TBL_E_DRR_CREDIT_LEN 24 - #define L0_DRR_CREDIT_TBL_E_DRR_CREDIT_DEFAULT 0x0 - /*[field] E_DRR_CREDIT_NEG*/ - #define L0_DRR_CREDIT_TBL_E_DRR_CREDIT_NEG - #define L0_DRR_CREDIT_TBL_E_DRR_CREDIT_NEG_OFFSET 49 - #define L0_DRR_CREDIT_TBL_E_DRR_CREDIT_NEG_LEN 1 - #define L0_DRR_CREDIT_TBL_E_DRR_CREDIT_NEG_DEFAULT 0x0 - -struct l0_drr_credit_tbl { - a_uint32_t c_drr_credit:24; - a_uint32_t c_drr_credit_neg:1; - a_uint32_t e_drr_credit_0:7; - a_uint32_t e_drr_credit_1:17; - a_uint32_t e_drr_credit_neg:1; - a_uint32_t _reserved0:14; -}; - -union l0_drr_credit_tbl_u { - a_uint32_t val[2]; - struct l0_drr_credit_tbl bf; -}; - -/*[table] L0_C_DRR_LL_TBL*/ -#define L0_C_DRR_LL_TBL -#define L0_C_DRR_LL_TBL_ADDRESS 0x10000 -#define L0_C_DRR_LL_TBL_NUM 300 -#define L0_C_DRR_LL_TBL_INC 0x10 -#define L0_C_DRR_LL_TBL_TYPE REG_TYPE_RO -#define L0_C_DRR_LL_TBL_DEFAULT 0x0 - /*[field] NEXT_PTR*/ - #define L0_C_DRR_LL_TBL_NEXT_PTR - #define L0_C_DRR_LL_TBL_NEXT_PTR_OFFSET 0 - #define L0_C_DRR_LL_TBL_NEXT_PTR_LEN 9 - #define L0_C_DRR_LL_TBL_NEXT_PTR_DEFAULT 0x0 - -struct l0_c_drr_ll_tbl { - a_uint32_t next_ptr:9; - a_uint32_t _reserved0:23; -}; - -union l0_c_drr_ll_tbl_u { - a_uint32_t val; - struct l0_c_drr_ll_tbl bf; -}; - -/*[table] L0_C_DRR_REVERSE_LL_TBL*/ -#define L0_C_DRR_REVERSE_LL_TBL -#define L0_C_DRR_REVERSE_LL_TBL_ADDRESS 0x12000 -#define L0_C_DRR_REVERSE_LL_TBL_NUM 300 -#define L0_C_DRR_REVERSE_LL_TBL_INC 0x10 -#define L0_C_DRR_REVERSE_LL_TBL_TYPE REG_TYPE_RO -#define L0_C_DRR_REVERSE_LL_TBL_DEFAULT 0x0 - /*[field] PRE_PTR*/ - #define L0_C_DRR_REVERSE_LL_TBL_PRE_PTR - #define L0_C_DRR_REVERSE_LL_TBL_PRE_PTR_OFFSET 0 - #define L0_C_DRR_REVERSE_LL_TBL_PRE_PTR_LEN 9 - #define L0_C_DRR_REVERSE_LL_TBL_PRE_PTR_DEFAULT 0x0 - -struct l0_c_drr_reverse_ll_tbl { - a_uint32_t pre_ptr:9; - a_uint32_t _reserved0:23; -}; - -union l0_c_drr_reverse_ll_tbl_u { - a_uint32_t val; - struct l0_c_drr_reverse_ll_tbl bf; -}; - -/*[table] L0_E_DRR_LL_TBL*/ -#define L0_E_DRR_LL_TBL -#define L0_E_DRR_LL_TBL_ADDRESS 0x14000 -#define L0_E_DRR_LL_TBL_NUM 300 -#define L0_E_DRR_LL_TBL_INC 0x10 -#define L0_E_DRR_LL_TBL_TYPE REG_TYPE_RO -#define L0_E_DRR_LL_TBL_DEFAULT 0x0 - /*[field] NEXT_PTR*/ - #define L0_E_DRR_LL_TBL_NEXT_PTR - #define L0_E_DRR_LL_TBL_NEXT_PTR_OFFSET 0 - #define L0_E_DRR_LL_TBL_NEXT_PTR_LEN 9 - #define L0_E_DRR_LL_TBL_NEXT_PTR_DEFAULT 0x0 - -struct l0_e_drr_ll_tbl { - a_uint32_t next_ptr:9; - a_uint32_t _reserved0:23; -}; - -union l0_e_drr_ll_tbl_u { - a_uint32_t val; - struct l0_e_drr_ll_tbl bf; -}; - -/*[table] L0_E_DRR_REVERSE_LL_TBL*/ -#define L0_E_DRR_REVERSE_LL_TBL -#define L0_E_DRR_REVERSE_LL_TBL_ADDRESS 0x16000 -#define L0_E_DRR_REVERSE_LL_TBL_NUM 300 -#define L0_E_DRR_REVERSE_LL_TBL_INC 0x10 -#define L0_E_DRR_REVERSE_LL_TBL_TYPE REG_TYPE_RO -#define L0_E_DRR_REVERSE_LL_TBL_DEFAULT 0x0 - /*[field] PRE_PTR*/ - #define L0_E_DRR_REVERSE_LL_TBL_PRE_PTR - #define L0_E_DRR_REVERSE_LL_TBL_PRE_PTR_OFFSET 0 - #define L0_E_DRR_REVERSE_LL_TBL_PRE_PTR_LEN 9 - #define L0_E_DRR_REVERSE_LL_TBL_PRE_PTR_DEFAULT 0x0 - -struct l0_e_drr_reverse_ll_tbl { - a_uint32_t pre_ptr:9; - a_uint32_t _reserved0:23; -}; - -union l0_e_drr_reverse_ll_tbl_u { - a_uint32_t val; - struct l0_e_drr_reverse_ll_tbl bf; -}; - -/*[table] L0_SP_ENTRY_TBL*/ -#define L0_SP_ENTRY_TBL -#define L0_SP_ENTRY_TBL_ADDRESS 0x18000 -#define L0_SP_ENTRY_TBL_NUM 64 -#define L0_SP_ENTRY_TBL_INC 0x20 -#define L0_SP_ENTRY_TBL_TYPE REG_TYPE_RO -#define L0_SP_ENTRY_TBL_DEFAULT 0x0 - /*[field] ENTRY_PATH_ID*/ - #define L0_SP_ENTRY_TBL_ENTRY_PATH_ID - #define L0_SP_ENTRY_TBL_ENTRY_PATH_ID_OFFSET 0 - #define L0_SP_ENTRY_TBL_ENTRY_PATH_ID_LEN 144 - #define L0_SP_ENTRY_TBL_ENTRY_PATH_ID_DEFAULT 0x0 - /*[field] ENTRY_VLD*/ - #define L0_SP_ENTRY_TBL_ENTRY_VLD - #define L0_SP_ENTRY_TBL_ENTRY_VLD_OFFSET 144 - #define L0_SP_ENTRY_TBL_ENTRY_VLD_LEN 16 - #define L0_SP_ENTRY_TBL_ENTRY_VLD_DEFAULT 0x0 - -struct l0_sp_entry_tbl { - a_uint32_t entry_path_id_0:32; - a_uint32_t entry_path_id_1:32; - a_uint32_t entry_path_id_2:32; - a_uint32_t entry_path_id_3:32; - a_uint32_t entry_path_id_4:16; - a_uint32_t entry_vld:16; -}; - -union l0_sp_entry_tbl_u { - a_uint32_t val[5]; - struct l0_sp_entry_tbl bf; -}; - - -/*[table] L0_ENS_Q_LL_TBL*/ -#define L0_ENS_Q_LL_TBL -#define L0_ENS_Q_LL_TBL_ADDRESS 0x1e000 -#define L0_ENS_Q_LL_TBL_NUM 300 -#define L0_ENS_Q_LL_TBL_INC 0x10 -#define L0_ENS_Q_LL_TBL_TYPE REG_TYPE_RO -#define L0_ENS_Q_LL_TBL_DEFAULT 0x0 - /*[field] NEXT_PTR*/ - #define L0_ENS_Q_LL_TBL_NEXT_PTR - #define L0_ENS_Q_LL_TBL_NEXT_PTR_OFFSET 0 - #define L0_ENS_Q_LL_TBL_NEXT_PTR_LEN 9 - #define L0_ENS_Q_LL_TBL_NEXT_PTR_DEFAULT 0x0 - -struct l0_ens_q_ll_tbl { - a_uint32_t next_ptr:9; - a_uint32_t _reserved0:23; -}; - -union l0_ens_q_ll_tbl_u { - a_uint32_t val; - struct l0_ens_q_ll_tbl bf; -}; - -/*[table] L0_ENS_Q_HEAD_TBL*/ -#define L0_ENS_Q_HEAD_TBL -#define L0_ENS_Q_HEAD_TBL_ADDRESS 0x20000 -#define L0_ENS_Q_HEAD_TBL_NUM 8 -#define L0_ENS_Q_HEAD_TBL_INC 0x10 -#define L0_ENS_Q_HEAD_TBL_TYPE REG_TYPE_RO -#define L0_ENS_Q_HEAD_TBL_DEFAULT 0x0 - /*[field] TAIL*/ - #define L0_ENS_Q_HEAD_TBL_TAIL - #define L0_ENS_Q_HEAD_TBL_TAIL_OFFSET 0 - #define L0_ENS_Q_HEAD_TBL_TAIL_LEN 9 - #define L0_ENS_Q_HEAD_TBL_TAIL_DEFAULT 0x0 - /*[field] HEAD*/ - #define L0_ENS_Q_HEAD_TBL_HEAD - #define L0_ENS_Q_HEAD_TBL_HEAD_OFFSET 9 - #define L0_ENS_Q_HEAD_TBL_HEAD_LEN 9 - #define L0_ENS_Q_HEAD_TBL_HEAD_DEFAULT 0x0 - /*[field] VLD*/ - #define L0_ENS_Q_HEAD_TBL_VLD - #define L0_ENS_Q_HEAD_TBL_VLD_OFFSET 18 - #define L0_ENS_Q_HEAD_TBL_VLD_LEN 1 - #define L0_ENS_Q_HEAD_TBL_VLD_DEFAULT 0x0 - -struct l0_ens_q_head_tbl { - a_uint32_t tail:9; - a_uint32_t head:9; - a_uint32_t vld:1; - a_uint32_t _reserved0:13; -}; - -union l0_ens_q_head_tbl_u { - a_uint32_t val; - struct l0_ens_q_head_tbl bf; -}; - -/*[table] L0_ENS_Q_ENTRY_TBL*/ -#define L0_ENS_Q_ENTRY_TBL -#define L0_ENS_Q_ENTRY_TBL_ADDRESS 0x22000 -#define L0_ENS_Q_ENTRY_TBL_NUM 300 -#define L0_ENS_Q_ENTRY_TBL_INC 0x10 -#define L0_ENS_Q_ENTRY_TBL_TYPE REG_TYPE_RO -#define L0_ENS_Q_ENTRY_TBL_DEFAULT 0x0 - /*[field] ENTRY_ENS_TYPE*/ - #define L0_ENS_Q_ENTRY_TBL_ENTRY_ENS_TYPE - #define L0_ENS_Q_ENTRY_TBL_ENTRY_ENS_TYPE_OFFSET 0 - #define L0_ENS_Q_ENTRY_TBL_ENTRY_ENS_TYPE_LEN 2 - #define L0_ENS_Q_ENTRY_TBL_ENTRY_ENS_TYPE_DEFAULT 0x0 - /*[field] ENTRY_ENS_VLD*/ - #define L0_ENS_Q_ENTRY_TBL_ENTRY_ENS_VLD - #define L0_ENS_Q_ENTRY_TBL_ENTRY_ENS_VLD_OFFSET 2 - #define L0_ENS_Q_ENTRY_TBL_ENTRY_ENS_VLD_LEN 1 - #define L0_ENS_Q_ENTRY_TBL_ENTRY_ENS_VLD_DEFAULT 0x0 - /*[field] ENTRY_ENS_IN_Q*/ - #define L0_ENS_Q_ENTRY_TBL_ENTRY_ENS_IN_Q - #define L0_ENS_Q_ENTRY_TBL_ENTRY_ENS_IN_Q_OFFSET 3 - #define L0_ENS_Q_ENTRY_TBL_ENTRY_ENS_IN_Q_LEN 1 - #define L0_ENS_Q_ENTRY_TBL_ENTRY_ENS_IN_Q_DEFAULT 0x0 - -struct l0_ens_q_entry_tbl { - a_uint32_t entry_ens_type:2; - a_uint32_t entry_ens_vld:1; - a_uint32_t entry_ens_in_q:1; - a_uint32_t _reserved0:28; -}; - -union l0_ens_q_entry_tbl_u { - a_uint32_t val; - struct l0_ens_q_entry_tbl bf; -}; - -/*[table] L0_FLOW_STATUS_TBL*/ -#define L0_FLOW_STATUS_TBL -#define L0_FLOW_STATUS_TBL_ADDRESS 0x24000 -#define L0_FLOW_STATUS_TBL_NUM 300 -#define L0_FLOW_STATUS_TBL_INC 0x10 -#define L0_FLOW_STATUS_TBL_TYPE REG_TYPE_RO -#define L0_FLOW_STATUS_TBL_DEFAULT 0x0 - /*[field] EN_LEVEL*/ - #define L0_FLOW_STATUS_TBL_EN_LEVEL - #define L0_FLOW_STATUS_TBL_EN_LEVEL_OFFSET 0 - #define L0_FLOW_STATUS_TBL_EN_LEVEL_LEN 1 - #define L0_FLOW_STATUS_TBL_EN_LEVEL_DEFAULT 0x0 - /*[field] EN_CDRR*/ - #define L0_FLOW_STATUS_TBL_EN_CDRR - #define L0_FLOW_STATUS_TBL_EN_CDRR_OFFSET 1 - #define L0_FLOW_STATUS_TBL_EN_CDRR_LEN 1 - #define L0_FLOW_STATUS_TBL_EN_CDRR_DEFAULT 0x0 - /*[field] EN_EDRR*/ - #define L0_FLOW_STATUS_TBL_EN_EDRR - #define L0_FLOW_STATUS_TBL_EN_EDRR_OFFSET 2 - #define L0_FLOW_STATUS_TBL_EN_EDRR_LEN 1 - #define L0_FLOW_STATUS_TBL_EN_EDRR_DEFAULT 0x0 - -struct l0_flow_status_tbl { - a_uint32_t en_level:1; - a_uint32_t en_cdrr:1; - a_uint32_t en_edrr:1; - a_uint32_t _reserved0:29; -}; - -union l0_flow_status_tbl_u { - a_uint32_t val; - struct l0_flow_status_tbl bf; -}; - - -/*[table] RING_Q_MAP_TBL*/ -#define RING_Q_MAP_TBL -#define RING_Q_MAP_TBL_ADDRESS 0x2a000 -#define RING_Q_MAP_TBL_NUM 16 -#define RING_Q_MAP_TBL_INC 0x40 -#define RING_Q_MAP_TBL_TYPE REG_TYPE_RW -#define RING_Q_MAP_TBL_DEFAULT 0x0 - /*[field] QUEUE_BITMAP*/ - #define RING_Q_MAP_TBL_QUEUE_BITMAP - #define RING_Q_MAP_TBL_QUEUE_BITMAP_OFFSET 0 - #define RING_Q_MAP_TBL_QUEUE_BITMAP_LEN 300 - #define RING_Q_MAP_TBL_QUEUE_BITMAP_DEFAULT 0x0 - -struct ring_q_map_tbl { - a_uint32_t queue_bitmap_0:32; - a_uint32_t queue_bitmap_1:32; - a_uint32_t queue_bitmap_2:32; - a_uint32_t queue_bitmap_3:32; - a_uint32_t queue_bitmap_4:32; - a_uint32_t queue_bitmap_5:32; - a_uint32_t queue_bitmap_6:32; - a_uint32_t queue_bitmap_7:32; - a_uint32_t queue_bitmap_8:32; - a_uint32_t queue_bitmap_9:12; - a_uint32_t _reserved0:20; -}; - -union ring_q_map_tbl_u { - a_uint32_t val[10]; - struct ring_q_map_tbl bf; -}; - -/*[table] RFC_BLOCK_TBL*/ -#define RFC_BLOCK_TBL -#define RFC_BLOCK_TBL_ADDRESS 0x2c000 -#define RFC_BLOCK_TBL_NUM 300 -#define RFC_BLOCK_TBL_INC 0x10 -#define RFC_BLOCK_TBL_TYPE REG_TYPE_RO -#define RFC_BLOCK_TBL_DEFAULT 0x0 - /*[field] RFC_BLOCK*/ - #define RFC_BLOCK_TBL_RFC_BLOCK - #define RFC_BLOCK_TBL_RFC_BLOCK_OFFSET 0 - #define RFC_BLOCK_TBL_RFC_BLOCK_LEN 1 - #define RFC_BLOCK_TBL_RFC_BLOCK_DEFAULT 0x0 - -struct rfc_block_tbl { - a_uint32_t rfc_block:1; - a_uint32_t _reserved0:31; -}; - -union rfc_block_tbl_u { - a_uint32_t val; - struct rfc_block_tbl bf; -}; - -/*[table] RFC_STATUS_TBL*/ -#define RFC_STATUS_TBL -#define RFC_STATUS_TBL_ADDRESS 0x2e000 -#define RFC_STATUS_TBL_NUM 300 -#define RFC_STATUS_TBL_INC 0x10 -#define RFC_STATUS_TBL_TYPE REG_TYPE_RO -#define RFC_STATUS_TBL_DEFAULT 0x0 - /*[field] RFC_STATUS*/ - #define RFC_STATUS_TBL_RFC_STATUS - #define RFC_STATUS_TBL_RFC_STATUS_OFFSET 0 - #define RFC_STATUS_TBL_RFC_STATUS_LEN 1 - #define RFC_STATUS_TBL_RFC_STATUS_DEFAULT 0x0 - -struct rfc_status_tbl { - a_uint32_t rfc_status:1; - a_uint32_t _reserved0:31; -}; - -union rfc_status_tbl_u { - a_uint32_t val; - struct rfc_status_tbl bf; -}; - -/*[table] DEQ_DIS_TBL*/ -#define DEQ_DIS_TBL -#define DEQ_DIS_TBL_ADDRESS 0x30000 -#define DEQ_DIS_TBL_NUM 300 -#define DEQ_DIS_TBL_INC 0x10 -#define DEQ_DIS_TBL_TYPE REG_TYPE_RW -#define DEQ_DIS_TBL_DEFAULT 0x0 - /*[field] DEQ_DIS*/ - #define DEQ_DIS_TBL_DEQ_DIS - #define DEQ_DIS_TBL_DEQ_DIS_OFFSET 0 - #define DEQ_DIS_TBL_DEQ_DIS_LEN 1 - #define DEQ_DIS_TBL_DEQ_DIS_DEFAULT 0x0 - -struct deq_dis_tbl { - a_uint32_t deq_dis:1; - a_uint32_t _reserved0:31; -}; - -union deq_dis_tbl_u { - a_uint32_t val; - struct deq_dis_tbl bf; -}; - -/*[table] L1_FLOW_MAP_TBL*/ -#define L1_FLOW_MAP_TBL -#define L1_FLOW_MAP_TBL_ADDRESS 0x40000 -#define L1_FLOW_MAP_TBL_NUM 64 -#define L1_FLOW_MAP_TBL_INC 0x10 -#define L1_FLOW_MAP_TBL_TYPE REG_TYPE_RW -#define L1_FLOW_MAP_TBL_DEFAULT 0x0 - /*[field] SP_ID*/ - #define L1_FLOW_MAP_TBL_SP_ID - #define L1_FLOW_MAP_TBL_SP_ID_OFFSET 0 - #define L1_FLOW_MAP_TBL_SP_ID_LEN 4 - #define L1_FLOW_MAP_TBL_SP_ID_DEFAULT 0x0 - /*[field] C_PRI*/ - #define L1_FLOW_MAP_TBL_C_PRI - #define L1_FLOW_MAP_TBL_C_PRI_OFFSET 4 - #define L1_FLOW_MAP_TBL_C_PRI_LEN 3 - #define L1_FLOW_MAP_TBL_C_PRI_DEFAULT 0x0 - /*[field] E_PRI*/ - #define L1_FLOW_MAP_TBL_E_PRI - #define L1_FLOW_MAP_TBL_E_PRI_OFFSET 7 - #define L1_FLOW_MAP_TBL_E_PRI_LEN 3 - #define L1_FLOW_MAP_TBL_E_PRI_DEFAULT 0x0 - /*[field] C_DRR_WT*/ - #define L1_FLOW_MAP_TBL_C_DRR_WT - #define L1_FLOW_MAP_TBL_C_DRR_WT_OFFSET 10 - #define L1_FLOW_MAP_TBL_C_DRR_WT_LEN 10 - #define L1_FLOW_MAP_TBL_C_DRR_WT_DEFAULT 0x0 - /*[field] E_DRR_WT*/ - #define L1_FLOW_MAP_TBL_E_DRR_WT - #define L1_FLOW_MAP_TBL_E_DRR_WT_OFFSET 20 - #define L1_FLOW_MAP_TBL_E_DRR_WT_LEN 10 - #define L1_FLOW_MAP_TBL_E_DRR_WT_DEFAULT 0x0 - -struct l1_flow_map_tbl { - a_uint32_t sp_id:4; - a_uint32_t c_pri:3; - a_uint32_t e_pri:3; - a_uint32_t c_drr_wt:10; - a_uint32_t e_drr_wt:10; - a_uint32_t _reserved0:2; -}; - -union l1_flow_map_tbl_u { - a_uint32_t val; - struct l1_flow_map_tbl bf; -}; - -/*[table] L1_C_SP_CFG_TBL*/ -#define L1_C_SP_CFG_TBL -#define L1_C_SP_CFG_TBL_ADDRESS 0x42000 -#define L1_C_SP_CFG_TBL_NUM 64 -#define L1_C_SP_CFG_TBL_INC 0x10 -#define L1_C_SP_CFG_TBL_TYPE REG_TYPE_RW -#define L1_C_SP_CFG_TBL_DEFAULT 0x0 - /*[field] DRR_ID*/ - #define L1_C_SP_CFG_TBL_DRR_ID - #define L1_C_SP_CFG_TBL_DRR_ID_OFFSET 0 - #define L1_C_SP_CFG_TBL_DRR_ID_LEN 6 - #define L1_C_SP_CFG_TBL_DRR_ID_DEFAULT 0x0 - /*[field] DRR_CREDIT_UNIT*/ - #define L1_C_SP_CFG_TBL_DRR_CREDIT_UNIT - #define L1_C_SP_CFG_TBL_DRR_CREDIT_UNIT_OFFSET 6 - #define L1_C_SP_CFG_TBL_DRR_CREDIT_UNIT_LEN 1 - #define L1_C_SP_CFG_TBL_DRR_CREDIT_UNIT_DEFAULT 0x0 - -struct l1_c_sp_cfg_tbl { - a_uint32_t drr_id:6; - a_uint32_t drr_credit_unit:1; - a_uint32_t _reserved0:25; -}; - -union l1_c_sp_cfg_tbl_u { - a_uint32_t val; - struct l1_c_sp_cfg_tbl bf; -}; - -/*[table] L1_E_SP_CFG_TBL*/ -#define L1_E_SP_CFG_TBL -#define L1_E_SP_CFG_TBL_ADDRESS 0x44000 -#define L1_E_SP_CFG_TBL_NUM 64 -#define L1_E_SP_CFG_TBL_INC 0x10 -#define L1_E_SP_CFG_TBL_TYPE REG_TYPE_RW -#define L1_E_SP_CFG_TBL_DEFAULT 0x0 - /*[field] DRR_ID*/ - #define L1_E_SP_CFG_TBL_DRR_ID - #define L1_E_SP_CFG_TBL_DRR_ID_OFFSET 0 - #define L1_E_SP_CFG_TBL_DRR_ID_LEN 6 - #define L1_E_SP_CFG_TBL_DRR_ID_DEFAULT 0x0 - /*[field] DRR_CREDIT_UNIT*/ - #define L1_E_SP_CFG_TBL_DRR_CREDIT_UNIT - #define L1_E_SP_CFG_TBL_DRR_CREDIT_UNIT_OFFSET 6 - #define L1_E_SP_CFG_TBL_DRR_CREDIT_UNIT_LEN 1 - #define L1_E_SP_CFG_TBL_DRR_CREDIT_UNIT_DEFAULT 0x0 - -struct l1_e_sp_cfg_tbl { - a_uint32_t drr_id:6; - a_uint32_t drr_credit_unit:1; - a_uint32_t _reserved0:25; -}; - -union l1_e_sp_cfg_tbl_u { - a_uint32_t val; - struct l1_e_sp_cfg_tbl bf; -}; - -/*[table] L1_FLOW_PORT_MAP_TBL*/ -#define L1_FLOW_PORT_MAP_TBL -#define L1_FLOW_PORT_MAP_TBL_ADDRESS 0x46000 -#define L1_FLOW_PORT_MAP_TBL_NUM 64 -#define L1_FLOW_PORT_MAP_TBL_INC 0x10 -#define L1_FLOW_PORT_MAP_TBL_TYPE REG_TYPE_RW -#define L1_FLOW_PORT_MAP_TBL_DEFAULT 0x0 - /*[field] PORT_NUM*/ - #define L1_FLOW_PORT_MAP_TBL_PORT_NUM - #define L1_FLOW_PORT_MAP_TBL_PORT_NUM_OFFSET 0 - #define L1_FLOW_PORT_MAP_TBL_PORT_NUM_LEN 4 - #define L1_FLOW_PORT_MAP_TBL_PORT_NUM_DEFAULT 0x0 - -struct l1_flow_port_map_tbl { - a_uint32_t port_num:4; - a_uint32_t _reserved0:28; -}; - -union l1_flow_port_map_tbl_u { - a_uint32_t val; - struct l1_flow_port_map_tbl bf; -}; - -/*[table] L1_C_DRR_HEAD_TBL*/ -#define L1_C_DRR_HEAD_TBL -#define L1_C_DRR_HEAD_TBL_ADDRESS 0x48000 -#define L1_C_DRR_HEAD_TBL_NUM 36 -#define L1_C_DRR_HEAD_TBL_INC 0x10 -#define L1_C_DRR_HEAD_TBL_TYPE REG_TYPE_RO -#define L1_C_DRR_HEAD_TBL_DEFAULT 0x0 - /*[field] BACKUP_TAIL*/ - #define L1_C_DRR_HEAD_TBL_BACKUP_TAIL - #define L1_C_DRR_HEAD_TBL_BACKUP_TAIL_OFFSET 0 - #define L1_C_DRR_HEAD_TBL_BACKUP_TAIL_LEN 6 - #define L1_C_DRR_HEAD_TBL_BACKUP_TAIL_DEFAULT 0x0 - /*[field] BACKUP_HEAD*/ - #define L1_C_DRR_HEAD_TBL_BACKUP_HEAD - #define L1_C_DRR_HEAD_TBL_BACKUP_HEAD_OFFSET 6 - #define L1_C_DRR_HEAD_TBL_BACKUP_HEAD_LEN 6 - #define L1_C_DRR_HEAD_TBL_BACKUP_HEAD_DEFAULT 0x0 - /*[field] BACKUP_VLD*/ - #define L1_C_DRR_HEAD_TBL_BACKUP_VLD - #define L1_C_DRR_HEAD_TBL_BACKUP_VLD_OFFSET 12 - #define L1_C_DRR_HEAD_TBL_BACKUP_VLD_LEN 1 - #define L1_C_DRR_HEAD_TBL_BACKUP_VLD_DEFAULT 0x0 - /*[field] BACKUP_MAX_N*/ - #define L1_C_DRR_HEAD_TBL_BACKUP_MAX_N - #define L1_C_DRR_HEAD_TBL_BACKUP_MAX_N_OFFSET 13 - #define L1_C_DRR_HEAD_TBL_BACKUP_MAX_N_LEN 5 - #define L1_C_DRR_HEAD_TBL_BACKUP_MAX_N_DEFAULT 0x0 - /*[field] ACTIVE_TAIL*/ - #define L1_C_DRR_HEAD_TBL_ACTIVE_TAIL - #define L1_C_DRR_HEAD_TBL_ACTIVE_TAIL_OFFSET 18 - #define L1_C_DRR_HEAD_TBL_ACTIVE_TAIL_LEN 6 - #define L1_C_DRR_HEAD_TBL_ACTIVE_TAIL_DEFAULT 0x0 - /*[field] ACTIVE_HEAD*/ - #define L1_C_DRR_HEAD_TBL_ACTIVE_HEAD - #define L1_C_DRR_HEAD_TBL_ACTIVE_HEAD_OFFSET 24 - #define L1_C_DRR_HEAD_TBL_ACTIVE_HEAD_LEN 6 - #define L1_C_DRR_HEAD_TBL_ACTIVE_HEAD_DEFAULT 0x0 - /*[field] ACTIVE_VLD*/ - #define L1_C_DRR_HEAD_TBL_ACTIVE_VLD - #define L1_C_DRR_HEAD_TBL_ACTIVE_VLD_OFFSET 30 - #define L1_C_DRR_HEAD_TBL_ACTIVE_VLD_LEN 1 - #define L1_C_DRR_HEAD_TBL_ACTIVE_VLD_DEFAULT 0x0 - /*[field] ACTIVE_MAX_N*/ - #define L1_C_DRR_HEAD_TBL_ACTIVE_MAX_N - #define L1_C_DRR_HEAD_TBL_ACTIVE_MAX_N_OFFSET 31 - #define L1_C_DRR_HEAD_TBL_ACTIVE_MAX_N_LEN 5 - #define L1_C_DRR_HEAD_TBL_ACTIVE_MAX_N_DEFAULT 0x0 - -struct l1_c_drr_head_tbl { - a_uint32_t backup_tail:6; - a_uint32_t backup_head:6; - a_uint32_t backup_vld:1; - a_uint32_t backup_max_n:5; - a_uint32_t active_tail:6; - a_uint32_t active_head:6; - a_uint32_t active_vld:1; - a_uint32_t active_max_n_0:1; - a_uint32_t active_max_n_1:4; - a_uint32_t _reserved0:28; -}; - -union l1_c_drr_head_tbl_u { - a_uint32_t val[2]; - struct l1_c_drr_head_tbl bf; -}; - -/*[table] L1_E_DRR_HEAD_TBL*/ -#define L1_E_DRR_HEAD_TBL -#define L1_E_DRR_HEAD_TBL_ADDRESS 0x4a000 -#define L1_E_DRR_HEAD_TBL_NUM 36 -#define L1_E_DRR_HEAD_TBL_INC 0x10 -#define L1_E_DRR_HEAD_TBL_TYPE REG_TYPE_RO -#define L1_E_DRR_HEAD_TBL_DEFAULT 0x0 - /*[field] BACKUP_TAIL*/ - #define L1_E_DRR_HEAD_TBL_BACKUP_TAIL - #define L1_E_DRR_HEAD_TBL_BACKUP_TAIL_OFFSET 0 - #define L1_E_DRR_HEAD_TBL_BACKUP_TAIL_LEN 6 - #define L1_E_DRR_HEAD_TBL_BACKUP_TAIL_DEFAULT 0x0 - /*[field] BACKUP_HEAD*/ - #define L1_E_DRR_HEAD_TBL_BACKUP_HEAD - #define L1_E_DRR_HEAD_TBL_BACKUP_HEAD_OFFSET 6 - #define L1_E_DRR_HEAD_TBL_BACKUP_HEAD_LEN 6 - #define L1_E_DRR_HEAD_TBL_BACKUP_HEAD_DEFAULT 0x0 - /*[field] BACKUP_VLD*/ - #define L1_E_DRR_HEAD_TBL_BACKUP_VLD - #define L1_E_DRR_HEAD_TBL_BACKUP_VLD_OFFSET 12 - #define L1_E_DRR_HEAD_TBL_BACKUP_VLD_LEN 1 - #define L1_E_DRR_HEAD_TBL_BACKUP_VLD_DEFAULT 0x0 - /*[field] BACKUP_MAX_N*/ - #define L1_E_DRR_HEAD_TBL_BACKUP_MAX_N - #define L1_E_DRR_HEAD_TBL_BACKUP_MAX_N_OFFSET 13 - #define L1_E_DRR_HEAD_TBL_BACKUP_MAX_N_LEN 5 - #define L1_E_DRR_HEAD_TBL_BACKUP_MAX_N_DEFAULT 0x0 - /*[field] ACTIVE_TAIL*/ - #define L1_E_DRR_HEAD_TBL_ACTIVE_TAIL - #define L1_E_DRR_HEAD_TBL_ACTIVE_TAIL_OFFSET 18 - #define L1_E_DRR_HEAD_TBL_ACTIVE_TAIL_LEN 6 - #define L1_E_DRR_HEAD_TBL_ACTIVE_TAIL_DEFAULT 0x0 - /*[field] ACTIVE_HEAD*/ - #define L1_E_DRR_HEAD_TBL_ACTIVE_HEAD - #define L1_E_DRR_HEAD_TBL_ACTIVE_HEAD_OFFSET 24 - #define L1_E_DRR_HEAD_TBL_ACTIVE_HEAD_LEN 6 - #define L1_E_DRR_HEAD_TBL_ACTIVE_HEAD_DEFAULT 0x0 - /*[field] ACTIVE_VLD*/ - #define L1_E_DRR_HEAD_TBL_ACTIVE_VLD - #define L1_E_DRR_HEAD_TBL_ACTIVE_VLD_OFFSET 30 - #define L1_E_DRR_HEAD_TBL_ACTIVE_VLD_LEN 1 - #define L1_E_DRR_HEAD_TBL_ACTIVE_VLD_DEFAULT 0x0 - /*[field] ACTIVE_MAX_N*/ - #define L1_E_DRR_HEAD_TBL_ACTIVE_MAX_N - #define L1_E_DRR_HEAD_TBL_ACTIVE_MAX_N_OFFSET 31 - #define L1_E_DRR_HEAD_TBL_ACTIVE_MAX_N_LEN 5 - #define L1_E_DRR_HEAD_TBL_ACTIVE_MAX_N_DEFAULT 0x0 - -struct l1_e_drr_head_tbl { - a_uint32_t backup_tail:6; - a_uint32_t backup_head:6; - a_uint32_t backup_vld:1; - a_uint32_t backup_max_n:5; - a_uint32_t active_tail:6; - a_uint32_t active_head:6; - a_uint32_t active_vld:1; - a_uint32_t active_max_n_0:1; - a_uint32_t active_max_n_1:4; - a_uint32_t _reserved0:28; -}; - -union l1_e_drr_head_tbl_u { - a_uint32_t val[2]; - struct l1_e_drr_head_tbl bf; -}; - -/*[table] L1_DRR_CREDIT_TBL*/ -#define L1_DRR_CREDIT_TBL -#define L1_DRR_CREDIT_TBL_ADDRESS 0x4c000 -#define L1_DRR_CREDIT_TBL_NUM 64 -#define L1_DRR_CREDIT_TBL_INC 0x10 -#define L1_DRR_CREDIT_TBL_TYPE REG_TYPE_RO -#define L1_DRR_CREDIT_TBL_DEFAULT 0x0 - /*[field] C_DRR_CREDIT*/ - #define L1_DRR_CREDIT_TBL_C_DRR_CREDIT - #define L1_DRR_CREDIT_TBL_C_DRR_CREDIT_OFFSET 0 - #define L1_DRR_CREDIT_TBL_C_DRR_CREDIT_LEN 24 - #define L1_DRR_CREDIT_TBL_C_DRR_CREDIT_DEFAULT 0x0 - /*[field] C_DRR_CREDIT_NEG*/ - #define L1_DRR_CREDIT_TBL_C_DRR_CREDIT_NEG - #define L1_DRR_CREDIT_TBL_C_DRR_CREDIT_NEG_OFFSET 24 - #define L1_DRR_CREDIT_TBL_C_DRR_CREDIT_NEG_LEN 1 - #define L1_DRR_CREDIT_TBL_C_DRR_CREDIT_NEG_DEFAULT 0x0 - /*[field] E_DRR_CREDIT*/ - #define L1_DRR_CREDIT_TBL_E_DRR_CREDIT - #define L1_DRR_CREDIT_TBL_E_DRR_CREDIT_OFFSET 25 - #define L1_DRR_CREDIT_TBL_E_DRR_CREDIT_LEN 24 - #define L1_DRR_CREDIT_TBL_E_DRR_CREDIT_DEFAULT 0x0 - /*[field] E_DRR_CREDIT_NEG*/ - #define L1_DRR_CREDIT_TBL_E_DRR_CREDIT_NEG - #define L1_DRR_CREDIT_TBL_E_DRR_CREDIT_NEG_OFFSET 49 - #define L1_DRR_CREDIT_TBL_E_DRR_CREDIT_NEG_LEN 1 - #define L1_DRR_CREDIT_TBL_E_DRR_CREDIT_NEG_DEFAULT 0x0 - -struct l1_drr_credit_tbl { - a_uint32_t c_drr_credit:24; - a_uint32_t c_drr_credit_neg:1; - a_uint32_t e_drr_credit_0:7; - a_uint32_t e_drr_credit_1:17; - a_uint32_t e_drr_credit_neg:1; - a_uint32_t _reserved0:14; -}; - -union l1_drr_credit_tbl_u { - a_uint32_t val[2]; - struct l1_drr_credit_tbl bf; -}; - -/*[table] L1_C_DRR_LL_TBL*/ -#define L1_C_DRR_LL_TBL -#define L1_C_DRR_LL_TBL_ADDRESS 0x4e000 -#define L1_C_DRR_LL_TBL_NUM 64 -#define L1_C_DRR_LL_TBL_INC 0x10 -#define L1_C_DRR_LL_TBL_TYPE REG_TYPE_RO -#define L1_C_DRR_LL_TBL_DEFAULT 0x0 - /*[field] NEXT_PTR*/ - #define L1_C_DRR_LL_TBL_NEXT_PTR - #define L1_C_DRR_LL_TBL_NEXT_PTR_OFFSET 0 - #define L1_C_DRR_LL_TBL_NEXT_PTR_LEN 6 - #define L1_C_DRR_LL_TBL_NEXT_PTR_DEFAULT 0x0 - -struct l1_c_drr_ll_tbl { - a_uint32_t next_ptr:6; - a_uint32_t _reserved0:26; -}; - -union l1_c_drr_ll_tbl_u { - a_uint32_t val; - struct l1_c_drr_ll_tbl bf; -}; - -/*[table] L1_C_DRR_REVERSE_LL_TBL*/ -#define L1_C_DRR_REVERSE_LL_TBL -#define L1_C_DRR_REVERSE_LL_TBL_ADDRESS 0x50000 -#define L1_C_DRR_REVERSE_LL_TBL_NUM 64 -#define L1_C_DRR_REVERSE_LL_TBL_INC 0x10 -#define L1_C_DRR_REVERSE_LL_TBL_TYPE REG_TYPE_RO -#define L1_C_DRR_REVERSE_LL_TBL_DEFAULT 0x0 - /*[field] PRE_PTR*/ - #define L1_C_DRR_REVERSE_LL_TBL_PRE_PTR - #define L1_C_DRR_REVERSE_LL_TBL_PRE_PTR_OFFSET 0 - #define L1_C_DRR_REVERSE_LL_TBL_PRE_PTR_LEN 6 - #define L1_C_DRR_REVERSE_LL_TBL_PRE_PTR_DEFAULT 0x0 - -struct l1_c_drr_reverse_ll_tbl { - a_uint32_t pre_ptr:6; - a_uint32_t _reserved0:26; -}; - -union l1_c_drr_reverse_ll_tbl_u { - a_uint32_t val; - struct l1_c_drr_reverse_ll_tbl bf; -}; - -/*[table] L1_E_DRR_LL_TBL*/ -#define L1_E_DRR_LL_TBL -#define L1_E_DRR_LL_TBL_ADDRESS 0x52000 -#define L1_E_DRR_LL_TBL_NUM 64 -#define L1_E_DRR_LL_TBL_INC 0x10 -#define L1_E_DRR_LL_TBL_TYPE REG_TYPE_RO -#define L1_E_DRR_LL_TBL_DEFAULT 0x0 - /*[field] NEXT_PTR*/ - #define L1_E_DRR_LL_TBL_NEXT_PTR - #define L1_E_DRR_LL_TBL_NEXT_PTR_OFFSET 0 - #define L1_E_DRR_LL_TBL_NEXT_PTR_LEN 6 - #define L1_E_DRR_LL_TBL_NEXT_PTR_DEFAULT 0x0 - -struct l1_e_drr_ll_tbl { - a_uint32_t next_ptr:6; - a_uint32_t _reserved0:26; -}; - -union l1_e_drr_ll_tbl_u { - a_uint32_t val; - struct l1_e_drr_ll_tbl bf; -}; - -/*[table] L1_E_DRR_REVERSE_LL_TBL*/ -#define L1_E_DRR_REVERSE_LL_TBL -#define L1_E_DRR_REVERSE_LL_TBL_ADDRESS 0x54000 -#define L1_E_DRR_REVERSE_LL_TBL_NUM 64 -#define L1_E_DRR_REVERSE_LL_TBL_INC 0x10 -#define L1_E_DRR_REVERSE_LL_TBL_TYPE REG_TYPE_RO -#define L1_E_DRR_REVERSE_LL_TBL_DEFAULT 0x0 - /*[field] PRE_PTR*/ - #define L1_E_DRR_REVERSE_LL_TBL_PRE_PTR - #define L1_E_DRR_REVERSE_LL_TBL_PRE_PTR_OFFSET 0 - #define L1_E_DRR_REVERSE_LL_TBL_PRE_PTR_LEN 6 - #define L1_E_DRR_REVERSE_LL_TBL_PRE_PTR_DEFAULT 0x0 - -struct l1_e_drr_reverse_ll_tbl { - a_uint32_t pre_ptr:6; - a_uint32_t _reserved0:26; -}; - -union l1_e_drr_reverse_ll_tbl_u { - a_uint32_t val; - struct l1_e_drr_reverse_ll_tbl bf; -}; - -/*[table] L1_A_FLOW_ENTRY_TBL*/ -#define L1_A_FLOW_ENTRY_TBL -#define L1_A_FLOW_ENTRY_TBL_ADDRESS 0x56000 -#define L1_A_FLOW_ENTRY_TBL_NUM 64 -#define L1_A_FLOW_ENTRY_TBL_INC 0x10 -#define L1_A_FLOW_ENTRY_TBL_TYPE REG_TYPE_RO -#define L1_A_FLOW_ENTRY_TBL_DEFAULT 0x0 - /*[field] ENTRY_PATH_ID*/ - #define L1_A_FLOW_ENTRY_TBL_ENTRY_PATH_ID - #define L1_A_FLOW_ENTRY_TBL_ENTRY_PATH_ID_OFFSET 0 - #define L1_A_FLOW_ENTRY_TBL_ENTRY_PATH_ID_LEN 10 - #define L1_A_FLOW_ENTRY_TBL_ENTRY_PATH_ID_DEFAULT 0x0 - -struct l1_a_flow_entry_tbl { - a_uint32_t entry_path_id:10; - a_uint32_t _reserved0:22; -}; - -union l1_a_flow_entry_tbl_u { - a_uint32_t val; - struct l1_a_flow_entry_tbl bf; -}; - -/*[table] L1_B_FLOW_ENTRY_TBL*/ -#define L1_B_FLOW_ENTRY_TBL -#define L1_B_FLOW_ENTRY_TBL_ADDRESS 0x58000 -#define L1_B_FLOW_ENTRY_TBL_NUM 64 -#define L1_B_FLOW_ENTRY_TBL_INC 0x10 -#define L1_B_FLOW_ENTRY_TBL_TYPE REG_TYPE_RO -#define L1_B_FLOW_ENTRY_TBL_DEFAULT 0x0 - /*[field] ENTRY_PATH_ID*/ - #define L1_B_FLOW_ENTRY_TBL_ENTRY_PATH_ID - #define L1_B_FLOW_ENTRY_TBL_ENTRY_PATH_ID_OFFSET 0 - #define L1_B_FLOW_ENTRY_TBL_ENTRY_PATH_ID_LEN 10 - #define L1_B_FLOW_ENTRY_TBL_ENTRY_PATH_ID_DEFAULT 0x0 - -struct l1_b_flow_entry_tbl { - a_uint32_t entry_path_id:10; - a_uint32_t _reserved0:22; -}; - -union l1_b_flow_entry_tbl_u { - a_uint32_t val; - struct l1_b_flow_entry_tbl bf; -}; - -/*[table] L1_SP_ENTRY_TBL*/ -#define L1_SP_ENTRY_TBL -#define L1_SP_ENTRY_TBL_ADDRESS 0x5a000 -#define L1_SP_ENTRY_TBL_NUM 8 -#define L1_SP_ENTRY_TBL_INC 0x40 -#define L1_SP_ENTRY_TBL_TYPE REG_TYPE_RO -#define L1_SP_ENTRY_TBL_DEFAULT 0x0 - /*[field] ENTRY_PATH_ID*/ - #define L1_SP_ENTRY_TBL_ENTRY_PATH_ID - #define L1_SP_ENTRY_TBL_ENTRY_PATH_ID_OFFSET 0 - #define L1_SP_ENTRY_TBL_ENTRY_PATH_ID_LEN 256 - #define L1_SP_ENTRY_TBL_ENTRY_PATH_ID_DEFAULT 0x0 - /*[field] ENTRY_VLD*/ - #define L1_SP_ENTRY_TBL_ENTRY_VLD - #define L1_SP_ENTRY_TBL_ENTRY_VLD_OFFSET 256 - #define L1_SP_ENTRY_TBL_ENTRY_VLD_LEN 16 - #define L1_SP_ENTRY_TBL_ENTRY_VLD_DEFAULT 0x0 - -struct l1_sp_entry_tbl { - a_uint32_t entry_path_id_0:32; - a_uint32_t entry_path_id_1:32; - a_uint32_t entry_path_id_2:32; - a_uint32_t entry_path_id_3:32; - a_uint32_t entry_path_id_4:32; - a_uint32_t entry_path_id_5:32; - a_uint32_t entry_path_id_6:32; - a_uint32_t entry_path_id_7:32; - a_uint32_t entry_vld:16; - a_uint32_t _reserved0:16; -}; - -union l1_sp_entry_tbl_u { - a_uint32_t val[9]; - struct l1_sp_entry_tbl bf; -}; - - -/*[table] L1_ENS_Q_LL_TBL*/ -#define L1_ENS_Q_LL_TBL -#define L1_ENS_Q_LL_TBL_ADDRESS 0x60000 -#define L1_ENS_Q_LL_TBL_NUM 64 -#define L1_ENS_Q_LL_TBL_INC 0x10 -#define L1_ENS_Q_LL_TBL_TYPE REG_TYPE_RO -#define L1_ENS_Q_LL_TBL_DEFAULT 0x0 - /*[field] NEXT_PTR*/ - #define L1_ENS_Q_LL_TBL_NEXT_PTR - #define L1_ENS_Q_LL_TBL_NEXT_PTR_OFFSET 0 - #define L1_ENS_Q_LL_TBL_NEXT_PTR_LEN 6 - #define L1_ENS_Q_LL_TBL_NEXT_PTR_DEFAULT 0x0 - -struct l1_ens_q_ll_tbl { - a_uint32_t next_ptr:6; - a_uint32_t _reserved0:26; -}; - -union l1_ens_q_ll_tbl_u { - a_uint32_t val; - struct l1_ens_q_ll_tbl bf; -}; - -/*[table] L1_ENS_Q_HEAD_TBL*/ -#define L1_ENS_Q_HEAD_TBL -#define L1_ENS_Q_HEAD_TBL_ADDRESS 0x62000 -#define L1_ENS_Q_HEAD_TBL_NUM 8 -#define L1_ENS_Q_HEAD_TBL_INC 0x10 -#define L1_ENS_Q_HEAD_TBL_TYPE REG_TYPE_RO -#define L1_ENS_Q_HEAD_TBL_DEFAULT 0x0 - /*[field] TAIL*/ - #define L1_ENS_Q_HEAD_TBL_TAIL - #define L1_ENS_Q_HEAD_TBL_TAIL_OFFSET 0 - #define L1_ENS_Q_HEAD_TBL_TAIL_LEN 6 - #define L1_ENS_Q_HEAD_TBL_TAIL_DEFAULT 0x0 - /*[field] HEAD*/ - #define L1_ENS_Q_HEAD_TBL_HEAD - #define L1_ENS_Q_HEAD_TBL_HEAD_OFFSET 6 - #define L1_ENS_Q_HEAD_TBL_HEAD_LEN 6 - #define L1_ENS_Q_HEAD_TBL_HEAD_DEFAULT 0x0 - /*[field] VLD*/ - #define L1_ENS_Q_HEAD_TBL_VLD - #define L1_ENS_Q_HEAD_TBL_VLD_OFFSET 12 - #define L1_ENS_Q_HEAD_TBL_VLD_LEN 1 - #define L1_ENS_Q_HEAD_TBL_VLD_DEFAULT 0x0 - -struct l1_ens_q_head_tbl { - a_uint32_t tail:6; - a_uint32_t head:6; - a_uint32_t vld:1; - a_uint32_t _reserved0:19; -}; - -union l1_ens_q_head_tbl_u { - a_uint32_t val; - struct l1_ens_q_head_tbl bf; -}; - -/*[table] L1_ENS_Q_ENTRY_TBL*/ -#define L1_ENS_Q_ENTRY_TBL -#define L1_ENS_Q_ENTRY_TBL_ADDRESS 0x64000 -#define L1_ENS_Q_ENTRY_TBL_NUM 64 -#define L1_ENS_Q_ENTRY_TBL_INC 0x10 -#define L1_ENS_Q_ENTRY_TBL_TYPE REG_TYPE_RO -#define L1_ENS_Q_ENTRY_TBL_DEFAULT 0x0 - /*[field] ENTRY_ENS_TYPE*/ - #define L1_ENS_Q_ENTRY_TBL_ENTRY_ENS_TYPE - #define L1_ENS_Q_ENTRY_TBL_ENTRY_ENS_TYPE_OFFSET 0 - #define L1_ENS_Q_ENTRY_TBL_ENTRY_ENS_TYPE_LEN 2 - #define L1_ENS_Q_ENTRY_TBL_ENTRY_ENS_TYPE_DEFAULT 0x0 - /*[field] ENTRY_ENS_VLD*/ - #define L1_ENS_Q_ENTRY_TBL_ENTRY_ENS_VLD - #define L1_ENS_Q_ENTRY_TBL_ENTRY_ENS_VLD_OFFSET 2 - #define L1_ENS_Q_ENTRY_TBL_ENTRY_ENS_VLD_LEN 1 - #define L1_ENS_Q_ENTRY_TBL_ENTRY_ENS_VLD_DEFAULT 0x0 - /*[field] ENTRY_ENS_IN_Q*/ - #define L1_ENS_Q_ENTRY_TBL_ENTRY_ENS_IN_Q - #define L1_ENS_Q_ENTRY_TBL_ENTRY_ENS_IN_Q_OFFSET 3 - #define L1_ENS_Q_ENTRY_TBL_ENTRY_ENS_IN_Q_LEN 1 - #define L1_ENS_Q_ENTRY_TBL_ENTRY_ENS_IN_Q_DEFAULT 0x0 - -struct l1_ens_q_entry_tbl { - a_uint32_t entry_ens_type:2; - a_uint32_t entry_ens_vld:1; - a_uint32_t entry_ens_in_q:1; - a_uint32_t _reserved0:28; -}; - -union l1_ens_q_entry_tbl_u { - a_uint32_t val; - struct l1_ens_q_entry_tbl bf; -}; - -/*[table] L1_FLOW_STATUS_TBL*/ -#define L1_FLOW_STATUS_TBL -#define L1_FLOW_STATUS_TBL_ADDRESS 0x66000 -#define L1_FLOW_STATUS_TBL_NUM 64 -#define L1_FLOW_STATUS_TBL_INC 0x10 -#define L1_FLOW_STATUS_TBL_TYPE REG_TYPE_RO -#define L1_FLOW_STATUS_TBL_DEFAULT 0x0 - /*[field] EN_LEVEL*/ - #define L1_FLOW_STATUS_TBL_EN_LEVEL - #define L1_FLOW_STATUS_TBL_EN_LEVEL_OFFSET 0 - #define L1_FLOW_STATUS_TBL_EN_LEVEL_LEN 1 - #define L1_FLOW_STATUS_TBL_EN_LEVEL_DEFAULT 0x0 - /*[field] EN_CDRR*/ - #define L1_FLOW_STATUS_TBL_EN_CDRR - #define L1_FLOW_STATUS_TBL_EN_CDRR_OFFSET 1 - #define L1_FLOW_STATUS_TBL_EN_CDRR_LEN 1 - #define L1_FLOW_STATUS_TBL_EN_CDRR_DEFAULT 0x0 - /*[field] EN_EDRR*/ - #define L1_FLOW_STATUS_TBL_EN_EDRR - #define L1_FLOW_STATUS_TBL_EN_EDRR_OFFSET 2 - #define L1_FLOW_STATUS_TBL_EN_EDRR_LEN 1 - #define L1_FLOW_STATUS_TBL_EN_EDRR_DEFAULT 0x0 - -struct l1_flow_status_tbl { - a_uint32_t en_level:1; - a_uint32_t en_cdrr:1; - a_uint32_t en_edrr:1; - a_uint32_t _reserved0:29; -}; - -union l1_flow_status_tbl_u { - a_uint32_t val; - struct l1_flow_status_tbl bf; -}; - -/*[table] PSCH_TDM_CFG_TBL*/ -#define PSCH_TDM_CFG_TBL -#define PSCH_TDM_CFG_TBL_ADDRESS 0x7a000 -#define PSCH_TDM_CFG_TBL_NUM 128 -#define PSCH_TDM_CFG_TBL_INC 0x10 -#define PSCH_TDM_CFG_TBL_TYPE REG_TYPE_RW -#define PSCH_TDM_CFG_TBL_DEFAULT 0x0 - /*[field] DES_PORT*/ - #define PSCH_TDM_CFG_TBL_DES_PORT - #define PSCH_TDM_CFG_TBL_DES_PORT_OFFSET 0 - #define PSCH_TDM_CFG_TBL_DES_PORT_LEN 4 - #define PSCH_TDM_CFG_TBL_DES_PORT_DEFAULT 0x0 - /*[field] ENS_PORT*/ - #define PSCH_TDM_CFG_TBL_ENS_PORT - #define PSCH_TDM_CFG_TBL_ENS_PORT_OFFSET 4 - #define PSCH_TDM_CFG_TBL_ENS_PORT_LEN 4 - #define PSCH_TDM_CFG_TBL_ENS_PORT_DEFAULT 0x0 - /*[field] ENS_PORT_BITMAP*/ - #define PSCH_TDM_CFG_TBL_ENS_PORT_BITMAP - #define PSCH_TDM_CFG_TBL_ENS_PORT_BITMAP_OFFSET 8 - #define PSCH_TDM_CFG_TBL_ENS_PORT_BITMAP_LEN 8 - #define PSCH_TDM_CFG_TBL_ENS_PORT_BITMAP_DEFAULT 0x0 - -struct psch_tdm_cfg_tbl { - a_uint32_t des_port:4; - a_uint32_t ens_port:4; - a_uint32_t ens_port_bitmap:8; - a_uint32_t _reserved0:16; -}; - -union psch_tdm_cfg_tbl_u { - a_uint32_t val; - struct psch_tdm_cfg_tbl bf; -}; - -/*[register] PORT_QOS_CTRL*/ -#define PORT_QOS_CTRL -#define PORT_QOS_CTRL_ADDRESS 0x900 -#define PORT_QOS_CTRL_NUM 8 -#define PORT_QOS_CTRL_INC 0x10 -#define PORT_QOS_CTRL_TYPE REG_TYPE_RW -#define PORT_QOS_CTRL_DEFAULT 0x23440 - /*[field] PCP_QOS_GROUP_ID*/ - #define PORT_QOS_CTRL_PCP_QOS_GROUP_ID - #define PORT_QOS_CTRL_PCP_QOS_GROUP_ID_OFFSET 0 - #define PORT_QOS_CTRL_PCP_QOS_GROUP_ID_LEN 1 - #define PORT_QOS_CTRL_PCP_QOS_GROUP_ID_DEFAULT 0x0 - /*[field] DSCP_QOS_GROUP_ID*/ - #define PORT_QOS_CTRL_DSCP_QOS_GROUP_ID - #define PORT_QOS_CTRL_DSCP_QOS_GROUP_ID_OFFSET 1 - #define PORT_QOS_CTRL_DSCP_QOS_GROUP_ID_LEN 1 - #define PORT_QOS_CTRL_DSCP_QOS_GROUP_ID_DEFAULT 0x0 - /*[field] FLOW_QOS_GROUP_ID*/ - #define PORT_QOS_CTRL_FLOW_QOS_GROUP_ID - #define PORT_QOS_CTRL_FLOW_QOS_GROUP_ID_OFFSET 2 - #define PORT_QOS_CTRL_FLOW_QOS_GROUP_ID_LEN 1 - #define PORT_QOS_CTRL_FLOW_QOS_GROUP_ID_DEFAULT 0x0 - /*[field] PORT_DSCP_QOS_PRI*/ - #define PORT_QOS_CTRL_PORT_DSCP_QOS_PRI - #define PORT_QOS_CTRL_PORT_DSCP_QOS_PRI_OFFSET 3 - #define PORT_QOS_CTRL_PORT_DSCP_QOS_PRI_LEN 3 - #define PORT_QOS_CTRL_PORT_DSCP_QOS_PRI_DEFAULT 0x0 - /*[field] PORT_PCP_QOS_PRI*/ - #define PORT_QOS_CTRL_PORT_PCP_QOS_PRI - #define PORT_QOS_CTRL_PORT_PCP_QOS_PRI_OFFSET 6 - #define PORT_QOS_CTRL_PORT_PCP_QOS_PRI_LEN 3 - #define PORT_QOS_CTRL_PORT_PCP_QOS_PRI_DEFAULT 0x1 - /*[field] PORT_PREHEADER_QOS_PRI*/ - #define PORT_QOS_CTRL_PORT_PREHEADER_QOS_PRI - #define PORT_QOS_CTRL_PORT_PREHEADER_QOS_PRI_OFFSET 9 - #define PORT_QOS_CTRL_PORT_PREHEADER_QOS_PRI_LEN 3 - #define PORT_QOS_CTRL_PORT_PREHEADER_QOS_PRI_DEFAULT 0x2 - /*[field] PORT_FLOW_QOS_PRI*/ - #define PORT_QOS_CTRL_PORT_FLOW_QOS_PRI - #define PORT_QOS_CTRL_PORT_FLOW_QOS_PRI_OFFSET 12 - #define PORT_QOS_CTRL_PORT_FLOW_QOS_PRI_LEN 3 - #define PORT_QOS_CTRL_PORT_FLOW_QOS_PRI_DEFAULT 0x3 - /*[field] PORT_ACL_QOS_PRI*/ - #define PORT_QOS_CTRL_PORT_ACL_QOS_PRI - #define PORT_QOS_CTRL_PORT_ACL_QOS_PRI_OFFSET 15 - #define PORT_QOS_CTRL_PORT_ACL_QOS_PRI_LEN 3 - #define PORT_QOS_CTRL_PORT_ACL_QOS_PRI_DEFAULT 0x4 - /*[field] PORT_PCP_CHANGE_EN*/ - #define PORT_QOS_CTRL_PORT_PCP_CHANGE_EN - #define PORT_QOS_CTRL_PORT_PCP_CHANGE_EN_OFFSET 18 - #define PORT_QOS_CTRL_PORT_PCP_CHANGE_EN_LEN 1 - #define PORT_QOS_CTRL_PORT_PCP_CHANGE_EN_DEFAULT 0x0 - /*[field] PORT_DEI_CHANGE_EN*/ - #define PORT_QOS_CTRL_PORT_DEI_CHANGE_EN - #define PORT_QOS_CTRL_PORT_DEI_CHANGE_EN_OFFSET 19 - #define PORT_QOS_CTRL_PORT_DEI_CHANGE_EN_LEN 1 - #define PORT_QOS_CTRL_PORT_DEI_CHANGE_EN_DEFAULT 0x0 - /*[field] PORT_DSCP_CHANGE_EN*/ - #define PORT_QOS_CTRL_PORT_DSCP_CHANGE_EN - #define PORT_QOS_CTRL_PORT_DSCP_CHANGE_EN_OFFSET 20 - #define PORT_QOS_CTRL_PORT_DSCP_CHANGE_EN_LEN 1 - #define PORT_QOS_CTRL_PORT_DSCP_CHANGE_EN_DEFAULT 0x0 - -struct port_qos_ctrl { - a_uint32_t pcp_qos_group_id:1; - a_uint32_t dscp_qos_group_id:1; - a_uint32_t flow_qos_group_id:1; - a_uint32_t port_dscp_qos_pri:3; - a_uint32_t port_pcp_qos_pri:3; - a_uint32_t port_preheader_qos_pri:3; - a_uint32_t port_flow_qos_pri:3; - a_uint32_t port_acl_qos_pri:3; - a_uint32_t port_pcp_change_en:1; - a_uint32_t port_dei_change_en:1; - a_uint32_t port_dscp_change_en:1; - a_uint32_t _reserved0:11; -}; - -union port_qos_ctrl_u { - a_uint32_t val; - struct port_qos_ctrl bf; -}; - -/*[register] PCP_QOS_GROUP_0*/ -#define PCP_QOS_GROUP_0 -#define PCP_QOS_GROUP_0_ADDRESS 0xb00 -#define PCP_QOS_GROUP_0_NUM 16 -#define PCP_QOS_GROUP_0_INC 0x4 -#define PCP_QOS_GROUP_0_TYPE REG_TYPE_RW -#define PCP_QOS_GROUP_0_DEFAULT 0x0 - /*[field] QOS_INFO*/ - #define PCP_QOS_GROUP_0_QOS_INFO - #define PCP_QOS_GROUP_0_QOS_INFO_OFFSET 0 - #define PCP_QOS_GROUP_0_QOS_INFO_LEN 16 - #define PCP_QOS_GROUP_0_QOS_INFO_DEFAULT 0x0 - -struct pcp_qos_group_0 { - a_uint32_t qos_info:16; - a_uint32_t _reserved0:16; -}; - -union pcp_qos_group_0_u { - a_uint32_t val; - struct pcp_qos_group_0 bf; -}; - -/*[register] PCP_QOS_GROUP_1*/ -#define PCP_QOS_GROUP_1 -#define PCP_QOS_GROUP_1_ADDRESS 0xc00 -#define PCP_QOS_GROUP_1_NUM 16 -#define PCP_QOS_GROUP_1_INC 0x4 -#define PCP_QOS_GROUP_1_TYPE REG_TYPE_RW -#define PCP_QOS_GROUP_1_DEFAULT 0x0 - /*[field] QOS_INFO*/ - #define PCP_QOS_GROUP_1_QOS_INFO - #define PCP_QOS_GROUP_1_QOS_INFO_OFFSET 0 - #define PCP_QOS_GROUP_1_QOS_INFO_LEN 16 - #define PCP_QOS_GROUP_1_QOS_INFO_DEFAULT 0x0 - -struct pcp_qos_group_1 { - a_uint32_t qos_info:16; - a_uint32_t _reserved0:16; -}; - -union pcp_qos_group_1_u { - a_uint32_t val; - struct pcp_qos_group_1 bf; -}; - -/*[register] FLOW_QOS_GROUP_0*/ -#define FLOW_QOS_GROUP_0 -#define FLOW_QOS_GROUP_0_ADDRESS 0xd00 -#define FLOW_QOS_GROUP_0_NUM 32 -#define FLOW_QOS_GROUP_0_INC 0x4 -#define FLOW_QOS_GROUP_0_TYPE REG_TYPE_RW -#define FLOW_QOS_GROUP_0_DEFAULT 0x0 - /*[field] QOS_INFO*/ - #define FLOW_QOS_GROUP_0_QOS_INFO - #define FLOW_QOS_GROUP_0_QOS_INFO_OFFSET 0 - #define FLOW_QOS_GROUP_0_QOS_INFO_LEN 16 - #define FLOW_QOS_GROUP_0_QOS_INFO_DEFAULT 0x0 - -struct flow_qos_group_0 { - a_uint32_t qos_info:16; - a_uint32_t _reserved0:16; -}; - -union flow_qos_group_0_u { - a_uint32_t val; - struct flow_qos_group_0 bf; -}; - -/*[register] FLOW_QOS_GROUP_1*/ -#define FLOW_QOS_GROUP_1 -#define FLOW_QOS_GROUP_1_ADDRESS 0xe00 -#define FLOW_QOS_GROUP_1_NUM 32 -#define FLOW_QOS_GROUP_1_INC 0x4 -#define FLOW_QOS_GROUP_1_TYPE REG_TYPE_RW -#define FLOW_QOS_GROUP_1_DEFAULT 0x0 - /*[field] QOS_INFO*/ - #define FLOW_QOS_GROUP_1_QOS_INFO - #define FLOW_QOS_GROUP_1_QOS_INFO_OFFSET 0 - #define FLOW_QOS_GROUP_1_QOS_INFO_LEN 16 - #define FLOW_QOS_GROUP_1_QOS_INFO_DEFAULT 0x0 - -struct flow_qos_group_1 { - a_uint32_t qos_info:16; - a_uint32_t _reserved0:16; -}; - -union flow_qos_group_1_u { - a_uint32_t val; - struct flow_qos_group_1 bf; -}; - -/*[register] DSCP_QOS_GROUP_0*/ -#define DSCP_QOS_GROUP_0 -#define DSCP_QOS_GROUP_0_ADDRESS 0x2000 -#define DSCP_QOS_GROUP_0_NUM 64 -#define DSCP_QOS_GROUP_0_INC 0x10 -#define DSCP_QOS_GROUP_0_TYPE REG_TYPE_RW -#define DSCP_QOS_GROUP_0_DEFAULT 0x0 - /*[field] QOS_INFO*/ - #define DSCP_QOS_GROUP_0_QOS_INFO - #define DSCP_QOS_GROUP_0_QOS_INFO_OFFSET 0 - #define DSCP_QOS_GROUP_0_QOS_INFO_LEN 16 - #define DSCP_QOS_GROUP_0_QOS_INFO_DEFAULT 0x0 - -struct dscp_qos_group_0 { - a_uint32_t qos_info:16; - a_uint32_t _reserved0:16; -}; - -union dscp_qos_group_0_u { - a_uint32_t val; - struct dscp_qos_group_0 bf; -}; - -/*[register] DSCP_QOS_GROUP_1*/ -#define DSCP_QOS_GROUP_1 -#define DSCP_QOS_GROUP_1_ADDRESS 0x2800 -#define DSCP_QOS_GROUP_1_NUM 64 -#define DSCP_QOS_GROUP_1_INC 0x10 -#define DSCP_QOS_GROUP_1_TYPE REG_TYPE_RW -#define DSCP_QOS_GROUP_1_DEFAULT 0x0 - /*[field] QOS_INFO*/ - #define DSCP_QOS_GROUP_1_QOS_INFO - #define DSCP_QOS_GROUP_1_QOS_INFO_OFFSET 0 - #define DSCP_QOS_GROUP_1_QOS_INFO_LEN 16 - #define DSCP_QOS_GROUP_1_QOS_INFO_DEFAULT 0x0 - -struct dscp_qos_group_1 { - a_uint32_t qos_info:16; - a_uint32_t _reserved0:16; -}; - -union dscp_qos_group_1_u { - a_uint32_t val; - struct dscp_qos_group_1 bf; -}; - -#endif diff --git a/feeds/ipq807x/qca-ssdk/src/include/hsl/hppe/hppe_reg_access.h b/feeds/ipq807x/qca-ssdk/src/include/hsl/hppe/hppe_reg_access.h deleted file mode 100755 index 9ecc4c8ad..000000000 --- a/feeds/ipq807x/qca-ssdk/src/include/hsl/hppe/hppe_reg_access.h +++ /dev/null @@ -1,55 +0,0 @@ -/* - * Copyright (c) 2014-2018, The Linux Foundation. All rights reserved. - * Permission to use, copy, modify, and/or distribute this software for - * any purpose with or without fee is hereby granted, provided that the - * above copyright notice and this permission notice appear in all copies. - * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES - * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR - * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES - * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN - * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT - * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. - */ - - - -#ifndef _HPPE_REG_ACCESS_H_ -#define _HPPE_REG_ACCESS_H_ - -#ifdef __cplusplus -extern "C" { -#endif /* __cplusplus */ - -#include "sw.h" - -#define EDMA_CSR_BASE_ADDR 0xb00000 -#define IPE_L3_BASE_ADDR 0x200000 -#define QUEUE_MANAGER_BASE_ADDR 0x800000 -#define TRAFFIC_MANAGER_BASE_ADDR 0x400000 -#define INGRESS_POLICER_BASE_ADDR 0x100000 -#define INGRESS_VLAN_BASE_ADDR 0x00f000 -#define IPE_L2_BASE_ADDR 0x060000 -#define IPO_CSR_BASE_ADDR 0x0b0000 -#define IPR_CSR_BASE_ADDR 0x002000 -#define NSS_MAC_CSR_BASE_ADDR 0x001000 -#define NSS_PRX_CSR_BASE_ADDR 0x00b000 -#define NSS_PTX_CSR_BASE_ADDR 0x020000 -#define NSS_BM_CSR_BASE_ADDR 0x600000 -#define NSS_XGMAC_CSR_BASE_ADDR 0x003000 -#define NSS_GLOBAL_BASE_ADDR 0x0 -#define NSS_UNIPHY_BASE_ADDR 0x0 -#define NSS_LPI_BASE_ADDR 0x400 - -sw_error_t hppe_reg_get(a_uint32_t dev_id, a_uint32_t reg_addr, a_uint32_t *val); -sw_error_t hppe_reg_set(a_uint32_t dev_id, a_uint32_t reg_addr, a_uint32_t val); -sw_error_t hppe_reg_tbl_get(a_uint32_t dev_id, a_uint32_t reg_addr, a_uint32_t *val, a_uint32_t num); -sw_error_t hppe_reg_tbl_set(a_uint32_t dev_id, a_uint32_t reg_addr, a_uint32_t *val, a_uint32_t num); -sw_error_t hppe_uniphy_reg_get(a_uint32_t dev_id, a_uint32_t reg_addr, a_uint32_t index, a_uint32_t *val); -sw_error_t hppe_uniphy_reg_set(a_uint32_t dev_id, a_uint32_t reg_addr, a_uint32_t index, a_uint32_t val); - -#ifdef __cplusplus -} -#endif /* __cplusplus */ - -#endif /* _HPPE_REG_ACCESS_H_ */ diff --git a/feeds/ipq807x/qca-ssdk/src/include/hsl/hppe/hppe_rss.h b/feeds/ipq807x/qca-ssdk/src/include/hsl/hppe/hppe_rss.h deleted file mode 100755 index 3be8a956a..000000000 --- a/feeds/ipq807x/qca-ssdk/src/include/hsl/hppe/hppe_rss.h +++ /dev/null @@ -1,249 +0,0 @@ -/* - * Copyright (c) 2016-2017, The Linux Foundation. All rights reserved. - * Permission to use, copy, modify, and/or distribute this software for - * any purpose with or without fee is hereby granted, provided that the - * above copyright notice and this permission notice appear in all copies. - * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES - * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR - * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES - * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN - * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT - * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. - */ - - -/** - * @defgroup - * @{ - */ -#ifndef _HPPE_RSS_H_ -#define _HPPE_RSS_H_ - -#define RSS_HASH_MIX_REG_MAX_ENTRY 11 -#define RSS_HASH_FIN_REG_MAX_ENTRY 5 -#define RSS_HASH_MIX_IPV4_REG_MAX_ENTRY 5 -#define RSS_HASH_FIN_IPV4_REG_MAX_ENTRY 5 - -sw_error_t -hppe_rss_hash_mask_reg_get( - a_uint32_t dev_id, - union rss_hash_mask_reg_u *value); - -sw_error_t -hppe_rss_hash_mask_reg_set( - a_uint32_t dev_id, - union rss_hash_mask_reg_u *value); - -sw_error_t -hppe_rss_hash_seed_reg_get( - a_uint32_t dev_id, - union rss_hash_seed_reg_u *value); - -sw_error_t -hppe_rss_hash_seed_reg_set( - a_uint32_t dev_id, - union rss_hash_seed_reg_u *value); - -sw_error_t -hppe_rss_hash_mix_reg_get( - a_uint32_t dev_id, - a_uint32_t index, - union rss_hash_mix_reg_u *value); - -sw_error_t -hppe_rss_hash_mix_reg_set( - a_uint32_t dev_id, - a_uint32_t index, - union rss_hash_mix_reg_u *value); - -sw_error_t -hppe_rss_hash_fin_reg_get( - a_uint32_t dev_id, - a_uint32_t index, - union rss_hash_fin_reg_u *value); - -sw_error_t -hppe_rss_hash_fin_reg_set( - a_uint32_t dev_id, - a_uint32_t index, - union rss_hash_fin_reg_u *value); - -sw_error_t -hppe_rss_hash_mask_ipv4_reg_get( - a_uint32_t dev_id, - union rss_hash_mask_ipv4_reg_u *value); - -sw_error_t -hppe_rss_hash_mask_ipv4_reg_set( - a_uint32_t dev_id, - union rss_hash_mask_ipv4_reg_u *value); - -sw_error_t -hppe_rss_hash_seed_ipv4_reg_get( - a_uint32_t dev_id, - union rss_hash_seed_ipv4_reg_u *value); - -sw_error_t -hppe_rss_hash_seed_ipv4_reg_set( - a_uint32_t dev_id, - union rss_hash_seed_ipv4_reg_u *value); - -sw_error_t -hppe_rss_hash_mix_ipv4_reg_get( - a_uint32_t dev_id, - a_uint32_t index, - union rss_hash_mix_ipv4_reg_u *value); - -sw_error_t -hppe_rss_hash_mix_ipv4_reg_set( - a_uint32_t dev_id, - a_uint32_t index, - union rss_hash_mix_ipv4_reg_u *value); - -sw_error_t -hppe_rss_hash_fin_ipv4_reg_get( - a_uint32_t dev_id, - a_uint32_t index, - union rss_hash_fin_ipv4_reg_u *value); - -sw_error_t -hppe_rss_hash_fin_ipv4_reg_set( - a_uint32_t dev_id, - a_uint32_t index, - union rss_hash_fin_ipv4_reg_u *value); - -sw_error_t -hppe_rss_hash_mask_reg_fragment_get( - a_uint32_t dev_id, - unsigned int *value); - -sw_error_t -hppe_rss_hash_mask_reg_fragment_set( - a_uint32_t dev_id, - unsigned int value); - -sw_error_t -hppe_rss_hash_mask_reg_mask_get( - a_uint32_t dev_id, - unsigned int *value); - -sw_error_t -hppe_rss_hash_mask_reg_mask_set( - a_uint32_t dev_id, - unsigned int value); - -sw_error_t -hppe_rss_hash_seed_reg_seed_get( - a_uint32_t dev_id, - unsigned int *value); - -sw_error_t -hppe_rss_hash_seed_reg_seed_set( - a_uint32_t dev_id, - unsigned int value); - -sw_error_t -hppe_rss_hash_mix_reg_hash_mix_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_rss_hash_mix_reg_hash_mix_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_rss_hash_fin_reg_fin_outer_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_rss_hash_fin_reg_fin_outer_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_rss_hash_fin_reg_fin_inner_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_rss_hash_fin_reg_fin_inner_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_rss_hash_mask_ipv4_reg_fragment_get( - a_uint32_t dev_id, - unsigned int *value); - -sw_error_t -hppe_rss_hash_mask_ipv4_reg_fragment_set( - a_uint32_t dev_id, - unsigned int value); - -sw_error_t -hppe_rss_hash_mask_ipv4_reg_mask_get( - a_uint32_t dev_id, - unsigned int *value); - -sw_error_t -hppe_rss_hash_mask_ipv4_reg_mask_set( - a_uint32_t dev_id, - unsigned int value); - -sw_error_t -hppe_rss_hash_seed_ipv4_reg_seed_get( - a_uint32_t dev_id, - unsigned int *value); - -sw_error_t -hppe_rss_hash_seed_ipv4_reg_seed_set( - a_uint32_t dev_id, - unsigned int value); - -sw_error_t -hppe_rss_hash_mix_ipv4_reg_hash_mix_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_rss_hash_mix_ipv4_reg_hash_mix_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_rss_hash_fin_ipv4_reg_fin_outer_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_rss_hash_fin_ipv4_reg_fin_outer_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_rss_hash_fin_ipv4_reg_fin_inner_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_rss_hash_fin_ipv4_reg_fin_inner_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -#endif - diff --git a/feeds/ipq807x/qca-ssdk/src/include/hsl/hppe/hppe_rss_reg.h b/feeds/ipq807x/qca-ssdk/src/include/hsl/hppe/hppe_rss_reg.h deleted file mode 100755 index 189cb7b24..000000000 --- a/feeds/ipq807x/qca-ssdk/src/include/hsl/hppe/hppe_rss_reg.h +++ /dev/null @@ -1,231 +0,0 @@ -/* - * Copyright (c) 2016-2017, The Linux Foundation. All rights reserved. - * Permission to use, copy, modify, and/or distribute this software for - * any purpose with or without fee is hereby granted, provided that the - * above copyright notice and this permission notice appear in all copies. - * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES - * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR - * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES - * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN - * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT - * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. - */ - - -/** - * @defgroup - * @{ - */ -#ifndef HPPE_RSS_REG_H -#define HPPE_RSS_REG_H - -/*[register] RSS_HASH_MASK_REG*/ -#define RSS_HASH_MASK_REG -#define RSS_HASH_MASK_REG_ADDRESS 0x4318 -#define RSS_HASH_MASK_REG_NUM 1 -#define RSS_HASH_MASK_REG_INC 0x4 -#define RSS_HASH_MASK_REG_TYPE REG_TYPE_RW -#define RSS_HASH_MASK_REG_DEFAULT 0x0 - /*[field] MASK*/ - #define RSS_HASH_MASK_REG_MASK - #define RSS_HASH_MASK_REG_MASK_OFFSET 0 - #define RSS_HASH_MASK_REG_MASK_LEN 21 - #define RSS_HASH_MASK_REG_MASK_DEFAULT 0x0 - /*[field] FRAGMENT*/ - #define RSS_HASH_MASK_REG_FRAGMENT - #define RSS_HASH_MASK_REG_FRAGMENT_OFFSET 28 - #define RSS_HASH_MASK_REG_FRAGMENT_LEN 1 - #define RSS_HASH_MASK_REG_FRAGMENT_DEFAULT 0x0 - -struct rss_hash_mask_reg { - a_uint32_t mask:21; - a_uint32_t _reserved0:7; - a_uint32_t fragment:1; - a_uint32_t _reserved1:3; -}; - -union rss_hash_mask_reg_u { - a_uint32_t val; - struct rss_hash_mask_reg bf; -}; - -/*[register] RSS_HASH_SEED_REG*/ -#define RSS_HASH_SEED_REG -#define RSS_HASH_SEED_REG_ADDRESS 0x431c -#define RSS_HASH_SEED_REG_NUM 1 -#define RSS_HASH_SEED_REG_INC 0x4 -#define RSS_HASH_SEED_REG_TYPE REG_TYPE_RW -#define RSS_HASH_SEED_REG_DEFAULT 0x0 - /*[field] SEED*/ - #define RSS_HASH_SEED_REG_SEED - #define RSS_HASH_SEED_REG_SEED_OFFSET 0 - #define RSS_HASH_SEED_REG_SEED_LEN 32 - #define RSS_HASH_SEED_REG_SEED_DEFAULT 0x0 - -struct rss_hash_seed_reg { - a_uint32_t seed:32; -}; - -union rss_hash_seed_reg_u { - a_uint32_t val; - struct rss_hash_seed_reg bf; -}; - -/*[register] RSS_HASH_MIX_REG*/ -#define RSS_HASH_MIX_REG -#define RSS_HASH_MIX_REG_ADDRESS 0x4320 -#define RSS_HASH_MIX_REG_NUM 11 -#define RSS_HASH_MIX_REG_INC 0x4 -#define RSS_HASH_MIX_REG_TYPE REG_TYPE_RW -#define RSS_HASH_MIX_REG_DEFAULT 0x0 - /*[field] HASH_MIX*/ - #define RSS_HASH_MIX_REG_HASH_MIX - #define RSS_HASH_MIX_REG_HASH_MIX_OFFSET 0 - #define RSS_HASH_MIX_REG_HASH_MIX_LEN 5 - #define RSS_HASH_MIX_REG_HASH_MIX_DEFAULT 0x0 - -struct rss_hash_mix_reg { - a_uint32_t hash_mix:5; - a_uint32_t _reserved0:27; -}; - -union rss_hash_mix_reg_u { - a_uint32_t val; - struct rss_hash_mix_reg bf; -}; - -/*[register] RSS_HASH_FIN_REG*/ -#define RSS_HASH_FIN_REG -#define RSS_HASH_FIN_REG_ADDRESS 0x4350 -#define RSS_HASH_FIN_REG_NUM 5 -#define RSS_HASH_FIN_REG_INC 0x4 -#define RSS_HASH_FIN_REG_TYPE REG_TYPE_RW -#define RSS_HASH_FIN_REG_DEFAULT 0x0 - /*[field] FIN_INNER*/ - #define RSS_HASH_FIN_REG_FIN_INNER - #define RSS_HASH_FIN_REG_FIN_INNER_OFFSET 0 - #define RSS_HASH_FIN_REG_FIN_INNER_LEN 5 - #define RSS_HASH_FIN_REG_FIN_INNER_DEFAULT 0x0 - /*[field] FIN_OUTER*/ - #define RSS_HASH_FIN_REG_FIN_OUTER - #define RSS_HASH_FIN_REG_FIN_OUTER_OFFSET 5 - #define RSS_HASH_FIN_REG_FIN_OUTER_LEN 5 - #define RSS_HASH_FIN_REG_FIN_OUTER_DEFAULT 0x0 - -struct rss_hash_fin_reg { - a_uint32_t fin_inner:5; - a_uint32_t fin_outer:5; - a_uint32_t _reserved0:22; -}; - -union rss_hash_fin_reg_u { - a_uint32_t val; - struct rss_hash_fin_reg bf; -}; - -/*[register] RSS_HASH_MASK_IPV4_REG*/ -#define RSS_HASH_MASK_IPV4_REG -#define RSS_HASH_MASK_IPV4_REG_ADDRESS 0x4380 -#define RSS_HASH_MASK_IPV4_REG_NUM 1 -#define RSS_HASH_MASK_IPV4_REG_INC 0x4 -#define RSS_HASH_MASK_IPV4_REG_TYPE REG_TYPE_RW -#define RSS_HASH_MASK_IPV4_REG_DEFAULT 0x0 - /*[field] MASK*/ - #define RSS_HASH_MASK_IPV4_REG_MASK - #define RSS_HASH_MASK_IPV4_REG_MASK_OFFSET 0 - #define RSS_HASH_MASK_IPV4_REG_MASK_LEN 21 - #define RSS_HASH_MASK_IPV4_REG_MASK_DEFAULT 0x0 - /*[field] FRAGMENT*/ - #define RSS_HASH_MASK_IPV4_REG_FRAGMENT - #define RSS_HASH_MASK_IPV4_REG_FRAGMENT_OFFSET 28 - #define RSS_HASH_MASK_IPV4_REG_FRAGMENT_LEN 1 - #define RSS_HASH_MASK_IPV4_REG_FRAGMENT_DEFAULT 0x0 - -struct rss_hash_mask_ipv4_reg { - a_uint32_t mask:21; - a_uint32_t _reserved0:7; - a_uint32_t fragment:1; - a_uint32_t _reserved1:3; -}; - -union rss_hash_mask_ipv4_reg_u { - a_uint32_t val; - struct rss_hash_mask_ipv4_reg bf; -}; - -/*[register] RSS_HASH_SEED_IPV4_REG*/ -#define RSS_HASH_SEED_IPV4_REG -#define RSS_HASH_SEED_IPV4_REG_ADDRESS 0x4384 -#define RSS_HASH_SEED_IPV4_REG_NUM 1 -#define RSS_HASH_SEED_IPV4_REG_INC 0x4 -#define RSS_HASH_SEED_IPV4_REG_TYPE REG_TYPE_RW -#define RSS_HASH_SEED_IPV4_REG_DEFAULT 0x0 - /*[field] SEED*/ - #define RSS_HASH_SEED_IPV4_REG_SEED - #define RSS_HASH_SEED_IPV4_REG_SEED_OFFSET 0 - #define RSS_HASH_SEED_IPV4_REG_SEED_LEN 32 - #define RSS_HASH_SEED_IPV4_REG_SEED_DEFAULT 0x0 - -struct rss_hash_seed_ipv4_reg { - a_uint32_t seed:32; -}; - -union rss_hash_seed_ipv4_reg_u { - a_uint32_t val; - struct rss_hash_seed_ipv4_reg bf; -}; - -/*[register] RSS_HASH_MIX_IPV4_REG*/ -#define RSS_HASH_MIX_IPV4_REG -#define RSS_HASH_MIX_IPV4_REG_ADDRESS 0x4390 -#define RSS_HASH_MIX_IPV4_REG_NUM 5 -#define RSS_HASH_MIX_IPV4_REG_INC 0x4 -#define RSS_HASH_MIX_IPV4_REG_TYPE REG_TYPE_RW -#define RSS_HASH_MIX_IPV4_REG_DEFAULT 0x0 - /*[field] HASH_MIX*/ - #define RSS_HASH_MIX_IPV4_REG_HASH_MIX - #define RSS_HASH_MIX_IPV4_REG_HASH_MIX_OFFSET 0 - #define RSS_HASH_MIX_IPV4_REG_HASH_MIX_LEN 5 - #define RSS_HASH_MIX_IPV4_REG_HASH_MIX_DEFAULT 0x0 - -struct rss_hash_mix_ipv4_reg { - a_uint32_t hash_mix:5; - a_uint32_t _reserved0:27; -}; - -union rss_hash_mix_ipv4_reg_u { - a_uint32_t val; - struct rss_hash_mix_ipv4_reg bf; -}; - -/*[register] RSS_HASH_FIN_IPV4_REG*/ -#define RSS_HASH_FIN_IPV4_REG -#define RSS_HASH_FIN_IPV4_REG_ADDRESS 0x43b0 -#define RSS_HASH_FIN_IPV4_REG_NUM 5 -#define RSS_HASH_FIN_IPV4_REG_INC 0x4 -#define RSS_HASH_FIN_IPV4_REG_TYPE REG_TYPE_RW -#define RSS_HASH_FIN_IPV4_REG_DEFAULT 0x0 - /*[field] FIN_INNER*/ - #define RSS_HASH_FIN_IPV4_REG_FIN_INNER - #define RSS_HASH_FIN_IPV4_REG_FIN_INNER_OFFSET 0 - #define RSS_HASH_FIN_IPV4_REG_FIN_INNER_LEN 5 - #define RSS_HASH_FIN_IPV4_REG_FIN_INNER_DEFAULT 0x0 - /*[field] FIN_OUTER*/ - #define RSS_HASH_FIN_IPV4_REG_FIN_OUTER - #define RSS_HASH_FIN_IPV4_REG_FIN_OUTER_OFFSET 5 - #define RSS_HASH_FIN_IPV4_REG_FIN_OUTER_LEN 5 - #define RSS_HASH_FIN_IPV4_REG_FIN_OUTER_DEFAULT 0x0 - -struct rss_hash_fin_ipv4_reg { - a_uint32_t fin_inner:5; - a_uint32_t fin_outer:5; - a_uint32_t _reserved0:22; -}; - -union rss_hash_fin_ipv4_reg_u { - a_uint32_t val; - struct rss_hash_fin_ipv4_reg bf; -}; - -#endif diff --git a/feeds/ipq807x/qca-ssdk/src/include/hsl/hppe/hppe_sec.h b/feeds/ipq807x/qca-ssdk/src/include/hsl/hppe/hppe_sec.h deleted file mode 100755 index e54618972..000000000 --- a/feeds/ipq807x/qca-ssdk/src/include/hsl/hppe/hppe_sec.h +++ /dev/null @@ -1,416 +0,0 @@ -/* - * Copyright (c) 2016-2017, The Linux Foundation. All rights reserved. - * Permission to use, copy, modify, and/or distribute this software for - * any purpose with or without fee is hereby granted, provided that the - * above copyright notice and this permission notice appear in all copies. - * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES - * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR - * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES - * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN - * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT - * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. - */ - - -/** - * @defgroup - * @{ - */ -#ifndef _HPPE_SEC_H_ -#define _HPPE_SEC_H_ - -#define L3_EXCEPTION_CMD_MAX_ENTRY 72 -#define L3_EXP_L3_ONLY_CTRL_MAX_ENTRY 72 -#define L3_EXP_L2_ONLY_CTRL_MAX_ENTRY 72 -#define L3_EXP_L2_FLOW_CTRL_MAX_ENTRY 72 -#define L3_EXP_L3_FLOW_CTRL_MAX_ENTRY 72 -#define L3_EXP_MULTICAST_CTRL_MAX_ENTRY 72 - -sw_error_t -hppe_l3_exception_cmd_get( - a_uint32_t dev_id, - a_uint32_t index, - union l3_exception_cmd_u *value); - -sw_error_t -hppe_l3_exception_cmd_set( - a_uint32_t dev_id, - a_uint32_t index, - union l3_exception_cmd_u *value); - -sw_error_t -hppe_l3_exp_l3_only_ctrl_get( - a_uint32_t dev_id, - a_uint32_t index, - union l3_exp_l3_only_ctrl_u *value); - -sw_error_t -hppe_l3_exp_l3_only_ctrl_set( - a_uint32_t dev_id, - a_uint32_t index, - union l3_exp_l3_only_ctrl_u *value); - -sw_error_t -hppe_l3_exp_l2_only_ctrl_get( - a_uint32_t dev_id, - a_uint32_t index, - union l3_exp_l2_only_ctrl_u *value); - -sw_error_t -hppe_l3_exp_l2_only_ctrl_set( - a_uint32_t dev_id, - a_uint32_t index, - union l3_exp_l2_only_ctrl_u *value); - -sw_error_t -hppe_l3_exp_l2_flow_ctrl_get( - a_uint32_t dev_id, - a_uint32_t index, - union l3_exp_l2_flow_ctrl_u *value); - -sw_error_t -hppe_l3_exp_l2_flow_ctrl_set( - a_uint32_t dev_id, - a_uint32_t index, - union l3_exp_l2_flow_ctrl_u *value); - -sw_error_t -hppe_l3_exp_l3_flow_ctrl_get( - a_uint32_t dev_id, - a_uint32_t index, - union l3_exp_l3_flow_ctrl_u *value); - -sw_error_t -hppe_l3_exp_l3_flow_ctrl_set( - a_uint32_t dev_id, - a_uint32_t index, - union l3_exp_l3_flow_ctrl_u *value); - -sw_error_t -hppe_l3_exp_multicast_ctrl_get( - a_uint32_t dev_id, - a_uint32_t index, - union l3_exp_multicast_ctrl_u *value); - -sw_error_t -hppe_l3_exp_multicast_ctrl_set( - a_uint32_t dev_id, - a_uint32_t index, - union l3_exp_multicast_ctrl_u *value); - -sw_error_t -hppe_l3_exception_cmd_l3_excep_cmd_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_l3_exception_cmd_l3_excep_cmd_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_l3_exception_cmd_de_acce_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_l3_exception_cmd_de_acce_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_l3_exp_l3_only_ctrl_excep_en_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_l3_exp_l3_only_ctrl_excep_en_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_l3_exp_l2_only_ctrl_excep_en_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_l3_exp_l2_only_ctrl_excep_en_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_l3_exp_l2_flow_ctrl_excep_en_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_l3_exp_l2_flow_ctrl_excep_en_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_l3_exp_l3_flow_ctrl_excep_en_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_l3_exp_l3_flow_ctrl_excep_en_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_l3_exp_multicast_ctrl_excep_en_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_l3_exp_multicast_ctrl_excep_en_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_l3_exception_parsing_ctrl_reg_get( - a_uint32_t dev_id, - union l3_exception_parsing_ctrl_reg_u *value); - -sw_error_t -hppe_l3_exception_parsing_ctrl_reg_set( - a_uint32_t dev_id, - union l3_exception_parsing_ctrl_reg_u *value); - -sw_error_t -hppe_l4_exception_parsing_ctrl_0_reg_get( - a_uint32_t dev_id, - union l4_exception_parsing_ctrl_0_reg_u *value); - -sw_error_t -hppe_l4_exception_parsing_ctrl_0_reg_set( - a_uint32_t dev_id, - union l4_exception_parsing_ctrl_0_reg_u *value); - -sw_error_t -hppe_l4_exception_parsing_ctrl_1_reg_get( - a_uint32_t dev_id, - union l4_exception_parsing_ctrl_1_reg_u *value); - -sw_error_t -hppe_l4_exception_parsing_ctrl_1_reg_set( - a_uint32_t dev_id, - union l4_exception_parsing_ctrl_1_reg_u *value); - -sw_error_t -hppe_l4_exception_parsing_ctrl_2_reg_get( - a_uint32_t dev_id, - union l4_exception_parsing_ctrl_2_reg_u *value); - -sw_error_t -hppe_l4_exception_parsing_ctrl_2_reg_set( - a_uint32_t dev_id, - union l4_exception_parsing_ctrl_2_reg_u *value); - -sw_error_t -hppe_l4_exception_parsing_ctrl_3_reg_get( - a_uint32_t dev_id, - union l4_exception_parsing_ctrl_3_reg_u *value); - -sw_error_t -hppe_l4_exception_parsing_ctrl_3_reg_set( - a_uint32_t dev_id, - union l4_exception_parsing_ctrl_3_reg_u *value); - -sw_error_t -hppe_l3_exception_parsing_ctrl_reg_small_hop_limit_get( - a_uint32_t dev_id, - unsigned int *value); - -sw_error_t -hppe_l3_exception_parsing_ctrl_reg_small_hop_limit_set( - a_uint32_t dev_id, - unsigned int value); - -sw_error_t -hppe_l3_exception_parsing_ctrl_reg_small_ttl_get( - a_uint32_t dev_id, - unsigned int *value); - -sw_error_t -hppe_l3_exception_parsing_ctrl_reg_small_ttl_set( - a_uint32_t dev_id, - unsigned int value); - -sw_error_t -hppe_l4_exception_parsing_ctrl_0_reg_tcp_flags0_get( - a_uint32_t dev_id, - unsigned int *value); - -sw_error_t -hppe_l4_exception_parsing_ctrl_0_reg_tcp_flags0_set( - a_uint32_t dev_id, - unsigned int value); - -sw_error_t -hppe_l4_exception_parsing_ctrl_0_reg_tcp_flags0_mask_get( - a_uint32_t dev_id, - unsigned int *value); - -sw_error_t -hppe_l4_exception_parsing_ctrl_0_reg_tcp_flags0_mask_set( - a_uint32_t dev_id, - unsigned int value); - -sw_error_t -hppe_l4_exception_parsing_ctrl_0_reg_tcp_flags1_get( - a_uint32_t dev_id, - unsigned int *value); - -sw_error_t -hppe_l4_exception_parsing_ctrl_0_reg_tcp_flags1_set( - a_uint32_t dev_id, - unsigned int value); - -sw_error_t -hppe_l4_exception_parsing_ctrl_0_reg_tcp_flags1_mask_get( - a_uint32_t dev_id, - unsigned int *value); - -sw_error_t -hppe_l4_exception_parsing_ctrl_0_reg_tcp_flags1_mask_set( - a_uint32_t dev_id, - unsigned int value); - -sw_error_t -hppe_l4_exception_parsing_ctrl_1_reg_tcp_flags2_get( - a_uint32_t dev_id, - unsigned int *value); - -sw_error_t -hppe_l4_exception_parsing_ctrl_1_reg_tcp_flags2_set( - a_uint32_t dev_id, - unsigned int value); - -sw_error_t -hppe_l4_exception_parsing_ctrl_1_reg_tcp_flags2_mask_get( - a_uint32_t dev_id, - unsigned int *value); - -sw_error_t -hppe_l4_exception_parsing_ctrl_1_reg_tcp_flags2_mask_set( - a_uint32_t dev_id, - unsigned int value); - -sw_error_t -hppe_l4_exception_parsing_ctrl_1_reg_tcp_flags3_get( - a_uint32_t dev_id, - unsigned int *value); - -sw_error_t -hppe_l4_exception_parsing_ctrl_1_reg_tcp_flags3_set( - a_uint32_t dev_id, - unsigned int value); - -sw_error_t -hppe_l4_exception_parsing_ctrl_1_reg_tcp_flags3_mask_get( - a_uint32_t dev_id, - unsigned int *value); - -sw_error_t -hppe_l4_exception_parsing_ctrl_1_reg_tcp_flags3_mask_set( - a_uint32_t dev_id, - unsigned int value); - -sw_error_t -hppe_l4_exception_parsing_ctrl_2_reg_tcp_flags4_get( - a_uint32_t dev_id, - unsigned int *value); - -sw_error_t -hppe_l4_exception_parsing_ctrl_2_reg_tcp_flags4_set( - a_uint32_t dev_id, - unsigned int value); - -sw_error_t -hppe_l4_exception_parsing_ctrl_2_reg_tcp_flags4_mask_get( - a_uint32_t dev_id, - unsigned int *value); - -sw_error_t -hppe_l4_exception_parsing_ctrl_2_reg_tcp_flags4_mask_set( - a_uint32_t dev_id, - unsigned int value); - -sw_error_t -hppe_l4_exception_parsing_ctrl_2_reg_tcp_flags5_get( - a_uint32_t dev_id, - unsigned int *value); - -sw_error_t -hppe_l4_exception_parsing_ctrl_2_reg_tcp_flags5_set( - a_uint32_t dev_id, - unsigned int value); - -sw_error_t -hppe_l4_exception_parsing_ctrl_2_reg_tcp_flags5_mask_get( - a_uint32_t dev_id, - unsigned int *value); - -sw_error_t -hppe_l4_exception_parsing_ctrl_2_reg_tcp_flags5_mask_set( - a_uint32_t dev_id, - unsigned int value); - -sw_error_t -hppe_l4_exception_parsing_ctrl_3_reg_tcp_flags6_get( - a_uint32_t dev_id, - unsigned int *value); - -sw_error_t -hppe_l4_exception_parsing_ctrl_3_reg_tcp_flags6_set( - a_uint32_t dev_id, - unsigned int value); - -sw_error_t -hppe_l4_exception_parsing_ctrl_3_reg_tcp_flags6_mask_get( - a_uint32_t dev_id, - unsigned int *value); - -sw_error_t -hppe_l4_exception_parsing_ctrl_3_reg_tcp_flags6_mask_set( - a_uint32_t dev_id, - unsigned int value); - -sw_error_t -hppe_l4_exception_parsing_ctrl_3_reg_tcp_flags7_get( - a_uint32_t dev_id, - unsigned int *value); - -sw_error_t -hppe_l4_exception_parsing_ctrl_3_reg_tcp_flags7_set( - a_uint32_t dev_id, - unsigned int value); - -sw_error_t -hppe_l4_exception_parsing_ctrl_3_reg_tcp_flags7_mask_get( - a_uint32_t dev_id, - unsigned int *value); - -sw_error_t -hppe_l4_exception_parsing_ctrl_3_reg_tcp_flags7_mask_set( - a_uint32_t dev_id, - unsigned int value); - -#endif diff --git a/feeds/ipq807x/qca-ssdk/src/include/hsl/hppe/hppe_sec_reg.h b/feeds/ipq807x/qca-ssdk/src/include/hsl/hppe/hppe_sec_reg.h deleted file mode 100755 index d2ab84109..000000000 --- a/feeds/ipq807x/qca-ssdk/src/include/hsl/hppe/hppe_sec_reg.h +++ /dev/null @@ -1,373 +0,0 @@ -/* - * Copyright (c) 2016-2017, The Linux Foundation. All rights reserved. - * Permission to use, copy, modify, and/or distribute this software for - * any purpose with or without fee is hereby granted, provided that the - * above copyright notice and this permission notice appear in all copies. - * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES - * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR - * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES - * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN - * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT - * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. - */ - - -/** - * @defgroup - * @{ - */ -#ifndef _HPPE_SEC_REG_H_ -#define _HPPE_SEC_REG_H_ - - -/*[register] L3_EXCEPTION_CMD*/ -#define L3_EXCEPTION_CMD -#define L3_EXCEPTION_CMD_ADDRESS 0x544 -#define L3_EXCEPTION_CMD_NUM 72 -#define L3_EXCEPTION_CMD_INC 0x4 -#define L3_EXCEPTION_CMD_TYPE REG_TYPE_RW -#define L3_EXCEPTION_CMD_DEFAULT 0x0 - /*[field] L3_EXCEP_CMD*/ - #define L3_EXCEPTION_CMD_L3_EXCEP_CMD - #define L3_EXCEPTION_CMD_L3_EXCEP_CMD_OFFSET 0 - #define L3_EXCEPTION_CMD_L3_EXCEP_CMD_LEN 2 - #define L3_EXCEPTION_CMD_L3_EXCEP_CMD_DEFAULT 0x0 - /*[field] DE_ACCE*/ - #define L3_EXCEPTION_CMD_DE_ACCE - #define L3_EXCEPTION_CMD_DE_ACCE_OFFSET 2 - #define L3_EXCEPTION_CMD_DE_ACCE_LEN 1 - #define L3_EXCEPTION_CMD_DE_ACCE_DEFAULT 0x0 - -struct l3_exception_cmd { - a_uint32_t l3_excep_cmd:2; - a_uint32_t de_acce:1; - a_uint32_t _reserved0:29; -}; - -union l3_exception_cmd_u { - a_uint32_t val; - struct l3_exception_cmd bf; -}; - -/*[register] L3_EXP_L3_ONLY_CTRL*/ -#define L3_EXP_L3_ONLY_CTRL -#define L3_EXP_L3_ONLY_CTRL_ADDRESS 0x664 -#define L3_EXP_L3_ONLY_CTRL_NUM 72 -#define L3_EXP_L3_ONLY_CTRL_INC 0x4 -#define L3_EXP_L3_ONLY_CTRL_TYPE REG_TYPE_RW -#define L3_EXP_L3_ONLY_CTRL_DEFAULT 0x0 - /*[field] EXCEP_EN*/ - #define L3_EXP_L3_ONLY_CTRL_EXCEP_EN - #define L3_EXP_L3_ONLY_CTRL_EXCEP_EN_OFFSET 0 - #define L3_EXP_L3_ONLY_CTRL_EXCEP_EN_LEN 1 - #define L3_EXP_L3_ONLY_CTRL_EXCEP_EN_DEFAULT 0x0 - -struct l3_exp_l3_only_ctrl { - a_uint32_t excep_en:1; - a_uint32_t _reserved0:31; -}; - -union l3_exp_l3_only_ctrl_u { - a_uint32_t val; - struct l3_exp_l3_only_ctrl bf; -}; - -/*[register] L3_EXP_L2_ONLY_CTRL*/ -#define L3_EXP_L2_ONLY_CTRL -#define L3_EXP_L2_ONLY_CTRL_ADDRESS 0x784 -#define L3_EXP_L2_ONLY_CTRL_NUM 72 -#define L3_EXP_L2_ONLY_CTRL_INC 0x4 -#define L3_EXP_L2_ONLY_CTRL_TYPE REG_TYPE_RW -#define L3_EXP_L2_ONLY_CTRL_DEFAULT 0x0 - /*[field] EXCEP_EN*/ - #define L3_EXP_L2_ONLY_CTRL_EXCEP_EN - #define L3_EXP_L2_ONLY_CTRL_EXCEP_EN_OFFSET 0 - #define L3_EXP_L2_ONLY_CTRL_EXCEP_EN_LEN 1 - #define L3_EXP_L2_ONLY_CTRL_EXCEP_EN_DEFAULT 0x0 - -struct l3_exp_l2_only_ctrl { - a_uint32_t excep_en:1; - a_uint32_t _reserved0:31; -}; - -union l3_exp_l2_only_ctrl_u { - a_uint32_t val; - struct l3_exp_l2_only_ctrl bf; -}; - -/*[register] L3_EXP_L2_FLOW_CTRL*/ -#define L3_EXP_L2_FLOW_CTRL -#define L3_EXP_L2_FLOW_CTRL_ADDRESS 0x8a4 -#define L3_EXP_L2_FLOW_CTRL_NUM 72 -#define L3_EXP_L2_FLOW_CTRL_INC 0x4 -#define L3_EXP_L2_FLOW_CTRL_TYPE REG_TYPE_RW -#define L3_EXP_L2_FLOW_CTRL_DEFAULT 0x0 - /*[field] EXCEP_EN*/ - #define L3_EXP_L2_FLOW_CTRL_EXCEP_EN - #define L3_EXP_L2_FLOW_CTRL_EXCEP_EN_OFFSET 0 - #define L3_EXP_L2_FLOW_CTRL_EXCEP_EN_LEN 1 - #define L3_EXP_L2_FLOW_CTRL_EXCEP_EN_DEFAULT 0x0 - -struct l3_exp_l2_flow_ctrl { - a_uint32_t excep_en:1; - a_uint32_t _reserved0:31; -}; - -union l3_exp_l2_flow_ctrl_u { - a_uint32_t val; - struct l3_exp_l2_flow_ctrl bf; -}; - -/*[register] L3_EXP_L3_FLOW_CTRL*/ -#define L3_EXP_L3_FLOW_CTRL -#define L3_EXP_L3_FLOW_CTRL_ADDRESS 0x9c4 -#define L3_EXP_L3_FLOW_CTRL_NUM 72 -#define L3_EXP_L3_FLOW_CTRL_INC 0x4 -#define L3_EXP_L3_FLOW_CTRL_TYPE REG_TYPE_RW -#define L3_EXP_L3_FLOW_CTRL_DEFAULT 0x0 - /*[field] EXCEP_EN*/ - #define L3_EXP_L3_FLOW_CTRL_EXCEP_EN - #define L3_EXP_L3_FLOW_CTRL_EXCEP_EN_OFFSET 0 - #define L3_EXP_L3_FLOW_CTRL_EXCEP_EN_LEN 1 - #define L3_EXP_L3_FLOW_CTRL_EXCEP_EN_DEFAULT 0x0 - -struct l3_exp_l3_flow_ctrl { - a_uint32_t excep_en:1; - a_uint32_t _reserved0:31; -}; - -union l3_exp_l3_flow_ctrl_u { - a_uint32_t val; - struct l3_exp_l3_flow_ctrl bf; -}; - -/*[register] L3_EXP_MULTICAST_CTRL*/ -#define L3_EXP_MULTICAST_CTRL -#define L3_EXP_MULTICAST_CTRL_ADDRESS 0xae4 -#define L3_EXP_MULTICAST_CTRL_NUM 72 -#define L3_EXP_MULTICAST_CTRL_INC 0x4 -#define L3_EXP_MULTICAST_CTRL_TYPE REG_TYPE_RW -#define L3_EXP_MULTICAST_CTRL_DEFAULT 0x0 - /*[field] EXCEP_EN*/ - #define L3_EXP_MULTICAST_CTRL_EXCEP_EN - #define L3_EXP_MULTICAST_CTRL_EXCEP_EN_OFFSET 0 - #define L3_EXP_MULTICAST_CTRL_EXCEP_EN_LEN 1 - #define L3_EXP_MULTICAST_CTRL_EXCEP_EN_DEFAULT 0x0 - -struct l3_exp_multicast_ctrl { - a_uint32_t excep_en:1; - a_uint32_t _reserved0:31; -}; - -union l3_exp_multicast_ctrl_u { - a_uint32_t val; - struct l3_exp_multicast_ctrl bf; -}; - -/*[register] L3_EXCEPTION_PARSING_CTRL_REG*/ -#define L3_EXCEPTION_PARSING_CTRL_REG -#define L3_EXCEPTION_PARSING_CTRL_REG_ADDRESS 0x24 -#define L3_EXCEPTION_PARSING_CTRL_REG_NUM 1 -#define L3_EXCEPTION_PARSING_CTRL_REG_INC 0x4 -#define L3_EXCEPTION_PARSING_CTRL_REG_TYPE REG_TYPE_RW -#define L3_EXCEPTION_PARSING_CTRL_REG_DEFAULT 0x0 - /*[field] SMALL_TTL*/ - #define L3_EXCEPTION_PARSING_CTRL_REG_SMALL_TTL - #define L3_EXCEPTION_PARSING_CTRL_REG_SMALL_TTL_OFFSET 0 - #define L3_EXCEPTION_PARSING_CTRL_REG_SMALL_TTL_LEN 8 - #define L3_EXCEPTION_PARSING_CTRL_REG_SMALL_TTL_DEFAULT 0x0 - /*[field] SMALL_HOP_LIMIT*/ - #define L3_EXCEPTION_PARSING_CTRL_REG_SMALL_HOP_LIMIT - #define L3_EXCEPTION_PARSING_CTRL_REG_SMALL_HOP_LIMIT_OFFSET 8 - #define L3_EXCEPTION_PARSING_CTRL_REG_SMALL_HOP_LIMIT_LEN 8 - #define L3_EXCEPTION_PARSING_CTRL_REG_SMALL_HOP_LIMIT_DEFAULT 0x0 - -struct l3_exception_parsing_ctrl_reg { - a_uint32_t small_ttl:8; - a_uint32_t small_hop_limit:8; - a_uint32_t _reserved0:16; -}; - -union l3_exception_parsing_ctrl_reg_u { - a_uint32_t val; - struct l3_exception_parsing_ctrl_reg bf; -}; - -/*[register] L4_EXCEPTION_PARSING_CTRL_0_REG*/ -#define L4_EXCEPTION_PARSING_CTRL_0_REG -#define L4_EXCEPTION_PARSING_CTRL_0_REG_ADDRESS 0x28 -#define L4_EXCEPTION_PARSING_CTRL_0_REG_NUM 1 -#define L4_EXCEPTION_PARSING_CTRL_0_REG_INC 0x4 -#define L4_EXCEPTION_PARSING_CTRL_0_REG_TYPE REG_TYPE_RW -#define L4_EXCEPTION_PARSING_CTRL_0_REG_DEFAULT 0x0 - /*[field] TCP_FLAGS0*/ - #define L4_EXCEPTION_PARSING_CTRL_0_REG_TCP_FLAGS0 - #define L4_EXCEPTION_PARSING_CTRL_0_REG_TCP_FLAGS0_OFFSET 0 - #define L4_EXCEPTION_PARSING_CTRL_0_REG_TCP_FLAGS0_LEN 6 - #define L4_EXCEPTION_PARSING_CTRL_0_REG_TCP_FLAGS0_DEFAULT 0x0 - /*[field] TCP_FLAGS0_MASK*/ - #define L4_EXCEPTION_PARSING_CTRL_0_REG_TCP_FLAGS0_MASK - #define L4_EXCEPTION_PARSING_CTRL_0_REG_TCP_FLAGS0_MASK_OFFSET 8 - #define L4_EXCEPTION_PARSING_CTRL_0_REG_TCP_FLAGS0_MASK_LEN 6 - #define L4_EXCEPTION_PARSING_CTRL_0_REG_TCP_FLAGS0_MASK_DEFAULT 0x0 - /*[field] TCP_FLAGS1*/ - #define L4_EXCEPTION_PARSING_CTRL_0_REG_TCP_FLAGS1 - #define L4_EXCEPTION_PARSING_CTRL_0_REG_TCP_FLAGS1_OFFSET 16 - #define L4_EXCEPTION_PARSING_CTRL_0_REG_TCP_FLAGS1_LEN 6 - #define L4_EXCEPTION_PARSING_CTRL_0_REG_TCP_FLAGS1_DEFAULT 0x0 - /*[field] TCP_FLAGS1_MASK*/ - #define L4_EXCEPTION_PARSING_CTRL_0_REG_TCP_FLAGS1_MASK - #define L4_EXCEPTION_PARSING_CTRL_0_REG_TCP_FLAGS1_MASK_OFFSET 24 - #define L4_EXCEPTION_PARSING_CTRL_0_REG_TCP_FLAGS1_MASK_LEN 6 - #define L4_EXCEPTION_PARSING_CTRL_0_REG_TCP_FLAGS1_MASK_DEFAULT 0x0 - -struct l4_exception_parsing_ctrl_0_reg { - a_uint32_t tcp_flags0:6; - a_uint32_t _reserved0:2; - a_uint32_t tcp_flags0_mask:6; - a_uint32_t _reserved1:2; - a_uint32_t tcp_flags1:6; - a_uint32_t _reserved2:2; - a_uint32_t tcp_flags1_mask:6; - a_uint32_t _reserved3:2; -}; - -union l4_exception_parsing_ctrl_0_reg_u { - a_uint32_t val; - struct l4_exception_parsing_ctrl_0_reg bf; -}; - -/*[register] L4_EXCEPTION_PARSING_CTRL_1_REG*/ -#define L4_EXCEPTION_PARSING_CTRL_1_REG -#define L4_EXCEPTION_PARSING_CTRL_1_REG_ADDRESS 0x2c -#define L4_EXCEPTION_PARSING_CTRL_1_REG_NUM 1 -#define L4_EXCEPTION_PARSING_CTRL_1_REG_INC 0x4 -#define L4_EXCEPTION_PARSING_CTRL_1_REG_TYPE REG_TYPE_RW -#define L4_EXCEPTION_PARSING_CTRL_1_REG_DEFAULT 0x0 - /*[field] TCP_FLAGS2*/ - #define L4_EXCEPTION_PARSING_CTRL_1_REG_TCP_FLAGS2 - #define L4_EXCEPTION_PARSING_CTRL_1_REG_TCP_FLAGS2_OFFSET 0 - #define L4_EXCEPTION_PARSING_CTRL_1_REG_TCP_FLAGS2_LEN 6 - #define L4_EXCEPTION_PARSING_CTRL_1_REG_TCP_FLAGS2_DEFAULT 0x0 - /*[field] TCP_FLAGS2_MASK*/ - #define L4_EXCEPTION_PARSING_CTRL_1_REG_TCP_FLAGS2_MASK - #define L4_EXCEPTION_PARSING_CTRL_1_REG_TCP_FLAGS2_MASK_OFFSET 8 - #define L4_EXCEPTION_PARSING_CTRL_1_REG_TCP_FLAGS2_MASK_LEN 6 - #define L4_EXCEPTION_PARSING_CTRL_1_REG_TCP_FLAGS2_MASK_DEFAULT 0x0 - /*[field] TCP_FLAGS3*/ - #define L4_EXCEPTION_PARSING_CTRL_1_REG_TCP_FLAGS3 - #define L4_EXCEPTION_PARSING_CTRL_1_REG_TCP_FLAGS3_OFFSET 16 - #define L4_EXCEPTION_PARSING_CTRL_1_REG_TCP_FLAGS3_LEN 6 - #define L4_EXCEPTION_PARSING_CTRL_1_REG_TCP_FLAGS3_DEFAULT 0x0 - /*[field] TCP_FLAGS3_MASK*/ - #define L4_EXCEPTION_PARSING_CTRL_1_REG_TCP_FLAGS3_MASK - #define L4_EXCEPTION_PARSING_CTRL_1_REG_TCP_FLAGS3_MASK_OFFSET 24 - #define L4_EXCEPTION_PARSING_CTRL_1_REG_TCP_FLAGS3_MASK_LEN 6 - #define L4_EXCEPTION_PARSING_CTRL_1_REG_TCP_FLAGS3_MASK_DEFAULT 0x0 - -struct l4_exception_parsing_ctrl_1_reg { - a_uint32_t tcp_flags2:6; - a_uint32_t _reserved0:2; - a_uint32_t tcp_flags2_mask:6; - a_uint32_t _reserved1:2; - a_uint32_t tcp_flags3:6; - a_uint32_t _reserved2:2; - a_uint32_t tcp_flags3_mask:6; - a_uint32_t _reserved3:2; -}; - -union l4_exception_parsing_ctrl_1_reg_u { - a_uint32_t val; - struct l4_exception_parsing_ctrl_1_reg bf; -}; - -/*[register] L4_EXCEPTION_PARSING_CTRL_2_REG*/ -#define L4_EXCEPTION_PARSING_CTRL_2_REG -#define L4_EXCEPTION_PARSING_CTRL_2_REG_ADDRESS 0x30 -#define L4_EXCEPTION_PARSING_CTRL_2_REG_NUM 1 -#define L4_EXCEPTION_PARSING_CTRL_2_REG_INC 0x4 -#define L4_EXCEPTION_PARSING_CTRL_2_REG_TYPE REG_TYPE_RW -#define L4_EXCEPTION_PARSING_CTRL_2_REG_DEFAULT 0x0 - /*[field] TCP_FLAGS4*/ - #define L4_EXCEPTION_PARSING_CTRL_2_REG_TCP_FLAGS4 - #define L4_EXCEPTION_PARSING_CTRL_2_REG_TCP_FLAGS4_OFFSET 0 - #define L4_EXCEPTION_PARSING_CTRL_2_REG_TCP_FLAGS4_LEN 6 - #define L4_EXCEPTION_PARSING_CTRL_2_REG_TCP_FLAGS4_DEFAULT 0x0 - /*[field] TCP_FLAGS4_MASK*/ - #define L4_EXCEPTION_PARSING_CTRL_2_REG_TCP_FLAGS4_MASK - #define L4_EXCEPTION_PARSING_CTRL_2_REG_TCP_FLAGS4_MASK_OFFSET 8 - #define L4_EXCEPTION_PARSING_CTRL_2_REG_TCP_FLAGS4_MASK_LEN 6 - #define L4_EXCEPTION_PARSING_CTRL_2_REG_TCP_FLAGS4_MASK_DEFAULT 0x0 - /*[field] TCP_FLAGS5*/ - #define L4_EXCEPTION_PARSING_CTRL_2_REG_TCP_FLAGS5 - #define L4_EXCEPTION_PARSING_CTRL_2_REG_TCP_FLAGS5_OFFSET 16 - #define L4_EXCEPTION_PARSING_CTRL_2_REG_TCP_FLAGS5_LEN 6 - #define L4_EXCEPTION_PARSING_CTRL_2_REG_TCP_FLAGS5_DEFAULT 0x0 - /*[field] TCP_FLAGS5_MASK*/ - #define L4_EXCEPTION_PARSING_CTRL_2_REG_TCP_FLAGS5_MASK - #define L4_EXCEPTION_PARSING_CTRL_2_REG_TCP_FLAGS5_MASK_OFFSET 24 - #define L4_EXCEPTION_PARSING_CTRL_2_REG_TCP_FLAGS5_MASK_LEN 6 - #define L4_EXCEPTION_PARSING_CTRL_2_REG_TCP_FLAGS5_MASK_DEFAULT 0x0 - -struct l4_exception_parsing_ctrl_2_reg { - a_uint32_t tcp_flags4:6; - a_uint32_t _reserved0:2; - a_uint32_t tcp_flags4_mask:6; - a_uint32_t _reserved1:2; - a_uint32_t tcp_flags5:6; - a_uint32_t _reserved2:2; - a_uint32_t tcp_flags5_mask:6; - a_uint32_t _reserved3:2; -}; - -union l4_exception_parsing_ctrl_2_reg_u { - a_uint32_t val; - struct l4_exception_parsing_ctrl_2_reg bf; -}; - -/*[register] L4_EXCEPTION_PARSING_CTRL_3_REG*/ -#define L4_EXCEPTION_PARSING_CTRL_3_REG -#define L4_EXCEPTION_PARSING_CTRL_3_REG_ADDRESS 0x34 -#define L4_EXCEPTION_PARSING_CTRL_3_REG_NUM 1 -#define L4_EXCEPTION_PARSING_CTRL_3_REG_INC 0x4 -#define L4_EXCEPTION_PARSING_CTRL_3_REG_TYPE REG_TYPE_RW -#define L4_EXCEPTION_PARSING_CTRL_3_REG_DEFAULT 0x0 - /*[field] TCP_FLAGS6*/ - #define L4_EXCEPTION_PARSING_CTRL_3_REG_TCP_FLAGS6 - #define L4_EXCEPTION_PARSING_CTRL_3_REG_TCP_FLAGS6_OFFSET 0 - #define L4_EXCEPTION_PARSING_CTRL_3_REG_TCP_FLAGS6_LEN 6 - #define L4_EXCEPTION_PARSING_CTRL_3_REG_TCP_FLAGS6_DEFAULT 0x0 - /*[field] TCP_FLAGS6_MASK*/ - #define L4_EXCEPTION_PARSING_CTRL_3_REG_TCP_FLAGS6_MASK - #define L4_EXCEPTION_PARSING_CTRL_3_REG_TCP_FLAGS6_MASK_OFFSET 8 - #define L4_EXCEPTION_PARSING_CTRL_3_REG_TCP_FLAGS6_MASK_LEN 6 - #define L4_EXCEPTION_PARSING_CTRL_3_REG_TCP_FLAGS6_MASK_DEFAULT 0x0 - /*[field] TCP_FLAGS7*/ - #define L4_EXCEPTION_PARSING_CTRL_3_REG_TCP_FLAGS7 - #define L4_EXCEPTION_PARSING_CTRL_3_REG_TCP_FLAGS7_OFFSET 16 - #define L4_EXCEPTION_PARSING_CTRL_3_REG_TCP_FLAGS7_LEN 6 - #define L4_EXCEPTION_PARSING_CTRL_3_REG_TCP_FLAGS7_DEFAULT 0x0 - /*[field] TCP_FLAGS7_MASK*/ - #define L4_EXCEPTION_PARSING_CTRL_3_REG_TCP_FLAGS7_MASK - #define L4_EXCEPTION_PARSING_CTRL_3_REG_TCP_FLAGS7_MASK_OFFSET 24 - #define L4_EXCEPTION_PARSING_CTRL_3_REG_TCP_FLAGS7_MASK_LEN 6 - #define L4_EXCEPTION_PARSING_CTRL_3_REG_TCP_FLAGS7_MASK_DEFAULT 0x0 - -struct l4_exception_parsing_ctrl_3_reg { - a_uint32_t tcp_flags6:6; - a_uint32_t _reserved0:2; - a_uint32_t tcp_flags6_mask:6; - a_uint32_t _reserved1:2; - a_uint32_t tcp_flags7:6; - a_uint32_t _reserved2:2; - a_uint32_t tcp_flags7_mask:6; - a_uint32_t _reserved3:2; -}; - -union l4_exception_parsing_ctrl_3_reg_u { - a_uint32_t val; - struct l4_exception_parsing_ctrl_3_reg bf; -}; - -#endif diff --git a/feeds/ipq807x/qca-ssdk/src/include/hsl/hppe/hppe_servcode.h b/feeds/ipq807x/qca-ssdk/src/include/hsl/hppe/hppe_servcode.h deleted file mode 100755 index bbeda36dc..000000000 --- a/feeds/ipq807x/qca-ssdk/src/include/hsl/hppe/hppe_servcode.h +++ /dev/null @@ -1,220 +0,0 @@ -/* - * Copyright (c) 2016-2017, The Linux Foundation. All rights reserved. - * Permission to use, copy, modify, and/or distribute this software for - * any purpose with or without fee is hereby granted, provided that the - * above copyright notice and this permission notice appear in all copies. - * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES - * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR - * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES - * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN - * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT - * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. - */ - - -/** - * @defgroup - * @{ - */ -#ifndef _HPPE_SERVCODE_H_ -#define _HPPE_SERVCODE_H_ - -#define IN_L2_SERVICE_TBL_MAX_ENTRY 256 -#define EG_SERVICE_TBL_MAX_ENTRY 256 - -sw_error_t -hppe_service_tbl_get( - a_uint32_t dev_id, - a_uint32_t index, - union service_tbl_u *value); - -sw_error_t -hppe_service_tbl_set( - a_uint32_t dev_id, - a_uint32_t index, - union service_tbl_u *value); - -sw_error_t -hppe_service_tbl_rx_counting_en_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_service_tbl_rx_counting_en_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_service_tbl_bypass_bitmap_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_service_tbl_bypass_bitmap_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_in_l2_service_tbl_get( - a_uint32_t dev_id, - a_uint32_t index, - union in_l2_service_tbl_u *value); - -sw_error_t -hppe_in_l2_service_tbl_set( - a_uint32_t dev_id, - a_uint32_t index, - union in_l2_service_tbl_u *value); - -sw_error_t -hppe_in_l2_service_tbl_direction_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_in_l2_service_tbl_direction_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_in_l2_service_tbl_rx_cnt_en_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_in_l2_service_tbl_rx_cnt_en_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_in_l2_service_tbl_tx_cnt_en_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_in_l2_service_tbl_tx_cnt_en_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_in_l2_service_tbl_bypass_bitmap_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_in_l2_service_tbl_bypass_bitmap_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_in_l2_service_tbl_dst_port_id_valid_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_in_l2_service_tbl_dst_port_id_valid_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_in_l2_service_tbl_dst_port_id_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_in_l2_service_tbl_dst_port_id_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - - sw_error_t -hppe_eg_service_tbl_next_service_code_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_eg_service_tbl_next_service_code_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_eg_service_tbl_tx_counting_en_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_eg_service_tbl_tx_counting_en_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_eg_service_tbl_field_update_action_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_eg_service_tbl_field_update_action_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_eg_service_tbl_offset_sel_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_eg_service_tbl_offset_sel_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_eg_service_tbl_hw_services_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_eg_service_tbl_hw_services_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_eg_service_tbl_set( - a_uint32_t dev_id, - a_uint32_t index, - union eg_service_tbl_u *value); - -sw_error_t -hppe_eg_service_tbl_get( - a_uint32_t dev_id, - a_uint32_t index, - union eg_service_tbl_u *value); - - -#endif - diff --git a/feeds/ipq807x/qca-ssdk/src/include/hsl/hppe/hppe_servcode_reg.h b/feeds/ipq807x/qca-ssdk/src/include/hsl/hppe/hppe_servcode_reg.h deleted file mode 100755 index 82f794b9f..000000000 --- a/feeds/ipq807x/qca-ssdk/src/include/hsl/hppe/hppe_servcode_reg.h +++ /dev/null @@ -1,150 +0,0 @@ -/* - * Copyright (c) 2016-2017, The Linux Foundation. All rights reserved. - * Permission to use, copy, modify, and/or distribute this software for - * any purpose with or without fee is hereby granted, provided that the - * above copyright notice and this permission notice appear in all copies. - * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES - * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR - * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES - * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN - * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT - * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. - */ - - -/** - * @defgroup - * @{ - */ -#ifndef HPPE_SERVCODE_REG_H -#define HPPE_SERVCODE_REG_H - -/*[table] SERVICE_TBL*/ -#define SERVICE_TBL -#define SERVICE_TBL_ADDRESS 0x6000 -#define SERVICE_TBL_NUM 256 -#define SERVICE_TBL_INC 0x10 -#define SERVICE_TBL_TYPE REG_TYPE_RW -#define SERVICE_TBL_DEFAULT 0x0 - /*[field] BYPASS_BITMAP*/ - #define SERVICE_TBL_BYPASS_BITMAP - #define SERVICE_TBL_BYPASS_BITMAP_OFFSET 0 - #define SERVICE_TBL_BYPASS_BITMAP_LEN 32 - #define SERVICE_TBL_BYPASS_BITMAP_DEFAULT 0x0 - /*[field] RX_COUNTING_EN*/ - #define SERVICE_TBL_RX_COUNTING_EN - #define SERVICE_TBL_RX_COUNTING_EN_OFFSET 32 - #define SERVICE_TBL_RX_COUNTING_EN_LEN 1 - #define SERVICE_TBL_RX_COUNTING_EN_DEFAULT 0x0 - -struct service_tbl { - a_uint32_t bypass_bitmap:32; - a_uint32_t rx_counting_en:1; - a_uint32_t _reserved0:31; -}; - -union service_tbl_u { - a_uint32_t val[2]; - struct service_tbl bf; -}; - -/*[table] IN_L2_SERVICE_TBL*/ -#define IN_L2_SERVICE_TBL -#define IN_L2_SERVICE_TBL_ADDRESS 0x4000 -#define IN_L2_SERVICE_TBL_NUM 256 -#define IN_L2_SERVICE_TBL_INC 0x10 -#define IN_L2_SERVICE_TBL_TYPE REG_TYPE_RW -#define IN_L2_SERVICE_TBL_DEFAULT 0x0 - /*[field] DST_PORT_ID_VALID*/ - #define IN_L2_SERVICE_TBL_DST_PORT_ID_VALID - #define IN_L2_SERVICE_TBL_DST_PORT_ID_VALID_OFFSET 0 - #define IN_L2_SERVICE_TBL_DST_PORT_ID_VALID_LEN 1 - #define IN_L2_SERVICE_TBL_DST_PORT_ID_VALID_DEFAULT 0x0 - /*[field] DST_PORT_ID*/ - #define IN_L2_SERVICE_TBL_DST_PORT_ID - #define IN_L2_SERVICE_TBL_DST_PORT_ID_OFFSET 1 - #define IN_L2_SERVICE_TBL_DST_PORT_ID_LEN 4 - #define IN_L2_SERVICE_TBL_DST_PORT_ID_DEFAULT 0x0 - /*[field] DIRECTION*/ - #define IN_L2_SERVICE_TBL_DIRECTION - #define IN_L2_SERVICE_TBL_DIRECTION_OFFSET 5 - #define IN_L2_SERVICE_TBL_DIRECTION_LEN 1 - #define IN_L2_SERVICE_TBL_DIRECTION_DEFAULT 0x0 - /*[field] BYPASS_BITMAP*/ - #define IN_L2_SERVICE_TBL_BYPASS_BITMAP - #define IN_L2_SERVICE_TBL_BYPASS_BITMAP_OFFSET 6 - #define IN_L2_SERVICE_TBL_BYPASS_BITMAP_LEN 24 - #define IN_L2_SERVICE_TBL_BYPASS_BITMAP_DEFAULT 0x0 - /*[field] RX_CNT_EN*/ - #define IN_L2_SERVICE_TBL_RX_CNT_EN - #define IN_L2_SERVICE_TBL_RX_CNT_EN_OFFSET 30 - #define IN_L2_SERVICE_TBL_RX_CNT_EN_LEN 1 - #define IN_L2_SERVICE_TBL_RX_CNT_EN_DEFAULT 0x0 - /*[field] TX_CNT_EN*/ - #define IN_L2_SERVICE_TBL_TX_CNT_EN - #define IN_L2_SERVICE_TBL_TX_CNT_EN_OFFSET 31 - #define IN_L2_SERVICE_TBL_TX_CNT_EN_LEN 1 - #define IN_L2_SERVICE_TBL_TX_CNT_EN_DEFAULT 0x0 - -struct in_l2_service_tbl { - a_uint32_t dst_port_id_valid:1; - a_uint32_t dst_port_id:4; - a_uint32_t direction:1; - a_uint32_t bypass_bitmap:24; - a_uint32_t rx_cnt_en:1; - a_uint32_t tx_cnt_en:1; -}; - -union in_l2_service_tbl_u { - a_uint32_t val; - struct in_l2_service_tbl bf; -}; - -/*[table] EG_SERVICE_TBL*/ -#define EG_SERVICE_TBL -#define EG_SERVICE_TBL_ADDRESS 0xc000 -#define EG_SERVICE_TBL_NUM 256 -#define EG_SERVICE_TBL_INC 0x8 -#define EG_SERVICE_TBL_TYPE REG_TYPE_RW -#define EG_SERVICE_TBL_DEFAULT 0x0 - /*[field] FIELD_UPDATE_ACTION*/ - #define EG_SERVICE_TBL_FIELD_UPDATE_ACTION - #define EG_SERVICE_TBL_FIELD_UPDATE_ACTION_OFFSET 0 - #define EG_SERVICE_TBL_FIELD_UPDATE_ACTION_LEN 32 - #define EG_SERVICE_TBL_FIELD_UPDATE_ACTION_DEFAULT 0x0 - /*[field] NEXT_SERVICE_CODE*/ - #define EG_SERVICE_TBL_NEXT_SERVICE_CODE - #define EG_SERVICE_TBL_NEXT_SERVICE_CODE_OFFSET 32 - #define EG_SERVICE_TBL_NEXT_SERVICE_CODE_LEN 8 - #define EG_SERVICE_TBL_NEXT_SERVICE_CODE_DEFAULT 0x0 - /*[field] HW_SERVICES*/ - #define EG_SERVICE_TBL_HW_SERVICES - #define EG_SERVICE_TBL_HW_SERVICES_OFFSET 40 - #define EG_SERVICE_TBL_HW_SERVICES_LEN 6 - #define EG_SERVICE_TBL_HW_SERVICES_DEFAULT 0x0 - /*[field] OFFSET_SEL*/ - #define EG_SERVICE_TBL_OFFSET_SEL - #define EG_SERVICE_TBL_OFFSET_SEL_OFFSET 46 - #define EG_SERVICE_TBL_OFFSET_SEL_LEN 1 - #define EG_SERVICE_TBL_OFFSET_SEL_DEFAULT 0x0 - /*[field] TX_COUNTING_EN*/ - #define EG_SERVICE_TBL_TX_COUNTING_EN - #define EG_SERVICE_TBL_TX_COUNTING_EN_OFFSET 47 - #define EG_SERVICE_TBL_TX_COUNTING_EN_LEN 1 - #define EG_SERVICE_TBL_TX_COUNTING_EN_DEFAULT 0x0 - -struct eg_service_tbl { - a_uint32_t field_update_action:32; - a_uint32_t next_service_code:8; - a_uint32_t hw_services:6; - a_uint32_t offset_sel:1; - a_uint32_t tx_counting_en:1; - a_uint32_t _reserved0:16; -}; - -union eg_service_tbl_u { - a_uint32_t val[2]; - struct eg_service_tbl bf; -}; -#endif diff --git a/feeds/ipq807x/qca-ssdk/src/include/hsl/hppe/hppe_shaper.h b/feeds/ipq807x/qca-ssdk/src/include/hsl/hppe/hppe_shaper.h deleted file mode 100755 index 4f8c74fd2..000000000 --- a/feeds/ipq807x/qca-ssdk/src/include/hsl/hppe/hppe_shaper.h +++ /dev/null @@ -1,1055 +0,0 @@ -/* - * Copyright (c) 2016-2017, The Linux Foundation. All rights reserved. - * Permission to use, copy, modify, and/or distribute this software for - * any purpose with or without fee is hereby granted, provided that the - * above copyright notice and this permission notice appear in all copies. - * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES - * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR - * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES - * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN - * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT - * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. - */ - - -/** - * @defgroup - * @{ - */ -#ifndef _HPPE_SHAPER_H_ -#define _HPPE_SHAPER_H_ - -#define L0_SHP_CREDIT_TBL_MAX_ENTRY 300 -#define L0_SHP_CFG_TBL_MAX_ENTRY 300 -#define L0_COMP_TBL_MAX_ENTRY 300 -#define L0_COMP_CFG_TBL_MAX_ENTRY 300 -#define L1_SHP_CREDIT_TBL_MAX_ENTRY 64 -#define L1_SHP_CFG_TBL_MAX_ENTRY 64 -#define L1_COMP_TBL_MAX_ENTRY 64 -#define L1_COMP_CFG_TBL_MAX_ENTRY 64 -#define PSCH_SHP_SIGN_TBL_MAX_ENTRY 8 -#define PSCH_SHP_CREDIT_TBL_MAX_ENTRY 8 -#define PSCH_SHP_CFG_TBL_MAX_ENTRY 8 -#define PSCH_COMP_TBL_MAX_ENTRY 8 -#define PSCH_COMP_CFG_TBL_MAX_ENTRY 8 - -sw_error_t -hppe_shp_slot_cfg_l0_get( - a_uint32_t dev_id, - union shp_slot_cfg_l0_u *value); - -sw_error_t -hppe_shp_slot_cfg_l0_set( - a_uint32_t dev_id, - union shp_slot_cfg_l0_u *value); - -sw_error_t -hppe_shp_slot_cfg_l1_get( - a_uint32_t dev_id, - union shp_slot_cfg_l1_u *value); - -sw_error_t -hppe_shp_slot_cfg_l1_set( - a_uint32_t dev_id, - union shp_slot_cfg_l1_u *value); - -sw_error_t -hppe_shp_slot_cfg_port_get( - a_uint32_t dev_id, - union shp_slot_cfg_port_u *value); - -sw_error_t -hppe_shp_slot_cfg_port_set( - a_uint32_t dev_id, - union shp_slot_cfg_port_u *value); - -sw_error_t -hppe_l0_shp_credit_tbl_get( - a_uint32_t dev_id, - a_uint32_t index, - union l0_shp_credit_tbl_u *value); - -sw_error_t -hppe_l0_shp_credit_tbl_set( - a_uint32_t dev_id, - a_uint32_t index, - union l0_shp_credit_tbl_u *value); - -sw_error_t -hppe_l0_shp_cfg_tbl_get( - a_uint32_t dev_id, - a_uint32_t index, - union l0_shp_cfg_tbl_u *value); - -sw_error_t -hppe_l0_shp_cfg_tbl_set( - a_uint32_t dev_id, - a_uint32_t index, - union l0_shp_cfg_tbl_u *value); - -sw_error_t -hppe_l0_comp_tbl_get( - a_uint32_t dev_id, - a_uint32_t index, - union l0_comp_tbl_u *value); - -sw_error_t -hppe_l0_comp_tbl_set( - a_uint32_t dev_id, - a_uint32_t index, - union l0_comp_tbl_u *value); - -sw_error_t -hppe_l0_comp_cfg_tbl_get( - a_uint32_t dev_id, - a_uint32_t index, - union l0_comp_cfg_tbl_u *value); - -sw_error_t -hppe_l0_comp_cfg_tbl_set( - a_uint32_t dev_id, - a_uint32_t index, - union l0_comp_cfg_tbl_u *value); - -sw_error_t -hppe_l1_shp_credit_tbl_get( - a_uint32_t dev_id, - a_uint32_t index, - union l1_shp_credit_tbl_u *value); - -sw_error_t -hppe_l1_shp_credit_tbl_set( - a_uint32_t dev_id, - a_uint32_t index, - union l1_shp_credit_tbl_u *value); - -sw_error_t -hppe_l1_shp_cfg_tbl_get( - a_uint32_t dev_id, - a_uint32_t index, - union l1_shp_cfg_tbl_u *value); - -sw_error_t -hppe_l1_shp_cfg_tbl_set( - a_uint32_t dev_id, - a_uint32_t index, - union l1_shp_cfg_tbl_u *value); - -sw_error_t -hppe_l1_comp_tbl_get( - a_uint32_t dev_id, - a_uint32_t index, - union l1_comp_tbl_u *value); - -sw_error_t -hppe_l1_comp_tbl_set( - a_uint32_t dev_id, - a_uint32_t index, - union l1_comp_tbl_u *value); - -sw_error_t -hppe_l1_comp_cfg_tbl_get( - a_uint32_t dev_id, - a_uint32_t index, - union l1_comp_cfg_tbl_u *value); - -sw_error_t -hppe_l1_comp_cfg_tbl_set( - a_uint32_t dev_id, - a_uint32_t index, - union l1_comp_cfg_tbl_u *value); - -sw_error_t -hppe_psch_shp_sign_tbl_get( - a_uint32_t dev_id, - a_uint32_t index, - union psch_shp_sign_tbl_u *value); - -sw_error_t -hppe_psch_shp_sign_tbl_set( - a_uint32_t dev_id, - a_uint32_t index, - union psch_shp_sign_tbl_u *value); - -sw_error_t -hppe_psch_shp_credit_tbl_get( - a_uint32_t dev_id, - a_uint32_t index, - union psch_shp_credit_tbl_u *value); - -sw_error_t -hppe_psch_shp_credit_tbl_set( - a_uint32_t dev_id, - a_uint32_t index, - union psch_shp_credit_tbl_u *value); - -sw_error_t -hppe_psch_shp_cfg_tbl_get( - a_uint32_t dev_id, - a_uint32_t index, - union psch_shp_cfg_tbl_u *value); - -sw_error_t -hppe_psch_shp_cfg_tbl_set( - a_uint32_t dev_id, - a_uint32_t index, - union psch_shp_cfg_tbl_u *value); - -sw_error_t -hppe_psch_comp_tbl_get( - a_uint32_t dev_id, - a_uint32_t index, - union psch_comp_tbl_u *value); - -sw_error_t -hppe_psch_comp_tbl_set( - a_uint32_t dev_id, - a_uint32_t index, - union psch_comp_tbl_u *value); - -sw_error_t -hppe_psch_comp_cfg_tbl_get( - a_uint32_t dev_id, - a_uint32_t index, - union psch_comp_cfg_tbl_u *value); - -sw_error_t -hppe_psch_comp_cfg_tbl_set( - a_uint32_t dev_id, - a_uint32_t index, - union psch_comp_cfg_tbl_u *value); - -sw_error_t -hppe_ipg_pre_len_cfg_get( - a_uint32_t dev_id, - union ipg_pre_len_cfg_u *value); - -sw_error_t -hppe_ipg_pre_len_cfg_set( - a_uint32_t dev_id, - union ipg_pre_len_cfg_u *value); - -sw_error_t -hppe_ipg_pre_len_cfg_ipg_pre_len_get( - a_uint32_t dev_id, - unsigned int *value); - -sw_error_t -hppe_ipg_pre_len_cfg_ipg_pre_len_set( - a_uint32_t dev_id, - unsigned int value); - -sw_error_t -hppe_shp_slot_cfg_l0_l0_shp_slot_time_get( - a_uint32_t dev_id, - unsigned int *value); - -sw_error_t -hppe_shp_slot_cfg_l0_l0_shp_slot_time_set( - a_uint32_t dev_id, - unsigned int value); - -sw_error_t -hppe_shp_slot_cfg_l1_l1_shp_slot_time_get( - a_uint32_t dev_id, - unsigned int *value); - -sw_error_t -hppe_shp_slot_cfg_l1_l1_shp_slot_time_set( - a_uint32_t dev_id, - unsigned int value); - -sw_error_t -hppe_shp_slot_cfg_port_port_shp_slot_time_get( - a_uint32_t dev_id, - unsigned int *value); - -sw_error_t -hppe_shp_slot_cfg_port_port_shp_slot_time_set( - a_uint32_t dev_id, - unsigned int value); - -sw_error_t -hppe_l0_shp_credit_tbl_e_shaper_credit_neg_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_l0_shp_credit_tbl_e_shaper_credit_neg_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_l0_shp_credit_tbl_e_shaper_credit_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_l0_shp_credit_tbl_e_shaper_credit_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_l0_shp_credit_tbl_c_shaper_credit_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_l0_shp_credit_tbl_c_shaper_credit_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_l0_shp_credit_tbl_c_shaper_credit_neg_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_l0_shp_credit_tbl_c_shaper_credit_neg_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_l0_shp_cfg_tbl_cir_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_l0_shp_cfg_tbl_cir_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_l0_shp_cfg_tbl_cf_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_l0_shp_cfg_tbl_cf_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_l0_shp_cfg_tbl_meter_unit_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_l0_shp_cfg_tbl_meter_unit_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_l0_shp_cfg_tbl_e_shaper_enable_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_l0_shp_cfg_tbl_e_shaper_enable_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_l0_shp_cfg_tbl_c_shaper_enable_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_l0_shp_cfg_tbl_c_shaper_enable_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_l0_shp_cfg_tbl_eir_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_l0_shp_cfg_tbl_eir_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_l0_shp_cfg_tbl_token_unit_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_l0_shp_cfg_tbl_token_unit_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_l0_shp_cfg_tbl_cbs_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_l0_shp_cfg_tbl_cbs_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_l0_shp_cfg_tbl_ebs_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_l0_shp_cfg_tbl_ebs_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_l0_comp_tbl_c_drr_compensate_byte_cnt_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_l0_comp_tbl_c_drr_compensate_byte_cnt_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_l0_comp_tbl_e_drr_compensate_byte_cnt_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_l0_comp_tbl_e_drr_compensate_byte_cnt_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_l0_comp_tbl_c_shaper_compensate_byte_neg_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_l0_comp_tbl_c_shaper_compensate_byte_neg_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_l0_comp_tbl_c_shaper_compensate_pkt_cnt_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_l0_comp_tbl_c_shaper_compensate_pkt_cnt_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_l0_comp_tbl_c_shaper_compensate_byte_cnt_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_l0_comp_tbl_c_shaper_compensate_byte_cnt_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_l0_comp_tbl_e_shaper_compensate_pkt_cnt_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_l0_comp_tbl_e_shaper_compensate_pkt_cnt_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_l0_comp_tbl_e_drr_compensate_pkt_cnt_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_l0_comp_tbl_e_drr_compensate_pkt_cnt_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_l0_comp_tbl_e_drr_compensate_byte_neg_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_l0_comp_tbl_e_drr_compensate_byte_neg_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_l0_comp_tbl_c_drr_compensate_pkt_cnt_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_l0_comp_tbl_c_drr_compensate_pkt_cnt_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_l0_comp_tbl_c_drr_compensate_byte_neg_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_l0_comp_tbl_c_drr_compensate_byte_neg_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_l0_comp_tbl_e_shaper_compensate_byte_cnt_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_l0_comp_tbl_e_shaper_compensate_byte_cnt_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_l0_comp_tbl_e_shaper_compensate_byte_neg_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_l0_comp_tbl_e_shaper_compensate_byte_neg_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_l0_comp_cfg_tbl_drr_meter_len_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_l0_comp_cfg_tbl_drr_meter_len_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_l0_comp_cfg_tbl_shaper_meter_len_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_l0_comp_cfg_tbl_shaper_meter_len_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_l1_shp_credit_tbl_e_shaper_credit_neg_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_l1_shp_credit_tbl_e_shaper_credit_neg_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_l1_shp_credit_tbl_e_shaper_credit_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_l1_shp_credit_tbl_e_shaper_credit_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_l1_shp_credit_tbl_c_shaper_credit_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_l1_shp_credit_tbl_c_shaper_credit_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_l1_shp_credit_tbl_c_shaper_credit_neg_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_l1_shp_credit_tbl_c_shaper_credit_neg_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_l1_shp_cfg_tbl_cir_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_l1_shp_cfg_tbl_cir_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_l1_shp_cfg_tbl_cf_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_l1_shp_cfg_tbl_cf_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_l1_shp_cfg_tbl_meter_unit_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_l1_shp_cfg_tbl_meter_unit_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_l1_shp_cfg_tbl_e_shaper_enable_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_l1_shp_cfg_tbl_e_shaper_enable_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_l1_shp_cfg_tbl_c_shaper_enable_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_l1_shp_cfg_tbl_c_shaper_enable_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_l1_shp_cfg_tbl_eir_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_l1_shp_cfg_tbl_eir_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_l1_shp_cfg_tbl_token_unit_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_l1_shp_cfg_tbl_token_unit_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_l1_shp_cfg_tbl_cbs_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_l1_shp_cfg_tbl_cbs_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_l1_shp_cfg_tbl_ebs_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_l1_shp_cfg_tbl_ebs_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_l1_comp_tbl_c_drr_compensate_byte_cnt_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_l1_comp_tbl_c_drr_compensate_byte_cnt_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_l1_comp_tbl_e_drr_compensate_byte_cnt_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_l1_comp_tbl_e_drr_compensate_byte_cnt_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_l1_comp_tbl_c_shaper_compensate_byte_neg_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_l1_comp_tbl_c_shaper_compensate_byte_neg_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_l1_comp_tbl_c_shaper_compensate_pkt_cnt_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_l1_comp_tbl_c_shaper_compensate_pkt_cnt_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_l1_comp_tbl_c_shaper_compensate_byte_cnt_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_l1_comp_tbl_c_shaper_compensate_byte_cnt_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_l1_comp_tbl_e_shaper_compensate_pkt_cnt_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_l1_comp_tbl_e_shaper_compensate_pkt_cnt_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_l1_comp_tbl_e_drr_compensate_pkt_cnt_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_l1_comp_tbl_e_drr_compensate_pkt_cnt_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_l1_comp_tbl_e_drr_compensate_byte_neg_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_l1_comp_tbl_e_drr_compensate_byte_neg_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_l1_comp_tbl_c_drr_compensate_pkt_cnt_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_l1_comp_tbl_c_drr_compensate_pkt_cnt_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_l1_comp_tbl_c_drr_compensate_byte_neg_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_l1_comp_tbl_c_drr_compensate_byte_neg_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_l1_comp_tbl_e_shaper_compensate_byte_cnt_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_l1_comp_tbl_e_shaper_compensate_byte_cnt_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_l1_comp_tbl_e_shaper_compensate_byte_neg_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_l1_comp_tbl_e_shaper_compensate_byte_neg_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_l1_comp_cfg_tbl_drr_meter_len_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_l1_comp_cfg_tbl_drr_meter_len_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_l1_comp_cfg_tbl_shaper_meter_len_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_l1_comp_cfg_tbl_shaper_meter_len_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - - -sw_error_t -hppe_psch_shp_sign_tbl_shaper_credit_neg_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_psch_shp_sign_tbl_shaper_credit_neg_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_psch_shp_credit_tbl_shaper_credit_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_psch_shp_credit_tbl_shaper_credit_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_psch_shp_cfg_tbl_cir_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_psch_shp_cfg_tbl_cir_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_psch_shp_cfg_tbl_meter_unit_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_psch_shp_cfg_tbl_meter_unit_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_psch_shp_cfg_tbl_token_unit_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_psch_shp_cfg_tbl_token_unit_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_psch_shp_cfg_tbl_cbs_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_psch_shp_cfg_tbl_cbs_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_psch_shp_cfg_tbl_shaper_enable_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_psch_shp_cfg_tbl_shaper_enable_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_psch_comp_tbl_shaper_compensate_byte_neg_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_psch_comp_tbl_shaper_compensate_byte_neg_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_psch_comp_tbl_shaper_compensate_pkt_cnt_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_psch_comp_tbl_shaper_compensate_pkt_cnt_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_psch_comp_tbl_shaper_compensate_byte_cnt_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_psch_comp_tbl_shaper_compensate_byte_cnt_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_psch_comp_cfg_tbl_shaper_meter_len_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_psch_comp_cfg_tbl_shaper_meter_len_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -#endif - diff --git a/feeds/ipq807x/qca-ssdk/src/include/hsl/hppe/hppe_shaper_reg.h b/feeds/ipq807x/qca-ssdk/src/include/hsl/hppe/hppe_shaper_reg.h deleted file mode 100755 index fe7b0afdd..000000000 --- a/feeds/ipq807x/qca-ssdk/src/include/hsl/hppe/hppe_shaper_reg.h +++ /dev/null @@ -1,730 +0,0 @@ -/* - * Copyright (c) 2016-2017, The Linux Foundation. All rights reserved. - * Permission to use, copy, modify, and/or distribute this software for - * any purpose with or without fee is hereby granted, provided that the - * above copyright notice and this permission notice appear in all copies. - * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES - * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR - * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES - * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN - * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT - * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. - */ - - -/** - * @defgroup - * @{ - */ -#ifndef HPPE_SHAPER_REG_H -#define HPPE_SHAPER_REG_H - -/*[register] SHP_SLOT_CFG_L0*/ -#define SHP_SLOT_CFG_L0 -#define SHP_SLOT_CFG_L0_ADDRESS 0x10 -#define SHP_SLOT_CFG_L0_NUM 1 -#define SHP_SLOT_CFG_L0_INC 0x4 -#define SHP_SLOT_CFG_L0_TYPE REG_TYPE_RW -#define SHP_SLOT_CFG_L0_DEFAULT 0x12c - /*[field] L0_SHP_SLOT_TIME*/ - #define SHP_SLOT_CFG_L0_L0_SHP_SLOT_TIME - #define SHP_SLOT_CFG_L0_L0_SHP_SLOT_TIME_OFFSET 0 - #define SHP_SLOT_CFG_L0_L0_SHP_SLOT_TIME_LEN 12 - #define SHP_SLOT_CFG_L0_L0_SHP_SLOT_TIME_DEFAULT 0x12c - -struct shp_slot_cfg_l0 { - a_uint32_t l0_shp_slot_time:12; - a_uint32_t _reserved0:20; -}; - -union shp_slot_cfg_l0_u { - a_uint32_t val; - struct shp_slot_cfg_l0 bf; -}; - -/*[register] SHP_SLOT_CFG_L1*/ -#define SHP_SLOT_CFG_L1 -#define SHP_SLOT_CFG_L1_ADDRESS 0x14 -#define SHP_SLOT_CFG_L1_NUM 1 -#define SHP_SLOT_CFG_L1_INC 0x4 -#define SHP_SLOT_CFG_L1_TYPE REG_TYPE_RW -#define SHP_SLOT_CFG_L1_DEFAULT 0x40 - /*[field] L1_SHP_SLOT_TIME*/ - #define SHP_SLOT_CFG_L1_L1_SHP_SLOT_TIME - #define SHP_SLOT_CFG_L1_L1_SHP_SLOT_TIME_OFFSET 0 - #define SHP_SLOT_CFG_L1_L1_SHP_SLOT_TIME_LEN 12 - #define SHP_SLOT_CFG_L1_L1_SHP_SLOT_TIME_DEFAULT 0x40 - -struct shp_slot_cfg_l1 { - a_uint32_t l1_shp_slot_time:12; - a_uint32_t _reserved0:20; -}; - -union shp_slot_cfg_l1_u { - a_uint32_t val; - struct shp_slot_cfg_l1 bf; -}; - -/*[register] SHP_SLOT_CFG_PORT*/ -#define SHP_SLOT_CFG_PORT -#define SHP_SLOT_CFG_PORT_ADDRESS 0x18 -#define SHP_SLOT_CFG_PORT_NUM 1 -#define SHP_SLOT_CFG_PORT_INC 0x4 -#define SHP_SLOT_CFG_PORT_TYPE REG_TYPE_RW -#define SHP_SLOT_CFG_PORT_DEFAULT 0x8 - /*[field] PORT_SHP_SLOT_TIME*/ - #define SHP_SLOT_CFG_PORT_PORT_SHP_SLOT_TIME - #define SHP_SLOT_CFG_PORT_PORT_SHP_SLOT_TIME_OFFSET 0 - #define SHP_SLOT_CFG_PORT_PORT_SHP_SLOT_TIME_LEN 12 - #define SHP_SLOT_CFG_PORT_PORT_SHP_SLOT_TIME_DEFAULT 0x8 - -struct shp_slot_cfg_port { - a_uint32_t port_shp_slot_time:12; - a_uint32_t _reserved0:20; -}; - -union shp_slot_cfg_port_u { - a_uint32_t val; - struct shp_slot_cfg_port bf; -}; - -/*[table] L0_SHP_CREDIT_TBL*/ -#define L0_SHP_CREDIT_TBL -#define L0_SHP_CREDIT_TBL_ADDRESS 0x1a000 -#define L0_SHP_CREDIT_TBL_NUM 300 -#define L0_SHP_CREDIT_TBL_INC 0x10 -#define L0_SHP_CREDIT_TBL_TYPE REG_TYPE_RW -#define L0_SHP_CREDIT_TBL_DEFAULT 0x0 - /*[field] C_SHAPER_CREDIT*/ - #define L0_SHP_CREDIT_TBL_C_SHAPER_CREDIT - #define L0_SHP_CREDIT_TBL_C_SHAPER_CREDIT_OFFSET 0 - #define L0_SHP_CREDIT_TBL_C_SHAPER_CREDIT_LEN 30 - #define L0_SHP_CREDIT_TBL_C_SHAPER_CREDIT_DEFAULT 0x0 - /*[field] C_SHAPER_CREDIT_NEG*/ - #define L0_SHP_CREDIT_TBL_C_SHAPER_CREDIT_NEG - #define L0_SHP_CREDIT_TBL_C_SHAPER_CREDIT_NEG_OFFSET 30 - #define L0_SHP_CREDIT_TBL_C_SHAPER_CREDIT_NEG_LEN 1 - #define L0_SHP_CREDIT_TBL_C_SHAPER_CREDIT_NEG_DEFAULT 0x0 - /*[field] E_SHAPER_CREDIT*/ - #define L0_SHP_CREDIT_TBL_E_SHAPER_CREDIT - #define L0_SHP_CREDIT_TBL_E_SHAPER_CREDIT_OFFSET 31 - #define L0_SHP_CREDIT_TBL_E_SHAPER_CREDIT_LEN 30 - #define L0_SHP_CREDIT_TBL_E_SHAPER_CREDIT_DEFAULT 0x0 - /*[field] E_SHAPER_CREDIT_NEG*/ - #define L0_SHP_CREDIT_TBL_E_SHAPER_CREDIT_NEG - #define L0_SHP_CREDIT_TBL_E_SHAPER_CREDIT_NEG_OFFSET 61 - #define L0_SHP_CREDIT_TBL_E_SHAPER_CREDIT_NEG_LEN 1 - #define L0_SHP_CREDIT_TBL_E_SHAPER_CREDIT_NEG_DEFAULT 0x0 - -struct l0_shp_credit_tbl { - a_uint32_t c_shaper_credit:30; - a_uint32_t c_shaper_credit_neg:1; - a_uint32_t e_shaper_credit_0:1; - a_uint32_t e_shaper_credit_1:29; - a_uint32_t e_shaper_credit_neg:1; - a_uint32_t _reserved0:2; -}; - -union l0_shp_credit_tbl_u { - a_uint32_t val[2]; - struct l0_shp_credit_tbl bf; -}; - -/*[table] L0_SHP_CFG_TBL*/ -#define L0_SHP_CFG_TBL -#define L0_SHP_CFG_TBL_ADDRESS 0x1c000 -#define L0_SHP_CFG_TBL_NUM 300 -#define L0_SHP_CFG_TBL_INC 0x10 -#define L0_SHP_CFG_TBL_TYPE REG_TYPE_RW -#define L0_SHP_CFG_TBL_DEFAULT 0x0 - /*[field] CIR*/ - #define L0_SHP_CFG_TBL_CIR - #define L0_SHP_CFG_TBL_CIR_OFFSET 0 - #define L0_SHP_CFG_TBL_CIR_LEN 18 - #define L0_SHP_CFG_TBL_CIR_DEFAULT 0x0 - /*[field] CBS*/ - #define L0_SHP_CFG_TBL_CBS - #define L0_SHP_CFG_TBL_CBS_OFFSET 18 - #define L0_SHP_CFG_TBL_CBS_LEN 14 - #define L0_SHP_CFG_TBL_CBS_DEFAULT 0x0 - /*[field] EIR*/ - #define L0_SHP_CFG_TBL_EIR - #define L0_SHP_CFG_TBL_EIR_OFFSET 32 - #define L0_SHP_CFG_TBL_EIR_LEN 18 - #define L0_SHP_CFG_TBL_EIR_DEFAULT 0x0 - /*[field] EBS*/ - #define L0_SHP_CFG_TBL_EBS - #define L0_SHP_CFG_TBL_EBS_OFFSET 50 - #define L0_SHP_CFG_TBL_EBS_LEN 14 - #define L0_SHP_CFG_TBL_EBS_DEFAULT 0x0 - /*[field] TOKEN_UNIT*/ - #define L0_SHP_CFG_TBL_TOKEN_UNIT - #define L0_SHP_CFG_TBL_TOKEN_UNIT_OFFSET 64 - #define L0_SHP_CFG_TBL_TOKEN_UNIT_LEN 3 - #define L0_SHP_CFG_TBL_TOKEN_UNIT_DEFAULT 0x0 - /*[field] METER_UNIT*/ - #define L0_SHP_CFG_TBL_METER_UNIT - #define L0_SHP_CFG_TBL_METER_UNIT_OFFSET 67 - #define L0_SHP_CFG_TBL_METER_UNIT_LEN 1 - #define L0_SHP_CFG_TBL_METER_UNIT_DEFAULT 0x0 - /*[field] C_SHAPER_ENABLE*/ - #define L0_SHP_CFG_TBL_C_SHAPER_ENABLE - #define L0_SHP_CFG_TBL_C_SHAPER_ENABLE_OFFSET 68 - #define L0_SHP_CFG_TBL_C_SHAPER_ENABLE_LEN 1 - #define L0_SHP_CFG_TBL_C_SHAPER_ENABLE_DEFAULT 0x0 - /*[field] E_SHAPER_ENABLE*/ - #define L0_SHP_CFG_TBL_E_SHAPER_ENABLE - #define L0_SHP_CFG_TBL_E_SHAPER_ENABLE_OFFSET 69 - #define L0_SHP_CFG_TBL_E_SHAPER_ENABLE_LEN 1 - #define L0_SHP_CFG_TBL_E_SHAPER_ENABLE_DEFAULT 0x0 - /*[field] CF*/ - #define L0_SHP_CFG_TBL_CF - #define L0_SHP_CFG_TBL_CF_OFFSET 70 - #define L0_SHP_CFG_TBL_CF_LEN 1 - #define L0_SHP_CFG_TBL_CF_DEFAULT 0x0 - -struct l0_shp_cfg_tbl { - a_uint32_t cir:18; - a_uint32_t cbs:14; - a_uint32_t eir:18; - a_uint32_t ebs:14; - a_uint32_t token_unit:3; - a_uint32_t meter_unit:1; - a_uint32_t c_shaper_enable:1; - a_uint32_t e_shaper_enable:1; - a_uint32_t cf:1; - a_uint32_t _reserved0:25; -}; - -union l0_shp_cfg_tbl_u { - a_uint32_t val[3]; - struct l0_shp_cfg_tbl bf; -}; - -/*[table] L0_COMP_TBL*/ -#define L0_COMP_TBL -#define L0_COMP_TBL_ADDRESS 0x26000 -#define L0_COMP_TBL_NUM 300 -#define L0_COMP_TBL_INC 0x10 -#define L0_COMP_TBL_TYPE REG_TYPE_RO -#define L0_COMP_TBL_DEFAULT 0x0 - /*[field] C_SHAPER_COMPENSATE_BYTE_CNT*/ - #define L0_COMP_TBL_C_SHAPER_COMPENSATE_BYTE_CNT - #define L0_COMP_TBL_C_SHAPER_COMPENSATE_BYTE_CNT_OFFSET 0 - #define L0_COMP_TBL_C_SHAPER_COMPENSATE_BYTE_CNT_LEN 18 - #define L0_COMP_TBL_C_SHAPER_COMPENSATE_BYTE_CNT_DEFAULT 0x0 - /*[field] C_SHAPER_COMPENSATE_BYTE_NEG*/ - #define L0_COMP_TBL_C_SHAPER_COMPENSATE_BYTE_NEG - #define L0_COMP_TBL_C_SHAPER_COMPENSATE_BYTE_NEG_OFFSET 18 - #define L0_COMP_TBL_C_SHAPER_COMPENSATE_BYTE_NEG_LEN 1 - #define L0_COMP_TBL_C_SHAPER_COMPENSATE_BYTE_NEG_DEFAULT 0x0 - /*[field] C_SHAPER_COMPENSATE_PKT_CNT*/ - #define L0_COMP_TBL_C_SHAPER_COMPENSATE_PKT_CNT - #define L0_COMP_TBL_C_SHAPER_COMPENSATE_PKT_CNT_OFFSET 19 - #define L0_COMP_TBL_C_SHAPER_COMPENSATE_PKT_CNT_LEN 4 - #define L0_COMP_TBL_C_SHAPER_COMPENSATE_PKT_CNT_DEFAULT 0x0 - /*[field] C_DRR_COMPENSATE_BYTE_CNT*/ - #define L0_COMP_TBL_C_DRR_COMPENSATE_BYTE_CNT - #define L0_COMP_TBL_C_DRR_COMPENSATE_BYTE_CNT_OFFSET 23 - #define L0_COMP_TBL_C_DRR_COMPENSATE_BYTE_CNT_LEN 18 - #define L0_COMP_TBL_C_DRR_COMPENSATE_BYTE_CNT_DEFAULT 0x0 - /*[field] C_DRR_COMPENSATE_BYTE_NEG*/ - #define L0_COMP_TBL_C_DRR_COMPENSATE_BYTE_NEG - #define L0_COMP_TBL_C_DRR_COMPENSATE_BYTE_NEG_OFFSET 41 - #define L0_COMP_TBL_C_DRR_COMPENSATE_BYTE_NEG_LEN 1 - #define L0_COMP_TBL_C_DRR_COMPENSATE_BYTE_NEG_DEFAULT 0x0 - /*[field] C_DRR_COMPENSATE_PKT_CNT*/ - #define L0_COMP_TBL_C_DRR_COMPENSATE_PKT_CNT - #define L0_COMP_TBL_C_DRR_COMPENSATE_PKT_CNT_OFFSET 42 - #define L0_COMP_TBL_C_DRR_COMPENSATE_PKT_CNT_LEN 4 - #define L0_COMP_TBL_C_DRR_COMPENSATE_PKT_CNT_DEFAULT 0x0 - /*[field] E_SHAPER_COMPENSATE_BYTE_CNT*/ - #define L0_COMP_TBL_E_SHAPER_COMPENSATE_BYTE_CNT - #define L0_COMP_TBL_E_SHAPER_COMPENSATE_BYTE_CNT_OFFSET 46 - #define L0_COMP_TBL_E_SHAPER_COMPENSATE_BYTE_CNT_LEN 18 - #define L0_COMP_TBL_E_SHAPER_COMPENSATE_BYTE_CNT_DEFAULT 0x0 - /*[field] E_SHAPER_COMPENSATE_BYTE_NEG*/ - #define L0_COMP_TBL_E_SHAPER_COMPENSATE_BYTE_NEG - #define L0_COMP_TBL_E_SHAPER_COMPENSATE_BYTE_NEG_OFFSET 64 - #define L0_COMP_TBL_E_SHAPER_COMPENSATE_BYTE_NEG_LEN 1 - #define L0_COMP_TBL_E_SHAPER_COMPENSATE_BYTE_NEG_DEFAULT 0x0 - /*[field] E_SHAPER_COMPENSATE_PKT_CNT*/ - #define L0_COMP_TBL_E_SHAPER_COMPENSATE_PKT_CNT - #define L0_COMP_TBL_E_SHAPER_COMPENSATE_PKT_CNT_OFFSET 65 - #define L0_COMP_TBL_E_SHAPER_COMPENSATE_PKT_CNT_LEN 4 - #define L0_COMP_TBL_E_SHAPER_COMPENSATE_PKT_CNT_DEFAULT 0x0 - /*[field] E_DRR_COMPENSATE_BYTE_CNT*/ - #define L0_COMP_TBL_E_DRR_COMPENSATE_BYTE_CNT - #define L0_COMP_TBL_E_DRR_COMPENSATE_BYTE_CNT_OFFSET 69 - #define L0_COMP_TBL_E_DRR_COMPENSATE_BYTE_CNT_LEN 18 - #define L0_COMP_TBL_E_DRR_COMPENSATE_BYTE_CNT_DEFAULT 0x0 - /*[field] E_DRR_COMPENSATE_BYTE_NEG*/ - #define L0_COMP_TBL_E_DRR_COMPENSATE_BYTE_NEG - #define L0_COMP_TBL_E_DRR_COMPENSATE_BYTE_NEG_OFFSET 87 - #define L0_COMP_TBL_E_DRR_COMPENSATE_BYTE_NEG_LEN 1 - #define L0_COMP_TBL_E_DRR_COMPENSATE_BYTE_NEG_DEFAULT 0x0 - /*[field] E_DRR_COMPENSATE_PKT_CNT*/ - #define L0_COMP_TBL_E_DRR_COMPENSATE_PKT_CNT - #define L0_COMP_TBL_E_DRR_COMPENSATE_PKT_CNT_OFFSET 88 - #define L0_COMP_TBL_E_DRR_COMPENSATE_PKT_CNT_LEN 4 - #define L0_COMP_TBL_E_DRR_COMPENSATE_PKT_CNT_DEFAULT 0x0 - -struct l0_comp_tbl { - a_uint32_t c_shaper_compensate_byte_cnt:18; - a_uint32_t c_shaper_compensate_byte_neg:1; - a_uint32_t c_shaper_compensate_pkt_cnt:4; - a_uint32_t c_drr_compensate_byte_cnt_0:9; - a_uint32_t c_drr_compensate_byte_cnt_1:9; - a_uint32_t c_drr_compensate_byte_neg:1; - a_uint32_t c_drr_compensate_pkt_cnt:4; - a_uint32_t e_shaper_compensate_byte_cnt:18; - a_uint32_t e_shaper_compensate_byte_neg:1; - a_uint32_t e_shaper_compensate_pkt_cnt:4; - a_uint32_t e_drr_compensate_byte_cnt:18; - a_uint32_t e_drr_compensate_byte_neg:1; - a_uint32_t e_drr_compensate_pkt_cnt:4; - a_uint32_t _reserved0:4; -}; - -union l0_comp_tbl_u { - a_uint32_t val[3]; - struct l0_comp_tbl bf; -}; - -/*[table] L0_COMP_CFG_TBL*/ -#define L0_COMP_CFG_TBL -#define L0_COMP_CFG_TBL_ADDRESS 0x28000 -#define L0_COMP_CFG_TBL_NUM 300 -#define L0_COMP_CFG_TBL_INC 0x10 -#define L0_COMP_CFG_TBL_TYPE REG_TYPE_RW -#define L0_COMP_CFG_TBL_DEFAULT 0x0 - /*[field] SHAPER_METER_LEN*/ - #define L0_COMP_CFG_TBL_SHAPER_METER_LEN - #define L0_COMP_CFG_TBL_SHAPER_METER_LEN_OFFSET 0 - #define L0_COMP_CFG_TBL_SHAPER_METER_LEN_LEN 2 - #define L0_COMP_CFG_TBL_SHAPER_METER_LEN_DEFAULT 0x0 - /*[field] DRR_METER_LEN*/ - #define L0_COMP_CFG_TBL_DRR_METER_LEN - #define L0_COMP_CFG_TBL_DRR_METER_LEN_OFFSET 2 - #define L0_COMP_CFG_TBL_DRR_METER_LEN_LEN 2 - #define L0_COMP_CFG_TBL_DRR_METER_LEN_DEFAULT 0x0 - -struct l0_comp_cfg_tbl { - a_uint32_t shaper_meter_len:2; - a_uint32_t drr_meter_len:2; - a_uint32_t _reserved0:28; -}; - -union l0_comp_cfg_tbl_u { - a_uint32_t val; - struct l0_comp_cfg_tbl bf; -}; - -/*[table] L1_SHP_CREDIT_TBL*/ -#define L1_SHP_CREDIT_TBL -#define L1_SHP_CREDIT_TBL_ADDRESS 0x5c000 -#define L1_SHP_CREDIT_TBL_NUM 64 -#define L1_SHP_CREDIT_TBL_INC 0x10 -#define L1_SHP_CREDIT_TBL_TYPE REG_TYPE_RW -#define L1_SHP_CREDIT_TBL_DEFAULT 0x0 - /*[field] C_SHAPER_CREDIT*/ - #define L1_SHP_CREDIT_TBL_C_SHAPER_CREDIT - #define L1_SHP_CREDIT_TBL_C_SHAPER_CREDIT_OFFSET 0 - #define L1_SHP_CREDIT_TBL_C_SHAPER_CREDIT_LEN 30 - #define L1_SHP_CREDIT_TBL_C_SHAPER_CREDIT_DEFAULT 0x0 - /*[field] C_SHAPER_CREDIT_NEG*/ - #define L1_SHP_CREDIT_TBL_C_SHAPER_CREDIT_NEG - #define L1_SHP_CREDIT_TBL_C_SHAPER_CREDIT_NEG_OFFSET 30 - #define L1_SHP_CREDIT_TBL_C_SHAPER_CREDIT_NEG_LEN 1 - #define L1_SHP_CREDIT_TBL_C_SHAPER_CREDIT_NEG_DEFAULT 0x0 - /*[field] E_SHAPER_CREDIT*/ - #define L1_SHP_CREDIT_TBL_E_SHAPER_CREDIT - #define L1_SHP_CREDIT_TBL_E_SHAPER_CREDIT_OFFSET 31 - #define L1_SHP_CREDIT_TBL_E_SHAPER_CREDIT_LEN 30 - #define L1_SHP_CREDIT_TBL_E_SHAPER_CREDIT_DEFAULT 0x0 - /*[field] E_SHAPER_CREDIT_NEG*/ - #define L1_SHP_CREDIT_TBL_E_SHAPER_CREDIT_NEG - #define L1_SHP_CREDIT_TBL_E_SHAPER_CREDIT_NEG_OFFSET 61 - #define L1_SHP_CREDIT_TBL_E_SHAPER_CREDIT_NEG_LEN 1 - #define L1_SHP_CREDIT_TBL_E_SHAPER_CREDIT_NEG_DEFAULT 0x0 - -struct l1_shp_credit_tbl { - a_uint32_t c_shaper_credit:30; - a_uint32_t c_shaper_credit_neg:1; - a_uint32_t e_shaper_credit_0:1; - a_uint32_t e_shaper_credit_1:29; - a_uint32_t e_shaper_credit_neg:1; - a_uint32_t _reserved0:2; -}; - -union l1_shp_credit_tbl_u { - a_uint32_t val[2]; - struct l1_shp_credit_tbl bf; -}; - -/*[table] L1_SHP_CFG_TBL*/ -#define L1_SHP_CFG_TBL -#define L1_SHP_CFG_TBL_ADDRESS 0x5e000 -#define L1_SHP_CFG_TBL_NUM 64 -#define L1_SHP_CFG_TBL_INC 0x10 -#define L1_SHP_CFG_TBL_TYPE REG_TYPE_RW -#define L1_SHP_CFG_TBL_DEFAULT 0x0 - /*[field] CIR*/ - #define L1_SHP_CFG_TBL_CIR - #define L1_SHP_CFG_TBL_CIR_OFFSET 0 - #define L1_SHP_CFG_TBL_CIR_LEN 18 - #define L1_SHP_CFG_TBL_CIR_DEFAULT 0x0 - /*[field] CBS*/ - #define L1_SHP_CFG_TBL_CBS - #define L1_SHP_CFG_TBL_CBS_OFFSET 18 - #define L1_SHP_CFG_TBL_CBS_LEN 14 - #define L1_SHP_CFG_TBL_CBS_DEFAULT 0x0 - /*[field] EIR*/ - #define L1_SHP_CFG_TBL_EIR - #define L1_SHP_CFG_TBL_EIR_OFFSET 32 - #define L1_SHP_CFG_TBL_EIR_LEN 18 - #define L1_SHP_CFG_TBL_EIR_DEFAULT 0x0 - /*[field] EBS*/ - #define L1_SHP_CFG_TBL_EBS - #define L1_SHP_CFG_TBL_EBS_OFFSET 50 - #define L1_SHP_CFG_TBL_EBS_LEN 14 - #define L1_SHP_CFG_TBL_EBS_DEFAULT 0x0 - /*[field] TOKEN_UNIT*/ - #define L1_SHP_CFG_TBL_TOKEN_UNIT - #define L1_SHP_CFG_TBL_TOKEN_UNIT_OFFSET 64 - #define L1_SHP_CFG_TBL_TOKEN_UNIT_LEN 3 - #define L1_SHP_CFG_TBL_TOKEN_UNIT_DEFAULT 0x0 - /*[field] METER_UNIT*/ - #define L1_SHP_CFG_TBL_METER_UNIT - #define L1_SHP_CFG_TBL_METER_UNIT_OFFSET 67 - #define L1_SHP_CFG_TBL_METER_UNIT_LEN 1 - #define L1_SHP_CFG_TBL_METER_UNIT_DEFAULT 0x0 - /*[field] C_SHAPER_ENABLE*/ - #define L1_SHP_CFG_TBL_C_SHAPER_ENABLE - #define L1_SHP_CFG_TBL_C_SHAPER_ENABLE_OFFSET 68 - #define L1_SHP_CFG_TBL_C_SHAPER_ENABLE_LEN 1 - #define L1_SHP_CFG_TBL_C_SHAPER_ENABLE_DEFAULT 0x0 - /*[field] E_SHAPER_ENABLE*/ - #define L1_SHP_CFG_TBL_E_SHAPER_ENABLE - #define L1_SHP_CFG_TBL_E_SHAPER_ENABLE_OFFSET 69 - #define L1_SHP_CFG_TBL_E_SHAPER_ENABLE_LEN 1 - #define L1_SHP_CFG_TBL_E_SHAPER_ENABLE_DEFAULT 0x0 - /*[field] CF*/ - #define L1_SHP_CFG_TBL_CF - #define L1_SHP_CFG_TBL_CF_OFFSET 70 - #define L1_SHP_CFG_TBL_CF_LEN 1 - #define L1_SHP_CFG_TBL_CF_DEFAULT 0x0 - -struct l1_shp_cfg_tbl { - a_uint32_t cir:18; - a_uint32_t cbs:14; - a_uint32_t eir:18; - a_uint32_t ebs:14; - a_uint32_t token_unit:3; - a_uint32_t meter_unit:1; - a_uint32_t c_shaper_enable:1; - a_uint32_t e_shaper_enable:1; - a_uint32_t cf:1; - a_uint32_t _reserved0:25; -}; - -union l1_shp_cfg_tbl_u { - a_uint32_t val[3]; - struct l1_shp_cfg_tbl bf; -}; - -/*[table] L1_COMP_TBL*/ -#define L1_COMP_TBL -#define L1_COMP_TBL_ADDRESS 0x68000 -#define L1_COMP_TBL_NUM 64 -#define L1_COMP_TBL_INC 0x10 -#define L1_COMP_TBL_TYPE REG_TYPE_RO -#define L1_COMP_TBL_DEFAULT 0x0 - /*[field] C_SHAPER_COMPENSATE_BYTE_CNT*/ - #define L1_COMP_TBL_C_SHAPER_COMPENSATE_BYTE_CNT - #define L1_COMP_TBL_C_SHAPER_COMPENSATE_BYTE_CNT_OFFSET 0 - #define L1_COMP_TBL_C_SHAPER_COMPENSATE_BYTE_CNT_LEN 18 - #define L1_COMP_TBL_C_SHAPER_COMPENSATE_BYTE_CNT_DEFAULT 0x0 - /*[field] C_SHAPER_COMPENSATE_BYTE_NEG*/ - #define L1_COMP_TBL_C_SHAPER_COMPENSATE_BYTE_NEG - #define L1_COMP_TBL_C_SHAPER_COMPENSATE_BYTE_NEG_OFFSET 18 - #define L1_COMP_TBL_C_SHAPER_COMPENSATE_BYTE_NEG_LEN 1 - #define L1_COMP_TBL_C_SHAPER_COMPENSATE_BYTE_NEG_DEFAULT 0x0 - /*[field] C_SHAPER_COMPENSATE_PKT_CNT*/ - #define L1_COMP_TBL_C_SHAPER_COMPENSATE_PKT_CNT - #define L1_COMP_TBL_C_SHAPER_COMPENSATE_PKT_CNT_OFFSET 19 - #define L1_COMP_TBL_C_SHAPER_COMPENSATE_PKT_CNT_LEN 4 - #define L1_COMP_TBL_C_SHAPER_COMPENSATE_PKT_CNT_DEFAULT 0x0 - /*[field] C_DRR_COMPENSATE_BYTE_CNT*/ - #define L1_COMP_TBL_C_DRR_COMPENSATE_BYTE_CNT - #define L1_COMP_TBL_C_DRR_COMPENSATE_BYTE_CNT_OFFSET 23 - #define L1_COMP_TBL_C_DRR_COMPENSATE_BYTE_CNT_LEN 18 - #define L1_COMP_TBL_C_DRR_COMPENSATE_BYTE_CNT_DEFAULT 0x0 - /*[field] C_DRR_COMPENSATE_BYTE_NEG*/ - #define L1_COMP_TBL_C_DRR_COMPENSATE_BYTE_NEG - #define L1_COMP_TBL_C_DRR_COMPENSATE_BYTE_NEG_OFFSET 41 - #define L1_COMP_TBL_C_DRR_COMPENSATE_BYTE_NEG_LEN 1 - #define L1_COMP_TBL_C_DRR_COMPENSATE_BYTE_NEG_DEFAULT 0x0 - /*[field] C_DRR_COMPENSATE_PKT_CNT*/ - #define L1_COMP_TBL_C_DRR_COMPENSATE_PKT_CNT - #define L1_COMP_TBL_C_DRR_COMPENSATE_PKT_CNT_OFFSET 42 - #define L1_COMP_TBL_C_DRR_COMPENSATE_PKT_CNT_LEN 4 - #define L1_COMP_TBL_C_DRR_COMPENSATE_PKT_CNT_DEFAULT 0x0 - /*[field] E_SHAPER_COMPENSATE_BYTE_CNT*/ - #define L1_COMP_TBL_E_SHAPER_COMPENSATE_BYTE_CNT - #define L1_COMP_TBL_E_SHAPER_COMPENSATE_BYTE_CNT_OFFSET 46 - #define L1_COMP_TBL_E_SHAPER_COMPENSATE_BYTE_CNT_LEN 18 - #define L1_COMP_TBL_E_SHAPER_COMPENSATE_BYTE_CNT_DEFAULT 0x0 - /*[field] E_SHAPER_COMPENSATE_BYTE_NEG*/ - #define L1_COMP_TBL_E_SHAPER_COMPENSATE_BYTE_NEG - #define L1_COMP_TBL_E_SHAPER_COMPENSATE_BYTE_NEG_OFFSET 64 - #define L1_COMP_TBL_E_SHAPER_COMPENSATE_BYTE_NEG_LEN 1 - #define L1_COMP_TBL_E_SHAPER_COMPENSATE_BYTE_NEG_DEFAULT 0x0 - /*[field] E_SHAPER_COMPENSATE_PKT_CNT*/ - #define L1_COMP_TBL_E_SHAPER_COMPENSATE_PKT_CNT - #define L1_COMP_TBL_E_SHAPER_COMPENSATE_PKT_CNT_OFFSET 65 - #define L1_COMP_TBL_E_SHAPER_COMPENSATE_PKT_CNT_LEN 4 - #define L1_COMP_TBL_E_SHAPER_COMPENSATE_PKT_CNT_DEFAULT 0x0 - /*[field] E_DRR_COMPENSATE_BYTE_CNT*/ - #define L1_COMP_TBL_E_DRR_COMPENSATE_BYTE_CNT - #define L1_COMP_TBL_E_DRR_COMPENSATE_BYTE_CNT_OFFSET 69 - #define L1_COMP_TBL_E_DRR_COMPENSATE_BYTE_CNT_LEN 18 - #define L1_COMP_TBL_E_DRR_COMPENSATE_BYTE_CNT_DEFAULT 0x0 - /*[field] E_DRR_COMPENSATE_BYTE_NEG*/ - #define L1_COMP_TBL_E_DRR_COMPENSATE_BYTE_NEG - #define L1_COMP_TBL_E_DRR_COMPENSATE_BYTE_NEG_OFFSET 87 - #define L1_COMP_TBL_E_DRR_COMPENSATE_BYTE_NEG_LEN 1 - #define L1_COMP_TBL_E_DRR_COMPENSATE_BYTE_NEG_DEFAULT 0x0 - /*[field] E_DRR_COMPENSATE_PKT_CNT*/ - #define L1_COMP_TBL_E_DRR_COMPENSATE_PKT_CNT - #define L1_COMP_TBL_E_DRR_COMPENSATE_PKT_CNT_OFFSET 88 - #define L1_COMP_TBL_E_DRR_COMPENSATE_PKT_CNT_LEN 4 - #define L1_COMP_TBL_E_DRR_COMPENSATE_PKT_CNT_DEFAULT 0x0 - -struct l1_comp_tbl { - a_uint32_t c_shaper_compensate_byte_cnt:18; - a_uint32_t c_shaper_compensate_byte_neg:1; - a_uint32_t c_shaper_compensate_pkt_cnt:4; - a_uint32_t c_drr_compensate_byte_cnt_0:9; - a_uint32_t c_drr_compensate_byte_cnt_1:9; - a_uint32_t c_drr_compensate_byte_neg:1; - a_uint32_t c_drr_compensate_pkt_cnt:4; - a_uint32_t e_shaper_compensate_byte_cnt:18; - a_uint32_t e_shaper_compensate_byte_neg:1; - a_uint32_t e_shaper_compensate_pkt_cnt:4; - a_uint32_t e_drr_compensate_byte_cnt:18; - a_uint32_t e_drr_compensate_byte_neg:1; - a_uint32_t e_drr_compensate_pkt_cnt:4; - a_uint32_t _reserved0:4; -}; - -union l1_comp_tbl_u { - a_uint32_t val[3]; - struct l1_comp_tbl bf; -}; - -/*[table] L1_COMP_CFG_TBL*/ -#define L1_COMP_CFG_TBL -#define L1_COMP_CFG_TBL_ADDRESS 0x6a000 -#define L1_COMP_CFG_TBL_NUM 64 -#define L1_COMP_CFG_TBL_INC 0x10 -#define L1_COMP_CFG_TBL_TYPE REG_TYPE_RW -#define L1_COMP_CFG_TBL_DEFAULT 0x0 - /*[field] SHAPER_METER_LEN*/ - #define L1_COMP_CFG_TBL_SHAPER_METER_LEN - #define L1_COMP_CFG_TBL_SHAPER_METER_LEN_OFFSET 0 - #define L1_COMP_CFG_TBL_SHAPER_METER_LEN_LEN 2 - #define L1_COMP_CFG_TBL_SHAPER_METER_LEN_DEFAULT 0x0 - /*[field] DRR_METER_LEN*/ - #define L1_COMP_CFG_TBL_DRR_METER_LEN - #define L1_COMP_CFG_TBL_DRR_METER_LEN_OFFSET 2 - #define L1_COMP_CFG_TBL_DRR_METER_LEN_LEN 2 - #define L1_COMP_CFG_TBL_DRR_METER_LEN_DEFAULT 0x0 - -struct l1_comp_cfg_tbl { - a_uint32_t shaper_meter_len:2; - a_uint32_t drr_meter_len:2; - a_uint32_t _reserved0:28; -}; - -union l1_comp_cfg_tbl_u { - a_uint32_t val; - struct l1_comp_cfg_tbl bf; -}; - -/*[table] PSCH_SHP_SIGN_TBL*/ -#define PSCH_SHP_SIGN_TBL -#define PSCH_SHP_SIGN_TBL_ADDRESS 0x70000 -#define PSCH_SHP_SIGN_TBL_NUM 8 -#define PSCH_SHP_SIGN_TBL_INC 0x10 -#define PSCH_SHP_SIGN_TBL_TYPE REG_TYPE_RW -#define PSCH_SHP_SIGN_TBL_DEFAULT 0x0 - /*[field] SHAPER_CREDIT_NEG*/ - #define PSCH_SHP_SIGN_TBL_SHAPER_CREDIT_NEG - #define PSCH_SHP_SIGN_TBL_SHAPER_CREDIT_NEG_OFFSET 0 - #define PSCH_SHP_SIGN_TBL_SHAPER_CREDIT_NEG_LEN 1 - #define PSCH_SHP_SIGN_TBL_SHAPER_CREDIT_NEG_DEFAULT 0x0 - -struct psch_shp_sign_tbl { - a_uint32_t shaper_credit_neg:1; - a_uint32_t _reserved0:31; -}; - -union psch_shp_sign_tbl_u { - a_uint32_t val; - struct psch_shp_sign_tbl bf; -}; - -/*[table] PSCH_SHP_CREDIT_TBL*/ -#define PSCH_SHP_CREDIT_TBL -#define PSCH_SHP_CREDIT_TBL_ADDRESS 0x72000 -#define PSCH_SHP_CREDIT_TBL_NUM 8 -#define PSCH_SHP_CREDIT_TBL_INC 0x10 -#define PSCH_SHP_CREDIT_TBL_TYPE REG_TYPE_RW -#define PSCH_SHP_CREDIT_TBL_DEFAULT 0x0 - /*[field] SHAPER_CREDIT*/ - #define PSCH_SHP_CREDIT_TBL_SHAPER_CREDIT - #define PSCH_SHP_CREDIT_TBL_SHAPER_CREDIT_OFFSET 0 - #define PSCH_SHP_CREDIT_TBL_SHAPER_CREDIT_LEN 30 - #define PSCH_SHP_CREDIT_TBL_SHAPER_CREDIT_DEFAULT 0x0 - -struct psch_shp_credit_tbl { - a_uint32_t shaper_credit:30; - a_uint32_t _reserved0:2; -}; - -union psch_shp_credit_tbl_u { - a_uint32_t val; - struct psch_shp_credit_tbl bf; -}; - -/*[table] PSCH_SHP_CFG_TBL*/ -#define PSCH_SHP_CFG_TBL -#define PSCH_SHP_CFG_TBL_ADDRESS 0x74000 -#define PSCH_SHP_CFG_TBL_NUM 8 -#define PSCH_SHP_CFG_TBL_INC 0x10 -#define PSCH_SHP_CFG_TBL_TYPE REG_TYPE_RW -#define PSCH_SHP_CFG_TBL_DEFAULT 0x0 - /*[field] CIR*/ - #define PSCH_SHP_CFG_TBL_CIR - #define PSCH_SHP_CFG_TBL_CIR_OFFSET 0 - #define PSCH_SHP_CFG_TBL_CIR_LEN 18 - #define PSCH_SHP_CFG_TBL_CIR_DEFAULT 0x0 - /*[field] CBS*/ - #define PSCH_SHP_CFG_TBL_CBS - #define PSCH_SHP_CFG_TBL_CBS_OFFSET 18 - #define PSCH_SHP_CFG_TBL_CBS_LEN 14 - #define PSCH_SHP_CFG_TBL_CBS_DEFAULT 0x0 - /*[field] TOKEN_UNIT*/ - #define PSCH_SHP_CFG_TBL_TOKEN_UNIT - #define PSCH_SHP_CFG_TBL_TOKEN_UNIT_OFFSET 32 - #define PSCH_SHP_CFG_TBL_TOKEN_UNIT_LEN 3 - #define PSCH_SHP_CFG_TBL_TOKEN_UNIT_DEFAULT 0x0 - /*[field] METER_UNIT*/ - #define PSCH_SHP_CFG_TBL_METER_UNIT - #define PSCH_SHP_CFG_TBL_METER_UNIT_OFFSET 35 - #define PSCH_SHP_CFG_TBL_METER_UNIT_LEN 1 - #define PSCH_SHP_CFG_TBL_METER_UNIT_DEFAULT 0x0 - /*[field] SHAPER_ENABLE*/ - #define PSCH_SHP_CFG_TBL_SHAPER_ENABLE - #define PSCH_SHP_CFG_TBL_SHAPER_ENABLE_OFFSET 36 - #define PSCH_SHP_CFG_TBL_SHAPER_ENABLE_LEN 1 - #define PSCH_SHP_CFG_TBL_SHAPER_ENABLE_DEFAULT 0x0 - -struct psch_shp_cfg_tbl { - a_uint32_t cir:18; - a_uint32_t cbs:14; - a_uint32_t token_unit:3; - a_uint32_t meter_unit:1; - a_uint32_t shaper_enable:1; - a_uint32_t _reserved0:27; -}; - -union psch_shp_cfg_tbl_u { - a_uint32_t val[2]; - struct psch_shp_cfg_tbl bf; -}; - -/*[table] PSCH_COMP_TBL*/ -#define PSCH_COMP_TBL -#define PSCH_COMP_TBL_ADDRESS 0x76000 -#define PSCH_COMP_TBL_NUM 8 -#define PSCH_COMP_TBL_INC 0x10 -#define PSCH_COMP_TBL_TYPE REG_TYPE_RO -#define PSCH_COMP_TBL_DEFAULT 0x0 - /*[field] SHAPER_COMPENSATE_BYTE_CNT*/ - #define PSCH_COMP_TBL_SHAPER_COMPENSATE_BYTE_CNT - #define PSCH_COMP_TBL_SHAPER_COMPENSATE_BYTE_CNT_OFFSET 0 - #define PSCH_COMP_TBL_SHAPER_COMPENSATE_BYTE_CNT_LEN 18 - #define PSCH_COMP_TBL_SHAPER_COMPENSATE_BYTE_CNT_DEFAULT 0x0 - /*[field] SHAPER_COMPENSATE_BYTE_NEG*/ - #define PSCH_COMP_TBL_SHAPER_COMPENSATE_BYTE_NEG - #define PSCH_COMP_TBL_SHAPER_COMPENSATE_BYTE_NEG_OFFSET 18 - #define PSCH_COMP_TBL_SHAPER_COMPENSATE_BYTE_NEG_LEN 1 - #define PSCH_COMP_TBL_SHAPER_COMPENSATE_BYTE_NEG_DEFAULT 0x0 - /*[field] SHAPER_COMPENSATE_PKT_CNT*/ - #define PSCH_COMP_TBL_SHAPER_COMPENSATE_PKT_CNT - #define PSCH_COMP_TBL_SHAPER_COMPENSATE_PKT_CNT_OFFSET 19 - #define PSCH_COMP_TBL_SHAPER_COMPENSATE_PKT_CNT_LEN 4 - #define PSCH_COMP_TBL_SHAPER_COMPENSATE_PKT_CNT_DEFAULT 0x0 - -struct psch_comp_tbl { - a_uint32_t shaper_compensate_byte_cnt:18; - a_uint32_t shaper_compensate_byte_neg:1; - a_uint32_t shaper_compensate_pkt_cnt:4; - a_uint32_t _reserved0:9; -}; - -union psch_comp_tbl_u { - a_uint32_t val; - struct psch_comp_tbl bf; -}; - -/*[table] PSCH_COMP_CFG_TBL*/ -#define PSCH_COMP_CFG_TBL -#define PSCH_COMP_CFG_TBL_ADDRESS 0x78000 -#define PSCH_COMP_CFG_TBL_NUM 8 -#define PSCH_COMP_CFG_TBL_INC 0x10 -#define PSCH_COMP_CFG_TBL_TYPE REG_TYPE_RW -#define PSCH_COMP_CFG_TBL_DEFAULT 0x0 - /*[field] SHAPER_METER_LEN*/ - #define PSCH_COMP_CFG_TBL_SHAPER_METER_LEN - #define PSCH_COMP_CFG_TBL_SHAPER_METER_LEN_OFFSET 0 - #define PSCH_COMP_CFG_TBL_SHAPER_METER_LEN_LEN 2 - #define PSCH_COMP_CFG_TBL_SHAPER_METER_LEN_DEFAULT 0x0 - -struct psch_comp_cfg_tbl { - a_uint32_t shaper_meter_len:2; - a_uint32_t _reserved0:30; -}; - -union psch_comp_cfg_tbl_u { - a_uint32_t val; - struct psch_comp_cfg_tbl bf; -}; - -/*[register] IPG_PRE_LEN_CFG*/ -#define IPG_PRE_LEN_CFG -#define IPG_PRE_LEN_CFG_ADDRESS 0x8 -#define IPG_PRE_LEN_CFG_NUM 1 -#define IPG_PRE_LEN_CFG_INC 0x4 -#define IPG_PRE_LEN_CFG_TYPE REG_TYPE_RW -#define IPG_PRE_LEN_CFG_DEFAULT 0x0 - /*[field] IPG_PRE_LEN*/ - #define IPG_PRE_LEN_CFG_IPG_PRE_LEN - #define IPG_PRE_LEN_CFG_IPG_PRE_LEN_OFFSET 0 - #define IPG_PRE_LEN_CFG_IPG_PRE_LEN_LEN 5 - #define IPG_PRE_LEN_CFG_IPG_PRE_LEN_DEFAULT 0x0 - -struct ipg_pre_len_cfg { - a_uint32_t ipg_pre_len:5; - a_uint32_t _reserved0:27; -}; - -union ipg_pre_len_cfg_u { - a_uint32_t val; - struct ipg_pre_len_cfg bf; -}; - -#endif diff --git a/feeds/ipq807x/qca-ssdk/src/include/hsl/hppe/hppe_stp.h b/feeds/ipq807x/qca-ssdk/src/include/hsl/hppe/hppe_stp.h deleted file mode 100755 index 76443dd0d..000000000 --- a/feeds/ipq807x/qca-ssdk/src/include/hsl/hppe/hppe_stp.h +++ /dev/null @@ -1,51 +0,0 @@ -/* - * Copyright (c) 2016-2017, The Linux Foundation. All rights reserved. - * Permission to use, copy, modify, and/or distribute this software for - * any purpose with or without fee is hereby granted, provided that the - * above copyright notice and this permission notice appear in all copies. - * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES - * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR - * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES - * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN - * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT - * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. - */ - - -/** - * @defgroup - * @{ - */ -#ifndef _HPPE_STP_H_ -#define _HPPE_STP_H_ - -#define CST_STATE_MAX_ENTRY 8 - -sw_error_t -hppe_cst_state_get( - a_uint32_t dev_id, - a_uint32_t index, - union cst_state_u *value); - -sw_error_t -hppe_cst_state_set( - a_uint32_t dev_id, - a_uint32_t index, - union cst_state_u *value); - -sw_error_t -hppe_cst_state_port_state_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_cst_state_port_state_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - - -#endif - diff --git a/feeds/ipq807x/qca-ssdk/src/include/hsl/hppe/hppe_stp_reg.h b/feeds/ipq807x/qca-ssdk/src/include/hsl/hppe/hppe_stp_reg.h deleted file mode 100755 index c472b7ba7..000000000 --- a/feeds/ipq807x/qca-ssdk/src/include/hsl/hppe/hppe_stp_reg.h +++ /dev/null @@ -1,46 +0,0 @@ -/* - * Copyright (c) 2016-2017, The Linux Foundation. All rights reserved. - * Permission to use, copy, modify, and/or distribute this software for - * any purpose with or without fee is hereby granted, provided that the - * above copyright notice and this permission notice appear in all copies. - * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES - * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR - * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES - * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN - * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT - * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. - */ - - -/** - * @defgroup - * @{ - */ -#ifndef HPPE_STP_REG_H -#define HPPE_STP_REG_H - -/*[register] CST_STATE*/ -#define CST_STATE -#define CST_STATE_ADDRESS 0x100 -#define CST_STATE_NUM 8 -#define CST_STATE_INC 0x4 -#define CST_STATE_TYPE REG_TYPE_RW -#define CST_STATE_DEFAULT 0x3 - /*[field] PORT_STATE*/ - #define CST_STATE_PORT_STATE - #define CST_STATE_PORT_STATE_OFFSET 0 - #define CST_STATE_PORT_STATE_LEN 2 - #define CST_STATE_PORT_STATE_DEFAULT 0x3 - -struct cst_state { - a_uint32_t port_state:2; - a_uint32_t _reserved0:30; -}; - -union cst_state_u { - a_uint32_t val; - struct cst_state bf; -}; - -#endif diff --git a/feeds/ipq807x/qca-ssdk/src/include/hsl/hppe/hppe_trunk.h b/feeds/ipq807x/qca-ssdk/src/include/hsl/hppe/hppe_trunk.h deleted file mode 100755 index 279b5d92f..000000000 --- a/feeds/ipq807x/qca-ssdk/src/include/hsl/hppe/hppe_trunk.h +++ /dev/null @@ -1,320 +0,0 @@ -/* - * Copyright (c) 2016-2017, The Linux Foundation. All rights reserved. - * Permission to use, copy, modify, and/or distribute this software for - * any purpose with or without fee is hereby granted, provided that the - * above copyright notice and this permission notice appear in all copies. - * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES - * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR - * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES - * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN - * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT - * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. - */ - - -/** - * @defgroup - * @{ - */ -#ifndef _HPPE_TRUNK_H_ -#define _HPPE_TRUNK_H_ - - -#define PORT_PARSING_REG_MAX_ENTRY 8 - -#define PC_GLOBAL_CNT_TBL_MAX_ENTRY 3 -#define TRUNK_FILTER_MAX_ENTRY 2 -#define TRUNK_MEMBER_MAX_ENTRY 2 -#define PORT_TRUNK_ID_MAX_ENTRY 8 - -sw_error_t -hppe_trunk_hash_field_reg_get( - a_uint32_t dev_id, - union trunk_hash_field_reg_u *value); - -sw_error_t -hppe_trunk_hash_field_reg_set( - a_uint32_t dev_id, - union trunk_hash_field_reg_u *value); - -sw_error_t -hppe_trunk_filter_get( - a_uint32_t dev_id, - a_uint32_t index, - union trunk_filter_u *value); - -sw_error_t -hppe_trunk_filter_set( - a_uint32_t dev_id, - a_uint32_t index, - union trunk_filter_u *value); - -sw_error_t -hppe_trunk_member_get( - a_uint32_t dev_id, - a_uint32_t index, - union trunk_member_u *value); - -sw_error_t -hppe_trunk_member_set( - a_uint32_t dev_id, - a_uint32_t index, - union trunk_member_u *value); - -sw_error_t -hppe_port_trunk_id_get( - a_uint32_t dev_id, - a_uint32_t index, - union port_trunk_id_u *value); - -sw_error_t -hppe_port_trunk_id_set( - a_uint32_t dev_id, - a_uint32_t index, - union port_trunk_id_u *value); - -sw_error_t -hppe_trunk_hash_field_reg_udf2_incl_get( - a_uint32_t dev_id, - unsigned int *value); - -sw_error_t -hppe_trunk_hash_field_reg_udf2_incl_set( - a_uint32_t dev_id, - unsigned int value); - -sw_error_t -hppe_trunk_hash_field_reg_mac_da_incl_get( - a_uint32_t dev_id, - unsigned int *value); - -sw_error_t -hppe_trunk_hash_field_reg_mac_da_incl_set( - a_uint32_t dev_id, - unsigned int value); - -sw_error_t -hppe_trunk_hash_field_reg_src_port_incl_get( - a_uint32_t dev_id, - unsigned int *value); - -sw_error_t -hppe_trunk_hash_field_reg_src_port_incl_set( - a_uint32_t dev_id, - unsigned int value); - -sw_error_t -hppe_trunk_hash_field_reg_udf3_incl_get( - a_uint32_t dev_id, - unsigned int *value); - -sw_error_t -hppe_trunk_hash_field_reg_udf3_incl_set( - a_uint32_t dev_id, - unsigned int value); - -sw_error_t -hppe_trunk_hash_field_reg_l4_dst_port_incl_get( - a_uint32_t dev_id, - unsigned int *value); - -sw_error_t -hppe_trunk_hash_field_reg_l4_dst_port_incl_set( - a_uint32_t dev_id, - unsigned int value); - -sw_error_t -hppe_trunk_hash_field_reg_udf0_incl_get( - a_uint32_t dev_id, - unsigned int *value); - -sw_error_t -hppe_trunk_hash_field_reg_udf0_incl_set( - a_uint32_t dev_id, - unsigned int value); - -sw_error_t -hppe_trunk_hash_field_reg_dst_ip_incl_get( - a_uint32_t dev_id, - unsigned int *value); - -sw_error_t -hppe_trunk_hash_field_reg_dst_ip_incl_set( - a_uint32_t dev_id, - unsigned int value); - -sw_error_t -hppe_trunk_hash_field_reg_l4_src_port_incl_get( - a_uint32_t dev_id, - unsigned int *value); - -sw_error_t -hppe_trunk_hash_field_reg_l4_src_port_incl_set( - a_uint32_t dev_id, - unsigned int value); - -sw_error_t -hppe_trunk_hash_field_reg_src_ip_incl_get( - a_uint32_t dev_id, - unsigned int *value); - -sw_error_t -hppe_trunk_hash_field_reg_src_ip_incl_set( - a_uint32_t dev_id, - unsigned int value); - -sw_error_t -hppe_trunk_hash_field_reg_udf1_incl_get( - a_uint32_t dev_id, - unsigned int *value); - -sw_error_t -hppe_trunk_hash_field_reg_udf1_incl_set( - a_uint32_t dev_id, - unsigned int value); - -sw_error_t -hppe_trunk_hash_field_reg_mac_sa_incl_get( - a_uint32_t dev_id, - unsigned int *value); - -sw_error_t -hppe_trunk_hash_field_reg_mac_sa_incl_set( - a_uint32_t dev_id, - unsigned int value); - -sw_error_t -hppe_trunk_filter_mem_bitmap_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_trunk_filter_mem_bitmap_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_trunk_member_member_2_port_id_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_trunk_member_member_2_port_id_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_trunk_member_member_0_port_id_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_trunk_member_member_0_port_id_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_trunk_member_member_1_port_id_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_trunk_member_member_1_port_id_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_trunk_member_member_6_port_id_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_trunk_member_member_6_port_id_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_trunk_member_member_4_port_id_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_trunk_member_member_4_port_id_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_trunk_member_member_3_port_id_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_trunk_member_member_3_port_id_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_trunk_member_member_5_port_id_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_trunk_member_member_5_port_id_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_trunk_member_member_7_port_id_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_trunk_member_member_7_port_id_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_port_trunk_id_trunk_id_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_port_trunk_id_trunk_id_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_port_trunk_id_trunk_en_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_port_trunk_id_trunk_en_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -#endif - diff --git a/feeds/ipq807x/qca-ssdk/src/include/hsl/hppe/hppe_trunk_reg.h b/feeds/ipq807x/qca-ssdk/src/include/hsl/hppe/hppe_trunk_reg.h deleted file mode 100755 index 7f9af5c61..000000000 --- a/feeds/ipq807x/qca-ssdk/src/include/hsl/hppe/hppe_trunk_reg.h +++ /dev/null @@ -1,230 +0,0 @@ -/* - * Copyright (c) 2016-2017, The Linux Foundation. All rights reserved. - * Permission to use, copy, modify, and/or distribute this software for - * any purpose with or without fee is hereby granted, provided that the - * above copyright notice and this permission notice appear in all copies. - * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES - * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR - * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES - * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN - * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT - * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. - */ - - -/** - * @defgroup - * @{ - */ -#ifndef HPPE_TRUNK_REG_H -#define HPPE_TRUNK_REG_H - -/*[register] TRUNK_HASH_FIELD_REG*/ -#define TRUNK_HASH_FIELD_REG -#define TRUNK_HASH_FIELD_REG_ADDRESS 0x68 -#define TRUNK_HASH_FIELD_REG_NUM 1 -#define TRUNK_HASH_FIELD_REG_INC 0x4 -#define TRUNK_HASH_FIELD_REG_TYPE REG_TYPE_RW -#define TRUNK_HASH_FIELD_REG_DEFAULT 0x0 - /*[field] SRC_PORT_INCL*/ - #define TRUNK_HASH_FIELD_REG_SRC_PORT_INCL - #define TRUNK_HASH_FIELD_REG_SRC_PORT_INCL_OFFSET 0 - #define TRUNK_HASH_FIELD_REG_SRC_PORT_INCL_LEN 1 - #define TRUNK_HASH_FIELD_REG_SRC_PORT_INCL_DEFAULT 0x0 - /*[field] MAC_DA_INCL*/ - #define TRUNK_HASH_FIELD_REG_MAC_DA_INCL - #define TRUNK_HASH_FIELD_REG_MAC_DA_INCL_OFFSET 1 - #define TRUNK_HASH_FIELD_REG_MAC_DA_INCL_LEN 1 - #define TRUNK_HASH_FIELD_REG_MAC_DA_INCL_DEFAULT 0x0 - /*[field] MAC_SA_INCL*/ - #define TRUNK_HASH_FIELD_REG_MAC_SA_INCL - #define TRUNK_HASH_FIELD_REG_MAC_SA_INCL_OFFSET 2 - #define TRUNK_HASH_FIELD_REG_MAC_SA_INCL_LEN 1 - #define TRUNK_HASH_FIELD_REG_MAC_SA_INCL_DEFAULT 0x0 - /*[field] SRC_IP_INCL*/ - #define TRUNK_HASH_FIELD_REG_SRC_IP_INCL - #define TRUNK_HASH_FIELD_REG_SRC_IP_INCL_OFFSET 3 - #define TRUNK_HASH_FIELD_REG_SRC_IP_INCL_LEN 1 - #define TRUNK_HASH_FIELD_REG_SRC_IP_INCL_DEFAULT 0x0 - /*[field] DST_IP_INCL*/ - #define TRUNK_HASH_FIELD_REG_DST_IP_INCL - #define TRUNK_HASH_FIELD_REG_DST_IP_INCL_OFFSET 4 - #define TRUNK_HASH_FIELD_REG_DST_IP_INCL_LEN 1 - #define TRUNK_HASH_FIELD_REG_DST_IP_INCL_DEFAULT 0x0 - /*[field] L4_SRC_PORT_INCL*/ - #define TRUNK_HASH_FIELD_REG_L4_SRC_PORT_INCL - #define TRUNK_HASH_FIELD_REG_L4_SRC_PORT_INCL_OFFSET 5 - #define TRUNK_HASH_FIELD_REG_L4_SRC_PORT_INCL_LEN 1 - #define TRUNK_HASH_FIELD_REG_L4_SRC_PORT_INCL_DEFAULT 0x0 - /*[field] L4_DST_PORT_INCL*/ - #define TRUNK_HASH_FIELD_REG_L4_DST_PORT_INCL - #define TRUNK_HASH_FIELD_REG_L4_DST_PORT_INCL_OFFSET 6 - #define TRUNK_HASH_FIELD_REG_L4_DST_PORT_INCL_LEN 1 - #define TRUNK_HASH_FIELD_REG_L4_DST_PORT_INCL_DEFAULT 0x0 - /*[field] UDF0_INCL*/ - #define TRUNK_HASH_FIELD_REG_UDF0_INCL - #define TRUNK_HASH_FIELD_REG_UDF0_INCL_OFFSET 7 - #define TRUNK_HASH_FIELD_REG_UDF0_INCL_LEN 1 - #define TRUNK_HASH_FIELD_REG_UDF0_INCL_DEFAULT 0x0 - /*[field] UDF1_INCL*/ - #define TRUNK_HASH_FIELD_REG_UDF1_INCL - #define TRUNK_HASH_FIELD_REG_UDF1_INCL_OFFSET 8 - #define TRUNK_HASH_FIELD_REG_UDF1_INCL_LEN 1 - #define TRUNK_HASH_FIELD_REG_UDF1_INCL_DEFAULT 0x0 - /*[field] UDF2_INCL*/ - #define TRUNK_HASH_FIELD_REG_UDF2_INCL - #define TRUNK_HASH_FIELD_REG_UDF2_INCL_OFFSET 9 - #define TRUNK_HASH_FIELD_REG_UDF2_INCL_LEN 1 - #define TRUNK_HASH_FIELD_REG_UDF2_INCL_DEFAULT 0x0 - /*[field] UDF3_INCL*/ - #define TRUNK_HASH_FIELD_REG_UDF3_INCL - #define TRUNK_HASH_FIELD_REG_UDF3_INCL_OFFSET 10 - #define TRUNK_HASH_FIELD_REG_UDF3_INCL_LEN 1 - #define TRUNK_HASH_FIELD_REG_UDF3_INCL_DEFAULT 0x0 - -struct trunk_hash_field_reg { - a_uint32_t src_port_incl:1; - a_uint32_t mac_da_incl:1; - a_uint32_t mac_sa_incl:1; - a_uint32_t src_ip_incl:1; - a_uint32_t dst_ip_incl:1; - a_uint32_t l4_src_port_incl:1; - a_uint32_t l4_dst_port_incl:1; - a_uint32_t udf0_incl:1; - a_uint32_t udf1_incl:1; - a_uint32_t udf2_incl:1; - a_uint32_t udf3_incl:1; - a_uint32_t _reserved0:21; -}; - -union trunk_hash_field_reg_u { - a_uint32_t val; - struct trunk_hash_field_reg bf; -}; - -/*[register] TRUNK_FILTER*/ -#define TRUNK_FILTER -#define TRUNK_FILTER_ADDRESS 0x50 -#define TRUNK_FILTER_NUM 2 -#define TRUNK_FILTER_INC 0x4 -#define TRUNK_FILTER_TYPE REG_TYPE_RW -#define TRUNK_FILTER_DEFAULT 0x0 - /*[field] MEM_BITMAP*/ - #define TRUNK_FILTER_MEM_BITMAP - #define TRUNK_FILTER_MEM_BITMAP_OFFSET 0 - #define TRUNK_FILTER_MEM_BITMAP_LEN 8 - #define TRUNK_FILTER_MEM_BITMAP_DEFAULT 0x0 - -struct trunk_filter { - a_uint32_t mem_bitmap:8; - a_uint32_t _reserved0:24; -}; - -union trunk_filter_u { - a_uint32_t val; - struct trunk_filter bf; -}; - -/*[register] TRUNK_MEMBER*/ -#define TRUNK_MEMBER -#define TRUNK_MEMBER_ADDRESS 0x60 -#define TRUNK_MEMBER_NUM 2 -#define TRUNK_MEMBER_INC 0x4 -#define TRUNK_MEMBER_TYPE REG_TYPE_RW -#define TRUNK_MEMBER_DEFAULT 0x0 - /*[field] MEMBER_0_PORT_ID*/ - #define TRUNK_MEMBER_MEMBER_0_PORT_ID - #define TRUNK_MEMBER_MEMBER_0_PORT_ID_OFFSET 0 - #define TRUNK_MEMBER_MEMBER_0_PORT_ID_LEN 3 - #define TRUNK_MEMBER_MEMBER_0_PORT_ID_DEFAULT 0x0 - /*[field] MEMBER_1_PORT_ID*/ - #define TRUNK_MEMBER_MEMBER_1_PORT_ID - #define TRUNK_MEMBER_MEMBER_1_PORT_ID_OFFSET 4 - #define TRUNK_MEMBER_MEMBER_1_PORT_ID_LEN 3 - #define TRUNK_MEMBER_MEMBER_1_PORT_ID_DEFAULT 0x0 - /*[field] MEMBER_2_PORT_ID*/ - #define TRUNK_MEMBER_MEMBER_2_PORT_ID - #define TRUNK_MEMBER_MEMBER_2_PORT_ID_OFFSET 8 - #define TRUNK_MEMBER_MEMBER_2_PORT_ID_LEN 3 - #define TRUNK_MEMBER_MEMBER_2_PORT_ID_DEFAULT 0x0 - /*[field] MEMBER_3_PORT_ID*/ - #define TRUNK_MEMBER_MEMBER_3_PORT_ID - #define TRUNK_MEMBER_MEMBER_3_PORT_ID_OFFSET 12 - #define TRUNK_MEMBER_MEMBER_3_PORT_ID_LEN 3 - #define TRUNK_MEMBER_MEMBER_3_PORT_ID_DEFAULT 0x0 - /*[field] MEMBER_4_PORT_ID*/ - #define TRUNK_MEMBER_MEMBER_4_PORT_ID - #define TRUNK_MEMBER_MEMBER_4_PORT_ID_OFFSET 16 - #define TRUNK_MEMBER_MEMBER_4_PORT_ID_LEN 3 - #define TRUNK_MEMBER_MEMBER_4_PORT_ID_DEFAULT 0x0 - /*[field] MEMBER_5_PORT_ID*/ - #define TRUNK_MEMBER_MEMBER_5_PORT_ID - #define TRUNK_MEMBER_MEMBER_5_PORT_ID_OFFSET 20 - #define TRUNK_MEMBER_MEMBER_5_PORT_ID_LEN 3 - #define TRUNK_MEMBER_MEMBER_5_PORT_ID_DEFAULT 0x0 - /*[field] MEMBER_6_PORT_ID*/ - #define TRUNK_MEMBER_MEMBER_6_PORT_ID - #define TRUNK_MEMBER_MEMBER_6_PORT_ID_OFFSET 24 - #define TRUNK_MEMBER_MEMBER_6_PORT_ID_LEN 3 - #define TRUNK_MEMBER_MEMBER_6_PORT_ID_DEFAULT 0x0 - /*[field] MEMBER_7_PORT_ID*/ - #define TRUNK_MEMBER_MEMBER_7_PORT_ID - #define TRUNK_MEMBER_MEMBER_7_PORT_ID_OFFSET 28 - #define TRUNK_MEMBER_MEMBER_7_PORT_ID_LEN 3 - #define TRUNK_MEMBER_MEMBER_7_PORT_ID_DEFAULT 0x0 - -struct trunk_member { - a_uint32_t member_0_port_id:3; - a_uint32_t _reserved0:1; - a_uint32_t member_1_port_id:3; - a_uint32_t _reserved1:1; - a_uint32_t member_2_port_id:3; - a_uint32_t _reserved2:1; - a_uint32_t member_3_port_id:3; - a_uint32_t _reserved3:1; - a_uint32_t member_4_port_id:3; - a_uint32_t _reserved4:1; - a_uint32_t member_5_port_id:3; - a_uint32_t _reserved5:1; - a_uint32_t member_6_port_id:3; - a_uint32_t _reserved6:1; - a_uint32_t member_7_port_id:3; - a_uint32_t _reserved7:1; -}; - -union trunk_member_u { - a_uint32_t val; - struct trunk_member bf; -}; - -/*[register] PORT_TRUNK_ID*/ -#define PORT_TRUNK_ID -#define PORT_TRUNK_ID_ADDRESS 0x600 -#define PORT_TRUNK_ID_NUM 8 -#define PORT_TRUNK_ID_INC 0x4 -#define PORT_TRUNK_ID_TYPE REG_TYPE_RW -#define PORT_TRUNK_ID_DEFAULT 0x0 - /*[field] TRUNK_EN*/ - #define PORT_TRUNK_ID_TRUNK_EN - #define PORT_TRUNK_ID_TRUNK_EN_OFFSET 0 - #define PORT_TRUNK_ID_TRUNK_EN_LEN 1 - #define PORT_TRUNK_ID_TRUNK_EN_DEFAULT 0x0 - /*[field] TRUNK_ID*/ - #define PORT_TRUNK_ID_TRUNK_ID - #define PORT_TRUNK_ID_TRUNK_ID_OFFSET 1 - #define PORT_TRUNK_ID_TRUNK_ID_LEN 1 - #define PORT_TRUNK_ID_TRUNK_ID_DEFAULT 0x0 - -struct port_trunk_id { - a_uint32_t trunk_en:1; - a_uint32_t trunk_id:1; - a_uint32_t _reserved0:30; -}; - -union port_trunk_id_u { - a_uint32_t val; - struct port_trunk_id bf; -}; - -#endif diff --git a/feeds/ipq807x/qca-ssdk/src/include/hsl/hppe/hppe_uniphy.h b/feeds/ipq807x/qca-ssdk/src/include/hsl/hppe/hppe_uniphy.h deleted file mode 100755 index c41c5bb0d..000000000 --- a/feeds/ipq807x/qca-ssdk/src/include/hsl/hppe/hppe_uniphy.h +++ /dev/null @@ -1,2440 +0,0 @@ -/* - * Copyright (c) 2017, 2019-2020, The Linux Foundation. All rights reserved. - * Permission to use, copy, modify, and/or distribute this software for - * any purpose with or without fee is hereby granted, provided that the - * above copyright notice and this permission notice appear in all copies. - * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES - * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR - * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES - * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN - * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT - * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. - */ - - -/** - * @defgroup - * @{ - */ -#ifndef _HPPE_UNIPHY_H_ -#define _HPPE_UNIPHY_H_ - -#define UNIPHY_OFFSET_CALIB_4_MAX_ENTRY 3 -#define UNIPHY_MODE_CTRL_MAX_ENTRY 3 -#define UNIPHY_CHANNEL0_INPUT_OUTPUT_4_MAX_ENTRY 3 -#define UNIPHY_CHANNEL1_INPUT_OUTPUT_4_MAX_ENTRY 3 -#define UNIPHY_CHANNEL2_INPUT_OUTPUT_4_MAX_ENTRY 3 -#define UNIPHY_CHANNEL3_INPUT_OUTPUT_4_MAX_ENTRY 3 -#define UNIPHY_CHANNEL4_INPUT_OUTPUT_4_MAX_ENTRY 3 -#define SR_XS_PCS_KR_STS1_MAX_ENTRY 3 -#define VR_XS_PCS_DIG_CTRL1_MAX_ENTRY 3 -#define SR_MII_CTRL_MAX_ENTRY 3 -#define VR_MII_AN_CTRL_MAX_ENTRY 3 -#define VR_MII_AN_INTR_STS_MAX_ENTRY 3 - -#define UNIPHY_PLL_CONTROL_VCO_RELATED_SELECTION_MAX_ENTRY 3 -#define UNIPHY_TX_AC_JTAG_MUX_DRIVER_SELECTION_MAX_ENTRY 3 -#define UNIPHY_RESISTOR_CALIBRATION_1_MAX_ENTRY 3 -#define UNIPHY_PLL_VCO_RELATED_CONTROL_1_MAX_ENTRY 3 -#define UNIPHY_RX_AFE_2_MAX_ENTRY 3 -#define BANDGAP_IP_MBIAS_2_MAX_ENTRY 4 -#define LDO_0P9V_RELATED_1_MAX_ENTRY 4 -#define OTP_VTT_LDO_RELATED_MAX_ENTRY 4 -#define OTP_TEMPERATURE_COMPENSATE_1_MAX_ENTRY 4 -#define PLL_VCO_RELATED_CONTROL_1_MAX_ENTRY 4 -#define PLL_CONTROL_VCO_RELATED_SELECTION_2_MAX_ENTRY 4 -#define UNIPHY_MISC2_PHY_MODE_MAX_ENTRY 4 -#define UNIPHY_PLL_POWER_ON_AND_RESET_INC_MAX_ENTRY 4 - -sw_error_t -hppe_uniphy_offset_calib_4_get( - a_uint32_t dev_id, - a_uint32_t index, - union uniphy_offset_calib_4_u *value); - -sw_error_t -hppe_uniphy_offset_calib_4_set( - a_uint32_t dev_id, - a_uint32_t index, - union uniphy_offset_calib_4_u *value); - -sw_error_t -hppe_uniphy_mode_ctrl_get( - a_uint32_t dev_id, - a_uint32_t index, - union uniphy_mode_ctrl_u *value); - -sw_error_t -hppe_uniphy_mode_ctrl_set( - a_uint32_t dev_id, - a_uint32_t index, - union uniphy_mode_ctrl_u *value); - -sw_error_t -hppe_uniphy_channel0_input_output_4_get( - a_uint32_t dev_id, - a_uint32_t index, - union uniphy_channel0_input_output_4_u *value); - -sw_error_t -hppe_uniphy_channel0_input_output_4_set( - a_uint32_t dev_id, - a_uint32_t index, - union uniphy_channel0_input_output_4_u *value); - -sw_error_t -hppe_uniphy_channel1_input_output_4_get( - a_uint32_t dev_id, - a_uint32_t index, - union uniphy_channel1_input_output_4_u *value); - -sw_error_t -hppe_uniphy_channel1_input_output_4_set( - a_uint32_t dev_id, - a_uint32_t index, - union uniphy_channel1_input_output_4_u *value); - -sw_error_t -hppe_uniphy_channel2_input_output_4_get( - a_uint32_t dev_id, - a_uint32_t index, - union uniphy_channel2_input_output_4_u *value); - -sw_error_t -hppe_uniphy_channel2_input_output_4_set( - a_uint32_t dev_id, - a_uint32_t index, - union uniphy_channel2_input_output_4_u *value); - -sw_error_t -hppe_uniphy_channel3_input_output_4_get( - a_uint32_t dev_id, - a_uint32_t index, - union uniphy_channel3_input_output_4_u *value); - -sw_error_t -hppe_uniphy_channel3_input_output_4_set( - a_uint32_t dev_id, - a_uint32_t index, - union uniphy_channel3_input_output_4_u *value); - -sw_error_t -hppe_uniphy_channel4_input_output_4_get( - a_uint32_t dev_id, - a_uint32_t index, - union uniphy_channel4_input_output_4_u *value); - -sw_error_t -hppe_uniphy_channel4_input_output_4_set( - a_uint32_t dev_id, - a_uint32_t index, - union uniphy_channel4_input_output_4_u *value); - -sw_error_t -hppe_uniphy_instance_link_detect_get( - a_uint32_t dev_id, - a_uint32_t index, - union uniphy_instance_link_detect_u *value); - -sw_error_t -hppe_uniphy_instance_link_detect_set( - a_uint32_t dev_id, - a_uint32_t index, - union uniphy_instance_link_detect_u *value); - - -sw_error_t -hppe_sr_xs_pcs_kr_sts1_get( - a_uint32_t dev_id, - a_uint32_t index, - union sr_xs_pcs_kr_sts1_u *value); - -sw_error_t -hppe_sr_xs_pcs_kr_sts1_set( - a_uint32_t dev_id, - a_uint32_t index, - union sr_xs_pcs_kr_sts1_u *value); - -sw_error_t -hppe_vr_xs_pcs_dig_ctrl1_get( - a_uint32_t dev_id, - a_uint32_t index, - union vr_xs_pcs_dig_ctrl1_u *value); - -sw_error_t -hppe_vr_xs_pcs_dig_ctrl1_set( - a_uint32_t dev_id, - a_uint32_t index, - union vr_xs_pcs_dig_ctrl1_u *value); - -sw_error_t -hppe_sr_mii_ctrl_get( - a_uint32_t dev_id, - a_uint32_t index, - union sr_mii_ctrl_u *value); - -sw_error_t -hppe_sr_mii_ctrl_set( - a_uint32_t dev_id, - a_uint32_t index, - union sr_mii_ctrl_u *value); - -sw_error_t -hppe_vr_mii_an_ctrl_get( - a_uint32_t dev_id, - a_uint32_t index, - union vr_mii_an_ctrl_u *value); - -sw_error_t -hppe_vr_mii_an_ctrl_set( - a_uint32_t dev_id, - a_uint32_t index, - union vr_mii_an_ctrl_u *value); - -sw_error_t -hppe_vr_mii_an_intr_sts_get( - a_uint32_t dev_id, - a_uint32_t index, - union vr_mii_an_intr_sts_u *value); - -sw_error_t -hppe_vr_mii_an_intr_sts_set( - a_uint32_t dev_id, - a_uint32_t index, - union vr_mii_an_intr_sts_u *value); - -sw_error_t -hppe_uniphy_offset_calib_4_mmd1_reg_cal_rep_time_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_uniphy_offset_calib_4_mmd1_reg_cal_rep_time_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_uniphy_offset_calib_4_mmd1_reg_pll_locked_reg_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_uniphy_offset_calib_4_mmd1_reg_pll_locked_reg_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_uniphy_offset_calib_4_mmd1_reg_clr_sampler_calib_timeout_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_uniphy_offset_calib_4_mmd1_reg_clr_sampler_calib_timeout_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_uniphy_offset_calib_4_mmd1_reg_lockdet_lckdt_reg_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_uniphy_offset_calib_4_mmd1_reg_lockdet_lckdt_reg_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_uniphy_offset_calib_4_mmd1_reg_cal_detect_time_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_uniphy_offset_calib_4_mmd1_reg_cal_detect_time_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_uniphy_offset_calib_4_mmd1_reg_calibration_done_reg_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_uniphy_offset_calib_4_mmd1_reg_calibration_done_reg_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_uniphy_offset_calib_4_mmd1_reg_smpl_cal_ready_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_uniphy_offset_calib_4_mmd1_reg_smpl_cal_ready_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_uniphy_mode_ctrl_newaddedfromhere_ch1_ch0_sgmii_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_uniphy_mode_ctrl_newaddedfromhere_ch1_ch0_sgmii_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_uniphy_mode_ctrl_newaddedfromhere_usxg_en_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_uniphy_mode_ctrl_newaddedfromhere_usxg_en_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_uniphy_mode_ctrl_newaddedfromhere_ch4_ch1_0_sgmii_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_uniphy_mode_ctrl_newaddedfromhere_ch4_ch1_0_sgmii_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_uniphy_mode_ctrl_newaddedfromhere_sgplus_mode_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_uniphy_mode_ctrl_newaddedfromhere_sgplus_mode_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_uniphy_mode_ctrl_newaddedfromhere_xpcs_mode_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_uniphy_mode_ctrl_newaddedfromhere_xpcs_mode_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_uniphy_mode_ctrl_newaddedfromhere_ch0_psgmii_qsgmii_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_uniphy_mode_ctrl_newaddedfromhere_ch0_psgmii_qsgmii_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_uniphy_mode_ctrl_newaddedfromhere_ch0_autoneg_mode_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_uniphy_mode_ctrl_newaddedfromhere_ch0_autoneg_mode_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_uniphy_mode_ctrl_newaddedfromhere_sw_v17_v18_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_uniphy_mode_ctrl_newaddedfromhere_sw_v17_v18_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_uniphy_mode_ctrl_newaddedfromhere_ch0_mode_ctrl_25m_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_uniphy_mode_ctrl_newaddedfromhere_ch0_mode_ctrl_25m_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_uniphy_mode_ctrl_newaddedfromhere_sgmii_even_low_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_uniphy_mode_ctrl_newaddedfromhere_sgmii_even_low_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_uniphy_mode_ctrl_newaddedfromhere_ch0_qsgmii_sgmii_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_uniphy_mode_ctrl_newaddedfromhere_ch0_qsgmii_sgmii_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_uniphy_mode_ctrl_newaddedfromhere_sg_mode_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_uniphy_mode_ctrl_newaddedfromhere_sg_mode_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_uniphy_channel0_input_output_4_newaddedfromhere_ch0_mr_restart_an_25m_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_uniphy_channel0_input_output_4_newaddedfromhere_ch0_mr_restart_an_25m_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_uniphy_channel0_input_output_4_newaddedfromhere_ch0_rem_phy_lpbk_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_uniphy_channel0_input_output_4_newaddedfromhere_ch0_rem_phy_lpbk_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_uniphy_channel0_input_output_4_newaddedfromhere_ch0_mr_reg4_ch_25m_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_uniphy_channel0_input_output_4_newaddedfromhere_ch0_mr_reg4_ch_25m_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_uniphy_channel0_input_output_4_newaddedfromhere_ch0_power_on_25m_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_uniphy_channel0_input_output_4_newaddedfromhere_ch0_power_on_25m_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_uniphy_channel0_input_output_4_newaddedfromhere_ch0_mr_main_reset_25m_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_uniphy_channel0_input_output_4_newaddedfromhere_ch0_mr_main_reset_25m_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_uniphy_channel0_force_speed_mode_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_uniphy_channel0_force_speed_mode_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_uniphy_channel0_input_output_4_newaddedfromhere_ch0_adp_sw_rstn_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_uniphy_channel0_input_output_4_newaddedfromhere_ch0_adp_sw_rstn_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_uniphy_channel0_input_output_4_newaddedfromhere_ch0_speed_25m_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_uniphy_channel0_input_output_4_newaddedfromhere_ch0_speed_25m_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_uniphy_channel0_input_output_4_newaddedfromhere_ch0_mr_an_enable_25m_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_uniphy_channel0_input_output_4_newaddedfromhere_ch0_mr_an_enable_25m_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_uniphy_channel0_input_output_4_newaddedfromhere_ch0_mr_np_loaded_25m_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_uniphy_channel0_input_output_4_newaddedfromhere_ch0_mr_np_loaded_25m_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_uniphy_channel0_input_output_4_newaddedfromhere_ch0_mr_loopback_25m_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_uniphy_channel0_input_output_4_newaddedfromhere_ch0_mr_loopback_25m_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_uniphy_channel1_input_output_4_newaddedfromhere_ch1_adp_sw_rstn_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_uniphy_channel1_input_output_4_newaddedfromhere_ch1_adp_sw_rstn_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_uniphy_channel1_input_output_4_newaddedfromhere_ch1_power_on_25m_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_uniphy_channel1_input_output_4_newaddedfromhere_ch1_power_on_25m_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_uniphy_channel1_input_output_4_newaddedfromhere_ch1_mr_main_reset_25m_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_uniphy_channel1_input_output_4_newaddedfromhere_ch1_mr_main_reset_25m_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_uniphy_channel1_input_output_4_newaddedfromhere_ch1_mr_an_enable_25m_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_uniphy_channel1_input_output_4_newaddedfromhere_ch1_mr_an_enable_25m_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_uniphy_channel1_input_output_4_newaddedfromhere_ch1_speed_25m_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_uniphy_channel1_input_output_4_newaddedfromhere_ch1_speed_25m_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_uniphy_channel1_input_output_4_newaddedfromhere_ch1_rem_phy_lpbk_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_uniphy_channel1_input_output_4_newaddedfromhere_ch1_rem_phy_lpbk_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_uniphy_channel1_input_output_4_newaddedfromhere_ch1_mr_reg4_ch_25m_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_uniphy_channel1_input_output_4_newaddedfromhere_ch1_mr_reg4_ch_25m_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_uniphy_channel1_input_output_4_newaddedfromhere_ch1_mr_np_loaded_25m_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_uniphy_channel1_input_output_4_newaddedfromhere_ch1_mr_np_loaded_25m_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_uniphy_channel1_input_output_4_newaddedfromhere_ch1_force_speed_25m_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_uniphy_channel1_input_output_4_newaddedfromhere_ch1_force_speed_25m_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_uniphy_channel1_input_output_4_newaddedfromhere_ch1_mr_restart_an_25m_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_uniphy_channel1_input_output_4_newaddedfromhere_ch1_mr_restart_an_25m_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_uniphy_channel1_input_output_4_newaddedfromhere_ch1_mr_loopback_25m_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_uniphy_channel1_input_output_4_newaddedfromhere_ch1_mr_loopback_25m_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_uniphy_channel2_input_output_4_newaddedfromhere_ch2_rem_phy_lpbk_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_uniphy_channel2_input_output_4_newaddedfromhere_ch2_rem_phy_lpbk_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_uniphy_channel2_input_output_4_newaddedfromhere_ch2_adp_sw_rstn_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_uniphy_channel2_input_output_4_newaddedfromhere_ch2_adp_sw_rstn_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_uniphy_channel2_input_output_4_newaddedfromhere_ch2_mr_main_reset_25m_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_uniphy_channel2_input_output_4_newaddedfromhere_ch2_mr_main_reset_25m_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_uniphy_channel2_input_output_4_newaddedfromhere_ch2_mr_loopback_25m_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_uniphy_channel2_input_output_4_newaddedfromhere_ch2_mr_loopback_25m_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_uniphy_channel2_input_output_4_newaddedfromhere_ch2_mr_restart_an_25m_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_uniphy_channel2_input_output_4_newaddedfromhere_ch2_mr_restart_an_25m_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_uniphy_channel2_input_output_4_newaddedfromhere_ch2_speed_25m_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_uniphy_channel2_input_output_4_newaddedfromhere_ch2_speed_25m_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_uniphy_channel2_input_output_4_newaddedfromhere_ch2_mr_np_loaded_25m_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_uniphy_channel2_input_output_4_newaddedfromhere_ch2_mr_np_loaded_25m_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_uniphy_channel2_input_output_4_newaddedfromhere_ch2_force_speed_25m_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_uniphy_channel2_input_output_4_newaddedfromhere_ch2_force_speed_25m_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_uniphy_channel2_input_output_4_newaddedfromhere_ch2_mr_an_enable_25m_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_uniphy_channel2_input_output_4_newaddedfromhere_ch2_mr_an_enable_25m_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_uniphy_channel2_input_output_4_newaddedfromhere_ch2_power_on_25m_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_uniphy_channel2_input_output_4_newaddedfromhere_ch2_power_on_25m_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_uniphy_channel2_input_output_4_newaddedfromhere_ch2_mr_reg4_ch_25m_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_uniphy_channel2_input_output_4_newaddedfromhere_ch2_mr_reg4_ch_25m_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_uniphy_channel3_input_output_4_newaddedfromhere_ch3_mr_main_reset_25m_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_uniphy_channel3_input_output_4_newaddedfromhere_ch3_mr_main_reset_25m_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_uniphy_channel3_input_output_4_newaddedfromhere_ch3_speed_25m_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_uniphy_channel3_input_output_4_newaddedfromhere_ch3_speed_25m_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_uniphy_channel3_input_output_4_newaddedfromhere_ch3_mr_np_loaded_25m_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_uniphy_channel3_input_output_4_newaddedfromhere_ch3_mr_np_loaded_25m_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_uniphy_channel3_input_output_4_newaddedfromhere_ch3_adp_sw_rstn_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_uniphy_channel3_input_output_4_newaddedfromhere_ch3_adp_sw_rstn_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_uniphy_channel3_input_output_4_newaddedfromhere_ch3_power_on_25m_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_uniphy_channel3_input_output_4_newaddedfromhere_ch3_power_on_25m_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_uniphy_channel3_input_output_4_newaddedfromhere_ch3_mr_an_enable_25m_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_uniphy_channel3_input_output_4_newaddedfromhere_ch3_mr_an_enable_25m_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_uniphy_channel3_input_output_4_newaddedfromhere_ch3_mr_reg4_ch_25m_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_uniphy_channel3_input_output_4_newaddedfromhere_ch3_mr_reg4_ch_25m_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_uniphy_channel3_input_output_4_newaddedfromhere_ch3_mr_restart_an_25m_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_uniphy_channel3_input_output_4_newaddedfromhere_ch3_mr_restart_an_25m_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_uniphy_channel3_input_output_4_newaddedfromhere_ch3_rem_phy_lpbk_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_uniphy_channel3_input_output_4_newaddedfromhere_ch3_rem_phy_lpbk_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_uniphy_channel3_input_output_4_newaddedfromhere_ch3_force_speed_25m_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_uniphy_channel3_input_output_4_newaddedfromhere_ch3_force_speed_25m_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_uniphy_channel3_input_output_4_newaddedfromhere_ch3_mr_loopback_25m_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_uniphy_channel3_input_output_4_newaddedfromhere_ch3_mr_loopback_25m_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_uniphy_channel4_input_output_4_newaddedfromhere_ch4_mr_loopback_25m_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_uniphy_channel4_input_output_4_newaddedfromhere_ch4_mr_loopback_25m_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_uniphy_channel4_input_output_4_newaddedfromhere_ch4_mr_reg4_ch_25m_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_uniphy_channel4_input_output_4_newaddedfromhere_ch4_mr_reg4_ch_25m_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_uniphy_channel4_input_output_4_newaddedfromhere_ch4_mr_restart_an_25m_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_uniphy_channel4_input_output_4_newaddedfromhere_ch4_mr_restart_an_25m_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_uniphy_channel4_input_output_4_newaddedfromhere_ch4_mr_an_enable_25m_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_uniphy_channel4_input_output_4_newaddedfromhere_ch4_mr_an_enable_25m_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_uniphy_channel4_input_output_4_newaddedfromhere_ch4_force_speed_25m_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_uniphy_channel4_input_output_4_newaddedfromhere_ch4_force_speed_25m_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_uniphy_channel4_input_output_4_newaddedfromhere_ch4_mr_main_reset_25m_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_uniphy_channel4_input_output_4_newaddedfromhere_ch4_mr_main_reset_25m_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_uniphy_channel4_input_output_4_newaddedfromhere_ch4_power_on_25m_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_uniphy_channel4_input_output_4_newaddedfromhere_ch4_power_on_25m_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_uniphy_channel4_input_output_4_newaddedfromhere_ch4_speed_25m_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_uniphy_channel4_input_output_4_newaddedfromhere_ch4_speed_25m_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_uniphy_channel4_input_output_4_newaddedfromhere_ch4_rem_phy_lpbk_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_uniphy_channel4_input_output_4_newaddedfromhere_ch4_rem_phy_lpbk_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_uniphy_channel4_input_output_4_newaddedfromhere_ch4_mr_np_loaded_25m_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_uniphy_channel4_input_output_4_newaddedfromhere_ch4_mr_np_loaded_25m_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_uniphy_channel4_input_output_4_newaddedfromhere_ch4_adp_sw_rstn_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_uniphy_channel4_input_output_4_newaddedfromhere_ch4_adp_sw_rstn_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_sr_xs_pcs_kr_sts1_plu_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_sr_xs_pcs_kr_sts1_plu_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_sr_xs_pcs_kr_sts1_prbs31abl_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_sr_xs_pcs_kr_sts1_prbs31abl_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_sr_xs_pcs_kr_sts1_rpcs_bklk_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_sr_xs_pcs_kr_sts1_rpcs_bklk_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_sr_xs_pcs_kr_sts1_prcs_hiber_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_sr_xs_pcs_kr_sts1_prcs_hiber_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_sr_xs_pcs_kr_sts1_prbs9abl_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_sr_xs_pcs_kr_sts1_prbs9abl_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_vr_xs_pcs_dig_ctrl1_vr_rst_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_vr_xs_pcs_dig_ctrl1_vr_rst_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_vr_xs_pcs_dig_ctrl1_usra_rst_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_vr_xs_pcs_dig_ctrl1_usra_rst_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_vr_xs_pcs_dig_ctrl1_en_2_5g_mode_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_vr_xs_pcs_dig_ctrl1_en_2_5g_mode_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_vr_xs_pcs_dig_ctrl1_dskbyp_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_vr_xs_pcs_dig_ctrl1_dskbyp_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_vr_xs_pcs_dig_ctrl1_en_vsmmd1_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_vr_xs_pcs_dig_ctrl1_en_vsmmd1_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_vr_xs_pcs_dig_ctrl1_init_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_vr_xs_pcs_dig_ctrl1_init_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_vr_xs_pcs_dig_ctrl1_cl37_bp_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_vr_xs_pcs_dig_ctrl1_cl37_bp_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_vr_xs_pcs_dig_ctrl1_pwrsv_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_vr_xs_pcs_dig_ctrl1_pwrsv_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_vr_xs_pcs_dig_ctrl1_dtxlaned_3_1_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_vr_xs_pcs_dig_ctrl1_dtxlaned_3_1_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_vr_xs_pcs_dig_ctrl1_usxg_en_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_vr_xs_pcs_dig_ctrl1_usxg_en_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_vr_xs_pcs_dig_ctrl1_r2tlbe_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_vr_xs_pcs_dig_ctrl1_r2tlbe_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_vr_xs_pcs_dig_ctrl1_cr_cjn_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_vr_xs_pcs_dig_ctrl1_cr_cjn_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_vr_xs_pcs_dig_ctrl1_dtxlaned_0_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_vr_xs_pcs_dig_ctrl1_dtxlaned_0_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_vr_xs_pcs_dig_ctrl1_byp_pwrup_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_vr_xs_pcs_dig_ctrl1_byp_pwrup_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_sr_mii_ctrl_lpm_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_sr_mii_ctrl_lpm_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_sr_mii_ctrl_duplex_mode_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_sr_mii_ctrl_duplex_mode_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_sr_mii_ctrl_ss6_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_sr_mii_ctrl_ss6_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_sr_mii_ctrl_ss5_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_sr_mii_ctrl_ss5_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_sr_mii_ctrl_ss13_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_sr_mii_ctrl_ss13_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_sr_mii_ctrl_an_enable_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_sr_mii_ctrl_an_enable_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_sr_mii_ctrl_restart_an_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_sr_mii_ctrl_restart_an_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_sr_mii_ctrl_rst_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_sr_mii_ctrl_rst_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_sr_mii_ctrl_lbe_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_sr_mii_ctrl_lbe_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_vr_mii_an_ctrl_pcs_mode_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_vr_mii_an_ctrl_pcs_mode_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_vr_mii_an_ctrl_mii_an_intr_en_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_vr_mii_an_ctrl_mii_an_intr_en_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_vr_mii_an_ctrl_sgmii_link_sts_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_vr_mii_an_ctrl_sgmii_link_sts_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_vr_mii_an_ctrl_tx_config_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_vr_mii_an_ctrl_tx_config_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_vr_mii_an_ctrl_mii_ctrl_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_vr_mii_an_ctrl_mii_ctrl_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_vr_mii_an_intr_sts_usxg_an_sts_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_vr_mii_an_intr_sts_usxg_an_sts_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_vr_mii_an_intr_sts_cl37_ansgm_sts_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_vr_mii_an_intr_sts_cl37_ansgm_sts_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_vr_mii_an_intr_sts_cl37_ancmplt_intr_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_vr_mii_an_intr_sts_cl37_ancmplt_intr_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_uniphy_pll_control_vco_related_selection_get( - a_uint32_t dev_id, - a_uint32_t index, - union uniphy_pll_control_vco_related_selection_u *value); - -sw_error_t -hppe_uniphy_pll_control_vco_related_selection_set( - a_uint32_t dev_id, - a_uint32_t index, - union uniphy_pll_control_vco_related_selection_u *value); - -sw_error_t -hppe_uniphy_tx_ac_jtag_mux_driver_selection_get( - a_uint32_t dev_id, - a_uint32_t index, - union uniphy_tx_ac_jtag_mux_driver_selection_u *value); - -sw_error_t -hppe_uniphy_tx_ac_jtag_mux_driver_selection_set( - a_uint32_t dev_id, - a_uint32_t index, - union uniphy_tx_ac_jtag_mux_driver_selection_u *value); - -sw_error_t -hppe_uniphy_resistor_calibration_1_get( - a_uint32_t dev_id, - a_uint32_t index, - union uniphy_resistor_calibration_1_u *value); - -sw_error_t -hppe_uniphy_resistor_calibration_1_set( - a_uint32_t dev_id, - a_uint32_t index, - union uniphy_resistor_calibration_1_u *value); - -sw_error_t -hppe_uniphy_pll_vco_related_control_1_get( - a_uint32_t dev_id, - a_uint32_t index, - union uniphy_pll_vco_related_control_1_u *value); - -sw_error_t -hppe_uniphy_pll_vco_related_control_1_set( - a_uint32_t dev_id, - a_uint32_t index, - union uniphy_pll_vco_related_control_1_u *value); - -sw_error_t -hppe_uniphy_rx_afe_2_get( - a_uint32_t dev_id, - a_uint32_t index, - union uniphy_rx_afe_2_u *value); - -sw_error_t -hppe_uniphy_rx_afe_2_set( - a_uint32_t dev_id, - a_uint32_t index, - union uniphy_rx_afe_2_u *value); - -sw_error_t -hppe_bandgap_ip_mbias_2_get( - a_uint32_t dev_id, - a_uint32_t index, - union bandgap_ip_mbias_2_u *value); - -sw_error_t -hppe_bandgap_ip_mbias_2_set( - a_uint32_t dev_id, - a_uint32_t index, - union bandgap_ip_mbias_2_u *value); - -sw_error_t -hppe_ldo_0p9v_related_1_get( - a_uint32_t dev_id, - a_uint32_t index, - union ldo_0p9v_related_1_u *value); - -sw_error_t -hppe_ldo_0p9v_related_1_set( - a_uint32_t dev_id, - a_uint32_t index, - union ldo_0p9v_related_1_u *value); - -sw_error_t -hppe_otp_vtt_ldo_related_get( - a_uint32_t dev_id, - a_uint32_t index, - union otp_vtt_ldo_related_u *value); - -sw_error_t -hppe_otp_vtt_ldo_related_set( - a_uint32_t dev_id, - a_uint32_t index, - union otp_vtt_ldo_related_u *value); - -sw_error_t -hppe_otp_temperature_compensate_1_get( - a_uint32_t dev_id, - a_uint32_t index, - union otp_temperature_compensate_1_u *value); - -sw_error_t -hppe_otp_temperature_compensate_1_set( - a_uint32_t dev_id, - a_uint32_t index, - union otp_temperature_compensate_1_u *value); - -sw_error_t -hppe_pll_vco_related_control_1_get( - a_uint32_t dev_id, - a_uint32_t index, - union pll_vco_related_control_1_u *value); - -sw_error_t -hppe_pll_vco_related_control_1_set( - a_uint32_t dev_id, - a_uint32_t index, - union pll_vco_related_control_1_u *value); - -sw_error_t -hppe_pll_control_vco_related_selection_2_get( - a_uint32_t dev_id, - a_uint32_t index, - union pll_control_vco_related_selection_2_u *value); - -sw_error_t -hppe_pll_control_vco_related_selection_2_set( - a_uint32_t dev_id, - a_uint32_t index, - union pll_control_vco_related_selection_2_u *value); - -sw_error_t -hppe_uniphy_pll_control_vco_related_selection_mmd1_reg_src_uphy_pll_vco_gain_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_uniphy_pll_control_vco_related_selection_mmd1_reg_src_uphy_pll_vco_gain_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_uniphy_pll_control_vco_related_selection_mmd1_reg_src_uphy_pll_vco_temp_cmp_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_uniphy_pll_control_vco_related_selection_mmd1_reg_src_uphy_pll_vco_temp_cmp_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_uniphy_pll_control_vco_related_selection_mmd1_reg_src_uphy_pll_lpf_c2_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_uniphy_pll_control_vco_related_selection_mmd1_reg_src_uphy_pll_lpf_c2_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_uniphy_pll_control_vco_related_selection_mmd1_reg_src_uphy_pll_vco_amp_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_uniphy_pll_control_vco_related_selection_mmd1_reg_src_uphy_pll_vco_amp_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_uniphy_pll_control_vco_related_selection_mmd1_reg_src_uphy_pll_lpf_dc_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_uniphy_pll_control_vco_related_selection_mmd1_reg_src_uphy_pll_lpf_dc_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_uniphy_pll_control_vco_related_selection_mmd1_reg_src_uphy_pll_cp_sel_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_uniphy_pll_control_vco_related_selection_mmd1_reg_src_uphy_pll_cp_sel_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_uniphy_pll_control_vco_related_selection_mmd1_reg_src_uphy_pll_lpf_res_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_uniphy_pll_control_vco_related_selection_mmd1_reg_src_uphy_pll_lpf_res_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_uniphy_tx_ac_jtag_mux_driver_selection_mmd1_reg_src_uphy_tx_vcm_delta_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_uniphy_tx_ac_jtag_mux_driver_selection_mmd1_reg_src_uphy_tx_vcm_delta_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_uniphy_tx_ac_jtag_mux_driver_selection_mmd1_reg_src_uphy_tx_emp_lsb_en_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_uniphy_tx_ac_jtag_mux_driver_selection_mmd1_reg_src_uphy_tx_emp_lsb_en_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_uniphy_tx_ac_jtag_mux_driver_selection_mmd1_reg_src_uphy_tx_emp_lvl_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_uniphy_tx_ac_jtag_mux_driver_selection_mmd1_reg_src_uphy_tx_emp_lvl_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_uniphy_tx_ac_jtag_mux_driver_selection_mmd1_reg_src_uphy_tx_acjtag_beacon_en_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_uniphy_tx_ac_jtag_mux_driver_selection_mmd1_reg_src_uphy_tx_acjtag_beacon_en_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_uniphy_tx_ac_jtag_mux_driver_selection_mmd1_reg_src_uphy_tx_en_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_uniphy_tx_ac_jtag_mux_driver_selection_mmd1_reg_src_uphy_tx_en_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_uniphy_tx_ac_jtag_mux_driver_selection_mmd1_reg_src_uphy_txd_bit_width_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_uniphy_tx_ac_jtag_mux_driver_selection_mmd1_reg_src_uphy_txd_bit_width_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_uniphy_tx_ac_jtag_mux_driver_selection_mmd1_reg_src_uphy_tx_rescal_code_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_uniphy_tx_ac_jtag_mux_driver_selection_mmd1_reg_src_uphy_tx_rescal_code_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_uniphy_tx_ac_jtag_mux_driver_selection_mmd1_reg_src_uphy_tx_amp_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_uniphy_tx_ac_jtag_mux_driver_selection_mmd1_reg_src_uphy_tx_amp_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_uniphy_resistor_calibration_1_mmd1_reg_disable_load_res_txrx_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_uniphy_resistor_calibration_1_mmd1_reg_disable_load_res_txrx_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_uniphy_resistor_calibration_1_mmd1_reg_calib_tx_reg_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_uniphy_resistor_calibration_1_mmd1_reg_calib_tx_reg_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_uniphy_resistor_calibration_1_mmd1_reg_calib_rx_reg_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_uniphy_resistor_calibration_1_mmd1_reg_calib_rx_reg_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_uniphy_resistor_calibration_1_mmd1_reg_vref_lvl_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_uniphy_resistor_calibration_1_mmd1_reg_vref_lvl_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_uniphy_pll_vco_related_control_1_miireg_uphy_pll_lckdt_en_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_uniphy_pll_vco_related_control_1_miireg_uphy_pll_lckdt_en_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_uniphy_pll_vco_related_control_1_miireg_autoload_sel_pll_vco_calib_ready_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_uniphy_pll_vco_related_control_1_miireg_autoload_sel_pll_vco_calib_ready_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_uniphy_pll_vco_related_control_1_miireg_reg_uphy_pll_vco_calib_ready_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_uniphy_pll_vco_related_control_1_miireg_reg_uphy_pll_vco_calib_ready_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_uniphy_pll_vco_related_control_1_miireg_reg_uphy_pll_vco_temp_cmp_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_uniphy_pll_vco_related_control_1_miireg_reg_uphy_pll_vco_temp_cmp_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_uniphy_pll_vco_related_control_1_miireg_reg_uphy_pll_vco_amp_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_uniphy_pll_vco_related_control_1_miireg_reg_uphy_pll_vco_amp_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_uniphy_pll_vco_related_control_1_miireg_reg_uphy_pll_vco_gain_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_uniphy_pll_vco_related_control_1_miireg_reg_uphy_pll_vco_gain_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_uniphy_rx_afe_2_miireg_reg_uphy_rx_afe_res1_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_uniphy_rx_afe_2_miireg_reg_uphy_rx_afe_res1_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_uniphy_rx_afe_2_miireg_reg_uphy_rx_afe_cap1_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_uniphy_rx_afe_2_miireg_reg_uphy_rx_afe_cap1_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_uniphy_rx_afe_2_miireg_reg_uphy_rx_rescal_code_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_uniphy_rx_afe_2_miireg_reg_uphy_rx_rescal_code_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_bandgap_ip_mbias_2_cmn_mmd1_reg_mbias_en_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_bandgap_ip_mbias_2_cmn_mmd1_reg_mbias_en_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_bandgap_ip_mbias_2_cmn_mmd1_reg_cmn_icc_rescode_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_bandgap_ip_mbias_2_cmn_mmd1_reg_cmn_icc_rescode_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_bandgap_ip_mbias_2_cmn_mmd1_reg_cmn_bg_rsv_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_bandgap_ip_mbias_2_cmn_mmd1_reg_cmn_bg_rsv_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_ldo_0p9v_related_1_cmn_mmd1_reg_cmn_ldo_ocp_en_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_ldo_0p9v_related_1_cmn_mmd1_reg_cmn_ldo_ocp_en_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_ldo_0p9v_related_1_cmn_mmd1_reg_cmn_ldo_int_load_en_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_ldo_0p9v_related_1_cmn_mmd1_reg_cmn_ldo_int_load_en_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_ldo_0p9v_related_1_cmn_mmd1_reg_cmn_ldo_int_res_ctrl_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_ldo_0p9v_related_1_cmn_mmd1_reg_cmn_ldo_int_res_ctrl_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_ldo_0p9v_related_1_cmn_mmd1_reg_cmn_ldo_vout_ctrl_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_ldo_0p9v_related_1_cmn_mmd1_reg_cmn_ldo_vout_ctrl_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_ldo_0p9v_related_1_cmn_mmd1_reg_cmn_ldo_ocp_current_sel_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_ldo_0p9v_related_1_cmn_mmd1_reg_cmn_ldo_ocp_current_sel_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_ldo_0p9v_related_1_cmn_mmd1_reg_cmn_vtt_ldo_biasgen_sel_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_ldo_0p9v_related_1_cmn_mmd1_reg_cmn_vtt_ldo_biasgen_sel_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_ldo_0p9v_related_1_cmn_mmd1_reg_cmn_ldo_en_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_ldo_0p9v_related_1_cmn_mmd1_reg_cmn_ldo_en_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_ldo_0p9v_related_1_cmn_mmd1_reg_cmn_ldo_comp_current_en_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_ldo_0p9v_related_1_cmn_mmd1_reg_cmn_ldo_comp_current_en_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_ldo_0p9v_related_1_cmn_mmd1_reg_cmn_ldo_bias_ctrl_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_ldo_0p9v_related_1_cmn_mmd1_reg_cmn_ldo_bias_ctrl_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_otp_vtt_ldo_related_cmn_mmd1_reg_cmn_ana_isolation_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_otp_vtt_ldo_related_cmn_mmd1_reg_cmn_ana_isolation_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_otp_vtt_ldo_related_cmn_mmd1_reg_cmn_vtt_ldo_ocp_en_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_otp_vtt_ldo_related_cmn_mmd1_reg_cmn_vtt_ldo_ocp_en_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_otp_vtt_ldo_related_cmn_mmd1_reg_cmn_vtt_ldo_en_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_otp_vtt_ldo_related_cmn_mmd1_reg_cmn_vtt_ldo_en_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_otp_vtt_ldo_related_cmn_mmd1_reg_cmn_vtt_ldo_bias_ctrl_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_otp_vtt_ldo_related_cmn_mmd1_reg_cmn_vtt_ldo_bias_ctrl_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_otp_vtt_ldo_related_cmn_mmd1_reg_cmn_vtt_ldo_rsv_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_otp_vtt_ldo_related_cmn_mmd1_reg_cmn_vtt_ldo_rsv_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_otp_vtt_ldo_related_cmn_mmd1_reg_cmn_vtt_ldo_ocp_current_sel_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_otp_vtt_ldo_related_cmn_mmd1_reg_cmn_vtt_ldo_ocp_current_sel_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_otp_vtt_ldo_related_cmn_mmd1_reg_cmn_vtt_ldo_int_load_ctrl_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_otp_vtt_ldo_related_cmn_mmd1_reg_cmn_vtt_ldo_int_load_ctrl_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_otp_temperature_compensate_1_cmn_mmd1_reg_uphy_ictat100u_en_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_otp_temperature_compensate_1_cmn_mmd1_reg_uphy_ictat100u_en_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_otp_temperature_compensate_1_cmn_mmd1_reg_cmn_pll_ictat100u_en_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_otp_temperature_compensate_1_cmn_mmd1_reg_cmn_pll_ictat100u_en_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_otp_temperature_compensate_1_cmn_mmd1_reg_uphy_ictat100u_ctrl1_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_otp_temperature_compensate_1_cmn_mmd1_reg_uphy_ictat100u_ctrl1_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_otp_temperature_compensate_1_cmn_mmd1_reg_uphy_ictat100u_ctrl2_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_otp_temperature_compensate_1_cmn_mmd1_reg_uphy_ictat100u_ctrl2_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_otp_temperature_compensate_1_cmn_mmd1_reg_uphy_ictat100u_ctrl0_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_otp_temperature_compensate_1_cmn_mmd1_reg_uphy_ictat100u_ctrl0_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_pll_vco_related_control_1_cmn_mii_reg_reg_cmn_pll_vco_calib_ready_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_pll_vco_related_control_1_cmn_mii_reg_reg_cmn_pll_vco_calib_ready_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_pll_vco_related_control_1_cmn_mii_reg_reg_cmn_pll_vco_temp_cmp_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_pll_vco_related_control_1_cmn_mii_reg_reg_cmn_pll_vco_temp_cmp_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_pll_vco_related_control_1_cmn_mii_reg_cmn_pll_lckdt_en_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_pll_vco_related_control_1_cmn_mii_reg_cmn_pll_lckdt_en_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_pll_vco_related_control_1_cmn_mii_reg_reg_cmn_pll_vco_amp_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_pll_vco_related_control_1_cmn_mii_reg_reg_cmn_pll_vco_amp_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_pll_vco_related_control_1_cmn_mii_reg_autoload_sel_pll_vco_calib_ready_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_pll_vco_related_control_1_cmn_mii_reg_autoload_sel_pll_vco_calib_ready_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_pll_control_vco_related_selection_2_cmn_mmd1_reg_src_cmn_pll_vco_calib_ready_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_pll_control_vco_related_selection_2_cmn_mmd1_reg_src_cmn_pll_vco_calib_ready_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_pll_control_vco_related_selection_2_cmn_mmd1_reg_src_cmn_pll_vco_temp_cmp_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_pll_control_vco_related_selection_2_cmn_mmd1_reg_src_cmn_pll_vco_temp_cmp_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_pll_control_vco_related_selection_2_cmn_mmd1_reg_src_cmn_pll_vco_amp_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_pll_control_vco_related_selection_2_cmn_mmd1_reg_src_cmn_pll_vco_amp_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_pll_control_vco_related_selection_2_cmn_mmd1_reg_src_cmn_pll_vco_calib_start_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_pll_control_vco_related_selection_2_cmn_mmd1_reg_src_cmn_pll_vco_calib_start_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_pll_control_vco_related_selection_2_cmn_mmd1_reg_src_cmn_pll_vco_calib_code_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_pll_control_vco_related_selection_2_cmn_mmd1_reg_src_cmn_pll_vco_calib_code_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_pll_control_vco_related_selection_2_cmn_mmd1_reg_src_cmn_pll_fbclk_div_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_pll_control_vco_related_selection_2_cmn_mmd1_reg_src_cmn_pll_fbclk_div_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_uniphy_phy_mode_ctrl_get( - a_uint32_t dev_id, - a_uint32_t index, - union uniphy_misc2_phy_mode_u *value); - -sw_error_t -hppe_uniphy_phy_mode_ctrl_set( - a_uint32_t dev_id, - a_uint32_t index, - union uniphy_misc2_phy_mode_u *value); - -sw_error_t -hppe_uniphy_pll_reset_ctrl_get( - a_uint32_t dev_id, - a_uint32_t index, - union pll_power_on_and_reset_u *value); - -sw_error_t -hppe_uniphy_pll_reset_ctrl_set( - a_uint32_t dev_id, - a_uint32_t index, - union pll_power_on_and_reset_u *value); - -#endif - diff --git a/feeds/ipq807x/qca-ssdk/src/include/hsl/hppe/hppe_uniphy_reg.h b/feeds/ipq807x/qca-ssdk/src/include/hsl/hppe/hppe_uniphy_reg.h deleted file mode 100755 index 773a3fe4c..000000000 --- a/feeds/ipq807x/qca-ssdk/src/include/hsl/hppe/hppe_uniphy_reg.h +++ /dev/null @@ -1,1594 +0,0 @@ -/* - * Copyright (c) 2017, 2019, The Linux Foundation. All rights reserved. - * Permission to use, copy, modify, and/or distribute this software for - * any purpose with or without fee is hereby granted, provided that the - * above copyright notice and this permission notice appear in all copies. - * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES - * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR - * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES - * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN - * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT - * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. - */ - - -/** - * @defgroup - * @{ - */ -#ifndef HPPE_UNIPHY_REG_H -#define HPPE_UNIPHY_REG_H - -/*[register] UNIPHY_OFFSET_CALIB_4*/ -#define UNIPHY_OFFSET_CALIB_4 -#define UNIPHY_OFFSET_CALIB_4_ADDRESS 0x1e0 -#define UNIPHY_OFFSET_CALIB_4_NUM 3 -#define UNIPHY_OFFSET_CALIB_4_INC 0x1 -#define UNIPHY_OFFSET_CALIB_4_TYPE REG_TYPE_RW -#define UNIPHY_OFFSET_CALIB_4_DEFAULT 0x0 - /*[field] MMD1_REG_SMPL_CAL_READY*/ - #define UNIPHY_OFFSET_CALIB_4_MMD1_REG_SMPL_CAL_READY - #define UNIPHY_OFFSET_CALIB_4_MMD1_REG_SMPL_CAL_READY_OFFSET 0 - #define UNIPHY_OFFSET_CALIB_4_MMD1_REG_SMPL_CAL_READY_LEN 1 - #define UNIPHY_OFFSET_CALIB_4_MMD1_REG_SMPL_CAL_READY_DEFAULT 0x0 - /*[field] MMD1_REG_CLR_SAMPLER_CALIB_TIMEOUT*/ - #define UNIPHY_OFFSET_CALIB_4_MMD1_REG_CLR_SAMPLER_CALIB_TIMEOUT - #define UNIPHY_OFFSET_CALIB_4_MMD1_REG_CLR_SAMPLER_CALIB_TIMEOUT_OFFSET 1 - #define UNIPHY_OFFSET_CALIB_4_MMD1_REG_CLR_SAMPLER_CALIB_TIMEOUT_LEN 1 - #define UNIPHY_OFFSET_CALIB_4_MMD1_REG_CLR_SAMPLER_CALIB_TIMEOUT_DEFAULT 0x0 - /*[field] MMD1_REG_LOCKDET_LCKDT_REG*/ - #define UNIPHY_OFFSET_CALIB_4_MMD1_REG_LOCKDET_LCKDT_REG - #define UNIPHY_OFFSET_CALIB_4_MMD1_REG_LOCKDET_LCKDT_REG_OFFSET 4 - #define UNIPHY_OFFSET_CALIB_4_MMD1_REG_LOCKDET_LCKDT_REG_LEN 1 - #define UNIPHY_OFFSET_CALIB_4_MMD1_REG_LOCKDET_LCKDT_REG_DEFAULT 0x0 - /*[field] MMD1_REG_PLL_LOCKED_REG*/ - #define UNIPHY_OFFSET_CALIB_4_MMD1_REG_PLL_LOCKED_REG - #define UNIPHY_OFFSET_CALIB_4_MMD1_REG_PLL_LOCKED_REG_OFFSET 6 - #define UNIPHY_OFFSET_CALIB_4_MMD1_REG_PLL_LOCKED_REG_LEN 1 - #define UNIPHY_OFFSET_CALIB_4_MMD1_REG_PLL_LOCKED_REG_DEFAULT 0x0 - /*[field] MMD1_REG_CALIBRATION_DONE_REG*/ - #define UNIPHY_OFFSET_CALIB_4_MMD1_REG_CALIBRATION_DONE_REG - #define UNIPHY_OFFSET_CALIB_4_MMD1_REG_CALIBRATION_DONE_REG_OFFSET 7 - #define UNIPHY_OFFSET_CALIB_4_MMD1_REG_CALIBRATION_DONE_REG_LEN 1 - #define UNIPHY_OFFSET_CALIB_4_MMD1_REG_CALIBRATION_DONE_REG_DEFAULT 0x0 - /*[field] MMD1_REG_CAL_DETECT_TIME*/ - #define UNIPHY_OFFSET_CALIB_4_MMD1_REG_CAL_DETECT_TIME - #define UNIPHY_OFFSET_CALIB_4_MMD1_REG_CAL_DETECT_TIME_OFFSET 8 - #define UNIPHY_OFFSET_CALIB_4_MMD1_REG_CAL_DETECT_TIME_LEN 5 - #define UNIPHY_OFFSET_CALIB_4_MMD1_REG_CAL_DETECT_TIME_DEFAULT 0x0 - /*[field] MMD1_REG_CAL_REP_TIME*/ - #define UNIPHY_OFFSET_CALIB_4_MMD1_REG_CAL_REP_TIME - #define UNIPHY_OFFSET_CALIB_4_MMD1_REG_CAL_REP_TIME_OFFSET 13 - #define UNIPHY_OFFSET_CALIB_4_MMD1_REG_CAL_REP_TIME_LEN 3 - #define UNIPHY_OFFSET_CALIB_4_MMD1_REG_CAL_REP_TIME_DEFAULT 0x0 - -struct uniphy_offset_calib_4 { - a_uint32_t mmd1_reg_smpl_cal_ready:1; - a_uint32_t mmd1_reg_clr_sampler_calib_timeout:1; - a_uint32_t _reserved0:2; - a_uint32_t mmd1_reg_lockdet_lckdt_reg:1; - a_uint32_t _reserved1:1; - a_uint32_t mmd1_reg_pll_locked_reg:1; - a_uint32_t mmd1_reg_calibration_done_reg:1; - a_uint32_t mmd1_reg_cal_detect_time:5; - a_uint32_t mmd1_reg_cal_rep_time:3; - a_uint32_t _reserved2:16; -}; - -union uniphy_offset_calib_4_u { - a_uint32_t val; - struct uniphy_offset_calib_4 bf; -}; - -/*[register] UNIPHY_MODE_CTRL*/ -#define UNIPHY_MODE_CTRL -#define UNIPHY_MODE_CTRL_ADDRESS 0x46c -#define UNIPHY_MODE_CTRL_NUM 3 -#define UNIPHY_MODE_CTRL_INC 0x1 -#define UNIPHY_MODE_CTRL_TYPE REG_TYPE_RW -#define UNIPHY_MODE_CTRL_DEFAULT 0x221 - /*[field] NEWADDEDFROMHERE_CH0_AUTONEG_MODE*/ - #define UNIPHY_MODE_CTRL_NEWADDEDFROMHERE_CH0_AUTONEG_MODE - #define UNIPHY_MODE_CTRL_NEWADDEDFROMHERE_CH0_AUTONEG_MODE_OFFSET 0 - #define UNIPHY_MODE_CTRL_NEWADDEDFROMHERE_CH0_AUTONEG_MODE_LEN 1 - #define UNIPHY_MODE_CTRL_NEWADDEDFROMHERE_CH0_AUTONEG_MODE_DEFAULT 0x1 - /*[field] NEWADDEDFROMHERE_CH1_CH0_SGMII*/ - #define UNIPHY_MODE_CTRL_NEWADDEDFROMHERE_CH1_CH0_SGMII - #define UNIPHY_MODE_CTRL_NEWADDEDFROMHERE_CH1_CH0_SGMII_OFFSET 1 - #define UNIPHY_MODE_CTRL_NEWADDEDFROMHERE_CH1_CH0_SGMII_LEN 1 - #define UNIPHY_MODE_CTRL_NEWADDEDFROMHERE_CH1_CH0_SGMII_DEFAULT 0x0 - /*[field] NEWADDEDFROMHERE_CH4_CH1_0_SGMII*/ - #define UNIPHY_MODE_CTRL_NEWADDEDFROMHERE_CH4_CH1_0_SGMII - #define UNIPHY_MODE_CTRL_NEWADDEDFROMHERE_CH4_CH1_0_SGMII_OFFSET 2 - #define UNIPHY_MODE_CTRL_NEWADDEDFROMHERE_CH4_CH1_0_SGMII_LEN 1 - #define UNIPHY_MODE_CTRL_NEWADDEDFROMHERE_CH4_CH1_0_SGMII_DEFAULT 0x0 - /*[field] NEWADDEDFROMHERE_SGMII_EVEN_LOW*/ - #define UNIPHY_MODE_CTRL_NEWADDEDFROMHERE_SGMII_EVEN_LOW - #define UNIPHY_MODE_CTRL_NEWADDEDFROMHERE_SGMII_EVEN_LOW_OFFSET 3 - #define UNIPHY_MODE_CTRL_NEWADDEDFROMHERE_SGMII_EVEN_LOW_LEN 1 - #define UNIPHY_MODE_CTRL_NEWADDEDFROMHERE_SGMII_EVEN_LOW_DEFAULT 0x0 - /*[field] NEWADDEDFROMHERE_CH0_MODE_CTRL_25M*/ - #define UNIPHY_MODE_CTRL_NEWADDEDFROMHERE_CH0_MODE_CTRL_25M - #define UNIPHY_MODE_CTRL_NEWADDEDFROMHERE_CH0_MODE_CTRL_25M_OFFSET 4 - #define UNIPHY_MODE_CTRL_NEWADDEDFROMHERE_CH0_MODE_CTRL_25M_LEN 3 - #define UNIPHY_MODE_CTRL_NEWADDEDFROMHERE_CH0_MODE_CTRL_25M_DEFAULT 0x2 - /*[field] NEWADDEDFROMHERE_CH0_QSGMII_SGMII*/ - #define UNIPHY_MODE_CTRL_NEWADDEDFROMHERE_CH0_QSGMII_SGMII - #define UNIPHY_MODE_CTRL_NEWADDEDFROMHERE_CH0_QSGMII_SGMII_OFFSET 8 - #define UNIPHY_MODE_CTRL_NEWADDEDFROMHERE_CH0_QSGMII_SGMII_LEN 1 - #define UNIPHY_MODE_CTRL_NEWADDEDFROMHERE_CH0_QSGMII_SGMII_DEFAULT 0x0 - /*[field] NEWADDEDFROMHERE_CH0_PSGMII_QSGMII*/ - #define UNIPHY_MODE_CTRL_NEWADDEDFROMHERE_CH0_PSGMII_QSGMII - #define UNIPHY_MODE_CTRL_NEWADDEDFROMHERE_CH0_PSGMII_QSGMII_OFFSET 9 - #define UNIPHY_MODE_CTRL_NEWADDEDFROMHERE_CH0_PSGMII_QSGMII_LEN 1 - #define UNIPHY_MODE_CTRL_NEWADDEDFROMHERE_CH0_PSGMII_QSGMII_DEFAULT 0x1 - /*[field] NEWADDEDFROMHERE_SG_MODE*/ - #define UNIPHY_MODE_CTRL_NEWADDEDFROMHERE_SG_MODE - #define UNIPHY_MODE_CTRL_NEWADDEDFROMHERE_SG_MODE_OFFSET 10 - #define UNIPHY_MODE_CTRL_NEWADDEDFROMHERE_SG_MODE_LEN 1 - #define UNIPHY_MODE_CTRL_NEWADDEDFROMHERE_SG_MODE_DEFAULT 0x0 - /*[field] NEWADDEDFROMHERE_SGPLUS_MODE*/ - #define UNIPHY_MODE_CTRL_NEWADDEDFROMHERE_SGPLUS_MODE - #define UNIPHY_MODE_CTRL_NEWADDEDFROMHERE_SGPLUS_MODE_OFFSET 11 - #define UNIPHY_MODE_CTRL_NEWADDEDFROMHERE_SGPLUS_MODE_LEN 1 - #define UNIPHY_MODE_CTRL_NEWADDEDFROMHERE_SGPLUS_MODE_DEFAULT 0x0 - /*[field] NEWADDEDFROMHERE_XPCS_MODE*/ - #define UNIPHY_MODE_CTRL_NEWADDEDFROMHERE_XPCS_MODE - #define UNIPHY_MODE_CTRL_NEWADDEDFROMHERE_XPCS_MODE_OFFSET 12 - #define UNIPHY_MODE_CTRL_NEWADDEDFROMHERE_XPCS_MODE_LEN 1 - #define UNIPHY_MODE_CTRL_NEWADDEDFROMHERE_XPCS_MODE_DEFAULT 0x0 - /*[field] NEWADDEDFROMHERE_USXG_EN*/ - #define UNIPHY_MODE_CTRL_NEWADDEDFROMHERE_USXG_EN - #define UNIPHY_MODE_CTRL_NEWADDEDFROMHERE_USXG_EN_OFFSET 13 - #define UNIPHY_MODE_CTRL_NEWADDEDFROMHERE_USXG_EN_LEN 1 - #define UNIPHY_MODE_CTRL_NEWADDEDFROMHERE_USXG_EN_DEFAULT 0x0 - /*[field] NEWADDEDFROMHERE_SW_V17_V18*/ - #define UNIPHY_MODE_CTRL_NEWADDEDFROMHERE_SW_V17_V18 - #define UNIPHY_MODE_CTRL_NEWADDEDFROMHERE_SW_V17_V18_OFFSET 15 - #define UNIPHY_MODE_CTRL_NEWADDEDFROMHERE_SW_V17_V18_LEN 1 - #define UNIPHY_MODE_CTRL_NEWADDEDFROMHERE_SW_V17_V18_DEFAULT 0x0 - -struct uniphy_mode_ctrl { - a_uint32_t newaddedfromhere_ch0_autoneg_mode:1; - a_uint32_t newaddedfromhere_ch1_ch0_sgmii:1; - a_uint32_t newaddedfromhere_ch4_ch1_0_sgmii:1; - a_uint32_t newaddedfromhere_sgmii_even_low:1; - a_uint32_t newaddedfromhere_ch0_mode_ctrl_25m:3; - a_uint32_t _reserved0:1; - a_uint32_t newaddedfromhere_ch0_qsgmii_sgmii:1; - a_uint32_t newaddedfromhere_ch0_psgmii_qsgmii:1; - a_uint32_t newaddedfromhere_sg_mode:1; - a_uint32_t newaddedfromhere_sgplus_mode:1; - a_uint32_t newaddedfromhere_xpcs_mode:1; - a_uint32_t newaddedfromhere_usxg_en:1; - a_uint32_t _reserved1:1; - a_uint32_t newaddedfromhere_sw_v17_v18:1; - a_uint32_t _reserved2:16; -}; - -union uniphy_mode_ctrl_u { - a_uint32_t val; - struct uniphy_mode_ctrl bf; -}; - -/*[register] UNIPHY_CHANNEL0_INPUT_OUTPUT_4*/ -#define UNIPHY_CHANNEL0_INPUT_OUTPUT_4 -#define UNIPHY_CHANNEL0_INPUT_OUTPUT_4_ADDRESS 0x480 -#define UNIPHY_CHANNEL0_INPUT_OUTPUT_4_NUM 3 -#define UNIPHY_CHANNEL0_INPUT_OUTPUT_4_INC 0x1 -#define UNIPHY_CHANNEL0_INPUT_OUTPUT_4_TYPE REG_TYPE_RW -#define UNIPHY_CHANNEL0_INPUT_OUTPUT_4_DEFAULT 0x844 - /*[field] NEWADDEDFROMHERE_CH0_REM_PHY_LPBK*/ - #define UNIPHY_CHANNEL0_INPUT_OUTPUT_4_NEWADDEDFROMHERE_CH0_REM_PHY_LPBK - #define UNIPHY_CHANNEL0_INPUT_OUTPUT_4_NEWADDEDFROMHERE_CH0_REM_PHY_LPBK_OFFSET 0 - #define UNIPHY_CHANNEL0_INPUT_OUTPUT_4_NEWADDEDFROMHERE_CH0_REM_PHY_LPBK_LEN 1 - #define UNIPHY_CHANNEL0_INPUT_OUTPUT_4_NEWADDEDFROMHERE_CH0_REM_PHY_LPBK_DEFAULT 0x0 - /*[field] NEWADDEDFROMHERE_CH0_SPEED_25M*/ - #define UNIPHY_CHANNEL0_INPUT_OUTPUT_4_NEWADDEDFROMHERE_CH0_SPEED_25M - #define UNIPHY_CHANNEL0_INPUT_OUTPUT_4_NEWADDEDFROMHERE_CH0_SPEED_25M_OFFSET 1 - #define UNIPHY_CHANNEL0_INPUT_OUTPUT_4_NEWADDEDFROMHERE_CH0_SPEED_25M_LEN 2 - #define UNIPHY_CHANNEL0_INPUT_OUTPUT_4_NEWADDEDFROMHERE_CH0_SPEED_25M_DEFAULT 0x2 - /*[field] NEWADDEDFROMHERE_CH0_FORCE_SPEED_25M*/ - #define UNIPHY_CHANNEL0_INPUT_OUTPUT_4_NEWADDEDFROMHERE_CH0_FORCE_SPEED_25M - #define UNIPHY_CHANNEL0_INPUT_OUTPUT_4_NEWADDEDFROMHERE_CH0_FORCE_SPEED_25M_OFFSET 3 - #define UNIPHY_CHANNEL0_INPUT_OUTPUT_4_NEWADDEDFROMHERE_CH0_FORCE_SPEED_25M_LEN 1 - #define UNIPHY_CHANNEL0_INPUT_OUTPUT_4_NEWADDEDFROMHERE_CH0_FORCE_SPEED_25M_DEFAULT 0x0 - /*[field] NEWADDEDFROMHERE_CH0_MR_NP_LOADED_25M*/ - #define UNIPHY_CHANNEL0_INPUT_OUTPUT_4_NEWADDEDFROMHERE_CH0_MR_NP_LOADED_25M - #define UNIPHY_CHANNEL0_INPUT_OUTPUT_4_NEWADDEDFROMHERE_CH0_MR_NP_LOADED_25M_OFFSET 4 - #define UNIPHY_CHANNEL0_INPUT_OUTPUT_4_NEWADDEDFROMHERE_CH0_MR_NP_LOADED_25M_LEN 1 - #define UNIPHY_CHANNEL0_INPUT_OUTPUT_4_NEWADDEDFROMHERE_CH0_MR_NP_LOADED_25M_DEFAULT 0x0 - /*[field] NEWADDEDFROMHERE_CH0_MR_REG4_CH_25M*/ - #define UNIPHY_CHANNEL0_INPUT_OUTPUT_4_NEWADDEDFROMHERE_CH0_MR_REG4_CH_25M - #define UNIPHY_CHANNEL0_INPUT_OUTPUT_4_NEWADDEDFROMHERE_CH0_MR_REG4_CH_25M_OFFSET 5 - #define UNIPHY_CHANNEL0_INPUT_OUTPUT_4_NEWADDEDFROMHERE_CH0_MR_REG4_CH_25M_LEN 1 - #define UNIPHY_CHANNEL0_INPUT_OUTPUT_4_NEWADDEDFROMHERE_CH0_MR_REG4_CH_25M_DEFAULT 0x0 - /*[field] NEWADDEDFROMHERE_CH0_MR_AN_ENABLE_25M*/ - #define UNIPHY_CHANNEL0_INPUT_OUTPUT_4_NEWADDEDFROMHERE_CH0_MR_AN_ENABLE_25M - #define UNIPHY_CHANNEL0_INPUT_OUTPUT_4_NEWADDEDFROMHERE_CH0_MR_AN_ENABLE_25M_OFFSET 6 - #define UNIPHY_CHANNEL0_INPUT_OUTPUT_4_NEWADDEDFROMHERE_CH0_MR_AN_ENABLE_25M_LEN 1 - #define UNIPHY_CHANNEL0_INPUT_OUTPUT_4_NEWADDEDFROMHERE_CH0_MR_AN_ENABLE_25M_DEFAULT 0x1 - /*[field] NEWADDEDFROMHERE_CH0_MR_RESTART_AN_25M*/ - #define UNIPHY_CHANNEL0_INPUT_OUTPUT_4_NEWADDEDFROMHERE_CH0_MR_RESTART_AN_25M - #define UNIPHY_CHANNEL0_INPUT_OUTPUT_4_NEWADDEDFROMHERE_CH0_MR_RESTART_AN_25M_OFFSET 7 - #define UNIPHY_CHANNEL0_INPUT_OUTPUT_4_NEWADDEDFROMHERE_CH0_MR_RESTART_AN_25M_LEN 1 - #define UNIPHY_CHANNEL0_INPUT_OUTPUT_4_NEWADDEDFROMHERE_CH0_MR_RESTART_AN_25M_DEFAULT 0x0 - /*[field] NEWADDEDFROMHERE_CH0_MR_LOOPBACK_25M*/ - #define UNIPHY_CHANNEL0_INPUT_OUTPUT_4_NEWADDEDFROMHERE_CH0_MR_LOOPBACK_25M - #define UNIPHY_CHANNEL0_INPUT_OUTPUT_4_NEWADDEDFROMHERE_CH0_MR_LOOPBACK_25M_OFFSET 8 - #define UNIPHY_CHANNEL0_INPUT_OUTPUT_4_NEWADDEDFROMHERE_CH0_MR_LOOPBACK_25M_LEN 1 - #define UNIPHY_CHANNEL0_INPUT_OUTPUT_4_NEWADDEDFROMHERE_CH0_MR_LOOPBACK_25M_DEFAULT 0x0 - /*[field] NEWADDEDFROMHERE_CH0_MR_MAIN_RESET_25M*/ - #define UNIPHY_CHANNEL0_INPUT_OUTPUT_4_NEWADDEDFROMHERE_CH0_MR_MAIN_RESET_25M - #define UNIPHY_CHANNEL0_INPUT_OUTPUT_4_NEWADDEDFROMHERE_CH0_MR_MAIN_RESET_25M_OFFSET 9 - #define UNIPHY_CHANNEL0_INPUT_OUTPUT_4_NEWADDEDFROMHERE_CH0_MR_MAIN_RESET_25M_LEN 1 - #define UNIPHY_CHANNEL0_INPUT_OUTPUT_4_NEWADDEDFROMHERE_CH0_MR_MAIN_RESET_25M_DEFAULT 0x0 - /*[field] NEWADDEDFROMHERE_CH0_POWER_ON_25M*/ - #define UNIPHY_CHANNEL0_INPUT_OUTPUT_4_NEWADDEDFROMHERE_CH0_POWER_ON_25M - #define UNIPHY_CHANNEL0_INPUT_OUTPUT_4_NEWADDEDFROMHERE_CH0_POWER_ON_25M_OFFSET 10 - #define UNIPHY_CHANNEL0_INPUT_OUTPUT_4_NEWADDEDFROMHERE_CH0_POWER_ON_25M_LEN 1 - #define UNIPHY_CHANNEL0_INPUT_OUTPUT_4_NEWADDEDFROMHERE_CH0_POWER_ON_25M_DEFAULT 0x0 - /*[field] NEWADDEDFROMHERE_CH0_ADP_SW_RSTN*/ - #define UNIPHY_CHANNEL0_INPUT_OUTPUT_4_NEWADDEDFROMHERE_CH0_ADP_SW_RSTN - #define UNIPHY_CHANNEL0_INPUT_OUTPUT_4_NEWADDEDFROMHERE_CH0_ADP_SW_RSTN_OFFSET 11 - #define UNIPHY_CHANNEL0_INPUT_OUTPUT_4_NEWADDEDFROMHERE_CH0_ADP_SW_RSTN_LEN 1 - #define UNIPHY_CHANNEL0_INPUT_OUTPUT_4_NEWADDEDFROMHERE_CH0_ADP_SW_RSTN_DEFAULT 0x1 - -struct uniphy_channel0_input_output_4 { - a_uint32_t newaddedfromhere_ch0_rem_phy_lpbk:1; - a_uint32_t newaddedfromhere_ch0_speed_25m:2; - a_uint32_t newaddedfromhere_ch0_force_speed_25m:1; - a_uint32_t newaddedfromhere_ch0_mr_np_loaded_25m:1; - a_uint32_t newaddedfromhere_ch0_mr_reg4_ch_25m:1; - a_uint32_t newaddedfromhere_ch0_mr_an_enable_25m:1; - a_uint32_t newaddedfromhere_ch0_mr_restart_an_25m:1; - a_uint32_t newaddedfromhere_ch0_mr_loopback_25m:1; - a_uint32_t newaddedfromhere_ch0_mr_main_reset_25m:1; - a_uint32_t newaddedfromhere_ch0_power_on_25m:1; - a_uint32_t newaddedfromhere_ch0_adp_sw_rstn:1; - a_uint32_t _reserved0:20; -}; - -union uniphy_channel0_input_output_4_u { - a_uint32_t val; - struct uniphy_channel0_input_output_4 bf; -}; - -/*[register] UNIPHY_CHANNEL1_INPUT_OUTPUT_4*/ -#define UNIPHY_CHANNEL1_INPUT_OUTPUT_4 -#define UNIPHY_CHANNEL1_INPUT_OUTPUT_4_ADDRESS 0x498 -#define UNIPHY_CHANNEL1_INPUT_OUTPUT_4_NUM 3 -#define UNIPHY_CHANNEL1_INPUT_OUTPUT_4_INC 0x1 -#define UNIPHY_CHANNEL1_INPUT_OUTPUT_4_TYPE REG_TYPE_RW -#define UNIPHY_CHANNEL1_INPUT_OUTPUT_4_DEFAULT 0x844 - /*[field] NEWADDEDFROMHERE_CH1_REM_PHY_LPBK*/ - #define UNIPHY_CHANNEL1_INPUT_OUTPUT_4_NEWADDEDFROMHERE_CH1_REM_PHY_LPBK - #define UNIPHY_CHANNEL1_INPUT_OUTPUT_4_NEWADDEDFROMHERE_CH1_REM_PHY_LPBK_OFFSET 0 - #define UNIPHY_CHANNEL1_INPUT_OUTPUT_4_NEWADDEDFROMHERE_CH1_REM_PHY_LPBK_LEN 1 - #define UNIPHY_CHANNEL1_INPUT_OUTPUT_4_NEWADDEDFROMHERE_CH1_REM_PHY_LPBK_DEFAULT 0x0 - /*[field] NEWADDEDFROMHERE_CH1_SPEED_25M*/ - #define UNIPHY_CHANNEL1_INPUT_OUTPUT_4_NEWADDEDFROMHERE_CH1_SPEED_25M - #define UNIPHY_CHANNEL1_INPUT_OUTPUT_4_NEWADDEDFROMHERE_CH1_SPEED_25M_OFFSET 1 - #define UNIPHY_CHANNEL1_INPUT_OUTPUT_4_NEWADDEDFROMHERE_CH1_SPEED_25M_LEN 2 - #define UNIPHY_CHANNEL1_INPUT_OUTPUT_4_NEWADDEDFROMHERE_CH1_SPEED_25M_DEFAULT 0x2 - /*[field] NEWADDEDFROMHERE_CH1_FORCE_SPEED_25M*/ - #define UNIPHY_CHANNEL1_INPUT_OUTPUT_4_NEWADDEDFROMHERE_CH1_FORCE_SPEED_25M - #define UNIPHY_CHANNEL1_INPUT_OUTPUT_4_NEWADDEDFROMHERE_CH1_FORCE_SPEED_25M_OFFSET 3 - #define UNIPHY_CHANNEL1_INPUT_OUTPUT_4_NEWADDEDFROMHERE_CH1_FORCE_SPEED_25M_LEN 1 - #define UNIPHY_CHANNEL1_INPUT_OUTPUT_4_NEWADDEDFROMHERE_CH1_FORCE_SPEED_25M_DEFAULT 0x0 - /*[field] NEWADDEDFROMHERE_CH1_MR_NP_LOADED_25M*/ - #define UNIPHY_CHANNEL1_INPUT_OUTPUT_4_NEWADDEDFROMHERE_CH1_MR_NP_LOADED_25M - #define UNIPHY_CHANNEL1_INPUT_OUTPUT_4_NEWADDEDFROMHERE_CH1_MR_NP_LOADED_25M_OFFSET 4 - #define UNIPHY_CHANNEL1_INPUT_OUTPUT_4_NEWADDEDFROMHERE_CH1_MR_NP_LOADED_25M_LEN 1 - #define UNIPHY_CHANNEL1_INPUT_OUTPUT_4_NEWADDEDFROMHERE_CH1_MR_NP_LOADED_25M_DEFAULT 0x0 - /*[field] NEWADDEDFROMHERE_CH1_MR_REG4_CH_25M*/ - #define UNIPHY_CHANNEL1_INPUT_OUTPUT_4_NEWADDEDFROMHERE_CH1_MR_REG4_CH_25M - #define UNIPHY_CHANNEL1_INPUT_OUTPUT_4_NEWADDEDFROMHERE_CH1_MR_REG4_CH_25M_OFFSET 5 - #define UNIPHY_CHANNEL1_INPUT_OUTPUT_4_NEWADDEDFROMHERE_CH1_MR_REG4_CH_25M_LEN 1 - #define UNIPHY_CHANNEL1_INPUT_OUTPUT_4_NEWADDEDFROMHERE_CH1_MR_REG4_CH_25M_DEFAULT 0x0 - /*[field] NEWADDEDFROMHERE_CH1_MR_AN_ENABLE_25M*/ - #define UNIPHY_CHANNEL1_INPUT_OUTPUT_4_NEWADDEDFROMHERE_CH1_MR_AN_ENABLE_25M - #define UNIPHY_CHANNEL1_INPUT_OUTPUT_4_NEWADDEDFROMHERE_CH1_MR_AN_ENABLE_25M_OFFSET 6 - #define UNIPHY_CHANNEL1_INPUT_OUTPUT_4_NEWADDEDFROMHERE_CH1_MR_AN_ENABLE_25M_LEN 1 - #define UNIPHY_CHANNEL1_INPUT_OUTPUT_4_NEWADDEDFROMHERE_CH1_MR_AN_ENABLE_25M_DEFAULT 0x1 - /*[field] NEWADDEDFROMHERE_CH1_MR_RESTART_AN_25M*/ - #define UNIPHY_CHANNEL1_INPUT_OUTPUT_4_NEWADDEDFROMHERE_CH1_MR_RESTART_AN_25M - #define UNIPHY_CHANNEL1_INPUT_OUTPUT_4_NEWADDEDFROMHERE_CH1_MR_RESTART_AN_25M_OFFSET 7 - #define UNIPHY_CHANNEL1_INPUT_OUTPUT_4_NEWADDEDFROMHERE_CH1_MR_RESTART_AN_25M_LEN 1 - #define UNIPHY_CHANNEL1_INPUT_OUTPUT_4_NEWADDEDFROMHERE_CH1_MR_RESTART_AN_25M_DEFAULT 0x0 - /*[field] NEWADDEDFROMHERE_CH1_MR_LOOPBACK_25M*/ - #define UNIPHY_CHANNEL1_INPUT_OUTPUT_4_NEWADDEDFROMHERE_CH1_MR_LOOPBACK_25M - #define UNIPHY_CHANNEL1_INPUT_OUTPUT_4_NEWADDEDFROMHERE_CH1_MR_LOOPBACK_25M_OFFSET 8 - #define UNIPHY_CHANNEL1_INPUT_OUTPUT_4_NEWADDEDFROMHERE_CH1_MR_LOOPBACK_25M_LEN 1 - #define UNIPHY_CHANNEL1_INPUT_OUTPUT_4_NEWADDEDFROMHERE_CH1_MR_LOOPBACK_25M_DEFAULT 0x0 - /*[field] NEWADDEDFROMHERE_CH1_MR_MAIN_RESET_25M*/ - #define UNIPHY_CHANNEL1_INPUT_OUTPUT_4_NEWADDEDFROMHERE_CH1_MR_MAIN_RESET_25M - #define UNIPHY_CHANNEL1_INPUT_OUTPUT_4_NEWADDEDFROMHERE_CH1_MR_MAIN_RESET_25M_OFFSET 9 - #define UNIPHY_CHANNEL1_INPUT_OUTPUT_4_NEWADDEDFROMHERE_CH1_MR_MAIN_RESET_25M_LEN 1 - #define UNIPHY_CHANNEL1_INPUT_OUTPUT_4_NEWADDEDFROMHERE_CH1_MR_MAIN_RESET_25M_DEFAULT 0x0 - /*[field] NEWADDEDFROMHERE_CH1_POWER_ON_25M*/ - #define UNIPHY_CHANNEL1_INPUT_OUTPUT_4_NEWADDEDFROMHERE_CH1_POWER_ON_25M - #define UNIPHY_CHANNEL1_INPUT_OUTPUT_4_NEWADDEDFROMHERE_CH1_POWER_ON_25M_OFFSET 10 - #define UNIPHY_CHANNEL1_INPUT_OUTPUT_4_NEWADDEDFROMHERE_CH1_POWER_ON_25M_LEN 1 - #define UNIPHY_CHANNEL1_INPUT_OUTPUT_4_NEWADDEDFROMHERE_CH1_POWER_ON_25M_DEFAULT 0x0 - /*[field] NEWADDEDFROMHERE_CH1_ADP_SW_RSTN*/ - #define UNIPHY_CHANNEL1_INPUT_OUTPUT_4_NEWADDEDFROMHERE_CH1_ADP_SW_RSTN - #define UNIPHY_CHANNEL1_INPUT_OUTPUT_4_NEWADDEDFROMHERE_CH1_ADP_SW_RSTN_OFFSET 11 - #define UNIPHY_CHANNEL1_INPUT_OUTPUT_4_NEWADDEDFROMHERE_CH1_ADP_SW_RSTN_LEN 1 - #define UNIPHY_CHANNEL1_INPUT_OUTPUT_4_NEWADDEDFROMHERE_CH1_ADP_SW_RSTN_DEFAULT 0x1 - -struct uniphy_channel1_input_output_4 { - a_uint32_t newaddedfromhere_ch1_rem_phy_lpbk:1; - a_uint32_t newaddedfromhere_ch1_speed_25m:2; - a_uint32_t newaddedfromhere_ch1_force_speed_25m:1; - a_uint32_t newaddedfromhere_ch1_mr_np_loaded_25m:1; - a_uint32_t newaddedfromhere_ch1_mr_reg4_ch_25m:1; - a_uint32_t newaddedfromhere_ch1_mr_an_enable_25m:1; - a_uint32_t newaddedfromhere_ch1_mr_restart_an_25m:1; - a_uint32_t newaddedfromhere_ch1_mr_loopback_25m:1; - a_uint32_t newaddedfromhere_ch1_mr_main_reset_25m:1; - a_uint32_t newaddedfromhere_ch1_power_on_25m:1; - a_uint32_t newaddedfromhere_ch1_adp_sw_rstn:1; - a_uint32_t _reserved0:20; -}; - -union uniphy_channel1_input_output_4_u { - a_uint32_t val; - struct uniphy_channel1_input_output_4 bf; -}; - -/*[register] UNIPHY_CHANNEL2_INPUT_OUTPUT_4*/ -#define UNIPHY_CHANNEL2_INPUT_OUTPUT_4 -#define UNIPHY_CHANNEL2_INPUT_OUTPUT_4_ADDRESS 0x4b0 -#define UNIPHY_CHANNEL2_INPUT_OUTPUT_4_NUM 3 -#define UNIPHY_CHANNEL2_INPUT_OUTPUT_4_INC 0x1 -#define UNIPHY_CHANNEL2_INPUT_OUTPUT_4_TYPE REG_TYPE_RW -#define UNIPHY_CHANNEL2_INPUT_OUTPUT_4_DEFAULT 0x844 - /*[field] NEWADDEDFROMHERE_CH2_REM_PHY_LPBK*/ - #define UNIPHY_CHANNEL2_INPUT_OUTPUT_4_NEWADDEDFROMHERE_CH2_REM_PHY_LPBK - #define UNIPHY_CHANNEL2_INPUT_OUTPUT_4_NEWADDEDFROMHERE_CH2_REM_PHY_LPBK_OFFSET 0 - #define UNIPHY_CHANNEL2_INPUT_OUTPUT_4_NEWADDEDFROMHERE_CH2_REM_PHY_LPBK_LEN 1 - #define UNIPHY_CHANNEL2_INPUT_OUTPUT_4_NEWADDEDFROMHERE_CH2_REM_PHY_LPBK_DEFAULT 0x0 - /*[field] NEWADDEDFROMHERE_CH2_SPEED_25M*/ - #define UNIPHY_CHANNEL2_INPUT_OUTPUT_4_NEWADDEDFROMHERE_CH2_SPEED_25M - #define UNIPHY_CHANNEL2_INPUT_OUTPUT_4_NEWADDEDFROMHERE_CH2_SPEED_25M_OFFSET 1 - #define UNIPHY_CHANNEL2_INPUT_OUTPUT_4_NEWADDEDFROMHERE_CH2_SPEED_25M_LEN 2 - #define UNIPHY_CHANNEL2_INPUT_OUTPUT_4_NEWADDEDFROMHERE_CH2_SPEED_25M_DEFAULT 0x2 - /*[field] NEWADDEDFROMHERE_CH2_FORCE_SPEED_25M*/ - #define UNIPHY_CHANNEL2_INPUT_OUTPUT_4_NEWADDEDFROMHERE_CH2_FORCE_SPEED_25M - #define UNIPHY_CHANNEL2_INPUT_OUTPUT_4_NEWADDEDFROMHERE_CH2_FORCE_SPEED_25M_OFFSET 3 - #define UNIPHY_CHANNEL2_INPUT_OUTPUT_4_NEWADDEDFROMHERE_CH2_FORCE_SPEED_25M_LEN 1 - #define UNIPHY_CHANNEL2_INPUT_OUTPUT_4_NEWADDEDFROMHERE_CH2_FORCE_SPEED_25M_DEFAULT 0x0 - /*[field] NEWADDEDFROMHERE_CH2_MR_NP_LOADED_25M*/ - #define UNIPHY_CHANNEL2_INPUT_OUTPUT_4_NEWADDEDFROMHERE_CH2_MR_NP_LOADED_25M - #define UNIPHY_CHANNEL2_INPUT_OUTPUT_4_NEWADDEDFROMHERE_CH2_MR_NP_LOADED_25M_OFFSET 4 - #define UNIPHY_CHANNEL2_INPUT_OUTPUT_4_NEWADDEDFROMHERE_CH2_MR_NP_LOADED_25M_LEN 1 - #define UNIPHY_CHANNEL2_INPUT_OUTPUT_4_NEWADDEDFROMHERE_CH2_MR_NP_LOADED_25M_DEFAULT 0x0 - /*[field] NEWADDEDFROMHERE_CH2_MR_REG4_CH_25M*/ - #define UNIPHY_CHANNEL2_INPUT_OUTPUT_4_NEWADDEDFROMHERE_CH2_MR_REG4_CH_25M - #define UNIPHY_CHANNEL2_INPUT_OUTPUT_4_NEWADDEDFROMHERE_CH2_MR_REG4_CH_25M_OFFSET 5 - #define UNIPHY_CHANNEL2_INPUT_OUTPUT_4_NEWADDEDFROMHERE_CH2_MR_REG4_CH_25M_LEN 1 - #define UNIPHY_CHANNEL2_INPUT_OUTPUT_4_NEWADDEDFROMHERE_CH2_MR_REG4_CH_25M_DEFAULT 0x0 - /*[field] NEWADDEDFROMHERE_CH2_MR_AN_ENABLE_25M*/ - #define UNIPHY_CHANNEL2_INPUT_OUTPUT_4_NEWADDEDFROMHERE_CH2_MR_AN_ENABLE_25M - #define UNIPHY_CHANNEL2_INPUT_OUTPUT_4_NEWADDEDFROMHERE_CH2_MR_AN_ENABLE_25M_OFFSET 6 - #define UNIPHY_CHANNEL2_INPUT_OUTPUT_4_NEWADDEDFROMHERE_CH2_MR_AN_ENABLE_25M_LEN 1 - #define UNIPHY_CHANNEL2_INPUT_OUTPUT_4_NEWADDEDFROMHERE_CH2_MR_AN_ENABLE_25M_DEFAULT 0x1 - /*[field] NEWADDEDFROMHERE_CH2_MR_RESTART_AN_25M*/ - #define UNIPHY_CHANNEL2_INPUT_OUTPUT_4_NEWADDEDFROMHERE_CH2_MR_RESTART_AN_25M - #define UNIPHY_CHANNEL2_INPUT_OUTPUT_4_NEWADDEDFROMHERE_CH2_MR_RESTART_AN_25M_OFFSET 7 - #define UNIPHY_CHANNEL2_INPUT_OUTPUT_4_NEWADDEDFROMHERE_CH2_MR_RESTART_AN_25M_LEN 1 - #define UNIPHY_CHANNEL2_INPUT_OUTPUT_4_NEWADDEDFROMHERE_CH2_MR_RESTART_AN_25M_DEFAULT 0x0 - /*[field] NEWADDEDFROMHERE_CH2_MR_LOOPBACK_25M*/ - #define UNIPHY_CHANNEL2_INPUT_OUTPUT_4_NEWADDEDFROMHERE_CH2_MR_LOOPBACK_25M - #define UNIPHY_CHANNEL2_INPUT_OUTPUT_4_NEWADDEDFROMHERE_CH2_MR_LOOPBACK_25M_OFFSET 8 - #define UNIPHY_CHANNEL2_INPUT_OUTPUT_4_NEWADDEDFROMHERE_CH2_MR_LOOPBACK_25M_LEN 1 - #define UNIPHY_CHANNEL2_INPUT_OUTPUT_4_NEWADDEDFROMHERE_CH2_MR_LOOPBACK_25M_DEFAULT 0x0 - /*[field] NEWADDEDFROMHERE_CH2_MR_MAIN_RESET_25M*/ - #define UNIPHY_CHANNEL2_INPUT_OUTPUT_4_NEWADDEDFROMHERE_CH2_MR_MAIN_RESET_25M - #define UNIPHY_CHANNEL2_INPUT_OUTPUT_4_NEWADDEDFROMHERE_CH2_MR_MAIN_RESET_25M_OFFSET 9 - #define UNIPHY_CHANNEL2_INPUT_OUTPUT_4_NEWADDEDFROMHERE_CH2_MR_MAIN_RESET_25M_LEN 1 - #define UNIPHY_CHANNEL2_INPUT_OUTPUT_4_NEWADDEDFROMHERE_CH2_MR_MAIN_RESET_25M_DEFAULT 0x0 - /*[field] NEWADDEDFROMHERE_CH2_POWER_ON_25M*/ - #define UNIPHY_CHANNEL2_INPUT_OUTPUT_4_NEWADDEDFROMHERE_CH2_POWER_ON_25M - #define UNIPHY_CHANNEL2_INPUT_OUTPUT_4_NEWADDEDFROMHERE_CH2_POWER_ON_25M_OFFSET 10 - #define UNIPHY_CHANNEL2_INPUT_OUTPUT_4_NEWADDEDFROMHERE_CH2_POWER_ON_25M_LEN 1 - #define UNIPHY_CHANNEL2_INPUT_OUTPUT_4_NEWADDEDFROMHERE_CH2_POWER_ON_25M_DEFAULT 0x0 - /*[field] NEWADDEDFROMHERE_CH2_ADP_SW_RSTN*/ - #define UNIPHY_CHANNEL2_INPUT_OUTPUT_4_NEWADDEDFROMHERE_CH2_ADP_SW_RSTN - #define UNIPHY_CHANNEL2_INPUT_OUTPUT_4_NEWADDEDFROMHERE_CH2_ADP_SW_RSTN_OFFSET 11 - #define UNIPHY_CHANNEL2_INPUT_OUTPUT_4_NEWADDEDFROMHERE_CH2_ADP_SW_RSTN_LEN 1 - #define UNIPHY_CHANNEL2_INPUT_OUTPUT_4_NEWADDEDFROMHERE_CH2_ADP_SW_RSTN_DEFAULT 0x1 - -struct uniphy_channel2_input_output_4 { - a_uint32_t newaddedfromhere_ch2_rem_phy_lpbk:1; - a_uint32_t newaddedfromhere_ch2_speed_25m:2; - a_uint32_t newaddedfromhere_ch2_force_speed_25m:1; - a_uint32_t newaddedfromhere_ch2_mr_np_loaded_25m:1; - a_uint32_t newaddedfromhere_ch2_mr_reg4_ch_25m:1; - a_uint32_t newaddedfromhere_ch2_mr_an_enable_25m:1; - a_uint32_t newaddedfromhere_ch2_mr_restart_an_25m:1; - a_uint32_t newaddedfromhere_ch2_mr_loopback_25m:1; - a_uint32_t newaddedfromhere_ch2_mr_main_reset_25m:1; - a_uint32_t newaddedfromhere_ch2_power_on_25m:1; - a_uint32_t newaddedfromhere_ch2_adp_sw_rstn:1; - a_uint32_t _reserved0:20; -}; - -union uniphy_channel2_input_output_4_u { - a_uint32_t val; - struct uniphy_channel2_input_output_4 bf; -}; - -/*[register] UNIPHY_CHANNEL3_INPUT_OUTPUT_4*/ -#define UNIPHY_CHANNEL3_INPUT_OUTPUT_4 -#define UNIPHY_CHANNEL3_INPUT_OUTPUT_4_ADDRESS 0x4c8 -#define UNIPHY_CHANNEL3_INPUT_OUTPUT_4_NUM 3 -#define UNIPHY_CHANNEL3_INPUT_OUTPUT_4_INC 0x1 -#define UNIPHY_CHANNEL3_INPUT_OUTPUT_4_TYPE REG_TYPE_RW -#define UNIPHY_CHANNEL3_INPUT_OUTPUT_4_DEFAULT 0x844 - /*[field] NEWADDEDFROMHERE_CH3_REM_PHY_LPBK*/ - #define UNIPHY_CHANNEL3_INPUT_OUTPUT_4_NEWADDEDFROMHERE_CH3_REM_PHY_LPBK - #define UNIPHY_CHANNEL3_INPUT_OUTPUT_4_NEWADDEDFROMHERE_CH3_REM_PHY_LPBK_OFFSET 0 - #define UNIPHY_CHANNEL3_INPUT_OUTPUT_4_NEWADDEDFROMHERE_CH3_REM_PHY_LPBK_LEN 1 - #define UNIPHY_CHANNEL3_INPUT_OUTPUT_4_NEWADDEDFROMHERE_CH3_REM_PHY_LPBK_DEFAULT 0x0 - /*[field] NEWADDEDFROMHERE_CH3_SPEED_25M*/ - #define UNIPHY_CHANNEL3_INPUT_OUTPUT_4_NEWADDEDFROMHERE_CH3_SPEED_25M - #define UNIPHY_CHANNEL3_INPUT_OUTPUT_4_NEWADDEDFROMHERE_CH3_SPEED_25M_OFFSET 1 - #define UNIPHY_CHANNEL3_INPUT_OUTPUT_4_NEWADDEDFROMHERE_CH3_SPEED_25M_LEN 2 - #define UNIPHY_CHANNEL3_INPUT_OUTPUT_4_NEWADDEDFROMHERE_CH3_SPEED_25M_DEFAULT 0x2 - /*[field] NEWADDEDFROMHERE_CH3_FORCE_SPEED_25M*/ - #define UNIPHY_CHANNEL3_INPUT_OUTPUT_4_NEWADDEDFROMHERE_CH3_FORCE_SPEED_25M - #define UNIPHY_CHANNEL3_INPUT_OUTPUT_4_NEWADDEDFROMHERE_CH3_FORCE_SPEED_25M_OFFSET 3 - #define UNIPHY_CHANNEL3_INPUT_OUTPUT_4_NEWADDEDFROMHERE_CH3_FORCE_SPEED_25M_LEN 1 - #define UNIPHY_CHANNEL3_INPUT_OUTPUT_4_NEWADDEDFROMHERE_CH3_FORCE_SPEED_25M_DEFAULT 0x0 - /*[field] NEWADDEDFROMHERE_CH3_MR_NP_LOADED_25M*/ - #define UNIPHY_CHANNEL3_INPUT_OUTPUT_4_NEWADDEDFROMHERE_CH3_MR_NP_LOADED_25M - #define UNIPHY_CHANNEL3_INPUT_OUTPUT_4_NEWADDEDFROMHERE_CH3_MR_NP_LOADED_25M_OFFSET 4 - #define UNIPHY_CHANNEL3_INPUT_OUTPUT_4_NEWADDEDFROMHERE_CH3_MR_NP_LOADED_25M_LEN 1 - #define UNIPHY_CHANNEL3_INPUT_OUTPUT_4_NEWADDEDFROMHERE_CH3_MR_NP_LOADED_25M_DEFAULT 0x0 - /*[field] NEWADDEDFROMHERE_CH3_MR_REG4_CH_25M*/ - #define UNIPHY_CHANNEL3_INPUT_OUTPUT_4_NEWADDEDFROMHERE_CH3_MR_REG4_CH_25M - #define UNIPHY_CHANNEL3_INPUT_OUTPUT_4_NEWADDEDFROMHERE_CH3_MR_REG4_CH_25M_OFFSET 5 - #define UNIPHY_CHANNEL3_INPUT_OUTPUT_4_NEWADDEDFROMHERE_CH3_MR_REG4_CH_25M_LEN 1 - #define UNIPHY_CHANNEL3_INPUT_OUTPUT_4_NEWADDEDFROMHERE_CH3_MR_REG4_CH_25M_DEFAULT 0x0 - /*[field] NEWADDEDFROMHERE_CH3_MR_AN_ENABLE_25M*/ - #define UNIPHY_CHANNEL3_INPUT_OUTPUT_4_NEWADDEDFROMHERE_CH3_MR_AN_ENABLE_25M - #define UNIPHY_CHANNEL3_INPUT_OUTPUT_4_NEWADDEDFROMHERE_CH3_MR_AN_ENABLE_25M_OFFSET 6 - #define UNIPHY_CHANNEL3_INPUT_OUTPUT_4_NEWADDEDFROMHERE_CH3_MR_AN_ENABLE_25M_LEN 1 - #define UNIPHY_CHANNEL3_INPUT_OUTPUT_4_NEWADDEDFROMHERE_CH3_MR_AN_ENABLE_25M_DEFAULT 0x1 - /*[field] NEWADDEDFROMHERE_CH3_MR_RESTART_AN_25M*/ - #define UNIPHY_CHANNEL3_INPUT_OUTPUT_4_NEWADDEDFROMHERE_CH3_MR_RESTART_AN_25M - #define UNIPHY_CHANNEL3_INPUT_OUTPUT_4_NEWADDEDFROMHERE_CH3_MR_RESTART_AN_25M_OFFSET 7 - #define UNIPHY_CHANNEL3_INPUT_OUTPUT_4_NEWADDEDFROMHERE_CH3_MR_RESTART_AN_25M_LEN 1 - #define UNIPHY_CHANNEL3_INPUT_OUTPUT_4_NEWADDEDFROMHERE_CH3_MR_RESTART_AN_25M_DEFAULT 0x0 - /*[field] NEWADDEDFROMHERE_CH3_MR_LOOPBACK_25M*/ - #define UNIPHY_CHANNEL3_INPUT_OUTPUT_4_NEWADDEDFROMHERE_CH3_MR_LOOPBACK_25M - #define UNIPHY_CHANNEL3_INPUT_OUTPUT_4_NEWADDEDFROMHERE_CH3_MR_LOOPBACK_25M_OFFSET 8 - #define UNIPHY_CHANNEL3_INPUT_OUTPUT_4_NEWADDEDFROMHERE_CH3_MR_LOOPBACK_25M_LEN 1 - #define UNIPHY_CHANNEL3_INPUT_OUTPUT_4_NEWADDEDFROMHERE_CH3_MR_LOOPBACK_25M_DEFAULT 0x0 - /*[field] NEWADDEDFROMHERE_CH3_MR_MAIN_RESET_25M*/ - #define UNIPHY_CHANNEL3_INPUT_OUTPUT_4_NEWADDEDFROMHERE_CH3_MR_MAIN_RESET_25M - #define UNIPHY_CHANNEL3_INPUT_OUTPUT_4_NEWADDEDFROMHERE_CH3_MR_MAIN_RESET_25M_OFFSET 9 - #define UNIPHY_CHANNEL3_INPUT_OUTPUT_4_NEWADDEDFROMHERE_CH3_MR_MAIN_RESET_25M_LEN 1 - #define UNIPHY_CHANNEL3_INPUT_OUTPUT_4_NEWADDEDFROMHERE_CH3_MR_MAIN_RESET_25M_DEFAULT 0x0 - /*[field] NEWADDEDFROMHERE_CH3_POWER_ON_25M*/ - #define UNIPHY_CHANNEL3_INPUT_OUTPUT_4_NEWADDEDFROMHERE_CH3_POWER_ON_25M - #define UNIPHY_CHANNEL3_INPUT_OUTPUT_4_NEWADDEDFROMHERE_CH3_POWER_ON_25M_OFFSET 10 - #define UNIPHY_CHANNEL3_INPUT_OUTPUT_4_NEWADDEDFROMHERE_CH3_POWER_ON_25M_LEN 1 - #define UNIPHY_CHANNEL3_INPUT_OUTPUT_4_NEWADDEDFROMHERE_CH3_POWER_ON_25M_DEFAULT 0x0 - /*[field] NEWADDEDFROMHERE_CH3_ADP_SW_RSTN*/ - #define UNIPHY_CHANNEL3_INPUT_OUTPUT_4_NEWADDEDFROMHERE_CH3_ADP_SW_RSTN - #define UNIPHY_CHANNEL3_INPUT_OUTPUT_4_NEWADDEDFROMHERE_CH3_ADP_SW_RSTN_OFFSET 11 - #define UNIPHY_CHANNEL3_INPUT_OUTPUT_4_NEWADDEDFROMHERE_CH3_ADP_SW_RSTN_LEN 1 - #define UNIPHY_CHANNEL3_INPUT_OUTPUT_4_NEWADDEDFROMHERE_CH3_ADP_SW_RSTN_DEFAULT 0x1 - -struct uniphy_channel3_input_output_4 { - a_uint32_t newaddedfromhere_ch3_rem_phy_lpbk:1; - a_uint32_t newaddedfromhere_ch3_speed_25m:2; - a_uint32_t newaddedfromhere_ch3_force_speed_25m:1; - a_uint32_t newaddedfromhere_ch3_mr_np_loaded_25m:1; - a_uint32_t newaddedfromhere_ch3_mr_reg4_ch_25m:1; - a_uint32_t newaddedfromhere_ch3_mr_an_enable_25m:1; - a_uint32_t newaddedfromhere_ch3_mr_restart_an_25m:1; - a_uint32_t newaddedfromhere_ch3_mr_loopback_25m:1; - a_uint32_t newaddedfromhere_ch3_mr_main_reset_25m:1; - a_uint32_t newaddedfromhere_ch3_power_on_25m:1; - a_uint32_t newaddedfromhere_ch3_adp_sw_rstn:1; - a_uint32_t _reserved0:20; -}; - -union uniphy_channel3_input_output_4_u { - a_uint32_t val; - struct uniphy_channel3_input_output_4 bf; -}; - -/*[register] UNIPHY_CHANNEL4_INPUT_OUTPUT_4*/ -#define UNIPHY_CHANNEL4_INPUT_OUTPUT_4 -#define UNIPHY_CHANNEL4_INPUT_OUTPUT_4_ADDRESS 0x4e0 -#define UNIPHY_CHANNEL4_INPUT_OUTPUT_4_NUM 3 -#define UNIPHY_CHANNEL4_INPUT_OUTPUT_4_INC 0x1 -#define UNIPHY_CHANNEL4_INPUT_OUTPUT_4_TYPE REG_TYPE_RW -#define UNIPHY_CHANNEL4_INPUT_OUTPUT_4_DEFAULT 0x844 - /*[field] NEWADDEDFROMHERE_CH4_REM_PHY_LPBK*/ - #define UNIPHY_CHANNEL4_INPUT_OUTPUT_4_NEWADDEDFROMHERE_CH4_REM_PHY_LPBK - #define UNIPHY_CHANNEL4_INPUT_OUTPUT_4_NEWADDEDFROMHERE_CH4_REM_PHY_LPBK_OFFSET 0 - #define UNIPHY_CHANNEL4_INPUT_OUTPUT_4_NEWADDEDFROMHERE_CH4_REM_PHY_LPBK_LEN 1 - #define UNIPHY_CHANNEL4_INPUT_OUTPUT_4_NEWADDEDFROMHERE_CH4_REM_PHY_LPBK_DEFAULT 0x0 - /*[field] NEWADDEDFROMHERE_CH4_SPEED_25M*/ - #define UNIPHY_CHANNEL4_INPUT_OUTPUT_4_NEWADDEDFROMHERE_CH4_SPEED_25M - #define UNIPHY_CHANNEL4_INPUT_OUTPUT_4_NEWADDEDFROMHERE_CH4_SPEED_25M_OFFSET 1 - #define UNIPHY_CHANNEL4_INPUT_OUTPUT_4_NEWADDEDFROMHERE_CH4_SPEED_25M_LEN 2 - #define UNIPHY_CHANNEL4_INPUT_OUTPUT_4_NEWADDEDFROMHERE_CH4_SPEED_25M_DEFAULT 0x2 - /*[field] NEWADDEDFROMHERE_CH4_FORCE_SPEED_25M*/ - #define UNIPHY_CHANNEL4_INPUT_OUTPUT_4_NEWADDEDFROMHERE_CH4_FORCE_SPEED_25M - #define UNIPHY_CHANNEL4_INPUT_OUTPUT_4_NEWADDEDFROMHERE_CH4_FORCE_SPEED_25M_OFFSET 3 - #define UNIPHY_CHANNEL4_INPUT_OUTPUT_4_NEWADDEDFROMHERE_CH4_FORCE_SPEED_25M_LEN 1 - #define UNIPHY_CHANNEL4_INPUT_OUTPUT_4_NEWADDEDFROMHERE_CH4_FORCE_SPEED_25M_DEFAULT 0x0 - /*[field] NEWADDEDFROMHERE_CH4_MR_NP_LOADED_25M*/ - #define UNIPHY_CHANNEL4_INPUT_OUTPUT_4_NEWADDEDFROMHERE_CH4_MR_NP_LOADED_25M - #define UNIPHY_CHANNEL4_INPUT_OUTPUT_4_NEWADDEDFROMHERE_CH4_MR_NP_LOADED_25M_OFFSET 4 - #define UNIPHY_CHANNEL4_INPUT_OUTPUT_4_NEWADDEDFROMHERE_CH4_MR_NP_LOADED_25M_LEN 1 - #define UNIPHY_CHANNEL4_INPUT_OUTPUT_4_NEWADDEDFROMHERE_CH4_MR_NP_LOADED_25M_DEFAULT 0x0 - /*[field] NEWADDEDFROMHERE_CH4_MR_REG4_CH_25M*/ - #define UNIPHY_CHANNEL4_INPUT_OUTPUT_4_NEWADDEDFROMHERE_CH4_MR_REG4_CH_25M - #define UNIPHY_CHANNEL4_INPUT_OUTPUT_4_NEWADDEDFROMHERE_CH4_MR_REG4_CH_25M_OFFSET 5 - #define UNIPHY_CHANNEL4_INPUT_OUTPUT_4_NEWADDEDFROMHERE_CH4_MR_REG4_CH_25M_LEN 1 - #define UNIPHY_CHANNEL4_INPUT_OUTPUT_4_NEWADDEDFROMHERE_CH4_MR_REG4_CH_25M_DEFAULT 0x0 - /*[field] NEWADDEDFROMHERE_CH4_MR_AN_ENABLE_25M*/ - #define UNIPHY_CHANNEL4_INPUT_OUTPUT_4_NEWADDEDFROMHERE_CH4_MR_AN_ENABLE_25M - #define UNIPHY_CHANNEL4_INPUT_OUTPUT_4_NEWADDEDFROMHERE_CH4_MR_AN_ENABLE_25M_OFFSET 6 - #define UNIPHY_CHANNEL4_INPUT_OUTPUT_4_NEWADDEDFROMHERE_CH4_MR_AN_ENABLE_25M_LEN 1 - #define UNIPHY_CHANNEL4_INPUT_OUTPUT_4_NEWADDEDFROMHERE_CH4_MR_AN_ENABLE_25M_DEFAULT 0x1 - /*[field] NEWADDEDFROMHERE_CH4_MR_RESTART_AN_25M*/ - #define UNIPHY_CHANNEL4_INPUT_OUTPUT_4_NEWADDEDFROMHERE_CH4_MR_RESTART_AN_25M - #define UNIPHY_CHANNEL4_INPUT_OUTPUT_4_NEWADDEDFROMHERE_CH4_MR_RESTART_AN_25M_OFFSET 7 - #define UNIPHY_CHANNEL4_INPUT_OUTPUT_4_NEWADDEDFROMHERE_CH4_MR_RESTART_AN_25M_LEN 1 - #define UNIPHY_CHANNEL4_INPUT_OUTPUT_4_NEWADDEDFROMHERE_CH4_MR_RESTART_AN_25M_DEFAULT 0x0 - /*[field] NEWADDEDFROMHERE_CH4_MR_LOOPBACK_25M*/ - #define UNIPHY_CHANNEL4_INPUT_OUTPUT_4_NEWADDEDFROMHERE_CH4_MR_LOOPBACK_25M - #define UNIPHY_CHANNEL4_INPUT_OUTPUT_4_NEWADDEDFROMHERE_CH4_MR_LOOPBACK_25M_OFFSET 8 - #define UNIPHY_CHANNEL4_INPUT_OUTPUT_4_NEWADDEDFROMHERE_CH4_MR_LOOPBACK_25M_LEN 1 - #define UNIPHY_CHANNEL4_INPUT_OUTPUT_4_NEWADDEDFROMHERE_CH4_MR_LOOPBACK_25M_DEFAULT 0x0 - /*[field] NEWADDEDFROMHERE_CH4_MR_MAIN_RESET_25M*/ - #define UNIPHY_CHANNEL4_INPUT_OUTPUT_4_NEWADDEDFROMHERE_CH4_MR_MAIN_RESET_25M - #define UNIPHY_CHANNEL4_INPUT_OUTPUT_4_NEWADDEDFROMHERE_CH4_MR_MAIN_RESET_25M_OFFSET 9 - #define UNIPHY_CHANNEL4_INPUT_OUTPUT_4_NEWADDEDFROMHERE_CH4_MR_MAIN_RESET_25M_LEN 1 - #define UNIPHY_CHANNEL4_INPUT_OUTPUT_4_NEWADDEDFROMHERE_CH4_MR_MAIN_RESET_25M_DEFAULT 0x0 - /*[field] NEWADDEDFROMHERE_CH4_POWER_ON_25M*/ - #define UNIPHY_CHANNEL4_INPUT_OUTPUT_4_NEWADDEDFROMHERE_CH4_POWER_ON_25M - #define UNIPHY_CHANNEL4_INPUT_OUTPUT_4_NEWADDEDFROMHERE_CH4_POWER_ON_25M_OFFSET 10 - #define UNIPHY_CHANNEL4_INPUT_OUTPUT_4_NEWADDEDFROMHERE_CH4_POWER_ON_25M_LEN 1 - #define UNIPHY_CHANNEL4_INPUT_OUTPUT_4_NEWADDEDFROMHERE_CH4_POWER_ON_25M_DEFAULT 0x0 - /*[field] NEWADDEDFROMHERE_CH4_ADP_SW_RSTN*/ - #define UNIPHY_CHANNEL4_INPUT_OUTPUT_4_NEWADDEDFROMHERE_CH4_ADP_SW_RSTN - #define UNIPHY_CHANNEL4_INPUT_OUTPUT_4_NEWADDEDFROMHERE_CH4_ADP_SW_RSTN_OFFSET 11 - #define UNIPHY_CHANNEL4_INPUT_OUTPUT_4_NEWADDEDFROMHERE_CH4_ADP_SW_RSTN_LEN 1 - #define UNIPHY_CHANNEL4_INPUT_OUTPUT_4_NEWADDEDFROMHERE_CH4_ADP_SW_RSTN_DEFAULT 0x1 - -struct uniphy_channel4_input_output_4 { - a_uint32_t newaddedfromhere_ch4_rem_phy_lpbk:1; - a_uint32_t newaddedfromhere_ch4_speed_25m:2; - a_uint32_t newaddedfromhere_ch4_force_speed_25m:1; - a_uint32_t newaddedfromhere_ch4_mr_np_loaded_25m:1; - a_uint32_t newaddedfromhere_ch4_mr_reg4_ch_25m:1; - a_uint32_t newaddedfromhere_ch4_mr_an_enable_25m:1; - a_uint32_t newaddedfromhere_ch4_mr_restart_an_25m:1; - a_uint32_t newaddedfromhere_ch4_mr_loopback_25m:1; - a_uint32_t newaddedfromhere_ch4_mr_main_reset_25m:1; - a_uint32_t newaddedfromhere_ch4_power_on_25m:1; - a_uint32_t newaddedfromhere_ch4_adp_sw_rstn:1; - a_uint32_t _reserved0:20; -}; - -union uniphy_channel4_input_output_4_u { - a_uint32_t val; - struct uniphy_channel4_input_output_4 bf; -}; - -/*[register] UNIPHY_INSTANCE_LINK_DETECT*/ -#define UNIPHY_INSTANCE_LINK_DETECT -#define UNIPHY_INSTANCE_LINK_DETECT_ADDRESS 0x570 -#define UNIPHY_INSTANCE_LINK_DETECT_NUM 3 -#define UNIPHY_INSTANCE_LINK_DETECT_INC 0x1 -#define UNIPHY_INSTANCE_LINK_DETECT_TYPE REG_TYPE_RW -#define UNIPHY_INSTANCE_LINK_DETECT_DEFAULT 0x0 - -struct uniphy_instance_link_detect { - a_uint32_t _reserved0:6; - a_uint32_t detect_los_from_sfp:3; - a_uint32_t _reserved1:23; -}; - -union uniphy_instance_link_detect_u { - a_uint32_t val; - struct uniphy_instance_link_detect bf; -}; - -/*[register] SR_XS_PCS_KR_STS1*/ -#define SR_XS_PCS_KR_STS1 -#define SR_XS_PCS_KR_STS1_ADDRESS 0x30020 -#define SR_XS_PCS_KR_STS1_NUM 3 -#define SR_XS_PCS_KR_STS1_INC 0x1 -#define SR_XS_PCS_KR_STS1_TYPE REG_TYPE_RW -#define SR_XS_PCS_KR_STS1_DEFAULT 0x0 - /*[field] RPCS_BKLK*/ - #define SR_XS_PCS_KR_STS1_RPCS_BKLK - #define SR_XS_PCS_KR_STS1_RPCS_BKLK_OFFSET 0 - #define SR_XS_PCS_KR_STS1_RPCS_BKLK_LEN 1 - #define SR_XS_PCS_KR_STS1_RPCS_BKLK_DEFAULT 0x0 - /*[field] PRCS_HIBER*/ - #define SR_XS_PCS_KR_STS1_PRCS_HIBER - #define SR_XS_PCS_KR_STS1_PRCS_HIBER_OFFSET 1 - #define SR_XS_PCS_KR_STS1_PRCS_HIBER_LEN 1 - #define SR_XS_PCS_KR_STS1_PRCS_HIBER_DEFAULT 0x0 - /*[field] PRBS31ABL*/ - #define SR_XS_PCS_KR_STS1_PRBS31ABL - #define SR_XS_PCS_KR_STS1_PRBS31ABL_OFFSET 2 - #define SR_XS_PCS_KR_STS1_PRBS31ABL_LEN 1 - #define SR_XS_PCS_KR_STS1_PRBS31ABL_DEFAULT 0x0 - /*[field] PRBS9ABL*/ - #define SR_XS_PCS_KR_STS1_PRBS9ABL - #define SR_XS_PCS_KR_STS1_PRBS9ABL_OFFSET 3 - #define SR_XS_PCS_KR_STS1_PRBS9ABL_LEN 1 - #define SR_XS_PCS_KR_STS1_PRBS9ABL_DEFAULT 0x0 - /*[field] PLU*/ - #define SR_XS_PCS_KR_STS1_PLU - #define SR_XS_PCS_KR_STS1_PLU_OFFSET 12 - #define SR_XS_PCS_KR_STS1_PLU_LEN 1 - #define SR_XS_PCS_KR_STS1_PLU_DEFAULT 0x0 - -struct sr_xs_pcs_kr_sts1 { - a_uint32_t rpcs_bklk:1; - a_uint32_t prcs_hiber:1; - a_uint32_t prbs31abl:1; - a_uint32_t prbs9abl:1; - a_uint32_t _reserved0:8; - a_uint32_t plu:1; - a_uint32_t _reserved1:19; -}; - -union sr_xs_pcs_kr_sts1_u { - a_uint32_t val; - struct sr_xs_pcs_kr_sts1 bf; -}; - -/*[register] VR_XS_PCS_DIG_CTRL1*/ -#define VR_XS_PCS_DIG_CTRL1 -#define VR_XS_PCS_DIG_CTRL1_ADDRESS 0x38000 -#define VR_XS_PCS_DIG_CTRL1_NUM 3 -#define VR_XS_PCS_DIG_CTRL1_INC 0x1 -#define VR_XS_PCS_DIG_CTRL1_TYPE REG_TYPE_RW -#define VR_XS_PCS_DIG_CTRL1_DEFAULT 0x0 - /*[field] DSKBYP*/ - #define VR_XS_PCS_DIG_CTRL1_DSKBYP - #define VR_XS_PCS_DIG_CTRL1_DSKBYP_OFFSET 0 - #define VR_XS_PCS_DIG_CTRL1_DSKBYP_LEN 1 - #define VR_XS_PCS_DIG_CTRL1_DSKBYP_DEFAULT 0x0 - /*[field] BYP_PWRUP*/ - #define VR_XS_PCS_DIG_CTRL1_BYP_PWRUP - #define VR_XS_PCS_DIG_CTRL1_BYP_PWRUP_OFFSET 1 - #define VR_XS_PCS_DIG_CTRL1_BYP_PWRUP_LEN 1 - #define VR_XS_PCS_DIG_CTRL1_BYP_PWRUP_DEFAULT 0x0 - /*[field] EN_2_5G_MODE*/ - #define VR_XS_PCS_DIG_CTRL1_EN_2_5G_MODE - #define VR_XS_PCS_DIG_CTRL1_EN_2_5G_MODE_OFFSET 2 - #define VR_XS_PCS_DIG_CTRL1_EN_2_5G_MODE_LEN 1 - #define VR_XS_PCS_DIG_CTRL1_EN_2_5G_MODE_DEFAULT 0x0 - /*[field] CR_CJN*/ - #define VR_XS_PCS_DIG_CTRL1_CR_CJN - #define VR_XS_PCS_DIG_CTRL1_CR_CJN_OFFSET 3 - #define VR_XS_PCS_DIG_CTRL1_CR_CJN_LEN 1 - #define VR_XS_PCS_DIG_CTRL1_CR_CJN_DEFAULT 0x0 - /*[field] DTXLANED_0*/ - #define VR_XS_PCS_DIG_CTRL1_DTXLANED_0 - #define VR_XS_PCS_DIG_CTRL1_DTXLANED_0_OFFSET 4 - #define VR_XS_PCS_DIG_CTRL1_DTXLANED_0_LEN 1 - #define VR_XS_PCS_DIG_CTRL1_DTXLANED_0_DEFAULT 0x0 - /*[field] DTXLANED_3_1*/ - #define VR_XS_PCS_DIG_CTRL1_DTXLANED_3_1 - #define VR_XS_PCS_DIG_CTRL1_DTXLANED_3_1_OFFSET 5 - #define VR_XS_PCS_DIG_CTRL1_DTXLANED_3_1_LEN 3 - #define VR_XS_PCS_DIG_CTRL1_DTXLANED_3_1_DEFAULT 0x0 - /*[field] INIT*/ - #define VR_XS_PCS_DIG_CTRL1_INIT - #define VR_XS_PCS_DIG_CTRL1_INIT_OFFSET 8 - #define VR_XS_PCS_DIG_CTRL1_INIT_LEN 1 - #define VR_XS_PCS_DIG_CTRL1_INIT_DEFAULT 0x0 - /*[field] USXG_EN*/ - #define VR_XS_PCS_DIG_CTRL1_USXG_EN - #define VR_XS_PCS_DIG_CTRL1_USXG_EN_OFFSET 9 - #define VR_XS_PCS_DIG_CTRL1_USXG_EN_LEN 1 - #define VR_XS_PCS_DIG_CTRL1_USXG_EN_DEFAULT 0x0 - /*[field] USRA_RST*/ - #define VR_XS_PCS_DIG_CTRL1_USRA_RST - #define VR_XS_PCS_DIG_CTRL1_USRA_RST_OFFSET 10 - #define VR_XS_PCS_DIG_CTRL1_USRA_RST_LEN 1 - #define VR_XS_PCS_DIG_CTRL1_USRA_RST_DEFAULT 0x0 - /*[field] PWRSV*/ - #define VR_XS_PCS_DIG_CTRL1_PWRSV - #define VR_XS_PCS_DIG_CTRL1_PWRSV_OFFSET 11 - #define VR_XS_PCS_DIG_CTRL1_PWRSV_LEN 1 - #define VR_XS_PCS_DIG_CTRL1_PWRSV_DEFAULT 0x0 - /*[field] CL37_BP*/ - #define VR_XS_PCS_DIG_CTRL1_CL37_BP - #define VR_XS_PCS_DIG_CTRL1_CL37_BP_OFFSET 12 - #define VR_XS_PCS_DIG_CTRL1_CL37_BP_LEN 1 - #define VR_XS_PCS_DIG_CTRL1_CL37_BP_DEFAULT 0x0 - /*[field] EN_VSMMD1*/ - #define VR_XS_PCS_DIG_CTRL1_EN_VSMMD1 - #define VR_XS_PCS_DIG_CTRL1_EN_VSMMD1_OFFSET 13 - #define VR_XS_PCS_DIG_CTRL1_EN_VSMMD1_LEN 1 - #define VR_XS_PCS_DIG_CTRL1_EN_VSMMD1_DEFAULT 0x0 - /*[field] R2TLBE*/ - #define VR_XS_PCS_DIG_CTRL1_R2TLBE - #define VR_XS_PCS_DIG_CTRL1_R2TLBE_OFFSET 14 - #define VR_XS_PCS_DIG_CTRL1_R2TLBE_LEN 1 - #define VR_XS_PCS_DIG_CTRL1_R2TLBE_DEFAULT 0x0 - /*[field] VR_RST*/ - #define VR_XS_PCS_DIG_CTRL1_VR_RST - #define VR_XS_PCS_DIG_CTRL1_VR_RST_OFFSET 15 - #define VR_XS_PCS_DIG_CTRL1_VR_RST_LEN 1 - #define VR_XS_PCS_DIG_CTRL1_VR_RST_DEFAULT 0x0 - -struct vr_xs_pcs_dig_ctrl1 { - a_uint32_t dskbyp:1; - a_uint32_t byp_pwrup:1; - a_uint32_t en_2_5g_mode:1; - a_uint32_t cr_cjn:1; - a_uint32_t dtxlaned_0:1; - a_uint32_t dtxlaned_3_1:3; - a_uint32_t init:1; - a_uint32_t usxg_en:1; - a_uint32_t usra_rst:1; - a_uint32_t pwrsv:1; - a_uint32_t cl37_bp:1; - a_uint32_t en_vsmmd1:1; - a_uint32_t r2tlbe:1; - a_uint32_t vr_rst:1; - a_uint32_t _reserved0:16; -}; - -union vr_xs_pcs_dig_ctrl1_u { - a_uint32_t val; - struct vr_xs_pcs_dig_ctrl1 bf; -}; - -/*[register] SR_MII_CTRL*/ -#define SR_MII_CTRL -#define SR_MII_CTRL_ADDRESS 0x1f0000 -#define SR_MII_CTRL_NUM 3 -#define SR_MII_CTRL_INC 0x1 -#define SR_MII_CTRL_TYPE REG_TYPE_RW -#define SR_MII_CTRL_DEFAULT 0x0 - /*[field] SS5*/ - #define SR_MII_CTRL_SS5 - #define SR_MII_CTRL_SS5_OFFSET 5 - #define SR_MII_CTRL_SS5_LEN 1 - #define SR_MII_CTRL_SS5_DEFAULT 0x0 - /*[field] SS6*/ - #define SR_MII_CTRL_SS6 - #define SR_MII_CTRL_SS6_OFFSET 6 - #define SR_MII_CTRL_SS6_LEN 1 - #define SR_MII_CTRL_SS6_DEFAULT 0x0 - /*[field] DUPLEX_MODE*/ - #define SR_MII_CTRL_DUPLEX_MODE - #define SR_MII_CTRL_DUPLEX_MODE_OFFSET 8 - #define SR_MII_CTRL_DUPLEX_MODE_LEN 1 - #define SR_MII_CTRL_DUPLEX_MODE_DEFAULT 0x0 - /*[field] RESTART_AN*/ - #define SR_MII_CTRL_RESTART_AN - #define SR_MII_CTRL_RESTART_AN_OFFSET 9 - #define SR_MII_CTRL_RESTART_AN_LEN 1 - #define SR_MII_CTRL_RESTART_AN_DEFAULT 0x0 - /*[field] LPM*/ - #define SR_MII_CTRL_LPM - #define SR_MII_CTRL_LPM_OFFSET 11 - #define SR_MII_CTRL_LPM_LEN 1 - #define SR_MII_CTRL_LPM_DEFAULT 0x0 - /*[field] AN_ENABLE*/ - #define SR_MII_CTRL_AN_ENABLE - #define SR_MII_CTRL_AN_ENABLE_OFFSET 12 - #define SR_MII_CTRL_AN_ENABLE_LEN 1 - #define SR_MII_CTRL_AN_ENABLE_DEFAULT 0x0 - /*[field] SS13*/ - #define SR_MII_CTRL_SS13 - #define SR_MII_CTRL_SS13_OFFSET 13 - #define SR_MII_CTRL_SS13_LEN 1 - #define SR_MII_CTRL_SS13_DEFAULT 0x0 - /*[field] LBE*/ - #define SR_MII_CTRL_LBE - #define SR_MII_CTRL_LBE_OFFSET 14 - #define SR_MII_CTRL_LBE_LEN 1 - #define SR_MII_CTRL_LBE_DEFAULT 0x0 - /*[field] RST*/ - #define SR_MII_CTRL_RST - #define SR_MII_CTRL_RST_OFFSET 15 - #define SR_MII_CTRL_RST_LEN 1 - #define SR_MII_CTRL_RST_DEFAULT 0x0 - -struct sr_mii_ctrl { - a_uint32_t _reserved0:5; - a_uint32_t ss5:1; - a_uint32_t ss6:1; - a_uint32_t _reserved1:1; - a_uint32_t duplex_mode:1; - a_uint32_t restart_an:1; - a_uint32_t _reserved2:1; - a_uint32_t lpm:1; - a_uint32_t an_enable:1; - a_uint32_t ss13:1; - a_uint32_t lbe:1; - a_uint32_t rst:1; - a_uint32_t _reserved3:16; -}; - -union sr_mii_ctrl_u { - a_uint32_t val; - struct sr_mii_ctrl bf; -}; - -/*[register] VR_MII_AN_CTRL*/ -#define VR_MII_AN_CTRL -#define VR_MII_AN_CTRL_ADDRESS 0x1f8001 -#define VR_MII_AN_CTRL_NUM 3 -#define VR_MII_AN_CTRL_INC 0x1 -#define VR_MII_AN_CTRL_TYPE REG_TYPE_RW -#define VR_MII_AN_CTRL_DEFAULT 0x0 - /*[field] MII_AN_INTR_EN*/ - #define VR_MII_AN_CTRL_MII_AN_INTR_EN - #define VR_MII_AN_CTRL_MII_AN_INTR_EN_OFFSET 0 - #define VR_MII_AN_CTRL_MII_AN_INTR_EN_LEN 1 - #define VR_MII_AN_CTRL_MII_AN_INTR_EN_DEFAULT 0x0 - /*[field] PCS_MODE*/ - #define VR_MII_AN_CTRL_PCS_MODE - #define VR_MII_AN_CTRL_PCS_MODE_OFFSET 1 - #define VR_MII_AN_CTRL_PCS_MODE_LEN 2 - #define VR_MII_AN_CTRL_PCS_MODE_DEFAULT 0x0 - /*[field] TX_CONFIG*/ - #define VR_MII_AN_CTRL_TX_CONFIG - #define VR_MII_AN_CTRL_TX_CONFIG_OFFSET 3 - #define VR_MII_AN_CTRL_TX_CONFIG_LEN 1 - #define VR_MII_AN_CTRL_TX_CONFIG_DEFAULT 0x0 - /*[field] SGMII_LINK_STS*/ - #define VR_MII_AN_CTRL_SGMII_LINK_STS - #define VR_MII_AN_CTRL_SGMII_LINK_STS_OFFSET 4 - #define VR_MII_AN_CTRL_SGMII_LINK_STS_LEN 1 - #define VR_MII_AN_CTRL_SGMII_LINK_STS_DEFAULT 0x0 - /*[field] MII_CTRL*/ - #define VR_MII_AN_CTRL_MII_CTRL - #define VR_MII_AN_CTRL_MII_CTRL_OFFSET 8 - #define VR_MII_AN_CTRL_MII_CTRL_LEN 1 - #define VR_MII_AN_CTRL_MII_CTRL_DEFAULT 0x0 - -struct vr_mii_an_ctrl { - a_uint32_t mii_an_intr_en:1; - a_uint32_t pcs_mode:2; - a_uint32_t tx_config:1; - a_uint32_t sgmii_link_sts:1; - a_uint32_t _reserved0:3; - a_uint32_t mii_ctrl:1; - a_uint32_t _reserved1:23; -}; - -union vr_mii_an_ctrl_u { - a_uint32_t val; - struct vr_mii_an_ctrl bf; -}; - -/*[register] VR_MII_AN_INTR_STS*/ -#define VR_MII_AN_INTR_STS -#define VR_MII_AN_INTR_STS_ADDRESS 0x1f8002 -#define VR_MII_AN_INTR_STS_NUM 3 -#define VR_MII_AN_INTR_STS_INC 0x1 -#define VR_MII_AN_INTR_STS_TYPE REG_TYPE_RW -#define VR_MII_AN_INTR_STS_DEFAULT 0x0 - /*[field] CL37_ANCMPLT_INTR*/ - #define VR_MII_AN_INTR_STS_CL37_ANCMPLT_INTR - #define VR_MII_AN_INTR_STS_CL37_ANCMPLT_INTR_OFFSET 0 - #define VR_MII_AN_INTR_STS_CL37_ANCMPLT_INTR_LEN 1 - #define VR_MII_AN_INTR_STS_CL37_ANCMPLT_INTR_DEFAULT 0x0 - /*[field] CL37_ANSGM_STS*/ - #define VR_MII_AN_INTR_STS_CL37_ANSGM_STS - #define VR_MII_AN_INTR_STS_CL37_ANSGM_STS_OFFSET 1 - #define VR_MII_AN_INTR_STS_CL37_ANSGM_STS_LEN 4 - #define VR_MII_AN_INTR_STS_CL37_ANSGM_STS_DEFAULT 0x0 - /*[field] USXG_AN_STS*/ - #define VR_MII_AN_INTR_STS_USXG_AN_STS - #define VR_MII_AN_INTR_STS_USXG_AN_STS_OFFSET 8 - #define VR_MII_AN_INTR_STS_USXG_AN_STS_LEN 7 - #define VR_MII_AN_INTR_STS_USXG_AN_STS_DEFAULT 0x0 - -struct vr_mii_an_intr_sts { - a_uint32_t cl37_ancmplt_intr:1; - a_uint32_t cl37_ansgm_sts:4; - a_uint32_t _reserved0:3; - a_uint32_t usxg_an_sts:7; - a_uint32_t _reserved1:17; -}; - -union vr_mii_an_intr_sts_u { - a_uint32_t val; - struct vr_mii_an_intr_sts bf; -}; - -/*[register] UNIPHY_PLL_CONTROL_VCO_RELATED_SELECTION*/ -#define UNIPHY_PLL_CONTROL_VCO_RELATED_SELECTION -#define UNIPHY_PLL_CONTROL_VCO_RELATED_SELECTION_ADDRESS 0x14 -#define UNIPHY_PLL_CONTROL_VCO_RELATED_SELECTION_NUM 3 -#define UNIPHY_PLL_CONTROL_VCO_RELATED_SELECTION_INC 0x1 -#define UNIPHY_PLL_CONTROL_VCO_RELATED_SELECTION_TYPE REG_TYPE_RW -#define UNIPHY_PLL_CONTROL_VCO_RELATED_SELECTION_DEFAULT 0x0 - /*[field] MMD1_REG_SRC_UPHY_PLL_VCO_TEMP_CMP*/ - #define UNIPHY_PLL_CONTROL_VCO_RELATED_SELECTION_MMD1_REG_SRC_UPHY_PLL_VCO_TEMP_CMP - #define UNIPHY_PLL_CONTROL_VCO_RELATED_SELECTION_MMD1_REG_SRC_UPHY_PLL_VCO_TEMP_CMP_OFFSET 2 - #define UNIPHY_PLL_CONTROL_VCO_RELATED_SELECTION_MMD1_REG_SRC_UPHY_PLL_VCO_TEMP_CMP_LEN 2 - #define UNIPHY_PLL_CONTROL_VCO_RELATED_SELECTION_MMD1_REG_SRC_UPHY_PLL_VCO_TEMP_CMP_DEFAULT 0x0 - /*[field] MMD1_REG_SRC_UPHY_PLL_VCO_AMP*/ - #define UNIPHY_PLL_CONTROL_VCO_RELATED_SELECTION_MMD1_REG_SRC_UPHY_PLL_VCO_AMP - #define UNIPHY_PLL_CONTROL_VCO_RELATED_SELECTION_MMD1_REG_SRC_UPHY_PLL_VCO_AMP_OFFSET 4 - #define UNIPHY_PLL_CONTROL_VCO_RELATED_SELECTION_MMD1_REG_SRC_UPHY_PLL_VCO_AMP_LEN 2 - #define UNIPHY_PLL_CONTROL_VCO_RELATED_SELECTION_MMD1_REG_SRC_UPHY_PLL_VCO_AMP_DEFAULT 0x0 - /*[field] MMD1_REG_SRC_UPHY_PLL_VCO_GAIN*/ - #define UNIPHY_PLL_CONTROL_VCO_RELATED_SELECTION_MMD1_REG_SRC_UPHY_PLL_VCO_GAIN - #define UNIPHY_PLL_CONTROL_VCO_RELATED_SELECTION_MMD1_REG_SRC_UPHY_PLL_VCO_GAIN_OFFSET 6 - #define UNIPHY_PLL_CONTROL_VCO_RELATED_SELECTION_MMD1_REG_SRC_UPHY_PLL_VCO_GAIN_LEN 2 - #define UNIPHY_PLL_CONTROL_VCO_RELATED_SELECTION_MMD1_REG_SRC_UPHY_PLL_VCO_GAIN_DEFAULT 0x0 - /*[field] MMD1_REG_SRC_UPHY_PLL_LPF_C2*/ - #define UNIPHY_PLL_CONTROL_VCO_RELATED_SELECTION_MMD1_REG_SRC_UPHY_PLL_LPF_C2 - #define UNIPHY_PLL_CONTROL_VCO_RELATED_SELECTION_MMD1_REG_SRC_UPHY_PLL_LPF_C2_OFFSET 8 - #define UNIPHY_PLL_CONTROL_VCO_RELATED_SELECTION_MMD1_REG_SRC_UPHY_PLL_LPF_C2_LEN 2 - #define UNIPHY_PLL_CONTROL_VCO_RELATED_SELECTION_MMD1_REG_SRC_UPHY_PLL_LPF_C2_DEFAULT 0x0 - /*[field] MMD1_REG_SRC_UPHY_PLL_LPF_RES*/ - #define UNIPHY_PLL_CONTROL_VCO_RELATED_SELECTION_MMD1_REG_SRC_UPHY_PLL_LPF_RES - #define UNIPHY_PLL_CONTROL_VCO_RELATED_SELECTION_MMD1_REG_SRC_UPHY_PLL_LPF_RES_OFFSET 10 - #define UNIPHY_PLL_CONTROL_VCO_RELATED_SELECTION_MMD1_REG_SRC_UPHY_PLL_LPF_RES_LEN 2 - #define UNIPHY_PLL_CONTROL_VCO_RELATED_SELECTION_MMD1_REG_SRC_UPHY_PLL_LPF_RES_DEFAULT 0x0 - /*[field] MMD1_REG_SRC_UPHY_PLL_CP_SEL*/ - #define UNIPHY_PLL_CONTROL_VCO_RELATED_SELECTION_MMD1_REG_SRC_UPHY_PLL_CP_SEL - #define UNIPHY_PLL_CONTROL_VCO_RELATED_SELECTION_MMD1_REG_SRC_UPHY_PLL_CP_SEL_OFFSET 12 - #define UNIPHY_PLL_CONTROL_VCO_RELATED_SELECTION_MMD1_REG_SRC_UPHY_PLL_CP_SEL_LEN 2 - #define UNIPHY_PLL_CONTROL_VCO_RELATED_SELECTION_MMD1_REG_SRC_UPHY_PLL_CP_SEL_DEFAULT 0x0 - /*[field] MMD1_REG_SRC_UPHY_PLL_LPF_DC*/ - #define UNIPHY_PLL_CONTROL_VCO_RELATED_SELECTION_MMD1_REG_SRC_UPHY_PLL_LPF_DC - #define UNIPHY_PLL_CONTROL_VCO_RELATED_SELECTION_MMD1_REG_SRC_UPHY_PLL_LPF_DC_OFFSET 14 - #define UNIPHY_PLL_CONTROL_VCO_RELATED_SELECTION_MMD1_REG_SRC_UPHY_PLL_LPF_DC_LEN 2 - #define UNIPHY_PLL_CONTROL_VCO_RELATED_SELECTION_MMD1_REG_SRC_UPHY_PLL_LPF_DC_DEFAULT 0x0 - -struct uniphy_pll_control_vco_related_selection { - a_uint32_t mmd1_reg_src_uphy_pll_vco_temp_cmp:2; - a_uint32_t mmd1_reg_src_uphy_pll_vco_amp:2; - a_uint32_t mmd1_reg_src_uphy_pll_vco_gain:2; - a_uint32_t mmd1_reg_src_uphy_pll_lpf_c2:2; - a_uint32_t mmd1_reg_src_uphy_pll_lpf_res:2; - a_uint32_t mmd1_reg_src_uphy_pll_cp_sel:2; - a_uint32_t mmd1_reg_src_uphy_pll_lpf_dc:2; - a_uint32_t _reserved0:16; -}; - -union uniphy_pll_control_vco_related_selection_u { - a_uint32_t val; - struct uniphy_pll_control_vco_related_selection bf; -}; - -/*[register] UNIPHY_TX_AC_JTAG_MUX_DRIVER_SELECTION*/ -#define UNIPHY_TX_AC_JTAG_MUX_DRIVER_SELECTION -#define UNIPHY_TX_AC_JTAG_MUX_DRIVER_SELECTION_ADDRESS 0x24 -#define UNIPHY_TX_AC_JTAG_MUX_DRIVER_SELECTION_NUM 3 -#define UNIPHY_TX_AC_JTAG_MUX_DRIVER_SELECTION_INC 0x1 -#define UNIPHY_TX_AC_JTAG_MUX_DRIVER_SELECTION_TYPE REG_TYPE_RW -#define UNIPHY_TX_AC_JTAG_MUX_DRIVER_SELECTION_DEFAULT 0x0 - /*[field] MMD1_REG_SRC_UPHY_TX_EMP_LSB_EN*/ - #define UNIPHY_TX_AC_JTAG_MUX_DRIVER_SELECTION_MMD1_REG_SRC_UPHY_TX_EMP_LSB_EN - #define UNIPHY_TX_AC_JTAG_MUX_DRIVER_SELECTION_MMD1_REG_SRC_UPHY_TX_EMP_LSB_EN_OFFSET 0 - #define UNIPHY_TX_AC_JTAG_MUX_DRIVER_SELECTION_MMD1_REG_SRC_UPHY_TX_EMP_LSB_EN_LEN 2 - #define UNIPHY_TX_AC_JTAG_MUX_DRIVER_SELECTION_MMD1_REG_SRC_UPHY_TX_EMP_LSB_EN_DEFAULT 0x0 - /*[field] MMD1_REG_SRC_UPHY_TX_RESCAL_CODE*/ - #define UNIPHY_TX_AC_JTAG_MUX_DRIVER_SELECTION_MMD1_REG_SRC_UPHY_TX_RESCAL_CODE - #define UNIPHY_TX_AC_JTAG_MUX_DRIVER_SELECTION_MMD1_REG_SRC_UPHY_TX_RESCAL_CODE_OFFSET 2 - #define UNIPHY_TX_AC_JTAG_MUX_DRIVER_SELECTION_MMD1_REG_SRC_UPHY_TX_RESCAL_CODE_LEN 2 - #define UNIPHY_TX_AC_JTAG_MUX_DRIVER_SELECTION_MMD1_REG_SRC_UPHY_TX_RESCAL_CODE_DEFAULT 0x0 - /*[field] MMD1_REG_SRC_UPHY_TX_EMP_LVL*/ - #define UNIPHY_TX_AC_JTAG_MUX_DRIVER_SELECTION_MMD1_REG_SRC_UPHY_TX_EMP_LVL - #define UNIPHY_TX_AC_JTAG_MUX_DRIVER_SELECTION_MMD1_REG_SRC_UPHY_TX_EMP_LVL_OFFSET 4 - #define UNIPHY_TX_AC_JTAG_MUX_DRIVER_SELECTION_MMD1_REG_SRC_UPHY_TX_EMP_LVL_LEN 2 - #define UNIPHY_TX_AC_JTAG_MUX_DRIVER_SELECTION_MMD1_REG_SRC_UPHY_TX_EMP_LVL_DEFAULT 0x0 - /*[field] MMD1_REG_SRC_UPHY_TX_AMP*/ - #define UNIPHY_TX_AC_JTAG_MUX_DRIVER_SELECTION_MMD1_REG_SRC_UPHY_TX_AMP - #define UNIPHY_TX_AC_JTAG_MUX_DRIVER_SELECTION_MMD1_REG_SRC_UPHY_TX_AMP_OFFSET 6 - #define UNIPHY_TX_AC_JTAG_MUX_DRIVER_SELECTION_MMD1_REG_SRC_UPHY_TX_AMP_LEN 2 - #define UNIPHY_TX_AC_JTAG_MUX_DRIVER_SELECTION_MMD1_REG_SRC_UPHY_TX_AMP_DEFAULT 0x0 - /*[field] MMD1_REG_SRC_UPHY_TX_VCM_DELTA*/ - #define UNIPHY_TX_AC_JTAG_MUX_DRIVER_SELECTION_MMD1_REG_SRC_UPHY_TX_VCM_DELTA - #define UNIPHY_TX_AC_JTAG_MUX_DRIVER_SELECTION_MMD1_REG_SRC_UPHY_TX_VCM_DELTA_OFFSET 8 - #define UNIPHY_TX_AC_JTAG_MUX_DRIVER_SELECTION_MMD1_REG_SRC_UPHY_TX_VCM_DELTA_LEN 2 - #define UNIPHY_TX_AC_JTAG_MUX_DRIVER_SELECTION_MMD1_REG_SRC_UPHY_TX_VCM_DELTA_DEFAULT 0x0 - /*[field] MMD1_REG_SRC_UPHY_TX_EN*/ - #define UNIPHY_TX_AC_JTAG_MUX_DRIVER_SELECTION_MMD1_REG_SRC_UPHY_TX_EN - #define UNIPHY_TX_AC_JTAG_MUX_DRIVER_SELECTION_MMD1_REG_SRC_UPHY_TX_EN_OFFSET 10 - #define UNIPHY_TX_AC_JTAG_MUX_DRIVER_SELECTION_MMD1_REG_SRC_UPHY_TX_EN_LEN 2 - #define UNIPHY_TX_AC_JTAG_MUX_DRIVER_SELECTION_MMD1_REG_SRC_UPHY_TX_EN_DEFAULT 0x0 - /*[field] MMD1_REG_SRC_UPHY_TXD_BIT_WIDTH*/ - #define UNIPHY_TX_AC_JTAG_MUX_DRIVER_SELECTION_MMD1_REG_SRC_UPHY_TXD_BIT_WIDTH - #define UNIPHY_TX_AC_JTAG_MUX_DRIVER_SELECTION_MMD1_REG_SRC_UPHY_TXD_BIT_WIDTH_OFFSET 12 - #define UNIPHY_TX_AC_JTAG_MUX_DRIVER_SELECTION_MMD1_REG_SRC_UPHY_TXD_BIT_WIDTH_LEN 2 - #define UNIPHY_TX_AC_JTAG_MUX_DRIVER_SELECTION_MMD1_REG_SRC_UPHY_TXD_BIT_WIDTH_DEFAULT 0x0 - /*[field] MMD1_REG_SRC_UPHY_TX_ACJTAG_BEACON_EN*/ - #define UNIPHY_TX_AC_JTAG_MUX_DRIVER_SELECTION_MMD1_REG_SRC_UPHY_TX_ACJTAG_BEACON_EN - #define UNIPHY_TX_AC_JTAG_MUX_DRIVER_SELECTION_MMD1_REG_SRC_UPHY_TX_ACJTAG_BEACON_EN_OFFSET 14 - #define UNIPHY_TX_AC_JTAG_MUX_DRIVER_SELECTION_MMD1_REG_SRC_UPHY_TX_ACJTAG_BEACON_EN_LEN 2 - #define UNIPHY_TX_AC_JTAG_MUX_DRIVER_SELECTION_MMD1_REG_SRC_UPHY_TX_ACJTAG_BEACON_EN_DEFAULT 0x0 - -struct uniphy_tx_ac_jtag_mux_driver_selection { - a_uint32_t mmd1_reg_src_uphy_tx_emp_lsb_en:2; - a_uint32_t mmd1_reg_src_uphy_tx_rescal_code:2; - a_uint32_t mmd1_reg_src_uphy_tx_emp_lvl:2; - a_uint32_t mmd1_reg_src_uphy_tx_amp:2; - a_uint32_t mmd1_reg_src_uphy_tx_vcm_delta:2; - a_uint32_t mmd1_reg_src_uphy_tx_en:2; - a_uint32_t mmd1_reg_src_uphy_txd_bit_width:2; - a_uint32_t mmd1_reg_src_uphy_tx_acjtag_beacon_en:2; - a_uint32_t _reserved0:16; -}; - -union uniphy_tx_ac_jtag_mux_driver_selection_u { - a_uint32_t val; - struct uniphy_tx_ac_jtag_mux_driver_selection bf; -}; - -/*[register] UNIPHY_RESISTOR_CALIBRATION_1*/ -#define UNIPHY_RESISTOR_CALIBRATION_1 -#define UNIPHY_RESISTOR_CALIBRATION_1_ADDRESS 0x170 -#define UNIPHY_RESISTOR_CALIBRATION_1_NUM 3 -#define UNIPHY_RESISTOR_CALIBRATION_1_INC 0x1 -#define UNIPHY_RESISTOR_CALIBRATION_1_TYPE REG_TYPE_RW -#define UNIPHY_RESISTOR_CALIBRATION_1_DEFAULT 0x0 - /*[field] MMD1_REG_CALIB_RX_REG*/ - #define UNIPHY_RESISTOR_CALIBRATION_1_MMD1_REG_CALIB_RX_REG - #define UNIPHY_RESISTOR_CALIBRATION_1_MMD1_REG_CALIB_RX_REG_OFFSET 0 - #define UNIPHY_RESISTOR_CALIBRATION_1_MMD1_REG_CALIB_RX_REG_LEN 5 - #define UNIPHY_RESISTOR_CALIBRATION_1_MMD1_REG_CALIB_RX_REG_DEFAULT 0x0 - /*[field] MMD1_REG_CALIB_TX_REG*/ - #define UNIPHY_RESISTOR_CALIBRATION_1_MMD1_REG_CALIB_TX_REG - #define UNIPHY_RESISTOR_CALIBRATION_1_MMD1_REG_CALIB_TX_REG_OFFSET 5 - #define UNIPHY_RESISTOR_CALIBRATION_1_MMD1_REG_CALIB_TX_REG_LEN 5 - #define UNIPHY_RESISTOR_CALIBRATION_1_MMD1_REG_CALIB_TX_REG_DEFAULT 0x0 - /*[field] MMD1_REG_VREF_LVL*/ - #define UNIPHY_RESISTOR_CALIBRATION_1_MMD1_REG_VREF_LVL - #define UNIPHY_RESISTOR_CALIBRATION_1_MMD1_REG_VREF_LVL_OFFSET 10 - #define UNIPHY_RESISTOR_CALIBRATION_1_MMD1_REG_VREF_LVL_LEN 5 - #define UNIPHY_RESISTOR_CALIBRATION_1_MMD1_REG_VREF_LVL_DEFAULT 0x0 - /*[field] MMD1_REG_DISABLE_LOAD_RES_TXRX*/ - #define UNIPHY_RESISTOR_CALIBRATION_1_MMD1_REG_DISABLE_LOAD_RES_TXRX - #define UNIPHY_RESISTOR_CALIBRATION_1_MMD1_REG_DISABLE_LOAD_RES_TXRX_OFFSET 15 - #define UNIPHY_RESISTOR_CALIBRATION_1_MMD1_REG_DISABLE_LOAD_RES_TXRX_LEN 1 - #define UNIPHY_RESISTOR_CALIBRATION_1_MMD1_REG_DISABLE_LOAD_RES_TXRX_DEFAULT 0x0 - -struct uniphy_resistor_calibration_1 { - a_uint32_t mmd1_reg_calib_rx_reg:5; - a_uint32_t mmd1_reg_calib_tx_reg:5; - a_uint32_t mmd1_reg_vref_lvl:5; - a_uint32_t mmd1_reg_disable_load_res_txrx:1; - a_uint32_t _reserved0:16; -}; - -union uniphy_resistor_calibration_1_u { - a_uint32_t val; - struct uniphy_resistor_calibration_1 bf; -}; - -/*[register] UNIPHY_PLL_VCO_RELATED_CONTROL_1*/ -#define UNIPHY_PLL_VCO_RELATED_CONTROL_1 -#define UNIPHY_PLL_VCO_RELATED_CONTROL_1_ADDRESS 0x78c -#define UNIPHY_PLL_VCO_RELATED_CONTROL_1_NUM 3 -#define UNIPHY_PLL_VCO_RELATED_CONTROL_1_INC 0x1 -#define UNIPHY_PLL_VCO_RELATED_CONTROL_1_TYPE REG_TYPE_RW -#define UNIPHY_PLL_VCO_RELATED_CONTROL_1_DEFAULT 0x0 - /*[field] MIIREG_REG_UPHY_PLL_VCO_TEMP_CMP*/ - #define UNIPHY_PLL_VCO_RELATED_CONTROL_1_MIIREG_REG_UPHY_PLL_VCO_TEMP_CMP - #define UNIPHY_PLL_VCO_RELATED_CONTROL_1_MIIREG_REG_UPHY_PLL_VCO_TEMP_CMP_OFFSET 0 - #define UNIPHY_PLL_VCO_RELATED_CONTROL_1_MIIREG_REG_UPHY_PLL_VCO_TEMP_CMP_LEN 6 - #define UNIPHY_PLL_VCO_RELATED_CONTROL_1_MIIREG_REG_UPHY_PLL_VCO_TEMP_CMP_DEFAULT 0x0 - /*[field] MIIREG_REG_UPHY_PLL_VCO_CALIB_READY*/ - #define UNIPHY_PLL_VCO_RELATED_CONTROL_1_MIIREG_REG_UPHY_PLL_VCO_CALIB_READY - #define UNIPHY_PLL_VCO_RELATED_CONTROL_1_MIIREG_REG_UPHY_PLL_VCO_CALIB_READY_OFFSET 6 - #define UNIPHY_PLL_VCO_RELATED_CONTROL_1_MIIREG_REG_UPHY_PLL_VCO_CALIB_READY_LEN 1 - #define UNIPHY_PLL_VCO_RELATED_CONTROL_1_MIIREG_REG_UPHY_PLL_VCO_CALIB_READY_DEFAULT 0x0 - /*[field] MIIREG_AUTOLOAD_SEL_PLL_VCO_CALIB_READY*/ - #define UNIPHY_PLL_VCO_RELATED_CONTROL_1_MIIREG_AUTOLOAD_SEL_PLL_VCO_CALIB_READY - #define UNIPHY_PLL_VCO_RELATED_CONTROL_1_MIIREG_AUTOLOAD_SEL_PLL_VCO_CALIB_READY_OFFSET 7 - #define UNIPHY_PLL_VCO_RELATED_CONTROL_1_MIIREG_AUTOLOAD_SEL_PLL_VCO_CALIB_READY_LEN 1 - #define UNIPHY_PLL_VCO_RELATED_CONTROL_1_MIIREG_AUTOLOAD_SEL_PLL_VCO_CALIB_READY_DEFAULT 0x0 - /*[field] MIIREG_REG_UPHY_PLL_VCO_AMP*/ - #define UNIPHY_PLL_VCO_RELATED_CONTROL_1_MIIREG_REG_UPHY_PLL_VCO_AMP - #define UNIPHY_PLL_VCO_RELATED_CONTROL_1_MIIREG_REG_UPHY_PLL_VCO_AMP_OFFSET 8 - #define UNIPHY_PLL_VCO_RELATED_CONTROL_1_MIIREG_REG_UPHY_PLL_VCO_AMP_LEN 4 - #define UNIPHY_PLL_VCO_RELATED_CONTROL_1_MIIREG_REG_UPHY_PLL_VCO_AMP_DEFAULT 0x0 - /*[field] MIIREG_REG_UPHY_PLL_VCO_GAIN*/ - #define UNIPHY_PLL_VCO_RELATED_CONTROL_1_MIIREG_REG_UPHY_PLL_VCO_GAIN - #define UNIPHY_PLL_VCO_RELATED_CONTROL_1_MIIREG_REG_UPHY_PLL_VCO_GAIN_OFFSET 12 - #define UNIPHY_PLL_VCO_RELATED_CONTROL_1_MIIREG_REG_UPHY_PLL_VCO_GAIN_LEN 3 - #define UNIPHY_PLL_VCO_RELATED_CONTROL_1_MIIREG_REG_UPHY_PLL_VCO_GAIN_DEFAULT 0x0 - /*[field] MIIREG_UPHY_PLL_LCKDT_EN*/ - #define UNIPHY_PLL_VCO_RELATED_CONTROL_1_MIIREG_UPHY_PLL_LCKDT_EN - #define UNIPHY_PLL_VCO_RELATED_CONTROL_1_MIIREG_UPHY_PLL_LCKDT_EN_OFFSET 15 - #define UNIPHY_PLL_VCO_RELATED_CONTROL_1_MIIREG_UPHY_PLL_LCKDT_EN_LEN 1 - #define UNIPHY_PLL_VCO_RELATED_CONTROL_1_MIIREG_UPHY_PLL_LCKDT_EN_DEFAULT 0x0 - -struct uniphy_pll_vco_related_control_1 { - a_uint32_t miireg_reg_uphy_pll_vco_temp_cmp:6; - a_uint32_t miireg_reg_uphy_pll_vco_calib_ready:1; - a_uint32_t miireg_autoload_sel_pll_vco_calib_ready:1; - a_uint32_t miireg_reg_uphy_pll_vco_amp:4; - a_uint32_t miireg_reg_uphy_pll_vco_gain:3; - a_uint32_t miireg_uphy_pll_lckdt_en:1; - a_uint32_t _reserved0:16; -}; - -union uniphy_pll_vco_related_control_1_u { - a_uint32_t val; - struct uniphy_pll_vco_related_control_1 bf; -}; - -/*[register] UNIPHY_RX_AFE_2*/ -#define UNIPHY_RX_AFE_2 -#define UNIPHY_RX_AFE_2_ADDRESS 0x7c4 -#define UNIPHY_RX_AFE_2_NUM 3 -#define UNIPHY_RX_AFE_2_INC 0x1 -#define UNIPHY_RX_AFE_2_TYPE REG_TYPE_RW -#define UNIPHY_RX_AFE_2_DEFAULT 0x0 - /*[field] MIIREG_REG_UPHY_RX_AFE_RES1*/ - #define UNIPHY_RX_AFE_2_MIIREG_REG_UPHY_RX_AFE_RES1 - #define UNIPHY_RX_AFE_2_MIIREG_REG_UPHY_RX_AFE_RES1_OFFSET 0 - #define UNIPHY_RX_AFE_2_MIIREG_REG_UPHY_RX_AFE_RES1_LEN 4 - #define UNIPHY_RX_AFE_2_MIIREG_REG_UPHY_RX_AFE_RES1_DEFAULT 0x0 - /*[field] MIIREG_REG_UPHY_RX_AFE_CAP1*/ - #define UNIPHY_RX_AFE_2_MIIREG_REG_UPHY_RX_AFE_CAP1 - #define UNIPHY_RX_AFE_2_MIIREG_REG_UPHY_RX_AFE_CAP1_OFFSET 4 - #define UNIPHY_RX_AFE_2_MIIREG_REG_UPHY_RX_AFE_CAP1_LEN 3 - #define UNIPHY_RX_AFE_2_MIIREG_REG_UPHY_RX_AFE_CAP1_DEFAULT 0x0 - /*[field] MIIREG_REG_UPHY_RX_RESCAL_CODE*/ - #define UNIPHY_RX_AFE_2_MIIREG_REG_UPHY_RX_RESCAL_CODE - #define UNIPHY_RX_AFE_2_MIIREG_REG_UPHY_RX_RESCAL_CODE_OFFSET 8 - #define UNIPHY_RX_AFE_2_MIIREG_REG_UPHY_RX_RESCAL_CODE_LEN 5 - #define UNIPHY_RX_AFE_2_MIIREG_REG_UPHY_RX_RESCAL_CODE_DEFAULT 0x0 - -struct uniphy_rx_afe_2 { - a_uint32_t miireg_reg_uphy_rx_afe_res1:4; - a_uint32_t miireg_reg_uphy_rx_afe_cap1:3; - a_uint32_t _reserved0:1; - a_uint32_t miireg_reg_uphy_rx_rescal_code:5; - a_uint32_t _reserved1:19; -}; - -union uniphy_rx_afe_2_u { - a_uint32_t val; - struct uniphy_rx_afe_2 bf; -}; - -/*[register] BANDGAP_IP_MBIAS_2*/ -#define BANDGAP_IP_MBIAS_2 -#define BANDGAP_IP_MBIAS_2_ADDRESS 0x9b004 -#define BANDGAP_IP_MBIAS_2_NUM 4 -#define BANDGAP_IP_MBIAS_2_INC 0x1 -#define BANDGAP_IP_MBIAS_2_TYPE REG_TYPE_RW -#define BANDGAP_IP_MBIAS_2_DEFAULT 0x0 - /*[field] CMN_MMD1_REG_CMN_BG_RSV*/ - #define BANDGAP_IP_MBIAS_2_CMN_MMD1_REG_CMN_BG_RSV - #define BANDGAP_IP_MBIAS_2_CMN_MMD1_REG_CMN_BG_RSV_OFFSET 0 - #define BANDGAP_IP_MBIAS_2_CMN_MMD1_REG_CMN_BG_RSV_LEN 8 - #define BANDGAP_IP_MBIAS_2_CMN_MMD1_REG_CMN_BG_RSV_DEFAULT 0x0 - /*[field] CMN_MMD1_REG_CMN_ICC_RESCODE*/ - #define BANDGAP_IP_MBIAS_2_CMN_MMD1_REG_CMN_ICC_RESCODE - #define BANDGAP_IP_MBIAS_2_CMN_MMD1_REG_CMN_ICC_RESCODE_OFFSET 8 - #define BANDGAP_IP_MBIAS_2_CMN_MMD1_REG_CMN_ICC_RESCODE_LEN 7 - #define BANDGAP_IP_MBIAS_2_CMN_MMD1_REG_CMN_ICC_RESCODE_DEFAULT 0x0 - /*[field] CMN_MMD1_REG_MBIAS_EN*/ - #define BANDGAP_IP_MBIAS_2_CMN_MMD1_REG_MBIAS_EN - #define BANDGAP_IP_MBIAS_2_CMN_MMD1_REG_MBIAS_EN_OFFSET 15 - #define BANDGAP_IP_MBIAS_2_CMN_MMD1_REG_MBIAS_EN_LEN 1 - #define BANDGAP_IP_MBIAS_2_CMN_MMD1_REG_MBIAS_EN_DEFAULT 0x0 - -struct bandgap_ip_mbias_2 { - a_uint32_t cmn_mmd1_reg_cmn_bg_rsv:8; - a_uint32_t cmn_mmd1_reg_cmn_icc_rescode:7; - a_uint32_t cmn_mmd1_reg_mbias_en:1; - a_uint32_t _reserved0:16; -}; - -union bandgap_ip_mbias_2_u { - a_uint32_t val; - struct bandgap_ip_mbias_2 bf; -}; - -/*[register] LDO_0P9V_RELATED_1*/ -#define LDO_0P9V_RELATED_1 -#define LDO_0P9V_RELATED_1_ADDRESS 0x9b054 -#define LDO_0P9V_RELATED_1_NUM 4 -#define LDO_0P9V_RELATED_1_INC 0x1 -#define LDO_0P9V_RELATED_1_TYPE REG_TYPE_RW -#define LDO_0P9V_RELATED_1_DEFAULT 0x0 - /*[field] CMN_MMD1_REG_CMN_LDO_INT_RES_CTRL*/ - #define LDO_0P9V_RELATED_1_CMN_MMD1_REG_CMN_LDO_INT_RES_CTRL - #define LDO_0P9V_RELATED_1_CMN_MMD1_REG_CMN_LDO_INT_RES_CTRL_OFFSET 0 - #define LDO_0P9V_RELATED_1_CMN_MMD1_REG_CMN_LDO_INT_RES_CTRL_LEN 2 - #define LDO_0P9V_RELATED_1_CMN_MMD1_REG_CMN_LDO_INT_RES_CTRL_DEFAULT 0x0 - /*[field] CMN_MMD1_REG_CMN_LDO_INT_LOAD_EN*/ - #define LDO_0P9V_RELATED_1_CMN_MMD1_REG_CMN_LDO_INT_LOAD_EN - #define LDO_0P9V_RELATED_1_CMN_MMD1_REG_CMN_LDO_INT_LOAD_EN_OFFSET 2 - #define LDO_0P9V_RELATED_1_CMN_MMD1_REG_CMN_LDO_INT_LOAD_EN_LEN 1 - #define LDO_0P9V_RELATED_1_CMN_MMD1_REG_CMN_LDO_INT_LOAD_EN_DEFAULT 0x0 - /*[field] CMN_MMD1_REG_CMN_LDO_OCP_CURRENT_SEL*/ - #define LDO_0P9V_RELATED_1_CMN_MMD1_REG_CMN_LDO_OCP_CURRENT_SEL - #define LDO_0P9V_RELATED_1_CMN_MMD1_REG_CMN_LDO_OCP_CURRENT_SEL_OFFSET 3 - #define LDO_0P9V_RELATED_1_CMN_MMD1_REG_CMN_LDO_OCP_CURRENT_SEL_LEN 1 - #define LDO_0P9V_RELATED_1_CMN_MMD1_REG_CMN_LDO_OCP_CURRENT_SEL_DEFAULT 0x0 - /*[field] CMN_MMD1_REG_CMN_LDO_OCP_EN*/ - #define LDO_0P9V_RELATED_1_CMN_MMD1_REG_CMN_LDO_OCP_EN - #define LDO_0P9V_RELATED_1_CMN_MMD1_REG_CMN_LDO_OCP_EN_OFFSET 4 - #define LDO_0P9V_RELATED_1_CMN_MMD1_REG_CMN_LDO_OCP_EN_LEN 1 - #define LDO_0P9V_RELATED_1_CMN_MMD1_REG_CMN_LDO_OCP_EN_DEFAULT 0x0 - /*[field] CMN_MMD1_REG_CMN_LDO_BIAS_CTRL*/ - #define LDO_0P9V_RELATED_1_CMN_MMD1_REG_CMN_LDO_BIAS_CTRL - #define LDO_0P9V_RELATED_1_CMN_MMD1_REG_CMN_LDO_BIAS_CTRL_OFFSET 5 - #define LDO_0P9V_RELATED_1_CMN_MMD1_REG_CMN_LDO_BIAS_CTRL_LEN 2 - #define LDO_0P9V_RELATED_1_CMN_MMD1_REG_CMN_LDO_BIAS_CTRL_DEFAULT 0x0 - /*[field] CMN_MMD1_REG_CMN_LDO_VOUT_CTRL*/ - #define LDO_0P9V_RELATED_1_CMN_MMD1_REG_CMN_LDO_VOUT_CTRL - #define LDO_0P9V_RELATED_1_CMN_MMD1_REG_CMN_LDO_VOUT_CTRL_OFFSET 7 - #define LDO_0P9V_RELATED_1_CMN_MMD1_REG_CMN_LDO_VOUT_CTRL_LEN 4 - #define LDO_0P9V_RELATED_1_CMN_MMD1_REG_CMN_LDO_VOUT_CTRL_DEFAULT 0x0 - /*[field] CMN_MMD1_REG_CMN_LDO_EN*/ - #define LDO_0P9V_RELATED_1_CMN_MMD1_REG_CMN_LDO_EN - #define LDO_0P9V_RELATED_1_CMN_MMD1_REG_CMN_LDO_EN_OFFSET 11 - #define LDO_0P9V_RELATED_1_CMN_MMD1_REG_CMN_LDO_EN_LEN 1 - #define LDO_0P9V_RELATED_1_CMN_MMD1_REG_CMN_LDO_EN_DEFAULT 0x0 - /*[field] CMN_MMD1_REG_CMN_LDO_COMP_CURRENT_EN*/ - #define LDO_0P9V_RELATED_1_CMN_MMD1_REG_CMN_LDO_COMP_CURRENT_EN - #define LDO_0P9V_RELATED_1_CMN_MMD1_REG_CMN_LDO_COMP_CURRENT_EN_OFFSET 12 - #define LDO_0P9V_RELATED_1_CMN_MMD1_REG_CMN_LDO_COMP_CURRENT_EN_LEN 1 - #define LDO_0P9V_RELATED_1_CMN_MMD1_REG_CMN_LDO_COMP_CURRENT_EN_DEFAULT 0x0 - /*[field] CMN_MMD1_REG_CMN_VTT_LDO_BIASGEN_SEL*/ - #define LDO_0P9V_RELATED_1_CMN_MMD1_REG_CMN_VTT_LDO_BIASGEN_SEL - #define LDO_0P9V_RELATED_1_CMN_MMD1_REG_CMN_VTT_LDO_BIASGEN_SEL_OFFSET 13 - #define LDO_0P9V_RELATED_1_CMN_MMD1_REG_CMN_VTT_LDO_BIASGEN_SEL_LEN 3 - #define LDO_0P9V_RELATED_1_CMN_MMD1_REG_CMN_VTT_LDO_BIASGEN_SEL_DEFAULT 0x0 - -struct ldo_0p9v_related_1 { - a_uint32_t cmn_mmd1_reg_cmn_ldo_int_res_ctrl:2; - a_uint32_t cmn_mmd1_reg_cmn_ldo_int_load_en:1; - a_uint32_t cmn_mmd1_reg_cmn_ldo_ocp_current_sel:1; - a_uint32_t cmn_mmd1_reg_cmn_ldo_ocp_en:1; - a_uint32_t cmn_mmd1_reg_cmn_ldo_bias_ctrl:2; - a_uint32_t cmn_mmd1_reg_cmn_ldo_vout_ctrl:4; - a_uint32_t cmn_mmd1_reg_cmn_ldo_en:1; - a_uint32_t cmn_mmd1_reg_cmn_ldo_comp_current_en:1; - a_uint32_t cmn_mmd1_reg_cmn_vtt_ldo_biasgen_sel:3; - a_uint32_t _reserved0:16; -}; - -union ldo_0p9v_related_1_u { - a_uint32_t val; - struct ldo_0p9v_related_1 bf; -}; - -/*[register] OTP_VTT_LDO_RELATED*/ -#define OTP_VTT_LDO_RELATED -#define OTP_VTT_LDO_RELATED_ADDRESS 0x9b05c -#define OTP_VTT_LDO_RELATED_NUM 4 -#define OTP_VTT_LDO_RELATED_INC 0x1 -#define OTP_VTT_LDO_RELATED_TYPE REG_TYPE_RW -#define OTP_VTT_LDO_RELATED_DEFAULT 0x0 - /*[field] CMN_MMD1_REG_CMN_VTT_LDO_RSV*/ - #define OTP_VTT_LDO_RELATED_CMN_MMD1_REG_CMN_VTT_LDO_RSV - #define OTP_VTT_LDO_RELATED_CMN_MMD1_REG_CMN_VTT_LDO_RSV_OFFSET 0 - #define OTP_VTT_LDO_RELATED_CMN_MMD1_REG_CMN_VTT_LDO_RSV_LEN 8 - #define OTP_VTT_LDO_RELATED_CMN_MMD1_REG_CMN_VTT_LDO_RSV_DEFAULT 0x0 - /*[field] CMN_MMD1_REG_CMN_VTT_LDO_INT_LOAD_CTRL*/ - #define OTP_VTT_LDO_RELATED_CMN_MMD1_REG_CMN_VTT_LDO_INT_LOAD_CTRL - #define OTP_VTT_LDO_RELATED_CMN_MMD1_REG_CMN_VTT_LDO_INT_LOAD_CTRL_OFFSET 8 - #define OTP_VTT_LDO_RELATED_CMN_MMD1_REG_CMN_VTT_LDO_INT_LOAD_CTRL_LEN 2 - #define OTP_VTT_LDO_RELATED_CMN_MMD1_REG_CMN_VTT_LDO_INT_LOAD_CTRL_DEFAULT 0x0 - /*[field] CMN_MMD1_REG_CMN_VTT_LDO_OCP_CURRENT_SEL*/ - #define OTP_VTT_LDO_RELATED_CMN_MMD1_REG_CMN_VTT_LDO_OCP_CURRENT_SEL - #define OTP_VTT_LDO_RELATED_CMN_MMD1_REG_CMN_VTT_LDO_OCP_CURRENT_SEL_OFFSET 10 - #define OTP_VTT_LDO_RELATED_CMN_MMD1_REG_CMN_VTT_LDO_OCP_CURRENT_SEL_LEN 1 - #define OTP_VTT_LDO_RELATED_CMN_MMD1_REG_CMN_VTT_LDO_OCP_CURRENT_SEL_DEFAULT 0x0 - /*[field] CMN_MMD1_REG_CMN_VTT_LDO_OCP_EN*/ - #define OTP_VTT_LDO_RELATED_CMN_MMD1_REG_CMN_VTT_LDO_OCP_EN - #define OTP_VTT_LDO_RELATED_CMN_MMD1_REG_CMN_VTT_LDO_OCP_EN_OFFSET 11 - #define OTP_VTT_LDO_RELATED_CMN_MMD1_REG_CMN_VTT_LDO_OCP_EN_LEN 1 - #define OTP_VTT_LDO_RELATED_CMN_MMD1_REG_CMN_VTT_LDO_OCP_EN_DEFAULT 0x0 - /*[field] CMN_MMD1_REG_CMN_VTT_LDO_BIAS_CTRL*/ - #define OTP_VTT_LDO_RELATED_CMN_MMD1_REG_CMN_VTT_LDO_BIAS_CTRL - #define OTP_VTT_LDO_RELATED_CMN_MMD1_REG_CMN_VTT_LDO_BIAS_CTRL_OFFSET 12 - #define OTP_VTT_LDO_RELATED_CMN_MMD1_REG_CMN_VTT_LDO_BIAS_CTRL_LEN 2 - #define OTP_VTT_LDO_RELATED_CMN_MMD1_REG_CMN_VTT_LDO_BIAS_CTRL_DEFAULT 0x0 - /*[field] CMN_MMD1_REG_CMN_VTT_LDO_EN*/ - #define OTP_VTT_LDO_RELATED_CMN_MMD1_REG_CMN_VTT_LDO_EN - #define OTP_VTT_LDO_RELATED_CMN_MMD1_REG_CMN_VTT_LDO_EN_OFFSET 14 - #define OTP_VTT_LDO_RELATED_CMN_MMD1_REG_CMN_VTT_LDO_EN_LEN 1 - #define OTP_VTT_LDO_RELATED_CMN_MMD1_REG_CMN_VTT_LDO_EN_DEFAULT 0x0 - /*[field] CMN_MMD1_REG_CMN_ANA_ISOLATION*/ - #define OTP_VTT_LDO_RELATED_CMN_MMD1_REG_CMN_ANA_ISOLATION - #define OTP_VTT_LDO_RELATED_CMN_MMD1_REG_CMN_ANA_ISOLATION_OFFSET 15 - #define OTP_VTT_LDO_RELATED_CMN_MMD1_REG_CMN_ANA_ISOLATION_LEN 1 - #define OTP_VTT_LDO_RELATED_CMN_MMD1_REG_CMN_ANA_ISOLATION_DEFAULT 0x0 - -struct otp_vtt_ldo_related { - a_uint32_t cmn_mmd1_reg_cmn_vtt_ldo_rsv:8; - a_uint32_t cmn_mmd1_reg_cmn_vtt_ldo_int_load_ctrl:2; - a_uint32_t cmn_mmd1_reg_cmn_vtt_ldo_ocp_current_sel:1; - a_uint32_t cmn_mmd1_reg_cmn_vtt_ldo_ocp_en:1; - a_uint32_t cmn_mmd1_reg_cmn_vtt_ldo_bias_ctrl:2; - a_uint32_t cmn_mmd1_reg_cmn_vtt_ldo_en:1; - a_uint32_t cmn_mmd1_reg_cmn_ana_isolation:1; - a_uint32_t _reserved0:16; -}; - -union otp_vtt_ldo_related_u { - a_uint32_t val; - struct otp_vtt_ldo_related bf; -}; - -/*[register] OTP_TEMPERATURE_COMPENSATE_1*/ -#define OTP_TEMPERATURE_COMPENSATE_1 -#define OTP_TEMPERATURE_COMPENSATE_1_ADDRESS 0x9b08c -#define OTP_TEMPERATURE_COMPENSATE_1_NUM 4 -#define OTP_TEMPERATURE_COMPENSATE_1_INC 0x1 -#define OTP_TEMPERATURE_COMPENSATE_1_TYPE REG_TYPE_RW -#define OTP_TEMPERATURE_COMPENSATE_1_DEFAULT 0x0 - /*[field] CMN_MMD1_REG_UPHY_ICTAT100U_CTRL0*/ - #define OTP_TEMPERATURE_COMPENSATE_1_CMN_MMD1_REG_UPHY_ICTAT100U_CTRL0 - #define OTP_TEMPERATURE_COMPENSATE_1_CMN_MMD1_REG_UPHY_ICTAT100U_CTRL0_OFFSET 0 - #define OTP_TEMPERATURE_COMPENSATE_1_CMN_MMD1_REG_UPHY_ICTAT100U_CTRL0_LEN 3 - #define OTP_TEMPERATURE_COMPENSATE_1_CMN_MMD1_REG_UPHY_ICTAT100U_CTRL0_DEFAULT 0x0 - /*[field] CMN_MMD1_REG_UPHY_ICTAT100U_CTRL1*/ - #define OTP_TEMPERATURE_COMPENSATE_1_CMN_MMD1_REG_UPHY_ICTAT100U_CTRL1 - #define OTP_TEMPERATURE_COMPENSATE_1_CMN_MMD1_REG_UPHY_ICTAT100U_CTRL1_OFFSET 4 - #define OTP_TEMPERATURE_COMPENSATE_1_CMN_MMD1_REG_UPHY_ICTAT100U_CTRL1_LEN 3 - #define OTP_TEMPERATURE_COMPENSATE_1_CMN_MMD1_REG_UPHY_ICTAT100U_CTRL1_DEFAULT 0x0 - /*[field] CMN_MMD1_REG_UPHY_ICTAT100U_CTRL2*/ - #define OTP_TEMPERATURE_COMPENSATE_1_CMN_MMD1_REG_UPHY_ICTAT100U_CTRL2 - #define OTP_TEMPERATURE_COMPENSATE_1_CMN_MMD1_REG_UPHY_ICTAT100U_CTRL2_OFFSET 8 - #define OTP_TEMPERATURE_COMPENSATE_1_CMN_MMD1_REG_UPHY_ICTAT100U_CTRL2_LEN 3 - #define OTP_TEMPERATURE_COMPENSATE_1_CMN_MMD1_REG_UPHY_ICTAT100U_CTRL2_DEFAULT 0x0 - /*[field] CMN_MMD1_REG_UPHY_ICTAT100U_EN*/ - #define OTP_TEMPERATURE_COMPENSATE_1_CMN_MMD1_REG_UPHY_ICTAT100U_EN - #define OTP_TEMPERATURE_COMPENSATE_1_CMN_MMD1_REG_UPHY_ICTAT100U_EN_OFFSET 12 - #define OTP_TEMPERATURE_COMPENSATE_1_CMN_MMD1_REG_UPHY_ICTAT100U_EN_LEN 3 - #define OTP_TEMPERATURE_COMPENSATE_1_CMN_MMD1_REG_UPHY_ICTAT100U_EN_DEFAULT 0x0 - /*[field] CMN_MMD1_REG_CMN_PLL_ICTAT100U_EN*/ - #define OTP_TEMPERATURE_COMPENSATE_1_CMN_MMD1_REG_CMN_PLL_ICTAT100U_EN - #define OTP_TEMPERATURE_COMPENSATE_1_CMN_MMD1_REG_CMN_PLL_ICTAT100U_EN_OFFSET 15 - #define OTP_TEMPERATURE_COMPENSATE_1_CMN_MMD1_REG_CMN_PLL_ICTAT100U_EN_LEN 1 - #define OTP_TEMPERATURE_COMPENSATE_1_CMN_MMD1_REG_CMN_PLL_ICTAT100U_EN_DEFAULT 0x0 - -struct otp_temperature_compensate_1 { - a_uint32_t cmn_mmd1_reg_uphy_ictat100u_ctrl0:3; - a_uint32_t _reserved0:1; - a_uint32_t cmn_mmd1_reg_uphy_ictat100u_ctrl1:3; - a_uint32_t _reserved1:1; - a_uint32_t cmn_mmd1_reg_uphy_ictat100u_ctrl2:3; - a_uint32_t _reserved2:1; - a_uint32_t cmn_mmd1_reg_uphy_ictat100u_en:3; - a_uint32_t cmn_mmd1_reg_cmn_pll_ictat100u_en:1; - a_uint32_t _reserved3:16; -}; - -union otp_temperature_compensate_1_u { - a_uint32_t val; - struct otp_temperature_compensate_1 bf; -}; - -/*[register] PLL_VCO_RELATED_CONTROL_1*/ -#define PLL_VCO_RELATED_CONTROL_1 -#define PLL_VCO_RELATED_CONTROL_1_ADDRESS 0x9b78c -#define PLL_VCO_RELATED_CONTROL_1_NUM 4 -#define PLL_VCO_RELATED_CONTROL_1_INC 0x1 -#define PLL_VCO_RELATED_CONTROL_1_TYPE REG_TYPE_RW -#define PLL_VCO_RELATED_CONTROL_1_DEFAULT 0x0 - /*[field] CMN_MII_REG_REG_CMN_PLL_VCO_TEMP_CMP*/ - #define PLL_VCO_RELATED_CONTROL_1_CMN_MII_REG_REG_CMN_PLL_VCO_TEMP_CMP - #define PLL_VCO_RELATED_CONTROL_1_CMN_MII_REG_REG_CMN_PLL_VCO_TEMP_CMP_OFFSET 0 - #define PLL_VCO_RELATED_CONTROL_1_CMN_MII_REG_REG_CMN_PLL_VCO_TEMP_CMP_LEN 6 - #define PLL_VCO_RELATED_CONTROL_1_CMN_MII_REG_REG_CMN_PLL_VCO_TEMP_CMP_DEFAULT 0x0 - /*[field] CMN_MII_REG_REG_CMN_PLL_VCO_CALIB_READY*/ - #define PLL_VCO_RELATED_CONTROL_1_CMN_MII_REG_REG_CMN_PLL_VCO_CALIB_READY - #define PLL_VCO_RELATED_CONTROL_1_CMN_MII_REG_REG_CMN_PLL_VCO_CALIB_READY_OFFSET 6 - #define PLL_VCO_RELATED_CONTROL_1_CMN_MII_REG_REG_CMN_PLL_VCO_CALIB_READY_LEN 1 - #define PLL_VCO_RELATED_CONTROL_1_CMN_MII_REG_REG_CMN_PLL_VCO_CALIB_READY_DEFAULT 0x0 - /*[field] CMN_MII_REG_AUTOLOAD_SEL_PLL_VCO_CALIB_READY*/ - #define PLL_VCO_RELATED_CONTROL_1_CMN_MII_REG_AUTOLOAD_SEL_PLL_VCO_CALIB_READY - #define PLL_VCO_RELATED_CONTROL_1_CMN_MII_REG_AUTOLOAD_SEL_PLL_VCO_CALIB_READY_OFFSET 7 - #define PLL_VCO_RELATED_CONTROL_1_CMN_MII_REG_AUTOLOAD_SEL_PLL_VCO_CALIB_READY_LEN 1 - #define PLL_VCO_RELATED_CONTROL_1_CMN_MII_REG_AUTOLOAD_SEL_PLL_VCO_CALIB_READY_DEFAULT 0x0 - /*[field] CMN_MII_REG_REG_CMN_PLL_VCO_AMP*/ - #define PLL_VCO_RELATED_CONTROL_1_CMN_MII_REG_REG_CMN_PLL_VCO_AMP - #define PLL_VCO_RELATED_CONTROL_1_CMN_MII_REG_REG_CMN_PLL_VCO_AMP_OFFSET 8 - #define PLL_VCO_RELATED_CONTROL_1_CMN_MII_REG_REG_CMN_PLL_VCO_AMP_LEN 4 - #define PLL_VCO_RELATED_CONTROL_1_CMN_MII_REG_REG_CMN_PLL_VCO_AMP_DEFAULT 0x0 - /*[field] CMN_MII_REG_CMN_PLL_LCKDT_EN*/ - #define PLL_VCO_RELATED_CONTROL_1_CMN_MII_REG_CMN_PLL_LCKDT_EN - #define PLL_VCO_RELATED_CONTROL_1_CMN_MII_REG_CMN_PLL_LCKDT_EN_OFFSET 15 - #define PLL_VCO_RELATED_CONTROL_1_CMN_MII_REG_CMN_PLL_LCKDT_EN_LEN 1 - #define PLL_VCO_RELATED_CONTROL_1_CMN_MII_REG_CMN_PLL_LCKDT_EN_DEFAULT 0x0 - -struct pll_vco_related_control_1 { - a_uint32_t cmn_mii_reg_reg_cmn_pll_vco_temp_cmp:6; - a_uint32_t cmn_mii_reg_reg_cmn_pll_vco_calib_ready:1; - a_uint32_t cmn_mii_reg_autoload_sel_pll_vco_calib_ready:1; - a_uint32_t cmn_mii_reg_reg_cmn_pll_vco_amp:4; - a_uint32_t _reserved0:3; - a_uint32_t cmn_mii_reg_cmn_pll_lckdt_en:1; - a_uint32_t _reserved1:16; -}; - -union pll_vco_related_control_1_u { - a_uint32_t val; - struct pll_vco_related_control_1 bf; -}; - -/*[register] PLL_CONTROL_VCO_RELATED_SELECTION_2*/ -#define PLL_CONTROL_VCO_RELATED_SELECTION_2 -#define PLL_CONTROL_VCO_RELATED_SELECTION_2_ADDRESS 0x9b02c -#define PLL_CONTROL_VCO_RELATED_SELECTION_2_NUM 4 -#define PLL_CONTROL_VCO_RELATED_SELECTION_2_INC 0x1 -#define PLL_CONTROL_VCO_RELATED_SELECTION_2_TYPE REG_TYPE_RW -#define PLL_CONTROL_VCO_RELATED_SELECTION_2_DEFAULT 0x0 - /*[field] CMN_MMD1_REG_SRC_CMN_PLL_VCO_TEMP_CMP*/ - #define PLL_CONTROL_VCO_RELATED_SELECTION_2_CMN_MMD1_REG_SRC_CMN_PLL_VCO_TEMP_CMP - #define PLL_CONTROL_VCO_RELATED_SELECTION_2_CMN_MMD1_REG_SRC_CMN_PLL_VCO_TEMP_CMP_OFFSET 0 - #define PLL_CONTROL_VCO_RELATED_SELECTION_2_CMN_MMD1_REG_SRC_CMN_PLL_VCO_TEMP_CMP_LEN 2 - #define PLL_CONTROL_VCO_RELATED_SELECTION_2_CMN_MMD1_REG_SRC_CMN_PLL_VCO_TEMP_CMP_DEFAULT 0x0 - /*[field] CMN_MMD1_REG_SRC_CMN_PLL_VCO_AMP*/ - #define PLL_CONTROL_VCO_RELATED_SELECTION_2_CMN_MMD1_REG_SRC_CMN_PLL_VCO_AMP - #define PLL_CONTROL_VCO_RELATED_SELECTION_2_CMN_MMD1_REG_SRC_CMN_PLL_VCO_AMP_OFFSET 2 - #define PLL_CONTROL_VCO_RELATED_SELECTION_2_CMN_MMD1_REG_SRC_CMN_PLL_VCO_AMP_LEN 2 - #define PLL_CONTROL_VCO_RELATED_SELECTION_2_CMN_MMD1_REG_SRC_CMN_PLL_VCO_AMP_DEFAULT 0x0 - /*[field] CMN_MMD1_REG_SRC_CMN_PLL_FBCLK_DIV*/ - #define PLL_CONTROL_VCO_RELATED_SELECTION_2_CMN_MMD1_REG_SRC_CMN_PLL_FBCLK_DIV - #define PLL_CONTROL_VCO_RELATED_SELECTION_2_CMN_MMD1_REG_SRC_CMN_PLL_FBCLK_DIV_OFFSET 4 - #define PLL_CONTROL_VCO_RELATED_SELECTION_2_CMN_MMD1_REG_SRC_CMN_PLL_FBCLK_DIV_LEN 2 - #define PLL_CONTROL_VCO_RELATED_SELECTION_2_CMN_MMD1_REG_SRC_CMN_PLL_FBCLK_DIV_DEFAULT 0x0 - /*[field] CMN_MMD1_REG_SRC_CMN_PLL_VCO_CALIB_READY*/ - #define PLL_CONTROL_VCO_RELATED_SELECTION_2_CMN_MMD1_REG_SRC_CMN_PLL_VCO_CALIB_READY - #define PLL_CONTROL_VCO_RELATED_SELECTION_2_CMN_MMD1_REG_SRC_CMN_PLL_VCO_CALIB_READY_OFFSET 6 - #define PLL_CONTROL_VCO_RELATED_SELECTION_2_CMN_MMD1_REG_SRC_CMN_PLL_VCO_CALIB_READY_LEN 2 - #define PLL_CONTROL_VCO_RELATED_SELECTION_2_CMN_MMD1_REG_SRC_CMN_PLL_VCO_CALIB_READY_DEFAULT 0x0 - /*[field] CMN_MMD1_REG_SRC_CMN_PLL_VCO_CALIB_CODE*/ - #define PLL_CONTROL_VCO_RELATED_SELECTION_2_CMN_MMD1_REG_SRC_CMN_PLL_VCO_CALIB_CODE - #define PLL_CONTROL_VCO_RELATED_SELECTION_2_CMN_MMD1_REG_SRC_CMN_PLL_VCO_CALIB_CODE_OFFSET 8 - #define PLL_CONTROL_VCO_RELATED_SELECTION_2_CMN_MMD1_REG_SRC_CMN_PLL_VCO_CALIB_CODE_LEN 2 - #define PLL_CONTROL_VCO_RELATED_SELECTION_2_CMN_MMD1_REG_SRC_CMN_PLL_VCO_CALIB_CODE_DEFAULT 0x0 - /*[field] CMN_MMD1_REG_SRC_CMN_PLL_VCO_CALIB_START*/ - #define PLL_CONTROL_VCO_RELATED_SELECTION_2_CMN_MMD1_REG_SRC_CMN_PLL_VCO_CALIB_START - #define PLL_CONTROL_VCO_RELATED_SELECTION_2_CMN_MMD1_REG_SRC_CMN_PLL_VCO_CALIB_START_OFFSET 10 - #define PLL_CONTROL_VCO_RELATED_SELECTION_2_CMN_MMD1_REG_SRC_CMN_PLL_VCO_CALIB_START_LEN 2 - #define PLL_CONTROL_VCO_RELATED_SELECTION_2_CMN_MMD1_REG_SRC_CMN_PLL_VCO_CALIB_START_DEFAULT 0x0 - -struct pll_control_vco_related_selection_2 { - a_uint32_t cmn_mmd1_reg_src_cmn_pll_vco_temp_cmp:2; - a_uint32_t cmn_mmd1_reg_src_cmn_pll_vco_amp:2; - a_uint32_t cmn_mmd1_reg_src_cmn_pll_fbclk_div:2; - a_uint32_t cmn_mmd1_reg_src_cmn_pll_vco_calib_ready:2; - a_uint32_t cmn_mmd1_reg_src_cmn_pll_vco_calib_code:2; - a_uint32_t cmn_mmd1_reg_src_cmn_pll_vco_calib_start:2; - a_uint32_t _reserved0:20; -}; - -union pll_control_vco_related_selection_2_u { - a_uint32_t val; - struct pll_control_vco_related_selection_2 bf; -}; - -/*[register] PLL_POWER_ON_AND_RESET*/ -#define PLL_POWER_ON_AND_RESET -#define PLL_POWER_ON_AND_RESET_ADDRESS 0x780 -#define PLL_POWER_ON_AND_RESET_NUM 4 -#define PLL_POWER_ON_AND_RESET_INC 0x1 -#define PLL_POWER_ON_AND_RESET_TYPE REG_TYPE_RW -#define PLL_POWER_ON_AND_RESET_DEFAULT 0x2ff - /*[field] MIIREG_UPHY_PLL_RSTN*/ - #define MIIREG_UPHY_PLL_RSTN_MIIREG_UPHY_PLL_RSTN - #define MIIREG_UPHY_PLL_RSTN_MIIREG_UPHY_PLL_RSTN_OFFSET 0 - #define MIIREG_UPHY_PLL_RSTN_MIIREG_UPHY_PLL_RSTN_LEN 1 - #define MIIREG_UPHY_PLL_RSTN_MIIREG_UPHY_PLL_RSTN_DEFAULT 0x1 - /*[field] MIIREG_REG_UPHY_PLL_EN*/ - #define PLL_POWER_ON_AND_RESET_MIIREG_REG_UPHY_PLL_EN - #define PLL_POWER_ON_AND_RESET_MIIREG_REG_UPHY_PLL_EN_OFFSET 1 - #define PLL_POWER_ON_AND_RESET_MIIREG_REG_UPHY_PLL_EN_LEN 1 - #define PLL_POWER_ON_AND_RESET_MIIREG_REG_UPHY_PLL_EN_DEFAULT 0x1 - /*[field] MIIREG_UPHY_RXCLK_SW_RSTN*/ - #define PLL_POWER_ON_AND_RESET_MIIREG_UPHY_RXCLK_SW_RSTN - #define PLL_POWER_ON_AND_RESET_MIIREG_UPHY_RXCLK_SW_RSTN_OFFSET 2 - #define PLL_POWER_ON_AND_RESET_MIIREG_UPHY_RXCLK_SW_RSTN_LEN 1 - #define PLL_POWER_ON_AND_RESET_MIIREG_UPHY_RXCLK_SW_RSTN_DEFAULT 0x1 - /*[field] MIIREG_UPHY_RXCLK_FLOOP_SW_RSTN*/ - #define PLL_POWER_ON_AND_RESET_MIIREG_UPHY_RXCLK_FLOOP_SW_RSTN - #define PLL_POWER_ON_AND_RESET_MIIREG_UPHY_RXCLK_FLOOP_SW_RSTN_OFFSET 3 - #define PLL_POWER_ON_AND_RESET_MIIREG_UPHY_RXCLK_FLOOP_SW_RSTN_LEN 1 - #define PLL_POWER_ON_AND_RESET_MIIREG_UPHY_RXCLK_FLOOP_SW_RSTN_DEFAULT 0x1 - /*[field] MIIREG_UPHY_TXCLK_SW_RSTN*/ - #define PLL_POWER_ON_AND_RESET_MIIREG_UPHY_TXCLK_SW_RSTN - #define PLL_POWER_ON_AND_RESET_MIIREG_UPHY_TXCLK_SW_RSTN_OFFSET 4 - #define PLL_POWER_ON_AND_RESET_MIIREG_UPHY_TXCLK_SW_RSTN_LEN 1 - #define PLL_POWER_ON_AND_RESET_MIIREG_UPHY_TXCLK_SW_RSTN_DEFAULT 0x0 - /*[field] MIIREG_UPHY_SSC_CTRL_CLK_SW_RSTN*/ - #define PLL_POWER_ON_AND_RESET_MIIREG_UPHY_SSC_CTRL_CLK_SW_RSTN - #define PLL_POWER_ON_AND_RESET_MIIREG_UPHY_SSC_CTRL_CLK_SW_RSTN_OFFSET 5 - #define PLL_POWER_ON_AND_RESET_MIIREG_UPHY_SSC_CTRL_CLK_SW_RSTN_LEN 1 - #define PLL_POWER_ON_AND_RESET_MIIREG_UPHY_SSC_CTRL_CLK_SW_RSTN_DEFAULT 0x0 - /*[field] MIIREG_UPHY_ANA_EN_SW_RSTN*/ - #define PLL_POWER_ON_AND_RESET_MIIREG_UPHY_ANA_EN_SW_RSTN - #define PLL_POWER_ON_AND_RESET_MIIREG_UPHY_ANA_EN_SW_RSTN_OFFSET 6 - #define PLL_POWER_ON_AND_RESET_MIIREG_UPHY_ANA_EN_SW_RSTN_LEN 1 - #define PLL_POWER_ON_AND_RESET_MIIREG_UPHY_ANA_EN_SW_RSTN_DEFAULT 0x0 - /*[field] MIIREG_UPHY_PLL_MMDIV_RSTN*/ - #define PLL_POWER_ON_AND_RESET_MIIREG_UPHY_PLL_MMDIV_RSTN - #define PLL_POWER_ON_AND_RESET_MIIREG_UPHY_PLL_MMDIV_RSTN_OFFSET 7 - #define PLL_POWER_ON_AND_RESET_MIIREG_UPHY_PLL_MMDIV_RSTN_LEN 1 - #define PLL_POWER_ON_AND_RESET_MIIREG_UPHY_PLL_MMDIV_RSTN_DEFAULT 0x0 - /*[field] MIIREG_UPHY_CMN_12GPLL_ISOLATION*/ - #define PLL_POWER_ON_AND_RESET_MIIREG_UPHY_CMN_12GPLL_ISOLATION - #define PLL_POWER_ON_AND_RESET_MIIREG_UPHY_CMN_12GPLL_ISOLATION_OFFSET 8 - #define PLL_POWER_ON_AND_RESET_MIIREG_UPHY_CMN_12GPLL_ISOLATION_LEN 1 - #define PLL_POWER_ON_AND_RESET_MIIREG_UPHY_CMN_12GPLL_ISOLATION_DEFAULT 0x0 - /*[field] MIIREG_UPHY_PCS_SW_RSTN*/ - #define PLL_POWER_ON_AND_RESET_MIIREG_UPHY_PCS_SW_RSTN - #define PLL_POWER_ON_AND_RESET_MIIREG_UPHY_PCS_SW_RSTN_OFFSET 9 - #define PLL_POWER_ON_AND_RESET_MIIREG_UPHY_PCS_SW_RSTN_LEN 1 - #define PLL_POWER_ON_AND_RESET_MIIREG_UPHY_PCS_SW_RSTN_DEFAULT 0x0 - -struct pll_power_on_and_reset { - a_uint32_t pll_reset:1; - a_uint32_t pll_power_on:1; - a_uint32_t software_reset_rxclk:1; - a_uint32_t software_reset_rxclk_floop:1; - a_uint32_t software_reset_txclk:1; - a_uint32_t software_reset_ctrlclk:1; - a_uint32_t software_reset_analog_reset:1; - a_uint32_t reference_clock_reset:1; - a_uint32_t cmn_12gpll_isolation:1; - a_uint32_t pqsgmii_pcs_reset:1; - a_uint32_t _reserved0:22; -}; - -union pll_power_on_and_reset_u { - a_uint32_t val; - struct pll_power_on_and_reset bf; -}; - -/*[register] UNIPHY_MISC2_PHY_MODE*/ -#define UNIPHY_MISC2_PHY_MODE -#define UNIPHY_MISC2_PHY_MODE_ADDRESS 0x218 -#define UNIPHY_MISC2_PHY_MODE_NUM 4 -#define UNIPHY_MISC2_PHY_MODE_INC 0x1 -#define UNIPHY_MISC2_PHY_MODE_TYPE REG_TYPE_RW -#define UNIPHY_MISC2_PHY_MODE_DEFAULT 0x0 - /*[field] MMD1_REG_REG_RATE*/ - #define UNIPHY_MISC2_PHY_MODE_MMD1_REG_REG_RATE - #define UNIPHY_MISC2_PHY_MODE_MMD1_REG_REG_RATE_OFFSET 0 - #define UNIPHY_MISC2_PHY_MODE_MMD1_REG_REG_RATE_LEN 2 - #define UNIPHY_MISC2_PHY_MODE_MMD1_REG_REG_RATE_DEFAULT 0x1 - /*[field] MMD1_REG_REG_PHY_MODE*/ - #define UNIPHY_MISC2_PHY_MODE_MMD1_REG_REG_PHY_MODE - #define UNIPHY_MISC2_PHY_MODE_MMD1_REG_REG_PHY_MODE_OFFSET 4 - #define UNIPHY_MISC2_PHY_MODE_MMD1_REG_REG_PHY_MODE_LEN 3 - #define UNIPHY_MISC2_PHY_MODE_MMD1_REG_REG_PHY_MODE_DEFAULT 0x1 - - -struct uniphy_misc2_phy_mode { - a_uint32_t phy_rate:2; - a_uint32_t _reserved0:2; - a_uint32_t phy_mode:3; - a_uint32_t _reserved1:25; -}; - -union uniphy_misc2_phy_mode_u { - a_uint32_t val; - struct uniphy_misc2_phy_mode bf; -}; - -#endif diff --git a/feeds/ipq807x/qca-ssdk/src/include/hsl/hppe/hppe_vsi.h b/feeds/ipq807x/qca-ssdk/src/include/hsl/hppe/hppe_vsi.h deleted file mode 100755 index b8f9b5fbb..000000000 --- a/feeds/ipq807x/qca-ssdk/src/include/hsl/hppe/hppe_vsi.h +++ /dev/null @@ -1,270 +0,0 @@ -/* - * Copyright (c) 2016-2017, The Linux Foundation. All rights reserved. - * Permission to use, copy, modify, and/or distribute this software for - * any purpose with or without fee is hereby granted, provided that the - * above copyright notice and this permission notice appear in all copies. - * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES - * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR - * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES - * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN - * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT - * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. - */ - - -/** - * @defgroup - * @{ - */ -#ifndef _HPPE_VSI_H_ -#define _HPPE_VSI_H_ - -#define VSI_TBL_MAX_ENTRY 32 -#define VLAN_CNT_TBL_MAX_ENTRY 32 -#define EG_VSI_COUNTER_TBL_MAX_ENTRY 32 -#define PRE_L2_CNT_TBL_MAX_ENTRY 32 - -sw_error_t -hppe_vsi_tbl_get( - a_uint32_t dev_id, - a_uint32_t index, - union vsi_tbl_u *value); - -sw_error_t -hppe_vsi_tbl_set( - a_uint32_t dev_id, - a_uint32_t index, - union vsi_tbl_u *value); - -sw_error_t -hppe_vsi_tbl_umc_bitmap_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_vsi_tbl_umc_bitmap_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_vsi_tbl_station_move_lrn_en_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_vsi_tbl_station_move_lrn_en_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_vsi_tbl_new_addr_fwd_cmd_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_vsi_tbl_new_addr_fwd_cmd_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_vsi_tbl_uuc_bitmap_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_vsi_tbl_uuc_bitmap_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_vsi_tbl_member_port_bitmap_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_vsi_tbl_member_port_bitmap_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_vsi_tbl_new_addr_lrn_en_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_vsi_tbl_new_addr_lrn_en_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_vsi_tbl_bc_bitmap_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_vsi_tbl_bc_bitmap_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_vsi_tbl_station_move_fwd_cmd_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_vsi_tbl_station_move_fwd_cmd_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_vlan_cnt_tbl_get( - a_uint32_t dev_id, - a_uint32_t index, - union vlan_cnt_tbl_u *value); - -sw_error_t -hppe_vlan_cnt_tbl_set( - a_uint32_t dev_id, - a_uint32_t index, - union vlan_cnt_tbl_u *value); - -sw_error_t -hppe_vlan_cnt_tbl_rx_byte_cnt_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint64_t *value); - -sw_error_t -hppe_vlan_cnt_tbl_rx_byte_cnt_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint64_t value); - -sw_error_t -hppe_vlan_cnt_tbl_rx_pkt_cnt_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_vlan_cnt_tbl_rx_pkt_cnt_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_eg_vsi_counter_tbl_get( - a_uint32_t dev_id, - a_uint32_t index, - union eg_vsi_counter_tbl_u *value); - -sw_error_t -hppe_eg_vsi_counter_tbl_set( - a_uint32_t dev_id, - a_uint32_t index, - union eg_vsi_counter_tbl_u *value); - - -sw_error_t -hppe_eg_vsi_counter_tbl_tx_bytes_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint64_t *value); - -sw_error_t -hppe_eg_vsi_counter_tbl_tx_bytes_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint64_t value); - -sw_error_t -hppe_eg_vsi_counter_tbl_tx_packets_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_eg_vsi_counter_tbl_tx_packets_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_pre_l2_cnt_tbl_get( - a_uint32_t dev_id, - a_uint32_t index, - union pre_l2_cnt_tbl_u *value); - -sw_error_t -hppe_pre_l2_cnt_tbl_set( - a_uint32_t dev_id, - a_uint32_t index, - union pre_l2_cnt_tbl_u *value); - -sw_error_t -hppe_pre_l2_cnt_tbl_rx_drop_byte_cnt_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint64_t *value); - -sw_error_t -hppe_pre_l2_cnt_tbl_rx_drop_byte_cnt_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint64_t value); - -sw_error_t -hppe_pre_l2_cnt_tbl_rx_byte_cnt_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint64_t *value); - -sw_error_t -hppe_pre_l2_cnt_tbl_rx_byte_cnt_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint64_t value); - -sw_error_t -hppe_pre_l2_cnt_tbl_rx_pkt_cnt_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_pre_l2_cnt_tbl_rx_pkt_cnt_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_pre_l2_cnt_tbl_rx_drop_pkt_cnt_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_pre_l2_cnt_tbl_rx_drop_pkt_cnt_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -#endif - diff --git a/feeds/ipq807x/qca-ssdk/src/include/hsl/hppe/hppe_vsi_reg.h b/feeds/ipq807x/qca-ssdk/src/include/hsl/hppe/hppe_vsi_reg.h deleted file mode 100755 index 7a94bc332..000000000 --- a/feeds/ipq807x/qca-ssdk/src/include/hsl/hppe/hppe_vsi_reg.h +++ /dev/null @@ -1,192 +0,0 @@ -/* - * Copyright (c) 2016-2017, The Linux Foundation. All rights reserved. - * Permission to use, copy, modify, and/or distribute this software for - * any purpose with or without fee is hereby granted, provided that the - * above copyright notice and this permission notice appear in all copies. - * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES - * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR - * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES - * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN - * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT - * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. - */ - - -/** - * @defgroup - * @{ - */ -#ifndef HPPE_VSI_REG_H -#define HPPE_VSI_REG_H - -/*[table] VSI_TBL*/ -#define VSI_TBL -#define VSI_TBL_ADDRESS 0x1800 -#define VSI_TBL_NUM 32 -#define VSI_TBL_INC 0x10 -#define VSI_TBL_TYPE REG_TYPE_RW -#define VSI_TBL_DEFAULT 0x0 - /*[field] MEMBER_PORT_BITMAP*/ - #define VSI_TBL_MEMBER_PORT_BITMAP - #define VSI_TBL_MEMBER_PORT_BITMAP_OFFSET 0 - #define VSI_TBL_MEMBER_PORT_BITMAP_LEN 8 - #define VSI_TBL_MEMBER_PORT_BITMAP_DEFAULT 0x0 - /*[field] UUC_BITMAP*/ - #define VSI_TBL_UUC_BITMAP - #define VSI_TBL_UUC_BITMAP_OFFSET 8 - #define VSI_TBL_UUC_BITMAP_LEN 8 - #define VSI_TBL_UUC_BITMAP_DEFAULT 0x0 - /*[field] UMC_BITMAP*/ - #define VSI_TBL_UMC_BITMAP - #define VSI_TBL_UMC_BITMAP_OFFSET 16 - #define VSI_TBL_UMC_BITMAP_LEN 8 - #define VSI_TBL_UMC_BITMAP_DEFAULT 0x0 - /*[field] BC_BITMAP*/ - #define VSI_TBL_BC_BITMAP - #define VSI_TBL_BC_BITMAP_OFFSET 24 - #define VSI_TBL_BC_BITMAP_LEN 8 - #define VSI_TBL_BC_BITMAP_DEFAULT 0x0 - /*[field] NEW_ADDR_LRN_EN*/ - #define VSI_TBL_NEW_ADDR_LRN_EN - #define VSI_TBL_NEW_ADDR_LRN_EN_OFFSET 32 - #define VSI_TBL_NEW_ADDR_LRN_EN_LEN 1 - #define VSI_TBL_NEW_ADDR_LRN_EN_DEFAULT 0x0 - /*[field] NEW_ADDR_FWD_CMD*/ - #define VSI_TBL_NEW_ADDR_FWD_CMD - #define VSI_TBL_NEW_ADDR_FWD_CMD_OFFSET 33 - #define VSI_TBL_NEW_ADDR_FWD_CMD_LEN 2 - #define VSI_TBL_NEW_ADDR_FWD_CMD_DEFAULT 0x0 - /*[field] STATION_MOVE_LRN_EN*/ - #define VSI_TBL_STATION_MOVE_LRN_EN - #define VSI_TBL_STATION_MOVE_LRN_EN_OFFSET 35 - #define VSI_TBL_STATION_MOVE_LRN_EN_LEN 1 - #define VSI_TBL_STATION_MOVE_LRN_EN_DEFAULT 0x0 - /*[field] STATION_MOVE_FWD_CMD*/ - #define VSI_TBL_STATION_MOVE_FWD_CMD - #define VSI_TBL_STATION_MOVE_FWD_CMD_OFFSET 36 - #define VSI_TBL_STATION_MOVE_FWD_CMD_LEN 2 - #define VSI_TBL_STATION_MOVE_FWD_CMD_DEFAULT 0x0 - -struct vsi_tbl { - a_uint32_t member_port_bitmap:8; - a_uint32_t uuc_bitmap:8; - a_uint32_t umc_bitmap:8; - a_uint32_t bc_bitmap:8; - a_uint32_t new_addr_lrn_en:1; - a_uint32_t new_addr_fwd_cmd:2; - a_uint32_t station_move_lrn_en:1; - a_uint32_t station_move_fwd_cmd:2; - a_uint32_t _reserved0:26; -}; - -union vsi_tbl_u { - a_uint32_t val[2]; - struct vsi_tbl bf; -}; - -/*[table] VLAN_CNT_TBL*/ -#define VLAN_CNT_TBL -#define VLAN_CNT_TBL_ADDRESS 0x78000 -#define VLAN_CNT_TBL_NUM 32 -#define VLAN_CNT_TBL_INC 0x10 -#define VLAN_CNT_TBL_TYPE REG_TYPE_RW -#define VLAN_CNT_TBL_DEFAULT 0x0 - /*[field] RX_PKT_CNT*/ - #define VLAN_CNT_TBL_RX_PKT_CNT - #define VLAN_CNT_TBL_RX_PKT_CNT_OFFSET 0 - #define VLAN_CNT_TBL_RX_PKT_CNT_LEN 32 - #define VLAN_CNT_TBL_RX_PKT_CNT_DEFAULT 0x0 - /*[field] RX_BYTE_CNT*/ - #define VLAN_CNT_TBL_RX_BYTE_CNT - #define VLAN_CNT_TBL_RX_BYTE_CNT_OFFSET 32 - #define VLAN_CNT_TBL_RX_BYTE_CNT_LEN 40 - #define VLAN_CNT_TBL_RX_BYTE_CNT_DEFAULT 0x0 - -struct vlan_cnt_tbl { - a_uint32_t rx_pkt_cnt:32; - a_uint32_t rx_byte_cnt_0:32; - a_uint32_t rx_byte_cnt_1:8; - a_uint32_t _reserved0:24; -}; - -union vlan_cnt_tbl_u { - a_uint32_t val[3]; - struct vlan_cnt_tbl bf; -}; - -/*[table] EG_VSI_COUNTER_TBL*/ -#define EG_VSI_COUNTER_TBL -#define EG_VSI_COUNTER_TBL_ADDRESS 0x600 -#define EG_VSI_COUNTER_TBL_NUM 32 -#define EG_VSI_COUNTER_TBL_INC 0x10 -#define EG_VSI_COUNTER_TBL_TYPE REG_TYPE_RW -#define EG_VSI_COUNTER_TBL_DEFAULT 0x0 - /*[field] TX_PACKETS*/ - #define EG_VSI_COUNTER_TBL_TX_PACKETS - #define EG_VSI_COUNTER_TBL_TX_PACKETS_OFFSET 0 - #define EG_VSI_COUNTER_TBL_TX_PACKETS_LEN 32 - #define EG_VSI_COUNTER_TBL_TX_PACKETS_DEFAULT 0x0 - /*[field] TX_BYTES*/ - #define EG_VSI_COUNTER_TBL_TX_BYTES - #define EG_VSI_COUNTER_TBL_TX_BYTES_OFFSET 32 - #define EG_VSI_COUNTER_TBL_TX_BYTES_LEN 40 - #define EG_VSI_COUNTER_TBL_TX_BYTES_DEFAULT 0x0 - -struct eg_vsi_counter_tbl { - a_uint32_t tx_packets:32; - a_uint32_t tx_bytes_0:32; - a_uint32_t tx_bytes_1:8; - a_uint32_t _reserved0:24; -}; - -union eg_vsi_counter_tbl_u { - a_uint32_t val[3]; - struct eg_vsi_counter_tbl bf; -}; - -/*[table] PRE_L2_CNT_TBL*/ -#define PRE_L2_CNT_TBL -#define PRE_L2_CNT_TBL_ADDRESS 0x7c000 -#define PRE_L2_CNT_TBL_NUM 32 -#define PRE_L2_CNT_TBL_INC 0x20 -#define PRE_L2_CNT_TBL_TYPE REG_TYPE_RW -#define PRE_L2_CNT_TBL_DEFAULT 0x0 - /*[field] RX_PKT_CNT*/ - #define PRE_L2_CNT_TBL_RX_PKT_CNT - #define PRE_L2_CNT_TBL_RX_PKT_CNT_OFFSET 0 - #define PRE_L2_CNT_TBL_RX_PKT_CNT_LEN 32 - #define PRE_L2_CNT_TBL_RX_PKT_CNT_DEFAULT 0x0 - /*[field] RX_BYTE_CNT*/ - #define PRE_L2_CNT_TBL_RX_BYTE_CNT - #define PRE_L2_CNT_TBL_RX_BYTE_CNT_OFFSET 32 - #define PRE_L2_CNT_TBL_RX_BYTE_CNT_LEN 40 - #define PRE_L2_CNT_TBL_RX_BYTE_CNT_DEFAULT 0x0 - /*[field] RX_DROP_PKT_CNT*/ - #define PRE_L2_CNT_TBL_RX_DROP_PKT_CNT - #define PRE_L2_CNT_TBL_RX_DROP_PKT_CNT_OFFSET 72 - #define PRE_L2_CNT_TBL_RX_DROP_PKT_CNT_LEN 32 - #define PRE_L2_CNT_TBL_RX_DROP_PKT_CNT_DEFAULT 0x0 - /*[field] RX_DROP_BYTE_CNT*/ - #define PRE_L2_CNT_TBL_RX_DROP_BYTE_CNT - #define PRE_L2_CNT_TBL_RX_DROP_BYTE_CNT_OFFSET 104 - #define PRE_L2_CNT_TBL_RX_DROP_BYTE_CNT_LEN 40 - #define PRE_L2_CNT_TBL_RX_DROP_BYTE_CNT_DEFAULT 0x0 - -struct pre_l2_cnt_tbl { - a_uint32_t rx_pkt_cnt:32; - a_uint32_t rx_byte_cnt_0:32; - a_uint32_t rx_byte_cnt_1:8; - a_uint32_t rx_drop_pkt_cnt_0:24; - a_uint32_t rx_drop_pkt_cnt_1:8; - a_uint32_t rx_drop_byte_cnt_0:24; - a_uint32_t rx_drop_byte_cnt_1:16; - a_uint32_t _reserved0:16; -}; - -union pre_l2_cnt_tbl_u { - a_uint32_t val[5]; - struct pre_l2_cnt_tbl bf; -}; - -#endif diff --git a/feeds/ipq807x/qca-ssdk/src/include/hsl/hppe/hppe_xgmacmib.h b/feeds/ipq807x/qca-ssdk/src/include/hsl/hppe/hppe_xgmacmib.h deleted file mode 100755 index 40997c6f2..000000000 --- a/feeds/ipq807x/qca-ssdk/src/include/hsl/hppe/hppe_xgmacmib.h +++ /dev/null @@ -1,2252 +0,0 @@ -/* - * Copyright (c) 2016-2017, The Linux Foundation. All rights reserved. - * Permission to use, copy, modify, and/or distribute this software for - * any purpose with or without fee is hereby granted, provided that the - * above copyright notice and this permission notice appear in all copies. - * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES - * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR - * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES - * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN - * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT - * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. - */ - - -/** - * @defgroup - * @{ - */ -#ifndef _HPPE_XGMACMIB_H_ -#define _HPPE_XGMACMIB_H_ - -#define MMC_CONTROL_MAX_ENTRY 2 -#define MMC_RECEIVE_INTERRUPT_MAX_ENTRY 2 -#define MMC_TRANSMIT_INTERRUPT_MAX_ENTRY 2 -#define MMC_RECEIVE_INTERRUPT_ENABLE_MAX_ENTRY 2 -#define MMC_TRANSMIT_INTERRUPT_ENABLE_MAX_ENTRY 2 -#define TX_OCTET_COUNT_GOOD_BAD_LOW_MAX_ENTRY 2 -#define TX_OCTET_COUNT_GOOD_BAD_HIGH_MAX_ENTRY 2 -#define TX_FRAME_COUNT_GOOD_BAD_LOW_MAX_ENTRY 2 -#define TX_FRAME_COUNT_GOOD_BAD_HIGH_MAX_ENTRY 2 -#define TX_BROADCAST_FRAMES_GOOD_LOW_MAX_ENTRY 2 -#define TX_BROADCAST_FRAMES_GOOD_HIGH_MAX_ENTRY 2 -#define TX_MULTICAST_FRAMES_GOOD_LOW_MAX_ENTRY 2 -#define TX_MULTICAST_FRAMES_GOOD_HIGH_MAX_ENTRY 2 -#define TX_64OCTETS_FRAMES_GOOD_BAD_LOW_MAX_ENTRY 2 -#define TX_64OCTETS_FRAMES_GOOD_BAD_HIGH_MAX_ENTRY 2 -#define TX_65TO127OCTETS_FRAMES_GOOD_BAD_LOW_MAX_ENTRY 2 -#define TX_65TO127OCTETS_FRAMES_GOOD_BAD_HIGH_MAX_ENTRY 2 -#define TX_128TO255OCTETS_FRAMES_GOOD_BAD_LOW_MAX_ENTRY 2 -#define TX_128TO255OCTETS_FRAMES_GOOD_BAD_HIGH_MAX_ENTRY 2 -#define TX_256TO511OCTETS_FRAMES_GOOD_BAD_LOW_MAX_ENTRY 2 -#define TX_256TO511OCTETS_FRAMES_GOOD_BAD_HIGH_MAX_ENTRY 2 -#define TX_512TO1023OCTETS_FRAMES_GOOD_BAD_LOW_MAX_ENTRY 2 -#define TX_512TO1023OCTETS_FRAMES_GOOD_BAD_HIGH_MAX_ENTRY 2 -#define TX_1024TOMAXOCTETS_FRAMES_GOOD_BAD_LOW_MAX_ENTRY 2 -#define TX_1024TOMAXOCTETS_FRAMES_GOOD_BAD_HIGH_MAX_ENTRY 2 -#define TX_UNICAST_FRAMES_GOOD_BAD_LOW_MAX_ENTRY 2 -#define TX_UNICAST_FRAMES_GOOD_BAD_HIGH_MAX_ENTRY 2 -#define TX_MULTICAST_FRAMES_GOOD_BAD_LOW_MAX_ENTRY 2 -#define TX_MULTICAST_FRAMES_GOOD_BAD_HIGH_MAX_ENTRY 2 -#define TX_BROADCAST_FRAMES_GOOD_BAD_LOW_MAX_ENTRY 2 -#define TX_BROADCAST_FRAMES_GOOD_BAD_HIGH_MAX_ENTRY 2 -#define TX_UNDERFLOW_ERROR_FRAMES_LOW_MAX_ENTRY 2 -#define TX_UNDERFLOW_ERROR_FRAMES_HIGH_MAX_ENTRY 2 -#define TX_OCTET_COUNT_GOOD_LOW_MAX_ENTRY 2 -#define TX_OCTET_COUNT_GOOD_HIGH_MAX_ENTRY 2 -#define TX_FRAME_COUNT_GOOD_LOW_MAX_ENTRY 2 -#define TX_FRAME_COUNT_GOOD_HIGH_MAX_ENTRY 2 -#define TX_PAUSE_FRAMES_LOW_MAX_ENTRY 2 -#define TX_PAUSE_FRAMES_HIGH_MAX_ENTRY 2 -#define TX_VLAN_FRAMES_GOOD_LOW_MAX_ENTRY 2 -#define TX_VLAN_FRAMES_GOOD_HIGH_MAX_ENTRY 2 -#define TX_LPI_USEC_CNTR_MAX_ENTRY 2 -#define TX_LPI_TRAN_CNTR_MAX_ENTRY 2 -#define RX_FRAME_COUNT_GOOD_BAD_LOW_MAX_ENTRY 2 -#define RX_FRAME_COUNT_GOOD_BAD_HIGH_MAX_ENTRY 2 -#define RX_OCTET_COUNT_GOOD_BAD_LOW_MAX_ENTRY 2 -#define RX_OCTET_COUNT_GOOD_BAD_HIGH_MAX_ENTRY 2 -#define RX_OCTET_COUNT_GOOD_LOW_MAX_ENTRY 2 -#define RX_OCTET_COUNT_GOOD_HIGH_MAX_ENTRY 2 -#define RX_BROADCAST_FRAMES_GOOD_LOW_MAX_ENTRY 2 -#define RX_BROADCAST_FRAMES_GOOD_HIGH_MAX_ENTRY 2 -#define RX_MULTICAST_FRAMES_GOOD_LOW_MAX_ENTRY 2 -#define RX_MULTICAST_FRAMES_GOOD_HIGH_MAX_ENTRY 2 -#define RX_CRC_ERROR_FRAMES_LOW_MAX_ENTRY 2 -#define RX_CRC_ERROR_FRAMES_HIGH_MAX_ENTRY 2 -#define RX_RUNT_ERROR_FRAMES_MAX_ENTRY 2 -#define RX_JABBER_ERROR_FRAMES_MAX_ENTRY 2 -#define RX_UNDERSIZE_FRAMES_GOOD_MAX_ENTRY 2 -#define RX_OVERSIZE_FRAMES_GOOD_MAX_ENTRY 2 -#define RX_64OCTETS_FRAMES_GOOD_BAD_LOW_MAX_ENTRY 2 -#define RX_64OCTETS_FRAMES_GOOD_BAD_HIGH_MAX_ENTRY 2 -#define RX_65TO127OCTETS_FRAMES_GOOD_BAD_LOW_MAX_ENTRY 2 -#define RX_65TO127OCTETS_FRAMES_GOOD_BAD_HIGH_MAX_ENTRY 2 -#define RX_128TO255OCTETS_FRAMES_GOOD_BAD_LOW_MAX_ENTRY 2 -#define RX_128TO255OCTETS_FRAMES_GOOD_BAD_HIGH_MAX_ENTRY 2 -#define RX_256TO511OCTETS_FRAMES_GOOD_BAD_LOW_MAX_ENTRY 2 -#define RX_256TO511OCTETS_FRAMES_GOOD_BAD_HIGH_MAX_ENTRY 2 -#define RX_512TO1023OCTETS_FRAMES_GOOD_BAD_LOW_MAX_ENTRY 2 -#define RX_512TO1023OCTETS_FRAMES_GOOD_BAD_HIGH_MAX_ENTRY 2 -#define RX_1024TOMAXOCTETS_FRAMES_GOOD_BAD_LOW_MAX_ENTRY 2 -#define RX_1024TOMAXOCTETS_FRAMES_GOOD_BAD_HIGH_MAX_ENTRY 2 -#define RX_UNICAST_FRAMES_GOOD_LOW_MAX_ENTRY 2 -#define RX_UNICAST_FRAMES_GOOD_HIGH_MAX_ENTRY 2 -#define RX_LENGTH_ERROR_FRAMES_LOW_MAX_ENTRY 2 -#define RX_LENGTH_ERROR_FRAMES_HIGH_MAX_ENTRY 2 -#define RX_OUTOFRANGE_FRAMES_LOW_MAX_ENTRY 2 -#define RX_OUTOFRANGE_FRAMES_HIGH_MAX_ENTRY 2 -#define RX_PAUSE_FRAMES_LOW_MAX_ENTRY 2 -#define RX_PAUSE_FRAMES_HIGH_MAX_ENTRY 2 -#define RX_FIFOOVERFLOW_FRAMES_LOW_MAX_ENTRY 2 -#define RX_FIFOOVERFLOW_FRAMES_HIGH_MAX_ENTRY 2 -#define RX_VLAN_FRAMES_GOOD_BAD_LOW_MAX_ENTRY 2 -#define RX_VLAN_FRAMES_GOOD_BAD_HIGH_MAX_ENTRY 2 -#define RX_WATCHDOG_ERROR_FRAMES_MAX_ENTRY 2 -#define RX_LPI_USEC_CNTR_MAX_ENTRY 2 -#define RX_LPI_TRAN_CNTR_MAX_ENTRY 2 -#define RX_DISCARD_FRAME_COUNT_GOOD_BAD_LOW_MAX_ENTRY 2 -#define RX_DISCARD_FRAME_COUNT_GOOD_BAD_HIGH_MAX_ENTRY 2 -#define RX_DISCARD_OCTET_COUNT_GOOD_BAD_LOW_MAX_ENTRY 2 -#define RX_DISCARD_OCTET_COUNT_GOOD_BAD_HIGH_MAX_ENTRY 2 - -sw_error_t -hppe_mmc_control_get( - a_uint32_t dev_id, - a_uint32_t index, - union mmc_control_u *value); - -sw_error_t -hppe_mmc_control_set( - a_uint32_t dev_id, - a_uint32_t index, - union mmc_control_u *value); - -sw_error_t -hppe_tx_octet_count_good_bad_low_get( - a_uint32_t dev_id, - a_uint32_t index, - union tx_octet_count_good_bad_low_u *value); - -sw_error_t -hppe_tx_octet_count_good_bad_low_set( - a_uint32_t dev_id, - a_uint32_t index, - union tx_octet_count_good_bad_low_u *value); - -sw_error_t -hppe_tx_octet_count_good_bad_high_get( - a_uint32_t dev_id, - a_uint32_t index, - union tx_octet_count_good_bad_high_u *value); - -sw_error_t -hppe_tx_octet_count_good_bad_high_set( - a_uint32_t dev_id, - a_uint32_t index, - union tx_octet_count_good_bad_high_u *value); - -sw_error_t -hppe_tx_frame_count_good_bad_low_get( - a_uint32_t dev_id, - a_uint32_t index, - union tx_frame_count_good_bad_low_u *value); - -sw_error_t -hppe_tx_frame_count_good_bad_low_set( - a_uint32_t dev_id, - a_uint32_t index, - union tx_frame_count_good_bad_low_u *value); - -sw_error_t -hppe_tx_frame_count_good_bad_high_get( - a_uint32_t dev_id, - a_uint32_t index, - union tx_frame_count_good_bad_high_u *value); - -sw_error_t -hppe_tx_frame_count_good_bad_high_set( - a_uint32_t dev_id, - a_uint32_t index, - union tx_frame_count_good_bad_high_u *value); - -sw_error_t -hppe_tx_broadcast_frames_good_low_get( - a_uint32_t dev_id, - a_uint32_t index, - union tx_broadcast_frames_good_low_u *value); - -sw_error_t -hppe_tx_broadcast_frames_good_low_set( - a_uint32_t dev_id, - a_uint32_t index, - union tx_broadcast_frames_good_low_u *value); - -sw_error_t -hppe_tx_broadcast_frames_good_high_get( - a_uint32_t dev_id, - a_uint32_t index, - union tx_broadcast_frames_good_high_u *value); - -sw_error_t -hppe_tx_broadcast_frames_good_high_set( - a_uint32_t dev_id, - a_uint32_t index, - union tx_broadcast_frames_good_high_u *value); - -sw_error_t -hppe_tx_multicast_frames_good_low_get( - a_uint32_t dev_id, - a_uint32_t index, - union tx_multicast_frames_good_low_u *value); - -sw_error_t -hppe_tx_multicast_frames_good_low_set( - a_uint32_t dev_id, - a_uint32_t index, - union tx_multicast_frames_good_low_u *value); - -sw_error_t -hppe_tx_multicast_frames_good_high_get( - a_uint32_t dev_id, - a_uint32_t index, - union tx_multicast_frames_good_high_u *value); - -sw_error_t -hppe_tx_multicast_frames_good_high_set( - a_uint32_t dev_id, - a_uint32_t index, - union tx_multicast_frames_good_high_u *value); - -sw_error_t -hppe_tx_64octets_frames_good_bad_low_get( - a_uint32_t dev_id, - a_uint32_t index, - union tx_64octets_frames_good_bad_low_u *value); - -sw_error_t -hppe_tx_64octets_frames_good_bad_low_set( - a_uint32_t dev_id, - a_uint32_t index, - union tx_64octets_frames_good_bad_low_u *value); - -sw_error_t -hppe_tx_64octets_frames_good_bad_high_get( - a_uint32_t dev_id, - a_uint32_t index, - union tx_64octets_frames_good_bad_high_u *value); - -sw_error_t -hppe_tx_64octets_frames_good_bad_high_set( - a_uint32_t dev_id, - a_uint32_t index, - union tx_64octets_frames_good_bad_high_u *value); - -sw_error_t -hppe_tx_65to127octets_frames_good_bad_low_get( - a_uint32_t dev_id, - a_uint32_t index, - union tx_65to127octets_frames_good_bad_low_u *value); - -sw_error_t -hppe_tx_65to127octets_frames_good_bad_low_set( - a_uint32_t dev_id, - a_uint32_t index, - union tx_65to127octets_frames_good_bad_low_u *value); - -sw_error_t -hppe_tx_65to127octets_frames_good_bad_high_get( - a_uint32_t dev_id, - a_uint32_t index, - union tx_65to127octets_frames_good_bad_high_u *value); - -sw_error_t -hppe_tx_65to127octets_frames_good_bad_high_set( - a_uint32_t dev_id, - a_uint32_t index, - union tx_65to127octets_frames_good_bad_high_u *value); - -sw_error_t -hppe_tx_128to255octets_frames_good_bad_low_get( - a_uint32_t dev_id, - a_uint32_t index, - union tx_128to255octets_frames_good_bad_low_u *value); - -sw_error_t -hppe_tx_128to255octets_frames_good_bad_low_set( - a_uint32_t dev_id, - a_uint32_t index, - union tx_128to255octets_frames_good_bad_low_u *value); - -sw_error_t -hppe_tx_128to255octets_frames_good_bad_high_get( - a_uint32_t dev_id, - a_uint32_t index, - union tx_128to255octets_frames_good_bad_high_u *value); - -sw_error_t -hppe_tx_128to255octets_frames_good_bad_high_set( - a_uint32_t dev_id, - a_uint32_t index, - union tx_128to255octets_frames_good_bad_high_u *value); - -sw_error_t -hppe_tx_256to511octets_frames_good_bad_low_get( - a_uint32_t dev_id, - a_uint32_t index, - union tx_256to511octets_frames_good_bad_low_u *value); - -sw_error_t -hppe_tx_256to511octets_frames_good_bad_low_set( - a_uint32_t dev_id, - a_uint32_t index, - union tx_256to511octets_frames_good_bad_low_u *value); - -sw_error_t -hppe_tx_256to511octets_frames_good_bad_high_get( - a_uint32_t dev_id, - a_uint32_t index, - union tx_256to511octets_frames_good_bad_high_u *value); - -sw_error_t -hppe_tx_256to511octets_frames_good_bad_high_set( - a_uint32_t dev_id, - a_uint32_t index, - union tx_256to511octets_frames_good_bad_high_u *value); - -sw_error_t -hppe_tx_512to1023octets_frames_good_bad_low_get( - a_uint32_t dev_id, - a_uint32_t index, - union tx_512to1023octets_frames_good_bad_low_u *value); - -sw_error_t -hppe_tx_512to1023octets_frames_good_bad_low_set( - a_uint32_t dev_id, - a_uint32_t index, - union tx_512to1023octets_frames_good_bad_low_u *value); - -sw_error_t -hppe_tx_512to1023octets_frames_good_bad_high_get( - a_uint32_t dev_id, - a_uint32_t index, - union tx_512to1023octets_frames_good_bad_high_u *value); - -sw_error_t -hppe_tx_512to1023octets_frames_good_bad_high_set( - a_uint32_t dev_id, - a_uint32_t index, - union tx_512to1023octets_frames_good_bad_high_u *value); - -sw_error_t -hppe_tx_1024tomaxoctets_frames_good_bad_low_get( - a_uint32_t dev_id, - a_uint32_t index, - union tx_1024tomaxoctets_frames_good_bad_low_u *value); - -sw_error_t -hppe_tx_1024tomaxoctets_frames_good_bad_low_set( - a_uint32_t dev_id, - a_uint32_t index, - union tx_1024tomaxoctets_frames_good_bad_low_u *value); - -sw_error_t -hppe_tx_1024tomaxoctets_frames_good_bad_high_get( - a_uint32_t dev_id, - a_uint32_t index, - union tx_1024tomaxoctets_frames_good_bad_high_u *value); - -sw_error_t -hppe_tx_1024tomaxoctets_frames_good_bad_high_set( - a_uint32_t dev_id, - a_uint32_t index, - union tx_1024tomaxoctets_frames_good_bad_high_u *value); - -sw_error_t -hppe_tx_unicast_frames_good_bad_low_get( - a_uint32_t dev_id, - a_uint32_t index, - union tx_unicast_frames_good_bad_low_u *value); - -sw_error_t -hppe_tx_unicast_frames_good_bad_low_set( - a_uint32_t dev_id, - a_uint32_t index, - union tx_unicast_frames_good_bad_low_u *value); - -sw_error_t -hppe_tx_unicast_frames_good_bad_high_get( - a_uint32_t dev_id, - a_uint32_t index, - union tx_unicast_frames_good_bad_high_u *value); - -sw_error_t -hppe_tx_unicast_frames_good_bad_high_set( - a_uint32_t dev_id, - a_uint32_t index, - union tx_unicast_frames_good_bad_high_u *value); - -sw_error_t -hppe_tx_multicast_frames_good_bad_low_get( - a_uint32_t dev_id, - a_uint32_t index, - union tx_multicast_frames_good_bad_low_u *value); - -sw_error_t -hppe_tx_multicast_frames_good_bad_low_set( - a_uint32_t dev_id, - a_uint32_t index, - union tx_multicast_frames_good_bad_low_u *value); - -sw_error_t -hppe_tx_multicast_frames_good_bad_high_get( - a_uint32_t dev_id, - a_uint32_t index, - union tx_multicast_frames_good_bad_high_u *value); - -sw_error_t -hppe_tx_multicast_frames_good_bad_high_set( - a_uint32_t dev_id, - a_uint32_t index, - union tx_multicast_frames_good_bad_high_u *value); - -sw_error_t -hppe_tx_broadcast_frames_good_bad_low_get( - a_uint32_t dev_id, - a_uint32_t index, - union tx_broadcast_frames_good_bad_low_u *value); - -sw_error_t -hppe_tx_broadcast_frames_good_bad_low_set( - a_uint32_t dev_id, - a_uint32_t index, - union tx_broadcast_frames_good_bad_low_u *value); - -sw_error_t -hppe_tx_broadcast_frames_good_bad_high_get( - a_uint32_t dev_id, - a_uint32_t index, - union tx_broadcast_frames_good_bad_high_u *value); - -sw_error_t -hppe_tx_broadcast_frames_good_bad_high_set( - a_uint32_t dev_id, - a_uint32_t index, - union tx_broadcast_frames_good_bad_high_u *value); - -sw_error_t -hppe_tx_underflow_error_frames_low_get( - a_uint32_t dev_id, - a_uint32_t index, - union tx_underflow_error_frames_low_u *value); - -sw_error_t -hppe_tx_underflow_error_frames_low_set( - a_uint32_t dev_id, - a_uint32_t index, - union tx_underflow_error_frames_low_u *value); - -sw_error_t -hppe_tx_underflow_error_frames_high_get( - a_uint32_t dev_id, - a_uint32_t index, - union tx_underflow_error_frames_high_u *value); - -sw_error_t -hppe_tx_underflow_error_frames_high_set( - a_uint32_t dev_id, - a_uint32_t index, - union tx_underflow_error_frames_high_u *value); - -sw_error_t -hppe_tx_octet_count_good_low_get( - a_uint32_t dev_id, - a_uint32_t index, - union tx_octet_count_good_low_u *value); - -sw_error_t -hppe_tx_octet_count_good_low_set( - a_uint32_t dev_id, - a_uint32_t index, - union tx_octet_count_good_low_u *value); - -sw_error_t -hppe_tx_octet_count_good_high_get( - a_uint32_t dev_id, - a_uint32_t index, - union tx_octet_count_good_high_u *value); - -sw_error_t -hppe_tx_octet_count_good_high_set( - a_uint32_t dev_id, - a_uint32_t index, - union tx_octet_count_good_high_u *value); - -sw_error_t -hppe_tx_frame_count_good_low_get( - a_uint32_t dev_id, - a_uint32_t index, - union tx_frame_count_good_low_u *value); - -sw_error_t -hppe_tx_frame_count_good_low_set( - a_uint32_t dev_id, - a_uint32_t index, - union tx_frame_count_good_low_u *value); - -sw_error_t -hppe_tx_frame_count_good_high_get( - a_uint32_t dev_id, - a_uint32_t index, - union tx_frame_count_good_high_u *value); - -sw_error_t -hppe_tx_frame_count_good_high_set( - a_uint32_t dev_id, - a_uint32_t index, - union tx_frame_count_good_high_u *value); - -sw_error_t -hppe_tx_pause_frames_low_get( - a_uint32_t dev_id, - a_uint32_t index, - union tx_pause_frames_low_u *value); - -sw_error_t -hppe_tx_pause_frames_low_set( - a_uint32_t dev_id, - a_uint32_t index, - union tx_pause_frames_low_u *value); - -sw_error_t -hppe_tx_pause_frames_high_get( - a_uint32_t dev_id, - a_uint32_t index, - union tx_pause_frames_high_u *value); - -sw_error_t -hppe_tx_pause_frames_high_set( - a_uint32_t dev_id, - a_uint32_t index, - union tx_pause_frames_high_u *value); - -sw_error_t -hppe_tx_vlan_frames_good_low_get( - a_uint32_t dev_id, - a_uint32_t index, - union tx_vlan_frames_good_low_u *value); - -sw_error_t -hppe_tx_vlan_frames_good_low_set( - a_uint32_t dev_id, - a_uint32_t index, - union tx_vlan_frames_good_low_u *value); - -sw_error_t -hppe_tx_vlan_frames_good_high_get( - a_uint32_t dev_id, - a_uint32_t index, - union tx_vlan_frames_good_high_u *value); - -sw_error_t -hppe_tx_vlan_frames_good_high_set( - a_uint32_t dev_id, - a_uint32_t index, - union tx_vlan_frames_good_high_u *value); - -sw_error_t -hppe_tx_lpi_usec_cntr_get( - a_uint32_t dev_id, - a_uint32_t index, - union tx_lpi_usec_cntr_u *value); - -sw_error_t -hppe_tx_lpi_usec_cntr_set( - a_uint32_t dev_id, - a_uint32_t index, - union tx_lpi_usec_cntr_u *value); - -sw_error_t -hppe_tx_lpi_tran_cntr_get( - a_uint32_t dev_id, - a_uint32_t index, - union tx_lpi_tran_cntr_u *value); - -sw_error_t -hppe_tx_lpi_tran_cntr_set( - a_uint32_t dev_id, - a_uint32_t index, - union tx_lpi_tran_cntr_u *value); - -sw_error_t -hppe_rx_frame_count_good_bad_low_get( - a_uint32_t dev_id, - a_uint32_t index, - union rx_frame_count_good_bad_low_u *value); - -sw_error_t -hppe_rx_frame_count_good_bad_low_set( - a_uint32_t dev_id, - a_uint32_t index, - union rx_frame_count_good_bad_low_u *value); - -sw_error_t -hppe_rx_frame_count_good_bad_high_get( - a_uint32_t dev_id, - a_uint32_t index, - union rx_frame_count_good_bad_high_u *value); - -sw_error_t -hppe_rx_frame_count_good_bad_high_set( - a_uint32_t dev_id, - a_uint32_t index, - union rx_frame_count_good_bad_high_u *value); - -sw_error_t -hppe_rx_octet_count_good_bad_low_get( - a_uint32_t dev_id, - a_uint32_t index, - union rx_octet_count_good_bad_low_u *value); - -sw_error_t -hppe_rx_octet_count_good_bad_low_set( - a_uint32_t dev_id, - a_uint32_t index, - union rx_octet_count_good_bad_low_u *value); - -sw_error_t -hppe_rx_octet_count_good_bad_high_get( - a_uint32_t dev_id, - a_uint32_t index, - union rx_octet_count_good_bad_high_u *value); - -sw_error_t -hppe_rx_octet_count_good_bad_high_set( - a_uint32_t dev_id, - a_uint32_t index, - union rx_octet_count_good_bad_high_u *value); - -sw_error_t -hppe_rx_octet_count_good_low_get( - a_uint32_t dev_id, - a_uint32_t index, - union rx_octet_count_good_low_u *value); - -sw_error_t -hppe_rx_octet_count_good_low_set( - a_uint32_t dev_id, - a_uint32_t index, - union rx_octet_count_good_low_u *value); - -sw_error_t -hppe_rx_octet_count_good_high_get( - a_uint32_t dev_id, - a_uint32_t index, - union rx_octet_count_good_high_u *value); - -sw_error_t -hppe_rx_octet_count_good_high_set( - a_uint32_t dev_id, - a_uint32_t index, - union rx_octet_count_good_high_u *value); - -sw_error_t -hppe_rx_broadcast_frames_good_low_get( - a_uint32_t dev_id, - a_uint32_t index, - union rx_broadcast_frames_good_low_u *value); - -sw_error_t -hppe_rx_broadcast_frames_good_low_set( - a_uint32_t dev_id, - a_uint32_t index, - union rx_broadcast_frames_good_low_u *value); - -sw_error_t -hppe_rx_broadcast_frames_good_high_get( - a_uint32_t dev_id, - a_uint32_t index, - union rx_broadcast_frames_good_high_u *value); - -sw_error_t -hppe_rx_broadcast_frames_good_high_set( - a_uint32_t dev_id, - a_uint32_t index, - union rx_broadcast_frames_good_high_u *value); - -sw_error_t -hppe_rx_multicast_frames_good_low_get( - a_uint32_t dev_id, - a_uint32_t index, - union rx_multicast_frames_good_low_u *value); - -sw_error_t -hppe_rx_multicast_frames_good_low_set( - a_uint32_t dev_id, - a_uint32_t index, - union rx_multicast_frames_good_low_u *value); - -sw_error_t -hppe_rx_multicast_frames_good_high_get( - a_uint32_t dev_id, - a_uint32_t index, - union rx_multicast_frames_good_high_u *value); - -sw_error_t -hppe_rx_multicast_frames_good_high_set( - a_uint32_t dev_id, - a_uint32_t index, - union rx_multicast_frames_good_high_u *value); - -sw_error_t -hppe_rx_crc_error_frames_low_get( - a_uint32_t dev_id, - a_uint32_t index, - union rx_crc_error_frames_low_u *value); - -sw_error_t -hppe_rx_crc_error_frames_low_set( - a_uint32_t dev_id, - a_uint32_t index, - union rx_crc_error_frames_low_u *value); - -sw_error_t -hppe_rx_crc_error_frames_high_get( - a_uint32_t dev_id, - a_uint32_t index, - union rx_crc_error_frames_high_u *value); - -sw_error_t -hppe_rx_crc_error_frames_high_set( - a_uint32_t dev_id, - a_uint32_t index, - union rx_crc_error_frames_high_u *value); - -sw_error_t -hppe_rx_runt_error_frames_get( - a_uint32_t dev_id, - a_uint32_t index, - union rx_runt_error_frames_u *value); - -sw_error_t -hppe_rx_runt_error_frames_set( - a_uint32_t dev_id, - a_uint32_t index, - union rx_runt_error_frames_u *value); - -sw_error_t -hppe_rx_jabber_error_frames_get( - a_uint32_t dev_id, - a_uint32_t index, - union rx_jabber_error_frames_u *value); - -sw_error_t -hppe_rx_jabber_error_frames_set( - a_uint32_t dev_id, - a_uint32_t index, - union rx_jabber_error_frames_u *value); - -sw_error_t -hppe_rx_undersize_frames_good_get( - a_uint32_t dev_id, - a_uint32_t index, - union rx_undersize_frames_good_u *value); - -sw_error_t -hppe_rx_undersize_frames_good_set( - a_uint32_t dev_id, - a_uint32_t index, - union rx_undersize_frames_good_u *value); - -sw_error_t -hppe_rx_oversize_frames_good_get( - a_uint32_t dev_id, - a_uint32_t index, - union rx_oversize_frames_good_u *value); - -sw_error_t -hppe_rx_oversize_frames_good_set( - a_uint32_t dev_id, - a_uint32_t index, - union rx_oversize_frames_good_u *value); - -sw_error_t -hppe_rx_64octets_frames_good_bad_low_get( - a_uint32_t dev_id, - a_uint32_t index, - union rx_64octets_frames_good_bad_low_u *value); - -sw_error_t -hppe_rx_64octets_frames_good_bad_low_set( - a_uint32_t dev_id, - a_uint32_t index, - union rx_64octets_frames_good_bad_low_u *value); - -sw_error_t -hppe_rx_64octets_frames_good_bad_high_get( - a_uint32_t dev_id, - a_uint32_t index, - union rx_64octets_frames_good_bad_high_u *value); - -sw_error_t -hppe_rx_64octets_frames_good_bad_high_set( - a_uint32_t dev_id, - a_uint32_t index, - union rx_64octets_frames_good_bad_high_u *value); - -sw_error_t -hppe_rx_65to127octets_frames_good_bad_low_get( - a_uint32_t dev_id, - a_uint32_t index, - union rx_65to127octets_frames_good_bad_low_u *value); - -sw_error_t -hppe_rx_65to127octets_frames_good_bad_low_set( - a_uint32_t dev_id, - a_uint32_t index, - union rx_65to127octets_frames_good_bad_low_u *value); - -sw_error_t -hppe_rx_65to127octets_frames_good_bad_high_get( - a_uint32_t dev_id, - a_uint32_t index, - union rx_65to127octets_frames_good_bad_high_u *value); - -sw_error_t -hppe_rx_65to127octets_frames_good_bad_high_set( - a_uint32_t dev_id, - a_uint32_t index, - union rx_65to127octets_frames_good_bad_high_u *value); - -sw_error_t -hppe_rx_128to255octets_frames_good_bad_low_get( - a_uint32_t dev_id, - a_uint32_t index, - union rx_128to255octets_frames_good_bad_low_u *value); - -sw_error_t -hppe_rx_128to255octets_frames_good_bad_low_set( - a_uint32_t dev_id, - a_uint32_t index, - union rx_128to255octets_frames_good_bad_low_u *value); - -sw_error_t -hppe_rx_128to255octets_frames_good_bad_high_get( - a_uint32_t dev_id, - a_uint32_t index, - union rx_128to255octets_frames_good_bad_high_u *value); - -sw_error_t -hppe_rx_128to255octets_frames_good_bad_high_set( - a_uint32_t dev_id, - a_uint32_t index, - union rx_128to255octets_frames_good_bad_high_u *value); - -sw_error_t -hppe_rx_256to511octets_frames_good_bad_low_get( - a_uint32_t dev_id, - a_uint32_t index, - union rx_256to511octets_frames_good_bad_low_u *value); - -sw_error_t -hppe_rx_256to511octets_frames_good_bad_low_set( - a_uint32_t dev_id, - a_uint32_t index, - union rx_256to511octets_frames_good_bad_low_u *value); - -sw_error_t -hppe_rx_256to511octets_frames_good_bad_high_get( - a_uint32_t dev_id, - a_uint32_t index, - union rx_256to511octets_frames_good_bad_high_u *value); - -sw_error_t -hppe_rx_256to511octets_frames_good_bad_high_set( - a_uint32_t dev_id, - a_uint32_t index, - union rx_256to511octets_frames_good_bad_high_u *value); - -sw_error_t -hppe_rx_512to1023octets_frames_good_bad_low_get( - a_uint32_t dev_id, - a_uint32_t index, - union rx_512to1023octets_frames_good_bad_low_u *value); - -sw_error_t -hppe_rx_512to1023octets_frames_good_bad_low_set( - a_uint32_t dev_id, - a_uint32_t index, - union rx_512to1023octets_frames_good_bad_low_u *value); - -sw_error_t -hppe_rx_512to1023octets_frames_good_bad_high_get( - a_uint32_t dev_id, - a_uint32_t index, - union rx_512to1023octets_frames_good_bad_high_u *value); - -sw_error_t -hppe_rx_512to1023octets_frames_good_bad_high_set( - a_uint32_t dev_id, - a_uint32_t index, - union rx_512to1023octets_frames_good_bad_high_u *value); - -sw_error_t -hppe_rx_1024tomaxoctets_frames_good_bad_low_get( - a_uint32_t dev_id, - a_uint32_t index, - union rx_1024tomaxoctets_frames_good_bad_low_u *value); - -sw_error_t -hppe_rx_1024tomaxoctets_frames_good_bad_low_set( - a_uint32_t dev_id, - a_uint32_t index, - union rx_1024tomaxoctets_frames_good_bad_low_u *value); - -sw_error_t -hppe_rx_1024tomaxoctets_frames_good_bad_high_get( - a_uint32_t dev_id, - a_uint32_t index, - union rx_1024tomaxoctets_frames_good_bad_high_u *value); - -sw_error_t -hppe_rx_1024tomaxoctets_frames_good_bad_high_set( - a_uint32_t dev_id, - a_uint32_t index, - union rx_1024tomaxoctets_frames_good_bad_high_u *value); - -sw_error_t -hppe_rx_unicast_frames_good_low_get( - a_uint32_t dev_id, - a_uint32_t index, - union rx_unicast_frames_good_low_u *value); - -sw_error_t -hppe_rx_unicast_frames_good_low_set( - a_uint32_t dev_id, - a_uint32_t index, - union rx_unicast_frames_good_low_u *value); - -sw_error_t -hppe_rx_unicast_frames_good_high_get( - a_uint32_t dev_id, - a_uint32_t index, - union rx_unicast_frames_good_high_u *value); - -sw_error_t -hppe_rx_unicast_frames_good_high_set( - a_uint32_t dev_id, - a_uint32_t index, - union rx_unicast_frames_good_high_u *value); - -sw_error_t -hppe_rx_length_error_frames_low_get( - a_uint32_t dev_id, - a_uint32_t index, - union rx_length_error_frames_low_u *value); - -sw_error_t -hppe_rx_length_error_frames_low_set( - a_uint32_t dev_id, - a_uint32_t index, - union rx_length_error_frames_low_u *value); - -sw_error_t -hppe_rx_length_error_frames_high_get( - a_uint32_t dev_id, - a_uint32_t index, - union rx_length_error_frames_high_u *value); - -sw_error_t -hppe_rx_length_error_frames_high_set( - a_uint32_t dev_id, - a_uint32_t index, - union rx_length_error_frames_high_u *value); - -sw_error_t -hppe_rx_outofrange_frames_low_get( - a_uint32_t dev_id, - a_uint32_t index, - union rx_outofrange_frames_low_u *value); - -sw_error_t -hppe_rx_outofrange_frames_low_set( - a_uint32_t dev_id, - a_uint32_t index, - union rx_outofrange_frames_low_u *value); - -sw_error_t -hppe_rx_outofrange_frames_high_get( - a_uint32_t dev_id, - a_uint32_t index, - union rx_outofrange_frames_high_u *value); - -sw_error_t -hppe_rx_outofrange_frames_high_set( - a_uint32_t dev_id, - a_uint32_t index, - union rx_outofrange_frames_high_u *value); - -sw_error_t -hppe_rx_pause_frames_low_get( - a_uint32_t dev_id, - a_uint32_t index, - union rx_pause_frames_low_u *value); - -sw_error_t -hppe_rx_pause_frames_low_set( - a_uint32_t dev_id, - a_uint32_t index, - union rx_pause_frames_low_u *value); - -sw_error_t -hppe_rx_pause_frames_high_get( - a_uint32_t dev_id, - a_uint32_t index, - union rx_pause_frames_high_u *value); - -sw_error_t -hppe_rx_pause_frames_high_set( - a_uint32_t dev_id, - a_uint32_t index, - union rx_pause_frames_high_u *value); - -sw_error_t -hppe_rx_fifooverflow_frames_low_get( - a_uint32_t dev_id, - a_uint32_t index, - union rx_fifooverflow_frames_low_u *value); - -sw_error_t -hppe_rx_fifooverflow_frames_low_set( - a_uint32_t dev_id, - a_uint32_t index, - union rx_fifooverflow_frames_low_u *value); - -sw_error_t -hppe_rx_fifooverflow_frames_high_get( - a_uint32_t dev_id, - a_uint32_t index, - union rx_fifooverflow_frames_high_u *value); - -sw_error_t -hppe_rx_fifooverflow_frames_high_set( - a_uint32_t dev_id, - a_uint32_t index, - union rx_fifooverflow_frames_high_u *value); - -sw_error_t -hppe_rx_vlan_frames_good_bad_low_get( - a_uint32_t dev_id, - a_uint32_t index, - union rx_vlan_frames_good_bad_low_u *value); - -sw_error_t -hppe_rx_vlan_frames_good_bad_low_set( - a_uint32_t dev_id, - a_uint32_t index, - union rx_vlan_frames_good_bad_low_u *value); - -sw_error_t -hppe_rx_vlan_frames_good_bad_high_get( - a_uint32_t dev_id, - a_uint32_t index, - union rx_vlan_frames_good_bad_high_u *value); - -sw_error_t -hppe_rx_vlan_frames_good_bad_high_set( - a_uint32_t dev_id, - a_uint32_t index, - union rx_vlan_frames_good_bad_high_u *value); - -sw_error_t -hppe_rx_watchdog_error_frames_get( - a_uint32_t dev_id, - a_uint32_t index, - union rx_watchdog_error_frames_u *value); - -sw_error_t -hppe_rx_watchdog_error_frames_set( - a_uint32_t dev_id, - a_uint32_t index, - union rx_watchdog_error_frames_u *value); - -sw_error_t -hppe_rx_lpi_usec_cntr_get( - a_uint32_t dev_id, - a_uint32_t index, - union rx_lpi_usec_cntr_u *value); - -sw_error_t -hppe_rx_lpi_usec_cntr_set( - a_uint32_t dev_id, - a_uint32_t index, - union rx_lpi_usec_cntr_u *value); - -sw_error_t -hppe_rx_lpi_tran_cntr_get( - a_uint32_t dev_id, - a_uint32_t index, - union rx_lpi_tran_cntr_u *value); - -sw_error_t -hppe_rx_lpi_tran_cntr_set( - a_uint32_t dev_id, - a_uint32_t index, - union rx_lpi_tran_cntr_u *value); - -sw_error_t -hppe_rx_discard_frame_count_good_bad_low_get( - a_uint32_t dev_id, - a_uint32_t index, - union rx_discard_frame_count_good_bad_low_u *value); - -sw_error_t -hppe_rx_discard_frame_count_good_bad_low_set( - a_uint32_t dev_id, - a_uint32_t index, - union rx_discard_frame_count_good_bad_low_u *value); - -sw_error_t -hppe_rx_discard_frame_count_good_bad_high_get( - a_uint32_t dev_id, - a_uint32_t index, - union rx_discard_frame_count_good_bad_high_u *value); - -sw_error_t -hppe_rx_discard_frame_count_good_bad_high_set( - a_uint32_t dev_id, - a_uint32_t index, - union rx_discard_frame_count_good_bad_high_u *value); - -sw_error_t -hppe_rx_discard_octet_count_good_bad_low_get( - a_uint32_t dev_id, - a_uint32_t index, - union rx_discard_octet_count_good_bad_low_u *value); - -sw_error_t -hppe_rx_discard_octet_count_good_bad_low_set( - a_uint32_t dev_id, - a_uint32_t index, - union rx_discard_octet_count_good_bad_low_u *value); - -sw_error_t -hppe_rx_discard_octet_count_good_bad_high_get( - a_uint32_t dev_id, - a_uint32_t index, - union rx_discard_octet_count_good_bad_high_u *value); - -sw_error_t -hppe_rx_discard_octet_count_good_bad_high_set( - a_uint32_t dev_id, - a_uint32_t index, - union rx_discard_octet_count_good_bad_high_u *value); - - -sw_error_t -hppe_mmc_control_cntrst_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_mmc_control_cntrst_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_mmc_control_rstonrd_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_mmc_control_rstonrd_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_mmc_control_cntstopro_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_mmc_control_cntstopro_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_mmc_control_mct_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_mmc_control_mct_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_mmc_control_pr_mmc_sel_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_mmc_control_pr_mmc_sel_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_mmc_control_cntprst_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_mmc_control_cntprst_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_mmc_control_mcf_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_mmc_control_mcf_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_tx_octet_count_good_bad_low_txoctgblo_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_tx_octet_count_good_bad_low_txoctgblo_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_tx_octet_count_good_bad_high_txoctgbhi_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_tx_octet_count_good_bad_high_txoctgbhi_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_tx_frame_count_good_bad_low_txfrmgblo_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_tx_frame_count_good_bad_low_txfrmgblo_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_tx_frame_count_good_bad_high_txfrmgbhi_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_tx_frame_count_good_bad_high_txfrmgbhi_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_tx_broadcast_frames_good_low_txbcastglo_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_tx_broadcast_frames_good_low_txbcastglo_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_tx_broadcast_frames_good_high_txbcastghi_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_tx_broadcast_frames_good_high_txbcastghi_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_tx_multicast_frames_good_low_txmcastglo_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_tx_multicast_frames_good_low_txmcastglo_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_tx_multicast_frames_good_high_txmcastghi_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_tx_multicast_frames_good_high_txmcastghi_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_tx_64octets_frames_good_bad_low_tx64octgblo_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_tx_64octets_frames_good_bad_low_tx64octgblo_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_tx_64octets_frames_good_bad_high_tx64octgbhi_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_tx_64octets_frames_good_bad_high_tx64octgbhi_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_tx_65to127octets_frames_good_bad_low_tx65_127octgblo_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_tx_65to127octets_frames_good_bad_low_tx65_127octgblo_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_tx_65to127octets_frames_good_bad_high_tx65_127octgbhi_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_tx_65to127octets_frames_good_bad_high_tx65_127octgbhi_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_tx_128to255octets_frames_good_bad_low_tx128_255octgblo_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_tx_128to255octets_frames_good_bad_low_tx128_255octgblo_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_tx_128to255octets_frames_good_bad_high_tx128_255octgbhi_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_tx_128to255octets_frames_good_bad_high_tx128_255octgbhi_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_tx_256to511octets_frames_good_bad_low_tx256_511octgblo_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_tx_256to511octets_frames_good_bad_low_tx256_511octgblo_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_tx_256to511octets_frames_good_bad_high_tx256_511octgbhi_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_tx_256to511octets_frames_good_bad_high_tx256_511octgbhi_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_tx_512to1023octets_frames_good_bad_low_tx512_1023octgblo_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_tx_512to1023octets_frames_good_bad_low_tx512_1023octgblo_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_tx_512to1023octets_frames_good_bad_high_tx512_1023octgbhi_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_tx_512to1023octets_frames_good_bad_high_tx512_1023octgbhi_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_tx_1024tomaxoctets_frames_good_bad_low_tx1024_maxoctgblo_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_tx_1024tomaxoctets_frames_good_bad_low_tx1024_maxoctgblo_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_tx_1024tomaxoctets_frames_good_bad_high_tx1024_maxoctgbhi_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_tx_1024tomaxoctets_frames_good_bad_high_tx1024_maxoctgbhi_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_tx_unicast_frames_good_bad_low_txucastgblo_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_tx_unicast_frames_good_bad_low_txucastgblo_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_tx_unicast_frames_good_bad_high_txucastgbhi_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_tx_unicast_frames_good_bad_high_txucastgbhi_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_tx_multicast_frames_good_bad_low_txmcastgblo_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_tx_multicast_frames_good_bad_low_txmcastgblo_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_tx_multicast_frames_good_bad_high_txmcastgbhi_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_tx_multicast_frames_good_bad_high_txmcastgbhi_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_tx_broadcast_frames_good_bad_low_txbcastgblo_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_tx_broadcast_frames_good_bad_low_txbcastgblo_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_tx_broadcast_frames_good_bad_high_txbcastgbhi_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_tx_broadcast_frames_good_bad_high_txbcastgbhi_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_tx_underflow_error_frames_low_txundrflwlo_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_tx_underflow_error_frames_low_txundrflwlo_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_tx_underflow_error_frames_high_txundrflwhi_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_tx_underflow_error_frames_high_txundrflwhi_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_tx_octet_count_good_low_txoctglo_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_tx_octet_count_good_low_txoctglo_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_tx_octet_count_good_high_txoctghi_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_tx_octet_count_good_high_txoctghi_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_tx_frame_count_good_low_txfrmglo_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_tx_frame_count_good_low_txfrmglo_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_tx_frame_count_good_high_txfrmghi_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_tx_frame_count_good_high_txfrmghi_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_tx_pause_frames_low_txpauseglo_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_tx_pause_frames_low_txpauseglo_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_tx_pause_frames_high_txpauseghi_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_tx_pause_frames_high_txpauseghi_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_tx_vlan_frames_good_low_txvlanglo_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_tx_vlan_frames_good_low_txvlanglo_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_tx_vlan_frames_good_high_txvlanghi_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_tx_vlan_frames_good_high_txvlanghi_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_tx_lpi_usec_cntr_txlpiusc_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_tx_lpi_usec_cntr_txlpiusc_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_tx_lpi_tran_cntr_txlpitrc_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_tx_lpi_tran_cntr_txlpitrc_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_rx_frame_count_good_bad_low_rxfrmgblo_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_rx_frame_count_good_bad_low_rxfrmgblo_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_rx_frame_count_good_bad_high_rxfrmgbhi_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_rx_frame_count_good_bad_high_rxfrmgbhi_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_rx_octet_count_good_bad_low_rxoctgblo_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_rx_octet_count_good_bad_low_rxoctgblo_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_rx_octet_count_good_bad_high_rxoctgbhi_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_rx_octet_count_good_bad_high_rxoctgbhi_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_rx_octet_count_good_low_rxoctglo_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_rx_octet_count_good_low_rxoctglo_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_rx_octet_count_good_high_rxoctghi_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_rx_octet_count_good_high_rxoctghi_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_rx_broadcast_frames_good_low_rxbcastglo_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_rx_broadcast_frames_good_low_rxbcastglo_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_rx_broadcast_frames_good_high_rxbcastghi_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_rx_broadcast_frames_good_high_rxbcastghi_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_rx_multicast_frames_good_low_rxmcastglo_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_rx_multicast_frames_good_low_rxmcastglo_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_rx_multicast_frames_good_high_rxmcastghi_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_rx_multicast_frames_good_high_rxmcastghi_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_rx_crc_error_frames_low_rxcrcerlo_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_rx_crc_error_frames_low_rxcrcerlo_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_rx_crc_error_frames_high_rxcrcerhi_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_rx_crc_error_frames_high_rxcrcerhi_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_rx_runt_error_frames_rxrunter_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_rx_runt_error_frames_rxrunter_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_rx_jabber_error_frames_rxjaberer_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_rx_jabber_error_frames_rxjaberer_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_rx_undersize_frames_good_rxusizeg_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_rx_undersize_frames_good_rxusizeg_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_rx_oversize_frames_good_rxosizeg_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_rx_oversize_frames_good_rxosizeg_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_rx_64octets_frames_good_bad_low_rx64octgblo_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_rx_64octets_frames_good_bad_low_rx64octgblo_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_rx_64octets_frames_good_bad_high_rx64octgbhi_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_rx_64octets_frames_good_bad_high_rx64octgbhi_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_rx_65to127octets_frames_good_bad_low_rx65_127octgblo_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_rx_65to127octets_frames_good_bad_low_rx65_127octgblo_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_rx_65to127octets_frames_good_bad_high_rx65_127octgbhi_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_rx_65to127octets_frames_good_bad_high_rx65_127octgbhi_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_rx_128to255octets_frames_good_bad_low_rx128_255octgblo_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_rx_128to255octets_frames_good_bad_low_rx128_255octgblo_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_rx_128to255octets_frames_good_bad_high_rx128_255octgbhi_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_rx_128to255octets_frames_good_bad_high_rx128_255octgbhi_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_rx_256to511octets_frames_good_bad_low_rx256_511octgblo_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_rx_256to511octets_frames_good_bad_low_rx256_511octgblo_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_rx_256to511octets_frames_good_bad_high_rx256_511octgbhi_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_rx_256to511octets_frames_good_bad_high_rx256_511octgbhi_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_rx_512to1023octets_frames_good_bad_low_rx512_1023octgblo_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_rx_512to1023octets_frames_good_bad_low_rx512_1023octgblo_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_rx_512to1023octets_frames_good_bad_high_rx512_1023octgbhi_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_rx_512to1023octets_frames_good_bad_high_rx512_1023octgbhi_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_rx_1024tomaxoctets_frames_good_bad_low_rx1024_maxgboctlo_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_rx_1024tomaxoctets_frames_good_bad_low_rx1024_maxgboctlo_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_rx_1024tomaxoctets_frames_good_bad_high_rx1024_maxgbocthi_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_rx_1024tomaxoctets_frames_good_bad_high_rx1024_maxgbocthi_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_rx_unicast_frames_good_low_rxucastglo_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_rx_unicast_frames_good_low_rxucastglo_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_rx_unicast_frames_good_high_rxucastghi_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_rx_unicast_frames_good_high_rxucastghi_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_rx_length_error_frames_low_rxlenerrlo_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_rx_length_error_frames_low_rxlenerrlo_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_rx_length_error_frames_high_rxlenerrhi_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_rx_length_error_frames_high_rxlenerrhi_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_rx_outofrange_frames_low_rxorangelo_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_rx_outofrange_frames_low_rxorangelo_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_rx_outofrange_frames_high_rxorangehi_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_rx_outofrange_frames_high_rxorangehi_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_rx_pause_frames_low_rxpauselo_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_rx_pause_frames_low_rxpauselo_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_rx_pause_frames_high_rxpausehi_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_rx_pause_frames_high_rxpausehi_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_rx_fifooverflow_frames_low_rxfovflo_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_rx_fifooverflow_frames_low_rxfovflo_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_rx_fifooverflow_frames_high_rxfovfhi_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_rx_fifooverflow_frames_high_rxfovfhi_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_rx_vlan_frames_good_bad_low_rxvlangblo_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_rx_vlan_frames_good_bad_low_rxvlangblo_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_rx_vlan_frames_good_bad_high_rxvlangbhi_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_rx_vlan_frames_good_bad_high_rxvlangbhi_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_rx_watchdog_error_frames_rxwdogerr_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_rx_watchdog_error_frames_rxwdogerr_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_rx_lpi_usec_cntr_rxlpiusc_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_rx_lpi_usec_cntr_rxlpiusc_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_rx_lpi_tran_cntr_rxlpitrc_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_rx_lpi_tran_cntr_rxlpitrc_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_rx_discard_frame_count_good_bad_low_rxdfcntgblo_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_rx_discard_frame_count_good_bad_low_rxdfcntgblo_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_rx_discard_frame_count_good_bad_high_rxdfcntgbhi_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_rx_discard_frame_count_good_bad_high_rxdfcntgbhi_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_rx_discard_octet_count_good_bad_low_rxdocntgblo_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_rx_discard_octet_count_good_bad_low_rxdocntgblo_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_rx_discard_octet_count_good_bad_high_rxdocntgbhi_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_rx_discard_octet_count_good_bad_high_rxdocntgbhi_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -#endif - diff --git a/feeds/ipq807x/qca-ssdk/src/include/hsl/hppe/hppe_xgmacmib_reg.h b/feeds/ipq807x/qca-ssdk/src/include/hsl/hppe/hppe_xgmacmib_reg.h deleted file mode 100755 index 8059aeb6d..000000000 --- a/feeds/ipq807x/qca-ssdk/src/include/hsl/hppe/hppe_xgmacmib_reg.h +++ /dev/null @@ -1,1956 +0,0 @@ -/* - * Copyright (c) 2016-2017, The Linux Foundation. All rights reserved. - * Permission to use, copy, modify, and/or distribute this software for - * any purpose with or without fee is hereby granted, provided that the - * above copyright notice and this permission notice appear in all copies. - * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES - * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR - * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES - * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN - * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT - * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. - */ - - -/** - * @defgroup - * @{ - */ -#ifndef HPPE_XGMACMIB_REG_H -#define HPPE_XGMACMIB_REG_H - -/*[register] MMC_CONTROL*/ -#define MMC_CONTROL -#define MMC_CONTROL_ADDRESS 0x800 -#define MMC_CONTROL_NUM 2 -#define MMC_CONTROL_INC 0x4000 -#define MMC_CONTROL_TYPE REG_TYPE_RO -#define MMC_CONTROL_DEFAULT 0x0 - /*[field] CNTRST*/ - #define MMC_CONTROL_CNTRST - #define MMC_CONTROL_CNTRST_OFFSET 0 - #define MMC_CONTROL_CNTRST_LEN 1 - #define MMC_CONTROL_CNTRST_DEFAULT 0x0 - /*[field] CNTSTOPRO*/ - #define MMC_CONTROL_CNTSTOPRO - #define MMC_CONTROL_CNTSTOPRO_OFFSET 1 - #define MMC_CONTROL_CNTSTOPRO_LEN 1 - #define MMC_CONTROL_CNTSTOPRO_DEFAULT 0x0 - /*[field] RSTONRD*/ - #define MMC_CONTROL_RSTONRD - #define MMC_CONTROL_RSTONRD_OFFSET 2 - #define MMC_CONTROL_RSTONRD_LEN 1 - #define MMC_CONTROL_RSTONRD_DEFAULT 0x0 - /*[field] MCF*/ - #define MMC_CONTROL_MCF - #define MMC_CONTROL_MCF_OFFSET 3 - #define MMC_CONTROL_MCF_LEN 1 - #define MMC_CONTROL_MCF_DEFAULT 0x0 - /*[field] MCT*/ - #define MMC_CONTROL_MCT - #define MMC_CONTROL_MCT_OFFSET 4 - #define MMC_CONTROL_MCT_LEN 2 - #define MMC_CONTROL_MCT_DEFAULT 0x0 - /*[field] CNTPRST*/ - #define MMC_CONTROL_CNTPRST - #define MMC_CONTROL_CNTPRST_OFFSET 7 - #define MMC_CONTROL_CNTPRST_LEN 1 - #define MMC_CONTROL_CNTPRST_DEFAULT 0x0 - /*[field] PR_MMC_SEL*/ - #define MMC_CONTROL_PR_MMC_SEL - #define MMC_CONTROL_PR_MMC_SEL_OFFSET 16 - #define MMC_CONTROL_PR_MMC_SEL_LEN 3 - #define MMC_CONTROL_PR_MMC_SEL_DEFAULT 0x0 - -struct mmc_control { - a_uint32_t cntrst:1; - a_uint32_t cntstopro:1; - a_uint32_t rstonrd:1; - a_uint32_t mcf:1; - a_uint32_t mct:2; - a_uint32_t _reserved0:1; - a_uint32_t cntprst:1; - a_uint32_t _reserved1:8; - a_uint32_t pr_mmc_sel:3; - a_uint32_t _reserved2:13; -}; - -union mmc_control_u { - a_uint32_t val; - struct mmc_control bf; -}; - -/*[register] TX_OCTET_COUNT_GOOD_BAD_LOW*/ -#define TX_OCTET_COUNT_GOOD_BAD_LOW -#define TX_OCTET_COUNT_GOOD_BAD_LOW_ADDRESS 0x814 -#define TX_OCTET_COUNT_GOOD_BAD_LOW_NUM 2 -#define TX_OCTET_COUNT_GOOD_BAD_LOW_INC 0x4000 -#define TX_OCTET_COUNT_GOOD_BAD_LOW_TYPE REG_TYPE_RO -#define TX_OCTET_COUNT_GOOD_BAD_LOW_DEFAULT 0x0 - /*[field] TXOCTGBLO*/ - #define TX_OCTET_COUNT_GOOD_BAD_LOW_TXOCTGBLO - #define TX_OCTET_COUNT_GOOD_BAD_LOW_TXOCTGBLO_OFFSET 0 - #define TX_OCTET_COUNT_GOOD_BAD_LOW_TXOCTGBLO_LEN 32 - #define TX_OCTET_COUNT_GOOD_BAD_LOW_TXOCTGBLO_DEFAULT 0x0 - -struct tx_octet_count_good_bad_low { - a_uint32_t txoctgblo:32; -}; - -union tx_octet_count_good_bad_low_u { - a_uint32_t val; - struct tx_octet_count_good_bad_low bf; -}; - -/*[register] TX_OCTET_COUNT_GOOD_BAD_HIGH*/ -#define TX_OCTET_COUNT_GOOD_BAD_HIGH -#define TX_OCTET_COUNT_GOOD_BAD_HIGH_ADDRESS 0x818 -#define TX_OCTET_COUNT_GOOD_BAD_HIGH_NUM 2 -#define TX_OCTET_COUNT_GOOD_BAD_HIGH_INC 0x4000 -#define TX_OCTET_COUNT_GOOD_BAD_HIGH_TYPE REG_TYPE_RO -#define TX_OCTET_COUNT_GOOD_BAD_HIGH_DEFAULT 0x0 - /*[field] TXOCTGBHI*/ - #define TX_OCTET_COUNT_GOOD_BAD_HIGH_TXOCTGBHI - #define TX_OCTET_COUNT_GOOD_BAD_HIGH_TXOCTGBHI_OFFSET 0 - #define TX_OCTET_COUNT_GOOD_BAD_HIGH_TXOCTGBHI_LEN 32 - #define TX_OCTET_COUNT_GOOD_BAD_HIGH_TXOCTGBHI_DEFAULT 0x0 - -struct tx_octet_count_good_bad_high { - a_uint32_t txoctgbhi:32; -}; - -union tx_octet_count_good_bad_high_u { - a_uint32_t val; - struct tx_octet_count_good_bad_high bf; -}; - -/*[register] TX_FRAME_COUNT_GOOD_BAD_LOW*/ -#define TX_FRAME_COUNT_GOOD_BAD_LOW -#define TX_FRAME_COUNT_GOOD_BAD_LOW_ADDRESS 0x81c -#define TX_FRAME_COUNT_GOOD_BAD_LOW_NUM 2 -#define TX_FRAME_COUNT_GOOD_BAD_LOW_INC 0x4000 -#define TX_FRAME_COUNT_GOOD_BAD_LOW_TYPE REG_TYPE_RO -#define TX_FRAME_COUNT_GOOD_BAD_LOW_DEFAULT 0x0 - /*[field] TXFRMGBLO*/ - #define TX_FRAME_COUNT_GOOD_BAD_LOW_TXFRMGBLO - #define TX_FRAME_COUNT_GOOD_BAD_LOW_TXFRMGBLO_OFFSET 0 - #define TX_FRAME_COUNT_GOOD_BAD_LOW_TXFRMGBLO_LEN 32 - #define TX_FRAME_COUNT_GOOD_BAD_LOW_TXFRMGBLO_DEFAULT 0x0 - -struct tx_frame_count_good_bad_low { - a_uint32_t txfrmgblo:32; -}; - -union tx_frame_count_good_bad_low_u { - a_uint32_t val; - struct tx_frame_count_good_bad_low bf; -}; - -/*[register] TX_FRAME_COUNT_GOOD_BAD_HIGH*/ -#define TX_FRAME_COUNT_GOOD_BAD_HIGH -#define TX_FRAME_COUNT_GOOD_BAD_HIGH_ADDRESS 0x820 -#define TX_FRAME_COUNT_GOOD_BAD_HIGH_NUM 2 -#define TX_FRAME_COUNT_GOOD_BAD_HIGH_INC 0x4000 -#define TX_FRAME_COUNT_GOOD_BAD_HIGH_TYPE REG_TYPE_RO -#define TX_FRAME_COUNT_GOOD_BAD_HIGH_DEFAULT 0x0 - /*[field] TXFRMGBHI*/ - #define TX_FRAME_COUNT_GOOD_BAD_HIGH_TXFRMGBHI - #define TX_FRAME_COUNT_GOOD_BAD_HIGH_TXFRMGBHI_OFFSET 0 - #define TX_FRAME_COUNT_GOOD_BAD_HIGH_TXFRMGBHI_LEN 32 - #define TX_FRAME_COUNT_GOOD_BAD_HIGH_TXFRMGBHI_DEFAULT 0x0 - -struct tx_frame_count_good_bad_high { - a_uint32_t txfrmgbhi:32; -}; - -union tx_frame_count_good_bad_high_u { - a_uint32_t val; - struct tx_frame_count_good_bad_high bf; -}; - -/*[register] TX_BROADCAST_FRAMES_GOOD_LOW*/ -#define TX_BROADCAST_FRAMES_GOOD_LOW -#define TX_BROADCAST_FRAMES_GOOD_LOW_ADDRESS 0x824 -#define TX_BROADCAST_FRAMES_GOOD_LOW_NUM 2 -#define TX_BROADCAST_FRAMES_GOOD_LOW_INC 0x4000 -#define TX_BROADCAST_FRAMES_GOOD_LOW_TYPE REG_TYPE_RO -#define TX_BROADCAST_FRAMES_GOOD_LOW_DEFAULT 0x0 - /*[field] TXBCASTGLO*/ - #define TX_BROADCAST_FRAMES_GOOD_LOW_TXBCASTGLO - #define TX_BROADCAST_FRAMES_GOOD_LOW_TXBCASTGLO_OFFSET 0 - #define TX_BROADCAST_FRAMES_GOOD_LOW_TXBCASTGLO_LEN 32 - #define TX_BROADCAST_FRAMES_GOOD_LOW_TXBCASTGLO_DEFAULT 0x0 - -struct tx_broadcast_frames_good_low { - a_uint32_t txbcastglo:32; -}; - -union tx_broadcast_frames_good_low_u { - a_uint32_t val; - struct tx_broadcast_frames_good_low bf; -}; - -/*[register] TX_BROADCAST_FRAMES_GOOD_HIGH*/ -#define TX_BROADCAST_FRAMES_GOOD_HIGH -#define TX_BROADCAST_FRAMES_GOOD_HIGH_ADDRESS 0x828 -#define TX_BROADCAST_FRAMES_GOOD_HIGH_NUM 2 -#define TX_BROADCAST_FRAMES_GOOD_HIGH_INC 0x4000 -#define TX_BROADCAST_FRAMES_GOOD_HIGH_TYPE REG_TYPE_RO -#define TX_BROADCAST_FRAMES_GOOD_HIGH_DEFAULT 0x0 - /*[field] TXBCASTGHI*/ - #define TX_BROADCAST_FRAMES_GOOD_HIGH_TXBCASTGHI - #define TX_BROADCAST_FRAMES_GOOD_HIGH_TXBCASTGHI_OFFSET 0 - #define TX_BROADCAST_FRAMES_GOOD_HIGH_TXBCASTGHI_LEN 32 - #define TX_BROADCAST_FRAMES_GOOD_HIGH_TXBCASTGHI_DEFAULT 0x0 - -struct tx_broadcast_frames_good_high { - a_uint32_t txbcastghi:32; -}; - -union tx_broadcast_frames_good_high_u { - a_uint32_t val; - struct tx_broadcast_frames_good_high bf; -}; - -/*[register] TX_MULTICAST_FRAMES_GOOD_LOW*/ -#define TX_MULTICAST_FRAMES_GOOD_LOW -#define TX_MULTICAST_FRAMES_GOOD_LOW_ADDRESS 0x82c -#define TX_MULTICAST_FRAMES_GOOD_LOW_NUM 2 -#define TX_MULTICAST_FRAMES_GOOD_LOW_INC 0x4000 -#define TX_MULTICAST_FRAMES_GOOD_LOW_TYPE REG_TYPE_RO -#define TX_MULTICAST_FRAMES_GOOD_LOW_DEFAULT 0x0 - /*[field] TXMCASTGLO*/ - #define TX_MULTICAST_FRAMES_GOOD_LOW_TXMCASTGLO - #define TX_MULTICAST_FRAMES_GOOD_LOW_TXMCASTGLO_OFFSET 0 - #define TX_MULTICAST_FRAMES_GOOD_LOW_TXMCASTGLO_LEN 32 - #define TX_MULTICAST_FRAMES_GOOD_LOW_TXMCASTGLO_DEFAULT 0x0 - -struct tx_multicast_frames_good_low { - a_uint32_t txmcastglo:32; -}; - -union tx_multicast_frames_good_low_u { - a_uint32_t val; - struct tx_multicast_frames_good_low bf; -}; - -/*[register] TX_MULTICAST_FRAMES_GOOD_HIGH*/ -#define TX_MULTICAST_FRAMES_GOOD_HIGH -#define TX_MULTICAST_FRAMES_GOOD_HIGH_ADDRESS 0x830 -#define TX_MULTICAST_FRAMES_GOOD_HIGH_NUM 2 -#define TX_MULTICAST_FRAMES_GOOD_HIGH_INC 0x4000 -#define TX_MULTICAST_FRAMES_GOOD_HIGH_TYPE REG_TYPE_RO -#define TX_MULTICAST_FRAMES_GOOD_HIGH_DEFAULT 0x0 - /*[field] TXMCASTGHI*/ - #define TX_MULTICAST_FRAMES_GOOD_HIGH_TXMCASTGHI - #define TX_MULTICAST_FRAMES_GOOD_HIGH_TXMCASTGHI_OFFSET 0 - #define TX_MULTICAST_FRAMES_GOOD_HIGH_TXMCASTGHI_LEN 32 - #define TX_MULTICAST_FRAMES_GOOD_HIGH_TXMCASTGHI_DEFAULT 0x0 - -struct tx_multicast_frames_good_high { - a_uint32_t txmcastghi:32; -}; - -union tx_multicast_frames_good_high_u { - a_uint32_t val; - struct tx_multicast_frames_good_high bf; -}; - -/*[register] TX_64OCTETS_FRAMES_GOOD_BAD_LOW*/ -#define TX_64OCTETS_FRAMES_GOOD_BAD_LOW -#define TX_64OCTETS_FRAMES_GOOD_BAD_LOW_ADDRESS 0x834 -#define TX_64OCTETS_FRAMES_GOOD_BAD_LOW_NUM 2 -#define TX_64OCTETS_FRAMES_GOOD_BAD_LOW_INC 0x4000 -#define TX_64OCTETS_FRAMES_GOOD_BAD_LOW_TYPE REG_TYPE_RO -#define TX_64OCTETS_FRAMES_GOOD_BAD_LOW_DEFAULT 0x0 - /*[field] TX64OCTGBLO*/ - #define TX_64OCTETS_FRAMES_GOOD_BAD_LOW_TX64OCTGBLO - #define TX_64OCTETS_FRAMES_GOOD_BAD_LOW_TX64OCTGBLO_OFFSET 0 - #define TX_64OCTETS_FRAMES_GOOD_BAD_LOW_TX64OCTGBLO_LEN 32 - #define TX_64OCTETS_FRAMES_GOOD_BAD_LOW_TX64OCTGBLO_DEFAULT 0x0 - -struct tx_64octets_frames_good_bad_low { - a_uint32_t tx64octgblo:32; -}; - -union tx_64octets_frames_good_bad_low_u { - a_uint32_t val; - struct tx_64octets_frames_good_bad_low bf; -}; - -/*[register] TX_64OCTETS_FRAMES_GOOD_BAD_HIGH*/ -#define TX_64OCTETS_FRAMES_GOOD_BAD_HIGH -#define TX_64OCTETS_FRAMES_GOOD_BAD_HIGH_ADDRESS 0x838 -#define TX_64OCTETS_FRAMES_GOOD_BAD_HIGH_NUM 2 -#define TX_64OCTETS_FRAMES_GOOD_BAD_HIGH_INC 0x4000 -#define TX_64OCTETS_FRAMES_GOOD_BAD_HIGH_TYPE REG_TYPE_RO -#define TX_64OCTETS_FRAMES_GOOD_BAD_HIGH_DEFAULT 0x0 - /*[field] TX64OCTGBHI*/ - #define TX_64OCTETS_FRAMES_GOOD_BAD_HIGH_TX64OCTGBHI - #define TX_64OCTETS_FRAMES_GOOD_BAD_HIGH_TX64OCTGBHI_OFFSET 0 - #define TX_64OCTETS_FRAMES_GOOD_BAD_HIGH_TX64OCTGBHI_LEN 32 - #define TX_64OCTETS_FRAMES_GOOD_BAD_HIGH_TX64OCTGBHI_DEFAULT 0x0 - -struct tx_64octets_frames_good_bad_high { - a_uint32_t tx64octgbhi:32; -}; - -union tx_64octets_frames_good_bad_high_u { - a_uint32_t val; - struct tx_64octets_frames_good_bad_high bf; -}; - -/*[register] TX_65TO127OCTETS_FRAMES_GOOD_BAD_LOW*/ -#define TX_65TO127OCTETS_FRAMES_GOOD_BAD_LOW -#define TX_65TO127OCTETS_FRAMES_GOOD_BAD_LOW_ADDRESS 0x83c -#define TX_65TO127OCTETS_FRAMES_GOOD_BAD_LOW_NUM 2 -#define TX_65TO127OCTETS_FRAMES_GOOD_BAD_LOW_INC 0x4000 -#define TX_65TO127OCTETS_FRAMES_GOOD_BAD_LOW_TYPE REG_TYPE_RO -#define TX_65TO127OCTETS_FRAMES_GOOD_BAD_LOW_DEFAULT 0x0 - /*[field] TX65_127OCTGBLO*/ - #define TX_65TO127OCTETS_FRAMES_GOOD_BAD_LOW_TX65_127OCTGBLO - #define TX_65TO127OCTETS_FRAMES_GOOD_BAD_LOW_TX65_127OCTGBLO_OFFSET 0 - #define TX_65TO127OCTETS_FRAMES_GOOD_BAD_LOW_TX65_127OCTGBLO_LEN 32 - #define TX_65TO127OCTETS_FRAMES_GOOD_BAD_LOW_TX65_127OCTGBLO_DEFAULT 0x0 - -struct tx_65to127octets_frames_good_bad_low { - a_uint32_t tx65_127octgblo:32; -}; - -union tx_65to127octets_frames_good_bad_low_u { - a_uint32_t val; - struct tx_65to127octets_frames_good_bad_low bf; -}; - -/*[register] TX_65TO127OCTETS_FRAMES_GOOD_BAD_HIGH*/ -#define TX_65TO127OCTETS_FRAMES_GOOD_BAD_HIGH -#define TX_65TO127OCTETS_FRAMES_GOOD_BAD_HIGH_ADDRESS 0x840 -#define TX_65TO127OCTETS_FRAMES_GOOD_BAD_HIGH_NUM 2 -#define TX_65TO127OCTETS_FRAMES_GOOD_BAD_HIGH_INC 0x4000 -#define TX_65TO127OCTETS_FRAMES_GOOD_BAD_HIGH_TYPE REG_TYPE_RO -#define TX_65TO127OCTETS_FRAMES_GOOD_BAD_HIGH_DEFAULT 0x0 - /*[field] TX65_127OCTGBHI*/ - #define TX_65TO127OCTETS_FRAMES_GOOD_BAD_HIGH_TX65_127OCTGBHI - #define TX_65TO127OCTETS_FRAMES_GOOD_BAD_HIGH_TX65_127OCTGBHI_OFFSET 0 - #define TX_65TO127OCTETS_FRAMES_GOOD_BAD_HIGH_TX65_127OCTGBHI_LEN 32 - #define TX_65TO127OCTETS_FRAMES_GOOD_BAD_HIGH_TX65_127OCTGBHI_DEFAULT 0x0 - -struct tx_65to127octets_frames_good_bad_high { - a_uint32_t tx65_127octgbhi:32; -}; - -union tx_65to127octets_frames_good_bad_high_u { - a_uint32_t val; - struct tx_65to127octets_frames_good_bad_high bf; -}; - -/*[register] TX_128TO255OCTETS_FRAMES_GOOD_BAD_LOW*/ -#define TX_128TO255OCTETS_FRAMES_GOOD_BAD_LOW -#define TX_128TO255OCTETS_FRAMES_GOOD_BAD_LOW_ADDRESS 0x844 -#define TX_128TO255OCTETS_FRAMES_GOOD_BAD_LOW_NUM 2 -#define TX_128TO255OCTETS_FRAMES_GOOD_BAD_LOW_INC 0x4000 -#define TX_128TO255OCTETS_FRAMES_GOOD_BAD_LOW_TYPE REG_TYPE_RO -#define TX_128TO255OCTETS_FRAMES_GOOD_BAD_LOW_DEFAULT 0x0 - /*[field] TX128_255OCTGBLO*/ - #define TX_128TO255OCTETS_FRAMES_GOOD_BAD_LOW_TX128_255OCTGBLO - #define TX_128TO255OCTETS_FRAMES_GOOD_BAD_LOW_TX128_255OCTGBLO_OFFSET 0 - #define TX_128TO255OCTETS_FRAMES_GOOD_BAD_LOW_TX128_255OCTGBLO_LEN 32 - #define TX_128TO255OCTETS_FRAMES_GOOD_BAD_LOW_TX128_255OCTGBLO_DEFAULT 0x0 - -struct tx_128to255octets_frames_good_bad_low { - a_uint32_t tx128_255octgblo:32; -}; - -union tx_128to255octets_frames_good_bad_low_u { - a_uint32_t val; - struct tx_128to255octets_frames_good_bad_low bf; -}; - -/*[register] TX_128TO255OCTETS_FRAMES_GOOD_BAD_HIGH*/ -#define TX_128TO255OCTETS_FRAMES_GOOD_BAD_HIGH -#define TX_128TO255OCTETS_FRAMES_GOOD_BAD_HIGH_ADDRESS 0x848 -#define TX_128TO255OCTETS_FRAMES_GOOD_BAD_HIGH_NUM 2 -#define TX_128TO255OCTETS_FRAMES_GOOD_BAD_HIGH_INC 0x4000 -#define TX_128TO255OCTETS_FRAMES_GOOD_BAD_HIGH_TYPE REG_TYPE_RO -#define TX_128TO255OCTETS_FRAMES_GOOD_BAD_HIGH_DEFAULT 0x0 - /*[field] TX128_255OCTGBHI*/ - #define TX_128TO255OCTETS_FRAMES_GOOD_BAD_HIGH_TX128_255OCTGBHI - #define TX_128TO255OCTETS_FRAMES_GOOD_BAD_HIGH_TX128_255OCTGBHI_OFFSET 0 - #define TX_128TO255OCTETS_FRAMES_GOOD_BAD_HIGH_TX128_255OCTGBHI_LEN 32 - #define TX_128TO255OCTETS_FRAMES_GOOD_BAD_HIGH_TX128_255OCTGBHI_DEFAULT 0x0 - -struct tx_128to255octets_frames_good_bad_high { - a_uint32_t tx128_255octgbhi:32; -}; - -union tx_128to255octets_frames_good_bad_high_u { - a_uint32_t val; - struct tx_128to255octets_frames_good_bad_high bf; -}; - -/*[register] TX_256TO511OCTETS_FRAMES_GOOD_BAD_LOW*/ -#define TX_256TO511OCTETS_FRAMES_GOOD_BAD_LOW -#define TX_256TO511OCTETS_FRAMES_GOOD_BAD_LOW_ADDRESS 0x84c -#define TX_256TO511OCTETS_FRAMES_GOOD_BAD_LOW_NUM 1 -#define TX_256TO511OCTETS_FRAMES_GOOD_BAD_LOW_INC 0x4000 -#define TX_256TO511OCTETS_FRAMES_GOOD_BAD_LOW_TYPE REG_TYPE_RO -#define TX_256TO511OCTETS_FRAMES_GOOD_BAD_LOW_DEFAULT 0x0 - /*[field] TX256_511OCTGBLO*/ - #define TX_256TO511OCTETS_FRAMES_GOOD_BAD_LOW_TX256_511OCTGBLO - #define TX_256TO511OCTETS_FRAMES_GOOD_BAD_LOW_TX256_511OCTGBLO_OFFSET 0 - #define TX_256TO511OCTETS_FRAMES_GOOD_BAD_LOW_TX256_511OCTGBLO_LEN 32 - #define TX_256TO511OCTETS_FRAMES_GOOD_BAD_LOW_TX256_511OCTGBLO_DEFAULT 0x0 - -struct tx_256to511octets_frames_good_bad_low { - a_uint32_t tx256_511octgblo:32; -}; - -union tx_256to511octets_frames_good_bad_low_u { - a_uint32_t val; - struct tx_256to511octets_frames_good_bad_low bf; -}; - -/*[register] TX_256TO511OCTETS_FRAMES_GOOD_BAD_HIGH*/ -#define TX_256TO511OCTETS_FRAMES_GOOD_BAD_HIGH -#define TX_256TO511OCTETS_FRAMES_GOOD_BAD_HIGH_ADDRESS 0x850 -#define TX_256TO511OCTETS_FRAMES_GOOD_BAD_HIGH_NUM 1 -#define TX_256TO511OCTETS_FRAMES_GOOD_BAD_HIGH_INC 0x4000 -#define TX_256TO511OCTETS_FRAMES_GOOD_BAD_HIGH_TYPE REG_TYPE_RO -#define TX_256TO511OCTETS_FRAMES_GOOD_BAD_HIGH_DEFAULT 0x0 - /*[field] TX256_511OCTGBHI*/ - #define TX_256TO511OCTETS_FRAMES_GOOD_BAD_HIGH_TX256_511OCTGBHI - #define TX_256TO511OCTETS_FRAMES_GOOD_BAD_HIGH_TX256_511OCTGBHI_OFFSET 0 - #define TX_256TO511OCTETS_FRAMES_GOOD_BAD_HIGH_TX256_511OCTGBHI_LEN 32 - #define TX_256TO511OCTETS_FRAMES_GOOD_BAD_HIGH_TX256_511OCTGBHI_DEFAULT 0x0 - -struct tx_256to511octets_frames_good_bad_high { - a_uint32_t tx256_511octgbhi:32; -}; - -union tx_256to511octets_frames_good_bad_high_u { - a_uint32_t val; - struct tx_256to511octets_frames_good_bad_high bf; -}; - -/*[register] TX_512TO1023OCTETS_FRAMES_GOOD_BAD_LOW*/ -#define TX_512TO1023OCTETS_FRAMES_GOOD_BAD_LOW -#define TX_512TO1023OCTETS_FRAMES_GOOD_BAD_LOW_ADDRESS 0x854 -#define TX_512TO1023OCTETS_FRAMES_GOOD_BAD_LOW_NUM 1 -#define TX_512TO1023OCTETS_FRAMES_GOOD_BAD_LOW_INC 0x4000 -#define TX_512TO1023OCTETS_FRAMES_GOOD_BAD_LOW_TYPE REG_TYPE_RO -#define TX_512TO1023OCTETS_FRAMES_GOOD_BAD_LOW_DEFAULT 0x0 - /*[field] TX512_1023OCTGBLO*/ - #define TX_512TO1023OCTETS_FRAMES_GOOD_BAD_LOW_TX512_1023OCTGBLO - #define TX_512TO1023OCTETS_FRAMES_GOOD_BAD_LOW_TX512_1023OCTGBLO_OFFSET 0 - #define TX_512TO1023OCTETS_FRAMES_GOOD_BAD_LOW_TX512_1023OCTGBLO_LEN 32 - #define TX_512TO1023OCTETS_FRAMES_GOOD_BAD_LOW_TX512_1023OCTGBLO_DEFAULT 0x0 - -struct tx_512to1023octets_frames_good_bad_low { - a_uint32_t tx512_1023octgblo:32; -}; - -union tx_512to1023octets_frames_good_bad_low_u { - a_uint32_t val; - struct tx_512to1023octets_frames_good_bad_low bf; -}; - -/*[register] TX_512TO1023OCTETS_FRAMES_GOOD_BAD_HIGH*/ -#define TX_512TO1023OCTETS_FRAMES_GOOD_BAD_HIGH -#define TX_512TO1023OCTETS_FRAMES_GOOD_BAD_HIGH_ADDRESS 0x858 -#define TX_512TO1023OCTETS_FRAMES_GOOD_BAD_HIGH_NUM 1 -#define TX_512TO1023OCTETS_FRAMES_GOOD_BAD_HIGH_INC 0x4000 -#define TX_512TO1023OCTETS_FRAMES_GOOD_BAD_HIGH_TYPE REG_TYPE_RO -#define TX_512TO1023OCTETS_FRAMES_GOOD_BAD_HIGH_DEFAULT 0x0 - /*[field] TX512_1023OCTGBHI*/ - #define TX_512TO1023OCTETS_FRAMES_GOOD_BAD_HIGH_TX512_1023OCTGBHI - #define TX_512TO1023OCTETS_FRAMES_GOOD_BAD_HIGH_TX512_1023OCTGBHI_OFFSET 0 - #define TX_512TO1023OCTETS_FRAMES_GOOD_BAD_HIGH_TX512_1023OCTGBHI_LEN 32 - #define TX_512TO1023OCTETS_FRAMES_GOOD_BAD_HIGH_TX512_1023OCTGBHI_DEFAULT 0x0 - -struct tx_512to1023octets_frames_good_bad_high { - a_uint32_t tx512_1023octgbhi:32; -}; - -union tx_512to1023octets_frames_good_bad_high_u { - a_uint32_t val; - struct tx_512to1023octets_frames_good_bad_high bf; -}; - -/*[register] TX_1024TOMAXOCTETS_FRAMES_GOOD_BAD_LOW*/ -#define TX_1024TOMAXOCTETS_FRAMES_GOOD_BAD_LOW -#define TX_1024TOMAXOCTETS_FRAMES_GOOD_BAD_LOW_ADDRESS 0x85c -#define TX_1024TOMAXOCTETS_FRAMES_GOOD_BAD_LOW_NUM 1 -#define TX_1024TOMAXOCTETS_FRAMES_GOOD_BAD_LOW_INC 0x4000 -#define TX_1024TOMAXOCTETS_FRAMES_GOOD_BAD_LOW_TYPE REG_TYPE_RO -#define TX_1024TOMAXOCTETS_FRAMES_GOOD_BAD_LOW_DEFAULT 0x0 - /*[field] TX1024_MAXOCTGBLO*/ - #define TX_1024TOMAXOCTETS_FRAMES_GOOD_BAD_LOW_TX1024_MAXOCTGBLO - #define TX_1024TOMAXOCTETS_FRAMES_GOOD_BAD_LOW_TX1024_MAXOCTGBLO_OFFSET 0 - #define TX_1024TOMAXOCTETS_FRAMES_GOOD_BAD_LOW_TX1024_MAXOCTGBLO_LEN 32 - #define TX_1024TOMAXOCTETS_FRAMES_GOOD_BAD_LOW_TX1024_MAXOCTGBLO_DEFAULT 0x0 - -struct tx_1024tomaxoctets_frames_good_bad_low { - a_uint32_t tx1024_maxoctgblo:32; -}; - -union tx_1024tomaxoctets_frames_good_bad_low_u { - a_uint32_t val; - struct tx_1024tomaxoctets_frames_good_bad_low bf; -}; - -/*[register] TX_1024TOMAXOCTETS_FRAMES_GOOD_BAD_HIGH*/ -#define TX_1024TOMAXOCTETS_FRAMES_GOOD_BAD_HIGH -#define TX_1024TOMAXOCTETS_FRAMES_GOOD_BAD_HIGH_ADDRESS 0x860 -#define TX_1024TOMAXOCTETS_FRAMES_GOOD_BAD_HIGH_NUM 1 -#define TX_1024TOMAXOCTETS_FRAMES_GOOD_BAD_HIGH_INC 0x4000 -#define TX_1024TOMAXOCTETS_FRAMES_GOOD_BAD_HIGH_TYPE REG_TYPE_RO -#define TX_1024TOMAXOCTETS_FRAMES_GOOD_BAD_HIGH_DEFAULT 0x0 - /*[field] TX1024_MAXOCTGBHI*/ - #define TX_1024TOMAXOCTETS_FRAMES_GOOD_BAD_HIGH_TX1024_MAXOCTGBHI - #define TX_1024TOMAXOCTETS_FRAMES_GOOD_BAD_HIGH_TX1024_MAXOCTGBHI_OFFSET 0 - #define TX_1024TOMAXOCTETS_FRAMES_GOOD_BAD_HIGH_TX1024_MAXOCTGBHI_LEN 32 - #define TX_1024TOMAXOCTETS_FRAMES_GOOD_BAD_HIGH_TX1024_MAXOCTGBHI_DEFAULT 0x0 - -struct tx_1024tomaxoctets_frames_good_bad_high { - a_uint32_t tx1024_maxoctgbhi:32; -}; - -union tx_1024tomaxoctets_frames_good_bad_high_u { - a_uint32_t val; - struct tx_1024tomaxoctets_frames_good_bad_high bf; -}; - -/*[register] TX_UNICAST_FRAMES_GOOD_BAD_LOW*/ -#define TX_UNICAST_FRAMES_GOOD_BAD_LOW -#define TX_UNICAST_FRAMES_GOOD_BAD_LOW_ADDRESS 0x864 -#define TX_UNICAST_FRAMES_GOOD_BAD_LOW_NUM 1 -#define TX_UNICAST_FRAMES_GOOD_BAD_LOW_INC 0x4000 -#define TX_UNICAST_FRAMES_GOOD_BAD_LOW_TYPE REG_TYPE_RO -#define TX_UNICAST_FRAMES_GOOD_BAD_LOW_DEFAULT 0x0 - /*[field] TXUCASTGBLO*/ - #define TX_UNICAST_FRAMES_GOOD_BAD_LOW_TXUCASTGBLO - #define TX_UNICAST_FRAMES_GOOD_BAD_LOW_TXUCASTGBLO_OFFSET 0 - #define TX_UNICAST_FRAMES_GOOD_BAD_LOW_TXUCASTGBLO_LEN 32 - #define TX_UNICAST_FRAMES_GOOD_BAD_LOW_TXUCASTGBLO_DEFAULT 0x0 - -struct tx_unicast_frames_good_bad_low { - a_uint32_t txucastgblo:32; -}; - -union tx_unicast_frames_good_bad_low_u { - a_uint32_t val; - struct tx_unicast_frames_good_bad_low bf; -}; - -/*[register] TX_UNICAST_FRAMES_GOOD_BAD_HIGH*/ -#define TX_UNICAST_FRAMES_GOOD_BAD_HIGH -#define TX_UNICAST_FRAMES_GOOD_BAD_HIGH_ADDRESS 0x868 -#define TX_UNICAST_FRAMES_GOOD_BAD_HIGH_NUM 1 -#define TX_UNICAST_FRAMES_GOOD_BAD_HIGH_INC 0x4000 -#define TX_UNICAST_FRAMES_GOOD_BAD_HIGH_TYPE REG_TYPE_RO -#define TX_UNICAST_FRAMES_GOOD_BAD_HIGH_DEFAULT 0x0 - /*[field] TXUCASTGBHI*/ - #define TX_UNICAST_FRAMES_GOOD_BAD_HIGH_TXUCASTGBHI - #define TX_UNICAST_FRAMES_GOOD_BAD_HIGH_TXUCASTGBHI_OFFSET 0 - #define TX_UNICAST_FRAMES_GOOD_BAD_HIGH_TXUCASTGBHI_LEN 32 - #define TX_UNICAST_FRAMES_GOOD_BAD_HIGH_TXUCASTGBHI_DEFAULT 0x0 - -struct tx_unicast_frames_good_bad_high { - a_uint32_t txucastgbhi:32; -}; - -union tx_unicast_frames_good_bad_high_u { - a_uint32_t val; - struct tx_unicast_frames_good_bad_high bf; -}; - -/*[register] TX_MULTICAST_FRAMES_GOOD_BAD_LOW*/ -#define TX_MULTICAST_FRAMES_GOOD_BAD_LOW -#define TX_MULTICAST_FRAMES_GOOD_BAD_LOW_ADDRESS 0x86c -#define TX_MULTICAST_FRAMES_GOOD_BAD_LOW_NUM 1 -#define TX_MULTICAST_FRAMES_GOOD_BAD_LOW_INC 0x4000 -#define TX_MULTICAST_FRAMES_GOOD_BAD_LOW_TYPE REG_TYPE_RO -#define TX_MULTICAST_FRAMES_GOOD_BAD_LOW_DEFAULT 0x0 - /*[field] TXMCASTGBLO*/ - #define TX_MULTICAST_FRAMES_GOOD_BAD_LOW_TXMCASTGBLO - #define TX_MULTICAST_FRAMES_GOOD_BAD_LOW_TXMCASTGBLO_OFFSET 0 - #define TX_MULTICAST_FRAMES_GOOD_BAD_LOW_TXMCASTGBLO_LEN 32 - #define TX_MULTICAST_FRAMES_GOOD_BAD_LOW_TXMCASTGBLO_DEFAULT 0x0 - -struct tx_multicast_frames_good_bad_low { - a_uint32_t txmcastgblo:32; -}; - -union tx_multicast_frames_good_bad_low_u { - a_uint32_t val; - struct tx_multicast_frames_good_bad_low bf; -}; - -/*[register] TX_MULTICAST_FRAMES_GOOD_BAD_HIGH*/ -#define TX_MULTICAST_FRAMES_GOOD_BAD_HIGH -#define TX_MULTICAST_FRAMES_GOOD_BAD_HIGH_ADDRESS 0x870 -#define TX_MULTICAST_FRAMES_GOOD_BAD_HIGH_NUM 1 -#define TX_MULTICAST_FRAMES_GOOD_BAD_HIGH_INC 0x4000 -#define TX_MULTICAST_FRAMES_GOOD_BAD_HIGH_TYPE REG_TYPE_RO -#define TX_MULTICAST_FRAMES_GOOD_BAD_HIGH_DEFAULT 0x0 - /*[field] TXMCASTGBHI*/ - #define TX_MULTICAST_FRAMES_GOOD_BAD_HIGH_TXMCASTGBHI - #define TX_MULTICAST_FRAMES_GOOD_BAD_HIGH_TXMCASTGBHI_OFFSET 0 - #define TX_MULTICAST_FRAMES_GOOD_BAD_HIGH_TXMCASTGBHI_LEN 32 - #define TX_MULTICAST_FRAMES_GOOD_BAD_HIGH_TXMCASTGBHI_DEFAULT 0x0 - -struct tx_multicast_frames_good_bad_high { - a_uint32_t txmcastgbhi:32; -}; - -union tx_multicast_frames_good_bad_high_u { - a_uint32_t val; - struct tx_multicast_frames_good_bad_high bf; -}; - -/*[register] TX_BROADCAST_FRAMES_GOOD_BAD_LOW*/ -#define TX_BROADCAST_FRAMES_GOOD_BAD_LOW -#define TX_BROADCAST_FRAMES_GOOD_BAD_LOW_ADDRESS 0x874 -#define TX_BROADCAST_FRAMES_GOOD_BAD_LOW_NUM 1 -#define TX_BROADCAST_FRAMES_GOOD_BAD_LOW_INC 0x4000 -#define TX_BROADCAST_FRAMES_GOOD_BAD_LOW_TYPE REG_TYPE_RO -#define TX_BROADCAST_FRAMES_GOOD_BAD_LOW_DEFAULT 0x0 - /*[field] TXBCASTGBLO*/ - #define TX_BROADCAST_FRAMES_GOOD_BAD_LOW_TXBCASTGBLO - #define TX_BROADCAST_FRAMES_GOOD_BAD_LOW_TXBCASTGBLO_OFFSET 0 - #define TX_BROADCAST_FRAMES_GOOD_BAD_LOW_TXBCASTGBLO_LEN 32 - #define TX_BROADCAST_FRAMES_GOOD_BAD_LOW_TXBCASTGBLO_DEFAULT 0x0 - -struct tx_broadcast_frames_good_bad_low { - a_uint32_t txbcastgblo:32; -}; - -union tx_broadcast_frames_good_bad_low_u { - a_uint32_t val; - struct tx_broadcast_frames_good_bad_low bf; -}; - -/*[register] TX_BROADCAST_FRAMES_GOOD_BAD_HIGH*/ -#define TX_BROADCAST_FRAMES_GOOD_BAD_HIGH -#define TX_BROADCAST_FRAMES_GOOD_BAD_HIGH_ADDRESS 0x878 -#define TX_BROADCAST_FRAMES_GOOD_BAD_HIGH_NUM 1 -#define TX_BROADCAST_FRAMES_GOOD_BAD_HIGH_INC 0x4000 -#define TX_BROADCAST_FRAMES_GOOD_BAD_HIGH_TYPE REG_TYPE_RO -#define TX_BROADCAST_FRAMES_GOOD_BAD_HIGH_DEFAULT 0x0 - /*[field] TXBCASTGBHI*/ - #define TX_BROADCAST_FRAMES_GOOD_BAD_HIGH_TXBCASTGBHI - #define TX_BROADCAST_FRAMES_GOOD_BAD_HIGH_TXBCASTGBHI_OFFSET 0 - #define TX_BROADCAST_FRAMES_GOOD_BAD_HIGH_TXBCASTGBHI_LEN 32 - #define TX_BROADCAST_FRAMES_GOOD_BAD_HIGH_TXBCASTGBHI_DEFAULT 0x0 - -struct tx_broadcast_frames_good_bad_high { - a_uint32_t txbcastgbhi:32; -}; - -union tx_broadcast_frames_good_bad_high_u { - a_uint32_t val; - struct tx_broadcast_frames_good_bad_high bf; -}; - -/*[register] TX_UNDERFLOW_ERROR_FRAMES_LOW*/ -#define TX_UNDERFLOW_ERROR_FRAMES_LOW -#define TX_UNDERFLOW_ERROR_FRAMES_LOW_ADDRESS 0x87c -#define TX_UNDERFLOW_ERROR_FRAMES_LOW_NUM 1 -#define TX_UNDERFLOW_ERROR_FRAMES_LOW_INC 0x4000 -#define TX_UNDERFLOW_ERROR_FRAMES_LOW_TYPE REG_TYPE_RO -#define TX_UNDERFLOW_ERROR_FRAMES_LOW_DEFAULT 0x0 - /*[field] TXUNDRFLWLO*/ - #define TX_UNDERFLOW_ERROR_FRAMES_LOW_TXUNDRFLWLO - #define TX_UNDERFLOW_ERROR_FRAMES_LOW_TXUNDRFLWLO_OFFSET 0 - #define TX_UNDERFLOW_ERROR_FRAMES_LOW_TXUNDRFLWLO_LEN 32 - #define TX_UNDERFLOW_ERROR_FRAMES_LOW_TXUNDRFLWLO_DEFAULT 0x0 - -struct tx_underflow_error_frames_low { - a_uint32_t txundrflwlo:32; -}; - -union tx_underflow_error_frames_low_u { - a_uint32_t val; - struct tx_underflow_error_frames_low bf; -}; - -/*[register] TX_UNDERFLOW_ERROR_FRAMES_HIGH*/ -#define TX_UNDERFLOW_ERROR_FRAMES_HIGH -#define TX_UNDERFLOW_ERROR_FRAMES_HIGH_ADDRESS 0x880 -#define TX_UNDERFLOW_ERROR_FRAMES_HIGH_NUM 1 -#define TX_UNDERFLOW_ERROR_FRAMES_HIGH_INC 0x4000 -#define TX_UNDERFLOW_ERROR_FRAMES_HIGH_TYPE REG_TYPE_RO -#define TX_UNDERFLOW_ERROR_FRAMES_HIGH_DEFAULT 0x0 - /*[field] TXUNDRFLWHI*/ - #define TX_UNDERFLOW_ERROR_FRAMES_HIGH_TXUNDRFLWHI - #define TX_UNDERFLOW_ERROR_FRAMES_HIGH_TXUNDRFLWHI_OFFSET 0 - #define TX_UNDERFLOW_ERROR_FRAMES_HIGH_TXUNDRFLWHI_LEN 32 - #define TX_UNDERFLOW_ERROR_FRAMES_HIGH_TXUNDRFLWHI_DEFAULT 0x0 - -struct tx_underflow_error_frames_high { - a_uint32_t txundrflwhi:32; -}; - -union tx_underflow_error_frames_high_u { - a_uint32_t val; - struct tx_underflow_error_frames_high bf; -}; - -/*[register] TX_OCTET_COUNT_GOOD_LOW*/ -#define TX_OCTET_COUNT_GOOD_LOW -#define TX_OCTET_COUNT_GOOD_LOW_ADDRESS 0x884 -#define TX_OCTET_COUNT_GOOD_LOW_NUM 1 -#define TX_OCTET_COUNT_GOOD_LOW_INC 0x4000 -#define TX_OCTET_COUNT_GOOD_LOW_TYPE REG_TYPE_RO -#define TX_OCTET_COUNT_GOOD_LOW_DEFAULT 0x0 - /*[field] TXOCTGLO*/ - #define TX_OCTET_COUNT_GOOD_LOW_TXOCTGLO - #define TX_OCTET_COUNT_GOOD_LOW_TXOCTGLO_OFFSET 0 - #define TX_OCTET_COUNT_GOOD_LOW_TXOCTGLO_LEN 32 - #define TX_OCTET_COUNT_GOOD_LOW_TXOCTGLO_DEFAULT 0x0 - -struct tx_octet_count_good_low { - a_uint32_t txoctglo:32; -}; - -union tx_octet_count_good_low_u { - a_uint32_t val; - struct tx_octet_count_good_low bf; -}; - -/*[register] TX_OCTET_COUNT_GOOD_HIGH*/ -#define TX_OCTET_COUNT_GOOD_HIGH -#define TX_OCTET_COUNT_GOOD_HIGH_ADDRESS 0x888 -#define TX_OCTET_COUNT_GOOD_HIGH_NUM 1 -#define TX_OCTET_COUNT_GOOD_HIGH_INC 0x4000 -#define TX_OCTET_COUNT_GOOD_HIGH_TYPE REG_TYPE_RO -#define TX_OCTET_COUNT_GOOD_HIGH_DEFAULT 0x0 - /*[field] TXOCTGHI*/ - #define TX_OCTET_COUNT_GOOD_HIGH_TXOCTGHI - #define TX_OCTET_COUNT_GOOD_HIGH_TXOCTGHI_OFFSET 0 - #define TX_OCTET_COUNT_GOOD_HIGH_TXOCTGHI_LEN 32 - #define TX_OCTET_COUNT_GOOD_HIGH_TXOCTGHI_DEFAULT 0x0 - -struct tx_octet_count_good_high { - a_uint32_t txoctghi:32; -}; - -union tx_octet_count_good_high_u { - a_uint32_t val; - struct tx_octet_count_good_high bf; -}; - -/*[register] TX_FRAME_COUNT_GOOD_LOW*/ -#define TX_FRAME_COUNT_GOOD_LOW -#define TX_FRAME_COUNT_GOOD_LOW_ADDRESS 0x88c -#define TX_FRAME_COUNT_GOOD_LOW_NUM 1 -#define TX_FRAME_COUNT_GOOD_LOW_INC 0x4000 -#define TX_FRAME_COUNT_GOOD_LOW_TYPE REG_TYPE_RO -#define TX_FRAME_COUNT_GOOD_LOW_DEFAULT 0x0 - /*[field] TXFRMGLO*/ - #define TX_FRAME_COUNT_GOOD_LOW_TXFRMGLO - #define TX_FRAME_COUNT_GOOD_LOW_TXFRMGLO_OFFSET 0 - #define TX_FRAME_COUNT_GOOD_LOW_TXFRMGLO_LEN 32 - #define TX_FRAME_COUNT_GOOD_LOW_TXFRMGLO_DEFAULT 0x0 - -struct tx_frame_count_good_low { - a_uint32_t txfrmglo:32; -}; - -union tx_frame_count_good_low_u { - a_uint32_t val; - struct tx_frame_count_good_low bf; -}; - -/*[register] TX_FRAME_COUNT_GOOD_HIGH*/ -#define TX_FRAME_COUNT_GOOD_HIGH -#define TX_FRAME_COUNT_GOOD_HIGH_ADDRESS 0x890 -#define TX_FRAME_COUNT_GOOD_HIGH_NUM 1 -#define TX_FRAME_COUNT_GOOD_HIGH_INC 0x4000 -#define TX_FRAME_COUNT_GOOD_HIGH_TYPE REG_TYPE_RO -#define TX_FRAME_COUNT_GOOD_HIGH_DEFAULT 0x0 - /*[field] TXFRMGHI*/ - #define TX_FRAME_COUNT_GOOD_HIGH_TXFRMGHI - #define TX_FRAME_COUNT_GOOD_HIGH_TXFRMGHI_OFFSET 0 - #define TX_FRAME_COUNT_GOOD_HIGH_TXFRMGHI_LEN 32 - #define TX_FRAME_COUNT_GOOD_HIGH_TXFRMGHI_DEFAULT 0x0 - -struct tx_frame_count_good_high { - a_uint32_t txfrmghi:32; -}; - -union tx_frame_count_good_high_u { - a_uint32_t val; - struct tx_frame_count_good_high bf; -}; - -/*[register] TX_PAUSE_FRAMES_LOW*/ -#define TX_PAUSE_FRAMES_LOW -#define TX_PAUSE_FRAMES_LOW_ADDRESS 0x894 -#define TX_PAUSE_FRAMES_LOW_NUM 1 -#define TX_PAUSE_FRAMES_LOW_INC 0x4000 -#define TX_PAUSE_FRAMES_LOW_TYPE REG_TYPE_RO -#define TX_PAUSE_FRAMES_LOW_DEFAULT 0x0 - /*[field] TXPAUSEGLO*/ - #define TX_PAUSE_FRAMES_LOW_TXPAUSEGLO - #define TX_PAUSE_FRAMES_LOW_TXPAUSEGLO_OFFSET 0 - #define TX_PAUSE_FRAMES_LOW_TXPAUSEGLO_LEN 32 - #define TX_PAUSE_FRAMES_LOW_TXPAUSEGLO_DEFAULT 0x0 - -struct tx_pause_frames_low { - a_uint32_t txpauseglo:32; -}; - -union tx_pause_frames_low_u { - a_uint32_t val; - struct tx_pause_frames_low bf; -}; - -/*[register] TX_PAUSE_FRAMES_HIGH*/ -#define TX_PAUSE_FRAMES_HIGH -#define TX_PAUSE_FRAMES_HIGH_ADDRESS 0x898 -#define TX_PAUSE_FRAMES_HIGH_NUM 1 -#define TX_PAUSE_FRAMES_HIGH_INC 0x4000 -#define TX_PAUSE_FRAMES_HIGH_TYPE REG_TYPE_RO -#define TX_PAUSE_FRAMES_HIGH_DEFAULT 0x0 - /*[field] TXPAUSEGHI*/ - #define TX_PAUSE_FRAMES_HIGH_TXPAUSEGHI - #define TX_PAUSE_FRAMES_HIGH_TXPAUSEGHI_OFFSET 0 - #define TX_PAUSE_FRAMES_HIGH_TXPAUSEGHI_LEN 32 - #define TX_PAUSE_FRAMES_HIGH_TXPAUSEGHI_DEFAULT 0x0 - -struct tx_pause_frames_high { - a_uint32_t txpauseghi:32; -}; - -union tx_pause_frames_high_u { - a_uint32_t val; - struct tx_pause_frames_high bf; -}; - -/*[register] TX_VLAN_FRAMES_GOOD_LOW*/ -#define TX_VLAN_FRAMES_GOOD_LOW -#define TX_VLAN_FRAMES_GOOD_LOW_ADDRESS 0x89c -#define TX_VLAN_FRAMES_GOOD_LOW_NUM 1 -#define TX_VLAN_FRAMES_GOOD_LOW_INC 0x4000 -#define TX_VLAN_FRAMES_GOOD_LOW_TYPE REG_TYPE_RO -#define TX_VLAN_FRAMES_GOOD_LOW_DEFAULT 0x0 - /*[field] TXVLANGLO*/ - #define TX_VLAN_FRAMES_GOOD_LOW_TXVLANGLO - #define TX_VLAN_FRAMES_GOOD_LOW_TXVLANGLO_OFFSET 0 - #define TX_VLAN_FRAMES_GOOD_LOW_TXVLANGLO_LEN 32 - #define TX_VLAN_FRAMES_GOOD_LOW_TXVLANGLO_DEFAULT 0x0 - -struct tx_vlan_frames_good_low { - a_uint32_t txvlanglo:32; -}; - -union tx_vlan_frames_good_low_u { - a_uint32_t val; - struct tx_vlan_frames_good_low bf; -}; - -/*[register] TX_VLAN_FRAMES_GOOD_HIGH*/ -#define TX_VLAN_FRAMES_GOOD_HIGH -#define TX_VLAN_FRAMES_GOOD_HIGH_ADDRESS 0x8a0 -#define TX_VLAN_FRAMES_GOOD_HIGH_NUM 1 -#define TX_VLAN_FRAMES_GOOD_HIGH_INC 0x4000 -#define TX_VLAN_FRAMES_GOOD_HIGH_TYPE REG_TYPE_RO -#define TX_VLAN_FRAMES_GOOD_HIGH_DEFAULT 0x0 - /*[field] TXVLANGHI*/ - #define TX_VLAN_FRAMES_GOOD_HIGH_TXVLANGHI - #define TX_VLAN_FRAMES_GOOD_HIGH_TXVLANGHI_OFFSET 0 - #define TX_VLAN_FRAMES_GOOD_HIGH_TXVLANGHI_LEN 32 - #define TX_VLAN_FRAMES_GOOD_HIGH_TXVLANGHI_DEFAULT 0x0 - -struct tx_vlan_frames_good_high { - a_uint32_t txvlanghi:32; -}; - -union tx_vlan_frames_good_high_u { - a_uint32_t val; - struct tx_vlan_frames_good_high bf; -}; - -/*[register] TX_LPI_USEC_CNTR*/ -#define TX_LPI_USEC_CNTR -#define TX_LPI_USEC_CNTR_ADDRESS 0x8a4 -#define TX_LPI_USEC_CNTR_NUM 1 -#define TX_LPI_USEC_CNTR_INC 0x4000 -#define TX_LPI_USEC_CNTR_TYPE REG_TYPE_RO -#define TX_LPI_USEC_CNTR_DEFAULT 0x0 - /*[field] TXLPIUSC*/ - #define TX_LPI_USEC_CNTR_TXLPIUSC - #define TX_LPI_USEC_CNTR_TXLPIUSC_OFFSET 0 - #define TX_LPI_USEC_CNTR_TXLPIUSC_LEN 32 - #define TX_LPI_USEC_CNTR_TXLPIUSC_DEFAULT 0x0 - -struct tx_lpi_usec_cntr { - a_uint32_t txlpiusc:32; -}; - -union tx_lpi_usec_cntr_u { - a_uint32_t val; - struct tx_lpi_usec_cntr bf; -}; - -/*[register] TX_LPI_TRAN_CNTR*/ -#define TX_LPI_TRAN_CNTR -#define TX_LPI_TRAN_CNTR_ADDRESS 0x8a8 -#define TX_LPI_TRAN_CNTR_NUM 1 -#define TX_LPI_TRAN_CNTR_INC 0x4000 -#define TX_LPI_TRAN_CNTR_TYPE REG_TYPE_RO -#define TX_LPI_TRAN_CNTR_DEFAULT 0x0 - /*[field] TXLPITRC*/ - #define TX_LPI_TRAN_CNTR_TXLPITRC - #define TX_LPI_TRAN_CNTR_TXLPITRC_OFFSET 0 - #define TX_LPI_TRAN_CNTR_TXLPITRC_LEN 32 - #define TX_LPI_TRAN_CNTR_TXLPITRC_DEFAULT 0x0 - -struct tx_lpi_tran_cntr { - a_uint32_t txlpitrc:32; -}; - -union tx_lpi_tran_cntr_u { - a_uint32_t val; - struct tx_lpi_tran_cntr bf; -}; - -/*[register] RX_FRAME_COUNT_GOOD_BAD_LOW*/ -#define RX_FRAME_COUNT_GOOD_BAD_LOW -#define RX_FRAME_COUNT_GOOD_BAD_LOW_ADDRESS 0x900 -#define RX_FRAME_COUNT_GOOD_BAD_LOW_NUM 1 -#define RX_FRAME_COUNT_GOOD_BAD_LOW_INC 0x4000 -#define RX_FRAME_COUNT_GOOD_BAD_LOW_TYPE REG_TYPE_RO -#define RX_FRAME_COUNT_GOOD_BAD_LOW_DEFAULT 0x0 - /*[field] RXFRMGBLO*/ - #define RX_FRAME_COUNT_GOOD_BAD_LOW_RXFRMGBLO - #define RX_FRAME_COUNT_GOOD_BAD_LOW_RXFRMGBLO_OFFSET 0 - #define RX_FRAME_COUNT_GOOD_BAD_LOW_RXFRMGBLO_LEN 32 - #define RX_FRAME_COUNT_GOOD_BAD_LOW_RXFRMGBLO_DEFAULT 0x0 - -struct rx_frame_count_good_bad_low { - a_uint32_t rxfrmgblo:32; -}; - -union rx_frame_count_good_bad_low_u { - a_uint32_t val; - struct rx_frame_count_good_bad_low bf; -}; - -/*[register] RX_FRAME_COUNT_GOOD_BAD_HIGH*/ -#define RX_FRAME_COUNT_GOOD_BAD_HIGH -#define RX_FRAME_COUNT_GOOD_BAD_HIGH_ADDRESS 0x904 -#define RX_FRAME_COUNT_GOOD_BAD_HIGH_NUM 1 -#define RX_FRAME_COUNT_GOOD_BAD_HIGH_INC 0x4000 -#define RX_FRAME_COUNT_GOOD_BAD_HIGH_TYPE REG_TYPE_RO -#define RX_FRAME_COUNT_GOOD_BAD_HIGH_DEFAULT 0x0 - /*[field] RXFRMGBHI*/ - #define RX_FRAME_COUNT_GOOD_BAD_HIGH_RXFRMGBHI - #define RX_FRAME_COUNT_GOOD_BAD_HIGH_RXFRMGBHI_OFFSET 0 - #define RX_FRAME_COUNT_GOOD_BAD_HIGH_RXFRMGBHI_LEN 32 - #define RX_FRAME_COUNT_GOOD_BAD_HIGH_RXFRMGBHI_DEFAULT 0x0 - -struct rx_frame_count_good_bad_high { - a_uint32_t rxfrmgbhi:32; -}; - -union rx_frame_count_good_bad_high_u { - a_uint32_t val; - struct rx_frame_count_good_bad_high bf; -}; - -/*[register] RX_OCTET_COUNT_GOOD_BAD_LOW*/ -#define RX_OCTET_COUNT_GOOD_BAD_LOW -#define RX_OCTET_COUNT_GOOD_BAD_LOW_ADDRESS 0x908 -#define RX_OCTET_COUNT_GOOD_BAD_LOW_NUM 1 -#define RX_OCTET_COUNT_GOOD_BAD_LOW_INC 0x4000 -#define RX_OCTET_COUNT_GOOD_BAD_LOW_TYPE REG_TYPE_RO -#define RX_OCTET_COUNT_GOOD_BAD_LOW_DEFAULT 0x0 - /*[field] RXOCTGBLO*/ - #define RX_OCTET_COUNT_GOOD_BAD_LOW_RXOCTGBLO - #define RX_OCTET_COUNT_GOOD_BAD_LOW_RXOCTGBLO_OFFSET 0 - #define RX_OCTET_COUNT_GOOD_BAD_LOW_RXOCTGBLO_LEN 32 - #define RX_OCTET_COUNT_GOOD_BAD_LOW_RXOCTGBLO_DEFAULT 0x0 - -struct rx_octet_count_good_bad_low { - a_uint32_t rxoctgblo:32; -}; - -union rx_octet_count_good_bad_low_u { - a_uint32_t val; - struct rx_octet_count_good_bad_low bf; -}; - -/*[register] RX_OCTET_COUNT_GOOD_BAD_HIGH*/ -#define RX_OCTET_COUNT_GOOD_BAD_HIGH -#define RX_OCTET_COUNT_GOOD_BAD_HIGH_ADDRESS 0x90c -#define RX_OCTET_COUNT_GOOD_BAD_HIGH_NUM 1 -#define RX_OCTET_COUNT_GOOD_BAD_HIGH_INC 0x4000 -#define RX_OCTET_COUNT_GOOD_BAD_HIGH_TYPE REG_TYPE_RO -#define RX_OCTET_COUNT_GOOD_BAD_HIGH_DEFAULT 0x0 - /*[field] RXOCTGBHI*/ - #define RX_OCTET_COUNT_GOOD_BAD_HIGH_RXOCTGBHI - #define RX_OCTET_COUNT_GOOD_BAD_HIGH_RXOCTGBHI_OFFSET 0 - #define RX_OCTET_COUNT_GOOD_BAD_HIGH_RXOCTGBHI_LEN 32 - #define RX_OCTET_COUNT_GOOD_BAD_HIGH_RXOCTGBHI_DEFAULT 0x0 - -struct rx_octet_count_good_bad_high { - a_uint32_t rxoctgbhi:32; -}; - -union rx_octet_count_good_bad_high_u { - a_uint32_t val; - struct rx_octet_count_good_bad_high bf; -}; - -/*[register] RX_OCTET_COUNT_GOOD_LOW*/ -#define RX_OCTET_COUNT_GOOD_LOW -#define RX_OCTET_COUNT_GOOD_LOW_ADDRESS 0x910 -#define RX_OCTET_COUNT_GOOD_LOW_NUM 1 -#define RX_OCTET_COUNT_GOOD_LOW_INC 0x4000 -#define RX_OCTET_COUNT_GOOD_LOW_TYPE REG_TYPE_RO -#define RX_OCTET_COUNT_GOOD_LOW_DEFAULT 0x0 - /*[field] RXOCTGLO*/ - #define RX_OCTET_COUNT_GOOD_LOW_RXOCTGLO - #define RX_OCTET_COUNT_GOOD_LOW_RXOCTGLO_OFFSET 0 - #define RX_OCTET_COUNT_GOOD_LOW_RXOCTGLO_LEN 32 - #define RX_OCTET_COUNT_GOOD_LOW_RXOCTGLO_DEFAULT 0x0 - -struct rx_octet_count_good_low { - a_uint32_t rxoctglo:32; -}; - -union rx_octet_count_good_low_u { - a_uint32_t val; - struct rx_octet_count_good_low bf; -}; - -/*[register] RX_OCTET_COUNT_GOOD_HIGH*/ -#define RX_OCTET_COUNT_GOOD_HIGH -#define RX_OCTET_COUNT_GOOD_HIGH_ADDRESS 0x914 -#define RX_OCTET_COUNT_GOOD_HIGH_NUM 1 -#define RX_OCTET_COUNT_GOOD_HIGH_INC 0x4000 -#define RX_OCTET_COUNT_GOOD_HIGH_TYPE REG_TYPE_RO -#define RX_OCTET_COUNT_GOOD_HIGH_DEFAULT 0x0 - /*[field] RXOCTGHI*/ - #define RX_OCTET_COUNT_GOOD_HIGH_RXOCTGHI - #define RX_OCTET_COUNT_GOOD_HIGH_RXOCTGHI_OFFSET 0 - #define RX_OCTET_COUNT_GOOD_HIGH_RXOCTGHI_LEN 32 - #define RX_OCTET_COUNT_GOOD_HIGH_RXOCTGHI_DEFAULT 0x0 - -struct rx_octet_count_good_high { - a_uint32_t rxoctghi:32; -}; - -union rx_octet_count_good_high_u { - a_uint32_t val; - struct rx_octet_count_good_high bf; -}; - -/*[register] RX_BROADCAST_FRAMES_GOOD_LOW*/ -#define RX_BROADCAST_FRAMES_GOOD_LOW -#define RX_BROADCAST_FRAMES_GOOD_LOW_ADDRESS 0x918 -#define RX_BROADCAST_FRAMES_GOOD_LOW_NUM 1 -#define RX_BROADCAST_FRAMES_GOOD_LOW_INC 0x4000 -#define RX_BROADCAST_FRAMES_GOOD_LOW_TYPE REG_TYPE_RO -#define RX_BROADCAST_FRAMES_GOOD_LOW_DEFAULT 0x0 - /*[field] RXBCASTGLO*/ - #define RX_BROADCAST_FRAMES_GOOD_LOW_RXBCASTGLO - #define RX_BROADCAST_FRAMES_GOOD_LOW_RXBCASTGLO_OFFSET 0 - #define RX_BROADCAST_FRAMES_GOOD_LOW_RXBCASTGLO_LEN 32 - #define RX_BROADCAST_FRAMES_GOOD_LOW_RXBCASTGLO_DEFAULT 0x0 - -struct rx_broadcast_frames_good_low { - a_uint32_t rxbcastglo:32; -}; - -union rx_broadcast_frames_good_low_u { - a_uint32_t val; - struct rx_broadcast_frames_good_low bf; -}; - -/*[register] RX_BROADCAST_FRAMES_GOOD_HIGH*/ -#define RX_BROADCAST_FRAMES_GOOD_HIGH -#define RX_BROADCAST_FRAMES_GOOD_HIGH_ADDRESS 0x91c -#define RX_BROADCAST_FRAMES_GOOD_HIGH_NUM 1 -#define RX_BROADCAST_FRAMES_GOOD_HIGH_INC 0x4000 -#define RX_BROADCAST_FRAMES_GOOD_HIGH_TYPE REG_TYPE_RO -#define RX_BROADCAST_FRAMES_GOOD_HIGH_DEFAULT 0x0 - /*[field] RXBCASTGHI*/ - #define RX_BROADCAST_FRAMES_GOOD_HIGH_RXBCASTGHI - #define RX_BROADCAST_FRAMES_GOOD_HIGH_RXBCASTGHI_OFFSET 0 - #define RX_BROADCAST_FRAMES_GOOD_HIGH_RXBCASTGHI_LEN 32 - #define RX_BROADCAST_FRAMES_GOOD_HIGH_RXBCASTGHI_DEFAULT 0x0 - -struct rx_broadcast_frames_good_high { - a_uint32_t rxbcastghi:32; -}; - -union rx_broadcast_frames_good_high_u { - a_uint32_t val; - struct rx_broadcast_frames_good_high bf; -}; - -/*[register] RX_MULTICAST_FRAMES_GOOD_LOW*/ -#define RX_MULTICAST_FRAMES_GOOD_LOW -#define RX_MULTICAST_FRAMES_GOOD_LOW_ADDRESS 0x920 -#define RX_MULTICAST_FRAMES_GOOD_LOW_NUM 1 -#define RX_MULTICAST_FRAMES_GOOD_LOW_INC 0x4000 -#define RX_MULTICAST_FRAMES_GOOD_LOW_TYPE REG_TYPE_RO -#define RX_MULTICAST_FRAMES_GOOD_LOW_DEFAULT 0x0 - /*[field] RXMCASTGLO*/ - #define RX_MULTICAST_FRAMES_GOOD_LOW_RXMCASTGLO - #define RX_MULTICAST_FRAMES_GOOD_LOW_RXMCASTGLO_OFFSET 0 - #define RX_MULTICAST_FRAMES_GOOD_LOW_RXMCASTGLO_LEN 32 - #define RX_MULTICAST_FRAMES_GOOD_LOW_RXMCASTGLO_DEFAULT 0x0 - -struct rx_multicast_frames_good_low { - a_uint32_t rxmcastglo:32; -}; - -union rx_multicast_frames_good_low_u { - a_uint32_t val; - struct rx_multicast_frames_good_low bf; -}; - -/*[register] RX_MULTICAST_FRAMES_GOOD_HIGH*/ -#define RX_MULTICAST_FRAMES_GOOD_HIGH -#define RX_MULTICAST_FRAMES_GOOD_HIGH_ADDRESS 0x924 -#define RX_MULTICAST_FRAMES_GOOD_HIGH_NUM 1 -#define RX_MULTICAST_FRAMES_GOOD_HIGH_INC 0x4000 -#define RX_MULTICAST_FRAMES_GOOD_HIGH_TYPE REG_TYPE_RO -#define RX_MULTICAST_FRAMES_GOOD_HIGH_DEFAULT 0x0 - /*[field] RXMCASTGHI*/ - #define RX_MULTICAST_FRAMES_GOOD_HIGH_RXMCASTGHI - #define RX_MULTICAST_FRAMES_GOOD_HIGH_RXMCASTGHI_OFFSET 0 - #define RX_MULTICAST_FRAMES_GOOD_HIGH_RXMCASTGHI_LEN 32 - #define RX_MULTICAST_FRAMES_GOOD_HIGH_RXMCASTGHI_DEFAULT 0x0 - -struct rx_multicast_frames_good_high { - a_uint32_t rxmcastghi:32; -}; - -union rx_multicast_frames_good_high_u { - a_uint32_t val; - struct rx_multicast_frames_good_high bf; -}; - -/*[register] RX_CRC_ERROR_FRAMES_LOW*/ -#define RX_CRC_ERROR_FRAMES_LOW -#define RX_CRC_ERROR_FRAMES_LOW_ADDRESS 0x928 -#define RX_CRC_ERROR_FRAMES_LOW_NUM 1 -#define RX_CRC_ERROR_FRAMES_LOW_INC 0x4000 -#define RX_CRC_ERROR_FRAMES_LOW_TYPE REG_TYPE_RO -#define RX_CRC_ERROR_FRAMES_LOW_DEFAULT 0x0 - /*[field] RXCRCERLO*/ - #define RX_CRC_ERROR_FRAMES_LOW_RXCRCERLO - #define RX_CRC_ERROR_FRAMES_LOW_RXCRCERLO_OFFSET 0 - #define RX_CRC_ERROR_FRAMES_LOW_RXCRCERLO_LEN 32 - #define RX_CRC_ERROR_FRAMES_LOW_RXCRCERLO_DEFAULT 0x0 - -struct rx_crc_error_frames_low { - a_uint32_t rxcrcerlo:32; -}; - -union rx_crc_error_frames_low_u { - a_uint32_t val; - struct rx_crc_error_frames_low bf; -}; - -/*[register] RX_CRC_ERROR_FRAMES_HIGH*/ -#define RX_CRC_ERROR_FRAMES_HIGH -#define RX_CRC_ERROR_FRAMES_HIGH_ADDRESS 0x92c -#define RX_CRC_ERROR_FRAMES_HIGH_NUM 1 -#define RX_CRC_ERROR_FRAMES_HIGH_INC 0x4000 -#define RX_CRC_ERROR_FRAMES_HIGH_TYPE REG_TYPE_RO -#define RX_CRC_ERROR_FRAMES_HIGH_DEFAULT 0x0 - /*[field] RXCRCERHI*/ - #define RX_CRC_ERROR_FRAMES_HIGH_RXCRCERHI - #define RX_CRC_ERROR_FRAMES_HIGH_RXCRCERHI_OFFSET 0 - #define RX_CRC_ERROR_FRAMES_HIGH_RXCRCERHI_LEN 32 - #define RX_CRC_ERROR_FRAMES_HIGH_RXCRCERHI_DEFAULT 0x0 - -struct rx_crc_error_frames_high { - a_uint32_t rxcrcerhi:32; -}; - -union rx_crc_error_frames_high_u { - a_uint32_t val; - struct rx_crc_error_frames_high bf; -}; - -/*[register] RX_RUNT_ERROR_FRAMES*/ -#define RX_RUNT_ERROR_FRAMES -#define RX_RUNT_ERROR_FRAMES_ADDRESS 0x930 -#define RX_RUNT_ERROR_FRAMES_NUM 1 -#define RX_RUNT_ERROR_FRAMES_INC 0x4000 -#define RX_RUNT_ERROR_FRAMES_TYPE REG_TYPE_RO -#define RX_RUNT_ERROR_FRAMES_DEFAULT 0x0 - /*[field] RXRUNTER*/ - #define RX_RUNT_ERROR_FRAMES_RXRUNTER - #define RX_RUNT_ERROR_FRAMES_RXRUNTER_OFFSET 0 - #define RX_RUNT_ERROR_FRAMES_RXRUNTER_LEN 32 - #define RX_RUNT_ERROR_FRAMES_RXRUNTER_DEFAULT 0x0 - -struct rx_runt_error_frames { - a_uint32_t rxrunter:32; -}; - -union rx_runt_error_frames_u { - a_uint32_t val; - struct rx_runt_error_frames bf; -}; - -/*[register] RX_JABBER_ERROR_FRAMES*/ -#define RX_JABBER_ERROR_FRAMES -#define RX_JABBER_ERROR_FRAMES_ADDRESS 0x934 -#define RX_JABBER_ERROR_FRAMES_NUM 1 -#define RX_JABBER_ERROR_FRAMES_INC 0x4000 -#define RX_JABBER_ERROR_FRAMES_TYPE REG_TYPE_RO -#define RX_JABBER_ERROR_FRAMES_DEFAULT 0x0 - /*[field] RXJABERER*/ - #define RX_JABBER_ERROR_FRAMES_RXJABERER - #define RX_JABBER_ERROR_FRAMES_RXJABERER_OFFSET 0 - #define RX_JABBER_ERROR_FRAMES_RXJABERER_LEN 32 - #define RX_JABBER_ERROR_FRAMES_RXJABERER_DEFAULT 0x0 - -struct rx_jabber_error_frames { - a_uint32_t rxjaberer:32; -}; - -union rx_jabber_error_frames_u { - a_uint32_t val; - struct rx_jabber_error_frames bf; -}; - -/*[register] RX_UNDERSIZE_FRAMES_GOOD*/ -#define RX_UNDERSIZE_FRAMES_GOOD -#define RX_UNDERSIZE_FRAMES_GOOD_ADDRESS 0x938 -#define RX_UNDERSIZE_FRAMES_GOOD_NUM 1 -#define RX_UNDERSIZE_FRAMES_GOOD_INC 0x4000 -#define RX_UNDERSIZE_FRAMES_GOOD_TYPE REG_TYPE_RO -#define RX_UNDERSIZE_FRAMES_GOOD_DEFAULT 0x0 - /*[field] RXUSIZEG*/ - #define RX_UNDERSIZE_FRAMES_GOOD_RXUSIZEG - #define RX_UNDERSIZE_FRAMES_GOOD_RXUSIZEG_OFFSET 0 - #define RX_UNDERSIZE_FRAMES_GOOD_RXUSIZEG_LEN 32 - #define RX_UNDERSIZE_FRAMES_GOOD_RXUSIZEG_DEFAULT 0x0 - -struct rx_undersize_frames_good { - a_uint32_t rxusizeg:32; -}; - -union rx_undersize_frames_good_u { - a_uint32_t val; - struct rx_undersize_frames_good bf; -}; - -/*[register] RX_OVERSIZE_FRAMES_GOOD*/ -#define RX_OVERSIZE_FRAMES_GOOD -#define RX_OVERSIZE_FRAMES_GOOD_ADDRESS 0x93c -#define RX_OVERSIZE_FRAMES_GOOD_NUM 1 -#define RX_OVERSIZE_FRAMES_GOOD_INC 0x4000 -#define RX_OVERSIZE_FRAMES_GOOD_TYPE REG_TYPE_RO -#define RX_OVERSIZE_FRAMES_GOOD_DEFAULT 0x0 - /*[field] RXOSIZEG*/ - #define RX_OVERSIZE_FRAMES_GOOD_RXOSIZEG - #define RX_OVERSIZE_FRAMES_GOOD_RXOSIZEG_OFFSET 0 - #define RX_OVERSIZE_FRAMES_GOOD_RXOSIZEG_LEN 32 - #define RX_OVERSIZE_FRAMES_GOOD_RXOSIZEG_DEFAULT 0x0 - -struct rx_oversize_frames_good { - a_uint32_t rxosizeg:32; -}; - -union rx_oversize_frames_good_u { - a_uint32_t val; - struct rx_oversize_frames_good bf; -}; - -/*[register] RX_64OCTETS_FRAMES_GOOD_BAD_LOW*/ -#define RX_64OCTETS_FRAMES_GOOD_BAD_LOW -#define RX_64OCTETS_FRAMES_GOOD_BAD_LOW_ADDRESS 0x940 -#define RX_64OCTETS_FRAMES_GOOD_BAD_LOW_NUM 1 -#define RX_64OCTETS_FRAMES_GOOD_BAD_LOW_INC 0x4000 -#define RX_64OCTETS_FRAMES_GOOD_BAD_LOW_TYPE REG_TYPE_RO -#define RX_64OCTETS_FRAMES_GOOD_BAD_LOW_DEFAULT 0x0 - /*[field] RX64OCTGBLO*/ - #define RX_64OCTETS_FRAMES_GOOD_BAD_LOW_RX64OCTGBLO - #define RX_64OCTETS_FRAMES_GOOD_BAD_LOW_RX64OCTGBLO_OFFSET 0 - #define RX_64OCTETS_FRAMES_GOOD_BAD_LOW_RX64OCTGBLO_LEN 32 - #define RX_64OCTETS_FRAMES_GOOD_BAD_LOW_RX64OCTGBLO_DEFAULT 0x0 - -struct rx_64octets_frames_good_bad_low { - a_uint32_t rx64octgblo:32; -}; - -union rx_64octets_frames_good_bad_low_u { - a_uint32_t val; - struct rx_64octets_frames_good_bad_low bf; -}; - -/*[register] RX_64OCTETS_FRAMES_GOOD_BAD_HIGH*/ -#define RX_64OCTETS_FRAMES_GOOD_BAD_HIGH -#define RX_64OCTETS_FRAMES_GOOD_BAD_HIGH_ADDRESS 0x944 -#define RX_64OCTETS_FRAMES_GOOD_BAD_HIGH_NUM 1 -#define RX_64OCTETS_FRAMES_GOOD_BAD_HIGH_INC 0x4000 -#define RX_64OCTETS_FRAMES_GOOD_BAD_HIGH_TYPE REG_TYPE_RO -#define RX_64OCTETS_FRAMES_GOOD_BAD_HIGH_DEFAULT 0x0 - /*[field] RX64OCTGBHI*/ - #define RX_64OCTETS_FRAMES_GOOD_BAD_HIGH_RX64OCTGBHI - #define RX_64OCTETS_FRAMES_GOOD_BAD_HIGH_RX64OCTGBHI_OFFSET 0 - #define RX_64OCTETS_FRAMES_GOOD_BAD_HIGH_RX64OCTGBHI_LEN 32 - #define RX_64OCTETS_FRAMES_GOOD_BAD_HIGH_RX64OCTGBHI_DEFAULT 0x0 - -struct rx_64octets_frames_good_bad_high { - a_uint32_t rx64octgbhi:32; -}; - -union rx_64octets_frames_good_bad_high_u { - a_uint32_t val; - struct rx_64octets_frames_good_bad_high bf; -}; - -/*[register] RX_65TO127OCTETS_FRAMES_GOOD_BAD_LOW*/ -#define RX_65TO127OCTETS_FRAMES_GOOD_BAD_LOW -#define RX_65TO127OCTETS_FRAMES_GOOD_BAD_LOW_ADDRESS 0x948 -#define RX_65TO127OCTETS_FRAMES_GOOD_BAD_LOW_NUM 1 -#define RX_65TO127OCTETS_FRAMES_GOOD_BAD_LOW_INC 0x4000 -#define RX_65TO127OCTETS_FRAMES_GOOD_BAD_LOW_TYPE REG_TYPE_RO -#define RX_65TO127OCTETS_FRAMES_GOOD_BAD_LOW_DEFAULT 0x0 - /*[field] RX65_127OCTGBLO*/ - #define RX_65TO127OCTETS_FRAMES_GOOD_BAD_LOW_RX65_127OCTGBLO - #define RX_65TO127OCTETS_FRAMES_GOOD_BAD_LOW_RX65_127OCTGBLO_OFFSET 0 - #define RX_65TO127OCTETS_FRAMES_GOOD_BAD_LOW_RX65_127OCTGBLO_LEN 32 - #define RX_65TO127OCTETS_FRAMES_GOOD_BAD_LOW_RX65_127OCTGBLO_DEFAULT 0x0 - -struct rx_65to127octets_frames_good_bad_low { - a_uint32_t rx65_127octgblo:32; -}; - -union rx_65to127octets_frames_good_bad_low_u { - a_uint32_t val; - struct rx_65to127octets_frames_good_bad_low bf; -}; - -/*[register] RX_65TO127OCTETS_FRAMES_GOOD_BAD_HIGH*/ -#define RX_65TO127OCTETS_FRAMES_GOOD_BAD_HIGH -#define RX_65TO127OCTETS_FRAMES_GOOD_BAD_HIGH_ADDRESS 0x94c -#define RX_65TO127OCTETS_FRAMES_GOOD_BAD_HIGH_NUM 1 -#define RX_65TO127OCTETS_FRAMES_GOOD_BAD_HIGH_INC 0x4000 -#define RX_65TO127OCTETS_FRAMES_GOOD_BAD_HIGH_TYPE REG_TYPE_RO -#define RX_65TO127OCTETS_FRAMES_GOOD_BAD_HIGH_DEFAULT 0x0 - /*[field] RX65_127OCTGBHI*/ - #define RX_65TO127OCTETS_FRAMES_GOOD_BAD_HIGH_RX65_127OCTGBHI - #define RX_65TO127OCTETS_FRAMES_GOOD_BAD_HIGH_RX65_127OCTGBHI_OFFSET 0 - #define RX_65TO127OCTETS_FRAMES_GOOD_BAD_HIGH_RX65_127OCTGBHI_LEN 32 - #define RX_65TO127OCTETS_FRAMES_GOOD_BAD_HIGH_RX65_127OCTGBHI_DEFAULT 0x0 - -struct rx_65to127octets_frames_good_bad_high { - a_uint32_t rx65_127octgbhi:32; -}; - -union rx_65to127octets_frames_good_bad_high_u { - a_uint32_t val; - struct rx_65to127octets_frames_good_bad_high bf; -}; - -/*[register] RX_128TO255OCTETS_FRAMES_GOOD_BAD_LOW*/ -#define RX_128TO255OCTETS_FRAMES_GOOD_BAD_LOW -#define RX_128TO255OCTETS_FRAMES_GOOD_BAD_LOW_ADDRESS 0x950 -#define RX_128TO255OCTETS_FRAMES_GOOD_BAD_LOW_NUM 1 -#define RX_128TO255OCTETS_FRAMES_GOOD_BAD_LOW_INC 0x4000 -#define RX_128TO255OCTETS_FRAMES_GOOD_BAD_LOW_TYPE REG_TYPE_RO -#define RX_128TO255OCTETS_FRAMES_GOOD_BAD_LOW_DEFAULT 0x0 - /*[field] RX128_255OCTGBLO*/ - #define RX_128TO255OCTETS_FRAMES_GOOD_BAD_LOW_RX128_255OCTGBLO - #define RX_128TO255OCTETS_FRAMES_GOOD_BAD_LOW_RX128_255OCTGBLO_OFFSET 0 - #define RX_128TO255OCTETS_FRAMES_GOOD_BAD_LOW_RX128_255OCTGBLO_LEN 32 - #define RX_128TO255OCTETS_FRAMES_GOOD_BAD_LOW_RX128_255OCTGBLO_DEFAULT 0x0 - -struct rx_128to255octets_frames_good_bad_low { - a_uint32_t rx128_255octgblo:32; -}; - -union rx_128to255octets_frames_good_bad_low_u { - a_uint32_t val; - struct rx_128to255octets_frames_good_bad_low bf; -}; - -/*[register] RX_128TO255OCTETS_FRAMES_GOOD_BAD_HIGH*/ -#define RX_128TO255OCTETS_FRAMES_GOOD_BAD_HIGH -#define RX_128TO255OCTETS_FRAMES_GOOD_BAD_HIGH_ADDRESS 0x954 -#define RX_128TO255OCTETS_FRAMES_GOOD_BAD_HIGH_NUM 1 -#define RX_128TO255OCTETS_FRAMES_GOOD_BAD_HIGH_INC 0x4000 -#define RX_128TO255OCTETS_FRAMES_GOOD_BAD_HIGH_TYPE REG_TYPE_RO -#define RX_128TO255OCTETS_FRAMES_GOOD_BAD_HIGH_DEFAULT 0x0 - /*[field] RX128_255OCTGBHI*/ - #define RX_128TO255OCTETS_FRAMES_GOOD_BAD_HIGH_RX128_255OCTGBHI - #define RX_128TO255OCTETS_FRAMES_GOOD_BAD_HIGH_RX128_255OCTGBHI_OFFSET 0 - #define RX_128TO255OCTETS_FRAMES_GOOD_BAD_HIGH_RX128_255OCTGBHI_LEN 32 - #define RX_128TO255OCTETS_FRAMES_GOOD_BAD_HIGH_RX128_255OCTGBHI_DEFAULT 0x0 - -struct rx_128to255octets_frames_good_bad_high { - a_uint32_t rx128_255octgbhi:32; -}; - -union rx_128to255octets_frames_good_bad_high_u { - a_uint32_t val; - struct rx_128to255octets_frames_good_bad_high bf; -}; - -/*[register] RX_256TO511OCTETS_FRAMES_GOOD_BAD_LOW*/ -#define RX_256TO511OCTETS_FRAMES_GOOD_BAD_LOW -#define RX_256TO511OCTETS_FRAMES_GOOD_BAD_LOW_ADDRESS 0x958 -#define RX_256TO511OCTETS_FRAMES_GOOD_BAD_LOW_NUM 1 -#define RX_256TO511OCTETS_FRAMES_GOOD_BAD_LOW_INC 0x4000 -#define RX_256TO511OCTETS_FRAMES_GOOD_BAD_LOW_TYPE REG_TYPE_RO -#define RX_256TO511OCTETS_FRAMES_GOOD_BAD_LOW_DEFAULT 0x0 - /*[field] RX256_511OCTGBLO*/ - #define RX_256TO511OCTETS_FRAMES_GOOD_BAD_LOW_RX256_511OCTGBLO - #define RX_256TO511OCTETS_FRAMES_GOOD_BAD_LOW_RX256_511OCTGBLO_OFFSET 0 - #define RX_256TO511OCTETS_FRAMES_GOOD_BAD_LOW_RX256_511OCTGBLO_LEN 32 - #define RX_256TO511OCTETS_FRAMES_GOOD_BAD_LOW_RX256_511OCTGBLO_DEFAULT 0x0 - -struct rx_256to511octets_frames_good_bad_low { - a_uint32_t rx256_511octgblo:32; -}; - -union rx_256to511octets_frames_good_bad_low_u { - a_uint32_t val; - struct rx_256to511octets_frames_good_bad_low bf; -}; - -/*[register] RX_256TO511OCTETS_FRAMES_GOOD_BAD_HIGH*/ -#define RX_256TO511OCTETS_FRAMES_GOOD_BAD_HIGH -#define RX_256TO511OCTETS_FRAMES_GOOD_BAD_HIGH_ADDRESS 0x95c -#define RX_256TO511OCTETS_FRAMES_GOOD_BAD_HIGH_NUM 1 -#define RX_256TO511OCTETS_FRAMES_GOOD_BAD_HIGH_INC 0x4000 -#define RX_256TO511OCTETS_FRAMES_GOOD_BAD_HIGH_TYPE REG_TYPE_RO -#define RX_256TO511OCTETS_FRAMES_GOOD_BAD_HIGH_DEFAULT 0x0 - /*[field] RX256_511OCTGBHI*/ - #define RX_256TO511OCTETS_FRAMES_GOOD_BAD_HIGH_RX256_511OCTGBHI - #define RX_256TO511OCTETS_FRAMES_GOOD_BAD_HIGH_RX256_511OCTGBHI_OFFSET 0 - #define RX_256TO511OCTETS_FRAMES_GOOD_BAD_HIGH_RX256_511OCTGBHI_LEN 32 - #define RX_256TO511OCTETS_FRAMES_GOOD_BAD_HIGH_RX256_511OCTGBHI_DEFAULT 0x0 - -struct rx_256to511octets_frames_good_bad_high { - a_uint32_t rx256_511octgbhi:32; -}; - -union rx_256to511octets_frames_good_bad_high_u { - a_uint32_t val; - struct rx_256to511octets_frames_good_bad_high bf; -}; - -/*[register] RX_512TO1023OCTETS_FRAMES_GOOD_BAD_LOW*/ -#define RX_512TO1023OCTETS_FRAMES_GOOD_BAD_LOW -#define RX_512TO1023OCTETS_FRAMES_GOOD_BAD_LOW_ADDRESS 0x960 -#define RX_512TO1023OCTETS_FRAMES_GOOD_BAD_LOW_NUM 1 -#define RX_512TO1023OCTETS_FRAMES_GOOD_BAD_LOW_INC 0x4000 -#define RX_512TO1023OCTETS_FRAMES_GOOD_BAD_LOW_TYPE REG_TYPE_RO -#define RX_512TO1023OCTETS_FRAMES_GOOD_BAD_LOW_DEFAULT 0x0 - /*[field] RX512_1023OCTGBLO*/ - #define RX_512TO1023OCTETS_FRAMES_GOOD_BAD_LOW_RX512_1023OCTGBLO - #define RX_512TO1023OCTETS_FRAMES_GOOD_BAD_LOW_RX512_1023OCTGBLO_OFFSET 0 - #define RX_512TO1023OCTETS_FRAMES_GOOD_BAD_LOW_RX512_1023OCTGBLO_LEN 32 - #define RX_512TO1023OCTETS_FRAMES_GOOD_BAD_LOW_RX512_1023OCTGBLO_DEFAULT 0x0 - -struct rx_512to1023octets_frames_good_bad_low { - a_uint32_t rx512_1023octgblo:32; -}; - -union rx_512to1023octets_frames_good_bad_low_u { - a_uint32_t val; - struct rx_512to1023octets_frames_good_bad_low bf; -}; - -/*[register] RX_512TO1023OCTETS_FRAMES_GOOD_BAD_HIGH*/ -#define RX_512TO1023OCTETS_FRAMES_GOOD_BAD_HIGH -#define RX_512TO1023OCTETS_FRAMES_GOOD_BAD_HIGH_ADDRESS 0x964 -#define RX_512TO1023OCTETS_FRAMES_GOOD_BAD_HIGH_NUM 1 -#define RX_512TO1023OCTETS_FRAMES_GOOD_BAD_HIGH_INC 0x4000 -#define RX_512TO1023OCTETS_FRAMES_GOOD_BAD_HIGH_TYPE REG_TYPE_RO -#define RX_512TO1023OCTETS_FRAMES_GOOD_BAD_HIGH_DEFAULT 0x0 - /*[field] RX512_1023OCTGBHI*/ - #define RX_512TO1023OCTETS_FRAMES_GOOD_BAD_HIGH_RX512_1023OCTGBHI - #define RX_512TO1023OCTETS_FRAMES_GOOD_BAD_HIGH_RX512_1023OCTGBHI_OFFSET 0 - #define RX_512TO1023OCTETS_FRAMES_GOOD_BAD_HIGH_RX512_1023OCTGBHI_LEN 32 - #define RX_512TO1023OCTETS_FRAMES_GOOD_BAD_HIGH_RX512_1023OCTGBHI_DEFAULT 0x0 - -struct rx_512to1023octets_frames_good_bad_high { - a_uint32_t rx512_1023octgbhi:32; -}; - -union rx_512to1023octets_frames_good_bad_high_u { - a_uint32_t val; - struct rx_512to1023octets_frames_good_bad_high bf; -}; - -/*[register] RX_1024TOMAXOCTETS_FRAMES_GOOD_BAD_LOW*/ -#define RX_1024TOMAXOCTETS_FRAMES_GOOD_BAD_LOW -#define RX_1024TOMAXOCTETS_FRAMES_GOOD_BAD_LOW_ADDRESS 0x968 -#define RX_1024TOMAXOCTETS_FRAMES_GOOD_BAD_LOW_NUM 1 -#define RX_1024TOMAXOCTETS_FRAMES_GOOD_BAD_LOW_INC 0x4000 -#define RX_1024TOMAXOCTETS_FRAMES_GOOD_BAD_LOW_TYPE REG_TYPE_RO -#define RX_1024TOMAXOCTETS_FRAMES_GOOD_BAD_LOW_DEFAULT 0x0 - /*[field] RX1024_MAXGBOCTLO*/ - #define RX_1024TOMAXOCTETS_FRAMES_GOOD_BAD_LOW_RX1024_MAXGBOCTLO - #define RX_1024TOMAXOCTETS_FRAMES_GOOD_BAD_LOW_RX1024_MAXGBOCTLO_OFFSET 0 - #define RX_1024TOMAXOCTETS_FRAMES_GOOD_BAD_LOW_RX1024_MAXGBOCTLO_LEN 32 - #define RX_1024TOMAXOCTETS_FRAMES_GOOD_BAD_LOW_RX1024_MAXGBOCTLO_DEFAULT 0x0 - -struct rx_1024tomaxoctets_frames_good_bad_low { - a_uint32_t rx1024_maxgboctlo:32; -}; - -union rx_1024tomaxoctets_frames_good_bad_low_u { - a_uint32_t val; - struct rx_1024tomaxoctets_frames_good_bad_low bf; -}; - -/*[register] RX_1024TOMAXOCTETS_FRAMES_GOOD_BAD_HIGH*/ -#define RX_1024TOMAXOCTETS_FRAMES_GOOD_BAD_HIGH -#define RX_1024TOMAXOCTETS_FRAMES_GOOD_BAD_HIGH_ADDRESS 0x96c -#define RX_1024TOMAXOCTETS_FRAMES_GOOD_BAD_HIGH_NUM 1 -#define RX_1024TOMAXOCTETS_FRAMES_GOOD_BAD_HIGH_INC 0x4000 -#define RX_1024TOMAXOCTETS_FRAMES_GOOD_BAD_HIGH_TYPE REG_TYPE_RO -#define RX_1024TOMAXOCTETS_FRAMES_GOOD_BAD_HIGH_DEFAULT 0x0 - /*[field] RX1024_MAXGBOCTHI*/ - #define RX_1024TOMAXOCTETS_FRAMES_GOOD_BAD_HIGH_RX1024_MAXGBOCTHI - #define RX_1024TOMAXOCTETS_FRAMES_GOOD_BAD_HIGH_RX1024_MAXGBOCTHI_OFFSET 0 - #define RX_1024TOMAXOCTETS_FRAMES_GOOD_BAD_HIGH_RX1024_MAXGBOCTHI_LEN 32 - #define RX_1024TOMAXOCTETS_FRAMES_GOOD_BAD_HIGH_RX1024_MAXGBOCTHI_DEFAULT 0x0 - -struct rx_1024tomaxoctets_frames_good_bad_high { - a_uint32_t rx1024_maxgbocthi:32; -}; - -union rx_1024tomaxoctets_frames_good_bad_high_u { - a_uint32_t val; - struct rx_1024tomaxoctets_frames_good_bad_high bf; -}; - -/*[register] RX_UNICAST_FRAMES_GOOD_LOW*/ -#define RX_UNICAST_FRAMES_GOOD_LOW -#define RX_UNICAST_FRAMES_GOOD_LOW_ADDRESS 0x970 -#define RX_UNICAST_FRAMES_GOOD_LOW_NUM 1 -#define RX_UNICAST_FRAMES_GOOD_LOW_INC 0x4000 -#define RX_UNICAST_FRAMES_GOOD_LOW_TYPE REG_TYPE_RO -#define RX_UNICAST_FRAMES_GOOD_LOW_DEFAULT 0x0 - /*[field] RXUCASTGLO*/ - #define RX_UNICAST_FRAMES_GOOD_LOW_RXUCASTGLO - #define RX_UNICAST_FRAMES_GOOD_LOW_RXUCASTGLO_OFFSET 0 - #define RX_UNICAST_FRAMES_GOOD_LOW_RXUCASTGLO_LEN 32 - #define RX_UNICAST_FRAMES_GOOD_LOW_RXUCASTGLO_DEFAULT 0x0 - -struct rx_unicast_frames_good_low { - a_uint32_t rxucastglo:32; -}; - -union rx_unicast_frames_good_low_u { - a_uint32_t val; - struct rx_unicast_frames_good_low bf; -}; - -/*[register] RX_UNICAST_FRAMES_GOOD_HIGH*/ -#define RX_UNICAST_FRAMES_GOOD_HIGH -#define RX_UNICAST_FRAMES_GOOD_HIGH_ADDRESS 0x974 -#define RX_UNICAST_FRAMES_GOOD_HIGH_NUM 1 -#define RX_UNICAST_FRAMES_GOOD_HIGH_INC 0x4000 -#define RX_UNICAST_FRAMES_GOOD_HIGH_TYPE REG_TYPE_RO -#define RX_UNICAST_FRAMES_GOOD_HIGH_DEFAULT 0x0 - /*[field] RXUCASTGHI*/ - #define RX_UNICAST_FRAMES_GOOD_HIGH_RXUCASTGHI - #define RX_UNICAST_FRAMES_GOOD_HIGH_RXUCASTGHI_OFFSET 0 - #define RX_UNICAST_FRAMES_GOOD_HIGH_RXUCASTGHI_LEN 32 - #define RX_UNICAST_FRAMES_GOOD_HIGH_RXUCASTGHI_DEFAULT 0x0 - -struct rx_unicast_frames_good_high { - a_uint32_t rxucastghi:32; -}; - -union rx_unicast_frames_good_high_u { - a_uint32_t val; - struct rx_unicast_frames_good_high bf; -}; - -/*[register] RX_LENGTH_ERROR_FRAMES_LOW*/ -#define RX_LENGTH_ERROR_FRAMES_LOW -#define RX_LENGTH_ERROR_FRAMES_LOW_ADDRESS 0x978 -#define RX_LENGTH_ERROR_FRAMES_LOW_NUM 1 -#define RX_LENGTH_ERROR_FRAMES_LOW_INC 0x4000 -#define RX_LENGTH_ERROR_FRAMES_LOW_TYPE REG_TYPE_RO -#define RX_LENGTH_ERROR_FRAMES_LOW_DEFAULT 0x0 - /*[field] RXLENERRLO*/ - #define RX_LENGTH_ERROR_FRAMES_LOW_RXLENERRLO - #define RX_LENGTH_ERROR_FRAMES_LOW_RXLENERRLO_OFFSET 0 - #define RX_LENGTH_ERROR_FRAMES_LOW_RXLENERRLO_LEN 32 - #define RX_LENGTH_ERROR_FRAMES_LOW_RXLENERRLO_DEFAULT 0x0 - -struct rx_length_error_frames_low { - a_uint32_t rxlenerrlo:32; -}; - -union rx_length_error_frames_low_u { - a_uint32_t val; - struct rx_length_error_frames_low bf; -}; - -/*[register] RX_LENGTH_ERROR_FRAMES_HIGH*/ -#define RX_LENGTH_ERROR_FRAMES_HIGH -#define RX_LENGTH_ERROR_FRAMES_HIGH_ADDRESS 0x97c -#define RX_LENGTH_ERROR_FRAMES_HIGH_NUM 1 -#define RX_LENGTH_ERROR_FRAMES_HIGH_INC 0x4000 -#define RX_LENGTH_ERROR_FRAMES_HIGH_TYPE REG_TYPE_RO -#define RX_LENGTH_ERROR_FRAMES_HIGH_DEFAULT 0x0 - /*[field] RXLENERRHI*/ - #define RX_LENGTH_ERROR_FRAMES_HIGH_RXLENERRHI - #define RX_LENGTH_ERROR_FRAMES_HIGH_RXLENERRHI_OFFSET 0 - #define RX_LENGTH_ERROR_FRAMES_HIGH_RXLENERRHI_LEN 32 - #define RX_LENGTH_ERROR_FRAMES_HIGH_RXLENERRHI_DEFAULT 0x0 - -struct rx_length_error_frames_high { - a_uint32_t rxlenerrhi:32; -}; - -union rx_length_error_frames_high_u { - a_uint32_t val; - struct rx_length_error_frames_high bf; -}; - -/*[register] RX_OUTOFRANGE_FRAMES_LOW*/ -#define RX_OUTOFRANGE_FRAMES_LOW -#define RX_OUTOFRANGE_FRAMES_LOW_ADDRESS 0x980 -#define RX_OUTOFRANGE_FRAMES_LOW_NUM 1 -#define RX_OUTOFRANGE_FRAMES_LOW_INC 0x4000 -#define RX_OUTOFRANGE_FRAMES_LOW_TYPE REG_TYPE_RO -#define RX_OUTOFRANGE_FRAMES_LOW_DEFAULT 0x0 - /*[field] RXORANGELO*/ - #define RX_OUTOFRANGE_FRAMES_LOW_RXORANGELO - #define RX_OUTOFRANGE_FRAMES_LOW_RXORANGELO_OFFSET 0 - #define RX_OUTOFRANGE_FRAMES_LOW_RXORANGELO_LEN 32 - #define RX_OUTOFRANGE_FRAMES_LOW_RXORANGELO_DEFAULT 0x0 - -struct rx_outofrange_frames_low { - a_uint32_t rxorangelo:32; -}; - -union rx_outofrange_frames_low_u { - a_uint32_t val; - struct rx_outofrange_frames_low bf; -}; - -/*[register] RX_OUTOFRANGE_FRAMES_HIGH*/ -#define RX_OUTOFRANGE_FRAMES_HIGH -#define RX_OUTOFRANGE_FRAMES_HIGH_ADDRESS 0x984 -#define RX_OUTOFRANGE_FRAMES_HIGH_NUM 1 -#define RX_OUTOFRANGE_FRAMES_HIGH_INC 0x4000 -#define RX_OUTOFRANGE_FRAMES_HIGH_TYPE REG_TYPE_RO -#define RX_OUTOFRANGE_FRAMES_HIGH_DEFAULT 0x0 - /*[field] RXORANGEHI*/ - #define RX_OUTOFRANGE_FRAMES_HIGH_RXORANGEHI - #define RX_OUTOFRANGE_FRAMES_HIGH_RXORANGEHI_OFFSET 0 - #define RX_OUTOFRANGE_FRAMES_HIGH_RXORANGEHI_LEN 32 - #define RX_OUTOFRANGE_FRAMES_HIGH_RXORANGEHI_DEFAULT 0x0 - -struct rx_outofrange_frames_high { - a_uint32_t rxorangehi:32; -}; - -union rx_outofrange_frames_high_u { - a_uint32_t val; - struct rx_outofrange_frames_high bf; -}; - -/*[register] RX_PAUSE_FRAMES_LOW*/ -#define RX_PAUSE_FRAMES_LOW -#define RX_PAUSE_FRAMES_LOW_ADDRESS 0x988 -#define RX_PAUSE_FRAMES_LOW_NUM 1 -#define RX_PAUSE_FRAMES_LOW_INC 0x4000 -#define RX_PAUSE_FRAMES_LOW_TYPE REG_TYPE_RO -#define RX_PAUSE_FRAMES_LOW_DEFAULT 0x0 - /*[field] RXPAUSELO*/ - #define RX_PAUSE_FRAMES_LOW_RXPAUSELO - #define RX_PAUSE_FRAMES_LOW_RXPAUSELO_OFFSET 0 - #define RX_PAUSE_FRAMES_LOW_RXPAUSELO_LEN 32 - #define RX_PAUSE_FRAMES_LOW_RXPAUSELO_DEFAULT 0x0 - -struct rx_pause_frames_low { - a_uint32_t rxpauselo:32; -}; - -union rx_pause_frames_low_u { - a_uint32_t val; - struct rx_pause_frames_low bf; -}; - -/*[register] RX_PAUSE_FRAMES_HIGH*/ -#define RX_PAUSE_FRAMES_HIGH -#define RX_PAUSE_FRAMES_HIGH_ADDRESS 0x98c -#define RX_PAUSE_FRAMES_HIGH_NUM 1 -#define RX_PAUSE_FRAMES_HIGH_INC 0x4000 -#define RX_PAUSE_FRAMES_HIGH_TYPE REG_TYPE_RO -#define RX_PAUSE_FRAMES_HIGH_DEFAULT 0x0 - /*[field] RXPAUSEHI*/ - #define RX_PAUSE_FRAMES_HIGH_RXPAUSEHI - #define RX_PAUSE_FRAMES_HIGH_RXPAUSEHI_OFFSET 0 - #define RX_PAUSE_FRAMES_HIGH_RXPAUSEHI_LEN 32 - #define RX_PAUSE_FRAMES_HIGH_RXPAUSEHI_DEFAULT 0x0 - -struct rx_pause_frames_high { - a_uint32_t rxpausehi:32; -}; - -union rx_pause_frames_high_u { - a_uint32_t val; - struct rx_pause_frames_high bf; -}; - -/*[register] RX_FIFOOVERFLOW_FRAMES_LOW*/ -#define RX_FIFOOVERFLOW_FRAMES_LOW -#define RX_FIFOOVERFLOW_FRAMES_LOW_ADDRESS 0x990 -#define RX_FIFOOVERFLOW_FRAMES_LOW_NUM 1 -#define RX_FIFOOVERFLOW_FRAMES_LOW_INC 0x4000 -#define RX_FIFOOVERFLOW_FRAMES_LOW_TYPE REG_TYPE_RO -#define RX_FIFOOVERFLOW_FRAMES_LOW_DEFAULT 0x0 - /*[field] RXFOVFLO*/ - #define RX_FIFOOVERFLOW_FRAMES_LOW_RXFOVFLO - #define RX_FIFOOVERFLOW_FRAMES_LOW_RXFOVFLO_OFFSET 0 - #define RX_FIFOOVERFLOW_FRAMES_LOW_RXFOVFLO_LEN 32 - #define RX_FIFOOVERFLOW_FRAMES_LOW_RXFOVFLO_DEFAULT 0x0 - -struct rx_fifooverflow_frames_low { - a_uint32_t rxfovflo:32; -}; - -union rx_fifooverflow_frames_low_u { - a_uint32_t val; - struct rx_fifooverflow_frames_low bf; -}; - -/*[register] RX_FIFOOVERFLOW_FRAMES_HIGH*/ -#define RX_FIFOOVERFLOW_FRAMES_HIGH -#define RX_FIFOOVERFLOW_FRAMES_HIGH_ADDRESS 0x994 -#define RX_FIFOOVERFLOW_FRAMES_HIGH_NUM 1 -#define RX_FIFOOVERFLOW_FRAMES_HIGH_INC 0x4000 -#define RX_FIFOOVERFLOW_FRAMES_HIGH_TYPE REG_TYPE_RO -#define RX_FIFOOVERFLOW_FRAMES_HIGH_DEFAULT 0x0 - /*[field] RXFOVFHI*/ - #define RX_FIFOOVERFLOW_FRAMES_HIGH_RXFOVFHI - #define RX_FIFOOVERFLOW_FRAMES_HIGH_RXFOVFHI_OFFSET 0 - #define RX_FIFOOVERFLOW_FRAMES_HIGH_RXFOVFHI_LEN 32 - #define RX_FIFOOVERFLOW_FRAMES_HIGH_RXFOVFHI_DEFAULT 0x0 - -struct rx_fifooverflow_frames_high { - a_uint32_t rxfovfhi:32; -}; - -union rx_fifooverflow_frames_high_u { - a_uint32_t val; - struct rx_fifooverflow_frames_high bf; -}; - -/*[register] RX_VLAN_FRAMES_GOOD_BAD_LOW*/ -#define RX_VLAN_FRAMES_GOOD_BAD_LOW -#define RX_VLAN_FRAMES_GOOD_BAD_LOW_ADDRESS 0x998 -#define RX_VLAN_FRAMES_GOOD_BAD_LOW_NUM 1 -#define RX_VLAN_FRAMES_GOOD_BAD_LOW_INC 0x4000 -#define RX_VLAN_FRAMES_GOOD_BAD_LOW_TYPE REG_TYPE_RO -#define RX_VLAN_FRAMES_GOOD_BAD_LOW_DEFAULT 0x0 - /*[field] RXVLANGBLO*/ - #define RX_VLAN_FRAMES_GOOD_BAD_LOW_RXVLANGBLO - #define RX_VLAN_FRAMES_GOOD_BAD_LOW_RXVLANGBLO_OFFSET 0 - #define RX_VLAN_FRAMES_GOOD_BAD_LOW_RXVLANGBLO_LEN 32 - #define RX_VLAN_FRAMES_GOOD_BAD_LOW_RXVLANGBLO_DEFAULT 0x0 - -struct rx_vlan_frames_good_bad_low { - a_uint32_t rxvlangblo:32; -}; - -union rx_vlan_frames_good_bad_low_u { - a_uint32_t val; - struct rx_vlan_frames_good_bad_low bf; -}; - -/*[register] RX_VLAN_FRAMES_GOOD_BAD_HIGH*/ -#define RX_VLAN_FRAMES_GOOD_BAD_HIGH -#define RX_VLAN_FRAMES_GOOD_BAD_HIGH_ADDRESS 0x99c -#define RX_VLAN_FRAMES_GOOD_BAD_HIGH_NUM 1 -#define RX_VLAN_FRAMES_GOOD_BAD_HIGH_INC 0x4000 -#define RX_VLAN_FRAMES_GOOD_BAD_HIGH_TYPE REG_TYPE_RO -#define RX_VLAN_FRAMES_GOOD_BAD_HIGH_DEFAULT 0x0 - /*[field] RXVLANGBHI*/ - #define RX_VLAN_FRAMES_GOOD_BAD_HIGH_RXVLANGBHI - #define RX_VLAN_FRAMES_GOOD_BAD_HIGH_RXVLANGBHI_OFFSET 0 - #define RX_VLAN_FRAMES_GOOD_BAD_HIGH_RXVLANGBHI_LEN 32 - #define RX_VLAN_FRAMES_GOOD_BAD_HIGH_RXVLANGBHI_DEFAULT 0x0 - -struct rx_vlan_frames_good_bad_high { - a_uint32_t rxvlangbhi:32; -}; - -union rx_vlan_frames_good_bad_high_u { - a_uint32_t val; - struct rx_vlan_frames_good_bad_high bf; -}; - -/*[register] RX_WATCHDOG_ERROR_FRAMES*/ -#define RX_WATCHDOG_ERROR_FRAMES -#define RX_WATCHDOG_ERROR_FRAMES_ADDRESS 0x9a0 -#define RX_WATCHDOG_ERROR_FRAMES_NUM 1 -#define RX_WATCHDOG_ERROR_FRAMES_INC 0x4000 -#define RX_WATCHDOG_ERROR_FRAMES_TYPE REG_TYPE_RO -#define RX_WATCHDOG_ERROR_FRAMES_DEFAULT 0x0 - /*[field] RXWDOGERR*/ - #define RX_WATCHDOG_ERROR_FRAMES_RXWDOGERR - #define RX_WATCHDOG_ERROR_FRAMES_RXWDOGERR_OFFSET 0 - #define RX_WATCHDOG_ERROR_FRAMES_RXWDOGERR_LEN 32 - #define RX_WATCHDOG_ERROR_FRAMES_RXWDOGERR_DEFAULT 0x0 - -struct rx_watchdog_error_frames { - a_uint32_t rxwdogerr:32; -}; - -union rx_watchdog_error_frames_u { - a_uint32_t val; - struct rx_watchdog_error_frames bf; -}; - -/*[register] RX_LPI_USEC_CNTR*/ -#define RX_LPI_USEC_CNTR -#define RX_LPI_USEC_CNTR_ADDRESS 0x9a4 -#define RX_LPI_USEC_CNTR_NUM 1 -#define RX_LPI_USEC_CNTR_INC 0x4000 -#define RX_LPI_USEC_CNTR_TYPE REG_TYPE_RO -#define RX_LPI_USEC_CNTR_DEFAULT 0x0 - /*[field] RXLPIUSC*/ - #define RX_LPI_USEC_CNTR_RXLPIUSC - #define RX_LPI_USEC_CNTR_RXLPIUSC_OFFSET 0 - #define RX_LPI_USEC_CNTR_RXLPIUSC_LEN 32 - #define RX_LPI_USEC_CNTR_RXLPIUSC_DEFAULT 0x0 - -struct rx_lpi_usec_cntr { - a_uint32_t rxlpiusc:32; -}; - -union rx_lpi_usec_cntr_u { - a_uint32_t val; - struct rx_lpi_usec_cntr bf; -}; - -/*[register] RX_LPI_TRAN_CNTR*/ -#define RX_LPI_TRAN_CNTR -#define RX_LPI_TRAN_CNTR_ADDRESS 0x9a8 -#define RX_LPI_TRAN_CNTR_NUM 1 -#define RX_LPI_TRAN_CNTR_INC 0x4000 -#define RX_LPI_TRAN_CNTR_TYPE REG_TYPE_RO -#define RX_LPI_TRAN_CNTR_DEFAULT 0x0 - /*[field] RXLPITRC*/ - #define RX_LPI_TRAN_CNTR_RXLPITRC - #define RX_LPI_TRAN_CNTR_RXLPITRC_OFFSET 0 - #define RX_LPI_TRAN_CNTR_RXLPITRC_LEN 32 - #define RX_LPI_TRAN_CNTR_RXLPITRC_DEFAULT 0x0 - -struct rx_lpi_tran_cntr { - a_uint32_t rxlpitrc:32; -}; - -union rx_lpi_tran_cntr_u { - a_uint32_t val; - struct rx_lpi_tran_cntr bf; -}; - -/*[register] RX_DISCARD_FRAME_COUNT_GOOD_BAD_LOW*/ -#define RX_DISCARD_FRAME_COUNT_GOOD_BAD_LOW -#define RX_DISCARD_FRAME_COUNT_GOOD_BAD_LOW_ADDRESS 0x9ac -#define RX_DISCARD_FRAME_COUNT_GOOD_BAD_LOW_NUM 1 -#define RX_DISCARD_FRAME_COUNT_GOOD_BAD_LOW_INC 0x4000 -#define RX_DISCARD_FRAME_COUNT_GOOD_BAD_LOW_TYPE REG_TYPE_RO -#define RX_DISCARD_FRAME_COUNT_GOOD_BAD_LOW_DEFAULT 0x0 - /*[field] RXDFCNTGBLO*/ - #define RX_DISCARD_FRAME_COUNT_GOOD_BAD_LOW_RXDFCNTGBLO - #define RX_DISCARD_FRAME_COUNT_GOOD_BAD_LOW_RXDFCNTGBLO_OFFSET 0 - #define RX_DISCARD_FRAME_COUNT_GOOD_BAD_LOW_RXDFCNTGBLO_LEN 32 - #define RX_DISCARD_FRAME_COUNT_GOOD_BAD_LOW_RXDFCNTGBLO_DEFAULT 0x0 - -struct rx_discard_frame_count_good_bad_low { - a_uint32_t rxdfcntgblo:32; -}; - -union rx_discard_frame_count_good_bad_low_u { - a_uint32_t val; - struct rx_discard_frame_count_good_bad_low bf; -}; - -/*[register] RX_DISCARD_FRAME_COUNT_GOOD_BAD_HIGH*/ -#define RX_DISCARD_FRAME_COUNT_GOOD_BAD_HIGH -#define RX_DISCARD_FRAME_COUNT_GOOD_BAD_HIGH_ADDRESS 0x9b0 -#define RX_DISCARD_FRAME_COUNT_GOOD_BAD_HIGH_NUM 1 -#define RX_DISCARD_FRAME_COUNT_GOOD_BAD_HIGH_INC 0x4000 -#define RX_DISCARD_FRAME_COUNT_GOOD_BAD_HIGH_TYPE REG_TYPE_RO -#define RX_DISCARD_FRAME_COUNT_GOOD_BAD_HIGH_DEFAULT 0x0 - /*[field] RXDFCNTGBHI*/ - #define RX_DISCARD_FRAME_COUNT_GOOD_BAD_HIGH_RXDFCNTGBHI - #define RX_DISCARD_FRAME_COUNT_GOOD_BAD_HIGH_RXDFCNTGBHI_OFFSET 0 - #define RX_DISCARD_FRAME_COUNT_GOOD_BAD_HIGH_RXDFCNTGBHI_LEN 32 - #define RX_DISCARD_FRAME_COUNT_GOOD_BAD_HIGH_RXDFCNTGBHI_DEFAULT 0x0 - -struct rx_discard_frame_count_good_bad_high { - a_uint32_t rxdfcntgbhi:32; -}; - -union rx_discard_frame_count_good_bad_high_u { - a_uint32_t val; - struct rx_discard_frame_count_good_bad_high bf; -}; - -/*[register] RX_DISCARD_OCTET_COUNT_GOOD_BAD_LOW*/ -#define RX_DISCARD_OCTET_COUNT_GOOD_BAD_LOW -#define RX_DISCARD_OCTET_COUNT_GOOD_BAD_LOW_ADDRESS 0x9b4 -#define RX_DISCARD_OCTET_COUNT_GOOD_BAD_LOW_NUM 1 -#define RX_DISCARD_OCTET_COUNT_GOOD_BAD_LOW_INC 0x4000 -#define RX_DISCARD_OCTET_COUNT_GOOD_BAD_LOW_TYPE REG_TYPE_RO -#define RX_DISCARD_OCTET_COUNT_GOOD_BAD_LOW_DEFAULT 0x0 - /*[field] RXDOCNTGBLO*/ - #define RX_DISCARD_OCTET_COUNT_GOOD_BAD_LOW_RXDOCNTGBLO - #define RX_DISCARD_OCTET_COUNT_GOOD_BAD_LOW_RXDOCNTGBLO_OFFSET 0 - #define RX_DISCARD_OCTET_COUNT_GOOD_BAD_LOW_RXDOCNTGBLO_LEN 32 - #define RX_DISCARD_OCTET_COUNT_GOOD_BAD_LOW_RXDOCNTGBLO_DEFAULT 0x0 - -struct rx_discard_octet_count_good_bad_low { - a_uint32_t rxdocntgblo:32; -}; - -union rx_discard_octet_count_good_bad_low_u { - a_uint32_t val; - struct rx_discard_octet_count_good_bad_low bf; -}; - -/*[register] RX_DISCARD_OCTET_COUNT_GOOD_BAD_HIGH*/ -#define RX_DISCARD_OCTET_COUNT_GOOD_BAD_HIGH -#define RX_DISCARD_OCTET_COUNT_GOOD_BAD_HIGH_ADDRESS 0x9b8 -#define RX_DISCARD_OCTET_COUNT_GOOD_BAD_HIGH_NUM 1 -#define RX_DISCARD_OCTET_COUNT_GOOD_BAD_HIGH_INC 0x4000 -#define RX_DISCARD_OCTET_COUNT_GOOD_BAD_HIGH_TYPE REG_TYPE_RO -#define RX_DISCARD_OCTET_COUNT_GOOD_BAD_HIGH_DEFAULT 0x0 - /*[field] RXDOCNTGBHI*/ - #define RX_DISCARD_OCTET_COUNT_GOOD_BAD_HIGH_RXDOCNTGBHI - #define RX_DISCARD_OCTET_COUNT_GOOD_BAD_HIGH_RXDOCNTGBHI_OFFSET 0 - #define RX_DISCARD_OCTET_COUNT_GOOD_BAD_HIGH_RXDOCNTGBHI_LEN 32 - #define RX_DISCARD_OCTET_COUNT_GOOD_BAD_HIGH_RXDOCNTGBHI_DEFAULT 0x0 - -struct rx_discard_octet_count_good_bad_high { - a_uint32_t rxdocntgbhi:32; -}; - -union rx_discard_octet_count_good_bad_high_u { - a_uint32_t val; - struct rx_discard_octet_count_good_bad_high bf; -}; - - - -#endif diff --git a/feeds/ipq807x/qca-ssdk/src/include/hsl/hppe/hppe_xgportctrl.h b/feeds/ipq807x/qca-ssdk/src/include/hsl/hppe/hppe_xgportctrl.h deleted file mode 100755 index c55a104bb..000000000 --- a/feeds/ipq807x/qca-ssdk/src/include/hsl/hppe/hppe_xgportctrl.h +++ /dev/null @@ -1,2758 +0,0 @@ -/* - * Copyright (c) 2016-2017, The Linux Foundation. All rights reserved. - * Permission to use, copy, modify, and/or distribute this software for - * any purpose with or without fee is hereby granted, provided that the - * above copyright notice and this permission notice appear in all copies. - * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES - * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR - * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES - * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN - * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT - * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. - */ - - -/** - * @defgroup - * @{ - */ -#ifndef _HPPE_XGPORTCTRL_H_ -#define _HPPE_XGPORTCTRL_H_ - -#define MAC_TX_CONFIGURATION_MAX_ENTRY 2 -#define MAC_RX_CONFIGURATION_MAX_ENTRY 2 -#define MAC_PACKET_FILTER_MAX_ENTRY 2 -#define MAC_WATCHDOG_TIMEOUT_MAX_ENTRY 2 -#define MAC_VLAN_TAG_MAX_ENTRY 2 -#define MAC_RX_ETH_TYPE_MATCH_MAX_ENTRY 2 -#define MAC_Q0_TX_FLOW_CTRL_MAX_ENTRY 2 -#define MAC_RX_FLOW_CTRL_MAX_ENTRY 2 -#define MAC_INTERRUPT_STATUS_MAX_ENTRY 2 -#define MAC_INTERRUPT_ENABLE_MAX_ENTRY 2 -#define MAC_RX_TX_STATUS_MAX_ENTRY 2 -#define MAC_LPI_CONTROL_STATUS_MAX_ENTRY 2 -#define MAC_LPI_TIMERS_CONTROL_MAX_ENTRY 2 -#define MAC_LPI_AUTO_ENTRY_TIMER_MAX_ENTRY 2 -#define MAC_1US_TIC_COUNTER_MAX_ENTRY 2 -#define MAC_ADDRESS0_HIGH_MAX_ENTRY 2 -#define MAC_ADDRESS0_LOW_MAX_ENTRY 2 -#define MMC_RECEIVE_INTERRUPT_MAX_ENTRY 2 -#define MMC_TRANSMIT_INTERRUPT_MAX_ENTRY 2 -#define MMC_RECEIVE_INTERRUPT_ENABLE_MAX_ENTRY 2 -#define MMC_TRANSMIT_INTERRUPT_ENABLE_MAX_ENTRY 2 - -sw_error_t -hppe_mac_tx_configuration_get( - a_uint32_t dev_id, - a_uint32_t index, - union mac_tx_configuration_u *value); - -sw_error_t -hppe_mac_tx_configuration_set( - a_uint32_t dev_id, - a_uint32_t index, - union mac_tx_configuration_u *value); - -sw_error_t -hppe_mac_rx_configuration_get( - a_uint32_t dev_id, - a_uint32_t index, - union mac_rx_configuration_u *value); - -sw_error_t -hppe_mac_rx_configuration_set( - a_uint32_t dev_id, - a_uint32_t index, - union mac_rx_configuration_u *value); - -sw_error_t -hppe_mac_packet_filter_get( - a_uint32_t dev_id, - a_uint32_t index, - union mac_packet_filter_u *value); - -sw_error_t -hppe_mac_packet_filter_set( - a_uint32_t dev_id, - a_uint32_t index, - union mac_packet_filter_u *value); - -sw_error_t -hppe_mac_watchdog_timeout_get( - a_uint32_t dev_id, - a_uint32_t index, - union mac_watchdog_timeout_u *value); - -sw_error_t -hppe_mac_watchdog_timeout_set( - a_uint32_t dev_id, - a_uint32_t index, - union mac_watchdog_timeout_u *value); - -sw_error_t -hppe_mac_vlan_tag_get( - a_uint32_t dev_id, - a_uint32_t index, - union mac_vlan_tag_u *value); - -sw_error_t -hppe_mac_vlan_tag_set( - a_uint32_t dev_id, - a_uint32_t index, - union mac_vlan_tag_u *value); - -sw_error_t -hppe_mac_rx_eth_type_match_get( - a_uint32_t dev_id, - a_uint32_t index, - union mac_rx_eth_type_match_u *value); - -sw_error_t -hppe_mac_rx_eth_type_match_set( - a_uint32_t dev_id, - a_uint32_t index, - union mac_rx_eth_type_match_u *value); - -sw_error_t -hppe_mac_q0_tx_flow_ctrl_get( - a_uint32_t dev_id, - a_uint32_t index, - union mac_q0_tx_flow_ctrl_u *value); - -sw_error_t -hppe_mac_q0_tx_flow_ctrl_set( - a_uint32_t dev_id, - a_uint32_t index, - union mac_q0_tx_flow_ctrl_u *value); - -sw_error_t -hppe_mac_rx_flow_ctrl_get( - a_uint32_t dev_id, - a_uint32_t index, - union mac_rx_flow_ctrl_u *value); - -sw_error_t -hppe_mac_rx_flow_ctrl_set( - a_uint32_t dev_id, - a_uint32_t index, - union mac_rx_flow_ctrl_u *value); - -sw_error_t -hppe_mac_interrupt_status_get( - a_uint32_t dev_id, - a_uint32_t index, - union mac_interrupt_status_u *value); - -sw_error_t -hppe_mac_interrupt_status_set( - a_uint32_t dev_id, - a_uint32_t index, - union mac_interrupt_status_u *value); - -sw_error_t -hppe_mac_interrupt_enable_get( - a_uint32_t dev_id, - a_uint32_t index, - union mac_interrupt_enable_u *value); - -sw_error_t -hppe_mac_interrupt_enable_set( - a_uint32_t dev_id, - a_uint32_t index, - union mac_interrupt_enable_u *value); - -sw_error_t -hppe_mac_rx_tx_status_get( - a_uint32_t dev_id, - a_uint32_t index, - union mac_rx_tx_status_u *value); - -sw_error_t -hppe_mac_rx_tx_status_set( - a_uint32_t dev_id, - a_uint32_t index, - union mac_rx_tx_status_u *value); - -sw_error_t -hppe_mac_lpi_control_status_get( - a_uint32_t dev_id, - a_uint32_t index, - union mac_lpi_control_status_u *value); - -sw_error_t -hppe_mac_lpi_control_status_set( - a_uint32_t dev_id, - a_uint32_t index, - union mac_lpi_control_status_u *value); - -sw_error_t -hppe_mac_lpi_timers_control_get( - a_uint32_t dev_id, - a_uint32_t index, - union mac_lpi_timers_control_u *value); - -sw_error_t -hppe_mac_lpi_timers_control_set( - a_uint32_t dev_id, - a_uint32_t index, - union mac_lpi_timers_control_u *value); - -sw_error_t -hppe_mac_lpi_auto_entry_timer_get( - a_uint32_t dev_id, - a_uint32_t index, - union mac_lpi_auto_entry_timer_u *value); - -sw_error_t -hppe_mac_lpi_auto_entry_timer_set( - a_uint32_t dev_id, - a_uint32_t index, - union mac_lpi_auto_entry_timer_u *value); - -sw_error_t -hppe_mac_1us_tic_counter_get( - a_uint32_t dev_id, - a_uint32_t index, - union mac_1us_tic_counter_u *value); - -sw_error_t -hppe_mac_1us_tic_counter_set( - a_uint32_t dev_id, - a_uint32_t index, - union mac_1us_tic_counter_u *value); - -sw_error_t -hppe_mac_address0_high_get( - a_uint32_t dev_id, - a_uint32_t index, - union mac_address0_high_u *value); - -sw_error_t -hppe_mac_address0_high_set( - a_uint32_t dev_id, - a_uint32_t index, - union mac_address0_high_u *value); - -sw_error_t -hppe_mac_address0_low_get( - a_uint32_t dev_id, - a_uint32_t index, - union mac_address0_low_u *value); - -sw_error_t -hppe_mac_address0_low_set( - a_uint32_t dev_id, - a_uint32_t index, - union mac_address0_low_u *value); - -sw_error_t -hppe_mmc_receive_interrupt_get( - a_uint32_t dev_id, - a_uint32_t index, - union mmc_receive_interrupt_u *value); - -sw_error_t -hppe_mmc_receive_interrupt_set( - a_uint32_t dev_id, - a_uint32_t index, - union mmc_receive_interrupt_u *value); - -sw_error_t -hppe_mmc_transmit_interrupt_get( - a_uint32_t dev_id, - a_uint32_t index, - union mmc_transmit_interrupt_u *value); - -sw_error_t -hppe_mmc_transmit_interrupt_set( - a_uint32_t dev_id, - a_uint32_t index, - union mmc_transmit_interrupt_u *value); - -sw_error_t -hppe_mmc_receive_interrupt_enable_get( - a_uint32_t dev_id, - a_uint32_t index, - union mmc_receive_interrupt_enable_u *value); - -sw_error_t -hppe_mmc_receive_interrupt_enable_set( - a_uint32_t dev_id, - a_uint32_t index, - union mmc_receive_interrupt_enable_u *value); - -sw_error_t -hppe_mmc_transmit_interrupt_enable_get( - a_uint32_t dev_id, - a_uint32_t index, - union mmc_transmit_interrupt_enable_u *value); - -sw_error_t -hppe_mmc_transmit_interrupt_enable_set( - a_uint32_t dev_id, - a_uint32_t index, - union mmc_transmit_interrupt_enable_u *value); - -sw_error_t -hppe_mac_tx_configuration_vne_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_mac_tx_configuration_vne_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_mac_tx_configuration_ddic_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_mac_tx_configuration_ddic_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_mac_tx_configuration_te_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_mac_tx_configuration_te_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_mac_tx_configuration_ipg_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_mac_tx_configuration_ipg_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_mac_tx_configuration_ism_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_mac_tx_configuration_ism_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_mac_tx_configuration_ifp_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_mac_tx_configuration_ifp_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_mac_tx_configuration_sarc_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_mac_tx_configuration_sarc_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_mac_tx_configuration_isr_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_mac_tx_configuration_isr_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_mac_tx_configuration_ss_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_mac_tx_configuration_ss_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_mac_tx_configuration_g9991en_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_mac_tx_configuration_g9991en_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_mac_tx_configuration_uss_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_mac_tx_configuration_uss_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_mac_tx_configuration_vnm_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_mac_tx_configuration_vnm_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_mac_tx_configuration_jd_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_mac_tx_configuration_jd_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_mac_rx_configuration_lm_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_mac_rx_configuration_lm_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_mac_rx_configuration_je_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_mac_rx_configuration_je_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_mac_rx_configuration_arpen_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_mac_rx_configuration_arpen_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_mac_rx_configuration_elen_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_mac_rx_configuration_elen_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_mac_rx_configuration_gmpslce_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_mac_rx_configuration_gmpslce_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_mac_rx_configuration_hdsms_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_mac_rx_configuration_hdsms_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_mac_rx_configuration_spen_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_mac_rx_configuration_spen_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_mac_rx_configuration_usp_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_mac_rx_configuration_usp_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_mac_rx_configuration_ipc_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_mac_rx_configuration_ipc_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_mac_rx_configuration_gpsl_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_mac_rx_configuration_gpsl_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_mac_rx_configuration_re_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_mac_rx_configuration_re_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_mac_rx_configuration_cst_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_mac_rx_configuration_cst_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_mac_rx_configuration_dcrcc_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_mac_rx_configuration_dcrcc_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_mac_rx_configuration_wd_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_mac_rx_configuration_wd_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_mac_rx_configuration_acs_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_mac_rx_configuration_acs_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_mac_rx_configuration_s2kp_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_mac_rx_configuration_s2kp_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_mac_packet_filter_pcf_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_mac_packet_filter_pcf_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_mac_packet_filter_hmc_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_mac_packet_filter_hmc_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_mac_packet_filter_dntu_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_mac_packet_filter_dntu_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_mac_packet_filter_saf_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_mac_packet_filter_saf_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_mac_packet_filter_dbf_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_mac_packet_filter_dbf_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_mac_packet_filter_huc_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_mac_packet_filter_huc_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_mac_packet_filter_vtfe_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_mac_packet_filter_vtfe_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_mac_packet_filter_daif_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_mac_packet_filter_daif_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_mac_packet_filter_ra_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_mac_packet_filter_ra_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_mac_packet_filter_hpf_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_mac_packet_filter_hpf_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_mac_packet_filter_pm_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_mac_packet_filter_pm_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_mac_packet_filter_vucc_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_mac_packet_filter_vucc_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_mac_packet_filter_pr_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_mac_packet_filter_pr_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_mac_packet_filter_ipfe_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_mac_packet_filter_ipfe_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_mac_packet_filter_saif_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_mac_packet_filter_saif_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_mac_watchdog_timeout_pwe_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_mac_watchdog_timeout_pwe_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_mac_watchdog_timeout_wto_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_mac_watchdog_timeout_wto_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_mac_vlan_tag_eivls_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_mac_vlan_tag_eivls_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_mac_vlan_tag_vthm_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_mac_vlan_tag_vthm_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_mac_vlan_tag_vl_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_mac_vlan_tag_vl_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_mac_vlan_tag_dovltc_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_mac_vlan_tag_dovltc_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_mac_vlan_tag_etv_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_mac_vlan_tag_etv_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_mac_vlan_tag_erivlt_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_mac_vlan_tag_erivlt_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_mac_vlan_tag_eivlrxs_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_mac_vlan_tag_eivlrxs_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_mac_vlan_tag_vtim_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_mac_vlan_tag_vtim_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_mac_vlan_tag_edvlp_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_mac_vlan_tag_edvlp_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_mac_vlan_tag_evlrxs_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_mac_vlan_tag_evlrxs_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_mac_vlan_tag_evls_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_mac_vlan_tag_evls_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_mac_vlan_tag_esvl_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_mac_vlan_tag_esvl_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_mac_vlan_tag_ersvlm_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_mac_vlan_tag_ersvlm_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_mac_rx_eth_type_match_et_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_mac_rx_eth_type_match_et_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_mac_q0_tx_flow_ctrl_pt_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_mac_q0_tx_flow_ctrl_pt_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_mac_q0_tx_flow_ctrl_plt_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_mac_q0_tx_flow_ctrl_plt_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_mac_q0_tx_flow_ctrl_tfe_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_mac_q0_tx_flow_ctrl_tfe_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_mac_q0_tx_flow_ctrl_fcb_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_mac_q0_tx_flow_ctrl_fcb_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_mac_q0_tx_flow_ctrl_dapq_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_mac_q0_tx_flow_ctrl_dapq_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_mac_rx_flow_ctrl_pfce_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_mac_rx_flow_ctrl_pfce_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_mac_rx_flow_ctrl_up_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_mac_rx_flow_ctrl_up_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_mac_rx_flow_ctrl_rfe_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_mac_rx_flow_ctrl_rfe_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_mac_interrupt_status_txesis_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_mac_interrupt_status_txesis_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_mac_interrupt_status_gpiis_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_mac_interrupt_status_gpiis_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_mac_interrupt_status_tsis_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_mac_interrupt_status_tsis_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_mac_interrupt_status_mmctxis_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_mac_interrupt_status_mmctxis_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_mac_interrupt_status_ls_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_mac_interrupt_status_ls_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_mac_interrupt_status_mmcrxis_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_mac_interrupt_status_mmcrxis_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_mac_interrupt_status_smi_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_mac_interrupt_status_smi_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_mac_interrupt_status_pmtis_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_mac_interrupt_status_pmtis_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_mac_interrupt_status_rxesis_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_mac_interrupt_status_rxesis_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_mac_interrupt_status_lpiis_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_mac_interrupt_status_lpiis_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_mac_interrupt_enable_tsie_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_mac_interrupt_enable_tsie_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_mac_interrupt_enable_lpiie_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_mac_interrupt_enable_lpiie_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_mac_interrupt_enable_txesie_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_mac_interrupt_enable_txesie_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_mac_interrupt_enable_pmtie_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_mac_interrupt_enable_pmtie_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_mac_interrupt_enable_rxesie_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_mac_interrupt_enable_rxesie_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_mac_rx_tx_status_tjt_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_mac_rx_tx_status_tjt_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_mac_rx_tx_status_rwt_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_mac_rx_tx_status_rwt_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_mac_lpi_control_status_tlpien_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_mac_lpi_control_status_tlpien_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_mac_lpi_control_status_lpitcse_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_mac_lpi_control_status_lpitcse_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_mac_lpi_control_status_rxrstp_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_mac_lpi_control_status_rxrstp_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_mac_lpi_control_status_lpite_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_mac_lpi_control_status_lpite_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_mac_lpi_control_status_pls_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_mac_lpi_control_status_pls_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_mac_lpi_control_status_rlpiex_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_mac_lpi_control_status_rlpiex_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_mac_lpi_control_status_rlpien_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_mac_lpi_control_status_rlpien_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_mac_lpi_control_status_rlpist_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_mac_lpi_control_status_rlpist_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_mac_lpi_control_status_tlpist_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_mac_lpi_control_status_tlpist_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_mac_lpi_control_status_txrstp_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_mac_lpi_control_status_txrstp_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_mac_lpi_control_status_plsdis_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_mac_lpi_control_status_plsdis_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_mac_lpi_control_status_lpitxa_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_mac_lpi_control_status_lpitxa_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_mac_lpi_control_status_tlpiex_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_mac_lpi_control_status_tlpiex_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_mac_lpi_control_status_lpitxen_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_mac_lpi_control_status_lpitxen_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_mac_lpi_timers_control_lst_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_mac_lpi_timers_control_lst_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_mac_lpi_timers_control_twt_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_mac_lpi_timers_control_twt_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_mac_lpi_auto_entry_timer_lpiet_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_mac_lpi_auto_entry_timer_lpiet_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_mac_1us_tic_counter_tic_1us_cntr_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_mac_1us_tic_counter_tic_1us_cntr_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_mac_address0_high_addrhi_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_mac_address0_high_addrhi_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_mac_address0_high_ae_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_mac_address0_high_ae_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_mac_address0_high_dcs_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_mac_address0_high_dcs_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_mac_address0_low_addrlo_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_mac_address0_low_addrlo_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_mmc_receive_interrupt_rxorangefis_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_mmc_receive_interrupt_rxorangefis_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_mmc_receive_interrupt_rxlenerfis_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_mmc_receive_interrupt_rxlenerfis_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_mmc_receive_interrupt_rx65t127octgbfis_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_mmc_receive_interrupt_rx65t127octgbfis_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_mmc_receive_interrupt_rxprmmcis_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_mmc_receive_interrupt_rxprmmcis_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_mmc_receive_interrupt_rx512t1023octgbfis_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_mmc_receive_interrupt_rx512t1023octgbfis_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_mmc_receive_interrupt_rxgboctis_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_mmc_receive_interrupt_rxgboctis_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_mmc_receive_interrupt_rxlpiuscis_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_mmc_receive_interrupt_rxlpiuscis_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_mmc_receive_interrupt_rxjaberfis_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_mmc_receive_interrupt_rxjaberfis_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_mmc_receive_interrupt_rxvlangbfis_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_mmc_receive_interrupt_rxvlangbfis_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_mmc_receive_interrupt_rxpausfis_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_mmc_receive_interrupt_rxpausfis_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_mmc_receive_interrupt_rxcrcerfis_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_mmc_receive_interrupt_rxcrcerfis_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_mmc_receive_interrupt_rxdisocgbis_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_mmc_receive_interrupt_rxdisocgbis_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_mmc_receive_interrupt_rxwdogfis_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_mmc_receive_interrupt_rxwdogfis_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_mmc_receive_interrupt_rx128t255octgbfis_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_mmc_receive_interrupt_rx128t255octgbfis_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_mmc_receive_interrupt_rxdisfcgbis_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_mmc_receive_interrupt_rxdisfcgbis_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_mmc_receive_interrupt_rxosizegfis_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_mmc_receive_interrupt_rxosizegfis_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_mmc_receive_interrupt_rx1024tmaxoctgbfis_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_mmc_receive_interrupt_rx1024tmaxoctgbfis_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_mmc_receive_interrupt_rxruntfis_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_mmc_receive_interrupt_rxruntfis_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_mmc_receive_interrupt_rxmcgfis_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_mmc_receive_interrupt_rxmcgfis_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_mmc_receive_interrupt_rx256t511octgbfis_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_mmc_receive_interrupt_rx256t511octgbfis_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_mmc_receive_interrupt_rx64octgbfis_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_mmc_receive_interrupt_rx64octgbfis_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_mmc_receive_interrupt_rxfovfis_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_mmc_receive_interrupt_rxfovfis_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_mmc_receive_interrupt_rxgoctis_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_mmc_receive_interrupt_rxgoctis_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_mmc_receive_interrupt_rxgbfrmis_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_mmc_receive_interrupt_rxgbfrmis_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_mmc_receive_interrupt_rxlpitrcis_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_mmc_receive_interrupt_rxlpitrcis_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_mmc_receive_interrupt_rxbcgfis_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_mmc_receive_interrupt_rxbcgfis_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_mmc_receive_interrupt_rxusizegfis_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_mmc_receive_interrupt_rxusizegfis_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_mmc_receive_interrupt_rxucgfis_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_mmc_receive_interrupt_rxucgfis_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_mmc_transmit_interrupt_txgbfrmis_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_mmc_transmit_interrupt_txgbfrmis_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_mmc_transmit_interrupt_txprmmcis_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_mmc_transmit_interrupt_txprmmcis_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_mmc_transmit_interrupt_tx1024tmaxoctgbfis_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_mmc_transmit_interrupt_tx1024tmaxoctgbfis_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_mmc_transmit_interrupt_tx256t511octgbfis_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_mmc_transmit_interrupt_tx256t511octgbfis_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_mmc_transmit_interrupt_txlpitrcis_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_mmc_transmit_interrupt_txlpitrcis_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_mmc_transmit_interrupt_txbcgfis_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_mmc_transmit_interrupt_txbcgfis_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_mmc_transmit_interrupt_tx64octgbfis_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_mmc_transmit_interrupt_tx64octgbfis_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_mmc_transmit_interrupt_txlpiuscis_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_mmc_transmit_interrupt_txlpiuscis_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_mmc_transmit_interrupt_txuflowerfis_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_mmc_transmit_interrupt_txuflowerfis_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_mmc_transmit_interrupt_txbcgbfis_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_mmc_transmit_interrupt_txbcgbfis_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_mmc_transmit_interrupt_txpausfis_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_mmc_transmit_interrupt_txpausfis_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_mmc_transmit_interrupt_txvlangfis_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_mmc_transmit_interrupt_txvlangfis_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_mmc_transmit_interrupt_txgboctis_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_mmc_transmit_interrupt_txgboctis_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_mmc_transmit_interrupt_txgfrmis_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_mmc_transmit_interrupt_txgfrmis_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_mmc_transmit_interrupt_tx512t1023octgbfis_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_mmc_transmit_interrupt_tx512t1023octgbfis_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_mmc_transmit_interrupt_txmcgfis_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_mmc_transmit_interrupt_txmcgfis_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_mmc_transmit_interrupt_txucgbfis_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_mmc_transmit_interrupt_txucgbfis_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_mmc_transmit_interrupt_tx65t127octgbfis_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_mmc_transmit_interrupt_tx65t127octgbfis_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_mmc_transmit_interrupt_txmcgbfis_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_mmc_transmit_interrupt_txmcgbfis_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_mmc_transmit_interrupt_tx128t255octgbfis_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_mmc_transmit_interrupt_tx128t255octgbfis_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_mmc_transmit_interrupt_txgoctis_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_mmc_transmit_interrupt_txgoctis_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_mmc_receive_interrupt_enable_rxprmmcise_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_mmc_receive_interrupt_enable_rxprmmcise_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_mmc_receive_interrupt_enable_rx65t127octgbfie_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_mmc_receive_interrupt_enable_rx65t127octgbfie_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_mmc_receive_interrupt_enable_rxruntfie_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_mmc_receive_interrupt_enable_rxruntfie_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_mmc_receive_interrupt_enable_rxcrcerfie_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_mmc_receive_interrupt_enable_rxcrcerfie_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_mmc_receive_interrupt_enable_rx256t511octgbfie_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_mmc_receive_interrupt_enable_rx256t511octgbfie_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_mmc_receive_interrupt_enable_rxlenerfie_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_mmc_receive_interrupt_enable_rxlenerfie_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_mmc_receive_interrupt_enable_rxusizegfie_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_mmc_receive_interrupt_enable_rxusizegfie_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_mmc_receive_interrupt_enable_rxosizegfie_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_mmc_receive_interrupt_enable_rxosizegfie_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_mmc_receive_interrupt_enable_rxfovfie_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_mmc_receive_interrupt_enable_rxfovfie_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_mmc_receive_interrupt_enable_rxmcgfie_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_mmc_receive_interrupt_enable_rxmcgfie_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_mmc_receive_interrupt_enable_rxvlangbfie_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_mmc_receive_interrupt_enable_rxvlangbfie_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_mmc_receive_interrupt_enable_rxwdogfie_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_mmc_receive_interrupt_enable_rxwdogfie_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_mmc_receive_interrupt_enable_rxdisocie_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_mmc_receive_interrupt_enable_rxdisocie_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_mmc_receive_interrupt_enable_rxgbfrmie_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_mmc_receive_interrupt_enable_rxgbfrmie_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_mmc_receive_interrupt_enable_rxjaberfie_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_mmc_receive_interrupt_enable_rxjaberfie_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_mmc_receive_interrupt_enable_rxlpiuscie_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_mmc_receive_interrupt_enable_rxlpiuscie_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_mmc_receive_interrupt_enable_rxucgfie_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_mmc_receive_interrupt_enable_rxucgfie_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_mmc_receive_interrupt_enable_rx1024tmaxoctgbfie_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_mmc_receive_interrupt_enable_rx1024tmaxoctgbfie_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_mmc_receive_interrupt_enable_rxpausfie_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_mmc_receive_interrupt_enable_rxpausfie_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_mmc_receive_interrupt_enable_rxdisfcie_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_mmc_receive_interrupt_enable_rxdisfcie_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_mmc_receive_interrupt_enable_rxgoctie_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_mmc_receive_interrupt_enable_rxgoctie_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_mmc_receive_interrupt_enable_rxgboctie_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_mmc_receive_interrupt_enable_rxgboctie_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_mmc_receive_interrupt_enable_rx128t255octgbfie_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_mmc_receive_interrupt_enable_rx128t255octgbfie_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_mmc_receive_interrupt_enable_rxlpitrcie_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_mmc_receive_interrupt_enable_rxlpitrcie_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_mmc_receive_interrupt_enable_rxbcgfie_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_mmc_receive_interrupt_enable_rxbcgfie_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_mmc_receive_interrupt_enable_rx64octgbfie_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_mmc_receive_interrupt_enable_rx64octgbfie_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_mmc_receive_interrupt_enable_rxorangefie_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_mmc_receive_interrupt_enable_rxorangefie_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_mmc_receive_interrupt_enable_rx512t1023octgbfie_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_mmc_receive_interrupt_enable_rx512t1023octgbfie_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_mmc_transmit_interrupt_enable_txucgbfie_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_mmc_transmit_interrupt_enable_txucgbfie_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_mmc_transmit_interrupt_enable_tx64octgbfie_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_mmc_transmit_interrupt_enable_tx64octgbfie_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_mmc_transmit_interrupt_enable_txbcgfie_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_mmc_transmit_interrupt_enable_txbcgfie_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_mmc_transmit_interrupt_enable_txgbfrmie_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_mmc_transmit_interrupt_enable_txgbfrmie_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_mmc_transmit_interrupt_enable_txgfrmie_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_mmc_transmit_interrupt_enable_txgfrmie_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_mmc_transmit_interrupt_enable_txgoctie_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_mmc_transmit_interrupt_enable_txgoctie_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_mmc_transmit_interrupt_enable_txbcgbfie_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_mmc_transmit_interrupt_enable_txbcgbfie_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_mmc_transmit_interrupt_enable_txlpitrcie_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_mmc_transmit_interrupt_enable_txlpitrcie_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_mmc_transmit_interrupt_enable_txvlangfie_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_mmc_transmit_interrupt_enable_txvlangfie_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_mmc_transmit_interrupt_enable_txpausfie_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_mmc_transmit_interrupt_enable_txpausfie_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_mmc_transmit_interrupt_enable_txgboctie_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_mmc_transmit_interrupt_enable_txgboctie_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_mmc_transmit_interrupt_enable_txmcgfie_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_mmc_transmit_interrupt_enable_txmcgfie_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_mmc_transmit_interrupt_enable_txuflowerfie_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_mmc_transmit_interrupt_enable_txuflowerfie_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_mmc_transmit_interrupt_enable_txlpiuscie_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_mmc_transmit_interrupt_enable_txlpiuscie_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_mmc_transmit_interrupt_enable_tx256t511octgbfie_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_mmc_transmit_interrupt_enable_tx256t511octgbfie_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_mmc_transmit_interrupt_enable_tx65t127octgbfie_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_mmc_transmit_interrupt_enable_tx65t127octgbfie_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_mmc_transmit_interrupt_enable_tx128t255octgbfie_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_mmc_transmit_interrupt_enable_tx128t255octgbfie_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_mmc_transmit_interrupt_enable_tx512t1023octgbfie_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_mmc_transmit_interrupt_enable_tx512t1023octgbfie_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_mmc_transmit_interrupt_enable_tx1024tmaxoctgbfie_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_mmc_transmit_interrupt_enable_tx1024tmaxoctgbfie_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_mmc_transmit_interrupt_enable_txprmmcise_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_mmc_transmit_interrupt_enable_txprmmcise_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -sw_error_t -hppe_mmc_transmit_interrupt_enable_txmcgbfie_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value); - -sw_error_t -hppe_mmc_transmit_interrupt_enable_txmcgbfie_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value); - -#endif - diff --git a/feeds/ipq807x/qca-ssdk/src/include/hsl/hppe/hppe_xgportctrl_reg.h b/feeds/ipq807x/qca-ssdk/src/include/hsl/hppe/hppe_xgportctrl_reg.h deleted file mode 100755 index 2adf06375..000000000 --- a/feeds/ipq807x/qca-ssdk/src/include/hsl/hppe/hppe_xgportctrl_reg.h +++ /dev/null @@ -1,1627 +0,0 @@ -/* - * Copyright (c) 2016-2017, The Linux Foundation. All rights reserved. - * Permission to use, copy, modify, and/or distribute this software for - * any purpose with or without fee is hereby granted, provided that the - * above copyright notice and this permission notice appear in all copies. - * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES - * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR - * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES - * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN - * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT - * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. - */ - - -/** - * @defgroup - * @{ - */ -#ifndef HPPE_XGPORTCTRL_REG_H -#define HPPE_XGPORTCTRL_REG_H - -/*[register] MAC_TX_CONFIGURATION*/ -#define MAC_TX_CONFIGURATION -#define MAC_TX_CONFIGURATION_ADDRESS 0x0 -#define MAC_TX_CONFIGURATION_NUM 2 -#define MAC_TX_CONFIGURATION_INC 0x4000 -#define MAC_TX_CONFIGURATION_TYPE REG_TYPE_RW -#define MAC_TX_CONFIGURATION_DEFAULT 0x4000000 - /*[field] TE*/ - #define MAC_TX_CONFIGURATION_TE - #define MAC_TX_CONFIGURATION_TE_OFFSET 0 - #define MAC_TX_CONFIGURATION_TE_LEN 1 - #define MAC_TX_CONFIGURATION_TE_DEFAULT 0x0 - /*[field] DDIC*/ - #define MAC_TX_CONFIGURATION_DDIC - #define MAC_TX_CONFIGURATION_DDIC_OFFSET 1 - #define MAC_TX_CONFIGURATION_DDIC_LEN 1 - #define MAC_TX_CONFIGURATION_DDIC_DEFAULT 0x0 - /*[field] ISM*/ - #define MAC_TX_CONFIGURATION_ISM - #define MAC_TX_CONFIGURATION_ISM_OFFSET 3 - #define MAC_TX_CONFIGURATION_ISM_LEN 1 - #define MAC_TX_CONFIGURATION_ISM_DEFAULT 0x0 - /*[field] ISR*/ - #define MAC_TX_CONFIGURATION_ISR - #define MAC_TX_CONFIGURATION_ISR_OFFSET 4 - #define MAC_TX_CONFIGURATION_ISR_LEN 4 - #define MAC_TX_CONFIGURATION_ISR_DEFAULT 0x0 - /*[field] IPG*/ - #define MAC_TX_CONFIGURATION_IPG - #define MAC_TX_CONFIGURATION_IPG_OFFSET 8 - #define MAC_TX_CONFIGURATION_IPG_LEN 3 - #define MAC_TX_CONFIGURATION_IPG_DEFAULT 0x0 - /*[field] IFP*/ - #define MAC_TX_CONFIGURATION_IFP - #define MAC_TX_CONFIGURATION_IFP_OFFSET 11 - #define MAC_TX_CONFIGURATION_IFP_LEN 1 - #define MAC_TX_CONFIGURATION_IFP_DEFAULT 0x0 - /*[field] JD*/ - #define MAC_TX_CONFIGURATION_JD - #define MAC_TX_CONFIGURATION_JD_OFFSET 16 - #define MAC_TX_CONFIGURATION_JD_LEN 1 - #define MAC_TX_CONFIGURATION_JD_DEFAULT 0x0 - /*[field] SARC*/ - #define MAC_TX_CONFIGURATION_SARC - #define MAC_TX_CONFIGURATION_SARC_OFFSET 20 - #define MAC_TX_CONFIGURATION_SARC_LEN 3 - #define MAC_TX_CONFIGURATION_SARC_DEFAULT 0x0 - /*[field] VNE*/ - #define MAC_TX_CONFIGURATION_VNE - #define MAC_TX_CONFIGURATION_VNE_OFFSET 24 - #define MAC_TX_CONFIGURATION_VNE_LEN 1 - #define MAC_TX_CONFIGURATION_VNE_DEFAULT 0x0 - /*[field] VNM*/ - #define MAC_TX_CONFIGURATION_VNM - #define MAC_TX_CONFIGURATION_VNM_OFFSET 25 - #define MAC_TX_CONFIGURATION_VNM_LEN 1 - #define MAC_TX_CONFIGURATION_VNM_DEFAULT 0x0 - /*[field] G9991EN*/ - #define MAC_TX_CONFIGURATION_G9991EN - #define MAC_TX_CONFIGURATION_G9991EN_OFFSET 28 - #define MAC_TX_CONFIGURATION_G9991EN_LEN 1 - #define MAC_TX_CONFIGURATION_G9991EN_DEFAULT 0x0 - /*[field] SS*/ - #define MAC_TX_CONFIGURATION_SS - #define MAC_TX_CONFIGURATION_SS_OFFSET 29 - #define MAC_TX_CONFIGURATION_SS_LEN 2 - #define MAC_TX_CONFIGURATION_SS_DEFAULT 0x0 - /*[field] USS*/ - #define MAC_TX_CONFIGURATION_USS - #define MAC_TX_CONFIGURATION_USS_OFFSET 31 - #define MAC_TX_CONFIGURATION_USS_LEN 1 - #define MAC_TX_CONFIGURATION_USS_DEFAULT 0x0 - -struct mac_tx_configuration { - a_uint32_t te:1; - a_uint32_t ddic:1; - a_uint32_t _reserved0:1; - a_uint32_t ism:1; - a_uint32_t isr:4; - a_uint32_t ipg:3; - a_uint32_t ifp:1; - a_uint32_t _reserved1:4; - a_uint32_t jd:1; - a_uint32_t _reserved2:3; - a_uint32_t sarc:3; - a_uint32_t _reserved3:1; - a_uint32_t vne:1; - a_uint32_t vnm:1; - a_uint32_t _reserved4:2; - a_uint32_t g9991en:1; - a_uint32_t ss:2; - a_uint32_t uss:1; -}; - -union mac_tx_configuration_u { - a_uint32_t val; - struct mac_tx_configuration bf; -}; - -/*[register] MAC_RX_CONFIGURATION*/ -#define MAC_RX_CONFIGURATION -#define MAC_RX_CONFIGURATION_ADDRESS 0x4 -#define MAC_RX_CONFIGURATION_NUM 2 -#define MAC_RX_CONFIGURATION_INC 0x4000 -#define MAC_RX_CONFIGURATION_TYPE REG_TYPE_RW -#define MAC_RX_CONFIGURATION_DEFAULT 0x0 - /*[field] RE*/ - #define MAC_RX_CONFIGURATION_RE - #define MAC_RX_CONFIGURATION_RE_OFFSET 0 - #define MAC_RX_CONFIGURATION_RE_LEN 1 - #define MAC_RX_CONFIGURATION_RE_DEFAULT 0x0 - /*[field] ACS*/ - #define MAC_RX_CONFIGURATION_ACS - #define MAC_RX_CONFIGURATION_ACS_OFFSET 1 - #define MAC_RX_CONFIGURATION_ACS_LEN 1 - #define MAC_RX_CONFIGURATION_ACS_DEFAULT 0x0 - /*[field] CST*/ - #define MAC_RX_CONFIGURATION_CST - #define MAC_RX_CONFIGURATION_CST_OFFSET 2 - #define MAC_RX_CONFIGURATION_CST_LEN 1 - #define MAC_RX_CONFIGURATION_CST_DEFAULT 0x0 - /*[field] DCRCC*/ - #define MAC_RX_CONFIGURATION_DCRCC - #define MAC_RX_CONFIGURATION_DCRCC_OFFSET 3 - #define MAC_RX_CONFIGURATION_DCRCC_LEN 1 - #define MAC_RX_CONFIGURATION_DCRCC_DEFAULT 0x0 - /*[field] SPEN*/ - #define MAC_RX_CONFIGURATION_SPEN - #define MAC_RX_CONFIGURATION_SPEN_OFFSET 4 - #define MAC_RX_CONFIGURATION_SPEN_LEN 1 - #define MAC_RX_CONFIGURATION_SPEN_DEFAULT 0x0 - /*[field] USP*/ - #define MAC_RX_CONFIGURATION_USP - #define MAC_RX_CONFIGURATION_USP_OFFSET 5 - #define MAC_RX_CONFIGURATION_USP_LEN 1 - #define MAC_RX_CONFIGURATION_USP_DEFAULT 0x0 - /*[field] GMPSLCE*/ - #define MAC_RX_CONFIGURATION_GMPSLCE - #define MAC_RX_CONFIGURATION_GMPSLCE_OFFSET 6 - #define MAC_RX_CONFIGURATION_GMPSLCE_LEN 1 - #define MAC_RX_CONFIGURATION_GMPSLCE_DEFAULT 0x0 - /*[field] WD*/ - #define MAC_RX_CONFIGURATION_WD - #define MAC_RX_CONFIGURATION_WD_OFFSET 7 - #define MAC_RX_CONFIGURATION_WD_LEN 1 - #define MAC_RX_CONFIGURATION_WD_DEFAULT 0x0 - /*[field] JE*/ - #define MAC_RX_CONFIGURATION_JE - #define MAC_RX_CONFIGURATION_JE_OFFSET 8 - #define MAC_RX_CONFIGURATION_JE_LEN 1 - #define MAC_RX_CONFIGURATION_JE_DEFAULT 0x0 - /*[field] IPC*/ - #define MAC_RX_CONFIGURATION_IPC - #define MAC_RX_CONFIGURATION_IPC_OFFSET 9 - #define MAC_RX_CONFIGURATION_IPC_LEN 1 - #define MAC_RX_CONFIGURATION_IPC_DEFAULT 0x0 - /*[field] LM*/ - #define MAC_RX_CONFIGURATION_LM - #define MAC_RX_CONFIGURATION_LM_OFFSET 10 - #define MAC_RX_CONFIGURATION_LM_LEN 1 - #define MAC_RX_CONFIGURATION_LM_DEFAULT 0x0 - /*[field] S2KP*/ - #define MAC_RX_CONFIGURATION_S2KP - #define MAC_RX_CONFIGURATION_S2KP_OFFSET 11 - #define MAC_RX_CONFIGURATION_S2KP_LEN 1 - #define MAC_RX_CONFIGURATION_S2KP_DEFAULT 0x0 - /*[field] HDSMS*/ - #define MAC_RX_CONFIGURATION_HDSMS - #define MAC_RX_CONFIGURATION_HDSMS_OFFSET 12 - #define MAC_RX_CONFIGURATION_HDSMS_LEN 3 - #define MAC_RX_CONFIGURATION_HDSMS_DEFAULT 0x0 - /*[field] GPSL*/ - #define MAC_RX_CONFIGURATION_GPSL - #define MAC_RX_CONFIGURATION_GPSL_OFFSET 16 - #define MAC_RX_CONFIGURATION_GPSL_LEN 14 - #define MAC_RX_CONFIGURATION_GPSL_DEFAULT 0x0 - /*[field] ELEN*/ - #define MAC_RX_CONFIGURATION_ELEN - #define MAC_RX_CONFIGURATION_ELEN_OFFSET 30 - #define MAC_RX_CONFIGURATION_ELEN_LEN 1 - #define MAC_RX_CONFIGURATION_ELEN_DEFAULT 0x0 - /*[field] ARPEN*/ - #define MAC_RX_CONFIGURATION_ARPEN - #define MAC_RX_CONFIGURATION_ARPEN_OFFSET 31 - #define MAC_RX_CONFIGURATION_ARPEN_LEN 1 - #define MAC_RX_CONFIGURATION_ARPEN_DEFAULT 0x0 - -struct mac_rx_configuration { - a_uint32_t re:1; - a_uint32_t acs:1; - a_uint32_t cst:1; - a_uint32_t dcrcc:1; - a_uint32_t spen:1; - a_uint32_t usp:1; - a_uint32_t gmpslce:1; - a_uint32_t wd:1; - a_uint32_t je:1; - a_uint32_t ipc:1; - a_uint32_t lm:1; - a_uint32_t s2kp:1; - a_uint32_t hdsms:3; - a_uint32_t _reserved0:1; - a_uint32_t gpsl:14; - a_uint32_t elen:1; - a_uint32_t arpen:1; -}; - -union mac_rx_configuration_u { - a_uint32_t val; - struct mac_rx_configuration bf; -}; - -/*[register] MAC_PACKET_FILTER*/ -#define MAC_PACKET_FILTER -#define MAC_PACKET_FILTER_ADDRESS 0x8 -#define MAC_PACKET_FILTER_NUM 2 -#define MAC_PACKET_FILTER_INC 0x4000 -#define MAC_PACKET_FILTER_TYPE REG_TYPE_RW -#define MAC_PACKET_FILTER_DEFAULT 0x0 - /*[field] PR*/ - #define MAC_PACKET_FILTER_PR - #define MAC_PACKET_FILTER_PR_OFFSET 0 - #define MAC_PACKET_FILTER_PR_LEN 1 - #define MAC_PACKET_FILTER_PR_DEFAULT 0x0 - /*[field] HUC*/ - #define MAC_PACKET_FILTER_HUC - #define MAC_PACKET_FILTER_HUC_OFFSET 1 - #define MAC_PACKET_FILTER_HUC_LEN 1 - #define MAC_PACKET_FILTER_HUC_DEFAULT 0x0 - /*[field] HMC*/ - #define MAC_PACKET_FILTER_HMC - #define MAC_PACKET_FILTER_HMC_OFFSET 2 - #define MAC_PACKET_FILTER_HMC_LEN 1 - #define MAC_PACKET_FILTER_HMC_DEFAULT 0x0 - /*[field] DAIF*/ - #define MAC_PACKET_FILTER_DAIF - #define MAC_PACKET_FILTER_DAIF_OFFSET 3 - #define MAC_PACKET_FILTER_DAIF_LEN 1 - #define MAC_PACKET_FILTER_DAIF_DEFAULT 0x0 - /*[field] PM*/ - #define MAC_PACKET_FILTER_PM - #define MAC_PACKET_FILTER_PM_OFFSET 4 - #define MAC_PACKET_FILTER_PM_LEN 1 - #define MAC_PACKET_FILTER_PM_DEFAULT 0x0 - /*[field] DBF*/ - #define MAC_PACKET_FILTER_DBF - #define MAC_PACKET_FILTER_DBF_OFFSET 5 - #define MAC_PACKET_FILTER_DBF_LEN 1 - #define MAC_PACKET_FILTER_DBF_DEFAULT 0x0 - /*[field] PCF*/ - #define MAC_PACKET_FILTER_PCF - #define MAC_PACKET_FILTER_PCF_OFFSET 6 - #define MAC_PACKET_FILTER_PCF_LEN 2 - #define MAC_PACKET_FILTER_PCF_DEFAULT 0x0 - /*[field] SAIF*/ - #define MAC_PACKET_FILTER_SAIF - #define MAC_PACKET_FILTER_SAIF_OFFSET 8 - #define MAC_PACKET_FILTER_SAIF_LEN 1 - #define MAC_PACKET_FILTER_SAIF_DEFAULT 0x0 - /*[field] SAF*/ - #define MAC_PACKET_FILTER_SAF - #define MAC_PACKET_FILTER_SAF_OFFSET 9 - #define MAC_PACKET_FILTER_SAF_LEN 1 - #define MAC_PACKET_FILTER_SAF_DEFAULT 0x0 - /*[field] HPF*/ - #define MAC_PACKET_FILTER_HPF - #define MAC_PACKET_FILTER_HPF_OFFSET 10 - #define MAC_PACKET_FILTER_HPF_LEN 1 - #define MAC_PACKET_FILTER_HPF_DEFAULT 0x0 - /*[field] VTFE*/ - #define MAC_PACKET_FILTER_VTFE - #define MAC_PACKET_FILTER_VTFE_OFFSET 16 - #define MAC_PACKET_FILTER_VTFE_LEN 1 - #define MAC_PACKET_FILTER_VTFE_DEFAULT 0x0 - /*[field] IPFE*/ - #define MAC_PACKET_FILTER_IPFE - #define MAC_PACKET_FILTER_IPFE_OFFSET 20 - #define MAC_PACKET_FILTER_IPFE_LEN 1 - #define MAC_PACKET_FILTER_IPFE_DEFAULT 0x0 - /*[field] DNTU*/ - #define MAC_PACKET_FILTER_DNTU - #define MAC_PACKET_FILTER_DNTU_OFFSET 21 - #define MAC_PACKET_FILTER_DNTU_LEN 1 - #define MAC_PACKET_FILTER_DNTU_DEFAULT 0x0 - /*[field] VUCC*/ - #define MAC_PACKET_FILTER_VUCC - #define MAC_PACKET_FILTER_VUCC_OFFSET 22 - #define MAC_PACKET_FILTER_VUCC_LEN 1 - #define MAC_PACKET_FILTER_VUCC_DEFAULT 0x0 - /*[field] RA*/ - #define MAC_PACKET_FILTER_RA - #define MAC_PACKET_FILTER_RA_OFFSET 31 - #define MAC_PACKET_FILTER_RA_LEN 1 - #define MAC_PACKET_FILTER_RA_DEFAULT 0x0 - -struct mac_packet_filter { - a_uint32_t pr:1; - a_uint32_t huc:1; - a_uint32_t hmc:1; - a_uint32_t daif:1; - a_uint32_t pm:1; - a_uint32_t dbf:1; - a_uint32_t pcf:2; - a_uint32_t saif:1; - a_uint32_t saf:1; - a_uint32_t hpf:1; - a_uint32_t _reserved0:5; - a_uint32_t vtfe:1; - a_uint32_t _reserved1:3; - a_uint32_t ipfe:1; - a_uint32_t dntu:1; - a_uint32_t vucc:1; - a_uint32_t _reserved2:8; - a_uint32_t ra:1; -}; - -union mac_packet_filter_u { - a_uint32_t val; - struct mac_packet_filter bf; -}; - -/*[register] MAC_WATCHDOG_TIMEOUT*/ -#define MAC_WATCHDOG_TIMEOUT -#define MAC_WATCHDOG_TIMEOUT_ADDRESS 0xc -#define MAC_WATCHDOG_TIMEOUT_NUM 2 -#define MAC_WATCHDOG_TIMEOUT_INC 0x4000 -#define MAC_WATCHDOG_TIMEOUT_TYPE REG_TYPE_RW -#define MAC_WATCHDOG_TIMEOUT_DEFAULT 0x0 - /*[field] WTO*/ - #define MAC_WATCHDOG_TIMEOUT_WTO - #define MAC_WATCHDOG_TIMEOUT_WTO_OFFSET 0 - #define MAC_WATCHDOG_TIMEOUT_WTO_LEN 4 - #define MAC_WATCHDOG_TIMEOUT_WTO_DEFAULT 0x0 - /*[field] PWE*/ - #define MAC_WATCHDOG_TIMEOUT_PWE - #define MAC_WATCHDOG_TIMEOUT_PWE_OFFSET 8 - #define MAC_WATCHDOG_TIMEOUT_PWE_LEN 1 - #define MAC_WATCHDOG_TIMEOUT_PWE_DEFAULT 0x0 - -struct mac_watchdog_timeout { - a_uint32_t wto:4; - a_uint32_t _reserved0:4; - a_uint32_t pwe:1; - a_uint32_t _reserved1:23; -}; - -union mac_watchdog_timeout_u { - a_uint32_t val; - struct mac_watchdog_timeout bf; -}; - -/*[register] MAC_VLAN_TAG*/ -#define MAC_VLAN_TAG -#define MAC_VLAN_TAG_ADDRESS 0x50 -#define MAC_VLAN_TAG_NUM 2 -#define MAC_VLAN_TAG_INC 0x4000 -#define MAC_VLAN_TAG_TYPE REG_TYPE_RW -#define MAC_VLAN_TAG_DEFAULT 0x1b800000 - /*[field] VL*/ - #define MAC_VLAN_TAG_VL - #define MAC_VLAN_TAG_VL_OFFSET 0 - #define MAC_VLAN_TAG_VL_LEN 16 - #define MAC_VLAN_TAG_VL_DEFAULT 0x0 - /*[field] ETV*/ - #define MAC_VLAN_TAG_ETV - #define MAC_VLAN_TAG_ETV_OFFSET 16 - #define MAC_VLAN_TAG_ETV_LEN 1 - #define MAC_VLAN_TAG_ETV_DEFAULT 0x0 - /*[field] VTIM*/ - #define MAC_VLAN_TAG_VTIM - #define MAC_VLAN_TAG_VTIM_OFFSET 17 - #define MAC_VLAN_TAG_VTIM_LEN 1 - #define MAC_VLAN_TAG_VTIM_DEFAULT 0x0 - /*[field] ESVL*/ - #define MAC_VLAN_TAG_ESVL - #define MAC_VLAN_TAG_ESVL_OFFSET 18 - #define MAC_VLAN_TAG_ESVL_LEN 1 - #define MAC_VLAN_TAG_ESVL_DEFAULT 0x0 - /*[field] ERSVLM*/ - #define MAC_VLAN_TAG_ERSVLM - #define MAC_VLAN_TAG_ERSVLM_OFFSET 19 - #define MAC_VLAN_TAG_ERSVLM_LEN 1 - #define MAC_VLAN_TAG_ERSVLM_DEFAULT 0x0 - /*[field] DOVLTC*/ - #define MAC_VLAN_TAG_DOVLTC - #define MAC_VLAN_TAG_DOVLTC_OFFSET 20 - #define MAC_VLAN_TAG_DOVLTC_LEN 1 - #define MAC_VLAN_TAG_DOVLTC_DEFAULT 0x0 - /*[field] EVLS*/ - #define MAC_VLAN_TAG_EVLS - #define MAC_VLAN_TAG_EVLS_OFFSET 21 - #define MAC_VLAN_TAG_EVLS_LEN 2 - #define MAC_VLAN_TAG_EVLS_DEFAULT 0x0 - /*[field] EVLRXS*/ - #define MAC_VLAN_TAG_EVLRXS - #define MAC_VLAN_TAG_EVLRXS_OFFSET 24 - #define MAC_VLAN_TAG_EVLRXS_LEN 1 - #define MAC_VLAN_TAG_EVLRXS_DEFAULT 0x1 - /*[field] VTHM*/ - #define MAC_VLAN_TAG_VTHM - #define MAC_VLAN_TAG_VTHM_OFFSET 25 - #define MAC_VLAN_TAG_VTHM_LEN 1 - #define MAC_VLAN_TAG_VTHM_DEFAULT 0x1 - /*[field] EDVLP*/ - #define MAC_VLAN_TAG_EDVLP - #define MAC_VLAN_TAG_EDVLP_OFFSET 26 - #define MAC_VLAN_TAG_EDVLP_LEN 1 - #define MAC_VLAN_TAG_EDVLP_DEFAULT 0x0 - /*[field] ERIVLT*/ - #define MAC_VLAN_TAG_ERIVLT - #define MAC_VLAN_TAG_ERIVLT_OFFSET 27 - #define MAC_VLAN_TAG_ERIVLT_LEN 1 - #define MAC_VLAN_TAG_ERIVLT_DEFAULT 0x1 - /*[field] EIVLS*/ - #define MAC_VLAN_TAG_EIVLS - #define MAC_VLAN_TAG_EIVLS_OFFSET 28 - #define MAC_VLAN_TAG_EIVLS_LEN 2 - #define MAC_VLAN_TAG_EIVLS_DEFAULT 0x1 - /*[field] EIVLRXS*/ - #define MAC_VLAN_TAG_EIVLRXS - #define MAC_VLAN_TAG_EIVLRXS_OFFSET 31 - #define MAC_VLAN_TAG_EIVLRXS_LEN 1 - #define MAC_VLAN_TAG_EIVLRXS_DEFAULT 0x0 - -struct mac_vlan_tag { - a_uint32_t vl:16; - a_uint32_t etv:1; - a_uint32_t vtim:1; - a_uint32_t esvl:1; - a_uint32_t ersvlm:1; - a_uint32_t dovltc:1; - a_uint32_t evls:2; - a_uint32_t _reserved0:1; - a_uint32_t evlrxs:1; - a_uint32_t vthm:1; - a_uint32_t edvlp:1; - a_uint32_t erivlt:1; - a_uint32_t eivls:2; - a_uint32_t _reserved1:1; - a_uint32_t eivlrxs:1; -}; - -union mac_vlan_tag_u { - a_uint32_t val; - struct mac_vlan_tag bf; -}; - -/*[register] MAC_RX_ETH_TYPE_MATCH*/ -#define MAC_RX_ETH_TYPE_MATCH -#define MAC_RX_ETH_TYPE_MATCH_ADDRESS 0x6c -#define MAC_RX_ETH_TYPE_MATCH_NUM 2 -#define MAC_RX_ETH_TYPE_MATCH_INC 0x4000 -#define MAC_RX_ETH_TYPE_MATCH_TYPE REG_TYPE_RW -#define MAC_RX_ETH_TYPE_MATCH_DEFAULT 0x0 - /*[field] ET*/ - #define MAC_RX_ETH_TYPE_MATCH_ET - #define MAC_RX_ETH_TYPE_MATCH_ET_OFFSET 0 - #define MAC_RX_ETH_TYPE_MATCH_ET_LEN 16 - #define MAC_RX_ETH_TYPE_MATCH_ET_DEFAULT 0x0 - -struct mac_rx_eth_type_match { - a_uint32_t et:16; - a_uint32_t _reserved0:16; -}; - -union mac_rx_eth_type_match_u { - a_uint32_t val; - struct mac_rx_eth_type_match bf; -}; - -/*[register] MAC_Q0_TX_FLOW_CTRL*/ -#define MAC_Q0_TX_FLOW_CTRL -#define MAC_Q0_TX_FLOW_CTRL_ADDRESS 0x70 -#define MAC_Q0_TX_FLOW_CTRL_NUM 2 -#define MAC_Q0_TX_FLOW_CTRL_INC 0x4000 -#define MAC_Q0_TX_FLOW_CTRL_TYPE REG_TYPE_RW -#define MAC_Q0_TX_FLOW_CTRL_DEFAULT 0x2 - /*[field] FCB*/ - #define MAC_Q0_TX_FLOW_CTRL_FCB - #define MAC_Q0_TX_FLOW_CTRL_FCB_OFFSET 0 - #define MAC_Q0_TX_FLOW_CTRL_FCB_LEN 1 - #define MAC_Q0_TX_FLOW_CTRL_FCB_DEFAULT 0x0 - /*[field] TFE*/ - #define MAC_Q0_TX_FLOW_CTRL_TFE - #define MAC_Q0_TX_FLOW_CTRL_TFE_OFFSET 1 - #define MAC_Q0_TX_FLOW_CTRL_TFE_LEN 1 - #define MAC_Q0_TX_FLOW_CTRL_TFE_DEFAULT 0x1 - /*[field] PLT*/ - #define MAC_Q0_TX_FLOW_CTRL_PLT - #define MAC_Q0_TX_FLOW_CTRL_PLT_OFFSET 4 - #define MAC_Q0_TX_FLOW_CTRL_PLT_LEN 3 - #define MAC_Q0_TX_FLOW_CTRL_PLT_DEFAULT 0x0 - /*[field] DAPQ*/ - #define MAC_Q0_TX_FLOW_CTRL_DAPQ - #define MAC_Q0_TX_FLOW_CTRL_DAPQ_OFFSET 7 - #define MAC_Q0_TX_FLOW_CTRL_DAPQ_LEN 1 - #define MAC_Q0_TX_FLOW_CTRL_DAPQ_DEFAULT 0x0 - /*[field] PT*/ - #define MAC_Q0_TX_FLOW_CTRL_PT - #define MAC_Q0_TX_FLOW_CTRL_PT_OFFSET 16 - #define MAC_Q0_TX_FLOW_CTRL_PT_LEN 16 - #define MAC_Q0_TX_FLOW_CTRL_PT_DEFAULT 0x0 - -struct mac_q0_tx_flow_ctrl { - a_uint32_t fcb:1; - a_uint32_t tfe:1; - a_uint32_t _reserved0:2; - a_uint32_t plt:3; - a_uint32_t dapq:1; - a_uint32_t _reserved1:8; - a_uint32_t pt:16; -}; - -union mac_q0_tx_flow_ctrl_u { - a_uint32_t val; - struct mac_q0_tx_flow_ctrl bf; -}; - -/*[register] MAC_RX_FLOW_CTRL*/ -#define MAC_RX_FLOW_CTRL -#define MAC_RX_FLOW_CTRL_ADDRESS 0x90 -#define MAC_RX_FLOW_CTRL_NUM 2 -#define MAC_RX_FLOW_CTRL_INC 0x4000 -#define MAC_RX_FLOW_CTRL_TYPE REG_TYPE_RW -#define MAC_RX_FLOW_CTRL_DEFAULT 0x80e - /*[field] RFE*/ - #define MAC_RX_FLOW_CTRL_RFE - #define MAC_RX_FLOW_CTRL_RFE_OFFSET 0 - #define MAC_RX_FLOW_CTRL_RFE_LEN 1 - #define MAC_RX_FLOW_CTRL_RFE_DEFAULT 0x0 - /*[field] UP*/ - #define MAC_RX_FLOW_CTRL_UP - #define MAC_RX_FLOW_CTRL_UP_OFFSET 1 - #define MAC_RX_FLOW_CTRL_UP_LEN 1 - #define MAC_RX_FLOW_CTRL_UP_DEFAULT 0x7 - /*[field] PFCE*/ - #define MAC_RX_FLOW_CTRL_PFCE - #define MAC_RX_FLOW_CTRL_PFCE_OFFSET 8 - #define MAC_RX_FLOW_CTRL_PFCE_LEN 1 - #define MAC_RX_FLOW_CTRL_PFCE_DEFAULT 0x0 - -struct mac_rx_flow_ctrl { - a_uint32_t rfe:1; - a_uint32_t up:1; - a_uint32_t _reserved0:6; - a_uint32_t pfce:1; - a_uint32_t _reserved1:23; -}; - -union mac_rx_flow_ctrl_u { - a_uint32_t val; - struct mac_rx_flow_ctrl bf; -}; - -/*[register] MAC_INTERRUPT_STATUS*/ -#define MAC_INTERRUPT_STATUS -#define MAC_INTERRUPT_STATUS_ADDRESS 0xb0 -#define MAC_INTERRUPT_STATUS_NUM 2 -#define MAC_INTERRUPT_STATUS_INC 0x4000 -#define MAC_INTERRUPT_STATUS_TYPE REG_TYPE_RW -#define MAC_INTERRUPT_STATUS_DEFAULT 0x0 - /*[field] SMI*/ - #define MAC_INTERRUPT_STATUS_SMI - #define MAC_INTERRUPT_STATUS_SMI_OFFSET 1 - #define MAC_INTERRUPT_STATUS_SMI_LEN 1 - #define MAC_INTERRUPT_STATUS_SMI_DEFAULT 0x0 - /*[field] PMTIS*/ - #define MAC_INTERRUPT_STATUS_PMTIS - #define MAC_INTERRUPT_STATUS_PMTIS_OFFSET 4 - #define MAC_INTERRUPT_STATUS_PMTIS_LEN 1 - #define MAC_INTERRUPT_STATUS_PMTIS_DEFAULT 0x0 - /*[field] LPIIS*/ - #define MAC_INTERRUPT_STATUS_LPIIS - #define MAC_INTERRUPT_STATUS_LPIIS_OFFSET 5 - #define MAC_INTERRUPT_STATUS_LPIIS_LEN 1 - #define MAC_INTERRUPT_STATUS_LPIIS_DEFAULT 0x0 - /*[field] MMCRXIS*/ - #define MAC_INTERRUPT_STATUS_MMCRXIS - #define MAC_INTERRUPT_STATUS_MMCRXIS_OFFSET 9 - #define MAC_INTERRUPT_STATUS_MMCRXIS_LEN 1 - #define MAC_INTERRUPT_STATUS_MMCRXIS_DEFAULT 0x0 - /*[field] MMCTXIS*/ - #define MAC_INTERRUPT_STATUS_MMCTXIS - #define MAC_INTERRUPT_STATUS_MMCTXIS_OFFSET 10 - #define MAC_INTERRUPT_STATUS_MMCTXIS_LEN 1 - #define MAC_INTERRUPT_STATUS_MMCTXIS_DEFAULT 0x0 - /*[field] TSIS*/ - #define MAC_INTERRUPT_STATUS_TSIS - #define MAC_INTERRUPT_STATUS_TSIS_OFFSET 12 - #define MAC_INTERRUPT_STATUS_TSIS_LEN 1 - #define MAC_INTERRUPT_STATUS_TSIS_DEFAULT 0x0 - /*[field] TXESIS*/ - #define MAC_INTERRUPT_STATUS_TXESIS - #define MAC_INTERRUPT_STATUS_TXESIS_OFFSET 13 - #define MAC_INTERRUPT_STATUS_TXESIS_LEN 1 - #define MAC_INTERRUPT_STATUS_TXESIS_DEFAULT 0x0 - /*[field] RXESIS*/ - #define MAC_INTERRUPT_STATUS_RXESIS - #define MAC_INTERRUPT_STATUS_RXESIS_OFFSET 14 - #define MAC_INTERRUPT_STATUS_RXESIS_LEN 1 - #define MAC_INTERRUPT_STATUS_RXESIS_DEFAULT 0x0 - /*[field] GPIIS*/ - #define MAC_INTERRUPT_STATUS_GPIIS - #define MAC_INTERRUPT_STATUS_GPIIS_OFFSET 15 - #define MAC_INTERRUPT_STATUS_GPIIS_LEN 1 - #define MAC_INTERRUPT_STATUS_GPIIS_DEFAULT 0x0 - /*[field] LS*/ - #define MAC_INTERRUPT_STATUS_LS - #define MAC_INTERRUPT_STATUS_LS_OFFSET 24 - #define MAC_INTERRUPT_STATUS_LS_LEN 2 - #define MAC_INTERRUPT_STATUS_LS_DEFAULT 0x0 - -struct mac_interrupt_status { - a_uint32_t smi:1; - a_uint32_t _reserved0:2; - a_uint32_t pmtis:1; - a_uint32_t lpiis:1; - a_uint32_t _reserved1:3; - a_uint32_t mmcrxis:1; - a_uint32_t mmctxis:1; - a_uint32_t _reserved2:1; - a_uint32_t tsis:1; - a_uint32_t txesis:1; - a_uint32_t rxesis:1; - a_uint32_t gpiis:1; - a_uint32_t _reserved3:8; - a_uint32_t ls:2; - a_uint32_t _reserved4:6; -}; - -union mac_interrupt_status_u { - a_uint32_t val; - struct mac_interrupt_status bf; -}; - -/*[register] MAC_INTERRUPT_ENABLE*/ -#define MAC_INTERRUPT_ENABLE -#define MAC_INTERRUPT_ENABLE_ADDRESS 0xb4 -#define MAC_INTERRUPT_ENABLE_NUM 2 -#define MAC_INTERRUPT_ENABLE_INC 0x4000 -#define MAC_INTERRUPT_ENABLE_TYPE REG_TYPE_RO -#define MAC_INTERRUPT_ENABLE_DEFAULT 0x0 - /*[field] PMTIE*/ - #define MAC_INTERRUPT_ENABLE_PMTIE - #define MAC_INTERRUPT_ENABLE_PMTIE_OFFSET 4 - #define MAC_INTERRUPT_ENABLE_PMTIE_LEN 1 - #define MAC_INTERRUPT_ENABLE_PMTIE_DEFAULT 0x0 - /*[field] LPIIE*/ - #define MAC_INTERRUPT_ENABLE_LPIIE - #define MAC_INTERRUPT_ENABLE_LPIIE_OFFSET 5 - #define MAC_INTERRUPT_ENABLE_LPIIE_LEN 1 - #define MAC_INTERRUPT_ENABLE_LPIIE_DEFAULT 0x0 - /*[field] TSIE*/ - #define MAC_INTERRUPT_ENABLE_TSIE - #define MAC_INTERRUPT_ENABLE_TSIE_OFFSET 12 - #define MAC_INTERRUPT_ENABLE_TSIE_LEN 1 - #define MAC_INTERRUPT_ENABLE_TSIE_DEFAULT 0x0 - /*[field] TXESIE*/ - #define MAC_INTERRUPT_ENABLE_TXESIE - #define MAC_INTERRUPT_ENABLE_TXESIE_OFFSET 13 - #define MAC_INTERRUPT_ENABLE_TXESIE_LEN 1 - #define MAC_INTERRUPT_ENABLE_TXESIE_DEFAULT 0x0 - /*[field] RXESIE*/ - #define MAC_INTERRUPT_ENABLE_RXESIE - #define MAC_INTERRUPT_ENABLE_RXESIE_OFFSET 14 - #define MAC_INTERRUPT_ENABLE_RXESIE_LEN 1 - #define MAC_INTERRUPT_ENABLE_RXESIE_DEFAULT 0x0 - -struct mac_interrupt_enable { - a_uint32_t pmtie:1; - a_uint32_t lpiie:1; - a_uint32_t _reserved0:6; - a_uint32_t tsie:1; - a_uint32_t txesie:1; - a_uint32_t rxesie:1; - a_uint32_t _reserved1:17; -}; - -union mac_interrupt_enable_u { - a_uint32_t val; - struct mac_interrupt_enable bf; -}; - -/*[register] MAC_RX_TX_STATUS*/ -#define MAC_RX_TX_STATUS -#define MAC_RX_TX_STATUS_ADDRESS 0xb8 -#define MAC_RX_TX_STATUS_NUM 2 -#define MAC_RX_TX_STATUS_INC 0x4000 -#define MAC_RX_TX_STATUS_TYPE REG_TYPE_RW -#define MAC_RX_TX_STATUS_DEFAULT 0x0 - /*[field] TJT*/ - #define MAC_RX_TX_STATUS_TJT - #define MAC_RX_TX_STATUS_TJT_OFFSET 0 - #define MAC_RX_TX_STATUS_TJT_LEN 1 - #define MAC_RX_TX_STATUS_TJT_DEFAULT 0x0 - /*[field] RWT*/ - #define MAC_RX_TX_STATUS_RWT - #define MAC_RX_TX_STATUS_RWT_OFFSET 8 - #define MAC_RX_TX_STATUS_RWT_LEN 1 - #define MAC_RX_TX_STATUS_RWT_DEFAULT 0x0 - -struct mac_rx_tx_status { - a_uint32_t tjt:1; - a_uint32_t _reserved0:7; - a_uint32_t rwt:1; - a_uint32_t _reserved1:23; -}; - -union mac_rx_tx_status_u { - a_uint32_t val; - struct mac_rx_tx_status bf; -}; - -/*[register] MAC_LPI_CONTROL_STATUS*/ -#define MAC_LPI_CONTROL_STATUS -#define MAC_LPI_CONTROL_STATUS_ADDRESS 0xd0 -#define MAC_LPI_CONTROL_STATUS_NUM 2 -#define MAC_LPI_CONTROL_STATUS_INC 0x4000 -#define MAC_LPI_CONTROL_STATUS_TYPE REG_TYPE_RW -#define MAC_LPI_CONTROL_STATUS_DEFAULT 0x0 - /*[field] TLPIEN*/ - #define MAC_LPI_CONTROL_STATUS_TLPIEN - #define MAC_LPI_CONTROL_STATUS_TLPIEN_OFFSET 0 - #define MAC_LPI_CONTROL_STATUS_TLPIEN_LEN 1 - #define MAC_LPI_CONTROL_STATUS_TLPIEN_DEFAULT 0x0 - /*[field] TLPIEX*/ - #define MAC_LPI_CONTROL_STATUS_TLPIEX - #define MAC_LPI_CONTROL_STATUS_TLPIEX_OFFSET 1 - #define MAC_LPI_CONTROL_STATUS_TLPIEX_LEN 1 - #define MAC_LPI_CONTROL_STATUS_TLPIEX_DEFAULT 0x0 - /*[field] RLPIEN*/ - #define MAC_LPI_CONTROL_STATUS_RLPIEN - #define MAC_LPI_CONTROL_STATUS_RLPIEN_OFFSET 2 - #define MAC_LPI_CONTROL_STATUS_RLPIEN_LEN 1 - #define MAC_LPI_CONTROL_STATUS_RLPIEN_DEFAULT 0x0 - /*[field] RLPIEX*/ - #define MAC_LPI_CONTROL_STATUS_RLPIEX - #define MAC_LPI_CONTROL_STATUS_RLPIEX_OFFSET 3 - #define MAC_LPI_CONTROL_STATUS_RLPIEX_LEN 1 - #define MAC_LPI_CONTROL_STATUS_RLPIEX_DEFAULT 0x0 - /*[field] TLPIST*/ - #define MAC_LPI_CONTROL_STATUS_TLPIST - #define MAC_LPI_CONTROL_STATUS_TLPIST_OFFSET 8 - #define MAC_LPI_CONTROL_STATUS_TLPIST_LEN 1 - #define MAC_LPI_CONTROL_STATUS_TLPIST_DEFAULT 0x0 - /*[field] RLPIST*/ - #define MAC_LPI_CONTROL_STATUS_RLPIST - #define MAC_LPI_CONTROL_STATUS_RLPIST_OFFSET 9 - #define MAC_LPI_CONTROL_STATUS_RLPIST_LEN 1 - #define MAC_LPI_CONTROL_STATUS_RLPIST_DEFAULT 0x0 - /*[field] RXRSTP*/ - #define MAC_LPI_CONTROL_STATUS_RXRSTP - #define MAC_LPI_CONTROL_STATUS_RXRSTP_OFFSET 10 - #define MAC_LPI_CONTROL_STATUS_RXRSTP_LEN 1 - #define MAC_LPI_CONTROL_STATUS_RXRSTP_DEFAULT 0x0 - /*[field] TXRSTP*/ - #define MAC_LPI_CONTROL_STATUS_TXRSTP - #define MAC_LPI_CONTROL_STATUS_TXRSTP_OFFSET 11 - #define MAC_LPI_CONTROL_STATUS_TXRSTP_LEN 1 - #define MAC_LPI_CONTROL_STATUS_TXRSTP_DEFAULT 0x0 - /*[field] LPITXEN*/ - #define MAC_LPI_CONTROL_STATUS_LPITXEN - #define MAC_LPI_CONTROL_STATUS_LPITXEN_OFFSET 16 - #define MAC_LPI_CONTROL_STATUS_LPITXEN_LEN 1 - #define MAC_LPI_CONTROL_STATUS_LPITXEN_DEFAULT 0x0 - /*[field] PLS*/ - #define MAC_LPI_CONTROL_STATUS_PLS - #define MAC_LPI_CONTROL_STATUS_PLS_OFFSET 17 - #define MAC_LPI_CONTROL_STATUS_PLS_LEN 1 - #define MAC_LPI_CONTROL_STATUS_PLS_DEFAULT 0x0 - /*[field] PLSDIS*/ - #define MAC_LPI_CONTROL_STATUS_PLSDIS - #define MAC_LPI_CONTROL_STATUS_PLSDIS_OFFSET 18 - #define MAC_LPI_CONTROL_STATUS_PLSDIS_LEN 1 - #define MAC_LPI_CONTROL_STATUS_PLSDIS_DEFAULT 0x0 - /*[field] LPITXA*/ - #define MAC_LPI_CONTROL_STATUS_LPITXA - #define MAC_LPI_CONTROL_STATUS_LPITXA_OFFSET 19 - #define MAC_LPI_CONTROL_STATUS_LPITXA_LEN 1 - #define MAC_LPI_CONTROL_STATUS_LPITXA_DEFAULT 0x0 - /*[field] LPITE*/ - #define MAC_LPI_CONTROL_STATUS_LPITE - #define MAC_LPI_CONTROL_STATUS_LPITE_OFFSET 20 - #define MAC_LPI_CONTROL_STATUS_LPITE_LEN 1 - #define MAC_LPI_CONTROL_STATUS_LPITE_DEFAULT 0x0 - /*[field] LPITCSE*/ - #define MAC_LPI_CONTROL_STATUS_LPITCSE - #define MAC_LPI_CONTROL_STATUS_LPITCSE_OFFSET 21 - #define MAC_LPI_CONTROL_STATUS_LPITCSE_LEN 1 - #define MAC_LPI_CONTROL_STATUS_LPITCSE_DEFAULT 0x0 - -struct mac_lpi_control_status { - a_uint32_t tlpien:1; - a_uint32_t tlpiex:1; - a_uint32_t rlpien:1; - a_uint32_t rlpiex:1; - a_uint32_t _reserved0:4; - a_uint32_t tlpist:1; - a_uint32_t rlpist:1; - a_uint32_t rxrstp:1; - a_uint32_t txrstp:1; - a_uint32_t _reserved1:4; - a_uint32_t lpitxen:1; - a_uint32_t pls:1; - a_uint32_t plsdis:1; - a_uint32_t lpitxa:1; - a_uint32_t lpite:1; - a_uint32_t lpitcse:1; - a_uint32_t _reserved2:10; -}; - -union mac_lpi_control_status_u { - a_uint32_t val; - struct mac_lpi_control_status bf; -}; - -/*[register] MAC_LPI_TIMERS_CONTROL*/ -#define MAC_LPI_TIMERS_CONTROL -#define MAC_LPI_TIMERS_CONTROL_ADDRESS 0xd4 -#define MAC_LPI_TIMERS_CONTROL_NUM 2 -#define MAC_LPI_TIMERS_CONTROL_INC 0x4000 -#define MAC_LPI_TIMERS_CONTROL_TYPE REG_TYPE_RO -#define MAC_LPI_TIMERS_CONTROL_DEFAULT 0x0 - /*[field] TWT*/ - #define MAC_LPI_TIMERS_CONTROL_TWT - #define MAC_LPI_TIMERS_CONTROL_TWT_OFFSET 0 - #define MAC_LPI_TIMERS_CONTROL_TWT_LEN 16 - #define MAC_LPI_TIMERS_CONTROL_TWT_DEFAULT 0x0 - /*[field] LST*/ - #define MAC_LPI_TIMERS_CONTROL_LST - #define MAC_LPI_TIMERS_CONTROL_LST_OFFSET 16 - #define MAC_LPI_TIMERS_CONTROL_LST_LEN 10 - #define MAC_LPI_TIMERS_CONTROL_LST_DEFAULT 0x0 - -struct mac_lpi_timers_control { - a_uint32_t twt:16; - a_uint32_t lst:10; - a_uint32_t _reserved0:6; -}; - -union mac_lpi_timers_control_u { - a_uint32_t val; - struct mac_lpi_timers_control bf; -}; - -/*[register] MAC_LPI_AUTO_ENTRY_TIMER*/ -#define MAC_LPI_AUTO_ENTRY_TIMER -#define MAC_LPI_AUTO_ENTRY_TIMER_ADDRESS 0xd8 -#define MAC_LPI_AUTO_ENTRY_TIMER_NUM 2 -#define MAC_LPI_AUTO_ENTRY_TIMER_INC 0x4000 -#define MAC_LPI_AUTO_ENTRY_TIMER_TYPE REG_TYPE_RO -#define MAC_LPI_AUTO_ENTRY_TIMER_DEFAULT 0x0 - /*[field] LPIET*/ - #define MAC_LPI_AUTO_ENTRY_TIMER_LPIET - #define MAC_LPI_AUTO_ENTRY_TIMER_LPIET_OFFSET 3 - #define MAC_LPI_AUTO_ENTRY_TIMER_LPIET_LEN 17 - #define MAC_LPI_AUTO_ENTRY_TIMER_LPIET_DEFAULT 0x0 - -struct mac_lpi_auto_entry_timer { - a_uint32_t lpiet:17; - a_uint32_t _reserved0:12; -}; - -union mac_lpi_auto_entry_timer_u { - a_uint32_t val; - struct mac_lpi_auto_entry_timer bf; -}; - -/*[register] MAC_1US_TIC_COUNTER*/ -#define MAC_1US_TIC_COUNTER -#define MAC_1US_TIC_COUNTER_ADDRESS 0xdc -#define MAC_1US_TIC_COUNTER_NUM 2 -#define MAC_1US_TIC_COUNTER_INC 0x4000 -#define MAC_1US_TIC_COUNTER_TYPE REG_TYPE_RO -#define MAC_1US_TIC_COUNTER_DEFAULT 0x0 - /*[field] TIC_1US_CNTR*/ - #define MAC_1US_TIC_COUNTER_TIC_1US_CNTR - #define MAC_1US_TIC_COUNTER_TIC_1US_CNTR_OFFSET 0 - #define MAC_1US_TIC_COUNTER_TIC_1US_CNTR_LEN 12 - #define MAC_1US_TIC_COUNTER_TIC_1US_CNTR_DEFAULT 0x0 - -struct mac_1us_tic_counter { - a_uint32_t tic_1us_cntr:12; - a_uint32_t _reserved0:20; -}; - -union mac_1us_tic_counter_u { - a_uint32_t val; - struct mac_1us_tic_counter bf; -}; - -/*[register] MAC_ADDRESS0_HIGH*/ -#define MAC_ADDRESS0_HIGH -#define MAC_ADDRESS0_HIGH_ADDRESS 0x300 -#define MAC_ADDRESS0_HIGH_NUM 2 -#define MAC_ADDRESS0_HIGH_INC 0x4000 -#define MAC_ADDRESS0_HIGH_TYPE REG_TYPE_RO -#define MAC_ADDRESS0_HIGH_DEFAULT 0x0 - /*[field] ADDRHI*/ - #define MAC_ADDRESS0_HIGH_ADDRHI - #define MAC_ADDRESS0_HIGH_ADDRHI_OFFSET 0 - #define MAC_ADDRESS0_HIGH_ADDRHI_LEN 16 - #define MAC_ADDRESS0_HIGH_ADDRHI_DEFAULT 0x0 - /*[field] DCS*/ - #define MAC_ADDRESS0_HIGH_DCS - #define MAC_ADDRESS0_HIGH_DCS_OFFSET 16 - #define MAC_ADDRESS0_HIGH_DCS_LEN 1 - #define MAC_ADDRESS0_HIGH_DCS_DEFAULT 0x0 - /*[field] AE*/ - #define MAC_ADDRESS0_HIGH_AE - #define MAC_ADDRESS0_HIGH_AE_OFFSET 31 - #define MAC_ADDRESS0_HIGH_AE_LEN 1 - #define MAC_ADDRESS0_HIGH_AE_DEFAULT 0x0 - -struct mac_address0_high { - a_uint32_t addrhi:16; - a_uint32_t dcs:1; - a_uint32_t _reserved0:14; - a_uint32_t ae:1; -}; - -union mac_address0_high_u { - a_uint32_t val; - struct mac_address0_high bf; -}; - -/*[register] MAC_ADDRESS0_LOW*/ -#define MAC_ADDRESS0_LOW -#define MAC_ADDRESS0_LOW_ADDRESS 0x304 -#define MAC_ADDRESS0_LOW_NUM 2 -#define MAC_ADDRESS0_LOW_INC 0x4000 -#define MAC_ADDRESS0_LOW_TYPE REG_TYPE_RO -#define MAC_ADDRESS0_LOW_DEFAULT 0x0 - /*[field] ADDRLO*/ - #define MAC_ADDRESS0_LOW_ADDRLO - #define MAC_ADDRESS0_LOW_ADDRLO_OFFSET 0 - #define MAC_ADDRESS0_LOW_ADDRLO_LEN 32 - #define MAC_ADDRESS0_LOW_ADDRLO_DEFAULT 0x0 - -struct mac_address0_low { - a_uint32_t addrlo:32; -}; - -union mac_address0_low_u { - a_uint32_t val; - struct mac_address0_low bf; -}; - -/*[register] MMC_RECEIVE_INTERRUPT*/ -#define MMC_RECEIVE_INTERRUPT -#define MMC_RECEIVE_INTERRUPT_ADDRESS 0x804 -#define MMC_RECEIVE_INTERRUPT_NUM 2 -#define MMC_RECEIVE_INTERRUPT_INC 0x4000 -#define MMC_RECEIVE_INTERRUPT_TYPE REG_TYPE_RO -#define MMC_RECEIVE_INTERRUPT_DEFAULT 0x0 - /*[field] RXGBFRMIS*/ - #define MMC_RECEIVE_INTERRUPT_RXGBFRMIS - #define MMC_RECEIVE_INTERRUPT_RXGBFRMIS_OFFSET 0 - #define MMC_RECEIVE_INTERRUPT_RXGBFRMIS_LEN 1 - #define MMC_RECEIVE_INTERRUPT_RXGBFRMIS_DEFAULT 0x0 - /*[field] RXGBOCTIS*/ - #define MMC_RECEIVE_INTERRUPT_RXGBOCTIS - #define MMC_RECEIVE_INTERRUPT_RXGBOCTIS_OFFSET 1 - #define MMC_RECEIVE_INTERRUPT_RXGBOCTIS_LEN 1 - #define MMC_RECEIVE_INTERRUPT_RXGBOCTIS_DEFAULT 0x0 - /*[field] RXGOCTIS*/ - #define MMC_RECEIVE_INTERRUPT_RXGOCTIS - #define MMC_RECEIVE_INTERRUPT_RXGOCTIS_OFFSET 2 - #define MMC_RECEIVE_INTERRUPT_RXGOCTIS_LEN 1 - #define MMC_RECEIVE_INTERRUPT_RXGOCTIS_DEFAULT 0x0 - /*[field] RXBCGFIS*/ - #define MMC_RECEIVE_INTERRUPT_RXBCGFIS - #define MMC_RECEIVE_INTERRUPT_RXBCGFIS_OFFSET 3 - #define MMC_RECEIVE_INTERRUPT_RXBCGFIS_LEN 1 - #define MMC_RECEIVE_INTERRUPT_RXBCGFIS_DEFAULT 0x0 - /*[field] RXMCGFIS*/ - #define MMC_RECEIVE_INTERRUPT_RXMCGFIS - #define MMC_RECEIVE_INTERRUPT_RXMCGFIS_OFFSET 4 - #define MMC_RECEIVE_INTERRUPT_RXMCGFIS_LEN 1 - #define MMC_RECEIVE_INTERRUPT_RXMCGFIS_DEFAULT 0x0 - /*[field] RXCRCERFIS*/ - #define MMC_RECEIVE_INTERRUPT_RXCRCERFIS - #define MMC_RECEIVE_INTERRUPT_RXCRCERFIS_OFFSET 5 - #define MMC_RECEIVE_INTERRUPT_RXCRCERFIS_LEN 1 - #define MMC_RECEIVE_INTERRUPT_RXCRCERFIS_DEFAULT 0x0 - /*[field] RXRUNTFIS*/ - #define MMC_RECEIVE_INTERRUPT_RXRUNTFIS - #define MMC_RECEIVE_INTERRUPT_RXRUNTFIS_OFFSET 6 - #define MMC_RECEIVE_INTERRUPT_RXRUNTFIS_LEN 1 - #define MMC_RECEIVE_INTERRUPT_RXRUNTFIS_DEFAULT 0x0 - /*[field] RXJABERFIS*/ - #define MMC_RECEIVE_INTERRUPT_RXJABERFIS - #define MMC_RECEIVE_INTERRUPT_RXJABERFIS_OFFSET 7 - #define MMC_RECEIVE_INTERRUPT_RXJABERFIS_LEN 1 - #define MMC_RECEIVE_INTERRUPT_RXJABERFIS_DEFAULT 0x0 - /*[field] RXUSIZEGFIS*/ - #define MMC_RECEIVE_INTERRUPT_RXUSIZEGFIS - #define MMC_RECEIVE_INTERRUPT_RXUSIZEGFIS_OFFSET 8 - #define MMC_RECEIVE_INTERRUPT_RXUSIZEGFIS_LEN 1 - #define MMC_RECEIVE_INTERRUPT_RXUSIZEGFIS_DEFAULT 0x0 - /*[field] RXOSIZEGFIS*/ - #define MMC_RECEIVE_INTERRUPT_RXOSIZEGFIS - #define MMC_RECEIVE_INTERRUPT_RXOSIZEGFIS_OFFSET 9 - #define MMC_RECEIVE_INTERRUPT_RXOSIZEGFIS_LEN 1 - #define MMC_RECEIVE_INTERRUPT_RXOSIZEGFIS_DEFAULT 0x0 - /*[field] RX64OCTGBFIS*/ - #define MMC_RECEIVE_INTERRUPT_RX64OCTGBFIS - #define MMC_RECEIVE_INTERRUPT_RX64OCTGBFIS_OFFSET 10 - #define MMC_RECEIVE_INTERRUPT_RX64OCTGBFIS_LEN 1 - #define MMC_RECEIVE_INTERRUPT_RX64OCTGBFIS_DEFAULT 0x0 - /*[field] RX65T127OCTGBFIS*/ - #define MMC_RECEIVE_INTERRUPT_RX65T127OCTGBFIS - #define MMC_RECEIVE_INTERRUPT_RX65T127OCTGBFIS_OFFSET 11 - #define MMC_RECEIVE_INTERRUPT_RX65T127OCTGBFIS_LEN 1 - #define MMC_RECEIVE_INTERRUPT_RX65T127OCTGBFIS_DEFAULT 0x0 - /*[field] RX128T255OCTGBFIS*/ - #define MMC_RECEIVE_INTERRUPT_RX128T255OCTGBFIS - #define MMC_RECEIVE_INTERRUPT_RX128T255OCTGBFIS_OFFSET 12 - #define MMC_RECEIVE_INTERRUPT_RX128T255OCTGBFIS_LEN 1 - #define MMC_RECEIVE_INTERRUPT_RX128T255OCTGBFIS_DEFAULT 0x0 - /*[field] RX256T511OCTGBFIS*/ - #define MMC_RECEIVE_INTERRUPT_RX256T511OCTGBFIS - #define MMC_RECEIVE_INTERRUPT_RX256T511OCTGBFIS_OFFSET 13 - #define MMC_RECEIVE_INTERRUPT_RX256T511OCTGBFIS_LEN 1 - #define MMC_RECEIVE_INTERRUPT_RX256T511OCTGBFIS_DEFAULT 0x0 - /*[field] RX512T1023OCTGBFIS*/ - #define MMC_RECEIVE_INTERRUPT_RX512T1023OCTGBFIS - #define MMC_RECEIVE_INTERRUPT_RX512T1023OCTGBFIS_OFFSET 14 - #define MMC_RECEIVE_INTERRUPT_RX512T1023OCTGBFIS_LEN 1 - #define MMC_RECEIVE_INTERRUPT_RX512T1023OCTGBFIS_DEFAULT 0x0 - /*[field] RX1024TMAXOCTGBFIS*/ - #define MMC_RECEIVE_INTERRUPT_RX1024TMAXOCTGBFIS - #define MMC_RECEIVE_INTERRUPT_RX1024TMAXOCTGBFIS_OFFSET 15 - #define MMC_RECEIVE_INTERRUPT_RX1024TMAXOCTGBFIS_LEN 1 - #define MMC_RECEIVE_INTERRUPT_RX1024TMAXOCTGBFIS_DEFAULT 0x0 - /*[field] RXUCGFIS*/ - #define MMC_RECEIVE_INTERRUPT_RXUCGFIS - #define MMC_RECEIVE_INTERRUPT_RXUCGFIS_OFFSET 16 - #define MMC_RECEIVE_INTERRUPT_RXUCGFIS_LEN 1 - #define MMC_RECEIVE_INTERRUPT_RXUCGFIS_DEFAULT 0x0 - /*[field] RXLENERFIS*/ - #define MMC_RECEIVE_INTERRUPT_RXLENERFIS - #define MMC_RECEIVE_INTERRUPT_RXLENERFIS_OFFSET 17 - #define MMC_RECEIVE_INTERRUPT_RXLENERFIS_LEN 1 - #define MMC_RECEIVE_INTERRUPT_RXLENERFIS_DEFAULT 0x0 - /*[field] RXORANGEFIS*/ - #define MMC_RECEIVE_INTERRUPT_RXORANGEFIS - #define MMC_RECEIVE_INTERRUPT_RXORANGEFIS_OFFSET 18 - #define MMC_RECEIVE_INTERRUPT_RXORANGEFIS_LEN 1 - #define MMC_RECEIVE_INTERRUPT_RXORANGEFIS_DEFAULT 0x0 - /*[field] RXPAUSFIS*/ - #define MMC_RECEIVE_INTERRUPT_RXPAUSFIS - #define MMC_RECEIVE_INTERRUPT_RXPAUSFIS_OFFSET 19 - #define MMC_RECEIVE_INTERRUPT_RXPAUSFIS_LEN 1 - #define MMC_RECEIVE_INTERRUPT_RXPAUSFIS_DEFAULT 0x0 - /*[field] RXFOVFIS*/ - #define MMC_RECEIVE_INTERRUPT_RXFOVFIS - #define MMC_RECEIVE_INTERRUPT_RXFOVFIS_OFFSET 20 - #define MMC_RECEIVE_INTERRUPT_RXFOVFIS_LEN 1 - #define MMC_RECEIVE_INTERRUPT_RXFOVFIS_DEFAULT 0x0 - /*[field] RXVLANGBFIS*/ - #define MMC_RECEIVE_INTERRUPT_RXVLANGBFIS - #define MMC_RECEIVE_INTERRUPT_RXVLANGBFIS_OFFSET 21 - #define MMC_RECEIVE_INTERRUPT_RXVLANGBFIS_LEN 1 - #define MMC_RECEIVE_INTERRUPT_RXVLANGBFIS_DEFAULT 0x0 - /*[field] RXWDOGFIS*/ - #define MMC_RECEIVE_INTERRUPT_RXWDOGFIS - #define MMC_RECEIVE_INTERRUPT_RXWDOGFIS_OFFSET 22 - #define MMC_RECEIVE_INTERRUPT_RXWDOGFIS_LEN 1 - #define MMC_RECEIVE_INTERRUPT_RXWDOGFIS_DEFAULT 0x0 - /*[field] RXDISFCGBIS*/ - #define MMC_RECEIVE_INTERRUPT_RXDISFCGBIS - #define MMC_RECEIVE_INTERRUPT_RXDISFCGBIS_OFFSET 23 - #define MMC_RECEIVE_INTERRUPT_RXDISFCGBIS_LEN 1 - #define MMC_RECEIVE_INTERRUPT_RXDISFCGBIS_DEFAULT 0x0 - /*[field] RXDISOCGBIS*/ - #define MMC_RECEIVE_INTERRUPT_RXDISOCGBIS - #define MMC_RECEIVE_INTERRUPT_RXDISOCGBIS_OFFSET 24 - #define MMC_RECEIVE_INTERRUPT_RXDISOCGBIS_LEN 1 - #define MMC_RECEIVE_INTERRUPT_RXDISOCGBIS_DEFAULT 0x0 - /*[field] RXLPIUSCIS*/ - #define MMC_RECEIVE_INTERRUPT_RXLPIUSCIS - #define MMC_RECEIVE_INTERRUPT_RXLPIUSCIS_OFFSET 25 - #define MMC_RECEIVE_INTERRUPT_RXLPIUSCIS_LEN 1 - #define MMC_RECEIVE_INTERRUPT_RXLPIUSCIS_DEFAULT 0x0 - /*[field] RXLPITRCIS*/ - #define MMC_RECEIVE_INTERRUPT_RXLPITRCIS - #define MMC_RECEIVE_INTERRUPT_RXLPITRCIS_OFFSET 26 - #define MMC_RECEIVE_INTERRUPT_RXLPITRCIS_LEN 1 - #define MMC_RECEIVE_INTERRUPT_RXLPITRCIS_DEFAULT 0x0 - /*[field] RXPRMMCIS*/ - #define MMC_RECEIVE_INTERRUPT_RXPRMMCIS - #define MMC_RECEIVE_INTERRUPT_RXPRMMCIS_OFFSET 31 - #define MMC_RECEIVE_INTERRUPT_RXPRMMCIS_LEN 1 - #define MMC_RECEIVE_INTERRUPT_RXPRMMCIS_DEFAULT 0x0 - -struct mmc_receive_interrupt { - a_uint32_t rxgbfrmis:1; - a_uint32_t rxgboctis:1; - a_uint32_t rxgoctis:1; - a_uint32_t rxbcgfis:1; - a_uint32_t rxmcgfis:1; - a_uint32_t rxcrcerfis:1; - a_uint32_t rxruntfis:1; - a_uint32_t rxjaberfis:1; - a_uint32_t rxusizegfis:1; - a_uint32_t rxosizegfis:1; - a_uint32_t rx64octgbfis:1; - a_uint32_t rx65t127octgbfis:1; - a_uint32_t rx128t255octgbfis:1; - a_uint32_t rx256t511octgbfis:1; - a_uint32_t rx512t1023octgbfis:1; - a_uint32_t rx1024tmaxoctgbfis:1; - a_uint32_t rxucgfis:1; - a_uint32_t rxlenerfis:1; - a_uint32_t rxorangefis:1; - a_uint32_t rxpausfis:1; - a_uint32_t rxfovfis:1; - a_uint32_t rxvlangbfis:1; - a_uint32_t rxwdogfis:1; - a_uint32_t rxdisfcgbis:1; - a_uint32_t rxdisocgbis:1; - a_uint32_t rxlpiuscis:1; - a_uint32_t rxlpitrcis:1; - a_uint32_t _reserved0:4; - a_uint32_t rxprmmcis:1; -}; - -union mmc_receive_interrupt_u { - a_uint32_t val; - struct mmc_receive_interrupt bf; -}; - -/*[register] MMC_TRANSMIT_INTERRUPT*/ -#define MMC_TRANSMIT_INTERRUPT -#define MMC_TRANSMIT_INTERRUPT_ADDRESS 0x808 -#define MMC_TRANSMIT_INTERRUPT_NUM 2 -#define MMC_TRANSMIT_INTERRUPT_INC 0x4000 -#define MMC_TRANSMIT_INTERRUPT_TYPE REG_TYPE_RO -#define MMC_TRANSMIT_INTERRUPT_DEFAULT 0x0 - /*[field] TXGBOCTIS*/ - #define MMC_TRANSMIT_INTERRUPT_TXGBOCTIS - #define MMC_TRANSMIT_INTERRUPT_TXGBOCTIS_OFFSET 0 - #define MMC_TRANSMIT_INTERRUPT_TXGBOCTIS_LEN 1 - #define MMC_TRANSMIT_INTERRUPT_TXGBOCTIS_DEFAULT 0x0 - /*[field] TXGBFRMIS*/ - #define MMC_TRANSMIT_INTERRUPT_TXGBFRMIS - #define MMC_TRANSMIT_INTERRUPT_TXGBFRMIS_OFFSET 1 - #define MMC_TRANSMIT_INTERRUPT_TXGBFRMIS_LEN 1 - #define MMC_TRANSMIT_INTERRUPT_TXGBFRMIS_DEFAULT 0x0 - /*[field] TXBCGFIS*/ - #define MMC_TRANSMIT_INTERRUPT_TXBCGFIS - #define MMC_TRANSMIT_INTERRUPT_TXBCGFIS_OFFSET 2 - #define MMC_TRANSMIT_INTERRUPT_TXBCGFIS_LEN 1 - #define MMC_TRANSMIT_INTERRUPT_TXBCGFIS_DEFAULT 0x0 - /*[field] TXMCGFIS*/ - #define MMC_TRANSMIT_INTERRUPT_TXMCGFIS - #define MMC_TRANSMIT_INTERRUPT_TXMCGFIS_OFFSET 3 - #define MMC_TRANSMIT_INTERRUPT_TXMCGFIS_LEN 1 - #define MMC_TRANSMIT_INTERRUPT_TXMCGFIS_DEFAULT 0x0 - /*[field] TX64OCTGBFIS*/ - #define MMC_TRANSMIT_INTERRUPT_TX64OCTGBFIS - #define MMC_TRANSMIT_INTERRUPT_TX64OCTGBFIS_OFFSET 4 - #define MMC_TRANSMIT_INTERRUPT_TX64OCTGBFIS_LEN 1 - #define MMC_TRANSMIT_INTERRUPT_TX64OCTGBFIS_DEFAULT 0x0 - /*[field] TX65T127OCTGBFIS*/ - #define MMC_TRANSMIT_INTERRUPT_TX65T127OCTGBFIS - #define MMC_TRANSMIT_INTERRUPT_TX65T127OCTGBFIS_OFFSET 5 - #define MMC_TRANSMIT_INTERRUPT_TX65T127OCTGBFIS_LEN 1 - #define MMC_TRANSMIT_INTERRUPT_TX65T127OCTGBFIS_DEFAULT 0x0 - /*[field] TX128T255OCTGBFIS*/ - #define MMC_TRANSMIT_INTERRUPT_TX128T255OCTGBFIS - #define MMC_TRANSMIT_INTERRUPT_TX128T255OCTGBFIS_OFFSET 6 - #define MMC_TRANSMIT_INTERRUPT_TX128T255OCTGBFIS_LEN 1 - #define MMC_TRANSMIT_INTERRUPT_TX128T255OCTGBFIS_DEFAULT 0x0 - /*[field] TX256T511OCTGBFIS*/ - #define MMC_TRANSMIT_INTERRUPT_TX256T511OCTGBFIS - #define MMC_TRANSMIT_INTERRUPT_TX256T511OCTGBFIS_OFFSET 7 - #define MMC_TRANSMIT_INTERRUPT_TX256T511OCTGBFIS_LEN 1 - #define MMC_TRANSMIT_INTERRUPT_TX256T511OCTGBFIS_DEFAULT 0x0 - /*[field] TX512T1023OCTGBFIS*/ - #define MMC_TRANSMIT_INTERRUPT_TX512T1023OCTGBFIS - #define MMC_TRANSMIT_INTERRUPT_TX512T1023OCTGBFIS_OFFSET 8 - #define MMC_TRANSMIT_INTERRUPT_TX512T1023OCTGBFIS_LEN 1 - #define MMC_TRANSMIT_INTERRUPT_TX512T1023OCTGBFIS_DEFAULT 0x0 - /*[field] TX1024TMAXOCTGBFIS*/ - #define MMC_TRANSMIT_INTERRUPT_TX1024TMAXOCTGBFIS - #define MMC_TRANSMIT_INTERRUPT_TX1024TMAXOCTGBFIS_OFFSET 9 - #define MMC_TRANSMIT_INTERRUPT_TX1024TMAXOCTGBFIS_LEN 1 - #define MMC_TRANSMIT_INTERRUPT_TX1024TMAXOCTGBFIS_DEFAULT 0x0 - /*[field] TXUCGBFIS*/ - #define MMC_TRANSMIT_INTERRUPT_TXUCGBFIS - #define MMC_TRANSMIT_INTERRUPT_TXUCGBFIS_OFFSET 10 - #define MMC_TRANSMIT_INTERRUPT_TXUCGBFIS_LEN 1 - #define MMC_TRANSMIT_INTERRUPT_TXUCGBFIS_DEFAULT 0x0 - /*[field] TXMCGBFIS*/ - #define MMC_TRANSMIT_INTERRUPT_TXMCGBFIS - #define MMC_TRANSMIT_INTERRUPT_TXMCGBFIS_OFFSET 11 - #define MMC_TRANSMIT_INTERRUPT_TXMCGBFIS_LEN 1 - #define MMC_TRANSMIT_INTERRUPT_TXMCGBFIS_DEFAULT 0x0 - /*[field] TXBCGBFIS*/ - #define MMC_TRANSMIT_INTERRUPT_TXBCGBFIS - #define MMC_TRANSMIT_INTERRUPT_TXBCGBFIS_OFFSET 12 - #define MMC_TRANSMIT_INTERRUPT_TXBCGBFIS_LEN 1 - #define MMC_TRANSMIT_INTERRUPT_TXBCGBFIS_DEFAULT 0x0 - /*[field] TXUFLOWERFIS*/ - #define MMC_TRANSMIT_INTERRUPT_TXUFLOWERFIS - #define MMC_TRANSMIT_INTERRUPT_TXUFLOWERFIS_OFFSET 13 - #define MMC_TRANSMIT_INTERRUPT_TXUFLOWERFIS_LEN 1 - #define MMC_TRANSMIT_INTERRUPT_TXUFLOWERFIS_DEFAULT 0x0 - /*[field] TXGOCTIS*/ - #define MMC_TRANSMIT_INTERRUPT_TXGOCTIS - #define MMC_TRANSMIT_INTERRUPT_TXGOCTIS_OFFSET 14 - #define MMC_TRANSMIT_INTERRUPT_TXGOCTIS_LEN 1 - #define MMC_TRANSMIT_INTERRUPT_TXGOCTIS_DEFAULT 0x0 - /*[field] TXGFRMIS*/ - #define MMC_TRANSMIT_INTERRUPT_TXGFRMIS - #define MMC_TRANSMIT_INTERRUPT_TXGFRMIS_OFFSET 15 - #define MMC_TRANSMIT_INTERRUPT_TXGFRMIS_LEN 1 - #define MMC_TRANSMIT_INTERRUPT_TXGFRMIS_DEFAULT 0x0 - /*[field] TXPAUSFIS*/ - #define MMC_TRANSMIT_INTERRUPT_TXPAUSFIS - #define MMC_TRANSMIT_INTERRUPT_TXPAUSFIS_OFFSET 16 - #define MMC_TRANSMIT_INTERRUPT_TXPAUSFIS_LEN 1 - #define MMC_TRANSMIT_INTERRUPT_TXPAUSFIS_DEFAULT 0x0 - /*[field] TXVLANGFIS*/ - #define MMC_TRANSMIT_INTERRUPT_TXVLANGFIS - #define MMC_TRANSMIT_INTERRUPT_TXVLANGFIS_OFFSET 17 - #define MMC_TRANSMIT_INTERRUPT_TXVLANGFIS_LEN 1 - #define MMC_TRANSMIT_INTERRUPT_TXVLANGFIS_DEFAULT 0x0 - /*[field] TXLPIUSCIS*/ - #define MMC_TRANSMIT_INTERRUPT_TXLPIUSCIS - #define MMC_TRANSMIT_INTERRUPT_TXLPIUSCIS_OFFSET 18 - #define MMC_TRANSMIT_INTERRUPT_TXLPIUSCIS_LEN 1 - #define MMC_TRANSMIT_INTERRUPT_TXLPIUSCIS_DEFAULT 0x0 - /*[field] TXLPITRCIS*/ - #define MMC_TRANSMIT_INTERRUPT_TXLPITRCIS - #define MMC_TRANSMIT_INTERRUPT_TXLPITRCIS_OFFSET 19 - #define MMC_TRANSMIT_INTERRUPT_TXLPITRCIS_LEN 1 - #define MMC_TRANSMIT_INTERRUPT_TXLPITRCIS_DEFAULT 0x0 - /*[field] TXPRMMCIS*/ - #define MMC_TRANSMIT_INTERRUPT_TXPRMMCIS - #define MMC_TRANSMIT_INTERRUPT_TXPRMMCIS_OFFSET 31 - #define MMC_TRANSMIT_INTERRUPT_TXPRMMCIS_LEN 1 - #define MMC_TRANSMIT_INTERRUPT_TXPRMMCIS_DEFAULT 0x0 - -struct mmc_transmit_interrupt { - a_uint32_t txgboctis:1; - a_uint32_t txgbfrmis:1; - a_uint32_t txbcgfis:1; - a_uint32_t txmcgfis:1; - a_uint32_t tx64octgbfis:1; - a_uint32_t tx65t127octgbfis:1; - a_uint32_t tx128t255octgbfis:1; - a_uint32_t tx256t511octgbfis:1; - a_uint32_t tx512t1023octgbfis:1; - a_uint32_t tx1024tmaxoctgbfis:1; - a_uint32_t txucgbfis:1; - a_uint32_t txmcgbfis:1; - a_uint32_t txbcgbfis:1; - a_uint32_t txuflowerfis:1; - a_uint32_t txgoctis:1; - a_uint32_t txgfrmis:1; - a_uint32_t txpausfis:1; - a_uint32_t txvlangfis:1; - a_uint32_t txlpiuscis:1; - a_uint32_t txlpitrcis:1; - a_uint32_t _reserved0:11; - a_uint32_t txprmmcis:1; -}; - -union mmc_transmit_interrupt_u { - a_uint32_t val; - struct mmc_transmit_interrupt bf; -}; - -/*[register] MMC_RECEIVE_INTERRUPT_ENABLE*/ -#define MMC_RECEIVE_INTERRUPT_ENABLE -#define MMC_RECEIVE_INTERRUPT_ENABLE_ADDRESS 0x80c -#define MMC_RECEIVE_INTERRUPT_ENABLE_NUM 2 -#define MMC_RECEIVE_INTERRUPT_ENABLE_INC 0x4000 -#define MMC_RECEIVE_INTERRUPT_ENABLE_TYPE REG_TYPE_RO -#define MMC_RECEIVE_INTERRUPT_ENABLE_DEFAULT 0x0 - /*[field] RXGBFRMIE*/ - #define MMC_RECEIVE_INTERRUPT_ENABLE_RXGBFRMIE - #define MMC_RECEIVE_INTERRUPT_ENABLE_RXGBFRMIE_OFFSET 0 - #define MMC_RECEIVE_INTERRUPT_ENABLE_RXGBFRMIE_LEN 1 - #define MMC_RECEIVE_INTERRUPT_ENABLE_RXGBFRMIE_DEFAULT 0x0 - /*[field] RXGBOCTIE*/ - #define MMC_RECEIVE_INTERRUPT_ENABLE_RXGBOCTIE - #define MMC_RECEIVE_INTERRUPT_ENABLE_RXGBOCTIE_OFFSET 1 - #define MMC_RECEIVE_INTERRUPT_ENABLE_RXGBOCTIE_LEN 1 - #define MMC_RECEIVE_INTERRUPT_ENABLE_RXGBOCTIE_DEFAULT 0x0 - /*[field] RXGOCTIE*/ - #define MMC_RECEIVE_INTERRUPT_ENABLE_RXGOCTIE - #define MMC_RECEIVE_INTERRUPT_ENABLE_RXGOCTIE_OFFSET 2 - #define MMC_RECEIVE_INTERRUPT_ENABLE_RXGOCTIE_LEN 1 - #define MMC_RECEIVE_INTERRUPT_ENABLE_RXGOCTIE_DEFAULT 0x0 - /*[field] RXBCGFIE*/ - #define MMC_RECEIVE_INTERRUPT_ENABLE_RXBCGFIE - #define MMC_RECEIVE_INTERRUPT_ENABLE_RXBCGFIE_OFFSET 3 - #define MMC_RECEIVE_INTERRUPT_ENABLE_RXBCGFIE_LEN 1 - #define MMC_RECEIVE_INTERRUPT_ENABLE_RXBCGFIE_DEFAULT 0x0 - /*[field] RXMCGFIE*/ - #define MMC_RECEIVE_INTERRUPT_ENABLE_RXMCGFIE - #define MMC_RECEIVE_INTERRUPT_ENABLE_RXMCGFIE_OFFSET 4 - #define MMC_RECEIVE_INTERRUPT_ENABLE_RXMCGFIE_LEN 1 - #define MMC_RECEIVE_INTERRUPT_ENABLE_RXMCGFIE_DEFAULT 0x0 - /*[field] RXCRCERFIE*/ - #define MMC_RECEIVE_INTERRUPT_ENABLE_RXCRCERFIE - #define MMC_RECEIVE_INTERRUPT_ENABLE_RXCRCERFIE_OFFSET 5 - #define MMC_RECEIVE_INTERRUPT_ENABLE_RXCRCERFIE_LEN 1 - #define MMC_RECEIVE_INTERRUPT_ENABLE_RXCRCERFIE_DEFAULT 0x0 - /*[field] RXRUNTFIE*/ - #define MMC_RECEIVE_INTERRUPT_ENABLE_RXRUNTFIE - #define MMC_RECEIVE_INTERRUPT_ENABLE_RXRUNTFIE_OFFSET 6 - #define MMC_RECEIVE_INTERRUPT_ENABLE_RXRUNTFIE_LEN 1 - #define MMC_RECEIVE_INTERRUPT_ENABLE_RXRUNTFIE_DEFAULT 0x0 - /*[field] RXJABERFIE*/ - #define MMC_RECEIVE_INTERRUPT_ENABLE_RXJABERFIE - #define MMC_RECEIVE_INTERRUPT_ENABLE_RXJABERFIE_OFFSET 7 - #define MMC_RECEIVE_INTERRUPT_ENABLE_RXJABERFIE_LEN 1 - #define MMC_RECEIVE_INTERRUPT_ENABLE_RXJABERFIE_DEFAULT 0x0 - /*[field] RXUSIZEGFIE*/ - #define MMC_RECEIVE_INTERRUPT_ENABLE_RXUSIZEGFIE - #define MMC_RECEIVE_INTERRUPT_ENABLE_RXUSIZEGFIE_OFFSET 8 - #define MMC_RECEIVE_INTERRUPT_ENABLE_RXUSIZEGFIE_LEN 1 - #define MMC_RECEIVE_INTERRUPT_ENABLE_RXUSIZEGFIE_DEFAULT 0x0 - /*[field] RXOSIZEGFIE*/ - #define MMC_RECEIVE_INTERRUPT_ENABLE_RXOSIZEGFIE - #define MMC_RECEIVE_INTERRUPT_ENABLE_RXOSIZEGFIE_OFFSET 9 - #define MMC_RECEIVE_INTERRUPT_ENABLE_RXOSIZEGFIE_LEN 1 - #define MMC_RECEIVE_INTERRUPT_ENABLE_RXOSIZEGFIE_DEFAULT 0x0 - /*[field] RX64OCTGBFIE*/ - #define MMC_RECEIVE_INTERRUPT_ENABLE_RX64OCTGBFIE - #define MMC_RECEIVE_INTERRUPT_ENABLE_RX64OCTGBFIE_OFFSET 10 - #define MMC_RECEIVE_INTERRUPT_ENABLE_RX64OCTGBFIE_LEN 1 - #define MMC_RECEIVE_INTERRUPT_ENABLE_RX64OCTGBFIE_DEFAULT 0x0 - /*[field] RX65T127OCTGBFIE*/ - #define MMC_RECEIVE_INTERRUPT_ENABLE_RX65T127OCTGBFIE - #define MMC_RECEIVE_INTERRUPT_ENABLE_RX65T127OCTGBFIE_OFFSET 11 - #define MMC_RECEIVE_INTERRUPT_ENABLE_RX65T127OCTGBFIE_LEN 1 - #define MMC_RECEIVE_INTERRUPT_ENABLE_RX65T127OCTGBFIE_DEFAULT 0x0 - /*[field] RX128T255OCTGBFIE*/ - #define MMC_RECEIVE_INTERRUPT_ENABLE_RX128T255OCTGBFIE - #define MMC_RECEIVE_INTERRUPT_ENABLE_RX128T255OCTGBFIE_OFFSET 12 - #define MMC_RECEIVE_INTERRUPT_ENABLE_RX128T255OCTGBFIE_LEN 1 - #define MMC_RECEIVE_INTERRUPT_ENABLE_RX128T255OCTGBFIE_DEFAULT 0x0 - /*[field] RX256T511OCTGBFIE*/ - #define MMC_RECEIVE_INTERRUPT_ENABLE_RX256T511OCTGBFIE - #define MMC_RECEIVE_INTERRUPT_ENABLE_RX256T511OCTGBFIE_OFFSET 13 - #define MMC_RECEIVE_INTERRUPT_ENABLE_RX256T511OCTGBFIE_LEN 1 - #define MMC_RECEIVE_INTERRUPT_ENABLE_RX256T511OCTGBFIE_DEFAULT 0x0 - /*[field] RX512T1023OCTGBFIE*/ - #define MMC_RECEIVE_INTERRUPT_ENABLE_RX512T1023OCTGBFIE - #define MMC_RECEIVE_INTERRUPT_ENABLE_RX512T1023OCTGBFIE_OFFSET 14 - #define MMC_RECEIVE_INTERRUPT_ENABLE_RX512T1023OCTGBFIE_LEN 1 - #define MMC_RECEIVE_INTERRUPT_ENABLE_RX512T1023OCTGBFIE_DEFAULT 0x0 - /*[field] RX1024TMAXOCTGBFIE*/ - #define MMC_RECEIVE_INTERRUPT_ENABLE_RX1024TMAXOCTGBFIE - #define MMC_RECEIVE_INTERRUPT_ENABLE_RX1024TMAXOCTGBFIE_OFFSET 15 - #define MMC_RECEIVE_INTERRUPT_ENABLE_RX1024TMAXOCTGBFIE_LEN 1 - #define MMC_RECEIVE_INTERRUPT_ENABLE_RX1024TMAXOCTGBFIE_DEFAULT 0x0 - /*[field] RXUCGFIE*/ - #define MMC_RECEIVE_INTERRUPT_ENABLE_RXUCGFIE - #define MMC_RECEIVE_INTERRUPT_ENABLE_RXUCGFIE_OFFSET 16 - #define MMC_RECEIVE_INTERRUPT_ENABLE_RXUCGFIE_LEN 1 - #define MMC_RECEIVE_INTERRUPT_ENABLE_RXUCGFIE_DEFAULT 0x0 - /*[field] RXLENERFIE*/ - #define MMC_RECEIVE_INTERRUPT_ENABLE_RXLENERFIE - #define MMC_RECEIVE_INTERRUPT_ENABLE_RXLENERFIE_OFFSET 17 - #define MMC_RECEIVE_INTERRUPT_ENABLE_RXLENERFIE_LEN 1 - #define MMC_RECEIVE_INTERRUPT_ENABLE_RXLENERFIE_DEFAULT 0x0 - /*[field] RXORANGEFIE*/ - #define MMC_RECEIVE_INTERRUPT_ENABLE_RXORANGEFIE - #define MMC_RECEIVE_INTERRUPT_ENABLE_RXORANGEFIE_OFFSET 18 - #define MMC_RECEIVE_INTERRUPT_ENABLE_RXORANGEFIE_LEN 1 - #define MMC_RECEIVE_INTERRUPT_ENABLE_RXORANGEFIE_DEFAULT 0x0 - /*[field] RXPAUSFIE*/ - #define MMC_RECEIVE_INTERRUPT_ENABLE_RXPAUSFIE - #define MMC_RECEIVE_INTERRUPT_ENABLE_RXPAUSFIE_OFFSET 19 - #define MMC_RECEIVE_INTERRUPT_ENABLE_RXPAUSFIE_LEN 1 - #define MMC_RECEIVE_INTERRUPT_ENABLE_RXPAUSFIE_DEFAULT 0x0 - /*[field] RXFOVFIE*/ - #define MMC_RECEIVE_INTERRUPT_ENABLE_RXFOVFIE - #define MMC_RECEIVE_INTERRUPT_ENABLE_RXFOVFIE_OFFSET 20 - #define MMC_RECEIVE_INTERRUPT_ENABLE_RXFOVFIE_LEN 1 - #define MMC_RECEIVE_INTERRUPT_ENABLE_RXFOVFIE_DEFAULT 0x0 - /*[field] RXVLANGBFIE*/ - #define MMC_RECEIVE_INTERRUPT_ENABLE_RXVLANGBFIE - #define MMC_RECEIVE_INTERRUPT_ENABLE_RXVLANGBFIE_OFFSET 21 - #define MMC_RECEIVE_INTERRUPT_ENABLE_RXVLANGBFIE_LEN 1 - #define MMC_RECEIVE_INTERRUPT_ENABLE_RXVLANGBFIE_DEFAULT 0x0 - /*[field] RXWDOGFIE*/ - #define MMC_RECEIVE_INTERRUPT_ENABLE_RXWDOGFIE - #define MMC_RECEIVE_INTERRUPT_ENABLE_RXWDOGFIE_OFFSET 22 - #define MMC_RECEIVE_INTERRUPT_ENABLE_RXWDOGFIE_LEN 1 - #define MMC_RECEIVE_INTERRUPT_ENABLE_RXWDOGFIE_DEFAULT 0x0 - /*[field] RXDISFCIE*/ - #define MMC_RECEIVE_INTERRUPT_ENABLE_RXDISFCIE - #define MMC_RECEIVE_INTERRUPT_ENABLE_RXDISFCIE_OFFSET 23 - #define MMC_RECEIVE_INTERRUPT_ENABLE_RXDISFCIE_LEN 1 - #define MMC_RECEIVE_INTERRUPT_ENABLE_RXDISFCIE_DEFAULT 0x0 - /*[field] RXDISOCIE*/ - #define MMC_RECEIVE_INTERRUPT_ENABLE_RXDISOCIE - #define MMC_RECEIVE_INTERRUPT_ENABLE_RXDISOCIE_OFFSET 24 - #define MMC_RECEIVE_INTERRUPT_ENABLE_RXDISOCIE_LEN 1 - #define MMC_RECEIVE_INTERRUPT_ENABLE_RXDISOCIE_DEFAULT 0x0 - /*[field] RXLPIUSCIE*/ - #define MMC_RECEIVE_INTERRUPT_ENABLE_RXLPIUSCIE - #define MMC_RECEIVE_INTERRUPT_ENABLE_RXLPIUSCIE_OFFSET 25 - #define MMC_RECEIVE_INTERRUPT_ENABLE_RXLPIUSCIE_LEN 1 - #define MMC_RECEIVE_INTERRUPT_ENABLE_RXLPIUSCIE_DEFAULT 0x0 - /*[field] RXLPITRCIE*/ - #define MMC_RECEIVE_INTERRUPT_ENABLE_RXLPITRCIE - #define MMC_RECEIVE_INTERRUPT_ENABLE_RXLPITRCIE_OFFSET 26 - #define MMC_RECEIVE_INTERRUPT_ENABLE_RXLPITRCIE_LEN 1 - #define MMC_RECEIVE_INTERRUPT_ENABLE_RXLPITRCIE_DEFAULT 0x0 - /*[field] RXPRMMCISE*/ - #define MMC_RECEIVE_INTERRUPT_ENABLE_RXPRMMCISE - #define MMC_RECEIVE_INTERRUPT_ENABLE_RXPRMMCISE_OFFSET 31 - #define MMC_RECEIVE_INTERRUPT_ENABLE_RXPRMMCISE_LEN 1 - #define MMC_RECEIVE_INTERRUPT_ENABLE_RXPRMMCISE_DEFAULT 0x0 - -struct mmc_receive_interrupt_enable { - a_uint32_t rxgbfrmie:1; - a_uint32_t rxgboctie:1; - a_uint32_t rxgoctie:1; - a_uint32_t rxbcgfie:1; - a_uint32_t rxmcgfie:1; - a_uint32_t rxcrcerfie:1; - a_uint32_t rxruntfie:1; - a_uint32_t rxjaberfie:1; - a_uint32_t rxusizegfie:1; - a_uint32_t rxosizegfie:1; - a_uint32_t rx64octgbfie:1; - a_uint32_t rx65t127octgbfie:1; - a_uint32_t rx128t255octgbfie:1; - a_uint32_t rx256t511octgbfie:1; - a_uint32_t rx512t1023octgbfie:1; - a_uint32_t rx1024tmaxoctgbfie:1; - a_uint32_t rxucgfie:1; - a_uint32_t rxlenerfie:1; - a_uint32_t rxorangefie:1; - a_uint32_t rxpausfie:1; - a_uint32_t rxfovfie:1; - a_uint32_t rxvlangbfie:1; - a_uint32_t rxwdogfie:1; - a_uint32_t rxdisfcie:1; - a_uint32_t rxdisocie:1; - a_uint32_t rxlpiuscie:1; - a_uint32_t rxlpitrcie:1; - a_uint32_t _reserved0:4; - a_uint32_t rxprmmcise:1; -}; - -union mmc_receive_interrupt_enable_u { - a_uint32_t val; - struct mmc_receive_interrupt_enable bf; -}; - -/*[register] MMC_TRANSMIT_INTERRUPT_ENABLE*/ -#define MMC_TRANSMIT_INTERRUPT_ENABLE -#define MMC_TRANSMIT_INTERRUPT_ENABLE_ADDRESS 0x810 -#define MMC_TRANSMIT_INTERRUPT_ENABLE_NUM 2 -#define MMC_TRANSMIT_INTERRUPT_ENABLE_INC 0x4000 -#define MMC_TRANSMIT_INTERRUPT_ENABLE_TYPE REG_TYPE_RO -#define MMC_TRANSMIT_INTERRUPT_ENABLE_DEFAULT 0x0 - /*[field] TXGBOCTIE*/ - #define MMC_TRANSMIT_INTERRUPT_ENABLE_TXGBOCTIE - #define MMC_TRANSMIT_INTERRUPT_ENABLE_TXGBOCTIE_OFFSET 0 - #define MMC_TRANSMIT_INTERRUPT_ENABLE_TXGBOCTIE_LEN 1 - #define MMC_TRANSMIT_INTERRUPT_ENABLE_TXGBOCTIE_DEFAULT 0x0 - /*[field] TXGBFRMIE*/ - #define MMC_TRANSMIT_INTERRUPT_ENABLE_TXGBFRMIE - #define MMC_TRANSMIT_INTERRUPT_ENABLE_TXGBFRMIE_OFFSET 1 - #define MMC_TRANSMIT_INTERRUPT_ENABLE_TXGBFRMIE_LEN 1 - #define MMC_TRANSMIT_INTERRUPT_ENABLE_TXGBFRMIE_DEFAULT 0x0 - /*[field] TXBCGFIE*/ - #define MMC_TRANSMIT_INTERRUPT_ENABLE_TXBCGFIE - #define MMC_TRANSMIT_INTERRUPT_ENABLE_TXBCGFIE_OFFSET 2 - #define MMC_TRANSMIT_INTERRUPT_ENABLE_TXBCGFIE_LEN 1 - #define MMC_TRANSMIT_INTERRUPT_ENABLE_TXBCGFIE_DEFAULT 0x0 - /*[field] TXMCGFIE*/ - #define MMC_TRANSMIT_INTERRUPT_ENABLE_TXMCGFIE - #define MMC_TRANSMIT_INTERRUPT_ENABLE_TXMCGFIE_OFFSET 3 - #define MMC_TRANSMIT_INTERRUPT_ENABLE_TXMCGFIE_LEN 1 - #define MMC_TRANSMIT_INTERRUPT_ENABLE_TXMCGFIE_DEFAULT 0x0 - /*[field] TX64OCTGBFIE*/ - #define MMC_TRANSMIT_INTERRUPT_ENABLE_TX64OCTGBFIE - #define MMC_TRANSMIT_INTERRUPT_ENABLE_TX64OCTGBFIE_OFFSET 4 - #define MMC_TRANSMIT_INTERRUPT_ENABLE_TX64OCTGBFIE_LEN 1 - #define MMC_TRANSMIT_INTERRUPT_ENABLE_TX64OCTGBFIE_DEFAULT 0x0 - /*[field] TX65T127OCTGBFIE*/ - #define MMC_TRANSMIT_INTERRUPT_ENABLE_TX65T127OCTGBFIE - #define MMC_TRANSMIT_INTERRUPT_ENABLE_TX65T127OCTGBFIE_OFFSET 5 - #define MMC_TRANSMIT_INTERRUPT_ENABLE_TX65T127OCTGBFIE_LEN 1 - #define MMC_TRANSMIT_INTERRUPT_ENABLE_TX65T127OCTGBFIE_DEFAULT 0x0 - /*[field] TX128T255OCTGBFIE*/ - #define MMC_TRANSMIT_INTERRUPT_ENABLE_TX128T255OCTGBFIE - #define MMC_TRANSMIT_INTERRUPT_ENABLE_TX128T255OCTGBFIE_OFFSET 6 - #define MMC_TRANSMIT_INTERRUPT_ENABLE_TX128T255OCTGBFIE_LEN 1 - #define MMC_TRANSMIT_INTERRUPT_ENABLE_TX128T255OCTGBFIE_DEFAULT 0x0 - /*[field] TX256T511OCTGBFIE*/ - #define MMC_TRANSMIT_INTERRUPT_ENABLE_TX256T511OCTGBFIE - #define MMC_TRANSMIT_INTERRUPT_ENABLE_TX256T511OCTGBFIE_OFFSET 7 - #define MMC_TRANSMIT_INTERRUPT_ENABLE_TX256T511OCTGBFIE_LEN 1 - #define MMC_TRANSMIT_INTERRUPT_ENABLE_TX256T511OCTGBFIE_DEFAULT 0x0 - /*[field] TX512T1023OCTGBFIE*/ - #define MMC_TRANSMIT_INTERRUPT_ENABLE_TX512T1023OCTGBFIE - #define MMC_TRANSMIT_INTERRUPT_ENABLE_TX512T1023OCTGBFIE_OFFSET 8 - #define MMC_TRANSMIT_INTERRUPT_ENABLE_TX512T1023OCTGBFIE_LEN 1 - #define MMC_TRANSMIT_INTERRUPT_ENABLE_TX512T1023OCTGBFIE_DEFAULT 0x0 - /*[field] TX1024TMAXOCTGBFIE*/ - #define MMC_TRANSMIT_INTERRUPT_ENABLE_TX1024TMAXOCTGBFIE - #define MMC_TRANSMIT_INTERRUPT_ENABLE_TX1024TMAXOCTGBFIE_OFFSET 9 - #define MMC_TRANSMIT_INTERRUPT_ENABLE_TX1024TMAXOCTGBFIE_LEN 1 - #define MMC_TRANSMIT_INTERRUPT_ENABLE_TX1024TMAXOCTGBFIE_DEFAULT 0x0 - /*[field] TXUCGBFIE*/ - #define MMC_TRANSMIT_INTERRUPT_ENABLE_TXUCGBFIE - #define MMC_TRANSMIT_INTERRUPT_ENABLE_TXUCGBFIE_OFFSET 10 - #define MMC_TRANSMIT_INTERRUPT_ENABLE_TXUCGBFIE_LEN 1 - #define MMC_TRANSMIT_INTERRUPT_ENABLE_TXUCGBFIE_DEFAULT 0x0 - /*[field] TXMCGBFIE*/ - #define MMC_TRANSMIT_INTERRUPT_ENABLE_TXMCGBFIE - #define MMC_TRANSMIT_INTERRUPT_ENABLE_TXMCGBFIE_OFFSET 11 - #define MMC_TRANSMIT_INTERRUPT_ENABLE_TXMCGBFIE_LEN 1 - #define MMC_TRANSMIT_INTERRUPT_ENABLE_TXMCGBFIE_DEFAULT 0x0 - /*[field] TXBCGBFIE*/ - #define MMC_TRANSMIT_INTERRUPT_ENABLE_TXBCGBFIE - #define MMC_TRANSMIT_INTERRUPT_ENABLE_TXBCGBFIE_OFFSET 12 - #define MMC_TRANSMIT_INTERRUPT_ENABLE_TXBCGBFIE_LEN 1 - #define MMC_TRANSMIT_INTERRUPT_ENABLE_TXBCGBFIE_DEFAULT 0x0 - /*[field] TXUFLOWERFIE*/ - #define MMC_TRANSMIT_INTERRUPT_ENABLE_TXUFLOWERFIE - #define MMC_TRANSMIT_INTERRUPT_ENABLE_TXUFLOWERFIE_OFFSET 13 - #define MMC_TRANSMIT_INTERRUPT_ENABLE_TXUFLOWERFIE_LEN 1 - #define MMC_TRANSMIT_INTERRUPT_ENABLE_TXUFLOWERFIE_DEFAULT 0x0 - /*[field] TXGOCTIE*/ - #define MMC_TRANSMIT_INTERRUPT_ENABLE_TXGOCTIE - #define MMC_TRANSMIT_INTERRUPT_ENABLE_TXGOCTIE_OFFSET 14 - #define MMC_TRANSMIT_INTERRUPT_ENABLE_TXGOCTIE_LEN 1 - #define MMC_TRANSMIT_INTERRUPT_ENABLE_TXGOCTIE_DEFAULT 0x0 - /*[field] TXGFRMIE*/ - #define MMC_TRANSMIT_INTERRUPT_ENABLE_TXGFRMIE - #define MMC_TRANSMIT_INTERRUPT_ENABLE_TXGFRMIE_OFFSET 15 - #define MMC_TRANSMIT_INTERRUPT_ENABLE_TXGFRMIE_LEN 1 - #define MMC_TRANSMIT_INTERRUPT_ENABLE_TXGFRMIE_DEFAULT 0x0 - /*[field] TXPAUSFIE*/ - #define MMC_TRANSMIT_INTERRUPT_ENABLE_TXPAUSFIE - #define MMC_TRANSMIT_INTERRUPT_ENABLE_TXPAUSFIE_OFFSET 16 - #define MMC_TRANSMIT_INTERRUPT_ENABLE_TXPAUSFIE_LEN 1 - #define MMC_TRANSMIT_INTERRUPT_ENABLE_TXPAUSFIE_DEFAULT 0x0 - /*[field] TXVLANGFIE*/ - #define MMC_TRANSMIT_INTERRUPT_ENABLE_TXVLANGFIE - #define MMC_TRANSMIT_INTERRUPT_ENABLE_TXVLANGFIE_OFFSET 17 - #define MMC_TRANSMIT_INTERRUPT_ENABLE_TXVLANGFIE_LEN 1 - #define MMC_TRANSMIT_INTERRUPT_ENABLE_TXVLANGFIE_DEFAULT 0x0 - /*[field] TXLPIUSCIE*/ - #define MMC_TRANSMIT_INTERRUPT_ENABLE_TXLPIUSCIE - #define MMC_TRANSMIT_INTERRUPT_ENABLE_TXLPIUSCIE_OFFSET 18 - #define MMC_TRANSMIT_INTERRUPT_ENABLE_TXLPIUSCIE_LEN 1 - #define MMC_TRANSMIT_INTERRUPT_ENABLE_TXLPIUSCIE_DEFAULT 0x0 - /*[field] TXLPITRCIE*/ - #define MMC_TRANSMIT_INTERRUPT_ENABLE_TXLPITRCIE - #define MMC_TRANSMIT_INTERRUPT_ENABLE_TXLPITRCIE_OFFSET 19 - #define MMC_TRANSMIT_INTERRUPT_ENABLE_TXLPITRCIE_LEN 1 - #define MMC_TRANSMIT_INTERRUPT_ENABLE_TXLPITRCIE_DEFAULT 0x0 - /*[field] TXPRMMCISE*/ - #define MMC_TRANSMIT_INTERRUPT_ENABLE_TXPRMMCISE - #define MMC_TRANSMIT_INTERRUPT_ENABLE_TXPRMMCISE_OFFSET 31 - #define MMC_TRANSMIT_INTERRUPT_ENABLE_TXPRMMCISE_LEN 1 - #define MMC_TRANSMIT_INTERRUPT_ENABLE_TXPRMMCISE_DEFAULT 0x0 - -struct mmc_transmit_interrupt_enable { - a_uint32_t txgboctie:1; - a_uint32_t txgbfrmie:1; - a_uint32_t txbcgfie:1; - a_uint32_t txmcgfie:1; - a_uint32_t tx64octgbfie:1; - a_uint32_t tx65t127octgbfie:1; - a_uint32_t tx128t255octgbfie:1; - a_uint32_t tx256t511octgbfie:1; - a_uint32_t tx512t1023octgbfie:1; - a_uint32_t tx1024tmaxoctgbfie:1; - a_uint32_t txucgbfie:1; - a_uint32_t txmcgbfie:1; - a_uint32_t txbcgbfie:1; - a_uint32_t txuflowerfie:1; - a_uint32_t txgoctie:1; - a_uint32_t txgfrmie:1; - a_uint32_t txpausfie:1; - a_uint32_t txvlangfie:1; - a_uint32_t txlpiuscie:1; - a_uint32_t txlpitrcie:1; - a_uint32_t _reserved0:11; - a_uint32_t txprmmcise:1; -}; - -union mmc_transmit_interrupt_enable_u { - a_uint32_t val; - struct mmc_transmit_interrupt_enable bf; -}; - -#endif diff --git a/feeds/ipq807x/qca-ssdk/src/include/hsl/hsl.h b/feeds/ipq807x/qca-ssdk/src/include/hsl/hsl.h deleted file mode 100755 index 1bb923ab3..000000000 --- a/feeds/ipq807x/qca-ssdk/src/include/hsl/hsl.h +++ /dev/null @@ -1,244 +0,0 @@ -/* - * Copyright (c) 2012,2018, The Linux Foundation. All rights reserved. - * Permission to use, copy, modify, and/or distribute this software for - * any purpose with or without fee is hereby granted, provided that the - * above copyright notice and this permission notice appear in all copies. - * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES - * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR - * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES - * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN - * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT - * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. - */ - - -/*qca808x_start*/ -#ifndef _HSL_H -#define _HSL_H - -#ifdef __cplusplus -extern "C" { -#endif /* __cplusplus */ - -#include "ssdk_init.h" - - typedef sw_error_t - (*hsl_acl_rule_copy) (a_uint32_t dev_id, a_uint32_t src_addr, - a_uint32_t dest_addr, a_uint32_t size); - - typedef sw_error_t - (*hsl_acl_rule_invalid) (a_uint32_t dev_id, a_uint32_t addr, - a_uint32_t size); - - typedef sw_error_t - (*hsl_acl_addr_update) (a_uint32_t dev_id, a_uint32_t old_addr, - a_uint32_t new_addr, a_uint32_t info); - - typedef struct - { - hsl_acl_rule_copy acl_rule_copy; - hsl_acl_rule_invalid acl_rule_invalid; - hsl_acl_addr_update acl_addr_update; - } hsl_acl_func_t; -/*qca808x_end*/ - -#if 1 -extern sw_error_t reduce_hsl_reg_entry_get(a_uint32_t dev,a_uint32_t reg,a_uint8_t* value,a_uint8_t val_len); -#define HSL_REG_ENTRY_GET(rv, dev, reg, index, value, val_len) \ - rv = reduce_hsl_reg_entry_get(dev,reg##_OFFSET + ((a_uint32_t)index) * reg##_E_OFFSET,value,val_len); - - -extern sw_error_t reduce_hsl_reg_entry_set(a_uint32_t dev,a_uint32_t reg,a_uint8_t* value,a_uint8_t val_len); -#define HSL_REG_ENTRY_SET(rv, dev, reg, index, value, val_len) \ - rv = reduce_hsl_reg_entry_set(dev,reg##_OFFSET + ((a_uint32_t)index) * reg##_E_OFFSET,value,val_len); - -extern sw_error_t reduce_hsl_reg_field_get(a_uint32_t dev,a_uint32_t reg,a_uint32_t reg_offset, - a_uint32_t reg_offset_len,a_uint8_t* value,a_uint8_t val_len); -#define HSL_REG_FIELD_GET(rv, dev, reg, index, field, value, val_len) \ - rv = reduce_hsl_reg_field_get(dev,reg##_OFFSET + ((a_uint32_t)index) * reg##_E_OFFSET,\ - reg##_##field##_BOFFSET, \ - reg##_##field##_BLEN,value,val_len); - -extern sw_error_t reduce_hsl_reg_field_set(a_uint32_t dev,a_uint32_t reg,a_uint32_t reg_offset, - a_uint32_t reg_offset_len,a_uint8_t* value,a_uint8_t val_len); - -#define HSL_REG_FIELD_SET(rv, dev, reg, index, field, value, val_len) \ - rv = reduce_hsl_reg_field_set(dev,reg##_OFFSET + ((a_uint32_t)index) * reg##_E_OFFSET,\ - reg##_##field##_BOFFSET, \ - reg##_##field##_BLEN,value,val_len); - - - -extern sw_error_t reduce_hsl_reg_entry_gen_get(a_uint32_t dev,a_uint32_t addr,a_uint8_t* value,a_uint8_t val_len); -#define HSL_REG_ENTRY_GEN_GET(rv, dev, addr, reg_len, value, val_len) \ - rv = reduce_hsl_reg_entry_gen_get(dev,addr,(a_uint8_t*)value,val_len); - - -extern sw_error_t reduce_hsl_reg_entry_gen_set(a_uint32_t dev,a_uint32_t addr,a_uint8_t* value,a_uint8_t val_len); -#define HSL_REG_ENTRY_GEN_SET(rv, dev, addr, reg_len, value, val_len) \ - rv = reduce_hsl_reg_entry_gen_set(dev,addr,(a_uint8_t*)value,val_len); - - - - -extern sw_error_t reduce_hsl_reg_field_gen_get(a_uint32_t dev,a_uint32_t reg_addr, - a_uint32_t bitoffset, a_uint32_t field_len, a_uint8_t* value,a_uint8_t val_len); -#define HSL_REG_FIELD_GEN_GET(rv, dev, regaddr, bitlength, bitoffset, value, val_len) \ - rv = reduce_hsl_reg_field_gen_get(dev, regaddr, bitoffset, bitlength, (a_uint8_t*)value, val_len); - -extern sw_error_t reduce_hsl_reg_field_gen_set(a_uint32_t dev,a_uint32_t regaddr,a_uint32_t bitoffset, - a_uint32_t bitlength,a_uint8_t* value,a_uint8_t val_len); - -#define HSL_REG_FIELD_GEN_SET(rv, dev, regaddr, bitlength, bitoffset, value, val_len) \ - rv = reduce_hsl_reg_field_gen_set(dev,regaddr,bitoffset,bitlength, (a_uint8_t*)value,val_len); - - -/*qca808x_start*/ -extern sw_error_t reduce_hsl_phy_get(a_uint32_t dev,a_uint32_t phy_addr,a_uint32_t reg,a_uint16_t* value); -#define HSL_PHY_GET(rv, dev, phy_addr, reg, value) \ - rv = reduce_hsl_phy_get(dev,phy_addr,reg,value); - - -extern sw_error_t reduce_hsl_phy_set(a_uint32_t dev,a_uint32_t phy_addr,a_uint32_t reg,a_uint16_t value); -#define HSL_PHY_SET(rv, dev, phy_addr, reg, value) \ - rv = reduce_hsl_phy_set(dev,phy_addr,reg,value); - -extern sw_error_t hsl_phy_i2c_get(a_uint32_t dev,a_uint32_t phy_addr,a_uint32_t reg,a_uint16_t* value); -#define HSL_PHY_I2C_GET(rv, dev, phy_addr, reg, value) \ - rv = hsl_phy_i2c_get(dev,phy_addr,reg,value); - - -extern sw_error_t hsl_phy_i2c_set(a_uint32_t dev,a_uint32_t phy_addr,a_uint32_t reg,a_uint16_t value); -#define HSL_PHY_I2C_SET(rv, dev, phy_addr, reg, value) \ - rv = hsl_phy_i2c_set(dev,phy_addr,reg,value); -/*qca808x_end*/ - - - - -#else -#define HSL_REG_ENTRY_GET(rv, dev, reg, index, value, val_len) \ -do { \ - hsl_api_t *p_api = hsl_api_ptr_get(dev); \ - if (p_api) { \ - rv = p_api->reg_get(dev, reg##_OFFSET + ((a_uint32_t)index) * reg##_E_OFFSET,\ - (a_uint8_t*)value, (a_uint8_t)val_len); \ - } else { \ - rv = SW_NOT_INITIALIZED; \ - } \ -} while (0); - -#define HSL_REG_ENTRY_SET(rv, dev, reg, index, value, val_len) \ -do { \ - hsl_api_t *p_api = hsl_api_ptr_get(dev); \ - if (p_api) { \ - rv = p_api->reg_set (dev, reg##_OFFSET + ((a_uint32_t)index) * reg##_E_OFFSET,\ - (a_uint8_t*)value, (a_uint8_t)val_len); \ - } else { \ - rv = SW_NOT_INITIALIZED; \ - } \ -} while (0); - -#define HSL_REG_FIELD_GET(rv, dev, reg, index, field, value, val_len) \ -do { \ - hsl_api_t *p_api = hsl_api_ptr_get(dev); \ - if (p_api) { \ - rv = p_api->reg_field_get(dev, reg##_OFFSET + ((a_uint32_t)index) * reg##_E_OFFSET,\ - reg##_##field##_BOFFSET, \ - reg##_##field##_BLEN, (a_uint8_t*)value, val_len);\ - } else { \ - rv = SW_NOT_INITIALIZED; \ - } \ -} while (0); - -#define HSL_REG_FIELD_SET(rv, dev, reg, index, field, value, val_len) \ -do { \ - hsl_api_t *p_api = hsl_api_ptr_get(dev); \ - if (p_api){ \ - rv = p_api->reg_field_set(dev, reg##_OFFSET + ((a_uint32_t)index) * reg##_E_OFFSET,\ - reg##_##field##_BOFFSET, \ - reg##_##field##_BLEN, (a_uint8_t*)value, val_len);\ - } else { \ - rv = SW_NOT_INITIALIZED; \ - } \ -} while (0); - -#define HSL_REG_ENTRY_GEN_GET(rv, dev, addr, reg_len, value, val_len) \ -do { \ - hsl_api_t *p_api = hsl_api_ptr_get(dev); \ - if (p_api) { \ - rv = p_api->reg_get(dev, addr, (a_uint8_t*)value, val_len);\ - } else { \ - rv = SW_NOT_INITIALIZED; \ - } \ -} while (0); - -#define HSL_REG_ENTRY_GEN_SET(rv, dev, addr, reg_len, value, val_len) \ -do { \ - hsl_api_t *p_api = hsl_api_ptr_get(dev); \ - if (p_api) { \ - rv = p_api->reg_set(dev, addr, (a_uint8_t*)value, val_len); \ - } else { \ - rv = SW_NOT_INITIALIZED; \ - } \ -} while (0); - -#define HSL_REG_FIELD_GEN_GET(rv, dev, regaddr, bitlength, bitoffset, value, val_len) \ -do { \ - hsl_api_t *p_api = hsl_api_ptr_get(dev); \ - if (p_api) { \ - rv = p_api->reg_field_get(dev, regaddr, bitoffset, bitlength, \ - (a_uint8_t *) value, val_len);\ - } else { \ - rv = SW_NOT_INITIALIZED; \ - } \ -} while (0); - -#define HSL_REG_FIELD_GEN_SET(rv, dev, regaddr, bitlength, bitoffset, value, val_len) \ -do { \ - hsl_api_t *p_api = hsl_api_ptr_get(dev); \ - if (p_api) {\ - rv = p_api->reg_field_set(dev, regaddr, bitoffset, bitlength, \ - (a_uint8_t *) value, val_len);\ - } else { \ - rv = SW_NOT_INITIALIZED; \ - } \ -} while (0); - -#define HSL_PHY_GET(rv, dev, phy_addr, reg, value) \ -do { \ - hsl_api_t *p_api = hsl_api_ptr_get(dev); \ - if (p_api) { \ - rv = p_api->phy_get(dev, phy_addr, reg, value); \ - } else { \ - rv = SW_NOT_INITIALIZED; \ - } \ -} while (0); - -#define HSL_PHY_SET(rv, dev, phy_addr, reg, value) \ -do { \ - hsl_api_t *p_api = hsl_api_ptr_get(dev); \ - if (p_api) { \ - rv = p_api->phy_set(dev, phy_addr, reg, value); \ - } else { \ - rv = SW_NOT_INITIALIZED; \ - } \ -} while (0); -#endif -/*qca808x_start*/ -#if (defined(API_LOCK) \ -&& (defined(HSL_STANDALONG) || (defined(KERNEL_MODULE) && defined(USER_MODE)))) - extern aos_lock_t sw_hsl_api_lock; -#define HSL_API_LOCK aos_lock(&sw_hsl_api_lock) -#define HSL_API_UNLOCK aos_unlock(&sw_hsl_api_lock) -#else -#define HSL_API_LOCK -#define HSL_API_UNLOCK -#endif - -#ifdef __cplusplus -} -#endif /* __cplusplus */ -#endif /* _HSL_H */ -/*qca808x_end*/ diff --git a/feeds/ipq807x/qca-ssdk/src/include/hsl/hsl_acl.h b/feeds/ipq807x/qca-ssdk/src/include/hsl/hsl_acl.h deleted file mode 100755 index ab9518561..000000000 --- a/feeds/ipq807x/qca-ssdk/src/include/hsl/hsl_acl.h +++ /dev/null @@ -1,46 +0,0 @@ -/* - * Copyright (c) 2012, The Linux Foundation. All rights reserved. - * Permission to use, copy, modify, and/or distribute this software for - * any purpose with or without fee is hereby granted, provided that the - * above copyright notice and this permission notice appear in all copies. - * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES - * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR - * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES - * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN - * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT - * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. - */ - - - -#ifndef _HSL_ACL_H_ -#define _HSL_ACL_H_ - -#ifdef __cplusplus -extern "c" { -#endif - - sw_error_t - hsl_acl_pool_creat(a_uint32_t dev_id, a_uint32_t blk_nr, a_uint32_t rsc_nr); - - sw_error_t - hsl_acl_pool_destroy(a_uint32_t dev_id); - - sw_error_t - hsl_acl_blk_alloc(a_uint32_t dev_id, a_uint32_t pri, a_uint32_t size, - a_uint32_t info, a_uint32_t * addr); - - sw_error_t - hsl_acl_blk_free(a_uint32_t dev_id, a_uint32_t addr); - - sw_error_t - hsl_acl_blk_resize(a_uint32_t dev_id, a_uint32_t addr, a_uint32_t new_size); - - sw_error_t - hsl_acl_free_rsc_get(a_uint32_t dev_id, a_uint32_t * free_rsc); - -#ifdef __cplusplus -} -#endif /* __cplusplus */ -#endif /*_HSL_ACL_H_ */ diff --git a/feeds/ipq807x/qca-ssdk/src/include/hsl/hsl_api.h b/feeds/ipq807x/qca-ssdk/src/include/hsl/hsl_api.h deleted file mode 100755 index 7ea0cc35d..000000000 --- a/feeds/ipq807x/qca-ssdk/src/include/hsl/hsl_api.h +++ /dev/null @@ -1,2619 +0,0 @@ -/* - * Copyright (c) 2012, 2015, 2017-2018, The Linux Foundation. All rights reserved. - * Permission to use, copy, modify, and/or distribute this software for - * any purpose with or without fee is hereby granted, provided that the - * above copyright notice and this permission notice appear in all copies. - * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES - * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR - * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES - * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN - * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT - * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. - */ - - -/*qca808x_start*/ -#ifndef _HSL_API_H -#define _HSL_API_H - -#ifdef __cplusplus -extern "C" -{ -#endif /* __cplusplus */ - -#include "fal.h" -/*qca808x_end*/ - - /* Misc */ -#define MISC_FUNC_PROTOTYPE_DEF - typedef sw_error_t - (*hsl_arp_status_set) (a_uint32_t dev_id, a_bool_t enable); - - typedef sw_error_t - (*hsl_arp_status_get) (a_uint32_t dev_id, a_bool_t * enable); - - typedef sw_error_t - (*hsl_frame_max_size_set) (a_uint32_t dev_id, a_uint32_t size); - - typedef sw_error_t - (*hsl_frame_max_size_get) (a_uint32_t dev_id, a_uint32_t * size); - - typedef sw_error_t - (*hsl_port_unk_sa_cmd_set) (a_uint32_t dev_id, fal_port_t port_id, - fal_fwd_cmd_t cmd); - - typedef sw_error_t - (*hsl_port_unk_sa_cmd_get) (a_uint32_t dev_id, fal_port_t port_id, - fal_fwd_cmd_t * cmd); - - typedef sw_error_t - (*hsl_port_unk_uc_filter_set) (a_uint32_t dev_id, fal_port_t port_id, - a_bool_t enable); - - typedef sw_error_t - (*hsl_port_unk_uc_filter_get) (a_uint32_t dev_id, fal_port_t port_id, - a_bool_t * enable); - - typedef sw_error_t - (*hsl_port_unk_mc_filter_set) (a_uint32_t dev_id, fal_port_t port_id, - a_bool_t enable); - - typedef sw_error_t - (*hsl_port_unk_mc_filter_get) (a_uint32_t dev_id, fal_port_t port_id, - a_bool_t * enable); - - typedef sw_error_t - (*hsl_port_bc_filter_set) (a_uint32_t dev_id, fal_port_t port_id, - a_bool_t enable); - - typedef sw_error_t - (*hsl_port_bc_filter_get) (a_uint32_t dev_id, fal_port_t port_id, - a_bool_t * enable); - - typedef sw_error_t - (*hsl_cpu_port_status_set) (a_uint32_t dev_id, a_bool_t enable); - - typedef sw_error_t - (*hsl_cpu_port_status_get) (a_uint32_t dev_id, a_bool_t * enable); - - typedef sw_error_t - (*hsl_bc_to_cpu_port_set) (a_uint32_t dev_id, a_bool_t enable); - - typedef sw_error_t - (*hsl_bc_to_cpu_port_get) (a_uint32_t dev_id, a_bool_t * enable); - - typedef sw_error_t - (*hsl_port_dhcp_set) (a_uint32_t dev_id, fal_port_t port_id, - a_bool_t enable); - - typedef sw_error_t - (*hsl_pppoe_cmd_set) (a_uint32_t dev_id, fal_fwd_cmd_t cmd); - - typedef sw_error_t - (*hsl_pppoe_cmd_get) (a_uint32_t dev_id, fal_fwd_cmd_t * cmd); - - typedef sw_error_t - (*hsl_pppoe_status_set) (a_uint32_t dev_id, a_bool_t enable); - - typedef sw_error_t - (*hsl_pppoe_status_get) (a_uint32_t dev_id, a_bool_t * enable); - - typedef sw_error_t - (*hsl_port_dhcp_get) (a_uint32_t dev_id, fal_port_t port_id, - a_bool_t * enable); - - typedef sw_error_t - (*hsl_arp_cmd_set) (a_uint32_t dev_id, fal_fwd_cmd_t cmd); - - typedef sw_error_t - (*hsl_arp_cmd_get) (a_uint32_t dev_id, fal_fwd_cmd_t * cmd); - - typedef sw_error_t - (*hsl_eapol_cmd_set) (a_uint32_t dev_id, fal_fwd_cmd_t cmd); - - typedef sw_error_t - (*hsl_eapol_cmd_get) (a_uint32_t dev_id, fal_fwd_cmd_t * cmd); - - typedef sw_error_t - (*hsl_pppoe_session_add) (a_uint32_t dev_id, a_uint32_t session_id, - a_bool_t strip_hdr); - - typedef sw_error_t - (*hsl_pppoe_session_del) (a_uint32_t dev_id, a_uint32_t session_id); - - typedef sw_error_t - (*hsl_pppoe_session_get) (a_uint32_t dev_id, a_uint32_t session_id, - a_bool_t * strip_hdr); - - typedef sw_error_t - (*hsl_eapol_status_set) (a_uint32_t dev_id, a_uint32_t port_id, - a_bool_t enable); - - typedef sw_error_t - (*hsl_eapol_status_get) (a_uint32_t dev_id, a_uint32_t port_id, - a_bool_t * enable); - - typedef sw_error_t - (*hsl_ripv1_status_set) (a_uint32_t dev_id, a_bool_t enable); - - typedef sw_error_t - (*hsl_ripv1_status_get) (a_uint32_t dev_id, a_bool_t * enable); - - typedef sw_error_t - (*hsl_port_arp_req_status_set) (a_uint32_t dev_id, fal_port_t port_id, - a_bool_t enable); - - typedef sw_error_t - (*hsl_port_arp_req_status_get) (a_uint32_t dev_id, fal_port_t port_id, - a_bool_t * enable); - - typedef sw_error_t - (*hsl_port_arp_ack_status_set) (a_uint32_t dev_id, fal_port_t port_id, - a_bool_t enable); - - typedef sw_error_t - (*hsl_port_arp_ack_status_get) (a_uint32_t dev_id, fal_port_t port_id, - a_bool_t * enable); - - typedef sw_error_t - (*hsl_pppoe_session_table_add) (a_uint32_t dev_id, - fal_pppoe_session_t * session_tbl); - - typedef sw_error_t - (*hsl_pppoe_session_table_del) (a_uint32_t dev_id, - fal_pppoe_session_t * session_tbl); - - typedef sw_error_t - (*hsl_pppoe_session_table_get) (a_uint32_t dev_id, - fal_pppoe_session_t * session_tbl); - - typedef sw_error_t - (*hsl_pppoe_session_id_set) (a_uint32_t dev_id, a_uint32_t index, - a_uint32_t id); - - typedef sw_error_t - (*hsl_pppoe_session_id_get) (a_uint32_t dev_id, a_uint32_t index, - a_uint32_t * id); - - typedef sw_error_t - (*hsl_intr_mask_set) (a_uint32_t dev_id, a_uint32_t intr_mask); - - typedef sw_error_t - (*hsl_intr_mask_get) (a_uint32_t dev_id, a_uint32_t * intr_mask); - - typedef sw_error_t - (*hsl_intr_status_get) (a_uint32_t dev_id, a_uint32_t * intr_status); - - typedef sw_error_t - (*hsl_intr_status_clear) (a_uint32_t dev_id, a_uint32_t intr_status); - - typedef sw_error_t - (*hsl_intr_port_link_mask_set) (a_uint32_t dev_id, fal_port_t port_id, - a_uint32_t intr_mask); - - typedef sw_error_t - (*hsl_intr_port_link_mask_get) (a_uint32_t dev_id, fal_port_t port_id, - a_uint32_t * intr_mask); - - typedef sw_error_t - (*hsl_intr_port_link_status_get) (a_uint32_t dev_id, fal_port_t port_id, - a_uint32_t * intr_mask); - - typedef sw_error_t - (*hsl_intr_mask_mac_linkchg_set) (a_uint32_t dev_id, fal_port_t port_id, - a_bool_t enable); - - typedef sw_error_t - (*hsl_intr_mask_mac_linkchg_get) (a_uint32_t dev_id, fal_port_t port_id, - a_bool_t * enable); - - typedef sw_error_t - (*hsl_intr_status_mac_linkchg_get) (a_uint32_t dev_id, - fal_pbmp_t * port_bitmap); - - typedef sw_error_t (*hsl_intr_status_mac_linkchg_clear) (a_uint32_t dev_id); - - typedef sw_error_t - (*hsl_cpu_vid_en_set) (a_uint32_t dev_id, a_bool_t enable); - - typedef sw_error_t - (*hsl_cpu_vid_en_get) (a_uint32_t dev_id, a_bool_t * enable); - - typedef sw_error_t - (*hsl_rtd_pppoe_en_set) (a_uint32_t dev_id, a_bool_t enable); - - typedef sw_error_t - (*hsl_rtd_pppoe_en_get) (a_uint32_t dev_id, a_bool_t * enable); - - typedef sw_error_t - (*hsl_global_macaddr_set) (a_uint32_t dev_id, fal_mac_addr_t * addr); - - typedef sw_error_t - (*hsl_global_macaddr_get) (a_uint32_t dev_id, fal_mac_addr_t * addr); - - typedef sw_error_t - (*hsl_lldp_status_set) (a_uint32_t dev_id, a_bool_t enable); - - typedef sw_error_t - (*hsl_lldp_status_get) (a_uint32_t dev_id, a_bool_t * enable); - - typedef sw_error_t - (*hsl_frame_crc_reserve_set) (a_uint32_t dev_id, a_bool_t enable); - - typedef sw_error_t - (*hsl_frame_crc_reserve_get) (a_uint32_t dev_id, a_bool_t * enable); - - - typedef sw_error_t - (*hsl_register_dump) (a_uint32_t dev_id,a_uint32_t register_idx, fal_reg_dump_t * reg_dump); - - typedef sw_error_t - (*hsl_debug_register_dump) (a_uint32_t dev_id, fal_debug_reg_dump_t * reg_dump); - /*qca808x_start*/ - - /* Port Control */ -#define PORT_CONTROL_FUNC_PROTOTYPE_DEF - typedef sw_error_t - (*hsl_port_duplex_get) (a_uint32_t dev_id, fal_port_t port_id, - fal_port_duplex_t * pduplex); - - typedef sw_error_t - (*hsl_port_duplex_set) (a_uint32_t dev_id, fal_port_t port_id, - fal_port_duplex_t duplex); - - typedef sw_error_t - (*hsl_port_speed_get) (a_uint32_t dev_id, fal_port_t port_id, - fal_port_speed_t * pspeed); - - typedef sw_error_t - (*hsl_port_autoneg_status_get) (a_uint32_t dev_id, fal_port_t port_id, - a_bool_t * status); - - typedef sw_error_t - (*hsl_port_speed_set) (a_uint32_t dev_id, fal_port_t port_id, - fal_port_speed_t speed); - - typedef sw_error_t - (*hsl_port_autoneg_enable) (a_uint32_t dev_id, fal_port_t port_id); - - typedef sw_error_t - (*hsl_port_autoneg_restart) (a_uint32_t dev_id, fal_port_t port_id); - - typedef sw_error_t - (*hsl_port_autoneg_adv_get) (a_uint32_t dev_id, fal_port_t port_id, - a_uint32_t * autoadv); - - typedef sw_error_t - (*hsl_port_autoneg_adv_set) (a_uint32_t dev_id, fal_port_t port_id, - a_uint32_t autoadv); - - typedef sw_error_t - (*hsl_port_hdr_status_set) (a_uint32_t dev_id, fal_port_t port_id, - a_bool_t enable); - - typedef sw_error_t - (*hsl_port_hdr_status_get) (a_uint32_t dev_id, fal_port_t port_id, - a_bool_t * enable); - - typedef sw_error_t - (*hsl_port_flowctrl_set) (a_uint32_t dev_id, fal_port_t port_id, - a_bool_t enable); - - typedef sw_error_t - (*hsl_port_flowctrl_get) (a_uint32_t dev_id, fal_port_t port_id, - a_bool_t * enable); -typedef sw_error_t - (*hsl_port_flowctrl_thresh_set) (a_uint32_t dev_id, fal_port_t port_id, - a_uint8_t on, a_uint8_t off); - - typedef sw_error_t - (*hsl_port_flowctrl_forcemode_set) (a_uint32_t dev_id, fal_port_t port_id, - a_bool_t enable); - - typedef sw_error_t - (*hsl_port_flowctrl_forcemode_get) (a_uint32_t dev_id, fal_port_t port_id, - a_bool_t * enable); - - typedef sw_error_t - (*hsl_port_powersave_set) (a_uint32_t dev_id, fal_port_t port_id, - a_bool_t enable); - - - typedef sw_error_t - (*hsl_port_powersave_get) (a_uint32_t dev_id, fal_port_t port_id, - a_bool_t * enable); - - - typedef sw_error_t - (*hsl_port_hibernate_set) (a_uint32_t dev_id, fal_port_t port_id, - a_bool_t enable); - - - typedef sw_error_t - (*hsl_port_hibernate_get) (a_uint32_t dev_id, fal_port_t port_id, - a_bool_t * enable); - - - typedef sw_error_t - (*hsl_port_cdt) (a_uint32_t dev_id, fal_port_t port_id, - a_uint32_t mdi_pair, fal_cable_status_t * cable_status, - a_uint32_t * cable_len); - - typedef sw_error_t - (*hsl_port_rxhdr_mode_set) (a_uint32_t dev_id, fal_port_t port_id, - fal_port_header_mode_t mode); - - typedef sw_error_t - (*hsl_port_rxhdr_mode_get) (a_uint32_t dev_id, fal_port_t port_id, - fal_port_header_mode_t * mode); - - typedef sw_error_t - (*hsl_port_txhdr_mode_set) (a_uint32_t dev_id, fal_port_t port_id, - fal_port_header_mode_t mode); - - typedef sw_error_t - (*hsl_port_txhdr_mode_get) (a_uint32_t dev_id, fal_port_t port_id, - fal_port_header_mode_t * mode); - - typedef sw_error_t - (*hsl_header_type_set) (a_uint32_t dev_id, a_bool_t enable, - a_uint32_t type); - - typedef sw_error_t - (*hsl_header_type_get) (a_uint32_t dev_id, a_bool_t * enable, - a_uint32_t * type); - - typedef sw_error_t - (*hsl_port_txmac_status_set) (a_uint32_t dev_id, fal_port_t port_id, - a_bool_t enable); - - typedef sw_error_t - (*hsl_port_txmac_status_get) (a_uint32_t dev_id, fal_port_t port_id, - a_bool_t * enable); - - typedef sw_error_t - (*hsl_port_rxmac_status_set) (a_uint32_t dev_id, fal_port_t port_id, - a_bool_t enable); - - typedef sw_error_t - (*hsl_port_rxmac_status_get) (a_uint32_t dev_id, fal_port_t port_id, - a_bool_t * enable); - - typedef sw_error_t - (*hsl_port_txfc_status_set) (a_uint32_t dev_id, fal_port_t port_id, - a_bool_t enable); - - typedef sw_error_t - (*hsl_port_txfc_status_get) (a_uint32_t dev_id, fal_port_t port_id, - a_bool_t * enable); - - typedef sw_error_t - (*hsl_port_rxfc_status_set) (a_uint32_t dev_id, fal_port_t port_id, - a_bool_t enable); - - typedef sw_error_t - (*hsl_port_rxfc_status_get) (a_uint32_t dev_id, fal_port_t port_id, - a_bool_t * enable); - - typedef sw_error_t - (*hsl_port_bp_status_set) (a_uint32_t dev_id, fal_port_t port_id, - a_bool_t enable); - - typedef sw_error_t - (*hsl_port_bp_status_get) (a_uint32_t dev_id, fal_port_t port_id, - a_bool_t * enable); - - typedef sw_error_t - (*hsl_port_link_forcemode_set) (a_uint32_t dev_id, fal_port_t port_id, - a_bool_t enable); - - typedef sw_error_t - (*hsl_port_link_forcemode_get) (a_uint32_t dev_id, fal_port_t port_id, - a_bool_t * enable); - - typedef sw_error_t - (*hsl_port_link_status_get) (a_uint32_t dev_id, fal_port_t port_id, - a_bool_t * status); - - typedef sw_error_t - (*hsl_ports_link_status_get) (a_uint32_t dev_id, a_uint32_t * status); - - typedef sw_error_t - (*hsl_port_mac_loopback_set) (a_uint32_t dev_id, fal_port_t port_id, - a_bool_t enable); - - typedef sw_error_t - (*hsl_port_mac_loopback_get) (a_uint32_t dev_id, fal_port_t port_id, - a_bool_t * enable); - - typedef sw_error_t - (*hsl_port_congestion_drop_set) (a_uint32_t dev_id, fal_port_t port_id, - a_uint32_t queue_id, a_bool_t enable); - - typedef sw_error_t - (*hsl_port_congestion_drop_get) (a_uint32_t dev_id, fal_port_t port_id, - a_uint32_t queue_id, a_bool_t * enable); - - typedef sw_error_t - (*hsl_ring_flow_ctrl_thres_set) (a_uint32_t dev_id, a_uint32_t ring_id, - a_uint8_t on_thres, a_uint8_t off_thres); - - typedef sw_error_t - (*hsl_ring_flow_ctrl_thres_get) (a_uint32_t dev_id, a_uint32_t ring_id, - a_uint8_t * on_thres, - a_uint8_t * off_thres); - - typedef sw_error_t - (*hsl_port_8023az_set) (a_uint32_t dev_id, fal_port_t port_id, - a_bool_t enable); - - - typedef sw_error_t - (*hsl_port_8023az_get) (a_uint32_t dev_id, fal_port_t port_id, - a_bool_t * enable); - - typedef sw_error_t - (*hsl_port_mdix_set) (a_uint32_t dev_id, fal_port_t port_id, - fal_port_mdix_mode_t mode); - - typedef sw_error_t - (*hsl_port_mdix_get) (a_uint32_t dev_id, fal_port_t port_id, - fal_port_mdix_mode_t * mode); - - typedef sw_error_t - (*hsl_port_mdix_status_get) (a_uint32_t dev_id, fal_port_t port_id, - fal_port_mdix_status_t * mode); - - typedef sw_error_t - (*hsl_port_combo_prefer_medium_set) (a_uint32_t dev_id, - fal_port_t port_id, - fal_port_medium_t medium); - - typedef sw_error_t - (*hsl_port_combo_prefer_medium_get) (a_uint32_t dev_id, - fal_port_t port_id, - fal_port_medium_t * medium); - - typedef sw_error_t - (*hsl_port_combo_medium_status_get) (a_uint32_t dev_id, - fal_port_t port_id, - fal_port_medium_t * medium); - - typedef sw_error_t - (*hsl_port_combo_fiber_mode_set) (a_uint32_t dev_id, fal_port_t port_id, - fal_port_fiber_mode_t mode); - - typedef sw_error_t - (*hsl_port_combo_fiber_mode_get) (a_uint32_t dev_id, fal_port_t port_id, - fal_port_fiber_mode_t * mode); - - typedef sw_error_t - (*hsl_port_local_loopback_set) (a_uint32_t dev_id, fal_port_t port_id, - a_bool_t enable); - - typedef sw_error_t - (*hsl_port_local_loopback_get) (a_uint32_t dev_id, fal_port_t port_id, - a_bool_t * enable); - - typedef sw_error_t - (*hsl_port_remote_loopback_set) (a_uint32_t dev_id, fal_port_t port_id, - a_bool_t enable); - - typedef sw_error_t - (*hsl_port_remote_loopback_get) (a_uint32_t dev_id, fal_port_t port_id, - a_bool_t * enable); - - typedef sw_error_t - (*hsl_port_reset) (a_uint32_t dev_id, fal_port_t port_id); - - typedef sw_error_t - (*hsl_port_power_off) (a_uint32_t dev_id, fal_port_t port_id); - - typedef sw_error_t - (*hsl_port_power_on) (a_uint32_t dev_id, fal_port_t port_id); - - typedef sw_error_t - (*hsl_port_phy_id_get) (a_uint32_t dev_id, fal_port_t port_id,a_uint16_t * org_id, a_uint16_t * rev_id); - - typedef sw_error_t - (*hsl_port_wol_status_set) (a_uint32_t dev_id, fal_port_t port_id,a_bool_t enable); - - typedef sw_error_t - (*hsl_port_wol_status_get) (a_uint32_t dev_id, fal_port_t port_id,a_bool_t *enable); - - typedef sw_error_t - (*hsl_port_magic_frame_mac_set) (a_uint32_t dev_id, fal_port_t port_id,fal_mac_addr_t * mac); - - typedef sw_error_t - (*hsl_port_magic_frame_mac_get) (a_uint32_t dev_id, fal_port_t port_id,fal_mac_addr_t * mac); - - typedef sw_error_t - (*hsl_port_interface_mode_set) (a_uint32_t dev_id, fal_port_t port_id, - fal_port_interface_mode_t mode); - - typedef sw_error_t - (*hsl_port_interface_mode_get) (a_uint32_t dev_id, fal_port_t port_id, - fal_port_interface_mode_t * mode); - typedef sw_error_t - (*hsl_port_interface_mode_apply) (a_uint32_t dev_id); - - typedef sw_error_t - (*hsl_port_interface_mode_status_get) (a_uint32_t dev_id, fal_port_t port_id, - fal_port_interface_mode_t * mode); - typedef sw_error_t - (*hsl_port_counter_set) (a_uint32_t dev_id, fal_port_t port_id, - a_bool_t enable); - typedef sw_error_t - (*hsl_port_counter_get) (a_uint32_t dev_id, fal_port_t port_id, - a_bool_t * enable); - typedef sw_error_t - (*hsl_port_counter_show) (a_uint32_t dev_id, fal_port_t port_id, - fal_port_counter_info_t * counter_info); -/*qca808x_end*/ - - /* VLAN */ -#define VLAN_FUNC_PROTOTYPE_DEF - typedef sw_error_t - (*hsl_vlan_entry_append) (a_uint32_t dev_id, - const fal_vlan_t * vlan_entry); - - typedef sw_error_t - (*hsl_vlan_create) (a_uint32_t dev_id, a_uint32_t vlan_id); - - typedef sw_error_t - (*hsl_vlan_next) (a_uint32_t dev_id, a_uint32_t vlan_id, - fal_vlan_t * p_vlan); - - typedef sw_error_t - (*hsl_vlan_find) (a_uint32_t dev_id, a_uint32_t vlan_id, - fal_vlan_t * p_vlan); - - typedef sw_error_t - (*hsl_vlan_member_update) (a_uint32_t dev_id, a_uint32_t vlan_id, - fal_pbmp_t member, fal_pbmp_t u_member); - - typedef sw_error_t - (*hsl_vlan_delete) (a_uint32_t dev_id, a_uint32_t vlan_id); - - typedef sw_error_t (*hsl_vlan_flush) (a_uint32_t dev_id); - - typedef sw_error_t - (*hsl_vlan_fid_set) (a_uint32_t dev_id, a_uint32_t vlan_id, - a_uint32_t fid); - - typedef sw_error_t - (*hsl_vlan_fid_get) (a_uint32_t dev_id, a_uint32_t vlan_id, - a_uint32_t * fid); - - typedef sw_error_t - (*hsl_vlan_member_add) (a_uint32_t dev_id, a_uint32_t vlan_id, - fal_port_t port_id, fal_pt_1q_egmode_t port_info); - - typedef sw_error_t - (*hsl_vlan_member_del) (a_uint32_t dev_id, a_uint32_t vlan_id, - fal_port_t port_id); - - typedef sw_error_t - (*hsl_vlan_learning_state_set) (a_uint32_t dev_id, a_uint32_t vlan_id, - a_bool_t enable); - - typedef sw_error_t - (*hsl_vlan_learning_state_get) (a_uint32_t dev_id, a_uint32_t vlan_id, - a_bool_t * enable); - - /* Port Vlan */ -#define PORT_VLAN_FUNC_PROTOTYPE_DEF - typedef sw_error_t - (*hsl_port_1qmode_get) (a_uint32_t dev_id, fal_port_t port_id, - fal_pt_1qmode_t * pport_1qmode); - - typedef sw_error_t - (*hsl_port_1qmode_set) (a_uint32_t dev_id, fal_port_t port_id, - fal_pt_1qmode_t port_1qmode); - - typedef sw_error_t - (*hsl_port_egvlanmode_get) (a_uint32_t dev_id, fal_port_t port_id, - fal_pt_1q_egmode_t * pport_egvlanmode); - - typedef sw_error_t - (*hsl_port_egvlanmode_set) (a_uint32_t dev_id, fal_port_t port_id, - fal_pt_1q_egmode_t port_egvlanmode); - - typedef sw_error_t - (*hsl_portvlan_member_add) (a_uint32_t dev_id, fal_port_t port_id, - a_uint32_t mem_port_id); - - typedef sw_error_t - (*hsl_portvlan_member_del) (a_uint32_t dev_id, fal_port_t port_id, - a_uint32_t mem_port_id); - - typedef sw_error_t - (*hsl_portvlan_member_update) (a_uint32_t dev_id, fal_port_t port_id, - fal_pbmp_t mem_port_map); - - typedef sw_error_t - (*hsl_portvlan_member_get) (a_uint32_t dev_id, fal_port_t port_id, - fal_pbmp_t * mem_port_map); - - typedef sw_error_t - (*hsl_port_nestvlan_set) (a_uint32_t dev_id, fal_port_t port_id, - a_bool_t enable); - - typedef sw_error_t - (*hsl_port_nestvlan_get) (a_uint32_t dev_id, fal_port_t port_id, - a_bool_t * enable); - - typedef sw_error_t - (*hsl_nestvlan_tpid_set) (a_uint32_t dev_id, a_uint32_t tpid); - - typedef sw_error_t - (*hsl_nestvlan_tpid_get) (a_uint32_t dev_id, a_uint32_t * tpid); - - typedef sw_error_t - (*hsl_port_default_vid_set) (a_uint32_t dev_id, fal_port_t port_id, - a_uint32_t vid); - - typedef sw_error_t - (*hsl_port_default_vid_get) (a_uint32_t dev_id, fal_port_t port_id, - a_uint32_t * vid); - - typedef sw_error_t - (*hsl_port_force_default_vid_set) (a_uint32_t dev_id, - fal_port_t port_id, a_bool_t enable); - - typedef sw_error_t - (*hsl_port_force_default_vid_get) (a_uint32_t dev_id, - fal_port_t port_id, a_bool_t * enable); - - typedef sw_error_t - (*hsl_port_force_portvlan_set) (a_uint32_t dev_id, fal_port_t port_id, - a_bool_t enable); - - typedef sw_error_t - (*hsl_port_force_portvlan_get) (a_uint32_t dev_id, fal_port_t port_id, - a_bool_t * enable); - - typedef sw_error_t - (*hsl_port_invlan_mode_set) (a_uint32_t dev_id, fal_port_t port_id, - fal_pt_invlan_mode_t mode); - - typedef sw_error_t - (*hsl_port_invlan_mode_get) (a_uint32_t dev_id, fal_port_t port_id, - fal_pt_invlan_mode_t * mode); - - typedef sw_error_t - (*hsl_port_tls_set) (a_uint32_t dev_id, fal_port_t port_id, - a_bool_t enable); - - typedef sw_error_t - (*hsl_port_tls_get) (a_uint32_t dev_id, fal_port_t port_id, - a_bool_t * enable); - - typedef sw_error_t - (*hsl_port_pri_propagation_set) (a_uint32_t dev_id, fal_port_t port_id, - a_bool_t enable); - - typedef sw_error_t - (*hsl_port_pri_propagation_get) (a_uint32_t dev_id, fal_port_t port_id, - a_bool_t * enable); - - typedef sw_error_t - (*hsl_port_default_svid_set) (a_uint32_t dev_id, fal_port_t port_id, - a_uint32_t vid); - - typedef sw_error_t - (*hsl_port_default_svid_get) (a_uint32_t dev_id, fal_port_t port_id, - a_uint32_t * vid); - - typedef sw_error_t - (*hsl_port_default_cvid_set) (a_uint32_t dev_id, fal_port_t port_id, - a_uint32_t vid); - - typedef sw_error_t - (*hsl_port_default_cvid_get) (a_uint32_t dev_id, fal_port_t port_id, - a_uint32_t * vid); - - typedef sw_error_t - (*hsl_port_vlan_propagation_set) (a_uint32_t dev_id, fal_port_t port_id, - fal_vlan_propagation_mode_t mode); - - typedef sw_error_t - (*hsl_port_vlan_propagation_get) (a_uint32_t dev_id, fal_port_t port_id, - fal_vlan_propagation_mode_t * mode); - - typedef sw_error_t - (*hsl_port_vlan_trans_add) (a_uint32_t dev_id, fal_port_t port_id, - fal_vlan_trans_entry_t * entry); - - typedef sw_error_t - (*hsl_port_vlan_trans_del) (a_uint32_t dev_id, fal_port_t port_id, - fal_vlan_trans_entry_t * entry); - - typedef sw_error_t - (*hsl_port_vlan_trans_get) (a_uint32_t dev_id, fal_port_t port_id, - fal_vlan_trans_entry_t * entry); - - typedef sw_error_t - (*hsl_qinq_mode_set) (a_uint32_t dev_id, fal_qinq_mode_t mode); - - typedef sw_error_t - (*hsl_qinq_mode_get) (a_uint32_t dev_id, fal_qinq_mode_t * mode); - - typedef sw_error_t - (*hsl_port_qinq_role_set) (a_uint32_t dev_id, fal_port_t port_id, - fal_qinq_port_role_t role); - - typedef sw_error_t - (*hsl_port_qinq_role_get) (a_uint32_t dev_id, fal_port_t port_id, - fal_qinq_port_role_t * role); - - typedef sw_error_t - (*hsl_port_vlan_trans_iterate) (a_uint32_t dev_id, fal_port_t port_id, - a_uint32_t * iterator, - fal_vlan_trans_entry_t * entry); - - typedef sw_error_t - (*hsl_port_mac_vlan_xlt_set) (a_uint32_t dev_id, fal_port_t port_id, - a_bool_t enable); - - typedef sw_error_t - (*hsl_port_mac_vlan_xlt_get) (a_uint32_t dev_id, fal_port_t port_id, - a_bool_t * enable); - - typedef sw_error_t - (*hsl_netisolate_set) (a_uint32_t dev_id, a_uint32_t enable); - - typedef sw_error_t - (*hsl_netisolate_get) (a_uint32_t dev_id, a_uint32_t * enable); - - typedef sw_error_t - (*hsl_eg_trans_filter_bypass_en_set) (a_uint32_t dev_id, - a_uint32_t enable); - - typedef sw_error_t - (*hsl_eg_trans_filter_bypass_en_get) (a_uint32_t dev_id, - a_uint32_t * enable); - - typedef sw_error_t - (*hsl_port_vrf_id_set) (a_uint32_t dev_id, fal_port_t port_id, - a_uint32_t vrf_id); - - typedef sw_error_t - (*hsl_port_vrf_id_get) (a_uint32_t dev_id, fal_port_t port_id, - a_uint32_t * vrf_id); - - /* FDB */ -#define FDB_FUNC_PROTOTYPE_DEF - typedef sw_error_t - (*hsl_fdb_add) (a_uint32_t dev_id, const fal_fdb_entry_t * entry); - - typedef sw_error_t - (*hsl_fdb_rfs_set) (a_uint32_t dev_id, const fal_fdb_rfs_t * entry); - - typedef sw_error_t - (*hsl_fdb_rfs_del) (a_uint32_t dev_id, const fal_fdb_rfs_t * entry); - - typedef sw_error_t (*hsl_fdb_del_all) (a_uint32_t dev_id, a_uint32_t flag); - - typedef sw_error_t - (*hsl_fdb_del_by_port) (a_uint32_t dev_id, a_uint32_t port_id, - a_uint32_t flag); - - typedef sw_error_t - (*hsl_fdb_del_by_mac) (a_uint32_t dev_id, const fal_fdb_entry_t * addr); - - typedef sw_error_t - (*hsl_fdb_first) (a_uint32_t dev_id, fal_fdb_entry_t * entry); - - typedef sw_error_t - (*hsl_fdb_next) (a_uint32_t dev_id, fal_fdb_entry_t * entry); - - typedef sw_error_t - (*hsl_fdb_find) (a_uint32_t dev_id, fal_fdb_entry_t * entry); - - typedef sw_error_t - (*hsl_fdb_port_learn_set) (a_uint32_t dev_id, fal_port_t port_id, - a_bool_t enable); - - typedef sw_error_t - (*hsl_fdb_port_learn_get) (a_uint32_t dev_id, fal_port_t port_id, - a_bool_t * enable); - - typedef sw_error_t - (*hsl_fdb_age_ctrl_set) (a_uint32_t dev_id, a_bool_t enable); - - typedef sw_error_t - (*hsl_fdb_age_ctrl_get) (a_uint32_t dev_id, a_bool_t * enable); - - typedef sw_error_t - (*hsl_fdb_vlan_ivl_svl_set) (a_uint32_t dev_id, fal_fdb_smode smode); - - typedef sw_error_t - (*hsl_fdb_vlan_ivl_svl_get) (a_uint32_t dev_id, fal_fdb_smode * smode); - - typedef sw_error_t - (*hsl_fdb_age_time_set) (a_uint32_t dev_id, a_uint32_t * time); - - typedef sw_error_t - (*hsl_fdb_age_time_get) (a_uint32_t dev_id, a_uint32_t * time); - - typedef sw_error_t - (*hsl_fdb_iterate) (a_uint32_t dev_id, a_uint32_t * iterator, - fal_fdb_entry_t * entry); - - typedef sw_error_t - (*hsl_fdb_extend_next) (a_uint32_t dev_id, fal_fdb_op_t * op, - fal_fdb_entry_t * entry); - - typedef sw_error_t - (*hsl_fdb_extend_first) (a_uint32_t dev_id, fal_fdb_op_t * option, - fal_fdb_entry_t * entry); - - typedef sw_error_t - (*hsl_fdb_transfer) (a_uint32_t dev_id, fal_port_t old_port, - fal_port_t new_port, a_uint32_t fid, - fal_fdb_op_t * option); - - typedef sw_error_t - (*hsl_port_fdb_learn_limit_set) (a_uint32_t dev_id, fal_port_t port_id, - a_bool_t enable, a_uint32_t cnt); - - typedef sw_error_t - (*hsl_port_fdb_learn_limit_get) (a_uint32_t dev_id, fal_port_t port_id, - a_bool_t * enable, a_uint32_t * cnt); - - typedef sw_error_t - (*hsl_port_fdb_learn_exceed_cmd_set) (a_uint32_t dev_id, - fal_port_t port_id, - fal_fwd_cmd_t cmd); - - typedef sw_error_t - (*hsl_port_fdb_learn_exceed_cmd_get) (a_uint32_t dev_id, - fal_port_t port_id, - fal_fwd_cmd_t * cmd); - - typedef sw_error_t - (*hsl_fdb_learn_limit_set) (a_uint32_t dev_id, a_bool_t enable, - a_uint32_t cnt); - - typedef sw_error_t - (*hsl_fdb_learn_limit_get) (a_uint32_t dev_id, a_bool_t * enable, - a_uint32_t * cnt); - - typedef sw_error_t - (*hsl_fdb_learn_exceed_cmd_set) (a_uint32_t dev_id, fal_fwd_cmd_t cmd); - - typedef sw_error_t - (*hsl_fdb_learn_exceed_cmd_get) (a_uint32_t dev_id, fal_fwd_cmd_t * cmd); - - typedef sw_error_t - (*hsl_fdb_resv_add) (a_uint32_t dev_id, fal_fdb_entry_t * entry); - - typedef sw_error_t - (*hsl_fdb_resv_del) (a_uint32_t dev_id, fal_fdb_entry_t * entry); - - typedef sw_error_t - (*hsl_fdb_resv_find) (a_uint32_t dev_id, fal_fdb_entry_t * entry); - - typedef sw_error_t - (*hsl_fdb_resv_iterate) (a_uint32_t dev_id, a_uint32_t * iterator, - fal_fdb_entry_t * entry); - - typedef sw_error_t - (*hsl_fdb_port_learn_static_set) (a_uint32_t dev_id, fal_port_t port_id, - a_bool_t enable); - - typedef sw_error_t - (*hsl_fdb_port_learn_static_get) (a_uint32_t dev_id, fal_port_t port_id, - a_bool_t * enable); - - typedef sw_error_t - (*hsl_fdb_port_add) (a_uint32_t dev_id, a_uint32_t fid, - fal_mac_addr_t * addr, fal_port_t port_id); - - typedef sw_error_t - (*hsl_fdb_port_del) (a_uint32_t dev_id, a_uint32_t fid, - fal_mac_addr_t * addr, fal_port_t port_id); - - /* QOS */ -#define QOS_FUNC_PROTOTYPE_DEF - typedef sw_error_t - (*hsl_cosmap_up_queue_set) (a_uint32_t dev_id, a_uint32_t up, - fal_queue_t queue); - - typedef sw_error_t - (*hsl_cosmap_up_queue_get) (a_uint32_t dev_id, a_uint32_t up, - fal_queue_t * queue); - - typedef sw_error_t - (*hsl_cosmap_dscp_queue_set) (a_uint32_t dev_id, a_uint32_t dscp, - fal_queue_t queue); - - typedef sw_error_t - (*hsl_cosmap_dscp_queue_get) (a_uint32_t dev_id, a_uint32_t dscp, - fal_queue_t * queue); - - typedef sw_error_t - (*hsl_qos_port_mode_set) (a_uint32_t dev_id, fal_port_t port_id, - fal_qos_mode_t mode, a_bool_t enable); - - typedef sw_error_t - (*hsl_qos_port_mode_get) (a_uint32_t dev_id, fal_port_t port_id, - fal_qos_mode_t mode, a_bool_t * enable); - - typedef sw_error_t - (*hsl_qos_port_mode_pri_set) (a_uint32_t dev_id, fal_port_t port_id, - fal_qos_mode_t mode, a_uint32_t pri); - - typedef sw_error_t - (*hsl_qos_port_mode_pri_get) (a_uint32_t dev_id, fal_port_t port_id, - fal_qos_mode_t mode, a_uint32_t * pri); - - typedef sw_error_t - (*hsl_qos_port_default_up_set) (a_uint32_t dev_id, fal_port_t port_id, - a_uint32_t up); - - typedef sw_error_t - (*hsl_qos_port_default_up_get) (a_uint32_t dev_id, fal_port_t port_id, - a_uint32_t * up); - - typedef sw_error_t - (*hsl_qos_sch_mode_set) (a_uint32_t dev_id, - fal_sch_mode_t mode, const a_uint32_t weight[]); - - typedef sw_error_t - (*hsl_qos_sch_mode_get) (a_uint32_t dev_id, - fal_sch_mode_t * mode, a_uint32_t weight[]); - - typedef sw_error_t - (*hsl_qos_queue_tx_buf_status_set) (a_uint32_t dev_id, fal_port_t port_id, - a_bool_t enable); - - typedef sw_error_t - (*hsl_qos_queue_tx_buf_status_get) (a_uint32_t dev_id, fal_port_t port_id, - a_bool_t * enable); - - typedef sw_error_t - (*hsl_qos_queue_tx_buf_nr_set) (a_uint32_t dev_id, fal_port_t port_id, - a_uint32_t queue_id, a_uint32_t * number); - - typedef sw_error_t - (*hsl_qos_queue_tx_buf_nr_get) (a_uint32_t dev_id, fal_port_t port_id, - a_uint32_t queue_id, a_uint32_t * number); - - typedef sw_error_t - (*hsl_qos_port_tx_buf_status_set) (a_uint32_t dev_id, fal_port_t port_id, - a_bool_t enable); - - typedef sw_error_t - (*hsl_qos_port_tx_buf_status_get) (a_uint32_t dev_id, fal_port_t port_id, - a_bool_t * enable); - - typedef sw_error_t - (*hsl_qos_port_red_en_set) (a_uint32_t dev_id, fal_port_t port_id, - a_bool_t enable); - - typedef sw_error_t - (*hsl_qos_port_red_en_get) (a_uint32_t dev_id, fal_port_t port_id, - a_bool_t * enable); - - typedef sw_error_t - (*hsl_qos_port_tx_buf_nr_set) (a_uint32_t dev_id, fal_port_t port_id, - a_uint32_t * number); - - typedef sw_error_t - (*hsl_qos_port_tx_buf_nr_get) (a_uint32_t dev_id, fal_port_t port_id, - a_uint32_t * number); - - typedef sw_error_t - (*hsl_qos_port_rx_buf_nr_set) (a_uint32_t dev_id, fal_port_t port_id, - a_uint32_t * number); - - typedef sw_error_t - (*hsl_qos_port_rx_buf_nr_get) (a_uint32_t dev_id, fal_port_t port_id, - a_uint32_t * number); - - typedef sw_error_t - (*hsl_qos_port_sch_mode_set) (a_uint32_t dev_id, a_uint32_t port_id, - fal_sch_mode_t mode, - const a_uint32_t weight[]); - - typedef sw_error_t - (*hsl_qos_port_sch_mode_get) (a_uint32_t dev_id, a_uint32_t port_id, - fal_sch_mode_t * mode, a_uint32_t weight[]); - - typedef sw_error_t - (*hsl_qos_port_default_spri_set) (a_uint32_t dev_id, fal_port_t port_id, - a_uint32_t spri); - - typedef sw_error_t - (*hsl_qos_port_default_spri_get) (a_uint32_t dev_id, fal_port_t port_id, - a_uint32_t * spri); - - typedef sw_error_t - (*hsl_qos_port_default_cpri_set) (a_uint32_t dev_id, fal_port_t port_id, - a_uint32_t cpri); - - typedef sw_error_t - (*hsl_qos_port_default_cpri_get) (a_uint32_t dev_id, fal_port_t port_id, - a_uint32_t * cpri); - - typedef sw_error_t - (*hsl_qos_port_force_spri_status_set) (a_uint32_t dev_id, - fal_port_t port_id, - a_bool_t enable); - - typedef sw_error_t - (*hsl_qos_port_force_spri_status_get) (a_uint32_t dev_id, - fal_port_t port_id, - a_bool_t * enable); - - typedef sw_error_t - (*hsl_qos_port_force_cpri_status_set) (a_uint32_t dev_id, - fal_port_t port_id, - a_bool_t enable); - - typedef sw_error_t - (*hsl_qos_port_force_cpri_status_get) (a_uint32_t dev_id, - fal_port_t port_id, - a_bool_t * enable); - - typedef sw_error_t - (*hsl_qos_queue_remark_table_set) (a_uint32_t dev_id, fal_port_t port_id, - fal_queue_t queue_id, - a_uint32_t tbl_id, a_bool_t enable); - - typedef sw_error_t - (*hsl_qos_queue_remark_table_get) (a_uint32_t dev_id, fal_port_t port_id, - fal_queue_t queue_id, - a_uint32_t * tbl_id, - a_bool_t * enable); - - typedef sw_error_t - (*hsl_port_static_thresh_get)(a_uint32_t dev_id, fal_port_t port, - fal_bm_static_cfg_t *cfg); - - typedef sw_error_t - (*hsl_port_static_thresh_set)(a_uint32_t dev_id, fal_port_t port, - fal_bm_static_cfg_t *cfg); - - /* Rate */ -#define RATE_FUNC_PROTOTYPE_DEF - typedef sw_error_t - (*hsl_rate_queue_egrl_set) (a_uint32_t dev_id, fal_port_t port_id, - a_uint32_t queue_id, a_uint32_t * speed, - a_bool_t enable); - - typedef sw_error_t - (*hsl_rate_queue_egrl_get) (a_uint32_t dev_id, fal_port_t port_id, - a_uint32_t queue_id, a_uint32_t * speed, - a_bool_t * enable); - - typedef sw_error_t - (*hsl_rate_port_egrl_set) (a_uint32_t dev_id, fal_port_t port_id, - a_uint32_t * speed, a_bool_t enable); - - typedef sw_error_t - (*hsl_rate_port_egrl_get) (a_uint32_t dev_id, fal_port_t port_id, - a_uint32_t * speed, a_bool_t * enable); - - typedef sw_error_t - (*hsl_rate_port_inrl_set) (a_uint32_t dev_id, fal_port_t port_id, - a_uint32_t * speed, a_bool_t enable); - - typedef sw_error_t - (*hsl_rate_port_inrl_get) (a_uint32_t dev_id, fal_port_t port_id, - a_uint32_t * speed, a_bool_t * enable); - - typedef sw_error_t - (*hsl_storm_ctrl_frame_set) (a_uint32_t dev_id, fal_port_t port_id, - fal_storm_type_t storm_type, - a_bool_t enable); - - typedef sw_error_t - (*hsl_storm_ctrl_frame_get) (a_uint32_t dev_id, fal_port_t port_id, - fal_storm_type_t storm_type, - a_bool_t * enable); - - typedef sw_error_t - (*hsl_storm_ctrl_rate_set) (a_uint32_t dev_id, fal_port_t port_id, - a_uint32_t * rate); - - typedef sw_error_t - (*hsl_storm_ctrl_rate_get) (a_uint32_t dev_id, fal_port_t port_id, - a_uint32_t * rate); - - typedef sw_error_t - (*hsl_rate_port_policer_set) (a_uint32_t dev_id, fal_port_t port_id, - fal_port_policer_t * policer); - - typedef sw_error_t - (*hsl_rate_port_policer_get) (a_uint32_t dev_id, fal_port_t port_id, - fal_port_policer_t * policer); - - typedef sw_error_t - (*hsl_rate_port_shaper_set) (a_uint32_t dev_id, fal_port_t port_id, - a_bool_t enable, - fal_egress_shaper_t * shaper); - - typedef sw_error_t - (*hsl_rate_port_shaper_get) (a_uint32_t dev_id, fal_port_t port_id, - a_bool_t * enable, - fal_egress_shaper_t * shaper); - - typedef sw_error_t - (*hsl_rate_queue_shaper_set) (a_uint32_t dev_id, fal_port_t port_id, - fal_queue_t queue_id, a_bool_t enable, - fal_egress_shaper_t * shaper); - - typedef sw_error_t - (*hsl_rate_queue_shaper_get) (a_uint32_t dev_id, fal_port_t port_id, - fal_queue_t queue_id, a_bool_t * enable, - fal_egress_shaper_t * shaper); - - typedef sw_error_t - (*hsl_rate_acl_policer_set) (a_uint32_t dev_id, a_uint32_t policer_id, - fal_acl_policer_t * policer); - - typedef sw_error_t - (*hsl_rate_acl_policer_get) (a_uint32_t dev_id, a_uint32_t policer_id, - fal_acl_policer_t * policer); - - typedef sw_error_t - (*hsl_rate_port_add_rate_byte_set) (a_uint32_t dev_id, fal_port_t port_id, - a_uint32_t number); - - typedef sw_error_t - (*hsl_rate_port_add_rate_byte_get) (a_uint32_t dev_id, fal_port_t port_id, - a_uint32_t * number); - typedef sw_error_t - (*hsl_rate_port_gol_flow_en_set) (a_uint32_t dev_id, fal_port_t port_id, - a_bool_t enable); - - typedef sw_error_t - (*hsl_rate_port_gol_flow_en_get) (a_uint32_t dev_id, fal_port_t port_id, - a_bool_t * enable); - - /* Mirror */ -#define MIRROR_FUNC_PROTOTYPE_DEF - typedef sw_error_t - (*hsl_mirr_analysis_port_set) (a_uint32_t dev_id, fal_port_t port_id); - - typedef sw_error_t - (*hsl_mirr_analysis_port_get) (a_uint32_t dev_id, fal_port_t * port_id); - - typedef sw_error_t - (*hsl_mirr_port_in_set) (a_uint32_t dev_id, fal_port_t port_id, - a_bool_t enable); - - typedef sw_error_t - (*hsl_mirr_port_in_get) (a_uint32_t dev_id, fal_port_t port_id, - a_bool_t * enable); - - typedef sw_error_t - (*hsl_mirr_port_eg_set) (a_uint32_t dev_id, fal_port_t port_id, - a_bool_t enable); - - typedef sw_error_t - (*hsl_mirr_port_eg_get) (a_uint32_t dev_id, fal_port_t port_id, - a_bool_t * enable); - - /* STP */ -#define STP_FUNC_PROTOTYPE_DEF - typedef sw_error_t - (*hsl_stp_port_state_set) (a_uint32_t dev_id, a_uint32_t st_id, - fal_port_t port_id, fal_stp_state_t state); - - typedef sw_error_t - (*hsl_stp_port_state_get) (a_uint32_t dev_id, a_uint32_t st_id, - fal_port_t port_id, fal_stp_state_t * state); - /* IGMP */ -#define IGMP_FUNC_PROTOTYPE_DEF - typedef sw_error_t - (*hsl_port_igmps_status_set) (a_uint32_t dev_id, fal_port_t port_id, - a_bool_t enable); - - typedef sw_error_t - (*hsl_port_igmps_status_get) (a_uint32_t dev_id, fal_port_t port_id, - a_bool_t * enable); - - typedef sw_error_t - (*hsl_igmp_mld_cmd_set) (a_uint32_t dev_id, fal_fwd_cmd_t cmd); - - typedef sw_error_t - (*hsl_igmp_mld_cmd_get) (a_uint32_t dev_id, fal_fwd_cmd_t * cmd); - - typedef sw_error_t - (*hsl_port_igmp_join_set) (a_uint32_t dev_id, fal_port_t port_id, - a_bool_t enable); - - typedef sw_error_t - (*hsl_port_igmp_join_get) (a_uint32_t dev_id, fal_port_t port_id, - a_bool_t * enable); - - typedef sw_error_t - (*hsl_port_igmp_leave_set) (a_uint32_t dev_id, fal_port_t port_id, - a_bool_t enable); - - typedef sw_error_t - (*hsl_port_igmp_leave_get) (a_uint32_t dev_id, fal_port_t port_id, - a_bool_t * enable); - - typedef sw_error_t (*hsl_igmp_rp_set) (a_uint32_t dev_id, fal_pbmp_t pts); - - typedef sw_error_t (*hsl_igmp_rp_get) (a_uint32_t dev_id, fal_pbmp_t * pts); - - typedef sw_error_t - (*hsl_igmp_entry_creat_set) (a_uint32_t dev_id, a_bool_t enable); - - typedef sw_error_t - (*hsl_igmp_entry_creat_get) (a_uint32_t dev_id, a_bool_t * enable); - - typedef sw_error_t - (*hsl_igmp_entry_static_set) (a_uint32_t dev_id, a_bool_t enable); - - typedef sw_error_t - (*hsl_igmp_entry_static_get) (a_uint32_t dev_id, a_bool_t * enable); - - typedef sw_error_t - (*hsl_igmp_entry_leaky_set) (a_uint32_t dev_id, a_bool_t enable); - - typedef sw_error_t - (*hsl_igmp_entry_leaky_get) (a_uint32_t dev_id, a_bool_t * enable); - - typedef sw_error_t - (*hsl_igmp_entry_v3_set) (a_uint32_t dev_id, a_bool_t enable); - - typedef sw_error_t - (*hsl_igmp_entry_v3_get) (a_uint32_t dev_id, a_bool_t * enable); - - typedef sw_error_t - (*hsl_igmp_entry_queue_set) (a_uint32_t dev_id, a_bool_t enable, - a_uint32_t queue); - - typedef sw_error_t - (*hsl_igmp_entry_queue_get) (a_uint32_t dev_id, a_bool_t * enable, - a_uint32_t * queue); - - typedef sw_error_t - (*hsl_port_igmp_mld_learn_limit_set) (a_uint32_t dev_id, - fal_port_t port_id, a_bool_t enable, - a_uint32_t cnt); - - typedef sw_error_t - (*hsl_port_igmp_mld_learn_limit_get) (a_uint32_t dev_id, - fal_port_t port_id, - a_bool_t * enable, - a_uint32_t * cnt); - - typedef sw_error_t - (*hsl_port_igmp_mld_learn_exceed_cmd_set) (a_uint32_t dev_id, - fal_port_t port_id, - fal_fwd_cmd_t cmd); - - typedef sw_error_t - (*hsl_port_igmp_mld_learn_exceed_cmd_get) (a_uint32_t dev_id, - fal_port_t port_id, - fal_fwd_cmd_t * cmd); - typedef sw_error_t (*hsl_igmp_sg_entry_set) (a_uint32_t dev_id, - fal_igmp_sg_entry_t * entry); - - typedef sw_error_t - (*hsl_igmp_sg_entry_clear) (a_uint32_t dev_id, - fal_igmp_sg_entry_t * entry); - - typedef sw_error_t (*hsl_igmp_sg_entry_show) (a_uint32_t dev_id); - - typedef sw_error_t - (*hsl_igmp_sg_entry_query) (a_uint32_t dev_id, fal_igmp_sg_info_t * info); - - /* Leaky */ -#define LEAKY_FUNC_PROTOTYPE_DEF - typedef sw_error_t - (*hsl_uc_leaky_mode_set) (a_uint32_t dev_id, - fal_leaky_ctrl_mode_t ctrl_mode); - - typedef sw_error_t - (*hsl_uc_leaky_mode_get) (a_uint32_t dev_id, - fal_leaky_ctrl_mode_t * ctrl_mode); - - typedef sw_error_t - (*hsl_mc_leaky_mode_set) (a_uint32_t dev_id, - fal_leaky_ctrl_mode_t ctrl_mode); - - typedef sw_error_t - (*hsl_mc_leaky_mode_get) (a_uint32_t dev_id, - fal_leaky_ctrl_mode_t * ctrl_mode); - - typedef sw_error_t - (*hsl_port_arp_leaky_set) (a_uint32_t dev_id, fal_port_t port_id, - a_bool_t enable); - - typedef sw_error_t - (*hsl_port_arp_leaky_get) (a_uint32_t dev_id, fal_port_t port_id, - a_bool_t * enable); - - typedef sw_error_t - (*hsl_port_uc_leaky_set) (a_uint32_t dev_id, fal_port_t port_id, - a_bool_t enable); - - typedef sw_error_t - (*hsl_port_uc_leaky_get) (a_uint32_t dev_id, fal_port_t port_id, - a_bool_t * enable); - - typedef sw_error_t - (*hsl_port_mc_leaky_set) (a_uint32_t dev_id, fal_port_t port_id, - a_bool_t enable); - - typedef sw_error_t - (*hsl_port_mc_leaky_get) (a_uint32_t dev_id, fal_port_t port_id, - a_bool_t * enable); - - /* Mib */ -#define MIB_FUNC_PROTOTYPE_DEF - typedef sw_error_t - (*hsl_get_mib_info) (a_uint32_t dev_id, fal_port_t port_id, - fal_mib_info_t * mib_info); - - typedef sw_error_t - (*hsl_get_rx_mib_info) (a_uint32_t dev_id, fal_port_t port_id, - fal_mib_info_t * mib_info); - - typedef sw_error_t - (*hsl_get_tx_mib_info) (a_uint32_t dev_id, fal_port_t port_id, - fal_mib_info_t * mib_info); - - typedef sw_error_t - (*hsl_mib_status_set) (a_uint32_t dev_id, a_bool_t enable); - - typedef sw_error_t - (*hsl_mib_status_get) (a_uint32_t dev_id, a_bool_t * enable); - - typedef sw_error_t - (*hsl_mib_port_flush_counters) (a_uint32_t dev_id, fal_port_t port_id); - - typedef sw_error_t - (*hsl_mib_cpukeep_set) (a_uint32_t dev_id, a_bool_t enable); - - typedef sw_error_t - (*hsl_mib_cpukeep_get) (a_uint32_t dev_id, a_bool_t * enable); - - /* Acl */ -#define ACL_FUNC_PROTOTYPE_DEF - typedef sw_error_t - (*hsl_acl_list_creat) (a_uint32_t dev_id, a_uint32_t list_id, - a_uint32_t list_pri); - - typedef sw_error_t - (*hsl_acl_list_destroy) (a_uint32_t dev_id, a_uint32_t list_id); - - typedef sw_error_t - (*hsl_acl_rule_add) (a_uint32_t dev_id, a_uint32_t list_id, - a_uint32_t rule_id, a_uint32_t rule_nr, - fal_acl_rule_t * rule); - - typedef sw_error_t - (*hsl_acl_rule_delete) (a_uint32_t dev_id, a_uint32_t list_id, - a_uint32_t rule_id, a_uint32_t rule_nr); - - typedef sw_error_t - (*hsl_acl_rule_query) (a_uint32_t dev_id, a_uint32_t list_id, - a_uint32_t rule_id, fal_acl_rule_t * rule); - - typedef sw_error_t - (*hsl_acl_list_bind) (a_uint32_t dev_id, a_uint32_t list_id, - fal_acl_direc_t direc, fal_acl_bind_obj_t obj_t, - a_uint32_t obj_idx); - - typedef sw_error_t - (*hsl_acl_list_unbind) (a_uint32_t dev_id, a_uint32_t list_id, - fal_acl_direc_t direc, fal_acl_bind_obj_t obj_t, - a_uint32_t obj_idx); - - typedef sw_error_t - (*hsl_acl_status_set) (a_uint32_t dev_id, a_bool_t enable); - - typedef sw_error_t - (*hsl_acl_status_get) (a_uint32_t dev_id, a_bool_t * enable); - - typedef sw_error_t (*hsl_acl_list_dump) (a_uint32_t dev_id); - - typedef sw_error_t (*hsl_acl_rule_dump) (a_uint32_t dev_id); - - typedef sw_error_t - (*hsl_acl_port_udf_profile_set) (a_uint32_t dev_id, fal_port_t port_id, - fal_acl_udf_type_t udf_type, - a_uint32_t offset, a_uint32_t length); - - typedef sw_error_t - (*hsl_acl_port_udf_profile_get) (a_uint32_t dev_id, fal_port_t port_id, - fal_acl_udf_type_t udf_type, - a_uint32_t * offset, - a_uint32_t * length); - - typedef sw_error_t - (*hsl_acl_rule_active) (a_uint32_t dev_id, a_uint32_t list_id, - a_uint32_t rule_id, a_uint32_t rule_nr); - - typedef sw_error_t - (*hsl_acl_rule_deactive) (a_uint32_t dev_id, a_uint32_t list_id, - a_uint32_t rule_id, a_uint32_t rule_nr); - - typedef sw_error_t - (*hsl_acl_rule_src_filter_sts_set) (a_uint32_t dev_id, - a_uint32_t rule_id, a_bool_t enable); - - typedef sw_error_t - (*hsl_acl_rule_src_filter_sts_get) (a_uint32_t dev_id, - a_uint32_t rule_id, - a_bool_t * enable); - - typedef a_uint32_t - (*hsl_acl_rule_get_offset) (a_uint32_t dev_id, a_uint32_t list_id, - a_uint32_t rule_id); - - typedef sw_error_t - (*hsl_acl_rule_sync_multi_portmap) (a_uint32_t dev_id, a_uint32_t pos, - a_uint32_t * act); -/*qca808x_start*/ - - typedef sw_error_t (*hsl_dev_reset) (a_uint32_t dev_id); - - typedef sw_error_t (*hsl_dev_clean) (a_uint32_t dev_id); - - typedef sw_error_t - (*hsl_dev_access_set) (a_uint32_t dev_id, hsl_access_mode mode); -/*qca808x_end*/ - - /* LED */ -#define LED_FUNC_PROTOTYPE_DEF - typedef sw_error_t - (*hsl_led_ctrl_pattern_set) (a_uint32_t dev_id, led_pattern_group_t group, - led_pattern_id_t id, - led_ctrl_pattern_t * pattern); - - typedef sw_error_t - (*hsl_led_ctrl_pattern_get) (a_uint32_t dev_id, led_pattern_group_t group, - led_pattern_id_t id, - led_ctrl_pattern_t * pattern); - - typedef sw_error_t - (*hsl_led_ctrl_source_set) (a_uint32_t dev_id, a_uint32_t source_id, - led_ctrl_pattern_t * pattern); - - /* CoSMAP */ -#define COSMAP_FUNC_PROTOTYPE_DEF - typedef sw_error_t - (*hsl_cosmap_dscp_to_pri_set) (a_uint32_t dev_id, a_uint32_t dscp, - a_uint32_t pri); - - typedef sw_error_t - (*hsl_cosmap_dscp_to_pri_get) (a_uint32_t dev_id, a_uint32_t dscp, - a_uint32_t * pri); - - typedef sw_error_t - (*hsl_cosmap_dscp_to_dp_set) (a_uint32_t dev_id, a_uint32_t dscp, - a_uint32_t dp); - - typedef sw_error_t - (*hsl_cosmap_dscp_to_dp_get) (a_uint32_t dev_id, a_uint32_t dscp, - a_uint32_t * dp); - - typedef sw_error_t - (*hsl_cosmap_up_to_pri_set) (a_uint32_t dev_id, a_uint32_t up, - a_uint32_t pri); - - typedef sw_error_t - (*hsl_cosmap_up_to_pri_get) (a_uint32_t dev_id, a_uint32_t up, - a_uint32_t * pri); - - typedef sw_error_t - (*hsl_cosmap_up_to_dp_set) (a_uint32_t dev_id, a_uint32_t up, - a_uint32_t dp); - - typedef sw_error_t - (*hsl_cosmap_up_to_dp_get) (a_uint32_t dev_id, a_uint32_t up, - a_uint32_t * dp); - - typedef sw_error_t - (*hsl_cosmap_dscp_to_ehpri_set) (a_uint32_t dev_id, a_uint32_t dscp, - a_uint32_t pri); - - typedef sw_error_t - (*hsl_cosmap_dscp_to_ehpri_get) (a_uint32_t dev_id, a_uint32_t dscp, - a_uint32_t * pri); - - typedef sw_error_t - (*hsl_cosmap_dscp_to_ehdp_set) (a_uint32_t dev_id, a_uint32_t dscp, - a_uint32_t dp); - - typedef sw_error_t - (*hsl_cosmap_dscp_to_ehdp_get) (a_uint32_t dev_id, a_uint32_t dscp, - a_uint32_t * dp); - - typedef sw_error_t - (*hsl_cosmap_up_to_ehpri_set) (a_uint32_t dev_id, a_uint32_t up, - a_uint32_t pri); - - typedef sw_error_t - (*hsl_cosmap_up_to_ehpri_get) (a_uint32_t dev_id, a_uint32_t up, - a_uint32_t * pri); - - typedef sw_error_t - (*hsl_cosmap_up_to_ehdp_set) (a_uint32_t dev_id, a_uint32_t up, - a_uint32_t dp); - - typedef sw_error_t - (*hsl_cosmap_up_to_ehdp_get) (a_uint32_t dev_id, a_uint32_t up, - a_uint32_t * dp); - - typedef sw_error_t - (*hsl_cosmap_pri_to_queue_set) (a_uint32_t dev_id, a_uint32_t pri, - a_uint32_t queue); - - typedef sw_error_t - (*hsl_cosmap_pri_to_queue_get) (a_uint32_t dev_id, a_uint32_t pri, - a_uint32_t * queue); - - typedef sw_error_t - (*hsl_cosmap_pri_to_ehqueue_set) (a_uint32_t dev_id, a_uint32_t pri, - a_uint32_t queue); - - typedef sw_error_t - (*hsl_cosmap_pri_to_ehqueue_get) (a_uint32_t dev_id, a_uint32_t pri, - a_uint32_t * queue); - - typedef sw_error_t - (*hsl_cosmap_egress_remark_set) (a_uint32_t dev_id, a_uint32_t tbl_id, - fal_egress_remark_table_t * tbl); - - typedef sw_error_t - (*hsl_cosmap_egress_remark_get) (a_uint32_t dev_id, a_uint32_t tbl_id, - fal_egress_remark_table_t * tbl); - - - /* IP */ -#define IP_FUNC_PROTOTYPE_DEF - typedef sw_error_t - (*hsl_ip_host_add) (a_uint32_t dev_id, fal_host_entry_t * host_entry); - - typedef sw_error_t - (*hsl_ip_host_del) (a_uint32_t dev_id, a_uint32_t del_mode, - fal_host_entry_t * host_entry); - - typedef sw_error_t - (*hsl_ip_host_get) (a_uint32_t dev_id, a_uint32_t get_mode, - fal_host_entry_t * host_entry); - - typedef sw_error_t - (*hsl_ip_host_next) (a_uint32_t dev_id, a_uint32_t next_mode, - fal_host_entry_t * host_entry); - - typedef sw_error_t - (*hsl_ip_host_counter_bind) (a_uint32_t dev_id, a_uint32_t entry_id, - a_uint32_t cnt_id, a_bool_t enable); - - typedef sw_error_t - (*hsl_ip_host_pppoe_bind) (a_uint32_t dev_id, a_uint32_t entry_id, - a_uint32_t pppoe_id, a_bool_t enable); - - typedef sw_error_t - (*hsl_ip_pt_arp_learn_set) (a_uint32_t dev_id, fal_port_t port_id, - a_uint32_t flags); - - typedef sw_error_t - (*hsl_ip_pt_arp_learn_get) (a_uint32_t dev_id, fal_port_t port_id, - a_uint32_t * flags); - - typedef sw_error_t - (*hsl_ip_arp_learn_set) (a_uint32_t dev_id, fal_arp_learn_mode_t mode); - - typedef sw_error_t - (*hsl_ip_arp_learn_get) (a_uint32_t dev_id, fal_arp_learn_mode_t * mode); - - typedef sw_error_t - (*hsl_ip_source_guard_set) (a_uint32_t dev_id, fal_port_t port_id, - fal_source_guard_mode_t mode); - - typedef sw_error_t - (*hsl_ip_source_guard_get) (a_uint32_t dev_id, fal_port_t port_id, - fal_source_guard_mode_t * mode); - - typedef sw_error_t - (*hsl_ip_unk_source_cmd_set) (a_uint32_t dev_id, fal_fwd_cmd_t cmd); - - typedef sw_error_t - (*hsl_ip_unk_source_cmd_get) (a_uint32_t dev_id, fal_fwd_cmd_t * cmd); - - typedef sw_error_t - (*hsl_ip_arp_guard_set) (a_uint32_t dev_id, fal_port_t port_id, - fal_source_guard_mode_t mode); - - typedef sw_error_t - (*hsl_ip_arp_guard_get) (a_uint32_t dev_id, fal_port_t port_id, - fal_source_guard_mode_t * mode); - - typedef sw_error_t - (*hsl_arp_unk_source_cmd_set) (a_uint32_t dev_id, fal_fwd_cmd_t cmd); - - typedef sw_error_t - (*hsl_arp_unk_source_cmd_get) (a_uint32_t dev_id, fal_fwd_cmd_t * cmd); - - typedef sw_error_t - (*hsl_ip_route_status_set) (a_uint32_t dev_id, a_bool_t enable); - - typedef sw_error_t - (*hsl_ip_route_status_get) (a_uint32_t dev_id, a_bool_t * enable); - - typedef sw_error_t - (*hsl_ip_intf_entry_add) (a_uint32_t dev_id, - fal_intf_mac_entry_t * entry); - - typedef sw_error_t - (*hsl_ip_intf_entry_del) (a_uint32_t dev_id, a_uint32_t del_mode, - fal_intf_mac_entry_t * entry); - - typedef sw_error_t - (*hsl_ip_intf_entry_next) (a_uint32_t dev_id, a_uint32_t next_mode, - fal_intf_mac_entry_t * entry); - - typedef sw_error_t - (*hsl_ip_age_time_set) (a_uint32_t dev_id, a_uint32_t * time); - - typedef sw_error_t - (*hsl_ip_age_time_get) (a_uint32_t dev_id, a_uint32_t * time); - - typedef sw_error_t - (*hsl_ip_wcmp_hash_mode_set) (a_uint32_t dev_id, a_uint32_t hash_mode); - - typedef sw_error_t - (*hsl_ip_wcmp_hash_mode_get) (a_uint32_t dev_id, a_uint32_t * hash_mode); - - typedef sw_error_t - (*hsl_ip_vrf_base_addr_set) (a_uint32_t dev_id, - a_uint32_t vrf_id, fal_ip4_addr_t addr); - - typedef sw_error_t - (*hsl_ip_vrf_base_addr_get) (a_uint32_t dev_id, - a_uint32_t vrf_id, fal_ip4_addr_t * addr); - - typedef sw_error_t - (*hsl_ip_vrf_base_mask_set) (a_uint32_t dev_id, - a_uint32_t vrf_id, fal_ip4_addr_t addr); - - typedef sw_error_t - (*hsl_ip_vrf_base_mask_get) (a_uint32_t dev_id, - a_uint32_t vrf_id, fal_ip4_addr_t * addr); - - typedef sw_error_t - (*hsl_ip_default_route_set) (a_uint32_t dev_id, - a_uint32_t droute_id, - fal_default_route_t * entry); - - typedef sw_error_t - (*hsl_ip_default_route_get) (a_uint32_t dev_id, - a_uint32_t droute_id, - fal_default_route_t * entry); - - typedef sw_error_t - (*hsl_ip_host_route_set) (a_uint32_t dev_id, - a_uint32_t hroute_id, fal_host_route_t * entry); - - typedef sw_error_t - (*hsl_ip_host_route_get) (a_uint32_t dev_id, - a_uint32_t hroute_id, fal_host_route_t * entry); - - typedef sw_error_t - (*hsl_ip_wcmp_entry_set) (a_uint32_t dev_id, - a_uint32_t wcmp_id, fal_ip_wcmp_t * wcmp); - - typedef sw_error_t - (*hsl_ip_wcmp_entry_get) (a_uint32_t dev_id, - a_uint32_t wcmp_id, fal_ip_wcmp_t * wcmp); - typedef sw_error_t - (*hsl_ip_rfs_ip4_set) (a_uint32_t dev_id, fal_ip4_rfs_t * rfs); - - typedef sw_error_t - (*hsl_ip_rfs_ip6_set) (a_uint32_t dev_id, fal_ip6_rfs_t * rfs); - typedef sw_error_t - (*hsl_ip_rfs_ip4_del) (a_uint32_t dev_id, fal_ip4_rfs_t * rfs); - - typedef sw_error_t - (*hsl_ip_rfs_ip6_del) (a_uint32_t dev_id, fal_ip6_rfs_t * rfs); - - typedef sw_error_t - (*hsl_default_flow_cmd_set) (a_uint32_t dev_id, - a_uint32_t vrf_id, fal_flow_type_t type, - fal_default_flow_cmd_t cmd); - - typedef sw_error_t - (*hsl_default_flow_cmd_get) (a_uint32_t dev_id, - a_uint32_t vrf_id, fal_flow_type_t type, - fal_default_flow_cmd_t * cmd); - - typedef sw_error_t - (*hsl_default_rt_flow_cmd_set) (a_uint32_t dev_id, - a_uint32_t vrf_id, fal_flow_type_t type, - fal_default_flow_cmd_t cmd); - - typedef sw_error_t - (*hsl_default_rt_flow_cmd_get) (a_uint32_t dev_id, - a_uint32_t vrf_id, fal_flow_type_t type, - fal_default_flow_cmd_t * cmd); - -typedef sw_error_t - (*hsl_ip_glb_lock_time_set) (a_uint32_t dev_id, fal_glb_lock_time_t lock_time); - - /* NAT */ -#define NAT_FUNC_PROTOTYPE_DEF - typedef sw_error_t - (*hsl_nat_add) (a_uint32_t dev_id, fal_nat_entry_t * nat_entry); - - typedef sw_error_t - (*hsl_nat_del) (a_uint32_t dev_id, a_uint32_t del_mode, - fal_nat_entry_t * nat_entry); - - typedef sw_error_t - (*hsl_nat_get) (a_uint32_t dev_id, a_uint32_t get_mode, - fal_nat_entry_t * nat_entry); - - typedef sw_error_t - (*hsl_nat_next) (a_uint32_t dev_id, a_uint32_t next_mode, - fal_nat_entry_t * nat_entry); - - typedef sw_error_t - (*hsl_nat_counter_bind) (a_uint32_t dev_id, a_uint32_t entry_id, - a_uint32_t cnt_id, a_bool_t enable); - - typedef sw_error_t - (*hsl_napt_add) (a_uint32_t dev_id, fal_napt_entry_t * napt_entry); - - typedef sw_error_t - (*hsl_napt_del) (a_uint32_t dev_id, a_uint32_t del_mode, - fal_napt_entry_t * napt_entry); - - typedef sw_error_t - (*hsl_napt_get) (a_uint32_t dev_id, a_uint32_t get_mode, - fal_napt_entry_t * napt_entry); - - typedef sw_error_t - (*hsl_napt_next) (a_uint32_t dev_id, a_uint32_t next_mode, - fal_napt_entry_t * napt_entry); - - typedef sw_error_t - (*hsl_napt_counter_bind) (a_uint32_t dev_id, a_uint32_t entry_id, - a_uint32_t cnt_id, a_bool_t enable); - - typedef sw_error_t - (*hsl_nat_status_set) (a_uint32_t dev_id, a_bool_t enable); - - typedef sw_error_t - (*hsl_nat_status_get) (a_uint32_t dev_id, a_bool_t * enable); - - typedef sw_error_t - (*hsl_nat_hash_mode_set) (a_uint32_t dev_id, a_uint32_t mode); - - typedef sw_error_t - (*hsl_nat_hash_mode_get) (a_uint32_t dev_id, a_uint32_t * mode); - - typedef sw_error_t - (*hsl_napt_status_set) (a_uint32_t dev_id, a_bool_t enable); - - typedef sw_error_t - (*hsl_napt_status_get) (a_uint32_t dev_id, a_bool_t * enable); - - typedef sw_error_t - (*hsl_napt_mode_set) (a_uint32_t dev_id, fal_napt_mode_t mode); - - typedef sw_error_t - (*hsl_napt_mode_get) (a_uint32_t dev_id, fal_napt_mode_t * mode); - - typedef sw_error_t - (*hsl_nat_prv_base_addr_set) (a_uint32_t dev_id, fal_ip4_addr_t addr); - - typedef sw_error_t - (*hsl_nat_prv_base_addr_get) (a_uint32_t dev_id, fal_ip4_addr_t * addr); - - typedef sw_error_t - (*hsl_nat_prv_base_mask_set) (a_uint32_t dev_id, fal_ip4_addr_t mask); - - typedef sw_error_t - (*hsl_nat_prv_base_mask_get) (a_uint32_t dev_id, fal_ip4_addr_t * mask); - - typedef sw_error_t - (*hsl_nat_prv_addr_mode_set) (a_uint32_t dev_id, a_bool_t map_en); - - typedef sw_error_t - (*hsl_nat_prv_addr_mode_get) (a_uint32_t dev_id, a_bool_t * map_en); - - typedef sw_error_t - (*hsl_nat_pub_addr_add) (a_uint32_t dev_id, fal_nat_pub_addr_t * entry); - - typedef sw_error_t - (*hsl_nat_pub_addr_del) (a_uint32_t dev_id, a_uint32_t del_mode, - fal_nat_pub_addr_t * entry); - - typedef sw_error_t - (*hsl_nat_pub_addr_next) (a_uint32_t dev_id, a_uint32_t next_mode, - fal_nat_pub_addr_t * entry); - - typedef sw_error_t - (*hsl_nat_unk_session_cmd_set) (a_uint32_t dev_id, fal_fwd_cmd_t cmd); - - typedef sw_error_t - (*hsl_nat_unk_session_cmd_get) (a_uint32_t dev_id, fal_fwd_cmd_t * cmd); - - typedef sw_error_t - (*hsl_nat_global_set) (a_uint32_t dev_id, a_bool_t enable, a_uint32_t portbmp); - - typedef sw_error_t - (*hsl_flow_cookie_set) (a_uint32_t dev_id, - fal_flow_cookie_t * flow_cookie); - - typedef sw_error_t - (*hsl_flow_rfs_set) (a_uint32_t dev_id, a_uint8_t action, - fal_flow_rfs_t * rfs); - - /* SEC */ -#define SEC_FUNC_PROTOTYPE_DEF - typedef sw_error_t - (*hsl_sec_norm_item_set) (a_uint32_t dev_id, fal_norm_item_t item, - void *value); - - typedef sw_error_t - (*hsl_sec_norm_item_get) (a_uint32_t dev_id, fal_norm_item_t item, - void *value); - - - /* Trunk */ -#define TRUNK_FUNC_PROTOTYPE_DEF - typedef sw_error_t - (*hsl_trunk_group_set) (a_uint32_t dev_id, a_uint32_t trunk_id, - a_bool_t enable, fal_pbmp_t member); - - typedef sw_error_t - (*hsl_trunk_group_get) (a_uint32_t dev_id, a_uint32_t trunk_id, - a_bool_t * enable, fal_pbmp_t * member); - - typedef sw_error_t - (*hsl_trunk_hash_mode_set) (a_uint32_t dev_id, a_uint32_t hash_mode); - - typedef sw_error_t - (*hsl_trunk_hash_mode_get) (a_uint32_t dev_id, a_uint32_t * hash_mode); - - typedef sw_error_t - (*hsl_trunk_manipulate_sa_set) (a_uint32_t dev_id, fal_mac_addr_t * addr); - - typedef sw_error_t - (*hsl_trunk_manipulate_sa_get) (a_uint32_t dev_id, fal_mac_addr_t * addr); - - /* Interface Control */ -#define INTERFACE_CONTROL_FUNC_PROTOTYPE_DEF - typedef sw_error_t - (*hsl_interface_mac_mode_set) (a_uint32_t dev_id, fal_port_t port_id, - fal_mac_config_t * config); - - typedef sw_error_t - (*hsl_interface_mac_mode_get) (a_uint32_t dev_id, fal_port_t port_id, - fal_mac_config_t * config); - - typedef sw_error_t - (*hsl_port_3az_status_set) (a_uint32_t dev_id, fal_port_t port_id, - a_bool_t enable); - - typedef sw_error_t - (*hsl_port_3az_status_get) (a_uint32_t dev_id, fal_port_t port_id, - a_bool_t * enable); - - typedef sw_error_t - (*hsl_interface_phy_mode_set) (a_uint32_t dev_id, a_uint32_t phy_id, - fal_phy_config_t * config); - - typedef sw_error_t - (*hsl_interface_phy_mode_get) (a_uint32_t dev_id, a_uint32_t phy_id, - fal_phy_config_t * config); - - typedef sw_error_t - (*hsl_interface_fx100_ctrl_set) (a_uint32_t dev_id, - fal_fx100_ctrl_config_t * config); - - typedef sw_error_t - (*hsl_interface_fx100_ctrl_get) (a_uint32_t dev_id, - fal_fx100_ctrl_config_t * config); - - typedef sw_error_t - (*hsl_interface_fx100_status_get) (a_uint32_t dev_id, - a_uint32_t * status); - - typedef sw_error_t - (*hsl_interface_mac06_exch_set) (a_uint32_t dev_id, a_bool_t enable); - - typedef sw_error_t - (*hsl_interface_mac06_exch_get) (a_uint32_t dev_id, a_bool_t * enable); - - typedef sw_error_t - (*hsl_interface_pad_get) (a_uint32_t dev_id,a_uint32_t port_num, a_uint32_t *value); - - typedef sw_error_t - (*hsl_interface_pad_set) (a_uint32_t dev_id,a_uint32_t port_num, a_uint32_t value); - - typedef sw_error_t - (*hsl_interface_sgmii_get) (a_uint32_t dev_id, a_uint32_t * value); - - typedef sw_error_t - (*hsl_interface_sgmii_set) (a_uint32_t dev_id, a_uint32_t value); - - - /* REG */ -/*qca808x_start*/ -#define REG_FUNC_PROTOTYPE_DEF - typedef sw_error_t - (*hsl_phy_get) (a_uint32_t dev_id, a_uint32_t phy_addr, a_uint32_t reg, - a_uint16_t * value); - - typedef sw_error_t - (*hsl_phy_set) (a_uint32_t dev_id, a_uint32_t phy_addr, a_uint32_t reg, - a_uint16_t value); -/*qca808x_end*/ - typedef sw_error_t - (*hsl_reg_get) (a_uint32_t dev_id, a_uint32_t reg_addr, - a_uint8_t value[], a_uint32_t value_len); - - typedef sw_error_t - (*hsl_reg_set) (a_uint32_t dev_id, a_uint32_t reg_addr, - a_uint8_t value[], a_uint32_t value_len); - - typedef sw_error_t - (*hsl_psgmii_reg_get) (a_uint32_t dev_id, a_uint32_t reg_addr, - a_uint8_t *value, a_uint32_t value_len); - - typedef sw_error_t - (*hsl_psgmii_reg_set) (a_uint32_t dev_id, a_uint32_t reg_addr, - a_uint8_t *value, a_uint32_t value_len); - - typedef sw_error_t - (*hsl_reg_field_get) (a_uint32_t dev_id, a_uint32_t reg_addr, - a_uint32_t bit_offset, a_uint32_t field_len, - a_uint8_t value[], a_uint32_t value_len); - - typedef sw_error_t - (*hsl_reg_field_set) (a_uint32_t dev_id, a_uint32_t reg_addr, - a_uint32_t bit_offset, a_uint32_t field_len, - const a_uint8_t value[], a_uint32_t value_len); - - typedef sw_error_t - (*hsl_reg_entries_get) (a_uint32_t dev_id, a_uint32_t reg_addr, - a_uint32_t entry_len, a_uint8_t value[], - a_uint32_t value_len); - - typedef sw_error_t - (*hsl_reg_entries_set) (a_uint32_t dev_id, a_uint32_t reg_addr, - a_uint32_t entry_len, const a_uint8_t value[], - a_uint32_t value_len); - - typedef sw_error_t - (*hsl_debug_psgmii_self_test) (a_uint32_t dev_id, a_bool_t enable, - a_uint32_t times, a_uint32_t *result); - typedef sw_error_t - (*hsl_phy_dump)(a_uint32_t dev_id, a_uint32_t phy_addr, - a_uint32_t idx,fal_phy_dump_t *phy_dump); - - typedef sw_error_t - (*hsl_uniphy_reg_get) (a_uint32_t dev_id, a_uint32_t index, - a_uint32_t reg_addr, a_uint8_t value[], a_uint32_t value_len); - - typedef sw_error_t - (*hsl_uniphy_reg_set) (a_uint32_t dev_id, a_uint32_t index, - a_uint32_t reg_addr, a_uint8_t value[], a_uint32_t value_len); -/*qca808x_start*/ - - typedef struct - { -/*qca808x_end*/ -#if (!(defined(USER_MODE) && defined(KERNEL_MODULE))) -#ifndef HSL_STANDALONG - - /* Misc */ - hsl_arp_status_set arp_status_set; - hsl_arp_status_get arp_status_get; - hsl_frame_max_size_set frame_max_size_set; - hsl_frame_max_size_get frame_max_size_get; - hsl_port_unk_sa_cmd_set port_unk_sa_cmd_set; - hsl_port_unk_sa_cmd_get port_unk_sa_cmd_get; - hsl_port_unk_uc_filter_set port_unk_uc_filter_set; - hsl_port_unk_uc_filter_get port_unk_uc_filter_get; - hsl_port_unk_mc_filter_set port_unk_mc_filter_set; - hsl_port_unk_mc_filter_get port_unk_mc_filter_get; - hsl_port_bc_filter_set port_bc_filter_set; - hsl_port_bc_filter_get port_bc_filter_get; - hsl_nestvlan_tpid_set nestvlan_tpid_set; - hsl_nestvlan_tpid_get nestvlan_tpid_get; - hsl_cpu_port_status_set cpu_port_status_set; - hsl_cpu_port_status_get cpu_port_status_get; - hsl_bc_to_cpu_port_set bc_to_cpu_port_set; - hsl_bc_to_cpu_port_get bc_to_cpu_port_get; - hsl_pppoe_cmd_set pppoe_cmd_set; - hsl_pppoe_cmd_get pppoe_cmd_get; - hsl_pppoe_status_set pppoe_status_set; - hsl_pppoe_status_get pppoe_status_get; - hsl_port_dhcp_set port_dhcp_set; - hsl_port_dhcp_get port_dhcp_get; - hsl_arp_cmd_set arp_cmd_set; - hsl_arp_cmd_get arp_cmd_get; - hsl_eapol_cmd_set eapol_cmd_set; - hsl_eapol_cmd_get eapol_cmd_get; - hsl_pppoe_session_add pppoe_session_add; - hsl_pppoe_session_del pppoe_session_del; - hsl_pppoe_session_get pppoe_session_get; - hsl_eapol_status_set eapol_status_set; - hsl_eapol_status_get eapol_status_get; - hsl_ripv1_status_set ripv1_status_set; - hsl_ripv1_status_get ripv1_status_get; - hsl_port_arp_req_status_set port_arp_req_status_set; - hsl_port_arp_req_status_get port_arp_req_status_get; - hsl_port_arp_ack_status_set port_arp_ack_status_set; - hsl_port_arp_ack_status_get port_arp_ack_status_get; - hsl_pppoe_session_table_add pppoe_session_table_add; - hsl_pppoe_session_table_del pppoe_session_table_del; - hsl_pppoe_session_table_get pppoe_session_table_get; - hsl_pppoe_session_id_set pppoe_session_id_set; - hsl_pppoe_session_id_get pppoe_session_id_get; - hsl_intr_mask_set intr_mask_set; - hsl_intr_mask_get intr_mask_get; - hsl_intr_status_get intr_status_get; - hsl_intr_status_clear intr_status_clear; - hsl_intr_port_link_mask_set intr_port_link_mask_set; - hsl_intr_port_link_mask_get intr_port_link_mask_get; - hsl_intr_port_link_status_get intr_port_link_status_get; - hsl_intr_mask_mac_linkchg_set intr_mask_mac_linkchg_set; - hsl_intr_mask_mac_linkchg_get intr_mask_mac_linkchg_get; - hsl_intr_status_mac_linkchg_get intr_status_mac_linkchg_get; - hsl_cpu_vid_en_set cpu_vid_en_set; - hsl_cpu_vid_en_get cpu_vid_en_get; - hsl_rtd_pppoe_en_set rtd_pppoe_en_set; - hsl_rtd_pppoe_en_get rtd_pppoe_en_get; - hsl_intr_status_mac_linkchg_clear intr_status_mac_linkchg_clear; - hsl_global_macaddr_set global_macaddr_set; - hsl_global_macaddr_get global_macaddr_get; - hsl_lldp_status_set lldp_status_set; - hsl_lldp_status_get lldp_status_get; - hsl_frame_crc_reserve_set frame_crc_reserve_set; - hsl_frame_crc_reserve_get frame_crc_reserve_get; - -/*qca808x_start*/ - /* Port control */ - hsl_port_duplex_set port_duplex_set; - hsl_port_duplex_get port_duplex_get; - hsl_port_speed_set port_speed_set; - hsl_port_speed_get port_speed_get; - hsl_port_autoneg_status_get port_autoneg_status_get; - hsl_port_autoneg_enable port_autoneg_enable; - hsl_port_autoneg_restart port_autoneg_restart; - hsl_port_autoneg_adv_get port_autoneg_adv_get; - hsl_port_autoneg_adv_set port_autoneg_adv_set; -/*qca808x_end*/ - hsl_port_hdr_status_set port_hdr_status_set; - hsl_port_hdr_status_get port_hdr_status_get; -/*qca808x_start*/ - hsl_port_flowctrl_set port_flowctrl_set; - hsl_port_flowctrl_get port_flowctrl_get; -/*qca808x_end*/ - hsl_port_flowctrl_thresh_set port_flowctrl_thresh_set; - hsl_port_flowctrl_forcemode_set port_flowctrl_forcemode_set; - hsl_port_flowctrl_forcemode_get port_flowctrl_forcemode_get; -/*qca808x_start*/ - hsl_port_powersave_set port_powersave_set; - hsl_port_powersave_get port_powersave_get; - hsl_port_hibernate_set port_hibernate_set; - hsl_port_hibernate_get port_hibernate_get; - hsl_port_cdt port_cdt; -/*qca808x_end*/ - hsl_port_rxhdr_mode_set port_rxhdr_mode_set; - hsl_port_rxhdr_mode_get port_rxhdr_mode_get; - hsl_port_txhdr_mode_set port_txhdr_mode_set; - hsl_port_txhdr_mode_get port_txhdr_mode_get; - hsl_header_type_set header_type_set; - hsl_header_type_get header_type_get; - hsl_port_txmac_status_set port_txmac_status_set; - hsl_port_txmac_status_get port_txmac_status_get; - hsl_port_rxmac_status_set port_rxmac_status_set; - hsl_port_rxmac_status_get port_rxmac_status_get; - hsl_port_txfc_status_set port_txfc_status_set; - hsl_port_txfc_status_get port_txfc_status_get; - hsl_port_rxfc_status_set port_rxfc_status_set; - hsl_port_rxfc_status_get port_rxfc_status_get; - hsl_port_bp_status_set port_bp_status_set; - hsl_port_bp_status_get port_bp_status_get; - hsl_port_link_forcemode_set port_link_forcemode_set; - hsl_port_link_forcemode_get port_link_forcemode_get; -/*qca808x_start*/ - hsl_port_link_status_get port_link_status_get; - hsl_ports_link_status_get ports_link_status_get; -/*qca808x_end*/ - hsl_port_mac_loopback_set port_mac_loopback_set; - hsl_port_mac_loopback_get port_mac_loopback_get; - hsl_port_congestion_drop_set port_congestion_drop_set; - hsl_port_congestion_drop_get port_congestion_drop_get; - hsl_ring_flow_ctrl_thres_set ring_flow_ctrl_thres_set; - hsl_ring_flow_ctrl_thres_get ring_flow_ctrl_thres_get; -/*qca808x_start*/ - hsl_port_8023az_set port_8023az_set; - hsl_port_8023az_get port_8023az_get; - hsl_port_mdix_set port_mdix_set; - hsl_port_mdix_get port_mdix_get; - hsl_port_mdix_status_get port_mdix_status_get; -/*qca808x_end*/ - hsl_port_combo_prefer_medium_set port_combo_prefer_medium_set; - hsl_port_combo_prefer_medium_get port_combo_prefer_medium_get; - hsl_port_combo_medium_status_get port_combo_medium_status_get; - hsl_port_combo_fiber_mode_set port_combo_fiber_mode_set; - hsl_port_combo_fiber_mode_get port_combo_fiber_mode_get; -/*qca808x_start*/ - hsl_port_local_loopback_set port_local_loopback_set; - hsl_port_local_loopback_get port_local_loopback_get; - hsl_port_remote_loopback_set port_remote_loopback_set; - hsl_port_remote_loopback_get port_remote_loopback_get; - hsl_port_reset port_reset; - hsl_port_power_off port_power_off; - hsl_port_power_on port_power_on; - hsl_port_phy_id_get port_phy_id_get; - hsl_port_wol_status_set port_wol_status_set; - hsl_port_wol_status_get port_wol_status_get; - hsl_port_magic_frame_mac_set port_magic_frame_mac_set; - hsl_port_magic_frame_mac_get port_magic_frame_mac_get; -/*qca808x_end*/ - hsl_port_interface_mode_set port_interface_mode_set; - hsl_port_interface_mode_get port_interface_mode_get; - hsl_port_interface_mode_apply port_interface_mode_apply; -/*qca808x_start*/ - hsl_port_interface_mode_status_get port_interface_mode_status_get; - hsl_port_counter_set port_counter_set; - hsl_port_counter_get port_counter_get; - hsl_port_counter_show port_counter_show; -/*qca808x_end*/ - - /* VLAN */ - hsl_vlan_entry_append vlan_entry_append; - hsl_vlan_create vlan_creat; - hsl_vlan_member_update vlan_member_update; - hsl_vlan_delete vlan_delete; - hsl_vlan_find vlan_find; - hsl_vlan_next vlan_next; - hsl_vlan_flush vlan_flush; - hsl_vlan_fid_set vlan_fid_set; - hsl_vlan_fid_get vlan_fid_get; - hsl_vlan_member_add vlan_member_add; - hsl_vlan_member_del vlan_member_del; - hsl_vlan_learning_state_set vlan_learning_state_set; - hsl_vlan_learning_state_get vlan_learning_state_get; - - /* Port VLAN */ - hsl_port_1qmode_set port_1qmode_set; - hsl_port_1qmode_get port_1qmode_get; - hsl_port_egvlanmode_get port_egvlanmode_get; - hsl_port_egvlanmode_set port_egvlanmode_set; - hsl_portvlan_member_add portvlan_member_add; - hsl_portvlan_member_del portvlan_member_del; - hsl_portvlan_member_update portvlan_member_update; - hsl_portvlan_member_get portvlan_member_get; - hsl_port_default_vid_set port_default_vid_set; - hsl_port_default_vid_get port_default_vid_get; - hsl_port_force_default_vid_set port_force_default_vid_set; - hsl_port_force_default_vid_get port_force_default_vid_get; - hsl_port_force_portvlan_set port_force_portvlan_set; - hsl_port_force_portvlan_get port_force_portvlan_get; - hsl_port_nestvlan_set port_nestvlan_set; - hsl_port_nestvlan_get port_nestvlan_get; - hsl_port_invlan_mode_set port_invlan_mode_set; - hsl_port_invlan_mode_get port_invlan_mode_get; - hsl_port_tls_set port_tls_set; - hsl_port_tls_get port_tls_get; - hsl_port_pri_propagation_set port_pri_propagation_set; - hsl_port_pri_propagation_get port_pri_propagation_get; - hsl_port_default_svid_set port_default_svid_set; - hsl_port_default_svid_get port_default_svid_get; - hsl_port_default_cvid_set port_default_cvid_set; - hsl_port_default_cvid_get port_default_cvid_get; - hsl_port_vlan_propagation_set port_vlan_propagation_set; - hsl_port_vlan_propagation_get port_vlan_propagation_get; - hsl_port_vlan_trans_add port_vlan_trans_add; - hsl_port_vlan_trans_del port_vlan_trans_del; - hsl_port_vlan_trans_get port_vlan_trans_get; - hsl_qinq_mode_set qinq_mode_set; - hsl_qinq_mode_get qinq_mode_get; - hsl_port_qinq_role_set port_qinq_role_set; - hsl_port_qinq_role_get port_qinq_role_get; - hsl_port_vlan_trans_iterate port_vlan_trans_iterate; - hsl_port_mac_vlan_xlt_set port_mac_vlan_xlt_set; - hsl_port_mac_vlan_xlt_get port_mac_vlan_xlt_get; - hsl_netisolate_set netisolate_set; - hsl_netisolate_get netisolate_get; - hsl_eg_trans_filter_bypass_en_set eg_trans_filter_bypass_en_set; - hsl_eg_trans_filter_bypass_en_get eg_trans_filter_bypass_en_get; - hsl_port_vrf_id_set port_vrf_id_set; - hsl_port_vrf_id_get port_vrf_id_get; - - /* FDB */ - hsl_fdb_add fdb_add; - hsl_fdb_del_all fdb_del_all; - hsl_fdb_del_by_port fdb_del_by_port; - hsl_fdb_del_by_mac fdb_del_by_mac; - hsl_fdb_first fdb_first; - hsl_fdb_next fdb_next; - hsl_fdb_find fdb_find; - hsl_fdb_port_learn_set port_learn_set; - hsl_fdb_port_learn_get port_learn_get; - hsl_fdb_age_ctrl_set age_ctrl_set; - hsl_fdb_age_ctrl_get age_ctrl_get; - hsl_fdb_vlan_ivl_svl_set vlan_ivl_svl_set; - hsl_fdb_vlan_ivl_svl_get vlan_ivl_svl_get; - hsl_fdb_age_time_set age_time_set; - hsl_fdb_age_time_get age_time_get; - hsl_fdb_iterate fdb_iterate; - hsl_fdb_extend_next fdb_extend_next; - hsl_fdb_extend_first fdb_extend_first; - hsl_fdb_transfer fdb_transfer; - hsl_port_fdb_learn_limit_set port_fdb_learn_limit_set; - hsl_port_fdb_learn_limit_get port_fdb_learn_limit_get; - hsl_port_fdb_learn_exceed_cmd_set port_fdb_learn_exceed_cmd_set; - hsl_port_fdb_learn_exceed_cmd_get port_fdb_learn_exceed_cmd_get; - hsl_fdb_learn_limit_set fdb_learn_limit_set; - hsl_fdb_learn_limit_get fdb_learn_limit_get; - hsl_fdb_learn_exceed_cmd_set fdb_learn_exceed_cmd_set; - hsl_fdb_learn_exceed_cmd_get fdb_learn_exceed_cmd_get; - hsl_fdb_resv_add fdb_resv_add; - hsl_fdb_resv_del fdb_resv_del; - hsl_fdb_resv_find fdb_resv_find; - hsl_fdb_resv_iterate fdb_resv_iterate; - hsl_fdb_port_learn_static_set fdb_port_learn_static_set; - hsl_fdb_port_learn_static_get fdb_port_learn_static_get; - hsl_fdb_port_add fdb_port_add; - hsl_fdb_port_del fdb_port_del; - hsl_fdb_rfs_set fdb_rfs_set; - hsl_fdb_rfs_del fdb_rfs_del; - - /* QOS */ - hsl_qos_sch_mode_set qos_sch_mode_set; - hsl_qos_sch_mode_get qos_sch_mode_get; - hsl_qos_queue_tx_buf_status_set qos_queue_tx_buf_status_set; - hsl_qos_queue_tx_buf_status_get qos_queue_tx_buf_status_get; - hsl_qos_port_tx_buf_status_set qos_port_tx_buf_status_set; - hsl_qos_port_tx_buf_status_get qos_port_tx_buf_status_get; - hsl_qos_port_red_en_set qos_port_red_en_set; - hsl_qos_port_red_en_get qos_port_red_en_get; - hsl_qos_queue_tx_buf_nr_set qos_queue_tx_buf_nr_set; - hsl_qos_queue_tx_buf_nr_get qos_queue_tx_buf_nr_get; - hsl_qos_port_tx_buf_nr_set qos_port_tx_buf_nr_set; - hsl_qos_port_tx_buf_nr_get qos_port_tx_buf_nr_get; - hsl_qos_port_rx_buf_nr_set qos_port_rx_buf_nr_set; - hsl_qos_port_rx_buf_nr_get qos_port_rx_buf_nr_get; - hsl_cosmap_up_queue_set cosmap_up_queue_set; - hsl_cosmap_up_queue_get cosmap_up_queue_get; - hsl_cosmap_dscp_queue_set cosmap_dscp_queue_set; - hsl_cosmap_dscp_queue_get cosmap_dscp_queue_get; - hsl_qos_port_mode_set qos_port_mode_set; - hsl_qos_port_mode_get qos_port_mode_get; - hsl_qos_port_mode_pri_set qos_port_mode_pri_set; - hsl_qos_port_mode_pri_get qos_port_mode_pri_get; - hsl_qos_port_default_up_set qos_port_default_up_set; - hsl_qos_port_default_up_get qos_port_default_up_get; - hsl_qos_port_sch_mode_set qos_port_sch_mode_set; - hsl_qos_port_sch_mode_get qos_port_sch_mode_get; - hsl_qos_port_default_spri_set qos_port_default_spri_set; - hsl_qos_port_default_spri_get qos_port_default_spri_get; - hsl_qos_port_default_cpri_set qos_port_default_cpri_set; - hsl_qos_port_default_cpri_get qos_port_default_cpri_get; - hsl_qos_port_force_spri_status_set qos_port_force_spri_status_set; - hsl_qos_port_force_spri_status_get qos_port_force_spri_status_get; - hsl_qos_port_force_cpri_status_set qos_port_force_cpri_status_set; - hsl_qos_port_force_cpri_status_get qos_port_force_cpri_status_get; - - hsl_qos_queue_remark_table_set qos_queue_remark_table_set; - hsl_qos_queue_remark_table_get qos_queue_remark_table_get; - hsl_port_static_thresh_get port_static_thresh_get; - hsl_port_static_thresh_set port_static_thresh_set; - - /* Rate */ - hsl_storm_ctrl_frame_set storm_ctrl_frame_set; - hsl_storm_ctrl_frame_get storm_ctrl_frame_get; - hsl_storm_ctrl_rate_set storm_ctrl_rate_set; - hsl_storm_ctrl_rate_get storm_ctrl_rate_get; - hsl_rate_queue_egrl_set rate_queue_egrl_set; - hsl_rate_queue_egrl_get rate_queue_egrl_get; - hsl_rate_port_egrl_set rate_port_egrl_set; - hsl_rate_port_egrl_get rate_port_egrl_get; - hsl_rate_port_inrl_set rate_port_inrl_set; - hsl_rate_port_inrl_get rate_port_inrl_get; - hsl_rate_port_policer_set rate_port_policer_set; - hsl_rate_port_policer_get rate_port_policer_get; - hsl_rate_port_shaper_set rate_port_shaper_set; - hsl_rate_port_shaper_get rate_port_shaper_get; - hsl_rate_queue_shaper_set rate_queue_shaper_set; - hsl_rate_queue_shaper_get rate_queue_shaper_get; - hsl_rate_acl_policer_set rate_acl_policer_set; - hsl_rate_acl_policer_get rate_acl_policer_get; - hsl_rate_port_add_rate_byte_set rate_port_add_rate_byte_set; - hsl_rate_port_add_rate_byte_get rate_port_add_rate_byte_get; - hsl_rate_port_gol_flow_en_set rate_port_gol_flow_en_set; - hsl_rate_port_gol_flow_en_get rate_port_gol_flow_en_get; - - /* Mirror */ - hsl_mirr_analysis_port_set mirr_analysis_port_set; - hsl_mirr_analysis_port_get mirr_analysis_port_get; - hsl_mirr_port_in_set mirr_port_in_set; - hsl_mirr_port_in_get mirr_port_in_get; - hsl_mirr_port_eg_set mirr_port_eg_set; - hsl_mirr_port_eg_get mirr_port_eg_get; - - /* Stp */ - hsl_stp_port_state_set stp_port_state_set; - hsl_stp_port_state_get stp_port_state_get; - - /* IGMP */ - hsl_port_igmps_status_set port_igmps_status_set; - hsl_port_igmps_status_get port_igmps_status_get; - hsl_igmp_mld_cmd_set igmp_mld_cmd_set; - hsl_igmp_mld_cmd_get igmp_mld_cmd_get; - hsl_port_igmp_join_set port_igmp_join_set; - hsl_port_igmp_join_get port_igmp_join_get; - hsl_port_igmp_leave_set port_igmp_leave_set; - hsl_port_igmp_leave_get port_igmp_leave_get; - hsl_igmp_rp_set igmp_rp_set; - hsl_igmp_rp_get igmp_rp_get; - hsl_igmp_entry_creat_set igmp_entry_creat_set; - hsl_igmp_entry_creat_get igmp_entry_creat_get; - hsl_igmp_entry_static_set igmp_entry_static_set; - hsl_igmp_entry_static_get igmp_entry_static_get; - hsl_igmp_entry_leaky_set igmp_entry_leaky_set; - hsl_igmp_entry_leaky_get igmp_entry_leaky_get; - hsl_igmp_entry_v3_set igmp_entry_v3_set; - hsl_igmp_entry_v3_get igmp_entry_v3_get; - hsl_igmp_entry_queue_set igmp_entry_queue_set; - hsl_igmp_entry_queue_get igmp_entry_queue_get; - hsl_port_igmp_mld_learn_limit_set port_igmp_mld_learn_limit_set; - hsl_port_igmp_mld_learn_limit_get port_igmp_mld_learn_limit_get; - hsl_port_igmp_mld_learn_exceed_cmd_set port_igmp_mld_learn_exceed_cmd_set; - hsl_port_igmp_mld_learn_exceed_cmd_get port_igmp_mld_learn_exceed_cmd_get; - hsl_igmp_sg_entry_set igmp_sg_entry_set; - hsl_igmp_sg_entry_clear igmp_sg_entry_clear; - hsl_igmp_sg_entry_show igmp_sg_entry_show; - hsl_igmp_sg_entry_query igmp_sg_entry_query; - - /* Leaky */ - hsl_uc_leaky_mode_set uc_leaky_mode_set; - hsl_uc_leaky_mode_get uc_leaky_mode_get; - hsl_mc_leaky_mode_set mc_leaky_mode_set; - hsl_mc_leaky_mode_get mc_leaky_mode_get; - hsl_port_arp_leaky_set port_arp_leaky_set; - hsl_port_arp_leaky_get port_arp_leaky_get; - hsl_port_uc_leaky_set port_uc_leaky_set; - hsl_port_uc_leaky_get port_uc_leaky_get; - hsl_port_mc_leaky_set port_mc_leaky_set; - hsl_port_mc_leaky_get port_mc_leaky_get; - - /* MIB API */ - hsl_get_mib_info get_mib_info; - hsl_get_rx_mib_info get_rx_mib_info; - hsl_get_tx_mib_info get_tx_mib_info; - hsl_mib_status_set mib_status_set; - hsl_mib_status_get mib_status_get; - hsl_mib_port_flush_counters mib_port_flush_counters; - hsl_mib_cpukeep_set mib_cpukeep_set; - hsl_mib_cpukeep_get mib_cpukeep_get; - - - /* Acl */ - hsl_acl_list_creat acl_list_creat; - hsl_acl_list_destroy acl_list_destroy; - hsl_acl_rule_add acl_rule_add; - hsl_acl_rule_delete acl_rule_delete; - hsl_acl_rule_query acl_rule_query; - hsl_acl_list_bind acl_list_bind; - hsl_acl_list_unbind acl_list_unbind; - hsl_acl_status_set acl_status_set; - hsl_acl_status_get acl_status_get; - hsl_acl_list_dump acl_list_dump; - hsl_acl_rule_dump acl_rule_dump; - hsl_acl_port_udf_profile_set acl_port_udf_profile_set; - hsl_acl_port_udf_profile_get acl_port_udf_profile_get; - hsl_acl_rule_active acl_rule_active; - hsl_acl_rule_deactive acl_rule_deactive; - hsl_acl_rule_src_filter_sts_set acl_rule_src_filter_sts_set; - hsl_acl_rule_src_filter_sts_get acl_rule_src_filter_sts_get; - hsl_acl_rule_get_offset acl_rule_get_offset; - hsl_acl_rule_sync_multi_portmap acl_rule_sync_multi_portmap; - - /* LED */ - hsl_led_ctrl_pattern_set led_ctrl_pattern_set; - hsl_led_ctrl_pattern_get led_ctrl_pattern_get; - hsl_led_ctrl_source_set led_ctrl_source_set; - - /* CoSMap */ - hsl_cosmap_dscp_to_pri_set cosmap_dscp_to_pri_set; - hsl_cosmap_dscp_to_pri_get cosmap_dscp_to_pri_get; - hsl_cosmap_dscp_to_dp_set cosmap_dscp_to_dp_set; - hsl_cosmap_dscp_to_dp_get cosmap_dscp_to_dp_get; - hsl_cosmap_up_to_pri_set cosmap_up_to_pri_set; - hsl_cosmap_up_to_pri_get cosmap_up_to_pri_get; - hsl_cosmap_up_to_dp_set cosmap_up_to_dp_set; - hsl_cosmap_up_to_dp_get cosmap_up_to_dp_get; - hsl_cosmap_dscp_to_ehpri_set cosmap_dscp_to_ehpri_set; - hsl_cosmap_dscp_to_ehpri_get cosmap_dscp_to_ehpri_get; - hsl_cosmap_dscp_to_ehdp_set cosmap_dscp_to_ehdp_set; - hsl_cosmap_dscp_to_ehdp_get cosmap_dscp_to_ehdp_get; - hsl_cosmap_up_to_ehpri_set cosmap_up_to_ehpri_set; - hsl_cosmap_up_to_ehpri_get cosmap_up_to_ehpri_get; - hsl_cosmap_up_to_ehdp_set cosmap_up_to_ehdp_set; - hsl_cosmap_up_to_ehdp_get cosmap_up_to_ehdp_get; - hsl_cosmap_pri_to_queue_set cosmap_pri_to_queue_set; - hsl_cosmap_pri_to_queue_get cosmap_pri_to_queue_get; - hsl_cosmap_pri_to_ehqueue_set cosmap_pri_to_ehqueue_set; - hsl_cosmap_pri_to_ehqueue_get cosmap_pri_to_ehqueue_get; - hsl_cosmap_egress_remark_set cosmap_egress_remark_set; - hsl_cosmap_egress_remark_get cosmap_egress_remark_get; - - /* IP */ - hsl_ip_host_add ip_host_add; - hsl_ip_host_del ip_host_del; - hsl_ip_host_get ip_host_get; - hsl_ip_host_next ip_host_next; - hsl_ip_host_counter_bind ip_host_counter_bind; - hsl_ip_host_pppoe_bind ip_host_pppoe_bind; - hsl_ip_pt_arp_learn_set ip_pt_arp_learn_set; - hsl_ip_pt_arp_learn_get ip_pt_arp_learn_get; - hsl_ip_arp_learn_set ip_arp_learn_set; - hsl_ip_arp_learn_get ip_arp_learn_get; - hsl_ip_source_guard_set ip_source_guard_set; - hsl_ip_source_guard_get ip_source_guard_get; - hsl_ip_unk_source_cmd_set ip_unk_source_cmd_set; - hsl_ip_unk_source_cmd_get ip_unk_source_cmd_get; - hsl_ip_arp_guard_set ip_arp_guard_set; - hsl_ip_arp_guard_get ip_arp_guard_get; - hsl_arp_unk_source_cmd_set arp_unk_source_cmd_set; - hsl_arp_unk_source_cmd_get arp_unk_source_cmd_get; - hsl_ip_route_status_set ip_route_status_set; - hsl_ip_route_status_get ip_route_status_get; - hsl_ip_intf_entry_add ip_intf_entry_add; - hsl_ip_intf_entry_del ip_intf_entry_del; - hsl_ip_intf_entry_next ip_intf_entry_next; - hsl_ip_age_time_set ip_age_time_set; - hsl_ip_age_time_get ip_age_time_get; - hsl_ip_wcmp_hash_mode_set ip_wcmp_hash_mode_set; - hsl_ip_wcmp_hash_mode_get ip_wcmp_hash_mode_get; - hsl_ip_vrf_base_addr_set ip_vrf_base_addr_set; - hsl_ip_vrf_base_addr_get ip_vrf_base_addr_get; - hsl_ip_vrf_base_mask_set ip_vrf_base_mask_set; - hsl_ip_vrf_base_mask_get ip_vrf_base_mask_get; - hsl_ip_default_route_set ip_default_route_set; - hsl_ip_default_route_get ip_default_route_get; - hsl_ip_host_route_set ip_host_route_set; - hsl_ip_host_route_get ip_host_route_get; - hsl_ip_wcmp_entry_set ip_wcmp_entry_set; - hsl_ip_wcmp_entry_get ip_wcmp_entry_get; - hsl_ip_rfs_ip4_set ip_rfs_ip4_set; - hsl_ip_rfs_ip6_set ip_rfs_ip6_set; - hsl_ip_rfs_ip4_del ip_rfs_ip4_del; - hsl_ip_rfs_ip6_del ip_rfs_ip6_del; - hsl_default_flow_cmd_set ip_default_flow_cmd_set; - hsl_default_flow_cmd_get ip_default_flow_cmd_get; - hsl_default_rt_flow_cmd_set ip_default_rt_flow_cmd_set; - hsl_default_rt_flow_cmd_get ip_default_rt_flow_cmd_get; - hsl_ip_glb_lock_time_set ip_glb_lock_time_set; - - /* NAT */ - hsl_nat_add nat_add; - hsl_nat_del nat_del; - hsl_nat_get nat_get; - hsl_nat_next nat_next; - hsl_nat_counter_bind nat_counter_bind; - hsl_napt_add napt_add; - hsl_napt_del napt_del; - hsl_napt_get napt_get; - hsl_napt_next napt_next; - hsl_napt_counter_bind napt_counter_bind; - hsl_napt_add flow_add; - hsl_napt_del flow_del; - hsl_napt_get flow_get; - hsl_napt_next flow_next; - hsl_napt_counter_bind flow_counter_bind; - hsl_nat_status_set nat_status_set; - hsl_nat_status_get nat_status_get; - hsl_nat_hash_mode_set nat_hash_mode_set; - hsl_nat_hash_mode_get nat_hash_mode_get; - hsl_napt_status_set napt_status_set; - hsl_napt_status_get napt_status_get; - hsl_napt_mode_set napt_mode_set; - hsl_napt_mode_get napt_mode_get; - hsl_nat_prv_base_addr_set nat_prv_base_addr_set; - hsl_nat_prv_base_addr_get nat_prv_base_addr_get; - hsl_nat_prv_base_mask_set nat_prv_base_mask_set; - hsl_nat_prv_base_mask_get nat_prv_base_mask_get; - hsl_nat_prv_addr_mode_set nat_prv_addr_mode_set; - hsl_nat_prv_addr_mode_get nat_prv_addr_mode_get; - hsl_nat_pub_addr_add nat_pub_addr_add; - hsl_nat_pub_addr_del nat_pub_addr_del; - hsl_nat_pub_addr_next nat_pub_addr_next; - hsl_nat_unk_session_cmd_set nat_unk_session_cmd_set; - hsl_nat_unk_session_cmd_get nat_unk_session_cmd_get; - hsl_nat_global_set nat_global_set; - hsl_flow_cookie_set flow_cookie_set; - hsl_flow_rfs_set flow_rfs_set; - - /* SEC */ - hsl_sec_norm_item_set sec_norm_item_set; - hsl_sec_norm_item_get sec_norm_item_get; - - /* Trunk */ - hsl_trunk_group_set trunk_group_set; - hsl_trunk_group_get trunk_group_get; - hsl_trunk_hash_mode_set trunk_hash_mode_set; - hsl_trunk_hash_mode_get trunk_hash_mode_get; - hsl_trunk_manipulate_sa_set trunk_manipulate_sa_set; - hsl_trunk_manipulate_sa_get trunk_manipulate_sa_get; - - /* Interface Control */ - hsl_interface_mac_mode_set interface_mac_mode_set; - hsl_interface_mac_mode_get interface_mac_mode_get; - hsl_port_3az_status_set port_3az_status_set; - hsl_port_3az_status_get port_3az_status_get; - hsl_interface_phy_mode_set interface_phy_mode_set; - hsl_interface_phy_mode_get interface_phy_mode_get; - hsl_interface_fx100_ctrl_set interface_fx100_ctrl_set; - hsl_interface_fx100_ctrl_get interface_fx100_ctrl_get; - hsl_interface_fx100_status_get interface_fx100_status_get; - hsl_interface_mac06_exch_set interface_mac06_exch_set; - hsl_interface_mac06_exch_get interface_mac06_exch_get; - hsl_interface_pad_get interface_mac_pad_get; - hsl_interface_pad_set interface_mac_pad_set; - hsl_interface_sgmii_get interface_mac_sgmii_get; - hsl_interface_sgmii_set interface_mac_sgmii_set; -#endif -#endif -/*qca808x_start*/ - /* REG Access */ - hsl_phy_get phy_get; - hsl_phy_set phy_set; -/*qca808x_end*/ - hsl_reg_get reg_get; - hsl_reg_set reg_set; - hsl_reg_field_get reg_field_get; - hsl_reg_field_set reg_field_set; - hsl_reg_entries_get reg_entries_get; - hsl_reg_entries_set reg_entries_set; - hsl_psgmii_reg_get psgmii_reg_get; - hsl_psgmii_reg_set psgmii_reg_set; - hsl_register_dump register_dump; - hsl_debug_register_dump debug_register_dump; - hsl_debug_psgmii_self_test debug_psgmii_self_test; - hsl_phy_dump phy_dump; - hsl_uniphy_reg_get uniphy_reg_get; - hsl_uniphy_reg_set uniphy_reg_set; -/*qca808x_start*/ - /*INIT*/ hsl_dev_reset dev_reset; - hsl_dev_clean dev_clean; -/*qca808x_end*/ - hsl_dev_access_set dev_access_set; -/*qca808x_start*/ - hsl_phy_get phy_i2c_get; - hsl_phy_set phy_i2c_set; - } hsl_api_t; - - hsl_api_t *hsl_api_ptr_get (a_uint32_t dev_id); - - sw_error_t hsl_api_init (a_uint32_t dev_id); - -#if defined(SW_API_LOCK) && (!defined(HSL_STANDALONG)) - extern aos_lock_t sw_hsl_api_lock; -#define FAL_API_LOCK aos_lock(&sw_hsl_api_lock) -#define FAL_API_UNLOCK aos_unlock(&sw_hsl_api_lock) -#else -#define FAL_API_LOCK -#define FAL_API_UNLOCK -#endif - -#ifdef __cplusplus -} -#endif /* __cplusplus */ -#endif /* _SW_API_H */ -/*qca808x_end*/ diff --git a/feeds/ipq807x/qca-ssdk/src/include/hsl/hsl_dev.h b/feeds/ipq807x/qca-ssdk/src/include/hsl/hsl_dev.h deleted file mode 100755 index 48d3eb581..000000000 --- a/feeds/ipq807x/qca-ssdk/src/include/hsl/hsl_dev.h +++ /dev/null @@ -1,78 +0,0 @@ -/* - * Copyright (c) 2012, 2019, The Linux Foundation. All rights reserved. - * Permission to use, copy, modify, and/or distribute this software for - * any purpose with or without fee is hereby granted, provided that the - * above copyright notice and this permission notice appear in all copies. - * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES - * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR - * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES - * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN - * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT - * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. - */ - - -/*qca808x_start*/ -#ifndef _HSL_DEV_H -#define _HSL_DEV_H - -#ifdef __cplusplus -extern "C" { -#endif /* __cplusplus */ - -#include "hsl_api.h" -#include "ssdk_init.h" - -#define HSL_DEV_ID_CHECK(dev_id) \ -do { \ - if (dev_id >= SW_MAX_NR_DEV) \ - return SW_OUT_OF_RANGE; \ -} while (0) - -#define HSL_PORT_ID_CHECK(port_id) \ -do { \ - if (port_id >= SW_MAX_NR_PORT) \ - return SW_OUT_OF_RANGE; \ -} while (0) - - typedef struct - { - a_uint32_t dev_id; - a_uint8_t cpu_port_nr; - a_uint8_t nr_ports; - a_uint8_t nr_phy; - a_uint8_t nr_queue; - a_uint16_t nr_vlans; - a_bool_t hw_vlan_query; - hsl_acl_func_t acl_func; - hsl_init_mode cpu_mode; - a_uint32_t wan_bmp; - } hsl_dev_t; - - hsl_dev_t *hsl_dev_ptr_get(a_uint32_t dev_id); -/*qca808x_end*/ - hsl_acl_func_t *hsl_acl_ptr_get(a_uint32_t dev_id); -/*qca808x_start*/ - sw_error_t - hsl_dev_init(a_uint32_t dev_id, ssdk_init_cfg * cfg); - - sw_error_t - hsl_dev_cleanup(void); - -/*qca808x_end*/ - sw_error_t - hsl_ssdk_cfg(a_uint32_t dev_id, ssdk_cfg_t *ssdk_cfg); - - sw_error_t - hsl_access_mode_set(a_uint32_t dev_id, hsl_access_mode reg_mode); - - a_uint32_t hsl_dev_inner_ports_get(a_uint32_t dev_id); - -/*qca808x_start*/ -#ifdef __cplusplus -} -#endif /* __cplusplus */ -#endif /* _HSL_DEV_H */ -/*qca808x_end*/ - diff --git a/feeds/ipq807x/qca-ssdk/src/include/hsl/hsl_lock.h b/feeds/ipq807x/qca-ssdk/src/include/hsl/hsl_lock.h deleted file mode 100755 index db79fd5e0..000000000 --- a/feeds/ipq807x/qca-ssdk/src/include/hsl/hsl_lock.h +++ /dev/null @@ -1,30 +0,0 @@ -/* - * Copyright (c) 2012, The Linux Foundation. All rights reserved. - * Permission to use, copy, modify, and/or distribute this software for - * any purpose with or without fee is hereby granted, provided that the - * above copyright notice and this permission notice appear in all copies. - * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES - * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR - * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES - * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN - * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT - * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. - */ - - - -#ifndef _HSL_LOCK_H_ -#define _HSL_LOCK_H_ - -#ifdef __cplusplus -extern "c" { -#endif - sw_error_t hsl_api_lock_init(void); - - - -#ifdef __cplusplus -} -#endif /* __cplusplus */ -#endif /*_HSL_LOCK_H_ */ diff --git a/feeds/ipq807x/qca-ssdk/src/include/hsl/hsl_port_prop.h b/feeds/ipq807x/qca-ssdk/src/include/hsl/hsl_port_prop.h deleted file mode 100755 index 9b2c419d8..000000000 --- a/feeds/ipq807x/qca-ssdk/src/include/hsl/hsl_port_prop.h +++ /dev/null @@ -1,81 +0,0 @@ -/* - * Copyright (c) 2012, 2017, 2019, The Linux Foundation. All rights reserved. - * Permission to use, copy, modify, and/or distribute this software for - * any purpose with or without fee is hereby granted, provided that the - * above copyright notice and this permission notice appear in all copies. - * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES - * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR - * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES - * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN - * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT - * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. - */ - - - -#ifndef _HSL_PORT_PROPERTY_H_ -#define _HSL_PORT_PROPERTY_H_ - -#ifdef __cplusplus -extern "c" { -#endif - - typedef enum { - HSL_PP_PHY = 0, /* setting concerning phy */ - HSL_PP_INCL_CPU, /* setting may include cpu port */ - HSL_PP_EXCL_CPU, /* setting exclude cpu port */ - HSL_PP_INNER, /* setting inner ports */ - HSL_PP_CPU, /* setting cpu ports */ - HSL_PP_BUTT - } - hsl_port_prop_t; - - a_bool_t - hsl_port_prop_check(a_uint32_t dev_id, fal_port_t port_id, - hsl_port_prop_t p_type); - - a_bool_t - hsl_mports_prop_check(a_uint32_t dev_id, fal_pbmp_t port_bitmap, - hsl_port_prop_t p_type); - a_bool_t - hsl_port_validity_check(a_uint32_t dev_id, fal_port_t port_id); - - a_bool_t - hsl_mports_validity_check(a_uint32_t dev_id, fal_pbmp_t port_bitmap); - - sw_error_t - hsl_port_prop_portmap_get(a_uint32_t dev_id, fal_pbmp_t port_bitmap); - - sw_error_t - hsl_port_prop_set(a_uint32_t dev_id, fal_port_t port_id, - hsl_port_prop_t p_type); - - sw_error_t - hsl_port_prop_portmap_set(a_uint32_t dev_id, fal_port_t port_id); - - sw_error_t - hsl_port_prop_clr(a_uint32_t dev_id, fal_port_t port_id, - hsl_port_prop_t p_type); - - sw_error_t - hsl_port_prop_get_phyid(a_uint32_t dev_id, fal_port_t port_id, - a_uint32_t *phy_id); - - sw_error_t - hsl_port_prop_set_phyid(a_uint32_t dev_id, fal_port_t port_id, - a_uint32_t phy_id); - - sw_error_t - hsl_port_prop_init_by_dev(a_uint32_t dev_id); - - sw_error_t - hsl_port_prop_cleanup_by_dev(a_uint32_t dev_id); - - sw_error_t - hsl_port_prop_init(a_uint32_t dev_id); - -#ifdef __cplusplus -} -#endif /* __cplusplus */ -#endif /*_HSL_PORT_PROPERTY_H_ */ diff --git a/feeds/ipq807x/qca-ssdk/src/include/hsl/hsl_shared_api.h b/feeds/ipq807x/qca-ssdk/src/include/hsl/hsl_shared_api.h deleted file mode 100755 index cbf7294ec..000000000 --- a/feeds/ipq807x/qca-ssdk/src/include/hsl/hsl_shared_api.h +++ /dev/null @@ -1,220 +0,0 @@ -/* - * Copyright (c) 2012, 2015, The Linux Foundation. All rights reserved. - * Permission to use, copy, modify, and/or distribute this software for - * any purpose with or without fee is hereby granted, provided that the - * above copyright notice and this permission notice appear in all copies. - * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES - * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR - * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES - * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN - * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT - * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. - */ - -#ifndef _HSL_SHARED_API_H -#define _HSL_SHARED_API_H - -#include "hsl.h" -#include "hsl_api.h" -#include "ssdk_init.h" - -extern ssdk_chip_type SSDK_CURRENT_CHIP_TYPE; /*running chip type*/ - -#if !defined (HSL_STANDALONG) -/*MISC API*/ -#define PORT_BC_FILTER_SET fal_port_bc_filter_set -#define PORT_UNK_MC_FILTER_SET fal_port_unk_mc_filter_set -#define PORT_UNK_UC_FILTER_SET fal_port_unk_uc_filter_set - -/*ACL API*/ -#define ACL_RULE_QUERY fal_acl_rule_query - -/*VLAN API */ -#define VLAN_CREATE fal_vlan_create -#define VLAN_DEL fal_vlan_delete -#define VLAN_FIND fal_vlan_find -#define VLAN_MEMBER_ADD fal_vlan_member_add - -/*RATE API*/ -#define RATE_ACL_POLICER_SET fal_rate_acl_policer_set - -/*MIB API*/ -#define MIB_STATUS_SET fal_mib_status_set -#define GET_MIB_INFO fal_get_mib_info - -/* PORT_CTRL API */ -#define PORT_TXMAC_STATUS_SET fal_port_txmac_status_set -#define PORT_RXMAC_STATUS_SET fal_port_rxmac_status_set - -#elif defined(ISISC) -/* NAT API*/ -#include "isisc_nat.h" -#define NAPT_ADD isisc_napt_add -#define NAT_PUB_ADDR_ADD isisc_nat_pub_addr_add -#define NAPT_NEXT isisc_napt_next -#define NAT_PRV_BASE_ADDR_SET isisc_nat_prv_base_addr_set -#define NAT_PRV_BASE_MASK_SET isisc_nat_prv_base_mask_set -#define NAPT_DEL isisc_napt_del -#define NAT_DEL isisc_nat_del -#define NAT_PUB_ADDR_DEL isisc_nat_pub_addr_del -#define NAT_ADD isisc_nat_add -#define NAT_PRV_ADDR_MODE_GET isisc_nat_prv_addr_mode_get - -/*IP API*/ -#include "isisc_ip.h" -#define IP_INTF_ENTRY_ADD isisc_ip_intf_entry_add -#define IP_HOST_ADD isisc_ip_host_add -#define IP_HOST_DEL isisc_ip_host_del -#define IP_HOST_GET isisc_ip_host_get -#define IP_HOST_NEXT isisc_ip_host_next -#define IP_INTF_ENTRY_DEL isisc_ip_intf_entry_del -#define IP_HOST_PPPOE_BIND isisc_ip_host_pppoe_bind -#define IP_ROUTE_STATUS_SET isisc_ip_route_status_set - -/*MISC API*/ -#include "isisc_misc.h" -#define PPPOE_STATUS_GET isisc_pppoe_status_get -#define PPPOE_STATUS_SET isisc_pppoe_status_set -#define PPPOE_SESSION_ID_SET isisc_pppoe_session_id_set -#define PPPOE_SESSION_TABLE_ADD isisc_pppoe_session_table_add -#define PPPOE_SESSION_TABLE_DEL isisc_pppoe_session_table_del -#define PORT_BC_FILTER_SET isisc_port_bc_filter_set -#define PORT_UNK_MC_FILTER_SET isisc_port_unk_mc_filter_set -#define PORT_UNK_UC_FILTER_SET isisc_port_unk_uc_filter_set -#define PORT_RXMAC_STATUS_SET isisc_port_rxmac_status_set -#define MISC_ARP_CMD_SET isisc_arp_cmd_set -#define MISC_ARP_SP_NOT_FOUND_SET isisc_arp_unk_source_cmd_set -#define MISC_ARP_GUARD_SET isisc_ip_arp_guard_set -#define CPU_VID_EN_SET isisc_cpu_vid_en_set -#define RTD_PPPOE_EN_SET isisc_rtd_pppoe_en_set -#define PORT_ARP_ACK_STATUS_SET isisc_port_arp_ack_status_set -#define CPU_PORT_STATUS_SET isisc_cpu_port_status_set - -/*ACL API*/ -#include "isisc_acl.h" -#define ACL_RULE_ADD isisc_acl_rule_add -#define ACL_RULE_DEL isisc_acl_rule_delete -#define ACL_LIST_CREATE isisc_acl_list_creat -#define ACL_LIST_DESTROY isisc_acl_list_destroy -#define ACL_LIST_BIND isisc_acl_list_bind -#define ACL_LIST_UNBIND isisc_acl_list_unbind -#define ACL_RULE_GET_OFFSET isisc_acl_rule_get_offset -#define ACL_RULE_QUERY isisc_acl_rule_query -#define ACL_RULE_SYNC_MULTI_PORTMAP isisc_acl_rule_sync_multi_portmap -#define ACL_STATUS_GET isisc_acl_status_get -#define ACL_STATUS_SET isisc_acl_status_set -#define ACL_PORT_UDF_PROFILE_SET isisc_acl_port_udf_profile_set - -/*VLAN API */ -#include "isisc_vlan.h" -#define VLAN_CREATE isisc_vlan_create -#define VLAN_DEL isisc_vlan_delete -#define VLAN_FIND isisc_vlan_find -#define VLAN_MEMBER_ADD isisc_vlan_member_add - -/*RATE API*/ -#include "isisc_rate.h" -#define RATE_ACL_POLICER_SET isisc_rate_acl_policer_set - -/*MIB API*/ -#include "isisc_mib.h" -#define MIB_STATUS_SET isisc_mib_status_set -#define GET_MIB_INFO isisc_get_mib_info - -/* PORTVLAN API */ -#include "isisc_portvlan.h" -#define PORTVLAN_ROUTE_DEFV_SET isisc_port_route_defv_set -#define NETISOLATE_SET isisc_netisolate_set - -/* PORT_CTRL API */ -#include "isisc_port_ctrl.h" -#define HEADER_TYPE_SET isisc_header_type_set -#define PORT_TXHDR_MODE_SET isisc_port_txhdr_mode_set -#define PORT_TXMAC_STATUS_SET isisc_port_txmac_status_set - -#elif defined(ISIS) -/* NAT API*/ -#include "isis_nat.h" -#define NAPT_ADD isis_napt_add -#define NAT_PUB_ADDR_ADD isis_nat_pub_addr_add -#define NAPT_NEXT isis_napt_next -#define NAT_PRV_BASE_ADDR_SET isis_nat_prv_base_addr_set -#define NAT_PRV_BASE_MASK_SET isis_nat_prv_base_mask_set -#define NAPT_DEL isis_napt_del -#define NAT_DEL isis_nat_del -#define NAT_PUB_ADDR_DEL isis_nat_pub_addr_del -#define NAT_ADD isis_nat_add -#define NAT_PRV_ADDR_MODE_GET isis_nat_prv_addr_mode_get - -/*IP API*/ -#include "isis_ip.h" -#define IP_INTF_ENTRY_ADD isis_ip_intf_entry_add -#define IP_HOST_ADD isis_ip_host_add -#define IP_HOST_DEL isis_ip_host_del -#define IP_HOST_GET isis_ip_host_get -#define IP_HOST_NEXT isis_ip_host_next -#define IP_INTF_ENTRY_DEL isis_ip_intf_entry_del -#define IP_HOST_PPPOE_BIND isis_ip_host_pppoe_bind -#define IP_ROUTE_STATUS_SET isis_ip_route_status_set - -/*MISC API*/ -#include "isis_misc.h" -#define PPPOE_STATUS_GET isis_pppoe_status_get -#define PPPOE_STATUS_SET isis_pppoe_status_set -#define PPPOE_SESSION_ID_SET isis_pppoe_session_id_set -#define PPPOE_SESSION_TABLE_ADD isis_pppoe_session_table_add -#define PPPOE_SESSION_TABLE_DEL isis_pppoe_session_table_del -#define PORT_BC_FILTER_SET isis_port_bc_filter_set -#define PORT_UNK_MC_FILTER_SET isis_port_unk_mc_filter_set -#define PORT_UNK_UC_FILTER_SET isis_port_unk_uc_filter_set -#define PORT_RXMAC_STATUS_SET isis_port_rxmac_status_set -#define MISC_ARP_CMD_SET isis_arp_cmd_set -#define CPU_VID_EN_SET isis_cpu_vid_en_set -#define RTD_PPPOE_EN_SET isis_rtd_pppoe_en_set -#define PORT_ARP_ACK_STATUS_SET isis_port_arp_ack_status_set -#define CPU_PORT_STATUS_SET isis_cpu_port_status_set - -/*ACL API*/ -#include "isis_acl.h" -#define ACL_RULE_ADD isis_acl_rule_add -#define ACL_RULE_DEL isis_acl_rule_delete -#define ACL_LIST_CREATE isis_acl_list_creat -#define ACL_LIST_DESTROY isis_acl_list_destroy -#define ACL_LIST_BIND isis_acl_list_bind -#define ACL_LIST_UNBIND isis_acl_list_unbind -#define ACL_RULE_GET_OFFSET isis_acl_rule_get_offset -#define ACL_RULE_QUERY isis_acl_rule_query -#define ACL_RULE_SYNC_MULTI_PORTMAP isis_acl_rule_sync_multi_portmap -#define ACL_STATUS_GET isis_acl_status_get -#define ACL_STATUS_SET isis_acl_status_set -#define ACL_PORT_UDF_PROFILE_SET isis_acl_port_udf_profile_set - -/*VLAN API */ -#include "isis_vlan.h" -#define VLAN_CREATE isis_vlan_create -#define VLAN_DEL isis_vlan_delete -#define VLAN_FIND isis_vlan_find -#define VLAN_MEMBER_ADD isis_vlan_member_add - -/*RATE API*/ -#include "isis_rate.h" -#define RATE_ACL_POLICER_SET isis_rate_acl_policer_set - -/*MIB API*/ -#include "isis_mib.h" -#define MIB_STATUS_SET isis_mib_status_set -#define GET_MIB_INFO isis_get_mib_info - -/* PORTVLAN API */ -#include "isis_portvlan.h" -#define PORTVLAN_ROUTE_DEFV_SET isis_port_route_defv_set - -/* PORT_CTRL API */ -#include "isis_port_ctrl.h" -#define HEADER_TYPE_SET isis_header_type_set -#define PORT_TXHDR_MODE_SET isis_port_txhdr_mode_set -#define PORT_TXMAC_STATUS_SET isis_port_txmac_status_set -#endif - -#endif diff --git a/feeds/ipq807x/qca-ssdk/src/include/hsl/isis/isis_acl.h b/feeds/ipq807x/qca-ssdk/src/include/hsl/isis/isis_acl.h deleted file mode 100755 index 8f34225e9..000000000 --- a/feeds/ipq807x/qca-ssdk/src/include/hsl/isis/isis_acl.h +++ /dev/null @@ -1,134 +0,0 @@ -/* - * Copyright (c) 2012, The Linux Foundation. All rights reserved. - * Permission to use, copy, modify, and/or distribute this software for - * any purpose with or without fee is hereby granted, provided that the - * above copyright notice and this permission notice appear in all copies. - * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES - * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR - * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES - * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN - * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT - * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. - */ - - -/** - * @defgroup isis_acl ISIS_ACL - * @{ - */ -#ifndef _ISIS_ACL_H_ -#define _ISIS_ACL_H_ - -#ifdef __cplusplus -extern "C" { -#endif /* __cplusplus */ - -#include "fal/fal_acl.h" - - sw_error_t isis_acl_init(a_uint32_t dev_id); - - sw_error_t isis_acl_reset(a_uint32_t dev_id); - - sw_error_t isis_acl_cleanup(a_uint32_t dev_id); - -#ifdef IN_ACL -#define ISIS_ACL_INIT(rv, dev_id) \ - { \ - rv = isis_acl_init(dev_id); \ - SW_RTN_ON_ERROR(rv); \ - } - -#define ISIS_ACL_RESET(rv, dev_id) \ - { \ - rv = isis_acl_reset(dev_id); \ - SW_RTN_ON_ERROR(rv); \ - } -#define ISIS_ACL_CLEANUP(rv, dev_id) \ - { \ - rv = isis_acl_cleanup(dev_id); \ - SW_RTN_ON_ERROR(rv); \ - } -#else -#define ISIS_ACL_INIT(rv, dev_id) -#define ISIS_ACL_RESET(rv, dev_id) -#define ISIS_ACL_CLEANUP(rv, dev_id) -#endif - - sw_error_t - isis_acl_list_creat(a_uint32_t dev_id, a_uint32_t list_id, - a_uint32_t list_pri); - - sw_error_t - isis_acl_rule_query(a_uint32_t dev_id, a_uint32_t list_id, - a_uint32_t rule_id, fal_acl_rule_t * rule); - - sw_error_t - isis_acl_rule_add(a_uint32_t dev_id, a_uint32_t list_id, - a_uint32_t rule_id, a_uint32_t rule_nr, - fal_acl_rule_t * rule); - - sw_error_t - isis_acl_rule_delete(a_uint32_t dev_id, a_uint32_t list_id, - a_uint32_t rule_id, a_uint32_t rule_nr); - - a_uint32_t - isis_acl_rule_get_offset(a_uint32_t dev_id, a_uint32_t list_id, a_uint32_t rule_id); - - sw_error_t - isis_acl_rule_sync_multi_portmap(a_uint32_t dev_id, a_uint32_t pos, a_uint32_t *act); - - sw_error_t - isis_acl_list_bind(a_uint32_t dev_id, a_uint32_t list_id, - fal_acl_direc_t direc, fal_acl_bind_obj_t obj_t, - a_uint32_t obj_idx); - - sw_error_t - isis_acl_list_unbind(a_uint32_t dev_id, a_uint32_t list_id, - fal_acl_direc_t direc, fal_acl_bind_obj_t obj_t, - a_uint32_t obj_idx); - - sw_error_t - isis_acl_status_set(a_uint32_t dev_id, a_bool_t enable); - -#ifdef HSL_STANDALONG - - HSL_LOCAL sw_error_t - isis_acl_list_destroy(a_uint32_t dev_id, a_uint32_t list_id); - - HSL_LOCAL sw_error_t - isis_acl_status_get(a_uint32_t dev_id, a_bool_t * enable); - - HSL_LOCAL sw_error_t - isis_acl_list_dump(a_uint32_t dev_id); - - HSL_LOCAL sw_error_t - isis_acl_rule_dump(a_uint32_t dev_id); - - HSL_LOCAL sw_error_t - isis_acl_port_udf_profile_set(a_uint32_t dev_id, fal_port_t port_id, - fal_acl_udf_type_t udf_type, - a_uint32_t offset, a_uint32_t length); - - HSL_LOCAL sw_error_t - isis_acl_port_udf_profile_get(a_uint32_t dev_id, fal_port_t port_id, - fal_acl_udf_type_t udf_type, - a_uint32_t * offset, a_uint32_t * length); - - HSL_LOCAL sw_error_t - isis_acl_rule_active(a_uint32_t dev_id, a_uint32_t list_id, - a_uint32_t rule_id, a_uint32_t rule_nr); - - HSL_LOCAL sw_error_t - isis_acl_rule_deactive(a_uint32_t dev_id, a_uint32_t list_id, - a_uint32_t rule_id, a_uint32_t rule_nr); - -#endif - -#ifdef __cplusplus -} -#endif /* __cplusplus */ -#endif /* _ISIS_ACL_H_ */ -/** - * @} - */ diff --git a/feeds/ipq807x/qca-ssdk/src/include/hsl/isis/isis_api.h b/feeds/ipq807x/qca-ssdk/src/include/hsl/isis/isis_api.h deleted file mode 100755 index 7fbc03f1b..000000000 --- a/feeds/ipq807x/qca-ssdk/src/include/hsl/isis/isis_api.h +++ /dev/null @@ -1,992 +0,0 @@ -/* - * Copyright (c) 2012, The Linux Foundation. All rights reserved. - * Permission to use, copy, modify, and/or distribute this software for - * any purpose with or without fee is hereby granted, provided that the - * above copyright notice and this permission notice appear in all copies. - * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES - * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR - * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES - * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN - * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT - * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. - */ - - - -#ifndef _ISIS_API_H_ -#define _ISIS_API_H_ - -#ifdef __cplusplus -extern "C" { -#endif /* __cplusplus */ - -#ifdef IN_PORTCONTROL -#define PORTCONTROL_API \ - SW_API_DEF(SW_API_PT_DUPLEX_GET, isis_port_duplex_get), \ - SW_API_DEF(SW_API_PT_DUPLEX_SET, isis_port_duplex_set), \ - SW_API_DEF(SW_API_PT_SPEED_GET, isis_port_speed_get), \ - SW_API_DEF(SW_API_PT_SPEED_SET, isis_port_speed_set), \ - SW_API_DEF(SW_API_PT_AN_GET, isis_port_autoneg_status_get), \ - SW_API_DEF(SW_API_PT_AN_ENABLE, isis_port_autoneg_enable), \ - SW_API_DEF(SW_API_PT_AN_RESTART, isis_port_autoneg_restart), \ - SW_API_DEF(SW_API_PT_AN_ADV_GET, isis_port_autoneg_adv_get), \ - SW_API_DEF(SW_API_PT_AN_ADV_SET, isis_port_autoneg_adv_set), \ - SW_API_DEF(SW_API_PT_FLOWCTRL_SET, isis_port_flowctrl_set), \ - SW_API_DEF(SW_API_PT_FLOWCTRL_GET, isis_port_flowctrl_get), \ - SW_API_DEF(SW_API_PT_FLOWCTRL_MODE_SET, isis_port_flowctrl_forcemode_set), \ - SW_API_DEF(SW_API_PT_FLOWCTRL_MODE_GET, isis_port_flowctrl_forcemode_get), \ - SW_API_DEF(SW_API_PT_POWERSAVE_SET, isis_port_powersave_set), \ - SW_API_DEF(SW_API_PT_POWERSAVE_GET, isis_port_powersave_get), \ - SW_API_DEF(SW_API_PT_HIBERNATE_SET, isis_port_hibernate_set), \ - SW_API_DEF(SW_API_PT_HIBERNATE_GET, isis_port_hibernate_get), \ - SW_API_DEF(SW_API_PT_CDT, isis_port_cdt), \ - SW_API_DEF(SW_API_PT_TXHDR_SET, isis_port_txhdr_mode_set), \ - SW_API_DEF(SW_API_PT_TXHDR_GET, isis_port_txhdr_mode_get), \ - SW_API_DEF(SW_API_PT_RXHDR_SET, isis_port_rxhdr_mode_set), \ - SW_API_DEF(SW_API_PT_RXHDR_GET, isis_port_rxhdr_mode_get), \ - SW_API_DEF(SW_API_HEADER_TYPE_SET, isis_header_type_set), \ - SW_API_DEF(SW_API_HEADER_TYPE_GET, isis_header_type_get), \ - SW_API_DEF(SW_API_TXMAC_STATUS_SET, isis_port_txmac_status_set), \ - SW_API_DEF(SW_API_TXMAC_STATUS_GET, isis_port_txmac_status_get), \ - SW_API_DEF(SW_API_RXMAC_STATUS_SET, isis_port_rxmac_status_set), \ - SW_API_DEF(SW_API_RXMAC_STATUS_GET, isis_port_rxmac_status_get), \ - SW_API_DEF(SW_API_TXFC_STATUS_SET, isis_port_txfc_status_set), \ - SW_API_DEF(SW_API_TXFC_STATUS_GET, isis_port_txfc_status_get), \ - SW_API_DEF(SW_API_RXFC_STATUS_SET, isis_port_rxfc_status_set), \ - SW_API_DEF(SW_API_RXFC_STATUS_GET, isis_port_rxfc_status_get), \ - SW_API_DEF(SW_API_BP_STATUS_SET, isis_port_bp_status_set), \ - SW_API_DEF(SW_API_BP_STATUS_GET, isis_port_bp_status_get), \ - SW_API_DEF(SW_API_PT_LINK_MODE_SET, isis_port_link_forcemode_set), \ - SW_API_DEF(SW_API_PT_LINK_MODE_GET, isis_port_link_forcemode_get), \ - SW_API_DEF(SW_API_PT_LINK_STATUS_GET, isis_port_link_status_get), \ - SW_API_DEF(SW_API_PT_MAC_LOOPBACK_SET, isis_port_mac_loopback_set), \ - SW_API_DEF(SW_API_PT_MAC_LOOPBACK_GET, isis_port_mac_loopback_get), \ - SW_API_DEF(SW_API_PT_8023AZ_SET, isis_port_8023az_set), \ - SW_API_DEF(SW_API_PT_8023AZ_GET, isis_port_8023az_get), - -#define PORTCONTROL_API_PARAM \ - SW_API_DESC(SW_API_PT_DUPLEX_GET) \ - SW_API_DESC(SW_API_PT_DUPLEX_SET) \ - SW_API_DESC(SW_API_PT_SPEED_GET) \ - SW_API_DESC(SW_API_PT_SPEED_SET) \ - SW_API_DESC(SW_API_PT_AN_GET) \ - SW_API_DESC(SW_API_PT_AN_ENABLE) \ - SW_API_DESC(SW_API_PT_AN_RESTART) \ - SW_API_DESC(SW_API_PT_AN_ADV_GET) \ - SW_API_DESC(SW_API_PT_AN_ADV_SET) \ - SW_API_DESC(SW_API_PT_FLOWCTRL_SET) \ - SW_API_DESC(SW_API_PT_FLOWCTRL_GET) \ - SW_API_DESC(SW_API_PT_FLOWCTRL_MODE_SET) \ - SW_API_DESC(SW_API_PT_FLOWCTRL_MODE_GET) \ - SW_API_DESC(SW_API_PT_POWERSAVE_SET) \ - SW_API_DESC(SW_API_PT_POWERSAVE_GET) \ - SW_API_DESC(SW_API_PT_HIBERNATE_SET) \ - SW_API_DESC(SW_API_PT_HIBERNATE_GET) \ - SW_API_DESC(SW_API_PT_CDT) \ - SW_API_DESC(SW_API_PT_TXHDR_SET) \ - SW_API_DESC(SW_API_PT_TXHDR_GET) \ - SW_API_DESC(SW_API_PT_RXHDR_SET) \ - SW_API_DESC(SW_API_PT_RXHDR_GET) \ - SW_API_DESC(SW_API_HEADER_TYPE_SET) \ - SW_API_DESC(SW_API_HEADER_TYPE_GET) \ - SW_API_DESC(SW_API_TXMAC_STATUS_SET) \ - SW_API_DESC(SW_API_TXMAC_STATUS_GET) \ - SW_API_DESC(SW_API_RXMAC_STATUS_SET) \ - SW_API_DESC(SW_API_RXMAC_STATUS_GET) \ - SW_API_DESC(SW_API_TXFC_STATUS_SET) \ - SW_API_DESC(SW_API_TXFC_STATUS_GET) \ - SW_API_DESC(SW_API_RXFC_STATUS_SET) \ - SW_API_DESC(SW_API_RXFC_STATUS_GET) \ - SW_API_DESC(SW_API_BP_STATUS_SET) \ - SW_API_DESC(SW_API_BP_STATUS_GET) \ - SW_API_DESC(SW_API_PT_LINK_MODE_SET) \ - SW_API_DESC(SW_API_PT_LINK_MODE_GET) \ - SW_API_DESC(SW_API_PT_LINK_STATUS_GET) \ - SW_API_DESC(SW_API_PT_MAC_LOOPBACK_SET) \ - SW_API_DESC(SW_API_PT_MAC_LOOPBACK_GET) \ - SW_API_DESC(SW_API_PT_8023AZ_SET) \ - SW_API_DESC(SW_API_PT_8023AZ_GET) -#else -#define PORTCONTROL_API -#define PORTCONTROL_API_PARAM -#endif - -#ifdef IN_VLAN -#define VLAN_API \ - SW_API_DEF(SW_API_VLAN_ADD, isis_vlan_create), \ - SW_API_DEF(SW_API_VLAN_DEL, isis_vlan_delete), \ - SW_API_DEF(SW_API_VLAN_FIND, isis_vlan_find), \ - SW_API_DEF(SW_API_VLAN_NEXT, isis_vlan_next), \ - SW_API_DEF(SW_API_VLAN_APPEND, isis_vlan_entry_append), \ - SW_API_DEF(SW_API_VLAN_FLUSH, isis_vlan_flush), \ - SW_API_DEF(SW_API_VLAN_FID_SET, isis_vlan_fid_set), \ - SW_API_DEF(SW_API_VLAN_FID_GET, isis_vlan_fid_get), \ - SW_API_DEF(SW_API_VLAN_MEMBER_ADD, isis_vlan_member_add), \ - SW_API_DEF(SW_API_VLAN_MEMBER_DEL, isis_vlan_member_del), \ - SW_API_DEF(SW_API_VLAN_LEARN_STATE_SET, isis_vlan_learning_state_set), \ - SW_API_DEF(SW_API_VLAN_LEARN_STATE_GET, isis_vlan_learning_state_get), - -#define VLAN_API_PARAM \ - SW_API_DESC(SW_API_VLAN_ADD) \ - SW_API_DESC(SW_API_VLAN_DEL) \ - SW_API_DESC(SW_API_VLAN_FIND) \ - SW_API_DESC(SW_API_VLAN_NEXT) \ - SW_API_DESC(SW_API_VLAN_APPEND) \ - SW_API_DESC(SW_API_VLAN_FLUSH) \ - SW_API_DESC(SW_API_VLAN_FID_SET) \ - SW_API_DESC(SW_API_VLAN_FID_GET) \ - SW_API_DESC(SW_API_VLAN_MEMBER_ADD) \ - SW_API_DESC(SW_API_VLAN_MEMBER_DEL) \ - SW_API_DESC(SW_API_VLAN_LEARN_STATE_SET) \ - SW_API_DESC(SW_API_VLAN_LEARN_STATE_GET) -#else -#define VLAN_API -#define VLAN_API_PARAM -#endif - -#ifdef IN_PORTVLAN -#define PORTVLAN_API \ - SW_API_DEF(SW_API_PT_ING_MODE_GET, isis_port_1qmode_get), \ - SW_API_DEF(SW_API_PT_ING_MODE_SET, isis_port_1qmode_set), \ - SW_API_DEF(SW_API_PT_EG_MODE_GET, isis_port_egvlanmode_get), \ - SW_API_DEF(SW_API_PT_EG_MODE_SET, isis_port_egvlanmode_set), \ - SW_API_DEF(SW_API_PT_VLAN_MEM_ADD, isis_portvlan_member_add), \ - SW_API_DEF(SW_API_PT_VLAN_MEM_DEL, isis_portvlan_member_del), \ - SW_API_DEF(SW_API_PT_VLAN_MEM_UPDATE, isis_portvlan_member_update), \ - SW_API_DEF(SW_API_PT_VLAN_MEM_GET, isis_portvlan_member_get), \ - SW_API_DEF(SW_API_PT_FORCE_DEF_VID_SET, isis_port_force_default_vid_set), \ - SW_API_DEF(SW_API_PT_FORCE_DEF_VID_GET, isis_port_force_default_vid_get), \ - SW_API_DEF(SW_API_PT_FORCE_PORTVLAN_SET, isis_port_force_portvlan_set), \ - SW_API_DEF(SW_API_PT_FORCE_PORTVLAN_GET, isis_port_force_portvlan_get), \ - SW_API_DEF(SW_API_NESTVLAN_TPID_SET, isis_nestvlan_tpid_set), \ - SW_API_DEF(SW_API_NESTVLAN_TPID_GET, isis_nestvlan_tpid_get), \ - SW_API_DEF(SW_API_PT_IN_VLAN_MODE_SET, isis_port_invlan_mode_set), \ - SW_API_DEF(SW_API_PT_IN_VLAN_MODE_GET, isis_port_invlan_mode_get), \ - SW_API_DEF(SW_API_PT_TLS_SET, isis_port_tls_set), \ - SW_API_DEF(SW_API_PT_TLS_GET, isis_port_tls_get), \ - SW_API_DEF(SW_API_PT_PRI_PROPAGATION_SET, isis_port_pri_propagation_set), \ - SW_API_DEF(SW_API_PT_PRI_PROPAGATION_GET, isis_port_pri_propagation_get), \ - SW_API_DEF(SW_API_PT_DEF_SVID_SET, isis_port_default_svid_set), \ - SW_API_DEF(SW_API_PT_DEF_SVID_GET, isis_port_default_svid_get), \ - SW_API_DEF(SW_API_PT_DEF_CVID_SET, isis_port_default_cvid_set), \ - SW_API_DEF(SW_API_PT_DEF_CVID_GET, isis_port_default_cvid_get), \ - SW_API_DEF(SW_API_PT_VLAN_PROPAGATION_SET, isis_port_vlan_propagation_set), \ - SW_API_DEF(SW_API_PT_VLAN_PROPAGATION_GET, isis_port_vlan_propagation_get), \ - SW_API_DEF(SW_API_PT_VLAN_TRANS_ADD, isis_port_vlan_trans_add), \ - SW_API_DEF(SW_API_PT_VLAN_TRANS_DEL, isis_port_vlan_trans_del), \ - SW_API_DEF(SW_API_PT_VLAN_TRANS_GET, isis_port_vlan_trans_get), \ - SW_API_DEF(SW_API_QINQ_MODE_SET, isis_qinq_mode_set), \ - SW_API_DEF(SW_API_QINQ_MODE_GET, isis_qinq_mode_get), \ - SW_API_DEF(SW_API_PT_QINQ_ROLE_SET, isis_port_qinq_role_set), \ - SW_API_DEF(SW_API_PT_QINQ_ROLE_GET, isis_port_qinq_role_get), \ - SW_API_DEF(SW_API_PT_VLAN_TRANS_ITERATE, isis_port_vlan_trans_iterate), \ - SW_API_DEF(SW_API_PT_MAC_VLAN_XLT_SET, isis_port_mac_vlan_xlt_set), \ - SW_API_DEF(SW_API_PT_MAC_VLAN_XLT_GET, isis_port_mac_vlan_xlt_get), - -#define PORTVLAN_API_PARAM \ - SW_API_DESC(SW_API_PT_ING_MODE_GET) \ - SW_API_DESC(SW_API_PT_ING_MODE_SET) \ - SW_API_DESC(SW_API_PT_EG_MODE_GET) \ - SW_API_DESC(SW_API_PT_EG_MODE_SET) \ - SW_API_DESC(SW_API_PT_VLAN_MEM_ADD) \ - SW_API_DESC(SW_API_PT_VLAN_MEM_DEL) \ - SW_API_DESC(SW_API_PT_VLAN_MEM_UPDATE) \ - SW_API_DESC(SW_API_PT_VLAN_MEM_GET) \ - SW_API_DESC(SW_API_PT_FORCE_DEF_VID_SET) \ - SW_API_DESC(SW_API_PT_FORCE_DEF_VID_GET) \ - SW_API_DESC(SW_API_PT_FORCE_PORTVLAN_SET) \ - SW_API_DESC(SW_API_PT_FORCE_PORTVLAN_GET) \ - SW_API_DESC(SW_API_NESTVLAN_TPID_SET) \ - SW_API_DESC(SW_API_NESTVLAN_TPID_GET) \ - SW_API_DESC(SW_API_PT_IN_VLAN_MODE_SET) \ - SW_API_DESC(SW_API_PT_IN_VLAN_MODE_GET) \ - SW_API_DESC(SW_API_PT_TLS_SET) \ - SW_API_DESC(SW_API_PT_TLS_GET) \ - SW_API_DESC(SW_API_PT_PRI_PROPAGATION_SET) \ - SW_API_DESC(SW_API_PT_PRI_PROPAGATION_GET) \ - SW_API_DESC(SW_API_PT_DEF_SVID_SET) \ - SW_API_DESC(SW_API_PT_DEF_SVID_GET) \ - SW_API_DESC(SW_API_PT_DEF_CVID_SET) \ - SW_API_DESC(SW_API_PT_DEF_CVID_GET) \ - SW_API_DESC(SW_API_PT_VLAN_PROPAGATION_SET) \ - SW_API_DESC(SW_API_PT_VLAN_PROPAGATION_GET) \ - SW_API_DESC(SW_API_PT_VLAN_TRANS_ADD) \ - SW_API_DESC(SW_API_PT_VLAN_TRANS_DEL) \ - SW_API_DESC(SW_API_PT_VLAN_TRANS_GET) \ - SW_API_DESC(SW_API_QINQ_MODE_SET) \ - SW_API_DESC(SW_API_QINQ_MODE_GET) \ - SW_API_DESC(SW_API_PT_QINQ_ROLE_SET) \ - SW_API_DESC(SW_API_PT_QINQ_ROLE_GET) \ - SW_API_DESC(SW_API_PT_VLAN_TRANS_ITERATE) \ - SW_API_DESC(SW_API_PT_MAC_VLAN_XLT_SET) \ - SW_API_DESC(SW_API_PT_MAC_VLAN_XLT_GET) -#else -#define PORTVLAN_API -#define PORTVLAN_API_PARAM -#endif - -#ifdef IN_FDB -#define FDB_API \ - SW_API_DEF(SW_API_FDB_ADD, isis_fdb_add), \ - SW_API_DEF(SW_API_FDB_DELALL, isis_fdb_del_all), \ - SW_API_DEF(SW_API_FDB_DELPORT,isis_fdb_del_by_port), \ - SW_API_DEF(SW_API_FDB_DELMAC, isis_fdb_del_by_mac), \ - SW_API_DEF(SW_API_FDB_FIND, isis_fdb_find), \ - SW_API_DEF(SW_API_FDB_EXTEND_NEXT, isis_fdb_extend_next), \ - SW_API_DEF(SW_API_FDB_EXTEND_FIRST, isis_fdb_extend_first), \ - SW_API_DEF(SW_API_FDB_TRANSFER, isis_fdb_transfer), \ - SW_API_DEF(SW_API_FDB_PT_LEARN_SET, isis_fdb_port_learn_set), \ - SW_API_DEF(SW_API_FDB_PT_LEARN_GET, isis_fdb_port_learn_get), \ - SW_API_DEF(SW_API_FDB_AGE_CTRL_SET, isis_fdb_age_ctrl_set), \ - SW_API_DEF(SW_API_FDB_AGE_CTRL_GET, isis_fdb_age_ctrl_get), \ - SW_API_DEF(SW_API_FDB_AGE_TIME_SET, isis_fdb_age_time_set), \ - SW_API_DEF(SW_API_FDB_AGE_TIME_GET, isis_fdb_age_time_get), \ - SW_API_DEF(SW_API_PT_FDB_LEARN_LIMIT_SET, isis_port_fdb_learn_limit_set), \ - SW_API_DEF(SW_API_PT_FDB_LEARN_LIMIT_GET, isis_port_fdb_learn_limit_get), \ - SW_API_DEF(SW_API_PT_FDB_LEARN_EXCEED_CMD_SET, isis_port_fdb_learn_exceed_cmd_set), \ - SW_API_DEF(SW_API_PT_FDB_LEARN_EXCEED_CMD_GET, isis_port_fdb_learn_exceed_cmd_get), \ - SW_API_DEF(SW_API_FDB_LEARN_LIMIT_SET, isis_fdb_learn_limit_set), \ - SW_API_DEF(SW_API_FDB_LEARN_LIMIT_GET, isis_fdb_learn_limit_get), \ - SW_API_DEF(SW_API_FDB_LEARN_EXCEED_CMD_SET, isis_fdb_learn_exceed_cmd_set), \ - SW_API_DEF(SW_API_FDB_LEARN_EXCEED_CMD_GET, isis_fdb_learn_exceed_cmd_get), \ - SW_API_DEF(SW_API_FDB_RESV_ADD, isis_fdb_resv_add), \ - SW_API_DEF(SW_API_FDB_RESV_DEL, isis_fdb_resv_del), \ - SW_API_DEF(SW_API_FDB_RESV_FIND, isis_fdb_resv_find), \ - SW_API_DEF(SW_API_FDB_RESV_ITERATE, isis_fdb_resv_iterate), \ - SW_API_DEF(SW_API_FDB_EXTEND_FIRST, isis_fdb_extend_first), \ - SW_API_DEF(SW_API_FDB_PT_LEARN_STATIC_SET, isis_fdb_port_learn_static_set), \ - SW_API_DEF(SW_API_FDB_PT_LEARN_STATIC_GET, isis_fdb_port_learn_static_get), \ - SW_API_DEF(SW_API_FDB_PORT_ADD, isis_fdb_port_add), \ - SW_API_DEF(SW_API_FDB_PORT_DEL, isis_fdb_port_del), - -#define FDB_API_PARAM \ - SW_API_DESC(SW_API_FDB_ADD) \ - SW_API_DESC(SW_API_FDB_DELALL) \ - SW_API_DESC(SW_API_FDB_DELPORT) \ - SW_API_DESC(SW_API_FDB_DELMAC) \ - SW_API_DESC(SW_API_FDB_FIND) \ - SW_API_DESC(SW_API_FDB_EXTEND_NEXT) \ - SW_API_DESC(SW_API_FDB_EXTEND_FIRST) \ - SW_API_DESC(SW_API_FDB_TRANSFER) \ - SW_API_DESC(SW_API_FDB_PT_LEARN_SET) \ - SW_API_DESC(SW_API_FDB_PT_LEARN_GET) \ - SW_API_DESC(SW_API_FDB_AGE_CTRL_SET) \ - SW_API_DESC(SW_API_FDB_AGE_CTRL_GET) \ - SW_API_DESC(SW_API_FDB_AGE_TIME_SET) \ - SW_API_DESC(SW_API_FDB_AGE_TIME_GET) \ - SW_API_DESC(SW_API_PT_FDB_LEARN_LIMIT_SET) \ - SW_API_DESC(SW_API_PT_FDB_LEARN_LIMIT_GET) \ - SW_API_DESC(SW_API_PT_FDB_LEARN_EXCEED_CMD_SET) \ - SW_API_DESC(SW_API_PT_FDB_LEARN_EXCEED_CMD_GET) \ - SW_API_DESC(SW_API_FDB_LEARN_LIMIT_SET) \ - SW_API_DESC(SW_API_FDB_LEARN_LIMIT_GET) \ - SW_API_DESC(SW_API_FDB_LEARN_EXCEED_CMD_SET) \ - SW_API_DESC(SW_API_FDB_LEARN_EXCEED_CMD_GET) \ - SW_API_DESC(SW_API_FDB_RESV_ADD) \ - SW_API_DESC(SW_API_FDB_RESV_DEL) \ - SW_API_DESC(SW_API_FDB_RESV_FIND) \ - SW_API_DESC(SW_API_FDB_RESV_ITERATE) \ - SW_API_DESC(SW_API_FDB_EXTEND_FIRST) \ - SW_API_DESC(SW_API_FDB_PT_LEARN_STATIC_SET) \ - SW_API_DESC(SW_API_FDB_PT_LEARN_STATIC_GET) \ - SW_API_DESC(SW_API_FDB_PORT_ADD) \ - SW_API_DESC(SW_API_FDB_PORT_DEL) - -#else -#define FDB_API -#define FDB_API_PARAM -#endif - - -#ifdef IN_ACL -#define ACL_API \ - SW_API_DEF(SW_API_ACL_LIST_CREAT, isis_acl_list_creat), \ - SW_API_DEF(SW_API_ACL_LIST_DESTROY, isis_acl_list_destroy), \ - SW_API_DEF(SW_API_ACL_RULE_ADD, isis_acl_rule_add), \ - SW_API_DEF(SW_API_ACL_RULE_DELETE, isis_acl_rule_delete), \ - SW_API_DEF(SW_API_ACL_RULE_QUERY, isis_acl_rule_query), \ - SW_API_DEF(SW_API_ACL_LIST_BIND, isis_acl_list_bind), \ - SW_API_DEF(SW_API_ACL_LIST_UNBIND, isis_acl_list_unbind), \ - SW_API_DEF(SW_API_ACL_STATUS_SET, isis_acl_status_set), \ - SW_API_DEF(SW_API_ACL_STATUS_GET, isis_acl_status_get), \ - SW_API_DEF(SW_API_ACL_LIST_DUMP, isis_acl_list_dump), \ - SW_API_DEF(SW_API_ACL_RULE_DUMP, isis_acl_rule_dump), \ - SW_API_DEF(SW_API_ACL_PT_UDF_PROFILE_SET, isis_acl_port_udf_profile_set), \ - SW_API_DEF(SW_API_ACL_PT_UDF_PROFILE_GET, isis_acl_port_udf_profile_get), \ - SW_API_DEF(SW_API_ACL_RULE_ACTIVE, isis_acl_rule_active), \ - SW_API_DEF(SW_API_ACL_RULE_DEACTIVE, isis_acl_rule_deactive),\ - SW_API_DEF(SW_API_ACL_RULE_GET_OFFSET, isis_acl_rule_get_offset), - -#define ACL_API_PARAM \ - SW_API_DESC(SW_API_ACL_LIST_CREAT) \ - SW_API_DESC(SW_API_ACL_LIST_DESTROY) \ - SW_API_DESC(SW_API_ACL_RULE_ADD) \ - SW_API_DESC(SW_API_ACL_RULE_DELETE) \ - SW_API_DESC(SW_API_ACL_RULE_QUERY) \ - SW_API_DESC(SW_API_ACL_LIST_BIND) \ - SW_API_DESC(SW_API_ACL_LIST_UNBIND) \ - SW_API_DESC(SW_API_ACL_STATUS_SET) \ - SW_API_DESC(SW_API_ACL_STATUS_GET) \ - SW_API_DESC(SW_API_ACL_LIST_DUMP) \ - SW_API_DESC(SW_API_ACL_RULE_DUMP) \ - SW_API_DESC(SW_API_ACL_PT_UDF_PROFILE_SET) \ - SW_API_DESC(SW_API_ACL_PT_UDF_PROFILE_GET) \ - SW_API_DESC(SW_API_ACL_RULE_ACTIVE) \ - SW_API_DESC(SW_API_ACL_RULE_DEACTIVE) -#else -#define ACL_API -#define ACL_API_PARAM -#endif - - -#ifdef IN_QOS -#define QOS_API \ - SW_API_DEF(SW_API_QOS_QU_TX_BUF_ST_SET, isis_qos_queue_tx_buf_status_set), \ - SW_API_DEF(SW_API_QOS_QU_TX_BUF_ST_GET, isis_qos_queue_tx_buf_status_get), \ - SW_API_DEF(SW_API_QOS_QU_TX_BUF_NR_SET, isis_qos_queue_tx_buf_nr_set), \ - SW_API_DEF(SW_API_QOS_QU_TX_BUF_NR_GET, isis_qos_queue_tx_buf_nr_get), \ - SW_API_DEF(SW_API_QOS_PT_TX_BUF_ST_SET, isis_qos_port_tx_buf_status_set), \ - SW_API_DEF(SW_API_QOS_PT_TX_BUF_ST_GET, isis_qos_port_tx_buf_status_get), \ - SW_API_DEF(SW_API_QOS_PT_TX_BUF_NR_SET, isis_qos_port_tx_buf_nr_set), \ - SW_API_DEF(SW_API_QOS_PT_TX_BUF_NR_GET, isis_qos_port_tx_buf_nr_get), \ - SW_API_DEF(SW_API_QOS_PT_RX_BUF_NR_SET, isis_qos_port_rx_buf_nr_set), \ - SW_API_DEF(SW_API_QOS_PT_RX_BUF_NR_GET, isis_qos_port_rx_buf_nr_get), \ - SW_API_DEF(SW_API_QOS_PT_MODE_SET, isis_qos_port_mode_set), \ - SW_API_DEF(SW_API_QOS_PT_MODE_GET, isis_qos_port_mode_get), \ - SW_API_DEF(SW_API_QOS_PT_MODE_PRI_SET, isis_qos_port_mode_pri_set), \ - SW_API_DEF(SW_API_QOS_PT_MODE_PRI_GET, isis_qos_port_mode_pri_get), \ - SW_API_DEF(SW_API_QOS_PORT_SCH_MODE_SET, isis_qos_port_sch_mode_set), \ - SW_API_DEF(SW_API_QOS_PORT_SCH_MODE_GET, isis_qos_port_sch_mode_get), \ - SW_API_DEF(SW_API_QOS_PT_DEF_SPRI_SET, isis_qos_port_default_spri_set), \ - SW_API_DEF(SW_API_QOS_PT_DEF_SPRI_GET, isis_qos_port_default_spri_get), \ - SW_API_DEF(SW_API_QOS_PT_DEF_CPRI_SET, isis_qos_port_default_cpri_set), \ - SW_API_DEF(SW_API_QOS_PT_DEF_CPRI_GET, isis_qos_port_default_cpri_get), \ - SW_API_DEF(SW_API_QOS_QUEUE_REMARK_SET, isis_qos_queue_remark_table_set), \ - SW_API_DEF(SW_API_QOS_QUEUE_REMARK_GET, isis_qos_queue_remark_table_get), - - -#define QOS_API_PARAM \ - SW_API_DESC(SW_API_QOS_QU_TX_BUF_ST_SET) \ - SW_API_DESC(SW_API_QOS_QU_TX_BUF_ST_GET) \ - SW_API_DESC(SW_API_QOS_QU_TX_BUF_NR_SET) \ - SW_API_DESC(SW_API_QOS_QU_TX_BUF_NR_GET) \ - SW_API_DESC(SW_API_QOS_PT_TX_BUF_ST_SET) \ - SW_API_DESC(SW_API_QOS_PT_TX_BUF_ST_GET) \ - SW_API_DESC(SW_API_QOS_PT_TX_BUF_NR_SET) \ - SW_API_DESC(SW_API_QOS_PT_TX_BUF_NR_GET) \ - SW_API_DESC(SW_API_QOS_PT_RX_BUF_NR_SET) \ - SW_API_DESC(SW_API_QOS_PT_RX_BUF_NR_GET) \ - SW_API_DESC(SW_API_QOS_PT_MODE_SET) \ - SW_API_DESC(SW_API_QOS_PT_MODE_GET) \ - SW_API_DESC(SW_API_QOS_PT_MODE_PRI_SET) \ - SW_API_DESC(SW_API_QOS_PT_MODE_PRI_GET) \ - SW_API_DESC(SW_API_QOS_PORT_DEF_UP_SET) \ - SW_API_DESC(SW_API_QOS_PORT_DEF_UP_GET) \ - SW_API_DESC(SW_API_QOS_PORT_SCH_MODE_SET) \ - SW_API_DESC(SW_API_QOS_PORT_SCH_MODE_GET) \ - SW_API_DESC(SW_API_QOS_PT_DEF_SPRI_SET) \ - SW_API_DESC(SW_API_QOS_PT_DEF_SPRI_GET) \ - SW_API_DESC(SW_API_QOS_PT_DEF_CPRI_SET) \ - SW_API_DESC(SW_API_QOS_PT_DEF_CPRI_GET) \ - SW_API_DESC(SW_API_QOS_QUEUE_REMARK_SET) \ - SW_API_DESC(SW_API_QOS_QUEUE_REMARK_GET) -#else -#define QOS_API -#define QOS_API_PARAM -#endif - - -#ifdef IN_IGMP -#define IGMP_API \ - SW_API_DEF(SW_API_PT_IGMPS_MODE_SET, isis_port_igmps_status_set), \ - SW_API_DEF(SW_API_PT_IGMPS_MODE_GET, isis_port_igmps_status_get), \ - SW_API_DEF(SW_API_IGMP_MLD_CMD_SET, isis_igmp_mld_cmd_set), \ - SW_API_DEF(SW_API_IGMP_MLD_CMD_GET, isis_igmp_mld_cmd_get), \ - SW_API_DEF(SW_API_IGMP_PT_JOIN_SET, isis_port_igmp_mld_join_set), \ - SW_API_DEF(SW_API_IGMP_PT_JOIN_GET, isis_port_igmp_mld_join_get), \ - SW_API_DEF(SW_API_IGMP_PT_LEAVE_SET, isis_port_igmp_mld_leave_set), \ - SW_API_DEF(SW_API_IGMP_PT_LEAVE_GET, isis_port_igmp_mld_leave_get), \ - SW_API_DEF(SW_API_IGMP_RP_SET, isis_igmp_mld_rp_set), \ - SW_API_DEF(SW_API_IGMP_RP_GET, isis_igmp_mld_rp_get), \ - SW_API_DEF(SW_API_IGMP_ENTRY_CREAT_SET, isis_igmp_mld_entry_creat_set), \ - SW_API_DEF(SW_API_IGMP_ENTRY_CREAT_GET, isis_igmp_mld_entry_creat_get), \ - SW_API_DEF(SW_API_IGMP_ENTRY_STATIC_SET, isis_igmp_mld_entry_static_set), \ - SW_API_DEF(SW_API_IGMP_ENTRY_STATIC_GET, isis_igmp_mld_entry_static_get), \ - SW_API_DEF(SW_API_IGMP_ENTRY_LEAKY_SET, isis_igmp_mld_entry_leaky_set), \ - SW_API_DEF(SW_API_IGMP_ENTRY_LEAKY_GET, isis_igmp_mld_entry_leaky_get), \ - SW_API_DEF(SW_API_IGMP_ENTRY_V3_SET, isis_igmp_mld_entry_v3_set), \ - SW_API_DEF(SW_API_IGMP_ENTRY_V3_GET, isis_igmp_mld_entry_v3_get), \ - SW_API_DEF(SW_API_IGMP_ENTRY_QUEUE_SET, isis_igmp_mld_entry_queue_set), \ - SW_API_DEF(SW_API_IGMP_ENTRY_QUEUE_GET, isis_igmp_mld_entry_queue_get), \ - SW_API_DEF(SW_API_PT_IGMP_LEARN_LIMIT_SET, isis_port_igmp_mld_learn_limit_set), \ - SW_API_DEF(SW_API_PT_IGMP_LEARN_LIMIT_GET, isis_port_igmp_mld_learn_limit_get), \ - SW_API_DEF(SW_API_PT_IGMP_LEARN_EXCEED_CMD_SET, isis_port_igmp_mld_learn_exceed_cmd_set), \ - SW_API_DEF(SW_API_PT_IGMP_LEARN_EXCEED_CMD_GET, isis_port_igmp_mld_learn_exceed_cmd_get), \ - SW_API_DEF(SW_API_IGMP_SG_ENTRY_SET, isis_igmp_sg_entry_set), \ - SW_API_DEF(SW_API_IGMP_SG_ENTRY_CLEAR, isis_igmp_sg_entry_clear), \ - SW_API_DEF(SW_API_IGMP_SG_ENTRY_SHOW, isis_igmp_sg_entry_show), - -#define IGMP_API_PARAM \ - SW_API_DESC(SW_API_PT_IGMPS_MODE_SET) \ - SW_API_DESC(SW_API_PT_IGMPS_MODE_GET) \ - SW_API_DESC(SW_API_IGMP_MLD_CMD_SET) \ - SW_API_DESC(SW_API_IGMP_MLD_CMD_GET) \ - SW_API_DESC(SW_API_IGMP_PT_JOIN_SET) \ - SW_API_DESC(SW_API_IGMP_PT_JOIN_GET) \ - SW_API_DESC(SW_API_IGMP_PT_LEAVE_SET) \ - SW_API_DESC(SW_API_IGMP_PT_LEAVE_GET) \ - SW_API_DESC(SW_API_IGMP_RP_SET) \ - SW_API_DESC(SW_API_IGMP_RP_GET) \ - SW_API_DESC(SW_API_IGMP_ENTRY_CREAT_SET) \ - SW_API_DESC(SW_API_IGMP_ENTRY_CREAT_GET) \ - SW_API_DESC(SW_API_IGMP_ENTRY_STATIC_SET) \ - SW_API_DESC(SW_API_IGMP_ENTRY_STATIC_GET) \ - SW_API_DESC(SW_API_IGMP_ENTRY_LEAKY_SET) \ - SW_API_DESC(SW_API_IGMP_ENTRY_LEAKY_GET) \ - SW_API_DESC(SW_API_IGMP_ENTRY_V3_SET) \ - SW_API_DESC(SW_API_IGMP_ENTRY_V3_GET) \ - SW_API_DESC(SW_API_IGMP_ENTRY_QUEUE_SET) \ - SW_API_DESC(SW_API_IGMP_ENTRY_QUEUE_GET) \ - SW_API_DESC(SW_API_PT_IGMP_LEARN_LIMIT_SET) \ - SW_API_DESC(SW_API_PT_IGMP_LEARN_LIMIT_GET) \ - SW_API_DESC(SW_API_PT_IGMP_LEARN_EXCEED_CMD_SET) \ - SW_API_DESC(SW_API_PT_IGMP_LEARN_EXCEED_CMD_GET) \ - SW_API_DESC(SW_API_IGMP_SG_ENTRY_SET) \ - SW_API_DESC(SW_API_IGMP_SG_ENTRY_CLEAR) \ - SW_API_DESC(SW_API_IGMP_SG_ENTRY_SHOW) -#else -#define IGMP_API -#define IGMP_API_PARAM -#endif - - -#ifdef IN_LEAKY -#define LEAKY_API \ - SW_API_DEF(SW_API_UC_LEAKY_MODE_SET, isis_uc_leaky_mode_set), \ - SW_API_DEF(SW_API_UC_LEAKY_MODE_GET, isis_uc_leaky_mode_get), \ - SW_API_DEF(SW_API_MC_LEAKY_MODE_SET, isis_mc_leaky_mode_set), \ - SW_API_DEF(SW_API_MC_LEAKY_MODE_GET, isis_mc_leaky_mode_get), \ - SW_API_DEF(SW_API_ARP_LEAKY_MODE_SET, isis_port_arp_leaky_set), \ - SW_API_DEF(SW_API_ARP_LEAKY_MODE_GET, isis_port_arp_leaky_get), \ - SW_API_DEF(SW_API_PT_UC_LEAKY_MODE_SET, isis_port_uc_leaky_set), \ - SW_API_DEF(SW_API_PT_UC_LEAKY_MODE_GET, isis_port_uc_leaky_get), \ - SW_API_DEF(SW_API_PT_MC_LEAKY_MODE_SET, isis_port_mc_leaky_set), \ - SW_API_DEF(SW_API_PT_MC_LEAKY_MODE_GET, isis_port_mc_leaky_get), - -#define LEAKY_API_PARAM \ - SW_API_DESC(SW_API_UC_LEAKY_MODE_SET) \ - SW_API_DESC(SW_API_UC_LEAKY_MODE_GET) \ - SW_API_DESC(SW_API_MC_LEAKY_MODE_SET) \ - SW_API_DESC(SW_API_MC_LEAKY_MODE_GET) \ - SW_API_DESC(SW_API_ARP_LEAKY_MODE_SET) \ - SW_API_DESC(SW_API_ARP_LEAKY_MODE_GET) \ - SW_API_DESC(SW_API_PT_UC_LEAKY_MODE_SET) \ - SW_API_DESC(SW_API_PT_UC_LEAKY_MODE_GET) \ - SW_API_DESC(SW_API_PT_MC_LEAKY_MODE_SET) \ - SW_API_DESC(SW_API_PT_MC_LEAKY_MODE_GET) -#else -#define LEAKY_API -#define LEAKY_API_PARAM -#endif - - -#ifdef IN_MIRROR -#define MIRROR_API \ - SW_API_DEF(SW_API_MIRROR_ANALY_PT_SET, isis_mirr_analysis_port_set), \ - SW_API_DEF(SW_API_MIRROR_ANALY_PT_GET, isis_mirr_analysis_port_get), \ - SW_API_DEF(SW_API_MIRROR_IN_PT_SET, isis_mirr_port_in_set), \ - SW_API_DEF(SW_API_MIRROR_IN_PT_GET, isis_mirr_port_in_get), \ - SW_API_DEF(SW_API_MIRROR_EG_PT_SET, isis_mirr_port_eg_set), \ - SW_API_DEF(SW_API_MIRROR_EG_PT_GET, isis_mirr_port_eg_get), - -#define MIRROR_API_PARAM \ - SW_API_DESC(SW_API_MIRROR_ANALY_PT_SET) \ - SW_API_DESC(SW_API_MIRROR_ANALY_PT_GET) \ - SW_API_DESC(SW_API_MIRROR_IN_PT_SET) \ - SW_API_DESC(SW_API_MIRROR_IN_PT_GET) \ - SW_API_DESC(SW_API_MIRROR_EG_PT_SET) \ - SW_API_DESC(SW_API_MIRROR_EG_PT_GET) -#else -#define MIRROR_API -#define MIRROR_API_PARAM -#endif - - -#ifdef IN_RATE -#define RATE_API \ - SW_API_DEF(SW_API_RATE_PORT_POLICER_SET, isis_rate_port_policer_set), \ - SW_API_DEF(SW_API_RATE_PORT_POLICER_GET, isis_rate_port_policer_get), \ - SW_API_DEF(SW_API_RATE_PORT_SHAPER_SET, isis_rate_port_shaper_set), \ - SW_API_DEF(SW_API_RATE_PORT_SHAPER_GET, isis_rate_port_shaper_get), \ - SW_API_DEF(SW_API_RATE_QUEUE_SHAPER_SET, isis_rate_queue_shaper_set), \ - SW_API_DEF(SW_API_RATE_QUEUE_SHAPER_GET, isis_rate_queue_shaper_get), \ - SW_API_DEF(SW_API_RATE_ACL_POLICER_SET, isis_rate_acl_policer_set), \ - SW_API_DEF(SW_API_RATE_ACL_POLICER_GET, isis_rate_acl_policer_get), \ - SW_API_DEF(SW_API_RATE_PT_ADDRATEBYTE_SET, isis_rate_port_add_rate_byte_set), \ - SW_API_DEF(SW_API_RATE_PT_ADDRATEBYTE_GET, isis_rate_port_add_rate_byte_get), - -#define RATE_API_PARAM \ - SW_API_DESC(SW_API_RATE_PORT_POLICER_SET) \ - SW_API_DESC(SW_API_RATE_PORT_POLICER_GET) \ - SW_API_DESC(SW_API_RATE_PORT_SHAPER_SET) \ - SW_API_DESC(SW_API_RATE_PORT_SHAPER_GET) \ - SW_API_DESC(SW_API_RATE_QUEUE_SHAPER_SET) \ - SW_API_DESC(SW_API_RATE_QUEUE_SHAPER_GET) \ - SW_API_DESC(SW_API_RATE_ACL_POLICER_SET) \ - SW_API_DESC(SW_API_RATE_ACL_POLICER_GET) \ - SW_API_DESC(SW_API_RATE_PT_ADDRATEBYTE_SET) \ - SW_API_DESC(SW_API_RATE_PT_ADDRATEBYTE_GET) -#else -#define RATE_API -#define RATE_API_PARAM -#endif - - -#ifdef IN_STP -#define STP_API \ - SW_API_DEF(SW_API_STP_PT_STATE_SET, isis_stp_port_state_set), \ - SW_API_DEF(SW_API_STP_PT_STATE_GET, isis_stp_port_state_get), - -#define STP_API_PARAM \ - SW_API_DESC(SW_API_STP_PT_STATE_SET) \ - SW_API_DESC(SW_API_STP_PT_STATE_GET) -#else -#define STP_API -#define STP_API_PARAM -#endif - - -#ifdef IN_MIB -#define MIB_API \ - SW_API_DEF(SW_API_PT_MIB_GET, isis_get_mib_info), \ - SW_API_DEF(SW_API_MIB_STATUS_SET, isis_mib_status_set), \ - SW_API_DEF(SW_API_MIB_STATUS_GET, isis_mib_status_get), - -#define MIB_API_PARAM \ - SW_API_DESC(SW_API_PT_MIB_GET) \ - SW_API_DESC(SW_API_MIB_STATUS_SET) \ - SW_API_DESC(SW_API_MIB_STATUS_GET) -#else -#define MIB_API -#define MIB_API_PARAM -#endif - - -#ifdef IN_MISC -#define MISC_API \ - SW_API_DEF(SW_API_FRAME_MAX_SIZE_SET, isis_frame_max_size_set), \ - SW_API_DEF(SW_API_FRAME_MAX_SIZE_GET, isis_frame_max_size_get), \ - SW_API_DEF(SW_API_PT_UNK_UC_FILTER_SET, isis_port_unk_uc_filter_set), \ - SW_API_DEF(SW_API_PT_UNK_UC_FILTER_GET, isis_port_unk_uc_filter_get), \ - SW_API_DEF(SW_API_PT_UNK_MC_FILTER_SET, isis_port_unk_mc_filter_set), \ - SW_API_DEF(SW_API_PT_UNK_MC_FILTER_GET, isis_port_unk_mc_filter_get), \ - SW_API_DEF(SW_API_PT_BC_FILTER_SET, isis_port_bc_filter_set), \ - SW_API_DEF(SW_API_PT_BC_FILTER_GET, isis_port_bc_filter_get), \ - SW_API_DEF(SW_API_CPU_PORT_STATUS_SET, isis_cpu_port_status_set), \ - SW_API_DEF(SW_API_CPU_PORT_STATUS_GET, isis_cpu_port_status_get), \ - SW_API_DEF(SW_API_PPPOE_CMD_SET, isis_pppoe_cmd_set), \ - SW_API_DEF(SW_API_PPPOE_CMD_GET, isis_pppoe_cmd_get), \ - SW_API_DEF(SW_API_PPPOE_STATUS_SET, isis_pppoe_status_set), \ - SW_API_DEF(SW_API_PPPOE_STATUS_GET, isis_pppoe_status_get), \ - SW_API_DEF(SW_API_PT_DHCP_SET, isis_port_dhcp_set), \ - SW_API_DEF(SW_API_PT_DHCP_GET, isis_port_dhcp_get), \ - SW_API_DEF(SW_API_ARP_CMD_SET, isis_arp_cmd_set), \ - SW_API_DEF(SW_API_ARP_CMD_GET, isis_arp_cmd_get), \ - SW_API_DEF(SW_API_EAPOL_CMD_SET, isis_eapol_cmd_set), \ - SW_API_DEF(SW_API_EAPOL_CMD_GET, isis_eapol_cmd_get), \ - SW_API_DEF(SW_API_EAPOL_STATUS_SET, isis_eapol_status_set), \ - SW_API_DEF(SW_API_EAPOL_STATUS_GET, isis_eapol_status_get), \ - SW_API_DEF(SW_API_RIPV1_STATUS_SET, isis_ripv1_status_set), \ - SW_API_DEF(SW_API_RIPV1_STATUS_GET, isis_ripv1_status_get), \ - SW_API_DEF(SW_API_PT_ARP_REQ_STATUS_SET, isis_port_arp_req_status_set), \ - SW_API_DEF(SW_API_PT_ARP_REQ_STATUS_GET, isis_port_arp_req_status_get), \ - SW_API_DEF(SW_API_PT_ARP_ACK_STATUS_SET, isis_port_arp_ack_status_set), \ - SW_API_DEF(SW_API_PT_ARP_ACK_STATUS_GET, isis_port_arp_ack_status_get), \ - SW_API_DEF(SW_API_PPPOE_SESSION_TABLE_ADD, isis_pppoe_session_table_add), \ - SW_API_DEF(SW_API_PPPOE_SESSION_TABLE_DEL, isis_pppoe_session_table_del), \ - SW_API_DEF(SW_API_PPPOE_SESSION_TABLE_GET, isis_pppoe_session_table_get), \ - SW_API_DEF(SW_API_PPPOE_SESSION_ID_SET, isis_pppoe_session_id_set), \ - SW_API_DEF(SW_API_PPPOE_SESSION_ID_GET, isis_pppoe_session_id_get), \ - SW_API_DEF(SW_API_INTR_MASK_SET, isis_intr_mask_set), \ - SW_API_DEF(SW_API_INTR_MASK_GET, isis_intr_mask_get), \ - SW_API_DEF(SW_API_INTR_STATUS_GET, isis_intr_status_get), \ - SW_API_DEF(SW_API_INTR_STATUS_CLEAR, isis_intr_status_clear), \ - SW_API_DEF(SW_API_INTR_PORT_LINK_MASK_SET, isis_intr_port_link_mask_set), \ - SW_API_DEF(SW_API_INTR_PORT_LINK_MASK_GET, isis_intr_port_link_mask_get), \ - SW_API_DEF(SW_API_INTR_PORT_LINK_STATUS_GET, isis_intr_port_link_status_get), - -#define MISC_API_PARAM \ - SW_API_DESC(SW_API_FRAME_MAX_SIZE_SET) \ - SW_API_DESC(SW_API_FRAME_MAX_SIZE_GET) \ - SW_API_DESC(SW_API_PT_UNK_UC_FILTER_SET) \ - SW_API_DESC(SW_API_PT_UNK_UC_FILTER_GET) \ - SW_API_DESC(SW_API_PT_UNK_MC_FILTER_SET) \ - SW_API_DESC(SW_API_PT_UNK_MC_FILTER_GET) \ - SW_API_DESC(SW_API_PT_BC_FILTER_SET) \ - SW_API_DESC(SW_API_PT_BC_FILTER_GET) \ - SW_API_DESC(SW_API_CPU_PORT_STATUS_SET) \ - SW_API_DESC(SW_API_CPU_PORT_STATUS_GET) \ - SW_API_DESC(SW_API_PPPOE_CMD_SET) \ - SW_API_DESC(SW_API_PPPOE_CMD_GET) \ - SW_API_DESC(SW_API_PPPOE_STATUS_SET) \ - SW_API_DESC(SW_API_PPPOE_STATUS_GET) \ - SW_API_DESC(SW_API_PT_DHCP_SET) \ - SW_API_DESC(SW_API_PT_DHCP_GET) \ - SW_API_DESC(SW_API_ARP_CMD_SET) \ - SW_API_DESC(SW_API_ARP_CMD_GET) \ - SW_API_DESC(SW_API_EAPOL_CMD_SET) \ - SW_API_DESC(SW_API_EAPOL_CMD_GET) \ - SW_API_DESC(SW_API_PPPOE_SESSION_ADD) \ - SW_API_DESC(SW_API_PPPOE_SESSION_DEL) \ - SW_API_DESC(SW_API_PPPOE_SESSION_GET) \ - SW_API_DESC(SW_API_EAPOL_STATUS_SET) \ - SW_API_DESC(SW_API_EAPOL_STATUS_GET) \ - SW_API_DESC(SW_API_RIPV1_STATUS_SET) \ - SW_API_DESC(SW_API_RIPV1_STATUS_GET) \ - SW_API_DESC(SW_API_PT_ARP_REQ_STATUS_SET) \ - SW_API_DESC(SW_API_PT_ARP_REQ_STATUS_GET) \ - SW_API_DESC(SW_API_PT_ARP_ACK_STATUS_SET) \ - SW_API_DESC(SW_API_PT_ARP_ACK_STATUS_GET) \ - SW_API_DESC(SW_API_PPPOE_SESSION_TABLE_ADD) \ - SW_API_DESC(SW_API_PPPOE_SESSION_TABLE_DEL) \ - SW_API_DESC(SW_API_PPPOE_SESSION_TABLE_GET) \ - SW_API_DESC(SW_API_PPPOE_SESSION_ID_SET) \ - SW_API_DESC(SW_API_PPPOE_SESSION_ID_GET) \ - SW_API_DESC(SW_API_INTR_MASK_SET) \ - SW_API_DESC(SW_API_INTR_MASK_GET) \ - SW_API_DESC(SW_API_INTR_STATUS_GET) \ - SW_API_DESC(SW_API_INTR_STATUS_CLEAR) \ - SW_API_DESC(SW_API_INTR_PORT_LINK_MASK_SET) \ - SW_API_DESC(SW_API_INTR_PORT_LINK_MASK_GET) \ - SW_API_DESC(SW_API_INTR_PORT_LINK_STATUS_GET) -#else -#define MISC_API -#define MISC_API_PARAM -#endif - - -#ifdef IN_LED -#define LED_API \ - SW_API_DEF(SW_API_LED_PATTERN_SET, isis_led_ctrl_pattern_set), \ - SW_API_DEF(SW_API_LED_PATTERN_GET, isis_led_ctrl_pattern_get), - -#define LED_API_PARAM \ - SW_API_DESC(SW_API_LED_PATTERN_SET) \ - SW_API_DESC(SW_API_LED_PATTERN_GET) -#else -#define LED_API -#define LED_API_PARAM -#endif - -#ifdef IN_COSMAP -#define COSMAP_API \ - SW_API_DEF(SW_API_COSMAP_DSCP_TO_PRI_SET, isis_cosmap_dscp_to_pri_set), \ - SW_API_DEF(SW_API_COSMAP_DSCP_TO_PRI_GET, isis_cosmap_dscp_to_pri_get), \ - SW_API_DEF(SW_API_COSMAP_DSCP_TO_DP_SET, isis_cosmap_dscp_to_dp_set), \ - SW_API_DEF(SW_API_COSMAP_DSCP_TO_DP_GET, isis_cosmap_dscp_to_dp_get), \ - SW_API_DEF(SW_API_COSMAP_UP_TO_PRI_SET, isis_cosmap_up_to_pri_set), \ - SW_API_DEF(SW_API_COSMAP_UP_TO_PRI_GET, isis_cosmap_up_to_pri_get), \ - SW_API_DEF(SW_API_COSMAP_UP_TO_DP_SET, isis_cosmap_up_to_dp_set), \ - SW_API_DEF(SW_API_COSMAP_UP_TO_DP_GET, isis_cosmap_up_to_dp_get), \ - SW_API_DEF(SW_API_COSMAP_PRI_TO_QU_SET, isis_cosmap_pri_to_queue_set), \ - SW_API_DEF(SW_API_COSMAP_PRI_TO_QU_GET, isis_cosmap_pri_to_queue_get), \ - SW_API_DEF(SW_API_COSMAP_PRI_TO_EHQU_SET, isis_cosmap_pri_to_ehqueue_set), \ - SW_API_DEF(SW_API_COSMAP_PRI_TO_EHQU_GET, isis_cosmap_pri_to_ehqueue_get), - -#define COSMAP_API_PARAM \ - SW_API_DESC(SW_API_COSMAP_DSCP_TO_PRI_SET) \ - SW_API_DESC(SW_API_COSMAP_DSCP_TO_PRI_GET) \ - SW_API_DESC(SW_API_COSMAP_DSCP_TO_DP_SET) \ - SW_API_DESC(SW_API_COSMAP_DSCP_TO_DP_GET) \ - SW_API_DESC(SW_API_COSMAP_UP_TO_PRI_SET) \ - SW_API_DESC(SW_API_COSMAP_UP_TO_PRI_GET) \ - SW_API_DESC(SW_API_COSMAP_UP_TO_DP_SET) \ - SW_API_DESC(SW_API_COSMAP_UP_TO_DP_GET) \ - SW_API_DESC(SW_API_COSMAP_PRI_TO_QU_SET) \ - SW_API_DESC(SW_API_COSMAP_PRI_TO_QU_GET) \ - SW_API_DESC(SW_API_COSMAP_PRI_TO_EHQU_SET) \ - SW_API_DESC(SW_API_COSMAP_PRI_TO_EHQU_GET) -#else -#define COSMAP_API -#define COSMAP_API_PARAM -#endif - -#ifdef IN_SEC -#define SEC_API \ - SW_API_DEF(SW_API_SEC_NORM_SET, isis_sec_norm_item_set), \ - SW_API_DEF(SW_API_SEC_NORM_GET, isis_sec_norm_item_get), - -#define SEC_API_PARAM \ - SW_API_DESC(SW_API_SEC_NORM_SET) \ - SW_API_DESC(SW_API_SEC_NORM_GET) -#else -#define SEC_API -#define SEC_API_PARAM -#endif - -#ifdef IN_IP -#define IP_API \ - SW_API_DEF(SW_API_IP_HOST_ADD, isis_ip_host_add), \ - SW_API_DEF(SW_API_IP_HOST_DEL, isis_ip_host_del), \ - SW_API_DEF(SW_API_IP_HOST_GET, isis_ip_host_get), \ - SW_API_DEF(SW_API_IP_HOST_NEXT, isis_ip_host_next), \ - SW_API_DEF(SW_API_IP_HOST_COUNTER_BIND, isis_ip_host_counter_bind), \ - SW_API_DEF(SW_API_IP_HOST_PPPOE_BIND, isis_ip_host_pppoe_bind), \ - SW_API_DEF(SW_API_IP_PT_ARP_LEARN_SET, isis_ip_pt_arp_learn_set), \ - SW_API_DEF(SW_API_IP_PT_ARP_LEARN_GET, isis_ip_pt_arp_learn_get), \ - SW_API_DEF(SW_API_IP_ARP_LEARN_SET, isis_ip_arp_learn_set), \ - SW_API_DEF(SW_API_IP_ARP_LEARN_GET, isis_ip_arp_learn_get), \ - SW_API_DEF(SW_API_IP_SOURCE_GUARD_SET, isis_ip_source_guard_set), \ - SW_API_DEF(SW_API_IP_SOURCE_GUARD_GET, isis_ip_source_guard_get), \ - SW_API_DEF(SW_API_IP_ARP_GUARD_SET, isis_ip_arp_guard_set), \ - SW_API_DEF(SW_API_IP_ARP_GUARD_GET, isis_ip_arp_guard_get), \ - SW_API_DEF(SW_API_IP_ROUTE_STATUS_SET, isis_ip_route_status_set), \ - SW_API_DEF(SW_API_IP_ROUTE_STATUS_GET, isis_ip_route_status_get), \ - SW_API_DEF(SW_API_IP_INTF_ENTRY_ADD, isis_ip_intf_entry_add), \ - SW_API_DEF(SW_API_IP_INTF_ENTRY_DEL, isis_ip_intf_entry_del), \ - SW_API_DEF(SW_API_IP_INTF_ENTRY_NEXT, isis_ip_intf_entry_next), \ - SW_API_DEF(SW_API_IP_UNK_SOURCE_CMD_SET, isis_ip_unk_source_cmd_set), \ - SW_API_DEF(SW_API_IP_UNK_SOURCE_CMD_GET, isis_ip_unk_source_cmd_get), \ - SW_API_DEF(SW_API_ARP_UNK_SOURCE_CMD_SET, isis_arp_unk_source_cmd_set), \ - SW_API_DEF(SW_API_ARP_UNK_SOURCE_CMD_GET, isis_arp_unk_source_cmd_get), \ - SW_API_DEF(SW_API_IP_AGE_TIME_SET, isis_ip_age_time_set), \ - SW_API_DEF(SW_API_IP_AGE_TIME_GET, isis_ip_age_time_get), \ - SW_API_DEF(SW_API_WCMP_HASH_MODE_SET, isis_ip_wcmp_hash_mode_set), \ - SW_API_DEF(SW_API_WCMP_HASH_MODE_GET, isis_ip_wcmp_hash_mode_get), - -#define IP_API_PARAM \ - SW_API_DESC(SW_API_IP_HOST_ADD) \ - SW_API_DESC(SW_API_IP_HOST_DEL) \ - SW_API_DESC(SW_API_IP_HOST_GET) \ - SW_API_DESC(SW_API_IP_HOST_NEXT) \ - SW_API_DESC(SW_API_IP_HOST_COUNTER_BIND) \ - SW_API_DESC(SW_API_IP_HOST_PPPOE_BIND) \ - SW_API_DESC(SW_API_IP_PT_ARP_LEARN_SET) \ - SW_API_DESC(SW_API_IP_PT_ARP_LEARN_GET) \ - SW_API_DESC(SW_API_IP_ARP_LEARN_SET) \ - SW_API_DESC(SW_API_IP_ARP_LEARN_GET) \ - SW_API_DESC(SW_API_IP_SOURCE_GUARD_SET) \ - SW_API_DESC(SW_API_IP_SOURCE_GUARD_GET) \ - SW_API_DESC(SW_API_IP_ARP_GUARD_SET) \ - SW_API_DESC(SW_API_IP_ARP_GUARD_GET) \ - SW_API_DESC(SW_API_IP_ROUTE_STATUS_SET) \ - SW_API_DESC(SW_API_IP_ROUTE_STATUS_GET) \ - SW_API_DESC(SW_API_IP_INTF_ENTRY_ADD) \ - SW_API_DESC(SW_API_IP_INTF_ENTRY_DEL) \ - SW_API_DESC(SW_API_IP_INTF_ENTRY_NEXT) \ - SW_API_DESC(SW_API_IP_UNK_SOURCE_CMD_SET) \ - SW_API_DESC(SW_API_IP_UNK_SOURCE_CMD_GET) \ - SW_API_DESC(SW_API_ARP_UNK_SOURCE_CMD_SET) \ - SW_API_DESC(SW_API_ARP_UNK_SOURCE_CMD_GET) \ - SW_API_DESC(SW_API_IP_AGE_TIME_SET) \ - SW_API_DESC(SW_API_IP_AGE_TIME_GET) \ - SW_API_DESC(SW_API_WCMP_HASH_MODE_SET) \ - SW_API_DESC(SW_API_WCMP_HASH_MODE_GET) - -#else -#define IP_API -#define IP_API_PARAM -#endif - -#ifdef IN_NAT -#define NAT_API \ - SW_API_DEF(SW_API_NAT_ADD, isis_nat_add), \ - SW_API_DEF(SW_API_NAT_DEL, isis_nat_del), \ - SW_API_DEF(SW_API_NAT_GET, isis_nat_get), \ - SW_API_DEF(SW_API_NAT_NEXT, isis_nat_next), \ - SW_API_DEF(SW_API_NAT_COUNTER_BIND, isis_nat_counter_bind), \ - SW_API_DEF(SW_API_NAPT_ADD, isis_napt_add), \ - SW_API_DEF(SW_API_NAPT_DEL, isis_napt_del), \ - SW_API_DEF(SW_API_NAPT_GET, isis_napt_get), \ - SW_API_DEF(SW_API_NAPT_NEXT, isis_napt_next), \ - SW_API_DEF(SW_API_NAPT_COUNTER_BIND, isis_napt_counter_bind), \ - SW_API_DEF(SW_API_NAT_STATUS_SET, isis_nat_status_set), \ - SW_API_DEF(SW_API_NAT_STATUS_GET, isis_nat_status_get), \ - SW_API_DEF(SW_API_NAT_HASH_MODE_SET, isis_nat_hash_mode_set), \ - SW_API_DEF(SW_API_NAT_HASH_MODE_GET, isis_nat_hash_mode_get), \ - SW_API_DEF(SW_API_NAPT_STATUS_SET, isis_napt_status_set), \ - SW_API_DEF(SW_API_NAPT_STATUS_GET, isis_napt_status_get), \ - SW_API_DEF(SW_API_NAPT_MODE_SET, isis_napt_mode_set), \ - SW_API_DEF(SW_API_NAPT_MODE_GET, isis_napt_mode_get), \ - SW_API_DEF(SW_API_PRV_BASE_ADDR_SET, isis_nat_prv_base_addr_set), \ - SW_API_DEF(SW_API_PRV_BASE_ADDR_GET, isis_nat_prv_base_addr_get), \ - SW_API_DEF(SW_API_PRV_ADDR_MODE_SET, isis_nat_prv_addr_mode_set), \ - SW_API_DEF(SW_API_PRV_ADDR_MODE_GET, isis_nat_prv_addr_mode_get), \ - SW_API_DEF(SW_API_PUB_ADDR_ENTRY_ADD, isis_nat_pub_addr_add), \ - SW_API_DEF(SW_API_PUB_ADDR_ENTRY_DEL, isis_nat_pub_addr_del), \ - SW_API_DEF(SW_API_PUB_ADDR_ENTRY_NEXT, isis_nat_pub_addr_next), \ - SW_API_DEF(SW_API_NAT_UNK_SESSION_CMD_SET, isis_nat_unk_session_cmd_set), \ - SW_API_DEF(SW_API_NAT_UNK_SESSION_CMD_GET, isis_nat_unk_session_cmd_get), \ - SW_API_DEF(SW_API_NAT_GLOBAL_SET, isis_nat_global_set), - -#define NAT_API_PARAM \ - SW_API_DESC(SW_API_NAT_ADD) \ - SW_API_DESC(SW_API_NAT_DEL) \ - SW_API_DESC(SW_API_NAT_GET) \ - SW_API_DESC(SW_API_NAT_NEXT) \ - SW_API_DESC(SW_API_NAT_COUNTER_BIND) \ - SW_API_DESC(SW_API_NAPT_ADD) \ - SW_API_DESC(SW_API_NAPT_DEL) \ - SW_API_DESC(SW_API_NAPT_GET) \ - SW_API_DESC(SW_API_NAPT_NEXT) \ - SW_API_DESC(SW_API_NAPT_COUNTER_BIND) \ - SW_API_DESC(SW_API_NAT_STATUS_SET) \ - SW_API_DESC(SW_API_NAT_STATUS_GET) \ - SW_API_DESC(SW_API_NAT_HASH_MODE_SET) \ - SW_API_DESC(SW_API_NAT_HASH_MODE_GET) \ - SW_API_DESC(SW_API_NAPT_STATUS_SET) \ - SW_API_DESC(SW_API_NAPT_STATUS_GET) \ - SW_API_DESC(SW_API_NAPT_MODE_SET) \ - SW_API_DESC(SW_API_NAPT_MODE_GET) \ - SW_API_DESC(SW_API_PRV_BASE_ADDR_SET) \ - SW_API_DESC(SW_API_PRV_BASE_ADDR_GET) \ - SW_API_DESC(SW_API_PRV_ADDR_MODE_SET) \ - SW_API_DESC(SW_API_PRV_ADDR_MODE_GET) \ - SW_API_DESC(SW_API_PUB_ADDR_ENTRY_ADD) \ - SW_API_DESC(SW_API_PUB_ADDR_ENTRY_DEL) \ - SW_API_DESC(SW_API_PUB_ADDR_ENTRY_NEXT) \ - SW_API_DESC(SW_API_NAT_UNK_SESSION_CMD_SET) \ - SW_API_DESC(SW_API_NAT_UNK_SESSION_CMD_GET) \ - SW_API_DESC(SW_API_NAT_GLOBAL_SET) -#else -#define NAT_API -#define NAT_API_PARAM -#endif - -#ifdef IN_TRUNK -#define TRUNK_API \ - SW_API_DEF(SW_API_TRUNK_GROUP_SET, isis_trunk_group_set), \ - SW_API_DEF(SW_API_TRUNK_GROUP_GET, isis_trunk_group_get), \ - SW_API_DEF(SW_API_TRUNK_HASH_SET, isis_trunk_hash_mode_set), \ - SW_API_DEF(SW_API_TRUNK_HASH_GET, isis_trunk_hash_mode_get), \ - SW_API_DEF(SW_API_TRUNK_MAN_SA_SET, isis_trunk_manipulate_sa_set), \ - SW_API_DEF(SW_API_TRUNK_MAN_SA_GET, isis_trunk_manipulate_sa_get), - -#define TRUNK_API_PARAM \ - SW_API_DESC(SW_API_TRUNK_GROUP_SET) \ - SW_API_DESC(SW_API_TRUNK_GROUP_GET) \ - SW_API_DESC(SW_API_TRUNK_HASH_SET) \ - SW_API_DESC(SW_API_TRUNK_HASH_GET) \ - SW_API_DESC(SW_API_TRUNK_MAN_SA_SET)\ - SW_API_DESC(SW_API_TRUNK_MAN_SA_GET) -#else -#define TRUNK_API -#define TRUNK_API_PARAM -#endif - -#ifdef IN_INTERFACECONTROL -#define INTERFACECTRL_API \ - SW_API_DEF(SW_API_MAC_MODE_SET, isis_interface_mac_mode_set), \ - SW_API_DEF(SW_API_MAC_MODE_GET, isis_interface_mac_mode_get), \ - SW_API_DEF(SW_API_PORT_3AZ_STATUS_SET, isis_port_3az_status_set), \ - SW_API_DEF(SW_API_PORT_3AZ_STATUS_GET, isis_port_3az_status_get), \ - SW_API_DEF(SW_API_PHY_MODE_SET, isis_interface_phy_mode_set), \ - SW_API_DEF(SW_API_PHY_MODE_GET, isis_interface_phy_mode_get), - -#define INTERFACECTRL_API_PARAM \ - SW_API_DESC(SW_API_MAC_MODE_SET) \ - SW_API_DESC(SW_API_MAC_MODE_GET) \ - SW_API_DESC(SW_API_PORT_3AZ_STATUS_SET) \ - SW_API_DESC(SW_API_PORT_3AZ_STATUS_GET) \ - SW_API_DESC(SW_API_PHY_MODE_SET) \ - SW_API_DESC(SW_API_PHY_MODE_GET) - -#else -#define INTERFACECTRL_API -#define INTERFACECTRL_API_PARAM -#endif - -#define REG_API \ - SW_API_DEF(SW_API_PHY_GET, isis_phy_get), \ - SW_API_DEF(SW_API_PHY_SET, isis_phy_set), \ - SW_API_DEF(SW_API_REG_GET, isis_reg_get), \ - SW_API_DEF(SW_API_REG_SET, isis_reg_set), \ - SW_API_DEF(SW_API_REG_FIELD_GET, isis_reg_field_get), \ - SW_API_DEF(SW_API_REG_FIELD_SET, isis_reg_field_set), \ - SW_API_DEF(SW_API_REG_DUMP, isis_regsiter_dump), \ - SW_API_DEF(SW_API_DBG_REG_DUMP, isis_debug_regsiter_dump), - -#define REG_API_PARAM \ - SW_API_DESC(SW_API_PHY_GET) \ - SW_API_DESC(SW_API_PHY_SET) \ - SW_API_DESC(SW_API_REG_GET) \ - SW_API_DESC(SW_API_REG_SET) \ - SW_API_DESC(SW_API_REG_FIELD_GET) \ - SW_API_DESC(SW_API_REG_FIELD_SET) \ - SW_API_DESC(SW_API_REG_DUMP) \ - SW_API_DESC(SW_API_DBG_REG_DUMP) - - -#define SSDK_API \ - SW_API_DEF(SW_API_SWITCH_RESET, isis_reset), \ - SW_API_DEF(SW_API_SSDK_CFG, hsl_ssdk_cfg), \ - PORTCONTROL_API \ - VLAN_API \ - PORTVLAN_API \ - FDB_API \ - ACL_API \ - QOS_API \ - IGMP_API \ - LEAKY_API \ - MIRROR_API \ - RATE_API \ - STP_API \ - MIB_API \ - MISC_API \ - LED_API \ - COSMAP_API \ - SEC_API \ - IP_API \ - NAT_API \ - TRUNK_API \ - INTERFACECTRL_API \ - REG_API \ - SW_API_DEF(SW_API_MAX, NULL), - - -#define SSDK_PARAM \ - SW_PARAM_DEF(SW_API_SWITCH_RESET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \ - SW_PARAM_DEF(SW_API_SSDK_CFG, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \ - SW_PARAM_DEF(SW_API_SSDK_CFG, SW_SSDK_CFG, sizeof(ssdk_cfg_t), SW_PARAM_PTR|SW_PARAM_OUT, "ssdk configuration"), \ - MIB_API_PARAM \ - LEAKY_API_PARAM \ - MISC_API_PARAM \ - IGMP_API_PARAM \ - MIRROR_API_PARAM \ - PORTCONTROL_API_PARAM \ - PORTVLAN_API_PARAM \ - VLAN_API_PARAM \ - FDB_API_PARAM \ - QOS_API_PARAM \ - RATE_API_PARAM \ - STP_API_PARAM \ - ACL_API_PARAM \ - LED_API_PARAM \ - COSMAP_API_PARAM \ - SEC_API_PARAM \ - IP_API_PARAM \ - NAT_API_PARAM \ - TRUNK_API_PARAM \ - INTERFACECTRL_API_PARAM \ - REG_API_PARAM \ - SW_PARAM_DEF(SW_API_MAX, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), - -#if (defined(USER_MODE) && defined(KERNEL_MODULE)) -#undef SSDK_API -#undef SSDK_PARAM - -#define SSDK_API \ - REG_API \ - SW_API_DEF(SW_API_MAX, NULL), - -#define SSDK_PARAM \ - REG_API_PARAM \ - SW_PARAM_DEF(SW_API_MAX, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), -#endif - -#ifdef __cplusplus -} -#endif /* __cplusplus */ - -#endif /* _ISIS_API_H_ */ diff --git a/feeds/ipq807x/qca-ssdk/src/include/hsl/isis/isis_cosmap.h b/feeds/ipq807x/qca-ssdk/src/include/hsl/isis/isis_cosmap.h deleted file mode 100755 index c55ce7a73..000000000 --- a/feeds/ipq807x/qca-ssdk/src/include/hsl/isis/isis_cosmap.h +++ /dev/null @@ -1,109 +0,0 @@ -/* - * Copyright (c) 2012, The Linux Foundation. All rights reserved. - * Permission to use, copy, modify, and/or distribute this software for - * any purpose with or without fee is hereby granted, provided that the - * above copyright notice and this permission notice appear in all copies. - * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES - * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR - * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES - * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN - * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT - * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. - */ - - -/** - * @defgroup isis_cosmap ISIS_COSMAP - * @{ - */ -#ifndef _ISIS_COSMAP_H_ -#define _ISIS_COSMAP_H_ - -#ifdef __cplusplus -extern "C" { -#endif /* __cplusplus */ - -#include "fal/fal_cosmap.h" - - sw_error_t isis_cosmap_init(a_uint32_t dev_id); - -#ifdef IN_COSMAP -#define ISIS_COSMAP_INIT(rv, dev_id) \ - { \ - rv = isis_cosmap_init(dev_id); \ - SW_RTN_ON_ERROR(rv); \ - } -#else -#define ISIS_COSMAP_INIT(rv, dev_id) -#endif - -#ifdef HSL_STANDALONG - - HSL_LOCAL sw_error_t - isis_cosmap_dscp_to_pri_set(a_uint32_t dev_id, a_uint32_t dscp, - a_uint32_t pri); - - HSL_LOCAL sw_error_t - isis_cosmap_dscp_to_pri_get(a_uint32_t dev_id, a_uint32_t dscp, - a_uint32_t * pri); - - HSL_LOCAL sw_error_t - isis_cosmap_dscp_to_dp_set(a_uint32_t dev_id, a_uint32_t dscp, - a_uint32_t dp); - - HSL_LOCAL sw_error_t - isis_cosmap_dscp_to_dp_get(a_uint32_t dev_id, a_uint32_t dscp, - a_uint32_t * dp); - - HSL_LOCAL sw_error_t - isis_cosmap_up_to_pri_set(a_uint32_t dev_id, a_uint32_t up, - a_uint32_t pri); - - HSL_LOCAL sw_error_t - isis_cosmap_up_to_pri_get(a_uint32_t dev_id, a_uint32_t up, - a_uint32_t * pri); - - HSL_LOCAL sw_error_t - isis_cosmap_up_to_dp_set(a_uint32_t dev_id, a_uint32_t up, - a_uint32_t dp); - - HSL_LOCAL sw_error_t - isis_cosmap_up_to_dp_get(a_uint32_t dev_id, a_uint32_t up, - a_uint32_t * dp); - - HSL_LOCAL sw_error_t - isis_cosmap_pri_to_queue_set(a_uint32_t dev_id, a_uint32_t pri, - a_uint32_t queue); - - HSL_LOCAL sw_error_t - isis_cosmap_pri_to_queue_get(a_uint32_t dev_id, a_uint32_t pri, - a_uint32_t * queue); - - HSL_LOCAL sw_error_t - isis_cosmap_pri_to_ehqueue_set(a_uint32_t dev_id, a_uint32_t pri, - a_uint32_t queue); - - HSL_LOCAL sw_error_t - isis_cosmap_pri_to_ehqueue_get(a_uint32_t dev_id, a_uint32_t pri, - a_uint32_t * queue); - - HSL_LOCAL sw_error_t - isis_cosmap_egress_remark_set(a_uint32_t dev_id, a_uint32_t tbl_id, - fal_egress_remark_table_t * tbl); - - HSL_LOCAL sw_error_t - isis_cosmap_egress_remark_get(a_uint32_t dev_id, a_uint32_t tbl_id, - fal_egress_remark_table_t * tbl); - -#endif - -#ifdef __cplusplus -} -#endif /* __cplusplus */ -#endif /* _ISIS_COSMAP_H_ */ - -/** - * @} - */ - diff --git a/feeds/ipq807x/qca-ssdk/src/include/hsl/isis/isis_fdb.h b/feeds/ipq807x/qca-ssdk/src/include/hsl/isis/isis_fdb.h deleted file mode 100755 index 3399eea20..000000000 --- a/feeds/ipq807x/qca-ssdk/src/include/hsl/isis/isis_fdb.h +++ /dev/null @@ -1,162 +0,0 @@ -/* - * Copyright (c) 2012, The Linux Foundation. All rights reserved. - * Permission to use, copy, modify, and/or distribute this software for - * any purpose with or without fee is hereby granted, provided that the - * above copyright notice and this permission notice appear in all copies. - * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES - * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR - * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES - * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN - * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT - * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. - */ - - -/** - * @defgroup isis_fdb ISIS_FDB - * @{ - */ -#ifndef _ISIS_FDB_H_ -#define _ISIS_FDB_H_ - -#ifdef __cplusplus -extern "C" { -#endif /* __cplusplus */ - -#include "fal/fal_fdb.h" - - sw_error_t isis_fdb_init(a_uint32_t dev_id); - -#ifdef IN_FDB -#define ISIS_FDB_INIT(rv, dev_id) \ - { \ - rv = isis_fdb_init(dev_id); \ - SW_RTN_ON_ERROR(rv); \ - } -#else -#define ISIS_FDB_INIT(rv, dev_id) -#endif - -#ifdef HSL_STANDALONG - - HSL_LOCAL sw_error_t - isis_fdb_add(a_uint32_t dev_id, const fal_fdb_entry_t * entry); - - HSL_LOCAL sw_error_t - isis_fdb_find(a_uint32_t dev_id, fal_fdb_entry_t * entry); - - HSL_LOCAL sw_error_t - isis_fdb_del_all(a_uint32_t dev_id, a_uint32_t flag); - - HSL_LOCAL sw_error_t - isis_fdb_del_by_port(a_uint32_t dev_id, fal_port_t port_id, - a_uint32_t flag); - - HSL_LOCAL sw_error_t - isis_fdb_del_by_mac(a_uint32_t dev_id, const fal_fdb_entry_t * entry); - - HSL_LOCAL sw_error_t - isis_fdb_extend_next(a_uint32_t dev_id, fal_fdb_op_t * op, - fal_fdb_entry_t * entry); - - HSL_LOCAL sw_error_t - isis_fdb_extend_first(a_uint32_t dev_id, fal_fdb_op_t * option, - fal_fdb_entry_t * entry); - - HSL_LOCAL sw_error_t - isis_fdb_transfer(a_uint32_t dev_id, fal_port_t old_port, - fal_port_t new_port, a_uint32_t fid, - fal_fdb_op_t * option); - - HSL_LOCAL sw_error_t - isis_fdb_port_learn_set(a_uint32_t dev_id, fal_port_t port_id, - a_bool_t enable); - - HSL_LOCAL sw_error_t - isis_fdb_port_learn_get(a_uint32_t dev_id, fal_port_t port_id, - a_bool_t * enable); - - HSL_LOCAL sw_error_t - isis_fdb_age_ctrl_set(a_uint32_t dev_id, a_bool_t enable); - - HSL_LOCAL sw_error_t - isis_fdb_age_ctrl_get(a_uint32_t dev_id, a_bool_t * enable); - - HSL_LOCAL sw_error_t - isis_fdb_age_time_set(a_uint32_t dev_id, a_uint32_t * time); - - HSL_LOCAL sw_error_t - isis_fdb_age_time_get(a_uint32_t dev_id, a_uint32_t * time); - - HSL_LOCAL sw_error_t - isis_port_fdb_learn_limit_set(a_uint32_t dev_id, fal_port_t port_id, - a_bool_t enable, a_uint32_t cnt); - - HSL_LOCAL sw_error_t - isis_port_fdb_learn_limit_get(a_uint32_t dev_id, fal_port_t port_id, - a_bool_t * enable, a_uint32_t * cnt); - - HSL_LOCAL sw_error_t - isis_port_fdb_learn_exceed_cmd_set(a_uint32_t dev_id, - fal_port_t port_id, - fal_fwd_cmd_t cmd); - - HSL_LOCAL sw_error_t - isis_port_fdb_learn_exceed_cmd_get(a_uint32_t dev_id, - fal_port_t port_id, - fal_fwd_cmd_t * cmd); - - HSL_LOCAL sw_error_t - isis_fdb_learn_limit_set(a_uint32_t dev_id, a_bool_t enable, - a_uint32_t cnt); - - HSL_LOCAL sw_error_t - isis_fdb_learn_limit_get(a_uint32_t dev_id, a_bool_t * enable, - a_uint32_t * cnt); - - HSL_LOCAL sw_error_t - isis_fdb_learn_exceed_cmd_set(a_uint32_t dev_id, fal_fwd_cmd_t cmd); - - HSL_LOCAL sw_error_t - isis_fdb_learn_exceed_cmd_get(a_uint32_t dev_id, fal_fwd_cmd_t * cmd); - - HSL_LOCAL sw_error_t - isis_fdb_resv_add(a_uint32_t dev_id, fal_fdb_entry_t * entry); - - HSL_LOCAL sw_error_t - isis_fdb_resv_del(a_uint32_t dev_id, fal_fdb_entry_t * entry); - - HSL_LOCAL sw_error_t - isis_fdb_resv_find(a_uint32_t dev_id, fal_fdb_entry_t * entry); - - HSL_LOCAL sw_error_t - isis_fdb_resv_iterate(a_uint32_t dev_id, a_uint32_t * iterator, - fal_fdb_entry_t * entry); - - HSL_LOCAL sw_error_t - isis_fdb_port_learn_static_set(a_uint32_t dev_id, fal_port_t port_id, - a_bool_t enable); - - HSL_LOCAL sw_error_t - isis_fdb_port_learn_static_get(a_uint32_t dev_id, fal_port_t port_id, - a_bool_t * enable); - - HSL_LOCAL sw_error_t - isis_fdb_port_add(a_uint32_t dev_id, a_uint32_t fid, fal_mac_addr_t * addr, fal_port_t port_id); - - HSL_LOCAL sw_error_t - isis_fdb_port_del(a_uint32_t dev_id, a_uint32_t fid, fal_mac_addr_t * addr, fal_port_t port_id); - - -#endif - -#ifdef __cplusplus -} -#endif /* __cplusplus */ -#endif /* _ISIS_FDB_H_ */ - -/** - * @} - */ - diff --git a/feeds/ipq807x/qca-ssdk/src/include/hsl/isis/isis_igmp.h b/feeds/ipq807x/qca-ssdk/src/include/hsl/isis/isis_igmp.h deleted file mode 100755 index db293786c..000000000 --- a/feeds/ipq807x/qca-ssdk/src/include/hsl/isis/isis_igmp.h +++ /dev/null @@ -1,162 +0,0 @@ -/* - * Copyright (c) 2012, The Linux Foundation. All rights reserved. - * Permission to use, copy, modify, and/or distribute this software for - * any purpose with or without fee is hereby granted, provided that the - * above copyright notice and this permission notice appear in all copies. - * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES - * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR - * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES - * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN - * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT - * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. - */ - - -/** - * @defgroup isis_igmp ISIS_IGMP - * @{ - */ -#ifndef _ISIS_IGMP_H_ -#define _ISIS_IGMP_H_ - -#ifdef __cplusplus -extern "C" { -#endif /* __cplusplus */ - -#include "fal/fal_igmp.h" -#include "fal/fal_multi.h" - - sw_error_t - isis_igmp_init(a_uint32_t dev_id); - -#ifdef IN_IGMP -#define ISIS_IGMP_INIT(rv, dev_id) \ - { \ - rv = isis_igmp_init(dev_id); \ - SW_RTN_ON_ERROR(rv); \ - } -#else -#define ISIS_IGMP_INIT(rv, dev_id) -#endif - -#ifdef HSL_STANDALONG - - HSL_LOCAL sw_error_t - isis_port_igmps_status_set(a_uint32_t dev_id, fal_port_t port_id, a_bool_t enable); - - - HSL_LOCAL sw_error_t - isis_port_igmps_status_get(a_uint32_t dev_id, fal_port_t port_id, a_bool_t *enable); - - - HSL_LOCAL sw_error_t - isis_igmp_mld_cmd_set(a_uint32_t dev_id, fal_fwd_cmd_t cmd); - - - HSL_LOCAL sw_error_t - isis_igmp_mld_cmd_get(a_uint32_t dev_id, fal_fwd_cmd_t * cmd); - - - HSL_LOCAL sw_error_t - isis_port_igmp_mld_join_set(a_uint32_t dev_id, fal_port_t port_id, a_bool_t enable); - - - HSL_LOCAL sw_error_t - isis_port_igmp_mld_join_get(a_uint32_t dev_id, fal_port_t port_id, a_bool_t * enable); - - - HSL_LOCAL sw_error_t - isis_port_igmp_mld_leave_set(a_uint32_t dev_id, fal_port_t port_id, a_bool_t enable); - - - HSL_LOCAL sw_error_t - isis_port_igmp_mld_leave_get(a_uint32_t dev_id, fal_port_t port_id, a_bool_t * enable); - - - HSL_LOCAL sw_error_t - isis_igmp_mld_rp_set(a_uint32_t dev_id, fal_pbmp_t pts); - - - HSL_LOCAL sw_error_t - isis_igmp_mld_rp_get(a_uint32_t dev_id, fal_pbmp_t * pts); - - - HSL_LOCAL sw_error_t - isis_igmp_mld_entry_creat_set(a_uint32_t dev_id, a_bool_t enable); - - - HSL_LOCAL sw_error_t - isis_igmp_mld_entry_creat_get(a_uint32_t dev_id, a_bool_t * enable); - - - HSL_LOCAL sw_error_t - isis_igmp_mld_entry_static_set(a_uint32_t dev_id, a_bool_t enable); - - - HSL_LOCAL sw_error_t - isis_igmp_mld_entry_static_get(a_uint32_t dev_id, a_bool_t * enable); - - - HSL_LOCAL sw_error_t - isis_igmp_mld_entry_leaky_set(a_uint32_t dev_id, a_bool_t enable); - - - HSL_LOCAL sw_error_t - isis_igmp_mld_entry_leaky_get(a_uint32_t dev_id, a_bool_t * enable); - - - HSL_LOCAL sw_error_t - isis_igmp_mld_entry_v3_set(a_uint32_t dev_id, a_bool_t enable); - - - HSL_LOCAL sw_error_t - isis_igmp_mld_entry_v3_get(a_uint32_t dev_id, a_bool_t * enable); - - - HSL_LOCAL sw_error_t - isis_igmp_mld_entry_queue_set(a_uint32_t dev_id, a_bool_t enable, a_uint32_t queue); - - - HSL_LOCAL sw_error_t - isis_igmp_mld_entry_queue_get(a_uint32_t dev_id, a_bool_t * enable, a_uint32_t * queue); - - - HSL_LOCAL sw_error_t - isis_port_igmp_mld_learn_limit_set(a_uint32_t dev_id, fal_port_t port_id, - a_bool_t enable, a_uint32_t cnt); - - - HSL_LOCAL sw_error_t - isis_port_igmp_mld_learn_limit_get(a_uint32_t dev_id, fal_port_t port_id, - a_bool_t * enable, a_uint32_t * cnt); - - - HSL_LOCAL sw_error_t - isis_port_igmp_mld_learn_exceed_cmd_set(a_uint32_t dev_id, fal_port_t port_id, - fal_fwd_cmd_t cmd); - - - HSL_LOCAL sw_error_t - isis_port_igmp_mld_learn_exceed_cmd_get(a_uint32_t dev_id, fal_port_t port_id, - fal_fwd_cmd_t * cmd); - - HSL_LOCAL sw_error_t - isis_igmp_sg_entry_set(a_uint32_t dev_id, fal_igmp_sg_entry_t * entry); - - HSL_LOCAL sw_error_t - isis_igmp_sg_entry_clear(a_uint32_t dev_id, fal_igmp_sg_entry_t * entry); - - HSL_LOCAL sw_error_t - isis_igmp_sg_entry_show(a_uint32_t dev_id); - -#endif - -#ifdef __cplusplus -} -#endif /* __cplusplus */ - -#endif /* _ISIS_IGMP_H_ */ -/** - * @} - */ diff --git a/feeds/ipq807x/qca-ssdk/src/include/hsl/isis/isis_init.h b/feeds/ipq807x/qca-ssdk/src/include/hsl/isis/isis_init.h deleted file mode 100755 index 8c31c41a5..000000000 --- a/feeds/ipq807x/qca-ssdk/src/include/hsl/isis/isis_init.h +++ /dev/null @@ -1,51 +0,0 @@ -/* - * Copyright (c) 2012, The Linux Foundation. All rights reserved. - * Permission to use, copy, modify, and/or distribute this software for - * any purpose with or without fee is hereby granted, provided that the - * above copyright notice and this permission notice appear in all copies. - * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES - * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR - * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES - * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN - * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT - * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. - */ - - -/** - * @defgroup isis_init ISIS_INIT - * @{ - */ -#ifndef _ISIS_INIT_H_ -#define _ISIS_INIT_H_ - -#ifdef __cplusplus -extern "C" { -#endif /* __cplusplus */ - -#include "init/ssdk_init.h" - - - sw_error_t - isis_init(a_uint32_t dev_id, ssdk_init_cfg *cfg); - - - sw_error_t - isis_cleanup(a_uint32_t dev_id); - -#ifdef HSL_STANDALONG - - HSL_LOCAL sw_error_t - isis_reset(a_uint32_t dev_id); - -#endif - -#ifdef __cplusplus -} -#endif /* __cplusplus */ - -#endif /* _ISIS_INIT_H_ */ -/** - * @} - */ diff --git a/feeds/ipq807x/qca-ssdk/src/include/hsl/isis/isis_interface_ctrl.h b/feeds/ipq807x/qca-ssdk/src/include/hsl/isis/isis_interface_ctrl.h deleted file mode 100755 index c3618cc06..000000000 --- a/feeds/ipq807x/qca-ssdk/src/include/hsl/isis/isis_interface_ctrl.h +++ /dev/null @@ -1,64 +0,0 @@ -/* - * Copyright (c) 2012, The Linux Foundation. All rights reserved. - * Permission to use, copy, modify, and/or distribute this software for - * any purpose with or without fee is hereby granted, provided that the - * above copyright notice and this permission notice appear in all copies. - * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES - * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR - * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES - * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN - * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT - * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. - */ - - -#ifndef _ISIS_INTERFACE_CTRL_H_ -#define _ISIS_INTERFACE_CTRL_H_ - -#ifdef __cplusplus -extern "C" { -#endif /* __cplusplus */ - -#include "fal/fal_interface_ctrl.h" - - sw_error_t isis_interface_ctrl_init(a_uint32_t dev_id); - -#ifdef IN_INTERFACECONTROL -#define ISIS_INTERFACE_CTRL_INIT(rv, dev_id) \ - { \ - rv = isis_interface_ctrl_init(dev_id); \ - SW_RTN_ON_ERROR(rv); \ - } -#else -#define ISIS_INTERFACE_CTRL_INIT(rv, dev_id) -#endif - -#ifdef HSL_STANDALONG - - HSL_LOCAL sw_error_t - isis_port_3az_status_set(a_uint32_t dev_id, fal_port_t port_id, a_bool_t enable); - - HSL_LOCAL sw_error_t - isis_port_3az_status_get(a_uint32_t dev_id, fal_port_t port_id, a_bool_t * enable); - - HSL_LOCAL sw_error_t - isis_interface_mac_mode_set(a_uint32_t dev_id, fal_port_t port_id, fal_mac_config_t * config); - - - HSL_LOCAL sw_error_t - isis_interface_mac_mode_get(a_uint32_t dev_id, fal_port_t port_id, fal_mac_config_t * config); - - HSL_LOCAL sw_error_t - isis_interface_phy_mode_set(a_uint32_t dev_id, a_uint32_t phy_id, fal_phy_config_t * config); - - HSL_LOCAL sw_error_t - isis_interface_phy_mode_get(a_uint32_t dev_id, a_uint32_t phy_id, fal_phy_config_t * config); - -#endif - -#ifdef __cplusplus -} -#endif /* __cplusplus */ -#endif /* _ISIS_INTERFACE_CTRL_H_ */ - diff --git a/feeds/ipq807x/qca-ssdk/src/include/hsl/isis/isis_ip.h b/feeds/ipq807x/qca-ssdk/src/include/hsl/isis/isis_ip.h deleted file mode 100755 index 409414d58..000000000 --- a/feeds/ipq807x/qca-ssdk/src/include/hsl/isis/isis_ip.h +++ /dev/null @@ -1,153 +0,0 @@ -/* - * Copyright (c) 2012, The Linux Foundation. All rights reserved. - * Permission to use, copy, modify, and/or distribute this software for - * any purpose with or without fee is hereby granted, provided that the - * above copyright notice and this permission notice appear in all copies. - * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES - * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR - * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES - * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN - * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT - * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. - */ - - -#ifndef _ISIS_IP_H_ -#define _ISIS_IP_H_ - -#ifdef __cplusplus -extern "C" { -#endif /* __cplusplus */ - -#include "fal/fal_ip.h" - - sw_error_t isis_ip_init(a_uint32_t dev_id); - - sw_error_t isis_ip_reset(a_uint32_t dev_id); - -#ifdef IN_IP -#define ISIS_IP_INIT(rv, dev_id) \ - { \ - rv = isis_ip_init(dev_id); \ - SW_RTN_ON_ERROR(rv); \ - } - -#define ISIS_IP_RESET(rv, dev_id) \ - { \ - rv = isis_ip_reset(dev_id); \ - SW_RTN_ON_ERROR(rv); \ - } -#else -#define ISIS_IP_INIT(rv, dev_id) -#define ISIS_IP_RESET(rv, dev_id) -#endif - -#ifdef HSL_STANDALONG - - HSL_LOCAL sw_error_t - isis_ip_host_add(a_uint32_t dev_id, fal_host_entry_t * host_entry); - - HSL_LOCAL sw_error_t - isis_ip_intf_entry_add(a_uint32_t dev_id, fal_intf_mac_entry_t * entry); - - HSL_LOCAL sw_error_t - isis_ip_host_del(a_uint32_t dev_id, a_uint32_t del_mode, - fal_host_entry_t * host_entry); - - HSL_LOCAL sw_error_t - isis_ip_host_get(a_uint32_t dev_id, a_uint32_t get_mode, - fal_host_entry_t * host_entry); - - HSL_LOCAL sw_error_t - isis_ip_host_next(a_uint32_t dev_id, a_uint32_t next_mode, - fal_host_entry_t * host_entry); - - HSL_LOCAL sw_error_t - isis_ip_host_counter_bind(a_uint32_t dev_id, a_uint32_t entry_id, - a_uint32_t cnt_id, a_bool_t enable); - - HSL_LOCAL sw_error_t - isis_ip_host_pppoe_bind(a_uint32_t dev_id, a_uint32_t entry_id, - a_uint32_t pppoe_id, a_bool_t enable); - - HSL_LOCAL sw_error_t - isis_ip_pt_arp_learn_set(a_uint32_t dev_id, fal_port_t port_id, - a_uint32_t flags); - - HSL_LOCAL sw_error_t - isis_ip_pt_arp_learn_get(a_uint32_t dev_id, fal_port_t port_id, - a_uint32_t * flags); - - HSL_LOCAL sw_error_t - isis_ip_arp_learn_set(a_uint32_t dev_id, fal_arp_learn_mode_t mode); - - HSL_LOCAL sw_error_t - isis_ip_arp_learn_get(a_uint32_t dev_id, fal_arp_learn_mode_t * mode); - - HSL_LOCAL sw_error_t - isis_ip_source_guard_set(a_uint32_t dev_id, fal_port_t port_id, - fal_source_guard_mode_t mode); - - HSL_LOCAL sw_error_t - isis_ip_source_guard_get(a_uint32_t dev_id, fal_port_t port_id, - fal_source_guard_mode_t * mode); - - HSL_LOCAL sw_error_t - isis_ip_unk_source_cmd_set(a_uint32_t dev_id, fal_fwd_cmd_t cmd); - - HSL_LOCAL sw_error_t - isis_ip_unk_source_cmd_get(a_uint32_t dev_id, fal_fwd_cmd_t * cmd); - - HSL_LOCAL sw_error_t - isis_ip_arp_guard_set(a_uint32_t dev_id, fal_port_t port_id, - fal_source_guard_mode_t mode); - - HSL_LOCAL sw_error_t - isis_ip_arp_guard_get(a_uint32_t dev_id, fal_port_t port_id, - fal_source_guard_mode_t * mode); - - HSL_LOCAL sw_error_t - isis_arp_unk_source_cmd_set(a_uint32_t dev_id, fal_fwd_cmd_t cmd); - - HSL_LOCAL sw_error_t - isis_arp_unk_source_cmd_get(a_uint32_t dev_id, fal_fwd_cmd_t * cmd); - - HSL_LOCAL sw_error_t - isis_ip_route_status_set(a_uint32_t dev_id, a_bool_t enable); - - HSL_LOCAL sw_error_t - isis_ip_route_status_get(a_uint32_t dev_id, a_bool_t * enable); - - HSL_LOCAL sw_error_t - isis_ip_intf_entry_del(a_uint32_t dev_id, a_uint32_t del_mode, - fal_intf_mac_entry_t * entry); - - HSL_LOCAL sw_error_t - isis_ip_intf_entry_next(a_uint32_t dev_id, a_uint32_t next_mode, - fal_intf_mac_entry_t * entry); - - HSL_LOCAL sw_error_t - isis_ip_age_time_set(a_uint32_t dev_id, a_uint32_t * time); - - HSL_LOCAL sw_error_t - isis_ip_age_time_get(a_uint32_t dev_id, a_uint32_t * time); - - HSL_LOCAL sw_error_t - isis_ip_wcmp_entry_set(a_uint32_t dev_id, a_uint32_t wcmp_id, fal_ip_wcmp_t * wcmp); - - HSL_LOCAL sw_error_t - isis_ip_wcmp_entry_get(a_uint32_t dev_id, a_uint32_t wcmp_id, fal_ip_wcmp_t * wcmp); - - HSL_LOCAL sw_error_t - isis_ip_wcmp_hash_mode_set(a_uint32_t dev_id, a_uint32_t hash_mode); - - HSL_LOCAL sw_error_t - isis_ip_wcmp_hash_mode_get(a_uint32_t dev_id, a_uint32_t * hash_mode); - -#endif - -#ifdef __cplusplus -} -#endif /* __cplusplus */ -#endif /* _ISIS_IP_H_ */ diff --git a/feeds/ipq807x/qca-ssdk/src/include/hsl/isis/isis_leaky.h b/feeds/ipq807x/qca-ssdk/src/include/hsl/isis/isis_leaky.h deleted file mode 100755 index 02192aaa1..000000000 --- a/feeds/ipq807x/qca-ssdk/src/include/hsl/isis/isis_leaky.h +++ /dev/null @@ -1,94 +0,0 @@ -/* - * Copyright (c) 2012, The Linux Foundation. All rights reserved. - * Permission to use, copy, modify, and/or distribute this software for - * any purpose with or without fee is hereby granted, provided that the - * above copyright notice and this permission notice appear in all copies. - * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES - * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR - * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES - * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN - * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT - * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. - */ - - -#ifndef _ISIS_LEAKY_H_ -#define _ISIS_LEAKY_H_ - -#ifdef __cplusplus -extern "C" { -#endif /* __cplusplus */ - -#include "fal/fal_leaky.h" - - sw_error_t isis_leaky_init(a_uint32_t dev_id); - -#ifdef IN_LEAKY -#define ISIS_LEAKY_INIT(rv, dev_id) \ - { \ - rv = isis_leaky_init(dev_id); \ - SW_RTN_ON_ERROR(rv); \ - } -#else -#define ISIS_LEAKY_INIT(rv, dev_id) -#endif - -#ifdef HSL_STANDALONG - - - HSL_LOCAL sw_error_t - isis_uc_leaky_mode_set(a_uint32_t dev_id, - fal_leaky_ctrl_mode_t ctrl_mode); - - - HSL_LOCAL sw_error_t - isis_uc_leaky_mode_get(a_uint32_t dev_id, - fal_leaky_ctrl_mode_t * ctrl_mode); - - - HSL_LOCAL sw_error_t - isis_mc_leaky_mode_set(a_uint32_t dev_id, - fal_leaky_ctrl_mode_t ctrl_mode); - - - HSL_LOCAL sw_error_t - isis_mc_leaky_mode_get(a_uint32_t dev_id, - fal_leaky_ctrl_mode_t * ctrl_mode); - - - HSL_LOCAL sw_error_t - isis_port_arp_leaky_set(a_uint32_t dev_id, fal_port_t port_id, - a_bool_t enable); - - - HSL_LOCAL sw_error_t - isis_port_arp_leaky_get(a_uint32_t dev_id, fal_port_t port_id, - a_bool_t * enable); - - - HSL_LOCAL sw_error_t - isis_port_uc_leaky_set(a_uint32_t dev_id, fal_port_t port_id, - a_bool_t enable); - - - HSL_LOCAL sw_error_t - isis_port_uc_leaky_get(a_uint32_t dev_id, fal_port_t port_id, - a_bool_t * enable); - - - HSL_LOCAL sw_error_t - isis_port_mc_leaky_set(a_uint32_t dev_id, fal_port_t port_id, - a_bool_t enable); - - - HSL_LOCAL sw_error_t - isis_port_mc_leaky_get(a_uint32_t dev_id, fal_port_t port_id, - a_bool_t * enable); -#endif - -#ifdef __cplusplus -} -#endif /* __cplusplus */ -#endif /* _ISIS_LEAKY_H_ */ - diff --git a/feeds/ipq807x/qca-ssdk/src/include/hsl/isis/isis_led.h b/feeds/ipq807x/qca-ssdk/src/include/hsl/isis/isis_led.h deleted file mode 100755 index d11b29fbc..000000000 --- a/feeds/ipq807x/qca-ssdk/src/include/hsl/isis/isis_led.h +++ /dev/null @@ -1,57 +0,0 @@ -/* - * Copyright (c) 2012, The Linux Foundation. All rights reserved. - * Permission to use, copy, modify, and/or distribute this software for - * any purpose with or without fee is hereby granted, provided that the - * above copyright notice and this permission notice appear in all copies. - * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES - * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR - * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES - * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN - * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT - * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. - */ - - -#ifndef _ISIS_LED_H_ -#define _ISIS_LED_H_ - -#ifdef __cplusplus -extern "C" { -#endif /* __cplusplus */ - -#include "fal/fal_led.h" - - sw_error_t - isis_led_init(a_uint32_t dev_id); - -#ifdef IN_LED -#define ISIS_LED_INIT(rv, dev_id) \ - { \ - rv = isis_led_init(dev_id); \ - SW_RTN_ON_ERROR(rv); \ - } -#else -#define ISIS_LED_INIT(rv, dev_id) -#endif - -#ifdef HSL_STANDALONG - - - HSL_LOCAL sw_error_t - isis_led_ctrl_pattern_set(a_uint32_t dev_id, led_pattern_group_t group, - led_pattern_id_t id, led_ctrl_pattern_t * pattern); - - - HSL_LOCAL sw_error_t - isis_led_ctrl_pattern_get(a_uint32_t dev_id, led_pattern_group_t group, - led_pattern_id_t id, led_ctrl_pattern_t * pattern); - -#endif - -#ifdef __cplusplus -} -#endif /* __cplusplus */ - -#endif /* _ISIS_LED_H_ */ - diff --git a/feeds/ipq807x/qca-ssdk/src/include/hsl/isis/isis_mib.h b/feeds/ipq807x/qca-ssdk/src/include/hsl/isis/isis_mib.h deleted file mode 100755 index b04389009..000000000 --- a/feeds/ipq807x/qca-ssdk/src/include/hsl/isis/isis_mib.h +++ /dev/null @@ -1,59 +0,0 @@ -/* - * Copyright (c) 2012, The Linux Foundation. All rights reserved. - * Permission to use, copy, modify, and/or distribute this software for - * any purpose with or without fee is hereby granted, provided that the - * above copyright notice and this permission notice appear in all copies. - * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES - * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR - * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES - * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN - * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT - * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. - */ - - -#ifndef _ISIS_MIB_H_ -#define _ISIS_MIB_H_ - -#ifdef __cplusplus -extern "C" { -#endif /* __cplusplus */ - -#include "fal/fal_mib.h" - - sw_error_t - isis_mib_init(a_uint32_t dev_id); - -#ifdef IN_MIB -#define ISIS_MIB_INIT(rv, dev_id) \ - { \ - rv = isis_mib_init(dev_id); \ - SW_RTN_ON_ERROR(rv); \ - } -#else -#define ISIS_MIB_INIT(rv, dev_id) -#endif - -#ifdef HSL_STANDALONG - - HSL_LOCAL sw_error_t - isis_get_mib_info(a_uint32_t dev_id, fal_port_t port_id, - fal_mib_info_t * mib_info ); - - - HSL_LOCAL sw_error_t - isis_mib_status_set(a_uint32_t dev_id, a_bool_t enable); - - - HSL_LOCAL sw_error_t - isis_mib_status_get(a_uint32_t dev_id, a_bool_t * enable); - -#endif - -#ifdef __cplusplus -} -#endif /* __cplusplus */ - -#endif /* _ISIS_MIB_H_ */ - diff --git a/feeds/ipq807x/qca-ssdk/src/include/hsl/isis/isis_mirror.h b/feeds/ipq807x/qca-ssdk/src/include/hsl/isis/isis_mirror.h deleted file mode 100755 index 793316812..000000000 --- a/feeds/ipq807x/qca-ssdk/src/include/hsl/isis/isis_mirror.h +++ /dev/null @@ -1,73 +0,0 @@ -/* - * Copyright (c) 2012, The Linux Foundation. All rights reserved. - * Permission to use, copy, modify, and/or distribute this software for - * any purpose with or without fee is hereby granted, provided that the - * above copyright notice and this permission notice appear in all copies. - * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES - * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR - * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES - * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN - * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT - * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. - */ - - -#ifndef _ISIS_MIRROR_H_ -#define _ISIS_MIRROR_H_ - -#ifdef __cplusplus -extern "C" { -#endif /* __cplusplus */ - -#include "fal/fal_mirror.h" -#define MIRROR_ANALYZER_NONE 0xf - - sw_error_t isis_mirr_init(a_uint32_t dev_id); - -#ifdef IN_MIRROR -#define ISIS_MIRR_INIT(rv, dev_id) \ - { \ - rv = isis_mirr_init(dev_id); \ - SW_RTN_ON_ERROR(rv); \ - } -#else -#define ISIS_MIRR_INIT(rv, dev_id) -#endif - -#ifdef HSL_STANDALONG - - HSL_LOCAL sw_error_t - isis_mirr_analysis_port_set(a_uint32_t dev_id, fal_port_t port_id); - - - HSL_LOCAL sw_error_t - isis_mirr_analysis_port_get(a_uint32_t dev_id, fal_port_t * port_id); - - - HSL_LOCAL sw_error_t - isis_mirr_port_in_set(a_uint32_t dev_id, fal_port_t port_id, - a_bool_t enable); - - - HSL_LOCAL sw_error_t - isis_mirr_port_in_get(a_uint32_t dev_id, fal_port_t port_id, - a_bool_t * enable); - - - HSL_LOCAL sw_error_t - isis_mirr_port_eg_set(a_uint32_t dev_id, fal_port_t port_id, - a_bool_t enable); - - - HSL_LOCAL sw_error_t - isis_mirr_port_eg_get(a_uint32_t dev_id, fal_port_t port_id, - a_bool_t * enable); - -#endif - -#ifdef __cplusplus -} -#endif /* __cplusplus */ -#endif /* _ISIS_MIRROR_H_ */ - diff --git a/feeds/ipq807x/qca-ssdk/src/include/hsl/isis/isis_misc.h b/feeds/ipq807x/qca-ssdk/src/include/hsl/isis/isis_misc.h deleted file mode 100755 index c0a70f046..000000000 --- a/feeds/ipq807x/qca-ssdk/src/include/hsl/isis/isis_misc.h +++ /dev/null @@ -1,212 +0,0 @@ -/* - * Copyright (c) 2012, The Linux Foundation. All rights reserved. - * Permission to use, copy, modify, and/or distribute this software for - * any purpose with or without fee is hereby granted, provided that the - * above copyright notice and this permission notice appear in all copies. - * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES - * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR - * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES - * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN - * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT - * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. - */ - - -#ifndef _ISIS_MISC_H_ -#define _ISIS_MISC_H_ - -#ifdef __cplusplus -extern "C" { -#endif /* __cplusplus */ - -#include "fal/fal_misc.h" - - sw_error_t isis_misc_init(a_uint32_t dev_id); - -#ifdef IN_MISC -#define ISIS_MISC_INIT(rv, dev_id) \ - { \ - rv = isis_misc_init(dev_id); \ - SW_RTN_ON_ERROR(rv); \ - } -#else -#define ISIS_MISC_INIT(rv, dev_id) -#endif - -#ifdef HSL_STANDALONG - - - HSL_LOCAL sw_error_t - isis_frame_max_size_set(a_uint32_t dev_id, a_uint32_t size); - - - HSL_LOCAL sw_error_t - isis_frame_max_size_get(a_uint32_t dev_id, a_uint32_t * size); - - - HSL_LOCAL sw_error_t - isis_port_unk_uc_filter_set(a_uint32_t dev_id, fal_port_t port_id, - a_bool_t enable); - - - HSL_LOCAL sw_error_t - isis_port_unk_uc_filter_get(a_uint32_t dev_id, fal_port_t port_id, - a_bool_t * enable); - - - HSL_LOCAL sw_error_t - isis_port_unk_mc_filter_set(a_uint32_t dev_id, fal_port_t port_id, - a_bool_t enable); - - - HSL_LOCAL sw_error_t - isis_port_unk_mc_filter_get(a_uint32_t dev_id, fal_port_t port_id, - a_bool_t * enable); - - - HSL_LOCAL sw_error_t - isis_port_bc_filter_set(a_uint32_t dev_id, fal_port_t port_id, - a_bool_t enable); - - - HSL_LOCAL sw_error_t - isis_port_bc_filter_get(a_uint32_t dev_id, fal_port_t port_id, - a_bool_t * enable); - - - HSL_LOCAL sw_error_t - isis_cpu_port_status_set(a_uint32_t dev_id, a_bool_t enable); - - - HSL_LOCAL sw_error_t - isis_cpu_port_status_get(a_uint32_t dev_id, a_bool_t * enable); - - - HSL_LOCAL sw_error_t - isis_pppoe_cmd_set(a_uint32_t dev_id, fal_fwd_cmd_t cmd); - - - HSL_LOCAL sw_error_t - isis_pppoe_cmd_get(a_uint32_t dev_id, fal_fwd_cmd_t * cmd); - - - HSL_LOCAL sw_error_t - isis_pppoe_status_set(a_uint32_t dev_id, a_bool_t enable); - - - HSL_LOCAL sw_error_t - isis_pppoe_status_get(a_uint32_t dev_id, a_bool_t * enable); - - - HSL_LOCAL sw_error_t - isis_port_dhcp_set(a_uint32_t dev_id, fal_port_t port_id, a_bool_t enable); - - - HSL_LOCAL sw_error_t - isis_port_dhcp_get(a_uint32_t dev_id, fal_port_t port_id, a_bool_t * enable); - - - HSL_LOCAL sw_error_t - isis_arp_cmd_set(a_uint32_t dev_id, fal_fwd_cmd_t cmd); - - - HSL_LOCAL sw_error_t - isis_arp_cmd_get(a_uint32_t dev_id, fal_fwd_cmd_t * cmd); - - - HSL_LOCAL sw_error_t - isis_eapol_cmd_set(a_uint32_t dev_id, fal_fwd_cmd_t cmd); - - - HSL_LOCAL sw_error_t - isis_eapol_cmd_get(a_uint32_t dev_id, fal_fwd_cmd_t * cmd); - - - HSL_LOCAL sw_error_t - isis_pppoe_session_table_add(a_uint32_t dev_id, fal_pppoe_session_t * session_tbl); - - - HSL_LOCAL sw_error_t - isis_pppoe_session_table_del(a_uint32_t dev_id, fal_pppoe_session_t * session_tbl); - - - HSL_LOCAL sw_error_t - isis_pppoe_session_table_get(a_uint32_t dev_id, fal_pppoe_session_t * session_tbl); - - - HSL_LOCAL sw_error_t - isis_pppoe_session_id_set(a_uint32_t dev_id, a_uint32_t index, - a_uint32_t id); - - - HSL_LOCAL sw_error_t - isis_pppoe_session_id_get(a_uint32_t dev_id, a_uint32_t index, - a_uint32_t * id); - - - HSL_LOCAL sw_error_t - isis_eapol_status_set(a_uint32_t dev_id, a_uint32_t port_id, a_bool_t enable); - - HSL_LOCAL sw_error_t - isis_eapol_status_get(a_uint32_t dev_id, a_uint32_t port_id, a_bool_t * enable); - - HSL_LOCAL sw_error_t - isis_ripv1_status_set(a_uint32_t dev_id, a_bool_t enable); - - HSL_LOCAL sw_error_t - isis_ripv1_status_get(a_uint32_t dev_id, a_bool_t * enable); - - - HSL_LOCAL sw_error_t - isis_port_arp_req_status_set(a_uint32_t dev_id, fal_port_t port_id, a_bool_t enable); - - - HSL_LOCAL sw_error_t - isis_port_arp_req_status_get(a_uint32_t dev_id, fal_port_t port_id, a_bool_t *enable); - - - HSL_LOCAL sw_error_t - isis_port_arp_ack_status_set(a_uint32_t dev_id, fal_port_t port_id, a_bool_t enable); - - - HSL_LOCAL sw_error_t - isis_port_arp_ack_status_get(a_uint32_t dev_id, fal_port_t port_id, a_bool_t *enable); - - - HSL_LOCAL sw_error_t - isis_intr_mask_set(a_uint32_t dev_id, a_uint32_t intr_mask); - - - HSL_LOCAL sw_error_t - isis_intr_mask_get(a_uint32_t dev_id, a_uint32_t * intr_mask); - - - HSL_LOCAL sw_error_t - isis_intr_status_get(a_uint32_t dev_id, a_uint32_t * intr_status); - - - HSL_LOCAL sw_error_t - isis_intr_status_clear(a_uint32_t dev_id, a_uint32_t intr_status); - - - HSL_LOCAL sw_error_t - isis_intr_port_link_mask_set(a_uint32_t dev_id, a_uint32_t port_id, a_uint32_t intr_mask_flag); - - - HSL_LOCAL sw_error_t - isis_intr_port_link_mask_get(a_uint32_t dev_id, a_uint32_t port_id, a_uint32_t * intr_mask_flag); - - - HSL_LOCAL sw_error_t - isis_intr_port_link_status_get(a_uint32_t dev_id, a_uint32_t port_id, a_uint32_t * intr_mask_flag); - - -#endif - -#ifdef __cplusplus -} -#endif /* __cplusplus */ - -#endif - diff --git a/feeds/ipq807x/qca-ssdk/src/include/hsl/isis/isis_nat.h b/feeds/ipq807x/qca-ssdk/src/include/hsl/isis/isis_nat.h deleted file mode 100755 index 2dcb93c81..000000000 --- a/feeds/ipq807x/qca-ssdk/src/include/hsl/isis/isis_nat.h +++ /dev/null @@ -1,153 +0,0 @@ -/* - * Copyright (c) 2012, The Linux Foundation. All rights reserved. - * Permission to use, copy, modify, and/or distribute this software for - * any purpose with or without fee is hereby granted, provided that the - * above copyright notice and this permission notice appear in all copies. - * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES - * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR - * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES - * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN - * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT - * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. - */ - - -#ifndef _ISIS_NAT_H_ -#define _ISIS_NAT_H_ - -#ifdef __cplusplus -extern "C" { -#endif /* __cplusplus */ - -#include "fal/fal_nat.h" - - sw_error_t isis_nat_init(a_uint32_t dev_id); - - sw_error_t isis_nat_reset(a_uint32_t dev_id); - -#ifdef IN_NAT -#define ISIS_NAT_INIT(rv, dev_id) \ - { \ - rv = isis_nat_init(dev_id); \ - SW_RTN_ON_ERROR(rv); \ - } - -#define ISIS_NAT_RESET(rv, dev_id) \ - { \ - rv = isis_nat_reset(dev_id); \ - SW_RTN_ON_ERROR(rv); \ - } -#else -#define ISIS_NAT_INIT(rv, dev_id) -#define ISIS_NAT_RESET(rv, dev_id) -#endif - -#ifdef HSL_STANDALONG - - HSL_LOCAL sw_error_t - isis_napt_add(a_uint32_t dev_id, fal_napt_entry_t * napt_entry); - - HSL_LOCAL sw_error_t - isis_nat_pub_addr_add(a_uint32_t dev_id, fal_nat_pub_addr_t * entry); - - HSL_LOCAL sw_error_t - isis_napt_next(a_uint32_t dev_id, a_uint32_t next_mode, - fal_napt_entry_t * napt_entry); - - HSL_LOCAL sw_error_t - isis_nat_prv_base_addr_set(a_uint32_t dev_id, fal_ip4_addr_t addr); - - HSL_LOCAL sw_error_t - isis_napt_del(a_uint32_t dev_id, a_uint32_t del_mode, - fal_napt_entry_t * napt_entry); - - HSL_LOCAL sw_error_t - isis_nat_del(a_uint32_t dev_id, a_uint32_t del_mode, - fal_nat_entry_t * nat_entry); - - HSL_LOCAL sw_error_t - isis_nat_pub_addr_del(a_uint32_t dev_id, a_uint32_t del_mode, - fal_nat_pub_addr_t * entry); - - HSL_LOCAL sw_error_t - isis_nat_add(a_uint32_t dev_id, fal_nat_entry_t * nat_entry); - - HSL_LOCAL sw_error_t - isis_nat_get(a_uint32_t dev_id, a_uint32_t get_mode, - fal_nat_entry_t * nat_entry); - - HSL_LOCAL sw_error_t - isis_nat_next(a_uint32_t dev_id, a_uint32_t next_mode, - fal_nat_entry_t * nat_entry); - - HSL_LOCAL sw_error_t - isis_nat_counter_bind(a_uint32_t dev_id, a_uint32_t entry_id, - a_uint32_t cnt_id, a_bool_t enable); - - HSL_LOCAL sw_error_t - isis_napt_get(a_uint32_t dev_id, a_uint32_t get_mode, - fal_napt_entry_t * napt_entry); - - HSL_LOCAL sw_error_t - isis_napt_counter_bind(a_uint32_t dev_id, a_uint32_t entry_id, - a_uint32_t cnt_id, a_bool_t enable); - - HSL_LOCAL sw_error_t - isis_nat_status_set(a_uint32_t dev_id, a_bool_t enable); - - HSL_LOCAL sw_error_t - isis_nat_status_get(a_uint32_t dev_id, a_bool_t * enable); - - HSL_LOCAL sw_error_t - isis_nat_hash_mode_set(a_uint32_t dev_id, a_uint32_t mode); - - HSL_LOCAL sw_error_t - isis_nat_hash_mode_get(a_uint32_t dev_id, a_uint32_t * mode); - - HSL_LOCAL sw_error_t - isis_napt_status_set(a_uint32_t dev_id, a_bool_t enable); - - HSL_LOCAL sw_error_t - isis_napt_status_get(a_uint32_t dev_id, a_bool_t * enable); - - HSL_LOCAL sw_error_t - isis_napt_mode_set(a_uint32_t dev_id, fal_napt_mode_t mode); - - HSL_LOCAL sw_error_t - isis_napt_mode_get(a_uint32_t dev_id, fal_napt_mode_t * mode); - - HSL_LOCAL sw_error_t - isis_nat_prv_base_addr_get(a_uint32_t dev_id, fal_ip4_addr_t * addr); - - HSL_LOCAL sw_error_t - isis_nat_prv_addr_mode_set(a_uint32_t dev_id, a_bool_t map_en); - - HSL_LOCAL sw_error_t - isis_nat_prv_addr_mode_get(a_uint32_t dev_id, a_bool_t * map_en); - - HSL_LOCAL sw_error_t - isis_nat_pub_addr_next(a_uint32_t dev_id, a_uint32_t next_mode, - fal_nat_pub_addr_t * entry); - - HSL_LOCAL sw_error_t - isis_nat_unk_session_cmd_set(a_uint32_t dev_id, fal_fwd_cmd_t cmd); - - HSL_LOCAL sw_error_t - isis_nat_unk_session_cmd_get(a_uint32_t dev_id, fal_fwd_cmd_t * cmd); - - HSL_LOCAL sw_error_t - isis_nat_psr_prv_base_addr_set(a_uint32_t dev_id, fal_ip4_addr_t addr); - - HSL_LOCAL sw_error_t - isis_nat_psr_prv_base_addr_get(a_uint32_t dev_id, fal_ip4_addr_t * addr); - - HSL_LOCAL sw_error_t - isis_nat_global_set(a_uint32_t dev_id, a_bool_t enable); - -#endif - -#ifdef __cplusplus -} -#endif /* __cplusplus */ -#endif /* _ISIS_NAT_H_ */ diff --git a/feeds/ipq807x/qca-ssdk/src/include/hsl/isis/isis_nat_helper.h b/feeds/ipq807x/qca-ssdk/src/include/hsl/isis/isis_nat_helper.h deleted file mode 100755 index 945079e19..000000000 --- a/feeds/ipq807x/qca-ssdk/src/include/hsl/isis/isis_nat_helper.h +++ /dev/null @@ -1,50 +0,0 @@ -/* - * Copyright (c) 2012, The Linux Foundation. All rights reserved. - * Permission to use, copy, modify, and/or distribute this software for - * any purpose with or without fee is hereby granted, provided that the - * above copyright notice and this permission notice appear in all copies. - * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES - * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR - * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES - * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN - * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT - * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. - */ - - -#ifndef _ISIS_NAT_HELPER_H_ -#define _ISIS_NAT_HELPER_H_ - -#ifdef __cplusplus -extern "C" { -#endif /* __cplusplus */ - -#include "fal/fal_nat.h" - - sw_error_t nat_helper_init(a_uint32_t dev_id, a_uint32_t portbmp); - - sw_error_t nat_helper_cleanup(a_uint32_t dev_id); - -#ifdef IN_NAT_HELPER -#define ISIS_NAT_HELPER_INIT(rv, dev_id, portbmp) \ - { \ - rv = nat_helper_init(dev_id, portbmp); \ - SW_RTN_ON_ERROR(rv); \ - } - -#define ISIS_NAT_HELPER_CLEANUP(rv, dev_id) \ - { \ - rv = nat_helper_cleanup(dev_id); \ - SW_RTN_ON_ERROR(rv); \ - } -#else -#define ISIS_NAT_HELPER_INIT(rv, dev_id, portbmp) -#define ISIS_NAT_HELPER_CLEANUP(rv, dev_id) -#endif - - -#ifdef __cplusplus -} -#endif /* __cplusplus */ -#endif /* _ISIS_NAT_HELPER_H_ */ diff --git a/feeds/ipq807x/qca-ssdk/src/include/hsl/isis/isis_port_ctrl.h b/feeds/ipq807x/qca-ssdk/src/include/hsl/isis/isis_port_ctrl.h deleted file mode 100755 index dd136d684..000000000 --- a/feeds/ipq807x/qca-ssdk/src/include/hsl/isis/isis_port_ctrl.h +++ /dev/null @@ -1,224 +0,0 @@ -/* - * Copyright (c) 2012, The Linux Foundation. All rights reserved. - * Permission to use, copy, modify, and/or distribute this software for - * any purpose with or without fee is hereby granted, provided that the - * above copyright notice and this permission notice appear in all copies. - * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES - * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR - * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES - * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN - * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT - * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. - */ - - -#ifndef _ISIS_PORT_CTRL_H_ -#define _ISIS_PORT_CTRL_H_ - -#ifdef __cplusplus -extern "C" { -#endif /* __cplusplus */ - -#include "fal/fal_port_ctrl.h" - - sw_error_t isis_port_ctrl_init(a_uint32_t dev_id); - -#ifdef IN_PORTCONTROL -#define ISIS_PORT_CTRL_INIT(rv, dev_id) \ - { \ - rv = isis_port_ctrl_init(dev_id); \ - SW_RTN_ON_ERROR(rv); \ - } -#else -#define ISIS_PORT_CTRL_INIT(rv, dev_id) -#endif - -#ifdef HSL_STANDALONG - - - HSL_LOCAL sw_error_t - isis_port_duplex_set(a_uint32_t dev_id, fal_port_t port_id, - fal_port_duplex_t duplex); - - - HSL_LOCAL sw_error_t - isis_port_duplex_get(a_uint32_t dev_id, fal_port_t port_id, - fal_port_duplex_t * pduplex); - - - HSL_LOCAL sw_error_t - isis_port_speed_set(a_uint32_t dev_id, fal_port_t port_id, - fal_port_speed_t speed); - - - HSL_LOCAL sw_error_t - isis_port_speed_get(a_uint32_t dev_id, fal_port_t port_id, - fal_port_speed_t * pspeed); - - - HSL_LOCAL sw_error_t - isis_port_autoneg_status_get(a_uint32_t dev_id, fal_port_t port_id, - a_bool_t * status); - - - HSL_LOCAL sw_error_t - isis_port_autoneg_enable(a_uint32_t dev_id, fal_port_t port_id); - - - HSL_LOCAL sw_error_t - isis_port_autoneg_restart(a_uint32_t dev_id, fal_port_t port_id); - - - HSL_LOCAL sw_error_t - isis_port_autoneg_adv_set(a_uint32_t dev_id, fal_port_t port_id, - a_uint32_t autoadv); - - - HSL_LOCAL sw_error_t - isis_port_autoneg_adv_get(a_uint32_t dev_id, fal_port_t port_id, - a_uint32_t * autoadv); - - - HSL_LOCAL sw_error_t - isis_port_flowctrl_set(a_uint32_t dev_id, fal_port_t port_id, - a_bool_t enable); - - - HSL_LOCAL sw_error_t - isis_port_flowctrl_get(a_uint32_t dev_id, fal_port_t port_id, - a_bool_t * enable); - - - HSL_LOCAL sw_error_t - isis_port_flowctrl_forcemode_set(a_uint32_t dev_id, - fal_port_t port_id, a_bool_t enable); - - - HSL_LOCAL sw_error_t - isis_port_flowctrl_forcemode_get(a_uint32_t dev_id, - fal_port_t port_id, - a_bool_t * enable); - - - HSL_LOCAL sw_error_t - isis_port_powersave_set(a_uint32_t dev_id, fal_port_t port_id, a_bool_t enable); - - - HSL_LOCAL sw_error_t - isis_port_powersave_get(a_uint32_t dev_id, fal_port_t port_id, a_bool_t *enable); - - - HSL_LOCAL sw_error_t - isis_port_hibernate_set(a_uint32_t dev_id, fal_port_t port_id, a_bool_t enable); - - - HSL_LOCAL sw_error_t - isis_port_hibernate_get(a_uint32_t dev_id, fal_port_t port_id, a_bool_t *enable); - - - HSL_LOCAL sw_error_t - isis_port_cdt(a_uint32_t dev_id, fal_port_t port_id, a_uint32_t mdi_pair, - fal_cable_status_t *cable_status, a_uint32_t *cable_len); - - - HSL_LOCAL sw_error_t - isis_port_rxhdr_mode_set(a_uint32_t dev_id, fal_port_t port_id, - fal_port_header_mode_t mode); - - - HSL_LOCAL sw_error_t - isis_port_rxhdr_mode_get(a_uint32_t dev_id, fal_port_t port_id, - fal_port_header_mode_t * mode); - - - HSL_LOCAL sw_error_t - isis_port_txhdr_mode_set(a_uint32_t dev_id, fal_port_t port_id, - fal_port_header_mode_t mode); - - - HSL_LOCAL sw_error_t - isis_port_txhdr_mode_get(a_uint32_t dev_id, fal_port_t port_id, - fal_port_header_mode_t * mode); - - - HSL_LOCAL sw_error_t - isis_header_type_set(a_uint32_t dev_id, a_bool_t enable, a_uint32_t type); - - - HSL_LOCAL sw_error_t - isis_header_type_get(a_uint32_t dev_id, a_bool_t * enable, a_uint32_t * type); - - - HSL_LOCAL sw_error_t - isis_port_txmac_status_set(a_uint32_t dev_id, fal_port_t port_id, a_bool_t enable); - - - HSL_LOCAL sw_error_t - isis_port_txmac_status_get(a_uint32_t dev_id, fal_port_t port_id, a_bool_t * enable); - - - HSL_LOCAL sw_error_t - isis_port_rxmac_status_set(a_uint32_t dev_id, fal_port_t port_id, a_bool_t enable); - - - HSL_LOCAL sw_error_t - isis_port_rxmac_status_get(a_uint32_t dev_id, fal_port_t port_id, a_bool_t * enable); - - - HSL_LOCAL sw_error_t - isis_port_txfc_status_set(a_uint32_t dev_id, fal_port_t port_id, a_bool_t enable); - - - HSL_LOCAL sw_error_t - isis_port_txfc_status_get(a_uint32_t dev_id, fal_port_t port_id, a_bool_t * enable); - - - HSL_LOCAL sw_error_t - isis_port_rxfc_status_set(a_uint32_t dev_id, fal_port_t port_id, a_bool_t enable); - - - HSL_LOCAL sw_error_t - isis_port_rxfc_status_get(a_uint32_t dev_id, fal_port_t port_id, a_bool_t * enable); - - - HSL_LOCAL sw_error_t - isis_port_bp_status_set(a_uint32_t dev_id, fal_port_t port_id, a_bool_t enable); - - - HSL_LOCAL sw_error_t - isis_port_bp_status_get(a_uint32_t dev_id, fal_port_t port_id, a_bool_t * enable); - - - HSL_LOCAL sw_error_t - isis_port_link_forcemode_set(a_uint32_t dev_id, fal_port_t port_id, a_bool_t enable); - - - HSL_LOCAL sw_error_t - isis_port_link_forcemode_get(a_uint32_t dev_id, fal_port_t port_id, a_bool_t * enable); - - - HSL_LOCAL sw_error_t - isis_port_link_status_get(a_uint32_t dev_id, fal_port_t port_id, a_bool_t * status); - - HSL_LOCAL sw_error_t - isis_port_mac_loopback_set(a_uint32_t dev_id, fal_port_t port_id, a_bool_t enable); - - - HSL_LOCAL sw_error_t - isis_port_mac_loopback_get(a_uint32_t dev_id, fal_port_t port_id, a_bool_t * enable); - - HSL_LOCAL sw_error_t - isis_port_8023az_set (a_uint32_t dev_id, fal_port_t port_id, a_bool_t enable); - - HSL_LOCAL sw_error_t - isis_port_8023az_get (a_uint32_t dev_id, fal_port_t port_id, a_bool_t *enable); - - -#endif - -#ifdef __cplusplus -} -#endif /* __cplusplus */ -#endif /* _ISIS_PORT_CTRL_H_ */ - diff --git a/feeds/ipq807x/qca-ssdk/src/include/hsl/isis/isis_portvlan.h b/feeds/ipq807x/qca-ssdk/src/include/hsl/isis/isis_portvlan.h deleted file mode 100755 index a4ef074aa..000000000 --- a/feeds/ipq807x/qca-ssdk/src/include/hsl/isis/isis_portvlan.h +++ /dev/null @@ -1,216 +0,0 @@ -/* - * Copyright (c) 2012, The Linux Foundation. All rights reserved. - * Permission to use, copy, modify, and/or distribute this software for - * any purpose with or without fee is hereby granted, provided that the - * above copyright notice and this permission notice appear in all copies. - * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES - * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR - * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES - * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN - * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT - * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. - */ - - -#ifndef _ISIS_PORTVLAN_H_ -#define _ISIS_PORTVLAN_H_ - -#ifdef __cplusplus -extern "C" { -#endif /* __cplusplus */ - -#include "fal/fal_portvlan.h" - - sw_error_t isis_portvlan_init(a_uint32_t dev_id); - -#ifdef IN_PORTVLAN -#define ISIS_PORTVLAN_INIT(rv, dev_id) \ - { \ - rv = isis_portvlan_init(dev_id); \ - SW_RTN_ON_ERROR(rv); \ - } -#else -#define ISIS_PORTVLAN_INIT(rv, dev_id) -#endif - -#ifdef HSL_STANDALONG - - - HSL_LOCAL sw_error_t - isis_port_1qmode_set(a_uint32_t dev_id, fal_port_t port_id, - fal_pt_1qmode_t port_1qmode); - - - HSL_LOCAL sw_error_t - isis_port_1qmode_get(a_uint32_t dev_id, fal_port_t port_id, - fal_pt_1qmode_t * pport_1qmode); - - - HSL_LOCAL sw_error_t - isis_port_egvlanmode_set(a_uint32_t dev_id, fal_port_t port_id, - fal_pt_1q_egmode_t port_egvlanmode); - - - HSL_LOCAL sw_error_t - isis_port_egvlanmode_get(a_uint32_t dev_id, fal_port_t port_id, - fal_pt_1q_egmode_t * pport_egvlanmode); - - - HSL_LOCAL sw_error_t - isis_portvlan_member_add(a_uint32_t dev_id, fal_port_t port_id, - a_uint32_t mem_port_id); - - - HSL_LOCAL sw_error_t - isis_portvlan_member_del(a_uint32_t dev_id, fal_port_t port_id, - a_uint32_t mem_port_id); - - - HSL_LOCAL sw_error_t - isis_portvlan_member_update(a_uint32_t dev_id, fal_port_t port_id, - fal_pbmp_t mem_port_map); - - - HSL_LOCAL sw_error_t - isis_portvlan_member_get(a_uint32_t dev_id, fal_port_t port_id, - fal_pbmp_t * mem_port_map); - - - HSL_LOCAL sw_error_t - isis_port_force_default_vid_set(a_uint32_t dev_id, fal_port_t port_id, - a_bool_t enable); - - - HSL_LOCAL sw_error_t - isis_port_force_default_vid_get(a_uint32_t dev_id, fal_port_t port_id, a_bool_t * enable); - - - HSL_LOCAL sw_error_t - isis_port_force_portvlan_set(a_uint32_t dev_id, fal_port_t port_id, - a_bool_t enable); - - - HSL_LOCAL sw_error_t - isis_port_force_portvlan_get(a_uint32_t dev_id, fal_port_t port_id, a_bool_t * enable); - - - HSL_LOCAL sw_error_t - isis_nestvlan_tpid_set(a_uint32_t dev_id, a_uint32_t tpid); - - - HSL_LOCAL sw_error_t - isis_nestvlan_tpid_get(a_uint32_t dev_id, a_uint32_t * tpid); - - - HSL_LOCAL sw_error_t - isis_port_invlan_mode_set(a_uint32_t dev_id, fal_port_t port_id, - fal_pt_invlan_mode_t mode); - - - HSL_LOCAL sw_error_t - isis_port_invlan_mode_get(a_uint32_t dev_id, fal_port_t port_id, - fal_pt_invlan_mode_t * mode); - - - HSL_LOCAL sw_error_t - isis_port_tls_set(a_uint32_t dev_id, fal_port_t port_id, - a_bool_t enable); - - - HSL_LOCAL sw_error_t - isis_port_tls_get(a_uint32_t dev_id, fal_port_t port_id, - a_bool_t * enable); - - - HSL_LOCAL sw_error_t - isis_port_pri_propagation_set(a_uint32_t dev_id, fal_port_t port_id, - a_bool_t enable); - - - HSL_LOCAL sw_error_t - isis_port_pri_propagation_get(a_uint32_t dev_id, fal_port_t port_id, - a_bool_t * enable); - - - HSL_LOCAL sw_error_t - isis_port_default_svid_set(a_uint32_t dev_id, fal_port_t port_id, - a_uint32_t vid); - - - HSL_LOCAL sw_error_t - isis_port_default_svid_get(a_uint32_t dev_id, fal_port_t port_id, - a_uint32_t * vid); - - HSL_LOCAL sw_error_t - isis_port_default_cvid_set(a_uint32_t dev_id, fal_port_t port_id, - a_uint32_t vid); - - - HSL_LOCAL sw_error_t - isis_port_default_cvid_get(a_uint32_t dev_id, fal_port_t port_id, - a_uint32_t * vid); - - - HSL_LOCAL sw_error_t - isis_port_vlan_propagation_set(a_uint32_t dev_id, fal_port_t port_id, - fal_vlan_propagation_mode_t mode); - - - HSL_LOCAL sw_error_t - isis_port_vlan_propagation_get(a_uint32_t dev_id, fal_port_t port_id, - fal_vlan_propagation_mode_t * mode); - - - HSL_LOCAL sw_error_t - isis_port_vlan_trans_add(a_uint32_t dev_id, fal_port_t port_id, fal_vlan_trans_entry_t *entry); - - - HSL_LOCAL sw_error_t - isis_port_vlan_trans_del(a_uint32_t dev_id, fal_port_t port_id, fal_vlan_trans_entry_t *entry); - - - HSL_LOCAL sw_error_t - isis_port_vlan_trans_get(a_uint32_t dev_id, fal_port_t port_id, fal_vlan_trans_entry_t *entry); - - - HSL_LOCAL sw_error_t - isis_qinq_mode_set(a_uint32_t dev_id, fal_qinq_mode_t mode); - - - HSL_LOCAL sw_error_t - isis_qinq_mode_get(a_uint32_t dev_id, fal_qinq_mode_t * mode); - - - HSL_LOCAL sw_error_t - isis_port_qinq_role_set(a_uint32_t dev_id, fal_port_t port_id, fal_qinq_port_role_t role); - - - HSL_LOCAL sw_error_t - isis_port_qinq_role_get(a_uint32_t dev_id, fal_port_t port_id, fal_qinq_port_role_t * role); - - - HSL_LOCAL sw_error_t - isis_port_vlan_trans_iterate(a_uint32_t dev_id, fal_port_t port_id, - a_uint32_t * iterator, fal_vlan_trans_entry_t * entry); - - - HSL_LOCAL sw_error_t - isis_port_mac_vlan_xlt_set(a_uint32_t dev_id, fal_port_t port_id, - a_bool_t enable); - - - HSL_LOCAL sw_error_t - isis_port_mac_vlan_xlt_get(a_uint32_t dev_id, fal_port_t port_id, - a_bool_t * enable); - - HSL_LOCAL sw_error_t - isis_port_route_defv_set(a_uint32_t dev_id, fal_port_t port_id); - -#endif - -#ifdef __cplusplus -} -#endif /* __cplusplus */ -#endif /* _ISIS_PORTVLAN_H */ - diff --git a/feeds/ipq807x/qca-ssdk/src/include/hsl/isis/isis_qos.h b/feeds/ipq807x/qca-ssdk/src/include/hsl/isis/isis_qos.h deleted file mode 100755 index 58c022a91..000000000 --- a/feeds/ipq807x/qca-ssdk/src/include/hsl/isis/isis_qos.h +++ /dev/null @@ -1,157 +0,0 @@ -/* - * Copyright (c) 2012, The Linux Foundation. All rights reserved. - * Permission to use, copy, modify, and/or distribute this software for - * any purpose with or without fee is hereby granted, provided that the - * above copyright notice and this permission notice appear in all copies. - * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES - * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR - * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES - * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN - * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT - * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. - */ - - -#ifndef _ISIS_QOS_H_ -#define _ISIS_QOS_H_ - -#ifdef __cplusplus -extern "C" { -#endif /* __cplusplus */ - -#include "fal/fal_qos.h" - - sw_error_t isis_qos_init(a_uint32_t dev_id); - -#ifdef IN_QOS -#define ISIS_QOS_INIT(rv, dev_id) \ - { \ - rv = isis_qos_init(dev_id); \ - SW_RTN_ON_ERROR(rv); \ - } -#else -#define ISIS_QOS_INIT(rv, dev_id) -#endif - -#ifdef HSL_STANDALONG - - - HSL_LOCAL sw_error_t - isis_qos_queue_tx_buf_status_set(a_uint32_t dev_id, - fal_port_t port_id, a_bool_t enable); - - - HSL_LOCAL sw_error_t - isis_qos_queue_tx_buf_status_get(a_uint32_t dev_id, - fal_port_t port_id, - a_bool_t * enable); - - HSL_LOCAL sw_error_t - isis_qos_port_tx_buf_status_set(a_uint32_t dev_id, fal_port_t port_id, - a_bool_t enable); - - - HSL_LOCAL sw_error_t - isis_qos_port_tx_buf_status_get(a_uint32_t dev_id, fal_port_t port_id, - a_bool_t * enable); - - - HSL_LOCAL sw_error_t - isis_qos_queue_tx_buf_nr_set(a_uint32_t dev_id, fal_port_t port_id, - fal_queue_t queue_id, - a_uint32_t * number); - - - HSL_LOCAL sw_error_t - isis_qos_queue_tx_buf_nr_get(a_uint32_t dev_id, fal_port_t port_id, - fal_queue_t queue_id, - a_uint32_t * number); - - - HSL_LOCAL sw_error_t - isis_qos_port_tx_buf_nr_set(a_uint32_t dev_id, fal_port_t port_id, - a_uint32_t * number); - - - HSL_LOCAL sw_error_t - isis_qos_port_tx_buf_nr_get(a_uint32_t dev_id, fal_port_t port_id, - a_uint32_t * number); - - - HSL_LOCAL sw_error_t - isis_qos_port_rx_buf_nr_set(a_uint32_t dev_id, fal_port_t port_id, - a_uint32_t * number); - - - HSL_LOCAL sw_error_t - isis_qos_port_rx_buf_nr_get(a_uint32_t dev_id, fal_port_t port_id, - a_uint32_t * number); - - - HSL_LOCAL sw_error_t - isis_qos_port_mode_set(a_uint32_t dev_id, fal_port_t port_id, - fal_qos_mode_t mode, a_bool_t enable); - - - HSL_LOCAL sw_error_t - isis_qos_port_mode_get(a_uint32_t dev_id, fal_port_t port_id, - fal_qos_mode_t mode, a_bool_t * enable); - - - HSL_LOCAL sw_error_t - isis_qos_port_mode_pri_set(a_uint32_t dev_id, fal_port_t port_id, - fal_qos_mode_t mode, a_uint32_t pri); - - - HSL_LOCAL sw_error_t - isis_qos_port_mode_pri_get(a_uint32_t dev_id, fal_port_t port_id, - fal_qos_mode_t mode, a_uint32_t * pri); - - - HSL_LOCAL sw_error_t - isis_qos_port_sch_mode_set(a_uint32_t dev_id, a_uint32_t port_id, - fal_sch_mode_t mode, const a_uint32_t weight[]); - - - HSL_LOCAL sw_error_t - isis_qos_port_sch_mode_get(a_uint32_t dev_id, a_uint32_t port_id, - fal_sch_mode_t * mode, a_uint32_t weight[]); - - HSL_LOCAL sw_error_t - isis_qos_port_default_spri_set(a_uint32_t dev_id, fal_port_t port_id, - a_uint32_t spri); - - - HSL_LOCAL sw_error_t - isis_qos_port_default_spri_get(a_uint32_t dev_id, fal_port_t port_id, - a_uint32_t * spri); - - - HSL_LOCAL sw_error_t - isis_qos_port_default_cpri_set(a_uint32_t dev_id, fal_port_t port_id, - a_uint32_t cpri); - - - HSL_LOCAL sw_error_t - isis_qos_port_default_cpri_get(a_uint32_t dev_id, fal_port_t port_id, - a_uint32_t * cpri); - - - HSL_LOCAL sw_error_t - isis_qos_queue_remark_table_set(a_uint32_t dev_id, fal_port_t port_id, - fal_queue_t queue_id, a_uint32_t tbl_id, a_bool_t enable); - - - HSL_LOCAL sw_error_t - isis_qos_queue_remark_table_get(a_uint32_t dev_id, fal_port_t port_id, - fal_queue_t queue_id, a_uint32_t * tbl_id, a_bool_t * enable); - - -#endif - -#ifdef __cplusplus -} -#endif /* __cplusplus */ -#endif /* _ISIS_QOS_H_ */ - diff --git a/feeds/ipq807x/qca-ssdk/src/include/hsl/isis/isis_rate.h b/feeds/ipq807x/qca-ssdk/src/include/hsl/isis/isis_rate.h deleted file mode 100755 index 375e1fab5..000000000 --- a/feeds/ipq807x/qca-ssdk/src/include/hsl/isis/isis_rate.h +++ /dev/null @@ -1,89 +0,0 @@ -/* - * Copyright (c) 2012, The Linux Foundation. All rights reserved. - * Permission to use, copy, modify, and/or distribute this software for - * any purpose with or without fee is hereby granted, provided that the - * above copyright notice and this permission notice appear in all copies. - * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES - * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR - * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES - * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN - * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT - * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. - */ - - -#ifndef _ISIS_RATE_H_ -#define _ISIS_RATE_H_ - -#ifdef __cplusplus -extern "C" { -#endif /* __cplusplus */ - -#include "fal/fal_rate.h" - - sw_error_t isis_rate_init(a_uint32_t dev_id); - -#ifdef IN_RATE -#define ISIS_RATE_INIT(rv, dev_id) \ - { \ - rv = isis_rate_init(dev_id); \ - SW_RTN_ON_ERROR(rv); \ - } -#else -#define ISIS_RATE_INIT(rv, dev_id) -#endif - -#ifdef HSL_STANDALONG - - HSL_LOCAL sw_error_t - isis_rate_port_policer_set(a_uint32_t dev_id, fal_port_t port_id, - fal_port_policer_t * policer); - - HSL_LOCAL sw_error_t - isis_rate_port_policer_get(a_uint32_t dev_id, fal_port_t port_id, - fal_port_policer_t * policer); - - HSL_LOCAL sw_error_t - isis_rate_port_shaper_set(a_uint32_t dev_id, fal_port_t port_id, - a_bool_t enable, - fal_egress_shaper_t * shaper); - - HSL_LOCAL sw_error_t - isis_rate_port_shaper_get(a_uint32_t dev_id, fal_port_t port_id, - a_bool_t * enable, - fal_egress_shaper_t * shaper); - - HSL_LOCAL sw_error_t - isis_rate_queue_shaper_set(a_uint32_t dev_id, fal_port_t port_id, - fal_queue_t queue_id, a_bool_t enable, - fal_egress_shaper_t * shaper); - - HSL_LOCAL sw_error_t - isis_rate_queue_shaper_get(a_uint32_t dev_id, fal_port_t port_id, - fal_queue_t queue_id, a_bool_t * enable, - fal_egress_shaper_t * shaper); - - HSL_LOCAL sw_error_t - isis_rate_acl_policer_set(a_uint32_t dev_id, a_uint32_t policer_id, - fal_acl_policer_t * policer); - - HSL_LOCAL sw_error_t - isis_rate_acl_policer_get(a_uint32_t dev_id, a_uint32_t policer_id, - fal_acl_policer_t * policer); - - HSL_LOCAL sw_error_t - isis_rate_port_add_rate_byte_set(a_uint32_t dev_id, fal_port_t port_id, - a_uint32_t number); - - HSL_LOCAL sw_error_t - isis_rate_port_add_rate_byte_get(a_uint32_t dev_id, fal_port_t port_id, - a_uint32_t *number); - -#endif - -#ifdef __cplusplus -} -#endif /* __cplusplus */ -#endif /* _ISIS_RATE_H_ */ - diff --git a/feeds/ipq807x/qca-ssdk/src/include/hsl/isis/isis_reg.h b/feeds/ipq807x/qca-ssdk/src/include/hsl/isis/isis_reg.h deleted file mode 100755 index d45975b45..000000000 --- a/feeds/ipq807x/qca-ssdk/src/include/hsl/isis/isis_reg.h +++ /dev/null @@ -1,5229 +0,0 @@ -/* - * Copyright (c) 2012, The Linux Foundation. All rights reserved. - * Permission to use, copy, modify, and/or distribute this software for - * any purpose with or without fee is hereby granted, provided that the - * above copyright notice and this permission notice appear in all copies. - * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES - * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR - * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES - * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN - * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT - * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. - */ - - - -#ifndef _ISIS_REG_H_ -#define _ISIS_REG_H_ - -#ifdef __cplusplus -extern "C" { -#endif /* __cplusplus */ - -#define S16E_DEVICE_ID 0x11 -#define S17_DEVICE_ID 0x12 -#define S17_REVISION_A 0x01 - -#define MAX_ENTRY_LEN 128 - -#define HSL_RW 1 -#define HSL_RO 0 - - - /* ISIS Mask Control Register */ -#define MASK_CTL -#define MASK_CTL_ID 0 -#define MASK_CTL_OFFSET 0x0000 -#define MASK_CTL_E_LENGTH 4 -#define MASK_CTL_E_OFFSET 0 -#define MASK_CTL_NR_E 1 - -#define SOFT_RST -#define MASK_CTL_SOFT_RST_BOFFSET 31 -#define MASK_CTL_SOFT_RST_BLEN 1 -#define MASK_CTL_SOFT_RST_FLAG HSL_RW - -#define LOAD_EEPROM -#define MASK_CTL_LOAD_EEPROM_BOFFSET 16 -#define MASK_CTL_LOAD_EEPROM_BLEN 1 -#define MASK_CTL_LOAD_EEPROM_FLAG HSL_RW - -#define DEVICE_ID -#define MASK_CTL_DEVICE_ID_BOFFSET 8 -#define MASK_CTL_DEVICE_ID_BLEN 8 -#define MASK_CTL_DEVICE_ID_FLAG HSL_RO - -#define REV_ID -#define MASK_CTL_REV_ID_BOFFSET 0 -#define MASK_CTL_REV_ID_BLEN 8 -#define MASK_CTL_REV_ID_FLAG HSL_RO - - - - - /* Port0 Pad Control Register */ -#define PORT0_PAD_CTRL -#define PORT0_PAD_CTRL_ID 0 -#define PORT0_PAD_CTRL_OFFSET 0x0004 -#define PORT0_PAD_CTRL_E_LENGTH 4 -#define PORT0_PAD_CTRL_E_OFFSET 0 -#define PORT0_PAD_CTRL_NR_E 1 - -#define MAC0_RGMII_EN -#define PORT0_PAD_CTRL_MAC0_RGMII_EN_BOFFSET 26 -#define PORT0_PAD_CTRL_MAC0_RGMII_EN_BLEN 1 -#define PORT0_PAD_CTRL_MAC0_RGMII_EN_FLAG HSL_RW - -#define MAC0_RGMII_TXCLK_DELAY_EN -#define PORT0_PAD_CTRL_MAC0_RGMII_TXCLK_DELAY_EN_BOFFSET 25 -#define PORT0_PAD_CTRL_MAC0_RGMII_TXCLK_DELAY_EN_BLEN 1 -#define PORT0_PAD_CTRL_MAC0_RGMII_TXCLK_DELAY_EN_FLAG HSL_RW - -#define MAC0_RGMII_RXCLK_DELAY_EN -#define PORT0_PAD_CTRL_MAC0_RGMII_RXCLK_DELAY_EN_BOFFSET 24 -#define PORT0_PAD_CTRL_MAC0_RGMII_RXCLK_DELAY_EN_BLEN 1 -#define PORT0_PAD_CTRL_MAC0_RGMII_RXCLK_DELAY_EN_FLAG HSL_RW - -#define MAC0_RGMII_TXCLK_DELAY_SEL -#define PORT0_PAD_CTRL_MAC0_RGMII_TXCLK_DELAY_SEL_BOFFSET 22 -#define PORT0_PAD_CTRL_MAC0_RGMII_TXCLK_DELAY_SEL_BLEN 2 -#define PORT0_PAD_CTRL_MAC0_RGMII_TXCLK_DELAY_SEL_FLAG HSL_RW - -#define MAC0_RGMII_RXCLK_DELAY_SEL -#define PORT0_PAD_CTRL_MAC0_RGMII_RXCLK_DELAY_SEL_BOFFSET 20 -#define PORT0_PAD_CTRL_MAC0_RGMII_RXCLK_DELAY_SEL_BLEN 2 -#define PORT0_PAD_CTRL_MAC0_RGMII_RXCLK_DELAY_SEL_FLAG HSL_RW - -#define SGMII_CLK125M_RX_SEL -#define PORT0_PAD_CTRL_SGMII_CLK125M_RX_SEL_BOFFSET 19 -#define PORT0_PAD_CTRL_SGMII_CLK125M_RX_SEL_BLEN 1 -#define PORT0_PAD_CTRL_SGMII_CLK125M_RX_SEL_FLAG HSL_RW - -#define SGMII_CLK125M_TX_SEL -#define PORT0_PAD_CTRL_SGMII_CLK125M_TX_SEL_BOFFSET 18 -#define PORT0_PAD_CTRL_SGMII_CLK125M_TX_SEL_BLEN 1 -#define PORT0_PAD_CTRL_SGMII_CLK125M_TX_SEL_FLAG HSL_RW - -#define MAC0_PHY_GMII_EN -#define PORT0_PAD_CTRL_MAC0_PHY_GMII_EN_BOFFSET 14 -#define PORT0_PAD_CTRL_MAC0_PHY_GMII_EN_BLEN 1 -#define PORT0_PAD_CTRL_MAC0_PHY_GMII_EN_FLAG HSL_RW - -#define MAC0_PHY_GMII_TXCLK_SEL -#define PORT0_PAD_CTRL_MAC0_PHY_GMII_TXCLK_SEL_BOFFSET 13 -#define PORT0_PAD_CTRL_MAC0_PHY_GMII_TXCLK_SEL_BLEN 1 -#define PORT0_PAD_CTRL_MAC0_PHY_GMII_TXCLK_SEL_FLAG HSL_RW - -#define MAC0_PHY_GMII_RXCLK_SEL -#define PORT0_PAD_CTRL_MAC0_PHY_GMII_RXCLK_SEL_BOFFSET 12 -#define PORT0_PAD_CTRL_MAC0_PHY_GMII_RXCLK_SEL_BLEN 1 -#define PORT0_PAD_CTRL_MAC0_PHY_GMII_RXCLK_SEL_FLAG HSL_RW - -#define MAC0_PHY_MII_PIPE_RXCLK_SEL -#define PORT0_PAD_CTRL_MAC0_PHY_MII_PIPE_RXCLK_SEL_BOFFSET 11 -#define PORT0_PAD_CTRL_MAC0_PHY_MII_PIPE_RXCLK_SEL_BLEN 1 -#define PORT0_PAD_CTRL_MAC0_PHY_MII_PIPE_RXCLK_SEL_FLAG HSL_RW - -#define MAC0_PHY_MII_EN -#define PORT0_PAD_CTRL_MAC0_PHY_MII_EN_BOFFSET 10 -#define PORT0_PAD_CTRL_MAC0_PHY_MII_EN_BLEN 1 -#define PORT0_PAD_CTRL_MAC0_PHY_MII_EN_FLAG HSL_RW - -#define MAC0_PHY_MII_TXCLK_SEL -#define PORT0_PAD_CTRL_MAC0_PHY_MII_TXCLK_SEL_BOFFSET 9 -#define PORT0_PAD_CTRL_MAC0_PHY_MII_TXCLK_SEL_BLEN 1 -#define PORT0_PAD_CTRL_MAC0_PHY_MII_TXCLK_SEL_FLAG HSL_RW - -#define MAC0_PHY_MII_RXCLK_SEL -#define PORT0_PAD_CTRL_MAC0_PHY_MII_RXCLK_SEL_BOFFSET 8 -#define PORT0_PAD_CTRL_MAC0_PHY_MII_RXCLK_SEL_BLEN 1 -#define PORT0_PAD_CTRL_MAC0_PHY_MII_RXCLK_SEL_FLAG HSL_RW - -#define MAC0_SGMII_EN -#define PORT0_PAD_CTRL_MAC0_SGMII_EN_BOFFSET 7 -#define PORT0_PAD_CTRL_MAC0_SGMII_EN_BLEN 1 -#define PORT0_PAD_CTRL_MAC0_SGMII_EN_FLAG HSL_RW - -#define MAC0_MAC_GMII_EN -#define PORT0_PAD_CTRL_MAC0_MAC_GMII_EN_BOFFSET 6 -#define PORT0_PAD_CTRL_MAC0_MAC_GMII_EN_BLEN 1 -#define PORT0_PAD_CTRL_MAC0_MAC_GMII_EN_FLAG HSL_RW - -#define MAC0_MAC_GMII_TXCLK_SEL -#define PORT0_PAD_CTRL_MAC0_MAC_GMII_TXCLK_SEL_BOFFSET 5 -#define PORT0_PAD_CTRL_MAC0_MAC_GMII_TXCLK_SEL_BLEN 1 -#define PORT0_PAD_CTRL_MAC0_MAC_GMII_TXCLK_SEL_FLAG HSL_RW - -#define MAC0_MAC_GMII_RXCLK_SEL -#define PORT0_PAD_CTRL_MAC0_MAC_GMII_RXCLK_SEL_BOFFSET 4 -#define PORT0_PAD_CTRL_MAC0_MAC_GMII_RXCLK_SEL_BLEN 1 -#define PORT0_PAD_CTRL_MAC0_MAC_GMII_RXCLK_SEL_FLAG HSL_RW - -#define MAC0_MAC_MII_EN -#define PORT0_PAD_CTRL_MAC0_MAC_MII_EN_BOFFSET 2 -#define PORT0_PAD_CTRL_MAC0_MAC_MII_EN_BLEN 1 -#define PORT0_PAD_CTRL_MAC0_MAC_MII_EN_FLAG HSL_RW - -#define MAC0_MAC_MII_TXCLK_SEL -#define PORT0_PAD_CTRL_MAC0_MAC_MII_TXCLK_SEL_BOFFSET 1 -#define PORT0_PAD_CTRL_MAC0_MAC_MII_TXCLK_SEL_BLEN 1 -#define PORT0_PAD_CTRL_MAC0_MAC_MII_TXCLK_SEL_FLAG HSL_RW - -#define MAC0_MAC_MII_RXCLK_SEL -#define PORT0_PAD_CTRL_MAC0_MAC_MII_RXCLK_SEL_BOFFSET 0 -#define PORT0_PAD_CTRL_MAC0_MAC_MII_RXCLK_SEL_BLEN 1 -#define PORT0_PAD_CTRL_MAC0_MAC_MII_RXCLK_SEL_FLAG HSL_RW - - - - - /* Port5 Pad Control Register */ -#define PORT5_PAD_CTRL -#define PORT5_PAD_CTRL_ID 0 -#define PORT5_PAD_CTRL_OFFSET 0x0008 -#define PORT5_PAD_CTRL_E_LENGTH 4 -#define PORT5_PAD_CTRL_E_OFFSET 0 -#define PORT5_PAD_CTRL_NR_E 1 - -#define MAC5_RGMII_EN -#define PORT5_PAD_CTRL_MAC5_RGMII_EN_BOFFSET 26 -#define PORT5_PAD_CTRL_MAC5_RGMII_EN_BLEN 1 -#define PORT5_PAD_CTRL_MAC5_RGMII_EN_FLAG HSL_RW - -#define MAC5_RGMII_TXCLK_DELAY_EN -#define PORT5_PAD_CTRL_MAC5_RGMII_TXCLK_DELAY_EN_BOFFSET 25 -#define PORT5_PAD_CTRL_MAC5_RGMII_TXCLK_DELAY_EN_BLEN 1 -#define PORT5_PAD_CTRL_MAC5_RGMII_TXCLK_DELAY_EN_FLAG HSL_RW - -#define MAC5_RGMII_RXCLK_DELAY_EN -#define PORT5_PAD_CTRL_MAC5_RGMII_RXCLK_DELAY_EN_BOFFSET 24 -#define PORT5_PAD_CTRL_MAC5_RGMII_RXCLK_DELAY_EN_BLEN 1 -#define PORT5_PAD_CTRL_MAC5_RGMII_RXCLK_DELAY_EN_FLAG HSL_RW - -#define MAC5_RGMII_TXCLK_DELAY_SEL -#define PORT5_PAD_CTRL_MAC5_RGMII_TXCLK_DELAY_SEL_BOFFSET 22 -#define PORT5_PAD_CTRL_MAC5_RGMII_TXCLK_DELAY_SEL_BLEN 2 -#define PORT5_PAD_CTRL_MAC5_RGMII_TXCLK_DELAY_SEL_FLAG HSL_RW - -#define MAC5_RGMII_RXCLK_DELAY_SEL -#define PORT5_PAD_CTRL_MAC5_RGMII_RXCLK_DELAY_SEL_BOFFSET 20 -#define PORT5_PAD_CTRL_MAC5_RGMII_RXCLK_DELAY_SEL_BLEN 2 -#define PORT5_PAD_CTRL_MAC5_RGMII_RXCLK_DELAY_SEL_FLAG HSL_RW - -#define MAC5_PHY_MII_PIPE_RXCLK_SEL -#define PORT5_PAD_CTRL_MAC5_PHY_MII_PIPE_RXCLK_SEL_BOFFSET 11 -#define PORT5_PAD_CTRL_MAC5_PHY_MII_PIPE_RXCLK_SEL_BLEN 1 -#define PORT5_PAD_CTRL_MAC5_PHY_MII_PIPE_RXCLK_SEL_FLAG HSL_RW - -#define MAC5_PHY_MII_EN -#define PORT5_PAD_CTRL_MAC5_PHY_MII_EN_BOFFSET 10 -#define PORT5_PAD_CTRL_MAC5_PHY_MII_EN_BLEN 1 -#define PORT5_PAD_CTRL_MAC5_PHY_MII_EN_FLAG HSL_RW - -#define MAC5_PHY_MII_TXCLK_SEL -#define PORT5_PAD_CTRL_MAC5_PHY_MII_TXCLK_SEL_BOFFSET 9 -#define PORT5_PAD_CTRL_MAC5_PHY_MII_TXCLK_SEL_BLEN 1 -#define PORT5_PAD_CTRL_MAC5_PHY_MII_TXCLK_SEL_FLAG HSL_RW - -#define MAC5_PHY_MII_RXCLK_SEL -#define PORT5_PAD_CTRL_MAC5_PHY_MII_RXCLK_SEL_BOFFSET 8 -#define PORT5_PAD_CTRL_MAC5_PHY_MII_RXCLK_SEL_BLEN 1 -#define PORT5_PAD_CTRL_MAC5_PHY_MII_RXCLK_SEL_FLAG HSL_RW - -#define MAC5_MAC_MII_EN -#define PORT5_PAD_CTRL_MAC5_MAC_MII_EN_BOFFSET 2 -#define PORT5_PAD_CTRL_MAC5_MAC_MII_EN_BLEN 1 -#define PORT5_PAD_CTRL_MAC5_MAC_MII_EN_FLAG HSL_RW - -#define MAC5_MAC_MII_TXCLK_SEL -#define PORT5_PAD_CTRL_MAC0_MAC_MII_TXCLK_SEL_BOFFSET 1 -#define PORT5_PAD_CTRL_MAC0_MAC_MII_TXCLK_SEL_BLEN 1 -#define PORT5_PAD_CTRL_MAC0_MAC_MII_TXCLK_SEL_FLAG HSL_RW - -#define MAC5_MAC_MII_RXCLK_SEL -#define PORT5_PAD_CTRL_MAC5_MAC_MII_RXCLK_SEL_BOFFSET 0 -#define PORT5_PAD_CTRL_MAC5_MAC_MII_RXCLK_SEL_BLEN 1 -#define PORT5_PAD_CTRL_MAC5_MAC_MII_RXCLK_SEL_FLAG HSL_RW - - - - - /* Port6 Pad Control Register */ -#define PORT6_PAD_CTRL -#define PORT6_PAD_CTRL_ID 0 -#define PORT6_PAD_CTRL_OFFSET 0x000c -#define PORT6_PAD_CTRL_E_LENGTH 4 -#define PORT6_PAD_CTRL_E_OFFSET 0 -#define PORT6_PAD_CTRL_NR_E 1 - -#define MAC6_RGMII_EN -#define PORT6_PAD_CTRL_MAC6_RGMII_EN_BOFFSET 26 -#define PORT6_PAD_CTRL_MAC6_RGMII_EN_BLEN 1 -#define PORT6_PAD_CTRL_MAC6_RGMII_EN_FLAG HSL_RW - -#define MAC6_RGMII_TXCLK_DELAY_EN -#define PORT6_PAD_CTRL_MAC6_RGMII_TXCLK_DELAY_EN_BOFFSET 25 -#define PORT6_PAD_CTRL_MAC6_RGMII_TXCLK_DELAY_EN_BLEN 1 -#define PORT6_PAD_CTRL_MAC6_RGMII_TXCLK_DELAY_EN_FLAG HSL_RW - -#define MAC6_RGMII_RXCLK_DELAY_EN -#define PORT6_PAD_CTRL_MAC6_RGMII_RXCLK_DELAY_EN_BOFFSET 24 -#define PORT6_PAD_CTRL_MAC6_RGMII_RXCLK_DELAY_EN_BLEN 1 -#define PORT6_PAD_CTRL_MAC6_RGMII_RXCLK_DELAY_EN_FLAG HSL_RW - -#define MAC6_RGMII_TXCLK_DELAY_SEL -#define PORT6_PAD_CTRL_MAC6_RGMII_TXCLK_DELAY_SEL_BOFFSET 22 -#define PORT6_PAD_CTRL_MAC6_RGMII_TXCLK_DELAY_SEL_BLEN 2 -#define PORT6_PAD_CTRL_MAC6_RGMII_TXCLK_DELAY_SEL_FLAG HSL_RW - -#define MAC6_RGMII_RXCLK_DELAY_SEL -#define PORT6_PAD_CTRL_MAC6_RGMII_RXCLK_DELAY_SEL_BOFFSET 20 -#define PORT6_PAD_CTRL_MAC6_RGMII_RXCLK_DELAY_SEL_BLEN 2 -#define PORT6_PAD_CTRL_MAC6_RGMII_RXCLK_DELAY_SEL_FLAG HSL_RW - -#define PHY4_MII_EN -#define PORT6_PAD_CTRL_PHY4_MII_EN_BOFFSET 18 -#define PORT6_PAD_CTRL_PHY4_MII_EN_BLEN 1 -#define PORT6_PAD_CTRL_PHY4_MII_EN_FLAG HSL_RW - -#define PHY4_RGMII_EN -#define PORT6_PAD_CTRL_PHY4_RGMII_EN_BOFFSET 17 -#define PORT6_PAD_CTRL_PHY4_RGMII_EN_BLEN 1 -#define PORT6_PAD_CTRL_PHY4_RGMII_EN_FLAG HSL_RW - -#define PHY4_GMII_EN -#define PORT6_PAD_CTRL_PHY4_GMII_EN_BOFFSET 16 -#define PORT6_PAD_CTRL_PHY4_GMII_EN_BLEN 1 -#define PORT6_PAD_CTRL_PHY4_GMII_EN_FLAG HSL_RW - -#define MAC6_PHY_GMII_EN -#define PORT6_PAD_CTRL_MAC6_PHY_GMII_EN_BOFFSET 14 -#define PORT6_PAD_CTRL_MAC6_PHY_GMII_EN_BLEN 1 -#define PORT6_PAD_CTRL_MAC6_PHY_GMII_EN_FLAG HSL_RW - -#define MAC6_PHY_GMII_TXCLK_SEL -#define PORT6_PAD_CTRL_MAC6_PHY_GMII_TXCLK_SEL_BOFFSET 13 -#define PORT6_PAD_CTRL_MAC6_PHY_GMII_TXCLK_SEL_BLEN 1 -#define PORT6_PAD_CTRL_MAC6_PHY_GMII_TXCLK_SEL_FLAG HSL_RW - -#define MAC6_PHY_GMII_RXCLK_SEL -#define PORT6_PAD_CTRL_MAC6_PHY_GMII_RXCLK_SEL_BOFFSET 12 -#define PORT6_PAD_CTRL_MAC6_PHY_GMII_RXCLK_SEL_BLEN 1 -#define PORT6_PAD_CTRL_MAC6_PHY_GMII_RXCLK_SEL_FLAG HSL_RW - -#define MAC6_PHY_MII_PIPE_RXCLK_SEL -#define PORT6_PAD_CTRL_MAC6_PHY_MII_PIPE_RXCLK_SEL_BOFFSET 11 -#define PORT6_PAD_CTRL_MAC6_PHY_MII_PIPE_RXCLK_SEL_BLEN 1 -#define PORT6_PAD_CTRL_MAC6_PHY_MII_PIPE_RXCLK_SEL_FLAG HSL_RW - -#define MAC6_PHY_MII_EN -#define PORT6_PAD_CTRL_MAC6_PHY_MII_EN_BOFFSET 10 -#define PORT6_PAD_CTRL_MAC6_PHY_MII_EN_BLEN 1 -#define PORT6_PAD_CTRL_MAC6_PHY_MII_EN_FLAG HSL_RW - -#define MAC6_PHY_MII_TXCLK_SEL -#define PORT6_PAD_CTRL_MAC6_PHY_MII_TXCLK_SEL_BOFFSET 9 -#define PORT6_PAD_CTRL_MAC6_PHY_MII_TXCLK_SEL_BLEN 1 -#define PORT6_PAD_CTRL_MAC6_PHY_MII_TXCLK_SEL_FLAG HSL_RW - -#define MAC6_PHY_MII_RXCLK_SEL -#define PORT6_PAD_CTRL_MAC6_PHY_MII_RXCLK_SEL_BOFFSET 8 -#define PORT6_PAD_CTRL_MAC6_PHY_MII_RXCLK_SEL_BLEN 1 -#define PORT6_PAD_CTRL_MAC6_PHY_MII_RXCLK_SEL_FLAG HSL_RW - -#define MAC6_SGMII_EN -#define PORT6_PAD_CTRL_MAC6_SGMII_EN_BOFFSET 7 -#define PORT6_PAD_CTRL_MAC6_SGMII_EN_BLEN 1 -#define PORT6_PAD_CTRL_MAC6_SGMII_EN_FLAG HSL_RW - -#define MAC6_MAC_GMII_EN -#define PORT6_PAD_CTRL_MAC6_MAC_GMII_EN_BOFFSET 6 -#define PORT6_PAD_CTRL_MAC6_MAC_GMII_EN_BLEN 1 -#define PORT6_PAD_CTRL_MAC6_MAC_GMII_EN_FLAG HSL_RW - -#define MAC6_MAC_GMII_TXCLK_SEL -#define PORT6_PAD_CTRL_MAC6_MAC_GMII_TXCLK_SEL_BOFFSET 5 -#define PORT6_PAD_CTRL_MAC6_MAC_GMII_TXCLK_SEL_BLEN 1 -#define PORT6_PAD_CTRL_MAC6_MAC_GMII_TXCLK_SEL_FLAG HSL_RW - -#define MAC6_MAC_GMII_RXCLK_SEL -#define PORT6_PAD_CTRL_MAC6_MAC_GMII_RXCLK_SEL_BOFFSET 4 -#define PORT6_PAD_CTRL_MAC6_MAC_GMII_RXCLK_SEL_BLEN 1 -#define PORT6_PAD_CTRL_MAC6_MAC_GMII_RXCLK_SEL_FLAG HSL_RW - -#define MAC6_MAC_MII_EN -#define PORT6_PAD_CTRL_MAC6_MAC_MII_EN_BOFFSET 2 -#define PORT6_PAD_CTRL_MAC6_MAC_MII_EN_BLEN 1 -#define PORT6_PAD_CTRL_MAC6_MAC_MII_EN_FLAG HSL_RW - -#define MAC6_MAC_MII_TXCLK_SEL -#define PORT6_PAD_CTRL_MAC6_MAC_MII_TXCLK_SEL_BOFFSET 1 -#define PORT6_PAD_CTRL_MAC6_MAC_MII_TXCLK_SEL_BLEN 1 -#define PORT6_PAD_CTRL_MAC6_MAC_MII_TXCLK_SEL_FLAG HSL_RW - -#define MAC6_MAC_MII_RXCLK_SEL -#define PORT6_PAD_CTRL_MAC6_MAC_MII_RXCLK_SEL_BOFFSET 0 -#define PORT6_PAD_CTRL_MAC6_MAC_MII_RXCLK_SEL_BLEN 1 -#define PORT6_PAD_CTRL_MAC6_MAC_MII_RXCLK_SEL_FLAG HSL_RW - - - - - /* SGMII Control Register */ -#define SGMII_CTRL -#define SGMII_CTRL_ID 0 -#define SGMII_CTRL_OFFSET 0x00e0 -#define SGMII_CTRL_E_LENGTH 4 -#define SGMII_CTRL_E_OFFSET 0 -#define SGMII_CTRL_NR_E 1 - -#define FULL_25M -#define SGMII_CTRL_FULL_25M_BOFFSET 31 -#define SGMII_CTRL_FULL_25M_BLEN 1 -#define SGMII_CTRL_FULL_25M_FLAG HSL_RW - -#define HALF_25M -#define SGMII_CTRL_HALF_25M_BOFFSET 30 -#define SGMII_CTRL_HALF_25M_BLEN 1 -#define SGMII_CTRL_HALF_25M_FLAG HSL_RW - -#define REMOTE_25M -#define SGMII_CTRL_REMOTE_25M_BOFFSET 28 -#define SGMII_CTRL_REMOTE_25M_BLEN 2 -#define SGMII_CTRL_REMOTE_25M_FLAG HSL_RW - -#define NEXT_PAGE_25M -#define SGMII_CTRL_NEXT_PAGE_25M_BOFFSET 27 -#define SGMII_CTRL_NEXT_PAGE_25M_BLEN 1 -#define SGMII_CTRL_NEXT_PAGE_25M_FLAG HSL_RW - -#define PAUSE_25M -#define SGMII_CTRL_PAUSE_25M_BOFFSET 26 -#define SGMII_CTRL_PAUSE_25M_BLEN 1 -#define SGMII_CTRL_PAUSE_25M_FLAG HSL_RW - -#define ASYM_PAUSE_25M -#define SGMII_CTRL_ASYM_PAUSE_25M_BOFFSET 25 -#define SGMII_CTRL_ASYM_PAUSE_25M_BLEN 1 -#define SGMII_CTRL_ASYM_PAUSE_25M_FLAG HSL_RW - -#define PAUSE_SG_25M -#define SGMII_CTRL_PAUSE_SG_25M_BOFFSET 24 -#define SGMII_CTRL_PAUSE_SG_25M_BLEN 1 -#define SGMII_CTRL_PAUSE_SG_25M_FLAG HSL_RW - -#define PAUSE_SG_25M -#define SGMII_CTRL_PAUSE_SG_25M_BOFFSET 24 -#define SGMII_CTRL_PAUSE_SG_25M_BLEN 1 -#define SGMII_CTRL_PAUSE_SG_25M_FLAG HSL_RW - -#define MODE_CTRL_25M -#define SGMII_CTRL_MODE_CTRL_25M_BOFFSET 22 -#define SGMII_CTRL_MODE_CTRL_25M_BLEN 2 -#define SGMII_CTRL_MODE_CTRL_25M_FLAG HSL_RW - -#define MR_LOOPBACK -#define SGMII_CTRL_MR_LOOPBACK_BOFFSET 21 -#define SGMII_CTRL_MR_LOOPBACK_BLEN 1 -#define SGMII_CTRL_MR_LOOPBACK_FLAG HSL_RW - -#define MR_REG4_25M -#define SGMII_CTRL_MR_REG4_25M_BOFFSET 20 -#define SGMII_CTRL_MR_REG4_25M_BLEN 1 -#define SGMII_CTRL_MR_REG4_25M_FLAG HSL_RW - -#define AUTO_LPI_25M -#define SGMII_CTRL_AUTO_LPI_25M_BOFFSET 19 -#define SGMII_CTRL_AUTO_LPI_25M_BLEN 1 -#define SGMII_CTRL_AUTO_LPI_25M_FLAG HSL_RW - -#define PRBS_EN -#define SGMII_CTRL_PRBS_EN_BOFFSET 18 -#define SGMII_CTRL_PRBS_EN_BLEN 1 -#define SGMII_CTRL_PRBS_EN_FLAG HSL_RW - -#define SGMII_TH_LOS1 -#define SGMII_CTRL_SGMII_TH_LOS1_BOFFSET 17 -#define SGMII_CTRL_SGMII_TH_LOS1_BLEN 1 -#define SGMII_CTRL_SGMII_TH_LOS1_FLAG HSL_RW - -#define DIS_AUTO_LPI_25M -#define SGMII_CTRL_DIS_AUTO_LPI_25M_BOFFSET 16 -#define SGMII_CTRL_DIS_AUTO_LPI_25M_BLEN 1 -#define SGMII_CTRL_DIS_AUTO_LPI_25M_FLAG HSL_RW - -#define SGMII_TH_LOS0 -#define SGMII_CTRL_SGMII_TH_LOS0_BOFFSET 15 -#define SGMII_CTRL_SGMII_TH_LOS0_BLEN 1 -#define SGMII_CTRL_SGMII_TH_LOS0_FLAG HSL_RW - -#define SGMII_CDR_BW -#define SGMII_CTRL_SGMII_CDR_BW_BOFFSET 13 -#define SGMII_CTRL_SGMII_CDR_BW_BLEN 2 -#define SGMII_CTRL_SGMII_CDR_BW_FLAG HSL_RW - -#define SGMII_TXDR_CTRL -#define SGMII_CTRL_SGMII_TXDR_CTRL_BOFFSET 10 -#define SGMII_CTRL_SGMII_TXDR_CTRL_BLEN 3 -#define SGMII_CTRL_SGMII_TXDR_CTRL_FLAG HSL_RW - -#define SGMII_FIBER_MODE -#define SGMII_CTRL_SGMII_FIBER_MODE_BOFFSET 8 -#define SGMII_CTRL_SGMII_FIBER_MODE_BLEN 2 -#define SGMII_CTRL_SGMII_FIBER_MODE_FLAG HSL_RW - -#define SGMII_SEL_125M -#define SGMII_CTRL_SGMII_SEL_125M_BOFFSET 7 -#define SGMII_CTRL_SGMII_SEL_125M_BLEN 1 -#define SGMII_CTRL_SGMII_SEL_125M_FLAG HSL_RW - -#define SGMII_PLL_BW -#define SGMII_CTRL_SGMII_PLL_BW_BOFFSET 6 -#define SGMII_CTRL_SGMII_PLL_BW_BLEN 1 -#define SGMII_CTRL_SGMII_PLL_BW_FLAG HSL_RW - -#define SGMII_HALFTX -#define SGMII_CTRL_SGMII_HALFTX_BOFFSET 5 -#define SGMII_CTRL_SGMII_HALFTX_BLEN 1 -#define SGMII_CTRL_SGMII_HALFTX_FLAG HSL_RW - -#define SGMII_EN_SD -#define SGMII_CTRL_SGMII_EN_SD_BOFFSET 4 -#define SGMII_CTRL_SGMII_EN_SD_BLEN 1 -#define SGMII_CTRL_SGMII_EN_SD_FLAG HSL_RW - -#define SGMII_EN_TX -#define SGMII_CTRL_SGMII_EN_TX_BOFFSET 3 -#define SGMII_CTRL_SGMII_EN_TX_BLEN 1 -#define SGMII_CTRL_SGMII_EN_TX_FLAG HSL_RW - -#define SGMII_EN_RX -#define SGMII_CTRL_SGMII_EN_RX_BOFFSET 2 -#define SGMII_CTRL_SGMII_EN_RX_BLEN 1 -#define SGMII_CTRL_SGMII_EN_RX_FLAG HSL_RW - -#define SGMII_EN_PLL -#define SGMII_CTRL_SGMII_EN_PLL_BOFFSET 1 -#define SGMII_CTRL_SGMII_EN_PLL_BLEN 1 -#define SGMII_CTRL_SGMII_EN_PLL_FLAG HSL_RW - -#define SGMII_EN_LCKDT -#define SGMII_CTRL_SGMII_EN_LCKDT_BOFFSET 0 -#define SGMII_CTRL_SGMII_EN_LCKDT_BLEN 1 -#define SGMII_CTRL_SGMII_EN_LCKDT_FLAG HSL_RW - - - - - /* Power On Strip Register */ -#define POWER_STRIP -#define POWER_STRIP_ID 0 -#define POWER_STRIP_OFFSET 0x0010 -#define POWER_STRIP_E_LENGTH 4 -#define POWER_STRIP_E_OFFSET 0 -#define POWER_STRIP_NR_E 1 - -#define POWER_ON_SEL -#define POWER_STRIP_POWER_ON_SEL_BOFFSET 31 -#define POWER_STRIP_POWER_ON_SEL_BLEN 1 -#define POWER_STRIP_POWER_ON_SEL_FLAG HSL_RW - -#define PKG128_EN -#define POWER_STRIP_PKG128_EN_BOFFSET 30 -#define POWER_STRIP_PKG128_EN_BLEN 1 -#define POWER_STRIP_PKG128_EN_FLAG HSL_RW - -#define PKG128_EN_LED -#define POWER_STRIP_PKG128_EN_LED_BOFFSET 29 -#define POWER_STRIP_PKG128_EN_LED_BLEN 1 -#define POWER_STRIP_PKG128_EN_LED_FLAG HSL_RW - -#define S16_MODE -#define POWER_STRIP_S16_MODE_BOFFSET 28 -#define POWER_STRIP_S16_MODE_BLEN 1 -#define POWER_STRIP_S16_MODE_FLAG HSL_RW - -#define INPUT_MODE -#define POWER_STRIP_INPUT_MODE_BOFFSET 27 -#define POWER_STRIP_INPUT_MODE_BLEN 1 -#define POWER_STRIP_INPUT_MODE_FLAG HSL_RW - -#define SGMII_POWER_ON_SEL -#define POWER_STRIP_SGMII_POWER_ON_SEL_BOFFSET 26 -#define POWER_STRIP_SGMII_POWER_ON_SEL_BLEN 1 -#define POWER_STRIP_SGMII_POWER_ON_SEL_FLAG HSL_RW - -#define SPI_EN -#define POWER_STRIP_SPI_EN_BOFFSET 25 -#define POWER_STRIP_SPI_EN_BLEN 1 -#define POWER_STRIP_SPI_EN_FLAG HSL_RW - -#define LED_OPEN_EN -#define POWER_STRIP_LED_OPEN_EN_BOFFSET 24 -#define POWER_STRIP_LED_OPEN_EN_BLEN 1 -#define POWER_STRIP_LED_OPEN_EN_FLAG HSL_RW - -#define SGMII_RXIMP_50_70 -#define POWER_STRIP_SGMII_RXIMP_50_70_BOFFSET 23 -#define POWER_STRIP_SGMII_RXIMP_50_70_BLEN 1 -#define POWER_STRIP_SGMII_RXIMP_50_70_FLAG HSL_RW - -#define SGMII_TXIMP_50_70 -#define POWER_STRIP_SGMII_TXIMP_50_70_BOFFSET 22 -#define POWER_STRIP_SGMII_TXIMP_50_70_BLEN 1 -#define POWER_STRIP_SGMII_TXIMP_50_70_FLAG HSL_RW - -#define SGMII_SIGNAL_DETECT -#define POWER_STRIP_SGMII_SIGNAL_DETECT_BOFFSET 21 -#define POWER_STRIP_SGMII_SIGNAL_DETECT_BLEN 1 -#define POWER_STRIP_SGMII_SIGNAL_DETECT_FLAG HSL_RW - -#define LPW_EXIT -#define POWER_STRIP_LPW_EXIT_BOFFSET 20 -#define POWER_STRIP_LPW_EXIT_BLEN 1 -#define POWER_STRIP_LPW_EXIT_FLAG HSL_RW - -#define MAN_EN -#define POWER_STRIP_MAN_EN_BOFFSET 18 -#define POWER_STRIP_MAN_EN_BLEN 1 -#define POWER_STRIP_MAN_EN_FLAG HSL_RW - -#define HIB_EN -#define POWER_STRIP_HIB_EN_BOFFSET 17 -#define POWER_STRIP_HIB_EN_BLEN 1 -#define POWER_STRIP_HIB_EN_FLAG HSL_RW - -#define POWER_DOWN_HW -#define POWER_STRIP_POWER_DOWN_HW_BOFFSET 16 -#define POWER_STRIP_POWER_DOWN_HW_BLEN 1 -#define POWER_STRIP_POWER_DOWN_HW_FLAG HSL_RW - -#define BIST_BYPASS_CEL -#define POWER_STRIP_BIST_BYPASS_CEL_BOFFSET 15 -#define POWER_STRIP_BIST_BYPASS_CEL_BLEN 1 -#define POWER_STRIP_BIST_BYPASS_CEL_FLAG HSL_RW - -#define BIST_BYPASS_CSR -#define POWER_STRIP_BIST_BYPASS_CSR_BOFFSET 14 -#define POWER_STRIP_BIST_BYPASS_CSR_BLEN 1 -#define POWER_STRIP_BIST_BYPASS_CSR_FLAG HSL_RW - -#define HIB_PULSE_HW -#define POWER_STRIP_HIB_PULSE_HW_BOFFSET 12 -#define POWER_STRIP_HIB_PULSE_HW_BLEN 1 -#define POWER_STRIP_HIB_PULSE_HW_FLAG HSL_RW - -#define GATE_25M_EN -#define POWER_STRIP_GATE_25M_EN_BOFFSET 10 -#define POWER_STRIP_GATE_25M_EN_BLEN 1 -#define POWER_STRIP_GATE_25M_EN_FLAG HSL_RW - -#define SEL_ANA_RST -#define POWER_STRIP_SEL_ANA_RST_BOFFSET 9 -#define POWER_STRIP_SEL_ANA_RST_BLEN 1 -#define POWER_STRIP_SEL_ANA_RST_FLAG HSL_RW - -#define SERDES_EN -#define POWER_STRIP_SERDES_EN_BOFFSET 8 -#define POWER_STRIP_SERDES_EN_BLEN 1 -#define POWER_STRIP_SERDES_EN_FLAG HSL_RW - -#define SERDES_AN_EN -#define POWER_STRIP_SERDES_AN_EN_BOFFSET 7 -#define POWER_STRIP_SERDES_AN_EN_BLEN 1 -#define POWER_STRIP_SERDES_AN_EN_FLAG HSL_RW - -#define RTL_MODE -#define POWER_STRIP_RTL_MODE_BOFFSET 5 -#define POWER_STRIP_RTL_MODE_BLEN 1 -#define POWER_STRIP_RTL_MODE_FLAG HSL_RW - -#define PAD_CTRL_FOR25M -#define POWER_STRIP_PAD_CTRL_FOR25M_BOFFSET 3 -#define POWER_STRIP_PAD_CTRL_FOR25M_BLEN 2 -#define POWER_STRIP_PAD_CTRL_FOR25M_FLAG HSL_RW - -#define PAD_CTRL -#define POWER_STRIP_PAD_CTRL_BOFFSET 0 -#define POWER_STRIP_PAD_CTRL_BLEN 2 -#define POWER_STRIP_PAD_CTRL_FLAG HSL_RW - - - - - /* Global Interrupt Status Register1 */ -#define GBL_INT_STATUS1 -#define GBL_INT_STATUS1_ID 1 -#define GBL_INT_STATUS1_OFFSET 0x0024 -#define GBL_INT_STATUS1_E_LENGTH 4 -#define GBL_INT_STATUS1_E_OFFSET 0 -#define GBL_INT_STATUS1_NR_E 1 - -#define PHY_INT_S -#define GBL_INT_STATUS1_PHY_INT_S_BOFFSET 15 -#define GBL_INT_STATUS1_PHY_INT_S_BLEN 1 -#define GBL_INT_STATUS1_PHY_INT_S_FLAG HSL_RO - - - - - /* Global Interrupt Mask Register1 */ -#define GBL_INT_MASK1 -#define GBL_INT_MASK1_ID 1 -#define GBL_INT_MASK1_OFFSET 0x002c -#define GBL_INT_MASK1_E_LENGTH 4 -#define GBL_INT_MASK1_E_OFFSET 0 -#define GBL_INT_MASK1_NR_E 1 - -#define PHY_INT_M -#define GBL_INT_MASK1_PHY_INT_M_BOFFSET 15 -#define GBL_INT_MASK1_PHY_INT_M_BLEN 1 -#define GBL_INT_MASK1_PHY_INT_M_FLAG HSL_RO - - - - - /* Module Enable Register */ -#define MOD_ENABLE -#define MOD_ENABLE_OFFSET 0x0030 -#define MOD_ENABLE_E_LENGTH 4 -#define MOD_ENABLE_E_OFFSET 0 -#define MOD_ENABLE_NR_E 1 - -#define L3_EN -#define MOD_ENABLE_L3_EN_BOFFSET 2 -#define MOD_ENABLE_L3_EN_BLEN 1 -#define MOD_ENABLE_L3_EN_FLAG HSL_RW - -#define ACL_EN -#define MOD_ENABLE_ACL_EN_BOFFSET 1 -#define MOD_ENABLE_ACL_EN_BLEN 1 -#define MOD_ENABLE_ACL_EN_FLAG HSL_RW - -#define MIB_EN -#define MOD_ENABLE_MIB_EN_BOFFSET 0 -#define MOD_ENABLE_MIB_EN_BLEN 1 -#define MOD_ENABLE_MIB_EN_FLAG HSL_RW - - - - - /* MIB Function Register */ -#define MIB_FUNC -#define MIB_FUNC_OFFSET 0x0034 -#define MIB_FUNC_E_LENGTH 4 -#define MIB_FUNC_E_OFFSET 0 -#define MIB_FUNC_NR_E 1 - -#define MIB_FUN -#define MIB_FUNC_MIB_FUN_BOFFSET 24 -#define MIB_FUNC_MIB_FUN_BLEN 3 -#define MIB_FUNC_MIB_FUN_FLAG HSL_RW - -#define MIB_BUSY -#define MIB_FUNC_MIB_BUSY_BOFFSET 17 -#define MIB_FUNC_MIB_BUSY_BLEN 1 -#define MIB_FUNC_MIB_BUSY_FLAG HSL_RW - -#define MIB_AT_HALF_EN -#define MIB_FUNC_MIB_AT_HALF_EN_BOFFSET 16 -#define MIB_FUNC_MIB_AT_HALF_EN_BLEN 1 -#define MIB_FUNC_MIB_AT_HALF_EN_FLAG HSL_RW - -#define MIB_TIMER -#define MIB_FUNC_MIB_TIMER_BOFFSET 0 -#define MIB_FUNC_MIB_TIMER_BLEN 16 -#define MIB_FUNC_MIB_TIMER_FLAG HSL_RW - - - - - /* Service tag Register */ -#define SERVICE_TAG -#define SERVICE_TAG_OFFSET 0x0048 -#define SERVICE_TAG_E_LENGTH 4 -#define SERVICE_TAG_E_OFFSET 0 -#define SERVICE_TAG_NR_E 1 - -#define STAG_MODE -#define SERVICE_TAG_STAG_MODE_BOFFSET 17 -#define SERVICE_TAG_STAG_MODE_BLEN 1 -#define SERVICE_TAG_STAG_MODE_FLAG HSL_RW - -#define TAG_VALUE -#define SERVICE_TAG_TAG_VALUE_BOFFSET 0 -#define SERVICE_TAG_TAG_VALUE_BLEN 16 -#define SERVICE_TAG_TAG_VALUE_FLAG HSL_RW - - - - - /* Global MAC Address Register */ -#define GLOBAL_MAC_ADDR0 -#define GLOBAL_MAC_ADDR0_OFFSET 0x0060 -#define GLOBAL_MAC_ADDR0_E_LENGTH 4 -#define GLOBAL_MAC_ADDR0_E_OFFSET 0 -#define GLOBAL_MAC_ADDR0_NR_E 1 - -#define GLB_BYTE4 -#define GLOBAL_MAC_ADDR0_GLB_BYTE4_BOFFSET 8 -#define GLOBAL_MAC_ADDR0_GLB_BYTE4_BLEN 8 -#define GLOBAL_MAC_ADDR0_GLB_BYTE4_FLAG HSL_RW - -#define GLB_BYTE5 -#define GLOBAL_MAC_ADDR0_GLB_BYTE5_BOFFSET 0 -#define GLOBAL_MAC_ADDR0_GLB_BYTE5_BLEN 8 -#define GLOBAL_MAC_ADDR0_GLB_BYTE5_FLAG HSL_RW - -#define GLOBAL_MAC_ADDR1 -#define GLOBAL_MAC_ADDR1_ID 4 -#define GLOBAL_MAC_ADDR1_OFFSET 0x0064 -#define GLOBAL_MAC_ADDR1_E_LENGTH 4 -#define GLOBAL_MAC_ADDR1_E_OFFSET 0 -#define GLOBAL_MAC_ADDR1_NR_E 1 - -#define GLB_BYTE0 -#define GLOBAL_MAC_ADDR1_GLB_BYTE0_BOFFSET 24 -#define GLOBAL_MAC_ADDR1_GLB_BYTE0_BLEN 8 -#define GLOBAL_MAC_ADDR1_GLB_BYTE0_FLAG HSL_RW - -#define GLB_BYTE1 -#define GLOBAL_MAC_ADDR1_GLB_BYTE1_BOFFSET 16 -#define GLOBAL_MAC_ADDR1_GLB_BYTE1_BLEN 8 -#define GLOBAL_MAC_ADDR1_GLB_BYTE1_FLAG HSL_RW - -#define GLB_BYTE2 -#define GLOBAL_MAC_ADDR1_GLB_BYTE2_BOFFSET 8 -#define GLOBAL_MAC_ADDR1_GLB_BYTE2_BLEN 8 -#define GLOBAL_MAC_ADDR1_GLB_BYTE2_FLAG HSL_RW - -#define GLB_BYTE3 -#define GLOBAL_MAC_ADDR1_GLB_BYTE3_BOFFSET 0 -#define GLOBAL_MAC_ADDR1_GLB_BYTE3_BLEN 8 -#define GLOBAL_MAC_ADDR1_GLB_BYTE3_FLAG HSL_RW - - - - - /* Max Size Register */ -#define MAX_SIZE -#define MAX_SIZE_OFFSET 0x0078 -#define MAX_SIZE_E_LENGTH 4 -#define MAX_SIZE_E_OFFSET 0 -#define MAX_SIZE_NR_E 1 - -#define MAX_FRAME_SIZE -#define MAX_SIZE_MAX_FRAME_SIZE_BOFFSET 0 -#define MAX_SIZE_MAX_FRAME_SIZE_BLEN 14 -#define MAX_SIZE_MAX_FRAME_SIZE_FLAG HSL_RW - - - - - /* Flow Control Register */ -#define FLOW_CTL0 "fctl" -#define FLOW_CTL0_ID 6 -#define FLOW_CTL0_OFFSET 0x0034 -#define FLOW_CTL0_E_LENGTH 4 -#define FLOW_CTL0_E_OFFSET 0 -#define FLOW_CTL0_NR_E 1 - -#define TEST_PAUSE "fctl_tps" -#define FLOW_CTL0_TEST_PAUSE_BOFFSET 31 -#define FLOW_CTL0_TEST_PAUSE_BLEN 1 -#define FLOW_CTL0_TEST_PAUSE_FLAG HSL_RW - - -#define GOL_PAUSE_ON_THRES "fctl_gont" -#define FLOW_CTL0_GOL_PAUSE_ON_THRES_BOFFSET 16 -#define FLOW_CTL0_GOL_PAUSE_ON_THRES_BLEN 8 -#define FLOW_CTL0_GOL_PAUSE_ON_THRES_FLAG HSL_RW - -#define GOL_PAUSE_OFF_THRES "fctl_gofft" -#define FLOW_CTL0_GOL_PAUSE_OFF_THRES_BOFFSET 0 -#define FLOW_CTL0_GOL_PAUSE_OFF_THRES_BLEN 8 -#define FLOW_CTL0_GOL_PAUSE_OFF_THRES_FLAG HSL_RW - - - - - /* Flow Control1 Register */ -#define FLOW_CTL1 "fctl1" -#define FLOW_CTL1_ID 6 -#define FLOW_CTL1_OFFSET 0x0038 -#define FLOW_CTL1_E_LENGTH 4 -#define FLOW_CTL1_E_OFFSET 0 -#define FLOW_CTL1_NR_E 1 - -#define PORT_PAUSE_ON_THRES "fctl1_pont" -#define FLOW_CTL1_PORT_PAUSE_ON_THRES_BOFFSET 16 -#define FLOW_CTL1_PORT_PAUSE_ON_THRES_BLEN 8 -#define FLOW_CTL1_PORT_PAUSE_ON_THRES_FLAG HSL_RW - -#define PORT_PAUSE_OFF_THRES "fctl1_pofft" -#define FLOW_CTL1_PORT_PAUSE_OFF_THRES_BOFFSET 0 -#define FLOW_CTL1_PORT_PAUSE_OFF_THRES_BLEN 8 -#define FLOW_CTL1_PORT_PAUSE_OFF_THRES_FLAG HSL_RW - - - - - /* Port Status Register */ -#define PORT_STATUS -#define PORT_STATUS_OFFSET 0x007c -#define PORT_STATUS_E_LENGTH 4 -#define PORT_STATUS_E_OFFSET 0x0004 -#define PORT_STATUS_NR_E 7 - -#define FLOW_LINK_EN -#define PORT_STATUS_FLOW_LINK_EN_BOFFSET 12 -#define PORT_STATUS_FLOW_LINK_EN_BLEN 1 -#define PORT_STATUS_FLOW_LINK_EN_FLAG HSL_RW - -#define AUTO_RX_FLOW -#define PORT_STATUS_AUTO_RX_FLOW_BOFFSET 11 -#define PORT_STATUS_AUTO_RX_FLOW_BLEN 1 -#define PORT_STATUS_AUTO_RX_FLOW_FLAG HSL_RO - -#define AUTO_TX_FLOW -#define PORT_STATUS_AUTO_TX_FLOW_BOFFSET 10 -#define PORT_STATUS_AUTO_TX_FLOW_BLEN 1 -#define PORT_STATUS_AUTO_TX_FLOW_FLAG HSL_RO - -#define LINK_EN -#define PORT_STATUS_LINK_EN_BOFFSET 9 -#define PORT_STATUS_LINK_EN_BLEN 1 -#define PORT_STATUS_LINK_EN_FLAG HSL_RW - -#define LINK -#define PORT_STATUS_LINK_BOFFSET 8 -#define PORT_STATUS_LINK_BLEN 1 -#define PORT_STATUS_LINK_FLAG HSL_RO - -#define TX_HALF_FLOW_EN -#define PORT_STATUS_TX_HALF_FLOW_EN_BOFFSET 7 -#define PORT_STATUS_TX_HALF_FLOW_EN_BLEN 1 -#define PORT_STATUS_TX_HALF_FLOW_EN_FLAG HSL_RW - -#define DUPLEX_MODE -#define PORT_STATUS_DUPLEX_MODE_BOFFSET 6 -#define PORT_STATUS_DUPLEX_MODE_BLEN 1 -#define PORT_STATUS_DUPLEX_MODE_FLAG HSL_RW - -#define RX_FLOW_EN -#define PORT_STATUS_RX_FLOW_EN_BOFFSET 5 -#define PORT_STATUS_RX_FLOW_EN_BLEN 1 -#define PORT_STATUS_RX_FLOW_EN_FLAG HSL_RW - -#define TX_FLOW_EN -#define PORT_STATUS_TX_FLOW_EN_BOFFSET 4 -#define PORT_STATUS_TX_FLOW_EN_BLEN 1 -#define PORT_STATUS_TX_FLOW_EN_FLAG HSL_RW - -#define RXMAC_EN -#define PORT_STATUS_RXMAC_EN_BOFFSET 3 -#define PORT_STATUS_RXMAC_EN_BLEN 1 -#define PORT_STATUS_RXMAC_EN_FLAG HSL_RW - -#define TXMAC_EN -#define PORT_STATUS_TXMAC_EN_BOFFSET 2 -#define PORT_STATUS_TXMAC_EN_BLEN 1 -#define PORT_STATUS_TXMAC_EN_FLAG HSL_RW - -#define SPEED_MODE -#define PORT_STATUS_SPEED_MODE_BOFFSET 0 -#define PORT_STATUS_SPEED_MODE_BLEN 2 -#define PORT_STATUS_SPEED_MODE_FLAG HSL_RW - - - - - /* Header Ctl Register */ -#define HEADER_CTL -#define HEADER_CTL_OFFSET 0x0098 -#define HEADER_CTL_E_LENGTH 4 -#define HEADER_CTL_E_OFFSET 0x0004 -#define HEADER_CTL_NR_E 1 - -#define TYPE_LEN -#define HEADER_CTL_TYPE_LEN_BOFFSET 16 -#define HEADER_CTL_TYPE_LEN_BLEN 1 -#define HEADER_CTL_TYPE_LEN_FLAG HSL_RW - -#define TYPE_VAL -#define HEADER_CTL_TYPE_VAL_BOFFSET 0 -#define HEADER_CTL_TYPE_VAL_BLEN 16 -#define HEADER_CTL_TYPE_VAL_FLAG HSL_RW - - - - - /* Port Header Ctl Register */ -#define PORT_HDR_CTL -#define PORT_HDR_CTL_OFFSET 0x009c -#define PORT_HDR_CTL_E_LENGTH 4 -#define PORT_HDR_CTL_E_OFFSET 0x0004 -#define PORT_HDR_CTL_NR_E 7 - -#define IPG_DEC_EN -#define PORT_HDR_CTL_IPG_DEC_EN_BOFFSET 5 -#define PORT_HDR_CTL_IPG_DEC_EN_BLEN 1 -#define PORT_HDR_CTL_IPG_DEC_EN_FLAG HSL_RW - -#define LOOPBACK_EN -#define PORT_HDR_CTL_LOOPBACK_EN_BOFFSET 4 -#define PORT_HDR_CTL_LOOPBACK_EN_BLEN 1 -#define PORT_HDR_CTL_LOOPBACK_EN_FLAG HSL_RW - -#define RXHDR_MODE -#define PORT_HDR_CTL_RXHDR_MODE_BOFFSET 2 -#define PORT_HDR_CTL_RXHDR_MODE_BLEN 2 -#define PORT_HDR_CTL_RXHDR_MODE_FLAG HSL_RW - -#define TXHDR_MODE -#define PORT_HDR_CTL_TXHDR_MODE_BOFFSET 0 -#define PORT_HDR_CTL_TXHDR_MODE_BLEN 2 -#define PORT_HDR_CTL_TXHDR_MODE_FLAG HSL_RW - - - - - /* EEE control Register */ -#define EEE_CTL -#define EEE_CTL_OFFSET 0x0100 -#define EEE_CTL_E_LENGTH 4 -#define EEE_CTL_E_OFFSET 0 -#define EEE_CTL_NR_E 1 - -#define LPI_STATE_REMAP_EN_5 -#define EEE_CTL_LPI_STATE_REMAP_EN_5_BOFFSET 13 -#define EEE_CTL_LPI_STATE_REMAP_EN_5_BLEN 1 -#define EEE_CTL_LPI_STATE_REMAP_EN_5_FLAG HSL_RW - -#define LPI_EN_5 -#define EEE_CTL_LPI_EN_5_BOFFSET 12 -#define EEE_CTL_LPI_EN_5_BLEN 1 -#define EEE_CTL_LPI_EN_5_FLAG HSL_RW - -#define LPI_STATE_REMAP_EN_4 -#define EEE_CTL_LPI_STATE_REMAP_EN_4_BOFFSET 11 -#define EEE_CTL_LPI_STATE_REMAP_EN_4_BLEN 1 -#define EEE_CTL_LPI_STATE_REMAP_EN_4_FLAG HSL_RW - -#define LPI_EN_4 -#define EEE_CTL_LPI_EN_4_BOFFSET 10 -#define EEE_CTL_LPI_EN_4_BLEN 1 -#define EEE_CTL_LPI_EN_4_FLAG HSL_RW - -#define LPI_STATE_REMAP_EN_3 -#define EEE_CTL_LPI_STATE_REMAP_EN_3_BOFFSET 9 -#define EEE_CTL_LPI_STATE_REMAP_EN_3_BLEN 1 -#define EEE_CTL_LPI_STATE_REMAP_EN_3_FLAG HSL_RW - -#define LPI_EN_3 -#define EEE_CTL_LPI_EN_3_BOFFSET 8 -#define EEE_CTL_LPI_EN_3_BLEN 1 -#define EEE_CTL_LPI_EN_3_FLAG HSL_RW - -#define LPI_STATE_REMAP_EN_2 -#define EEE_CTL_LPI_STATE_REMAP_EN_2_BOFFSET 7 -#define EEE_CTL_LPI_STATE_REMAP_EN_2_BLEN 1 -#define EEE_CTL_LPI_STATE_REMAP_EN_2_FLAG HSL_RW - -#define LPI_EN_2 -#define EEE_CTL_LPI_EN_2_BOFFSET 6 -#define EEE_CTL_LPI_EN_2_BLEN 1 -#define EEE_CTL_LPI_EN_2_FLAG HSL_RW - -#define LPI_STATE_REMAP_EN_1 -#define EEE_CTL_LPI_STATE_REMAP_EN_1_BOFFSET 5 -#define EEE_CTL_LPI_STATE_REMAP_EN_1_BLEN 1 -#define EEE_CTL_LPI_STATE_REMAP_EN_1_FLAG HSL_RW - -#define LPI_EN_1 -#define EEE_CTL_LPI_EN_1_BOFFSET 4 -#define EEE_CTL_LPI_EN_1_BLEN 1 -#define EEE_CTL_LPI_EN_1_FLAG HSL_RW - - - - - /* Frame Ack Ctl0 Register */ -#define FRAME_ACK_CTL0 -#define FRAME_ACK_CTL0_OFFSET 0x0210 -#define FRAME_ACK_CTL0_E_LENGTH 4 -#define FRAME_ACK_CTL0_E_OFFSET 0 -#define FRAME_ACK_CTL0_NR_E 1 - -#define ARP_REQ_EN -#define FRAME_ACK_CTL0_ARP_REQ_EN_BOFFSET 6 -#define FRAME_ACK_CTL0_ARP_REQ_EN_BLEN 1 -#define FRAME_ACK_CTL0_ARP_REQ_EN_FLAG HSL_RW - -#define ARP_REP_EN -#define FRAME_ACK_CTL0_ARP_REP_EN_BOFFSET 5 -#define FRAME_ACK_CTL0_ARP_REP_EN_BLEN 1 -#define FRAME_ACK_CTL0_ARP_REP_EN_FLAG HSL_RW - -#define DHCP_EN -#define FRAME_ACK_CTL0_DHCP_EN_BOFFSET 4 -#define FRAME_ACK_CTL0_DHCP_EN_BLEN 1 -#define FRAME_ACK_CTL0_DHCP_EN_FLAG HSL_RW - -#define EAPOL_EN -#define FRAME_ACK_CTL0_EAPOL_EN_BOFFSET 3 -#define FRAME_ACK_CTL0_EAPOL_EN_BLEN 1 -#define FRAME_ACK_CTL0_EAPOL_EN_FLAG HSL_RW - -#define LEAVE_EN -#define FRAME_ACK_CTL0_LEAVE_EN_BOFFSET 2 -#define FRAME_ACK_CTL0_LEAVE_EN_BLEN 1 -#define FRAME_ACK_CTL0_LEAVE_EN_FLAG HSL_RW - -#define JOIN_EN -#define FRAME_ACK_CTL0_JOIN_EN_BOFFSET 1 -#define FRAME_ACK_CTL0_JOIN_EN_BLEN 1 -#define FRAME_ACK_CTL0_JOIN_EN_FLAG HSL_RW - -#define IGMP_MLD_EN -#define FRAME_ACK_CTL0_IGMP_MLD_EN_BOFFSET 0 -#define FRAME_ACK_CTL0_IGMP_MLD_EN_BLEN 1 -#define FRAME_ACK_CTL0_IGMP_MLD_EN_FLAG HSL_RW - - - - - /* Frame Ack Ctl1 Register */ -#define FRAME_ACK_CTL1 -#define FRAME_ACK_CTL1_OFFSET 0x0214 -#define FRAME_ACK_CTL1_E_LENGTH 4 -#define FRAME_ACK_CTL1_E_OFFSET 0 -#define FRAME_ACK_CTL1_NR_E 1 - -#define PPPOE_EN -#define FRAME_ACK_CTL1_PPPOE_EN_BOFFSET 25 -#define FRAME_ACK_CTL1_PPPOE_EN_BLEN 1 -#define FRAME_ACK_CTL1_PPPOE_EN_FLAG HSL_RW - -#define IGMP_V3_EN -#define FRAME_ACK_CTL1_IGMP_V3_EN_BOFFSET 24 -#define FRAME_ACK_CTL1_IGMP_V3_EN_BLEN 1 -#define FRAME_ACK_CTL1_IGMP_V3_EN_FLAG HSL_RW - - - - - /* Window Rule Ctl0 Register */ -#define WIN_RULE_CTL0 -#define WIN_RULE_CTL0_OFFSET 0x0218 -#define WIN_RULE_CTL0_E_LENGTH 4 -#define WIN_RULE_CTL0_E_OFFSET 0x4 -#define WIN_RULE_CTL0_NR_E 7 - -#define L4_LENGTH -#define WIN_RULE_CTL0_L4_LENGTH_BOFFSET 24 -#define WIN_RULE_CTL0_L4_LENGTH_BLEN 4 -#define WIN_RULE_CTL0_L4_LENGTH_FLAG HSL_RW - -#define L3_LENGTH -#define WIN_RULE_CTL0_L3_LENGTH_BOFFSET 20 -#define WIN_RULE_CTL0_L3_LENGTH_BLEN 4 -#define WIN_RULE_CTL0_L3_LENGTH_FLAG HSL_RW - -#define L2_LENGTH -#define WIN_RULE_CTL0_L2_LENGTH_BOFFSET 16 -#define WIN_RULE_CTL0_L2_LENGTH_BLEN 4 -#define WIN_RULE_CTL0_L2_LENGTH_FLAG HSL_RW - -#define L4_OFFSET -#define WIN_RULE_CTL0_L4_OFFSET_BOFFSET 10 -#define WIN_RULE_CTL0_L4_OFFSET_BLEN 5 -#define WIN_RULE_CTL0_L4_OFFSET_FLAG HSL_RW - -#define L3_OFFSET -#define WIN_RULE_CTL0_L3_OFFSET_BOFFSET 5 -#define WIN_RULE_CTL0_L3_OFFSET_BLEN 5 -#define WIN_RULE_CTL0_L3_OFFSET_FLAG HSL_RW - -#define L2_OFFSET -#define WIN_RULE_CTL0_L2_OFFSET_BOFFSET 0 -#define WIN_RULE_CTL0_L2_OFFSET_BLEN 5 -#define WIN_RULE_CTL0_L2_OFFSET_FLAG HSL_RW - - - - - /* Window Rule Ctl1 Register */ -#define WIN_RULE_CTL1 -#define WIN_RULE_CTL1_OFFSET 0x0234 -#define WIN_RULE_CTL1_E_LENGTH 4 -#define WIN_RULE_CTL1_E_OFFSET 0x4 -#define WIN_RULE_CTL1_NR_E 7 - -#define L3P_LENGTH -#define WIN_RULE_CTL1_L3P_LENGTH_BOFFSET 20 -#define WIN_RULE_CTL1_L3P_LENGTH_BLEN 4 -#define WIN_RULE_CTL1_L3P_LENGTH_FLAG HSL_RW - -#define L2S_LENGTH -#define WIN_RULE_CTL1_L2S_LENGTH_BOFFSET 16 -#define WIN_RULE_CTL1_L2S_LENGTH_BLEN 4 -#define WIN_RULE_CTL1_L2S_LENGTH_FLAG HSL_RW - -#define L3P_OFFSET -#define WIN_RULE_CTL1_L3P_OFFSET_BOFFSET 5 -#define WIN_RULE_CTL1_L3P_OFFSET_BLEN 5 -#define WIN_RULE_CTL1_L3P_OFFSET_FLAG HSL_RW - -#define L2S_OFFSET -#define WIN_RULE_CTL1_L2S_OFFSET_BOFFSET 0 -#define WIN_RULE_CTL1_L2S_OFFSET_BLEN 5 -#define WIN_RULE_CTL1_L2S_OFFSET_FLAG HSL_RW - - - - - /* Trunk Hash Mode Register */ -#define TRUNK_HASH_MODE -#define TRUNK_HASH_MODE_OFFSET 0x0270 -#define TRUNK_HASH_MODE_E_LENGTH 4 -#define TRUNK_HASH_MODE_E_OFFSET 0x4 -#define TRUNK_HASH_MODE_NR_E 1 - -#define SIP_EN -#define TRUNK_HASH_MODE_SIP_EN_BOFFSET 3 -#define TRUNK_HASH_MODE_SIP_EN_BLEN 1 -#define TRUNK_HASH_MODE_SIP_EN_FLAG HSL_RW - -#define DIP_EN -#define TRUNK_HASH_MODE_DIP_EN_BOFFSET 2 -#define TRUNK_HASH_MODE_DIP_EN_BLEN 1 -#define TRUNK_HASH_MODE_DIP_EN_FLAG HSL_RW - -#define SA_EN -#define TRUNK_HASH_MODE_SA_EN_BOFFSET 1 -#define TRUNK_HASH_MODE_SA_EN_BLEN 1 -#define TRUNK_HASH_MODE_SA_EN_FLAG HSL_RW - -#define DA_EN -#define TRUNK_HASH_MODE_DA_EN_BOFFSET 0 -#define TRUNK_HASH_MODE_DA_EN_BLEN 1 -#define TRUNK_HASH_MODE_DA_EN_FLAG HSL_RW - - - - - /* Vlan Table Function0 Register */ -#define VLAN_TABLE_FUNC0 -#define VLAN_TABLE_FUNC0_OFFSET 0x0610 -#define VLAN_TABLE_FUNC0_E_LENGTH 4 -#define VLAN_TABLE_FUNC0_E_OFFSET 0 -#define VLAN_TABLE_FUNC0_NR_E 1 - -#define VT_VALID -#define VLAN_TABLE_FUNC0_VT_VALID_BOFFSET 20 -#define VLAN_TABLE_FUNC0_VT_VALID_BLEN 1 -#define VLAN_TABLE_FUNC0_VT_VALID_FLAG HSL_RW - -#define IVL_EN -#define VLAN_TABLE_FUNC0_IVL_EN_BOFFSET 19 -#define VLAN_TABLE_FUNC0_IVL_EN_BLEN 1 -#define VLAN_TABLE_FUNC0_IVL_EN_FLAG HSL_RW - -#define LEARN_DIS -#define VLAN_TABLE_FUNC0_LEARN_DIS_BOFFSET 18 -#define VLAN_TABLE_FUNC0_LEARN_DIS_BLEN 1 -#define VLAN_TABLE_FUNC0_LEARN_DIS_FLAG HSL_RW - -#define VID_MEM -#define VLAN_TABLE_FUNC0_VID_MEM_BOFFSET 4 -#define VLAN_TABLE_FUNC0_VID_MEM_BLEN 14 -#define VLAN_TABLE_FUNC0_VID_MEM_FLAG HSL_RW - -#define VT_PRI_EN -#define VLAN_TABLE_FUNC0_VT_PRI_EN_BOFFSET 3 -#define VLAN_TABLE_FUNC0_VT_PRI_EN_BLEN 1 -#define VLAN_TABLE_FUNC0_VT_PRI_EN_FLAG HSL_RW - -#define VT_PRI -#define VLAN_TABLE_FUNC0_VT_PRI_BOFFSET 0 -#define VLAN_TABLE_FUNC0_VT_PRI_BLEN 3 -#define VLAN_TABLE_FUNC0_VT_PRI_FLAG HSL_RW - - /* Vlan Table Function1 Register */ -#define VLAN_TABLE_FUNC1 -#define VLAN_TABLE_FUNC1_OFFSET 0x0614 -#define VLAN_TABLE_FUNC1_E_LENGTH 4 -#define VLAN_TABLE_FUNC1_E_OFFSET 0 -#define VLAN_TABLE_FUNC1_NR_E 1 - -#define VT_BUSY -#define VLAN_TABLE_FUNC1_VT_BUSY_BOFFSET 31 -#define VLAN_TABLE_FUNC1_VT_BUSY_BLEN 1 -#define VLAN_TABLE_FUNC1_VT_BUSY_FLAG HSL_RW - -#define VLAN_ID -#define VLAN_TABLE_FUNC1_VLAN_ID_BOFFSET 16 -#define VLAN_TABLE_FUNC1_VLAN_ID_BLEN 12 -#define VLAN_TABLE_FUNC1_VLAN_ID_FLAG HSL_RW - -#define VT_PORT_NUM -#define VLAN_TABLE_FUNC1_VT_PORT_NUM_BOFFSET 8 -#define VLAN_TABLE_FUNC1_VT_PORT_NUM_BLEN 4 -#define VLAN_TABLE_FUNC1_VT_PORT_NUM_FLAG HSL_RW - -#define VT_FULL_VIO -#define VLAN_TABLE_FUNC1_VT_FULL_VIO_BOFFSET 4 -#define VLAN_TABLE_FUNC1_VT_FULL_VIO_BLEN 1 -#define VLAN_TABLE_FUNC1_VT_FULL_VIO_FLAG HSL_RW - -#define VT_FUNC -#define VLAN_TABLE_FUNC1_VT_FUNC_BOFFSET 0 -#define VLAN_TABLE_FUNC1_VT_FUNC_BLEN 3 -#define VLAN_TABLE_FUNC1_VT_FUNC_FLAG HSL_RW - - - - - /* Address Table Function0 Register */ -#define ADDR_TABLE_FUNC0 -#define ADDR_TABLE_FUNC0_OFFSET 0x0600 -#define ADDR_TABLE_FUNC0_E_LENGTH 4 -#define ADDR_TABLE_FUNC0_E_OFFSET 0 -#define ADDR_TABLE_FUNC0_NR_E 1 - - -#define AT_ADDR_BYTE2 -#define ADDR_TABLE_FUNC0_AT_ADDR_BYTE2_BOFFSET 24 -#define ADDR_TABLE_FUNC0_AT_ADDR_BYTE2_BLEN 8 -#define ADDR_TABLE_FUNC0_AT_ADDR_BYTE2_FLAG HSL_RW - -#define AT_ADDR_BYTE3 -#define ADDR_TABLE_FUNC0_AT_ADDR_BYTE3_BOFFSET 16 -#define ADDR_TABLE_FUNC0_AT_ADDR_BYTE3_BLEN 8 -#define ADDR_TABLE_FUNC0_AT_ADDR_BYTE3_FLAG HSL_RW - -#define AT_ADDR_BYTE4 -#define ADDR_TABLE_FUNC0_AT_ADDR_BYTE4_BOFFSET 8 -#define ADDR_TABLE_FUNC0_AT_ADDR_BYTE4_BLEN 8 -#define ADDR_TABLE_FUNC0_AT_ADDR_BYTE4_FLAG HSL_RW - -#define AT_ADDR_BYTE5 -#define ADDR_TABLE_FUNC0_AT_ADDR_BYTE5_BOFFSET 0 -#define ADDR_TABLE_FUNC0_AT_ADDR_BYTE5_BLEN 8 -#define ADDR_TABLE_FUNC0_AT_ADDR_BYTE5_FLAG HSL_RW - - /* Address Table Function1 Register */ -#define ADDR_TABLE_FUNC1 -#define ADDR_TABLE_FUNC1_OFFSET 0x0604 -#define ADDR_TABLE_FUNC1_E_LENGTH 4 -#define ADDR_TABLE_FUNC1_E_OFFSET 0 -#define ADDR_TABLE_FUNC1_NR_E 1 - -#define SA_DROP_EN -#define ADDR_TABLE_FUNC1_SA_DROP_EN_BOFFSET 30 -#define ADDR_TABLE_FUNC1_SA_DROP_EN_BLEN 1 -#define ADDR_TABLE_FUNC1_SA_DROP_EN_FLAG HSL_RW - -#define MIRROR_EN -#define ADDR_TABLE_FUNC1_MIRROR_EN_BOFFSET 29 -#define ADDR_TABLE_FUNC1_MIRROR_EN_BLEN 1 -#define ADDR_TABLE_FUNC1_MIRROR_EN_FLAG HSL_RW - -#define AT_PRI_EN -#define ADDR_TABLE_FUNC1_AT_PRI_EN_BOFFSET 28 -#define ADDR_TABLE_FUNC1_AT_PRI_EN_BLEN 1 -#define ADDR_TABLE_FUNC1_AT_PRI_EN_FLAG HSL_RW - -#define AT_SVL_EN -#define ADDR_TABLE_FUNC1_AT_SVL_EN_BOFFSET 27 -#define ADDR_TABLE_FUNC1_AT_SVL_EN_BLEN 1 -#define ADDR_TABLE_FUNC1_AT_SVL_EN_FLAG HSL_RW - -#define AT_PRI -#define ADDR_TABLE_FUNC1_AT_PRI_BOFFSET 24 -#define ADDR_TABLE_FUNC1_AT_PRI_BLEN 3 -#define ADDR_TABLE_FUNC1_AT_PRI_FLAG HSL_RW - -#define CROSS_PT -#define ADDR_TABLE_FUNC1_CROSS_PT_BOFFSET 23 -#define ADDR_TABLE_FUNC1_CROSS_PT_BLEN 1 -#define ADDR_TABLE_FUNC1_CROSS_PT_FLAG HSL_RW - -#define DES_PORT -#define ADDR_TABLE_FUNC1_DES_PORT_BOFFSET 16 -#define ADDR_TABLE_FUNC1_DES_PORT_BLEN 7 -#define ADDR_TABLE_FUNC1_DES_PORT_FLAG HSL_RW - -#define AT_ADDR_BYTE0 -#define ADDR_TABLE_FUNC1_AT_ADDR_BYTE0_BOFFSET 8 -#define ADDR_TABLE_FUNC1_AT_ADDR_BYTE0_BLEN 8 -#define ADDR_TABLE_FUNC1_AT_ADDR_BYTE0_FLAG HSL_RW - -#define AT_ADDR_BYTE1 -#define ADDR_TABLE_FUNC1_AT_ADDR_BYTE1_BOFFSET 0 -#define ADDR_TABLE_FUNC1_AT_ADDR_BYTE1_BLEN 8 -#define ADDR_TABLE_FUNC1_AT_ADDR_BYTE1_FLAG HSL_RW - - /* Address Table Function2 Register */ -#define ADDR_TABLE_FUNC2 -#define ADDR_TABLE_FUNC2_OFFSET 0x0608 -#define ADDR_TABLE_FUNC2_E_LENGTH 4 -#define ADDR_TABLE_FUNC2_E_OFFSET 0 -#define ADDR_TABLE_FUNC2_NR_E 1 - -#define WL_EN -#define ADDR_TABLE_FUNC2_WL_EN_BOFFSET 20 -#define ADDR_TABLE_FUNC2_WL_EN_BLEN 1 -#define ADDR_TABLE_FUNC2_WL_EN_FLAG HSL_RW - -#define AT_VID -#define ADDR_TABLE_FUNC2_AT_VID_BOFFSET 8 -#define ADDR_TABLE_FUNC2_AT_VID_BLEN 12 -#define ADDR_TABLE_FUNC2_AT_VID_FLAG HSL_RW - -#define SHORT_LOOP -#define ADDR_TABLE_FUNC2_SHORT_LOOP_BOFFSET 7 -#define ADDR_TABLE_FUNC2_SHORT_LOOP_BLEN 1 -#define ADDR_TABLE_FUNC2_SHORT_LOOP_FLAG HSL_RW - -#define COPY_TO_CPU -#define ADDR_TABLE_FUNC2_COPY_TO_CPU_BOFFSET 6 -#define ADDR_TABLE_FUNC2_COPY_TO_CPU_BLEN 1 -#define ADDR_TABLE_FUNC2_COPY_TO_CPU_FLAG HSL_RW - -#define REDRCT_TO_CPU -#define ADDR_TABLE_FUNC2_REDRCT_TO_CPU_BOFFSET 5 -#define ADDR_TABLE_FUNC2_REDRCT_TO_CPU_BLEN 1 -#define ADDR_TABLE_FUNC2_REDRCT_TO_CPU_FLAG HSL_RW - -#define LEAKY_EN -#define ADDR_TABLE_FUNC2_LEAKY_EN_BOFFSET 4 -#define ADDR_TABLE_FUNC2_LEAKY_EN_BLEN 1 -#define ADDR_TABLE_FUNC2_LEAKY_EN_FLAG HSL_RW - -#define AT_STATUS -#define ADDR_TABLE_FUNC2_AT_STATUS_BOFFSET 0 -#define ADDR_TABLE_FUNC2_AT_STATUS_BLEN 4 -#define ADDR_TABLE_FUNC2_AT_STATUS_FLAG HSL_RW - - /* Address Table Function3 Register */ -#define ADDR_TABLE_FUNC3 -#define ADDR_TABLE_FUNC3_OFFSET 0x060c -#define ADDR_TABLE_FUNC3_E_LENGTH 4 -#define ADDR_TABLE_FUNC3_E_OFFSET 0 -#define ADDR_TABLE_FUNC3_NR_E 1 - -#define AT_BUSY -#define ADDR_TABLE_FUNC3_AT_BUSY_BOFFSET 31 -#define ADDR_TABLE_FUNC3_AT_BUSY_BLEN 1 -#define ADDR_TABLE_FUNC3_AT_BUSY_FLAG HSL_RW - -#define NEW_PORT_NUM -#define ADDR_TABLE_FUNC3_NEW_PORT_NUM_BOFFSET 22 -#define ADDR_TABLE_FUNC3_NEW_PORT_NUM_BLEN 3 -#define ADDR_TABLE_FUNC3_NEW_PORT_NUM_FLAG HSL_RW - -#define AT_INDEX -#define ADDR_TABLE_FUNC3_AT_INDEX_BOFFSET 16 -#define ADDR_TABLE_FUNC3_AT_INDEX_BLEN 5 -#define ADDR_TABLE_FUNC3_AT_INDEX_FLAG HSL_RW - -#define AT_VID_EN -#define ADDR_TABLE_FUNC3_AT_VID_EN_BOFFSET 15 -#define ADDR_TABLE_FUNC3_AT_VID_EN_BLEN 1 -#define ADDR_TABLE_FUNC3_AT_VID_EN_FLAG HSL_RW - -#define AT_PORT_EN -#define ADDR_TABLE_FUNC3_AT_PORT_EN_BOFFSET 14 -#define ADDR_TABLE_FUNC3_AT_PORT_EN_BLEN 1 -#define ADDR_TABLE_FUNC3_AT_PORT_EN_FLAG HSL_RW - -#define AT_MULTI_EN -#define ADDR_TABLE_FUNC3_AT_MULTI_EN_BOFFSET 13 -#define ADDR_TABLE_FUNC3_AT_MULTI_EN_BLEN 1 -#define ADDR_TABLE_FUNC3_AT_MULTI_EN_FLAG HSL_RW - -#define AT_FULL_VIO -#define ADDR_TABLE_FUNC3_AT_FULL_VIO_BOFFSET 12 -#define ADDR_TABLE_FUNC3_AT_FULL_VIO_BLEN 1 -#define ADDR_TABLE_FUNC3_AT_FULL_VIO_FLAG HSL_RW - -#define AT_PORT_NUM -#define ADDR_TABLE_FUNC3_AT_PORT_NUM_BOFFSET 8 -#define ADDR_TABLE_FUNC3_AT_PORT_NUM_BLEN 4 -#define ADDR_TABLE_FUNC3_AT_PORT_NUM_FLAG HSL_RW - -#define FLUSH_ST_EN -#define ADDR_TABLE_FUNC3_FLUSH_ST_EN_BOFFSET 4 -#define ADDR_TABLE_FUNC3_FLUSH_ST_EN_BLEN 1 -#define ADDR_TABLE_FUNC3_FLUSH_ST_EN_FLAG HSL_RW - -#define AT_FUNC -#define ADDR_TABLE_FUNC3_AT_FUNC_BOFFSET 0 -#define ADDR_TABLE_FUNC3_AT_FUNC_BLEN 4 -#define ADDR_TABLE_FUNC3_AT_FUNC_FLAG HSL_RW - - - - - /* Reserve Address Table0 Register */ -#define RESV_ADDR_TBL0 -#define RESV_ADDR_TBL0_OFFSET 0x3c000 -#define RESV_ADDR_TBL0_E_LENGTH 4 -#define RESV_ADDR_TBL0_E_OFFSET 0 -#define RESV_ADDR_TBL0_NR_E 1 - -#define RESV_ADDR_BYTE2 -#define RESV_ADDR_TBL0_RESV_ADDR_BYTE2_BOFFSET 24 -#define RESV_ADDR_TBL0_RESV_ADDR_BYTE2_BLEN 8 -#define RESV_ADDR_TBL0_RESV_ADDR_BYTE2_FLAG HSL_RW - -#define RESV_ADDR_BYTE3 -#define RESV_ADDR_TBL0_RESV_ADDR_BYTE3_BOFFSET 16 -#define RESV_ADDR_TBL0_RESV_ADDR_BYTE3_BLEN 8 -#define RESV_ADDR_TBL0_RESV_ADDR_BYTE3_FLAG HSL_RW - -#define RESV_ADDR_BYTE4 -#define RESV_ADDR_TBL0_RESV_ADDR_BYTE4_BOFFSET 8 -#define RESV_ADDR_TBL0_RESV_ADDR_BYTE4_BLEN 8 -#define RESV_ADDR_TBL0_RESV_ADDR_BYTE4_FLAG HSL_RW - -#define RESV_ADDR_BYTE5 -#define RESV_ADDR_TBL0_RESV_ADDR_BYTE5_BOFFSET 0 -#define RESV_ADDR_TBL0_RESV_ADDR_BYTE5_BLEN 8 -#define RESV_ADDR_TBL0_RESV_ADDR_BYTE5_FLAG HSL_RW - - /* Reserve Address Table1 Register */ -#define RESV_ADDR_TBL1 -#define RESV_ADDR_TBL1_OFFSET 0x3c004 -#define RESV_ADDR_TBL1_E_LENGTH 4 -#define RESV_ADDR_TBL1_E_OFFSET 0 -#define RESV_ADDR_TBL1_NR_E 1 - -#define RESV_COPY_TO_CPU -#define RESV_ADDR_TBL1_RESV_COPY_TO_CPU_BOFFSET 31 -#define RESV_ADDR_TBL1_RESV_COPY_TO_CPU_BLEN 1 -#define RESV_ADDR_TBL1_RESV_COPY_TO_CPU_FLAG HSL_RW - -#define RESV_REDRCT_TO_CPU -#define RESV_ADDR_TBL1_RESV_REDRCT_TO_CPU_BOFFSET 30 -#define RESV_ADDR_TBL1_RESV_REDRCT_TO_CPU_BLEN 1 -#define RESV_ADDR_TBL1_RESV_REDRCT_TO_CPU_FLAG HSL_RW - -#define RESV_LEAKY_EN -#define RESV_ADDR_TBL1_RESV_LEAKY_EN_BOFFSET 29 -#define RESV_ADDR_TBL1_RESV_LEAKY_EN_BLEN 1 -#define RESV_ADDR_TBL1_RESV_LEAKY_EN_FLAG HSL_RW - -#define RESV_MIRROR_EN -#define RESV_ADDR_TBL1_RESV_MIRROR_EN_BOFFSET 28 -#define RESV_ADDR_TBL1_RESV_MIRROR_EN_BLEN 1 -#define RESV_ADDR_TBL1_RESV_MIRROR_EN_FLAG HSL_RW - -#define RESV_PRI_EN -#define RESV_ADDR_TBL1_RESV_PRI_EN_BOFFSET 27 -#define RESV_ADDR_TBL1_RESV_PRI_EN_BLEN 1 -#define RESV_ADDR_TBL1_RESV_PRI_EN_FLAG HSL_RW - -#define RESV_PRI -#define RESV_ADDR_TBL1_RESV_PRI_BOFFSET 24 -#define RESV_ADDR_TBL1_RESV_PRI_BLEN 3 -#define RESV_ADDR_TBL1_RESV_PRI_FLAG HSL_RW - -#define RESV_CROSS_PT -#define RESV_ADDR_TBL1_RESV_CROSS_PT_BOFFSET 23 -#define RESV_ADDR_TBL1_RESV_CROSS_PT_BLEN 1 -#define RESV_ADDR_TBL1_RESV_CROSS_PT_FLAG HSL_RW - -#define RESV_DES_PORT -#define RESV_ADDR_TBL1_RESV_DES_PORT_BOFFSET 16 -#define RESV_ADDR_TBL1_RESV_DES_PORT_BLEN 7 -#define RESV_ADDR_TBL1_RESV_DES_PORT_FLAG HSL_RW - -#define RESV_ADDR_BYTE0 -#define RESV_ADDR_TBL1_RESV_ADDR_BYTE0_BOFFSET 8 -#define RESV_ADDR_TBL1_RESV_ADDR_BYTE0_BLEN 8 -#define RESV_ADDR_TBL1_RESV_ADDR_BYTE0_FLAG HSL_RW - -#define RESV_ADDR_BYTE1 -#define RESV_ADDR_TBL1_RESV_ADDR_BYTE1_BOFFSET 0 -#define RESV_ADDR_TBL1_RESV_ADDR_BYTE1_BLEN 8 -#define RESV_ADDR_TBL1_RESV_ADDR_BYTE1_FLAG HSL_RW - - /* Reserve Address Table2 Register */ -#define RESV_ADDR_TBL2 -#define RESV_ADDR_TBL2_OFFSET 0x3c008 -#define RESV_ADDR_TBL2_E_LENGTH 4 -#define RESV_ADDR_TBL2_E_OFFSET 0 -#define RESV_ADDR_TBL2_NR_E 1 - -#define RESV_STATUS -#define RESV_ADDR_TBL2_RESV_STATUS_BOFFSET 0 -#define RESV_ADDR_TBL2_RESV_STATUS_BLEN 1 -#define RESV_ADDR_TBL2_RESV_STATUS_FLAG HSL_RW - - - - - /* Address Table Control Register */ -#define ADDR_TABLE_CTL -#define ADDR_TABLE_CTL_OFFSET 0x0618 -#define ADDR_TABLE_CTL_E_LENGTH 4 -#define ADDR_TABLE_CTL_E_OFFSET 0 -#define ADDR_TABLE_CTL_NR_E 1 - -#define ARL_INI_EN -#define ADDR_TABLE_CTL_ARL_INI_EN_BOFFSET 31 -#define ADDR_TABLE_CTL_ARL_INI_EN_BLEN 1 -#define ADDR_TABLE_CTL_ARL_INI_EN_FLAG HSL_RW - -#define LEARN_CHANGE_EN -#define ADDR_TABLE_CTL_LEARN_CHANGE_EN_BOFFSET 30 -#define ADDR_TABLE_CTL_LEARN_CHANGE_EN_BLEN 1 -#define ADDR_TABLE_CTL_LEARN_CHANGE_EN_FLAG HSL_RW - -#define IGMP_JOIN_LEAKY -#define ADDR_TABLE_CTL_IGMP_JOIN_LEAKY_BOFFSET 29 -#define ADDR_TABLE_CTL_IGMP_JOIN_LEAKY_BLEN 1 -#define ADDR_TABLE_CTL_IGMP_JOIN_LEAKY_FLAG HSL_RW - -#define IGMP_CREAT_EN -#define ADDR_TABLE_CTL_IGMP_CREAT_EN_BOFFSET 28 -#define ADDR_TABLE_CTL_IGMP_CREAT_EN_BLEN 1 -#define ADDR_TABLE_CTL_IGMP_CREAT_EN_FLAG HSL_RW - -#define IGMP_PRI_EN -#define ADDR_TABLE_CTL_IGMP_PRI_EN_BOFFSET 27 -#define ADDR_TABLE_CTL_IGMP_PRI_EN_BLEN 1 -#define ADDR_TABLE_CTL_IGMP_PRI_EN_FLAG HSL_RW - -#define IGMP_PRI -#define ADDR_TABLE_CTL_IGMP_PRI_BOFFSET 24 -#define ADDR_TABLE_CTL_IGMP_PRI_BLEN 3 -#define ADDR_TABLE_CTL_IGMP_PRI_FLAG HSL_RW - -#define IGMP_JOIN_STATIC -#define ADDR_TABLE_CTL_IGMP_JOIN_STATIC_BOFFSET 20 -#define ADDR_TABLE_CTL_IGMP_JOIN_STATIC_BLEN 4 -#define ADDR_TABLE_CTL_IGMP_JOIN_STATIC_FLAG HSL_RW - -#define AGE_EN -#define ADDR_TABLE_CTL_AGE_EN_BOFFSET 19 -#define ADDR_TABLE_CTL_AGE_EN_BLEN 1 -#define ADDR_TABLE_CTL_AGE_EN_FLAG HSL_RW - -#define LOOP_CHECK_TIMER -#define ADDR_TABLE_CTL_LOOP_CHECK_TIMER_BOFFSET 16 -#define ADDR_TABLE_CTL_LOOP_CHECK_TIMER_BLEN 3 -#define ADDR_TABLE_CTL_LOOP_CHECK_TIMER_FLAG HSL_RW - -#define AGE_TIME -#define ADDR_TABLE_CTL_AGE_TIME_BOFFSET 0 -#define ADDR_TABLE_CTL_AGE_TIME_BLEN 16 -#define ADDR_TABLE_CTL_AGE_TIME_FLAG HSL_RW - - - - - /* Global Forward Control0 Register */ -#define FORWARD_CTL0 -#define FORWARD_CTL0_OFFSET 0x0620 -#define FORWARD_CTL0_E_LENGTH 4 -#define FORWARD_CTL0_E_OFFSET 0 -#define FORWARD_CTL0_NR_E 1 - -#define ARP_CMD -#define FORWARD_CTL0_ARP_CMD_BOFFSET 26 -#define FORWARD_CTL0_ARP_CMD_BLEN 2 -#define FORWARD_CTL0_ARP_CMD_FLAG HSL_RW - -#define IP_NOT_FOUND -#define FORWARD_CTL0_IP_NOT_FOUND_BOFFSET 24 -#define FORWARD_CTL0_IP_NOT_FOUND_BLEN 2 -#define FORWARD_CTL0_IP_NOT_FOUND_FLAG HSL_RW - -#define ARP_NOT_FOUND -#define FORWARD_CTL0_ARP_NOT_FOUND_BOFFSET 22 -#define FORWARD_CTL0_ARP_NOT_FOUND_BLEN 2 -#define FORWARD_CTL0_ARP_NOT_FOUND_FLAG HSL_RW - -#define HASH_MODE -#define FORWARD_CTL0_HASH_MODE_BOFFSET 20 -#define FORWARD_CTL0_HASH_MODE_BLEN 2 -#define FORWARD_CTL0_HASH_MODE_FLAG HSL_RW - -#define NAT_NOT_FOUND_DROP -#define FORWARD_CTL0_NAT_NOT_FOUND_DROP_BOFFSET 17 -#define FORWARD_CTL0_NAT_NOT_FOUND_DROP_BLEN 1 -#define FORWARD_CTL0_NAT_NOT_FOUND_DROP_FLAG HSL_RW - -#define SP_NOT_FOUND_DROP -#define FORWARD_CTL0_SP_NOT_FOUND_DROP_BOFFSET 16 -#define FORWARD_CTL0_SP_NOT_FOUND_DROP_BLEN 1 -#define FORWARD_CTL0_SP_NOT_FOUND_DROP_FLAG HSL_RW - -#define IGMP_LEAVE_DROP -#define FORWARD_CTL0_IGMP_LEAVE_DROP_BOFFSET 14 -#define FORWARD_CTL0_IGMP_LEAVE_DROP_BLEN 1 -#define FORWARD_CTL0_IGMP_LEAVE_DROP_FLAG HSL_RW - -#define ARL_UNI_LEAKY -#define FORWARD_CTL0_ARL_UNI_LEAKY_BOFFSET 13 -#define FORWARD_CTL0_ARL_UNI_LEAKY_BLEN 1 -#define FORWARD_CTL0_ARL_UNI_LEAKY_FLAG HSL_RW - -#define ARL_MUL_LEAKY -#define FORWARD_CTL0_ARL_MUL_LEAKY_BOFFSET 12 -#define FORWARD_CTL0_ARL_MUL_LEAKY_BLEN 1 -#define FORWARD_CTL0_ARL_MUL_LEAKY_FLAG HSL_RW - -#define MANAGE_VID_VIO_DROP_EN -#define FORWARD_CTL0_MANAGE_VID_VIO_DROP_EN_BOFFSET 11 -#define FORWARD_CTL0_MANAGE_VID_VIO_DROP_EN_BLEN 1 -#define FORWARD_CTL0_MANAGE_VID_VIO_DROP_EN_FLAG HSL_RW - -#define CPU_PORT_EN -#define FORWARD_CTL0_CPU_PORT_EN_BOFFSET 10 -#define FORWARD_CTL0_CPU_PORT_EN_BLEN 1 -#define FORWARD_CTL0_CPU_PORT_EN_FLAG HSL_RW - -#define PPPOE_RDT_EN -#define FORWARD_CTL0_PPPOE_RDT_EN_BOFFSET 8 -#define FORWARD_CTL0_PPPOE_RDT_EN_BLEN 1 -#define FORWARD_CTL0_PPPOE_RDT_EN_FLAG HSL_RW - -#define MIRROR_PORT_NUM -#define FORWARD_CTL0_MIRROR_PORT_NUM_BOFFSET 4 -#define FORWARD_CTL0_MIRROR_PORT_NUM_BLEN 4 -#define FORWARD_CTL0_MIRROR_PORT_NUM_FLAG HSL_RW - -#define IGMP_COPY_EN -#define FORWARD_CTL0_IGMP_COPY_EN_BOFFSET 3 -#define FORWARD_CTL0_IGMP_COPY_EN_BLEN 1 -#define FORWARD_CTL0_IGMP_COPY_EN_FLAG HSL_RW - -#define RIP_CPY_EN -#define FORWARD_CTL0_RIP_CPY_EN_BOFFSET 2 -#define FORWARD_CTL0_RIP_CPY_EN_BLEN 1 -#define FORWARD_CTL0_RIP_CPY_EN_FLAG HSL_RW - -#define EAPOL_CMD -#define FORWARD_CTL0_EAPOL_CMD_BOFFSET 0 -#define FORWARD_CTL0_EAPOL_CMD_BLEN 1 -#define FORWARD_CTL0_EAPOL_CMD_FLAG HSL_RW - - /* Global Forward Control1 Register */ -#define FORWARD_CTL1 -#define FORWARD_CTL1_OFFSET 0x0624 -#define FORWARD_CTL1_E_LENGTH 4 -#define FORWARD_CTL1_E_OFFSET 0 -#define FORWARD_CTL1_NR_E 1 - -#define IGMP_DP -#define FORWARD_CTL1_IGMP_DP_BOFFSET 24 -#define FORWARD_CTL1_IGMP_DP_BLEN 7 -#define FORWARD_CTL1_IGMP_DP_FLAG HSL_RW - -#define BC_FLOOD_DP -#define FORWARD_CTL1_BC_FLOOD_DP_BOFFSET 16 -#define FORWARD_CTL1_BC_FLOOD_DP_BLEN 7 -#define FORWARD_CTL1_BC_FLOOD_DP_FLAG HSL_RW - -#define MUL_FLOOD_DP -#define FORWARD_CTL1_MUL_FLOOD_DP_BOFFSET 8 -#define FORWARD_CTL1_MUL_FLOOD_DP_BLEN 7 -#define FORWARD_CTL1_MUL_FLOOD_DP_FLAG HSL_RW - -#define UNI_FLOOD_DP -#define FORWARD_CTL1_UNI_FLOOD_DP_BOFFSET 0 -#define FORWARD_CTL1_UNI_FLOOD_DP_BLEN 7 -#define FORWARD_CTL1_UNI_FLOOD_DP_FLAG HSL_RW - - - - - /* Global Learn Limit Ctl Register */ -#define GLOBAL_LEARN_LIMIT_CTL -#define GLOBAL_LEARN_LIMIT_CTL_OFFSET 0x0628 -#define GLOBAL_LEARN_LIMIT_CTL_E_LENGTH 4 -#define GLOBAL_LEARN_LIMIT_CTL_E_OFFSET 0 -#define GLOBAL_LEARN_LIMIT_CTL_NR_E 1 - -#define GOL_SA_LEARN_LIMIT_EN -#define GLOBAL_LEARN_LIMIT_CTL_GOL_SA_LEARN_LIMIT_EN_BOFFSET 12 -#define GLOBAL_LEARN_LIMIT_CTL_GOL_SA_LEARN_LIMIT_EN_BLEN 1 -#define GLOBAL_LEARN_LIMIT_CTL_GOL_SA_LEARN_LIMIT_EN_FLAG HSL_RW - -#define GOL_SA_LEARN_LIMIT_DROP_EN -#define GLOBAL_LEARN_LIMIT_CTL_GOL_SA_LEARN_LIMIT_DROP_EN_BOFFSET 11 -#define GLOBAL_LEARN_LIMIT_CTL_GOL_SA_LEARN_LIMIT_DROP_EN_BLEN 1 -#define GLOBAL_LEARN_LIMIT_CTL_GOL_SA_LEARN_LIMIT_DROP_EN_FLAG HSL_RW - -#define GOL_SA_LEARN_CNT -#define GLOBAL_LEARN_LIMIT_CTL_GOL_SA_LEARN_CNT_BOFFSET 0 -#define GLOBAL_LEARN_LIMIT_CTL_GOL_SA_LEARN_CNT_BLEN 11 -#define GLOBAL_LEARN_LIMIT_CTL_GOL_SA_LEARN_CNT_FLAG HSL_RW - - - - - /* DSCP To Priority Register */ -#define DSCP_TO_PRI -#define DSCP_TO_PRI_OFFSET 0x0630 -#define DSCP_TO_PRI_E_LENGTH 4 -#define DSCP_TO_PRI_E_OFFSET 0x0004 -#define DSCP_TO_PRI_NR_E 8 - - - - - /* UP To Priority Register */ -#define UP_TO_PRI -#define UP_TO_PRI_OFFSET 0x0650 -#define UP_TO_PRI_E_LENGTH 4 -#define UP_TO_PRI_E_OFFSET 0x0004 -#define UP_TO_PRI_NR_E 1 - - - - - /* Port Lookup control Register */ -#define PORT_LOOKUP_CTL -#define PORT_LOOKUP_CTL_OFFSET 0x0660 -#define PORT_LOOKUP_CTL_E_LENGTH 4 -#define PORT_LOOKUP_CTL_E_OFFSET 0x000c -#define PORT_LOOKUP_CTL_NR_E 7 - -#define MULTI_DROP_EN -#define PORT_LOOKUP_CTL_MULTI_DROP_EN_BOFFSET 31 -#define PORT_LOOKUP_CTL_MULTI_DROP_EN_BLEN 1 -#define PORT_LOOKUP_CTL_MULTI_DROP_EN_FLAG HSL_RW - -#define UNI_LEAKY_EN -#define PORT_LOOKUP_CTL_UNI_LEAKY_EN_BOFFSET 28 -#define PORT_LOOKUP_CTL_UNI_LEAKY_EN_BLEN 1 -#define PORT_LOOKUP_CTL_UNI_LEAKY_EN_FLAG HSL_RW - -#define MUL_LEAKY_EN -#define PORT_LOOKUP_CTL_MUL_LEAKY_EN_BOFFSET 27 -#define PORT_LOOKUP_CTL_MUL_LEAKY_EN_BLEN 1 -#define PORT_LOOKUP_CTL_MUL_LEAKY_EN_FLAG HSL_RW - -#define ARP_LEAKY_EN -#define PORT_LOOKUP_CTL_ARP_LEAKY_EN_BOFFSET 26 -#define PORT_LOOKUP_CTL_ARP_LEAKY_EN_BLEN 1 -#define PORT_LOOKUP_CTL_ARP_LEAKY_EN_FLAG HSL_RW - -#define ING_MIRROR_EN -#define PORT_LOOKUP_CTL_ING_MIRROR_EN_BOFFSET 25 -#define PORT_LOOKUP_CTL_ING_MIRROR_EN_BLEN 1 -#define PORT_LOOKUP_CTL_ING_MIRROR_EN_FLAG HSL_RW - -#define PORT_LOOP_BACK -#define PORT_LOOKUP_CTL_PORT_LOOP_BACK_BOFFSET 21 -#define PORT_LOOKUP_CTL_PORT_LOOP_BACK_BLEN 1 -#define PORT_LOOKUP_CTL_PORT_LOOP_BACK_FLAG HSL_RW - -#define LEARN_EN -#define PORT_LOOKUP_CTL_LEARN_EN_BOFFSET 20 -#define PORT_LOOKUP_CTL_LEARN_EN_BLEN 1 -#define PORT_LOOKUP_CTL_LEARN_EN_FLAG HSL_RW - -#define PORT_STATE -#define PORT_LOOKUP_CTL_PORT_STATE_BOFFSET 16 -#define PORT_LOOKUP_CTL_PORT_STATE_BLEN 3 -#define PORT_LOOKUP_CTL_PORT_STATE_FLAG HSL_RW - -#define FORCE_PVLAN -#define PORT_LOOKUP_CTL_FORCE_PVLAN_BOFFSET 10 -#define PORT_LOOKUP_CTL_FORCE_PVLAN_BLEN 1 -#define PORT_LOOKUP_CTL_FORCE_PVLAN_FLAG HSL_RW - -#define DOT1Q_MODE -#define PORT_LOOKUP_CTL_DOT1Q_MODE_BOFFSET 8 -#define PORT_LOOKUP_CTL_DOT1Q_MODE_BLEN 2 -#define PORT_LOOKUP_CTL_DOT1Q_MODE_FLAG HSL_RW - -#define PORT_VID_MEM -#define PORT_LOOKUP_CTL_PORT_VID_MEM_BOFFSET 0 -#define PORT_LOOKUP_CTL_PORT_VID_MEM_BLEN 7 -#define PORT_LOOKUP_CTL_PORT_VID_MEM_FLAG HSL_RW - - - - - /* Priority Control Register */ -#define PRI_CTL -#define PRI_CTL_OFFSET 0x0664 -#define PRI_CTL_E_LENGTH 4 -#define PRI_CTL_E_OFFSET 0x000c -#define PRI_CTL_NR_E 7 - -#define EG_MAC_BASE_VLAN_EN -#define PRI_CTL_EG_MAC_BASE_VLAN_EN_BOFFSET 20 -#define PRI_CTL_EG_MAC_BASE_VLAN_EN_BLEN 1 -#define PRI_CTL_EG_MAC_BASE_VLAN_EN_FLAG HSL_RW - -#define DA_PRI_EN -#define PRI_CTL_DA_PRI_EN_BOFFSET 18 -#define PRI_CTL_DA_PRI_EN_BLEN 1 -#define PRI_CTL_DA_PRI_EN_FLAG HSL_RW - -#define VLAN_PRI_EN -#define PRI_CTL_VLAN_PRI_EN_BOFFSET 17 -#define PRI_CTL_VLAN_PRI_EN_BLEN 1 -#define PRI_CTL_VLAN_PRI_EN_FLAG HSL_RW - -#define IP_PRI_EN -#define PRI_CTL_IP_PRI_EN_BOFFSET 16 -#define PRI_CTL_IP_PRI_EN_BLEN 1 -#define PRI_CTL_IP_PRI_EN_FLAG HSL_RW - -#define DA_PRI_SEL -#define PRI_CTL_DA_PRI_SEL_BOFFSET 6 -#define PRI_CTL_DA_PRI_SEL_BLEN 2 -#define PRI_CTL_DA_PRI_SEL_FLAG HSL_RW - -#define VLAN_PRI_SEL -#define PRI_CTL_VLAN_PRI_SEL_BOFFSET 4 -#define PRI_CTL_VLAN_PRI_SEL_BLEN 2 -#define PRI_CTL_VLAN_PRI_SEL_FLAG HSL_RW - -#define IP_PRI_SEL -#define PRI_CTL_IP_PRI_SEL_BOFFSET 2 -#define PRI_CTL_IP_PRI_SEL_BLEN 2 -#define PRI_CTL_IP_PRI_SEL_FLAG HSL_RW - - - - /* Port Learn Limit Ctl Register */ -#define PORT_LEARN_LIMIT_CTL -#define PORT_LEARN_LIMIT_CTL_OFFSET 0x0668 -#define PORT_LEARN_LIMIT_CTL_E_LENGTH 4 -#define PORT_LEARN_LIMIT_CTL_E_OFFSET 0x000c -#define PORT_LEARN_LIMIT_CTL_NR_E 7 - -#define IGMP_JOIN_LIMIT_EN -#define PORT_LEARN_LIMIT_CTL_IGMP_JOIN_LIMIT_EN_BOFFSET 27 -#define PORT_LEARN_LIMIT_CTL_IGMP_JOIN_LIMIT_EN_BLEN 1 -#define PORT_LEARN_LIMIT_CTL_IGMP_JOIN_LIMIT_EN_FLAG HSL_RW - -#define IGMP_JOIN_LIMIT_DROP_EN -#define PORT_LEARN_LIMIT_CTL_IGMP_JOIN_LIMIT_DROP_EN_BOFFSET 26 -#define PORT_LEARN_LIMIT_CTL_IGMP_JOIN_LIMIT_DROP_EN_BLEN 1 -#define PORT_LEARN_LIMIT_CTL_IGMP_JOIN_LIMIT_DROP_EN_FLAG HSL_RW - -#define IGMP_JOIN_CNT -#define PORT_LEARN_LIMIT_CTL_IGMP_JOIN_CNT_BOFFSET 16 -#define PORT_LEARN_LIMIT_CTL_IGMP_JOIN_CNT_BLEN 10 -#define PORT_LEARN_LIMIT_CTL_IGMP_JOIN_CNT_FLAG HSL_RW - -#define SA_LEARN_STATUS -#define PORT_LEARN_LIMIT_CTL_SA_LEARN_STATUS_BOFFSET 12 -#define PORT_LEARN_LIMIT_CTL_SA_LEARN_STATUS_BLEN 4 -#define PORT_LEARN_LIMIT_CTL_SA_LEARN_STATUS_FLAG HSL_RW - -#define SA_LEARN_LIMIT_EN -#define PORT_LEARN_LIMIT_CTL_SA_LEARN_LIMIT_EN_BOFFSET 11 -#define PORT_LEARN_LIMIT_CTL_SA_LEARN_LIMIT_EN_BLEN 1 -#define PORT_LEARN_LIMIT_CTL_SA_LEARN_LIMIT_EN_FLAG HSL_RW - -#define SA_LEARN_LIMIT_DROP_EN -#define PORT_LEARN_LIMIT_CTL_SA_LEARN_LIMIT_DROP_EN_BOFFSET 10 -#define PORT_LEARN_LIMIT_CTL_SA_LEARN_LIMIT_DROP_EN_BLEN 1 -#define PORT_LEARN_LIMIT_CTL_SA_LEARN_LIMIT_DROP_EN_FLAG HSL_RW - -#define SA_LEARN_CNT -#define PORT_LEARN_LIMIT_CTL_SA_LEARN_CNT_BOFFSET 0 -#define PORT_LEARN_LIMIT_CTL_SA_LEARN_CNT_BLEN 10 -#define PORT_LEARN_LIMIT_CTL_SA_LEARN_CNT_FLAG HSL_RW - - - - /* Global Trunk Ctl0 Register */ -#define GOL_TRUNK_CTL0 -#define GOL_TRUNK_CTL0_OFFSET 0x0700 -#define GOL_TRUNK_CTL0_E_LENGTH 4 -#define GOL_TRUNK_CTL0_E_OFFSET 0x4 -#define GOL_TRUNK_CTL0_NR_E 1 - - - /* Global Trunk Ctl1 Register */ -#define GOL_TRUNK_CTL1 -#define GOL_TRUNK_CTL1_OFFSET 0x0704 -#define GOL_TRUNK_CTL1_E_LENGTH 4 -#define GOL_TRUNK_CTL1_E_OFFSET 0x4 -#define GOL_TRUNK_CTL1_NR_E 2 - - - - - /* Port vlan0 Register */ -#define PORT_VLAN0 -#define PORT_VLAN0_OFFSET 0x0420 -#define PORT_VLAN0_E_LENGTH 4 -#define PORT_VLAN0_E_OFFSET 0x0008 -#define PORT_VLAN0_NR_E 7 - -#define ING_CPRI -#define PORT_VLAN0_ING_CPRI_BOFFSET 29 -#define PORT_VLAN0_ING_CPRI_BLEN 3 -#define PORT_VLAN0_ING_CPRI_FLAG HSL_RW - -#define DEF_CVID -#define PORT_VLAN0_DEF_CVID_BOFFSET 16 -#define PORT_VLAN0_DEF_CVID_BLEN 12 -#define PORT_VLAN0_DEF_CVID_FLAG HSL_RW - -#define ING_SPRI -#define PORT_VLAN0_ING_SPRI_BOFFSET 13 -#define PORT_VLAN0_ING_SPRI_BLEN 3 -#define PORT_VLAN0_ING_SPRI_FLAG HSL_RW - -#define DEF_SVID -#define PORT_VLAN0_DEF_SVID_BOFFSET 0 -#define PORT_VLAN0_DEF_SVID_BLEN 12 -#define PORT_VLAN0_DEF_SVID_FLAG HSL_RW - - /* Port vlan1 Register */ -#define PORT_VLAN1 -#define PORT_VLAN1_OFFSET 0x0424 -#define PORT_VLAN1_E_LENGTH 4 -#define PORT_VLAN1_E_OFFSET 0x0008 -#define PORT_VLAN1_NR_E 7 - -#define EG_VLAN_MODE -#define PORT_VLAN1_EG_VLAN_MODE_BOFFSET 12 -#define PORT_VLAN1_EG_VLAN_MODE_BLEN 2 -#define PORT_VLAN1_EG_VLAN_MODE_FLAG HSL_RW - -#define VLAN_DIS -#define PORT_VLAN1_VLAN_DIS_BOFFSET 11 -#define PORT_VLAN1_VLAN_DIS_BLEN 1 -#define PORT_VLAN1_VLAN_DIS_FLAG HSL_RW - -#define SP_CHECK_EN -#define PORT_VLAN1_SP_CHECK_EN_BOFFSET 10 -#define PORT_VLAN1_SP_CHECK_EN_BLEN 1 -#define PORT_VLAN1_SP_CHECK_EN_FLAG HSL_RW - -#define COREP_EN -#define PORT_VLAN1_COREP_EN_BOFFSET 9 -#define PORT_VLAN1_COREP_EN_BLEN 1 -#define PORT_VLAN1_COREP_EN_FLAG HSL_RW - -#define FORCE_DEF_VID -#define PORT_VLAN1_FORCE_DEF_VID_BOFFSET 8 -#define PORT_VLAN1_FORCE_DEF_VID_BLEN 1 -#define PORT_VLAN1_FORCE_DEF_VID_FLAG HSL_RW - -#define TLS_EN -#define PORT_VLAN1_TLS_EN_BOFFSET 7 -#define PORT_VLAN1_TLS_EN_BLEN 1 -#define PORT_VLAN1_TLS_EN_FLAG HSL_RW - -#define PROPAGATION_EN -#define PORT_VLAN1_PROPAGATION_EN_BOFFSET 6 -#define PORT_VLAN1_PROPAGATION_EN_BLEN 1 -#define PORT_VLAN1_PROPAGATION_EN_FLAG HSL_RW - -#define CLONE -#define PORT_VLAN1_CLONE_BOFFSET 5 -#define PORT_VLAN1_CLONE_BLEN 1 -#define PORT_VLAN1_CLONE_FLAG HSL_RW - -#define PRI_PROPAGATION -#define PORT_VLAN1_PRI_PROPAGATION_BOFFSET 4 -#define PORT_VLAN1_PRI_PROPAGATION_BLEN 1 -#define PORT_VLAN1_VLAN_PRI_PROPAGATION_FLAG HSL_RW - -#define IN_VLAN_MODE -#define PORT_VLAN1_IN_VLAN_MODE_BOFFSET 2 -#define PORT_VLAN1_IN_VLAN_MODE_BLEN 2 -#define PORT_VLAN1_IN_VLAN_MODE_FLAG HSL_RW - - - /* Route Default VID Register */ -#define ROUTER_DEFV -#define ROUTER_DEFV_OFFSET 0x0c70 -#define ROUTER_DEFV_E_LENGTH 4 -#define ROUTER_DEFV_E_OFFSET 0x0004 -#define ROUTER_DEFV_NR_E 4 - - - /* Route Egress VLAN Mode Register */ -#define ROUTER_EG -#define ROUTER_EG_OFFSET 0x0c80 -#define ROUTER_EG_E_LENGTH 4 -#define ROUTER_EG_E_OFFSET 0x0004 -#define ROUTER_EG_NR_E 1 - - - - - /* Mdio control Register */ -#define MDIO_CTRL "mctrl" -#define MDIO_CTRL_ID 24 -#define MDIO_CTRL_OFFSET 0x0098 -#define MDIO_CTRL_E_LENGTH 4 -#define MDIO_CTRL_E_OFFSET 0 -#define MDIO_CTRL_NR_E 1 - -#define MSTER_EN "mctrl_msteren" -#define MDIO_CTRL_MSTER_EN_BOFFSET 30 -#define MDIO_CTRL_MSTER_EN_BLEN 1 -#define MDIO_CTRL_MSTER_EN_FLAG HSL_RW - -#define MSTER_EN "mctrl_msteren" -#define MDIO_CTRL_MSTER_EN_BOFFSET 30 -#define MDIO_CTRL_MSTER_EN_BLEN 1 -#define MDIO_CTRL_MSTER_EN_FLAG HSL_RW - -#define CMD "mctrl_cmd" -#define MDIO_CTRL_CMD_BOFFSET 27 -#define MDIO_CTRL_CMD_BLEN 1 -#define MDIO_CTRL_CMD_FLAG HSL_RW - -#define SUP_PRE "mctrl_spre" -#define MDIO_CTRL_SUP_PRE_BOFFSET 26 -#define MDIO_CTRL_SUP_PRE_BLEN 1 -#define MDIO_CTRL_SUP_PRE_FLAG HSL_RW - -#define PHY_ADDR "mctrl_phyaddr" -#define MDIO_CTRL_PHY_ADDR_BOFFSET 21 -#define MDIO_CTRL_PHY_ADDR_BLEN 5 -#define MDIO_CTRL_PHY_ADDR_FLAG HSL_RW - -#define REG_ADDR "mctrl_regaddr" -#define MDIO_CTRL_REG_ADDR_BOFFSET 16 -#define MDIO_CTRL_REG_ADDR_BLEN 5 -#define MDIO_CTRL_REG_ADDR_FLAG HSL_RW - -#define DATA "mctrl_data" -#define MDIO_CTRL_DATA_BOFFSET 0 -#define MDIO_CTRL_DATA_BLEN 16 -#define MDIO_CTRL_DATA_FLAG HSL_RW - - - - - /* BIST control Register */ -#define BIST_CTRL "bctrl" -#define BIST_CTRL_ID 24 -#define BIST_CTRL_OFFSET 0x00a0 -#define BIST_CTRL_E_LENGTH 4 -#define BIST_CTRL_E_OFFSET 0 -#define BIST_CTRL_NR_E 1 - -#define BIST_BUSY "bctrl_bb" -#define BIST_CTRL_BIST_BUSY_BOFFSET 31 -#define BIST_CTRL_BIST_BUSY_BLEN 1 -#define BIST_CTRL_BIST_BUSY_FLAG HSL_RW - -#define ONE_ERR "bctrl_oe" -#define BIST_CTRL_ONE_ERR_BOFFSET 30 -#define BIST_CTRL_ONE_ERR_BLEN 1 -#define BIST_CTRL_ONE_ERR_FLAG HSL_RO - -#define ERR_MEM "bctrl_em" -#define BIST_CTRL_ERR_MEM_BOFFSET 24 -#define BIST_CTRL_ERR_MEM_BLEN 4 -#define BIST_CTRL_ERR_MEM_FLAG HSL_RO - -#define PTN_EN2 "bctrl_pe2" -#define BIST_CTRL_PTN_EN2_BOFFSET 22 -#define BIST_CTRL_PTN_EN2_BLEN 1 -#define BIST_CTRL_PTN_EN2_FLAG HSL_RW - -#define PTN_EN1 "bctrl_pe1" -#define BIST_CTRL_PTN_EN1_BOFFSET 21 -#define BIST_CTRL_PTN_EN1_BLEN 1 -#define BIST_CTRL_PTN_EN1_FLAG HSL_RW - -#define PTN_EN0 "bctrl_pe0" -#define BIST_CTRL_PTN_EN0_BOFFSET 20 -#define BIST_CTRL_PTN_EN0_BLEN 1 -#define BIST_CTRL_PTN_EN0_FLAG HSL_RW - -#define ERR_PTN "bctrl_ep" -#define BIST_CTRL_ERR_PTN_BOFFSET 16 -#define BIST_CTRL_ERR_PTN_BLEN 2 -#define BIST_CTRL_ERR_PTN_FLAG HSL_RO - -#define ERR_CNT "bctrl_ec" -#define BIST_CTRL_ERR_CNT_BOFFSET 13 -#define BIST_CTRL_ERR_CNT_BLEN 2 -#define BIST_CTRL_ERR_CNT_FLAG HSL_RO - -#define ERR_ADDR "bctrl_ea" -#define BIST_CTRL_ERR_ADDR_BOFFSET 0 -#define BIST_CTRL_ERR_ADDR_BLEN 12 -#define BIST_CTRL_ERR_ADDR_FLAG HSL_RO - - - - - /* BIST recover Register */ -#define BIST_RCV "brcv" -#define BIST_RCV_ID 24 -#define BIST_RCV_OFFSET 0x00a4 -#define BIST_RCV_E_LENGTH 4 -#define BIST_RCV_E_OFFSET 0 -#define BIST_RCV_NR_E 1 - -#define RCV_EN "brcv_en" -#define BIST_RCV_RCV_EN_BOFFSET 31 -#define BIST_RCV_RCV_EN_BLEN 1 -#define BIST_RCV_RCV_EN_FLAG HSL_RW - -#define RCV_ADDR "brcv_addr" -#define BIST_RCV_RCV_ADDR_BOFFSET 0 -#define BIST_RCV_RCV_ADDR_BLEN 12 -#define BIST_RCV_RCV_ADDR_FLAG HSL_RW - - - - - /* LED control Register */ -#define LED_CTRL "ledctrl" -#define LED_CTRL_ID 25 -#define LED_CTRL_OFFSET 0x0050 -#define LED_CTRL_E_LENGTH 4 -#define LED_CTRL_E_OFFSET 0 -#define LED_CTRL_NR_E 3 - -#define PATTERN_EN "lctrl_pen" -#define LED_CTRL_PATTERN_EN_BOFFSET 14 -#define LED_CTRL_PATTERN_EN_BLEN 2 -#define LED_CTRL_PATTERN_EN_FLAG HSL_RW - -#define FULL_LIGHT_EN "lctrl_fen" -#define LED_CTRL_FULL_LIGHT_EN_BOFFSET 13 -#define LED_CTRL_FULL_LIGHT_EN_BLEN 1 -#define LED_CTRL_FULL_LIGHT_EN_FLAG HSL_RW - -#define HALF_LIGHT_EN "lctrl_hen" -#define LED_CTRL_HALF_LIGHT_EN_BOFFSET 12 -#define LED_CTRL_HALF_LIGHT_EN_BLEN 1 -#define LED_CTRL_HALF_LIGHT_EN_FLAG HSL_RW - -#define POWERON_LIGHT_EN "lctrl_poen" -#define LED_CTRL_POWERON_LIGHT_EN_BOFFSET 11 -#define LED_CTRL_POWERON_LIGHT_EN_BLEN 1 -#define LED_CTRL_POWERON_LIGHT_EN_FLAG HSL_RW - -#define GE_LIGHT_EN "lctrl_geen" -#define LED_CTRL_GE_LIGHT_EN_BOFFSET 10 -#define LED_CTRL_GE_LIGHT_EN_BLEN 1 -#define LED_CTRL_GE_LIGHT_EN_FLAG HSL_RW - -#define FE_LIGHT_EN "lctrl_feen" -#define LED_CTRL_FE_LIGHT_EN_BOFFSET 9 -#define LED_CTRL_FE_LIGHT_EN_BLEN 1 -#define LED_CTRL_FE_LIGHT_EN_FLAG HSL_RW - -#define ETH_LIGHT_EN "lctrl_ethen" -#define LED_CTRL_ETH_LIGHT_EN_BOFFSET 8 -#define LED_CTRL_ETH_LIGHT_EN_BLEN 1 -#define LED_CTRL_ETH_LIGHT_EN_FLAG HSL_RW - -#define COL_BLINK_EN "lctrl_cen" -#define LED_CTRL_COL_BLINK_EN_BOFFSET 7 -#define LED_CTRL_COL_BLINK_EN_BLEN 1 -#define LED_CTRL_COL_BLINK_EN_FLAG HSL_RW - -#define RX_BLINK_EN "lctrl_rxen" -#define LED_CTRL_RX_BLINK_EN_BOFFSET 5 -#define LED_CTRL_RX_BLINK_EN_BLEN 1 -#define LED_CTRL_RX_BLINK_EN_FLAG HSL_RW - -#define TX_BLINK_EN "lctrl_txen" -#define LED_CTRL_TX_BLINK_EN_BOFFSET 4 -#define LED_CTRL_TX_BLINK_EN_BLEN 1 -#define LED_CTRL_TX_BLINK_EN_FLAG HSL_RW - -#define LINKUP_OVER_EN "lctrl_loen" -#define LED_CTRL_LINKUP_OVER_EN_BOFFSET 2 -#define LED_CTRL_LINKUP_OVER_EN_BLEN 1 -#define LED_CTRL_LINKUP_OVER_EN_FLAG HSL_RW - -#define BLINK_FREQ "lctrl_bfreq" -#define LED_CTRL_BLINK_FREQ_BOFFSET 0 -#define LED_CTRL_BLINK_FREQ_BLEN 2 -#define LED_CTRL_BLINK_FREQ_FLAG HSL_RW - - /* LED control Register */ -#define LED_PATTERN "ledpatten" -#define LED_PATTERN_ID 25 -#define LED_PATTERN_OFFSET 0x005c -#define LED_PATTERN_E_LENGTH 4 -#define LED_PATTERN_E_OFFSET 0 -#define LED_PATTERN_NR_E 1 - - -#define P3L2_MODE -#define LED_PATTERN_P3L2_MODE_BOFFSET 24 -#define LED_PATTERN_P3L2_MODE_BLEN 2 -#define LED_PATTERN_P3L2_MODE_FLAG HSL_RW - -#define P3L1_MODE -#define LED_PATTERN_P3L1_MODE_BOFFSET 22 -#define LED_PATTERN_P3L1_MODE_BLEN 2 -#define LED_PATTERN_P3L1_MODE_FLAG HSL_RW - -#define P3L0_MODE -#define LED_PATTERN_P3L0_MODE_BOFFSET 20 -#define LED_PATTERN_P3L0_MODE_BLEN 2 -#define LED_PATTERN_P3L0_MODE_FLAG HSL_RW - -#define P2L2_MODE -#define LED_PATTERN_P2L2_MODE_BOFFSET 18 -#define LED_PATTERN_P2L2_MODE_BLEN 2 -#define LED_PATTERN_P2L2_MODE_FLAG HSL_RW - -#define P2L1_MODE -#define LED_PATTERN_P2L1_MODE_BOFFSET 16 -#define LED_PATTERN_P2L1_MODE_BLEN 2 -#define LED_PATTERN_P2L1_MODE_FLAG HSL_RW - -#define P2L0_MODE -#define LED_PATTERN_P2L0_MODE_BOFFSET 14 -#define LED_PATTERN_P2L0_MODE_BLEN 2 -#define LED_PATTERN_P2L0_MODE_FLAG HSL_RW - -#define P1L2_MODE -#define LED_PATTERN_P1L2_MODE_BOFFSET 12 -#define LED_PATTERN_P1L2_MODE_BLEN 2 -#define LED_PATTERN_P1L2_MODE_FLAG HSL_RW - -#define P1L1_MODE -#define LED_PATTERN_P1L1_MODE_BOFFSET 10 -#define LED_PATTERN_P1L1_MODE_BLEN 2 -#define LED_PATTERN_P1L1_MODE_FLAG HSL_RW - -#define P1L0_MODE -#define LED_PATTERN_P1L0_MODE_BOFFSET 8 -#define LED_PATTERN_P1L0_MODE_BLEN 2 -#define LED_PATTERN_P1L0_MODE_FLAG HSL_RW - - - - - /* Pri To Queue Register */ -#define PRI_TO_QUEUE -#define PRI_TO_QUEUE_OFFSET 0x0814 -#define PRI_TO_QUEUE_E_LENGTH 4 -#define PRI_TO_QUEUE_E_OFFSET 0x0004 -#define PRI_TO_QUEUE_NR_E 1 - - - - - /* Pri To EhQueue Register */ -#define PRI_TO_EHQUEUE -#define PRI_TO_EHQUEUE_OFFSET 0x0810 -#define PRI_TO_EHQUEUE_E_LENGTH 4 -#define PRI_TO_EHQUEUE_E_OFFSET 0x0004 -#define PRI_TO_EHQUEUE_NR_E 1 - - - - - /* Port HOL CTL0 Register */ -#define PORT_HOL_CTL0 -#define PORT_HOL_CTL0_OFFSET 0x0970 -#define PORT_HOL_CTL0_E_LENGTH 4 -#define PORT_HOL_CTL0_E_OFFSET 0x0008 -#define PORT_HOL_CTL0_NR_E 7 - -#define PORT_DESC_NR -#define PORT_HOL_CTL0_PORT_DESC_NR_BOFFSET 24 -#define PORT_HOL_CTL0_PORT_DESC_NR_BLEN 6 -#define PORT_HOL_CTL0_PORT_DESC_NR_FLAG HSL_RW - -#define QUEUE5_DESC_NR -#define PORT_HOL_CTL0_QUEUE5_DESC_NR_BOFFSET 20 -#define PORT_HOL_CTL0_QUEUE5_DESC_NR_BLEN 4 -#define PORT_HOL_CTL0_QUEUE5_DESC_NR_FLAG HSL_RW - -#define QUEUE4_DESC_NR -#define PORT_HOL_CTL0_QUEUE4_DESC_NR_BOFFSET 16 -#define PORT_HOL_CTL0_QUEUE4_DESC_NR_BLEN 4 -#define PORT_HOL_CTL0_QUEUE4_DESC_NR_FLAG HSL_RW - -#define QUEUE3_DESC_NR -#define PORT_HOL_CTL0_QUEUE3_DESC_NR_BOFFSET 12 -#define PORT_HOL_CTL0_QUEUE3_DESC_NR_BLEN 4 -#define PORT_HOL_CTL0_QUEUE3_DESC_NR_FLAG HSL_RW - -#define QUEUE2_DESC_NR -#define PORT_HOL_CTL0_QUEUE2_DESC_NR_BOFFSET 8 -#define PORT_HOL_CTL0_QUEUE2_DESC_NR_BLEN 4 -#define PORT_HOL_CTL0_QUEUE2_DESC_NR_FLAG HSL_RW - -#define QUEUE1_DESC_NR -#define PORT_HOL_CTL0_QUEUE1_DESC_NR_BOFFSET 4 -#define PORT_HOL_CTL0_QUEUE1_DESC_NR_BLEN 4 -#define PORT_HOL_CTL0_QUEUE1_DESC_NR_FLAG HSL_RW - -#define QUEUE0_DESC_NR -#define PORT_HOL_CTL0_QUEUE0_DESC_NR_BOFFSET 0 -#define PORT_HOL_CTL0_QUEUE0_DESC_NR_BLEN 4 -#define PORT_HOL_CTL0_QUEUE0_DESC_NR_FLAG HSL_RW - - /* Port HOL CTL1 Register */ -#define PORT_HOL_CTL1 -#define PORT_HOL_CTL1_OFFSET 0x0974 -#define PORT_HOL_CTL1_E_LENGTH 4 -#define PORT_HOL_CTL1_E_OFFSET 0x0008 -#define PORT_HOL_CTL1_NR_E 7 - -#define EG_MIRROR_EN -#define PORT_HOL_CTL1_EG_MIRROR_EN_BOFFSET 16 -#define PORT_HOL_CTL1_EG_MIRROR_EN_BLEN 1 -#define PORT_HOL_CTL1_EG_MIRROR_EN_FLAG HSL_RW - -#define PORT_DESC_EN -#define PORT_HOL_CTL1_PORT_DESC_EN_BOFFSET 7 -#define PORT_HOL_CTL1_PORT_DESC_EN_BLEN 1 -#define PORT_HOL_CTL1_PORT_DESC_EN_FLAG HSL_RW - -#define QUEUE_DESC_EN -#define PORT_HOL_CTL1_QUEUE_DESC_EN_BOFFSET 6 -#define PORT_HOL_CTL1_QUEUE_DESC_EN_BLEN 1 -#define PORT_HOL_CTL1_QUEUE_DESC_EN_FLAG HSL_RW - -#define PORT_IN_DESC_EN -#define PORT_HOL_CTL1_PORT_IN_DESC_EN_BOFFSET 0 -#define PORT_HOL_CTL1_PORT_IN_DESC_EN_BLEN 4 -#define PORT_HOL_CTL1_PORT_IN_DESC_EN_FLAG HSL_RW - - /* PORT FLOW CTRL THRESHOLD REGISTER */ -#define PORT_FLOW_CTRL_THRESHOLD -#define PORT_FLOW_CTRL_THRESHOLD_OFFSET 0x09B0 -#define PORT_FLOW_CTRL_THRESHOLD_E_LENGTH 4 -#define PORT_FLOW_CTRL_THRESHOLD_E_OFFSET 0x0004 -#define PORT_FLOW_CTRL_THRESHOLD_NR_E 7 - -#define XON_THRES -#define PORT_FLOW_CTRL_THRESHOLD_XON_THRES_BOFFSET 16 -#define PORT_FLOW_CTRL_THRESHOLD_XON_THRES_BLEN 8 -#define PORT_FLOW_CTRL_THRESHOLD_XON_THRES_FLAG HSL_RW - -#define XOFF_THRES -#define PORT_FLOW_CTRL_THRESHOLD_XOFF_THRES_BOFFSET 0 -#define PORT_FLOW_CTRL_THRESHOLD_XOFF_THRES_BLEN 8 -#define PORT_FLOW_CTRL_THRESHOLD_XOFF_THRES_FLAG HSL_RW - - /* Port Rate Limit0 Register */ -#define RATE_LIMIT0 "rlmt0" -#define RATE_LIMIT0_ID 32 -#define RATE_LIMIT0_OFFSET 0x0110 -#define RATE_LIMIT0_E_LENGTH 4 -#define RATE_LIMIT0_E_OFFSET 0x0100 -#define RATE_LIMIT0_NR_E 7 - - -#define EG_RATE_EN "rlmt_egen" -#define RATE_LIMIT0_EG_RATE_EN_BOFFSET 23 -#define RATE_LIMIT0_EG_RATE_EN_BLEN 1 -#define RATE_LIMIT0_EG_RATE_EN_FLAG HSL_RW - -#define EG_MNG_RATE_EN "rlmt_egmngen" -#define RATE_LIMIT0_EG_MNG_RATE_EN_BOFFSET 22 -#define RATE_LIMIT0_EG_MNG_RATE_EN_BLEN 1 -#define RATE_LIMIT0_EG_MNG_RATE_EN_FLAG HSL_RW - -#define IN_MNG_RATE_EN "rlmt_inmngen" -#define RATE_LIMIT0_IN_MNG_RATE_EN_BOFFSET 21 -#define RATE_LIMIT0_IN_MNG_RATE_EN_BLEN 1 -#define RATE_LIMIT0_IN_MNG_RATE_EN_FLAG HSL_RW - -#define IN_MUL_RATE_EN "rlmt_inmulen" -#define RATE_LIMIT0_IN_MUL_RATE_EN_BOFFSET 20 -#define RATE_LIMIT0_IN_MUL_RATE_EN_BLEN 1 -#define RATE_LIMIT0_IN_MUL_RATE_EN_FLAG HSL_RW - -#define ING_RATE "rlmt_ingrate" -#define RATE_LIMIT0_ING_RATE_BOFFSET 0 -#define RATE_LIMIT0_ING_RATE_BLEN 15 -#define RATE_LIMIT0_ING_RATE_FLAG HSL_RW - - - - - - - - - - - /* mib memory info */ -#define MIB_RXBROAD -#define MIB_RXBROAD_OFFSET 0x01000 -#define MIB_RXBROAD_E_LENGTH 4 -#define MIB_RXBROAD_E_OFFSET 0x100 -#define MIB_RXBROAD_NR_E 7 - -#define MIB_RXPAUSE -#define MIB_RXPAUSE_OFFSET 0x01004 -#define MIB_RXPAUSE_E_LENGTH 4 -#define MIB_RXPAUSE_E_OFFSET 0x100 -#define MIB_RXPAUSE_NR_E 7 - -#define MIB_RXMULTI -#define MIB_RXMULTI_OFFSET 0x01008 -#define MIB_RXMULTI_E_LENGTH 4 -#define MIB_RXMULTI_E_OFFSET 0x100 -#define MIB_RXMULTI_NR_E 7 - -#define MIB_RXFCSERR -#define MIB_RXFCSERR_OFFSET 0x0100c -#define MIB_RXFCSERR_E_LENGTH 4 -#define MIB_RXFCSERR_E_OFFSET 0x100 -#define MIB_RXFCSERR_NR_E 7 - -#define MIB_RXALLIGNERR -#define MIB_RXALLIGNERR_OFFSET 0x01010 -#define MIB_RXALLIGNERR_E_LENGTH 4 -#define MIB_RXALLIGNERR_E_OFFSET 0x100 -#define MIB_RXALLIGNERR_NR_E 7 - -#define MIB_RXRUNT -#define MIB_RXRUNT_OFFSET 0x01014 -#define MIB_RXRUNT_E_LENGTH 4 -#define MIB_RXRUNT_E_OFFSET 0x100 -#define MIB_RXRUNT_NR_E 7 - -#define MIB_RXFRAGMENT -#define MIB_RXFRAGMENT_OFFSET 0x01018 -#define MIB_RXFRAGMENT_E_LENGTH 4 -#define MIB_RXFRAGMENT_E_OFFSET 0x100 -#define MIB_RXFRAGMENT_NR_E 7 - -#define MIB_RX64BYTE -#define MIB_RX64BYTE_OFFSET 0x0101c -#define MIB_RX64BYTE_E_LENGTH 4 -#define MIB_RX64BYTE_E_OFFSET 0x100 -#define MIB_RX64BYTE_NR_E 7 - -#define MIB_RX128BYTE -#define MIB_RX128BYTE_OFFSET 0x01020 -#define MIB_RX128BYTE_E_LENGTH 4 -#define MIB_RX128BYTE_E_OFFSET 0x100 -#define MIB_RX128BYTE_NR_E 7 - -#define MIB_RX256BYTE -#define MIB_RX256BYTE_OFFSET 0x01024 -#define MIB_RX256BYTE_E_LENGTH 4 -#define MIB_RX256BYTE_E_OFFSET 0x100 -#define MIB_RX256BYTE_NR_E 7 - -#define MIB_RX512BYTE -#define MIB_RX512BYTE_OFFSET 0x01028 -#define MIB_RX512BYTE_E_LENGTH 4 -#define MIB_RX512BYTE_E_OFFSET 0x100 -#define MIB_RX512BYTE_NR_E 7 - -#define MIB_RX1024BYTE -#define MIB_RX1024BYTE_OFFSET 0x0102c -#define MIB_RX1024BYTE_E_LENGTH 4 -#define MIB_RX1024BYTE_E_OFFSET 0x100 -#define MIB_RX1024BYTE_NR_E 7 - -#define MIB_RX1518BYTE -#define MIB_RX1518BYTE_OFFSET 0x01030 -#define MIB_RX1518BYTE_E_LENGTH 4 -#define MIB_RX1518BYTE_E_OFFSET 0x100 -#define MIB_RX1518BYTE_NR_E 7 - -#define MIB_RXMAXBYTE -#define MIB_RXMAXBYTE_OFFSET 0x01034 -#define MIB_RXMAXBYTE_E_LENGTH 4 -#define MIB_RXMAXBYTE_E_OFFSET 0x100 -#define MIB_RXMAXBYTE_NR_E 7 - -#define MIB_RXTOOLONG -#define MIB_RXTOOLONG_OFFSET 0x01038 -#define MIB_RXTOOLONG_E_LENGTH 4 -#define MIB_RXTOOLONG_E_OFFSET 0x100 -#define MIB_RXTOOLONG_NR_E 7 - -#define MIB_RXGOODBYTE_LO -#define MIB_RXGOODBYTE_LO_OFFSET 0x0103c -#define MIB_RXGOODBYTE_LO_E_LENGTH 4 -#define MIB_RXGOODBYTE_LO_E_OFFSET 0x100 -#define MIB_RXGOODBYTE_LO_NR_E 7 - -#define MIB_RXGOODBYTE_HI -#define MIB_RXGOODBYTE_HI_OFFSET 0x01040 -#define MIB_RXGOODBYTE_HI_E_LENGTH 4 -#define MIB_RXGOODBYTE_HI_E_OFFSET 0x100 -#define MIB_RXGOODBYTE_HI_NR_E 7 - -#define MIB_RXBADBYTE_LO -#define MIB_RXBADBYTE_LO_OFFSET 0x01044 -#define MIB_RXBADBYTE_LO_E_LENGTH 4 -#define MIB_RXBADBYTE_LO_E_OFFSET 0x100 -#define MIB_RXBADBYTE_LO_NR_E 7 - -#define MIB_RXBADBYTE_HI -#define MIB_RXBADBYTE_HI_OFFSET 0x01048 -#define MIB_RXBADBYTE_HI_E_LENGTH 4 -#define MIB_RXBADBYTE_HI_E_OFFSET 0x100 -#define MIB_RXBADBYTE_HI_NR_E 7 - -#define MIB_RXOVERFLOW -#define MIB_RXOVERFLOW_OFFSET 0x0104c -#define MIB_RXOVERFLOW_E_LENGTH 4 -#define MIB_RXOVERFLOW_E_OFFSET 0x100 -#define MIB_RXOVERFLOW_NR_E 7 - -#define MIB_FILTERED -#define MIB_FILTERED_OFFSET 0x01050 -#define MIB_FILTERED_E_LENGTH 4 -#define MIB_FILTERED_E_OFFSET 0x100 -#define MIB_FILTERED_NR_E 7 - -#define MIB_TXBROAD -#define MIB_TXBROAD_OFFSET 0x01054 -#define MIB_TXBROAD_E_LENGTH 4 -#define MIB_TXBROAD_E_OFFSET 0x100 -#define MIB_TXBROAD_NR_E 7 - -#define MIB_TXPAUSE -#define MIB_TXPAUSE_OFFSET 0x01058 -#define MIB_TXPAUSE_E_LENGTH 4 -#define MIB_TXPAUSE_E_OFFSET 0x100 -#define MIB_TXPAUSE_NR_E 7 - -#define MIB_TXMULTI -#define MIB_TXMULTI_OFFSET 0x0105c -#define MIB_TXMULTI_E_LENGTH 4 -#define MIB_TXMULTI_E_OFFSET 0x100 -#define MIB_TXMULTI_NR_E 7 - -#define MIB_TXUNDERRUN -#define MIB_TXUNDERRUN_OFFSET 0x01060 -#define MIB_TXUNDERRUN_E_LENGTH 4 -#define MIB_TXUNDERRUN_E_OFFSET 0x100 -#define MIB_TXUNDERRUN_NR_E 7 - -#define MIB_TX64BYTE -#define MIB_TX64BYTE_OFFSET 0x01064 -#define MIB_TX64BYTE_E_LENGTH 4 -#define MIB_TX64BYTE_E_OFFSET 0x100 -#define MIB_TX64BYTE_NR_E 7 - -#define MIB_TX128BYTE -#define MIB_TX128BYTE_OFFSET 0x01068 -#define MIB_TX128BYTE_E_LENGTH 4 -#define MIB_TX128BYTE_E_OFFSET 0x100 -#define MIB_TX128BYTE_NR_E 7 - -#define MIB_TX256BYTE -#define MIB_TX256BYTE_OFFSET 0x0106c -#define MIB_TX256BYTE_E_LENGTH 4 -#define MIB_TX256BYTE_E_OFFSET 0x100 -#define MIB_TX256BYTE_NR_E 7 - -#define MIB_TX512BYTE -#define MIB_TX512BYTE_OFFSET 0x01070 -#define MIB_TX512BYTE_E_LENGTH 4 -#define MIB_TX512BYTE_E_OFFSET 0x100 -#define MIB_TX512BYTE_NR_E 7 - -#define MIB_TX1024BYTE -#define MIB_TX1024BYTE_OFFSET 0x01074 -#define MIB_TX1024BYTE_E_LENGTH 4 -#define MIB_TX1024BYTE_E_OFFSET 0x100 -#define MIB_TX1024BYTE_NR_E 7 - -#define MIB_TX1518BYTE -#define MIB_TX1518BYTE_OFFSET 0x01078 -#define MIB_TX1518BYTE_E_LENGTH 4 -#define MIB_TX1518BYTE_E_OFFSET 0x100 -#define MIB_TX1518BYTE_NR_E 7 - -#define MIB_TXMAXBYTE -#define MIB_TXMAXBYTE_OFFSET 0x0107c -#define MIB_TXMAXBYTE_E_LENGTH 4 -#define MIB_TXMAXBYTE_E_OFFSET 0x100 -#define MIB_TXMAXBYTE_NR_E 7 - -#define MIB_TXOVERSIZE -#define MIB_TXOVERSIZE_OFFSET 0x01080 -#define MIB_TXOVERSIZE_E_LENGTH 4 -#define MIB_TXOVERSIZE_E_OFFSET 0x100 -#define MIB_TXOVERSIZE_NR_E 7 - -#define MIB_TXBYTE_LO -#define MIB_TXBYTE_LO_OFFSET 0x01084 -#define MIB_TXBYTE_LO_E_LENGTH 4 -#define MIB_TXBYTE_LO_E_OFFSET 0x100 -#define MIB_TXBYTE_LO_NR_E 7 - -#define MIB_TXBYTE_HI -#define MIB_TXBYTE_HI_OFFSET 0x01088 -#define MIB_TXBYTE_HI_E_LENGTH 4 -#define MIB_TXBYTE_HI_E_OFFSET 0x100 -#define MIB_TXBYTE_HI_NR_E 7 - -#define MIB_TXCOLLISION -#define MIB_TXCOLLISION_OFFSET 0x0108c -#define MIB_TXCOLLISION_E_LENGTH 4 -#define MIB_TXCOLLISION_E_OFFSET 0x100 -#define MIB_TXCOLLISION_NR_E 7 - -#define MIB_TXABORTCOL -#define MIB_TXABORTCOL_OFFSET 0x01090 -#define MIB_TXABORTCOL_E_LENGTH 4 -#define MIB_TXABORTCOL_E_OFFSET 0x100 -#define MIB_TXABORTCOL_NR_E 7 - -#define MIB_TXMULTICOL -#define MIB_TXMULTICOL_OFFSET 0x01094 -#define MIB_TXMULTICOL_E_LENGTH 4 -#define MIB_TXMULTICOL_E_OFFSET 0x100 -#define MIB_TXMULTICOL_NR_E 7 - -#define MIB_TXSINGALCOL -#define MIB_TXSINGALCOL_OFFSET 0x01098 -#define MIB_TXSINGALCOL_E_LENGTH 4 -#define MIB_TXSINGALCOL_E_OFFSET 0x100 -#define MIB_TXSINGALCOL_NR_E 7 - -#define MIB_TXEXCDEFER -#define MIB_TXEXCDEFER_OFFSET 0x0109c -#define MIB_TXEXCDEFER_E_LENGTH 4 -#define MIB_TXEXCDEFER_E_OFFSET 0x100 -#define MIB_TXEXCDEFER_NR_E 7 - -#define MIB_TXDEFER -#define MIB_TXDEFER_OFFSET 0x010a0 -#define MIB_TXDEFER_E_LENGTH 4 -#define MIB_TXDEFER_E_OFFSET 0x100 -#define MIB_TXDEFER_NR_E 7 - -#define MIB_TXLATECOL -#define MIB_TXLATECOL_OFFSET 0x010a4 -#define MIB_TXLATECOL_E_LENGTH 4 -#define MIB_TXLATECOL_E_OFFSET 0x100 -#define MIB_TXLATECOL_NR_E 7 - - - - /* ACL Action Register */ -#define ACL_RSLT0 10 -#define ACL_RSLT0_OFFSET 0x5a000 -#define ACL_RSLT0_E_LENGTH 4 -#define ACL_RSLT0_E_OFFSET 0x10 -#define ACL_RSLT0_NR_E 96 - -#define CTAGPRI -#define ACL_RSLT0_CTAGPRI_BOFFSET 29 -#define ACL_RSLT0_CTAGPRI_BLEN 3 -#define ACL_RSLT0_CTAGPRI_FLAG HSL_RW - -#define CTAGCFI -#define ACL_RSLT0_CTAGCFI_BOFFSET 28 -#define ACL_RSLT0_CTAGCFI_BLEN 1 -#define ACL_RSLT0_CTAGCFI_FLAG HSL_RW - -#define CTAGVID -#define ACL_RSLT0_CTAGVID_BOFFSET 16 -#define ACL_RSLT0_CTAGVID_BLEN 12 -#define ACL_RSLT0_CTAGVID_FLAG HSL_RW - -#define STAGPRI -#define ACL_RSLT0_STAGPRI_BOFFSET 13 -#define ACL_RSLT0_STAGPRI_BLEN 3 -#define ACL_RSLT0_STAGPRI_FLAG HSL_RW - -#define STAGDEI -#define ACL_RSLT0_STAGDEI_BOFFSET 12 -#define ACL_RSLT0_STAGDEI_BLEN 1 -#define ACL_RSLT0_STAGDEI_FLAG HSL_RW - -#define STAGVID -#define ACL_RSLT0_STAGVID_BOFFSET 0 -#define ACL_RSLT0_STAGVID_BLEN 12 -#define ACL_RSLT0_STAGVID_FLAG HSL_RW - - -#define ACL_RSLT1 11 -#define ACL_RSLT1_OFFSET 0x5a004 -#define ACL_RSLT1_E_LENGTH 4 -#define ACL_RSLT1_E_OFFSET 0x10 -#define ACL_RSLT1_NR_E 96 - -#define DES_PORT0 -#define ACL_RSLT1_DES_PORT0_BOFFSET 29 -#define ACL_RSLT1_DES_PORT0_BLEN 3 -#define ACL_RSLT1_DES_PORT0_FLAG HSL_RW - -#define PRI_QU_EN -#define ACL_RSLT1_PRI_QU_EN_BOFFSET 28 -#define ACL_RSLT1_PRI_QU_EN_BLEN 1 -#define ACL_RSLT1_PRI_QU_EN_FLAG HSL_RW - -#define PRI_QU -#define ACL_RSLT1_PRI_QU_BOFFSET 25 -#define ACL_RSLT1_PRI_QU_BLEN 3 -#define ACL_RSLT1_PRI_QU_FLAG HSL_RW - -#define WCMP_EN -#define ACL_RSLT1_WCMP_EN_BOFFSET 24 -#define ACL_RSLT1_WCMP_EN_BLEN 1 -#define ACL_RSLT1_WCMP_EN_FLAG HSL_RW - -#define ARP_PTR -#define ACL_RSLT1_ARP_PTR_BOFFSET 17 -#define ACL_RSLT1_ARP_PTR_BLEN 7 -#define ACL_RSLT1_ARP_PTR_FLAG HSL_RW - -#define ARP_PTR_EN -#define ACL_RSLT1_ARP_PTR_EN_BOFFSET 16 -#define ACL_RSLT1_ARP_PTR_EN_BLEN 1 -#define ACL_RSLT1_ARP_PTR_EN_FLAG HSL_RW - -#define FORCE_L3_MODE -#define ACL_RSLT1_FORCE_L3_MODE_BOFFSET 14 -#define ACL_RSLT1_FORCE_L3_MODE_BLEN 2 -#define ACL_RSLT1_FORCE_L3_MODE_FLAG HSL_RW - -#define LOOK_VID_CHG -#define ACL_RSLT1_LOOK_VID_CHG_BOFFSET 13 -#define ACL_RSLT1_LOOK_VID_CHG_BLEN 1 -#define ACL_RSLT1_LOOK_VID_CHG_FLAG HSL_RW - -#define TRANS_CVID_CHG -#define ACL_RSLT1_TRANS_CVID_CHG_BOFFSET 12 -#define ACL_RSLT1_TRANS_CVID_CHG_BLEN 1 -#define ACL_RSLT1_TRANS_CVID_CHG_FLAG HSL_RW - -#define TRANS_SVID_CHG -#define ACL_RSLT1_TRANS_SVID_CHG_BOFFSET 11 -#define ACL_RSLT1_TRANS_SVID_CHG_BLEN 1 -#define ACL_RSLT1_TRANS_SVID_CHG_FLAG HSL_RW - -#define CTAG_CFI_CHG -#define ACL_RSLT1_CTAG_CFI_CHG_BOFFSET 10 -#define ACL_RSLT1_CTAG_CFI_CHG_BLEN 1 -#define ACL_RSLT1_CTAG_CFI_CHG_FLAG HSL_RW - -#define CTAG_PRI_REMAP -#define ACL_RSLT1_CTAG_PRI_REMAP_BOFFSET 9 -#define ACL_RSLT1_CTAG_PRI_REMAP_BLEN 1 -#define ACL_RSLT1_CTAG_PRI_REMAP_FLAG HSL_RW - -#define STAG_DEI_CHG -#define ACL_RSLT1_STAG_DEI_CHG_BOFFSET 8 -#define ACL_RSLT1_STAG_DEI_CHG_BLEN 1 -#define ACL_RSLT1_STAG_DEI_CHG_FLAG HSL_RW - -#define STAG_PRI_REMAP -#define ACL_RSLT1_STAG_PRI_REMAP_BOFFSET 7 -#define ACL_RSLT1_STAG_PRI_REMAP_BLEN 1 -#define ACL_RSLT1_STAG_PRI_REMAP_FLAG HSL_RW - -#define DSCP_REMAP -#define ACL_RSLT1_DSCP_REMAP_BOFFSET 6 -#define ACL_RSLT1_DSCP_REMAP_BLEN 1 -#define ACL_RSLT1_DSCP_REMAP_FLAG HSL_RW - -#define DSCPV -#define ACL_RSLT1_DSCPV_BOFFSET 0 -#define ACL_RSLT1_DSCPV_BLEN 6 -#define ACL_RSLT1_DSCPV_FLAG HSL_RW - -#define ACL_RSLT2 12 -#define ACL_RSLT2_OFFSET 0x5a008 -#define ACL_RSLT2_E_LENGTH 4 -#define ACL_RSLT2_E_OFFSET 0x10 -#define ACL_RSLT2_NR_E 96 - -#define TRIGGER_INTR -#define ACL_RSLT2_TRIGGER_INTR_BOFFSET 16 -#define ACL_RSLT2_TRIGGER_INTR_BLEN 1 -#define ACL_RSLT2_TRIGGER_INTR_FLAG HSL_RW - -#define EG_BYPASS -#define ACL_RSLT2_EG_BYPASS_BOFFSET 15 -#define ACL_RSLT2_EG_BYPASS_BLEN 1 -#define ACL_RSLT2_EG_BYPASS_FLAG HSL_RW - -#define POLICER_EN -#define ACL_RSLT2_POLICER_EN_BOFFSET 14 -#define ACL_RSLT2_POLICER_EN_BLEN 1 -#define ACL_RSLT2_POLICER_EN_FLAG HSL_RW - -#define POLICER_PTR -#define ACL_RSLT2_POLICER_PTR_BOFFSET 9 -#define ACL_RSLT2_POLICER_PTR_BLEN 5 -#define ACL_RSLT2_POLICER_PTR_FLAG HSL_RW - -#define FWD_CMD -#define ACL_RSLT2_FWD_CMD_BOFFSET 6 -#define ACL_RSLT2_FWD_CMD_BLEN 3 -#define ACL_RSLT2_FWD_CMD_FLAG HSL_RW - -#define MIRR_EN -#define ACL_RSLT2_MIRR_EN_BOFFSET 5 -#define ACL_RSLT2_MIRR_EN_BLEN 1 -#define ACL_RSLT2_MIRR_EN_FLAG HSL_RW - -#define DES_PORT_EN -#define ACL_RSLT2_DES_PORT_EN_BOFFSET 4 -#define ACL_RSLT2_DES_PORT_EN_BLEN 1 -#define ACL_RSLT2_DES_PORT_EN_FLAG HSL_RW - -#define DES_PORT1 -#define ACL_RSLT2_DES_PORT1_BOFFSET 0 -#define ACL_RSLT2_DES_PORT1_BLEN 4 -#define ACL_RSLT2_DES_PORT1_FLAG HSL_RW - - - - - /* MAC Type Rule Field Define */ -#define MAC_RUL_V0 0 -#define MAC_RUL_V0_OFFSET 0x58000 -#define MAC_RUL_V0_E_LENGTH 4 -#define MAC_RUL_V0_E_OFFSET 0x20 -#define MAC_RUL_V0_NR_E 96 - -#define DAV_BYTE2 -#define MAC_RUL_V0_DAV_BYTE2_BOFFSET 24 -#define MAC_RUL_V0_DAV_BYTE2_BLEN 8 -#define MAC_RUL_V0_DAV_BYTE2_FLAG HSL_RW - -#define DAV_BYTE3 -#define MAC_RUL_V0_DAV_BYTE3_BOFFSET 16 -#define MAC_RUL_V0_DAV_BYTE3_BLEN 8 -#define MAC_RUL_V0_DAV_BYTE3_FLAG HSL_RW - -#define DAV_BYTE4 -#define MAC_RUL_V0_DAV_BYTE4_BOFFSET 8 -#define MAC_RUL_V0_DAV_BYTE4_BLEN 8 -#define MAC_RUL_V0_DAV_BYTE4_FLAG HSL_RW - -#define DAV_BYTE5 -#define MAC_RUL_V0_DAV_BYTE5_BOFFSET 0 -#define MAC_RUL_V0_DAV_BYTE5_BLEN 8 -#define MAC_RUL_V0_DAV_BYTE5_FLAG HSL_RW - - -#define MAC_RUL_V1 1 -#define MAC_RUL_V1_OFFSET 0x58004 -#define MAC_RUL_V1_E_LENGTH 4 -#define MAC_RUL_V1_E_OFFSET 0x20 -#define MAC_RUL_V1_NR_E 96 - -#define SAV_BYTE4 -#define MAC_RUL_V1_SAV_BYTE4_BOFFSET 24 -#define MAC_RUL_V1_SAV_BYTE4_BLEN 8 -#define MAC_RUL_V1_SAV_BYTE4_FLAG HSL_RW - -#define SAV_BYTE5 -#define MAC_RUL_V1_SAV_BYTE5_BOFFSET 16 -#define MAC_RUL_V1_SAV_BYTE5_BLEN 8 -#define MAC_RUL_V1_SAV_BYTE5_FLAG HSL_RW - -#define DAV_BYTE0 -#define MAC_RUL_V1_DAV_BYTE0_BOFFSET 8 -#define MAC_RUL_V1_DAV_BYTE0_BLEN 8 -#define MAC_RUL_V1_DAV_BYTE0_FLAG HSL_RW - -#define DAV_BYTE1 -#define MAC_RUL_V1_DAV_BYTE1_BOFFSET 0 -#define MAC_RUL_V1_DAV_BYTE1_BLEN 8 -#define MAC_RUL_V1_DAV_BYTE1_FLAG HSL_RW - - -#define MAC_RUL_V2 2 -#define MAC_RUL_V2_OFFSET 0x58008 -#define MAC_RUL_V2_E_LENGTH 4 -#define MAC_RUL_V2_E_OFFSET 0x20 -#define MAC_RUL_V2_NR_E 96 - -#define SAV_BYTE0 -#define MAC_RUL_V2_SAV_BYTE0_BOFFSET 24 -#define MAC_RUL_V2_SAV_BYTE0_BLEN 8 -#define MAC_RUL_V2_SAV_BYTE0_FLAG HSL_RW - -#define SAV_BYTE1 -#define MAC_RUL_V2_SAV_BYTE1_BOFFSET 16 -#define MAC_RUL_V2_SAV_BYTE1_BLEN 8 -#define MAC_RUL_V2_SAV_BYTE1_FLAG HSL_RW - -#define SAV_BYTE2 -#define MAC_RUL_V2_SAV_BYTE2_BOFFSET 8 -#define MAC_RUL_V2_SAV_BYTE2_BLEN 8 -#define MAC_RUL_V2_SAV_BYTE2_FLAG HSL_RW - -#define SAV_BYTE3 -#define MAC_RUL_V2_SAV_BYTE3_BOFFSET 0 -#define MAC_RUL_V2_SAV_BYTE3_BLEN 8 -#define MAC_RUL_V2_SAV_BYTE3_FLAG HSL_RW - - -#define MAC_RUL_V3 3 -#define MAC_RUL_V3_ID 13 -#define MAC_RUL_V3_OFFSET 0x5800c -#define MAC_RUL_V3_E_LENGTH 4 -#define MAC_RUL_V3_E_OFFSET 0x20 -#define MAC_RUL_V3_NR_E 96 - -#define ETHTYPV -#define MAC_RUL_V3_ETHTYPV_BOFFSET 16 -#define MAC_RUL_V3_ETHTYPV_BLEN 16 -#define MAC_RUL_V3_ETHTYPV_FLAG HSL_RW - -#define VLANPRIV -#define MAC_RUL_V3_VLANPRIV_BOFFSET 13 -#define MAC_RUL_V3_VLANPRIV_BLEN 3 -#define MAC_RUL_V3_VLANPRIV_FLAG HSL_RW - -#define VLANCFIV -#define MAC_RUL_V3_VLANCFIV_BOFFSET 12 -#define MAC_RUL_V3_VLANCFIV_BLEN 1 -#define MAC_RUL_V3_VLANCFIV_FLAG HSL_RW - -#define VLANIDV -#define MAC_RUL_V3_VLANIDV_BOFFSET 0 -#define MAC_RUL_V3_VLANIDV_BLEN 12 -#define MAC_RUL_V3_VLANIDV_FLAG HSL_RW - - -#define MAC_RUL_V4 4 -#define MAC_RUL_V4_OFFSET 0x58010 -#define MAC_RUL_V4_E_LENGTH 4 -#define MAC_RUL_V4_E_OFFSET 0x20 -#define MAC_RUL_V4_NR_E 96 - -#define RULE_INV -#define MAC_RUL_V4_RULE_INV_BOFFSET 7 -#define MAC_RUL_V4_RULE_INV_BLEN 1 -#define MAC_RUL_V4_RULE_INV_FLAG HSL_RW - -#define SRC_PT -#define MAC_RUL_V4_SRC_PT_BOFFSET 0 -#define MAC_RUL_V4_SRC_PT_BLEN 7 -#define MAC_RUL_V4_SRC_PT_FLAG HSL_RW - - -#define MAC_RUL_M0 5 -#define MAC_RUL_M0_OFFSET 0x59000 -#define MAC_RUL_M0_E_LENGTH 4 -#define MAC_RUL_M0_E_OFFSET 0x20 -#define MAC_RUL_M0_NR_E 96 - -#define DAM_BYTE2 -#define MAC_RUL_M0_DAM_BYTE2_BOFFSET 24 -#define MAC_RUL_M0_DAM_BYTE2_BLEN 8 -#define MAC_RUL_M0_DAM_BYTE2_FLAG HSL_RW - -#define DAM_BYTE3 -#define MAC_RUL_M0_DAM_BYTE3_BOFFSET 16 -#define MAC_RUL_M0_DAM_BYTE3_BLEN 8 -#define MAC_RUL_M0_DAM_BYTE3_FLAG HSL_RW - -#define DAM_BYTE4 -#define MAC_RUL_M0_DAM_BYTE4_BOFFSET 8 -#define MAC_RUL_M0_DAM_BYTE4_BLEN 8 -#define MAC_RUL_M0_DAM_BYTE4_FLAG HSL_RW - -#define DAM_BYTE5 -#define MAC_RUL_M0_DAM_BYTE5_BOFFSET 0 -#define MAC_RUL_M0_DAM_BYTE5_BLEN 8 -#define MAC_RUL_M0_DAM_BYTE5_FLAG HSL_RW - - -#define MAC_RUL_M1 6 -#define MAC_RUL_M1_OFFSET 0x59004 -#define MAC_RUL_M1_E_LENGTH 4 -#define MAC_RUL_M1_E_OFFSET 0x20 -#define MAC_RUL_M1_NR_E 96 - -#define SAM_BYTE4 -#define MAC_RUL_M1_SAM_BYTE4_BOFFSET 24 -#define MAC_RUL_M1_SAM_BYTE4_BLEN 8 -#define MAC_RUL_M1_SAM_BYTE4_FLAG HSL_RW - -#define SAM_BYTE5 -#define MAC_RUL_M1_SAM_BYTE5_BOFFSET 16 -#define MAC_RUL_M1_SAM_BYTE5_BLEN 8 -#define MAC_RUL_M1_SAM_BYTE5_FLAG HSL_RW - -#define DAM_BYTE0 -#define MAC_RUL_M1_DAM_BYTE0_BOFFSET 8 -#define MAC_RUL_M1_DAM_BYTE0_BLEN 8 -#define MAC_RUL_M1_DAM_BYTE0_FLAG HSL_RW - -#define DAM_BYTE1 -#define MAC_RUL_M1_DAM_BYTE1_BOFFSET 0 -#define MAC_RUL_M1_DAM_BYTE1_BLEN 8 -#define MAC_RUL_M1_DAM_BYTE1_FLAG HSL_RW - - -#define MAC_RUL_M2 7 -#define MAC_RUL_M2_OFFSET 0x59008 -#define MAC_RUL_M2_E_LENGTH 4 -#define MAC_RUL_M2_E_OFFSET 0x20 -#define MAC_RUL_M2_NR_E 96 - -#define SAM_BYTE0 -#define MAC_RUL_M2_SAM_BYTE0_BOFFSET 24 -#define MAC_RUL_M2_SAM_BYTE0_BLEN 8 -#define MAC_RUL_M2_SAM_BYTE0_FLAG HSL_RW - -#define SAM_BYTE1 -#define MAC_RUL_M2_SAM_BYTE1_BOFFSET 16 -#define MAC_RUL_M2_SAM_BYTE1_BLEN 8 -#define MAC_RUL_M2_SAM_BYTE1_FLAG HSL_RW - -#define SAM_BYTE2 -#define MAC_RUL_M2_SAM_BYTE2_BOFFSET 8 -#define MAC_RUL_M2_SAM_BYTE2_BLEN 8 -#define MAC_RUL_M2_SAM_BYTE2_FLAG HSL_RW - -#define SAM_BYTE3 -#define MAC_RUL_M2_SAM_BYTE3_BOFFSET 0 -#define MAC_RUL_M2_SAM_BYTE3_BLEN 8 -#define MAC_RUL_M2_SAM_BYTE3_FLAG HSL_RW - - -#define MAC_RUL_M3 8 -#define MAC_RUL_M3_OFFSET 0x5900c -#define MAC_RUL_M3_E_LENGTH 4 -#define MAC_RUL_M3_E_OFFSET 0x20 -#define MAC_RUL_M3_NR_E 96 - -#define ETHTYPM -#define MAC_RUL_M3_ETHTYPM_BOFFSET 16 -#define MAC_RUL_M3_ETHTYPM_BLEN 16 -#define MAC_RUL_M3_ETHTYPM_FLAG HSL_RW - -#define VLANPRIM -#define MAC_RUL_M3_VLANPRIM_BOFFSET 13 -#define MAC_RUL_M3_VLANPRIM_BLEN 3 -#define MAC_RUL_M3_VLANPRIM_FLAG HSL_RW - -#define VLANCFIM -#define MAC_RUL_M3_VLANCFIM_BOFFSET 12 -#define MAC_RUL_M3_VLANCFIM_BLEN 1 -#define MAC_RUL_M3_VLANCFIM_FLAG HSL_RW - -#define VLANIDM -#define MAC_RUL_M3_VLANIDM_BOFFSET 0 -#define MAC_RUL_M3_VLANIDM_BLEN 12 -#define MAC_RUL_M3_VLANIDM_FLAG HSL_RW - - -#define MAC_RUL_M4 9 -#define MAC_RUL_M4_OFFSET 0x59010 -#define MAC_RUL_M4_E_LENGTH 4 -#define MAC_RUL_M4_E_OFFSET 0x20 -#define MAC_RUL_M4_NR_E 96 - -#define RULE_VALID -#define MAC_RUL_M4_RULE_VALID_BOFFSET 6 -#define MAC_RUL_M4_RULE_VALID_BLEN 2 -#define MAC_RUL_M4_RULE_VALID_FLAG HSL_RW - -#define TAGGEDM -#define MAC_RUL_M4_TAGGEDM_BOFFSET 5 -#define MAC_RUL_M4_TAGGEDM_BLEN 1 -#define MAC_RUL_M4_TAGGEDM_FLAG HSL_RW - -#define TAGGEDV -#define MAC_RUL_M4_TAGGEDV_BOFFSET 4 -#define MAC_RUL_M4_TAGGEDV_BLEN 1 -#define MAC_RUL_M4_TAGGEDV_FLAG HSL_RW - -#define VIDMSK -#define MAC_RUL_M4_VIDMSK_BOFFSET 3 -#define MAC_RUL_M4_VIDMSK_BLEN 1 -#define MAC_RUL_M4_VIDMSK_FLAG HSL_RW - -#define RULE_TYP -#define MAC_RUL_M4_RULE_TYP_BOFFSET 0 -#define MAC_RUL_M4_RULE_TYP_BLEN 3 -#define MAC_RUL_M4_RULE_TYP_FLAG HSL_RW - - - - - /* IP4 Type Rule Field Define */ -#define IP4_RUL_V0 0 -#define IP4_RUL_V0_OFFSET 0x58000 -#define IP4_RUL_V0_E_LENGTH 4 -#define IP4_RUL_V0_E_OFFSET 0x20 -#define IP4_RUL_V0_NR_E 96 - -#define DIPV -#define IP4_RUL_V0_DIPV_BOFFSET 0 -#define IP4_RUL_V0_DIPV_BLEN 32 -#define IP4_RUL_V0_DIPV_FLAG HSL_RW - - -#define IP4_RUL_V1 1 -#define IP4_RUL_V1_OFFSET 0x58004 -#define IP4_RUL_V1_E_LENGTH 4 -#define IP4_RUL_V1_E_OFFSET 0x20 -#define IP4_RUL_V1_NR_E 96 - -#define SIPV -#define IP4_RUL_V1_SIPV_BOFFSET 0 -#define IP4_RUL_V1_SIPV_BLEN 32 -#define IP4_RUL_V1_SIPV_FLAG HSL_RW - - -#define IP4_RUL_V2 2 -#define IP4_RUL_V2_OFFSET 0x58008 -#define IP4_RUL_V2_E_LENGTH 4 -#define IP4_RUL_V2_E_OFFSET 0x20 -#define IP4_RUL_V2_NR_E 96 - -#define IP4PROTV -#define IP4_RUL_V2_IP4PROTV_BOFFSET 0 -#define IP4_RUL_V2_IP4PROTV_BLEN 8 -#define IP4_RUL_V2_IP4PROTV_FLAG HSL_RW - -#define IP4DSCPV -#define IP4_RUL_V2_IP4DSCPV_BOFFSET 8 -#define IP4_RUL_V2_IP4DSCPV_BLEN 8 -#define IP4_RUL_V2_IP4DSCPV_FLAG HSL_RW - -#define IP4DPORTV -#define IP4_RUL_V2_IP4DPORTV_BOFFSET 16 -#define IP4_RUL_V2_IP4DPORTV_BLEN 16 -#define IP4_RUL_V2_IP4DPORTV_FLAG HSL_RW - - -#define IP4_RUL_V3 3 -#define IP4_RUL_V3_OFFSET 0x5800c -#define IP4_RUL_V3_E_LENGTH 4 -#define IP4_RUL_V3_E_OFFSET 0x20 -#define IP4_RUL_V3_NR_E 96 - -#define IP4TCPFLAGV -#define IP4_RUL_V3_IP4TCPFLAGV_BOFFSET 24 -#define IP4_RUL_V3_IP4TCPFLAGV_BLEN 6 -#define IP4_RUL_V3_IP4TCPFLAGV_FLAG HSL_RW - -#define IP4DHCPV -#define IP4_RUL_V3_IP4DHCPV_BOFFSET 22 -#define IP4_RUL_V3_IP4DHCPV_BLEN 1 -#define IP4_RUL_V3_IP4DHCPV_FLAG HSL_RW - -#define IP4RIPV -#define IP4_RUL_V3_IP4RIPV_BOFFSET 21 -#define IP4_RUL_V3_IP4RIPV_BLEN 1 -#define IP4_RUL_V3_IP4RIPV_FLAG HSL_RW - -#define ICMP_EN -#define IP4_RUL_V3_ICMP_EN_BOFFSET 20 -#define IP4_RUL_V3_ICMP_EN_BLEN 1 -#define IP4_RUL_V3_ICMP_EN_FLAG HSL_RW - -#define IP4SPORTV -#define IP4_RUL_V3_IP4SPORTV_BOFFSET 0 -#define IP4_RUL_V3_IP4SPORTV_BLEN 16 -#define IP4_RUL_V3_IP4SPORTV_FLAG HSL_RW - -#define IP4ICMPTYPV -#define IP4_RUL_V3_IP4ICMPTYPV_BOFFSET 8 -#define IP4_RUL_V3_IP4ICMPTYPV_BLEN 8 -#define IP4_RUL_V3_IP4ICMPTYPV_FLAG HSL_RW - -#define IP4ICMPCODEV -#define IP4_RUL_V3_IP4ICMPCODEV_BOFFSET 0 -#define IP4_RUL_V3_IP4ICMPCODEV_BLEN 8 -#define IP4_RUL_V3_IP4ICMPCODEV_FLAG HSL_RW - - -#define IP4_RUL_V4 4 -#define IP4_RUL_V4_OFFSET 0x58010 -#define IP4_RUL_V4_E_LENGTH 4 -#define IP4_RUL_V4_E_OFFSET 0x20 -#define IP4_RUL_V4_NR_E 96 - - -#define IP4_RUL_M0 5 -#define IP4_RUL_M0_OFFSET 0x59000 -#define IP4_RUL_M0_E_LENGTH 4 -#define IP4_RUL_M0_E_OFFSET 0x20 -#define IP4_RUL_M0_NR_E 96 - -#define DIPM -#define IP4_RUL_M0_DIPM_BOFFSET 0 -#define IP4_RUL_M0_DIPM_BLEN 32 -#define IP4_RUL_M0_DIPM_FLAG HSL_RW - - -#define IP4_RUL_M1 6 -#define IP4_RUL_M1_OFFSET 0x59004 -#define IP4_RUL_M1_E_LENGTH 4 -#define IP4_RUL_M1_E_OFFSET 0x20 -#define IP4_RUL_M1_NR_E 96 - -#define SIPM -#define IP4_RUL_M1_SIPM_BOFFSET 0 -#define IP4_RUL_M1_SIPM_BLEN 32 -#define IP4_RUL_M1_SIPM_FLAG HSL_RW - - -#define IP4_RUL_M2 7 -#define IP4_RUL_M2_OFFSET 0x59008 -#define IP4_RUL_M2_E_LENGTH 4 -#define IP4_RUL_M2_E_OFFSET 0x20 -#define IP4_RUL_M2_NR_E 96 - -#define IP4PROTM -#define IP4_RUL_M2_IP4PROTM_BOFFSET 0 -#define IP4_RUL_M2_IP4PROTM_BLEN 8 -#define IP4_RUL_M2_IP4PROTM_FLAG HSL_RW - -#define IP4DSCPM -#define IP4_RUL_M2_IP4DSCPM_BOFFSET 8 -#define IP4_RUL_M2_IP4DSCPM_BLEN 8 -#define IP4_RUL_M2_IP4DSCPM_FLAG HSL_RW - -#define IP4DPORTM -#define IP4_RUL_M2_IP4DPORTM_BOFFSET 16 -#define IP4_RUL_M2_IP4DPORTM_BLEN 16 -#define IP4_RUL_M2_IP4DPORTM_FLAG HSL_RW - - -#define IP4_RUL_M3 8 -#define IP4_RUL_M3_OFFSET 0x5900c -#define IP4_RUL_M3_E_LENGTH 4 -#define IP4_RUL_M3_E_OFFSET 0x20 -#define IP4_RUL_M3_NR_E 96 - -#define IP4TCPFLAGM -#define IP4_RUL_M3_IP4TCPFLAGM_BOFFSET 24 -#define IP4_RUL_M3_IP4TCPFLAGM_BLEN 6 -#define IP4_RUL_M3_IP4TCPFLAGM_FLAG HSL_RW - -#define IP4DHCPM -#define IP4_RUL_M3_IP4DHCPM_BOFFSET 22 -#define IP4_RUL_M3_IP4DHCPM_BLEN 1 -#define IP4_RUL_M3_IP4DHCPM_FLAG HSL_RW - -#define IP4RIPM -#define IP4_RUL_M3_IP4RIPM_BOFFSET 21 -#define IP4_RUL_M3_IP4RIPM_BLEN 1 -#define IP4_RUL_M3_IP4RIPM_FLAG HSL_RW - -#define IP4DPORTM_EN -#define IP4_RUL_M3_IP4DPORTM_EN_BOFFSET 17 -#define IP4_RUL_M3_IP4DPORTM_EN_BLEN 1 -#define IP4_RUL_M3_IP4DPORTM_EN_FLAG HSL_RW - -#define IP4SPORTM_EN -#define IP4_RUL_M3_IP4SPORTM_EN_BOFFSET 16 -#define IP4_RUL_M3_IP4SPORTM_EN_BLEN 1 -#define IP4_RUL_M3_IP4SPORTM_EN_FLAG HSL_RW - -#define IP4SPORTM -#define IP4_RUL_M3_IP4SPORTM_BOFFSET 0 -#define IP4_RUL_M3_IP4SPORTM_BLEN 16 -#define IP4_RUL_M3_IP4SPORTM_FLAG HSL_RW - -#define IP4ICMPTYPM -#define IP4_RUL_M3_IP4ICMPTYPM_BOFFSET 8 -#define IP4_RUL_M3_IP4ICMPTYPM_BLEN 8 -#define IP4_RUL_M3_IP4ICMPTYPM_FLAG HSL_RW - -#define IP4ICMPCODEM -#define IP4_RUL_M3_IP4ICMPCODEM_BOFFSET 0 -#define IP4_RUL_M3_IP4ICMPCODEM_BLEN 8 -#define IP4_RUL_M3_IP4ICMPCODEM_FLAG HSL_RW - - -#define IP4_RUL_M4 9 -#define IP4_RUL_M4_OFFSET 0x59010 -#define IP4_RUL_M4_E_LENGTH 4 -#define IP4_RUL_M4_E_OFFSET 0x20 -#define IP4_RUL_M4_NR_E 32 - - - - - /* IP6 Type1 Rule Field Define */ -#define IP6_RUL1_V0 0 -#define IP6_RUL1_V0_OFFSET 0x58000 -#define IP6_RUL1_V0_E_LENGTH 4 -#define IP6_RUL1_V0_E_OFFSET 0x20 -#define IP6_RUL1_V0_NR_E 96 - -#define IP6_DIPV0 -#define IP6_RUL1_V0_IP6_DIPV0_BOFFSET 0 -#define IP6_RUL1_V0_IP6_DIPV0_BLEN 32 -#define IP6_RUL1_V0_IP6_DIPV0_FLAG HSL_RW - - -#define IP6_RUL1_V1 1 -#define IP6_RUL1_V1_OFFSET 0x58004 -#define IP6_RUL1_V1_E_LENGTH 4 -#define IP6_RUL1_V1_E_OFFSET 0x20 -#define IP6_RUL1_V1_NR_E 96 - -#define IP6_DIPV1 -#define IP6_RUL1_V1_IP6_DIPV1_BOFFSET 0 -#define IP6_RUL1_V1_IP6_DIPv1_BLEN 32 -#define IP6_RUL1_V1_IP6_DIPV1_FLAG HSL_RW - - -#define IP6_RUL1_V2 2 -#define IP6_RUL1_V2_OFFSET 0x58008 -#define IP6_RUL1_V2_E_LENGTH 4 -#define IP6_RUL1_V2_E_OFFSET 0x20 -#define IP6_RUL1_V2_NR_E 96 - -#define IP6_DIPV2 -#define IP6_RUL1_V2_IP6_DIPV2_BOFFSET 0 -#define IP6_RUL1_V2_IP6_DIPv2_BLEN 32 -#define IP6_RUL1_V2_IP6_DIPV2_FLAG HSL_RW - - -#define IP6_RUL1_V3 3 -#define IP6_RUL1_V3_OFFSET 0x5800c -#define IP6_RUL1_V3_E_LENGTH 4 -#define IP6_RUL1_V3_E_OFFSET 0x20 -#define IP6_RUL1_V3_NR_E 96 - -#define IP6_DIPV3 -#define IP6_RUL1_V3_IP6_DIPV3_BOFFSET 0 -#define IP6_RUL1_V3_IP6_DIPv3_BLEN 32 -#define IP6_RUL1_V3_IP6_DIPV3_FLAG HSL_RW - - -#define IP6_RUL1_V4 4 -#define IP6_RUL1_V4_OFFSET 0x58010 -#define IP6_RUL1_V4_E_LENGTH 4 -#define IP6_RUL1_V4_E_OFFSET 0x20 -#define IP6_RUL1_V4_NR_E 96 - - -#define IP6_RUL1_M0 5 -#define IP6_RUL1_M0_OFFSET 0x59000 -#define IP6_RUL1_M0_E_LENGTH 4 -#define IP6_RUL1_M0_E_OFFSET 0x20 -#define IP6_RUL1_M0_NR_E 96 - -#define IP6_DIPM0 -#define IP6_RUL1_M0_IP6_DIPM0_BOFFSET 0 -#define IP6_RUL1_M0_IP6_DIPM0_BLEN 32 -#define IP6_RUL1_M0_IP6_DIPM0_FLAG HSL_RW - - -#define IP6_RUL1_M1 6 -#define IP6_RUL1_M1_OFFSET 0x59004 -#define IP6_RUL1_M1_E_LENGTH 4 -#define IP6_RUL1_M1_E_OFFSET 0x20 -#define IP6_RUL1_M1_NR_E 96 - -#define IP6_DIPM1 -#define IP6_RUL1_M1_IP6_DIPM1_BOFFSET 0 -#define IP6_RUL1_M1_IP6_DIPM1_BLEN 32 -#define IP6_RUL1_M1_IP6_DIPM1_FLAG HSL_RW - - -#define IP6_RUL1_M2 7 -#define IP6_RUL1_M2_OFFSET 0x59008 -#define IP6_RUL1_M2_E_LENGTH 4 -#define IP6_RUL1_M2_E_OFFSET 0x20 -#define IP6_RUL1_M2_NR_E 96 - -#define IP6_DIPM2 -#define IP6_RUL1_M2_IP6_DIPM2_BOFFSET 0 -#define IP6_RUL1_M2_IP6_DIPM2_BLEN 32 -#define IP6_RUL1_M2_IP6_DIPM2_FLAG HSL_RW - - -#define IP6_RUL1_M3 8 -#define IP6_RUL1_M3_OFFSET 0x5900c -#define IP6_RUL1_M3_E_LENGTH 4 -#define IP6_RUL1_M3_E_OFFSET 0x20 -#define IP6_RUL1_M3_NR_E 96 - -#define IP6_DIPM3 -#define IP6_RUL1_M3_IP6_DIPM3_BOFFSET 0 -#define IP6_RUL1_M3_IP6_DIPM3_BLEN 32 -#define IP6_RUL1_M3_IP6_DIPM3_FLAG HSL_RW - - -#define IP6_RUL1_M4 9 -#define IP6_RUL1_M4_OFFSET 0x59010 -#define IP6_RUL1_M4_E_LENGTH 4 -#define IP6_RUL1_M4_E_OFFSET 0x20 -#define IP6_RUL1_M4_NR_E 96 - - - - - /* IP6 Type2 Rule Field Define */ -#define IP6_RUL2_V0 0 -#define IP6_RUL2_V0_OFFSET 0x58000 -#define IP6_RUL2_V0_E_LENGTH 4 -#define IP6_RUL2_V0_E_OFFSET 0x20 -#define IP6_RUL2_V0_NR_E 96 - -#define IP6_SIPV0 -#define IP6_RUL2_V0_IP6_SIPV0_BOFFSET 0 -#define IP6_RUL2_V0_IP6_SIPv0_BLEN 32 -#define IP6_RUL2_V0_IP6_SIPV0_FLAG HSL_RW - - -#define IP6_RUL2_V1 1 -#define IP6_RUL2_V1_OFFSET 0x58004 -#define IP6_RUL2_V1_E_LENGTH 4 -#define IP6_RUL2_V1_E_OFFSET 0x20 -#define IP6_RUL2_V1_NR_E 96 - -#define IP6_SIPV1 -#define IP6_RUL2_V1_IP6_SIPV1_BOFFSET 0 -#define IP6_RUL2_V1_IP6_SIPv1_BLEN 32 -#define IP6_RUL2_V1_IP6_SIPV1_FLAG HSL_RW - - -#define IP6_RUL2_V2 2 -#define IP6_RUL2_V2_OFFSET 0x58008 -#define IP6_RUL2_V2_E_LENGTH 4 -#define IP6_RUL2_V2_E_OFFSET 0x20 -#define IP6_RUL2_V2_NR_E 96 - -#define IP6_SIPV2 -#define IP6_RUL2_V2_IP6_SIPV2_BOFFSET 0 -#define IP6_RUL2_V2_IP6_SIPv2_BLEN 32 -#define IP6_RUL2_V2_IP6_SIPV2_FLAG HSL_RW - - -#define IP6_RUL2_V3 3 -#define IP6_RUL2_V3_OFFSET 0x5800c -#define IP6_RUL2_V3_E_LENGTH 4 -#define IP6_RUL2_V3_E_OFFSET 0x20 -#define IP6_RUL2_V3_NR_E 96 - -#define IP6_SIPV3 -#define IP6_RUL2_V3_IP6_SIPV3_BOFFSET 0 -#define IP6_RUL2_V3_IP6_SIPv3_BLEN 32 -#define IP6_RUL2_V3_IP6_SIPV3_FLAG HSL_RW - - -#define IP6_RUL2_V4 4 -#define IP6_RUL2_V4_OFFSET 0x58010 -#define IP6_RUL2_V4_E_LENGTH 4 -#define IP6_RUL2_V4_E_OFFSET 0x20 -#define IP6_RUL2_V4_NR_E 96 - - -#define IP6_RUL2_M0 5 -#define IP6_RUL2_M0_OFFSET 0x59000 -#define IP6_RUL2_M0_E_LENGTH 4 -#define IP6_RUL2_M0_E_OFFSET 0x20 -#define IP6_RUL2_M0_NR_E 96 - -#define IP6_SIPM0 -#define IP6_RUL2_M0_IP6_SIPM0_BOFFSET 0 -#define IP6_RUL2_M0_IP6_SIPM0_BLEN 32 -#define IP6_RUL2_M0_IP6_SIPM0_FLAG HSL_RW - - -#define IP6_RUL2_M1 6 -#define IP6_RUL2_M1_OFFSET 0x59004 -#define IP6_RUL2_M1_E_LENGTH 4 -#define IP6_RUL2_M1_E_OFFSET 0x20 -#define IP6_RUL2_M1_NR_E 96 - -#define IP6_SIPM1 -#define IP6_RUL2_M1_IP6_DIPM1_BOFFSET 0 -#define IP6_RUL2_M1_IP6_DIPM1_BLEN 32 -#define IP6_RUL2_M1_IP6_DIPM1_FLAG HSL_RW - - -#define IP6_RUL2_M2 7 -#define IP6_RUL2_M2_OFFSET 0x59008 -#define IP6_RUL2_M2_E_LENGTH 4 -#define IP6_RUL2_M2_E_OFFSET 0x20 -#define IP6_RUL2_M2_NR_E 96 - -#define IP6_SIPM2 -#define IP6_RUL2_M2_IP6_DIPM2_BOFFSET 0 -#define IP6_RUL2_M2_IP6_DIPM2_BLEN 32 -#define IP6_RUL2_M2_IP6_DIPM2_FLAG HSL_RW - - -#define IP6_RUL2_M3 8 -#define IP6_RUL2_M3_OFFSET 0x5900c -#define IP6_RUL2_M3_E_LENGTH 4 -#define IP6_RUL2_M3_E_OFFSET 0x20 -#define IP6_RUL2_M3_NR_E 96 - -#define IP6_SIPM3 -#define IP6_RUL2_M3_IP6_SIPM3_BOFFSET 0 -#define IP6_RUL2_M3_IP6_SIPM3_BLEN 32 -#define IP6_RUL2_M3_IP6_SIPM3_FLAG HSL_RW - - -#define IP6_RUL2_M4 9 -#define IP6_RUL2_M4_OFFSET 0x59010 -#define IP6_RUL2_M4_E_LENGTH 4 -#define IP6_RUL2_M4_E_OFFSET 0x20 -#define IP6_RUL2_M4_NR_E 96 - - - - - /* IP6 Type3 Rule Field Define */ -#define IP6_RUL3_V0 0 -#define IP6_RUL3_V0_OFFSET 0x58000 -#define IP6_RUL3_V0_E_LENGTH 4 -#define IP6_RUL3_V0_E_OFFSET 0x20 -#define IP6_RUL3_V0_NR_E 96 - -#define IP6PROTV -#define IP6_RUL3_V0_IP6PROTV_BOFFSET 0 -#define IP6_RUL3_V0_IP6PROTV_BLEN 8 -#define IP6_RUL3_V0_IP6PROTV_FLAG HSL_RW - -#define IP6DSCPV -#define IP6_RUL3_V0_IP6DSCPV_BOFFSET 8 -#define IP6_RUL3_V0_IP6DSCPV_BLEN 8 -#define IP6_RUL3_V0_IP6DSCPV_FLAG HSL_RW - - -#define IP6_RUL3_V1 1 -#define IP6_RUL3_V1_OFFSET 0x58004 -#define IP6_RUL3_V1_E_LENGTH 4 -#define IP6_RUL3_V1_E_OFFSET 0x20 -#define IP6_RUL3_V1_NR_E 96 - -#define IP6LABEL1V -#define IP6_RUL3_V1_IP6LABEL1V_BOFFSET 16 -#define IP6_RUL3_V1_IP6LABEL1V_BLEN 16 -#define IP6_RUL3_V1_IP6LABEL1V_FLAG HSL_RW - - -#define IP6_RUL3_V2 2 -#define IP6_RUL3_V2_OFFSET 0x58008 -#define IP6_RUL3_V2_E_LENGTH 4 -#define IP6_RUL3_V2_E_OFFSET 0x20 -#define IP6_RUL3_V2_NR_E 96 - -#define IP6LABEL2V -#define IP6_RUL3_V2_IP6LABEL2V_BOFFSET 0 -#define IP6_RUL3_V2_IP6LABEL2V_BLEN 4 -#define IP6_RUL3_V2_IP6LABEL2V_FLAG HSL_RW - -#define IP6DPORTV -#define IP6_RUL3_V2_IP6DPORTV_BOFFSET 16 -#define IP6_RUL3_V2_IP6DPORTV_BLEN 16 -#define IP6_RUL3_V2_IP6DPORTV_FLAG HSL_RW - - -#define IP6_RUL3_V3 3 -#define IP6_RUL3_V3_OFFSET 0x5800c -#define IP6_RUL3_V3_E_LENGTH 4 -#define IP6_RUL3_V3_E_OFFSET 0x20 -#define IP6_RUL3_V3_NR_E 96 - -#define IP6TCPFLAGV -#define IP6_RUL3_V3_IP6TCPFLAGV_BOFFSET 24 -#define IP6_RUL3_V3_IP6TCPFLAGV_BLEN 6 -#define IP6_RUL3_V3_IP6TCPFLAGV_FLAG HSL_RW - -#define IP6FWDTYPV -#define IP6_RUL3_V3_IP6FWDTYPV_BOFFSET 23 -#define IP6_RUL3_V3_IP6FWDTYPV_BLEN 1 -#define IP6_RUL3_V3_IP6FWDTYPV_FLAG HSL_RW - -#define IP6DHCPV -#define IP6_RUL3_V3_IP6DHCPV_BOFFSET 22 -#define IP6_RUL3_V3_IP6DHCPV_BLEN 1 -#define IP6_RUL3_V3_IP6DHCPV_FLAG HSL_RW - -#define ICMP6_EN -#define IP6_RUL3_V3_ICMP6_EN_BOFFSET 20 -#define IP6_RUL3_V3_ICMP6_EN_BLEN 1 -#define IP6_RUL3_V3_ICMP6_EN_FLAG HSL_RW - -#define IP6SPORTV -#define IP6_RUL3_V3_IP6SPORTV_BOFFSET 0 -#define IP6_RUL3_V3_IP6SPORTV_BLEN 16 -#define IP6_RUL3_V3_IP6SPORTV_FLAG HSL_RW - -#define IP6ICMPTYPV -#define IP6_RUL3_V3_IP6ICMPTYPV_BOFFSET 8 -#define IP6_RUL3_V3_IP6ICMPTYPV_BLEN 8 -#define IP6_RUL3_V3_IP6ICMPTYPV_FLAG HSL_RW - -#define IP6ICMPCODEV -#define IP6_RUL3_V3_IP6ICMPCODEV_BOFFSET 0 -#define IP6_RUL3_V3_IP6ICMPCODEV_BLEN 8 -#define IP6_RUL3_V3_IP6ICMPCODEV_FLAG HSL_RW - - -#define IP6_RUL3_V4 4 -#define IP6_RUL3_V4_OFFSET 0x58010 -#define IP6_RUL3_V4_E_LENGTH 4 -#define IP6_RUL3_V4_E_OFFSET 0x20 -#define IP6_RUL3_V4_NR_E 96 - - -#define IP6_RUL3_M0 5 -#define IP6_RUL3_M0_OFFSET 0x59000 -#define IP6_RUL3_M0_E_LENGTH 4 -#define IP6_RUL3_M0_E_OFFSET 0x20 -#define IP6_RUL3_M0_NR_E 96 - -#define IP6PROTM -#define IP6_RUL3_M0_IP6PROTM_BOFFSET 0 -#define IP6_RUL3_M0_IP6PROTM_BLEN 8 -#define IP6_RUL3_M0_IP6PROTM_FLAG HSL_RW - -#define IP6DSCPM -#define IP6_RUL3_M0_IP6DSCPM_BOFFSET 8 -#define IP6_RUL3_M0_IP6DSCPM_BLEN 8 -#define IP6_RUL3_M0_IP6DSCPM_FLAG HSL_RW - - -#define IP6_RUL3_M1 6 -#define IP6_RUL3_M1_OFFSET 0x59004 -#define IP6_RUL3_M1_E_LENGTH 4 -#define IP6_RUL3_M1_E_OFFSET 0x20 -#define IP6_RUL3_M1_NR_E 96 - -#define IP6LABEL1M -#define IP6_RUL3_M1_IP6LABEL1M_BOFFSET 16 -#define IP6_RUL3_M1_IP6LABEL1M_BLEN 16 -#define IP6_RUL3_M1_IP6LABEL1M_FLAG HSL_RW - - -#define IP6_RUL3_M2 7 -#define IP6_RUL3_M2_OFFSET 0x59008 -#define IP6_RUL3_M2_E_LENGTH 4 -#define IP6_RUL3_M2_E_OFFSET 0x20 -#define IP6_RUL3_M2_NR_E 96 - -#define IP6LABEL2M -#define IP6_RUL3_M2_IP6LABEL2M_BOFFSET 0 -#define IP6_RUL3_M2_IP6LABEL2M_BLEN 4 -#define IP6_RUL3_M2_IP6LABEL21M_FLAG HSL_RW - -#define IP6DPORTM -#define IP6_RUL3_M2_IP6DPORTM_BOFFSET 16 -#define IP6_RUL3_M2_IP6DPORTM_BLEN 16 -#define IP6_RUL3_M2_IP6DPORTM_FLAG HSL_RW - - -#define IP6_RUL3_M3 8 -#define IP6_RUL3_M3_OFFSET 0x5900c -#define IP6_RUL3_M3_E_LENGTH 4 -#define IP6_RUL3_M3_E_OFFSET 0x20 -#define IP6_RUL3_M3_NR_E 96 - -#define IP6TCPFLAGM -#define IP6_RUL3_M3_IP6TCPFLAGM_BOFFSET 24 -#define IP6_RUL3_M3_IP6TCPFLAGM_BLEN 6 -#define IP6_RUL3_M3_IP6TCPFLAGM_FLAG HSL_RW - -#define IP6RWDTYPM -#define IP6_RUL3_M3_IP6RWDTYPV_BOFFSET 23 -#define IP6_RUL3_M3_IP6RWDTYPV_BLEN 1 -#define IP6_RUL3_M3_IP6RWDTYPV_FLAG HSL_RW - -#define IP6DHCPM -#define IP6_RUL3_M3_IP6DHCPM_BOFFSET 22 -#define IP6_RUL3_M3_IP6DHCPM_BLEN 1 -#define IP6_RUL3_M3_IP6DHCPM_FLAG HSL_RW - -#define IP6DPORTM_EN -#define IP6_RUL3_M3_IP6DPORTM_EN_BOFFSET 17 -#define IP6_RUL3_M3_IP6DPORTM_EN_BLEN 1 -#define IP6_RUL3_M3_IP6DPORTM_EN_FLAG HSL_RW - -#define IP6SPORTM_EN -#define IP6_RUL3_M3_IP6SPORTM_EN_BOFFSET 16 -#define IP6_RUL3_M3_IP6SPORTM_EN_BLEN 1 -#define IP6_RUL3_M3_IP6SPORTM_EN_FLAG HSL_RW - -#define IP6SPORTM -#define IP6_RUL3_M3_IP6SPORTM_BOFFSET 0 -#define IP6_RUL3_M3_IP6SPORTM_BLEN 16 -#define IP6_RUL3_M3_IP6SPORTM_FLAG HSL_RW - -#define IP6ICMPTYPM -#define IP6_RUL3_M3_IP6ICMPTYPM_BOFFSET 8 -#define IP6_RUL3_M3_IP6ICMPTYPM_BLEN 8 -#define IP6_RUL3_M3_IP6ICMPTYPM_FLAG HSL_RW - -#define IP6ICMPCODEM -#define IP6_RUL3_M3_IP6ICMPCODEM_BOFFSET 0 -#define IP6_RUL3_M3_IP6ICMPCODEM_BLEN 8 -#define IP6_RUL3_M3_IP6ICMPCODEM_FLAG HSL_RW - - -#define IP6_RUL3_M4 9 -#define IP6_RUL3_M4_OFFSET 0x59010 -#define IP6_RUL3_M4_E_LENGTH 4 -#define IP6_RUL3_M4_E_OFFSET 0x20 -#define IP6_RUL3_M4_NR_E 96 - - - - - /* Enhanced MAC Type Rule Field Define */ -#define EHMAC_RUL_V0 0 -#define EHMAC_RUL_V0_OFFSET 0x58000 -#define EHMAC_RUL_V0_E_LENGTH 4 -#define EHMAC_RUL_V0_E_OFFSET 0x20 -#define EHMAC_RUL_V0_NR_E 96 - -#define DAV_BYTE2 -#define EHMAC_RUL_V0_DAV_BYTE2_BOFFSET 24 -#define EHMAC_RUL_V0_DAV_BYTE2_BLEN 8 -#define EHMAC_RUL_V0_DAV_BYTE2_FLAG HSL_RW - -#define DAV_BYTE3 -#define EHMAC_RUL_V0_DAV_BYTE3_BOFFSET 16 -#define EHMAC_RUL_V0_DAV_BYTE3_BLEN 8 -#define EHMAC_RUL_V0_DAV_BYTE3_FLAG HSL_RW - -#define DAV_BYTE4 -#define EHMAC_RUL_V0_DAV_BYTE4_BOFFSET 8 -#define EHMAC_RUL_V0_DAV_BYTE4_BLEN 8 -#define EHMAC_RUL_V0_DAV_BYTE4_FLAG HSL_RW - -#define DAV_BYTE5 -#define EHMAC_RUL_V0_DAV_BYTE5_BOFFSET 0 -#define EHMAC_RUL_V0_DAV_BYTE5_BLEN 8 -#define EHMAC_RUL_V0_DAV_BYTE5_FLAG HSL_RW - - -#define EHMAC_RUL_V1 1 -#define EHMAC_RUL_V1_OFFSET 0x58004 -#define EHMAC_RUL_V1_E_LENGTH 4 -#define EHMAC_RUL_V1_E_OFFSET 0x20 -#define EHMAC_RUL_V1_NR_E 96 - -#define SAV_BYTE4 -#define EHMAC_RUL_V1_SAV_BYTE4_BOFFSET 24 -#define EHMAC_RUL_V1_SAV_BYTE4_BLEN 8 -#define EHMAC_RUL_V1_SAV_BYTE4_FLAG HSL_RW - -#define SAV_BYTE5 -#define EHMAC_RUL_V1_SAV_BYTE5_BOFFSET 16 -#define EHMAC_RUL_V1_SAV_BYTE5_BLEN 8 -#define EHMAC_RUL_V1_SAV_BYTE5_FLAG HSL_RW - -#define DAV_BYTE0 -#define EHMAC_RUL_V1_DAV_BYTE0_BOFFSET 8 -#define EHMAC_RUL_V1_DAV_BYTE0_BLEN 8 -#define EHMAC_RUL_V1_DAV_BYTE0_FLAG HSL_RW - -#define DAV_BYTE1 -#define EHMAC_RUL_V1_DAV_BYTE1_BOFFSET 0 -#define EHMAC_RUL_V1_DAV_BYTE1_BLEN 8 -#define EHMAC_RUL_V1_DAV_BYTE1_FLAG HSL_RW - - -#define EHMAC_RUL_V2 2 -#define EHMAC_RUL_V2_OFFSET 0x58008 -#define EHMAC_RUL_V2_E_LENGTH 4 -#define EHMAC_RUL_V2_E_OFFSET 0x20 -#define EHMAC_RUL_V2_NR_E 96 - -#define CTAG_VIDLV -#define EHMAC_RUL_V2_CTAG_VIDLV_BOFFSET 24 -#define EHMAC_RUL_V2_CTAG_VIDLV_BLEN 8 -#define EHMAC_RUL_V2_CTAG_VIDLV_FLAG HSL_RW - -#define STAG_PRIV -#define EHMAC_RUL_V2_STAG_PRIV_BOFFSET 21 -#define EHMAC_RUL_V2_STAG_PRIV_BLEN 3 -#define EHMAC_RUL_V2_STAG_PRIV_FLAG HSL_RW - -#define STAG_DEIV -#define EHMAC_RUL_V2_STAG_DEIV_BOFFSET 20 -#define EHMAC_RUL_V2_STAG_DEIV_BLEN 1 -#define EHMAC_RUL_V2_STAG_DEIV_FLAG HSL_RW - -#define STAG_VIDV -#define EHMAC_RUL_V2_STAG_VIDV_BOFFSET 8 -#define EHMAC_RUL_V2_STAG_VIDV_BLEN 12 -#define EHMAC_RUL_V2_STAG_VIDV_FLAG HSL_RW - -#define SAV_BYTE3 -#define EHMAC_RUL_V2_SAV_BYTE3_BOFFSET 0 -#define EHMAC_RUL_V2_SAV_BYTE3_BLEN 8 -#define EHMAC_RUL_V2_SAV_BYTE3_FLAG HSL_RW - - -#define EHMAC_RUL_V3 3 -#define EHMAC_RUL_V3_ID 13 -#define EHMAC_RUL_V3_OFFSET 0x5800c -#define EHMAC_RUL_V3_E_LENGTH 4 -#define EHMAC_RUL_V3_E_OFFSET 0x20 -#define EHMAC_RUL_V3_NR_E 96 - -#define STAGGEDM -#define EHMAC_RUL_V3_STAGGEDM_BOFFSET 31 -#define EHMAC_RUL_V3_STAGGEDM_BLEN 1 -#define EHMAC_RUL_V3_STAGGEDM_FLAG HSL_RW - -#define STAGGEDV -#define EHMAC_RUL_V3_STAGGEDV_BOFFSET 30 -#define EHMAC_RUL_V3_STAGGEDV_BLEN 1 -#define EHMAC_RUL_V3_STAGGEDV_FLAG HSL_RW - -#define DA_EN -#define EHMAC_RUL_V3_DA_EN_BOFFSET 25 -#define EHMAC_RUL_V3_DA_EN_BLEN 1 -#define EHMAC_RUL_V3_DA_EN_FLAG HSL_RW - -#define SVIDMSK -#define EHMAC_RUL_V3_SVIDMSK_BOFFSET 24 -#define EHMAC_RUL_V3_SVIDMSK_BLEN 1 -#define EHMAC_RUL_V3_SVIDMSK_FLAG HSL_RW - -#define ETHTYPV -#define EHMAC_RUL_V3_ETHTYPV_BOFFSET 8 -#define EHMAC_RUL_V3_ETHTYPV_BLEN 16 -#define EHMAC_RUL_V3_ETHTYPV_FLAG HSL_RW - -#define CTAG_PRIV -#define EHMAC_RUL_V3_CTAG_PRIV_BOFFSET 5 -#define EHMAC_RUL_V3_CTAG_PRIV_BLEN 3 -#define EHMAC_RUL_V3_CTAG_PRIV_FLAG HSL_RW - -#define CTAG_CFIV -#define EHMAC_RUL_V3_CTAG_CFIV_BOFFSET 4 -#define EHMAC_RUL_V3_CTAG_CFIV_BLEN 1 -#define EHMAC_RUL_V3_CTAG_CFIV_FLAG HSL_RW - -#define CTAG_VIDHV -#define EHMAC_RUL_V3_CTAG_VIDHV_BOFFSET 0 -#define EHMAC_RUL_V3_CTAG_VIDHV_BLEN 4 -#define EHMAC_RUL_V3_CTAG_VIDHV_FLAG HSL_RW - - -#define EHMAC_RUL_V4 4 -#define EHMAC_RUL_V4_OFFSET 0x58010 -#define EHMAC_RUL_V4_E_LENGTH 4 -#define EHMAC_RUL_V4_E_OFFSET 0x20 -#define EHMAC_RUL_V4_NR_E 96 - - -#define EHMAC_RUL_M0 5 -#define EHMAC_RUL_M0_OFFSET 0x59000 -#define EHMAC_RUL_M0_E_LENGTH 4 -#define EHMAC_RUL_M0_E_OFFSET 0x20 -#define EHMAC_RUL_M0_NR_E 96 - -#define DAM_BYTE2 -#define EHMAC_RUL_M0_DAM_BYTE2_BOFFSET 24 -#define EHMAC_RUL_M0_DAM_BYTE2_BLEN 8 -#define EHMAC_RUL_M0_DAM_BYTE2_FLAG HSL_RW - -#define DAM_BYTE3 -#define EHMAC_RUL_M0_DAM_BYTE3_BOFFSET 16 -#define EHMAC_RUL_M0_DAM_BYTE3_BLEN 8 -#define EHMAC_RUL_M0_DAM_BYTE3_FLAG HSL_RW - -#define DAM_BYTE4 -#define EHMAC_RUL_M0_DAM_BYTE4_BOFFSET 8 -#define EHMAC_RUL_M0_DAM_BYTE4_BLEN 8 -#define EHMAC_RUL_M0_DAM_BYTE4_FLAG HSL_RW - -#define DAM_BYTE5 -#define EHMAC_RUL_M0_DAM_BYTE5_BOFFSET 0 -#define EHMAC_RUL_M0_DAM_BYTE5_BLEN 8 -#define EHMAC_RUL_M0_DAM_BYTE5_FLAG HSL_RW - - -#define EHMAC_RUL_M1 6 -#define EHMAC_RUL_M1_OFFSET 0x59004 -#define EHMAC_RUL_M1_E_LENGTH 4 -#define EHMAC_RUL_M1_E_OFFSET 0x20 -#define EHMAC_RUL_M1_NR_E 96 - -#define SAM_BYTE4 -#define EHMAC_RUL_M1_SAM_BYTE4_BOFFSET 24 -#define EHMAC_RUL_M1_SAM_BYTE4_BLEN 8 -#define EHMAC_RUL_M1_SAM_BYTE4_FLAG HSL_RW - -#define SAM_BYTE5 -#define EHMAC_RUL_M1_SAM_BYTE5_BOFFSET 16 -#define EHMAC_RUL_M1_SAM_BYTE5_BLEN 8 -#define EHMAC_RUL_M1_SAM_BYTE5_FLAG HSL_RW - -#define DAM_BYTE0 -#define EHMAC_RUL_M1_DAM_BYTE0_BOFFSET 8 -#define EHMAC_RUL_M1_DAM_BYTE0_BLEN 8 -#define EHMAC_RUL_M1_DAM_BYTE0_FLAG HSL_RW - -#define DAM_BYTE1 -#define EHMAC_RUL_M1_DAM_BYTE1_BOFFSET 0 -#define EHMAC_RUL_M1_DAM_BYTE1_BLEN 8 -#define EHMAC_RUL_M1_DAM_BYTE1_FLAG HSL_RW - - -#define EHMAC_RUL_M2 7 -#define EHMAC_RUL_M2_OFFSET 0x59008 -#define EHMAC_RUL_M2_E_LENGTH 4 -#define EHMAC_RUL_M2_E_OFFSET 0x20 -#define EHMAC_RUL_M2_NR_E 96 - -#define CTAG_VIDLM -#define EHMAC_RUL_M2_CTAG_VIDLM_BOFFSET 24 -#define EHMAC_RUL_M2_CTAG_VIDLM_BLEN 8 -#define EHMAC_RUL_M2_CTAG_VIDLM_FLAG HSL_RW - -#define STAG_PRIM -#define EHMAC_RUL_M2_STAG_PRIM_BOFFSET 21 -#define EHMAC_RUL_M2_STAG_PRIM_BLEN 3 -#define EHMAC_RUL_M2_STAG_PRIM_FLAG HSL_RW - -#define STAG_DEIM -#define EHMAC_RUL_M2_STAG_DEIM_BOFFSET 20 -#define EHMAC_RUL_M2_STAG_DEIM_BLEN 1 -#define EHMAC_RUL_M2_STAG_DEIM_FLAG HSL_RW - -#define STAG_VIDM -#define EHMAC_RUL_M2_STAG_VIDM_BOFFSET 8 -#define EHMAC_RUL_M2_STAG_VIDM_BLEN 12 -#define EHMAC_RUL_M2_STAG_VIDM_FLAG HSL_RW - -#define SAM_BYTE3 -#define EHMAC_RUL_M2_SAM_BYTE3_BOFFSET 0 -#define EHMAC_RUL_M2_SAM_BYTE3_BLEN 8 -#define EHMAC_RUL_M2_SAM_BYTE3_FLAG HSL_RW - - -#define EHMAC_RUL_M3 8 -#define EHMAC_RUL_M3_OFFSET 0x5900c -#define EHMAC_RUL_M3_E_LENGTH 4 -#define EHMAC_RUL_M3_E_OFFSET 0x20 -#define EHMAC_RUL_M3_NR_E 96 - -#define ETHTYPM -#define EHMAC_RUL_M3_ETHTYPM_BOFFSET 8 -#define EHMAC_RUL_M3_ETHTYPM_BLEN 16 -#define EHMAC_RUL_M3_ETHTYPM_FLAG HSL_RW - -#define CTAG_PRIM -#define EHMAC_RUL_M3_CTAG_PRIM_BOFFSET 5 -#define EHMAC_RUL_M3_CTAG_PRIM_BLEN 3 -#define EHMAC_RUL_M3_CTAG_PRIM_FLAG HSL_RW - -#define CTAG_CFIM -#define EHMAC_RUL_M3_CTAG_CFIM_BOFFSET 4 -#define EHMAC_RUL_M3_CTAG_CFIM_BLEN 1 -#define EHMAC_RUL_M3_CTAG_CFIM_FLAG HSL_RW - -#define CTAG_VIDHM -#define EHMAC_RUL_M3_CTAG_VIDHM_BOFFSET 0 -#define EHMAC_RUL_M3_CTAG_VIDHM_BLEN 4 -#define EHMAC_RUL_M3_CTAG_VIDHM_FLAG HSL_RW - - -#define EHMAC_RUL_M4 9 -#define EHMAC_RUL_M4_OFFSET 0x59010 -#define EHMAC_RUL_M4_E_LENGTH 4 -#define EHMAC_RUL_M4_E_OFFSET 0x20 -#define EHMAC_RUL_M4_NR_E 96 - -#define CTAGGEDM -#define EHMAC_RUL_M4_CTAGGEDM_BOFFSET 5 -#define EHMAC_RUL_M4_CTAGGEDM_BLEN 1 -#define EHMAC_RUL_M4_CTAGGEDM_FLAG HSL_RW - -#define CTAGGEDV -#define EHMAC_RUL_M4_CTAGGEDV_BOFFSET 4 -#define EHMAC_RUL_M4_CTAGGEDV_BLEN 1 -#define EHMAC_RUL_M4_CTAGGEDV_FLAG HSL_RW - -#define CVIDMSK -#define EHMAC_RUL_M4_CVIDMSK_BOFFSET 3 -#define EHMAC_RUL_M4_CVIDMSK_BLEN 1 -#define EHMAC_RUL_M4_CVIDMSK_FLAG HSL_RW - - - - - /* PPPoE Session Table Define */ -#define PPPOE_SESSION -#define PPPOE_SESSION_OFFSET 0x5f000 -#define PPPOE_SESSION_E_LENGTH 4 -#define PPPOE_SESSION_E_OFFSET 0x4 -#define PPPOE_SESSION_NR_E 16 - -#define ENTRY_VALID -#define PPPOE_SESSION_ENTRY_VALID_BOFFSET 16 -#define PPPOE_SESSION_ENTRY_VALID_BLEN 2 -#define PPPOE_SESSION_ENTRY_VALID_FLAG HSL_RW - -#define SEESION_ID -#define PPPOE_SESSION_SEESION_ID_BOFFSET 0 -#define PPPOE_SESSION_SEESION_ID_BLEN 16 -#define PPPOE_SESSION_SEESION_ID_FLAG HSL_RW - - -#define PPPOE_EDIT -#define PPPOE_EDIT_OFFSET 0x02200 -#define PPPOE_EDIT_E_LENGTH 4 -#define PPPOE_EDIT_E_OFFSET 0x10 -#define PPPOE_EDIT_NR_E 16 - -#define EDIT_ID -#define PPPOE_EDIT_EDIT_ID_BOFFSET 0 -#define PPPOE_EDIT_EDIT_ID_BLEN 16 -#define PPPOE_EDIT_EDIT_ID_FLAG HSL_RW - - - - - /* L3 Host Entry Defile */ -#define HOST_ENTRY0 -#define HOST_ENTRY0_OFFSET 0x0e48 -#define HOST_ENTRY0_E_LENGTH 4 -#define HOST_ENTRY0_E_OFFSET 0x0 -#define HOST_ENTRY0_NR_E 1 - -#define IP_ADDR -#define HOST_ENTRY0_IP_ADDR_BOFFSET 0 -#define HOST_ENTRY0_IP_ADDR_BLEN 32 -#define HOST_ENTRY0_IP_ADDR_FLAG HSL_RW - -#define HOST_ENTRY1 -#define HOST_ENTRY1_OFFSET 0x0e4c -#define HOST_ENTRY1_E_LENGTH 4 -#define HOST_ENTRY1_E_OFFSET 0x0 -#define HOST_ENTRY1_NR_E 1 - -#define MAC_ADDR2 -#define HOST_ENTRY1_MAC_ADDR2_BOFFSET 24 -#define HOST_ENTRY1_MAC_ADDR2_BLEN 8 -#define HOST_ENTRY1_MAC_ADDR2_FLAG HSL_RW - -#define MAC_ADDR3 -#define HOST_ENTRY1_MAC_ADDR3_BOFFSET 16 -#define HOST_ENTRY1_MAC_ADDR3_BLEN 8 -#define HOST_ENTRY1_MAC_ADDR3_FLAG HSL_RW - -#define MAC_ADDR4 -#define HOST_ENTRY1_MAC_ADDR4_BOFFSET 8 -#define HOST_ENTRY1_MAC_ADDR4_BLEN 8 -#define HOST_ENTRY1_MAC_ADDR4_FLAG HSL_RW - -#define MAC_ADDR5 -#define HOST_ENTRY1_MAC_ADDR5_BOFFSET 0 -#define HOST_ENTRY1_MAC_ADDR5_BLEN 8 -#define HOST_ENTRY1_MAC_ADDR5_FLAG HSL_RW - -#define HOST_ENTRY2 -#define HOST_ENTRY2_OFFSET 0x0e50 -#define HOST_ENTRY2_E_LENGTH 4 -#define HOST_ENTRY2_E_OFFSET 0x0 -#define HOST_ENTRY2_NR_E 1 - -#define CPU_ADDR -#define HOST_ENTRY2_CPU_ADDR_BOFFSET 31 -#define HOST_ENTRY2_CPU_ADDR_BLEN 1 -#define HOST_ENTRY2_CPU_ADDR_FLAG HSL_RW - -#define SRC_PORT -#define HOST_ENTRY2_SRC_PORT_BOFFSET 28 -#define HOST_ENTRY2_SRC_PORT_BLEN 3 -#define HOST_ENTRY2_SRC_PORT_FLAG HSL_RW - -#define INTF_ID -#define HOST_ENTRY2_INTF_ID_BOFFSET 16 -#define HOST_ENTRY2_INTF_ID_BLEN 12 -#define HOST_ENTRY2_INTF_ID_FLAG HSL_RW - -#define MAC_ADDR0 -#define HOST_ENTRY2_MAC_ADDR0_BOFFSET 8 -#define HOST_ENTRY2_MAC_ADDR0_BLEN 8 -#define HOST_ENTRY2_MAC_ADDR0_FLAG HSL_RW - -#define MAC_ADDR1 -#define HOST_ENTRY2_MAC_ADDR1_BOFFSET 0 -#define HOST_ENTRY2_MAC_ADDR1_BLEN 8 -#define HOST_ENTRY2_MAC_ADDR1_FLAG HSL_RW - - -#define HOST_ENTRY3 -#define HOST_ENTRY3_OFFSET 0x0e54 -#define HOST_ENTRY3_E_LENGTH 4 -#define HOST_ENTRY3_E_OFFSET 0x0 -#define HOST_ENTRY3_NR_E 1 - -#define IP_VER -#define HOST_ENTRY3_IP_VER_BOFFSET 15 -#define HOST_ENTRY3_IP_VER_BLEN 1 -#define HOST_ENTRY3_IP_VER_FLAG HSL_RW - -#define AGE_FLAG -#define HOST_ENTRY3_AGE_FLAG_BOFFSET 12 -#define HOST_ENTRY3_AGE_FLAG_BLEN 3 -#define HOST_ENTRY3_AGE_FLAG_FLAG HSL_RW - -#define PPPOE_EN -#define HOST_ENTRY3_PPPOE_EN_BOFFSET 11 -#define HOST_ENTRY3_PPPOE_EN_BLEN 1 -#define HOST_ENTRY3_PPPOE_EN_FLAG HSL_RW - -#define PPPOE_IDX -#define HOST_ENTRY3_PPPOE_IDX_BOFFSET 7 -#define HOST_ENTRY3_PPPOE_IDX_BLEN 4 -#define HOST_ENTRY3_PPPOE_IDX_FLAG HSL_RW - -#define CNT_EN -#define HOST_ENTRY3_CNT_EN_BOFFSET 6 -#define HOST_ENTRY3_CNT_EN_BLEN 1 -#define HOST_ENTRY3_CNT_EN_FLAG HSL_RW - -#define CNT_IDX -#define HOST_ENTRY3_CNT_IDX_BOFFSET 2 -#define HOST_ENTRY3_CNT_IDX_BLEN 4 -#define HOST_ENTRY3_CNT_IDX_FLAG HSL_RW - -#define ACTION -#define HOST_ENTRY3_ACTION_BOFFSET 0 -#define HOST_ENTRY3_ACTION_BLEN 2 -#define HOST_ENTRY3_ACTION_FLAG HSL_RW - - -#define HOST_ENTRY4 -#define HOST_ENTRY4_OFFSET 0x0e58 -#define HOST_ENTRY4_E_LENGTH 4 -#define HOST_ENTRY4_E_OFFSET 0x0 -#define HOST_ENTRY4_NR_E 1 - -#define TBL_BUSY -#define HOST_ENTRY4_TBL_BUSY_BOFFSET 31 -#define HOST_ENTRY4_TBL_BUSY_BLEN 1 -#define HOST_ENTRY4_TBL_BUSY_FLAG HSL_RW - -#define SPEC_SP -#define HOST_ENTRY4_SPEC_SP_BOFFSET 22 -#define HOST_ENTRY4_SPEC_SP_BLEN 1 -#define HOST_ENTRY4_SPEC_SP_FLAG HSL_RW - -#define SPEC_VID -#define HOST_ENTRY4_SPEC_VID_BOFFSET 21 -#define HOST_ENTRY4_SPEC_VID_BLEN 1 -#define HOST_ENTRY4_SPEC_VID_FLAG HSL_RW - -#define SPEC_PIP -#define HOST_ENTRY4_SPEC_PIP_BOFFSET 20 -#define HOST_ENTRY4_SPEC_PIP_BLEN 1 -#define HOST_ENTRY4_SPEC_PIP_FLAG HSL_RW - -#define SPEC_SIP -#define HOST_ENTRY4_SPEC_SIP_BOFFSET 19 -#define HOST_ENTRY4_SPEC_SIP_BLEN 1 -#define HOST_ENTRY4_SPEC_SIP_FLAG HSL_RW - -#define SPEC_STATUS -#define HOST_ENTRY4_SPEC_STATUS_BOFFSET 18 -#define HOST_ENTRY4_SPEC_STATUS_BLEN 1 -#define HOST_ENTRY4_SPEC_STATUS_FLAG HSL_RW - -#define TBL_IDX -#define HOST_ENTRY4_TBL_IDX_BOFFSET 8 -#define HOST_ENTRY4_TBL_IDX_BLEN 10 -#define HOST_ENTRY4_TBL_IDX_FLAG HSL_RW - -#define TBL_STAUS -#define HOST_ENTRY4_TBL_STAUS_BOFFSET 7 -#define HOST_ENTRY4_TBL_STAUS_BLEN 1 -#define HOST_ENTRY4_TBL_STAUS_FLAG HSL_RW - -#define TBL_SEL -#define HOST_ENTRY4_TBL_SEL_BOFFSET 4 -#define HOST_ENTRY4_TBL_SEL_BLEN 2 -#define HOST_ENTRY4_TBL_SEL_FLAG HSL_RW - -#define ENTRY_FUNC -#define HOST_ENTRY4_ENTRY_FUNC_BOFFSET 0 -#define HOST_ENTRY4_ENTRY_FUNC_BLEN 3 -#define HOST_ENTRY4_ENTRY_FUNC_FLAG HSL_RW - - - - -#define NAT_ENTRY0 -#define NAT_ENTRY0_OFFSET 0x0e48 -#define NAT_ENTRY0_E_LENGTH 4 -#define NAT_ENTRY0_E_OFFSET 0x0 -#define NAT_ENTRY0_NR_E 1 - -#define IP_ADDR -#define NAT_ENTRY0_IP_ADDR_BOFFSET 0 -#define NAT_ENTRY0_IP_ADDR_BLEN 32 -#define NAT_ENTRY0_IP_ADDR_FLAG HSL_RW - - -#define NAT_ENTRY1 -#define NAT_ENTRY1_OFFSET 0x0e4c -#define NAT_ENTRY1_E_LENGTH 4 -#define NAT_ENTRY1_E_OFFSET 0x0 -#define NAT_ENTRY1_NR_E 1 - -#define PRV_IPADDR0 -#define NAT_ENTRY1_PRV_IPADDR0_BOFFSET 24 -#define NAT_ENTRY1_PRV_IPADDR0_BLEN 8 -#define NAT_ENTRY1_PRV_IPADDR0_FLAG HSL_RW - -#define PORT_RANGE -#define NAT_ENTRY1_PORT_RANGE_BOFFSET 16 -#define NAT_ENTRY1_PORT_RANGE_BLEN 8 -#define NAT_ENTRY1_PORT_RANGE_FLAG HSL_RW - -#define PORT_NUM -#define NAT_ENTRY1_PORT_NUM_BOFFSET 0 -#define NAT_ENTRY1_PORT_NUM_BLEN 16 -#define NAT_ENTRY1_PORT_NUM_FLAG HSL_RW - - -#define NAT_ENTRY2 -#define NAT_ENTRY2_OFFSET 0x0e50 -#define NAT_ENTRY2_E_LENGTH 4 -#define NAT_ENTRY2_E_OFFSET 0x0 -#define NAT_ENTRY2_NR_E 1 - -#define ENTRY_VALID -#define NAT_ENTRY2_ENTRY_VALID_BOFFSET 15 -#define NAT_ENTRY2_ENTRY_VALID_BLEN 1 -#define NAT_ENTRY2_ENTRY_VALID_FLAG HSL_RW - -#define PORT_EN -#define NAT_ENTRY2_PORT_EN_BOFFSET 14 -#define NAT_ENTRY2_PORT_EN_BLEN 1 -#define NAT_ENTRY2_PORT_EN_FLAG HSL_RW - -#define PRO_TYP -#define NAT_ENTRY2_PRO_TYP_BOFFSET 12 -#define NAT_ENTRY2_PRO_TYP_BLEN 2 -#define NAT_ENTRY2_PRO_TYP_FLAG HSL_RW - -#define HASH_KEY -#define NAT_ENTRY2_HASH_KEY_BOFFSET 10 -#define NAT_ENTRY2_HASH_KEY_BLEN 2 -#define NAT_ENTRY2_HASH_KEY_FLAG HSL_RW - -#define ACTION -#define NAT_ENTRY2_ACTION_BOFFSET 8 -#define NAT_ENTRY2_ACTION_BLEN 2 -#define NAT_ENTRY2_ACTION_FLAG HSL_RW - -#define CNT_EN -#define NAT_ENTRY2_CNT_EN_BOFFSET 7 -#define NAT_ENTRY2_CNT_EN_BLEN 1 -#define NAT_ENTRY2_CNT_EN_FLAG HSL_RW - -#define CNT_IDX -#define NAT_ENTRY2_CNT_IDX_BOFFSET 4 -#define NAT_ENTRY2_CNT_IDX_BLEN 3 -#define NAT_ENTRY2_CNT_IDX_FLAG HSL_RW - -#define PRV_IPADDR1 -#define NAT_ENTRY2_PRV_IPADDR1_BOFFSET 0 -#define NAT_ENTRY2_PRV_IPADDR1_BLEN 4 -#define NAT_ENTRY2_PRV_IPADDR1_FLAG HSL_RW - - - - -#define NAPT_ENTRY0 -#define NAPT_ENTRY0_OFFSET 0x0e48 -#define NAPT_ENTRY0_E_LENGTH 4 -#define NAPT_ENTRY0_E_OFFSET 0x0 -#define NAPT_ENTRY0_NR_E 1 - -#define DST_IPADDR -#define NAPT_ENTRY0_DST_IPADDR_BOFFSET 0 -#define NAPT_ENTRY0_DST_IPADDR_BLEN 32 -#define NAPT_ENTRY0_DST_IPADDR_FLAG HSL_RW - - -#define NAPT_ENTRY1 -#define NAPT_ENTRY1_OFFSET 0x0e4c -#define NAPT_ENTRY1_E_LENGTH 4 -#define NAPT_ENTRY1_E_OFFSET 0x0 -#define NAPT_ENTRY1_NR_E 1 - -#define SRC_PORT -#define NAPT_ENTRY1_SRC_PORT_BOFFSET 16 -#define NAPT_ENTRY1_SRC_PORT_BLEN 16 -#define NAPT_ENTRY1_SRC_PORT_FLAG HSL_RW - -#define DST_PORT -#define NAPT_ENTRY1_DST_PORT_BOFFSET 0 -#define NAPT_ENTRY1_DST_PORT_BLEN 16 -#define NAPT_ENTRY1_DST_PORT_FLAG HSL_RW - - -#define NAPT_ENTRY2 -#define NAPT_ENTRY2_OFFSET 0x0e50 -#define NAPT_ENTRY2_E_LENGTH 4 -#define NAPT_ENTRY2_E_OFFSET 0x0 -#define NAPT_ENTRY2_NR_E 1 - -#define SRC_IPADDR -#define NAPT_ENTRY2_SRC_IPADDR_BOFFSET 20 -#define NAPT_ENTRY2_SRC_IPADDR_BLEN 12 -#define NAPT_ENTRY2_SRC_IPADDR_FLAG HSL_RW - -#define TRANS_IPADDR -#define NAPT_ENTRY2_TRANS_IPADDR_BOFFSET 16 -#define NAPT_ENTRY2_TRANS_IPADDR_BLEN 4 -#define NAPT_ENTRY2_TRANS_IPADDR_FLAG HSL_RW - -#define TRANS_PORT -#define NAPT_ENTRY2_TRANS_PORT_BOFFSET 0 -#define NAPT_ENTRY2_TRANS_PORT_BLEN 16 -#define NAPT_ENTRY2_TRANS_PORT_FLAG HSL_RW - - -#define NAPT_ENTRY3 -#define NAPT_ENTRY3_OFFSET 0x0e54 -#define NAPT_ENTRY3_E_LENGTH 4 -#define NAPT_ENTRY3_E_OFFSET 0x0 -#define NAPT_ENTRY3_NR_E 1 - -#define AGE_FLAG -#define NAPT_ENTRY3_AGE_FLAG_BOFFSET 12 -#define NAPT_ENTRY3_AGE_FLAG_BLEN 4 -#define NAPT_ENTRY3_AGE_FLAG_FLAG HSL_RW - -#define CNT_EN -#define NAPT_ENTRY3_CNT_EN_BOFFSET 7 -#define NAPT_ENTRY3_CNT_EN_BLEN 1 -#define NAPT_ENTRY3_CNT_EN_FLAG HSL_RW - -#define CNT_IDX -#define NAPT_ENTRY3_CNT_IDX_BOFFSET 4 -#define NAPT_ENTRY3_CNT_IDX_BLEN 3 -#define NAPT_ENTRY3_CNT_IDX_FLAG HSL_RW - -#define PROT_TYP -#define NAPT_ENTRY3_PROT_TYP_BOFFSET 2 -#define NAPT_ENTRY3_PROT_TYP_BLEN 2 -#define NAPT_ENTRY3_PROT_TYP_FLAG HSL_RW - -#define ACTION -#define NAPT_ENTRY3_ACTION_BOFFSET 0 -#define NAPT_ENTRY3_ACTION_BLEN 2 -#define NAPT_ENTRY3_ACTION_FLAG HSL_RW - - - - -#define ROUTER_CTRL -#define ROUTER_CTRL_OFFSET 0x0e00 -#define ROUTER_CTRL_E_LENGTH 4 -#define ROUTER_CTRL_E_OFFSET 0x0 -#define ROUTER_CTRL_NR_E 1 - -#define ARP_LEARN_MODE -#define ROUTER_CTRL_ARP_LEARN_MODE_BOFFSET 19 -#define ROUTER_CTRL_ARP_LEARN_MODE_BLEN 1 -#define ROUTER_CTRL_ARP_LEARN_MODE_FLAG HSL_RW - -#define GLB_LOCKTIME -#define ROUTER_CTRL_GLB_LOCKTIME_BOFFSET 16 -#define ROUTER_CTRL_GLB_LOCKTIME_BLEN 2 -#define ROUTER_CTRL_GLB_LOCKTIME_FLAG HSL_RW - -#define ARP_AGE_TIME -#define ROUTER_CTRL_ARP_AGE_TIME_BOFFSET 8 -#define ROUTER_CTRL_ARP_AGE_TIME_BLEN 8 -#define ROUTER_CTRL_ARP_AGE_TIME_FLAG HSL_RW - -#define WCMP_HAHS_DP -#define ROUTER_CTRL_WCMP_HAHS_DP_BOFFSET 7 -#define ROUTER_CTRL_WCMP_HAHS_DP_BLEN 1 -#define ROUTER_CTRL_WCMP_HAHS_DP_FLAG HSL_RW - -#define WCMP_HAHS_DIP -#define ROUTER_CTRL_WCMP_HAHS_DIP_BOFFSET 6 -#define ROUTER_CTRL_WCMP_HAHS_DIP_BLEN 1 -#define ROUTER_CTRL_WCMP_HAHS_DIP_FLAG HSL_RW - -#define WCMP_HAHS_SP -#define ROUTER_CTRL_WCMP_HAHS_SP_BOFFSET 5 -#define ROUTER_CTRL_WCMP_HAHS_SP_BLEN 1 -#define ROUTER_CTRL_WCMP_HAHS_SP_FLAG HSL_RW - -#define WCMP_HAHS_SIP -#define ROUTER_CTRL_WCMP_HAHS_SIP_BOFFSET 4 -#define ROUTER_CTRL_WCMP_HAHS_SIP_BLEN 1 -#define ROUTER_CTRL_WCMP_HAHS_SIP_FLAG HSL_RW - -#define ARP_AGE_MODE -#define ROUTER_CTRL_ARP_AGE_MODE_BOFFSET 1 -#define ROUTER_CTRL_ARP_AGE_MODE_BLEN 1 -#define ROUTER_CTRL_ARP_AGE_MODE_FLAG HSL_RW - -#define ROUTER_EN -#define ROUTER_CTRL_ROUTER_EN_BOFFSET 0 -#define ROUTER_CTRL_ROUTER_EN_BLEN 1 -#define ROUTER_CTRL_ROUTER_EN_FLAG HSL_RW - - - - -#define ROUTER_PTCTRL0 -#define ROUTER_PTCTRL0_OFFSET 0x0e04 -#define ROUTER_PTCTRL0_E_LENGTH 4 -#define ROUTER_PTCTRL0_E_OFFSET 0x0 -#define ROUTER_PTCTRL0_NR_E 1 - - - - -#define ROUTER_PTCTRL1 -#define ROUTER_PTCTRL1_OFFSET 0x0e08 -#define ROUTER_PTCTRL1_E_LENGTH 4 -#define ROUTER_PTCTRL1_E_OFFSET 0x0 -#define ROUTER_PTCTRL1_NR_E 1 - - - -#define ROUTER_PTCTRL2 -#define ROUTER_PTCTRL2_OFFSET 0x0e0c -#define ROUTER_PTCTRL2_E_LENGTH 4 -#define ROUTER_PTCTRL2_E_OFFSET 0x0 -#define ROUTER_PTCTRL2_NR_E 1 - -#define ARP_PT_UP -#define ROUTER_PTCTRL2_ARP_PT_UP_BOFFSET 16 -#define ROUTER_PTCTRL2_ARP_PT_UP_BLEN 7 -#define ROUTER_PTCTRL2_ARP_PT_UP_FLAG HSL_RW - -#define ARP_LEARN_ACK -#define ROUTER_PTCTRL2_ARP_LEARN_ACK_BOFFSET 8 -#define ROUTER_PTCTRL2_ARP_LEARN_ACK_BLEN 7 -#define ROUTER_PTCTRL2_ARP_LEARN_ACK_FLAG HSL_RW - -#define ARP_LEARN_REQ -#define ROUTER_PTCTRL2_ARP_LEARN_REQ_BOFFSET 0 -#define ROUTER_PTCTRL2_ARP_LEARN_REQ_BLEN 7 -#define ROUTER_PTCTRL2_ARP_LEARN_REQ_FLAG HSL_RW - - - - -#define NAT_CTRL -#define NAT_CTRL_OFFSET 0x0e38 -#define NAT_CTRL_E_LENGTH 4 -#define NAT_CTRL_E_OFFSET 0x0 -#define NAT_CTRL_NR_E 1 - -#define NAT_HASH_MODE -#define NAT_CTRL_NAT_HASH_MODE_BOFFSET 5 -#define NAT_CTRL_NAT_HASH_MODE_BLEN 2 -#define NAT_CTRL_NAT_HASH_MODE_FLAG HSL_RW - -#define NAPT_OVERRIDE -#define NAT_CTRL_NAPT_OVERRIDE_BOFFSET 4 -#define NAT_CTRL_NAPT_OVERRIDE_BLEN 1 -#define NAT_CTRL_NAPT_OVERRIDE_FLAG HSL_RW - -#define NAPT_MODE -#define NAT_CTRL_NAPT_MODE_BOFFSET 2 -#define NAT_CTRL_NAPT_MODE_BLEN 2 -#define NAT_CTRL_NAPT_MODE_FLAG HSL_RW - -#define NAT_EN -#define NAT_CTRL_NAT_EN_BOFFSET 1 -#define NAT_CTRL_NAT_EN_BLEN 1 -#define NAT_CTRL_NAT_EN_FLAG HSL_RW - -#define NAPT_EN -#define NAT_CTRL_NAPT_EN_BOFFSET 0 -#define NAT_CTRL_NAPT_EN_BLEN 1 -#define NAT_CTRL_NAPT_EN_FLAG HSL_RW - - - - -#define PRV_BASEADDR -#define PRV_BASEADDR_OFFSET 0x0e5c -#define PRV_BASEADDR_E_LENGTH 4 -#define PRV_BASEADDR_E_OFFSET 0x0 -#define PRV_BASEADDR_NR_E 1 - -#define IP4_ADDR -#define PRV_BASEADDR_IP4_ADDR_BOFFSET 0 -#define PRV_BASEADDR_IP4_ADDR_BLEN 20 -#define PRV_BASEADDR_IP4_ADDR_FLAG HSL_RW - - - - -#define PRVIP_CTL -#define PRVIP_CTL_OFFSET 0x0418 -#define PRVIP_CTL_E_LENGTH 4 -#define PRVIP_CTL_E_OFFSET 0x0 -#define PRVIP_CTL_NR_E 1 - -#define BASEADDR_SEL -#define PRVIP_CTL_BASEADDR_SEL_BOFFSET 28 -#define PRVIP_CTL_BASEADDR_SEL_BLEN 1 -#define PRVIP_CTL_BASEADDR_SEL_FLAG HSL_RW - -#define IP4_BASEADDR -#define PRVIP_CTL_IP4_BASEADDR_BOFFSET 0 -#define PRVIP_CTL_IP4_BASEADDR_BLEN 20 -#define PRVIP_CTL_IP4_BASEADDR_FLAG HSL_RW - - -#define OFFLOAD_PRVIP_CTL -#define OFFLOAD_PRVIP_CTL_OFFSET 0x0e5c -#define OFFLOAD_PRVIP_CTL_E_LENGTH 4 -#define OFFLOAD_PRVIP_CTL_E_OFFSET 0x0 -#define OFFLOAD_PRVIP_CTL_NR_E 1 - -#define IP4_BASEADDR -#define OFFLOAD_PRVIP_CTL_IP4_BASEADDR_BOFFSET 0 -#define OFFLOAD_PRVIP_CTL_IP4_BASEADDR_BLEN 20 -#define OFFLOAD_PRVIP_CTL_IP4_BASEADDR_FLAG HSL_RW - - - - -#define PUB_ADDR0 -#define PUB_ADDR0_OFFSET 0x5aa00 -#define PUB_ADDR0_E_LENGTH 4 -#define PUB_ADDR0_E_OFFSET 0x0 -#define PUB_ADDR0_NR_E 1 - -#define IP4_ADDR -#define PUB_ADDR0_IP4_ADDR_BOFFSET 0 -#define PUB_ADDR0_IP4_ADDR_BLEN 32 -#define PUB_ADDR0_IP4_ADDR_FLAG HSL_RW - - -#define PUB_ADDR1 -#define PUB_ADDR1_OFFSET 0x5aa04 -#define PUB_ADDR1_E_LENGTH 4 -#define PUB_ADDR1_E_OFFSET 0x0 -#define PUB_ADDR1_NR_E 1 - -#define ADDR_VALID -#define PUB_ADDR1_ADDR_VALID_BOFFSET 0 -#define PUB_ADDR1_ADDR_VALID_BLEN 1 -#define PUB_ADDR1_ADDR_VALID_FLAG HSL_RW - - - - -#define INTF_ADDR_ENTRY0 -#define INTF_ADDR_ENTRY0_OFFSET 0x5aa00 -#define INTF_ADDR_ENTRY0_E_LENGTH 4 -#define INTF_ADDR_ENTRY0_E_OFFSET 0x0 -#define INTF_ADDR_ENTRY0_NR_E 8 - -#define MAC_ADDR2 -#define INTF_ADDR_ENTRY0_MAC_ADDR2_BOFFSET 24 -#define INTF_ADDR_ENTRY0_MAC_ADDR2_BLEN 8 -#define INTF_ADDR_ENTRY0_MAC_ADDR2_FLAG HSL_RW - -#define MAC_ADDR3 -#define INTF_ADDR_ENTRY0_MAC_ADDR3_BOFFSET 16 -#define INTF_ADDR_ENTRY0_MAC_ADDR3_BLEN 8 -#define INTF_ADDR_ENTRY0_MAC_ADDR3_FLAG HSL_RW - -#define MAC_ADDR4 -#define INTF_ADDR_ENTRY0_MAC_ADDR4_BOFFSET 8 -#define INTF_ADDR_ENTRY0_MAC_ADDR4_BLEN 8 -#define INTF_ADDR_ENTRY0_MAC_ADDR4_FLAG HSL_RW - -#define MAC_ADDR5 -#define INTF_ADDR_ENTRY0_MAC_ADDR5_BOFFSET 0 -#define INTF_ADDR_ENTRY0_MAC_ADDR5_BLEN 8 -#define INTF_ADDR_ENTRY0_MAC_ADDR5_FLAG HSL_RW - - -#define INTF_ADDR_ENTRY1 -#define INTF_ADDR_ENTRY1_OFFSET 0x5aa04 -#define INTF_ADDR_ENTRY1_E_LENGTH 4 -#define INTF_ADDR_ENTRY1_E_OFFSET 0x0 -#define INTF_ADDR_ENTRY1_NR_E 8 - -#define VID_HIGH0 -#define INTF_ADDR_ENTRY1_VID_HIGH0_BOFFSET 28 -#define INTF_ADDR_ENTRY1_VID_HIGH0_BLEN 4 -#define INTF_ADDR_ENTRY1_VID_HIGH0_FLAG HSL_RW - -#define VID_LOW -#define INTF_ADDR_ENTRY1_VID_LOW_BOFFSET 16 -#define INTF_ADDR_ENTRY1_VID_LOW_BLEN 12 -#define INTF_ADDR_ENTRY1_VID_LOW_FLAG HSL_RW - -#define MAC_ADDR0 -#define INTF_ADDR_ENTRY1_MAC_ADDR0_BOFFSET 8 -#define INTF_ADDR_ENTRY1_MAC_ADDR0_BLEN 8 -#define INTF_ADDR_ENTRY1_MAC_ADDR0_FLAG HSL_RW - -#define MAC_ADDR1 -#define INTF_ADDR_ENTRY1_MAC_ADDR1_BOFFSET 0 -#define INTF_ADDR_ENTRY1_MAC_ADDR1_BLEN 8 -#define INTF_ADDR_ENTRY1_MAC_ADDR1_FLAG HSL_RW - - -#define INTF_ADDR_ENTRY2 -#define INTF_ADDR_ENTRY2_OFFSET 0x5aa08 -#define INTF_ADDR_ENTRY2_E_LENGTH 4 -#define INTF_ADDR_ENTRY2_E_OFFSET 0x0 -#define INTF_ADDR_ENTRY2_NR_E 8 - -#define IP6_ROUTE -#define INTF_ADDR_ENTRY2_IP6_ROUTE_BOFFSET 9 -#define INTF_ADDR_ENTRY2_IP6_ROUTE_BLEN 1 -#define INTF_ADDR_ENTRY2_IP6_ROUTE_FLAG HSL_RW - -#define IP4_ROUTE -#define INTF_ADDR_ENTRY2_IP4_ROUTE_BOFFSET 8 -#define INTF_ADDR_ENTRY2_IP4_ROUTE_BLEN 1 -#define INTF_ADDR_ENTRY2_IP4_ROUTE_FLAG HSL_RW - -#define VID_HIGH1 -#define INTF_ADDR_ENTRY2_VID_HIGH1_BOFFSET 0 -#define INTF_ADDR_ENTRY2_VID_HIGH1_BLEN 8 -#define INTF_ADDR_ENTRY2_VID_HIGH1_FLAG HSL_RW - - - - - /* Port Shaper Register0 */ -#define EG_SHAPER0 -#define EG_SHAPER0_OFFSET 0x0890 -#define EG_SHAPER0_E_LENGTH 4 -#define EG_SHAPER0_E_OFFSET 0x0020 -#define EG_SHAPER0_NR_E 7 - -#define EG_Q1_CIR -#define EG_SHAPER0_EG_Q1_CIR_BOFFSET 16 -#define EG_SHAPER0_EG_Q1_CIR_BLEN 15 -#define EG_SHAPER0_EG_Q1_CIR_FLAG HSL_RW - -#define EG_Q0_CIR -#define EG_SHAPER0_EG_Q0_CIR_BOFFSET 0 -#define EG_SHAPER0_EG_Q0_CIR_BLEN 15 -#define EG_SHAPER0_EG_Q0_CIR_FLAG HSL_RW - - - /* Port Shaper Register1 */ -#define EG_SHAPER1 -#define EG_SHAPER1_OFFSET 0x0894 -#define EG_SHAPER1_E_LENGTH 4 -#define EG_SHAPER1_E_OFFSET 0x0020 -#define EG_SHAPER1_NR_E 7 - -#define EG_Q3_CIR -#define EG_SHAPER1_EG_Q3_CIR_BOFFSET 16 -#define EG_SHAPER1_EG_Q3_CIR_BLEN 15 -#define EG_SHAPER1_EG_Q3_CIR_FLAG HSL_RW - -#define EG_Q2_CIR -#define EG_SHAPER1_EG_Q2_CIR_BOFFSET 0 -#define EG_SHAPER1_EG_Q2_CIR_BLEN 15 -#define EG_SHAPER1_EG_Q2_CIR_FLAG HSL_RW - - - /* Port Shaper Register2 */ -#define EG_SHAPER2 -#define EG_SHAPER2_OFFSET 0x0898 -#define EG_SHAPER2_E_LENGTH 4 -#define EG_SHAPER2_E_OFFSET 0x0020 -#define EG_SHAPER2_NR_E 7 - -#define EG_Q5_CIR -#define EG_SHAPER2_EG_Q5_CIR_BOFFSET 16 -#define EG_SHAPER2_EG_Q5_CIR_BLEN 15 -#define EG_SHAPER2_EG_Q5_CIR_FLAG HSL_RW - -#define EG_Q4_CIR -#define EG_SHAPER2_EG_Q4_CIR_BOFFSET 0 -#define EG_SHAPER2_EG_Q4_CIR_BLEN 15 -#define EG_SHAPER2_EG_Q4_CIR_FLAG HSL_RW - - - /* Port Shaper Register3 */ -#define EG_SHAPER3 -#define EG_SHAPER3_OFFSET 0x089c -#define EG_SHAPER3_E_LENGTH 4 -#define EG_SHAPER3_E_OFFSET 0x0020 -#define EG_SHAPER3_NR_E 7 - -#define EG_Q1_EIR -#define EG_SHAPER3_EG_Q1_EIR_BOFFSET 16 -#define EG_SHAPER3_EG_Q1_EIR_BLEN 15 -#define EG_SHAPER3_EG_Q1_EIR_FLAG HSL_RW - -#define EG_Q0_EIR -#define EG_SHAPER3_EG_Q0_EIR_BOFFSET 0 -#define EG_SHAPER3_EG_Q0_EIR_BLEN 15 -#define EG_SHAPER3_EG_Q0_EIR_FLAG HSL_RW - - - /* Port Shaper Register4 */ -#define EG_SHAPER4 -#define EG_SHAPER4_OFFSET 0x08a0 -#define EG_SHAPER4_E_LENGTH 4 -#define EG_SHAPER4_E_OFFSET 0x0020 -#define EG_SHAPER4_NR_E 7 - -#define EG_Q3_EIR -#define EG_SHAPER4_EG_Q3_EIR_BOFFSET 16 -#define EG_SHAPER4_EG_Q3_EIR_BLEN 15 -#define EG_SHAPER4_EG_Q3_EIR_FLAG HSL_RW - -#define EG_Q2_EIR -#define EG_SHAPER4_EG_Q2_EIR_BOFFSET 0 -#define EG_SHAPER4_EG_Q2_EIR_BLEN 15 -#define EG_SHAPER4_EG_Q2_EIR_FLAG HSL_RW - - - /* Port Shaper Register5 */ -#define EG_SHAPER5 -#define EG_SHAPER5_OFFSET 0x08a4 -#define EG_SHAPER5_E_LENGTH 4 -#define EG_SHAPER5_E_OFFSET 0x0020 -#define EG_SHAPER5_NR_E 7 - -#define EG_Q5_EIR -#define EG_SHAPER5_EG_Q5_EIR_BOFFSET 16 -#define EG_SHAPER5_EG_Q5_EIR_BLEN 15 -#define EG_SHAPER5_EG_Q5_EIR_FLAG HSL_RW - -#define EG_Q4_EIR -#define EG_SHAPER5_EG_Q4_EIR_BOFFSET 0 -#define EG_SHAPER5_EG_Q4_EIR_BLEN 15 -#define EG_SHAPER5_EG_Q4_EIR_FLAG HSL_RW - - - /* Port Shaper Register6 */ -#define EG_SHAPER6 -#define EG_SHAPER6_OFFSET 0x08a8 -#define EG_SHAPER6_E_LENGTH 4 -#define EG_SHAPER6_E_OFFSET 0x0020 -#define EG_SHAPER6_NR_E 7 - -#define EG_Q3_CBS -#define EG_SHAPER6_EG_Q3_CBS_BOFFSET 28 -#define EG_SHAPER6_EG_Q3_CBS_BLEN 3 -#define EG_SHAPER6_EG_Q3_CBS_FLAG HSL_RW - -#define EG_Q3_EBS -#define EG_SHAPER6_EG_Q3_EBS_BOFFSET 24 -#define EG_SHAPER6_EG_Q3_EBS_BLEN 3 -#define EG_SHAPER6_EG_Q3_EBS_FLAG HSL_RW - -#define EG_Q2_CBS -#define EG_SHAPER6_EG_Q2_CBS_BOFFSET 20 -#define EG_SHAPER6_EG_Q2_CBS_BLEN 3 -#define EG_SHAPER6_EG_Q2_CBS_FLAG HSL_RW - -#define EG_Q2_EBS -#define EG_SHAPER6_EG_Q2_EBS_BOFFSET 16 -#define EG_SHAPER6_EG_Q2_EBS_BLEN 3 -#define EG_SHAPER6_EG_Q2_EBS_FLAG HSL_RW - -#define EG_Q1_CBS -#define EG_SHAPER6_EG_Q1_CBS_BOFFSET 12 -#define EG_SHAPER6_EG_Q1_CBS_BLEN 3 -#define EG_SHAPER6_EG_Q1_CBS_FLAG HSL_RW - -#define EG_Q1_EBS -#define EG_SHAPER6_EG_Q1_EBS_BOFFSET 8 -#define EG_SHAPER6_EG_Q1_EBS_BLEN 3 -#define EG_SHAPER6_EG_Q1_EBS_FLAG HSL_RW - -#define EG_Q0_CBS -#define EG_SHAPER6_EG_Q0_CBS_BOFFSET 4 -#define EG_SHAPER6_EG_Q0_CBS_BLEN 3 -#define EG_SHAPER6_EG_Q0_CBS_FLAG HSL_RW - -#define EG_Q0_EBS -#define EG_SHAPER6_EG_Q0_EBS_BOFFSET 0 -#define EG_SHAPER6_EG_Q0_EBS_BLEN 3 -#define EG_SHAPER6_EG_Q0_EBS_FLAG HSL_RW - - - /* Port Shaper Register7 */ -#define EG_SHAPER7 -#define EG_SHAPER7_OFFSET 0x08ac -#define EG_SHAPER7_E_LENGTH 4 -#define EG_SHAPER7_E_OFFSET 0x0020 -#define EG_SHAPER7_NR_E 7 - -#define EG_Q5_CBS -#define EG_SHAPER7_EG_Q5_CBS_BOFFSET 28 -#define EG_SHAPER7_EG_Q5_CBS_BLEN 3 -#define EG_SHAPER7_EG_Q5_CBS_FLAG HSL_RW - -#define EG_Q5_EBS -#define EG_SHAPER7_EG_Q5_EBS_BOFFSET 24 -#define EG_SHAPER7_EG_Q5_EBS_BLEN 3 -#define EG_SHAPER7_EG_Q5_EBS_FLAG HSL_RW - -#define EG_Q4_CBS -#define EG_SHAPER7_EG_Q4_CBS_BOFFSET 20 -#define EG_SHAPER7_EG_Q4_CBS_BLEN 3 -#define EG_SHAPER7_EG_Q4_CBS_FLAG HSL_RW - -#define EG_Q4_EBS -#define EG_SHAPER7_EG_Q4_EBS_BOFFSET 16 -#define EG_SHAPER7_EG_Q4_EBS_BLEN 3 -#define EG_SHAPER7_EG_Q4_EBS_FLAG HSL_RW - -#define EG_Q5_UNIT -#define EG_SHAPER7_EG_Q5_UNIT_BOFFSET 13 -#define EG_SHAPER7_EG_Q5_UNIT_BLEN 1 -#define EG_SHAPER7_EG_Q5_UNIT_FLAG HSL_RW - -#define EG_Q4_UNIT -#define EG_SHAPER7_EG_Q4_UNIT_BOFFSET 12 -#define EG_SHAPER7_EG_Q4_UNIT_BLEN 1 -#define EG_SHAPER7_EG_Q4_UNIT_FLAG HSL_RW - -#define EG_Q3_UNIT -#define EG_SHAPER7_EG_Q3_UNIT_BOFFSET 11 -#define EG_SHAPER7_EG_Q3_UNIT_BLEN 1 -#define EG_SHAPER7_EG_Q3_UNIT_FLAG HSL_RW - -#define EG_Q2_UNIT -#define EG_SHAPER7_EG_Q2_UNIT_BOFFSET 10 -#define EG_SHAPER7_EG_Q2_UNIT_BLEN 1 -#define EG_SHAPER7_EG_Q2_UNIT_FLAG HSL_RW - -#define EG_Q1_UNIT -#define EG_SHAPER7_EG_Q1_UNIT_BOFFSET 9 -#define EG_SHAPER7_EG_Q1_UNIT_BLEN 1 -#define EG_SHAPER7_EG_Q1_UNIT_FLAG HSL_RW - -#define EG_Q0_UNIT -#define EG_SHAPER7_EG_Q0_UNIT_BOFFSET 8 -#define EG_SHAPER7_EG_Q0_UNIT_BLEN 1 -#define EG_SHAPER7_EG_Q0_UNIT_FLAG HSL_RW - -#define EG_PT -#define EG_SHAPER7_EG_PT_BOFFSET 3 -#define EG_SHAPER7_EG_PT_BLEN 1 -#define EG_SHAPER7_EG_PT_FLAG HSL_RW - -#define EG_TS -#define EG_SHAPER7_EG_TS_BOFFSET 0 -#define EG_SHAPER7_EG_TS_BLEN 3 -#define EG_SHAPER7_EG_TS_FLAG HSL_RW - - - - /* ACL Policer Register0 */ -#define ACL_POLICER0 -#define ACL_POLICER0_OFFSET 0x0a00 -#define ACL_POLICER0_E_LENGTH 4 -#define ACL_POLICER0_E_OFFSET 0x0008 -#define ACL_POLICER0_NR_E 32 - -#define ACL_CBS -#define ACL_POLICER0_ACL_CBS_BOFFSET 15 -#define ACL_POLICER0_ACL_CBS_BLEN 3 -#define ACL_POLICER0_ACL_CBS_FLAG HSL_RW - -#define ACL_CIR -#define ACL_POLICER0_ACL_CIR_BOFFSET 0 -#define ACL_POLICER0_ACL_CIR_BLEN 15 -#define ACL_POLICER0_ACL_CIR_FLAG HSL_RW - - - /* ACL Policer Register1 */ -#define ACL_POLICER1 -#define ACL_POLICER1_OFFSET 0x0a04 -#define ACL_POLICER1_E_LENGTH 4 -#define ACL_POLICER1_E_OFFSET 0x0008 -#define ACL_POLICER1_NR_E 32 - -#define ACL_BORROW -#define ACL_POLICER1_ACL_BORROW_BOFFSET 23 -#define ACL_POLICER1_ACL_BORROW_BLEN 1 -#define ACL_POLICER1_ACL_BORROW_FLAG HSL_RW - -#define ACL_UNIT -#define ACL_POLICER1_ACL_UNIT_BOFFSET 22 -#define ACL_POLICER1_ACL_UNIT_BLEN 1 -#define ACL_POLICER1_ACL_UNIT_FLAG HSL_RW - -#define ACL_CF -#define ACL_POLICER1_ACL_CF_BOFFSET 21 -#define ACL_POLICER1_ACL_CF_BLEN 1 -#define ACL_POLICER1_ACL_CF_FLAG HSL_RW - -#define ACL_CM -#define ACL_POLICER1_ACL_CM_BOFFSET 20 -#define ACL_POLICER1_ACL_CM_BLEN 1 -#define ACL_POLICER1_ACL_CM_FLAG HSL_RW - -#define ACL_TS -#define ACL_POLICER1_ACL_TS_BOFFSET 18 -#define ACL_POLICER1_ACL_TS_BLEN 2 -#define ACL_POLICER1_ACL_TS_FLAG HSL_RW - -#define ACL_EBS -#define ACL_POLICER1_ACL_EBS_BOFFSET 15 -#define ACL_POLICER1_ACL_EBS_BLEN 3 -#define ACL_POLICER1_ACL_EBS_FLAG HSL_RW - -#define ACL_EIR -#define ACL_POLICER1_ACL_EIR_BOFFSET 0 -#define ACL_POLICER1_ACL_EIR_BLEN 15 -#define ACL_POLICER1_ACL_EIR_FLAG HSL_RW - - - /* ACL Counter Register0 */ -#define ACL_COUNTER0 -#define ACL_COUNTER0_OFFSET 0x1c000 -#define ACL_COUNTER0_E_LENGTH 4 -#define ACL_COUNTER0_E_OFFSET 0x0008 -#define ACL_COUNTER0_NR_E 32 - - /* ACL Counter Register1 */ -#define ACL_COUNTER1 -#define ACL_COUNTER1_OFFSET 0x1c004 -#define ACL_COUNTER1_E_LENGTH 4 -#define ACL_COUNTER1_E_OFFSET 0x0008 -#define ACL_COUNTER1_NR_E 32 - - - - - /* INGRESS Policer Register0 */ -#define INGRESS_POLICER0 -#define INGRESS_POLICER0_OFFSET 0x0b00 -#define INGRESS_POLICER0_E_LENGTH 4 -#define INGRESS_POLICER0_E_OFFSET 0x0010 -#define INGRESS_POLICER0_NR_E 7 - -#define ADD_RATE_BYTE -#define INGRESS_POLICER0_ADD_RATE_BYTE_BOFFSET 24 -#define INGRESS_POLICER0_ADD_RATE_BYTE_BLEN 8 -#define INGRESS_POLICER0_ADD_RATE_BYTE_FLAG HSL_RW - -#define C_ING_TS -#define INGRESS_POLICER0_C_ING_TS_BOFFSET 22 -#define INGRESS_POLICER0_C_ING_TS_BLEN 2 -#define INGRESS_POLICER0_C_ING_TS_FLAG HSL_RW - -#define RATE_MODE -#define INGRESS_POLICER0_RATE_MODE_BOFFSET 20 -#define INGRESS_POLICER0_RATE_MODE_BLEN 1 -#define INGRESS_POLICER0_RATE_MODE_FLAG HSL_RW - -#define INGRESS_CBS -#define INGRESS_POLICER0_INGRESS_CBS_BOFFSET 15 -#define INGRESS_POLICER0_INGRESS_CBS_BLEN 3 -#define INGRESS_POLICER0_INGRESS_CBS_FLAG HSL_RW - -#define INGRESS_CIR -#define INGRESS_POLICER0_INGRESS_CIR_BOFFSET 0 -#define INGRESS_POLICER0_INGRESS_CIR_BLEN 15 -#define INGRESS_POLICER0_INGRESS_CIR_FLAG HSL_RW - - - /* INGRESS Policer Register1 */ -#define INGRESS_POLICER1 -#define INGRESS_POLICER1_OFFSET 0x0b04 -#define INGRESS_POLICER1_E_LENGTH 4 -#define INGRESS_POLICER1_E_OFFSET 0x0010 -#define INGRESS_POLICER1_NR_E 7 - -#define INGRESS_BORROW -#define INGRESS_POLICER1_INGRESS_BORROW_BOFFSET 23 -#define INGRESS_POLICER1_INGRESS_BORROW_BLEN 1 -#define INGRESS_POLICER1_INGRESS_BORROW_FLAG HSL_RW - -#define INGRESS_UNIT -#define INGRESS_POLICER1_INGRESS_UNIT_BOFFSET 22 -#define INGRESS_POLICER1_INGRESS_UNIT_BLEN 1 -#define INGRESS_POLICER1_INGRESS_UNIT_FLAG HSL_RW - -#define INGRESS_CF -#define INGRESS_POLICER1_INGRESS_CF_BOFFSET 21 -#define INGRESS_POLICER1_INGRESS_CF_BLEN 1 -#define INGRESS_POLICER1_INGRESS_CF_FLAG HSL_RW - -#define INGRESS_CM -#define INGRESS_POLICER1_INGRESS_CM_BOFFSET 20 -#define INGRESS_POLICER1_INGRESS_CM_BLEN 1 -#define INGRESS_POLICER1_INGRESS_CM_FLAG HSL_RW - -#define E_ING_TS -#define INGRESS_POLICER1_E_ING_TS_BOFFSET 18 -#define INGRESS_POLICER1_E_ING_TS_BLEN 2 -#define INGRESS_POLICER1_E_ING_TS_FLAG HSL_RW - -#define INGRESS_EBS -#define INGRESS_POLICER1_INGRESS_EBS_BOFFSET 15 -#define INGRESS_POLICER1_INGRESS_EBS_BLEN 3 -#define INGRESS_POLICER1_INGRESS_EBS_FLAG HSL_RW - -#define INGRESS_EIR -#define INGRESS_POLICER1_INGRESS_EIR_BOFFSET 0 -#define INGRESS_POLICER1_INGRESS_EIR_BLEN 15 -#define INGRESS_POLICER1_INGRESS_EIR_FLAG HSL_RW - - - /* INGRESS Policer Register2 */ -#define INGRESS_POLICER2 -#define INGRESS_POLICER2_OFFSET 0x0b08 -#define INGRESS_POLICER2_E_LENGTH 4 -#define INGRESS_POLICER2_E_OFFSET 0x0010 -#define INGRESS_POLICER2_NR_E 7 - -#define C_MUL -#define INGRESS_POLICER2_C_MUL_BOFFSET 15 -#define INGRESS_POLICER2_C_MUL_BLEN 1 -#define INGRESS_POLICER2_C_UNK_MUL_FLAG HSL_RW - -#define C_UNI -#define INGRESS_POLICER2_C_UNI_BOFFSET 14 -#define INGRESS_POLICER2_C_UNI_BLEN 1 -#define INGRESS_POLICER2_C_UNI_FLAG HSL_RW - -#define C_UNK_MUL -#define INGRESS_POLICER2_C_UNK_MUL_BOFFSET 13 -#define INGRESS_POLICER2_C_UNK_MUL_BLEN 1 -#define INGRESS_POLICER2_C_UNK_MUL_FLAG HSL_RW - -#define C_UNK_UNI -#define INGRESS_POLICER2_C_UNK_UNI_BOFFSET 12 -#define INGRESS_POLICER2_C_UNK_UNI_BLEN 1 -#define INGRESS_POLICER2_C_UNK_UNI_FLAG HSL_RW - -#define C_BROAD -#define INGRESS_POLICER2_C_BROAD_BOFFSET 11 -#define INGRESS_POLICER2_C_BROAD_BLEN 1 -#define INGRESS_POLICER2_C_BROAD_FLAG HSL_RW - -#define C_MANAGE -#define INGRESS_POLICER2_C_MANAGC_BOFFSET 10 -#define INGRESS_POLICER2_C_MANAGC_BLEN 1 -#define INGRESS_POLICER2_C_MANAGC_FLAG HSL_RW - -#define C_TCP -#define INGRESS_POLICER2_C_TCP_BOFFSET 9 -#define INGRESS_POLICER2_C_TCP_BLEN 1 -#define INGRESS_POLICER2_C_TCP_FLAG HSL_RW - -#define C_MIRR -#define INGRESS_POLICER2_C_MIRR_BOFFSET 8 -#define INGRESS_POLICER2_C_MIRR_BLEN 1 -#define INGRESS_POLICER2_C_MIRR_FLAG HSL_RW - -#define E_MUL -#define INGRESS_POLICER2_E_MUL_BOFFSET 7 -#define INGRESS_POLICER2_E_MUL_BLEN 1 -#define INGRESS_POLICER2_E_UNK_MUL_FLAG HSL_RW - -#define E_UNI -#define INGRESS_POLICER2_E_UNI_BOFFSET 6 -#define INGRESS_POLICER2_E_UNI_BLEN 1 -#define INGRESS_POLICER2_E_UNI_FLAG HSL_RW - -#define E_UNK_MUL -#define INGRESS_POLICER2_E_UNK_MUL_BOFFSET 5 -#define INGRESS_POLICER2_E_UNK_MUL_BLEN 1 -#define INGRESS_POLICER2_E_UNK_MUL_FLAG HSL_RW - -#define E_UNK_UNI -#define INGRESS_POLICER2_E_UNK_UNI_BOFFSET 4 -#define INGRESS_POLICER2_E_UNK_UNI_BLEN 1 -#define INGRESS_POLICER2_E_UNK_UNI_FLAG HSL_RW - -#define E_BROAD -#define INGRESS_POLICER2_E_BROAD_BOFFSET 3 -#define INGRESS_POLICER2_E_BROAD_BLEN 1 -#define INGRESS_POLICER2_E_BROAD_FLAG HSL_RW - -#define E_MANAGE -#define INGRESS_POLICER2_E_MANAGE_BOFFSET 2 -#define INGRESS_POLICER2_E_MANAGE_BLEN 1 -#define INGRESS_POLICER2_E_MANAGE_FLAG HSL_RW - -#define E_TCP -#define INGRESS_POLICER2_E_TCP_BOFFSET 1 -#define INGRESS_POLICER2_E_TCP_BLEN 1 -#define INGRESS_POLICER2_E_TCP_FLAG HSL_RW - -#define E_MIRR -#define INGRESS_POLICER2_E_MIRR_BOFFSET 0 -#define INGRESS_POLICER2_E_MIRR_BLEN 1 -#define INGRESS_POLICER2_E_MIRR_FLAG HSL_RW - - - - - /* Port Rate Limit2 Register */ -#define WRR_CTRL -#define WRR_CTRL_OFFSET 0x0830 -#define WRR_CTRL_E_LENGTH 4 -#define WRR_CTRL_E_OFFSET 0x0004 -#define WRR_CTRL_NR_E 7 - -#define SCH_MODE -#define WRR_CTRL_SCH_MODE_BOFFSET 30 -#define WRR_CTRL_SCH_MODE_BLEN 2 -#define WRR_CTRL_SCH_MODE_FLAG HSL_RW - -#define Q5_W -#define WRR_CTRL_Q5_W_BOFFSET 25 -#define WRR_CTRL_Q5_W_BLEN 5 -#define WRR_CTRL_Q5_W_FLAG HSL_RW - -#define Q4_W -#define WRR_CTRL_Q4_W_BOFFSET 20 -#define WRR_CTRL_Q4_W_BLEN 5 -#define WRR_CTRL_Q4_W_FLAG HSL_RW - -#define Q3_W -#define WRR_CTRL_Q3_W_BOFFSET 15 -#define WRR_CTRL_Q3_W_BLEN 5 -#define WRR_CTRL_Q3_W_FLAG HSL_RW - -#define Q2_W -#define WRR_CTRL_Q2_W_BOFFSET 10 -#define WRR_CTRL_Q2_W_BLEN 5 -#define WRR_CTRL_Q2_W_FLAG HSL_RW - -#define Q1_W -#define WRR_CTRL_Q1_W_BOFFSET 5 -#define WRR_CTRL_Q1_W_BLEN 5 -#define WRR_CTRL_Q1_W_FLAG HSL_RW - -#define Q0_W -#define WRR_CTRL_Q0_W_BOFFSET 0 -#define WRR_CTRL_Q0_W_BLEN 5 -#define WRR_CTRL_Q0_W_FLAG HSL_RW - - - - - -#ifdef __cplusplus -} -#endif /* __cplusplus */ -#endif /* _ISIS_REG_H_ */ - diff --git a/feeds/ipq807x/qca-ssdk/src/include/hsl/isis/isis_reg_access.h b/feeds/ipq807x/qca-ssdk/src/include/hsl/isis/isis_reg_access.h deleted file mode 100755 index 22fc6ca17..000000000 --- a/feeds/ipq807x/qca-ssdk/src/include/hsl/isis/isis_reg_access.h +++ /dev/null @@ -1,124 +0,0 @@ -/* - * Copyright (c) 2012,2018, The Linux Foundation. All rights reserved. - * Permission to use, copy, modify, and/or distribute this software for - * any purpose with or without fee is hereby granted, provided that the - * above copyright notice and this permission notice appear in all copies. - * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES - * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR - * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES - * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN - * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT - * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. - */ - - - -#ifndef _ISIS_REG_ACCESS_H_ -#define _ISIS_REG_ACCESS_H_ - -#ifdef __cplusplus -extern "C" { -#endif /* __cplusplus */ - -#include "sw.h" - -#define ISIS_HEADER_CMD_LEN 8 -#define ISIS_HEADER_DATA_LEN 4 -#define ISIS_HEADER_LEN 4 -#define ISIS_HEADER_MAX_DATA_LEN 16 -#define VID_LEN 2 -#define ATHRS_HEADER_4BYTE_VAL 0xaaaa - - typedef enum { - NORMAL_PACKET, - RESERVED0, - MIB_1ST, - RESERVED1, - RESERVED2, - READ_WRITE_REG, - READ_WRITE_REG_ACK, - RESERVED3 - } - ATHRS_HEADER_TYPE; - - typedef struct - { - a_uint8_t version; - a_uint8_t priority; - a_uint8_t type ; - a_uint8_t broadcast; - a_uint8_t from_cpu; - a_uint8_t port_num; - } athrs_header_t; - - typedef struct - { - a_uint32_t reg_addr; - a_uint8_t cmd_len; - a_uint8_t cmd; - a_uint16_t check_code; - a_uint32_t seq_num; - } athrs_header_regcmd_t; - - typedef struct - { - a_uint8_t data[ISIS_HEADER_MAX_DATA_LEN]; - a_uint8_t len; - a_uint16_t athrs_4byte_value; - volatile a_uint32_t seq; - } athrs_cmd_resp_t; - - sw_error_t - isis_phy_get(a_uint32_t dev_id, a_uint32_t phy_addr, - a_uint32_t reg, a_uint16_t * value); - - sw_error_t - isis_phy_set(a_uint32_t dev_id, a_uint32_t phy_addr, - a_uint32_t reg, a_uint16_t value); - - sw_error_t - isis_reg_get(a_uint32_t dev_id, a_uint32_t reg_addr, a_uint8_t value[], - a_uint32_t value_len); - - sw_error_t - isis_reg_set(a_uint32_t dev_id, a_uint32_t reg_addr, a_uint8_t value[], - a_uint32_t value_len); - - sw_error_t - isis_reg_field_get(a_uint32_t dev_id, a_uint32_t reg_addr, - a_uint32_t bit_offset, a_uint32_t field_len, - a_uint8_t value[], a_uint32_t value_len); - - sw_error_t - isis_reg_field_set(a_uint32_t dev_id, a_uint32_t reg_addr, - a_uint32_t bit_offset, a_uint32_t field_len, - const a_uint8_t value[], a_uint32_t value_len); - - sw_error_t - isis_regsiter_dump(a_uint32_t dev_id,a_uint32_t register_idx, fal_reg_dump_t * reg_dump); - - sw_error_t - isis_debug_regsiter_dump(a_uint32_t dev_id, fal_debug_reg_dump_t * dbg_reg_dump); - - - sw_error_t - isis_reg_access_init(a_uint32_t dev_id, hsl_access_mode mode); - - sw_error_t - isis_access_mode_set(a_uint32_t dev_id, hsl_access_mode mode); - - int - isis_reg_config_header (a_uint8_t *header, a_uint8_t wr_flag, - a_uint32_t reg_addr, a_uint8_t cmd_len, - a_uint8_t *val, a_uint32_t seq_num); - - sw_error_t isis_reg_parser_header_skb(a_uint8_t *header_buf, athrs_cmd_resp_t *cmd_resp); - - -#ifdef __cplusplus -} -#endif /* __cplusplus */ - -#endif /* _ISIS_REG_ACCESS_H_ */ - diff --git a/feeds/ipq807x/qca-ssdk/src/include/hsl/isis/isis_sec.h b/feeds/ipq807x/qca-ssdk/src/include/hsl/isis/isis_sec.h deleted file mode 100755 index c671d4138..000000000 --- a/feeds/ipq807x/qca-ssdk/src/include/hsl/isis/isis_sec.h +++ /dev/null @@ -1,53 +0,0 @@ -/* - * Copyright (c) 2012, The Linux Foundation. All rights reserved. - * Permission to use, copy, modify, and/or distribute this software for - * any purpose with or without fee is hereby granted, provided that the - * above copyright notice and this permission notice appear in all copies. - * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES - * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR - * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES - * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN - * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT - * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. - */ - - -#ifndef _ISIS_SEC_H_ -#define _ISIS_SEC_H_ - -#ifdef __cplusplus -extern "C" { -#endif /* __cplusplus */ - -#include "fal/fal_sec.h" - - sw_error_t isis_sec_init(a_uint32_t dev_id); - -#ifdef IN_SEC -#define ISIS_SEC_INIT(rv, dev_id) \ - { \ - rv = isis_sec_init(dev_id); \ - SW_RTN_ON_ERROR(rv); \ - } -#else -#define ISIS_SEC_INIT(rv, dev_id) -#endif - -#ifdef HSL_STANDALONG - - HSL_LOCAL sw_error_t - isis_sec_norm_item_set(a_uint32_t dev_id, fal_norm_item_t item, - void *value); - - HSL_LOCAL sw_error_t - isis_sec_norm_item_get(a_uint32_t dev_id, fal_norm_item_t item, - void *value); - -#endif - -#ifdef __cplusplus -} -#endif /* __cplusplus */ -#endif /* _ISIS_SEC_H_ */ - diff --git a/feeds/ipq807x/qca-ssdk/src/include/hsl/isis/isis_stp.h b/feeds/ipq807x/qca-ssdk/src/include/hsl/isis/isis_stp.h deleted file mode 100755 index 407017d10..000000000 --- a/feeds/ipq807x/qca-ssdk/src/include/hsl/isis/isis_stp.h +++ /dev/null @@ -1,55 +0,0 @@ -/* - * Copyright (c) 2012, The Linux Foundation. All rights reserved. - * Permission to use, copy, modify, and/or distribute this software for - * any purpose with or without fee is hereby granted, provided that the - * above copyright notice and this permission notice appear in all copies. - * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES - * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR - * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES - * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN - * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT - * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. - */ - - -#ifndef _ISIS_STP_H_ -#define _ISIS_STP_H_ - -#ifdef __cplusplus -extern "C" { -#endif /* __cplusplus */ - -#include "fal/fal_stp.h" - - sw_error_t isis_stp_init(a_uint32_t dev_id); - -#ifdef IN_STP -#define ISIS_STP_INIT(rv, dev_id) \ - { \ - rv = isis_stp_init(dev_id); \ - SW_RTN_ON_ERROR(rv); \ - } -#else -#define ISIS_STP_INIT(rv, dev_id) -#endif - -#ifdef HSL_STANDALONG - - - HSL_LOCAL sw_error_t - isis_stp_port_state_set(a_uint32_t dev_id, a_uint32_t st_id, - fal_port_t port_id, fal_stp_state_t state); - - - HSL_LOCAL sw_error_t - isis_stp_port_state_get(a_uint32_t dev_id, a_uint32_t st_id, - fal_port_t port_id, fal_stp_state_t * state); - -#endif - -#ifdef __cplusplus -} -#endif /* __cplusplus */ -#endif /* _ISIS_STP_H_ */ - diff --git a/feeds/ipq807x/qca-ssdk/src/include/hsl/isis/isis_trunk.h b/feeds/ipq807x/qca-ssdk/src/include/hsl/isis/isis_trunk.h deleted file mode 100755 index 66c602c7e..000000000 --- a/feeds/ipq807x/qca-ssdk/src/include/hsl/isis/isis_trunk.h +++ /dev/null @@ -1,69 +0,0 @@ -/* - * Copyright (c) 2012, The Linux Foundation. All rights reserved. - * Permission to use, copy, modify, and/or distribute this software for - * any purpose with or without fee is hereby granted, provided that the - * above copyright notice and this permission notice appear in all copies. - * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES - * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR - * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES - * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN - * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT - * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. - */ - - -#ifndef _ISIS_TRUNK_H_ -#define _ISIS_TRUNK_H_ - -#ifdef __cplusplus -extern "C" { -#endif /* __cplusplus */ - -#include "fal/fal_trunk.h" - - sw_error_t isis_trunk_init(a_uint32_t dev_id); - -#ifdef IN_TRUNK -#define ISIS_TRUNK_INIT(rv, dev_id) \ - { \ - rv = isis_trunk_init(dev_id); \ - SW_RTN_ON_ERROR(rv); \ - } -#else -#define ISIS_TRUNK_INIT(rv, dev_id) -#endif - -#ifdef HSL_STANDALONG - - HSL_LOCAL sw_error_t - isis_trunk_group_set(a_uint32_t dev_id, a_uint32_t trunk_id, - a_bool_t enable, fal_pbmp_t member); - - HSL_LOCAL sw_error_t - isis_trunk_group_get(a_uint32_t dev_id, a_uint32_t trunk_id, - a_bool_t * enable, fal_pbmp_t * member); - - HSL_LOCAL sw_error_t - isis_trunk_hash_mode_set(a_uint32_t dev_id, a_uint32_t hash_mode); - - HSL_LOCAL sw_error_t - isis_trunk_hash_mode_get(a_uint32_t dev_id, a_uint32_t * hash_mode); - - HSL_LOCAL sw_error_t - isis_trunk_manipulate_sa_set(a_uint32_t dev_id, fal_mac_addr_t * addr); - - HSL_LOCAL sw_error_t - isis_trunk_manipulate_sa_get(a_uint32_t dev_id, fal_mac_addr_t * addr); - - HSL_LOCAL sw_error_t - isis_trunk_manipulate_dp(a_uint32_t dev_id, a_uint8_t * header, - a_uint32_t len, fal_pbmp_t dp_member); - -#endif - -#ifdef __cplusplus -} -#endif /* __cplusplus */ -#endif /* _ISIS_TRUNK_H_ */ - diff --git a/feeds/ipq807x/qca-ssdk/src/include/hsl/isis/isis_vlan.h b/feeds/ipq807x/qca-ssdk/src/include/hsl/isis/isis_vlan.h deleted file mode 100755 index 245d59539..000000000 --- a/feeds/ipq807x/qca-ssdk/src/include/hsl/isis/isis_vlan.h +++ /dev/null @@ -1,99 +0,0 @@ -/* - * Copyright (c) 2012, The Linux Foundation. All rights reserved. - * Permission to use, copy, modify, and/or distribute this software for - * any purpose with or without fee is hereby granted, provided that the - * above copyright notice and this permission notice appear in all copies. - * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES - * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR - * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES - * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN - * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT - * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. - */ - - -#ifndef _ISIS_VLAN_H_ -#define _ISIS_VLAN_H_ - -#ifdef __cplusplus -extern "C" { -#endif /* __cplusplus */ - -#include "fal/fal_vlan.h" - - sw_error_t - isis_vlan_init(a_uint32_t dev_id); - -#ifdef IN_VLAN -#define ISIS_VLAN_INIT(rv, dev_id) \ - { \ - rv = isis_vlan_init(dev_id); \ - SW_RTN_ON_ERROR(rv); \ - } -#else -#define ISIS_VLAN_INIT(rv, dev_id) -#endif - -#ifdef HSL_STANDALONG - - - HSL_LOCAL sw_error_t - isis_vlan_entry_append(a_uint32_t dev_id, const fal_vlan_t * vlan_entry); - - - HSL_LOCAL sw_error_t - isis_vlan_create(a_uint32_t dev_id, a_uint32_t vlan_id); - - - HSL_LOCAL sw_error_t - isis_vlan_next(a_uint32_t dev_id, a_uint32_t vlan_id, fal_vlan_t * p_vlan); - - - HSL_LOCAL sw_error_t - isis_vlan_find(a_uint32_t dev_id, a_uint32_t vlan_id, fal_vlan_t * p_vlan); - - - HSL_LOCAL sw_error_t - isis_vlan_delete(a_uint32_t dev_id, a_uint32_t vlan_id); - - - HSL_LOCAL sw_error_t - isis_vlan_flush(a_uint32_t dev_id); - - - HSL_LOCAL sw_error_t - isis_vlan_fid_set(a_uint32_t dev_id, a_uint32_t vlan_id, a_uint32_t fid); - - - HSL_LOCAL sw_error_t - isis_vlan_fid_get(a_uint32_t dev_id, a_uint32_t vlan_id, a_uint32_t * fid); - - - HSL_LOCAL sw_error_t - isis_vlan_member_add(a_uint32_t dev_id, a_uint32_t vlan_id, - fal_port_t port_id, fal_pt_1q_egmode_t port_info); - - - HSL_LOCAL sw_error_t - isis_vlan_member_del(a_uint32_t dev_id, a_uint32_t vlan_id, fal_port_t port_id); - - - HSL_LOCAL sw_error_t - isis_vlan_learning_state_set(a_uint32_t dev_id, a_uint32_t vlan_id, - a_bool_t enable); - - - HSL_LOCAL sw_error_t - isis_vlan_learning_state_get(a_uint32_t dev_id, a_uint32_t vlan_id, - a_bool_t * enable); - - -#endif - -#ifdef __cplusplus -} -#endif /* __cplusplus */ - -#endif /* _ISIS_VLAN_H_ */ - diff --git a/feeds/ipq807x/qca-ssdk/src/include/hsl/isisc/isisc_acl.h b/feeds/ipq807x/qca-ssdk/src/include/hsl/isisc/isisc_acl.h deleted file mode 100755 index 704b04749..000000000 --- a/feeds/ipq807x/qca-ssdk/src/include/hsl/isisc/isisc_acl.h +++ /dev/null @@ -1,143 +0,0 @@ -/* - * Copyright (c) 2012, The Linux Foundation. All rights reserved. - * Permission to use, copy, modify, and/or distribute this software for - * any purpose with or without fee is hereby granted, provided that the - * above copyright notice and this permission notice appear in all copies. - * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES - * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR - * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES - * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN - * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT - * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. - */ - - -/** - * @defgroup isisc_acl ISISC_ACL - * @{ - */ -#ifndef _ISISC_ACL_H_ -#define _ISISC_ACL_H_ - -#ifdef __cplusplus -extern "C" { -#endif /* __cplusplus */ - -#include "fal/fal_acl.h" - - sw_error_t isisc_acl_init(a_uint32_t dev_id); - - sw_error_t isisc_acl_reset(a_uint32_t dev_id); - - sw_error_t isisc_acl_cleanup(a_uint32_t dev_id); - - -#ifdef IN_ACL -#define ISISC_ACL_INIT(rv, dev_id) \ - { \ - rv = isisc_acl_init(dev_id); \ - SW_RTN_ON_ERROR(rv); \ - } - -#define ISISC_ACL_RESET(rv, dev_id) \ - { \ - rv = isisc_acl_reset(dev_id); \ - SW_RTN_ON_ERROR(rv); \ - } -#define ISISC_ACL_CLEANUP(rv, dev_id) \ - { \ - rv = isisc_acl_cleanup(dev_id); \ - SW_RTN_ON_ERROR(rv); \ - } -#else -#define ISISC_ACL_INIT(rv, dev_id) -#define ISISC_ACL_RESET(rv, dev_id) -#define ISISC_ACL_CLEANUP(rv, dev_id) -#endif - - sw_error_t - isisc_acl_list_creat(a_uint32_t dev_id, a_uint32_t list_id, - a_uint32_t list_pri); - - sw_error_t - isisc_acl_rule_add(a_uint32_t dev_id, a_uint32_t list_id, - a_uint32_t rule_id, a_uint32_t rule_nr, - fal_acl_rule_t * rule); - - sw_error_t - isisc_acl_rule_delete(a_uint32_t dev_id, a_uint32_t list_id, - a_uint32_t rule_id, a_uint32_t rule_nr); - - sw_error_t - isisc_acl_rule_query(a_uint32_t dev_id, a_uint32_t list_id, - a_uint32_t rule_id, fal_acl_rule_t * rule); - - a_uint32_t - isisc_acl_rule_get_offset(a_uint32_t dev_id, a_uint32_t list_id, a_uint32_t rule_id); - - sw_error_t - isisc_acl_rule_sync_multi_portmap(a_uint32_t dev_id, a_uint32_t pos, a_uint32_t *act); - - sw_error_t - isisc_acl_list_bind(a_uint32_t dev_id, a_uint32_t list_id, - fal_acl_direc_t direc, fal_acl_bind_obj_t obj_t, - a_uint32_t obj_idx); - - sw_error_t - isisc_acl_list_unbind(a_uint32_t dev_id, a_uint32_t list_id, - fal_acl_direc_t direc, fal_acl_bind_obj_t obj_t, - a_uint32_t obj_idx); - - sw_error_t - isisc_acl_status_set(a_uint32_t dev_id, a_bool_t enable); - -#ifdef HSL_STANDALONG - - - HSL_LOCAL sw_error_t - isisc_acl_list_destroy(a_uint32_t dev_id, a_uint32_t list_id); - - HSL_LOCAL sw_error_t - isisc_acl_status_get(a_uint32_t dev_id, a_bool_t * enable); - - HSL_LOCAL sw_error_t - isisc_acl_list_dump(a_uint32_t dev_id); - - HSL_LOCAL sw_error_t - isisc_acl_rule_dump(a_uint32_t dev_id); - - HSL_LOCAL sw_error_t - isisc_acl_port_udf_profile_set(a_uint32_t dev_id, fal_port_t port_id, - fal_acl_udf_type_t udf_type, - a_uint32_t offset, a_uint32_t length); - - HSL_LOCAL sw_error_t - isisc_acl_port_udf_profile_get(a_uint32_t dev_id, fal_port_t port_id, - fal_acl_udf_type_t udf_type, - a_uint32_t * offset, a_uint32_t * length); - - HSL_LOCAL sw_error_t - isisc_acl_rule_active(a_uint32_t dev_id, a_uint32_t list_id, - a_uint32_t rule_id, a_uint32_t rule_nr); - - HSL_LOCAL sw_error_t - isisc_acl_rule_deactive(a_uint32_t dev_id, a_uint32_t list_id, - a_uint32_t rule_id, a_uint32_t rule_nr); - HSL_LOCAL sw_error_t - isisc_acl_rule_src_filter_sts_set(a_uint32_t dev_id, - a_uint32_t rule_id, a_bool_t enable); - - HSL_LOCAL sw_error_t - isisc_acl_rule_src_filter_sts_get(a_uint32_t dev_id, - a_uint32_t rule_id, a_bool_t* enable); - -#endif - -#ifdef __cplusplus -} -#endif /* __cplusplus */ -#endif /* _ISISC_ACL_H_ */ -/** - * @} - */ diff --git a/feeds/ipq807x/qca-ssdk/src/include/hsl/isisc/isisc_api.h b/feeds/ipq807x/qca-ssdk/src/include/hsl/isisc/isisc_api.h deleted file mode 100755 index 4e9d75348..000000000 --- a/feeds/ipq807x/qca-ssdk/src/include/hsl/isisc/isisc_api.h +++ /dev/null @@ -1,1093 +0,0 @@ -/* - * Copyright (c) 2012, The Linux Foundation. All rights reserved. - * Permission to use, copy, modify, and/or distribute this software for - * any purpose with or without fee is hereby granted, provided that the - * above copyright notice and this permission notice appear in all copies. - * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES - * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR - * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES - * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN - * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT - * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. - */ - - - -#ifndef _ISISC_API_H_ -#define _ISISC_API_H_ - -#ifdef __cplusplus -extern "C" { -#endif /* __cplusplus */ - -#ifdef IN_PORTCONTROL -#define PORTCONTROL_API \ - SW_API_DEF(SW_API_PT_DUPLEX_GET, isisc_port_duplex_get), \ - SW_API_DEF(SW_API_PT_DUPLEX_SET, isisc_port_duplex_set), \ - SW_API_DEF(SW_API_PT_SPEED_GET, isisc_port_speed_get), \ - SW_API_DEF(SW_API_PT_SPEED_SET, isisc_port_speed_set), \ - SW_API_DEF(SW_API_PT_AN_GET, isisc_port_autoneg_status_get), \ - SW_API_DEF(SW_API_PT_AN_ENABLE, isisc_port_autoneg_enable), \ - SW_API_DEF(SW_API_PT_AN_RESTART, isisc_port_autoneg_restart), \ - SW_API_DEF(SW_API_PT_AN_ADV_GET, isisc_port_autoneg_adv_get), \ - SW_API_DEF(SW_API_PT_AN_ADV_SET, isisc_port_autoneg_adv_set), \ - SW_API_DEF(SW_API_PT_FLOWCTRL_SET, isisc_port_flowctrl_set), \ - SW_API_DEF(SW_API_PT_FLOWCTRL_GET, isisc_port_flowctrl_get), \ - SW_API_DEF(SW_API_PT_FLOWCTRL_MODE_SET, isisc_port_flowctrl_forcemode_set), \ - SW_API_DEF(SW_API_PT_FLOWCTRL_MODE_GET, isisc_port_flowctrl_forcemode_get), \ - SW_API_DEF(SW_API_PT_POWERSAVE_SET, isisc_port_powersave_set), \ - SW_API_DEF(SW_API_PT_POWERSAVE_GET, isisc_port_powersave_get), \ - SW_API_DEF(SW_API_PT_HIBERNATE_SET, isisc_port_hibernate_set), \ - SW_API_DEF(SW_API_PT_HIBERNATE_GET, isisc_port_hibernate_get), \ - SW_API_DEF(SW_API_PT_CDT, isisc_port_cdt), \ - SW_API_DEF(SW_API_PT_TXHDR_SET, isisc_port_txhdr_mode_set), \ - SW_API_DEF(SW_API_PT_TXHDR_GET, isisc_port_txhdr_mode_get), \ - SW_API_DEF(SW_API_PT_RXHDR_SET, isisc_port_rxhdr_mode_set), \ - SW_API_DEF(SW_API_PT_RXHDR_GET, isisc_port_rxhdr_mode_get), \ - SW_API_DEF(SW_API_HEADER_TYPE_SET, isisc_header_type_set), \ - SW_API_DEF(SW_API_HEADER_TYPE_GET, isisc_header_type_get), \ - SW_API_DEF(SW_API_TXMAC_STATUS_SET, isisc_port_txmac_status_set), \ - SW_API_DEF(SW_API_TXMAC_STATUS_GET, isisc_port_txmac_status_get), \ - SW_API_DEF(SW_API_RXMAC_STATUS_SET, isisc_port_rxmac_status_set), \ - SW_API_DEF(SW_API_RXMAC_STATUS_GET, isisc_port_rxmac_status_get), \ - SW_API_DEF(SW_API_TXFC_STATUS_SET, isisc_port_txfc_status_set), \ - SW_API_DEF(SW_API_TXFC_STATUS_GET, isisc_port_txfc_status_get), \ - SW_API_DEF(SW_API_RXFC_STATUS_SET, isisc_port_rxfc_status_set), \ - SW_API_DEF(SW_API_RXFC_STATUS_GET, isisc_port_rxfc_status_get), \ - SW_API_DEF(SW_API_BP_STATUS_SET, isisc_port_bp_status_set), \ - SW_API_DEF(SW_API_BP_STATUS_GET, isisc_port_bp_status_get), \ - SW_API_DEF(SW_API_PT_LINK_MODE_SET, isisc_port_link_forcemode_set), \ - SW_API_DEF(SW_API_PT_LINK_MODE_GET, isisc_port_link_forcemode_get), \ - SW_API_DEF(SW_API_PT_LINK_STATUS_GET, isisc_port_link_status_get), \ - SW_API_DEF(SW_API_PT_MAC_LOOPBACK_SET, isisc_port_mac_loopback_set), \ - SW_API_DEF(SW_API_PT_MAC_LOOPBACK_GET, isisc_port_mac_loopback_get), \ - SW_API_DEF(SW_API_PT_8023AZ_SET, isisc_port_8023az_set), \ - SW_API_DEF(SW_API_PT_8023AZ_GET, isisc_port_8023az_get), - -#define PORTCONTROL_API_PARAM \ - SW_API_DESC(SW_API_PT_DUPLEX_GET) \ - SW_API_DESC(SW_API_PT_DUPLEX_SET) \ - SW_API_DESC(SW_API_PT_SPEED_GET) \ - SW_API_DESC(SW_API_PT_SPEED_SET) \ - SW_API_DESC(SW_API_PT_AN_GET) \ - SW_API_DESC(SW_API_PT_AN_ENABLE) \ - SW_API_DESC(SW_API_PT_AN_RESTART) \ - SW_API_DESC(SW_API_PT_AN_ADV_GET) \ - SW_API_DESC(SW_API_PT_AN_ADV_SET) \ - SW_API_DESC(SW_API_PT_FLOWCTRL_SET) \ - SW_API_DESC(SW_API_PT_FLOWCTRL_GET) \ - SW_API_DESC(SW_API_PT_FLOWCTRL_MODE_SET) \ - SW_API_DESC(SW_API_PT_FLOWCTRL_MODE_GET) \ - SW_API_DESC(SW_API_PT_POWERSAVE_SET) \ - SW_API_DESC(SW_API_PT_POWERSAVE_GET) \ - SW_API_DESC(SW_API_PT_HIBERNATE_SET) \ - SW_API_DESC(SW_API_PT_HIBERNATE_GET) \ - SW_API_DESC(SW_API_PT_CDT) \ - SW_API_DESC(SW_API_PT_TXHDR_SET) \ - SW_API_DESC(SW_API_PT_TXHDR_GET) \ - SW_API_DESC(SW_API_PT_RXHDR_SET) \ - SW_API_DESC(SW_API_PT_RXHDR_GET) \ - SW_API_DESC(SW_API_HEADER_TYPE_SET) \ - SW_API_DESC(SW_API_HEADER_TYPE_GET) \ - SW_API_DESC(SW_API_TXMAC_STATUS_SET) \ - SW_API_DESC(SW_API_TXMAC_STATUS_GET) \ - SW_API_DESC(SW_API_RXMAC_STATUS_SET) \ - SW_API_DESC(SW_API_RXMAC_STATUS_GET) \ - SW_API_DESC(SW_API_TXFC_STATUS_SET) \ - SW_API_DESC(SW_API_TXFC_STATUS_GET) \ - SW_API_DESC(SW_API_RXFC_STATUS_SET) \ - SW_API_DESC(SW_API_RXFC_STATUS_GET) \ - SW_API_DESC(SW_API_BP_STATUS_SET) \ - SW_API_DESC(SW_API_BP_STATUS_GET) \ - SW_API_DESC(SW_API_PT_LINK_MODE_SET) \ - SW_API_DESC(SW_API_PT_LINK_MODE_GET) \ - SW_API_DESC(SW_API_PT_LINK_STATUS_GET) \ - SW_API_DESC(SW_API_PT_MAC_LOOPBACK_SET) \ - SW_API_DESC(SW_API_PT_MAC_LOOPBACK_GET) \ - SW_API_DESC(SW_API_PT_8023AZ_SET) \ - SW_API_DESC(SW_API_PT_8023AZ_GET) -#else -#define PORTCONTROL_API -#define PORTCONTROL_API_PARAM -#endif - -#ifdef IN_VLAN -#define VLAN_API \ - SW_API_DEF(SW_API_VLAN_ADD, isisc_vlan_create), \ - SW_API_DEF(SW_API_VLAN_DEL, isisc_vlan_delete), \ - SW_API_DEF(SW_API_VLAN_FIND, isisc_vlan_find), \ - SW_API_DEF(SW_API_VLAN_NEXT, isisc_vlan_next), \ - SW_API_DEF(SW_API_VLAN_APPEND, isisc_vlan_entry_append), \ - SW_API_DEF(SW_API_VLAN_FLUSH, isisc_vlan_flush), \ - SW_API_DEF(SW_API_VLAN_FID_SET, isisc_vlan_fid_set), \ - SW_API_DEF(SW_API_VLAN_FID_GET, isisc_vlan_fid_get), \ - SW_API_DEF(SW_API_VLAN_MEMBER_ADD, isisc_vlan_member_add), \ - SW_API_DEF(SW_API_VLAN_MEMBER_DEL, isisc_vlan_member_del), \ - SW_API_DEF(SW_API_VLAN_LEARN_STATE_SET, isisc_vlan_learning_state_set), \ - SW_API_DEF(SW_API_VLAN_LEARN_STATE_GET, isisc_vlan_learning_state_get), - -#define VLAN_API_PARAM \ - SW_API_DESC(SW_API_VLAN_ADD) \ - SW_API_DESC(SW_API_VLAN_DEL) \ - SW_API_DESC(SW_API_VLAN_FIND) \ - SW_API_DESC(SW_API_VLAN_NEXT) \ - SW_API_DESC(SW_API_VLAN_APPEND) \ - SW_API_DESC(SW_API_VLAN_FLUSH) \ - SW_API_DESC(SW_API_VLAN_FID_SET) \ - SW_API_DESC(SW_API_VLAN_FID_GET) \ - SW_API_DESC(SW_API_VLAN_MEMBER_ADD) \ - SW_API_DESC(SW_API_VLAN_MEMBER_DEL) \ - SW_API_DESC(SW_API_VLAN_LEARN_STATE_SET) \ - SW_API_DESC(SW_API_VLAN_LEARN_STATE_GET) -#else -#define VLAN_API -#define VLAN_API_PARAM -#endif - -#ifdef IN_PORTVLAN -#define PORTVLAN_API \ - SW_API_DEF(SW_API_PT_ING_MODE_GET, isisc_port_1qmode_get), \ - SW_API_DEF(SW_API_PT_ING_MODE_SET, isisc_port_1qmode_set), \ - SW_API_DEF(SW_API_PT_EG_MODE_GET, isisc_port_egvlanmode_get), \ - SW_API_DEF(SW_API_PT_EG_MODE_SET, isisc_port_egvlanmode_set), \ - SW_API_DEF(SW_API_PT_VLAN_MEM_ADD, isisc_portvlan_member_add), \ - SW_API_DEF(SW_API_PT_VLAN_MEM_DEL, isisc_portvlan_member_del), \ - SW_API_DEF(SW_API_PT_VLAN_MEM_UPDATE, isisc_portvlan_member_update), \ - SW_API_DEF(SW_API_PT_VLAN_MEM_GET, isisc_portvlan_member_get), \ - SW_API_DEF(SW_API_PT_FORCE_DEF_VID_SET, isisc_port_force_default_vid_set), \ - SW_API_DEF(SW_API_PT_FORCE_DEF_VID_GET, isisc_port_force_default_vid_get), \ - SW_API_DEF(SW_API_PT_FORCE_PORTVLAN_SET, isisc_port_force_portvlan_set), \ - SW_API_DEF(SW_API_PT_FORCE_PORTVLAN_GET, isisc_port_force_portvlan_get), \ - SW_API_DEF(SW_API_NESTVLAN_TPID_SET, isisc_nestvlan_tpid_set), \ - SW_API_DEF(SW_API_NESTVLAN_TPID_GET, isisc_nestvlan_tpid_get), \ - SW_API_DEF(SW_API_PT_IN_VLAN_MODE_SET, isisc_port_invlan_mode_set), \ - SW_API_DEF(SW_API_PT_IN_VLAN_MODE_GET, isisc_port_invlan_mode_get), \ - SW_API_DEF(SW_API_PT_TLS_SET, isisc_port_tls_set), \ - SW_API_DEF(SW_API_PT_TLS_GET, isisc_port_tls_get), \ - SW_API_DEF(SW_API_PT_PRI_PROPAGATION_SET, isisc_port_pri_propagation_set), \ - SW_API_DEF(SW_API_PT_PRI_PROPAGATION_GET, isisc_port_pri_propagation_get), \ - SW_API_DEF(SW_API_PT_DEF_SVID_SET, isisc_port_default_svid_set), \ - SW_API_DEF(SW_API_PT_DEF_SVID_GET, isisc_port_default_svid_get), \ - SW_API_DEF(SW_API_PT_DEF_CVID_SET, isisc_port_default_cvid_set), \ - SW_API_DEF(SW_API_PT_DEF_CVID_GET, isisc_port_default_cvid_get), \ - SW_API_DEF(SW_API_PT_VLAN_PROPAGATION_SET, isisc_port_vlan_propagation_set), \ - SW_API_DEF(SW_API_PT_VLAN_PROPAGATION_GET, isisc_port_vlan_propagation_get), \ - SW_API_DEF(SW_API_PT_VLAN_TRANS_ADD, isisc_port_vlan_trans_add), \ - SW_API_DEF(SW_API_PT_VLAN_TRANS_DEL, isisc_port_vlan_trans_del), \ - SW_API_DEF(SW_API_PT_VLAN_TRANS_GET, isisc_port_vlan_trans_get), \ - SW_API_DEF(SW_API_QINQ_MODE_SET, isisc_qinq_mode_set), \ - SW_API_DEF(SW_API_QINQ_MODE_GET, isisc_qinq_mode_get), \ - SW_API_DEF(SW_API_PT_QINQ_ROLE_SET, isisc_port_qinq_role_set), \ - SW_API_DEF(SW_API_PT_QINQ_ROLE_GET, isisc_port_qinq_role_get), \ - SW_API_DEF(SW_API_PT_VLAN_TRANS_ITERATE, isisc_port_vlan_trans_iterate), \ - SW_API_DEF(SW_API_PT_MAC_VLAN_XLT_SET, isisc_port_mac_vlan_xlt_set), \ - SW_API_DEF(SW_API_PT_MAC_VLAN_XLT_GET, isisc_port_mac_vlan_xlt_get), \ - SW_API_DEF(SW_API_NETISOLATE_SET, isisc_netisolate_set), \ - SW_API_DEF(SW_API_NETISOLATE_GET, isisc_netisolate_get),\ - SW_API_DEF(SW_API_EG_FLTR_BYPASS_EN_SET, isisc_eg_trans_filter_bypass_en_set), \ - SW_API_DEF(SW_API_EG_FLTR_BYPASS_EN_GET, isisc_eg_trans_filter_bypass_en_get), - - -#define PORTVLAN_API_PARAM \ - SW_API_DESC(SW_API_PT_ING_MODE_GET) \ - SW_API_DESC(SW_API_PT_ING_MODE_SET) \ - SW_API_DESC(SW_API_PT_EG_MODE_GET) \ - SW_API_DESC(SW_API_PT_EG_MODE_SET) \ - SW_API_DESC(SW_API_PT_VLAN_MEM_ADD) \ - SW_API_DESC(SW_API_PT_VLAN_MEM_DEL) \ - SW_API_DESC(SW_API_PT_VLAN_MEM_UPDATE) \ - SW_API_DESC(SW_API_PT_VLAN_MEM_GET) \ - SW_API_DESC(SW_API_PT_FORCE_DEF_VID_SET) \ - SW_API_DESC(SW_API_PT_FORCE_DEF_VID_GET) \ - SW_API_DESC(SW_API_PT_FORCE_PORTVLAN_SET) \ - SW_API_DESC(SW_API_PT_FORCE_PORTVLAN_GET) \ - SW_API_DESC(SW_API_NESTVLAN_TPID_SET) \ - SW_API_DESC(SW_API_NESTVLAN_TPID_GET) \ - SW_API_DESC(SW_API_PT_IN_VLAN_MODE_SET) \ - SW_API_DESC(SW_API_PT_IN_VLAN_MODE_GET) \ - SW_API_DESC(SW_API_PT_TLS_SET) \ - SW_API_DESC(SW_API_PT_TLS_GET) \ - SW_API_DESC(SW_API_PT_PRI_PROPAGATION_SET) \ - SW_API_DESC(SW_API_PT_PRI_PROPAGATION_GET) \ - SW_API_DESC(SW_API_PT_DEF_SVID_SET) \ - SW_API_DESC(SW_API_PT_DEF_SVID_GET) \ - SW_API_DESC(SW_API_PT_DEF_CVID_SET) \ - SW_API_DESC(SW_API_PT_DEF_CVID_GET) \ - SW_API_DESC(SW_API_PT_VLAN_PROPAGATION_SET) \ - SW_API_DESC(SW_API_PT_VLAN_PROPAGATION_GET) \ - SW_API_DESC(SW_API_PT_VLAN_TRANS_ADD) \ - SW_API_DESC(SW_API_PT_VLAN_TRANS_DEL) \ - SW_API_DESC(SW_API_PT_VLAN_TRANS_GET) \ - SW_API_DESC(SW_API_QINQ_MODE_SET) \ - SW_API_DESC(SW_API_QINQ_MODE_GET) \ - SW_API_DESC(SW_API_PT_QINQ_ROLE_SET) \ - SW_API_DESC(SW_API_PT_QINQ_ROLE_GET) \ - SW_API_DESC(SW_API_PT_VLAN_TRANS_ITERATE) \ - SW_API_DESC(SW_API_PT_MAC_VLAN_XLT_SET) \ - SW_API_DESC(SW_API_PT_MAC_VLAN_XLT_GET) \ - SW_API_DESC(SW_API_NETISOLATE_SET) \ - SW_API_DESC(SW_API_NETISOLATE_GET) \ - SW_API_DESC(SW_API_EG_FLTR_BYPASS_EN_SET) \ - SW_API_DESC(SW_API_EG_FLTR_BYPASS_EN_GET) - -#else -#define PORTVLAN_API -#define PORTVLAN_API_PARAM -#endif - -#ifdef IN_FDB -#define FDB_API \ - SW_API_DEF(SW_API_FDB_ADD, isisc_fdb_add), \ - SW_API_DEF(SW_API_FDB_DELALL, isisc_fdb_del_all), \ - SW_API_DEF(SW_API_FDB_DELPORT,isisc_fdb_del_by_port), \ - SW_API_DEF(SW_API_FDB_DELMAC, isisc_fdb_del_by_mac), \ - SW_API_DEF(SW_API_FDB_FIND, isisc_fdb_find), \ - SW_API_DEF(SW_API_FDB_EXTEND_NEXT, isisc_fdb_extend_next), \ - SW_API_DEF(SW_API_FDB_EXTEND_FIRST, isisc_fdb_extend_first), \ - SW_API_DEF(SW_API_FDB_TRANSFER, isisc_fdb_transfer), \ - SW_API_DEF(SW_API_FDB_PT_LEARN_SET, isisc_fdb_port_learn_set), \ - SW_API_DEF(SW_API_FDB_PT_LEARN_GET, isisc_fdb_port_learn_get), \ - SW_API_DEF(SW_API_FDB_AGE_CTRL_SET, isisc_fdb_age_ctrl_set), \ - SW_API_DEF(SW_API_FDB_AGE_CTRL_GET, isisc_fdb_age_ctrl_get), \ - SW_API_DEF(SW_API_FDB_VLAN_IVL_SVL_SET, isisc_fdb_vlan_ivl_svl_set),\ - SW_API_DEF(SW_API_FDB_VLAN_IVL_SVL_GET, isisc_fdb_vlan_ivl_svl_get),\ - SW_API_DEF(SW_API_FDB_AGE_TIME_SET, isisc_fdb_age_time_set), \ - SW_API_DEF(SW_API_FDB_AGE_TIME_GET, isisc_fdb_age_time_get), \ - SW_API_DEF(SW_API_PT_FDB_LEARN_LIMIT_SET, isisc_port_fdb_learn_limit_set), \ - SW_API_DEF(SW_API_PT_FDB_LEARN_LIMIT_GET, isisc_port_fdb_learn_limit_get), \ - SW_API_DEF(SW_API_PT_FDB_LEARN_EXCEED_CMD_SET, isisc_port_fdb_learn_exceed_cmd_set), \ - SW_API_DEF(SW_API_PT_FDB_LEARN_EXCEED_CMD_GET, isisc_port_fdb_learn_exceed_cmd_get), \ - SW_API_DEF(SW_API_FDB_LEARN_LIMIT_SET, isisc_fdb_learn_limit_set), \ - SW_API_DEF(SW_API_FDB_LEARN_LIMIT_GET, isisc_fdb_learn_limit_get), \ - SW_API_DEF(SW_API_FDB_LEARN_EXCEED_CMD_SET, isisc_fdb_learn_exceed_cmd_set), \ - SW_API_DEF(SW_API_FDB_LEARN_EXCEED_CMD_GET, isisc_fdb_learn_exceed_cmd_get), \ - SW_API_DEF(SW_API_FDB_RESV_ADD, isisc_fdb_resv_add), \ - SW_API_DEF(SW_API_FDB_RESV_DEL, isisc_fdb_resv_del), \ - SW_API_DEF(SW_API_FDB_RESV_FIND, isisc_fdb_resv_find), \ - SW_API_DEF(SW_API_FDB_RESV_ITERATE, isisc_fdb_resv_iterate), \ - SW_API_DEF(SW_API_FDB_PT_LEARN_STATIC_SET, isisc_fdb_port_learn_static_set), \ - SW_API_DEF(SW_API_FDB_PT_LEARN_STATIC_GET, isisc_fdb_port_learn_static_get), \ - SW_API_DEF(SW_API_FDB_PORT_ADD, isisc_fdb_port_add), \ - SW_API_DEF(SW_API_FDB_PORT_DEL, isisc_fdb_port_del), - -#define FDB_API_PARAM \ - SW_API_DESC(SW_API_FDB_ADD) \ - SW_API_DESC(SW_API_FDB_DELALL) \ - SW_API_DESC(SW_API_FDB_DELPORT) \ - SW_API_DESC(SW_API_FDB_DELMAC) \ - SW_API_DESC(SW_API_FDB_FIND) \ - SW_API_DESC(SW_API_FDB_EXTEND_NEXT) \ - SW_API_DESC(SW_API_FDB_EXTEND_FIRST) \ - SW_API_DESC(SW_API_FDB_TRANSFER) \ - SW_API_DESC(SW_API_FDB_PT_LEARN_SET) \ - SW_API_DESC(SW_API_FDB_PT_LEARN_GET) \ - SW_API_DESC(SW_API_FDB_AGE_CTRL_SET) \ - SW_API_DESC(SW_API_FDB_AGE_CTRL_GET) \ - SW_API_DESC(SW_API_FDB_VLAN_IVL_SVL_SET) \ - SW_API_DESC(SW_API_FDB_VLAN_IVL_SVL_GET) \ - SW_API_DESC(SW_API_FDB_AGE_TIME_SET) \ - SW_API_DESC(SW_API_FDB_AGE_TIME_GET) \ - SW_API_DESC(SW_API_PT_FDB_LEARN_LIMIT_SET) \ - SW_API_DESC(SW_API_PT_FDB_LEARN_LIMIT_GET) \ - SW_API_DESC(SW_API_PT_FDB_LEARN_EXCEED_CMD_SET) \ - SW_API_DESC(SW_API_PT_FDB_LEARN_EXCEED_CMD_GET) \ - SW_API_DESC(SW_API_FDB_LEARN_LIMIT_SET) \ - SW_API_DESC(SW_API_FDB_LEARN_LIMIT_GET) \ - SW_API_DESC(SW_API_FDB_LEARN_EXCEED_CMD_SET) \ - SW_API_DESC(SW_API_FDB_LEARN_EXCEED_CMD_GET) \ - SW_API_DESC(SW_API_FDB_RESV_ADD) \ - SW_API_DESC(SW_API_FDB_RESV_DEL) \ - SW_API_DESC(SW_API_FDB_RESV_FIND) \ - SW_API_DESC(SW_API_FDB_RESV_ITERATE) \ - SW_API_DESC(SW_API_FDB_PT_LEARN_STATIC_SET) \ - SW_API_DESC(SW_API_FDB_PT_LEARN_STATIC_GET) \ - SW_API_DESC(SW_API_FDB_PORT_ADD) \ - SW_API_DESC(SW_API_FDB_PORT_DEL) - -#else -#define FDB_API -#define FDB_API_PARAM -#endif - - -#ifdef IN_ACL -#define ACL_API \ - SW_API_DEF(SW_API_ACL_LIST_CREAT, isisc_acl_list_creat), \ - SW_API_DEF(SW_API_ACL_LIST_DESTROY, isisc_acl_list_destroy), \ - SW_API_DEF(SW_API_ACL_RULE_ADD, isisc_acl_rule_add), \ - SW_API_DEF(SW_API_ACL_RULE_DELETE, isisc_acl_rule_delete), \ - SW_API_DEF(SW_API_ACL_RULE_QUERY, isisc_acl_rule_query), \ - SW_API_DEF(SW_API_ACL_LIST_BIND, isisc_acl_list_bind), \ - SW_API_DEF(SW_API_ACL_LIST_UNBIND, isisc_acl_list_unbind), \ - SW_API_DEF(SW_API_ACL_STATUS_SET, isisc_acl_status_set), \ - SW_API_DEF(SW_API_ACL_STATUS_GET, isisc_acl_status_get), \ - SW_API_DEF(SW_API_ACL_LIST_DUMP, isisc_acl_list_dump), \ - SW_API_DEF(SW_API_ACL_RULE_DUMP, isisc_acl_rule_dump), \ - SW_API_DEF(SW_API_ACL_PT_UDF_PROFILE_SET, isisc_acl_port_udf_profile_set), \ - SW_API_DEF(SW_API_ACL_PT_UDF_PROFILE_GET, isisc_acl_port_udf_profile_get), \ - SW_API_DEF(SW_API_ACL_RULE_ACTIVE, isisc_acl_rule_active), \ - SW_API_DEF(SW_API_ACL_RULE_DEACTIVE, isisc_acl_rule_deactive),\ - SW_API_DEF(SW_API_ACL_RULE_SRC_FILTER_STS_SET, isisc_acl_rule_src_filter_sts_set),\ - SW_API_DEF(SW_API_ACL_RULE_SRC_FILTER_STS_GET, isisc_acl_rule_src_filter_sts_get), \ - SW_API_DEF(SW_API_ACL_RULE_GET_OFFSET, isisc_acl_rule_get_offset), - -#define ACL_API_PARAM \ - SW_API_DESC(SW_API_ACL_LIST_CREAT) \ - SW_API_DESC(SW_API_ACL_LIST_DESTROY) \ - SW_API_DESC(SW_API_ACL_RULE_ADD) \ - SW_API_DESC(SW_API_ACL_RULE_DELETE) \ - SW_API_DESC(SW_API_ACL_RULE_QUERY) \ - SW_API_DESC(SW_API_ACL_LIST_BIND) \ - SW_API_DESC(SW_API_ACL_LIST_UNBIND) \ - SW_API_DESC(SW_API_ACL_STATUS_SET) \ - SW_API_DESC(SW_API_ACL_STATUS_GET) \ - SW_API_DESC(SW_API_ACL_LIST_DUMP) \ - SW_API_DESC(SW_API_ACL_RULE_DUMP) \ - SW_API_DESC(SW_API_ACL_PT_UDF_PROFILE_SET) \ - SW_API_DESC(SW_API_ACL_PT_UDF_PROFILE_GET) \ - SW_API_DESC(SW_API_ACL_RULE_ACTIVE) \ - SW_API_DESC(SW_API_ACL_RULE_DEACTIVE) \ - SW_API_DESC(SW_API_ACL_RULE_SRC_FILTER_STS_SET) \ - SW_API_DESC(SW_API_ACL_RULE_SRC_FILTER_STS_GET) -#else -#define ACL_API -#define ACL_API_PARAM -#endif - - -#ifdef IN_QOS -#define QOS_API \ - SW_API_DEF(SW_API_QOS_QU_TX_BUF_ST_SET, isisc_qos_queue_tx_buf_status_set), \ - SW_API_DEF(SW_API_QOS_QU_TX_BUF_ST_GET, isisc_qos_queue_tx_buf_status_get), \ - SW_API_DEF(SW_API_QOS_QU_TX_BUF_NR_SET, isisc_qos_queue_tx_buf_nr_set), \ - SW_API_DEF(SW_API_QOS_QU_TX_BUF_NR_GET, isisc_qos_queue_tx_buf_nr_get), \ - SW_API_DEF(SW_API_QOS_PT_TX_BUF_ST_SET, isisc_qos_port_tx_buf_status_set), \ - SW_API_DEF(SW_API_QOS_PT_TX_BUF_ST_GET, isisc_qos_port_tx_buf_status_get), \ - SW_API_DEF(SW_API_QOS_PT_RED_EN_SET, isisc_qos_port_red_en_set),\ - SW_API_DEF(SW_API_QOS_PT_RED_EN_GET, isisc_qos_port_red_en_get),\ - SW_API_DEF(SW_API_QOS_PT_TX_BUF_NR_SET, isisc_qos_port_tx_buf_nr_set), \ - SW_API_DEF(SW_API_QOS_PT_TX_BUF_NR_GET, isisc_qos_port_tx_buf_nr_get), \ - SW_API_DEF(SW_API_QOS_PT_RX_BUF_NR_SET, isisc_qos_port_rx_buf_nr_set), \ - SW_API_DEF(SW_API_QOS_PT_RX_BUF_NR_GET, isisc_qos_port_rx_buf_nr_get), \ - SW_API_DEF(SW_API_QOS_PT_MODE_SET, isisc_qos_port_mode_set), \ - SW_API_DEF(SW_API_QOS_PT_MODE_GET, isisc_qos_port_mode_get), \ - SW_API_DEF(SW_API_QOS_PT_MODE_PRI_SET, isisc_qos_port_mode_pri_set), \ - SW_API_DEF(SW_API_QOS_PT_MODE_PRI_GET, isisc_qos_port_mode_pri_get), \ - SW_API_DEF(SW_API_QOS_PORT_SCH_MODE_SET, isisc_qos_port_sch_mode_set), \ - SW_API_DEF(SW_API_QOS_PORT_SCH_MODE_GET, isisc_qos_port_sch_mode_get), \ - SW_API_DEF(SW_API_QOS_PT_DEF_SPRI_SET, isisc_qos_port_default_spri_set), \ - SW_API_DEF(SW_API_QOS_PT_DEF_SPRI_GET, isisc_qos_port_default_spri_get), \ - SW_API_DEF(SW_API_QOS_PT_DEF_CPRI_SET, isisc_qos_port_default_cpri_set), \ - SW_API_DEF(SW_API_QOS_PT_DEF_CPRI_GET, isisc_qos_port_default_cpri_get), \ - SW_API_DEF(SW_API_QOS_PT_FORCE_SPRI_ST_SET, isisc_qos_port_force_spri_status_set), \ - SW_API_DEF(SW_API_QOS_PT_FORCE_SPRI_ST_GET, isisc_qos_port_force_spri_status_get), \ - SW_API_DEF(SW_API_QOS_PT_FORCE_CPRI_ST_SET, isisc_qos_port_force_cpri_status_set), \ - SW_API_DEF(SW_API_QOS_PT_FORCE_CPRI_ST_GET, isisc_qos_port_force_cpri_status_get), \ - SW_API_DEF(SW_API_QOS_QUEUE_REMARK_SET, isisc_qos_queue_remark_table_set), \ - SW_API_DEF(SW_API_QOS_QUEUE_REMARK_GET, isisc_qos_queue_remark_table_get), - - -#define QOS_API_PARAM \ - SW_API_DESC(SW_API_QOS_QU_TX_BUF_ST_SET) \ - SW_API_DESC(SW_API_QOS_QU_TX_BUF_ST_GET) \ - SW_API_DESC(SW_API_QOS_QU_TX_BUF_NR_SET) \ - SW_API_DESC(SW_API_QOS_QU_TX_BUF_NR_GET) \ - SW_API_DESC(SW_API_QOS_PT_TX_BUF_ST_SET) \ - SW_API_DESC(SW_API_QOS_PT_TX_BUF_ST_GET) \ - SW_API_DESC(SW_API_QOS_PT_RED_EN_SET) \ - SW_API_DESC(SW_API_QOS_PT_RED_EN_GET) \ - SW_API_DESC(SW_API_QOS_PT_TX_BUF_NR_SET) \ - SW_API_DESC(SW_API_QOS_PT_TX_BUF_NR_GET) \ - SW_API_DESC(SW_API_QOS_PT_RX_BUF_NR_SET) \ - SW_API_DESC(SW_API_QOS_PT_RX_BUF_NR_GET) \ - SW_API_DESC(SW_API_QOS_PT_MODE_SET) \ - SW_API_DESC(SW_API_QOS_PT_MODE_GET) \ - SW_API_DESC(SW_API_QOS_PT_MODE_PRI_SET) \ - SW_API_DESC(SW_API_QOS_PT_MODE_PRI_GET) \ - SW_API_DESC(SW_API_QOS_PORT_DEF_UP_SET) \ - SW_API_DESC(SW_API_QOS_PORT_DEF_UP_GET) \ - SW_API_DESC(SW_API_QOS_PORT_SCH_MODE_SET) \ - SW_API_DESC(SW_API_QOS_PORT_SCH_MODE_GET) \ - SW_API_DESC(SW_API_QOS_PT_DEF_SPRI_SET) \ - SW_API_DESC(SW_API_QOS_PT_DEF_SPRI_GET) \ - SW_API_DESC(SW_API_QOS_PT_DEF_CPRI_SET) \ - SW_API_DESC(SW_API_QOS_PT_DEF_CPRI_GET) \ - SW_API_DESC(SW_API_QOS_PT_FORCE_SPRI_ST_SET) \ - SW_API_DESC(SW_API_QOS_PT_FORCE_SPRI_ST_GET) \ - SW_API_DESC(SW_API_QOS_PT_FORCE_CPRI_ST_SET) \ - SW_API_DESC(SW_API_QOS_PT_FORCE_CPRI_ST_GET) \ - SW_API_DESC(SW_API_QOS_QUEUE_REMARK_SET) \ - SW_API_DESC(SW_API_QOS_QUEUE_REMARK_GET) -#else -#define QOS_API -#define QOS_API_PARAM -#endif - - -#ifdef IN_IGMP -#define IGMP_API \ - SW_API_DEF(SW_API_PT_IGMPS_MODE_SET, isisc_port_igmps_status_set), \ - SW_API_DEF(SW_API_PT_IGMPS_MODE_GET, isisc_port_igmps_status_get), \ - SW_API_DEF(SW_API_IGMP_MLD_CMD_SET, isisc_igmp_mld_cmd_set), \ - SW_API_DEF(SW_API_IGMP_MLD_CMD_GET, isisc_igmp_mld_cmd_get), \ - SW_API_DEF(SW_API_IGMP_PT_JOIN_SET, isisc_port_igmp_mld_join_set), \ - SW_API_DEF(SW_API_IGMP_PT_JOIN_GET, isisc_port_igmp_mld_join_get), \ - SW_API_DEF(SW_API_IGMP_PT_LEAVE_SET, isisc_port_igmp_mld_leave_set), \ - SW_API_DEF(SW_API_IGMP_PT_LEAVE_GET, isisc_port_igmp_mld_leave_get), \ - SW_API_DEF(SW_API_IGMP_RP_SET, isisc_igmp_mld_rp_set), \ - SW_API_DEF(SW_API_IGMP_RP_GET, isisc_igmp_mld_rp_get), \ - SW_API_DEF(SW_API_IGMP_ENTRY_CREAT_SET, isisc_igmp_mld_entry_creat_set), \ - SW_API_DEF(SW_API_IGMP_ENTRY_CREAT_GET, isisc_igmp_mld_entry_creat_get), \ - SW_API_DEF(SW_API_IGMP_ENTRY_STATIC_SET, isisc_igmp_mld_entry_static_set), \ - SW_API_DEF(SW_API_IGMP_ENTRY_STATIC_GET, isisc_igmp_mld_entry_static_get), \ - SW_API_DEF(SW_API_IGMP_ENTRY_LEAKY_SET, isisc_igmp_mld_entry_leaky_set), \ - SW_API_DEF(SW_API_IGMP_ENTRY_LEAKY_GET, isisc_igmp_mld_entry_leaky_get), \ - SW_API_DEF(SW_API_IGMP_ENTRY_V3_SET, isisc_igmp_mld_entry_v3_set), \ - SW_API_DEF(SW_API_IGMP_ENTRY_V3_GET, isisc_igmp_mld_entry_v3_get), \ - SW_API_DEF(SW_API_IGMP_ENTRY_QUEUE_SET, isisc_igmp_mld_entry_queue_set), \ - SW_API_DEF(SW_API_IGMP_ENTRY_QUEUE_GET, isisc_igmp_mld_entry_queue_get), \ - SW_API_DEF(SW_API_PT_IGMP_LEARN_LIMIT_SET, isisc_port_igmp_mld_learn_limit_set), \ - SW_API_DEF(SW_API_PT_IGMP_LEARN_LIMIT_GET, isisc_port_igmp_mld_learn_limit_get), \ - SW_API_DEF(SW_API_PT_IGMP_LEARN_EXCEED_CMD_SET, isisc_port_igmp_mld_learn_exceed_cmd_set), \ - SW_API_DEF(SW_API_PT_IGMP_LEARN_EXCEED_CMD_GET, isisc_port_igmp_mld_learn_exceed_cmd_get), \ - SW_API_DEF(SW_API_IGMP_SG_ENTRY_SET, isisc_igmp_sg_entry_set), \ - SW_API_DEF(SW_API_IGMP_SG_ENTRY_CLEAR, isisc_igmp_sg_entry_clear), \ - SW_API_DEF(SW_API_IGMP_SG_ENTRY_SHOW, isisc_igmp_sg_entry_show), - -#define IGMP_API_PARAM \ - SW_API_DESC(SW_API_PT_IGMPS_MODE_SET) \ - SW_API_DESC(SW_API_PT_IGMPS_MODE_GET) \ - SW_API_DESC(SW_API_IGMP_MLD_CMD_SET) \ - SW_API_DESC(SW_API_IGMP_MLD_CMD_GET) \ - SW_API_DESC(SW_API_IGMP_PT_JOIN_SET) \ - SW_API_DESC(SW_API_IGMP_PT_JOIN_GET) \ - SW_API_DESC(SW_API_IGMP_PT_LEAVE_SET) \ - SW_API_DESC(SW_API_IGMP_PT_LEAVE_GET) \ - SW_API_DESC(SW_API_IGMP_RP_SET) \ - SW_API_DESC(SW_API_IGMP_RP_GET) \ - SW_API_DESC(SW_API_IGMP_ENTRY_CREAT_SET) \ - SW_API_DESC(SW_API_IGMP_ENTRY_CREAT_GET) \ - SW_API_DESC(SW_API_IGMP_ENTRY_STATIC_SET) \ - SW_API_DESC(SW_API_IGMP_ENTRY_STATIC_GET) \ - SW_API_DESC(SW_API_IGMP_ENTRY_LEAKY_SET) \ - SW_API_DESC(SW_API_IGMP_ENTRY_LEAKY_GET) \ - SW_API_DESC(SW_API_IGMP_ENTRY_V3_SET) \ - SW_API_DESC(SW_API_IGMP_ENTRY_V3_GET) \ - SW_API_DESC(SW_API_IGMP_ENTRY_QUEUE_SET) \ - SW_API_DESC(SW_API_IGMP_ENTRY_QUEUE_GET) \ - SW_API_DESC(SW_API_PT_IGMP_LEARN_LIMIT_SET) \ - SW_API_DESC(SW_API_PT_IGMP_LEARN_LIMIT_GET) \ - SW_API_DESC(SW_API_PT_IGMP_LEARN_EXCEED_CMD_SET) \ - SW_API_DESC(SW_API_PT_IGMP_LEARN_EXCEED_CMD_GET) \ - SW_API_DESC(SW_API_IGMP_SG_ENTRY_SET) \ - SW_API_DESC(SW_API_IGMP_SG_ENTRY_CLEAR) \ - SW_API_DESC(SW_API_IGMP_SG_ENTRY_SHOW) -#else -#define IGMP_API -#define IGMP_API_PARAM -#endif - - -#ifdef IN_LEAKY -#define LEAKY_API \ - SW_API_DEF(SW_API_UC_LEAKY_MODE_SET, isisc_uc_leaky_mode_set), \ - SW_API_DEF(SW_API_UC_LEAKY_MODE_GET, isisc_uc_leaky_mode_get), \ - SW_API_DEF(SW_API_MC_LEAKY_MODE_SET, isisc_mc_leaky_mode_set), \ - SW_API_DEF(SW_API_MC_LEAKY_MODE_GET, isisc_mc_leaky_mode_get), \ - SW_API_DEF(SW_API_ARP_LEAKY_MODE_SET, isisc_port_arp_leaky_set), \ - SW_API_DEF(SW_API_ARP_LEAKY_MODE_GET, isisc_port_arp_leaky_get), \ - SW_API_DEF(SW_API_PT_UC_LEAKY_MODE_SET, isisc_port_uc_leaky_set), \ - SW_API_DEF(SW_API_PT_UC_LEAKY_MODE_GET, isisc_port_uc_leaky_get), \ - SW_API_DEF(SW_API_PT_MC_LEAKY_MODE_SET, isisc_port_mc_leaky_set), \ - SW_API_DEF(SW_API_PT_MC_LEAKY_MODE_GET, isisc_port_mc_leaky_get), - -#define LEAKY_API_PARAM \ - SW_API_DESC(SW_API_UC_LEAKY_MODE_SET) \ - SW_API_DESC(SW_API_UC_LEAKY_MODE_GET) \ - SW_API_DESC(SW_API_MC_LEAKY_MODE_SET) \ - SW_API_DESC(SW_API_MC_LEAKY_MODE_GET) \ - SW_API_DESC(SW_API_ARP_LEAKY_MODE_SET) \ - SW_API_DESC(SW_API_ARP_LEAKY_MODE_GET) \ - SW_API_DESC(SW_API_PT_UC_LEAKY_MODE_SET) \ - SW_API_DESC(SW_API_PT_UC_LEAKY_MODE_GET) \ - SW_API_DESC(SW_API_PT_MC_LEAKY_MODE_SET) \ - SW_API_DESC(SW_API_PT_MC_LEAKY_MODE_GET) -#else -#define LEAKY_API -#define LEAKY_API_PARAM -#endif - - -#ifdef IN_MIRROR -#define MIRROR_API \ - SW_API_DEF(SW_API_MIRROR_ANALY_PT_SET, isisc_mirr_analysis_port_set), \ - SW_API_DEF(SW_API_MIRROR_ANALY_PT_GET, isisc_mirr_analysis_port_get), \ - SW_API_DEF(SW_API_MIRROR_IN_PT_SET, isisc_mirr_port_in_set), \ - SW_API_DEF(SW_API_MIRROR_IN_PT_GET, isisc_mirr_port_in_get), \ - SW_API_DEF(SW_API_MIRROR_EG_PT_SET, isisc_mirr_port_eg_set), \ - SW_API_DEF(SW_API_MIRROR_EG_PT_GET, isisc_mirr_port_eg_get), - -#define MIRROR_API_PARAM \ - SW_API_DESC(SW_API_MIRROR_ANALY_PT_SET) \ - SW_API_DESC(SW_API_MIRROR_ANALY_PT_GET) \ - SW_API_DESC(SW_API_MIRROR_IN_PT_SET) \ - SW_API_DESC(SW_API_MIRROR_IN_PT_GET) \ - SW_API_DESC(SW_API_MIRROR_EG_PT_SET) \ - SW_API_DESC(SW_API_MIRROR_EG_PT_GET) -#else -#define MIRROR_API -#define MIRROR_API_PARAM -#endif - - -#ifdef IN_RATE -#define RATE_API \ - SW_API_DEF(SW_API_RATE_PORT_POLICER_SET, isisc_rate_port_policer_set), \ - SW_API_DEF(SW_API_RATE_PORT_POLICER_GET, isisc_rate_port_policer_get), \ - SW_API_DEF(SW_API_RATE_PORT_SHAPER_SET, isisc_rate_port_shaper_set), \ - SW_API_DEF(SW_API_RATE_PORT_SHAPER_GET, isisc_rate_port_shaper_get), \ - SW_API_DEF(SW_API_RATE_QUEUE_SHAPER_SET, isisc_rate_queue_shaper_set), \ - SW_API_DEF(SW_API_RATE_QUEUE_SHAPER_GET, isisc_rate_queue_shaper_get), \ - SW_API_DEF(SW_API_RATE_ACL_POLICER_SET, isisc_rate_acl_policer_set), \ - SW_API_DEF(SW_API_RATE_ACL_POLICER_GET, isisc_rate_acl_policer_get), \ - SW_API_DEF(SW_API_RATE_PT_ADDRATEBYTE_SET, isisc_rate_port_add_rate_byte_set), \ - SW_API_DEF(SW_API_RATE_PT_ADDRATEBYTE_GET, isisc_rate_port_add_rate_byte_get), \ - SW_API_DEF(SW_API_RATE_PT_GOL_FLOW_EN_SET, isisc_rate_port_gol_flow_en_set), \ - SW_API_DEF(SW_API_RATE_PT_GOL_FLOW_EN_GET, isisc_rate_port_gol_flow_en_get), - -#define RATE_API_PARAM \ - SW_API_DESC(SW_API_RATE_PORT_POLICER_SET) \ - SW_API_DESC(SW_API_RATE_PORT_POLICER_GET) \ - SW_API_DESC(SW_API_RATE_PORT_SHAPER_SET) \ - SW_API_DESC(SW_API_RATE_PORT_SHAPER_GET) \ - SW_API_DESC(SW_API_RATE_QUEUE_SHAPER_SET) \ - SW_API_DESC(SW_API_RATE_QUEUE_SHAPER_GET) \ - SW_API_DESC(SW_API_RATE_ACL_POLICER_SET) \ - SW_API_DESC(SW_API_RATE_ACL_POLICER_GET) \ - SW_API_DESC(SW_API_RATE_PT_ADDRATEBYTE_SET) \ - SW_API_DESC(SW_API_RATE_PT_ADDRATEBYTE_GET) \ - SW_API_DESC(SW_API_RATE_PT_GOL_FLOW_EN_SET) \ - SW_API_DESC(SW_API_RATE_PT_GOL_FLOW_EN_GET) -#else -#define RATE_API -#define RATE_API_PARAM -#endif - - -#ifdef IN_STP -#define STP_API \ - SW_API_DEF(SW_API_STP_PT_STATE_SET, isisc_stp_port_state_set), \ - SW_API_DEF(SW_API_STP_PT_STATE_GET, isisc_stp_port_state_get), - -#define STP_API_PARAM \ - SW_API_DESC(SW_API_STP_PT_STATE_SET) \ - SW_API_DESC(SW_API_STP_PT_STATE_GET) -#else -#define STP_API -#define STP_API_PARAM -#endif - - -#ifdef IN_MIB -#define MIB_API \ - SW_API_DEF(SW_API_PT_MIB_GET, isisc_get_mib_info), \ - SW_API_DEF(SW_API_MIB_STATUS_SET, isisc_mib_status_set), \ - SW_API_DEF(SW_API_MIB_STATUS_GET, isisc_mib_status_get), \ - SW_API_DEF(SW_API_PT_MIB_FLUSH_COUNTERS, isisc_mib_port_flush_counters), \ - SW_API_DEF(SW_API_MIB_CPU_KEEP_SET, isisc_mib_cpukeep_set), \ - SW_API_DEF(SW_API_MIB_CPU_KEEP_GET, isisc_mib_cpukeep_get), - - -#define MIB_API_PARAM \ - SW_API_DESC(SW_API_PT_MIB_GET) \ - SW_API_DESC(SW_API_MIB_STATUS_SET) \ - SW_API_DESC(SW_API_MIB_STATUS_GET)\ - SW_API_DESC(SW_API_PT_MIB_FLUSH_COUNTERS) \ - SW_API_DESC(SW_API_MIB_CPU_KEEP_SET) \ - SW_API_DESC(SW_API_MIB_CPU_KEEP_GET) -#else -#define MIB_API -#define MIB_API_PARAM -#endif - - -#ifdef IN_MISC -#define MISC_API \ - SW_API_DEF(SW_API_FRAME_MAX_SIZE_SET, isisc_frame_max_size_set), \ - SW_API_DEF(SW_API_FRAME_MAX_SIZE_GET, isisc_frame_max_size_get), \ - SW_API_DEF(SW_API_PT_UNK_UC_FILTER_SET, isisc_port_unk_uc_filter_set), \ - SW_API_DEF(SW_API_PT_UNK_UC_FILTER_GET, isisc_port_unk_uc_filter_get), \ - SW_API_DEF(SW_API_PT_UNK_MC_FILTER_SET, isisc_port_unk_mc_filter_set), \ - SW_API_DEF(SW_API_PT_UNK_MC_FILTER_GET, isisc_port_unk_mc_filter_get), \ - SW_API_DEF(SW_API_PT_BC_FILTER_SET, isisc_port_bc_filter_set), \ - SW_API_DEF(SW_API_PT_BC_FILTER_GET, isisc_port_bc_filter_get), \ - SW_API_DEF(SW_API_CPU_PORT_STATUS_SET, isisc_cpu_port_status_set), \ - SW_API_DEF(SW_API_CPU_PORT_STATUS_GET, isisc_cpu_port_status_get), \ - SW_API_DEF(SW_API_PPPOE_CMD_SET, isisc_pppoe_cmd_set), \ - SW_API_DEF(SW_API_PPPOE_CMD_GET, isisc_pppoe_cmd_get), \ - SW_API_DEF(SW_API_PPPOE_STATUS_SET, isisc_pppoe_status_set), \ - SW_API_DEF(SW_API_PPPOE_STATUS_GET, isisc_pppoe_status_get), \ - SW_API_DEF(SW_API_PT_DHCP_SET, isisc_port_dhcp_set), \ - SW_API_DEF(SW_API_PT_DHCP_GET, isisc_port_dhcp_get), \ - SW_API_DEF(SW_API_ARP_CMD_SET, isisc_arp_cmd_set), \ - SW_API_DEF(SW_API_ARP_CMD_GET, isisc_arp_cmd_get), \ - SW_API_DEF(SW_API_EAPOL_CMD_SET, isisc_eapol_cmd_set), \ - SW_API_DEF(SW_API_EAPOL_CMD_GET, isisc_eapol_cmd_get), \ - SW_API_DEF(SW_API_EAPOL_STATUS_SET, isisc_eapol_status_set), \ - SW_API_DEF(SW_API_EAPOL_STATUS_GET, isisc_eapol_status_get), \ - SW_API_DEF(SW_API_RIPV1_STATUS_SET, isisc_ripv1_status_set), \ - SW_API_DEF(SW_API_RIPV1_STATUS_GET, isisc_ripv1_status_get), \ - SW_API_DEF(SW_API_PT_ARP_REQ_STATUS_SET, isisc_port_arp_req_status_set), \ - SW_API_DEF(SW_API_PT_ARP_REQ_STATUS_GET, isisc_port_arp_req_status_get), \ - SW_API_DEF(SW_API_PT_ARP_ACK_STATUS_SET, isisc_port_arp_ack_status_set), \ - SW_API_DEF(SW_API_PT_ARP_ACK_STATUS_GET, isisc_port_arp_ack_status_get), \ - SW_API_DEF(SW_API_PPPOE_SESSION_TABLE_ADD, isisc_pppoe_session_table_add), \ - SW_API_DEF(SW_API_PPPOE_SESSION_TABLE_DEL, isisc_pppoe_session_table_del), \ - SW_API_DEF(SW_API_PPPOE_SESSION_TABLE_GET, isisc_pppoe_session_table_get), \ - SW_API_DEF(SW_API_PPPOE_SESSION_ID_SET, isisc_pppoe_session_id_set), \ - SW_API_DEF(SW_API_PPPOE_SESSION_ID_GET, isisc_pppoe_session_id_get), \ - SW_API_DEF(SW_API_INTR_MASK_SET, isisc_intr_mask_set), \ - SW_API_DEF(SW_API_INTR_MASK_GET, isisc_intr_mask_get), \ - SW_API_DEF(SW_API_INTR_STATUS_GET, isisc_intr_status_get), \ - SW_API_DEF(SW_API_INTR_STATUS_CLEAR, isisc_intr_status_clear), \ - SW_API_DEF(SW_API_INTR_PORT_LINK_MASK_SET, isisc_intr_port_link_mask_set), \ - SW_API_DEF(SW_API_INTR_PORT_LINK_MASK_GET, isisc_intr_port_link_mask_get), \ - SW_API_DEF(SW_API_INTR_PORT_LINK_STATUS_GET, isisc_intr_port_link_status_get),\ - SW_API_DEF(SW_API_INTR_MASK_MAC_LINKCHG_SET, isisc_intr_mask_mac_linkchg_set), \ - SW_API_DEF(SW_API_INTR_MASK_MAC_LINKCHG_GET, isisc_intr_mask_mac_linkchg_get), \ - SW_API_DEF(SW_API_INTR_STATUS_MAC_LINKCHG_GET, isisc_intr_status_mac_linkchg_get), \ - SW_API_DEF(SW_API_INTR_STATUS_MAC_LINKCHG_CLEAR, isisc_intr_status_mac_linkchg_clear), \ - SW_API_DEF(SW_API_CPU_VID_EN_SET, isisc_cpu_vid_en_set), \ - SW_API_DEF(SW_API_CPU_VID_EN_GET, isisc_cpu_vid_en_get), \ - SW_API_DEF(SW_API_RTD_PPPOE_EN_SET, isisc_rtd_pppoe_en_set), \ - SW_API_DEF(SW_API_RTD_PPPOE_EN_GET, isisc_rtd_pppoe_en_get), - -#define MISC_API_PARAM \ - SW_API_DESC(SW_API_FRAME_MAX_SIZE_SET) \ - SW_API_DESC(SW_API_FRAME_MAX_SIZE_GET) \ - SW_API_DESC(SW_API_PT_UNK_UC_FILTER_SET) \ - SW_API_DESC(SW_API_PT_UNK_UC_FILTER_GET) \ - SW_API_DESC(SW_API_PT_UNK_MC_FILTER_SET) \ - SW_API_DESC(SW_API_PT_UNK_MC_FILTER_GET) \ - SW_API_DESC(SW_API_PT_BC_FILTER_SET) \ - SW_API_DESC(SW_API_PT_BC_FILTER_GET) \ - SW_API_DESC(SW_API_CPU_PORT_STATUS_SET) \ - SW_API_DESC(SW_API_CPU_PORT_STATUS_GET) \ - SW_API_DESC(SW_API_PPPOE_CMD_SET) \ - SW_API_DESC(SW_API_PPPOE_CMD_GET) \ - SW_API_DESC(SW_API_PPPOE_STATUS_SET) \ - SW_API_DESC(SW_API_PPPOE_STATUS_GET) \ - SW_API_DESC(SW_API_PT_DHCP_SET) \ - SW_API_DESC(SW_API_PT_DHCP_GET) \ - SW_API_DESC(SW_API_ARP_CMD_SET) \ - SW_API_DESC(SW_API_ARP_CMD_GET) \ - SW_API_DESC(SW_API_EAPOL_CMD_SET) \ - SW_API_DESC(SW_API_EAPOL_CMD_GET) \ - SW_API_DESC(SW_API_PPPOE_SESSION_ADD) \ - SW_API_DESC(SW_API_PPPOE_SESSION_DEL) \ - SW_API_DESC(SW_API_PPPOE_SESSION_GET) \ - SW_API_DESC(SW_API_EAPOL_STATUS_SET) \ - SW_API_DESC(SW_API_EAPOL_STATUS_GET) \ - SW_API_DESC(SW_API_RIPV1_STATUS_SET) \ - SW_API_DESC(SW_API_RIPV1_STATUS_GET) \ - SW_API_DESC(SW_API_PT_ARP_REQ_STATUS_SET) \ - SW_API_DESC(SW_API_PT_ARP_REQ_STATUS_GET) \ - SW_API_DESC(SW_API_PT_ARP_ACK_STATUS_SET) \ - SW_API_DESC(SW_API_PT_ARP_ACK_STATUS_GET) \ - SW_API_DESC(SW_API_PPPOE_SESSION_TABLE_ADD) \ - SW_API_DESC(SW_API_PPPOE_SESSION_TABLE_DEL) \ - SW_API_DESC(SW_API_PPPOE_SESSION_TABLE_GET) \ - SW_API_DESC(SW_API_PPPOE_SESSION_ID_SET) \ - SW_API_DESC(SW_API_PPPOE_SESSION_ID_GET) \ - SW_API_DESC(SW_API_INTR_MASK_SET) \ - SW_API_DESC(SW_API_INTR_MASK_GET) \ - SW_API_DESC(SW_API_INTR_STATUS_GET) \ - SW_API_DESC(SW_API_INTR_STATUS_CLEAR) \ - SW_API_DESC(SW_API_INTR_PORT_LINK_MASK_SET) \ - SW_API_DESC(SW_API_INTR_PORT_LINK_MASK_GET) \ - SW_API_DESC(SW_API_INTR_PORT_LINK_STATUS_GET) \ - SW_API_DESC(SW_API_INTR_MASK_MAC_LINKCHG_SET) \ - SW_API_DESC(SW_API_INTR_MASK_MAC_LINKCHG_GET) \ - SW_API_DESC(SW_API_INTR_STATUS_MAC_LINKCHG_GET) \ - SW_API_DESC(SW_API_INTR_STATUS_MAC_LINKCHG_CLEAR) \ - SW_API_DESC(SW_API_CPU_VID_EN_SET) \ - SW_API_DESC(SW_API_CPU_VID_EN_GET) \ - SW_API_DESC(SW_API_RTD_PPPOE_EN_SET) \ - SW_API_DESC(SW_API_RTD_PPPOE_EN_GET) - -#else -#define MISC_API -#define MISC_API_PARAM -#endif - - -#ifdef IN_LED -#define LED_API \ - SW_API_DEF(SW_API_LED_PATTERN_SET, isisc_led_ctrl_pattern_set), \ - SW_API_DEF(SW_API_LED_PATTERN_GET, isisc_led_ctrl_pattern_get), - -#define LED_API_PARAM \ - SW_API_DESC(SW_API_LED_PATTERN_SET) \ - SW_API_DESC(SW_API_LED_PATTERN_GET) -#else -#define LED_API -#define LED_API_PARAM -#endif - -#ifdef IN_COSMAP -#define COSMAP_API \ - SW_API_DEF(SW_API_COSMAP_DSCP_TO_PRI_SET, isisc_cosmap_dscp_to_pri_set), \ - SW_API_DEF(SW_API_COSMAP_DSCP_TO_PRI_GET, isisc_cosmap_dscp_to_pri_get), \ - SW_API_DEF(SW_API_COSMAP_DSCP_TO_DP_SET, isisc_cosmap_dscp_to_dp_set), \ - SW_API_DEF(SW_API_COSMAP_DSCP_TO_DP_GET, isisc_cosmap_dscp_to_dp_get), \ - SW_API_DEF(SW_API_COSMAP_UP_TO_PRI_SET, isisc_cosmap_up_to_pri_set), \ - SW_API_DEF(SW_API_COSMAP_UP_TO_PRI_GET, isisc_cosmap_up_to_pri_get), \ - SW_API_DEF(SW_API_COSMAP_UP_TO_DP_SET, isisc_cosmap_up_to_dp_set), \ - SW_API_DEF(SW_API_COSMAP_UP_TO_DP_GET, isisc_cosmap_up_to_dp_get), \ - SW_API_DEF(SW_API_COSMAP_PRI_TO_QU_SET, isisc_cosmap_pri_to_queue_set), \ - SW_API_DEF(SW_API_COSMAP_PRI_TO_QU_GET, isisc_cosmap_pri_to_queue_get), \ - SW_API_DEF(SW_API_COSMAP_PRI_TO_EHQU_SET, isisc_cosmap_pri_to_ehqueue_set), \ - SW_API_DEF(SW_API_COSMAP_PRI_TO_EHQU_GET, isisc_cosmap_pri_to_ehqueue_get), \ - SW_API_DEF(SW_API_COSMAP_EG_REMARK_SET, isisc_cosmap_egress_remark_set), \ - SW_API_DEF(SW_API_COSMAP_EG_REMARK_GET, isisc_cosmap_egress_remark_get), - -#define COSMAP_API_PARAM \ - SW_API_DESC(SW_API_COSMAP_DSCP_TO_PRI_SET) \ - SW_API_DESC(SW_API_COSMAP_DSCP_TO_PRI_GET) \ - SW_API_DESC(SW_API_COSMAP_DSCP_TO_DP_SET) \ - SW_API_DESC(SW_API_COSMAP_DSCP_TO_DP_GET) \ - SW_API_DESC(SW_API_COSMAP_UP_TO_PRI_SET) \ - SW_API_DESC(SW_API_COSMAP_UP_TO_PRI_GET) \ - SW_API_DESC(SW_API_COSMAP_UP_TO_DP_SET) \ - SW_API_DESC(SW_API_COSMAP_UP_TO_DP_GET) \ - SW_API_DESC(SW_API_COSMAP_PRI_TO_QU_SET) \ - SW_API_DESC(SW_API_COSMAP_PRI_TO_QU_GET) \ - SW_API_DESC(SW_API_COSMAP_PRI_TO_EHQU_SET) \ - SW_API_DESC(SW_API_COSMAP_PRI_TO_EHQU_GET) \ - SW_API_DESC(SW_API_COSMAP_EG_REMARK_SET) \ - SW_API_DESC(SW_API_COSMAP_EG_REMARK_GET) -#else -#define COSMAP_API -#define COSMAP_API_PARAM -#endif - -#ifdef IN_SEC -#define SEC_API \ - SW_API_DEF(SW_API_SEC_NORM_SET, isisc_sec_norm_item_set), \ - SW_API_DEF(SW_API_SEC_NORM_GET, isisc_sec_norm_item_get), \ - SW_API_DEF(SW_API_SEC_MAC_SET, isisc_sec_norm_item_set), \ - SW_API_DEF(SW_API_SEC_MAC_GET, isisc_sec_norm_item_get), \ - SW_API_DEF(SW_API_SEC_IP_SET, isisc_sec_norm_item_set), \ - SW_API_DEF(SW_API_SEC_IP_GET, isisc_sec_norm_item_get), \ - SW_API_DEF(SW_API_SEC_IP4_SET, isisc_sec_norm_item_set), \ - SW_API_DEF(SW_API_SEC_IP4_GET, isisc_sec_norm_item_get), \ - SW_API_DEF(SW_API_SEC_IP6_SET, isisc_sec_norm_item_set), \ - SW_API_DEF(SW_API_SEC_IP6_GET, isisc_sec_norm_item_get), \ - SW_API_DEF(SW_API_SEC_TCP_SET, isisc_sec_norm_item_set), \ - SW_API_DEF(SW_API_SEC_TCP_GET, isisc_sec_norm_item_get), \ - SW_API_DEF(SW_API_SEC_UDP_SET, isisc_sec_norm_item_set), \ - SW_API_DEF(SW_API_SEC_UDP_GET, isisc_sec_norm_item_get), \ - SW_API_DEF(SW_API_SEC_ICMP4_SET, isisc_sec_norm_item_set), \ - SW_API_DEF(SW_API_SEC_ICMP4_GET, isisc_sec_norm_item_get), \ - SW_API_DEF(SW_API_SEC_ICMP6_SET, isisc_sec_norm_item_set), \ - SW_API_DEF(SW_API_SEC_ICMP6_GET, isisc_sec_norm_item_get), - -#define SEC_API_PARAM \ - SW_API_DESC(SW_API_SEC_NORM_SET) \ - SW_API_DESC(SW_API_SEC_NORM_GET) \ - SW_API_DESC(SW_API_SEC_MAC_SET) \ - SW_API_DESC(SW_API_SEC_MAC_GET) \ - SW_API_DESC(SW_API_SEC_IP_SET) \ - SW_API_DESC(SW_API_SEC_IP_GET) \ - SW_API_DESC(SW_API_SEC_IP4_SET) \ - SW_API_DESC(SW_API_SEC_IP4_GET) \ - SW_API_DESC(SW_API_SEC_IP6_SET) \ - SW_API_DESC(SW_API_SEC_IP6_GET) \ - SW_API_DESC(SW_API_SEC_TCP_SET) \ - SW_API_DESC(SW_API_SEC_TCP_GET) \ - SW_API_DESC(SW_API_SEC_UDP_SET) \ - SW_API_DESC(SW_API_SEC_UDP_GET) \ - SW_API_DESC(SW_API_SEC_ICMP4_SET) \ - SW_API_DESC(SW_API_SEC_ICMP4_GET) \ - SW_API_DESC(SW_API_SEC_ICMP6_SET) \ - SW_API_DESC(SW_API_SEC_ICMP6_GET) -#else -#define SEC_API -#define SEC_API_PARAM -#endif - -#ifdef IN_IP -#define IP_API \ - SW_API_DEF(SW_API_IP_HOST_ADD, isisc_ip_host_add), \ - SW_API_DEF(SW_API_IP_HOST_DEL, isisc_ip_host_del), \ - SW_API_DEF(SW_API_IP_HOST_GET, isisc_ip_host_get), \ - SW_API_DEF(SW_API_IP_HOST_NEXT, isisc_ip_host_next), \ - SW_API_DEF(SW_API_IP_HOST_COUNTER_BIND, isisc_ip_host_counter_bind), \ - SW_API_DEF(SW_API_IP_HOST_PPPOE_BIND, isisc_ip_host_pppoe_bind), \ - SW_API_DEF(SW_API_IP_PT_ARP_LEARN_SET, isisc_ip_pt_arp_learn_set), \ - SW_API_DEF(SW_API_IP_PT_ARP_LEARN_GET, isisc_ip_pt_arp_learn_get), \ - SW_API_DEF(SW_API_IP_ARP_LEARN_SET, isisc_ip_arp_learn_set), \ - SW_API_DEF(SW_API_IP_ARP_LEARN_GET, isisc_ip_arp_learn_get), \ - SW_API_DEF(SW_API_IP_SOURCE_GUARD_SET, isisc_ip_source_guard_set), \ - SW_API_DEF(SW_API_IP_SOURCE_GUARD_GET, isisc_ip_source_guard_get), \ - SW_API_DEF(SW_API_IP_ARP_GUARD_SET, isisc_ip_arp_guard_set), \ - SW_API_DEF(SW_API_IP_ARP_GUARD_GET, isisc_ip_arp_guard_get), \ - SW_API_DEF(SW_API_IP_ROUTE_STATUS_SET, isisc_ip_route_status_set), \ - SW_API_DEF(SW_API_IP_ROUTE_STATUS_GET, isisc_ip_route_status_get), \ - SW_API_DEF(SW_API_IP_INTF_ENTRY_ADD, isisc_ip_intf_entry_add), \ - SW_API_DEF(SW_API_IP_INTF_ENTRY_DEL, isisc_ip_intf_entry_del), \ - SW_API_DEF(SW_API_IP_INTF_ENTRY_NEXT, isisc_ip_intf_entry_next), \ - SW_API_DEF(SW_API_IP_UNK_SOURCE_CMD_SET, isisc_ip_unk_source_cmd_set), \ - SW_API_DEF(SW_API_IP_UNK_SOURCE_CMD_GET, isisc_ip_unk_source_cmd_get), \ - SW_API_DEF(SW_API_ARP_UNK_SOURCE_CMD_SET, isisc_arp_unk_source_cmd_set), \ - SW_API_DEF(SW_API_ARP_UNK_SOURCE_CMD_GET, isisc_arp_unk_source_cmd_get), \ - SW_API_DEF(SW_API_IP_AGE_TIME_SET, isisc_ip_age_time_set), \ - SW_API_DEF(SW_API_IP_AGE_TIME_GET, isisc_ip_age_time_get), \ - SW_API_DEF(SW_API_WCMP_HASH_MODE_SET, isisc_ip_wcmp_hash_mode_set), \ - SW_API_DEF(SW_API_WCMP_HASH_MODE_GET, isisc_ip_wcmp_hash_mode_get), - -#define IP_API_PARAM \ - SW_API_DESC(SW_API_IP_HOST_ADD) \ - SW_API_DESC(SW_API_IP_HOST_DEL) \ - SW_API_DESC(SW_API_IP_HOST_GET) \ - SW_API_DESC(SW_API_IP_HOST_NEXT) \ - SW_API_DESC(SW_API_IP_HOST_COUNTER_BIND) \ - SW_API_DESC(SW_API_IP_HOST_PPPOE_BIND) \ - SW_API_DESC(SW_API_IP_PT_ARP_LEARN_SET) \ - SW_API_DESC(SW_API_IP_PT_ARP_LEARN_GET) \ - SW_API_DESC(SW_API_IP_ARP_LEARN_SET) \ - SW_API_DESC(SW_API_IP_ARP_LEARN_GET) \ - SW_API_DESC(SW_API_IP_SOURCE_GUARD_SET) \ - SW_API_DESC(SW_API_IP_SOURCE_GUARD_GET) \ - SW_API_DESC(SW_API_IP_ARP_GUARD_SET) \ - SW_API_DESC(SW_API_IP_ARP_GUARD_GET) \ - SW_API_DESC(SW_API_IP_ROUTE_STATUS_SET) \ - SW_API_DESC(SW_API_IP_ROUTE_STATUS_GET) \ - SW_API_DESC(SW_API_IP_INTF_ENTRY_ADD) \ - SW_API_DESC(SW_API_IP_INTF_ENTRY_DEL) \ - SW_API_DESC(SW_API_IP_INTF_ENTRY_NEXT) \ - SW_API_DESC(SW_API_IP_UNK_SOURCE_CMD_SET) \ - SW_API_DESC(SW_API_IP_UNK_SOURCE_CMD_GET) \ - SW_API_DESC(SW_API_ARP_UNK_SOURCE_CMD_SET) \ - SW_API_DESC(SW_API_ARP_UNK_SOURCE_CMD_GET) \ - SW_API_DESC(SW_API_IP_AGE_TIME_SET) \ - SW_API_DESC(SW_API_IP_AGE_TIME_GET) \ - SW_API_DESC(SW_API_WCMP_HASH_MODE_SET) \ - SW_API_DESC(SW_API_WCMP_HASH_MODE_GET) - -#else -#define IP_API -#define IP_API_PARAM -#endif - -#ifdef IN_NAT -#define NAT_API \ - SW_API_DEF(SW_API_NAT_ADD, isisc_nat_add), \ - SW_API_DEF(SW_API_NAT_DEL, isisc_nat_del), \ - SW_API_DEF(SW_API_NAT_GET, isisc_nat_get), \ - SW_API_DEF(SW_API_NAT_NEXT, isisc_nat_next), \ - SW_API_DEF(SW_API_NAT_COUNTER_BIND, isisc_nat_counter_bind), \ - SW_API_DEF(SW_API_NAPT_ADD, isisc_napt_add), \ - SW_API_DEF(SW_API_NAPT_DEL, isisc_napt_del), \ - SW_API_DEF(SW_API_NAPT_GET, isisc_napt_get), \ - SW_API_DEF(SW_API_NAPT_NEXT, isisc_napt_next), \ - SW_API_DEF(SW_API_NAPT_COUNTER_BIND, isisc_napt_counter_bind), \ - SW_API_DEF(SW_API_NAT_STATUS_SET, isisc_nat_status_set), \ - SW_API_DEF(SW_API_NAT_STATUS_GET, isisc_nat_status_get), \ - SW_API_DEF(SW_API_NAT_HASH_MODE_SET, isisc_nat_hash_mode_set), \ - SW_API_DEF(SW_API_NAT_HASH_MODE_GET, isisc_nat_hash_mode_get), \ - SW_API_DEF(SW_API_NAPT_STATUS_SET, isisc_napt_status_set), \ - SW_API_DEF(SW_API_NAPT_STATUS_GET, isisc_napt_status_get), \ - SW_API_DEF(SW_API_NAPT_MODE_SET, isisc_napt_mode_set), \ - SW_API_DEF(SW_API_NAPT_MODE_GET, isisc_napt_mode_get), \ - SW_API_DEF(SW_API_PRV_BASE_ADDR_SET, isisc_nat_prv_base_addr_set), \ - SW_API_DEF(SW_API_PRV_BASE_ADDR_GET, isisc_nat_prv_base_addr_get), \ - SW_API_DEF(SW_API_PUB_ADDR_ENTRY_ADD, isisc_nat_pub_addr_add), \ - SW_API_DEF(SW_API_PUB_ADDR_ENTRY_DEL, isisc_nat_pub_addr_del), \ - SW_API_DEF(SW_API_PUB_ADDR_ENTRY_NEXT, isisc_nat_pub_addr_next), \ - SW_API_DEF(SW_API_NAT_UNK_SESSION_CMD_SET, isisc_nat_unk_session_cmd_set), \ - SW_API_DEF(SW_API_NAT_UNK_SESSION_CMD_GET, isisc_nat_unk_session_cmd_get), \ - SW_API_DEF(SW_API_PRV_BASE_MASK_SET, isisc_nat_prv_base_mask_set), \ - SW_API_DEF(SW_API_PRV_BASE_MASK_GET, isisc_nat_prv_base_mask_get), \ - SW_API_DEF(SW_API_NAT_GLOBAL_SET, isisc_nat_global_set), - -#define NAT_API_PARAM \ - SW_API_DESC(SW_API_NAT_ADD) \ - SW_API_DESC(SW_API_NAT_DEL) \ - SW_API_DESC(SW_API_NAT_GET) \ - SW_API_DESC(SW_API_NAT_NEXT) \ - SW_API_DESC(SW_API_NAT_COUNTER_BIND) \ - SW_API_DESC(SW_API_NAPT_ADD) \ - SW_API_DESC(SW_API_NAPT_DEL) \ - SW_API_DESC(SW_API_NAPT_GET) \ - SW_API_DESC(SW_API_NAPT_NEXT) \ - SW_API_DESC(SW_API_NAPT_COUNTER_BIND) \ - SW_API_DESC(SW_API_NAT_STATUS_SET) \ - SW_API_DESC(SW_API_NAT_STATUS_GET) \ - SW_API_DESC(SW_API_NAT_HASH_MODE_SET) \ - SW_API_DESC(SW_API_NAT_HASH_MODE_GET) \ - SW_API_DESC(SW_API_NAPT_STATUS_SET) \ - SW_API_DESC(SW_API_NAPT_STATUS_GET) \ - SW_API_DESC(SW_API_NAPT_MODE_SET) \ - SW_API_DESC(SW_API_NAPT_MODE_GET) \ - SW_API_DESC(SW_API_PRV_BASE_ADDR_SET) \ - SW_API_DESC(SW_API_PRV_BASE_ADDR_GET) \ - SW_API_DESC(SW_API_PUB_ADDR_ENTRY_ADD) \ - SW_API_DESC(SW_API_PUB_ADDR_ENTRY_DEL) \ - SW_API_DESC(SW_API_PUB_ADDR_ENTRY_NEXT) \ - SW_API_DESC(SW_API_NAT_UNK_SESSION_CMD_SET) \ - SW_API_DESC(SW_API_NAT_UNK_SESSION_CMD_GET) \ - SW_API_DESC(SW_API_PRV_BASE_MASK_SET) \ - SW_API_DESC(SW_API_PRV_BASE_MASK_GET) \ - SW_API_DESC(SW_API_NAT_GLOBAL_SET) -#else -#define NAT_API -#define NAT_API_PARAM -#endif - -#ifdef IN_TRUNK -#define TRUNK_API \ - SW_API_DEF(SW_API_TRUNK_GROUP_SET, isisc_trunk_group_set), \ - SW_API_DEF(SW_API_TRUNK_GROUP_GET, isisc_trunk_group_get), \ - SW_API_DEF(SW_API_TRUNK_HASH_SET, isisc_trunk_hash_mode_set), \ - SW_API_DEF(SW_API_TRUNK_HASH_GET, isisc_trunk_hash_mode_get), \ - SW_API_DEF(SW_API_TRUNK_MAN_SA_SET, isisc_trunk_manipulate_sa_set), \ - SW_API_DEF(SW_API_TRUNK_MAN_SA_GET, isisc_trunk_manipulate_sa_get), - -#define TRUNK_API_PARAM \ - SW_API_DESC(SW_API_TRUNK_GROUP_SET) \ - SW_API_DESC(SW_API_TRUNK_GROUP_GET) \ - SW_API_DESC(SW_API_TRUNK_HASH_SET) \ - SW_API_DESC(SW_API_TRUNK_HASH_GET) \ - SW_API_DESC(SW_API_TRUNK_MAN_SA_SET)\ - SW_API_DESC(SW_API_TRUNK_MAN_SA_GET) -#else -#define TRUNK_API -#define TRUNK_API_PARAM -#endif - -#ifdef IN_INTERFACECONTROL -#define INTERFACECTRL_API \ - SW_API_DEF(SW_API_MAC_MODE_SET, isisc_interface_mac_mode_set), \ - SW_API_DEF(SW_API_MAC_MODE_GET, isisc_interface_mac_mode_get), \ - SW_API_DEF(SW_API_PORT_3AZ_STATUS_SET, isisc_port_3az_status_set), \ - SW_API_DEF(SW_API_PORT_3AZ_STATUS_GET, isisc_port_3az_status_get), \ - SW_API_DEF(SW_API_PHY_MODE_SET, isisc_interface_phy_mode_set), \ - SW_API_DEF(SW_API_PHY_MODE_GET, isisc_interface_phy_mode_get), \ - SW_API_DEF(SW_API_FX100_CTRL_SET, isisc_interface_fx100_ctrl_set), \ - SW_API_DEF(SW_API_FX100_CTRL_GET, isisc_interface_fx100_ctrl_get), \ - SW_API_DEF(SW_API_FX100_STATUS_GET, isisc_interface_fx100_status_get), \ - SW_API_DEF(SW_API_MAC06_EXCH_SET, isisc_interface_mac06_exch_set), \ - SW_API_DEF(SW_API_MAC06_EXCH_GET, isisc_interface_mac06_exch_get), - -#define INTERFACECTRL_API_PARAM \ - SW_API_DESC(SW_API_MAC_MODE_SET) \ - SW_API_DESC(SW_API_MAC_MODE_GET) \ - SW_API_DESC(SW_API_PORT_3AZ_STATUS_SET) \ - SW_API_DESC(SW_API_PORT_3AZ_STATUS_GET) \ - SW_API_DESC(SW_API_PHY_MODE_SET) \ - SW_API_DESC(SW_API_PHY_MODE_GET) \ - SW_API_DESC(SW_API_FX100_CTRL_SET) \ - SW_API_DESC(SW_API_FX100_CTRL_GET) \ - SW_API_DESC(SW_API_FX100_STATUS_GET) \ - SW_API_DESC(SW_API_MAC06_EXCH_SET) \ - SW_API_DESC(SW_API_MAC06_EXCH_GET) - -#else -#define INTERFACECTRL_API -#define INTERFACECTRL_API_PARAM -#endif - -#define REG_API \ - SW_API_DEF(SW_API_PHY_GET, isisc_phy_get), \ - SW_API_DEF(SW_API_PHY_SET, isisc_phy_set), \ - SW_API_DEF(SW_API_REG_GET, isisc_reg_get), \ - SW_API_DEF(SW_API_REG_SET, isisc_reg_set), \ - SW_API_DEF(SW_API_REG_FIELD_GET, isisc_reg_field_get), \ - SW_API_DEF(SW_API_REG_FIELD_SET, isisc_reg_field_set), \ - SW_API_DEF(SW_API_REG_DUMP, isisc_regsiter_dump), \ - SW_API_DEF(SW_API_DBG_REG_DUMP, isisc_debug_regsiter_dump), - -#define REG_API_PARAM \ - SW_API_DESC(SW_API_PHY_GET) \ - SW_API_DESC(SW_API_PHY_SET) \ - SW_API_DESC(SW_API_REG_GET) \ - SW_API_DESC(SW_API_REG_SET) \ - SW_API_DESC(SW_API_REG_FIELD_GET) \ - SW_API_DESC(SW_API_REG_FIELD_SET) \ - SW_API_DESC(SW_API_REG_DUMP) \ - SW_API_DESC(SW_API_DBG_REG_DUMP) - -#define SSDK_API \ - SW_API_DEF(SW_API_SWITCH_RESET, isisc_reset), \ - SW_API_DEF(SW_API_SSDK_CFG, hsl_ssdk_cfg), \ - PORTCONTROL_API \ - VLAN_API \ - PORTVLAN_API \ - FDB_API \ - ACL_API \ - QOS_API \ - IGMP_API \ - LEAKY_API \ - MIRROR_API \ - RATE_API \ - STP_API \ - MIB_API \ - MISC_API \ - LED_API \ - COSMAP_API \ - SEC_API \ - IP_API \ - NAT_API \ - TRUNK_API \ - INTERFACECTRL_API \ - REG_API \ - SW_API_DEF(SW_API_MAX, NULL), - - -#define SSDK_PARAM \ - SW_PARAM_DEF(SW_API_SWITCH_RESET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \ - SW_PARAM_DEF(SW_API_SSDK_CFG, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \ - SW_PARAM_DEF(SW_API_SSDK_CFG, SW_SSDK_CFG, sizeof(ssdk_cfg_t), SW_PARAM_PTR|SW_PARAM_OUT, "ssdk configuration"), \ - MIB_API_PARAM \ - LEAKY_API_PARAM \ - MISC_API_PARAM \ - IGMP_API_PARAM \ - MIRROR_API_PARAM \ - PORTCONTROL_API_PARAM \ - PORTVLAN_API_PARAM \ - VLAN_API_PARAM \ - FDB_API_PARAM \ - QOS_API_PARAM \ - RATE_API_PARAM \ - STP_API_PARAM \ - ACL_API_PARAM \ - LED_API_PARAM \ - COSMAP_API_PARAM \ - SEC_API_PARAM \ - IP_API_PARAM \ - NAT_API_PARAM \ - TRUNK_API_PARAM \ - INTERFACECTRL_API_PARAM \ - REG_API_PARAM \ - SW_PARAM_DEF(SW_API_MAX, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), - -#if (defined(USER_MODE) && defined(KERNEL_MODULE)) -#undef SSDK_API -#undef SSDK_PARAM - -#define SSDK_API \ - REG_API \ - SW_API_DEF(SW_API_MAX, NULL), - -#define SSDK_PARAM \ - REG_API_PARAM \ - SW_PARAM_DEF(SW_API_MAX, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), -#endif - -#ifdef __cplusplus -} -#endif /* __cplusplus */ - -#endif /* _ISISC_API_H_ */ diff --git a/feeds/ipq807x/qca-ssdk/src/include/hsl/isisc/isisc_cosmap.h b/feeds/ipq807x/qca-ssdk/src/include/hsl/isisc/isisc_cosmap.h deleted file mode 100755 index d79a20bc9..000000000 --- a/feeds/ipq807x/qca-ssdk/src/include/hsl/isisc/isisc_cosmap.h +++ /dev/null @@ -1,109 +0,0 @@ -/* - * Copyright (c) 2012, The Linux Foundation. All rights reserved. - * Permission to use, copy, modify, and/or distribute this software for - * any purpose with or without fee is hereby granted, provided that the - * above copyright notice and this permission notice appear in all copies. - * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES - * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR - * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES - * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN - * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT - * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. - */ - - -/** - * @defgroup isisc_cosmap ISISC_COSMAP - * @{ - */ -#ifndef _ISISC_COSMAP_H_ -#define _ISISC_COSMAP_H_ - -#ifdef __cplusplus -extern "C" { -#endif /* __cplusplus */ - -#include "fal/fal_cosmap.h" - - sw_error_t isisc_cosmap_init(a_uint32_t dev_id); - -#ifdef IN_COSMAP -#define ISISC_COSMAP_INIT(rv, dev_id) \ - { \ - rv = isisc_cosmap_init(dev_id); \ - SW_RTN_ON_ERROR(rv); \ - } -#else -#define ISISC_COSMAP_INIT(rv, dev_id) -#endif - -#ifdef HSL_STANDALONG - - HSL_LOCAL sw_error_t - isisc_cosmap_dscp_to_pri_set(a_uint32_t dev_id, a_uint32_t dscp, - a_uint32_t pri); - - HSL_LOCAL sw_error_t - isisc_cosmap_dscp_to_pri_get(a_uint32_t dev_id, a_uint32_t dscp, - a_uint32_t * pri); - - HSL_LOCAL sw_error_t - isisc_cosmap_dscp_to_dp_set(a_uint32_t dev_id, a_uint32_t dscp, - a_uint32_t dp); - - HSL_LOCAL sw_error_t - isisc_cosmap_dscp_to_dp_get(a_uint32_t dev_id, a_uint32_t dscp, - a_uint32_t * dp); - - HSL_LOCAL sw_error_t - isisc_cosmap_up_to_pri_set(a_uint32_t dev_id, a_uint32_t up, - a_uint32_t pri); - - HSL_LOCAL sw_error_t - isisc_cosmap_up_to_pri_get(a_uint32_t dev_id, a_uint32_t up, - a_uint32_t * pri); - - HSL_LOCAL sw_error_t - isisc_cosmap_up_to_dp_set(a_uint32_t dev_id, a_uint32_t up, - a_uint32_t dp); - - HSL_LOCAL sw_error_t - isisc_cosmap_up_to_dp_get(a_uint32_t dev_id, a_uint32_t up, - a_uint32_t * dp); - - HSL_LOCAL sw_error_t - isisc_cosmap_pri_to_queue_set(a_uint32_t dev_id, a_uint32_t pri, - a_uint32_t queue); - - HSL_LOCAL sw_error_t - isisc_cosmap_pri_to_queue_get(a_uint32_t dev_id, a_uint32_t pri, - a_uint32_t * queue); - - HSL_LOCAL sw_error_t - isisc_cosmap_pri_to_ehqueue_set(a_uint32_t dev_id, a_uint32_t pri, - a_uint32_t queue); - - HSL_LOCAL sw_error_t - isisc_cosmap_pri_to_ehqueue_get(a_uint32_t dev_id, a_uint32_t pri, - a_uint32_t * queue); - - HSL_LOCAL sw_error_t - isisc_cosmap_egress_remark_set(a_uint32_t dev_id, a_uint32_t tbl_id, - fal_egress_remark_table_t * tbl); - - HSL_LOCAL sw_error_t - isisc_cosmap_egress_remark_get(a_uint32_t dev_id, a_uint32_t tbl_id, - fal_egress_remark_table_t * tbl); - -#endif - -#ifdef __cplusplus -} -#endif /* __cplusplus */ -#endif /* _ISISC_COSMAP_H_ */ - -/** - * @} - */ - diff --git a/feeds/ipq807x/qca-ssdk/src/include/hsl/isisc/isisc_fdb.h b/feeds/ipq807x/qca-ssdk/src/include/hsl/isisc/isisc_fdb.h deleted file mode 100755 index 13cd37c8b..000000000 --- a/feeds/ipq807x/qca-ssdk/src/include/hsl/isisc/isisc_fdb.h +++ /dev/null @@ -1,168 +0,0 @@ -/* - * Copyright (c) 2012, The Linux Foundation. All rights reserved. - * Permission to use, copy, modify, and/or distribute this software for - * any purpose with or without fee is hereby granted, provided that the - * above copyright notice and this permission notice appear in all copies. - * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES - * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR - * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES - * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN - * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT - * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. - */ - - -/** - * @defgroup isisc_fdb ISISC_FDB - * @{ - */ -#ifndef _ISISC_FDB_H_ -#define _ISISC_FDB_H_ - -#ifdef __cplusplus -extern "C" { -#endif /* __cplusplus */ - -#include "fal/fal_fdb.h" - - sw_error_t isisc_fdb_init(a_uint32_t dev_id); - -#ifdef IN_FDB -#define ISISC_FDB_INIT(rv, dev_id) \ - { \ - rv = isisc_fdb_init(dev_id); \ - SW_RTN_ON_ERROR(rv); \ - } -#else -#define ISISC_FDB_INIT(rv, dev_id) -#endif - -#ifdef HSL_STANDALONG - - HSL_LOCAL sw_error_t - isisc_fdb_add(a_uint32_t dev_id, const fal_fdb_entry_t * entry); - - HSL_LOCAL sw_error_t - isisc_fdb_find(a_uint32_t dev_id, fal_fdb_entry_t * entry); - - HSL_LOCAL sw_error_t - isisc_fdb_del_all(a_uint32_t dev_id, a_uint32_t flag); - - HSL_LOCAL sw_error_t - isisc_fdb_del_by_port(a_uint32_t dev_id, fal_port_t port_id, - a_uint32_t flag); - - HSL_LOCAL sw_error_t - isisc_fdb_del_by_mac(a_uint32_t dev_id, const fal_fdb_entry_t * entry); - - HSL_LOCAL sw_error_t - isisc_fdb_extend_next(a_uint32_t dev_id, fal_fdb_op_t * op, - fal_fdb_entry_t * entry); - - HSL_LOCAL sw_error_t - isisc_fdb_extend_first(a_uint32_t dev_id, fal_fdb_op_t * option, - fal_fdb_entry_t * entry); - - HSL_LOCAL sw_error_t - isisc_fdb_transfer(a_uint32_t dev_id, fal_port_t old_port, - fal_port_t new_port, a_uint32_t fid, - fal_fdb_op_t * option); - - HSL_LOCAL sw_error_t - isisc_fdb_port_learn_set(a_uint32_t dev_id, fal_port_t port_id, - a_bool_t enable); - - HSL_LOCAL sw_error_t - isisc_fdb_port_learn_get(a_uint32_t dev_id, fal_port_t port_id, - a_bool_t * enable); - - HSL_LOCAL sw_error_t - isisc_fdb_age_ctrl_set(a_uint32_t dev_id, a_bool_t enable); - - HSL_LOCAL sw_error_t - isisc_fdb_age_ctrl_get(a_uint32_t dev_id, a_bool_t * enable); - - HSL_LOCAL sw_error_t - isisc_fdb_vlan_ivl_svl_set(a_uint32_t dev_id, fal_fdb_smode smode); - - HSL_LOCAL sw_error_t - isisc_fdb_vlan_ivl_svl_get(a_uint32_t dev_id, fal_fdb_smode * smode); - - HSL_LOCAL sw_error_t - isisc_fdb_age_time_set(a_uint32_t dev_id, a_uint32_t * time); - - HSL_LOCAL sw_error_t - isisc_fdb_age_time_get(a_uint32_t dev_id, a_uint32_t * time); - - HSL_LOCAL sw_error_t - isisc_port_fdb_learn_limit_set(a_uint32_t dev_id, fal_port_t port_id, - a_bool_t enable, a_uint32_t cnt); - - HSL_LOCAL sw_error_t - isisc_port_fdb_learn_limit_get(a_uint32_t dev_id, fal_port_t port_id, - a_bool_t * enable, a_uint32_t * cnt); - - HSL_LOCAL sw_error_t - isisc_port_fdb_learn_exceed_cmd_set(a_uint32_t dev_id, - fal_port_t port_id, - fal_fwd_cmd_t cmd); - - HSL_LOCAL sw_error_t - isisc_port_fdb_learn_exceed_cmd_get(a_uint32_t dev_id, - fal_port_t port_id, - fal_fwd_cmd_t * cmd); - - HSL_LOCAL sw_error_t - isisc_fdb_learn_limit_set(a_uint32_t dev_id, a_bool_t enable, - a_uint32_t cnt); - - HSL_LOCAL sw_error_t - isisc_fdb_learn_limit_get(a_uint32_t dev_id, a_bool_t * enable, - a_uint32_t * cnt); - - HSL_LOCAL sw_error_t - isisc_fdb_learn_exceed_cmd_set(a_uint32_t dev_id, fal_fwd_cmd_t cmd); - - HSL_LOCAL sw_error_t - isisc_fdb_learn_exceed_cmd_get(a_uint32_t dev_id, fal_fwd_cmd_t * cmd); - - HSL_LOCAL sw_error_t - isisc_fdb_resv_add(a_uint32_t dev_id, fal_fdb_entry_t * entry); - - HSL_LOCAL sw_error_t - isisc_fdb_resv_del(a_uint32_t dev_id, fal_fdb_entry_t * entry); - - HSL_LOCAL sw_error_t - isisc_fdb_resv_find(a_uint32_t dev_id, fal_fdb_entry_t * entry); - - HSL_LOCAL sw_error_t - isisc_fdb_resv_iterate(a_uint32_t dev_id, a_uint32_t * iterator, - fal_fdb_entry_t * entry); - - HSL_LOCAL sw_error_t - isisc_fdb_port_learn_static_set(a_uint32_t dev_id, fal_port_t port_id, - a_bool_t enable); - - HSL_LOCAL sw_error_t - isisc_fdb_port_learn_static_get(a_uint32_t dev_id, fal_port_t port_id, - a_bool_t * enable); - - HSL_LOCAL sw_error_t - isisc_fdb_port_add(a_uint32_t dev_id, a_uint32_t fid, fal_mac_addr_t * addr, fal_port_t port_id); - - HSL_LOCAL sw_error_t - isisc_fdb_port_del(a_uint32_t dev_id, a_uint32_t fid, fal_mac_addr_t * addr, fal_port_t port_id); - - -#endif - -#ifdef __cplusplus -} -#endif /* __cplusplus */ -#endif /* _ISISC_FDB_H_ */ - -/** - * @} - */ - diff --git a/feeds/ipq807x/qca-ssdk/src/include/hsl/isisc/isisc_fdb_prv.h b/feeds/ipq807x/qca-ssdk/src/include/hsl/isisc/isisc_fdb_prv.h deleted file mode 100755 index a67e58dc7..000000000 --- a/feeds/ipq807x/qca-ssdk/src/include/hsl/isisc/isisc_fdb_prv.h +++ /dev/null @@ -1,49 +0,0 @@ -/* - * Copyright (c) 2012, The Linux Foundation. All rights reserved. - * Permission to use, copy, modify, and/or distribute this software for - * any purpose with or without fee is hereby granted, provided that the - * above copyright notice and this permission notice appear in all copies. - * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES - * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR - * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES - * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN - * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT - * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. - */ - - -#ifndef _ISISC_FDB_PRV_H_ -#define _ISISC_FDB_PRV_H_ - -#ifdef __cplusplus -extern "C" { -#endif /* __cplusplus */ - - -#define ARL_FLUSH_ALL 1 -#define ARL_LOAD_ENTRY 2 -#define ARL_PURGE_ENTRY 3 -#define ARL_FLUSH_ALL_UNLOCK 4 -#define ARL_FLUSH_PORT_UNICAST 5 -#define ARL_NEXT_ENTRY 6 -#define ARL_FIND_ENTRY 7 -#define ARL_TRANSFER_ENTRY 8 - -#define ARL_FIRST_ENTRY 1001 -#define ARL_FLUSH_PORT_NO_STATIC 1002 -#define ARL_FLUSH_PORT_AND_STATIC 1003 - -#define ISISC_MAX_FID 4095 -#define ISISC_MAX_LEARN_LIMIT_CNT 2048 -#define ISISC_MAX_PORT_LEARN_LIMIT_CNT 1024 - - sw_error_t - inter_isisc_fdb_flush(a_uint32_t dev_id, a_uint32_t flag); - - -#ifdef __cplusplus -} -#endif /* __cplusplus */ -#endif /* _ISISC_FDB_PRV_H_ */ - diff --git a/feeds/ipq807x/qca-ssdk/src/include/hsl/isisc/isisc_igmp.h b/feeds/ipq807x/qca-ssdk/src/include/hsl/isisc/isisc_igmp.h deleted file mode 100755 index 7d83f5d23..000000000 --- a/feeds/ipq807x/qca-ssdk/src/include/hsl/isisc/isisc_igmp.h +++ /dev/null @@ -1,165 +0,0 @@ -/* - * Copyright (c) 2012, The Linux Foundation. All rights reserved. - * Permission to use, copy, modify, and/or distribute this software for - * any purpose with or without fee is hereby granted, provided that the - * above copyright notice and this permission notice appear in all copies. - * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES - * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR - * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES - * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN - * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT - * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. - */ - - -/** - * @defgroup isisc_igmp ISISC_IGMP - * @{ - */ -#ifndef _ISISC_IGMP_H_ -#define _ISISC_IGMP_H_ - -#ifdef __cplusplus -extern "C" { -#endif /* __cplusplus */ - -#include "fal/fal_igmp.h" -#include "fal/fal_multi.h" - - sw_error_t - isisc_igmp_init(a_uint32_t dev_id); - -#ifdef IN_IGMP -#define ISISC_IGMP_INIT(rv, dev_id) \ - { \ - rv = isisc_igmp_init(dev_id); \ - SW_RTN_ON_ERROR(rv); \ - } -#else -#define ISISC_IGMP_INIT(rv, dev_id) -#endif - -#ifdef HSL_STANDALONG - - HSL_LOCAL sw_error_t - isisc_port_igmps_status_set(a_uint32_t dev_id, fal_port_t port_id, a_bool_t enable); - - - HSL_LOCAL sw_error_t - isisc_port_igmps_status_get(a_uint32_t dev_id, fal_port_t port_id, a_bool_t *enable); - - - HSL_LOCAL sw_error_t - isisc_igmp_mld_cmd_set(a_uint32_t dev_id, fal_fwd_cmd_t cmd); - - - HSL_LOCAL sw_error_t - isisc_igmp_mld_cmd_get(a_uint32_t dev_id, fal_fwd_cmd_t * cmd); - - - HSL_LOCAL sw_error_t - isisc_port_igmp_mld_join_set(a_uint32_t dev_id, fal_port_t port_id, a_bool_t enable); - - - HSL_LOCAL sw_error_t - isisc_port_igmp_mld_join_get(a_uint32_t dev_id, fal_port_t port_id, a_bool_t * enable); - - - HSL_LOCAL sw_error_t - isisc_port_igmp_mld_leave_set(a_uint32_t dev_id, fal_port_t port_id, a_bool_t enable); - - - HSL_LOCAL sw_error_t - isisc_port_igmp_mld_leave_get(a_uint32_t dev_id, fal_port_t port_id, a_bool_t * enable); - - - HSL_LOCAL sw_error_t - isisc_igmp_mld_rp_set(a_uint32_t dev_id, fal_pbmp_t pts); - - - HSL_LOCAL sw_error_t - isisc_igmp_mld_rp_get(a_uint32_t dev_id, fal_pbmp_t * pts); - - - HSL_LOCAL sw_error_t - isisc_igmp_mld_entry_creat_set(a_uint32_t dev_id, a_bool_t enable); - - - HSL_LOCAL sw_error_t - isisc_igmp_mld_entry_creat_get(a_uint32_t dev_id, a_bool_t * enable); - - - HSL_LOCAL sw_error_t - isisc_igmp_mld_entry_static_set(a_uint32_t dev_id, a_bool_t enable); - - - HSL_LOCAL sw_error_t - isisc_igmp_mld_entry_static_get(a_uint32_t dev_id, a_bool_t * enable); - - - HSL_LOCAL sw_error_t - isisc_igmp_mld_entry_leaky_set(a_uint32_t dev_id, a_bool_t enable); - - - HSL_LOCAL sw_error_t - isisc_igmp_mld_entry_leaky_get(a_uint32_t dev_id, a_bool_t * enable); - - - HSL_LOCAL sw_error_t - isisc_igmp_mld_entry_v3_set(a_uint32_t dev_id, a_bool_t enable); - - - HSL_LOCAL sw_error_t - isisc_igmp_mld_entry_v3_get(a_uint32_t dev_id, a_bool_t * enable); - - - HSL_LOCAL sw_error_t - isisc_igmp_mld_entry_queue_set(a_uint32_t dev_id, a_bool_t enable, a_uint32_t queue); - - - HSL_LOCAL sw_error_t - isisc_igmp_mld_entry_queue_get(a_uint32_t dev_id, a_bool_t * enable, a_uint32_t * queue); - - - HSL_LOCAL sw_error_t - isisc_port_igmp_mld_learn_limit_set(a_uint32_t dev_id, fal_port_t port_id, - a_bool_t enable, a_uint32_t cnt); - - - HSL_LOCAL sw_error_t - isisc_port_igmp_mld_learn_limit_get(a_uint32_t dev_id, fal_port_t port_id, - a_bool_t * enable, a_uint32_t * cnt); - - - HSL_LOCAL sw_error_t - isisc_port_igmp_mld_learn_exceed_cmd_set(a_uint32_t dev_id, fal_port_t port_id, - fal_fwd_cmd_t cmd); - - - HSL_LOCAL sw_error_t - isisc_port_igmp_mld_learn_exceed_cmd_get(a_uint32_t dev_id, fal_port_t port_id, - fal_fwd_cmd_t * cmd); - - HSL_LOCAL sw_error_t - isisc_igmp_sg_entry_set(a_uint32_t dev_id, fal_igmp_sg_entry_t * entry); - - HSL_LOCAL sw_error_t - isisc_igmp_sg_entry_clear(a_uint32_t dev_id, fal_igmp_sg_entry_t * entry); - - HSL_LOCAL sw_error_t - isisc_igmp_sg_entry_show(a_uint32_t dev_id); - - HSL_LOCAL sw_error_t - isisc_igmp_sg_entry_query(a_uint32_t dev_id, fal_igmp_sg_info_t * info); - -#endif - -#ifdef __cplusplus -} -#endif /* __cplusplus */ - -#endif /* _ISISC_IGMP_H_ */ -/** - * @} - */ diff --git a/feeds/ipq807x/qca-ssdk/src/include/hsl/isisc/isisc_init.h b/feeds/ipq807x/qca-ssdk/src/include/hsl/isisc/isisc_init.h deleted file mode 100755 index 18e8b0752..000000000 --- a/feeds/ipq807x/qca-ssdk/src/include/hsl/isisc/isisc_init.h +++ /dev/null @@ -1,51 +0,0 @@ -/* - * Copyright (c) 2012, The Linux Foundation. All rights reserved. - * Permission to use, copy, modify, and/or distribute this software for - * any purpose with or without fee is hereby granted, provided that the - * above copyright notice and this permission notice appear in all copies. - * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES - * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR - * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES - * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN - * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT - * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. - */ - - -/** - * @defgroup isisc_init ISISC_INIT - * @{ - */ -#ifndef _ISISC_INIT_H_ -#define _ISISC_INIT_H_ - -#ifdef __cplusplus -extern "C" { -#endif /* __cplusplus */ - -#include "init/ssdk_init.h" - - - sw_error_t - isisc_init(a_uint32_t dev_id, ssdk_init_cfg *cfg); - - - sw_error_t - isisc_cleanup(a_uint32_t dev_id); - -#ifdef HSL_STANDALONG - - HSL_LOCAL sw_error_t - isisc_reset(a_uint32_t dev_id); - -#endif - -#ifdef __cplusplus -} -#endif /* __cplusplus */ - -#endif /* _ISISC_INIT_H_ */ -/** - * @} - */ diff --git a/feeds/ipq807x/qca-ssdk/src/include/hsl/isisc/isisc_interface_ctrl.h b/feeds/ipq807x/qca-ssdk/src/include/hsl/isisc/isisc_interface_ctrl.h deleted file mode 100755 index 2c9a9abb7..000000000 --- a/feeds/ipq807x/qca-ssdk/src/include/hsl/isisc/isisc_interface_ctrl.h +++ /dev/null @@ -1,78 +0,0 @@ -/* - * Copyright (c) 2012, The Linux Foundation. All rights reserved. - * Permission to use, copy, modify, and/or distribute this software for - * any purpose with or without fee is hereby granted, provided that the - * above copyright notice and this permission notice appear in all copies. - * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES - * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR - * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES - * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN - * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT - * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. - */ - - -#ifndef _ISISC_INTERFACE_CTRL_H_ -#define _ISISC_INTERFACE_CTRL_H_ - -#ifdef __cplusplus -extern "C" { -#endif /* __cplusplus */ - -#include "fal/fal_interface_ctrl.h" - - sw_error_t isisc_interface_ctrl_init(a_uint32_t dev_id); - -#ifdef IN_INTERFACECONTROL -#define ISISC_INTERFACE_CTRL_INIT(rv, dev_id) \ - { \ - rv = isisc_interface_ctrl_init(dev_id); \ - SW_RTN_ON_ERROR(rv); \ - } -#else -#define ISISC_INTERFACE_CTRL_INIT(rv, dev_id) -#endif - -#ifdef HSL_STANDALONG - - HSL_LOCAL sw_error_t - isisc_port_3az_status_set(a_uint32_t dev_id, fal_port_t port_id, a_bool_t enable); - - HSL_LOCAL sw_error_t - isisc_port_3az_status_get(a_uint32_t dev_id, fal_port_t port_id, a_bool_t * enable); - - HSL_LOCAL sw_error_t - isisc_interface_mac_mode_set(a_uint32_t dev_id, fal_port_t port_id, fal_mac_config_t * config); - - - HSL_LOCAL sw_error_t - isisc_interface_mac_mode_get(a_uint32_t dev_id, fal_port_t port_id, fal_mac_config_t * config); - - HSL_LOCAL sw_error_t - isisc_interface_phy_mode_set(a_uint32_t dev_id, a_uint32_t phy_id, fal_phy_config_t * config); - - HSL_LOCAL sw_error_t - isisc_interface_phy_mode_get(a_uint32_t dev_id, a_uint32_t phy_id, fal_phy_config_t * config); - - HSL_LOCAL sw_error_t - isisc_interface_fx100_ctrl_set(a_uint32_t dev_id, fal_fx100_ctrl_config_t* config); - - HSL_LOCAL sw_error_t - isisc_interface_fx100_ctrl_get(a_uint32_t dev_id, fal_fx100_ctrl_config_t* config); - - HSL_LOCAL sw_error_t - isisc_interface_fx100_status_get(a_uint32_t dev_id, a_uint32_t* status); - - HSL_LOCAL sw_error_t - isisc_interface_mac06_exch_set(a_uint32_t dev_id, a_bool_t enable); - - HSL_LOCAL sw_error_t - isisc_interface_mac06_exch_get(a_uint32_t dev_id, a_bool_t* enable); -#endif - -#ifdef __cplusplus -} -#endif /* __cplusplus */ -#endif /* _ISISC_INTERFACE_CTRL_H_ */ - diff --git a/feeds/ipq807x/qca-ssdk/src/include/hsl/isisc/isisc_ip.h b/feeds/ipq807x/qca-ssdk/src/include/hsl/isisc/isisc_ip.h deleted file mode 100755 index bf900144a..000000000 --- a/feeds/ipq807x/qca-ssdk/src/include/hsl/isisc/isisc_ip.h +++ /dev/null @@ -1,153 +0,0 @@ -/* - * Copyright (c) 2012, The Linux Foundation. All rights reserved. - * Permission to use, copy, modify, and/or distribute this software for - * any purpose with or without fee is hereby granted, provided that the - * above copyright notice and this permission notice appear in all copies. - * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES - * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR - * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES - * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN - * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT - * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. - */ - - -#ifndef _ISISC_IP_H_ -#define _ISISC_IP_H_ - -#ifdef __cplusplus -extern "C" { -#endif /* __cplusplus */ - -#include "fal/fal_ip.h" - - sw_error_t isisc_ip_init(a_uint32_t dev_id); - - sw_error_t isisc_ip_reset(a_uint32_t dev_id); - -#ifdef IN_IP -#define ISISC_IP_INIT(rv, dev_id) \ - { \ - rv = isisc_ip_init(dev_id); \ - SW_RTN_ON_ERROR(rv); \ - } - -#define ISISC_IP_RESET(rv, dev_id) \ - { \ - rv = isisc_ip_reset(dev_id); \ - SW_RTN_ON_ERROR(rv); \ - } -#else -#define ISISC_IP_INIT(rv, dev_id) -#define ISISC_IP_RESET(rv, dev_id) -#endif - -#ifdef HSL_STANDALONG - - HSL_LOCAL sw_error_t - isisc_ip_host_add(a_uint32_t dev_id, fal_host_entry_t * host_entry); - - HSL_LOCAL sw_error_t - isisc_ip_intf_entry_add(a_uint32_t dev_id, fal_intf_mac_entry_t * entry); - - HSL_LOCAL sw_error_t - isisc_ip_host_del(a_uint32_t dev_id, a_uint32_t del_mode, - fal_host_entry_t * host_entry); - - HSL_LOCAL sw_error_t - isisc_ip_host_get(a_uint32_t dev_id, a_uint32_t get_mode, - fal_host_entry_t * host_entry); - - HSL_LOCAL sw_error_t - isisc_ip_host_next(a_uint32_t dev_id, a_uint32_t next_mode, - fal_host_entry_t * host_entry); - - HSL_LOCAL sw_error_t - isisc_ip_host_counter_bind(a_uint32_t dev_id, a_uint32_t entry_id, - a_uint32_t cnt_id, a_bool_t enable); - - HSL_LOCAL sw_error_t - isisc_ip_host_pppoe_bind(a_uint32_t dev_id, a_uint32_t entry_id, - a_uint32_t pppoe_id, a_bool_t enable); - - HSL_LOCAL sw_error_t - isisc_ip_pt_arp_learn_set(a_uint32_t dev_id, fal_port_t port_id, - a_uint32_t flags); - - HSL_LOCAL sw_error_t - isisc_ip_pt_arp_learn_get(a_uint32_t dev_id, fal_port_t port_id, - a_uint32_t * flags); - - HSL_LOCAL sw_error_t - isisc_ip_arp_learn_set(a_uint32_t dev_id, fal_arp_learn_mode_t mode); - - HSL_LOCAL sw_error_t - isisc_ip_arp_learn_get(a_uint32_t dev_id, fal_arp_learn_mode_t * mode); - - HSL_LOCAL sw_error_t - isisc_ip_source_guard_set(a_uint32_t dev_id, fal_port_t port_id, - fal_source_guard_mode_t mode); - - HSL_LOCAL sw_error_t - isisc_ip_source_guard_get(a_uint32_t dev_id, fal_port_t port_id, - fal_source_guard_mode_t * mode); - - HSL_LOCAL sw_error_t - isisc_ip_unk_source_cmd_set(a_uint32_t dev_id, fal_fwd_cmd_t cmd); - - HSL_LOCAL sw_error_t - isisc_ip_unk_source_cmd_get(a_uint32_t dev_id, fal_fwd_cmd_t * cmd); - - HSL_LOCAL sw_error_t - isisc_ip_arp_guard_set(a_uint32_t dev_id, fal_port_t port_id, - fal_source_guard_mode_t mode); - - HSL_LOCAL sw_error_t - isisc_ip_arp_guard_get(a_uint32_t dev_id, fal_port_t port_id, - fal_source_guard_mode_t * mode); - - HSL_LOCAL sw_error_t - isisc_arp_unk_source_cmd_set(a_uint32_t dev_id, fal_fwd_cmd_t cmd); - - HSL_LOCAL sw_error_t - isisc_arp_unk_source_cmd_get(a_uint32_t dev_id, fal_fwd_cmd_t * cmd); - - HSL_LOCAL sw_error_t - isisc_ip_route_status_set(a_uint32_t dev_id, a_bool_t enable); - - HSL_LOCAL sw_error_t - isisc_ip_route_status_get(a_uint32_t dev_id, a_bool_t * enable); - - HSL_LOCAL sw_error_t - isisc_ip_intf_entry_del(a_uint32_t dev_id, a_uint32_t del_mode, - fal_intf_mac_entry_t * entry); - - HSL_LOCAL sw_error_t - isisc_ip_intf_entry_next(a_uint32_t dev_id, a_uint32_t next_mode, - fal_intf_mac_entry_t * entry); - - HSL_LOCAL sw_error_t - isisc_ip_age_time_set(a_uint32_t dev_id, a_uint32_t * time); - - HSL_LOCAL sw_error_t - isisc_ip_age_time_get(a_uint32_t dev_id, a_uint32_t * time); - - HSL_LOCAL sw_error_t - isisc_ip_wcmp_entry_set(a_uint32_t dev_id, a_uint32_t wcmp_id, fal_ip_wcmp_t * wcmp); - - HSL_LOCAL sw_error_t - isisc_ip_wcmp_entry_get(a_uint32_t dev_id, a_uint32_t wcmp_id, fal_ip_wcmp_t * wcmp); - - HSL_LOCAL sw_error_t - isisc_ip_wcmp_hash_mode_set(a_uint32_t dev_id, a_uint32_t hash_mode); - - HSL_LOCAL sw_error_t - isisc_ip_wcmp_hash_mode_get(a_uint32_t dev_id, a_uint32_t * hash_mode); - -#endif - -#ifdef __cplusplus -} -#endif /* __cplusplus */ -#endif /* _ISISC_IP_H_ */ diff --git a/feeds/ipq807x/qca-ssdk/src/include/hsl/isisc/isisc_leaky.h b/feeds/ipq807x/qca-ssdk/src/include/hsl/isisc/isisc_leaky.h deleted file mode 100755 index 5325cdd3d..000000000 --- a/feeds/ipq807x/qca-ssdk/src/include/hsl/isisc/isisc_leaky.h +++ /dev/null @@ -1,94 +0,0 @@ -/* - * Copyright (c) 2012, The Linux Foundation. All rights reserved. - * Permission to use, copy, modify, and/or distribute this software for - * any purpose with or without fee is hereby granted, provided that the - * above copyright notice and this permission notice appear in all copies. - * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES - * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR - * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES - * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN - * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT - * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. - */ - - -#ifndef _ISISC_LEAKY_H_ -#define _ISISC_LEAKY_H_ - -#ifdef __cplusplus -extern "C" { -#endif /* __cplusplus */ - -#include "fal/fal_leaky.h" - - sw_error_t isisc_leaky_init(a_uint32_t dev_id); - -#ifdef IN_LEAKY -#define ISISC_LEAKY_INIT(rv, dev_id) \ - { \ - rv = isisc_leaky_init(dev_id); \ - SW_RTN_ON_ERROR(rv); \ - } -#else -#define ISISC_LEAKY_INIT(rv, dev_id) -#endif - -#ifdef HSL_STANDALONG - - - HSL_LOCAL sw_error_t - isisc_uc_leaky_mode_set(a_uint32_t dev_id, - fal_leaky_ctrl_mode_t ctrl_mode); - - - HSL_LOCAL sw_error_t - isisc_uc_leaky_mode_get(a_uint32_t dev_id, - fal_leaky_ctrl_mode_t * ctrl_mode); - - - HSL_LOCAL sw_error_t - isisc_mc_leaky_mode_set(a_uint32_t dev_id, - fal_leaky_ctrl_mode_t ctrl_mode); - - - HSL_LOCAL sw_error_t - isisc_mc_leaky_mode_get(a_uint32_t dev_id, - fal_leaky_ctrl_mode_t * ctrl_mode); - - - HSL_LOCAL sw_error_t - isisc_port_arp_leaky_set(a_uint32_t dev_id, fal_port_t port_id, - a_bool_t enable); - - - HSL_LOCAL sw_error_t - isisc_port_arp_leaky_get(a_uint32_t dev_id, fal_port_t port_id, - a_bool_t * enable); - - - HSL_LOCAL sw_error_t - isisc_port_uc_leaky_set(a_uint32_t dev_id, fal_port_t port_id, - a_bool_t enable); - - - HSL_LOCAL sw_error_t - isisc_port_uc_leaky_get(a_uint32_t dev_id, fal_port_t port_id, - a_bool_t * enable); - - - HSL_LOCAL sw_error_t - isisc_port_mc_leaky_set(a_uint32_t dev_id, fal_port_t port_id, - a_bool_t enable); - - - HSL_LOCAL sw_error_t - isisc_port_mc_leaky_get(a_uint32_t dev_id, fal_port_t port_id, - a_bool_t * enable); -#endif - -#ifdef __cplusplus -} -#endif /* __cplusplus */ -#endif /* _ISISC_LEAKY_H_ */ - diff --git a/feeds/ipq807x/qca-ssdk/src/include/hsl/isisc/isisc_led.h b/feeds/ipq807x/qca-ssdk/src/include/hsl/isisc/isisc_led.h deleted file mode 100755 index 304763e0a..000000000 --- a/feeds/ipq807x/qca-ssdk/src/include/hsl/isisc/isisc_led.h +++ /dev/null @@ -1,57 +0,0 @@ -/* - * Copyright (c) 2012, The Linux Foundation. All rights reserved. - * Permission to use, copy, modify, and/or distribute this software for - * any purpose with or without fee is hereby granted, provided that the - * above copyright notice and this permission notice appear in all copies. - * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES - * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR - * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES - * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN - * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT - * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. - */ - - -#ifndef _ISISC_LED_H_ -#define _ISISC_LED_H_ - -#ifdef __cplusplus -extern "C" { -#endif /* __cplusplus */ - -#include "fal/fal_led.h" - - sw_error_t - isisc_led_init(a_uint32_t dev_id); - -#ifdef IN_LED -#define ISISC_LED_INIT(rv, dev_id) \ - { \ - rv = isisc_led_init(dev_id); \ - SW_RTN_ON_ERROR(rv); \ - } -#else -#define ISISC_LED_INIT(rv, dev_id) -#endif - -#ifdef HSL_STANDALONG - - - HSL_LOCAL sw_error_t - isisc_led_ctrl_pattern_set(a_uint32_t dev_id, led_pattern_group_t group, - led_pattern_id_t id, led_ctrl_pattern_t * pattern); - - - HSL_LOCAL sw_error_t - isisc_led_ctrl_pattern_get(a_uint32_t dev_id, led_pattern_group_t group, - led_pattern_id_t id, led_ctrl_pattern_t * pattern); - -#endif - -#ifdef __cplusplus -} -#endif /* __cplusplus */ - -#endif /* _ISISC_LED_H_ */ - diff --git a/feeds/ipq807x/qca-ssdk/src/include/hsl/isisc/isisc_mib.h b/feeds/ipq807x/qca-ssdk/src/include/hsl/isisc/isisc_mib.h deleted file mode 100755 index 3a1677dcd..000000000 --- a/feeds/ipq807x/qca-ssdk/src/include/hsl/isisc/isisc_mib.h +++ /dev/null @@ -1,69 +0,0 @@ -/* - * Copyright (c) 2012, The Linux Foundation. All rights reserved. - * Permission to use, copy, modify, and/or distribute this software for - * any purpose with or without fee is hereby granted, provided that the - * above copyright notice and this permission notice appear in all copies. - * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES - * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR - * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES - * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN - * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT - * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. - */ - - -#ifndef _ISISC_MIB_H_ -#define _ISISC_MIB_H_ - -#ifdef __cplusplus -extern "C" { -#endif /* __cplusplus */ - -#include "fal/fal_mib.h" - - sw_error_t - isisc_mib_init(a_uint32_t dev_id); - -#ifdef IN_MIB -#define ISISC_MIB_INIT(rv, dev_id) \ - { \ - rv = isisc_mib_init(dev_id); \ - SW_RTN_ON_ERROR(rv); \ - } -#else -#define ISISC_MIB_INIT(rv, dev_id) -#endif - -#ifdef HSL_STANDALONG - - HSL_LOCAL sw_error_t - isisc_get_mib_info(a_uint32_t dev_id, fal_port_t port_id, - fal_mib_info_t * mib_info ); - - - HSL_LOCAL sw_error_t - isisc_mib_status_set(a_uint32_t dev_id, a_bool_t enable); - - - HSL_LOCAL sw_error_t - isisc_mib_status_get(a_uint32_t dev_id, a_bool_t * enable); - - HSL_LOCAL sw_error_t - isisc_mib_port_flush_counters(a_uint32_t dev_id, fal_port_t port_id); - - HSL_LOCAL sw_error_t - isisc_mib_cpukeep_set(a_uint32_t dev_id, a_bool_t enable); - - - HSL_LOCAL sw_error_t - isisc_mib_cpukeep_get(a_uint32_t dev_id, a_bool_t * enable); - -#endif - -#ifdef __cplusplus -} -#endif /* __cplusplus */ - -#endif /* _ISISC_MIB_H_ */ - diff --git a/feeds/ipq807x/qca-ssdk/src/include/hsl/isisc/isisc_mirror.h b/feeds/ipq807x/qca-ssdk/src/include/hsl/isisc/isisc_mirror.h deleted file mode 100755 index 22e28c046..000000000 --- a/feeds/ipq807x/qca-ssdk/src/include/hsl/isisc/isisc_mirror.h +++ /dev/null @@ -1,73 +0,0 @@ -/* - * Copyright (c) 2012, The Linux Foundation. All rights reserved. - * Permission to use, copy, modify, and/or distribute this software for - * any purpose with or without fee is hereby granted, provided that the - * above copyright notice and this permission notice appear in all copies. - * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES - * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR - * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES - * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN - * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT - * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. - */ - - -#ifndef _ISISC_MIRROR_H_ -#define _ISISC_MIRROR_H_ - -#ifdef __cplusplus -extern "C" { -#endif /* __cplusplus */ - -#include "fal/fal_mirror.h" -#define MIRROR_ANALYZER_NONE 0xf - - sw_error_t isisc_mirr_init(a_uint32_t dev_id); - -#ifdef IN_MIRROR -#define ISISC_MIRR_INIT(rv, dev_id) \ - { \ - rv = isisc_mirr_init(dev_id); \ - SW_RTN_ON_ERROR(rv); \ - } -#else -#define ISISC_MIRR_INIT(rv, dev_id) -#endif - -#ifdef HSL_STANDALONG - - HSL_LOCAL sw_error_t - isisc_mirr_analysis_port_set(a_uint32_t dev_id, fal_port_t port_id); - - - HSL_LOCAL sw_error_t - isisc_mirr_analysis_port_get(a_uint32_t dev_id, fal_port_t * port_id); - - - HSL_LOCAL sw_error_t - isisc_mirr_port_in_set(a_uint32_t dev_id, fal_port_t port_id, - a_bool_t enable); - - - HSL_LOCAL sw_error_t - isisc_mirr_port_in_get(a_uint32_t dev_id, fal_port_t port_id, - a_bool_t * enable); - - - HSL_LOCAL sw_error_t - isisc_mirr_port_eg_set(a_uint32_t dev_id, fal_port_t port_id, - a_bool_t enable); - - - HSL_LOCAL sw_error_t - isisc_mirr_port_eg_get(a_uint32_t dev_id, fal_port_t port_id, - a_bool_t * enable); - -#endif - -#ifdef __cplusplus -} -#endif /* __cplusplus */ -#endif /* _ISISC_MIRROR_H_ */ - diff --git a/feeds/ipq807x/qca-ssdk/src/include/hsl/isisc/isisc_misc.h b/feeds/ipq807x/qca-ssdk/src/include/hsl/isisc/isisc_misc.h deleted file mode 100755 index 826105b1e..000000000 --- a/feeds/ipq807x/qca-ssdk/src/include/hsl/isisc/isisc_misc.h +++ /dev/null @@ -1,238 +0,0 @@ -/* - * Copyright (c) 2012, The Linux Foundation. All rights reserved. - * Permission to use, copy, modify, and/or distribute this software for - * any purpose with or without fee is hereby granted, provided that the - * above copyright notice and this permission notice appear in all copies. - * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES - * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR - * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES - * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN - * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT - * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. - */ - - -#ifndef _ISISC_MISC_H_ -#define _ISISC_MISC_H_ - -#ifdef __cplusplus -extern "C" { -#endif /* __cplusplus */ - -#include "fal/fal_misc.h" - - sw_error_t isisc_misc_init(a_uint32_t dev_id); - -#ifdef IN_MISC -#define ISISC_MISC_INIT(rv, dev_id) \ - { \ - rv = isisc_misc_init(dev_id); \ - SW_RTN_ON_ERROR(rv); \ - } -#else -#define ISISC_MISC_INIT(rv, dev_id) -#endif - -#ifdef HSL_STANDALONG - - - HSL_LOCAL sw_error_t - isisc_frame_max_size_set(a_uint32_t dev_id, a_uint32_t size); - - - HSL_LOCAL sw_error_t - isisc_frame_max_size_get(a_uint32_t dev_id, a_uint32_t * size); - - - HSL_LOCAL sw_error_t - isisc_port_unk_uc_filter_set(a_uint32_t dev_id, fal_port_t port_id, - a_bool_t enable); - - - HSL_LOCAL sw_error_t - isisc_port_unk_uc_filter_get(a_uint32_t dev_id, fal_port_t port_id, - a_bool_t * enable); - - - HSL_LOCAL sw_error_t - isisc_port_unk_mc_filter_set(a_uint32_t dev_id, fal_port_t port_id, - a_bool_t enable); - - - HSL_LOCAL sw_error_t - isisc_port_unk_mc_filter_get(a_uint32_t dev_id, fal_port_t port_id, - a_bool_t * enable); - - - HSL_LOCAL sw_error_t - isisc_port_bc_filter_set(a_uint32_t dev_id, fal_port_t port_id, - a_bool_t enable); - - - HSL_LOCAL sw_error_t - isisc_port_bc_filter_get(a_uint32_t dev_id, fal_port_t port_id, - a_bool_t * enable); - - - HSL_LOCAL sw_error_t - isisc_cpu_port_status_set(a_uint32_t dev_id, a_bool_t enable); - - - HSL_LOCAL sw_error_t - isisc_cpu_port_status_get(a_uint32_t dev_id, a_bool_t * enable); - - - HSL_LOCAL sw_error_t - isisc_pppoe_cmd_set(a_uint32_t dev_id, fal_fwd_cmd_t cmd); - - - HSL_LOCAL sw_error_t - isisc_pppoe_cmd_get(a_uint32_t dev_id, fal_fwd_cmd_t * cmd); - - - HSL_LOCAL sw_error_t - isisc_pppoe_status_set(a_uint32_t dev_id, a_bool_t enable); - - - HSL_LOCAL sw_error_t - isisc_pppoe_status_get(a_uint32_t dev_id, a_bool_t * enable); - - - HSL_LOCAL sw_error_t - isisc_port_dhcp_set(a_uint32_t dev_id, fal_port_t port_id, a_bool_t enable); - - - HSL_LOCAL sw_error_t - isisc_port_dhcp_get(a_uint32_t dev_id, fal_port_t port_id, a_bool_t * enable); - - - HSL_LOCAL sw_error_t - isisc_arp_cmd_set(a_uint32_t dev_id, fal_fwd_cmd_t cmd); - - - HSL_LOCAL sw_error_t - isisc_arp_cmd_get(a_uint32_t dev_id, fal_fwd_cmd_t * cmd); - - - HSL_LOCAL sw_error_t - isisc_eapol_cmd_set(a_uint32_t dev_id, fal_fwd_cmd_t cmd); - - - HSL_LOCAL sw_error_t - isisc_eapol_cmd_get(a_uint32_t dev_id, fal_fwd_cmd_t * cmd); - - - HSL_LOCAL sw_error_t - isisc_pppoe_session_table_add(a_uint32_t dev_id, fal_pppoe_session_t * session_tbl); - - - HSL_LOCAL sw_error_t - isisc_pppoe_session_table_del(a_uint32_t dev_id, fal_pppoe_session_t * session_tbl); - - - HSL_LOCAL sw_error_t - isisc_pppoe_session_table_get(a_uint32_t dev_id, fal_pppoe_session_t * session_tbl); - - - HSL_LOCAL sw_error_t - isisc_pppoe_session_id_set(a_uint32_t dev_id, a_uint32_t index, - a_uint32_t id); - - - HSL_LOCAL sw_error_t - isisc_pppoe_session_id_get(a_uint32_t dev_id, a_uint32_t index, - a_uint32_t * id); - - - HSL_LOCAL sw_error_t - isisc_eapol_status_set(a_uint32_t dev_id, a_uint32_t port_id, a_bool_t enable); - - HSL_LOCAL sw_error_t - isisc_eapol_status_get(a_uint32_t dev_id, a_uint32_t port_id, a_bool_t * enable); - - HSL_LOCAL sw_error_t - isisc_ripv1_status_set(a_uint32_t dev_id, a_bool_t enable); - - HSL_LOCAL sw_error_t - isisc_ripv1_status_get(a_uint32_t dev_id, a_bool_t * enable); - - - HSL_LOCAL sw_error_t - isisc_port_arp_req_status_set(a_uint32_t dev_id, fal_port_t port_id, a_bool_t enable); - - - HSL_LOCAL sw_error_t - isisc_port_arp_req_status_get(a_uint32_t dev_id, fal_port_t port_id, a_bool_t *enable); - - - HSL_LOCAL sw_error_t - isisc_port_arp_ack_status_set(a_uint32_t dev_id, fal_port_t port_id, a_bool_t enable); - - - HSL_LOCAL sw_error_t - isisc_port_arp_ack_status_get(a_uint32_t dev_id, fal_port_t port_id, a_bool_t *enable); - - - HSL_LOCAL sw_error_t - isisc_intr_mask_set(a_uint32_t dev_id, a_uint32_t intr_mask); - - - HSL_LOCAL sw_error_t - isisc_intr_mask_get(a_uint32_t dev_id, a_uint32_t * intr_mask); - - - HSL_LOCAL sw_error_t - isisc_intr_status_get(a_uint32_t dev_id, a_uint32_t * intr_status); - - - HSL_LOCAL sw_error_t - isisc_intr_status_clear(a_uint32_t dev_id, a_uint32_t intr_status); - - - HSL_LOCAL sw_error_t - isisc_intr_port_link_mask_set(a_uint32_t dev_id, a_uint32_t port_id, a_uint32_t intr_mask_flag); - - - HSL_LOCAL sw_error_t - isisc_intr_port_link_mask_get(a_uint32_t dev_id, a_uint32_t port_id, a_uint32_t * intr_mask_flag); - - - HSL_LOCAL sw_error_t - isisc_intr_port_link_status_get(a_uint32_t dev_id, a_uint32_t port_id, a_uint32_t * intr_mask_flag); - - HSL_LOCAL sw_error_t - isisc_intr_mask_mac_linkchg_set(a_uint32_t dev_id, a_uint32_t port_id, a_bool_t enable); - - - HSL_LOCAL sw_error_t - isisc_intr_mask_mac_linkchg_get(a_uint32_t dev_id, a_uint32_t port_id, a_bool_t * enable); - - HSL_LOCAL sw_error_t - isisc_intr_status_mac_linkchg_get(a_uint32_t dev_id, fal_pbmp_t *port_bitmap); - - HSL_LOCAL sw_error_t - isisc_cpu_vid_en_set(a_uint32_t dev_id, a_bool_t enable); - - - HSL_LOCAL sw_error_t - isisc_cpu_vid_en_get(a_uint32_t dev_id, a_bool_t * enable); - - HSL_LOCAL sw_error_t - isisc_rtd_pppoe_en_set(a_uint32_t dev_id, a_bool_t enable); - - - HSL_LOCAL sw_error_t - isisc_rtd_pppoe_en_get(a_uint32_t dev_id, a_bool_t * enable); - - HSL_LOCAL sw_error_t - isisc_intr_status_mac_linkchg_clear(a_uint32_t dev_id); - -#endif - -#ifdef __cplusplus -} -#endif /* __cplusplus */ - -#endif - diff --git a/feeds/ipq807x/qca-ssdk/src/include/hsl/isisc/isisc_nat.h b/feeds/ipq807x/qca-ssdk/src/include/hsl/isisc/isisc_nat.h deleted file mode 100755 index 7943ce9f5..000000000 --- a/feeds/ipq807x/qca-ssdk/src/include/hsl/isisc/isisc_nat.h +++ /dev/null @@ -1,153 +0,0 @@ -/* - * Copyright (c) 2012, The Linux Foundation. All rights reserved. - * Permission to use, copy, modify, and/or distribute this software for - * any purpose with or without fee is hereby granted, provided that the - * above copyright notice and this permission notice appear in all copies. - * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES - * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR - * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES - * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN - * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT - * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. - */ - - -#ifndef _ISISC_NAT_H_ -#define _ISISC_NAT_H_ - -#ifdef __cplusplus -extern "C" { -#endif /* __cplusplus */ - -#include "fal/fal_nat.h" - - sw_error_t isisc_nat_init(a_uint32_t dev_id); - - sw_error_t isisc_nat_reset(a_uint32_t dev_id); - -#ifdef IN_NAT -#define ISISC_NAT_INIT(rv, dev_id) \ - { \ - rv = isisc_nat_init(dev_id); \ - SW_RTN_ON_ERROR(rv); \ - } - -#define ISISC_NAT_RESET(rv, dev_id) \ - { \ - rv = isisc_nat_reset(dev_id); \ - SW_RTN_ON_ERROR(rv); \ - } -#else -#define ISISC_NAT_INIT(rv, dev_id) -#define ISISC_NAT_RESET(rv, dev_id) -#endif - -#ifdef HSL_STANDALONG - - HSL_LOCAL sw_error_t - isisc_napt_add(a_uint32_t dev_id, fal_napt_entry_t * napt_entry); - - HSL_LOCAL sw_error_t - isisc_nat_pub_addr_add(a_uint32_t dev_id, fal_nat_pub_addr_t * entry); - - HSL_LOCAL sw_error_t - isisc_napt_next(a_uint32_t dev_id, a_uint32_t next_mode, - fal_napt_entry_t * napt_entry); - - HSL_LOCAL sw_error_t - isisc_nat_prv_base_addr_set(a_uint32_t dev_id, fal_ip4_addr_t addr); - - HSL_LOCAL sw_error_t - isisc_napt_del(a_uint32_t dev_id, a_uint32_t del_mode, - fal_napt_entry_t * napt_entry); - - HSL_LOCAL sw_error_t - isisc_nat_del(a_uint32_t dev_id, a_uint32_t del_mode, - fal_nat_entry_t * nat_entry); - - HSL_LOCAL sw_error_t - isisc_nat_pub_addr_del(a_uint32_t dev_id, a_uint32_t del_mode, - fal_nat_pub_addr_t * entry); - - HSL_LOCAL sw_error_t - isisc_nat_add(a_uint32_t dev_id, fal_nat_entry_t * nat_entry); - - HSL_LOCAL sw_error_t - isisc_nat_get(a_uint32_t dev_id, a_uint32_t get_mode, - fal_nat_entry_t * nat_entry); - - HSL_LOCAL sw_error_t - isisc_nat_next(a_uint32_t dev_id, a_uint32_t next_mode, - fal_nat_entry_t * nat_entry); - - HSL_LOCAL sw_error_t - isisc_nat_counter_bind(a_uint32_t dev_id, a_uint32_t entry_id, - a_uint32_t cnt_id, a_bool_t enable); - - HSL_LOCAL sw_error_t - isisc_napt_get(a_uint32_t dev_id, a_uint32_t get_mode, - fal_napt_entry_t * napt_entry); - - HSL_LOCAL sw_error_t - isisc_napt_counter_bind(a_uint32_t dev_id, a_uint32_t entry_id, - a_uint32_t cnt_id, a_bool_t enable); - - HSL_LOCAL sw_error_t - isisc_nat_status_set(a_uint32_t dev_id, a_bool_t enable); - - HSL_LOCAL sw_error_t - isisc_nat_status_get(a_uint32_t dev_id, a_bool_t * enable); - - HSL_LOCAL sw_error_t - isisc_nat_hash_mode_set(a_uint32_t dev_id, a_uint32_t mode); - - HSL_LOCAL sw_error_t - isisc_nat_hash_mode_get(a_uint32_t dev_id, a_uint32_t * mode); - - HSL_LOCAL sw_error_t - isisc_napt_status_set(a_uint32_t dev_id, a_bool_t enable); - - HSL_LOCAL sw_error_t - isisc_napt_status_get(a_uint32_t dev_id, a_bool_t * enable); - - HSL_LOCAL sw_error_t - isisc_napt_mode_set(a_uint32_t dev_id, fal_napt_mode_t mode); - - HSL_LOCAL sw_error_t - isisc_napt_mode_get(a_uint32_t dev_id, fal_napt_mode_t * mode); - - HSL_LOCAL sw_error_t - isisc_nat_prv_base_addr_get(a_uint32_t dev_id, fal_ip4_addr_t * addr); - - HSL_LOCAL sw_error_t - isisc_nat_prv_base_mask_set(a_uint32_t dev_id, fal_ip4_addr_t addr); - - HSL_LOCAL sw_error_t - isisc_nat_prv_base_mask_get(a_uint32_t dev_id, fal_ip4_addr_t * addr); - - HSL_LOCAL sw_error_t - isisc_nat_pub_addr_next(a_uint32_t dev_id, a_uint32_t next_mode, - fal_nat_pub_addr_t * entry); - - HSL_LOCAL sw_error_t - isisc_nat_unk_session_cmd_set(a_uint32_t dev_id, fal_fwd_cmd_t cmd); - - HSL_LOCAL sw_error_t - isisc_nat_unk_session_cmd_get(a_uint32_t dev_id, fal_fwd_cmd_t * cmd); - - HSL_LOCAL sw_error_t - isisc_nat_psr_prv_base_addr_set(a_uint32_t dev_id, fal_ip4_addr_t addr); - - HSL_LOCAL sw_error_t - isisc_nat_psr_prv_base_addr_get(a_uint32_t dev_id, fal_ip4_addr_t * addr); - - HSL_LOCAL sw_error_t - isisc_nat_global_set(a_uint32_t dev_id, a_bool_t enable); - -#endif - -#ifdef __cplusplus -} -#endif /* __cplusplus */ -#endif /* _ISISC_NAT_H_ */ diff --git a/feeds/ipq807x/qca-ssdk/src/include/hsl/isisc/isisc_nat_helper.h b/feeds/ipq807x/qca-ssdk/src/include/hsl/isisc/isisc_nat_helper.h deleted file mode 100755 index e7ff032f5..000000000 --- a/feeds/ipq807x/qca-ssdk/src/include/hsl/isisc/isisc_nat_helper.h +++ /dev/null @@ -1,50 +0,0 @@ -/* - * Copyright (c) 2012, The Linux Foundation. All rights reserved. - * Permission to use, copy, modify, and/or distribute this software for - * any purpose with or without fee is hereby granted, provided that the - * above copyright notice and this permission notice appear in all copies. - * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES - * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR - * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES - * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN - * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT - * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. - */ - - -#ifndef _ISISC_NAT_HELPER_H_ -#define _ISISC_NAT_HELPER_H_ - -#ifdef __cplusplus -extern "C" { -#endif /* __cplusplus */ - -#include "fal/fal_nat.h" - - sw_error_t nat_helper_init(a_uint32_t dev_id, a_uint32_t portbmp); - - sw_error_t nat_helper_cleanup(a_uint32_t dev_id); - -#ifdef IN_NAT_HELPER -#define ISISC_NAT_HELPER_INIT(rv, dev_id, portbmp) \ - { \ - rv = nat_helper_init(dev_id, portbmp); \ - SW_RTN_ON_ERROR(rv); \ - } - -#define ISISC_NAT_HELPER_CLEANUP(rv, dev_id) \ - { \ - rv = nat_helper_cleanup(dev_id); \ - SW_RTN_ON_ERROR(rv); \ - } -#else -#define ISISC_NAT_HELPER_INIT(rv, dev_id, portbmp) -#define ISISC_NAT_HELPER_CLEANUP(rv, dev_id) -#endif - - -#ifdef __cplusplus -} -#endif /* __cplusplus */ -#endif /* _ISISC_NAT_HELPER_H_ */ diff --git a/feeds/ipq807x/qca-ssdk/src/include/hsl/isisc/isisc_port_ctrl.h b/feeds/ipq807x/qca-ssdk/src/include/hsl/isisc/isisc_port_ctrl.h deleted file mode 100755 index 19fc0875e..000000000 --- a/feeds/ipq807x/qca-ssdk/src/include/hsl/isisc/isisc_port_ctrl.h +++ /dev/null @@ -1,226 +0,0 @@ -/* - * Copyright (c) 2012, The Linux Foundation. All rights reserved. - * Permission to use, copy, modify, and/or distribute this software for - * any purpose with or without fee is hereby granted, provided that the - * above copyright notice and this permission notice appear in all copies. - * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES - * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR - * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES - * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN - * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT - * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. - */ - - -#ifndef _ISISC_PORT_CTRL_H_ -#define _ISISC_PORT_CTRL_H_ - -#ifdef __cplusplus -extern "C" { -#endif /* __cplusplus */ - -#include "fal/fal_port_ctrl.h" - - sw_error_t isisc_port_ctrl_init(a_uint32_t dev_id); - -#ifdef IN_PORTCONTROL -#define ISISC_PORT_CTRL_INIT(rv, dev_id) \ - { \ - rv = isisc_port_ctrl_init(dev_id); \ - SW_RTN_ON_ERROR(rv); \ - } -#else -#define ISISC_PORT_CTRL_INIT(rv, dev_id) -#endif - -#ifdef HSL_STANDALONG - - - HSL_LOCAL sw_error_t - isisc_port_duplex_set(a_uint32_t dev_id, fal_port_t port_id, - fal_port_duplex_t duplex); - - - HSL_LOCAL sw_error_t - isisc_port_duplex_get(a_uint32_t dev_id, fal_port_t port_id, - fal_port_duplex_t * pduplex); - - - HSL_LOCAL sw_error_t - isisc_port_speed_set(a_uint32_t dev_id, fal_port_t port_id, - fal_port_speed_t speed); - - - HSL_LOCAL sw_error_t - isisc_port_speed_get(a_uint32_t dev_id, fal_port_t port_id, - fal_port_speed_t * pspeed); - - - HSL_LOCAL sw_error_t - isisc_port_autoneg_status_get(a_uint32_t dev_id, fal_port_t port_id, - a_bool_t * status); - - - HSL_LOCAL sw_error_t - isisc_port_autoneg_enable(a_uint32_t dev_id, fal_port_t port_id); - - - HSL_LOCAL sw_error_t - isisc_port_autoneg_restart(a_uint32_t dev_id, fal_port_t port_id); - - - HSL_LOCAL sw_error_t - isisc_port_autoneg_adv_set(a_uint32_t dev_id, fal_port_t port_id, - a_uint32_t autoadv); - - - HSL_LOCAL sw_error_t - isisc_port_autoneg_adv_get(a_uint32_t dev_id, fal_port_t port_id, - a_uint32_t * autoadv); - - - HSL_LOCAL sw_error_t - isisc_port_flowctrl_set(a_uint32_t dev_id, fal_port_t port_id, - a_bool_t enable); - - - HSL_LOCAL sw_error_t - isisc_port_flowctrl_get(a_uint32_t dev_id, fal_port_t port_id, - a_bool_t * enable); - - - HSL_LOCAL sw_error_t - isisc_port_flowctrl_forcemode_set(a_uint32_t dev_id, - fal_port_t port_id, a_bool_t enable); - - - HSL_LOCAL sw_error_t - isisc_port_flowctrl_forcemode_get(a_uint32_t dev_id, - fal_port_t port_id, - a_bool_t * enable); - - - HSL_LOCAL sw_error_t - isisc_port_powersave_set(a_uint32_t dev_id, fal_port_t port_id, a_bool_t enable); - - - HSL_LOCAL sw_error_t - isisc_port_powersave_get(a_uint32_t dev_id, fal_port_t port_id, a_bool_t *enable); - - - HSL_LOCAL sw_error_t - isisc_port_hibernate_set(a_uint32_t dev_id, fal_port_t port_id, a_bool_t enable); - - - HSL_LOCAL sw_error_t - isisc_port_hibernate_get(a_uint32_t dev_id, fal_port_t port_id, a_bool_t *enable); - - - HSL_LOCAL sw_error_t - isisc_port_cdt(a_uint32_t dev_id, fal_port_t port_id, a_uint32_t mdi_pair, - fal_cable_status_t *cable_status, a_uint32_t *cable_len); - - - HSL_LOCAL sw_error_t - isisc_port_rxhdr_mode_set(a_uint32_t dev_id, fal_port_t port_id, - fal_port_header_mode_t mode); - - - HSL_LOCAL sw_error_t - isisc_port_rxhdr_mode_get(a_uint32_t dev_id, fal_port_t port_id, - fal_port_header_mode_t * mode); - - - HSL_LOCAL sw_error_t - isisc_port_txhdr_mode_set(a_uint32_t dev_id, fal_port_t port_id, - fal_port_header_mode_t mode); - - - HSL_LOCAL sw_error_t - isisc_port_txhdr_mode_get(a_uint32_t dev_id, fal_port_t port_id, - fal_port_header_mode_t * mode); - - - HSL_LOCAL sw_error_t - isisc_header_type_set(a_uint32_t dev_id, a_bool_t enable, a_uint32_t type); - - - HSL_LOCAL sw_error_t - isisc_header_type_get(a_uint32_t dev_id, a_bool_t * enable, a_uint32_t * type); - - - HSL_LOCAL sw_error_t - isisc_port_txmac_status_set(a_uint32_t dev_id, fal_port_t port_id, a_bool_t enable); - - - HSL_LOCAL sw_error_t - isisc_port_txmac_status_get(a_uint32_t dev_id, fal_port_t port_id, a_bool_t * enable); - - - HSL_LOCAL sw_error_t - isisc_port_rxmac_status_set(a_uint32_t dev_id, fal_port_t port_id, a_bool_t enable); - - - HSL_LOCAL sw_error_t - isisc_port_rxmac_status_get(a_uint32_t dev_id, fal_port_t port_id, a_bool_t * enable); - - - HSL_LOCAL sw_error_t - isisc_port_txfc_status_set(a_uint32_t dev_id, fal_port_t port_id, a_bool_t enable); - - - HSL_LOCAL sw_error_t - isisc_port_txfc_status_get(a_uint32_t dev_id, fal_port_t port_id, a_bool_t * enable); - - - HSL_LOCAL sw_error_t - isisc_port_rxfc_status_set(a_uint32_t dev_id, fal_port_t port_id, a_bool_t enable); - - - HSL_LOCAL sw_error_t - isisc_port_rxfc_status_get(a_uint32_t dev_id, fal_port_t port_id, a_bool_t * enable); - - - HSL_LOCAL sw_error_t - isisc_port_bp_status_set(a_uint32_t dev_id, fal_port_t port_id, a_bool_t enable); - - - HSL_LOCAL sw_error_t - isisc_port_bp_status_get(a_uint32_t dev_id, fal_port_t port_id, a_bool_t * enable); - - - HSL_LOCAL sw_error_t - isisc_port_link_forcemode_set(a_uint32_t dev_id, fal_port_t port_id, a_bool_t enable); - - - HSL_LOCAL sw_error_t - isisc_port_link_forcemode_get(a_uint32_t dev_id, fal_port_t port_id, a_bool_t * enable); - - - HSL_LOCAL sw_error_t - isisc_port_link_status_get(a_uint32_t dev_id, fal_port_t port_id, a_bool_t * status); - - HSL_LOCAL sw_error_t - isisc_ports_link_status_get(a_uint32_t dev_id, a_uint32_t * status); - - HSL_LOCAL sw_error_t - isisc_port_mac_loopback_set(a_uint32_t dev_id, fal_port_t port_id, a_bool_t enable); - - - HSL_LOCAL sw_error_t - isisc_port_mac_loopback_get(a_uint32_t dev_id, fal_port_t port_id, a_bool_t * enable); - - HSL_LOCAL sw_error_t - isisc_port_8023az_set (a_uint32_t dev_id, fal_port_t port_id, a_bool_t enable); - - HSL_LOCAL sw_error_t - isisc_port_8023az_get (a_uint32_t dev_id, fal_port_t port_id, a_bool_t *enable); - -#endif - -#ifdef __cplusplus -} -#endif /* __cplusplus */ -#endif /* _ISISC_PORT_CTRL_H_ */ - diff --git a/feeds/ipq807x/qca-ssdk/src/include/hsl/isisc/isisc_portvlan.h b/feeds/ipq807x/qca-ssdk/src/include/hsl/isisc/isisc_portvlan.h deleted file mode 100755 index 248df0b30..000000000 --- a/feeds/ipq807x/qca-ssdk/src/include/hsl/isisc/isisc_portvlan.h +++ /dev/null @@ -1,228 +0,0 @@ -/* - * Copyright (c) 2012, The Linux Foundation. All rights reserved. - * Permission to use, copy, modify, and/or distribute this software for - * any purpose with or without fee is hereby granted, provided that the - * above copyright notice and this permission notice appear in all copies. - * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES - * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR - * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES - * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN - * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT - * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. - */ - - -#ifndef _ISISC_PORTVLAN_H_ -#define _ISISC_PORTVLAN_H_ - -#ifdef __cplusplus -extern "C" { -#endif /* __cplusplus */ - -#include "fal/fal_portvlan.h" - - sw_error_t isisc_portvlan_init(a_uint32_t dev_id); - -#ifdef IN_PORTVLAN -#define ISISC_PORTVLAN_INIT(rv, dev_id) \ - { \ - rv = isisc_portvlan_init(dev_id); \ - SW_RTN_ON_ERROR(rv); \ - } -#else -#define ISISC_PORTVLAN_INIT(rv, dev_id) -#endif - -#ifdef HSL_STANDALONG - - - HSL_LOCAL sw_error_t - isisc_port_1qmode_set(a_uint32_t dev_id, fal_port_t port_id, - fal_pt_1qmode_t port_1qmode); - - - HSL_LOCAL sw_error_t - isisc_port_1qmode_get(a_uint32_t dev_id, fal_port_t port_id, - fal_pt_1qmode_t * pport_1qmode); - - - HSL_LOCAL sw_error_t - isisc_port_egvlanmode_set(a_uint32_t dev_id, fal_port_t port_id, - fal_pt_1q_egmode_t port_egvlanmode); - - - HSL_LOCAL sw_error_t - isisc_port_egvlanmode_get(a_uint32_t dev_id, fal_port_t port_id, - fal_pt_1q_egmode_t * pport_egvlanmode); - - - HSL_LOCAL sw_error_t - isisc_portvlan_member_add(a_uint32_t dev_id, fal_port_t port_id, - a_uint32_t mem_port_id); - - - HSL_LOCAL sw_error_t - isisc_portvlan_member_del(a_uint32_t dev_id, fal_port_t port_id, - a_uint32_t mem_port_id); - - - HSL_LOCAL sw_error_t - isisc_portvlan_member_update(a_uint32_t dev_id, fal_port_t port_id, - fal_pbmp_t mem_port_map); - - - HSL_LOCAL sw_error_t - isisc_portvlan_member_get(a_uint32_t dev_id, fal_port_t port_id, - fal_pbmp_t * mem_port_map); - - - HSL_LOCAL sw_error_t - isisc_port_force_default_vid_set(a_uint32_t dev_id, fal_port_t port_id, - a_bool_t enable); - - - HSL_LOCAL sw_error_t - isisc_port_force_default_vid_get(a_uint32_t dev_id, fal_port_t port_id, a_bool_t * enable); - - - HSL_LOCAL sw_error_t - isisc_port_force_portvlan_set(a_uint32_t dev_id, fal_port_t port_id, - a_bool_t enable); - - - HSL_LOCAL sw_error_t - isisc_port_force_portvlan_get(a_uint32_t dev_id, fal_port_t port_id, a_bool_t * enable); - - - HSL_LOCAL sw_error_t - isisc_nestvlan_tpid_set(a_uint32_t dev_id, a_uint32_t tpid); - - - HSL_LOCAL sw_error_t - isisc_nestvlan_tpid_get(a_uint32_t dev_id, a_uint32_t * tpid); - - - HSL_LOCAL sw_error_t - isisc_port_invlan_mode_set(a_uint32_t dev_id, fal_port_t port_id, - fal_pt_invlan_mode_t mode); - - - HSL_LOCAL sw_error_t - isisc_port_invlan_mode_get(a_uint32_t dev_id, fal_port_t port_id, - fal_pt_invlan_mode_t * mode); - - - HSL_LOCAL sw_error_t - isisc_port_tls_set(a_uint32_t dev_id, fal_port_t port_id, - a_bool_t enable); - - - HSL_LOCAL sw_error_t - isisc_port_tls_get(a_uint32_t dev_id, fal_port_t port_id, - a_bool_t * enable); - - - HSL_LOCAL sw_error_t - isisc_port_pri_propagation_set(a_uint32_t dev_id, fal_port_t port_id, - a_bool_t enable); - - - HSL_LOCAL sw_error_t - isisc_port_pri_propagation_get(a_uint32_t dev_id, fal_port_t port_id, - a_bool_t * enable); - - - HSL_LOCAL sw_error_t - isisc_port_default_svid_set(a_uint32_t dev_id, fal_port_t port_id, - a_uint32_t vid); - - - HSL_LOCAL sw_error_t - isisc_port_default_svid_get(a_uint32_t dev_id, fal_port_t port_id, - a_uint32_t * vid); - - HSL_LOCAL sw_error_t - isisc_port_default_cvid_set(a_uint32_t dev_id, fal_port_t port_id, - a_uint32_t vid); - - - HSL_LOCAL sw_error_t - isisc_port_default_cvid_get(a_uint32_t dev_id, fal_port_t port_id, - a_uint32_t * vid); - - - HSL_LOCAL sw_error_t - isisc_port_vlan_propagation_set(a_uint32_t dev_id, fal_port_t port_id, - fal_vlan_propagation_mode_t mode); - - - HSL_LOCAL sw_error_t - isisc_port_vlan_propagation_get(a_uint32_t dev_id, fal_port_t port_id, - fal_vlan_propagation_mode_t * mode); - - - HSL_LOCAL sw_error_t - isisc_port_vlan_trans_add(a_uint32_t dev_id, fal_port_t port_id, fal_vlan_trans_entry_t *entry); - - - HSL_LOCAL sw_error_t - isisc_port_vlan_trans_del(a_uint32_t dev_id, fal_port_t port_id, fal_vlan_trans_entry_t *entry); - - - HSL_LOCAL sw_error_t - isisc_port_vlan_trans_get(a_uint32_t dev_id, fal_port_t port_id, fal_vlan_trans_entry_t *entry); - - - HSL_LOCAL sw_error_t - isisc_qinq_mode_set(a_uint32_t dev_id, fal_qinq_mode_t mode); - - - HSL_LOCAL sw_error_t - isisc_qinq_mode_get(a_uint32_t dev_id, fal_qinq_mode_t * mode); - - - HSL_LOCAL sw_error_t - isisc_port_qinq_role_set(a_uint32_t dev_id, fal_port_t port_id, fal_qinq_port_role_t role); - - - HSL_LOCAL sw_error_t - isisc_port_qinq_role_get(a_uint32_t dev_id, fal_port_t port_id, fal_qinq_port_role_t * role); - - - HSL_LOCAL sw_error_t - isisc_port_vlan_trans_iterate(a_uint32_t dev_id, fal_port_t port_id, - a_uint32_t * iterator, fal_vlan_trans_entry_t * entry); - - - HSL_LOCAL sw_error_t - isisc_port_mac_vlan_xlt_set(a_uint32_t dev_id, fal_port_t port_id, - a_bool_t enable); - - - HSL_LOCAL sw_error_t - isisc_port_mac_vlan_xlt_get(a_uint32_t dev_id, fal_port_t port_id, - a_bool_t * enable); - - HSL_LOCAL sw_error_t - isisc_netisolate_set(a_uint32_t dev_id, a_bool_t enable); - - HSL_LOCAL sw_error_t - isisc_netisolate_get(a_uint32_t dev_id, a_bool_t * enable); - - HSL_LOCAL sw_error_t - isisc_eg_trans_filter_bypass_en_set(a_uint32_t dev_id, a_bool_t enable); - - HSL_LOCAL sw_error_t - isisc_eg_trans_filter_bypass_en_get(a_uint32_t dev_id, a_bool_t * enable); - - HSL_LOCAL sw_error_t - isisc_port_route_defv_set(a_uint32_t dev_id, fal_port_t port_id); - -#endif - -#ifdef __cplusplus -} -#endif /* __cplusplus */ -#endif /* _ISISC_PORTVLAN_H */ - diff --git a/feeds/ipq807x/qca-ssdk/src/include/hsl/isisc/isisc_qos.h b/feeds/ipq807x/qca-ssdk/src/include/hsl/isisc/isisc_qos.h deleted file mode 100755 index e4d932361..000000000 --- a/feeds/ipq807x/qca-ssdk/src/include/hsl/isisc/isisc_qos.h +++ /dev/null @@ -1,180 +0,0 @@ -/* - * Copyright (c) 2012, The Linux Foundation. All rights reserved. - * Permission to use, copy, modify, and/or distribute this software for - * any purpose with or without fee is hereby granted, provided that the - * above copyright notice and this permission notice appear in all copies. - * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES - * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR - * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES - * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN - * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT - * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. - */ - - -#ifndef _ISISC_QOS_H_ -#define _ISISC_QOS_H_ - -#ifdef __cplusplus -extern "C" { -#endif /* __cplusplus */ - -#include "fal/fal_qos.h" - - sw_error_t isisc_qos_init(a_uint32_t dev_id); - -#ifdef IN_QOS -#define ISISC_QOS_INIT(rv, dev_id) \ - { \ - rv = isisc_qos_init(dev_id); \ - SW_RTN_ON_ERROR(rv); \ - } -#else -#define ISISC_QOS_INIT(rv, dev_id) -#endif - -#ifdef HSL_STANDALONG - - - HSL_LOCAL sw_error_t - isisc_qos_queue_tx_buf_status_set(a_uint32_t dev_id, - fal_port_t port_id, a_bool_t enable); - - - HSL_LOCAL sw_error_t - isisc_qos_queue_tx_buf_status_get(a_uint32_t dev_id, - fal_port_t port_id, - a_bool_t * enable); - - HSL_LOCAL sw_error_t - isisc_qos_port_tx_buf_status_set(a_uint32_t dev_id, fal_port_t port_id, - a_bool_t enable); - - - HSL_LOCAL sw_error_t - isisc_qos_port_tx_buf_status_get(a_uint32_t dev_id, fal_port_t port_id, - a_bool_t * enable); - - HSL_LOCAL sw_error_t - isisc_qos_port_red_en_set(a_uint32_t dev_id, fal_port_t port_id, - a_bool_t enable); - - HSL_LOCAL sw_error_t - isisc_qos_port_red_en_get(a_uint32_t dev_id, fal_port_t port_id, - a_bool_t* enable); - - - HSL_LOCAL sw_error_t - isisc_qos_queue_tx_buf_nr_set(a_uint32_t dev_id, fal_port_t port_id, - fal_queue_t queue_id, - a_uint32_t * number); - - - HSL_LOCAL sw_error_t - isisc_qos_queue_tx_buf_nr_get(a_uint32_t dev_id, fal_port_t port_id, - fal_queue_t queue_id, - a_uint32_t * number); - - - HSL_LOCAL sw_error_t - isisc_qos_port_tx_buf_nr_set(a_uint32_t dev_id, fal_port_t port_id, - a_uint32_t * number); - - - HSL_LOCAL sw_error_t - isisc_qos_port_tx_buf_nr_get(a_uint32_t dev_id, fal_port_t port_id, - a_uint32_t * number); - - - HSL_LOCAL sw_error_t - isisc_qos_port_rx_buf_nr_set(a_uint32_t dev_id, fal_port_t port_id, - a_uint32_t * number); - - - HSL_LOCAL sw_error_t - isisc_qos_port_rx_buf_nr_get(a_uint32_t dev_id, fal_port_t port_id, - a_uint32_t * number); - - - HSL_LOCAL sw_error_t - isisc_qos_port_mode_set(a_uint32_t dev_id, fal_port_t port_id, - fal_qos_mode_t mode, a_bool_t enable); - - - HSL_LOCAL sw_error_t - isisc_qos_port_mode_get(a_uint32_t dev_id, fal_port_t port_id, - fal_qos_mode_t mode, a_bool_t * enable); - - - HSL_LOCAL sw_error_t - isisc_qos_port_mode_pri_set(a_uint32_t dev_id, fal_port_t port_id, - fal_qos_mode_t mode, a_uint32_t pri); - - - HSL_LOCAL sw_error_t - isisc_qos_port_mode_pri_get(a_uint32_t dev_id, fal_port_t port_id, - fal_qos_mode_t mode, a_uint32_t * pri); - - - HSL_LOCAL sw_error_t - isisc_qos_port_sch_mode_set(a_uint32_t dev_id, a_uint32_t port_id, - fal_sch_mode_t mode, const a_uint32_t weight[]); - - - HSL_LOCAL sw_error_t - isisc_qos_port_sch_mode_get(a_uint32_t dev_id, a_uint32_t port_id, - fal_sch_mode_t * mode, a_uint32_t weight[]); - - HSL_LOCAL sw_error_t - isisc_qos_port_default_spri_set(a_uint32_t dev_id, fal_port_t port_id, - a_uint32_t spri); - - - HSL_LOCAL sw_error_t - isisc_qos_port_default_spri_get(a_uint32_t dev_id, fal_port_t port_id, - a_uint32_t * spri); - - - HSL_LOCAL sw_error_t - isisc_qos_port_default_cpri_set(a_uint32_t dev_id, fal_port_t port_id, - a_uint32_t cpri); - - - HSL_LOCAL sw_error_t - isisc_qos_port_default_cpri_get(a_uint32_t dev_id, fal_port_t port_id, - a_uint32_t * cpri); - - sw_error_t - isisc_qos_port_force_spri_status_set(a_uint32_t dev_id, fal_port_t port_id, - a_bool_t enable); - - sw_error_t - isisc_qos_port_force_spri_status_get(a_uint32_t dev_id, fal_port_t port_id, - a_bool_t* enable); - - sw_error_t - isisc_qos_port_force_cpri_status_set(a_uint32_t dev_id, fal_port_t port_id, - a_bool_t enable); - - sw_error_t - isisc_qos_port_force_cpri_status_get(a_uint32_t dev_id, fal_port_t port_id, - a_bool_t* enable); - - HSL_LOCAL sw_error_t - isisc_qos_queue_remark_table_set(a_uint32_t dev_id, fal_port_t port_id, - fal_queue_t queue_id, a_uint32_t tbl_id, a_bool_t enable); - - - HSL_LOCAL sw_error_t - isisc_qos_queue_remark_table_get(a_uint32_t dev_id, fal_port_t port_id, - fal_queue_t queue_id, a_uint32_t * tbl_id, a_bool_t * enable); - - -#endif - -#ifdef __cplusplus -} -#endif /* __cplusplus */ -#endif /* _ISISC_QOS_H_ */ - diff --git a/feeds/ipq807x/qca-ssdk/src/include/hsl/isisc/isisc_rate.h b/feeds/ipq807x/qca-ssdk/src/include/hsl/isisc/isisc_rate.h deleted file mode 100755 index 4b4f48a03..000000000 --- a/feeds/ipq807x/qca-ssdk/src/include/hsl/isisc/isisc_rate.h +++ /dev/null @@ -1,96 +0,0 @@ -/* - * Copyright (c) 2012, The Linux Foundation. All rights reserved. - * Permission to use, copy, modify, and/or distribute this software for - * any purpose with or without fee is hereby granted, provided that the - * above copyright notice and this permission notice appear in all copies. - * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES - * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR - * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES - * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN - * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT - * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. - */ - - -#ifndef _ISISC_RATE_H_ -#define _ISISC_RATE_H_ - -#ifdef __cplusplus -extern "C" { -#endif /* __cplusplus */ - -#include "fal/fal_rate.h" - - sw_error_t isisc_rate_init(a_uint32_t dev_id); - -#ifdef IN_RATE -#define ISISC_RATE_INIT(rv, dev_id) \ - { \ - rv = isisc_rate_init(dev_id); \ - SW_RTN_ON_ERROR(rv); \ - } -#else -#define ISISC_RATE_INIT(rv, dev_id) -#endif - -#ifdef HSL_STANDALONG - - HSL_LOCAL sw_error_t - isisc_rate_port_policer_set(a_uint32_t dev_id, fal_port_t port_id, - fal_port_policer_t * policer); - - HSL_LOCAL sw_error_t - isisc_rate_port_policer_get(a_uint32_t dev_id, fal_port_t port_id, - fal_port_policer_t * policer); - - HSL_LOCAL sw_error_t - isisc_rate_port_shaper_set(a_uint32_t dev_id, fal_port_t port_id, - a_bool_t enable, - fal_egress_shaper_t * shaper); - - HSL_LOCAL sw_error_t - isisc_rate_port_shaper_get(a_uint32_t dev_id, fal_port_t port_id, - a_bool_t * enable, - fal_egress_shaper_t * shaper); - - HSL_LOCAL sw_error_t - isisc_rate_queue_shaper_set(a_uint32_t dev_id, fal_port_t port_id, - fal_queue_t queue_id, a_bool_t enable, - fal_egress_shaper_t * shaper); - - HSL_LOCAL sw_error_t - isisc_rate_queue_shaper_get(a_uint32_t dev_id, fal_port_t port_id, - fal_queue_t queue_id, a_bool_t * enable, - fal_egress_shaper_t * shaper); - - HSL_LOCAL sw_error_t - isisc_rate_acl_policer_set(a_uint32_t dev_id, a_uint32_t policer_id, - fal_acl_policer_t * policer); - - HSL_LOCAL sw_error_t - isisc_rate_acl_policer_get(a_uint32_t dev_id, a_uint32_t policer_id, - fal_acl_policer_t * policer); - - HSL_LOCAL sw_error_t - isisc_rate_port_add_rate_byte_set(a_uint32_t dev_id, fal_port_t port_id, - a_uint32_t number); - - HSL_LOCAL sw_error_t - isisc_rate_port_add_rate_byte_get(a_uint32_t dev_id, fal_port_t port_id, - a_uint32_t *number); - - HSL_LOCAL sw_error_t - isisc_rate_port_gol_flow_en_set(a_uint32_t dev_id, fal_port_t port_id, - a_bool_t enable); - - HSL_LOCAL sw_error_t - isisc_rate_port_gol_flow_en_get(a_uint32_t dev_id, fal_port_t port_id, - a_bool_t* enable); -#endif - -#ifdef __cplusplus -} -#endif /* __cplusplus */ -#endif /* _ISISC_RATE_H_ */ - diff --git a/feeds/ipq807x/qca-ssdk/src/include/hsl/isisc/isisc_reg.h b/feeds/ipq807x/qca-ssdk/src/include/hsl/isisc/isisc_reg.h deleted file mode 100755 index 1eb3d1b5f..000000000 --- a/feeds/ipq807x/qca-ssdk/src/include/hsl/isisc/isisc_reg.h +++ /dev/null @@ -1,5478 +0,0 @@ -/* - * Copyright (c) 2012, The Linux Foundation. All rights reserved. - * Permission to use, copy, modify, and/or distribute this software for - * any purpose with or without fee is hereby granted, provided that the - * above copyright notice and this permission notice appear in all copies. - * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES - * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR - * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES - * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN - * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT - * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. - */ - - - -#ifndef _ISISC_REG_H_ -#define _ISISC_REG_H_ - -#ifdef __cplusplus -extern "C" { -#endif /* __cplusplus */ - -#define S16E_DEVICE_ID 0x11 -#define S17C_DEVICE_ID 0x13 /* TBD */ -#define S17_REVISION_A 0x01 - -#define MAX_ENTRY_LEN 128 - -#define HSL_RW 1 -#define HSL_RO 0 - - - /* ISIS Mask Control Register */ -#define MASK_CTL -#define MASK_CTL_ID 0 -#define MASK_CTL_OFFSET 0x0000 -#define MASK_CTL_E_LENGTH 4 -#define MASK_CTL_E_OFFSET 0 -#define MASK_CTL_NR_E 1 - -#define SOFT_RST -#define MASK_CTL_SOFT_RST_BOFFSET 31 -#define MASK_CTL_SOFT_RST_BLEN 1 -#define MASK_CTL_SOFT_RST_FLAG HSL_RW - -#define LOAD_EEPROM -#define MASK_CTL_LOAD_EEPROM_BOFFSET 16 -#define MASK_CTL_LOAD_EEPROM_BLEN 1 -#define MASK_CTL_LOAD_EEPROM_FLAG HSL_RW - -#define DEVICE_ID -#define MASK_CTL_DEVICE_ID_BOFFSET 8 -#define MASK_CTL_DEVICE_ID_BLEN 8 -#define MASK_CTL_DEVICE_ID_FLAG HSL_RO - -#define REV_ID -#define MASK_CTL_REV_ID_BOFFSET 0 -#define MASK_CTL_REV_ID_BLEN 8 -#define MASK_CTL_REV_ID_FLAG HSL_RO - - - - - /* Port0 Pad Control Register */ -#define PORT0_PAD_CTRL -#define PORT0_PAD_CTRL_ID 0 -#define PORT0_PAD_CTRL_OFFSET 0x0004 -#define PORT0_PAD_CTRL_E_LENGTH 4 -#define PORT0_PAD_CTRL_E_OFFSET 0 -#define PORT0_PAD_CTRL_NR_E 1 - -#define RMII_MAC06_EXCH_EN -#define PORT0_PAD_CTRL_RMII_MAC06_EXCH_EN_BOFFSET 31 -#define PORT0_PAD_CTRL_RMII_MAC06_EXCH_EN_BLEN 1 -#define PORT0_PAD_CTRL_RMII_MAC06_EXCH_EN_FLAG HSL_RW - -#define RMII_MASTER_EN -#define PORT0_PAD_CTRL_RMII_MASTER_EN_BOFFSET 30 -#define PORT0_PAD_CTRL_RMII_MASTER_EN_BLEN 1 -#define PORT0_PAD_CTRL_RMII_MASTER_EN_FLAG HSL_RW - -#define RMII_SLAVE_EN -#define PORT0_PAD_CTRL_RMII_SLAVE_EN_BOFFSET 29 -#define PORT0_PAD_CTRL_RMII_SLAVE_EN_BLEN 1 -#define PORT0_PAD_CTRL_RMII_SLAVE_EN_FLAG HSL_RW - -#define RMII_SEL -#define PORT0_PAD_CTRL_RMII_SEL_BOFFSET 28 -#define PORT0_PAD_CTRL_RMII_SEL_BLEN 1 -#define PORT0_PAD_CTRL_RMII_SEL_FLAG HSL_RW - -#define RMII_PIPE_RXCLK_SEL -#define PORT0_PAD_CTRL_RMII_PIPE_RXCLK_SEL_BOFFSET 27 -#define PORT0_PAD_CTRL_RMII_PIPE_RXCLK_SEL_BLEN 1 -#define PORT0_PAD_CTRL_RMII_PIPE_RXCLK_SEL_FLAG HSL_RW - -#define MAC0_RGMII_EN -#define PORT0_PAD_CTRL_MAC0_RGMII_EN_BOFFSET 26 -#define PORT0_PAD_CTRL_MAC0_RGMII_EN_BLEN 1 -#define PORT0_PAD_CTRL_MAC0_RGMII_EN_FLAG HSL_RW - -#define MAC0_RGMII_TXCLK_DELAY_EN -#define PORT0_PAD_CTRL_MAC0_RGMII_TXCLK_DELAY_EN_BOFFSET 25 -#define PORT0_PAD_CTRL_MAC0_RGMII_TXCLK_DELAY_EN_BLEN 1 -#define PORT0_PAD_CTRL_MAC0_RGMII_TXCLK_DELAY_EN_FLAG HSL_RW - -#define MAC0_RGMII_RXCLK_DELAY_EN -#define PORT0_PAD_CTRL_MAC0_RGMII_RXCLK_DELAY_EN_BOFFSET 24 -#define PORT0_PAD_CTRL_MAC0_RGMII_RXCLK_DELAY_EN_BLEN 1 -#define PORT0_PAD_CTRL_MAC0_RGMII_RXCLK_DELAY_EN_FLAG HSL_RW - -#define MAC0_RGMII_TXCLK_DELAY_SEL -#define PORT0_PAD_CTRL_MAC0_RGMII_TXCLK_DELAY_SEL_BOFFSET 22 -#define PORT0_PAD_CTRL_MAC0_RGMII_TXCLK_DELAY_SEL_BLEN 2 -#define PORT0_PAD_CTRL_MAC0_RGMII_TXCLK_DELAY_SEL_FLAG HSL_RW - -#define MAC0_RGMII_RXCLK_DELAY_SEL -#define PORT0_PAD_CTRL_MAC0_RGMII_RXCLK_DELAY_SEL_BOFFSET 20 -#define PORT0_PAD_CTRL_MAC0_RGMII_RXCLK_DELAY_SEL_BLEN 2 -#define PORT0_PAD_CTRL_MAC0_RGMII_RXCLK_DELAY_SEL_FLAG HSL_RW - -#define SGMII_CLK125M_RX_SEL -#define PORT0_PAD_CTRL_SGMII_CLK125M_RX_SEL_BOFFSET 19 -#define PORT0_PAD_CTRL_SGMII_CLK125M_RX_SEL_BLEN 1 -#define PORT0_PAD_CTRL_SGMII_CLK125M_RX_SEL_FLAG HSL_RW - -#define SGMII_CLK125M_TX_SEL -#define PORT0_PAD_CTRL_SGMII_CLK125M_TX_SEL_BOFFSET 18 -#define PORT0_PAD_CTRL_SGMII_CLK125M_TX_SEL_BLEN 1 -#define PORT0_PAD_CTRL_SGMII_CLK125M_TX_SEL_FLAG HSL_RW - -#define SGMII_FX100_EN -#define PORT0_PAD_CTRL_SGMII_FX100_EN_BOFFSET 17 -#define PORT0_PAD_CTRL_SGMII_FX100_EN_BLEN 1 -#define PORT0_PAD_CTRL_SGMII_FX100_EN_FLAG HSL_RW - -#define SGMII_PRBS_BERT_EN -#define PORT0_PAD_CTRL_SGMII_PRBS_BERT_EN_BOFFSET 16 -#define PORT0_PAD_CTRL_SGMII_PRBS_BERT_EN_BLEN 1 -#define PORT0_PAD_CTRL_SGMII_PRBS_BERT_EN_FLAG HSL_RW - -#define SGMII_REM_PHY_LPBK_EN -#define PORT0_PAD_CTRL_SGMII_REM_PHY_LPBK_EN_BOFFSET 15 -#define PORT0_PAD_CTRL_SGMII_REM_PHY_LPBK_EN_BLEN 1 -#define PORT0_PAD_CTRL_SGMII_REM_PHY_LPBK_EN_FLAG HSL_RW - -#define MAC0_PHY_GMII_EN -#define PORT0_PAD_CTRL_MAC0_PHY_GMII_EN_BOFFSET 14 -#define PORT0_PAD_CTRL_MAC0_PHY_GMII_EN_BLEN 1 -#define PORT0_PAD_CTRL_MAC0_PHY_GMII_EN_FLAG HSL_RW - -#define MAC0_PHY_GMII_TXCLK_SEL -#define PORT0_PAD_CTRL_MAC0_PHY_GMII_TXCLK_SEL_BOFFSET 13 -#define PORT0_PAD_CTRL_MAC0_PHY_GMII_TXCLK_SEL_BLEN 1 -#define PORT0_PAD_CTRL_MAC0_PHY_GMII_TXCLK_SEL_FLAG HSL_RW - -#define MAC0_PHY_GMII_RXCLK_SEL -#define PORT0_PAD_CTRL_MAC0_PHY_GMII_RXCLK_SEL_BOFFSET 12 -#define PORT0_PAD_CTRL_MAC0_PHY_GMII_RXCLK_SEL_BLEN 1 -#define PORT0_PAD_CTRL_MAC0_PHY_GMII_RXCLK_SEL_FLAG HSL_RW - -#define MAC0_PHY_MII_PIPE_RXCLK_SEL -#define PORT0_PAD_CTRL_MAC0_PHY_MII_PIPE_RXCLK_SEL_BOFFSET 11 -#define PORT0_PAD_CTRL_MAC0_PHY_MII_PIPE_RXCLK_SEL_BLEN 1 -#define PORT0_PAD_CTRL_MAC0_PHY_MII_PIPE_RXCLK_SEL_FLAG HSL_RW - -#define MAC0_PHY_MII_EN -#define PORT0_PAD_CTRL_MAC0_PHY_MII_EN_BOFFSET 10 -#define PORT0_PAD_CTRL_MAC0_PHY_MII_EN_BLEN 1 -#define PORT0_PAD_CTRL_MAC0_PHY_MII_EN_FLAG HSL_RW - -#define MAC0_PHY_MII_TXCLK_SEL -#define PORT0_PAD_CTRL_MAC0_PHY_MII_TXCLK_SEL_BOFFSET 9 -#define PORT0_PAD_CTRL_MAC0_PHY_MII_TXCLK_SEL_BLEN 1 -#define PORT0_PAD_CTRL_MAC0_PHY_MII_TXCLK_SEL_FLAG HSL_RW - -#define MAC0_PHY_MII_RXCLK_SEL -#define PORT0_PAD_CTRL_MAC0_PHY_MII_RXCLK_SEL_BOFFSET 8 -#define PORT0_PAD_CTRL_MAC0_PHY_MII_RXCLK_SEL_BLEN 1 -#define PORT0_PAD_CTRL_MAC0_PHY_MII_RXCLK_SEL_FLAG HSL_RW - -#define MAC0_SGMII_EN -#define PORT0_PAD_CTRL_MAC0_SGMII_EN_BOFFSET 7 -#define PORT0_PAD_CTRL_MAC0_SGMII_EN_BLEN 1 -#define PORT0_PAD_CTRL_MAC0_SGMII_EN_FLAG HSL_RW - -#define MAC0_MAC_GMII_EN -#define PORT0_PAD_CTRL_MAC0_MAC_GMII_EN_BOFFSET 6 -#define PORT0_PAD_CTRL_MAC0_MAC_GMII_EN_BLEN 1 -#define PORT0_PAD_CTRL_MAC0_MAC_GMII_EN_FLAG HSL_RW - -#define MAC0_MAC_GMII_TXCLK_SEL -#define PORT0_PAD_CTRL_MAC0_MAC_GMII_TXCLK_SEL_BOFFSET 5 -#define PORT0_PAD_CTRL_MAC0_MAC_GMII_TXCLK_SEL_BLEN 1 -#define PORT0_PAD_CTRL_MAC0_MAC_GMII_TXCLK_SEL_FLAG HSL_RW - -#define MAC0_MAC_GMII_RXCLK_SEL -#define PORT0_PAD_CTRL_MAC0_MAC_GMII_RXCLK_SEL_BOFFSET 4 -#define PORT0_PAD_CTRL_MAC0_MAC_GMII_RXCLK_SEL_BLEN 1 -#define PORT0_PAD_CTRL_MAC0_MAC_GMII_RXCLK_SEL_FLAG HSL_RW - -#define MAC0_MAC_SGMII_FORCE_SPEED -#define PORT0_PAD_CTRL_MAC0_MAC_SGMII_FORCE_SPEED_BOFFSET 3 -#define PORT0_PAD_CTRL_MAC0_MAC_SGMII_FORCE_SPEED_BLEN 1 -#define PORT0_PAD_CTRL_MAC0_MAC_SGMII_FORCE_SPEED_FLAG HSL_RW - -#define MAC0_MAC_MII_EN -#define PORT0_PAD_CTRL_MAC0_MAC_MII_EN_BOFFSET 2 -#define PORT0_PAD_CTRL_MAC0_MAC_MII_EN_BLEN 1 -#define PORT0_PAD_CTRL_MAC0_MAC_MII_EN_FLAG HSL_RW - -#define MAC0_MAC_MII_TXCLK_SEL -#define PORT0_PAD_CTRL_MAC0_MAC_MII_TXCLK_SEL_BOFFSET 1 -#define PORT0_PAD_CTRL_MAC0_MAC_MII_TXCLK_SEL_BLEN 1 -#define PORT0_PAD_CTRL_MAC0_MAC_MII_TXCLK_SEL_FLAG HSL_RW - -#define MAC0_MAC_MII_RXCLK_SEL -#define PORT0_PAD_CTRL_MAC0_MAC_MII_RXCLK_SEL_BOFFSET 0 -#define PORT0_PAD_CTRL_MAC0_MAC_MII_RXCLK_SEL_BLEN 1 -#define PORT0_PAD_CTRL_MAC0_MAC_MII_RXCLK_SEL_FLAG HSL_RW - - - - - /* Port5 Pad Control Register */ -#define PORT5_PAD_CTRL -#define PORT5_PAD_CTRL_ID 0 -#define PORT5_PAD_CTRL_OFFSET 0x0008 -#define PORT5_PAD_CTRL_E_LENGTH 4 -#define PORT5_PAD_CTRL_E_OFFSET 0 -#define PORT5_PAD_CTRL_NR_E 1 - -#define MAC5_RGMII_EN -#define PORT5_PAD_CTRL_MAC5_RGMII_EN_BOFFSET 26 -#define PORT5_PAD_CTRL_MAC5_RGMII_EN_BLEN 1 -#define PORT5_PAD_CTRL_MAC5_RGMII_EN_FLAG HSL_RW - -#define MAC5_RGMII_TXCLK_DELAY_EN -#define PORT5_PAD_CTRL_MAC5_RGMII_TXCLK_DELAY_EN_BOFFSET 25 -#define PORT5_PAD_CTRL_MAC5_RGMII_TXCLK_DELAY_EN_BLEN 1 -#define PORT5_PAD_CTRL_MAC5_RGMII_TXCLK_DELAY_EN_FLAG HSL_RW - -#define MAC5_RGMII_RXCLK_DELAY_EN -#define PORT5_PAD_CTRL_MAC5_RGMII_RXCLK_DELAY_EN_BOFFSET 24 -#define PORT5_PAD_CTRL_MAC5_RGMII_RXCLK_DELAY_EN_BLEN 1 -#define PORT5_PAD_CTRL_MAC5_RGMII_RXCLK_DELAY_EN_FLAG HSL_RW - -#define MAC5_RGMII_TXCLK_DELAY_SEL -#define PORT5_PAD_CTRL_MAC5_RGMII_TXCLK_DELAY_SEL_BOFFSET 22 -#define PORT5_PAD_CTRL_MAC5_RGMII_TXCLK_DELAY_SEL_BLEN 2 -#define PORT5_PAD_CTRL_MAC5_RGMII_TXCLK_DELAY_SEL_FLAG HSL_RW - -#define MAC5_RGMII_RXCLK_DELAY_SEL -#define PORT5_PAD_CTRL_MAC5_RGMII_RXCLK_DELAY_SEL_BOFFSET 20 -#define PORT5_PAD_CTRL_MAC5_RGMII_RXCLK_DELAY_SEL_BLEN 2 -#define PORT5_PAD_CTRL_MAC5_RGMII_RXCLK_DELAY_SEL_FLAG HSL_RW - -#define MAC5_PHY_MII_PIPE_RXCLK_SEL -#define PORT5_PAD_CTRL_MAC5_PHY_MII_PIPE_RXCLK_SEL_BOFFSET 11 -#define PORT5_PAD_CTRL_MAC5_PHY_MII_PIPE_RXCLK_SEL_BLEN 1 -#define PORT5_PAD_CTRL_MAC5_PHY_MII_PIPE_RXCLK_SEL_FLAG HSL_RW - -#define MAC5_PHY_MII_EN -#define PORT5_PAD_CTRL_MAC5_PHY_MII_EN_BOFFSET 10 -#define PORT5_PAD_CTRL_MAC5_PHY_MII_EN_BLEN 1 -#define PORT5_PAD_CTRL_MAC5_PHY_MII_EN_FLAG HSL_RW - -#define MAC5_PHY_MII_TXCLK_SEL -#define PORT5_PAD_CTRL_MAC5_PHY_MII_TXCLK_SEL_BOFFSET 9 -#define PORT5_PAD_CTRL_MAC5_PHY_MII_TXCLK_SEL_BLEN 1 -#define PORT5_PAD_CTRL_MAC5_PHY_MII_TXCLK_SEL_FLAG HSL_RW - -#define MAC5_PHY_MII_RXCLK_SEL -#define PORT5_PAD_CTRL_MAC5_PHY_MII_RXCLK_SEL_BOFFSET 8 -#define PORT5_PAD_CTRL_MAC5_PHY_MII_RXCLK_SEL_BLEN 1 -#define PORT5_PAD_CTRL_MAC5_PHY_MII_RXCLK_SEL_FLAG HSL_RW - -#define MAC5_MAC_MII_EN -#define PORT5_PAD_CTRL_MAC5_MAC_MII_EN_BOFFSET 2 -#define PORT5_PAD_CTRL_MAC5_MAC_MII_EN_BLEN 1 -#define PORT5_PAD_CTRL_MAC5_MAC_MII_EN_FLAG HSL_RW - -#define MAC5_MAC_MII_TXCLK_SEL -#define PORT5_PAD_CTRL_MAC0_MAC_MII_TXCLK_SEL_BOFFSET 1 -#define PORT5_PAD_CTRL_MAC0_MAC_MII_TXCLK_SEL_BLEN 1 -#define PORT5_PAD_CTRL_MAC0_MAC_MII_TXCLK_SEL_FLAG HSL_RW - -#define MAC5_MAC_MII_RXCLK_SEL -#define PORT5_PAD_CTRL_MAC5_MAC_MII_RXCLK_SEL_BOFFSET 0 -#define PORT5_PAD_CTRL_MAC5_MAC_MII_RXCLK_SEL_BLEN 1 -#define PORT5_PAD_CTRL_MAC5_MAC_MII_RXCLK_SEL_FLAG HSL_RW - - - - - /* Port6 Pad Control Register */ -#define PORT6_PAD_CTRL -#define PORT6_PAD_CTRL_ID 0 -#define PORT6_PAD_CTRL_OFFSET 0x000c -#define PORT6_PAD_CTRL_E_LENGTH 4 -#define PORT6_PAD_CTRL_E_OFFSET 0 -#define PORT6_PAD_CTRL_NR_E 1 - -#define MAC6_RGMII_EN -#define PORT6_PAD_CTRL_MAC6_RGMII_EN_BOFFSET 26 -#define PORT6_PAD_CTRL_MAC6_RGMII_EN_BLEN 1 -#define PORT6_PAD_CTRL_MAC6_RGMII_EN_FLAG HSL_RW - -#define MAC6_RGMII_TXCLK_DELAY_EN -#define PORT6_PAD_CTRL_MAC6_RGMII_TXCLK_DELAY_EN_BOFFSET 25 -#define PORT6_PAD_CTRL_MAC6_RGMII_TXCLK_DELAY_EN_BLEN 1 -#define PORT6_PAD_CTRL_MAC6_RGMII_TXCLK_DELAY_EN_FLAG HSL_RW - -#define MAC6_RGMII_RXCLK_DELAY_EN -#define PORT6_PAD_CTRL_MAC6_RGMII_RXCLK_DELAY_EN_BOFFSET 24 -#define PORT6_PAD_CTRL_MAC6_RGMII_RXCLK_DELAY_EN_BLEN 1 -#define PORT6_PAD_CTRL_MAC6_RGMII_RXCLK_DELAY_EN_FLAG HSL_RW - -#define MAC6_RGMII_TXCLK_DELAY_SEL -#define PORT6_PAD_CTRL_MAC6_RGMII_TXCLK_DELAY_SEL_BOFFSET 22 -#define PORT6_PAD_CTRL_MAC6_RGMII_TXCLK_DELAY_SEL_BLEN 2 -#define PORT6_PAD_CTRL_MAC6_RGMII_TXCLK_DELAY_SEL_FLAG HSL_RW - -#define MAC6_RGMII_RXCLK_DELAY_SEL -#define PORT6_PAD_CTRL_MAC6_RGMII_RXCLK_DELAY_SEL_BOFFSET 20 -#define PORT6_PAD_CTRL_MAC6_RGMII_RXCLK_DELAY_SEL_BLEN 2 -#define PORT6_PAD_CTRL_MAC6_RGMII_RXCLK_DELAY_SEL_FLAG HSL_RW - -#define PHY4_RGMII_EN -#define PORT6_PAD_CTRL_PHY4_RGMII_EN_BOFFSET 17 -#define PORT6_PAD_CTRL_PHY4_RGMII_EN_BLEN 1 -#define PORT6_PAD_CTRL_PHY4_RGMII_EN_FLAG HSL_RW - -#define MAC6_PHY_GMII_EN -#define PORT6_PAD_CTRL_MAC6_PHY_GMII_EN_BOFFSET 14 -#define PORT6_PAD_CTRL_MAC6_PHY_GMII_EN_BLEN 1 -#define PORT6_PAD_CTRL_MAC6_PHY_GMII_EN_FLAG HSL_RW - -#define MAC6_PHY_GMII_TXCLK_SEL -#define PORT6_PAD_CTRL_MAC6_PHY_GMII_TXCLK_SEL_BOFFSET 13 -#define PORT6_PAD_CTRL_MAC6_PHY_GMII_TXCLK_SEL_BLEN 1 -#define PORT6_PAD_CTRL_MAC6_PHY_GMII_TXCLK_SEL_FLAG HSL_RW - -#define MAC6_PHY_GMII_RXCLK_SEL -#define PORT6_PAD_CTRL_MAC6_PHY_GMII_RXCLK_SEL_BOFFSET 12 -#define PORT6_PAD_CTRL_MAC6_PHY_GMII_RXCLK_SEL_BLEN 1 -#define PORT6_PAD_CTRL_MAC6_PHY_GMII_RXCLK_SEL_FLAG HSL_RW - -#define MAC6_PHY_MII_PIPE_RXCLK_SEL -#define PORT6_PAD_CTRL_MAC6_PHY_MII_PIPE_RXCLK_SEL_BOFFSET 11 -#define PORT6_PAD_CTRL_MAC6_PHY_MII_PIPE_RXCLK_SEL_BLEN 1 -#define PORT6_PAD_CTRL_MAC6_PHY_MII_PIPE_RXCLK_SEL_FLAG HSL_RW - -#define MAC6_PHY_MII_EN -#define PORT6_PAD_CTRL_MAC6_PHY_MII_EN_BOFFSET 10 -#define PORT6_PAD_CTRL_MAC6_PHY_MII_EN_BLEN 1 -#define PORT6_PAD_CTRL_MAC6_PHY_MII_EN_FLAG HSL_RW - -#define MAC6_PHY_MII_TXCLK_SEL -#define PORT6_PAD_CTRL_MAC6_PHY_MII_TXCLK_SEL_BOFFSET 9 -#define PORT6_PAD_CTRL_MAC6_PHY_MII_TXCLK_SEL_BLEN 1 -#define PORT6_PAD_CTRL_MAC6_PHY_MII_TXCLK_SEL_FLAG HSL_RW - -#define MAC6_PHY_MII_RXCLK_SEL -#define PORT6_PAD_CTRL_MAC6_PHY_MII_RXCLK_SEL_BOFFSET 8 -#define PORT6_PAD_CTRL_MAC6_PHY_MII_RXCLK_SEL_BLEN 1 -#define PORT6_PAD_CTRL_MAC6_PHY_MII_RXCLK_SEL_FLAG HSL_RW - -#define MAC6_SGMII_EN -#define PORT6_PAD_CTRL_MAC6_SGMII_EN_BOFFSET 7 -#define PORT6_PAD_CTRL_MAC6_SGMII_EN_BLEN 1 -#define PORT6_PAD_CTRL_MAC6_SGMII_EN_FLAG HSL_RW - -#define MAC6_MAC_GMII_EN -#define PORT6_PAD_CTRL_MAC6_MAC_GMII_EN_BOFFSET 6 -#define PORT6_PAD_CTRL_MAC6_MAC_GMII_EN_BLEN 1 -#define PORT6_PAD_CTRL_MAC6_MAC_GMII_EN_FLAG HSL_RW - -#define MAC6_MAC_GMII_TXCLK_SEL -#define PORT6_PAD_CTRL_MAC6_MAC_GMII_TXCLK_SEL_BOFFSET 5 -#define PORT6_PAD_CTRL_MAC6_MAC_GMII_TXCLK_SEL_BLEN 1 -#define PORT6_PAD_CTRL_MAC6_MAC_GMII_TXCLK_SEL_FLAG HSL_RW - -#define MAC6_MAC_GMII_RXCLK_SEL -#define PORT6_PAD_CTRL_MAC6_MAC_GMII_RXCLK_SEL_BOFFSET 4 -#define PORT6_PAD_CTRL_MAC6_MAC_GMII_RXCLK_SEL_BLEN 1 -#define PORT6_PAD_CTRL_MAC6_MAC_GMII_RXCLK_SEL_FLAG HSL_RW - -#define MAC6_MAC_MII_EN -#define PORT6_PAD_CTRL_MAC6_MAC_MII_EN_BOFFSET 2 -#define PORT6_PAD_CTRL_MAC6_MAC_MII_EN_BLEN 1 -#define PORT6_PAD_CTRL_MAC6_MAC_MII_EN_FLAG HSL_RW - -#define MAC6_MAC_MII_TXCLK_SEL -#define PORT6_PAD_CTRL_MAC6_MAC_MII_TXCLK_SEL_BOFFSET 1 -#define PORT6_PAD_CTRL_MAC6_MAC_MII_TXCLK_SEL_BLEN 1 -#define PORT6_PAD_CTRL_MAC6_MAC_MII_TXCLK_SEL_FLAG HSL_RW - -#define MAC6_MAC_MII_RXCLK_SEL -#define PORT6_PAD_CTRL_MAC6_MAC_MII_RXCLK_SEL_BOFFSET 0 -#define PORT6_PAD_CTRL_MAC6_MAC_MII_RXCLK_SEL_BLEN 1 -#define PORT6_PAD_CTRL_MAC6_MAC_MII_RXCLK_SEL_FLAG HSL_RW - - - - - /* SGMII Control Register */ -#define SGMII_CTRL -#define SGMII_CTRL_ID 0 -#define SGMII_CTRL_OFFSET 0x00e0 -#define SGMII_CTRL_E_LENGTH 4 -#define SGMII_CTRL_E_OFFSET 0 -#define SGMII_CTRL_NR_E 1 - -#define FULL_25M -#define SGMII_CTRL_FULL_25M_BOFFSET 31 -#define SGMII_CTRL_FULL_25M_BLEN 1 -#define SGMII_CTRL_FULL_25M_FLAG HSL_RW - -#define HALF_25M -#define SGMII_CTRL_HALF_25M_BOFFSET 30 -#define SGMII_CTRL_HALF_25M_BLEN 1 -#define SGMII_CTRL_HALF_25M_FLAG HSL_RW - -#define REMOTE_25M -#define SGMII_CTRL_REMOTE_25M_BOFFSET 28 -#define SGMII_CTRL_REMOTE_25M_BLEN 2 -#define SGMII_CTRL_REMOTE_25M_FLAG HSL_RW - -#define NEXT_PAGE_25M -#define SGMII_CTRL_NEXT_PAGE_25M_BOFFSET 27 -#define SGMII_CTRL_NEXT_PAGE_25M_BLEN 1 -#define SGMII_CTRL_NEXT_PAGE_25M_FLAG HSL_RW - -#define PAUSE_25M -#define SGMII_CTRL_PAUSE_25M_BOFFSET 26 -#define SGMII_CTRL_PAUSE_25M_BLEN 1 -#define SGMII_CTRL_PAUSE_25M_FLAG HSL_RW - -#define ASYM_PAUSE_25M -#define SGMII_CTRL_ASYM_PAUSE_25M_BOFFSET 25 -#define SGMII_CTRL_ASYM_PAUSE_25M_BLEN 1 -#define SGMII_CTRL_ASYM_PAUSE_25M_FLAG HSL_RW - -#define PAUSE_SG_25M -#define SGMII_CTRL_PAUSE_SG_25M_BOFFSET 24 -#define SGMII_CTRL_PAUSE_SG_25M_BLEN 1 -#define SGMII_CTRL_PAUSE_SG_25M_FLAG HSL_RW - -#define PAUSE_SG_25M -#define SGMII_CTRL_PAUSE_SG_25M_BOFFSET 24 -#define SGMII_CTRL_PAUSE_SG_25M_BLEN 1 -#define SGMII_CTRL_PAUSE_SG_25M_FLAG HSL_RW - -#define MODE_CTRL_25M -#define SGMII_CTRL_MODE_CTRL_25M_BOFFSET 22 -#define SGMII_CTRL_MODE_CTRL_25M_BLEN 2 -#define SGMII_CTRL_MODE_CTRL_25M_FLAG HSL_RW - -#define MR_LOOPBACK -#define SGMII_CTRL_MR_LOOPBACK_BOFFSET 21 -#define SGMII_CTRL_MR_LOOPBACK_BLEN 1 -#define SGMII_CTRL_MR_LOOPBACK_FLAG HSL_RW - -#define MR_REG4_25M -#define SGMII_CTRL_MR_REG4_25M_BOFFSET 20 -#define SGMII_CTRL_MR_REG4_25M_BLEN 1 -#define SGMII_CTRL_MR_REG4_25M_FLAG HSL_RW - -#define AUTO_LPI_25M -#define SGMII_CTRL_AUTO_LPI_25M_BOFFSET 19 -#define SGMII_CTRL_AUTO_LPI_25M_BLEN 1 -#define SGMII_CTRL_AUTO_LPI_25M_FLAG HSL_RW - -#define PRBS_EN -#define SGMII_CTRL_PRBS_EN_BOFFSET 18 -#define SGMII_CTRL_PRBS_EN_BLEN 1 -#define SGMII_CTRL_PRBS_EN_FLAG HSL_RW - -#define SGMII_TH_LOS1 -#define SGMII_CTRL_SGMII_TH_LOS1_BOFFSET 17 -#define SGMII_CTRL_SGMII_TH_LOS1_BLEN 1 -#define SGMII_CTRL_SGMII_TH_LOS1_FLAG HSL_RW - -#define DIS_AUTO_LPI_25M -#define SGMII_CTRL_DIS_AUTO_LPI_25M_BOFFSET 16 -#define SGMII_CTRL_DIS_AUTO_LPI_25M_BLEN 1 -#define SGMII_CTRL_DIS_AUTO_LPI_25M_FLAG HSL_RW - -#define SGMII_TH_LOS0 -#define SGMII_CTRL_SGMII_TH_LOS0_BOFFSET 15 -#define SGMII_CTRL_SGMII_TH_LOS0_BLEN 1 -#define SGMII_CTRL_SGMII_TH_LOS0_FLAG HSL_RW - -#define SGMII_CDR_BW -#define SGMII_CTRL_SGMII_CDR_BW_BOFFSET 13 -#define SGMII_CTRL_SGMII_CDR_BW_BLEN 2 -#define SGMII_CTRL_SGMII_CDR_BW_FLAG HSL_RW - -#define SGMII_TXDR_CTRL -#define SGMII_CTRL_SGMII_TXDR_CTRL_BOFFSET 10 -#define SGMII_CTRL_SGMII_TXDR_CTRL_BLEN 3 -#define SGMII_CTRL_SGMII_TXDR_CTRL_FLAG HSL_RW - -#define SGMII_FIBER_MODE -#define SGMII_CTRL_SGMII_FIBER_MODE_BOFFSET 8 -#define SGMII_CTRL_SGMII_FIBER_MODE_BLEN 2 -#define SGMII_CTRL_SGMII_FIBER_MODE_FLAG HSL_RW - -#define SGMII_SEL_125M -#define SGMII_CTRL_SGMII_SEL_125M_BOFFSET 7 -#define SGMII_CTRL_SGMII_SEL_125M_BLEN 1 -#define SGMII_CTRL_SGMII_SEL_125M_FLAG HSL_RW - -#define SGMII_PLL_BW -#define SGMII_CTRL_SGMII_PLL_BW_BOFFSET 6 -#define SGMII_CTRL_SGMII_PLL_BW_BLEN 1 -#define SGMII_CTRL_SGMII_PLL_BW_FLAG HSL_RW - -#define SGMII_HALFTX -#define SGMII_CTRL_SGMII_HALFTX_BOFFSET 5 -#define SGMII_CTRL_SGMII_HALFTX_BLEN 1 -#define SGMII_CTRL_SGMII_HALFTX_FLAG HSL_RW - -#define SGMII_EN_SD -#define SGMII_CTRL_SGMII_EN_SD_BOFFSET 4 -#define SGMII_CTRL_SGMII_EN_SD_BLEN 1 -#define SGMII_CTRL_SGMII_EN_SD_FLAG HSL_RW - -#define SGMII_EN_TX -#define SGMII_CTRL_SGMII_EN_TX_BOFFSET 3 -#define SGMII_CTRL_SGMII_EN_TX_BLEN 1 -#define SGMII_CTRL_SGMII_EN_TX_FLAG HSL_RW - -#define SGMII_EN_RX -#define SGMII_CTRL_SGMII_EN_RX_BOFFSET 2 -#define SGMII_CTRL_SGMII_EN_RX_BLEN 1 -#define SGMII_CTRL_SGMII_EN_RX_FLAG HSL_RW - -#define SGMII_EN_PLL -#define SGMII_CTRL_SGMII_EN_PLL_BOFFSET 1 -#define SGMII_CTRL_SGMII_EN_PLL_BLEN 1 -#define SGMII_CTRL_SGMII_EN_PLL_FLAG HSL_RW - -#define SGMII_EN_LCKDT -#define SGMII_CTRL_SGMII_EN_LCKDT_BOFFSET 0 -#define SGMII_CTRL_SGMII_EN_LCKDT_BLEN 1 -#define SGMII_CTRL_SGMII_EN_LCKDT_FLAG HSL_RW - - - - - /* Power On Strip Register */ -#define POWER_STRIP -#define POWER_STRIP_ID 0 -#define POWER_STRIP_OFFSET 0x0010 -#define POWER_STRIP_E_LENGTH 4 -#define POWER_STRIP_E_OFFSET 0 -#define POWER_STRIP_NR_E 1 - -#define POWER_ON_SEL -#define POWER_STRIP_POWER_ON_SEL_BOFFSET 31 -#define POWER_STRIP_POWER_ON_SEL_BLEN 1 -#define POWER_STRIP_POWER_ON_SEL_FLAG HSL_RW - -#define PKG128_EN -#define POWER_STRIP_PKG128_EN_BOFFSET 30 -#define POWER_STRIP_PKG128_EN_BLEN 1 -#define POWER_STRIP_PKG128_EN_FLAG HSL_RW - -#define PKG128_EN_LED -#define POWER_STRIP_PKG128_EN_LED_BOFFSET 29 -#define POWER_STRIP_PKG128_EN_LED_BLEN 1 -#define POWER_STRIP_PKG128_EN_LED_FLAG HSL_RW - -#define S16_MODE -#define POWER_STRIP_S16_MODE_BOFFSET 28 -#define POWER_STRIP_S16_MODE_BLEN 1 -#define POWER_STRIP_S16_MODE_FLAG HSL_RW - -#define INPUT_MODE -#define POWER_STRIP_INPUT_MODE_BOFFSET 27 -#define POWER_STRIP_INPUT_MODE_BLEN 1 -#define POWER_STRIP_INPUT_MODE_FLAG HSL_RW - -#define SGMII_POWER_ON_SEL -#define POWER_STRIP_SGMII_POWER_ON_SEL_BOFFSET 26 -#define POWER_STRIP_SGMII_POWER_ON_SEL_BLEN 1 -#define POWER_STRIP_SGMII_POWER_ON_SEL_FLAG HSL_RW - -#define SPI_EN -#define POWER_STRIP_SPI_EN_BOFFSET 25 -#define POWER_STRIP_SPI_EN_BLEN 1 -#define POWER_STRIP_SPI_EN_FLAG HSL_RW - -#define LED_OPEN_EN -#define POWER_STRIP_LED_OPEN_EN_BOFFSET 24 -#define POWER_STRIP_LED_OPEN_EN_BLEN 1 -#define POWER_STRIP_LED_OPEN_EN_FLAG HSL_RW - -#define SGMII_RXIMP_50_70 -#define POWER_STRIP_SGMII_RXIMP_50_70_BOFFSET 23 -#define POWER_STRIP_SGMII_RXIMP_50_70_BLEN 1 -#define POWER_STRIP_SGMII_RXIMP_50_70_FLAG HSL_RW - -#define SGMII_TXIMP_50_70 -#define POWER_STRIP_SGMII_TXIMP_50_70_BOFFSET 22 -#define POWER_STRIP_SGMII_TXIMP_50_70_BLEN 1 -#define POWER_STRIP_SGMII_TXIMP_50_70_FLAG HSL_RW - -#define SGMII_SIGNAL_DETECT -#define POWER_STRIP_SGMII_SIGNAL_DETECT_BOFFSET 21 -#define POWER_STRIP_SGMII_SIGNAL_DETECT_BLEN 1 -#define POWER_STRIP_SGMII_SIGNAL_DETECT_FLAG HSL_RW - -#define LPW_EXIT -#define POWER_STRIP_LPW_EXIT_BOFFSET 20 -#define POWER_STRIP_LPW_EXIT_BLEN 1 -#define POWER_STRIP_LPW_EXIT_FLAG HSL_RW - -#define MAN_EN -#define POWER_STRIP_MAN_EN_BOFFSET 18 -#define POWER_STRIP_MAN_EN_BLEN 1 -#define POWER_STRIP_MAN_EN_FLAG HSL_RW - -#define HIB_EN -#define POWER_STRIP_HIB_EN_BOFFSET 17 -#define POWER_STRIP_HIB_EN_BLEN 1 -#define POWER_STRIP_HIB_EN_FLAG HSL_RW - -#define POWER_DOWN_HW -#define POWER_STRIP_POWER_DOWN_HW_BOFFSET 16 -#define POWER_STRIP_POWER_DOWN_HW_BLEN 1 -#define POWER_STRIP_POWER_DOWN_HW_FLAG HSL_RW - -#define BIST_BYPASS_CEL -#define POWER_STRIP_BIST_BYPASS_CEL_BOFFSET 15 -#define POWER_STRIP_BIST_BYPASS_CEL_BLEN 1 -#define POWER_STRIP_BIST_BYPASS_CEL_FLAG HSL_RW - -#define BIST_BYPASS_CSR -#define POWER_STRIP_BIST_BYPASS_CSR_BOFFSET 14 -#define POWER_STRIP_BIST_BYPASS_CSR_BLEN 1 -#define POWER_STRIP_BIST_BYPASS_CSR_FLAG HSL_RW - -#define HIB_PULSE_HW -#define POWER_STRIP_HIB_PULSE_HW_BOFFSET 12 -#define POWER_STRIP_HIB_PULSE_HW_BLEN 1 -#define POWER_STRIP_HIB_PULSE_HW_FLAG HSL_RW - -#define GATE_25M_EN -#define POWER_STRIP_GATE_25M_EN_BOFFSET 10 -#define POWER_STRIP_GATE_25M_EN_BLEN 1 -#define POWER_STRIP_GATE_25M_EN_FLAG HSL_RW - -#define SEL_ANA_RST -#define POWER_STRIP_SEL_ANA_RST_BOFFSET 9 -#define POWER_STRIP_SEL_ANA_RST_BLEN 1 -#define POWER_STRIP_SEL_ANA_RST_FLAG HSL_RW - -#define SERDES_EN -#define POWER_STRIP_SERDES_EN_BOFFSET 8 -#define POWER_STRIP_SERDES_EN_BLEN 1 -#define POWER_STRIP_SERDES_EN_FLAG HSL_RW - -#define SERDES_AN_EN -#define POWER_STRIP_SERDES_AN_EN_BOFFSET 7 -#define POWER_STRIP_SERDES_AN_EN_BLEN 1 -#define POWER_STRIP_SERDES_AN_EN_FLAG HSL_RW - -#define RTL_MODE -#define POWER_STRIP_RTL_MODE_BOFFSET 5 -#define POWER_STRIP_RTL_MODE_BLEN 1 -#define POWER_STRIP_RTL_MODE_FLAG HSL_RW - -#define PAD_CTRL_FOR25M -#define POWER_STRIP_PAD_CTRL_FOR25M_BOFFSET 3 -#define POWER_STRIP_PAD_CTRL_FOR25M_BLEN 2 -#define POWER_STRIP_PAD_CTRL_FOR25M_FLAG HSL_RW - -#define PAD_CTRL -#define POWER_STRIP_PAD_CTRL_BOFFSET 0 -#define POWER_STRIP_PAD_CTRL_BLEN 2 -#define POWER_STRIP_PAD_CTRL_FLAG HSL_RW - - - - - /* Global Interrupt Status Register1 */ -#define GBL_INT_STATUS1 -#define GBL_INT_STATUS1_ID 1 -#define GBL_INT_STATUS1_OFFSET 0x0024 -#define GBL_INT_STATUS1_E_LENGTH 4 -#define GBL_INT_STATUS1_E_OFFSET 0 -#define GBL_INT_STATUS1_NR_E 1 - -#define LINK_CHG_INT_S -#define GBL_INT_STATUS1_LINK_CHG_INT_S_BOFFSET 1 -#define GBL_INT_STATUS1_LINK_CHG_INT_S_BLEN 7 -#define GBL_INT_STATUS1_LINK_CHG_INT_S_FLAG HSL_RW - -#define PHY_INT_S -#define GBL_INT_STATUS1_PHY_INT_S_BOFFSET 15 -#define GBL_INT_STATUS1_PHY_INT_S_BLEN 1 -#define GBL_INT_STATUS1_PHY_INT_S_FLAG HSL_RO - - - - - /* Global Interrupt Mask Register1 */ -#define GBL_INT_MASK1 -#define GBL_INT_MASK1_ID 1 -#define GBL_INT_MASK1_OFFSET 0x002c -#define GBL_INT_MASK1_E_LENGTH 4 -#define GBL_INT_MASK1_E_OFFSET 0 -#define GBL_INT_MASK1_NR_E 1 - -#define LINK_CHG_INT_M -#define GBL_INT_MASK1_LINK_CHG_INT_M_BOFFSET 1 -#define GBL_INT_MASK1_LINK_CHG_INT_M_BLEN 7 -#define GBL_INT_MASK1_LINK_CHG_INT_M_FLAG HSL_RW - -#define PHY_INT_M -#define GBL_INT_MASK1_PHY_INT_M_BOFFSET 15 -#define GBL_INT_MASK1_PHY_INT_M_BLEN 1 -#define GBL_INT_MASK1_PHY_INT_M_FLAG HSL_RO - - - - - /* Module Enable Register */ -#define MOD_ENABLE -#define MOD_ENABLE_OFFSET 0x0030 -#define MOD_ENABLE_E_LENGTH 4 -#define MOD_ENABLE_E_OFFSET 0 -#define MOD_ENABLE_NR_E 1 - -#define L3_EN -#define MOD_ENABLE_L3_EN_BOFFSET 2 -#define MOD_ENABLE_L3_EN_BLEN 1 -#define MOD_ENABLE_L3_EN_FLAG HSL_RW - -#define ACL_EN -#define MOD_ENABLE_ACL_EN_BOFFSET 1 -#define MOD_ENABLE_ACL_EN_BLEN 1 -#define MOD_ENABLE_ACL_EN_FLAG HSL_RW - -#define MIB_EN -#define MOD_ENABLE_MIB_EN_BOFFSET 0 -#define MOD_ENABLE_MIB_EN_BLEN 1 -#define MOD_ENABLE_MIB_EN_FLAG HSL_RW - - - - - /* MIB Function Register */ -#define MIB_FUNC -#define MIB_FUNC_OFFSET 0x0034 -#define MIB_FUNC_E_LENGTH 4 -#define MIB_FUNC_E_OFFSET 0 -#define MIB_FUNC_NR_E 1 - -#define MIB_FUN -#define MIB_FUNC_MIB_FUN_BOFFSET 24 -#define MIB_FUNC_MIB_FUN_BLEN 3 -#define MIB_FUNC_MIB_FUN_FLAG HSL_RW - -#define MIB_FLUSH_PORT -#define MIB_FUNC_MIB_FLUSH_PORT_BOFFSET 21 -#define MIB_FUNC_MIB_FLUSH_PORT_BLEN 3 -#define MIB_FUNC_MIB_FLUSH_PORT_FLAG HSL_RW - -#define MIB_CPU_KEEP -#define MIB_FUNC_MIB_CPU_KEEP_BOFFSET 20 -#define MIB_FUNC_MIB_CPU_KEEP_BLEN 1 -#define MIB_FUNC_MIB_CPU_KEEP_FLAG HSL_RW - -#define MIB_BUSY -#define MIB_FUNC_MIB_BUSY_BOFFSET 17 -#define MIB_FUNC_MIB_BUSY_BLEN 1 -#define MIB_FUNC_MIB_BUSY_FLAG HSL_RW - -#define MIB_AT_HALF_EN -#define MIB_FUNC_MIB_AT_HALF_EN_BOFFSET 16 -#define MIB_FUNC_MIB_AT_HALF_EN_BLEN 1 -#define MIB_FUNC_MIB_AT_HALF_EN_FLAG HSL_RW - -#define MIB_TIMER -#define MIB_FUNC_MIB_TIMER_BOFFSET 0 -#define MIB_FUNC_MIB_TIMER_BLEN 16 -#define MIB_FUNC_MIB_TIMER_FLAG HSL_RW - - - - - /* Service tag Register */ -#define SERVICE_TAG -#define SERVICE_TAG_OFFSET 0x0048 -#define SERVICE_TAG_E_LENGTH 4 -#define SERVICE_TAG_E_OFFSET 0 -#define SERVICE_TAG_NR_E 1 - -#define STAG_MODE -#define SERVICE_TAG_STAG_MODE_BOFFSET 17 -#define SERVICE_TAG_STAG_MODE_BLEN 1 -#define SERVICE_TAG_STAG_MODE_FLAG HSL_RW - -#define TAG_VALUE -#define SERVICE_TAG_TAG_VALUE_BOFFSET 0 -#define SERVICE_TAG_TAG_VALUE_BLEN 16 -#define SERVICE_TAG_TAG_VALUE_FLAG HSL_RW - - - - - /* Global MAC Address Register */ -#define GLOBAL_MAC_ADDR0 -#define GLOBAL_MAC_ADDR0_OFFSET 0x0060 -#define GLOBAL_MAC_ADDR0_E_LENGTH 4 -#define GLOBAL_MAC_ADDR0_E_OFFSET 0 -#define GLOBAL_MAC_ADDR0_NR_E 1 - -#define GLB_BYTE4 -#define GLOBAL_MAC_ADDR0_GLB_BYTE4_BOFFSET 8 -#define GLOBAL_MAC_ADDR0_GLB_BYTE4_BLEN 8 -#define GLOBAL_MAC_ADDR0_GLB_BYTE4_FLAG HSL_RW - -#define GLB_BYTE5 -#define GLOBAL_MAC_ADDR0_GLB_BYTE5_BOFFSET 0 -#define GLOBAL_MAC_ADDR0_GLB_BYTE5_BLEN 8 -#define GLOBAL_MAC_ADDR0_GLB_BYTE5_FLAG HSL_RW - -#define GLOBAL_MAC_ADDR1 -#define GLOBAL_MAC_ADDR1_ID 4 -#define GLOBAL_MAC_ADDR1_OFFSET 0x0064 -#define GLOBAL_MAC_ADDR1_E_LENGTH 4 -#define GLOBAL_MAC_ADDR1_E_OFFSET 0 -#define GLOBAL_MAC_ADDR1_NR_E 1 - -#define GLB_BYTE0 -#define GLOBAL_MAC_ADDR1_GLB_BYTE0_BOFFSET 24 -#define GLOBAL_MAC_ADDR1_GLB_BYTE0_BLEN 8 -#define GLOBAL_MAC_ADDR1_GLB_BYTE0_FLAG HSL_RW - -#define GLB_BYTE1 -#define GLOBAL_MAC_ADDR1_GLB_BYTE1_BOFFSET 16 -#define GLOBAL_MAC_ADDR1_GLB_BYTE1_BLEN 8 -#define GLOBAL_MAC_ADDR1_GLB_BYTE1_FLAG HSL_RW - -#define GLB_BYTE2 -#define GLOBAL_MAC_ADDR1_GLB_BYTE2_BOFFSET 8 -#define GLOBAL_MAC_ADDR1_GLB_BYTE2_BLEN 8 -#define GLOBAL_MAC_ADDR1_GLB_BYTE2_FLAG HSL_RW - -#define GLB_BYTE3 -#define GLOBAL_MAC_ADDR1_GLB_BYTE3_BOFFSET 0 -#define GLOBAL_MAC_ADDR1_GLB_BYTE3_BLEN 8 -#define GLOBAL_MAC_ADDR1_GLB_BYTE3_FLAG HSL_RW - - - - - /* Max Size Register */ -#define MAX_SIZE -#define MAX_SIZE_OFFSET 0x0078 -#define MAX_SIZE_E_LENGTH 4 -#define MAX_SIZE_E_OFFSET 0 -#define MAX_SIZE_NR_E 1 - -#define MAX_FRAME_SIZE -#define MAX_SIZE_MAX_FRAME_SIZE_BOFFSET 0 -#define MAX_SIZE_MAX_FRAME_SIZE_BLEN 14 -#define MAX_SIZE_MAX_FRAME_SIZE_FLAG HSL_RW - - - - - /* Flow Control Register */ -#define FLOW_CTL0 "fctl" -#define FLOW_CTL0_ID 6 -#define FLOW_CTL0_OFFSET 0x0034 -#define FLOW_CTL0_E_LENGTH 4 -#define FLOW_CTL0_E_OFFSET 0 -#define FLOW_CTL0_NR_E 1 - -#define TEST_PAUSE "fctl_tps" -#define FLOW_CTL0_TEST_PAUSE_BOFFSET 31 -#define FLOW_CTL0_TEST_PAUSE_BLEN 1 -#define FLOW_CTL0_TEST_PAUSE_FLAG HSL_RW - - -#define GOL_PAUSE_ON_THRES "fctl_gont" -#define FLOW_CTL0_GOL_PAUSE_ON_THRES_BOFFSET 16 -#define FLOW_CTL0_GOL_PAUSE_ON_THRES_BLEN 8 -#define FLOW_CTL0_GOL_PAUSE_ON_THRES_FLAG HSL_RW - -#define GOL_PAUSE_OFF_THRES "fctl_gofft" -#define FLOW_CTL0_GOL_PAUSE_OFF_THRES_BOFFSET 0 -#define FLOW_CTL0_GOL_PAUSE_OFF_THRES_BLEN 8 -#define FLOW_CTL0_GOL_PAUSE_OFF_THRES_FLAG HSL_RW - - - - - /* Flow Control1 Register */ -#define FLOW_CTL1 "fctl1" -#define FLOW_CTL1_ID 6 -#define FLOW_CTL1_OFFSET 0x0038 -#define FLOW_CTL1_E_LENGTH 4 -#define FLOW_CTL1_E_OFFSET 0 -#define FLOW_CTL1_NR_E 1 - -#define PORT_PAUSE_ON_THRES "fctl1_pont" -#define FLOW_CTL1_PORT_PAUSE_ON_THRES_BOFFSET 16 -#define FLOW_CTL1_PORT_PAUSE_ON_THRES_BLEN 8 -#define FLOW_CTL1_PORT_PAUSE_ON_THRES_FLAG HSL_RW - -#define PORT_PAUSE_OFF_THRES "fctl1_pofft" -#define FLOW_CTL1_PORT_PAUSE_OFF_THRES_BOFFSET 0 -#define FLOW_CTL1_PORT_PAUSE_OFF_THRES_BLEN 8 -#define FLOW_CTL1_PORT_PAUSE_OFF_THRES_FLAG HSL_RW - - - - - /* Port Status Register */ -#define PORT_STATUS -#define PORT_STATUS_OFFSET 0x007c -#define PORT_STATUS_E_LENGTH 4 -#define PORT_STATUS_E_OFFSET 0x0004 -#define PORT_STATUS_NR_E 7 - -#define FLOW_LINK_EN -#define PORT_STATUS_FLOW_LINK_EN_BOFFSET 12 -#define PORT_STATUS_FLOW_LINK_EN_BLEN 1 -#define PORT_STATUS_FLOW_LINK_EN_FLAG HSL_RW - -#define AUTO_RX_FLOW -#define PORT_STATUS_AUTO_RX_FLOW_BOFFSET 11 -#define PORT_STATUS_AUTO_RX_FLOW_BLEN 1 -#define PORT_STATUS_AUTO_RX_FLOW_FLAG HSL_RO - -#define AUTO_TX_FLOW -#define PORT_STATUS_AUTO_TX_FLOW_BOFFSET 10 -#define PORT_STATUS_AUTO_TX_FLOW_BLEN 1 -#define PORT_STATUS_AUTO_TX_FLOW_FLAG HSL_RO - -#define LINK_EN -#define PORT_STATUS_LINK_EN_BOFFSET 9 -#define PORT_STATUS_LINK_EN_BLEN 1 -#define PORT_STATUS_LINK_EN_FLAG HSL_RW - -#define LINK -#define PORT_STATUS_LINK_BOFFSET 8 -#define PORT_STATUS_LINK_BLEN 1 -#define PORT_STATUS_LINK_FLAG HSL_RO - -#define TX_HALF_FLOW_EN -#define PORT_STATUS_TX_HALF_FLOW_EN_BOFFSET 7 -#define PORT_STATUS_TX_HALF_FLOW_EN_BLEN 1 -#define PORT_STATUS_TX_HALF_FLOW_EN_FLAG HSL_RW - -#define DUPLEX_MODE -#define PORT_STATUS_DUPLEX_MODE_BOFFSET 6 -#define PORT_STATUS_DUPLEX_MODE_BLEN 1 -#define PORT_STATUS_DUPLEX_MODE_FLAG HSL_RW - -#define RX_FLOW_EN -#define PORT_STATUS_RX_FLOW_EN_BOFFSET 5 -#define PORT_STATUS_RX_FLOW_EN_BLEN 1 -#define PORT_STATUS_RX_FLOW_EN_FLAG HSL_RW - -#define TX_FLOW_EN -#define PORT_STATUS_TX_FLOW_EN_BOFFSET 4 -#define PORT_STATUS_TX_FLOW_EN_BLEN 1 -#define PORT_STATUS_TX_FLOW_EN_FLAG HSL_RW - -#define RXMAC_EN -#define PORT_STATUS_RXMAC_EN_BOFFSET 3 -#define PORT_STATUS_RXMAC_EN_BLEN 1 -#define PORT_STATUS_RXMAC_EN_FLAG HSL_RW - -#define TXMAC_EN -#define PORT_STATUS_TXMAC_EN_BOFFSET 2 -#define PORT_STATUS_TXMAC_EN_BLEN 1 -#define PORT_STATUS_TXMAC_EN_FLAG HSL_RW - -#define SPEED_MODE -#define PORT_STATUS_SPEED_MODE_BOFFSET 0 -#define PORT_STATUS_SPEED_MODE_BLEN 2 -#define PORT_STATUS_SPEED_MODE_FLAG HSL_RW - - - - - /* Header Ctl Register */ -#define HEADER_CTL -#define HEADER_CTL_OFFSET 0x0098 -#define HEADER_CTL_E_LENGTH 4 -#define HEADER_CTL_E_OFFSET 0x0004 -#define HEADER_CTL_NR_E 1 - -#define TYPE_LEN -#define HEADER_CTL_TYPE_LEN_BOFFSET 16 -#define HEADER_CTL_TYPE_LEN_BLEN 1 -#define HEADER_CTL_TYPE_LEN_FLAG HSL_RW - -#define TYPE_VAL -#define HEADER_CTL_TYPE_VAL_BOFFSET 0 -#define HEADER_CTL_TYPE_VAL_BLEN 16 -#define HEADER_CTL_TYPE_VAL_FLAG HSL_RW - - - - - /* Port Header Ctl Register */ -#define PORT_HDR_CTL -#define PORT_HDR_CTL_OFFSET 0x009c -#define PORT_HDR_CTL_E_LENGTH 4 -#define PORT_HDR_CTL_E_OFFSET 0x0004 -#define PORT_HDR_CTL_NR_E 7 - -#define IPG_DEC_EN -#define PORT_HDR_CTL_IPG_DEC_EN_BOFFSET 5 -#define PORT_HDR_CTL_IPG_DEC_EN_BLEN 1 -#define PORT_HDR_CTL_IPG_DEC_EN_FLAG HSL_RW - -#define LOOPBACK_EN -#define PORT_HDR_CTL_LOOPBACK_EN_BOFFSET 4 -#define PORT_HDR_CTL_LOOPBACK_EN_BLEN 1 -#define PORT_HDR_CTL_LOOPBACK_EN_FLAG HSL_RW - -#define RXHDR_MODE -#define PORT_HDR_CTL_RXHDR_MODE_BOFFSET 2 -#define PORT_HDR_CTL_RXHDR_MODE_BLEN 2 -#define PORT_HDR_CTL_RXHDR_MODE_FLAG HSL_RW - -#define TXHDR_MODE -#define PORT_HDR_CTL_TXHDR_MODE_BOFFSET 0 -#define PORT_HDR_CTL_TXHDR_MODE_BLEN 2 -#define PORT_HDR_CTL_TXHDR_MODE_FLAG HSL_RW - - - - - /* EEE control Register */ -#define EEE_CTL -#define EEE_CTL_OFFSET 0x0100 -#define EEE_CTL_E_LENGTH 4 -#define EEE_CTL_E_OFFSET 0 -#define EEE_CTL_NR_E 1 - -#define LPI_STATE_REMAP_EN_5 -#define EEE_CTL_LPI_STATE_REMAP_EN_5_BOFFSET 13 -#define EEE_CTL_LPI_STATE_REMAP_EN_5_BLEN 1 -#define EEE_CTL_LPI_STATE_REMAP_EN_5_FLAG HSL_RW - -#define LPI_EN_5 -#define EEE_CTL_LPI_EN_5_BOFFSET 12 -#define EEE_CTL_LPI_EN_5_BLEN 1 -#define EEE_CTL_LPI_EN_5_FLAG HSL_RW - -#define LPI_STATE_REMAP_EN_4 -#define EEE_CTL_LPI_STATE_REMAP_EN_4_BOFFSET 11 -#define EEE_CTL_LPI_STATE_REMAP_EN_4_BLEN 1 -#define EEE_CTL_LPI_STATE_REMAP_EN_4_FLAG HSL_RW - -#define LPI_EN_4 -#define EEE_CTL_LPI_EN_4_BOFFSET 10 -#define EEE_CTL_LPI_EN_4_BLEN 1 -#define EEE_CTL_LPI_EN_4_FLAG HSL_RW - -#define LPI_STATE_REMAP_EN_3 -#define EEE_CTL_LPI_STATE_REMAP_EN_3_BOFFSET 9 -#define EEE_CTL_LPI_STATE_REMAP_EN_3_BLEN 1 -#define EEE_CTL_LPI_STATE_REMAP_EN_3_FLAG HSL_RW - -#define LPI_EN_3 -#define EEE_CTL_LPI_EN_3_BOFFSET 8 -#define EEE_CTL_LPI_EN_3_BLEN 1 -#define EEE_CTL_LPI_EN_3_FLAG HSL_RW - -#define LPI_STATE_REMAP_EN_2 -#define EEE_CTL_LPI_STATE_REMAP_EN_2_BOFFSET 7 -#define EEE_CTL_LPI_STATE_REMAP_EN_2_BLEN 1 -#define EEE_CTL_LPI_STATE_REMAP_EN_2_FLAG HSL_RW - -#define LPI_EN_2 -#define EEE_CTL_LPI_EN_2_BOFFSET 6 -#define EEE_CTL_LPI_EN_2_BLEN 1 -#define EEE_CTL_LPI_EN_2_FLAG HSL_RW - -#define LPI_STATE_REMAP_EN_1 -#define EEE_CTL_LPI_STATE_REMAP_EN_1_BOFFSET 5 -#define EEE_CTL_LPI_STATE_REMAP_EN_1_BLEN 1 -#define EEE_CTL_LPI_STATE_REMAP_EN_1_FLAG HSL_RW - -#define LPI_EN_1 -#define EEE_CTL_LPI_EN_1_BOFFSET 4 -#define EEE_CTL_LPI_EN_1_BLEN 1 -#define EEE_CTL_LPI_EN_1_FLAG HSL_RW - - - - - /* Frame Ack Ctl0 Register */ -#define FRAME_ACK_CTL0 -#define FRAME_ACK_CTL0_OFFSET 0x0210 -#define FRAME_ACK_CTL0_E_LENGTH 4 -#define FRAME_ACK_CTL0_E_OFFSET 0 -#define FRAME_ACK_CTL0_NR_E 1 - -#define ARP_REQ_EN -#define FRAME_ACK_CTL0_ARP_REQ_EN_BOFFSET 6 -#define FRAME_ACK_CTL0_ARP_REQ_EN_BLEN 1 -#define FRAME_ACK_CTL0_ARP_REQ_EN_FLAG HSL_RW - -#define ARP_REP_EN -#define FRAME_ACK_CTL0_ARP_REP_EN_BOFFSET 5 -#define FRAME_ACK_CTL0_ARP_REP_EN_BLEN 1 -#define FRAME_ACK_CTL0_ARP_REP_EN_FLAG HSL_RW - -#define DHCP_EN -#define FRAME_ACK_CTL0_DHCP_EN_BOFFSET 4 -#define FRAME_ACK_CTL0_DHCP_EN_BLEN 1 -#define FRAME_ACK_CTL0_DHCP_EN_FLAG HSL_RW - -#define EAPOL_EN -#define FRAME_ACK_CTL0_EAPOL_EN_BOFFSET 3 -#define FRAME_ACK_CTL0_EAPOL_EN_BLEN 1 -#define FRAME_ACK_CTL0_EAPOL_EN_FLAG HSL_RW - -#define LEAVE_EN -#define FRAME_ACK_CTL0_LEAVE_EN_BOFFSET 2 -#define FRAME_ACK_CTL0_LEAVE_EN_BLEN 1 -#define FRAME_ACK_CTL0_LEAVE_EN_FLAG HSL_RW - -#define JOIN_EN -#define FRAME_ACK_CTL0_JOIN_EN_BOFFSET 1 -#define FRAME_ACK_CTL0_JOIN_EN_BLEN 1 -#define FRAME_ACK_CTL0_JOIN_EN_FLAG HSL_RW - -#define IGMP_MLD_EN -#define FRAME_ACK_CTL0_IGMP_MLD_EN_BOFFSET 0 -#define FRAME_ACK_CTL0_IGMP_MLD_EN_BLEN 1 -#define FRAME_ACK_CTL0_IGMP_MLD_EN_FLAG HSL_RW - - - - - /* Frame Ack Ctl1 Register */ -#define FRAME_ACK_CTL1 -#define FRAME_ACK_CTL1_OFFSET 0x0214 -#define FRAME_ACK_CTL1_E_LENGTH 4 -#define FRAME_ACK_CTL1_E_OFFSET 0 -#define FRAME_ACK_CTL1_NR_E 1 - -#define PPPOE_EN -#define FRAME_ACK_CTL1_PPPOE_EN_BOFFSET 25 -#define FRAME_ACK_CTL1_PPPOE_EN_BLEN 1 -#define FRAME_ACK_CTL1_PPPOE_EN_FLAG HSL_RW - -#define IGMP_V3_EN -#define FRAME_ACK_CTL1_IGMP_V3_EN_BOFFSET 24 -#define FRAME_ACK_CTL1_IGMP_V3_EN_BLEN 1 -#define FRAME_ACK_CTL1_IGMP_V3_EN_FLAG HSL_RW - - - - - /* Window Rule Ctl0 Register */ -#define WIN_RULE_CTL0 -#define WIN_RULE_CTL0_OFFSET 0x0218 -#define WIN_RULE_CTL0_E_LENGTH 4 -#define WIN_RULE_CTL0_E_OFFSET 0x4 -#define WIN_RULE_CTL0_NR_E 7 - -#define L4_LENGTH -#define WIN_RULE_CTL0_L4_LENGTH_BOFFSET 24 -#define WIN_RULE_CTL0_L4_LENGTH_BLEN 4 -#define WIN_RULE_CTL0_L4_LENGTH_FLAG HSL_RW - -#define L3_LENGTH -#define WIN_RULE_CTL0_L3_LENGTH_BOFFSET 20 -#define WIN_RULE_CTL0_L3_LENGTH_BLEN 4 -#define WIN_RULE_CTL0_L3_LENGTH_FLAG HSL_RW - -#define L2_LENGTH -#define WIN_RULE_CTL0_L2_LENGTH_BOFFSET 16 -#define WIN_RULE_CTL0_L2_LENGTH_BLEN 4 -#define WIN_RULE_CTL0_L2_LENGTH_FLAG HSL_RW - -#define L4_OFFSET -#define WIN_RULE_CTL0_L4_OFFSET_BOFFSET 10 -#define WIN_RULE_CTL0_L4_OFFSET_BLEN 5 -#define WIN_RULE_CTL0_L4_OFFSET_FLAG HSL_RW - -#define L3_OFFSET -#define WIN_RULE_CTL0_L3_OFFSET_BOFFSET 5 -#define WIN_RULE_CTL0_L3_OFFSET_BLEN 5 -#define WIN_RULE_CTL0_L3_OFFSET_FLAG HSL_RW - -#define L2_OFFSET -#define WIN_RULE_CTL0_L2_OFFSET_BOFFSET 0 -#define WIN_RULE_CTL0_L2_OFFSET_BLEN 5 -#define WIN_RULE_CTL0_L2_OFFSET_FLAG HSL_RW - - - - - /* Window Rule Ctl1 Register */ -#define WIN_RULE_CTL1 -#define WIN_RULE_CTL1_OFFSET 0x0234 -#define WIN_RULE_CTL1_E_LENGTH 4 -#define WIN_RULE_CTL1_E_OFFSET 0x4 -#define WIN_RULE_CTL1_NR_E 7 - -#define L3P_LENGTH -#define WIN_RULE_CTL1_L3P_LENGTH_BOFFSET 20 -#define WIN_RULE_CTL1_L3P_LENGTH_BLEN 4 -#define WIN_RULE_CTL1_L3P_LENGTH_FLAG HSL_RW - -#define L2S_LENGTH -#define WIN_RULE_CTL1_L2S_LENGTH_BOFFSET 16 -#define WIN_RULE_CTL1_L2S_LENGTH_BLEN 4 -#define WIN_RULE_CTL1_L2S_LENGTH_FLAG HSL_RW - -#define L3P_OFFSET -#define WIN_RULE_CTL1_L3P_OFFSET_BOFFSET 5 -#define WIN_RULE_CTL1_L3P_OFFSET_BLEN 5 -#define WIN_RULE_CTL1_L3P_OFFSET_FLAG HSL_RW - -#define L2S_OFFSET -#define WIN_RULE_CTL1_L2S_OFFSET_BOFFSET 0 -#define WIN_RULE_CTL1_L2S_OFFSET_BLEN 5 -#define WIN_RULE_CTL1_L2S_OFFSET_FLAG HSL_RW - - - - - /* Trunk Hash Mode Register */ -#define TRUNK_HASH_MODE -#define TRUNK_HASH_MODE_OFFSET 0x0270 -#define TRUNK_HASH_MODE_E_LENGTH 4 -#define TRUNK_HASH_MODE_E_OFFSET 0x4 -#define TRUNK_HASH_MODE_NR_E 1 - -#define SIP_EN -#define TRUNK_HASH_MODE_SIP_EN_BOFFSET 3 -#define TRUNK_HASH_MODE_SIP_EN_BLEN 1 -#define TRUNK_HASH_MODE_SIP_EN_FLAG HSL_RW - -#define DIP_EN -#define TRUNK_HASH_MODE_DIP_EN_BOFFSET 2 -#define TRUNK_HASH_MODE_DIP_EN_BLEN 1 -#define TRUNK_HASH_MODE_DIP_EN_FLAG HSL_RW - -#define SA_EN -#define TRUNK_HASH_MODE_SA_EN_BOFFSET 1 -#define TRUNK_HASH_MODE_SA_EN_BLEN 1 -#define TRUNK_HASH_MODE_SA_EN_FLAG HSL_RW - -#define DA_EN -#define TRUNK_HASH_MODE_DA_EN_BOFFSET 0 -#define TRUNK_HASH_MODE_DA_EN_BLEN 1 -#define TRUNK_HASH_MODE_DA_EN_FLAG HSL_RW - - - - - /* Vlan Table Function0 Register */ -#define VLAN_TABLE_FUNC0 -#define VLAN_TABLE_FUNC0_OFFSET 0x0610 -#define VLAN_TABLE_FUNC0_E_LENGTH 4 -#define VLAN_TABLE_FUNC0_E_OFFSET 0 -#define VLAN_TABLE_FUNC0_NR_E 1 - -#define VT_VALID -#define VLAN_TABLE_FUNC0_VT_VALID_BOFFSET 20 -#define VLAN_TABLE_FUNC0_VT_VALID_BLEN 1 -#define VLAN_TABLE_FUNC0_VT_VALID_FLAG HSL_RW - -#define IVL_EN -#define VLAN_TABLE_FUNC0_IVL_EN_BOFFSET 19 -#define VLAN_TABLE_FUNC0_IVL_EN_BLEN 1 -#define VLAN_TABLE_FUNC0_IVL_EN_FLAG HSL_RW - -#define LEARN_DIS -#define VLAN_TABLE_FUNC0_LEARN_DIS_BOFFSET 18 -#define VLAN_TABLE_FUNC0_LEARN_DIS_BLEN 1 -#define VLAN_TABLE_FUNC0_LEARN_DIS_FLAG HSL_RW - -#define VID_MEM -#define VLAN_TABLE_FUNC0_VID_MEM_BOFFSET 4 -#define VLAN_TABLE_FUNC0_VID_MEM_BLEN 14 -#define VLAN_TABLE_FUNC0_VID_MEM_FLAG HSL_RW - -#define VT_PRI_EN -#define VLAN_TABLE_FUNC0_VT_PRI_EN_BOFFSET 3 -#define VLAN_TABLE_FUNC0_VT_PRI_EN_BLEN 1 -#define VLAN_TABLE_FUNC0_VT_PRI_EN_FLAG HSL_RW - -#define VT_PRI -#define VLAN_TABLE_FUNC0_VT_PRI_BOFFSET 0 -#define VLAN_TABLE_FUNC0_VT_PRI_BLEN 3 -#define VLAN_TABLE_FUNC0_VT_PRI_FLAG HSL_RW - - /* Vlan Table Function1 Register */ -#define VLAN_TABLE_FUNC1 -#define VLAN_TABLE_FUNC1_OFFSET 0x0614 -#define VLAN_TABLE_FUNC1_E_LENGTH 4 -#define VLAN_TABLE_FUNC1_E_OFFSET 0 -#define VLAN_TABLE_FUNC1_NR_E 1 - -#define VT_BUSY -#define VLAN_TABLE_FUNC1_VT_BUSY_BOFFSET 31 -#define VLAN_TABLE_FUNC1_VT_BUSY_BLEN 1 -#define VLAN_TABLE_FUNC1_VT_BUSY_FLAG HSL_RW - -#define VLAN_ID -#define VLAN_TABLE_FUNC1_VLAN_ID_BOFFSET 16 -#define VLAN_TABLE_FUNC1_VLAN_ID_BLEN 12 -#define VLAN_TABLE_FUNC1_VLAN_ID_FLAG HSL_RW - -#define VT_PORT_NUM -#define VLAN_TABLE_FUNC1_VT_PORT_NUM_BOFFSET 8 -#define VLAN_TABLE_FUNC1_VT_PORT_NUM_BLEN 4 -#define VLAN_TABLE_FUNC1_VT_PORT_NUM_FLAG HSL_RW - -#define VT_FULL_VIO -#define VLAN_TABLE_FUNC1_VT_FULL_VIO_BOFFSET 4 -#define VLAN_TABLE_FUNC1_VT_FULL_VIO_BLEN 1 -#define VLAN_TABLE_FUNC1_VT_FULL_VIO_FLAG HSL_RW - -#define VT_FUNC -#define VLAN_TABLE_FUNC1_VT_FUNC_BOFFSET 0 -#define VLAN_TABLE_FUNC1_VT_FUNC_BLEN 3 -#define VLAN_TABLE_FUNC1_VT_FUNC_FLAG HSL_RW - - - - - /* Address Table Function0 Register */ -#define ADDR_TABLE_FUNC0 -#define ADDR_TABLE_FUNC0_OFFSET 0x0600 -#define ADDR_TABLE_FUNC0_E_LENGTH 4 -#define ADDR_TABLE_FUNC0_E_OFFSET 0 -#define ADDR_TABLE_FUNC0_NR_E 1 - - -#define AT_ADDR_BYTE2 -#define ADDR_TABLE_FUNC0_AT_ADDR_BYTE2_BOFFSET 24 -#define ADDR_TABLE_FUNC0_AT_ADDR_BYTE2_BLEN 8 -#define ADDR_TABLE_FUNC0_AT_ADDR_BYTE2_FLAG HSL_RW - -#define AT_ADDR_BYTE3 -#define ADDR_TABLE_FUNC0_AT_ADDR_BYTE3_BOFFSET 16 -#define ADDR_TABLE_FUNC0_AT_ADDR_BYTE3_BLEN 8 -#define ADDR_TABLE_FUNC0_AT_ADDR_BYTE3_FLAG HSL_RW - -#define AT_ADDR_BYTE4 -#define ADDR_TABLE_FUNC0_AT_ADDR_BYTE4_BOFFSET 8 -#define ADDR_TABLE_FUNC0_AT_ADDR_BYTE4_BLEN 8 -#define ADDR_TABLE_FUNC0_AT_ADDR_BYTE4_FLAG HSL_RW - -#define AT_ADDR_BYTE5 -#define ADDR_TABLE_FUNC0_AT_ADDR_BYTE5_BOFFSET 0 -#define ADDR_TABLE_FUNC0_AT_ADDR_BYTE5_BLEN 8 -#define ADDR_TABLE_FUNC0_AT_ADDR_BYTE5_FLAG HSL_RW - - /* Address Table Function1 Register */ -#define ADDR_TABLE_FUNC1 -#define ADDR_TABLE_FUNC1_OFFSET 0x0604 -#define ADDR_TABLE_FUNC1_E_LENGTH 4 -#define ADDR_TABLE_FUNC1_E_OFFSET 0 -#define ADDR_TABLE_FUNC1_NR_E 1 - -#define SA_DROP_EN -#define ADDR_TABLE_FUNC1_SA_DROP_EN_BOFFSET 30 -#define ADDR_TABLE_FUNC1_SA_DROP_EN_BLEN 1 -#define ADDR_TABLE_FUNC1_SA_DROP_EN_FLAG HSL_RW - -#define MIRROR_EN -#define ADDR_TABLE_FUNC1_MIRROR_EN_BOFFSET 29 -#define ADDR_TABLE_FUNC1_MIRROR_EN_BLEN 1 -#define ADDR_TABLE_FUNC1_MIRROR_EN_FLAG HSL_RW - -#define AT_PRI_EN -#define ADDR_TABLE_FUNC1_AT_PRI_EN_BOFFSET 28 -#define ADDR_TABLE_FUNC1_AT_PRI_EN_BLEN 1 -#define ADDR_TABLE_FUNC1_AT_PRI_EN_FLAG HSL_RW - -#define AT_SVL_EN -#define ADDR_TABLE_FUNC1_AT_SVL_EN_BOFFSET 27 -#define ADDR_TABLE_FUNC1_AT_SVL_EN_BLEN 1 -#define ADDR_TABLE_FUNC1_AT_SVL_EN_FLAG HSL_RW - -#define AT_PRI -#define ADDR_TABLE_FUNC1_AT_PRI_BOFFSET 24 -#define ADDR_TABLE_FUNC1_AT_PRI_BLEN 3 -#define ADDR_TABLE_FUNC1_AT_PRI_FLAG HSL_RW - -#define CROSS_PT -#define ADDR_TABLE_FUNC1_CROSS_PT_BOFFSET 23 -#define ADDR_TABLE_FUNC1_CROSS_PT_BLEN 1 -#define ADDR_TABLE_FUNC1_CROSS_PT_FLAG HSL_RW - -#define DES_PORT -#define ADDR_TABLE_FUNC1_DES_PORT_BOFFSET 16 -#define ADDR_TABLE_FUNC1_DES_PORT_BLEN 7 -#define ADDR_TABLE_FUNC1_DES_PORT_FLAG HSL_RW - -#define AT_ADDR_BYTE0 -#define ADDR_TABLE_FUNC1_AT_ADDR_BYTE0_BOFFSET 8 -#define ADDR_TABLE_FUNC1_AT_ADDR_BYTE0_BLEN 8 -#define ADDR_TABLE_FUNC1_AT_ADDR_BYTE0_FLAG HSL_RW - -#define AT_ADDR_BYTE1 -#define ADDR_TABLE_FUNC1_AT_ADDR_BYTE1_BOFFSET 0 -#define ADDR_TABLE_FUNC1_AT_ADDR_BYTE1_BLEN 8 -#define ADDR_TABLE_FUNC1_AT_ADDR_BYTE1_FLAG HSL_RW - - /* Address Table Function2 Register */ -#define ADDR_TABLE_FUNC2 -#define ADDR_TABLE_FUNC2_OFFSET 0x0608 -#define ADDR_TABLE_FUNC2_E_LENGTH 4 -#define ADDR_TABLE_FUNC2_E_OFFSET 0 -#define ADDR_TABLE_FUNC2_NR_E 1 - -#define WL_EN -#define ADDR_TABLE_FUNC2_WL_EN_BOFFSET 20 -#define ADDR_TABLE_FUNC2_WL_EN_BLEN 1 -#define ADDR_TABLE_FUNC2_WL_EN_FLAG HSL_RW - -#define AT_VID -#define ADDR_TABLE_FUNC2_AT_VID_BOFFSET 8 -#define ADDR_TABLE_FUNC2_AT_VID_BLEN 12 -#define ADDR_TABLE_FUNC2_AT_VID_FLAG HSL_RW - -#define SHORT_LOOP -#define ADDR_TABLE_FUNC2_SHORT_LOOP_BOFFSET 7 -#define ADDR_TABLE_FUNC2_SHORT_LOOP_BLEN 1 -#define ADDR_TABLE_FUNC2_SHORT_LOOP_FLAG HSL_RW - -#define COPY_TO_CPU -#define ADDR_TABLE_FUNC2_COPY_TO_CPU_BOFFSET 6 -#define ADDR_TABLE_FUNC2_COPY_TO_CPU_BLEN 1 -#define ADDR_TABLE_FUNC2_COPY_TO_CPU_FLAG HSL_RW - -#define REDRCT_TO_CPU -#define ADDR_TABLE_FUNC2_REDRCT_TO_CPU_BOFFSET 5 -#define ADDR_TABLE_FUNC2_REDRCT_TO_CPU_BLEN 1 -#define ADDR_TABLE_FUNC2_REDRCT_TO_CPU_FLAG HSL_RW - -#define LEAKY_EN -#define ADDR_TABLE_FUNC2_LEAKY_EN_BOFFSET 4 -#define ADDR_TABLE_FUNC2_LEAKY_EN_BLEN 1 -#define ADDR_TABLE_FUNC2_LEAKY_EN_FLAG HSL_RW - -#define AT_STATUS -#define ADDR_TABLE_FUNC2_AT_STATUS_BOFFSET 0 -#define ADDR_TABLE_FUNC2_AT_STATUS_BLEN 4 -#define ADDR_TABLE_FUNC2_AT_STATUS_FLAG HSL_RW - - /* Address Table Function3 Register */ -#define ADDR_TABLE_FUNC3 -#define ADDR_TABLE_FUNC3_OFFSET 0x060c -#define ADDR_TABLE_FUNC3_E_LENGTH 4 -#define ADDR_TABLE_FUNC3_E_OFFSET 0 -#define ADDR_TABLE_FUNC3_NR_E 1 - -#define AT_BUSY -#define ADDR_TABLE_FUNC3_AT_BUSY_BOFFSET 31 -#define ADDR_TABLE_FUNC3_AT_BUSY_BLEN 1 -#define ADDR_TABLE_FUNC3_AT_BUSY_FLAG HSL_RW - -#define NEW_PORT_NUM -#define ADDR_TABLE_FUNC3_NEW_PORT_NUM_BOFFSET 22 -#define ADDR_TABLE_FUNC3_NEW_PORT_NUM_BLEN 3 -#define ADDR_TABLE_FUNC3_NEW_PORT_NUM_FLAG HSL_RW - -#define AT_INDEX -#define ADDR_TABLE_FUNC3_AT_INDEX_BOFFSET 16 -#define ADDR_TABLE_FUNC3_AT_INDEX_BLEN 5 -#define ADDR_TABLE_FUNC3_AT_INDEX_FLAG HSL_RW - -#define AT_VID_EN -#define ADDR_TABLE_FUNC3_AT_VID_EN_BOFFSET 15 -#define ADDR_TABLE_FUNC3_AT_VID_EN_BLEN 1 -#define ADDR_TABLE_FUNC3_AT_VID_EN_FLAG HSL_RW - -#define AT_PORT_EN -#define ADDR_TABLE_FUNC3_AT_PORT_EN_BOFFSET 14 -#define ADDR_TABLE_FUNC3_AT_PORT_EN_BLEN 1 -#define ADDR_TABLE_FUNC3_AT_PORT_EN_FLAG HSL_RW - -#define AT_MULTI_EN -#define ADDR_TABLE_FUNC3_AT_MULTI_EN_BOFFSET 13 -#define ADDR_TABLE_FUNC3_AT_MULTI_EN_BLEN 1 -#define ADDR_TABLE_FUNC3_AT_MULTI_EN_FLAG HSL_RW - -#define AT_FULL_VIO -#define ADDR_TABLE_FUNC3_AT_FULL_VIO_BOFFSET 12 -#define ADDR_TABLE_FUNC3_AT_FULL_VIO_BLEN 1 -#define ADDR_TABLE_FUNC3_AT_FULL_VIO_FLAG HSL_RW - -#define AT_PORT_NUM -#define ADDR_TABLE_FUNC3_AT_PORT_NUM_BOFFSET 8 -#define ADDR_TABLE_FUNC3_AT_PORT_NUM_BLEN 4 -#define ADDR_TABLE_FUNC3_AT_PORT_NUM_FLAG HSL_RW - -#define FLUSH_ST_EN -#define ADDR_TABLE_FUNC3_FLUSH_ST_EN_BOFFSET 4 -#define ADDR_TABLE_FUNC3_FLUSH_ST_EN_BLEN 1 -#define ADDR_TABLE_FUNC3_FLUSH_ST_EN_FLAG HSL_RW - -#define AT_FUNC -#define ADDR_TABLE_FUNC3_AT_FUNC_BOFFSET 0 -#define ADDR_TABLE_FUNC3_AT_FUNC_BLEN 4 -#define ADDR_TABLE_FUNC3_AT_FUNC_FLAG HSL_RW - - - - - /* Reserve Address Table0 Register */ -#define RESV_ADDR_TBL0 -#define RESV_ADDR_TBL0_OFFSET 0x3c000 -#define RESV_ADDR_TBL0_E_LENGTH 4 -#define RESV_ADDR_TBL0_E_OFFSET 0 -#define RESV_ADDR_TBL0_NR_E 1 - -#define RESV_ADDR_BYTE2 -#define RESV_ADDR_TBL0_RESV_ADDR_BYTE2_BOFFSET 24 -#define RESV_ADDR_TBL0_RESV_ADDR_BYTE2_BLEN 8 -#define RESV_ADDR_TBL0_RESV_ADDR_BYTE2_FLAG HSL_RW - -#define RESV_ADDR_BYTE3 -#define RESV_ADDR_TBL0_RESV_ADDR_BYTE3_BOFFSET 16 -#define RESV_ADDR_TBL0_RESV_ADDR_BYTE3_BLEN 8 -#define RESV_ADDR_TBL0_RESV_ADDR_BYTE3_FLAG HSL_RW - -#define RESV_ADDR_BYTE4 -#define RESV_ADDR_TBL0_RESV_ADDR_BYTE4_BOFFSET 8 -#define RESV_ADDR_TBL0_RESV_ADDR_BYTE4_BLEN 8 -#define RESV_ADDR_TBL0_RESV_ADDR_BYTE4_FLAG HSL_RW - -#define RESV_ADDR_BYTE5 -#define RESV_ADDR_TBL0_RESV_ADDR_BYTE5_BOFFSET 0 -#define RESV_ADDR_TBL0_RESV_ADDR_BYTE5_BLEN 8 -#define RESV_ADDR_TBL0_RESV_ADDR_BYTE5_FLAG HSL_RW - - /* Reserve Address Table1 Register */ -#define RESV_ADDR_TBL1 -#define RESV_ADDR_TBL1_OFFSET 0x3c004 -#define RESV_ADDR_TBL1_E_LENGTH 4 -#define RESV_ADDR_TBL1_E_OFFSET 0 -#define RESV_ADDR_TBL1_NR_E 1 - -#define RESV_COPY_TO_CPU -#define RESV_ADDR_TBL1_RESV_COPY_TO_CPU_BOFFSET 31 -#define RESV_ADDR_TBL1_RESV_COPY_TO_CPU_BLEN 1 -#define RESV_ADDR_TBL1_RESV_COPY_TO_CPU_FLAG HSL_RW - -#define RESV_REDRCT_TO_CPU -#define RESV_ADDR_TBL1_RESV_REDRCT_TO_CPU_BOFFSET 30 -#define RESV_ADDR_TBL1_RESV_REDRCT_TO_CPU_BLEN 1 -#define RESV_ADDR_TBL1_RESV_REDRCT_TO_CPU_FLAG HSL_RW - -#define RESV_LEAKY_EN -#define RESV_ADDR_TBL1_RESV_LEAKY_EN_BOFFSET 29 -#define RESV_ADDR_TBL1_RESV_LEAKY_EN_BLEN 1 -#define RESV_ADDR_TBL1_RESV_LEAKY_EN_FLAG HSL_RW - -#define RESV_MIRROR_EN -#define RESV_ADDR_TBL1_RESV_MIRROR_EN_BOFFSET 28 -#define RESV_ADDR_TBL1_RESV_MIRROR_EN_BLEN 1 -#define RESV_ADDR_TBL1_RESV_MIRROR_EN_FLAG HSL_RW - -#define RESV_PRI_EN -#define RESV_ADDR_TBL1_RESV_PRI_EN_BOFFSET 27 -#define RESV_ADDR_TBL1_RESV_PRI_EN_BLEN 1 -#define RESV_ADDR_TBL1_RESV_PRI_EN_FLAG HSL_RW - -#define RESV_PRI -#define RESV_ADDR_TBL1_RESV_PRI_BOFFSET 24 -#define RESV_ADDR_TBL1_RESV_PRI_BLEN 3 -#define RESV_ADDR_TBL1_RESV_PRI_FLAG HSL_RW - -#define RESV_CROSS_PT -#define RESV_ADDR_TBL1_RESV_CROSS_PT_BOFFSET 23 -#define RESV_ADDR_TBL1_RESV_CROSS_PT_BLEN 1 -#define RESV_ADDR_TBL1_RESV_CROSS_PT_FLAG HSL_RW - -#define RESV_DES_PORT -#define RESV_ADDR_TBL1_RESV_DES_PORT_BOFFSET 16 -#define RESV_ADDR_TBL1_RESV_DES_PORT_BLEN 7 -#define RESV_ADDR_TBL1_RESV_DES_PORT_FLAG HSL_RW - -#define RESV_ADDR_BYTE0 -#define RESV_ADDR_TBL1_RESV_ADDR_BYTE0_BOFFSET 8 -#define RESV_ADDR_TBL1_RESV_ADDR_BYTE0_BLEN 8 -#define RESV_ADDR_TBL1_RESV_ADDR_BYTE0_FLAG HSL_RW - -#define RESV_ADDR_BYTE1 -#define RESV_ADDR_TBL1_RESV_ADDR_BYTE1_BOFFSET 0 -#define RESV_ADDR_TBL1_RESV_ADDR_BYTE1_BLEN 8 -#define RESV_ADDR_TBL1_RESV_ADDR_BYTE1_FLAG HSL_RW - - /* Reserve Address Table2 Register */ -#define RESV_ADDR_TBL2 -#define RESV_ADDR_TBL2_OFFSET 0x3c008 -#define RESV_ADDR_TBL2_E_LENGTH 4 -#define RESV_ADDR_TBL2_E_OFFSET 0 -#define RESV_ADDR_TBL2_NR_E 1 - -#define RESV_STATUS -#define RESV_ADDR_TBL2_RESV_STATUS_BOFFSET 0 -#define RESV_ADDR_TBL2_RESV_STATUS_BLEN 1 -#define RESV_ADDR_TBL2_RESV_STATUS_FLAG HSL_RW - - - - - /* Address Table Control Register */ -#define ADDR_TABLE_CTL -#define ADDR_TABLE_CTL_OFFSET 0x0618 -#define ADDR_TABLE_CTL_E_LENGTH 4 -#define ADDR_TABLE_CTL_E_OFFSET 0 -#define ADDR_TABLE_CTL_NR_E 1 - -#define ARL_INI_EN -#define ADDR_TABLE_CTL_ARL_INI_EN_BOFFSET 31 -#define ADDR_TABLE_CTL_ARL_INI_EN_BLEN 1 -#define ADDR_TABLE_CTL_ARL_INI_EN_FLAG HSL_RW - -#define LEARN_CHANGE_EN -#define ADDR_TABLE_CTL_LEARN_CHANGE_EN_BOFFSET 30 -#define ADDR_TABLE_CTL_LEARN_CHANGE_EN_BLEN 1 -#define ADDR_TABLE_CTL_LEARN_CHANGE_EN_FLAG HSL_RW - -#define IGMP_JOIN_LEAKY -#define ADDR_TABLE_CTL_IGMP_JOIN_LEAKY_BOFFSET 29 -#define ADDR_TABLE_CTL_IGMP_JOIN_LEAKY_BLEN 1 -#define ADDR_TABLE_CTL_IGMP_JOIN_LEAKY_FLAG HSL_RW - -#define IGMP_CREAT_EN -#define ADDR_TABLE_CTL_IGMP_CREAT_EN_BOFFSET 28 -#define ADDR_TABLE_CTL_IGMP_CREAT_EN_BLEN 1 -#define ADDR_TABLE_CTL_IGMP_CREAT_EN_FLAG HSL_RW - -#define IGMP_PRI_EN -#define ADDR_TABLE_CTL_IGMP_PRI_EN_BOFFSET 27 -#define ADDR_TABLE_CTL_IGMP_PRI_EN_BLEN 1 -#define ADDR_TABLE_CTL_IGMP_PRI_EN_FLAG HSL_RW - -#define IGMP_PRI -#define ADDR_TABLE_CTL_IGMP_PRI_BOFFSET 24 -#define ADDR_TABLE_CTL_IGMP_PRI_BLEN 3 -#define ADDR_TABLE_CTL_IGMP_PRI_FLAG HSL_RW - -#define IGMP_JOIN_STATIC -#define ADDR_TABLE_CTL_IGMP_JOIN_STATIC_BOFFSET 20 -#define ADDR_TABLE_CTL_IGMP_JOIN_STATIC_BLEN 4 -#define ADDR_TABLE_CTL_IGMP_JOIN_STATIC_FLAG HSL_RW - -#define AGE_EN -#define ADDR_TABLE_CTL_AGE_EN_BOFFSET 19 -#define ADDR_TABLE_CTL_AGE_EN_BLEN 1 -#define ADDR_TABLE_CTL_AGE_EN_FLAG HSL_RW - -#define LOOP_CHECK_TIMER -#define ADDR_TABLE_CTL_LOOP_CHECK_TIMER_BOFFSET 16 -#define ADDR_TABLE_CTL_LOOP_CHECK_TIMER_BLEN 3 -#define ADDR_TABLE_CTL_LOOP_CHECK_TIMER_FLAG HSL_RW - -#define AGE_TIME -#define ADDR_TABLE_CTL_AGE_TIME_BOFFSET 0 -#define ADDR_TABLE_CTL_AGE_TIME_BLEN 16 -#define ADDR_TABLE_CTL_AGE_TIME_FLAG HSL_RW - - - - - /* Global Forward Control0 Register */ -#define FORWARD_CTL0 -#define FORWARD_CTL0_OFFSET 0x0620 -#define FORWARD_CTL0_E_LENGTH 4 -#define FORWARD_CTL0_E_OFFSET 0 -#define FORWARD_CTL0_NR_E 1 - -#define ARP_CMD -#define FORWARD_CTL0_ARP_CMD_BOFFSET 26 -#define FORWARD_CTL0_ARP_CMD_BLEN 2 -#define FORWARD_CTL0_ARP_CMD_FLAG HSL_RW - -#define IP_NOT_FOUND -#define FORWARD_CTL0_IP_NOT_FOUND_BOFFSET 24 -#define FORWARD_CTL0_IP_NOT_FOUND_BLEN 2 -#define FORWARD_CTL0_IP_NOT_FOUND_FLAG HSL_RW - -#define ARP_NOT_FOUND -#define FORWARD_CTL0_ARP_NOT_FOUND_BOFFSET 22 -#define FORWARD_CTL0_ARP_NOT_FOUND_BLEN 2 -#define FORWARD_CTL0_ARP_NOT_FOUND_FLAG HSL_RW - -#define HASH_MODE -#define FORWARD_CTL0_HASH_MODE_BOFFSET 20 -#define FORWARD_CTL0_HASH_MODE_BLEN 2 -#define FORWARD_CTL0_HASH_MODE_FLAG HSL_RW - -#define NAT_NOT_FOUND_DROP -#define FORWARD_CTL0_NAT_NOT_FOUND_DROP_BOFFSET 17 -#define FORWARD_CTL0_NAT_NOT_FOUND_DROP_BLEN 1 -#define FORWARD_CTL0_NAT_NOT_FOUND_DROP_FLAG HSL_RW - -#define SP_NOT_FOUND_DROP -#define FORWARD_CTL0_SP_NOT_FOUND_DROP_BOFFSET 16 -#define FORWARD_CTL0_SP_NOT_FOUND_DROP_BLEN 1 -#define FORWARD_CTL0_SP_NOT_FOUND_DROP_FLAG HSL_RW - -#define IGMP_LEAVE_DROP -#define FORWARD_CTL0_IGMP_LEAVE_DROP_BOFFSET 14 -#define FORWARD_CTL0_IGMP_LEAVE_DROP_BLEN 1 -#define FORWARD_CTL0_IGMP_LEAVE_DROP_FLAG HSL_RW - -#define ARL_UNI_LEAKY -#define FORWARD_CTL0_ARL_UNI_LEAKY_BOFFSET 13 -#define FORWARD_CTL0_ARL_UNI_LEAKY_BLEN 1 -#define FORWARD_CTL0_ARL_UNI_LEAKY_FLAG HSL_RW - -#define ARL_MUL_LEAKY -#define FORWARD_CTL0_ARL_MUL_LEAKY_BOFFSET 12 -#define FORWARD_CTL0_ARL_MUL_LEAKY_BLEN 1 -#define FORWARD_CTL0_ARL_MUL_LEAKY_FLAG HSL_RW - -#define MANAGE_VID_VIO_DROP_EN -#define FORWARD_CTL0_MANAGE_VID_VIO_DROP_EN_BOFFSET 11 -#define FORWARD_CTL0_MANAGE_VID_VIO_DROP_EN_BLEN 1 -#define FORWARD_CTL0_MANAGE_VID_VIO_DROP_EN_FLAG HSL_RW - -#define CPU_PORT_EN -#define FORWARD_CTL0_CPU_PORT_EN_BOFFSET 10 -#define FORWARD_CTL0_CPU_PORT_EN_BLEN 1 -#define FORWARD_CTL0_CPU_PORT_EN_FLAG HSL_RW - -#define PPPOE_RDT_EN -#define FORWARD_CTL0_PPPOE_RDT_EN_BOFFSET 8 -#define FORWARD_CTL0_PPPOE_RDT_EN_BLEN 1 -#define FORWARD_CTL0_PPPOE_RDT_EN_FLAG HSL_RW - -#define MIRROR_PORT_NUM -#define FORWARD_CTL0_MIRROR_PORT_NUM_BOFFSET 4 -#define FORWARD_CTL0_MIRROR_PORT_NUM_BLEN 4 -#define FORWARD_CTL0_MIRROR_PORT_NUM_FLAG HSL_RW - -#define IGMP_COPY_EN -#define FORWARD_CTL0_IGMP_COPY_EN_BOFFSET 3 -#define FORWARD_CTL0_IGMP_COPY_EN_BLEN 1 -#define FORWARD_CTL0_IGMP_COPY_EN_FLAG HSL_RW - -#define RIP_CPY_EN -#define FORWARD_CTL0_RIP_CPY_EN_BOFFSET 2 -#define FORWARD_CTL0_RIP_CPY_EN_BLEN 1 -#define FORWARD_CTL0_RIP_CPY_EN_FLAG HSL_RW - -#define EAPOL_CMD -#define FORWARD_CTL0_EAPOL_CMD_BOFFSET 0 -#define FORWARD_CTL0_EAPOL_CMD_BLEN 1 -#define FORWARD_CTL0_EAPOL_CMD_FLAG HSL_RW - - /* Global Forward Control1 Register */ -#define FORWARD_CTL1 -#define FORWARD_CTL1_OFFSET 0x0624 -#define FORWARD_CTL1_E_LENGTH 4 -#define FORWARD_CTL1_E_OFFSET 0 -#define FORWARD_CTL1_NR_E 1 - -#define IGMP_DP -#define FORWARD_CTL1_IGMP_DP_BOFFSET 24 -#define FORWARD_CTL1_IGMP_DP_BLEN 7 -#define FORWARD_CTL1_IGMP_DP_FLAG HSL_RW - -#define BC_FLOOD_DP -#define FORWARD_CTL1_BC_FLOOD_DP_BOFFSET 16 -#define FORWARD_CTL1_BC_FLOOD_DP_BLEN 7 -#define FORWARD_CTL1_BC_FLOOD_DP_FLAG HSL_RW - -#define MUL_FLOOD_DP -#define FORWARD_CTL1_MUL_FLOOD_DP_BOFFSET 8 -#define FORWARD_CTL1_MUL_FLOOD_DP_BLEN 7 -#define FORWARD_CTL1_MUL_FLOOD_DP_FLAG HSL_RW - -#define UNI_FLOOD_DP -#define FORWARD_CTL1_UNI_FLOOD_DP_BOFFSET 0 -#define FORWARD_CTL1_UNI_FLOOD_DP_BLEN 7 -#define FORWARD_CTL1_UNI_FLOOD_DP_FLAG HSL_RW - - - - - /* Global Learn Limit Ctl Register */ -#define GLOBAL_LEARN_LIMIT_CTL -#define GLOBAL_LEARN_LIMIT_CTL_OFFSET 0x0628 -#define GLOBAL_LEARN_LIMIT_CTL_E_LENGTH 4 -#define GLOBAL_LEARN_LIMIT_CTL_E_OFFSET 0 -#define GLOBAL_LEARN_LIMIT_CTL_NR_E 1 - -#define GOL_SA_LEARN_LIMIT_EN -#define GLOBAL_LEARN_LIMIT_CTL_GOL_SA_LEARN_LIMIT_EN_BOFFSET 12 -#define GLOBAL_LEARN_LIMIT_CTL_GOL_SA_LEARN_LIMIT_EN_BLEN 1 -#define GLOBAL_LEARN_LIMIT_CTL_GOL_SA_LEARN_LIMIT_EN_FLAG HSL_RW - -#define GOL_SA_LEARN_LIMIT_DROP_EN -#define GLOBAL_LEARN_LIMIT_CTL_GOL_SA_LEARN_LIMIT_DROP_EN_BOFFSET 13 -#define GLOBAL_LEARN_LIMIT_CTL_GOL_SA_LEARN_LIMIT_DROP_EN_BLEN 1 -#define GLOBAL_LEARN_LIMIT_CTL_GOL_SA_LEARN_LIMIT_DROP_EN_FLAG HSL_RW - -#define GOL_SA_LEARN_CNT -#define GLOBAL_LEARN_LIMIT_CTL_GOL_SA_LEARN_CNT_BOFFSET 0 -#define GLOBAL_LEARN_LIMIT_CTL_GOL_SA_LEARN_CNT_BLEN 12 -#define GLOBAL_LEARN_LIMIT_CTL_GOL_SA_LEARN_CNT_FLAG HSL_RW - - - - - /* DSCP To Priority Register */ -#define DSCP_TO_PRI -#define DSCP_TO_PRI_OFFSET 0x0630 -#define DSCP_TO_PRI_E_LENGTH 4 -#define DSCP_TO_PRI_E_OFFSET 0x0004 -#define DSCP_TO_PRI_NR_E 8 - - - - - /* UP To Priority Register */ -#define UP_TO_PRI -#define UP_TO_PRI_OFFSET 0x0650 -#define UP_TO_PRI_E_LENGTH 4 -#define UP_TO_PRI_E_OFFSET 0x0004 -#define UP_TO_PRI_NR_E 1 - - - - - /* Port Lookup control Register */ -#define PORT_LOOKUP_CTL -#define PORT_LOOKUP_CTL_OFFSET 0x0660 -#define PORT_LOOKUP_CTL_E_LENGTH 4 -#define PORT_LOOKUP_CTL_E_OFFSET 0x000c -#define PORT_LOOKUP_CTL_NR_E 7 - -#define MULTI_DROP_EN -#define PORT_LOOKUP_CTL_MULTI_DROP_EN_BOFFSET 31 -#define PORT_LOOKUP_CTL_MULTI_DROP_EN_BLEN 1 -#define PORT_LOOKUP_CTL_MULTI_DROP_EN_FLAG HSL_RW - -#define UNI_LEAKY_EN -#define PORT_LOOKUP_CTL_UNI_LEAKY_EN_BOFFSET 28 -#define PORT_LOOKUP_CTL_UNI_LEAKY_EN_BLEN 1 -#define PORT_LOOKUP_CTL_UNI_LEAKY_EN_FLAG HSL_RW - -#define MUL_LEAKY_EN -#define PORT_LOOKUP_CTL_MUL_LEAKY_EN_BOFFSET 27 -#define PORT_LOOKUP_CTL_MUL_LEAKY_EN_BLEN 1 -#define PORT_LOOKUP_CTL_MUL_LEAKY_EN_FLAG HSL_RW - -#define ARP_LEAKY_EN -#define PORT_LOOKUP_CTL_ARP_LEAKY_EN_BOFFSET 26 -#define PORT_LOOKUP_CTL_ARP_LEAKY_EN_BLEN 1 -#define PORT_LOOKUP_CTL_ARP_LEAKY_EN_FLAG HSL_RW - -#define ING_MIRROR_EN -#define PORT_LOOKUP_CTL_ING_MIRROR_EN_BOFFSET 25 -#define PORT_LOOKUP_CTL_ING_MIRROR_EN_BLEN 1 -#define PORT_LOOKUP_CTL_ING_MIRROR_EN_FLAG HSL_RW - -#define PORT_LOOP_BACK -#define PORT_LOOKUP_CTL_PORT_LOOP_BACK_BOFFSET 21 -#define PORT_LOOKUP_CTL_PORT_LOOP_BACK_BLEN 1 -#define PORT_LOOKUP_CTL_PORT_LOOP_BACK_FLAG HSL_RW - -#define LEARN_EN -#define PORT_LOOKUP_CTL_LEARN_EN_BOFFSET 20 -#define PORT_LOOKUP_CTL_LEARN_EN_BLEN 1 -#define PORT_LOOKUP_CTL_LEARN_EN_FLAG HSL_RW - -#define PORT_STATE -#define PORT_LOOKUP_CTL_PORT_STATE_BOFFSET 16 -#define PORT_LOOKUP_CTL_PORT_STATE_BLEN 3 -#define PORT_LOOKUP_CTL_PORT_STATE_FLAG HSL_RW - -#define FORCE_PVLAN -#define PORT_LOOKUP_CTL_FORCE_PVLAN_BOFFSET 10 -#define PORT_LOOKUP_CTL_FORCE_PVLAN_BLEN 1 -#define PORT_LOOKUP_CTL_FORCE_PVLAN_FLAG HSL_RW - -#define DOT1Q_MODE -#define PORT_LOOKUP_CTL_DOT1Q_MODE_BOFFSET 8 -#define PORT_LOOKUP_CTL_DOT1Q_MODE_BLEN 2 -#define PORT_LOOKUP_CTL_DOT1Q_MODE_FLAG HSL_RW - -#define PORT_VID_MEM -#define PORT_LOOKUP_CTL_PORT_VID_MEM_BOFFSET 0 -#define PORT_LOOKUP_CTL_PORT_VID_MEM_BLEN 7 -#define PORT_LOOKUP_CTL_PORT_VID_MEM_FLAG HSL_RW - - - - - /* Priority Control Register */ -#define PRI_CTL -#define PRI_CTL_OFFSET 0x0664 -#define PRI_CTL_E_LENGTH 4 -#define PRI_CTL_E_OFFSET 0x000c -#define PRI_CTL_NR_E 7 - -#define EG_MAC_BASE_VLAN_EN -#define PRI_CTL_EG_MAC_BASE_VLAN_EN_BOFFSET 20 -#define PRI_CTL_EG_MAC_BASE_VLAN_EN_BLEN 1 -#define PRI_CTL_EG_MAC_BASE_VLAN_EN_FLAG HSL_RW - -#define DA_PRI_EN -#define PRI_CTL_DA_PRI_EN_BOFFSET 18 -#define PRI_CTL_DA_PRI_EN_BLEN 1 -#define PRI_CTL_DA_PRI_EN_FLAG HSL_RW - -#define VLAN_PRI_EN -#define PRI_CTL_VLAN_PRI_EN_BOFFSET 17 -#define PRI_CTL_VLAN_PRI_EN_BLEN 1 -#define PRI_CTL_VLAN_PRI_EN_FLAG HSL_RW - -#define IP_PRI_EN -#define PRI_CTL_IP_PRI_EN_BOFFSET 16 -#define PRI_CTL_IP_PRI_EN_BLEN 1 -#define PRI_CTL_IP_PRI_EN_FLAG HSL_RW - -#define DA_PRI_SEL -#define PRI_CTL_DA_PRI_SEL_BOFFSET 6 -#define PRI_CTL_DA_PRI_SEL_BLEN 2 -#define PRI_CTL_DA_PRI_SEL_FLAG HSL_RW - -#define VLAN_PRI_SEL -#define PRI_CTL_VLAN_PRI_SEL_BOFFSET 4 -#define PRI_CTL_VLAN_PRI_SEL_BLEN 2 -#define PRI_CTL_VLAN_PRI_SEL_FLAG HSL_RW - -#define IP_PRI_SEL -#define PRI_CTL_IP_PRI_SEL_BOFFSET 2 -#define PRI_CTL_IP_PRI_SEL_BLEN 2 -#define PRI_CTL_IP_PRI_SEL_FLAG HSL_RW - - - - /* Port Learn Limit Ctl Register */ -#define PORT_LEARN_LIMIT_CTL -#define PORT_LEARN_LIMIT_CTL_OFFSET 0x0668 -#define PORT_LEARN_LIMIT_CTL_E_LENGTH 4 -#define PORT_LEARN_LIMIT_CTL_E_OFFSET 0x000c -#define PORT_LEARN_LIMIT_CTL_NR_E 7 - -#define IGMP_JOIN_LIMIT_DROP_EN -#define PORT_LEARN_LIMIT_CTL_IGMP_JOIN_LIMIT_DROP_EN_BOFFSET 29 -#define PORT_LEARN_LIMIT_CTL_IGMP_JOIN_LIMIT_DROP_EN_BLEN 1 -#define PORT_LEARN_LIMIT_CTL_IGMP_JOIN_LIMIT_DROP_EN_FLAG HSL_RW - -#define SA_LEARN_LIMIT_DROP_EN -#define PORT_LEARN_LIMIT_CTL_SA_LEARN_LIMIT_DROP_EN_BOFFSET 28 -#define PORT_LEARN_LIMIT_CTL_SA_LEARN_LIMIT_DROP_EN_BLEN 1 -#define PORT_LEARN_LIMIT_CTL_SA_LEARN_LIMIT_DROP_EN_FLAG HSL_RW - -#define IGMP_JOIN_LIMIT_EN -#define PORT_LEARN_LIMIT_CTL_IGMP_JOIN_LIMIT_EN_BOFFSET 27 -#define PORT_LEARN_LIMIT_CTL_IGMP_JOIN_LIMIT_EN_BLEN 1 -#define PORT_LEARN_LIMIT_CTL_IGMP_JOIN_LIMIT_EN_FLAG HSL_RW - -#define IGMP_JOIN_CNT -#define PORT_LEARN_LIMIT_CTL_IGMP_JOIN_CNT_BOFFSET 16 -#define PORT_LEARN_LIMIT_CTL_IGMP_JOIN_CNT_BLEN 11 -#define PORT_LEARN_LIMIT_CTL_IGMP_JOIN_CNT_FLAG HSL_RW - -#define SA_LEARN_STATUS -#define PORT_LEARN_LIMIT_CTL_SA_LEARN_STATUS_BOFFSET 12 -#define PORT_LEARN_LIMIT_CTL_SA_LEARN_STATUS_BLEN 4 -#define PORT_LEARN_LIMIT_CTL_SA_LEARN_STATUS_FLAG HSL_RW - -#define SA_LEARN_LIMIT_EN -#define PORT_LEARN_LIMIT_CTL_SA_LEARN_LIMIT_EN_BOFFSET 11 -#define PORT_LEARN_LIMIT_CTL_SA_LEARN_LIMIT_EN_BLEN 1 -#define PORT_LEARN_LIMIT_CTL_SA_LEARN_LIMIT_EN_FLAG HSL_RW - -#define SA_LEARN_CNT -#define PORT_LEARN_LIMIT_CTL_SA_LEARN_CNT_BOFFSET 0 -#define PORT_LEARN_LIMIT_CTL_SA_LEARN_CNT_BLEN 11 -#define PORT_LEARN_LIMIT_CTL_SA_LEARN_CNT_FLAG HSL_RW - - - - /* Global Trunk Ctl0 Register */ -#define GOL_TRUNK_CTL0 -#define GOL_TRUNK_CTL0_OFFSET 0x0700 -#define GOL_TRUNK_CTL0_E_LENGTH 4 -#define GOL_TRUNK_CTL0_E_OFFSET 0x4 -#define GOL_TRUNK_CTL0_NR_E 1 - - - /* Global Trunk Ctl1 Register */ -#define GOL_TRUNK_CTL1 -#define GOL_TRUNK_CTL1_OFFSET 0x0704 -#define GOL_TRUNK_CTL1_E_LENGTH 4 -#define GOL_TRUNK_CTL1_E_OFFSET 0x4 -#define GOL_TRUNK_CTL1_NR_E 2 - - - /* ACL Forward source filter Register */ -#define ACL_FWD_SRC_FILTER_CTL0 -#define ACL_FWD_SRC_FILTER_CTL0_OFFSET 0x0710 -#define ACL_FWD_SRC_FILTER_CTL0_E_LENGTH 4 -#define ACL_FWD_SRC_FILTER_CTL0_E_OFFSET 0x4 -#define ACL_FWD_SRC_FILTER_CTL0_NR_E 3 - - - /* VLAN translation register */ -#define VLAN_TRANS -#define VLAN_TRANS_OFFSET 0x0418 -#define VLAN_TRANS_E_LENGTH 4 -#define VLAN_TRANS_E_OFFSET 0 -#define VLAN_TRANS_NR_E 7 - -#define EG_FLTR_BYPASS_EN -#define VLAN_TRANS_EG_FLTR_BYPASS_EN_BOFFSET 1 -#define VLAN_TRANS_EG_FLTR_BYPASS_EN_BLEN 1 -#define VLAN_TRANS_EG_FLTR_BYPASS_EN_FLAG HSL_RW - -#define NET_ISO -#define VLAN_TRANS_NET_ISO_BOFFSET 0 -#define VLAN_TRANS_NET_ISO_BLEN 1 -#define VLAN_TRANS_NET_ISO_FLAG HSL_RW - - - /* Port vlan0 Register */ -#define PORT_VLAN0 -#define PORT_VLAN0_OFFSET 0x0420 -#define PORT_VLAN0_E_LENGTH 4 -#define PORT_VLAN0_E_OFFSET 0x0008 -#define PORT_VLAN0_NR_E 7 - -#define ING_CPRI -#define PORT_VLAN0_ING_CPRI_BOFFSET 29 -#define PORT_VLAN0_ING_CPRI_BLEN 3 -#define PORT_VLAN0_ING_CPRI_FLAG HSL_RW - -#define ING_FORCE_CPRI -#define PORT_VLAN0_ING_FORCE_CPRI_BOFFSET 28 -#define PORT_VLAN0_ING_FORCE_CPRI_BLEN 1 -#define PORT_VLAN0_ING_FORCE_CPRI_FLAG HSL_RW - -#define DEF_CVID -#define PORT_VLAN0_DEF_CVID_BOFFSET 16 -#define PORT_VLAN0_DEF_CVID_BLEN 12 -#define PORT_VLAN0_DEF_CVID_FLAG HSL_RW - -#define ING_SPRI -#define PORT_VLAN0_ING_SPRI_BOFFSET 13 -#define PORT_VLAN0_ING_SPRI_BLEN 3 -#define PORT_VLAN0_ING_SPRI_FLAG HSL_RW - -#define ING_FORCE_SPRI -#define PORT_VLAN0_ING_FORCE_SPRI_BOFFSET 12 -#define PORT_VLAN0_ING_FORCE_SPRI_BLEN 1 -#define PORT_VLAN0_ING_FORCE_SPRI_FLAG HSL_RW - -#define DEF_SVID -#define PORT_VLAN0_DEF_SVID_BOFFSET 0 -#define PORT_VLAN0_DEF_SVID_BLEN 12 -#define PORT_VLAN0_DEF_SVID_FLAG HSL_RW - - /* Port vlan1 Register */ -#define PORT_VLAN1 -#define PORT_VLAN1_OFFSET 0x0424 -#define PORT_VLAN1_E_LENGTH 4 -#define PORT_VLAN1_E_OFFSET 0x0008 -#define PORT_VLAN1_NR_E 7 - -#define EG_VLAN_MODE -#define PORT_VLAN1_EG_VLAN_MODE_BOFFSET 12 -#define PORT_VLAN1_EG_VLAN_MODE_BLEN 2 -#define PORT_VLAN1_EG_VLAN_MODE_FLAG HSL_RW - -#define VLAN_DIS -#define PORT_VLAN1_VLAN_DIS_BOFFSET 11 -#define PORT_VLAN1_VLAN_DIS_BLEN 1 -#define PORT_VLAN1_VLAN_DIS_FLAG HSL_RW - -#define SP_CHECK_EN -#define PORT_VLAN1_SP_CHECK_EN_BOFFSET 10 -#define PORT_VLAN1_SP_CHECK_EN_BLEN 1 -#define PORT_VLAN1_SP_CHECK_EN_FLAG HSL_RW - -#define COREP_EN -#define PORT_VLAN1_COREP_EN_BOFFSET 9 -#define PORT_VLAN1_COREP_EN_BLEN 1 -#define PORT_VLAN1_COREP_EN_FLAG HSL_RW - -#define FORCE_DEF_VID -#define PORT_VLAN1_FORCE_DEF_VID_BOFFSET 8 -#define PORT_VLAN1_FORCE_DEF_VID_BLEN 1 -#define PORT_VLAN1_FORCE_DEF_VID_FLAG HSL_RW - -#define TLS_EN -#define PORT_VLAN1_TLS_EN_BOFFSET 7 -#define PORT_VLAN1_TLS_EN_BLEN 1 -#define PORT_VLAN1_TLS_EN_FLAG HSL_RW - -#define PROPAGATION_EN -#define PORT_VLAN1_PROPAGATION_EN_BOFFSET 6 -#define PORT_VLAN1_PROPAGATION_EN_BLEN 1 -#define PORT_VLAN1_PROPAGATION_EN_FLAG HSL_RW - -#define CLONE -#define PORT_VLAN1_CLONE_BOFFSET 5 -#define PORT_VLAN1_CLONE_BLEN 1 -#define PORT_VLAN1_CLONE_FLAG HSL_RW - -#define PRI_PROPAGATION -#define PORT_VLAN1_PRI_PROPAGATION_BOFFSET 4 -#define PORT_VLAN1_PRI_PROPAGATION_BLEN 1 -#define PORT_VLAN1_VLAN_PRI_PROPAGATION_FLAG HSL_RW - -#define IN_VLAN_MODE -#define PORT_VLAN1_IN_VLAN_MODE_BOFFSET 2 -#define PORT_VLAN1_IN_VLAN_MODE_BLEN 2 -#define PORT_VLAN1_IN_VLAN_MODE_FLAG HSL_RW - - - /* Route Default VID Register */ -#define ROUTER_DEFV -#define ROUTER_DEFV_OFFSET 0x0c70 -#define ROUTER_DEFV_E_LENGTH 4 -#define ROUTER_DEFV_E_OFFSET 0x0004 -#define ROUTER_DEFV_NR_E 4 - - - /* Route Egress VLAN Mode Register */ -#define ROUTER_EG -#define ROUTER_EG_OFFSET 0x0c80 -#define ROUTER_EG_E_LENGTH 4 -#define ROUTER_EG_E_OFFSET 0x0004 -#define ROUTER_EG_NR_E 1 - - - - - /* Mdio control Register */ -#define MDIO_CTRL "mctrl" -#define MDIO_CTRL_ID 24 -#define MDIO_CTRL_OFFSET 0x0098 -#define MDIO_CTRL_E_LENGTH 4 -#define MDIO_CTRL_E_OFFSET 0 -#define MDIO_CTRL_NR_E 1 - -#define MSTER_EN "mctrl_msteren" -#define MDIO_CTRL_MSTER_EN_BOFFSET 30 -#define MDIO_CTRL_MSTER_EN_BLEN 1 -#define MDIO_CTRL_MSTER_EN_FLAG HSL_RW - -#define MSTER_EN "mctrl_msteren" -#define MDIO_CTRL_MSTER_EN_BOFFSET 30 -#define MDIO_CTRL_MSTER_EN_BLEN 1 -#define MDIO_CTRL_MSTER_EN_FLAG HSL_RW - -#define CMD "mctrl_cmd" -#define MDIO_CTRL_CMD_BOFFSET 27 -#define MDIO_CTRL_CMD_BLEN 1 -#define MDIO_CTRL_CMD_FLAG HSL_RW - -#define SUP_PRE "mctrl_spre" -#define MDIO_CTRL_SUP_PRE_BOFFSET 26 -#define MDIO_CTRL_SUP_PRE_BLEN 1 -#define MDIO_CTRL_SUP_PRE_FLAG HSL_RW - -#define PHY_ADDR "mctrl_phyaddr" -#define MDIO_CTRL_PHY_ADDR_BOFFSET 21 -#define MDIO_CTRL_PHY_ADDR_BLEN 5 -#define MDIO_CTRL_PHY_ADDR_FLAG HSL_RW - -#define REG_ADDR "mctrl_regaddr" -#define MDIO_CTRL_REG_ADDR_BOFFSET 16 -#define MDIO_CTRL_REG_ADDR_BLEN 5 -#define MDIO_CTRL_REG_ADDR_FLAG HSL_RW - -#define DATA "mctrl_data" -#define MDIO_CTRL_DATA_BOFFSET 0 -#define MDIO_CTRL_DATA_BLEN 16 -#define MDIO_CTRL_DATA_FLAG HSL_RW - - - - - /* BIST control Register */ -#define BIST_CTRL "bctrl" -#define BIST_CTRL_ID 24 -#define BIST_CTRL_OFFSET 0x00a0 -#define BIST_CTRL_E_LENGTH 4 -#define BIST_CTRL_E_OFFSET 0 -#define BIST_CTRL_NR_E 1 - -#define BIST_BUSY "bctrl_bb" -#define BIST_CTRL_BIST_BUSY_BOFFSET 31 -#define BIST_CTRL_BIST_BUSY_BLEN 1 -#define BIST_CTRL_BIST_BUSY_FLAG HSL_RW - -#define ONE_ERR "bctrl_oe" -#define BIST_CTRL_ONE_ERR_BOFFSET 30 -#define BIST_CTRL_ONE_ERR_BLEN 1 -#define BIST_CTRL_ONE_ERR_FLAG HSL_RO - -#define ERR_MEM "bctrl_em" -#define BIST_CTRL_ERR_MEM_BOFFSET 24 -#define BIST_CTRL_ERR_MEM_BLEN 4 -#define BIST_CTRL_ERR_MEM_FLAG HSL_RO - -#define PTN_EN2 "bctrl_pe2" -#define BIST_CTRL_PTN_EN2_BOFFSET 22 -#define BIST_CTRL_PTN_EN2_BLEN 1 -#define BIST_CTRL_PTN_EN2_FLAG HSL_RW - -#define PTN_EN1 "bctrl_pe1" -#define BIST_CTRL_PTN_EN1_BOFFSET 21 -#define BIST_CTRL_PTN_EN1_BLEN 1 -#define BIST_CTRL_PTN_EN1_FLAG HSL_RW - -#define PTN_EN0 "bctrl_pe0" -#define BIST_CTRL_PTN_EN0_BOFFSET 20 -#define BIST_CTRL_PTN_EN0_BLEN 1 -#define BIST_CTRL_PTN_EN0_FLAG HSL_RW - -#define ERR_PTN "bctrl_ep" -#define BIST_CTRL_ERR_PTN_BOFFSET 16 -#define BIST_CTRL_ERR_PTN_BLEN 2 -#define BIST_CTRL_ERR_PTN_FLAG HSL_RO - -#define ERR_CNT "bctrl_ec" -#define BIST_CTRL_ERR_CNT_BOFFSET 13 -#define BIST_CTRL_ERR_CNT_BLEN 2 -#define BIST_CTRL_ERR_CNT_FLAG HSL_RO - -#define ERR_ADDR "bctrl_ea" -#define BIST_CTRL_ERR_ADDR_BOFFSET 0 -#define BIST_CTRL_ERR_ADDR_BLEN 12 -#define BIST_CTRL_ERR_ADDR_FLAG HSL_RO - - - - - /* BIST recover Register */ -#define BIST_RCV "brcv" -#define BIST_RCV_ID 24 -#define BIST_RCV_OFFSET 0x00a4 -#define BIST_RCV_E_LENGTH 4 -#define BIST_RCV_E_OFFSET 0 -#define BIST_RCV_NR_E 1 - -#define RCV_EN "brcv_en" -#define BIST_RCV_RCV_EN_BOFFSET 31 -#define BIST_RCV_RCV_EN_BLEN 1 -#define BIST_RCV_RCV_EN_FLAG HSL_RW - -#define RCV_ADDR "brcv_addr" -#define BIST_RCV_RCV_ADDR_BOFFSET 0 -#define BIST_RCV_RCV_ADDR_BLEN 12 -#define BIST_RCV_RCV_ADDR_FLAG HSL_RW - - - - - /* LED control Register */ -#define LED_CTRL "ledctrl" -#define LED_CTRL_ID 25 -#define LED_CTRL_OFFSET 0x0050 -#define LED_CTRL_E_LENGTH 4 -#define LED_CTRL_E_OFFSET 0 -#define LED_CTRL_NR_E 3 - -#define PATTERN_EN "lctrl_pen" -#define LED_CTRL_PATTERN_EN_BOFFSET 14 -#define LED_CTRL_PATTERN_EN_BLEN 2 -#define LED_CTRL_PATTERN_EN_FLAG HSL_RW - -#define FULL_LIGHT_EN "lctrl_fen" -#define LED_CTRL_FULL_LIGHT_EN_BOFFSET 13 -#define LED_CTRL_FULL_LIGHT_EN_BLEN 1 -#define LED_CTRL_FULL_LIGHT_EN_FLAG HSL_RW - -#define HALF_LIGHT_EN "lctrl_hen" -#define LED_CTRL_HALF_LIGHT_EN_BOFFSET 12 -#define LED_CTRL_HALF_LIGHT_EN_BLEN 1 -#define LED_CTRL_HALF_LIGHT_EN_FLAG HSL_RW - -#define POWERON_LIGHT_EN "lctrl_poen" -#define LED_CTRL_POWERON_LIGHT_EN_BOFFSET 11 -#define LED_CTRL_POWERON_LIGHT_EN_BLEN 1 -#define LED_CTRL_POWERON_LIGHT_EN_FLAG HSL_RW - -#define GE_LIGHT_EN "lctrl_geen" -#define LED_CTRL_GE_LIGHT_EN_BOFFSET 10 -#define LED_CTRL_GE_LIGHT_EN_BLEN 1 -#define LED_CTRL_GE_LIGHT_EN_FLAG HSL_RW - -#define FE_LIGHT_EN "lctrl_feen" -#define LED_CTRL_FE_LIGHT_EN_BOFFSET 9 -#define LED_CTRL_FE_LIGHT_EN_BLEN 1 -#define LED_CTRL_FE_LIGHT_EN_FLAG HSL_RW - -#define ETH_LIGHT_EN "lctrl_ethen" -#define LED_CTRL_ETH_LIGHT_EN_BOFFSET 8 -#define LED_CTRL_ETH_LIGHT_EN_BLEN 1 -#define LED_CTRL_ETH_LIGHT_EN_FLAG HSL_RW - -#define COL_BLINK_EN "lctrl_cen" -#define LED_CTRL_COL_BLINK_EN_BOFFSET 7 -#define LED_CTRL_COL_BLINK_EN_BLEN 1 -#define LED_CTRL_COL_BLINK_EN_FLAG HSL_RW - -#define RX_BLINK_EN "lctrl_rxen" -#define LED_CTRL_RX_BLINK_EN_BOFFSET 5 -#define LED_CTRL_RX_BLINK_EN_BLEN 1 -#define LED_CTRL_RX_BLINK_EN_FLAG HSL_RW - -#define TX_BLINK_EN "lctrl_txen" -#define LED_CTRL_TX_BLINK_EN_BOFFSET 4 -#define LED_CTRL_TX_BLINK_EN_BLEN 1 -#define LED_CTRL_TX_BLINK_EN_FLAG HSL_RW - -#define LINKUP_OVER_EN "lctrl_loen" -#define LED_CTRL_LINKUP_OVER_EN_BOFFSET 2 -#define LED_CTRL_LINKUP_OVER_EN_BLEN 1 -#define LED_CTRL_LINKUP_OVER_EN_FLAG HSL_RW - -#define BLINK_FREQ "lctrl_bfreq" -#define LED_CTRL_BLINK_FREQ_BOFFSET 0 -#define LED_CTRL_BLINK_FREQ_BLEN 2 -#define LED_CTRL_BLINK_FREQ_FLAG HSL_RW - - /* LED control Register */ -#define LED_PATTERN "ledpatten" -#define LED_PATTERN_ID 25 -#define LED_PATTERN_OFFSET 0x005c -#define LED_PATTERN_E_LENGTH 4 -#define LED_PATTERN_E_OFFSET 0 -#define LED_PATTERN_NR_E 1 - - -#define P3L2_MODE -#define LED_PATTERN_P3L2_MODE_BOFFSET 24 -#define LED_PATTERN_P3L2_MODE_BLEN 2 -#define LED_PATTERN_P3L2_MODE_FLAG HSL_RW - -#define P3L1_MODE -#define LED_PATTERN_P3L1_MODE_BOFFSET 22 -#define LED_PATTERN_P3L1_MODE_BLEN 2 -#define LED_PATTERN_P3L1_MODE_FLAG HSL_RW - -#define P3L0_MODE -#define LED_PATTERN_P3L0_MODE_BOFFSET 20 -#define LED_PATTERN_P3L0_MODE_BLEN 2 -#define LED_PATTERN_P3L0_MODE_FLAG HSL_RW - -#define P2L2_MODE -#define LED_PATTERN_P2L2_MODE_BOFFSET 18 -#define LED_PATTERN_P2L2_MODE_BLEN 2 -#define LED_PATTERN_P2L2_MODE_FLAG HSL_RW - -#define P2L1_MODE -#define LED_PATTERN_P2L1_MODE_BOFFSET 16 -#define LED_PATTERN_P2L1_MODE_BLEN 2 -#define LED_PATTERN_P2L1_MODE_FLAG HSL_RW - -#define P2L0_MODE -#define LED_PATTERN_P2L0_MODE_BOFFSET 14 -#define LED_PATTERN_P2L0_MODE_BLEN 2 -#define LED_PATTERN_P2L0_MODE_FLAG HSL_RW - -#define P1L2_MODE -#define LED_PATTERN_P1L2_MODE_BOFFSET 12 -#define LED_PATTERN_P1L2_MODE_BLEN 2 -#define LED_PATTERN_P1L2_MODE_FLAG HSL_RW - -#define P1L1_MODE -#define LED_PATTERN_P1L1_MODE_BOFFSET 10 -#define LED_PATTERN_P1L1_MODE_BLEN 2 -#define LED_PATTERN_P1L1_MODE_FLAG HSL_RW - -#define P1L0_MODE -#define LED_PATTERN_P1L0_MODE_BOFFSET 8 -#define LED_PATTERN_P1L0_MODE_BLEN 2 -#define LED_PATTERN_P1L0_MODE_FLAG HSL_RW - - - - - /* Pri To Queue Register */ -#define PRI_TO_QUEUE -#define PRI_TO_QUEUE_OFFSET 0x0814 -#define PRI_TO_QUEUE_E_LENGTH 4 -#define PRI_TO_QUEUE_E_OFFSET 0x0004 -#define PRI_TO_QUEUE_NR_E 1 - - - - - /* Pri To EhQueue Register */ -#define PRI_TO_EHQUEUE -#define PRI_TO_EHQUEUE_OFFSET 0x0810 -#define PRI_TO_EHQUEUE_E_LENGTH 4 -#define PRI_TO_EHQUEUE_E_OFFSET 0x0004 -#define PRI_TO_EHQUEUE_NR_E 1 - - - - - /*Global Flow Control Register*/ -#define QM_CTRL_REG -#define QM_CTRL_REG_OFFSET 0X0808 -#define QM_CTRL_REG_E_LENGTH 4 -#define QM_CTRL_REG_E_OFFSET 0x0004 -#define QM_CTRL_REG_NR_E 1 - -#define GOL_FLOW_EN -#define QM_CTRL_REG_GOL_FLOW_EN_BOFFSET 16 -#define QM_CTRL_REG_GOL_FLOW_EN_BLEN 7 -#define QM_CTRL_REG_GOL_FLOW_EN_FLAG HSL_RW - -#define QM_FUNC_TEST -#define QM_CTRL_REG_QM_FUNC_TEST_BOFFSET 10 -#define QM_CTRL_REG_QM_FUNC_TEST_BLEN 1 -#define QM_CTRL_REG_QM_FUNC_TEST_FLAG HSL_RW - -#define RATE_DROP_EN -#define QM_CTRL_REG_RATE_DROP_EN_BOFFSET 7 -#define QM_CTRL_REG_RATE_DROP_EN_BLEN 1 -#define QM_CTRL_REG_RATE_DROP_EN_FLAG HSL_RW - -#define FLOW_DROP_EN -#define QM_CTRL_REG_FLOW_DROP_EN_BOFFSET 6 -#define QM_CTRL_REG_FLOW_DROP_EN_BLEN 1 -#define QM_CTRL_REG_FLOW_DROP_EN_FLAG HSL_RW - -#define FLOW_DROP_CNT -#define QM_CTRL_REG_FLOW_DROP_CNT_BOFFSET 0 -#define QM_CTRL_REG_FLOW_DROP_CNT_BLEN 6 -#define QM_CTRL_REG_FLOW_DROP_CNT_FLAG HSL_RW - - - - - /* Port HOL CTL0 Register */ -#define PORT_HOL_CTL0 -#define PORT_HOL_CTL0_OFFSET 0x0970 -#define PORT_HOL_CTL0_E_LENGTH 4 -#define PORT_HOL_CTL0_E_OFFSET 0x0008 -#define PORT_HOL_CTL0_NR_E 7 - -#define PORT_DESC_NR -#define PORT_HOL_CTL0_PORT_DESC_NR_BOFFSET 24 -#define PORT_HOL_CTL0_PORT_DESC_NR_BLEN 6 -#define PORT_HOL_CTL0_PORT_DESC_NR_FLAG HSL_RW - -#define QUEUE5_DESC_NR -#define PORT_HOL_CTL0_QUEUE5_DESC_NR_BOFFSET 20 -#define PORT_HOL_CTL0_QUEUE5_DESC_NR_BLEN 4 -#define PORT_HOL_CTL0_QUEUE5_DESC_NR_FLAG HSL_RW - -#define QUEUE4_DESC_NR -#define PORT_HOL_CTL0_QUEUE4_DESC_NR_BOFFSET 16 -#define PORT_HOL_CTL0_QUEUE4_DESC_NR_BLEN 4 -#define PORT_HOL_CTL0_QUEUE4_DESC_NR_FLAG HSL_RW - -#define QUEUE3_DESC_NR -#define PORT_HOL_CTL0_QUEUE3_DESC_NR_BOFFSET 12 -#define PORT_HOL_CTL0_QUEUE3_DESC_NR_BLEN 4 -#define PORT_HOL_CTL0_QUEUE3_DESC_NR_FLAG HSL_RW - -#define QUEUE2_DESC_NR -#define PORT_HOL_CTL0_QUEUE2_DESC_NR_BOFFSET 8 -#define PORT_HOL_CTL0_QUEUE2_DESC_NR_BLEN 4 -#define PORT_HOL_CTL0_QUEUE2_DESC_NR_FLAG HSL_RW - -#define QUEUE1_DESC_NR -#define PORT_HOL_CTL0_QUEUE1_DESC_NR_BOFFSET 4 -#define PORT_HOL_CTL0_QUEUE1_DESC_NR_BLEN 4 -#define PORT_HOL_CTL0_QUEUE1_DESC_NR_FLAG HSL_RW - -#define QUEUE0_DESC_NR -#define PORT_HOL_CTL0_QUEUE0_DESC_NR_BOFFSET 0 -#define PORT_HOL_CTL0_QUEUE0_DESC_NR_BLEN 4 -#define PORT_HOL_CTL0_QUEUE0_DESC_NR_FLAG HSL_RW - - /* Port HOL CTL1 Register */ -#define PORT_HOL_CTL1 -#define PORT_HOL_CTL1_OFFSET 0x0974 -#define PORT_HOL_CTL1_E_LENGTH 4 -#define PORT_HOL_CTL1_E_OFFSET 0x0008 -#define PORT_HOL_CTL1_NR_E 7 - -#define EG_MIRROR_EN -#define PORT_HOL_CTL1_EG_MIRROR_EN_BOFFSET 16 -#define PORT_HOL_CTL1_EG_MIRROR_EN_BLEN 1 -#define PORT_HOL_CTL1_EG_MIRROR_EN_FLAG HSL_RW - -#define PORT_RED_EN -#define PORT_HOL_CTL1_PORT_RED_EN_BOFFSET 8 -#define PORT_HOL_CTL1_PORT_RED_EN_BLEN 1 -#define PORT_HOL_CTL1_PORT_RED_EN_FLAG HSL_RW - -#define PORT_DESC_EN -#define PORT_HOL_CTL1_PORT_DESC_EN_BOFFSET 7 -#define PORT_HOL_CTL1_PORT_DESC_EN_BLEN 1 -#define PORT_HOL_CTL1_PORT_DESC_EN_FLAG HSL_RW - -#define QUEUE_DESC_EN -#define PORT_HOL_CTL1_QUEUE_DESC_EN_BOFFSET 6 -#define PORT_HOL_CTL1_QUEUE_DESC_EN_BLEN 1 -#define PORT_HOL_CTL1_QUEUE_DESC_EN_FLAG HSL_RW - -#define PORT_IN_DESC_EN -#define PORT_HOL_CTL1_PORT_IN_DESC_EN_BOFFSET 0 -#define PORT_HOL_CTL1_PORT_IN_DESC_EN_BLEN 4 -#define PORT_HOL_CTL1_PORT_IN_DESC_EN_FLAG HSL_RW - - /* PORT FLOW CTRL THRESHOLD REGISTER */ -#define PORT_FLOW_CTRL_THRESHOLD -#define PORT_FLOW_CTRL_THRESHOLD_OFFSET 0x09B0 -#define PORT_FLOW_CTRL_THRESHOLD_E_LENGTH 4 -#define PORT_FLOW_CTRL_THRESHOLD_E_OFFSET 0x0004 -#define PORT_FLOW_CTRL_THRESHOLD_NR_E 7 - -#define XON_THRES -#define PORT_FLOW_CTRL_THRESHOLD_XON_THRES_BOFFSET 16 -#define PORT_FLOW_CTRL_THRESHOLD_XON_THRES_BLEN 8 -#define PORT_FLOW_CTRL_THRESHOLD_XON_THRES_FLAG HSL_RW - -#define XOFF_THRES -#define PORT_FLOW_CTRL_THRESHOLD_XOFF_THRES_BOFFSET 0 -#define PORT_FLOW_CTRL_THRESHOLD_XOFF_THRES_BLEN 8 -#define PORT_FLOW_CTRL_THRESHOLD_XOFF_THRES_FLAG HSL_RW - - /* FX100 CTRL Register */ -#define FX100_CTRL -#define FX100_CTRL_OFFSET 0x00fc -#define FX100_CTRL_E_LENGTH 4 -#define FX100_CTRL_E_OFFSET 0X0004 -#define FX100_CTRL_NR_E 1 - -#define FX100_STATUS -#define FX100_CTRL_FX100_STATUS_BOFFSET 24 -#define FX100_CTRL_FX100_STATUS_BLEN 8 -#define FX100_CTRL_FX100_STATUS_FLAG HSL_RO - -#define FX100_LOOP_EN -#define FX100_CTRL_FX100_LOOP_EN_BOFFSET 23 -#define FX100_CTRL_FX100_LOOP_EN_BLEN 1 -#define FX100_CTRL_FX100_LOOP_EN_FLAG HSL_Rw - -#define SGMII_FIBER -#define FX100_CTRL_SGMII_FIBER_BOFFSET 15 -#define FX100_CTRL_SGMII_FIBER_BLEN 2 -#define FX100_CTRL_SGMII_FIBER_FLAG HSL_Rw - -#define CRS_COL_100_CTRL -#define FX100_CTRL_CRS_COL_100_CTRL_BOFFSET 14 -#define FX100_CTRL_CRS_COL_100_CTRL_BLEN 1 -#define FX100_CTRL_CRS_COL_100_CTRL_FLAG HSL_Rw - -#define LOOPBACK_TEST -#define FX100_CTRL_LOOPBACK_TEST_BOFFSET 13 -#define FX100_CTRL_LOOPBACK_TEST_BLEN 1 -#define FX100_CTRL_LOOPBACK_TEST_FLAG HSL_Rw - -#define CRS_CTRL -#define FX100_CTRL_CRS_CTRL_BOFFSET 12 -#define FX100_CTRL_CRS_CTRL_BLEN 1 -#define FX100_CTRL_CRS_CTRL_FLAG HSL_Rw - -#define COL_TEST -#define FX100_CTRL_COL_TEST_BOFFSET 11 -#define FX100_CTRL_COL_TEST_BLEN 1 -#define FX100_CTRL_COL_TEST_FLAG HSL_Rw - -#define FD_MODE -#define FX100_CTRL_FD_MODE_BOFFSET 10 -#define FX100_CTRL_FD_MODE_BLEN 1 -#define FX100_CTRL_FD_MODE_FLAG HSL_Rw - -#define LINK_CTRL -#define FX100_CTRL_LINK_CTRL_BOFFSET 8 -#define FX100_CTRL_LINK_CTRL_BLEN 2 -#define FX100_CTRL_LINK_CTRL_FLAG HSL_Rw - -#define OVERSHOOT_MODE -#define FX100_CTRL_OVERSHOOT_MODE_BOFFSET 6 -#define FX100_CTRL_OVERSHOOT_MODE_BLEN 1 -#define FX100_CTRL_OVERSHOOT_MODE_FLAG HSL_Rw - -#define LOOPBACK_MODE -#define FX100_CTRL_LOOPBACK_MODE_BOFFSET 3 -#define FX100_CTRL_LOOPBACK_MODE_BLEN 1 -#define FX100_CTRL_LOOPBACK_MODE_FLAG HSL_Rw - - - - /* Port Rate Limit0 Register */ -#define RATE_LIMIT0 "rlmt0" -#define RATE_LIMIT0_ID 32 -#define RATE_LIMIT0_OFFSET 0x0110 -#define RATE_LIMIT0_E_LENGTH 4 -#define RATE_LIMIT0_E_OFFSET 0x0100 -#define RATE_LIMIT0_NR_E 7 - - -#define EG_RATE_EN "rlmt_egen" -#define RATE_LIMIT0_EG_RATE_EN_BOFFSET 23 -#define RATE_LIMIT0_EG_RATE_EN_BLEN 1 -#define RATE_LIMIT0_EG_RATE_EN_FLAG HSL_RW - -#define EG_MNG_RATE_EN "rlmt_egmngen" -#define RATE_LIMIT0_EG_MNG_RATE_EN_BOFFSET 22 -#define RATE_LIMIT0_EG_MNG_RATE_EN_BLEN 1 -#define RATE_LIMIT0_EG_MNG_RATE_EN_FLAG HSL_RW - -#define IN_MNG_RATE_EN "rlmt_inmngen" -#define RATE_LIMIT0_IN_MNG_RATE_EN_BOFFSET 21 -#define RATE_LIMIT0_IN_MNG_RATE_EN_BLEN 1 -#define RATE_LIMIT0_IN_MNG_RATE_EN_FLAG HSL_RW - -#define IN_MUL_RATE_EN "rlmt_inmulen" -#define RATE_LIMIT0_IN_MUL_RATE_EN_BOFFSET 20 -#define RATE_LIMIT0_IN_MUL_RATE_EN_BLEN 1 -#define RATE_LIMIT0_IN_MUL_RATE_EN_FLAG HSL_RW - -#define ING_RATE "rlmt_ingrate" -#define RATE_LIMIT0_ING_RATE_BOFFSET 0 -#define RATE_LIMIT0_ING_RATE_BLEN 15 -#define RATE_LIMIT0_ING_RATE_FLAG HSL_RW - - - - /* PKT edit control register */ -#define PKT_CTRL -#define PKT_CTRL_OFFSET 0x0c00 -#define PKT_CTRL_E_LENGTH 4 -#define PKT_CTRL_E_OFFSET 0 -#define PKT_CTRL_NR_E 7 - -#define CPU_VID_EN -#define PKT_CTRL_CPU_VID_EN_BOFFSET 1 -#define PKT_CTRL_CPU_VID_EN_BLEN 1 -#define PKT_CTRL_CPU_VID_EN_FLAG HSL_RW - - -#define RTD_PPPOE_EN -#define PKT_CTRL_RTD_PPPOE_EN_BOFFSET 0 -#define PKT_CTRL_RTD_PPPOE_EN_BLEN 1 -#define PKT_CTRL_RTD_PPPOE_EN_FLAG HSL_RW - - - - - /* mib memory info */ -#define MIB_RXBROAD -#define MIB_RXBROAD_OFFSET 0x01000 -#define MIB_RXBROAD_E_LENGTH 4 -#define MIB_RXBROAD_E_OFFSET 0x100 -#define MIB_RXBROAD_NR_E 7 - -#define MIB_RXPAUSE -#define MIB_RXPAUSE_OFFSET 0x01004 -#define MIB_RXPAUSE_E_LENGTH 4 -#define MIB_RXPAUSE_E_OFFSET 0x100 -#define MIB_RXPAUSE_NR_E 7 - -#define MIB_RXMULTI -#define MIB_RXMULTI_OFFSET 0x01008 -#define MIB_RXMULTI_E_LENGTH 4 -#define MIB_RXMULTI_E_OFFSET 0x100 -#define MIB_RXMULTI_NR_E 7 - -#define MIB_RXFCSERR -#define MIB_RXFCSERR_OFFSET 0x0100c -#define MIB_RXFCSERR_E_LENGTH 4 -#define MIB_RXFCSERR_E_OFFSET 0x100 -#define MIB_RXFCSERR_NR_E 7 - -#define MIB_RXALLIGNERR -#define MIB_RXALLIGNERR_OFFSET 0x01010 -#define MIB_RXALLIGNERR_E_LENGTH 4 -#define MIB_RXALLIGNERR_E_OFFSET 0x100 -#define MIB_RXALLIGNERR_NR_E 7 - -#define MIB_RXRUNT -#define MIB_RXRUNT_OFFSET 0x01014 -#define MIB_RXRUNT_E_LENGTH 4 -#define MIB_RXRUNT_E_OFFSET 0x100 -#define MIB_RXRUNT_NR_E 7 - -#define MIB_RXFRAGMENT -#define MIB_RXFRAGMENT_OFFSET 0x01018 -#define MIB_RXFRAGMENT_E_LENGTH 4 -#define MIB_RXFRAGMENT_E_OFFSET 0x100 -#define MIB_RXFRAGMENT_NR_E 7 - -#define MIB_RX64BYTE -#define MIB_RX64BYTE_OFFSET 0x0101c -#define MIB_RX64BYTE_E_LENGTH 4 -#define MIB_RX64BYTE_E_OFFSET 0x100 -#define MIB_RX64BYTE_NR_E 7 - -#define MIB_RX128BYTE -#define MIB_RX128BYTE_OFFSET 0x01020 -#define MIB_RX128BYTE_E_LENGTH 4 -#define MIB_RX128BYTE_E_OFFSET 0x100 -#define MIB_RX128BYTE_NR_E 7 - -#define MIB_RX256BYTE -#define MIB_RX256BYTE_OFFSET 0x01024 -#define MIB_RX256BYTE_E_LENGTH 4 -#define MIB_RX256BYTE_E_OFFSET 0x100 -#define MIB_RX256BYTE_NR_E 7 - -#define MIB_RX512BYTE -#define MIB_RX512BYTE_OFFSET 0x01028 -#define MIB_RX512BYTE_E_LENGTH 4 -#define MIB_RX512BYTE_E_OFFSET 0x100 -#define MIB_RX512BYTE_NR_E 7 - -#define MIB_RX1024BYTE -#define MIB_RX1024BYTE_OFFSET 0x0102c -#define MIB_RX1024BYTE_E_LENGTH 4 -#define MIB_RX1024BYTE_E_OFFSET 0x100 -#define MIB_RX1024BYTE_NR_E 7 - -#define MIB_RX1518BYTE -#define MIB_RX1518BYTE_OFFSET 0x01030 -#define MIB_RX1518BYTE_E_LENGTH 4 -#define MIB_RX1518BYTE_E_OFFSET 0x100 -#define MIB_RX1518BYTE_NR_E 7 - -#define MIB_RXMAXBYTE -#define MIB_RXMAXBYTE_OFFSET 0x01034 -#define MIB_RXMAXBYTE_E_LENGTH 4 -#define MIB_RXMAXBYTE_E_OFFSET 0x100 -#define MIB_RXMAXBYTE_NR_E 7 - -#define MIB_RXTOOLONG -#define MIB_RXTOOLONG_OFFSET 0x01038 -#define MIB_RXTOOLONG_E_LENGTH 4 -#define MIB_RXTOOLONG_E_OFFSET 0x100 -#define MIB_RXTOOLONG_NR_E 7 - -#define MIB_RXGOODBYTE_LO -#define MIB_RXGOODBYTE_LO_OFFSET 0x0103c -#define MIB_RXGOODBYTE_LO_E_LENGTH 4 -#define MIB_RXGOODBYTE_LO_E_OFFSET 0x100 -#define MIB_RXGOODBYTE_LO_NR_E 7 - -#define MIB_RXGOODBYTE_HI -#define MIB_RXGOODBYTE_HI_OFFSET 0x01040 -#define MIB_RXGOODBYTE_HI_E_LENGTH 4 -#define MIB_RXGOODBYTE_HI_E_OFFSET 0x100 -#define MIB_RXGOODBYTE_HI_NR_E 7 - -#define MIB_RXBADBYTE_LO -#define MIB_RXBADBYTE_LO_OFFSET 0x01044 -#define MIB_RXBADBYTE_LO_E_LENGTH 4 -#define MIB_RXBADBYTE_LO_E_OFFSET 0x100 -#define MIB_RXBADBYTE_LO_NR_E 7 - -#define MIB_RXBADBYTE_HI -#define MIB_RXBADBYTE_HI_OFFSET 0x01048 -#define MIB_RXBADBYTE_HI_E_LENGTH 4 -#define MIB_RXBADBYTE_HI_E_OFFSET 0x100 -#define MIB_RXBADBYTE_HI_NR_E 7 - -#define MIB_RXOVERFLOW -#define MIB_RXOVERFLOW_OFFSET 0x0104c -#define MIB_RXOVERFLOW_E_LENGTH 4 -#define MIB_RXOVERFLOW_E_OFFSET 0x100 -#define MIB_RXOVERFLOW_NR_E 7 - -#define MIB_FILTERED -#define MIB_FILTERED_OFFSET 0x01050 -#define MIB_FILTERED_E_LENGTH 4 -#define MIB_FILTERED_E_OFFSET 0x100 -#define MIB_FILTERED_NR_E 7 - -#define MIB_TXBROAD -#define MIB_TXBROAD_OFFSET 0x01054 -#define MIB_TXBROAD_E_LENGTH 4 -#define MIB_TXBROAD_E_OFFSET 0x100 -#define MIB_TXBROAD_NR_E 7 - -#define MIB_TXPAUSE -#define MIB_TXPAUSE_OFFSET 0x01058 -#define MIB_TXPAUSE_E_LENGTH 4 -#define MIB_TXPAUSE_E_OFFSET 0x100 -#define MIB_TXPAUSE_NR_E 7 - -#define MIB_TXMULTI -#define MIB_TXMULTI_OFFSET 0x0105c -#define MIB_TXMULTI_E_LENGTH 4 -#define MIB_TXMULTI_E_OFFSET 0x100 -#define MIB_TXMULTI_NR_E 7 - -#define MIB_TXUNDERRUN -#define MIB_TXUNDERRUN_OFFSET 0x01060 -#define MIB_TXUNDERRUN_E_LENGTH 4 -#define MIB_TXUNDERRUN_E_OFFSET 0x100 -#define MIB_TXUNDERRUN_NR_E 7 - -#define MIB_TX64BYTE -#define MIB_TX64BYTE_OFFSET 0x01064 -#define MIB_TX64BYTE_E_LENGTH 4 -#define MIB_TX64BYTE_E_OFFSET 0x100 -#define MIB_TX64BYTE_NR_E 7 - -#define MIB_TX128BYTE -#define MIB_TX128BYTE_OFFSET 0x01068 -#define MIB_TX128BYTE_E_LENGTH 4 -#define MIB_TX128BYTE_E_OFFSET 0x100 -#define MIB_TX128BYTE_NR_E 7 - -#define MIB_TX256BYTE -#define MIB_TX256BYTE_OFFSET 0x0106c -#define MIB_TX256BYTE_E_LENGTH 4 -#define MIB_TX256BYTE_E_OFFSET 0x100 -#define MIB_TX256BYTE_NR_E 7 - -#define MIB_TX512BYTE -#define MIB_TX512BYTE_OFFSET 0x01070 -#define MIB_TX512BYTE_E_LENGTH 4 -#define MIB_TX512BYTE_E_OFFSET 0x100 -#define MIB_TX512BYTE_NR_E 7 - -#define MIB_TX1024BYTE -#define MIB_TX1024BYTE_OFFSET 0x01074 -#define MIB_TX1024BYTE_E_LENGTH 4 -#define MIB_TX1024BYTE_E_OFFSET 0x100 -#define MIB_TX1024BYTE_NR_E 7 - -#define MIB_TX1518BYTE -#define MIB_TX1518BYTE_OFFSET 0x01078 -#define MIB_TX1518BYTE_E_LENGTH 4 -#define MIB_TX1518BYTE_E_OFFSET 0x100 -#define MIB_TX1518BYTE_NR_E 7 - -#define MIB_TXMAXBYTE -#define MIB_TXMAXBYTE_OFFSET 0x0107c -#define MIB_TXMAXBYTE_E_LENGTH 4 -#define MIB_TXMAXBYTE_E_OFFSET 0x100 -#define MIB_TXMAXBYTE_NR_E 7 - -#define MIB_TXOVERSIZE -#define MIB_TXOVERSIZE_OFFSET 0x01080 -#define MIB_TXOVERSIZE_E_LENGTH 4 -#define MIB_TXOVERSIZE_E_OFFSET 0x100 -#define MIB_TXOVERSIZE_NR_E 7 - -#define MIB_TXBYTE_LO -#define MIB_TXBYTE_LO_OFFSET 0x01084 -#define MIB_TXBYTE_LO_E_LENGTH 4 -#define MIB_TXBYTE_LO_E_OFFSET 0x100 -#define MIB_TXBYTE_LO_NR_E 7 - -#define MIB_TXBYTE_HI -#define MIB_TXBYTE_HI_OFFSET 0x01088 -#define MIB_TXBYTE_HI_E_LENGTH 4 -#define MIB_TXBYTE_HI_E_OFFSET 0x100 -#define MIB_TXBYTE_HI_NR_E 7 - -#define MIB_TXCOLLISION -#define MIB_TXCOLLISION_OFFSET 0x0108c -#define MIB_TXCOLLISION_E_LENGTH 4 -#define MIB_TXCOLLISION_E_OFFSET 0x100 -#define MIB_TXCOLLISION_NR_E 7 - -#define MIB_TXABORTCOL -#define MIB_TXABORTCOL_OFFSET 0x01090 -#define MIB_TXABORTCOL_E_LENGTH 4 -#define MIB_TXABORTCOL_E_OFFSET 0x100 -#define MIB_TXABORTCOL_NR_E 7 - -#define MIB_TXMULTICOL -#define MIB_TXMULTICOL_OFFSET 0x01094 -#define MIB_TXMULTICOL_E_LENGTH 4 -#define MIB_TXMULTICOL_E_OFFSET 0x100 -#define MIB_TXMULTICOL_NR_E 7 - -#define MIB_TXSINGALCOL -#define MIB_TXSINGALCOL_OFFSET 0x01098 -#define MIB_TXSINGALCOL_E_LENGTH 4 -#define MIB_TXSINGALCOL_E_OFFSET 0x100 -#define MIB_TXSINGALCOL_NR_E 7 - -#define MIB_TXEXCDEFER -#define MIB_TXEXCDEFER_OFFSET 0x0109c -#define MIB_TXEXCDEFER_E_LENGTH 4 -#define MIB_TXEXCDEFER_E_OFFSET 0x100 -#define MIB_TXEXCDEFER_NR_E 7 - -#define MIB_TXDEFER -#define MIB_TXDEFER_OFFSET 0x010a0 -#define MIB_TXDEFER_E_LENGTH 4 -#define MIB_TXDEFER_E_OFFSET 0x100 -#define MIB_TXDEFER_NR_E 7 - -#define MIB_TXLATECOL -#define MIB_TXLATECOL_OFFSET 0x010a4 -#define MIB_TXLATECOL_E_LENGTH 4 -#define MIB_TXLATECOL_E_OFFSET 0x100 -#define MIB_TXLATECOL_NR_E 7 - -#define MIB_RXUNICAST -#define MIB_RXUNICAST_OFFSET 0x010a8 -#define MIB_RXUNICAST_E_LENGTH 4 -#define MIB_RXUNICAST_E_OFFSET 0x100 -#define MIB_RXUNICAST_NR_E 7 - -#define MIB_TXUNICAST -#define MIB_TXUNICAST_OFFSET 0x010ac -#define MIB_TXUNICAST_E_LENGTH 4 -#define MIB_TXUNICAST_E_OFFSET 0x100 -#define MIB_TXUNICAST_NR_E 7 - - /* ACL Action Register */ -#define ACL_RSLT0 10 -#define ACL_RSLT0_OFFSET 0x5a000 -#define ACL_RSLT0_E_LENGTH 4 -#define ACL_RSLT0_E_OFFSET 0x10 -#define ACL_RSLT0_NR_E 96 - -#define CTAGPRI -#define ACL_RSLT0_CTAGPRI_BOFFSET 29 -#define ACL_RSLT0_CTAGPRI_BLEN 3 -#define ACL_RSLT0_CTAGPRI_FLAG HSL_RW - -#define CTAGCFI -#define ACL_RSLT0_CTAGCFI_BOFFSET 28 -#define ACL_RSLT0_CTAGCFI_BLEN 1 -#define ACL_RSLT0_CTAGCFI_FLAG HSL_RW - -#define CTAGVID -#define ACL_RSLT0_CTAGVID_BOFFSET 16 -#define ACL_RSLT0_CTAGVID_BLEN 12 -#define ACL_RSLT0_CTAGVID_FLAG HSL_RW - -#define STAGPRI -#define ACL_RSLT0_STAGPRI_BOFFSET 13 -#define ACL_RSLT0_STAGPRI_BLEN 3 -#define ACL_RSLT0_STAGPRI_FLAG HSL_RW - -#define STAGDEI -#define ACL_RSLT0_STAGDEI_BOFFSET 12 -#define ACL_RSLT0_STAGDEI_BLEN 1 -#define ACL_RSLT0_STAGDEI_FLAG HSL_RW - -#define STAGVID -#define ACL_RSLT0_STAGVID_BOFFSET 0 -#define ACL_RSLT0_STAGVID_BLEN 12 -#define ACL_RSLT0_STAGVID_FLAG HSL_RW - - -#define ACL_RSLT1 11 -#define ACL_RSLT1_OFFSET 0x5a004 -#define ACL_RSLT1_E_LENGTH 4 -#define ACL_RSLT1_E_OFFSET 0x10 -#define ACL_RSLT1_NR_E 96 - -#define DES_PORT0 -#define ACL_RSLT1_DES_PORT0_BOFFSET 29 -#define ACL_RSLT1_DES_PORT0_BLEN 3 -#define ACL_RSLT1_DES_PORT0_FLAG HSL_RW - -#define PRI_QU_EN -#define ACL_RSLT1_PRI_QU_EN_BOFFSET 28 -#define ACL_RSLT1_PRI_QU_EN_BLEN 1 -#define ACL_RSLT1_PRI_QU_EN_FLAG HSL_RW - -#define PRI_QU -#define ACL_RSLT1_PRI_QU_BOFFSET 25 -#define ACL_RSLT1_PRI_QU_BLEN 3 -#define ACL_RSLT1_PRI_QU_FLAG HSL_RW - -#define WCMP_EN -#define ACL_RSLT1_WCMP_EN_BOFFSET 24 -#define ACL_RSLT1_WCMP_EN_BLEN 1 -#define ACL_RSLT1_WCMP_EN_FLAG HSL_RW - -#define ARP_PTR -#define ACL_RSLT1_ARP_PTR_BOFFSET 17 -#define ACL_RSLT1_ARP_PTR_BLEN 7 -#define ACL_RSLT1_ARP_PTR_FLAG HSL_RW - -#define ARP_PTR_EN -#define ACL_RSLT1_ARP_PTR_EN_BOFFSET 16 -#define ACL_RSLT1_ARP_PTR_EN_BLEN 1 -#define ACL_RSLT1_ARP_PTR_EN_FLAG HSL_RW - -#define FORCE_L3_MODE -#define ACL_RSLT1_FORCE_L3_MODE_BOFFSET 14 -#define ACL_RSLT1_FORCE_L3_MODE_BLEN 2 -#define ACL_RSLT1_FORCE_L3_MODE_FLAG HSL_RW - -#define LOOK_VID_CHG -#define ACL_RSLT1_LOOK_VID_CHG_BOFFSET 13 -#define ACL_RSLT1_LOOK_VID_CHG_BLEN 1 -#define ACL_RSLT1_LOOK_VID_CHG_FLAG HSL_RW - -#define TRANS_CVID_CHG -#define ACL_RSLT1_TRANS_CVID_CHG_BOFFSET 12 -#define ACL_RSLT1_TRANS_CVID_CHG_BLEN 1 -#define ACL_RSLT1_TRANS_CVID_CHG_FLAG HSL_RW - -#define TRANS_SVID_CHG -#define ACL_RSLT1_TRANS_SVID_CHG_BOFFSET 11 -#define ACL_RSLT1_TRANS_SVID_CHG_BLEN 1 -#define ACL_RSLT1_TRANS_SVID_CHG_FLAG HSL_RW - -#define CTAG_CFI_CHG -#define ACL_RSLT1_CTAG_CFI_CHG_BOFFSET 10 -#define ACL_RSLT1_CTAG_CFI_CHG_BLEN 1 -#define ACL_RSLT1_CTAG_CFI_CHG_FLAG HSL_RW - -#define CTAG_PRI_REMAP -#define ACL_RSLT1_CTAG_PRI_REMAP_BOFFSET 9 -#define ACL_RSLT1_CTAG_PRI_REMAP_BLEN 1 -#define ACL_RSLT1_CTAG_PRI_REMAP_FLAG HSL_RW - -#define STAG_DEI_CHG -#define ACL_RSLT1_STAG_DEI_CHG_BOFFSET 8 -#define ACL_RSLT1_STAG_DEI_CHG_BLEN 1 -#define ACL_RSLT1_STAG_DEI_CHG_FLAG HSL_RW - -#define STAG_PRI_REMAP -#define ACL_RSLT1_STAG_PRI_REMAP_BOFFSET 7 -#define ACL_RSLT1_STAG_PRI_REMAP_BLEN 1 -#define ACL_RSLT1_STAG_PRI_REMAP_FLAG HSL_RW - -#define DSCP_REMAP -#define ACL_RSLT1_DSCP_REMAP_BOFFSET 6 -#define ACL_RSLT1_DSCP_REMAP_BLEN 1 -#define ACL_RSLT1_DSCP_REMAP_FLAG HSL_RW - -#define DSCPV -#define ACL_RSLT1_DSCPV_BOFFSET 0 -#define ACL_RSLT1_DSCPV_BLEN 6 -#define ACL_RSLT1_DSCPV_FLAG HSL_RW - -#define ACL_RSLT2 12 -#define ACL_RSLT2_OFFSET 0x5a008 -#define ACL_RSLT2_E_LENGTH 4 -#define ACL_RSLT2_E_OFFSET 0x10 -#define ACL_RSLT2_NR_E 96 - -#define TRIGGER_INTR -#define ACL_RSLT2_TRIGGER_INTR_BOFFSET 16 -#define ACL_RSLT2_TRIGGER_INTR_BLEN 1 -#define ACL_RSLT2_TRIGGER_INTR_FLAG HSL_RW - -#define EG_BYPASS -#define ACL_RSLT2_EG_BYPASS_BOFFSET 15 -#define ACL_RSLT2_EG_BYPASS_BLEN 1 -#define ACL_RSLT2_EG_BYPASS_FLAG HSL_RW - -#define POLICER_EN -#define ACL_RSLT2_POLICER_EN_BOFFSET 14 -#define ACL_RSLT2_POLICER_EN_BLEN 1 -#define ACL_RSLT2_POLICER_EN_FLAG HSL_RW - -#define POLICER_PTR -#define ACL_RSLT2_POLICER_PTR_BOFFSET 9 -#define ACL_RSLT2_POLICER_PTR_BLEN 5 -#define ACL_RSLT2_POLICER_PTR_FLAG HSL_RW - -#define FWD_CMD -#define ACL_RSLT2_FWD_CMD_BOFFSET 6 -#define ACL_RSLT2_FWD_CMD_BLEN 3 -#define ACL_RSLT2_FWD_CMD_FLAG HSL_RW - -#define MIRR_EN -#define ACL_RSLT2_MIRR_EN_BOFFSET 5 -#define ACL_RSLT2_MIRR_EN_BLEN 1 -#define ACL_RSLT2_MIRR_EN_FLAG HSL_RW - -#define DES_PORT_EN -#define ACL_RSLT2_DES_PORT_EN_BOFFSET 4 -#define ACL_RSLT2_DES_PORT_EN_BLEN 1 -#define ACL_RSLT2_DES_PORT_EN_FLAG HSL_RW - -#define DES_PORT1 -#define ACL_RSLT2_DES_PORT1_BOFFSET 0 -#define ACL_RSLT2_DES_PORT1_BLEN 4 -#define ACL_RSLT2_DES_PORT1_FLAG HSL_RW - - - - - /* MAC Type Rule Field Define */ -#define MAC_RUL_V0 0 -#define MAC_RUL_V0_OFFSET 0x58000 -#define MAC_RUL_V0_E_LENGTH 4 -#define MAC_RUL_V0_E_OFFSET 0x20 -#define MAC_RUL_V0_NR_E 96 - -#define DAV_BYTE2 -#define MAC_RUL_V0_DAV_BYTE2_BOFFSET 24 -#define MAC_RUL_V0_DAV_BYTE2_BLEN 8 -#define MAC_RUL_V0_DAV_BYTE2_FLAG HSL_RW - -#define DAV_BYTE3 -#define MAC_RUL_V0_DAV_BYTE3_BOFFSET 16 -#define MAC_RUL_V0_DAV_BYTE3_BLEN 8 -#define MAC_RUL_V0_DAV_BYTE3_FLAG HSL_RW - -#define DAV_BYTE4 -#define MAC_RUL_V0_DAV_BYTE4_BOFFSET 8 -#define MAC_RUL_V0_DAV_BYTE4_BLEN 8 -#define MAC_RUL_V0_DAV_BYTE4_FLAG HSL_RW - -#define DAV_BYTE5 -#define MAC_RUL_V0_DAV_BYTE5_BOFFSET 0 -#define MAC_RUL_V0_DAV_BYTE5_BLEN 8 -#define MAC_RUL_V0_DAV_BYTE5_FLAG HSL_RW - - -#define MAC_RUL_V1 1 -#define MAC_RUL_V1_OFFSET 0x58004 -#define MAC_RUL_V1_E_LENGTH 4 -#define MAC_RUL_V1_E_OFFSET 0x20 -#define MAC_RUL_V1_NR_E 96 - -#define SAV_BYTE4 -#define MAC_RUL_V1_SAV_BYTE4_BOFFSET 24 -#define MAC_RUL_V1_SAV_BYTE4_BLEN 8 -#define MAC_RUL_V1_SAV_BYTE4_FLAG HSL_RW - -#define SAV_BYTE5 -#define MAC_RUL_V1_SAV_BYTE5_BOFFSET 16 -#define MAC_RUL_V1_SAV_BYTE5_BLEN 8 -#define MAC_RUL_V1_SAV_BYTE5_FLAG HSL_RW - -#define DAV_BYTE0 -#define MAC_RUL_V1_DAV_BYTE0_BOFFSET 8 -#define MAC_RUL_V1_DAV_BYTE0_BLEN 8 -#define MAC_RUL_V1_DAV_BYTE0_FLAG HSL_RW - -#define DAV_BYTE1 -#define MAC_RUL_V1_DAV_BYTE1_BOFFSET 0 -#define MAC_RUL_V1_DAV_BYTE1_BLEN 8 -#define MAC_RUL_V1_DAV_BYTE1_FLAG HSL_RW - - -#define MAC_RUL_V2 2 -#define MAC_RUL_V2_OFFSET 0x58008 -#define MAC_RUL_V2_E_LENGTH 4 -#define MAC_RUL_V2_E_OFFSET 0x20 -#define MAC_RUL_V2_NR_E 96 - -#define SAV_BYTE0 -#define MAC_RUL_V2_SAV_BYTE0_BOFFSET 24 -#define MAC_RUL_V2_SAV_BYTE0_BLEN 8 -#define MAC_RUL_V2_SAV_BYTE0_FLAG HSL_RW - -#define SAV_BYTE1 -#define MAC_RUL_V2_SAV_BYTE1_BOFFSET 16 -#define MAC_RUL_V2_SAV_BYTE1_BLEN 8 -#define MAC_RUL_V2_SAV_BYTE1_FLAG HSL_RW - -#define SAV_BYTE2 -#define MAC_RUL_V2_SAV_BYTE2_BOFFSET 8 -#define MAC_RUL_V2_SAV_BYTE2_BLEN 8 -#define MAC_RUL_V2_SAV_BYTE2_FLAG HSL_RW - -#define SAV_BYTE3 -#define MAC_RUL_V2_SAV_BYTE3_BOFFSET 0 -#define MAC_RUL_V2_SAV_BYTE3_BLEN 8 -#define MAC_RUL_V2_SAV_BYTE3_FLAG HSL_RW - - -#define MAC_RUL_V3 3 -#define MAC_RUL_V3_ID 13 -#define MAC_RUL_V3_OFFSET 0x5800c -#define MAC_RUL_V3_E_LENGTH 4 -#define MAC_RUL_V3_E_OFFSET 0x20 -#define MAC_RUL_V3_NR_E 96 - -#define ETHTYPV -#define MAC_RUL_V3_ETHTYPV_BOFFSET 16 -#define MAC_RUL_V3_ETHTYPV_BLEN 16 -#define MAC_RUL_V3_ETHTYPV_FLAG HSL_RW - -#define VLANPRIV -#define MAC_RUL_V3_VLANPRIV_BOFFSET 13 -#define MAC_RUL_V3_VLANPRIV_BLEN 3 -#define MAC_RUL_V3_VLANPRIV_FLAG HSL_RW - -#define VLANCFIV -#define MAC_RUL_V3_VLANCFIV_BOFFSET 12 -#define MAC_RUL_V3_VLANCFIV_BLEN 1 -#define MAC_RUL_V3_VLANCFIV_FLAG HSL_RW - -#define VLANIDV -#define MAC_RUL_V3_VLANIDV_BOFFSET 0 -#define MAC_RUL_V3_VLANIDV_BLEN 12 -#define MAC_RUL_V3_VLANIDV_FLAG HSL_RW - - -#define MAC_RUL_V4 4 -#define MAC_RUL_V4_OFFSET 0x58010 -#define MAC_RUL_V4_E_LENGTH 4 -#define MAC_RUL_V4_E_OFFSET 0x20 -#define MAC_RUL_V4_NR_E 96 - -#define RULE_INV -#define MAC_RUL_V4_RULE_INV_BOFFSET 7 -#define MAC_RUL_V4_RULE_INV_BLEN 1 -#define MAC_RUL_V4_RULE_INV_FLAG HSL_RW - -#define SRC_PT -#define MAC_RUL_V4_SRC_PT_BOFFSET 0 -#define MAC_RUL_V4_SRC_PT_BLEN 7 -#define MAC_RUL_V4_SRC_PT_FLAG HSL_RW - - -#define MAC_RUL_M0 5 -#define MAC_RUL_M0_OFFSET 0x59000 -#define MAC_RUL_M0_E_LENGTH 4 -#define MAC_RUL_M0_E_OFFSET 0x20 -#define MAC_RUL_M0_NR_E 96 - -#define DAM_BYTE2 -#define MAC_RUL_M0_DAM_BYTE2_BOFFSET 24 -#define MAC_RUL_M0_DAM_BYTE2_BLEN 8 -#define MAC_RUL_M0_DAM_BYTE2_FLAG HSL_RW - -#define DAM_BYTE3 -#define MAC_RUL_M0_DAM_BYTE3_BOFFSET 16 -#define MAC_RUL_M0_DAM_BYTE3_BLEN 8 -#define MAC_RUL_M0_DAM_BYTE3_FLAG HSL_RW - -#define DAM_BYTE4 -#define MAC_RUL_M0_DAM_BYTE4_BOFFSET 8 -#define MAC_RUL_M0_DAM_BYTE4_BLEN 8 -#define MAC_RUL_M0_DAM_BYTE4_FLAG HSL_RW - -#define DAM_BYTE5 -#define MAC_RUL_M0_DAM_BYTE5_BOFFSET 0 -#define MAC_RUL_M0_DAM_BYTE5_BLEN 8 -#define MAC_RUL_M0_DAM_BYTE5_FLAG HSL_RW - - -#define MAC_RUL_M1 6 -#define MAC_RUL_M1_OFFSET 0x59004 -#define MAC_RUL_M1_E_LENGTH 4 -#define MAC_RUL_M1_E_OFFSET 0x20 -#define MAC_RUL_M1_NR_E 96 - -#define SAM_BYTE4 -#define MAC_RUL_M1_SAM_BYTE4_BOFFSET 24 -#define MAC_RUL_M1_SAM_BYTE4_BLEN 8 -#define MAC_RUL_M1_SAM_BYTE4_FLAG HSL_RW - -#define SAM_BYTE5 -#define MAC_RUL_M1_SAM_BYTE5_BOFFSET 16 -#define MAC_RUL_M1_SAM_BYTE5_BLEN 8 -#define MAC_RUL_M1_SAM_BYTE5_FLAG HSL_RW - -#define DAM_BYTE0 -#define MAC_RUL_M1_DAM_BYTE0_BOFFSET 8 -#define MAC_RUL_M1_DAM_BYTE0_BLEN 8 -#define MAC_RUL_M1_DAM_BYTE0_FLAG HSL_RW - -#define DAM_BYTE1 -#define MAC_RUL_M1_DAM_BYTE1_BOFFSET 0 -#define MAC_RUL_M1_DAM_BYTE1_BLEN 8 -#define MAC_RUL_M1_DAM_BYTE1_FLAG HSL_RW - - -#define MAC_RUL_M2 7 -#define MAC_RUL_M2_OFFSET 0x59008 -#define MAC_RUL_M2_E_LENGTH 4 -#define MAC_RUL_M2_E_OFFSET 0x20 -#define MAC_RUL_M2_NR_E 96 - -#define SAM_BYTE0 -#define MAC_RUL_M2_SAM_BYTE0_BOFFSET 24 -#define MAC_RUL_M2_SAM_BYTE0_BLEN 8 -#define MAC_RUL_M2_SAM_BYTE0_FLAG HSL_RW - -#define SAM_BYTE1 -#define MAC_RUL_M2_SAM_BYTE1_BOFFSET 16 -#define MAC_RUL_M2_SAM_BYTE1_BLEN 8 -#define MAC_RUL_M2_SAM_BYTE1_FLAG HSL_RW - -#define SAM_BYTE2 -#define MAC_RUL_M2_SAM_BYTE2_BOFFSET 8 -#define MAC_RUL_M2_SAM_BYTE2_BLEN 8 -#define MAC_RUL_M2_SAM_BYTE2_FLAG HSL_RW - -#define SAM_BYTE3 -#define MAC_RUL_M2_SAM_BYTE3_BOFFSET 0 -#define MAC_RUL_M2_SAM_BYTE3_BLEN 8 -#define MAC_RUL_M2_SAM_BYTE3_FLAG HSL_RW - - -#define MAC_RUL_M3 8 -#define MAC_RUL_M3_OFFSET 0x5900c -#define MAC_RUL_M3_E_LENGTH 4 -#define MAC_RUL_M3_E_OFFSET 0x20 -#define MAC_RUL_M3_NR_E 96 - -#define ETHTYPM -#define MAC_RUL_M3_ETHTYPM_BOFFSET 16 -#define MAC_RUL_M3_ETHTYPM_BLEN 16 -#define MAC_RUL_M3_ETHTYPM_FLAG HSL_RW - -#define VLANPRIM -#define MAC_RUL_M3_VLANPRIM_BOFFSET 13 -#define MAC_RUL_M3_VLANPRIM_BLEN 3 -#define MAC_RUL_M3_VLANPRIM_FLAG HSL_RW - -#define VLANCFIM -#define MAC_RUL_M3_VLANCFIM_BOFFSET 12 -#define MAC_RUL_M3_VLANCFIM_BLEN 1 -#define MAC_RUL_M3_VLANCFIM_FLAG HSL_RW - -#define VLANIDM -#define MAC_RUL_M3_VLANIDM_BOFFSET 0 -#define MAC_RUL_M3_VLANIDM_BLEN 12 -#define MAC_RUL_M3_VLANIDM_FLAG HSL_RW - - -#define MAC_RUL_M4 9 -#define MAC_RUL_M4_OFFSET 0x59010 -#define MAC_RUL_M4_E_LENGTH 4 -#define MAC_RUL_M4_E_OFFSET 0x20 -#define MAC_RUL_M4_NR_E 96 - -#define RULE_VALID -#define MAC_RUL_M4_RULE_VALID_BOFFSET 6 -#define MAC_RUL_M4_RULE_VALID_BLEN 2 -#define MAC_RUL_M4_RULE_VALID_FLAG HSL_RW - -#define TAGGEDM -#define MAC_RUL_M4_TAGGEDM_BOFFSET 5 -#define MAC_RUL_M4_TAGGEDM_BLEN 1 -#define MAC_RUL_M4_TAGGEDM_FLAG HSL_RW - -#define TAGGEDV -#define MAC_RUL_M4_TAGGEDV_BOFFSET 4 -#define MAC_RUL_M4_TAGGEDV_BLEN 1 -#define MAC_RUL_M4_TAGGEDV_FLAG HSL_RW - -#define VIDMSK -#define MAC_RUL_M4_VIDMSK_BOFFSET 3 -#define MAC_RUL_M4_VIDMSK_BLEN 1 -#define MAC_RUL_M4_VIDMSK_FLAG HSL_RW - -#define RULE_TYP -#define MAC_RUL_M4_RULE_TYP_BOFFSET 0 -#define MAC_RUL_M4_RULE_TYP_BLEN 3 -#define MAC_RUL_M4_RULE_TYP_FLAG HSL_RW - - - - - /* IP4 Type Rule Field Define */ -#define IP4_RUL_V0 0 -#define IP4_RUL_V0_OFFSET 0x58000 -#define IP4_RUL_V0_E_LENGTH 4 -#define IP4_RUL_V0_E_OFFSET 0x20 -#define IP4_RUL_V0_NR_E 96 - -#define DIPV -#define IP4_RUL_V0_DIPV_BOFFSET 0 -#define IP4_RUL_V0_DIPV_BLEN 32 -#define IP4_RUL_V0_DIPV_FLAG HSL_RW - - -#define IP4_RUL_V1 1 -#define IP4_RUL_V1_OFFSET 0x58004 -#define IP4_RUL_V1_E_LENGTH 4 -#define IP4_RUL_V1_E_OFFSET 0x20 -#define IP4_RUL_V1_NR_E 96 - -#define SIPV -#define IP4_RUL_V1_SIPV_BOFFSET 0 -#define IP4_RUL_V1_SIPV_BLEN 32 -#define IP4_RUL_V1_SIPV_FLAG HSL_RW - - -#define IP4_RUL_V2 2 -#define IP4_RUL_V2_OFFSET 0x58008 -#define IP4_RUL_V2_E_LENGTH 4 -#define IP4_RUL_V2_E_OFFSET 0x20 -#define IP4_RUL_V2_NR_E 96 - -#define IP4PROTV -#define IP4_RUL_V2_IP4PROTV_BOFFSET 0 -#define IP4_RUL_V2_IP4PROTV_BLEN 8 -#define IP4_RUL_V2_IP4PROTV_FLAG HSL_RW - -#define IP4DSCPV -#define IP4_RUL_V2_IP4DSCPV_BOFFSET 8 -#define IP4_RUL_V2_IP4DSCPV_BLEN 8 -#define IP4_RUL_V2_IP4DSCPV_FLAG HSL_RW - -#define IP4DPORTV -#define IP4_RUL_V2_IP4DPORTV_BOFFSET 16 -#define IP4_RUL_V2_IP4DPORTV_BLEN 16 -#define IP4_RUL_V2_IP4DPORTV_FLAG HSL_RW - - -#define IP4_RUL_V3 3 -#define IP4_RUL_V3_OFFSET 0x5800c -#define IP4_RUL_V3_E_LENGTH 4 -#define IP4_RUL_V3_E_OFFSET 0x20 -#define IP4_RUL_V3_NR_E 96 - -#define IP4TCPFLAGV -#define IP4_RUL_V3_IP4TCPFLAGV_BOFFSET 24 -#define IP4_RUL_V3_IP4TCPFLAGV_BLEN 6 -#define IP4_RUL_V3_IP4TCPFLAGV_FLAG HSL_RW - -#define IP4DHCPV -#define IP4_RUL_V3_IP4DHCPV_BOFFSET 22 -#define IP4_RUL_V3_IP4DHCPV_BLEN 1 -#define IP4_RUL_V3_IP4DHCPV_FLAG HSL_RW - -#define IP4RIPV -#define IP4_RUL_V3_IP4RIPV_BOFFSET 21 -#define IP4_RUL_V3_IP4RIPV_BLEN 1 -#define IP4_RUL_V3_IP4RIPV_FLAG HSL_RW - -#define ICMP_EN -#define IP4_RUL_V3_ICMP_EN_BOFFSET 20 -#define IP4_RUL_V3_ICMP_EN_BLEN 1 -#define IP4_RUL_V3_ICMP_EN_FLAG HSL_RW - -#define IP4SPORTV -#define IP4_RUL_V3_IP4SPORTV_BOFFSET 0 -#define IP4_RUL_V3_IP4SPORTV_BLEN 16 -#define IP4_RUL_V3_IP4SPORTV_FLAG HSL_RW - -#define IP4ICMPTYPV -#define IP4_RUL_V3_IP4ICMPTYPV_BOFFSET 8 -#define IP4_RUL_V3_IP4ICMPTYPV_BLEN 8 -#define IP4_RUL_V3_IP4ICMPTYPV_FLAG HSL_RW - -#define IP4ICMPCODEV -#define IP4_RUL_V3_IP4ICMPCODEV_BOFFSET 0 -#define IP4_RUL_V3_IP4ICMPCODEV_BLEN 8 -#define IP4_RUL_V3_IP4ICMPCODEV_FLAG HSL_RW - - -#define IP4_RUL_V4 4 -#define IP4_RUL_V4_OFFSET 0x58010 -#define IP4_RUL_V4_E_LENGTH 4 -#define IP4_RUL_V4_E_OFFSET 0x20 -#define IP4_RUL_V4_NR_E 96 - - -#define IP4_RUL_M0 5 -#define IP4_RUL_M0_OFFSET 0x59000 -#define IP4_RUL_M0_E_LENGTH 4 -#define IP4_RUL_M0_E_OFFSET 0x20 -#define IP4_RUL_M0_NR_E 96 - -#define DIPM -#define IP4_RUL_M0_DIPM_BOFFSET 0 -#define IP4_RUL_M0_DIPM_BLEN 32 -#define IP4_RUL_M0_DIPM_FLAG HSL_RW - - -#define IP4_RUL_M1 6 -#define IP4_RUL_M1_OFFSET 0x59004 -#define IP4_RUL_M1_E_LENGTH 4 -#define IP4_RUL_M1_E_OFFSET 0x20 -#define IP4_RUL_M1_NR_E 96 - -#define SIPM -#define IP4_RUL_M1_SIPM_BOFFSET 0 -#define IP4_RUL_M1_SIPM_BLEN 32 -#define IP4_RUL_M1_SIPM_FLAG HSL_RW - - -#define IP4_RUL_M2 7 -#define IP4_RUL_M2_OFFSET 0x59008 -#define IP4_RUL_M2_E_LENGTH 4 -#define IP4_RUL_M2_E_OFFSET 0x20 -#define IP4_RUL_M2_NR_E 96 - -#define IP4PROTM -#define IP4_RUL_M2_IP4PROTM_BOFFSET 0 -#define IP4_RUL_M2_IP4PROTM_BLEN 8 -#define IP4_RUL_M2_IP4PROTM_FLAG HSL_RW - -#define IP4DSCPM -#define IP4_RUL_M2_IP4DSCPM_BOFFSET 8 -#define IP4_RUL_M2_IP4DSCPM_BLEN 8 -#define IP4_RUL_M2_IP4DSCPM_FLAG HSL_RW - -#define IP4DPORTM -#define IP4_RUL_M2_IP4DPORTM_BOFFSET 16 -#define IP4_RUL_M2_IP4DPORTM_BLEN 16 -#define IP4_RUL_M2_IP4DPORTM_FLAG HSL_RW - - -#define IP4_RUL_M3 8 -#define IP4_RUL_M3_OFFSET 0x5900c -#define IP4_RUL_M3_E_LENGTH 4 -#define IP4_RUL_M3_E_OFFSET 0x20 -#define IP4_RUL_M3_NR_E 96 - -#define IP4TCPFLAGM -#define IP4_RUL_M3_IP4TCPFLAGM_BOFFSET 24 -#define IP4_RUL_M3_IP4TCPFLAGM_BLEN 6 -#define IP4_RUL_M3_IP4TCPFLAGM_FLAG HSL_RW - -#define IP4DHCPM -#define IP4_RUL_M3_IP4DHCPM_BOFFSET 22 -#define IP4_RUL_M3_IP4DHCPM_BLEN 1 -#define IP4_RUL_M3_IP4DHCPM_FLAG HSL_RW - -#define IP4RIPM -#define IP4_RUL_M3_IP4RIPM_BOFFSET 21 -#define IP4_RUL_M3_IP4RIPM_BLEN 1 -#define IP4_RUL_M3_IP4RIPM_FLAG HSL_RW - -#define IP4DPORTM_EN -#define IP4_RUL_M3_IP4DPORTM_EN_BOFFSET 17 -#define IP4_RUL_M3_IP4DPORTM_EN_BLEN 1 -#define IP4_RUL_M3_IP4DPORTM_EN_FLAG HSL_RW - -#define IP4SPORTM_EN -#define IP4_RUL_M3_IP4SPORTM_EN_BOFFSET 16 -#define IP4_RUL_M3_IP4SPORTM_EN_BLEN 1 -#define IP4_RUL_M3_IP4SPORTM_EN_FLAG HSL_RW - -#define IP4SPORTM -#define IP4_RUL_M3_IP4SPORTM_BOFFSET 0 -#define IP4_RUL_M3_IP4SPORTM_BLEN 16 -#define IP4_RUL_M3_IP4SPORTM_FLAG HSL_RW - -#define IP4ICMPTYPM -#define IP4_RUL_M3_IP4ICMPTYPM_BOFFSET 8 -#define IP4_RUL_M3_IP4ICMPTYPM_BLEN 8 -#define IP4_RUL_M3_IP4ICMPTYPM_FLAG HSL_RW - -#define IP4ICMPCODEM -#define IP4_RUL_M3_IP4ICMPCODEM_BOFFSET 0 -#define IP4_RUL_M3_IP4ICMPCODEM_BLEN 8 -#define IP4_RUL_M3_IP4ICMPCODEM_FLAG HSL_RW - - -#define IP4_RUL_M4 9 -#define IP4_RUL_M4_OFFSET 0x59010 -#define IP4_RUL_M4_E_LENGTH 4 -#define IP4_RUL_M4_E_OFFSET 0x20 -#define IP4_RUL_M4_NR_E 32 - - - - - /* IP6 Type1 Rule Field Define */ -#define IP6_RUL1_V0 0 -#define IP6_RUL1_V0_OFFSET 0x58000 -#define IP6_RUL1_V0_E_LENGTH 4 -#define IP6_RUL1_V0_E_OFFSET 0x20 -#define IP6_RUL1_V0_NR_E 96 - -#define IP6_DIPV0 -#define IP6_RUL1_V0_IP6_DIPV0_BOFFSET 0 -#define IP6_RUL1_V0_IP6_DIPV0_BLEN 32 -#define IP6_RUL1_V0_IP6_DIPV0_FLAG HSL_RW - - -#define IP6_RUL1_V1 1 -#define IP6_RUL1_V1_OFFSET 0x58004 -#define IP6_RUL1_V1_E_LENGTH 4 -#define IP6_RUL1_V1_E_OFFSET 0x20 -#define IP6_RUL1_V1_NR_E 96 - -#define IP6_DIPV1 -#define IP6_RUL1_V1_IP6_DIPV1_BOFFSET 0 -#define IP6_RUL1_V1_IP6_DIPv1_BLEN 32 -#define IP6_RUL1_V1_IP6_DIPV1_FLAG HSL_RW - - -#define IP6_RUL1_V2 2 -#define IP6_RUL1_V2_OFFSET 0x58008 -#define IP6_RUL1_V2_E_LENGTH 4 -#define IP6_RUL1_V2_E_OFFSET 0x20 -#define IP6_RUL1_V2_NR_E 96 - -#define IP6_DIPV2 -#define IP6_RUL1_V2_IP6_DIPV2_BOFFSET 0 -#define IP6_RUL1_V2_IP6_DIPv2_BLEN 32 -#define IP6_RUL1_V2_IP6_DIPV2_FLAG HSL_RW - - -#define IP6_RUL1_V3 3 -#define IP6_RUL1_V3_OFFSET 0x5800c -#define IP6_RUL1_V3_E_LENGTH 4 -#define IP6_RUL1_V3_E_OFFSET 0x20 -#define IP6_RUL1_V3_NR_E 96 - -#define IP6_DIPV3 -#define IP6_RUL1_V3_IP6_DIPV3_BOFFSET 0 -#define IP6_RUL1_V3_IP6_DIPv3_BLEN 32 -#define IP6_RUL1_V3_IP6_DIPV3_FLAG HSL_RW - - -#define IP6_RUL1_V4 4 -#define IP6_RUL1_V4_OFFSET 0x58010 -#define IP6_RUL1_V4_E_LENGTH 4 -#define IP6_RUL1_V4_E_OFFSET 0x20 -#define IP6_RUL1_V4_NR_E 96 - - -#define IP6_RUL1_M0 5 -#define IP6_RUL1_M0_OFFSET 0x59000 -#define IP6_RUL1_M0_E_LENGTH 4 -#define IP6_RUL1_M0_E_OFFSET 0x20 -#define IP6_RUL1_M0_NR_E 96 - -#define IP6_DIPM0 -#define IP6_RUL1_M0_IP6_DIPM0_BOFFSET 0 -#define IP6_RUL1_M0_IP6_DIPM0_BLEN 32 -#define IP6_RUL1_M0_IP6_DIPM0_FLAG HSL_RW - - -#define IP6_RUL1_M1 6 -#define IP6_RUL1_M1_OFFSET 0x59004 -#define IP6_RUL1_M1_E_LENGTH 4 -#define IP6_RUL1_M1_E_OFFSET 0x20 -#define IP6_RUL1_M1_NR_E 96 - -#define IP6_DIPM1 -#define IP6_RUL1_M1_IP6_DIPM1_BOFFSET 0 -#define IP6_RUL1_M1_IP6_DIPM1_BLEN 32 -#define IP6_RUL1_M1_IP6_DIPM1_FLAG HSL_RW - - -#define IP6_RUL1_M2 7 -#define IP6_RUL1_M2_OFFSET 0x59008 -#define IP6_RUL1_M2_E_LENGTH 4 -#define IP6_RUL1_M2_E_OFFSET 0x20 -#define IP6_RUL1_M2_NR_E 96 - -#define IP6_DIPM2 -#define IP6_RUL1_M2_IP6_DIPM2_BOFFSET 0 -#define IP6_RUL1_M2_IP6_DIPM2_BLEN 32 -#define IP6_RUL1_M2_IP6_DIPM2_FLAG HSL_RW - - -#define IP6_RUL1_M3 8 -#define IP6_RUL1_M3_OFFSET 0x5900c -#define IP6_RUL1_M3_E_LENGTH 4 -#define IP6_RUL1_M3_E_OFFSET 0x20 -#define IP6_RUL1_M3_NR_E 96 - -#define IP6_DIPM3 -#define IP6_RUL1_M3_IP6_DIPM3_BOFFSET 0 -#define IP6_RUL1_M3_IP6_DIPM3_BLEN 32 -#define IP6_RUL1_M3_IP6_DIPM3_FLAG HSL_RW - - -#define IP6_RUL1_M4 9 -#define IP6_RUL1_M4_OFFSET 0x59010 -#define IP6_RUL1_M4_E_LENGTH 4 -#define IP6_RUL1_M4_E_OFFSET 0x20 -#define IP6_RUL1_M4_NR_E 96 - - - - - /* IP6 Type2 Rule Field Define */ -#define IP6_RUL2_V0 0 -#define IP6_RUL2_V0_OFFSET 0x58000 -#define IP6_RUL2_V0_E_LENGTH 4 -#define IP6_RUL2_V0_E_OFFSET 0x20 -#define IP6_RUL2_V0_NR_E 96 - -#define IP6_SIPV0 -#define IP6_RUL2_V0_IP6_SIPV0_BOFFSET 0 -#define IP6_RUL2_V0_IP6_SIPv0_BLEN 32 -#define IP6_RUL2_V0_IP6_SIPV0_FLAG HSL_RW - - -#define IP6_RUL2_V1 1 -#define IP6_RUL2_V1_OFFSET 0x58004 -#define IP6_RUL2_V1_E_LENGTH 4 -#define IP6_RUL2_V1_E_OFFSET 0x20 -#define IP6_RUL2_V1_NR_E 96 - -#define IP6_SIPV1 -#define IP6_RUL2_V1_IP6_SIPV1_BOFFSET 0 -#define IP6_RUL2_V1_IP6_SIPv1_BLEN 32 -#define IP6_RUL2_V1_IP6_SIPV1_FLAG HSL_RW - - -#define IP6_RUL2_V2 2 -#define IP6_RUL2_V2_OFFSET 0x58008 -#define IP6_RUL2_V2_E_LENGTH 4 -#define IP6_RUL2_V2_E_OFFSET 0x20 -#define IP6_RUL2_V2_NR_E 96 - -#define IP6_SIPV2 -#define IP6_RUL2_V2_IP6_SIPV2_BOFFSET 0 -#define IP6_RUL2_V2_IP6_SIPv2_BLEN 32 -#define IP6_RUL2_V2_IP6_SIPV2_FLAG HSL_RW - - -#define IP6_RUL2_V3 3 -#define IP6_RUL2_V3_OFFSET 0x5800c -#define IP6_RUL2_V3_E_LENGTH 4 -#define IP6_RUL2_V3_E_OFFSET 0x20 -#define IP6_RUL2_V3_NR_E 96 - -#define IP6_SIPV3 -#define IP6_RUL2_V3_IP6_SIPV3_BOFFSET 0 -#define IP6_RUL2_V3_IP6_SIPv3_BLEN 32 -#define IP6_RUL2_V3_IP6_SIPV3_FLAG HSL_RW - - -#define IP6_RUL2_V4 4 -#define IP6_RUL2_V4_OFFSET 0x58010 -#define IP6_RUL2_V4_E_LENGTH 4 -#define IP6_RUL2_V4_E_OFFSET 0x20 -#define IP6_RUL2_V4_NR_E 96 - - -#define IP6_RUL2_M0 5 -#define IP6_RUL2_M0_OFFSET 0x59000 -#define IP6_RUL2_M0_E_LENGTH 4 -#define IP6_RUL2_M0_E_OFFSET 0x20 -#define IP6_RUL2_M0_NR_E 96 - -#define IP6_SIPM0 -#define IP6_RUL2_M0_IP6_SIPM0_BOFFSET 0 -#define IP6_RUL2_M0_IP6_SIPM0_BLEN 32 -#define IP6_RUL2_M0_IP6_SIPM0_FLAG HSL_RW - - -#define IP6_RUL2_M1 6 -#define IP6_RUL2_M1_OFFSET 0x59004 -#define IP6_RUL2_M1_E_LENGTH 4 -#define IP6_RUL2_M1_E_OFFSET 0x20 -#define IP6_RUL2_M1_NR_E 96 - -#define IP6_SIPM1 -#define IP6_RUL2_M1_IP6_DIPM1_BOFFSET 0 -#define IP6_RUL2_M1_IP6_DIPM1_BLEN 32 -#define IP6_RUL2_M1_IP6_DIPM1_FLAG HSL_RW - - -#define IP6_RUL2_M2 7 -#define IP6_RUL2_M2_OFFSET 0x59008 -#define IP6_RUL2_M2_E_LENGTH 4 -#define IP6_RUL2_M2_E_OFFSET 0x20 -#define IP6_RUL2_M2_NR_E 96 - -#define IP6_SIPM2 -#define IP6_RUL2_M2_IP6_DIPM2_BOFFSET 0 -#define IP6_RUL2_M2_IP6_DIPM2_BLEN 32 -#define IP6_RUL2_M2_IP6_DIPM2_FLAG HSL_RW - - -#define IP6_RUL2_M3 8 -#define IP6_RUL2_M3_OFFSET 0x5900c -#define IP6_RUL2_M3_E_LENGTH 4 -#define IP6_RUL2_M3_E_OFFSET 0x20 -#define IP6_RUL2_M3_NR_E 96 - -#define IP6_SIPM3 -#define IP6_RUL2_M3_IP6_SIPM3_BOFFSET 0 -#define IP6_RUL2_M3_IP6_SIPM3_BLEN 32 -#define IP6_RUL2_M3_IP6_SIPM3_FLAG HSL_RW - - -#define IP6_RUL2_M4 9 -#define IP6_RUL2_M4_OFFSET 0x59010 -#define IP6_RUL2_M4_E_LENGTH 4 -#define IP6_RUL2_M4_E_OFFSET 0x20 -#define IP6_RUL2_M4_NR_E 96 - - - - - /* IP6 Type3 Rule Field Define */ -#define IP6_RUL3_V0 0 -#define IP6_RUL3_V0_OFFSET 0x58000 -#define IP6_RUL3_V0_E_LENGTH 4 -#define IP6_RUL3_V0_E_OFFSET 0x20 -#define IP6_RUL3_V0_NR_E 96 - -#define IP6PROTV -#define IP6_RUL3_V0_IP6PROTV_BOFFSET 0 -#define IP6_RUL3_V0_IP6PROTV_BLEN 8 -#define IP6_RUL3_V0_IP6PROTV_FLAG HSL_RW - -#define IP6DSCPV -#define IP6_RUL3_V0_IP6DSCPV_BOFFSET 8 -#define IP6_RUL3_V0_IP6DSCPV_BLEN 8 -#define IP6_RUL3_V0_IP6DSCPV_FLAG HSL_RW - - -#define IP6_RUL3_V1 1 -#define IP6_RUL3_V1_OFFSET 0x58004 -#define IP6_RUL3_V1_E_LENGTH 4 -#define IP6_RUL3_V1_E_OFFSET 0x20 -#define IP6_RUL3_V1_NR_E 96 - -#define IP6LABEL1V -#define IP6_RUL3_V1_IP6LABEL1V_BOFFSET 16 -#define IP6_RUL3_V1_IP6LABEL1V_BLEN 16 -#define IP6_RUL3_V1_IP6LABEL1V_FLAG HSL_RW - - -#define IP6_RUL3_V2 2 -#define IP6_RUL3_V2_OFFSET 0x58008 -#define IP6_RUL3_V2_E_LENGTH 4 -#define IP6_RUL3_V2_E_OFFSET 0x20 -#define IP6_RUL3_V2_NR_E 96 - -#define IP6LABEL2V -#define IP6_RUL3_V2_IP6LABEL2V_BOFFSET 0 -#define IP6_RUL3_V2_IP6LABEL2V_BLEN 4 -#define IP6_RUL3_V2_IP6LABEL2V_FLAG HSL_RW - -#define IP6DPORTV -#define IP6_RUL3_V2_IP6DPORTV_BOFFSET 16 -#define IP6_RUL3_V2_IP6DPORTV_BLEN 16 -#define IP6_RUL3_V2_IP6DPORTV_FLAG HSL_RW - - -#define IP6_RUL3_V3 3 -#define IP6_RUL3_V3_OFFSET 0x5800c -#define IP6_RUL3_V3_E_LENGTH 4 -#define IP6_RUL3_V3_E_OFFSET 0x20 -#define IP6_RUL3_V3_NR_E 96 - -#define IP6TCPFLAGV -#define IP6_RUL3_V3_IP6TCPFLAGV_BOFFSET 24 -#define IP6_RUL3_V3_IP6TCPFLAGV_BLEN 6 -#define IP6_RUL3_V3_IP6TCPFLAGV_FLAG HSL_RW - -#define IP6FWDTYPV -#define IP6_RUL3_V3_IP6FWDTYPV_BOFFSET 23 -#define IP6_RUL3_V3_IP6FWDTYPV_BLEN 1 -#define IP6_RUL3_V3_IP6FWDTYPV_FLAG HSL_RW - -#define IP6DHCPV -#define IP6_RUL3_V3_IP6DHCPV_BOFFSET 22 -#define IP6_RUL3_V3_IP6DHCPV_BLEN 1 -#define IP6_RUL3_V3_IP6DHCPV_FLAG HSL_RW - -#define ICMP6_EN -#define IP6_RUL3_V3_ICMP6_EN_BOFFSET 20 -#define IP6_RUL3_V3_ICMP6_EN_BLEN 1 -#define IP6_RUL3_V3_ICMP6_EN_FLAG HSL_RW - -#define IP6SPORTV -#define IP6_RUL3_V3_IP6SPORTV_BOFFSET 0 -#define IP6_RUL3_V3_IP6SPORTV_BLEN 16 -#define IP6_RUL3_V3_IP6SPORTV_FLAG HSL_RW - -#define IP6ICMPTYPV -#define IP6_RUL3_V3_IP6ICMPTYPV_BOFFSET 8 -#define IP6_RUL3_V3_IP6ICMPTYPV_BLEN 8 -#define IP6_RUL3_V3_IP6ICMPTYPV_FLAG HSL_RW - -#define IP6ICMPCODEV -#define IP6_RUL3_V3_IP6ICMPCODEV_BOFFSET 0 -#define IP6_RUL3_V3_IP6ICMPCODEV_BLEN 8 -#define IP6_RUL3_V3_IP6ICMPCODEV_FLAG HSL_RW - - -#define IP6_RUL3_V4 4 -#define IP6_RUL3_V4_OFFSET 0x58010 -#define IP6_RUL3_V4_E_LENGTH 4 -#define IP6_RUL3_V4_E_OFFSET 0x20 -#define IP6_RUL3_V4_NR_E 96 - - -#define IP6_RUL3_M0 5 -#define IP6_RUL3_M0_OFFSET 0x59000 -#define IP6_RUL3_M0_E_LENGTH 4 -#define IP6_RUL3_M0_E_OFFSET 0x20 -#define IP6_RUL3_M0_NR_E 96 - -#define IP6PROTM -#define IP6_RUL3_M0_IP6PROTM_BOFFSET 0 -#define IP6_RUL3_M0_IP6PROTM_BLEN 8 -#define IP6_RUL3_M0_IP6PROTM_FLAG HSL_RW - -#define IP6DSCPM -#define IP6_RUL3_M0_IP6DSCPM_BOFFSET 8 -#define IP6_RUL3_M0_IP6DSCPM_BLEN 8 -#define IP6_RUL3_M0_IP6DSCPM_FLAG HSL_RW - - -#define IP6_RUL3_M1 6 -#define IP6_RUL3_M1_OFFSET 0x59004 -#define IP6_RUL3_M1_E_LENGTH 4 -#define IP6_RUL3_M1_E_OFFSET 0x20 -#define IP6_RUL3_M1_NR_E 96 - -#define IP6LABEL1M -#define IP6_RUL3_M1_IP6LABEL1M_BOFFSET 16 -#define IP6_RUL3_M1_IP6LABEL1M_BLEN 16 -#define IP6_RUL3_M1_IP6LABEL1M_FLAG HSL_RW - - -#define IP6_RUL3_M2 7 -#define IP6_RUL3_M2_OFFSET 0x59008 -#define IP6_RUL3_M2_E_LENGTH 4 -#define IP6_RUL3_M2_E_OFFSET 0x20 -#define IP6_RUL3_M2_NR_E 96 - -#define IP6LABEL2M -#define IP6_RUL3_M2_IP6LABEL2M_BOFFSET 0 -#define IP6_RUL3_M2_IP6LABEL2M_BLEN 4 -#define IP6_RUL3_M2_IP6LABEL21M_FLAG HSL_RW - -#define IP6DPORTM -#define IP6_RUL3_M2_IP6DPORTM_BOFFSET 16 -#define IP6_RUL3_M2_IP6DPORTM_BLEN 16 -#define IP6_RUL3_M2_IP6DPORTM_FLAG HSL_RW - - -#define IP6_RUL3_M3 8 -#define IP6_RUL3_M3_OFFSET 0x5900c -#define IP6_RUL3_M3_E_LENGTH 4 -#define IP6_RUL3_M3_E_OFFSET 0x20 -#define IP6_RUL3_M3_NR_E 96 - -#define IP6TCPFLAGM -#define IP6_RUL3_M3_IP6TCPFLAGM_BOFFSET 24 -#define IP6_RUL3_M3_IP6TCPFLAGM_BLEN 6 -#define IP6_RUL3_M3_IP6TCPFLAGM_FLAG HSL_RW - -#define IP6RWDTYPM -#define IP6_RUL3_M3_IP6RWDTYPV_BOFFSET 23 -#define IP6_RUL3_M3_IP6RWDTYPV_BLEN 1 -#define IP6_RUL3_M3_IP6RWDTYPV_FLAG HSL_RW - -#define IP6DHCPM -#define IP6_RUL3_M3_IP6DHCPM_BOFFSET 22 -#define IP6_RUL3_M3_IP6DHCPM_BLEN 1 -#define IP6_RUL3_M3_IP6DHCPM_FLAG HSL_RW - -#define IP6DPORTM_EN -#define IP6_RUL3_M3_IP6DPORTM_EN_BOFFSET 17 -#define IP6_RUL3_M3_IP6DPORTM_EN_BLEN 1 -#define IP6_RUL3_M3_IP6DPORTM_EN_FLAG HSL_RW - -#define IP6SPORTM_EN -#define IP6_RUL3_M3_IP6SPORTM_EN_BOFFSET 16 -#define IP6_RUL3_M3_IP6SPORTM_EN_BLEN 1 -#define IP6_RUL3_M3_IP6SPORTM_EN_FLAG HSL_RW - -#define IP6SPORTM -#define IP6_RUL3_M3_IP6SPORTM_BOFFSET 0 -#define IP6_RUL3_M3_IP6SPORTM_BLEN 16 -#define IP6_RUL3_M3_IP6SPORTM_FLAG HSL_RW - -#define IP6ICMPTYPM -#define IP6_RUL3_M3_IP6ICMPTYPM_BOFFSET 8 -#define IP6_RUL3_M3_IP6ICMPTYPM_BLEN 8 -#define IP6_RUL3_M3_IP6ICMPTYPM_FLAG HSL_RW - -#define IP6ICMPCODEM -#define IP6_RUL3_M3_IP6ICMPCODEM_BOFFSET 0 -#define IP6_RUL3_M3_IP6ICMPCODEM_BLEN 8 -#define IP6_RUL3_M3_IP6ICMPCODEM_FLAG HSL_RW - - -#define IP6_RUL3_M4 9 -#define IP6_RUL3_M4_OFFSET 0x59010 -#define IP6_RUL3_M4_E_LENGTH 4 -#define IP6_RUL3_M4_E_OFFSET 0x20 -#define IP6_RUL3_M4_NR_E 96 - - - - - /* Enhanced MAC Type Rule Field Define */ -#define EHMAC_RUL_V0 0 -#define EHMAC_RUL_V0_OFFSET 0x58000 -#define EHMAC_RUL_V0_E_LENGTH 4 -#define EHMAC_RUL_V0_E_OFFSET 0x20 -#define EHMAC_RUL_V0_NR_E 96 - -#define DAV_BYTE2 -#define EHMAC_RUL_V0_DAV_BYTE2_BOFFSET 24 -#define EHMAC_RUL_V0_DAV_BYTE2_BLEN 8 -#define EHMAC_RUL_V0_DAV_BYTE2_FLAG HSL_RW - -#define DAV_BYTE3 -#define EHMAC_RUL_V0_DAV_BYTE3_BOFFSET 16 -#define EHMAC_RUL_V0_DAV_BYTE3_BLEN 8 -#define EHMAC_RUL_V0_DAV_BYTE3_FLAG HSL_RW - -#define DAV_BYTE4 -#define EHMAC_RUL_V0_DAV_BYTE4_BOFFSET 8 -#define EHMAC_RUL_V0_DAV_BYTE4_BLEN 8 -#define EHMAC_RUL_V0_DAV_BYTE4_FLAG HSL_RW - -#define DAV_BYTE5 -#define EHMAC_RUL_V0_DAV_BYTE5_BOFFSET 0 -#define EHMAC_RUL_V0_DAV_BYTE5_BLEN 8 -#define EHMAC_RUL_V0_DAV_BYTE5_FLAG HSL_RW - - -#define EHMAC_RUL_V1 1 -#define EHMAC_RUL_V1_OFFSET 0x58004 -#define EHMAC_RUL_V1_E_LENGTH 4 -#define EHMAC_RUL_V1_E_OFFSET 0x20 -#define EHMAC_RUL_V1_NR_E 96 - -#define SAV_BYTE4 -#define EHMAC_RUL_V1_SAV_BYTE4_BOFFSET 24 -#define EHMAC_RUL_V1_SAV_BYTE4_BLEN 8 -#define EHMAC_RUL_V1_SAV_BYTE4_FLAG HSL_RW - -#define SAV_BYTE5 -#define EHMAC_RUL_V1_SAV_BYTE5_BOFFSET 16 -#define EHMAC_RUL_V1_SAV_BYTE5_BLEN 8 -#define EHMAC_RUL_V1_SAV_BYTE5_FLAG HSL_RW - -#define DAV_BYTE0 -#define EHMAC_RUL_V1_DAV_BYTE0_BOFFSET 8 -#define EHMAC_RUL_V1_DAV_BYTE0_BLEN 8 -#define EHMAC_RUL_V1_DAV_BYTE0_FLAG HSL_RW - -#define DAV_BYTE1 -#define EHMAC_RUL_V1_DAV_BYTE1_BOFFSET 0 -#define EHMAC_RUL_V1_DAV_BYTE1_BLEN 8 -#define EHMAC_RUL_V1_DAV_BYTE1_FLAG HSL_RW - - -#define EHMAC_RUL_V2 2 -#define EHMAC_RUL_V2_OFFSET 0x58008 -#define EHMAC_RUL_V2_E_LENGTH 4 -#define EHMAC_RUL_V2_E_OFFSET 0x20 -#define EHMAC_RUL_V2_NR_E 96 - -#define CTAG_VIDLV -#define EHMAC_RUL_V2_CTAG_VIDLV_BOFFSET 24 -#define EHMAC_RUL_V2_CTAG_VIDLV_BLEN 8 -#define EHMAC_RUL_V2_CTAG_VIDLV_FLAG HSL_RW - -#define STAG_PRIV -#define EHMAC_RUL_V2_STAG_PRIV_BOFFSET 21 -#define EHMAC_RUL_V2_STAG_PRIV_BLEN 3 -#define EHMAC_RUL_V2_STAG_PRIV_FLAG HSL_RW - -#define STAG_DEIV -#define EHMAC_RUL_V2_STAG_DEIV_BOFFSET 20 -#define EHMAC_RUL_V2_STAG_DEIV_BLEN 1 -#define EHMAC_RUL_V2_STAG_DEIV_FLAG HSL_RW - -#define STAG_VIDV -#define EHMAC_RUL_V2_STAG_VIDV_BOFFSET 8 -#define EHMAC_RUL_V2_STAG_VIDV_BLEN 12 -#define EHMAC_RUL_V2_STAG_VIDV_FLAG HSL_RW - -#define SAV_BYTE3 -#define EHMAC_RUL_V2_SAV_BYTE3_BOFFSET 0 -#define EHMAC_RUL_V2_SAV_BYTE3_BLEN 8 -#define EHMAC_RUL_V2_SAV_BYTE3_FLAG HSL_RW - - -#define EHMAC_RUL_V3 3 -#define EHMAC_RUL_V3_ID 13 -#define EHMAC_RUL_V3_OFFSET 0x5800c -#define EHMAC_RUL_V3_E_LENGTH 4 -#define EHMAC_RUL_V3_E_OFFSET 0x20 -#define EHMAC_RUL_V3_NR_E 96 - -#define STAGGEDM -#define EHMAC_RUL_V3_STAGGEDM_BOFFSET 31 -#define EHMAC_RUL_V3_STAGGEDM_BLEN 1 -#define EHMAC_RUL_V3_STAGGEDM_FLAG HSL_RW - -#define STAGGEDV -#define EHMAC_RUL_V3_STAGGEDV_BOFFSET 30 -#define EHMAC_RUL_V3_STAGGEDV_BLEN 1 -#define EHMAC_RUL_V3_STAGGEDV_FLAG HSL_RW - -#define DA_EN -#define EHMAC_RUL_V3_DA_EN_BOFFSET 25 -#define EHMAC_RUL_V3_DA_EN_BLEN 1 -#define EHMAC_RUL_V3_DA_EN_FLAG HSL_RW - -#define SVIDMSK -#define EHMAC_RUL_V3_SVIDMSK_BOFFSET 24 -#define EHMAC_RUL_V3_SVIDMSK_BLEN 1 -#define EHMAC_RUL_V3_SVIDMSK_FLAG HSL_RW - -#define ETHTYPV -#define EHMAC_RUL_V3_ETHTYPV_BOFFSET 8 -#define EHMAC_RUL_V3_ETHTYPV_BLEN 16 -#define EHMAC_RUL_V3_ETHTYPV_FLAG HSL_RW - -#define CTAG_PRIV -#define EHMAC_RUL_V3_CTAG_PRIV_BOFFSET 5 -#define EHMAC_RUL_V3_CTAG_PRIV_BLEN 3 -#define EHMAC_RUL_V3_CTAG_PRIV_FLAG HSL_RW - -#define CTAG_CFIV -#define EHMAC_RUL_V3_CTAG_CFIV_BOFFSET 4 -#define EHMAC_RUL_V3_CTAG_CFIV_BLEN 1 -#define EHMAC_RUL_V3_CTAG_CFIV_FLAG HSL_RW - -#define CTAG_VIDHV -#define EHMAC_RUL_V3_CTAG_VIDHV_BOFFSET 0 -#define EHMAC_RUL_V3_CTAG_VIDHV_BLEN 4 -#define EHMAC_RUL_V3_CTAG_VIDHV_FLAG HSL_RW - - -#define EHMAC_RUL_V4 4 -#define EHMAC_RUL_V4_OFFSET 0x58010 -#define EHMAC_RUL_V4_E_LENGTH 4 -#define EHMAC_RUL_V4_E_OFFSET 0x20 -#define EHMAC_RUL_V4_NR_E 96 - - -#define EHMAC_RUL_M0 5 -#define EHMAC_RUL_M0_OFFSET 0x59000 -#define EHMAC_RUL_M0_E_LENGTH 4 -#define EHMAC_RUL_M0_E_OFFSET 0x20 -#define EHMAC_RUL_M0_NR_E 96 - -#define DAM_BYTE2 -#define EHMAC_RUL_M0_DAM_BYTE2_BOFFSET 24 -#define EHMAC_RUL_M0_DAM_BYTE2_BLEN 8 -#define EHMAC_RUL_M0_DAM_BYTE2_FLAG HSL_RW - -#define DAM_BYTE3 -#define EHMAC_RUL_M0_DAM_BYTE3_BOFFSET 16 -#define EHMAC_RUL_M0_DAM_BYTE3_BLEN 8 -#define EHMAC_RUL_M0_DAM_BYTE3_FLAG HSL_RW - -#define DAM_BYTE4 -#define EHMAC_RUL_M0_DAM_BYTE4_BOFFSET 8 -#define EHMAC_RUL_M0_DAM_BYTE4_BLEN 8 -#define EHMAC_RUL_M0_DAM_BYTE4_FLAG HSL_RW - -#define DAM_BYTE5 -#define EHMAC_RUL_M0_DAM_BYTE5_BOFFSET 0 -#define EHMAC_RUL_M0_DAM_BYTE5_BLEN 8 -#define EHMAC_RUL_M0_DAM_BYTE5_FLAG HSL_RW - - -#define EHMAC_RUL_M1 6 -#define EHMAC_RUL_M1_OFFSET 0x59004 -#define EHMAC_RUL_M1_E_LENGTH 4 -#define EHMAC_RUL_M1_E_OFFSET 0x20 -#define EHMAC_RUL_M1_NR_E 96 - -#define SAM_BYTE4 -#define EHMAC_RUL_M1_SAM_BYTE4_BOFFSET 24 -#define EHMAC_RUL_M1_SAM_BYTE4_BLEN 8 -#define EHMAC_RUL_M1_SAM_BYTE4_FLAG HSL_RW - -#define SAM_BYTE5 -#define EHMAC_RUL_M1_SAM_BYTE5_BOFFSET 16 -#define EHMAC_RUL_M1_SAM_BYTE5_BLEN 8 -#define EHMAC_RUL_M1_SAM_BYTE5_FLAG HSL_RW - -#define DAM_BYTE0 -#define EHMAC_RUL_M1_DAM_BYTE0_BOFFSET 8 -#define EHMAC_RUL_M1_DAM_BYTE0_BLEN 8 -#define EHMAC_RUL_M1_DAM_BYTE0_FLAG HSL_RW - -#define DAM_BYTE1 -#define EHMAC_RUL_M1_DAM_BYTE1_BOFFSET 0 -#define EHMAC_RUL_M1_DAM_BYTE1_BLEN 8 -#define EHMAC_RUL_M1_DAM_BYTE1_FLAG HSL_RW - - -#define EHMAC_RUL_M2 7 -#define EHMAC_RUL_M2_OFFSET 0x59008 -#define EHMAC_RUL_M2_E_LENGTH 4 -#define EHMAC_RUL_M2_E_OFFSET 0x20 -#define EHMAC_RUL_M2_NR_E 96 - -#define CTAG_VIDLM -#define EHMAC_RUL_M2_CTAG_VIDLM_BOFFSET 24 -#define EHMAC_RUL_M2_CTAG_VIDLM_BLEN 8 -#define EHMAC_RUL_M2_CTAG_VIDLM_FLAG HSL_RW - -#define STAG_PRIM -#define EHMAC_RUL_M2_STAG_PRIM_BOFFSET 21 -#define EHMAC_RUL_M2_STAG_PRIM_BLEN 3 -#define EHMAC_RUL_M2_STAG_PRIM_FLAG HSL_RW - -#define STAG_DEIM -#define EHMAC_RUL_M2_STAG_DEIM_BOFFSET 20 -#define EHMAC_RUL_M2_STAG_DEIM_BLEN 1 -#define EHMAC_RUL_M2_STAG_DEIM_FLAG HSL_RW - -#define STAG_VIDM -#define EHMAC_RUL_M2_STAG_VIDM_BOFFSET 8 -#define EHMAC_RUL_M2_STAG_VIDM_BLEN 12 -#define EHMAC_RUL_M2_STAG_VIDM_FLAG HSL_RW - -#define SAM_BYTE3 -#define EHMAC_RUL_M2_SAM_BYTE3_BOFFSET 0 -#define EHMAC_RUL_M2_SAM_BYTE3_BLEN 8 -#define EHMAC_RUL_M2_SAM_BYTE3_FLAG HSL_RW - - -#define EHMAC_RUL_M3 8 -#define EHMAC_RUL_M3_OFFSET 0x5900c -#define EHMAC_RUL_M3_E_LENGTH 4 -#define EHMAC_RUL_M3_E_OFFSET 0x20 -#define EHMAC_RUL_M3_NR_E 96 - -#define ETHTYPM -#define EHMAC_RUL_M3_ETHTYPM_BOFFSET 8 -#define EHMAC_RUL_M3_ETHTYPM_BLEN 16 -#define EHMAC_RUL_M3_ETHTYPM_FLAG HSL_RW - -#define CTAG_PRIM -#define EHMAC_RUL_M3_CTAG_PRIM_BOFFSET 5 -#define EHMAC_RUL_M3_CTAG_PRIM_BLEN 3 -#define EHMAC_RUL_M3_CTAG_PRIM_FLAG HSL_RW - -#define CTAG_CFIM -#define EHMAC_RUL_M3_CTAG_CFIM_BOFFSET 4 -#define EHMAC_RUL_M3_CTAG_CFIM_BLEN 1 -#define EHMAC_RUL_M3_CTAG_CFIM_FLAG HSL_RW - -#define CTAG_VIDHM -#define EHMAC_RUL_M3_CTAG_VIDHM_BOFFSET 0 -#define EHMAC_RUL_M3_CTAG_VIDHM_BLEN 4 -#define EHMAC_RUL_M3_CTAG_VIDHM_FLAG HSL_RW - - -#define EHMAC_RUL_M4 9 -#define EHMAC_RUL_M4_OFFSET 0x59010 -#define EHMAC_RUL_M4_E_LENGTH 4 -#define EHMAC_RUL_M4_E_OFFSET 0x20 -#define EHMAC_RUL_M4_NR_E 96 - -#define CTAGGEDM -#define EHMAC_RUL_M4_CTAGGEDM_BOFFSET 5 -#define EHMAC_RUL_M4_CTAGGEDM_BLEN 1 -#define EHMAC_RUL_M4_CTAGGEDM_FLAG HSL_RW - -#define CTAGGEDV -#define EHMAC_RUL_M4_CTAGGEDV_BOFFSET 4 -#define EHMAC_RUL_M4_CTAGGEDV_BLEN 1 -#define EHMAC_RUL_M4_CTAGGEDV_FLAG HSL_RW - -#define CVIDMSK -#define EHMAC_RUL_M4_CVIDMSK_BOFFSET 3 -#define EHMAC_RUL_M4_CVIDMSK_BLEN 1 -#define EHMAC_RUL_M4_CVIDMSK_FLAG HSL_RW - - - - - /* PPPoE Session Table Define */ -#define PPPOE_SESSION -#define PPPOE_SESSION_OFFSET 0x5f000 -#define PPPOE_SESSION_E_LENGTH 4 -#define PPPOE_SESSION_E_OFFSET 0x4 -#define PPPOE_SESSION_NR_E 16 - -#define ENTRY_VALID -#define PPPOE_SESSION_ENTRY_VALID_BOFFSET 16 -#define PPPOE_SESSION_ENTRY_VALID_BLEN 2 -#define PPPOE_SESSION_ENTRY_VALID_FLAG HSL_RW - -#define SEESION_ID -#define PPPOE_SESSION_SEESION_ID_BOFFSET 0 -#define PPPOE_SESSION_SEESION_ID_BLEN 16 -#define PPPOE_SESSION_SEESION_ID_FLAG HSL_RW - - -#define PPPOE_EDIT -#define PPPOE_EDIT_OFFSET 0x02200 -#define PPPOE_EDIT_E_LENGTH 4 -#define PPPOE_EDIT_E_OFFSET 0x10 -#define PPPOE_EDIT_NR_E 16 - -#define EDIT_ID -#define PPPOE_EDIT_EDIT_ID_BOFFSET 0 -#define PPPOE_EDIT_EDIT_ID_BLEN 16 -#define PPPOE_EDIT_EDIT_ID_FLAG HSL_RW - - - - - /* L3 Host Entry Define */ -#define HOST_ENTRY0 -#define HOST_ENTRY0_OFFSET 0x0e80 -#define HOST_ENTRY0_E_LENGTH 4 -#define HOST_ENTRY0_E_OFFSET 0x0 -#define HOST_ENTRY0_NR_E 1 - -#define IP_ADDR -#define HOST_ENTRY0_IP_ADDR_BOFFSET 0 -#define HOST_ENTRY0_IP_ADDR_BLEN 32 -#define HOST_ENTRY0_IP_ADDR_FLAG HSL_RW - - -#define HOST_ENTRY1 -#define HOST_ENTRY1_OFFSET 0x0e84 -#define HOST_ENTRY1_E_LENGTH 4 -#define HOST_ENTRY1_E_OFFSET 0x0 -#define HOST_ENTRY1_NR_E 1 - - -#define HOST_ENTRY2 -#define HOST_ENTRY2_OFFSET 0x0e88 -#define HOST_ENTRY2_E_LENGTH 4 -#define HOST_ENTRY2_E_OFFSET 0x0 -#define HOST_ENTRY2_NR_E 1 - - -#define HOST_ENTRY3 -#define HOST_ENTRY3_OFFSET 0x0e8c -#define HOST_ENTRY3_E_LENGTH 4 -#define HOST_ENTRY3_E_OFFSET 0x0 -#define HOST_ENTRY3_NR_E 1 - - -#define HOST_ENTRY4 -#define HOST_ENTRY4_OFFSET 0x0e90 -#define HOST_ENTRY4_E_LENGTH 4 -#define HOST_ENTRY4_E_OFFSET 0x0 -#define HOST_ENTRY4_NR_E 1 - -#define MAC_ADDR2 -#define HOST_ENTRY4_MAC_ADDR2_BOFFSET 24 -#define HOST_ENTRY4_MAC_ADDR2_BLEN 8 -#define HOST_ENTRY4_MAC_ADDR2_FLAG HSL_RW - -#define MAC_ADDR3 -#define HOST_ENTRY4_MAC_ADDR3_BOFFSET 16 -#define HOST_ENTRY4_MAC_ADDR3_BLEN 8 -#define HOST_ENTRY4_MAC_ADDR3_FLAG HSL_RW - -#define MAC_ADDR4 -#define HOST_ENTRY4_MAC_ADDR4_BOFFSET 8 -#define HOST_ENTRY4_MAC_ADDR4_BLEN 8 -#define HOST_ENTRY4_MAC_ADDR4_FLAG HSL_RW - -#define MAC_ADDR5 -#define HOST_ENTRY4_MAC_ADDR5_BOFFSET 0 -#define HOST_ENTRY4_MAC_ADDR5_BLEN 8 -#define HOST_ENTRY4_MAC_ADDR5_FLAG HSL_RW - -#define HOST_ENTRY5 -#define HOST_ENTRY5_OFFSET 0x0e94 -#define HOST_ENTRY5_E_LENGTH 4 -#define HOST_ENTRY5_E_OFFSET 0x0 -#define HOST_ENTRY5_NR_E 1 - -#define CPU_ADDR -#define HOST_ENTRY5_CPU_ADDR_BOFFSET 31 -#define HOST_ENTRY5_CPU_ADDR_BLEN 1 -#define HOST_ENTRY5_CPU_ADDR_FLAG HSL_RW - -#define SRC_PORT -#define HOST_ENTRY5_SRC_PORT_BOFFSET 28 -#define HOST_ENTRY5_SRC_PORT_BLEN 3 -#define HOST_ENTRY5_SRC_PORT_FLAG HSL_RW - -#define INTF_ID -#define HOST_ENTRY5_INTF_ID_BOFFSET 16 -#define HOST_ENTRY5_INTF_ID_BLEN 12 -#define HOST_ENTRY5_INTF_ID_FLAG HSL_RW - -#define MAC_ADDR0 -#define HOST_ENTRY5_MAC_ADDR0_BOFFSET 8 -#define HOST_ENTRY5_MAC_ADDR0_BLEN 8 -#define HOST_ENTRY5_MAC_ADDR0_FLAG HSL_RW - -#define MAC_ADDR1 -#define HOST_ENTRY5_MAC_ADDR1_BOFFSET 0 -#define HOST_ENTRY5_MAC_ADDR1_BLEN 8 -#define HOST_ENTRY5_MAC_ADDR1_FLAG HSL_RW - - -#define HOST_ENTRY6 -#define HOST_ENTRY6_OFFSET 0x0e98 -#define HOST_ENTRY6_E_LENGTH 4 -#define HOST_ENTRY6_E_OFFSET 0x0 -#define HOST_ENTRY6_NR_E 1 - -#define IP_VER -#define HOST_ENTRY6_IP_VER_BOFFSET 15 -#define HOST_ENTRY6_IP_VER_BLEN 1 -#define HOST_ENTRY6_IP_VER_FLAG HSL_RW - -#define AGE_FLAG -#define HOST_ENTRY6_AGE_FLAG_BOFFSET 12 -#define HOST_ENTRY6_AGE_FLAG_BLEN 3 -#define HOST_ENTRY6_AGE_FLAG_FLAG HSL_RW - -#define PPPOE_EN -#define HOST_ENTRY6_PPPOE_EN_BOFFSET 11 -#define HOST_ENTRY6_PPPOE_EN_BLEN 1 -#define HOST_ENTRY6_PPPOE_EN_FLAG HSL_RW - -#define PPPOE_IDX -#define HOST_ENTRY6_PPPOE_IDX_BOFFSET 7 -#define HOST_ENTRY6_PPPOE_IDX_BLEN 4 -#define HOST_ENTRY6_PPPOE_IDX_FLAG HSL_RW - -#define CNT_EN -#define HOST_ENTRY6_CNT_EN_BOFFSET 6 -#define HOST_ENTRY6_CNT_EN_BLEN 1 -#define HOST_ENTRY6_CNT_EN_FLAG HSL_RW - -#define CNT_IDX -#define HOST_ENTRY6_CNT_IDX_BOFFSET 2 -#define HOST_ENTRY6_CNT_IDX_BLEN 4 -#define HOST_ENTRY6_CNT_IDX_FLAG HSL_RW - -#define ACTION -#define HOST_ENTRY6_ACTION_BOFFSET 0 -#define HOST_ENTRY6_ACTION_BLEN 2 -#define HOST_ENTRY6_ACTION_FLAG HSL_RW - - -#define HOST_ENTRY7 -#define HOST_ENTRY7_OFFSET 0x0e58 -#define HOST_ENTRY7_E_LENGTH 4 -#define HOST_ENTRY7_E_OFFSET 0x0 -#define HOST_ENTRY7_NR_E 1 - -#define TBL_BUSY -#define HOST_ENTRY7_TBL_BUSY_BOFFSET 31 -#define HOST_ENTRY7_TBL_BUSY_BLEN 1 -#define HOST_ENTRY7_TBL_BUSY_FLAG HSL_RW - -#define SPEC_SP -#define HOST_ENTRY7_SPEC_SP_BOFFSET 22 -#define HOST_ENTRY7_SPEC_SP_BLEN 1 -#define HOST_ENTRY7_SPEC_SP_FLAG HSL_RW - -#define SPEC_VID -#define HOST_ENTRY7_SPEC_VID_BOFFSET 21 -#define HOST_ENTRY7_SPEC_VID_BLEN 1 -#define HOST_ENTRY7_SPEC_VID_FLAG HSL_RW - -#define SPEC_PIP -#define HOST_ENTRY7_SPEC_PIP_BOFFSET 20 -#define HOST_ENTRY7_SPEC_PIP_BLEN 1 -#define HOST_ENTRY7_SPEC_PIP_FLAG HSL_RW - -#define SPEC_SIP -#define HOST_ENTRY7_SPEC_SIP_BOFFSET 19 -#define HOST_ENTRY7_SPEC_SIP_BLEN 1 -#define HOST_ENTRY7_SPEC_SIP_FLAG HSL_RW - -#define SPEC_STATUS -#define HOST_ENTRY7_SPEC_STATUS_BOFFSET 18 -#define HOST_ENTRY7_SPEC_STATUS_BLEN 1 -#define HOST_ENTRY7_SPEC_STATUS_FLAG HSL_RW - -#define TBL_IDX -#define HOST_ENTRY7_TBL_IDX_BOFFSET 8 -#define HOST_ENTRY7_TBL_IDX_BLEN 10 -#define HOST_ENTRY7_TBL_IDX_FLAG HSL_RW - -#define TBL_STAUS -#define HOST_ENTRY7_TBL_STAUS_BOFFSET 7 -#define HOST_ENTRY7_TBL_STAUS_BLEN 1 -#define HOST_ENTRY7_TBL_STAUS_FLAG HSL_RW - -#define TBL_SEL -#define HOST_ENTRY7_TBL_SEL_BOFFSET 4 -#define HOST_ENTRY7_TBL_SEL_BLEN 2 -#define HOST_ENTRY7_TBL_SEL_FLAG HSL_RW - -#define ENTRY_FUNC -#define HOST_ENTRY7_ENTRY_FUNC_BOFFSET 0 -#define HOST_ENTRY7_ENTRY_FUNC_BLEN 3 -#define HOST_ENTRY7_ENTRY_FUNC_FLAG HSL_RW - - - - -#define NAT_ENTRY0 -#define NAT_ENTRY0_OFFSET 0x0e80 -#define NAT_ENTRY0_E_LENGTH 4 -#define NAT_ENTRY0_E_OFFSET 0x0 -#define NAT_ENTRY0_NR_E 1 - -#define IP_ADDR -#define NAT_ENTRY0_IP_ADDR_BOFFSET 0 -#define NAT_ENTRY0_IP_ADDR_BLEN 32 -#define NAT_ENTRY0_IP_ADDR_FLAG HSL_RW - - -#define NAT_ENTRY1 -#define NAT_ENTRY1_OFFSET 0x0e84 -#define NAT_ENTRY1_E_LENGTH 4 -#define NAT_ENTRY1_E_OFFSET 0x0 -#define NAT_ENTRY1_NR_E 1 - -#define PRV_IPADDR0 -#define NAT_ENTRY1_PRV_IPADDR0_BOFFSET 24 -#define NAT_ENTRY1_PRV_IPADDR0_BLEN 8 -#define NAT_ENTRY1_PRV_IPADDR0_FLAG HSL_RW - -#define PORT_RANGE -#define NAT_ENTRY1_PORT_RANGE_BOFFSET 16 -#define NAT_ENTRY1_PORT_RANGE_BLEN 8 -#define NAT_ENTRY1_PORT_RANGE_FLAG HSL_RW - -#define PORT_NUM -#define NAT_ENTRY1_PORT_NUM_BOFFSET 0 -#define NAT_ENTRY1_PORT_NUM_BLEN 16 -#define NAT_ENTRY1_PORT_NUM_FLAG HSL_RW - - -#define NAT_ENTRY2 -#define NAT_ENTRY2_OFFSET 0x0e88 -#define NAT_ENTRY2_E_LENGTH 4 -#define NAT_ENTRY2_E_OFFSET 0x0 -#define NAT_ENTRY2_NR_E 1 - -#define HASH_KEY -#define NAT_ENTRY2_HASH_KEY_BOFFSET 30 -#define NAT_ENTRY2_HASH_KEY_BLEN 2 -#define NAT_ENTRY2_HASH_KEY_FLAG HSL_RW - -#define ACTION -#define NAT_ENTRY2_ACTION_BOFFSET 28 -#define NAT_ENTRY2_ACTION_BLEN 2 -#define NAT_ENTRY2_ACTION_FLAG HSL_RW - -#define CNT_EN -#define NAT_ENTRY2_CNT_EN_BOFFSET 27 -#define NAT_ENTRY2_CNT_EN_BLEN 1 -#define NAT_ENTRY2_CNT_EN_FLAG HSL_RW - -#define CNT_IDX -#define NAT_ENTRY2_CNT_IDX_BOFFSET 24 -#define NAT_ENTRY2_CNT_IDX_BLEN 3 -#define NAT_ENTRY2_CNT_IDX_FLAG HSL_RW - -#define PRV_IPADDR1 -#define NAT_ENTRY2_PRV_IPADDR1_BOFFSET 0 -#define NAT_ENTRY2_PRV_IPADDR1_BLEN 24 -#define NAT_ENTRY2_PRV_IPADDR1_FLAG HSL_RW - - -#define NAT_ENTRY3 -#define NAT_ENTRY3_OFFSET 0x0e8c -#define NAT_ENTRY3_E_LENGTH 4 -#define NAT_ENTRY3_E_OFFSET 0x0 -#define NAT_ENTRY3_NR_E 1 - -#define ENTRY_VALID -#define NAT_ENTRY3_ENTRY_VALID_BOFFSET 3 -#define NAT_ENTRY3_ENTRY_VALID_BLEN 1 -#define NAT_ENTRY3_ENTRY_VALID_FLAG HSL_RW - -#define PORT_EN -#define NAT_ENTRY3_PORT_EN_BOFFSET 2 -#define NAT_ENTRY3_PORT_EN_BLEN 1 -#define NAT_ENTRY3_PORT_EN_FLAG HSL_RW - -#define PRO_TYP -#define NAT_ENTRY3_PRO_TYP_BOFFSET 0 -#define NAT_ENTRY3_PRO_TYP_BLEN 2 -#define NAT_ENTRY3_PRO_TYP_FLAG HSL_RW - - -#define NAPT_ENTRY0 -#define NAPT_ENTRY0_OFFSET 0x0e80 -#define NAPT_ENTRY0_E_LENGTH 4 -#define NAPT_ENTRY0_E_OFFSET 0x0 -#define NAPT_ENTRY0_NR_E 1 - -#define DST_IPADDR -#define NAPT_ENTRY0_DST_IPADDR_BOFFSET 0 -#define NAPT_ENTRY0_DST_IPADDR_BLEN 32 -#define NAPT_ENTRY0_DST_IPADDR_FLAG HSL_RW - - -#define NAPT_ENTRY1 -#define NAPT_ENTRY1_OFFSET 0x0e84 -#define NAPT_ENTRY1_E_LENGTH 4 -#define NAPT_ENTRY1_E_OFFSET 0x0 -#define NAPT_ENTRY1_NR_E 1 - -#define SRC_PORT -#define NAPT_ENTRY1_SRC_PORT_BOFFSET 16 -#define NAPT_ENTRY1_SRC_PORT_BLEN 16 -#define NAPT_ENTRY1_SRC_PORT_FLAG HSL_RW - -#define DST_PORT -#define NAPT_ENTRY1_DST_PORT_BOFFSET 0 -#define NAPT_ENTRY1_DST_PORT_BLEN 16 -#define NAPT_ENTRY1_DST_PORT_FLAG HSL_RW - - -#define NAPT_ENTRY2 -#define NAPT_ENTRY2_OFFSET 0x0e88 -#define NAPT_ENTRY2_E_LENGTH 4 -#define NAPT_ENTRY2_E_OFFSET 0x0 -#define NAPT_ENTRY2_NR_E 1 - -#define SRC_IPADDR0 -#define NAPT_ENTRY2_SRC_IPADDR0_BOFFSET 20 -#define NAPT_ENTRY2_SRC_IPADDR0_BLEN 12 -#define NAPT_ENTRY2_SRC_IPADDR0_FLAG HSL_RW - -#define TRANS_IPADDR -#define NAPT_ENTRY2_TRANS_IPADDR_BOFFSET 16 -#define NAPT_ENTRY2_TRANS_IPADDR_BLEN 4 -#define NAPT_ENTRY2_TRANS_IPADDR_FLAG HSL_RW - -#define TRANS_PORT -#define NAPT_ENTRY2_TRANS_PORT_BOFFSET 0 -#define NAPT_ENTRY2_TRANS_PORT_BLEN 16 -#define NAPT_ENTRY2_TRANS_PORT_FLAG HSL_RW - - -#define NAPT_ENTRY3 -#define NAPT_ENTRY3_OFFSET 0x0e8c -#define NAPT_ENTRY3_E_LENGTH 4 -#define NAPT_ENTRY3_E_OFFSET 0x0 -#define NAPT_ENTRY3_NR_E 1 - -#define CNT_EN -#define NAPT_ENTRY3_CNT_EN_BOFFSET 27 -#define NAPT_ENTRY3_CNT_EN_BLEN 1 -#define NAPT_ENTRY3_CNT_EN_FLAG HSL_RW - -#define CNT_IDX -#define NAPT_ENTRY3_CNT_IDX_BOFFSET 24 -#define NAPT_ENTRY3_CNT_IDX_BLEN 3 -#define NAPT_ENTRY3_CNT_IDX_FLAG HSL_RW - -#define PROT_TYP -#define NAPT_ENTRY3_PROT_TYP_BOFFSET 22 -#define NAPT_ENTRY3_PROT_TYP_BLEN 2 -#define NAPT_ENTRY3_PROT_TYP_FLAG HSL_RW - -#define ACTION -#define NAPT_ENTRY3_ACTION_BOFFSET 20 -#define NAPT_ENTRY3_ACTION_BLEN 2 -#define NAPT_ENTRY3_ACTION_FLAG HSL_RW - -#define SRC_IPADDR1 -#define NAPT_ENTRY3_SRC_IPADDR1_BOFFSET 0 -#define NAPT_ENTRY3_SRC_IPADDR1_BLEN 20 -#define NAPT_ENTRY3_SRC_IPADDR1_FLAG HSL_RW - - -#define NAPT_ENTRY4 -#define NAPT_ENTRY4_OFFSET 0x0e90 -#define NAPT_ENTRY4_E_LENGTH 4 -#define NAPT_ENTRY4_E_OFFSET 0x0 -#define NAPT_ENTRY4_NR_E 1 - -#define AGE_FLAG -#define NAPT_ENTRY4_AGE_FLAG_BOFFSET 0 -#define NAPT_ENTRY4_AGE_FLAG_BLEN 4 -#define NAPT_ENTRY4_AGE_FLAG_FLAG HSL_RW - - -#define ROUTER_CTRL -#define ROUTER_CTRL_OFFSET 0x0e00 -#define ROUTER_CTRL_E_LENGTH 4 -#define ROUTER_CTRL_E_OFFSET 0x0 -#define ROUTER_CTRL_NR_E 1 - -#define ARP_LEARN_MODE -#define ROUTER_CTRL_ARP_LEARN_MODE_BOFFSET 19 -#define ROUTER_CTRL_ARP_LEARN_MODE_BLEN 1 -#define ROUTER_CTRL_ARP_LEARN_MODE_FLAG HSL_RW - -#define GLB_LOCKTIME -#define ROUTER_CTRL_GLB_LOCKTIME_BOFFSET 16 -#define ROUTER_CTRL_GLB_LOCKTIME_BLEN 2 -#define ROUTER_CTRL_GLB_LOCKTIME_FLAG HSL_RW - -#define ARP_AGE_TIME -#define ROUTER_CTRL_ARP_AGE_TIME_BOFFSET 8 -#define ROUTER_CTRL_ARP_AGE_TIME_BLEN 8 -#define ROUTER_CTRL_ARP_AGE_TIME_FLAG HSL_RW - -#define WCMP_HAHS_DP -#define ROUTER_CTRL_WCMP_HAHS_DP_BOFFSET 7 -#define ROUTER_CTRL_WCMP_HAHS_DP_BLEN 1 -#define ROUTER_CTRL_WCMP_HAHS_DP_FLAG HSL_RW - -#define WCMP_HAHS_DIP -#define ROUTER_CTRL_WCMP_HAHS_DIP_BOFFSET 6 -#define ROUTER_CTRL_WCMP_HAHS_DIP_BLEN 1 -#define ROUTER_CTRL_WCMP_HAHS_DIP_FLAG HSL_RW - -#define WCMP_HAHS_SP -#define ROUTER_CTRL_WCMP_HAHS_SP_BOFFSET 5 -#define ROUTER_CTRL_WCMP_HAHS_SP_BLEN 1 -#define ROUTER_CTRL_WCMP_HAHS_SP_FLAG HSL_RW - -#define WCMP_HAHS_SIP -#define ROUTER_CTRL_WCMP_HAHS_SIP_BOFFSET 4 -#define ROUTER_CTRL_WCMP_HAHS_SIP_BLEN 1 -#define ROUTER_CTRL_WCMP_HAHS_SIP_FLAG HSL_RW - -#define ARP_AGE_MODE -#define ROUTER_CTRL_ARP_AGE_MODE_BOFFSET 1 -#define ROUTER_CTRL_ARP_AGE_MODE_BLEN 1 -#define ROUTER_CTRL_ARP_AGE_MODE_FLAG HSL_RW - -#define ROUTER_EN -#define ROUTER_CTRL_ROUTER_EN_BOFFSET 0 -#define ROUTER_CTRL_ROUTER_EN_BLEN 1 -#define ROUTER_CTRL_ROUTER_EN_FLAG HSL_RW - - - - -#define ROUTER_PTCTRL0 -#define ROUTER_PTCTRL0_OFFSET 0x0e04 -#define ROUTER_PTCTRL0_E_LENGTH 4 -#define ROUTER_PTCTRL0_E_OFFSET 0x0 -#define ROUTER_PTCTRL0_NR_E 1 - - - - -#define ROUTER_PTCTRL1 -#define ROUTER_PTCTRL1_OFFSET 0x0e08 -#define ROUTER_PTCTRL1_E_LENGTH 4 -#define ROUTER_PTCTRL1_E_OFFSET 0x0 -#define ROUTER_PTCTRL1_NR_E 1 - - - -#define ROUTER_PTCTRL2 -#define ROUTER_PTCTRL2_OFFSET 0x0e0c -#define ROUTER_PTCTRL2_E_LENGTH 4 -#define ROUTER_PTCTRL2_E_OFFSET 0x0 -#define ROUTER_PTCTRL2_NR_E 1 - -#define ARP_PT_UP -#define ROUTER_PTCTRL2_ARP_PT_UP_BOFFSET 16 -#define ROUTER_PTCTRL2_ARP_PT_UP_BLEN 7 -#define ROUTER_PTCTRL2_ARP_PT_UP_FLAG HSL_RW - -#define ARP_LEARN_ACK -#define ROUTER_PTCTRL2_ARP_LEARN_ACK_BOFFSET 8 -#define ROUTER_PTCTRL2_ARP_LEARN_ACK_BLEN 7 -#define ROUTER_PTCTRL2_ARP_LEARN_ACK_FLAG HSL_RW - -#define ARP_LEARN_REQ -#define ROUTER_PTCTRL2_ARP_LEARN_REQ_BOFFSET 0 -#define ROUTER_PTCTRL2_ARP_LEARN_REQ_BLEN 7 -#define ROUTER_PTCTRL2_ARP_LEARN_REQ_FLAG HSL_RW - - - - -#define NAT_CTRL -#define NAT_CTRL_OFFSET 0x0e38 -#define NAT_CTRL_E_LENGTH 4 -#define NAT_CTRL_E_OFFSET 0x0 -#define NAT_CTRL_NR_E 1 - -#define NAT_HASH_MODE -#define NAT_CTRL_NAT_HASH_MODE_BOFFSET 5 -#define NAT_CTRL_NAT_HASH_MODE_BLEN 2 -#define NAT_CTRL_NAT_HASH_MODE_FLAG HSL_RW - -#define NAPT_OVERRIDE -#define NAT_CTRL_NAPT_OVERRIDE_BOFFSET 4 -#define NAT_CTRL_NAPT_OVERRIDE_BLEN 1 -#define NAT_CTRL_NAPT_OVERRIDE_FLAG HSL_RW - -#define NAPT_MODE -#define NAT_CTRL_NAPT_MODE_BOFFSET 2 -#define NAT_CTRL_NAPT_MODE_BLEN 2 -#define NAT_CTRL_NAPT_MODE_FLAG HSL_RW - -#define NAT_EN -#define NAT_CTRL_NAT_EN_BOFFSET 1 -#define NAT_CTRL_NAT_EN_BLEN 1 -#define NAT_CTRL_NAT_EN_FLAG HSL_RW - -#define NAPT_EN -#define NAT_CTRL_NAPT_EN_BOFFSET 0 -#define NAT_CTRL_NAPT_EN_BLEN 1 -#define NAT_CTRL_NAPT_EN_FLAG HSL_RW - - - - -#define PRV_BASEADDR -#define PRV_BASEADDR_OFFSET 0x0e5c -#define PRV_BASEADDR_E_LENGTH 4 -#define PRV_BASEADDR_E_OFFSET 0x0 -#define PRV_BASEADDR_NR_E 1 - -#define IP4_ADDR -#define PRV_BASEADDR_IP4_ADDR_BOFFSET 0 -#define PRV_BASEADDR_IP4_ADDR_BLEN 20 -#define PRV_BASEADDR_IP4_ADDR_FLAG HSL_RW - - - - -#define PRVIP_ADDR -#define PRVIP_ADDR_OFFSET 0x0470 -#define PRVIP_ADDR_E_LENGTH 4 -#define PRVIP_ADDR_E_OFFSET 0x0 -#define PRVIP_ADDR_NR_E 1 - -#define IP4_BASEADDR -#define PRVIP_ADDR_IP4_BASEADDR_BOFFSET 0 -#define PRVIP_ADDR_IP4_BASEADDR_BLEN 32 -#define PRVIP_ADDR_IP4_BASEADDR_FLAG HSL_RW - - -#define PRVIP_MASK -#define PRVIP_MASK_OFFSET 0x0474 -#define PRVIP_MASK_E_LENGTH 4 -#define PRVIP_MASK_E_OFFSET 0x0 -#define PRVIP_MASK_NR_E 1 - -#define IP4_BASEMASK -#define PRVIP_MASK_IP4_BASEMASK_BOFFSET 0 -#define PRVIP_MASK_IP4_BASEMASK_BLEN 32 -#define PRVIP_MASK_IP4_BASEMASK_FLAG HSL_RW - - - - -#define PUB_ADDR0 -#define PUB_ADDR0_OFFSET 0x5aa00 -#define PUB_ADDR0_E_LENGTH 4 -#define PUB_ADDR0_E_OFFSET 0x0 -#define PUB_ADDR0_NR_E 1 - -#define IP4_ADDR -#define PUB_ADDR0_IP4_ADDR_BOFFSET 0 -#define PUB_ADDR0_IP4_ADDR_BLEN 32 -#define PUB_ADDR0_IP4_ADDR_FLAG HSL_RW - - -#define PUB_ADDR1 -#define PUB_ADDR1_OFFSET 0x5aa04 -#define PUB_ADDR1_E_LENGTH 4 -#define PUB_ADDR1_E_OFFSET 0x0 -#define PUB_ADDR1_NR_E 1 - -#define ADDR_VALID -#define PUB_ADDR1_ADDR_VALID_BOFFSET 0 -#define PUB_ADDR1_ADDR_VALID_BLEN 1 -#define PUB_ADDR1_ADDR_VALID_FLAG HSL_RW - - - - -#define INTF_ADDR_ENTRY0 -#define INTF_ADDR_ENTRY0_OFFSET 0x5aa00 -#define INTF_ADDR_ENTRY0_E_LENGTH 4 -#define INTF_ADDR_ENTRY0_E_OFFSET 0x0 -#define INTF_ADDR_ENTRY0_NR_E 8 - -#define MAC_ADDR2 -#define INTF_ADDR_ENTRY0_MAC_ADDR2_BOFFSET 24 -#define INTF_ADDR_ENTRY0_MAC_ADDR2_BLEN 8 -#define INTF_ADDR_ENTRY0_MAC_ADDR2_FLAG HSL_RW - -#define MAC_ADDR3 -#define INTF_ADDR_ENTRY0_MAC_ADDR3_BOFFSET 16 -#define INTF_ADDR_ENTRY0_MAC_ADDR3_BLEN 8 -#define INTF_ADDR_ENTRY0_MAC_ADDR3_FLAG HSL_RW - -#define MAC_ADDR4 -#define INTF_ADDR_ENTRY0_MAC_ADDR4_BOFFSET 8 -#define INTF_ADDR_ENTRY0_MAC_ADDR4_BLEN 8 -#define INTF_ADDR_ENTRY0_MAC_ADDR4_FLAG HSL_RW - -#define MAC_ADDR5 -#define INTF_ADDR_ENTRY0_MAC_ADDR5_BOFFSET 0 -#define INTF_ADDR_ENTRY0_MAC_ADDR5_BLEN 8 -#define INTF_ADDR_ENTRY0_MAC_ADDR5_FLAG HSL_RW - - -#define INTF_ADDR_ENTRY1 -#define INTF_ADDR_ENTRY1_OFFSET 0x5aa04 -#define INTF_ADDR_ENTRY1_E_LENGTH 4 -#define INTF_ADDR_ENTRY1_E_OFFSET 0x0 -#define INTF_ADDR_ENTRY1_NR_E 8 - -#define VID_HIGH0 -#define INTF_ADDR_ENTRY1_VID_HIGH0_BOFFSET 28 -#define INTF_ADDR_ENTRY1_VID_HIGH0_BLEN 4 -#define INTF_ADDR_ENTRY1_VID_HIGH0_FLAG HSL_RW - -#define VID_LOW -#define INTF_ADDR_ENTRY1_VID_LOW_BOFFSET 16 -#define INTF_ADDR_ENTRY1_VID_LOW_BLEN 12 -#define INTF_ADDR_ENTRY1_VID_LOW_FLAG HSL_RW - -#define MAC_ADDR0 -#define INTF_ADDR_ENTRY1_MAC_ADDR0_BOFFSET 8 -#define INTF_ADDR_ENTRY1_MAC_ADDR0_BLEN 8 -#define INTF_ADDR_ENTRY1_MAC_ADDR0_FLAG HSL_RW - -#define MAC_ADDR1 -#define INTF_ADDR_ENTRY1_MAC_ADDR1_BOFFSET 0 -#define INTF_ADDR_ENTRY1_MAC_ADDR1_BLEN 8 -#define INTF_ADDR_ENTRY1_MAC_ADDR1_FLAG HSL_RW - - -#define INTF_ADDR_ENTRY2 -#define INTF_ADDR_ENTRY2_OFFSET 0x5aa08 -#define INTF_ADDR_ENTRY2_E_LENGTH 4 -#define INTF_ADDR_ENTRY2_E_OFFSET 0x0 -#define INTF_ADDR_ENTRY2_NR_E 8 - -#define IP6_ROUTE -#define INTF_ADDR_ENTRY2_IP6_ROUTE_BOFFSET 9 -#define INTF_ADDR_ENTRY2_IP6_ROUTE_BLEN 1 -#define INTF_ADDR_ENTRY2_IP6_ROUTE_FLAG HSL_RW - -#define IP4_ROUTE -#define INTF_ADDR_ENTRY2_IP4_ROUTE_BOFFSET 8 -#define INTF_ADDR_ENTRY2_IP4_ROUTE_BLEN 1 -#define INTF_ADDR_ENTRY2_IP4_ROUTE_FLAG HSL_RW - -#define VID_HIGH1 -#define INTF_ADDR_ENTRY2_VID_HIGH1_BOFFSET 0 -#define INTF_ADDR_ENTRY2_VID_HIGH1_BLEN 8 -#define INTF_ADDR_ENTRY2_VID_HIGH1_FLAG HSL_RW - - - - - /* Port Shaper Register0 */ -#define EG_SHAPER0 -#define EG_SHAPER0_OFFSET 0x0890 -#define EG_SHAPER0_E_LENGTH 4 -#define EG_SHAPER0_E_OFFSET 0x0020 -#define EG_SHAPER0_NR_E 7 - -#define EG_Q1_CIR -#define EG_SHAPER0_EG_Q1_CIR_BOFFSET 16 -#define EG_SHAPER0_EG_Q1_CIR_BLEN 15 -#define EG_SHAPER0_EG_Q1_CIR_FLAG HSL_RW - -#define EG_Q0_CIR -#define EG_SHAPER0_EG_Q0_CIR_BOFFSET 0 -#define EG_SHAPER0_EG_Q0_CIR_BLEN 15 -#define EG_SHAPER0_EG_Q0_CIR_FLAG HSL_RW - - - /* Port Shaper Register1 */ -#define EG_SHAPER1 -#define EG_SHAPER1_OFFSET 0x0894 -#define EG_SHAPER1_E_LENGTH 4 -#define EG_SHAPER1_E_OFFSET 0x0020 -#define EG_SHAPER1_NR_E 7 - -#define EG_Q3_CIR -#define EG_SHAPER1_EG_Q3_CIR_BOFFSET 16 -#define EG_SHAPER1_EG_Q3_CIR_BLEN 15 -#define EG_SHAPER1_EG_Q3_CIR_FLAG HSL_RW - -#define EG_Q2_CIR -#define EG_SHAPER1_EG_Q2_CIR_BOFFSET 0 -#define EG_SHAPER1_EG_Q2_CIR_BLEN 15 -#define EG_SHAPER1_EG_Q2_CIR_FLAG HSL_RW - - - /* Port Shaper Register2 */ -#define EG_SHAPER2 -#define EG_SHAPER2_OFFSET 0x0898 -#define EG_SHAPER2_E_LENGTH 4 -#define EG_SHAPER2_E_OFFSET 0x0020 -#define EG_SHAPER2_NR_E 7 - -#define EG_Q5_CIR -#define EG_SHAPER2_EG_Q5_CIR_BOFFSET 16 -#define EG_SHAPER2_EG_Q5_CIR_BLEN 15 -#define EG_SHAPER2_EG_Q5_CIR_FLAG HSL_RW - -#define EG_Q4_CIR -#define EG_SHAPER2_EG_Q4_CIR_BOFFSET 0 -#define EG_SHAPER2_EG_Q4_CIR_BLEN 15 -#define EG_SHAPER2_EG_Q4_CIR_FLAG HSL_RW - - - /* Port Shaper Register3 */ -#define EG_SHAPER3 -#define EG_SHAPER3_OFFSET 0x089c -#define EG_SHAPER3_E_LENGTH 4 -#define EG_SHAPER3_E_OFFSET 0x0020 -#define EG_SHAPER3_NR_E 7 - -#define EG_Q1_EIR -#define EG_SHAPER3_EG_Q1_EIR_BOFFSET 16 -#define EG_SHAPER3_EG_Q1_EIR_BLEN 15 -#define EG_SHAPER3_EG_Q1_EIR_FLAG HSL_RW - -#define EG_Q0_EIR -#define EG_SHAPER3_EG_Q0_EIR_BOFFSET 0 -#define EG_SHAPER3_EG_Q0_EIR_BLEN 15 -#define EG_SHAPER3_EG_Q0_EIR_FLAG HSL_RW - - - /* Port Shaper Register4 */ -#define EG_SHAPER4 -#define EG_SHAPER4_OFFSET 0x08a0 -#define EG_SHAPER4_E_LENGTH 4 -#define EG_SHAPER4_E_OFFSET 0x0020 -#define EG_SHAPER4_NR_E 7 - -#define EG_Q3_EIR -#define EG_SHAPER4_EG_Q3_EIR_BOFFSET 16 -#define EG_SHAPER4_EG_Q3_EIR_BLEN 15 -#define EG_SHAPER4_EG_Q3_EIR_FLAG HSL_RW - -#define EG_Q2_EIR -#define EG_SHAPER4_EG_Q2_EIR_BOFFSET 0 -#define EG_SHAPER4_EG_Q2_EIR_BLEN 15 -#define EG_SHAPER4_EG_Q2_EIR_FLAG HSL_RW - - - /* Port Shaper Register5 */ -#define EG_SHAPER5 -#define EG_SHAPER5_OFFSET 0x08a4 -#define EG_SHAPER5_E_LENGTH 4 -#define EG_SHAPER5_E_OFFSET 0x0020 -#define EG_SHAPER5_NR_E 7 - -#define EG_Q5_EIR -#define EG_SHAPER5_EG_Q5_EIR_BOFFSET 16 -#define EG_SHAPER5_EG_Q5_EIR_BLEN 15 -#define EG_SHAPER5_EG_Q5_EIR_FLAG HSL_RW - -#define EG_Q4_EIR -#define EG_SHAPER5_EG_Q4_EIR_BOFFSET 0 -#define EG_SHAPER5_EG_Q4_EIR_BLEN 15 -#define EG_SHAPER5_EG_Q4_EIR_FLAG HSL_RW - - - /* Port Shaper Register6 */ -#define EG_SHAPER6 -#define EG_SHAPER6_OFFSET 0x08a8 -#define EG_SHAPER6_E_LENGTH 4 -#define EG_SHAPER6_E_OFFSET 0x0020 -#define EG_SHAPER6_NR_E 7 - -#define EG_Q3_CBS -#define EG_SHAPER6_EG_Q3_CBS_BOFFSET 28 -#define EG_SHAPER6_EG_Q3_CBS_BLEN 3 -#define EG_SHAPER6_EG_Q3_CBS_FLAG HSL_RW - -#define EG_Q3_EBS -#define EG_SHAPER6_EG_Q3_EBS_BOFFSET 24 -#define EG_SHAPER6_EG_Q3_EBS_BLEN 3 -#define EG_SHAPER6_EG_Q3_EBS_FLAG HSL_RW - -#define EG_Q2_CBS -#define EG_SHAPER6_EG_Q2_CBS_BOFFSET 20 -#define EG_SHAPER6_EG_Q2_CBS_BLEN 3 -#define EG_SHAPER6_EG_Q2_CBS_FLAG HSL_RW - -#define EG_Q2_EBS -#define EG_SHAPER6_EG_Q2_EBS_BOFFSET 16 -#define EG_SHAPER6_EG_Q2_EBS_BLEN 3 -#define EG_SHAPER6_EG_Q2_EBS_FLAG HSL_RW - -#define EG_Q1_CBS -#define EG_SHAPER6_EG_Q1_CBS_BOFFSET 12 -#define EG_SHAPER6_EG_Q1_CBS_BLEN 3 -#define EG_SHAPER6_EG_Q1_CBS_FLAG HSL_RW - -#define EG_Q1_EBS -#define EG_SHAPER6_EG_Q1_EBS_BOFFSET 8 -#define EG_SHAPER6_EG_Q1_EBS_BLEN 3 -#define EG_SHAPER6_EG_Q1_EBS_FLAG HSL_RW - -#define EG_Q0_CBS -#define EG_SHAPER6_EG_Q0_CBS_BOFFSET 4 -#define EG_SHAPER6_EG_Q0_CBS_BLEN 3 -#define EG_SHAPER6_EG_Q0_CBS_FLAG HSL_RW - -#define EG_Q0_EBS -#define EG_SHAPER6_EG_Q0_EBS_BOFFSET 0 -#define EG_SHAPER6_EG_Q0_EBS_BLEN 3 -#define EG_SHAPER6_EG_Q0_EBS_FLAG HSL_RW - - - /* Port Shaper Register7 */ -#define EG_SHAPER7 -#define EG_SHAPER7_OFFSET 0x08ac -#define EG_SHAPER7_E_LENGTH 4 -#define EG_SHAPER7_E_OFFSET 0x0020 -#define EG_SHAPER7_NR_E 7 - -#define EG_Q5_CBS -#define EG_SHAPER7_EG_Q5_CBS_BOFFSET 28 -#define EG_SHAPER7_EG_Q5_CBS_BLEN 3 -#define EG_SHAPER7_EG_Q5_CBS_FLAG HSL_RW - -#define EG_Q5_EBS -#define EG_SHAPER7_EG_Q5_EBS_BOFFSET 24 -#define EG_SHAPER7_EG_Q5_EBS_BLEN 3 -#define EG_SHAPER7_EG_Q5_EBS_FLAG HSL_RW - -#define EG_Q4_CBS -#define EG_SHAPER7_EG_Q4_CBS_BOFFSET 20 -#define EG_SHAPER7_EG_Q4_CBS_BLEN 3 -#define EG_SHAPER7_EG_Q4_CBS_FLAG HSL_RW - -#define EG_Q4_EBS -#define EG_SHAPER7_EG_Q4_EBS_BOFFSET 16 -#define EG_SHAPER7_EG_Q4_EBS_BLEN 3 -#define EG_SHAPER7_EG_Q4_EBS_FLAG HSL_RW - -#define EG_Q5_UNIT -#define EG_SHAPER7_EG_Q5_UNIT_BOFFSET 13 -#define EG_SHAPER7_EG_Q5_UNIT_BLEN 1 -#define EG_SHAPER7_EG_Q5_UNIT_FLAG HSL_RW - -#define EG_Q4_UNIT -#define EG_SHAPER7_EG_Q4_UNIT_BOFFSET 12 -#define EG_SHAPER7_EG_Q4_UNIT_BLEN 1 -#define EG_SHAPER7_EG_Q4_UNIT_FLAG HSL_RW - -#define EG_Q3_UNIT -#define EG_SHAPER7_EG_Q3_UNIT_BOFFSET 11 -#define EG_SHAPER7_EG_Q3_UNIT_BLEN 1 -#define EG_SHAPER7_EG_Q3_UNIT_FLAG HSL_RW - -#define EG_Q2_UNIT -#define EG_SHAPER7_EG_Q2_UNIT_BOFFSET 10 -#define EG_SHAPER7_EG_Q2_UNIT_BLEN 1 -#define EG_SHAPER7_EG_Q2_UNIT_FLAG HSL_RW - -#define EG_Q1_UNIT -#define EG_SHAPER7_EG_Q1_UNIT_BOFFSET 9 -#define EG_SHAPER7_EG_Q1_UNIT_BLEN 1 -#define EG_SHAPER7_EG_Q1_UNIT_FLAG HSL_RW - -#define EG_Q0_UNIT -#define EG_SHAPER7_EG_Q0_UNIT_BOFFSET 8 -#define EG_SHAPER7_EG_Q0_UNIT_BLEN 1 -#define EG_SHAPER7_EG_Q0_UNIT_FLAG HSL_RW - -#define EG_PT -#define EG_SHAPER7_EG_PT_BOFFSET 3 -#define EG_SHAPER7_EG_PT_BLEN 1 -#define EG_SHAPER7_EG_PT_FLAG HSL_RW - -#define EG_TS -#define EG_SHAPER7_EG_TS_BOFFSET 0 -#define EG_SHAPER7_EG_TS_BLEN 3 -#define EG_SHAPER7_EG_TS_FLAG HSL_RW - - - - /* ACL Policer Register0 */ -#define ACL_POLICER0 -#define ACL_POLICER0_OFFSET 0x0a00 -#define ACL_POLICER0_E_LENGTH 4 -#define ACL_POLICER0_E_OFFSET 0x0008 -#define ACL_POLICER0_NR_E 32 - -#define ACL_CBS -#define ACL_POLICER0_ACL_CBS_BOFFSET 15 -#define ACL_POLICER0_ACL_CBS_BLEN 3 -#define ACL_POLICER0_ACL_CBS_FLAG HSL_RW - -#define ACL_CIR -#define ACL_POLICER0_ACL_CIR_BOFFSET 0 -#define ACL_POLICER0_ACL_CIR_BLEN 15 -#define ACL_POLICER0_ACL_CIR_FLAG HSL_RW - - - /* ACL Policer Register1 */ -#define ACL_POLICER1 -#define ACL_POLICER1_OFFSET 0x0a04 -#define ACL_POLICER1_E_LENGTH 4 -#define ACL_POLICER1_E_OFFSET 0x0008 -#define ACL_POLICER1_NR_E 32 - -#define ACL_BORROW -#define ACL_POLICER1_ACL_BORROW_BOFFSET 23 -#define ACL_POLICER1_ACL_BORROW_BLEN 1 -#define ACL_POLICER1_ACL_BORROW_FLAG HSL_RW - -#define ACL_UNIT -#define ACL_POLICER1_ACL_UNIT_BOFFSET 22 -#define ACL_POLICER1_ACL_UNIT_BLEN 1 -#define ACL_POLICER1_ACL_UNIT_FLAG HSL_RW - -#define ACL_CF -#define ACL_POLICER1_ACL_CF_BOFFSET 21 -#define ACL_POLICER1_ACL_CF_BLEN 1 -#define ACL_POLICER1_ACL_CF_FLAG HSL_RW - -#define ACL_CM -#define ACL_POLICER1_ACL_CM_BOFFSET 20 -#define ACL_POLICER1_ACL_CM_BLEN 1 -#define ACL_POLICER1_ACL_CM_FLAG HSL_RW - -#define ACL_TS -#define ACL_POLICER1_ACL_TS_BOFFSET 18 -#define ACL_POLICER1_ACL_TS_BLEN 2 -#define ACL_POLICER1_ACL_TS_FLAG HSL_RW - -#define ACL_EBS -#define ACL_POLICER1_ACL_EBS_BOFFSET 15 -#define ACL_POLICER1_ACL_EBS_BLEN 3 -#define ACL_POLICER1_ACL_EBS_FLAG HSL_RW - -#define ACL_EIR -#define ACL_POLICER1_ACL_EIR_BOFFSET 0 -#define ACL_POLICER1_ACL_EIR_BLEN 15 -#define ACL_POLICER1_ACL_EIR_FLAG HSL_RW - - - /* ACL Counter Register0 */ -#define ACL_COUNTER0 -#define ACL_COUNTER0_OFFSET 0x1c000 -#define ACL_COUNTER0_E_LENGTH 4 -#define ACL_COUNTER0_E_OFFSET 0x0008 -#define ACL_COUNTER0_NR_E 32 - - /* ACL Counter Register1 */ -#define ACL_COUNTER1 -#define ACL_COUNTER1_OFFSET 0x1c004 -#define ACL_COUNTER1_E_LENGTH 4 -#define ACL_COUNTER1_E_OFFSET 0x0008 -#define ACL_COUNTER1_NR_E 32 - - - - - /* INGRESS Policer Register0 */ -#define INGRESS_POLICER0 -#define INGRESS_POLICER0_OFFSET 0x0b00 -#define INGRESS_POLICER0_E_LENGTH 4 -#define INGRESS_POLICER0_E_OFFSET 0x0010 -#define INGRESS_POLICER0_NR_E 7 - -#define ADD_RATE_BYTE -#define INGRESS_POLICER0_ADD_RATE_BYTE_BOFFSET 24 -#define INGRESS_POLICER0_ADD_RATE_BYTE_BLEN 8 -#define INGRESS_POLICER0_ADD_RATE_BYTE_FLAG HSL_RW - -#define C_ING_TS -#define INGRESS_POLICER0_C_ING_TS_BOFFSET 22 -#define INGRESS_POLICER0_C_ING_TS_BLEN 2 -#define INGRESS_POLICER0_C_ING_TS_FLAG HSL_RW - -#define RATE_MODE -#define INGRESS_POLICER0_RATE_MODE_BOFFSET 20 -#define INGRESS_POLICER0_RATE_MODE_BLEN 1 -#define INGRESS_POLICER0_RATE_MODE_FLAG HSL_RW - -#define INGRESS_CBS -#define INGRESS_POLICER0_INGRESS_CBS_BOFFSET 15 -#define INGRESS_POLICER0_INGRESS_CBS_BLEN 3 -#define INGRESS_POLICER0_INGRESS_CBS_FLAG HSL_RW - -#define INGRESS_CIR -#define INGRESS_POLICER0_INGRESS_CIR_BOFFSET 0 -#define INGRESS_POLICER0_INGRESS_CIR_BLEN 15 -#define INGRESS_POLICER0_INGRESS_CIR_FLAG HSL_RW - - - /* INGRESS Policer Register1 */ -#define INGRESS_POLICER1 -#define INGRESS_POLICER1_OFFSET 0x0b04 -#define INGRESS_POLICER1_E_LENGTH 4 -#define INGRESS_POLICER1_E_OFFSET 0x0010 -#define INGRESS_POLICER1_NR_E 7 - -#define INGRESS_BORROW -#define INGRESS_POLICER1_INGRESS_BORROW_BOFFSET 23 -#define INGRESS_POLICER1_INGRESS_BORROW_BLEN 1 -#define INGRESS_POLICER1_INGRESS_BORROW_FLAG HSL_RW - -#define INGRESS_UNIT -#define INGRESS_POLICER1_INGRESS_UNIT_BOFFSET 22 -#define INGRESS_POLICER1_INGRESS_UNIT_BLEN 1 -#define INGRESS_POLICER1_INGRESS_UNIT_FLAG HSL_RW - -#define INGRESS_CF -#define INGRESS_POLICER1_INGRESS_CF_BOFFSET 21 -#define INGRESS_POLICER1_INGRESS_CF_BLEN 1 -#define INGRESS_POLICER1_INGRESS_CF_FLAG HSL_RW - -#define INGRESS_CM -#define INGRESS_POLICER1_INGRESS_CM_BOFFSET 20 -#define INGRESS_POLICER1_INGRESS_CM_BLEN 1 -#define INGRESS_POLICER1_INGRESS_CM_FLAG HSL_RW - -#define E_ING_TS -#define INGRESS_POLICER1_E_ING_TS_BOFFSET 18 -#define INGRESS_POLICER1_E_ING_TS_BLEN 2 -#define INGRESS_POLICER1_E_ING_TS_FLAG HSL_RW - -#define INGRESS_EBS -#define INGRESS_POLICER1_INGRESS_EBS_BOFFSET 15 -#define INGRESS_POLICER1_INGRESS_EBS_BLEN 3 -#define INGRESS_POLICER1_INGRESS_EBS_FLAG HSL_RW - -#define INGRESS_EIR -#define INGRESS_POLICER1_INGRESS_EIR_BOFFSET 0 -#define INGRESS_POLICER1_INGRESS_EIR_BLEN 15 -#define INGRESS_POLICER1_INGRESS_EIR_FLAG HSL_RW - - - /* INGRESS Policer Register2 */ -#define INGRESS_POLICER2 -#define INGRESS_POLICER2_OFFSET 0x0b08 -#define INGRESS_POLICER2_E_LENGTH 4 -#define INGRESS_POLICER2_E_OFFSET 0x0010 -#define INGRESS_POLICER2_NR_E 7 - -#define C_MUL -#define INGRESS_POLICER2_C_MUL_BOFFSET 15 -#define INGRESS_POLICER2_C_MUL_BLEN 1 -#define INGRESS_POLICER2_C_UNK_MUL_FLAG HSL_RW - -#define C_UNI -#define INGRESS_POLICER2_C_UNI_BOFFSET 14 -#define INGRESS_POLICER2_C_UNI_BLEN 1 -#define INGRESS_POLICER2_C_UNI_FLAG HSL_RW - -#define C_UNK_MUL -#define INGRESS_POLICER2_C_UNK_MUL_BOFFSET 13 -#define INGRESS_POLICER2_C_UNK_MUL_BLEN 1 -#define INGRESS_POLICER2_C_UNK_MUL_FLAG HSL_RW - -#define C_UNK_UNI -#define INGRESS_POLICER2_C_UNK_UNI_BOFFSET 12 -#define INGRESS_POLICER2_C_UNK_UNI_BLEN 1 -#define INGRESS_POLICER2_C_UNK_UNI_FLAG HSL_RW - -#define C_BROAD -#define INGRESS_POLICER2_C_BROAD_BOFFSET 11 -#define INGRESS_POLICER2_C_BROAD_BLEN 1 -#define INGRESS_POLICER2_C_BROAD_FLAG HSL_RW - -#define C_MANAGE -#define INGRESS_POLICER2_C_MANAGC_BOFFSET 10 -#define INGRESS_POLICER2_C_MANAGC_BLEN 1 -#define INGRESS_POLICER2_C_MANAGC_FLAG HSL_RW - -#define C_TCP -#define INGRESS_POLICER2_C_TCP_BOFFSET 9 -#define INGRESS_POLICER2_C_TCP_BLEN 1 -#define INGRESS_POLICER2_C_TCP_FLAG HSL_RW - -#define C_MIRR -#define INGRESS_POLICER2_C_MIRR_BOFFSET 8 -#define INGRESS_POLICER2_C_MIRR_BLEN 1 -#define INGRESS_POLICER2_C_MIRR_FLAG HSL_RW - -#define E_MUL -#define INGRESS_POLICER2_E_MUL_BOFFSET 7 -#define INGRESS_POLICER2_E_MUL_BLEN 1 -#define INGRESS_POLICER2_E_UNK_MUL_FLAG HSL_RW - -#define E_UNI -#define INGRESS_POLICER2_E_UNI_BOFFSET 6 -#define INGRESS_POLICER2_E_UNI_BLEN 1 -#define INGRESS_POLICER2_E_UNI_FLAG HSL_RW - -#define E_UNK_MUL -#define INGRESS_POLICER2_E_UNK_MUL_BOFFSET 5 -#define INGRESS_POLICER2_E_UNK_MUL_BLEN 1 -#define INGRESS_POLICER2_E_UNK_MUL_FLAG HSL_RW - -#define E_UNK_UNI -#define INGRESS_POLICER2_E_UNK_UNI_BOFFSET 4 -#define INGRESS_POLICER2_E_UNK_UNI_BLEN 1 -#define INGRESS_POLICER2_E_UNK_UNI_FLAG HSL_RW - -#define E_BROAD -#define INGRESS_POLICER2_E_BROAD_BOFFSET 3 -#define INGRESS_POLICER2_E_BROAD_BLEN 1 -#define INGRESS_POLICER2_E_BROAD_FLAG HSL_RW - -#define E_MANAGE -#define INGRESS_POLICER2_E_MANAGE_BOFFSET 2 -#define INGRESS_POLICER2_E_MANAGE_BLEN 1 -#define INGRESS_POLICER2_E_MANAGE_FLAG HSL_RW - -#define E_TCP -#define INGRESS_POLICER2_E_TCP_BOFFSET 1 -#define INGRESS_POLICER2_E_TCP_BLEN 1 -#define INGRESS_POLICER2_E_TCP_FLAG HSL_RW - -#define E_MIRR -#define INGRESS_POLICER2_E_MIRR_BOFFSET 0 -#define INGRESS_POLICER2_E_MIRR_BLEN 1 -#define INGRESS_POLICER2_E_MIRR_FLAG HSL_RW - - - - - /* Port Rate Limit2 Register */ -#define WRR_CTRL -#define WRR_CTRL_OFFSET 0x0830 -#define WRR_CTRL_E_LENGTH 4 -#define WRR_CTRL_E_OFFSET 0x0004 -#define WRR_CTRL_NR_E 7 - -#define SCH_MODE -#define WRR_CTRL_SCH_MODE_BOFFSET 30 -#define WRR_CTRL_SCH_MODE_BLEN 2 -#define WRR_CTRL_SCH_MODE_FLAG HSL_RW - -#define Q5_W -#define WRR_CTRL_Q5_W_BOFFSET 25 -#define WRR_CTRL_Q5_W_BLEN 5 -#define WRR_CTRL_Q5_W_FLAG HSL_RW - -#define Q4_W -#define WRR_CTRL_Q4_W_BOFFSET 20 -#define WRR_CTRL_Q4_W_BLEN 5 -#define WRR_CTRL_Q4_W_FLAG HSL_RW - -#define Q3_W -#define WRR_CTRL_Q3_W_BOFFSET 15 -#define WRR_CTRL_Q3_W_BLEN 5 -#define WRR_CTRL_Q3_W_FLAG HSL_RW - -#define Q2_W -#define WRR_CTRL_Q2_W_BOFFSET 10 -#define WRR_CTRL_Q2_W_BLEN 5 -#define WRR_CTRL_Q2_W_FLAG HSL_RW - -#define Q1_W -#define WRR_CTRL_Q1_W_BOFFSET 5 -#define WRR_CTRL_Q1_W_BLEN 5 -#define WRR_CTRL_Q1_W_FLAG HSL_RW - -#define Q0_W -#define WRR_CTRL_Q0_W_BOFFSET 0 -#define WRR_CTRL_Q0_W_BLEN 5 -#define WRR_CTRL_Q0_W_FLAG HSL_RW - - - - - -#ifdef __cplusplus -} -#endif /* __cplusplus */ -#endif /* _ISISC_REG_H_ */ - diff --git a/feeds/ipq807x/qca-ssdk/src/include/hsl/isisc/isisc_reg_access.h b/feeds/ipq807x/qca-ssdk/src/include/hsl/isisc/isisc_reg_access.h deleted file mode 100755 index 5f6ea310b..000000000 --- a/feeds/ipq807x/qca-ssdk/src/include/hsl/isisc/isisc_reg_access.h +++ /dev/null @@ -1,70 +0,0 @@ -/* - * Copyright (c) 2012,2018, The Linux Foundation. All rights reserved. - * Permission to use, copy, modify, and/or distribute this software for - * any purpose with or without fee is hereby granted, provided that the - * above copyright notice and this permission notice appear in all copies. - * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES - * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR - * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES - * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN - * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT - * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. - */ - - - -#ifndef _ISISC_REG_ACCESS_H_ -#define _ISISC_REG_ACCESS_H_ - -#ifdef __cplusplus -extern "C" { -#endif /* __cplusplus */ - -#include "sw.h" - - sw_error_t - isisc_phy_get(a_uint32_t dev_id, a_uint32_t phy_addr, - a_uint32_t reg, a_uint16_t * value); - - sw_error_t - isisc_phy_set(a_uint32_t dev_id, a_uint32_t phy_addr, - a_uint32_t reg, a_uint16_t value); - - sw_error_t - isisc_reg_get(a_uint32_t dev_id, a_uint32_t reg_addr, a_uint8_t value[], - a_uint32_t value_len); - - sw_error_t - isisc_reg_set(a_uint32_t dev_id, a_uint32_t reg_addr, a_uint8_t value[], - a_uint32_t value_len); - - sw_error_t - isisc_reg_field_get(a_uint32_t dev_id, a_uint32_t reg_addr, - a_uint32_t bit_offset, a_uint32_t field_len, - a_uint8_t value[], a_uint32_t value_len); - - sw_error_t - isisc_reg_field_set(a_uint32_t dev_id, a_uint32_t reg_addr, - a_uint32_t bit_offset, a_uint32_t field_len, - const a_uint8_t value[], a_uint32_t value_len); - - sw_error_t - isisc_regsiter_dump(a_uint32_t dev_id,a_uint32_t register_idx, fal_reg_dump_t * reg_dump); - - sw_error_t - isisc_debug_regsiter_dump(a_uint32_t dev_id, fal_debug_reg_dump_t * reg_dump); - - sw_error_t - isisc_reg_access_init(a_uint32_t dev_id, hsl_access_mode mode); - - sw_error_t - isisc_access_mode_set(a_uint32_t dev_id, hsl_access_mode mode); - - -#ifdef __cplusplus -} -#endif /* __cplusplus */ - -#endif /* _ISISC_REG_ACCESS_H_ */ - diff --git a/feeds/ipq807x/qca-ssdk/src/include/hsl/isisc/isisc_sec.h b/feeds/ipq807x/qca-ssdk/src/include/hsl/isisc/isisc_sec.h deleted file mode 100755 index 93849b49f..000000000 --- a/feeds/ipq807x/qca-ssdk/src/include/hsl/isisc/isisc_sec.h +++ /dev/null @@ -1,53 +0,0 @@ -/* - * Copyright (c) 2012, The Linux Foundation. All rights reserved. - * Permission to use, copy, modify, and/or distribute this software for - * any purpose with or without fee is hereby granted, provided that the - * above copyright notice and this permission notice appear in all copies. - * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES - * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR - * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES - * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN - * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT - * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. - */ - - -#ifndef _ISISC_SEC_H_ -#define _ISISC_SEC_H_ - -#ifdef __cplusplus -extern "C" { -#endif /* __cplusplus */ - -#include "fal/fal_sec.h" - - sw_error_t isisc_sec_init(a_uint32_t dev_id); - -#ifdef IN_SEC -#define ISISC_SEC_INIT(rv, dev_id) \ - { \ - rv = isisc_sec_init(dev_id); \ - SW_RTN_ON_ERROR(rv); \ - } -#else -#define ISISC_SEC_INIT(rv, dev_id) -#endif - -#ifdef HSL_STANDALONG - - HSL_LOCAL sw_error_t - isisc_sec_norm_item_set(a_uint32_t dev_id, fal_norm_item_t item, - void *value); - - HSL_LOCAL sw_error_t - isisc_sec_norm_item_get(a_uint32_t dev_id, fal_norm_item_t item, - void *value); - -#endif - -#ifdef __cplusplus -} -#endif /* __cplusplus */ -#endif /* _ISISC_SEC_H_ */ - diff --git a/feeds/ipq807x/qca-ssdk/src/include/hsl/isisc/isisc_stp.h b/feeds/ipq807x/qca-ssdk/src/include/hsl/isisc/isisc_stp.h deleted file mode 100755 index cb4b9c6f9..000000000 --- a/feeds/ipq807x/qca-ssdk/src/include/hsl/isisc/isisc_stp.h +++ /dev/null @@ -1,55 +0,0 @@ -/* - * Copyright (c) 2012, The Linux Foundation. All rights reserved. - * Permission to use, copy, modify, and/or distribute this software for - * any purpose with or without fee is hereby granted, provided that the - * above copyright notice and this permission notice appear in all copies. - * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES - * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR - * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES - * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN - * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT - * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. - */ - - -#ifndef _ISISC_STP_H_ -#define _ISISC_STP_H_ - -#ifdef __cplusplus -extern "C" { -#endif /* __cplusplus */ - -#include "fal/fal_stp.h" - - sw_error_t isisc_stp_init(a_uint32_t dev_id); - -#ifdef IN_STP -#define ISISC_STP_INIT(rv, dev_id) \ - { \ - rv = isisc_stp_init(dev_id); \ - SW_RTN_ON_ERROR(rv); \ - } -#else -#define ISISC_STP_INIT(rv, dev_id) -#endif - -#ifdef HSL_STANDALONG - - - HSL_LOCAL sw_error_t - isisc_stp_port_state_set(a_uint32_t dev_id, a_uint32_t st_id, - fal_port_t port_id, fal_stp_state_t state); - - - HSL_LOCAL sw_error_t - isisc_stp_port_state_get(a_uint32_t dev_id, a_uint32_t st_id, - fal_port_t port_id, fal_stp_state_t * state); - -#endif - -#ifdef __cplusplus -} -#endif /* __cplusplus */ -#endif /* _ISISC_STP_H_ */ - diff --git a/feeds/ipq807x/qca-ssdk/src/include/hsl/isisc/isisc_trunk.h b/feeds/ipq807x/qca-ssdk/src/include/hsl/isisc/isisc_trunk.h deleted file mode 100755 index 4346e08d2..000000000 --- a/feeds/ipq807x/qca-ssdk/src/include/hsl/isisc/isisc_trunk.h +++ /dev/null @@ -1,69 +0,0 @@ -/* - * Copyright (c) 2012, The Linux Foundation. All rights reserved. - * Permission to use, copy, modify, and/or distribute this software for - * any purpose with or without fee is hereby granted, provided that the - * above copyright notice and this permission notice appear in all copies. - * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES - * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR - * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES - * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN - * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT - * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. - */ - - -#ifndef _ISISC_TRUNK_H_ -#define _ISISC_TRUNK_H_ - -#ifdef __cplusplus -extern "C" { -#endif /* __cplusplus */ - -#include "fal/fal_trunk.h" - - sw_error_t isisc_trunk_init(a_uint32_t dev_id); - -#ifdef IN_TRUNK -#define ISISC_TRUNK_INIT(rv, dev_id) \ - { \ - rv = isisc_trunk_init(dev_id); \ - SW_RTN_ON_ERROR(rv); \ - } -#else -#define ISISC_TRUNK_INIT(rv, dev_id) -#endif - -#ifdef HSL_STANDALONG - - HSL_LOCAL sw_error_t - isisc_trunk_group_set(a_uint32_t dev_id, a_uint32_t trunk_id, - a_bool_t enable, fal_pbmp_t member); - - HSL_LOCAL sw_error_t - isisc_trunk_group_get(a_uint32_t dev_id, a_uint32_t trunk_id, - a_bool_t * enable, fal_pbmp_t * member); - - HSL_LOCAL sw_error_t - isisc_trunk_hash_mode_set(a_uint32_t dev_id, a_uint32_t hash_mode); - - HSL_LOCAL sw_error_t - isisc_trunk_hash_mode_get(a_uint32_t dev_id, a_uint32_t * hash_mode); - - HSL_LOCAL sw_error_t - isisc_trunk_manipulate_sa_set(a_uint32_t dev_id, fal_mac_addr_t * addr); - - HSL_LOCAL sw_error_t - isisc_trunk_manipulate_sa_get(a_uint32_t dev_id, fal_mac_addr_t * addr); - - HSL_LOCAL sw_error_t - isisc_trunk_manipulate_dp(a_uint32_t dev_id, a_uint8_t * header, - a_uint32_t len, fal_pbmp_t dp_member); - -#endif - -#ifdef __cplusplus -} -#endif /* __cplusplus */ -#endif /* _ISISC_TRUNK_H_ */ - diff --git a/feeds/ipq807x/qca-ssdk/src/include/hsl/isisc/isisc_vlan.h b/feeds/ipq807x/qca-ssdk/src/include/hsl/isisc/isisc_vlan.h deleted file mode 100755 index c198a7208..000000000 --- a/feeds/ipq807x/qca-ssdk/src/include/hsl/isisc/isisc_vlan.h +++ /dev/null @@ -1,99 +0,0 @@ -/* - * Copyright (c) 2012, The Linux Foundation. All rights reserved. - * Permission to use, copy, modify, and/or distribute this software for - * any purpose with or without fee is hereby granted, provided that the - * above copyright notice and this permission notice appear in all copies. - * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES - * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR - * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES - * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN - * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT - * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. - */ - - -#ifndef _ISISC_VLAN_H_ -#define _ISISC_VLAN_H_ - -#ifdef __cplusplus -extern "C" { -#endif /* __cplusplus */ - -#include "fal/fal_vlan.h" - - sw_error_t - isisc_vlan_init(a_uint32_t dev_id); - -#ifdef IN_VLAN -#define ISISC_VLAN_INIT(rv, dev_id) \ - { \ - rv = isisc_vlan_init(dev_id); \ - SW_RTN_ON_ERROR(rv); \ - } -#else -#define ISISC_VLAN_INIT(rv, dev_id) -#endif - -#ifdef HSL_STANDALONG - - - HSL_LOCAL sw_error_t - isisc_vlan_entry_append(a_uint32_t dev_id, const fal_vlan_t * vlan_entry); - - - HSL_LOCAL sw_error_t - isisc_vlan_create(a_uint32_t dev_id, a_uint32_t vlan_id); - - - HSL_LOCAL sw_error_t - isisc_vlan_next(a_uint32_t dev_id, a_uint32_t vlan_id, fal_vlan_t * p_vlan); - - - HSL_LOCAL sw_error_t - isisc_vlan_find(a_uint32_t dev_id, a_uint32_t vlan_id, fal_vlan_t * p_vlan); - - - HSL_LOCAL sw_error_t - isisc_vlan_delete(a_uint32_t dev_id, a_uint32_t vlan_id); - - - HSL_LOCAL sw_error_t - isisc_vlan_flush(a_uint32_t dev_id); - - - HSL_LOCAL sw_error_t - isisc_vlan_fid_set(a_uint32_t dev_id, a_uint32_t vlan_id, a_uint32_t fid); - - - HSL_LOCAL sw_error_t - isisc_vlan_fid_get(a_uint32_t dev_id, a_uint32_t vlan_id, a_uint32_t * fid); - - - HSL_LOCAL sw_error_t - isisc_vlan_member_add(a_uint32_t dev_id, a_uint32_t vlan_id, - fal_port_t port_id, fal_pt_1q_egmode_t port_info); - - - HSL_LOCAL sw_error_t - isisc_vlan_member_del(a_uint32_t dev_id, a_uint32_t vlan_id, fal_port_t port_id); - - - HSL_LOCAL sw_error_t - isisc_vlan_learning_state_set(a_uint32_t dev_id, a_uint32_t vlan_id, - a_bool_t enable); - - - HSL_LOCAL sw_error_t - isisc_vlan_learning_state_get(a_uint32_t dev_id, a_uint32_t vlan_id, - a_bool_t * enable); - - -#endif - -#ifdef __cplusplus -} -#endif /* __cplusplus */ - -#endif /* _ISISC_VLAN_H_ */ - diff --git a/feeds/ipq807x/qca-ssdk/src/include/hsl/mp/mp_mib.h b/feeds/ipq807x/qca-ssdk/src/include/hsl/mp/mp_mib.h deleted file mode 100755 index f79a761e5..000000000 --- a/feeds/ipq807x/qca-ssdk/src/include/hsl/mp/mp_mib.h +++ /dev/null @@ -1,392 +0,0 @@ -/* - * Copyright (c) 2020, The Linux Foundation. All rights reserved. - * - * Permission to use, copy, modify, and/or distribute this software for any - * purpose with or without fee is hereby granted, provided that the above - * copyright notice and this permission notice appear in all copies. - * - * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES - * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR - * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES - * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN - * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF - * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. - */ - -#ifndef _MP_MIB_H_ -#define _MP_MIB_H_ - -#define MMC_CONTROL_MAX_ENTRY 2 -#define TX_OCTET_COUNT_GOOD_BAD_MAX_ENTRY 2 -#define TX_FRAME_COUNT_GOOD_BAD_MAX_ENTRY 2 -#define TX_BROADCAST_FRAMES_GOOD_MAX_ENTRY 2 -#define TX_MULTICAST_FRAMES_GOOD_MAX_ENTRY 2 -#define TX_64OCTETS_FRAMES_GOOD_BAD_MAX_ENTRY 2 -#define TX_65TO127OCTETS_FRAMES_GOOD_BAD_MAX_ENTRY 2 -#define TX_128TO255OCTETS_FRAMES_GOOD_BAD_MAX_ENTRY 2 -#define TX_256TO511OCTETS_FRAMES_GOOD_BAD_MAX_ENTRY 2 -#define TX_512TO1023OCTETS_FRAMES_GOOD_BAD_MAX_ENTRY 2 -#define TX_1024TOMAXOCTETS_FRAMES_GOOD_BAD_MAX_ENTRY 2 -#define TX_UNICAST_FRAMES_GOOD_BAD_MAX_ENTRY 2 -#define TX_MULTICAST_FRAMES_GOOD_BAD_MAX_ENTRY 2 -#define TX_BROADCAST_FRAMES_GOOD_BAD_MAX_ENTRY 2 -#define TX_UNDERFERROR_FRAMES_MAX_ENTRY 2 -#define TX_SINGLE_COLLISION_GOOD_FRAMES_MAX_ENTRY 2 -#define TX_MULTIPLE_COLLISION_GOOD_FRAMES_MAX_ENTRY 2 -#define TX_DEFERRED_FRAMES_MAX_ENTRY 2 -#define TX_LATE_COLLISION_FRAMES_MAX_ENTRY 2 -#define TX_EXCESSIVE_COLLISION_FRAMES_MAX_ENTRY 2 -#define TX_CARRIER_ERROR_FRAMES_MAX_ENTRY 2 -#define TX_OCTET_COUNT_GOOD_MAX_ENTRY 2 -#define TX_FRAME_COUNT_GOOD_MAX_ENTRY 2 -#define TX_PAUSE_FRAMES_MAX_ENTRY 2 -#define TX_VLAN_FRAMES_GOOD_MAX_ENTRY 2 -#define TX_OSIZE_FRAMES_GOOD_MAX_ENTRY 2 -#define RX_FRAME_COUNT_GOOD_BAD_MAX_ENTRY 2 -#define RX_OCTET_COUNT_GOOD_BAD_MAX_ENTRY 2 -#define RX_OCTET_COUNT_GOOD_MAX_ENTRY 2 -#define RX_BROADCAST_FRAMES_GOOD_MAX_ENTRY 2 -#define RX_MULTICAST_FRAMES_GOOD_MAX_ENTRY 2 -#define RX_CRC_ERROR_FRAMES_MAX_ENTRY 2 -#define RX_ALIGNMENT_ERROR_FRAMES_MAX_ENTRY 2 -#define RX_RUNT_ERROR_FRAMES_MAX_ENTRY 2 -#define RX_JABBER_ERROR_FRAMES_MAX_ENTRY 2 -#define RX_UNDERSIZE_FRAMES_GOOD_MAX_ENTRY 2 -#define RX_OVERSIZE_FRAMES_GOOD_MAX_ENTRY 2 -#define RX_64OCTETS_FRAMES_GOOD_BAD_MAX_ENTRY 2 -#define RX_65TO127OCTETS_FRAMES_GOOD_BAD_MAX_ENTRY 2 -#define RX_128TO255OCTETS_FRAMES_GOOD_BAD_MAX_ENTRY 2 -#define RX_256TO511OCTETS_FRAMES_GOOD_BAD_MAX_ENTRY 2 -#define RX_512TO1023OCTETS_FRAMES_GOOD_BAD_MAX_ENTRY 2 -#define RX_1024TOMAXOCTETS_FRAMES_GOOD_BAD_MAX_ENTRY 2 -#define RX_UNICAST_FRAMES_GOOD_MAX_ENTRY 2 -#define RX_LENGTH_ERROR_FRAMES_MAX_ENTRY 2 -#define RX_OUTOFRANGE_FRAMES_MAX_ENTRY 2 -#define RX_PAUSE_FRAMES_MAX_ENTRY 2 -#define RX_FIFO_OVER_FLOW_FRAMES_MAX_ENTRY 2 -#define RX_VLAN_FRAMES_GOOD_BAD_MAX_ENTRY 2 -#define RX_WATCHDOG_ERROR_FRAMES_MAX_ENTRY 2 -#define RX_RECEIVE_ERROR_FRAMES_MAX_ENTRY 2 -#define RX_CONTROL_FRAMES_GOOD_MAX_ENTRY 2 - -sw_error_t -mp_mmc_control_get( - a_uint32_t dev_id, - a_uint32_t index, - union mmc_control_u *value); - -sw_error_t -mp_mmc_control_set( - a_uint32_t dev_id, - a_uint32_t index, - union mmc_control_u *value); - -sw_error_t -mp_tx_octet_count_good_bad_get( - a_uint32_t dev_id, - a_uint32_t index, - union tx_octet_count_good_bad_u *value); - -sw_error_t -mp_tx_frame_count_good_bad_get( - a_uint32_t dev_id, - a_uint32_t index, - union tx_frame_count_good_bad_u *value); - -sw_error_t -mp_tx_broadcast_frames_good_get( - a_uint32_t dev_id, - a_uint32_t index, - union tx_broadcast_frames_good_u *value); - -sw_error_t -mp_tx_multicast_frames_good_get( - a_uint32_t dev_id, - a_uint32_t index, - union tx_multicast_frames_good_u *value); - -sw_error_t -mp_tx_64octets_frames_good_bad_get( - a_uint32_t dev_id, - a_uint32_t index, - union tx_64octets_frames_good_bad_u *value); - -sw_error_t -mp_tx_65to127octets_frames_good_bad_get( - a_uint32_t dev_id, - a_uint32_t index, - union tx_65to127octets_frames_good_bad_u *value); - -sw_error_t -mp_tx_128to255octets_frames_good_bad_get( - a_uint32_t dev_id, - a_uint32_t index, - union tx_128to255octets_frames_good_bad_u *value); - -sw_error_t -mp_tx_256to511octets_frames_good_bad_get( - a_uint32_t dev_id, - a_uint32_t index, - union tx_256to511octets_frames_good_bad_u *value); - -sw_error_t -mp_tx_512to1023octets_frames_good_bad_get( - a_uint32_t dev_id, - a_uint32_t index, - union tx_512to1023octets_frames_good_bad_u *value); - -sw_error_t -mp_tx_1024tomaxoctets_frames_good_bad_get( - a_uint32_t dev_id, - a_uint32_t index, - union tx_1024tomaxoctets_frames_good_bad_u *value); - -sw_error_t -mp_tx_unicast_frames_good_bad_get( - a_uint32_t dev_id, - a_uint32_t index, - union tx_unicast_frames_good_bad_u *value); - -sw_error_t -mp_tx_multicast_frames_good_bad_get( - a_uint32_t dev_id, - a_uint32_t index, - union tx_multicast_frames_good_bad_u *value); - -sw_error_t -mp_tx_broadcast_frames_good_bad_get( - a_uint32_t dev_id, - a_uint32_t index, - union tx_broadcast_frames_good_bad_u *value); - -sw_error_t -mp_tx_underflow_error_frames_get( - a_uint32_t dev_id, - a_uint32_t index, - union tx_underflow_error_frames_u *value); - -sw_error_t -mp_tx_single_col_good_frames_get( - a_uint32_t dev_id, - a_uint32_t index, - union tx_single_collision_good_frames_u *value); - - -sw_error_t -mp_t_multi_col_good_frames_get( - a_uint32_t dev_id, - a_uint32_t index, - union tx_multiple_collision_good_frames_u *value); - -sw_error_t -mp_tx_defer_frames_get( - a_uint32_t dev_id, - a_uint32_t index, - union tx_deferred_frames_u *value); - -sw_error_t -mp_tx_late_col_frames_get( - a_uint32_t dev_id, - a_uint32_t index, - union tx_late_collision_frames_u *value); - -sw_error_t -mp_tx_excessive_col_frames_get( - a_uint32_t dev_id, - a_uint32_t index, - union tx_excessive_collision_frames_u *value); - -sw_error_t -mp_tx_carrier_error_frames_get( - a_uint32_t dev_id, - a_uint32_t index, - union tx_carrier_error_frames_u *value); - -sw_error_t -mp_tx_octet_count_good_get( - a_uint32_t dev_id, - a_uint32_t index, - union tx_octet_count_good_u *value); - -sw_error_t -mp_tx_frame_count_good_get( - a_uint32_t dev_id, - a_uint32_t index, - union tx_frame_count_good_u *value); - -sw_error_t -mp_tx_pause_frames_get( - a_uint32_t dev_id, - a_uint32_t index, - union tx_pause_frames_u *value); - -sw_error_t -mp_tx_vlan_frames_good_get( - a_uint32_t dev_id, - a_uint32_t index, - union tx_vlan_frames_good_u *value); - -sw_error_t -mp_tx_osize_frames_good_get( - a_uint32_t dev_id, - a_uint32_t index, - union tx_osize_frames_good_u *value); - -sw_error_t -mp_rx_frame_count_good_bad_get( - a_uint32_t dev_id, - a_uint32_t index, - union rx_frame_count_good_bad_u *value); - -sw_error_t -mp_rx_octet_count_good_bad_get( - a_uint32_t dev_id, - a_uint32_t index, - union rx_octet_count_good_bad_u *value); - -sw_error_t -mp_rx_octet_count_good_get( - a_uint32_t dev_id, - a_uint32_t index, - union rx_octet_count_good_u *value); - -sw_error_t -mp_rx_broadcast_frames_good_get( - a_uint32_t dev_id, - a_uint32_t index, - union rx_broadcast_frames_good_u *value); - -sw_error_t -mp_rx_multicast_frames_good_get( - a_uint32_t dev_id, - a_uint32_t index, - union rx_multicast_frames_good_u *value); - -sw_error_t -mp_rx_crc_error_frames_get( - a_uint32_t dev_id, - a_uint32_t index, - union rx_crc_error_frames_u *value); - -sw_error_t -mp_rx_alignment_error_frames_get( - a_uint32_t dev_id, - a_uint32_t index, - union rx_crc_error_frames_u *value); - -sw_error_t -mp_rx_runt_error_frames_get( - a_uint32_t dev_id, - a_uint32_t index, - union rx_runt_error_frames_u *value); - -sw_error_t -mp_rx_jabber_error_frames_get( - a_uint32_t dev_id, - a_uint32_t index, - union rx_jabber_error_frames_u *value); - -sw_error_t -mp_rx_undersize_frames_good_get( - a_uint32_t dev_id, - a_uint32_t index, - union rx_undersize_frames_good_u *value); - -sw_error_t -mp_rx_oversize_frames_good_get( - a_uint32_t dev_id, - a_uint32_t index, - union rx_oversize_frames_good_u *value); - -sw_error_t -mp_rx_64octets_frames_good_bad_get( - a_uint32_t dev_id, - a_uint32_t index, - union rx_64octets_frames_good_bad_u *value); - -sw_error_t -mp_rx_65to127octets_frames_good_bad_get( - a_uint32_t dev_id, - a_uint32_t index, - union rx_65to127octets_frames_good_bad_u *value); - -sw_error_t -mp_rx_128to255octets_frames_good_bad_get( - a_uint32_t dev_id, - a_uint32_t index, - union rx_128to255octets_frames_good_bad_u *value); - -sw_error_t -mp_rx_256to511octets_frames_good_bad_get( - a_uint32_t dev_id, - a_uint32_t index, - union rx_256to511octets_frames_good_bad_u *value); - -sw_error_t -mp_rx_512to1023octets_frames_good_bad_get( - a_uint32_t dev_id, - a_uint32_t index, - union rx_512to1023octets_frames_good_bad_u *value); - -sw_error_t -mp_rx_1024tomaxoctets_frames_good_bad_get( - a_uint32_t dev_id, - a_uint32_t index, - union rx_1024tomaxoctets_frames_good_bad_u *value); - -sw_error_t -mp_rx_unicast_frames_good_get( - a_uint32_t dev_id, - a_uint32_t index, - union rx_unicast_frames_good_u *value); - -sw_error_t -mp_rx_length_error_frames_get( - a_uint32_t dev_id, - a_uint32_t index, - union rx_length_error_frames_u *value); - -sw_error_t -mp_rx_outofrange_frames_get( - a_uint32_t dev_id, - a_uint32_t index, - union rx_outofrange_frames_u *value); - -sw_error_t -mp_rx_pause_frames_get( - a_uint32_t dev_id, - a_uint32_t index, - union rx_pause_frames_u *value); - -sw_error_t -mp_rx_fifo_over_flow_frames_get( - a_uint32_t dev_id, - a_uint32_t index, - union rx_fifo_over_flow_frames_u *value); - -sw_error_t -mp_rx_vlan_frames_good_bad_get( - a_uint32_t dev_id, - a_uint32_t index, - union rx_vlan_frames_good_bad_u *value); - -sw_error_t -mp_rx_watchdog_error_frames_get( - a_uint32_t dev_id, - a_uint32_t index, - union rx_watchdog_error_frames_u *value); - -sw_error_t -mp_rx_receive_error_frames_get( - a_uint32_t dev_id, - a_uint32_t index, - union rx_receive_error_frames_u *value); - -sw_error_t -mp_rx_control_frames_good_get( - a_uint32_t dev_id, - a_uint32_t index, - union rx_control_frames_good_u *value); -#endif - diff --git a/feeds/ipq807x/qca-ssdk/src/include/hsl/mp/mp_mib_reg.h b/feeds/ipq807x/qca-ssdk/src/include/hsl/mp/mp_mib_reg.h deleted file mode 100755 index 45929f154..000000000 --- a/feeds/ipq807x/qca-ssdk/src/include/hsl/mp/mp_mib_reg.h +++ /dev/null @@ -1,875 +0,0 @@ -/* - * Copyright (c) 2020, The Linux Foundation. All rights reserved. - * - * Permission to use, copy, modify, and/or distribute this software for any - * purpose with or without fee is hereby granted, provided that the above - * copyright notice and this permission notice appear in all copies. - * - * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES - * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR - * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES - * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN - * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF - * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. - */ - -#ifndef MP_MIB_REG_H -#define MP_MIB_REG_H - -/*[register] MMC_CONTROL*/ -#define MMC_CONTROL -#define MMC_CONTROL_ADDRESS 0x100 -#define MMC_CONTROL_NUM 2 -#define MMC_CONTROL_INC 0x100000 -#define MMC_CONTROL_DEFAULT 0x0 - -struct mmc_control { - a_uint32_t cntrst:1; - a_uint32_t cntstopro:1; - a_uint32_t rstonrd:1; - a_uint32_t cntfreez:1; - a_uint32_t cntprst:1; - a_uint32_t cntprstlvl:1; - a_uint32_t _reserved1:2; - a_uint32_t ucdbc:8; - a_uint32_t _reserved2:23; -}; - -union mmc_control_u { - a_uint32_t val; - struct mmc_control bf; -}; - -/*[register] TX_OCTET_COUNT_GOOD_BAD*/ -#define TX_OCTET_COUNT_GOOD_BAD -#define TX_OCTET_COUNT_GOOD_BAD_ADDRESS 0x114 -#define TX_OCTET_COUNT_GOOD_BAD_NUM 2 -#define TX_OCTET_COUNT_GOOD_BAD_INC 0x100000 -#define TX_OCTET_COUNT_GOOD_BAD_DEFAULT 0x0 - -struct tx_octet_count_good_bad { - a_uint32_t txoctgb:32; -}; - -union tx_octet_count_good_bad_u { - a_uint32_t val; - struct tx_octet_count_good_bad bf; -}; - -/*[register] TX_FRAME_COUNT_GOOD_BAD*/ -#define TX_FRAME_COUNT_GOOD_BAD -#define TX_FRAME_COUNT_GOOD_BAD_ADDRESS 0x118 -#define TX_FRAME_COUNT_GOOD_BAD_NUM 2 -#define TX_FRAME_COUNT_GOOD_BAD_INC 0x100000 -#define TX_FRAME_COUNT_GOOD_BAD_DEFAULT 0x0 - -struct tx_frame_count_good_bad { - a_uint32_t txfrmgb:32; -}; - -union tx_frame_count_good_bad_u { - a_uint32_t val; - struct tx_frame_count_good_bad bf; -}; - -/*[register] TX_BROADCAST_FRAMES_GOOD*/ -#define TX_BROADCAST_FRAMES_GOOD -#define TX_BROADCAST_FRAMES_GOOD_ADDRESS 0x11c -#define TX_BROADCAST_FRAMES_GOOD_NUM 2 -#define TX_BROADCAST_FRAMES_GOOD_INC 0x100000 -#define TX_BROADCAST_FRAMES_GOOD_DEFAULT 0x0 - -struct tx_broadcast_frames_good { - a_uint32_t txbcastg:32; -}; - -union tx_broadcast_frames_good_u { - a_uint32_t val; - struct tx_broadcast_frames_good bf; -}; - -/*[register] TX_MULTICAST_FRAMES_GOOD*/ -#define TX_MULTICAST_FRAMES_GOOD -#define TX_MULTICAST_FRAMES_GOOD_ADDRESS 0x120 -#define TX_MULTICAST_FRAMES_GOOD_NUM 2 -#define TX_MULTICAST_FRAMES_GOOD_INC 0x100000 -#define TX_MULTICAST_FRAMES_GOOD_DEFAULT 0x0 - -struct tx_multicast_frames_good { - a_uint32_t txmcastg:32; -}; - -union tx_multicast_frames_good_u { - a_uint32_t val; - struct tx_multicast_frames_good bf; -}; - -/*[register] TX_64OCTETS_FRAMES_GOOD_BAD*/ -#define TX_64OCTETS_FRAMES_GOOD_BAD -#define TX_64OCTETS_FRAMES_GOOD_BAD_ADDRESS 0x124 -#define TX_64OCTETS_FRAMES_GOOD_BAD_NUM 2 -#define TX_64OCTETS_FRAMES_GOOD_BAD_INC 0x100000 -#define TX_64OCTETS_FRAMES_GOOD_BAD_DEFAULT 0x0 - -struct tx_64octets_frames_good_bad { - a_uint32_t tx64octgb:32; -}; - -union tx_64octets_frames_good_bad_u { - a_uint32_t val; - struct tx_64octets_frames_good_bad bf; -}; - -/*[register] TX_65TO127OCTETS_FRAMES_GOOD_BAD*/ -#define TX_65TO127OCTETS_FRAMES_GOOD_BAD -#define TX_65TO127OCTETS_FRAMES_GOOD_BAD_ADDRESS 0x128 -#define TX_65TO127OCTETS_FRAMES_GOOD_BAD_NUM 2 -#define TX_65TO127OCTETS_FRAMES_GOOD_BAD_INC 0x100000 -#define TX_65TO127OCTETS_FRAMES_GOOD_BAD_DEFAULT 0x0 - -struct tx_65to127octets_frames_good_bad { - a_uint32_t tx65_127octgb:32; -}; - -union tx_65to127octets_frames_good_bad_u { - a_uint32_t val; - struct tx_65to127octets_frames_good_bad bf; -}; - -/*[register] TX_128TO255OCTETS_FRAMES_GOOD_BAD*/ -#define TX_128TO255OCTETS_FRAMES_GOOD_BAD -#define TX_128TO255OCTETS_FRAMES_GOOD_BAD_ADDRESS 0x12c -#define TX_128TO255OCTETS_FRAMES_GOOD_BAD_NUM 2 -#define TX_128TO255OCTETS_FRAMES_GOOD_BAD_INC 0x100000 -#define TX_128TO255OCTETS_FRAMES_GOOD_BAD_DEFAULT 0x0 - -struct tx_128to255octets_frames_good_bad { - a_uint32_t tx128_255octgb:32; -}; - -union tx_128to255octets_frames_good_bad_u { - a_uint32_t val; - struct tx_128to255octets_frames_good_bad bf; -}; - -/*[register] TX_256TO511OCTETS_FRAMES_GOOD_BAD*/ -#define TX_256TO511OCTETS_FRAMES_GOOD_BAD -#define TX_256TO511OCTETS_FRAMES_GOOD_BAD_ADDRESS 0x130 -#define TX_256TO511OCTETS_FRAMES_GOOD_BAD_NUM 2 -#define TX_256TO511OCTETS_FRAMES_GOOD_BAD_INC 0x100000 -#define TX_256TO511OCTETS_FRAMES_GOOD_BAD_DEFAULT 0x0 - -struct tx_256to511octets_frames_good_bad { - a_uint32_t tx256_511octgb:32; -}; - -union tx_256to511octets_frames_good_bad_u { - a_uint32_t val; - struct tx_256to511octets_frames_good_bad bf; -}; - -/*[register] TX_512TO1023OCTETS_FRAMES_GOOD_BAD*/ -#define TX_512TO1023OCTETS_FRAMES_GOOD_BAD -#define TX_512TO1023OCTETS_FRAMES_GOOD_BAD_ADDRESS 0x134 -#define TX_512TO1023OCTETS_FRAMES_GOOD_BAD_NUM 2 -#define TX_512TO1023OCTETS_FRAMES_GOOD_BAD_INC 0x100000 -#define TX_512TO1023OCTETS_FRAMES_GOOD_BAD_DEFAULT 0x0 - -struct tx_512to1023octets_frames_good_bad { - a_uint32_t tx512_1023octgb:32; -}; - -union tx_512to1023octets_frames_good_bad_u { - a_uint32_t val; - struct tx_512to1023octets_frames_good_bad bf; -}; - -/*[register] TX_1024TOMAXOCTETS_FRAMES_GOOD_BAD*/ -#define TX_1024TOMAXOCTETS_FRAMES_GOOD_BAD -#define TX_1024TOMAXOCTETS_FRAMES_GOOD_BAD_ADDRESS 0x138 -#define TX_1024TOMAXOCTETS_FRAMES_GOOD_BAD_NUM 2 -#define TX_1024TOMAXOCTETS_FRAMES_GOOD_BAD_INC 0x100000 -#define TX_1024TOMAXOCTETS_FRAMES_GOOD_BAD_DEFAULT 0x0 - -struct tx_1024tomaxoctets_frames_good_bad { - a_uint32_t tx1024_maxoctgb:32; -}; - -union tx_1024tomaxoctets_frames_good_bad_u { - a_uint32_t val; - struct tx_1024tomaxoctets_frames_good_bad bf; -}; - -/*[register] TX_UNICAST_FRAMES_GOOD_BAD*/ -#define TX_UNICAST_FRAMES_GOOD_BAD -#define TX_UNICAST_FRAMES_GOOD_BAD_ADDRESS 0x13c -#define TX_UNICAST_FRAMES_GOOD_BAD_NUM 2 -#define TX_UNICAST_FRAMES_GOOD_BAD_INC 0x100000 -#define TX_UNICAST_FRAMES_GOOD_BAD_DEFAULT 0x0 - -struct tx_unicast_frames_good_bad { - a_uint32_t txucastgb:32; -}; - -union tx_unicast_frames_good_bad_u { - a_uint32_t val; - struct tx_unicast_frames_good_bad bf; -}; - -/*[register] TX_MULTICAST_FRAMES_GOOD_BAD*/ -#define TX_MULTICAST_FRAMES_GOOD_BAD -#define TX_MULTICAST_FRAMES_GOOD_BAD_ADDRESS 0x140 -#define TX_MULTICAST_FRAMES_GOOD_BAD_NUM 2 -#define TX_MULTICAST_FRAMES_GOOD_BAD_INC 0x100000 -#define TX_MULTICAST_FRAMES_GOOD_BAD_DEFAULT 0x0 - -struct tx_multicast_frames_good_bad { - a_uint32_t txmcastgb:32; -}; - -union tx_multicast_frames_good_bad_u { - a_uint32_t val; - struct tx_multicast_frames_good_bad bf; -}; - -/*[register] TX_BROADCAST_FRAMES_GOOD_BAD*/ -#define TX_BROADCAST_FRAMES_GOOD_BAD -#define TX_BROADCAST_FRAMES_GOOD_BAD_ADDRESS 0x144 -#define TX_BROADCAST_FRAMES_GOOD_BAD_NUM 2 -#define TX_BROADCAST_FRAMES_GOOD_BAD_INC 0x100000 -#define TX_BROADCAST_FRAMES_GOOD_BAD_DEFAULT 0x0 - -struct tx_broadcast_frames_good_bad { - a_uint32_t txbcastgb:32; -}; - -union tx_broadcast_frames_good_bad_u { - a_uint32_t val; - struct tx_broadcast_frames_good_bad bf; -}; - -/*[register] TX_UNDERFLOW_ERROR_FRAMES*/ -#define TX_UNDERFLOW_ERROR_FRAMES -#define TX_UNDERFLOW_ERROR_FRAMES_ADDRESS 0x148 -#define TX_UNDERFLOW_ERROR_FRAMES_NUM 2 -#define TX_UNDERFLOW_ERROR_FRAMES_INC 0x100000 -#define TX_UNDERFLOW_ERROR_FRAMES_DEFAULT 0x0 - -struct tx_underflow_error_frames { - a_uint32_t txundrflw:32; -}; - -union tx_underflow_error_frames_u { - a_uint32_t val; - struct tx_underflow_error_frames bf; -}; - -/*[register] TX_SINGLE_COLLISION_GOOD_FRAMES*/ -#define TX_SINGLE_COLLISION_GOOD_FRAMES -#define TX_SINGLE_COLLISION_GOOD_FRAMES_ADDRESS 0x14c -#define TX_SINGLE_COLLISION_GOOD_FRAMES_NUM 2 -#define TX_SINGLE_COLLISION_GOOD_FRAMES_INC 0x100000 -#define TX_SINGLE_COLLISION_GOOD_FRAMES_DEFAULT 0x0 - -struct tx_single_collision_good_frames { - a_uint32_t txsnglcolg:32; -}; - -union tx_single_collision_good_frames_u { - a_uint32_t val; - struct tx_single_collision_good_frames bf; -}; - -/*[register] TX_MULTIPLE_COLLISION_GOOD_FRAMES*/ -#define TX_MULTIPLE_COLLISION_GOOD_FRAMES -#define TX_MULTIPLE_COLLISION_GOOD_FRAMES_ADDRESS 0x150 -#define TX_MULTIPLE_COLLISION_GOOD_FRAMES_NUM 2 -#define TX_MULTIPLE_COLLISION_GOOD_FRAMES_INC 0x100000 -#define TX_MULTIPLE_COLLISION_GOOD_FRAMES_DEFAULT 0x0 - -struct tx_multiple_collision_good_frames { - a_uint32_t txmultcolg:32; -}; - -union tx_multiple_collision_good_frames_u { - a_uint32_t val; - struct tx_multiple_collision_good_frames bf; -}; - -/*[register] TX_DEFERRED_FRAMES*/ -#define TX_DEFERRED_FRAMES -#define TX_DEFERRED_FRAMES_ADDRESS 0x154 -#define TX_DEFERRED_FRAMES_NUM 2 -#define TX_DEFERRED_FRAMES_INC 0x100000 -#define TX_DEFERRED_FRAMES_DEFAULT 0x0 - -struct tx_deferred_frames { - a_uint32_t txdefrd:32; -}; - -union tx_deferred_frames_u { - a_uint32_t val; - struct tx_deferred_frames bf; -}; - -/*[register] TX_LATE_COLLISION_FRAMES*/ -#define TX_LATE_COLLISION_FRAMES -#define TX_LATE_COLLISION_FRAMES_ADDRESS 0x158 -#define TX_LATE_COLLISION_FRAMES_NUM 2 -#define TX_LATE_COLLISION_FRAMES_INC 0x100000 -#define TX_LATE_COLLISION_FRAMES_DEFAULT 0x0 - -struct tx_late_collision_frames { - a_uint32_t txlatecol:32; -}; - -union tx_late_collision_frames_u { - a_uint32_t val; - struct tx_late_collision_frames bf; -}; - -/*[register] TX_EXCESSIVE_COLLISION_FRAMES*/ -#define TX_EXCESSIVE_COLLISION_FRAMES -#define TX_EXCESSIVE_COLLISION_FRAMES_ADDRESS 0x15c -#define TX_EXCESSIVE_COLLISION_FRAMES_NUM 2 -#define TX_EXCESSIVE_COLLISION_FRAMES_INC 0x100000 -#define TX_EXCESSIVE_COLLISION_FRAMES_DEFAULT 0x0 - -struct tx_excessive_collision_frames { - a_uint32_t txexscol:32; -}; - -union tx_excessive_collision_frames_u { - a_uint32_t val; - struct tx_excessive_collision_frames bf; -}; - -/*[register] TX_CARRIER_ERROR_FRAMES*/ -#define TX_CARRIER_ERROR_FRAMES -#define TX_CARRIER_ERROR_FRAMES_ADDRESS 0x160 -#define TX_CARRIER_ERROR_FRAMES_NUM 2 -#define TX_CARRIER_ERROR_FRAMES_INC 0x100000 -#define TX_CARRIER_ERROR_FRAMES_DEFAULT 0x0 - -struct tx_carrier_error_frames { - a_uint32_t txexscol:32; -}; - -union tx_carrier_error_frames_u { - a_uint32_t val; - struct tx_carrier_error_frames bf; -}; - -/*[register] TX_OCTET_COUNT_GOOD*/ -#define TX_OCTET_COUNT_GOOD -#define TX_OCTET_COUNT_GOOD_ADDRESS 0x164 -#define TX_OCTET_COUNT_GOOD_NUM 2 -#define TX_OCTET_COUNT_GOOD_INC 0x100000 -#define TX_OCTET_COUNT_GOOD_DEFAULT 0x0 - -struct tx_octet_count_good { - a_uint32_t txoctg:32; -}; - -union tx_octet_count_good_u { - a_uint32_t val; - struct tx_octet_count_good bf; -}; - -/*[register] TX_FRAME_COUNT_GOOD*/ -#define TX_FRAME_COUNT_GOOD -#define TX_FRAME_COUNT_GOOD_ADDRESS 0x168 -#define TX_FRAME_COUNT_GOOD_NUM 2 -#define TX_FRAME_COUNT_GOOD_INC 0x100000 -#define TX_FRAME_COUNT_GOOD_DEFAULT 0x0 - -struct tx_frame_count_good { - a_uint32_t txfrmg:32; -}; - -union tx_frame_count_good_u { - a_uint32_t val; - struct tx_frame_count_good bf; -}; - -/*[register] TX_EXCESSIVE_DEFERRAL_ERROR*/ -#define TX_EXCESSIVE_DEFERRAL_ERROR -#define TX_EXCESSIVE_DEFERRAL_ERROR_ADDRESS 0x16c -#define TX_EXCESSIVE_DEFERRAL_ERROR_NUM 2 -#define TX_EXCESSIVE_DEFERRAL_ERROR_INC 0x100000 -#define TX_EXCESSIVE_DEFERRAL_ERRORD_DEFAULT 0x0 - -struct tx_excessive_deferral_error { - a_uint32_t txexsdef:32; -}; - -union tx_excessive_deferral_error_u { - a_uint32_t val; - struct tx_excessive_deferral_error bf; -}; - -/*[register] TX_PAUSE_FRAMES*/ -#define TX_PAUSE_FRAMES -#define TX_PAUSE_FRAMES_ADDRESS 0x170 -#define TX_PAUSE_FRAMES_NUM 2 -#define TX_PAUSE_FRAMES_INC 0x100000 -#define TX_PAUSE_FRAMES_DEFAULT 0x0 - -struct tx_pause_frames { - a_uint32_t txpauseg:32; -}; - -union tx_pause_frames_u { - a_uint32_t val; - struct tx_pause_frames bf; -}; - -/*[register] TX_VLAN_FRAMES_GOOD*/ -#define TX_VLAN_FRAMES_GOOD -#define TX_VLAN_FRAMES_GOOD_ADDRESS 0x174 -#define TX_VLAN_FRAMES_GOOD_NUM 2 -#define TX_VLAN_FRAMES_GOOD_INC 0x100000 -#define TX_VLAN_FRAMES_GOOD_DEFAULT 0x0 - -struct tx_vlan_frames_good { - a_uint32_t txvlang:32; -}; - -union tx_vlan_frames_good_u { - a_uint32_t val; - struct tx_vlan_frames_good bf; -}; - -/*[register] TX_OSIZE_FRAMES_GOOD*/ -#define TX_OSIZE_FRAMES_GOOD -#define TX_OSIZE_FRAMES_GOOD_ADDRESS 0x178 -#define TX_OSIZE_FRAMES_GOOD_NUM 2 -#define TX_OSIZE_FRAMES_GOOD_INC 0x100000 -#define TX_OSIZE_FRAMES_GOOD_DEFAULT 0x0 - -struct tx_osize_frames_good { - a_uint32_t txosize:32; -}; - -union tx_osize_frames_good_u { - a_uint32_t val; - struct tx_osize_frames_good bf; -}; - -/*[register] RX_FRAME_COUNT_GOOD_BAD*/ -#define RX_FRAME_COUNT_GOOD_BAD -#define RX_FRAME_COUNT_GOOD_BAD_ADDRESS 0x180 -#define RX_FRAME_COUNT_GOOD_BAD_NUM 2 -#define RX_FRAME_COUNT_GOOD_BAD_INC 0x100000 -#define RX_FRAME_COUNT_GOOD_BAD_DEFAULT 0x0 - -struct rx_frame_count_good_bad { - a_uint32_t rxfrmgb:32; -}; - -union rx_frame_count_good_bad_u { - a_uint32_t val; - struct rx_frame_count_good_bad bf; -}; - -/*[register] RX_OCTET_COUNT_GOOD_BAD*/ -#define RX_OCTET_COUNT_GOOD_BAD -#define RX_OCTET_COUNT_GOOD_BAD_ADDRESS 0x184 -#define RX_OCTET_COUNT_GOOD_BAD_NUM 2 -#define RX_OCTET_COUNT_GOOD_BAD_INC 0x100000 -#define RX_OCTET_COUNT_GOOD_BAD_DEFAULT 0x0 - -struct rx_octet_count_good_bad { - a_uint32_t rxoctgb:32; -}; - -union rx_octet_count_good_bad_u { - a_uint32_t val; - struct rx_octet_count_good_bad bf; -}; - -/*[register] RX_OCTET_COUNT_GOOD*/ -#define RX_OCTET_COUNT_GOOD -#define RX_OCTET_COUNT_GOOD_ADDRESS 0x188 -#define RX_OCTET_COUNT_GOOD_NUM 2 -#define RX_OCTET_COUNT_GOOD_INC 0x100000 -#define RX_OCTET_COUNT_GOOD_DEFAULT 0x0 - -struct rx_octet_count_good { - a_uint32_t rxoctg:32; -}; - -union rx_octet_count_good_u { - a_uint32_t val; - struct rx_octet_count_good bf; -}; - -/*[register] RX_BROADCAST_FRAMES_GOOD*/ -#define RX_BROADCAST_FRAMES_GOOD -#define RX_BROADCAST_FRAMES_GOOD_ADDRESS 0x18c -#define RX_BROADCAST_FRAMES_GOOD_NUM 2 -#define RX_BROADCAST_FRAMES_GOOD_INC 0x100000 -#define RX_BROADCAST_FRAMES_GOOD_DEFAULT 0x0 - -struct rx_broadcast_frames_good { - a_uint32_t rxbcastg:32; -}; - -union rx_broadcast_frames_good_u { - a_uint32_t val; - struct rx_broadcast_frames_good bf; -}; - -/*[register] RX_MULTICAST_FRAMES_GOOD*/ -#define RX_MULTICAST_FRAMES_GOOD -#define RX_MULTICAST_FRAMES_GOOD_ADDRESS 0x190 -#define RX_MULTICAST_FRAMES_GOOD_NUM 2 -#define RX_MULTICAST_FRAMES_GOOD_INC 0x100000 -#define RX_MULTICAST_FRAMES_GOOD_DEFAULT 0x0 - -struct rx_multicast_frames_good { - a_uint32_t rxmcastg:32; -}; - -union rx_multicast_frames_good_u { - a_uint32_t val; - struct rx_multicast_frames_good bf; -}; - -/*[register] RX_CRC_ERROR_FRAMES*/ -#define RX_CRC_ERROR_FRAMES -#define RX_CRC_ERROR_FRAMES_ADDRESS 0x194 -#define RX_CRC_ERROR_FRAMES_NUM 2 -#define RX_CRC_ERROR_FRAMES_INC 0x100000 -#define RX_CRC_ERROR_FRAMES_DEFAULT 0x0 - -struct rx_crc_error_frames { - a_uint32_t rxcrcer:32; -}; - -union rx_crc_error_frames_u { - a_uint32_t val; - struct rx_crc_error_frames bf; -}; - -/*[register] RX_ALIGNMENT_ERROR_FRAMES*/ -#define RX_ALIGNMENT_ERROR_FRAMES -#define RX_ALIGNMENT_ERROR_FRAMES_ADDRESS 0x198 -#define RX_ALIGNMENT_ERROR_FRAMES_NUM 2 -#define RX_ALIGNMENT_ERROR_FRAMES_INC 0x100000 -#define RX_ALIGNMENT_ERROR_FRAMES_DEFAULT 0x0 - -struct rx_alignment_error_frames { - a_uint32_t rxalgnerr:32; -}; - -union rx_alignment_error_frames_u { - a_uint32_t val; - struct rx_alignment_error_frames bf; -}; - -/*[register] RX_RUNT_ERROR_FRAMES*/ -#define RX_RUNT_ERROR_FRAMES -#define RX_RUNT_ERROR_FRAMES_ADDRESS 0x19c -#define RX_RUNT_ERROR_FRAMES_NUM 2 -#define RX_RUNT_ERROR_FRAMES_INC 0x100000 -#define RX_RUNT_ERROR_FRAMES_DEFAULT 0x0 - -struct rx_runt_error_frames { - a_uint32_t rxrunter:32; -}; - -union rx_runt_error_frames_u { - a_uint32_t val; - struct rx_runt_error_frames bf; -}; - -/*[register] RX_JABBER_ERROR_FRAMES*/ -#define RX_JABBER_ERROR_FRAMES -#define RX_JABBER_ERROR_FRAMES_ADDRESS 0x1a0 -#define RX_JABBER_ERROR_FRAMES_NUM 2 -#define RX_JABBER_ERROR_FRAMES_INC 0x100000 -#define RX_JABBER_ERROR_FRAMES_DEFAULT 0x0 - -struct rx_jabber_error_frames { - a_uint32_t rxjaberer:32; -}; - -union rx_jabber_error_frames_u { - a_uint32_t val; - struct rx_jabber_error_frames bf; -}; - -/*[register] RX_UNDERSIZE_FRAMES_GOOD*/ -#define RX_UNDERSIZE_FRAMES_GOOD -#define RX_UNDERSIZE_FRAMES_GOOD_ADDRESS 0x1a4 -#define RX_UNDERSIZE_FRAMES_GOOD_NUM 2 -#define RX_UNDERSIZE_FRAMES_GOOD_INC 0x100000 -#define RX_UNDERSIZE_FRAMES_GOOD_DEFAULT 0x0 - -struct rx_undersize_frames_good { - a_uint32_t rxusizeg:32; -}; - -union rx_undersize_frames_good_u { - a_uint32_t val; - struct rx_undersize_frames_good bf; -}; - -/*[register] RX_OVERSIZE_FRAMES_GOOD*/ -#define RX_OVERSIZE_FRAMES_GOOD -#define RX_OVERSIZE_FRAMES_GOOD_ADDRESS 0x1a8 -#define RX_OVERSIZE_FRAMES_GOOD_NUM 2 -#define RX_OVERSIZE_FRAMES_GOOD_INC 0x100000 -#define RX_OVERSIZE_FRAMES_GOOD_DEFAULT 0x0 - -struct rx_oversize_frames_good { - a_uint32_t rxosizeg:32; -}; - -union rx_oversize_frames_good_u { - a_uint32_t val; - struct rx_oversize_frames_good bf; -}; - -/*[register] RX_64OCTETS_FRAMES_GOOD_BAD*/ -#define RX_64OCTETS_FRAMES_GOOD_BAD -#define RX_64OCTETS_FRAMES_GOOD_BAD_ADDRESS 0x1ac -#define RX_64OCTETS_FRAMES_GOOD_BAD_NUM 2 -#define RX_64OCTETS_FRAMES_GOOD_BAD_INC 0x100000 -#define RX_64OCTETS_FRAMES_GOOD_BAD_DEFAULT 0x0 - -struct rx_64octets_frames_good_bad { - a_uint32_t rx64octgb:32; -}; - -union rx_64octets_frames_good_bad_u { - a_uint32_t val; - struct rx_64octets_frames_good_bad bf; -}; - -/*[register] RX_65TO127OCTETS_FRAMES_GOOD_BAD*/ -#define RX_65TO127OCTETS_FRAMES_GOOD_BAD -#define RX_65TO127OCTETS_FRAMES_GOOD_BAD_ADDRESS 0x1b0 -#define RX_65TO127OCTETS_FRAMES_GOOD_BAD_NUM 2 -#define RX_65TO127OCTETS_FRAMES_GOOD_BAD_INC 0x100000 -#define RX_65TO127OCTETS_FRAMES_GOOD_BAD_DEFAULT 0x0 - -struct rx_65to127octets_frames_good_bad { - a_uint32_t rx65_127octgb:32; -}; - -union rx_65to127octets_frames_good_bad_u { - a_uint32_t val; - struct rx_65to127octets_frames_good_bad bf; -}; - -/*[register] RX_128TO255OCTETS_FRAMES_GOOD_BAD*/ -#define RX_128TO255OCTETS_FRAMES_GOOD_BAD -#define RX_128TO255OCTETS_FRAMES_GOOD_BAD_ADDRESS 0x1b4 -#define RX_128TO255OCTETS_FRAMES_GOOD_BAD_NUM 2 -#define RX_128TO255OCTETS_FRAMES_GOOD_BAD_INC 0x100000 -#define RX_128TO255OCTETS_FRAMES_GOOD_BAD_DEFAULT 0x0 - -struct rx_128to255octets_frames_good_bad { - a_uint32_t rx128_255octgb:32; -}; - -union rx_128to255octets_frames_good_bad_u { - a_uint32_t val; - struct rx_128to255octets_frames_good_bad bf; -}; - -/*[register] RX_256TO511OCTETS_FRAMES_GOOD_BAD*/ -#define RX_256TO511OCTETS_FRAMES_GOOD_BAD -#define RX_256TO511OCTETS_FRAMES_GOOD_BAD_ADDRESS 0x1b8 -#define RX_256TO511OCTETS_FRAMES_GOOD_BAD_NUM 2 -#define RX_256TO511OCTETS_FRAMES_GOOD_BAD_INC 0x100000 -#define RX_256TO511OCTETS_FRAMES_GOOD_BAD_DEFAULT 0x0 - -struct rx_256to511octets_frames_good_bad { - a_uint32_t rx256_511octgb:32; -}; - -union rx_256to511octets_frames_good_bad_u { - a_uint32_t val; - struct rx_256to511octets_frames_good_bad bf; -}; - -/*[register] RX_512TO1023OCTETS_FRAMES_GOOD_BAD*/ -#define RX_512TO1023OCTETS_FRAMES_GOOD_BAD -#define RX_512TO1023OCTETS_FRAMES_GOOD_BAD_ADDRESS 0x1bc -#define RX_512TO1023OCTETS_FRAMES_GOOD_BAD_NUM 2 -#define RX_512TO1023OCTETS_FRAMES_GOOD_BAD_INC 0x100000 -#define RX_512TO1023OCTETS_FRAMES_GOOD_BAD_DEFAULT 0x0 - -struct rx_512to1023octets_frames_good_bad { - a_uint32_t rx512_1023octgb:32; -}; - -union rx_512to1023octets_frames_good_bad_u { - a_uint32_t val; - struct rx_512to1023octets_frames_good_bad bf; -}; - -/*[register] RX_1024TOMAXOCTETS_FRAMES_GOOD_BAD*/ -#define RX_1024TOMAXOCTETS_FRAMES_GOOD_BAD -#define RX_1024TOMAXOCTETS_FRAMES_GOOD_BAD_ADDRESS 0x1c0 -#define RX_1024TOMAXOCTETS_FRAMES_GOOD_BAD_NUM 2 -#define RX_1024TOMAXOCTETS_FRAMES_GOOD_BAD_INC 0x100000 -#define RX_1024TOMAXOCTETS_FRAMES_GOOD_BAD_DEFAULT 0x0 - -struct rx_1024tomaxoctets_frames_good_bad { - a_uint32_t rx1024_maxgboct:32; -}; - -union rx_1024tomaxoctets_frames_good_bad_u { - a_uint32_t val; - struct rx_1024tomaxoctets_frames_good_bad bf; -}; - -/*[register] RX_UNICAST_FRAMES_GOOD*/ -#define RX_UNICAST_FRAMES_GOOD -#define RX_UNICAST_FRAMES_GOOD_ADDRESS 0x1c4 -#define RX_UNICAST_FRAMES_GOOD_NUM 2 -#define RX_UNICAST_FRAMES_GOOD_INC 0x100000 -#define RX_UNICAST_FRAMES_GOOD_DEFAULT 0x0 - -struct rx_unicast_frames_good { - a_uint32_t rxucastg:32; -}; - -union rx_unicast_frames_good_u { - a_uint32_t val; - struct rx_unicast_frames_good bf; -}; - -/*[register] RX_LENGTH_ERROR_FRAMES*/ -#define RX_LENGTH_ERROR_FRAMES -#define RX_LENGTH_ERROR_FRAMES_ADDRESS 0x1c8 -#define RX_LENGTH_ERROR_FRAMES_NUM 2 -#define RX_LENGTH_ERROR_FRAMES_INC 0x100000 -#define RX_LENGTH_ERROR_FRAMES_DEFAULT 0x0 - -struct rx_length_error_frames { - a_uint32_t rxlenerr:32; -}; - -union rx_length_error_frames_u { - a_uint32_t val; - struct rx_length_error_frames bf; -}; - -/*[register] RX_OUTOFRANGE_FRAMES*/ -#define RX_OUTOFRANGE_FRAMES -#define RX_OUTOFRANGE_FRAMES_ADDRESS 0x1cc -#define RX_OUTOFRANGE_FRAMES_NUM 2 -#define RX_OUTOFRANGE_FRAMES_INC 0x100000 -#define RX_OUTOFRANGE_FRAMES_DEFAULT 0x0 - -struct rx_outofrange_frames { - a_uint32_t rxorange:32; -}; - -union rx_outofrange_frames_u { - a_uint32_t val; - struct rx_outofrange_frames bf; -}; - -/*[register] RX_PAUSE_FRAMES*/ -#define RX_PAUSE_FRAMES -#define RX_PAUSE_FRAMES_ADDRESS 0x1d0 -#define RX_PAUSE_FRAMES_NUM 2 -#define RX_PAUSE_FRAMES_INC 0x100000 -#define RX_PAUSE_FRAMES_DEFAULT 0x0 - -struct rx_pause_frames { - a_uint32_t rxpause:32; -}; - -union rx_pause_frames_u { - a_uint32_t val; - struct rx_pause_frames bf; -}; - -/*[register] RX_FIFOOVERFW_FRAMES*/ -#define RX_FIFOOVERFW_FRAMES -#define RX_FIFOOVERFW_FRAMES_ADDRESS 0x1d4 -#define RX_FIFOOVERFW_FRAMES_NUM 2 -#define RX_FIFOOVERFW_FRAMES_INC 0x100000 -#define RX_FIFOOVERFW_FRAMES_DEFAULT 0x0 - -struct rx_fifo_over_flow_frames { - a_uint32_t rxfovf:32; -}; - -union rx_fifo_over_flow_frames_u { - a_uint32_t val; - struct rx_fifo_over_flow_frames bf; -}; - -/*[register] RX_VLAN_FRAMES_GOOD_BAD*/ -#define RX_VLAN_FRAMES_GOOD_BAD -#define RX_VLAN_FRAMES_GOOD_BAD_ADDRESS 0x1d8 -#define RX_VLAN_FRAMES_GOOD_BAD_NUM 2 -#define RX_VLAN_FRAMES_GOOD_BAD_INC 0x100000 -#define RX_VLAN_FRAMES_GOOD_BAD_DEFAULT 0x0 - -struct rx_vlan_frames_good_bad { - a_uint32_t rxvlangb:32; -}; - -union rx_vlan_frames_good_bad_u { - a_uint32_t val; - struct rx_vlan_frames_good_bad bf; -}; - -/*[register] RX_WATCHDOG_ERROR_FRAMES*/ -#define RX_WATCHDOG_ERROR_FRAMES -#define RX_WATCHDOG_ERROR_FRAMES_ADDRESS 0x1dc -#define RX_WATCHDOG_ERROR_FRAMES_NUM 2 -#define RX_WATCHDOG_ERROR_FRAMES_INC 0x100000 -#define RX_WATCHDOG_ERROR_FRAMES_DEFAULT 0x0 - -struct rx_watchdog_error_frames { - a_uint32_t rxwdogerr:32; -}; - -union rx_watchdog_error_frames_u { - a_uint32_t val; - struct rx_watchdog_error_frames bf; -}; - -/*[register] GMAC0_RX_RECEIVE_ERROR_FRAMES*/ -#define RX_RECEIVE_ERROR_FRAMES -#define RX_RECEIVE_ERROR_FRAMES_ADDRESS 0x1e0 -#define RX_RECEIVE_ERROR_FRAMES_NUM 2 -#define RX_RECEIVE_ERROR_FRAMES_INC 0x100000 -#define RX_RECEIVE_ERROR_FRAMES_DEFAULT 0x0 - -struct rx_receive_error_frames { - a_uint32_t rxrcverr:32; -}; - -union rx_receive_error_frames_u { - a_uint32_t val; - struct rx_receive_error_frames bf; -}; - -/*[register] RX_CONTROL_FRAMES_GOOD*/ -#define RX_CONTROL_FRAMES_GOOD -#define RX_CONTROL_FRAMES_GOOD_ADDRESS 0x1e4 -#define RX_CONTROL_FRAMES_GOOD_NUM 2 -#define RX_CONTROL_FRAMES_GOOD_INC 0x100000 -#define RX_CONTROL_FRAMES_GOOD_DEFAULT 0x0 - -struct rx_control_frames_good { - a_uint32_t rxctlg:32; -}; - -union rx_control_frames_good_u { - a_uint32_t val; - struct rx_control_frames_good bf; -}; -#endif diff --git a/feeds/ipq807x/qca-ssdk/src/include/hsl/mp/mp_portctrl.h b/feeds/ipq807x/qca-ssdk/src/include/hsl/mp/mp_portctrl.h deleted file mode 100755 index 32c95ca3d..000000000 --- a/feeds/ipq807x/qca-ssdk/src/include/hsl/mp/mp_portctrl.h +++ /dev/null @@ -1,113 +0,0 @@ -/* - * Copyright (c) 2020, The Linux Foundation. All rights reserved. - * - * Permission to use, copy, modify, and/or distribute this software for any - * purpose with or without fee is hereby granted, provided that the above - * copyright notice and this permission notice appear in all copies. - * - * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES - * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR - * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES - * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN - * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF - * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. - */ - -#ifndef MAPLE_PORTCTRL_H -#define MAPLE_PORTCTRL_H - -#define MAC_CONFIGURATION_MAX_ENTRY 2 -#define MAC_FRAME_FILTER_MAX_ENTRY 2 -#define MAC_FLOW_CTRL_MAX_ENTRY 2 -#define MAC_LPI_CTRL_STATUS_MAX_ENTRY 2 -#define MAC_LPI_TIMER_CTRL_MAX_ENTRY 2 -#define MAC_MAX_FRAME_CTRL_MAX_ENTRY 2 -#define MAC_OPERATION_MODE_CTRL_MAX_ENTRY 2 - -sw_error_t -mp_mac_configuration_get( - a_uint32_t dev_id, - a_uint32_t index, - union mac_configuration_u *value); - -sw_error_t -mp_mac_configuration_set( - a_uint32_t dev_id, - a_uint32_t index, - union mac_configuration_u *value); - - -sw_error_t -mp_mac_frame_filter_get( - a_uint32_t dev_id, - a_uint32_t index, - union mac_frame_filter_u *value); - -sw_error_t -mp_mac_frame_filter_set( - a_uint32_t dev_id, - a_uint32_t index, - union mac_frame_filter_u *value); - -sw_error_t -mp_mac_flowctrl_get( - a_uint32_t dev_id, - a_uint32_t index, - union mac_flow_ctrl_u *value); - -sw_error_t -mp_mac_flowctrl_set( - a_uint32_t dev_id, - a_uint32_t index, - union mac_flow_ctrl_u *value); - -sw_error_t -mp_mac_lpi_ctrl_status_get( - a_uint32_t dev_id, - a_uint32_t index, - union mac_lpi_ctrl_status_u *value); - -sw_error_t -mp_mac_lpi_ctrl_status_set( - a_uint32_t dev_id, - a_uint32_t index, - union mac_lpi_ctrl_status_u *value); - -sw_error_t -mp_mac_lpi_timer_ctrl_get( - a_uint32_t dev_id, - a_uint32_t index, - union mac_lpi_timer_ctrl_u *value); - -sw_error_t -mp_mac_lpi_timer_ctrl_set( - a_uint32_t dev_id, - a_uint32_t index, - union mac_lpi_timer_ctrl_u *value); - -sw_error_t -mp_mac_max_frame_ctrl_get( - a_uint32_t dev_id, - a_uint32_t index, - union mac_max_frame_ctrl_u *value); - -sw_error_t -mp_mac_max_frame_ctrl_set( - a_uint32_t dev_id, - a_uint32_t index, - union mac_max_frame_ctrl_u *value); - -sw_error_t -mp_mac_operation_mode_ctrl_get( - a_uint32_t dev_id, - a_uint32_t index, - union mac_operation_mode_ctrl_u *value); - -sw_error_t -mp_mac_operation_mode_ctrl_set( - a_uint32_t dev_id, - a_uint32_t index, - union mac_operation_mode_ctrl_u *value); -#endif - diff --git a/feeds/ipq807x/qca-ssdk/src/include/hsl/mp/mp_portctrl_reg.h b/feeds/ipq807x/qca-ssdk/src/include/hsl/mp/mp_portctrl_reg.h deleted file mode 100755 index 9ead6b6dc..000000000 --- a/feeds/ipq807x/qca-ssdk/src/include/hsl/mp/mp_portctrl_reg.h +++ /dev/null @@ -1,219 +0,0 @@ -/* - * Copyright (c) 2020, The Linux Foundation. All rights reserved. - * - * Permission to use, copy, modify, and/or distribute this software for any - * purpose with or without fee is hereby granted, provided that the above - * copyright notice and this permission notice appear in all copies. - * - * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES - * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR - * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES - * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN - * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF - * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. - */ - -#ifndef MAPLE_PORTCTRL_REG_H -#define MAPLE_PORTCTRL_REG_H - -/*[register] MAC_CONFIGURATION*/ -#define MAC_CONFIGURATION -#define MAC_CONFIGURATION_ADDRESS 0x0 -#define MAC_CONFIGURATION_NUM 2 -#define MAC_CONFIGURATION_INC 0x100000 -#define MAC_CONFIGURATION_DEFAULT 0x0 - -struct mac_configuration { - a_uint32_t preamble_length:2; - a_uint32_t rx_enable:1; - a_uint32_t tx_enable:1; - a_uint32_t deferral_check:1; - a_uint32_t back_off_limit:2; - a_uint32_t acs:1; - a_uint32_t link_status:1; - a_uint32_t disable_retry:1; - a_uint32_t checksum_offload:1; - a_uint32_t duplex:1; - a_uint32_t loopback:1; - a_uint32_t disable_receive_own:1; - a_uint32_t mii_speed:1; - a_uint32_t port_select:1; - a_uint32_t disable_carrier_sense:1; - a_uint32_t ipg:3; - a_uint32_t jumbo_frame_enable:1; - a_uint32_t frame_burst_enable:1; - a_uint32_t jabber_disable:1; - a_uint32_t watchdog_disable:1; - a_uint32_t tc:1; - a_uint32_t crc_strpping:1; - a_uint32_t sfterr:1; - a_uint32_t twokpe:1; - a_uint32_t sarc:3; - a_uint32_t reserved:1; - -}; - -union mac_configuration_u { - a_uint32_t val; - struct mac_configuration bf; -}; - -/*[register] MAC_FRAME_FILTER*/ -#define MAC_FRAME_FILTER -#define MAC_FRAME_FILTER_ADDRESS 0x4 -#define MAC_FRAME_FILTER_NUM 2 -#define MAC_FRAME_FILTER_INC 0x100000 -#define MAC_FRAME_FILTER_DEFAULT 0x0 - -struct mac_frame_filter { - a_uint32_t promiscuous_mode:1; - a_uint32_t hash_unicast:1; - a_uint32_t hash_multicast:1; - a_uint32_t da_inverse_filtering:1; - a_uint32_t pass_multicast:1; - a_uint32_t disable_broadcast:1; - a_uint32_t pass_control_frame:2; - a_uint32_t sa_inverse_filtering:1; - a_uint32_t source_addr_filter_enable:1; - a_uint32_t perfect_filter:1; - a_uint32_t reserved_0:5; - a_uint32_t vlan_tag_filter_enable:1; - a_uint32_t resereved_1:3; - a_uint32_t layer_3_4_filter_enable:1; - a_uint32_t drop_non_tcp_udp:1; - a_uint32_t reserved_2:9; - a_uint32_t receive_all:1; -}; - -union mac_frame_filter_u { - a_uint32_t val; - struct mac_frame_filter bf; -}; - -/*[register] MAC_FLOW_CTRL*/ -#define MAC_FLOW_CTRL -#define MAC_FLOW_CTRL_ADDRESS 0x18 -#define MAC_FLOW_CTRL_NUM 2 -#define MAC_FLOW_CTRL_INC 0x100000 -#define MAC_FLOW_CTRL_DEFAULT 0x0 - -struct mac_flow_ctrl { - a_uint32_t flowctrl_busy:1; - a_uint32_t flowctrl_tx_enable:1; - a_uint32_t flowctrl_rx_enable:1; - a_uint32_t unicast_pause_frame_detect:1; - a_uint32_t pause_low_threshold:2; - a_uint32_t reserved_0:1; - a_uint32_t disable_zero_quanta_pause:1; - a_uint32_t reserved_1:8; - a_uint32_t pause_time:16; -}; - -union mac_flow_ctrl_u { - a_uint32_t val; - struct mac_flow_ctrl bf; -}; - -/*[register] LPI_CONTROL_STATUS*/ -#define MAC_LPI_CTRL_STATUS -#define MAC_LPI_CTRL_STATUS_ADDRESS 0x30 -#define MAC_LPI_CTRL_STATUS_NUM 2 -#define MAC_LPI_CTRL_STATUS_INC 0x100000 -#define MAC_LPI_CTRL_STATUS_DEFAULT 0x0 - -struct mac_lpi_ctrl_status { - a_uint32_t tx_lpi_entry:1; - a_uint32_t tx_lpi_exit:1; - a_uint32_t rx_lpi_entry:1; - a_uint32_t rx_lpi_exit:1; - a_uint32_t reserved_0:4; - a_uint32_t tx_lpi_state:1; - a_uint32_t rx_lpi_state:1; - a_uint32_t reserved_1:6; - a_uint32_t lpi_enable:1; - a_uint32_t link_status:1; - a_uint32_t link_status_enable:1; - a_uint32_t lpi_tx_auto_enable:1; - a_uint32_t reserved_2:12; -}; - -union mac_lpi_ctrl_status_u { - a_uint32_t val; - struct mac_lpi_ctrl_status bf; -}; - -/*[register] LPI_TIMER_CONTROL*/ -#define MAC_LPI_TIMER_CTRL -#define MAC_LPI_TIMER_CTRL_ADDRESS 0x34 -#define MAC_LPI_TIMER_CTRL_NUM 2 -#define MAC_LPI_TIMER_CTRL_INC 0x100000 -#define MAC_LPI_TIMER_CTRL_DEFAULT 0x0 - -struct mac_lpi_timer_ctrl { - a_uint32_t lpi_tw_timer:16; - a_uint32_t lpi_ls_timer:10; - a_uint32_t reserved_0:6; -}; - -union mac_lpi_timer_ctrl_u { - a_uint32_t val; - struct mac_lpi_timer_ctrl bf; -}; - -/*[register] MAX_FRAME_CONTROL*/ -#define MAC_MAX_FRAME_CTRL -#define MAC_MAX_FRAME_CTRL_ADDRESS 0xDC -#define MAC_MAX_FRAME_CTRL_NUM 2 -#define MAC_MAX_FRAME_CTRL_INC 0x100000 -#define MAC_MAX_FRAME_CTRL_DEFAULT 0x0 - -struct mac_max_frame_ctrl { - a_uint32_t max_frame_ctrl:14; - a_uint32_t reserved_0:2; - a_uint32_t max_frame_ctrl_enable:1; -}; - -union mac_max_frame_ctrl_u { - a_uint32_t val; - struct mac_max_frame_ctrl bf; -}; - -/*[register] OPERATION_MODE*/ -#define MAC_OPERATION_MODE_CTRL -#define MAC_OPERATION_MODE_CTRL_ADDRESS 0x01018 -#define MAC_OPERATION_MODE_CTRL_NUM 2 -#define MAC_OPERATION_MODE_CTRL_INC 0x100000 -#define MAC_OPERATION_MODE_CTRL_DEFAULT 0x0 - -struct mac_operation_mode_ctrl { - a_uint32_t reserved_0:1; - a_uint32_t stop_receive:1; - a_uint32_t second_frame:1; - a_uint32_t receive_threshold_ctrl:2; - a_uint32_t drop_gaint_frame:1; - a_uint32_t forwad_good_undersize_frame:1; - a_uint32_t forward_error_frame:1; - a_uint32_t enable_hw_flowctrl:1; - a_uint32_t threshold_of_activating:2; - a_uint32_t threshold_of_deactivating:2; - a_uint32_t stop_transmission_command:1; - a_uint32_t transmit_threshold_ctrl:3; - a_uint32_t reserved_1:3; - a_uint32_t flush_transmit_fifo:1; - a_uint32_t transmit_store_and_foward:1; - a_uint32_t msb_threshold_of_deactivating:1; - a_uint32_t msb_threshold_of_activating:1; - a_uint32_t disable_flushing_receiving_frame:1; - a_uint32_t receive_store_and_foward:1; - a_uint32_t disable_dropping_checking_error_frame:1; - a_uint32_t reserved_2:5; -}; - -union mac_operation_mode_ctrl_u { - a_uint32_t val; - struct mac_operation_mode_ctrl bf; -}; - -#endif - diff --git a/feeds/ipq807x/qca-ssdk/src/include/hsl/mp/mp_uniphy.h b/feeds/ipq807x/qca-ssdk/src/include/hsl/mp/mp_uniphy.h deleted file mode 100755 index 5c3920c64..000000000 --- a/feeds/ipq807x/qca-ssdk/src/include/hsl/mp/mp_uniphy.h +++ /dev/null @@ -1,40 +0,0 @@ -/* - * Copyright (c) 2020, The Linux Foundation. All rights reserved. - * - * Permission to use, copy, modify, and/or distribute this software for any - * purpose with or without fee is hereby granted, provided that the above - * copyright notice and this permission notice appear in all copies. - * - * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES - * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR - * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES - * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN - * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF - * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. - */ - -/** - * @defgroup - * @{ - */ - -#ifndef _MP_UNIPHY_H_ -#define _MP_UNIPHY_H_ - -#define UNIPHY_CLK_DIV_25M 1 -#define UNIPHY_CLK_DIV_50M 0 -#define UNIPHY_CLK_DRV_1 1 - -sw_error_t -mp_uniphy_clock_output_control_get( - a_uint32_t dev_id, - a_uint32_t index, - union uniphy_clock_output_control_u *value); -sw_error_t -mp_uniphy_clock_output_control_set( - a_uint32_t dev_id, - a_uint32_t index, - union uniphy_clock_output_control_u *value); -#endif - diff --git a/feeds/ipq807x/qca-ssdk/src/include/hsl/mp/mp_uniphy_reg.h b/feeds/ipq807x/qca-ssdk/src/include/hsl/mp/mp_uniphy_reg.h deleted file mode 100755 index 8a509096e..000000000 --- a/feeds/ipq807x/qca-ssdk/src/include/hsl/mp/mp_uniphy_reg.h +++ /dev/null @@ -1,60 +0,0 @@ -/* - * Copyright (c) 2020, The Linux Foundation. All rights reserved. - * - * Permission to use, copy, modify, and/or distribute this software for any - * purpose with or without fee is hereby granted, provided that the above - * copyright notice and this permission notice appear in all copies. - * - * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES - * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR - * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES - * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN - * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF - * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. - */ - -/** - * @defgroup - * @{ - */ - -#ifndef MP_UNIPHY_REG_H -#define MP_UNIPHY_REG_H - -#define UNIPHY_CLOCK_OUTPUT_CONTROL_MAX_ENTRY 1 -/*[register] UNIPHY_ALLREG_DEC_REFCLKOUTPUTCONTROLREGISTERS*/ -#define UNIPHY_CLOCK_OUTPUT_CONTROL -#define UNIPHY_CLOCK_OUTPUT_CONTROL_ADDRESS 0x74 -#define UNIPHY_CLOCK_OUTPUT_CONTROL_NUM 0x1 -#define UNIPHY_CLOCK_OUTPUT_CONTROL_INC 0x1 -#define UNIPHY_CLOCK_OUTPUT_CONTROL_TYPE REG_TYPE_RW -#define UNIPHY_CLOCK_OUTPUT_CONTROL_DEFAULT 0x5 - /*[field] MMD1_REG_REFCLK_OUTPUT_EN*/ - #define MMD1_REG_REFCLK_OUTPUT_EN - #define MMD1_REG_REFCLK_OUTPUT_EN_OFFSET 0 - #define MMD1_REG_REFCLK_OUTPUT_EN_LEN 1 - #define MMD1_REG_REFCLK_OUTPUT_EN_DEFAULT 0x1 - /*[field] MMD1_REG_REFCLK_OUTPUT_DIV*/ - #define MMD1_REG_REFCLK_OUTPUT_DIV - #define MMD1_REG_REFCLK_OUTPUT_DIV_OFFSET 1 - #define MMD1_REG_REFCLK_OUTPUT_DIV_LEN 1 - #define MMD1_REG_REFCLK_OUTPUT_DIV_DEFAULT 0x0 - /*[field] MMD1_REG_REFCLK_OUTPUT_DRV*/ - #define MMD1_REG_REFCLK_OUTPUT_DRV - #define MMD1_REG_REFCLK_OUTPUT_DRV_OFFSET 2 - #define MMD1_REG_REFCLK_OUTPUT_DRV_LEN 2 - #define MMD1_REG_REFCLK_OUTPUT_DRV_DEFAULT 0x1 - -struct uniphy_clock_output_control { - a_uint32_t ref_clk_output_en:1; - a_uint32_t ref_clk_output_div:1; - a_uint32_t ref_clk_output_drv:2; - a_uint32_t _reserved1:28; -}; - -union uniphy_clock_output_control_u { - a_uint32_t val; - struct uniphy_clock_output_control bf; -}; -#endif diff --git a/feeds/ipq807x/qca-ssdk/src/include/hsl/phy/aquantia_phy.h b/feeds/ipq807x/qca-ssdk/src/include/hsl/phy/aquantia_phy.h deleted file mode 100755 index 71930d1de..000000000 --- a/feeds/ipq807x/qca-ssdk/src/include/hsl/phy/aquantia_phy.h +++ /dev/null @@ -1,394 +0,0 @@ -/* - * Copyright (c) 2017, The Linux Foundation. All rights reserved. - * Permission to use, copy, modify, and/or distribute this software for - * any purpose with or without fee is hereby granted, provided that the - * above copyright notice and this permission notice appear in all copies. - * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES - * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR - * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES - * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN - * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT - * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. - */ - -#ifndef _AQUANTIA_PHY_H_ -#define _AQUANTIA_PHY_H_ - -#ifdef __cplusplus -extern "C" -{ -#endif /* __cplusplus */ -#define PHY_ID_AQ1202 0x03a1b445 -#define PHY_ID_AQ2104 0x03a1b460 -#define PHY_ID_AQR105 0x03a1b4a2 -#define PHY_ID_AQR405 0x03a1b4b0 -#define PHY_ID_AQR107 0x03a1b4e1 - -#define AQUANTIA_MII_ADDR_C45 (1<<30) -#define AQUANTIA_REG_ADDRESS(dev_ad, reg_num) (AQUANTIA_MII_ADDR_C45 |\ - ((dev_ad & 0x1f) << 16) | (reg_num & 0xFFFF)) -#define AQUANTIA_MMD_AUTONEG 0x7 -#define AQUANTIA_MMD_PHY_XS_REGISTERS 4 -#define AQUANTIA_MMD_GLOBAL_REGISTERS 0x1E -#define AQUANTIA_MMD_GBE_STANDARD_REGISTERS 0x1D -#define AQUANTIA_MMD_PCS_REGISTERS 0x3 - /* PHY Registers */ -#define AQUANTIA_GLOBAL_STANDARD_CONTROL1 0 -#define AQUANTIA_EEE_ADVERTISTMENT_REGISTER 0x3C -#define AQUANTIA_EEE_ADVERTISTMENT_REGISTER1 0x3E -#define AQUANTIA_EEE_PARTNER_ADVERTISTMENT_REGISTER 0x3D -#define AQUANTIA_EEE_PARTNER_ADVERTISTMENT_REGISTER1 0x3F -#define AQUANTIA_EEE_CAPABILITY_REGISTER 0x14 -#define AQUANTIA_EEE_CAPABILITY_REGISTER1 0x15 - -#define AQUANTIA_REG_AUTONEG_VENDOR_STATUS 0xC800 -#define AQUANTIA_AUTONEG_STANDARD_STATUS1 0x1 -#define AQUANTIA_AUTONEG_STANDARD_CONTROL1 0 -#define AQUANTIA_AUTONEG_TRANSMIT_VENDOR_INTR_MASK 0xD401 -#define AQUANTIA_GLOBAL_INTR_STANDARD_MASK 0xff00 -#define AQUANTIA_GLOBAL_INTR_VENDOR_MASK 0xff01 -#define AQUANTIA_PHY_XS_USX_TRANSMIT 0xc441 -#define AQUANTIA_PHY_INTR_STATUS 19 -#define AQUANTIA_RESERVED_VENDOR_PROVISIONING1 0xC410 -#define AQUANTIA_RESERVED_VENDOR_STATUS1 0xC810 -#define AQUANTIA_GLOBAL_RESERVED_PROVISIONING 0xC47a -#define AQUANTIA_GLOBAL_RESERVED_PROVISIONING6 0xC475 -#define AQUANTIA_PHY_XS_TRANAMIT_RESERVED_VENDOR_PROVISION5 0xC444 -#define AQUANTIA_CHIP_WIDE_VENDORT_INTERRUPT_FLAGS 0xFC01 -#define AQUANTIA_AUTONEG_ADVERTISEMENT_REGISTER 0x10 -#define AQUANTIA_AUTONEG_VENDOR_PROVISION1 0xC400 -#define AQUANTIA_AUTONEG_10GBASE_T_CONTROL_REGISTER 0x20 -#define AQUANTIA_AUTONEG_LINK_PARTNER_ABILITY 0x13 -#define AQUANTIA_AUTONEG_LINK_PARTNER_5G_ABILITY 0xE820 -#define AQUANTIA_AUTONEG_LINK_PARTNER_10G_ABILITY 0x21 - -#define AQUANTIA_GLOBAL_CDT_CONTROL 0xC470 -#define AQUANTIA_GLOBAL_GENERAL_STATUS 0xC831 -#define AQUANTIA_NORMAL_CABLE_DIAGNOSTICS 0x10 -#define AQUANTIA_CABLE_DIAGNOSTICS_STATUS 0x8000 -/*AQUANTIA PHY LINE SIDE PACKETS COUNTER REGISTER*/ -#define AQUANTIA_LINE_SIDE_TRANSMIT_GOOD_FRAME_COUNTER2 0xc821 -#define AQUANTIA_LINE_SIDE_TRANSMIT_GOOD_FRAME_COUNTER1 0xc820 -#define AQUANTIA_LINE_SIDE_TRANSMIT_ERROR_FRAME_COUNTER2 0xc823 -#define AQUANTIA_LINE_SIDE_TRANSMIT_ERROR_FRAME_COUNTER1 0xc822 - -#define AQUANTIA_LINE_SIDE_RECEIVE_GOOD_FRAME_COUNTER2 0xe813 -#define AQUANTIA_LINE_SIDE_RECEIVE_GOOD_FRAME_COUNTER1 0xe812 -#define AQUANTIA_LINE_SIDE_RECEIVE_ERROR_FRAME_COUNTER2 0xe815 -#define AQUANTIA_LINE_SIDE_RECEIVE_ERROR_FRAME_COUNTER1 0xe814 - -/*AQUANTIA PHY SYSTEM SIDE PACKETS COUNTER REGISTER*/ -#define AQUANTIA_SYSTEM_SIDE_TRANSMIT_GOOD_FRAME_COUNTER2 0xc861 -#define AQUANTIA_SYSTEM_SIDE_TRANSMIT_GOOD_FRAME_COUNTER1 0xc860 -#define AQUANTIA_SYSTEM_SIDE_TRANSMIT_ERROR_FRAME_COUNTER2 0xc863 -#define AQUANTIA_SYSTEM_SIDE_TRANSMIT_ERROR_FRAME_COUNTER1 0xc862 - -#define AQUANTIA_SYSTEM_SIDE_RECEIVE_GOOD_FRAME_COUNTER2 0xe861 -#define AQUANTIA_SYSTEM_SIDE_RECEIVE_GOOD_FRAME_COUNTER1 0xe860 -#define AQUANTIA_SYSTEM_SIDE_RECEIVE_ERROR_FRAME_COUNTER2 0xe863 -#define AQUANTIA_SYSTEM_SIDE_RECEIVE_ERROR_FRAME_COUNTER1 0xe862 - -#define AQUANTIA_CABLE_DIAGNOSTIC_STATUS1 0xC800 -#define AQUANTIA_CABLE_DIAGNOSTIC_STATUS_PAIRA 0x7000/*0XC800, BITC:E*/ -#define AQUANTIA_CABLE_DIAGNOSTIC_STATUS_PAIRB 0x0700/*0XC800, BITA:8*/ -#define AQUANTIA_CABLE_DIAGNOSTIC_STATUS_PAIRC 0x0070/*0XC800, BIT6:4*/ -#define AQUANTIA_CABLE_DIAGNOSTIC_STATUS_PAIRD 0x0007/*0XC800, BIT2:0*/ - - -#define AQUANTIA_CABLE_DIAGNOSTIC_STATUS2 0xC801 -#define AQUANTIA_CABLE_DIAGNOSTIC_STATUS4 0xC803 -#define AQUANTIA_CABLE_DIAGNOSTIC_STATUS6 0xC805 -#define AQUANTIA_CABLE_DIAGNOSTIC_STATUS8 0xC807 -#define AQUANTIA_ACT_LED_STATUS 0xc430 -#define AQUANTIA_LINK_LED_STATUS 0xc431 -#define AQUANTIA_ACT_LED_VALUE 0xc0ef -#define AQUANTIA_LINK_LED_VALUE 0xc0e0 - - -#define AQUANTIA_PHY_ID1 0x2 -#define AQUANTIA_PHY_ID2 0x3 -#define AQUANTIA_MAGIC_FRAME_MAC0 0xC339 -#define AQUANTIA_MAGIC_FRAME_MAC1 0xC33a -#define AQUANTIA_MAGIC_FRAME_MAC2 0xC33b -#define AQUANTIA_MAGIC_ENGINE_REGISTER1 0xC355 -#define AQUANTIA_MAGIC_ENGINE_REGISTER2 0xC356 - -#define AQUANTIA_GLOBAL_SYS_CONFIG_FOR_100M 0x31B -#define AQUANTIA_GLOBAL_SYS_CONFIG_FOR_1000M 0x31C -#define AQUANTIA_GLOBAL_SYS_CONFIG_FOR_2500M 0x31D -#define AQUANTIA_GLOBAL_SYS_CONFIG_FOR_5000M 0x31E -#define AQUANTIA_GLOBAL_SYS_CONFIG_FOR_10000M 0x31F - - - /* PHY Registers Field */ -#define AQUANTIA_SERDES_MODE_XFI 0 -#define AQUANTIA_SERDES_MODE_SGMII 0x3 -#define AQUANTIA_SERDES_MODE_OCSGMII 0X4 - -#define AQUANTIA_MAGIC_PACKETS_ENABLE 0x0001 -#define AQUANTIA_PHY_MDIX_CONTRO_BIT 3 -#define AQUANTIA_PHY_MDIX_AUTO 0 -#define AQUANTIA_PHY_MDI 1 -#define AQUANTIA_PHY_MDIX 2 -#define AQUANTIA_PHY_MDIX_STATUS 0x0100 -#define AQUANTIA_PHY_WOL_ENABLE 0x0040 -#define AQUANTIA_PHY_REMOTE_LOOPBACK 0x1800 -#define AQUANTIA_COMMON_CTRL 0x1040 -#define AQUANTIA_INTERNAL_LOOPBACK 0x4800 -#define AQUANTIA_100M_LOOPBACK 0x0001 -#define AQUANTIA_1000M_LOOPBACK 0x0002 -#define AQUANTIA_10000M_LOOPBACK 0x0003 -#define AQUANTIA_2500M_LOOPBACK 0x0004 -#define AQUANTIA_5000M_LOOPBACK 0x0005 -#define AQUANTIA_POWER_DOWN 0x0800 -#define AQUANTIA_ALL_SPEED_LOOPBACK (AQUANTIA_100M_LOOPBACK |\ - AQUANTIA_1000M_LOOPBACK | AQUANTIA_1000M_LOOPBACK |AQUANTIA_2500M_LOOPBACK |\ - AQUANTIA_5000M_LOOPBACK | AQUANTIA_10000M_LOOPBACK) - -#define AQUANTIA_POWER_SAVE 0x0004 -#define AQUANTIA_STATUS_LINK 0x0004 -#define AQUANTIA_EEE_ADV_1000M 0x0004 -#define AQUANTIA_EEE_ADV_2500M 0x0001 -#define AQUANTIA_EEE_ADV_5000M 0x0002 -#define AQUANTIA_EEE_ADV_10000M 0x0008 -#define AQUANTIA_EEE_PARTNER_ADV_1000M 0x0004 -#define AQUANTIA_EEE_PARTNER_ADV_2500M 0x0001 -#define AQUANTIA_EEE_PARTNER_ADV_5000M 0x0002 -#define AQUANTIA_EEE_PARTNER_ADV_10000M 0x0008 -#define AQUANTIA_EEE_CAPABILITY_1000M 0x0004 -#define AQUANTIA_EEE_CAPABILITY_2500M 0x0001 -#define AQUANTIA_EEE_CAPABILITY_5000M 0x0002 -#define AQUANTIA_EEE_CAPABILITY_10000M 0x0008 - -#define AQUANTIA_PHY_USX_AUTONEG_ENABLE 0x0008 - -#define AQUANTIA_PHY_RX_FLOWCTRL_STATUS 0x0002 -#define AQUANTIA_PHY_TX_FLOWCTRL_STATUS 0x0001 - /* FDX =1, half duplex =0 */ -#define AQUANTIA_CTRL_FULL_DUPLEX 0x0100 - - /* Restart auto negotiation */ -#define AQUANTIA_CTRL_RESTART_AUTONEGOTIATION 0x0200 - - /* Power down */ -#define AQUANTIA_CTRL_POWER_DOWN 0x0800 - - /* Auto Neg Enable */ -#define AQUANTIA_CTRL_AUTONEGOTIATION_ENABLE 0x1000 - - /* Local Loopback Enable */ -#define AQUANTIA_LOCAL_LOOPBACK_ENABLE 0x4000 - - /* 0 = normal, 1 = loopback */ -#define AQUANTIA_CTRL_SOFTWARE_RESET 0x8000 - -#define AQUANTIA_RESET_DONE(phy_control) \ - (((phy_control) & (AQUANTIA_CTRL_SOFTWARE_RESET)) == 0) - - /* Auto Neg Complete */ -#define AQUANTIA_STATUS_AUTO_NEG_DONE 0x0020 - -#define AQUANTIA_AUTONEG_DONE(ip_phy_status) \ - (((ip_phy_status) & (AQUANTIA_STATUS_AUTO_NEG_DONE)) == \ - (AQUANTIA_STATUS_AUTO_NEG_DONE)) - -/*AQUANTIA interrupt flag */ -#define AQUANTIA_INTR_DUPLEX_CHANGE 0x2000 -#define AQUANTIA_INTR_LINK_STATUS_CHANGE 0x0001 -#define AQUANTIA_ALL_VENDOR_ALARMS_INTR_MASK 0x0001 -#define AQUANTIA_AUTO_AND_ALARMS_INTR_MASK 0x1001 - - /* 10T Half Duplex Capable */ -#define AQUANTIA_ADVERTISE_10HALF 0x0020 - - /* 10T Full Duplex Capable */ -#define AQUANTIA_ADVERTISE_10FULL 0x0040 - - /* 100TX Half Duplex Capable */ -#define AQUANTIA_ADVERTISE_100HALF 0x0080 - - /* 100TX Full Duplex Capable */ -#define AQUANTIA_ADVERTISE_100FULL 0x0100 - - /* Pause operation desired */ -#define AQUANTIA_ADVERTISE_PAUSE 0x0400 - - /* Asymmetric Pause Direction bit */ -#define AQUANTIA_ADVERTISE_ASYM_PAUSE 0x0800 - - /* Remote Fault detected */ -#define AQUANTIA_ADVERTISE_REMOTE_FAULT 0x2000 - - /* Next Page ability supported */ -#define AQUANTIA_ADVERTISE_NEXT_PAGE 0x8000 - - /* 1000TX Half Duplex Capable */ -#define AQUANTIA_ADVERTISE_1000HALF 0x4000 - - /* 1000TX Full Duplex Capable */ -#define AQUANTIA_ADVERTISE_1000FULL 0x8000 - - /* 2500TX Full Duplex Capable */ -#define AQUANTIA_ADVERTISE_2500FULL 0x0400 -#define AQUANTIA_ADVERTISE_8023BZ_2500FULL 0x80 - - /* 10000TX Full Duplex Capable */ -#define AQUANTIA_ADVERTISE_10000FULL 0x1000 - - /* 5000TX Full Duplex Capable */ -#define AQUANTIA_ADVERTISE_5000FULL 0x0800 -#define AQUANTIA_ADVERTISE_8023BZ_5000FULL 0x100 - -#define AQUANTIA_ADVERTISE_ALL \ - (AQUANTIA_ADVERTISE_10HALF | AQUANTIA_ADVERTISE_10FULL | \ - AQUANTIA_ADVERTISE_100HALF | AQUANTIA_ADVERTISE_100FULL | \ - AQUANTIA_ADVERTISE_1000HALF |AQUANTIA_ADVERTISE_1000FULL |\ - AQUANTIA_ADVERTISE_10000FULL | AQUANTIA_ADVERTISE_2500FULL |\ - AQUANTIA_ADVERTISE_5000FULL) - -#define AQUANTIA_ADVERTISE_MEGA_ALL \ - (AQUANTIA_ADVERTISE_10HALF | AQUANTIA_ADVERTISE_10FULL | \ - AQUANTIA_ADVERTISE_100HALF | AQUANTIA_ADVERTISE_100FULL) - -#define AQUANTIA_ADVERTISE_GIGA_ALL \ - (AQUANTIA_ADVERTISE_1000HALF |AQUANTIA_ADVERTISE_1000FULL |\ - AQUANTIA_ADVERTISE_2500FULL | AQUANTIA_ADVERTISE_5000FULL) - - #define AQUANTIA_ADVERTISE_GIGA_PLUS_ALL \ - (AQUANTIA_ADVERTISE_10000FULL | AQUANTIA_ADVERTISE_8023BZ_2500FULL|\ - AQUANTIA_ADVERTISE_8023BZ_5000FULL) - - -#define AQUANTIA_BX_ADVERTISE_1000FULL 0x0020 -#define AQUANTIA_BX_ADVERTISE_1000HALF 0x0040 -#define AQUANTIA_BX_ADVERTISE_PAUSE 0x0080 -#define AQUANTIA_BX_ADVERTISE_ASYM_PAUSE 0x0100 - -#define AQUANTIA_BX_ADVERTISE_ALL \ - (AQUANTIA_BX_ADVERTISE_ASYM_PAUSE | AQUANTIA_BX_ADVERTISE_PAUSE | \ - AQUANTIA_BX_ADVERTISE_1000HALF | AQUANTIA_BX_ADVERTISE_1000FULL) - - /* Link Partner ability offset:5 */ - /* Same as advertise selector */ -#define AQUANTIA_LINK_SLCT 0x001f - - /* Can do 10mbps half-duplex */ -#define AQUANTIA_LINK_10BASETX_HALF_DUPLEX 0x0020 - - /* Can do 10mbps full-duplex */ -#define AQUANTIA_LINK_10BASETX_FULL_DUPLEX 0x0040 - - /* Can do 100mbps half-duplex */ -#define AQUANTIA_LINK_100BASETX_HALF_DUPLEX 0x0080 -#define AQUANTIA_LINK_100BASETX_FULL_DUPLEX 0x0100 -/*Can do 1G*/ - -#define AQUANTIA_LINK_1000BASETX_FULL_DUPLEX 0x8000 - /*Can do 5G*/ -#define AQUANTIA_LINK_5000BASETX_FULL_DUPLEX 0x0800 -/*Can do 2.5G*/ -#define AQUANTIA_LINK_2500BASETX_FULL_DUPLEX 0x0400 -/*Can do 10G*/ -#define AQUANTIA_LINK_10000BASETX_FULL_DUPLEX 0x1 - - - - /* 1=Duplex 0=Half Duplex */ -#define AQUANTIA_STATUS_FULL_DUPLEX 0x0001 - - /* Speed, bits 1 : 3*/ -#define AQUANTIA_STATUS_SPEED 0xC000 -#define AQUANTIA_STATUS_SPEED_MASK 0x000E - /* 000=10Mbs */ -#define AQUANTIA_STATUS_SPEED_10MBS 0x0000 - /* 001=100Mbs */ -#define AQUANTIA_STATUS_SPEED_100MBS 0x0001 - /* 010=1000Mbs */ -#define AQUANTIA_STATUS_SPEED_1000MBS 0x0002 - /* 011=10000Mbs */ -#define AQUANTIA_STATUS_SPEED_10000MBS 0x0003 - /* 100=2500Mbs */ -#define AQUANTIA_STATUS_SPEED_2500MBS 0x0004 - /* 101=5000Mbs */ -#define AQUANTIA_STATUS_SPEED_5000MBS 0x0005 - -#define RUN_CDT 0x8000 -#define CABLE_LENGTH_UNIT 0x0400 -#define AQUANTIA_PHY_CDT_MODE0 0 -#define AQUANTIA_PHY_CDT_MODE1 1 -#define AQUANTIA_PHY_CDT_MODE2 2 - -/** Phy pages */ - typedef enum - { - AQUANTIA_PHY_SGBX_PAGES = 0, - /**< sgbx pages */ - AQUANTIA_PHY_COPPER_PAGES = 1 - /**< copper pages */ - } AQUANTIA_PHY_reg_pages_t; -#ifndef IN_PORTCONTROL_MINI -sw_error_t - aquantia_phy_set_powersave (a_uint32_t dev_id, a_uint32_t phy_id, - a_bool_t enable); - -sw_error_t - aquantia_phy_get_powersave (a_uint32_t dev_id, a_uint32_t phy_id, - a_bool_t * enable); - -sw_error_t - aquantia_phy_cdt (a_uint32_t dev_id, a_uint32_t phy_id, - a_uint32_t mdi_pair, - fal_cable_status_t * cable_status, - a_uint32_t * cable_len); -#endif -sw_error_t - aquantia_phy_set_duplex (a_uint32_t dev_id, a_uint32_t phy_id, - fal_port_duplex_t duplex); - -sw_error_t - aquantia_phy_get_duplex (a_uint32_t dev_id, a_uint32_t phy_id, - fal_port_duplex_t * duplex); - -sw_error_t - aquantia_phy_set_speed (a_uint32_t dev_id, a_uint32_t phy_id, - fal_port_speed_t speed); - -sw_error_t -aquantia_phy_get_speed (a_uint32_t dev_id, a_uint32_t phy_id, - fal_port_speed_t * speed); - -sw_error_t - aquantia_phy_restart_autoneg (a_uint32_t dev_id, a_uint32_t phy_id); - -sw_error_t - aquantia_phy_enable_autoneg (a_uint32_t dev_id, a_uint32_t phy_id); - -a_bool_t - aquantia_phy_get_link_status (a_uint32_t dev_id, a_uint32_t phy_id); - -sw_error_t - aquantia_phy_set_autoneg_adv (a_uint32_t dev_id, a_uint32_t phy_id, - a_uint32_t autoneg); - -sw_error_t - aquantia_phy_get_autoneg_adv (a_uint32_t dev_id, a_uint32_t phy_id, - a_uint32_t * autoneg); - -a_bool_t - aquantia_phy_autoneg_status (a_uint32_t dev_id, a_uint32_t phy_id); -#ifndef IN_PORTCONTROL_MINI -sw_error_t - aquantia_phy_intr_mask_set (a_uint32_t dev_id, a_uint32_t phy_id, - a_uint32_t intr_mask_flag); - -sw_error_t - aquantia_phy_intr_mask_get (a_uint32_t dev_id, a_uint32_t phy_id, - a_uint32_t * intr_mask_flag); -#endif -int aquantia_phy_init(a_uint32_t dev_id, a_uint32_t port_bmp); - -#ifdef __cplusplus -} -#endif /* __cplusplus */ -#endif /* _AQUANTIA_PHY_H_ */ diff --git a/feeds/ipq807x/qca-ssdk/src/include/hsl/phy/f1_phy.h b/feeds/ipq807x/qca-ssdk/src/include/hsl/phy/f1_phy.h deleted file mode 100755 index b3f7ed2fe..000000000 --- a/feeds/ipq807x/qca-ssdk/src/include/hsl/phy/f1_phy.h +++ /dev/null @@ -1,479 +0,0 @@ -/* - * Copyright (c) 2012, 2015, 2017-2018, The Linux Foundation. All rights reserved. - * Permission to use, copy, modify, and/or distribute this software for - * any purpose with or without fee is hereby granted, provided that the - * above copyright notice and this permission notice appear in all copies. - * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES - * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR - * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES - * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN - * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT - * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. - */ - - - -#ifndef _F1_PHY_H_ -#define _F1_PHY_H_ - -#ifdef __cplusplus -extern "C" { -#endif /* __cplusplus */ - - /* PHY Registers */ -#define F1_PHY_CONTROL 0 -#define F1_PHY_STATUS 1 -#define F1_PHY_ID1 2 -#define F1_PHY_ID2 3 -#define F1_AUTONEG_ADVERT 4 -#define F1_LINK_PARTNER_ABILITY 5 -#define F1_AUTONEG_EXPANSION 6 -#define F1_NEXT_PAGE_TRANSMIT 7 -#define F1_LINK_PARTNER_NEXT_PAGE 8 -#define F1_1000BASET_CONTROL 9 -#define F1_1000BASET_STATUS 10 -#define F1_MMD_CTRL_REG 13 -#define F1_MMD_DATA_REG 14 -#define F1_EXTENDED_STATUS 15 -#define F1_PHY_SPEC_CONTROL 16 -#define F1_PHY_SPEC_STATUS 17 -#define F1_PHY_INTR_MASK 18 -#define F1_PHY_INTR_STATUS 19 -#define F1_PHY_CDT_CONTROL 22 -#define F1_PHY_CDT_STATUS 28 -#define F1_DEBUG_PORT_ADDRESS 29 -#define F1_DEBUG_PORT_DATA 30 -#define F1_PHY_8023AZ_EEE_CTRL 0x3c -#define F1_PHY_MMD7_NUM 7 -#define F1_PHY_AZ_ENABLE 0x6 - - /*debug port*/ -#define F1_DEBUG_PORT_RGMII_MODE 18 -#define F1_DEBUG_PORT_RGMII_MODE_EN 0x0008 - -#define F1_DEBUG_PORT_RX_DELAY 0 -#define F1_DEBUG_PORT_RX_DELAY_EN 0x8000 - -#define F1_DEBUG_PORT_TX_DELAY 5 -#define F1_DEBUG_PORT_TX_DELAY_EN 0x0100 - - /* PHY Registers Field*/ - - /* Control Register fields offset:0*/ - /* bits 6,13: 10=1000, 01=100, 00=10 */ -#define F1_CTRL_SPEED_MSB 0x0040 - - /* Collision test enable */ -#define F1_CTRL_COLL_TEST_ENABLE 0x0080 - - /* FDX =1, half duplex =0 */ -#define F1_CTRL_FULL_DUPLEX 0x0100 - - /* Restart auto negotiation */ -#define F1_CTRL_RESTART_AUTONEGOTIATION 0x0200 - - /* Isolate PHY from MII */ -#define F1_CTRL_ISOLATE 0x0400 - - /* Power down */ -#define F1_CTRL_POWER_DOWN 0x0800 - - /* Auto Neg Enable */ -#define F1_CTRL_AUTONEGOTIATION_ENABLE 0x1000 - - /* bits 6,13: 10=1000, 01=100, 00=10 */ -#define F1_CTRL_SPEED_LSB 0x2000 - - /* 0 = normal, 1 = loopback */ -#define F1_LOCAL_LOOPBACK_ENABLE 0x4000 -#define F1_COMMON_CTRL 0x1040 -#define F1_10M_LOOPBACK 0x4100 -#define F1_100M_LOOPBACK 0x6100 -#define F1_1000M_LOOPBACK 0x4140 - -#define F1_PHY_MMD3_NUM 3 -#define F1_PHY_MMD3_ADDR_REMOTE_LOOPBACK_CTRL 0x805a -#define F1_PHY_REMOTE_LOOPBACK_ENABLE 0x0001 -#define F1_CTRL_SOFTWARE_RESET 0x8000 - -#define F1_CTRL_SPEED_MASK 0x2040 -#define F1_CTRL_SPEED_1000 0x0040 -#define F1_CTRL_SPEED_100 0x2000 -#define F1_CTRL_SPEED_10 0x0000 - -#define F1_RESET_DONE(phy_control) \ - (((phy_control) & (F1_CTRL_SOFTWARE_RESET)) == 0) - - /* Status Register fields offset:1*/ - /* Extended register capabilities */ -#define F1_STATUS_EXTENDED_CAPS 0x0001 - - /* Jabber Detected */ -#define F1_STATUS_JABBER_DETECT 0x0002 - - /* Link Status 1 = link */ -#define F1_STATUS_LINK_STATUS_UP 0x0004 - - /* Auto Neg Capable */ -#define F1_STATUS_AUTONEG_CAPS 0x0008 - - /* Remote Fault Detect */ -#define F1_STATUS_REMOTE_FAULT 0x0010 - - /* Auto Neg Complete */ -#define F1_STATUS_AUTO_NEG_DONE 0x0020 - - /* Preamble may be suppressed */ -#define F1_STATUS_PREAMBLE_SUPPRESS 0x0040 - - /* Ext. status info in Reg 0x0F */ -#define F1_STATUS_EXTENDED_STATUS 0x0100 - - /* 100T2 Half Duplex Capable */ -#define F1_STATUS_100T2_HD_CAPS 0x0200 - - /* 100T2 Full Duplex Capable */ -#define F1_STATUS_100T2_FD_CAPS 0x0400 - - /* 10T Half Duplex Capable */ -#define F1_STATUS_10T_HD_CAPS 0x0800 - - /* 10T Full Duplex Capable */ -#define F1_STATUS_10T_FD_CAPS 0x1000 - - /* 100X Half Duplex Capable */ -#define F1_STATUS_100X_HD_CAPS 0x2000 - - /* 100X Full Duplex Capable */ -#define F1_STATUS_100X_FD_CAPS 0x4000 - - /* 100T4 Capable */ -#define F1_STATUS_100T4_CAPS 0x8000 - - /* extended status register capabilities */ - -#define F1_STATUS_1000T_HD_CAPS 0x1000 - -#define F1_STATUS_1000T_FD_CAPS 0x2000 - -#define F1_STATUS_1000X_HD_CAPS 0x4000 - -#define F1_STATUS_1000X_FD_CAPS 0x8000 - -#define F1_AUTONEG_DONE(ip_phy_status) \ - (((ip_phy_status) & (F1_STATUS_AUTO_NEG_DONE)) == \ - (F1_STATUS_AUTO_NEG_DONE)) - - /* PHY identifier1 offset:2*/ -//Organizationally Unique Identifier bits 3:18 - - /* PHY identifier2 offset:3*/ -//Organizationally Unique Identifier bits 19:24 - - /* Auto-Negotiation Advertisement register. offset:4*/ - /* indicates IEEE 802.3 CSMA/CD */ -#define F1_ADVERTISE_SELECTOR_FIELD 0x0001 - - /* 10T Half Duplex Capable */ -#define F1_ADVERTISE_10HALF 0x0020 - - /* 10T Full Duplex Capable */ -#define F1_ADVERTISE_10FULL 0x0040 - - /* 100TX Half Duplex Capable */ -#define F1_ADVERTISE_100HALF 0x0080 - - /* 100TX Full Duplex Capable */ -#define F1_ADVERTISE_100FULL 0x0100 - - /* 100T4 Capable */ -#define F1_ADVERTISE_100T4 0x0200 - - /* Pause operation desired */ -#define F1_ADVERTISE_PAUSE 0x0400 - - /* Asymmetric Pause Direction bit */ -#define F1_ADVERTISE_ASYM_PAUSE 0x0800 - - /* Remote Fault detected */ -#define F1_ADVERTISE_REMOTE_FAULT 0x2000 - - /* Next Page ability supported */ -#define F1_ADVERTISE_NEXT_PAGE 0x8000 - - /* 100TX Half Duplex Capable */ -#define F1_ADVERTISE_1000HALF 0x0100 - - /* 100TX Full Duplex Capable */ -#define F1_ADVERTISE_1000FULL 0x0200 - -#define F1_ADVERTISE_ALL \ - (F1_ADVERTISE_10HALF | F1_ADVERTISE_10FULL | \ - F1_ADVERTISE_100HALF | F1_ADVERTISE_100FULL | \ - F1_ADVERTISE_1000FULL) - -#define F1_ADVERTISE_MEGA_ALL \ - (F1_ADVERTISE_10HALF | F1_ADVERTISE_10FULL | \ - F1_ADVERTISE_100HALF | F1_ADVERTISE_100FULL) - - /* Link Partner ability offset:5*/ - /* Same as advertise selector */ -#define F1_LINK_SLCT 0x001f - - /* Can do 10mbps half-duplex */ -#define F1_LINK_10BASETX_HALF_DUPLEX 0x0020 - - /* Can do 10mbps full-duplex */ -#define F1_LINK_10BASETX_FULL_DUPLEX 0x0040 - - /* Can do 100mbps half-duplex */ -#define F1_LINK_100BASETX_HALF_DUPLEX 0x0080 - - /* Can do 100mbps full-duplex */ -#define F1_LINK_100BASETX_FULL_DUPLEX 0x0100 - - /* Can do 1000mbps full-duplex */ -#define F1_LINK_1000BASETX_FULL_DUPLEX 0x0800 - - /* Can do 1000mbps half-duplex */ -#define F1_LINK_1000BASETX_HALF_DUPLEX 0x0400 - - /* 100BASE-T4 */ -#define F1_LINK_100BASE4 0x0200 - - /* PAUSE */ -#define F1_LINK_PAUSE 0x0400 - - /* Asymmetrical PAUSE */ -#define F1_LINK_ASYPAUSE 0x0800 - - /* Link partner faulted */ -#define F1_LINK_RFAULT 0x2000 - - /* Link partner acked us */ -#define F1_LINK_LPACK 0x4000 - - /* Next page bit */ -#define F1_LINK_NPAGE 0x8000 - - /* Auto-Negotiation Expansion Register offset:6 */ - - /* Next Page Transmit Register offset:7 */ - - /* Link partner Next Page Register offset:8*/ - - /* 1000BASE-T Control Register offset:9*/ - /* Advertise 1000T HD capability */ -#define F1_CTL_1000T_HD_CAPS 0x0100 - - /* Advertise 1000T FD capability */ -#define F1_CTL_1000T_FD_CAPS 0x0200 - - /* 1=Repeater/switch device port 0=DTE device*/ -#define F1_CTL_1000T_REPEATER_DTE 0x0400 - - /* 1=Configure PHY as Master 0=Configure PHY as Slave */ -#define F1_CTL_1000T_MS_VALUE 0x0800 - - /* 1=Master/Slave manual config value 0=Automatic Master/Slave config */ -#define F1_CTL_1000T_MS_ENABLE 0x1000 - - /* Normal Operation */ -#define F1_CTL_1000T_TEST_MODE_NORMAL 0x0000 - - /* Transmit Waveform test */ -#define F1_CTL_1000T_TEST_MODE_1 0x2000 - - /* Master Transmit Jitter test */ -#define F1_CTL_1000T_TEST_MODE_2 0x4000 - - /* Slave Transmit Jitter test */ -#define F1_CTL_1000T_TEST_MODE_3 0x6000 - - /* Transmitter Distortion test */ -#define F1_CTL_1000T_TEST_MODE_4 0x8000 -#define F1_CTL_1000T_SPEED_MASK 0x0300 -#define F1_CTL_1000T_DEFAULT_CAP_MASK 0x0300 - - /* 1000BASE-T Status Register offset:10 */ - /* LP is 1000T HD capable */ -#define F1_STATUS_1000T_LP_HD_CAPS 0x0400 - - /* LP is 1000T FD capable */ -#define F1_STATUS_1000T_LP_FD_CAPS 0x0800 - - /* Remote receiver OK */ -#define F1_STATUS_1000T_REMOTE_RX_STATUS 0x1000 - - /* Local receiver OK */ -#define F1_STATUS_1000T_LOCAL_RX_STATUS 0x2000 - - /* 1=Local TX is Master, 0=Slave */ -#define F1_STATUS_1000T_MS_CONFIG_RES 0x4000 - -#define F1_STATUS_1000T_MS_CONFIG_FAULT 0x8000 - - /* Master/Slave config fault */ -#define F1_STATUS_1000T_REMOTE_RX_STATUS_SHIFT 12 -#define F1_STATUS_1000T_LOCAL_RX_STATUS_SHIFT 13 - - /* Phy Specific Control Register offset:16*/ - /* 1=Jabber Function disabled */ -#define F1_CTL_JABBER_DISABLE 0x0001 - - /* 1=Polarity Reversal enabled */ -#define F1_CTL_POLARITY_REVERSAL 0x0002 - - /* 1=SQE Test enabled */ -#define F1_CTL_SQE_TEST 0x0004 -#define F1_CTL_MAC_POWERDOWN 0x0008 - - /* 1=CLK125 low, 0=CLK125 toggling - #define F1_CTL_CLK125_DISABLE 0x0010 - */ - /* MDI Crossover Mode bits 6:5 */ - /* Manual MDI configuration */ -#define F1_CTL_MDI_MANUAL_MODE 0x0000 - - /* Manual MDIX configuration */ -#define F1_CTL_MDIX_MANUAL_MODE 0x0020 - - /* 1000BASE-T: Auto crossover, 100BASE-TX/10BASE-T: MDI Mode */ -#define F1_CTL_AUTO_X_1000T 0x0040 - - /* Auto crossover enabled all speeds */ -#define F1_CTL_AUTO_X_MODE 0x0060 - - /* 1=Enable Extended 10BASE-T distance - * (Lower 10BASE-T RX Threshold) - * 0=Normal 10BASE-T RX Threshold */ -#define F1_CTL_10BT_EXT_DIST_ENABLE 0x0080 - - /* 1=5-Bit interface in 100BASE-TX - * 0=MII interface in 100BASE-TX */ -#define F1_CTL_MII_5BIT_ENABLE 0x0100 - - /* 1=Scrambler disable */ -#define F1_CTL_SCRAMBLER_DISABLE 0x0200 - - /* 1=Force link good */ -#define F1_CTL_FORCE_LINK_GOOD 0x0400 - - /* 1=Assert CRS on Transmit */ -#define F1_CTL_ASSERT_CRS_ON_TX 0x0800 - -#define F1_CTL_POLARITY_REVERSAL_SHIFT 1 -#define F1_CTL_AUTO_X_MODE_SHIFT 5 -#define F1_CTL_10BT_EXT_DIST_ENABLE_SHIFT 7 - - /* Phy Specific status fields offset:17*/ - /* 1=Speed & Duplex resolved */ -#define F1_STATUS_LINK_PASS 0x0400 -#define F1_STATUS_RESOVLED 0x0800 - - /* 1=Duplex 0=Half Duplex */ -#define F1_STATUS_FULL_DUPLEX 0x2000 - - /* Speed, bits 14:15 */ -#define F1_STATUS_SPEED 0xC000 -#define F1_STATUS_SPEED_MASK 0xC000 - - /* 00=10Mbs */ -#define F1_STATUS_SPEED_10MBS 0x0000 - - /* 01=100Mbs */ -#define F1_STATUS_SPEED_100MBS 0x4000 - - /* 10=1000Mbs */ -#define F1_STATUS_SPEED_1000MBS 0x8000 -#define F1_SPEED_DUPLEX_RESOVLED(phy_status) \ - (((phy_status) & \ - (F1_STATUS_RESOVLED)) == \ - (F1_STATUS_RESOVLED)) - - /*phy debug port1 register offset:29*/ - /*phy debug port2 register offset:30*/ - - /*F1 interrupt flag */ -#define F1_INTR_SPEED_CHANGE 0x4000 -#define F1_INTR_DUPLEX_CHANGE 0x2000 -#define F1_INTR_STATUS_UP_CHANGE 0x0400 -#define F1_INTR_STATUS_DOWN_CHANGE 0x0800 - - sw_error_t - f1_phy_set_powersave(a_uint32_t dev_id, a_uint32_t phy_id, a_bool_t enable); - - sw_error_t - f1_phy_get_powersave(a_uint32_t dev_id, a_uint32_t phy_id, a_bool_t *enable); - - sw_error_t - f1_phy_set_hibernate(a_uint32_t dev_id, a_uint32_t phy_id, a_bool_t enable); - - sw_error_t - f1_phy_get_hibernate(a_uint32_t dev_id, a_uint32_t phy_id, a_bool_t *enable); - - sw_error_t - f1_phy_cdt(a_uint32_t dev_id, a_uint32_t phy_id, a_uint32_t mdi_pair, - fal_cable_status_t *cable_status, a_uint32_t *cable_len) ; - - sw_error_t - f1_phy_set_duplex(a_uint32_t dev_id, a_uint32_t phy_id, - fal_port_duplex_t duplex); - - sw_error_t - f1_phy_get_duplex(a_uint32_t dev_id, a_uint32_t phy_id, - fal_port_duplex_t * duplex); - - sw_error_t - f1_phy_set_speed(a_uint32_t dev_id, a_uint32_t phy_id, - fal_port_speed_t speed); - - sw_error_t - f1_phy_get_speed(a_uint32_t dev_id, a_uint32_t phy_id, - fal_port_speed_t * speed); - - sw_error_t - f1_phy_restart_autoneg(a_uint32_t dev_id, a_uint32_t phy_id); - - sw_error_t - f1_phy_enable_autoneg(a_uint32_t dev_id, a_uint32_t phy_id); - - a_bool_t - f1_phy_get_link_status(a_uint32_t dev_id, a_uint32_t phy_id); - - sw_error_t - f1_phy_set_autoneg_adv(a_uint32_t dev_id, a_uint32_t phy_id, - a_uint32_t autoneg); - - sw_error_t - f1_phy_get_autoneg_adv(a_uint32_t dev_id, a_uint32_t phy_id, - a_uint32_t * autoneg); - - a_bool_t f1_phy_autoneg_status(a_uint32_t dev_id, a_uint32_t phy_id); - - sw_error_t - f1_phy_intr_mask_set(a_uint32_t dev_id, a_uint32_t phy_id, - a_uint32_t intr_mask_flag); - - sw_error_t - f1_phy_intr_mask_get(a_uint32_t dev_id, a_uint32_t phy_id, - a_uint32_t * intr_mask_flag); - - sw_error_t - f1_phy_intr_status_get(a_uint32_t dev_id, a_uint32_t phy_id, - a_uint32_t * intr_status_flag); - - sw_error_t - f1_phy_set_8023az(a_uint32_t dev_id, a_uint32_t phy_id, a_bool_t enable); - - sw_error_t - f1_phy_get_8023az(a_uint32_t dev_id, a_uint32_t phy_id, a_bool_t *enable); - - int - f1_phy_init(a_uint32_t dev_id, a_uint32_t port_bmp); - -#ifdef __cplusplus -} -#endif /* __cplusplus */ -#endif /* _F1_PHY_H_ */ diff --git a/feeds/ipq807x/qca-ssdk/src/include/hsl/phy/f2_phy.h b/feeds/ipq807x/qca-ssdk/src/include/hsl/phy/f2_phy.h deleted file mode 100755 index 13ce278a8..000000000 --- a/feeds/ipq807x/qca-ssdk/src/include/hsl/phy/f2_phy.h +++ /dev/null @@ -1,399 +0,0 @@ -/* - * Copyright (c) 2012, 2015, 2017, The Linux Foundation. All rights reserved. - * Permission to use, copy, modify, and/or distribute this software for - * any purpose with or without fee is hereby granted, provided that the - * above copyright notice and this permission notice appear in all copies. - * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES - * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR - * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES - * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN - * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT - * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. - */ - - - -#ifndef _F2_PHY_H_ -#define _F2_PHY_H_ - -#ifdef __cplusplus -extern "C" { -#endif /* __cplusplus */ - - /* Athena PHY Registers */ -#define F2_PHY_CONTROL 0 -#define F2_PHY_STATUS 1 -#define F2_PHY_ID1 2 -#define F2_PHY_ID2 3 -#define F2_AUTONEG_ADVERT 4 -#define F2_LINK_PARTNER_ABILITY 5 -#define F2_AUTONEG_EXPANSION 6 -#define F2_NEXT_PAGE_TRANSMIT 7 -#define F2_LINK_PARTNER_NEXT_PAGE 8 -#define F2_1000BASET_CONTROL 9 -#define F2_1000BASET_STATUS 10 -#define F2_PHY_SPEC_CONTROL 16 -#define F2_PHY_SPEC_STATUS 17 -#define F2_PHY_CDT_CONTROL 22 -#define F2_PHY_CDT_STATUS 28 -#define F2_DEBUG_PORT_ADDRESS 29 -#define F2_DEBUG_PORT_DATA 30 - - /* Athena PHY Registers Field*/ - - /* Control Register fields offset:0*/ - /* bits 6,13: 10=1000, 01=100, 00=10 */ -#define F2_CTRL_SPEED_MSB 0x0040 - - /* Collision test enable */ -#define F2_CTRL_COLL_TEST_ENABLE 0x0080 - - /* FDX =1, half duplex =0 */ -#define F2_CTRL_FULL_DUPLEX 0x0100 - - /* Restart auto negotiation */ -#define F2_CTRL_RESTART_AUTONEGOTIATION 0x0200 - - /* Isolate PHY from MII */ -#define F2_CTRL_ISOLATE 0x0400 - - /* Power down */ -#define F2_CTRL_POWER_DOWN 0x0800 - - /* Auto Neg Enable */ -#define F2_CTRL_AUTONEGOTIATION_ENABLE 0x1000 - - /* bits 6,13: 10=1000, 01=100, 00=10 */ -#define F2_CTRL_SPEED_LSB 0x2000 - - /* 0 = normal, 1 = loopback */ -#define F2_CTRL_LOOPBACK 0x4000 -#define F2_CTRL_SOFTWARE_RESET 0x8000 - -#define F2_CTRL_SPEED_MASK 0x2040 -#define F2_CTRL_SPEED_1000 0x0040 -#define F2_CTRL_SPEED_100 0x2000 -#define F2_CTRL_SPEED_10 0x0000 - -#define F2_RESET_DONE(phy_control) \ - (((phy_control) & (F2_CTRL_SOFTWARE_RESET)) == 0) - - /* Status Register fields offset:1*/ - /* Extended register capabilities */ -#define F2_STATUS_EXTENDED_CAPS 0x0001 - - /* Jabber Detected */ -#define F2_STATUS_JABBER_DETECT 0x0002 - - /* Link Status 1 = link */ -#define F2_STATUS_LINK_STATUS_UP 0x0004 - - /* Auto Neg Capable */ -#define F2_STATUS_AUTONEG_CAPS 0x0008 - - /* Remote Fault Detect */ -#define F2_STATUS_REMOTE_FAULT 0x0010 - - /* Auto Neg Complete */ -#define F2_STATUS_AUTO_NEG_DONE 0x0020 - - /* Preamble may be suppressed */ -#define F2_STATUS_PREAMBLE_SUPPRESS 0x0040 - - /* Ext. status info in Reg 0x0F */ -#define F2_STATUS_EXTENDED_STATUS 0x0100 - - /* 100T2 Half Duplex Capable */ -#define F2_STATUS_100T2_HD_CAPS 0x0200 - - /* 100T2 Full Duplex Capable */ -#define F2_STATUS_100T2_FD_CAPS 0x0400 - - /* 10T Half Duplex Capable */ -#define F2_STATUS_10T_HD_CAPS 0x0800 - - /* 10T Full Duplex Capable */ -#define F2_STATUS_10T_FD_CAPS 0x1000 - - /* 100X Half Duplex Capable */ -#define F2_STATUS_100X_HD_CAPS 0x2000 - - /* 100X Full Duplex Capable */ -#define F2_STATUS_100X_FD_CAPS 0x4000 - - /* 100T4 Capable */ -#define F2_STATUS_100T4_CAPS 0x8000 - -#define F2_AUTONEG_DONE(ip_phy_status) \ - (((ip_phy_status) & (F2_STATUS_AUTO_NEG_DONE)) == \ - (F2_STATUS_AUTO_NEG_DONE)) - - /* PHY identifier1 offset:2*/ -//Organizationally Unique Identifier bits 3:18 - - /* PHY identifier2 offset:3*/ -//Organizationally Unique Identifier bits 19:24 - - /* Auto-Negotiation Advertisement register. offset:4*/ - /* indicates IEEE 802.3 CSMA/CD */ -#define F2_ADVERTISE_SELECTOR_FIELD 0x0001 - - /* 10T Half Duplex Capable */ -#define F2_ADVERTISE_10HALF 0x0020 - - /* 10T Full Duplex Capable */ -#define F2_ADVERTISE_10FULL 0x0040 - - /* 100TX Half Duplex Capable */ -#define F2_ADVERTISE_100HALF 0x0080 - - /* 100TX Full Duplex Capable */ -#define F2_ADVERTISE_100FULL 0x0100 - - /* 100T4 Capable */ -#define F2_ADVERTISE_100T4 0x0200 - - /* Pause operation desired */ -#define F2_ADVERTISE_PAUSE 0x0400 - - /* Asymmetric Pause Direction bit */ -#define F2_ADVERTISE_ASYM_PAUSE 0x0800 - - /* Remote Fault detected */ -#define F2_ADVERTISE_REMOTE_FAULT 0x2000 - - /* Next Page ability supported */ -#define F2_ADVERTISE_NEXT_PAGE 0x8000 - -#define F2_ADVERTISE_ALL \ - (F2_ADVERTISE_10HALF | F2_ADVERTISE_10FULL | \ - F2_ADVERTISE_100HALF | F2_ADVERTISE_100FULL ) - - /* Link Partner ability offset:5*/ - /* Same as advertise selector */ -#define F2_LINK_SLCT 0x001f - - /* Can do 10mbps half-duplex */ -#define F2_LINK_10BASETX_HALF_DUPLEX 0x0020 - - /* Can do 10mbps full-duplex */ -#define F2_LINK_10BASETX_FULL_DUPLEX 0x0040 - - /* Can do 100mbps half-duplex */ -#define F2_LINK_100BASETX_HALF_DUPLEX 0x0080 - - /* Can do 100mbps full-duplex */ -#define F2_LINK_100BASETX_FULL_DUPLEX 0x0100 - - /* 100BASE-T4 */ -#define F2_LINK_100BASE4 0x0200 - - /* PAUSE */ -#define F2_LINK_PAUSE 0x0400 - - /* Asymmetrical PAUSE */ -#define F2_LINK_ASYPAUSE 0x0800 - - /* Link partner faulted */ -#define F2_LINK_RFAULT 0x2000 - - /* Link partner acked us */ -#define F2_LINK_LPACK 0x4000 - - /* Next page bit */ -#define F2_LINK_NPAGE 0x8000 - - /* Auto-Negotiation Expansion Register offset:6 */ - - /* Next Page Transmit Register offset:7 */ - - /* Link partner Next Page Register offset:8*/ - - /* 1000BASE-T Control Register offset:9*/ - /* Advertise 1000T HD capability */ -#define F2_CTL_1000T_HD_CAPS 0x0100 - - /* Advertise 1000T FD capability */ -#define F2_CTL_1000T_FD_CAPS 0x0200 - - /* 1=Repeater/switch device port 0=DTE device*/ -#define F2_CTL_1000T_REPEATER_DTE 0x0400 - - /* 1=Configure PHY as Master 0=Configure PHY as Slave */ -#define F2_CTL_1000T_MS_VALUE 0x0800 - - /* 1=Master/Slave manual config value 0=Automatic Master/Slave config */ -#define F2_CTL_1000T_MS_ENABLE 0x1000 - - /* Normal Operation */ -#define F2_CTL_1000T_TEST_MODE_NORMAL 0x0000 - - /* Transmit Waveform test */ -#define F2_CTL_1000T_TEST_MODE_1 0x2000 - - /* Master Transmit Jitter test */ -#define F2_CTL_1000T_TEST_MODE_2 0x4000 - - /* Slave Transmit Jitter test */ -#define F2_CTL_1000T_TEST_MODE_3 0x6000 - - /* Transmitter Distortion test */ -#define F2_CTL_1000T_TEST_MODE_4 0x8000 -#define F2_CTL_1000T_SPEED_MASK 0x0300 -#define F2_CTL_1000T_DEFAULT_CAP_MASK 0x0300 - - /* 1000BASE-T Status Register offset:10 */ - /* LP is 1000T HD capable */ -#define F2_STATUS_1000T_LP_HD_CAPS 0x0400 - - /* LP is 1000T FD capable */ -#define F2_STATUS_1000T_LP_FD_CAPS 0x0800 - - /* Remote receiver OK */ -#define F2_STATUS_1000T_REMOTE_RX_STATUS 0x1000 - - /* Local receiver OK */ -#define F2_STATUS_1000T_LOCAL_RX_STATUS 0x2000 - - /* 1=Local TX is Master, 0=Slave */ -#define F2_STATUS_1000T_MS_CONFIG_RES 0x4000 - -#define F2_STATUS_1000T_MS_CONFIG_FAULT 0x8000 - - /* Master/Slave config fault */ -#define F2_STATUS_1000T_REMOTE_RX_STATUS_SHIFT 12 -#define F2_STATUS_1000T_LOCAL_RX_STATUS_SHIFT 13 - - /* Phy Specific Control Register offset:16*/ - /* 1=Jabber Function disabled */ -#define F2_CTL_JABBER_DISABLE 0x0001 - - /* 1=Polarity Reversal enabled */ -#define F2_CTL_POLARITY_REVERSAL 0x0002 - - /* 1=SQE Test enabled */ -#define F2_CTL_SQE_TEST 0x0004 -#define F2_CTL_MAC_POWERDOWN 0x0008 - - /* 1=CLK125 low, 0=CLK125 toggling - #define F2_CTL_CLK125_DISABLE 0x0010 - */ - /* MDI Crossover Mode bits 6:5 */ - /* Manual MDI configuration */ -#define F2_CTL_MDI_MANUAL_MODE 0x0000 - - /* Manual MDIX configuration */ -#define F2_CTL_MDIX_MANUAL_MODE 0x0020 - - /* 1000BASE-T: Auto crossover, 100BASE-TX/10BASE-T: MDI Mode */ -#define F2_CTL_AUTO_X_1000T 0x0040 - - /* Auto crossover enabled all speeds */ -#define F2_CTL_AUTO_X_MODE 0x0060 - - /* 1=Enable Extended 10BASE-T distance - * (Lower 10BASE-T RX Threshold) - * 0=Normal 10BASE-T RX Threshold */ -#define F2_CTL_10BT_EXT_DIST_ENABLE 0x0080 - - /* 1=5-Bit interface in 100BASE-TX - * 0=MII interface in 100BASE-TX */ -#define F2_CTL_MII_5BIT_ENABLE 0x0100 - - /* 1=Scrambler disable */ -#define F2_CTL_SCRAMBLER_DISABLE 0x0200 - - /* 1=Force link good */ -#define F2_CTL_FORCE_LINK_GOOD 0x0400 - - /* 1=Assert CRS on Transmit */ -#define F2_CTL_ASSERT_CRS_ON_TX 0x0800 - -#define F2_CTL_POLARITY_REVERSAL_SHIFT 1 -#define F2_CTL_AUTO_X_MODE_SHIFT 5 -#define F2_CTL_10BT_EXT_DIST_ENABLE_SHIFT 7 - - /* Phy Specific status fields offset:17*/ - /* 1=Speed & Duplex resolved */ -#define F2_STATUS_RESOVLED 0x0800 - - /* 1=Duplex 0=Half Duplex */ -#define F2_STATUS_FULL_DUPLEX 0x2000 - - /* Speed, bits 14:15 */ -#define F2_STATUS_SPEED 0xC000 -#define F2_STATUS_SPEED_MASK 0xC000 - - /* 00=10Mbs */ -#define F2_STATUS_SPEED_10MBS 0x0000 - - /* 01=100Mbs */ -#define F2_STATUS_SPEED_100MBS 0x4000 - - /* 10=1000Mbs */ -#define F2_STATUS_SPEED_1000MBS 0x8000 -#define F2_SPEED_DUPLEX_RESOVLED(phy_status) \ - (((phy_status) & \ - (F2_STATUS_RESOVLED)) == \ - (F2_STATUS_RESOVLED)) - - /*phy debug port1 register offset:29*/ - /*phy debug port2 register offset:30*/ - - sw_error_t - f2_phy_set_powersave(a_uint32_t dev_id, a_uint32_t phy_id, a_bool_t enable); - - sw_error_t - f2_phy_get_powersave(a_uint32_t dev_id, a_uint32_t phy_id, a_bool_t *enable); - - sw_error_t - f2_phy_set_hibernate(a_uint32_t dev_id, a_uint32_t phy_id, a_bool_t enable); - - sw_error_t - f2_phy_get_hibernate(a_uint32_t dev_id, a_uint32_t phy_id, a_bool_t *enable); - - sw_error_t - f2_phy_cdt(a_uint32_t dev_id, a_uint32_t phy_id, a_uint32_t mdi_pair, - fal_cable_status_t *cable_status, a_uint32_t *cable_len) ; - - sw_error_t - f2_phy_set_duplex(a_uint32_t dev_id, a_uint32_t phy_id, - fal_port_duplex_t duplex); - - sw_error_t - f2_phy_get_duplex(a_uint32_t dev_id, a_uint32_t phy_id, - fal_port_duplex_t * duplex); - - sw_error_t - f2_phy_set_speed(a_uint32_t dev_id, a_uint32_t phy_id, - fal_port_speed_t speed); - - sw_error_t - f2_phy_get_speed(a_uint32_t dev_id, a_uint32_t phy_id, - fal_port_speed_t * speed); - - sw_error_t - f2_phy_restart_autoneg(a_uint32_t dev_id, a_uint32_t phy_id); - - sw_error_t - f2_phy_enable_autoneg(a_uint32_t dev_id, a_uint32_t phy_id); - - sw_error_t - f2_phy_set_autoneg_adv(a_uint32_t dev_id, a_uint32_t phy_id, - a_uint32_t autoneg); - - sw_error_t - f2_phy_get_autoneg_adv(a_uint32_t dev_id, a_uint32_t phy_id, - a_uint32_t * autoneg); - - a_bool_t - f2_phy_autoneg_status(a_uint32_t dev_id, a_uint32_t phy_id); - - int f2_phy_init(a_uint32_t dev_id, a_uint32_t port_bmp); - - -#ifdef __cplusplus -} -#endif /* __cplusplus */ -#endif /* _F2_PHY_H_ */ diff --git a/feeds/ipq807x/qca-ssdk/src/include/hsl/phy/hsl_phy.h b/feeds/ipq807x/qca-ssdk/src/include/hsl/phy/hsl_phy.h deleted file mode 100755 index 4621e725d..000000000 --- a/feeds/ipq807x/qca-ssdk/src/include/hsl/phy/hsl_phy.h +++ /dev/null @@ -1,722 +0,0 @@ -/* - * Copyright (c) 2015, 2017-2021, The Linux Foundation. All rights reserved. - * Permission to use, copy, modify, and/or distribute this software for - * any purpose with or without fee is hereby granted, provided that the - * above copyright notice and this permission notice appear in all copies. - * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES - * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR - * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES - * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN - * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT - * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. - */ -/*qca808x_start*/ -#ifndef _HSL_PHY_H_ -#define _HSL_PHY_H_ - -#ifdef __cplusplus -extern "C" { -#endif /* __cplusplus */ - -#include "fal.h" -#include - - /** Phy function reset type */ - typedef enum { - PHY_FIFO_RESET = 0, /**< Phy fifo reset */ - } hsl_phy_function_reset_t; - - typedef sw_error_t(*hsl_phy_init) (a_uint32_t dev_id, - a_uint32_t phy_id); - typedef sw_error_t(*hsl_phy_hibernation_set) (a_uint32_t dev_id, - a_uint32_t phy_id, - a_bool_t enable); - typedef sw_error_t(*hsl_phy_hibernation_get) (a_uint32_t dev_id, - a_uint32_t phy_id, - a_bool_t * enable); - typedef sw_error_t(*hsl_phy_speed_get) (a_uint32_t dev_id, - a_uint32_t phy_id, - fal_port_speed_t * speed); - typedef sw_error_t(*hsl_phy_speed_set) (a_uint32_t dev_id, - a_uint32_t phy_id, - fal_port_speed_t speed); - typedef sw_error_t(*hsl_phy_duplex_get) (a_uint32_t dev_id, - a_uint32_t phy_id, - fal_port_duplex_t * duplex); - typedef sw_error_t(*hsl_phy_duplex_set) (a_uint32_t dev_id, - a_uint32_t phy_id, - fal_port_duplex_t duplex); - typedef sw_error_t(*hsl_phy_autoneg_enable_set) (a_uint32_t dev_id, - a_uint32_t phy_id); - typedef sw_error_t(*hsl_phy_autoneg_enable_get) (a_uint32_t dev_id, - a_uint32_t phy_id, - a_bool_t * enable); - typedef sw_error_t(*hsl_phy_restart_autoneg) (a_uint32_t dev_id, - a_uint32_t phy_id); - typedef a_bool_t(*hsl_phy_autoneg_status_get) (a_uint32_t dev_id, - a_uint32_t phy_id); - typedef sw_error_t(*hsl_phy_powersave_set) (a_uint32_t dev_id, - a_uint32_t phy_id, - a_bool_t enable); - typedef sw_error_t(*hsl_phy_powersave_get) (a_uint32_t dev_id, - a_uint32_t phy_id, - a_bool_t * enable); - typedef sw_error_t(*hsl_phy_cdt) (a_uint32_t dev_id, a_uint32_t phy_id, - a_uint32_t mdi_pair, - fal_cable_status_t * cable_status, - a_uint32_t * cable_len); - typedef a_bool_t(*hsl_phy_link_status_get) (a_uint32_t dev_id, - a_uint32_t phy_id); - typedef sw_error_t(*hsl_phy_get_ability) (a_uint32_t dev_id, - a_uint32_t phy_id, - a_uint32_t * ability); - typedef sw_error_t(*hsl_phy_mdix_set) (a_uint32_t dev_id, - a_uint32_t phy_id, - fal_port_mdix_mode_t mode); - typedef sw_error_t(*hsl_phy_mdix_get) (a_uint32_t dev_id, - a_uint32_t phy_id, - fal_port_mdix_mode_t * mode); - typedef sw_error_t(*hsl_phy_mdix_status_get) (a_uint32_t dev_id, - a_uint32_t phy_id, - fal_port_mdix_status_t * - mode); - typedef sw_error_t(*hsl_phy_8023az_set) (a_uint32_t dev_id, - a_uint32_t phy_id, - a_bool_t enable); - typedef sw_error_t(*hsl_phy_8023az_get) (a_uint32_t dev_id, - a_uint32_t phy_id, - a_bool_t * enable); - typedef sw_error_t(*hsl_phy_local_loopback_set) (a_uint32_t dev_id, - a_uint32_t phy_id, - a_bool_t enable); - typedef sw_error_t(*hsl_phy_local_loopback_get) (a_uint32_t dev_id, - a_uint32_t phy_id, - a_bool_t * enable); - typedef sw_error_t(*hsl_phy_remote_loopback_set) (a_uint32_t dev_id, - a_uint32_t phy_id, - a_bool_t enable); - typedef sw_error_t(*hsl_phy_remote_loopback_get) (a_uint32_t dev_id, - a_uint32_t phy_id, - a_bool_t * enable); - typedef sw_error_t(*hsl_phy_master_set) (a_uint32_t dev_id, - a_uint32_t phy_id, - fal_port_master_t master); - typedef sw_error_t(*hsl_phy_master_get) (a_uint32_t dev_id, - a_uint32_t phy_id, - fal_port_master_t * master); -/*qca808x_end*/ - typedef sw_error_t(*hsl_phy_combo_prefer_medium_set) (a_uint32_t dev_id, - a_uint32_t phy_id, - fal_port_medium_t - phy_medium); - typedef sw_error_t(*hsl_phy_combo_prefer_medium_get) (a_uint32_t dev_id, - a_uint32_t phy_id, - fal_port_medium_t - * phy_medium); - typedef sw_error_t(*hsl_phy_combo_medium_status_get) (a_uint32_t dev_id, - a_uint32_t phy_id, - fal_port_medium_t - * phy_medium); - typedef sw_error_t(*hsl_phy_combo_fiber_mode_set) (a_uint32_t dev_id, - a_uint32_t phy_id, - fal_port_fiber_mode_t - fiber_mode); - typedef sw_error_t(*hsl_phy_combo_fiber_mode_get) (a_uint32_t dev_id, - a_uint32_t phy_id, - fal_port_fiber_mode_t - * fiber_mode); - typedef sw_error_t (*hsl_phy_function_reset) (a_uint32_t dev_id, - a_uint32_t phy_id, - hsl_phy_function_reset_t - phy_reset_type); -/*qca808x_start*/ - typedef sw_error_t(*hsl_phy_reset) (a_uint32_t dev_id, - a_uint32_t phy_id); - typedef sw_error_t(*hsl_phy_reset_status_get) (a_uint32_t dev_id, - a_uint32_t phy_id, - fal_port_reset_status_t * - status); - typedef sw_error_t(*hsl_phy_power_off) (a_uint32_t dev_id, - a_uint32_t phy_id); - typedef sw_error_t(*hsl_phy_power_on) (a_uint32_t dev_id, - a_uint32_t phy_id); - typedef sw_error_t(*hsl_phy_id_get) (a_uint32_t dev_id, - a_uint32_t phy_id, - a_uint32_t *phy_chip_id); - typedef sw_error_t(*hsl_phy_autoneg_adv_set) (a_uint32_t dev_id, - a_uint32_t phy_id, - a_uint32_t autoneg); - typedef sw_error_t(*hsl_phy_autoneg_adv_get) (a_uint32_t dev_id, - a_uint32_t phy_id, - a_uint32_t * autoneg); - typedef sw_error_t(*hsl_phy_reg_write) (a_uint32_t dev_id, - a_uint32_t phy_addr, - a_uint32_t reg, - a_uint16_t reg_val); - typedef a_uint16_t(*hsl_phy_reg_read) (a_uint32_t dev_id, - a_uint32_t phy_addr, - a_uint32_t reg); - typedef sw_error_t(*hsl_phy_debug_write) (a_uint32_t dev_id, - a_uint32_t phy_id, - a_uint16_t reg_id, - a_uint16_t reg_val); - typedef a_uint16_t(*hsl_phy_debug_read) (a_uint32_t dev_id, - a_uint32_t phy_id, - a_uint16_t reg_id); - typedef sw_error_t(*hsl_phy_mmd_write) (a_uint32_t dev_id, - a_uint32_t phy_id, - a_uint16_t mmd_num, - a_uint16_t reg_id, - a_uint16_t reg_val); - typedef a_uint16_t(*hsl_phy_mmd_read) (a_uint32_t dev_id, - a_uint32_t phy_id, - a_uint16_t mmd_num, - a_uint16_t reg_id); - - typedef sw_error_t(*hsl_phy_magic_frame_mac_set) (a_uint32_t dev_id, - a_uint32_t phy_id, - fal_mac_addr_t * mac); - - typedef sw_error_t(*hsl_phy_magic_frame_mac_get) (a_uint32_t dev_id, - a_uint32_t phy_id, - fal_mac_addr_t * mac); - typedef sw_error_t(*hsl_phy_wol_status_set) (a_uint32_t dev_id, - a_uint32_t phy_id, - a_bool_t enable); - typedef sw_error_t(*hsl_phy_wol_status_get) (a_uint32_t dev_id, - a_uint32_t phy_id, - a_bool_t * enable); - typedef sw_error_t(*hsl_phy_interface_mode_set) (a_uint32_t dev_id, - a_uint32_t phy_id, - fal_port_interface_mode_t - interface_mode); - typedef sw_error_t(*hsl_phy_interface_mode_get) (a_uint32_t dev_id, - a_uint32_t phy_id, - fal_port_interface_mode_t - * interface_mode); - typedef sw_error_t(*hsl_phy_interface_mode_status_get) (a_uint32_t dev_id, - a_uint32_t phy_id, - fal_port_interface_mode_t - * interface_mode); - typedef sw_error_t(*hsl_phy_intr_mask_set) (a_uint32_t dev_id, - a_uint32_t phy_id, - a_uint32_t mask); - typedef sw_error_t(*hsl_phy_intr_mask_get) (a_uint32_t dev_id, - a_uint32_t phy_id, - a_uint32_t * mask); - typedef sw_error_t(*hsl_phy_intr_status_get) (a_uint32_t dev_id, - a_uint32_t phy_id, - a_uint32_t * status); - typedef sw_error_t(*hsl_phy_counter_set) (a_uint32_t dev_id, - a_uint32_t phy_id, - a_bool_t enable); - typedef sw_error_t(*hsl_phy_counter_get) (a_uint32_t dev_id, - a_uint32_t phy_id, - a_bool_t * enable); - typedef sw_error_t(*hsl_phy_counter_show) (a_uint32_t dev_id, - a_uint32_t phy_id, - fal_port_counter_info_t * counter_info); - typedef sw_error_t(*hsl_phy_serdes_reset) (a_uint32_t dev_id); - - typedef sw_error_t(*hsl_phy_get_status) (a_uint32_t dev_id, - a_uint32_t phy_id, struct port_phy_status *phy_status); - - typedef sw_error_t(*hsl_phy_eee_adv_set) (a_uint32_t dev_id, - a_uint32_t phy_id, - a_uint32_t adv); - typedef sw_error_t(*hsl_phy_eee_adv_get) (a_uint32_t dev_id, - a_uint32_t phy_id, - a_uint32_t * adv); - typedef sw_error_t(*hsl_phy_eee_partner_adv_get) (a_uint32_t dev_id, - a_uint32_t phy_id, - a_uint32_t * adv); - typedef sw_error_t(*hsl_phy_eee_cap_get) (a_uint32_t dev_id, - a_uint32_t phy_id, - a_uint32_t * cap); - typedef sw_error_t(*hsl_phy_eee_status_get) (a_uint32_t dev_id, - a_uint32_t phy_id, - a_uint32_t * status); -/*qca808x_end*/ - typedef sw_error_t(*hsl_phy_led_ctrl_pattern_set) (a_uint32_t dev_id, - a_uint32_t phy_id, - led_ctrl_pattern_t * pattern); - typedef sw_error_t(*hsl_phy_led_ctrl_pattern_get) (a_uint32_t dev_id, - a_uint32_t phy_id, - led_ctrl_pattern_t * pattern); - typedef sw_error_t(*hsl_phy_led_ctrl_source_set) (a_uint32_t dev_id, - a_uint32_t phy_id, - a_uint32_t source_id, - led_ctrl_pattern_t * pattern); - typedef sw_error_t(*hsl_phy_ptp_security_set) (a_uint32_t dev_id, - a_uint32_t phy_id, fal_ptp_security_t *sec); - - typedef sw_error_t(*hsl_phy_ptp_link_delay_set) (a_uint32_t dev_id, - a_uint32_t phy_id, fal_ptp_time_t *time); - - typedef sw_error_t(*hsl_phy_ptp_rx_crc_recalc_status_get) (a_uint32_t dev_id, - a_uint32_t phy_id, a_bool_t *status); - - typedef sw_error_t(*hsl_phy_ptp_tod_uart_set) (a_uint32_t dev_id, - a_uint32_t phy_id, fal_ptp_tod_uart_t *tod_uart); - - typedef sw_error_t(*hsl_phy_ptp_enhanced_timestamp_engine_get) (a_uint32_t dev_id, - a_uint32_t phy_id, fal_ptp_direction_t direction, - fal_ptp_enhanced_ts_engine_t *ts_engine); - - typedef sw_error_t(*hsl_phy_ptp_pps_signal_control_set) (a_uint32_t dev_id, - a_uint32_t phy_id, fal_ptp_pps_signal_control_t *sig_control); - - typedef sw_error_t(*hsl_phy_ptp_timestamp_get) (a_uint32_t dev_id, - a_uint32_t phy_id, fal_ptp_direction_t direction, - fal_ptp_pkt_info_t *pkt_info, fal_ptp_time_t *time); - - typedef sw_error_t(*hsl_phy_ptp_asym_correction_get) (a_uint32_t dev_id, - a_uint32_t phy_id, fal_ptp_asym_correction_t* asym_cf); - - typedef sw_error_t(*hsl_phy_ptp_rtc_time_snapshot_status_get) (a_uint32_t dev_id, - a_uint32_t phy_id, a_bool_t *status); - - typedef sw_error_t(*hsl_phy_ptp_capture_set) (a_uint32_t dev_id, - a_uint32_t phy_id, a_uint32_t capture_id, - fal_ptp_capture_t *capture); - - typedef sw_error_t(*hsl_phy_ptp_rtc_adjfreq_set) (a_uint32_t dev_id, - a_uint32_t phy_id, fal_ptp_time_t *time); - - typedef sw_error_t(*hsl_phy_ptp_asym_correction_set) (a_uint32_t dev_id, - a_uint32_t phy_id, fal_ptp_asym_correction_t *asym_cf); - - typedef sw_error_t(*hsl_phy_ptp_pkt_timestamp_set) (a_uint32_t dev_id, - a_uint32_t phy_id, fal_ptp_time_t *time); - - typedef sw_error_t(*hsl_phy_ptp_rtc_time_get) (a_uint32_t dev_id, - a_uint32_t phy_id, fal_ptp_time_t *time); - - typedef sw_error_t(*hsl_phy_ptp_rtc_time_set) (a_uint32_t dev_id, - a_uint32_t phy_id, fal_ptp_time_t *time); - - typedef sw_error_t(*hsl_phy_ptp_pkt_timestamp_get) (a_uint32_t dev_id, - a_uint32_t phy_id, fal_ptp_time_t *time); - - typedef sw_error_t(*hsl_phy_ptp_interrupt_set) (a_uint32_t dev_id, - a_uint32_t phy_id, fal_ptp_interrupt_t *interrupt); - - typedef sw_error_t(*hsl_phy_ptp_trigger_set) (a_uint32_t dev_id, - a_uint32_t phy_id, a_uint32_t trigger_id, - fal_ptp_trigger_t *triger); - - typedef sw_error_t(*hsl_phy_ptp_pps_signal_control_get) (a_uint32_t dev_id, - a_uint32_t phy_id, - fal_ptp_pps_signal_control_t *sig_control); - - typedef sw_error_t(*hsl_phy_ptp_capture_get) (a_uint32_t dev_id, - a_uint32_t phy_id, a_uint32_t capture_id, - fal_ptp_capture_t *capture); - - typedef sw_error_t(*hsl_phy_ptp_rx_crc_recalc_enable) (a_uint32_t dev_id, - a_uint32_t phy_id, a_bool_t status); - - typedef sw_error_t(*hsl_phy_ptp_security_get) (a_uint32_t dev_id, - a_uint32_t phy_id, fal_ptp_security_t *sec); - - typedef sw_error_t(*hsl_phy_ptp_increment_sync_from_clock_status_get) (a_uint32_t dev_id, - a_uint32_t phy_id, a_bool_t *status); - - typedef sw_error_t(*hsl_phy_ptp_tod_uart_get) (a_uint32_t dev_id, - a_uint32_t phy_id, fal_ptp_tod_uart_t *tod_uart); - - typedef sw_error_t(*hsl_phy_ptp_enhanced_timestamp_engine_set) (a_uint32_t dev_id, - a_uint32_t phy_id, fal_ptp_direction_t direction, - fal_ptp_enhanced_ts_engine_t *ts_engine); - - typedef sw_error_t(*hsl_phy_ptp_rtc_time_clear) (a_uint32_t dev_id, - a_uint32_t phy_id); - - typedef sw_error_t(*hsl_phy_ptp_reference_clock_set) (a_uint32_t dev_id, - a_uint32_t phy_id, fal_ptp_reference_clock_t ref_clock); - - typedef sw_error_t(*hsl_phy_ptp_output_waveform_set) (a_uint32_t dev_id, - a_uint32_t phy_id, fal_ptp_output_waveform_t *waveform); - - typedef sw_error_t(*hsl_phy_ptp_rx_timestamp_mode_set) (a_uint32_t dev_id, - a_uint32_t phy_id, fal_ptp_rx_timestamp_mode_t ts_mode); - - typedef sw_error_t(*hsl_phy_ptp_grandmaster_mode_set) (a_uint32_t dev_id, - a_uint32_t phy_id, fal_ptp_grandmaster_mode_t *gm_mode); - - typedef sw_error_t(*hsl_phy_ptp_config_set) (a_uint32_t dev_id, - a_uint32_t phy_id, fal_ptp_config_t *config); - - typedef sw_error_t(*hsl_phy_ptp_trigger_get) (a_uint32_t dev_id, - a_uint32_t phy_id, a_uint32_t trigger_id, - fal_ptp_trigger_t *triger); - - typedef sw_error_t(*hsl_phy_ptp_rtc_adjfreq_get) (a_uint32_t dev_id, - a_uint32_t phy_id, fal_ptp_time_t *time); - - typedef sw_error_t(*hsl_phy_ptp_grandmaster_mode_get) (a_uint32_t dev_id, - a_uint32_t phy_id, fal_ptp_grandmaster_mode_t *gm_mode); - - typedef sw_error_t(*hsl_phy_ptp_rx_timestamp_mode_get) (a_uint32_t dev_id, - a_uint32_t phy_id, fal_ptp_rx_timestamp_mode_t *ts_mode); - - typedef sw_error_t(*hsl_phy_ptp_rtc_adjtime_set) (a_uint32_t dev_id, - a_uint32_t phy_id, fal_ptp_time_t *time); - - typedef sw_error_t(*hsl_phy_ptp_link_delay_get) (a_uint32_t dev_id, - a_uint32_t phy_id, fal_ptp_time_t *time); - - typedef sw_error_t(*hsl_phy_ptp_increment_sync_from_clock_enable) (a_uint32_t dev_id, - a_uint32_t phy_id, a_bool_t status); - - typedef sw_error_t(*hsl_phy_ptp_config_get) (a_uint32_t dev_id, - a_uint32_t phy_id, fal_ptp_config_t *config); - - typedef sw_error_t(*hsl_phy_ptp_output_waveform_get) (a_uint32_t dev_id, - a_uint32_t phy_id, fal_ptp_output_waveform_t *waveform); - - typedef sw_error_t(*hsl_phy_ptp_interrupt_get) (a_uint32_t dev_id, - a_uint32_t phy_id, fal_ptp_interrupt_t *interrupt); - - typedef sw_error_t(*hsl_phy_ptp_rtc_time_snapshot_enable) (a_uint32_t dev_id, - a_uint32_t phy_id, a_bool_t status); - - typedef sw_error_t(*hsl_phy_ptp_reference_clock_get) (a_uint32_t dev_id, - a_uint32_t phy_id, fal_ptp_reference_clock_t *ref_clock); - - typedef struct hsl_phy_ptp_ops_s { - hsl_phy_ptp_security_set phy_ptp_security_set; - hsl_phy_ptp_link_delay_set phy_ptp_link_delay_set; - hsl_phy_ptp_rx_crc_recalc_status_get phy_ptp_rx_crc_recalc_status_get; - hsl_phy_ptp_tod_uart_set phy_ptp_tod_uart_set; - hsl_phy_ptp_enhanced_timestamp_engine_get phy_ptp_enhanced_timestamp_engine_get; - hsl_phy_ptp_pps_signal_control_set phy_ptp_pps_signal_control_set; - hsl_phy_ptp_timestamp_get phy_ptp_timestamp_get; - hsl_phy_ptp_asym_correction_get phy_ptp_asym_correction_get; - hsl_phy_ptp_rtc_time_snapshot_status_get phy_ptp_rtc_time_snapshot_status_get; - hsl_phy_ptp_capture_set phy_ptp_capture_set; - hsl_phy_ptp_rtc_adjfreq_set phy_ptp_rtc_adjfreq_set; - hsl_phy_ptp_asym_correction_set phy_ptp_asym_correction_set; - hsl_phy_ptp_pkt_timestamp_set phy_ptp_pkt_timestamp_set; - hsl_phy_ptp_rtc_time_get phy_ptp_rtc_time_get; - hsl_phy_ptp_rtc_time_set phy_ptp_rtc_time_set; - hsl_phy_ptp_pkt_timestamp_get phy_ptp_pkt_timestamp_get; - hsl_phy_ptp_interrupt_set phy_ptp_interrupt_set; - hsl_phy_ptp_trigger_set phy_ptp_trigger_set; - hsl_phy_ptp_pps_signal_control_get phy_ptp_pps_signal_control_get; - hsl_phy_ptp_capture_get phy_ptp_capture_get; - hsl_phy_ptp_rx_crc_recalc_enable phy_ptp_rx_crc_recalc_enable; - hsl_phy_ptp_security_get phy_ptp_security_get; - hsl_phy_ptp_increment_sync_from_clock_status_get \ - phy_ptp_increment_sync_from_clock_status_get; - hsl_phy_ptp_tod_uart_get phy_ptp_tod_uart_get; - hsl_phy_ptp_enhanced_timestamp_engine_set phy_ptp_enhanced_timestamp_engine_set; - hsl_phy_ptp_rtc_time_clear phy_ptp_rtc_time_clear; - hsl_phy_ptp_reference_clock_set phy_ptp_reference_clock_set; - hsl_phy_ptp_output_waveform_set phy_ptp_output_waveform_set; - hsl_phy_ptp_rx_timestamp_mode_set phy_ptp_rx_timestamp_mode_set; - hsl_phy_ptp_grandmaster_mode_set phy_ptp_grandmaster_mode_set; - hsl_phy_ptp_config_set phy_ptp_config_set; - hsl_phy_ptp_trigger_get phy_ptp_trigger_get; - hsl_phy_ptp_rtc_adjfreq_get phy_ptp_rtc_adjfreq_get; - hsl_phy_ptp_grandmaster_mode_get phy_ptp_grandmaster_mode_get; - hsl_phy_ptp_rx_timestamp_mode_get phy_ptp_rx_timestamp_mode_get; - hsl_phy_ptp_rtc_adjtime_set phy_ptp_rtc_adjtime_set; - hsl_phy_ptp_link_delay_get phy_ptp_link_delay_get; - hsl_phy_ptp_increment_sync_from_clock_enable \ - phy_ptp_increment_sync_from_clock_enable; - hsl_phy_ptp_config_get phy_ptp_config_get; - hsl_phy_ptp_output_waveform_get phy_ptp_output_waveform_get; - hsl_phy_ptp_interrupt_get phy_ptp_interrupt_get; - hsl_phy_ptp_rtc_time_snapshot_enable phy_ptp_rtc_time_snapshot_enable; - hsl_phy_ptp_reference_clock_get phy_ptp_reference_clock_get; - } hsl_phy_ptp_ops_t; - -/*qca808x_start*/ - typedef struct hsl_phy_ops_s { - - hsl_phy_init phy_init; - hsl_phy_hibernation_set phy_hibernation_set; - hsl_phy_hibernation_get phy_hibernation_get; - hsl_phy_speed_get phy_speed_get; - hsl_phy_speed_set phy_speed_set; - hsl_phy_duplex_get phy_duplex_get; - hsl_phy_duplex_set phy_duplex_set; - hsl_phy_autoneg_enable_set phy_autoneg_enable_set; - hsl_phy_autoneg_enable_get phy_autoneg_enable_get; - hsl_phy_restart_autoneg phy_restart_autoneg; - hsl_phy_autoneg_status_get phy_autoneg_status_get; - hsl_phy_autoneg_adv_set phy_autoneg_adv_set; - hsl_phy_autoneg_adv_get phy_autoneg_adv_get; - hsl_phy_powersave_set phy_powersave_set; - hsl_phy_powersave_get phy_powersave_get; - hsl_phy_cdt phy_cdt; - hsl_phy_link_status_get phy_link_status_get; - hsl_phy_get_ability phy_get_ability; - hsl_phy_mdix_set phy_mdix_set; - hsl_phy_mdix_get phy_mdix_get; - hsl_phy_mdix_status_get phy_mdix_status_get; - hsl_phy_8023az_set phy_8023az_set; - hsl_phy_8023az_get phy_8023az_get; - hsl_phy_local_loopback_set phy_local_loopback_set; - hsl_phy_local_loopback_get phy_local_loopback_get; - hsl_phy_remote_loopback_set phy_remote_loopback_set; - hsl_phy_remote_loopback_get phy_remote_loopback_get; - hsl_phy_master_set phy_master_set; - hsl_phy_master_get phy_master_get; -/*qca808x_end*/ - hsl_phy_combo_prefer_medium_set phy_combo_prefer_medium_set; - hsl_phy_combo_prefer_medium_get phy_combo_prefer_medium_get; - hsl_phy_combo_medium_status_get phy_combo_medium_status_get; - hsl_phy_combo_fiber_mode_set phy_combo_fiber_mode_set; - hsl_phy_combo_fiber_mode_get phy_combo_fiber_mode_get; - hsl_phy_function_reset phy_function_reset; -/*qca808x_start*/ - hsl_phy_reset phy_reset; - hsl_phy_power_off phy_power_off; - hsl_phy_power_on phy_power_on; - hsl_phy_reset_status_get phy_reset_status_get; - hsl_phy_id_get phy_id_get; - hsl_phy_reg_write phy_reg_write; - hsl_phy_reg_read phy_reg_read; - hsl_phy_debug_write phy_debug_write; - hsl_phy_debug_read phy_debug_read; - hsl_phy_mmd_write phy_mmd_write; - hsl_phy_mmd_read phy_mmd_read; - hsl_phy_magic_frame_mac_set phy_magic_frame_mac_set; - hsl_phy_magic_frame_mac_get phy_magic_frame_mac_get; - hsl_phy_wol_status_set phy_wol_status_set; - hsl_phy_wol_status_get phy_wol_status_get; - hsl_phy_interface_mode_set phy_interface_mode_set; - hsl_phy_interface_mode_get phy_interface_mode_get; - hsl_phy_interface_mode_status_get phy_interface_mode_status_get; - hsl_phy_intr_mask_set phy_intr_mask_set; - hsl_phy_intr_mask_get phy_intr_mask_get; - hsl_phy_intr_status_get phy_intr_status_get; - hsl_phy_counter_set phy_counter_set; - hsl_phy_counter_get phy_counter_get; - hsl_phy_counter_show phy_counter_show; - hsl_phy_serdes_reset phy_serdes_reset; - hsl_phy_get_status phy_get_status; - hsl_phy_eee_adv_set phy_eee_adv_set; - hsl_phy_eee_adv_get phy_eee_adv_get; - hsl_phy_eee_partner_adv_get phy_eee_partner_adv_get; - hsl_phy_eee_cap_get phy_eee_cap_get; - hsl_phy_eee_status_get phy_eee_status_get; -/*qca808x_end*/ - hsl_phy_led_ctrl_pattern_set phy_led_ctrl_pattern_set; - hsl_phy_led_ctrl_pattern_get phy_led_ctrl_pattern_get; - hsl_phy_led_ctrl_source_set phy_led_ctrl_source_set; - hsl_phy_ptp_ops_t phy_ptp_ops; -/*qca808x_start*/ - } hsl_phy_ops_t; - -typedef struct phy_driver_instance { - a_uint32_t phy_type; - a_uint32_t port_bmp[SW_MAX_NR_DEV]; - hsl_phy_ops_t *phy_ops; - int (*init)(a_uint32_t dev_id, a_uint32_t portbmp); - void (*exit)(a_uint32_t dev_id, a_uint32_t portbmp); -} phy_driver_instance_t; - -typedef enum -{ -/*qca808x_end*/ - F1_PHY_CHIP = 0, - F2_PHY_CHIP, - MALIBU_PHY_CHIP, - AQUANTIA_PHY_CHIP, - QCA803X_PHY_CHIP, - SFP_PHY_CHIP, - MPGE_PHY_CHIP, -/*qca808x_start*/ - QCA808X_PHY_CHIP, - MAX_PHY_CHIP, -} phy_type_t; - -#define PHY_INVALID_DAC 0 - -typedef struct { - a_uint8_t mdac; - a_uint8_t edac; -} phy_dac_t; - -typedef struct { - a_uint32_t phy_address[SW_MAX_NR_PORT]; - a_uint32_t phy_type[SW_MAX_NR_PORT]; - /* fake mdio address is used to register the phy device, - * when the phy is not accessed by the MDIO bus. - * */ - a_uint32_t phy_mdio_fake_address[SW_MAX_NR_PORT]; - a_uint8_t phy_access_type[SW_MAX_NR_PORT]; - a_bool_t phy_c45[SW_MAX_NR_PORT]; - a_bool_t phy_combo[SW_MAX_NR_PORT]; - a_uint32_t phy_reset_gpio[SW_MAX_NR_PORT]; - phy_dac_t phy_dac[SW_MAX_NR_PORT]; -} phy_info_t; -/*qca808x_end*/ -#define MALIBU5PORT_PHY 0x004DD0B1 -#define MALIBU2PORT_PHY 0x004DD0B2 -#define QCA8030_PHY 0x004DD076 -#define QCA8033_PHY 0x004DD074 -#define QCA8035_PHY 0x004DD072 -/*qca808x_start*/ -#define QCA8081_PHY_V1_1 0x004DD101 -#define INVALID_PHY_ID 0xFFFFFFFF - -/*qca808x_end*/ -#define F1V1_PHY 0x004DD033 -#define F1V2_PHY 0x004DD034 -#define F1V3_PHY 0x004DD035 -#define F1V4_PHY 0x004DD036 -#define F2V1_PHY 0x004DD042 -#define AQUANTIA_PHY_107 0x03a1b4e2 -#define AQUANTIA_PHY_108 0x03a1b4f2 -#define AQUANTIA_PHY_109 0x03a1b502 -#define AQUANTIA_PHY_111 0x03a1b610 -#define AQUANTIA_PHY_111B0 0x03a1b612 -#define AQUANTIA_PHY_112 0x03a1b660 -#define AQUANTIA_PHY_113C_A0 0x31c31C10 -#define AQUANTIA_PHY_113C_A1 0x31c31C11 -#define AQUANTIA_PHY_112C 0x03a1b792 - -#define PHY_805XV2 0x004DD082 -#define PHY_805XV1 0x004DD081 -/*qca808x_start*/ -#define SFP_PHY 0xaaaabbbb -/*qca808x_end*/ -#define MP_GEPHY 0x004DD0C0 -#define SFP_PHY_MASK 0xffffffff - -#define CABLE_PAIR_A 0 -#define CABLE_PAIR_B 1 -#define CABLE_PAIR_C 2 -#define CABLE_PAIR_D 3 -/*qca808x_start*/ -#define PHY_MDIO_ACCESS 0 -#define PHY_I2C_ACCESS 1 - -#define INVALID_PHY_ADDR 0xff -#define MAX_PHY_ADDR 0x1f -#define QCA8072_PHY_NUM 0x2 - -#define PHY_INVALID_DATA 0xffff - -#define PHY_RTN_ON_READ_ERROR(phy_data) \ - do { if (phy_data == PHY_INVALID_DATA) return(SW_READ_ERROR); } while(0); - -#define PHY_RTN_ON_ERROR(rv) \ - do { if (rv != SW_OK) return(rv); } while(0); - -sw_error_t -hsl_phy_api_ops_register(phy_type_t phy_type, hsl_phy_ops_t * phy_api_ops); - -sw_error_t -hsl_phy_api_ops_unregister(phy_type_t phy_type, hsl_phy_ops_t * phy_api_ops); - -hsl_phy_ops_t *hsl_phy_api_ops_get(a_uint32_t dev_id, a_uint32_t port_id); - -sw_error_t phy_api_ops_init(phy_type_t phy_type); - -int ssdk_phy_driver_init(a_uint32_t dev_id, ssdk_init_cfg *cfg); - -int qca_ssdk_phy_info_init(a_uint32_t dev_id); - -void qca_ssdk_port_bmp_init(a_uint32_t dev_id); -/*qca808x_end*/ -void hsl_phy_address_init(a_uint32_t dev_id, a_uint32_t i, - a_uint32_t value); -/*qca808x_start*/ -a_uint32_t -hsl_phyid_get(a_uint32_t dev_id, a_uint32_t port_id, ssdk_init_cfg *cfg); - -a_uint32_t -qca_ssdk_port_to_phy_addr(a_uint32_t dev_id, a_uint32_t port_id); -/*qca808x_end*/ -a_uint32_t -qca_ssdk_port_to_phy_mdio_fake_addr(a_uint32_t dev_id, a_uint32_t port_id); - -a_uint32_t -qca_ssdk_phy_mdio_fake_addr_to_port(a_uint32_t dev_id, a_uint32_t phy_addr); - -void qca_ssdk_phy_mdio_fake_address_set(a_uint32_t dev_id, a_uint32_t i, - a_uint32_t value); -/*qca808x_start*/ -void qca_ssdk_port_bmp_set(a_uint32_t dev_id, a_uint32_t value); - -a_uint32_t qca_ssdk_port_bmp_get(a_uint32_t dev_id); -/*qca808x_end*/ -a_uint32_t qca_ssdk_phy_type_port_bmp_get(a_uint32_t dev_id, - phy_type_t phy_type); -/*qca808x_start*/ -a_uint32_t -qca_ssdk_phy_addr_to_port(a_uint32_t dev_id, a_uint32_t phy_addr); -/*qca808x_end*/ -void -hsl_port_phy_c45_capability_set(a_uint32_t dev_id, a_uint32_t port_id, - a_bool_t enable); - -a_bool_t -hsl_port_phy_combo_capability_get(a_uint32_t dev_id, a_uint32_t port_id); - -void -hsl_port_phy_combo_capability_set(a_uint32_t dev_id, a_uint32_t port_id, - a_bool_t enable); -/*qca808x_start*/ -a_uint8_t -hsl_port_phy_access_type_get(a_uint32_t dev_id, a_uint32_t port_id); - -void -hsl_port_phy_access_type_set(a_uint32_t dev_id, a_uint32_t port_id, - a_uint8_t access_type); -/*qca808x_end*/ -sw_error_t -hsl_port_phy_serdes_reset(a_uint32_t dev_id); - -sw_error_t -hsl_port_phy_mode_set(a_uint32_t dev_id, fal_port_interface_mode_t mode); -phy_type_t hsl_phy_type_get(a_uint32_t dev_id, a_uint32_t port_id); - -a_uint32_t -hsl_port_phyid_get(a_uint32_t dev_id, fal_port_t port_id); - -a_uint32_t hsl_port_phy_reset_gpio_get(a_uint32_t dev_id, a_uint32_t port_id); - -void hsl_port_phy_reset_gpio_set(a_uint32_t dev_id, a_uint32_t port_id, - a_uint32_t phy_reset_gpio); - -void hsl_port_phy_gpio_reset(a_uint32_t dev_id, a_uint32_t port_id); - -void -hsl_port_phy_dac_get(a_uint32_t dev_id, a_uint32_t port_id, - phy_dac_t *phy_dac); - -void -hsl_port_phy_dac_set(a_uint32_t dev_id, a_uint32_t port_id, - phy_dac_t phy_dac); -/*qca808x_start*/ -sw_error_t ssdk_phy_driver_cleanup(void); -/*qca808x_end*/ -sw_error_t -hsl_phydriver_update(a_uint32_t dev_id, a_uint32_t port_id, - a_uint32_t mode); - -void -qca_ssdk_phy_address_set(a_uint32_t dev_id, a_uint32_t port_id, - a_uint32_t phy_addr); - -sw_error_t -hsl_port_phy_hw_init(a_uint32_t dev_id, a_uint32_t port_id); - -#if (LINUX_VERSION_CODE >= KERNEL_VERSION(5, 0, 0)) -sw_error_t -hsl_port_phydev_adv_update(a_uint32_t dev_id, a_uint32_t port_id, - a_uint32_t autoadv); -#endif -/*qca808x_start*/ -#ifdef __cplusplus -} -#endif /* __cplusplus */ -#endif /* _HSL_PHY_H_ */ -/*qca808x_end*/ diff --git a/feeds/ipq807x/qca-ssdk/src/include/hsl/phy/malibu_phy.h b/feeds/ipq807x/qca-ssdk/src/include/hsl/phy/malibu_phy.h deleted file mode 100755 index b73540417..000000000 --- a/feeds/ipq807x/qca-ssdk/src/include/hsl/phy/malibu_phy.h +++ /dev/null @@ -1,676 +0,0 @@ -/* - * Copyright (c) 2015, 2017, 2019, The Linux Foundation. All rights reserved. - * Permission to use, copy, modify, and/or distribute this software for - * any purpose with or without fee is hereby granted, provided that the - * above copyright notice and this permission notice appear in all copies. - * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES - * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR - * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES - * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN - * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT - * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. - */ - -#ifndef _MALIBU_PHY_H_ -#define _MALIBU_PHY_H_ - -#ifdef __cplusplus -extern "C" -{ -#endif /* __cplusplus */ - -#define BIT_15 15 -#define BIT_14 14 -#define BIT_13 13 -#define BIT_12 12 -#define BIT_11 11 -#define BIT_10 10 -#define BIT_9 9 -#define BIT_8 8 -#define BIT_7 7 -#define BIT_6 6 -#define BIT_5 5 -#define BIT_4 4 -#define BIT_3 3 -#define BIT_2 2 -#define BIT_1 1 -#define BIT_0 0 -#define COMBO_PHY_ID 4 -#define PSGMII_ID 5 - -#define MALIBU_COMMON_CTRL 0x1040 -#define MALIBU_10M_LOOPBACK 0x4100 -#define MALIBU_100M_LOOPBACK 0x6100 -#define MALIBU_1000M_LOOPBACK 0x4140 - -#define MALIBU_1_0 0x004DD0B0 -#define MALIBU_1_1 0x004DD0B1 -#define MALIBU_1_1_2PORT 0x004DD0B2 -#define MALIBU_ORG_ID_OFFSET_LEN 16 -#define MALIBU_PHY_COPPER_MODE 0x8000 - - /* PHY Registers */ -#define MALIBU_PHY_CONTROL 0 -#define MALIBU_PHY_STATUS 1 -#define MALIBU_PHY_ID1 2 -#define MALIBU_PHY_ID2 3 -#define MALIBU_AUTONEG_ADVERT 4 -#define MALIBU_LINK_PARTNER_ABILITY 5 -#define MALIBU_AUTONEG_EXPANSION 6 -#define MALIBU_NEXT_PAGE_TRANSMIT 7 -#define MALIBU_LINK_PARTNER_NEXT_PAGE 8 -#define MALIBU_1000BASET_CONTROL 9 -#define MALIBU_1000BASET_STATUS 10 -#define MALIBU_MMD_CTRL_REG 13 -#define MALIBU_MMD_DATA_REG 14 -#define MALIBU_EXTENDED_STATUS 15 -#define MALIBU_PHY_SPEC_CONTROL 16 -#define MALIBU_PHY_SPEC_STATUS 17 -#define MALIBU_PHY_INTR_MASK 18 -#define MALIBU_PHY_INTR_STATUS 19 -#define MALIBU_PHY_CDT_CONTROL 22 -#define MALIBU_PHY_CDT_STATUS 28 -#define MALIBU_DEBUG_PORT_ADDRESS 29 -#define MALIBU_DEBUG_PORT_DATA 30 - -#define MALIBU_DEBUG_PHY_HIBERNATION_CTRL 0xb -#define MALIBU_DEBUG_PHY_POWER_SAVING_CTRL 0x29 -#define MALIBU_PHY_MMD7_ADDR_8023AZ_EEE_CTRL 0x3c -#define MALIBU_PHY_MMD7_ADDR_8023AZ_EEE_PARTNER 0x3d -#define MALIBU_PHY_MMD7_ADDR_8023AZ_EEE_STATUS 0x8000 -#define MALIBU_PHY_MMD3_ADDR_8023AZ_EEE_CAPABILITY 0x14 - -#define MALIBU_PHY_MMD3_ADDR_REMOTE_LOOPBACK_CTRL 0x805a -#define MALIBU_PHY_MMD3_WOL_MAGIC_MAC_CTRL1 0x804a -#define MALIBU_PHY_MMD3_WOL_MAGIC_MAC_CTRL2 0x804b -#define MALIBU_PHY_MMD3_WOL_MAGIC_MAC_CTRL3 0x804c -#define MALIBU_PHY_MMD3_WOL_CTRL 0x8012 -#define MALIBU_PHY_MMD3_ADDR_8023AZ_TIMER_CTRL 0x804e -#define MALIBU_PHY_MMD3_ADDR_8023AZ_CLD_CTRL 0x8007 -#define MALIBU_PHY_MMD3_ADDR_CLD_CTRL5 0x8005 -#define MALIBU_PHY_MMD3_ADDR_CLD_CTRL3 0x8003 -#define MALIBU_PHY_MMD7_DAC_CTRL 0x801a -#define MALIBU_DAC_CTRL_MASK 0x380 -#define MALIBU_DAC_CTRL_VALUE 0x280 -#define MALIBU_LED_1000_CTRL1_100_10_MASK 0x30 - -#define MALIBU_PHY_EEE_ADV_100M 0x0002 -#define MALIBU_PHY_EEE_ADV_1000M 0x0004 -#define MALIBU_PHY_EEE_PARTNER_ADV_100M 0x0002 -#define MALIBU_PHY_EEE_PARTNER_ADV_1000M 0x0004 -#define MALIBU_PHY_EEE_CAPABILITY_100M 0x0002 -#define MALIBU_PHY_EEE_CAPABILITY_1000M 0x0004 -#define MALIBU_PHY_EEE_STATUS_100M 0x0002 -#define MALIBU_PHY_EEE_STATUS_1000M 0x0004 - - -#define AZ_TIMER_CTRL_DEFAULT_VALUE 0x3062 -#define AZ_CLD_CTRL_DEFAULT_VALUE 0x83f6 -#define AZ_TIMER_CTRL_ADJUST_VALUE 0x7062 -#define AZ_CLD_CTRL_ADJUST_VALUE 0x8396 - - -#define MALIBU_PHY_MMD7_COUNTER_CTRL 0x8029 -#define MALIBU_PHY_MMD7_INGRESS_COUNTER_HIGH 0x802a -#define MALIBU_PHY_MMD7_INGRESS_COUNTER_LOW 0x802b -#define MALIBU_PHY_MMD7_INGRESS_ERROR_COUNTER 0x802c -#define MALIBU_PHY_MMD7_EGRESS_COUNTER_HIGH 0x802d -#define MALIBU_PHY_MMD7_EGRESS_COUNTER_LOW 0x802e -#define MALIBU_PHY_MMD7_EGRESS_ERROR_COUNTER 0x802f -#define MALIBU_PHY_MMD7_LED_1000_CTRL1 0x8076 - - - -#define MALIBU_PSGMII_FIFI_CTRL 0x6e -#define MALIBU_PSGMII_CALIB_CTRL 0x27 -#define MALIBU_PSGMII_MODE_CTRL 0x6d -#define MALIBU_PSGMII_TX_DRIVER_1_CTRL 0xb - -#define MALIBU_PHY_PSGMII_MODE_CTRL_DEFAULT_VALUE 0x220d -#define MALIBU_PHY_PSGMII_MODE_CTRL_ADJUST_VALUE 0x220c -#define MALIBU_PHY_PSGMII_REDUCE_SERDES_TX_AMP 0x8a - -#define MALIBU_PHY_QSGMII 0x8504 -#define MALIBU_PHY_PSGMII_ADDR_INC 0x5 -#define MALIBU_PHY_MAX_ADDR_INC 0x4 -#define MALIBU_MODE_CHANAGE_RESET 0x0 -#define MALIBU_MODE_RESET_DEFAULT_VALUE 0x5f -#define MALIBU_MODE_RESET_REG 0x0 - -#define MALIBU_PHY_TX_FLOWCTRL_STATUS 0x8 -#define MALIBU_PHY_RX_FLOWCTRL_STATUS 0x4 - - -#define MALIBU_PHY_MMD7_NUM 7 -#define MALIBU_PHY_MMD3_NUM 3 -#define MALIBU_PHY_MMD1_NUM 1 - -#define MALIBU_PHY_SGMII_STATUS 0x1a /* sgmii_status Register */ -#define MALIBU_PHY4_AUTO_SGMII_SELECT 0x40 -#define MALIBU_PHY4_AUTO_COPPER_SELECT 0x20 -#define MALIBU_PHY4_AUTO_BX1000_SELECT 0x10 -#define MALIBU_PHY4_AUTO_FX100_SELECT 0x8 - -#define MALIBU_PHY_CHIP_CONFIG 0x1f /* Chip Configuration Register */ -#define BT_BX_SG_REG_SELECT BIT_15 -#define BT_BX_SG_REG_SELECT_OFFSET 15 -#define BT_BX_SG_REG_SELECT_LEN 1 -#define MALIBU_SG_BX_PAGES 0x0 -#define MALIBU_SG_COPPER_PAGES 0x1 - -#define MALIBU_PHY_PSGMII_BASET 0x0 -#define MALIBU_PHY_PSGMII_BX1000 0x1 -#define MALIBU_PHY_PSGMII_FX100 0x2 -#define MALIBU_PHY_PSGMII_AMDET 0x3 -#define MALIBU_PHY_SGMII_BASET 0x4 - -#define MALIBU_PHY4_PREFER_FIBER 0x400 -#define PHY4_PREFER_COPPER 0x0 -#define PHY4_PREFER_FIBER 0x1 - -#define MALIBU_PHY4_FIBER_MODE_1000BX 0x100 -#define AUTO_100FX_FIBER 0x0 -#define AUTO_1000BX_FIBER 0x1 - -#define MALIBU_PHY_MDIX 0x0020 -#define MALIBU_PHY_MDIX_AUTO 0x0060 -#define MALIBU_PHY_MDIX_STATUS 0x0040 - -#define MODE_CFG_QUAL BIT_4 -#define MODE_CFG_QUAL_OFFSET 4 -#define MODE_CFG_QUAL_LEN 4 - -#define MODE_CFG BIT_0 -#define MODE_CFG_OFFSET 0 -#define MODE_CFG_LEN 4 - -#define MALIBU_MODECTRL_DFLT 0x533 -#define MALIBU_MIICTRL_DFLT 0x140 - - /*debug port */ -#define MALIBU_DEBUG_PORT_RGMII_MODE 18 -#define MALIBU_DEBUG_PORT_RGMII_MODE_EN 0x0008 - -#define MALIBU_DEBUG_PORT_RX_DELAY 0 -#define MALIBU_DEBUG_PORT_RX_DELAY_EN 0x8000 - -#define MALIBU_DEBUG_PORT_TX_DELAY 5 -#define MALIBU_DEBUG_PORT_TX_DELAY_EN 0x0100 - - /* PHY Registers Field */ - - /* Control Register fields offset:0 */ - /* bits 6,13: 10=1000, 01=100, 00=10 */ -#define MALIBU_CTRL_SPEED_MSB 0x0040 - - /* Collision test enable */ -#define MALIBU_CTRL_COLL_TEST_ENABLE 0x0080 - - /* FDX =1, half duplex =0 */ -#define MALIBU_CTRL_FULL_DUPLEX 0x0100 - - /* Restart auto negotiation */ -#define MALIBU_CTRL_RESTART_AUTONEGOTIATION 0x0200 - - /* Isolate PHY from MII */ -#define MALIBU_CTRL_ISOLATE 0x0400 - - /* Power down */ -#define MALIBU_CTRL_POWER_DOWN 0x0800 - - /* Auto Neg Enable */ -#define MALIBU_CTRL_AUTONEGOTIATION_ENABLE 0x1000 - - /* Local Loopback Enable */ -#define MALIBU_LOCAL_LOOPBACK_ENABLE 0x4000 - - /* bits 6,13: 10=1000, 01=100, 00=10 */ -#define MALIBU_CTRL_SPEED_LSB 0x2000 - - /* 0 = normal, 1 = loopback */ -#define MALIBU_CTRL_LOOPBACK 0x4000 -#define MALIBU_CTRL_SOFTWARE_RESET 0x8000 - -#define MALIBU_CTRL_SPEED_MASK 0x2040 -#define MALIBU_CTRL_SPEED_1000 0x0040 -#define MALIBU_CTRL_SPEED_100 0x2000 -#define MALIBU_CTRL_SPEED_10 0x0000 - -#define MALIBU_RESET_DONE(phy_control) \ - (((phy_control) & (MALIBU_CTRL_SOFTWARE_RESET)) == 0) - - /* Status Register fields offset:1 */ - /* Extended register capabilities */ -#define MALIBU_STATUS_EXTENDED_CAPS 0x0001 - - /* Jabber Detected */ -#define MALIBU_STATUS_JABBER_DETECT 0x0002 - - /* Link Status 1 = link */ -#define MALIBU_STATUS_LINK_STATUS_UP 0x0004 - - /* Auto Neg Capable */ -#define MALIBU_STATUS_AUTONEG_CAPS 0x0008 - - /* Remote Fault Detect */ -#define MALIBU_STATUS_REMOTE_FAULT 0x0010 - - /* Auto Neg Complete */ -#define MALIBU_STATUS_AUTO_NEG_DONE 0x0020 - - /* Preamble may be suppressed */ -#define MALIBU_STATUS_PREAMBLE_SUPPRESS 0x0040 - - /* Ext. status info in Reg 0x0F */ -#define MALIBU_STATUS_EXTENDED_STATUS 0x0100 - - /* 100T2 Half Duplex Capable */ -#define MALIBU_STATUS_100T2_HD_CAPS 0x0200 - - /* 100T2 Full Duplex Capable */ -#define MALIBU_STATUS_100T2_FD_CAPS 0x0400 - - /* 10T Half Duplex Capable */ -#define MALIBU_STATUS_10T_HD_CAPS 0x0800 - - /* 10T Full Duplex Capable */ -#define MALIBU_STATUS_10T_FD_CAPS 0x1000 - - /* 100X Half Duplex Capable */ -#define MALIBU_STATUS_100X_HD_CAPS 0x2000 - - /* 100X Full Duplex Capable */ -#define MALIBU_STATUS_100X_FD_CAPS 0x4000 - - /* 100T4 Capable */ -#define MALIBU_STATUS_100T4_CAPS 0x8000 - - /* extended status register capabilities */ - -#define MALIBU_STATUS_1000T_HD_CAPS 0x1000 - -#define MALIBU_STATUS_1000T_FD_CAPS 0x2000 - -#define MALIBU_STATUS_1000X_HD_CAPS 0x4000 - -#define MALIBU_STATUS_1000X_FD_CAPS 0x8000 - -#define MALIBU_AUTONEG_DONE(ip_phy_status) \ - (((ip_phy_status) & (MALIBU_STATUS_AUTO_NEG_DONE)) == \ - (MALIBU_STATUS_AUTO_NEG_DONE)) - - /* PHY identifier1 offset:2 */ -//Organizationally Unique Identifier bits 3:18 - - /* PHY identifier2 offset:3 */ -//Organizationally Unique Identifier bits 19:24 - - /* Auto-Negotiation Advertisement register. offset:4 */ - /* indicates IEEE 802.3 CSMA/CD */ -#define MALIBU_ADVERTISE_SELECTOR_FIELD 0x0001 - - /* 10T Half Duplex Capable */ -#define MALIBU_ADVERTISE_10HALF 0x0020 - - /* 10T Full Duplex Capable */ -#define MALIBU_ADVERTISE_10FULL 0x0040 - - /* 100TX Half Duplex Capable */ -#define MALIBU_ADVERTISE_100HALF 0x0080 - - /* 100TX Full Duplex Capable */ -#define MALIBU_ADVERTISE_100FULL 0x0100 - - /* 100T4 Capable */ -#define MALIBU_ADVERTISE_100T4 0x0200 - - /* Pause operation desired */ -#define MALIBU_ADVERTISE_PAUSE 0x0400 - - /* Asymmetric Pause Direction bit */ -#define MALIBU_ADVERTISE_ASYM_PAUSE 0x0800 - - /* Remote Fault detected */ -#define MALIBU_ADVERTISE_REMOTE_FAULT 0x2000 - - /* Next Page ability supported */ -#define MALIBU_ADVERTISE_NEXT_PAGE 0x8000 - - /* 100TX Half Duplex Capable */ -#define MALIBU_ADVERTISE_1000HALF 0x0100 - - /* 100TX Full Duplex Capable */ -#define MALIBU_ADVERTISE_1000FULL 0x0200 - - /* Extended next page enable control */ -#define MALIBU_EXTENDED_NEXT_PAGE_EN 0x1000 - -#define MALIBU_ADVERTISE_ALL \ - (MALIBU_ADVERTISE_10HALF | MALIBU_ADVERTISE_10FULL | \ - MALIBU_ADVERTISE_100HALF | MALIBU_ADVERTISE_100FULL | \ - MALIBU_ADVERTISE_1000FULL) - -#define MALIBU_ADVERTISE_MEGA_ALL \ - (MALIBU_ADVERTISE_10HALF | MALIBU_ADVERTISE_10FULL | \ - MALIBU_ADVERTISE_100HALF | MALIBU_ADVERTISE_100FULL) - -#define MALIBU_BX_ADVERTISE_1000FULL 0x0020 -#define MALIBU_BX_ADVERTISE_1000HALF 0x0040 -#define MALIBU_BX_ADVERTISE_PAUSE 0x0080 -#define MALIBU_BX_ADVERTISE_ASYM_PAUSE 0x0100 - -#define MALIBU_BX_ADVERTISE_ALL \ - (MALIBU_BX_ADVERTISE_ASYM_PAUSE | MALIBU_BX_ADVERTISE_PAUSE | \ - MALIBU_BX_ADVERTISE_1000HALF | MALIBU_BX_ADVERTISE_1000FULL) - - /* Link Partner ability offset:5 */ - /* Same as advertise selector */ -#define MALIBU_LINK_SLCT 0x001f - - /* Can do 10mbps half-duplex */ -#define MALIBU_LINK_10BASETX_HALF_DUPLEX 0x0020 - - /* Can do 10mbps full-duplex */ -#define MALIBU_LINK_10BASETX_FULL_DUPLEX 0x0040 - - /* Can do 100mbps half-duplex */ -#define MALIBU_LINK_100BASETX_HALF_DUPLEX 0x0080 - - /* Can do 100mbps full-duplex */ -#define MALIBU_LINK_100BASETX_FULL_DUPLEX 0x0100 - - /* Can do 1000mbps full-duplex */ -#define MALIBU_LINK_1000BASETX_FULL_DUPLEX 0x0800 - - /* Can do 1000mbps half-duplex */ -#define MALIBU_LINK_1000BASETX_HALF_DUPLEX 0x0400 - - /* 100BASE-T4 */ -#define MALIBU_LINK_100BASE4 0x0200 - - /* PAUSE */ -#define MALIBU_LINK_PAUSE 0x0400 - - /* Asymmetrical PAUSE */ -#define MALIBU_LINK_ASYPAUSE 0x0800 - - /* Link partner faulted */ -#define MALIBU_LINK_RFAULT 0x2000 - - /* Link partner acked us */ -#define MALIBU_LINK_LPACK 0x4000 - - /* Next page bit */ -#define MALIBU_LINK_NPAGE 0x8000 - - /* Auto-Negotiation Expansion Register offset:6 */ - - /* Next Page Transmit Register offset:7 */ - - /* Link partner Next Page Register offset:8 */ - - /* 1000BASE-T Control Register offset:9 */ - /* Advertise 1000T HD capability */ -#define MALIBU_CTL_1000T_HD_CAPS 0x0100 - - /* Advertise 1000T FD capability */ -#define MALIBU_CTL_1000T_FD_CAPS 0x0200 - - /* 1=Repeater/switch device port 0=DTE device */ -#define MALIBU_CTL_1000T_REPEATER_DTE 0x0400 - - /* 1=Configure PHY as Master 0=Configure PHY as Slave */ -#define MALIBU_CTL_1000T_MS_VALUE 0x0800 - - /* 1=Master/Slave manual config value 0=Automatic Master/Slave config */ -#define MALIBU_CTL_1000T_MS_ENABLE 0x1000 - - /* Normal Operation */ -#define MALIBU_CTL_1000T_TEST_MODE_NORMAL 0x0000 - - /* Transmit Waveform test */ -#define MALIBU_CTL_1000T_TEST_MODE_1 0x2000 - - /* Master Transmit Jitter test */ -#define MALIBU_CTL_1000T_TEST_MODE_2 0x4000 - - /* Slave Transmit Jitter test */ -#define MALIBU_CTL_1000T_TEST_MODE_3 0x6000 - - /* Transmitter Distortion test */ -#define MALIBU_CTL_1000T_TEST_MODE_4 0x8000 -#define MALIBU_CTL_1000T_SPEED_MASK 0x0300 -#define MALIBU_CTL_1000T_DEFAULT_CAP_MASK 0x0300 - - /* 1000BASE-T Status Register offset:10 */ - /* LP is 1000T HD capable */ -#define MALIBU_STATUS_1000T_LP_HD_CAPS 0x0400 - - /* LP is 1000T FD capable */ -#define MALIBU_STATUS_1000T_LP_FD_CAPS 0x0800 - - /* Remote receiver OK */ -#define MALIBU_STATUS_1000T_REMOTE_RX_STATUS 0x1000 - - /* Local receiver OK */ -#define MALIBU_STATUS_1000T_LOCAL_RX_STATUS 0x2000 - - /* 1=Local TX is Master, 0=Slave */ -#define MALIBU_STATUS_1000T_MS_CONFIG_RES 0x4000 - -#define MALIBU_STATUS_1000T_MS_CONFIG_FAULT 0x8000 - - /* Master/Slave config fault */ -#define MALIBU_STATUS_1000T_REMOTE_RX_STATUS_SHIFT 12 -#define MALIBU_STATUS_1000T_LOCAL_RX_STATUS_SHIFT 13 - - /* Phy Specific Control Register offset:16 */ - /* 1=Jabber Function disabled */ -#define MALIBU_CTL_JABBER_DISABLE 0x0001 - - /* 1=Polarity Reversal enabled */ -#define MALIBU_CTL_POLARITY_REVERSAL 0x0002 - - /* 1=SQE Test enabled */ -#define MALIBU_CTL_SQE_TEST 0x0004 -#define MALIBU_CTL_MAC_POWERDOWN 0x0008 - - /* 1=CLK125 low, 0=CLK125 toggling - #define MALIBU_CTL_CLK125_DISABLE 0x0010 - */ - /* MDI Crossover Mode bits 6:5 */ - /* Manual MDI configuration */ -#define MALIBU_CTL_MDI_MANUAL_MODE 0x0000 - - /* Manual MDIX configuration */ -#define MALIBU_CTL_MDIX_MANUAL_MODE 0x0020 - - /* 1000BASE-T: Auto crossover, 100BASE-TX/10BASE-T: MDI Mode */ -#define MALIBU_CTL_AUTO_X_1000T 0x0040 - - /* Auto crossover enabled all speeds */ -#define MALIBU_CTL_AUTO_X_MODE 0x0060 - - /* 1=Enable Extended 10BASE-T distance - * (Lower 10BASE-T RX Threshold) - * 0=Normal 10BASE-T RX Threshold */ -#define MALIBU_CTL_10BT_EXT_DIST_ENABLE 0x0080 - - /* 1=5-Bit interface in 100BASE-TX - * 0=MII interface in 100BASE-TX */ -#define MALIBU_CTL_MII_5BIT_ENABLE 0x0100 - - /* 1=Scrambler disable */ -#define MALIBU_CTL_SCRAMBLER_DISABLE 0x0200 - - /* 1=Force link good */ -#define MALIBU_CTL_FORCE_LINK_GOOD 0x0400 - - /* 1=Assert CRS on Transmit */ -#define MALIBU_CTL_ASSERT_CRS_ON_TX 0x0800 - -#define MALIBU_CTL_POLARITY_REVERSAL_SHIFT 1 -#define MALIBU_CTL_AUTO_X_MODE_SHIFT 5 -#define MALIBU_CTL_10BT_EXT_DIST_ENABLE_SHIFT 7 - - /* Phy Specific status fields offset:17 */ - /* 1=Speed & Duplex resolved */ -#define MALIBU_STATUS_LINK_PASS 0x0400 -#define MALIBU_STATUS_RESOVLED 0x0800 - - /* 1=Duplex 0=Half Duplex */ -#define MALIBU_STATUS_FULL_DUPLEX 0x2000 - - /* Speed, bits 14:15 */ -#define MALIBU_STATUS_SPEED 0xC000 -#define MALIBU_STATUS_SPEED_MASK 0xC000 - - /* 00=10Mbs */ -#define MALIBU_STATUS_SPEED_10MBS 0x0000 - - /* 01=100Mbs */ -#define MALIBU_STATUS_SPEED_100MBS 0x4000 - - /* 10=1000Mbs */ -#define MALIBU_STATUS_SPEED_1000MBS 0x8000 -#define MALIBU_SPEED_DUPLEX_RESOVLED(phy_status) \ - (((phy_status) & \ - (MALIBU_STATUS_RESOVLED)) == \ - (MALIBU_STATUS_RESOVLED)) - - /*phy debug port1 register offset:29 */ - /*phy debug port2 register offset:30 */ - - /*MALIBU interrupt flag */ -#define MALIBU_INTR_SPEED_CHANGE 0x4000 -#define MALIBU_INTR_DUPLEX_CHANGE 0x2000 -#define MALIBU_INTR_STATUS_UP_CHANGE 0x0400 -#define MALIBU_INTR_STATUS_DOWN_CHANGE 0x0800 -#define MALIBU_INTR_BX_FX_STATUS_DOWN_CHANGE 0x0100 -#define MALIBU_INTR_BX_FX_STATUS_UP_CHANGE 0x0080 -#define MALIBU_INTR_MEDIA_STATUS_CHANGE 0x1000 -#define MALIBU_INTR_WOL 0x0001 -#define MALIBU_INTR_POE 0x0002 - -#define RUN_CDT 0x8000 -#define CABLE_LENGTH_UNIT 0x0400 - -/** Phy preferred medium type */ - typedef enum - { - MALIBU_PHY_MEDIUM_COPPER = 0, - /**< Copper */ - MALIBU_PHY_MEDIUM_FIBER = 1, - /**< Fiber */ - - } malibu_phy_medium_t; - -/** Phy pages */ - typedef enum - { - MALIBU_PHY_SGBX_PAGES = 0, - /**< sgbx pages */ - MALIBU_PHY_COPPER_PAGES = 1 - /**< copper pages */ - } malibu_phy_reg_pages_t; -#ifndef IN_PORTCONTROL_MINI - sw_error_t - malibu_phy_set_powersave (a_uint32_t dev_id, a_uint32_t phy_id, - a_bool_t enable); - - sw_error_t - malibu_phy_get_powersave (a_uint32_t dev_id, a_uint32_t phy_id, - a_bool_t * enable); - - sw_error_t - malibu_phy_set_hibernate (a_uint32_t dev_id, a_uint32_t phy_id, - a_bool_t enable); - - sw_error_t - malibu_phy_get_hibernate (a_uint32_t dev_id, a_uint32_t phy_id, - a_bool_t * enable); - - sw_error_t - malibu_phy_cdt (a_uint32_t dev_id, a_uint32_t phy_id, - a_uint32_t mdi_pair, - fal_cable_status_t * cable_status, - a_uint32_t * cable_len); -#endif - sw_error_t - malibu_phy_set_duplex (a_uint32_t dev_id, a_uint32_t phy_id, - fal_port_duplex_t duplex); - - sw_error_t - malibu_phy_get_duplex (a_uint32_t dev_id, a_uint32_t phy_id, - fal_port_duplex_t * duplex); - - sw_error_t - malibu_phy_set_speed (a_uint32_t dev_id, a_uint32_t phy_id, - fal_port_speed_t speed); - - sw_error_t - malibu_phy_get_speed (a_uint32_t dev_id, a_uint32_t phy_id, - fal_port_speed_t * speed); - - sw_error_t - malibu_phy_restart_autoneg (a_uint32_t dev_id, a_uint32_t phy_id); - - sw_error_t - malibu_phy_enable_autoneg (a_uint32_t dev_id, a_uint32_t phy_id); - - a_bool_t - malibu_phy_get_link_status (a_uint32_t dev_id, a_uint32_t phy_id); - - sw_error_t - malibu_phy_set_autoneg_adv (a_uint32_t dev_id, a_uint32_t phy_id, - a_uint32_t autoneg); - - sw_error_t - malibu_phy_get_autoneg_adv (a_uint32_t dev_id, a_uint32_t phy_id, - a_uint32_t * autoneg); - - a_bool_t malibu_phy_autoneg_status (a_uint32_t dev_id, a_uint32_t phy_id); -#ifndef IN_PORTCONTROL_MINI - sw_error_t - malibu_phy_intr_mask_set (a_uint32_t dev_id, a_uint32_t phy_id, - a_uint32_t intr_mask_flag); - - sw_error_t - malibu_phy_intr_mask_get (a_uint32_t dev_id, a_uint32_t phy_id, - a_uint32_t * intr_mask_flag); - - sw_error_t - malibu_phy_intr_status_get (a_uint32_t dev_id, a_uint32_t phy_id, - a_uint32_t * intr_status_flag); - - sw_error_t - malibu_phy_set_counter (a_uint32_t dev_id, a_uint32_t phy_id, - a_bool_t enable); - - sw_error_t - malibu_phy_get_counter (a_uint32_t dev_id, a_uint32_t phy_id, - a_bool_t * enable); - - sw_error_t - malibu_phy_show_counter (a_uint32_t dev_id, a_uint32_t phy_id, - fal_port_counter_info_t * counter_info); -#endif - sw_error_t - malibu_phy_get_8023az(a_uint32_t dev_id, a_uint32_t phy_id, - a_bool_t * enable); -#ifndef IN_PORTCONTROL_MINI - sw_error_t - malibu_phy_set_8023az(a_uint32_t dev_id, a_uint32_t phy_id, - a_bool_t enable); - - sw_error_t - malibu_phy_get_phy_id(a_uint32_t dev_id, a_uint32_t phy_id, - a_uint32_t *phy_data); -#endif - int malibu_phy_init(a_uint32_t dev_id, a_uint32_t port_bmp); - -#ifdef __cplusplus -} -#endif /* __cplusplus */ -#endif /* _MALIBU_PHY_H_ */ diff --git a/feeds/ipq807x/qca-ssdk/src/include/hsl/phy/mpge_led.h b/feeds/ipq807x/qca-ssdk/src/include/hsl/phy/mpge_led.h deleted file mode 100644 index 81d4b5e2c..000000000 --- a/feeds/ipq807x/qca-ssdk/src/include/hsl/phy/mpge_led.h +++ /dev/null @@ -1,41 +0,0 @@ -/* - * Copyright (c) 2020, The Linux Foundation. All rights reserved. - * - * Permission to use, copy, modify, and/or distribute this software for any - * purpose with or without fee is hereby granted, provided that the above - * copyright notice and this permission notice appear in all copies. - * - * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES - * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR - * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES - * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN - * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF - * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. - */ - -#ifndef _MPGE_LED_H_ -#define _MPGE_LED_H_ - -#ifdef __cplusplus -extern "C" -{ -#endif /* __cplusplus */ - -sw_error_t -mpge_phy_led_ctrl_pattern_set(a_uint32_t dev_id, a_uint32_t phy_id, - led_ctrl_pattern_t *pattern); - -sw_error_t -mpge_phy_led_ctrl_pattern_get(a_uint32_t dev_id, a_uint32_t phy_id, - led_ctrl_pattern_t * pattern); - -sw_error_t -mpge_phy_led_ctrl_source_set(a_uint32_t dev_id, a_uint32_t phy_id, - a_uint32_t source_id, led_ctrl_pattern_t * pattern); - -void mpge_phy_led_api_ops_init(hsl_phy_ops_t *mpge_phy_led_api_ops); -#ifdef __cplusplus -} -#endif /* __cplusplus */ -#endif /* _MPGE_LED_H_ */ diff --git a/feeds/ipq807x/qca-ssdk/src/include/hsl/phy/mpge_phy.h b/feeds/ipq807x/qca-ssdk/src/include/hsl/phy/mpge_phy.h deleted file mode 100644 index 7854389d7..000000000 --- a/feeds/ipq807x/qca-ssdk/src/include/hsl/phy/mpge_phy.h +++ /dev/null @@ -1,101 +0,0 @@ -/* - * Copyright (c) 2020, The Linux Foundation. All rights reserved. - * - * Permission to use, copy, modify, and/or distribute this software for any - * purpose with or without fee is hereby granted, provided that the above - * copyright notice and this permission notice appear in all copies. - * - * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES - * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR - * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES - * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN - * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF - * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. - */ - - -#ifndef _MPGE_PHY_H_ -#define _MPGE_PHY_H_ - -#ifdef __cplusplus -extern "C" -{ -#endif /* __cplusplus */ -/*MII register*/ -#define MPGE_PHY_CONTROL 0x0 -#define MPGE_PHY_FIFO_CONTROL 0x19 -#define MPGE_PHY_INTR_MASK 0x12 -#define MPGE_PHY_INTR_STATUS 0x13 - - /*MII register field*/ -#define MPGE_CTRL_AUTONEGOTIATION_ENABLE 0x1000 -#define MPGE_CTRL_RESTART_AUTONEGOTIATION 0x0200 -#define MPGE_CTRL_FULL_DUPLEX 0x0100 -#define MPGE_CONTROL_SPEED_MASK 0x2040 -#define MPGE_CONTROL_100M 0x2000 -#define MPGE_CONTROL_10M 0x0 -#define MPGE_PHY_FIFO_RESET 0x3 -#define MPGE_INTR_SPEED_CHANGE 0x4000 -#define MPGE_INTR_DUPLEX_CHANGE 0x2000 -#define MPGE_INTR_STATUS_LINK_DOWN 0x0800 -#define MPGE_INTR_STATUS_LINK_UP 0x0400 -#define MPGE_INTR_DOWNSHIF 0x0020 -#define MPGE_INTR_WOL 0x0001 -#define MPGE_INTR_FAST_LINK_DOWN_STAT_10M 0x40 -#define MPGE_INTR_FAST_LINK_DOWN_STAT_100M 0x200 -#define MPGE_INTR_FAST_LINK_DOWN_STAT_1000M 0x240 -#define MPGE_COMMON_CTRL 0x1040 -#define MPGE_10M_LOOPBACK 0x4100 -#define MPGE_100M_LOOPBACK 0x6100 -#define MPGE_1000M_LOOPBACK 0x4140 - -/*MMD1 register*/ -#define MPGE_PHY_MMD1_NUM 0x1 -#define MPGE_PHY_MMD1_MSE_THRESH1 0x1000 -#define MPGE_PHY_MMD1_MSE_THRESH2 0x1001 -#define MPGE_PHY_MMD1_DAC 0x8100 -/*MMD1 register field*/ -#define MPGE_PHY_MMD1_MSE_THRESH1_VAL 0xf1 -#define MPGE_PHY_MMD1_MSE_THRESH2_VAL 0x1f6 - -/*MMD3 register*/ -#define MPGE_PHY_MMD3_NUM 0x3 -#define MPGE_PHY_MMD3_AZ_CTRL1 0x8008 -#define MPGE_PHY_MMD3_AZ_CTRL2 0x8009 -#define MPGE_PHY_MMD3_CDT_THRESH_CTRL3 0x8074 -#define MPGE_PHY_MMD3_CDT_THRESH_CTRL4 0x8075 -#define MPGE_PHY_MMD3_CDT_THRESH_CTRL5 0x8076 -#define MPGE_PHY_MMD3_CDT_THRESH_CTRL6 0x8077 -#define MPGE_PHY_MMD3_CDT_THRESH_CTRL7 0x8078 -#define MPGE_PHY_MMD3_CDT_THRESH_CTRL9 0x807a -#define MPGE_PHY_MMD3_CDT_THRESH_CTRL13 0x807e -#define MPGE_PHY_MMD3_CDT_THRESH_CTRL14 0x807f - -/*MMD3 register field*/ -#define MPGE_PHY_MMD3_AZ_CTRL1_VAL 0x7880 -#define MPGE_PHY_MMD3_AZ_CTRL2_VAL 0xc8 -#define MPGE_PHY_MMD3_CDT_THRESH_CTRL3_VAL 0xc040 -#define MPGE_PHY_MMD3_CDT_THRESH_CTRL4_VAL 0xa060 -#define MPGE_PHY_MMD3_CDT_THRESH_CTRL5_VAL 0xc040 -#define MPGE_PHY_MMD3_CDT_THRESH_CTRL6_VAL 0xa060 -#define MPGE_PHY_MMD3_CDT_THRESH_CTRL7_VAL 0xc24c -#define MPGE_PHY_MMD3_CDT_THRESH_CTRL9_VAL 0xc060 -#define MPGE_PHY_MMD3_CDT_THRESH_CTRL13_VAL 0xb060 -#define MPGE_PHY_MMD3_NEAR_ECHO_THRESH_VAL 0x90b0 - -/*debug register*/ -#define MPGE_PHY_DEBUG_EDAC 0x4380 - -/*debug port analog*/ -#define MPGE_PHY_DEBUG_ANA_LDO_EFUSE 0x180 -#define MPGE_PHY_DEBUG_ANA_DAC_FILTER 0xa080 - -#define MPGE_PHY_DEBUG_ANA_LDO_EFUSE_DEFAULT 0x50 - -int mpge_phy_init(a_uint32_t dev_id, a_uint32_t port_bmp); - -#ifdef __cplusplus -} -#endif /* __cplusplus */ -#endif /* _MPGE_PHY_H_ */ diff --git a/feeds/ipq807x/qca-ssdk/src/include/hsl/phy/qca803x_phy.h b/feeds/ipq807x/qca-ssdk/src/include/hsl/phy/qca803x_phy.h deleted file mode 100755 index 33013cc7d..000000000 --- a/feeds/ipq807x/qca-ssdk/src/include/hsl/phy/qca803x_phy.h +++ /dev/null @@ -1,425 +0,0 @@ -/* - * Copyright (c) 2017, 2019, The Linux Foundation. All rights reserved. - * Permission to use, copy, modify, and/or distribute this software for - * any purpose with or without fee is hereby granted, provided that the - * above copyright notice and this permission notice appear in all copies. - * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES - * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR - * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES - * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN - * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT - * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. - */ - -#ifndef _QCA803X_PHY_H_ -#define _QCA803X_PHY_H_ - -#ifdef __cplusplus -extern "C" -{ -#endif /* __cplusplus */ - -#define QCA803X_COMMON_CTRL 0x1040 -#define QCA803X_10M_LOOPBACK 0x4100 -#define QCA803X_100M_LOOPBACK 0x6100 -#define QCA803X_1000M_LOOPBACK 0x4140 - - /* PHY Registers */ -#define QCA803X_PHY_CONTROL 0 -#define QCA803X_PHY_STATUS 1 -#define QCA803X_PHY_SPEC_STATUS 17 - -#define QCA803X_PHY_ID1 2 -#define QCA803X_PHY_ID2 3 -#define QCA803X_AUTONEG_ADVERT 4 -#define QCA803X_LINK_PARTNER_ABILITY 5 -#define QCA803X_1000BASET_CONTROL 9 -#define QCA803X_1000BASET_STATUS 10 -#define QCA803X_MMD_CTRL_REG 13 -#define QCA803X_MMD_DATA_REG 14 -#define QCA803X_EXTENDED_STATUS 15 -#define QCA803X_PHY_SPEC_CONTROL 16 -#define QCA803X_PHY_INTR_MASK 18 -#define QCA803X_PHY_INTR_STATUS 19 -#define QCA803X_PHY_CDT_CONTROL 22 -#define QCA803X_PHY_CDT_STATUS 28 -#define QCA803X_DEBUG_PORT_ADDRESS 29 -#define QCA803X_DEBUG_PORT_DATA 30 -#define QCA803X_PHY_CHIP_CONFIG 31 /* Chip Configuration Register */ -#define QCA803X_DEBUG_MSE_THRESH 27 -#define QCA803X_DEBUG_MSE_OVER_THRESH_TIMES 28 - -#define QCA803X_PHY_MSE_THRESH_MASK 0x3f8 -#define QCA803X_PHY_MSE_THRESH_LINK_DOWN 0x170 -#define QCA803X_PHY_MSE_THRESH_LINK_UP 0x2e8 -#define QCA803X_PHY_MSE_OVER_THRESH_TIMES_MAX 0x7000 - -#define QCA803X_PHY_FIBER_MODE_1000BX 0x100 - -#define QCA803X_PHY_COPPER_PAGE_SEL 0x8000 -#define QCA803X_PHY_PREFER_FIBER 0x400 - -#define QCA803X_PHY_CHIP_MODE_CFG 0x000f -#define QCA803X_PHY_CHIP_MODE_STAT 0x00f0 - -#define QCA803X_DEBUG_PHY_HIBERNATION_CTRL 0xb -#define QCA803X_DEBUG_PHY_POWER_SAVING_CTRL 0x29 -#define QCA803X_PHY_MMD7_ADDR_8023AZ_EEE_CTRL 0x3c -#define QCA803X_PHY_MMD7_ADDR_8023AZ_EEE_PARTNER 0x3d -#define QCA803X_PHY_MMD7_ADDR_8023AZ_EEE_STATUS 0x8000 -#define QCA803X_PHY_MMD3_ADDR_8023AZ_EEE_CAPABILITY 0x14 - -#define QCA803X_PHY_MMD3_ADDR_REMOTE_LOOPBACK_CTRL 0x805a -#define QCA803X_PHY_MMD3_WOL_MAGIC_MAC_CTRL1 0x804a -#define QCA803X_PHY_MMD3_WOL_MAGIC_MAC_CTRL2 0x804b -#define QCA803X_PHY_MMD3_WOL_MAGIC_MAC_CTRL3 0x804c -#define QCA803X_PHY_MMD3_WOL_CTRL 0x8012 -#define QCA803X_PHY_MMD3_ADDR_8023AZ_TIMER_CTRL 0x804e -#define QCA803X_PHY_MMD3_ADDR_8023AZ_CLD_CTRL 0x8007 -#define QCA803X_PHY_MMD3_ADDR_CLD_CTRL5 0x8005 -#define QCA803X_PHY_MMD3_ADDR_CLD_CTRL3 0x8003 - -#define QCA803X_PHY_MDIX 0x0020 -#define QCA803X_PHY_MDIX_AUTO 0x0060 -#define QCA803X_PHY_MDIX_STATUS 0x0040 - -#define QCA803X_PHY_MMD7_NUM 7 -#define QCA803X_PHY_MMD3_NUM 3 - -#define QCA803X_PWR_SAVE 0x29 -#define QCA803X_PWR_SAVE_EN 0x8000 - -#define QCA803X_PHY_EEE_ADV_100M 0x0002 -#define QCA803X_PHY_EEE_ADV_1000M 0x0004 -#define QCA803X_PHY_EEE_PARTNER_ADV_100M 0x0002 -#define QCA803X_PHY_EEE_PARTNER_ADV_1000M 0x0004 -#define QCA803X_PHY_EEE_CAPABILITY_100M 0x0002 -#define QCA803X_PHY_EEE_CAPABILITY_1000M 0x0004 -#define QCA803X_PHY_EEE_STATUS_100M 0x0002 -#define QCA803X_PHY_EEE_STATUS_1000M 0x0004 - - /* CDT */ -#define QCA803X_MDI_PAIR_NUM 4 -#define QCA803X_RUN_CDT 0x1 -#define CDT_PAIR_MASK 0x0300 - - /* PHY Registers Field */ -#define QCA803X_STATUS_LINK_PASS 0x0400 - - /* Control Register fields offset:0 */ - /* bits 6,13: 10=1000, 01=100, 00=10 */ -#define QCA803X_CTRL_SPEED_MSB 0x0040 - - /* Collision test enable */ -#define QCA803X_CTRL_COLL_TEST_ENABLE 0x0080 - - /* FDX =1, half duplex =0 */ -#define QCA803X_CTRL_FULL_DUPLEX 0x0100 - - /* Restart auto negotiation */ -#define QCA803X_CTRL_RESTART_AUTONEGOTIATION 0x0200 - - /* Power down */ -#define QCA803X_CTRL_POWER_DOWN 0x0800 - - /* Auto Neg Enable */ -#define QCA803X_CTRL_AUTONEGOTIATION_ENABLE 0x1000 - - /* Local Loopback Enable */ -#define QCA803X_LOCAL_LOOPBACK_ENABLE 0x4000 - - /* bits 6,13: 10=1000, 01=100, 00=10 */ -#define QCA803X_CTRL_SPEED_LSB 0x2000 - - /* 0 = normal, 1 = loopback */ -#define QCA803X_CTRL_LOOPBACK 0x4000 -#define QCA803X_CTRL_SOFTWARE_RESET 0x8000 - -#define QCA803X_CTRL_SPEED_MASK 0x2040 -#define QCA803X_CTRL_SPEED_1000 0x0040 -#define QCA803X_CTRL_SPEED_100 0x2000 -#define QCA803X_CTRL_SPEED_10 0x0000 - -#define QCA803X_RESET_DONE(phy_control) \ - (((phy_control) & (QCA803X_CTRL_SOFTWARE_RESET)) == 0) - - /* Status Register fields offset:1 */ -#define QCA803X_STATUS_EXTENDED_CAPS 0x0001 - - /* Jabber Detected */ -#define QCA803X_STATUS_JABBER_DETECT 0x0002 - - /* Link Status 1 = link */ -#define QCA803X_STATUS_LINK_STATUS_UP 0x0004 - - /* Auto Neg Capable */ -#define QCA803X_STATUS_AUTONEG_CAPS 0x0008 - - /* Remote Fault Detect */ -#define QCA803X_STATUS_REMOTE_FAULT 0x0010 - - /* Auto Neg Complete */ -#define QCA803X_STATUS_AUTO_NEG_DONE 0x0020 - - /* Preamble may be suppressed */ -#define QCA803X_STATUS_PREAMBLE_SUPPRESS 0x0040 - - /* Ext. status info in Reg 0x0F */ -#define QCA803X_STATUS_EXTENDED_STATUS 0x0100 - - /* 100T2 Half Duplex Capable */ -#define QCA803X_STATUS_100T2_HD_CAPS 0x0200 - - /* 100T2 Full Duplex Capable */ -#define QCA803X_STATUS_100T2_FD_CAPS 0x0400 - - /* 10T Half Duplex Capable */ -#define QCA803X_STATUS_10T_HD_CAPS 0x0800 - - /* 10T Full Duplex Capable */ -#define QCA803X_STATUS_10T_FD_CAPS 0x1000 - - /* 100X Half Duplex Capable */ -#define QCA803X_STATUS_100X_HD_CAPS 0x2000 - - /* 100X Full Duplex Capable */ -#define QCA803X_STATUS_100X_FD_CAPS 0x4000 - - /* 100T4 Capable */ -#define QCA803X_STATUS_100T4_CAPS 0x8000 - - /* extended status register capabilities */ - -#define QCA803X_STATUS_1000T_HD_CAPS 0x1000 - -#define QCA803X_STATUS_1000T_FD_CAPS 0x2000 - -#define QCA803X_STATUS_1000X_HD_CAPS 0x4000 - -#define QCA803X_STATUS_1000X_FD_CAPS 0x8000 - - /* Link Partner ability offset:5 */ -#define QCA803X_LINK_SLCT 0x001f - - /* Can do 10mbps half-duplex */ -#define QCA803X_LINK_10BASETX_HALF_DUPLEX 0x0020 - - /* Can do 10mbps full-duplex */ -#define QCA803X_LINK_10BASETX_FULL_DUPLEX 0x0040 - - /* Can do 100mbps half-duplex */ -#define QCA803X_LINK_100BASETX_HALF_DUPLEX 0x0080 - - /* Can do 100mbps full-duplex */ -#define QCA803X_LINK_100BASETX_FULL_DUPLEX 0x0100 - - /* Can do 1000mbps full-duplex */ -#define QCA803X_LINK_1000BASETX_FULL_DUPLEX 0x0800 - - /* Can do 1000mbps half-duplex */ -#define QCA803X_LINK_1000BASETX_HALF_DUPLEX 0x0400 - - /* 100BASE-T4 */ -#define QCA803X_LINK_100BASE4 0x0200 - - /* PAUSE */ -#define QCA803X_LINK_PAUSE 0x0400 - - /* Asymmetrical PAUSE */ -#define QCA803X_LINK_ASYPAUSE 0x0800 - - /* Link partner faulted */ -#define QCA803X_LINK_RFAULT 0x2000 - - /* Link partner acked us */ -#define QCA803X_LINK_LPACK 0x4000 - - /* Next page bit */ -#define QCA803X_LINK_NPAGE 0x8000 - - /* Auto Neg Complete */ -#define QCA803X_STATUS_AUTO_NEG_DONE 0x0020 -#define QCA803X_AUTONEG_DONE(ip_phy_status) \ - (((ip_phy_status) & (QCA803X_STATUS_AUTO_NEG_DONE)) == \ - (QCA803X_STATUS_AUTO_NEG_DONE)) - -#define QCA803X_STATUS_RESOVLED 0x0800 -#define QCA803X_SPEED_DUPLEX_RESOVLED(phy_status) \ - (((phy_status) & \ - (QCA803X_STATUS_RESOVLED)) == \ - (QCA803X_STATUS_RESOVLED)) - - /* Auto-Negotiation Advertisement register. offset:4 */ -#define QCA803X_ADVERTISE_SELECTOR_FIELD 0x0001 - - /* 10T Half Duplex Capable */ -#define QCA803X_ADVERTISE_10HALF 0x0020 - - /* 10T Full Duplex Capable */ -#define QCA803X_ADVERTISE_10FULL 0x0040 - - /* 100TX Half Duplex Capable */ -#define QCA803X_ADVERTISE_100HALF 0x0080 - - /* 100TX Full Duplex Capable */ -#define QCA803X_ADVERTISE_100FULL 0x0100 - - /* 100T4 Capable */ -#define QCA803X_ADVERTISE_100T4 0x0200 - - /* Pause operation desired */ -#define QCA803X_ADVERTISE_PAUSE 0x0400 - - /* Asymmetric Pause Direction bit */ -#define QCA803X_ADVERTISE_ASYM_PAUSE 0x0800 - - /* Remote Fault detected */ -#define QCA803X_ADVERTISE_REMOTE_FAULT 0x2000 - - /* 100TX Half Duplex Capable */ -#define QCA803X_ADVERTISE_1000HALF 0x0100 - - /* 100TX Full Duplex Capable */ -#define QCA803X_ADVERTISE_1000FULL 0x0200 - - /* Extended next page enable control */ -#define QCA803X_EXTENDED_NEXT_PAGE_EN 0x1000 - -#define QCA803X_ADVERTISE_ALL \ - (QCA803X_ADVERTISE_10HALF | QCA803X_ADVERTISE_10FULL | \ - QCA803X_ADVERTISE_100HALF | QCA803X_ADVERTISE_100FULL | \ - QCA803X_ADVERTISE_1000FULL) - -#define QCA803X_ADVERTISE_MEGA_ALL \ - (QCA803X_ADVERTISE_10HALF | QCA803X_ADVERTISE_10FULL | \ - QCA803X_ADVERTISE_100HALF | QCA803X_ADVERTISE_100FULL | \ - QCA803X_ADVERTISE_PAUSE | QCA803X_ADVERTISE_ASYM_PAUSE) - -#define QCA803X_BX_ADVERTISE_1000FULL 0x0020 -#define QCA803X_BX_ADVERTISE_1000HALF 0x0040 -#define QCA803X_BX_ADVERTISE_PAUSE 0x0080 -#define QCA803X_BX_ADVERTISE_ASYM_PAUSE 0x0100 - -#define QCA803X_BX_ADVERTISE_ALL \ - (QCA803X_BX_ADVERTISE_ASYM_PAUSE | QCA803X_BX_ADVERTISE_PAUSE | \ - QCA803X_BX_ADVERTISE_1000HALF | QCA803X_BX_ADVERTISE_1000FULL) - - /* 1=Duplex 0=Half Duplex */ -#define QCA803X_STATUS_FULL_DUPLEX 0x2000 - - /* Speed, bits 14:15 */ -#define QCA803X_STATUS_SPEED 0xC000 -#define QCA803X_STATUS_SPEED_MASK 0xC000 - - /* 00=10Mbs */ -#define QCA803X_STATUS_SPEED_10MBS 0x0000 - - /* 01=100Mbs */ -#define QCA803X_STATUS_SPEED_100MBS 0x4000 - - /* 10=1000Mbs */ -#define QCA803X_STATUS_SPEED_1000MBS 0x8000 - - /*pause status */ -#define QCA803X_PHY_RX_FLOWCTRL_STATUS 0x4 -#define QCA803X_PHY_TX_FLOWCTRL_STATUS 0x8 - - /*QCA803X interrupt flag */ -#define QCA803X_INTR_SPEED_CHANGE 0x4000 -#define QCA803X_INTR_DUPLEX_CHANGE 0x2000 -#define QCA803X_INTR_STATUS_UP_CHANGE 0x0400 -#define QCA803X_INTR_STATUS_DOWN_CHANGE 0x0800 -#define QCA803X_INTR_BX_FX_STATUS_DOWN_CHANGE 0x0100 -#define QCA803X_INTR_BX_FX_STATUS_UP_CHANGE 0x0080 -#define QCA803X_INTR_MEDIA_STATUS_CHANGE 0x1000 -#define QCA803X_INTR_WOL 0x0001 -#define QCA803X_INTR_POE 0x0002 - -/*QCA803X phy counter*/ -#define QCA803X_PHY_MMD7_FRAME_CTRL 0x8020 -#define QCA803X_PHY_MMD7_FRAME_DATA 0x8021 - -#define QCA803X_PHY_MMD7_FRAME_CHECK 0x2000 -#define QCA803X_PHY_MMD7_FRAME_DIR 0x4000 -#define QCA803X_PHY_FRAME_CNT 0x00FF -#define QCA803X_PHY_FRAME_ERROR 0xFF00 - - /** phy chip config */ - typedef enum { - QCA803X_PHY_RGMII_BASET = 0, - QCA803X_PHY_SGMII_BASET = 1, - QCA803X_PHY_BX1000_RGMII_50 = 2, - QCA803X_PHY_FX100_RGMII_50 = 6, - QCA803X_PHY_RGMII_AMDET = 11 - } qca803x_cfg_t; - - typedef enum { - QCA803X_CHIP_CFG_SET, - QCA803X_CHIP_CFG_STAT - } qca803x_cfg_type_t; - -/** Phy preferred medium type */ - typedef enum - { - QCA803X_PHY_MEDIUM_COPPER = 0, /* Copper */ - QCA803X_PHY_MEDIUM_FIBER = 1, /* Fiber */ - QCA803X_PHY_MEDIUM_MAX - } qca803x_phy_medium_t; - -sw_error_t -qca803x_phy_set_duplex (a_uint32_t dev_id, a_uint32_t phy_id, - fal_port_duplex_t duplex); - -sw_error_t -qca803x_phy_get_duplex (a_uint32_t dev_id, a_uint32_t phy_id, - fal_port_duplex_t * duplex); - -sw_error_t -qca803x_phy_set_speed (a_uint32_t dev_id, a_uint32_t phy_id, - fal_port_speed_t speed); - -sw_error_t -qca803x_phy_get_speed (a_uint32_t dev_id, a_uint32_t phy_id, - fal_port_speed_t * speed); - -sw_error_t -qca803x_phy_restart_autoneg (a_uint32_t dev_id, a_uint32_t phy_id); - -sw_error_t -qca803x_phy_enable_autoneg (a_uint32_t dev_id, a_uint32_t phy_id); - -a_bool_t -qca803x_phy_get_link_status (a_uint32_t dev_id, a_uint32_t phy_id); - -sw_error_t -qca803x_phy_set_autoneg_adv (a_uint32_t dev_id, a_uint32_t phy_id, - a_uint32_t autoneg); - -sw_error_t -qca803x_phy_get_autoneg_adv (a_uint32_t dev_id, a_uint32_t phy_id, - a_uint32_t * autoneg); - -a_bool_t qca803x_phy_autoneg_status (a_uint32_t dev_id, a_uint32_t phy_id); -#ifndef IN_PORTCONTROL_MINI -sw_error_t -qca803x_phy_intr_mask_set (a_uint32_t dev_id, a_uint32_t phy_id, - a_uint32_t intr_mask_flag); - -sw_error_t -qca803x_phy_intr_mask_get (a_uint32_t dev_id, a_uint32_t phy_id, - a_uint32_t * intr_mask_flag); - -sw_error_t -qca803x_phy_intr_status_get (a_uint32_t dev_id, a_uint32_t phy_id, - a_uint32_t * intr_status_flag); -#endif -sw_error_t -qca803x_phy_get_phy_id(a_uint32_t dev_id, a_uint32_t phy_id, - a_uint32_t *phy_data); -int qca803x_phy_init(a_uint32_t dev_id, a_uint32_t port_bmp); - -#ifdef __cplusplus -} -#endif /* __cplusplus */ -#endif /* _qca803x_PHY_H_ */ diff --git a/feeds/ipq807x/qca-ssdk/src/include/hsl/phy/qca808x.h b/feeds/ipq807x/qca-ssdk/src/include/hsl/phy/qca808x.h deleted file mode 100755 index 12fb3f4d9..000000000 --- a/feeds/ipq807x/qca-ssdk/src/include/hsl/phy/qca808x.h +++ /dev/null @@ -1,135 +0,0 @@ -/* - * Copyright (c) 2018, The Linux Foundation. All rights reserved. - * Permission to use, copy, modify, and/or distribute this software for - * any purpose with or without fee is hereby granted, provided that the - * above copyright notice and this permission notice appear in all copies. - * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES - * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR - * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES - * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN - * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT - * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. - */ - -#include -#include -#include -#include - -#include "hsl.h" -#include "ssdk_plat.h" -#include "hsl_phy.h" -#include "qca808x_phy.h" - -#if defined(IN_LINUX_STD_PTP) -#include -enum { - PTP_PKT_SEQID_UNMATCHED, - PTP_PKT_SEQID_MATCHED, - PTP_PKT_SEQID_MATCH_MAX -}; - -enum { - QCA808X_PTP_MSG_SYNC, - QCA808X_PTP_MSG_DREQ, - QCA808X_PTP_MSG_PREQ, - QCA808X_PTP_MSG_PRESP, - QCA808X_PTP_MSG_MAX -}; - -typedef struct { - /* ptp filter class */ - a_int32_t ptp_type; - /* ptp frame type */ - a_int32_t pkt_type; -} qca808x_ptp_cb; - -/* statistics for the event packet*/ -typedef struct { - /* the counter saves the packet with sequence id - * matched and unmatched */ - a_uint64_t sync_cnt[PTP_PKT_SEQID_MATCH_MAX]; - a_uint64_t delay_req_cnt[PTP_PKT_SEQID_MATCH_MAX]; - a_uint64_t pdelay_req_cnt[PTP_PKT_SEQID_MATCH_MAX]; - a_uint64_t pdelay_resp_cnt[PTP_PKT_SEQID_MATCH_MAX]; - a_uint64_t event_pkt_cnt; -} ptp_packet_stat; - -typedef struct { - a_uint8_t reserved0; - a_uint8_t reserved1; - a_uint8_t msg_type; - a_uint16_t seqid; - a_uint32_t reserved2; - a_int64_t correction; -} qca808x_embeded_ts; - -struct qca808x_ptp_info { - a_int32_t hwts_tx_type; - a_int32_t hwts_rx_type; - struct qca808x_ptp_clock *clock; - struct delayed_work tx_ts_work; - struct delayed_work rx_ts_work; - /* work for writing ingress time to register */ - struct delayed_work ingress_trig_work; - a_int32_t ingress_time; - struct sk_buff_head tx_queue; - struct sk_buff_head rx_queue; - qca808x_embeded_ts embeded_ts; -}; -#endif - -struct qca808x_phy_info { - struct list_head list; - a_uint32_t dev_id; - /* phy real address,it is the mdio addr or the i2c slave addr */ - a_uint32_t phy_addr; - /* the address of phy device, it is a fake addr for the i2c accessed phy */ - a_uint32_t phydev_addr; -#if defined(IN_LINUX_STD_PTP) - a_int32_t speed; - a_uint16_t clock_mode; - a_uint16_t step_mode; - /* work for gps sencond sync */ - struct delayed_work ts_schedule_work; - a_bool_t gps_seconds_sync_en; - /*the statistics array records the counter of - * rx and tx ptp event packet */ - ptp_packet_stat pkt_stat[2]; -#endif -}; - -typedef struct { - struct phy_device *phydev; - struct qca808x_phy_info *phy_info; -#if defined(IN_LINUX_STD_PTP) - struct qca808x_ptp_info ptp_info; -#endif -} qca808x_priv; - -#if defined(IN_LINUX_STD_PTP) -struct qca808x_ptp_clock{ - struct ptp_clock_info caps; - struct ptp_clock *ptp_clock; - struct mutex tsreg_lock; - qca808x_priv *priv; -}; - -struct qca808x_phy_info* qca808x_phy_info_get(a_uint32_t phy_addr); -void qca808x_ptp_change_notify(struct phy_device *phydev); -int qca808x_hwtstamp(struct phy_device *phydev, struct ifreq *ifr); -bool qca808x_rxtstamp(struct phy_device *phydev, struct sk_buff *skb, int type); -void qca808x_txtstamp(struct phy_device *phydev, struct sk_buff *skb, int type); -#if (LINUX_VERSION_CODE >= KERNEL_VERSION(4,4,0)) -int qca808x_ts_info(struct phy_device *phydev, struct ethtool_ts_info *info); -#endif -sw_error_t qca808x_ptp_config_init(struct phy_device *phydev); -int qca808x_ptp_init(qca808x_priv *priv); -void qca808x_ptp_deinit(qca808x_priv *priv); -#endif - -void qca808x_phydev_init(a_uint32_t dev_id, a_uint32_t port_id); -void qca808x_phydev_deinit(a_uint32_t dev_id, a_uint32_t port_id); -a_int32_t qca808x_phy_driver_register(void); -void qca808x_phy_driver_unregister(void); diff --git a/feeds/ipq807x/qca-ssdk/src/include/hsl/phy/qca808x_led.h b/feeds/ipq807x/qca-ssdk/src/include/hsl/phy/qca808x_led.h deleted file mode 100644 index 8991b09d4..000000000 --- a/feeds/ipq807x/qca-ssdk/src/include/hsl/phy/qca808x_led.h +++ /dev/null @@ -1,52 +0,0 @@ -/* - * Copyright (c) 2020, The Linux Foundation. All rights reserved. - * - * Permission to use, copy, modify, and/or distribute this software for any - * purpose with or without fee is hereby granted, provided that the above - * copyright notice and this permission notice appear in all copies. - * - * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES - * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR - * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES - * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN - * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF - * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. - */ - -#ifndef _QCA808X_LED_H_ -#define _QCA808X_LED_H_ - -#ifdef __cplusplus -extern "C" -{ -#endif /* __cplusplus */ -#define QCA808X_PHY_MMD7_LED_POLARITY_MASK 0x40 -#define QCA808X_PHY_LINK_2500M_LIGHT_EN 0x8000 -#define QCA808X_PHY_LINK_1000M_LIGHT_EN 0x40 -#define QCA808X_PHY_LINK_100M_LIGHT_EN 0x20 -#define QCA808X_PHY_LINK_10M_LIGHT_EN 0x10 -#define QCA808X_PHY_RX_TRAFFIC_BLINK_EN 0x200 -#define QCA808X_PHY_TX_TRAFFIC_BLINK_EN 0x400 - -#define QCA808X_PHY_LED_SOURCE0 0x0 -#define QCA808X_PHY_LED_SOURCE1 0x1 -#define QCA808X_PHY_LED_SOURCE2 0x2 - -sw_error_t -qca808x_phy_led_ctrl_pattern_set(a_uint32_t dev_id, a_uint32_t phy_id, - led_ctrl_pattern_t *pattern); -sw_error_t -qca808x_phy_led_ctrl_pattern_get(a_uint32_t dev_id, a_uint32_t phy_id, - led_ctrl_pattern_t *pattern); -sw_error_t -qca808x_phy_led_ctrl_source_set(a_uint32_t dev_id, a_uint32_t phy_id, - a_uint32_t source_id, led_ctrl_pattern_t *pattern); -sw_error_t -qca808x_phy_led_ctrl_source_get(a_uint32_t dev_id, a_uint32_t phy_id, - a_uint32_t source_id, led_ctrl_pattern_t *pattern); -void qca808x_phy_led_api_ops_init(hsl_phy_ops_t *qca808x_phy_led_api_ops); -#ifdef __cplusplus -} -#endif /* __cplusplus */ -#endif /* _qca808x_LED_H_ */ diff --git a/feeds/ipq807x/qca-ssdk/src/include/hsl/phy/qca808x_phy.h b/feeds/ipq807x/qca-ssdk/src/include/hsl/phy/qca808x_phy.h deleted file mode 100644 index 41c5f66e5..000000000 --- a/feeds/ipq807x/qca-ssdk/src/include/hsl/phy/qca808x_phy.h +++ /dev/null @@ -1,630 +0,0 @@ -/* - * Copyright (c) 2018, 2020, The Linux Foundation. All rights reserved. - * Permission to use, copy, modify, and/or distribute this software for - * any purpose with or without fee is hereby granted, provided that the - * above copyright notice and this permission notice appear in all copies. - * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES - * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR - * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES - * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN - * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT - * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. - */ - -#ifndef _QCA808X_PHY_H_ -#define _QCA808X_PHY_H_ - -#ifdef __cplusplus -extern "C" -{ -#endif /* __cplusplus */ - -#define QCA808X_MII_ADDR_C45 (1<<30) -#define QCA808X_REG_C45_ADDRESS(dev_type, reg_num) (QCA808X_MII_ADDR_C45 | \ - ((dev_type & 0x1f) << 16) | (reg_num & 0xffff)) - -#define QCA808X_COMMON_CTRL 0x1040 - -#define QCA808X_PHY_MMD1_PMA_CONTROL 0x0 -#define QCA808X_PMA_CONTROL_SPEED_MASK 0x2040 -#define QCA808X_PMA_CONTROL_2500M 0x2040 -#define QCA808X_PMA_CONTROL_1000M 0x40 -#define QCA808X_PMA_CONTROL_100M 0x2000 -#define QCA808X_PMA_CONTROL_10M 0x0 - -#define QCA808X_PHY_MMD1_PMA_TYPE 0x7 -#define QCA808X_PMA_TYPE_MASK 0x3f -#define QCA808X_PMA_TYPE_2500M 0x30 -#define QCA808X_PMA_TYPE_1000M 0xc -#define QCA808X_PMA_TYPE_100M 0xe -#define QCA808X_PMA_TYPE_10M 0xf - - /* PHY Registers */ -#define QCA808X_PHY_CONTROL 0 -#define QCA808X_PHY_STATUS 1 -#define QCA808X_PHY_SPEC_STATUS 17 - -#define QCA808X_PHY_ID1 2 -#define QCA808X_PHY_ID2 3 -#define QCA808X_AUTONEG_ADVERT 4 -#define QCA808X_LINK_PARTNER_ABILITY 5 -#define QCA808X_1000BASET_CONTROL 9 -#define QCA808X_1000BASET_STATUS 10 -#define QCA808X_MMD_CTRL_REG 13 -#define QCA808X_MMD_DATA_REG 14 -#define QCA808X_EXTENDED_STATUS 15 -#define QCA808X_PHY_SPEC_CONTROL 16 -#define QCA808X_PHY_INTR_MASK 18 -#define QCA808X_PHY_INTR_STATUS 19 -#define QCA808X_PHY_CDT_CONTROL 22 -#define QCA808X_DEBUG_PORT_ADDRESS 29 -#define QCA808X_DEBUG_PORT_DATA 30 -#define QCA808X_DEBUG_LOCAL_SEED 9 - -/* Chip Configuration Register */ -#define QCA808X_PHY_CHIP_CONFIG 31 - -#define QCA808X_PHY_MODE_MASK 0x6000 -#define QCA808X_PHY_SGMII_MODE 0x0000 -#define QCA808X_PHY_SGMII_PLUS_MODE 0x2000 -#define QCA808X_PHY_SGMII_BASET 0x4 -#define QCA808X_PHY_CHIP_MODE_CFG 0xf - -#define QCA808X_DEBUG_PHY_HIBERNATION_CTRL 0xb -#define QCA808X_DEBUG_PHY_HIBERNATION_STAT 0xc -#define QCA808X_DEBUG_PHY_POWER_SAVING_CTRL 0x29 -#define QCA808X_PHY_MMD7_ADDR_8023AZ_EEE_CTRL 0x3c -#define QCA808X_PHY_MMD7_ADDR_8023AZ_EEE_PARTNER 0x3d -#define QCA808X_PHY_MMD7_ADDR_8023AZ_EEE_STATUS 0x8000 -#define QCA808X_PHY_MMD3_ADDR_8023AZ_EEE_CAPABILITY 0x14 -#define QCA808X_PHY_MMD7_ADDR_EEE_LP_ADVERTISEMENT 0x40 - -#define QCA808X_PHY_MMD3_ADDR_8023AZ_EEE_DB 0x800f -#define QCA808X_PHY_8023AZ_EEE_LP_STAT 0x2000 -#define QCA808X_PHY_MMD3_ADDR_REMOTE_LOOPBACK_CTRL 0x805a -#define QCA808X_PHY_MMD3_WOL_MAGIC_MAC_CTRL1 0x804a -#define QCA808X_PHY_MMD3_WOL_MAGIC_MAC_CTRL2 0x804b -#define QCA808X_PHY_MMD3_WOL_MAGIC_MAC_CTRL3 0x804c -#define QCA808X_PHY_MMD3_WOL_CTRL 0x8012 -#define QCA808X_PHY_MMD3_ADDR_8023AZ_TIMER_CTRL 0x804e -#define QCA808X_PHY_MMD3_ADDR_CLD_CTRL7 0x8007 -#define QCA808X_PHY_MMD3_ADDR_CLD_CTRL5 0x8005 -#define QCA808X_PHY_MMD3_ADDR_CLD_CTRL3 0x8003 -#define QCA808X_PHY_MMD3_AZ_TRAINING_CTRL 0x8008 - -#define QCA808X_PHY_HIBERNATION_CFG 0x8000 -#define QCA808X_PHY_HIBERNATION_STAT_EN 0x0800 - -#define QCA808X_PHY_WOL_EN 0x0020 - -#define QCA808X_PHY_REMOTE_LOOPBACK_EN 0x0001 - -#define QCA808X_PHY_8023AZ_EEE_1000BT 0x0004 -#define QCA808X_PHY_8023AZ_EEE_100BT 0x0002 -#define QCA808X_PHY_MMD3_AZ_TRAINING_VAL 0x1c32 - -#define QCA808X_PHY_MDIX 0x0020 -#define QCA808X_PHY_MDIX_AUTO 0x0060 -#define QCA808X_PHY_MDIX_STATUS 0x0040 - -#define QCA808X_PHY_MMD7_NUM 7 -#define QCA808X_PHY_MMD3_NUM 3 -#define QCA808X_PHY_MMD1_NUM 1 - -#define QCA808X_PHY_MMD1_FAST_RETRAIN_STATUS_CTL 0x93 -#define QCA808X_PHY_MMD1_MSE_THRESHOLD_20DB 0x8014 -#define QCA808X_PHY_MMD1_MSE_THRESHOLD_17DB 0x800E -#define QCA808X_PHY_MMD1_MSE_THRESHOLD_27DB 0x801E -#define QCA808X_PHY_MMD1_MSE_THRESHOLD_28DB 0x8020 -#define QCA808X_PHY_MMD7_TOP_OPTION1 0x901c -#define QCA808X_PHY_EEE_ADV_100M 0x0002 -#define QCA808X_PHY_EEE_ADV_1000M 0x0004 -#define QCA808X_PHY_EEE_PARTNER_ADV_100M 0x0002 -#define QCA808X_PHY_EEE_PARTNER_ADV_1000M 0x0004 -#define QCA808X_PHY_EEE_CAPABILITY_100M 0x0002 -#define QCA808X_PHY_EEE_CAPABILITY_1000M 0x0004 -#define QCA808X_PHY_EEE_STATUS_100M 0x0002 -#define QCA808X_PHY_EEE_STATUS_1000M 0x0004 - -#define QCA808X_PHY_FAST_RETRAIN_CTRL 0x1 -#define QCA808X_PHY_MSE_THRESHOLD_20DB_VALUE 0x529 -#define QCA808X_PHY_MSE_THRESHOLD_17DB_VALUE 0x341 -#define QCA808X_PHY_MSE_THRESHOLD_27DB_VALUE 0x419 -#define QCA808X_PHY_MSE_THRESHOLD_28DB_VALUE 0x341 -#define QCA808X_PHY_FAST_RETRAIN_2500BT 0x20 -#define QCA808X_PHY_ADV_LOOP_TIMING 0x1 -#define QCA808X_PHY_EEE_ADV_THP 0x8 -#define QCA808X_PHY_TOP_OPTION1_DATA 0x0 - - /* CDT */ -#define QCA808X_MDI_PAIR_NUM 4 -#define QCA808X_RUN_CDT 0x8000 -#define QCA808X_CABLE_LENGTH_UNIT 0x0400 -#define QCA808X_PHY_CDT_STATUS 0X8064 -#define QCA808X_PHY_CDT_DIAG_PAIR0 0X8065 -#define QCA808X_PHY_CDT_DIAG_PAIR1 0X8066 -#define QCA808X_PHY_CDT_DIAG_PAIR2 0X8067 -#define QCA808X_PHY_CDT_DIAG_PAIR3 0X8068 - - /* SYNCE CLOCK OUTPUT */ -#define QCA808X_DEBUG_ANA_CLOCK_CTRL_REG 0x3e80 -#define QCA808X_ANALOG_PHY_SYNCE_CLOCK_EN 0x20 - -#define QCA808X_MMD7_CLOCK_CTRL_REG 0x8072 -#define QCA808X_DIGITAL_PHY_SYNCE_CLOCK_EN 0x1 - - /* PHY Registers Field */ -#define QCA808X_STATUS_LINK_PASS 0x0400 - - /* Control Register fields offset:0 */ - /* bits 6,13: 10=1000, 01=100, 00=10 */ -#define QCA808X_CTRL_SPEED_MSB 0x0040 - - /* Collision test enable */ -#define QCA808X_CTRL_COLL_TEST_ENABLE 0x0080 -/* FDX =1, half duplex =0 */ -#define QCA808X_CTRL_FULL_DUPLEX 0x0100 - - /* Restart auto negotiation */ -#define QCA808X_CTRL_RESTART_AUTONEGOTIATION 0x0200 - - /* Power down */ -#define QCA808X_CTRL_POWER_DOWN 0x0800 - - /* Auto Neg Enable */ -#define QCA808X_CTRL_AUTONEGOTIATION_ENABLE 0x1000 - - /* Local Loopback Enable */ -#define QCA808X_LOCAL_LOOPBACK_ENABLE 0x4000 - - /* bits 6,13: 10=1000, 01=100, 00=10 */ -#define QCA808X_CTRL_SPEED_LSB 0x2000 - - /* 0 = normal, 1 = loopback */ -#define QCA808X_CTRL_LOOPBACK 0x4000 -#define QCA808X_CTRL_SOFTWARE_RESET 0x8000 - -#define QCA808X_PHY_MMD7_AUTONEGOTIATION_CONTROL 0x20 - -#define QCA808X_CTRL_SPEED_MASK 0x2040 -#define QCA808X_CTRL_SPEED_1000 0x0040 -#define QCA808X_CTRL_SPEED_100 0x2000 -#define QCA808X_CTRL_SPEED_10 0x0000 - -#define QCA808X_MASTER_SLAVE_SEED_ENABLE 0x2 -#define QCA808X_MASTER_SLAVE_SEED_CFG 0x1FFC -#define QCA808X_MASTER_SLAVE_SEED_RANGE 0x32 -#define QCA808X_MASTER_SLAVE_CONFIG_FAULT 0x8000 - -#define QCA808X_RESET_DONE(phy_control) \ - (((phy_control) & (QCA808X_CTRL_SOFTWARE_RESET)) == 0) - - /* Status Register fields offset:1 */ -#define QCA808X_STATUS_EXTENDED_CAPS 0x0001 - - /* Jabber Detected */ -#define QCA808X_STATUS_JABBER_DETECT 0x0002 - - /* Link Status 1 = link */ -#define QCA808X_STATUS_LINK_STATUS_UP 0x0004 - - /* Auto Neg Capable */ -#define QCA808X_STATUS_AUTONEG_CAPS 0x0008 - - /* Remote Fault Detect */ -#define QCA808X_STATUS_REMOTE_FAULT 0x0010 - - /* Auto Neg Complete */ -#define QCA808X_STATUS_AUTO_NEG_DONE 0x0020 - - /* Preamble may be suppressed */ -#define QCA808X_STATUS_PREAMBLE_SUPPRESS 0x0040 - - /* Ext. status info in Reg 0x0F */ -#define QCA808X_STATUS_EXTENDED_STATUS 0x0100 - - /* 100T2 Half Duplex Capable */ -#define QCA808X_STATUS_100T2_HD_CAPS 0x0200 - - /* 100T2 Full Duplex Capable */ -#define QCA808X_STATUS_100T2_FD_CAPS 0x0400 - - /* 10T Half Duplex Capable */ -#define QCA808X_STATUS_10T_HD_CAPS 0x0800 - - /* 10T Full Duplex Capable */ -#define QCA808X_STATUS_10T_FD_CAPS 0x1000 - - /* 100TX Half Duplex Capable */ -#define QCA808X_STATUS_100TX_HD_CAPS 0x2000 - - /* 100TX Full Duplex Capable */ -#define QCA808X_STATUS_100TX_FD_CAPS 0x4000 - - /* 100T4 Capable */ -#define QCA808X_STATUS_100T4_CAPS 0x8000 - - /* extended status register capabilities */ - -#define QCA808X_STATUS_1000T_HD_CAPS 0x1000 - -#define QCA808X_STATUS_1000T_FD_CAPS 0x2000 - -#define QCA808X_STATUS_1000X_HD_CAPS 0x4000 - -#define QCA808X_STATUS_1000X_FD_CAPS 0x8000 - -#define QCA808X_MMD1_PMA_CAP_REG 0x4 - /* MMD1 2500T capabilities */ -#define QCA808X_STATUS_2500T_FD_CAPS 0x2000 - - /* Link Partner ability offset:5 */ -#define QCA808X_LINK_SLCT 0x001f - - /* Can do 10mbps half-duplex */ -#define QCA808X_LINK_10BASETX_HALF_DUPLEX 0x0020 - - /* Can do 10mbps full-duplex */ -#define QCA808X_LINK_10BASETX_FULL_DUPLEX 0x0040 - - /* Can do 100mbps half-duplex */ -#define QCA808X_LINK_100BASETX_HALF_DUPLEX 0x0080 - - /* Can do 100mbps full-duplex */ -#define QCA808X_LINK_100BASETX_FULL_DUPLEX 0x0100 - - /* Can do 1000mbps full-duplex */ -#define QCA808X_LINK_1000BASETX_FULL_DUPLEX 0x0800 - - /* Can do 1000mbps half-duplex */ -#define QCA808X_LINK_1000BASETX_HALF_DUPLEX 0x0400 - - /* Can do 2500mbps full-duplex */ -#define QCA808X_LINK_2500BASETX_FULL_DUPLEX 0x0020 - - /* 100BASE-T4 */ -#define QCA808X_LINK_100BASE4 0x0200 - - /* PAUSE */ -#define QCA808X_LINK_PAUSE 0x0400 - - /* Asymmetrical PAUSE */ -#define QCA808X_LINK_ASYPAUSE 0x0800 - - /* Link partner faulted */ -#define QCA808X_LINK_RFAULT 0x2000 - - /* Link partner acked us */ -#define QCA808X_LINK_LPACK 0x4000 - - /* Next page bit */ -#define QCA808X_LINK_NPAGE 0x8000 - - /* Auto Neg Complete */ -#define QCA808X_STATUS_AUTO_NEG_DONE 0x0020 -#define QCA808X_AUTONEG_DONE(ip_phy_status) \ - (((ip_phy_status) & (QCA808X_STATUS_AUTO_NEG_DONE)) == \ - (QCA808X_STATUS_AUTO_NEG_DONE)) - -#define QCA808X_STATUS_RESOVLED 0x0800 -#define QCA808X_SPEED_DUPLEX_RESOVLED(phy_status) \ - (((phy_status) & \ - (QCA808X_STATUS_RESOVLED)) == \ - (QCA808X_STATUS_RESOVLED)) - - /* Auto-Negotiation Advertisement register. offset:4 */ -#define QCA808X_ADVERTISE_SELECTOR_FIELD 0x0001 - - /* 10T Half Duplex Capable */ -#define QCA808X_ADVERTISE_10HALF 0x0020 - - /* 10T Full Duplex Capable */ -#define QCA808X_ADVERTISE_10FULL 0x0040 - - /* 100TX Half Duplex Capable */ -#define QCA808X_ADVERTISE_100HALF 0x0080 - - /* 100TX Full Duplex Capable */ -#define QCA808X_ADVERTISE_100FULL 0x0100 - - /* 100T4 Capable */ -#define QCA808X_ADVERTISE_100T4 0x0200 - - /* Pause operation desired */ -#define QCA808X_ADVERTISE_PAUSE 0x0400 - - /* Asymmetric Pause Direction bit */ -#define QCA808X_ADVERTISE_ASYM_PAUSE 0x0800 - - /* Remote Fault detected */ -#define QCA808X_ADVERTISE_REMOTE_FAULT 0x2000 - - /* 1000TX Half Duplex Capable */ -#define QCA808X_ADVERTISE_1000HALF 0x0100 - - /* 1000TX Full Duplex Capable */ -#define QCA808X_ADVERTISE_1000FULL 0x0200 - - /* 2500TX Full Duplex Capable */ -#define QCA808X_ADVERTISE_2500FULL 0x80 - -#define QCA808X_ADVERTISE_ALL \ - (QCA808X_ADVERTISE_10HALF | QCA808X_ADVERTISE_10FULL | \ - QCA808X_ADVERTISE_100HALF | QCA808X_ADVERTISE_100FULL | \ - QCA808X_ADVERTISE_1000FULL) - -#define QCA808X_ADVERTISE_MEGA_ALL \ - (QCA808X_ADVERTISE_10HALF | QCA808X_ADVERTISE_10FULL | \ - QCA808X_ADVERTISE_100HALF | QCA808X_ADVERTISE_100FULL | \ - QCA808X_ADVERTISE_PAUSE | QCA808X_ADVERTISE_ASYM_PAUSE) - -#define QCA808X_BX_ADVERTISE_1000FULL 0x0020 -#define QCA808X_BX_ADVERTISE_1000HALF 0x0040 -#define QCA808X_BX_ADVERTISE_PAUSE 0x0080 -#define QCA808X_BX_ADVERTISE_ASYM_PAUSE 0x0100 - -#define QCA808X_BX_ADVERTISE_ALL \ - (QCA808X_BX_ADVERTISE_ASYM_PAUSE | QCA808X_BX_ADVERTISE_PAUSE | \ - QCA808X_BX_ADVERTISE_1000HALF | QCA808X_BX_ADVERTISE_1000FULL) - - /* 1=Duplex 0=Half Duplex */ -#define QCA808X_STATUS_FULL_DUPLEX 0x2000 -#define QCA808X_PHY_RX_FLOWCTRL_STATUS 0x4 -#define QCA808X_PHY_TX_FLOWCTRL_STATUS 0x8 - - /* Speed, bits 9:7 */ -#define QCA808X_STATUS_SPEED_MASK 0x380 - - /* 000=10Mbs */ -#define QCA808X_STATUS_SPEED_10MBS 0x0000 - - /* 001=100Mbs */ -#define QCA808X_STATUS_SPEED_100MBS 0x80 - - /* 010=1000Mbs */ -#define QCA808X_STATUS_SPEED_1000MBS 0x100 - - /* 100=2500Mbs */ -#define QCA808X_STATUS_SPEED_2500MBS 0x200 - - /*QCA808X interrupt flag */ -#define QCA808X_INTR_FAST_LINK_DOWN 0x8000 -#define QCA808X_INTR_SPEED_CHANGE 0x4000 -#define QCA808X_INTR_SEC_ENA_CHANGE 0x2000 -#define QCA808X_INTR_STATUS_DOWN_CHANGE 0x0800 -#define QCA808X_INTR_STATUS_UP_CHANGE 0x0400 -#define QCA808X_INTR_FAST_LINK_DOWN_MASK 0x240 -#define QCA808X_INTR_FAST_LINK_DOWN_STAT_10M 0x40 -#define QCA808X_INTR_FAST_LINK_DOWN_STAT_100M 0x200 -#define QCA808X_INTR_FAST_LINK_DOWN_STAT_1000M 0x240 -#define QCA808X_INTR_LINK_FAIL_SG 0x0100 -#define QCA808X_INTR_LINK_SUCCESS_SG 0x0080 -#define QCA808X_INTR_DOWNSHIF 0x0020 -#define QCA808X_INTR_10MS_PTP 0x0010 -#define QCA808X_INTR_RX_PTP 0x0008 -#define QCA808X_INTR_TX_PTP 0x0004 -#define QCA808X_INTR_POE 0x0002 -#define QCA808X_INTR_WOL 0x0001 - - /* QCA808X counter */ -#define QCA808X_PHY_MMD7_COUNTER_CTRL 0x8029 -#define QCA808X_PHY_MMD7_INGRESS_COUNTER_HIGH 0x802a -#define QCA808X_PHY_MMD7_INGRESS_COUNTER_LOW 0x802b -#define QCA808X_PHY_MMD7_INGRESS_ERROR_COUNTER 0x802c -#define QCA808X_PHY_MMD7_EGRESS_COUNTER_HIGH 0x802d -#define QCA808X_PHY_MMD7_EGRESS_COUNTER_LOW 0x802e -#define QCA808X_PHY_MMD7_EGRESS_ERROR_COUNTER 0x802f -#define QCA808X_PHY_MMD7_LED_POLARITY_CTRL 0x901a -#define QCA808X_PHY_MMD7_LED0_CTRL 0x8078 -#define QCA808X_PHY_MMD7_LED1_CTRL 0x8074 -#define QCA808X_PHY_MMD7_LED2_CTRL 0x8076 -#define QCA808X_PHY_MMD7_LED_POLARITY_ACTIVE_HIGH 0x46 -#define QCA808X_PHY_MMD7_LED0_CTRL_ENABLE 0x8670 -#define QCA808X_PHY_MMD7_LED1_CTRL_DISABLE 0x0 -#define QCA808X_PHY_MMD7_LED2_CTRL_DISABLE 0x0 - -#define QCA808X_PHY_FRAME_CHECK_EN 0x0001 -#define QCA808X_PHY_XMIT_MAC_CNT_SELFCLR 0x0002 - -#define QCA808X_PHY_ADC_THRESHOLD 0x2c80 -#define QCA808X_PHY_ADC_THRESHOLD_80MV 0 -#define QCA808X_PHY_ADC_THRESHOLD_100MV 0xf0 -#define QCA808X_PHY_ADC_THRESHOLD_200MV 0x0f -#define QCA808X_PHY_ADC_THRESHOLD_300MV 0xff - -a_uint16_t -qca808x_phy_reg_read(a_uint32_t dev_id, a_uint32_t phy_id, a_uint32_t reg_id); - -sw_error_t -qca808x_phy_reg_write(a_uint32_t dev_id, a_uint32_t phy_id, - a_uint32_t reg_id, a_uint16_t reg_val); - -sw_error_t -qca808x_phy_mmd_write(a_uint32_t dev_id, a_uint32_t phy_id, - a_uint16_t mmd_num, a_uint16_t reg_id, - a_uint16_t reg_val); - -a_uint16_t -qca808x_phy_mmd_read(a_uint32_t dev_id, a_uint32_t phy_id, - a_uint16_t mmd_num, a_uint16_t reg_id); - -a_uint16_t -qca808x_phy_reg_read(a_uint32_t dev_id, a_uint32_t phy_id, a_uint32_t reg_id); - -sw_error_t -qca808x_phy_reg_write(a_uint32_t dev_id, a_uint32_t phy_id, a_uint32_t -reg_id, a_uint16_t reg_val); - -sw_error_t -qca808x_phy_debug_write(a_uint32_t dev_id, a_uint32_t phy_id, a_uint16_t reg_id, - a_uint16_t reg_val); -a_uint16_t -qca808x_phy_debug_read(a_uint32_t dev_id, a_uint32_t phy_id, a_uint16_t reg_id); - -sw_error_t -qca808x_phy_mmd_write(a_uint32_t dev_id, a_uint32_t phy_id, - a_uint16_t mmd_num, a_uint16_t reg_id, a_uint16_t -reg_val); - -a_uint16_t -qca808x_phy_mmd_read(a_uint32_t dev_id, a_uint32_t phy_id, - a_uint16_t mmd_num, a_uint16_t reg_id); - -#define QCA808X_PHY_8023AZ_AFE_CTRL_MASK 0x01f0 -#define QCA808X_PHY_8023AZ_AFE_EN 0x0090 - -sw_error_t -qca808x_phy_set_duplex (a_uint32_t dev_id, a_uint32_t phy_id, - fal_port_duplex_t duplex); - -sw_error_t -qca808x_phy_get_duplex (a_uint32_t dev_id, a_uint32_t phy_id, - fal_port_duplex_t * duplex); - -sw_error_t -qca808x_phy_set_speed (a_uint32_t dev_id, a_uint32_t phy_id, - fal_port_speed_t speed); - -sw_error_t -qca808x_phy_get_speed (a_uint32_t dev_id, a_uint32_t phy_id, - fal_port_speed_t * speed); - -sw_error_t -qca808x_phy_restart_autoneg (a_uint32_t dev_id, a_uint32_t phy_id); - -sw_error_t -qca808x_phy_enable_autoneg (a_uint32_t dev_id, a_uint32_t phy_id); - -a_bool_t -qca808x_phy_get_link_status (a_uint32_t dev_id, a_uint32_t phy_id); - -sw_error_t -qca808x_phy_set_autoneg_adv (a_uint32_t dev_id, a_uint32_t phy_id, - a_uint32_t autoneg); - -sw_error_t -qca808x_phy_get_autoneg_adv (a_uint32_t dev_id, a_uint32_t phy_id, - a_uint32_t * autoneg); - -a_bool_t qca808x_phy_autoneg_status (a_uint32_t dev_id, a_uint32_t phy_id); -#ifndef IN_PORTCONTROL_MINI -sw_error_t -qca808x_phy_intr_mask_set (a_uint32_t dev_id, a_uint32_t phy_id, - a_uint32_t intr_mask_flag); - -sw_error_t -qca808x_phy_intr_mask_get (a_uint32_t dev_id, a_uint32_t phy_id, - a_uint32_t * intr_mask_flag); - -sw_error_t -qca808x_phy_intr_status_get (a_uint32_t dev_id, a_uint32_t phy_id, - a_uint32_t * intr_status_flag); -#endif -sw_error_t -qca808x_phy_get_phy_id(a_uint32_t dev_id, a_uint32_t phy_id, - a_uint32_t *phy_data); - -sw_error_t -qca808x_phy_get_status(a_uint32_t dev_id, a_uint32_t phy_id, - struct port_phy_status *phy_status); - -sw_error_t -qca808x_phy_interface_get_mode_status(a_uint32_t dev_id, a_uint32_t phy_id, - fal_port_interface_mode_t *interface_mode_status); - -sw_error_t qca808x_phy_reset(a_uint32_t dev_id, a_uint32_t phy_id); - -sw_error_t -qca808x_phy_set_force_speed(a_uint32_t dev_id, a_uint32_t phy_id, - fal_port_speed_t speed); -sw_error_t qca808x_phy_poweroff(a_uint32_t dev_id, a_uint32_t phy_id); -sw_error_t qca808x_phy_poweron(a_uint32_t dev_id, a_uint32_t phy_id); -#ifndef IN_PORTCONTROL_MINI -sw_error_t -qca808x_phy_set_hibernate(a_uint32_t dev_id, a_uint32_t phy_id, a_bool_t enable); -sw_error_t -qca808x_phy_get_hibernate(a_uint32_t dev_id, a_uint32_t phy_id, - a_bool_t * enable); -sw_error_t -qca808x_phy_cdt(a_uint32_t dev_id, a_uint32_t phy_id, a_uint32_t mdi_pair, - fal_cable_status_t * cable_status, a_uint32_t * cable_len); -sw_error_t -qca808x_phy_set_mdix(a_uint32_t dev_id, a_uint32_t phy_id, - fal_port_mdix_mode_t mode); -sw_error_t -qca808x_phy_get_mdix(a_uint32_t dev_id, a_uint32_t phy_id, - fal_port_mdix_mode_t * mode); -sw_error_t -qca808x_phy_get_mdix_status(a_uint32_t dev_id, a_uint32_t phy_id, - fal_port_mdix_status_t * mode); -sw_error_t -qca808x_phy_set_local_loopback(a_uint32_t dev_id, a_uint32_t phy_id, - a_bool_t enable); -sw_error_t -qca808x_phy_get_local_loopback(a_uint32_t dev_id, a_uint32_t phy_id, - a_bool_t * enable); -sw_error_t -qca808x_phy_set_remote_loopback(a_uint32_t dev_id, a_uint32_t phy_id, - a_bool_t enable); -sw_error_t -qca808x_phy_get_remote_loopback(a_uint32_t dev_id, a_uint32_t phy_id, - a_bool_t * enable); -sw_error_t -qca808x_phy_set_wol_status(a_uint32_t dev_id, a_uint32_t phy_id, a_bool_t enable); -sw_error_t -qca808x_phy_get_wol_status(a_uint32_t dev_id, a_uint32_t phy_id, a_bool_t * enable); -sw_error_t -qca808x_phy_set_magic_frame_mac(a_uint32_t dev_id, a_uint32_t phy_id, - fal_mac_addr_t * mac); -sw_error_t -qca808x_phy_get_magic_frame_mac(a_uint32_t dev_id, a_uint32_t phy_id, - fal_mac_addr_t * mac); -sw_error_t -qca808x_phy_set_counter(a_uint32_t dev_id, a_uint32_t phy_id, a_bool_t enable); -sw_error_t -qca808x_phy_get_counter(a_uint32_t dev_id, a_uint32_t phy_id, - a_bool_t * enable); -sw_error_t -qca808x_phy_show_counter(a_uint32_t dev_id, a_uint32_t phy_id, - fal_port_counter_info_t * counter_infor); -sw_error_t -qca808x_phy_set_intr_mask(a_uint32_t dev_id, a_uint32_t phy_id, - a_uint32_t intr_mask_flag); -sw_error_t -qca808x_phy_get_intr_mask(a_uint32_t dev_id, a_uint32_t phy_id, - a_uint32_t * intr_mask_flag); -sw_error_t -qca808x_phy_get_intr_status(a_uint32_t dev_id, a_uint32_t phy_id, - a_uint32_t * intr_status_flag); -sw_error_t -qca808x_phy_set_8023az(a_uint32_t dev_id, a_uint32_t phy_id, a_bool_t enable); -sw_error_t -qca808x_phy_get_8023az(a_uint32_t dev_id, a_uint32_t phy_id, a_bool_t * enable); -#endif -sw_error_t -qca808x_phy_set_eee_adv(a_uint32_t dev_id, a_uint32_t phy_id, - a_uint32_t adv); -sw_error_t -qca808x_phy_get_eee_adv(a_uint32_t dev_id, a_uint32_t phy_id, - a_uint32_t *adv); -sw_error_t -qca808x_phy_get_eee_partner_adv(a_uint32_t dev_id, a_uint32_t phy_id, - a_uint32_t *adv); -sw_error_t -qca808x_phy_get_eee_cap(a_uint32_t dev_id, a_uint32_t phy_id, - a_uint32_t *cap); -sw_error_t -qca808x_phy_get_eee_status(a_uint32_t dev_id, a_uint32_t phy_id, - a_uint32_t *status); -void qca808x_phy_lock_init(void); -int qca808x_phy_init(a_uint32_t dev_id, a_uint32_t port_bmp); - -void qca808x_phy_exit(a_uint32_t dev_id, a_uint32_t port_id); -a_bool_t -qca808x_phy_2500caps(a_uint32_t dev_id, a_uint32_t phy_id); - -#ifdef __cplusplus -} -#endif /* __cplusplus */ -#endif /* _qca808x_PHY_H_ */ diff --git a/feeds/ipq807x/qca-ssdk/src/include/hsl/phy/qca808x_ptp.h b/feeds/ipq807x/qca-ssdk/src/include/hsl/phy/qca808x_ptp.h deleted file mode 100755 index 045c3702e..000000000 --- a/feeds/ipq807x/qca-ssdk/src/include/hsl/phy/qca808x_ptp.h +++ /dev/null @@ -1,223 +0,0 @@ -/* - * Copyright (c) 2018, The Linux Foundation. All rights reserved. - * Permission to use, copy, modify, and/or distribute this software for - * any purpose with or without fee is hereby granted, provided that the - * above copyright notice and this permission notice appear in all copies. - * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES - * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR - * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES - * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN - * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT - * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. - */ - -#ifndef _QCA808X_PTP_H_ -#define _QCA808X_PTP_H_ - -#ifdef __cplusplus -extern "C" -{ -#endif /* __cplusplus */ - -#define PTP_DEV_ID 0 - -sw_error_t -qca808x_phy_ptp_security_set(a_uint32_t dev_id, - a_uint32_t phy_id, fal_ptp_security_t *sec); - -sw_error_t -qca808x_phy_ptp_link_delay_set(a_uint32_t dev_id, - a_uint32_t phy_id, fal_ptp_time_t *time); - -sw_error_t -qca808x_phy_ptp_rx_crc_recalc_status_get(a_uint32_t dev_id, - a_uint32_t phy_id, a_bool_t *status); - -sw_error_t -qca808x_phy_ptp_tod_uart_set(a_uint32_t dev_id, - a_uint32_t phy_id, fal_ptp_tod_uart_t *tod_uart); - -sw_error_t -qca808x_phy_ptp_enhanced_timestamp_engine_get(a_uint32_t dev_id, - a_uint32_t phy_id, fal_ptp_direction_t direction, - fal_ptp_enhanced_ts_engine_t *ts_engine); - -sw_error_t -qca808x_phy_ptp_pps_signal_control_set(a_uint32_t dev_id, - a_uint32_t phy_id, fal_ptp_pps_signal_control_t *sig_control); - -sw_error_t -qca808x_phy_ptp_timestamp_get(a_uint32_t dev_id, - a_uint32_t phy_id, fal_ptp_direction_t direction, - fal_ptp_pkt_info_t *pkt_info, fal_ptp_time_t *time); - -sw_error_t -qca808x_phy_ptp_asym_correction_get(a_uint32_t dev_id, - a_uint32_t phy_id, fal_ptp_asym_correction_t* asym_cf); - -sw_error_t -qca808x_phy_ptp_rtc_time_snapshot_status_get(a_uint32_t dev_id, - a_uint32_t phy_id, a_bool_t *status); - -sw_error_t -qca808x_phy_ptp_capture_set(a_uint32_t dev_id, - a_uint32_t phy_id, a_uint32_t capture_id, - fal_ptp_capture_t *capture); - -sw_error_t -qca808x_phy_ptp_rtc_adjfreq_set(a_uint32_t dev_id, - a_uint32_t phy_id, fal_ptp_time_t *time); - -sw_error_t -qca808x_phy_ptp_asym_correction_set(a_uint32_t dev_id, - a_uint32_t phy_id, fal_ptp_asym_correction_t *asym_cf); - -sw_error_t -qca808x_phy_ptp_pkt_timestamp_set(a_uint32_t dev_id, - a_uint32_t phy_id, fal_ptp_time_t *time); - -sw_error_t -qca808x_phy_ptp_rtc_time_get(a_uint32_t dev_id, - a_uint32_t phy_id, fal_ptp_time_t *time); - -sw_error_t -qca808x_phy_ptp_rtc_time_set(a_uint32_t dev_id, - a_uint32_t phy_id, fal_ptp_time_t *time); - -sw_error_t -qca808x_phy_ptp_pkt_timestamp_get(a_uint32_t dev_id, - a_uint32_t phy_id, fal_ptp_time_t *time); - -sw_error_t -qca808x_phy_ptp_interrupt_set(a_uint32_t dev_id, - a_uint32_t phy_id, fal_ptp_interrupt_t *interrupt); - -sw_error_t -qca808x_phy_ptp_trigger_set(a_uint32_t dev_id, - a_uint32_t phy_id, a_uint32_t trigger_id, - fal_ptp_trigger_t *triger); - -sw_error_t -qca808x_phy_ptp_pps_signal_control_get(a_uint32_t dev_id, - a_uint32_t phy_id, fal_ptp_pps_signal_control_t *sig_control); - -sw_error_t -qca808x_phy_ptp_capture_get(a_uint32_t dev_id, - a_uint32_t phy_id, a_uint32_t capture_id, - fal_ptp_capture_t *capture); - -sw_error_t -qca808x_phy_ptp_rx_crc_recalc_enable(a_uint32_t dev_id, - a_uint32_t phy_id, a_bool_t status); - -sw_error_t -qca808x_phy_ptp_security_get(a_uint32_t dev_id, - a_uint32_t phy_id, fal_ptp_security_t *sec); - -sw_error_t -qca808x_phy_ptp_increment_sync_from_clock_status_get(a_uint32_t dev_id, - a_uint32_t phy_id, a_bool_t *status); - -sw_error_t -qca808x_phy_ptp_tod_uart_get(a_uint32_t dev_id, - a_uint32_t phy_id, fal_ptp_tod_uart_t *tod_uart); - -sw_error_t -qca808x_phy_ptp_enhanced_timestamp_engine_set(a_uint32_t dev_id, - a_uint32_t phy_id, fal_ptp_direction_t direction, - fal_ptp_enhanced_ts_engine_t *ts_engine); - -sw_error_t -qca808x_phy_ptp_rtc_time_clear(a_uint32_t dev_id, - a_uint32_t phy_id); - -sw_error_t -qca808x_phy_ptp_reference_clock_set(a_uint32_t dev_id, - a_uint32_t phy_id, fal_ptp_reference_clock_t ref_clock); - -sw_error_t -qca808x_phy_ptp_output_waveform_set(a_uint32_t dev_id, - a_uint32_t phy_id, fal_ptp_output_waveform_t *waveform); - -sw_error_t -qca808x_phy_ptp_rx_timestamp_mode_set(a_uint32_t dev_id, - a_uint32_t phy_id, fal_ptp_rx_timestamp_mode_t ts_mode); - -sw_error_t -qca808x_phy_ptp_grandmaster_mode_set(a_uint32_t dev_id, - a_uint32_t phy_id, fal_ptp_grandmaster_mode_t *gm_mode); - -sw_error_t -qca808x_phy_ptp_config_set(a_uint32_t dev_id, - a_uint32_t phy_id, fal_ptp_config_t *config); - -sw_error_t -qca808x_phy_ptp_trigger_get(a_uint32_t dev_id, - a_uint32_t phy_id, a_uint32_t trigger_id, - fal_ptp_trigger_t *triger); - -sw_error_t -qca808x_phy_ptp_rtc_adjfreq_get(a_uint32_t dev_id, - a_uint32_t phy_id, fal_ptp_time_t *time); - -sw_error_t -qca808x_phy_ptp_grandmaster_mode_get(a_uint32_t dev_id, - a_uint32_t phy_id, fal_ptp_grandmaster_mode_t *gm_mode); - -sw_error_t -qca808x_phy_ptp_rx_timestamp_mode_get(a_uint32_t dev_id, - a_uint32_t phy_id, fal_ptp_rx_timestamp_mode_t *ts_mode); - -sw_error_t -qca808x_phy_ptp_rtc_adjtime_set(a_uint32_t dev_id, - a_uint32_t phy_id, fal_ptp_time_t *time); - -sw_error_t -qca808x_phy_ptp_link_delay_get(a_uint32_t dev_id, - a_uint32_t phy_id, fal_ptp_time_t *time); - -sw_error_t -qca808x_phy_ptp_increment_sync_from_clock_enable(a_uint32_t dev_id, - a_uint32_t phy_id, a_bool_t status); - -sw_error_t -qca808x_phy_ptp_config_get(a_uint32_t dev_id, - a_uint32_t phy_id, fal_ptp_config_t *config); - -sw_error_t -qca808x_phy_ptp_output_waveform_get(a_uint32_t dev_id, - a_uint32_t phy_id, fal_ptp_output_waveform_t *waveform); - -sw_error_t -qca808x_phy_ptp_interrupt_get(a_uint32_t dev_id, - a_uint32_t phy_id, fal_ptp_interrupt_t *interrupt); - -sw_error_t -qca808x_phy_ptp_rtc_time_snapshot_enable(a_uint32_t dev_id, - a_uint32_t phy_id, a_bool_t status); - -sw_error_t -qca808x_phy_ptp_reference_clock_get(a_uint32_t dev_id, - a_uint32_t phy_id, fal_ptp_reference_clock_t *ref_clock); - -void qca808x_phy_ptp_api_ops_init(hsl_phy_ptp_ops_t *phy_ptp_ops); - -#if defined(IN_LINUX_STD_PTP) -void qca808x_ptp_gm_gps_seconds_sync_enable(a_uint32_t dev_id, - a_uint32_t phy_addr, a_bool_t en); - -a_bool_t qca808x_ptp_gm_gps_seconds_sync_status_get(a_uint32_t dev_id, - a_uint32_t phy_addr); - -void qca808x_ptp_clock_mode_config(a_uint32_t dev_id, - a_uint32_t phy_addr, a_uint16_t clock_mode, a_uint16_t step_mode); - -void qca808x_ptp_stat_get(void); - -void qca808x_ptp_stat_set(void); -#endif -#ifdef __cplusplus -} -#endif /* __cplusplus */ -#endif /* _qca808x_PTP_H_ */ diff --git a/feeds/ipq807x/qca-ssdk/src/include/hsl/phy/qca808x_ptp_api.h b/feeds/ipq807x/qca-ssdk/src/include/hsl/phy/qca808x_ptp_api.h deleted file mode 100755 index 5e1464fdb..000000000 --- a/feeds/ipq807x/qca-ssdk/src/include/hsl/phy/qca808x_ptp_api.h +++ /dev/null @@ -1,5858 +0,0 @@ -/* - * Copyright (c) 2018, The Linux Foundation. All rights reserved. - * Permission to use, copy, modify, and/or distribute this software for - * any purpose with or without fee is hereby granted, provided that the - * above copyright notice and this permission notice appear in all copies. - * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES - * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR - * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES - * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN - * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT - * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. - */ - - -/** - * @defgroup - * @{ - */ -#ifndef _PTP_REG_API_H_ -#define _PTP_REG_API_H_ - -#define PTP_REG_BASE_ADDR 0x3000 - - -sw_error_t -qca808x_ptp_imr_reg_get( - a_uint32_t dev_id, a_uint32_t phy_id, - union ptp_imr_reg_u *value); - -sw_error_t -qca808x_ptp_imr_reg_set( - a_uint32_t dev_id, a_uint32_t phy_id, - union ptp_imr_reg_u *value); - -sw_error_t -qca808x_ptp_isr_reg_get( - a_uint32_t dev_id, a_uint32_t phy_id, - union ptp_isr_reg_u *value); - -sw_error_t -qca808x_ptp_isr_reg_set( - a_uint32_t dev_id, a_uint32_t phy_id, - union ptp_isr_reg_u *value); - -sw_error_t -qca808x_ptp_hw_enable_reg_get( - a_uint32_t dev_id, a_uint32_t phy_id, - union ptp_hw_enable_reg_u *value); - -sw_error_t -qca808x_ptp_hw_enable_reg_set( - a_uint32_t dev_id, a_uint32_t phy_id, - union ptp_hw_enable_reg_u *value); - -sw_error_t -qca808x_ptp_main_conf_reg_get( - a_uint32_t dev_id, a_uint32_t phy_id, - union ptp_main_conf_reg_u *value); - -sw_error_t -qca808x_ptp_main_conf_reg_set( - a_uint32_t dev_id, a_uint32_t phy_id, - union ptp_main_conf_reg_u *value); - -sw_error_t -qca808x_ptp_rx_seqid0_reg_get( - a_uint32_t dev_id, a_uint32_t phy_id, - union ptp_rx_seqid0_reg_u *value); - -sw_error_t -qca808x_ptp_rx_seqid0_reg_set( - a_uint32_t dev_id, a_uint32_t phy_id, - union ptp_rx_seqid0_reg_u *value); - -sw_error_t -qca808x_ptp_rx_portid0_0_reg_get( - a_uint32_t dev_id, a_uint32_t phy_id, - union ptp_rx_portid0_0_reg_u *value); - -sw_error_t -qca808x_ptp_rx_portid0_0_reg_set( - a_uint32_t dev_id, a_uint32_t phy_id, - union ptp_rx_portid0_0_reg_u *value); - -sw_error_t -qca808x_ptp_rx_portid0_1_reg_get( - a_uint32_t dev_id, a_uint32_t phy_id, - union ptp_rx_portid0_1_reg_u *value); - -sw_error_t -qca808x_ptp_rx_portid0_1_reg_set( - a_uint32_t dev_id, a_uint32_t phy_id, - union ptp_rx_portid0_1_reg_u *value); - -sw_error_t -qca808x_ptp_rx_portid0_2_reg_get( - a_uint32_t dev_id, a_uint32_t phy_id, - union ptp_rx_portid0_2_reg_u *value); - -sw_error_t -qca808x_ptp_rx_portid0_2_reg_set( - a_uint32_t dev_id, a_uint32_t phy_id, - union ptp_rx_portid0_2_reg_u *value); - -sw_error_t -qca808x_ptp_rx_portid0_3_reg_get( - a_uint32_t dev_id, a_uint32_t phy_id, - union ptp_rx_portid0_3_reg_u *value); - -sw_error_t -qca808x_ptp_rx_portid0_3_reg_set( - a_uint32_t dev_id, a_uint32_t phy_id, - union ptp_rx_portid0_3_reg_u *value); - -sw_error_t -qca808x_ptp_rx_portid0_4_reg_get( - a_uint32_t dev_id, a_uint32_t phy_id, - union ptp_rx_portid0_4_reg_u *value); - -sw_error_t -qca808x_ptp_rx_portid0_4_reg_set( - a_uint32_t dev_id, a_uint32_t phy_id, - union ptp_rx_portid0_4_reg_u *value); - -sw_error_t -qca808x_ptp_rtc_clk_reg_get( - a_uint32_t dev_id, a_uint32_t phy_id, - union ptp_rtc_clk_reg_u *value); - -sw_error_t -qca808x_ptp_rtc_clk_reg_set( - a_uint32_t dev_id, a_uint32_t phy_id, - union ptp_rtc_clk_reg_u *value); - -sw_error_t -qca808x_ptp_rx_ts0_0_reg_get( - a_uint32_t dev_id, a_uint32_t phy_id, - union ptp_rx_ts0_0_reg_u *value); - -sw_error_t -qca808x_ptp_rx_ts0_0_reg_set( - a_uint32_t dev_id, a_uint32_t phy_id, - union ptp_rx_ts0_0_reg_u *value); - -sw_error_t -qca808x_ptp_rx_ts0_1_reg_get( - a_uint32_t dev_id, a_uint32_t phy_id, - union ptp_rx_ts0_1_reg_u *value); - -sw_error_t -qca808x_ptp_rx_ts0_1_reg_set( - a_uint32_t dev_id, a_uint32_t phy_id, - union ptp_rx_ts0_1_reg_u *value); - -sw_error_t -qca808x_ptp_rx_ts0_2_reg_get( - a_uint32_t dev_id, a_uint32_t phy_id, - union ptp_rx_ts0_2_reg_u *value); - -sw_error_t -qca808x_ptp_rx_ts0_2_reg_set( - a_uint32_t dev_id, a_uint32_t phy_id, - union ptp_rx_ts0_2_reg_u *value); - -sw_error_t -qca808x_ptp_rx_ts0_3_reg_get( - a_uint32_t dev_id, a_uint32_t phy_id, - union ptp_rx_ts0_3_reg_u *value); - -sw_error_t -qca808x_ptp_rx_ts0_3_reg_set( - a_uint32_t dev_id, a_uint32_t phy_id, - union ptp_rx_ts0_3_reg_u *value); - -sw_error_t -qca808x_ptp_rx_ts0_4_reg_get( - a_uint32_t dev_id, a_uint32_t phy_id, - union ptp_rx_ts0_4_reg_u *value); - -sw_error_t -qca808x_ptp_rx_ts0_4_reg_set( - a_uint32_t dev_id, a_uint32_t phy_id, - union ptp_rx_ts0_4_reg_u *value); - -sw_error_t -qca808x_ptp_rx_ts0_5_reg_get( - a_uint32_t dev_id, a_uint32_t phy_id, - union ptp_rx_ts0_5_reg_u *value); - -sw_error_t -qca808x_ptp_rx_ts0_5_reg_set( - a_uint32_t dev_id, a_uint32_t phy_id, - union ptp_rx_ts0_5_reg_u *value); - -sw_error_t -qca808x_ptp_rx_ts0_6_reg_get( - a_uint32_t dev_id, a_uint32_t phy_id, - union ptp_rx_ts0_6_reg_u *value); - -sw_error_t -qca808x_ptp_rx_ts0_6_reg_set( - a_uint32_t dev_id, a_uint32_t phy_id, - union ptp_rx_ts0_6_reg_u *value); - -sw_error_t -qca808x_ptp_tx_seqid_reg_get( - a_uint32_t dev_id, a_uint32_t phy_id, - union ptp_tx_seqid_reg_u *value); - -sw_error_t -qca808x_ptp_tx_seqid_reg_set( - a_uint32_t dev_id, a_uint32_t phy_id, - union ptp_tx_seqid_reg_u *value); - -sw_error_t -qca808x_ptp_tx_portid0_reg_get( - a_uint32_t dev_id, a_uint32_t phy_id, - union ptp_tx_portid0_reg_u *value); - -sw_error_t -qca808x_ptp_tx_portid0_reg_set( - a_uint32_t dev_id, a_uint32_t phy_id, - union ptp_tx_portid0_reg_u *value); - -sw_error_t -qca808x_ptp_tx_portid1_reg_get( - a_uint32_t dev_id, a_uint32_t phy_id, - union ptp_tx_portid1_reg_u *value); - -sw_error_t -qca808x_ptp_tx_portid1_reg_set( - a_uint32_t dev_id, a_uint32_t phy_id, - union ptp_tx_portid1_reg_u *value); - -sw_error_t -qca808x_ptp_tx_portid2_reg_get( - a_uint32_t dev_id, a_uint32_t phy_id, - union ptp_tx_portid2_reg_u *value); - -sw_error_t -qca808x_ptp_tx_portid2_reg_set( - a_uint32_t dev_id, a_uint32_t phy_id, - union ptp_tx_portid2_reg_u *value); - -sw_error_t -qca808x_ptp_tx_portid3_reg_get( - a_uint32_t dev_id, a_uint32_t phy_id, - union ptp_tx_portid3_reg_u *value); - -sw_error_t -qca808x_ptp_tx_portid3_reg_set( - a_uint32_t dev_id, a_uint32_t phy_id, - union ptp_tx_portid3_reg_u *value); - -sw_error_t -qca808x_ptp_tx_portid4_reg_get( - a_uint32_t dev_id, a_uint32_t phy_id, - union ptp_tx_portid4_reg_u *value); - -sw_error_t -qca808x_ptp_tx_portid4_reg_set( - a_uint32_t dev_id, a_uint32_t phy_id, - union ptp_tx_portid4_reg_u *value); - -sw_error_t -qca808x_ptp_tx_ts0_reg_get( - a_uint32_t dev_id, a_uint32_t phy_id, - union ptp_tx_ts0_reg_u *value); - -sw_error_t -qca808x_ptp_tx_ts0_reg_set( - a_uint32_t dev_id, a_uint32_t phy_id, - union ptp_tx_ts0_reg_u *value); - -sw_error_t -qca808x_ptp_tx_ts1_reg_get( - a_uint32_t dev_id, a_uint32_t phy_id, - union ptp_tx_ts1_reg_u *value); - -sw_error_t -qca808x_ptp_tx_ts1_reg_set( - a_uint32_t dev_id, a_uint32_t phy_id, - union ptp_tx_ts1_reg_u *value); - -sw_error_t -qca808x_ptp_tx_ts2_reg_get( - a_uint32_t dev_id, a_uint32_t phy_id, - union ptp_tx_ts2_reg_u *value); - -sw_error_t -qca808x_ptp_tx_ts2_reg_set( - a_uint32_t dev_id, a_uint32_t phy_id, - union ptp_tx_ts2_reg_u *value); - -sw_error_t -qca808x_ptp_tx_ts3_reg_get( - a_uint32_t dev_id, a_uint32_t phy_id, - union ptp_tx_ts3_reg_u *value); - -sw_error_t -qca808x_ptp_tx_ts3_reg_set( - a_uint32_t dev_id, a_uint32_t phy_id, - union ptp_tx_ts3_reg_u *value); - -sw_error_t -qca808x_ptp_tx_ts4_reg_get( - a_uint32_t dev_id, a_uint32_t phy_id, - union ptp_tx_ts4_reg_u *value); - -sw_error_t -qca808x_ptp_tx_ts4_reg_set( - a_uint32_t dev_id, a_uint32_t phy_id, - union ptp_tx_ts4_reg_u *value); - -sw_error_t -qca808x_ptp_tx_ts5_reg_get( - a_uint32_t dev_id, a_uint32_t phy_id, - union ptp_tx_ts5_reg_u *value); - -sw_error_t -qca808x_ptp_tx_ts5_reg_set( - a_uint32_t dev_id, a_uint32_t phy_id, - union ptp_tx_ts5_reg_u *value); - -sw_error_t -qca808x_ptp_tx_ts6_reg_get( - a_uint32_t dev_id, a_uint32_t phy_id, - union ptp_tx_ts6_reg_u *value); - -sw_error_t -qca808x_ptp_tx_ts6_reg_set( - a_uint32_t dev_id, a_uint32_t phy_id, - union ptp_tx_ts6_reg_u *value); - -sw_error_t -qca808x_ptp_orig_corr0_reg_get( - a_uint32_t dev_id, a_uint32_t phy_id, - union ptp_orig_corr0_reg_u *value); - -sw_error_t -qca808x_ptp_orig_corr0_reg_set( - a_uint32_t dev_id, a_uint32_t phy_id, - union ptp_orig_corr0_reg_u *value); - -sw_error_t -qca808x_ptp_orig_corr1_reg_get( - a_uint32_t dev_id, a_uint32_t phy_id, - union ptp_orig_corr1_reg_u *value); - -sw_error_t -qca808x_ptp_orig_corr1_reg_set( - a_uint32_t dev_id, a_uint32_t phy_id, - union ptp_orig_corr1_reg_u *value); - -sw_error_t -qca808x_ptp_orig_corr2_reg_get( - a_uint32_t dev_id, a_uint32_t phy_id, - union ptp_orig_corr2_reg_u *value); - -sw_error_t -qca808x_ptp_orig_corr2_reg_set( - a_uint32_t dev_id, a_uint32_t phy_id, - union ptp_orig_corr2_reg_u *value); - -sw_error_t -qca808x_ptp_orig_corr3_reg_get( - a_uint32_t dev_id, a_uint32_t phy_id, - union ptp_orig_corr3_reg_u *value); - -sw_error_t -qca808x_ptp_orig_corr3_reg_set( - a_uint32_t dev_id, a_uint32_t phy_id, - union ptp_orig_corr3_reg_u *value); - -sw_error_t -qca808x_ptp_in_trig0_reg_get( - a_uint32_t dev_id, a_uint32_t phy_id, - union ptp_in_trig0_reg_u *value); - -sw_error_t -qca808x_ptp_in_trig0_reg_set( - a_uint32_t dev_id, a_uint32_t phy_id, - union ptp_in_trig0_reg_u *value); - -sw_error_t -qca808x_ptp_in_trig1_reg_get( - a_uint32_t dev_id, a_uint32_t phy_id, - union ptp_in_trig1_reg_u *value); - -sw_error_t -qca808x_ptp_in_trig1_reg_set( - a_uint32_t dev_id, a_uint32_t phy_id, - union ptp_in_trig1_reg_u *value); - -sw_error_t -qca808x_ptp_in_trig2_reg_get( - a_uint32_t dev_id, a_uint32_t phy_id, - union ptp_in_trig2_reg_u *value); - -sw_error_t -qca808x_ptp_in_trig2_reg_set( - a_uint32_t dev_id, a_uint32_t phy_id, - union ptp_in_trig2_reg_u *value); - -sw_error_t -qca808x_ptp_in_trig3_reg_get( - a_uint32_t dev_id, a_uint32_t phy_id, - union ptp_in_trig3_reg_u *value); - -sw_error_t -qca808x_ptp_in_trig3_reg_set( - a_uint32_t dev_id, a_uint32_t phy_id, - union ptp_in_trig3_reg_u *value); - -sw_error_t -qca808x_ptp_tx_latency_reg_get( - a_uint32_t dev_id, a_uint32_t phy_id, - union ptp_tx_latency_reg_u *value); - -sw_error_t -qca808x_ptp_tx_latency_reg_set( - a_uint32_t dev_id, a_uint32_t phy_id, - union ptp_tx_latency_reg_u *value); - -sw_error_t -qca808x_ptp_rtc_inc0_reg_get( - a_uint32_t dev_id, a_uint32_t phy_id, - union ptp_rtc_inc0_reg_u *value); - -sw_error_t -qca808x_ptp_rtc_inc0_reg_set( - a_uint32_t dev_id, a_uint32_t phy_id, - union ptp_rtc_inc0_reg_u *value); - -sw_error_t -qca808x_ptp_rtc_inc1_reg_get( - a_uint32_t dev_id, a_uint32_t phy_id, - union ptp_rtc_inc1_reg_u *value); - -sw_error_t -qca808x_ptp_rtc_inc1_reg_set( - a_uint32_t dev_id, a_uint32_t phy_id, - union ptp_rtc_inc1_reg_u *value); - -sw_error_t -qca808x_ptp_rtcoffs0_reg_get( - a_uint32_t dev_id, a_uint32_t phy_id, - union ptp_rtcoffs0_reg_u *value); - -sw_error_t -qca808x_ptp_rtcoffs0_reg_set( - a_uint32_t dev_id, a_uint32_t phy_id, - union ptp_rtcoffs0_reg_u *value); - -sw_error_t -qca808x_ptp_rtcoffs1_reg_get( - a_uint32_t dev_id, a_uint32_t phy_id, - union ptp_rtcoffs1_reg_u *value); - -sw_error_t -qca808x_ptp_rtcoffs1_reg_set( - a_uint32_t dev_id, a_uint32_t phy_id, - union ptp_rtcoffs1_reg_u *value); - -sw_error_t -qca808x_ptp_rtcoffs2_reg_get( - a_uint32_t dev_id, a_uint32_t phy_id, - union ptp_rtcoffs2_reg_u *value); - -sw_error_t -qca808x_ptp_rtcoffs2_reg_set( - a_uint32_t dev_id, a_uint32_t phy_id, - union ptp_rtcoffs2_reg_u *value); - -sw_error_t -qca808x_ptp_rtcoffs3_reg_get( - a_uint32_t dev_id, a_uint32_t phy_id, - union ptp_rtcoffs3_reg_u *value); - -sw_error_t -qca808x_ptp_rtcoffs3_reg_set( - a_uint32_t dev_id, a_uint32_t phy_id, - union ptp_rtcoffs3_reg_u *value); - -sw_error_t -qca808x_ptp_rtcoffs4_reg_get( - a_uint32_t dev_id, a_uint32_t phy_id, - union ptp_rtcoffs4_reg_u *value); - -sw_error_t -qca808x_ptp_rtcoffs4_reg_set( - a_uint32_t dev_id, a_uint32_t phy_id, - union ptp_rtcoffs4_reg_u *value); - -sw_error_t -qca808x_ptp_rtc0_reg_get( - a_uint32_t dev_id, a_uint32_t phy_id, - union ptp_rtc0_reg_u *value); - -sw_error_t -qca808x_ptp_rtc0_reg_set( - a_uint32_t dev_id, a_uint32_t phy_id, - union ptp_rtc0_reg_u *value); - -sw_error_t -qca808x_ptp_rtc1_reg_get( - a_uint32_t dev_id, a_uint32_t phy_id, - union ptp_rtc1_reg_u *value); - -sw_error_t -qca808x_ptp_rtc1_reg_set( - a_uint32_t dev_id, a_uint32_t phy_id, - union ptp_rtc1_reg_u *value); - -sw_error_t -qca808x_ptp_rtc2_reg_get( - a_uint32_t dev_id, a_uint32_t phy_id, - union ptp_rtc2_reg_u *value); - -sw_error_t -qca808x_ptp_rtc2_reg_set( - a_uint32_t dev_id, a_uint32_t phy_id, - union ptp_rtc2_reg_u *value); - -sw_error_t -qca808x_ptp_rtc3_reg_get( - a_uint32_t dev_id, a_uint32_t phy_id, - union ptp_rtc3_reg_u *value); - -sw_error_t -qca808x_ptp_rtc3_reg_set( - a_uint32_t dev_id, a_uint32_t phy_id, - union ptp_rtc3_reg_u *value); - -sw_error_t -qca808x_ptp_rtc4_reg_get( - a_uint32_t dev_id, a_uint32_t phy_id, - union ptp_rtc4_reg_u *value); - -sw_error_t -qca808x_ptp_rtc4_reg_set( - a_uint32_t dev_id, a_uint32_t phy_id, - union ptp_rtc4_reg_u *value); - -sw_error_t -qca808x_ptp_rtc5_reg_get( - a_uint32_t dev_id, a_uint32_t phy_id, - union ptp_rtc5_reg_u *value); - -sw_error_t -qca808x_ptp_rtc5_reg_set( - a_uint32_t dev_id, a_uint32_t phy_id, - union ptp_rtc5_reg_u *value); - -sw_error_t -qca808x_ptp_rtc6_reg_get( - a_uint32_t dev_id, a_uint32_t phy_id, - union ptp_rtc6_reg_u *value); - -sw_error_t -qca808x_ptp_rtc6_reg_set( - a_uint32_t dev_id, a_uint32_t phy_id, - union ptp_rtc6_reg_u *value); - -sw_error_t -qca808x_ptp_rtcoffs_valid_reg_get( - a_uint32_t dev_id, a_uint32_t phy_id, - union ptp_rtcoffs_valid_reg_u *value); - -sw_error_t -qca808x_ptp_rtcoffs_valid_reg_set( - a_uint32_t dev_id, a_uint32_t phy_id, - union ptp_rtcoffs_valid_reg_u *value); - -sw_error_t -qca808x_ptp_misc_config_reg_get( - a_uint32_t dev_id, a_uint32_t phy_id, - union ptp_misc_config_reg_u *value); - -sw_error_t -qca808x_ptp_misc_config_reg_set( - a_uint32_t dev_id, a_uint32_t phy_id, - union ptp_misc_config_reg_u *value); - -sw_error_t -qca808x_ptp_ext_imr_reg_get( - a_uint32_t dev_id, a_uint32_t phy_id, - union ptp_ext_imr_reg_u *value); - -sw_error_t -qca808x_ptp_ext_imr_reg_set( - a_uint32_t dev_id, a_uint32_t phy_id, - union ptp_ext_imr_reg_u *value); - -sw_error_t -qca808x_ptp_ext_isr_reg_get( - a_uint32_t dev_id, a_uint32_t phy_id, - union ptp_ext_isr_reg_u *value); - -sw_error_t -qca808x_ptp_ext_isr_reg_set( - a_uint32_t dev_id, a_uint32_t phy_id, - union ptp_ext_isr_reg_u *value); - -sw_error_t -qca808x_ptp_rtc_ext_conf_reg_get( - a_uint32_t dev_id, a_uint32_t phy_id, - union ptp_rtc_ext_conf_reg_u *value); - -sw_error_t -qca808x_ptp_rtc_ext_conf_reg_set( - a_uint32_t dev_id, a_uint32_t phy_id, - union ptp_rtc_ext_conf_reg_u *value); - -sw_error_t -qca808x_ptp_rtc_preloaded0_reg_get( - a_uint32_t dev_id, a_uint32_t phy_id, - union ptp_rtc_preloaded0_reg_u *value); - -sw_error_t -qca808x_ptp_rtc_preloaded0_reg_set( - a_uint32_t dev_id, a_uint32_t phy_id, - union ptp_rtc_preloaded0_reg_u *value); - -sw_error_t -qca808x_ptp_rtc_preloaded1_reg_get( - a_uint32_t dev_id, a_uint32_t phy_id, - union ptp_rtc_preloaded1_reg_u *value); - -sw_error_t -qca808x_ptp_rtc_preloaded1_reg_set( - a_uint32_t dev_id, a_uint32_t phy_id, - union ptp_rtc_preloaded1_reg_u *value); - -sw_error_t -qca808x_ptp_rtc_preloaded2_reg_get( - a_uint32_t dev_id, a_uint32_t phy_id, - union ptp_rtc_preloaded2_reg_u *value); - -sw_error_t -qca808x_ptp_rtc_preloaded2_reg_set( - a_uint32_t dev_id, a_uint32_t phy_id, - union ptp_rtc_preloaded2_reg_u *value); - -sw_error_t -qca808x_ptp_rtc_preloaded3_reg_get( - a_uint32_t dev_id, a_uint32_t phy_id, - union ptp_rtc_preloaded3_reg_u *value); - -sw_error_t -qca808x_ptp_rtc_preloaded3_reg_set( - a_uint32_t dev_id, a_uint32_t phy_id, - union ptp_rtc_preloaded3_reg_u *value); - -sw_error_t -qca808x_ptp_rtc_preloaded4_reg_get( - a_uint32_t dev_id, a_uint32_t phy_id, - union ptp_rtc_preloaded4_reg_u *value); - -sw_error_t -qca808x_ptp_rtc_preloaded4_reg_set( - a_uint32_t dev_id, a_uint32_t phy_id, - union ptp_rtc_preloaded4_reg_u *value); - -sw_error_t -qca808x_ptp_gm_conf0_reg_get( - a_uint32_t dev_id, a_uint32_t phy_id, - union ptp_gm_conf0_reg_u *value); - -sw_error_t -qca808x_ptp_gm_conf0_reg_set( - a_uint32_t dev_id, a_uint32_t phy_id, - union ptp_gm_conf0_reg_u *value); - -sw_error_t -qca808x_ptp_gm_conf1_reg_get( - a_uint32_t dev_id, a_uint32_t phy_id, - union ptp_gm_conf1_reg_u *value); - -sw_error_t -qca808x_ptp_gm_conf1_reg_set( - a_uint32_t dev_id, a_uint32_t phy_id, - union ptp_gm_conf1_reg_u *value); - -sw_error_t -qca808x_ptp_ppsin_ts0_reg_get( - a_uint32_t dev_id, a_uint32_t phy_id, - union ptp_ppsin_ts0_reg_u *value); - -sw_error_t -qca808x_ptp_ppsin_ts0_reg_set( - a_uint32_t dev_id, a_uint32_t phy_id, - union ptp_ppsin_ts0_reg_u *value); - -sw_error_t -qca808x_ptp_ppsin_ts1_reg_get( - a_uint32_t dev_id, a_uint32_t phy_id, - union ptp_ppsin_ts1_reg_u *value); - -sw_error_t -qca808x_ptp_ppsin_ts1_reg_set( - a_uint32_t dev_id, a_uint32_t phy_id, - union ptp_ppsin_ts1_reg_u *value); - -sw_error_t -qca808x_ptp_ppsin_ts2_reg_get( - a_uint32_t dev_id, a_uint32_t phy_id, - union ptp_ppsin_ts2_reg_u *value); - -sw_error_t -qca808x_ptp_ppsin_ts2_reg_set( - a_uint32_t dev_id, a_uint32_t phy_id, - union ptp_ppsin_ts2_reg_u *value); - -sw_error_t -qca808x_ptp_ppsin_ts3_reg_get( - a_uint32_t dev_id, a_uint32_t phy_id, - union ptp_ppsin_ts3_reg_u *value); - -sw_error_t -qca808x_ptp_ppsin_ts3_reg_set( - a_uint32_t dev_id, a_uint32_t phy_id, - union ptp_ppsin_ts3_reg_u *value); - -sw_error_t -qca808x_ptp_ppsin_ts4_reg_get( - a_uint32_t dev_id, a_uint32_t phy_id, - union ptp_ppsin_ts4_reg_u *value); - -sw_error_t -qca808x_ptp_ppsin_ts4_reg_set( - a_uint32_t dev_id, a_uint32_t phy_id, - union ptp_ppsin_ts4_reg_u *value); - -sw_error_t -qca808x_ptp_hwpll_inc0_reg_get( - a_uint32_t dev_id, a_uint32_t phy_id, - union ptp_hwpll_inc0_reg_u *value); - -sw_error_t -qca808x_ptp_hwpll_inc0_reg_set( - a_uint32_t dev_id, a_uint32_t phy_id, - union ptp_hwpll_inc0_reg_u *value); - -sw_error_t -qca808x_ptp_hwpll_inc1_reg_get( - a_uint32_t dev_id, a_uint32_t phy_id, - union ptp_hwpll_inc1_reg_u *value); - -sw_error_t -qca808x_ptp_hwpll_inc1_reg_set( - a_uint32_t dev_id, a_uint32_t phy_id, - union ptp_hwpll_inc1_reg_u *value); - -sw_error_t -qca808x_ptp_ppsin_latency_reg_get( - a_uint32_t dev_id, a_uint32_t phy_id, - union ptp_ppsin_latency_reg_u *value); - -sw_error_t -qca808x_ptp_ppsin_latency_reg_set( - a_uint32_t dev_id, a_uint32_t phy_id, - union ptp_ppsin_latency_reg_u *value); - -sw_error_t -qca808x_ptp_trigger0_config_reg_get( - a_uint32_t dev_id, a_uint32_t phy_id, - union ptp_trigger0_config_reg_u *value); - -sw_error_t -qca808x_ptp_trigger0_config_reg_set( - a_uint32_t dev_id, a_uint32_t phy_id, - union ptp_trigger0_config_reg_u *value); - -sw_error_t -qca808x_ptp_trigger0_status_reg_get( - a_uint32_t dev_id, a_uint32_t phy_id, - union ptp_trigger0_status_reg_u *value); - -sw_error_t -qca808x_ptp_trigger0_status_reg_set( - a_uint32_t dev_id, a_uint32_t phy_id, - union ptp_trigger0_status_reg_u *value); - -sw_error_t -qca808x_ptp_trigger1_config_reg_get( - a_uint32_t dev_id, a_uint32_t phy_id, - union ptp_trigger1_config_reg_u *value); - -sw_error_t -qca808x_ptp_trigger1_config_reg_set( - a_uint32_t dev_id, a_uint32_t phy_id, - union ptp_trigger1_config_reg_u *value); - -sw_error_t -qca808x_ptp_trigger1_status_reg_get( - a_uint32_t dev_id, a_uint32_t phy_id, - union ptp_trigger1_status_reg_u *value); - -sw_error_t -qca808x_ptp_trigger1_status_reg_set( - a_uint32_t dev_id, a_uint32_t phy_id, - union ptp_trigger1_status_reg_u *value); - -sw_error_t -qca808x_ptp_trigger0_timestamp0_reg_get( - a_uint32_t dev_id, a_uint32_t phy_id, - union ptp_trigger0_timestamp0_reg_u *value); - -sw_error_t -qca808x_ptp_trigger0_timestamp0_reg_set( - a_uint32_t dev_id, a_uint32_t phy_id, - union ptp_trigger0_timestamp0_reg_u *value); - -sw_error_t -qca808x_ptp_trigger0_timestamp1_reg_get( - a_uint32_t dev_id, a_uint32_t phy_id, - union ptp_trigger0_timestamp1_reg_u *value); - -sw_error_t -qca808x_ptp_trigger0_timestamp1_reg_set( - a_uint32_t dev_id, a_uint32_t phy_id, - union ptp_trigger0_timestamp1_reg_u *value); - -sw_error_t -qca808x_ptp_trigger0_timestamp2_reg_get( - a_uint32_t dev_id, a_uint32_t phy_id, - union ptp_trigger0_timestamp2_reg_u *value); - -sw_error_t -qca808x_ptp_trigger0_timestamp2_reg_set( - a_uint32_t dev_id, a_uint32_t phy_id, - union ptp_trigger0_timestamp2_reg_u *value); - -sw_error_t -qca808x_ptp_trigger0_timestamp3_reg_get( - a_uint32_t dev_id, a_uint32_t phy_id, - union ptp_trigger0_timestamp3_reg_u *value); - -sw_error_t -qca808x_ptp_trigger0_timestamp3_reg_set( - a_uint32_t dev_id, a_uint32_t phy_id, - union ptp_trigger0_timestamp3_reg_u *value); - -sw_error_t -qca808x_ptp_trigger0_timestamp4_reg_get( - a_uint32_t dev_id, a_uint32_t phy_id, - union ptp_trigger0_timestamp4_reg_u *value); - -sw_error_t -qca808x_ptp_trigger0_timestamp4_reg_set( - a_uint32_t dev_id, a_uint32_t phy_id, - union ptp_trigger0_timestamp4_reg_u *value); - -sw_error_t -qca808x_ptp_trigger1_timestamp0_reg_get( - a_uint32_t dev_id, a_uint32_t phy_id, - union ptp_trigger1_timestamp0_reg_u *value); - -sw_error_t -qca808x_ptp_trigger1_timestamp0_reg_set( - a_uint32_t dev_id, a_uint32_t phy_id, - union ptp_trigger1_timestamp0_reg_u *value); - -sw_error_t -qca808x_ptp_trigger1_timestamp1_reg_get( - a_uint32_t dev_id, a_uint32_t phy_id, - union ptp_trigger1_timestamp1_reg_u *value); - -sw_error_t -qca808x_ptp_trigger1_timestamp1_reg_set( - a_uint32_t dev_id, a_uint32_t phy_id, - union ptp_trigger1_timestamp1_reg_u *value); - -sw_error_t -qca808x_ptp_trigger1_timestamp2_reg_get( - a_uint32_t dev_id, a_uint32_t phy_id, - union ptp_trigger1_timestamp2_reg_u *value); - -sw_error_t -qca808x_ptp_trigger1_timestamp2_reg_set( - a_uint32_t dev_id, a_uint32_t phy_id, - union ptp_trigger1_timestamp2_reg_u *value); - -sw_error_t -qca808x_ptp_trigger1_timestamp3_reg_get( - a_uint32_t dev_id, a_uint32_t phy_id, - union ptp_trigger1_timestamp3_reg_u *value); - -sw_error_t -qca808x_ptp_trigger1_timestamp3_reg_set( - a_uint32_t dev_id, a_uint32_t phy_id, - union ptp_trigger1_timestamp3_reg_u *value); - -sw_error_t -qca808x_ptp_trigger1_timestamp4_reg_get( - a_uint32_t dev_id, a_uint32_t phy_id, - union ptp_trigger1_timestamp4_reg_u *value); - -sw_error_t -qca808x_ptp_trigger1_timestamp4_reg_set( - a_uint32_t dev_id, a_uint32_t phy_id, - union ptp_trigger1_timestamp4_reg_u *value); - -sw_error_t -qca808x_ptp_event0_config_reg_get( - a_uint32_t dev_id, a_uint32_t phy_id, - union ptp_event0_config_reg_u *value); - -sw_error_t -qca808x_ptp_event0_config_reg_set( - a_uint32_t dev_id, a_uint32_t phy_id, - union ptp_event0_config_reg_u *value); - -sw_error_t -qca808x_ptp_event0_status_reg_get( - a_uint32_t dev_id, a_uint32_t phy_id, - union ptp_event0_status_reg_u *value); - -sw_error_t -qca808x_ptp_event0_status_reg_set( - a_uint32_t dev_id, a_uint32_t phy_id, - union ptp_event0_status_reg_u *value); - -sw_error_t -qca808x_ptp_event1_config_reg_get( - a_uint32_t dev_id, a_uint32_t phy_id, - union ptp_event1_config_reg_u *value); - -sw_error_t -qca808x_ptp_event1_config_reg_set( - a_uint32_t dev_id, a_uint32_t phy_id, - union ptp_event1_config_reg_u *value); - -sw_error_t -qca808x_ptp_event1_status_reg_get( - a_uint32_t dev_id, a_uint32_t phy_id, - union ptp_event1_status_reg_u *value); - -sw_error_t -qca808x_ptp_event1_status_reg_set( - a_uint32_t dev_id, a_uint32_t phy_id, - union ptp_event1_status_reg_u *value); - -sw_error_t -qca808x_ptp_event0_timestamp0_reg_get( - a_uint32_t dev_id, a_uint32_t phy_id, - union ptp_event0_timestamp0_reg_u *value); - -sw_error_t -qca808x_ptp_event0_timestamp0_reg_set( - a_uint32_t dev_id, a_uint32_t phy_id, - union ptp_event0_timestamp0_reg_u *value); - -sw_error_t -qca808x_ptp_event0_timestamp1_reg_get( - a_uint32_t dev_id, a_uint32_t phy_id, - union ptp_event0_timestamp1_reg_u *value); - -sw_error_t -qca808x_ptp_event0_timestamp1_reg_set( - a_uint32_t dev_id, a_uint32_t phy_id, - union ptp_event0_timestamp1_reg_u *value); - -sw_error_t -qca808x_ptp_event0_timestamp2_reg_get( - a_uint32_t dev_id, a_uint32_t phy_id, - union ptp_event0_timestamp2_reg_u *value); - -sw_error_t -qca808x_ptp_event0_timestamp2_reg_set( - a_uint32_t dev_id, a_uint32_t phy_id, - union ptp_event0_timestamp2_reg_u *value); - -sw_error_t -qca808x_ptp_event0_timestamp3_reg_get( - a_uint32_t dev_id, a_uint32_t phy_id, - union ptp_event0_timestamp3_reg_u *value); - -sw_error_t -qca808x_ptp_event0_timestamp3_reg_set( - a_uint32_t dev_id, a_uint32_t phy_id, - union ptp_event0_timestamp3_reg_u *value); - -sw_error_t -qca808x_ptp_event0_timestamp4_reg_get( - a_uint32_t dev_id, a_uint32_t phy_id, - union ptp_event0_timestamp4_reg_u *value); - -sw_error_t -qca808x_ptp_event0_timestamp4_reg_set( - a_uint32_t dev_id, a_uint32_t phy_id, - union ptp_event0_timestamp4_reg_u *value); - -sw_error_t -qca808x_ptp_event1_timestamp0_reg_get( - a_uint32_t dev_id, a_uint32_t phy_id, - union ptp_event1_timestamp0_reg_u *value); - -sw_error_t -qca808x_ptp_event1_timestamp0_reg_set( - a_uint32_t dev_id, a_uint32_t phy_id, - union ptp_event1_timestamp0_reg_u *value); - -sw_error_t -qca808x_ptp_event1_timestamp1_reg_get( - a_uint32_t dev_id, a_uint32_t phy_id, - union ptp_event1_timestamp1_reg_u *value); - -sw_error_t -qca808x_ptp_event1_timestamp1_reg_set( - a_uint32_t dev_id, a_uint32_t phy_id, - union ptp_event1_timestamp1_reg_u *value); - -sw_error_t -qca808x_ptp_event1_timestamp2_reg_get( - a_uint32_t dev_id, a_uint32_t phy_id, - union ptp_event1_timestamp2_reg_u *value); - -sw_error_t -qca808x_ptp_event1_timestamp2_reg_set( - a_uint32_t dev_id, a_uint32_t phy_id, - union ptp_event1_timestamp2_reg_u *value); - -sw_error_t -qca808x_ptp_event1_timestamp3_reg_get( - a_uint32_t dev_id, a_uint32_t phy_id, - union ptp_event1_timestamp3_reg_u *value); - -sw_error_t -qca808x_ptp_event1_timestamp3_reg_set( - a_uint32_t dev_id, a_uint32_t phy_id, - union ptp_event1_timestamp3_reg_u *value); - -sw_error_t -qca808x_ptp_event1_timestamp4_reg_get( - a_uint32_t dev_id, a_uint32_t phy_id, - union ptp_event1_timestamp4_reg_u *value); - -sw_error_t -qca808x_ptp_event1_timestamp4_reg_set( - a_uint32_t dev_id, a_uint32_t phy_id, - union ptp_event1_timestamp4_reg_u *value); - -sw_error_t -qca808x_ptp_rx_seqid1_reg_get( - a_uint32_t dev_id, a_uint32_t phy_id, - union ptp_rx_seqid1_reg_u *value); - -sw_error_t -qca808x_ptp_rx_seqid1_reg_set( - a_uint32_t dev_id, a_uint32_t phy_id, - union ptp_rx_seqid1_reg_u *value); - -sw_error_t -qca808x_ptp_rx_portid1_0_reg_get( - a_uint32_t dev_id, a_uint32_t phy_id, - union ptp_rx_portid1_0_reg_u *value); - -sw_error_t -qca808x_ptp_rx_portid1_0_reg_set( - a_uint32_t dev_id, a_uint32_t phy_id, - union ptp_rx_portid1_0_reg_u *value); - -sw_error_t -qca808x_ptp_rx_portid1_1_reg_get( - a_uint32_t dev_id, a_uint32_t phy_id, - union ptp_rx_portid1_1_reg_u *value); - -sw_error_t -qca808x_ptp_rx_portid1_1_reg_set( - a_uint32_t dev_id, a_uint32_t phy_id, - union ptp_rx_portid1_1_reg_u *value); - -sw_error_t -qca808x_ptp_rx_portid1_2_reg_get( - a_uint32_t dev_id, a_uint32_t phy_id, - union ptp_rx_portid1_2_reg_u *value); - -sw_error_t -qca808x_ptp_rx_portid1_2_reg_set( - a_uint32_t dev_id, a_uint32_t phy_id, - union ptp_rx_portid1_2_reg_u *value); - -sw_error_t -qca808x_ptp_rx_portid1_3_reg_get( - a_uint32_t dev_id, a_uint32_t phy_id, - union ptp_rx_portid1_3_reg_u *value); - -sw_error_t -qca808x_ptp_rx_portid1_3_reg_set( - a_uint32_t dev_id, a_uint32_t phy_id, - union ptp_rx_portid1_3_reg_u *value); - -sw_error_t -qca808x_ptp_rx_portid1_4_reg_get( - a_uint32_t dev_id, a_uint32_t phy_id, - union ptp_rx_portid1_4_reg_u *value); - -sw_error_t -qca808x_ptp_rx_portid1_4_reg_set( - a_uint32_t dev_id, a_uint32_t phy_id, - union ptp_rx_portid1_4_reg_u *value); - -sw_error_t -qca808x_ptp_rx_ts1_0_reg_get( - a_uint32_t dev_id, a_uint32_t phy_id, - union ptp_rx_ts1_0_reg_u *value); - -sw_error_t -qca808x_ptp_rx_ts1_0_reg_set( - a_uint32_t dev_id, a_uint32_t phy_id, - union ptp_rx_ts1_0_reg_u *value); - -sw_error_t -qca808x_ptp_rx_ts1_1_reg_get( - a_uint32_t dev_id, a_uint32_t phy_id, - union ptp_rx_ts1_1_reg_u *value); - -sw_error_t -qca808x_ptp_rx_ts1_1_reg_set( - a_uint32_t dev_id, a_uint32_t phy_id, - union ptp_rx_ts1_1_reg_u *value); - -sw_error_t -qca808x_ptp_rx_ts1_2_reg_get( - a_uint32_t dev_id, a_uint32_t phy_id, - union ptp_rx_ts1_2_reg_u *value); - -sw_error_t -qca808x_ptp_rx_ts1_2_reg_set( - a_uint32_t dev_id, a_uint32_t phy_id, - union ptp_rx_ts1_2_reg_u *value); - -sw_error_t -qca808x_ptp_rx_ts1_3_reg_get( - a_uint32_t dev_id, a_uint32_t phy_id, - union ptp_rx_ts1_3_reg_u *value); - -sw_error_t -qca808x_ptp_rx_ts1_3_reg_set( - a_uint32_t dev_id, a_uint32_t phy_id, - union ptp_rx_ts1_3_reg_u *value); - -sw_error_t -qca808x_ptp_rx_ts1_4_reg_get( - a_uint32_t dev_id, a_uint32_t phy_id, - union ptp_rx_ts1_4_reg_u *value); - -sw_error_t -qca808x_ptp_rx_ts1_4_reg_set( - a_uint32_t dev_id, a_uint32_t phy_id, - union ptp_rx_ts1_4_reg_u *value); - -sw_error_t -qca808x_ptp_rx_ts1_5_reg_get( - a_uint32_t dev_id, a_uint32_t phy_id, - union ptp_rx_ts1_5_reg_u *value); - -sw_error_t -qca808x_ptp_rx_ts1_5_reg_set( - a_uint32_t dev_id, a_uint32_t phy_id, - union ptp_rx_ts1_5_reg_u *value); - -sw_error_t -qca808x_ptp_rx_ts1_6_reg_get( - a_uint32_t dev_id, a_uint32_t phy_id, - union ptp_rx_ts1_6_reg_u *value); - -sw_error_t -qca808x_ptp_rx_ts1_6_reg_set( - a_uint32_t dev_id, a_uint32_t phy_id, - union ptp_rx_ts1_6_reg_u *value); - -sw_error_t -qca808x_ptp_rx_seqid2_reg_get( - a_uint32_t dev_id, a_uint32_t phy_id, - union ptp_rx_seqid2_reg_u *value); - -sw_error_t -qca808x_ptp_rx_seqid2_reg_set( - a_uint32_t dev_id, a_uint32_t phy_id, - union ptp_rx_seqid2_reg_u *value); - -sw_error_t -qca808x_ptp_rx_portid2_0_reg_get( - a_uint32_t dev_id, a_uint32_t phy_id, - union ptp_rx_portid2_0_reg_u *value); - -sw_error_t -qca808x_ptp_rx_portid2_0_reg_set( - a_uint32_t dev_id, a_uint32_t phy_id, - union ptp_rx_portid2_0_reg_u *value); - -sw_error_t -qca808x_ptp_rx_portid2_1_reg_get( - a_uint32_t dev_id, a_uint32_t phy_id, - union ptp_rx_portid2_1_reg_u *value); - -sw_error_t -qca808x_ptp_rx_portid2_1_reg_set( - a_uint32_t dev_id, a_uint32_t phy_id, - union ptp_rx_portid2_1_reg_u *value); - -sw_error_t -qca808x_ptp_rx_portid2_2_reg_get( - a_uint32_t dev_id, a_uint32_t phy_id, - union ptp_rx_portid2_2_reg_u *value); - -sw_error_t -qca808x_ptp_rx_portid2_2_reg_set( - a_uint32_t dev_id, a_uint32_t phy_id, - union ptp_rx_portid2_2_reg_u *value); - -sw_error_t -qca808x_ptp_rx_portid2_3_reg_get( - a_uint32_t dev_id, a_uint32_t phy_id, - union ptp_rx_portid2_3_reg_u *value); - -sw_error_t -qca808x_ptp_rx_portid2_3_reg_set( - a_uint32_t dev_id, a_uint32_t phy_id, - union ptp_rx_portid2_3_reg_u *value); - -sw_error_t -qca808x_ptp_rx_portid2_4_reg_get( - a_uint32_t dev_id, a_uint32_t phy_id, - union ptp_rx_portid2_4_reg_u *value); - -sw_error_t -qca808x_ptp_rx_portid2_4_reg_set( - a_uint32_t dev_id, a_uint32_t phy_id, - union ptp_rx_portid2_4_reg_u *value); - -sw_error_t -qca808x_ptp_rx_ts2_0_reg_get( - a_uint32_t dev_id, a_uint32_t phy_id, - union ptp_rx_ts2_0_reg_u *value); - -sw_error_t -qca808x_ptp_rx_ts2_0_reg_set( - a_uint32_t dev_id, a_uint32_t phy_id, - union ptp_rx_ts2_0_reg_u *value); - -sw_error_t -qca808x_ptp_rx_ts2_1_reg_get( - a_uint32_t dev_id, a_uint32_t phy_id, - union ptp_rx_ts2_1_reg_u *value); - -sw_error_t -qca808x_ptp_rx_ts2_1_reg_set( - a_uint32_t dev_id, a_uint32_t phy_id, - union ptp_rx_ts2_1_reg_u *value); - -sw_error_t -qca808x_ptp_rx_ts2_2_reg_get( - a_uint32_t dev_id, a_uint32_t phy_id, - union ptp_rx_ts2_2_reg_u *value); - -sw_error_t -qca808x_ptp_rx_ts2_2_reg_set( - a_uint32_t dev_id, a_uint32_t phy_id, - union ptp_rx_ts2_2_reg_u *value); - -sw_error_t -qca808x_ptp_rx_ts2_3_reg_get( - a_uint32_t dev_id, a_uint32_t phy_id, - union ptp_rx_ts2_3_reg_u *value); - -sw_error_t -qca808x_ptp_rx_ts2_3_reg_set( - a_uint32_t dev_id, a_uint32_t phy_id, - union ptp_rx_ts2_3_reg_u *value); - -sw_error_t -qca808x_ptp_rx_ts2_4_reg_get( - a_uint32_t dev_id, a_uint32_t phy_id, - union ptp_rx_ts2_4_reg_u *value); - -sw_error_t -qca808x_ptp_rx_ts2_4_reg_set( - a_uint32_t dev_id, a_uint32_t phy_id, - union ptp_rx_ts2_4_reg_u *value); - -sw_error_t -qca808x_ptp_rx_ts2_5_reg_get( - a_uint32_t dev_id, a_uint32_t phy_id, - union ptp_rx_ts2_5_reg_u *value); - -sw_error_t -qca808x_ptp_rx_ts2_5_reg_set( - a_uint32_t dev_id, a_uint32_t phy_id, - union ptp_rx_ts2_5_reg_u *value); - -sw_error_t -qca808x_ptp_rx_ts2_6_reg_get( - a_uint32_t dev_id, a_uint32_t phy_id, - union ptp_rx_ts2_6_reg_u *value); - -sw_error_t -qca808x_ptp_rx_ts2_6_reg_set( - a_uint32_t dev_id, a_uint32_t phy_id, - union ptp_rx_ts2_6_reg_u *value); - -sw_error_t -qca808x_ptp_rx_seqid3_reg_get( - a_uint32_t dev_id, a_uint32_t phy_id, - union ptp_rx_seqid3_reg_u *value); - -sw_error_t -qca808x_ptp_rx_seqid3_reg_set( - a_uint32_t dev_id, a_uint32_t phy_id, - union ptp_rx_seqid3_reg_u *value); - -sw_error_t -qca808x_ptp_rx_portid3_0_reg_get( - a_uint32_t dev_id, a_uint32_t phy_id, - union ptp_rx_portid3_0_reg_u *value); - -sw_error_t -qca808x_ptp_rx_portid3_0_reg_set( - a_uint32_t dev_id, a_uint32_t phy_id, - union ptp_rx_portid3_0_reg_u *value); - -sw_error_t -qca808x_ptp_rx_portid3_1_reg_get( - a_uint32_t dev_id, a_uint32_t phy_id, - union ptp_rx_portid3_1_reg_u *value); - -sw_error_t -qca808x_ptp_rx_portid3_1_reg_set( - a_uint32_t dev_id, a_uint32_t phy_id, - union ptp_rx_portid3_1_reg_u *value); - -sw_error_t -qca808x_ptp_rx_portid3_2_reg_get( - a_uint32_t dev_id, a_uint32_t phy_id, - union ptp_rx_portid3_2_reg_u *value); - -sw_error_t -qca808x_ptp_rx_portid3_2_reg_set( - a_uint32_t dev_id, a_uint32_t phy_id, - union ptp_rx_portid3_2_reg_u *value); - -sw_error_t -qca808x_ptp_rx_portid3_3_reg_get( - a_uint32_t dev_id, a_uint32_t phy_id, - union ptp_rx_portid3_3_reg_u *value); - -sw_error_t -qca808x_ptp_rx_portid3_3_reg_set( - a_uint32_t dev_id, a_uint32_t phy_id, - union ptp_rx_portid3_3_reg_u *value); - -sw_error_t -qca808x_ptp_rx_portid3_4_reg_get( - a_uint32_t dev_id, a_uint32_t phy_id, - union ptp_rx_portid3_4_reg_u *value); - -sw_error_t -qca808x_ptp_rx_portid3_4_reg_set( - a_uint32_t dev_id, a_uint32_t phy_id, - union ptp_rx_portid3_4_reg_u *value); - -sw_error_t -qca808x_ptp_rx_ts3_0_reg_get( - a_uint32_t dev_id, a_uint32_t phy_id, - union ptp_rx_ts3_0_reg_u *value); - -sw_error_t -qca808x_ptp_rx_ts3_0_reg_set( - a_uint32_t dev_id, a_uint32_t phy_id, - union ptp_rx_ts3_0_reg_u *value); - -sw_error_t -qca808x_ptp_rx_ts3_1_reg_get( - a_uint32_t dev_id, a_uint32_t phy_id, - union ptp_rx_ts3_1_reg_u *value); - -sw_error_t -qca808x_ptp_rx_ts3_1_reg_set( - a_uint32_t dev_id, a_uint32_t phy_id, - union ptp_rx_ts3_1_reg_u *value); - -sw_error_t -qca808x_ptp_rx_ts3_2_reg_get( - a_uint32_t dev_id, a_uint32_t phy_id, - union ptp_rx_ts3_2_reg_u *value); - -sw_error_t -qca808x_ptp_rx_ts3_2_reg_set( - a_uint32_t dev_id, a_uint32_t phy_id, - union ptp_rx_ts3_2_reg_u *value); - -sw_error_t -qca808x_ptp_rx_ts3_3_reg_get( - a_uint32_t dev_id, a_uint32_t phy_id, - union ptp_rx_ts3_3_reg_u *value); - -sw_error_t -qca808x_ptp_rx_ts3_3_reg_set( - a_uint32_t dev_id, a_uint32_t phy_id, - union ptp_rx_ts3_3_reg_u *value); - -sw_error_t -qca808x_ptp_rx_ts3_4_reg_get( - a_uint32_t dev_id, a_uint32_t phy_id, - union ptp_rx_ts3_4_reg_u *value); - -sw_error_t -qca808x_ptp_rx_ts3_4_reg_set( - a_uint32_t dev_id, a_uint32_t phy_id, - union ptp_rx_ts3_4_reg_u *value); - -sw_error_t -qca808x_ptp_rx_ts3_5_reg_get( - a_uint32_t dev_id, a_uint32_t phy_id, - union ptp_rx_ts3_5_reg_u *value); - -sw_error_t -qca808x_ptp_rx_ts3_5_reg_set( - a_uint32_t dev_id, a_uint32_t phy_id, - union ptp_rx_ts3_5_reg_u *value); - -sw_error_t -qca808x_ptp_rx_ts3_6_reg_get( - a_uint32_t dev_id, a_uint32_t phy_id, - union ptp_rx_ts3_6_reg_u *value); - -sw_error_t -qca808x_ptp_rx_ts3_6_reg_set( - a_uint32_t dev_id, a_uint32_t phy_id, - union ptp_rx_ts3_6_reg_u *value); - -sw_error_t -qca808x_ptp_imr_reg_mask_bmp_get( - a_uint32_t dev_id, a_uint32_t phy_id, - unsigned int *value); - -sw_error_t -qca808x_ptp_imr_reg_mask_bmp_set( - a_uint32_t dev_id, a_uint32_t phy_id, - unsigned int value); - -sw_error_t -qca808x_ptp_isr_reg_status_bmp_get( - a_uint32_t dev_id, a_uint32_t phy_id, - unsigned int *value); - -sw_error_t -qca808x_ptp_isr_reg_status_bmp_set( - a_uint32_t dev_id, a_uint32_t phy_id, - unsigned int value); - -sw_error_t -qca808x_ptp_hw_enable_reg_ptp_hw_enable_get( - a_uint32_t dev_id, a_uint32_t phy_id, - unsigned int *value); - -sw_error_t -qca808x_ptp_hw_enable_reg_ptp_hw_enable_set( - a_uint32_t dev_id, a_uint32_t phy_id, - unsigned int value); - -sw_error_t -qca808x_ptp_main_conf_reg_ts_attach_mode_get( - a_uint32_t dev_id, a_uint32_t phy_id, - unsigned int *value); - -sw_error_t -qca808x_ptp_main_conf_reg_ts_attach_mode_set( - a_uint32_t dev_id, a_uint32_t phy_id, - unsigned int value); - -sw_error_t -qca808x_ptp_main_conf_reg_ptp_clk_sel_get( - a_uint32_t dev_id, a_uint32_t phy_id, - unsigned int *value); - -sw_error_t -qca808x_ptp_main_conf_reg_ptp_clk_sel_set( - a_uint32_t dev_id, a_uint32_t phy_id, - unsigned int value); - -sw_error_t -qca808x_ptp_main_conf_reg_disable_1588_phy_get( - a_uint32_t dev_id, a_uint32_t phy_id, - unsigned int *value); - -sw_error_t -qca808x_ptp_main_conf_reg_disable_1588_phy_set( - a_uint32_t dev_id, a_uint32_t phy_id, - unsigned int value); - -sw_error_t -qca808x_ptp_main_conf_reg_attach_crc_recal_get( - a_uint32_t dev_id, a_uint32_t phy_id, - unsigned int *value); - -sw_error_t -qca808x_ptp_main_conf_reg_attach_crc_recal_set( - a_uint32_t dev_id, a_uint32_t phy_id, - unsigned int value); - -sw_error_t -qca808x_ptp_main_conf_reg_ipv4_force_checksum_zero_get( - a_uint32_t dev_id, a_uint32_t phy_id, - unsigned int *value); - -sw_error_t -qca808x_ptp_main_conf_reg_ipv4_force_checksum_zero_set( - a_uint32_t dev_id, a_uint32_t phy_id, - unsigned int value); - -sw_error_t -qca808x_ptp_main_conf_reg_ipv6_embed_force_checksum_zero_get( - a_uint32_t dev_id, a_uint32_t phy_id, - unsigned int *value); - -sw_error_t -qca808x_ptp_main_conf_reg_ipv6_embed_force_checksum_zero_set( - a_uint32_t dev_id, a_uint32_t phy_id, - unsigned int value); - -sw_error_t -qca808x_ptp_main_conf_reg_ptp_bypass_get( - a_uint32_t dev_id, a_uint32_t phy_id, - unsigned int *value); - -sw_error_t -qca808x_ptp_main_conf_reg_ptp_bypass_set( - a_uint32_t dev_id, a_uint32_t phy_id, - unsigned int value); - -sw_error_t -qca808x_ptp_main_conf_reg_wol_en_get( - a_uint32_t dev_id, a_uint32_t phy_id, - unsigned int *value); - -sw_error_t -qca808x_ptp_main_conf_reg_wol_en_set( - a_uint32_t dev_id, a_uint32_t phy_id, - unsigned int value); - -sw_error_t -qca808x_ptp_main_conf_reg_ptp_clock_mode_get( - a_uint32_t dev_id, a_uint32_t phy_id, - unsigned int *value); - -sw_error_t -qca808x_ptp_main_conf_reg_ptp_clock_mode_set( - a_uint32_t dev_id, a_uint32_t phy_id, - unsigned int value); - -sw_error_t -qca808x_ptp_rx_seqid0_reg_rx_seqid_get( - a_uint32_t dev_id, a_uint32_t phy_id, - unsigned int *value); - -sw_error_t -qca808x_ptp_rx_seqid0_reg_rx_seqid_set( - a_uint32_t dev_id, a_uint32_t phy_id, - unsigned int value); - -sw_error_t -qca808x_ptp_rx_portid0_0_reg_rx_portid_get( - a_uint32_t dev_id, a_uint32_t phy_id, - unsigned int *value); - -sw_error_t -qca808x_ptp_rx_portid0_0_reg_rx_portid_set( - a_uint32_t dev_id, a_uint32_t phy_id, - unsigned int value); - -sw_error_t -qca808x_ptp_rx_portid0_1_reg_rx_portid_get( - a_uint32_t dev_id, a_uint32_t phy_id, - unsigned int *value); - -sw_error_t -qca808x_ptp_rx_portid0_1_reg_rx_portid_set( - a_uint32_t dev_id, a_uint32_t phy_id, - unsigned int value); - -sw_error_t -qca808x_ptp_rx_portid0_2_reg_rx_portid_get( - a_uint32_t dev_id, a_uint32_t phy_id, - unsigned int *value); - -sw_error_t -qca808x_ptp_rx_portid0_2_reg_rx_portid_set( - a_uint32_t dev_id, a_uint32_t phy_id, - unsigned int value); - -sw_error_t -qca808x_ptp_rx_portid0_3_reg_rx_portid_get( - a_uint32_t dev_id, a_uint32_t phy_id, - unsigned int *value); - -sw_error_t -qca808x_ptp_rx_portid0_3_reg_rx_portid_set( - a_uint32_t dev_id, a_uint32_t phy_id, - unsigned int value); - -sw_error_t -qca808x_ptp_rx_portid0_4_reg_rx_portid_get( - a_uint32_t dev_id, a_uint32_t phy_id, - unsigned int *value); - -sw_error_t -qca808x_ptp_rx_portid0_4_reg_rx_portid_set( - a_uint32_t dev_id, a_uint32_t phy_id, - unsigned int value); - -sw_error_t -qca808x_ptp_rtc_clk_reg_rtc_clk_selection_get( - a_uint32_t dev_id, a_uint32_t phy_id, - unsigned int *value); - -sw_error_t -qca808x_ptp_rtc_clk_reg_rtc_clk_selection_set( - a_uint32_t dev_id, a_uint32_t phy_id, - unsigned int value); - -sw_error_t -qca808x_ptp_rx_ts0_0_reg_rx_ts_sec_get( - a_uint32_t dev_id, a_uint32_t phy_id, - unsigned int *value); - -sw_error_t -qca808x_ptp_rx_ts0_0_reg_rx_ts_sec_set( - a_uint32_t dev_id, a_uint32_t phy_id, - unsigned int value); - -sw_error_t -qca808x_ptp_rx_ts0_1_reg_rx_ts_sec_get( - a_uint32_t dev_id, a_uint32_t phy_id, - unsigned int *value); - -sw_error_t -qca808x_ptp_rx_ts0_1_reg_rx_ts_sec_set( - a_uint32_t dev_id, a_uint32_t phy_id, - unsigned int value); - -sw_error_t -qca808x_ptp_rx_ts0_2_reg_rx_ts_sec_get( - a_uint32_t dev_id, a_uint32_t phy_id, - unsigned int *value); - -sw_error_t -qca808x_ptp_rx_ts0_2_reg_rx_ts_sec_set( - a_uint32_t dev_id, a_uint32_t phy_id, - unsigned int value); - -sw_error_t -qca808x_ptp_rx_ts0_3_reg_rx_ts_nsec_get( - a_uint32_t dev_id, a_uint32_t phy_id, - unsigned int *value); - -sw_error_t -qca808x_ptp_rx_ts0_3_reg_rx_ts_nsec_set( - a_uint32_t dev_id, a_uint32_t phy_id, - unsigned int value); - -sw_error_t -qca808x_ptp_rx_ts0_4_reg_rx_ts_nsec_get( - a_uint32_t dev_id, a_uint32_t phy_id, - unsigned int *value); - -sw_error_t -qca808x_ptp_rx_ts0_4_reg_rx_ts_nsec_set( - a_uint32_t dev_id, a_uint32_t phy_id, - unsigned int value); - -sw_error_t -qca808x_ptp_rx_ts0_5_reg_rx_ts_nfsec_get( - a_uint32_t dev_id, a_uint32_t phy_id, - unsigned int *value); - -sw_error_t -qca808x_ptp_rx_ts0_5_reg_rx_ts_nfsec_set( - a_uint32_t dev_id, a_uint32_t phy_id, - unsigned int value); - -sw_error_t -qca808x_ptp_rx_ts0_5_reg_rx_msg_type_get( - a_uint32_t dev_id, a_uint32_t phy_id, - unsigned int *value); - -sw_error_t -qca808x_ptp_rx_ts0_5_reg_rx_msg_type_set( - a_uint32_t dev_id, a_uint32_t phy_id, - unsigned int value); - -sw_error_t -qca808x_ptp_rx_ts0_6_reg_rx_ts_nfsec_get( - a_uint32_t dev_id, a_uint32_t phy_id, - unsigned int *value); - -sw_error_t -qca808x_ptp_rx_ts0_6_reg_rx_ts_nfsec_set( - a_uint32_t dev_id, a_uint32_t phy_id, - unsigned int value); - -sw_error_t -qca808x_ptp_tx_seqid_reg_tx_seqid_get( - a_uint32_t dev_id, a_uint32_t phy_id, - unsigned int *value); - -sw_error_t -qca808x_ptp_tx_seqid_reg_tx_seqid_set( - a_uint32_t dev_id, a_uint32_t phy_id, - unsigned int value); - -sw_error_t -qca808x_ptp_tx_portid0_reg_tx_portid_get( - a_uint32_t dev_id, a_uint32_t phy_id, - unsigned int *value); - -sw_error_t -qca808x_ptp_tx_portid0_reg_tx_portid_set( - a_uint32_t dev_id, a_uint32_t phy_id, - unsigned int value); - -sw_error_t -qca808x_ptp_tx_portid1_reg_tx_portid_get( - a_uint32_t dev_id, a_uint32_t phy_id, - unsigned int *value); - -sw_error_t -qca808x_ptp_tx_portid1_reg_tx_portid_set( - a_uint32_t dev_id, a_uint32_t phy_id, - unsigned int value); - -sw_error_t -qca808x_ptp_tx_portid2_reg_tx_portid_get( - a_uint32_t dev_id, a_uint32_t phy_id, - unsigned int *value); - -sw_error_t -qca808x_ptp_tx_portid2_reg_tx_portid_set( - a_uint32_t dev_id, a_uint32_t phy_id, - unsigned int value); - -sw_error_t -qca808x_ptp_tx_portid3_reg_tx_portid_get( - a_uint32_t dev_id, a_uint32_t phy_id, - unsigned int *value); - -sw_error_t -qca808x_ptp_tx_portid3_reg_tx_portid_set( - a_uint32_t dev_id, a_uint32_t phy_id, - unsigned int value); - -sw_error_t -qca808x_ptp_tx_portid4_reg_tx_portid_get( - a_uint32_t dev_id, a_uint32_t phy_id, - unsigned int *value); - -sw_error_t -qca808x_ptp_tx_portid4_reg_tx_portid_set( - a_uint32_t dev_id, a_uint32_t phy_id, - unsigned int value); - -sw_error_t -qca808x_ptp_tx_ts0_reg_tx_ts_sec_get( - a_uint32_t dev_id, a_uint32_t phy_id, - unsigned int *value); - -sw_error_t -qca808x_ptp_tx_ts0_reg_tx_ts_sec_set( - a_uint32_t dev_id, a_uint32_t phy_id, - unsigned int value); - -sw_error_t -qca808x_ptp_tx_ts1_reg_tx_ts_sec_get( - a_uint32_t dev_id, a_uint32_t phy_id, - unsigned int *value); - -sw_error_t -qca808x_ptp_tx_ts1_reg_tx_ts_sec_set( - a_uint32_t dev_id, a_uint32_t phy_id, - unsigned int value); - -sw_error_t -qca808x_ptp_tx_ts2_reg_tx_ts_sec_get( - a_uint32_t dev_id, a_uint32_t phy_id, - unsigned int *value); - -sw_error_t -qca808x_ptp_tx_ts2_reg_tx_ts_sec_set( - a_uint32_t dev_id, a_uint32_t phy_id, - unsigned int value); - -sw_error_t -qca808x_ptp_tx_ts3_reg_tx_ts_nsec_get( - a_uint32_t dev_id, a_uint32_t phy_id, - unsigned int *value); - -sw_error_t -qca808x_ptp_tx_ts3_reg_tx_ts_nsec_set( - a_uint32_t dev_id, a_uint32_t phy_id, - unsigned int value); - -sw_error_t -qca808x_ptp_tx_ts4_reg_tx_ts_nsec_get( - a_uint32_t dev_id, a_uint32_t phy_id, - unsigned int *value); - -sw_error_t -qca808x_ptp_tx_ts4_reg_tx_ts_nsec_set( - a_uint32_t dev_id, a_uint32_t phy_id, - unsigned int value); - -sw_error_t -qca808x_ptp_tx_ts5_reg_tx_ts_nfsec_get( - a_uint32_t dev_id, a_uint32_t phy_id, - unsigned int *value); - -sw_error_t -qca808x_ptp_tx_ts5_reg_tx_ts_nfsec_set( - a_uint32_t dev_id, a_uint32_t phy_id, - unsigned int value); - -sw_error_t -qca808x_ptp_tx_ts5_reg_tx_msg_type_get( - a_uint32_t dev_id, a_uint32_t phy_id, - unsigned int *value); - -sw_error_t -qca808x_ptp_tx_ts5_reg_tx_msg_type_set( - a_uint32_t dev_id, a_uint32_t phy_id, - unsigned int value); - -sw_error_t -qca808x_ptp_tx_ts6_reg_tx_ts_nfsec_get( - a_uint32_t dev_id, a_uint32_t phy_id, - unsigned int *value); - -sw_error_t -qca808x_ptp_tx_ts6_reg_tx_ts_nfsec_set( - a_uint32_t dev_id, a_uint32_t phy_id, - unsigned int value); - -sw_error_t -qca808x_ptp_orig_corr0_reg_ptp_orig_corr_get( - a_uint32_t dev_id, a_uint32_t phy_id, - unsigned int *value); - -sw_error_t -qca808x_ptp_orig_corr0_reg_ptp_orig_corr_set( - a_uint32_t dev_id, a_uint32_t phy_id, - unsigned int value); - -sw_error_t -qca808x_ptp_orig_corr1_reg_ptp_orig_corr_get( - a_uint32_t dev_id, a_uint32_t phy_id, - unsigned int *value); - -sw_error_t -qca808x_ptp_orig_corr1_reg_ptp_orig_corr_set( - a_uint32_t dev_id, a_uint32_t phy_id, - unsigned int value); - -sw_error_t -qca808x_ptp_orig_corr2_reg_ptp_orig_corr_get( - a_uint32_t dev_id, a_uint32_t phy_id, - unsigned int *value); - -sw_error_t -qca808x_ptp_orig_corr2_reg_ptp_orig_corr_set( - a_uint32_t dev_id, a_uint32_t phy_id, - unsigned int value); - -sw_error_t -qca808x_ptp_orig_corr3_reg_ptp_orig_corr_get( - a_uint32_t dev_id, a_uint32_t phy_id, - unsigned int *value); - -sw_error_t -qca808x_ptp_orig_corr3_reg_ptp_orig_corr_set( - a_uint32_t dev_id, a_uint32_t phy_id, - unsigned int value); - -sw_error_t -qca808x_ptp_in_trig0_reg_ptp_in_trig_nisec_get( - a_uint32_t dev_id, a_uint32_t phy_id, - unsigned int *value); - -sw_error_t -qca808x_ptp_in_trig0_reg_ptp_in_trig_nisec_set( - a_uint32_t dev_id, a_uint32_t phy_id, - unsigned int value); - -sw_error_t -qca808x_ptp_in_trig1_reg_ptp_in_trig_nisec_get( - a_uint32_t dev_id, a_uint32_t phy_id, - unsigned int *value); - -sw_error_t -qca808x_ptp_in_trig1_reg_ptp_in_trig_nisec_set( - a_uint32_t dev_id, a_uint32_t phy_id, - unsigned int value); - -sw_error_t -qca808x_ptp_in_trig2_reg_ptp_in_trig_nisec_get( - a_uint32_t dev_id, a_uint32_t phy_id, - unsigned int *value); - -sw_error_t -qca808x_ptp_in_trig2_reg_ptp_in_trig_nisec_set( - a_uint32_t dev_id, a_uint32_t phy_id, - unsigned int value); - -sw_error_t -qca808x_ptp_in_trig3_reg_ptp_in_trig_nisec_get( - a_uint32_t dev_id, a_uint32_t phy_id, - unsigned int *value); - -sw_error_t -qca808x_ptp_in_trig3_reg_ptp_in_trig_nisec_set( - a_uint32_t dev_id, a_uint32_t phy_id, - unsigned int value); - -sw_error_t -qca808x_ptp_tx_latency_reg_ptp_tx_latency_get( - a_uint32_t dev_id, a_uint32_t phy_id, - unsigned int *value); - -sw_error_t -qca808x_ptp_tx_latency_reg_ptp_tx_latency_set( - a_uint32_t dev_id, a_uint32_t phy_id, - unsigned int value); - -sw_error_t -qca808x_ptp_rtc_inc0_reg_ptp_rtc_inc_nis_get( - a_uint32_t dev_id, a_uint32_t phy_id, - unsigned int *value); - -sw_error_t -qca808x_ptp_rtc_inc0_reg_ptp_rtc_inc_nis_set( - a_uint32_t dev_id, a_uint32_t phy_id, - unsigned int value); - -sw_error_t -qca808x_ptp_rtc_inc0_reg_ptp_rtc_inc_nfs_get( - a_uint32_t dev_id, a_uint32_t phy_id, - unsigned int *value); - -sw_error_t -qca808x_ptp_rtc_inc0_reg_ptp_rtc_inc_nfs_set( - a_uint32_t dev_id, a_uint32_t phy_id, - unsigned int value); - -sw_error_t -qca808x_ptp_rtc_inc1_reg_ptp_rtc_inc_nfs_get( - a_uint32_t dev_id, a_uint32_t phy_id, - unsigned int *value); - -sw_error_t -qca808x_ptp_rtc_inc1_reg_ptp_rtc_inc_nfs_set( - a_uint32_t dev_id, a_uint32_t phy_id, - unsigned int value); - -sw_error_t -qca808x_ptp_rtcoffs0_reg_ptp_rtcoffs_nsec_get( - a_uint32_t dev_id, a_uint32_t phy_id, - unsigned int *value); - -sw_error_t -qca808x_ptp_rtcoffs0_reg_ptp_rtcoffs_nsec_set( - a_uint32_t dev_id, a_uint32_t phy_id, - unsigned int value); - -sw_error_t -qca808x_ptp_rtcoffs1_reg_ptp_rtcoffs_nsec_get( - a_uint32_t dev_id, a_uint32_t phy_id, - unsigned int *value); - -sw_error_t -qca808x_ptp_rtcoffs1_reg_ptp_rtcoffs_nsec_set( - a_uint32_t dev_id, a_uint32_t phy_id, - unsigned int value); - -sw_error_t -qca808x_ptp_rtcoffs2_reg_ptp_rtcoffs_sec_get( - a_uint32_t dev_id, a_uint32_t phy_id, - unsigned int *value); - -sw_error_t -qca808x_ptp_rtcoffs2_reg_ptp_rtcoffs_sec_set( - a_uint32_t dev_id, a_uint32_t phy_id, - unsigned int value); - -sw_error_t -qca808x_ptp_rtcoffs3_reg_ptp_rtcoffs_sec_get( - a_uint32_t dev_id, a_uint32_t phy_id, - unsigned int *value); - -sw_error_t -qca808x_ptp_rtcoffs3_reg_ptp_rtcoffs_sec_set( - a_uint32_t dev_id, a_uint32_t phy_id, - unsigned int value); - -sw_error_t -qca808x_ptp_rtcoffs4_reg_ptp_rtcoffs_sec_get( - a_uint32_t dev_id, a_uint32_t phy_id, - unsigned int *value); - -sw_error_t -qca808x_ptp_rtcoffs4_reg_ptp_rtcoffs_sec_set( - a_uint32_t dev_id, a_uint32_t phy_id, - unsigned int value); - -sw_error_t -qca808x_ptp_rtc0_reg_ptp_rtc_sec_get( - a_uint32_t dev_id, a_uint32_t phy_id, - unsigned int *value); - -sw_error_t -qca808x_ptp_rtc0_reg_ptp_rtc_sec_set( - a_uint32_t dev_id, a_uint32_t phy_id, - unsigned int value); - -sw_error_t -qca808x_ptp_rtc1_reg_ptp_rtc_sec_get( - a_uint32_t dev_id, a_uint32_t phy_id, - unsigned int *value); - -sw_error_t -qca808x_ptp_rtc1_reg_ptp_rtc_sec_set( - a_uint32_t dev_id, a_uint32_t phy_id, - unsigned int value); - -sw_error_t -qca808x_ptp_rtc2_reg_ptp_rtc_sec_get( - a_uint32_t dev_id, a_uint32_t phy_id, - unsigned int *value); - -sw_error_t -qca808x_ptp_rtc2_reg_ptp_rtc_sec_set( - a_uint32_t dev_id, a_uint32_t phy_id, - unsigned int value); - -sw_error_t -qca808x_ptp_rtc3_reg_ptp_rtc_nisec_get( - a_uint32_t dev_id, a_uint32_t phy_id, - unsigned int *value); - -sw_error_t -qca808x_ptp_rtc3_reg_ptp_rtc_nisec_set( - a_uint32_t dev_id, a_uint32_t phy_id, - unsigned int value); - -sw_error_t -qca808x_ptp_rtc4_reg_ptp_rtc_nisec_get( - a_uint32_t dev_id, a_uint32_t phy_id, - unsigned int *value); - -sw_error_t -qca808x_ptp_rtc4_reg_ptp_rtc_nisec_set( - a_uint32_t dev_id, a_uint32_t phy_id, - unsigned int value); - -sw_error_t -qca808x_ptp_rtc5_reg_ptp_rtc_nfsec_get( - a_uint32_t dev_id, a_uint32_t phy_id, - unsigned int *value); - -sw_error_t -qca808x_ptp_rtc5_reg_ptp_rtc_nfsec_set( - a_uint32_t dev_id, a_uint32_t phy_id, - unsigned int value); - -sw_error_t -qca808x_ptp_rtc6_reg_ptp_rtc_nfsec_get( - a_uint32_t dev_id, a_uint32_t phy_id, - unsigned int *value); - -sw_error_t -qca808x_ptp_rtc6_reg_ptp_rtc_nfsec_set( - a_uint32_t dev_id, a_uint32_t phy_id, - unsigned int value); - -sw_error_t -qca808x_ptp_rtcoffs_valid_reg_ptp_rtcoffs_valid_get( - a_uint32_t dev_id, a_uint32_t phy_id, - unsigned int *value); - -sw_error_t -qca808x_ptp_rtcoffs_valid_reg_ptp_rtcoffs_valid_set( - a_uint32_t dev_id, a_uint32_t phy_id, - unsigned int value); - -sw_error_t -qca808x_ptp_misc_config_reg_ptp_ver_chk_en_get( - a_uint32_t dev_id, a_uint32_t phy_id, - unsigned int *value); - -sw_error_t -qca808x_ptp_misc_config_reg_ptp_ver_chk_en_set( - a_uint32_t dev_id, a_uint32_t phy_id, - unsigned int value); - -sw_error_t -qca808x_ptp_misc_config_reg_ipv6_udp_chk_en_get( - a_uint32_t dev_id, a_uint32_t phy_id, - unsigned int *value); - -sw_error_t -qca808x_ptp_misc_config_reg_ipv6_udp_chk_en_set( - a_uint32_t dev_id, a_uint32_t phy_id, - unsigned int value); - -sw_error_t -qca808x_ptp_misc_config_reg_cf_from_pkt_en_get( - a_uint32_t dev_id, a_uint32_t phy_id, - unsigned int *value); - -sw_error_t -qca808x_ptp_misc_config_reg_cf_from_pkt_en_set( - a_uint32_t dev_id, a_uint32_t phy_id, - unsigned int value); - -sw_error_t -qca808x_ptp_misc_config_reg_embed_ingress_time_en_get( - a_uint32_t dev_id, a_uint32_t phy_id, - unsigned int *value); - -sw_error_t -qca808x_ptp_misc_config_reg_embed_ingress_time_en_set( - a_uint32_t dev_id, a_uint32_t phy_id, - unsigned int value); - -sw_error_t -qca808x_ptp_misc_config_reg_ptp_addr_chk_en_get( - a_uint32_t dev_id, a_uint32_t phy_id, - unsigned int *value); - -sw_error_t -qca808x_ptp_misc_config_reg_ptp_addr_chk_en_set( - a_uint32_t dev_id, a_uint32_t phy_id, - unsigned int value); - -sw_error_t -qca808x_ptp_misc_config_reg_crc_validate_en_get( - a_uint32_t dev_id, a_uint32_t phy_id, - unsigned int *value); - -sw_error_t -qca808x_ptp_misc_config_reg_crc_validate_en_set( - a_uint32_t dev_id, a_uint32_t phy_id, - unsigned int value); - -sw_error_t -qca808x_ptp_misc_config_reg_pkt_one_step_en_get( - a_uint32_t dev_id, a_uint32_t phy_id, - unsigned int *value); - -sw_error_t -qca808x_ptp_misc_config_reg_pkt_one_step_en_set( - a_uint32_t dev_id, a_uint32_t phy_id, - unsigned int value); - -sw_error_t -qca808x_ptp_misc_config_reg_ptp_version_get( - a_uint32_t dev_id, a_uint32_t phy_id, - unsigned int *value); - -sw_error_t -qca808x_ptp_misc_config_reg_ptp_version_set( - a_uint32_t dev_id, a_uint32_t phy_id, - unsigned int value); - -sw_error_t -qca808x_ptp_misc_config_reg_appended_timestamp_size_get( - a_uint32_t dev_id, a_uint32_t phy_id, - unsigned int *value); - -sw_error_t -qca808x_ptp_misc_config_reg_appended_timestamp_size_set( - a_uint32_t dev_id, a_uint32_t phy_id, - unsigned int value); - -sw_error_t -qca808x_ptp_misc_config_reg_ts_rtc_select_get( - a_uint32_t dev_id, a_uint32_t phy_id, - unsigned int *value); - -sw_error_t -qca808x_ptp_misc_config_reg_ts_rtc_select_set( - a_uint32_t dev_id, a_uint32_t phy_id, - unsigned int value); - -sw_error_t -qca808x_ptp_ext_imr_reg_mask_bmp_get( - a_uint32_t dev_id, a_uint32_t phy_id, - unsigned int *value); - -sw_error_t -qca808x_ptp_ext_imr_reg_mask_bmp_set( - a_uint32_t dev_id, a_uint32_t phy_id, - unsigned int value); - -sw_error_t -qca808x_ptp_ext_isr_reg_status_bmp_get( - a_uint32_t dev_id, a_uint32_t phy_id, - unsigned int *value); - -sw_error_t -qca808x_ptp_ext_isr_reg_status_bmp_set( - a_uint32_t dev_id, a_uint32_t phy_id, - unsigned int value); - -sw_error_t -qca808x_ptp_rtc_ext_conf_reg_rtc_snapshot_get( - a_uint32_t dev_id, a_uint32_t phy_id, - unsigned int *value); - -sw_error_t -qca808x_ptp_rtc_ext_conf_reg_rtc_snapshot_set( - a_uint32_t dev_id, a_uint32_t phy_id, - unsigned int value); - -sw_error_t -qca808x_ptp_rtc_ext_conf_reg_set_incval_mode_get( - a_uint32_t dev_id, a_uint32_t phy_id, - unsigned int *value); - -sw_error_t -qca808x_ptp_rtc_ext_conf_reg_set_incval_mode_set( - a_uint32_t dev_id, a_uint32_t phy_id, - unsigned int value); - -sw_error_t -qca808x_ptp_rtc_ext_conf_reg_load_rtc_get( - a_uint32_t dev_id, a_uint32_t phy_id, - unsigned int *value); - -sw_error_t -qca808x_ptp_rtc_ext_conf_reg_load_rtc_set( - a_uint32_t dev_id, a_uint32_t phy_id, - unsigned int value); - -sw_error_t -qca808x_ptp_rtc_ext_conf_reg_clear_rtc_get( - a_uint32_t dev_id, a_uint32_t phy_id, - unsigned int *value); - -sw_error_t -qca808x_ptp_rtc_ext_conf_reg_clear_rtc_set( - a_uint32_t dev_id, a_uint32_t phy_id, - unsigned int value); - -sw_error_t -qca808x_ptp_rtc_ext_conf_reg_rtc_read_mode_get( - a_uint32_t dev_id, a_uint32_t phy_id, - unsigned int *value); - -sw_error_t -qca808x_ptp_rtc_ext_conf_reg_rtc_read_mode_set( - a_uint32_t dev_id, a_uint32_t phy_id, - unsigned int value); - -sw_error_t -qca808x_ptp_rtc_ext_conf_reg_select_output_waveform_get( - a_uint32_t dev_id, a_uint32_t phy_id, - unsigned int *value); - -sw_error_t -qca808x_ptp_rtc_ext_conf_reg_select_output_waveform_set( - a_uint32_t dev_id, a_uint32_t phy_id, - unsigned int value); - -sw_error_t -qca808x_ptp_rtc_ext_conf_reg_set_incval_valid_get( - a_uint32_t dev_id, a_uint32_t phy_id, - unsigned int *value); - -sw_error_t -qca808x_ptp_rtc_ext_conf_reg_set_incval_valid_set( - a_uint32_t dev_id, a_uint32_t phy_id, - unsigned int value); - -sw_error_t -qca808x_ptp_rtc_preloaded0_reg_ptp_rtc_preloaded_sec_get( - a_uint32_t dev_id, a_uint32_t phy_id, - unsigned int *value); - -sw_error_t -qca808x_ptp_rtc_preloaded0_reg_ptp_rtc_preloaded_sec_set( - a_uint32_t dev_id, a_uint32_t phy_id, - unsigned int value); - -sw_error_t -qca808x_ptp_rtc_preloaded1_reg_ptp_rtc_preloaded_sec_get( - a_uint32_t dev_id, a_uint32_t phy_id, - unsigned int *value); - -sw_error_t -qca808x_ptp_rtc_preloaded1_reg_ptp_rtc_preloaded_sec_set( - a_uint32_t dev_id, a_uint32_t phy_id, - unsigned int value); - -sw_error_t -qca808x_ptp_rtc_preloaded2_reg_ptp_rtc_preloaded_sec_get( - a_uint32_t dev_id, a_uint32_t phy_id, - unsigned int *value); - -sw_error_t -qca808x_ptp_rtc_preloaded2_reg_ptp_rtc_preloaded_sec_set( - a_uint32_t dev_id, a_uint32_t phy_id, - unsigned int value); - -sw_error_t -qca808x_ptp_rtc_preloaded3_reg_ptp_rtc_preloaded_nisec_get( - a_uint32_t dev_id, a_uint32_t phy_id, - unsigned int *value); - -sw_error_t -qca808x_ptp_rtc_preloaded3_reg_ptp_rtc_preloaded_nisec_set( - a_uint32_t dev_id, a_uint32_t phy_id, - unsigned int value); - -sw_error_t -qca808x_ptp_rtc_preloaded4_reg_ptp_rtc_preloaded_nisec_get( - a_uint32_t dev_id, a_uint32_t phy_id, - unsigned int *value); - -sw_error_t -qca808x_ptp_rtc_preloaded4_reg_ptp_rtc_preloaded_nisec_set( - a_uint32_t dev_id, a_uint32_t phy_id, - unsigned int value); - -sw_error_t -qca808x_ptp_gm_conf0_reg_gm_pps_sync_get( - a_uint32_t dev_id, a_uint32_t phy_id, - unsigned int *value); - -sw_error_t -qca808x_ptp_gm_conf0_reg_gm_pps_sync_set( - a_uint32_t dev_id, a_uint32_t phy_id, - unsigned int value); - -sw_error_t -qca808x_ptp_gm_conf0_reg_gm_pll_mode_get( - a_uint32_t dev_id, a_uint32_t phy_id, - unsigned int *value); - -sw_error_t -qca808x_ptp_gm_conf0_reg_gm_pll_mode_set( - a_uint32_t dev_id, a_uint32_t phy_id, - unsigned int value); - -sw_error_t -qca808x_ptp_gm_conf0_reg_gm_maxfreq_offset_get( - a_uint32_t dev_id, a_uint32_t phy_id, - unsigned int *value); - -sw_error_t -qca808x_ptp_gm_conf0_reg_gm_maxfreq_offset_set( - a_uint32_t dev_id, a_uint32_t phy_id, - unsigned int value); - -sw_error_t -qca808x_ptp_gm_conf0_reg_grandmaster_mode_get( - a_uint32_t dev_id, a_uint32_t phy_id, - unsigned int *value); - -sw_error_t -qca808x_ptp_gm_conf0_reg_grandmaster_mode_set( - a_uint32_t dev_id, a_uint32_t phy_id, - unsigned int value); - -sw_error_t -qca808x_ptp_gm_conf1_reg_gm_kp_ldn_get( - a_uint32_t dev_id, a_uint32_t phy_id, - unsigned int *value); - -sw_error_t -qca808x_ptp_gm_conf1_reg_gm_kp_ldn_set( - a_uint32_t dev_id, a_uint32_t phy_id, - unsigned int value); - -sw_error_t -qca808x_ptp_gm_conf1_reg_gm_ki_ldn_get( - a_uint32_t dev_id, a_uint32_t phy_id, - unsigned int *value); - -sw_error_t -qca808x_ptp_gm_conf1_reg_gm_ki_ldn_set( - a_uint32_t dev_id, a_uint32_t phy_id, - unsigned int value); - -sw_error_t -qca808x_ptp_ppsin_ts0_reg_rx_ts_sec_get( - a_uint32_t dev_id, a_uint32_t phy_id, - unsigned int *value); - -sw_error_t -qca808x_ptp_ppsin_ts0_reg_rx_ts_sec_set( - a_uint32_t dev_id, a_uint32_t phy_id, - unsigned int value); - -sw_error_t -qca808x_ptp_ppsin_ts1_reg_rx_ts_sec_get( - a_uint32_t dev_id, a_uint32_t phy_id, - unsigned int *value); - -sw_error_t -qca808x_ptp_ppsin_ts1_reg_rx_ts_sec_set( - a_uint32_t dev_id, a_uint32_t phy_id, - unsigned int value); - -sw_error_t -qca808x_ptp_ppsin_ts2_reg_rx_ts_sec_get( - a_uint32_t dev_id, a_uint32_t phy_id, - unsigned int *value); - -sw_error_t -qca808x_ptp_ppsin_ts2_reg_rx_ts_sec_set( - a_uint32_t dev_id, a_uint32_t phy_id, - unsigned int value); - -sw_error_t -qca808x_ptp_ppsin_ts3_reg_rx_ts_nsec_get( - a_uint32_t dev_id, a_uint32_t phy_id, - unsigned int *value); - -sw_error_t -qca808x_ptp_ppsin_ts3_reg_rx_ts_nsec_set( - a_uint32_t dev_id, a_uint32_t phy_id, - unsigned int value); - -sw_error_t -qca808x_ptp_ppsin_ts4_reg_rx_ts_nsec_get( - a_uint32_t dev_id, a_uint32_t phy_id, - unsigned int *value); - -sw_error_t -qca808x_ptp_ppsin_ts4_reg_rx_ts_nsec_set( - a_uint32_t dev_id, a_uint32_t phy_id, - unsigned int value); - -sw_error_t -qca808x_ptp_hwpll_inc0_reg_ptp_rtc_inc_nfs1_get( - a_uint32_t dev_id, a_uint32_t phy_id, - unsigned int *value); - -sw_error_t -qca808x_ptp_hwpll_inc0_reg_ptp_rtc_inc_nfs1_set( - a_uint32_t dev_id, a_uint32_t phy_id, - unsigned int value); - -sw_error_t -qca808x_ptp_hwpll_inc0_reg_ptp_rtc_inc_nis_get( - a_uint32_t dev_id, a_uint32_t phy_id, - unsigned int *value); - -sw_error_t -qca808x_ptp_hwpll_inc0_reg_ptp_rtc_inc_nis_set( - a_uint32_t dev_id, a_uint32_t phy_id, - unsigned int value); - -sw_error_t -qca808x_ptp_hwpll_inc1_reg_ptp_rtc_inc_nfs0_get( - a_uint32_t dev_id, a_uint32_t phy_id, - unsigned int *value); - -sw_error_t -qca808x_ptp_hwpll_inc1_reg_ptp_rtc_inc_nfs0_set( - a_uint32_t dev_id, a_uint32_t phy_id, - unsigned int value); - -sw_error_t -qca808x_ptp_ppsin_latency_reg_ptp_ppsin_latency_sign_get( - a_uint32_t dev_id, a_uint32_t phy_id, - unsigned int *value); - -sw_error_t -qca808x_ptp_ppsin_latency_reg_ptp_ppsin_latency_sign_set( - a_uint32_t dev_id, a_uint32_t phy_id, - unsigned int value); - -sw_error_t -qca808x_ptp_ppsin_latency_reg_ptp_ppsin_latency_value_get( - a_uint32_t dev_id, a_uint32_t phy_id, - unsigned int *value); - -sw_error_t -qca808x_ptp_ppsin_latency_reg_ptp_ppsin_latency_value_set( - a_uint32_t dev_id, a_uint32_t phy_id, - unsigned int value); - -sw_error_t -qca808x_ptp_trigger0_config_reg_force_value_get( - a_uint32_t dev_id, a_uint32_t phy_id, - unsigned int *value); - -sw_error_t -qca808x_ptp_trigger0_config_reg_force_value_set( - a_uint32_t dev_id, a_uint32_t phy_id, - unsigned int value); - -sw_error_t -qca808x_ptp_trigger0_config_reg_pattern_get( - a_uint32_t dev_id, a_uint32_t phy_id, - unsigned int *value); - -sw_error_t -qca808x_ptp_trigger0_config_reg_pattern_set( - a_uint32_t dev_id, a_uint32_t phy_id, - unsigned int value); - -sw_error_t -qca808x_ptp_trigger0_config_reg_status_get( - a_uint32_t dev_id, a_uint32_t phy_id, - unsigned int *value); - -sw_error_t -qca808x_ptp_trigger0_config_reg_status_set( - a_uint32_t dev_id, a_uint32_t phy_id, - unsigned int value); - -sw_error_t -qca808x_ptp_trigger0_config_reg_force_en_get( - a_uint32_t dev_id, a_uint32_t phy_id, - unsigned int *value); - -sw_error_t -qca808x_ptp_trigger0_config_reg_force_en_set( - a_uint32_t dev_id, a_uint32_t phy_id, - unsigned int value); - -sw_error_t -qca808x_ptp_trigger0_config_reg_setting_get( - a_uint32_t dev_id, a_uint32_t phy_id, - unsigned int *value); - -sw_error_t -qca808x_ptp_trigger0_config_reg_setting_set( - a_uint32_t dev_id, a_uint32_t phy_id, - unsigned int value); - -sw_error_t -qca808x_ptp_trigger0_config_reg_notify_get( - a_uint32_t dev_id, a_uint32_t phy_id, - unsigned int *value); - -sw_error_t -qca808x_ptp_trigger0_config_reg_notify_set( - a_uint32_t dev_id, a_uint32_t phy_id, - unsigned int value); - -sw_error_t -qca808x_ptp_trigger0_config_reg_if_late_get( - a_uint32_t dev_id, a_uint32_t phy_id, - unsigned int *value); - -sw_error_t -qca808x_ptp_trigger0_config_reg_if_late_set( - a_uint32_t dev_id, a_uint32_t phy_id, - unsigned int value); - -sw_error_t -qca808x_ptp_trigger0_status_reg_error_get( - a_uint32_t dev_id, a_uint32_t phy_id, - unsigned int *value); - -sw_error_t -qca808x_ptp_trigger0_status_reg_error_set( - a_uint32_t dev_id, a_uint32_t phy_id, - unsigned int value); - -sw_error_t -qca808x_ptp_trigger0_status_reg_active_get( - a_uint32_t dev_id, a_uint32_t phy_id, - unsigned int *value); - -sw_error_t -qca808x_ptp_trigger0_status_reg_active_set( - a_uint32_t dev_id, a_uint32_t phy_id, - unsigned int value); - -sw_error_t -qca808x_ptp_trigger0_status_reg_finished_get( - a_uint32_t dev_id, a_uint32_t phy_id, - unsigned int *value); - -sw_error_t -qca808x_ptp_trigger0_status_reg_finished_set( - a_uint32_t dev_id, a_uint32_t phy_id, - unsigned int value); - -sw_error_t -qca808x_ptp_trigger1_config_reg_force_value_get( - a_uint32_t dev_id, a_uint32_t phy_id, - unsigned int *value); - -sw_error_t -qca808x_ptp_trigger1_config_reg_force_value_set( - a_uint32_t dev_id, a_uint32_t phy_id, - unsigned int value); - -sw_error_t -qca808x_ptp_trigger1_config_reg_pattern_get( - a_uint32_t dev_id, a_uint32_t phy_id, - unsigned int *value); - -sw_error_t -qca808x_ptp_trigger1_config_reg_pattern_set( - a_uint32_t dev_id, a_uint32_t phy_id, - unsigned int value); - -sw_error_t -qca808x_ptp_trigger1_config_reg_status_get( - a_uint32_t dev_id, a_uint32_t phy_id, - unsigned int *value); - -sw_error_t -qca808x_ptp_trigger1_config_reg_status_set( - a_uint32_t dev_id, a_uint32_t phy_id, - unsigned int value); - -sw_error_t -qca808x_ptp_trigger1_config_reg_force_en_get( - a_uint32_t dev_id, a_uint32_t phy_id, - unsigned int *value); - -sw_error_t -qca808x_ptp_trigger1_config_reg_force_en_set( - a_uint32_t dev_id, a_uint32_t phy_id, - unsigned int value); - -sw_error_t -qca808x_ptp_trigger1_config_reg_setting_get( - a_uint32_t dev_id, a_uint32_t phy_id, - unsigned int *value); - -sw_error_t -qca808x_ptp_trigger1_config_reg_setting_set( - a_uint32_t dev_id, a_uint32_t phy_id, - unsigned int value); - -sw_error_t -qca808x_ptp_trigger1_config_reg_notify_get( - a_uint32_t dev_id, a_uint32_t phy_id, - unsigned int *value); - -sw_error_t -qca808x_ptp_trigger1_config_reg_notify_set( - a_uint32_t dev_id, a_uint32_t phy_id, - unsigned int value); - -sw_error_t -qca808x_ptp_trigger1_config_reg_if_late_get( - a_uint32_t dev_id, a_uint32_t phy_id, - unsigned int *value); - -sw_error_t -qca808x_ptp_trigger1_config_reg_if_late_set( - a_uint32_t dev_id, a_uint32_t phy_id, - unsigned int value); - -sw_error_t -qca808x_ptp_trigger1_status_reg_error_get( - a_uint32_t dev_id, a_uint32_t phy_id, - unsigned int *value); - -sw_error_t -qca808x_ptp_trigger1_status_reg_error_set( - a_uint32_t dev_id, a_uint32_t phy_id, - unsigned int value); - -sw_error_t -qca808x_ptp_trigger1_status_reg_active_get( - a_uint32_t dev_id, a_uint32_t phy_id, - unsigned int *value); - -sw_error_t -qca808x_ptp_trigger1_status_reg_active_set( - a_uint32_t dev_id, a_uint32_t phy_id, - unsigned int value); - -sw_error_t -qca808x_ptp_trigger1_status_reg_finished_get( - a_uint32_t dev_id, a_uint32_t phy_id, - unsigned int *value); - -sw_error_t -qca808x_ptp_trigger1_status_reg_finished_set( - a_uint32_t dev_id, a_uint32_t phy_id, - unsigned int value); - -sw_error_t -qca808x_ptp_trigger0_timestamp0_reg_ts_sec_get( - a_uint32_t dev_id, a_uint32_t phy_id, - unsigned int *value); - -sw_error_t -qca808x_ptp_trigger0_timestamp0_reg_ts_sec_set( - a_uint32_t dev_id, a_uint32_t phy_id, - unsigned int value); - -sw_error_t -qca808x_ptp_trigger0_timestamp1_reg_ts_sec_get( - a_uint32_t dev_id, a_uint32_t phy_id, - unsigned int *value); - -sw_error_t -qca808x_ptp_trigger0_timestamp1_reg_ts_sec_set( - a_uint32_t dev_id, a_uint32_t phy_id, - unsigned int value); - -sw_error_t -qca808x_ptp_trigger0_timestamp2_reg_ts_sec_get( - a_uint32_t dev_id, a_uint32_t phy_id, - unsigned int *value); - -sw_error_t -qca808x_ptp_trigger0_timestamp2_reg_ts_sec_set( - a_uint32_t dev_id, a_uint32_t phy_id, - unsigned int value); - -sw_error_t -qca808x_ptp_trigger0_timestamp3_reg_ts_nsec_get( - a_uint32_t dev_id, a_uint32_t phy_id, - unsigned int *value); - -sw_error_t -qca808x_ptp_trigger0_timestamp3_reg_ts_nsec_set( - a_uint32_t dev_id, a_uint32_t phy_id, - unsigned int value); - -sw_error_t -qca808x_ptp_trigger0_timestamp4_reg_ts_nsec_get( - a_uint32_t dev_id, a_uint32_t phy_id, - unsigned int *value); - -sw_error_t -qca808x_ptp_trigger0_timestamp4_reg_ts_nsec_set( - a_uint32_t dev_id, a_uint32_t phy_id, - unsigned int value); - -sw_error_t -qca808x_ptp_trigger1_timestamp0_reg_ts_sec_get( - a_uint32_t dev_id, a_uint32_t phy_id, - unsigned int *value); - -sw_error_t -qca808x_ptp_trigger1_timestamp0_reg_ts_sec_set( - a_uint32_t dev_id, a_uint32_t phy_id, - unsigned int value); - -sw_error_t -qca808x_ptp_trigger1_timestamp1_reg_ts_sec_get( - a_uint32_t dev_id, a_uint32_t phy_id, - unsigned int *value); - -sw_error_t -qca808x_ptp_trigger1_timestamp1_reg_ts_sec_set( - a_uint32_t dev_id, a_uint32_t phy_id, - unsigned int value); - -sw_error_t -qca808x_ptp_trigger1_timestamp2_reg_ts_sec_get( - a_uint32_t dev_id, a_uint32_t phy_id, - unsigned int *value); - -sw_error_t -qca808x_ptp_trigger1_timestamp2_reg_ts_sec_set( - a_uint32_t dev_id, a_uint32_t phy_id, - unsigned int value); - -sw_error_t -qca808x_ptp_trigger1_timestamp3_reg_ts_nsec_get( - a_uint32_t dev_id, a_uint32_t phy_id, - unsigned int *value); - -sw_error_t -qca808x_ptp_trigger1_timestamp3_reg_ts_nsec_set( - a_uint32_t dev_id, a_uint32_t phy_id, - unsigned int value); - -sw_error_t -qca808x_ptp_trigger1_timestamp4_reg_ts_nsec_get( - a_uint32_t dev_id, a_uint32_t phy_id, - unsigned int *value); - -sw_error_t -qca808x_ptp_trigger1_timestamp4_reg_ts_nsec_set( - a_uint32_t dev_id, a_uint32_t phy_id, - unsigned int value); - -sw_error_t -qca808x_ptp_event0_config_reg_rise_en_get( - a_uint32_t dev_id, a_uint32_t phy_id, - unsigned int *value); - -sw_error_t -qca808x_ptp_event0_config_reg_rise_en_set( - a_uint32_t dev_id, a_uint32_t phy_id, - unsigned int value); - -sw_error_t -qca808x_ptp_event0_config_reg_single_cap_get( - a_uint32_t dev_id, a_uint32_t phy_id, - unsigned int *value); - -sw_error_t -qca808x_ptp_event0_config_reg_single_cap_set( - a_uint32_t dev_id, a_uint32_t phy_id, - unsigned int value); - -sw_error_t -qca808x_ptp_event0_config_reg_fall_en_get( - a_uint32_t dev_id, a_uint32_t phy_id, - unsigned int *value); - -sw_error_t -qca808x_ptp_event0_config_reg_fall_en_set( - a_uint32_t dev_id, a_uint32_t phy_id, - unsigned int value); - -sw_error_t -qca808x_ptp_event0_config_reg_notify_get( - a_uint32_t dev_id, a_uint32_t phy_id, - unsigned int *value); - -sw_error_t -qca808x_ptp_event0_config_reg_notify_set( - a_uint32_t dev_id, a_uint32_t phy_id, - unsigned int value); - -sw_error_t -qca808x_ptp_event0_config_reg_clear_stat_get( - a_uint32_t dev_id, a_uint32_t phy_id, - unsigned int *value); - -sw_error_t -qca808x_ptp_event0_config_reg_clear_stat_set( - a_uint32_t dev_id, a_uint32_t phy_id, - unsigned int value); - -sw_error_t -qca808x_ptp_event0_status_reg_mul_event_get( - a_uint32_t dev_id, a_uint32_t phy_id, - unsigned int *value); - -sw_error_t -qca808x_ptp_event0_status_reg_mul_event_set( - a_uint32_t dev_id, a_uint32_t phy_id, - unsigned int value); - -sw_error_t -qca808x_ptp_event0_status_reg_missed_count_get( - a_uint32_t dev_id, a_uint32_t phy_id, - unsigned int *value); - -sw_error_t -qca808x_ptp_event0_status_reg_missed_count_set( - a_uint32_t dev_id, a_uint32_t phy_id, - unsigned int value); - -sw_error_t -qca808x_ptp_event0_status_reg_dir_detected_get( - a_uint32_t dev_id, a_uint32_t phy_id, - unsigned int *value); - -sw_error_t -qca808x_ptp_event0_status_reg_dir_detected_set( - a_uint32_t dev_id, a_uint32_t phy_id, - unsigned int value); - -sw_error_t -qca808x_ptp_event0_status_reg_detected_get( - a_uint32_t dev_id, a_uint32_t phy_id, - unsigned int *value); - -sw_error_t -qca808x_ptp_event0_status_reg_detected_set( - a_uint32_t dev_id, a_uint32_t phy_id, - unsigned int value); - -sw_error_t -qca808x_ptp_event1_config_reg_rise_en_get( - a_uint32_t dev_id, a_uint32_t phy_id, - unsigned int *value); - -sw_error_t -qca808x_ptp_event1_config_reg_rise_en_set( - a_uint32_t dev_id, a_uint32_t phy_id, - unsigned int value); - -sw_error_t -qca808x_ptp_event1_config_reg_single_cap_get( - a_uint32_t dev_id, a_uint32_t phy_id, - unsigned int *value); - -sw_error_t -qca808x_ptp_event1_config_reg_single_cap_set( - a_uint32_t dev_id, a_uint32_t phy_id, - unsigned int value); - -sw_error_t -qca808x_ptp_event1_config_reg_fall_en_get( - a_uint32_t dev_id, a_uint32_t phy_id, - unsigned int *value); - -sw_error_t -qca808x_ptp_event1_config_reg_fall_en_set( - a_uint32_t dev_id, a_uint32_t phy_id, - unsigned int value); - -sw_error_t -qca808x_ptp_event1_config_reg_notify_get( - a_uint32_t dev_id, a_uint32_t phy_id, - unsigned int *value); - -sw_error_t -qca808x_ptp_event1_config_reg_notify_set( - a_uint32_t dev_id, a_uint32_t phy_id, - unsigned int value); - -sw_error_t -qca808x_ptp_event1_config_reg_clear_stat_get( - a_uint32_t dev_id, a_uint32_t phy_id, - unsigned int *value); - -sw_error_t -qca808x_ptp_event1_config_reg_clear_stat_set( - a_uint32_t dev_id, a_uint32_t phy_id, - unsigned int value); - -sw_error_t -qca808x_ptp_event1_status_reg_mul_event_get( - a_uint32_t dev_id, a_uint32_t phy_id, - unsigned int *value); - -sw_error_t -qca808x_ptp_event1_status_reg_mul_event_set( - a_uint32_t dev_id, a_uint32_t phy_id, - unsigned int value); - -sw_error_t -qca808x_ptp_event1_status_reg_missed_count_get( - a_uint32_t dev_id, a_uint32_t phy_id, - unsigned int *value); - -sw_error_t -qca808x_ptp_event1_status_reg_missed_count_set( - a_uint32_t dev_id, a_uint32_t phy_id, - unsigned int value); - -sw_error_t -qca808x_ptp_event1_status_reg_dir_detected_get( - a_uint32_t dev_id, a_uint32_t phy_id, - unsigned int *value); - -sw_error_t -qca808x_ptp_event1_status_reg_dir_detected_set( - a_uint32_t dev_id, a_uint32_t phy_id, - unsigned int value); - -sw_error_t -qca808x_ptp_event1_status_reg_detected_get( - a_uint32_t dev_id, a_uint32_t phy_id, - unsigned int *value); - -sw_error_t -qca808x_ptp_event1_status_reg_detected_set( - a_uint32_t dev_id, a_uint32_t phy_id, - unsigned int value); - -sw_error_t -qca808x_ptp_event0_timestamp0_reg_ts_nsec_get( - a_uint32_t dev_id, a_uint32_t phy_id, - unsigned int *value); - -sw_error_t -qca808x_ptp_event0_timestamp0_reg_ts_nsec_set( - a_uint32_t dev_id, a_uint32_t phy_id, - unsigned int value); - -sw_error_t -qca808x_ptp_event0_timestamp1_reg_ts_nsec_get( - a_uint32_t dev_id, a_uint32_t phy_id, - unsigned int *value); - -sw_error_t -qca808x_ptp_event0_timestamp1_reg_ts_nsec_set( - a_uint32_t dev_id, a_uint32_t phy_id, - unsigned int value); - -sw_error_t -qca808x_ptp_event0_timestamp2_reg_ts_nsec_get( - a_uint32_t dev_id, a_uint32_t phy_id, - unsigned int *value); - -sw_error_t -qca808x_ptp_event0_timestamp2_reg_ts_nsec_set( - a_uint32_t dev_id, a_uint32_t phy_id, - unsigned int value); - -sw_error_t -qca808x_ptp_event0_timestamp3_reg_ts_nsec_get( - a_uint32_t dev_id, a_uint32_t phy_id, - unsigned int *value); - -sw_error_t -qca808x_ptp_event0_timestamp3_reg_ts_nsec_set( - a_uint32_t dev_id, a_uint32_t phy_id, - unsigned int value); - -sw_error_t -qca808x_ptp_event0_timestamp4_reg_ts_nsec_get( - a_uint32_t dev_id, a_uint32_t phy_id, - unsigned int *value); - -sw_error_t -qca808x_ptp_event0_timestamp4_reg_ts_nsec_set( - a_uint32_t dev_id, a_uint32_t phy_id, - unsigned int value); - -sw_error_t -qca808x_ptp_event1_timestamp0_reg_ts_nsec_get( - a_uint32_t dev_id, a_uint32_t phy_id, - unsigned int *value); - -sw_error_t -qca808x_ptp_event1_timestamp0_reg_ts_nsec_set( - a_uint32_t dev_id, a_uint32_t phy_id, - unsigned int value); - -sw_error_t -qca808x_ptp_event1_timestamp1_reg_ts_nsec_get( - a_uint32_t dev_id, a_uint32_t phy_id, - unsigned int *value); - -sw_error_t -qca808x_ptp_event1_timestamp1_reg_ts_nsec_set( - a_uint32_t dev_id, a_uint32_t phy_id, - unsigned int value); - -sw_error_t -qca808x_ptp_event1_timestamp2_reg_ts_nsec_get( - a_uint32_t dev_id, a_uint32_t phy_id, - unsigned int *value); - -sw_error_t -qca808x_ptp_event1_timestamp2_reg_ts_nsec_set( - a_uint32_t dev_id, a_uint32_t phy_id, - unsigned int value); - -sw_error_t -qca808x_ptp_event1_timestamp3_reg_ts_nsec_get( - a_uint32_t dev_id, a_uint32_t phy_id, - unsigned int *value); - -sw_error_t -qca808x_ptp_event1_timestamp3_reg_ts_nsec_set( - a_uint32_t dev_id, a_uint32_t phy_id, - unsigned int value); - -sw_error_t -qca808x_ptp_event1_timestamp4_reg_ts_nsec_get( - a_uint32_t dev_id, a_uint32_t phy_id, - unsigned int *value); - -sw_error_t -qca808x_ptp_event1_timestamp4_reg_ts_nsec_set( - a_uint32_t dev_id, a_uint32_t phy_id, - unsigned int value); - -sw_error_t -qca808x_ptp_rx_seqid1_reg_rx_seqid_get( - a_uint32_t dev_id, a_uint32_t phy_id, - unsigned int *value); - -sw_error_t -qca808x_ptp_rx_seqid1_reg_rx_seqid_set( - a_uint32_t dev_id, a_uint32_t phy_id, - unsigned int value); - -sw_error_t -qca808x_ptp_rx_portid1_0_reg_rx_portid_get( - a_uint32_t dev_id, a_uint32_t phy_id, - unsigned int *value); - -sw_error_t -qca808x_ptp_rx_portid1_0_reg_rx_portid_set( - a_uint32_t dev_id, a_uint32_t phy_id, - unsigned int value); - -sw_error_t -qca808x_ptp_rx_portid1_1_reg_rx_portid_get( - a_uint32_t dev_id, a_uint32_t phy_id, - unsigned int *value); - -sw_error_t -qca808x_ptp_rx_portid1_1_reg_rx_portid_set( - a_uint32_t dev_id, a_uint32_t phy_id, - unsigned int value); - -sw_error_t -qca808x_ptp_rx_portid1_2_reg_rx_portid_get( - a_uint32_t dev_id, a_uint32_t phy_id, - unsigned int *value); - -sw_error_t -qca808x_ptp_rx_portid1_2_reg_rx_portid_set( - a_uint32_t dev_id, a_uint32_t phy_id, - unsigned int value); - -sw_error_t -qca808x_ptp_rx_portid1_3_reg_rx_portid_get( - a_uint32_t dev_id, a_uint32_t phy_id, - unsigned int *value); - -sw_error_t -qca808x_ptp_rx_portid1_3_reg_rx_portid_set( - a_uint32_t dev_id, a_uint32_t phy_id, - unsigned int value); - -sw_error_t -qca808x_ptp_rx_portid1_4_reg_rx_portid_get( - a_uint32_t dev_id, a_uint32_t phy_id, - unsigned int *value); - -sw_error_t -qca808x_ptp_rx_portid1_4_reg_rx_portid_set( - a_uint32_t dev_id, a_uint32_t phy_id, - unsigned int value); - -sw_error_t -qca808x_ptp_rx_ts1_0_reg_rx_ts_sec_get( - a_uint32_t dev_id, a_uint32_t phy_id, - unsigned int *value); - -sw_error_t -qca808x_ptp_rx_ts1_0_reg_rx_ts_sec_set( - a_uint32_t dev_id, a_uint32_t phy_id, - unsigned int value); - -sw_error_t -qca808x_ptp_rx_ts1_1_reg_rx_ts_sec_get( - a_uint32_t dev_id, a_uint32_t phy_id, - unsigned int *value); - -sw_error_t -qca808x_ptp_rx_ts1_1_reg_rx_ts_sec_set( - a_uint32_t dev_id, a_uint32_t phy_id, - unsigned int value); - -sw_error_t -qca808x_ptp_rx_ts1_2_reg_rx_ts_sec_get( - a_uint32_t dev_id, a_uint32_t phy_id, - unsigned int *value); - -sw_error_t -qca808x_ptp_rx_ts1_2_reg_rx_ts_sec_set( - a_uint32_t dev_id, a_uint32_t phy_id, - unsigned int value); - -sw_error_t -qca808x_ptp_rx_ts1_3_reg_rx_ts_nsec_get( - a_uint32_t dev_id, a_uint32_t phy_id, - unsigned int *value); - -sw_error_t -qca808x_ptp_rx_ts1_3_reg_rx_ts_nsec_set( - a_uint32_t dev_id, a_uint32_t phy_id, - unsigned int value); - -sw_error_t -qca808x_ptp_rx_ts1_4_reg_rx_ts_nsec_get( - a_uint32_t dev_id, a_uint32_t phy_id, - unsigned int *value); - -sw_error_t -qca808x_ptp_rx_ts1_4_reg_rx_ts_nsec_set( - a_uint32_t dev_id, a_uint32_t phy_id, - unsigned int value); - -sw_error_t -qca808x_ptp_rx_ts1_5_reg_rx_ts_nfsec_get( - a_uint32_t dev_id, a_uint32_t phy_id, - unsigned int *value); - -sw_error_t -qca808x_ptp_rx_ts1_5_reg_rx_ts_nfsec_set( - a_uint32_t dev_id, a_uint32_t phy_id, - unsigned int value); - -sw_error_t -qca808x_ptp_rx_ts1_5_reg_rx_msg_type_get( - a_uint32_t dev_id, a_uint32_t phy_id, - unsigned int *value); - -sw_error_t -qca808x_ptp_rx_ts1_5_reg_rx_msg_type_set( - a_uint32_t dev_id, a_uint32_t phy_id, - unsigned int value); - -sw_error_t -qca808x_ptp_rx_ts1_6_reg_rx_ts_nfsec_get( - a_uint32_t dev_id, a_uint32_t phy_id, - unsigned int *value); - -sw_error_t -qca808x_ptp_rx_ts1_6_reg_rx_ts_nfsec_set( - a_uint32_t dev_id, a_uint32_t phy_id, - unsigned int value); - -sw_error_t -qca808x_ptp_rx_seqid2_reg_rx_seqid_get( - a_uint32_t dev_id, a_uint32_t phy_id, - unsigned int *value); - -sw_error_t -qca808x_ptp_rx_seqid2_reg_rx_seqid_set( - a_uint32_t dev_id, a_uint32_t phy_id, - unsigned int value); - -sw_error_t -qca808x_ptp_rx_portid2_0_reg_rx_portid_get( - a_uint32_t dev_id, a_uint32_t phy_id, - unsigned int *value); - -sw_error_t -qca808x_ptp_rx_portid2_0_reg_rx_portid_set( - a_uint32_t dev_id, a_uint32_t phy_id, - unsigned int value); - -sw_error_t -qca808x_ptp_rx_portid2_1_reg_rx_portid_get( - a_uint32_t dev_id, a_uint32_t phy_id, - unsigned int *value); - -sw_error_t -qca808x_ptp_rx_portid2_1_reg_rx_portid_set( - a_uint32_t dev_id, a_uint32_t phy_id, - unsigned int value); - -sw_error_t -qca808x_ptp_rx_portid2_2_reg_rx_portid_get( - a_uint32_t dev_id, a_uint32_t phy_id, - unsigned int *value); - -sw_error_t -qca808x_ptp_rx_portid2_2_reg_rx_portid_set( - a_uint32_t dev_id, a_uint32_t phy_id, - unsigned int value); - -sw_error_t -qca808x_ptp_rx_portid2_3_reg_rx_portid_get( - a_uint32_t dev_id, a_uint32_t phy_id, - unsigned int *value); - -sw_error_t -qca808x_ptp_rx_portid2_3_reg_rx_portid_set( - a_uint32_t dev_id, a_uint32_t phy_id, - unsigned int value); - -sw_error_t -qca808x_ptp_rx_portid2_4_reg_rx_portid_get( - a_uint32_t dev_id, a_uint32_t phy_id, - unsigned int *value); - -sw_error_t -qca808x_ptp_rx_portid2_4_reg_rx_portid_set( - a_uint32_t dev_id, a_uint32_t phy_id, - unsigned int value); - -sw_error_t -qca808x_ptp_rx_ts2_0_reg_rx_ts_sec_get( - a_uint32_t dev_id, a_uint32_t phy_id, - unsigned int *value); - -sw_error_t -qca808x_ptp_rx_ts2_0_reg_rx_ts_sec_set( - a_uint32_t dev_id, a_uint32_t phy_id, - unsigned int value); - -sw_error_t -qca808x_ptp_rx_ts2_1_reg_rx_ts_sec_get( - a_uint32_t dev_id, a_uint32_t phy_id, - unsigned int *value); - -sw_error_t -qca808x_ptp_rx_ts2_1_reg_rx_ts_sec_set( - a_uint32_t dev_id, a_uint32_t phy_id, - unsigned int value); - -sw_error_t -qca808x_ptp_rx_ts2_2_reg_rx_ts_sec_get( - a_uint32_t dev_id, a_uint32_t phy_id, - unsigned int *value); - -sw_error_t -qca808x_ptp_rx_ts2_2_reg_rx_ts_sec_set( - a_uint32_t dev_id, a_uint32_t phy_id, - unsigned int value); - -sw_error_t -qca808x_ptp_rx_ts2_3_reg_rx_ts_nsec_get( - a_uint32_t dev_id, a_uint32_t phy_id, - unsigned int *value); - -sw_error_t -qca808x_ptp_rx_ts2_3_reg_rx_ts_nsec_set( - a_uint32_t dev_id, a_uint32_t phy_id, - unsigned int value); - -sw_error_t -qca808x_ptp_rx_ts2_4_reg_rx_ts_nsec_get( - a_uint32_t dev_id, a_uint32_t phy_id, - unsigned int *value); - -sw_error_t -qca808x_ptp_rx_ts2_4_reg_rx_ts_nsec_set( - a_uint32_t dev_id, a_uint32_t phy_id, - unsigned int value); - -sw_error_t -qca808x_ptp_rx_ts2_5_reg_rx_ts_nfsec_get( - a_uint32_t dev_id, a_uint32_t phy_id, - unsigned int *value); - -sw_error_t -qca808x_ptp_rx_ts2_5_reg_rx_ts_nfsec_set( - a_uint32_t dev_id, a_uint32_t phy_id, - unsigned int value); - -sw_error_t -qca808x_ptp_rx_ts2_5_reg_rx_msg_type_get( - a_uint32_t dev_id, a_uint32_t phy_id, - unsigned int *value); - -sw_error_t -qca808x_ptp_rx_ts2_5_reg_rx_msg_type_set( - a_uint32_t dev_id, a_uint32_t phy_id, - unsigned int value); - -sw_error_t -qca808x_ptp_rx_ts2_6_reg_rx_ts_nfsec_get( - a_uint32_t dev_id, a_uint32_t phy_id, - unsigned int *value); - -sw_error_t -qca808x_ptp_rx_ts2_6_reg_rx_ts_nfsec_set( - a_uint32_t dev_id, a_uint32_t phy_id, - unsigned int value); - -sw_error_t -qca808x_ptp_rx_seqid3_reg_rx_seqid_get( - a_uint32_t dev_id, a_uint32_t phy_id, - unsigned int *value); - -sw_error_t -qca808x_ptp_rx_seqid3_reg_rx_seqid_set( - a_uint32_t dev_id, a_uint32_t phy_id, - unsigned int value); - -sw_error_t -qca808x_ptp_rx_portid3_0_reg_rx_portid_get( - a_uint32_t dev_id, a_uint32_t phy_id, - unsigned int *value); - -sw_error_t -qca808x_ptp_rx_portid3_0_reg_rx_portid_set( - a_uint32_t dev_id, a_uint32_t phy_id, - unsigned int value); - -sw_error_t -qca808x_ptp_rx_portid3_1_reg_rx_portid_get( - a_uint32_t dev_id, a_uint32_t phy_id, - unsigned int *value); - -sw_error_t -qca808x_ptp_rx_portid3_1_reg_rx_portid_set( - a_uint32_t dev_id, a_uint32_t phy_id, - unsigned int value); - -sw_error_t -qca808x_ptp_rx_portid3_2_reg_rx_portid_get( - a_uint32_t dev_id, a_uint32_t phy_id, - unsigned int *value); - -sw_error_t -qca808x_ptp_rx_portid3_2_reg_rx_portid_set( - a_uint32_t dev_id, a_uint32_t phy_id, - unsigned int value); - -sw_error_t -qca808x_ptp_rx_portid3_3_reg_rx_portid_get( - a_uint32_t dev_id, a_uint32_t phy_id, - unsigned int *value); - -sw_error_t -qca808x_ptp_rx_portid3_3_reg_rx_portid_set( - a_uint32_t dev_id, a_uint32_t phy_id, - unsigned int value); - -sw_error_t -qca808x_ptp_rx_portid3_4_reg_rx_portid_get( - a_uint32_t dev_id, a_uint32_t phy_id, - unsigned int *value); - -sw_error_t -qca808x_ptp_rx_portid3_4_reg_rx_portid_set( - a_uint32_t dev_id, a_uint32_t phy_id, - unsigned int value); - -sw_error_t -qca808x_ptp_rx_ts3_0_reg_rx_ts_sec_get( - a_uint32_t dev_id, a_uint32_t phy_id, - unsigned int *value); - -sw_error_t -qca808x_ptp_rx_ts3_0_reg_rx_ts_sec_set( - a_uint32_t dev_id, a_uint32_t phy_id, - unsigned int value); - -sw_error_t -qca808x_ptp_rx_ts3_1_reg_rx_ts_sec_get( - a_uint32_t dev_id, a_uint32_t phy_id, - unsigned int *value); - -sw_error_t -qca808x_ptp_rx_ts3_1_reg_rx_ts_sec_set( - a_uint32_t dev_id, a_uint32_t phy_id, - unsigned int value); - -sw_error_t -qca808x_ptp_rx_ts3_2_reg_rx_ts_sec_get( - a_uint32_t dev_id, a_uint32_t phy_id, - unsigned int *value); - -sw_error_t -qca808x_ptp_rx_ts3_2_reg_rx_ts_sec_set( - a_uint32_t dev_id, a_uint32_t phy_id, - unsigned int value); - -sw_error_t -qca808x_ptp_rx_ts3_3_reg_rx_ts_nsec_get( - a_uint32_t dev_id, a_uint32_t phy_id, - unsigned int *value); - -sw_error_t -qca808x_ptp_rx_ts3_3_reg_rx_ts_nsec_set( - a_uint32_t dev_id, a_uint32_t phy_id, - unsigned int value); - -sw_error_t -qca808x_ptp_rx_ts3_4_reg_rx_ts_nsec_get( - a_uint32_t dev_id, a_uint32_t phy_id, - unsigned int *value); - -sw_error_t -qca808x_ptp_rx_ts3_4_reg_rx_ts_nsec_set( - a_uint32_t dev_id, a_uint32_t phy_id, - unsigned int value); - -sw_error_t -qca808x_ptp_rx_ts3_5_reg_rx_ts_nfsec_get( - a_uint32_t dev_id, a_uint32_t phy_id, - unsigned int *value); - -sw_error_t -qca808x_ptp_rx_ts3_5_reg_rx_ts_nfsec_set( - a_uint32_t dev_id, a_uint32_t phy_id, - unsigned int value); - -sw_error_t -qca808x_ptp_rx_ts3_5_reg_rx_msg_type_get( - a_uint32_t dev_id, a_uint32_t phy_id, - unsigned int *value); - -sw_error_t -qca808x_ptp_rx_ts3_5_reg_rx_msg_type_set( - a_uint32_t dev_id, a_uint32_t phy_id, - unsigned int value); - -sw_error_t -qca808x_ptp_rx_ts3_6_reg_rx_ts_nfsec_get( - a_uint32_t dev_id, a_uint32_t phy_id, - unsigned int *value); - -sw_error_t -qca808x_ptp_rx_ts3_6_reg_rx_ts_nfsec_set( - a_uint32_t dev_id, a_uint32_t phy_id, - unsigned int value); - -sw_error_t -qca808x_ptp_phase_adjust_0_reg_get( - a_uint32_t dev_id, a_uint32_t phy_id, - union ptp_phase_adjust_0_reg_u *value); - -sw_error_t -qca808x_ptp_phase_adjust_0_reg_set( - a_uint32_t dev_id, a_uint32_t phy_id, - union ptp_phase_adjust_0_reg_u *value); - -sw_error_t -qca808x_ptp_phase_adjust_0_reg_phase_value_get( - a_uint32_t dev_id, a_uint32_t phy_id, - unsigned int *value); - -sw_error_t -qca808x_ptp_phase_adjust_0_reg_phase_value_set( - a_uint32_t dev_id, a_uint32_t phy_id, - unsigned int value); - -sw_error_t -qca808x_ptp_phase_adjust_1_reg_get( - a_uint32_t dev_id, a_uint32_t phy_id, - union ptp_phase_adjust_1_reg_u *value); - -sw_error_t -qca808x_ptp_phase_adjust_1_reg_set( - a_uint32_t dev_id, a_uint32_t phy_id, - union ptp_phase_adjust_1_reg_u *value); - -sw_error_t -qca808x_ptp_phase_adjust_1_reg_phase_value_get( - a_uint32_t dev_id, a_uint32_t phy_id, - unsigned int *value); - -sw_error_t -qca808x_ptp_phase_adjust_1_reg_phase_value_set( - a_uint32_t dev_id, a_uint32_t phy_id, - unsigned int value); - -sw_error_t -qca808x_ptp_pps_pul_width_0_reg_get( - a_uint32_t dev_id, a_uint32_t phy_id, - union ptp_pps_pul_width_0_reg_u *value); - -sw_error_t -qca808x_ptp_pps_pul_width_0_reg_set( - a_uint32_t dev_id, a_uint32_t phy_id, - union ptp_pps_pul_width_0_reg_u *value); - -sw_error_t -qca808x_ptp_pps_pul_width_0_reg_pul_value_get( - a_uint32_t dev_id, a_uint32_t phy_id, - unsigned int *value); - -sw_error_t -qca808x_ptp_pps_pul_width_0_reg_pul_value_set( - a_uint32_t dev_id, a_uint32_t phy_id, - unsigned int value); - -sw_error_t -qca808x_ptp_pps_pul_width_1_reg_get( - a_uint32_t dev_id, a_uint32_t phy_id, - union ptp_pps_pul_width_1_reg_u *value); - -sw_error_t -qca808x_ptp_pps_pul_width_1_reg_set( - a_uint32_t dev_id, a_uint32_t phy_id, - union ptp_pps_pul_width_1_reg_u *value); - -sw_error_t -qca808x_ptp_pps_pul_width_1_reg_pul_value_get( - a_uint32_t dev_id, a_uint32_t phy_id, - unsigned int *value); - -sw_error_t -qca808x_ptp_pps_pul_width_1_reg_pul_value_set( - a_uint32_t dev_id, a_uint32_t phy_id, - unsigned int value); - -sw_error_t -qca808x_ptp_freq_waveform_period_0_reg_get( - a_uint32_t dev_id, a_uint32_t phy_id, - union ptp_freq_waveform_period_0_reg_u *value); - -sw_error_t -qca808x_ptp_freq_waveform_period_0_reg_set( - a_uint32_t dev_id, a_uint32_t phy_id, - union ptp_freq_waveform_period_0_reg_u *value); - -sw_error_t -qca808x_ptp_freq_waveform_period_0_reg_wave_period_get( - a_uint32_t dev_id, a_uint32_t phy_id, - unsigned int *value); - -sw_error_t -qca808x_ptp_freq_waveform_period_0_reg_wave_period_set( - a_uint32_t dev_id, a_uint32_t phy_id, - unsigned int value); - -sw_error_t -qca808x_ptp_freq_waveform_period_0_reg_phase_ali_get( - a_uint32_t dev_id, a_uint32_t phy_id, - unsigned int *value); - -sw_error_t -qca808x_ptp_freq_waveform_period_0_reg_phase_ali_set( - a_uint32_t dev_id, a_uint32_t phy_id, - unsigned int value); - -sw_error_t -qca808x_ptp_freq_waveform_period_1_reg_get( - a_uint32_t dev_id, a_uint32_t phy_id, - union ptp_freq_waveform_period_1_reg_u *value); - -sw_error_t -qca808x_ptp_freq_waveform_period_1_reg_set( - a_uint32_t dev_id, a_uint32_t phy_id, - union ptp_freq_waveform_period_1_reg_u *value); - -sw_error_t -qca808x_ptp_freq_waveform_period_1_reg_wave_period_get( - a_uint32_t dev_id, a_uint32_t phy_id, - unsigned int *value); - -sw_error_t -qca808x_ptp_freq_waveform_period_1_reg_wave_period_set( - a_uint32_t dev_id, a_uint32_t phy_id, - unsigned int value); - -sw_error_t -qca808x_ptp_freq_waveform_period_2_reg_get( - a_uint32_t dev_id, a_uint32_t phy_id, - union ptp_freq_waveform_period_2_reg_u *value); - -sw_error_t -qca808x_ptp_freq_waveform_period_2_reg_set( - a_uint32_t dev_id, a_uint32_t phy_id, - union ptp_freq_waveform_period_2_reg_u *value); - -sw_error_t -qca808x_ptp_freq_waveform_period_2_reg_wave_period_get( - a_uint32_t dev_id, a_uint32_t phy_id, - unsigned int *value); - -sw_error_t -qca808x_ptp_freq_waveform_period_2_reg_wave_period_set( - a_uint32_t dev_id, a_uint32_t phy_id, - unsigned int value); - -sw_error_t -qca808x_ptp_rx_com_ts_ctrl_reg_get( - a_uint32_t dev_id, a_uint32_t phy_id, - union ptp_rx_com_ts_ctrl_reg_u *value); - -sw_error_t -qca808x_ptp_rx_com_ts_ctrl_reg_set( - a_uint32_t dev_id, a_uint32_t phy_id, - union ptp_rx_com_ts_ctrl_reg_u *value); - -sw_error_t -qca808x_ptp_rx_filt_mac_da0_reg_get( - a_uint32_t dev_id, a_uint32_t phy_id, - union ptp_rx_filt_mac_da0_reg_u *value); - -sw_error_t -qca808x_ptp_rx_filt_mac_da0_reg_set( - a_uint32_t dev_id, a_uint32_t phy_id, - union ptp_rx_filt_mac_da0_reg_u *value); - -sw_error_t -qca808x_ptp_rx_filt_mac_da1_reg_get( - a_uint32_t dev_id, a_uint32_t phy_id, - union ptp_rx_filt_mac_da1_reg_u *value); - -sw_error_t -qca808x_ptp_rx_filt_mac_da1_reg_set( - a_uint32_t dev_id, a_uint32_t phy_id, - union ptp_rx_filt_mac_da1_reg_u *value); - -sw_error_t -qca808x_ptp_rx_filt_mac_da2_reg_get( - a_uint32_t dev_id, a_uint32_t phy_id, - union ptp_rx_filt_mac_da2_reg_u *value); - -sw_error_t -qca808x_ptp_rx_filt_mac_da2_reg_set( - a_uint32_t dev_id, a_uint32_t phy_id, - union ptp_rx_filt_mac_da2_reg_u *value); - -sw_error_t -qca808x_ptp_rx_filt_ipv4_da0_reg_get( - a_uint32_t dev_id, a_uint32_t phy_id, - union ptp_rx_filt_ipv4_da0_reg_u *value); - -sw_error_t -qca808x_ptp_rx_filt_ipv4_da0_reg_set( - a_uint32_t dev_id, a_uint32_t phy_id, - union ptp_rx_filt_ipv4_da0_reg_u *value); - -sw_error_t -qca808x_ptp_rx_filt_ipv4_da1_reg_get( - a_uint32_t dev_id, a_uint32_t phy_id, - union ptp_rx_filt_ipv4_da1_reg_u *value); - -sw_error_t -qca808x_ptp_rx_filt_ipv4_da1_reg_set( - a_uint32_t dev_id, a_uint32_t phy_id, - union ptp_rx_filt_ipv4_da1_reg_u *value); - -sw_error_t -qca808x_ptp_rx_filt_ipv6_da0_reg_get( - a_uint32_t dev_id, a_uint32_t phy_id, - union ptp_rx_filt_ipv6_da0_reg_u *value); - -sw_error_t -qca808x_ptp_rx_filt_ipv6_da0_reg_set( - a_uint32_t dev_id, a_uint32_t phy_id, - union ptp_rx_filt_ipv6_da0_reg_u *value); - -sw_error_t -qca808x_ptp_rx_filt_ipv6_da1_reg_get( - a_uint32_t dev_id, a_uint32_t phy_id, - union ptp_rx_filt_ipv6_da1_reg_u *value); - -sw_error_t -qca808x_ptp_rx_filt_ipv6_da1_reg_set( - a_uint32_t dev_id, a_uint32_t phy_id, - union ptp_rx_filt_ipv6_da1_reg_u *value); - -sw_error_t -qca808x_ptp_rx_filt_ipv6_da2_reg_get( - a_uint32_t dev_id, a_uint32_t phy_id, - union ptp_rx_filt_ipv6_da2_reg_u *value); - -sw_error_t -qca808x_ptp_rx_filt_ipv6_da2_reg_set( - a_uint32_t dev_id, a_uint32_t phy_id, - union ptp_rx_filt_ipv6_da2_reg_u *value); - -sw_error_t -qca808x_ptp_rx_filt_ipv6_da3_reg_get( - a_uint32_t dev_id, a_uint32_t phy_id, - union ptp_rx_filt_ipv6_da3_reg_u *value); - -sw_error_t -qca808x_ptp_rx_filt_ipv6_da3_reg_set( - a_uint32_t dev_id, a_uint32_t phy_id, - union ptp_rx_filt_ipv6_da3_reg_u *value); - -sw_error_t -qca808x_ptp_rx_filt_ipv6_da4_reg_get( - a_uint32_t dev_id, a_uint32_t phy_id, - union ptp_rx_filt_ipv6_da4_reg_u *value); - -sw_error_t -qca808x_ptp_rx_filt_ipv6_da4_reg_set( - a_uint32_t dev_id, a_uint32_t phy_id, - union ptp_rx_filt_ipv6_da4_reg_u *value); - -sw_error_t -qca808x_ptp_rx_filt_ipv6_da5_reg_get( - a_uint32_t dev_id, a_uint32_t phy_id, - union ptp_rx_filt_ipv6_da5_reg_u *value); - -sw_error_t -qca808x_ptp_rx_filt_ipv6_da5_reg_set( - a_uint32_t dev_id, a_uint32_t phy_id, - union ptp_rx_filt_ipv6_da5_reg_u *value); - -sw_error_t -qca808x_ptp_rx_filt_ipv6_da6_reg_get( - a_uint32_t dev_id, a_uint32_t phy_id, - union ptp_rx_filt_ipv6_da6_reg_u *value); - -sw_error_t -qca808x_ptp_rx_filt_ipv6_da6_reg_set( - a_uint32_t dev_id, a_uint32_t phy_id, - union ptp_rx_filt_ipv6_da6_reg_u *value); - -sw_error_t -qca808x_ptp_rx_filt_ipv6_da7_reg_get( - a_uint32_t dev_id, a_uint32_t phy_id, - union ptp_rx_filt_ipv6_da7_reg_u *value); - -sw_error_t -qca808x_ptp_rx_filt_ipv6_da7_reg_set( - a_uint32_t dev_id, a_uint32_t phy_id, - union ptp_rx_filt_ipv6_da7_reg_u *value); - -sw_error_t -qca808x_ptp_rx_filt_mac_lengthtype_reg_get( - a_uint32_t dev_id, a_uint32_t phy_id, - union ptp_rx_filt_mac_lengthtype_reg_u *value); - -sw_error_t -qca808x_ptp_rx_filt_mac_lengthtype_reg_set( - a_uint32_t dev_id, a_uint32_t phy_id, - union ptp_rx_filt_mac_lengthtype_reg_u *value); - -sw_error_t -qca808x_ptp_rx_filt_layer4_protocol_reg_get( - a_uint32_t dev_id, a_uint32_t phy_id, - union ptp_rx_filt_layer4_protocol_reg_u *value); - -sw_error_t -qca808x_ptp_rx_filt_layer4_protocol_reg_set( - a_uint32_t dev_id, a_uint32_t phy_id, - union ptp_rx_filt_layer4_protocol_reg_u *value); - -sw_error_t -qca808x_ptp_rx_filt_udp_port_reg_get( - a_uint32_t dev_id, a_uint32_t phy_id, - union ptp_rx_filt_udp_port_reg_u *value); - -sw_error_t -qca808x_ptp_rx_filt_udp_port_reg_set( - a_uint32_t dev_id, a_uint32_t phy_id, - union ptp_rx_filt_udp_port_reg_u *value); - -sw_error_t -qca808x_ptp_rx_com_ts_status_reg_get( - a_uint32_t dev_id, a_uint32_t phy_id, - union ptp_rx_com_ts_status_reg_u *value); - -sw_error_t -qca808x_ptp_rx_com_ts_status_reg_set( - a_uint32_t dev_id, a_uint32_t phy_id, - union ptp_rx_com_ts_status_reg_u *value); - -sw_error_t -qca808x_ptp_rx_com_timestamp0_reg_get( - a_uint32_t dev_id, a_uint32_t phy_id, - union ptp_rx_com_timestamp0_reg_u *value); - -sw_error_t -qca808x_ptp_rx_com_timestamp0_reg_set( - a_uint32_t dev_id, a_uint32_t phy_id, - union ptp_rx_com_timestamp0_reg_u *value); - -sw_error_t -qca808x_ptp_rx_com_timestamp1_reg_get( - a_uint32_t dev_id, a_uint32_t phy_id, - union ptp_rx_com_timestamp1_reg_u *value); - -sw_error_t -qca808x_ptp_rx_com_timestamp1_reg_set( - a_uint32_t dev_id, a_uint32_t phy_id, - union ptp_rx_com_timestamp1_reg_u *value); - -sw_error_t -qca808x_ptp_rx_com_timestamp2_reg_get( - a_uint32_t dev_id, a_uint32_t phy_id, - union ptp_rx_com_timestamp2_reg_u *value); - -sw_error_t -qca808x_ptp_rx_com_timestamp2_reg_set( - a_uint32_t dev_id, a_uint32_t phy_id, - union ptp_rx_com_timestamp2_reg_u *value); - -sw_error_t -qca808x_ptp_rx_com_timestamp3_reg_get( - a_uint32_t dev_id, a_uint32_t phy_id, - union ptp_rx_com_timestamp3_reg_u *value); - -sw_error_t -qca808x_ptp_rx_com_timestamp3_reg_set( - a_uint32_t dev_id, a_uint32_t phy_id, - union ptp_rx_com_timestamp3_reg_u *value); - -sw_error_t -qca808x_ptp_rx_com_timestamp4_reg_get( - a_uint32_t dev_id, a_uint32_t phy_id, - union ptp_rx_com_timestamp4_reg_u *value); - -sw_error_t -qca808x_ptp_rx_com_timestamp4_reg_set( - a_uint32_t dev_id, a_uint32_t phy_id, - union ptp_rx_com_timestamp4_reg_u *value); - -sw_error_t -qca808x_ptp_rx_com_frac_nano_reg_get( - a_uint32_t dev_id, a_uint32_t phy_id, - union ptp_rx_com_frac_nano_reg_u *value); - -sw_error_t -qca808x_ptp_rx_com_frac_nano_reg_set( - a_uint32_t dev_id, a_uint32_t phy_id, - union ptp_rx_com_frac_nano_reg_u *value); - -sw_error_t -qca808x_ptp_rx_com_timestamp_pre0_reg_get( - a_uint32_t dev_id, a_uint32_t phy_id, - union ptp_rx_com_timestamp_pre0_reg_u *value); - -sw_error_t -qca808x_ptp_rx_com_timestamp_pre0_reg_set( - a_uint32_t dev_id, a_uint32_t phy_id, - union ptp_rx_com_timestamp_pre0_reg_u *value); - -sw_error_t -qca808x_ptp_rx_com_timestamp_pre1_reg_get( - a_uint32_t dev_id, a_uint32_t phy_id, - union ptp_rx_com_timestamp_pre1_reg_u *value); - -sw_error_t -qca808x_ptp_rx_com_timestamp_pre1_reg_set( - a_uint32_t dev_id, a_uint32_t phy_id, - union ptp_rx_com_timestamp_pre1_reg_u *value); - -sw_error_t -qca808x_ptp_rx_com_timestamp_pre2_reg_get( - a_uint32_t dev_id, a_uint32_t phy_id, - union ptp_rx_com_timestamp_pre2_reg_u *value); - -sw_error_t -qca808x_ptp_rx_com_timestamp_pre2_reg_set( - a_uint32_t dev_id, a_uint32_t phy_id, - union ptp_rx_com_timestamp_pre2_reg_u *value); - -sw_error_t -qca808x_ptp_rx_com_timestamp_pre3_reg_get( - a_uint32_t dev_id, a_uint32_t phy_id, - union ptp_rx_com_timestamp_pre3_reg_u *value); - -sw_error_t -qca808x_ptp_rx_com_timestamp_pre3_reg_set( - a_uint32_t dev_id, a_uint32_t phy_id, - union ptp_rx_com_timestamp_pre3_reg_u *value); - -sw_error_t -qca808x_ptp_rx_com_timestamp_pre4_reg_get( - a_uint32_t dev_id, a_uint32_t phy_id, - union ptp_rx_com_timestamp_pre4_reg_u *value); - -sw_error_t -qca808x_ptp_rx_com_timestamp_pre4_reg_set( - a_uint32_t dev_id, a_uint32_t phy_id, - union ptp_rx_com_timestamp_pre4_reg_u *value); - -sw_error_t -qca808x_ptp_rx_com_frac_nano_pre_reg_get( - a_uint32_t dev_id, a_uint32_t phy_id, - union ptp_rx_com_frac_nano_pre_reg_u *value); - -sw_error_t -qca808x_ptp_rx_com_frac_nano_pre_reg_set( - a_uint32_t dev_id, a_uint32_t phy_id, - union ptp_rx_com_frac_nano_pre_reg_u *value); - -sw_error_t -qca808x_ptp_rx_y1731_identify_reg_get( - a_uint32_t dev_id, a_uint32_t phy_id, - union ptp_rx_y1731_identify_reg_u *value); - -sw_error_t -qca808x_ptp_rx_y1731_identify_reg_set( - a_uint32_t dev_id, a_uint32_t phy_id, - union ptp_rx_y1731_identify_reg_u *value); - -sw_error_t -qca808x_ptp_rx_y1731_identify_pre_reg_get( - a_uint32_t dev_id, a_uint32_t phy_id, - union ptp_rx_y1731_identify_pre_reg_u *value); - -sw_error_t -qca808x_ptp_rx_y1731_identify_pre_reg_set( - a_uint32_t dev_id, a_uint32_t phy_id, - union ptp_rx_y1731_identify_pre_reg_u *value); - -sw_error_t -qca808x_ptp_tx_com_ts_ctrl_reg_get( - a_uint32_t dev_id, a_uint32_t phy_id, - union ptp_tx_com_ts_ctrl_reg_u *value); - -sw_error_t -qca808x_ptp_tx_com_ts_ctrl_reg_set( - a_uint32_t dev_id, a_uint32_t phy_id, - union ptp_tx_com_ts_ctrl_reg_u *value); - -sw_error_t -qca808x_ptp_tx_filt_mac_da0_reg_get( - a_uint32_t dev_id, a_uint32_t phy_id, - union ptp_tx_filt_mac_da0_reg_u *value); - -sw_error_t -qca808x_ptp_tx_filt_mac_da0_reg_set( - a_uint32_t dev_id, a_uint32_t phy_id, - union ptp_tx_filt_mac_da0_reg_u *value); - -sw_error_t -qca808x_ptp_tx_filt_mac_da1_reg_get( - a_uint32_t dev_id, a_uint32_t phy_id, - union ptp_tx_filt_mac_da1_reg_u *value); - -sw_error_t -qca808x_ptp_tx_filt_mac_da1_reg_set( - a_uint32_t dev_id, a_uint32_t phy_id, - union ptp_tx_filt_mac_da1_reg_u *value); - -sw_error_t -qca808x_ptp_tx_filt_mac_da2_reg_get( - a_uint32_t dev_id, a_uint32_t phy_id, - union ptp_tx_filt_mac_da2_reg_u *value); - -sw_error_t -qca808x_ptp_tx_filt_mac_da2_reg_set( - a_uint32_t dev_id, a_uint32_t phy_id, - union ptp_tx_filt_mac_da2_reg_u *value); - -sw_error_t -qca808x_ptp_tx_filt_ipv4_da0_reg_get( - a_uint32_t dev_id, a_uint32_t phy_id, - union ptp_tx_filt_ipv4_da0_reg_u *value); - -sw_error_t -qca808x_ptp_tx_filt_ipv4_da0_reg_set( - a_uint32_t dev_id, a_uint32_t phy_id, - union ptp_tx_filt_ipv4_da0_reg_u *value); - -sw_error_t -qca808x_ptp_tx_filt_ipv4_da1_reg_get( - a_uint32_t dev_id, a_uint32_t phy_id, - union ptp_tx_filt_ipv4_da1_reg_u *value); - -sw_error_t -qca808x_ptp_tx_filt_ipv4_da1_reg_set( - a_uint32_t dev_id, a_uint32_t phy_id, - union ptp_tx_filt_ipv4_da1_reg_u *value); - -sw_error_t -qca808x_ptp_tx_filt_ipv6_da0_reg_get( - a_uint32_t dev_id, a_uint32_t phy_id, - union ptp_tx_filt_ipv6_da0_reg_u *value); - -sw_error_t -qca808x_ptp_tx_filt_ipv6_da0_reg_set( - a_uint32_t dev_id, a_uint32_t phy_id, - union ptp_tx_filt_ipv6_da0_reg_u *value); - -sw_error_t -qca808x_ptp_tx_filt_ipv6_da1_reg_get( - a_uint32_t dev_id, a_uint32_t phy_id, - union ptp_tx_filt_ipv6_da1_reg_u *value); - -sw_error_t -qca808x_ptp_tx_filt_ipv6_da1_reg_set( - a_uint32_t dev_id, a_uint32_t phy_id, - union ptp_tx_filt_ipv6_da1_reg_u *value); - -sw_error_t -qca808x_ptp_tx_filt_ipv6_da2_reg_get( - a_uint32_t dev_id, a_uint32_t phy_id, - union ptp_tx_filt_ipv6_da2_reg_u *value); - -sw_error_t -qca808x_ptp_tx_filt_ipv6_da2_reg_set( - a_uint32_t dev_id, a_uint32_t phy_id, - union ptp_tx_filt_ipv6_da2_reg_u *value); - -sw_error_t -qca808x_ptp_tx_filt_ipv6_da3_reg_get( - a_uint32_t dev_id, a_uint32_t phy_id, - union ptp_tx_filt_ipv6_da3_reg_u *value); - -sw_error_t -qca808x_ptp_tx_filt_ipv6_da3_reg_set( - a_uint32_t dev_id, a_uint32_t phy_id, - union ptp_tx_filt_ipv6_da3_reg_u *value); - -sw_error_t -qca808x_ptp_tx_filt_ipv6_da4_reg_get( - a_uint32_t dev_id, a_uint32_t phy_id, - union ptp_tx_filt_ipv6_da4_reg_u *value); - -sw_error_t -qca808x_ptp_tx_filt_ipv6_da4_reg_set( - a_uint32_t dev_id, a_uint32_t phy_id, - union ptp_tx_filt_ipv6_da4_reg_u *value); - -sw_error_t -qca808x_ptp_tx_filt_ipv6_da5_reg_get( - a_uint32_t dev_id, a_uint32_t phy_id, - union ptp_tx_filt_ipv6_da5_reg_u *value); - -sw_error_t -qca808x_ptp_tx_filt_ipv6_da5_reg_set( - a_uint32_t dev_id, a_uint32_t phy_id, - union ptp_tx_filt_ipv6_da5_reg_u *value); - -sw_error_t -qca808x_ptp_tx_filt_ipv6_da6_reg_get( - a_uint32_t dev_id, a_uint32_t phy_id, - union ptp_tx_filt_ipv6_da6_reg_u *value); - -sw_error_t -qca808x_ptp_tx_filt_ipv6_da6_reg_set( - a_uint32_t dev_id, a_uint32_t phy_id, - union ptp_tx_filt_ipv6_da6_reg_u *value); - -sw_error_t -qca808x_ptp_tx_filt_ipv6_da7_reg_get( - a_uint32_t dev_id, a_uint32_t phy_id, - union ptp_tx_filt_ipv6_da7_reg_u *value); - -sw_error_t -qca808x_ptp_tx_filt_ipv6_da7_reg_set( - a_uint32_t dev_id, a_uint32_t phy_id, - union ptp_tx_filt_ipv6_da7_reg_u *value); - -sw_error_t -qca808x_ptp_tx_filt_mac_lengthtype_reg_get( - a_uint32_t dev_id, a_uint32_t phy_id, - union ptp_tx_filt_mac_lengthtype_reg_u *value); - -sw_error_t -qca808x_ptp_tx_filt_mac_lengthtype_reg_set( - a_uint32_t dev_id, a_uint32_t phy_id, - union ptp_tx_filt_mac_lengthtype_reg_u *value); - -sw_error_t -qca808x_ptp_tx_filt_layer4_protocol_reg_get( - a_uint32_t dev_id, a_uint32_t phy_id, - union ptp_tx_filt_layer4_protocol_reg_u *value); - -sw_error_t -qca808x_ptp_tx_filt_layer4_protocol_reg_set( - a_uint32_t dev_id, a_uint32_t phy_id, - union ptp_tx_filt_layer4_protocol_reg_u *value); - -sw_error_t -qca808x_ptp_tx_filt_udp_port_reg_get( - a_uint32_t dev_id, a_uint32_t phy_id, - union ptp_tx_filt_udp_port_reg_u *value); - -sw_error_t -qca808x_ptp_tx_filt_udp_port_reg_set( - a_uint32_t dev_id, a_uint32_t phy_id, - union ptp_tx_filt_udp_port_reg_u *value); - -sw_error_t -qca808x_ptp_tx_com_ts_status_reg_get( - a_uint32_t dev_id, a_uint32_t phy_id, - union ptp_tx_com_ts_status_reg_u *value); - -sw_error_t -qca808x_ptp_tx_com_ts_status_reg_set( - a_uint32_t dev_id, a_uint32_t phy_id, - union ptp_tx_com_ts_status_reg_u *value); - -sw_error_t -qca808x_ptp_tx_com_timestamp0_reg_get( - a_uint32_t dev_id, a_uint32_t phy_id, - union ptp_tx_com_timestamp0_reg_u *value); - -sw_error_t -qca808x_ptp_tx_com_timestamp0_reg_set( - a_uint32_t dev_id, a_uint32_t phy_id, - union ptp_tx_com_timestamp0_reg_u *value); - -sw_error_t -qca808x_ptp_tx_com_timestamp1_reg_get( - a_uint32_t dev_id, a_uint32_t phy_id, - union ptp_tx_com_timestamp1_reg_u *value); - -sw_error_t -qca808x_ptp_tx_com_timestamp1_reg_set( - a_uint32_t dev_id, a_uint32_t phy_id, - union ptp_tx_com_timestamp1_reg_u *value); - -sw_error_t -qca808x_ptp_tx_com_timestamp2_reg_get( - a_uint32_t dev_id, a_uint32_t phy_id, - union ptp_tx_com_timestamp2_reg_u *value); - -sw_error_t -qca808x_ptp_tx_com_timestamp2_reg_set( - a_uint32_t dev_id, a_uint32_t phy_id, - union ptp_tx_com_timestamp2_reg_u *value); - -sw_error_t -qca808x_ptp_tx_com_timestamp3_reg_get( - a_uint32_t dev_id, a_uint32_t phy_id, - union ptp_tx_com_timestamp3_reg_u *value); - -sw_error_t -qca808x_ptp_tx_com_timestamp3_reg_set( - a_uint32_t dev_id, a_uint32_t phy_id, - union ptp_tx_com_timestamp3_reg_u *value); - -sw_error_t -qca808x_ptp_tx_com_timestamp4_reg_get( - a_uint32_t dev_id, a_uint32_t phy_id, - union ptp_tx_com_timestamp4_reg_u *value); - -sw_error_t -qca808x_ptp_tx_com_timestamp4_reg_set( - a_uint32_t dev_id, a_uint32_t phy_id, - union ptp_tx_com_timestamp4_reg_u *value); - -sw_error_t -qca808x_ptp_tx_com_frac_nano_reg_get( - a_uint32_t dev_id, a_uint32_t phy_id, - union ptp_tx_com_frac_nano_reg_u *value); - -sw_error_t -qca808x_ptp_tx_com_frac_nano_reg_set( - a_uint32_t dev_id, a_uint32_t phy_id, - union ptp_tx_com_frac_nano_reg_u *value); - -sw_error_t -qca808x_ptp_tx_y1731_identify_reg_get( - a_uint32_t dev_id, a_uint32_t phy_id, - union ptp_tx_y1731_identify_reg_u *value); - -sw_error_t -qca808x_ptp_tx_y1731_identify_reg_set( - a_uint32_t dev_id, a_uint32_t phy_id, - union ptp_tx_y1731_identify_reg_u *value); - -sw_error_t -qca808x_ptp_y1731_dm_control_reg_get( - a_uint32_t dev_id, a_uint32_t phy_id, - union ptp_y1731_dm_control_reg_u *value); - -sw_error_t -qca808x_ptp_y1731_dm_control_reg_set( - a_uint32_t dev_id, a_uint32_t phy_id, - union ptp_y1731_dm_control_reg_u *value); - -sw_error_t -qca808x_ptp_rx_com_ts_status_pre_reg_get( - a_uint32_t dev_id, a_uint32_t phy_id, - union ptp_rx_com_ts_status_pre_reg_u *value); - -sw_error_t -qca808x_ptp_rx_com_ts_status_pre_reg_set( - a_uint32_t dev_id, a_uint32_t phy_id, - union ptp_rx_com_ts_status_pre_reg_u *value); - -sw_error_t -qca808x_ptp_baud_config_reg_get( - a_uint32_t dev_id, a_uint32_t phy_id, - union ptp_baud_config_reg_u *value); - -sw_error_t -qca808x_ptp_baud_config_reg_set( - a_uint32_t dev_id, a_uint32_t phy_id, - union ptp_baud_config_reg_u *value); - -sw_error_t -qca808x_ptp_uart_configuration_reg_get( - a_uint32_t dev_id, a_uint32_t phy_id, - union ptp_uart_configuration_reg_u *value); - -sw_error_t -qca808x_ptp_uart_configuration_reg_set( - a_uint32_t dev_id, a_uint32_t phy_id, - union ptp_uart_configuration_reg_u *value); - -sw_error_t -qca808x_ptp_reset_buffer_reg_get( - a_uint32_t dev_id, a_uint32_t phy_id, - union ptp_reset_buffer_reg_u *value); - -sw_error_t -qca808x_ptp_reset_buffer_reg_set( - a_uint32_t dev_id, a_uint32_t phy_id, - union ptp_reset_buffer_reg_u *value); - -sw_error_t -qca808x_ptp_buffer_status_reg_get( - a_uint32_t dev_id, a_uint32_t phy_id, - union ptp_buffer_status_reg_u *value); - -sw_error_t -qca808x_ptp_buffer_status_reg_set( - a_uint32_t dev_id, a_uint32_t phy_id, - union ptp_buffer_status_reg_u *value); - -sw_error_t -qca808x_ptp_tx_buffer_write_reg_get( - a_uint32_t dev_id, a_uint32_t phy_id, - union ptp_tx_buffer_write_reg_u *value); - -sw_error_t -qca808x_ptp_tx_buffer_write_reg_set( - a_uint32_t dev_id, a_uint32_t phy_id, - union ptp_tx_buffer_write_reg_u *value); - -sw_error_t -qca808x_ptp_rx_buffer_read_reg_get( - a_uint32_t dev_id, a_uint32_t phy_id, - union ptp_rx_buffer_read_reg_u *value); - -sw_error_t -qca808x_ptp_rx_buffer_read_reg_set( - a_uint32_t dev_id, a_uint32_t phy_id, - union ptp_rx_buffer_read_reg_u *value); - - -sw_error_t -qca808x_ptp_rx_com_ts_ctrl_reg_ipv4_da_en_get( - a_uint32_t dev_id, a_uint32_t phy_id, - unsigned int *value); - -sw_error_t -qca808x_ptp_rx_com_ts_ctrl_reg_ipv4_da_en_set( - a_uint32_t dev_id, a_uint32_t phy_id, - unsigned int value); - -sw_error_t -qca808x_ptp_rx_com_ts_ctrl_reg_mac_lengthtype_en_get( - a_uint32_t dev_id, a_uint32_t phy_id, - unsigned int *value); - -sw_error_t -qca808x_ptp_rx_com_ts_ctrl_reg_mac_lengthtype_en_set( - a_uint32_t dev_id, a_uint32_t phy_id, - unsigned int value); - -sw_error_t -qca808x_ptp_rx_com_ts_ctrl_reg_y1731_da_chk_en_get( - a_uint32_t dev_id, a_uint32_t phy_id, - unsigned int *value); - -sw_error_t -qca808x_ptp_rx_com_ts_ctrl_reg_y1731_da_chk_en_set( - a_uint32_t dev_id, a_uint32_t phy_id, - unsigned int value); - -sw_error_t -qca808x_ptp_rx_com_ts_ctrl_reg_pw_mac_en_get( - a_uint32_t dev_id, a_uint32_t phy_id, - unsigned int *value); - -sw_error_t -qca808x_ptp_rx_com_ts_ctrl_reg_pw_mac_en_set( - a_uint32_t dev_id, a_uint32_t phy_id, - unsigned int value); - -sw_error_t -qca808x_ptp_rx_com_ts_ctrl_reg_udp_ptp_event_filt_en_get( - a_uint32_t dev_id, a_uint32_t phy_id, - unsigned int *value); - -sw_error_t -qca808x_ptp_rx_com_ts_ctrl_reg_udp_ptp_event_filt_en_set( - a_uint32_t dev_id, a_uint32_t phy_id, - unsigned int value); - -sw_error_t -qca808x_ptp_rx_com_ts_ctrl_reg_udp_dport_en_get( - a_uint32_t dev_id, a_uint32_t phy_id, - unsigned int *value); - -sw_error_t -qca808x_ptp_rx_com_ts_ctrl_reg_udp_dport_en_set( - a_uint32_t dev_id, a_uint32_t phy_id, - unsigned int value); - -sw_error_t -qca808x_ptp_rx_com_ts_ctrl_reg_mac_ptp_filt_en_get( - a_uint32_t dev_id, a_uint32_t phy_id, - unsigned int *value); - -sw_error_t -qca808x_ptp_rx_com_ts_ctrl_reg_mac_ptp_filt_en_set( - a_uint32_t dev_id, a_uint32_t phy_id, - unsigned int value); - -sw_error_t -qca808x_ptp_rx_com_ts_ctrl_reg_ipv6_da_filt_en_get( - a_uint32_t dev_id, a_uint32_t phy_id, - unsigned int *value); - -sw_error_t -qca808x_ptp_rx_com_ts_ctrl_reg_ipv6_da_filt_en_set( - a_uint32_t dev_id, a_uint32_t phy_id, - unsigned int value); - -sw_error_t -qca808x_ptp_rx_com_ts_ctrl_reg_ipv6_next_header_en_get( - a_uint32_t dev_id, a_uint32_t phy_id, - unsigned int *value); - -sw_error_t -qca808x_ptp_rx_com_ts_ctrl_reg_ipv6_next_header_en_set( - a_uint32_t dev_id, a_uint32_t phy_id, - unsigned int value); - -sw_error_t -qca808x_ptp_rx_com_ts_ctrl_reg_ipv4_layer4_protocol_en_get( - a_uint32_t dev_id, a_uint32_t phy_id, - unsigned int *value); - -sw_error_t -qca808x_ptp_rx_com_ts_ctrl_reg_ipv4_layer4_protocol_en_set( - a_uint32_t dev_id, a_uint32_t phy_id, - unsigned int value); - -sw_error_t -qca808x_ptp_rx_com_ts_ctrl_reg_y1731_en_get( - a_uint32_t dev_id, a_uint32_t phy_id, - unsigned int *value); - -sw_error_t -qca808x_ptp_rx_com_ts_ctrl_reg_y1731_en_set( - a_uint32_t dev_id, a_uint32_t phy_id, - unsigned int value); - -sw_error_t -qca808x_ptp_rx_com_ts_ctrl_reg_filt_en_get( - a_uint32_t dev_id, a_uint32_t phy_id, - unsigned int *value); - -sw_error_t -qca808x_ptp_rx_com_ts_ctrl_reg_filt_en_set( - a_uint32_t dev_id, a_uint32_t phy_id, - unsigned int value); - -sw_error_t -qca808x_ptp_rx_com_ts_ctrl_reg_ipv6_ptp_filt_en_get( - a_uint32_t dev_id, a_uint32_t phy_id, - unsigned int *value); - -sw_error_t -qca808x_ptp_rx_com_ts_ctrl_reg_ipv6_ptp_filt_en_set( - a_uint32_t dev_id, a_uint32_t phy_id, - unsigned int value); - -sw_error_t -qca808x_ptp_rx_com_ts_ctrl_reg_ipv4_ptp_filt_en_get( - a_uint32_t dev_id, a_uint32_t phy_id, - unsigned int *value); - -sw_error_t -qca808x_ptp_rx_com_ts_ctrl_reg_ipv4_ptp_filt_en_set( - a_uint32_t dev_id, a_uint32_t phy_id, - unsigned int value); - -sw_error_t -qca808x_ptp_rx_com_ts_ctrl_reg_y1731_insert_ts_en_get( - a_uint32_t dev_id, a_uint32_t phy_id, - unsigned int *value); - -sw_error_t -qca808x_ptp_rx_com_ts_ctrl_reg_y1731_insert_ts_en_set( - a_uint32_t dev_id, a_uint32_t phy_id, - unsigned int value); - -sw_error_t -qca808x_ptp_rx_com_ts_ctrl_reg_mac_da_en_get( - a_uint32_t dev_id, a_uint32_t phy_id, - unsigned int *value); - -sw_error_t -qca808x_ptp_rx_com_ts_ctrl_reg_mac_da_en_set( - a_uint32_t dev_id, a_uint32_t phy_id, - unsigned int value); - -sw_error_t -qca808x_ptp_rx_filt_mac_da0_reg_mac_addr_get( - a_uint32_t dev_id, a_uint32_t phy_id, - unsigned int *value); - -sw_error_t -qca808x_ptp_rx_filt_mac_da0_reg_mac_addr_set( - a_uint32_t dev_id, a_uint32_t phy_id, - unsigned int value); - -sw_error_t -qca808x_ptp_rx_filt_mac_da1_reg_mac_addr_get( - a_uint32_t dev_id, a_uint32_t phy_id, - unsigned int *value); - -sw_error_t -qca808x_ptp_rx_filt_mac_da1_reg_mac_addr_set( - a_uint32_t dev_id, a_uint32_t phy_id, - unsigned int value); - -sw_error_t -qca808x_ptp_rx_filt_mac_da2_reg_mac_addr_get( - a_uint32_t dev_id, a_uint32_t phy_id, - unsigned int *value); - -sw_error_t -qca808x_ptp_rx_filt_mac_da2_reg_mac_addr_set( - a_uint32_t dev_id, a_uint32_t phy_id, - unsigned int value); - -sw_error_t -qca808x_ptp_rx_filt_ipv4_da0_reg_ip_addr_get( - a_uint32_t dev_id, a_uint32_t phy_id, - unsigned int *value); - -sw_error_t -qca808x_ptp_rx_filt_ipv4_da0_reg_ip_addr_set( - a_uint32_t dev_id, a_uint32_t phy_id, - unsigned int value); - -sw_error_t -qca808x_ptp_rx_filt_ipv4_da1_reg_ip_addr_get( - a_uint32_t dev_id, a_uint32_t phy_id, - unsigned int *value); - -sw_error_t -qca808x_ptp_rx_filt_ipv4_da1_reg_ip_addr_set( - a_uint32_t dev_id, a_uint32_t phy_id, - unsigned int value); - -sw_error_t -qca808x_ptp_rx_filt_ipv6_da0_reg_ip_addr_get( - a_uint32_t dev_id, a_uint32_t phy_id, - unsigned int *value); - -sw_error_t -qca808x_ptp_rx_filt_ipv6_da0_reg_ip_addr_set( - a_uint32_t dev_id, a_uint32_t phy_id, - unsigned int value); - -sw_error_t -qca808x_ptp_rx_filt_ipv6_da1_reg_ip_addr_get( - a_uint32_t dev_id, a_uint32_t phy_id, - unsigned int *value); - -sw_error_t -qca808x_ptp_rx_filt_ipv6_da1_reg_ip_addr_set( - a_uint32_t dev_id, a_uint32_t phy_id, - unsigned int value); - -sw_error_t -qca808x_ptp_rx_filt_ipv6_da2_reg_ip_addr_get( - a_uint32_t dev_id, a_uint32_t phy_id, - unsigned int *value); - -sw_error_t -qca808x_ptp_rx_filt_ipv6_da2_reg_ip_addr_set( - a_uint32_t dev_id, a_uint32_t phy_id, - unsigned int value); - -sw_error_t -qca808x_ptp_rx_filt_ipv6_da3_reg_ip_addr_get( - a_uint32_t dev_id, a_uint32_t phy_id, - unsigned int *value); - -sw_error_t -qca808x_ptp_rx_filt_ipv6_da3_reg_ip_addr_set( - a_uint32_t dev_id, a_uint32_t phy_id, - unsigned int value); - -sw_error_t -qca808x_ptp_rx_filt_ipv6_da4_reg_ip_addr_get( - a_uint32_t dev_id, a_uint32_t phy_id, - unsigned int *value); - -sw_error_t -qca808x_ptp_rx_filt_ipv6_da4_reg_ip_addr_set( - a_uint32_t dev_id, a_uint32_t phy_id, - unsigned int value); - -sw_error_t -qca808x_ptp_rx_filt_ipv6_da5_reg_ip_addr_get( - a_uint32_t dev_id, a_uint32_t phy_id, - unsigned int *value); - -sw_error_t -qca808x_ptp_rx_filt_ipv6_da5_reg_ip_addr_set( - a_uint32_t dev_id, a_uint32_t phy_id, - unsigned int value); - -sw_error_t -qca808x_ptp_rx_filt_ipv6_da6_reg_ip_addr_get( - a_uint32_t dev_id, a_uint32_t phy_id, - unsigned int *value); - -sw_error_t -qca808x_ptp_rx_filt_ipv6_da6_reg_ip_addr_set( - a_uint32_t dev_id, a_uint32_t phy_id, - unsigned int value); - -sw_error_t -qca808x_ptp_rx_filt_ipv6_da7_reg_ip_addr_get( - a_uint32_t dev_id, a_uint32_t phy_id, - unsigned int *value); - -sw_error_t -qca808x_ptp_rx_filt_ipv6_da7_reg_ip_addr_set( - a_uint32_t dev_id, a_uint32_t phy_id, - unsigned int value); - -sw_error_t -qca808x_ptp_rx_filt_mac_lengthtype_reg_length_type_get( - a_uint32_t dev_id, a_uint32_t phy_id, - unsigned int *value); - -sw_error_t -qca808x_ptp_rx_filt_mac_lengthtype_reg_length_type_set( - a_uint32_t dev_id, a_uint32_t phy_id, - unsigned int value); - -sw_error_t -qca808x_ptp_rx_filt_layer4_protocol_reg_l4_protocol_get( - a_uint32_t dev_id, a_uint32_t phy_id, - unsigned int *value); - -sw_error_t -qca808x_ptp_rx_filt_layer4_protocol_reg_l4_protocol_set( - a_uint32_t dev_id, a_uint32_t phy_id, - unsigned int value); - -sw_error_t -qca808x_ptp_rx_filt_udp_port_reg_udp_port_get( - a_uint32_t dev_id, a_uint32_t phy_id, - unsigned int *value); - -sw_error_t -qca808x_ptp_rx_filt_udp_port_reg_udp_port_set( - a_uint32_t dev_id, a_uint32_t phy_id, - unsigned int value); - -sw_error_t -qca808x_ptp_rx_com_ts_status_reg_mac_ptp_pdelay_addr_get( - a_uint32_t dev_id, a_uint32_t phy_id, - unsigned int *value); - -sw_error_t -qca808x_ptp_rx_com_ts_status_reg_mac_ptp_pdelay_addr_set( - a_uint32_t dev_id, a_uint32_t phy_id, - unsigned int value); - -sw_error_t -qca808x_ptp_rx_com_ts_status_reg_mac_da_get( - a_uint32_t dev_id, a_uint32_t phy_id, - unsigned int *value); - -sw_error_t -qca808x_ptp_rx_com_ts_status_reg_mac_da_set( - a_uint32_t dev_id, a_uint32_t phy_id, - unsigned int value); - -sw_error_t -qca808x_ptp_rx_com_ts_status_reg_ipv4_ptp_pdelay_addr_get( - a_uint32_t dev_id, a_uint32_t phy_id, - unsigned int *value); - -sw_error_t -qca808x_ptp_rx_com_ts_status_reg_ipv4_ptp_pdelay_addr_set( - a_uint32_t dev_id, a_uint32_t phy_id, - unsigned int value); - -sw_error_t -qca808x_ptp_rx_com_ts_status_reg_mac_lengthtype_get( - a_uint32_t dev_id, a_uint32_t phy_id, - unsigned int *value); - -sw_error_t -qca808x_ptp_rx_com_ts_status_reg_mac_lengthtype_set( - a_uint32_t dev_id, a_uint32_t phy_id, - unsigned int value); - -sw_error_t -qca808x_ptp_rx_com_ts_status_reg_udp_dport_get( - a_uint32_t dev_id, a_uint32_t phy_id, - unsigned int *value); - -sw_error_t -qca808x_ptp_rx_com_ts_status_reg_udp_dport_set( - a_uint32_t dev_id, a_uint32_t phy_id, - unsigned int value); - -sw_error_t -qca808x_ptp_rx_com_ts_status_reg_ipv4_layer4_protocol_get( - a_uint32_t dev_id, a_uint32_t phy_id, - unsigned int *value); - -sw_error_t -qca808x_ptp_rx_com_ts_status_reg_ipv4_layer4_protocol_set( - a_uint32_t dev_id, a_uint32_t phy_id, - unsigned int value); - -sw_error_t -qca808x_ptp_rx_com_ts_status_reg_udp_ptp_event_dport_get( - a_uint32_t dev_id, a_uint32_t phy_id, - unsigned int *value); - -sw_error_t -qca808x_ptp_rx_com_ts_status_reg_udp_ptp_event_dport_set( - a_uint32_t dev_id, a_uint32_t phy_id, - unsigned int value); - -sw_error_t -qca808x_ptp_rx_com_ts_status_reg_ipv6_da_get( - a_uint32_t dev_id, a_uint32_t phy_id, - unsigned int *value); - -sw_error_t -qca808x_ptp_rx_com_ts_status_reg_ipv6_da_set( - a_uint32_t dev_id, a_uint32_t phy_id, - unsigned int value); - -sw_error_t -qca808x_ptp_rx_com_ts_status_reg_ipv4_ptp_prim_addr_get( - a_uint32_t dev_id, a_uint32_t phy_id, - unsigned int *value); - -sw_error_t -qca808x_ptp_rx_com_ts_status_reg_ipv4_ptp_prim_addr_set( - a_uint32_t dev_id, a_uint32_t phy_id, - unsigned int value); - -sw_error_t -qca808x_ptp_rx_com_ts_status_reg_ipv4_da_get( - a_uint32_t dev_id, a_uint32_t phy_id, - unsigned int *value); - -sw_error_t -qca808x_ptp_rx_com_ts_status_reg_ipv4_da_set( - a_uint32_t dev_id, a_uint32_t phy_id, - unsigned int value); - -sw_error_t -qca808x_ptp_rx_com_ts_status_reg_ipv6_ptp_pdelay_addr_get( - a_uint32_t dev_id, a_uint32_t phy_id, - unsigned int *value); - -sw_error_t -qca808x_ptp_rx_com_ts_status_reg_ipv6_ptp_pdelay_addr_set( - a_uint32_t dev_id, a_uint32_t phy_id, - unsigned int value); - -sw_error_t -qca808x_ptp_rx_com_ts_status_reg_ipv6_ptp_prim_addr_get( - a_uint32_t dev_id, a_uint32_t phy_id, - unsigned int *value); - -sw_error_t -qca808x_ptp_rx_com_ts_status_reg_ipv6_ptp_prim_addr_set( - a_uint32_t dev_id, a_uint32_t phy_id, - unsigned int value); - -sw_error_t -qca808x_ptp_rx_com_ts_status_reg_ipv6_next_header_get( - a_uint32_t dev_id, a_uint32_t phy_id, - unsigned int *value); - -sw_error_t -qca808x_ptp_rx_com_ts_status_reg_ipv6_next_header_set( - a_uint32_t dev_id, a_uint32_t phy_id, - unsigned int value); - -sw_error_t -qca808x_ptp_rx_com_ts_status_reg_y1731_mach_get( - a_uint32_t dev_id, a_uint32_t phy_id, - unsigned int *value); - -sw_error_t -qca808x_ptp_rx_com_ts_status_reg_y1731_mach_set( - a_uint32_t dev_id, a_uint32_t phy_id, - unsigned int value); - -sw_error_t -qca808x_ptp_rx_com_ts_status_reg_mac_ptp_prim_addr_get( - a_uint32_t dev_id, a_uint32_t phy_id, - unsigned int *value); - -sw_error_t -qca808x_ptp_rx_com_ts_status_reg_mac_ptp_prim_addr_set( - a_uint32_t dev_id, a_uint32_t phy_id, - unsigned int value); - -sw_error_t -qca808x_ptp_rx_com_timestamp0_reg_com_ts_get( - a_uint32_t dev_id, a_uint32_t phy_id, - unsigned int *value); - -sw_error_t -qca808x_ptp_rx_com_timestamp0_reg_com_ts_set( - a_uint32_t dev_id, a_uint32_t phy_id, - unsigned int value); - -sw_error_t -qca808x_ptp_rx_com_timestamp1_reg_com_ts_get( - a_uint32_t dev_id, a_uint32_t phy_id, - unsigned int *value); - -sw_error_t -qca808x_ptp_rx_com_timestamp1_reg_com_ts_set( - a_uint32_t dev_id, a_uint32_t phy_id, - unsigned int value); - -sw_error_t -qca808x_ptp_rx_com_timestamp2_reg_com_ts_get( - a_uint32_t dev_id, a_uint32_t phy_id, - unsigned int *value); - -sw_error_t -qca808x_ptp_rx_com_timestamp2_reg_com_ts_set( - a_uint32_t dev_id, a_uint32_t phy_id, - unsigned int value); - -sw_error_t -qca808x_ptp_rx_com_timestamp3_reg_com_ts_get( - a_uint32_t dev_id, a_uint32_t phy_id, - unsigned int *value); - -sw_error_t -qca808x_ptp_rx_com_timestamp3_reg_com_ts_set( - a_uint32_t dev_id, a_uint32_t phy_id, - unsigned int value); - -sw_error_t -qca808x_ptp_rx_com_timestamp4_reg_com_ts_get( - a_uint32_t dev_id, a_uint32_t phy_id, - unsigned int *value); - -sw_error_t -qca808x_ptp_rx_com_timestamp4_reg_com_ts_set( - a_uint32_t dev_id, a_uint32_t phy_id, - unsigned int value); - -sw_error_t -qca808x_ptp_rx_com_frac_nano_reg_frac_nano_get( - a_uint32_t dev_id, a_uint32_t phy_id, - unsigned int *value); - -sw_error_t -qca808x_ptp_rx_com_frac_nano_reg_frac_nano_set( - a_uint32_t dev_id, a_uint32_t phy_id, - unsigned int value); - -sw_error_t -qca808x_ptp_rx_com_timestamp_pre0_reg_com_ts_pre_get( - a_uint32_t dev_id, a_uint32_t phy_id, - unsigned int *value); - -sw_error_t -qca808x_ptp_rx_com_timestamp_pre0_reg_com_ts_pre_set( - a_uint32_t dev_id, a_uint32_t phy_id, - unsigned int value); - -sw_error_t -qca808x_ptp_rx_com_timestamp_pre1_reg_com_ts_pre_get( - a_uint32_t dev_id, a_uint32_t phy_id, - unsigned int *value); - -sw_error_t -qca808x_ptp_rx_com_timestamp_pre1_reg_com_ts_pre_set( - a_uint32_t dev_id, a_uint32_t phy_id, - unsigned int value); - -sw_error_t -qca808x_ptp_rx_com_timestamp_pre2_reg_com_ts_pre_get( - a_uint32_t dev_id, a_uint32_t phy_id, - unsigned int *value); - -sw_error_t -qca808x_ptp_rx_com_timestamp_pre2_reg_com_ts_pre_set( - a_uint32_t dev_id, a_uint32_t phy_id, - unsigned int value); - -sw_error_t -qca808x_ptp_rx_com_timestamp_pre3_reg_com_ts_pre_get( - a_uint32_t dev_id, a_uint32_t phy_id, - unsigned int *value); - -sw_error_t -qca808x_ptp_rx_com_timestamp_pre3_reg_com_ts_pre_set( - a_uint32_t dev_id, a_uint32_t phy_id, - unsigned int value); - -sw_error_t -qca808x_ptp_rx_com_timestamp_pre4_reg_com_ts_pre_get( - a_uint32_t dev_id, a_uint32_t phy_id, - unsigned int *value); - -sw_error_t -qca808x_ptp_rx_com_timestamp_pre4_reg_com_ts_pre_set( - a_uint32_t dev_id, a_uint32_t phy_id, - unsigned int value); - -sw_error_t -qca808x_ptp_rx_com_frac_nano_pre_reg_frac_nano_pre_get( - a_uint32_t dev_id, a_uint32_t phy_id, - unsigned int *value); - -sw_error_t -qca808x_ptp_rx_com_frac_nano_pre_reg_frac_nano_pre_set( - a_uint32_t dev_id, a_uint32_t phy_id, - unsigned int value); - -sw_error_t -qca808x_ptp_rx_y1731_identify_reg_identify_get( - a_uint32_t dev_id, a_uint32_t phy_id, - unsigned int *value); - -sw_error_t -qca808x_ptp_rx_y1731_identify_reg_identify_set( - a_uint32_t dev_id, a_uint32_t phy_id, - unsigned int value); - -sw_error_t -qca808x_ptp_rx_y1731_identify_pre_reg_identify_pre_get( - a_uint32_t dev_id, a_uint32_t phy_id, - unsigned int *value); - -sw_error_t -qca808x_ptp_rx_y1731_identify_pre_reg_identify_pre_set( - a_uint32_t dev_id, a_uint32_t phy_id, - unsigned int value); - -sw_error_t -qca808x_ptp_tx_com_ts_ctrl_reg_ipv4_da_en_get( - a_uint32_t dev_id, a_uint32_t phy_id, - unsigned int *value); - -sw_error_t -qca808x_ptp_tx_com_ts_ctrl_reg_ipv4_da_en_set( - a_uint32_t dev_id, a_uint32_t phy_id, - unsigned int value); - -sw_error_t -qca808x_ptp_tx_com_ts_ctrl_reg_mac_lengthtype_en_get( - a_uint32_t dev_id, a_uint32_t phy_id, - unsigned int *value); - -sw_error_t -qca808x_ptp_tx_com_ts_ctrl_reg_mac_lengthtype_en_set( - a_uint32_t dev_id, a_uint32_t phy_id, - unsigned int value); - -sw_error_t -qca808x_ptp_tx_com_ts_ctrl_reg_ipv6_da_en_get( - a_uint32_t dev_id, a_uint32_t phy_id, - unsigned int *value); - -sw_error_t -qca808x_ptp_tx_com_ts_ctrl_reg_ipv6_da_en_set( - a_uint32_t dev_id, a_uint32_t phy_id, - unsigned int value); - -sw_error_t -qca808x_ptp_tx_com_ts_ctrl_reg_pw_mac_en_get( - a_uint32_t dev_id, a_uint32_t phy_id, - unsigned int *value); - -sw_error_t -qca808x_ptp_tx_com_ts_ctrl_reg_pw_mac_en_set( - a_uint32_t dev_id, a_uint32_t phy_id, - unsigned int value); - -sw_error_t -qca808x_ptp_tx_com_ts_ctrl_reg_udp_ptp_event_filt_en_get( - a_uint32_t dev_id, a_uint32_t phy_id, - unsigned int *value); - -sw_error_t -qca808x_ptp_tx_com_ts_ctrl_reg_udp_ptp_event_filt_en_set( - a_uint32_t dev_id, a_uint32_t phy_id, - unsigned int value); - -sw_error_t -qca808x_ptp_tx_com_ts_ctrl_reg_udp_dport_en_get( - a_uint32_t dev_id, a_uint32_t phy_id, - unsigned int *value); - -sw_error_t -qca808x_ptp_tx_com_ts_ctrl_reg_udp_dport_en_set( - a_uint32_t dev_id, a_uint32_t phy_id, - unsigned int value); - -sw_error_t -qca808x_ptp_tx_com_ts_ctrl_reg_mac_ptp_filt_en_get( - a_uint32_t dev_id, a_uint32_t phy_id, - unsigned int *value); - -sw_error_t -qca808x_ptp_tx_com_ts_ctrl_reg_mac_ptp_filt_en_set( - a_uint32_t dev_id, a_uint32_t phy_id, - unsigned int value); - -sw_error_t -qca808x_ptp_tx_com_ts_ctrl_reg_ipv6_next_header_en_get( - a_uint32_t dev_id, a_uint32_t phy_id, - unsigned int *value); - -sw_error_t -qca808x_ptp_tx_com_ts_ctrl_reg_ipv6_next_header_en_set( - a_uint32_t dev_id, a_uint32_t phy_id, - unsigned int value); - -sw_error_t -qca808x_ptp_tx_com_ts_ctrl_reg_ipv4_layer4_protocol_en_get( - a_uint32_t dev_id, a_uint32_t phy_id, - unsigned int *value); - -sw_error_t -qca808x_ptp_tx_com_ts_ctrl_reg_ipv4_layer4_protocol_en_set( - a_uint32_t dev_id, a_uint32_t phy_id, - unsigned int value); - -sw_error_t -qca808x_ptp_tx_com_ts_ctrl_reg_y1731_en_get( - a_uint32_t dev_id, a_uint32_t phy_id, - unsigned int *value); - -sw_error_t -qca808x_ptp_tx_com_ts_ctrl_reg_y1731_en_set( - a_uint32_t dev_id, a_uint32_t phy_id, - unsigned int value); - -sw_error_t -qca808x_ptp_tx_com_ts_ctrl_reg_filt_en_get( - a_uint32_t dev_id, a_uint32_t phy_id, - unsigned int *value); - -sw_error_t -qca808x_ptp_tx_com_ts_ctrl_reg_filt_en_set( - a_uint32_t dev_id, a_uint32_t phy_id, - unsigned int value); - -sw_error_t -qca808x_ptp_tx_com_ts_ctrl_reg_ipv6_ptp_filt_en_get( - a_uint32_t dev_id, a_uint32_t phy_id, - unsigned int *value); - -sw_error_t -qca808x_ptp_tx_com_ts_ctrl_reg_ipv6_ptp_filt_en_set( - a_uint32_t dev_id, a_uint32_t phy_id, - unsigned int value); - -sw_error_t -qca808x_ptp_tx_com_ts_ctrl_reg_ipv4_ptp_filt_en_get( - a_uint32_t dev_id, a_uint32_t phy_id, - unsigned int *value); - -sw_error_t -qca808x_ptp_tx_com_ts_ctrl_reg_ipv4_ptp_filt_en_set( - a_uint32_t dev_id, a_uint32_t phy_id, - unsigned int value); - -sw_error_t -qca808x_ptp_tx_com_ts_ctrl_reg_y1731_insert_ts_en_get( - a_uint32_t dev_id, a_uint32_t phy_id, - unsigned int *value); - -sw_error_t -qca808x_ptp_tx_com_ts_ctrl_reg_y1731_insert_ts_en_set( - a_uint32_t dev_id, a_uint32_t phy_id, - unsigned int value); - -sw_error_t -qca808x_ptp_tx_com_ts_ctrl_reg_mac_da_en_get( - a_uint32_t dev_id, a_uint32_t phy_id, - unsigned int *value); - -sw_error_t -qca808x_ptp_tx_com_ts_ctrl_reg_mac_da_en_set( - a_uint32_t dev_id, a_uint32_t phy_id, - unsigned int value); - -sw_error_t -qca808x_ptp_tx_com_ts_ctrl_reg_y1731_sa_chk_en_get( - a_uint32_t dev_id, a_uint32_t phy_id, - unsigned int *value); - -sw_error_t -qca808x_ptp_tx_com_ts_ctrl_reg_y1731_sa_chk_en_set( - a_uint32_t dev_id, a_uint32_t phy_id, - unsigned int value); - -sw_error_t -qca808x_ptp_tx_filt_mac_da0_reg_mac_addr_get( - a_uint32_t dev_id, a_uint32_t phy_id, - unsigned int *value); - -sw_error_t -qca808x_ptp_tx_filt_mac_da0_reg_mac_addr_set( - a_uint32_t dev_id, a_uint32_t phy_id, - unsigned int value); - -sw_error_t -qca808x_ptp_tx_filt_mac_da1_reg_mac_addr_get( - a_uint32_t dev_id, a_uint32_t phy_id, - unsigned int *value); - -sw_error_t -qca808x_ptp_tx_filt_mac_da1_reg_mac_addr_set( - a_uint32_t dev_id, a_uint32_t phy_id, - unsigned int value); - -sw_error_t -qca808x_ptp_tx_filt_mac_da2_reg_mac_addr_get( - a_uint32_t dev_id, a_uint32_t phy_id, - unsigned int *value); - -sw_error_t -qca808x_ptp_tx_filt_mac_da2_reg_mac_addr_set( - a_uint32_t dev_id, a_uint32_t phy_id, - unsigned int value); - -sw_error_t -qca808x_ptp_tx_filt_ipv4_da0_reg_ip_addr_get( - a_uint32_t dev_id, a_uint32_t phy_id, - unsigned int *value); - -sw_error_t -qca808x_ptp_tx_filt_ipv4_da0_reg_ip_addr_set( - a_uint32_t dev_id, a_uint32_t phy_id, - unsigned int value); - -sw_error_t -qca808x_ptp_tx_filt_ipv4_da1_reg_ip_addr_get( - a_uint32_t dev_id, a_uint32_t phy_id, - unsigned int *value); - -sw_error_t -qca808x_ptp_tx_filt_ipv4_da1_reg_ip_addr_set( - a_uint32_t dev_id, a_uint32_t phy_id, - unsigned int value); - -sw_error_t -qca808x_ptp_tx_filt_ipv6_da0_reg_ip_addr_get( - a_uint32_t dev_id, a_uint32_t phy_id, - unsigned int *value); - -sw_error_t -qca808x_ptp_tx_filt_ipv6_da0_reg_ip_addr_set( - a_uint32_t dev_id, a_uint32_t phy_id, - unsigned int value); - -sw_error_t -qca808x_ptp_tx_filt_ipv6_da1_reg_ip_addr_get( - a_uint32_t dev_id, a_uint32_t phy_id, - unsigned int *value); - -sw_error_t -qca808x_ptp_tx_filt_ipv6_da1_reg_ip_addr_set( - a_uint32_t dev_id, a_uint32_t phy_id, - unsigned int value); - -sw_error_t -qca808x_ptp_tx_filt_ipv6_da2_reg_ip_addr_get( - a_uint32_t dev_id, a_uint32_t phy_id, - unsigned int *value); - -sw_error_t -qca808x_ptp_tx_filt_ipv6_da2_reg_ip_addr_set( - a_uint32_t dev_id, a_uint32_t phy_id, - unsigned int value); - -sw_error_t -qca808x_ptp_tx_filt_ipv6_da3_reg_ip_addr_get( - a_uint32_t dev_id, a_uint32_t phy_id, - unsigned int *value); - -sw_error_t -qca808x_ptp_tx_filt_ipv6_da3_reg_ip_addr_set( - a_uint32_t dev_id, a_uint32_t phy_id, - unsigned int value); - -sw_error_t -qca808x_ptp_tx_filt_ipv6_da4_reg_ip_addr_get( - a_uint32_t dev_id, a_uint32_t phy_id, - unsigned int *value); - -sw_error_t -qca808x_ptp_tx_filt_ipv6_da4_reg_ip_addr_set( - a_uint32_t dev_id, a_uint32_t phy_id, - unsigned int value); - -sw_error_t -qca808x_ptp_tx_filt_ipv6_da5_reg_ip_addr_get( - a_uint32_t dev_id, a_uint32_t phy_id, - unsigned int *value); - -sw_error_t -qca808x_ptp_tx_filt_ipv6_da5_reg_ip_addr_set( - a_uint32_t dev_id, a_uint32_t phy_id, - unsigned int value); - -sw_error_t -qca808x_ptp_tx_filt_ipv6_da6_reg_ip_addr_get( - a_uint32_t dev_id, a_uint32_t phy_id, - unsigned int *value); - -sw_error_t -qca808x_ptp_tx_filt_ipv6_da6_reg_ip_addr_set( - a_uint32_t dev_id, a_uint32_t phy_id, - unsigned int value); - -sw_error_t -qca808x_ptp_tx_filt_ipv6_da7_reg_ip_addr_get( - a_uint32_t dev_id, a_uint32_t phy_id, - unsigned int *value); - -sw_error_t -qca808x_ptp_tx_filt_ipv6_da7_reg_ip_addr_set( - a_uint32_t dev_id, a_uint32_t phy_id, - unsigned int value); - -sw_error_t -qca808x_ptp_tx_filt_mac_lengthtype_reg_length_type_get( - a_uint32_t dev_id, a_uint32_t phy_id, - unsigned int *value); - -sw_error_t -qca808x_ptp_tx_filt_mac_lengthtype_reg_length_type_set( - a_uint32_t dev_id, a_uint32_t phy_id, - unsigned int value); - -sw_error_t -qca808x_ptp_tx_filt_layer4_protocol_reg_l4_protocol_get( - a_uint32_t dev_id, a_uint32_t phy_id, - unsigned int *value); - -sw_error_t -qca808x_ptp_tx_filt_layer4_protocol_reg_l4_protocol_set( - a_uint32_t dev_id, a_uint32_t phy_id, - unsigned int value); - -sw_error_t -qca808x_ptp_tx_filt_udp_port_reg_udp_port_get( - a_uint32_t dev_id, a_uint32_t phy_id, - unsigned int *value); - -sw_error_t -qca808x_ptp_tx_filt_udp_port_reg_udp_port_set( - a_uint32_t dev_id, a_uint32_t phy_id, - unsigned int value); - -sw_error_t -qca808x_ptp_tx_com_ts_status_reg_mac_ptp_pdelay_addr_get( - a_uint32_t dev_id, a_uint32_t phy_id, - unsigned int *value); - -sw_error_t -qca808x_ptp_tx_com_ts_status_reg_mac_ptp_pdelay_addr_set( - a_uint32_t dev_id, a_uint32_t phy_id, - unsigned int value); - -sw_error_t -qca808x_ptp_tx_com_ts_status_reg_mac_da_get( - a_uint32_t dev_id, a_uint32_t phy_id, - unsigned int *value); - -sw_error_t -qca808x_ptp_tx_com_ts_status_reg_mac_da_set( - a_uint32_t dev_id, a_uint32_t phy_id, - unsigned int value); - -sw_error_t -qca808x_ptp_tx_com_ts_status_reg_ipv4_ptp_pdelay_addr_get( - a_uint32_t dev_id, a_uint32_t phy_id, - unsigned int *value); - -sw_error_t -qca808x_ptp_tx_com_ts_status_reg_ipv4_ptp_pdelay_addr_set( - a_uint32_t dev_id, a_uint32_t phy_id, - unsigned int value); - -sw_error_t -qca808x_ptp_tx_com_ts_status_reg_mac_lengthtype_get( - a_uint32_t dev_id, a_uint32_t phy_id, - unsigned int *value); - -sw_error_t -qca808x_ptp_tx_com_ts_status_reg_mac_lengthtype_set( - a_uint32_t dev_id, a_uint32_t phy_id, - unsigned int value); - -sw_error_t -qca808x_ptp_tx_com_ts_status_reg_udp_dport_get( - a_uint32_t dev_id, a_uint32_t phy_id, - unsigned int *value); - -sw_error_t -qca808x_ptp_tx_com_ts_status_reg_udp_dport_set( - a_uint32_t dev_id, a_uint32_t phy_id, - unsigned int value); - -sw_error_t -qca808x_ptp_tx_com_ts_status_reg_ipv4_layer4_protocol_get( - a_uint32_t dev_id, a_uint32_t phy_id, - unsigned int *value); - -sw_error_t -qca808x_ptp_tx_com_ts_status_reg_ipv4_layer4_protocol_set( - a_uint32_t dev_id, a_uint32_t phy_id, - unsigned int value); - -sw_error_t -qca808x_ptp_tx_com_ts_status_reg_udp_ptp_event_dport_get( - a_uint32_t dev_id, a_uint32_t phy_id, - unsigned int *value); - -sw_error_t -qca808x_ptp_tx_com_ts_status_reg_udp_ptp_event_dport_set( - a_uint32_t dev_id, a_uint32_t phy_id, - unsigned int value); - -sw_error_t -qca808x_ptp_tx_com_ts_status_reg_ipv6_da_get( - a_uint32_t dev_id, a_uint32_t phy_id, - unsigned int *value); - -sw_error_t -qca808x_ptp_tx_com_ts_status_reg_ipv6_da_set( - a_uint32_t dev_id, a_uint32_t phy_id, - unsigned int value); - -sw_error_t -qca808x_ptp_tx_com_ts_status_reg_ipv4_ptp_prim_addr_get( - a_uint32_t dev_id, a_uint32_t phy_id, - unsigned int *value); - -sw_error_t -qca808x_ptp_tx_com_ts_status_reg_ipv4_ptp_prim_addr_set( - a_uint32_t dev_id, a_uint32_t phy_id, - unsigned int value); - -sw_error_t -qca808x_ptp_tx_com_ts_status_reg_ipv4_da_get( - a_uint32_t dev_id, a_uint32_t phy_id, - unsigned int *value); - -sw_error_t -qca808x_ptp_tx_com_ts_status_reg_ipv4_da_set( - a_uint32_t dev_id, a_uint32_t phy_id, - unsigned int value); - -sw_error_t -qca808x_ptp_tx_com_ts_status_reg_ipv6_ptp_pdelay_addr_get( - a_uint32_t dev_id, a_uint32_t phy_id, - unsigned int *value); - -sw_error_t -qca808x_ptp_tx_com_ts_status_reg_ipv6_ptp_pdelay_addr_set( - a_uint32_t dev_id, a_uint32_t phy_id, - unsigned int value); - -sw_error_t -qca808x_ptp_tx_com_ts_status_reg_ipv6_ptp_prim_addr_get( - a_uint32_t dev_id, a_uint32_t phy_id, - unsigned int *value); - -sw_error_t -qca808x_ptp_tx_com_ts_status_reg_ipv6_ptp_prim_addr_set( - a_uint32_t dev_id, a_uint32_t phy_id, - unsigned int value); - -sw_error_t -qca808x_ptp_tx_com_ts_status_reg_ipv6_next_header_get( - a_uint32_t dev_id, a_uint32_t phy_id, - unsigned int *value); - -sw_error_t -qca808x_ptp_tx_com_ts_status_reg_ipv6_next_header_set( - a_uint32_t dev_id, a_uint32_t phy_id, - unsigned int value); - -sw_error_t -qca808x_ptp_tx_com_ts_status_reg_y1731_mach_get( - a_uint32_t dev_id, a_uint32_t phy_id, - unsigned int *value); - -sw_error_t -qca808x_ptp_tx_com_ts_status_reg_y1731_mach_set( - a_uint32_t dev_id, a_uint32_t phy_id, - unsigned int value); - -sw_error_t -qca808x_ptp_tx_com_ts_status_reg_mac_ptp_prim_addr_get( - a_uint32_t dev_id, a_uint32_t phy_id, - unsigned int *value); - -sw_error_t -qca808x_ptp_tx_com_ts_status_reg_mac_ptp_prim_addr_set( - a_uint32_t dev_id, a_uint32_t phy_id, - unsigned int value); - -sw_error_t -qca808x_ptp_tx_com_timestamp0_reg_com_ts_get( - a_uint32_t dev_id, a_uint32_t phy_id, - unsigned int *value); - -sw_error_t -qca808x_ptp_tx_com_timestamp0_reg_com_ts_set( - a_uint32_t dev_id, a_uint32_t phy_id, - unsigned int value); - -sw_error_t -qca808x_ptp_tx_com_timestamp1_reg_com_ts_get( - a_uint32_t dev_id, a_uint32_t phy_id, - unsigned int *value); - -sw_error_t -qca808x_ptp_tx_com_timestamp1_reg_com_ts_set( - a_uint32_t dev_id, a_uint32_t phy_id, - unsigned int value); - -sw_error_t -qca808x_ptp_tx_com_timestamp2_reg_com_ts_get( - a_uint32_t dev_id, a_uint32_t phy_id, - unsigned int *value); - -sw_error_t -qca808x_ptp_tx_com_timestamp2_reg_com_ts_set( - a_uint32_t dev_id, a_uint32_t phy_id, - unsigned int value); - -sw_error_t -qca808x_ptp_tx_com_timestamp3_reg_com_ts_get( - a_uint32_t dev_id, a_uint32_t phy_id, - unsigned int *value); - -sw_error_t -qca808x_ptp_tx_com_timestamp3_reg_com_ts_set( - a_uint32_t dev_id, a_uint32_t phy_id, - unsigned int value); - -sw_error_t -qca808x_ptp_tx_com_timestamp4_reg_com_ts_get( - a_uint32_t dev_id, a_uint32_t phy_id, - unsigned int *value); - -sw_error_t -qca808x_ptp_tx_com_timestamp4_reg_com_ts_set( - a_uint32_t dev_id, a_uint32_t phy_id, - unsigned int value); - -sw_error_t -qca808x_ptp_tx_com_frac_nano_reg_frac_nano_get( - a_uint32_t dev_id, a_uint32_t phy_id, - unsigned int *value); - -sw_error_t -qca808x_ptp_tx_com_frac_nano_reg_frac_nano_set( - a_uint32_t dev_id, a_uint32_t phy_id, - unsigned int value); - -sw_error_t -qca808x_ptp_tx_y1731_identify_reg_identify_get( - a_uint32_t dev_id, a_uint32_t phy_id, - unsigned int *value); - -sw_error_t -qca808x_ptp_tx_y1731_identify_reg_identify_set( - a_uint32_t dev_id, a_uint32_t phy_id, - unsigned int value); - -sw_error_t -qca808x_ptp_y1731_dm_control_reg_y1731_dmm_lpbk_en_get( - a_uint32_t dev_id, a_uint32_t phy_id, - unsigned int *value); - -sw_error_t -qca808x_ptp_y1731_dm_control_reg_y1731_dmm_lpbk_en_set( - a_uint32_t dev_id, a_uint32_t phy_id, - unsigned int value); - -sw_error_t -qca808x_ptp_y1731_dm_control_reg_valid_msg_lev_bmp_get( - a_uint32_t dev_id, a_uint32_t phy_id, - unsigned int *value); - -sw_error_t -qca808x_ptp_y1731_dm_control_reg_valid_msg_lev_bmp_set( - a_uint32_t dev_id, a_uint32_t phy_id, - unsigned int value); - -sw_error_t -qca808x_ptp_baud_config_reg_baud_rate_get( - a_uint32_t dev_id, a_uint32_t phy_id, - unsigned int *value); - -sw_error_t -qca808x_ptp_baud_config_reg_baud_rate_set( - a_uint32_t dev_id, a_uint32_t phy_id, - unsigned int value); - -sw_error_t -qca808x_ptp_uart_configuration_reg_start_polarity_get( - a_uint32_t dev_id, a_uint32_t phy_id, - unsigned int *value); - -sw_error_t -qca808x_ptp_uart_configuration_reg_start_polarity_set( - a_uint32_t dev_id, a_uint32_t phy_id, - unsigned int value); - -sw_error_t -qca808x_ptp_uart_configuration_reg_msb_first_get( - a_uint32_t dev_id, a_uint32_t phy_id, - unsigned int *value); - -sw_error_t -qca808x_ptp_uart_configuration_reg_msb_first_set( - a_uint32_t dev_id, a_uint32_t phy_id, - unsigned int value); - -sw_error_t -qca808x_ptp_uart_configuration_reg_parity_en_get( - a_uint32_t dev_id, a_uint32_t phy_id, - unsigned int *value); - -sw_error_t -qca808x_ptp_uart_configuration_reg_parity_en_set( - a_uint32_t dev_id, a_uint32_t phy_id, - unsigned int value); - -sw_error_t -qca808x_ptp_uart_configuration_reg_auto_tod_out_en_get( - a_uint32_t dev_id, a_uint32_t phy_id, - unsigned int *value); - -sw_error_t -qca808x_ptp_uart_configuration_reg_auto_tod_out_en_set( - a_uint32_t dev_id, a_uint32_t phy_id, - unsigned int value); - -sw_error_t -qca808x_ptp_uart_configuration_reg_auto_tod_in_en_get( - a_uint32_t dev_id, a_uint32_t phy_id, - unsigned int *value); - -sw_error_t -qca808x_ptp_uart_configuration_reg_auto_tod_in_en_set( - a_uint32_t dev_id, a_uint32_t phy_id, - unsigned int value); - -sw_error_t -qca808x_ptp_reset_buffer_reg_reset_get( - a_uint32_t dev_id, a_uint32_t phy_id, - unsigned int *value); - -sw_error_t -qca808x_ptp_reset_buffer_reg_reset_set( - a_uint32_t dev_id, a_uint32_t phy_id, - unsigned int value); - -sw_error_t -qca808x_ptp_buffer_status_reg_tx_buffer_almost_empty_get( - a_uint32_t dev_id, a_uint32_t phy_id, - unsigned int *value); - -sw_error_t -qca808x_ptp_buffer_status_reg_tx_buffer_almost_empty_set( - a_uint32_t dev_id, a_uint32_t phy_id, - unsigned int value); - -sw_error_t -qca808x_ptp_buffer_status_reg_tx_buffer_almost_full_get( - a_uint32_t dev_id, a_uint32_t phy_id, - unsigned int *value); - -sw_error_t -qca808x_ptp_buffer_status_reg_tx_buffer_almost_full_set( - a_uint32_t dev_id, a_uint32_t phy_id, - unsigned int value); - -sw_error_t -qca808x_ptp_buffer_status_reg_tx_buffer_half_full_get( - a_uint32_t dev_id, a_uint32_t phy_id, - unsigned int *value); - -sw_error_t -qca808x_ptp_buffer_status_reg_tx_buffer_half_full_set( - a_uint32_t dev_id, a_uint32_t phy_id, - unsigned int value); - -sw_error_t -qca808x_ptp_buffer_status_reg_tx_buffer_full_get( - a_uint32_t dev_id, a_uint32_t phy_id, - unsigned int *value); - -sw_error_t -qca808x_ptp_buffer_status_reg_tx_buffer_full_set( - a_uint32_t dev_id, a_uint32_t phy_id, - unsigned int value); - -sw_error_t -qca808x_ptp_buffer_status_reg_rx_buffer_almost_empty_get( - a_uint32_t dev_id, a_uint32_t phy_id, - unsigned int *value); - -sw_error_t -qca808x_ptp_buffer_status_reg_rx_buffer_almost_empty_set( - a_uint32_t dev_id, a_uint32_t phy_id, - unsigned int value); - -sw_error_t -qca808x_ptp_buffer_status_reg_rx_buffer_almost_full_get( - a_uint32_t dev_id, a_uint32_t phy_id, - unsigned int *value); - -sw_error_t -qca808x_ptp_buffer_status_reg_rx_buffer_almost_full_set( - a_uint32_t dev_id, a_uint32_t phy_id, - unsigned int value); - -sw_error_t -qca808x_ptp_buffer_status_reg_rx_buffer_half_full_get( - a_uint32_t dev_id, a_uint32_t phy_id, - unsigned int *value); - -sw_error_t -qca808x_ptp_buffer_status_reg_rx_buffer_half_full_set( - a_uint32_t dev_id, a_uint32_t phy_id, - unsigned int value); - -sw_error_t -qca808x_ptp_buffer_status_reg_rx_buffer_full_get( - a_uint32_t dev_id, a_uint32_t phy_id, - unsigned int *value); - -sw_error_t -qca808x_ptp_buffer_status_reg_rx_buffer_full_set( - a_uint32_t dev_id, a_uint32_t phy_id, - unsigned int value); - -sw_error_t -qca808x_ptp_buffer_status_reg_rx_buffer_data_present_get( - a_uint32_t dev_id, a_uint32_t phy_id, - unsigned int *value); - -sw_error_t -qca808x_ptp_buffer_status_reg_rx_buffer_data_present_set( - a_uint32_t dev_id, a_uint32_t phy_id, - unsigned int value); - -sw_error_t -qca808x_ptp_tx_buffer_write_reg_tx_buffer_get( - a_uint32_t dev_id, a_uint32_t phy_id, - unsigned int *value); - -sw_error_t -qca808x_ptp_tx_buffer_write_reg_tx_buffer_set( - a_uint32_t dev_id, a_uint32_t phy_id, - unsigned int value); - -sw_error_t -qca808x_ptp_rx_buffer_read_reg_rx_data_get( - a_uint32_t dev_id, a_uint32_t phy_id, - unsigned int *value); - -sw_error_t -qca808x_ptp_rx_buffer_read_reg_rx_data_set( - a_uint32_t dev_id, a_uint32_t phy_id, - unsigned int value); - -sw_error_t -qca808x_ptp_rx_buffer_read_reg_rx_buffer_almost_empty_get( - a_uint32_t dev_id, a_uint32_t phy_id, - unsigned int *value); - -sw_error_t -qca808x_ptp_rx_buffer_read_reg_rx_buffer_almost_empty_set( - a_uint32_t dev_id, a_uint32_t phy_id, - unsigned int value); - -sw_error_t -qca808x_ptp_rx_buffer_read_reg_rx_buffer_almost_full_get( - a_uint32_t dev_id, a_uint32_t phy_id, - unsigned int *value); - -sw_error_t -qca808x_ptp_rx_buffer_read_reg_rx_buffer_almost_full_set( - a_uint32_t dev_id, a_uint32_t phy_id, - unsigned int value); - -sw_error_t -qca808x_ptp_rx_buffer_read_reg_rx_buffer_half_full_get( - a_uint32_t dev_id, a_uint32_t phy_id, - unsigned int *value); - -sw_error_t -qca808x_ptp_rx_buffer_read_reg_rx_buffer_half_full_set( - a_uint32_t dev_id, a_uint32_t phy_id, - unsigned int value); - -sw_error_t -qca808x_ptp_rx_buffer_read_reg_rx_buffer_full_get( - a_uint32_t dev_id, a_uint32_t phy_id, - unsigned int *value); - -sw_error_t -qca808x_ptp_rx_buffer_read_reg_rx_buffer_full_set( - a_uint32_t dev_id, a_uint32_t phy_id, - unsigned int value); - -sw_error_t -qca808x_ptp_rx_buffer_read_reg_rx_buffer_data_present_get( - a_uint32_t dev_id, a_uint32_t phy_id, - unsigned int *value); - -sw_error_t -qca808x_ptp_rx_buffer_read_reg_rx_buffer_data_present_set( - a_uint32_t dev_id, a_uint32_t phy_id, - unsigned int value); - -sw_error_t -qca808x_ptp_loc_mac_addr_0_reg_get( - a_uint32_t dev_id, a_uint32_t phy_id, - union ptp_loc_mac_addr_0_reg_u *value); - -sw_error_t -qca808x_ptp_loc_mac_addr_0_reg_set( - a_uint32_t dev_id, a_uint32_t phy_id, - union ptp_loc_mac_addr_0_reg_u *value); - -sw_error_t -qca808x_ptp_loc_mac_addr_1_reg_get( - a_uint32_t dev_id, a_uint32_t phy_id, - union ptp_loc_mac_addr_1_reg_u *value); - -sw_error_t -qca808x_ptp_loc_mac_addr_1_reg_set( - a_uint32_t dev_id, a_uint32_t phy_id, - union ptp_loc_mac_addr_1_reg_u *value); - -sw_error_t -qca808x_ptp_loc_mac_addr_2_reg_get( - a_uint32_t dev_id, a_uint32_t phy_id, - union ptp_loc_mac_addr_2_reg_u *value); - -sw_error_t -qca808x_ptp_loc_mac_addr_2_reg_set( - a_uint32_t dev_id, a_uint32_t phy_id, - union ptp_loc_mac_addr_2_reg_u *value); - -sw_error_t -qca808x_ptp_loc_mac_addr_0_reg_mac_addr_get( - a_uint32_t dev_id, a_uint32_t phy_id, - unsigned int *value); - -sw_error_t -qca808x_ptp_loc_mac_addr_0_reg_mac_addr_set( - a_uint32_t dev_id, a_uint32_t phy_id, - unsigned int value); - -sw_error_t -qca808x_ptp_loc_mac_addr_1_reg_mac_addr_get( - a_uint32_t dev_id, a_uint32_t phy_id, - unsigned int *value); - -sw_error_t -qca808x_ptp_loc_mac_addr_1_reg_mac_addr_set( - a_uint32_t dev_id, a_uint32_t phy_id, - unsigned int value); - -sw_error_t -qca808x_ptp_loc_mac_addr_2_reg_mac_addr_get( - a_uint32_t dev_id, a_uint32_t phy_id, - unsigned int *value); - -sw_error_t -qca808x_ptp_loc_mac_addr_2_reg_mac_addr_set( - a_uint32_t dev_id, a_uint32_t phy_id, - unsigned int value); - -sw_error_t -qca808x_ptp_link_delay_0_reg_get( - a_uint32_t dev_id, a_uint32_t phy_id, - union ptp_link_delay_0_reg_u *value); - -sw_error_t -qca808x_ptp_link_delay_0_reg_set( - a_uint32_t dev_id, a_uint32_t phy_id, - union ptp_link_delay_0_reg_u *value); - -sw_error_t -qca808x_ptp_link_delay_1_reg_get( - a_uint32_t dev_id, a_uint32_t phy_id, - union ptp_link_delay_1_reg_u *value); - -sw_error_t -qca808x_ptp_link_delay_1_reg_set( - a_uint32_t dev_id, a_uint32_t phy_id, - union ptp_link_delay_1_reg_u *value); - -sw_error_t -qca808x_ptp_link_delay_0_reg_link_delay_get( - a_uint32_t dev_id, a_uint32_t phy_id, - unsigned int *value); - -sw_error_t -qca808x_ptp_link_delay_0_reg_link_delay_set( - a_uint32_t dev_id, a_uint32_t phy_id, - unsigned int value); - -sw_error_t -qca808x_ptp_link_delay_1_reg_link_delay_get( - a_uint32_t dev_id, a_uint32_t phy_id, - unsigned int *value); - -sw_error_t -qca808x_ptp_link_delay_1_reg_link_delay_set( - a_uint32_t dev_id, a_uint32_t phy_id, - unsigned int value); - -sw_error_t -qca808x_ptp_misc_control_reg_get( - a_uint32_t dev_id, a_uint32_t phy_id, - union ptp_misc_control_reg_u *value); - -sw_error_t -qca808x_ptp_misc_control_reg_set( - a_uint32_t dev_id, a_uint32_t phy_id, - union ptp_misc_control_reg_u *value); - -sw_error_t -qca808x_ptp_ingress_asymmetry_0_reg_get( - a_uint32_t dev_id, a_uint32_t phy_id, - union ptp_ingress_asymmetry_0_reg_u *value); - -sw_error_t -qca808x_ptp_ingress_asymmetry_0_reg_set( - a_uint32_t dev_id, a_uint32_t phy_id, - union ptp_ingress_asymmetry_0_reg_u *value); - -sw_error_t -qca808x_ptp_ingress_asymmetry_1_reg_get( - a_uint32_t dev_id, a_uint32_t phy_id, - union ptp_ingress_asymmetry_1_reg_u *value); - -sw_error_t -qca808x_ptp_ingress_asymmetry_1_reg_set( - a_uint32_t dev_id, a_uint32_t phy_id, - union ptp_ingress_asymmetry_1_reg_u *value); - -sw_error_t -qca808x_ptp_egress_asymmetry_0_reg_get( - a_uint32_t dev_id, a_uint32_t phy_id, - union ptp_egress_asymmetry_0_reg_u *value); - -sw_error_t -qca808x_ptp_egress_asymmetry_0_reg_set( - a_uint32_t dev_id, a_uint32_t phy_id, - union ptp_egress_asymmetry_0_reg_u *value); - -sw_error_t -qca808x_ptp_egress_asymmetry_1_reg_get( - a_uint32_t dev_id, a_uint32_t phy_id, - union ptp_egress_asymmetry_1_reg_u *value); - -sw_error_t -qca808x_ptp_egress_asymmetry_1_reg_set( - a_uint32_t dev_id, a_uint32_t phy_id, - union ptp_egress_asymmetry_1_reg_u *value); - -sw_error_t -qca808x_ptp_backup_reg_get( - a_uint32_t dev_id, a_uint32_t phy_id, - union ptp_backup_reg_u *value); - -sw_error_t -qca808x_ptp_backup_reg_set( - a_uint32_t dev_id, a_uint32_t phy_id, - union ptp_backup_reg_u *value); - -#endif - diff --git a/feeds/ipq807x/qca-ssdk/src/include/hsl/phy/qca808x_ptp_reg.h b/feeds/ipq807x/qca-ssdk/src/include/hsl/phy/qca808x_ptp_reg.h deleted file mode 100755 index 4e8c4c0a4..000000000 --- a/feeds/ipq807x/qca-ssdk/src/include/hsl/phy/qca808x_ptp_reg.h +++ /dev/null @@ -1,5853 +0,0 @@ -/* - * Copyright (c) 2018, The Linux Foundation. All rights reserved. - * Permission to use, copy, modify, and/or distribute this software for - * any purpose with or without fee is hereby granted, provided that the - * above copyright notice and this permission notice appear in all copies. - * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES - * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR - * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES - * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN - * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT - * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. - */ - - -/** - * @defgroup - * @{ - */ -#ifndef PTP_REG_REG_H -#define PTP_REG_REG_H - -#define PTP_REG_BIT_FALSE 0 -#define PTP_REG_BIT_TRUE 1 - -/*[register] PTP_IMR_REG*/ -#define PTP_IMR_REG -#define PTP_IMR_REG_ADDRESS 0x12 -#define PTP_IMR_REG_NUM 1 -#define PTP_IMR_REG_INC 0x1 -#define PTP_IMR_REG_TYPE REG_TYPE_RW -#define PTP_IMR_REG_DEFAULT 0x0 - /*[field] MASK_BMP*/ - #define PTP_IMR_REG_MASK_BMP - #define PTP_IMR_REG_MASK_BMP_OFFSET 0 - #define PTP_IMR_REG_MASK_BMP_LEN 16 - #define PTP_IMR_REG_MASK_BMP_DEFAULT 0x0 - -struct ptp_imr_reg { - a_uint16_t mask_bmp:16; -}; - -union ptp_imr_reg_u { - a_uint32_t val; - struct ptp_imr_reg bf; -}; - -/*[register] PTP_ISR_REG*/ -#define PTP_ISR_REG -#define PTP_ISR_REG_ADDRESS 0x13 -#define PTP_ISR_REG_NUM 1 -#define PTP_ISR_REG_INC 0x1 -#define PTP_ISR_REG_TYPE REG_TYPE_RW -#define PTP_ISR_REG_DEFAULT 0x0 - /*[field] STATUS_BMP*/ - #define PTP_ISR_REG_STATUS_BMP - #define PTP_ISR_REG_STATUS_BMP_OFFSET 0 - #define PTP_ISR_REG_STATUS_BMP_LEN 16 - #define PTP_ISR_REG_STATUS_BMP_DEFAULT 0x0 - -struct ptp_isr_reg { - a_uint16_t status_bmp:16; -}; - -union ptp_isr_reg_u { - a_uint32_t val; - struct ptp_isr_reg bf; -}; - -/*[register] PTP_HW_ENABLE_REG*/ -#define PTP_HW_ENABLE_REG -#define PTP_HW_ENABLE_REG_ADDRESS 0x1f -#define PTP_HW_ENABLE_REG_NUM 1 -#define PTP_HW_ENABLE_REG_INC 0x1 -#define PTP_HW_ENABLE_REG_TYPE REG_TYPE_RW -#define PTP_HW_ENABLE_REG_DEFAULT 0x0 - /*[field] PTP_HW_ENABLE*/ - #define PTP_HW_ENABLE_REG_PTP_HW_ENABLE - #define PTP_HW_ENABLE_REG_PTP_HW_ENABLE_OFFSET 1 - #define PTP_HW_ENABLE_REG_PTP_HW_ENABLE_LEN 1 - #define PTP_HW_ENABLE_REG_PTP_HW_ENABLE_DEFAULT 0x0 - -struct ptp_hw_enable_reg { - a_uint16_t _reserved0:1; - a_uint16_t ptp_hw_enable:1; -}; - -union ptp_hw_enable_reg_u { - a_uint32_t val; - struct ptp_hw_enable_reg bf; -}; - -/*[register] PTP_MAIN_CONF_REG*/ -#define PTP_MAIN_CONF_REG -#define PTP_MAIN_CONF_REG_ADDRESS 0x8012 -#define PTP_MAIN_CONF_REG_NUM 1 -#define PTP_MAIN_CONF_REG_INC 0x1 -#define PTP_MAIN_CONF_REG_TYPE REG_TYPE_RW -#define PTP_MAIN_CONF_REG_DEFAULT 0x0 - /*[field] PTP_CLOCK_MODE*/ - #define PTP_MAIN_CONF_REG_PTP_CLOCK_MODE - #define PTP_MAIN_CONF_REG_PTP_CLOCK_MODE_OFFSET 1 - #define PTP_MAIN_CONF_REG_PTP_CLOCK_MODE_LEN 2 - #define PTP_MAIN_CONF_REG_PTP_CLOCK_MODE_DEFAULT 0x0 - #define PTP_MAIN_CONF_REG_PTP_CLOCK_MODE_OC_TWO_STEP 0x0 - #define PTP_MAIN_CONF_REG_PTP_CLOCK_MODE_OC_ONE_STEP 0x1 - #define PTP_MAIN_CONF_REG_PTP_CLOCK_MODE_TC_TWO_STEP 0x2 - #define PTP_MAIN_CONF_REG_PTP_CLOCK_MODE_TC_ONE_STEP 0x3 - /*[field] PTP_BYPASS*/ - #define PTP_MAIN_CONF_REG_PTP_BYPASS - #define PTP_MAIN_CONF_REG_PTP_BYPASS_OFFSET 3 - #define PTP_MAIN_CONF_REG_PTP_BYPASS_LEN 1 - #define PTP_MAIN_CONF_REG_PTP_BYPASS_DEFAULT 0x0 - /*[field] TS_ATTACH_MODE*/ - #define PTP_MAIN_CONF_REG_TS_ATTACH_MODE - #define PTP_MAIN_CONF_REG_TS_ATTACH_MODE_OFFSET 4 - #define PTP_MAIN_CONF_REG_TS_ATTACH_MODE_LEN 1 - #define PTP_MAIN_CONF_REG_TS_ATTACH_MODE_DEFAULT 0x0 - /*[field] WOL_EN*/ - #define PTP_MAIN_CONF_REG_WOL_EN - #define PTP_MAIN_CONF_REG_WOL_EN_OFFSET 5 - #define PTP_MAIN_CONF_REG_WOL_EN_LEN 1 - #define PTP_MAIN_CONF_REG_WOL_EN_DEFAULT 0x0 - /*[field] PTP_CLK_SEL*/ - #define PTP_MAIN_CONF_REG_PTP_CLK_SEL - #define PTP_MAIN_CONF_REG_PTP_CLK_SEL_OFFSET 7 - #define PTP_MAIN_CONF_REG_PTP_CLK_SEL_LEN 1 - #define PTP_MAIN_CONF_REG_PTP_CLK_SEL_DEFAULT 0x0 - /*[field] DISABLE_1588_PHY*/ - #define PTP_MAIN_CONF_REG_DISABLE_1588_PHY - #define PTP_MAIN_CONF_REG_DISABLE_1588_PHY_OFFSET 8 - #define PTP_MAIN_CONF_REG_DISABLE_1588_PHY_LEN 1 - #define PTP_MAIN_CONF_REG_DISABLE_1588_PHY_DEFAULT 0x0 - /*[field] ATTACH_CRC_RECAL*/ - #define PTP_MAIN_CONF_REG_ATTACH_CRC_RECAL - #define PTP_MAIN_CONF_REG_ATTACH_CRC_RECAL_OFFSET 9 - #define PTP_MAIN_CONF_REG_ATTACH_CRC_RECAL_LEN 1 - #define PTP_MAIN_CONF_REG_ATTACH_CRC_RECAL_DEFAULT 0x0 - /*[field] IPV4_FORCE_CHECKSUM_ZERO*/ - #define PTP_MAIN_CONF_REG_IPV4_FORCE_CHECKSUM_ZERO - #define PTP_MAIN_CONF_REG_IPV4_FORCE_CHECKSUM_ZERO_OFFSET 10 - #define PTP_MAIN_CONF_REG_IPV4_FORCE_CHECKSUM_ZERO_LEN 1 - #define PTP_MAIN_CONF_REG_IPV4_FORCE_CHECKSUM_ZERO_DEFAULT 0x1 - /*[field] IPV6_EMBED_FORCE_CHECKSUM_ZERO*/ - #define PTP_MAIN_CONF_REG_IPV6_EMBED_FORCE_CHECKSUM_ZERO - #define PTP_MAIN_CONF_REG_IPV6_EMBED_FORCE_CHECKSUM_ZERO_OFFSET 11 - #define PTP_MAIN_CONF_REG_IPV6_EMBED_FORCE_CHECKSUM_ZERO_LEN 1 - #define PTP_MAIN_CONF_REG_IPV6_EMBED_FORCE_CHECKSUM_ZERO_DEFAULT 0x0 - -struct ptp_main_conf_reg { - a_uint16_t _reserved0:1; - a_uint16_t ptp_clock_mode:2; - a_uint16_t ptp_bypass:1; - a_uint16_t ts_attach_mode:1; - a_uint16_t wol_en:1; - a_uint16_t _reserved1:1; - a_uint16_t ptp_clk_sel:1; - a_uint16_t disable_1588_phy:1; - a_uint16_t attach_crc_recal:1; - a_uint16_t ipv4_force_checksum_zero:1; - a_uint16_t ipv6_embed_force_checksum_zero:1; -}; - -union ptp_main_conf_reg_u { - a_uint32_t val; - struct ptp_main_conf_reg bf; -}; - -/*[register] PTP_RX_SEQID0_REG*/ -#define PTP_RX_SEQID0_REG -#define PTP_RX_SEQID0_REG_ADDRESS 0x8013 -#define PTP_RX_SEQID0_REG_NUM 1 -#define PTP_RX_SEQID0_REG_INC 0x1 -#define PTP_RX_SEQID0_REG_TYPE REG_TYPE_RW -#define PTP_RX_SEQID0_REG_DEFAULT 0x0 - /*[field] RX_SEQID*/ - #define PTP_RX_SEQID0_REG_RX_SEQID - #define PTP_RX_SEQID0_REG_RX_SEQID_OFFSET 0 - #define PTP_RX_SEQID0_REG_RX_SEQID_LEN 16 - #define PTP_RX_SEQID0_REG_RX_SEQID_DEFAULT 0x0 - -struct ptp_rx_seqid0_reg { - a_uint16_t rx_seqid:16; -}; - -union ptp_rx_seqid0_reg_u { - a_uint32_t val; - struct ptp_rx_seqid0_reg bf; -}; - -/*[register] PTP_RX_PORTID0_0_REG*/ -#define PTP_RX_PORTID0_0_REG -#define PTP_RX_PORTID0_0_REG_ADDRESS 0x8014 -#define PTP_RX_PORTID0_0_REG_NUM 1 -#define PTP_RX_PORTID0_0_REG_INC 0x1 -#define PTP_RX_PORTID0_0_REG_TYPE REG_TYPE_RW -#define PTP_RX_PORTID0_0_REG_DEFAULT 0x0 - /*[field] RX_PORTID*/ - #define PTP_RX_PORTID0_0_REG_RX_PORTID - #define PTP_RX_PORTID0_0_REG_RX_PORTID_OFFSET 0 - #define PTP_RX_PORTID0_0_REG_RX_PORTID_LEN 16 - #define PTP_RX_PORTID0_0_REG_RX_PORTID_DEFAULT 0x0 - -struct ptp_rx_portid0_0_reg { - a_uint16_t rx_portid:16; -}; - -union ptp_rx_portid0_0_reg_u { - a_uint32_t val; - struct ptp_rx_portid0_0_reg bf; -}; - -/*[register] PTP_RX_PORTID0_1_REG*/ -#define PTP_RX_PORTID0_1_REG -#define PTP_RX_PORTID0_1_REG_ADDRESS 0x8015 -#define PTP_RX_PORTID0_1_REG_NUM 1 -#define PTP_RX_PORTID0_1_REG_INC 0x1 -#define PTP_RX_PORTID0_1_REG_TYPE REG_TYPE_RW -#define PTP_RX_PORTID0_1_REG_DEFAULT 0x0 - /*[field] RX_PORTID*/ - #define PTP_RX_PORTID0_1_REG_RX_PORTID - #define PTP_RX_PORTID0_1_REG_RX_PORTID_OFFSET 0 - #define PTP_RX_PORTID0_1_REG_RX_PORTID_LEN 16 - #define PTP_RX_PORTID0_1_REG_RX_PORTID_DEFAULT 0x0 - -struct ptp_rx_portid0_1_reg { - a_uint16_t rx_portid:16; -}; - -union ptp_rx_portid0_1_reg_u { - a_uint32_t val; - struct ptp_rx_portid0_1_reg bf; -}; - -/*[register] PTP_RX_PORTID0_2_REG*/ -#define PTP_RX_PORTID0_2_REG -#define PTP_RX_PORTID0_2_REG_ADDRESS 0x8016 -#define PTP_RX_PORTID0_2_REG_NUM 1 -#define PTP_RX_PORTID0_2_REG_INC 0x1 -#define PTP_RX_PORTID0_2_REG_TYPE REG_TYPE_RW -#define PTP_RX_PORTID0_2_REG_DEFAULT 0x0 - /*[field] RX_PORTID*/ - #define PTP_RX_PORTID0_2_REG_RX_PORTID - #define PTP_RX_PORTID0_2_REG_RX_PORTID_OFFSET 0 - #define PTP_RX_PORTID0_2_REG_RX_PORTID_LEN 16 - #define PTP_RX_PORTID0_2_REG_RX_PORTID_DEFAULT 0x0 - -struct ptp_rx_portid0_2_reg { - a_uint16_t rx_portid:16; -}; - -union ptp_rx_portid0_2_reg_u { - a_uint32_t val; - struct ptp_rx_portid0_2_reg bf; -}; - -/*[register] PTP_RX_PORTID0_3_REG*/ -#define PTP_RX_PORTID0_3_REG -#define PTP_RX_PORTID0_3_REG_ADDRESS 0x8017 -#define PTP_RX_PORTID0_3_REG_NUM 1 -#define PTP_RX_PORTID0_3_REG_INC 0x1 -#define PTP_RX_PORTID0_3_REG_TYPE REG_TYPE_RW -#define PTP_RX_PORTID0_3_REG_DEFAULT 0x0 - /*[field] RX_PORTID*/ - #define PTP_RX_PORTID0_3_REG_RX_PORTID - #define PTP_RX_PORTID0_3_REG_RX_PORTID_OFFSET 0 - #define PTP_RX_PORTID0_3_REG_RX_PORTID_LEN 16 - #define PTP_RX_PORTID0_3_REG_RX_PORTID_DEFAULT 0x0 - -struct ptp_rx_portid0_3_reg { - a_uint16_t rx_portid:16; -}; - -union ptp_rx_portid0_3_reg_u { - a_uint32_t val; - struct ptp_rx_portid0_3_reg bf; -}; - -/*[register] PTP_RX_PORTID0_4_REG*/ -#define PTP_RX_PORTID0_4_REG -#define PTP_RX_PORTID0_4_REG_ADDRESS 0x8018 -#define PTP_RX_PORTID0_4_REG_NUM 1 -#define PTP_RX_PORTID0_4_REG_INC 0x1 -#define PTP_RX_PORTID0_4_REG_TYPE REG_TYPE_RW -#define PTP_RX_PORTID0_4_REG_DEFAULT 0x0 - /*[field] RX_PORTID*/ - #define PTP_RX_PORTID0_4_REG_RX_PORTID - #define PTP_RX_PORTID0_4_REG_RX_PORTID_OFFSET 0 - #define PTP_RX_PORTID0_4_REG_RX_PORTID_LEN 16 - #define PTP_RX_PORTID0_4_REG_RX_PORTID_DEFAULT 0x0 - -struct ptp_rx_portid0_4_reg { - a_uint16_t rx_portid:16; -}; - -union ptp_rx_portid0_4_reg_u { - a_uint32_t val; - struct ptp_rx_portid0_4_reg bf; -}; - - -// -/*[register] PTP_RTC_CLK_REG*/ -#define PTP_RTC_CLK_REG -#define PTP_RTC_CLK_REG_ADDRESS 0x8017 -#define PTP_RTC_CLK_REG_NUM 1 -#define PTP_RTC_CLK_REG_INC 0x1 -#define PTP_RTC_CLK_REG_TYPE REG_TYPE_RW -#define PTP_RTC_CLK_REG_DEFAULT 0x0 - /*[field] RTC_CLK_SELECTION*/ - #define PTP_RTC_CLK_REG_RTC_CLK_SELECTION - #define PTP_RTC_CLK_REG_RTC_CLK_SELECTION_OFFSET 11 - #define PTP_RTC_CLK_REG_RTC_CLK_SELECTION_LEN 1 - #define PTP_RTC_CLK_REG_RTC_CLK_SELECTION_DEFAULT 0x0 - -struct ptp_rtc_clk_reg { - a_uint16_t _reserved0:11; - a_uint16_t rtc_clk_selection:1; -}; - -union ptp_rtc_clk_reg_u { - a_uint32_t val; - struct ptp_rtc_clk_reg bf; -}; - -/*[register] PTP_RX_TS0_0_REG*/ -#define PTP_RX_TS0_0_REG -#define PTP_RX_TS0_0_REG_ADDRESS 0x8019 -#define PTP_RX_TS0_0_REG_NUM 1 -#define PTP_RX_TS0_0_REG_INC 0x1 -#define PTP_RX_TS0_0_REG_TYPE REG_TYPE_RW -#define PTP_RX_TS0_0_REG_DEFAULT 0x0 - /*[field] RX_TS_SEC*/ - #define PTP_RX_TS0_0_REG_RX_TS_SEC - #define PTP_RX_TS0_0_REG_RX_TS_SEC_OFFSET 0 - #define PTP_RX_TS0_0_REG_RX_TS_SEC_LEN 16 - #define PTP_RX_TS0_0_REG_RX_TS_SEC_DEFAULT 0x0 - -struct ptp_rx_ts0_0_reg { - a_uint16_t rx_ts_sec:16; -}; - -union ptp_rx_ts0_0_reg_u { - a_uint32_t val; - struct ptp_rx_ts0_0_reg bf; -}; - -/*[register] PTP_RX_TS0_1_REG*/ -#define PTP_RX_TS0_1_REG -#define PTP_RX_TS0_1_REG_ADDRESS 0x801a -#define PTP_RX_TS0_1_REG_NUM 1 -#define PTP_RX_TS0_1_REG_INC 0x1 -#define PTP_RX_TS0_1_REG_TYPE REG_TYPE_RW -#define PTP_RX_TS0_1_REG_DEFAULT 0x0 - /*[field] RX_TS_SEC*/ - #define PTP_RX_TS0_1_REG_RX_TS_SEC - #define PTP_RX_TS0_1_REG_RX_TS_SEC_OFFSET 0 - #define PTP_RX_TS0_1_REG_RX_TS_SEC_LEN 16 - #define PTP_RX_TS0_1_REG_RX_TS_SEC_DEFAULT 0x0 - -struct ptp_rx_ts0_1_reg { - a_uint16_t rx_ts_sec:16; -}; - -union ptp_rx_ts0_1_reg_u { - a_uint32_t val; - struct ptp_rx_ts0_1_reg bf; -}; - -/*[register] PTP_RX_TS0_2_REG*/ -#define PTP_RX_TS0_2_REG -#define PTP_RX_TS0_2_REG_ADDRESS 0x801b -#define PTP_RX_TS0_2_REG_NUM 1 -#define PTP_RX_TS0_2_REG_INC 0x1 -#define PTP_RX_TS0_2_REG_TYPE REG_TYPE_RW -#define PTP_RX_TS0_2_REG_DEFAULT 0x0 - /*[field] RX_TS_SEC*/ - #define PTP_RX_TS0_2_REG_RX_TS_SEC - #define PTP_RX_TS0_2_REG_RX_TS_SEC_OFFSET 0 - #define PTP_RX_TS0_2_REG_RX_TS_SEC_LEN 16 - #define PTP_RX_TS0_2_REG_RX_TS_SEC_DEFAULT 0x0 - -struct ptp_rx_ts0_2_reg { - a_uint16_t rx_ts_sec:16; -}; - -union ptp_rx_ts0_2_reg_u { - a_uint32_t val; - struct ptp_rx_ts0_2_reg bf; -}; - -/*[register] PTP_RX_TS0_3_REG*/ -#define PTP_RX_TS0_3_REG -#define PTP_RX_TS0_3_REG_ADDRESS 0x801c -#define PTP_RX_TS0_3_REG_NUM 1 -#define PTP_RX_TS0_3_REG_INC 0x1 -#define PTP_RX_TS0_3_REG_TYPE REG_TYPE_RW -#define PTP_RX_TS0_3_REG_DEFAULT 0x0 - /*[field] RX_TS_NSEC*/ - #define PTP_RX_TS0_3_REG_RX_TS_NSEC - #define PTP_RX_TS0_3_REG_RX_TS_NSEC_OFFSET 0 - #define PTP_RX_TS0_3_REG_RX_TS_NSEC_LEN 16 - #define PTP_RX_TS0_3_REG_RX_TS_NSEC_DEFAULT 0x0 - -struct ptp_rx_ts0_3_reg { - a_uint16_t rx_ts_nsec:16; -}; - -union ptp_rx_ts0_3_reg_u { - a_uint32_t val; - struct ptp_rx_ts0_3_reg bf; -}; - -/*[register] PTP_RX_TS0_4_REG*/ -#define PTP_RX_TS0_4_REG -#define PTP_RX_TS0_4_REG_ADDRESS 0x801d -#define PTP_RX_TS0_4_REG_NUM 1 -#define PTP_RX_TS0_4_REG_INC 0x1 -#define PTP_RX_TS0_4_REG_TYPE REG_TYPE_RW -#define PTP_RX_TS0_4_REG_DEFAULT 0x0 - /*[field] RX_TS_NSEC*/ - #define PTP_RX_TS0_4_REG_RX_TS_NSEC - #define PTP_RX_TS0_4_REG_RX_TS_NSEC_OFFSET 0 - #define PTP_RX_TS0_4_REG_RX_TS_NSEC_LEN 16 - #define PTP_RX_TS0_4_REG_RX_TS_NSEC_DEFAULT 0x0 - -struct ptp_rx_ts0_4_reg { - a_uint16_t rx_ts_nsec:16; -}; - -union ptp_rx_ts0_4_reg_u { - a_uint32_t val; - struct ptp_rx_ts0_4_reg bf; -}; - -/*[register] PTP_RX_TS0_5_REG*/ -#define PTP_RX_TS0_5_REG -#define PTP_RX_TS0_5_REG_ADDRESS 0x801e -#define PTP_RX_TS0_5_REG_NUM 1 -#define PTP_RX_TS0_5_REG_INC 0x1 -#define PTP_RX_TS0_5_REG_TYPE REG_TYPE_RW -#define PTP_RX_TS0_5_REG_DEFAULT 0x0 - /*[field] RX_TS_NFSEC*/ - #define PTP_RX_TS0_5_REG_RX_TS_NFSEC - #define PTP_RX_TS0_5_REG_RX_TS_NFSEC_OFFSET 0 - #define PTP_RX_TS0_5_REG_RX_TS_NFSEC_LEN 12 - #define PTP_RX_TS0_5_REG_RX_TS_NFSEC_DEFAULT 0x0 - /*[field] RX_MSG_TYPE*/ - #define PTP_RX_TS0_5_REG_RX_MSG_TYPE - #define PTP_RX_TS0_5_REG_RX_MSG_TYPE_OFFSET 12 - #define PTP_RX_TS0_5_REG_RX_MSG_TYPE_LEN 4 - #define PTP_RX_TS0_5_REG_RX_MSG_TYPE_DEFAULT 0x0 - -struct ptp_rx_ts0_5_reg { - a_uint16_t rx_ts_nfsec:12; - a_uint16_t rx_msg_type:4; -}; - -union ptp_rx_ts0_5_reg_u { - a_uint32_t val; - struct ptp_rx_ts0_5_reg bf; -}; - -/*[register] PTP_RX_TS0_6_REG*/ -#define PTP_RX_TS0_6_REG -#define PTP_RX_TS0_6_REG_ADDRESS 0x801f -#define PTP_RX_TS0_6_REG_NUM 1 -#define PTP_RX_TS0_6_REG_INC 0x1 -#define PTP_RX_TS0_6_REG_TYPE REG_TYPE_RW -#define PTP_RX_TS0_6_REG_DEFAULT 0x0 - /*[field] RX_TS_NFSEC*/ - #define PTP_RX_TS0_6_REG_RX_TS_NFSEC - #define PTP_RX_TS0_6_REG_RX_TS_NFSEC_OFFSET 0 - #define PTP_RX_TS0_6_REG_RX_TS_NFSEC_LEN 8 - #define PTP_RX_TS0_6_REG_RX_TS_NFSEC_DEFAULT 0x0 - -struct ptp_rx_ts0_6_reg { - a_uint16_t rx_ts_nfsec:8; -}; - -union ptp_rx_ts0_6_reg_u { - a_uint32_t val; - struct ptp_rx_ts0_6_reg bf; -}; - -/*[register] PTP_TX_SEQID_REG*/ -#define PTP_TX_SEQID_REG -#define PTP_TX_SEQID_REG_ADDRESS 0x8020 -#define PTP_TX_SEQID_REG_NUM 1 -#define PTP_TX_SEQID_REG_INC 0x1 -#define PTP_TX_SEQID_REG_TYPE REG_TYPE_RW -#define PTP_TX_SEQID_REG_DEFAULT 0x0 - /*[field] TX_SEQID*/ - #define PTP_TX_SEQID_REG_TX_SEQID - #define PTP_TX_SEQID_REG_TX_SEQID_OFFSET 0 - #define PTP_TX_SEQID_REG_TX_SEQID_LEN 16 - #define PTP_TX_SEQID_REG_TX_SEQID_DEFAULT 0x0 - -struct ptp_tx_seqid_reg { - a_uint16_t tx_seqid:16; -}; - -union ptp_tx_seqid_reg_u { - a_uint32_t val; - struct ptp_tx_seqid_reg bf; -}; - -/*[register] PTP_TX_PORTID0_REG*/ -#define PTP_TX_PORTID0_REG -#define PTP_TX_PORTID0_REG_ADDRESS 0x8021 -#define PTP_TX_PORTID0_REG_NUM 1 -#define PTP_TX_PORTID0_REG_INC 0x1 -#define PTP_TX_PORTID0_REG_TYPE REG_TYPE_RW -#define PTP_TX_PORTID0_REG_DEFAULT 0x0 - /*[field] TX_PORTID*/ - #define PTP_TX_PORTID0_REG_TX_PORTID - #define PTP_TX_PORTID0_REG_TX_PORTID_OFFSET 0 - #define PTP_TX_PORTID0_REG_TX_PORTID_LEN 16 - #define PTP_TX_PORTID0_REG_TX_PORTID_DEFAULT 0x0 - -struct ptp_tx_portid0_reg { - a_uint16_t tx_portid:16; -}; - -union ptp_tx_portid0_reg_u { - a_uint32_t val; - struct ptp_tx_portid0_reg bf; -}; - -/*[register] PTP_TX_PORTID1_REG*/ -#define PTP_TX_PORTID1_REG -#define PTP_TX_PORTID1_REG_ADDRESS 0x8022 -#define PTP_TX_PORTID1_REG_NUM 1 -#define PTP_TX_PORTID1_REG_INC 0x1 -#define PTP_TX_PORTID1_REG_TYPE REG_TYPE_RW -#define PTP_TX_PORTID1_REG_DEFAULT 0x0 - /*[field] TX_PORTID*/ - #define PTP_TX_PORTID1_REG_TX_PORTID - #define PTP_TX_PORTID1_REG_TX_PORTID_OFFSET 0 - #define PTP_TX_PORTID1_REG_TX_PORTID_LEN 16 - #define PTP_TX_PORTID1_REG_TX_PORTID_DEFAULT 0x0 - -struct ptp_tx_portid1_reg { - a_uint16_t tx_portid:16; -}; - -union ptp_tx_portid1_reg_u { - a_uint32_t val; - struct ptp_tx_portid1_reg bf; -}; - -/*[register] PTP_TX_PORTID2_REG*/ -#define PTP_TX_PORTID2_REG -#define PTP_TX_PORTID2_REG_ADDRESS 0x8023 -#define PTP_TX_PORTID2_REG_NUM 1 -#define PTP_TX_PORTID2_REG_INC 0x1 -#define PTP_TX_PORTID2_REG_TYPE REG_TYPE_RW -#define PTP_TX_PORTID2_REG_DEFAULT 0x0 - /*[field] TX_PORTID*/ - #define PTP_TX_PORTID2_REG_TX_PORTID - #define PTP_TX_PORTID2_REG_TX_PORTID_OFFSET 0 - #define PTP_TX_PORTID2_REG_TX_PORTID_LEN 16 - #define PTP_TX_PORTID2_REG_TX_PORTID_DEFAULT 0x0 - -struct ptp_tx_portid2_reg { - a_uint16_t tx_portid:16; -}; - -union ptp_tx_portid2_reg_u { - a_uint32_t val; - struct ptp_tx_portid2_reg bf; -}; - -/*[register] PTP_TX_PORTID3_REG*/ -#define PTP_TX_PORTID3_REG -#define PTP_TX_PORTID3_REG_ADDRESS 0x8024 -#define PTP_TX_PORTID3_REG_NUM 1 -#define PTP_TX_PORTID3_REG_INC 0x1 -#define PTP_TX_PORTID3_REG_TYPE REG_TYPE_RW -#define PTP_TX_PORTID3_REG_DEFAULT 0x0 - /*[field] TX_PORTID*/ - #define PTP_TX_PORTID3_REG_TX_PORTID - #define PTP_TX_PORTID3_REG_TX_PORTID_OFFSET 0 - #define PTP_TX_PORTID3_REG_TX_PORTID_LEN 16 - #define PTP_TX_PORTID3_REG_TX_PORTID_DEFAULT 0x0 - -struct ptp_tx_portid3_reg { - a_uint16_t tx_portid:16; -}; - -union ptp_tx_portid3_reg_u { - a_uint32_t val; - struct ptp_tx_portid3_reg bf; -}; - -/*[register] PTP_TX_PORTID4_REG*/ -#define PTP_TX_PORTID4_REG -#define PTP_TX_PORTID4_REG_ADDRESS 0x8025 -#define PTP_TX_PORTID4_REG_NUM 1 -#define PTP_TX_PORTID4_REG_INC 0x1 -#define PTP_TX_PORTID4_REG_TYPE REG_TYPE_RW -#define PTP_TX_PORTID4_REG_DEFAULT 0x0 - /*[field] TX_PORTID*/ - #define PTP_TX_PORTID4_REG_TX_PORTID - #define PTP_TX_PORTID4_REG_TX_PORTID_OFFSET 0 - #define PTP_TX_PORTID4_REG_TX_PORTID_LEN 16 - #define PTP_TX_PORTID4_REG_TX_PORTID_DEFAULT 0x0 - -struct ptp_tx_portid4_reg { - a_uint16_t tx_portid:16; -}; - -union ptp_tx_portid4_reg_u { - a_uint32_t val; - struct ptp_tx_portid4_reg bf; -}; - -/*[register] PTP_TX_TS0_REG*/ -#define PTP_TX_TS0_REG -#define PTP_TX_TS0_REG_ADDRESS 0x8026 -#define PTP_TX_TS0_REG_NUM 1 -#define PTP_TX_TS0_REG_INC 0x1 -#define PTP_TX_TS0_REG_TYPE REG_TYPE_RW -#define PTP_TX_TS0_REG_DEFAULT 0x0 - /*[field] TX_TS_SEC*/ - #define PTP_TX_TS0_REG_TX_TS_SEC - #define PTP_TX_TS0_REG_TX_TS_SEC_OFFSET 0 - #define PTP_TX_TS0_REG_TX_TS_SEC_LEN 16 - #define PTP_TX_TS0_REG_TX_TS_SEC_DEFAULT 0x0 - -struct ptp_tx_ts0_reg { - a_uint16_t tx_ts_sec:16; -}; - -union ptp_tx_ts0_reg_u { - a_uint32_t val; - struct ptp_tx_ts0_reg bf; -}; - -/*[register] PTP_TX_TS1_REG*/ -#define PTP_TX_TS1_REG -#define PTP_TX_TS1_REG_ADDRESS 0x8027 -#define PTP_TX_TS1_REG_NUM 1 -#define PTP_TX_TS1_REG_INC 0x1 -#define PTP_TX_TS1_REG_TYPE REG_TYPE_RW -#define PTP_TX_TS1_REG_DEFAULT 0x0 - /*[field] TX_TS_SEC*/ - #define PTP_TX_TS1_REG_TX_TS_SEC - #define PTP_TX_TS1_REG_TX_TS_SEC_OFFSET 0 - #define PTP_TX_TS1_REG_TX_TS_SEC_LEN 16 - #define PTP_TX_TS1_REG_TX_TS_SEC_DEFAULT 0x0 - -struct ptp_tx_ts1_reg { - a_uint16_t tx_ts_sec:16; -}; - -union ptp_tx_ts1_reg_u { - a_uint32_t val; - struct ptp_tx_ts1_reg bf; -}; - -/*[register] PTP_TX_TS2_REG*/ -#define PTP_TX_TS2_REG -#define PTP_TX_TS2_REG_ADDRESS 0x8028 -#define PTP_TX_TS2_REG_NUM 1 -#define PTP_TX_TS2_REG_INC 0x1 -#define PTP_TX_TS2_REG_TYPE REG_TYPE_RW -#define PTP_TX_TS2_REG_DEFAULT 0x0 - /*[field] TX_TS_SEC*/ - #define PTP_TX_TS2_REG_TX_TS_SEC - #define PTP_TX_TS2_REG_TX_TS_SEC_OFFSET 0 - #define PTP_TX_TS2_REG_TX_TS_SEC_LEN 16 - #define PTP_TX_TS2_REG_TX_TS_SEC_DEFAULT 0x0 - -struct ptp_tx_ts2_reg { - a_uint16_t tx_ts_sec:16; -}; - -union ptp_tx_ts2_reg_u { - a_uint32_t val; - struct ptp_tx_ts2_reg bf; -}; - -/*[register] PTP_TX_TS3_REG*/ -#define PTP_TX_TS3_REG -#define PTP_TX_TS3_REG_ADDRESS 0x8029 -#define PTP_TX_TS3_REG_NUM 1 -#define PTP_TX_TS3_REG_INC 0x1 -#define PTP_TX_TS3_REG_TYPE REG_TYPE_RW -#define PTP_TX_TS3_REG_DEFAULT 0x0 - /*[field] TX_TS_NSEC*/ - #define PTP_TX_TS3_REG_TX_TS_NSEC - #define PTP_TX_TS3_REG_TX_TS_NSEC_OFFSET 0 - #define PTP_TX_TS3_REG_TX_TS_NSEC_LEN 16 - #define PTP_TX_TS3_REG_TX_TS_NSEC_DEFAULT 0x0 - -struct ptp_tx_ts3_reg { - a_uint16_t tx_ts_nsec:16; -}; - -union ptp_tx_ts3_reg_u { - a_uint32_t val; - struct ptp_tx_ts3_reg bf; -}; - -/*[register] PTP_TX_TS4_REG*/ -#define PTP_TX_TS4_REG -#define PTP_TX_TS4_REG_ADDRESS 0x802a -#define PTP_TX_TS4_REG_NUM 1 -#define PTP_TX_TS4_REG_INC 0x1 -#define PTP_TX_TS4_REG_TYPE REG_TYPE_RW -#define PTP_TX_TS4_REG_DEFAULT 0x0 - /*[field] TX_TS_NSEC*/ - #define PTP_TX_TS4_REG_TX_TS_NSEC - #define PTP_TX_TS4_REG_TX_TS_NSEC_OFFSET 0 - #define PTP_TX_TS4_REG_TX_TS_NSEC_LEN 16 - #define PTP_TX_TS4_REG_TX_TS_NSEC_DEFAULT 0x0 - -struct ptp_tx_ts4_reg { - a_uint16_t tx_ts_nsec:16; -}; - -union ptp_tx_ts4_reg_u { - a_uint32_t val; - struct ptp_tx_ts4_reg bf; -}; - -/*[register] PTP_TX_TS5_REG*/ -#define PTP_TX_TS5_REG -#define PTP_TX_TS5_REG_ADDRESS 0x802b -#define PTP_TX_TS5_REG_NUM 1 -#define PTP_TX_TS5_REG_INC 0x1 -#define PTP_TX_TS5_REG_TYPE REG_TYPE_RW -#define PTP_TX_TS5_REG_DEFAULT 0x0 - /*[field] TX_TS_NFSEC*/ - #define PTP_TX_TS5_REG_TX_TS_NFSEC - #define PTP_TX_TS5_REG_TX_TS_NFSEC_OFFSET 0 - #define PTP_TX_TS5_REG_TX_TS_NFSEC_LEN 12 - #define PTP_TX_TS5_REG_TX_TS_NFSEC_DEFAULT 0x0 - /*[field] TX_MSG_TYPE*/ - #define PTP_TX_TS5_REG_TX_MSG_TYPE - #define PTP_TX_TS5_REG_TX_MSG_TYPE_OFFSET 12 - #define PTP_TX_TS5_REG_TX_MSG_TYPE_LEN 4 - #define PTP_TX_TS5_REG_TX_MSG_TYPE_DEFAULT 0x0 - -struct ptp_tx_ts5_reg { - a_uint16_t tx_ts_nfsec:12; - a_uint16_t tx_msg_type:4; -}; - -union ptp_tx_ts5_reg_u { - a_uint32_t val; - struct ptp_tx_ts5_reg bf; -}; - -/*[register] PTP_TX_TS6_REG*/ -#define PTP_TX_TS6_REG -#define PTP_TX_TS6_REG_ADDRESS 0x802c -#define PTP_TX_TS6_REG_NUM 1 -#define PTP_TX_TS6_REG_INC 0x1 -#define PTP_TX_TS6_REG_TYPE REG_TYPE_RW -#define PTP_TX_TS6_REG_DEFAULT 0x0 - /*[field] TX_TS_NFSEC*/ - #define PTP_TX_TS6_REG_TX_TS_NFSEC - #define PTP_TX_TS6_REG_TX_TS_NFSEC_OFFSET 0 - #define PTP_TX_TS6_REG_TX_TS_NFSEC_LEN 8 - #define PTP_TX_TS6_REG_TX_TS_NFSEC_DEFAULT 0x0 - -struct ptp_tx_ts6_reg { - a_uint16_t tx_ts_nfsec:8; -}; - -union ptp_tx_ts6_reg_u { - a_uint32_t val; - struct ptp_tx_ts6_reg bf; -}; - -/*[register] PTP_ORIG_CORR0_REG*/ -#define PTP_ORIG_CORR0_REG -#define PTP_ORIG_CORR0_REG_ADDRESS 0x802d -#define PTP_ORIG_CORR0_REG_NUM 1 -#define PTP_ORIG_CORR0_REG_INC 0x1 -#define PTP_ORIG_CORR0_REG_TYPE REG_TYPE_RW -#define PTP_ORIG_CORR0_REG_DEFAULT 0x0 - /*[field] PTP_ORIG_CORR*/ - #define PTP_ORIG_CORR0_REG_PTP_ORIG_CORR - #define PTP_ORIG_CORR0_REG_PTP_ORIG_CORR_OFFSET 0 - #define PTP_ORIG_CORR0_REG_PTP_ORIG_CORR_LEN 16 - #define PTP_ORIG_CORR0_REG_PTP_ORIG_CORR_DEFAULT 0x0 - -struct ptp_orig_corr0_reg { - a_uint16_t ptp_orig_corr:16; -}; - -union ptp_orig_corr0_reg_u { - a_uint32_t val; - struct ptp_orig_corr0_reg bf; -}; - -/*[register] PTP_ORIG_CORR1_REG*/ -#define PTP_ORIG_CORR1_REG -#define PTP_ORIG_CORR1_REG_ADDRESS 0x802e -#define PTP_ORIG_CORR1_REG_NUM 1 -#define PTP_ORIG_CORR1_REG_INC 0x1 -#define PTP_ORIG_CORR1_REG_TYPE REG_TYPE_RW -#define PTP_ORIG_CORR1_REG_DEFAULT 0x0 - /*[field] PTP_ORIG_CORR*/ - #define PTP_ORIG_CORR1_REG_PTP_ORIG_CORR - #define PTP_ORIG_CORR1_REG_PTP_ORIG_CORR_OFFSET 0 - #define PTP_ORIG_CORR1_REG_PTP_ORIG_CORR_LEN 16 - #define PTP_ORIG_CORR1_REG_PTP_ORIG_CORR_DEFAULT 0x0 - -struct ptp_orig_corr1_reg { - a_uint16_t ptp_orig_corr:16; -}; - -union ptp_orig_corr1_reg_u { - a_uint32_t val; - struct ptp_orig_corr1_reg bf; -}; - -/*[register] PTP_ORIG_CORR2_REG*/ -#define PTP_ORIG_CORR2_REG -#define PTP_ORIG_CORR2_REG_ADDRESS 0x802f -#define PTP_ORIG_CORR2_REG_NUM 1 -#define PTP_ORIG_CORR2_REG_INC 0x1 -#define PTP_ORIG_CORR2_REG_TYPE REG_TYPE_RW -#define PTP_ORIG_CORR2_REG_DEFAULT 0x0 - /*[field] PTP_ORIG_CORR*/ - #define PTP_ORIG_CORR2_REG_PTP_ORIG_CORR - #define PTP_ORIG_CORR2_REG_PTP_ORIG_CORR_OFFSET 0 - #define PTP_ORIG_CORR2_REG_PTP_ORIG_CORR_LEN 16 - #define PTP_ORIG_CORR2_REG_PTP_ORIG_CORR_DEFAULT 0x0 - -struct ptp_orig_corr2_reg { - a_uint16_t ptp_orig_corr:16; -}; - -union ptp_orig_corr2_reg_u { - a_uint32_t val; - struct ptp_orig_corr2_reg bf; -}; - -/*[register] PTP_ORIG_CORR3_REG*/ -#define PTP_ORIG_CORR3_REG -#define PTP_ORIG_CORR3_REG_ADDRESS 0x8030 -#define PTP_ORIG_CORR3_REG_NUM 1 -#define PTP_ORIG_CORR3_REG_INC 0x1 -#define PTP_ORIG_CORR3_REG_TYPE REG_TYPE_RW -#define PTP_ORIG_CORR3_REG_DEFAULT 0x0 - /*[field] PTP_ORIG_CORR*/ - #define PTP_ORIG_CORR3_REG_PTP_ORIG_CORR - #define PTP_ORIG_CORR3_REG_PTP_ORIG_CORR_OFFSET 0 - #define PTP_ORIG_CORR3_REG_PTP_ORIG_CORR_LEN 16 - #define PTP_ORIG_CORR3_REG_PTP_ORIG_CORR_DEFAULT 0x0 - -struct ptp_orig_corr3_reg { - a_uint16_t ptp_orig_corr:16; -}; - -union ptp_orig_corr3_reg_u { - a_uint32_t val; - struct ptp_orig_corr3_reg bf; -}; - -/*[register] PTP_IN_TRIG0_REG*/ -#define PTP_IN_TRIG0_REG -#define PTP_IN_TRIG0_REG_ADDRESS 0x8031 -#define PTP_IN_TRIG0_REG_NUM 1 -#define PTP_IN_TRIG0_REG_INC 0x1 -#define PTP_IN_TRIG0_REG_TYPE REG_TYPE_RW -#define PTP_IN_TRIG0_REG_DEFAULT 0x0 - /*[field] PTP_IN_TRIG_NISEC*/ - #define PTP_IN_TRIG0_REG_PTP_IN_TRIG_NISEC - #define PTP_IN_TRIG0_REG_PTP_IN_TRIG_NISEC_OFFSET 0 - #define PTP_IN_TRIG0_REG_PTP_IN_TRIG_NISEC_LEN 16 - #define PTP_IN_TRIG0_REG_PTP_IN_TRIG_NISEC_DEFAULT 0x0 - -struct ptp_in_trig0_reg { - a_uint16_t ptp_in_trig_nisec:16; -}; - -union ptp_in_trig0_reg_u { - a_uint32_t val; - struct ptp_in_trig0_reg bf; -}; - -/*[register] PTP_IN_TRIG1_REG*/ -#define PTP_IN_TRIG1_REG -#define PTP_IN_TRIG1_REG_ADDRESS 0x8032 -#define PTP_IN_TRIG1_REG_NUM 1 -#define PTP_IN_TRIG1_REG_INC 0x1 -#define PTP_IN_TRIG1_REG_TYPE REG_TYPE_RW -#define PTP_IN_TRIG1_REG_DEFAULT 0x0 - /*[field] PTP_IN_TRIG_NISEC*/ - #define PTP_IN_TRIG1_REG_PTP_IN_TRIG_NISEC - #define PTP_IN_TRIG1_REG_PTP_IN_TRIG_NISEC_OFFSET 0 - #define PTP_IN_TRIG1_REG_PTP_IN_TRIG_NISEC_LEN 16 - #define PTP_IN_TRIG1_REG_PTP_IN_TRIG_NISEC_DEFAULT 0x0 - -struct ptp_in_trig1_reg { - a_uint16_t ptp_in_trig_nisec:16; -}; - -union ptp_in_trig1_reg_u { - a_uint32_t val; - struct ptp_in_trig1_reg bf; -}; - -/*[register] PTP_IN_TRIG2_REG*/ -#define PTP_IN_TRIG2_REG -#define PTP_IN_TRIG2_REG_ADDRESS 0x8033 -#define PTP_IN_TRIG2_REG_NUM 1 -#define PTP_IN_TRIG2_REG_INC 0x1 -#define PTP_IN_TRIG2_REG_TYPE REG_TYPE_RW -#define PTP_IN_TRIG2_REG_DEFAULT 0x0 - /*[field] PTP_IN_TRIG_NISEC*/ - #define PTP_IN_TRIG2_REG_PTP_IN_TRIG_NISEC - #define PTP_IN_TRIG2_REG_PTP_IN_TRIG_NISEC_OFFSET 0 - #define PTP_IN_TRIG2_REG_PTP_IN_TRIG_NISEC_LEN 16 - #define PTP_IN_TRIG2_REG_PTP_IN_TRIG_NISEC_DEFAULT 0x0 - -struct ptp_in_trig2_reg { - a_uint16_t ptp_in_trig_nisec:16; -}; - -union ptp_in_trig2_reg_u { - a_uint32_t val; - struct ptp_in_trig2_reg bf; -}; - -/*[register] PTP_IN_TRIG3_REG*/ -#define PTP_IN_TRIG3_REG -#define PTP_IN_TRIG3_REG_ADDRESS 0x8034 -#define PTP_IN_TRIG3_REG_NUM 1 -#define PTP_IN_TRIG3_REG_INC 0x1 -#define PTP_IN_TRIG3_REG_TYPE REG_TYPE_RW -#define PTP_IN_TRIG3_REG_DEFAULT 0x0 - /*[field] PTP_IN_TRIG_NISEC*/ - #define PTP_IN_TRIG3_REG_PTP_IN_TRIG_NISEC - #define PTP_IN_TRIG3_REG_PTP_IN_TRIG_NISEC_OFFSET 0 - #define PTP_IN_TRIG3_REG_PTP_IN_TRIG_NISEC_LEN 4 - #define PTP_IN_TRIG3_REG_PTP_IN_TRIG_NISEC_DEFAULT 0x0 - -struct ptp_in_trig3_reg { - a_uint16_t ptp_in_trig_nisec:4; -}; - -union ptp_in_trig3_reg_u { - a_uint32_t val; - struct ptp_in_trig3_reg bf; -}; - -/*[register] PTP_TX_LATENCY_REG*/ -#define PTP_TX_LATENCY_REG -#define PTP_TX_LATENCY_REG_ADDRESS 0x8035 -#define PTP_TX_LATENCY_REG_NUM 1 -#define PTP_TX_LATENCY_REG_INC 0x1 -#define PTP_TX_LATENCY_REG_TYPE REG_TYPE_RW -#define PTP_TX_LATENCY_REG_DEFAULT 0x0 - /*[field] PTP_TX_LATENCY*/ - #define PTP_TX_LATENCY_REG_PTP_TX_LATENCY - #define PTP_TX_LATENCY_REG_PTP_TX_LATENCY_OFFSET 0 - #define PTP_TX_LATENCY_REG_PTP_TX_LATENCY_LEN 16 - #define PTP_TX_LATENCY_REG_PTP_TX_LATENCY_DEFAULT 0x0 - -struct ptp_tx_latency_reg { - a_uint16_t ptp_tx_latency:16; -}; - -union ptp_tx_latency_reg_u { - a_uint32_t val; - struct ptp_tx_latency_reg bf; -}; - -/*[register] PTP_RTC_INC0_REG*/ -#define PTP_RTC_INC0_REG -#define PTP_RTC_INC0_REG_ADDRESS 0x8036 -#define PTP_RTC_INC0_REG_NUM 1 -#define PTP_RTC_INC0_REG_INC 0x1 -#define PTP_RTC_INC0_REG_TYPE REG_TYPE_RW -#define PTP_RTC_INC0_REG_DEFAULT 0x0 - /*[field] PTP_RTC_INC_NFS*/ - #define PTP_RTC_INC0_REG_PTP_RTC_INC_NFS - #define PTP_RTC_INC0_REG_PTP_RTC_INC_NFS_OFFSET 0 - #define PTP_RTC_INC0_REG_PTP_RTC_INC_NFS_LEN 10 - #define PTP_RTC_INC0_REG_PTP_RTC_INC_NFS_DEFAULT 0x0 - /*[field] PTP_RTC_INC_NIS*/ - #define PTP_RTC_INC0_REG_PTP_RTC_INC_NIS - #define PTP_RTC_INC0_REG_PTP_RTC_INC_NIS_OFFSET 10 - #define PTP_RTC_INC0_REG_PTP_RTC_INC_NIS_LEN 6 - #define PTP_RTC_INC0_REG_PTP_RTC_INC_NIS_DEFAULT 0x0 - -struct ptp_rtc_inc0_reg { - a_uint16_t ptp_rtc_inc_nfs:10; - a_uint16_t ptp_rtc_inc_nis:6; -}; - -union ptp_rtc_inc0_reg_u { - a_uint32_t val; - struct ptp_rtc_inc0_reg bf; -}; - -/*[register] PTP_RTC_INC1_REG*/ -#define PTP_RTC_INC1_REG -#define PTP_RTC_INC1_REG_ADDRESS 0x8037 -#define PTP_RTC_INC1_REG_NUM 1 -#define PTP_RTC_INC1_REG_INC 0x1 -#define PTP_RTC_INC1_REG_TYPE REG_TYPE_RW -#define PTP_RTC_INC1_REG_DEFAULT 0x0 - /*[field] PTP_RTC_INC_NFS*/ - #define PTP_RTC_INC1_REG_PTP_RTC_INC_NFS - #define PTP_RTC_INC1_REG_PTP_RTC_INC_NFS_OFFSET 0 - #define PTP_RTC_INC1_REG_PTP_RTC_INC_NFS_LEN 16 - #define PTP_RTC_INC1_REG_PTP_RTC_INC_NFS_DEFAULT 0x0 - -struct ptp_rtc_inc1_reg { - a_uint16_t ptp_rtc_inc_nfs:16; -}; - -union ptp_rtc_inc1_reg_u { - a_uint32_t val; - struct ptp_rtc_inc1_reg bf; -}; - -/*[register] PTP_RTCOFFS0_REG*/ -#define PTP_RTCOFFS0_REG -#define PTP_RTCOFFS0_REG_ADDRESS 0x8038 -#define PTP_RTCOFFS0_REG_NUM 1 -#define PTP_RTCOFFS0_REG_INC 0x1 -#define PTP_RTCOFFS0_REG_TYPE REG_TYPE_RW -#define PTP_RTCOFFS0_REG_DEFAULT 0x0 - /*[field] PTP_RTCOFFS_NSEC*/ - #define PTP_RTCOFFS0_REG_PTP_RTCOFFS_NSEC - #define PTP_RTCOFFS0_REG_PTP_RTCOFFS_NSEC_OFFSET 0 - #define PTP_RTCOFFS0_REG_PTP_RTCOFFS_NSEC_LEN 16 - #define PTP_RTCOFFS0_REG_PTP_RTCOFFS_NSEC_DEFAULT 0x0 - -struct ptp_rtcoffs0_reg { - a_uint16_t ptp_rtcoffs_nsec:16; -}; - -union ptp_rtcoffs0_reg_u { - a_uint32_t val; - struct ptp_rtcoffs0_reg bf; -}; - -/*[register] PTP_RTCOFFS1_REG*/ -#define PTP_RTCOFFS1_REG -#define PTP_RTCOFFS1_REG_ADDRESS 0x8039 -#define PTP_RTCOFFS1_REG_NUM 1 -#define PTP_RTCOFFS1_REG_INC 0x1 -#define PTP_RTCOFFS1_REG_TYPE REG_TYPE_RW -#define PTP_RTCOFFS1_REG_DEFAULT 0x0 - /*[field] PTP_RTCOFFS_NSEC*/ - #define PTP_RTCOFFS1_REG_PTP_RTCOFFS_NSEC - #define PTP_RTCOFFS1_REG_PTP_RTCOFFS_NSEC_OFFSET 0 - #define PTP_RTCOFFS1_REG_PTP_RTCOFFS_NSEC_LEN 16 - #define PTP_RTCOFFS1_REG_PTP_RTCOFFS_NSEC_DEFAULT 0x0 - -struct ptp_rtcoffs1_reg { - a_uint16_t ptp_rtcoffs_nsec:16; -}; - -union ptp_rtcoffs1_reg_u { - a_uint32_t val; - struct ptp_rtcoffs1_reg bf; -}; - -/*[register] PTP_RTCOFFS2_REG*/ -#define PTP_RTCOFFS2_REG -#define PTP_RTCOFFS2_REG_ADDRESS 0x803a -#define PTP_RTCOFFS2_REG_NUM 1 -#define PTP_RTCOFFS2_REG_INC 0x1 -#define PTP_RTCOFFS2_REG_TYPE REG_TYPE_RW -#define PTP_RTCOFFS2_REG_DEFAULT 0x0 - /*[field] PTP_RTCOFFS_SEC*/ - #define PTP_RTCOFFS2_REG_PTP_RTCOFFS_SEC - #define PTP_RTCOFFS2_REG_PTP_RTCOFFS_SEC_OFFSET 0 - #define PTP_RTCOFFS2_REG_PTP_RTCOFFS_SEC_LEN 16 - #define PTP_RTCOFFS2_REG_PTP_RTCOFFS_SEC_DEFAULT 0x0 - -struct ptp_rtcoffs2_reg { - a_uint16_t ptp_rtcoffs_sec:16; -}; - -union ptp_rtcoffs2_reg_u { - a_uint32_t val; - struct ptp_rtcoffs2_reg bf; -}; - -/*[register] PTP_RTCOFFS3_REG*/ -#define PTP_RTCOFFS3_REG -#define PTP_RTCOFFS3_REG_ADDRESS 0x803b -#define PTP_RTCOFFS3_REG_NUM 1 -#define PTP_RTCOFFS3_REG_INC 0x1 -#define PTP_RTCOFFS3_REG_TYPE REG_TYPE_RW -#define PTP_RTCOFFS3_REG_DEFAULT 0x0 - /*[field] PTP_RTCOFFS_SEC*/ - #define PTP_RTCOFFS3_REG_PTP_RTCOFFS_SEC - #define PTP_RTCOFFS3_REG_PTP_RTCOFFS_SEC_OFFSET 0 - #define PTP_RTCOFFS3_REG_PTP_RTCOFFS_SEC_LEN 16 - #define PTP_RTCOFFS3_REG_PTP_RTCOFFS_SEC_DEFAULT 0x0 - -struct ptp_rtcoffs3_reg { - a_uint16_t ptp_rtcoffs_sec:16; -}; - -union ptp_rtcoffs3_reg_u { - a_uint32_t val; - struct ptp_rtcoffs3_reg bf; -}; - -/*[register] PTP_RTCOFFS4_REG*/ -#define PTP_RTCOFFS4_REG -#define PTP_RTCOFFS4_REG_ADDRESS 0x803c -#define PTP_RTCOFFS4_REG_NUM 1 -#define PTP_RTCOFFS4_REG_INC 0x1 -#define PTP_RTCOFFS4_REG_TYPE REG_TYPE_RW -#define PTP_RTCOFFS4_REG_DEFAULT 0x0 - /*[field] PTP_RTCOFFS_SEC*/ - #define PTP_RTCOFFS4_REG_PTP_RTCOFFS_SEC - #define PTP_RTCOFFS4_REG_PTP_RTCOFFS_SEC_OFFSET 0 - #define PTP_RTCOFFS4_REG_PTP_RTCOFFS_SEC_LEN 16 - #define PTP_RTCOFFS4_REG_PTP_RTCOFFS_SEC_DEFAULT 0x0 - -struct ptp_rtcoffs4_reg { - a_uint16_t ptp_rtcoffs_sec:16; -}; - -union ptp_rtcoffs4_reg_u { - a_uint32_t val; - struct ptp_rtcoffs4_reg bf; -}; - -/*[register] PTP_RTC0_REG*/ -#define PTP_RTC0_REG -#define PTP_RTC0_REG_ADDRESS 0x803d -#define PTP_RTC0_REG_NUM 1 -#define PTP_RTC0_REG_INC 0x1 -#define PTP_RTC0_REG_TYPE REG_TYPE_RW -#define PTP_RTC0_REG_DEFAULT 0x0 - /*[field] PTP_RTC_SEC*/ - #define PTP_RTC0_REG_PTP_RTC_SEC - #define PTP_RTC0_REG_PTP_RTC_SEC_OFFSET 0 - #define PTP_RTC0_REG_PTP_RTC_SEC_LEN 16 - #define PTP_RTC0_REG_PTP_RTC_SEC_DEFAULT 0x0 - -struct ptp_rtc0_reg { - a_uint16_t ptp_rtc_sec:16; -}; - -union ptp_rtc0_reg_u { - a_uint32_t val; - struct ptp_rtc0_reg bf; -}; - -/*[register] PTP_RTC1_REG*/ -#define PTP_RTC1_REG -#define PTP_RTC1_REG_ADDRESS 0x803e -#define PTP_RTC1_REG_NUM 1 -#define PTP_RTC1_REG_INC 0x1 -#define PTP_RTC1_REG_TYPE REG_TYPE_RW -#define PTP_RTC1_REG_DEFAULT 0x0 - /*[field] PTP_RTC_SEC*/ - #define PTP_RTC1_REG_PTP_RTC_SEC - #define PTP_RTC1_REG_PTP_RTC_SEC_OFFSET 0 - #define PTP_RTC1_REG_PTP_RTC_SEC_LEN 16 - #define PTP_RTC1_REG_PTP_RTC_SEC_DEFAULT 0x0 - -struct ptp_rtc1_reg { - a_uint16_t ptp_rtc_sec:16; -}; - -union ptp_rtc1_reg_u { - a_uint32_t val; - struct ptp_rtc1_reg bf; -}; - -/*[register] PTP_RTC2_REG*/ -#define PTP_RTC2_REG -#define PTP_RTC2_REG_ADDRESS 0x803f -#define PTP_RTC2_REG_NUM 1 -#define PTP_RTC2_REG_INC 0x1 -#define PTP_RTC2_REG_TYPE REG_TYPE_RW -#define PTP_RTC2_REG_DEFAULT 0x0 - /*[field] PTP_RTC_SEC*/ - #define PTP_RTC2_REG_PTP_RTC_SEC - #define PTP_RTC2_REG_PTP_RTC_SEC_OFFSET 0 - #define PTP_RTC2_REG_PTP_RTC_SEC_LEN 16 - #define PTP_RTC2_REG_PTP_RTC_SEC_DEFAULT 0x0 - -struct ptp_rtc2_reg { - a_uint16_t ptp_rtc_sec:16; -}; - -union ptp_rtc2_reg_u { - a_uint32_t val; - struct ptp_rtc2_reg bf; -}; - -/*[register] PTP_RTC3_REG*/ -#define PTP_RTC3_REG -#define PTP_RTC3_REG_ADDRESS 0x8040 -#define PTP_RTC3_REG_NUM 1 -#define PTP_RTC3_REG_INC 0x1 -#define PTP_RTC3_REG_TYPE REG_TYPE_RW -#define PTP_RTC3_REG_DEFAULT 0x0 - /*[field] PTP_RTC_NISEC*/ - #define PTP_RTC3_REG_PTP_RTC_NISEC - #define PTP_RTC3_REG_PTP_RTC_NISEC_OFFSET 0 - #define PTP_RTC3_REG_PTP_RTC_NISEC_LEN 16 - #define PTP_RTC3_REG_PTP_RTC_NISEC_DEFAULT 0x0 - -struct ptp_rtc3_reg { - a_uint16_t ptp_rtc_nisec:16; -}; - -union ptp_rtc3_reg_u { - a_uint32_t val; - struct ptp_rtc3_reg bf; -}; - -/*[register] PTP_RTC4_REG*/ -#define PTP_RTC4_REG -#define PTP_RTC4_REG_ADDRESS 0x8041 -#define PTP_RTC4_REG_NUM 1 -#define PTP_RTC4_REG_INC 0x1 -#define PTP_RTC4_REG_TYPE REG_TYPE_RW -#define PTP_RTC4_REG_DEFAULT 0x0 - /*[field] PTP_RTC_NISEC*/ - #define PTP_RTC4_REG_PTP_RTC_NISEC - #define PTP_RTC4_REG_PTP_RTC_NISEC_OFFSET 0 - #define PTP_RTC4_REG_PTP_RTC_NISEC_LEN 16 - #define PTP_RTC4_REG_PTP_RTC_NISEC_DEFAULT 0x0 - -struct ptp_rtc4_reg { - a_uint16_t ptp_rtc_nisec:16; -}; - -union ptp_rtc4_reg_u { - a_uint32_t val; - struct ptp_rtc4_reg bf; -}; - -/*[register] PTP_RTC5_REG*/ -#define PTP_RTC5_REG -#define PTP_RTC5_REG_ADDRESS 0x8042 -#define PTP_RTC5_REG_NUM 1 -#define PTP_RTC5_REG_INC 0x1 -#define PTP_RTC5_REG_TYPE REG_TYPE_RW -#define PTP_RTC5_REG_DEFAULT 0x0 - /*[field] PTP_RTC_NFSEC*/ - #define PTP_RTC5_REG_PTP_RTC_NFSEC - #define PTP_RTC5_REG_PTP_RTC_NFSEC_OFFSET 0 - #define PTP_RTC5_REG_PTP_RTC_NFSEC_LEN 16 - #define PTP_RTC5_REG_PTP_RTC_NFSEC_DEFAULT 0x0 - -struct ptp_rtc5_reg { - a_uint16_t ptp_rtc_nfsec:16; -}; - -union ptp_rtc5_reg_u { - a_uint32_t val; - struct ptp_rtc5_reg bf; -}; - -/*[register] PTP_RTC6_REG*/ -#define PTP_RTC6_REG -#define PTP_RTC6_REG_ADDRESS 0x8043 -#define PTP_RTC6_REG_NUM 1 -#define PTP_RTC6_REG_INC 0x1 -#define PTP_RTC6_REG_TYPE REG_TYPE_RW -#define PTP_RTC6_REG_DEFAULT 0x0 - /*[field] PTP_RTC_NFSEC*/ - #define PTP_RTC6_REG_PTP_RTC_NFSEC - #define PTP_RTC6_REG_PTP_RTC_NFSEC_OFFSET 0 - #define PTP_RTC6_REG_PTP_RTC_NFSEC_LEN 4 - #define PTP_RTC6_REG_PTP_RTC_NFSEC_DEFAULT 0x0 - -struct ptp_rtc6_reg { - a_uint16_t ptp_rtc_nfsec:4; -}; - -union ptp_rtc6_reg_u { - a_uint32_t val; - struct ptp_rtc6_reg bf; -}; - -/*[register] PTP_RTCOFFS_VALID_REG*/ -#define PTP_RTCOFFS_VALID_REG -#define PTP_RTCOFFS_VALID_REG_ADDRESS 0x8044 -#define PTP_RTCOFFS_VALID_REG_NUM 1 -#define PTP_RTCOFFS_VALID_REG_INC 0x1 -#define PTP_RTCOFFS_VALID_REG_TYPE REG_TYPE_RW -#define PTP_RTCOFFS_VALID_REG_DEFAULT 0x0 - /*[field] PTP_RTCOFFS_VALID*/ - #define PTP_RTCOFFS_VALID_REG_PTP_RTCOFFS_VALID - #define PTP_RTCOFFS_VALID_REG_PTP_RTCOFFS_VALID_OFFSET 0 - #define PTP_RTCOFFS_VALID_REG_PTP_RTCOFFS_VALID_LEN 1 - #define PTP_RTCOFFS_VALID_REG_PTP_RTCOFFS_VALID_DEFAULT 0x0 - -struct ptp_rtcoffs_valid_reg { - a_uint16_t ptp_rtcoffs_valid:1; -}; - -union ptp_rtcoffs_valid_reg_u { - a_uint32_t val; - struct ptp_rtcoffs_valid_reg bf; -}; - -/*[register] PTP_MISC_CONFIG_REG*/ -#define PTP_MISC_CONFIG_REG -#define PTP_MISC_CONFIG_REG_ADDRESS 0x80f0 -#define PTP_MISC_CONFIG_REG_NUM 1 -#define PTP_MISC_CONFIG_REG_INC 0x1 -#define PTP_MISC_CONFIG_REG_TYPE REG_TYPE_RW -#define PTP_MISC_CONFIG_REG_DEFAULT 0x4 - /*[field] IPV6_UDP_CHK_EN*/ - #define PTP_MISC_CONFIG_REG_IPV6_UDP_CHK_EN - #define PTP_MISC_CONFIG_REG_IPV6_UDP_CHK_EN_OFFSET 0 - #define PTP_MISC_CONFIG_REG_IPV6_UDP_CHK_EN_LEN 1 - #define PTP_MISC_CONFIG_REG_IPV6_UDP_CHK_EN_DEFAULT 0x0 - /*[field] PTP_VERSION*/ - #define PTP_MISC_CONFIG_REG_PTP_VERSION - #define PTP_MISC_CONFIG_REG_PTP_VERSION_OFFSET 1 - #define PTP_MISC_CONFIG_REG_PTP_VERSION_LEN 4 - #define PTP_MISC_CONFIG_REG_PTP_VERSION_DEFAULT 0x2 - /*[field] PTP_VER_CHK_EN*/ - #define PTP_MISC_CONFIG_REG_PTP_VER_CHK_EN - #define PTP_MISC_CONFIG_REG_PTP_VER_CHK_EN_OFFSET 5 - #define PTP_MISC_CONFIG_REG_PTP_VER_CHK_EN_LEN 1 - #define PTP_MISC_CONFIG_REG_PTP_VER_CHK_EN_DEFAULT 0x0 - /*[field] PTP_ADDR_CHK_EN*/ - #define PTP_MISC_CONFIG_REG_PTP_ADDR_CHK_EN - #define PTP_MISC_CONFIG_REG_PTP_ADDR_CHK_EN_OFFSET 6 - #define PTP_MISC_CONFIG_REG_PTP_ADDR_CHK_EN_LEN 1 - #define PTP_MISC_CONFIG_REG_PTP_ADDR_CHK_EN_DEFAULT 0x0 - /*[field] CRC_VALIDATE_EN*/ - #define PTP_MISC_CONFIG_REG_CRC_VALIDATE_EN - #define PTP_MISC_CONFIG_REG_CRC_VALIDATE_EN_OFFSET 7 - #define PTP_MISC_CONFIG_REG_CRC_VALIDATE_EN_LEN 1 - #define PTP_MISC_CONFIG_REG_CRC_VALIDATE_EN_DEFAULT 0x0 - /*[field] APPENDED_TIMESTAMP_SIZE*/ - #define PTP_MISC_CONFIG_REG_APPENDED_TIMESTAMP_SIZE - #define PTP_MISC_CONFIG_REG_APPENDED_TIMESTAMP_SIZE_OFFSET 8 - #define PTP_MISC_CONFIG_REG_APPENDED_TIMESTAMP_SIZE_LEN 2 - #define PTP_MISC_CONFIG_REG_APPENDED_TIMESTAMP_SIZE_DEFAULT 0x0 - /*[field] TS_RTC_SELECT*/ - #define PTP_MISC_CONFIG_REG_TS_RTC_SELECT - #define PTP_MISC_CONFIG_REG_TS_RTC_SELECT_OFFSET 10 - #define PTP_MISC_CONFIG_REG_TS_RTC_SELECT_LEN 1 - #define PTP_MISC_CONFIG_REG_TS_RTC_SELECT_DEFAULT 0x0 - /*[field] PKT_ONE_STEP_EN*/ - #define PTP_MISC_CONFIG_REG_PKT_ONE_STEP_EN - #define PTP_MISC_CONFIG_REG_PKT_ONE_STEP_EN_OFFSET 11 - #define PTP_MISC_CONFIG_REG_PKT_ONE_STEP_EN_LEN 1 - #define PTP_MISC_CONFIG_REG_PKT_ONE_STEP_EN_DEFAULT 0x0 - /*[field] CF_FROM_PKT_EN*/ - #define PTP_MISC_CONFIG_REG_CF_FROM_PKT_EN - #define PTP_MISC_CONFIG_REG_CF_FROM_PKT_EN_OFFSET 12 - #define PTP_MISC_CONFIG_REG_CF_FROM_PKT_EN_LEN 1 - #define PTP_MISC_CONFIG_REG_CF_FROM_PKT_EN_DEFAULT 0x0 - /*[field] EMBED_INGRESS_TIME_EN*/ - #define PTP_MISC_CONFIG_REG_EMBED_INGRESS_TIME_EN - #define PTP_MISC_CONFIG_REG_EMBED_INGRESS_TIME_EN_OFFSET 13 - #define PTP_MISC_CONFIG_REG_EMBED_INGRESS_TIME_EN_LEN 1 - #define PTP_MISC_CONFIG_REG_EMBED_INGRESS_TIME_EN_DEFAULT 0x0 - /*[field] DROP_NEXT_PREAMBLE_EN*/ - #define PTP_MISC_CONFIG_REG_DROP_NEXT_PREAMBLE_EN - #define PTP_MISC_CONFIG_REG_DROP_NEXT_PREAMBLE_EN_OFFSET 14 - #define PTP_MISC_CONFIG_REG_DROP_NEXT_PREAMBLE_EN_LEN 1 - #define PTP_MISC_CONFIG_REG_DROP_NEXT_PREAMBLE_EN_DEFAULT 0x0 - /*[field] P2P_TC_OFFLOAD*/ - #define PTP_MISC_CONFIG_REG_P2P_TC_OFFLOAD - #define PTP_MISC_CONFIG_REG_P2P_TC_OFFLOAD_OFFSET 15 - #define PTP_MISC_CONFIG_REG_P2P_TC_OFFLOAD_LEN 1 - #define PTP_MISC_CONFIG_REG_P2P_TC_OFFLOAD_DEFAULT 0x0 - -struct ptp_misc_config_reg { - a_uint16_t ipv6_udp_chk_en:1; - a_uint16_t ptp_version:4; - a_uint16_t ptp_ver_chk_en:1; - a_uint16_t ptp_addr_chk_en:1; - a_uint16_t crc_validate_en:1; - a_uint16_t appended_timestamp_size:2; - a_uint16_t ts_rtc_select:1; - a_uint16_t pkt_one_step_en:1; - a_uint16_t cf_from_pkt_en:1; - a_uint16_t embed_ingress_time_en:1; - a_uint16_t drop_next_preamble_en:1; - a_uint16_t tc_offload:1; -}; - -union ptp_misc_config_reg_u { - a_uint32_t val; - struct ptp_misc_config_reg bf; -}; - -/*[register] PTP_EXT_IMR_REG*/ -#define PTP_EXT_IMR_REG -#define PTP_EXT_IMR_REG_ADDRESS 0x80f1 -#define PTP_EXT_IMR_REG_NUM 1 -#define PTP_EXT_IMR_REG_INC 0x1 -#define PTP_EXT_IMR_REG_TYPE REG_TYPE_RW -#define PTP_EXT_IMR_REG_DEFAULT 0x0 - /*[field] MASK_BMP*/ - #define PTP_EXT_IMR_REG_MASK_BMP - #define PTP_EXT_IMR_REG_MASK_BMP_OFFSET 0 - #define PTP_EXT_IMR_REG_MASK_BMP_LEN 5 - #define PTP_EXT_IMR_REG_MASK_BMP_DEFAULT 0x0 - -struct ptp_ext_imr_reg { - a_uint16_t mask_bmp:16; -}; - -union ptp_ext_imr_reg_u { - a_uint32_t val; - struct ptp_ext_imr_reg bf; -}; - -/*[register] PTP_EXT_ISR_REG*/ -#define PTP_EXT_ISR_REG -#define PTP_EXT_ISR_REG_ADDRESS 0x80f2 -#define PTP_EXT_ISR_REG_NUM 1 -#define PTP_EXT_ISR_REG_INC 0x1 -#define PTP_EXT_ISR_REG_TYPE REG_TYPE_RW -#define PTP_EXT_ISR_REG_DEFAULT 0x0 - /*[field] STATUS_BMP*/ - #define PTP_EXT_ISR_REG_STATUS_BMP - #define PTP_EXT_ISR_REG_STATUS_BMP_OFFSET 0 - #define PTP_EXT_ISR_REG_STATUS_BMP_LEN 5 - #define PTP_EXT_ISR_REG_STATUS_BMP_DEFAULT 0x0 - -struct ptp_ext_isr_reg { - a_uint16_t status_bmp:16; -}; - -union ptp_ext_isr_reg_u { - a_uint32_t val; - struct ptp_ext_isr_reg bf; -}; - -/*[register] PTP_RTC_EXT_CONF_REG*/ -#define PTP_RTC_EXT_CONF_REG -#define PTP_RTC_EXT_CONF_REG_ADDRESS 0x8100 -#define PTP_RTC_EXT_CONF_REG_NUM 1 -#define PTP_RTC_EXT_CONF_REG_INC 0x1 -#define PTP_RTC_EXT_CONF_REG_TYPE REG_TYPE_RW -#define PTP_RTC_EXT_CONF_REG_DEFAULT 0x0 - /*[field] LOAD_RTC*/ - #define PTP_RTC_EXT_CONF_REG_LOAD_RTC - #define PTP_RTC_EXT_CONF_REG_LOAD_RTC_OFFSET 0 - #define PTP_RTC_EXT_CONF_REG_LOAD_RTC_LEN 1 - #define PTP_RTC_EXT_CONF_REG_LOAD_RTC_DEFAULT 0x0 - /*[field] CLEAR_RTC*/ - #define PTP_RTC_EXT_CONF_REG_CLEAR_RTC - #define PTP_RTC_EXT_CONF_REG_CLEAR_RTC_OFFSET 1 - #define PTP_RTC_EXT_CONF_REG_CLEAR_RTC_LEN 1 - #define PTP_RTC_EXT_CONF_REG_CLEAR_RTC_DEFAULT 0x0 - /*[field] SET_INCVAL_VALID*/ - #define PTP_RTC_EXT_CONF_REG_SET_INCVAL_VALID - #define PTP_RTC_EXT_CONF_REG_SET_INCVAL_VALID_OFFSET 2 - #define PTP_RTC_EXT_CONF_REG_SET_INCVAL_VALID_LEN 1 - #define PTP_RTC_EXT_CONF_REG_SET_INCVAL_VALID_DEFAULT 0x0 - /*[field] SET_INCVAL_MODE*/ - #define PTP_RTC_EXT_CONF_REG_SET_INCVAL_MODE - #define PTP_RTC_EXT_CONF_REG_SET_INCVAL_MODE_OFFSET 3 - #define PTP_RTC_EXT_CONF_REG_SET_INCVAL_MODE_LEN 1 - #define PTP_RTC_EXT_CONF_REG_SET_INCVAL_MODE_DEFAULT 0x0 - /*[field] RTC_SNAPSHOT*/ - #define PTP_RTC_EXT_CONF_REG_RTC_SNAPSHOT - #define PTP_RTC_EXT_CONF_REG_RTC_SNAPSHOT_OFFSET 4 - #define PTP_RTC_EXT_CONF_REG_RTC_SNAPSHOT_LEN 1 - #define PTP_RTC_EXT_CONF_REG_RTC_SNAPSHOT_DEFAULT 0x0 - /*[field] RTC_READ_MODE*/ - #define PTP_RTC_EXT_CONF_REG_RTC_READ_MODE - #define PTP_RTC_EXT_CONF_REG_RTC_READ_MODE_OFFSET 5 - #define PTP_RTC_EXT_CONF_REG_RTC_READ_MODE_LEN 1 - #define PTP_RTC_EXT_CONF_REG_RTC_READ_MODE_DEFAULT 0x0 - /*[field] SELECT_OUTPUT_WAVEFORM*/ - #define PTP_RTC_EXT_CONF_REG_SELECT_OUTPUT_WAVEFORM - #define PTP_RTC_EXT_CONF_REG_SELECT_OUTPUT_WAVEFORM_OFFSET 6 - #define PTP_RTC_EXT_CONF_REG_SELECT_OUTPUT_WAVEFORM_LEN 3 - #define PTP_RTC_EXT_CONF_REG_SELECT_OUTPUT_WAVEFORM_DEFAULT 0x0 - -#define PTP_RTC_EXT_CONF_REG_SELECT_OUTPUT_WAVEFORM_FREQ 0 -#define PTP_RTC_EXT_CONF_REG_SELECT_OUTPUT_WAVEFORM_PULSE_10MS 2 -#define PTP_RTC_EXT_CONF_REG_SELECT_OUTPUT_WAVEFORM_TRIG0_GPIO 5 -#define PTP_RTC_EXT_CONF_REG_SELECT_OUTPUT_WAVEFORM_RXTS_VALID 7 - -struct ptp_rtc_ext_conf_reg { - a_uint16_t load_rtc:1; - a_uint16_t clear_rtc:1; - a_uint16_t set_incval_valid:1; - a_uint16_t set_incval_mode:1; - a_uint16_t rtc_snapshot:1; - a_uint16_t rtc_read_mode:1; - a_uint16_t select_output_waveform:3; -}; - -union ptp_rtc_ext_conf_reg_u { - a_uint32_t val; - struct ptp_rtc_ext_conf_reg bf; -}; - -/*[register] PTP_RTC_PRELOADED0_REG*/ -#define PTP_RTC_PRELOADED0_REG -#define PTP_RTC_PRELOADED0_REG_ADDRESS 0x8101 -#define PTP_RTC_PRELOADED0_REG_NUM 1 -#define PTP_RTC_PRELOADED0_REG_INC 0x1 -#define PTP_RTC_PRELOADED0_REG_TYPE REG_TYPE_RW -#define PTP_RTC_PRELOADED0_REG_DEFAULT 0x0 - /*[field] PTP_RTC_PRELOADED_SEC*/ - #define PTP_RTC_PRELOADED0_REG_PTP_RTC_PRELOADED_SEC - #define PTP_RTC_PRELOADED0_REG_PTP_RTC_PRELOADED_SEC_OFFSET 0 - #define PTP_RTC_PRELOADED0_REG_PTP_RTC_PRELOADED_SEC_LEN 16 - #define PTP_RTC_PRELOADED0_REG_PTP_RTC_PRELOADED_SEC_DEFAULT 0x0 - -struct ptp_rtc_preloaded0_reg { - a_uint16_t ptp_rtc_preloaded_sec:16; -}; - -union ptp_rtc_preloaded0_reg_u { - a_uint32_t val; - struct ptp_rtc_preloaded0_reg bf; -}; - -/*[register] PTP_RTC_PRELOADED1_REG*/ -#define PTP_RTC_PRELOADED1_REG -#define PTP_RTC_PRELOADED1_REG_ADDRESS 0x8102 -#define PTP_RTC_PRELOADED1_REG_NUM 1 -#define PTP_RTC_PRELOADED1_REG_INC 0x1 -#define PTP_RTC_PRELOADED1_REG_TYPE REG_TYPE_RW -#define PTP_RTC_PRELOADED1_REG_DEFAULT 0x0 - /*[field] PTP_RTC_PRELOADED_SEC*/ - #define PTP_RTC_PRELOADED1_REG_PTP_RTC_PRELOADED_SEC - #define PTP_RTC_PRELOADED1_REG_PTP_RTC_PRELOADED_SEC_OFFSET 0 - #define PTP_RTC_PRELOADED1_REG_PTP_RTC_PRELOADED_SEC_LEN 16 - #define PTP_RTC_PRELOADED1_REG_PTP_RTC_PRELOADED_SEC_DEFAULT 0x0 - -struct ptp_rtc_preloaded1_reg { - a_uint16_t ptp_rtc_preloaded_sec:16; -}; - -union ptp_rtc_preloaded1_reg_u { - a_uint32_t val; - struct ptp_rtc_preloaded1_reg bf; -}; - -/*[register] PTP_RTC_PRELOADED2_REG*/ -#define PTP_RTC_PRELOADED2_REG -#define PTP_RTC_PRELOADED2_REG_ADDRESS 0x8103 -#define PTP_RTC_PRELOADED2_REG_NUM 1 -#define PTP_RTC_PRELOADED2_REG_INC 0x1 -#define PTP_RTC_PRELOADED2_REG_TYPE REG_TYPE_RW -#define PTP_RTC_PRELOADED2_REG_DEFAULT 0x0 - /*[field] PTP_RTC_PRELOADED_SEC*/ - #define PTP_RTC_PRELOADED2_REG_PTP_RTC_PRELOADED_SEC - #define PTP_RTC_PRELOADED2_REG_PTP_RTC_PRELOADED_SEC_OFFSET 0 - #define PTP_RTC_PRELOADED2_REG_PTP_RTC_PRELOADED_SEC_LEN 16 - #define PTP_RTC_PRELOADED2_REG_PTP_RTC_PRELOADED_SEC_DEFAULT 0x0 - -struct ptp_rtc_preloaded2_reg { - a_uint16_t ptp_rtc_preloaded_sec:16; -}; - -union ptp_rtc_preloaded2_reg_u { - a_uint32_t val; - struct ptp_rtc_preloaded2_reg bf; -}; - -/*[register] PTP_RTC_PRELOADED3_REG*/ -#define PTP_RTC_PRELOADED3_REG -#define PTP_RTC_PRELOADED3_REG_ADDRESS 0x8104 -#define PTP_RTC_PRELOADED3_REG_NUM 1 -#define PTP_RTC_PRELOADED3_REG_INC 0x1 -#define PTP_RTC_PRELOADED3_REG_TYPE REG_TYPE_RW -#define PTP_RTC_PRELOADED3_REG_DEFAULT 0x0 - /*[field] PTP_RTC_PRELOADED_NISEC*/ - #define PTP_RTC_PRELOADED3_REG_PTP_RTC_PRELOADED_NISEC - #define PTP_RTC_PRELOADED3_REG_PTP_RTC_PRELOADED_NISEC_OFFSET 0 - #define PTP_RTC_PRELOADED3_REG_PTP_RTC_PRELOADED_NISEC_LEN 16 - #define PTP_RTC_PRELOADED3_REG_PTP_RTC_PRELOADED_NISEC_DEFAULT 0x0 - -struct ptp_rtc_preloaded3_reg { - a_uint16_t ptp_rtc_preloaded_nisec:16; -}; - -union ptp_rtc_preloaded3_reg_u { - a_uint32_t val; - struct ptp_rtc_preloaded3_reg bf; -}; - -/*[register] PTP_RTC_PRELOADED4_REG*/ -#define PTP_RTC_PRELOADED4_REG -#define PTP_RTC_PRELOADED4_REG_ADDRESS 0x8105 -#define PTP_RTC_PRELOADED4_REG_NUM 1 -#define PTP_RTC_PRELOADED4_REG_INC 0x1 -#define PTP_RTC_PRELOADED4_REG_TYPE REG_TYPE_RW -#define PTP_RTC_PRELOADED4_REG_DEFAULT 0x0 - /*[field] PTP_RTC_PRELOADED_NISEC*/ - #define PTP_RTC_PRELOADED4_REG_PTP_RTC_PRELOADED_NISEC - #define PTP_RTC_PRELOADED4_REG_PTP_RTC_PRELOADED_NISEC_OFFSET 0 - #define PTP_RTC_PRELOADED4_REG_PTP_RTC_PRELOADED_NISEC_LEN 16 - #define PTP_RTC_PRELOADED4_REG_PTP_RTC_PRELOADED_NISEC_DEFAULT 0x0 - -struct ptp_rtc_preloaded4_reg { - a_uint16_t ptp_rtc_preloaded_nisec:16; -}; - -union ptp_rtc_preloaded4_reg_u { - a_uint32_t val; - struct ptp_rtc_preloaded4_reg bf; -}; - -/*[register] PTP_GM_CONF0_REG*/ -#define PTP_GM_CONF0_REG -#define PTP_GM_CONF0_REG_ADDRESS 0x8200 -#define PTP_GM_CONF0_REG_NUM 1 -#define PTP_GM_CONF0_REG_INC 0x1 -#define PTP_GM_CONF0_REG_TYPE REG_TYPE_RW -#define PTP_GM_CONF0_REG_DEFAULT 0x0 - /*[field] GM_MAXFREQ_OFFSET*/ - #define PTP_GM_CONF0_REG_GM_MAXFREQ_OFFSET - #define PTP_GM_CONF0_REG_GM_MAXFREQ_OFFSET_OFFSET 0 - #define PTP_GM_CONF0_REG_GM_MAXFREQ_OFFSET_LEN 4 - #define PTP_GM_CONF0_REG_GM_MAXFREQ_OFFSET_DEFAULT 0x0 - /*[field] GM_PLL_MODE*/ - #define PTP_GM_CONF0_REG_GM_PLL_MODE - #define PTP_GM_CONF0_REG_GM_PLL_MODE_OFFSET 4 - #define PTP_GM_CONF0_REG_GM_PLL_MODE_LEN 1 - #define PTP_GM_CONF0_REG_GM_PLL_MODE_DEFAULT 0x0 - /*[field] GM_PPS_SYNC*/ - #define PTP_GM_CONF0_REG_GM_PPS_SYNC - #define PTP_GM_CONF0_REG_GM_PPS_SYNC_OFFSET 5 - #define PTP_GM_CONF0_REG_GM_PPS_SYNC_LEN 1 - #define PTP_GM_CONF0_REG_GM_PPS_SYNC_DEFAULT 0x0 - /*[field] GRANDMASTER_MODE*/ - #define PTP_GM_CONF0_REG_GRANDMASTER_MODE - #define PTP_GM_CONF0_REG_GRANDMASTER_MODE_OFFSET 6 - #define PTP_GM_CONF0_REG_GRANDMASTER_MODE_LEN 1 - #define PTP_GM_CONF0_REG_GRANDMASTER_MODE_DEFAULT 0x0 - -struct ptp_gm_conf0_reg { - a_uint16_t gm_maxfreq_offset:4; - a_uint16_t gm_pll_mode:1; - a_uint16_t gm_pps_sync:1; - a_uint16_t grandmaster_mode:1; -}; - -union ptp_gm_conf0_reg_u { - a_uint32_t val; - struct ptp_gm_conf0_reg bf; -}; - -/*[register] PTP_GM_CONF1_REG*/ -#define PTP_GM_CONF1_REG -#define PTP_GM_CONF1_REG_ADDRESS 0x8201 -#define PTP_GM_CONF1_REG_NUM 1 -#define PTP_GM_CONF1_REG_INC 0x1 -#define PTP_GM_CONF1_REG_TYPE REG_TYPE_RW -#define PTP_GM_CONF1_REG_DEFAULT 0x0 - /*[field] GM_KI_LDN*/ - #define PTP_GM_CONF1_REG_GM_KI_LDN - #define PTP_GM_CONF1_REG_GM_KI_LDN_OFFSET 0 - #define PTP_GM_CONF1_REG_GM_KI_LDN_LEN 6 - #define PTP_GM_CONF1_REG_GM_KI_LDN_DEFAULT 0x0 - /*[field] GM_KP_LDN*/ - #define PTP_GM_CONF1_REG_GM_KP_LDN - #define PTP_GM_CONF1_REG_GM_KP_LDN_OFFSET 6 - #define PTP_GM_CONF1_REG_GM_KP_LDN_LEN 6 - #define PTP_GM_CONF1_REG_GM_KP_LDN_DEFAULT 0x0 - -struct ptp_gm_conf1_reg { - a_uint16_t gm_ki_ldn:6; - a_uint16_t gm_kp_ldn:6; -}; - -union ptp_gm_conf1_reg_u { - a_uint32_t val; - struct ptp_gm_conf1_reg bf; -}; - -/*[register] PTP_PPSIN_TS0_REG*/ -#define PTP_PPSIN_TS0_REG -#define PTP_PPSIN_TS0_REG_ADDRESS 0x8202 -#define PTP_PPSIN_TS0_REG_NUM 1 -#define PTP_PPSIN_TS0_REG_INC 0x1 -#define PTP_PPSIN_TS0_REG_TYPE REG_TYPE_RW -#define PTP_PPSIN_TS0_REG_DEFAULT 0x0 - /*[field] RX_TS_SEC*/ - #define PTP_PPSIN_TS0_REG_RX_TS_SEC - #define PTP_PPSIN_TS0_REG_RX_TS_SEC_OFFSET 0 - #define PTP_PPSIN_TS0_REG_RX_TS_SEC_LEN 16 - #define PTP_PPSIN_TS0_REG_RX_TS_SEC_DEFAULT 0x0 - -struct ptp_ppsin_ts0_reg { - a_uint16_t rx_ts_sec:16; -}; - -union ptp_ppsin_ts0_reg_u { - a_uint32_t val; - struct ptp_ppsin_ts0_reg bf; -}; - -/*[register] PTP_PPSIN_TS1_REG*/ -#define PTP_PPSIN_TS1_REG -#define PTP_PPSIN_TS1_REG_ADDRESS 0x8203 -#define PTP_PPSIN_TS1_REG_NUM 1 -#define PTP_PPSIN_TS1_REG_INC 0x1 -#define PTP_PPSIN_TS1_REG_TYPE REG_TYPE_RW -#define PTP_PPSIN_TS1_REG_DEFAULT 0x0 - /*[field] RX_TS_SEC*/ - #define PTP_PPSIN_TS1_REG_RX_TS_SEC - #define PTP_PPSIN_TS1_REG_RX_TS_SEC_OFFSET 0 - #define PTP_PPSIN_TS1_REG_RX_TS_SEC_LEN 16 - #define PTP_PPSIN_TS1_REG_RX_TS_SEC_DEFAULT 0x0 - -struct ptp_ppsin_ts1_reg { - a_uint16_t rx_ts_sec:16; -}; - -union ptp_ppsin_ts1_reg_u { - a_uint32_t val; - struct ptp_ppsin_ts1_reg bf; -}; - -/*[register] PTP_PPSIN_TS2_REG*/ -#define PTP_PPSIN_TS2_REG -#define PTP_PPSIN_TS2_REG_ADDRESS 0x8204 -#define PTP_PPSIN_TS2_REG_NUM 1 -#define PTP_PPSIN_TS2_REG_INC 0x1 -#define PTP_PPSIN_TS2_REG_TYPE REG_TYPE_RW -#define PTP_PPSIN_TS2_REG_DEFAULT 0x0 - /*[field] RX_TS_SEC*/ - #define PTP_PPSIN_TS2_REG_RX_TS_SEC - #define PTP_PPSIN_TS2_REG_RX_TS_SEC_OFFSET 0 - #define PTP_PPSIN_TS2_REG_RX_TS_SEC_LEN 16 - #define PTP_PPSIN_TS2_REG_RX_TS_SEC_DEFAULT 0x0 - -struct ptp_ppsin_ts2_reg { - a_uint16_t rx_ts_sec:16; -}; - -union ptp_ppsin_ts2_reg_u { - a_uint32_t val; - struct ptp_ppsin_ts2_reg bf; -}; - -/*[register] PTP_PPSIN_TS3_REG*/ -#define PTP_PPSIN_TS3_REG -#define PTP_PPSIN_TS3_REG_ADDRESS 0x8205 -#define PTP_PPSIN_TS3_REG_NUM 1 -#define PTP_PPSIN_TS3_REG_INC 0x1 -#define PTP_PPSIN_TS3_REG_TYPE REG_TYPE_RW -#define PTP_PPSIN_TS3_REG_DEFAULT 0x0 - /*[field] RX_TS_NSEC*/ - #define PTP_PPSIN_TS3_REG_RX_TS_NSEC - #define PTP_PPSIN_TS3_REG_RX_TS_NSEC_OFFSET 0 - #define PTP_PPSIN_TS3_REG_RX_TS_NSEC_LEN 16 - #define PTP_PPSIN_TS3_REG_RX_TS_NSEC_DEFAULT 0x0 - -struct ptp_ppsin_ts3_reg { - a_uint16_t rx_ts_nsec:16; -}; - -union ptp_ppsin_ts3_reg_u { - a_uint32_t val; - struct ptp_ppsin_ts3_reg bf; -}; - -/*[register] PTP_PPSIN_TS4_REG*/ -#define PTP_PPSIN_TS4_REG -#define PTP_PPSIN_TS4_REG_ADDRESS 0x8206 -#define PTP_PPSIN_TS4_REG_NUM 1 -#define PTP_PPSIN_TS4_REG_INC 0x1 -#define PTP_PPSIN_TS4_REG_TYPE REG_TYPE_RW -#define PTP_PPSIN_TS4_REG_DEFAULT 0x0 - /*[field] RX_TS_NSEC*/ - #define PTP_PPSIN_TS4_REG_RX_TS_NSEC - #define PTP_PPSIN_TS4_REG_RX_TS_NSEC_OFFSET 0 - #define PTP_PPSIN_TS4_REG_RX_TS_NSEC_LEN 16 - #define PTP_PPSIN_TS4_REG_RX_TS_NSEC_DEFAULT 0x0 - -struct ptp_ppsin_ts4_reg { - a_uint16_t rx_ts_nsec:16; -}; - -union ptp_ppsin_ts4_reg_u { - a_uint32_t val; - struct ptp_ppsin_ts4_reg bf; -}; - -/*[register] PTP_HWPLL_INC0_REG*/ -#define PTP_HWPLL_INC0_REG -#define PTP_HWPLL_INC0_REG_ADDRESS 0x8207 -#define PTP_HWPLL_INC0_REG_NUM 1 -#define PTP_HWPLL_INC0_REG_INC 0x1 -#define PTP_HWPLL_INC0_REG_TYPE REG_TYPE_RW -#define PTP_HWPLL_INC0_REG_DEFAULT 0x0 - /*[field] PTP_RTC_INC_NFS1*/ - #define PTP_HWPLL_INC0_REG_PTP_RTC_INC_NFS1 - #define PTP_HWPLL_INC0_REG_PTP_RTC_INC_NFS1_OFFSET 0 - #define PTP_HWPLL_INC0_REG_PTP_RTC_INC_NFS1_LEN 10 - #define PTP_HWPLL_INC0_REG_PTP_RTC_INC_NFS1_DEFAULT 0x0 - /*[field] PTP_RTC_INC_NIS*/ - #define PTP_HWPLL_INC0_REG_PTP_RTC_INC_NIS - #define PTP_HWPLL_INC0_REG_PTP_RTC_INC_NIS_OFFSET 10 - #define PTP_HWPLL_INC0_REG_PTP_RTC_INC_NIS_LEN 6 - #define PTP_HWPLL_INC0_REG_PTP_RTC_INC_NIS_DEFAULT 0x0 - -struct ptp_hwpll_inc0_reg { - a_uint16_t ptp_rtc_inc_nfs1:10; - a_uint16_t ptp_rtc_inc_nis:6; -}; - -union ptp_hwpll_inc0_reg_u { - a_uint32_t val; - struct ptp_hwpll_inc0_reg bf; -}; - -/*[register] PTP_HWPLL_INC1_REG*/ -#define PTP_HWPLL_INC1_REG -#define PTP_HWPLL_INC1_REG_ADDRESS 0x8208 -#define PTP_HWPLL_INC1_REG_NUM 1 -#define PTP_HWPLL_INC1_REG_INC 0x1 -#define PTP_HWPLL_INC1_REG_TYPE REG_TYPE_RW -#define PTP_HWPLL_INC1_REG_DEFAULT 0x0 - /*[field] PTP_RTC_INC_NFS0*/ - #define PTP_HWPLL_INC1_REG_PTP_RTC_INC_NFS0 - #define PTP_HWPLL_INC1_REG_PTP_RTC_INC_NFS0_OFFSET 0 - #define PTP_HWPLL_INC1_REG_PTP_RTC_INC_NFS0_LEN 16 - #define PTP_HWPLL_INC1_REG_PTP_RTC_INC_NFS0_DEFAULT 0x0 - -struct ptp_hwpll_inc1_reg { - a_uint16_t ptp_rtc_inc_nfs0:16; -}; - -union ptp_hwpll_inc1_reg_u { - a_uint32_t val; - struct ptp_hwpll_inc1_reg bf; -}; - -/*[register] PTP_PPSIN_LATENCY_REG*/ -#define PTP_PPSIN_LATENCY_REG -#define PTP_PPSIN_LATENCY_REG_ADDRESS 0x8209 -#define PTP_PPSIN_LATENCY_REG_NUM 1 -#define PTP_PPSIN_LATENCY_REG_INC 0x1 -#define PTP_PPSIN_LATENCY_REG_TYPE REG_TYPE_RW -#define PTP_PPSIN_LATENCY_REG_DEFAULT 0x0 - /*[field] PTP_PPSIN_LATENCY_VALUE*/ - #define PTP_PPSIN_LATENCY_REG_PTP_PPSIN_LATENCY_VALUE - #define PTP_PPSIN_LATENCY_REG_PTP_PPSIN_LATENCY_VALUE_OFFSET 0 - #define PTP_PPSIN_LATENCY_REG_PTP_PPSIN_LATENCY_VALUE_LEN 7 - #define PTP_PPSIN_LATENCY_REG_PTP_PPSIN_LATENCY_VALUE_DEFAULT 0x0 - /*[field] PTP_PPSIN_LATENCY_SIGN*/ - #define PTP_PPSIN_LATENCY_REG_PTP_PPSIN_LATENCY_SIGN - #define PTP_PPSIN_LATENCY_REG_PTP_PPSIN_LATENCY_SIGN_OFFSET 7 - #define PTP_PPSIN_LATENCY_REG_PTP_PPSIN_LATENCY_SIGN_LEN 1 - #define PTP_PPSIN_LATENCY_REG_PTP_PPSIN_LATENCY_SIGN_DEFAULT 0x0 - -struct ptp_ppsin_latency_reg { - a_uint16_t ptp_ppsin_latency_value:7; - a_uint16_t ptp_ppsin_latency_sign:1; -}; - -union ptp_ppsin_latency_reg_u { - a_uint32_t val; - struct ptp_ppsin_latency_reg bf; -}; - -/*[register] PTP_TRIGGER0_CONFIG_REG*/ -#define PTP_TRIGGER0_CONFIG_REG -#define PTP_TRIGGER0_CONFIG_REG_ADDRESS 0x8400 -#define PTP_TRIGGER0_CONFIG_REG_NUM 1 -#define PTP_TRIGGER0_CONFIG_REG_INC 0x1 -#define PTP_TRIGGER0_CONFIG_REG_TYPE REG_TYPE_RW -#define PTP_TRIGGER0_CONFIG_REG_DEFAULT 0x0 - /*[field] STATUS*/ - #define PTP_TRIGGER0_CONFIG_REG_STATUS - #define PTP_TRIGGER0_CONFIG_REG_STATUS_OFFSET 0 - #define PTP_TRIGGER0_CONFIG_REG_STATUS_LEN 1 - #define PTP_TRIGGER0_CONFIG_REG_STATUS_DEFAULT 0x0 - /*[field] FORCE_EN*/ - #define PTP_TRIGGER0_CONFIG_REG_FORCE_EN - #define PTP_TRIGGER0_CONFIG_REG_FORCE_EN_OFFSET 1 - #define PTP_TRIGGER0_CONFIG_REG_FORCE_EN_LEN 1 - #define PTP_TRIGGER0_CONFIG_REG_FORCE_EN_DEFAULT 0x0 - /*[field] FORCE_VALUE*/ - #define PTP_TRIGGER0_CONFIG_REG_FORCE_VALUE - #define PTP_TRIGGER0_CONFIG_REG_FORCE_VALUE_OFFSET 2 - #define PTP_TRIGGER0_CONFIG_REG_FORCE_VALUE_LEN 1 - #define PTP_TRIGGER0_CONFIG_REG_FORCE_VALUE_DEFAULT 0x0 - /*[field] PATTERN*/ - #define PTP_TRIGGER0_CONFIG_REG_PATTERN - #define PTP_TRIGGER0_CONFIG_REG_PATTERN_OFFSET 3 - #define PTP_TRIGGER0_CONFIG_REG_PATTERN_LEN 3 - #define PTP_TRIGGER0_CONFIG_REG_PATTERN_DEFAULT 0x0 - /*[field] IF_LATE*/ - #define PTP_TRIGGER0_CONFIG_REG_IF_LATE - #define PTP_TRIGGER0_CONFIG_REG_IF_LATE_OFFSET 6 - #define PTP_TRIGGER0_CONFIG_REG_IF_LATE_LEN 1 - #define PTP_TRIGGER0_CONFIG_REG_IF_LATE_DEFAULT 0x0 - /*[field] NOTIFY*/ - #define PTP_TRIGGER0_CONFIG_REG_NOTIFY - #define PTP_TRIGGER0_CONFIG_REG_NOTIFY_OFFSET 7 - #define PTP_TRIGGER0_CONFIG_REG_NOTIFY_LEN 1 - #define PTP_TRIGGER0_CONFIG_REG_NOTIFY_DEFAULT 0x0 - /*[field] SETTING*/ - #define PTP_TRIGGER0_CONFIG_REG_SETTING - #define PTP_TRIGGER0_CONFIG_REG_SETTING_OFFSET 8 - #define PTP_TRIGGER0_CONFIG_REG_SETTING_LEN 1 - #define PTP_TRIGGER0_CONFIG_REG_SETTING_DEFAULT 0x0 - -struct ptp_trigger0_config_reg { - a_uint16_t status:1; - a_uint16_t force_en:1; - a_uint16_t force_value:1; - a_uint16_t pattern:3; - a_uint16_t if_late:1; - a_uint16_t notify:1; - a_uint16_t setting:1; -}; - -union ptp_trigger0_config_reg_u { - a_uint32_t val; - struct ptp_trigger0_config_reg bf; -}; - -/*[register] PTP_TRIGGER0_STATUS_REG*/ -#define PTP_TRIGGER0_STATUS_REG -#define PTP_TRIGGER0_STATUS_REG_ADDRESS 0x8401 -#define PTP_TRIGGER0_STATUS_REG_NUM 1 -#define PTP_TRIGGER0_STATUS_REG_INC 0x1 -#define PTP_TRIGGER0_STATUS_REG_TYPE REG_TYPE_RW -#define PTP_TRIGGER0_STATUS_REG_DEFAULT 0x0 - /*[field] FINISHED*/ - #define PTP_TRIGGER0_STATUS_REG_FINISHED - #define PTP_TRIGGER0_STATUS_REG_FINISHED_OFFSET 0 - #define PTP_TRIGGER0_STATUS_REG_FINISHED_LEN 1 - #define PTP_TRIGGER0_STATUS_REG_FINISHED_DEFAULT 0x0 - /*[field] ACTIVE*/ - #define PTP_TRIGGER0_STATUS_REG_ACTIVE - #define PTP_TRIGGER0_STATUS_REG_ACTIVE_OFFSET 1 - #define PTP_TRIGGER0_STATUS_REG_ACTIVE_LEN 1 - #define PTP_TRIGGER0_STATUS_REG_ACTIVE_DEFAULT 0x0 - /*[field] ERROR*/ - #define PTP_TRIGGER0_STATUS_REG_ERROR - #define PTP_TRIGGER0_STATUS_REG_ERROR_OFFSET 2 - #define PTP_TRIGGER0_STATUS_REG_ERROR_LEN 2 - #define PTP_TRIGGER0_STATUS_REG_ERROR_DEFAULT 0x0 - -struct ptp_trigger0_status_reg { - a_uint16_t finished:1; - a_uint16_t active:1; - a_uint16_t error:2; -}; - -union ptp_trigger0_status_reg_u { - a_uint32_t val; - struct ptp_trigger0_status_reg bf; -}; - -/*[register] PTP_TRIGGER1_CONFIG_REG*/ -#define PTP_TRIGGER1_CONFIG_REG -#define PTP_TRIGGER1_CONFIG_REG_ADDRESS 0x8402 -#define PTP_TRIGGER1_CONFIG_REG_NUM 1 -#define PTP_TRIGGER1_CONFIG_REG_INC 0x1 -#define PTP_TRIGGER1_CONFIG_REG_TYPE REG_TYPE_RW -#define PTP_TRIGGER1_CONFIG_REG_DEFAULT 0x0 - /*[field] STATUS*/ - #define PTP_TRIGGER1_CONFIG_REG_STATUS - #define PTP_TRIGGER1_CONFIG_REG_STATUS_OFFSET 0 - #define PTP_TRIGGER1_CONFIG_REG_STATUS_LEN 1 - #define PTP_TRIGGER1_CONFIG_REG_STATUS_DEFAULT 0x0 - /*[field] FORCE_EN*/ - #define PTP_TRIGGER1_CONFIG_REG_FORCE_EN - #define PTP_TRIGGER1_CONFIG_REG_FORCE_EN_OFFSET 1 - #define PTP_TRIGGER1_CONFIG_REG_FORCE_EN_LEN 1 - #define PTP_TRIGGER1_CONFIG_REG_FORCE_EN_DEFAULT 0x0 - /*[field] FORCE_VALUE*/ - #define PTP_TRIGGER1_CONFIG_REG_FORCE_VALUE - #define PTP_TRIGGER1_CONFIG_REG_FORCE_VALUE_OFFSET 2 - #define PTP_TRIGGER1_CONFIG_REG_FORCE_VALUE_LEN 1 - #define PTP_TRIGGER1_CONFIG_REG_FORCE_VALUE_DEFAULT 0x0 - /*[field] PATTERN*/ - #define PTP_TRIGGER1_CONFIG_REG_PATTERN - #define PTP_TRIGGER1_CONFIG_REG_PATTERN_OFFSET 3 - #define PTP_TRIGGER1_CONFIG_REG_PATTERN_LEN 3 - #define PTP_TRIGGER1_CONFIG_REG_PATTERN_DEFAULT 0x0 - /*[field] IF_LATE*/ - #define PTP_TRIGGER1_CONFIG_REG_IF_LATE - #define PTP_TRIGGER1_CONFIG_REG_IF_LATE_OFFSET 6 - #define PTP_TRIGGER1_CONFIG_REG_IF_LATE_LEN 1 - #define PTP_TRIGGER1_CONFIG_REG_IF_LATE_DEFAULT 0x0 - /*[field] NOTIFY*/ - #define PTP_TRIGGER1_CONFIG_REG_NOTIFY - #define PTP_TRIGGER1_CONFIG_REG_NOTIFY_OFFSET 7 - #define PTP_TRIGGER1_CONFIG_REG_NOTIFY_LEN 1 - #define PTP_TRIGGER1_CONFIG_REG_NOTIFY_DEFAULT 0x0 - /*[field] SETTING*/ - #define PTP_TRIGGER1_CONFIG_REG_SETTING - #define PTP_TRIGGER1_CONFIG_REG_SETTING_OFFSET 8 - #define PTP_TRIGGER1_CONFIG_REG_SETTING_LEN 1 - #define PTP_TRIGGER1_CONFIG_REG_SETTING_DEFAULT 0x0 - -struct ptp_trigger1_config_reg { - a_uint16_t status:1; - a_uint16_t force_en:1; - a_uint16_t force_value:1; - a_uint16_t pattern:3; - a_uint16_t if_late:1; - a_uint16_t notify:1; - a_uint16_t setting:1; -}; - -union ptp_trigger1_config_reg_u { - a_uint32_t val; - struct ptp_trigger1_config_reg bf; -}; - -/*[register] PTP_TRIGGER1_STATUS_REG*/ -#define PTP_TRIGGER1_STATUS_REG -#define PTP_TRIGGER1_STATUS_REG_ADDRESS 0x8403 -#define PTP_TRIGGER1_STATUS_REG_NUM 1 -#define PTP_TRIGGER1_STATUS_REG_INC 0x1 -#define PTP_TRIGGER1_STATUS_REG_TYPE REG_TYPE_RW -#define PTP_TRIGGER1_STATUS_REG_DEFAULT 0x0 - /*[field] FINISHED*/ - #define PTP_TRIGGER1_STATUS_REG_FINISHED - #define PTP_TRIGGER1_STATUS_REG_FINISHED_OFFSET 0 - #define PTP_TRIGGER1_STATUS_REG_FINISHED_LEN 1 - #define PTP_TRIGGER1_STATUS_REG_FINISHED_DEFAULT 0x0 - /*[field] ACTIVE*/ - #define PTP_TRIGGER1_STATUS_REG_ACTIVE - #define PTP_TRIGGER1_STATUS_REG_ACTIVE_OFFSET 1 - #define PTP_TRIGGER1_STATUS_REG_ACTIVE_LEN 1 - #define PTP_TRIGGER1_STATUS_REG_ACTIVE_DEFAULT 0x0 - /*[field] ERROR*/ - #define PTP_TRIGGER1_STATUS_REG_ERROR - #define PTP_TRIGGER1_STATUS_REG_ERROR_OFFSET 2 - #define PTP_TRIGGER1_STATUS_REG_ERROR_LEN 2 - #define PTP_TRIGGER1_STATUS_REG_ERROR_DEFAULT 0x0 - -struct ptp_trigger1_status_reg { - a_uint16_t finished:1; - a_uint16_t active:1; - a_uint16_t error:2; -}; - -union ptp_trigger1_status_reg_u { - a_uint32_t val; - struct ptp_trigger1_status_reg bf; -}; - -/*[register] PTP_TRIGGER0_TIMESTAMP0_REG*/ -#define PTP_TRIGGER0_TIMESTAMP0_REG -#define PTP_TRIGGER0_TIMESTAMP0_REG_ADDRESS 0x8404 -#define PTP_TRIGGER0_TIMESTAMP0_REG_NUM 1 -#define PTP_TRIGGER0_TIMESTAMP0_REG_INC 0x1 -#define PTP_TRIGGER0_TIMESTAMP0_REG_TYPE REG_TYPE_RW -#define PTP_TRIGGER0_TIMESTAMP0_REG_DEFAULT 0x0 - /*[field] TS_SEC*/ - #define PTP_TRIGGER0_TIMESTAMP0_REG_TS_SEC - #define PTP_TRIGGER0_TIMESTAMP0_REG_TS_SEC_OFFSET 0 - #define PTP_TRIGGER0_TIMESTAMP0_REG_TS_SEC_LEN 16 - #define PTP_TRIGGER0_TIMESTAMP0_REG_TS_SEC_DEFAULT 0x0 - -struct ptp_trigger0_timestamp0_reg { - a_uint16_t ts_sec:16; -}; - -union ptp_trigger0_timestamp0_reg_u { - a_uint32_t val; - struct ptp_trigger0_timestamp0_reg bf; -}; - -/*[register] PTP_TRIGGER0_TIMESTAMP1_REG*/ -#define PTP_TRIGGER0_TIMESTAMP1_REG -#define PTP_TRIGGER0_TIMESTAMP1_REG_ADDRESS 0x8405 -#define PTP_TRIGGER0_TIMESTAMP1_REG_NUM 1 -#define PTP_TRIGGER0_TIMESTAMP1_REG_INC 0x1 -#define PTP_TRIGGER0_TIMESTAMP1_REG_TYPE REG_TYPE_RW -#define PTP_TRIGGER0_TIMESTAMP1_REG_DEFAULT 0x0 - /*[field] TS_SEC*/ - #define PTP_TRIGGER0_TIMESTAMP1_REG_TS_SEC - #define PTP_TRIGGER0_TIMESTAMP1_REG_TS_SEC_OFFSET 0 - #define PTP_TRIGGER0_TIMESTAMP1_REG_TS_SEC_LEN 16 - #define PTP_TRIGGER0_TIMESTAMP1_REG_TS_SEC_DEFAULT 0x0 - -struct ptp_trigger0_timestamp1_reg { - a_uint16_t ts_sec:16; -}; - -union ptp_trigger0_timestamp1_reg_u { - a_uint32_t val; - struct ptp_trigger0_timestamp1_reg bf; -}; - -/*[register] PTP_TRIGGER0_TIMESTAMP2_REG*/ -#define PTP_TRIGGER0_TIMESTAMP2_REG -#define PTP_TRIGGER0_TIMESTAMP2_REG_ADDRESS 0x8406 -#define PTP_TRIGGER0_TIMESTAMP2_REG_NUM 1 -#define PTP_TRIGGER0_TIMESTAMP2_REG_INC 0x1 -#define PTP_TRIGGER0_TIMESTAMP2_REG_TYPE REG_TYPE_RW -#define PTP_TRIGGER0_TIMESTAMP2_REG_DEFAULT 0x0 - /*[field] TS_SEC*/ - #define PTP_TRIGGER0_TIMESTAMP2_REG_TS_SEC - #define PTP_TRIGGER0_TIMESTAMP2_REG_TS_SEC_OFFSET 0 - #define PTP_TRIGGER0_TIMESTAMP2_REG_TS_SEC_LEN 16 - #define PTP_TRIGGER0_TIMESTAMP2_REG_TS_SEC_DEFAULT 0x0 - -struct ptp_trigger0_timestamp2_reg { - a_uint16_t ts_sec:16; -}; - -union ptp_trigger0_timestamp2_reg_u { - a_uint32_t val; - struct ptp_trigger0_timestamp2_reg bf; -}; - -/*[register] PTP_TRIGGER0_TIMESTAMP3_REG*/ -#define PTP_TRIGGER0_TIMESTAMP3_REG -#define PTP_TRIGGER0_TIMESTAMP3_REG_ADDRESS 0x8407 -#define PTP_TRIGGER0_TIMESTAMP3_REG_NUM 1 -#define PTP_TRIGGER0_TIMESTAMP3_REG_INC 0x1 -#define PTP_TRIGGER0_TIMESTAMP3_REG_TYPE REG_TYPE_RW -#define PTP_TRIGGER0_TIMESTAMP3_REG_DEFAULT 0x0 - /*[field] TS_NSEC*/ - #define PTP_TRIGGER0_TIMESTAMP3_REG_TS_NSEC - #define PTP_TRIGGER0_TIMESTAMP3_REG_TS_NSEC_OFFSET 0 - #define PTP_TRIGGER0_TIMESTAMP3_REG_TS_NSEC_LEN 16 - #define PTP_TRIGGER0_TIMESTAMP3_REG_TS_NSEC_DEFAULT 0x0 - -struct ptp_trigger0_timestamp3_reg { - a_uint16_t ts_nsec:16; -}; - -union ptp_trigger0_timestamp3_reg_u { - a_uint32_t val; - struct ptp_trigger0_timestamp3_reg bf; -}; - -/*[register] PTP_TRIGGER0_TIMESTAMP4_REG*/ -#define PTP_TRIGGER0_TIMESTAMP4_REG -#define PTP_TRIGGER0_TIMESTAMP4_REG_ADDRESS 0x8408 -#define PTP_TRIGGER0_TIMESTAMP4_REG_NUM 1 -#define PTP_TRIGGER0_TIMESTAMP4_REG_INC 0x1 -#define PTP_TRIGGER0_TIMESTAMP4_REG_TYPE REG_TYPE_RW -#define PTP_TRIGGER0_TIMESTAMP4_REG_DEFAULT 0x0 - /*[field] TS_NSEC*/ - #define PTP_TRIGGER0_TIMESTAMP4_REG_TS_NSEC - #define PTP_TRIGGER0_TIMESTAMP4_REG_TS_NSEC_OFFSET 0 - #define PTP_TRIGGER0_TIMESTAMP4_REG_TS_NSEC_LEN 16 - #define PTP_TRIGGER0_TIMESTAMP4_REG_TS_NSEC_DEFAULT 0x0 - -struct ptp_trigger0_timestamp4_reg { - a_uint16_t ts_nsec:16; -}; - -union ptp_trigger0_timestamp4_reg_u { - a_uint32_t val; - struct ptp_trigger0_timestamp4_reg bf; -}; - -/*[register] PTP_TRIGGER1_TIMESTAMP0_REG*/ -#define PTP_TRIGGER1_TIMESTAMP0_REG -#define PTP_TRIGGER1_TIMESTAMP0_REG_ADDRESS 0x8409 -#define PTP_TRIGGER1_TIMESTAMP0_REG_NUM 1 -#define PTP_TRIGGER1_TIMESTAMP0_REG_INC 0x1 -#define PTP_TRIGGER1_TIMESTAMP0_REG_TYPE REG_TYPE_RW -#define PTP_TRIGGER1_TIMESTAMP0_REG_DEFAULT 0x0 - /*[field] TS_SEC*/ - #define PTP_TRIGGER1_TIMESTAMP0_REG_TS_SEC - #define PTP_TRIGGER1_TIMESTAMP0_REG_TS_SEC_OFFSET 0 - #define PTP_TRIGGER1_TIMESTAMP0_REG_TS_SEC_LEN 16 - #define PTP_TRIGGER1_TIMESTAMP0_REG_TS_SEC_DEFAULT 0x0 - -struct ptp_trigger1_timestamp0_reg { - a_uint16_t ts_sec:16; -}; - -union ptp_trigger1_timestamp0_reg_u { - a_uint32_t val; - struct ptp_trigger1_timestamp0_reg bf; -}; - -/*[register] PTP_TRIGGER1_TIMESTAMP1_REG*/ -#define PTP_TRIGGER1_TIMESTAMP1_REG -#define PTP_TRIGGER1_TIMESTAMP1_REG_ADDRESS 0x840a -#define PTP_TRIGGER1_TIMESTAMP1_REG_NUM 1 -#define PTP_TRIGGER1_TIMESTAMP1_REG_INC 0x1 -#define PTP_TRIGGER1_TIMESTAMP1_REG_TYPE REG_TYPE_RW -#define PTP_TRIGGER1_TIMESTAMP1_REG_DEFAULT 0x0 - /*[field] TS_SEC*/ - #define PTP_TRIGGER1_TIMESTAMP1_REG_TS_SEC - #define PTP_TRIGGER1_TIMESTAMP1_REG_TS_SEC_OFFSET 0 - #define PTP_TRIGGER1_TIMESTAMP1_REG_TS_SEC_LEN 16 - #define PTP_TRIGGER1_TIMESTAMP1_REG_TS_SEC_DEFAULT 0x0 - -struct ptp_trigger1_timestamp1_reg { - a_uint16_t ts_sec:16; -}; - -union ptp_trigger1_timestamp1_reg_u { - a_uint32_t val; - struct ptp_trigger1_timestamp1_reg bf; -}; - -/*[register] PTP_TRIGGER1_TIMESTAMP2_REG*/ -#define PTP_TRIGGER1_TIMESTAMP2_REG -#define PTP_TRIGGER1_TIMESTAMP2_REG_ADDRESS 0x840b -#define PTP_TRIGGER1_TIMESTAMP2_REG_NUM 1 -#define PTP_TRIGGER1_TIMESTAMP2_REG_INC 0x1 -#define PTP_TRIGGER1_TIMESTAMP2_REG_TYPE REG_TYPE_RW -#define PTP_TRIGGER1_TIMESTAMP2_REG_DEFAULT 0x0 - /*[field] TS_SEC*/ - #define PTP_TRIGGER1_TIMESTAMP2_REG_TS_SEC - #define PTP_TRIGGER1_TIMESTAMP2_REG_TS_SEC_OFFSET 0 - #define PTP_TRIGGER1_TIMESTAMP2_REG_TS_SEC_LEN 16 - #define PTP_TRIGGER1_TIMESTAMP2_REG_TS_SEC_DEFAULT 0x0 - -struct ptp_trigger1_timestamp2_reg { - a_uint16_t ts_sec:16; -}; - -union ptp_trigger1_timestamp2_reg_u { - a_uint32_t val; - struct ptp_trigger1_timestamp2_reg bf; -}; - -/*[register] PTP_TRIGGER1_TIMESTAMP3_REG*/ -#define PTP_TRIGGER1_TIMESTAMP3_REG -#define PTP_TRIGGER1_TIMESTAMP3_REG_ADDRESS 0x840c -#define PTP_TRIGGER1_TIMESTAMP3_REG_NUM 1 -#define PTP_TRIGGER1_TIMESTAMP3_REG_INC 0x1 -#define PTP_TRIGGER1_TIMESTAMP3_REG_TYPE REG_TYPE_RW -#define PTP_TRIGGER1_TIMESTAMP3_REG_DEFAULT 0x0 - /*[field] TS_NSEC*/ - #define PTP_TRIGGER1_TIMESTAMP3_REG_TS_NSEC - #define PTP_TRIGGER1_TIMESTAMP3_REG_TS_NSEC_OFFSET 0 - #define PTP_TRIGGER1_TIMESTAMP3_REG_TS_NSEC_LEN 16 - #define PTP_TRIGGER1_TIMESTAMP3_REG_TS_NSEC_DEFAULT 0x0 - -struct ptp_trigger1_timestamp3_reg { - a_uint16_t ts_nsec:16; -}; - -union ptp_trigger1_timestamp3_reg_u { - a_uint32_t val; - struct ptp_trigger1_timestamp3_reg bf; -}; - -/*[register] PTP_TRIGGER1_TIMESTAMP4_REG*/ -#define PTP_TRIGGER1_TIMESTAMP4_REG -#define PTP_TRIGGER1_TIMESTAMP4_REG_ADDRESS 0x840d -#define PTP_TRIGGER1_TIMESTAMP4_REG_NUM 1 -#define PTP_TRIGGER1_TIMESTAMP4_REG_INC 0x1 -#define PTP_TRIGGER1_TIMESTAMP4_REG_TYPE REG_TYPE_RW -#define PTP_TRIGGER1_TIMESTAMP4_REG_DEFAULT 0x0 - /*[field] TS_NSEC*/ - #define PTP_TRIGGER1_TIMESTAMP4_REG_TS_NSEC - #define PTP_TRIGGER1_TIMESTAMP4_REG_TS_NSEC_OFFSET 0 - #define PTP_TRIGGER1_TIMESTAMP4_REG_TS_NSEC_LEN 16 - #define PTP_TRIGGER1_TIMESTAMP4_REG_TS_NSEC_DEFAULT 0x0 - -struct ptp_trigger1_timestamp4_reg { - a_uint16_t ts_nsec:16; -}; - -union ptp_trigger1_timestamp4_reg_u { - a_uint32_t val; - struct ptp_trigger1_timestamp4_reg bf; -}; - -/*[register] PTP_EVENT0_CONFIG_REG*/ -#define PTP_EVENT0_CONFIG_REG -#define PTP_EVENT0_CONFIG_REG_ADDRESS 0x840e -#define PTP_EVENT0_CONFIG_REG_NUM 1 -#define PTP_EVENT0_CONFIG_REG_INC 0x1 -#define PTP_EVENT0_CONFIG_REG_TYPE REG_TYPE_RW -#define PTP_EVENT0_CONFIG_REG_DEFAULT 0x0 - /*[field] CLEAR_STAT*/ - #define PTP_EVENT0_CONFIG_REG_CLEAR_STAT - #define PTP_EVENT0_CONFIG_REG_CLEAR_STAT_OFFSET 0 - #define PTP_EVENT0_CONFIG_REG_CLEAR_STAT_LEN 1 - #define PTP_EVENT0_CONFIG_REG_CLEAR_STAT_DEFAULT 0x0 - /*[field] NOTIFY*/ - #define PTP_EVENT0_CONFIG_REG_NOTIFY - #define PTP_EVENT0_CONFIG_REG_NOTIFY_OFFSET 1 - #define PTP_EVENT0_CONFIG_REG_NOTIFY_LEN 1 - #define PTP_EVENT0_CONFIG_REG_NOTIFY_DEFAULT 0x0 - /*[field] SINGLE_CAP*/ - #define PTP_EVENT0_CONFIG_REG_SINGLE_CAP - #define PTP_EVENT0_CONFIG_REG_SINGLE_CAP_OFFSET 2 - #define PTP_EVENT0_CONFIG_REG_SINGLE_CAP_LEN 1 - #define PTP_EVENT0_CONFIG_REG_SINGLE_CAP_DEFAULT 0x0 - /*[field] FALL_EN*/ - #define PTP_EVENT0_CONFIG_REG_FALL_EN - #define PTP_EVENT0_CONFIG_REG_FALL_EN_OFFSET 3 - #define PTP_EVENT0_CONFIG_REG_FALL_EN_LEN 1 - #define PTP_EVENT0_CONFIG_REG_FALL_EN_DEFAULT 0x0 - /*[field] RISE_EN*/ - #define PTP_EVENT0_CONFIG_REG_RISE_EN - #define PTP_EVENT0_CONFIG_REG_RISE_EN_OFFSET 4 - #define PTP_EVENT0_CONFIG_REG_RISE_EN_LEN 1 - #define PTP_EVENT0_CONFIG_REG_RISE_EN_DEFAULT 0x0 - -struct ptp_event0_config_reg { - a_uint16_t clear_stat:1; - a_uint16_t notify:1; - a_uint16_t single_cap:1; - a_uint16_t fall_en:1; - a_uint16_t rise_en:1; -}; - -union ptp_event0_config_reg_u { - a_uint32_t val; - struct ptp_event0_config_reg bf; -}; - -/*[register] PTP_EVENT0_STATUS_REG*/ -#define PTP_EVENT0_STATUS_REG -#define PTP_EVENT0_STATUS_REG_ADDRESS 0x840f -#define PTP_EVENT0_STATUS_REG_NUM 1 -#define PTP_EVENT0_STATUS_REG_INC 0x1 -#define PTP_EVENT0_STATUS_REG_TYPE REG_TYPE_RW -#define PTP_EVENT0_STATUS_REG_DEFAULT 0x0 - /*[field] DETECTED*/ - #define PTP_EVENT0_STATUS_REG_DETECTED - #define PTP_EVENT0_STATUS_REG_DETECTED_OFFSET 0 - #define PTP_EVENT0_STATUS_REG_DETECTED_LEN 1 - #define PTP_EVENT0_STATUS_REG_DETECTED_DEFAULT 0x0 - /*[field] DIR_DETECTED*/ - #define PTP_EVENT0_STATUS_REG_DIR_DETECTED - #define PTP_EVENT0_STATUS_REG_DIR_DETECTED_OFFSET 1 - #define PTP_EVENT0_STATUS_REG_DIR_DETECTED_LEN 1 - #define PTP_EVENT0_STATUS_REG_DIR_DETECTED_DEFAULT 0x0 - /*[field] MUL_EVENT*/ - #define PTP_EVENT0_STATUS_REG_MUL_EVENT - #define PTP_EVENT0_STATUS_REG_MUL_EVENT_OFFSET 2 - #define PTP_EVENT0_STATUS_REG_MUL_EVENT_LEN 1 - #define PTP_EVENT0_STATUS_REG_MUL_EVENT_DEFAULT 0x0 - /*[field] MISSED_COUNT*/ - #define PTP_EVENT0_STATUS_REG_MISSED_COUNT - #define PTP_EVENT0_STATUS_REG_MISSED_COUNT_OFFSET 3 - #define PTP_EVENT0_STATUS_REG_MISSED_COUNT_LEN 4 - #define PTP_EVENT0_STATUS_REG_MISSED_COUNT_DEFAULT 0x0 - -struct ptp_event0_status_reg { - a_uint16_t detected:1; - a_uint16_t dir_detected:1; - a_uint16_t mul_event:1; - a_uint16_t missed_count:4; -}; - -union ptp_event0_status_reg_u { - a_uint32_t val; - struct ptp_event0_status_reg bf; -}; - -/*[register] PTP_EVENT1_CONFIG_REG*/ -#define PTP_EVENT1_CONFIG_REG -#define PTP_EVENT1_CONFIG_REG_ADDRESS 0x8410 -#define PTP_EVENT1_CONFIG_REG_NUM 1 -#define PTP_EVENT1_CONFIG_REG_INC 0x1 -#define PTP_EVENT1_CONFIG_REG_TYPE REG_TYPE_RW -#define PTP_EVENT1_CONFIG_REG_DEFAULT 0x0 - /*[field] CLEAR_STAT*/ - #define PTP_EVENT1_CONFIG_REG_CLEAR_STAT - #define PTP_EVENT1_CONFIG_REG_CLEAR_STAT_OFFSET 0 - #define PTP_EVENT1_CONFIG_REG_CLEAR_STAT_LEN 1 - #define PTP_EVENT1_CONFIG_REG_CLEAR_STAT_DEFAULT 0x0 - /*[field] NOTIFY*/ - #define PTP_EVENT1_CONFIG_REG_NOTIFY - #define PTP_EVENT1_CONFIG_REG_NOTIFY_OFFSET 1 - #define PTP_EVENT1_CONFIG_REG_NOTIFY_LEN 1 - #define PTP_EVENT1_CONFIG_REG_NOTIFY_DEFAULT 0x0 - /*[field] SINGLE_CAP*/ - #define PTP_EVENT1_CONFIG_REG_SINGLE_CAP - #define PTP_EVENT1_CONFIG_REG_SINGLE_CAP_OFFSET 2 - #define PTP_EVENT1_CONFIG_REG_SINGLE_CAP_LEN 1 - #define PTP_EVENT1_CONFIG_REG_SINGLE_CAP_DEFAULT 0x0 - /*[field] FALL_EN*/ - #define PTP_EVENT1_CONFIG_REG_FALL_EN - #define PTP_EVENT1_CONFIG_REG_FALL_EN_OFFSET 3 - #define PTP_EVENT1_CONFIG_REG_FALL_EN_LEN 1 - #define PTP_EVENT1_CONFIG_REG_FALL_EN_DEFAULT 0x0 - /*[field] RISE_EN*/ - #define PTP_EVENT1_CONFIG_REG_RISE_EN - #define PTP_EVENT1_CONFIG_REG_RISE_EN_OFFSET 4 - #define PTP_EVENT1_CONFIG_REG_RISE_EN_LEN 1 - #define PTP_EVENT1_CONFIG_REG_RISE_EN_DEFAULT 0x0 - -struct ptp_event1_config_reg { - a_uint16_t clear_stat:1; - a_uint16_t notify:1; - a_uint16_t single_cap:1; - a_uint16_t fall_en:1; - a_uint16_t rise_en:1; -}; - -union ptp_event1_config_reg_u { - a_uint32_t val; - struct ptp_event1_config_reg bf; -}; - -/*[register] PTP_EVENT1_STATUS_REG*/ -#define PTP_EVENT1_STATUS_REG -#define PTP_EVENT1_STATUS_REG_ADDRESS 0x8411 -#define PTP_EVENT1_STATUS_REG_NUM 1 -#define PTP_EVENT1_STATUS_REG_INC 0x1 -#define PTP_EVENT1_STATUS_REG_TYPE REG_TYPE_RW -#define PTP_EVENT1_STATUS_REG_DEFAULT 0x0 - /*[field] DETECTED*/ - #define PTP_EVENT1_STATUS_REG_DETECTED - #define PTP_EVENT1_STATUS_REG_DETECTED_OFFSET 0 - #define PTP_EVENT1_STATUS_REG_DETECTED_LEN 1 - #define PTP_EVENT1_STATUS_REG_DETECTED_DEFAULT 0x0 - /*[field] DIR_DETECTED*/ - #define PTP_EVENT1_STATUS_REG_DIR_DETECTED - #define PTP_EVENT1_STATUS_REG_DIR_DETECTED_OFFSET 1 - #define PTP_EVENT1_STATUS_REG_DIR_DETECTED_LEN 1 - #define PTP_EVENT1_STATUS_REG_DIR_DETECTED_DEFAULT 0x0 - /*[field] MUL_EVENT*/ - #define PTP_EVENT1_STATUS_REG_MUL_EVENT - #define PTP_EVENT1_STATUS_REG_MUL_EVENT_OFFSET 2 - #define PTP_EVENT1_STATUS_REG_MUL_EVENT_LEN 1 - #define PTP_EVENT1_STATUS_REG_MUL_EVENT_DEFAULT 0x0 - /*[field] MISSED_COUNT*/ - #define PTP_EVENT1_STATUS_REG_MISSED_COUNT - #define PTP_EVENT1_STATUS_REG_MISSED_COUNT_OFFSET 3 - #define PTP_EVENT1_STATUS_REG_MISSED_COUNT_LEN 4 - #define PTP_EVENT1_STATUS_REG_MISSED_COUNT_DEFAULT 0x0 - -struct ptp_event1_status_reg { - a_uint16_t detected:1; - a_uint16_t dir_detected:1; - a_uint16_t mul_event:1; - a_uint16_t missed_count:4; -}; - -union ptp_event1_status_reg_u { - a_uint32_t val; - struct ptp_event1_status_reg bf; -}; - -/*[register] PTP_EVENT0_TIMESTAMP0_REG*/ -#define PTP_EVENT0_TIMESTAMP0_REG -#define PTP_EVENT0_TIMESTAMP0_REG_ADDRESS 0x8412 -#define PTP_EVENT0_TIMESTAMP0_REG_NUM 1 -#define PTP_EVENT0_TIMESTAMP0_REG_INC 0x1 -#define PTP_EVENT0_TIMESTAMP0_REG_TYPE REG_TYPE_RW -#define PTP_EVENT0_TIMESTAMP0_REG_DEFAULT 0x0 - /*[field] TS_NSEC*/ - #define PTP_EVENT0_TIMESTAMP0_REG_TS_NSEC - #define PTP_EVENT0_TIMESTAMP0_REG_TS_NSEC_OFFSET 0 - #define PTP_EVENT0_TIMESTAMP0_REG_TS_NSEC_LEN 16 - #define PTP_EVENT0_TIMESTAMP0_REG_TS_NSEC_DEFAULT 0x0 - -struct ptp_event0_timestamp0_reg { - a_uint16_t ts_nsec:16; -}; - -union ptp_event0_timestamp0_reg_u { - a_uint32_t val; - struct ptp_event0_timestamp0_reg bf; -}; - -/*[register] PTP_EVENT0_TIMESTAMP1_REG*/ -#define PTP_EVENT0_TIMESTAMP1_REG -#define PTP_EVENT0_TIMESTAMP1_REG_ADDRESS 0x8413 -#define PTP_EVENT0_TIMESTAMP1_REG_NUM 1 -#define PTP_EVENT0_TIMESTAMP1_REG_INC 0x1 -#define PTP_EVENT0_TIMESTAMP1_REG_TYPE REG_TYPE_RW -#define PTP_EVENT0_TIMESTAMP1_REG_DEFAULT 0x0 - /*[field] TS_NSEC*/ - #define PTP_EVENT0_TIMESTAMP1_REG_TS_NSEC - #define PTP_EVENT0_TIMESTAMP1_REG_TS_NSEC_OFFSET 0 - #define PTP_EVENT0_TIMESTAMP1_REG_TS_NSEC_LEN 16 - #define PTP_EVENT0_TIMESTAMP1_REG_TS_NSEC_DEFAULT 0x0 - -struct ptp_event0_timestamp1_reg { - a_uint16_t ts_nsec:16; -}; - -union ptp_event0_timestamp1_reg_u { - a_uint32_t val; - struct ptp_event0_timestamp1_reg bf; -}; - -/*[register] PTP_EVENT0_TIMESTAMP2_REG*/ -#define PTP_EVENT0_TIMESTAMP2_REG -#define PTP_EVENT0_TIMESTAMP2_REG_ADDRESS 0x8414 -#define PTP_EVENT0_TIMESTAMP2_REG_NUM 1 -#define PTP_EVENT0_TIMESTAMP2_REG_INC 0x1 -#define PTP_EVENT0_TIMESTAMP2_REG_TYPE REG_TYPE_RW -#define PTP_EVENT0_TIMESTAMP2_REG_DEFAULT 0x0 - /*[field] TS_NSEC*/ - #define PTP_EVENT0_TIMESTAMP2_REG_TS_NSEC - #define PTP_EVENT0_TIMESTAMP2_REG_TS_NSEC_OFFSET 0 - #define PTP_EVENT0_TIMESTAMP2_REG_TS_NSEC_LEN 16 - #define PTP_EVENT0_TIMESTAMP2_REG_TS_NSEC_DEFAULT 0x0 - -struct ptp_event0_timestamp2_reg { - a_uint16_t ts_nsec:16; -}; - -union ptp_event0_timestamp2_reg_u { - a_uint32_t val; - struct ptp_event0_timestamp2_reg bf; -}; - -/*[register] PTP_EVENT0_TIMESTAMP3_REG*/ -#define PTP_EVENT0_TIMESTAMP3_REG -#define PTP_EVENT0_TIMESTAMP3_REG_ADDRESS 0x8415 -#define PTP_EVENT0_TIMESTAMP3_REG_NUM 1 -#define PTP_EVENT0_TIMESTAMP3_REG_INC 0x1 -#define PTP_EVENT0_TIMESTAMP3_REG_TYPE REG_TYPE_RW -#define PTP_EVENT0_TIMESTAMP3_REG_DEFAULT 0x0 - /*[field] TS_NSEC*/ - #define PTP_EVENT0_TIMESTAMP3_REG_TS_NSEC - #define PTP_EVENT0_TIMESTAMP3_REG_TS_NSEC_OFFSET 0 - #define PTP_EVENT0_TIMESTAMP3_REG_TS_NSEC_LEN 16 - #define PTP_EVENT0_TIMESTAMP3_REG_TS_NSEC_DEFAULT 0x0 - -struct ptp_event0_timestamp3_reg { - a_uint16_t ts_nsec:16; -}; - -union ptp_event0_timestamp3_reg_u { - a_uint32_t val; - struct ptp_event0_timestamp3_reg bf; -}; - -/*[register] PTP_EVENT0_TIMESTAMP4_REG*/ -#define PTP_EVENT0_TIMESTAMP4_REG -#define PTP_EVENT0_TIMESTAMP4_REG_ADDRESS 0x8416 -#define PTP_EVENT0_TIMESTAMP4_REG_NUM 1 -#define PTP_EVENT0_TIMESTAMP4_REG_INC 0x1 -#define PTP_EVENT0_TIMESTAMP4_REG_TYPE REG_TYPE_RW -#define PTP_EVENT0_TIMESTAMP4_REG_DEFAULT 0x0 - /*[field] TS_NSEC*/ - #define PTP_EVENT0_TIMESTAMP4_REG_TS_NSEC - #define PTP_EVENT0_TIMESTAMP4_REG_TS_NSEC_OFFSET 0 - #define PTP_EVENT0_TIMESTAMP4_REG_TS_NSEC_LEN 16 - #define PTP_EVENT0_TIMESTAMP4_REG_TS_NSEC_DEFAULT 0x0 - -struct ptp_event0_timestamp4_reg { - a_uint16_t ts_nsec:16; -}; - -union ptp_event0_timestamp4_reg_u { - a_uint32_t val; - struct ptp_event0_timestamp4_reg bf; -}; - -/*[register] PTP_EVENT1_TIMESTAMP0_REG*/ -#define PTP_EVENT1_TIMESTAMP0_REG -#define PTP_EVENT1_TIMESTAMP0_REG_ADDRESS 0x8417 -#define PTP_EVENT1_TIMESTAMP0_REG_NUM 1 -#define PTP_EVENT1_TIMESTAMP0_REG_INC 0x1 -#define PTP_EVENT1_TIMESTAMP0_REG_TYPE REG_TYPE_RW -#define PTP_EVENT1_TIMESTAMP0_REG_DEFAULT 0x0 - /*[field] TS_NSEC*/ - #define PTP_EVENT1_TIMESTAMP0_REG_TS_NSEC - #define PTP_EVENT1_TIMESTAMP0_REG_TS_NSEC_OFFSET 0 - #define PTP_EVENT1_TIMESTAMP0_REG_TS_NSEC_LEN 16 - #define PTP_EVENT1_TIMESTAMP0_REG_TS_NSEC_DEFAULT 0x0 - -struct ptp_event1_timestamp0_reg { - a_uint16_t ts_nsec:16; -}; - -union ptp_event1_timestamp0_reg_u { - a_uint32_t val; - struct ptp_event1_timestamp0_reg bf; -}; - -/*[register] PTP_EVENT1_TIMESTAMP1_REG*/ -#define PTP_EVENT1_TIMESTAMP1_REG -#define PTP_EVENT1_TIMESTAMP1_REG_ADDRESS 0x8418 -#define PTP_EVENT1_TIMESTAMP1_REG_NUM 1 -#define PTP_EVENT1_TIMESTAMP1_REG_INC 0x1 -#define PTP_EVENT1_TIMESTAMP1_REG_TYPE REG_TYPE_RW -#define PTP_EVENT1_TIMESTAMP1_REG_DEFAULT 0x0 - /*[field] TS_NSEC*/ - #define PTP_EVENT1_TIMESTAMP1_REG_TS_NSEC - #define PTP_EVENT1_TIMESTAMP1_REG_TS_NSEC_OFFSET 0 - #define PTP_EVENT1_TIMESTAMP1_REG_TS_NSEC_LEN 16 - #define PTP_EVENT1_TIMESTAMP1_REG_TS_NSEC_DEFAULT 0x0 - -struct ptp_event1_timestamp1_reg { - a_uint16_t ts_nsec:16; -}; - -union ptp_event1_timestamp1_reg_u { - a_uint32_t val; - struct ptp_event1_timestamp1_reg bf; -}; - -/*[register] PTP_EVENT1_TIMESTAMP2_REG*/ -#define PTP_EVENT1_TIMESTAMP2_REG -#define PTP_EVENT1_TIMESTAMP2_REG_ADDRESS 0x8419 -#define PTP_EVENT1_TIMESTAMP2_REG_NUM 1 -#define PTP_EVENT1_TIMESTAMP2_REG_INC 0x1 -#define PTP_EVENT1_TIMESTAMP2_REG_TYPE REG_TYPE_RW -#define PTP_EVENT1_TIMESTAMP2_REG_DEFAULT 0x0 - /*[field] TS_NSEC*/ - #define PTP_EVENT1_TIMESTAMP2_REG_TS_NSEC - #define PTP_EVENT1_TIMESTAMP2_REG_TS_NSEC_OFFSET 0 - #define PTP_EVENT1_TIMESTAMP2_REG_TS_NSEC_LEN 16 - #define PTP_EVENT1_TIMESTAMP2_REG_TS_NSEC_DEFAULT 0x0 - -struct ptp_event1_timestamp2_reg { - a_uint16_t ts_nsec:16; -}; - -union ptp_event1_timestamp2_reg_u { - a_uint32_t val; - struct ptp_event1_timestamp2_reg bf; -}; - -/*[register] PTP_EVENT1_TIMESTAMP3_REG*/ -#define PTP_EVENT1_TIMESTAMP3_REG -#define PTP_EVENT1_TIMESTAMP3_REG_ADDRESS 0x841a -#define PTP_EVENT1_TIMESTAMP3_REG_NUM 1 -#define PTP_EVENT1_TIMESTAMP3_REG_INC 0x4 -#define PTP_EVENT1_TIMESTAMP3_REG_TYPE REG_TYPE_RW -#define PTP_EVENT1_TIMESTAMP3_REG_DEFAULT 0x0 - /*[field] TS_NSEC*/ - #define PTP_EVENT1_TIMESTAMP3_REG_TS_NSEC - #define PTP_EVENT1_TIMESTAMP3_REG_TS_NSEC_OFFSET 0 - #define PTP_EVENT1_TIMESTAMP3_REG_TS_NSEC_LEN 16 - #define PTP_EVENT1_TIMESTAMP3_REG_TS_NSEC_DEFAULT 0x0 - -struct ptp_event1_timestamp3_reg { - a_uint16_t ts_nsec:16; -}; - -union ptp_event1_timestamp3_reg_u { - a_uint32_t val; - struct ptp_event1_timestamp3_reg bf; -}; - -/*[register] PTP_EVENT1_TIMESTAMP4_REG*/ -#define PTP_EVENT1_TIMESTAMP4_REG -#define PTP_EVENT1_TIMESTAMP4_REG_ADDRESS 0x841b -#define PTP_EVENT1_TIMESTAMP4_REG_NUM 1 -#define PTP_EVENT1_TIMESTAMP4_REG_INC 0x1 -#define PTP_EVENT1_TIMESTAMP4_REG_TYPE REG_TYPE_RW -#define PTP_EVENT1_TIMESTAMP4_REG_DEFAULT 0x0 - /*[field] TS_NSEC*/ - #define PTP_EVENT1_TIMESTAMP4_REG_TS_NSEC - #define PTP_EVENT1_TIMESTAMP4_REG_TS_NSEC_OFFSET 0 - #define PTP_EVENT1_TIMESTAMP4_REG_TS_NSEC_LEN 16 - #define PTP_EVENT1_TIMESTAMP4_REG_TS_NSEC_DEFAULT 0x0 - -struct ptp_event1_timestamp4_reg { - a_uint16_t ts_nsec:16; -}; - -union ptp_event1_timestamp4_reg_u { - a_uint32_t val; - struct ptp_event1_timestamp4_reg bf; -}; - -/*[register] PTP_RX_SEQID1_REG*/ -#define PTP_RX_SEQID1_REG -#define PTP_RX_SEQID1_REG_ADDRESS 0x8500 -#define PTP_RX_SEQID1_REG_NUM 1 -#define PTP_RX_SEQID1_REG_INC 0x1 -#define PTP_RX_SEQID1_REG_TYPE REG_TYPE_RW -#define PTP_RX_SEQID1_REG_DEFAULT 0x0 - /*[field] RX_SEQID*/ - #define PTP_RX_SEQID1_REG_RX_SEQID - #define PTP_RX_SEQID1_REG_RX_SEQID_OFFSET 0 - #define PTP_RX_SEQID1_REG_RX_SEQID_LEN 16 - #define PTP_RX_SEQID1_REG_RX_SEQID_DEFAULT 0x0 - -struct ptp_rx_seqid1_reg { - a_uint16_t rx_seqid:16; -}; - -union ptp_rx_seqid1_reg_u { - a_uint32_t val; - struct ptp_rx_seqid1_reg bf; -}; - -/*[register] PTP_RX_PORTID1_0_REG*/ -#define PTP_RX_PORTID1_0_REG -#define PTP_RX_PORTID1_0_REG_ADDRESS 0x8501 -#define PTP_RX_PORTID1_0_REG_NUM 1 -#define PTP_RX_PORTID1_0_REG_INC 0x1 -#define PTP_RX_PORTID1_0_REG_TYPE REG_TYPE_RW -#define PTP_RX_PORTID1_0_REG_DEFAULT 0x0 - /*[field] RX_PORTID*/ - #define PTP_RX_PORTID1_0_REG_RX_PORTID - #define PTP_RX_PORTID1_0_REG_RX_PORTID_OFFSET 0 - #define PTP_RX_PORTID1_0_REG_RX_PORTID_LEN 16 - #define PTP_RX_PORTID1_0_REG_RX_PORTID_DEFAULT 0x0 - -struct ptp_rx_portid1_0_reg { - a_uint16_t rx_portid:16; -}; - -union ptp_rx_portid1_0_reg_u { - a_uint32_t val; - struct ptp_rx_portid1_0_reg bf; -}; - -/*[register] PTP_RX_PORTID1_1_REG*/ -#define PTP_RX_PORTID1_1_REG -#define PTP_RX_PORTID1_1_REG_ADDRESS 0x8502 -#define PTP_RX_PORTID1_1_REG_NUM 1 -#define PTP_RX_PORTID1_1_REG_INC 0x1 -#define PTP_RX_PORTID1_1_REG_TYPE REG_TYPE_RW -#define PTP_RX_PORTID1_1_REG_DEFAULT 0x0 - /*[field] RX_PORTID*/ - #define PTP_RX_PORTID1_1_REG_RX_PORTID - #define PTP_RX_PORTID1_1_REG_RX_PORTID_OFFSET 0 - #define PTP_RX_PORTID1_1_REG_RX_PORTID_LEN 16 - #define PTP_RX_PORTID1_1_REG_RX_PORTID_DEFAULT 0x0 - -struct ptp_rx_portid1_1_reg { - a_uint16_t rx_portid:16; -}; - -union ptp_rx_portid1_1_reg_u { - a_uint32_t val; - struct ptp_rx_portid1_1_reg bf; -}; - -/*[register] PTP_RX_PORTID1_2_REG*/ -#define PTP_RX_PORTID1_2_REG -#define PTP_RX_PORTID1_2_REG_ADDRESS 0x8503 -#define PTP_RX_PORTID1_2_REG_NUM 1 -#define PTP_RX_PORTID1_2_REG_INC 0x1 -#define PTP_RX_PORTID1_2_REG_TYPE REG_TYPE_RW -#define PTP_RX_PORTID1_2_REG_DEFAULT 0x0 - /*[field] RX_PORTID*/ - #define PTP_RX_PORTID1_2_REG_RX_PORTID - #define PTP_RX_PORTID1_2_REG_RX_PORTID_OFFSET 0 - #define PTP_RX_PORTID1_2_REG_RX_PORTID_LEN 16 - #define PTP_RX_PORTID1_2_REG_RX_PORTID_DEFAULT 0x0 - -struct ptp_rx_portid1_2_reg { - a_uint16_t rx_portid:16; -}; - -union ptp_rx_portid1_2_reg_u { - a_uint32_t val; - struct ptp_rx_portid1_2_reg bf; -}; - -/*[register] PTP_RX_PORTID1_3_REG*/ -#define PTP_RX_PORTID1_3_REG -#define PTP_RX_PORTID1_3_REG_ADDRESS 0x8504 -#define PTP_RX_PORTID1_3_REG_NUM 1 -#define PTP_RX_PORTID1_3_REG_INC 0x1 -#define PTP_RX_PORTID1_3_REG_TYPE REG_TYPE_RW -#define PTP_RX_PORTID1_3_REG_DEFAULT 0x0 - /*[field] RX_PORTID*/ - #define PTP_RX_PORTID1_3_REG_RX_PORTID - #define PTP_RX_PORTID1_3_REG_RX_PORTID_OFFSET 0 - #define PTP_RX_PORTID1_3_REG_RX_PORTID_LEN 16 - #define PTP_RX_PORTID1_3_REG_RX_PORTID_DEFAULT 0x0 - -struct ptp_rx_portid1_3_reg { - a_uint16_t rx_portid:16; -}; - -union ptp_rx_portid1_3_reg_u { - a_uint32_t val; - struct ptp_rx_portid1_3_reg bf; -}; - -/*[register] PTP_RX_PORTID1_4_REG*/ -#define PTP_RX_PORTID1_4_REG -#define PTP_RX_PORTID1_4_REG_ADDRESS 0x8505 -#define PTP_RX_PORTID1_4_REG_NUM 1 -#define PTP_RX_PORTID1_4_REG_INC 0x1 -#define PTP_RX_PORTID1_4_REG_TYPE REG_TYPE_RW -#define PTP_RX_PORTID1_4_REG_DEFAULT 0x0 - /*[field] RX_PORTID*/ - #define PTP_RX_PORTID1_4_REG_RX_PORTID - #define PTP_RX_PORTID1_4_REG_RX_PORTID_OFFSET 0 - #define PTP_RX_PORTID1_4_REG_RX_PORTID_LEN 16 - #define PTP_RX_PORTID1_4_REG_RX_PORTID_DEFAULT 0x0 - -struct ptp_rx_portid1_4_reg { - a_uint16_t rx_portid:16; -}; - -union ptp_rx_portid1_4_reg_u { - a_uint32_t val; - struct ptp_rx_portid1_4_reg bf; -}; - -/*[register] PTP_RX_TS1_0_REG*/ -#define PTP_RX_TS1_0_REG -#define PTP_RX_TS1_0_REG_ADDRESS 0x8506 -#define PTP_RX_TS1_0_REG_NUM 1 -#define PTP_RX_TS1_0_REG_INC 0x1 -#define PTP_RX_TS1_0_REG_TYPE REG_TYPE_RW -#define PTP_RX_TS1_0_REG_DEFAULT 0x0 - /*[field] RX_TS_SEC*/ - #define PTP_RX_TS1_0_REG_RX_TS_SEC - #define PTP_RX_TS1_0_REG_RX_TS_SEC_OFFSET 0 - #define PTP_RX_TS1_0_REG_RX_TS_SEC_LEN 16 - #define PTP_RX_TS1_0_REG_RX_TS_SEC_DEFAULT 0x0 - -struct ptp_rx_ts1_0_reg { - a_uint16_t rx_ts_sec:16; -}; - -union ptp_rx_ts1_0_reg_u { - a_uint32_t val; - struct ptp_rx_ts1_0_reg bf; -}; - -/*[register] PTP_RX_TS1_1_REG*/ -#define PTP_RX_TS1_1_REG -#define PTP_RX_TS1_1_REG_ADDRESS 0x8507 -#define PTP_RX_TS1_1_REG_NUM 1 -#define PTP_RX_TS1_1_REG_INC 0x1 -#define PTP_RX_TS1_1_REG_TYPE REG_TYPE_RW -#define PTP_RX_TS1_1_REG_DEFAULT 0x0 - /*[field] RX_TS_SEC*/ - #define PTP_RX_TS1_1_REG_RX_TS_SEC - #define PTP_RX_TS1_1_REG_RX_TS_SEC_OFFSET 0 - #define PTP_RX_TS1_1_REG_RX_TS_SEC_LEN 16 - #define PTP_RX_TS1_1_REG_RX_TS_SEC_DEFAULT 0x0 - -struct ptp_rx_ts1_1_reg { - a_uint16_t rx_ts_sec:16; -}; - -union ptp_rx_ts1_1_reg_u { - a_uint32_t val; - struct ptp_rx_ts1_1_reg bf; -}; - -/*[register] PTP_RX_TS1_2_REG*/ -#define PTP_RX_TS1_2_REG -#define PTP_RX_TS1_2_REG_ADDRESS 0x8508 -#define PTP_RX_TS1_2_REG_NUM 1 -#define PTP_RX_TS1_2_REG_INC 0x1 -#define PTP_RX_TS1_2_REG_TYPE REG_TYPE_RW -#define PTP_RX_TS1_2_REG_DEFAULT 0x0 - /*[field] RX_TS_SEC*/ - #define PTP_RX_TS1_2_REG_RX_TS_SEC - #define PTP_RX_TS1_2_REG_RX_TS_SEC_OFFSET 0 - #define PTP_RX_TS1_2_REG_RX_TS_SEC_LEN 16 - #define PTP_RX_TS1_2_REG_RX_TS_SEC_DEFAULT 0x0 - -struct ptp_rx_ts1_2_reg { - a_uint16_t rx_ts_sec:16; -}; - -union ptp_rx_ts1_2_reg_u { - a_uint32_t val; - struct ptp_rx_ts1_2_reg bf; -}; - -/*[register] PTP_RX_TS1_3_REG*/ -#define PTP_RX_TS1_3_REG -#define PTP_RX_TS1_3_REG_ADDRESS 0x8509 -#define PTP_RX_TS1_3_REG_NUM 1 -#define PTP_RX_TS1_3_REG_INC 0x1 -#define PTP_RX_TS1_3_REG_TYPE REG_TYPE_RW -#define PTP_RX_TS1_3_REG_DEFAULT 0x0 - /*[field] RX_TS_NSEC*/ - #define PTP_RX_TS1_3_REG_RX_TS_NSEC - #define PTP_RX_TS1_3_REG_RX_TS_NSEC_OFFSET 0 - #define PTP_RX_TS1_3_REG_RX_TS_NSEC_LEN 16 - #define PTP_RX_TS1_3_REG_RX_TS_NSEC_DEFAULT 0x0 - -struct ptp_rx_ts1_3_reg { - a_uint16_t rx_ts_nsec:16; -}; - -union ptp_rx_ts1_3_reg_u { - a_uint32_t val; - struct ptp_rx_ts1_3_reg bf; -}; - -/*[register] PTP_RX_TS1_4_REG*/ -#define PTP_RX_TS1_4_REG -#define PTP_RX_TS1_4_REG_ADDRESS 0x850a -#define PTP_RX_TS1_4_REG_NUM 1 -#define PTP_RX_TS1_4_REG_INC 0x1 -#define PTP_RX_TS1_4_REG_TYPE REG_TYPE_RW -#define PTP_RX_TS1_4_REG_DEFAULT 0x0 - /*[field] RX_TS_NSEC*/ - #define PTP_RX_TS1_4_REG_RX_TS_NSEC - #define PTP_RX_TS1_4_REG_RX_TS_NSEC_OFFSET 0 - #define PTP_RX_TS1_4_REG_RX_TS_NSEC_LEN 16 - #define PTP_RX_TS1_4_REG_RX_TS_NSEC_DEFAULT 0x0 - -struct ptp_rx_ts1_4_reg { - a_uint16_t rx_ts_nsec:16; -}; - -union ptp_rx_ts1_4_reg_u { - a_uint32_t val; - struct ptp_rx_ts1_4_reg bf; -}; - -/*[register] PTP_RX_TS1_5_REG*/ -#define PTP_RX_TS1_5_REG -#define PTP_RX_TS1_5_REG_ADDRESS 0x850b -#define PTP_RX_TS1_5_REG_NUM 1 -#define PTP_RX_TS1_5_REG_INC 0x1 -#define PTP_RX_TS1_5_REG_TYPE REG_TYPE_RW -#define PTP_RX_TS1_5_REG_DEFAULT 0x0 - /*[field] RX_TS_NFSEC*/ - #define PTP_RX_TS1_5_REG_RX_TS_NFSEC - #define PTP_RX_TS1_5_REG_RX_TS_NFSEC_OFFSET 0 - #define PTP_RX_TS1_5_REG_RX_TS_NFSEC_LEN 12 - #define PTP_RX_TS1_5_REG_RX_TS_NFSEC_DEFAULT 0x0 - /*[field] RX_MSG_TYPE*/ - #define PTP_RX_TS1_5_REG_RX_MSG_TYPE - #define PTP_RX_TS1_5_REG_RX_MSG_TYPE_OFFSET 12 - #define PTP_RX_TS1_5_REG_RX_MSG_TYPE_LEN 4 - #define PTP_RX_TS1_5_REG_RX_MSG_TYPE_DEFAULT 0x0 - -struct ptp_rx_ts1_5_reg { - a_uint16_t rx_ts_nfsec:12; - a_uint16_t rx_msg_type:4; -}; - -union ptp_rx_ts1_5_reg_u { - a_uint32_t val; - struct ptp_rx_ts1_5_reg bf; -}; - -/*[register] PTP_RX_TS1_6_REG*/ -#define PTP_RX_TS1_6_REG -#define PTP_RX_TS1_6_REG_ADDRESS 0x850c -#define PTP_RX_TS1_6_REG_NUM 1 -#define PTP_RX_TS1_6_REG_INC 0x1 -#define PTP_RX_TS1_6_REG_TYPE REG_TYPE_RW -#define PTP_RX_TS1_6_REG_DEFAULT 0x0 - /*[field] RX_TS_NFSEC*/ - #define PTP_RX_TS1_6_REG_RX_TS_NFSEC - #define PTP_RX_TS1_6_REG_RX_TS_NFSEC_OFFSET 0 - #define PTP_RX_TS1_6_REG_RX_TS_NFSEC_LEN 8 - #define PTP_RX_TS1_6_REG_RX_TS_NFSEC_DEFAULT 0x0 - -struct ptp_rx_ts1_6_reg { - a_uint16_t rx_ts_nfsec:8; -}; - -union ptp_rx_ts1_6_reg_u { - a_uint32_t val; - struct ptp_rx_ts1_6_reg bf; -}; - -/*[register] PTP_RX_SEQID2_REG*/ -#define PTP_RX_SEQID2_REG -#define PTP_RX_SEQID2_REG_ADDRESS 0x851a -#define PTP_RX_SEQID2_REG_NUM 1 -#define PTP_RX_SEQID2_REG_INC 0x1 -#define PTP_RX_SEQID2_REG_TYPE REG_TYPE_RW -#define PTP_RX_SEQID2_REG_DEFAULT 0x0 - /*[field] RX_SEQID*/ - #define PTP_RX_SEQID2_REG_RX_SEQID - #define PTP_RX_SEQID2_REG_RX_SEQID_OFFSET 0 - #define PTP_RX_SEQID2_REG_RX_SEQID_LEN 16 - #define PTP_RX_SEQID2_REG_RX_SEQID_DEFAULT 0x0 - -struct ptp_rx_seqid2_reg { - a_uint16_t rx_seqid:16; -}; - -union ptp_rx_seqid2_reg_u { - a_uint32_t val; - struct ptp_rx_seqid2_reg bf; -}; - -/*[register] PTP_RX_PORTID2_0_REG*/ -#define PTP_RX_PORTID2_0_REG -#define PTP_RX_PORTID2_0_REG_ADDRESS 0x851b -#define PTP_RX_PORTID2_0_REG_NUM 1 -#define PTP_RX_PORTID2_0_REG_INC 0x1 -#define PTP_RX_PORTID2_0_REG_TYPE REG_TYPE_RW -#define PTP_RX_PORTID2_0_REG_DEFAULT 0x0 - /*[field] RX_PORTID*/ - #define PTP_RX_PORTID2_0_REG_RX_PORTID - #define PTP_RX_PORTID2_0_REG_RX_PORTID_OFFSET 0 - #define PTP_RX_PORTID2_0_REG_RX_PORTID_LEN 16 - #define PTP_RX_PORTID2_0_REG_RX_PORTID_DEFAULT 0x0 - -struct ptp_rx_portid2_0_reg { - a_uint16_t rx_portid:16; -}; - -union ptp_rx_portid2_0_reg_u { - a_uint32_t val; - struct ptp_rx_portid2_0_reg bf; -}; - -/*[register] PTP_RX_PORTID2_1_REG*/ -#define PTP_RX_PORTID2_1_REG -#define PTP_RX_PORTID2_1_REG_ADDRESS 0x851c -#define PTP_RX_PORTID2_1_REG_NUM 1 -#define PTP_RX_PORTID2_1_REG_INC 0x1 -#define PTP_RX_PORTID2_1_REG_TYPE REG_TYPE_RW -#define PTP_RX_PORTID2_1_REG_DEFAULT 0x0 - /*[field] RX_PORTID*/ - #define PTP_RX_PORTID2_1_REG_RX_PORTID - #define PTP_RX_PORTID2_1_REG_RX_PORTID_OFFSET 0 - #define PTP_RX_PORTID2_1_REG_RX_PORTID_LEN 16 - #define PTP_RX_PORTID2_1_REG_RX_PORTID_DEFAULT 0x0 - -struct ptp_rx_portid2_1_reg { - a_uint16_t rx_portid:16; -}; - -union ptp_rx_portid2_1_reg_u { - a_uint32_t val; - struct ptp_rx_portid2_1_reg bf; -}; - -/*[register] PTP_RX_PORTID2_2_REG*/ -#define PTP_RX_PORTID2_2_REG -#define PTP_RX_PORTID2_2_REG_ADDRESS 0x851d -#define PTP_RX_PORTID2_2_REG_NUM 1 -#define PTP_RX_PORTID2_2_REG_INC 0x1 -#define PTP_RX_PORTID2_2_REG_TYPE REG_TYPE_RW -#define PTP_RX_PORTID2_2_REG_DEFAULT 0x0 - /*[field] RX_PORTID*/ - #define PTP_RX_PORTID2_2_REG_RX_PORTID - #define PTP_RX_PORTID2_2_REG_RX_PORTID_OFFSET 0 - #define PTP_RX_PORTID2_2_REG_RX_PORTID_LEN 16 - #define PTP_RX_PORTID2_2_REG_RX_PORTID_DEFAULT 0x0 - -struct ptp_rx_portid2_2_reg { - a_uint16_t rx_portid:16; -}; - -union ptp_rx_portid2_2_reg_u { - a_uint32_t val; - struct ptp_rx_portid2_2_reg bf; -}; - -/*[register] PTP_RX_PORTID2_3_REG*/ -#define PTP_RX_PORTID2_3_REG -#define PTP_RX_PORTID2_3_REG_ADDRESS 0x851e -#define PTP_RX_PORTID2_3_REG_NUM 1 -#define PTP_RX_PORTID2_3_REG_INC 0x1 -#define PTP_RX_PORTID2_3_REG_TYPE REG_TYPE_RW -#define PTP_RX_PORTID2_3_REG_DEFAULT 0x0 - /*[field] RX_PORTID*/ - #define PTP_RX_PORTID2_3_REG_RX_PORTID - #define PTP_RX_PORTID2_3_REG_RX_PORTID_OFFSET 0 - #define PTP_RX_PORTID2_3_REG_RX_PORTID_LEN 16 - #define PTP_RX_PORTID2_3_REG_RX_PORTID_DEFAULT 0x0 - -struct ptp_rx_portid2_3_reg { - a_uint16_t rx_portid:16; -}; - -union ptp_rx_portid2_3_reg_u { - a_uint32_t val; - struct ptp_rx_portid2_3_reg bf; -}; - -/*[register] PTP_RX_PORTID2_4_REG*/ -#define PTP_RX_PORTID2_4_REG -#define PTP_RX_PORTID2_4_REG_ADDRESS 0x851f -#define PTP_RX_PORTID2_4_REG_NUM 1 -#define PTP_RX_PORTID2_4_REG_INC 0x1 -#define PTP_RX_PORTID2_4_REG_TYPE REG_TYPE_RW -#define PTP_RX_PORTID2_4_REG_DEFAULT 0x0 - /*[field] RX_PORTID*/ - #define PTP_RX_PORTID2_4_REG_RX_PORTID - #define PTP_RX_PORTID2_4_REG_RX_PORTID_OFFSET 0 - #define PTP_RX_PORTID2_4_REG_RX_PORTID_LEN 16 - #define PTP_RX_PORTID2_4_REG_RX_PORTID_DEFAULT 0x0 - -struct ptp_rx_portid2_4_reg { - a_uint16_t rx_portid:16; -}; - -union ptp_rx_portid2_4_reg_u { - a_uint32_t val; - struct ptp_rx_portid2_4_reg bf; -}; - -/*[register] PTP_RX_TS2_0_REG*/ -#define PTP_RX_TS2_0_REG -#define PTP_RX_TS2_0_REG_ADDRESS 0x8520 -#define PTP_RX_TS2_0_REG_NUM 1 -#define PTP_RX_TS2_0_REG_INC 0x1 -#define PTP_RX_TS2_0_REG_TYPE REG_TYPE_RW -#define PTP_RX_TS2_0_REG_DEFAULT 0x0 - /*[field] RX_TS_SEC*/ - #define PTP_RX_TS2_0_REG_RX_TS_SEC - #define PTP_RX_TS2_0_REG_RX_TS_SEC_OFFSET 0 - #define PTP_RX_TS2_0_REG_RX_TS_SEC_LEN 16 - #define PTP_RX_TS2_0_REG_RX_TS_SEC_DEFAULT 0x0 - -struct ptp_rx_ts2_0_reg { - a_uint16_t rx_ts_sec:16; -}; - -union ptp_rx_ts2_0_reg_u { - a_uint32_t val; - struct ptp_rx_ts2_0_reg bf; -}; - -/*[register] PTP_RX_TS2_1_REG*/ -#define PTP_RX_TS2_1_REG -#define PTP_RX_TS2_1_REG_ADDRESS 0x8521 -#define PTP_RX_TS2_1_REG_NUM 1 -#define PTP_RX_TS2_1_REG_INC 0x1 -#define PTP_RX_TS2_1_REG_TYPE REG_TYPE_RW -#define PTP_RX_TS2_1_REG_DEFAULT 0x0 - /*[field] RX_TS_SEC*/ - #define PTP_RX_TS2_1_REG_RX_TS_SEC - #define PTP_RX_TS2_1_REG_RX_TS_SEC_OFFSET 0 - #define PTP_RX_TS2_1_REG_RX_TS_SEC_LEN 16 - #define PTP_RX_TS2_1_REG_RX_TS_SEC_DEFAULT 0x0 - -struct ptp_rx_ts2_1_reg { - a_uint16_t rx_ts_sec:16; -}; - -union ptp_rx_ts2_1_reg_u { - a_uint32_t val; - struct ptp_rx_ts2_1_reg bf; -}; - -/*[register] PTP_RX_TS2_2_REG*/ -#define PTP_RX_TS2_2_REG -#define PTP_RX_TS2_2_REG_ADDRESS 0x8522 -#define PTP_RX_TS2_2_REG_NUM 1 -#define PTP_RX_TS2_2_REG_INC 0x1 -#define PTP_RX_TS2_2_REG_TYPE REG_TYPE_RW -#define PTP_RX_TS2_2_REG_DEFAULT 0x0 - /*[field] RX_TS_SEC*/ - #define PTP_RX_TS2_2_REG_RX_TS_SEC - #define PTP_RX_TS2_2_REG_RX_TS_SEC_OFFSET 0 - #define PTP_RX_TS2_2_REG_RX_TS_SEC_LEN 16 - #define PTP_RX_TS2_2_REG_RX_TS_SEC_DEFAULT 0x0 - -struct ptp_rx_ts2_2_reg { - a_uint16_t rx_ts_sec:16; -}; - -union ptp_rx_ts2_2_reg_u { - a_uint32_t val; - struct ptp_rx_ts2_2_reg bf; -}; - -/*[register] PTP_RX_TS2_3_REG*/ -#define PTP_RX_TS2_3_REG -#define PTP_RX_TS2_3_REG_ADDRESS 0x8523 -#define PTP_RX_TS2_3_REG_NUM 1 -#define PTP_RX_TS2_3_REG_INC 0x1 -#define PTP_RX_TS2_3_REG_TYPE REG_TYPE_RW -#define PTP_RX_TS2_3_REG_DEFAULT 0x0 - /*[field] RX_TS_NSEC*/ - #define PTP_RX_TS2_3_REG_RX_TS_NSEC - #define PTP_RX_TS2_3_REG_RX_TS_NSEC_OFFSET 0 - #define PTP_RX_TS2_3_REG_RX_TS_NSEC_LEN 16 - #define PTP_RX_TS2_3_REG_RX_TS_NSEC_DEFAULT 0x0 - -struct ptp_rx_ts2_3_reg { - a_uint16_t rx_ts_nsec:16; -}; - -union ptp_rx_ts2_3_reg_u { - a_uint32_t val; - struct ptp_rx_ts2_3_reg bf; -}; - -/*[register] PTP_RX_TS2_4_REG*/ -#define PTP_RX_TS2_4_REG -#define PTP_RX_TS2_4_REG_ADDRESS 0x8524 -#define PTP_RX_TS2_4_REG_NUM 1 -#define PTP_RX_TS2_4_REG_INC 0x1 -#define PTP_RX_TS2_4_REG_TYPE REG_TYPE_RW -#define PTP_RX_TS2_4_REG_DEFAULT 0x0 - /*[field] RX_TS_NSEC*/ - #define PTP_RX_TS2_4_REG_RX_TS_NSEC - #define PTP_RX_TS2_4_REG_RX_TS_NSEC_OFFSET 0 - #define PTP_RX_TS2_4_REG_RX_TS_NSEC_LEN 16 - #define PTP_RX_TS2_4_REG_RX_TS_NSEC_DEFAULT 0x0 - -struct ptp_rx_ts2_4_reg { - a_uint16_t rx_ts_nsec:16; -}; - -union ptp_rx_ts2_4_reg_u { - a_uint32_t val; - struct ptp_rx_ts2_4_reg bf; -}; - -/*[register] PTP_RX_TS2_5_REG*/ -#define PTP_RX_TS2_5_REG -#define PTP_RX_TS2_5_REG_ADDRESS 0x8525 -#define PTP_RX_TS2_5_REG_NUM 1 -#define PTP_RX_TS2_5_REG_INC 0x1 -#define PTP_RX_TS2_5_REG_TYPE REG_TYPE_RW -#define PTP_RX_TS2_5_REG_DEFAULT 0x0 - /*[field] RX_TS_NFSEC*/ - #define PTP_RX_TS2_5_REG_RX_TS_NFSEC - #define PTP_RX_TS2_5_REG_RX_TS_NFSEC_OFFSET 0 - #define PTP_RX_TS2_5_REG_RX_TS_NFSEC_LEN 12 - #define PTP_RX_TS2_5_REG_RX_TS_NFSEC_DEFAULT 0x0 - /*[field] RX_MSG_TYPE*/ - #define PTP_RX_TS2_5_REG_RX_MSG_TYPE - #define PTP_RX_TS2_5_REG_RX_MSG_TYPE_OFFSET 12 - #define PTP_RX_TS2_5_REG_RX_MSG_TYPE_LEN 4 - #define PTP_RX_TS2_5_REG_RX_MSG_TYPE_DEFAULT 0x0 - -struct ptp_rx_ts2_5_reg { - a_uint16_t rx_ts_nfsec:12; - a_uint16_t rx_msg_type:4; -}; - -union ptp_rx_ts2_5_reg_u { - a_uint32_t val; - struct ptp_rx_ts2_5_reg bf; -}; - -/*[register] PTP_RX_TS2_6_REG*/ -#define PTP_RX_TS2_6_REG -#define PTP_RX_TS2_6_REG_ADDRESS 0x8526 -#define PTP_RX_TS2_6_REG_NUM 1 -#define PTP_RX_TS2_6_REG_INC 0x1 -#define PTP_RX_TS2_6_REG_TYPE REG_TYPE_RW -#define PTP_RX_TS2_6_REG_DEFAULT 0x0 - /*[field] RX_TS_NFSEC*/ - #define PTP_RX_TS2_6_REG_RX_TS_NFSEC - #define PTP_RX_TS2_6_REG_RX_TS_NFSEC_OFFSET 0 - #define PTP_RX_TS2_6_REG_RX_TS_NFSEC_LEN 8 - #define PTP_RX_TS2_6_REG_RX_TS_NFSEC_DEFAULT 0x0 - -struct ptp_rx_ts2_6_reg { - a_uint16_t rx_ts_nfsec:8; -}; - -union ptp_rx_ts2_6_reg_u { - a_uint32_t val; - struct ptp_rx_ts2_6_reg bf; -}; - -/*[register] PTP_RX_SEQID3_REG*/ -#define PTP_RX_SEQID3_REG -#define PTP_RX_SEQID3_REG_ADDRESS 0x8534 -#define PTP_RX_SEQID3_REG_NUM 1 -#define PTP_RX_SEQID3_REG_INC 0x1 -#define PTP_RX_SEQID3_REG_TYPE REG_TYPE_RW -#define PTP_RX_SEQID3_REG_DEFAULT 0x0 - /*[field] RX_SEQID*/ - #define PTP_RX_SEQID3_REG_RX_SEQID - #define PTP_RX_SEQID3_REG_RX_SEQID_OFFSET 0 - #define PTP_RX_SEQID3_REG_RX_SEQID_LEN 16 - #define PTP_RX_SEQID3_REG_RX_SEQID_DEFAULT 0x0 - -struct ptp_rx_seqid3_reg { - a_uint16_t rx_seqid:16; -}; - -union ptp_rx_seqid3_reg_u { - a_uint32_t val; - struct ptp_rx_seqid3_reg bf; -}; - -/*[register] PTP_RX_PORTID3_0_REG*/ -#define PTP_RX_PORTID3_0_REG -#define PTP_RX_PORTID3_0_REG_ADDRESS 0x8535 -#define PTP_RX_PORTID3_0_REG_NUM 1 -#define PTP_RX_PORTID3_0_REG_INC 0x1 -#define PTP_RX_PORTID3_0_REG_TYPE REG_TYPE_RW -#define PTP_RX_PORTID3_0_REG_DEFAULT 0x0 - /*[field] RX_PORTID*/ - #define PTP_RX_PORTID3_0_REG_RX_PORTID - #define PTP_RX_PORTID3_0_REG_RX_PORTID_OFFSET 0 - #define PTP_RX_PORTID3_0_REG_RX_PORTID_LEN 16 - #define PTP_RX_PORTID3_0_REG_RX_PORTID_DEFAULT 0x0 - -struct ptp_rx_portid3_0_reg { - a_uint16_t rx_portid:16; -}; - -union ptp_rx_portid3_0_reg_u { - a_uint32_t val; - struct ptp_rx_portid3_0_reg bf; -}; - -/*[register] PTP_RX_PORTID3_1_REG*/ -#define PTP_RX_PORTID3_1_REG -#define PTP_RX_PORTID3_1_REG_ADDRESS 0x8536 -#define PTP_RX_PORTID3_1_REG_NUM 1 -#define PTP_RX_PORTID3_1_REG_INC 0x1 -#define PTP_RX_PORTID3_1_REG_TYPE REG_TYPE_RW -#define PTP_RX_PORTID3_1_REG_DEFAULT 0x0 - /*[field] RX_PORTID*/ - #define PTP_RX_PORTID3_1_REG_RX_PORTID - #define PTP_RX_PORTID3_1_REG_RX_PORTID_OFFSET 0 - #define PTP_RX_PORTID3_1_REG_RX_PORTID_LEN 16 - #define PTP_RX_PORTID3_1_REG_RX_PORTID_DEFAULT 0x0 - -struct ptp_rx_portid3_1_reg { - a_uint16_t rx_portid:16; -}; - -union ptp_rx_portid3_1_reg_u { - a_uint32_t val; - struct ptp_rx_portid3_1_reg bf; -}; - -/*[register] PTP_RX_PORTID3_2_REG*/ -#define PTP_RX_PORTID3_2_REG -#define PTP_RX_PORTID3_2_REG_ADDRESS 0x8537 -#define PTP_RX_PORTID3_2_REG_NUM 1 -#define PTP_RX_PORTID3_2_REG_INC 0x1 -#define PTP_RX_PORTID3_2_REG_TYPE REG_TYPE_RW -#define PTP_RX_PORTID3_2_REG_DEFAULT 0x0 - /*[field] RX_PORTID*/ - #define PTP_RX_PORTID3_2_REG_RX_PORTID - #define PTP_RX_PORTID3_2_REG_RX_PORTID_OFFSET 0 - #define PTP_RX_PORTID3_2_REG_RX_PORTID_LEN 16 - #define PTP_RX_PORTID3_2_REG_RX_PORTID_DEFAULT 0x0 - -struct ptp_rx_portid3_2_reg { - a_uint16_t rx_portid:16; -}; - -union ptp_rx_portid3_2_reg_u { - a_uint32_t val; - struct ptp_rx_portid3_2_reg bf; -}; - -/*[register] PTP_RX_PORTID3_3_REG*/ -#define PTP_RX_PORTID3_3_REG -#define PTP_RX_PORTID3_3_REG_ADDRESS 0x8538 -#define PTP_RX_PORTID3_3_REG_NUM 1 -#define PTP_RX_PORTID3_3_REG_INC 0x1 -#define PTP_RX_PORTID3_3_REG_TYPE REG_TYPE_RW -#define PTP_RX_PORTID3_3_REG_DEFAULT 0x0 - /*[field] RX_PORTID*/ - #define PTP_RX_PORTID3_3_REG_RX_PORTID - #define PTP_RX_PORTID3_3_REG_RX_PORTID_OFFSET 0 - #define PTP_RX_PORTID3_3_REG_RX_PORTID_LEN 16 - #define PTP_RX_PORTID3_3_REG_RX_PORTID_DEFAULT 0x0 - -struct ptp_rx_portid3_3_reg { - a_uint16_t rx_portid:16; -}; - -union ptp_rx_portid3_3_reg_u { - a_uint32_t val; - struct ptp_rx_portid3_3_reg bf; -}; - -/*[register] PTP_RX_PORTID3_4_REG*/ -#define PTP_RX_PORTID3_4_REG -#define PTP_RX_PORTID3_4_REG_ADDRESS 0x8539 -#define PTP_RX_PORTID3_4_REG_NUM 1 -#define PTP_RX_PORTID3_4_REG_INC 0x1 -#define PTP_RX_PORTID3_4_REG_TYPE REG_TYPE_RW -#define PTP_RX_PORTID3_4_REG_DEFAULT 0x0 - /*[field] RX_PORTID*/ - #define PTP_RX_PORTID3_4_REG_RX_PORTID - #define PTP_RX_PORTID3_4_REG_RX_PORTID_OFFSET 0 - #define PTP_RX_PORTID3_4_REG_RX_PORTID_LEN 16 - #define PTP_RX_PORTID3_4_REG_RX_PORTID_DEFAULT 0x0 - -struct ptp_rx_portid3_4_reg { - a_uint16_t rx_portid:16; -}; - -union ptp_rx_portid3_4_reg_u { - a_uint32_t val; - struct ptp_rx_portid3_4_reg bf; -}; - -/*[register] PTP_RX_TS3_0_REG*/ -#define PTP_RX_TS3_0_REG -#define PTP_RX_TS3_0_REG_ADDRESS 0x853a -#define PTP_RX_TS3_0_REG_NUM 1 -#define PTP_RX_TS3_0_REG_INC 0x1 -#define PTP_RX_TS3_0_REG_TYPE REG_TYPE_RW -#define PTP_RX_TS3_0_REG_DEFAULT 0x0 - /*[field] RX_TS_SEC*/ - #define PTP_RX_TS3_0_REG_RX_TS_SEC - #define PTP_RX_TS3_0_REG_RX_TS_SEC_OFFSET 0 - #define PTP_RX_TS3_0_REG_RX_TS_SEC_LEN 16 - #define PTP_RX_TS3_0_REG_RX_TS_SEC_DEFAULT 0x0 - -struct ptp_rx_ts3_0_reg { - a_uint16_t rx_ts_sec:16; -}; - -union ptp_rx_ts3_0_reg_u { - a_uint32_t val; - struct ptp_rx_ts3_0_reg bf; -}; - -/*[register] PTP_RX_TS3_1_REG*/ -#define PTP_RX_TS3_1_REG -#define PTP_RX_TS3_1_REG_ADDRESS 0x853b -#define PTP_RX_TS3_1_REG_NUM 1 -#define PTP_RX_TS3_1_REG_INC 0x1 -#define PTP_RX_TS3_1_REG_TYPE REG_TYPE_RW -#define PTP_RX_TS3_1_REG_DEFAULT 0x0 - /*[field] RX_TS_SEC*/ - #define PTP_RX_TS3_1_REG_RX_TS_SEC - #define PTP_RX_TS3_1_REG_RX_TS_SEC_OFFSET 0 - #define PTP_RX_TS3_1_REG_RX_TS_SEC_LEN 16 - #define PTP_RX_TS3_1_REG_RX_TS_SEC_DEFAULT 0x0 - -struct ptp_rx_ts3_1_reg { - a_uint16_t rx_ts_sec:16; -}; - -union ptp_rx_ts3_1_reg_u { - a_uint32_t val; - struct ptp_rx_ts3_1_reg bf; -}; - -/*[register] PTP_RX_TS3_2_REG*/ -#define PTP_RX_TS3_2_REG -#define PTP_RX_TS3_2_REG_ADDRESS 0x853c -#define PTP_RX_TS3_2_REG_NUM 1 -#define PTP_RX_TS3_2_REG_INC 0x1 -#define PTP_RX_TS3_2_REG_TYPE REG_TYPE_RW -#define PTP_RX_TS3_2_REG_DEFAULT 0x0 - /*[field] RX_TS_SEC*/ - #define PTP_RX_TS3_2_REG_RX_TS_SEC - #define PTP_RX_TS3_2_REG_RX_TS_SEC_OFFSET 0 - #define PTP_RX_TS3_2_REG_RX_TS_SEC_LEN 16 - #define PTP_RX_TS3_2_REG_RX_TS_SEC_DEFAULT 0x0 - -struct ptp_rx_ts3_2_reg { - a_uint16_t rx_ts_sec:16; -}; - -union ptp_rx_ts3_2_reg_u { - a_uint32_t val; - struct ptp_rx_ts3_2_reg bf; -}; - -/*[register] PTP_RX_TS3_3_REG*/ -#define PTP_RX_TS3_3_REG -#define PTP_RX_TS3_3_REG_ADDRESS 0x853d -#define PTP_RX_TS3_3_REG_NUM 1 -#define PTP_RX_TS3_3_REG_INC 0x1 -#define PTP_RX_TS3_3_REG_TYPE REG_TYPE_RW -#define PTP_RX_TS3_3_REG_DEFAULT 0x0 - /*[field] RX_TS_NSEC*/ - #define PTP_RX_TS3_3_REG_RX_TS_NSEC - #define PTP_RX_TS3_3_REG_RX_TS_NSEC_OFFSET 0 - #define PTP_RX_TS3_3_REG_RX_TS_NSEC_LEN 16 - #define PTP_RX_TS3_3_REG_RX_TS_NSEC_DEFAULT 0x0 - -struct ptp_rx_ts3_3_reg { - a_uint16_t rx_ts_nsec:16; -}; - -union ptp_rx_ts3_3_reg_u { - a_uint32_t val; - struct ptp_rx_ts3_3_reg bf; -}; - -/*[register] PTP_RX_TS3_4_REG*/ -#define PTP_RX_TS3_4_REG -#define PTP_RX_TS3_4_REG_ADDRESS 0x853e -#define PTP_RX_TS3_4_REG_NUM 1 -#define PTP_RX_TS3_4_REG_INC 0x1 -#define PTP_RX_TS3_4_REG_TYPE REG_TYPE_RW -#define PTP_RX_TS3_4_REG_DEFAULT 0x0 - /*[field] RX_TS_NSEC*/ - #define PTP_RX_TS3_4_REG_RX_TS_NSEC - #define PTP_RX_TS3_4_REG_RX_TS_NSEC_OFFSET 0 - #define PTP_RX_TS3_4_REG_RX_TS_NSEC_LEN 16 - #define PTP_RX_TS3_4_REG_RX_TS_NSEC_DEFAULT 0x0 - -struct ptp_rx_ts3_4_reg { - a_uint16_t rx_ts_nsec:16; -}; - -union ptp_rx_ts3_4_reg_u { - a_uint32_t val; - struct ptp_rx_ts3_4_reg bf; -}; - -/*[register] PTP_RX_TS3_5_REG*/ -#define PTP_RX_TS3_5_REG -#define PTP_RX_TS3_5_REG_ADDRESS 0x853f -#define PTP_RX_TS3_5_REG_NUM 1 -#define PTP_RX_TS3_5_REG_INC 0x1 -#define PTP_RX_TS3_5_REG_TYPE REG_TYPE_RW -#define PTP_RX_TS3_5_REG_DEFAULT 0x0 - /*[field] RX_TS_NFSEC*/ - #define PTP_RX_TS3_5_REG_RX_TS_NFSEC - #define PTP_RX_TS3_5_REG_RX_TS_NFSEC_OFFSET 0 - #define PTP_RX_TS3_5_REG_RX_TS_NFSEC_LEN 12 - #define PTP_RX_TS3_5_REG_RX_TS_NFSEC_DEFAULT 0x0 - /*[field] RX_MSG_TYPE*/ - #define PTP_RX_TS3_5_REG_RX_MSG_TYPE - #define PTP_RX_TS3_5_REG_RX_MSG_TYPE_OFFSET 12 - #define PTP_RX_TS3_5_REG_RX_MSG_TYPE_LEN 4 - #define PTP_RX_TS3_5_REG_RX_MSG_TYPE_DEFAULT 0x0 - -struct ptp_rx_ts3_5_reg { - a_uint16_t rx_ts_nfsec:12; - a_uint16_t rx_msg_type:4; -}; - -union ptp_rx_ts3_5_reg_u { - a_uint32_t val; - struct ptp_rx_ts3_5_reg bf; -}; - -/*[register] PTP_RX_TS3_6_REG*/ -#define PTP_RX_TS3_6_REG -#define PTP_RX_TS3_6_REG_ADDRESS 0x8540 -#define PTP_RX_TS3_6_REG_NUM 1 -#define PTP_RX_TS3_6_REG_INC 0x1 -#define PTP_RX_TS3_6_REG_TYPE REG_TYPE_RW -#define PTP_RX_TS3_6_REG_DEFAULT 0x0 - /*[field] RX_TS_NFSEC*/ - #define PTP_RX_TS3_6_REG_RX_TS_NFSEC - #define PTP_RX_TS3_6_REG_RX_TS_NFSEC_OFFSET 0 - #define PTP_RX_TS3_6_REG_RX_TS_NFSEC_LEN 8 - #define PTP_RX_TS3_6_REG_RX_TS_NFSEC_DEFAULT 0x0 - -struct ptp_rx_ts3_6_reg { - a_uint16_t rx_ts_nfsec:8; -}; - -union ptp_rx_ts3_6_reg_u { - a_uint32_t val; - struct ptp_rx_ts3_6_reg bf; -}; - -/*[register] PTP_PHASE_ADJUST_0*/ -#define PTP_PHASE_ADJUST_0_REG -#define PTP_PHASE_ADJUST_0_REG_ADDRESS 0x8300 -#define PTP_PHASE_ADJUST_0_REG_NUM 1 -#define PTP_PHASE_ADJUST_0_REG_INC 0x1 -#define PTP_PHASE_ADJUST_0_REG_TYPE REG_TYPE_RW -#define PTP_PHASE_ADJUST_0_REG_DEFAULT 0x0 - /*[field] PTP_PHASE_ADJUST_0*/ - #define PTP_PHASE_ADJUST_0_REG_PHASE_VALUE - #define PTP_PHASE_ADJUST_0_REG_PHASE_VALUE_OFFSET 0 - #define PTP_PHASE_ADJUST_0_REG_PHASE_VALUE_LEN 16 - #define PTP_PHASE_ADJUST_0_REG_PHASE_VALUE_DEFAULT 0x0 - -struct ptp_phase_adjust_0_reg { - a_uint16_t phase_value:16; -}; - -union ptp_phase_adjust_0_reg_u { - a_uint32_t val; - struct ptp_phase_adjust_0_reg bf; -}; - -/*[register] PTP_PHASE_ADJUST_1*/ -#define PTP_PHASE_ADJUST_1_REG -#define PTP_PHASE_ADJUST_1_REG_ADDRESS 0x8301 -#define PTP_PHASE_ADJUST_1_REG_NUM 1 -#define PTP_PHASE_ADJUST_1_REG_INC 0x1 -#define PTP_PHASE_ADJUST_1_REG_TYPE REG_TYPE_RW -#define PTP_PHASE_ADJUST_1_REG_DEFAULT 0x0 - /*[field] PTP_PHASE_ADJUST_1*/ - #define PTP_PHASE_ADJUST_1_REG_PHASE_VALUE - #define PTP_PHASE_ADJUST_1_REG_PHASE_VALUE_OFFSET 0 - #define PTP_PHASE_ADJUST_1_REG_PHASE_VALUE_LEN 16 - #define PTP_PHASE_ADJUST_1_REG_PHASE_VALUE_DEFAULT 0x0 - -struct ptp_phase_adjust_1_reg { - a_uint16_t phase_value:16; -}; - -union ptp_phase_adjust_1_reg_u { - a_uint32_t val; - struct ptp_phase_adjust_1_reg bf; -}; - -/*[register] PTP_PPS_PUL_WIDTH_0*/ -#define PTP_PPS_PUL_WIDTH_0_REG -#define PTP_PPS_PUL_WIDTH_0_REG_ADDRESS 0x8303 -#define PTP_PPS_PUL_WIDTH_0_REG_NUM 1 -#define PTP_PPS_PUL_WIDTH_0_REG_INC 0x1 -#define PTP_PPS_PUL_WIDTH_0_REG_TYPE REG_TYPE_RW -#define PTP_PPS_PUL_WIDTH_0_REG_DEFAULT 0x0 - /*[field] PTP_PPS_PUL_WIDTH_0*/ - #define PTP_PPS_PUL_WIDTH_0_REG_PUL_VALUE - #define PTP_PPS_PUL_WIDTH_0_REG_PUL_VALUE_OFFSET 0 - #define PTP_PPS_PUL_WIDTH_0_REG_PUL_VALUE_LEN 16 - #define PTP_PPS_PUL_WIDTH_0_REG_PUL_VALUE_DEFAULT 0x0 - -struct ptp_pps_pul_width_0_reg { - a_uint16_t pul_value:16; -}; - -union ptp_pps_pul_width_0_reg_u { - a_uint32_t val; - struct ptp_pps_pul_width_0_reg bf; -}; - -/*[register] PTP_PPS_PUL_WIDTH_1*/ -#define PTP_PPS_PUL_WIDTH_1_REG -#define PTP_PPS_PUL_WIDTH_1_REG_ADDRESS 0x8304 -#define PTP_PPS_PUL_WIDTH_1_REG_NUM 1 -#define PTP_PPS_PUL_WIDTH_1_REG_INC 0x1 -#define PTP_PPS_PUL_WIDTH_1_REG_TYPE REG_TYPE_RW -#define PTP_PPS_PUL_WIDTH_1_REG_DEFAULT 0x0 - /*[field] PTP_PPS_PUL_WIDTH_1*/ - #define PTP_PPS_PUL_WIDTH_1_REG_PUL_VALUE - #define PTP_PPS_PUL_WIDTH_1_REG_PUL_VALUE_OFFSET 0 - #define PTP_PPS_PUL_WIDTH_1_REG_PUL_VALUE_LEN 16 - #define PTP_PPS_PUL_WIDTH_1_REG_PUL_VALUE_DEFAULT 0x0 - -struct ptp_pps_pul_width_1_reg { - a_uint16_t pul_value:16; -}; - -union ptp_pps_pul_width_1_reg_u { - a_uint32_t val; - struct ptp_pps_pul_width_1_reg bf; -}; - -/*[register] PTP_FREQ_WAVEFORM_PERIOD_0_REG*/ -#define PTP_FREQ_WAVEFORM_PERIOD_0_REG -#define PTP_FREQ_WAVEFORM_PERIOD_0_REG_ADDRESS 0x8305 -#define PTP_FREQ_WAVEFORM_PERIOD_0_REG_NUM 1 -#define PTP_FREQ_WAVEFORM_PERIOD_0_REG_INC 0x1 -#define PTP_FREQ_WAVEFORM_PERIOD_0_REG_TYPE REG_TYPE_RW -#define PTP_FREQ_WAVEFORM_PERIOD_0_REG_DEFAULT 0x0 - /*[field] WAVE_PERIOD*/ - #define PTP_FREQ_WAVEFORM_PERIOD_0_REG_WAVE_PERIOD - #define PTP_FREQ_WAVEFORM_PERIOD_0_REG_WAVE_PERIOD_OFFSET 0 - #define PTP_FREQ_WAVEFORM_PERIOD_0_REG_WAVE_PERIOD_LEN 15 - #define PTP_FREQ_WAVEFORM_PERIOD_0_REG_WAVE_PERIOD_DEFAULT 0x0 - /*[field] PHASE_ALI*/ - #define PTP_FREQ_WAVEFORM_PERIOD_0_REG_PHASE_ALI - #define PTP_FREQ_WAVEFORM_PERIOD_0_REG_PHASE_ALI_OFFSET 15 - #define PTP_FREQ_WAVEFORM_PERIOD_0_REG_PHASE_ALI_LEN 1 - #define PTP_FREQ_WAVEFORM_PERIOD_0_REG_PHASE_ALI_DEFAULT 0x0 - -struct ptp_freq_waveform_period_0_reg { - a_uint16_t wave_period:15; - a_uint16_t phase_ali:1; -}; - -union ptp_freq_waveform_period_0_reg_u { - a_uint32_t val; - struct ptp_freq_waveform_period_0_reg bf; -}; - -/*[register] PTP_FREQ_WAVEFORM_PERIOD_1_REG*/ -#define PTP_FREQ_WAVEFORM_PERIOD_1_REG -#define PTP_FREQ_WAVEFORM_PERIOD_1_REG_ADDRESS 0x8306 -#define PTP_FREQ_WAVEFORM_PERIOD_1_REG_NUM 1 -#define PTP_FREQ_WAVEFORM_PERIOD_1_REG_INC 0x1 -#define PTP_FREQ_WAVEFORM_PERIOD_1_REG_TYPE REG_TYPE_RW -#define PTP_FREQ_WAVEFORM_PERIOD_1_REG_DEFAULT 0x0 - /*[field] WAVE_PERIOD*/ - #define PTP_FREQ_WAVEFORM_PERIOD_1_REG_WAVE_PERIOD - #define PTP_FREQ_WAVEFORM_PERIOD_1_REG_WAVE_PERIOD_OFFSET 0 - #define PTP_FREQ_WAVEFORM_PERIOD_1_REG_WAVE_PERIOD_LEN 16 - #define PTP_FREQ_WAVEFORM_PERIOD_1_REG_WAVE_PERIOD_DEFAULT 0x0 - -struct ptp_freq_waveform_period_1_reg { - a_uint16_t wave_period:16; -}; - -union ptp_freq_waveform_period_1_reg_u { - a_uint32_t val; - struct ptp_freq_waveform_period_1_reg bf; -}; - -/*[register] PTP_FREQ_WAVEFORM_PERIOD_2_REG*/ -#define PTP_FREQ_WAVEFORM_PERIOD_2_REG -#define PTP_FREQ_WAVEFORM_PERIOD_2_REG_ADDRESS 0x8307 -#define PTP_FREQ_WAVEFORM_PERIOD_2_REG_NUM 1 -#define PTP_FREQ_WAVEFORM_PERIOD_2_REG_INC 0x1 -#define PTP_FREQ_WAVEFORM_PERIOD_2_REG_TYPE REG_TYPE_RW -#define PTP_FREQ_WAVEFORM_PERIOD_2_REG_DEFAULT 0x0 - /*[field] WAVE_PERIOD*/ - #define PTP_FREQ_WAVEFORM_PERIOD_2_REG_WAVE_PERIOD - #define PTP_FREQ_WAVEFORM_PERIOD_2_REG_WAVE_PERIOD_OFFSET 0 - #define PTP_FREQ_WAVEFORM_PERIOD_2_REG_WAVE_PERIOD_LEN 16 - #define PTP_FREQ_WAVEFORM_PERIOD_2_REG_WAVE_PERIOD_DEFAULT 0x0 - -struct ptp_freq_waveform_period_2_reg { - a_uint16_t wave_period:16; -}; - -union ptp_freq_waveform_period_2_reg_u { - a_uint32_t val; - struct ptp_freq_waveform_period_2_reg bf; -}; - -/*[register] PTP_RX_COM_TS_CTRL_REG*/ -#define PTP_RX_COM_TS_CTRL_REG -#define PTP_RX_COM_TS_CTRL_REG_ADDRESS 0x8600 -#define PTP_RX_COM_TS_CTRL_REG_NUM 1 -#define PTP_RX_COM_TS_CTRL_REG_INC 0x1 -#define PTP_RX_COM_TS_CTRL_REG_TYPE REG_TYPE_RW -#define PTP_RX_COM_TS_CTRL_REG_DEFAULT 0x0 - /*[field] FILT_EN*/ - #define PTP_RX_COM_TS_CTRL_REG_FILT_EN - #define PTP_RX_COM_TS_CTRL_REG_FILT_EN_OFFSET 0 - #define PTP_RX_COM_TS_CTRL_REG_FILT_EN_LEN 1 - #define PTP_RX_COM_TS_CTRL_REG_FILT_EN_DEFAULT 0x0 - /*[field] MAC_LENGTHTYPE_EN*/ - #define PTP_RX_COM_TS_CTRL_REG_MAC_LENGTHTYPE_EN - #define PTP_RX_COM_TS_CTRL_REG_MAC_LENGTHTYPE_EN_OFFSET 1 - #define PTP_RX_COM_TS_CTRL_REG_MAC_LENGTHTYPE_EN_LEN 1 - #define PTP_RX_COM_TS_CTRL_REG_MAC_LENGTHTYPE_EN_DEFAULT 0x0 - /*[field] MAC_DA_EN*/ - #define PTP_RX_COM_TS_CTRL_REG_MAC_DA_EN - #define PTP_RX_COM_TS_CTRL_REG_MAC_DA_EN_OFFSET 2 - #define PTP_RX_COM_TS_CTRL_REG_MAC_DA_EN_LEN 1 - #define PTP_RX_COM_TS_CTRL_REG_MAC_DA_EN_DEFAULT 0x0 - /*[field] MAC_PTP_FILT_EN*/ - #define PTP_RX_COM_TS_CTRL_REG_MAC_PTP_FILT_EN - #define PTP_RX_COM_TS_CTRL_REG_MAC_PTP_FILT_EN_OFFSET 3 - #define PTP_RX_COM_TS_CTRL_REG_MAC_PTP_FILT_EN_LEN 1 - #define PTP_RX_COM_TS_CTRL_REG_MAC_PTP_FILT_EN_DEFAULT 0x0 - /*[field] IPV4_LAYER4_PROTOCOL_EN*/ - #define PTP_RX_COM_TS_CTRL_REG_IPV4_LAYER4_PROTOCOL_EN - #define PTP_RX_COM_TS_CTRL_REG_IPV4_LAYER4_PROTOCOL_EN_OFFSET 4 - #define PTP_RX_COM_TS_CTRL_REG_IPV4_LAYER4_PROTOCOL_EN_LEN 1 - #define PTP_RX_COM_TS_CTRL_REG_IPV4_LAYER4_PROTOCOL_EN_DEFAULT 0x0 - /*[field] IPV4_DA_EN*/ - #define PTP_RX_COM_TS_CTRL_REG_IPV4_DA_EN - #define PTP_RX_COM_TS_CTRL_REG_IPV4_DA_EN_OFFSET 5 - #define PTP_RX_COM_TS_CTRL_REG_IPV4_DA_EN_LEN 1 - #define PTP_RX_COM_TS_CTRL_REG_IPV4_DA_EN_DEFAULT 0x0 - /*[field] IPV4_PTP_FILT_EN*/ - #define PTP_RX_COM_TS_CTRL_REG_IPV4_PTP_FILT_EN - #define PTP_RX_COM_TS_CTRL_REG_IPV4_PTP_FILT_EN_OFFSET 6 - #define PTP_RX_COM_TS_CTRL_REG_IPV4_PTP_FILT_EN_LEN 1 - #define PTP_RX_COM_TS_CTRL_REG_IPV4_PTP_FILT_EN_DEFAULT 0x0 - /*[field] IPV6_NEXT_HEADER_EN*/ - #define PTP_RX_COM_TS_CTRL_REG_IPV6_NEXT_HEADER_EN - #define PTP_RX_COM_TS_CTRL_REG_IPV6_NEXT_HEADER_EN_OFFSET 7 - #define PTP_RX_COM_TS_CTRL_REG_IPV6_NEXT_HEADER_EN_LEN 1 - #define PTP_RX_COM_TS_CTRL_REG_IPV6_NEXT_HEADER_EN_DEFAULT 0x0 - /*[field] IPV6_DA_FILT_EN*/ - #define PTP_RX_COM_TS_CTRL_REG_IPV6_DA_FILT_EN - #define PTP_RX_COM_TS_CTRL_REG_IPV6_DA_FILT_EN_OFFSET 8 - #define PTP_RX_COM_TS_CTRL_REG_IPV6_DA_FILT_EN_LEN 1 - #define PTP_RX_COM_TS_CTRL_REG_IPV6_DA_FILT_EN_DEFAULT 0x0 - /*[field] IPV6_PTP_FILT_EN*/ - #define PTP_RX_COM_TS_CTRL_REG_IPV6_PTP_FILT_EN - #define PTP_RX_COM_TS_CTRL_REG_IPV6_PTP_FILT_EN_OFFSET 9 - #define PTP_RX_COM_TS_CTRL_REG_IPV6_PTP_FILT_EN_LEN 1 - #define PTP_RX_COM_TS_CTRL_REG_IPV6_PTP_FILT_EN_DEFAULT 0x0 - /*[field] UDP_DPORT_EN*/ - #define PTP_RX_COM_TS_CTRL_REG_UDP_DPORT_EN - #define PTP_RX_COM_TS_CTRL_REG_UDP_DPORT_EN_OFFSET 10 - #define PTP_RX_COM_TS_CTRL_REG_UDP_DPORT_EN_LEN 1 - #define PTP_RX_COM_TS_CTRL_REG_UDP_DPORT_EN_DEFAULT 0x0 - /*[field] UDP_PTP_EVENT_FILT_EN*/ - #define PTP_RX_COM_TS_CTRL_REG_UDP_PTP_EVENT_FILT_EN - #define PTP_RX_COM_TS_CTRL_REG_UDP_PTP_EVENT_FILT_EN_OFFSET 11 - #define PTP_RX_COM_TS_CTRL_REG_UDP_PTP_EVENT_FILT_EN_LEN 1 - #define PTP_RX_COM_TS_CTRL_REG_UDP_PTP_EVENT_FILT_EN_DEFAULT 0x0 - /*[field] Y1731_EN*/ - #define PTP_RX_COM_TS_CTRL_REG_Y1731_EN - #define PTP_RX_COM_TS_CTRL_REG_Y1731_EN_OFFSET 12 - #define PTP_RX_COM_TS_CTRL_REG_Y1731_EN_LEN 1 - #define PTP_RX_COM_TS_CTRL_REG_Y1731_EN_DEFAULT 0x0 - /*[field] Y1731_INSERT_TS_EN*/ - #define PTP_RX_COM_TS_CTRL_REG_Y1731_INSERT_TS_EN - #define PTP_RX_COM_TS_CTRL_REG_Y1731_INSERT_TS_EN_OFFSET 13 - #define PTP_RX_COM_TS_CTRL_REG_Y1731_INSERT_TS_EN_LEN 1 - #define PTP_RX_COM_TS_CTRL_REG_Y1731_INSERT_TS_EN_DEFAULT 0x0 - /*[field] Y1731_DA_CHK_EN*/ - #define PTP_RX_COM_TS_CTRL_REG_Y1731_DA_CHK_EN - #define PTP_RX_COM_TS_CTRL_REG_Y1731_DA_CHK_EN_OFFSET 14 - #define PTP_RX_COM_TS_CTRL_REG_Y1731_DA_CHK_EN_LEN 1 - #define PTP_RX_COM_TS_CTRL_REG_Y1731_DA_CHK_EN_DEFAULT 0x0 - /*[field] PW_MAC_EN*/ - #define PTP_RX_COM_TS_CTRL_REG_PW_MAC_EN - #define PTP_RX_COM_TS_CTRL_REG_PW_MAC_EN_OFFSET 15 - #define PTP_RX_COM_TS_CTRL_REG_PW_MAC_EN_LEN 1 - #define PTP_RX_COM_TS_CTRL_REG_PW_MAC_EN_DEFAULT 0x0 - -struct ptp_rx_com_ts_ctrl_reg { - a_uint32_t filt_en:1; - a_uint32_t mac_lengthtype_en:1; - a_uint32_t mac_da_en:1; - a_uint32_t mac_ptp_filt_en:1; - a_uint32_t ipv4_layer4_protocol_en:1; - a_uint32_t ipv4_da_en:1; - a_uint32_t ipv4_ptp_filt_en:1; - a_uint32_t ipv6_next_header_en:1; - a_uint32_t ipv6_da_filt_en:1; - a_uint32_t ipv6_ptp_filt_en:1; - a_uint32_t udp_dport_en:1; - a_uint32_t udp_ptp_event_filt_en:1; - a_uint32_t y1731_en:1; - a_uint32_t y1731_insert_ts_en:1; - a_uint32_t y1731_da_chk_en:1; - a_uint32_t pw_mac_en:1; -}; - -union ptp_rx_com_ts_ctrl_reg_u { - a_uint32_t val; - struct ptp_rx_com_ts_ctrl_reg bf; -}; - -/*[register] PTP_RX_FILT_MAC_DA0_REG*/ -#define PTP_RX_FILT_MAC_DA0_REG -#define PTP_RX_FILT_MAC_DA0_REG_ADDRESS 0x8601 -#define PTP_RX_FILT_MAC_DA0_REG_NUM 1 -#define PTP_RX_FILT_MAC_DA0_REG_INC 0x1 -#define PTP_RX_FILT_MAC_DA0_REG_TYPE REG_TYPE_RW -#define PTP_RX_FILT_MAC_DA0_REG_DEFAULT 0x0 - /*[field] MAC_ADDR*/ - #define PTP_RX_FILT_MAC_DA0_REG_MAC_ADDR - #define PTP_RX_FILT_MAC_DA0_REG_MAC_ADDR_OFFSET 0 - #define PTP_RX_FILT_MAC_DA0_REG_MAC_ADDR_LEN 16 - #define PTP_RX_FILT_MAC_DA0_REG_MAC_ADDR_DEFAULT 0x0 - -struct ptp_rx_filt_mac_da0_reg { - a_uint32_t mac_addr:16; -}; - -union ptp_rx_filt_mac_da0_reg_u { - a_uint32_t val; - struct ptp_rx_filt_mac_da0_reg bf; -}; - -/*[register] PTP_RX_FILT_MAC_DA1_REG*/ -#define PTP_RX_FILT_MAC_DA1_REG -#define PTP_RX_FILT_MAC_DA1_REG_ADDRESS 0x8602 -#define PTP_RX_FILT_MAC_DA1_REG_NUM 1 -#define PTP_RX_FILT_MAC_DA1_REG_INC 0x1 -#define PTP_RX_FILT_MAC_DA1_REG_TYPE REG_TYPE_RW -#define PTP_RX_FILT_MAC_DA1_REG_DEFAULT 0x0 - /*[field] MAC_ADDR*/ - #define PTP_RX_FILT_MAC_DA1_REG_MAC_ADDR - #define PTP_RX_FILT_MAC_DA1_REG_MAC_ADDR_OFFSET 0 - #define PTP_RX_FILT_MAC_DA1_REG_MAC_ADDR_LEN 16 - #define PTP_RX_FILT_MAC_DA1_REG_MAC_ADDR_DEFAULT 0x0 - -struct ptp_rx_filt_mac_da1_reg { - a_uint32_t mac_addr:16; -}; - -union ptp_rx_filt_mac_da1_reg_u { - a_uint32_t val; - struct ptp_rx_filt_mac_da1_reg bf; -}; - -/*[register] PTP_RX_FILT_MAC_DA2_REG*/ -#define PTP_RX_FILT_MAC_DA2_REG -#define PTP_RX_FILT_MAC_DA2_REG_ADDRESS 0x8603 -#define PTP_RX_FILT_MAC_DA2_REG_NUM 1 -#define PTP_RX_FILT_MAC_DA2_REG_INC 0x1 -#define PTP_RX_FILT_MAC_DA2_REG_TYPE REG_TYPE_RW -#define PTP_RX_FILT_MAC_DA2_REG_DEFAULT 0x0 - /*[field] MAC_ADDR*/ - #define PTP_RX_FILT_MAC_DA2_REG_MAC_ADDR - #define PTP_RX_FILT_MAC_DA2_REG_MAC_ADDR_OFFSET 0 - #define PTP_RX_FILT_MAC_DA2_REG_MAC_ADDR_LEN 16 - #define PTP_RX_FILT_MAC_DA2_REG_MAC_ADDR_DEFAULT 0x0 - -struct ptp_rx_filt_mac_da2_reg { - a_uint32_t mac_addr:16; -}; - -union ptp_rx_filt_mac_da2_reg_u { - a_uint32_t val; - struct ptp_rx_filt_mac_da2_reg bf; -}; - -/*[register] PTP_RX_FILT_IPV4_DA0_REG*/ -#define PTP_RX_FILT_IPV4_DA0_REG -#define PTP_RX_FILT_IPV4_DA0_REG_ADDRESS 0x8604 -#define PTP_RX_FILT_IPV4_DA0_REG_NUM 1 -#define PTP_RX_FILT_IPV4_DA0_REG_INC 0x1 -#define PTP_RX_FILT_IPV4_DA0_REG_TYPE REG_TYPE_RW -#define PTP_RX_FILT_IPV4_DA0_REG_DEFAULT 0x0 - /*[field] IP_ADDR*/ - #define PTP_RX_FILT_IPV4_DA0_REG_IP_ADDR - #define PTP_RX_FILT_IPV4_DA0_REG_IP_ADDR_OFFSET 0 - #define PTP_RX_FILT_IPV4_DA0_REG_IP_ADDR_LEN 16 - #define PTP_RX_FILT_IPV4_DA0_REG_IP_ADDR_DEFAULT 0x0 - -struct ptp_rx_filt_ipv4_da0_reg { - a_uint32_t ip_addr:16; -}; - -union ptp_rx_filt_ipv4_da0_reg_u { - a_uint32_t val; - struct ptp_rx_filt_ipv4_da0_reg bf; -}; - -/*[register] PTP_RX_FILT_IPV4_DA1_REG*/ -#define PTP_RX_FILT_IPV4_DA1_REG -#define PTP_RX_FILT_IPV4_DA1_REG_ADDRESS 0x8605 -#define PTP_RX_FILT_IPV4_DA1_REG_NUM 1 -#define PTP_RX_FILT_IPV4_DA1_REG_INC 0x1 -#define PTP_RX_FILT_IPV4_DA1_REG_TYPE REG_TYPE_RW -#define PTP_RX_FILT_IPV4_DA1_REG_DEFAULT 0x0 - /*[field] IP_ADDR*/ - #define PTP_RX_FILT_IPV4_DA1_REG_IP_ADDR - #define PTP_RX_FILT_IPV4_DA1_REG_IP_ADDR_OFFSET 0 - #define PTP_RX_FILT_IPV4_DA1_REG_IP_ADDR_LEN 16 - #define PTP_RX_FILT_IPV4_DA1_REG_IP_ADDR_DEFAULT 0x0 - -struct ptp_rx_filt_ipv4_da1_reg { - a_uint32_t ip_addr:16; -}; - -union ptp_rx_filt_ipv4_da1_reg_u { - a_uint32_t val; - struct ptp_rx_filt_ipv4_da1_reg bf; -}; - -/*[register] PTP_RX_FILT_IPV6_DA0_REG*/ -#define PTP_RX_FILT_IPV6_DA0_REG -#define PTP_RX_FILT_IPV6_DA0_REG_ADDRESS 0x8606 -#define PTP_RX_FILT_IPV6_DA0_REG_NUM 1 -#define PTP_RX_FILT_IPV6_DA0_REG_INC 0x1 -#define PTP_RX_FILT_IPV6_DA0_REG_TYPE REG_TYPE_RW -#define PTP_RX_FILT_IPV6_DA0_REG_DEFAULT 0x0 - /*[field] IP_ADDR*/ - #define PTP_RX_FILT_IPV6_DA0_REG_IP_ADDR - #define PTP_RX_FILT_IPV6_DA0_REG_IP_ADDR_OFFSET 0 - #define PTP_RX_FILT_IPV6_DA0_REG_IP_ADDR_LEN 16 - #define PTP_RX_FILT_IPV6_DA0_REG_IP_ADDR_DEFAULT 0x0 - -struct ptp_rx_filt_ipv6_da0_reg { - a_uint32_t ip_addr:16; -}; - -union ptp_rx_filt_ipv6_da0_reg_u { - a_uint32_t val; - struct ptp_rx_filt_ipv6_da0_reg bf; -}; - -/*[register] PTP_RX_FILT_IPV6_DA1_REG*/ -#define PTP_RX_FILT_IPV6_DA1_REG -#define PTP_RX_FILT_IPV6_DA1_REG_ADDRESS 0x8607 -#define PTP_RX_FILT_IPV6_DA1_REG_NUM 1 -#define PTP_RX_FILT_IPV6_DA1_REG_INC 0x1 -#define PTP_RX_FILT_IPV6_DA1_REG_TYPE REG_TYPE_RW -#define PTP_RX_FILT_IPV6_DA1_REG_DEFAULT 0x0 - /*[field] IP_ADDR*/ - #define PTP_RX_FILT_IPV6_DA1_REG_IP_ADDR - #define PTP_RX_FILT_IPV6_DA1_REG_IP_ADDR_OFFSET 0 - #define PTP_RX_FILT_IPV6_DA1_REG_IP_ADDR_LEN 16 - #define PTP_RX_FILT_IPV6_DA1_REG_IP_ADDR_DEFAULT 0x0 - -struct ptp_rx_filt_ipv6_da1_reg { - a_uint32_t ip_addr:16; -}; - -union ptp_rx_filt_ipv6_da1_reg_u { - a_uint32_t val; - struct ptp_rx_filt_ipv6_da1_reg bf; -}; - -/*[register] PTP_RX_FILT_IPV6_DA2_REG*/ -#define PTP_RX_FILT_IPV6_DA2_REG -#define PTP_RX_FILT_IPV6_DA2_REG_ADDRESS 0x8608 -#define PTP_RX_FILT_IPV6_DA2_REG_NUM 1 -#define PTP_RX_FILT_IPV6_DA2_REG_INC 0x1 -#define PTP_RX_FILT_IPV6_DA2_REG_TYPE REG_TYPE_RW -#define PTP_RX_FILT_IPV6_DA2_REG_DEFAULT 0x0 - /*[field] IP_ADDR*/ - #define PTP_RX_FILT_IPV6_DA2_REG_IP_ADDR - #define PTP_RX_FILT_IPV6_DA2_REG_IP_ADDR_OFFSET 0 - #define PTP_RX_FILT_IPV6_DA2_REG_IP_ADDR_LEN 16 - #define PTP_RX_FILT_IPV6_DA2_REG_IP_ADDR_DEFAULT 0x0 - -struct ptp_rx_filt_ipv6_da2_reg { - a_uint32_t ip_addr:16; -}; - -union ptp_rx_filt_ipv6_da2_reg_u { - a_uint32_t val; - struct ptp_rx_filt_ipv6_da2_reg bf; -}; - -/*[register] PTP_RX_FILT_IPV6_DA3_REG*/ -#define PTP_RX_FILT_IPV6_DA3_REG -#define PTP_RX_FILT_IPV6_DA3_REG_ADDRESS 0x8609 -#define PTP_RX_FILT_IPV6_DA3_REG_NUM 1 -#define PTP_RX_FILT_IPV6_DA3_REG_INC 0x1 -#define PTP_RX_FILT_IPV6_DA3_REG_TYPE REG_TYPE_RW -#define PTP_RX_FILT_IPV6_DA3_REG_DEFAULT 0x0 - /*[field] IP_ADDR*/ - #define PTP_RX_FILT_IPV6_DA3_REG_IP_ADDR - #define PTP_RX_FILT_IPV6_DA3_REG_IP_ADDR_OFFSET 0 - #define PTP_RX_FILT_IPV6_DA3_REG_IP_ADDR_LEN 16 - #define PTP_RX_FILT_IPV6_DA3_REG_IP_ADDR_DEFAULT 0x0 - -struct ptp_rx_filt_ipv6_da3_reg { - a_uint32_t ip_addr:16; -}; - -union ptp_rx_filt_ipv6_da3_reg_u { - a_uint32_t val; - struct ptp_rx_filt_ipv6_da3_reg bf; -}; - -/*[register] PTP_RX_FILT_IPV6_DA4_REG*/ -#define PTP_RX_FILT_IPV6_DA4_REG -#define PTP_RX_FILT_IPV6_DA4_REG_ADDRESS 0x860a -#define PTP_RX_FILT_IPV6_DA4_REG_NUM 1 -#define PTP_RX_FILT_IPV6_DA4_REG_INC 0x1 -#define PTP_RX_FILT_IPV6_DA4_REG_TYPE REG_TYPE_RW -#define PTP_RX_FILT_IPV6_DA4_REG_DEFAULT 0x0 - /*[field] IP_ADDR*/ - #define PTP_RX_FILT_IPV6_DA4_REG_IP_ADDR - #define PTP_RX_FILT_IPV6_DA4_REG_IP_ADDR_OFFSET 0 - #define PTP_RX_FILT_IPV6_DA4_REG_IP_ADDR_LEN 16 - #define PTP_RX_FILT_IPV6_DA4_REG_IP_ADDR_DEFAULT 0x0 - -struct ptp_rx_filt_ipv6_da4_reg { - a_uint32_t ip_addr:16; -}; - -union ptp_rx_filt_ipv6_da4_reg_u { - a_uint32_t val; - struct ptp_rx_filt_ipv6_da4_reg bf; -}; - -/*[register] PTP_RX_FILT_IPV6_DA5_REG*/ -#define PTP_RX_FILT_IPV6_DA5_REG -#define PTP_RX_FILT_IPV6_DA5_REG_ADDRESS 0x860b -#define PTP_RX_FILT_IPV6_DA5_REG_NUM 1 -#define PTP_RX_FILT_IPV6_DA5_REG_INC 0x1 -#define PTP_RX_FILT_IPV6_DA5_REG_TYPE REG_TYPE_RW -#define PTP_RX_FILT_IPV6_DA5_REG_DEFAULT 0x0 - /*[field] IP_ADDR*/ - #define PTP_RX_FILT_IPV6_DA5_REG_IP_ADDR - #define PTP_RX_FILT_IPV6_DA5_REG_IP_ADDR_OFFSET 0 - #define PTP_RX_FILT_IPV6_DA5_REG_IP_ADDR_LEN 16 - #define PTP_RX_FILT_IPV6_DA5_REG_IP_ADDR_DEFAULT 0x0 - -struct ptp_rx_filt_ipv6_da5_reg { - a_uint32_t ip_addr:16; -}; - -union ptp_rx_filt_ipv6_da5_reg_u { - a_uint32_t val; - struct ptp_rx_filt_ipv6_da5_reg bf; -}; - -/*[register] PTP_RX_FILT_IPV6_DA6_REG*/ -#define PTP_RX_FILT_IPV6_DA6_REG -#define PTP_RX_FILT_IPV6_DA6_REG_ADDRESS 0x860c -#define PTP_RX_FILT_IPV6_DA6_REG_NUM 1 -#define PTP_RX_FILT_IPV6_DA6_REG_INC 0x1 -#define PTP_RX_FILT_IPV6_DA6_REG_TYPE REG_TYPE_RW -#define PTP_RX_FILT_IPV6_DA6_REG_DEFAULT 0x0 - /*[field] IP_ADDR*/ - #define PTP_RX_FILT_IPV6_DA6_REG_IP_ADDR - #define PTP_RX_FILT_IPV6_DA6_REG_IP_ADDR_OFFSET 0 - #define PTP_RX_FILT_IPV6_DA6_REG_IP_ADDR_LEN 16 - #define PTP_RX_FILT_IPV6_DA6_REG_IP_ADDR_DEFAULT 0x0 - -struct ptp_rx_filt_ipv6_da6_reg { - a_uint32_t ip_addr:16; -}; - -union ptp_rx_filt_ipv6_da6_reg_u { - a_uint32_t val; - struct ptp_rx_filt_ipv6_da6_reg bf; -}; - -/*[register] PTP_RX_FILT_IPV6_DA7_REG*/ -#define PTP_RX_FILT_IPV6_DA7_REG -#define PTP_RX_FILT_IPV6_DA7_REG_ADDRESS 0x860d -#define PTP_RX_FILT_IPV6_DA7_REG_NUM 1 -#define PTP_RX_FILT_IPV6_DA7_REG_INC 0x1 -#define PTP_RX_FILT_IPV6_DA7_REG_TYPE REG_TYPE_RW -#define PTP_RX_FILT_IPV6_DA7_REG_DEFAULT 0x0 - /*[field] IP_ADDR*/ - #define PTP_RX_FILT_IPV6_DA7_REG_IP_ADDR - #define PTP_RX_FILT_IPV6_DA7_REG_IP_ADDR_OFFSET 0 - #define PTP_RX_FILT_IPV6_DA7_REG_IP_ADDR_LEN 16 - #define PTP_RX_FILT_IPV6_DA7_REG_IP_ADDR_DEFAULT 0x0 - -struct ptp_rx_filt_ipv6_da7_reg { - a_uint32_t ip_addr:16; -}; - -union ptp_rx_filt_ipv6_da7_reg_u { - a_uint32_t val; - struct ptp_rx_filt_ipv6_da7_reg bf; -}; - -/*[register] PTP_RX_FILT_MAC_LENGTHTYPE_REG*/ -#define PTP_RX_FILT_MAC_LENGTHTYPE_REG -#define PTP_RX_FILT_MAC_LENGTHTYPE_REG_ADDRESS 0x860e -#define PTP_RX_FILT_MAC_LENGTHTYPE_REG_NUM 1 -#define PTP_RX_FILT_MAC_LENGTHTYPE_REG_INC 0x1 -#define PTP_RX_FILT_MAC_LENGTHTYPE_REG_TYPE REG_TYPE_RW -#define PTP_RX_FILT_MAC_LENGTHTYPE_REG_DEFAULT 0x0 - /*[field] LENGTH_TYPE*/ - #define PTP_RX_FILT_MAC_LENGTHTYPE_REG_LENGTH_TYPE - #define PTP_RX_FILT_MAC_LENGTHTYPE_REG_LENGTH_TYPE_OFFSET 0 - #define PTP_RX_FILT_MAC_LENGTHTYPE_REG_LENGTH_TYPE_LEN 16 - #define PTP_RX_FILT_MAC_LENGTHTYPE_REG_LENGTH_TYPE_DEFAULT 0x0 - -struct ptp_rx_filt_mac_lengthtype_reg { - a_uint32_t length_type:16; -}; - -union ptp_rx_filt_mac_lengthtype_reg_u { - a_uint32_t val; - struct ptp_rx_filt_mac_lengthtype_reg bf; -}; - -/*[register] PTP_RX_FILT_LAYER4_PROTOCOL_REG*/ -#define PTP_RX_FILT_LAYER4_PROTOCOL_REG -#define PTP_RX_FILT_LAYER4_PROTOCOL_REG_ADDRESS 0x860f -#define PTP_RX_FILT_LAYER4_PROTOCOL_REG_NUM 1 -#define PTP_RX_FILT_LAYER4_PROTOCOL_REG_INC 0x1 -#define PTP_RX_FILT_LAYER4_PROTOCOL_REG_TYPE REG_TYPE_RW -#define PTP_RX_FILT_LAYER4_PROTOCOL_REG_DEFAULT 0x0 - /*[field] L4_PROTOCOL*/ - #define PTP_RX_FILT_LAYER4_PROTOCOL_REG_L4_PROTOCOL - #define PTP_RX_FILT_LAYER4_PROTOCOL_REG_L4_PROTOCOL_OFFSET 0 - #define PTP_RX_FILT_LAYER4_PROTOCOL_REG_L4_PROTOCOL_LEN 16 - #define PTP_RX_FILT_LAYER4_PROTOCOL_REG_L4_PROTOCOL_DEFAULT 0x0 - -struct ptp_rx_filt_layer4_protocol_reg { - a_uint32_t l4_protocol:16; -}; - -union ptp_rx_filt_layer4_protocol_reg_u { - a_uint32_t val; - struct ptp_rx_filt_layer4_protocol_reg bf; -}; - -/*[register] PTP_RX_FILT_UDP_PORT_REG*/ -#define PTP_RX_FILT_UDP_PORT_REG -#define PTP_RX_FILT_UDP_PORT_REG_ADDRESS 0x8610 -#define PTP_RX_FILT_UDP_PORT_REG_NUM 1 -#define PTP_RX_FILT_UDP_PORT_REG_INC 0x1 -#define PTP_RX_FILT_UDP_PORT_REG_TYPE REG_TYPE_RW -#define PTP_RX_FILT_UDP_PORT_REG_DEFAULT 0x0 - /*[field] UDP_PORT*/ - #define PTP_RX_FILT_UDP_PORT_REG_UDP_PORT - #define PTP_RX_FILT_UDP_PORT_REG_UDP_PORT_OFFSET 0 - #define PTP_RX_FILT_UDP_PORT_REG_UDP_PORT_LEN 16 - #define PTP_RX_FILT_UDP_PORT_REG_UDP_PORT_DEFAULT 0x0 - -struct ptp_rx_filt_udp_port_reg { - a_uint32_t udp_port:16; -}; - -union ptp_rx_filt_udp_port_reg_u { - a_uint32_t val; - struct ptp_rx_filt_udp_port_reg bf; -}; - -/*[register] PTP_RX_COM_TS_STATUS_REG*/ -#define PTP_RX_COM_TS_STATUS_REG -#define PTP_RX_COM_TS_STATUS_REG_ADDRESS 0x8611 -#define PTP_RX_COM_TS_STATUS_REG_NUM 1 -#define PTP_RX_COM_TS_STATUS_REG_INC 0x1 -#define PTP_RX_COM_TS_STATUS_REG_TYPE REG_TYPE_RW -#define PTP_RX_COM_TS_STATUS_REG_DEFAULT 0x0 - /*[field] MAC_LENGTHTYPE*/ - #define PTP_RX_COM_TS_STATUS_REG_MAC_LENGTHTYPE - #define PTP_RX_COM_TS_STATUS_REG_MAC_LENGTHTYPE_OFFSET 0 - #define PTP_RX_COM_TS_STATUS_REG_MAC_LENGTHTYPE_LEN 1 - #define PTP_RX_COM_TS_STATUS_REG_MAC_LENGTHTYPE_DEFAULT 0x0 - /*[field] MAC_DA*/ - #define PTP_RX_COM_TS_STATUS_REG_MAC_DA - #define PTP_RX_COM_TS_STATUS_REG_MAC_DA_OFFSET 1 - #define PTP_RX_COM_TS_STATUS_REG_MAC_DA_LEN 1 - #define PTP_RX_COM_TS_STATUS_REG_MAC_DA_DEFAULT 0x0 - /*[field] MAC_PTP_PRIM_ADDR*/ - #define PTP_RX_COM_TS_STATUS_REG_MAC_PTP_PRIM_ADDR - #define PTP_RX_COM_TS_STATUS_REG_MAC_PTP_PRIM_ADDR_OFFSET 2 - #define PTP_RX_COM_TS_STATUS_REG_MAC_PTP_PRIM_ADDR_LEN 1 - #define PTP_RX_COM_TS_STATUS_REG_MAC_PTP_PRIM_ADDR_DEFAULT 0x0 - /*[field] MAC_PTP_PDELAY_ADDR*/ - #define PTP_RX_COM_TS_STATUS_REG_MAC_PTP_PDELAY_ADDR - #define PTP_RX_COM_TS_STATUS_REG_MAC_PTP_PDELAY_ADDR_OFFSET 3 - #define PTP_RX_COM_TS_STATUS_REG_MAC_PTP_PDELAY_ADDR_LEN 1 - #define PTP_RX_COM_TS_STATUS_REG_MAC_PTP_PDELAY_ADDR_DEFAULT 0x0 - /*[field] IPV4_LAYER4_PROTOCOL*/ - #define PTP_RX_COM_TS_STATUS_REG_IPV4_LAYER4_PROTOCOL - #define PTP_RX_COM_TS_STATUS_REG_IPV4_LAYER4_PROTOCOL_OFFSET 4 - #define PTP_RX_COM_TS_STATUS_REG_IPV4_LAYER4_PROTOCOL_LEN 1 - #define PTP_RX_COM_TS_STATUS_REG_IPV4_LAYER4_PROTOCOL_DEFAULT 0x0 - /*[field] IPV4_DA*/ - #define PTP_RX_COM_TS_STATUS_REG_IPV4_DA - #define PTP_RX_COM_TS_STATUS_REG_IPV4_DA_OFFSET 5 - #define PTP_RX_COM_TS_STATUS_REG_IPV4_DA_LEN 1 - #define PTP_RX_COM_TS_STATUS_REG_IPV4_DA_DEFAULT 0x0 - /*[field] IPV4_PTP_PRIM_ADDR*/ - #define PTP_RX_COM_TS_STATUS_REG_IPV4_PTP_PRIM_ADDR - #define PTP_RX_COM_TS_STATUS_REG_IPV4_PTP_PRIM_ADDR_OFFSET 6 - #define PTP_RX_COM_TS_STATUS_REG_IPV4_PTP_PRIM_ADDR_LEN 1 - #define PTP_RX_COM_TS_STATUS_REG_IPV4_PTP_PRIM_ADDR_DEFAULT 0x0 - /*[field] IPV4_PTP_PDELAY_ADDR*/ - #define PTP_RX_COM_TS_STATUS_REG_IPV4_PTP_PDELAY_ADDR - #define PTP_RX_COM_TS_STATUS_REG_IPV4_PTP_PDELAY_ADDR_OFFSET 7 - #define PTP_RX_COM_TS_STATUS_REG_IPV4_PTP_PDELAY_ADDR_LEN 1 - #define PTP_RX_COM_TS_STATUS_REG_IPV4_PTP_PDELAY_ADDR_DEFAULT 0x0 - /*[field] IPV6_NEXT_HEADER*/ - #define PTP_RX_COM_TS_STATUS_REG_IPV6_NEXT_HEADER - #define PTP_RX_COM_TS_STATUS_REG_IPV6_NEXT_HEADER_OFFSET 8 - #define PTP_RX_COM_TS_STATUS_REG_IPV6_NEXT_HEADER_LEN 1 - #define PTP_RX_COM_TS_STATUS_REG_IPV6_NEXT_HEADER_DEFAULT 0x0 - /*[field] IPV6_DA*/ - #define PTP_RX_COM_TS_STATUS_REG_IPV6_DA - #define PTP_RX_COM_TS_STATUS_REG_IPV6_DA_OFFSET 9 - #define PTP_RX_COM_TS_STATUS_REG_IPV6_DA_LEN 1 - #define PTP_RX_COM_TS_STATUS_REG_IPV6_DA_DEFAULT 0x0 - /*[field] IPV6_PTP_PRIM_ADDR*/ - #define PTP_RX_COM_TS_STATUS_REG_IPV6_PTP_PRIM_ADDR - #define PTP_RX_COM_TS_STATUS_REG_IPV6_PTP_PRIM_ADDR_OFFSET 10 - #define PTP_RX_COM_TS_STATUS_REG_IPV6_PTP_PRIM_ADDR_LEN 1 - #define PTP_RX_COM_TS_STATUS_REG_IPV6_PTP_PRIM_ADDR_DEFAULT 0x0 - /*[field] IPV6_PTP_PDELAY_ADDR*/ - #define PTP_RX_COM_TS_STATUS_REG_IPV6_PTP_PDELAY_ADDR - #define PTP_RX_COM_TS_STATUS_REG_IPV6_PTP_PDELAY_ADDR_OFFSET 11 - #define PTP_RX_COM_TS_STATUS_REG_IPV6_PTP_PDELAY_ADDR_LEN 1 - #define PTP_RX_COM_TS_STATUS_REG_IPV6_PTP_PDELAY_ADDR_DEFAULT 0x0 - /*[field] UDP_DPORT*/ - #define PTP_RX_COM_TS_STATUS_REG_UDP_DPORT - #define PTP_RX_COM_TS_STATUS_REG_UDP_DPORT_OFFSET 12 - #define PTP_RX_COM_TS_STATUS_REG_UDP_DPORT_LEN 1 - #define PTP_RX_COM_TS_STATUS_REG_UDP_DPORT_DEFAULT 0x0 - /*[field] UDP_PTP_EVENT_DPORT*/ - #define PTP_RX_COM_TS_STATUS_REG_UDP_PTP_EVENT_DPORT - #define PTP_RX_COM_TS_STATUS_REG_UDP_PTP_EVENT_DPORT_OFFSET 13 - #define PTP_RX_COM_TS_STATUS_REG_UDP_PTP_EVENT_DPORT_LEN 1 - #define PTP_RX_COM_TS_STATUS_REG_UDP_PTP_EVENT_DPORT_DEFAULT 0x0 - /*[field] Y1731_MACH*/ - #define PTP_RX_COM_TS_STATUS_REG_Y1731_MACH - #define PTP_RX_COM_TS_STATUS_REG_Y1731_MACH_OFFSET 14 - #define PTP_RX_COM_TS_STATUS_REG_Y1731_MACH_LEN 1 - #define PTP_RX_COM_TS_STATUS_REG_Y1731_MACH_DEFAULT 0x0 - -struct ptp_rx_com_ts_status_reg { - a_uint32_t mac_lengthtype:1; - a_uint32_t mac_da:1; - a_uint32_t mac_ptp_prim_addr:1; - a_uint32_t mac_ptp_pdelay_addr:1; - a_uint32_t ipv4_layer4_protocol:1; - a_uint32_t ipv4_da:1; - a_uint32_t ipv4_ptp_prim_addr:1; - a_uint32_t ipv4_ptp_pdelay_addr:1; - a_uint32_t ipv6_next_header:1; - a_uint32_t ipv6_da:1; - a_uint32_t ipv6_ptp_prim_addr:1; - a_uint32_t ipv6_ptp_pdelay_addr:1; - a_uint32_t udp_dport:1; - a_uint32_t udp_ptp_event_dport:1; - a_uint32_t y1731_mach:1; -}; - -union ptp_rx_com_ts_status_reg_u { - a_uint32_t val; - struct ptp_rx_com_ts_status_reg bf; -}; - -/*[register] PTP_RX_COM_TIMESTAMP0_REG*/ -#define PTP_RX_COM_TIMESTAMP0_REG -#define PTP_RX_COM_TIMESTAMP0_REG_ADDRESS 0x8612 -#define PTP_RX_COM_TIMESTAMP0_REG_NUM 1 -#define PTP_RX_COM_TIMESTAMP0_REG_INC 0x1 -#define PTP_RX_COM_TIMESTAMP0_REG_TYPE REG_TYPE_RW -#define PTP_RX_COM_TIMESTAMP0_REG_DEFAULT 0x0 - /*[field] COM_TS*/ - #define PTP_RX_COM_TIMESTAMP0_REG_COM_TS - #define PTP_RX_COM_TIMESTAMP0_REG_COM_TS_OFFSET 0 - #define PTP_RX_COM_TIMESTAMP0_REG_COM_TS_LEN 16 - #define PTP_RX_COM_TIMESTAMP0_REG_COM_TS_DEFAULT 0x0 - -struct ptp_rx_com_timestamp0_reg { - a_uint32_t com_ts:16; -}; - -union ptp_rx_com_timestamp0_reg_u { - a_uint32_t val; - struct ptp_rx_com_timestamp0_reg bf; -}; - -/*[register] PTP_RX_COM_TIMESTAMP1_REG*/ -#define PTP_RX_COM_TIMESTAMP1_REG -#define PTP_RX_COM_TIMESTAMP1_REG_ADDRESS 0x8613 -#define PTP_RX_COM_TIMESTAMP1_REG_NUM 1 -#define PTP_RX_COM_TIMESTAMP1_REG_INC 0x1 -#define PTP_RX_COM_TIMESTAMP1_REG_TYPE REG_TYPE_RW -#define PTP_RX_COM_TIMESTAMP1_REG_DEFAULT 0x0 - /*[field] COM_TS*/ - #define PTP_RX_COM_TIMESTAMP1_REG_COM_TS - #define PTP_RX_COM_TIMESTAMP1_REG_COM_TS_OFFSET 0 - #define PTP_RX_COM_TIMESTAMP1_REG_COM_TS_LEN 16 - #define PTP_RX_COM_TIMESTAMP1_REG_COM_TS_DEFAULT 0x0 - -struct ptp_rx_com_timestamp1_reg { - a_uint32_t com_ts:16; -}; - -union ptp_rx_com_timestamp1_reg_u { - a_uint32_t val; - struct ptp_rx_com_timestamp1_reg bf; -}; - -/*[register] PTP_RX_COM_TIMESTAMP2_REG*/ -#define PTP_RX_COM_TIMESTAMP2_REG -#define PTP_RX_COM_TIMESTAMP2_REG_ADDRESS 0x8614 -#define PTP_RX_COM_TIMESTAMP2_REG_NUM 1 -#define PTP_RX_COM_TIMESTAMP2_REG_INC 0x1 -#define PTP_RX_COM_TIMESTAMP2_REG_TYPE REG_TYPE_RW -#define PTP_RX_COM_TIMESTAMP2_REG_DEFAULT 0x0 - /*[field] COM_TS*/ - #define PTP_RX_COM_TIMESTAMP2_REG_COM_TS - #define PTP_RX_COM_TIMESTAMP2_REG_COM_TS_OFFSET 0 - #define PTP_RX_COM_TIMESTAMP2_REG_COM_TS_LEN 16 - #define PTP_RX_COM_TIMESTAMP2_REG_COM_TS_DEFAULT 0x0 - -struct ptp_rx_com_timestamp2_reg { - a_uint32_t com_ts:16; -}; - -union ptp_rx_com_timestamp2_reg_u { - a_uint32_t val; - struct ptp_rx_com_timestamp2_reg bf; -}; - -/*[register] PTP_RX_COM_TIMESTAMP3_REG*/ -#define PTP_RX_COM_TIMESTAMP3_REG -#define PTP_RX_COM_TIMESTAMP3_REG_ADDRESS 0x8615 -#define PTP_RX_COM_TIMESTAMP3_REG_NUM 1 -#define PTP_RX_COM_TIMESTAMP3_REG_INC 0x1 -#define PTP_RX_COM_TIMESTAMP3_REG_TYPE REG_TYPE_RW -#define PTP_RX_COM_TIMESTAMP3_REG_DEFAULT 0x0 - /*[field] COM_TS*/ - #define PTP_RX_COM_TIMESTAMP3_REG_COM_TS - #define PTP_RX_COM_TIMESTAMP3_REG_COM_TS_OFFSET 0 - #define PTP_RX_COM_TIMESTAMP3_REG_COM_TS_LEN 16 - #define PTP_RX_COM_TIMESTAMP3_REG_COM_TS_DEFAULT 0x0 - -struct ptp_rx_com_timestamp3_reg { - a_uint32_t com_ts:16; -}; - -union ptp_rx_com_timestamp3_reg_u { - a_uint32_t val; - struct ptp_rx_com_timestamp3_reg bf; -}; - -/*[register] PTP_RX_COM_TIMESTAMP4_REG*/ -#define PTP_RX_COM_TIMESTAMP4_REG -#define PTP_RX_COM_TIMESTAMP4_REG_ADDRESS 0x8616 -#define PTP_RX_COM_TIMESTAMP4_REG_NUM 1 -#define PTP_RX_COM_TIMESTAMP4_REG_INC 0x1 -#define PTP_RX_COM_TIMESTAMP4_REG_TYPE REG_TYPE_RW -#define PTP_RX_COM_TIMESTAMP4_REG_DEFAULT 0x0 - /*[field] COM_TS*/ - #define PTP_RX_COM_TIMESTAMP4_REG_COM_TS - #define PTP_RX_COM_TIMESTAMP4_REG_COM_TS_OFFSET 0 - #define PTP_RX_COM_TIMESTAMP4_REG_COM_TS_LEN 16 - #define PTP_RX_COM_TIMESTAMP4_REG_COM_TS_DEFAULT 0x0 - -struct ptp_rx_com_timestamp4_reg { - a_uint32_t com_ts:16; -}; - -union ptp_rx_com_timestamp4_reg_u { - a_uint32_t val; - struct ptp_rx_com_timestamp4_reg bf; -}; - -/*[register] PTP_RX_COM_FRAC_NANO_REG*/ -#define PTP_RX_COM_FRAC_NANO_REG -#define PTP_RX_COM_FRAC_NANO_REG_ADDRESS 0x8617 -#define PTP_RX_COM_FRAC_NANO_REG_NUM 1 -#define PTP_RX_COM_FRAC_NANO_REG_INC 0x1 -#define PTP_RX_COM_FRAC_NANO_REG_TYPE REG_TYPE_RW -#define PTP_RX_COM_FRAC_NANO_REG_DEFAULT 0x0 - /*[field] FRAC_NANO*/ - #define PTP_RX_COM_FRAC_NANO_REG_FRAC_NANO - #define PTP_RX_COM_FRAC_NANO_REG_FRAC_NANO_OFFSET 0 - #define PTP_RX_COM_FRAC_NANO_REG_FRAC_NANO_LEN 16 - #define PTP_RX_COM_FRAC_NANO_REG_FRAC_NANO_DEFAULT 0x0 - -struct ptp_rx_com_frac_nano_reg { - a_uint32_t frac_nano:16; -}; - -union ptp_rx_com_frac_nano_reg_u { - a_uint32_t val; - struct ptp_rx_com_frac_nano_reg bf; -}; - -/*[register] PTP_RX_COM_TIMESTAMP_PRE0_REG*/ -#define PTP_RX_COM_TIMESTAMP_PRE0_REG -#define PTP_RX_COM_TIMESTAMP_PRE0_REG_ADDRESS 0x8618 -#define PTP_RX_COM_TIMESTAMP_PRE0_REG_NUM 1 -#define PTP_RX_COM_TIMESTAMP_PRE0_REG_INC 0x1 -#define PTP_RX_COM_TIMESTAMP_PRE0_REG_TYPE REG_TYPE_RW -#define PTP_RX_COM_TIMESTAMP_PRE0_REG_DEFAULT 0x0 - /*[field] COM_TS_PRE*/ - #define PTP_RX_COM_TIMESTAMP_PRE0_REG_COM_TS_PRE - #define PTP_RX_COM_TIMESTAMP_PRE0_REG_COM_TS_PRE_OFFSET 0 - #define PTP_RX_COM_TIMESTAMP_PRE0_REG_COM_TS_PRE_LEN 16 - #define PTP_RX_COM_TIMESTAMP_PRE0_REG_COM_TS_PRE_DEFAULT 0x0 - -struct ptp_rx_com_timestamp_pre0_reg { - a_uint32_t com_ts_pre:16; -}; - -union ptp_rx_com_timestamp_pre0_reg_u { - a_uint32_t val; - struct ptp_rx_com_timestamp_pre0_reg bf; -}; - -/*[register] PTP_RX_COM_TIMESTAMP_PRE1_REG*/ -#define PTP_RX_COM_TIMESTAMP_PRE1_REG -#define PTP_RX_COM_TIMESTAMP_PRE1_REG_ADDRESS 0x8619 -#define PTP_RX_COM_TIMESTAMP_PRE1_REG_NUM 1 -#define PTP_RX_COM_TIMESTAMP_PRE1_REG_INC 0x1 -#define PTP_RX_COM_TIMESTAMP_PRE1_REG_TYPE REG_TYPE_RW -#define PTP_RX_COM_TIMESTAMP_PRE1_REG_DEFAULT 0x0 - /*[field] COM_TS_PRE*/ - #define PTP_RX_COM_TIMESTAMP_PRE1_REG_COM_TS_PRE - #define PTP_RX_COM_TIMESTAMP_PRE1_REG_COM_TS_PRE_OFFSET 0 - #define PTP_RX_COM_TIMESTAMP_PRE1_REG_COM_TS_PRE_LEN 16 - #define PTP_RX_COM_TIMESTAMP_PRE1_REG_COM_TS_PRE_DEFAULT 0x0 - -struct ptp_rx_com_timestamp_pre1_reg { - a_uint32_t com_ts_pre:16; -}; - -union ptp_rx_com_timestamp_pre1_reg_u { - a_uint32_t val; - struct ptp_rx_com_timestamp_pre1_reg bf; -}; - -/*[register] PTP_RX_COM_TIMESTAMP_PRE2_REG*/ -#define PTP_RX_COM_TIMESTAMP_PRE2_REG -#define PTP_RX_COM_TIMESTAMP_PRE2_REG_ADDRESS 0x861a -#define PTP_RX_COM_TIMESTAMP_PRE2_REG_NUM 1 -#define PTP_RX_COM_TIMESTAMP_PRE2_REG_INC 0x1 -#define PTP_RX_COM_TIMESTAMP_PRE2_REG_TYPE REG_TYPE_RW -#define PTP_RX_COM_TIMESTAMP_PRE2_REG_DEFAULT 0x0 - /*[field] COM_TS_PRE*/ - #define PTP_RX_COM_TIMESTAMP_PRE2_REG_COM_TS_PRE - #define PTP_RX_COM_TIMESTAMP_PRE2_REG_COM_TS_PRE_OFFSET 0 - #define PTP_RX_COM_TIMESTAMP_PRE2_REG_COM_TS_PRE_LEN 16 - #define PTP_RX_COM_TIMESTAMP_PRE2_REG_COM_TS_PRE_DEFAULT 0x0 - -struct ptp_rx_com_timestamp_pre2_reg { - a_uint32_t com_ts_pre:16; -}; - -union ptp_rx_com_timestamp_pre2_reg_u { - a_uint32_t val; - struct ptp_rx_com_timestamp_pre2_reg bf; -}; - -/*[register] PTP_RX_COM_TIMESTAMP_PRE3_REG*/ -#define PTP_RX_COM_TIMESTAMP_PRE3_REG -#define PTP_RX_COM_TIMESTAMP_PRE3_REG_ADDRESS 0x861b -#define PTP_RX_COM_TIMESTAMP_PRE3_REG_NUM 1 -#define PTP_RX_COM_TIMESTAMP_PRE3_REG_INC 0x1 -#define PTP_RX_COM_TIMESTAMP_PRE3_REG_TYPE REG_TYPE_RW -#define PTP_RX_COM_TIMESTAMP_PRE3_REG_DEFAULT 0x0 - /*[field] COM_TS_PRE*/ - #define PTP_RX_COM_TIMESTAMP_PRE3_REG_COM_TS_PRE - #define PTP_RX_COM_TIMESTAMP_PRE3_REG_COM_TS_PRE_OFFSET 0 - #define PTP_RX_COM_TIMESTAMP_PRE3_REG_COM_TS_PRE_LEN 16 - #define PTP_RX_COM_TIMESTAMP_PRE3_REG_COM_TS_PRE_DEFAULT 0x0 - -struct ptp_rx_com_timestamp_pre3_reg { - a_uint32_t com_ts_pre:16; -}; - -union ptp_rx_com_timestamp_pre3_reg_u { - a_uint32_t val; - struct ptp_rx_com_timestamp_pre3_reg bf; -}; - -/*[register] PTP_RX_COM_TIMESTAMP_PRE4_REG*/ -#define PTP_RX_COM_TIMESTAMP_PRE4_REG -#define PTP_RX_COM_TIMESTAMP_PRE4_REG_ADDRESS 0x861c -#define PTP_RX_COM_TIMESTAMP_PRE4_REG_NUM 1 -#define PTP_RX_COM_TIMESTAMP_PRE4_REG_INC 0x1 -#define PTP_RX_COM_TIMESTAMP_PRE4_REG_TYPE REG_TYPE_RW -#define PTP_RX_COM_TIMESTAMP_PRE4_REG_DEFAULT 0x0 - /*[field] COM_TS_PRE*/ - #define PTP_RX_COM_TIMESTAMP_PRE4_REG_COM_TS_PRE - #define PTP_RX_COM_TIMESTAMP_PRE4_REG_COM_TS_PRE_OFFSET 0 - #define PTP_RX_COM_TIMESTAMP_PRE4_REG_COM_TS_PRE_LEN 16 - #define PTP_RX_COM_TIMESTAMP_PRE4_REG_COM_TS_PRE_DEFAULT 0x0 - -struct ptp_rx_com_timestamp_pre4_reg { - a_uint32_t com_ts_pre:16; -}; - -union ptp_rx_com_timestamp_pre4_reg_u { - a_uint32_t val; - struct ptp_rx_com_timestamp_pre4_reg bf; -}; - -/*[register] PTP_RX_COM_FRAC_NANO_PRE_REG*/ -#define PTP_RX_COM_FRAC_NANO_PRE_REG -#define PTP_RX_COM_FRAC_NANO_PRE_REG_ADDRESS 0x861d -#define PTP_RX_COM_FRAC_NANO_PRE_REG_NUM 1 -#define PTP_RX_COM_FRAC_NANO_PRE_REG_INC 0x1 -#define PTP_RX_COM_FRAC_NANO_PRE_REG_TYPE REG_TYPE_RW -#define PTP_RX_COM_FRAC_NANO_PRE_REG_DEFAULT 0x0 - /*[field] FRAC_NANO_PRE*/ - #define PTP_RX_COM_FRAC_NANO_PRE_REG_FRAC_NANO_PRE - #define PTP_RX_COM_FRAC_NANO_PRE_REG_FRAC_NANO_PRE_OFFSET 0 - #define PTP_RX_COM_FRAC_NANO_PRE_REG_FRAC_NANO_PRE_LEN 16 - #define PTP_RX_COM_FRAC_NANO_PRE_REG_FRAC_NANO_PRE_DEFAULT 0x0 - -struct ptp_rx_com_frac_nano_pre_reg { - a_uint32_t frac_nano_pre:16; -}; - -union ptp_rx_com_frac_nano_pre_reg_u { - a_uint32_t val; - struct ptp_rx_com_frac_nano_pre_reg bf; -}; - -/*[register] PTP_RX_Y1731_IDENTIFY_REG*/ -#define PTP_RX_Y1731_IDENTIFY_REG -#define PTP_RX_Y1731_IDENTIFY_REG_ADDRESS 0x861e -#define PTP_RX_Y1731_IDENTIFY_REG_NUM 1 -#define PTP_RX_Y1731_IDENTIFY_REG_INC 0x1 -#define PTP_RX_Y1731_IDENTIFY_REG_TYPE REG_TYPE_RW -#define PTP_RX_Y1731_IDENTIFY_REG_DEFAULT 0x0 - /*[field] IDENTIFY*/ - #define PTP_RX_Y1731_IDENTIFY_REG_IDENTIFY - #define PTP_RX_Y1731_IDENTIFY_REG_IDENTIFY_OFFSET 0 - #define PTP_RX_Y1731_IDENTIFY_REG_IDENTIFY_LEN 16 - #define PTP_RX_Y1731_IDENTIFY_REG_IDENTIFY_DEFAULT 0x0 - -struct ptp_rx_y1731_identify_reg { - a_uint32_t identify:16; -}; - -union ptp_rx_y1731_identify_reg_u { - a_uint32_t val; - struct ptp_rx_y1731_identify_reg bf; -}; - -/*[register] PTP_RX_Y1731_IDENTIFY_PRE_REG*/ -#define PTP_RX_Y1731_IDENTIFY_PRE_REG -#define PTP_RX_Y1731_IDENTIFY_PRE_REG_ADDRESS 0x861f -#define PTP_RX_Y1731_IDENTIFY_PRE_REG_NUM 1 -#define PTP_RX_Y1731_IDENTIFY_PRE_REG_INC 0x1 -#define PTP_RX_Y1731_IDENTIFY_PRE_REG_TYPE REG_TYPE_RW -#define PTP_RX_Y1731_IDENTIFY_PRE_REG_DEFAULT 0x0 - /*[field] IDENTIFY_PRE*/ - #define PTP_RX_Y1731_IDENTIFY_PRE_REG_IDENTIFY_PRE - #define PTP_RX_Y1731_IDENTIFY_PRE_REG_IDENTIFY_PRE_OFFSET 0 - #define PTP_RX_Y1731_IDENTIFY_PRE_REG_IDENTIFY_PRE_LEN 16 - #define PTP_RX_Y1731_IDENTIFY_PRE_REG_IDENTIFY_PRE_DEFAULT 0x0 - -struct ptp_rx_y1731_identify_pre_reg { - a_uint32_t identify_pre:16; -}; - -union ptp_rx_y1731_identify_pre_reg_u { - a_uint32_t val; - struct ptp_rx_y1731_identify_pre_reg bf; -}; - -/*[register] PTP_TX_COM_TS_CTRL_REG*/ -#define PTP_TX_COM_TS_CTRL_REG -#define PTP_TX_COM_TS_CTRL_REG_ADDRESS 0x8620 -#define PTP_TX_COM_TS_CTRL_REG_NUM 1 -#define PTP_TX_COM_TS_CTRL_REG_INC 0x1 -#define PTP_TX_COM_TS_CTRL_REG_TYPE REG_TYPE_RW -#define PTP_TX_COM_TS_CTRL_REG_DEFAULT 0x0 - /*[field] FILT_EN*/ - #define PTP_TX_COM_TS_CTRL_REG_FILT_EN - #define PTP_TX_COM_TS_CTRL_REG_FILT_EN_OFFSET 0 - #define PTP_TX_COM_TS_CTRL_REG_FILT_EN_LEN 1 - #define PTP_TX_COM_TS_CTRL_REG_FILT_EN_DEFAULT 0x0 - /*[field] MAC_LENGTHTYPE_EN*/ - #define PTP_TX_COM_TS_CTRL_REG_MAC_LENGTHTYPE_EN - #define PTP_TX_COM_TS_CTRL_REG_MAC_LENGTHTYPE_EN_OFFSET 1 - #define PTP_TX_COM_TS_CTRL_REG_MAC_LENGTHTYPE_EN_LEN 1 - #define PTP_TX_COM_TS_CTRL_REG_MAC_LENGTHTYPE_EN_DEFAULT 0x0 - /*[field] MAC_DA_EN*/ - #define PTP_TX_COM_TS_CTRL_REG_MAC_DA_EN - #define PTP_TX_COM_TS_CTRL_REG_MAC_DA_EN_OFFSET 2 - #define PTP_TX_COM_TS_CTRL_REG_MAC_DA_EN_LEN 1 - #define PTP_TX_COM_TS_CTRL_REG_MAC_DA_EN_DEFAULT 0x0 - /*[field] MAC_PTP_FILT_EN*/ - #define PTP_TX_COM_TS_CTRL_REG_MAC_PTP_FILT_EN - #define PTP_TX_COM_TS_CTRL_REG_MAC_PTP_FILT_EN_OFFSET 3 - #define PTP_TX_COM_TS_CTRL_REG_MAC_PTP_FILT_EN_LEN 1 - #define PTP_TX_COM_TS_CTRL_REG_MAC_PTP_FILT_EN_DEFAULT 0x0 - /*[field] IPV4_LAYER4_PROTOCOL_EN*/ - #define PTP_TX_COM_TS_CTRL_REG_IPV4_LAYER4_PROTOCOL_EN - #define PTP_TX_COM_TS_CTRL_REG_IPV4_LAYER4_PROTOCOL_EN_OFFSET 4 - #define PTP_TX_COM_TS_CTRL_REG_IPV4_LAYER4_PROTOCOL_EN_LEN 1 - #define PTP_TX_COM_TS_CTRL_REG_IPV4_LAYER4_PROTOCOL_EN_DEFAULT 0x0 - /*[field] IPV4_DA_EN*/ - #define PTP_TX_COM_TS_CTRL_REG_IPV4_DA_EN - #define PTP_TX_COM_TS_CTRL_REG_IPV4_DA_EN_OFFSET 5 - #define PTP_TX_COM_TS_CTRL_REG_IPV4_DA_EN_LEN 1 - #define PTP_TX_COM_TS_CTRL_REG_IPV4_DA_EN_DEFAULT 0x0 - /*[field] IPV4_PTP_FILT_EN*/ - #define PTP_TX_COM_TS_CTRL_REG_IPV4_PTP_FILT_EN - #define PTP_TX_COM_TS_CTRL_REG_IPV4_PTP_FILT_EN_OFFSET 6 - #define PTP_TX_COM_TS_CTRL_REG_IPV4_PTP_FILT_EN_LEN 1 - #define PTP_TX_COM_TS_CTRL_REG_IPV4_PTP_FILT_EN_DEFAULT 0x0 - /*[field] IPV6_NEXT_HEADER_EN*/ - #define PTP_TX_COM_TS_CTRL_REG_IPV6_NEXT_HEADER_EN - #define PTP_TX_COM_TS_CTRL_REG_IPV6_NEXT_HEADER_EN_OFFSET 7 - #define PTP_TX_COM_TS_CTRL_REG_IPV6_NEXT_HEADER_EN_LEN 1 - #define PTP_TX_COM_TS_CTRL_REG_IPV6_NEXT_HEADER_EN_DEFAULT 0x0 - /*[field] IPV6_DA_EN*/ - #define PTP_TX_COM_TS_CTRL_REG_IPV6_DA_EN - #define PTP_TX_COM_TS_CTRL_REG_IPV6_DA_EN_OFFSET 8 - #define PTP_TX_COM_TS_CTRL_REG_IPV6_DA_EN_LEN 1 - #define PTP_TX_COM_TS_CTRL_REG_IPV6_DA_EN_DEFAULT 0x0 - /*[field] IPV6_PTP_FILT_EN*/ - #define PTP_TX_COM_TS_CTRL_REG_IPV6_PTP_FILT_EN - #define PTP_TX_COM_TS_CTRL_REG_IPV6_PTP_FILT_EN_OFFSET 9 - #define PTP_TX_COM_TS_CTRL_REG_IPV6_PTP_FILT_EN_LEN 1 - #define PTP_TX_COM_TS_CTRL_REG_IPV6_PTP_FILT_EN_DEFAULT 0x0 - /*[field] UDP_DPORT_EN*/ - #define PTP_TX_COM_TS_CTRL_REG_UDP_DPORT_EN - #define PTP_TX_COM_TS_CTRL_REG_UDP_DPORT_EN_OFFSET 10 - #define PTP_TX_COM_TS_CTRL_REG_UDP_DPORT_EN_LEN 1 - #define PTP_TX_COM_TS_CTRL_REG_UDP_DPORT_EN_DEFAULT 0x0 - /*[field] UDP_PTP_EVENT_FILT_EN*/ - #define PTP_TX_COM_TS_CTRL_REG_UDP_PTP_EVENT_FILT_EN - #define PTP_TX_COM_TS_CTRL_REG_UDP_PTP_EVENT_FILT_EN_OFFSET 11 - #define PTP_TX_COM_TS_CTRL_REG_UDP_PTP_EVENT_FILT_EN_LEN 1 - #define PTP_TX_COM_TS_CTRL_REG_UDP_PTP_EVENT_FILT_EN_DEFAULT 0x0 - /*[field] Y1731_EN*/ - #define PTP_TX_COM_TS_CTRL_REG_Y1731_EN - #define PTP_TX_COM_TS_CTRL_REG_Y1731_EN_OFFSET 12 - #define PTP_TX_COM_TS_CTRL_REG_Y1731_EN_LEN 1 - #define PTP_TX_COM_TS_CTRL_REG_Y1731_EN_DEFAULT 0x0 - /*[field] Y1731_INSERT_TS_EN*/ - #define PTP_TX_COM_TS_CTRL_REG_Y1731_INSERT_TS_EN - #define PTP_TX_COM_TS_CTRL_REG_Y1731_INSERT_TS_EN_OFFSET 13 - #define PTP_TX_COM_TS_CTRL_REG_Y1731_INSERT_TS_EN_LEN 1 - #define PTP_TX_COM_TS_CTRL_REG_Y1731_INSERT_TS_EN_DEFAULT 0x0 - /*[field] Y1731_SA_CHK_EN*/ - #define PTP_TX_COM_TS_CTRL_REG_Y1731_SA_CHK_EN - #define PTP_TX_COM_TS_CTRL_REG_Y1731_SA_CHK_EN_OFFSET 14 - #define PTP_TX_COM_TS_CTRL_REG_Y1731_SA_CHK_EN_LEN 1 - #define PTP_TX_COM_TS_CTRL_REG_Y1731_SA_CHK_EN_DEFAULT 0x0 - /*[field] PW_MAC_EN*/ - #define PTP_TX_COM_TS_CTRL_REG_PW_MAC_EN - #define PTP_TX_COM_TS_CTRL_REG_PW_MAC_EN_OFFSET 15 - #define PTP_TX_COM_TS_CTRL_REG_PW_MAC_EN_LEN 1 - #define PTP_TX_COM_TS_CTRL_REG_PW_MAC_EN_DEFAULT 0x0 - -struct ptp_tx_com_ts_ctrl_reg { - a_uint32_t filt_en:1; - a_uint32_t mac_lengthtype_en:1; - a_uint32_t mac_da_en:1; - a_uint32_t mac_ptp_filt_en:1; - a_uint32_t ipv4_layer4_protocol_en:1; - a_uint32_t ipv4_da_en:1; - a_uint32_t ipv4_ptp_filt_en:1; - a_uint32_t ipv6_next_header_en:1; - a_uint32_t ipv6_da_en:1; - a_uint32_t ipv6_ptp_filt_en:1; - a_uint32_t udp_dport_en:1; - a_uint32_t udp_ptp_event_filt_en:1; - a_uint32_t y1731_en:1; - a_uint32_t y1731_insert_ts_en:1; - a_uint32_t y1731_sa_chk_en:1; - a_uint32_t pw_mac_en:1; -}; - -union ptp_tx_com_ts_ctrl_reg_u { - a_uint32_t val; - struct ptp_tx_com_ts_ctrl_reg bf; -}; - -/*[register] PTP_TX_FILT_MAC_DA0_REG*/ -#define PTP_TX_FILT_MAC_DA0_REG -#define PTP_TX_FILT_MAC_DA0_REG_ADDRESS 0x8621 -#define PTP_TX_FILT_MAC_DA0_REG_NUM 1 -#define PTP_TX_FILT_MAC_DA0_REG_INC 0x1 -#define PTP_TX_FILT_MAC_DA0_REG_TYPE REG_TYPE_RW -#define PTP_TX_FILT_MAC_DA0_REG_DEFAULT 0x0 - /*[field] MAC_ADDR*/ - #define PTP_TX_FILT_MAC_DA0_REG_MAC_ADDR - #define PTP_TX_FILT_MAC_DA0_REG_MAC_ADDR_OFFSET 0 - #define PTP_TX_FILT_MAC_DA0_REG_MAC_ADDR_LEN 16 - #define PTP_TX_FILT_MAC_DA0_REG_MAC_ADDR_DEFAULT 0x0 - -struct ptp_tx_filt_mac_da0_reg { - a_uint32_t mac_addr:16; -}; - -union ptp_tx_filt_mac_da0_reg_u { - a_uint32_t val; - struct ptp_tx_filt_mac_da0_reg bf; -}; - -/*[register] PTP_TX_FILT_MAC_DA1_REG*/ -#define PTP_TX_FILT_MAC_DA1_REG -#define PTP_TX_FILT_MAC_DA1_REG_ADDRESS 0x8622 -#define PTP_TX_FILT_MAC_DA1_REG_NUM 1 -#define PTP_TX_FILT_MAC_DA1_REG_INC 0x1 -#define PTP_TX_FILT_MAC_DA1_REG_TYPE REG_TYPE_RW -#define PTP_TX_FILT_MAC_DA1_REG_DEFAULT 0x0 - /*[field] MAC_ADDR*/ - #define PTP_TX_FILT_MAC_DA1_REG_MAC_ADDR - #define PTP_TX_FILT_MAC_DA1_REG_MAC_ADDR_OFFSET 0 - #define PTP_TX_FILT_MAC_DA1_REG_MAC_ADDR_LEN 16 - #define PTP_TX_FILT_MAC_DA1_REG_MAC_ADDR_DEFAULT 0x0 - -struct ptp_tx_filt_mac_da1_reg { - a_uint32_t mac_addr:16; -}; - -union ptp_tx_filt_mac_da1_reg_u { - a_uint32_t val; - struct ptp_tx_filt_mac_da1_reg bf; -}; - -/*[register] PTP_TX_FILT_MAC_DA2_REG*/ -#define PTP_TX_FILT_MAC_DA2_REG -#define PTP_TX_FILT_MAC_DA2_REG_ADDRESS 0x8623 -#define PTP_TX_FILT_MAC_DA2_REG_NUM 1 -#define PTP_TX_FILT_MAC_DA2_REG_INC 0x1 -#define PTP_TX_FILT_MAC_DA2_REG_TYPE REG_TYPE_RW -#define PTP_TX_FILT_MAC_DA2_REG_DEFAULT 0x0 - /*[field] MAC_ADDR*/ - #define PTP_TX_FILT_MAC_DA2_REG_MAC_ADDR - #define PTP_TX_FILT_MAC_DA2_REG_MAC_ADDR_OFFSET 0 - #define PTP_TX_FILT_MAC_DA2_REG_MAC_ADDR_LEN 16 - #define PTP_TX_FILT_MAC_DA2_REG_MAC_ADDR_DEFAULT 0x0 - -struct ptp_tx_filt_mac_da2_reg { - a_uint32_t mac_addr:16; -}; - -union ptp_tx_filt_mac_da2_reg_u { - a_uint32_t val; - struct ptp_tx_filt_mac_da2_reg bf; -}; - -/*[register] PTP_TX_FILT_IPV4_DA0_REG*/ -#define PTP_TX_FILT_IPV4_DA0_REG -#define PTP_TX_FILT_IPV4_DA0_REG_ADDRESS 0x8624 -#define PTP_TX_FILT_IPV4_DA0_REG_NUM 1 -#define PTP_TX_FILT_IPV4_DA0_REG_INC 0x1 -#define PTP_TX_FILT_IPV4_DA0_REG_TYPE REG_TYPE_RW -#define PTP_TX_FILT_IPV4_DA0_REG_DEFAULT 0x0 - /*[field] IP_ADDR*/ - #define PTP_TX_FILT_IPV4_DA0_REG_IP_ADDR - #define PTP_TX_FILT_IPV4_DA0_REG_IP_ADDR_OFFSET 0 - #define PTP_TX_FILT_IPV4_DA0_REG_IP_ADDR_LEN 16 - #define PTP_TX_FILT_IPV4_DA0_REG_IP_ADDR_DEFAULT 0x0 - -struct ptp_tx_filt_ipv4_da0_reg { - a_uint32_t ip_addr:16; -}; - -union ptp_tx_filt_ipv4_da0_reg_u { - a_uint32_t val; - struct ptp_tx_filt_ipv4_da0_reg bf; -}; - -/*[register] PTP_TX_FILT_IPV4_DA1_REG*/ -#define PTP_TX_FILT_IPV4_DA1_REG -#define PTP_TX_FILT_IPV4_DA1_REG_ADDRESS 0x8625 -#define PTP_TX_FILT_IPV4_DA1_REG_NUM 1 -#define PTP_TX_FILT_IPV4_DA1_REG_INC 0x1 -#define PTP_TX_FILT_IPV4_DA1_REG_TYPE REG_TYPE_RW -#define PTP_TX_FILT_IPV4_DA1_REG_DEFAULT 0x0 - /*[field] IP_ADDR*/ - #define PTP_TX_FILT_IPV4_DA1_REG_IP_ADDR - #define PTP_TX_FILT_IPV4_DA1_REG_IP_ADDR_OFFSET 0 - #define PTP_TX_FILT_IPV4_DA1_REG_IP_ADDR_LEN 16 - #define PTP_TX_FILT_IPV4_DA1_REG_IP_ADDR_DEFAULT 0x0 - -struct ptp_tx_filt_ipv4_da1_reg { - a_uint32_t ip_addr:16; -}; - -union ptp_tx_filt_ipv4_da1_reg_u { - a_uint32_t val; - struct ptp_tx_filt_ipv4_da1_reg bf; -}; - -/*[register] PTP_TX_FILT_IPV6_DA0_REG*/ -#define PTP_TX_FILT_IPV6_DA0_REG -#define PTP_TX_FILT_IPV6_DA0_REG_ADDRESS 0x8626 -#define PTP_TX_FILT_IPV6_DA0_REG_NUM 1 -#define PTP_TX_FILT_IPV6_DA0_REG_INC 0x1 -#define PTP_TX_FILT_IPV6_DA0_REG_TYPE REG_TYPE_RW -#define PTP_TX_FILT_IPV6_DA0_REG_DEFAULT 0x0 - /*[field] IP_ADDR*/ - #define PTP_TX_FILT_IPV6_DA0_REG_IP_ADDR - #define PTP_TX_FILT_IPV6_DA0_REG_IP_ADDR_OFFSET 0 - #define PTP_TX_FILT_IPV6_DA0_REG_IP_ADDR_LEN 16 - #define PTP_TX_FILT_IPV6_DA0_REG_IP_ADDR_DEFAULT 0x0 - -struct ptp_tx_filt_ipv6_da0_reg { - a_uint32_t ip_addr:16; -}; - -union ptp_tx_filt_ipv6_da0_reg_u { - a_uint32_t val; - struct ptp_tx_filt_ipv6_da0_reg bf; -}; - -/*[register] PTP_TX_FILT_IPV6_DA1_REG*/ -#define PTP_TX_FILT_IPV6_DA1_REG -#define PTP_TX_FILT_IPV6_DA1_REG_ADDRESS 0x8627 -#define PTP_TX_FILT_IPV6_DA1_REG_NUM 1 -#define PTP_TX_FILT_IPV6_DA1_REG_INC 0x1 -#define PTP_TX_FILT_IPV6_DA1_REG_TYPE REG_TYPE_RW -#define PTP_TX_FILT_IPV6_DA1_REG_DEFAULT 0x0 - /*[field] IP_ADDR*/ - #define PTP_TX_FILT_IPV6_DA1_REG_IP_ADDR - #define PTP_TX_FILT_IPV6_DA1_REG_IP_ADDR_OFFSET 0 - #define PTP_TX_FILT_IPV6_DA1_REG_IP_ADDR_LEN 16 - #define PTP_TX_FILT_IPV6_DA1_REG_IP_ADDR_DEFAULT 0x0 - -struct ptp_tx_filt_ipv6_da1_reg { - a_uint32_t ip_addr:16; -}; - -union ptp_tx_filt_ipv6_da1_reg_u { - a_uint32_t val; - struct ptp_tx_filt_ipv6_da1_reg bf; -}; - -/*[register] PTP_TX_FILT_IPV6_DA2_REG*/ -#define PTP_TX_FILT_IPV6_DA2_REG -#define PTP_TX_FILT_IPV6_DA2_REG_ADDRESS 0x8628 -#define PTP_TX_FILT_IPV6_DA2_REG_NUM 1 -#define PTP_TX_FILT_IPV6_DA2_REG_INC 0x1 -#define PTP_TX_FILT_IPV6_DA2_REG_TYPE REG_TYPE_RW -#define PTP_TX_FILT_IPV6_DA2_REG_DEFAULT 0x0 - /*[field] IP_ADDR*/ - #define PTP_TX_FILT_IPV6_DA2_REG_IP_ADDR - #define PTP_TX_FILT_IPV6_DA2_REG_IP_ADDR_OFFSET 0 - #define PTP_TX_FILT_IPV6_DA2_REG_IP_ADDR_LEN 16 - #define PTP_TX_FILT_IPV6_DA2_REG_IP_ADDR_DEFAULT 0x0 - -struct ptp_tx_filt_ipv6_da2_reg { - a_uint32_t ip_addr:16; -}; - -union ptp_tx_filt_ipv6_da2_reg_u { - a_uint32_t val; - struct ptp_tx_filt_ipv6_da2_reg bf; -}; - -/*[register] PTP_TX_FILT_IPV6_DA3_REG*/ -#define PTP_TX_FILT_IPV6_DA3_REG -#define PTP_TX_FILT_IPV6_DA3_REG_ADDRESS 0x8629 -#define PTP_TX_FILT_IPV6_DA3_REG_NUM 1 -#define PTP_TX_FILT_IPV6_DA3_REG_INC 0x1 -#define PTP_TX_FILT_IPV6_DA3_REG_TYPE REG_TYPE_RW -#define PTP_TX_FILT_IPV6_DA3_REG_DEFAULT 0x0 - /*[field] IP_ADDR*/ - #define PTP_TX_FILT_IPV6_DA3_REG_IP_ADDR - #define PTP_TX_FILT_IPV6_DA3_REG_IP_ADDR_OFFSET 0 - #define PTP_TX_FILT_IPV6_DA3_REG_IP_ADDR_LEN 16 - #define PTP_TX_FILT_IPV6_DA3_REG_IP_ADDR_DEFAULT 0x0 - -struct ptp_tx_filt_ipv6_da3_reg { - a_uint32_t ip_addr:16; -}; - -union ptp_tx_filt_ipv6_da3_reg_u { - a_uint32_t val; - struct ptp_tx_filt_ipv6_da3_reg bf; -}; - -/*[register] PTP_TX_FILT_IPV6_DA4_REG*/ -#define PTP_TX_FILT_IPV6_DA4_REG -#define PTP_TX_FILT_IPV6_DA4_REG_ADDRESS 0x862a -#define PTP_TX_FILT_IPV6_DA4_REG_NUM 1 -#define PTP_TX_FILT_IPV6_DA4_REG_INC 0x1 -#define PTP_TX_FILT_IPV6_DA4_REG_TYPE REG_TYPE_RW -#define PTP_TX_FILT_IPV6_DA4_REG_DEFAULT 0x0 - /*[field] IP_ADDR*/ - #define PTP_TX_FILT_IPV6_DA4_REG_IP_ADDR - #define PTP_TX_FILT_IPV6_DA4_REG_IP_ADDR_OFFSET 0 - #define PTP_TX_FILT_IPV6_DA4_REG_IP_ADDR_LEN 16 - #define PTP_TX_FILT_IPV6_DA4_REG_IP_ADDR_DEFAULT 0x0 - -struct ptp_tx_filt_ipv6_da4_reg { - a_uint32_t ip_addr:16; -}; - -union ptp_tx_filt_ipv6_da4_reg_u { - a_uint32_t val; - struct ptp_tx_filt_ipv6_da4_reg bf; -}; - -/*[register] PTP_TX_FILT_IPV6_DA5_REG*/ -#define PTP_TX_FILT_IPV6_DA5_REG -#define PTP_TX_FILT_IPV6_DA5_REG_ADDRESS 0x862b -#define PTP_TX_FILT_IPV6_DA5_REG_NUM 1 -#define PTP_TX_FILT_IPV6_DA5_REG_INC 0x1 -#define PTP_TX_FILT_IPV6_DA5_REG_TYPE REG_TYPE_RW -#define PTP_TX_FILT_IPV6_DA5_REG_DEFAULT 0x0 - /*[field] IP_ADDR*/ - #define PTP_TX_FILT_IPV6_DA5_REG_IP_ADDR - #define PTP_TX_FILT_IPV6_DA5_REG_IP_ADDR_OFFSET 0 - #define PTP_TX_FILT_IPV6_DA5_REG_IP_ADDR_LEN 16 - #define PTP_TX_FILT_IPV6_DA5_REG_IP_ADDR_DEFAULT 0x0 - -struct ptp_tx_filt_ipv6_da5_reg { - a_uint32_t ip_addr:16; -}; - -union ptp_tx_filt_ipv6_da5_reg_u { - a_uint32_t val; - struct ptp_tx_filt_ipv6_da5_reg bf; -}; - -/*[register] PTP_TX_FILT_IPV6_DA6_REG*/ -#define PTP_TX_FILT_IPV6_DA6_REG -#define PTP_TX_FILT_IPV6_DA6_REG_ADDRESS 0x862c -#define PTP_TX_FILT_IPV6_DA6_REG_NUM 1 -#define PTP_TX_FILT_IPV6_DA6_REG_INC 0x1 -#define PTP_TX_FILT_IPV6_DA6_REG_TYPE REG_TYPE_RW -#define PTP_TX_FILT_IPV6_DA6_REG_DEFAULT 0x0 - /*[field] IP_ADDR*/ - #define PTP_TX_FILT_IPV6_DA6_REG_IP_ADDR - #define PTP_TX_FILT_IPV6_DA6_REG_IP_ADDR_OFFSET 0 - #define PTP_TX_FILT_IPV6_DA6_REG_IP_ADDR_LEN 16 - #define PTP_TX_FILT_IPV6_DA6_REG_IP_ADDR_DEFAULT 0x0 - -struct ptp_tx_filt_ipv6_da6_reg { - a_uint32_t ip_addr:16; -}; - -union ptp_tx_filt_ipv6_da6_reg_u { - a_uint32_t val; - struct ptp_tx_filt_ipv6_da6_reg bf; -}; - -/*[register] PTP_TX_FILT_IPV6_DA7_REG*/ -#define PTP_TX_FILT_IPV6_DA7_REG -#define PTP_TX_FILT_IPV6_DA7_REG_ADDRESS 0x862d -#define PTP_TX_FILT_IPV6_DA7_REG_NUM 1 -#define PTP_TX_FILT_IPV6_DA7_REG_INC 0x1 -#define PTP_TX_FILT_IPV6_DA7_REG_TYPE REG_TYPE_RW -#define PTP_TX_FILT_IPV6_DA7_REG_DEFAULT 0x0 - /*[field] IP_ADDR*/ - #define PTP_TX_FILT_IPV6_DA7_REG_IP_ADDR - #define PTP_TX_FILT_IPV6_DA7_REG_IP_ADDR_OFFSET 0 - #define PTP_TX_FILT_IPV6_DA7_REG_IP_ADDR_LEN 16 - #define PTP_TX_FILT_IPV6_DA7_REG_IP_ADDR_DEFAULT 0x0 - -struct ptp_tx_filt_ipv6_da7_reg { - a_uint32_t ip_addr:16; -}; - -union ptp_tx_filt_ipv6_da7_reg_u { - a_uint32_t val; - struct ptp_tx_filt_ipv6_da7_reg bf; -}; - -/*[register] PTP_TX_FILT_MAC_LENGTHTYPE_REG*/ -#define PTP_TX_FILT_MAC_LENGTHTYPE_REG -#define PTP_TX_FILT_MAC_LENGTHTYPE_REG_ADDRESS 0x862e -#define PTP_TX_FILT_MAC_LENGTHTYPE_REG_NUM 1 -#define PTP_TX_FILT_MAC_LENGTHTYPE_REG_INC 0x1 -#define PTP_TX_FILT_MAC_LENGTHTYPE_REG_TYPE REG_TYPE_RW -#define PTP_TX_FILT_MAC_LENGTHTYPE_REG_DEFAULT 0x0 - /*[field] LENGTH_TYPE*/ - #define PTP_TX_FILT_MAC_LENGTHTYPE_REG_LENGTH_TYPE - #define PTP_TX_FILT_MAC_LENGTHTYPE_REG_LENGTH_TYPE_OFFSET 0 - #define PTP_TX_FILT_MAC_LENGTHTYPE_REG_LENGTH_TYPE_LEN 16 - #define PTP_TX_FILT_MAC_LENGTHTYPE_REG_LENGTH_TYPE_DEFAULT 0x0 - -struct ptp_tx_filt_mac_lengthtype_reg { - a_uint32_t length_type:16; -}; - -union ptp_tx_filt_mac_lengthtype_reg_u { - a_uint32_t val; - struct ptp_tx_filt_mac_lengthtype_reg bf; -}; - -/*[register] PTP_TX_FILT_LAYER4_PROTOCOL_REG*/ -#define PTP_TX_FILT_LAYER4_PROTOCOL_REG -#define PTP_TX_FILT_LAYER4_PROTOCOL_REG_ADDRESS 0x862f -#define PTP_TX_FILT_LAYER4_PROTOCOL_REG_NUM 1 -#define PTP_TX_FILT_LAYER4_PROTOCOL_REG_INC 0x1 -#define PTP_TX_FILT_LAYER4_PROTOCOL_REG_TYPE REG_TYPE_RW -#define PTP_TX_FILT_LAYER4_PROTOCOL_REG_DEFAULT 0x0 - /*[field] L4_PROTOCOL*/ - #define PTP_TX_FILT_LAYER4_PROTOCOL_REG_L4_PROTOCOL - #define PTP_TX_FILT_LAYER4_PROTOCOL_REG_L4_PROTOCOL_OFFSET 0 - #define PTP_TX_FILT_LAYER4_PROTOCOL_REG_L4_PROTOCOL_LEN 16 - #define PTP_TX_FILT_LAYER4_PROTOCOL_REG_L4_PROTOCOL_DEFAULT 0x0 - -struct ptp_tx_filt_layer4_protocol_reg { - a_uint32_t l4_protocol:16; -}; - -union ptp_tx_filt_layer4_protocol_reg_u { - a_uint32_t val; - struct ptp_tx_filt_layer4_protocol_reg bf; -}; - -/*[register] PTP_TX_FILT_UDP_PORT_REG*/ -#define PTP_TX_FILT_UDP_PORT_REG -#define PTP_TX_FILT_UDP_PORT_REG_ADDRESS 0x8630 -#define PTP_TX_FILT_UDP_PORT_REG_NUM 1 -#define PTP_TX_FILT_UDP_PORT_REG_INC 0x1 -#define PTP_TX_FILT_UDP_PORT_REG_TYPE REG_TYPE_RW -#define PTP_TX_FILT_UDP_PORT_REG_DEFAULT 0x0 - /*[field] UDP_PORT*/ - #define PTP_TX_FILT_UDP_PORT_REG_UDP_PORT - #define PTP_TX_FILT_UDP_PORT_REG_UDP_PORT_OFFSET 0 - #define PTP_TX_FILT_UDP_PORT_REG_UDP_PORT_LEN 16 - #define PTP_TX_FILT_UDP_PORT_REG_UDP_PORT_DEFAULT 0x0 - -struct ptp_tx_filt_udp_port_reg { - a_uint32_t udp_port:16; -}; - -union ptp_tx_filt_udp_port_reg_u { - a_uint32_t val; - struct ptp_tx_filt_udp_port_reg bf; -}; - -/*[register] PTP_TX_COM_TS_STATUS_REG*/ -#define PTP_TX_COM_TS_STATUS_REG -#define PTP_TX_COM_TS_STATUS_REG_ADDRESS 0x8631 -#define PTP_TX_COM_TS_STATUS_REG_NUM 1 -#define PTP_TX_COM_TS_STATUS_REG_INC 0x1 -#define PTP_TX_COM_TS_STATUS_REG_TYPE REG_TYPE_RW -#define PTP_TX_COM_TS_STATUS_REG_DEFAULT 0x0 - /*[field] MAC_LENGTHTYPE*/ - #define PTP_TX_COM_TS_STATUS_REG_MAC_LENGTHTYPE - #define PTP_TX_COM_TS_STATUS_REG_MAC_LENGTHTYPE_OFFSET 0 - #define PTP_TX_COM_TS_STATUS_REG_MAC_LENGTHTYPE_LEN 1 - #define PTP_TX_COM_TS_STATUS_REG_MAC_LENGTHTYPE_DEFAULT 0x0 - /*[field] MAC_DA*/ - #define PTP_TX_COM_TS_STATUS_REG_MAC_DA - #define PTP_TX_COM_TS_STATUS_REG_MAC_DA_OFFSET 1 - #define PTP_TX_COM_TS_STATUS_REG_MAC_DA_LEN 1 - #define PTP_TX_COM_TS_STATUS_REG_MAC_DA_DEFAULT 0x0 - /*[field] MAC_PTP_PRIM_ADDR*/ - #define PTP_TX_COM_TS_STATUS_REG_MAC_PTP_PRIM_ADDR - #define PTP_TX_COM_TS_STATUS_REG_MAC_PTP_PRIM_ADDR_OFFSET 2 - #define PTP_TX_COM_TS_STATUS_REG_MAC_PTP_PRIM_ADDR_LEN 1 - #define PTP_TX_COM_TS_STATUS_REG_MAC_PTP_PRIM_ADDR_DEFAULT 0x0 - /*[field] MAC_PTP_PDELAY_ADDR*/ - #define PTP_TX_COM_TS_STATUS_REG_MAC_PTP_PDELAY_ADDR - #define PTP_TX_COM_TS_STATUS_REG_MAC_PTP_PDELAY_ADDR_OFFSET 3 - #define PTP_TX_COM_TS_STATUS_REG_MAC_PTP_PDELAY_ADDR_LEN 1 - #define PTP_TX_COM_TS_STATUS_REG_MAC_PTP_PDELAY_ADDR_DEFAULT 0x0 - /*[field] IPV4_LAYER4_PROTOCOL*/ - #define PTP_TX_COM_TS_STATUS_REG_IPV4_LAYER4_PROTOCOL - #define PTP_TX_COM_TS_STATUS_REG_IPV4_LAYER4_PROTOCOL_OFFSET 4 - #define PTP_TX_COM_TS_STATUS_REG_IPV4_LAYER4_PROTOCOL_LEN 1 - #define PTP_TX_COM_TS_STATUS_REG_IPV4_LAYER4_PROTOCOL_DEFAULT 0x0 - /*[field] IPV4_DA*/ - #define PTP_TX_COM_TS_STATUS_REG_IPV4_DA - #define PTP_TX_COM_TS_STATUS_REG_IPV4_DA_OFFSET 5 - #define PTP_TX_COM_TS_STATUS_REG_IPV4_DA_LEN 1 - #define PTP_TX_COM_TS_STATUS_REG_IPV4_DA_DEFAULT 0x0 - /*[field] IPV4_PTP_PRIM_ADDR*/ - #define PTP_TX_COM_TS_STATUS_REG_IPV4_PTP_PRIM_ADDR - #define PTP_TX_COM_TS_STATUS_REG_IPV4_PTP_PRIM_ADDR_OFFSET 6 - #define PTP_TX_COM_TS_STATUS_REG_IPV4_PTP_PRIM_ADDR_LEN 1 - #define PTP_TX_COM_TS_STATUS_REG_IPV4_PTP_PRIM_ADDR_DEFAULT 0x0 - /*[field] IPV4_PTP_PDELAY_ADDR*/ - #define PTP_TX_COM_TS_STATUS_REG_IPV4_PTP_PDELAY_ADDR - #define PTP_TX_COM_TS_STATUS_REG_IPV4_PTP_PDELAY_ADDR_OFFSET 7 - #define PTP_TX_COM_TS_STATUS_REG_IPV4_PTP_PDELAY_ADDR_LEN 1 - #define PTP_TX_COM_TS_STATUS_REG_IPV4_PTP_PDELAY_ADDR_DEFAULT 0x0 - /*[field] IPV6_NEXT_HEADER*/ - #define PTP_TX_COM_TS_STATUS_REG_IPV6_NEXT_HEADER - #define PTP_TX_COM_TS_STATUS_REG_IPV6_NEXT_HEADER_OFFSET 8 - #define PTP_TX_COM_TS_STATUS_REG_IPV6_NEXT_HEADER_LEN 1 - #define PTP_TX_COM_TS_STATUS_REG_IPV6_NEXT_HEADER_DEFAULT 0x0 - /*[field] IPV6_DA*/ - #define PTP_TX_COM_TS_STATUS_REG_IPV6_DA - #define PTP_TX_COM_TS_STATUS_REG_IPV6_DA_OFFSET 9 - #define PTP_TX_COM_TS_STATUS_REG_IPV6_DA_LEN 1 - #define PTP_TX_COM_TS_STATUS_REG_IPV6_DA_DEFAULT 0x0 - /*[field] IPV6_PTP_PRIM_ADDR*/ - #define PTP_TX_COM_TS_STATUS_REG_IPV6_PTP_PRIM_ADDR - #define PTP_TX_COM_TS_STATUS_REG_IPV6_PTP_PRIM_ADDR_OFFSET 10 - #define PTP_TX_COM_TS_STATUS_REG_IPV6_PTP_PRIM_ADDR_LEN 1 - #define PTP_TX_COM_TS_STATUS_REG_IPV6_PTP_PRIM_ADDR_DEFAULT 0x0 - /*[field] IPV6_PTP_PDELAY_ADDR*/ - #define PTP_TX_COM_TS_STATUS_REG_IPV6_PTP_PDELAY_ADDR - #define PTP_TX_COM_TS_STATUS_REG_IPV6_PTP_PDELAY_ADDR_OFFSET 11 - #define PTP_TX_COM_TS_STATUS_REG_IPV6_PTP_PDELAY_ADDR_LEN 1 - #define PTP_TX_COM_TS_STATUS_REG_IPV6_PTP_PDELAY_ADDR_DEFAULT 0x0 - /*[field] UDP_DPORT*/ - #define PTP_TX_COM_TS_STATUS_REG_UDP_DPORT - #define PTP_TX_COM_TS_STATUS_REG_UDP_DPORT_OFFSET 12 - #define PTP_TX_COM_TS_STATUS_REG_UDP_DPORT_LEN 1 - #define PTP_TX_COM_TS_STATUS_REG_UDP_DPORT_DEFAULT 0x0 - /*[field] UDP_PTP_EVENT_DPORT*/ - #define PTP_TX_COM_TS_STATUS_REG_UDP_PTP_EVENT_DPORT - #define PTP_TX_COM_TS_STATUS_REG_UDP_PTP_EVENT_DPORT_OFFSET 13 - #define PTP_TX_COM_TS_STATUS_REG_UDP_PTP_EVENT_DPORT_LEN 1 - #define PTP_TX_COM_TS_STATUS_REG_UDP_PTP_EVENT_DPORT_DEFAULT 0x0 - /*[field] Y1731_MACH*/ - #define PTP_TX_COM_TS_STATUS_REG_Y1731_MACH - #define PTP_TX_COM_TS_STATUS_REG_Y1731_MACH_OFFSET 14 - #define PTP_TX_COM_TS_STATUS_REG_Y1731_MACH_LEN 1 - #define PTP_TX_COM_TS_STATUS_REG_Y1731_MACH_DEFAULT 0x0 - -struct ptp_tx_com_ts_status_reg { - a_uint32_t mac_lengthtype:1; - a_uint32_t mac_da:1; - a_uint32_t mac_ptp_prim_addr:1; - a_uint32_t mac_ptp_pdelay_addr:1; - a_uint32_t ipv4_layer4_protocol:1; - a_uint32_t ipv4_da:1; - a_uint32_t ipv4_ptp_prim_addr:1; - a_uint32_t ipv4_ptp_pdelay_addr:1; - a_uint32_t ipv6_next_header:1; - a_uint32_t ipv6_da:1; - a_uint32_t ipv6_ptp_prim_addr:1; - a_uint32_t ipv6_ptp_pdelay_addr:1; - a_uint32_t udp_dport:1; - a_uint32_t udp_ptp_event_dport:1; - a_uint32_t y1731_mach:1; -}; - -union ptp_tx_com_ts_status_reg_u { - a_uint32_t val; - struct ptp_tx_com_ts_status_reg bf; -}; - -/*[register] PTP_TX_COM_TIMESTAMP0_REG*/ -#define PTP_TX_COM_TIMESTAMP0_REG -#define PTP_TX_COM_TIMESTAMP0_REG_ADDRESS 0x8632 -#define PTP_TX_COM_TIMESTAMP0_REG_NUM 1 -#define PTP_TX_COM_TIMESTAMP0_REG_INC 0x1 -#define PTP_TX_COM_TIMESTAMP0_REG_TYPE REG_TYPE_RW -#define PTP_TX_COM_TIMESTAMP0_REG_DEFAULT 0x0 - /*[field] COM_TS*/ - #define PTP_TX_COM_TIMESTAMP0_REG_COM_TS - #define PTP_TX_COM_TIMESTAMP0_REG_COM_TS_OFFSET 0 - #define PTP_TX_COM_TIMESTAMP0_REG_COM_TS_LEN 16 - #define PTP_TX_COM_TIMESTAMP0_REG_COM_TS_DEFAULT 0x0 - -struct ptp_tx_com_timestamp0_reg { - a_uint32_t com_ts:16; -}; - -union ptp_tx_com_timestamp0_reg_u { - a_uint32_t val; - struct ptp_tx_com_timestamp0_reg bf; -}; - -/*[register] PTP_TX_COM_TIMESTAMP1_REG*/ -#define PTP_TX_COM_TIMESTAMP1_REG -#define PTP_TX_COM_TIMESTAMP1_REG_ADDRESS 0x8633 -#define PTP_TX_COM_TIMESTAMP1_REG_NUM 1 -#define PTP_TX_COM_TIMESTAMP1_REG_INC 0x1 -#define PTP_TX_COM_TIMESTAMP1_REG_TYPE REG_TYPE_RW -#define PTP_TX_COM_TIMESTAMP1_REG_DEFAULT 0x0 - /*[field] COM_TS*/ - #define PTP_TX_COM_TIMESTAMP1_REG_COM_TS - #define PTP_TX_COM_TIMESTAMP1_REG_COM_TS_OFFSET 0 - #define PTP_TX_COM_TIMESTAMP1_REG_COM_TS_LEN 16 - #define PTP_TX_COM_TIMESTAMP1_REG_COM_TS_DEFAULT 0x0 - -struct ptp_tx_com_timestamp1_reg { - a_uint32_t com_ts:16; -}; - -union ptp_tx_com_timestamp1_reg_u { - a_uint32_t val; - struct ptp_tx_com_timestamp1_reg bf; -}; - -/*[register] PTP_TX_COM_TIMESTAMP2_REG*/ -#define PTP_TX_COM_TIMESTAMP2_REG -#define PTP_TX_COM_TIMESTAMP2_REG_ADDRESS 0x8634 -#define PTP_TX_COM_TIMESTAMP2_REG_NUM 1 -#define PTP_TX_COM_TIMESTAMP2_REG_INC 0x1 -#define PTP_TX_COM_TIMESTAMP2_REG_TYPE REG_TYPE_RW -#define PTP_TX_COM_TIMESTAMP2_REG_DEFAULT 0x0 - /*[field] COM_TS*/ - #define PTP_TX_COM_TIMESTAMP2_REG_COM_TS - #define PTP_TX_COM_TIMESTAMP2_REG_COM_TS_OFFSET 0 - #define PTP_TX_COM_TIMESTAMP2_REG_COM_TS_LEN 16 - #define PTP_TX_COM_TIMESTAMP2_REG_COM_TS_DEFAULT 0x0 - -struct ptp_tx_com_timestamp2_reg { - a_uint32_t com_ts:16; -}; - -union ptp_tx_com_timestamp2_reg_u { - a_uint32_t val; - struct ptp_tx_com_timestamp2_reg bf; -}; - -/*[register] PTP_TX_COM_TIMESTAMP3_REG*/ -#define PTP_TX_COM_TIMESTAMP3_REG -#define PTP_TX_COM_TIMESTAMP3_REG_ADDRESS 0x8635 -#define PTP_TX_COM_TIMESTAMP3_REG_NUM 1 -#define PTP_TX_COM_TIMESTAMP3_REG_INC 0x1 -#define PTP_TX_COM_TIMESTAMP3_REG_TYPE REG_TYPE_RW -#define PTP_TX_COM_TIMESTAMP3_REG_DEFAULT 0x0 - /*[field] COM_TS*/ - #define PTP_TX_COM_TIMESTAMP3_REG_COM_TS - #define PTP_TX_COM_TIMESTAMP3_REG_COM_TS_OFFSET 0 - #define PTP_TX_COM_TIMESTAMP3_REG_COM_TS_LEN 16 - #define PTP_TX_COM_TIMESTAMP3_REG_COM_TS_DEFAULT 0x0 - -struct ptp_tx_com_timestamp3_reg { - a_uint32_t com_ts:16; -}; - -union ptp_tx_com_timestamp3_reg_u { - a_uint32_t val; - struct ptp_tx_com_timestamp3_reg bf; -}; - -/*[register] PTP_TX_COM_TIMESTAMP4_REG*/ -#define PTP_TX_COM_TIMESTAMP4_REG -#define PTP_TX_COM_TIMESTAMP4_REG_ADDRESS 0x8636 -#define PTP_TX_COM_TIMESTAMP4_REG_NUM 1 -#define PTP_TX_COM_TIMESTAMP4_REG_INC 0x1 -#define PTP_TX_COM_TIMESTAMP4_REG_TYPE REG_TYPE_RW -#define PTP_TX_COM_TIMESTAMP4_REG_DEFAULT 0x0 - /*[field] COM_TS*/ - #define PTP_TX_COM_TIMESTAMP4_REG_COM_TS - #define PTP_TX_COM_TIMESTAMP4_REG_COM_TS_OFFSET 0 - #define PTP_TX_COM_TIMESTAMP4_REG_COM_TS_LEN 16 - #define PTP_TX_COM_TIMESTAMP4_REG_COM_TS_DEFAULT 0x0 - -struct ptp_tx_com_timestamp4_reg { - a_uint32_t com_ts:16; -}; - -union ptp_tx_com_timestamp4_reg_u { - a_uint32_t val; - struct ptp_tx_com_timestamp4_reg bf; -}; - -/*[register] PTP_TX_COM_FRAC_NANO_REG*/ -#define PTP_TX_COM_FRAC_NANO_REG -#define PTP_TX_COM_FRAC_NANO_REG_ADDRESS 0x8637 -#define PTP_TX_COM_FRAC_NANO_REG_NUM 1 -#define PTP_TX_COM_FRAC_NANO_REG_INC 0x1 -#define PTP_TX_COM_FRAC_NANO_REG_TYPE REG_TYPE_RW -#define PTP_TX_COM_FRAC_NANO_REG_DEFAULT 0x0 - /*[field] FRAC_NANO*/ - #define PTP_TX_COM_FRAC_NANO_REG_FRAC_NANO - #define PTP_TX_COM_FRAC_NANO_REG_FRAC_NANO_OFFSET 0 - #define PTP_TX_COM_FRAC_NANO_REG_FRAC_NANO_LEN 16 - #define PTP_TX_COM_FRAC_NANO_REG_FRAC_NANO_DEFAULT 0x0 - -struct ptp_tx_com_frac_nano_reg { - a_uint32_t frac_nano:16; -}; - -union ptp_tx_com_frac_nano_reg_u { - a_uint32_t val; - struct ptp_tx_com_frac_nano_reg bf; -}; - -/*[register] PTP_TX_Y1731_IDENTIFY_REG*/ -#define PTP_TX_Y1731_IDENTIFY_REG -#define PTP_TX_Y1731_IDENTIFY_REG_ADDRESS 0x863e -#define PTP_TX_Y1731_IDENTIFY_REG_NUM 1 -#define PTP_TX_Y1731_IDENTIFY_REG_INC 0x1 -#define PTP_TX_Y1731_IDENTIFY_REG_TYPE REG_TYPE_RW -#define PTP_TX_Y1731_IDENTIFY_REG_DEFAULT 0x0 - /*[field] IDENTIFY*/ - #define PTP_TX_Y1731_IDENTIFY_REG_IDENTIFY - #define PTP_TX_Y1731_IDENTIFY_REG_IDENTIFY_OFFSET 0 - #define PTP_TX_Y1731_IDENTIFY_REG_IDENTIFY_LEN 16 - #define PTP_TX_Y1731_IDENTIFY_REG_IDENTIFY_DEFAULT 0x0 - -struct ptp_tx_y1731_identify_reg { - a_uint32_t identify:16; -}; - -union ptp_tx_y1731_identify_reg_u { - a_uint32_t val; - struct ptp_tx_y1731_identify_reg bf; -}; - -/*[register] PTP_Y1731_DM_CONTROL_REG*/ -#define PTP_Y1731_DM_CONTROL_REG -#define PTP_Y1731_DM_CONTROL_REG_ADDRESS 0x8640 -#define PTP_Y1731_DM_CONTROL_REG_NUM 1 -#define PTP_Y1731_DM_CONTROL_REG_INC 0x1 -#define PTP_Y1731_DM_CONTROL_REG_TYPE REG_TYPE_RW -#define PTP_Y1731_DM_CONTROL_REG_DEFAULT 0x0 - /*[field] VALID_MSG_LEV_BMP*/ - #define PTP_Y1731_DM_CONTROL_REG_VALID_MSG_LEV_BMP - #define PTP_Y1731_DM_CONTROL_REG_VALID_MSG_LEV_BMP_OFFSET 0 - #define PTP_Y1731_DM_CONTROL_REG_VALID_MSG_LEV_BMP_LEN 8 - #define PTP_Y1731_DM_CONTROL_REG_VALID_MSG_LEV_BMP_DEFAULT 0x0 - /*[field] Y1731_DMM_LPBK_EN*/ - #define PTP_Y1731_DM_CONTROL_REG_Y1731_DMM_LPBK_EN - #define PTP_Y1731_DM_CONTROL_REG_Y1731_DMM_LPBK_EN_OFFSET 8 - #define PTP_Y1731_DM_CONTROL_REG_Y1731_DMM_LPBK_EN_LEN 1 - #define PTP_Y1731_DM_CONTROL_REG_Y1731_DMM_LPBK_EN_DEFAULT 0x0 - -struct ptp_y1731_dm_control_reg { - a_uint32_t valid_msg_lev_bmp:8; - a_uint32_t y1731_dmm_lpbk_en:1; -}; - -union ptp_y1731_dm_control_reg_u { - a_uint32_t val; - struct ptp_y1731_dm_control_reg bf; -}; - -/*[register] PTP_RX_COM_TS_STATUS_PRE_REG*/ -#define PTP_RX_COM_TS_STATUS_PRE_REG -#define PTP_RX_COM_TS_STATUS_PRE_REG_ADDRESS 0x8641 -#define PTP_RX_COM_TS_STATUS_PRE_REG_NUM 1 -#define PTP_RX_COM_TS_STATUS_PRE_REG_INC 0x1 -#define PTP_RX_COM_TS_STATUS_PRE_REG_TYPE REG_TYPE_RW -#define PTP_RX_COM_TS_STATUS_PRE_REG_DEFAULT 0x0 - /*[field] TS_STATUS*/ - #define PTP_RX_COM_TS_STATUS_PRE_REG_TS_STATUS - #define PTP_RX_COM_TS_STATUS_PRE_REG_TS_STATUS_OFFSET 0 - #define PTP_RX_COM_TS_STATUS_PRE_REG_TS_STATUS_LEN 15 - #define PTP_RX_COM_TS_STATUS_PRE_REG_TS_STATUS_DEFAULT 0x0 - -struct ptp_rx_com_ts_status_pre_reg { - a_uint32_t mac_lengthtype:1; - a_uint32_t mac_da:1; - a_uint32_t mac_ptp_prim_addr:1; - a_uint32_t mac_ptp_pdelay_addr:1; - a_uint32_t ipv4_layer4_protocol:1; - a_uint32_t ipv4_da:1; - a_uint32_t ipv4_ptp_prim_addr:1; - a_uint32_t ipv4_ptp_pdelay_addr:1; - a_uint32_t ipv6_next_header:1; - a_uint32_t ipv6_da:1; - a_uint32_t ipv6_ptp_prim_addr:1; - a_uint32_t ipv6_ptp_pdelay_addr:1; - a_uint32_t udp_dport:1; - a_uint32_t udp_ptp_event_dport:1; - a_uint32_t y1731_mach:1; -}; - -union ptp_rx_com_ts_status_pre_reg_u { - a_uint32_t val; - struct ptp_rx_com_ts_status_pre_reg bf; -}; - -/*[register] PTP_BAUD_CONFIG_REG*/ -#define PTP_BAUD_CONFIG_REG -#define PTP_BAUD_CONFIG_REG_ADDRESS 0x8700 -#define PTP_BAUD_CONFIG_REG_NUM 1 -#define PTP_BAUD_CONFIG_REG_INC 0x1 -#define PTP_BAUD_CONFIG_REG_TYPE REG_TYPE_RW -#define PTP_BAUD_CONFIG_REG_DEFAULT 0x0 - /*[field] BAUD_RATE*/ - #define PTP_BAUD_CONFIG_REG_BAUD_RATE - #define PTP_BAUD_CONFIG_REG_BAUD_RATE_OFFSET 0 - #define PTP_BAUD_CONFIG_REG_BAUD_RATE_LEN 16 - #define PTP_BAUD_CONFIG_REG_BAUD_RATE_DEFAULT 0x0 - -struct ptp_baud_config_reg { - a_uint32_t baud_rate:16; -}; - -union ptp_baud_config_reg_u { - a_uint32_t val; - struct ptp_baud_config_reg bf; -}; - -/*[register] PTP_UART_CONFIGURATION_REG*/ -#define PTP_UART_CONFIGURATION_REG -#define PTP_UART_CONFIGURATION_REG_ADDRESS 0x8701 -#define PTP_UART_CONFIGURATION_REG_NUM 1 -#define PTP_UART_CONFIGURATION_REG_INC 0x1 -#define PTP_UART_CONFIGURATION_REG_TYPE REG_TYPE_RW -#define PTP_UART_CONFIGURATION_REG_DEFAULT 0x0 - /*[field] START_POLARITY*/ - #define PTP_UART_CONFIGURATION_REG_START_POLARITY - #define PTP_UART_CONFIGURATION_REG_START_POLARITY_OFFSET 0 - #define PTP_UART_CONFIGURATION_REG_START_POLARITY_LEN 1 - #define PTP_UART_CONFIGURATION_REG_START_POLARITY_DEFAULT 0x0 - /*[field] MSB_FIRST*/ - #define PTP_UART_CONFIGURATION_REG_MSB_FIRST - #define PTP_UART_CONFIGURATION_REG_MSB_FIRST_OFFSET 1 - #define PTP_UART_CONFIGURATION_REG_MSB_FIRST_LEN 1 - #define PTP_UART_CONFIGURATION_REG_MSB_FIRST_DEFAULT 0x0 - /*[field] PARITY_EN*/ - #define PTP_UART_CONFIGURATION_REG_PARITY_EN - #define PTP_UART_CONFIGURATION_REG_PARITY_EN_OFFSET 2 - #define PTP_UART_CONFIGURATION_REG_PARITY_EN_LEN 1 - #define PTP_UART_CONFIGURATION_REG_PARITY_EN_DEFAULT 0x0 - /*[field] AUTO_TOD_OUT_EN*/ - #define PTP_UART_CONFIGURATION_REG_AUTO_TOD_OUT_EN - #define PTP_UART_CONFIGURATION_REG_AUTO_TOD_OUT_EN_OFFSET 3 - #define PTP_UART_CONFIGURATION_REG_AUTO_TOD_OUT_EN_LEN 1 - #define PTP_UART_CONFIGURATION_REG_AUTO_TOD_OUT_EN_DEFAULT 0x0 - /*[field] AUTO_TOD_IN_EN*/ - #define PTP_UART_CONFIGURATION_REG_AUTO_TOD_IN_EN - #define PTP_UART_CONFIGURATION_REG_AUTO_TOD_IN_EN_OFFSET 4 - #define PTP_UART_CONFIGURATION_REG_AUTO_TOD_IN_EN_LEN 1 - #define PTP_UART_CONFIGURATION_REG_AUTO_TOD_IN_EN_DEFAULT 0x0 - -struct ptp_uart_configuration_reg { - a_uint32_t start_polarity:1; - a_uint32_t msb_first:1; - a_uint32_t parity_en:1; - a_uint32_t auto_tod_out_en:1; - a_uint32_t auto_tod_in_en:1; -}; - -union ptp_uart_configuration_reg_u { - a_uint32_t val; - struct ptp_uart_configuration_reg bf; -}; - -/*[register] PTP_RESET_BUFFER_REG*/ -#define PTP_RESET_BUFFER_REG -#define PTP_RESET_BUFFER_REG_ADDRESS 0x8702 -#define PTP_RESET_BUFFER_REG_NUM 1 -#define PTP_RESET_BUFFER_REG_INC 0x1 -#define PTP_RESET_BUFFER_REG_TYPE REG_TYPE_RW -#define PTP_RESET_BUFFER_REG_DEFAULT 0x0 - /*[field] RESET*/ - #define PTP_RESET_BUFFER_REG_RESET - #define PTP_RESET_BUFFER_REG_RESET_OFFSET 0 - #define PTP_RESET_BUFFER_REG_RESET_LEN 1 - #define PTP_RESET_BUFFER_REG_RESET_DEFAULT 0x0 - -struct ptp_reset_buffer_reg { - a_uint32_t reset:1; -}; - -union ptp_reset_buffer_reg_u { - a_uint32_t val; - struct ptp_reset_buffer_reg bf; -}; - -/*[register] PTP_BUFFER_STATUS_REG*/ -#define PTP_BUFFER_STATUS_REG -#define PTP_BUFFER_STATUS_REG_ADDRESS 0x8703 -#define PTP_BUFFER_STATUS_REG_NUM 1 -#define PTP_BUFFER_STATUS_REG_INC 0x1 -#define PTP_BUFFER_STATUS_REG_TYPE REG_TYPE_RW -#define PTP_BUFFER_STATUS_REG_DEFAULT 0x0 - /*[field] TX_BUFFER_ALMOST_EMPTY*/ - #define PTP_BUFFER_STATUS_REG_TX_BUFFER_ALMOST_EMPTY - #define PTP_BUFFER_STATUS_REG_TX_BUFFER_ALMOST_EMPTY_OFFSET 0 - #define PTP_BUFFER_STATUS_REG_TX_BUFFER_ALMOST_EMPTY_LEN 1 - #define PTP_BUFFER_STATUS_REG_TX_BUFFER_ALMOST_EMPTY_DEFAULT 0x0 - /*[field] TX_BUFFER_ALMOST_FULL*/ - #define PTP_BUFFER_STATUS_REG_TX_BUFFER_ALMOST_FULL - #define PTP_BUFFER_STATUS_REG_TX_BUFFER_ALMOST_FULL_OFFSET 1 - #define PTP_BUFFER_STATUS_REG_TX_BUFFER_ALMOST_FULL_LEN 1 - #define PTP_BUFFER_STATUS_REG_TX_BUFFER_ALMOST_FULL_DEFAULT 0x0 - /*[field] TX_BUFFER_HALF_FULL*/ - #define PTP_BUFFER_STATUS_REG_TX_BUFFER_HALF_FULL - #define PTP_BUFFER_STATUS_REG_TX_BUFFER_HALF_FULL_OFFSET 2 - #define PTP_BUFFER_STATUS_REG_TX_BUFFER_HALF_FULL_LEN 1 - #define PTP_BUFFER_STATUS_REG_TX_BUFFER_HALF_FULL_DEFAULT 0x0 - /*[field] TX_BUFFER_FULL*/ - #define PTP_BUFFER_STATUS_REG_TX_BUFFER_FULL - #define PTP_BUFFER_STATUS_REG_TX_BUFFER_FULL_OFFSET 3 - #define PTP_BUFFER_STATUS_REG_TX_BUFFER_FULL_LEN 1 - #define PTP_BUFFER_STATUS_REG_TX_BUFFER_FULL_DEFAULT 0x0 - /*[field] RX_BUFFER_ALMOST_EMPTY*/ - #define PTP_BUFFER_STATUS_REG_RX_BUFFER_ALMOST_EMPTY - #define PTP_BUFFER_STATUS_REG_RX_BUFFER_ALMOST_EMPTY_OFFSET 4 - #define PTP_BUFFER_STATUS_REG_RX_BUFFER_ALMOST_EMPTY_LEN 1 - #define PTP_BUFFER_STATUS_REG_RX_BUFFER_ALMOST_EMPTY_DEFAULT 0x0 - /*[field] RX_BUFFER_ALMOST_FULL*/ - #define PTP_BUFFER_STATUS_REG_RX_BUFFER_ALMOST_FULL - #define PTP_BUFFER_STATUS_REG_RX_BUFFER_ALMOST_FULL_OFFSET 5 - #define PTP_BUFFER_STATUS_REG_RX_BUFFER_ALMOST_FULL_LEN 1 - #define PTP_BUFFER_STATUS_REG_RX_BUFFER_ALMOST_FULL_DEFAULT 0x0 - /*[field] RX_BUFFER_HALF_FULL*/ - #define PTP_BUFFER_STATUS_REG_RX_BUFFER_HALF_FULL - #define PTP_BUFFER_STATUS_REG_RX_BUFFER_HALF_FULL_OFFSET 6 - #define PTP_BUFFER_STATUS_REG_RX_BUFFER_HALF_FULL_LEN 1 - #define PTP_BUFFER_STATUS_REG_RX_BUFFER_HALF_FULL_DEFAULT 0x0 - /*[field] RX_BUFFER_FULL*/ - #define PTP_BUFFER_STATUS_REG_RX_BUFFER_FULL - #define PTP_BUFFER_STATUS_REG_RX_BUFFER_FULL_OFFSET 7 - #define PTP_BUFFER_STATUS_REG_RX_BUFFER_FULL_LEN 1 - #define PTP_BUFFER_STATUS_REG_RX_BUFFER_FULL_DEFAULT 0x0 - /*[field] RX_BUFFER_DATA_PRESENT*/ - #define PTP_BUFFER_STATUS_REG_RX_BUFFER_DATA_PRESENT - #define PTP_BUFFER_STATUS_REG_RX_BUFFER_DATA_PRESENT_OFFSET 8 - #define PTP_BUFFER_STATUS_REG_RX_BUFFER_DATA_PRESENT_LEN 1 - #define PTP_BUFFER_STATUS_REG_RX_BUFFER_DATA_PRESENT_DEFAULT 0x0 - -struct ptp_buffer_status_reg { - a_uint32_t tx_buffer_almost_empty:1; - a_uint32_t tx_buffer_almost_full:1; - a_uint32_t tx_buffer_half_full:1; - a_uint32_t tx_buffer_full:1; - a_uint32_t rx_buffer_almost_empty:1; - a_uint32_t rx_buffer_almost_full:1; - a_uint32_t rx_buffer_half_full:1; - a_uint32_t rx_buffer_full:1; - a_uint32_t rx_buffer_data_present:1; -}; - -union ptp_buffer_status_reg_u { - a_uint32_t val; - struct ptp_buffer_status_reg bf; -}; - -/*[register] PTP_TX_BUFFER_WRITE_REG*/ -#define PTP_TX_BUFFER_WRITE_REG -#define PTP_TX_BUFFER_WRITE_REG_ADDRESS 0x8704 -#define PTP_TX_BUFFER_WRITE_REG_NUM 1 -#define PTP_TX_BUFFER_WRITE_REG_INC 0x1 -#define PTP_TX_BUFFER_WRITE_REG_TYPE REG_TYPE_RW -#define PTP_TX_BUFFER_WRITE_REG_DEFAULT 0x0 - /*[field] TX_BUFFER*/ - #define PTP_TX_BUFFER_WRITE_REG_TX_BUFFER - #define PTP_TX_BUFFER_WRITE_REG_TX_BUFFER_OFFSET 0 - #define PTP_TX_BUFFER_WRITE_REG_TX_BUFFER_LEN 8 - #define PTP_TX_BUFFER_WRITE_REG_TX_BUFFER_DEFAULT 0x0 - -struct ptp_tx_buffer_write_reg { - a_uint32_t tx_buffer:8; -}; - -union ptp_tx_buffer_write_reg_u { - a_uint32_t val; - struct ptp_tx_buffer_write_reg bf; -}; - -/*[register] PTP_RX_BUFFER_READ_REG*/ -#define PTP_RX_BUFFER_READ_REG -#define PTP_RX_BUFFER_READ_REG_ADDRESS 0x8705 -#define PTP_RX_BUFFER_READ_REG_NUM 1 -#define PTP_RX_BUFFER_READ_REG_INC 0x1 -#define PTP_RX_BUFFER_READ_REG_TYPE REG_TYPE_RW -#define PTP_RX_BUFFER_READ_REG_DEFAULT 0x0 - /*[field] RX_DATA*/ - #define PTP_RX_BUFFER_READ_REG_RX_DATA - #define PTP_RX_BUFFER_READ_REG_RX_DATA_OFFSET 0 - #define PTP_RX_BUFFER_READ_REG_RX_DATA_LEN 8 - #define PTP_RX_BUFFER_READ_REG_RX_DATA_DEFAULT 0x0 - /*[field] RX_BUFFER_ALMOST_EMPTY*/ - #define PTP_RX_BUFFER_READ_REG_RX_BUFFER_ALMOST_EMPTY - #define PTP_RX_BUFFER_READ_REG_RX_BUFFER_ALMOST_EMPTY_OFFSET 8 - #define PTP_RX_BUFFER_READ_REG_RX_BUFFER_ALMOST_EMPTY_LEN 1 - #define PTP_RX_BUFFER_READ_REG_RX_BUFFER_ALMOST_EMPTY_DEFAULT 0x0 - /*[field] RX_BUFFER_ALMOST_FULL*/ - #define PTP_RX_BUFFER_READ_REG_RX_BUFFER_ALMOST_FULL - #define PTP_RX_BUFFER_READ_REG_RX_BUFFER_ALMOST_FULL_OFFSET 9 - #define PTP_RX_BUFFER_READ_REG_RX_BUFFER_ALMOST_FULL_LEN 1 - #define PTP_RX_BUFFER_READ_REG_RX_BUFFER_ALMOST_FULL_DEFAULT 0x0 - /*[field] RX_BUFFER_HALF_FULL*/ - #define PTP_RX_BUFFER_READ_REG_RX_BUFFER_HALF_FULL - #define PTP_RX_BUFFER_READ_REG_RX_BUFFER_HALF_FULL_OFFSET 10 - #define PTP_RX_BUFFER_READ_REG_RX_BUFFER_HALF_FULL_LEN 1 - #define PTP_RX_BUFFER_READ_REG_RX_BUFFER_HALF_FULL_DEFAULT 0x0 - /*[field] RX_BUFFER_FULL*/ - #define PTP_RX_BUFFER_READ_REG_RX_BUFFER_FULL - #define PTP_RX_BUFFER_READ_REG_RX_BUFFER_FULL_OFFSET 11 - #define PTP_RX_BUFFER_READ_REG_RX_BUFFER_FULL_LEN 1 - #define PTP_RX_BUFFER_READ_REG_RX_BUFFER_FULL_DEFAULT 0x0 - /*[field] RX_BUFFER_DATA_PRESENT*/ - #define PTP_RX_BUFFER_READ_REG_RX_BUFFER_DATA_PRESENT - #define PTP_RX_BUFFER_READ_REG_RX_BUFFER_DATA_PRESENT_OFFSET 12 - #define PTP_RX_BUFFER_READ_REG_RX_BUFFER_DATA_PRESENT_LEN 1 - #define PTP_RX_BUFFER_READ_REG_RX_BUFFER_DATA_PRESENT_DEFAULT 0x0 - -struct ptp_rx_buffer_read_reg { - a_uint32_t rx_data:8; - a_uint32_t rx_buffer_almost_empty:1; - a_uint32_t rx_buffer_almost_full:1; - a_uint32_t rx_buffer_half_full:1; - a_uint32_t rx_buffer_full:1; - a_uint32_t rx_buffer_data_present:1; -}; - -union ptp_rx_buffer_read_reg_u { - a_uint32_t val; - struct ptp_rx_buffer_read_reg bf; -}; - -/*[register] PTP_LOC_MAC_ADDR_0_REG*/ -#define PTP_LOC_MAC_ADDR_0_REG -#define PTP_LOC_MAC_ADDR_0_REG_ADDRESS 0x804a -#define PTP_LOC_MAC_ADDR_0_REG_NUM 1 -#define PTP_LOC_MAC_ADDR_0_REG_INC 0x1 -#define PTP_LOC_MAC_ADDR_0_REG_TYPE REG_TYPE_RW -#define PTP_LOC_MAC_ADDR_0_REG_DEFAULT 0x0 - /*[field] MAC_ADDR*/ - #define PTP_LOC_MAC_ADDR_0_REG_MAC_ADDR - #define PTP_LOC_MAC_ADDR_0_REG_MAC_ADDR_OFFSET 0 - #define PTP_LOC_MAC_ADDR_0_REG_MAC_ADDR_LEN 16 - #define PTP_LOC_MAC_ADDR_0_REG_MAC_ADDR_DEFAULT 0x0 - -struct ptp_loc_mac_addr_0_reg { - a_uint32_t mac_addr:16; -}; - -union ptp_loc_mac_addr_0_reg_u { - a_uint32_t val; - struct ptp_loc_mac_addr_0_reg bf; -}; - -/*[register] PTP_LOC_MAC_ADDR_1_REG*/ -#define PTP_LOC_MAC_ADDR_1_REG -#define PTP_LOC_MAC_ADDR_1_REG_ADDRESS 0x804b -#define PTP_LOC_MAC_ADDR_1_REG_NUM 1 -#define PTP_LOC_MAC_ADDR_1_REG_INC 0x1 -#define PTP_LOC_MAC_ADDR_1_REG_TYPE REG_TYPE_RW -#define PTP_LOC_MAC_ADDR_1_REG_DEFAULT 0x0 - /*[field] MAC_ADDR*/ - #define PTP_LOC_MAC_ADDR_1_REG_MAC_ADDR - #define PTP_LOC_MAC_ADDR_1_REG_MAC_ADDR_OFFSET 0 - #define PTP_LOC_MAC_ADDR_1_REG_MAC_ADDR_LEN 16 - #define PTP_LOC_MAC_ADDR_1_REG_MAC_ADDR_DEFAULT 0x0 - -struct ptp_loc_mac_addr_1_reg { - a_uint32_t mac_addr:16; -}; - -union ptp_loc_mac_addr_1_reg_u { - a_uint32_t val; - struct ptp_loc_mac_addr_1_reg bf; -}; - -/*[register] PTP_LOC_MAC_ADDR_2_REG*/ -#define PTP_LOC_MAC_ADDR_2_REG -#define PTP_LOC_MAC_ADDR_2_REG_ADDRESS 0x804c -#define PTP_LOC_MAC_ADDR_2_REG_NUM 1 -#define PTP_LOC_MAC_ADDR_2_REG_INC 0x1 -#define PTP_LOC_MAC_ADDR_2_REG_TYPE REG_TYPE_RW -#define PTP_LOC_MAC_ADDR_2_REG_DEFAULT 0x0 - /*[field] MAC_ADDR*/ - #define PTP_LOC_MAC_ADDR_2_REG_MAC_ADDR - #define PTP_LOC_MAC_ADDR_2_REG_MAC_ADDR_OFFSET 0 - #define PTP_LOC_MAC_ADDR_2_REG_MAC_ADDR_LEN 16 - #define PTP_LOC_MAC_ADDR_2_REG_MAC_ADDR_DEFAULT 0x0 - -struct ptp_loc_mac_addr_2_reg { - a_uint32_t mac_addr:16; -}; - -union ptp_loc_mac_addr_2_reg_u { - a_uint32_t val; - struct ptp_loc_mac_addr_2_reg bf; -}; - -/*[register] PTP_LINK_DELAY_0_REG*/ -#define PTP_LINK_DELAY_0_REG -#define PTP_LINK_DELAY_0_REG_ADDRESS 0x80f3 -#define PTP_LINK_DELAY_0_REG_NUM 1 -#define PTP_LINK_DELAY_0_REG_INC 0x1 -#define PTP_LINK_DELAY_0_REG_TYPE REG_TYPE_RW -#define PTP_LINK_DELAY_0_REG_DEFAULT 0x0 - /*[field] LINK_DELAY*/ - #define PTP_LINK_DELAY_0_REG_LINK_DELAY - #define PTP_LINK_DELAY_0_REG_LINK_DELAY_OFFSET 0 - #define PTP_LINK_DELAY_0_REG_LINK_DELAY_LEN 16 - #define PTP_LINK_DELAY_0_REG_LINK_DELAY_DEFAULT 0x0 - -struct ptp_link_delay_0_reg { - a_uint32_t link_delay:16; -}; - -union ptp_link_delay_0_reg_u { - a_uint32_t val; - struct ptp_link_delay_0_reg bf; -}; - -/*[register] PTP_LINK_DELAY_1_REG*/ -#define PTP_LINK_DELAY_1_REG -#define PTP_LINK_DELAY_1_REG_ADDRESS 0x80f4 -#define PTP_LINK_DELAY_1_REG_NUM 1 -#define PTP_LINK_DELAY_1_REG_INC 0x1 -#define PTP_LINK_DELAY_1_REG_TYPE REG_TYPE_RW -#define PTP_LINK_DELAY_1_REG_DEFAULT 0x0 - /*[field] LINK_DELAY*/ - #define PTP_LINK_DELAY_1_REG_LINK_DELAY - #define PTP_LINK_DELAY_1_REG_LINK_DELAY_OFFSET 0 - #define PTP_LINK_DELAY_1_REG_LINK_DELAY_LEN 16 - #define PTP_LINK_DELAY_1_REG_LINK_DELAY_DEFAULT 0x0 - -struct ptp_link_delay_1_reg { - a_uint32_t link_delay:16; -}; - -union ptp_link_delay_1_reg_u { - a_uint32_t val; - struct ptp_link_delay_1_reg bf; -}; - -/*[register] PTP_MISC_CONTROL_REG*/ -#define PTP_MISC_CONTROL_REG -#define PTP_MISC_CONTROL_REG_ADDRESS 0x80f5 -#define PTP_MISC_CONTROL_REG_NUM 1 -#define PTP_MISC_CONTROL_REG_INC 0x1 -#define PTP_MISC_CONTROL_REG_TYPE REG_TYPE_RW -#define PTP_MISC_CONTROL_REG_DEFAULT 0x0 - /*[field] EG_ASYM_EN*/ - #define PTP_MISC_CONTROL_REG_EG_ASYM_EN - #define PTP_MISC_CONTROL_REG_EG_ASYM_EN_OFFSET 0 - #define PTP_MISC_CONTROL_REG_EG_ASYM_EN_LEN 1 - #define PTP_MISC_CONTROL_REG_EG_ASYM_EN_DEFAULT 0x0 - /*[field] IN_ASYM_EN*/ - #define PTP_MISC_CONTROL_REG_IN_ASYM_EN - #define PTP_MISC_CONTROL_REG_IN_ASYM_EN_OFFSET 1 - #define PTP_MISC_CONTROL_REG_IN_ASYM_EN_LEN 1 - #define PTP_MISC_CONTROL_REG_IN_ASYM_EN_DEFAULT 0x0 - -struct ptp_misc_control_reg { - a_uint32_t eg_asym_en:1; - a_uint32_t in_asym_en:1; -}; - -union ptp_misc_control_reg_u { - a_uint32_t val; - struct ptp_misc_control_reg bf; -}; - -/*[register] PTP_INGRESS_ASYMMETRY_0_REG*/ -#define PTP_INGRESS_ASYMMETRY_0_REG -#define PTP_INGRESS_ASYMMETRY_0_REG_ADDRESS 0x80f6 -#define PTP_INGRESS_ASYMMETRY_0_REG_NUM 1 -#define PTP_INGRESS_ASYMMETRY_0_REG_INC 0x1 -#define PTP_INGRESS_ASYMMETRY_0_REG_TYPE REG_TYPE_RW -#define PTP_INGRESS_ASYMMETRY_0_REG_DEFAULT 0x0 - /*[field] IN_ASYM*/ - #define PTP_INGRESS_ASYMMETRY_0_REG_IN_ASYM - #define PTP_INGRESS_ASYMMETRY_0_REG_IN_ASYM_OFFSET 0 - #define PTP_INGRESS_ASYMMETRY_0_REG_IN_ASYM_LEN 16 - #define PTP_INGRESS_ASYMMETRY_0_REG_IN_ASYM_DEFAULT 0x0 - -struct ptp_ingress_asymmetry_0_reg { - a_uint32_t in_asym:16; -}; - -union ptp_ingress_asymmetry_0_reg_u { - a_uint32_t val; - struct ptp_ingress_asymmetry_0_reg bf; -}; - -/*[register] PTP_INGRESS_ASYMMETRY_1_REG*/ -#define PTP_INGRESS_ASYMMETRY_1_REG -#define PTP_INGRESS_ASYMMETRY_1_REG_ADDRESS 0x80f7 -#define PTP_INGRESS_ASYMMETRY_1_REG_NUM 1 -#define PTP_INGRESS_ASYMMETRY_1_REG_INC 0x1 -#define PTP_INGRESS_ASYMMETRY_1_REG_TYPE REG_TYPE_RW -#define PTP_INGRESS_ASYMMETRY_1_REG_DEFAULT 0x0 - /*[field] IN_ASYM*/ - #define PTP_INGRESS_ASYMMETRY_1_REG_IN_ASYM - #define PTP_INGRESS_ASYMMETRY_1_REG_IN_ASYM_OFFSET 0 - #define PTP_INGRESS_ASYMMETRY_1_REG_IN_ASYM_LEN 16 - #define PTP_INGRESS_ASYMMETRY_1_REG_IN_ASYM_DEFAULT 0x0 - -struct ptp_ingress_asymmetry_1_reg { - a_uint32_t in_asym:16; -}; - -union ptp_ingress_asymmetry_1_reg_u { - a_uint32_t val; - struct ptp_ingress_asymmetry_1_reg bf; -}; - -/*[register] PTP_EGRESS_ASYMMETRY_0_REG*/ -#define PTP_EGRESS_ASYMMETRY_0_REG -#define PTP_EGRESS_ASYMMETRY_0_REG_ADDRESS 0x80f8 -#define PTP_EGRESS_ASYMMETRY_0_REG_NUM 1 -#define PTP_EGRESS_ASYMMETRY_0_REG_INC 0x1 -#define PTP_EGRESS_ASYMMETRY_0_REG_TYPE REG_TYPE_RW -#define PTP_EGRESS_ASYMMETRY_0_REG_DEFAULT 0x0 - /*[field] EG_ASYM*/ - #define PTP_EGRESS_ASYMMETRY_0_REG_EG_ASYM - #define PTP_EGRESS_ASYMMETRY_0_REG_EG_ASYM_OFFSET 0 - #define PTP_EGRESS_ASYMMETRY_0_REG_EG_ASYM_LEN 16 - #define PTP_EGRESS_ASYMMETRY_0_REG_EG_ASYM_DEFAULT 0x0 - -struct ptp_egress_asymmetry_0_reg { - a_uint32_t eg_asym:16; -}; - -union ptp_egress_asymmetry_0_reg_u { - a_uint32_t val; - struct ptp_egress_asymmetry_0_reg bf; -}; - -/*[register] PTP_EGRESS_ASYMMETRY_1_REG*/ -#define PTP_EGRESS_ASYMMETRY_1_REG -#define PTP_EGRESS_ASYMMETRY_1_REG_ADDRESS 0x80f9 -#define PTP_EGRESS_ASYMMETRY_1_REG_NUM 1 -#define PTP_EGRESS_ASYMMETRY_1_REG_INC 0x1 -#define PTP_EGRESS_ASYMMETRY_1_REG_TYPE REG_TYPE_RW -#define PTP_EGRESS_ASYMMETRY_1_REG_DEFAULT 0x0 - /*[field] EG_ASYM*/ - #define PTP_EGRESS_ASYMMETRY_1_REG_EG_ASYM - #define PTP_EGRESS_ASYMMETRY_1_REG_EG_ASYM_OFFSET 0 - #define PTP_EGRESS_ASYMMETRY_1_REG_EG_ASYM_LEN 16 - #define PTP_EGRESS_ASYMMETRY_1_REG_EG_ASYM_DEFAULT 0x0 - -struct ptp_egress_asymmetry_1_reg { - a_uint32_t eg_asym:16; -}; - -union ptp_egress_asymmetry_1_reg_u { - a_uint32_t val; - struct ptp_egress_asymmetry_1_reg bf; -}; - -/*[register] PTP_BACKUP_REG*/ -#define PTP_BACKUP_REG -#define PTP_BACKUP_REG_ADDRESS 0x9036 -#define PTP_BACKUP_REG_NUM 1 -#define PTP_BACKUP_REG_INC 0x1 -#define PTP_BACKUP_REG_TYPE REG_TYPE_RW -#define PTP_BACKUP_REG_DEFAULT 0x0 - /*[field] P2P_TC_EN*/ - #define PTP_BACKUP_REG_P2P_TC_EN - #define PTP_BACKUP_REG_P2P_TC_EN_OFFSET 0 - #define PTP_BACKUP_REG_P2P_TC_EN_LEN 1 - #define PTP_BACKUP_REG_P2P_TC_EN_DEFAULT 0x0 - -struct ptp_backup_reg { - a_uint32_t p2p_tc_en:1; -}; - -union ptp_backup_reg_u { - a_uint32_t val; - struct ptp_backup_reg bf; -}; - -#endif diff --git a/feeds/ipq807x/qca-ssdk/src/include/hsl/phy/sfp_phy.h b/feeds/ipq807x/qca-ssdk/src/include/hsl/phy/sfp_phy.h deleted file mode 100755 index 8b4c7a127..000000000 --- a/feeds/ipq807x/qca-ssdk/src/include/hsl/phy/sfp_phy.h +++ /dev/null @@ -1,47 +0,0 @@ -/* - * Copyright (c) 2018, The Linux Foundation. All rights reserved. - * Permission to use, copy, modify, and/or distribute this software for - * any purpose with or without fee is hereby granted, provided that the - * above copyright notice and this permission notice appear in all copies. - * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES - * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR - * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES - * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN - * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT - * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. - */ - -#ifndef _SFP_PHY_H_ -#define _SFP_PHY_H_ - -#ifdef __cplusplus -extern "C" -{ -#endif /* __cplusplus */ - - -#define SFP_ANEG_DONE 0x20 - -#define SFP_E2PROM_ADDR 0x50 -#define SFP_SPEED_ADDR 0xc -#define SFP_SPEED_1000M 10 -#define SFP_SPEED_2500M 25 -#define SFP_SPEED_10000M 100 - -#define SFP_TO_SFP_SPEED(reg_data) ((reg_data >> 8) & 0xff) - -int sfp_phy_device_setup(a_uint32_t dev_id, a_uint32_t port_id, a_uint32_t phy_id); -void sfp_phy_device_remove(a_uint32_t dev_id, a_uint32_t port); - -int sfp_phy_init(a_uint32_t dev_id, a_uint32_t port_bmp); -void sfp_phy_exit(a_uint32_t dev_id, a_uint32_t port_bmp); - -sw_error_t sfp_phy_interface_get_mode_status(a_uint32_t dev_id, a_uint32_t phy_id, - fal_port_interface_mode_t *interface_mode); - -#ifdef __cplusplus -} -#endif /* __cplusplus */ -#endif /* _SFP_PHY_H_ */ - diff --git a/feeds/ipq807x/qca-ssdk/src/include/hsl/scomphy/scomphy_init.h b/feeds/ipq807x/qca-ssdk/src/include/hsl/scomphy/scomphy_init.h deleted file mode 100755 index decb90945..000000000 --- a/feeds/ipq807x/qca-ssdk/src/include/hsl/scomphy/scomphy_init.h +++ /dev/null @@ -1,42 +0,0 @@ -/* - * Copyright (c) 2017-2018, The Linux Foundation. All rights reserved. - * Permission to use, copy, modify, and/or distribute this software for - * any purpose with or without fee is hereby granted, provided that the - * above copyright notice and this permission notice appear in all copies. - * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES - * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR - * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES - * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN - * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT - * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. - */ - - -/** - * @defgroup scomphy_init SCOMPHY_INIT - * @{ - */ -#ifndef _SCOMPHY_INIT_H_ -#define _SCOMPHY_INIT_H_ - -#ifdef __cplusplus -extern "C" { -#endif /* __cplusplus */ - -#include "ssdk_init.h" - -sw_error_t -scomphy_init(a_uint32_t dev_id, ssdk_init_cfg *cfg); - -sw_error_t -scomphy_cleanup(a_uint32_t dev_id); - -#ifdef __cplusplus -} -#endif /* __cplusplus */ - -#endif /* _SCOMPHY_INIT_H_ */ -/** - * @} - */ diff --git a/feeds/ipq807x/qca-ssdk/src/include/hsl/scomphy/scomphy_port_ctrl.h b/feeds/ipq807x/qca-ssdk/src/include/hsl/scomphy/scomphy_port_ctrl.h deleted file mode 100644 index 399e25306..000000000 --- a/feeds/ipq807x/qca-ssdk/src/include/hsl/scomphy/scomphy_port_ctrl.h +++ /dev/null @@ -1,233 +0,0 @@ -/* - * Copyright (c) 2017-2018, The Linux Foundation. All rights reserved. - * Permission to use, copy, modify, and/or distribute this software for - * any purpose with or without fee is hereby granted, provided that the - * above copyright notice and this permission notice appear in all copies. - * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES - * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR - * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES - * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN - * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT - * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. - */ - -/*qca808x_start*/ -#ifndef _SCOMPHY_PORT_CTRL_H_ -#define _SCOMPHY_PORT_CTRL_H_ - -#ifdef __cplusplus -extern "C" -{ -#endif /* __cplusplus */ - -#include "fal/fal_port_ctrl.h" - -sw_error_t scomphy_port_ctrl_init (a_uint32_t dev_id); - -sw_error_t -scomphy_port_reset (a_uint32_t dev_id, fal_port_t port_id); - -/*qca808x_end*/ -#ifdef IN_PORTCONTROL -/*qca808x_start*/ -#define SCOMPHY_PORT_CTRL_INIT(rv, dev_id) \ - { \ - rv = scomphy_port_ctrl_init(dev_id); \ - SW_RTN_ON_ERROR(rv); \ - } -/*qca808x_end*/ -#else -#define SCOMPHY_PORT_CTRL_INIT(rv, dev_id) -#endif - -#ifdef HSL_STANDALONG - - -HSL_LOCAL sw_error_t -scomphy_port_duplex_set (a_uint32_t dev_id, fal_port_t port_id, - fal_port_duplex_t duplex); - - -HSL_LOCAL sw_error_t -scomphy_port_duplex_get (a_uint32_t dev_id, fal_port_t port_id, - fal_port_duplex_t * pduplex); - - -HSL_LOCAL sw_error_t -scomphy_port_speed_set (a_uint32_t dev_id, fal_port_t port_id, - fal_port_speed_t speed); - - -HSL_LOCAL sw_error_t -scomphy_port_speed_get (a_uint32_t dev_id, fal_port_t port_id, - fal_port_speed_t * pspeed); - - -HSL_LOCAL sw_error_t -scomphy_port_autoneg_status_get (a_uint32_t dev_id, fal_port_t port_id, - a_bool_t * status); - - -HSL_LOCAL sw_error_t -scomphy_port_autoneg_enable (a_uint32_t dev_id, fal_port_t port_id); - - -HSL_LOCAL sw_error_t -scomphy_port_autoneg_restart (a_uint32_t dev_id, fal_port_t port_id); - - -HSL_LOCAL sw_error_t -scomphy_port_autoneg_adv_set (a_uint32_t dev_id, fal_port_t port_id, - a_uint32_t autoadv); - - -HSL_LOCAL sw_error_t -scomphy_port_autoneg_adv_get (a_uint32_t dev_id, fal_port_t port_id, - a_uint32_t * autoadv); - -#ifndef IN_PORTCONTROL_MINI -HSL_LOCAL sw_error_t -scomphy_port_powersave_set (a_uint32_t dev_id, fal_port_t port_id, - a_bool_t enable); - - -HSL_LOCAL sw_error_t -scomphy_port_powersave_get (a_uint32_t dev_id, fal_port_t port_id, - a_bool_t * enable); - - -HSL_LOCAL sw_error_t -scomphy_port_hibernate_set (a_uint32_t dev_id, fal_port_t port_id, - a_bool_t enable); - - -HSL_LOCAL sw_error_t -scomphy_port_hibernate_get (a_uint32_t dev_id, fal_port_t port_id, - a_bool_t * enable); - - -HSL_LOCAL sw_error_t -scomphy_port_cdt (a_uint32_t dev_id, fal_port_t port_id, a_uint32_t mdi_pair, - fal_cable_status_t * cable_status, a_uint32_t * cable_len); -#endif - -HSL_LOCAL sw_error_t -scomphy_port_link_status_get (a_uint32_t dev_id, fal_port_t port_id, - a_bool_t * status); -#ifndef IN_PORTCONTROL_MINI - -HSL_LOCAL sw_error_t -scomphy_port_8023az_set (a_uint32_t dev_id, fal_port_t port_id, - a_bool_t enable); - -HSL_LOCAL sw_error_t -scomphy_port_8023az_get (a_uint32_t dev_id, fal_port_t port_id, - a_bool_t * enable); - -HSL_LOCAL sw_error_t -scomphy_port_mdix_set (a_uint32_t dev_id, a_uint32_t phy_id, - fal_port_mdix_mode_t mode); - -HSL_LOCAL sw_error_t -scomphy_port_mdix_get (a_uint32_t dev_id, fal_port_t port_id, - fal_port_mdix_mode_t * mode); - -HSL_LOCAL sw_error_t -scomphy_port_mdix_status_get (a_uint32_t dev_id, fal_port_t port_id, - fal_port_mdix_status_t * mode); - -HSL_LOCAL sw_error_t -scomphy_port_combo_prefer_medium_set (a_uint32_t dev_id, a_uint32_t phy_id, - fal_port_medium_t phy_medium); - -HSL_LOCAL sw_error_t -scomphy_port_combo_prefer_medium_get (a_uint32_t dev_id, a_uint32_t phy_id, - fal_port_medium_t * phy_medium); - -HSL_LOCAL sw_error_t -scomphy_port_combo_medium_status_get (a_uint32_t dev_id, a_uint32_t phy_id, - fal_port_medium_t * phy_medium); - -HSL_LOCAL sw_error_t -scomphy_port_combo_fiber_mode_set (a_uint32_t dev_id, a_uint32_t phy_id, - fal_port_fiber_mode_t fiber_mode); - -HSL_LOCAL sw_error_t -scomphy_port_combo_fiber_mode_get (a_uint32_t dev_id, a_uint32_t phy_id, - fal_port_fiber_mode_t * fiber_mode); - -HSL_LOCAL sw_error_t -scomphy_port_local_loopback_set (a_uint32_t dev_id, fal_port_t port_id, - a_bool_t enable); - -HSL_LOCAL sw_error_t -scomphy_port_local_loopback_get (a_uint32_t dev_id, fal_port_t port_id, - a_bool_t * enable); - -HSL_LOCAL sw_error_t -scomphy_port_remote_loopback_set (a_uint32_t dev_id, fal_port_t port_id, - a_bool_t enable); - -HSL_LOCAL sw_error_t -scomphy_port_remote_loopback_get (a_uint32_t dev_id, fal_port_t port_id, - a_bool_t * enable); - -HSL_LOCAL sw_error_t -scomphy_port_magic_frame_mac_set (a_uint32_t dev_id, fal_port_t port_id, - fal_mac_addr_t * mac); - -HSL_LOCAL sw_error_t -scomphy_port_magic_frame_mac_get (a_uint32_t dev_id, fal_port_t port_id, - fal_mac_addr_t * mac); - -HSL_LOCAL sw_error_t -scomphy_port_phy_id_get (a_uint32_t dev_id, fal_port_t port_id, - a_uint16_t * org_id, a_uint16_t * rev_id); - -HSL_LOCAL sw_error_t -scomphy_port_wol_status_set (a_uint32_t dev_id, fal_port_t port_id, - a_bool_t enable); - -HSL_LOCAL sw_error_t -scomphy_port_wol_status_get (a_uint32_t dev_id, fal_port_t port_id, - a_bool_t * enable); -#endif -HSL_LOCAL sw_error_t -scomphy_port_power_off (a_uint32_t dev_id, fal_port_t port_id); - -HSL_LOCAL sw_error_t -scomphy_port_power_on (a_uint32_t dev_id, fal_port_t port_id); - -#ifndef IN_PORTCONTROL_MINI -HSL_LOCAL sw_error_t -scomphy_port_interface_mode_set (a_uint32_t dev_id, fal_port_t port_id, - fal_port_interface_mode_t mode); - -HSL_LOCAL sw_error_t -scomphy_port_interface_mode_get (a_uint32_t dev_id, fal_port_t port_id, - fal_port_interface_mode_t * mode); - -HSL_LOCAL sw_error_t -scomphy_port_interface_mode_status_get (a_uint32_t dev_id, fal_port_t port_id, - fal_port_interface_mode_t * mode); - -HSL_LOCAL sw_error_t -scomphy_port_counter_set (a_uint32_t dev_id, fal_port_t port_id, - a_bool_t enable); - -HSL_LOCAL sw_error_t -scomphy_port_counter_get (a_uint32_t dev_id, fal_port_t port_id, - a_bool_t * enable); - -HSL_LOCAL sw_error_t -scomphy_port_counter_show (a_uint32_t dev_id, fal_port_t port_id, - fal_port_counter_info_t * counter_info); -#endif -#endif -/*qca808x_start*/ -#ifdef __cplusplus -} -#endif /* __cplusplus */ -#endif /* _SCOMPHY_PORT_CTRL_H_ */ -/*qca808x_end*/ diff --git a/feeds/ipq807x/qca-ssdk/src/include/hsl/scomphy/scomphy_reg_access.h b/feeds/ipq807x/qca-ssdk/src/include/hsl/scomphy/scomphy_reg_access.h deleted file mode 100755 index 995ff35af..000000000 --- a/feeds/ipq807x/qca-ssdk/src/include/hsl/scomphy/scomphy_reg_access.h +++ /dev/null @@ -1,62 +0,0 @@ -/* - * Copyright (c) 2017-2019, The Linux Foundation. All rights reserved. - * Permission to use, copy, modify, and/or distribute this software for - * any purpose with or without fee is hereby granted, provided that the - * above copyright notice and this permission notice appear in all copies. - * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES - * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR - * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES - * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN - * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT - * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. - */ - - -/*qca808x_start*/ - -#ifndef _SCOMPHY_REG_ACCESS_H_ -#define _SCOMPHY_REG_ACCESS_H_ - -#ifdef __cplusplus -extern "C" { -#endif /* __cplusplus */ - -#include "sw.h" - -sw_error_t -scomphy_phy_get(a_uint32_t dev_id, a_uint32_t phy_addr, - a_uint32_t reg, a_uint16_t * value); - -sw_error_t -scomphy_phy_set(a_uint32_t dev_id, a_uint32_t phy_addr, - a_uint32_t reg, a_uint16_t value); -/*qca808x_end*/ - -sw_error_t -scomphy_reg_get(a_uint32_t dev_id, a_uint32_t reg_addr, - a_uint8_t *val, a_uint32_t len); - -sw_error_t -scomphy_reg_set(a_uint32_t dev_id, a_uint32_t reg_addr, - a_uint8_t *val, a_uint32_t len); - -sw_error_t -scomphy_uniphy_reg_get(a_uint32_t dev_id, a_uint32_t index, - a_uint32_t reg_addr, a_uint8_t *val, a_uint32_t len); - -sw_error_t -scomphy_uniphy_reg_set(a_uint32_t dev_id, a_uint32_t index, - a_uint32_t reg_addr, a_uint8_t *val, a_uint32_t len); - -/*qca808x_start*/ -sw_error_t -scomphy_reg_access_init(a_uint32_t dev_id, ssdk_init_cfg *cfg); - - -#ifdef __cplusplus -} -#endif /* __cplusplus */ - -#endif /* _SCOMPHY_REG_ACCESS_H_ */ -/*qca808x_end*/ diff --git a/feeds/ipq807x/qca-ssdk/src/include/hsl/sfp/sfp.h b/feeds/ipq807x/qca-ssdk/src/include/hsl/sfp/sfp.h deleted file mode 100644 index 186332663..000000000 --- a/feeds/ipq807x/qca-ssdk/src/include/hsl/sfp/sfp.h +++ /dev/null @@ -1,956 +0,0 @@ -/* - * Copyright (c) 2019, The Linux Foundation. All rights reserved. - * Permission to use, copy, modify, and/or distribute this software for - * any purpose with or without fee is hereby granted, provided that the - * above copyright notice and this permission notice appear in all copies. - * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES - * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR - * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES - * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN - * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT - * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. - */ - - -/** - * @defgroup - * @{ - */ -#ifndef _SFP_H_ -#define _SFP_H_ - - -sw_error_t -sfp_eeprom_data_get(a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t i2c_slave, - a_uint32_t offset, a_uint8_t *buf, a_uint32_t counter); - -sw_error_t -sfp_eeprom_data_set(a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t i2c_slave, - a_uint32_t offset, a_uint8_t *buf, a_uint32_t counter); - -sw_error_t -sfp_dev_type_get( - a_uint32_t dev_id, - a_uint32_t index, - union sfp_dev_type_u *value); - -sw_error_t -sfp_dev_type_ext_get( - a_uint32_t dev_id, - a_uint32_t index, - union sfp_dev_type_ext_u *value); - -sw_error_t -sfp_dev_connector_type_get( - a_uint32_t dev_id, - a_uint32_t index, - union sfp_dev_connector_type_u *value); - -sw_error_t -sfp_transc_get( - a_uint32_t dev_id, - a_uint32_t index, - union sfp_transc_u *value); - -sw_error_t -sfp_encoding_get( - a_uint32_t dev_id, - a_uint32_t index, - union sfp_encoding_u *value); - -sw_error_t -sfp_br_get( - a_uint32_t dev_id, - a_uint32_t index, - union sfp_br_u *value); - -sw_error_t -sfp_rate_get( - a_uint32_t dev_id, - a_uint32_t index, - union sfp_rate_u *value); - -sw_error_t -sfp_link_len_get( - a_uint32_t dev_id, - a_uint32_t index, - union sfp_link_len_u *value); - -sw_error_t -sfp_vendor_get( - a_uint32_t dev_id, - a_uint32_t index, - union sfp_vendor_u *value); - -sw_error_t -sfp_laser_get( - a_uint32_t dev_id, - a_uint32_t index, - union sfp_laser_u *value); - -sw_error_t -sfp_base_get( - a_uint32_t dev_id, - a_uint32_t index, - union sfp_base_u *value); - -sw_error_t -sfp_option_get( - a_uint32_t dev_id, - a_uint32_t index, - union sfp_option_u *value); - -sw_error_t -sfp_rate_ctrl_get( - a_uint32_t dev_id, - a_uint32_t index, - union sfp_rate_ctrl_u *value); - -sw_error_t -sfp_vendor_ext_get( - a_uint32_t dev_id, - a_uint32_t index, - union sfp_vendor_ext_u *value); - -sw_error_t -sfp_enhanced_get( - a_uint32_t dev_id, - a_uint32_t index, - union sfp_enhanced_u *value); - -sw_error_t -sfp_ext_get( - a_uint32_t dev_id, - a_uint32_t index, - union sfp_ext_u *value); - -sw_error_t -sfp_dev_type_id_get( - a_uint32_t dev_id, - a_uint32_t index, - unsigned int *value); - -sw_error_t -sfp_dev_type_ext_id_get( - a_uint32_t dev_id, - a_uint32_t index, - unsigned int *value); - -sw_error_t -sfp_dev_connector_type_code_get( - a_uint32_t dev_id, - a_uint32_t index, - unsigned int *value); - -sw_error_t -sfp_transc_sonet_ccode_2_get( - a_uint32_t dev_id, - a_uint32_t index, - unsigned int *value); - -sw_error_t -sfp_transc_fiber_ch_tech_1_get( - a_uint32_t dev_id, - a_uint32_t index, - unsigned int *value); - -sw_error_t -sfp_transc_sonet_ccode_1_get( - a_uint32_t dev_id, - a_uint32_t index, - unsigned int *value); - -sw_error_t -sfp_transc_fiber_ch_speed_get( - a_uint32_t dev_id, - a_uint32_t index, - unsigned int *value); - -sw_error_t -sfp_transc_fiber_ch_tech_2_get( - a_uint32_t dev_id, - a_uint32_t index, - unsigned int *value); - -sw_error_t -sfp_transc_cable_tech_get( - a_uint32_t dev_id, - a_uint32_t index, - unsigned int *value); - -sw_error_t -sfp_transc_fiber_ch_link_len_get( - a_uint32_t dev_id, - a_uint32_t index, - unsigned int *value); - -sw_error_t -sfp_transc_unallocated_get( - a_uint32_t dev_id, - a_uint32_t index, - unsigned int *value); - -sw_error_t -sfp_transc_fiber_chan_tm_media_get( - a_uint32_t dev_id, - a_uint32_t index, - unsigned int *value); - -sw_error_t -sfp_transc_escon_ccode_get( - a_uint32_t dev_id, - a_uint32_t index, - unsigned int *value); - -sw_error_t -sfp_transc_infiniband_ccode_get( - a_uint32_t dev_id, - a_uint32_t index, - unsigned int *value); - -sw_error_t -sfp_transc_eth_ccode_get( - a_uint32_t dev_id, - a_uint32_t index, - unsigned int *value); - -sw_error_t -sfp_transc_eth_10g_ccode_get( - a_uint32_t dev_id, - a_uint32_t index, - unsigned int *value); - -sw_error_t -sfp_encoding_code_get( - a_uint32_t dev_id, - a_uint32_t index, - unsigned int *value); - -sw_error_t -sfp_br_bit_get( - a_uint32_t dev_id, - a_uint32_t index, - unsigned int *value); - -sw_error_t -sfp_rate_id_get( - a_uint32_t dev_id, - a_uint32_t index, - unsigned int *value); - -sw_error_t -sfp_link_len_om3_mode_1m_get( - a_uint32_t dev_id, - a_uint32_t index, - unsigned int *value); - -sw_error_t -sfp_link_len_single_mode_100m_get( - a_uint32_t dev_id, - a_uint32_t index, - unsigned int *value); - -sw_error_t -sfp_link_len_om2_mode_10m_get( - a_uint32_t dev_id, - a_uint32_t index, - unsigned int *value); - -sw_error_t -sfp_link_len_copper_mode_1m_get( - a_uint32_t dev_id, - a_uint32_t index, - unsigned int *value); - -sw_error_t -sfp_link_len_om1_mode_10m_get( - a_uint32_t dev_id, - a_uint32_t index, - unsigned int *value); - -sw_error_t -sfp_link_len_single_mode_km_get( - a_uint32_t dev_id, - a_uint32_t index, - unsigned int *value); - -sw_error_t -sfp_vendor_rev_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint8_t *value); - -sw_error_t -sfp_vendor_name_get( - a_uint32_t dev_id, a_uint32_t index, - a_uint8_t *value); - -sw_error_t -sfp_vendor_oui_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint8_t *value); - -sw_error_t -sfp_vendor_pn_get( - a_uint32_t dev_id, a_uint32_t index, - a_uint8_t *value); - -sw_error_t -sfp_laser_wavelength_get( - a_uint32_t dev_id, - a_uint32_t index, - unsigned int *value); - -sw_error_t -sfp_base_check_code_get( - a_uint32_t dev_id, - a_uint32_t index, - unsigned int *value); - -sw_error_t -sfp_option_linear_recv_output_get( - a_uint32_t dev_id, - a_uint32_t index, - unsigned int *value); - -sw_error_t -sfp_option_pwr_level_declar_get( - a_uint32_t dev_id, - a_uint32_t index, - unsigned int *value); - -sw_error_t -sfp_option_unallocated_1_get( - a_uint32_t dev_id, - a_uint32_t index, - unsigned int *value); - -sw_error_t -sfp_option_unallocated_3_get( - a_uint32_t dev_id, - a_uint32_t index, - unsigned int *value); - -sw_error_t -sfp_option_loss_signal_get( - a_uint32_t dev_id, - a_uint32_t index, - unsigned int *value); - -sw_error_t -sfp_option_rate_sel_get( - a_uint32_t dev_id, - a_uint32_t index, - unsigned int *value); - -sw_error_t -sfp_option_unallocated_2_get( - a_uint32_t dev_id, - a_uint32_t index, - unsigned int *value); - -sw_error_t -sfp_option_loss_invert_signal_get( - a_uint32_t dev_id, - a_uint32_t index, - unsigned int *value); - -sw_error_t -sfp_option_tx_disable_get( - a_uint32_t dev_id, - a_uint32_t index, - unsigned int *value); - -sw_error_t -sfp_option_cool_transc_declar_get( - a_uint32_t dev_id, - a_uint32_t index, - unsigned int *value); - -sw_error_t -sfp_option_tx_fault_signal_get( - a_uint32_t dev_id, - a_uint32_t index, - unsigned int *value); - -sw_error_t -sfp_rate_ctrl_upper_get( - a_uint32_t dev_id, - a_uint32_t index, - unsigned int *value); - -sw_error_t -sfp_rate_ctrl_lower_get( - a_uint32_t dev_id, - a_uint32_t index, - unsigned int *value); - -sw_error_t -sfp_vendor_ext_date_code_get( - a_uint32_t dev_id, a_uint32_t index, - a_uint8_t *value); - -sw_error_t -sfp_vendor_ext_sn_get( - a_uint32_t dev_id, a_uint32_t index, - a_uint8_t *value); - -sw_error_t -sfp_enhanced_diag_mon_flag_get( - a_uint32_t dev_id, - a_uint32_t index, - unsigned int *value); - -sw_error_t -sfp_enhanced_rx_los_op_get( - a_uint32_t dev_id, - a_uint32_t index, - unsigned int *value); - -sw_error_t -sfp_enhanced_cmpl_feature_get( - a_uint32_t dev_id, - a_uint32_t index, - unsigned int *value); - -sw_error_t -sfp_enhanced_tx_disable_ctrl_op_get( - a_uint32_t dev_id, - a_uint32_t index, - unsigned int *value); - -sw_error_t -sfp_enhanced_alarm_warning_flag_op_get( - a_uint32_t dev_id, - a_uint32_t index, - unsigned int *value); - -sw_error_t -sfp_enhanced_addr_mode_get( - a_uint32_t dev_id, - a_uint32_t index, - unsigned int *value); - -sw_error_t -sfp_enhanced_unallocated_op_get( - a_uint32_t dev_id, - a_uint32_t index, - unsigned int *value); - -sw_error_t -sfp_enhanced_soft_rate_sel_op_get( - a_uint32_t dev_id, - a_uint32_t index, - unsigned int *value); - -sw_error_t -sfp_enhanced_external_cal_get( - a_uint32_t dev_id, - a_uint32_t index, - unsigned int *value); - -sw_error_t -sfp_enhanced_internal_cal_get( - a_uint32_t dev_id, - a_uint32_t index, - unsigned int *value); - -sw_error_t -sfp_enhanced_re_pwr_type_get( - a_uint32_t dev_id, - a_uint32_t index, - unsigned int *value); - -sw_error_t -sfp_enhanced_soft_rate_ctrl_op_get( - a_uint32_t dev_id, - a_uint32_t index, - unsigned int *value); - -sw_error_t -sfp_enhanced_app_sel_op_get( - a_uint32_t dev_id, - a_uint32_t index, - unsigned int *value); - -sw_error_t -sfp_enhanced_legacy_type_get( - a_uint32_t dev_id, - a_uint32_t index, - unsigned int *value); - -sw_error_t -sfp_enhanced_tx_fault_op_get( - a_uint32_t dev_id, - a_uint32_t index, - unsigned int *value); - -sw_error_t -sfp_enhanced_unallocated_type_get( - a_uint32_t dev_id, - a_uint32_t index, - unsigned int *value); - -sw_error_t -sfp_ext_check_code_get( - a_uint32_t dev_id, - a_uint32_t index, - unsigned int *value); - -sw_error_t -sfp_diag_threshold_get( - a_uint32_t dev_id, - a_uint32_t index, - union sfp_diag_threshold_u *value); - -sw_error_t -sfp_diag_cal_const_get( - a_uint32_t dev_id, - a_uint32_t index, - union sfp_diag_cal_const_u *value); - -sw_error_t -sfp_diag_dmi_get( - a_uint32_t dev_id, - a_uint32_t index, - union sfp_diag_dmi_u *value); - -sw_error_t -sfp_diag_realtime_get( - a_uint32_t dev_id, - a_uint32_t index, - union sfp_diag_realtime_u *value); - -sw_error_t -sfp_diag_optional_ctrl_status_get( - a_uint32_t dev_id, - a_uint32_t index, - union sfp_diag_optional_ctrl_status_u *value); - -sw_error_t -sfp_diag_flag_get( - a_uint32_t dev_id, - a_uint32_t index, - union sfp_diag_flag_u *value); - -sw_error_t -sfp_diag_extended_ctrl_status_get( - a_uint32_t dev_id, - a_uint32_t index, - union sfp_diag_extended_ctrl_status_u *value); - -sw_error_t -sfp_diag_threshold_rx_pwr_low_alarm_get( - a_uint32_t dev_id, - a_uint32_t index, - unsigned int *value); - -sw_error_t -sfp_diag_threshold_rx_pwr_high_warning_get( - a_uint32_t dev_id, - a_uint32_t index, - unsigned int *value); - -sw_error_t -sfp_diag_threshold_temp_low_alarm_get( - a_uint32_t dev_id, - a_uint32_t index, - unsigned int *value); - -sw_error_t -sfp_diag_threshold_vol_high_alarm_get( - a_uint32_t dev_id, - a_uint32_t index, - unsigned int *value); - -sw_error_t -sfp_diag_threshold_tx_pwr_high_alarm_get( - a_uint32_t dev_id, - a_uint32_t index, - unsigned int *value); - -sw_error_t -sfp_diag_threshold_bias_low_alarm_get( - a_uint32_t dev_id, - a_uint32_t index, - unsigned int *value); - -sw_error_t -sfp_diag_threshold_bias_high_alarm_get( - a_uint32_t dev_id, - a_uint32_t index, - unsigned int *value); - -sw_error_t -sfp_diag_threshold_vol_low_alarm_get( - a_uint32_t dev_id, - a_uint32_t index, - unsigned int *value); - -sw_error_t -sfp_diag_threshold_bias_high_warning_get( - a_uint32_t dev_id, - a_uint32_t index, - unsigned int *value); - -sw_error_t -sfp_diag_threshold_temp_high_warning_get( - a_uint32_t dev_id, - a_uint32_t index, - unsigned int *value); - -sw_error_t -sfp_diag_threshold_rx_pwr_low_warning_get( - a_uint32_t dev_id, - a_uint32_t index, - unsigned int *value); - -sw_error_t -sfp_diag_threshold_vol_low_warning_get( - a_uint32_t dev_id, - a_uint32_t index, - unsigned int *value); - -sw_error_t -sfp_diag_threshold_tx_pwr_low_alarm_get( - a_uint32_t dev_id, - a_uint32_t index, - unsigned int *value); - -sw_error_t -sfp_diag_threshold_bias_low_warning_get( - a_uint32_t dev_id, - a_uint32_t index, - unsigned int *value); - -sw_error_t -sfp_diag_threshold_temp_high_alarm_get( - a_uint32_t dev_id, - a_uint32_t index, - unsigned int *value); - -sw_error_t -sfp_diag_threshold_tx_pwr_high_warning_get( - a_uint32_t dev_id, - a_uint32_t index, - unsigned int *value); - -sw_error_t -sfp_diag_threshold_vol_high_warning_get( - a_uint32_t dev_id, - a_uint32_t index, - unsigned int *value); - -sw_error_t -sfp_diag_threshold_temp_low_warning_get( - a_uint32_t dev_id, - a_uint32_t index, - unsigned int *value); - -sw_error_t -sfp_diag_threshold_rx_pwr_high_alarm_get( - a_uint32_t dev_id, - a_uint32_t index, - unsigned int *value); - -sw_error_t -sfp_diag_threshold_tx_pwr_low_warning_get( - a_uint32_t dev_id, - a_uint32_t index, - unsigned int *value); - -sw_error_t -sfp_diag_cal_const_rx_pwr_1_get( - a_uint32_t dev_id, - a_uint32_t index, - unsigned int *value); - -sw_error_t -sfp_diag_cal_const_t_slope_get( - a_uint32_t dev_id, - a_uint32_t index, - unsigned int *value); - -sw_error_t -sfp_diag_cal_const_rx_pwr_3_get( - a_uint32_t dev_id, - a_uint32_t index, - unsigned int *value); - -sw_error_t -sfp_diag_cal_const_rx_pwr_2_get( - a_uint32_t dev_id, - a_uint32_t index, - unsigned int *value); - -sw_error_t -sfp_diag_cal_const_tx_i_slope_get( - a_uint32_t dev_id, - a_uint32_t index, - unsigned int *value); - -sw_error_t -sfp_diag_cal_const_v_slope_get( - a_uint32_t dev_id, - a_uint32_t index, - unsigned int *value); - -sw_error_t -sfp_diag_cal_const_tx_pwr_slope_get( - a_uint32_t dev_id, - a_uint32_t index, - unsigned int *value); - -sw_error_t -sfp_diag_cal_const_rx_pwr_4_get( - a_uint32_t dev_id, - a_uint32_t index, - unsigned int *value); - -sw_error_t -sfp_diag_cal_const_rx_pwr_0_get( - a_uint32_t dev_id, - a_uint32_t index, - unsigned int *value); - -sw_error_t -sfp_diag_dmi_check_code_get( - a_uint32_t dev_id, - a_uint32_t index, - unsigned int *value); - -sw_error_t -sfp_diag_realtime_vcc_get( - a_uint32_t dev_id, - a_uint32_t index, - unsigned int *value); - -sw_error_t -sfp_diag_realtime_tx_pwr_get( - a_uint32_t dev_id, - a_uint32_t index, - unsigned int *value); - -sw_error_t -sfp_diag_realtime_tx_bias_get( - a_uint32_t dev_id, - a_uint32_t index, - unsigned int *value); - -sw_error_t -sfp_diag_realtime_rx_pwr_get( - a_uint32_t dev_id, - a_uint32_t index, - unsigned int *value); - -sw_error_t -sfp_diag_realtime_tmp_get( - a_uint32_t dev_id, - a_uint32_t index, - unsigned int *value); - -sw_error_t -sfp_diag_optional_ctrl_status_rs_get( - a_uint32_t dev_id, - a_uint32_t index, - unsigned int *value); - -sw_error_t -sfp_diag_optional_ctrl_status_tx_fault_get( - a_uint32_t dev_id, - a_uint32_t index, - unsigned int *value); - -sw_error_t -sfp_diag_optional_ctrl_status_rx_los_get( - a_uint32_t dev_id, - a_uint32_t index, - unsigned int *value); - -sw_error_t -sfp_diag_optional_ctrl_status_data_ready_get( - a_uint32_t dev_id, - a_uint32_t index, - unsigned int *value); - -sw_error_t -sfp_diag_optional_ctrl_status_soft_rate_sel_get( - a_uint32_t dev_id, - a_uint32_t index, - unsigned int *value); - -sw_error_t -sfp_diag_optional_ctrl_status_soft_tx_disable_sel_get( - a_uint32_t dev_id, - a_uint32_t index, - unsigned int *value); - -sw_error_t -sfp_diag_optional_ctrl_status_rate_sel_get( - a_uint32_t dev_id, - a_uint32_t index, - unsigned int *value); - -sw_error_t -sfp_diag_optional_ctrl_status_tx_disable_get( - a_uint32_t dev_id, - a_uint32_t index, - unsigned int *value); - -sw_error_t -sfp_diag_flag_rx_pwr_low_alarm_get( - a_uint32_t dev_id, - a_uint32_t index, - unsigned int *value); - -sw_error_t -sfp_diag_flag_rx_pwr_high_warning_get( - a_uint32_t dev_id, - a_uint32_t index, - unsigned int *value); - -sw_error_t -sfp_diag_flag_tx_bias_high_alarm_get( - a_uint32_t dev_id, - a_uint32_t index, - unsigned int *value); - -sw_error_t -sfp_diag_flag_tmp_high_alarm_get( - a_uint32_t dev_id, - a_uint32_t index, - unsigned int *value); - -sw_error_t -sfp_diag_flag_tmp_low_alarm_get( - a_uint32_t dev_id, - a_uint32_t index, - unsigned int *value); - -sw_error_t -sfp_diag_flag_tx_pwr_high_alarm_get( - a_uint32_t dev_id, - a_uint32_t index, - unsigned int *value); - -sw_error_t -sfp_diag_flag_vcc_low_warning_get( - a_uint32_t dev_id, - a_uint32_t index, - unsigned int *value); - -sw_error_t -sfp_diag_flag_vcc_high_warning_get( - a_uint32_t dev_id, - a_uint32_t index, - unsigned int *value); - -sw_error_t -sfp_diag_flag_rx_pwr_low_warning_get( - a_uint32_t dev_id, - a_uint32_t index, - unsigned int *value); - -sw_error_t -sfp_diag_flag_unallocated_get( - a_uint32_t dev_id, - a_uint32_t index, - unsigned int *value); - -sw_error_t -sfp_diag_flag_tx_bias_high_warning_get( - a_uint32_t dev_id, - a_uint32_t index, - unsigned int *value); - -sw_error_t -sfp_diag_flag_vcc_low_alarm_get( - a_uint32_t dev_id, - a_uint32_t index, - unsigned int *value); - -sw_error_t -sfp_diag_flag_tx_pwr_low_alarm_get( - a_uint32_t dev_id, - a_uint32_t index, - unsigned int *value); - -sw_error_t -sfp_diag_flag_vcc_high_alarm_get( - a_uint32_t dev_id, - a_uint32_t index, - unsigned int *value); - -sw_error_t -sfp_diag_flag_tmp_low_warning_get( - a_uint32_t dev_id, - a_uint32_t index, - unsigned int *value); - -sw_error_t -sfp_diag_flag_tx_bias_low_warning_get( - a_uint32_t dev_id, - a_uint32_t index, - unsigned int *value); - -sw_error_t -sfp_diag_flag_tx_bias_low_alarm_get( - a_uint32_t dev_id, - a_uint32_t index, - unsigned int *value); - -sw_error_t -sfp_diag_flag_tmp_high_warning_get( - a_uint32_t dev_id, - a_uint32_t index, - unsigned int *value); - -sw_error_t -sfp_diag_flag_tx_pwr_high_warning_get( - a_uint32_t dev_id, - a_uint32_t index, - unsigned int *value); - -sw_error_t -sfp_diag_flag_rx_pwr_high_alarm_get( - a_uint32_t dev_id, - a_uint32_t index, - unsigned int *value); - -sw_error_t -sfp_diag_flag_tx_pwr_low_warning_get( - a_uint32_t dev_id, - a_uint32_t index, - unsigned int *value); - -sw_error_t -sfp_diag_extended_ctrl_status_unallocated_get( - a_uint32_t dev_id, - a_uint32_t index, - unsigned int *value); - -sw_error_t -sfp_diag_extended_ctrl_status_pwr_level_op_state_get( - a_uint32_t dev_id, - a_uint32_t index, - unsigned int *value); - -sw_error_t -sfp_diag_extended_ctrl_status_soft_rs_sel_get( - a_uint32_t dev_id, - a_uint32_t index, - unsigned int *value); - -sw_error_t -sfp_diag_extended_ctrl_status_pwr_level_sel_get( - a_uint32_t dev_id, - a_uint32_t index, - unsigned int *value); - -#endif diff --git a/feeds/ipq807x/qca-ssdk/src/include/hsl/sfp/sfp_access.h b/feeds/ipq807x/qca-ssdk/src/include/hsl/sfp/sfp_access.h deleted file mode 100755 index d96c66ee2..000000000 --- a/feeds/ipq807x/qca-ssdk/src/include/hsl/sfp/sfp_access.h +++ /dev/null @@ -1,53 +0,0 @@ -/* - * Copyright (c) 2019, The Linux Foundation. All rights reserved. - * Permission to use, copy, modify, and/or distribute this software for - * any purpose with or without fee is hereby granted, provided that the - * above copyright notice and this permission notice appear in all copies. - * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES - * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR - * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES - * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN - * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT - * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. - */ - - - -#ifndef _SFP_ACCESS_H_ -#define _SFP_ACCESS_H_ - -#ifdef __cplusplus -extern "C" { -#endif /* __cplusplus */ - -#include "sw.h" - -#define SFP_BASE_ADDR 0x0 -#define SFP_DIAG_BASE_ADDR 0x0 - -#define SFP_EEPROM_BASE_A0 0x50 -#define SFP_EEPROM_DIAG_A2 0x51 - - -sw_error_t -sfp_data_tbl_get(a_uint32_t dev_id, a_uint32_t index, a_uint32_t i2c_slave, - a_uint32_t data_addr, a_uint8_t *buf, a_uint32_t count); - -sw_error_t -sfp_data_get(a_uint32_t dev_id, a_uint32_t index, a_uint32_t i2c_slave, - a_uint32_t data_addr, a_uint8_t *buf); - -sw_error_t -sfp_data_tbl_set(a_uint32_t dev_id, a_uint32_t index, a_uint32_t i2c_slave, - a_uint32_t data_addr, a_uint8_t *buf, a_uint32_t count); - -sw_error_t -sfp_data_set(a_uint32_t dev_id, a_uint32_t index, a_uint32_t i2c_slave, - a_uint32_t data_addr, a_uint8_t *buf); - -#ifdef __cplusplus -} -#endif /* __cplusplus */ - -#endif /* _PPE_SFP_ACCESS_H_ */ diff --git a/feeds/ipq807x/qca-ssdk/src/include/hsl/sfp/sfp_reg.h b/feeds/ipq807x/qca-ssdk/src/include/hsl/sfp/sfp_reg.h deleted file mode 100755 index 59fb4dcf6..000000000 --- a/feeds/ipq807x/qca-ssdk/src/include/hsl/sfp/sfp_reg.h +++ /dev/null @@ -1,1319 +0,0 @@ -/* - * Copyright (c) 2019, The Linux Foundation. All rights reserved. - * Permission to use, copy, modify, and/or distribute this software for - * any purpose with or without fee is hereby granted, provided that the - * above copyright notice and this permission notice appear in all copies. - * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES - * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR - * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES - * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN - * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT - * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. - */ - - -/** - * @defgroup - * @{ - */ -#ifndef _SFP_REG_H_ -#define _SFP_REG_H_ - -/*[register] SFP_DEV_TYPE*/ -#define SFP_DEV_TYPE -#define SFP_DEV_TYPE_ADDRESS 0x0 -#define SFP_DEV_TYPE_NUM 1 -#define SFP_DEV_TYPE_INC 0x1 -#define SFP_DEV_TYPE_TYPE REG_TYPE_RO -#define SFP_DEV_TYPE_DEFAULT 0x0 - /*[field] ID*/ - #define SFP_DEV_TYPE_ID - #define SFP_DEV_TYPE_ID_OFFSET 0 - #define SFP_DEV_TYPE_ID_LEN 8 - #define SFP_DEV_TYPE_ID_DEFAULT 0x0 - -struct sfp_dev_type { - a_uint8_t id:8; -}; - -union sfp_dev_type_u { - a_uint8_t val; - struct sfp_dev_type bf; -}; - -/*[register] SFP_DEV_TYPE_EXT*/ -#define SFP_DEV_TYPE_EXT -#define SFP_DEV_TYPE_EXT_ADDRESS 0x1 -#define SFP_DEV_TYPE_EXT_NUM 1 -#define SFP_DEV_TYPE_EXT_INC 0x1 -#define SFP_DEV_TYPE_EXT_TYPE REG_TYPE_RO -#define SFP_DEV_TYPE_EXT_DEFAULT 0x0 - /*[field] ID*/ - #define SFP_DEV_TYPE_EXT_ID - #define SFP_DEV_TYPE_EXT_ID_OFFSET 0 - #define SFP_DEV_TYPE_EXT_ID_LEN 8 - #define SFP_DEV_TYPE_EXT_ID_DEFAULT 0x0 - -struct sfp_dev_type_ext { - a_uint8_t id:8; -}; - -union sfp_dev_type_ext_u { - a_uint8_t val; - struct sfp_dev_type_ext bf; -}; - -/*[register] SFP_DEV_CONNECTOR_TYPE*/ -#define SFP_DEV_CONNECTOR_TYPE -#define SFP_DEV_CONNECTOR_TYPE_ADDRESS 0x2 -#define SFP_DEV_CONNECTOR_TYPE_NUM 1 -#define SFP_DEV_CONNECTOR_TYPE_INC 0x1 -#define SFP_DEV_CONNECTOR_TYPE_TYPE REG_TYPE_RO -#define SFP_DEV_CONNECTOR_TYPE_DEFAULT 0x0 - /*[field] CODE*/ - #define SFP_DEV_CONNECTOR_TYPE_CODE - #define SFP_DEV_CONNECTOR_TYPE_CODE_OFFSET 0 - #define SFP_DEV_CONNECTOR_TYPE_CODE_LEN 8 - #define SFP_DEV_CONNECTOR_TYPE_CODE_DEFAULT 0x0 - -struct sfp_dev_connector_type { - a_uint8_t code:8; -}; - -union sfp_dev_connector_type_u { - a_uint8_t val; - struct sfp_dev_connector_type bf; -}; - -/*[register] SFP_TRANSC*/ -#define SFP_TRANSC -#define SFP_TRANSC_ADDRESS 0x3 -#define SFP_TRANSC_NUM 1 -#define SFP_TRANSC_INC 0x8 -#define SFP_TRANSC_TYPE REG_TYPE_RO -#define SFP_TRANSC_DEFAULT 0x0 - /*[field] INFINIBAND_CCODE*/ - #define SFP_TRANSC_INFINIBAND_CCODE - #define SFP_TRANSC_INFINIBAND_CCODE_OFFSET 0 - #define SFP_TRANSC_INFINIBAND_CCODE_LEN 4 - #define SFP_TRANSC_INFINIBAND_CCODE_DEFAULT 0x0 - /*[field] ETH_10G_CCODE*/ - #define SFP_TRANSC_ETH_10G_CCODE - #define SFP_TRANSC_ETH_10G_CCODE_OFFSET 4 - #define SFP_TRANSC_ETH_10G_CCODE_LEN 4 - #define SFP_TRANSC_ETH_10G_CCODE_DEFAULT 0x0 - /*[field] SONET_CCODE_1*/ - #define SFP_TRANSC_SONET_CCODE_1 - #define SFP_TRANSC_SONET_CCODE_1_OFFSET 8 - #define SFP_TRANSC_SONET_CCODE_1_LEN 6 - #define SFP_TRANSC_SONET_CCODE_1_DEFAULT 0x0 - /*[field] ESCON_CCODE*/ - #define SFP_TRANSC_ESCON_CCODE - #define SFP_TRANSC_ESCON_CCODE_OFFSET 14 - #define SFP_TRANSC_ESCON_CCODE_LEN 2 - #define SFP_TRANSC_ESCON_CCODE_DEFAULT 0x0 - /*[field] SONET_CCODE_2*/ - #define SFP_TRANSC_SONET_CCODE_2 - #define SFP_TRANSC_SONET_CCODE_2_OFFSET 16 - #define SFP_TRANSC_SONET_CCODE_2_LEN 8 - #define SFP_TRANSC_SONET_CCODE_2_DEFAULT 0x0 - /*[field] ETH_CCODE*/ - #define SFP_TRANSC_ETH_CCODE - #define SFP_TRANSC_ETH_CCODE_OFFSET 24 - #define SFP_TRANSC_ETH_CCODE_LEN 8 - #define SFP_TRANSC_ETH_CCODE_DEFAULT 0x0 - /*[field] FIBER_CH_TECH_1*/ - #define SFP_TRANSC_FIBER_CH_TECH_1 - #define SFP_TRANSC_FIBER_CH_TECH_1_OFFSET 32 - #define SFP_TRANSC_FIBER_CH_TECH_1_LEN 3 - #define SFP_TRANSC_FIBER_CH_TECH_1_DEFAULT 0x0 - /*[field] FIBER_CH_LINK_LEN*/ - #define SFP_TRANSC_FIBER_CH_LINK_LEN - #define SFP_TRANSC_FIBER_CH_LINK_LEN_OFFSET 35 - #define SFP_TRANSC_FIBER_CH_LINK_LEN_LEN 5 - #define SFP_TRANSC_FIBER_CH_LINK_LEN_DEFAULT 0x0 - /*[field] UNALLOCATED*/ - #define SFP_TRANSC_UNALLOCATED - #define SFP_TRANSC_UNALLOCATED_OFFSET 40 - #define SFP_TRANSC_UNALLOCATED_LEN 2 - #define SFP_TRANSC_UNALLOCATED_DEFAULT 0x0 - /*[field] CABLE_TECH*/ - #define SFP_TRANSC_CABLE_TECH - #define SFP_TRANSC_CABLE_TECH_OFFSET 42 - #define SFP_TRANSC_CABLE_TECH_LEN 2 - #define SFP_TRANSC_CABLE_TECH_DEFAULT 0x0 - /*[field] FIBER_CH_TECH_2*/ - #define SFP_TRANSC_FIBER_CH_TECH_2 - #define SFP_TRANSC_FIBER_CH_TECH_2_OFFSET 44 - #define SFP_TRANSC_FIBER_CH_TECH_2_LEN 4 - #define SFP_TRANSC_FIBER_CH_TECH_2_DEFAULT 0x0 - /*[field] FIBER_CHAN_TM_MEDIA*/ - #define SFP_TRANSC_FIBER_CHAN_TM_MEDIA - #define SFP_TRANSC_FIBER_CHAN_TM_MEDIA_OFFSET 48 - #define SFP_TRANSC_FIBER_CHAN_TM_MEDIA_LEN 8 - #define SFP_TRANSC_FIBER_CHAN_TM_MEDIA_DEFAULT 0x0 - /*[field] FIBER_CH_SPEED*/ - #define SFP_TRANSC_FIBER_CH_SPEED - #define SFP_TRANSC_FIBER_CH_SPEED_OFFSET 56 - #define SFP_TRANSC_FIBER_CH_SPEED_LEN 8 - #define SFP_TRANSC_FIBER_CH_SPEED_DEFAULT 0x0 - -struct sfp_transc { - a_uint8_t infiniband_ccode:4; - a_uint8_t eth_10g_ccode:4; - a_uint8_t sonet_ccode_1:6; - a_uint8_t escon_ccode:2; - a_uint8_t sonet_ccode_2:8; - a_uint8_t eth_ccode:8; - a_uint8_t fiber_ch_tech_1:3; - a_uint8_t fiber_ch_link_len:5; - a_uint8_t unallocated:2; - a_uint8_t cable_tech:2; - a_uint8_t fiber_ch_tech_2:4; - a_uint8_t fiber_chan_tm_media:8; - a_uint8_t fiber_ch_speed:8; -}; - -union sfp_transc_u { - a_uint8_t val[8]; - struct sfp_transc bf; -}; - -/*[register] SFP_ENCODING*/ -#define SFP_ENCODING -#define SFP_ENCODING_ADDRESS 0xb -#define SFP_ENCODING_NUM 1 -#define SFP_ENCODING_INC 0x1 -#define SFP_ENCODING_TYPE REG_TYPE_RO -#define SFP_ENCODING_DEFAULT 0x0 - /*[field] CODE*/ - #define SFP_ENCODING_CODE - #define SFP_ENCODING_CODE_OFFSET 0 - #define SFP_ENCODING_CODE_LEN 8 - #define SFP_ENCODING_CODE_DEFAULT 0x0 - -struct sfp_encoding { - a_uint8_t code:8; -}; - -union sfp_encoding_u { - a_uint8_t val; - struct sfp_encoding bf; -}; - -/*[register] SFP_BR*/ -#define SFP_BR -#define SFP_BR_ADDRESS 0xc -#define SFP_BR_NUM 1 -#define SFP_BR_INC 0x1 -#define SFP_BR_TYPE REG_TYPE_RO -#define SFP_BR_DEFAULT 0x0 - /*[field] BIT*/ - #define SFP_BR_BIT - #define SFP_BR_BIT_OFFSET 0 - #define SFP_BR_BIT_LEN 8 - #define SFP_BR_BIT_DEFAULT 0x0 - -struct sfp_br { - a_uint8_t bit:8; -}; - -union sfp_br_u { - a_uint8_t val; - struct sfp_br bf; -}; - -/*[register] SFP_RATE*/ -#define SFP_RATE -#define SFP_RATE_ADDRESS 0xd -#define SFP_RATE_NUM 1 -#define SFP_RATE_INC 0x1 -#define SFP_RATE_TYPE REG_TYPE_RO -#define SFP_RATE_DEFAULT 0x0 - /*[field] ID*/ - #define SFP_RATE_ID - #define SFP_RATE_ID_OFFSET 0 - #define SFP_RATE_ID_LEN 8 - #define SFP_RATE_ID_DEFAULT 0x0 - -struct sfp_rate { - a_uint8_t id:8; -}; - -union sfp_rate_u { - a_uint8_t val; - struct sfp_rate bf; -}; - -/*[register] SFP_LINK_LEN*/ -#define SFP_LINK_LEN -#define SFP_LINK_LEN_ADDRESS 0xe -#define SFP_LINK_LEN_NUM 1 -#define SFP_LINK_LEN_INC 0x6 -#define SFP_LINK_LEN_TYPE REG_TYPE_RO -#define SFP_LINK_LEN_DEFAULT 0x0 - /*[field] SINGLE_MODE_KM*/ - #define SFP_LINK_LEN_SINGLE_MODE_KM - #define SFP_LINK_LEN_SINGLE_MODE_KM_OFFSET 0 - #define SFP_LINK_LEN_SINGLE_MODE_KM_LEN 8 - #define SFP_LINK_LEN_SINGLE_MODE_KM_DEFAULT 0x0 - /*[field] SINGLE_MODE_100M*/ - #define SFP_LINK_LEN_SINGLE_MODE_100M - #define SFP_LINK_LEN_SINGLE_MODE_100M_OFFSET 8 - #define SFP_LINK_LEN_SINGLE_MODE_100M_LEN 8 - #define SFP_LINK_LEN_SINGLE_MODE_100M_DEFAULT 0x0 - /*[field] OM2_MODE_10M*/ - #define SFP_LINK_LEN_OM2_MODE_10M - #define SFP_LINK_LEN_OM2_MODE_10M_OFFSET 16 - #define SFP_LINK_LEN_OM2_MODE_10M_LEN 8 - #define SFP_LINK_LEN_OM2_MODE_10M_DEFAULT 0x0 - /*[field] OM1_MODE_10M*/ - #define SFP_LINK_LEN_OM1_MODE_10M - #define SFP_LINK_LEN_OM1_MODE_10M_OFFSET 24 - #define SFP_LINK_LEN_OM1_MODE_10M_LEN 8 - #define SFP_LINK_LEN_OM1_MODE_10M_DEFAULT 0x0 - /*[field] COPPER_MODE_1M*/ - #define SFP_LINK_LEN_COPPER_MODE_1M - #define SFP_LINK_LEN_COPPER_MODE_1M_OFFSET 32 - #define SFP_LINK_LEN_COPPER_MODE_1M_LEN 8 - #define SFP_LINK_LEN_COPPER_MODE_1M_DEFAULT 0x0 - /*[field] OM3_MODE_1M*/ - #define SFP_LINK_LEN_OM3_MODE_1M - #define SFP_LINK_LEN_OM3_MODE_1M_OFFSET 40 - #define SFP_LINK_LEN_OM3_MODE_1M_LEN 8 - #define SFP_LINK_LEN_OM3_MODE_1M_DEFAULT 0x0 - -struct sfp_link_len { - a_uint8_t single_mode_km:8; - a_uint8_t single_mode_100m:8; - a_uint8_t om2_mode_10m:8; - a_uint8_t om1_mode_10m:8; - a_uint8_t copper_mode_1m:8; - a_uint8_t om3_mode_1m:8; -}; - -union sfp_link_len_u { - a_uint8_t val[6]; - struct sfp_link_len bf; -}; - -/*[register] SFP_VENDOR*/ -#define SFP_VENDOR -#define SFP_VENDOR_ADDRESS 0x14 -#define SFP_VENDOR_NUM 1 -#define SFP_VENDOR_INC 0x28 -#define SFP_VENDOR_TYPE REG_TYPE_RO -#define SFP_VENDOR_DEFAULT 0x0 - /*[field] NAME*/ - #define SFP_VENDOR_NAME - #define SFP_VENDOR_NAME_OFFSET 0 - #define SFP_VENDOR_NAME_LEN 128 - #define SFP_VENDOR_NAME_DEFAULT 0x0 - /*[field] TRANSCODE*/ - #define SFP_VENDOR_TRANSCODE - #define SFP_VENDOR_TRANSCODE_OFFSET 128 - #define SFP_VENDOR_TRANSCODE_LEN 8 - #define SFP_VENDOR_TRANSCODE_DEFAULT 0x0 - /*[field] OUI*/ - #define SFP_VENDOR_OUI - #define SFP_VENDOR_OUI_OFFSET 136 - #define SFP_VENDOR_OUI_LEN 24 - #define SFP_VENDOR_OUI_DEFAULT 0x0 - /*[field] PN*/ - #define SFP_VENDOR_PN - #define SFP_VENDOR_PN_OFFSET 160 - #define SFP_VENDOR_PN_LEN 128 - #define SFP_VENDOR_PN_DEFAULT 0x0 - /*[field] REV*/ - #define SFP_VENDOR_REV - #define SFP_VENDOR_REV_OFFSET 288 - #define SFP_VENDOR_REV_LEN 32 - #define SFP_VENDOR_REV_DEFAULT 0x0 - -struct sfp_vendor { - a_uint8_t name_0:8; - a_uint8_t name_1:8; - a_uint8_t name_2:8; - a_uint8_t name_3:8; - a_uint8_t name_4:8; - a_uint8_t name_5:8; - a_uint8_t name_6:8; - a_uint8_t name_7:8; - a_uint8_t name_8:8; - a_uint8_t name_9:8; - a_uint8_t name_10:8; - a_uint8_t name_11:8; - a_uint8_t name_12:8; - a_uint8_t name_13:8; - a_uint8_t name_14:8; - a_uint8_t name_15:8; - a_uint8_t transcode:8; - a_uint8_t oui_0:8; - a_uint8_t oui_1:8; - a_uint8_t oui_2:8; - a_uint8_t pn_0:8; - a_uint8_t pn_1:8; - a_uint8_t pn_2:8; - a_uint8_t pn_3:8; - a_uint8_t pn_4:8; - a_uint8_t pn_5:8; - a_uint8_t pn_6:8; - a_uint8_t pn_7:8; - a_uint8_t pn_8:8; - a_uint8_t pn_9:8; - a_uint8_t pn_10:8; - a_uint8_t pn_11:8; - a_uint8_t pn_12:8; - a_uint8_t pn_13:8; - a_uint8_t pn_14:8; - a_uint8_t pn_15:8; - a_uint8_t rev_0:8; - a_uint8_t rev_1:8; - a_uint8_t rev_2:8; - a_uint8_t rev_3:8; -}; - -union sfp_vendor_u { - a_uint8_t val[40]; - struct sfp_vendor bf; -}; - -/*[register] SFP_LASER*/ -#define SFP_LASER -#define SFP_LASER_ADDRESS 0x3c -#define SFP_LASER_NUM 1 -#define SFP_LASER_INC 0x2 -#define SFP_LASER_TYPE REG_TYPE_RO -#define SFP_LASER_DEFAULT 0x0 - /*[field] WAVELENGTH*/ - #define SFP_LASER_WAVELENGTH - #define SFP_LASER_WAVELENGTH_OFFSET 0 - #define SFP_LASER_WAVELENGTH_LEN 16 - #define SFP_LASER_WAVELENGTH_DEFAULT 0x0 - -struct sfp_laser { - a_uint8_t wavelength_0:8; - a_uint8_t wavelength_1:8; -}; - -union sfp_laser_u { - a_uint8_t val[2]; - struct sfp_laser bf; -}; - -/*[register] SFP_BASE*/ -#define SFP_BASE -#define SFP_BASE_ADDRESS 0x3f -#define SFP_BASE_NUM 1 -#define SFP_BASE_INC 0x1 -#define SFP_BASE_TYPE REG_TYPE_RO -#define SFP_BASE_DEFAULT 0x0 - /*[field] CHECK_CODE*/ - #define SFP_BASE_CHECK_CODE - #define SFP_BASE_CHECK_CODE_OFFSET 0 - #define SFP_BASE_CHECK_CODE_LEN 8 - #define SFP_BASE_CHECK_CODE_DEFAULT 0x0 - -struct sfp_base { - a_uint8_t check_code:8; -}; - -union sfp_base_u { - a_uint8_t val; - struct sfp_base bf; -}; - -/*[register] SFP_OPTION*/ -#define SFP_OPTION -#define SFP_OPTION_ADDRESS 0x40 -#define SFP_OPTION_NUM 1 -#define SFP_OPTION_INC 0x2 -#define SFP_OPTION_TYPE REG_TYPE_RO -#define SFP_OPTION_DEFAULT 0x0 - /*[field] LINEAR_RECV_OUTPUT*/ - #define SFP_OPTION_LINEAR_RECV_OUTPUT - #define SFP_OPTION_LINEAR_RECV_OUTPUT_OFFSET 0 - #define SFP_OPTION_LINEAR_RECV_OUTPUT_LEN 1 - #define SFP_OPTION_LINEAR_RECV_OUTPUT_DEFAULT 0x0 - /*[field] PWR_LEVEL_DECLAR*/ - #define SFP_OPTION_PWR_LEVEL_DECLAR - #define SFP_OPTION_PWR_LEVEL_DECLAR_OFFSET 1 - #define SFP_OPTION_PWR_LEVEL_DECLAR_LEN 1 - #define SFP_OPTION_PWR_LEVEL_DECLAR_DEFAULT 0x0 - /*[field] COOL_TRANSC_DECLAR*/ - #define SFP_OPTION_COOL_TRANSC_DECLAR - #define SFP_OPTION_COOL_TRANSC_DECLAR_OFFSET 2 - #define SFP_OPTION_COOL_TRANSC_DECLAR_LEN 1 - #define SFP_OPTION_COOL_TRANSC_DECLAR_DEFAULT 0x0 - /*[field] UNALLOCATED_1*/ - #define SFP_OPTION_UNALLOCATED_1 - #define SFP_OPTION_UNALLOCATED_1_OFFSET 3 - #define SFP_OPTION_UNALLOCATED_1_LEN 5 - #define SFP_OPTION_UNALLOCATED_1_DEFAULT 0x0 - /*[field] UNALLOCATED_2*/ - #define SFP_OPTION_UNALLOCATED_2 - #define SFP_OPTION_UNALLOCATED_2_OFFSET 8 - #define SFP_OPTION_UNALLOCATED_2_LEN 1 - #define SFP_OPTION_UNALLOCATED_2_DEFAULT 0x0 - /*[field] LOSS_SIGNAL*/ - #define SFP_OPTION_LOSS_SIGNAL - #define SFP_OPTION_LOSS_SIGNAL_OFFSET 9 - #define SFP_OPTION_LOSS_SIGNAL_LEN 1 - #define SFP_OPTION_LOSS_SIGNAL_DEFAULT 0x0 - /*[field] LOSS_INVERT_SIGNAL*/ - #define SFP_OPTION_LOSS_INVERT_SIGNAL - #define SFP_OPTION_LOSS_INVERT_SIGNAL_OFFSET 10 - #define SFP_OPTION_LOSS_INVERT_SIGNAL_LEN 1 - #define SFP_OPTION_LOSS_INVERT_SIGNAL_DEFAULT 0x0 - /*[field] TX_FAULT_SIGNAL*/ - #define SFP_OPTION_TX_FAULT_SIGNAL - #define SFP_OPTION_TX_FAULT_SIGNAL_OFFSET 11 - #define SFP_OPTION_TX_FAULT_SIGNAL_LEN 1 - #define SFP_OPTION_TX_FAULT_SIGNAL_DEFAULT 0x0 - /*[field] TX_DISABLE*/ - #define SFP_OPTION_TX_DISABLE - #define SFP_OPTION_TX_DISABLE_OFFSET 12 - #define SFP_OPTION_TX_DISABLE_LEN 1 - #define SFP_OPTION_TX_DISABLE_DEFAULT 0x0 - /*[field] RATE_SEL*/ - #define SFP_OPTION_RATE_SEL - #define SFP_OPTION_RATE_SEL_OFFSET 13 - #define SFP_OPTION_RATE_SEL_LEN 1 - #define SFP_OPTION_RATE_SEL_DEFAULT 0x0 - /*[field] UNALLOCATED_3*/ - #define SFP_OPTION_UNALLOCATED_3 - #define SFP_OPTION_UNALLOCATED_3_OFFSET 14 - #define SFP_OPTION_UNALLOCATED_3_LEN 2 - #define SFP_OPTION_UNALLOCATED_3_DEFAULT 0x0 - -struct sfp_option { - a_uint8_t linear_recv_output:1; - a_uint8_t pwr_level_declar:1; - a_uint8_t cool_transc_declar:1; - a_uint8_t unallocated_1:5; - a_uint8_t unallocated_2:1; - a_uint8_t loss_signal:1; - a_uint8_t loss_invert_signal:1; - a_uint8_t tx_fault_signal:1; - a_uint8_t tx_disable:1; - a_uint8_t rate_sel:1; - a_uint8_t unallocated_3:2; -}; - -union sfp_option_u { - a_uint8_t val[2]; - struct sfp_option bf; -}; - -/*[register] SFP_RATE_CTRL*/ -#define SFP_RATE_CTRL -#define SFP_RATE_CTRL_ADDRESS 0x42 -#define SFP_RATE_CTRL_NUM 1 -#define SFP_RATE_CTRL_INC 0x2 -#define SFP_RATE_CTRL_TYPE REG_TYPE_RO -#define SFP_RATE_CTRL_DEFAULT 0x0 - /*[field] UPPER*/ - #define SFP_RATE_CTRL_UPPER - #define SFP_RATE_CTRL_UPPER_OFFSET 0 - #define SFP_RATE_CTRL_UPPER_LEN 8 - #define SFP_RATE_CTRL_UPPER_DEFAULT 0x0 - /*[field] LOWER*/ - #define SFP_RATE_CTRL_LOWER - #define SFP_RATE_CTRL_LOWER_OFFSET 8 - #define SFP_RATE_CTRL_LOWER_LEN 8 - #define SFP_RATE_CTRL_LOWER_DEFAULT 0x0 - -struct sfp_rate_ctrl { - a_uint8_t upper:8; - a_uint8_t lower:8; -}; - -union sfp_rate_ctrl_u { - a_uint8_t val[2]; - struct sfp_rate_ctrl bf; -}; - -/*[register] SFP_VENDOR_EXT*/ -#define SFP_VENDOR_EXT -#define SFP_VENDOR_EXT_ADDRESS 0x44 -#define SFP_VENDOR_EXT_NUM 1 -#define SFP_VENDOR_EXT_INC 0x18 -#define SFP_VENDOR_EXT_TYPE REG_TYPE_RO -#define SFP_VENDOR_EXT_DEFAULT 0x0 - /*[field] SN*/ - #define SFP_VENDOR_EXT_SN - #define SFP_VENDOR_EXT_SN_OFFSET 0 - #define SFP_VENDOR_EXT_SN_LEN 128 - #define SFP_VENDOR_EXT_SN_DEFAULT 0x0 - /*[field] DATE_CODE*/ - #define SFP_VENDOR_EXT_DATE_CODE - #define SFP_VENDOR_EXT_DATE_CODE_OFFSET 128 - #define SFP_VENDOR_EXT_DATE_CODE_LEN 64 - #define SFP_VENDOR_EXT_DATE_CODE_DEFAULT 0x0 - -struct sfp_vendor_ext { - a_uint8_t sn_0:8; - a_uint8_t sn_1:8; - a_uint8_t sn_2:8; - a_uint8_t sn_3:8; - a_uint8_t sn_4:8; - a_uint8_t sn_5:8; - a_uint8_t sn_6:8; - a_uint8_t sn_7:8; - a_uint8_t sn_8:8; - a_uint8_t sn_9:8; - a_uint8_t sn_10:8; - a_uint8_t sn_11:8; - a_uint8_t sn_12:8; - a_uint8_t sn_13:8; - a_uint8_t sn_14:8; - a_uint8_t sn_15:8; - a_uint8_t date_code_0:8; - a_uint8_t date_code_1:8; - a_uint8_t date_code_2:8; - a_uint8_t date_code_3:8; - a_uint8_t date_code_4:8; - a_uint8_t date_code_5:8; - a_uint8_t date_code_6:8; - a_uint8_t date_code_7:8; -}; - -union sfp_vendor_ext_u { - a_uint8_t val[24]; - struct sfp_vendor_ext bf; -}; - -/*[register] SFP_ENHANCED*/ -#define SFP_ENHANCED -#define SFP_ENHANCED_ADDRESS 0x5c -#define SFP_ENHANCED_NUM 1 -#define SFP_ENHANCED_INC 0x3 -#define SFP_ENHANCED_TYPE REG_TYPE_RO -#define SFP_ENHANCED_DEFAULT 0x0 - /*[field] UNALLOCATED_TYPE*/ - #define SFP_ENHANCED_UNALLOCATED_TYPE - #define SFP_ENHANCED_UNALLOCATED_TYPE_OFFSET 0 - #define SFP_ENHANCED_UNALLOCATED_TYPE_LEN 2 - #define SFP_ENHANCED_UNALLOCATED_TYPE_DEFAULT 0x0 - /*[field] ADDR_MODE*/ - #define SFP_ENHANCED_ADDR_MODE - #define SFP_ENHANCED_ADDR_MODE_OFFSET 2 - #define SFP_ENHANCED_ADDR_MODE_LEN 1 - #define SFP_ENHANCED_ADDR_MODE_DEFAULT 0x0 - /*[field] RE_PWR_TYPE*/ - #define SFP_ENHANCED_RE_PWR_TYPE - #define SFP_ENHANCED_RE_PWR_TYPE_OFFSET 3 - #define SFP_ENHANCED_RE_PWR_TYPE_LEN 1 - #define SFP_ENHANCED_RE_PWR_TYPE_DEFAULT 0x0 - /*[field] EXTERNAL_CAL*/ - #define SFP_ENHANCED_EXTERNAL_CAL - #define SFP_ENHANCED_EXTERNAL_CAL_OFFSET 4 - #define SFP_ENHANCED_EXTERNAL_CAL_LEN 1 - #define SFP_ENHANCED_EXTERNAL_CAL_DEFAULT 0x0 - /*[field] INTERNAL_CAL*/ - #define SFP_ENHANCED_INTERNAL_CAL - #define SFP_ENHANCED_INTERNAL_CAL_OFFSET 5 - #define SFP_ENHANCED_INTERNAL_CAL_LEN 1 - #define SFP_ENHANCED_INTERNAL_CAL_DEFAULT 0x0 - /*[field] DIAG_MON_FLAG*/ - #define SFP_ENHANCED_DIAG_MON_FLAG - #define SFP_ENHANCED_DIAG_MON_FLAG_OFFSET 6 - #define SFP_ENHANCED_DIAG_MON_FLAG_LEN 1 - #define SFP_ENHANCED_DIAG_MON_FLAG_DEFAULT 0x0 - /*[field] LEGACY_TYPE*/ - #define SFP_ENHANCED_LEGACY_TYPE - #define SFP_ENHANCED_LEGACY_TYPE_OFFSET 7 - #define SFP_ENHANCED_LEGACY_TYPE_LEN 1 - #define SFP_ENHANCED_LEGACY_TYPE_DEFAULT 0x0 - /*[field] UNALLOCATED_OP*/ - #define SFP_ENHANCED_UNALLOCATED_OP - #define SFP_ENHANCED_UNALLOCATED_OP_OFFSET 8 - #define SFP_ENHANCED_UNALLOCATED_OP_LEN 1 - #define SFP_ENHANCED_UNALLOCATED_OP_DEFAULT 0x0 - /*[field] SOFT_RATE_SEL_OP*/ - #define SFP_ENHANCED_SOFT_RATE_SEL_OP - #define SFP_ENHANCED_SOFT_RATE_SEL_OP_OFFSET 9 - #define SFP_ENHANCED_SOFT_RATE_SEL_OP_LEN 1 - #define SFP_ENHANCED_SOFT_RATE_SEL_OP_DEFAULT 0x0 - /*[field] APP_SEL_OP*/ - #define SFP_ENHANCED_APP_SEL_OP - #define SFP_ENHANCED_APP_SEL_OP_OFFSET 10 - #define SFP_ENHANCED_APP_SEL_OP_LEN 1 - #define SFP_ENHANCED_APP_SEL_OP_DEFAULT 0x0 - /*[field] SOFT_RATE_CTRL_OP*/ - #define SFP_ENHANCED_SOFT_RATE_CTRL_OP - #define SFP_ENHANCED_SOFT_RATE_CTRL_OP_OFFSET 11 - #define SFP_ENHANCED_SOFT_RATE_CTRL_OP_LEN 1 - #define SFP_ENHANCED_SOFT_RATE_CTRL_OP_DEFAULT 0x0 - /*[field] RX_LOS_OP*/ - #define SFP_ENHANCED_RX_LOS_OP - #define SFP_ENHANCED_RX_LOS_OP_OFFSET 12 - #define SFP_ENHANCED_RX_LOS_OP_LEN 1 - #define SFP_ENHANCED_RX_LOS_OP_DEFAULT 0x0 - /*[field] TX_FAULT_OP*/ - #define SFP_ENHANCED_TX_FAULT_OP - #define SFP_ENHANCED_TX_FAULT_OP_OFFSET 13 - #define SFP_ENHANCED_TX_FAULT_OP_LEN 1 - #define SFP_ENHANCED_TX_FAULT_OP_DEFAULT 0x0 - /*[field] TX_DISABLE_CTRL_OP*/ - #define SFP_ENHANCED_TX_DISABLE_CTRL_OP - #define SFP_ENHANCED_TX_DISABLE_CTRL_OP_OFFSET 14 - #define SFP_ENHANCED_TX_DISABLE_CTRL_OP_LEN 1 - #define SFP_ENHANCED_TX_DISABLE_CTRL_OP_DEFAULT 0x0 - /*[field] ALARM_WARNING_FLAG_OP*/ - #define SFP_ENHANCED_ALARM_WARNING_FLAG_OP - #define SFP_ENHANCED_ALARM_WARNING_FLAG_OP_OFFSET 15 - #define SFP_ENHANCED_ALARM_WARNING_FLAG_OP_LEN 1 - #define SFP_ENHANCED_ALARM_WARNING_FLAG_OP_DEFAULT 0x0 - /*[field] CMPL_FEATURE*/ - #define SFP_ENHANCED_CMPL_FEATURE - #define SFP_ENHANCED_CMPL_FEATURE_OFFSET 16 - #define SFP_ENHANCED_CMPL_FEATURE_LEN 8 - #define SFP_ENHANCED_CMPL_FEATURE_DEFAULT 0x0 - -struct sfp_enhanced { - a_uint8_t unallocated_type:2; - a_uint8_t addr_mode:1; - a_uint8_t re_pwr_type:1; - a_uint8_t external_cal:1; - a_uint8_t internal_cal:1; - a_uint8_t diag_mon_flag:1; - a_uint8_t legacy_type:1; - a_uint8_t unallocated_op:1; - a_uint8_t soft_rate_sel_op:1; - a_uint8_t app_sel_op:1; - a_uint8_t soft_rate_ctrl_op:1; - a_uint8_t rx_los_op:1; - a_uint8_t tx_fault_op:1; - a_uint8_t tx_disable_ctrl_op:1; - a_uint8_t alarm_warning_flag_op:1; - a_uint8_t cmpl_feature:8; -}; - -union sfp_enhanced_u { - a_uint8_t val[3]; - struct sfp_enhanced bf; -}; - -/*[register] SFP_EXT*/ -#define SFP_EXT -#define SFP_EXT_ADDRESS 0x5f -#define SFP_EXT_NUM 1 -#define SFP_EXT_INC 0x1 -#define SFP_EXT_TYPE REG_TYPE_RO -#define SFP_EXT_DEFAULT 0x0 - /*[field] CHECK_CODE*/ - #define SFP_EXT_CHECK_CODE - #define SFP_EXT_CHECK_CODE_OFFSET 0 - #define SFP_EXT_CHECK_CODE_LEN 8 - #define SFP_EXT_CHECK_CODE_DEFAULT 0x0 - -struct sfp_ext { - a_uint8_t check_code:8; -}; - -union sfp_ext_u { - a_uint8_t val; - struct sfp_ext bf; -}; - -/*[register] SFP_DIAG_THRESHOLD*/ -#define SFP_DIAG_THRESHOLD -#define SFP_DIAG_THRESHOLD_ADDRESS 0x0 -#define SFP_DIAG_THRESHOLD_NUM 1 -#define SFP_DIAG_THRESHOLD_INC 0x28 -#define SFP_DIAG_THRESHOLD_TYPE REG_TYPE_RO -#define SFP_DIAG_THRESHOLD_DEFAULT 0x0 - /*[field] TEMP_HIGH_ALARM*/ - #define SFP_DIAG_THRESHOLD_TEMP_HIGH_ALARM - #define SFP_DIAG_THRESHOLD_TEMP_HIGH_ALARM_OFFSET 0 - #define SFP_DIAG_THRESHOLD_TEMP_HIGH_ALARM_LEN 16 - #define SFP_DIAG_THRESHOLD_TEMP_HIGH_ALARM_DEFAULT 0x0 - /*[field] TEMP_LOW_ALARM*/ - #define SFP_DIAG_THRESHOLD_TEMP_LOW_ALARM - #define SFP_DIAG_THRESHOLD_TEMP_LOW_ALARM_OFFSET 16 - #define SFP_DIAG_THRESHOLD_TEMP_LOW_ALARM_LEN 16 - #define SFP_DIAG_THRESHOLD_TEMP_LOW_ALARM_DEFAULT 0x0 - /*[field] TEMP_HIGH_WARNING*/ - #define SFP_DIAG_THRESHOLD_TEMP_HIGH_WARNING - #define SFP_DIAG_THRESHOLD_TEMP_HIGH_WARNING_OFFSET 32 - #define SFP_DIAG_THRESHOLD_TEMP_HIGH_WARNING_LEN 16 - #define SFP_DIAG_THRESHOLD_TEMP_HIGH_WARNING_DEFAULT 0x0 - /*[field] TEMP_LOW_WARNING*/ - #define SFP_DIAG_THRESHOLD_TEMP_LOW_WARNING - #define SFP_DIAG_THRESHOLD_TEMP_LOW_WARNING_OFFSET 48 - #define SFP_DIAG_THRESHOLD_TEMP_LOW_WARNING_LEN 16 - #define SFP_DIAG_THRESHOLD_TEMP_LOW_WARNING_DEFAULT 0x0 - /*[field] VOL_HIGH_ALARM*/ - #define SFP_DIAG_THRESHOLD_VOL_HIGH_ALARM - #define SFP_DIAG_THRESHOLD_VOL_HIGH_ALARM_OFFSET 64 - #define SFP_DIAG_THRESHOLD_VOL_HIGH_ALARM_LEN 16 - #define SFP_DIAG_THRESHOLD_VOL_HIGH_ALARM_DEFAULT 0x0 - /*[field] VOL_LOW_ALARM*/ - #define SFP_DIAG_THRESHOLD_VOL_LOW_ALARM - #define SFP_DIAG_THRESHOLD_VOL_LOW_ALARM_OFFSET 80 - #define SFP_DIAG_THRESHOLD_VOL_LOW_ALARM_LEN 16 - #define SFP_DIAG_THRESHOLD_VOL_LOW_ALARM_DEFAULT 0x0 - /*[field] VOL_HIGH_WARNING*/ - #define SFP_DIAG_THRESHOLD_VOL_HIGH_WARNING - #define SFP_DIAG_THRESHOLD_VOL_HIGH_WARNING_OFFSET 96 - #define SFP_DIAG_THRESHOLD_VOL_HIGH_WARNING_LEN 16 - #define SFP_DIAG_THRESHOLD_VOL_HIGH_WARNING_DEFAULT 0x0 - /*[field] VOL_LOW_WARNING*/ - #define SFP_DIAG_THRESHOLD_VOL_LOW_WARNING - #define SFP_DIAG_THRESHOLD_VOL_LOW_WARNING_OFFSET 112 - #define SFP_DIAG_THRESHOLD_VOL_LOW_WARNING_LEN 16 - #define SFP_DIAG_THRESHOLD_VOL_LOW_WARNING_DEFAULT 0x0 - /*[field] BIAS_HIGH_ALARM*/ - #define SFP_DIAG_THRESHOLD_BIAS_HIGH_ALARM - #define SFP_DIAG_THRESHOLD_BIAS_HIGH_ALARM_OFFSET 128 - #define SFP_DIAG_THRESHOLD_BIAS_HIGH_ALARM_LEN 16 - #define SFP_DIAG_THRESHOLD_BIAS_HIGH_ALARM_DEFAULT 0x0 - /*[field] BIAS_LOW_ALARM*/ - #define SFP_DIAG_THRESHOLD_BIAS_LOW_ALARM - #define SFP_DIAG_THRESHOLD_BIAS_LOW_ALARM_OFFSET 144 - #define SFP_DIAG_THRESHOLD_BIAS_LOW_ALARM_LEN 16 - #define SFP_DIAG_THRESHOLD_BIAS_LOW_ALARM_DEFAULT 0x0 - /*[field] BIAS_HIGH_WARNING*/ - #define SFP_DIAG_THRESHOLD_BIAS_HIGH_WARNING - #define SFP_DIAG_THRESHOLD_BIAS_HIGH_WARNING_OFFSET 160 - #define SFP_DIAG_THRESHOLD_BIAS_HIGH_WARNING_LEN 16 - #define SFP_DIAG_THRESHOLD_BIAS_HIGH_WARNING_DEFAULT 0x0 - /*[field] BIAS_LOW_WARNING*/ - #define SFP_DIAG_THRESHOLD_BIAS_LOW_WARNING - #define SFP_DIAG_THRESHOLD_BIAS_LOW_WARNING_OFFSET 176 - #define SFP_DIAG_THRESHOLD_BIAS_LOW_WARNING_LEN 16 - #define SFP_DIAG_THRESHOLD_BIAS_LOW_WARNING_DEFAULT 0x0 - /*[field] TX_PWR_HIGH_ALARM*/ - #define SFP_DIAG_THRESHOLD_TX_PWR_HIGH_ALARM - #define SFP_DIAG_THRESHOLD_TX_PWR_HIGH_ALARM_OFFSET 192 - #define SFP_DIAG_THRESHOLD_TX_PWR_HIGH_ALARM_LEN 16 - #define SFP_DIAG_THRESHOLD_TX_PWR_HIGH_ALARM_DEFAULT 0x0 - /*[field] TX_PWR_LOW_ALARM*/ - #define SFP_DIAG_THRESHOLD_TX_PWR_LOW_ALARM - #define SFP_DIAG_THRESHOLD_TX_PWR_LOW_ALARM_OFFSET 208 - #define SFP_DIAG_THRESHOLD_TX_PWR_LOW_ALARM_LEN 16 - #define SFP_DIAG_THRESHOLD_TX_PWR_LOW_ALARM_DEFAULT 0x0 - /*[field] TX_PWR_HIGH_WARNING*/ - #define SFP_DIAG_THRESHOLD_TX_PWR_HIGH_WARNING - #define SFP_DIAG_THRESHOLD_TX_PWR_HIGH_WARNING_OFFSET 224 - #define SFP_DIAG_THRESHOLD_TX_PWR_HIGH_WARNING_LEN 16 - #define SFP_DIAG_THRESHOLD_TX_PWR_HIGH_WARNING_DEFAULT 0x0 - /*[field] TX_PWR_LOW_WARNING*/ - #define SFP_DIAG_THRESHOLD_TX_PWR_LOW_WARNING - #define SFP_DIAG_THRESHOLD_TX_PWR_LOW_WARNING_OFFSET 240 - #define SFP_DIAG_THRESHOLD_TX_PWR_LOW_WARNING_LEN 16 - #define SFP_DIAG_THRESHOLD_TX_PWR_LOW_WARNING_DEFAULT 0x0 - /*[field] RX_PWR_HIGH_ALARM*/ - #define SFP_DIAG_THRESHOLD_RX_PWR_HIGH_ALARM - #define SFP_DIAG_THRESHOLD_RX_PWR_HIGH_ALARM_OFFSET 256 - #define SFP_DIAG_THRESHOLD_RX_PWR_HIGH_ALARM_LEN 16 - #define SFP_DIAG_THRESHOLD_RX_PWR_HIGH_ALARM_DEFAULT 0x0 - /*[field] RX_PWR_LOW_ALARM*/ - #define SFP_DIAG_THRESHOLD_RX_PWR_LOW_ALARM - #define SFP_DIAG_THRESHOLD_RX_PWR_LOW_ALARM_OFFSET 272 - #define SFP_DIAG_THRESHOLD_RX_PWR_LOW_ALARM_LEN 16 - #define SFP_DIAG_THRESHOLD_RX_PWR_LOW_ALARM_DEFAULT 0x0 - /*[field] RX_PWR_HIGH_WARNING*/ - #define SFP_DIAG_THRESHOLD_RX_PWR_HIGH_WARNING - #define SFP_DIAG_THRESHOLD_RX_PWR_HIGH_WARNING_OFFSET 288 - #define SFP_DIAG_THRESHOLD_RX_PWR_HIGH_WARNING_LEN 16 - #define SFP_DIAG_THRESHOLD_RX_PWR_HIGH_WARNING_DEFAULT 0x0 - /*[field] RX_PWR_LOW_WARNING*/ - #define SFP_DIAG_THRESHOLD_RX_PWR_LOW_WARNING - #define SFP_DIAG_THRESHOLD_RX_PWR_LOW_WARNING_OFFSET 304 - #define SFP_DIAG_THRESHOLD_RX_PWR_LOW_WARNING_LEN 16 - #define SFP_DIAG_THRESHOLD_RX_PWR_LOW_WARNING_DEFAULT 0x0 - -struct sfp_diag_threshold { - a_uint8_t temp_high_alarm_0:8; - a_uint8_t temp_high_alarm_1:8; - a_uint8_t temp_low_alarm_0:8; - a_uint8_t temp_low_alarm_1:8; - a_uint8_t temp_high_warning_0:8; - a_uint8_t temp_high_warning_1:8; - a_uint8_t temp_low_warning_0:8; - a_uint8_t temp_low_warning_1:8; - a_uint8_t vol_high_alarm_0:8; - a_uint8_t vol_high_alarm_1:8; - a_uint8_t vol_low_alarm_0:8; - a_uint8_t vol_low_alarm_1:8; - a_uint8_t vol_high_warning_0:8; - a_uint8_t vol_high_warning_1:8; - a_uint8_t vol_low_warning_0:8; - a_uint8_t vol_low_warning_1:8; - a_uint8_t bias_high_alarm_0:8; - a_uint8_t bias_high_alarm_1:8; - a_uint8_t bias_low_alarm_0:8; - a_uint8_t bias_low_alarm_1:8; - a_uint8_t bias_high_warning_0:8; - a_uint8_t bias_high_warning_1:8; - a_uint8_t bias_low_warning_0:8; - a_uint8_t bias_low_warning_1:8; - a_uint8_t tx_pwr_high_alarm_0:8; - a_uint8_t tx_pwr_high_alarm_1:8; - a_uint8_t tx_pwr_low_alarm_0:8; - a_uint8_t tx_pwr_low_alarm_1:8; - a_uint8_t tx_pwr_high_warning_0:8; - a_uint8_t tx_pwr_high_warning_1:8; - a_uint8_t tx_pwr_low_warning_0:8; - a_uint8_t tx_pwr_low_warning_1:8; - a_uint8_t rx_pwr_high_alarm_0:8; - a_uint8_t rx_pwr_high_alarm_1:8; - a_uint8_t rx_pwr_low_alarm_0:8; - a_uint8_t rx_pwr_low_alarm_1:8; - a_uint8_t rx_pwr_high_warning_0:8; - a_uint8_t rx_pwr_high_warning_1:8; - a_uint8_t rx_pwr_low_warning_0:8; - a_uint8_t rx_pwr_low_warning_1:8; -}; - -union sfp_diag_threshold_u { - a_uint8_t val[40]; - struct sfp_diag_threshold bf; -}; - -/*[register] SFP_DIAG_CAL_CONST*/ -#define SFP_DIAG_CAL_CONST -#define SFP_DIAG_CAL_CONST_ADDRESS 0x38 -#define SFP_DIAG_CAL_CONST_NUM 1 -#define SFP_DIAG_CAL_CONST_INC 0x24 -#define SFP_DIAG_CAL_CONST_TYPE REG_TYPE_RO -#define SFP_DIAG_CAL_CONST_DEFAULT 0x0 - /*[field] RX_PWR_4*/ - #define SFP_DIAG_CAL_CONST_RX_PWR_4 - #define SFP_DIAG_CAL_CONST_RX_PWR_4_OFFSET 0 - #define SFP_DIAG_CAL_CONST_RX_PWR_4_LEN 32 - #define SFP_DIAG_CAL_CONST_RX_PWR_4_DEFAULT 0x0 - /*[field] RX_PWR_3*/ - #define SFP_DIAG_CAL_CONST_RX_PWR_3 - #define SFP_DIAG_CAL_CONST_RX_PWR_3_OFFSET 32 - #define SFP_DIAG_CAL_CONST_RX_PWR_3_LEN 32 - #define SFP_DIAG_CAL_CONST_RX_PWR_3_DEFAULT 0x0 - /*[field] RX_PWR_2*/ - #define SFP_DIAG_CAL_CONST_RX_PWR_2 - #define SFP_DIAG_CAL_CONST_RX_PWR_2_OFFSET 64 - #define SFP_DIAG_CAL_CONST_RX_PWR_2_LEN 32 - #define SFP_DIAG_CAL_CONST_RX_PWR_2_DEFAULT 0x0 - /*[field] RX_PWR_1*/ - #define SFP_DIAG_CAL_CONST_RX_PWR_1 - #define SFP_DIAG_CAL_CONST_RX_PWR_1_OFFSET 96 - #define SFP_DIAG_CAL_CONST_RX_PWR_1_LEN 32 - #define SFP_DIAG_CAL_CONST_RX_PWR_1_DEFAULT 0x0 - /*[field] RX_PWR_0*/ - #define SFP_DIAG_CAL_CONST_RX_PWR_0 - #define SFP_DIAG_CAL_CONST_RX_PWR_0_OFFSET 128 - #define SFP_DIAG_CAL_CONST_RX_PWR_0_LEN 32 - #define SFP_DIAG_CAL_CONST_RX_PWR_0_DEFAULT 0x0 - /*[field] TX_I_SLOPE*/ - #define SFP_DIAG_CAL_CONST_TX_I_SLOPE - #define SFP_DIAG_CAL_CONST_TX_I_SLOPE_OFFSET 160 - #define SFP_DIAG_CAL_CONST_TX_I_SLOPE_LEN 16 - #define SFP_DIAG_CAL_CONST_TX_I_SLOPE_DEFAULT 0x0 - /*[field] TX_I_OFFSET*/ - #define SFP_DIAG_CAL_CONST_TX_I_OFFSET - #define SFP_DIAG_CAL_CONST_TX_I_OFFSET_OFFSET 176 - #define SFP_DIAG_CAL_CONST_TX_I_OFFSET_LEN 16 - #define SFP_DIAG_CAL_CONST_TX_I_OFFSET_DEFAULT 0x0 - /*[field] TX_PWR_SLOPE*/ - #define SFP_DIAG_CAL_CONST_TX_PWR_SLOPE - #define SFP_DIAG_CAL_CONST_TX_PWR_SLOPE_OFFSET 192 - #define SFP_DIAG_CAL_CONST_TX_PWR_SLOPE_LEN 16 - #define SFP_DIAG_CAL_CONST_TX_PWR_SLOPE_DEFAULT 0x0 - /*[field] TX_PWR_OFFSET*/ - #define SFP_DIAG_CAL_CONST_TX_PWR_OFFSET - #define SFP_DIAG_CAL_CONST_TX_PWR_OFFSET_OFFSET 208 - #define SFP_DIAG_CAL_CONST_TX_PWR_OFFSET_LEN 16 - #define SFP_DIAG_CAL_CONST_TX_PWR_OFFSET_DEFAULT 0x0 - /*[field] T_SLOPE*/ - #define SFP_DIAG_CAL_CONST_T_SLOPE - #define SFP_DIAG_CAL_CONST_T_SLOPE_OFFSET 224 - #define SFP_DIAG_CAL_CONST_T_SLOPE_LEN 16 - #define SFP_DIAG_CAL_CONST_T_SLOPE_DEFAULT 0x0 - /*[field] T_OFFSET*/ - #define SFP_DIAG_CAL_CONST_T_OFFSET - #define SFP_DIAG_CAL_CONST_T_OFFSET_OFFSET 240 - #define SFP_DIAG_CAL_CONST_T_OFFSET_LEN 16 - #define SFP_DIAG_CAL_CONST_T_OFFSET_DEFAULT 0x0 - /*[field] V_SLOPE*/ - #define SFP_DIAG_CAL_CONST_V_SLOPE - #define SFP_DIAG_CAL_CONST_V_SLOPE_OFFSET 256 - #define SFP_DIAG_CAL_CONST_V_SLOPE_LEN 16 - #define SFP_DIAG_CAL_CONST_V_SLOPE_DEFAULT 0x0 - /*[field] V_OFFSET*/ - #define SFP_DIAG_CAL_CONST_V_OFFSET - #define SFP_DIAG_CAL_CONST_V_OFFSET_OFFSET 272 - #define SFP_DIAG_CAL_CONST_V_OFFSET_LEN 16 - #define SFP_DIAG_CAL_CONST_V_OFFSET_DEFAULT 0x0 - -struct sfp_diag_cal_const { - a_uint8_t rx_pwr_4_0:8; - a_uint8_t rx_pwr_4_1:8; - a_uint8_t rx_pwr_4_2:8; - a_uint8_t rx_pwr_4_3:8; - a_uint8_t rx_pwr_3_0:8; - a_uint8_t rx_pwr_3_1:8; - a_uint8_t rx_pwr_3_2:8; - a_uint8_t rx_pwr_3_3:8; - a_uint8_t rx_pwr_2_0:8; - a_uint8_t rx_pwr_2_1:8; - a_uint8_t rx_pwr_2_2:8; - a_uint8_t rx_pwr_2_3:8; - a_uint8_t rx_pwr_1_0:8; - a_uint8_t rx_pwr_1_1:8; - a_uint8_t rx_pwr_1_2:8; - a_uint8_t rx_pwr_1_3:8; - a_uint8_t rx_pwr_0_0:8; - a_uint8_t rx_pwr_0_1:8; - a_uint8_t rx_pwr_0_2:8; - a_uint8_t rx_pwr_0_3:8; - a_uint8_t tx_i_slope_0:8; - a_uint8_t tx_i_slope_1:8; - a_uint8_t tx_i_offset_0:8; - a_uint8_t tx_i_offset_1:8; - a_uint8_t tx_pwr_slope_0:8; - a_uint8_t tx_pwr_slope_1:8; - a_uint8_t tx_pwr_offset_0:8; - a_uint8_t tx_pwr_offset_1:8; - a_uint8_t t_slope_0:8; - a_uint8_t t_slope_1:8; - a_uint8_t t_offset_0:8; - a_uint8_t t_offset_1:8; - a_uint8_t v_slope_0:8; - a_uint8_t v_slope_1:8; - a_uint8_t v_offset_0:8; - a_uint8_t v_offset_1:8; -}; - -union sfp_diag_cal_const_u { - a_uint8_t val[36]; - struct sfp_diag_cal_const bf; -}; - -/*[register] SFP_DIAG_DMI*/ -#define SFP_DIAG_DMI -#define SFP_DIAG_DMI_ADDRESS 0x5f -#define SFP_DIAG_DMI_NUM 1 -#define SFP_DIAG_DMI_INC 0x1 -#define SFP_DIAG_DMI_TYPE REG_TYPE_RO -#define SFP_DIAG_DMI_DEFAULT 0x0 - /*[field] CHECK_CODE*/ - #define SFP_DIAG_DMI_CHECK_CODE - #define SFP_DIAG_DMI_CHECK_CODE_OFFSET 0 - #define SFP_DIAG_DMI_CHECK_CODE_LEN 8 - #define SFP_DIAG_DMI_CHECK_CODE_DEFAULT 0x0 - -struct sfp_diag_dmi { - a_uint8_t check_code:8; -}; - -union sfp_diag_dmi_u { - a_uint8_t val; - struct sfp_diag_dmi bf; -}; - -/*[register] SFP_DIAG_REALTIME*/ -#define SFP_DIAG_REALTIME -#define SFP_DIAG_REALTIME_ADDRESS 0x60 -#define SFP_DIAG_REALTIME_NUM 1 -#define SFP_DIAG_REALTIME_INC 0xa -#define SFP_DIAG_REALTIME_TYPE REG_TYPE_RO -#define SFP_DIAG_REALTIME_DEFAULT 0x0 - /*[field] TMP*/ - #define SFP_DIAG_REALTIME_TMP - #define SFP_DIAG_REALTIME_TMP_OFFSET 0 - #define SFP_DIAG_REALTIME_TMP_LEN 16 - #define SFP_DIAG_REALTIME_TMP_DEFAULT 0x0 - /*[field] VCC*/ - #define SFP_DIAG_REALTIME_VCC - #define SFP_DIAG_REALTIME_VCC_OFFSET 16 - #define SFP_DIAG_REALTIME_VCC_LEN 16 - #define SFP_DIAG_REALTIME_VCC_DEFAULT 0x0 - /*[field] TX_BIAS*/ - #define SFP_DIAG_REALTIME_TX_BIAS - #define SFP_DIAG_REALTIME_TX_BIAS_OFFSET 32 - #define SFP_DIAG_REALTIME_TX_BIAS_LEN 16 - #define SFP_DIAG_REALTIME_TX_BIAS_DEFAULT 0x0 - /*[field] TX_PWR*/ - #define SFP_DIAG_REALTIME_TX_PWR - #define SFP_DIAG_REALTIME_TX_PWR_OFFSET 48 - #define SFP_DIAG_REALTIME_TX_PWR_LEN 16 - #define SFP_DIAG_REALTIME_TX_PWR_DEFAULT 0x0 - /*[field] RX_PWR*/ - #define SFP_DIAG_REALTIME_RX_PWR - #define SFP_DIAG_REALTIME_RX_PWR_OFFSET 64 - #define SFP_DIAG_REALTIME_RX_PWR_LEN 16 - #define SFP_DIAG_REALTIME_RX_PWR_DEFAULT 0x0 - -struct sfp_diag_realtime { - a_uint8_t tmp_0:8; - a_uint8_t tmp_1:8; - a_uint8_t vcc_0:8; - a_uint8_t vcc_1:8; - a_uint8_t tx_bias_0:8; - a_uint8_t tx_bias_1:8; - a_uint8_t tx_pwr_0:8; - a_uint8_t tx_pwr_1:8; - a_uint8_t rx_pwr_0:8; - a_uint8_t rx_pwr_1:8; -}; - -union sfp_diag_realtime_u { - a_uint8_t val[10]; - struct sfp_diag_realtime bf; -}; - -/*[register] SFP_DIAG_OPTIONAL_CTRL_STATUS*/ -#define SFP_DIAG_OPTIONAL_CTRL_STATUS -#define SFP_DIAG_OPTIONAL_CTRL_STATUS_ADDRESS 0x6e -#define SFP_DIAG_OPTIONAL_CTRL_STATUS_NUM 1 -#define SFP_DIAG_OPTIONAL_CTRL_STATUS_INC 0x2 -#define SFP_DIAG_OPTIONAL_CTRL_STATUS_TYPE REG_TYPE_RO -#define SFP_DIAG_OPTIONAL_CTRL_STATUS_DEFAULT 0x0 - /*[field] DATA_READY*/ - #define SFP_DIAG_OPTIONAL_CTRL_STATUS_DATA_READY - #define SFP_DIAG_OPTIONAL_CTRL_STATUS_DATA_READY_OFFSET 0 - #define SFP_DIAG_OPTIONAL_CTRL_STATUS_DATA_READY_LEN 1 - #define SFP_DIAG_OPTIONAL_CTRL_STATUS_DATA_READY_DEFAULT 0x0 - /*[field] RX_LOS*/ - #define SFP_DIAG_OPTIONAL_CTRL_STATUS_RX_LOS - #define SFP_DIAG_OPTIONAL_CTRL_STATUS_RX_LOS_OFFSET 1 - #define SFP_DIAG_OPTIONAL_CTRL_STATUS_RX_LOS_LEN 1 - #define SFP_DIAG_OPTIONAL_CTRL_STATUS_RX_LOS_DEFAULT 0x0 - /*[field] TX_FAULT*/ - #define SFP_DIAG_OPTIONAL_CTRL_STATUS_TX_FAULT - #define SFP_DIAG_OPTIONAL_CTRL_STATUS_TX_FAULT_OFFSET 2 - #define SFP_DIAG_OPTIONAL_CTRL_STATUS_TX_FAULT_LEN 1 - #define SFP_DIAG_OPTIONAL_CTRL_STATUS_TX_FAULT_DEFAULT 0x0 - /*[field] SOFT_RATE_SEL*/ - #define SFP_DIAG_OPTIONAL_CTRL_STATUS_SOFT_RATE_SEL - #define SFP_DIAG_OPTIONAL_CTRL_STATUS_SOFT_RATE_SEL_OFFSET 3 - #define SFP_DIAG_OPTIONAL_CTRL_STATUS_SOFT_RATE_SEL_LEN 1 - #define SFP_DIAG_OPTIONAL_CTRL_STATUS_SOFT_RATE_SEL_DEFAULT 0x0 - /*[field] RATE_SEL*/ - #define SFP_DIAG_OPTIONAL_CTRL_STATUS_RATE_SEL - #define SFP_DIAG_OPTIONAL_CTRL_STATUS_RATE_SEL_OFFSET 4 - #define SFP_DIAG_OPTIONAL_CTRL_STATUS_RATE_SEL_LEN 1 - #define SFP_DIAG_OPTIONAL_CTRL_STATUS_RATE_SEL_DEFAULT 0x0 - /*[field] RS*/ - #define SFP_DIAG_OPTIONAL_CTRL_STATUS_RS - #define SFP_DIAG_OPTIONAL_CTRL_STATUS_RS_OFFSET 5 - #define SFP_DIAG_OPTIONAL_CTRL_STATUS_RS_LEN 1 - #define SFP_DIAG_OPTIONAL_CTRL_STATUS_RS_DEFAULT 0x0 - /*[field] SOFT_TX_DISABLE_SEL*/ - #define SFP_DIAG_OPTIONAL_CTRL_STATUS_SOFT_TX_DISABLE_SEL - #define SFP_DIAG_OPTIONAL_CTRL_STATUS_SOFT_TX_DISABLE_SEL_OFFSET 6 - #define SFP_DIAG_OPTIONAL_CTRL_STATUS_SOFT_TX_DISABLE_SEL_LEN 1 - #define SFP_DIAG_OPTIONAL_CTRL_STATUS_SOFT_TX_DISABLE_SEL_DEFAULT 0x0 - /*[field] TX_DISABLE*/ - #define SFP_DIAG_OPTIONAL_CTRL_STATUS_TX_DISABLE - #define SFP_DIAG_OPTIONAL_CTRL_STATUS_TX_DISABLE_OFFSET 7 - #define SFP_DIAG_OPTIONAL_CTRL_STATUS_TX_DISABLE_LEN 1 - #define SFP_DIAG_OPTIONAL_CTRL_STATUS_TX_DISABLE_DEFAULT 0x0 - -struct sfp_diag_optional_ctrl_status { - a_uint8_t data_ready:1; - a_uint8_t rx_los:1; - a_uint8_t tx_fault:1; - a_uint8_t soft_rate_sel:1; - a_uint8_t rate_sel:1; - a_uint8_t rs:1; - a_uint8_t soft_tx_disable_sel:1; - a_uint8_t tx_disable:1; - a_uint8_t _reserved0:8; -}; - -union sfp_diag_optional_ctrl_status_u { - a_uint8_t val[2]; - struct sfp_diag_optional_ctrl_status bf; -}; - -/*[register] SFP_DIAG_FLAG*/ -#define SFP_DIAG_FLAG -#define SFP_DIAG_FLAG_ADDRESS 0x70 -#define SFP_DIAG_FLAG_NUM 1 -#define SFP_DIAG_FLAG_INC 0x6 -#define SFP_DIAG_FLAG_TYPE REG_TYPE_RO -#define SFP_DIAG_FLAG_DEFAULT 0x0 - /*[field] TX_PWR_LOW_ALARM*/ - #define SFP_DIAG_FLAG_TX_PWR_LOW_ALARM - #define SFP_DIAG_FLAG_TX_PWR_LOW_ALARM_OFFSET 0 - #define SFP_DIAG_FLAG_TX_PWR_LOW_ALARM_LEN 1 - #define SFP_DIAG_FLAG_TX_PWR_LOW_ALARM_DEFAULT 0x0 - /*[field] TX_PWR_HIGH_ALARM*/ - #define SFP_DIAG_FLAG_TX_PWR_HIGH_ALARM - #define SFP_DIAG_FLAG_TX_PWR_HIGH_ALARM_OFFSET 1 - #define SFP_DIAG_FLAG_TX_PWR_HIGH_ALARM_LEN 1 - #define SFP_DIAG_FLAG_TX_PWR_HIGH_ALARM_DEFAULT 0x0 - /*[field] TX_BIAS_LOW_ALARM*/ - #define SFP_DIAG_FLAG_TX_BIAS_LOW_ALARM - #define SFP_DIAG_FLAG_TX_BIAS_LOW_ALARM_OFFSET 2 - #define SFP_DIAG_FLAG_TX_BIAS_LOW_ALARM_LEN 1 - #define SFP_DIAG_FLAG_TX_BIAS_LOW_ALARM_DEFAULT 0x0 - /*[field] TX_BIAS_HIGH_ALARM*/ - #define SFP_DIAG_FLAG_TX_BIAS_HIGH_ALARM - #define SFP_DIAG_FLAG_TX_BIAS_HIGH_ALARM_OFFSET 3 - #define SFP_DIAG_FLAG_TX_BIAS_HIGH_ALARM_LEN 1 - #define SFP_DIAG_FLAG_TX_BIAS_HIGH_ALARM_DEFAULT 0x0 - /*[field] VCC_LOW_ALARM*/ - #define SFP_DIAG_FLAG_VCC_LOW_ALARM - #define SFP_DIAG_FLAG_VCC_LOW_ALARM_OFFSET 4 - #define SFP_DIAG_FLAG_VCC_LOW_ALARM_LEN 1 - #define SFP_DIAG_FLAG_VCC_LOW_ALARM_DEFAULT 0x0 - /*[field] VCC_HIGH_ALARM*/ - #define SFP_DIAG_FLAG_VCC_HIGH_ALARM - #define SFP_DIAG_FLAG_VCC_HIGH_ALARM_OFFSET 5 - #define SFP_DIAG_FLAG_VCC_HIGH_ALARM_LEN 1 - #define SFP_DIAG_FLAG_VCC_HIGH_ALARM_DEFAULT 0x0 - /*[field] TMP_LOW_ALARM*/ - #define SFP_DIAG_FLAG_TMP_LOW_ALARM - #define SFP_DIAG_FLAG_TMP_LOW_ALARM_OFFSET 6 - #define SFP_DIAG_FLAG_TMP_LOW_ALARM_LEN 1 - #define SFP_DIAG_FLAG_TMP_LOW_ALARM_DEFAULT 0x0 - /*[field] TMP_HIGH_ALARM*/ - #define SFP_DIAG_FLAG_TMP_HIGH_ALARM - #define SFP_DIAG_FLAG_TMP_HIGH_ALARM_OFFSET 7 - #define SFP_DIAG_FLAG_TMP_HIGH_ALARM_LEN 1 - #define SFP_DIAG_FLAG_TMP_HIGH_ALARM_DEFAULT 0x0 - /*[field] RX_PWR_LOW_ALARM*/ - #define SFP_DIAG_FLAG_RX_PWR_LOW_ALARM - #define SFP_DIAG_FLAG_RX_PWR_LOW_ALARM_OFFSET 14 - #define SFP_DIAG_FLAG_RX_PWR_LOW_ALARM_LEN 1 - #define SFP_DIAG_FLAG_RX_PWR_LOW_ALARM_DEFAULT 0x0 - /*[field] RX_PWR_HIGH_ALARM*/ - #define SFP_DIAG_FLAG_RX_PWR_HIGH_ALARM - #define SFP_DIAG_FLAG_RX_PWR_HIGH_ALARM_OFFSET 15 - #define SFP_DIAG_FLAG_RX_PWR_HIGH_ALARM_LEN 1 - #define SFP_DIAG_FLAG_RX_PWR_HIGH_ALARM_DEFAULT 0x0 - /*[field] UNALLOCATED*/ - #define SFP_DIAG_FLAG_UNALLOCATED - #define SFP_DIAG_FLAG_UNALLOCATED_OFFSET 16 - #define SFP_DIAG_FLAG_UNALLOCATED_LEN 16 - #define SFP_DIAG_FLAG_UNALLOCATED_DEFAULT 0x0 - /*[field] TX_PWR_LOW_WARNING*/ - #define SFP_DIAG_FLAG_TX_PWR_LOW_WARNING - #define SFP_DIAG_FLAG_TX_PWR_LOW_WARNING_OFFSET 32 - #define SFP_DIAG_FLAG_TX_PWR_LOW_WARNING_LEN 1 - #define SFP_DIAG_FLAG_TX_PWR_LOW_WARNING_DEFAULT 0x0 - /*[field] TX_PWR_HIGH_WARNING*/ - #define SFP_DIAG_FLAG_TX_PWR_HIGH_WARNING - #define SFP_DIAG_FLAG_TX_PWR_HIGH_WARNING_OFFSET 33 - #define SFP_DIAG_FLAG_TX_PWR_HIGH_WARNING_LEN 1 - #define SFP_DIAG_FLAG_TX_PWR_HIGH_WARNING_DEFAULT 0x0 - /*[field] TX_BIAS_LOW_WARNING*/ - #define SFP_DIAG_FLAG_TX_BIAS_LOW_WARNING - #define SFP_DIAG_FLAG_TX_BIAS_LOW_WARNING_OFFSET 34 - #define SFP_DIAG_FLAG_TX_BIAS_LOW_WARNING_LEN 1 - #define SFP_DIAG_FLAG_TX_BIAS_LOW_WARNING_DEFAULT 0x0 - /*[field] TX_BIAS_HIGH_WARNING*/ - #define SFP_DIAG_FLAG_TX_BIAS_HIGH_WARNING - #define SFP_DIAG_FLAG_TX_BIAS_HIGH_WARNING_OFFSET 35 - #define SFP_DIAG_FLAG_TX_BIAS_HIGH_WARNING_LEN 1 - #define SFP_DIAG_FLAG_TX_BIAS_HIGH_WARNING_DEFAULT 0x0 - /*[field] VCC_LOW_WARNING*/ - #define SFP_DIAG_FLAG_VCC_LOW_WARNING - #define SFP_DIAG_FLAG_VCC_LOW_WARNING_OFFSET 36 - #define SFP_DIAG_FLAG_VCC_LOW_WARNING_LEN 1 - #define SFP_DIAG_FLAG_VCC_LOW_WARNING_DEFAULT 0x0 - /*[field] VCC_HIGH_WARNING*/ - #define SFP_DIAG_FLAG_VCC_HIGH_WARNING - #define SFP_DIAG_FLAG_VCC_HIGH_WARNING_OFFSET 37 - #define SFP_DIAG_FLAG_VCC_HIGH_WARNING_LEN 1 - #define SFP_DIAG_FLAG_VCC_HIGH_WARNING_DEFAULT 0x0 - /*[field] TMP_LOW_WARNING*/ - #define SFP_DIAG_FLAG_TMP_LOW_WARNING - #define SFP_DIAG_FLAG_TMP_LOW_WARNING_OFFSET 38 - #define SFP_DIAG_FLAG_TMP_LOW_WARNING_LEN 1 - #define SFP_DIAG_FLAG_TMP_LOW_WARNING_DEFAULT 0x0 - /*[field] TMP_HIGH_WARNING*/ - #define SFP_DIAG_FLAG_TMP_HIGH_WARNING - #define SFP_DIAG_FLAG_TMP_HIGH_WARNING_OFFSET 39 - #define SFP_DIAG_FLAG_TMP_HIGH_WARNING_LEN 1 - #define SFP_DIAG_FLAG_TMP_HIGH_WARNING_DEFAULT 0x0 - /*[field] RX_PWR_LOW_WARNING*/ - #define SFP_DIAG_FLAG_RX_PWR_LOW_WARNING - #define SFP_DIAG_FLAG_RX_PWR_LOW_WARNING_OFFSET 46 - #define SFP_DIAG_FLAG_RX_PWR_LOW_WARNING_LEN 1 - #define SFP_DIAG_FLAG_RX_PWR_LOW_WARNING_DEFAULT 0x0 - /*[field] RX_PWR_HIGH_WARNING*/ - #define SFP_DIAG_FLAG_RX_PWR_HIGH_WARNING - #define SFP_DIAG_FLAG_RX_PWR_HIGH_WARNING_OFFSET 47 - #define SFP_DIAG_FLAG_RX_PWR_HIGH_WARNING_LEN 1 - #define SFP_DIAG_FLAG_RX_PWR_HIGH_WARNING_DEFAULT 0x0 - -struct sfp_diag_flag { - a_uint8_t tx_pwr_low_alarm:1; - a_uint8_t tx_pwr_high_alarm:1; - a_uint8_t tx_bias_low_alarm:1; - a_uint8_t tx_bias_high_alarm:1; - a_uint8_t vcc_low_alarm:1; - a_uint8_t vcc_high_alarm:1; - a_uint8_t tmp_low_alarm:1; - a_uint8_t tmp_high_alarm:1; - a_uint8_t _reserved0:6; - a_uint8_t rx_pwr_low_alarm:1; - a_uint8_t rx_pwr_high_alarm:1; - a_uint8_t unallocated_0:8; - a_uint8_t unallocated_1:8; - a_uint8_t tx_pwr_low_warning:1; - a_uint8_t tx_pwr_high_warning:1; - a_uint8_t tx_bias_low_warning:1; - a_uint8_t tx_bias_high_warning:1; - a_uint8_t vcc_low_warning:1; - a_uint8_t vcc_high_warning:1; - a_uint8_t tmp_low_warning:1; - a_uint8_t tmp_high_warning:1; - a_uint8_t _reserved1:6; - a_uint8_t rx_pwr_low_warning:1; - a_uint8_t rx_pwr_high_warning:1; -}; - -union sfp_diag_flag_u { - a_uint8_t val[6]; - struct sfp_diag_flag bf; -}; - -/*[register] SFP_DIAG_EXTENDED_CTRL_STATUS*/ -#define SFP_DIAG_EXTENDED_CTRL_STATUS -#define SFP_DIAG_EXTENDED_CTRL_STATUS_ADDRESS 0x76 -#define SFP_DIAG_EXTENDED_CTRL_STATUS_NUM 1 -#define SFP_DIAG_EXTENDED_CTRL_STATUS_INC 0x2 -#define SFP_DIAG_EXTENDED_CTRL_STATUS_TYPE REG_TYPE_RO -#define SFP_DIAG_EXTENDED_CTRL_STATUS_DEFAULT 0x0 - /*[field] PWR_LEVEL_SEL*/ - #define SFP_DIAG_EXTENDED_CTRL_STATUS_PWR_LEVEL_SEL - #define SFP_DIAG_EXTENDED_CTRL_STATUS_PWR_LEVEL_SEL_OFFSET 0 - #define SFP_DIAG_EXTENDED_CTRL_STATUS_PWR_LEVEL_SEL_LEN 1 - #define SFP_DIAG_EXTENDED_CTRL_STATUS_PWR_LEVEL_SEL_DEFAULT 0x0 - /*[field] PWR_LEVEL_OP_STATE*/ - #define SFP_DIAG_EXTENDED_CTRL_STATUS_PWR_LEVEL_OP_STATE - #define SFP_DIAG_EXTENDED_CTRL_STATUS_PWR_LEVEL_OP_STATE_OFFSET 1 - #define SFP_DIAG_EXTENDED_CTRL_STATUS_PWR_LEVEL_OP_STATE_LEN 1 - #define SFP_DIAG_EXTENDED_CTRL_STATUS_PWR_LEVEL_OP_STATE_DEFAULT 0x0 - /*[field] SOFT_RS_SEL*/ - #define SFP_DIAG_EXTENDED_CTRL_STATUS_SOFT_RS_SEL - #define SFP_DIAG_EXTENDED_CTRL_STATUS_SOFT_RS_SEL_OFFSET 3 - #define SFP_DIAG_EXTENDED_CTRL_STATUS_SOFT_RS_SEL_LEN 1 - #define SFP_DIAG_EXTENDED_CTRL_STATUS_SOFT_RS_SEL_DEFAULT 0x0 - /*[field] UNALLOCATED*/ - #define SFP_DIAG_EXTENDED_CTRL_STATUS_UNALLOCATED - #define SFP_DIAG_EXTENDED_CTRL_STATUS_UNALLOCATED_OFFSET 4 - #define SFP_DIAG_EXTENDED_CTRL_STATUS_UNALLOCATED_LEN 12 - #define SFP_DIAG_EXTENDED_CTRL_STATUS_UNALLOCATED_DEFAULT 0x0 - -struct sfp_diag_extended_ctrl_status { - a_uint8_t pwr_level_sel:1; - a_uint8_t pwr_level_op_state:1; - a_uint8_t _reserved0:1; - a_uint8_t soft_rs_sel:1; - a_uint8_t unallocated_0:4; - a_uint8_t unallocated_1:8; -}; - -union sfp_diag_extended_ctrl_status_u { - a_uint8_t val[2]; - struct sfp_diag_extended_ctrl_status bf; -}; - -#endif diff --git a/feeds/ipq807x/qca-ssdk/src/include/hsl/shiva/shiva_acl.h b/feeds/ipq807x/qca-ssdk/src/include/hsl/shiva/shiva_acl.h deleted file mode 100755 index 7ad6d9540..000000000 --- a/feeds/ipq807x/qca-ssdk/src/include/hsl/shiva/shiva_acl.h +++ /dev/null @@ -1,114 +0,0 @@ -/* - * Copyright (c) 2012, The Linux Foundation. All rights reserved. - * Permission to use, copy, modify, and/or distribute this software for - * any purpose with or without fee is hereby granted, provided that the - * above copyright notice and this permission notice appear in all copies. - * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES - * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR - * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES - * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN - * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT - * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. - */ - - -/** - * @defgroup shiva_acl SHIVA_ACL - * @{ - */ -#ifndef _SHIVA_ACL_H_ -#define _SHIVA_ACL_H_ - -#ifdef __cplusplus -extern "C" { -#endif /* __cplusplus */ - -#include "fal/fal_acl.h" - - sw_error_t - shiva_acl_init(a_uint32_t dev_id); - - sw_error_t - shiva_acl_reset(a_uint32_t dev_id); - -#ifdef IN_ACL -#define SHIVA_ACL_INIT(rv, dev_id) \ - { \ - rv = shiva_acl_init(dev_id); \ - SW_RTN_ON_ERROR(rv); \ - } - -#define SHIVA_ACL_RESET(rv, dev_id) \ - { \ - rv = shiva_acl_reset(dev_id); \ - SW_RTN_ON_ERROR(rv); \ - } -#else -#define SHIVA_ACL_INIT(rv, dev_id) -#define SHIVA_ACL_RESET(rv, dev_id) -#endif - -#ifdef HSL_STANDALONG - - HSL_LOCAL sw_error_t - shiva_acl_list_creat(a_uint32_t dev_id, a_uint32_t list_id, - a_uint32_t list_pri); - - - HSL_LOCAL sw_error_t - shiva_acl_list_destroy(a_uint32_t dev_id, a_uint32_t list_id); - - - HSL_LOCAL sw_error_t - shiva_acl_rule_add(a_uint32_t dev_id, a_uint32_t list_id, - a_uint32_t rule_id, a_uint32_t rule_nr, - fal_acl_rule_t * rule); - - - HSL_LOCAL sw_error_t - shiva_acl_rule_delete(a_uint32_t dev_id, a_uint32_t list_id, - a_uint32_t rule_id, a_uint32_t rule_nr); - - - HSL_LOCAL sw_error_t - shiva_acl_rule_query(a_uint32_t dev_id, a_uint32_t list_id, - a_uint32_t rule_id, fal_acl_rule_t * rule); - - - HSL_LOCAL sw_error_t - shiva_acl_list_bind(a_uint32_t dev_id, a_uint32_t list_id, - fal_acl_direc_t direc, fal_acl_bind_obj_t obj_t, - a_uint32_t obj_idx); - - - HSL_LOCAL sw_error_t - shiva_acl_list_unbind(a_uint32_t dev_id, a_uint32_t list_id, - fal_acl_direc_t direc, fal_acl_bind_obj_t obj_t, - a_uint32_t obj_idx); - - - HSL_LOCAL sw_error_t - shiva_acl_status_set(a_uint32_t dev_id, a_bool_t enable); - - - HSL_LOCAL sw_error_t - shiva_acl_status_get(a_uint32_t dev_id, a_bool_t * enable); - - - HSL_LOCAL sw_error_t - shiva_acl_list_dump(a_uint32_t dev_id); - - - HSL_LOCAL sw_error_t - shiva_acl_rule_dump(a_uint32_t dev_id); - -#endif - -#ifdef __cplusplus -} -#endif /* __cplusplus */ -#endif /* _SHIVA_ACL_H_ */ -/** - * @} - */ diff --git a/feeds/ipq807x/qca-ssdk/src/include/hsl/shiva/shiva_api.h b/feeds/ipq807x/qca-ssdk/src/include/hsl/shiva/shiva_api.h deleted file mode 100755 index cdc428d7d..000000000 --- a/feeds/ipq807x/qca-ssdk/src/include/hsl/shiva/shiva_api.h +++ /dev/null @@ -1,609 +0,0 @@ -/* - * Copyright (c) 2012, The Linux Foundation. All rights reserved. - * Permission to use, copy, modify, and/or distribute this software for - * any purpose with or without fee is hereby granted, provided that the - * above copyright notice and this permission notice appear in all copies. - * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES - * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR - * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES - * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN - * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT - * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. - */ - - - -#ifndef _SHIVA_API_H_ -#define _SHIVA_API_H_ - -#ifdef __cplusplus -extern "C" { -#endif /* __cplusplus */ - -#ifdef IN_PORTCONTROL -#define PORTCONTROL_API \ - SW_API_DEF(SW_API_PT_DUPLEX_GET, shiva_port_duplex_get), \ - SW_API_DEF(SW_API_PT_DUPLEX_SET, shiva_port_duplex_set), \ - SW_API_DEF(SW_API_PT_SPEED_GET, shiva_port_speed_get), \ - SW_API_DEF(SW_API_PT_SPEED_SET, shiva_port_speed_set), \ - SW_API_DEF(SW_API_PT_AN_GET, shiva_port_autoneg_status_get), \ - SW_API_DEF(SW_API_PT_AN_ENABLE, shiva_port_autoneg_enable), \ - SW_API_DEF(SW_API_PT_AN_RESTART, shiva_port_autoneg_restart), \ - SW_API_DEF(SW_API_PT_AN_ADV_GET, shiva_port_autoneg_adv_get), \ - SW_API_DEF(SW_API_PT_AN_ADV_SET, shiva_port_autoneg_adv_set), \ - SW_API_DEF(SW_API_PT_HDR_SET, shiva_port_hdr_status_set), \ - SW_API_DEF(SW_API_PT_HDR_GET, shiva_port_hdr_status_get), \ - SW_API_DEF(SW_API_PT_FLOWCTRL_SET, shiva_port_flowctrl_set), \ - SW_API_DEF(SW_API_PT_FLOWCTRL_GET, shiva_port_flowctrl_get), \ - SW_API_DEF(SW_API_PT_FLOWCTRL_MODE_SET, shiva_port_flowctrl_forcemode_set), \ - SW_API_DEF(SW_API_PT_FLOWCTRL_MODE_GET, shiva_port_flowctrl_forcemode_get), \ - SW_API_DEF(SW_API_PT_POWERSAVE_SET, shiva_port_powersave_set), \ - SW_API_DEF(SW_API_PT_POWERSAVE_GET, shiva_port_powersave_get), \ - SW_API_DEF(SW_API_PT_HIBERNATE_SET, shiva_port_hibernate_set), \ - SW_API_DEF(SW_API_PT_HIBERNATE_GET, shiva_port_hibernate_get), \ - SW_API_DEF(SW_API_PT_CDT, shiva_port_cdt), - - -#define PORTCONTROL_API_PARAM \ - SW_API_DESC(SW_API_PT_DUPLEX_GET) \ - SW_API_DESC(SW_API_PT_DUPLEX_SET) \ - SW_API_DESC(SW_API_PT_SPEED_GET) \ - SW_API_DESC(SW_API_PT_SPEED_SET) \ - SW_API_DESC(SW_API_PT_AN_GET) \ - SW_API_DESC(SW_API_PT_AN_ENABLE) \ - SW_API_DESC(SW_API_PT_AN_RESTART) \ - SW_API_DESC(SW_API_PT_AN_ADV_GET) \ - SW_API_DESC(SW_API_PT_AN_ADV_SET) \ - SW_API_DESC(SW_API_PT_HDR_SET) \ - SW_API_DESC(SW_API_PT_HDR_GET) \ - SW_API_DESC(SW_API_PT_FLOWCTRL_SET) \ - SW_API_DESC(SW_API_PT_FLOWCTRL_GET) \ - SW_API_DESC(SW_API_PT_FLOWCTRL_MODE_SET) \ - SW_API_DESC(SW_API_PT_FLOWCTRL_MODE_GET) \ - SW_API_DESC(SW_API_PT_POWERSAVE_SET) \ - SW_API_DESC(SW_API_PT_POWERSAVE_GET) \ - SW_API_DESC(SW_API_PT_HIBERNATE_SET) \ - SW_API_DESC(SW_API_PT_HIBERNATE_GET) \ - SW_API_DESC(SW_API_PT_CDT) - -#else -#define PORTCONTROL_API -#define PORTCONTROL_API_PARAM -#endif - -#ifdef IN_VLAN -#define VLAN_API \ - SW_API_DEF(SW_API_VLAN_ADD, shiva_vlan_create), \ - SW_API_DEF(SW_API_VLAN_DEL, shiva_vlan_delete), \ - SW_API_DEF(SW_API_VLAN_MEM_UPDATE, shiva_vlan_member_update), \ - SW_API_DEF(SW_API_VLAN_FIND, shiva_vlan_find), \ - SW_API_DEF(SW_API_VLAN_NEXT, shiva_vlan_next), \ - SW_API_DEF(SW_API_VLAN_APPEND, shiva_vlan_entry_append), \ - SW_API_DEF(SW_API_VLAN_FLUSH, shiva_vlan_flush), - -#define VLAN_API_PARAM \ - SW_API_DESC(SW_API_VLAN_ADD) \ - SW_API_DESC(SW_API_VLAN_DEL) \ - SW_API_DESC(SW_API_VLAN_MEM_UPDATE) \ - SW_API_DESC(SW_API_VLAN_FIND) \ - SW_API_DESC(SW_API_VLAN_NEXT) \ - SW_API_DESC(SW_API_VLAN_APPEND) \ - SW_API_DESC(SW_API_VLAN_FLUSH) -#else -#define VLAN_API -#define VLAN_API_PARAM -#endif - -#ifdef IN_PORTVLAN -#define PORTVLAN_API \ - SW_API_DEF(SW_API_PT_ING_MODE_GET, shiva_port_1qmode_get), \ - SW_API_DEF(SW_API_PT_ING_MODE_SET, shiva_port_1qmode_set), \ - SW_API_DEF(SW_API_PT_EG_MODE_GET, shiva_port_egvlanmode_get), \ - SW_API_DEF(SW_API_PT_EG_MODE_SET, shiva_port_egvlanmode_set), \ - SW_API_DEF(SW_API_PT_VLAN_MEM_ADD, shiva_portvlan_member_add), \ - SW_API_DEF(SW_API_PT_VLAN_MEM_DEL, shiva_portvlan_member_del), \ - SW_API_DEF(SW_API_PT_VLAN_MEM_UPDATE, shiva_portvlan_member_update), \ - SW_API_DEF(SW_API_PT_VLAN_MEM_GET, shiva_portvlan_member_get), \ - SW_API_DEF(SW_API_PT_FORCE_DEF_VID_SET, shiva_port_force_default_vid_set), \ - SW_API_DEF(SW_API_PT_FORCE_DEF_VID_GET, shiva_port_force_default_vid_get), \ - SW_API_DEF(SW_API_PT_FORCE_PORTVLAN_SET, shiva_port_force_portvlan_set), \ - SW_API_DEF(SW_API_PT_FORCE_PORTVLAN_GET, shiva_port_force_portvlan_get), \ - SW_API_DEF(SW_API_NESTVLAN_TPID_SET, shiva_nestvlan_tpid_set), \ - SW_API_DEF(SW_API_NESTVLAN_TPID_GET, shiva_nestvlan_tpid_get), \ - SW_API_DEF(SW_API_PT_IN_VLAN_MODE_SET, shiva_port_invlan_mode_set), \ - SW_API_DEF(SW_API_PT_IN_VLAN_MODE_GET, shiva_port_invlan_mode_get), \ - SW_API_DEF(SW_API_PT_TLS_SET, shiva_port_tls_set), \ - SW_API_DEF(SW_API_PT_TLS_GET, shiva_port_tls_get), \ - SW_API_DEF(SW_API_PT_PRI_PROPAGATION_SET, shiva_port_pri_propagation_set), \ - SW_API_DEF(SW_API_PT_PRI_PROPAGATION_GET, shiva_port_pri_propagation_get), \ - SW_API_DEF(SW_API_PT_DEF_SVID_SET, shiva_port_default_svid_set), \ - SW_API_DEF(SW_API_PT_DEF_SVID_GET, shiva_port_default_svid_get), \ - SW_API_DEF(SW_API_PT_DEF_CVID_SET, shiva_port_default_cvid_set), \ - SW_API_DEF(SW_API_PT_DEF_CVID_GET, shiva_port_default_cvid_get), \ - SW_API_DEF(SW_API_PT_VLAN_PROPAGATION_SET, shiva_port_vlan_propagation_set), \ - SW_API_DEF(SW_API_PT_VLAN_PROPAGATION_GET, shiva_port_vlan_propagation_get), \ - SW_API_DEF(SW_API_PT_VLAN_TRANS_ADD, shiva_port_vlan_trans_add), \ - SW_API_DEF(SW_API_PT_VLAN_TRANS_DEL, shiva_port_vlan_trans_del), \ - SW_API_DEF(SW_API_PT_VLAN_TRANS_GET, shiva_port_vlan_trans_get), \ - SW_API_DEF(SW_API_QINQ_MODE_SET, shiva_qinq_mode_set), \ - SW_API_DEF(SW_API_QINQ_MODE_GET, shiva_qinq_mode_get), \ - SW_API_DEF(SW_API_PT_QINQ_ROLE_SET, shiva_port_qinq_role_set), \ - SW_API_DEF(SW_API_PT_QINQ_ROLE_GET, shiva_port_qinq_role_get), \ - SW_API_DEF(SW_API_PT_VLAN_TRANS_ITERATE, shiva_port_vlan_trans_iterate), - -#define PORTVLAN_API_PARAM \ - SW_API_DESC(SW_API_PT_ING_MODE_GET) \ - SW_API_DESC(SW_API_PT_ING_MODE_SET) \ - SW_API_DESC(SW_API_PT_EG_MODE_GET) \ - SW_API_DESC(SW_API_PT_EG_MODE_SET) \ - SW_API_DESC(SW_API_PT_VLAN_MEM_ADD) \ - SW_API_DESC(SW_API_PT_VLAN_MEM_DEL) \ - SW_API_DESC(SW_API_PT_VLAN_MEM_UPDATE) \ - SW_API_DESC(SW_API_PT_VLAN_MEM_GET) \ - SW_API_DESC(SW_API_PT_FORCE_DEF_VID_SET) \ - SW_API_DESC(SW_API_PT_FORCE_DEF_VID_GET) \ - SW_API_DESC(SW_API_PT_FORCE_PORTVLAN_SET) \ - SW_API_DESC(SW_API_PT_FORCE_PORTVLAN_GET) \ - SW_API_DESC(SW_API_NESTVLAN_TPID_SET) \ - SW_API_DESC(SW_API_NESTVLAN_TPID_GET) \ - SW_API_DESC(SW_API_PT_IN_VLAN_MODE_SET) \ - SW_API_DESC(SW_API_PT_IN_VLAN_MODE_GET) \ - SW_API_DESC(SW_API_PT_TLS_SET) \ - SW_API_DESC(SW_API_PT_TLS_GET) \ - SW_API_DESC(SW_API_PT_PRI_PROPAGATION_SET) \ - SW_API_DESC(SW_API_PT_PRI_PROPAGATION_GET) \ - SW_API_DESC(SW_API_PT_DEF_SVID_SET) \ - SW_API_DESC(SW_API_PT_DEF_SVID_GET) \ - SW_API_DESC(SW_API_PT_DEF_CVID_SET) \ - SW_API_DESC(SW_API_PT_DEF_CVID_GET) \ - SW_API_DESC(SW_API_PT_VLAN_PROPAGATION_SET) \ - SW_API_DESC(SW_API_PT_VLAN_PROPAGATION_GET) \ - SW_API_DESC(SW_API_PT_VLAN_TRANS_ADD) \ - SW_API_DESC(SW_API_PT_VLAN_TRANS_DEL) \ - SW_API_DESC(SW_API_PT_VLAN_TRANS_GET) \ - SW_API_DESC(SW_API_QINQ_MODE_SET) \ - SW_API_DESC(SW_API_QINQ_MODE_GET) \ - SW_API_DESC(SW_API_PT_QINQ_ROLE_SET) \ - SW_API_DESC(SW_API_PT_QINQ_ROLE_GET) \ - SW_API_DESC(SW_API_PT_VLAN_TRANS_ITERATE) -#else -#define PORTVLAN_API -#define PORTVLAN_API_PARAM -#endif - -#ifdef IN_FDB -#define FDB_API \ - SW_API_DEF(SW_API_FDB_ADD, shiva_fdb_add), \ - SW_API_DEF(SW_API_FDB_DELALL, shiva_fdb_del_all), \ - SW_API_DEF(SW_API_FDB_DELPORT,shiva_fdb_del_by_port), \ - SW_API_DEF(SW_API_FDB_DELMAC, shiva_fdb_del_by_mac), \ - SW_API_DEF(SW_API_FDB_FIRST, shiva_fdb_first), \ - SW_API_DEF(SW_API_FDB_FIND, shiva_fdb_find), \ - SW_API_DEF(SW_API_FDB_PT_LEARN_SET, shiva_fdb_port_learn_set), \ - SW_API_DEF(SW_API_FDB_PT_LEARN_GET, shiva_fdb_port_learn_get), \ - SW_API_DEF(SW_API_FDB_AGE_CTRL_SET, shiva_fdb_age_ctrl_set), \ - SW_API_DEF(SW_API_FDB_AGE_CTRL_GET, shiva_fdb_age_ctrl_get), \ - SW_API_DEF(SW_API_FDB_AGE_TIME_SET, shiva_fdb_age_time_set), \ - SW_API_DEF(SW_API_FDB_AGE_TIME_GET, shiva_fdb_age_time_get), \ - SW_API_DEF(SW_API_FDB_ITERATE, shiva_fdb_iterate), - -#define FDB_API_PARAM \ - SW_API_DESC(SW_API_FDB_ADD) \ - SW_API_DESC(SW_API_FDB_DELALL) \ - SW_API_DESC(SW_API_FDB_DELPORT) \ - SW_API_DESC(SW_API_FDB_DELMAC) \ - SW_API_DESC(SW_API_FDB_FIRST) \ - SW_API_DESC(SW_API_FDB_FIND) \ - SW_API_DESC(SW_API_FDB_PT_LEARN_SET) \ - SW_API_DESC(SW_API_FDB_PT_LEARN_GET) \ - SW_API_DESC(SW_API_FDB_AGE_CTRL_SET) \ - SW_API_DESC(SW_API_FDB_AGE_CTRL_GET) \ - SW_API_DESC(SW_API_FDB_AGE_TIME_SET) \ - SW_API_DESC(SW_API_FDB_AGE_TIME_GET) \ - SW_API_DESC(SW_API_FDB_ITERATE) -#else -#define FDB_API -#define FDB_API_PARAM -#endif - -#ifdef IN_ACL -#define ACL_API \ - SW_API_DEF(SW_API_ACL_LIST_CREAT, shiva_acl_list_creat), \ - SW_API_DEF(SW_API_ACL_LIST_DESTROY, shiva_acl_list_destroy), \ - SW_API_DEF(SW_API_ACL_RULE_ADD, shiva_acl_rule_add), \ - SW_API_DEF(SW_API_ACL_RULE_DELETE, shiva_acl_rule_delete), \ - SW_API_DEF(SW_API_ACL_RULE_QUERY, shiva_acl_rule_query), \ - SW_API_DEF(SW_API_ACL_LIST_BIND, shiva_acl_list_bind), \ - SW_API_DEF(SW_API_ACL_LIST_UNBIND, shiva_acl_list_unbind), \ - SW_API_DEF(SW_API_ACL_STATUS_SET, shiva_acl_status_set), \ - SW_API_DEF(SW_API_ACL_STATUS_GET, shiva_acl_status_get), \ - SW_API_DEF(SW_API_ACL_LIST_DUMP, shiva_acl_list_dump), \ - SW_API_DEF(SW_API_ACL_RULE_DUMP, shiva_acl_rule_dump), - -#define ACL_API_PARAM \ - SW_API_DESC(SW_API_ACL_LIST_CREAT) \ - SW_API_DESC(SW_API_ACL_LIST_DESTROY) \ - SW_API_DESC(SW_API_ACL_RULE_ADD) \ - SW_API_DESC(SW_API_ACL_RULE_DELETE) \ - SW_API_DESC(SW_API_ACL_RULE_QUERY) \ - SW_API_DESC(SW_API_ACL_LIST_BIND) \ - SW_API_DESC(SW_API_ACL_LIST_UNBIND) \ - SW_API_DESC(SW_API_ACL_STATUS_SET) \ - SW_API_DESC(SW_API_ACL_STATUS_GET) \ - SW_API_DESC(SW_API_ACL_LIST_DUMP) \ - SW_API_DESC(SW_API_ACL_RULE_DUMP) -#else -#define ACL_API -#define ACL_API_PARAM -#endif - -#ifdef IN_QOS -#define QOS_API \ - SW_API_DEF(SW_API_QOS_QU_TX_BUF_ST_SET, shiva_qos_queue_tx_buf_status_set), \ - SW_API_DEF(SW_API_QOS_QU_TX_BUF_ST_GET, shiva_qos_queue_tx_buf_status_get), \ - SW_API_DEF(SW_API_QOS_QU_TX_BUF_NR_SET, shiva_qos_queue_tx_buf_nr_set), \ - SW_API_DEF(SW_API_QOS_QU_TX_BUF_NR_GET, shiva_qos_queue_tx_buf_nr_get), \ - SW_API_DEF(SW_API_QOS_PT_TX_BUF_ST_SET, shiva_qos_port_tx_buf_status_set), \ - SW_API_DEF(SW_API_QOS_PT_TX_BUF_ST_GET, shiva_qos_port_tx_buf_status_get), \ - SW_API_DEF(SW_API_QOS_PT_TX_BUF_NR_SET, shiva_qos_port_tx_buf_nr_set), \ - SW_API_DEF(SW_API_QOS_PT_TX_BUF_NR_GET, shiva_qos_port_tx_buf_nr_get), \ - SW_API_DEF(SW_API_QOS_PT_RX_BUF_NR_SET, shiva_qos_port_rx_buf_nr_set), \ - SW_API_DEF(SW_API_QOS_PT_RX_BUF_NR_GET, shiva_qos_port_rx_buf_nr_get), \ - SW_API_DEF(SW_API_COSMAP_UP_QU_SET, shiva_cosmap_up_queue_set), \ - SW_API_DEF(SW_API_COSMAP_UP_QU_GET, shiva_cosmap_up_queue_get), \ - SW_API_DEF(SW_API_COSMAP_DSCP_QU_SET, shiva_cosmap_dscp_queue_set), \ - SW_API_DEF(SW_API_COSMAP_DSCP_QU_GET, shiva_cosmap_dscp_queue_get), \ - SW_API_DEF(SW_API_QOS_PT_MODE_SET, shiva_qos_port_mode_set), \ - SW_API_DEF(SW_API_QOS_PT_MODE_GET, shiva_qos_port_mode_get), \ - SW_API_DEF(SW_API_QOS_PT_MODE_PRI_SET, shiva_qos_port_mode_pri_set), \ - SW_API_DEF(SW_API_QOS_PT_MODE_PRI_GET, shiva_qos_port_mode_pri_get), \ - SW_API_DEF(SW_API_QOS_PORT_DEF_UP_SET, shiva_qos_port_default_up_set), \ - SW_API_DEF(SW_API_QOS_PORT_DEF_UP_GET, shiva_qos_port_default_up_get), \ - SW_API_DEF(SW_API_QOS_PORT_SCH_MODE_SET, shiva_qos_port_sch_mode_set), \ - SW_API_DEF(SW_API_QOS_PORT_SCH_MODE_GET, shiva_qos_port_sch_mode_get), - -#define QOS_API_PARAM \ - SW_API_DESC(SW_API_QOS_QU_TX_BUF_ST_SET) \ - SW_API_DESC(SW_API_QOS_QU_TX_BUF_ST_GET) \ - SW_API_DESC(SW_API_QOS_QU_TX_BUF_NR_SET) \ - SW_API_DESC(SW_API_QOS_QU_TX_BUF_NR_GET) \ - SW_API_DESC(SW_API_QOS_PT_TX_BUF_ST_SET) \ - SW_API_DESC(SW_API_QOS_PT_TX_BUF_ST_GET) \ - SW_API_DESC(SW_API_QOS_PT_TX_BUF_NR_SET) \ - SW_API_DESC(SW_API_QOS_PT_TX_BUF_NR_GET) \ - SW_API_DESC(SW_API_QOS_PT_RX_BUF_NR_SET) \ - SW_API_DESC(SW_API_QOS_PT_RX_BUF_NR_GET) \ - SW_API_DESC(SW_API_COSMAP_UP_QU_SET) \ - SW_API_DESC(SW_API_COSMAP_UP_QU_GET) \ - SW_API_DESC(SW_API_COSMAP_DSCP_QU_SET) \ - SW_API_DESC(SW_API_COSMAP_DSCP_QU_GET) \ - SW_API_DESC(SW_API_QOS_PT_MODE_SET) \ - SW_API_DESC(SW_API_QOS_PT_MODE_GET) \ - SW_API_DESC(SW_API_QOS_PT_MODE_PRI_SET) \ - SW_API_DESC(SW_API_QOS_PT_MODE_PRI_GET) \ - SW_API_DESC(SW_API_QOS_PORT_DEF_UP_SET) \ - SW_API_DESC(SW_API_QOS_PORT_DEF_UP_GET) \ - SW_API_DESC(SW_API_QOS_PORT_SCH_MODE_SET) \ - SW_API_DESC(SW_API_QOS_PORT_SCH_MODE_GET) -#else -#define QOS_API -#define QOS_API_PARAM -#endif - -#ifdef IN_IGMP -#define IGMP_API \ - SW_API_DEF(SW_API_PT_IGMPS_MODE_SET, shiva_port_igmps_status_set), \ - SW_API_DEF(SW_API_PT_IGMPS_MODE_GET, shiva_port_igmps_status_get), \ - SW_API_DEF(SW_API_IGMP_MLD_CMD_SET, shiva_igmp_mld_cmd_set), \ - SW_API_DEF(SW_API_IGMP_MLD_CMD_GET, shiva_igmp_mld_cmd_get), \ - SW_API_DEF(SW_API_IGMP_PT_JOIN_SET, shiva_port_igmp_mld_join_set), \ - SW_API_DEF(SW_API_IGMP_PT_JOIN_GET, shiva_port_igmp_mld_join_get), \ - SW_API_DEF(SW_API_IGMP_PT_LEAVE_SET, shiva_port_igmp_mld_leave_set), \ - SW_API_DEF(SW_API_IGMP_PT_LEAVE_GET, shiva_port_igmp_mld_leave_get), \ - SW_API_DEF(SW_API_IGMP_RP_SET, shiva_igmp_mld_rp_set), \ - SW_API_DEF(SW_API_IGMP_RP_GET, shiva_igmp_mld_rp_get), \ - SW_API_DEF(SW_API_IGMP_ENTRY_CREAT_SET, shiva_igmp_mld_entry_creat_set), \ - SW_API_DEF(SW_API_IGMP_ENTRY_CREAT_GET, shiva_igmp_mld_entry_creat_get), \ - SW_API_DEF(SW_API_IGMP_ENTRY_STATIC_SET, shiva_igmp_mld_entry_static_set), \ - SW_API_DEF(SW_API_IGMP_ENTRY_STATIC_GET, shiva_igmp_mld_entry_static_get), \ - SW_API_DEF(SW_API_IGMP_ENTRY_LEAKY_SET, shiva_igmp_mld_entry_leaky_set), \ - SW_API_DEF(SW_API_IGMP_ENTRY_LEAKY_GET, shiva_igmp_mld_entry_leaky_get), \ - SW_API_DEF(SW_API_IGMP_ENTRY_V3_SET, shiva_igmp_mld_entry_v3_set), \ - SW_API_DEF(SW_API_IGMP_ENTRY_V3_GET, shiva_igmp_mld_entry_v3_get), \ - SW_API_DEF(SW_API_IGMP_ENTRY_QUEUE_SET, shiva_igmp_mld_entry_queue_set), \ - SW_API_DEF(SW_API_IGMP_ENTRY_QUEUE_GET, shiva_igmp_mld_entry_queue_get), - -#define IGMP_API_PARAM \ - SW_API_DESC(SW_API_PT_IGMPS_MODE_SET) \ - SW_API_DESC(SW_API_PT_IGMPS_MODE_GET) \ - SW_API_DESC(SW_API_IGMP_MLD_CMD_SET) \ - SW_API_DESC(SW_API_IGMP_MLD_CMD_GET) \ - SW_API_DESC(SW_API_IGMP_PT_JOIN_SET) \ - SW_API_DESC(SW_API_IGMP_PT_JOIN_GET) \ - SW_API_DESC(SW_API_IGMP_PT_LEAVE_SET) \ - SW_API_DESC(SW_API_IGMP_PT_LEAVE_GET) \ - SW_API_DESC(SW_API_IGMP_RP_SET) \ - SW_API_DESC(SW_API_IGMP_RP_GET) \ - SW_API_DESC(SW_API_IGMP_ENTRY_CREAT_SET) \ - SW_API_DESC(SW_API_IGMP_ENTRY_CREAT_GET) \ - SW_API_DESC(SW_API_IGMP_ENTRY_STATIC_SET) \ - SW_API_DESC(SW_API_IGMP_ENTRY_STATIC_GET) \ - SW_API_DESC(SW_API_IGMP_ENTRY_LEAKY_SET) \ - SW_API_DESC(SW_API_IGMP_ENTRY_LEAKY_GET) \ - SW_API_DESC(SW_API_IGMP_ENTRY_V3_SET) \ - SW_API_DESC(SW_API_IGMP_ENTRY_V3_GET) \ - SW_API_DESC(SW_API_IGMP_ENTRY_QUEUE_SET) \ - SW_API_DESC(SW_API_IGMP_ENTRY_QUEUE_GET) -#else -#define IGMP_API -#define IGMP_API_PARAM -#endif - -#ifdef IN_LEAKY -#define LEAKY_API \ - SW_API_DEF(SW_API_UC_LEAKY_MODE_SET, shiva_uc_leaky_mode_set), \ - SW_API_DEF(SW_API_UC_LEAKY_MODE_GET, shiva_uc_leaky_mode_get), \ - SW_API_DEF(SW_API_MC_LEAKY_MODE_SET, shiva_mc_leaky_mode_set), \ - SW_API_DEF(SW_API_MC_LEAKY_MODE_GET, shiva_mc_leaky_mode_get), \ - SW_API_DEF(SW_API_ARP_LEAKY_MODE_SET, shiva_port_arp_leaky_set), \ - SW_API_DEF(SW_API_ARP_LEAKY_MODE_GET, shiva_port_arp_leaky_get), \ - SW_API_DEF(SW_API_PT_UC_LEAKY_MODE_SET, shiva_port_uc_leaky_set), \ - SW_API_DEF(SW_API_PT_UC_LEAKY_MODE_GET, shiva_port_uc_leaky_get), \ - SW_API_DEF(SW_API_PT_MC_LEAKY_MODE_SET, shiva_port_mc_leaky_set), \ - SW_API_DEF(SW_API_PT_MC_LEAKY_MODE_GET, shiva_port_mc_leaky_get), - -#define LEAKY_API_PARAM \ - SW_API_DESC(SW_API_UC_LEAKY_MODE_SET) \ - SW_API_DESC(SW_API_UC_LEAKY_MODE_GET) \ - SW_API_DESC(SW_API_MC_LEAKY_MODE_SET) \ - SW_API_DESC(SW_API_MC_LEAKY_MODE_GET) \ - SW_API_DESC(SW_API_ARP_LEAKY_MODE_SET) \ - SW_API_DESC(SW_API_ARP_LEAKY_MODE_GET) \ - SW_API_DESC(SW_API_PT_UC_LEAKY_MODE_SET) \ - SW_API_DESC(SW_API_PT_UC_LEAKY_MODE_GET) \ - SW_API_DESC(SW_API_PT_MC_LEAKY_MODE_SET) \ - SW_API_DESC(SW_API_PT_MC_LEAKY_MODE_GET) -#else -#define LEAKY_API -#define LEAKY_API_PARAM -#endif - -#ifdef IN_MIRROR -#define MIRROR_API \ - SW_API_DEF(SW_API_MIRROR_ANALY_PT_SET, shiva_mirr_analysis_port_set), \ - SW_API_DEF(SW_API_MIRROR_ANALY_PT_GET, shiva_mirr_analysis_port_get), \ - SW_API_DEF(SW_API_MIRROR_IN_PT_SET, shiva_mirr_port_in_set), \ - SW_API_DEF(SW_API_MIRROR_IN_PT_GET, shiva_mirr_port_in_get), \ - SW_API_DEF(SW_API_MIRROR_EG_PT_SET, shiva_mirr_port_eg_set), \ - SW_API_DEF(SW_API_MIRROR_EG_PT_GET, shiva_mirr_port_eg_get), - -#define MIRROR_API_PARAM \ - SW_API_DESC(SW_API_MIRROR_ANALY_PT_SET) \ - SW_API_DESC(SW_API_MIRROR_ANALY_PT_GET) \ - SW_API_DESC(SW_API_MIRROR_IN_PT_SET) \ - SW_API_DESC(SW_API_MIRROR_IN_PT_GET) \ - SW_API_DESC(SW_API_MIRROR_EG_PT_SET) \ - SW_API_DESC(SW_API_MIRROR_EG_PT_GET) -#else -#define MIRROR_API -#define MIRROR_API_PARAM -#endif - -#ifdef IN_RATE -#define RATE_API \ - SW_API_DEF(SW_API_RATE_QU_EGRL_SET, shiva_rate_queue_egrl_set), \ - SW_API_DEF(SW_API_RATE_QU_EGRL_GET, shiva_rate_queue_egrl_get), \ - SW_API_DEF(SW_API_RATE_PT_EGRL_SET, shiva_rate_port_egrl_set), \ - SW_API_DEF(SW_API_RATE_PT_EGRL_GET, shiva_rate_port_egrl_get), \ - SW_API_DEF(SW_API_RATE_PT_INRL_SET, shiva_rate_port_inrl_set), \ - SW_API_DEF(SW_API_RATE_PT_INRL_GET, shiva_rate_port_inrl_get), \ - SW_API_DEF(SW_API_STORM_CTRL_FRAME_SET, shiva_storm_ctrl_frame_set), \ - SW_API_DEF(SW_API_STORM_CTRL_FRAME_GET, shiva_storm_ctrl_frame_get), \ - SW_API_DEF(SW_API_STORM_CTRL_RATE_SET, shiva_storm_ctrl_rate_set), \ - SW_API_DEF(SW_API_STORM_CTRL_RATE_GET, shiva_storm_ctrl_rate_get), - -#define RATE_API_PARAM \ - SW_API_DESC(SW_API_RATE_QU_EGRL_SET) \ - SW_API_DESC(SW_API_RATE_QU_EGRL_GET) \ - SW_API_DESC(SW_API_RATE_PT_EGRL_SET) \ - SW_API_DESC(SW_API_RATE_PT_EGRL_GET) \ - SW_API_DESC(SW_API_RATE_PT_INRL_SET) \ - SW_API_DESC(SW_API_RATE_PT_INRL_GET) \ - SW_API_DESC(SW_API_STORM_CTRL_FRAME_SET) \ - SW_API_DESC(SW_API_STORM_CTRL_FRAME_GET) \ - SW_API_DESC(SW_API_STORM_CTRL_RATE_SET) \ - SW_API_DESC(SW_API_STORM_CTRL_RATE_GET) -#else -#define RATE_API -#define RATE_API_PARAM -#endif - -#ifdef IN_STP -#define STP_API \ - SW_API_DEF(SW_API_STP_PT_STATE_SET, shiva_stp_port_state_set), \ - SW_API_DEF(SW_API_STP_PT_STATE_GET, shiva_stp_port_state_get), - -#define STP_API_PARAM \ - SW_API_DESC(SW_API_STP_PT_STATE_SET) \ - SW_API_DESC(SW_API_STP_PT_STATE_GET) -#else -#define STP_API -#define STP_API_PARAM -#endif - -#ifdef IN_MIB -#define MIB_API \ - SW_API_DEF(SW_API_PT_MIB_GET, shiva_get_mib_info), \ - SW_API_DEF(SW_API_MIB_STATUS_SET, shiva_mib_status_set), \ - SW_API_DEF(SW_API_MIB_STATUS_GET, shiva_mib_status_get), - -#define MIB_API_PARAM \ - SW_API_DESC(SW_API_PT_MIB_GET) \ - SW_API_DESC(SW_API_MIB_STATUS_SET) \ - SW_API_DESC(SW_API_MIB_STATUS_GET) -#else -#define MIB_API -#define MIB_API_PARAM -#endif - -#ifdef IN_MISC -#define MISC_API \ - SW_API_DEF(SW_API_ARP_STATUS_SET, shiva_arp_status_set), \ - SW_API_DEF(SW_API_ARP_STATUS_GET, shiva_arp_status_get), \ - SW_API_DEF(SW_API_FRAME_MAX_SIZE_SET, shiva_frame_max_size_set), \ - SW_API_DEF(SW_API_FRAME_MAX_SIZE_GET, shiva_frame_max_size_get), \ - SW_API_DEF(SW_API_PT_UNK_SA_CMD_SET, shiva_port_unk_sa_cmd_set), \ - SW_API_DEF(SW_API_PT_UNK_SA_CMD_GET, shiva_port_unk_sa_cmd_get), \ - SW_API_DEF(SW_API_PT_UNK_UC_FILTER_SET, shiva_port_unk_uc_filter_set), \ - SW_API_DEF(SW_API_PT_UNK_UC_FILTER_GET, shiva_port_unk_uc_filter_get), \ - SW_API_DEF(SW_API_PT_UNK_MC_FILTER_SET, shiva_port_unk_mc_filter_set), \ - SW_API_DEF(SW_API_PT_UNK_MC_FILTER_GET, shiva_port_unk_mc_filter_get), \ - SW_API_DEF(SW_API_PT_BC_FILTER_SET, shiva_port_bc_filter_set), \ - SW_API_DEF(SW_API_PT_BC_FILTER_GET, shiva_port_bc_filter_get), \ - SW_API_DEF(SW_API_CPU_PORT_STATUS_SET, shiva_cpu_port_status_set), \ - SW_API_DEF(SW_API_CPU_PORT_STATUS_GET, shiva_cpu_port_status_get), \ - SW_API_DEF(SW_API_PPPOE_CMD_SET, shiva_pppoe_cmd_set), \ - SW_API_DEF(SW_API_PPPOE_CMD_GET, shiva_pppoe_cmd_get), \ - SW_API_DEF(SW_API_PPPOE_STATUS_SET, shiva_pppoe_status_set), \ - SW_API_DEF(SW_API_PPPOE_STATUS_GET, shiva_pppoe_status_get), \ - SW_API_DEF(SW_API_PT_DHCP_SET, shiva_port_dhcp_set), \ - SW_API_DEF(SW_API_PT_DHCP_GET, shiva_port_dhcp_get), \ - SW_API_DEF(SW_API_ARP_CMD_SET, shiva_arp_cmd_set), \ - SW_API_DEF(SW_API_ARP_CMD_GET, shiva_arp_cmd_get), \ - SW_API_DEF(SW_API_EAPOL_CMD_SET, shiva_eapol_cmd_set), \ - SW_API_DEF(SW_API_EAPOL_CMD_GET, shiva_eapol_cmd_get), \ - SW_API_DEF(SW_API_PPPOE_SESSION_ADD, shiva_pppoe_session_add), \ - SW_API_DEF(SW_API_PPPOE_SESSION_DEL, shiva_pppoe_session_del), \ - SW_API_DEF(SW_API_PPPOE_SESSION_GET, shiva_pppoe_session_get), \ - SW_API_DEF(SW_API_EAPOL_STATUS_SET, shiva_eapol_status_set), \ - SW_API_DEF(SW_API_EAPOL_STATUS_GET, shiva_eapol_status_get), \ - SW_API_DEF(SW_API_RIPV1_STATUS_SET, shiva_ripv1_status_set), \ - SW_API_DEF(SW_API_RIPV1_STATUS_GET, shiva_ripv1_status_get), - -#define MISC_API_PARAM \ - SW_API_DESC(SW_API_ARP_STATUS_SET) \ - SW_API_DESC(SW_API_ARP_STATUS_GET) \ - SW_API_DESC(SW_API_FRAME_MAX_SIZE_SET) \ - SW_API_DESC(SW_API_FRAME_MAX_SIZE_GET) \ - SW_API_DESC(SW_API_PT_UNK_SA_CMD_SET) \ - SW_API_DESC(SW_API_PT_UNK_SA_CMD_GET) \ - SW_API_DESC(SW_API_PT_UNK_UC_FILTER_SET) \ - SW_API_DESC(SW_API_PT_UNK_UC_FILTER_GET) \ - SW_API_DESC(SW_API_PT_UNK_MC_FILTER_SET) \ - SW_API_DESC(SW_API_PT_UNK_MC_FILTER_GET) \ - SW_API_DESC(SW_API_PT_BC_FILTER_SET) \ - SW_API_DESC(SW_API_PT_BC_FILTER_GET) \ - SW_API_DESC(SW_API_CPU_PORT_STATUS_SET) \ - SW_API_DESC(SW_API_CPU_PORT_STATUS_GET) \ - SW_API_DESC(SW_API_PPPOE_CMD_SET) \ - SW_API_DESC(SW_API_PPPOE_CMD_GET) \ - SW_API_DESC(SW_API_PPPOE_STATUS_SET) \ - SW_API_DESC(SW_API_PPPOE_STATUS_GET) \ - SW_API_DESC(SW_API_PT_DHCP_SET) \ - SW_API_DESC(SW_API_PT_DHCP_GET) \ - SW_API_DESC(SW_API_ARP_CMD_SET) \ - SW_API_DESC(SW_API_ARP_CMD_GET) \ - SW_API_DESC(SW_API_EAPOL_CMD_SET) \ - SW_API_DESC(SW_API_EAPOL_CMD_GET) \ - SW_API_DESC(SW_API_PPPOE_SESSION_ADD) \ - SW_API_DESC(SW_API_PPPOE_SESSION_DEL) \ - SW_API_DESC(SW_API_PPPOE_SESSION_GET) \ - SW_API_DESC(SW_API_EAPOL_STATUS_SET) \ - SW_API_DESC(SW_API_EAPOL_STATUS_GET) \ - SW_API_DESC(SW_API_RIPV1_STATUS_SET) \ - SW_API_DESC(SW_API_RIPV1_STATUS_GET) -#else -#define MISC_API -#define MISC_API_PARAM -#endif - -#ifdef IN_LED -#define LED_API \ - SW_API_DEF(SW_API_LED_PATTERN_SET, shiva_led_ctrl_pattern_set), \ - SW_API_DEF(SW_API_LED_PATTERN_GET, shiva_led_ctrl_pattern_get), - -#define LED_API_PARAM \ - SW_API_DESC(SW_API_LED_PATTERN_SET) \ - SW_API_DESC(SW_API_LED_PATTERN_GET) -#else -#define LED_API -#define LED_API_PARAM -#endif - -#define REG_API \ - SW_API_DEF(SW_API_PHY_GET, shiva_phy_get), \ - SW_API_DEF(SW_API_PHY_SET, shiva_phy_set), \ - SW_API_DEF(SW_API_REG_GET, shiva_reg_get), \ - SW_API_DEF(SW_API_REG_SET, shiva_reg_set), \ - SW_API_DEF(SW_API_REG_FIELD_GET, shiva_reg_field_get), \ - SW_API_DEF(SW_API_REG_FIELD_SET, shiva_reg_field_set), - -#define REG_API_PARAM \ - SW_API_DESC(SW_API_PHY_GET) \ - SW_API_DESC(SW_API_PHY_SET) \ - SW_API_DESC(SW_API_REG_GET) \ - SW_API_DESC(SW_API_REG_SET) \ - SW_API_DESC(SW_API_REG_FIELD_GET) \ - SW_API_DESC(SW_API_REG_FIELD_SET) - -#define SSDK_API \ - SW_API_DEF(SW_API_SWITCH_RESET, shiva_reset), \ - SW_API_DEF(SW_API_SSDK_CFG, hsl_ssdk_cfg), \ - PORTCONTROL_API \ - VLAN_API \ - PORTVLAN_API \ - FDB_API \ - ACL_API \ - QOS_API \ - IGMP_API \ - LEAKY_API \ - MIRROR_API \ - RATE_API \ - STP_API \ - MIB_API \ - MISC_API \ - LED_API \ - REG_API \ - SW_API_DEF(SW_API_MAX, NULL), - - -#define SSDK_PARAM \ - SW_PARAM_DEF(SW_API_SWITCH_RESET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \ - SW_PARAM_DEF(SW_API_SSDK_CFG, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \ - SW_PARAM_DEF(SW_API_SSDK_CFG, SW_SSDK_CFG, sizeof(ssdk_cfg_t), SW_PARAM_PTR|SW_PARAM_OUT, "ssdk configuration"), \ - MIB_API_PARAM \ - LEAKY_API_PARAM \ - MISC_API_PARAM \ - IGMP_API_PARAM \ - MIRROR_API_PARAM \ - PORTCONTROL_API_PARAM \ - PORTVLAN_API_PARAM \ - VLAN_API_PARAM \ - FDB_API_PARAM \ - QOS_API_PARAM \ - RATE_API_PARAM \ - STP_API_PARAM \ - ACL_API_PARAM \ - LED_API_PARAM \ - REG_API_PARAM \ - SW_PARAM_DEF(SW_API_MAX, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), - -#if (defined(USER_MODE) && defined(KERNEL_MODULE)) -#undef SSDK_API -#undef SSDK_PARAM - -#define SSDK_API \ - REG_API \ - SW_API_DEF(SW_API_MAX, NULL), - -#define SSDK_PARAM \ - REG_API_PARAM \ - SW_PARAM_DEF(SW_API_MAX, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), -#endif - -#ifdef __cplusplus -} -#endif /* __cplusplus */ - -#endif /* _SHIVA_API_H_ */ diff --git a/feeds/ipq807x/qca-ssdk/src/include/hsl/shiva/shiva_fdb.h b/feeds/ipq807x/qca-ssdk/src/include/hsl/shiva/shiva_fdb.h deleted file mode 100755 index f5e450e17..000000000 --- a/feeds/ipq807x/qca-ssdk/src/include/hsl/shiva/shiva_fdb.h +++ /dev/null @@ -1,109 +0,0 @@ -/* - * Copyright (c) 2012, The Linux Foundation. All rights reserved. - * Permission to use, copy, modify, and/or distribute this software for - * any purpose with or without fee is hereby granted, provided that the - * above copyright notice and this permission notice appear in all copies. - * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES - * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR - * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES - * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN - * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT - * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. - */ - - -/** - * @defgroup shiva_fdb SHIVA_FDB - * @{ - */ -#ifndef _SHIVA_FDB_H_ -#define _SHIVA_FDB_H_ - -#ifdef __cplusplus -extern "C" { -#endif /* __cplusplus */ - -#include "fal/fal_fdb.h" - - sw_error_t - shiva_fdb_init(a_uint32_t dev_id); - -#ifdef IN_FDB -#define SHIVA_FDB_INIT(rv, dev_id) \ - { \ - rv = shiva_fdb_init(dev_id); \ - SW_RTN_ON_ERROR(rv); \ - } -#else -#define SHIVA_FDB_INIT(rv, dev_id) -#endif - -#ifdef HSL_STANDALONG - - - HSL_LOCAL sw_error_t - shiva_fdb_add(a_uint32_t dev_id, const fal_fdb_entry_t * entry); - - - HSL_LOCAL sw_error_t - shiva_fdb_del_all(a_uint32_t dev_id, a_uint32_t flag); - - - HSL_LOCAL sw_error_t - shiva_fdb_del_by_port(a_uint32_t dev_id, a_uint32_t port_id, a_uint32_t flag); - - - HSL_LOCAL sw_error_t - shiva_fdb_del_by_mac(a_uint32_t dev_id, - const fal_fdb_entry_t *entry); - - - HSL_LOCAL sw_error_t - shiva_fdb_first(a_uint32_t dev_id, fal_fdb_entry_t * entry); - - - HSL_LOCAL sw_error_t - shiva_fdb_find(a_uint32_t dev_id, fal_fdb_entry_t * entry); - - - HSL_LOCAL sw_error_t - shiva_fdb_port_learn_set(a_uint32_t dev_id, fal_port_t port_id, - a_bool_t enable); - - - HSL_LOCAL sw_error_t - shiva_fdb_port_learn_get(a_uint32_t dev_id, fal_port_t port_id, - a_bool_t *enable); - - - HSL_LOCAL sw_error_t - shiva_fdb_age_ctrl_set(a_uint32_t dev_id, a_bool_t enable); - - - HSL_LOCAL sw_error_t - shiva_fdb_age_ctrl_get(a_uint32_t dev_id, a_bool_t *enable); - - - HSL_LOCAL sw_error_t - shiva_fdb_age_time_set(a_uint32_t dev_id, a_uint32_t * time); - - - HSL_LOCAL sw_error_t - shiva_fdb_age_time_get(a_uint32_t dev_id, a_uint32_t * time); - - - HSL_LOCAL sw_error_t - shiva_fdb_iterate(a_uint32_t dev_id, a_uint32_t * iterator, fal_fdb_entry_t * entry); - - -#endif - -#ifdef __cplusplus -} -#endif /* __cplusplus */ - -#endif /* _SHIVA_FDB_H_ */ -/** - * @} - */ diff --git a/feeds/ipq807x/qca-ssdk/src/include/hsl/shiva/shiva_igmp.h b/feeds/ipq807x/qca-ssdk/src/include/hsl/shiva/shiva_igmp.h deleted file mode 100755 index cfae2f764..000000000 --- a/feeds/ipq807x/qca-ssdk/src/include/hsl/shiva/shiva_igmp.h +++ /dev/null @@ -1,133 +0,0 @@ -/* - * Copyright (c) 2012, The Linux Foundation. All rights reserved. - * Permission to use, copy, modify, and/or distribute this software for - * any purpose with or without fee is hereby granted, provided that the - * above copyright notice and this permission notice appear in all copies. - * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES - * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR - * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES - * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN - * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT - * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. - */ - - -/** - * @defgroup shiva_igmp SHIVA_IGMP - * @{ - */ -#ifndef _SHIVA_IGMP_H_ -#define _SHIVA_IGMP_H_ - -#ifdef __cplusplus -extern "C" { -#endif /* __cplusplus */ - -#include "fal/fal_igmp.h" - - sw_error_t - shiva_igmp_init(a_uint32_t dev_id); - -#ifdef IN_IGMP -#define SHIVA_IGMP_INIT(rv, dev_id) \ - { \ - rv = shiva_igmp_init(dev_id); \ - SW_RTN_ON_ERROR(rv); \ - } -#else -#define SHIVA_IGMP_INIT(rv, dev_id) -#endif - -#ifdef HSL_STANDALONG - - HSL_LOCAL sw_error_t - shiva_port_igmps_status_set(a_uint32_t dev_id, fal_port_t port_id, a_bool_t enable); - - - HSL_LOCAL sw_error_t - shiva_port_igmps_status_get(a_uint32_t dev_id, fal_port_t port_id, a_bool_t *enable); - - - HSL_LOCAL sw_error_t - shiva_igmp_mld_cmd_set(a_uint32_t dev_id, fal_fwd_cmd_t cmd); - - - HSL_LOCAL sw_error_t - shiva_igmp_mld_cmd_get(a_uint32_t dev_id, fal_fwd_cmd_t * cmd); - - - HSL_LOCAL sw_error_t - shiva_port_igmp_mld_join_set(a_uint32_t dev_id, fal_port_t port_id, a_bool_t enable); - - - HSL_LOCAL sw_error_t - shiva_port_igmp_mld_join_get(a_uint32_t dev_id, fal_port_t port_id, a_bool_t * enable); - - - HSL_LOCAL sw_error_t - shiva_port_igmp_mld_leave_set(a_uint32_t dev_id, fal_port_t port_id, a_bool_t enable); - - - HSL_LOCAL sw_error_t - shiva_port_igmp_mld_leave_get(a_uint32_t dev_id, fal_port_t port_id, a_bool_t * enable); - - - HSL_LOCAL sw_error_t - shiva_igmp_mld_rp_set(a_uint32_t dev_id, fal_pbmp_t pts); - - - HSL_LOCAL sw_error_t - shiva_igmp_mld_rp_get(a_uint32_t dev_id, fal_pbmp_t * pts); - - - HSL_LOCAL sw_error_t - shiva_igmp_mld_entry_creat_set(a_uint32_t dev_id, a_bool_t enable); - - - HSL_LOCAL sw_error_t - shiva_igmp_mld_entry_creat_get(a_uint32_t dev_id, a_bool_t * enable); - - - HSL_LOCAL sw_error_t - shiva_igmp_mld_entry_static_set(a_uint32_t dev_id, a_bool_t enable); - - - HSL_LOCAL sw_error_t - shiva_igmp_mld_entry_static_get(a_uint32_t dev_id, a_bool_t * enable); - - - HSL_LOCAL sw_error_t - shiva_igmp_mld_entry_leaky_set(a_uint32_t dev_id, a_bool_t enable); - - - HSL_LOCAL sw_error_t - shiva_igmp_mld_entry_leaky_get(a_uint32_t dev_id, a_bool_t * enable); - - - HSL_LOCAL sw_error_t - shiva_igmp_mld_entry_v3_set(a_uint32_t dev_id, a_bool_t enable); - - - HSL_LOCAL sw_error_t - shiva_igmp_mld_entry_v3_get(a_uint32_t dev_id, a_bool_t * enable); - - - HSL_LOCAL sw_error_t - shiva_igmp_mld_entry_queue_set(a_uint32_t dev_id, a_bool_t enable, a_uint32_t queue); - - - HSL_LOCAL sw_error_t - shiva_igmp_mld_entry_queue_get(a_uint32_t dev_id, a_bool_t * enable, a_uint32_t * queue); - - -#endif - -#ifdef __cplusplus -} -#endif /* __cplusplus */ - -#endif /* _SHIVA_IGMP_H_ */ -/** - * @} - */ diff --git a/feeds/ipq807x/qca-ssdk/src/include/hsl/shiva/shiva_init.h b/feeds/ipq807x/qca-ssdk/src/include/hsl/shiva/shiva_init.h deleted file mode 100755 index 8610ec098..000000000 --- a/feeds/ipq807x/qca-ssdk/src/include/hsl/shiva/shiva_init.h +++ /dev/null @@ -1,51 +0,0 @@ -/* - * Copyright (c) 2012, The Linux Foundation. All rights reserved. - * Permission to use, copy, modify, and/or distribute this software for - * any purpose with or without fee is hereby granted, provided that the - * above copyright notice and this permission notice appear in all copies. - * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES - * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR - * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES - * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN - * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT - * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. - */ - - -/** - * @defgroup shiva_init SHIVA_INIT - * @{ - */ -#ifndef _SHIVA_INIT_H_ -#define _SHIVA_INIT_H_ - -#ifdef __cplusplus -extern "C" { -#endif /* __cplusplus */ - -#include "init/ssdk_init.h" - - - sw_error_t - shiva_init(a_uint32_t dev_id, ssdk_init_cfg *cfg); - - - sw_error_t - shiva_cleanup(a_uint32_t dev_id); - -#ifdef HSL_STANDALONG - - HSL_LOCAL sw_error_t - shiva_reset(a_uint32_t dev_id); - -#endif - -#ifdef __cplusplus -} -#endif /* __cplusplus */ - -#endif /* _SHIVA_INIT_H_ */ -/** - * @} - */ diff --git a/feeds/ipq807x/qca-ssdk/src/include/hsl/shiva/shiva_leaky.h b/feeds/ipq807x/qca-ssdk/src/include/hsl/shiva/shiva_leaky.h deleted file mode 100755 index 6cd53b24e..000000000 --- a/feeds/ipq807x/qca-ssdk/src/include/hsl/shiva/shiva_leaky.h +++ /dev/null @@ -1,100 +0,0 @@ -/* - * Copyright (c) 2012, The Linux Foundation. All rights reserved. - * Permission to use, copy, modify, and/or distribute this software for - * any purpose with or without fee is hereby granted, provided that the - * above copyright notice and this permission notice appear in all copies. - * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES - * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR - * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES - * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN - * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT - * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. - */ - - -/** - * @defgroup shiva_leaky SHIVA_LEAKY - * @{ - */ -#ifndef _SHIVA_LEAKY_H_ -#define _SHIVA_LEAKY_H_ - -#ifdef __cplusplus -extern "C" { -#endif /* __cplusplus */ - -#include "fal/fal_leaky.h" - - sw_error_t shiva_leaky_init(a_uint32_t dev_id); - -#ifdef IN_LEAKY -#define SHIVA_LEAKY_INIT(rv, dev_id) \ - { \ - rv = shiva_leaky_init(dev_id); \ - SW_RTN_ON_ERROR(rv); \ - } -#else -#define SHIVA_LEAKY_INIT(rv, dev_id) -#endif - -#ifdef HSL_STANDALONG - - - HSL_LOCAL sw_error_t - shiva_uc_leaky_mode_set(a_uint32_t dev_id, - fal_leaky_ctrl_mode_t ctrl_mode); - - - HSL_LOCAL sw_error_t - shiva_uc_leaky_mode_get(a_uint32_t dev_id, - fal_leaky_ctrl_mode_t * ctrl_mode); - - - HSL_LOCAL sw_error_t - shiva_mc_leaky_mode_set(a_uint32_t dev_id, - fal_leaky_ctrl_mode_t ctrl_mode); - - - HSL_LOCAL sw_error_t - shiva_mc_leaky_mode_get(a_uint32_t dev_id, - fal_leaky_ctrl_mode_t * ctrl_mode); - - - HSL_LOCAL sw_error_t - shiva_port_arp_leaky_set(a_uint32_t dev_id, fal_port_t port_id, - a_bool_t enable); - - - HSL_LOCAL sw_error_t - shiva_port_arp_leaky_get(a_uint32_t dev_id, fal_port_t port_id, - a_bool_t * enable); - - - HSL_LOCAL sw_error_t - shiva_port_uc_leaky_set(a_uint32_t dev_id, fal_port_t port_id, - a_bool_t enable); - - - HSL_LOCAL sw_error_t - shiva_port_uc_leaky_get(a_uint32_t dev_id, fal_port_t port_id, - a_bool_t * enable); - - - HSL_LOCAL sw_error_t - shiva_port_mc_leaky_set(a_uint32_t dev_id, fal_port_t port_id, - a_bool_t enable); - - - HSL_LOCAL sw_error_t - shiva_port_mc_leaky_get(a_uint32_t dev_id, fal_port_t port_id, - a_bool_t * enable); -#endif - -#ifdef __cplusplus -} -#endif /* __cplusplus */ -#endif /* _SHIVA_LEAKY_H_ */ -/** - * @} - */ diff --git a/feeds/ipq807x/qca-ssdk/src/include/hsl/shiva/shiva_led.h b/feeds/ipq807x/qca-ssdk/src/include/hsl/shiva/shiva_led.h deleted file mode 100755 index a75369fba..000000000 --- a/feeds/ipq807x/qca-ssdk/src/include/hsl/shiva/shiva_led.h +++ /dev/null @@ -1,55 +0,0 @@ -/* - * Copyright (c) 2012, The Linux Foundation. All rights reserved. - * Permission to use, copy, modify, and/or distribute this software for - * any purpose with or without fee is hereby granted, provided that the - * above copyright notice and this permission notice appear in all copies. - * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES - * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR - * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES - * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN - * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT - * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. - */ - - -#ifndef _SHIVA_LED_H_ -#define _SHIVA_LED_H_ - -#ifdef __cplusplus -extern "C" { -#endif /* __cplusplus */ - -#include "fal/fal_led.h" - - sw_error_t - shiva_led_init(a_uint32_t dev_id); - -#ifdef IN_LED -#define SHIVA_LED_INIT(rv, dev_id) \ - { \ - rv = shiva_led_init(dev_id); \ - SW_RTN_ON_ERROR(rv); \ - } -#else -#define SHIVA_LED_INIT(rv, dev_id) -#endif - -#ifdef HSL_STANDALONG - - HSL_LOCAL sw_error_t - shiva_led_ctrl_pattern_set(a_uint32_t dev_id, led_pattern_group_t group, - led_pattern_id_t id, led_ctrl_pattern_t * pattern); - - - HSL_LOCAL sw_error_t - shiva_led_ctrl_pattern_get(a_uint32_t dev_id, led_pattern_group_t group, - led_pattern_id_t id, led_ctrl_pattern_t * pattern); - -#endif - -#ifdef __cplusplus -} -#endif /* __cplusplus */ - -#endif /* _SHIVA_LED_H_ */ diff --git a/feeds/ipq807x/qca-ssdk/src/include/hsl/shiva/shiva_mib.h b/feeds/ipq807x/qca-ssdk/src/include/hsl/shiva/shiva_mib.h deleted file mode 100755 index 0b91b5b35..000000000 --- a/feeds/ipq807x/qca-ssdk/src/include/hsl/shiva/shiva_mib.h +++ /dev/null @@ -1,65 +0,0 @@ -/* - * Copyright (c) 2012, The Linux Foundation. All rights reserved. - * Permission to use, copy, modify, and/or distribute this software for - * any purpose with or without fee is hereby granted, provided that the - * above copyright notice and this permission notice appear in all copies. - * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES - * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR - * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES - * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN - * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT - * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. - */ - - -/** - * @defgroup shiva_mib SHIVA_MIB - * @{ - */ -#ifndef _SHIVA_MIB_H_ -#define _SHIVA_MIB_H_ - -#ifdef __cplusplus -extern "C" { -#endif /* __cplusplus */ - -#include "fal/fal_mib.h" - - sw_error_t - shiva_mib_init(a_uint32_t dev_id); - -#ifdef IN_MIB -#define SHIVA_MIB_INIT(rv, dev_id) \ - { \ - rv = shiva_mib_init(dev_id); \ - SW_RTN_ON_ERROR(rv); \ - } -#else -#define SHIVA_MIB_INIT(rv, dev_id) -#endif - -#ifdef HSL_STANDALONG - - HSL_LOCAL sw_error_t - shiva_get_mib_info(a_uint32_t dev_id, fal_port_t port_id, - fal_mib_info_t * mib_info ); - - - HSL_LOCAL sw_error_t - shiva_mib_status_set(a_uint32_t dev_id, a_bool_t enable); - - - HSL_LOCAL sw_error_t - shiva_mib_status_get(a_uint32_t dev_id, a_bool_t * enable); - -#endif - -#ifdef __cplusplus -} -#endif /* __cplusplus */ - -#endif /* _SHIVA_MIB_H_ */ -/** - * @} - */ diff --git a/feeds/ipq807x/qca-ssdk/src/include/hsl/shiva/shiva_mirror.h b/feeds/ipq807x/qca-ssdk/src/include/hsl/shiva/shiva_mirror.h deleted file mode 100755 index d889fd597..000000000 --- a/feeds/ipq807x/qca-ssdk/src/include/hsl/shiva/shiva_mirror.h +++ /dev/null @@ -1,79 +0,0 @@ -/* - * Copyright (c) 2012, The Linux Foundation. All rights reserved. - * Permission to use, copy, modify, and/or distribute this software for - * any purpose with or without fee is hereby granted, provided that the - * above copyright notice and this permission notice appear in all copies. - * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES - * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR - * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES - * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN - * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT - * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. - */ - - -/** - * @defgroup shiva_mirror SHIVA_MIRROR - * @{ - */ -#ifndef _SHIVA_MIRROR_H_ -#define _SHIVA_MIRROR_H_ - -#ifdef __cplusplus -extern "C" { -#endif /* __cplusplus */ - -#include "fal/fal_mirror.h" -#define MIRROR_ANALYZER_NONE 0xf - - sw_error_t shiva_mirr_init(a_uint32_t dev_id); - -#ifdef IN_MIRROR -#define SHIVA_MIRR_INIT(rv, dev_id) \ - { \ - rv = shiva_mirr_init(dev_id); \ - SW_RTN_ON_ERROR(rv); \ - } -#else -#define SHIVA_MIRR_INIT(rv, dev_id) -#endif - -#ifdef HSL_STANDALONG - - HSL_LOCAL sw_error_t - shiva_mirr_analysis_port_set(a_uint32_t dev_id, fal_port_t port_id); - - - HSL_LOCAL sw_error_t - shiva_mirr_analysis_port_get(a_uint32_t dev_id, fal_port_t * port_id); - - - HSL_LOCAL sw_error_t - shiva_mirr_port_in_set(a_uint32_t dev_id, fal_port_t port_id, - a_bool_t enable); - - - HSL_LOCAL sw_error_t - shiva_mirr_port_in_get(a_uint32_t dev_id, fal_port_t port_id, - a_bool_t * enable); - - - HSL_LOCAL sw_error_t - shiva_mirr_port_eg_set(a_uint32_t dev_id, fal_port_t port_id, - a_bool_t enable); - - - HSL_LOCAL sw_error_t - shiva_mirr_port_eg_get(a_uint32_t dev_id, fal_port_t port_id, - a_bool_t * enable); - -#endif - -#ifdef __cplusplus -} -#endif /* __cplusplus */ -#endif /* _SHIVA_MIRROR_H_ */ -/** - * @} - */ diff --git a/feeds/ipq807x/qca-ssdk/src/include/hsl/shiva/shiva_misc.h b/feeds/ipq807x/qca-ssdk/src/include/hsl/shiva/shiva_misc.h deleted file mode 100755 index 5c4fdbd2e..000000000 --- a/feeds/ipq807x/qca-ssdk/src/include/hsl/shiva/shiva_misc.h +++ /dev/null @@ -1,188 +0,0 @@ -/* - * Copyright (c) 2012, The Linux Foundation. All rights reserved. - * Permission to use, copy, modify, and/or distribute this software for - * any purpose with or without fee is hereby granted, provided that the - * above copyright notice and this permission notice appear in all copies. - * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES - * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR - * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES - * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN - * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT - * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. - */ - - -/** - * @defgroup shiva_misc SHIVA_MISC - * @{ - */ -#ifndef _SHIVA_MISC_H_ -#define _SHIVA_MISC_H_ - -#ifdef __cplusplus -extern "C" { -#endif /* __cplusplus */ - -#include "fal/fal_misc.h" - - sw_error_t shiva_misc_init(a_uint32_t dev_id); - -#ifdef IN_MISC -#define SHIVA_MISC_INIT(rv, dev_id) \ - { \ - rv = shiva_misc_init(dev_id); \ - SW_RTN_ON_ERROR(rv); \ - } -#else -#define SHIVA_MISC_INIT(rv, dev_id) -#endif - -#ifdef HSL_STANDALONG - - HSL_LOCAL sw_error_t - shiva_arp_status_set(a_uint32_t dev_id, a_bool_t enable); - - - HSL_LOCAL sw_error_t - shiva_arp_status_get(a_uint32_t dev_id, a_bool_t * enable); - - - HSL_LOCAL sw_error_t - shiva_frame_max_size_set(a_uint32_t dev_id, a_uint32_t size); - - - HSL_LOCAL sw_error_t - shiva_frame_max_size_get(a_uint32_t dev_id, a_uint32_t * size); - - - HSL_LOCAL sw_error_t - shiva_port_unk_sa_cmd_set(a_uint32_t dev_id, fal_port_t port_id, - fal_fwd_cmd_t cmd); - - - HSL_LOCAL sw_error_t - shiva_port_unk_sa_cmd_get(a_uint32_t dev_id, fal_port_t port_id, - fal_fwd_cmd_t * cmd); - - - HSL_LOCAL sw_error_t - shiva_port_unk_uc_filter_set(a_uint32_t dev_id, fal_port_t port_id, - a_bool_t enable); - - - HSL_LOCAL sw_error_t - shiva_port_unk_uc_filter_get(a_uint32_t dev_id, fal_port_t port_id, - a_bool_t * enable); - - - HSL_LOCAL sw_error_t - shiva_port_unk_mc_filter_set(a_uint32_t dev_id, fal_port_t port_id, - a_bool_t enable); - - - HSL_LOCAL sw_error_t - shiva_port_unk_mc_filter_get(a_uint32_t dev_id, fal_port_t port_id, - a_bool_t * enable); - - - HSL_LOCAL sw_error_t - shiva_port_bc_filter_set(a_uint32_t dev_id, fal_port_t port_id, - a_bool_t enable); - - - HSL_LOCAL sw_error_t - shiva_port_bc_filter_get(a_uint32_t dev_id, fal_port_t port_id, - a_bool_t * enable); - - - HSL_LOCAL sw_error_t - shiva_cpu_port_status_set(a_uint32_t dev_id, a_bool_t enable); - - - HSL_LOCAL sw_error_t - shiva_cpu_port_status_get(a_uint32_t dev_id, a_bool_t * enable); - - - HSL_LOCAL sw_error_t - shiva_pppoe_cmd_set(a_uint32_t dev_id, fal_fwd_cmd_t cmd); - - - HSL_LOCAL sw_error_t - shiva_pppoe_cmd_get(a_uint32_t dev_id, fal_fwd_cmd_t * cmd); - - - HSL_LOCAL sw_error_t - shiva_pppoe_status_set(a_uint32_t dev_id, a_bool_t enable); - - - HSL_LOCAL sw_error_t - shiva_pppoe_status_get(a_uint32_t dev_id, a_bool_t * enable); - - - HSL_LOCAL sw_error_t - shiva_port_dhcp_set(a_uint32_t dev_id, fal_port_t port_id, a_bool_t enable); - - - HSL_LOCAL sw_error_t - shiva_port_dhcp_get(a_uint32_t dev_id, fal_port_t port_id, a_bool_t * enable); - - - HSL_LOCAL sw_error_t - shiva_arp_cmd_set(a_uint32_t dev_id, fal_fwd_cmd_t cmd); - - - HSL_LOCAL sw_error_t - shiva_arp_cmd_get(a_uint32_t dev_id, fal_fwd_cmd_t * cmd); - - - HSL_LOCAL sw_error_t - shiva_eapol_cmd_set(a_uint32_t dev_id, fal_fwd_cmd_t cmd); - - - HSL_LOCAL sw_error_t - shiva_eapol_cmd_get(a_uint32_t dev_id, fal_fwd_cmd_t * cmd); - - - HSL_LOCAL sw_error_t - shiva_pppoe_session_add(a_uint32_t dev_id, a_uint32_t session_id, a_bool_t strip_hdr); - - - HSL_LOCAL sw_error_t - shiva_pppoe_session_del(a_uint32_t dev_id, a_uint32_t session_id); - - - HSL_LOCAL sw_error_t - shiva_pppoe_session_get(a_uint32_t dev_id, a_uint32_t session_id, a_bool_t * strip_hdr); - - HSL_LOCAL sw_error_t - shiva_eapol_status_set(a_uint32_t dev_id, a_uint32_t port_id, a_bool_t enable); - - HSL_LOCAL sw_error_t - shiva_eapol_status_get(a_uint32_t dev_id, a_uint32_t port_id, a_bool_t * enable); - - HSL_LOCAL sw_error_t - shiva_ripv1_status_set(a_uint32_t dev_id, a_bool_t enable); - - HSL_LOCAL sw_error_t - shiva_ripv1_status_get(a_uint32_t dev_id, a_bool_t * enable); - - HSL_LOCAL sw_error_t - shiva_loop_check_status_set(a_uint32_t dev_id, fal_loop_check_time_t time, a_bool_t enable); - - HSL_LOCAL sw_error_t - shiva_loop_check_status_get(a_uint32_t dev_id, fal_loop_check_time_t * time, a_bool_t * enable); - - HSL_LOCAL sw_error_t - shiva_loop_check_info_get(a_uint32_t dev_id, a_uint32_t * old_port_id, a_uint32_t * new_port_id); - - -#endif - -#ifdef __cplusplus -} -#endif /* __cplusplus */ -#endif /* _SHIVA_GEN_H_ */ -/** - * @} - */ diff --git a/feeds/ipq807x/qca-ssdk/src/include/hsl/shiva/shiva_port_ctrl.h b/feeds/ipq807x/qca-ssdk/src/include/hsl/shiva/shiva_port_ctrl.h deleted file mode 100755 index 169041339..000000000 --- a/feeds/ipq807x/qca-ssdk/src/include/hsl/shiva/shiva_port_ctrl.h +++ /dev/null @@ -1,151 +0,0 @@ -/* - * Copyright (c) 2012, The Linux Foundation. All rights reserved. - * Permission to use, copy, modify, and/or distribute this software for - * any purpose with or without fee is hereby granted, provided that the - * above copyright notice and this permission notice appear in all copies. - * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES - * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR - * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES - * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN - * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT - * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. - */ - - -/** - * @defgroup shiva_port_ctrl SHIVA_PORT_CONTROL - * @{ - */ -#ifndef _SHIVA_PORT_CTRL_H_ -#define _SHIVA_PORT_CTRL_H_ - -#ifdef __cplusplus -extern "C" { -#endif /* __cplusplus */ - -#include "fal/fal_port_ctrl.h" - -#define RX_FC_EN 1 -#define TX_FC_FULL_EN 1 -#define TX_FC_HALF_EN 1 - -sw_error_t shiva_port_ctrl_init(a_uint32_t dev_id); - -#ifdef IN_PORTCONTROL -#define SHIVA_PORT_CTRL_INIT(rv, dev_id) \ - { \ - rv = shiva_port_ctrl_init(dev_id); \ - SW_RTN_ON_ERROR(rv); \ - } -#else -#define SHIVA_PORT_CTRL_INIT(rv, dev_id) -#endif - -#ifdef HSL_STANDALONG - - - HSL_LOCAL sw_error_t - shiva_port_duplex_set(a_uint32_t dev_id, fal_port_t port_id, - fal_port_duplex_t duplex); - - - HSL_LOCAL sw_error_t - shiva_port_duplex_get(a_uint32_t dev_id, fal_port_t port_id, - fal_port_duplex_t * pduplex); - - - HSL_LOCAL sw_error_t - shiva_port_speed_set(a_uint32_t dev_id, fal_port_t port_id, - fal_port_speed_t speed); - - - HSL_LOCAL sw_error_t - shiva_port_speed_get(a_uint32_t dev_id, fal_port_t port_id, - fal_port_speed_t * pspeed); - - - HSL_LOCAL sw_error_t - shiva_port_autoneg_status_get(a_uint32_t dev_id, fal_port_t port_id, - a_bool_t * status); - - - HSL_LOCAL sw_error_t - shiva_port_autoneg_enable(a_uint32_t dev_id, fal_port_t port_id); - - - HSL_LOCAL sw_error_t - shiva_port_autoneg_restart(a_uint32_t dev_id, fal_port_t port_id); - - - HSL_LOCAL sw_error_t - shiva_port_autoneg_adv_set(a_uint32_t dev_id, fal_port_t port_id, - a_uint32_t autoadv); - - - HSL_LOCAL sw_error_t - shiva_port_autoneg_adv_get(a_uint32_t dev_id, fal_port_t port_id, - a_uint32_t * autoadv); - - - HSL_LOCAL sw_error_t - shiva_port_hdr_status_set(a_uint32_t dev_id, fal_port_t port_id, - a_bool_t enable); - - - HSL_LOCAL sw_error_t - shiva_port_hdr_status_get(a_uint32_t dev_id, fal_port_t port_id, - a_bool_t * enable); - - - HSL_LOCAL sw_error_t - shiva_port_flowctrl_set(a_uint32_t dev_id, fal_port_t port_id, - a_bool_t enable); - - - HSL_LOCAL sw_error_t - shiva_port_flowctrl_get(a_uint32_t dev_id, fal_port_t port_id, - a_bool_t * enable); - - - HSL_LOCAL sw_error_t - shiva_port_flowctrl_forcemode_set(a_uint32_t dev_id, - fal_port_t port_id, a_bool_t enable); - - - HSL_LOCAL sw_error_t - shiva_port_flowctrl_forcemode_get(a_uint32_t dev_id, - fal_port_t port_id, - a_bool_t * enable); - - - HSL_LOCAL sw_error_t - shiva_port_powersave_set(a_uint32_t dev_id, fal_port_t port_id, a_bool_t enable); - - - HSL_LOCAL sw_error_t - shiva_port_powersave_get(a_uint32_t dev_id, fal_port_t port_id, a_bool_t *enable); - - - HSL_LOCAL sw_error_t - shiva_port_hibernate_set(a_uint32_t dev_id, fal_port_t port_id, a_bool_t enable); - - - HSL_LOCAL sw_error_t - shiva_port_hibernate_get(a_uint32_t dev_id, fal_port_t port_id, a_bool_t *enable); - - - HSL_LOCAL sw_error_t - shiva_port_cdt(a_uint32_t dev_id, fal_port_t port_id, a_uint32_t mdi_pair, - fal_cable_status_t *cable_status, a_uint32_t *cable_len); - - -#endif - -#ifdef __cplusplus -} -#endif /* __cplusplus */ -#endif /* _SHIVA_PORT_CTRL_H_ */ -/** - * @} - */ diff --git a/feeds/ipq807x/qca-ssdk/src/include/hsl/shiva/shiva_portvlan.h b/feeds/ipq807x/qca-ssdk/src/include/hsl/shiva/shiva_portvlan.h deleted file mode 100755 index fdfa27d4f..000000000 --- a/feeds/ipq807x/qca-ssdk/src/include/hsl/shiva/shiva_portvlan.h +++ /dev/null @@ -1,211 +0,0 @@ -/* - * Copyright (c) 2012, The Linux Foundation. All rights reserved. - * Permission to use, copy, modify, and/or distribute this software for - * any purpose with or without fee is hereby granted, provided that the - * above copyright notice and this permission notice appear in all copies. - * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES - * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR - * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES - * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN - * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT - * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. - */ - - - -/** - * @defgroup shiva_port_vlan SHIVA_PORT_VLAN - * @{ - */ -#ifndef _SHIVA_PORTVLAN_H_ -#define _SHIVA_PORTVLAN_H_ - -#ifdef __cplusplus -extern "C" { -#endif /* __cplusplus */ - -#include "fal/fal_portvlan.h" - - sw_error_t shiva_portvlan_init(a_uint32_t dev_id); - -#ifdef IN_PORTVLAN -#define SHIVA_PORTVLAN_INIT(rv, dev_id) \ - { \ - rv = shiva_portvlan_init(dev_id); \ - SW_RTN_ON_ERROR(rv); \ - } -#else -#define SHIVA_PORTVLAN_INIT(rv, dev_id) -#endif - -#ifdef HSL_STANDALONG - - - HSL_LOCAL sw_error_t - shiva_port_1qmode_set(a_uint32_t dev_id, fal_port_t port_id, - fal_pt_1qmode_t port_1qmode); - - - HSL_LOCAL sw_error_t - shiva_port_1qmode_get(a_uint32_t dev_id, fal_port_t port_id, - fal_pt_1qmode_t * pport_1qmode); - - - HSL_LOCAL sw_error_t - shiva_port_egvlanmode_set(a_uint32_t dev_id, fal_port_t port_id, - fal_pt_1q_egmode_t port_egvlanmode); - - - HSL_LOCAL sw_error_t - shiva_port_egvlanmode_get(a_uint32_t dev_id, fal_port_t port_id, - fal_pt_1q_egmode_t * pport_egvlanmode); - - - HSL_LOCAL sw_error_t - shiva_portvlan_member_add(a_uint32_t dev_id, fal_port_t port_id, - a_uint32_t mem_port_id); - - - HSL_LOCAL sw_error_t - shiva_portvlan_member_del(a_uint32_t dev_id, fal_port_t port_id, - a_uint32_t mem_port_id); - - - HSL_LOCAL sw_error_t - shiva_portvlan_member_update(a_uint32_t dev_id, fal_port_t port_id, - fal_pbmp_t mem_port_map); - - - HSL_LOCAL sw_error_t - shiva_portvlan_member_get(a_uint32_t dev_id, fal_port_t port_id, - fal_pbmp_t * mem_port_map); - - - HSL_LOCAL sw_error_t - shiva_port_force_default_vid_set(a_uint32_t dev_id, fal_port_t port_id, - a_bool_t enable); - - - HSL_LOCAL sw_error_t - shiva_port_force_default_vid_get(a_uint32_t dev_id, fal_port_t port_id, a_bool_t * enable); - - - HSL_LOCAL sw_error_t - shiva_port_force_portvlan_set(a_uint32_t dev_id, fal_port_t port_id, - a_bool_t enable); - - - HSL_LOCAL sw_error_t - shiva_port_force_portvlan_get(a_uint32_t dev_id, fal_port_t port_id, a_bool_t * enable); - - - HSL_LOCAL sw_error_t - shiva_nestvlan_tpid_set(a_uint32_t dev_id, a_uint32_t tpid); - - - HSL_LOCAL sw_error_t - shiva_nestvlan_tpid_get(a_uint32_t dev_id, a_uint32_t * tpid); - - - HSL_LOCAL sw_error_t - shiva_port_invlan_mode_set(a_uint32_t dev_id, fal_port_t port_id, - fal_pt_invlan_mode_t mode); - - - HSL_LOCAL sw_error_t - shiva_port_invlan_mode_get(a_uint32_t dev_id, fal_port_t port_id, - fal_pt_invlan_mode_t * mode); - - - HSL_LOCAL sw_error_t - shiva_port_tls_set(a_uint32_t dev_id, fal_port_t port_id, - a_bool_t enable); - - - HSL_LOCAL sw_error_t - shiva_port_tls_get(a_uint32_t dev_id, fal_port_t port_id, - a_bool_t * enable); - - - HSL_LOCAL sw_error_t - shiva_port_pri_propagation_set(a_uint32_t dev_id, fal_port_t port_id, - a_bool_t enable); - - - HSL_LOCAL sw_error_t - shiva_port_pri_propagation_get(a_uint32_t dev_id, fal_port_t port_id, - a_bool_t * enable); - - - HSL_LOCAL sw_error_t - shiva_port_default_svid_set(a_uint32_t dev_id, fal_port_t port_id, - a_uint32_t vid); - - - HSL_LOCAL sw_error_t - shiva_port_default_svid_get(a_uint32_t dev_id, fal_port_t port_id, - a_uint32_t * vid); - - HSL_LOCAL sw_error_t - shiva_port_default_cvid_set(a_uint32_t dev_id, fal_port_t port_id, - a_uint32_t vid); - - - HSL_LOCAL sw_error_t - shiva_port_default_cvid_get(a_uint32_t dev_id, fal_port_t port_id, - a_uint32_t * vid); - - - HSL_LOCAL sw_error_t - shiva_port_vlan_propagation_set(a_uint32_t dev_id, fal_port_t port_id, - fal_vlan_propagation_mode_t mode); - - - HSL_LOCAL sw_error_t - shiva_port_vlan_propagation_get(a_uint32_t dev_id, fal_port_t port_id, - fal_vlan_propagation_mode_t * mode); - - - HSL_LOCAL sw_error_t - shiva_port_vlan_trans_add(a_uint32_t dev_id, fal_port_t port_id, fal_vlan_trans_entry_t *entry); - - - HSL_LOCAL sw_error_t - shiva_port_vlan_trans_del(a_uint32_t dev_id, fal_port_t port_id, fal_vlan_trans_entry_t *entry); - - - HSL_LOCAL sw_error_t - shiva_port_vlan_trans_get(a_uint32_t dev_id, fal_port_t port_id, fal_vlan_trans_entry_t *entry); - - - HSL_LOCAL sw_error_t - shiva_qinq_mode_set(a_uint32_t dev_id, fal_qinq_mode_t mode); - - - HSL_LOCAL sw_error_t - shiva_qinq_mode_get(a_uint32_t dev_id, fal_qinq_mode_t * mode); - - - HSL_LOCAL sw_error_t - shiva_port_qinq_role_set(a_uint32_t dev_id, fal_port_t port_id, fal_qinq_port_role_t role); - - - HSL_LOCAL sw_error_t - shiva_port_qinq_role_get(a_uint32_t dev_id, fal_port_t port_id, fal_qinq_port_role_t * role); - - - HSL_LOCAL sw_error_t - shiva_port_vlan_trans_iterate(a_uint32_t dev_id, fal_port_t port_id, - a_uint32_t * iterator, fal_vlan_trans_entry_t * entry); - - -#endif - -#ifdef __cplusplus -} -#endif /* __cplusplus */ -#endif /* _SHIVA_PORTVLAN_H_ */ -/** - * @} - */ diff --git a/feeds/ipq807x/qca-ssdk/src/include/hsl/shiva/shiva_qos.h b/feeds/ipq807x/qca-ssdk/src/include/hsl/shiva/shiva_qos.h deleted file mode 100755 index cd588ac6f..000000000 --- a/feeds/ipq807x/qca-ssdk/src/include/hsl/shiva/shiva_qos.h +++ /dev/null @@ -1,164 +0,0 @@ -/* - * Copyright (c) 2012, The Linux Foundation. All rights reserved. - * Permission to use, copy, modify, and/or distribute this software for - * any purpose with or without fee is hereby granted, provided that the - * above copyright notice and this permission notice appear in all copies. - * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES - * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR - * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES - * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN - * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT - * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. - */ - - -/** - * @defgroup shiva_qos SHIVA_QOS - * @{ - */ -#ifndef _SHIVA_QOS_H_ -#define _SHIVA_QOS_H_ - -#ifdef __cplusplus -extern "C" { -#endif /* __cplusplus */ - -#include "fal/fal_qos.h" - - sw_error_t shiva_qos_init(a_uint32_t dev_id); - -#ifdef IN_QOS -#define SHIVA_QOS_INIT(rv, dev_id) \ - { \ - rv = shiva_qos_init(dev_id); \ - SW_RTN_ON_ERROR(rv); \ - } -#else -#define SHIVA_QOS_INIT(rv, dev_id) -#endif - -#ifdef HSL_STANDALONG - - - HSL_LOCAL sw_error_t - shiva_qos_queue_tx_buf_status_set(a_uint32_t dev_id, - fal_port_t port_id, a_bool_t enable); - - - HSL_LOCAL sw_error_t - shiva_qos_queue_tx_buf_status_get(a_uint32_t dev_id, - fal_port_t port_id, - a_bool_t * enable); - - HSL_LOCAL sw_error_t - shiva_qos_port_tx_buf_status_set(a_uint32_t dev_id, fal_port_t port_id, - a_bool_t enable); - - - HSL_LOCAL sw_error_t - shiva_qos_port_tx_buf_status_get(a_uint32_t dev_id, fal_port_t port_id, - a_bool_t * enable); - - - HSL_LOCAL sw_error_t - shiva_qos_queue_tx_buf_nr_set(a_uint32_t dev_id, fal_port_t port_id, - fal_queue_t queue_id, - a_uint32_t * number); - - - HSL_LOCAL sw_error_t - shiva_qos_queue_tx_buf_nr_get(a_uint32_t dev_id, fal_port_t port_id, - fal_queue_t queue_id, - a_uint32_t * number); - - - HSL_LOCAL sw_error_t - shiva_qos_port_tx_buf_nr_set(a_uint32_t dev_id, fal_port_t port_id, - a_uint32_t * number); - - - HSL_LOCAL sw_error_t - shiva_qos_port_tx_buf_nr_get(a_uint32_t dev_id, fal_port_t port_id, - a_uint32_t * number); - - - HSL_LOCAL sw_error_t - shiva_qos_port_rx_buf_nr_set(a_uint32_t dev_id, fal_port_t port_id, - a_uint32_t * number); - - - HSL_LOCAL sw_error_t - shiva_qos_port_rx_buf_nr_get(a_uint32_t dev_id, fal_port_t port_id, - a_uint32_t * number); - - - HSL_LOCAL sw_error_t - shiva_cosmap_up_queue_set(a_uint32_t dev_id, a_uint32_t up, - fal_queue_t queue); - - - HSL_LOCAL sw_error_t - shiva_cosmap_up_queue_get(a_uint32_t dev_id, a_uint32_t up, - fal_queue_t * queue); - - - HSL_LOCAL sw_error_t - shiva_cosmap_dscp_queue_set(a_uint32_t dev_id, a_uint32_t dscp, - fal_queue_t queue); - - - HSL_LOCAL sw_error_t - shiva_cosmap_dscp_queue_get(a_uint32_t dev_id, a_uint32_t dscp, - fal_queue_t * queue); - - - HSL_LOCAL sw_error_t - shiva_qos_port_mode_set(a_uint32_t dev_id, fal_port_t port_id, - fal_qos_mode_t mode, a_bool_t enable); - - - HSL_LOCAL sw_error_t - shiva_qos_port_mode_get(a_uint32_t dev_id, fal_port_t port_id, - fal_qos_mode_t mode, a_bool_t * enable); - - - HSL_LOCAL sw_error_t - shiva_qos_port_mode_pri_set(a_uint32_t dev_id, fal_port_t port_id, - fal_qos_mode_t mode, a_uint32_t pri); - - - HSL_LOCAL sw_error_t - shiva_qos_port_mode_pri_get(a_uint32_t dev_id, fal_port_t port_id, - fal_qos_mode_t mode, a_uint32_t * pri); - - - HSL_LOCAL sw_error_t - shiva_qos_port_default_up_set(a_uint32_t dev_id, fal_port_t port_id, - a_uint32_t up); - - - HSL_LOCAL sw_error_t - shiva_qos_port_default_up_get(a_uint32_t dev_id, fal_port_t port_id, - a_uint32_t * up); - - - HSL_LOCAL sw_error_t - shiva_qos_port_sch_mode_set(a_uint32_t dev_id, a_uint32_t port_id, - fal_sch_mode_t mode, const a_uint32_t weight[]); - - - HSL_LOCAL sw_error_t - shiva_qos_port_sch_mode_get(a_uint32_t dev_id, a_uint32_t port_id, - fal_sch_mode_t * mode, a_uint32_t weight[]); - - -#endif - -#ifdef __cplusplus -} -#endif /* __cplusplus */ -#endif /* _SHIVA_QOS_H_ */ -/** - * @} - */ diff --git a/feeds/ipq807x/qca-ssdk/src/include/hsl/shiva/shiva_rate.h b/feeds/ipq807x/qca-ssdk/src/include/hsl/shiva/shiva_rate.h deleted file mode 100755 index 7648dbbfa..000000000 --- a/feeds/ipq807x/qca-ssdk/src/include/hsl/shiva/shiva_rate.h +++ /dev/null @@ -1,102 +0,0 @@ -/* - * Copyright (c) 2012, The Linux Foundation. All rights reserved. - * Permission to use, copy, modify, and/or distribute this software for - * any purpose with or without fee is hereby granted, provided that the - * above copyright notice and this permission notice appear in all copies. - * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES - * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR - * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES - * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN - * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT - * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. - */ - - -/** - * @defgroup shiva_rate SHIVA_RATE - * @{ - */ -#ifndef _SHIVA_RATE_H_ -#define _SHIVA_RATE_H_ - -#ifdef __cplusplus -extern "C" { -#endif /* __cplusplus */ - -#include "fal/fal_rate.h" - - sw_error_t shiva_rate_init(a_uint32_t dev_id); - -#ifdef IN_RATE -#define SHIVA_RATE_INIT(rv, dev_id) \ - { \ - rv = shiva_rate_init(dev_id); \ - SW_RTN_ON_ERROR(rv); \ - } -#else -#define SHIVA_RATE_INIT(rv, dev_id) -#endif - -#ifdef HSL_STANDALONG - - - HSL_LOCAL sw_error_t - shiva_rate_queue_egrl_set(a_uint32_t dev_id, fal_port_t port_id, - fal_queue_t queue_id, a_uint32_t * speed, - a_bool_t enable); - - - HSL_LOCAL sw_error_t - shiva_rate_queue_egrl_get(a_uint32_t dev_id, fal_port_t port_id, - fal_queue_t queue_id, a_uint32_t * speed, - a_bool_t * enable); - - - HSL_LOCAL sw_error_t - shiva_rate_port_egrl_set(a_uint32_t dev_id, fal_port_t port_id, - a_uint32_t * speed, a_bool_t enable); - - - HSL_LOCAL sw_error_t - shiva_rate_port_egrl_get(a_uint32_t dev_id, fal_port_t port_id, - a_uint32_t * speed, a_bool_t * enable); - - - HSL_LOCAL sw_error_t - shiva_rate_port_inrl_set(a_uint32_t dev_id, fal_port_t port_id, - a_uint32_t * speed, a_bool_t enable); - - - HSL_LOCAL sw_error_t - shiva_rate_port_inrl_get(a_uint32_t dev_id, fal_port_t port_id, - a_uint32_t * speed, a_bool_t * enable); - - - HSL_LOCAL sw_error_t - shiva_storm_ctrl_frame_set(a_uint32_t dev_id, fal_port_t port_id, - fal_storm_type_t storm_type, a_bool_t enable); - - - HSL_LOCAL sw_error_t - shiva_storm_ctrl_frame_get(a_uint32_t dev_id, fal_port_t port_id, - fal_storm_type_t storm_type, a_bool_t * enable); - - - HSL_LOCAL sw_error_t - shiva_storm_ctrl_rate_set(a_uint32_t dev_id, fal_port_t port_id, - a_uint32_t * rate_in_pps); - - - HSL_LOCAL sw_error_t - shiva_storm_ctrl_rate_get(a_uint32_t dev_id, fal_port_t port_id, - a_uint32_t * rate_in_pps); -#endif - -#ifdef __cplusplus -} -#endif /* __cplusplus */ -#endif /* _SHIVA_RATE_H_ */ -/** - * @} - */ diff --git a/feeds/ipq807x/qca-ssdk/src/include/hsl/shiva/shiva_reduced_acl.h b/feeds/ipq807x/qca-ssdk/src/include/hsl/shiva/shiva_reduced_acl.h deleted file mode 100755 index 51fa9a10f..000000000 --- a/feeds/ipq807x/qca-ssdk/src/include/hsl/shiva/shiva_reduced_acl.h +++ /dev/null @@ -1,54 +0,0 @@ -/* - * Copyright (c) 2012,2018, The Linux Foundation. All rights reserved. - * Permission to use, copy, modify, and/or distribute this software for - * any purpose with or without fee is hereby granted, provided that the - * above copyright notice and this permission notice appear in all copies. - * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES - * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR - * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES - * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN - * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT - * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. - */ - - - -#ifndef _SHIVA_REDUCED_ACL_H_ -#define _SHIVA_REDUCED_ACL_H_ - -#ifdef __cplusplus -extern "C" { -#endif /* __cplusplus */ - -#include "sw.h" - - sw_error_t - shiva_acl_rule_write(a_uint32_t dev_id, a_uint32_t rule_idx, a_uint32_t vlu[8], - a_uint32_t msk[8]); - - sw_error_t - shiva_acl_action_write(a_uint32_t dev_id, a_uint32_t act_idx, - a_uint32_t act[3]); - - sw_error_t - shiva_acl_slct_write(a_uint32_t dev_id, a_uint32_t slct_idx, - a_uint32_t slct[8]); - - sw_error_t - shiva_acl_rule_read(a_uint32_t dev_id, a_uint32_t rule_idx, a_uint32_t vlu[8], - a_uint32_t msk[8]); - - sw_error_t - shiva_acl_action_read(a_uint32_t dev_id, a_uint32_t act_idx, - a_uint32_t act[3]); - - sw_error_t - shiva_acl_slct_read(a_uint32_t dev_id, a_uint32_t slct_idx, - a_uint32_t slct[8]); - -#ifdef __cplusplus -} -#endif /* __cplusplus */ -#endif /* _SHIVA_REDUCED_ACL_H_ */ - diff --git a/feeds/ipq807x/qca-ssdk/src/include/hsl/shiva/shiva_reg.h b/feeds/ipq807x/qca-ssdk/src/include/hsl/shiva/shiva_reg.h deleted file mode 100755 index 48561c7ea..000000000 --- a/feeds/ipq807x/qca-ssdk/src/include/hsl/shiva/shiva_reg.h +++ /dev/null @@ -1,4075 +0,0 @@ -/* - * Copyright (c) 2012, The Linux Foundation. All rights reserved. - * Permission to use, copy, modify, and/or distribute this software for - * any purpose with or without fee is hereby granted, provided that the - * above copyright notice and this permission notice appear in all copies. - * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES - * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR - * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES - * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN - * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT - * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. - */ - - - -#ifndef _SHIVA_REG_H_ -#define _SHIVA_REG_H_ - -#ifdef __cplusplus -extern "C" { -#endif /* __cplusplus */ - -#define MAX_ENTRY_LEN 128 - -#define HSL_RW 1 -#define HSL_RO 0 - - - /* SHIVA Mask Control Register */ -#define MASK_CTL "mask" -#define MASK_CTL_ID 0 -#define MASK_CTL_OFFSET 0x0000 -#define MASK_CTL_E_LENGTH 4 -#define MASK_CTL_E_OFFSET 0 -#define MASK_CTL_NR_E 1 - -#define SOFT_RST "mask_rst" -#define MASK_CTL_SOFT_RST_BOFFSET 31 -#define MASK_CTL_SOFT_RST_BLEN 1 -#define MASK_CTL_SOFT_RST_FLAG HSL_RW - -#define MII_CLK5_SEL "mask_clk5s" -#define MASK_CTL_MII_CLK5_SEL_BOFFSET 21 -#define MASK_CTL_MII_CLK5_SEL_BLEN 1 -#define MASK_CTL_MII_CLK5_SEL_FLAG HSL_RW - -#define MII_CLK0_SEL "mask_clk0s" -#define MASK_CTL_MII_CLK0_SEL_BOFFSET 20 -#define MASK_CTL_MII_CLK0_SEL_BLEN 1 -#define MASK_CTL_MII_CLK0_SEL_FLAG HSL_RW - -#define LOAD_EEPROM "mask_ldro" -#define MASK_CTL_LOAD_EEPROM_BOFFSET 16 -#define MASK_CTL_LOAD_EEPROM_BLEN 1 -#define MASK_CTL_LOAD_EEPROM_FLAG HSL_RW - -#define DEVICE_ID "mask_did" -#define MASK_CTL_DEVICE_ID_BOFFSET 8 -#define MASK_CTL_DEVICE_ID_BLEN 8 -#define MASK_CTL_DEVICE_ID_FLAG HSL_RO - -#define REV_ID "mask_rid" -#define MASK_CTL_REV_ID_BOFFSET 0 -#define MASK_CTL_REV_ID_BLEN 8 -#define MASK_CTL_REV_ID_FLAG HSL_RO - - - /* SHIVA Mask Control Register */ -#define POSTRIP "postrip" -#define POSTRIP_ID 0 -#define POSTRIP_OFFSET 0x0008 -#define POSTRIP_E_LENGTH 4 -#define POSTRIP_E_OFFSET 0 -#define POSTRIP_NR_E 1 - -#define POWER_ON_SEL "postrip_sel" -#define POSTRIP_POWER_ON_SEL_BOFFSET 31 -#define POSTRIP_POWER_ON_SEL_BLEN 1 -#define POSTRIP_POWER_ON_SEL_FLAG HSL_RW - -#define RXDELAY_S1 "postrip_rx_s1" -#define POSTRIP_RXDELAY_S1_BOFFSET 26 -#define POSTRIP_RXDELAY_S1_BLEN 1 -#define POSTRIP_RXDELAY_S1_FLAG HSL_RW - -#define SPI_EN "postrip_spi" -#define POSTRIP_SPI_EN_BOFFSET 25 -#define POSTRIP_SPI_EN_BLEN 1 -#define POSTRIP_SPI_EN_FLAG HSL_RW - -#define LED_OPEN_EN "postrip_led" -#define POSTRIP_LED_OPEN_EN_BOFFSET 24 -#define POSTRIP_LED_OPEN_EN_BLEN 1 -#define POSTRIP_LED_OPEN_EN_FLAG HSL_RW - -#define RXDELAY_S0 "postrip_rx_s0" -#define POSTRIP_RXDELAY_S0_BOFFSET 23 -#define POSTRIP_RXDELAY_S0_BLEN 1 -#define POSTRIP_RXDELAY_S0_FLAG HSL_RW - -#define TXDELAY_S1 "postrip_tx_s1" -#define POSTRIP_TXDELAY_S1_BOFFSET 22 -#define POSTRIP_TXDELAY_S1_BLEN 1 -#define POSTRIP_TXDELAY_S1_FLAG HSL_RW - -#define TXDELAY_S0 "postrip_tx_s0" -#define POSTRIP_TXDELAY_S0_BOFFSET 21 -#define POSTRIP_TXDELAY_S0_BLEN 1 -#define POSTRIP_TXDELAY_S0_FLAG HSL_RW - -#define LPW_EXIT "postrip_lpw_exit" -#define POSTRIP_LPW_EXIT_BOFFSET 20 -#define POSTRIP_LPW_EXIT_BLEN 1 -#define POSTRIP_LPW_EXIT_FLAG HSL_RW - -#define PHY_PLL_ON "postrip_phy_pll" -#define POSTRIP_PHY_PLL_ON_BOFFSET 19 -#define POSTRIP_PHY_PLL_ON_BLEN 1 -#define POSTRIP_PHY_PLL_ON_FLAG HSL_RW - -#define MAN_ENABLE "postrip_man_en" -#define POSTRIP_MAN_ENABLE_BOFFSET 18 -#define POSTRIP_MAN_ENABLE_BLEN 1 -#define POSTRIP_MAN_ENABLE_FLAG HSL_RW - -#define LPW_STATE_EN "postrip_lpw_state" -#define POSTRIP_LPW_STATE_EN_BOFFSET 17 -#define POSTRIP_LPW_STATE_EN_BLEN 1 -#define POSTRIP_LPW_STATE_EN_FLAG HSL_RW - -#define POWER_DOWN_HW "postrip_power_down" -#define POSTRIP_POWER_DOWN_HW_BOFFSET 16 -#define POSTRIP_POWER_DOWN_HW_BLEN 1 -#define POSTRIP_POWER_DOWN_HW_FLAG HSL_RW - -#define MAC5_PHY_MODE "postrip_mac5_phy" -#define POSTRIP_MAC5_PHY_MODE_BOFFSET 15 -#define POSTRIP_MAC5_PHY_MODE_BLEN 1 -#define POSTRIP_MAC5_PHY_MODE_FLAG HSL_RW - -#define MAC5_MAC_MODE "postrip_mac5_mac" -#define POSTRIP_MAC5_MAC_MODE_BOFFSET 14 -#define POSTRIP_MAC5_MAC_MODE_BLEN 1 -#define POSTRIP_MAC5_MAC_MODE_FLAG HSL_RW - -#define DBG_MODE_I "postrip_dbg" -#define POSTRIP_DBG_MODE_I_BOFFSET 13 -#define POSTRIP_DBG_MODE_I_BLEN 1 -#define POSTRIP_DBG_MODE_I_FLAG HSL_RW - -#define HIB_PULSE_HW "postrip_hib" -#define POSTRIP_HIB_PULSE_HW_BOFFSET 12 -#define POSTRIP_HIB_PULSE_HW_BLEN 1 -#define POSTRIP_HIB_PULSE_HW_FLAG HSL_RW - -#define SEL_CLK25M "postrip_clk25" -#define POSTRIP_SEL_CLK25M_BOFFSET 11 -#define POSTRIP_SEL_CLK25M_BLEN 1 -#define POSTRIP_SEL_CLK25M_FLAG HSL_RW - -#define GATE_25M_EN "postrip_gate25" -#define POSTRIP_GATE_25M_EN_BOFFSET 10 -#define POSTRIP_GATE_25M_EN_BLEN 1 -#define POSTRIP_GATE_25M_EN_FLAG HSL_RW - -#define SEL_ANA_RST "postrip_sel_ana" -#define POSTRIP_SEL_ANA_RST_BOFFSET 9 -#define POSTRIP_SEL_ANA_RST_BLEN 1 -#define POSTRIP_SEL_ANA_RST_FLAG HSL_RW - -#define SERDES_EN "postrip_serdes_en" -#define POSTRIP_SERDES_EN_BOFFSET 8 -#define POSTRIP_SERDES_EN_BLEN 1 -#define POSTRIP_SERDES_EN_FLAG HSL_RW - -#define RGMII_TXCLK_DELAY_EN "postrip_tx_delay" -#define POSTRIP_RGMII_TXCLK_DELAY_EN_BOFFSET 7 -#define POSTRIP_RGMII_TXCLK_DELAY_EN_BLEN 1 -#define POSTRIP_RGMII_TXCLK_DELAY_EN_FLAG HSL_RW - -#define RGMII_RXCLK_DELAY_EN "postrip_rx_delay" -#define POSTRIP_RGMII_RXCLK_DELAY_EN_BOFFSET 6 -#define POSTRIP_RGMII_RXCLK_DELAY_EN_BLEN 1 -#define POSTRIP_RGMII_RXCLK_DELAY_EN_FLAG HSL_RW - -#define RTL_MODE "postrip_rtl" -#define POSTRIP_RTL_MODE_BOFFSET 5 -#define POSTRIP_RTL_MODE_BLEN 1 -#define POSTRIP_RTL_MODE_FLAG HSL_RW - -#define MAC0_MAC_MODE "postrip_mac0_mac" -#define POSTRIP_MAC0_MAC_MODE_BOFFSET 4 -#define POSTRIP_MAC0_MAC_MODE_BLEN 1 -#define POSTRIP_MAC0_MAC_MODE_FLAG HSL_RW - -#define PHY4_RGMII_EN "postrip_phy4_rgmii" -#define POSTRIP_PHY4_RGMII_EN_BOFFSET 3 -#define POSTRIP_PHY4_RGMII_EN_BLEN 1 -#define POSTRIP_PHY4_RGMII_EN_FLAG HSL_RW - -#define PHY4_GMII_EN "postrip_phy4_gmii" -#define POSTRIP_PHY4_GMII_EN_BOFFSET 2 -#define POSTRIP_PHY4_GMII_EN_BLEN 1 -#define POSTRIP_PHY4_GMII_EN_FLAG HSL_RW - -#define MAC0_RGMII_EN "postrip_mac0_rgmii" -#define POSTRIP_MAC0_RGMII_EN_BOFFSET 1 -#define POSTRIP_MAC0_RGMII_EN_BLEN 1 -#define POSTRIP_MAC0_RGMII_EN_FLAG HSL_RW - -#define MAC0_GMII_EN "postrip_mac0_gmii" -#define POSTRIP_MAC0_GMII_EN_BOFFSET 0 -#define POSTRIP_MAC0_GMII_EN_BLEN 1 -#define POSTRIP_MAC0_GMII_EN_FLAG HSL_RW - - - - /* Global Interrupt Register */ -#define GLOBAL_INT "gint" -#define GLOBAL_INT_ID 1 -#define GLOBAL_INT_OFFSET 0x0014 -#define GLOBAL_INT_E_LENGTH 4 -#define GLOBAL_INT_E_OFFSET 0 -#define GLOBAL_INT_NR_E 1 - -#define GLB_QM_ERR_CNT "gint_qmen" -#define GLOBAL_INT_GLB_QM_ERR_CNT_BOFFSET 24 -#define GLOBAL_INT_GLB_QM_ERR_CNT_BLEN 8 -#define GLOBAL_INT_GLB_QM_ERR_CNT_FLAG HSL_RO - -#define GLB_LOOKUP_ERR "gint_glblper" -#define GLOBAL_INT_GLB_LOOKUP_ERR_BOFFSET 17 -#define GLOBAL_INT_GLB_LOOKUP_ERR_BLEN 1 -#define GLOBAL_INT_GLB_LOOKUP_ERR_FLAG HSL_RW - -#define GLB_QM_ERR "gint_glbqmer" -#define GLOBAL_INT_GLB_QM_ERR_BOFFSET 16 -#define GLOBAL_INT_GLB_QM_ERR_BLEN 1 -#define GLOBAL_INT_GLB_QM_ERR_FLAG HSL_RW - -#define GLB_HW_INI_DONE "gint_hwid" -#define GLOBAL_INT_GLB_HW_INI_DONE_BOFFSET 14 -#define GLOBAL_INT_GLB_HW_INI_DONE_BLEN 1 -#define GLOBAL_INT_GLB_HW_INI_DONE_FLAG HSL_RW - -#define GLB_MIB_INI "gint_mibi" -#define GLOBAL_INT_GLB_MIB_INI_BOFFSET 13 -#define GLOBAL_INT_GLB_MIB_INI_BLEN 1 -#define GLOBAL_INT_GLB_MIB_INI_FLAG HSL_RW - -#define GLB_MIB_DONE "gint_mibd" -#define GLOBAL_INT_GLB_MIB_DONE_BOFFSET 12 -#define GLOBAL_INT_GLB_MIB_DONE_BLEN 1 -#define GLOBAL_INT_GLB_MIB_DONE_FLAG HSL_RW - -#define GLB_BIST_DONE "gint_bisd" -#define GLOBAL_INT_GLB_BIST_DONE_BOFFSET 11 -#define GLOBAL_INT_GLB_BIST_DONE_BLEN 1 -#define GLOBAL_INT_GLB_BIST_DONE_FLAG HSL_RW - -#define GLB_VT_MISS_VIO "gint_vtms" -#define GLOBAL_INT_GLB_VT_MISS_VIO_BOFFSET 10 -#define GLOBAL_INT_GLB_VT_MISS_VIO_BLEN 1 -#define GLOBAL_INT_GLB_VT_MISS_VIO_FLAG HSL_RW - -#define GLB_VT_MEM_VIO "gint_vtme" -#define GLOBAL_INT_GLB_VT_MEM_VIO_BOFFSET 9 -#define GLOBAL_INT_GLB_VT_MEM_VIO_BLEN 1 -#define GLOBAL_INT_GLB_VT_MEM_VIO_FLAG HSL_RW - -#define GLB_VT_DONE "gint_vtd" -#define GLOBAL_INT_GLB_VT_DONE_BOFFSET 8 -#define GLOBAL_INT_GLB_VT_DONE_BLEN 1 -#define GLOBAL_INT_GLB_VT_DONE_FLAG HSL_RW - -#define GLB_QM_INI "gint_qmin" -#define GLOBAL_INT_GLB_QM_INI_BOFFSET 7 -#define GLOBAL_INT_GLB_QM_INI_BLEN 1 -#define GLOBAL_INT_GLB_QM_INI_FLAG HSL_RW - -#define GLB_AT_INI "gint_atin" -#define GLOBAL_INT_GLB_AT_INI_BOFFSET 6 -#define GLOBAL_INT_GLB_AT_INI_BLEN 1 -#define GLOBAL_INT_GLB_AT_INI_FLAG HSL_RW - -#define GLB_ARL_FULL "gint_arlf" -#define GLOBAL_INT_GLB_ARL_FULL_BOFFSET 5 -#define GLOBAL_INT_GLB_ARL_FULL_BLEN 1 -#define GLOBAL_INT_GLB_ARL_FULL_FLAG HSL_RW - -#define GLB_ARL_DONE "gint_arld" -#define GLOBAL_INT_GLB_ARL_DONE_BOFFSET 4 -#define GLOBAL_INT_GLB_ARL_DONE_BLEN 1 -#define GLOBAL_INT_GLB_ARL_DONE_FLAG HSL_RW - -#define GLB_MDIO_DONE "gint_mdid" -#define GLOBAL_INT_GLB_MDIO_DONE_BOFFSET 3 -#define GLOBAL_INT_GLB_MDIO_DONE_BLEN 1 -#define GLOBAL_INT_GLB_MDIO_DONE_FLAG HSL_RW - -#define GLB_PHY_INT "gint_phyi" -#define GLOBAL_INT_GLB_PHY_INT_BOFFSET 2 -#define GLOBAL_INT_GLB_PHY_INT_BLEN 1 -#define GLOBAL_INT_GLB_PHY_INT_FLAG HSL_RW - -#define GLB_EEPROM_ERR "gint_epei" -#define GLOBAL_INT_GLB_EEPROM_ERR_BOFFSET 1 -#define GLOBAL_INT_GLB_EEPROM_ERR_BLEN 1 -#define GLOBAL_INT_GLB_EEPROM_ERR_FLAG HSL_RW - -#define GLB_EEPROM_INT "gint_epi" -#define GLOBAL_INT_GLB_EEPROM_INT_BOFFSET 0 -#define GLOBAL_INT_GLB_EEPROM_INT_BLEN 1 -#define GLOBAL_INT_GLB_EEPROM_INT_FLAG HSL_RW - - - /* Global Interrupt Mask Register */ -#define GLOBAL_INT_MASK "gintm" -#define GLOBAL_INT_MASK_ID 2 -#define GLOBAL_INT_MASK_OFFSET 0x0018 -#define GLOBAL_INT_MASK_E_LENGTH 4 -#define GLOBAL_INT_MASK_E_OFFSET 0 -#define GLOBAL_INT_MASK_NR_E 1 - -#define GLBM_LOOP_CHECK "gintm_lc" -#define GLOBAL_INT_MASK_GLBM_LOOP_CHECK_BOFFSET 18 -#define GLOBAL_INT_MASK_GLBM_LOOP_CHECK_BLEN 1 -#define GLOBAL_INT_MASK_GLBM_LOOP_CHECK_FLAG HSL_RW - -#define GLBM_LOOKUP_ERR "gintm_lpe" -#define GLOBAL_INT_MASK_GLBM_LOOKUP_ERR_BOFFSET 17 -#define GLOBAL_INT_MASK_GLBM_LOOKUP_ERR_BLEN 1 -#define GLOBAL_INT_MASK_GLBM_LOOKUP_ERR_FLAG HSL_RW - -#define GLBM_QM_ERR "gintm_qme" -#define GLOBAL_INT_MASK_GLBM_QM_ERR_BOFFSET 16 -#define GLOBAL_INT_MASK_GLBM_QM_ERR_BLEN 1 -#define GLOBAL_INT_MASK_GLBM_QM_ERR_FLAG HSL_RW - -#define GLBM_HW_INI_DONE "gintm_hwid" -#define GLOBAL_INT_MASK_GLBM_HW_INI_DONE_BOFFSET 14 -#define GLOBAL_INT_MASK_GLBM_HW_INI_DONE_BLEN 1 -#define GLOBAL_INT_MASK_GLBM_HW_INI_DONE_FLAG HSL_RW - -#define GLBM_MIB_INI "gintm_mibi" -#define GLOBAL_INT_MASK_GLBM_MIB_INI_BOFFSET 13 -#define GLOBAL_INT_MASK_GLBM_MIB_INI_BLEN 1 -#define GLOBAL_INT_MASK_GLBM_MIB_INI_FLAG HSL_RW - -#define GLBM_MIB_DONE "gintm_mibd" -#define GLOBAL_INT_MASK_GLBM_MIB_DONE_BOFFSET 12 -#define GLOBAL_INT_MASK_GLBM_MIB_DONE_BLEN 1 -#define GLOBAL_INT_MASK_GLBM_MIB_DONE_FLAG HSL_RW - -#define GLBM_BIST_DONE "gintm_bisd" -#define GLOBAL_INT_MASK_GLBM_BIST_DONE_BOFFSET 11 -#define GLOBAL_INT_MASK_GLBM_BIST_DONE_BLEN 1 -#define GLOBAL_INT_MASK_GLBM_BIST_DONE_FLAG HSL_RW - -#define GLBM_VT_MISS_VIO "gintm_vtms" -#define GLOBAL_INT_MASK_GLBM_VT_MISS_VIO_BOFFSET 10 -#define GLOBAL_INT_MASK_GLBM_VT_MISS_VIO_BLEN 1 -#define GLOBAL_INT_MASK_GLBM_VT_MISS_VIO_FLAG HSL_RW - -#define GLBM_VT_MEM_VIO "gintm_vtme" -#define GLOBAL_INT_MASK_GLBM_VT_MEM_VIO_BOFFSET 9 -#define GLOBAL_INT_MASK_GLBM_VT_MEM_VIO_BLEN 1 -#define GLOBAL_INT_MASK_GLBM_VT_MEM_VIO_FLAG HSL_RW - -#define GLBM_VT_DONE "gintm_vtd" -#define GLOBAL_INT_MASK_GLBM_VT_DONE_BOFFSET 8 -#define GLOBAL_INT_MASK_GLBM_VT_DONE_BLEN 1 -#define GLOBAL_INT_MASK_GLBM_VT_DONE_FLAG HSL_RW - -#define GLBM_QM_INI "gintm_qmin" -#define GLOBAL_INT_MASK_GLBM_QM_INI_BOFFSET 7 -#define GLOBAL_INT_MASK_GLBM_QM_INI_BLEN 1 -#define GLOBAL_INT_MASK_GLBM_QM_INI_FLAG HSL_RW - -#define GLBM_AT_INI "gintm_atin" -#define GLOBAL_INT_MASK_GLBM_AT_INI_BOFFSET 6 -#define GLOBAL_INT_MASK_GLBM_AT_INI_BLEN 1 -#define GLOBAL_INT_MASK_GLBM_AT_INI_FLAG HSL_RW - -#define GLBM_ARL_FULL "gintm_arlf" -#define GLOBAL_INT_MASK_GLBM_ARL_FULL_BOFFSET 5 -#define GLOBAL_INT_MASK_GLBM_ARL_FULL_BLEN 1 -#define GLOBAL_INT_MASK_GLBM_ARL_FULL_FLAG HSL_RW - -#define GLBM_ARL_DONE "gintm_arld" -#define GLOBAL_INT_MASK_GLBM_ARL_DONE_BOFFSET 4 -#define GLOBAL_INT_MASK_GLBM_ARL_DONE_BLEN 1 -#define GLOBAL_INT_MASK_GLBM_ARL_DONE_FLAG HSL_RW - -#define GLBM_MDIO_DONE "gintm_mdid" -#define GLOBAL_INT_MASK_GLBM_MDIO_DONE_BOFFSET 3 -#define GLOBAL_INT_MASK_GLBM_MDIO_DONE_BLEN 1 -#define GLOBAL_INT_MASK_GLBM_MDIO_DONE_FLAG HSL_RW - -#define GLBM_PHY_INT "gintm_phy" -#define GLOBAL_INT_MASK_GLBM_PHY_INT_BOFFSET 2 -#define GLOBAL_INT_MASK_GLBM_PHY_INT_BLEN 1 -#define GLOBAL_INT_MASK_GLBM_PHY_INT_FLAG HSL_RW - -#define GLBM_EEPROM_ERR "gintm_epe" -#define GLOBAL_INT_MASK_GLBM_EEPROM_ERR_BOFFSET 1 -#define GLOBAL_INT_MASK_GLBM_EEPROM_ERR_BLEN 1 -#define GLOBAL_INT_MASK_GLBM_EEPROM_ERR_FLAG HSL_RW - -#define GLBM_EEPROM_INT "gintm_ep" -#define GLOBAL_INT_MASK_GLBM_EEPROM_INT_BOFFSET 0 -#define GLOBAL_INT_MASK_GLBM_EEPROM_INT_BLEN 1 -#define GLOBAL_INT_MASK_GLBM_EEPROM_INT_FLAG HSL_RW - - - /* Global MAC Address Register */ -#define GLOBAL_MAC_ADDR0 "gmac0" -#define GLOBAL_MAC_ADDR0_ID 3 -#define GLOBAL_MAC_ADDR0_OFFSET 0x0020 -#define GLOBAL_MAC_ADDR0_E_LENGTH 4 -#define GLOBAL_MAC_ADDR0_E_OFFSET 0 -#define GLOBAL_MAC_ADDR0_NR_E 1 - -#define GLB_BYTE4 "gmac_b4" -#define GLOBAL_MAC_ADDR0_GLB_BYTE4_BOFFSET 8 -#define GLOBAL_MAC_ADDR0_GLB_BYTE4_BLEN 8 -#define GLOBAL_MAC_ADDR0_GLB_BYTE4_FLAG HSL_RW - -#define GLB_BYTE5 "gmac_b5" -#define GLOBAL_MAC_ADDR0_GLB_BYTE5_BOFFSET 0 -#define GLOBAL_MAC_ADDR0_GLB_BYTE5_BLEN 8 -#define GLOBAL_MAC_ADDR0_GLB_BYTE5_FLAG HSL_RW - -#define GLOBAL_MAC_ADDR1 "gmac1" -#define GLOBAL_MAC_ADDR1_ID 4 -#define GLOBAL_MAC_ADDR1_OFFSET 0x0024 -#define GLOBAL_MAC_ADDR1_E_LENGTH 4 -#define GLOBAL_MAC_ADDR1_E_OFFSET 0 -#define GLOBAL_MAC_ADDR1_NR_E 1 - -#define GLB_BYTE0 "gmac_b0" -#define GLOBAL_MAC_ADDR1_GLB_BYTE0_BOFFSET 24 -#define GLOBAL_MAC_ADDR1_GLB_BYTE0_BLEN 8 -#define GLOBAL_MAC_ADDR1_GLB_BYTE0_FLAG HSL_RW - -#define GLB_BYTE1 "gmac_b1" -#define GLOBAL_MAC_ADDR1_GLB_BYTE1_BOFFSET 16 -#define GLOBAL_MAC_ADDR1_GLB_BYTE1_BLEN 8 -#define GLOBAL_MAC_ADDR1_GLB_BYTE1_FLAG HSL_RW - -#define GLB_BYTE2 "gmac_b2" -#define GLOBAL_MAC_ADDR1_GLB_BYTE2_BOFFSET 8 -#define GLOBAL_MAC_ADDR1_GLB_BYTE2_BLEN 8 -#define GLOBAL_MAC_ADDR1_GLB_BYTE2_FLAG HSL_RW - -#define GLB_BYTE3 "gmac_b3" -#define GLOBAL_MAC_ADDR1_GLB_BYTE3_BOFFSET 0 -#define GLOBAL_MAC_ADDR1_GLB_BYTE3_BLEN 8 -#define GLOBAL_MAC_ADDR1_GLB_BYTE3_FLAG HSL_RW - - - /* Flood Mask Register */ -#define LOOP_CHECK "loopc" -#define LOOP_CHECK_ID 4 -#define LOOP_CHECK_OFFSET 0x0028 -#define LOOP_CHECK_E_LENGTH 4 -#define LOOP_CHECK_E_OFFSET 0 -#define LOOP_CHECK_NR_E 1 - -#define NEW_PORT -#define LOOP_CHECK_NEW_PORT_BOFFSET 4 -#define LOOP_CHECK_NEW_PORT_BLEN 4 -#define LOOP_CHECK_NEW_PORT_FLAG HSL_RW - -#define OLD_PORT -#define LOOP_CHECK_OLD_PORT_BOFFSET 0 -#define LOOP_CHECK_OLD_PORT_BLEN 4 -#define LOOP_CHECK_OLD_PORT_FLAG HSL_RW - - - /* Flood Mask Register */ -#define FLOOD_MASK "fmask" -#define FLOOD_MASK_ID 5 -#define FLOOD_MASK_OFFSET 0x002c -#define FLOOD_MASK_E_LENGTH 4 -#define FLOOD_MASK_E_OFFSET 0 -#define FLOOD_MASK_NR_E 1 - -#define BC_FLOOD_DP "fmask_bfdp" -#define FLOOD_MASK_BC_FLOOD_DP_BOFFSET 25 -#define FLOOD_MASK_BC_FLOOD_DP_BLEN 7 -#define FLOOD_MASK_BC_FLOOD_DP_FLAG HSL_RW - -#define ARL_UNI_LEAKY "fmask_aulky" -#define FLOOD_MASK_ARL_UNI_LEAKY_BOFFSET 24 -#define FLOOD_MASK_ARL_UNI_LEAKY_BLEN 1 -#define FLOOD_MASK_ARL_UNI_LEAKY_FLAG HSL_RW - -#define ARL_MUL_LEAKY "fmask_amlky" -#define FLOOD_MASK_ARL_MUL_LEAKY_BOFFSET 23 -#define FLOOD_MASK_ARL_MUL_LEAKY_BLEN 1 -#define FLOOD_MASK_ARL_MUL_LEAKY_FLAG HSL_RW - -#define MUL_FLOOD_DP "fmask_mfdp" -#define FLOOD_MASK_MUL_FLOOD_DP_BOFFSET 16 -#define FLOOD_MASK_MUL_FLOOD_DP_BLEN 7 -#define FLOOD_MASK_MUL_FLOOD_DP_FLAG HSL_RW - -#define IGMP_DP "fmask_igmpdp" -#define FLOOD_MASK_IGMP_DP_BOFFSET 8 -#define FLOOD_MASK_IGMP_DP_BLEN 7 -#define FLOOD_MASK_IGMP_DP_FLAG HSL_RW - -#define UNI_FLOOD_DP "fmask_ufdp" -#define FLOOD_MASK_UNI_FLOOD_DP_BOFFSET 0 -#define FLOOD_MASK_UNI_FLOOD_DP_BLEN 7 -#define FLOOD_MASK_UNI_FLOOD_DP_FLAG HSL_RW - - - /* Global Control Register */ -#define GLOBAL_CTL "gctl" -#define GLOBAL_CTL_ID 5 -#define GLOBAL_CTL_OFFSET 0x0030 -#define GLOBAL_CTL_E_LENGTH 4 -#define GLOBAL_CTL_E_OFFSET 0 -#define GLOBAL_CTL_NR_E 1 - -#define RATE_DROP_EN "gctl_rden" -#define GLOBAL_CTL_RATE_DROP_EN_BOFFSET 29 -#define GLOBAL_CTL_RATE_DROP_EN_BLEN 1 -#define GLOBAL_CTL_RATE_DROP_EN_FLAG HSL_RW - -#define QM_PRI_MODE "gctl_qmpm" -#define GLOBAL_CTL_QM_PRI_MODE_BOFFSET 28 -#define GLOBAL_CTL_QM_PRI_MODE_BLEN 1 -#define GLOBAL_CTL_QM_PRI_MODE_FLAG HSL_RW - -#define RATE_CRE_LIMIT "gctl_rcrl" -#define GLOBAL_CTL_RATE_CRE_LIMIT_BOFFSET 26 -#define GLOBAL_CTL_RATE_CRE_LIMIT_BLEN 2 -#define GLOBAL_CTL_RATE_CRE_LIMIT_FLAG HSL_RW - -#define RATE_TIME_SLOT "gctl_rtms" -#define GLOBAL_CTL_RATE_TIME_SLOT_BOFFSET 24 -#define GLOBAL_CTL_RATE_TIME_SLOT_BLEN 2 -#define GLOBAL_CTL_RATE_TIME_SLOT_FLAG HSL_RW - -#define RELOAD_TIMER "gctl_rdtm" -#define GLOBAL_CTL_RELOAD_TIMER_BOFFSET 20 -#define GLOBAL_CTL_RELOAD_TIMER_BLEN 4 -#define GLOBAL_CTL_RELOAD_TIMER_FLAG HSL_RW - -#define QM_CNT_LOCK "gctl_qmcl" -#define GLOBAL_CTL_QM_CNT_LOCK_BOFFSET 19 -#define GLOBAL_CTL_QM_CNT_LOCK_BLEN 1 -#define GLOBAL_CTL_QM_CNT_LOCK_FLAG HSL_RO - -#define BROAD_DROP_EN "gctl_bden" -#define GLOBAL_CTL_BROAD_DROP_EN_BOFFSET 18 -#define GLOBAL_CTL_BROAD_DROP_EN_BLEN 1 -#define GLOBAL_CTL_BROAD_DROP_EN_FLAG HSL_RW - -#define MAX_FRAME_SIZE "gctl_mfsz" -#define GLOBAL_CTL_MAX_FRAME_SIZE_BOFFSET 0 -#define GLOBAL_CTL_MAX_FRAME_SIZE_BLEN 14 -#define GLOBAL_CTL_MAX_FRAME_SIZE_FLAG HSL_RW - - - /* Flow Control Register */ -#define FLOW_CTL0 "fctl" -#define FLOW_CTL0_ID 6 -#define FLOW_CTL0_OFFSET 0x0034 -#define FLOW_CTL0_E_LENGTH 4 -#define FLOW_CTL0_E_OFFSET 0 -#define FLOW_CTL0_NR_E 1 - -#define TEST_PAUSE "fctl_tps" -#define FLOW_CTL0_TEST_PAUSE_BOFFSET 31 -#define FLOW_CTL0_TEST_PAUSE_BLEN 1 -#define FLOW_CTL0_TEST_PAUSE_FLAG HSL_RW - - -#define GOL_PAUSE_ON_THRES "fctl_gont" -#define FLOW_CTL0_GOL_PAUSE_ON_THRES_BOFFSET 16 -#define FLOW_CTL0_GOL_PAUSE_ON_THRES_BLEN 8 -#define FLOW_CTL0_GOL_PAUSE_ON_THRES_FLAG HSL_RW - -#define GOL_PAUSE_OFF_THRES "fctl_gofft" -#define FLOW_CTL0_GOL_PAUSE_OFF_THRES_BOFFSET 0 -#define FLOW_CTL0_GOL_PAUSE_OFF_THRES_BLEN 8 -#define FLOW_CTL0_GOL_PAUSE_OFF_THRES_FLAG HSL_RW - - - - - /* Flow Control1 Register */ -#define FLOW_CTL1 "fctl1" -#define FLOW_CTL1_ID 6 -#define FLOW_CTL1_OFFSET 0x0038 -#define FLOW_CTL1_E_LENGTH 4 -#define FLOW_CTL1_E_OFFSET 0 -#define FLOW_CTL1_NR_E 1 - -#define PORT_PAUSE_ON_THRES "fctl1_pont" -#define FLOW_CTL1_PORT_PAUSE_ON_THRES_BOFFSET 16 -#define FLOW_CTL1_PORT_PAUSE_ON_THRES_BLEN 8 -#define FLOW_CTL1_PORT_PAUSE_ON_THRES_FLAG HSL_RW - -#define PORT_PAUSE_OFF_THRES "fctl1_pofft" -#define FLOW_CTL1_PORT_PAUSE_OFF_THRES_BOFFSET 0 -#define FLOW_CTL1_PORT_PAUSE_OFF_THRES_BLEN 8 -#define FLOW_CTL1_PORT_PAUSE_OFF_THRES_FLAG HSL_RW - - - - - /* QM Control Register */ -#define QM_CTL "qmct" -#define QM_CTL_ID 7 -#define QM_CTL_OFFSET 0x003c -#define QM_CTL_E_LENGTH 4 -#define QM_CTL_E_OFFSET 0 -#define QM_CTL_NR_E 1 - -#define QM_ERR_RST_EN "qmct_qeren" -#define QM_CTL_QM_ERR_RST_EN_BOFFSET 31 -#define QM_CTL_QM_ERR_RST_EN_BLEN 1 -#define QM_CTL_QM_ERR_RST_EN_FLAG HSL_RW - -#define LOOKUP_ERR_RST_EN "qmct_lpesen" -#define QM_CTL_LOOKUP_ERR_RST_EN_BOFFSET 30 -#define QM_CTL_LOOKUP_ERR_RST_EN_BLEN 1 -#define QM_CTL_LOOKUP_ERR_RST_EN_FLAG HSL_RW - -#define IGMP_JOIN_STATIC "qmct_igmpjs" -#define QM_CTL_IGMP_JOIN_STATIC_BOFFSET 24 -#define QM_CTL_IGMP_JOIN_STATIC_BLEN 4 -#define QM_CTL_IGMP_JOIN_STATIC_FLAG HSL_RW - -#define IGMP_JOIN_LEAKY "qmct_igmpjl" -#define QM_CTL_IGMP_JOIN_LEAKY_BOFFSET 23 -#define QM_CTL_IGMP_JOIN_LEAKY_BLEN 1 -#define QM_CTL_IGMP_JOIN_LEAKY_FLAG HSL_RW - -#define IGMP_CREAT_EN "qmct_igmpcrt" -#define QM_CTL_IGMP_CREAT_EN_BOFFSET 22 -#define QM_CTL_IGMP_CREAT_EN_BLEN 1 -#define QM_CTL_IGMP_CREAT_EN_FLAG HSL_RW - -#define ACL_EN "qmct_aclen" -#define QM_CTL_ACL_EN_BOFFSET 21 -#define QM_CTL_ACL_EN_BLEN 1 -#define QM_CTL_ACL_EN_FLAG HSL_RW - -#define PPPOE_RDT_EN "qmct_pppoerdten" -#define QM_CTL_PPPOE_RDT_EN_BOFFSET 20 -#define QM_CTL_PPPOE_RDT_EN_BLEN 1 -#define QM_CTL_PPPOE_RDT_EN_FLAG HSL_RW - -#define IGMP_V3_EN "qmct_igmpv3e" -#define QM_CTL_IGMP_V3_EN_BOFFSET 19 -#define QM_CTL_IGMP_V3_EN_BLEN 1 -#define QM_CTL_IGMP_V3_EN_FLAG HSL_RW - -#define IGMP_PRI_EN "qmct_igmpprie" -#define QM_CTL_IGMP_PRI_EN_BOFFSET 18 -#define QM_CTL_IGMP_PRI_EN_BLEN 1 -#define QM_CTL_IGMP_PRI_EN_FLAG HSL_RW - -#define IGMP_PRI "qmct_igmppri" -#define QM_CTL_IGMP_PRI_BOFFSET 16 -#define QM_CTL_IGMP_PRI_BLEN 2 -#define QM_CTL_IGMP_PRI_FLAG HSL_RW - -#define ARP_EN "qmct_arpe" -#define QM_CTL_ARP_EN_BOFFSET 15 -#define QM_CTL_ARP_EN_BLEN 1 -#define QM_CTL_ARP_EN_FLAG HSL_RW - -#define ARP_CMD "qmct_arpc" -#define QM_CTL_ARP_CMD_BOFFSET 14 -#define QM_CTL_ARP_CMD_BLEN 1 -#define QM_CTL_ARP_CMD_FLAG HSL_RW - -#define RIP_CPY_EN "qmct_ripcpyen" -#define QM_CTL_RIP_CPY_EN_BOFFSET 13 -#define QM_CTL_RIP_CPY_EN_BLEN 1 -#define QM_CTL_RIP_CPY_EN_FLAG HSL_RW - -#define EAPOL_CMD "qmct_eapolc" -#define QM_CTL_EAPOL_CMD_BOFFSET 12 -#define QM_CTL_EAPOL_CMD_BLEN 1 -#define QM_CTL_EAPOL_CMD_FLAG HSL_RW - -#define IGMP_COPY_EN "qmct_igmpcpy" -#define QM_CTL_IGMP_COPY_EN_BOFFSET 11 -#define QM_CTL_IGMP_COPY_EN_BLEN 1 -#define QM_CTL_IGMP_COPY_EN_FLAG HSL_RW - -#define PPPOE_EN "qmct_pppoeen" -#define QM_CTL_PPPOE_EN_BOFFSET 10 -#define QM_CTL_PPPOE_EN_BLEN 1 -#define QM_CTL_PPPOE_EN_FLAG HSL_RW - -#define QM_FUNC_TEST "qmct_qmft" -#define QM_CTL_QM_FUNC_TEST_BOFFSET 9 -#define QM_CTL_QM_FUNC_TEST_BLEN 1 -#define QM_CTL_QM_FUNC_TEST_FLAG HSL_RW - -#define MS_FC_EN "qmct_msfe" -#define QM_CTL_MS_FC_EN_BOFFSET 8 -#define QM_CTL_MS_FC_EN_BLEN 1 -#define QM_CTL_MS_FC_EN_FLAG HSL_RW - -#define FLOW_DROP_EN "qmct_fden" -#define QM_CTL_FLOW_DROP_EN_BOFFSET 7 -#define QM_CTL_FLOW_DROP_EN_BLEN 1 -#define QM_CTL_FLOW_DROP_EN_FLAG HSL_RW - -#define MANAGE_VID_VIO_DROP_EN "qmct_mden" -#define QM_CTL_MANAGE_VID_VIO_DROP_EN_BOFFSET 6 -#define QM_CTL_MANAGE_VID_VIO_DROP_EN_BLEN 1 -#define QM_CTL_MANAGE_VID_VIO_DROP_EN_FLAG HSL_RW - -#define FLOW_DROP_CNT "qmct_fdcn" -#define QM_CTL_FLOW_DROP_CNT_BOFFSET 0 -#define QM_CTL_FLOW_DROP_CNT_BLEN 6 -#define QM_CTL_FLOW_DROP_CNT_FLAG HSL_RW - - - /* Vlan Table Function Register */ -#define VLAN_TABLE_FUNC0 "vtbf0" -#define VLAN_TABLE_FUNC0_ID 9 -#define VLAN_TABLE_FUNC0_OFFSET 0x0040 -#define VLAN_TABLE_FUNC0_E_LENGTH 4 -#define VLAN_TABLE_FUNC0_E_OFFSET 0 -#define VLAN_TABLE_FUNC0_NR_E 1 - -#define VT_PRI_EN "vtbf_vtpen" -#define VLAN_TABLE_FUNC0_VT_PRI_EN_BOFFSET 31 -#define VLAN_TABLE_FUNC0_VT_PRI_EN_BLEN 1 -#define VLAN_TABLE_FUNC0_VT_PRI_EN_FLAG HSL_RW - -#define VT_PRI "vtbf_vtpri" -#define VLAN_TABLE_FUNC0_VT_PRI_BOFFSET 28 -#define VLAN_TABLE_FUNC0_VT_PRI_BLEN 3 -#define VLAN_TABLE_FUNC0_VT_PRI_FLAG HSL_RW - -#define VLAN_ID "vtbf_vid" -#define VLAN_TABLE_FUNC0_VLAN_ID_BOFFSET 16 -#define VLAN_TABLE_FUNC0_VLAN_ID_BLEN 12 -#define VLAN_TABLE_FUNC0_VLAN_ID_FLAG HSL_RW - -#define VT_PORT_NUM "vtbf_vtpn" -#define VLAN_TABLE_FUNC0_VT_PORT_NUM_BOFFSET 8 -#define VLAN_TABLE_FUNC0_VT_PORT_NUM_BLEN 4 -#define VLAN_TABLE_FUNC0_VT_PORT_NUM_FLAG HSL_RW - -#define VT_FULL_VIO "vtbf_vtflv" -#define VLAN_TABLE_FUNC0_VT_FULL_VIO_BOFFSET 4 -#define VLAN_TABLE_FUNC0_VT_FULL_VIO_BLEN 1 -#define VLAN_TABLE_FUNC0_VT_FULL_VIO_FLAG HSL_RW - -#define VT_BUSY "vtbf_vtbs" -#define VLAN_TABLE_FUNC0_VT_BUSY_BOFFSET 3 -#define VLAN_TABLE_FUNC0_VT_BUSY_BLEN 1 -#define VLAN_TABLE_FUNC0_VT_BUSY_FLAG HSL_RW - -#define VT_FUNC "vtbf_vtfc" -#define VLAN_TABLE_FUNC0_VT_FUNC_BOFFSET 0 -#define VLAN_TABLE_FUNC0_VT_FUNC_BLEN 3 -#define VLAN_TABLE_FUNC0_VT_FUNC_FLAG HSL_RW - -#define VLAN_TABLE_FUNC1 "vtbf1" -#define VLAN_TABLE_FUNC1_ID 10 -#define VLAN_TABLE_FUNC1_OFFSET 0x0044 -#define VLAN_TABLE_FUNC1_E_LENGTH 4 -#define VLAN_TABLE_FUNC1_E_OFFSET 0 -#define VLAN_TABLE_FUNC1_NR_E 1 - -#define VT_VALID "vtbf_vtvd" -#define VLAN_TABLE_FUNC1_VT_VALID_BOFFSET 11 -#define VLAN_TABLE_FUNC1_VT_VALID_BLEN 1 -#define VLAN_TABLE_FUNC1_VT_VALID_FLAG HSL_RW - -#define VID_MEM "vtbf_vidm" -#define VLAN_TABLE_FUNC1_VID_MEM_BOFFSET 0 -#define VLAN_TABLE_FUNC1_VID_MEM_BLEN 7 -#define VLAN_TABLE_FUNC1_VID_MEM_FLAG HSL_RW - - - /* Address Table Function Register */ -#define ADDR_TABLE_FUNC0 "atbf0" -#define ADDR_TABLE_FUNC0_ID 11 -#define ADDR_TABLE_FUNC0_OFFSET 0x0050 -#define ADDR_TABLE_FUNC0_E_LENGTH 4 -#define ADDR_TABLE_FUNC0_E_OFFSET 0 -#define ADDR_TABLE_FUNC0_NR_E 1 - -#define AT_ADDR_BYTE4 "atbf_adb4" -#define ADDR_TABLE_FUNC0_AT_ADDR_BYTE4_BOFFSET 24 -#define ADDR_TABLE_FUNC0_AT_ADDR_BYTE4_BLEN 8 -#define ADDR_TABLE_FUNC0_AT_ADDR_BYTE4_FLAG HSL_RW - -#define AT_ADDR_BYTE5 "atbf_adb5" -#define ADDR_TABLE_FUNC0_AT_ADDR_BYTE5_BOFFSET 16 -#define ADDR_TABLE_FUNC0_AT_ADDR_BYTE5_BLEN 8 -#define ADDR_TABLE_FUNC0_AT_ADDR_BYTE5_FLAG HSL_RW - -#define AT_FULL_VIO "atbf_atfv" -#define ADDR_TABLE_FUNC0_AT_FULL_VIO_BOFFSET 12 -#define ADDR_TABLE_FUNC0_AT_FULL_VIO_BLEN 1 -#define ADDR_TABLE_FUNC0_AT_FULL_VIO_FLAG HSL_RW - -#define AT_PORT_NUM "atbf_atpn" -#define ADDR_TABLE_FUNC0_AT_PORT_NUM_BOFFSET 8 -#define ADDR_TABLE_FUNC0_AT_PORT_NUM_BLEN 4 -#define ADDR_TABLE_FUNC0_AT_PORT_NUM_FLAG HSL_RW - -#define FLUSH_ST_EN "atbf_fsen" -#define ADDR_TABLE_FUNC0_FLUSH_ST_EN_BOFFSET 4 -#define ADDR_TABLE_FUNC0_FLUSH_ST_EN_BLEN 1 -#define ADDR_TABLE_FUNC0_FLUSH_ST_EN_FLAG HSL_RW - -#define AT_BUSY "atbf_atbs" -#define ADDR_TABLE_FUNC0_AT_BUSY_BOFFSET 3 -#define ADDR_TABLE_FUNC0_AT_BUSY_BLEN 1 -#define ADDR_TABLE_FUNC0_AT_BUSY_FLAG HSL_RW - -#define AT_FUNC "atbf_atfc" -#define ADDR_TABLE_FUNC0_AT_FUNC_BOFFSET 0 -#define ADDR_TABLE_FUNC0_AT_FUNC_BLEN 3 -#define ADDR_TABLE_FUNC0_AT_FUNC_FLAG HSL_RW - -#define ADDR_TABLE_FUNC1 "atbf1" -#define ADDR_TABLE_FUNC1_ID 12 -#define ADDR_TABLE_FUNC1_OFFSET 0x0054 -#define ADDR_TABLE_FUNC1_E_LENGTH 4 -#define ADDR_TABLE_FUNC1_E_OFFSET 0 -#define ADDR_TABLE_FUNC1_NR_E 0 - -#define AT_ADDR_BYTE0 "atbf_adb0" -#define ADDR_TABLE_FUNC1_AT_ADDR_BYTE0_BOFFSET 24 -#define ADDR_TABLE_FUNC1_AT_ADDR_BYTE0_BLEN 8 -#define ADDR_TABLE_FUNC1_AT_ADDR_BYTE0_FLAG HSL_RW - -#define AT_ADDR_BYTE1 "atbf_adb1" -#define ADDR_TABLE_FUNC1_AT_ADDR_BYTE1_BOFFSET 16 -#define ADDR_TABLE_FUNC1_AT_ADDR_BYTE1_BLEN 8 -#define ADDR_TABLE_FUNC1_AT_ADDR_BYTE1_FLAG HSL_RW - -#define AT_ADDR_BYTE2 "atbf_adb2" -#define ADDR_TABLE_FUNC1_AT_ADDR_BYTE2_BOFFSET 8 -#define ADDR_TABLE_FUNC1_AT_ADDR_BYTE2_BLEN 8 -#define ADDR_TABLE_FUNC1_AT_ADDR_BYTE2_FLAG HSL_RW - -#define AT_ADDR_BYTE3 "atbf_adb3" -#define ADDR_TABLE_FUNC1_AT_ADDR_BYTE3_BOFFSET 0 -#define ADDR_TABLE_FUNC1_AT_ADDR_BYTE3_BLEN 8 -#define ADDR_TABLE_FUNC1_AT_ADDR_BYTE3_FLAG HSL_RW - -#define ADDR_TABLE_FUNC2 "atbf2" -#define ADDR_TABLE_FUNC2_ID 13 -#define ADDR_TABLE_FUNC2_OFFSET 0x0058 -#define ADDR_TABLE_FUNC2_E_LENGTH 4 -#define ADDR_TABLE_FUNC2_E_OFFSET 0 -#define ADDR_TABLE_FUNC2_NR_E 0 - -#define COPY_TO_CPU "atbf_cpcpu" -#define ADDR_TABLE_FUNC2_COPY_TO_CPU_BOFFSET 26 -#define ADDR_TABLE_FUNC2_COPY_TO_CPU_BLEN 1 -#define ADDR_TABLE_FUNC2_COPY_TO_CPU_FLAG HSL_RW - -#define REDRCT_TO_CPU "atbf_rdcpu" -#define ADDR_TABLE_FUNC2_REDRCT_TO_CPU_BOFFSET 25 -#define ADDR_TABLE_FUNC2_REDRCT_TO_CPU_BLEN 1 -#define ADDR_TABLE_FUNC2_REDRCT_TO_CPU_FLAG HSL_RW - -#define LEAKY_EN "atbf_lkyen" -#define ADDR_TABLE_FUNC2_LEAKY_EN_BOFFSET 24 -#define ADDR_TABLE_FUNC2_LEAKY_EN_BLEN 1 -#define ADDR_TABLE_FUNC2_LEAKY_EN_FLAG HSL_RW - -#define AT_STATUS "atbf_atsts" -#define ADDR_TABLE_FUNC2_AT_STATUS_BOFFSET 16 -#define ADDR_TABLE_FUNC2_AT_STATUS_BLEN 4 -#define ADDR_TABLE_FUNC2_AT_STATUS_FLAG HSL_RW - -#define CLONE_EN "atbf_clone" -#define ADDR_TABLE_FUNC2_CLONE_EN_BOFFSET 15 -#define ADDR_TABLE_FUNC2_CLONE_EN_BLEN 1 -#define ADDR_TABLE_FUNC2_CLONE_EN_FLAG HSL_RW - -#define SA_DROP_EN "atbf_saden" -#define ADDR_TABLE_FUNC2_SA_DROP_EN_BOFFSET 14 -#define ADDR_TABLE_FUNC2_SA_DROP_EN_BLEN 1 -#define ADDR_TABLE_FUNC2_SA_DROP_EN_FLAG HSL_RW - -#define MIRROR_EN "atbf_miren" -#define ADDR_TABLE_FUNC2_MIRROR_EN_BOFFSET 13 -#define ADDR_TABLE_FUNC2_MIRROR_EN_BLEN 1 -#define ADDR_TABLE_FUNC2_MIRROR_EN_FLAG HSL_RW - -#define AT_PRI_EN "atbf_atpen" -#define ADDR_TABLE_FUNC2_AT_PRI_EN_BOFFSET 12 -#define ADDR_TABLE_FUNC2_AT_PRI_EN_BLEN 1 -#define ADDR_TABLE_FUNC2_AT_PRI_EN_FLAG HSL_RW - -#define AT_PRI "atbf_atpri" -#define ADDR_TABLE_FUNC2_AT_PRI_BOFFSET 10 -#define ADDR_TABLE_FUNC2_AT_PRI_BLEN 2 -#define ADDR_TABLE_FUNC2_AT_PRI_FLAG HSL_RW - -#define CROSS_PT "atbf_cpt" -#define ADDR_TABLE_FUNC2_CROSS_PT_BOFFSET 8 -#define ADDR_TABLE_FUNC2_CROSS_PT_BLEN 1 -#define ADDR_TABLE_FUNC2_CROSS_PT_FLAG HSL_RW - -#define DES_PORT "atbf_desp" -#define ADDR_TABLE_FUNC2_DES_PORT_BOFFSET 0 -#define ADDR_TABLE_FUNC2_DES_PORT_BLEN 7 -#define ADDR_TABLE_FUNC2_DES_PORT_FLAG HSL_RW - - - /* FDB entry Register0 */ -#define FDB_TABLE_FUNC0 "fdb0" -#define FDB_TABLE_FUNC0_ID 11 -#define FDB_TABLE_FUNC0_OFFSET 0x30000 -#define FDB_TABLE_FUNC0_E_LENGTH 4 -#define FDB_TABLE_FUNC0_E_OFFSET 0 -#define FDB_TABLE_FUNC0_NR_E 1 - -#define FDB_ADDR_BYTE2 -#define FDB_TABLE_FUNC0_FDB_ADDR_BYTE2_BOFFSET 24 -#define FDB_TABLE_FUNC0_FDB_ADDR_BYTE2_BLEN 8 -#define FDB_TABLE_FUNC0_FDB_ADDR_BYTE2_FLAG HSL_RW - -#define FDB_ADDR_BYTE3 -#define FDB_TABLE_FUNC0_FDB_ADDR_BYTE3_BOFFSET 16 -#define FDB_TABLE_FUNC0_FDB_ADDR_BYTE3_BLEN 8 -#define FDB_TABLE_FUNC0_FDB_ADDR_BYTE3_FLAG HSL_RW - -#define FDB_ADDR_BYTE4 -#define FDB_TABLE_FUNC0_FDB_ADDR_BYTE4_BOFFSET 8 -#define FDB_TABLE_FUNC0_FDB_ADDR_BYTE4_BLEN 8 -#define FDB_TABLE_FUNC0_FDB_ADDR_BYTE4_FLAG HSL_RW - -#define FDB_ADDR_BYTE5 -#define FDB_TABLE_FUNC0_FDB_ADDR_BYTE5_BOFFSET 0 -#define FDB_TABLE_FUNC0_FDB_ADDR_BYTE5_BLEN 8 -#define FDB_TABLE_FUNC0_FDB_ADDR_BYTE5_FLAG HSL_RW - - - /* FDB entry Register1 */ -#define FDB_TABLE_FUNC1 "fdb1" -#define FDB_TABLE_FUNC1_ID 11 -#define FDB_TABLE_FUNC1_OFFSET 0x30004 -#define FDB_TABLE_FUNC1_E_LENGTH 4 -#define FDB_TABLE_FUNC1_E_OFFSET 0 -#define FDB_TABLE_FUNC1_NR_E 1 - -#define FDB_MACCLONE_EN -#define FDB_TABLE_FUNC1_FDB_MACCLONE_EN_BOFFSET 31 -#define FDB_TABLE_FUNC1_FDB_MACCLONE_EN_BLEN 1 -#define FDB_TABLE_FUNC1_FDB_MACCLONE_EN_FLAG HSL_RW - -#define FDB_SADROP_EN -#define FDB_TABLE_FUNC1_FDB_SADROP_EN_BOFFSET 30 -#define FDB_TABLE_FUNC1_FDB_SADROP_EN_BLEN 1 -#define FDB_TABLE_FUNC1_FDB_SADROP_EN_FLAG HSL_RW - -#define FDB_MIRROR_EN -#define FDB_TABLE_FUNC1_FDB_MIRROR_EN_BOFFSET 29 -#define FDB_TABLE_FUNC1_FDB_MIRROR_EN_BLEN 1 -#define FDB_TABLE_FUNC1_FDB_MIRROR_EN_FLAG HSL_RW - -#define FDB_PRIORITY_EN -#define FDB_TABLE_FUNC1_FDB_PRIORITY_EN_BOFFSET 28 -#define FDB_TABLE_FUNC1_FDB_PRIORITY_EN_BLEN 1 -#define FDB_TABLE_FUNC1_FDB_PRIORITY_EN_FLAG HSL_RW - -#define FDB_PRIORITY -#define FDB_TABLE_FUNC1_FDB_PRIORITY_BOFFSET 26 -#define FDB_TABLE_FUNC1_FDB_PRIORITY_BLEN 2 -#define FDB_TABLE_FUNC1_FDB_PRIORITY_FLAG HSL_RW - -#define FDB_CROSS_STATE -#define FDB_TABLE_FUNC1_FDB_CROSS_STATE_BOFFSET 24 -#define FDB_TABLE_FUNC1_FDB_CROSS_STATE_BLEN 1 -#define FDB_TABLE_FUNC1_FDB_CROSS_STATE_FLAG HSL_RW - -#define FDB_DES_PORT -#define FDB_TABLE_FUNC1_FDB_DES_PORT_BOFFSET 16 -#define FDB_TABLE_FUNC1_FDB_DES_PORT_BLEN 7 -#define FDB_TABLE_FUNC1_FDB_DES_PORT_FLAG HSL_RW - -#define FDB_ADDR_BYTE0 -#define FDB_TABLE_FUNC1_FDB_ADDR_BYTE0_BOFFSET 8 -#define FDB_TABLE_FUNC1_FDB_ADDR_BYTE0_BLEN 8 -#define FDB_TABLE_FUNC1_FDB_ADDR_BYTE0_FLAG HSL_RW - -#define FDB_ADDR_BYTE1 -#define FDB_TABLE_FUNC1_FDB_ADDR_BYTE1_BOFFSET 0 -#define FDB_TABLE_FUNC1_FDB_ADDR_BYTE1_BLEN 8 -#define FDB_TABLE_FUNC1_FDB_ADDR_BYTE1_FLAG HSL_RW - - - /* FDB entry Register2 */ -#define FDB_TABLE_FUNC2 "fdb2" -#define FDB_TABLE_FUNC2_ID 11 -#define FDB_TABLE_FUNC2_OFFSET 0x30008 -#define FDB_TABLE_FUNC2_E_LENGTH 4 -#define FDB_TABLE_FUNC2_E_OFFSET 0 -#define FDB_TABLE_FUNC2_NR_E 1 - -#define FDB_CPYCPU_EN -#define FDB_TABLE_FUNC2_FDB_CPYCPU_EN_BOFFSET 6 -#define FDB_TABLE_FUNC2_FDB_CPYCPU_EN_BLEN 1 -#define FDB_TABLE_FUNC2_FDB_CPYCPU_EN_FLAG HSL_RW - -#define FDB_RDTCPU_EN -#define FDB_TABLE_FUNC2_FDB_RDTCPU_EN_BOFFSET 5 -#define FDB_TABLE_FUNC2_FDB_RDTCPU_EN_BLEN 1 -#define FDB_TABLE_FUNC2_FDB_RDTCPU_EN_FLAG HSL_RW - -#define FDB_LEANKY_EN -#define FDB_TABLE_FUNC2_FDB_LEANKY_EN_BOFFSET 4 -#define FDB_TABLE_FUNC2_FDB_LEANKY_EN_BLEN 1 -#define FDB_TABLE_FUNC2_FDB_LEANKY_EN_FLAG HSL_RW - -#define FDB_STATUS -#define FDB_TABLE_FUNC2_FDB_STATUS_BOFFSET 0 -#define FDB_TABLE_FUNC2_FDB_STATUS_BLEN 4 -#define FDB_TABLE_FUNC2_FDB_STATUS_FLAG HSL_RW - - - /* Address Table Control Register */ -#define ADDR_TABLE_CTL "atbc" -#define ADDR_TABLE_CTL_ID 14 -#define ADDR_TABLE_CTL_OFFSET 0x005C -#define ADDR_TABLE_CTL_E_LENGTH 4 -#define ADDR_TABLE_CTL_E_OFFSET 0 -#define ADDR_TABLE_CTL_NR_E 1 - -#define LOOP_CHK_TIME "atbc_lctime" -#define ADDR_TABLE_CTL_LOOP_CHK_TIME_BOFFSET 24 -#define ADDR_TABLE_CTL_LOOP_CHK_TIME_BLEN 3 -#define ADDR_TABLE_CTL_LOOP_CHK_TIME_FLAG HSL_RW - -#define RESVID_DROP "atbc_rviddrop" -#define ADDR_TABLE_CTL_RESVID_DROP_BOFFSET 22 -#define ADDR_TABLE_CTL_RESVID_DROP_BLEN 1 -#define ADDR_TABLE_CTL_RESVID_DROP_FLAG HSL_RW - -#define STAG_MODE "atbc_stag" -#define ADDR_TABLE_CTL_STAG_MODE_BOFFSET 21 -#define ADDR_TABLE_CTL_STAG_MODE_BLEN 1 -#define ADDR_TABLE_CTL_STAG_MODE_FLAG HSL_RW - -#define ARL_INI_EN "atbc_arlie" -#define ADDR_TABLE_CTL_ARL_INI_EN_BOFFSET 19 -#define ADDR_TABLE_CTL_ARL_INI_EN_BLEN 1 -#define ADDR_TABLE_CTL_ARL_INI_EN_FLAG HSL_RW - -#define LEARN_CHANGE_EN "atbc_lcen" -#define ADDR_TABLE_CTL_LEARN_CHANGE_EN_BOFFSET 18 -#define ADDR_TABLE_CTL_LEARN_CHANGE_EN_BLEN 1 -#define ADDR_TABLE_CTL_LEARN_CHANGE_EN_FLAG HSL_RW - -#define AGE_EN "atbc_agee" -#define ADDR_TABLE_CTL_AGE_EN_BOFFSET 17 -#define ADDR_TABLE_CTL_AGE_EN_BLEN 1 -#define ADDR_TABLE_CTL_AGE_EN_FLAG HSL_RW - -#define AGE_TIME "atbc_aget" -#define ADDR_TABLE_CTL_AGE_TIME_BOFFSET 0 -#define ADDR_TABLE_CTL_AGE_TIME_BLEN 16 -#define ADDR_TABLE_CTL_AGE_TIME_FLAG HSL_RW - - - /* IP Priority Mapping Register */ -#define IP_PRI_MAPPING "imap" -#define IP_PRI_MAPPING_ID 15 -#define IP_PRI_MAPPING_OFFSET 0x0060 -#define IP_PRI_MAPPING_E_LENGTH 4 -#define IP_PRI_MAPPING_E_OFFSET 0 -#define IP_PRI_MAPPING_NR_E 1 - - - /* IP Priority Mapping Register */ -#define IP_PRI_MAPPING0 "imap0" -#define IP_PRI_MAPPING0_ID 15 -#define IP_PRI_MAPPING0_OFFSET 0x0060 -#define IP_PRI_MAPPING0_E_LENGTH 4 -#define IP_PRI_MAPPING0_E_OFFSET 0 -#define IP_PRI_MAPPING0_NR_E 0 - -#define IP_0X3C "imap_ip3c" -#define IP_PRI_MAPPING0_IP_0X3C_BOFFSET 30 -#define IP_PRI_MAPPING0_IP_0X3C_BLEN 2 -#define IP_PRI_MAPPING0_IP_0X3C_FLAG HSL_RW - -#define IP_0X38 "imap_ip38" -#define IP_PRI_MAPPING0_IP_0X38_BOFFSET 28 -#define IP_PRI_MAPPING0_IP_0X38_BLEN 2 -#define IP_PRI_MAPPING0_IP_0X38_FLAG HSL_RW - -#define IP_0X34 "imap_ip34" -#define IP_PRI_MAPPING0_IP_0X34_BOFFSET 26 -#define IP_PRI_MAPPING0_IP_0X34_BLEN 2 -#define IP_PRI_MAPPING0_IP_0X34_FLAG HSL_RW - -#define IP_0X30 "imap_ip30" -#define IP_PRI_MAPPING0_IP_0X30_BOFFSET 24 -#define IP_PRI_MAPPING0_IP_0X30_BLEN 2 -#define IP_PRI_MAPPING0_IP_0X30_FLAG HSL_RW - -#define IP_0X2C "imap_ip2c" -#define IP_PRI_MAPPING0_IP_0X2C_BOFFSET 22 -#define IP_PRI_MAPPING0_IP_0X2C_BLEN 2 -#define IP_PRI_MAPPING0_IP_0X2C_FLAG HSL_RW - -#define IP_0X28 "imap_ip28" -#define IP_PRI_MAPPING0_IP_0X28_BOFFSET 20 -#define IP_PRI_MAPPING0_IP_0X28_BLEN 2 -#define IP_PRI_MAPPING0_IP_0X28_FLAG HSL_RW - -#define IP_0X24 "imap_ip24" -#define IP_PRI_MAPPING0_IP_0X24_BOFFSET 18 -#define IP_PRI_MAPPING0_IP_0X24_BLEN 2 -#define IP_PRI_MAPPING0_IP_0X24_FLAG HSL_RW - -#define IP_0X20 "imap_ip20" -#define IP_PRI_MAPPING0_IP_0X20_BOFFSET 16 -#define IP_PRI_MAPPING0_IP_0X20_BLEN 2 -#define IP_PRI_MAPPING0_IP_0X20_FLAG HSL_RW - -#define IP_0X1C "imap_ip1c" -#define IP_PRI_MAPPING0_IP_0X1C_BOFFSET 14 -#define IP_PRI_MAPPING0_IP_0X1C_BLEN 2 -#define IP_PRI_MAPPING0_IP_0X1C_FLAG HSL_RW - -#define IP_0X18 "imap_ip18" -#define IP_PRI_MAPPING0_IP_0X18_BOFFSET 12 -#define IP_PRI_MAPPING0_IP_0X18_BLEN 2 -#define IP_PRI_MAPPING0_IP_0X18_FLAG HSL_RW - -#define IP_0X14 "imap_ip14" -#define IP_PRI_MAPPING0_IP_0X14_BOFFSET 10 -#define IP_PRI_MAPPING0_IP_0X14_BLEN 2 -#define IP_PRI_MAPPING0_IP_0X14_FLAG HSL_RW - -#define IP_0X10 "imap_ip10" -#define IP_PRI_MAPPING0_IP_0X10_BOFFSET 8 -#define IP_PRI_MAPPING0_IP_0X10_BLEN 2 -#define IP_PRI_MAPPING0_IP_0X10_FLAG HSL_RW - -#define IP_0X0C "imap_ip0c" -#define IP_PRI_MAPPING0_IP_0X0C_BOFFSET 6 -#define IP_PRI_MAPPING0_IP_0X0C_BLEN 2 -#define IP_PRI_MAPPING0_IP_0X0C_FLAG HSL_RW - -#define IP_0X08 "imap_ip08" -#define IP_PRI_MAPPING0_IP_0X08_BOFFSET 4 -#define IP_PRI_MAPPING0_IP_0X08_BLEN 2 -#define IP_PRI_MAPPING0_IP_0X08_FLAG HSL_RW - -#define IP_0X04 "imap_ip04" -#define IP_PRI_MAPPING0_IP_0X04_BOFFSET 2 -#define IP_PRI_MAPPING0_IP_0X04_BLEN 2 -#define IP_PRI_MAPPING0_IP_0X04_FLAG HSL_RW - -#define IP_0X00 "imap_ip00" -#define IP_PRI_MAPPING0_IP_0X00_BOFFSET 0 -#define IP_PRI_MAPPING0_IP_0X00_BLEN 2 -#define IP_PRI_MAPPING0_IP_0X00_FLAG HSL_RW - -#define IP_PRI_MAPPING1 "imap1" -#define IP_PRI_MAPPING1_ID 16 -#define IP_PRI_MAPPING1_OFFSET 0x0064 -#define IP_PRI_MAPPING1_E_LENGTH 4 -#define IP_PRI_MAPPING1_E_OFFSET 0 -#define IP_PRI_MAPPING1_NR_E 0 - -#define IP_0X7C "imap_ip7c" -#define IP_PRI_MAPPING1_IP_0X7C_BOFFSET 30 -#define IP_PRI_MAPPING1_IP_0X7C_BLEN 2 -#define IP_PRI_MAPPING1_IP_0X7C_FLAG HSL_RW - -#define IP_0X78 "imap_ip78" -#define IP_PRI_MAPPING1_IP_0X78_BOFFSET 28 -#define IP_PRI_MAPPING1_IP_0X78_BLEN 2 -#define IP_PRI_MAPPING1_IP_0X78_FLAG HSL_RW - -#define IP_0X74 "imap_ip74" -#define IP_PRI_MAPPING1_IP_0X74_BOFFSET 26 -#define IP_PRI_MAPPING1_IP_0X74_BLEN 2 -#define IP_PRI_MAPPING1_IP_0X74_FLAG HSL_RW - -#define IP_0X70 "imap_ip70" -#define IP_PRI_MAPPING1_IP_0X70_BOFFSET 24 -#define IP_PRI_MAPPING1_IP_0X70_BLEN 2 -#define IP_PRI_MAPPING1_IP_0X70_FLAG HSL_RW - -#define IP_0X6C "imap_ip6c" -#define IP_PRI_MAPPING1_IP_0X6C_BOFFSET 22 -#define IP_PRI_MAPPING1_IP_0X6C_BLEN 2 -#define IP_PRI_MAPPING1_IP_0X6C_FLAG HSL_RW - -#define IP_0X68 "imap_ip68" -#define IP_PRI_MAPPING1_IP_0X68_BOFFSET 20 -#define IP_PRI_MAPPING1_IP_0X68_BLEN 2 -#define IP_PRI_MAPPING1_IP_0X68_FLAG HSL_RW - -#define IP_0X64 "imap_ip64" -#define IP_PRI_MAPPING1_IP_0X64_BOFFSET 18 -#define IP_PRI_MAPPING1_IP_0X64_BLEN 2 -#define IP_PRI_MAPPING1_IP_0X64_FLAG HSL_RW - -#define IP_0X60 "imap_ip60" -#define IP_PRI_MAPPING1_IP_0X60_BOFFSET 16 -#define IP_PRI_MAPPING1_IP_0X60_BLEN 2 -#define IP_PRI_MAPPING1_IP_0X60_FLAG HSL_RW - -#define IP_0X5C "imap_ip5c" -#define IP_PRI_MAPPING1_IP_0X5C_BOFFSET 14 -#define IP_PRI_MAPPING1_IP_0X5C_BLEN 2 -#define IP_PRI_MAPPING1_IP_0X5C_FLAG HSL_RW - -#define IP_0X58 "imap_ip58" -#define IP_PRI_MAPPING1_IP_0X58_BOFFSET 12 -#define IP_PRI_MAPPING1_IP_0X58_BLEN 2 -#define IP_PRI_MAPPING1_IP_0X58_FLAG HSL_RW - -#define IP_0X54 "imap_ip54" -#define IP_PRI_MAPPING1_IP_0X54_BOFFSET 10 -#define IP_PRI_MAPPING1_IP_0X54_BLEN 2 -#define IP_PRI_MAPPING1_IP_0X54_FLAG HSL_RW - -#define IP_0X50 "imap_ip50" -#define IP_PRI_MAPPING1_IP_0X50_BOFFSET 8 -#define IP_PRI_MAPPING1_IP_0X50_BLEN 2 -#define IP_PRI_MAPPING1_IP_0X50_FLAG HSL_RW - -#define IP_0X4C "imap_ip4c" -#define IP_PRI_MAPPING1_IP_0X4C_BOFFSET 6 -#define IP_PRI_MAPPING1_IP_0X4C_BLEN 2 -#define IP_PRI_MAPPING1_IP_0X4C_FLAG HSL_RW - -#define IP_0X48 "imap_ip48" -#define IP_PRI_MAPPING1_IP_0X48_BOFFSET 4 -#define IP_PRI_MAPPING1_IP_0X48_BLEN 2 -#define IP_PRI_MAPPING1_IP_0X48_FLAG HSL_RW - -#define IP_0X44 "imap_ip44" -#define IP_PRI_MAPPING1_IP_0X44_BOFFSET 2 -#define IP_PRI_MAPPING1_IP_0X44_BLEN 2 -#define IP_PRI_MAPPING1_IP_0X44_FLAG HSL_RW - -#define IP_0X40 "imap_ip40" -#define IP_PRI_MAPPING1_IP_0X40_BOFFSET 0 -#define IP_PRI_MAPPING1_IP_0X40_BLEN 2 -#define IP_PRI_MAPPING1_IP_0X40_FLAG HSL_RW - - -#define IP_PRI_MAPPING2 "imap2" -#define IP_PRI_MAPPING2_ID 17 -#define IP_PRI_MAPPING2_OFFSET 0x0068 -#define IP_PRI_MAPPING2_E_LENGTH 4 -#define IP_PRI_MAPPING2_E_OFFSET 0 -#define IP_PRI_MAPPING2_NR_E 0 - -#define IP_0XBC "imap_ipbc" -#define IP_PRI_MAPPING2_IP_0XBC_BOFFSET 30 -#define IP_PRI_MAPPING2_IP_0XBC_BLEN 2 -#define IP_PRI_MAPPING2_IP_0XBC_FLAG HSL_RW - -#define IP_0XB8 "imap_ipb8" -#define IP_PRI_MAPPING2_IP_0XB8_BOFFSET 28 -#define IP_PRI_MAPPING2_IP_0XB8_BLEN 2 -#define IP_PRI_MAPPING2_IP_0XB8_FLAG HSL_RW - -#define IP_0XB4 "imap_ipb4" -#define IP_PRI_MAPPING2_IP_0XB4_BOFFSET 26 -#define IP_PRI_MAPPING2_IP_0XB4_BLEN 2 -#define IP_PRI_MAPPING2_IP_0XB4_FLAG HSL_RW - -#define IP_0XB0 "imap_ipb0" -#define IP_PRI_MAPPING2_IP_0XB0_BOFFSET 24 -#define IP_PRI_MAPPING2_IP_0XB0_BLEN 2 -#define IP_PRI_MAPPING2_IP_0XB0_FLAG HSL_RW - -#define IP_0XAC "imap_ipac" -#define IP_PRI_MAPPING2_IP_0XAC_BOFFSET 22 -#define IP_PRI_MAPPING2_IP_0XAC_BLEN 2 -#define IP_PRI_MAPPING2_IP_0XAC_FLAG HSL_RW - -#define IP_0XA8 "imap_ipa8" -#define IP_PRI_MAPPING2_IP_0XA8_BOFFSET 20 -#define IP_PRI_MAPPING2_IP_0XA8_BLEN 2 -#define IP_PRI_MAPPING2_IP_0XA8_FLAG HSL_RW - -#define IP_0XA4 "imap_ipa4" -#define IP_PRI_MAPPING2_IP_0XA4_BOFFSET 18 -#define IP_PRI_MAPPING2_IP_0XA4_BLEN 2 -#define IP_PRI_MAPPING2_IP_0XA4_FLAG HSL_RW - -#define IP_0XA0 "imap_ipa0" -#define IP_PRI_MAPPING2_IP_0XA0_BOFFSET 16 -#define IP_PRI_MAPPING2_IP_0XA0_BLEN 2 -#define IP_PRI_MAPPING2_IP_0XA0_FLAG HSL_RW - -#define IP_0X9C "imap_ip9c" -#define IP_PRI_MAPPING2_IP_0X9C_BOFFSET 14 -#define IP_PRI_MAPPING2_IP_0X9C_BLEN 2 -#define IP_PRI_MAPPING2_IP_0X9C_FLAG HSL_RW - -#define IP_0X98 "imap_ip98" -#define IP_PRI_MAPPING2_IP_0X98_BOFFSET 12 -#define IP_PRI_MAPPING2_IP_0X98_BLEN 2 -#define IP_PRI_MAPPING2_IP_0X98_FLAG HSL_RW - -#define IP_0X94 "imap_ip94" -#define IP_PRI_MAPPING2_IP_0X94_BOFFSET 10 -#define IP_PRI_MAPPING2_IP_0X94_BLEN 2 -#define IP_PRI_MAPPING2_IP_0X94_FLAG HSL_RW - -#define IP_0X90 "imap_ip90" -#define IP_PRI_MAPPING2_IP_0X90_BOFFSET 8 -#define IP_PRI_MAPPING2_IP_0X90_BLEN 2 -#define IP_PRI_MAPPING2_IP_0X90_FLAG HSL_RW - -#define IP_0X8C "imap_ip8c" -#define IP_PRI_MAPPING2_IP_0X8C_BOFFSET 6 -#define IP_PRI_MAPPING2_IP_0X8C_BLEN 2 -#define IP_PRI_MAPPING2_IP_0X8C_FLAG HSL_RW - -#define IP_0X88 "imap_ip88" -#define IP_PRI_MAPPING2_IP_0X88_BOFFSET 4 -#define IP_PRI_MAPPING2_IP_0X88_BLEN 2 -#define IP_PRI_MAPPING2_IP_0X88_FLAG HSL_RW - -#define IP_0X84 "imap_ip84" -#define IP_PRI_MAPPING2_IP_0X84_BOFFSET 2 -#define IP_PRI_MAPPING2_IP_0X84_BLEN 2 -#define IP_PRI_MAPPING2_IP_0X84_FLAG HSL_RW - -#define IP_0X80 "imap_ip80" -#define IP_PRI_MAPPING2_IP_0X80_BOFFSET 0 -#define IP_PRI_MAPPING2_IP_0X80_BLEN 2 -#define IP_PRI_MAPPING2_IP_0X80_FLAG HSL_RW - -#define IP_PRI_MAPPING3 "imap3" -#define IP_PRI_MAPPING3_ID 18 -#define IP_PRI_MAPPING3_OFFSET 0x006C -#define IP_PRI_MAPPING3_E_LENGTH 4 -#define IP_PRI_MAPPING3_E_OFFSET 0 -#define IP_PRI_MAPPING3_NR_E 0 - -#define IP_0XFC "imap_ipfc" -#define IP_PRI_MAPPING3_IP_0XFC_BOFFSET 30 -#define IP_PRI_MAPPING3_IP_0XFC_BLEN 2 -#define IP_PRI_MAPPING3_IP_0XFC_FLAG HSL_RW - -#define IP_0XF8 "imap_ipf8" -#define IP_PRI_MAPPING3_IP_0XF8_BOFFSET 28 -#define IP_PRI_MAPPING3_IP_0XF8_BLEN 2 -#define IP_PRI_MAPPING3_IP_0XF8_FLAG HSL_RW - -#define IP_0XF4 "imap_ipf4" -#define IP_PRI_MAPPING3_IP_0XF4_BOFFSET 26 -#define IP_PRI_MAPPING3_IP_0XF4_BLEN 2 -#define IP_PRI_MAPPING3_IP_0XF4_FLAG HSL_RW - -#define IP_0XF0 "imap_ipf0" -#define IP_PRI_MAPPING3_IP_0XF0_BOFFSET 24 -#define IP_PRI_MAPPING3_IP_0XF0_BLEN 2 -#define IP_PRI_MAPPING3_IP_0XF0_FLAG HSL_RW - -#define IP_0XEC "imap_ipec" -#define IP_PRI_MAPPING3_IP_0XEC_BOFFSET 22 -#define IP_PRI_MAPPING3_IP_0XEC_BLEN 2 -#define IP_PRI_MAPPING3_IP_0XEC_FLAG HSL_RW - -#define IP_0XE8 "imap_ipe8" -#define IP_PRI_MAPPING3_IP_0XE8_BOFFSET 20 -#define IP_PRI_MAPPING3_IP_0XE8_BLEN 2 -#define IP_PRI_MAPPING3_IP_0XE8_FLAG HSL_RW - -#define IP_0XE4 "imap_ipe4" -#define IP_PRI_MAPPING3_IP_0XE4_BOFFSET 18 -#define IP_PRI_MAPPING3_IP_0XE4_BLEN 2 -#define IP_PRI_MAPPING3_IP_0XE4_FLAG HSL_RW - -#define IP_0XE0 "imap_ipe0" -#define IP_PRI_MAPPING3_IP_0XE0_BOFFSET 16 -#define IP_PRI_MAPPING3_IP_0XE0_BLEN 2 -#define IP_PRI_MAPPING3_IP_0XE0_FLAG HSL_RW - -#define IP_0XDC "imap_ipdc" -#define IP_PRI_MAPPING3_IP_0XDC_BOFFSET 14 -#define IP_PRI_MAPPING3_IP_0XDC_BLEN 2 -#define IP_PRI_MAPPING3_IP_0XDC_FLAG HSL_RW - -#define IP_0XD8 "imap_ipd8" -#define IP_PRI_MAPPING3_IP_0XD8_BOFFSET 12 -#define IP_PRI_MAPPING3_IP_0XD8_BLEN 2 -#define IP_PRI_MAPPING3_IP_0XD8_FLAG HSL_RW - -#define IP_0XD4 "imap_ipd4" -#define IP_PRI_MAPPING3_IP_0XD4_BOFFSET 10 -#define IP_PRI_MAPPING3_IP_0XD4_BLEN 2 -#define IP_PRI_MAPPING3_IP_0XD4_FLAG HSL_RW - -#define IP_0XD0 "imap_ipd0" -#define IP_PRI_MAPPING3_IP_0XD0_BOFFSET 8 -#define IP_PRI_MAPPING3_IP_0XD0_BLEN 2 -#define IP_PRI_MAPPING3_IP_0XD0_FLAG HSL_RW - -#define IP_0XCC "imap_ipcc" -#define IP_PRI_MAPPING3_IP_0XCC_BOFFSET 6 -#define IP_PRI_MAPPING3_IP_0XCC_BLEN 2 -#define IP_PRI_MAPPING3_IP_0XCC_FLAG HSL_RW - -#define IP_0XC8 "imap_ipc8" -#define IP_PRI_MAPPING3_IP_0XC8_BOFFSET 4 -#define IP_PRI_MAPPING3_IP_0XC8_BLEN 2 -#define IP_PRI_MAPPING3_IP_0XC8_FLAG HSL_RW - -#define IP_0XC4 "imap_ipc4" -#define IP_PRI_MAPPING3_IP_0XC4_BOFFSET 2 -#define IP_PRI_MAPPING3_IP_0XC4_BLEN 2 -#define IP_PRI_MAPPING3_IP_0XC4_FLAG HSL_RW - -#define IP_0XC0 "imap_ipc0" -#define IP_PRI_MAPPING3_IP_0XC0_BOFFSET 0 -#define IP_PRI_MAPPING3_IP_0XC0_BLEN 2 -#define IP_PRI_MAPPING3_IP_0XC0_FLAG HSL_RW - - - /* Tag Priority Mapping Register */ -#define TAG_PRI_MAPPING "tpmap" -#define TAG_PRI_MAPPING_ID 19 -#define TAG_PRI_MAPPING_OFFSET 0x0070 -#define TAG_PRI_MAPPING_E_LENGTH 4 -#define TAG_PRI_MAPPING_E_OFFSET 0 -#define TAG_PRI_MAPPING_NR_E 1 - -#define TAG_0X07 "tpmap_tg07" -#define TAG_PRI_MAPPING_TAG_0X07_BOFFSET 14 -#define TAG_PRI_MAPPING_TAG_0X07_BLEN 2 -#define TAG_PRI_MAPPING_TAG_0X07_FLAG HSL_RW - -#define TAG_0X06 "tpmap_tg06" -#define TAG_PRI_MAPPING_TAG_0X06_BOFFSET 12 -#define TAG_PRI_MAPPING_TAG_0X06_BLEN 2 -#define TAG_PRI_MAPPING_TAG_0X06_FLAG HSL_RW - -#define TAG_0X05 "tpmap_tg05" -#define TAG_PRI_MAPPING_TAG_0X05_BOFFSET 10 -#define TAG_PRI_MAPPING_TAG_0X05_BLEN 2 -#define TAG_PRI_MAPPING_TAG_0X05_FLAG HSL_RW - -#define TAG_0X04 "tpmap_tg04" -#define TAG_PRI_MAPPING_TAG_0X04_BOFFSET 8 -#define TAG_PRI_MAPPING_TAG_0X04_BLEN 2 -#define TAG_PRI_MAPPING_TAG_0X04_FLAG HSL_RW - -#define TAG_0X03 "tpmap_tg03" -#define TAG_PRI_MAPPING_TAG_0X03_BOFFSET 6 -#define TAG_PRI_MAPPING_TAG_0X03_BLEN 2 -#define TAG_PRI_MAPPING_TAG_0X03_FLAG HSL_RW - -#define TAG_0X02 "tpmap_tg02" -#define TAG_PRI_MAPPING_TAG_0X02_BOFFSET 4 -#define TAG_PRI_MAPPING_TAG_0X02_BLEN 2 -#define TAG_PRI_MAPPING_TAG_0X02_FLAG HSL_RW - -#define TAG_0X01 "tpmap_tg01" -#define TAG_PRI_MAPPING_TAG_0X01_BOFFSET 2 -#define TAG_PRI_MAPPING_TAG_0X01_BLEN 2 -#define TAG_PRI_MAPPING_TAG_0X01_FLAG HSL_RW - -#define TAG_0X00 "tpmap_tg00" -#define TAG_PRI_MAPPING_TAG_0X00_BOFFSET 0 -#define TAG_PRI_MAPPING_TAG_0X00_BLEN 2 -#define TAG_PRI_MAPPING_TAG_0X00_FLAG HSL_RW - - - /* Service tag Register */ -#define SERVICE_TAG "servicetag" -#define SERVICE_TAG_ID 20 -#define SERVICE_TAG_OFFSET 0x0074 -#define SERVICE_TAG_E_LENGTH 4 -#define SERVICE_TAG_E_OFFSET 0 -#define SERVICE_TAG_NR_E 1 - -#define TAG_VALUE "servicetag_val" -#define SERVICE_TAG_TAG_VALUE_BOFFSET 0 -#define SERVICE_TAG_TAG_VALUE_BLEN 16 -#define SERVICE_TAG_TAG_VALUE_FLAG HSL_RW - - - /* Cpu Port Register */ -#define CPU_PORT "cpup" -#define CPU_PORT_ID 20 -#define CPU_PORT_OFFSET 0x0078 -#define CPU_PORT_E_LENGTH 4 -#define CPU_PORT_E_OFFSET 0 -#define CPU_PORT_NR_E 0 - -#define CPU_PORT_EN "cpup_cpupe" -#define CPU_PORT_CPU_PORT_EN_BOFFSET 8 -#define CPU_PORT_CPU_PORT_EN_BLEN 1 -#define CPU_PORT_CPU_PORT_EN_FLAG HSL_RW - -#define MIRROR_PORT_NUM "cpup_mirpn" -#define CPU_PORT_MIRROR_PORT_NUM_BOFFSET 4 -#define CPU_PORT_MIRROR_PORT_NUM_BLEN 4 -#define CPU_PORT_MIRROR_PORT_NUM_FLAG HSL_RW - - - /* MIB Function Register */ -#define MIB_FUNC "mibfunc" -#define MIB_FUNC_ID 21 -#define MIB_FUNC_OFFSET 0x0080 -#define MIB_FUNC_E_LENGTH 4 -#define MIB_FUNC_E_OFFSET 0 -#define MIB_FUNC_NR_E 1 - -#define MAC_CRC_EN "mibfunc_crcen" -#define MIB_FUNC_MAC_CRC_EN_BOFFSET 31 -#define MIB_FUNC_MAC_CRC_EN_BLEN 1 -#define MIB_FUNC_MAC_CRC_EN_FLAG HSL_RW - -#define MIB_EN "mib_en" -#define MIB_FUNC_MIB_EN_BOFFSET 30 -#define MIB_FUNC_MIB_EN_BLEN 1 -#define MIB_FUNC_MIB_EN_FLAG HSL_RW - -#define MIB_FUN "mibfunc_mibf" -#define MIB_FUNC_MIB_FUN_BOFFSET 24 -#define MIB_FUNC_MIB_FUN_BLEN 3 -#define MIB_FUNC_MIB_FUN_FLAG HSL_RW - -#define MIB_BUSY "mibfunc_mibb" -#define MIB_FUNC_MIB_BUSY_BOFFSET 17 -#define MIB_FUNC_MIB_BUSY_BLEN 1 -#define MIB_FUNC_MIB_BUSY_FLAG HSL_RW - -#define MIB_AT_HALF_EN "mibfunc_mibhe" -#define MIB_FUNC_MIB_AT_HALF_EN_BOFFSET 16 -#define MIB_FUNC_MIB_AT_HALF_EN_BLEN 1 -#define MIB_FUNC_MIB_AT_HALF_EN_FLAG HSL_RW - -#define MIB_TIMER "mibfunc_mibt" -#define MIB_FUNC_MIB_TIMER_BOFFSET 0 -#define MIB_FUNC_MIB_TIMER_BLEN 16 -#define MIB_FUNC_MIB_TIMER_FLAG HSL_RW - - - /* Mdio control Register */ -#define MDIO_CTRL "mctrl" -#define MDIO_CTRL_ID 24 -#define MDIO_CTRL_OFFSET 0x0098 -#define MDIO_CTRL_E_LENGTH 4 -#define MDIO_CTRL_E_OFFSET 0 -#define MDIO_CTRL_NR_E 1 - -#define MSTER_EN "mctrl_msteren" -#define MDIO_CTRL_MSTER_EN_BOFFSET 30 -#define MDIO_CTRL_MSTER_EN_BLEN 1 -#define MDIO_CTRL_MSTER_EN_FLAG HSL_RW - -#define MSTER_EN "mctrl_msteren" -#define MDIO_CTRL_MSTER_EN_BOFFSET 30 -#define MDIO_CTRL_MSTER_EN_BLEN 1 -#define MDIO_CTRL_MSTER_EN_FLAG HSL_RW - -#define CMD "mctrl_cmd" -#define MDIO_CTRL_CMD_BOFFSET 27 -#define MDIO_CTRL_CMD_BLEN 1 -#define MDIO_CTRL_CMD_FLAG HSL_RW - -#define SUP_PRE "mctrl_spre" -#define MDIO_CTRL_SUP_PRE_BOFFSET 26 -#define MDIO_CTRL_SUP_PRE_BLEN 1 -#define MDIO_CTRL_SUP_PRE_FLAG HSL_RW - -#define PHY_ADDR "mctrl_phyaddr" -#define MDIO_CTRL_PHY_ADDR_BOFFSET 21 -#define MDIO_CTRL_PHY_ADDR_BLEN 5 -#define MDIO_CTRL_PHY_ADDR_FLAG HSL_RW - -#define REG_ADDR "mctrl_regaddr" -#define MDIO_CTRL_REG_ADDR_BOFFSET 16 -#define MDIO_CTRL_REG_ADDR_BLEN 5 -#define MDIO_CTRL_REG_ADDR_FLAG HSL_RW - -#define DATA "mctrl_data" -#define MDIO_CTRL_DATA_BOFFSET 0 -#define MDIO_CTRL_DATA_BLEN 16 -#define MDIO_CTRL_DATA_FLAG HSL_RW - - - - - /* BIST control Register */ -#define BIST_CTRL "bctrl" -#define BIST_CTRL_ID 24 -#define BIST_CTRL_OFFSET 0x00a0 -#define BIST_CTRL_E_LENGTH 4 -#define BIST_CTRL_E_OFFSET 0 -#define BIST_CTRL_NR_E 1 - -#define BIST_BUSY "bctrl_bb" -#define BIST_CTRL_BIST_BUSY_BOFFSET 31 -#define BIST_CTRL_BIST_BUSY_BLEN 1 -#define BIST_CTRL_BIST_BUSY_FLAG HSL_RW - -#define ONE_ERR "bctrl_oe" -#define BIST_CTRL_ONE_ERR_BOFFSET 30 -#define BIST_CTRL_ONE_ERR_BLEN 1 -#define BIST_CTRL_ONE_ERR_FLAG HSL_RO - -#define ERR_MEM "bctrl_em" -#define BIST_CTRL_ERR_MEM_BOFFSET 24 -#define BIST_CTRL_ERR_MEM_BLEN 4 -#define BIST_CTRL_ERR_MEM_FLAG HSL_RO - -#define PTN_EN2 "bctrl_pe2" -#define BIST_CTRL_PTN_EN2_BOFFSET 22 -#define BIST_CTRL_PTN_EN2_BLEN 1 -#define BIST_CTRL_PTN_EN2_FLAG HSL_RW - -#define PTN_EN1 "bctrl_pe1" -#define BIST_CTRL_PTN_EN1_BOFFSET 21 -#define BIST_CTRL_PTN_EN1_BLEN 1 -#define BIST_CTRL_PTN_EN1_FLAG HSL_RW - -#define PTN_EN0 "bctrl_pe0" -#define BIST_CTRL_PTN_EN0_BOFFSET 20 -#define BIST_CTRL_PTN_EN0_BLEN 1 -#define BIST_CTRL_PTN_EN0_FLAG HSL_RW - -#define ERR_PTN "bctrl_ep" -#define BIST_CTRL_ERR_PTN_BOFFSET 16 -#define BIST_CTRL_ERR_PTN_BLEN 2 -#define BIST_CTRL_ERR_PTN_FLAG HSL_RO - -#define ERR_CNT "bctrl_ec" -#define BIST_CTRL_ERR_CNT_BOFFSET 13 -#define BIST_CTRL_ERR_CNT_BLEN 2 -#define BIST_CTRL_ERR_CNT_FLAG HSL_RO - -#define ERR_ADDR "bctrl_ea" -#define BIST_CTRL_ERR_ADDR_BOFFSET 0 -#define BIST_CTRL_ERR_ADDR_BLEN 12 -#define BIST_CTRL_ERR_ADDR_FLAG HSL_RO - - - - - /* BIST recover Register */ -#define BIST_RCV "brcv" -#define BIST_RCV_ID 24 -#define BIST_RCV_OFFSET 0x00a4 -#define BIST_RCV_E_LENGTH 4 -#define BIST_RCV_E_OFFSET 0 -#define BIST_RCV_NR_E 1 - -#define RCV_EN "brcv_en" -#define BIST_RCV_RCV_EN_BOFFSET 31 -#define BIST_RCV_RCV_EN_BLEN 1 -#define BIST_RCV_RCV_EN_FLAG HSL_RW - -#define RCV_ADDR "brcv_addr" -#define BIST_RCV_RCV_ADDR_BOFFSET 0 -#define BIST_RCV_RCV_ADDR_BLEN 12 -#define BIST_RCV_RCV_ADDR_FLAG HSL_RW - - - - - /* LED control Register */ -#define LED_CTRL "ledctrl" -#define LED_CTRL_ID 25 -#define LED_CTRL_OFFSET 0x00b0 -#define LED_CTRL_E_LENGTH 4 -#define LED_CTRL_E_OFFSET 0 -#define LED_CTRL_NR_E 1 - -#define PATTERN_EN "lctrl_pen" -#define LED_CTRL_PATTERN_EN_BOFFSET 14 -#define LED_CTRL_PATTERN_EN_BLEN 2 -#define LED_CTRL_PATTERN_EN_FLAG HSL_RW - -#define FULL_LIGHT_EN "lctrl_fen" -#define LED_CTRL_FULL_LIGHT_EN_BOFFSET 13 -#define LED_CTRL_FULL_LIGHT_EN_BLEN 1 -#define LED_CTRL_FULL_LIGHT_EN_FLAG HSL_RW - -#define HALF_LIGHT_EN "lctrl_hen" -#define LED_CTRL_HALF_LIGHT_EN_BOFFSET 12 -#define LED_CTRL_HALF_LIGHT_EN_BLEN 1 -#define LED_CTRL_HALF_LIGHT_EN_FLAG HSL_RW - -#define POWERON_LIGHT_EN "lctrl_poen" -#define LED_CTRL_POWERON_LIGHT_EN_BOFFSET 11 -#define LED_CTRL_POWERON_LIGHT_EN_BLEN 1 -#define LED_CTRL_POWERON_LIGHT_EN_FLAG HSL_RW - -#define GE_LIGHT_EN "lctrl_geen" -#define LED_CTRL_GE_LIGHT_EN_BOFFSET 10 -#define LED_CTRL_GE_LIGHT_EN_BLEN 1 -#define LED_CTRL_GE_LIGHT_EN_FLAG HSL_RW - -#define FE_LIGHT_EN "lctrl_feen" -#define LED_CTRL_FE_LIGHT_EN_BOFFSET 9 -#define LED_CTRL_FE_LIGHT_EN_BLEN 1 -#define LED_CTRL_FE_LIGHT_EN_FLAG HSL_RW - -#define ETH_LIGHT_EN "lctrl_ethen" -#define LED_CTRL_ETH_LIGHT_EN_BOFFSET 8 -#define LED_CTRL_ETH_LIGHT_EN_BLEN 1 -#define LED_CTRL_ETH_LIGHT_EN_FLAG HSL_RW - -#define COL_BLINK_EN "lctrl_cen" -#define LED_CTRL_COL_BLINK_EN_BOFFSET 7 -#define LED_CTRL_COL_BLINK_EN_BLEN 1 -#define LED_CTRL_COL_BLINK_EN_FLAG HSL_RW - -#define RX_BLINK_EN "lctrl_rxen" -#define LED_CTRL_RX_BLINK_EN_BOFFSET 5 -#define LED_CTRL_RX_BLINK_EN_BLEN 1 -#define LED_CTRL_RX_BLINK_EN_FLAG HSL_RW - -#define TX_BLINK_EN "lctrl_txen" -#define LED_CTRL_TX_BLINK_EN_BOFFSET 4 -#define LED_CTRL_TX_BLINK_EN_BLEN 1 -#define LED_CTRL_TX_BLINK_EN_FLAG HSL_RW - -#define LINKUP_OVER_EN "lctrl_loen" -#define LED_CTRL_LINKUP_OVER_EN_BOFFSET 2 -#define LED_CTRL_LINKUP_OVER_EN_BLEN 1 -#define LED_CTRL_LINKUP_OVER_EN_FLAG HSL_RW - -#define BLINK_FREQ "lctrl_bfreq" -#define LED_CTRL_BLINK_FREQ_BOFFSET 0 -#define LED_CTRL_BLINK_FREQ_BLEN 2 -#define LED_CTRL_BLINK_FREQ_FLAG HSL_RW - - /* LED control Register */ -#define LED_PATTERN "ledpatten" -#define LED_PATTERN_ID 25 -#define LED_PATTERN_OFFSET 0x00bc -#define LED_PATTERN_E_LENGTH 4 -#define LED_PATTERN_E_OFFSET 0 -#define LED_PATTERN_NR_E 1 - -#define P3L1_MODE "p3l1_mode" -#define LED_PATTERN_P3L1_MODE_BOFFSET 24 -#define LED_PATTERN_P3L1_MODE_BLEN 2 -#define LED_PATTERN_P3L1_MODE_FLAG HSL_RW - -#define P3L0_MODE "p3l0_mode" -#define LED_PATTERN_P3L0_MODE_BOFFSET 22 -#define LED_PATTERN_P3L0_MODE_BLEN 2 -#define LED_PATTERN_P3L0_MODE_FLAG HSL_RW - -#define P2L1_MODE "p2l1_mode" -#define LED_PATTERN_P2L1_MODE_BOFFSET 20 -#define LED_PATTERN_P2L1_MODE_BLEN 2 -#define LED_PATTERN_P2L1_MODE_FLAG HSL_RW - -#define P2L0_MODE "p2l0_mode" -#define LED_PATTERN_P2L0_MODE_BOFFSET 18 -#define LED_PATTERN_P2L0_MODE_BLEN 2 -#define LED_PATTERN_P2L0_MODE_FLAG HSL_RW - -#define P1L1_MODE "p1l1_mode" -#define LED_PATTERN_P1L1_MODE_BOFFSET 16 -#define LED_PATTERN_P1L1_MODE_BLEN 2 -#define LED_PATTERN_P1L1_MODE_FLAG HSL_RW - -#define P1L0_MODE "p1l0_mode" -#define LED_PATTERN_P1L0_MODE_BOFFSET 14 -#define LED_PATTERN_P1L0_MODE_BLEN 2 -#define LED_PATTERN_P1L0_MODE_FLAG HSL_RW - -#define M6_MODE "m6_mode" -#define LED_PATTERN_M6_MODE_BOFFSET 12 -#define LED_PATTERN_M6_MODE_BLEN 2 -#define LED_PATTERN_M6_MODE_FLAG HSL_RW - -#define M5_MODE "m5_mode" -#define LED_PATTERN_M5_MODE_BOFFSET 10 -#define LED_PATTERN_M5_MODE_BLEN 2 -#define LED_PATTERN_M5_MODE_FLAG HSL_RW - - - /* Port Status Register */ -#define PORT_STATUS "ptsts" -#define PORT_STATUS_ID 29 -#define PORT_STATUS_OFFSET 0x0100 -#define PORT_STATUS_E_LENGTH 4 -#define PORT_STATUS_E_OFFSET 0x0100 -#define PORT_STATUS_NR_E 7 - -#define FLOW_LINK_EN "ptsts_flen" -#define PORT_STATUS_FLOW_LINK_EN_BOFFSET 12 -#define PORT_STATUS_FLOW_LINK_EN_BLEN 1 -#define PORT_STATUS_FLOW_LINK_EN_FLAG HSL_RW - - -#define LINK_ASYN_PAUSE "ptsts_lasynp" -#define PORT_STATUS_LINK_ASYN_PAUSE_BOFFSET 11 -#define PORT_STATUS_LINK_ASYN_PAUSE_BLEN 1 -#define PORT_STATUS_LINK_ASYN_PAUSE_FLAG HSL_RO - -#define LINK_PAUSE "ptsts_lpause" -#define PORT_STATUS_LINK_PAUSE_BOFFSET 10 -#define PORT_STATUS_LINK_PAUSE_BLEN 1 -#define PORT_STATUS_LINK_PAUSE_FLAG HSL_RO - -#define LINK_EN "ptsts_linken" -#define PORT_STATUS_LINK_EN_BOFFSET 9 -#define PORT_STATUS_LINK_EN_BLEN 1 -#define PORT_STATUS_LINK_EN_FLAG HSL_RW - -#define LINK "ptsts_ptlink" -#define PORT_STATUS_LINK_BOFFSET 8 -#define PORT_STATUS_LINK_BLEN 1 -#define PORT_STATUS_LINK_FLAG HSL_RO - -#define TX_HALF_FLOW_EN -#define PORT_STATUS_TX_HALF_FLOW_EN_BOFFSET 7 -#define PORT_STATUS_TX_HALF_FLOW_EN_BLEN 1 -#define PORT_STATUS_TX_HALF_FLOW_EN_FLAG HSL_RW - -#define DUPLEX_MODE "ptsts_dupmod" -#define PORT_STATUS_DUPLEX_MODE_BOFFSET 6 -#define PORT_STATUS_DUPLEX_MODE_BLEN 1 -#define PORT_STATUS_DUPLEX_MODE_FLAG HSL_RW - -#define RX_FLOW_EN "ptsts_rxfwen" -#define PORT_STATUS_RX_FLOW_EN_BOFFSET 5 -#define PORT_STATUS_RX_FLOW_EN_BLEN 1 -#define PORT_STATUS_RX_FLOW_EN_FLAG HSL_RW - -#define TX_FLOW_EN "ptsts_txfwen" -#define PORT_STATUS_TX_FLOW_EN_BOFFSET 4 -#define PORT_STATUS_TX_FLOW_EN_BLEN 1 -#define PORT_STATUS_TX_FLOW_EN_FLAG HSL_RW - -#define RXMAC_EN "ptsts_rxmacen" -#define PORT_STATUS_RXMAC_EN_BOFFSET 3 -#define PORT_STATUS_RXMAC_EN_BLEN 1 -#define PORT_STATUS_RXMAC_EN_FLAG HSL_RW - -#define TXMAC_EN "ptsts_txmacen" -#define PORT_STATUS_TXMAC_EN_BOFFSET 2 -#define PORT_STATUS_TXMAC_EN_BLEN 1 -#define PORT_STATUS_TXMAC_EN_FLAG HSL_RW - -#define SPEED_MODE "ptsts_speed" -#define PORT_STATUS_SPEED_MODE_BOFFSET 0 -#define PORT_STATUS_SPEED_MODE_BLEN 2 -#define PORT_STATUS_SPEED_MODE_FLAG HSL_RW - - - /* Port Control Register */ -#define PORT_CTL "pctl" -#define PORT_CTL_ID 30 -#define PORT_CTL_OFFSET 0x0104 -#define PORT_CTL_E_LENGTH 4 -#define PORT_CTL_E_OFFSET 0x0100 -#define PORT_CTL_NR_E 7 - -#define EAPOL_EN "pctl_eapolen" -#define PORT_CTL_EAPOL_EN_BOFFSET 23 -#define PORT_CTL_EAPOL_EN_BLEN 1 -#define PORT_CTL_EAPOL_EN_FLAG HSL_RW - -#define ARP_LEAKY_EN "pbvlan_alen" -#define PORT_CTL_ARP_LEAKY_EN_BOFFSET 22 -#define PORT_CTL_ARP_LEAKY_EN_BLEN 1 -#define PORT_CTL_ARP_LEAKY_EN_FLAG HSL_RW - -#define LEAVE_EN "pctl_leaveen" -#define PORT_CTL_LEAVE_EN_BOFFSET 21 -#define PORT_CTL_LEAVE_EN_BLEN 1 -#define PORT_CTL_LEAVE_EN_FLAG HSL_RW - -#define JOIN_EN "pctl_joinen" -#define PORT_CTL_JOIN_EN_BOFFSET 20 -#define PORT_CTL_JOIN_EN_BLEN 1 -#define PORT_CTL_JOIN_EN_FLAG HSL_RW - -#define DHCP_EN "pctl_dhcpen" -#define PORT_CTL_DHCP_EN_BOFFSET 19 -#define PORT_CTL_DHCP_EN_BLEN 1 -#define PORT_CTL_DHCP_EN_FLAG HSL_RW - -#define ING_MIRROR_EN "pctl_ingmiren" -#define PORT_CTL_ING_MIRROR_EN_BOFFSET 17 -#define PORT_CTL_ING_MIRROR_EN_BLEN 1 -#define PORT_CTL_ING_MIRROR_EN_FLAG HSL_RW - -#define EG_MIRROR_EN "pctl_egmiren" -#define PORT_CTL_EG_MIRROR_EN_BOFFSET 16 -#define PORT_CTL_EG_MIRROR_EN_BLEN 1 -#define PORT_CTL_EG_MIRROR_EN_FLAG HSL_RW - -#define DTAG_EN "pctl_dtagen" -#define PORT_CTL_DTAG_EN_BOFFSET 15 -#define PORT_CTL_DTAG_EN_BLEN 1 -#define PORT_CTL_DTAG_EN_FLAG HSL_RW - -#define LEARN_EN "pctl_learnen" -#define PORT_CTL_LEARN_EN_BOFFSET 14 -#define PORT_CTL_LEARN_EN_BLEN 1 -#define PORT_CTL_LEARN_EN_FLAG HSL_RW - -#define SINGLE_VLAN_EN "pctl_svlanen" -#define PORT_CTL_SINGLE_VLAN_EN_BOFFSET 13 -#define PORT_CTL_SINGLE_VLAN_EN_BLEN 1 -#define PORT_CTL_SINGLE_VLAN_EN_FLAG HSL_RW - -#define MAC_LOOP_BACK "pctl_maclp" -#define PORT_CTL_MAC_LOOP_BACK_BOFFSET 12 -#define PORT_CTL_MAC_LOOP_BACK_BLEN 1 -#define PORT_CTL_MAC_LOOP_BACK_FLAG HSL_RW - -#define HEAD_EN "pctl_headen" -#define PORT_CTL_HEAD_EN_BOFFSET 11 -#define PORT_CTL_HEAD_EN_BLEN 1 -#define PORT_CTL_HEAD_EN_FLAG HSL_RW - -#define IGMP_MLD_EN "pctl_imlden" -#define PORT_CTL_IGMP_MLD_EN_BOFFSET 10 -#define PORT_CTL_IGMP_MLD_EN_BLEN 1 -#define PORT_CTL_IGMP_MLD_EN_FLAG HSL_RW - -#define EG_VLAN_MODE "pctl_egvmode" -#define PORT_CTL_EG_VLAN_MODE_BOFFSET 8 -#define PORT_CTL_EG_VLAN_MODE_BLEN 2 -#define PORT_CTL_EG_VLAN_MODE_FLAG HSL_RW - -#define LEARN_ONE_LOCK "pctl_lonelck" -#define PORT_CTL_LEARN_ONE_LOCK_BOFFSET 7 -#define PORT_CTL_LEARN_ONE_LOCK_BLEN 1 -#define PORT_CTL_LEARN_ONE_LOCK_FLAG HSL_RW - -#define PORT_LOCK_EN "pctl_locken" -#define PORT_CTL_PORT_LOCK_EN_BOFFSET 6 -#define PORT_CTL_PORT_LOCK_EN_BLEN 1 -#define PORT_CTL_PORT_LOCK_EN_FLAG HSL_RW - -#define LOCK_DROP_EN "pctl_dropen" -#define PORT_CTL_LOCK_DROP_EN_BOFFSET 5 -#define PORT_CTL_LOCK_DROP_EN_BLEN 1 -#define PORT_CTL_LOCK_DROP_EN_FLAG HSL_RW - -#define PORT_STATE "pctl_pstate" -#define PORT_CTL_PORT_STATE_BOFFSET 0 -#define PORT_CTL_PORT_STATE_BLEN 3 -#define PORT_CTL_PORT_STATE_FLAG HSL_RW - - - /* Port dot1ad Register */ -#define PORT_DOT1AD "pdot1ad" -#define PORT_DOT1AD_ID 31 -#define PORT_DOT1AD_OFFSET 0x0108 -#define PORT_DOT1AD_E_LENGTH 4 -#define PORT_DOT1AD_E_OFFSET 0x0100 -#define PORT_DOT1AD_NR_E 7 - -#define ING_PRI "pdot1ad_ingpri" -#define PORT_DOT1AD_ING_PRI_BOFFSET 29 -#define PORT_DOT1AD_ING_PRI_BLEN 3 -#define PORT_DOT1AD_ING_PRI_FLAG HSL_RW - -#define FORCE_PVLAN "pdot1ad_fpvlan" -#define PORT_DOT1AD_FORCE_PVLAN_BOFFSET 28 -#define PORT_DOT1AD_FORCE_PVLAN_BLEN 1 -#define PORT_DOT1AD_FORCE_PVLAN_FLAG HSL_RW - -#define DEF_CVID "pdot1ad_dcvid" -#define PORT_DOT1AD_DEF_CVID_BOFFSET 16 -#define PORT_DOT1AD_DEF_CVID_BLEN 12 -#define PORT_DOT1AD_DEF_CVID_FLAG HSL_RW - -#define CLONE "pdot1ad_clone" -#define PORT_DOT1AD_CLONE_BOFFSET 15 -#define PORT_DOT1AD_CLONE_BLEN 1 -#define PORT_DOT1AD_CLONE_FLAG HSL_RW - -#define PROPAGATION_EN "pdot1ad_pen" -#define PORT_DOT1AD_PROPAGATION_EN_BOFFSET 14 -#define PORT_DOT1AD_PROPAGATION_EN_BLEN 1 -#define PORT_DOT1AD_PROPAGATION_EN_FLAG HSL_RW - -#define TLS_EN "pdot1ad_tlsen" -#define PORT_DOT1AD_TLS_EN_BOFFSET 13 -#define PORT_DOT1AD_TLS_EN_BLEN 1 -#define PORT_DOT1AD_TLS_EN_FLAG HSL_RW - -#define FORCE_DEF_VID "pbot1ad_fdvid" -#define PORT_DOT1AD_FORCE_DEF_VID_BOFFSET 12 -#define PORT_DOT1AD_FORCE_DEF_VID_BLEN 1 -#define PORT_DOT1AD_FORCE_DEF_VID_FLAG HSL_RW - -#define DEF_SVID "pdot1ad_dsvid" -#define PORT_DOT1AD_DEF_SVID_BOFFSET 0 -#define PORT_DOT1AD_DEF_SVID_BLEN 12 -#define PORT_DOT1AD_DEF_SVID_FLAG HSL_RW - - - /* Port Based Vlan Register */ -#define PORT_BASE_VLAN "pbvlan" -#define PORT_BASE_VLAN_ID 31 -#define PORT_BASE_VLAN_OFFSET 0x010c -#define PORT_BASE_VLAN_E_LENGTH 4 -#define PORT_BASE_VLAN_E_OFFSET 0x0100 -#define PORT_BASE_VLAN_NR_E 7 - -#define DOT1Q_MODE "pbvlan_8021q" -#define PORT_BASE_VLAN_DOT1Q_MODE_BOFFSET 30 -#define PORT_BASE_VLAN_DOT1Q_MODE_BLEN 2 -#define PORT_BASE_VLAN_DOT1Q_MODE_FLAG HSL_RW - -#define COREP_EN "pbvlan_corepen" -#define PORT_BASE_VLAN_COREP_EN_BOFFSET 29 -#define PORT_BASE_VLAN_COREP_EN_BLEN 1 -#define PORT_BASE_VLAN_COREP_EN_FLAG HSL_RW - -#define IN_VLAN_MODE "pbvlan_imode" -#define PORT_BASE_VLAN_IN_VLAN_MODE_BOFFSET 27 -#define PORT_BASE_VLAN_IN_VLAN_MODE_BLEN 2 -#define PORT_BASE_VLAN_IN_VLAN_MODE_FLAG HSL_RW - -#define PRI_PROPAGATION "pbvlan_prip" -#define PORT_BASE_VLAN_PRI_PROPAGATION_BOFFSET 23 -#define PORT_BASE_VLAN_PRI_PROPAGATION_BLEN 1 -#define PORT_BASE_VLAN_PRI_PROPAGATION_FLAG HSL_RW - -#define PORT_VID_MEM "pbvlan_pvidm" -#define PORT_BASE_VLAN_PORT_VID_MEM_BOFFSET 16 -#define PORT_BASE_VLAN_PORT_VID_MEM_BLEN 7 -#define PORT_BASE_VLAN_PORT_VID_MEM_FLAG HSL_RW - -#define UNI_LEAKY_EN "pbvlan_ulen" -#define PORT_BASE_VLAN_UNI_LEAKY_EN_BOFFSET 14 -#define PORT_BASE_VLAN_UNI_LEAKY_EN_BLEN 1 -#define PORT_BASE_VLAN_UNI_LEAKY_EN_FLAG HSL_RW - -#define MUL_LEAKY_EN "pbvlan_mlen" -#define PORT_BASE_VLAN_MUL_LEAKY_EN_BOFFSET 13 -#define PORT_BASE_VLAN_MUL_LEAKY_EN_BLEN 1 -#define PORT_BASE_VLAN_MUL_LEAKY_EN_FLAG HSL_RW - - - /* Port Rate Limit0 Register */ -#define RATE_LIMIT0 "rlmt0" -#define RATE_LIMIT0_ID 32 -#define RATE_LIMIT0_OFFSET 0x0110 -#define RATE_LIMIT0_E_LENGTH 4 -#define RATE_LIMIT0_E_OFFSET 0x0100 -#define RATE_LIMIT0_NR_E 7 - -#define ADD_RATE_BYTE "rlmt_addbyte" -#define RATE_LIMIT0_ADD_RATE_BYTE_BOFFSET 24 -#define RATE_LIMIT0_ADD_RATE_BYTE_BLEN 8 -#define RATE_LIMIT0_ADD_RATE_BYTE_FLAG HSL_RW - -#define EG_RATE_EN "rlmt_egen" -#define RATE_LIMIT0_EG_RATE_EN_BOFFSET 23 -#define RATE_LIMIT0_EG_RATE_EN_BLEN 1 -#define RATE_LIMIT0_EG_RATE_EN_FLAG HSL_RW - -#define EG_MNG_RATE_EN "rlmt_egmngen" -#define RATE_LIMIT0_EG_MNG_RATE_EN_BOFFSET 22 -#define RATE_LIMIT0_EG_MNG_RATE_EN_BLEN 1 -#define RATE_LIMIT0_EG_MNG_RATE_EN_FLAG HSL_RW - -#define IN_MNG_RATE_EN "rlmt_inmngen" -#define RATE_LIMIT0_IN_MNG_RATE_EN_BOFFSET 21 -#define RATE_LIMIT0_IN_MNG_RATE_EN_BLEN 1 -#define RATE_LIMIT0_IN_MNG_RATE_EN_FLAG HSL_RW - -#define IN_MUL_RATE_EN "rlmt_inmulen" -#define RATE_LIMIT0_IN_MUL_RATE_EN_BOFFSET 20 -#define RATE_LIMIT0_IN_MUL_RATE_EN_BLEN 1 -#define RATE_LIMIT0_IN_MUL_RATE_EN_FLAG HSL_RW - -#define ING_RATE "rlmt_ingrate" -#define RATE_LIMIT0_ING_RATE_BOFFSET 0 -#define RATE_LIMIT0_ING_RATE_BLEN 15 -#define RATE_LIMIT0_ING_RATE_FLAG HSL_RW - - - /* Priority Control Register */ -#define PRI_CTL "prctl" -#define PRI_CTL_ID 33 -#define PRI_CTL_OFFSET 0x0114 -#define PRI_CTL_E_LENGTH 4 -#define PRI_CTL_E_OFFSET 0x0100 -#define PRI_CTL_NR_E 7 - -#define PORT_PRI_EN "prctl_ptprien" -#define PRI_CTL_PORT_PRI_EN_BOFFSET 19 -#define PRI_CTL_PORT_PRI_EN_BLEN 1 -#define PRI_CTL_PORT_PRI_EN_FLAG HSL_RW - -#define DA_PRI_EN "prctl_daprien" -#define PRI_CTL_DA_PRI_EN_BOFFSET 18 -#define PRI_CTL_DA_PRI_EN_BLEN 1 -#define PRI_CTL_DA_PRI_EN_FLAG HSL_RW - -#define VLAN_PRI_EN "prctl_vprien" -#define PRI_CTL_VLAN_PRI_EN_BOFFSET 17 -#define PRI_CTL_VLAN_PRI_EN_BLEN 1 -#define PRI_CTL_VLAN_PRI_EN_FLAG HSL_RW - -#define IP_PRI_EN "prctl_ipprien" -#define PRI_CTL_IP_PRI_EN_BOFFSET 16 -#define PRI_CTL_IP_PRI_EN_BLEN 1 -#define PRI_CTL_IP_PRI_EN_FLAG HSL_RW - -#define DA_PRI_SEL "prctl_dapris" -#define PRI_CTL_DA_PRI_SEL_BOFFSET 6 -#define PRI_CTL_DA_PRI_SEL_BLEN 2 -#define PRI_CTL_DA_PRI_SEL_FLAG HSL_RW - -#define VLAN_PRI_SEL "prctl_vpris" -#define PRI_CTL_VLAN_PRI_SEL_BOFFSET 4 -#define PRI_CTL_VLAN_PRI_SEL_BLEN 2 -#define PRI_CTL_VLAN_PRI_SEL_FLAG HSL_RW - -#define IP_PRI_SEL "prctl_ippris" -#define PRI_CTL_IP_PRI_SEL_BOFFSET 2 -#define PRI_CTL_IP_PRI_SEL_BLEN 2 -#define PRI_CTL_IP_PRI_SEL_FLAG HSL_RW - -#define PORT_PRI_SEL "prctl_ptpris" -#define PRI_CTL_PORT_PRI_SEL_BOFFSET 0 -#define PRI_CTL_PORT_PRI_SEL_BLEN 2 -#define PRI_CTL_PORT_PRI_SEL_FLAG HSL_RW - - - /* Storm Control Register */ -#define STORM_CTL "sctrl" -#define STORM_CTL_ID 33 -#define STORM_CTL_OFFSET 0x0118 -#define STORM_CTL_E_LENGTH 4 -#define STORM_CTL_E_OFFSET 0x0100 -#define STORM_CTL_NR_E 7 - -#define UNIT "sctrl_unit" -#define STORM_CTL_UNIT_BOFFSET 24 -#define STORM_CTL_UNIT_BLEN 2 -#define STORM_CTL_UNIT_FLAG HSL_RW - -#define MUL_EN "sctrl_mulen" -#define STORM_CTL_MUL_EN_BOFFSET 10 -#define STORM_CTL_MUL_EN_BLEN 1 -#define STORM_CTL_MUL_EN_FLAG HSL_RW - -#define UNI_EN "sctrl_unien" -#define STORM_CTL_UNI_EN_BOFFSET 9 -#define STORM_CTL_UNI_EN_BLEN 1 -#define STORM_CTL_UNI_EN_FLAG HSL_RW - -#define BRO_EN "sctrl_broen" -#define STORM_CTL_BRO_EN_BOFFSET 8 -#define STORM_CTL_BRO_EN_BLEN 1 -#define STORM_CTL_BRO_EN_FLAG HSL_RW - -#define RATE "sctrl_rate" -#define STORM_CTL_RATE_BOFFSET 0 -#define STORM_CTL_RATE_BLEN 4 -#define STORM_CTL_RATE_FLAG HSL_RW - - - /* Queue Control Register */ -#define QUEUE_CTL "qctl" -#define QUEUE_CTL_ID 34 -#define QUEUE_CTL_OFFSET 0x011c -#define QUEUE_CTL_E_LENGTH 4 -#define QUEUE_CTL_E_OFFSET 0x0100 -#define QUEUE_CTL_NR_E 7 - -#define PORT_IN_DESC_EN "qctl_pdescen" -#define QUEUE_CTL_PORT_IN_DESC_EN_BOFFSET 28 -#define QUEUE_CTL_PORT_IN_DESC_EN_BLEN 4 -#define QUEUE_CTL_PORT_IN_DESC_EN_FLAG HSL_RW - -#define PORT_DESC_EN "qctl_pdescen" -#define QUEUE_CTL_PORT_DESC_EN_BOFFSET 25 -#define QUEUE_CTL_PORT_DESC_EN_BLEN 1 -#define QUEUE_CTL_PORT_DESC_EN_FLAG HSL_RW - -#define QUEUE_DESC_EN "qctl_qdescen" -#define QUEUE_CTL_QUEUE_DESC_EN_BOFFSET 24 -#define QUEUE_CTL_QUEUE_DESC_EN_BLEN 1 -#define QUEUE_CTL_QUEUE_DESC_EN_FLAG HSL_RW - -#define PORT_DESC_NR "qctl_pdscpnr" -#define QUEUE_CTL_PORT_DESC_NR_BOFFSET 16 -#define QUEUE_CTL_PORT_DESC_NR_BLEN 6 -#define QUEUE_CTL_PORT_DESC_NR_FLAG HSL_RW - -#define QUEUE3_DESC_NR "qctl_q3dscpnr" -#define QUEUE_CTL_QUEUE3_DESC_NR_BOFFSET 12 -#define QUEUE_CTL_QUEUE3_DESC_NR_BLEN 4 -#define QUEUE_CTL_QUEUE3_DESC_NR_FLAG HSL_RW - -#define QUEUE2_DESC_NR "qctl_q2dscpnr" -#define QUEUE_CTL_QUEUE2_DESC_NR_BOFFSET 8 -#define QUEUE_CTL_QUEUE2_DESC_NR_BLEN 4 -#define QUEUE_CTL_QUEUE2_DESC_NR_FLAG HSL_RW - -#define QUEUE1_DESC_NR "qctl_q1dscpnr" -#define QUEUE_CTL_QUEUE1_DESC_NR_BOFFSET 4 -#define QUEUE_CTL_QUEUE1_DESC_NR_BLEN 4 -#define QUEUE_CTL_QUEUE1_DESC_NR_FLAG HSL_RW - -#define QUEUE0_DESC_NR "qctl_q0dscpnr" -#define QUEUE_CTL_QUEUE0_DESC_NR_BOFFSET 0 -#define QUEUE_CTL_QUEUE0_DESC_NR_BLEN 4 -#define QUEUE_CTL_QUEUE0_DESC_NR_FLAG HSL_RW - - - /* Port Rate Limit1 Register */ -#define RATE_LIMIT1 "rlmt1" -#define RATE_LIMIT1_ID 32 -#define RATE_LIMIT1_OFFSET 0x0120 -#define RATE_LIMIT1_E_LENGTH 4 -#define RATE_LIMIT1_E_OFFSET 0x0100 -#define RATE_LIMIT1_NR_E 7 - -#define EG_Q1_RATE "rlmt_egq1rate" -#define RATE_LIMIT1_EG_Q1_RATE_BOFFSET 16 -#define RATE_LIMIT1_EG_Q1_RATE_BLEN 15 -#define RATE_LIMIT1_EG_Q1_RATE_FLAG HSL_RW - -#define EG_Q0_RATE "rlmt_egq0rate" -#define RATE_LIMIT1_EG_Q0_RATE_BOFFSET 0 -#define RATE_LIMIT1_EG_Q0_RATE_BLEN 15 -#define RATE_LIMIT1_EG_Q0_RATE_FLAG HSL_RW - - - /* Port Rate Limit2 Register */ -#define RATE_LIMIT2 "rlmt2" -#define RATE_LIMIT2_ID 32 -#define RATE_LIMIT2_OFFSET 0x0124 -#define RATE_LIMIT2_E_LENGTH 4 -#define RATE_LIMIT2_E_OFFSET 0x0100 -#define RATE_LIMIT2_NR_E 7 - -#define EG_Q3_RATE "rlmt_egq3rate" -#define RATE_LIMIT2_EG_Q3_RATE_BOFFSET 16 -#define RATE_LIMIT2_EG_Q3_RATE_BLEN 15 -#define RATE_LIMIT2_EG_Q3_RATE_FLAG HSL_RW - -#define EG_Q2_RATE "rlmt_egq2rate" -#define RATE_LIMIT2_EG_Q2_RATE_BOFFSET 0 -#define RATE_LIMIT2_EG_Q2_RATE_BLEN 15 -#define RATE_LIMIT2_EG_Q2_RATE_FLAG HSL_RW - - - - - /* Port Rate Limit3 Register */ -#define RATE_LIMIT3 "rlmt3" -#define RATE_LIMIT3_ID 32 -#define RATE_LIMIT3_OFFSET 0x0128 -#define RATE_LIMIT3_E_LENGTH 4 -#define RATE_LIMIT3_E_OFFSET 0x0100 -#define RATE_LIMIT3_NR_E 7 - -#define EG_Q3_CBS "rlmt_egq3cbs" -#define RATE_LIMIT3_EG_Q3_CBS_BOFFSET 22 -#define RATE_LIMIT3_EG_Q3_CBS_BLEN 2 -#define RATE_LIMIT3_EG_Q3_CBS_FLAG HSL_RW - -#define EG_Q2_CBS "rlmt_egq2cbs" -#define RATE_LIMIT3_EG_Q2_CBS_BOFFSET 20 -#define RATE_LIMIT3_EG_Q2_CBS_BLEN 2 -#define RATE_LIMIT3_EG_Q2_CBS_FLAG HSL_RW - -#define EG_Q1_CBS "rlmt_egq1cbs" -#define RATE_LIMIT3_EG_Q1_CBS_BOFFSET 18 -#define RATE_LIMIT3_EG_Q1_CBS_BLEN 2 -#define RATE_LIMIT3_EG_Q1_CBS_FLAG HSL_RW - -#define EG_Q0_CBS "rlmt_egq0cbs" -#define RATE_LIMIT3_EG_Q0_CBS_BOFFSET 16 -#define RATE_LIMIT3_EG_Q0_CBS_BLEN 2 -#define RATE_LIMIT3_EG_Q0_CBS_FLAG HSL_RW - -#define EG_TS "rlmt_egts" -#define RATE_LIMIT3_EG_TS_BOFFSET 0 -#define RATE_LIMIT3_EG_TS_BLEN 3 -#define RATE_LIMIT3_EG_TS_FLAG HSL_RW - - - - - /* Port Rate Limit2 Register */ -#define WRR_CTRL "wrrc" -#define WRR_CTRL_ID 32 -#define WRR_CTRL_OFFSET 0x012c -#define WRR_CTRL_E_LENGTH 4 -#define WRR_CTRL_E_OFFSET 0x0100 -#define WRR_CTRL_NR_E 7 - -#define SCH_MODE "wrrc_mode" -#define WRR_CTRL_SCH_MODE_BOFFSET 29 -#define WRR_CTRL_SCH_MODE_BLEN 2 -#define WRR_CTRL_SCH_MODE_FLAG HSL_RW - -#define Q3_W "wrrc_q3w" -#define WRR_CTRL_Q3_W_BOFFSET 24 -#define WRR_CTRL_Q3_W_BLEN 5 -#define WRR_CTRL_Q3_W_FLAG HSL_RW - -#define Q2_W "wrrc_q2w" -#define WRR_CTRL_Q2_W_BOFFSET 16 -#define WRR_CTRL_Q2_W_BLEN 5 -#define WRR_CTRL_Q2_W_FLAG HSL_RW - -#define Q1_W "wrrc_q1w" -#define WRR_CTRL_Q1_W_BOFFSET 8 -#define WRR_CTRL_Q1_W_BLEN 5 -#define WRR_CTRL_Q1_W_FLAG HSL_RW - -#define Q0_W "wrrc_q0w" -#define WRR_CTRL_Q0_W_BOFFSET 0 -#define WRR_CTRL_Q0_W_BLEN 5 -#define WRR_CTRL_Q0_W_FLAG HSL_RW - - - /* mib memory info */ -#define MIB_RXBROAD "RxBroad" -#define MIB_RXBROAD_ID 34 -#define MIB_RXBROAD_OFFSET 0x20000 -#define MIB_RXBROAD_E_LENGTH 4 -#define MIB_RXBROAD_E_OFFSET 0x100 -#define MIB_RXBROAD_NR_E 6 - -#define MIB_RXPAUSE "RxPause" -#define MIB_RXPAUSE_ID 35 -#define MIB_RXPAUSE_OFFSET 0x20004 -#define MIB_RXPAUSE_E_LENGTH 4 -#define MIB_RXPAUSE_E_OFFSET 0x100 -#define MIB_RXPAUSE_NR_E 6 - -#define MIB_RXMULTI "RxMulti" -#define MIB_RXMULTI_ID 36 -#define MIB_RXMULTI_OFFSET 0x20008 -#define MIB_RXMULTI_E_LENGTH 4 -#define MIB_RXMULTI_E_OFFSET 0x100 -#define MIB_RXMULTI_NR_E 6 - -#define MIB_RXFCSERR "RxFcsErr" -#define MIB_RXFCSERR_ID 37 -#define MIB_RXFCSERR_OFFSET 0x2000c -#define MIB_RXFCSERR_E_LENGTH 4 -#define MIB_RXFCSERR_E_OFFSET 0x100 -#define MIB_RXFCSERR_NR_E 6 - -#define MIB_RXALLIGNERR "RxAllignErr" -#define MIB_RXALLIGNERR_ID 38 -#define MIB_RXALLIGNERR_OFFSET 0x20010 -#define MIB_RXALLIGNERR_E_LENGTH 4 -#define MIB_RXALLIGNERR_E_OFFSET 0x100 -#define MIB_RXALLIGNERR_NR_E 6 - -#define MIB_RXRUNT "RxRunt" -#define MIB_RXRUNT_ID 39 -#define MIB_RXRUNT_OFFSET 0x20014 -#define MIB_RXRUNT_E_LENGTH 4 -#define MIB_RXRUNT_E_OFFSET 0x100 -#define MIB_RXRUNT_NR_E 6 - -#define MIB_RXFRAGMENT "RxFragment" -#define MIB_RXFRAGMENT_ID 40 -#define MIB_RXFRAGMENT_OFFSET 0x20018 -#define MIB_RXFRAGMENT_E_LENGTH 4 -#define MIB_RXFRAGMENT_E_OFFSET 0x100 -#define MIB_RXFRAGMENT_NR_E 6 - -#define MIB_RX64BYTE "Rx64Byte" -#define MIB_RX64BYTE_ID 41 -#define MIB_RX64BYTE_OFFSET 0x2001c -#define MIB_RX64BYTE_E_LENGTH 4 -#define MIB_RX64BYTE_E_OFFSET 0x100 -#define MIB_RX64BYTE_NR_E 6 - -#define MIB_RX128BYTE "Rx128Byte" -#define MIB_RX128BYTE_ID 42 -#define MIB_RX128BYTE_OFFSET 0x20020 -#define MIB_RX128BYTE_E_LENGTH 4 -#define MIB_RX128BYTE_E_OFFSET 0x100 -#define MIB_RX128BYTE_NR_E 6 - -#define MIB_RX256BYTE "Rx256Byte" -#define MIB_RX256BYTE_ID 43 -#define MIB_RX256BYTE_OFFSET 0x20024 -#define MIB_RX256BYTE_E_LENGTH 4 -#define MIB_RX256BYTE_E_OFFSET 0x100 -#define MIB_RX256BYTE_NR_E 6 - -#define MIB_RX512BYTE "Rx512Byte" -#define MIB_RX512BYTE_ID 44 -#define MIB_RX512BYTE_OFFSET 0x20028 -#define MIB_RX512BYTE_E_LENGTH 4 -#define MIB_RX512BYTE_E_OFFSET 0x100 -#define MIB_RX512BYTE_NR_E 6 - -#define MIB_RX1024BYTE "Rx1024Byte" -#define MIB_RX1024BYTE_ID 45 -#define MIB_RX1024BYTE_OFFSET 0x2002c -#define MIB_RX1024BYTE_E_LENGTH 4 -#define MIB_RX1024BYTE_E_OFFSET 0x100 -#define MIB_RX1024BYTE_NR_E 6 - -#define MIB_RX1518BYTE "Rx1518Byte" -#define MIB_RX1518BYTE_ID 45 -#define MIB_RX1518BYTE_OFFSET 0x20030 -#define MIB_RX1518BYTE_E_LENGTH 4 -#define MIB_RX1518BYTE_E_OFFSET 0x100 -#define MIB_RX1518BYTE_NR_E 6 - -#define MIB_RXMAXBYTE "RxMaxByte" -#define MIB_RXMAXBYTE_ID 46 -#define MIB_RXMAXBYTE_OFFSET 0x20034 -#define MIB_RXMAXBYTE_E_LENGTH 4 -#define MIB_RXMAXBYTE_E_OFFSET 0x100 -#define MIB_RXMAXBYTE_NR_E 6 - -#define MIB_RXTOOLONG "RxTooLong" -#define MIB_RXTOOLONG_ID 47 -#define MIB_RXTOOLONG_OFFSET 0x20038 -#define MIB_RXTOOLONG_E_LENGTH 4 -#define MIB_RXTOOLONG_E_OFFSET 0x100 -#define MIB_RXTOOLONG_NR_E 6 - -#define MIB_RXGOODBYTE_LO "RxGoodByteLo" -#define MIB_RXGOODBYTE_LO_ID 48 -#define MIB_RXGOODBYTE_LO_OFFSET 0x2003c -#define MIB_RXGOODBYTE_LO_E_LENGTH 4 -#define MIB_RXGOODBYTE_LO_E_OFFSET 0x100 -#define MIB_RXGOODBYTE_LO_NR_E 6 - -#define MIB_RXGOODBYTE_HI "RxGoodByteHi" -#define MIB_RXGOODBYTE_HI_ID 49 -#define MIB_RXGOODBYTE_HI_OFFSET 0x20040 -#define MIB_RXGOODBYTE_HI_E_LENGTH 4 -#define MIB_RXGOODBYTE_HI_E_OFFSET 0x100 -#define MIB_RXGOODBYTE_HI_NR_E 6 - -#define MIB_RXBADBYTE_LO "RxBadByteLo" -#define MIB_RXBADBYTE_LO_ID 50 -#define MIB_RXBADBYTE_LO_OFFSET 0x20044 -#define MIB_RXBADBYTE_LO_E_LENGTH 4 -#define MIB_RXBADBYTE_LO_E_OFFSET 0x100 -#define MIB_RXBADBYTE_LO_NR_E 6 - -#define MIB_RXBADBYTE_HI "RxBadByteHi" -#define MIB_RXBADBYTE_HI_ID 51 -#define MIB_RXBADBYTE_HI_OFFSET 0x20048 -#define MIB_RXBADBYTE_HI_E_LENGTH 4 -#define MIB_RXBADBYTE_HI_E_OFFSET 0x100 -#define MIB_RXBADBYTE_HI_NR_E 6 - -#define MIB_RXOVERFLOW "RxOverFlow" -#define MIB_RXOVERFLOW_ID 52 -#define MIB_RXOVERFLOW_OFFSET 0x2004c -#define MIB_RXOVERFLOW_E_LENGTH 4 -#define MIB_RXOVERFLOW_E_OFFSET 0x100 -#define MIB_RXOVERFLOW_NR_E 6 - -#define MIB_FILTERED "Filtered" -#define MIB_FILTERED_ID 53 -#define MIB_FILTERED_OFFSET 0x20050 -#define MIB_FILTERED_E_LENGTH 4 -#define MIB_FILTERED_E_OFFSET 0x100 -#define MIB_FILTERED_NR_E 6 - -#define MIB_TXBROAD "TxBroad" -#define MIB_TXBROAD_ID 54 -#define MIB_TXBROAD_OFFSET 0x20054 -#define MIB_TXBROAD_E_LENGTH 4 -#define MIB_TXBROAD_E_OFFSET 0x100 -#define MIB_TXBROAD_NR_E 6 - -#define MIB_TXPAUSE "TxPause" -#define MIB_TXPAUSE_ID 55 -#define MIB_TXPAUSE_OFFSET 0x20058 -#define MIB_TXPAUSE_E_LENGTH 4 -#define MIB_TXPAUSE_E_OFFSET 0x100 -#define MIB_TXPAUSE_NR_E 6 - -#define MIB_TXMULTI "TxMulti" -#define MIB_TXMULTI_ID 56 -#define MIB_TXMULTI_OFFSET 0x2005c -#define MIB_TXMULTI_E_LENGTH 4 -#define MIB_TXMULTI_E_OFFSET 0x100 -#define MIB_TXMULTI_NR_E 6 - -#define MIB_TXUNDERRUN "TxUnderRun" -#define MIB_TXUNDERRUN_ID 57 -#define MIB_TXUNDERRUN_OFFSET 0x20060 -#define MIB_TXUNDERRUN_E_LENGTH 4 -#define MIB_TXUNDERRUN_E_OFFSET 0x100 -#define MIB_TXUNDERRUN_NR_E 6 - -#define MIB_TX64BYTE "Tx64Byte" -#define MIB_TX64BYTE_ID 58 -#define MIB_TX64BYTE_OFFSET 0x20064 -#define MIB_TX64BYTE_E_LENGTH 4 -#define MIB_TX64BYTE_E_OFFSET 0x100 -#define MIB_TX64BYTE_NR_E 6 - -#define MIB_TX128BYTE "Tx128Byte" -#define MIB_TX128BYTE_ID 59 -#define MIB_TX128BYTE_OFFSET 0x20068 -#define MIB_TX128BYTE_E_LENGTH 4 -#define MIB_TX128BYTE_E_OFFSET 0x100 -#define MIB_TX128BYTE_NR_E 6 - -#define MIB_TX256BYTE "Tx256Byte" -#define MIB_TX256BYTE_ID 60 -#define MIB_TX256BYTE_OFFSET 0x2006c -#define MIB_TX256BYTE_E_LENGTH 4 -#define MIB_TX256BYTE_E_OFFSET 0x100 -#define MIB_TX256BYTE_NR_E 6 - -#define MIB_TX512BYTE "Tx512Byte" -#define MIB_TX512BYTE_ID 61 -#define MIB_TX512BYTE_OFFSET 0x20070 -#define MIB_TX512BYTE_E_LENGTH 4 -#define MIB_TX512BYTE_E_OFFSET 0x100 -#define MIB_TX512BYTE_NR_E 6 - -#define MIB_TX1024BYTE "Tx1024Byte" -#define MIB_TX1024BYTE_ID 62 -#define MIB_TX1024BYTE_OFFSET 0x20074 -#define MIB_TX1024BYTE_E_LENGTH 4 -#define MIB_TX1024BYTE_E_OFFSET 0x100 -#define MIB_TX1024BYTE_NR_E 6 - -#define MIB_TX1518BYTE "Tx1518Byte" -#define MIB_TX1518BYTE_ID 62 -#define MIB_TX1518BYTE_OFFSET 0x20078 -#define MIB_TX1518BYTE_E_LENGTH 4 -#define MIB_TX1518BYTE_E_OFFSET 0x100 -#define MIB_TX1518BYTE_NR_E 6 - -#define MIB_TXMAXBYTE "TxMaxByte" -#define MIB_TXMAXBYTE_ID 63 -#define MIB_TXMAXBYTE_OFFSET 0x2007c -#define MIB_TXMAXBYTE_E_LENGTH 4 -#define MIB_TXMAXBYTE_E_OFFSET 0x100 -#define MIB_TXMAXBYTE_NR_E 6 - -#define MIB_TXOVERSIZE "TxOverSize" -#define MIB_TXOVERSIZE_ID 64 -#define MIB_TXOVERSIZE_OFFSET 0x20080 -#define MIB_TXOVERSIZE_E_LENGTH 4 -#define MIB_TXOVERSIZE_E_OFFSET 0x100 -#define MIB_TXOVERSIZE_NR_E 6 - -#define MIB_TXBYTE_LO "TxByteLo" -#define MIB_TXBYTE_LO_ID 65 -#define MIB_TXBYTE_LO_OFFSET 0x20084 -#define MIB_TXBYTE_LO_E_LENGTH 4 -#define MIB_TXBYTE_LO_E_OFFSET 0x100 -#define MIB_TXBYTE_LO_NR_E 6 - -#define MIB_TXBYTE_HI "TxByteHi" -#define MIB_TXBYTE_HI_ID 66 -#define MIB_TXBYTE_HI_OFFSET 0x20088 -#define MIB_TXBYTE_HI_E_LENGTH 4 -#define MIB_TXBYTE_HI_E_OFFSET 0x100 -#define MIB_TXBYTE_HI_NR_E 6 - -#define MIB_TXCOLLISION "TxCollision" -#define MIB_TXCOLLISION_ID 67 -#define MIB_TXCOLLISION_OFFSET 0x2008c -#define MIB_TXCOLLISION_E_LENGTH 4 -#define MIB_TXCOLLISION_E_OFFSET 0x100 -#define MIB_TXCOLLISION_NR_E 6 - -#define MIB_TXABORTCOL "TxAbortCol" -#define MIB_TXABORTCOL_ID 68 -#define MIB_TXABORTCOL_OFFSET 0x20090 -#define MIB_TXABORTCOL_E_LENGTH 4 -#define MIB_TXABORTCOL_E_OFFSET 0x100 -#define MIB_TXABORTCOL_NR_E 6 - -#define MIB_TXMULTICOL "TxMultiCol" -#define MIB_TXMULTICOL_ID 69 -#define MIB_TXMULTICOL_OFFSET 0x20094 -#define MIB_TXMULTICOL_E_LENGTH 4 -#define MIB_TXMULTICOL_E_OFFSET 0x100 -#define MIB_TXMULTICOL_NR_E 6 - -#define MIB_TXSINGALCOL "TxSingalCol" -#define MIB_TXSINGALCOL_ID 70 -#define MIB_TXSINGALCOL_OFFSET 0x20098 -#define MIB_TXSINGALCOL_E_LENGTH 4 -#define MIB_TXSINGALCOL_E_OFFSET 0x100 -#define MIB_TXSINGALCOL_NR_E 6 - -#define MIB_TXEXCDEFER "TxExcDefer" -#define MIB_TXEXCDEFER_ID 71 -#define MIB_TXEXCDEFER_OFFSET 0x2009c -#define MIB_TXEXCDEFER_E_LENGTH 4 -#define MIB_TXEXCDEFER_E_OFFSET 0x100 -#define MIB_TXEXCDEFER_NR_E 6 - -#define MIB_TXDEFER "TxDefer" -#define MIB_TXDEFER_ID 72 -#define MIB_TXDEFER_OFFSET 0x200a0 -#define MIB_TXDEFER_E_LENGTH 4 -#define MIB_TXDEFER_E_OFFSET 0x100 -#define MIB_TXDEFER_NR_E 6 - -#define MIB_TXLATECOL "TxLateCol" -#define MIB_TXLATECOL_ID 73 -#define MIB_TXLATECOL_OFFSET 0x200a4 -#define MIB_TXLATECOL_E_LENGTH 4 -#define MIB_TXLATECOL_E_OFFSET 0x100 -#define MIB_TXLATECOL_NR_E 6 - -#if 0 - /* mib info second mem block */ -#define MIB_RXBROAD_2 "RxBroad_2" -#define MIB_RXBROAD_2_ID 34 -#define MIB_RXBROAD_2_OFFSET (MIB_RXBROAD_OFFSET + 0x400) -#define MIB_RXBROAD_2_E_LENGTH 4 -#define MIB_RXBROAD_2_E_OFFSET 0xa8 -#define MIB_RXBROAD_2_NR_E 6 - -#define MIB_RXPAUSE_2 "RxPause_2" -#define MIB_RXPAUSE_2_ID 35 -#define MIB_RXPAUSE_2_OFFSET (MIB_RXPAUSE_OFFSET + 0x400) -#define MIB_RXPAUSE_2_E_LENGTH 4 -#define MIB_RXPAUSE_2_E_OFFSET 0xa8 -#define MIB_RXPAUSE_2_NR_E 6 - -#define MIB_RXMULTI_2 "RxMulti_2" -#define MIB_RXMULTI_2_ID 36 -#define MIB_RXMULTI_2_OFFSET (MIB_RXMULTI_OFFSET + 0x400) -#define MIB_RXMULTI_2_E_LENGTH 4 -#define MIB_RXMULTI_2_E_OFFSET 0xa8 -#define MIB_RXMULTI_2_NR_E 6 - -#define MIB_RXFCSERR_2 "RxFcsErr_2" -#define MIB_RXFCSERR_2_ID 37 -#define MIB_RXFCSERR_2_OFFSET (MIB_RXFCSERR_OFFSET + 0x400) -#define MIB_RXFCSERR_2_E_LENGTH 4 -#define MIB_RXFCSERR_2_E_OFFSET 0xa8 -#define MIB_RXFCSERR_2_NR_E 6 - -#define MIB_RXALLIGNERR_2 "RxAllignErr_2" -#define MIB_RXALLIGNERR_2_ID 38 -#define MIB_RXALLIGNERR_2_OFFSET (MIB_RXALLIGNERR_OFFSET + 0x400) -#define MIB_RXALLIGNERR_2_E_LENGTH 4 -#define MIB_RXALLIGNERR_2_E_OFFSET 0xa8 -#define MIB_RXALLIGNERR_2_NR_E 6 - -#define MIB_RXRUNT_2 "RxRunt_2" -#define MIB_RXRUNT_2_ID 39 -#define MIB_RXRUNT_2_OFFSET (MIB_RXRUNT_OFFSET + 0x400) -#define MIB_RXRUNT_2_E_LENGTH 4 -#define MIB_RXRUNT_2_E_OFFSET 0xa8 -#define MIB_RXRUNT_2_NR_E 6 - -#define MIB_RXFRAGMENT_2 "RxFragment_2" -#define MIB_RXFRAGMENT_2_ID 40 -#define MIB_RXFRAGMENT_2_OFFSET (MIB_RXFRAGMENT_OFFSET + 0x400) -#define MIB_RXFRAGMENT_2_E_LENGTH 4 -#define MIB_RXFRAGMENT_2_E_OFFSET 0xa8 -#define MIB_RXFRAGMENT_2_NR_E 6 - -#define MIB_RX64BYTE_2 "Rx64Byte_2" -#define MIB_RX64BYTE_2_ID 41 -#define MIB_RX64BYTE_2_OFFSET (MIB_RX64BYTE_OFFSET + 0x400) -#define MIB_RX64BYTE_2_E_LENGTH 4 -#define MIB_RX64BYTE_2_E_OFFSET 0xa8 -#define MIB_RX64BYTE_2_NR_E 6 - -#define MIB_RX128BYTE_2 "Rx128Byte_2" -#define MIB_RX128BYTE_2_ID 42 -#define MIB_RX128BYTE_2_OFFSET (MIB_RX128BYTE_OFFSET + 0x400) -#define MIB_RX128BYTE_2_E_LENGTH 4 -#define MIB_RX128BYTE_2_E_OFFSET 0xa8 -#define MIB_RX128BYTE_2_NR_E 6 - -#define MIB_RX256BYTE_2 "Rx256Byte_2" -#define MIB_RX256BYTE_2_ID 43 -#define MIB_RX256BYTE_2_OFFSET (MIB_RX256BYTE_OFFSET + 0x400) -#define MIB_RX256BYTE_2_E_LENGTH 4 -#define MIB_RX256BYTE_2_E_OFFSET 0xa8 -#define MIB_RX256BYTE_2_NR_E 6 - -#define MIB_RX512BYTE_2 "Rx512Byte_2" -#define MIB_RX512BYTE_2_ID 44 -#define MIB_RX512BYTE_2_OFFSET (MIB_RX512BYTE_OFFSET + 0x400) -#define MIB_RX512BYTE_2_E_LENGTH 4 -#define MIB_RX512BYTE_2_E_OFFSET 0xa8 -#define MIB_RX512BYTE_2_NR_E 6 - -#define MIB_RX1024BYTE_2 "Rx1024Byte_2" -#define MIB_RX1024BYTE_2_ID 45 -#define MIB_RX1024BYTE_2_OFFSET (MIB_RX1024BYTE_OFFSET + 0x400) -#define MIB_RX1024BYTE_2_E_LENGTH 4 -#define MIB_RX1024BYTE_2_E_OFFSET 0xa8 -#define MIB_RX1024BYTE_2_NR_E 6 - -#define MIB_RX1518BYTE_2 "Rx1518Byte_2" -#define MIB_RX1518BYTE_2_ID 45 -#define MIB_RX1518BYTE_2_OFFSET (MIB_RX1518BYTE_OFFSET + 0x400) -#define MIB_RX1518BYTE_2_E_LENGTH 4 -#define MIB_RX1518BYTE_2_E_OFFSET 0xa8 -#define MIB_RX1518BYTE_2_NR_E 6 - -#define MIB_RXMAXBYTE_2 "RxMaxByte_2" -#define MIB_RXMAXBYTE_2_ID 46 -#define MIB_RXMAXBYTE_2_OFFSET (MIB_RXMAXBYTE_OFFSET + 0x400) -#define MIB_RXMAXBYTE_2_E_LENGTH 4 -#define MIB_RXMAXBYTE_2_E_OFFSET 0xa8 -#define MIB_RXMAXBYTE_2_NR_E 6 - -#define MIB_RXTOOLONG_2 "RxTooLong_2" -#define MIB_RXTOOLONG_2_ID 47 -#define MIB_RXTOOLONG_2_OFFSET (MIB_RXTOOLONG_OFFSET + 0x400) -#define MIB_RXTOOLONG_2_E_LENGTH 4 -#define MIB_RXTOOLONG_2_E_OFFSET 0xa8 -#define MIB_RXTOOLONG_2_NR_E 6 - -#define MIB_RXGOODBYTE_LO_2 "RxGoodByteLo_2" -#define MIB_RXGOODBYTE_LO_2_ID 48 -#define MIB_RXGOODBYTE_LO_2_OFFSET (MIB_RXGOODBYTE_LO_OFFSET + 0x400) -#define MIB_RXGOODBYTE_LO_2_E_LENGTH 4 -#define MIB_RXGOODBYTE_LO_2_E_OFFSET 0xa8 -#define MIB_RXGOODBYTE_LO_2_NR_E 6 - -#define MIB_RXGOODBYTE_HI_2 "RxGoodByteHi_2" -#define MIB_RXGOODBYTE_HI_2_ID 49 -#define MIB_RXGOODBYTE_HI_2_OFFSET (MIB_RXGOODBYTE_HI_OFFSET + 0x400) -#define MIB_RXGOODBYTE_HI_2_E_LENGTH 4 -#define MIB_RXGOODBYTE_HI_2_E_OFFSET 0xa8 -#define MIB_RXGOODBYTE_HI_2_NR_E 6 - -#define MIB_RXBADBYTE_LO_2 "RxBadByteLo_2" -#define MIB_RXBADBYTE_LO_2_ID 50 -#define MIB_RXBADBYTE_LO_2_OFFSET (MIB_RXBADBYTE_LO_OFFSET + 0x400) -#define MIB_RXBADBYTE_LO_2_E_LENGTH 4 -#define MIB_RXBADBYTE_LO_2_E_OFFSET 0xa8 -#define MIB_RXBADBYTE_LO_2_NR_E 6 - -#define MIB_RXBADBYTE_HI_2 "RxBadByteHi_2" -#define MIB_RXBADBYTE_HI_2_ID 51 -#define MIB_RXBADBYTE_HI_2_OFFSET (MIB_RXBADBYTE_HI_OFFSET + 0x400) -#define MIB_RXBADBYTE_HI_2_E_LENGTH 4 -#define MIB_RXBADBYTE_HI_2_E_OFFSET 0xa8 -#define MIB_RXBADBYTE_HI_2_NR_E 6 - -#define MIB_RXOVERFLOW_2 "RxOverFlow_2" -#define MIB_RXOVERFLOW_2_ID 52 -#define MIB_RXOVERFLOW_2_OFFSET (MIB_RXOVERFLOW_OFFSET + 0x400) -#define MIB_RXOVERFLOW_2_E_LENGTH 4 -#define MIB_RXOVERFLOW_2_E_OFFSET 0xa8 -#define MIB_RXOVERFLOW_2_NR_E 6 - -#define MIB_FILTERED_2 "Filtered_2" -#define MIB_FILTERED_2_ID 53 -#define MIB_FILTERED_2_OFFSET (MIB_FILTERED_OFFSET + 0x400) -#define MIB_FILTERED_2_E_LENGTH 4 -#define MIB_FILTERED_2_E_OFFSET 0xa8 -#define MIB_FILTERED_2_NR_E 6 - -#define MIB_TXBROAD_2 "TxBroad_2" -#define MIB_TXBROAD_2_ID 54 -#define MIB_TXBROAD_2_OFFSET (MIB_TXBROAD_OFFSET + 0x400) -#define MIB_TXBROAD_2_E_LENGTH 4 -#define MIB_TXBROAD_2_E_OFFSET 0xa8 -#define MIB_TXBROAD_2_NR_E 6 - -#define MIB_TXPAUSE_2 "TxPause_2" -#define MIB_TXPAUSE_2_ID 55 -#define MIB_TXPAUSE_2_OFFSET (MIB_TXPAUSE_OFFSET + 0x400) -#define MIB_TXPAUSE_2_E_LENGTH 4 -#define MIB_TXPAUSE_2_E_OFFSET 0xa8 -#define MIB_TXPAUSE_2_NR_E 6 - -#define MIB_TXMULTI_2 "TxMulti_2" -#define MIB_TXMULTI_2_ID 56 -#define MIB_TXMULTI_2_OFFSET (MIB_TXMULTI_OFFSET + 0x400) -#define MIB_TXMULTI_2_E_LENGTH 4 -#define MIB_TXMULTI_2_E_OFFSET 0xa8 -#define MIB_TXMULTI_2_NR_E 6 - -#define MIB_TXUNDERRUN_2 "TxUnderRun_2" -#define MIB_TXUNDERRUN_2_ID 57 -#define MIB_TXUNDERRUN_2_OFFSET (MIB_TXUNDERRUN_OFFSET + 0x400) -#define MIB_TXUNDERRUN_2_E_LENGTH 4 -#define MIB_TXUNDERRUN_2_E_OFFSET 0xa8 -#define MIB_TXUNDERRUN_2_NR_E 6 - -#define MIB_TX64BYTE_2 "Tx64Byte_2" -#define MIB_TX64BYTE_2_ID 58 -#define MIB_TX64BYTE_2_OFFSET (MIB_TX64BYTE_OFFSET + 0x400) -#define MIB_TX64BYTE_2_E_LENGTH 4 -#define MIB_TX64BYTE_2_E_OFFSET 0xa8 -#define MIB_TX64BYTE_2_NR_E 6 - -#define MIB_TX128BYTE_2 "Tx128Byte_2" -#define MIB_TX128BYTE_2_ID 59 -#define MIB_TX128BYTE_2_OFFSET (MIB_TX128BYTE_OFFSET + 0x400) -#define MIB_TX128BYTE_2_E_LENGTH 4 -#define MIB_TX128BYTE_2_E_OFFSET 0xa8 -#define MIB_TX128BYTE_2_NR_E 6 - -#define MIB_TX256BYTE_2 "Tx256Byte_2" -#define MIB_TX256BYTE_2_ID 60 -#define MIB_TX256BYTE_2_OFFSET (MIB_TX256BYTE_OFFSET + 0x400) -#define MIB_TX256BYTE_2_E_LENGTH 4 -#define MIB_TX256BYTE_2_E_OFFSET 0xa8 -#define MIB_TX256BYTE_2_NR_E 6 - -#define MIB_TX512BYTE_2 "Tx512Byte_2" -#define MIB_TX512BYTE_2_ID 61 -#define MIB_TX512BYTE_2_OFFSET (MIB_TX512BYTE_OFFSET + 0x400) -#define MIB_TX512BYTE_2_E_LENGTH 4 -#define MIB_TX512BYTE_2_E_OFFSET 0xa8 -#define MIB_TX512BYTE_2_NR_E 6 - -#define MIB_TX1024BYTE_2 "Tx1024Byte_2" -#define MIB_TX1024BYTE_2_ID 62 -#define MIB_TX1024BYTE_2_OFFSET (MIB_TX1024BYTE_OFFSET + 0x400) -#define MIB_TX1024BYTE_2_E_LENGTH 4 -#define MIB_TX1024BYTE_2_E_OFFSET 0xa8 -#define MIB_TX1024BYTE_2_NR_E 6 - -#define MIB_TX1518BYTE_2 "Tx1518Byte_2" -#define MIB_TX1518BYTE_2_ID 62 -#define MIB_TX1518BYTE_2_OFFSET (MIB_TX1518BYTE_OFFSET + 0x400) -#define MIB_TX1518BYTE_2_E_LENGTH 4 -#define MIB_TX1518BYTE_2_E_OFFSET 0xa8 -#define MIB_TX1518BYTE_2_NR_E 6 - -#define MIB_TXMAXBYTE_2 "TxMaxByte_2" -#define MIB_TXMAXBYTE_2_ID 63 -#define MIB_TXMAXBYTE_2_OFFSET (MIB_TXMAXBYTE_OFFSET + 0x400) -#define MIB_TXMAXBYTE_2_E_LENGTH 4 -#define MIB_TXMAXBYTE_2_E_OFFSET 0xa8 -#define MIB_TXMAXBYTE_2_NR_E 6 - -#define MIB_TXOVERSIZE_2 "TxOverSize_2" -#define MIB_TXOVERSIZE_2_ID 64 -#define MIB_TXOVERSIZE_2_OFFSET (MIB_TXOVERSIZE_OFFSET + 0x400) -#define MIB_TXOVERSIZE_2_E_LENGTH 4 -#define MIB_TXOVERSIZE_2_E_OFFSET 0xa8 -#define MIB_TXOVERSIZE_2_NR_E 6 - -#define MIB_TXBYTE_LO_2 "TxByteLo_2" -#define MIB_TXBYTE_LO_2_ID 65 -#define MIB_TXBYTE_LO_2_OFFSET (MIB_TXBYTE_LO_OFFSET + 0x400) -#define MIB_TXBYTE_LO_2_E_LENGTH 4 -#define MIB_TXBYTE_LO_2_E_OFFSET 0xa8 -#define MIB_TXBYTE_LO_2_NR_E 6 - -#define MIB_TXBYTE_HI_2 "TxByteHi_2" -#define MIB_TXBYTE_HI_2_ID 66 -#define MIB_TXBYTE_HI_2_OFFSET (MIB_TXBYTE_HI_OFFSET + 0x400) -#define MIB_TXBYTE_HI_2_E_LENGTH 4 -#define MIB_TXBYTE_HI_2_E_OFFSET 0xa8 -#define MIB_TXBYTE_HI_2_NR_E 6 - -#define MIB_TXCOLLISION_2 "TxCollision_2" -#define MIB_TXCOLLISION_2_ID 67 -#define MIB_TXCOLLISION_2_OFFSET (MIB_TXCOLLISION_OFFSET + 0x400) -#define MIB_TXCOLLISION_2_E_LENGTH 4 -#define MIB_TXCOLLISION_2_E_OFFSET 0xa8 -#define MIB_TXCOLLISION_2_NR_E 6 - -#define MIB_TXABORTCOL_2 "TxAbortCol_2" -#define MIB_TXABORTCOL_2_ID 68 -#define MIB_TXABORTCOL_2_OFFSET (MIB_TXABORTCOL_OFFSET + 0x400) -#define MIB_TXABORTCOL_2_E_LENGTH 4 -#define MIB_TXABORTCOL_2_E_OFFSET 0xa8 -#define MIB_TXABORTCOL_2_NR_E 6 - -#define MIB_TXMULTICOL_2 "TxMultiCol_2" -#define MIB_TXMULTICOL_2_ID 69 -#define MIB_TXMULTICOL_2_OFFSET (MIB_TXMULTICOL_OFFSET + 0x400) -#define MIB_TXMULTICOL_2_E_LENGTH 4 -#define MIB_TXMULTICOL_2_E_OFFSET 0xa8 -#define MIB_TXMULTICOL_2_NR_E 6 - -#define MIB_TXSINGALCOL_2 "TxSingalCol_2" -#define MIB_TXSINGALCOL_2_ID 70 -#define MIB_TXSINGALCOL_2_OFFSET (MIB_TXSINGALCOL_OFFSET + 0x400) -#define MIB_TXSINGALCOL_2_E_LENGTH 4 -#define MIB_TXSINGALCOL_2_E_OFFSET 0xa8 -#define MIB_TXSINGALCOL_2_NR_E 6 - -#define MIB_TXEXCDEFER_2 "TxExcDefer_2" -#define MIB_TXEXCDEFER_2_ID 71 -#define MIB_TXEXCDEFER_2_OFFSET (MIB_TXEXCDEFER_OFFSET + 0x400) -#define MIB_TXEXCDEFER_2_E_LENGTH 4 -#define MIB_TXEXCDEFER_2_E_OFFSET 0xa8 -#define MIB_TXEXCDEFER_2_NR_E 6 - -#define MIB_TXDEFER_2 "TxDefer_2" -#define MIB_TXDEFER_2_ID 72 -#define MIB_TXDEFER_2_OFFSET (MIB_TXDEFER_OFFSET + 0x400) -#define MIB_TXDEFER_2_E_LENGTH 4 -#define MIB_TXDEFER_2_E_OFFSET 0xa8 -#define MIB_TXDEFER_2_NR_E 6 - -#define MIB_TXLATECOL_2 "TxLateCol_2" -#define MIB_TXLATECOL_2_ID 73 -#define MIB_TXLATECOL_2_OFFSET (MIB_TXLATECOL_OFFSET + 0x400) -#define MIB_TXLATECOL_2_E_LENGTH 4 -#define MIB_TXLATECOL_2_E_OFFSET 0xa8 -#define MIB_TXLATECOL_2_NR_E 6 -#endif - - - - -#define ACL_RSLT0 "aclact0" -#define ACL_RSLT0_ID 13 -#define ACL_RSLT0_OFFSET 0x58000 -#define ACL_RSLT0_E_LENGTH 4 -#define ACL_RSLT0_E_OFFSET 0x20 -#define ACL_RSLT0_NR_E 32 - -#define MATCH_CNT "aclact_cnt" -#define ACL_RSLT0_MATCH_CNT_BOFFSET 0 -#define ACL_RSLT0_MATCH_CNT_BLEN 32 -#define ACL_RSLT0_MATCH_CNT_FLAG HSL_RW - - - - -#define ACL_RSLT1 "aclact1" -#define ACL_RSLT1_ID 13 -#define ACL_RSLT1_OFFSET 0x58004 -#define ACL_RSLT1_E_LENGTH 4 -#define ACL_RSLT1_E_OFFSET 0x20 -#define ACL_RSLT1_NR_E 32 - -#define MIRR_EN "aclact1_mirr" -#define ACL_RSLT1_MIRR_EN_BOFFSET 31 -#define ACL_RSLT1_MIRR_EN_BLEN 1 -#define ACL_RSLT1_MIRR_EN_FLAG HSL_RW - -#define STAG_CHG_EN "aclact1_rdcpu" -#define ACL_RSLT1_STAG_CHG_EN_BOFFSET 30 -#define ACL_RSLT1_STAG_CHG_EN_BLEN 1 -#define ACL_RSLT1_STAG_CHG_EN_FLAG HSL_RW - -#define VID_MEM_EN "aclact1_rdcpu" -#define ACL_RSLT1_VID_MEM_EN_BOFFSET 29 -#define ACL_RSLT1_VID_MEM_EN_BLEN 1 -#define ACL_RSLT1_VID_MEM_EN_FLAG HSL_RW - -#define DES_PORT_EN "aclact1_rdcpu" -#define ACL_RSLT1_DES_PORT_EN_BOFFSET 28 -#define ACL_RSLT1_DES_PORT_EN_BLEN 1 -#define ACL_RSLT1_DES_PORT_EN_FLAG HSL_RW - -#define PORT_MEM "aclact1_rdcpu" -#define ACL_RSLT1_PORT_MEM_BOFFSET 20 -#define ACL_RSLT1_PORT_MEM_BLEN 7 -#define ACL_RSLT1_PORT_MEM_FLAG HSL_RW - -#define REMARK_PRI_QU "aclact1_rdcpu" -#define ACL_RSLT1_REMARK_PRI_QU_BOFFSET 19 -#define ACL_RSLT1_REMARK_PRI_QU_BLEN 1 -#define ACL_RSLT1_REMARK_PRI_QU_FLAG HSL_RW - -#define DOT1P "aclact1_rdcpu" -#define ACL_RSLT1_DOT1P_BOFFSET 16 -#define ACL_RSLT1_DOT1P_BLEN 3 -#define ACL_RSLT1_DOT1P_FLAG HSL_RW - -#define PRI_QU "aclact1_rdcpu" -#define ACL_RSLT1_PRI_QU_BOFFSET 14 -#define ACL_RSLT1_PRI_QU_BLEN 2 -#define ACL_RSLT1_PRI_QU_FLAG HSL_RW - -#define REMARK_DOT1P "aclact1_rdcpu" -#define ACL_RSLT1_REMARK_DOT1P_BOFFSET 13 -#define ACL_RSLT1_REMARK_DOT1P_BLEN 1 -#define ACL_RSLT1_REMARK_DOT1P_FLAG HSL_RW - -#define CHG_VID_EN "aclact1_rdcpu" -#define ACL_RSLT1_CHG_VID_EN_BOFFSET 12 -#define ACL_RSLT1_CHG_VID_EN_BLEN 1 -#define ACL_RSLT1_CHG_VID_EN_FLAG HSL_RW - -#define VID "aclact1_rdcpu" -#define ACL_RSLT1_VID_BOFFSET 0 -#define ACL_RSLT1_VID_BLEN 12 -#define ACL_RSLT1_VID_FLAG HSL_RW - - - - -#define ACL_RSLT2 "aclact2" -#define ACL_RSLT2_ID 13 -#define ACL_RSLT2_OFFSET 0x58008 -#define ACL_RSLT2_E_LENGTH 4 -#define ACL_RSLT2_E_OFFSET 0x20 -#define ACL_RSLT2_NR_E 32 - -#define RDTCPU "aclact2_rdtpu" -#define ACL_RSLT2_RDTCPU_BOFFSET 1 -#define ACL_RSLT2_RDTCPU_BLEN 1 -#define ACL_RSLT2_RDTCPU_FLAG HSL_RW - -#define CPYCPU "aclact2_cpcpu" -#define ACL_RSLT2_CPYCPU_BOFFSET 0 -#define ACL_RSLT2_CPYCPU_BLEN 1 -#define ACL_RSLT2_CPYCPU_FLAG HSL_RW - - - - - -#define RUL_SLCT0 "rulslct0" -#define RUL_SLCT0_ID 13 -#define RUL_SLCT0_OFFSET 0x58800 -#define RUL_SLCT0_E_LENGTH 4 -#define RUL_SLCT0_E_OFFSET 0x20 -#define RUL_SLCT0_NR_E 32 - -#define ADDR3_EN "rulslct_addr3en" -#define RUL_SLCT0_ADDR3_EN_BOFFSET 3 -#define RUL_SLCT0_ADDR3_EN_BLEN 1 -#define RUL_SLCT0_ADDR3_EN_FLAG HSL_RW - -#define ADDR2_EN "rulslct_addr2en" -#define RUL_SLCT0_ADDR2_EN_BOFFSET 2 -#define RUL_SLCT0_ADDR2_EN_BLEN 1 -#define RUL_SLCT0_ADDR2_EN_FLAG HSL_RW - -#define ADDR1_EN "rulslct_addr1en" -#define RUL_SLCT0_ADDR1_EN_BOFFSET 1 -#define RUL_SLCT0_ADDR1_EN_BLEN 1 -#define RUL_SLCT0_ADDR1_EN_FLAG HSL_RW - -#define ADDR0_EN "rulslct_addr0en" -#define RUL_SLCT0_ADDR0_EN_BOFFSET 0 -#define RUL_SLCT0_ADDR0_EN_BLEN 1 -#define RUL_SLCT0_ADDR0_EN_FLAG HSL_RW - - - - -#define RUL_SLCT1 "rulslct1" -#define RUL_SLCT1_ID 13 -#define RUL_SLCT1_OFFSET 0x58804 -#define RUL_SLCT1_E_LENGTH 4 -#define RUL_SLCT1_E_OFFSET 0x20 -#define RUL_SLCT1_NR_E 32 - -#define ADDR0 "rulslct1_addr0" -#define RUL_SLCT1_ADDR0_BOFFSET 0 -#define RUL_SLCT1_ADDR0_BLEN 5 -#define RUL_SLCT1_ADDR0_FLAG HSL_RW - - - - -#define RUL_SLCT2 "rulslct2" -#define RUL_SLCT2_ID 13 -#define RUL_SLCT2_OFFSET 0x58808 -#define RUL_SLCT2_E_LENGTH 4 -#define RUL_SLCT2_E_OFFSET 0x20 -#define RUL_SLCT2_NR_E 32 - -#define ADDR1 "rulslct2_addr1" -#define RUL_SLCT2_ADDR1_BOFFSET 0 -#define RUL_SLCT2_ADDR1_BLEN 5 -#define RUL_SLCT2_ADDR1_FLAG HSL_RW - - - - -#define RUL_SLCT3 "rulslct3" -#define RUL_SLCT3_ID 13 -#define RUL_SLCT3_OFFSET 0x5880c -#define RUL_SLCT3_E_LENGTH 4 -#define RUL_SLCT3_E_OFFSET 0x20 -#define RUL_SLCT3_NR_E 32 - -#define ADDR2 "rulslct3_addr2" -#define RUL_SLCT3_ADDR2_BOFFSET 0 -#define RUL_SLCT3_ADDR2_BLEN 5 -#define RUL_SLCT3_ADDR2_FLAG HSL_RW - - - - -#define RUL_SLCT4 "rulslct4" -#define RUL_SLCT4_ID 13 -#define RUL_SLCT4_OFFSET 0x58810 -#define RUL_SLCT4_E_LENGTH 4 -#define RUL_SLCT4_E_OFFSET 0x20 -#define RUL_SLCT4_NR_E 32 - -#define ADDR3 "rulslct4_addr3" -#define RUL_SLCT4_ADDR3_BOFFSET 0 -#define RUL_SLCT4_ADDR3_BLEN 5 -#define RUL_SLCT4_ADDR3_FLAG HSL_RW - - - - -#define RUL_SLCT5 "rulslct5" -#define RUL_SLCT5_ID 13 -#define RUL_SLCT5_OFFSET 0x58814 -#define RUL_SLCT5_E_LENGTH 4 -#define RUL_SLCT5_E_OFFSET 0x20 -#define RUL_SLCT5_NR_E 32 - -#define SRC_PT "rulslct5_srcpt" -#define RUL_SLCT5_SRC_PT_BOFFSET 0 -#define RUL_SLCT5_SRC_PT_BLEN 7 -#define RUL_SLCT5_SRC_PT_FLAG HSL_RW - - - - -#define RUL_SLCT6 "rulslct6" -#define RUL_SLCT6_ID 13 -#define RUL_SLCT6_OFFSET 0x58818 -#define RUL_SLCT6_E_LENGTH 4 -#define RUL_SLCT6_E_OFFSET 0x20 -#define RUL_SLCT6_NR_E 32 - -#define RULE_LEN "rulslct6_rulelen" -#define RUL_SLCT6_RULE_LEN_BOFFSET 0 -#define RUL_SLCT6_RULE_LEN_BLEN 8 -#define RUL_SLCT6_RULE_LEN_FLAG HSL_RW - - - - -#define RUL_SLCT7 "rulslct7" -#define RUL_SLCT7_ID 13 -#define RUL_SLCT7_OFFSET 0x5881c -#define RUL_SLCT7_E_LENGTH 4 -#define RUL_SLCT7_E_OFFSET 0x20 -#define RUL_SLCT7_NR_E 32 - -#define RULE_TYP "rulslct7_ruletyp" -#define RUL_SLCT7_RULE_TYP_BOFFSET 0 -#define RUL_SLCT7_RULE_TYP_BLEN 3 -#define RUL_SLCT7_RULE_TYP_FLAG HSL_RW - - - - -#define MAC_RUL_V0 "macrv0" -#define MAC_RUL_V0_ID 13 -#define MAC_RUL_V0_OFFSET 0x58400 -#define MAC_RUL_V0_E_LENGTH 4 -#define MAC_RUL_V0_E_OFFSET 0x20 -#define MAC_RUL_V0_NR_E 32 - -#define DAV_BYTE2 "macrv0_dav2" -#define MAC_RUL_V0_DAV_BYTE2_BOFFSET 24 -#define MAC_RUL_V0_DAV_BYTE2_BLEN 8 -#define MAC_RUL_V0_DAV_BYTE2_FLAG HSL_RW - -#define DAV_BYTE3 "macrv0_dav3" -#define MAC_RUL_V0_DAV_BYTE3_BOFFSET 16 -#define MAC_RUL_V0_DAV_BYTE3_BLEN 8 -#define MAC_RUL_V0_DAV_BYTE3_FLAG HSL_RW - -#define DAV_BYTE4 "macrv0_dav4" -#define MAC_RUL_V0_DAV_BYTE4_BOFFSET 8 -#define MAC_RUL_V0_DAV_BYTE4_BLEN 8 -#define MAC_RUL_V0_DAV_BYTE4_FLAG HSL_RW - -#define DAV_BYTE5 "macrv0_dav5" -#define MAC_RUL_V0_DAV_BYTE5_BOFFSET 0 -#define MAC_RUL_V0_DAV_BYTE5_BLEN 8 -#define MAC_RUL_V0_DAV_BYTE5_FLAG HSL_RW - - - - -#define MAC_RUL_V1 "macrv1" -#define MAC_RUL_V1_ID 13 -#define MAC_RUL_V1_OFFSET 0x58404 -#define MAC_RUL_V1_E_LENGTH 4 -#define MAC_RUL_V1_E_OFFSET 0x20 -#define MAC_RUL_V1_NR_E 32 - -#define SAV_BYTE4 "macrv1_sav4" -#define MAC_RUL_V1_SAV_BYTE4_BOFFSET 24 -#define MAC_RUL_V1_SAV_BYTE4_BLEN 8 -#define MAC_RUL_V1_SAV_BYTE4_FLAG HSL_RW - -#define SAV_BYTE5 "macrv1_sav5" -#define MAC_RUL_V1_SAV_BYTE5_BOFFSET 16 -#define MAC_RUL_V1_SAV_BYTE5_BLEN 8 -#define MAC_RUL_V1_SAV_BYTE5_FLAG HSL_RW - -#define DAV_BYTE0 "macrv1_dav0" -#define MAC_RUL_V1_DAV_BYTE0_BOFFSET 8 -#define MAC_RUL_V1_DAV_BYTE0_BLEN 8 -#define MAC_RUL_V1_DAV_BYTE0_FLAG HSL_RW - -#define DAV_BYTE1 "macrv1_dav1" -#define MAC_RUL_V1_DAV_BYTE1_BOFFSET 0 -#define MAC_RUL_V1_DAV_BYTE1_BLEN 8 -#define MAC_RUL_V1_DAV_BYTE1_FLAG HSL_RW - - - - -#define MAC_RUL_V2 "macrv2" -#define MAC_RUL_V2_ID 13 -#define MAC_RUL_V2_OFFSET 0x58408 -#define MAC_RUL_V2_E_LENGTH 4 -#define MAC_RUL_V2_E_OFFSET 0x20 -#define MAC_RUL_V2_NR_E 32 - -#define SAV_BYTE0 "macrv2_sav0" -#define MAC_RUL_V2_SAV_BYTE0_BOFFSET 24 -#define MAC_RUL_V2_SAV_BYTE0_BLEN 8 -#define MAC_RUL_V2_SAV_BYTE0_FLAG HSL_RW - -#define SAV_BYTE1 "macrv2_sav1" -#define MAC_RUL_V2_SAV_BYTE1_BOFFSET 16 -#define MAC_RUL_V2_SAV_BYTE1_BLEN 8 -#define MAC_RUL_V2_SAV_BYTE1_FLAG HSL_RW - -#define SAV_BYTE2 "macrv2_sav2" -#define MAC_RUL_V2_SAV_BYTE2_BOFFSET 8 -#define MAC_RUL_V2_SAV_BYTE2_BLEN 8 -#define MAC_RUL_V2_SAV_BYTE2_FLAG HSL_RW - -#define SAV_BYTE3 "macrv2_sav3" -#define MAC_RUL_V2_SAV_BYTE3_BOFFSET 0 -#define MAC_RUL_V2_SAV_BYTE3_BLEN 8 -#define MAC_RUL_V2_SAV_BYTE3_FLAG HSL_RW - - - - -#define MAC_RUL_V3 "macrv3" -#define MAC_RUL_V3_ID 13 -#define MAC_RUL_V3_OFFSET 0x5840c -#define MAC_RUL_V3_E_LENGTH 4 -#define MAC_RUL_V3_E_OFFSET 0x20 -#define MAC_RUL_V3_NR_E 32 - -#define ETHTYPV "macrv3_ethtypv" -#define MAC_RUL_V3_ETHTYPV_BOFFSET 16 -#define MAC_RUL_V3_ETHTYPV_BLEN 16 -#define MAC_RUL_V3_ETHTYPV_FLAG HSL_RW - -#define VLANPRIV "macrv3_vlanpriv" -#define MAC_RUL_V3_VLANPRIV_BOFFSET 13 -#define MAC_RUL_V3_VLANPRIV_BLEN 3 -#define MAC_RUL_V3_VLANPRIV_FLAG HSL_RW - -#define VLANCFIV "macrv3_vlancfiv" -#define MAC_RUL_V3_VLANCFIV_BOFFSET 12 -#define MAC_RUL_V3_VLANCFIV_BLEN 1 -#define MAC_RUL_V3_VLANCFIV_FLAG HSL_RW - -#define VLANIDV "macrv3_vlanidv" -#define MAC_RUL_V3_VLANIDV_BOFFSET 0 -#define MAC_RUL_V3_VLANIDV_BLEN 12 -#define MAC_RUL_V3_VLANIDV_FLAG HSL_RW - - - - -#define MAC_RUL_V4 "macrv4" -#define MAC_RUL_V4_ID 13 -#define MAC_RUL_V4_OFFSET 0x58410 -#define MAC_RUL_V4_E_LENGTH 4 -#define MAC_RUL_V4_E_OFFSET 0x20 -#define MAC_RUL_V4_NR_E 32 - -#define TAGGEDM "macrv4_vlanid" -#define MAC_RUL_V4_TAGGEDM_BOFFSET 7 -#define MAC_RUL_V4_TAGGEDM_BLEN 1 -#define MAC_RUL_V4_TAGGEDM_FLAG HSL_RW - -#define TAGGEDV "macrv4_vlanid" -#define MAC_RUL_V4_TAGGEDV_BOFFSET 6 -#define MAC_RUL_V4_TAGGEDV_BLEN 1 -#define MAC_RUL_V4_TAGGEDV_FLAG HSL_RW - -#define VIDMSK "macrv4_vidmsk" -#define MAC_RUL_V4_VIDMSK_BOFFSET 0 -#define MAC_RUL_V4_VIDMSK_BLEN 1 -#define MAC_RUL_V4_VIDMSK_FLAG HSL_RW - - - - - -#define MAC_RUL_M0 "macrv0" -#define MAC_RUL_M0_ID 13 -#define MAC_RUL_M0_OFFSET 0x58c00 -#define MAC_RUL_M0_E_LENGTH 4 -#define MAC_RUL_M0_E_OFFSET 0x20 -#define MAC_RUL_M0_NR_E 32 - -#define DAM_BYTE2 "macrv0_dam2" -#define MAC_RUL_M0_DAM_BYTE2_BOFFSET 24 -#define MAC_RUL_M0_DAM_BYTE2_BLEN 8 -#define MAC_RUL_M0_DAM_BYTE2_FLAG HSL_RW - -#define DAM_BYTE3 "macrv0_dam3" -#define MAC_RUL_M0_DAM_BYTE3_BOFFSET 16 -#define MAC_RUL_M0_DAM_BYTE3_BLEN 8 -#define MAC_RUL_M0_DAM_BYTE3_FLAG HSL_RW - -#define DAM_BYTE4 "macrv0_dam4" -#define MAC_RUL_M0_DAM_BYTE4_BOFFSET 8 -#define MAC_RUL_M0_DAM_BYTE4_BLEN 8 -#define MAC_RUL_M0_DAM_BYTE4_FLAG HSL_RW - -#define DAM_BYTE5 "macrv0_dam5" -#define MAC_RUL_M0_DAM_BYTE5_BOFFSET 0 -#define MAC_RUL_M0_DAM_BYTE5_BLEN 8 -#define MAC_RUL_M0_DAM_BYTE5_FLAG HSL_RW - - - - -#define MAC_RUL_M1 "macrm1" -#define MAC_RUL_M1_ID 13 -#define MAC_RUL_M1_OFFSET 0x58c04 -#define MAC_RUL_M1_E_LENGTH 4 -#define MAC_RUL_M1_E_OFFSET 0x20 -#define MAC_RUL_M1_NR_E 32 - -#define SAM_BYTE4 "macrm1_sam4" -#define MAC_RUL_M1_SAM_BYTE4_BOFFSET 24 -#define MAC_RUL_M1_SAM_BYTE4_BLEN 8 -#define MAC_RUL_M1_SAM_BYTE4_FLAG HSL_RW - -#define SAM_BYTE5 "macrm1_sam5" -#define MAC_RUL_M1_SAM_BYTE5_BOFFSET 16 -#define MAC_RUL_M1_SAM_BYTE5_BLEN 8 -#define MAC_RUL_M1_SAM_BYTE5_FLAG HSL_RW - -#define DAM_BYTE0 "macrm1_dam0" -#define MAC_RUL_M1_DAM_BYTE0_BOFFSET 8 -#define MAC_RUL_M1_DAM_BYTE0_BLEN 8 -#define MAC_RUL_M1_DAM_BYTE0_FLAG HSL_RW - -#define DAM_BYTE1 "macrm1_dam1" -#define MAC_RUL_M1_DAM_BYTE1_BOFFSET 0 -#define MAC_RUL_M1_DAM_BYTE1_BLEN 8 -#define MAC_RUL_M1_DAM_BYTE1_FLAG HSL_RW - - - - -#define MAC_RUL_M2 "macrm2" -#define MAC_RUL_M2_ID 13 -#define MAC_RUL_M2_OFFSET 0x58c08 -#define MAC_RUL_M2_E_LENGTH 4 -#define MAC_RUL_M2_E_OFFSET 0x20 -#define MAC_RUL_M2_NR_E 32 - -#define SAM_BYTE0 "macrm2_sam0" -#define MAC_RUL_M2_SAM_BYTE0_BOFFSET 24 -#define MAC_RUL_M2_SAM_BYTE0_BLEN 8 -#define MAC_RUL_M2_SAM_BYTE0_FLAG HSL_RW - -#define SAM_BYTE1 "macrm2_samv1" -#define MAC_RUL_M2_SAM_BYTE1_BOFFSET 16 -#define MAC_RUL_M2_SAM_BYTE1_BLEN 8 -#define MAC_RUL_M2_SAM_BYTE1_FLAG HSL_RW - -#define SAM_BYTE2 "macrm2_sam2" -#define MAC_RUL_M2_SAM_BYTE2_BOFFSET 8 -#define MAC_RUL_M2_SAM_BYTE2_BLEN 8 -#define MAC_RUL_M2_SAM_BYTE2_FLAG HSL_RW - -#define SAM_BYTE3 "macrm2_sam3" -#define MAC_RUL_M2_SAM_BYTE3_BOFFSET 0 -#define MAC_RUL_M2_SAM_BYTE3_BLEN 8 -#define MAC_RUL_M2_SAM_BYTE3_FLAG HSL_RW - - - - -#define MAC_RUL_M3 "macrv3" -#define MAC_RUL_M3_ID 13 -#define MAC_RUL_M3_OFFSET 0x58c0c -#define MAC_RUL_M3_E_LENGTH 4 -#define MAC_RUL_M3_E_OFFSET 0x20 -#define MAC_RUL_M3_NR_E 32 - -#define ETHTYPM "macrm3_ethtypm" -#define MAC_RUL_M3_ETHTYPM_BOFFSET 16 -#define MAC_RUL_M3_ETHTYPM_BLEN 16 -#define MAC_RUL_M3_ETHTYPM_FLAG HSL_RW - -#define VLANPRIM "macrm3_vlanprim" -#define MAC_RUL_M3_VLANPRIM_BOFFSET 13 -#define MAC_RUL_M3_VLANPRIM_BLEN 3 -#define MAC_RUL_M3_VLANPRIM_FLAG HSL_RW - -#define VLANCFIM "macrm3_vlancfim" -#define MAC_RUL_M3_VLANCFIM_BOFFSET 12 -#define MAC_RUL_M3_VLANCFIM_BLEN 1 -#define MAC_RUL_M3_VLANCFIM_FLAG HSL_RW - -#define VLANIDM "macrm3_vlanidm" -#define MAC_RUL_M3_VLANIDM_BOFFSET 0 -#define MAC_RUL_M3_VLANIDM_BLEN 12 -#define MAC_RUL_M3_VLANIDM_FLAG HSL_RW - - - - -#define IP4_RUL_V0 "ip4v0" -#define IP4_RUL_V0_ID 13 -#define IP4_RUL_V0_OFFSET 0x58400 -#define IP4_RUL_V0_E_LENGTH 4 -#define IP4_RUL_V0_E_OFFSET 0x20 -#define IP4_RUL_V0_NR_E 32 - -#define DIPV "ip4v0_dipv" -#define IP4_RUL_V0_DIPV_BOFFSET 0 -#define IP4_RUL_V0_DIPV_BLEN 32 -#define IP4_RUL_V0_DIPV_FLAG HSL_RW - - - - -#define IP4_RUL_V1 "ip4v1" -#define IP4_RUL_V1_ID 13 -#define IP4_RUL_V1_OFFSET 0x58404 -#define IP4_RUL_V1_E_LENGTH 4 -#define IP4_RUL_V1_E_OFFSET 0x20 -#define IP4_RUL_V1_NR_E 32 - -#define SIPV "ip4v1_sipv" -#define IP4_RUL_V1_SIPV_BOFFSET 0 -#define IP4_RUL_V1_SIPV_BLEN 32 -#define IP4_RUL_V1_SIPV_FLAG HSL_RW - - - - -#define IP4_RUL_V2 "ip4v2" -#define IP4_RUL_V2_ID 13 -#define IP4_RUL_V2_OFFSET 0x58408 -#define IP4_RUL_V2_E_LENGTH 4 -#define IP4_RUL_V2_E_OFFSET 0x20 -#define IP4_RUL_V2_NR_E 32 - -#define IP4PROTV "ip4v2_protv" -#define IP4_RUL_V2_IP4PROTV_BOFFSET 0 -#define IP4_RUL_V2_IP4PROTV_BLEN 8 -#define IP4_RUL_V2_IP4PROTV_FLAG HSL_RW - -#define IP4DSCPV "ip4v2_dscpv" -#define IP4_RUL_V2_IP4DSCPV_BOFFSET 8 -#define IP4_RUL_V2_IP4DSCPV_BLEN 8 -#define IP4_RUL_V2_IP4DSCPV_FLAG HSL_RW - -#define IP4DPORTV "ip4v2_dportv" -#define IP4_RUL_V2_IP4DPORTV_BOFFSET 16 -#define IP4_RUL_V2_IP4DPORTV_BLEN 16 -#define IP4_RUL_V2_IP4DPORTV_FLAG HSL_RW - - - - -#define IP4_RUL_V3 "ip4v3" -#define IP4_RUL_V3_ID 13 -#define IP4_RUL_V3_OFFSET 0x5840c -#define IP4_RUL_V3_E_LENGTH 4 -#define IP4_RUL_V3_E_OFFSET 0x20 -#define IP4_RUL_V3_NR_E 32 - -#define IP4SPORTV "ip4v3_sportv" -#define IP4_RUL_V3_IP4SPORTV_BOFFSET 0 -#define IP4_RUL_V3_IP4SPORTV_BLEN 16 -#define IP4_RUL_V3_IP4SPORTV_FLAG HSL_RW - - -#define IP4_RUL_V4 "ip4v2" -#define IP4_RUL_V4_ID 13 -#define IP4_RUL_V4_OFFSET 0x58410 -#define IP4_RUL_V4_E_LENGTH 4 -#define IP4_RUL_V4_E_OFFSET 0x20 -#define IP4_RUL_V4_NR_E 32 - -#define IP4_INPT "ip4rv4_inpt" -#define IP4_RUL_V4_IP4_INPT_BOFFSET 0 -#define IP4_RUL_V4_IP4_INPT_BLEN 6 -#define IP4_RUL_V4_IP4_INPT_FLAG HSL_RW - - - - - - -#define IP4_RUL_M0 "ip4m0" -#define IP4_RUL_M0_ID 13 -#define IP4_RUL_M0_OFFSET 0x58c00 -#define IP4_RUL_M0_E_LENGTH 4 -#define IP4_RUL_M0_E_OFFSET 0x20 -#define IP4_RUL_M0_NR_E 32 - -#define DIPM "ip4m0_dipm" -#define IP4_RUL_M0_DIPM_BOFFSET 0 -#define IP4_RUL_M0_DIPM_BLEN 32 -#define IP4_RUL_M0_DIPM_FLAG HSL_RW - - - - -#define IP4_RUL_M1 "ip4m1" -#define IP4_RUL_M1_ID 13 -#define IP4_RUL_M1_OFFSET 0x58c04 -#define IP4_RUL_M1_E_LENGTH 4 -#define IP4_RUL_M1_E_OFFSET 0x20 -#define IP4_RUL_M1_NR_E 32 - -#define SIPM "ip4m1_sipm" -#define IP4_RUL_M1_SIPM_BOFFSET 0 -#define IP4_RUL_M1_SIPM_BLEN 32 -#define IP4_RUL_M1_SIPM_FLAG HSL_RW - - - - -#define IP4_RUL_M2 "ip4m2" -#define IP4_RUL_M2_ID 13 -#define IP4_RUL_M2_OFFSET 0x58c08 -#define IP4_RUL_M2_E_LENGTH 4 -#define IP4_RUL_M2_E_OFFSET 0x20 -#define IP4_RUL_M2_NR_E 32 - -#define IP4PROTM "ip4m2_protm" -#define IP4_RUL_M2_IP4PROTM_BOFFSET 0 -#define IP4_RUL_M2_IP4PROTM_BLEN 8 -#define IP4_RUL_M2_IP4PROTM_FLAG HSL_RW - -#define IP4DSCPM "ip4m2_dscpm" -#define IP4_RUL_M2_IP4DSCPM_BOFFSET 8 -#define IP4_RUL_M2_IP4DSCPM_BLEN 8 -#define IP4_RUL_M2_IP4DSCPM_FLAG HSL_RW - -#define IP4DPORTM "ip4m2_dportm" -#define IP4_RUL_M2_IP4DPORTM_BOFFSET 16 -#define IP4_RUL_M2_IP4DPORTM_BLEN 16 -#define IP4_RUL_M2_IP4DPORTM_FLAG HSL_RW - - - - -#define IP4_RUL_M3 "ip4m3" -#define IP4_RUL_M3_ID 13 -#define IP4_RUL_M3_OFFSET 0x58c0c -#define IP4_RUL_M3_E_LENGTH 4 -#define IP4_RUL_M3_E_OFFSET 0x20 -#define IP4_RUL_M3_NR_E 32 - -#define IP4SPORTM "ip4m3_sportm" -#define IP4_RUL_M3_IP4SPORTM_BOFFSET 0 -#define IP4_RUL_M3_IP4SPORTM_BLEN 16 -#define IP4_RUL_M3_IP4SPORTM_FLAG HSL_RW - -#define IP4SPORTM_EN "ip4m3_sportmen" -#define IP4_RUL_M3_IP4SPORTM_EN_BOFFSET 16 -#define IP4_RUL_M3_IP4SPORTM_EN_BLEN 1 -#define IP4_RUL_M3_IP4SPORTM_EN_FLAG HSL_RW - -#define IP4DPORTM_EN "ip4m3_dportmen" -#define IP4_RUL_M3_IP4DPORTM_EN_BOFFSET 17 -#define IP4_RUL_M3_IP4DPORTM_EN_BLEN 1 -#define IP4_RUL_M3_IP4DPORTM_EN_FLAG HSL_RW - - - - -#define IP6_RUL1_V0 "ip6r1v0" -#define IP6_RUL1_V0_ID 13 -#define IP6_RUL1_V0_OFFSET 0x58400 -#define IP6_RUL1_V0_E_LENGTH 4 -#define IP6_RUL1_V0_E_OFFSET 0x20 -#define IP6_RUL1_V0_NR_E 32 - -#define IP6_DIPV0 "ip6r1v0_dipv0" -#define IP6_RUL1_V0_IP6_DIPV0_BOFFSET 0 -#define IP6_RUL1_V0_IP6_DIPV0_BLEN 32 -#define IP6_RUL1_V0_IP6_DIPV0_FLAG HSL_RW - - - - -#define IP6_RUL1_V1 "ip6r1v1" -#define IP6_RUL1_V1_ID 13 -#define IP6_RUL1_V1_OFFSET 0x58404 -#define IP6_RUL1_V1_E_LENGTH 4 -#define IP6_RUL1_V1_E_OFFSET 0x20 -#define IP6_RUL1_V1_NR_E 32 - -#define IP6_DIPV1 "ip6r1v1_dipv1" -#define IP6_RUL1_V1_IP6_DIPV1_BOFFSET 0 -#define IP6_RUL1_V1_IP6_DIPv1_BLEN 32 -#define IP6_RUL1_V1_IP6_DIPV1_FLAG HSL_RW - - - -#define IP6_RUL1_V2 "ip6r1v2" -#define IP6_RUL1_V2_ID 13 -#define IP6_RUL1_V2_OFFSET 0x58408 -#define IP6_RUL1_V2_E_LENGTH 4 -#define IP6_RUL1_V2_E_OFFSET 0x20 -#define IP6_RUL1_V2_NR_E 32 - -#define IP6_DIPV2 "ip6r1v2_dipv2" -#define IP6_RUL1_V2_IP6_DIPV2_BOFFSET 0 -#define IP6_RUL1_V2_IP6_DIPv2_BLEN 32 -#define IP6_RUL1_V2_IP6_DIPV2_FLAG HSL_RW - - - - -#define IP6_RUL1_V3 "ip6r1v3" -#define IP6_RUL1_V3_ID 13 -#define IP6_RUL1_V3_OFFSET 0x5840c -#define IP6_RUL1_V3_E_LENGTH 4 -#define IP6_RUL1_V3_E_OFFSET 0x20 -#define IP6_RUL1_V3_NR_E 32 - -#define IP6_DIPV3 "ip6r1v3_dipv3" -#define IP6_RUL1_V3_IP6_DIPV3_BOFFSET 0 -#define IP6_RUL1_V3_IP6_DIPv3_BLEN 32 -#define IP6_RUL1_V3_IP6_DIPV3_FLAG HSL_RW - - - - -#define IP6_RUL1_V4 "ip6r1v4" -#define IP6_RUL1_V4_ID 13 -#define IP6_RUL1_V4_OFFSET 0x58410 -#define IP6_RUL1_V4_E_LENGTH 4 -#define IP6_RUL1_V4_E_OFFSET 0x20 -#define IP6_RUL1_V4_NR_E 32 - -#define IP6_RUL1_INPT "ip6r1v4_inpt" -#define IP6_RUL1_V4_IP6_RUL1_INPT_BOFFSET 0 -#define IP6_RUL1_V4_IP6_RUL1_INPT_BLEN 6 -#define IP6_RUL1_V4_IP6_RUL1_INPT_FLAG HSL_RW - - - - - -#define IP6_RUL1_M0 "ip6r1m0" -#define IP6_RUL1_M0_ID 13 -#define IP6_RUL1_M0_OFFSET 0x58c00 -#define IP6_RUL1_M0_E_LENGTH 4 -#define IP6_RUL1_M0_E_OFFSET 0x20 -#define IP6_RUL1_M0_NR_E 32 - -#define IP6_DIPM0 "ip6r1m0_dipm0" -#define IP6_RUL1_M0_IP6_DIPM0_BOFFSET 0 -#define IP6_RUL1_M0_IP6_DIPM0_BLEN 32 -#define IP6_RUL1_M0_IP6_DIPM0_FLAG HSL_RW - - - - -#define IP6_RUL1_M1 "ip6r1m1" -#define IP6_RUL1_M1_ID 13 -#define IP6_RUL1_M1_OFFSET 0x58c04 -#define IP6_RUL1_M1_E_LENGTH 4 -#define IP6_RUL1_M1_E_OFFSET 0x20 -#define IP6_RUL1_M1_NR_E 32 - -#define IP6_DIPM1 "ip6r1m1_dipm1" -#define IP6_RUL1_M1_IP6_DIPM1_BOFFSET 0 -#define IP6_RUL1_M1_IP6_DIPM1_BLEN 32 -#define IP6_RUL1_M1_IP6_DIPM1_FLAG HSL_RW - - - -#define IP6_RUL1_M2 "ip6r1m2" -#define IP6_RUL1_M2_ID 13 -#define IP6_RUL1_M2_OFFSET 0x58c08 -#define IP6_RUL1_M2_E_LENGTH 4 -#define IP6_RUL1_M2_E_OFFSET 0x20 -#define IP6_RUL1_M2_NR_E 32 - -#define IP6_DIPM2 "ip6r1m2_dipm2" -#define IP6_RUL1_M2_IP6_DIPM2_BOFFSET 0 -#define IP6_RUL1_M2_IP6_DIPM2_BLEN 32 -#define IP6_RUL1_M2_IP6_DIPM2_FLAG HSL_RW - - - - -#define IP6_RUL1_M3 "ip6r1m3" -#define IP6_RUL1_M3_ID 13 -#define IP6_RUL1_M3_OFFSET 0x58c0c -#define IP6_RUL1_M3_E_LENGTH 4 -#define IP6_RUL1_M3_E_OFFSET 0x20 -#define IP6_RUL1_M3_NR_E 32 - -#define IP6_DIPM3 "ip6r1m3_dipm3" -#define IP6_RUL1_M3_IP6_DIPM3_BOFFSET 0 -#define IP6_RUL1_M3_IP6_DIPM3_BLEN 32 -#define IP6_RUL1_M3_IP6_DIPM3_FLAG HSL_RW - - - - - -#define IP6_RUL2_V0 "ip6r2v0" -#define IP6_RUL2_V0_ID 13 -#define IP6_RUL2_V0_OFFSET 0x58400 -#define IP6_RUL2_V0_E_LENGTH 4 -#define IP6_RUL2_V0_E_OFFSET 0x20 -#define IP6_RUL2_V0_NR_E 32 - -#define IP6_SIPV0 "ip6r2v0_sipv0" -#define IP6_RUL2_V0_IP6_SIPV0_BOFFSET 0 -#define IP6_RUL2_V0_IP6_SIPv0_BLEN 32 -#define IP6_RUL2_V0_IP6_SIPV0_FLAG HSL_RW - - - - -#define IP6_RUL2_V1 "ip6r2v1" -#define IP6_RUL2_V1_ID 13 -#define IP6_RUL2_V1_OFFSET 0x58404 -#define IP6_RUL2_V1_E_LENGTH 4 -#define IP6_RUL2_V1_E_OFFSET 0x20 -#define IP6_RUL2_V1_NR_E 32 - -#define IP6_SIPV1 "ip6r2v1_sipv1" -#define IP6_RUL2_V1_IP6_SIPV1_BOFFSET 0 -#define IP6_RUL2_V1_IP6_SIPv1_BLEN 32 -#define IP6_RUL2_V1_IP6_SIPV1_FLAG HSL_RW - - - -#define IP6_RUL2_V2 "ip6r2v2" -#define IP6_RUL2_V2_ID 13 -#define IP6_RUL2_V2_OFFSET 0x58408 -#define IP6_RUL2_V2_E_LENGTH 4 -#define IP6_RUL2_V2_E_OFFSET 0x20 -#define IP6_RUL2_V2_NR_E 32 - -#define IP6_SIPV2 "ip6r2v2_sipv2" -#define IP6_RUL2_V2_IP6_SIPV2_BOFFSET 0 -#define IP6_RUL2_V2_IP6_SIPv2_BLEN 32 -#define IP6_RUL2_V2_IP6_SIPV2_FLAG HSL_RW - - - - -#define IP6_RUL2_V3 "ip6r2v3" -#define IP6_RUL2_V3_ID 13 -#define IP6_RUL2_V3_OFFSET 0x5840c -#define IP6_RUL2_V3_E_LENGTH 4 -#define IP6_RUL2_V3_E_OFFSET 0x20 -#define IP6_RUL2_V3_NR_E 32 - -#define IP6_SIPV3 "ip6r2v3_sipv3" -#define IP6_RUL2_V3_IP6_SIPV3_BOFFSET 0 -#define IP6_RUL2_V3_IP6_SIPv3_BLEN 32 -#define IP6_RUL2_V3_IP6_SIPV3_FLAG HSL_RW - - - - -#define IP6_RUL2_V4 "ip6r2v4" -#define IP6_RUL2_V4_ID 13 -#define IP6_RUL2_V4_OFFSET 0x58410 -#define IP6_RUL2_V4_E_LENGTH 4 -#define IP6_RUL2_V4_E_OFFSET 0x20 -#define IP6_RUL2_V4_NR_E 32 - -#define IP6_RUL2_INPT "ip6r2v4_inptm" -#define IP6_RUL2_V4_IP6_RUL2_INPT_BOFFSET 0 -#define IP6_RUL2_V4_IP6_RUL2_INPT_BLEN 6 -#define IP6_RUL2_V4_IP6_RUL2_INPT_FLAG HSL_RW - - - - -#define IP6_RUL2_M0 "ip6r2m0" -#define IP6_RUL2_M0_ID 13 -#define IP6_RUL2_M0_OFFSET 0x58c00 -#define IP6_RUL2_M0_E_LENGTH 4 -#define IP6_RUL2_M0_E_OFFSET 0x20 -#define IP6_RUL2_M0_NR_E 32 - -#define IP6_SIPM0 "ip6r2m0_sipm0" -#define IP6_RUL2_M0_IP6_SIPM0_BOFFSET 0 -#define IP6_RUL2_M0_IP6_SIPM0_BLEN 32 -#define IP6_RUL2_M0_IP6_SIPM0_FLAG HSL_RW - - - - -#define IP6_RUL2_M1 "ip6r2m1" -#define IP6_RUL2_M1_ID 13 -#define IP6_RUL2_M1_OFFSET 0x58c04 -#define IP6_RUL2_M1_E_LENGTH 4 -#define IP6_RUL2_M1_E_OFFSET 0x20 -#define IP6_RUL2_M1_NR_E 32 - -#define IP6_SIPM1 "ip6r2m1_sipm1" -#define IP6_RUL2_M1_IP6_DIPM1_BOFFSET 0 -#define IP6_RUL2_M1_IP6_DIPM1_BLEN 32 -#define IP6_RUL2_M1_IP6_DIPM1_FLAG HSL_RW - - - -#define IP6_RUL2_M2 "ip6r2m2" -#define IP6_RUL2_M2_ID 13 -#define IP6_RUL2_M2_OFFSET 0x58c08 -#define IP6_RUL2_M2_E_LENGTH 4 -#define IP6_RUL2_M2_E_OFFSET 0x20 -#define IP6_RUL2_M2_NR_E 32 - -#define IP6_SIPM2 "ip6r2m2_sipm2" -#define IP6_RUL2_M2_IP6_DIPM2_BOFFSET 0 -#define IP6_RUL2_M2_IP6_DIPM2_BLEN 32 -#define IP6_RUL2_M2_IP6_DIPM2_FLAG HSL_RW - - - - -#define IP6_RUL2_M3 "ip6r2m3" -#define IP6_RUL2_M3_ID 13 -#define IP6_RUL2_M3_OFFSET 0x58c0c -#define IP6_RUL2_M3_E_LENGTH 4 -#define IP6_RUL2_M3_E_OFFSET 0x20 -#define IP6_RUL2_M3_NR_E 32 - -#define IP6_SIPM3 "ip6r2m3_sipm3" -#define IP6_RUL2_M3_IP6_SIPM3_BOFFSET 0 -#define IP6_RUL2_M3_IP6_SIPM3_BLEN 32 -#define IP6_RUL2_M3_IP6_SIPM3_FLAG HSL_RW - - - - - -#define IP6_RUL3_V0 "ip6r3v0" -#define IP6_RUL3_V0_ID 13 -#define IP6_RUL3_V0_OFFSET 0x58400 -#define IP6_RUL3_V0_E_LENGTH 4 -#define IP6_RUL3_V0_E_OFFSET 0x20 -#define IP6_RUL3_V0_NR_E 32 - -#define IP6PROTV "ip6r3v0_protv" -#define IP6_RUL3_V0_IP6PROTV_BOFFSET 0 -#define IP6_RUL3_V0_IP6PROTV_BLEN 8 -#define IP6_RUL3_V0_IP6PROTV_FLAG HSL_RW - -#define IP6DSCPV "ip6r3v0_dscpv" -#define IP6_RUL3_V0_IP6DSCPV_BOFFSET 8 -#define IP6_RUL3_V0_IP6DSCPV_BLEN 8 -#define IP6_RUL3_V0_IP6DSCPV_FLAG HSL_RW - - - - -#define IP6_RUL3_V1 "ip6r3v1" -#define IP6_RUL3_V1_ID 13 -#define IP6_RUL3_V1_OFFSET 0x58404 -#define IP6_RUL3_V1_E_LENGTH 4 -#define IP6_RUL3_V1_E_OFFSET 0x20 -#define IP6_RUL3_V1_NR_E 32 - -#define IP6LABEL1V "ip6r3v1_label1v" -#define IP6_RUL3_V1_IP6LABEL1V_BOFFSET 16 -#define IP6_RUL3_V1_IP6LABEL1V_BLEN 16 -#define IP6_RUL3_V1_IP6LABEL1V_FLAG HSL_RW - - - - -#define IP6_RUL3_V2 "ip6r3v2" -#define IP6_RUL3_V2_ID 13 -#define IP6_RUL3_V2_OFFSET 0x58408 -#define IP6_RUL3_V2_E_LENGTH 4 -#define IP6_RUL3_V2_E_OFFSET 0x20 -#define IP6_RUL3_V2_NR_E 32 - -#define IP6LABEL2V "ip6r3v2_label2v" -#define IP6_RUL3_V2_IP6LABEL2V_BOFFSET 0 -#define IP6_RUL3_V2_IP6LABEL2V_BLEN 4 -#define IP6_RUL3_V2_IP6LABEL2V_FLAG HSL_RW - -#define IP6DPORTV "ip6r3v2_dportv" -#define IP6_RUL3_V2_IP6DPORTV_BOFFSET 16 -#define IP6_RUL3_V2_IP6DPORTV_BLEN 16 -#define IP6_RUL3_V2_IP6DPORTV_FLAG HSL_RW - - - - -#define IP6_RUL3_V3 "ip6r3v3" -#define IP6_RUL3_V3_ID 13 -#define IP6_RUL3_V3_OFFSET 0x5840c -#define IP6_RUL3_V3_E_LENGTH 4 -#define IP6_RUL3_V3_E_OFFSET 0x20 -#define IP6_RUL3_V3_NR_E 32 - -#define IP6SPORTV "ip6r3v3_sportv" -#define IP6_RUL3_V3_IP6SPORTV_BOFFSET 0 -#define IP6_RUL3_V3_IP6SPORTV_BLEN 16 -#define IP6_RUL3_V3_IP6SPORTV_FLAG HSL_RW - - - -#define IP6_RUL3_M0 "ip6r3m0" -#define IP6_RUL3_M0_ID 13 -#define IP6_RUL3_M0_OFFSET 0x58c00 -#define IP6_RUL3_M0_E_LENGTH 4 -#define IP6_RUL3_M0_E_OFFSET 0x20 -#define IP6_RUL3_M0_NR_E 32 - -#define IP6PROTM "ip6r3m0_protm" -#define IP6_RUL3_M0_IP6PROTM_BOFFSET 0 -#define IP6_RUL3_M0_IP6PROTM_BLEN 8 -#define IP6_RUL3_M0_IP6PROTM_FLAG HSL_RW - -#define IP6DSCPM "ip6r3m0_dscpm" -#define IP6_RUL3_M0_IP6DSCPM_BOFFSET 8 -#define IP6_RUL3_M0_IP6DSCPM_BLEN 8 -#define IP6_RUL3_M0_IP6DSCPM_FLAG HSL_RW - - - - -#define IP6_RUL3_M1 "ip6r3m1" -#define IP6_RUL3_M1_ID 13 -#define IP6_RUL3_M1_OFFSET 0x58c04 -#define IP6_RUL3_M1_E_LENGTH 4 -#define IP6_RUL3_M1_E_OFFSET 0x20 -#define IP6_RUL3_M1_NR_E 32 - -#define IP6LABEL1M "ip6r3m1_label1m" -#define IP6_RUL3_M1_IP6LABEL1M_BOFFSET 16 -#define IP6_RUL3_M1_IP6LABEL1M_BLEN 16 -#define IP6_RUL3_M1_IP6LABEL1M_FLAG HSL_RW - - - - -#define IP6_RUL3_M2 "ip6r3m2" -#define IP6_RUL3_M2_ID 13 -#define IP6_RUL3_M2_OFFSET 0x58c08 -#define IP6_RUL3_M2_E_LENGTH 4 -#define IP6_RUL3_M2_E_OFFSET 0x20 -#define IP6_RUL3_M2_NR_E 32 - -#define IP6LABEL2M "ip6r3m2_label2m" -#define IP6_RUL3_M2_IP6LABEL2M_BOFFSET 0 -#define IP6_RUL3_M2_IP6LABEL2M_BLEN 4 -#define IP6_RUL3_M2_IP6LABEL21M_FLAG HSL_RW - -#define IP6DPORTM "ip6r3m2_dportm" -#define IP6_RUL3_M2_IP6DPORTM_BOFFSET 16 -#define IP6_RUL3_M2_IP6DPORTM_BLEN 16 -#define IP6_RUL3_M2_IP6DPORTM_FLAG HSL_RW - - - - -#define IP6_RUL3_M3 "ip6r3m3" -#define IP6_RUL3_M3_ID 13 -#define IP6_RUL3_M3_OFFSET 0x58c0c -#define IP6_RUL3_M3_E_LENGTH 4 -#define IP6_RUL3_M3_E_OFFSET 0x20 -#define IP6_RUL3_M3_NR_E 32 - -#define IP6SPORTM "ip6r3m3_sportm" -#define IP6_RUL3_M3_IP6SPORTM_BOFFSET 0 -#define IP6_RUL3_M3_IP6SPORTM_BLEN 16 -#define IP6_RUL3_M3_IP6SPORTM_FLAG HSL_RW - -#define IP6DPORTM_EN "ip6r3m3_dportmen" -#define IP6_RUL3_M3_IP6DPORTM_EN_BOFFSET 17 -#define IP6_RUL3_M3_IP6DPORTM_EN_BLEN 1 -#define IP6_RUL3_M3_IP6DPORTM_EN_FLAG HSL_RW - -#define IP6SPORTM_EN "ip6r3m3_sportmen" -#define IP6_RUL3_M3_IP6SPORTM_EN_BOFFSET 16 -#define IP6_RUL3_M3_IP6SPORTM_EN_BLEN 1 -#define IP6_RUL3_M3_IP6SPORTM_EN_FLAG HSL_RW - - - - -#define UDF_RUL_V4 "udfv4" -#define UDF_RUL_V4_ID 13 -#define UDF_RUL_V4_OFFSET 0x58410 -#define UDF_RUL_V4_E_LENGTH 4 -#define UDF_RUL_V4_E_OFFSET 0x20 -#define UDF_RUL_V4_NR_E 32 - - -#define LAYER_TYP "udfv4_typ" -#define UDF_RUL_V4_LAYER_TYP_BOFFSET 7 -#define UDF_RUL_V4_LAYER_TYP_BLEN 1 -#define UDF_RUL_V4_LAYER_TYP_FLAG HSL_RW - -#define LAYER_OFFSET "udfv4_offset" -#define UDF_RUL_V4_LAYER_OFFSET_BOFFSET 0 -#define UDF_RUL_V4_LAYER_OFFSET_BLEN 7 -#define UDF_RUL_V4_LAYER_OFFSET_FLAG HSL_RW - - - - -#define PPPOE_SESSION "pppoes" -#define PPPOE_SESSION_ID 13 -#define PPPOE_SESSION_OFFSET 0x59100 -#define PPPOE_SESSION_E_LENGTH 4 -#define PPPOE_SESSION_E_OFFSET 0x4 -#define PPPOE_SESSION_NR_E 16 - -#define ENTRY_VALID "pppoes_v" -#define PPPOE_SESSION_ENTRY_VALID_BOFFSET 19 -#define PPPOE_SESSION_ENTRY_VALID_BLEN 1 -#define PPPOE_SESSION_ENTRY_VALID_FLAG HSL_RW - -#define STRIP_EN "pppoes_s" -#define PPPOE_SESSION_STRIP_EN_BOFFSET 16 -#define PPPOE_SESSION_STRIP_EN_BLEN 1 -#define PPPOE_SESSION_STRIP_EN_FLAG HSL_RW - -#define SEESION_ID "pppoes_id" -#define PPPOE_SESSION_SEESION_ID_BOFFSET 0 -#define PPPOE_SESSION_SEESION_ID_BLEN 16 -#define PPPOE_SESSION_SEESION_ID_FLAG HSL_RW - - - -#ifdef __cplusplus -} -#endif /* __cplusplus */ -#endif /* _SHIVA_REG_H_ */ - diff --git a/feeds/ipq807x/qca-ssdk/src/include/hsl/shiva/shiva_reg_access.h b/feeds/ipq807x/qca-ssdk/src/include/hsl/shiva/shiva_reg_access.h deleted file mode 100755 index 5cb9df621..000000000 --- a/feeds/ipq807x/qca-ssdk/src/include/hsl/shiva/shiva_reg_access.h +++ /dev/null @@ -1,63 +0,0 @@ -/* - * Copyright (c) 2012,2018, The Linux Foundation. All rights reserved. - * Permission to use, copy, modify, and/or distribute this software for - * any purpose with or without fee is hereby granted, provided that the - * above copyright notice and this permission notice appear in all copies. - * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES - * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR - * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES - * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN - * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT - * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. - */ - - - -#ifndef _SHIVA_REG_ACCESS_H_ -#define _SHIVA_REG_ACCESS_H_ - -#ifdef __cplusplus -extern "C" { -#endif /* __cplusplus */ - -#include "sw.h" - - sw_error_t - shiva_phy_get(a_uint32_t dev_id, a_uint32_t phy_addr, - a_uint32_t reg, a_uint16_t * value); - - sw_error_t - shiva_phy_set(a_uint32_t dev_id, a_uint32_t phy_addr, - a_uint32_t reg, a_uint16_t value); - - sw_error_t - shiva_reg_get(a_uint32_t dev_id, a_uint32_t reg_addr, a_uint8_t value[], - a_uint32_t value_len); - - sw_error_t - shiva_reg_set(a_uint32_t dev_id, a_uint32_t reg_addr, a_uint8_t value[], - a_uint32_t value_len); - - sw_error_t - shiva_reg_field_get(a_uint32_t dev_id, a_uint32_t reg_addr, - a_uint32_t bit_offset, a_uint32_t field_len, - a_uint8_t value[], a_uint32_t value_len); - - sw_error_t - shiva_reg_field_set(a_uint32_t dev_id, a_uint32_t reg_addr, - a_uint32_t bit_offset, a_uint32_t field_len, - const a_uint8_t value[], a_uint32_t value_len); - - sw_error_t - shiva_reg_access_init(a_uint32_t dev_id, hsl_access_mode mode); - - sw_error_t - shiva_access_mode_set(a_uint32_t dev_id, hsl_access_mode mode); - -#ifdef __cplusplus -} -#endif /* __cplusplus */ - -#endif /* _SHIVA_REG_ACCESS_H_ */ - diff --git a/feeds/ipq807x/qca-ssdk/src/include/hsl/shiva/shiva_stp.h b/feeds/ipq807x/qca-ssdk/src/include/hsl/shiva/shiva_stp.h deleted file mode 100755 index 6d2195560..000000000 --- a/feeds/ipq807x/qca-ssdk/src/include/hsl/shiva/shiva_stp.h +++ /dev/null @@ -1,61 +0,0 @@ -/* - * Copyright (c) 2012, The Linux Foundation. All rights reserved. - * Permission to use, copy, modify, and/or distribute this software for - * any purpose with or without fee is hereby granted, provided that the - * above copyright notice and this permission notice appear in all copies. - * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES - * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR - * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES - * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN - * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT - * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. - */ - - -/** - * @defgroup shiva_stp SHIVA_STP - * @{ - */ -#ifndef _SHIVA_STP_H_ -#define _SHIVA_STP_H_ - -#ifdef __cplusplus -extern "C" { -#endif /* __cplusplus */ - -#include "fal/fal_stp.h" - - sw_error_t shiva_stp_init(a_uint32_t dev_id); - -#ifdef IN_STP -#define SHIVA_STP_INIT(rv, dev_id) \ - { \ - rv = shiva_stp_init(dev_id); \ - SW_RTN_ON_ERROR(rv); \ - } -#else -#define SHIVA_STP_INIT(rv, dev_id) -#endif - -#ifdef HSL_STANDALONG - - - HSL_LOCAL sw_error_t - shiva_stp_port_state_set(a_uint32_t dev_id, a_uint32_t st_id, - fal_port_t port_id, fal_stp_state_t state); - - - HSL_LOCAL sw_error_t - shiva_stp_port_state_get(a_uint32_t dev_id, a_uint32_t st_id, - fal_port_t port_id, fal_stp_state_t * state); - -#endif - -#ifdef __cplusplus -} -#endif /* __cplusplus */ -#endif /* _SHIVA_STP_H_ */ -/** - * @} - */ diff --git a/feeds/ipq807x/qca-ssdk/src/include/hsl/shiva/shiva_vlan.h b/feeds/ipq807x/qca-ssdk/src/include/hsl/shiva/shiva_vlan.h deleted file mode 100755 index 5d50dfc78..000000000 --- a/feeds/ipq807x/qca-ssdk/src/include/hsl/shiva/shiva_vlan.h +++ /dev/null @@ -1,83 +0,0 @@ -/* - * Copyright (c) 2012, The Linux Foundation. All rights reserved. - * Permission to use, copy, modify, and/or distribute this software for - * any purpose with or without fee is hereby granted, provided that the - * above copyright notice and this permission notice appear in all copies. - * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES - * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR - * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES - * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN - * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT - * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. - */ - - -/** - * @defgroup shiva_vlan SHIVA_VLAN - * @{ - */ -#ifndef _SHIVA_VLAN_H_ -#define _SHIVA_VLAN_H_ - -#ifdef __cplusplus -extern "C" { -#endif /* __cplusplus */ - -#include "fal/fal_vlan.h" - - sw_error_t - shiva_vlan_init(a_uint32_t dev_id); - -#ifdef IN_VLAN -#define SHIVA_VLAN_INIT(rv, dev_id) \ - { \ - rv = shiva_vlan_init(dev_id); \ - SW_RTN_ON_ERROR(rv); \ - } -#else -#define SHIVA_VLAN_INIT(rv, dev_id) -#endif - -#ifdef HSL_STANDALONG - - - HSL_LOCAL sw_error_t - shiva_vlan_entry_append(a_uint32_t dev_id, const fal_vlan_t * vlan_entry); - - - HSL_LOCAL sw_error_t - shiva_vlan_create(a_uint32_t dev_id, a_uint32_t vlan_id); - - - HSL_LOCAL sw_error_t - shiva_vlan_next(a_uint32_t dev_id, a_uint32_t vlan_id, fal_vlan_t * p_vlan); - - - HSL_LOCAL sw_error_t - shiva_vlan_find(a_uint32_t dev_id, a_uint32_t vlan_id, fal_vlan_t * p_vlan); - - - HSL_LOCAL sw_error_t - shiva_vlan_member_update(a_uint32_t dev_id, a_uint32_t vlan_id, - fal_pbmp_t member, fal_pbmp_t u_member); - - - HSL_LOCAL sw_error_t - shiva_vlan_delete(a_uint32_t dev_id, a_uint32_t vlan_id); - - - HSL_LOCAL sw_error_t - shiva_vlan_flush(a_uint32_t dev_id); - - -#endif - -#ifdef __cplusplus -} -#endif /* __cplusplus */ - -#endif /* _SHIVA_VLAN_H_ */ -/** - * @} - */ diff --git a/feeds/ipq807x/qca-ssdk/src/include/init/ssdk_clk.h b/feeds/ipq807x/qca-ssdk/src/include/init/ssdk_clk.h deleted file mode 100755 index e03c76a04..000000000 --- a/feeds/ipq807x/qca-ssdk/src/include/init/ssdk_clk.h +++ /dev/null @@ -1,313 +0,0 @@ -/* - * Copyright (c) 2017, 2019-2020, The Linux Foundation. All rights reserved. - * Permission to use, copy, modify, and/or distribute this software for - * any purpose with or without fee is hereby granted, provided that the - * above copyright notice and this permission notice appear in all copies. - * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES - * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR - * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES - * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN - * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT - * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. - */ - - #ifndef _SSDK_CLK_H_ -#define _SSDK_CLK_H_ - -#ifdef __cplusplus -extern "C" { -#endif /* __cplusplus */ - -#define PPE_RESET_ID "ppe_rst" -#define UNIPHY0_SOFT_RESET_ID "uniphy0_soft_rst" -#define UNIPHY0_XPCS_RESET_ID "uniphy0_xpcs_rst" -#define UNIPHY1_SOFT_RESET_ID "uniphy1_soft_rst" -#define UNIPHY1_XPCS_RESET_ID "uniphy1_xpcs_rst" -#define UNIPHY2_SOFT_RESET_ID "uniphy2_soft_rst" -#define UNIPHY2_XPCS_RESET_ID "uniphy2_xpcs_rst" -#define UNIPHY0_PORT1_DISABLE_ID "uniphy0_port1_dis" -#define UNIPHY0_PORT2_DISABLE_ID "uniphy0_port2_dis" -#define UNIPHY0_PORT3_DISABLE_ID "uniphy0_port3_dis" -#define UNIPHY0_PORT4_DISABLE_ID "uniphy0_port4_dis" -#define UNIPHY0_PORT5_DISABLE_ID "uniphy0_port5_dis" -#define UNIPHY0_PORT_4_5_RESET_ID "uniphy0_port_4_5_rst" -#define UNIPHY0_PORT_4_RESET_ID "uniphy0_port_4_rst" - -#define SSDK_PORT1_RESET_ID "nss_port1_rst" -#define SSDK_PORT2_RESET_ID "nss_port2_rst" -#define SSDK_PORT3_RESET_ID "nss_port3_rst" -#define SSDK_PORT4_RESET_ID "nss_port4_rst" -#define SSDK_PORT5_RESET_ID "nss_port5_rst" -#define SSDK_PORT6_RESET_ID "nss_port6_rst" - -enum ssdk_rst_action { - SSDK_RESET_DEASSERT = 0, - SSDK_RESET_ASSERT = 1 -}; - -enum unphy_rst_type { - UNIPHY0_SOFT_RESET_E = 0, - UNIPHY0_XPCS_RESET_E, - UNIPHY1_SOFT_RESET_E, - UNIPHY1_XPCS_RESET_E, - UNIPHY2_SOFT_RESET_E, - UNIPHY2_XPCS_RESET_E, - UNIPHY0_PORT1_DISABLE_E, - UNIPHY0_PORT2_DISABLE_E, - UNIPHY0_PORT3_DISABLE_E, - UNIPHY0_PORT4_DISABLE_E, - UNIPHY0_PORT5_DISABLE_E, - UNIPHY0_PORT_4_5_RESET_E, - UNIPHY0_PORT_4_RESET_E, - UNIPHY_RST_MAX -}; - -#define CMN_AHB_CLK "cmn_ahb_clk" -#define CMN_SYS_CLK "cmn_sys_clk" -#define UNIPHY0_AHB_CLK "uniphy0_ahb_clk" -#define UNIPHY0_SYS_CLK "uniphy0_sys_clk" -#define UNIPHY1_AHB_CLK "uniphy1_ahb_clk" -#define UNIPHY1_SYS_CLK "uniphy1_sys_clk" -#define UNIPHY2_AHB_CLK "uniphy2_ahb_clk" -#define UNIPHY2_SYS_CLK "uniphy2_sys_clk" -#define PORT1_MAC_CLK "port1_mac_clk" -#define PORT2_MAC_CLK "port2_mac_clk" -#define PORT3_MAC_CLK "port3_mac_clk" -#define PORT4_MAC_CLK "port4_mac_clk" -#define PORT5_MAC_CLK "port5_mac_clk" -#define PORT6_MAC_CLK "port6_mac_clk" -#define NSS_PPE_CLK "nss_ppe_clk" -#define NSS_PPE_CFG_CLK "nss_ppe_cfg_clk" -#define NSSNOC_PPE_CLK "nssnoc_ppe_clk" -#define NSSNOC_PPE_CFG_CLK "nssnoc_ppe_cfg_clk" -#define NSS_EDMA_CLK "nss_edma_clk" -#define NSS_EDMA_CFG_CLK "nss_edma_cfg_clk" -#define NSS_PPE_IPE_CLK "nss_ppe_ipe_clk" -#define NSS_PPE_BTQ_CLK "nss_ppe_btq_clk" -#define MDIO_AHB_CLK "gcc_mdio_ahb_clk" -#define NSSNOC_CLK "gcc_nss_noc_clk" -#define NSSNOC_SNOC_CLK "gcc_nssnoc_snoc_clk" -#define MEM_NOC_NSSAXI_CLK "gcc_mem_noc_nss_axi_clk" -#define CRYPTO_PPE_CLK "gcc_nss_crypto_clk" -#define NSS_IMEM_CLK "gcc_nss_imem_clk" -#define NSS_PTP_REF_CLK "gcc_nss_ptp_ref_clk" -#define SNOC_NSSNOC_CLK "gcc_snoc_nssnoc_clk" - -#define UNIPHY_AHB_CLK "uniphy_ahb_clk" -#define UNIPHY_SYS_CLK "uniphy_sys_clk" -#define MP_UNIPHY_SYS_CLK_RATE 24000000 -#define MDIO0_AHB_CLK "gcc_mdio0_ahb_clk" -#define MDIO1_AHB_CLK "gcc_mdio1_ahb_clk" -#define GMAC0_CFG_CLK "gcc_gmac0_cfg_clk" -#define GMAC0_SYS_CLK "gcc_gmac0_sys_clk" -#define GMAC1_CFG_CLK "gcc_gmac1_cfg_clk" -#define GMAC1_SYS_CLK "gcc_gmac1_sys_clk" -#define SNOC_GMAC0_AHB_CLK "gcc_snoc_gmac0_ahb_clk" -#define SNOC_GMAC1_AHB_CLK "gcc_snoc_gmac1_ahb_clk" -#define GMAC0_PTP_CLK "gcc_gmac0_ptp_clk" -#define GMAC1_PTP_CLK "gcc_gmac1_ptp_clk" -#define GMAC_CLK_RATE 240000000 - -#define NSS_PORT1_RX_CLK "nss_port1_rx_clk" -#define NSS_PORT1_TX_CLK "nss_port1_tx_clk" -#define NSS_PORT2_RX_CLK "nss_port2_rx_clk" -#define NSS_PORT2_TX_CLK "nss_port2_tx_clk" -#define NSS_PORT3_RX_CLK "nss_port3_rx_clk" -#define NSS_PORT3_TX_CLK "nss_port3_tx_clk" -#define NSS_PORT4_RX_CLK "nss_port4_rx_clk" -#define NSS_PORT4_TX_CLK "nss_port4_tx_clk" -#define NSS_PORT5_RX_CLK "nss_port5_rx_clk" -#define NSS_PORT5_TX_CLK "nss_port5_tx_clk" -#define NSS_PORT6_RX_CLK "nss_port6_rx_clk" -#define NSS_PORT6_TX_CLK "nss_port6_tx_clk" -#define UNIPHY0_PORT1_RX_CLK "uniphy0_port1_rx_clk" -#define UNIPHY0_PORT1_TX_CLK "uniphy0_port1_tx_clk" -#define UNIPHY0_PORT2_RX_CLK "uniphy0_port2_rx_clk" -#define UNIPHY0_PORT2_TX_CLK "uniphy0_port2_tx_clk" -#define UNIPHY0_PORT3_RX_CLK "uniphy0_port3_rx_clk" -#define UNIPHY0_PORT3_TX_CLK "uniphy0_port3_tx_clk" -#define UNIPHY0_PORT4_RX_CLK "uniphy0_port4_rx_clk" -#define UNIPHY0_PORT4_TX_CLK "uniphy0_port4_tx_clk" -#define UNIPHY0_PORT5_RX_CLK "uniphy0_port5_rx_clk" -#define UNIPHY0_PORT5_TX_CLK "uniphy0_port5_tx_clk" -#define UNIPHY1_PORT5_RX_CLK "uniphy1_port5_rx_clk" -#define UNIPHY1_PORT5_TX_CLK "uniphy1_port5_tx_clk" -#define UNIPHY2_PORT6_RX_CLK "uniphy2_port6_rx_clk" -#define UNIPHY2_PORT6_TX_CLK "uniphy2_port6_tx_clk" -#define PORT5_RX_SRC "nss_port5_rx_clk_src" -#define PORT5_TX_SRC "nss_port5_tx_clk_src" - -enum unphy_clk_type { - NSS_PORT1_RX_CLK_E = 0, - NSS_PORT1_TX_CLK_E, - NSS_PORT2_RX_CLK_E, - NSS_PORT2_TX_CLK_E, - NSS_PORT3_RX_CLK_E, - NSS_PORT3_TX_CLK_E, - NSS_PORT4_RX_CLK_E, - NSS_PORT4_TX_CLK_E, - NSS_PORT5_RX_CLK_E, - NSS_PORT5_TX_CLK_E, - NSS_PORT6_RX_CLK_E, - NSS_PORT6_TX_CLK_E, - UNIPHY0_PORT1_RX_CLK_E, - UNIPHY0_PORT1_TX_CLK_E, - UNIPHY0_PORT2_RX_CLK_E, - UNIPHY0_PORT2_TX_CLK_E, - UNIPHY0_PORT3_RX_CLK_E, - UNIPHY0_PORT3_TX_CLK_E, - UNIPHY0_PORT4_RX_CLK_E, - UNIPHY0_PORT4_TX_CLK_E, - UNIPHY0_PORT5_RX_CLK_E, - UNIPHY0_PORT5_TX_CLK_E, - UNIPHY1_PORT5_RX_CLK_E, - UNIPHY1_PORT5_TX_CLK_E, - UNIPHY2_PORT6_RX_CLK_E, - UNIPHY2_PORT6_TX_CLK_E, - PORT5_RX_SRC_E, - PORT5_TX_SRC_E, - UNIPHYT_CLK_MAX -}; - -enum cmnblk_clk_type { - INTERNAL_48MHZ = 0, - EXTERNAL_25MHZ, - EXTERNAL_31250KHZ, - EXTERNAL_40MHZ, - EXTERNAL_48MHZ, - EXTERNAL_50MHZ, - INTERNAL_96MHZ, -}; - -enum cmnblk_pll_src_type { - CMN_BLK_PLL_SRC_SEL_FROM_REG = 0, - CMN_BLK_PLL_SRC_SEL_FROM_LOGIC = 1, - CMN_BLK_PLL_SRC_SEL_FROM_PCS = 2, -}; - -enum mp_bcr_rst_type { - GEPHY_BCR_RESET_E = 0, - UNIPHY_BCR_RESET_E, - GMAC0_BCR_RESET_E, - GMAC1_BCR_RESET_E, - GEPHY_MISC_RESET_E, - MP_BCR_RST_MAX -}; - -#define GEHPY_BCR_RESET_ID "gephy_bcr_rst" -#define UNIPHY_BCR_RESET_ID "uniphy_bcr_rst" -#define GMAC0_BCR_RESET_ID "gmac0_bcr_rst" -#define GMAC1_BCR_RESET_ID "gmac1_bcr_rst" -#define GEPHY_MISC_RESET_ID "gephy_misc_rst" - -#define CMN_BLK_ADDR 0x0009B780 -#define CMN_BLK_PLL_SRC_ADDR 0x0009B028 -#define CMN_BLK_SIZE 0x100 -#define PLL_CTRL_SRC_MASK 0xfffffcff -#define PLL_REFCLK_DIV_MASK 0xfffffe0f -#define PLL_REFCLK_DIV_2 0x20 -#define FREQUENCY_MASK 0xfffffdf0 -#define INTERNAL_48MHZ_CLOCK 0x7 -#define EXTERNAL_25MHZ_CLOCK 0x203 -#define EXTERNAL_31250KHZ_CLOCK 0x204 -#define EXTERNAL_40MHZ_CLOCK 0x206 -#define EXTERNAL_48MHZ_CLOCK 0x207 -#define EXTERNAL_50MHZ_CLOCK 0x208 -#define UNIPHY_AHB_CLK_RATE 100000000 -#define UNIPHY_SYS_CLK_RATE 19200000 -#define CPPE_UNIPHY_SYS_CLK_RATE 24000000 -#define PPE_CLK_RATE 300000000 -#define MDIO_AHB_RATE 100000000 -#define NSS_NOC_RATE 461500000 -#define NSSNOC_SNOC_RATE 266670000 -#define NSS_IMEM_RATE 400000000 -#define PTP_REF_RARE 150000000 -#define NSS_AXI_RATE 461500000 -#define NSS_PORT5_DFLT_RATE 19200000 - -#define UNIPHY_CLK_RATE_25M 25000000 -#define UNIPHY_CLK_RATE_50M 50000000 -#define UNIPHY_CLK_RATE_125M 125000000 -#define UNIPHY_CLK_RATE_312M 312500000 -#define UNIPHY_DEFAULT_RATE UNIPHY_CLK_RATE_125M - -#define PQSGMII_SPEED_10M_CLK 2500000 -#define PQSGMII_SPEED_100M_CLK 25000000 -#define PQSGMII_SPEED_1000M_CLK 125000000 -#define USXGMII_SPEED_10M_CLK 1250000 -#define USXGMII_SPEED_100M_CLK 12500000 -#define USXGMII_SPEED_1000M_CLK 125000000 -#define USXGMII_SPEED_2500M_CLK 78125000 -#define USXGMII_SPEED_5000M_CLK 156250000 -#define USXGMII_SPEED_10000M_CLK 312500000 -#define SGMII_PLUS_SPEED_2500M_CLK 312500000 -#define SGMII_SPEED_10M_CLK 2500000 -#define SGMII_SPEED_100M_CLK 25000000 -#define SGMII_SPEED_1000M_CLK 125000000 - -#define CPPE_XGMAC_CLK_REG 0x0194900c -#define CPPE_XGMAC_CLK_SIZE 0x10 -#define CPPE_XGMAC_CLK_ENABLE 0x20 - -enum { - UNIPHY_RX = 0, - UNIPHY_TX, -}; - -void ssdk_uniphy_reset( - a_uint32_t dev_id, - enum unphy_rst_type rst_type, - a_uint32_t action); - -void ssdk_port_reset( - a_uint32_t dev_id, - a_uint32_t port_id, - a_uint32_t action); - -#if defined(HPPE) || defined(MP) -void -qca_gcc_mac_port_clock_set(a_uint32_t dev_id, a_uint32_t port_id, - a_bool_t enable); - -void -qca_gcc_uniphy_port_clock_set(a_uint32_t dev_id, a_uint32_t uniphy_index, - a_uint32_t port_id, a_bool_t enable); -void ssdk_gcc_clock_init(void); -void -ssdk_port_speed_clock_set( - a_uint32_t dev_id, - a_uint32_t port_id, - a_uint32_t rate); -void ssdk_port_mac_clock_reset( - a_uint32_t dev_id, - a_uint32_t port_id); -#endif - -#if defined(HPPE) -void ssdk_ppe_reset_init(void); -void ssdk_uniphy_raw_clock_reset(a_uint8_t uniphy_index); -void ssdk_uniphy_raw_clock_set( - a_uint8_t uniphy_index, - a_uint8_t direction, - a_uint32_t clock); -void ssdk_gcc_uniphy_sys_set(a_uint32_t dev_id, a_uint32_t uniphy_index, - a_bool_t enable); -void ssdk_uniphy_port5_clock_source_set(void); -#endif - -#if defined(MP) -void ssdk_mp_raw_clock_set( - a_uint8_t uniphy_index, - a_uint8_t direction, - a_uint32_t clock); -void ssdk_mp_gephy_icc_efuse_load_enable( - a_bool_t enable); - -#endif - -#ifdef __cplusplus -} -#endif /* __cplusplus */ -#endif /* _SSDK_CLK_H */ - diff --git a/feeds/ipq807x/qca-ssdk/src/include/init/ssdk_dts.h b/feeds/ipq807x/qca-ssdk/src/include/init/ssdk_dts.h deleted file mode 100644 index d7ffe0482..000000000 --- a/feeds/ipq807x/qca-ssdk/src/include/init/ssdk_dts.h +++ /dev/null @@ -1,188 +0,0 @@ -/* - * Copyright (c) 2018-2019, The Linux Foundation. All rights reserved. - * Permission to use, copy, modify, and/or distribute this software for - * any purpose with or without fee is hereby granted, provided that the - * above copyright notice and this permission notice appear in all copies. - * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES - * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR - * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES - * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN - * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT - * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. - */ - - #ifndef _SSDK_DTS_H_ -#define _SSDK_DTS_H_ - -#ifdef __cplusplus -extern "C" { -#endif - -#ifndef BOARD_AR71XX -#include -#endif -#include "ssdk_init.h" -#include - -typedef struct { - a_uint16_t ucastq_start; - a_uint16_t ucastq_end; - a_uint16_t mcastq_start; - a_uint16_t mcastq_end; - a_uint8_t l0sp_start; - a_uint8_t l0sp_end; - a_uint8_t l0cdrr_start; - a_uint8_t l0cdrr_end; - a_uint8_t l0edrr_start; - a_uint8_t l0edrr_end; - a_uint8_t l1cdrr_start; - a_uint8_t l1cdrr_end; - a_uint8_t l1edrr_start; - a_uint8_t l1edrr_end; -} ssdk_dt_portscheduler_cfg; - -typedef struct { - a_uint8_t valid; - a_uint8_t port_id; - a_uint8_t cpri; - a_uint8_t cdrr_id; - a_uint8_t epri; - a_uint8_t edrr_id; - a_uint8_t sp_id; -} ssdk_dt_l0scheduler_cfg; - -typedef struct { - a_uint8_t valid; - a_uint8_t port_id; - a_uint8_t cpri; - a_uint8_t cdrr_id; - a_uint8_t epri; - a_uint8_t edrr_id; -} ssdk_dt_l1scheduler_cfg; - -typedef struct { - ssdk_dt_portscheduler_cfg pool[SSDK_MAX_PORT_NUM]; - ssdk_dt_l0scheduler_cfg l0cfg[SSDK_L0SCHEDULER_CFG_MAX]; - ssdk_dt_l1scheduler_cfg l1cfg[SSDK_L1SCHEDULER_CFG_MAX]; -} ssdk_dt_scheduler_cfg; - -typedef struct -{ - a_uint8_t port_id; - a_uint8_t phy_addr; - a_uint8_t port_duplex; - a_uint32_t port_speed; - phy_features_t phy_features; - struct mii_bus *miibus; -} ssdk_port_phyinfo; - -typedef struct -{ - a_uint32_t switchreg_base_addr; - a_uint32_t switchreg_size; - a_uint32_t psgmiireg_base_addr; - a_uint32_t psgmiireg_size; - a_uint8_t *reg_access_mode; - a_uint8_t *psgmii_reg_access_str; - hsl_reg_mode switch_reg_access_mode; - hsl_reg_mode psgmii_reg_access_mode; - struct clk *ess_clk; - struct clk *cmnblk_clk; - ssdk_port_cfg port_cfg; - a_uint32_t phyinfo_num; - ssdk_port_phyinfo *port_phyinfo; - a_uint32_t mac_mode; - a_uint32_t mac_mode1; - a_uint32_t mac_mode2; - a_uint32_t uniphyreg_base_addr; - a_uint32_t uniphyreg_size; - a_uint8_t *uniphy_access_mode; - hsl_reg_mode uniphy_reg_access_mode; - ssdk_dt_scheduler_cfg scheduler_cfg; - a_uint8_t bm_tick_mode; - a_uint8_t tm_tick_mode; - a_bool_t ess_switch_flag; - a_uint32_t device_id; - struct device_node *of_node; - a_bool_t is_emulation; - a_uint32_t emu_chip_ver; /*only valid when is_emulation is true*/ -} ssdk_dt_cfg; - -#define SSDK_MAX_NR_ETH 6 -#define SSDK_PHY_RESET_GPIO_INDEX 0 - -typedef struct -{ - a_uint32_t num_devices; - ssdk_dt_cfg **ssdk_dt_switch_nodes; - a_uint32_t num_intf_mac; - fal_mac_addr_t intf_mac[SSDK_MAX_NR_ETH]; -} ssdk_dt_global_t; - -typedef struct -{ - a_uint32_t base_addr; - a_uint32_t size; -} ssdk_reg_map_info; - -/* DTS info for get */ -#ifdef HPPE -#ifdef IN_QOS -a_uint8_t ssdk_tm_tick_mode_get(a_uint32_t dev_id); -ssdk_dt_scheduler_cfg* ssdk_bootup_shceduler_cfg_get(a_uint32_t dev_id); -#endif -#endif -#ifdef IN_BM -a_uint8_t ssdk_bm_tick_mode_get(a_uint32_t dev_id); -#endif -#ifdef IN_QM -a_uint16_t ssdk_ucast_queue_start_get(a_uint32_t dev_id, a_uint32_t port); -#endif -a_uint32_t ssdk_intf_mac_num_get(void); -a_uint8_t* ssdk_intf_macaddr_get(a_uint32_t index); -a_uint32_t ssdk_dt_global_get_mac_mode(a_uint32_t dev_id, a_uint32_t index); -a_uint32_t ssdk_dt_global_set_mac_mode(a_uint32_t dev_id, a_uint32_t index, a_uint32_t mode); -a_uint32_t ssdk_cpu_bmp_get(a_uint32_t dev_id); -a_uint32_t ssdk_lan_bmp_get(a_uint32_t dev_id); -a_uint32_t ssdk_wan_bmp_get(a_uint32_t dev_id); -sw_error_t ssdk_lan_bmp_set(a_uint32_t dev_id, a_uint32_t lan_bmp); -sw_error_t ssdk_wan_bmp_set(a_uint32_t dev_id, a_uint32_t wan_bmp); -a_uint32_t ssdk_inner_bmp_get(a_uint32_t dev_id); -ssdk_port_phyinfo* ssdk_port_phyinfo_get(a_uint32_t dev_id, a_uint32_t port_id); -a_bool_t ssdk_port_feature_get(a_uint32_t dev_id, a_uint32_t port_id, phy_features_t feature); -a_uint32_t ssdk_port_force_speed_get(a_uint32_t dev_id, a_uint32_t port_id); -struct mii_bus * -ssdk_dts_miibus_get(a_uint32_t dev_id, a_uint32_t phy_addr); -hsl_reg_mode ssdk_switch_reg_access_mode_get(a_uint32_t dev_id); -void ssdk_switch_reg_map_info_get(a_uint32_t dev_id, ssdk_reg_map_info *info); -#ifdef DESS -hsl_reg_mode ssdk_psgmii_reg_access_mode_get(a_uint32_t dev_id); -void ssdk_psgmii_reg_map_info_get(a_uint32_t dev_id, ssdk_reg_map_info *info); -#endif -#ifdef IN_UNIPHY -hsl_reg_mode ssdk_uniphy_reg_access_mode_get(a_uint32_t dev_id); -void ssdk_uniphy_reg_map_info_get(a_uint32_t dev_id, ssdk_reg_map_info *info); -#endif -a_bool_t ssdk_ess_switch_flag_get(a_uint32_t dev_id); -a_uint32_t ssdk_device_id_get(a_uint32_t index); -struct device_node *ssdk_dts_node_get(a_uint32_t dev_id); -struct clk *ssdk_dts_essclk_get(a_uint32_t dev_id); -struct clk *ssdk_dts_cmnclk_get(a_uint32_t dev_id); - -int ssdk_switch_device_num_init(void); -void ssdk_switch_device_num_exit(void); -a_uint32_t ssdk_switch_device_num_get(void); -a_bool_t ssdk_is_emulation(a_uint32_t dev_id); -a_uint32_t ssdk_emu_chip_ver_get(a_uint32_t dev_id); - -#ifndef BOARD_AR71XX -#if defined(CONFIG_OF) && (LINUX_VERSION_CODE >= KERNEL_VERSION(3,14,0)) -sw_error_t ssdk_dt_parse(ssdk_init_cfg *cfg, a_uint32_t num, a_uint32_t *dev_id); -#endif -#endif - -#ifdef __cplusplus -} -#endif /* __cplusplus */ -#endif /* _SSDK_DTS_H */ diff --git a/feeds/ipq807x/qca-ssdk/src/include/init/ssdk_hppe.h b/feeds/ipq807x/qca-ssdk/src/include/init/ssdk_hppe.h deleted file mode 100755 index 6e8c68cb9..000000000 --- a/feeds/ipq807x/qca-ssdk/src/include/init/ssdk_hppe.h +++ /dev/null @@ -1,32 +0,0 @@ -/* - * Copyright (c) 2017, The Linux Foundation. All rights reserved. - * Permission to use, copy, modify, and/or distribute this software for - * any purpose with or without fee is hereby granted, provided that the - * above copyright notice and this permission notice appear in all copies. - * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES - * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR - * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES - * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN - * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT - * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. - */ - - - -#ifndef _SSDK_HPPE_H_ -#define _SSDK_HPPE_H_ - -#ifdef __cplusplus -extern "C" { -#endif /* __cplusplus */ - -#include "init/ssdk_init.h" - -sw_error_t qca_hppe_hw_init(ssdk_init_cfg *cfg, a_uint32_t dev_id); - -#ifdef __cplusplus -} -#endif /* __cplusplus */ -#endif /* _SSDK_HPPE_H */ - diff --git a/feeds/ipq807x/qca-ssdk/src/include/init/ssdk_init.h b/feeds/ipq807x/qca-ssdk/src/include/init/ssdk_init.h deleted file mode 100755 index 9187479ba..000000000 --- a/feeds/ipq807x/qca-ssdk/src/include/init/ssdk_init.h +++ /dev/null @@ -1,390 +0,0 @@ -/* - * Copyright (c) 2012, 2015-2020, The Linux Foundation. All rights reserved. - * Permission to use, copy, modify, and/or distribute this software for - * any purpose with or without fee is hereby granted, provided that the - * above copyright notice and this permission notice appear in all copies. - * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES - * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR - * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES - * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN - * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT - * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. - */ - - -/*qca808x_start*/ -#ifndef _SSDK_INIT_H_ -#define _SSDK_INIT_H_ - -#ifdef __cplusplus -extern "C" { -#endif /* __cplusplus */ - -#include "sw.h" -#include "fal_type.h" -/*qca808x_end*/ -#include "fal/fal_led.h" -/*qca808x_start*/ -#define SSDK_MAX_PORT_NUM 8 -/*qca808x_end*/ -#define SSDK_MAX_VIRTUAL_PORT_NUM 256 -#define SSDK_MAX_SERVICE_CODE_NUM 256 -#define SSDK_MAX_CPU_CODE_NUM 256 -#define SSDK_L0SCHEDULER_CFG_MAX 300 -#define SSDK_L0SCHEDULER_UCASTQ_CFG_MAX 256 -#define SSDK_L1SCHEDULER_CFG_MAX 64 -#define SSDK_SP_MAX_PRIORITY 8 -#define SSDK_MAX_FRAME_SIZE 0x3000 - -#define PORT_GMAC_TYPE 1 -#define PORT_XGMAC_TYPE 2 -#define PORT_LINK_UP 1 -#define PORT_LINK_DOWN 0 - -/*qca808x_start*/ - typedef enum { - HSL_MDIO = 1, - HSL_HEADER, - } - hsl_access_mode; - - typedef enum - { - HSL_NO_CPU = 0, - HSL_CPU_1, - HSL_CPU_2, - HSL_CPU_1_PLUS, - } hsl_init_mode; - - typedef enum - { - HSL_REG_MDIO = 0, - HSL_REG_LOCAL_BUS, - } hsl_reg_mode; - - typedef sw_error_t - (*mdio_reg_set) (a_uint32_t dev_id, a_uint32_t phy_addr, a_uint32_t reg, - a_uint16_t data); - - typedef sw_error_t - (*mdio_reg_get) (a_uint32_t dev_id, a_uint32_t phy_addr, a_uint32_t reg, - a_uint16_t * data); - - typedef sw_error_t - (*i2c_reg_set) (a_uint32_t dev_id, a_uint32_t phy_addr, a_uint32_t reg, - a_uint16_t data); - - typedef sw_error_t - (*i2c_reg_get) (a_uint32_t dev_id, a_uint32_t phy_addr, a_uint32_t reg, - a_uint16_t * data); -/*qca808x_end*/ - - typedef sw_error_t - (*hdr_reg_set) (a_uint32_t dev_id, a_uint32_t reg_addr, a_uint8_t *reg_data, a_uint32_t len); - - typedef sw_error_t - (*hdr_reg_get) (a_uint32_t dev_id, a_uint32_t reg_addr, a_uint8_t *reg_data, a_uint32_t len); - - typedef sw_error_t - (*psgmii_reg_set) (a_uint32_t dev_id, a_uint32_t reg_addr, a_uint8_t *reg_data, a_uint32_t len); - - typedef sw_error_t - (*psgmii_reg_get) (a_uint32_t dev_id, a_uint32_t reg_addr, a_uint8_t *reg_data, a_uint32_t len); - - typedef sw_error_t - (*uniphy_reg_set) (a_uint32_t dev_id, a_uint32_t index, a_uint32_t reg_addr, a_uint8_t *reg_data, a_uint32_t len); - - typedef sw_error_t - (*uniphy_reg_get) (a_uint32_t dev_id, a_uint32_t index, a_uint32_t reg_addr, a_uint8_t *reg_data, a_uint32_t len); - - typedef void (*mii_reg_set)(a_uint32_t dev_id, a_uint32_t reg, a_uint32_t val); - - typedef a_uint32_t (*mii_reg_get)(a_uint32_t dev_id, a_uint32_t reg); -/*qca808x_start*/ -enum ssdk_port_wrapper_cfg { - PORT_WRAPPER_PSGMII = 0, - PORT_WRAPPER_PSGMII_RGMII5, - PORT_WRAPPER_SGMII0_RGMII5, - PORT_WRAPPER_SGMII1_RGMII5, - PORT_WRAPPER_PSGMII_RMII0, - PORT_WRAPPER_PSGMII_RMII1, - PORT_WRAPPER_PSGMII_RMII0_RMII1, - PORT_WRAPPER_PSGMII_RGMII4, - PORT_WRAPPER_SGMII0_RGMII4, - PORT_WRAPPER_SGMII1_RGMII4, - PORT_WRAPPER_SGMII4_RGMII4, - PORT_WRAPPER_QSGMII, - PORT_WRAPPER_SGMII_PLUS, - PORT_WRAPPER_USXGMII, - PORT_WRAPPER_10GBASE_R, - PORT_WRAPPER_SGMII_CHANNEL0, - PORT_WRAPPER_SGMII_CHANNEL1, - PORT_WRAPPER_SGMII_CHANNEL4, - PORT_WRAPPER_RGMII, - PORT_WRAPPER_PSGMII_FIBER, - PORT_WRAPPER_SGMII_FIBER, - PORT_WRAPPER_MAX = 0xFF -}; - - typedef struct - { - mdio_reg_set mdio_set; - mdio_reg_get mdio_get; -/*qca808x_end*/ - hdr_reg_set header_reg_set; - hdr_reg_get header_reg_get; - psgmii_reg_set psgmii_reg_set; - psgmii_reg_get psgmii_reg_get; - uniphy_reg_set uniphy_reg_set; - uniphy_reg_get uniphy_reg_get; - mii_reg_set mii_reg_set; - mii_reg_get mii_reg_get; -/*qca808x_start*/ - i2c_reg_set i2c_set; - i2c_reg_get i2c_get; - } hsl_reg_func; -/*qca808x_end*/ - typedef struct - { - a_bool_t mac0_rgmii; - a_bool_t mac5_rgmii; - a_bool_t rx_delay_s0; - a_bool_t rx_delay_s1; - a_bool_t tx_delay_s0; - a_bool_t tx_delay_s1; - a_bool_t rgmii_rxclk_delay; - a_bool_t rgmii_txclk_delay; - a_bool_t phy4_rx_delay; - a_bool_t phy4_tx_delay; - } garuda_init_spec_cfg; -/*qca808x_start*/ - typedef enum - { - CHIP_UNSPECIFIED = 0, - CHIP_ATHENA, - CHIP_GARUDA, - CHIP_SHIVA, - CHIP_HORUS, - CHIP_ISIS, - CHIP_ISISC, - CHIP_DESS, - CHIP_HPPE, - CHIP_SCOMPHY, - } ssdk_chip_type; -/*qca808x_end*/ - typedef struct - { - a_uint32_t cpu_bmp; - a_uint32_t lan_bmp; - a_uint32_t wan_bmp; - a_uint32_t inner_bmp; - } ssdk_port_cfg; - - typedef struct - { - a_uint32_t led_num; - a_uint32_t led_source_id; - led_ctrl_pattern_t led_pattern; - - } led_source_cfg_t; - -enum { - QCA_PHY_F_CLAUSE45_BIT, - QCA_PHY_F_COMBO_BIT, - QCA_PHY_F_QGMAC_BIT, - QCA_PHY_F_XGMAC_BIT, - QCA_PHY_F_I2C_BIT, - QCA_PHY_F_INIT_BIT, - QCA_PHY_F_FORCE_BIT, - QCA_PHY_FEATURE_MAX -}; -/*qca808x_start*/ -#define phy_features_t a_uint16_t -#define __PHY_F_BIT(bit) ((phy_features_t)1 << (bit)) -#define _PHY_F(name) __PHY_F_BIT(QCA_PHY_F_##name##_BIT) - -#define PHY_F_CLAUSE45 _PHY_F(CLAUSE45) -#define PHY_F_COMBO _PHY_F(COMBO) -#define PHY_F_QGMAC _PHY_F(QGMAC) -#define PHY_F_XGMAC _PHY_F(XGMAC) -#define PHY_F_I2C _PHY_F(I2C) -#define PHY_F_INIT _PHY_F(INIT) -#define PHY_F_FORCE _PHY_F(FORCE) - -typedef struct -{ - hsl_init_mode cpu_mode; - hsl_access_mode reg_mode; - hsl_reg_func reg_func; - - ssdk_chip_type chip_type; - a_uint32_t chip_revision; - - /* os specific parameter */ - /* when uk_if based on netlink, it's netlink protocol type*/ - /* when uk_if based on ioctl, it's minor device number, major number - is always 10(misc device) */ - a_uint32_t nl_prot; - - /* chip specific parameter */ - void * chip_spec_cfg; -/*qca808x_end*/ - /* port cfg */ - ssdk_port_cfg port_cfg; - a_uint32_t mac_mode; - a_uint32_t led_source_num; - led_source_cfg_t led_source_cfg[15]; -/*qca808x_start*/ - a_uint32_t phy_id; - a_uint32_t mac_mode1; - a_uint32_t mac_mode2; -} ssdk_init_cfg; -/*qca808x_end*/ - -#if defined ATHENA -#define def_init_cfg {.reg_mode = HSL_MDIO, .cpu_mode = HSL_CPU_2}; -#elif defined GARUDA - -#define def_init_cfg_cpu2 {.reg_mode = HSL_MDIO, .cpu_mode = HSL_CPU_2,}; - -#define def_init_spec_cfg_cpu2 {.mac0_rgmii = A_TRUE, .mac5_rgmii = A_TRUE, \ - .rx_delay_s0 = A_FALSE, .rx_delay_s1 = A_FALSE, \ - .tx_delay_s0 = A_TRUE, .tx_delay_s1 = A_FALSE,\ - .rgmii_rxclk_delay = A_TRUE, .rgmii_txclk_delay = A_TRUE,\ - .phy4_rx_delay = A_TRUE, .phy4_tx_delay = A_TRUE,} - -#define def_init_cfg_cpu1 {.reg_mode = HSL_MDIO, .cpu_mode = HSL_CPU_1,}; - -#define def_init_spec_cfg_cpu1 {.mac0_rgmii = A_TRUE, .mac5_rgmii = A_FALSE, \ - .rx_delay_s0 = A_FALSE, .rx_delay_s1 = A_FALSE, \ - .tx_delay_s0 = A_TRUE, .tx_delay_s1 = A_FALSE,\ - .rgmii_rxclk_delay = A_TRUE, .rgmii_txclk_delay = A_TRUE, \ - .phy4_rx_delay = A_TRUE, .phy4_tx_delay = A_TRUE,} - -#define def_init_cfg_cpu1plus {.reg_mode = HSL_MDIO, .cpu_mode = HSL_CPU_1_PLUS,}; - -#define def_init_spec_cfg_cpu1plus {.mac0_rgmii = A_TRUE, .mac5_rgmii = A_FALSE, \ - .rx_delay_s0 = A_FALSE, .rx_delay_s1 = A_FALSE, \ - .tx_delay_s0 = A_FALSE, .tx_delay_s1 = A_FALSE,\ - .rgmii_rxclk_delay = A_TRUE, .rgmii_txclk_delay = A_TRUE, \ - .phy4_rx_delay = A_TRUE, .phy4_tx_delay = A_TRUE,} - -#define def_init_cfg_nocpu {.reg_mode = HSL_MDIO, .cpu_mode = HSL_NO_CPU,}; - -#define def_init_spec_cfg_nocpu { .mac0_rgmii = A_FALSE, .mac5_rgmii = A_FALSE, \ - .rx_delay_s0 = A_FALSE, .rx_delay_s1 = A_FALSE, \ - .tx_delay_s0 = A_FALSE, .tx_delay_s1 = A_FALSE,\ - .rgmii_rxclk_delay = A_TRUE, .rgmii_txclk_delay = A_TRUE, \ - .phy4_rx_delay = A_TRUE, .phy4_tx_delay = A_TRUE,} - -#define def_init_cfg_cpu1_gmii {.reg_mode = HSL_MDIO, .cpu_mode = HSL_CPU_1,}; - -#define def_init_spec_cfg_cpu1_gmii {.mac0_rgmii = A_FALSE, .mac5_rgmii = A_FALSE, \ - .rx_delay_s0 = A_FALSE, .rx_delay_s1 = A_FALSE, \ - .tx_delay_s0 = A_TRUE, .tx_delay_s1 = A_FALSE,\ - .rgmii_rxclk_delay = A_TRUE, .rgmii_txclk_delay = A_TRUE, \ - .phy4_rx_delay = A_TRUE, .phy4_tx_delay = A_TRUE,} - -#define def_init_cfg def_init_cfg_cpu2 -#define def_init_spec_cfg def_init_spec_cfg_cpu2 - -#elif defined SHIVA -#define def_init_cfg {.reg_mode = HSL_MDIO, .cpu_mode = HSL_CPU_2}; -#elif defined HORUS -#define def_init_cfg {.reg_mode = HSL_MDIO, .cpu_mode = HSL_CPU_2}; -#elif defined ISIS -#define def_init_cfg {.reg_mode = HSL_MDIO, .cpu_mode = HSL_CPU_2}; -#elif defined ISISC -#define def_init_cfg {.reg_mode = HSL_MDIO, .cpu_mode = HSL_CPU_2}; -#endif - - typedef struct - { - a_bool_t in_acl; - a_bool_t in_fdb; - a_bool_t in_igmp; - a_bool_t in_leaky; - a_bool_t in_led; - a_bool_t in_mib; - a_bool_t in_mirror; - a_bool_t in_misc; - a_bool_t in_portcontrol; - a_bool_t in_portvlan; - a_bool_t in_qos; - a_bool_t in_rate; - a_bool_t in_stp; - a_bool_t in_vlan; - a_bool_t in_reduced_acl; - a_bool_t in_ip; - a_bool_t in_nat; - a_bool_t in_cosmap; - a_bool_t in_sec; - a_bool_t in_trunk; - a_bool_t in_nathelper; - a_bool_t in_interfacectrl; - } ssdk_features; -/*qca808x_start*/ -#define CFG_STR_SIZE 20 - typedef struct - { - a_uint8_t build_ver[CFG_STR_SIZE]; - a_uint8_t build_date[CFG_STR_SIZE]; - - a_uint8_t chip_type[CFG_STR_SIZE]; //GARUDA - a_uint8_t cpu_type[CFG_STR_SIZE]; //mips - a_uint8_t os_info[CFG_STR_SIZE]; //OS=linux OS_VER=2_6 - - a_bool_t fal_mod; - a_bool_t kernel_mode; - a_bool_t uk_if; -/*qca808x_end*/ - ssdk_features features; -/*qca808x_start*/ - ssdk_init_cfg init_cfg; - } ssdk_cfg_t; - -#define SSDK_RFS_INTF_MAX 8 -typedef struct -{ - a_uint32_t if_idx; /*netdevic idx*/ - fal_mac_addr_t macaddr; - a_uint16_t vid; - a_uint8_t hw_idx; /* HW table entry idx*/ -} ssdk_rfs_intf_t; - -sw_error_t -ssdk_init(a_uint32_t dev_id, ssdk_init_cfg *cfg); -/*qca808x_end*/ -sw_error_t -ssdk_hsl_access_mode_set(a_uint32_t dev_id, hsl_access_mode reg_mode); - -a_uint32_t ssdk_dt_global_get_mac_mode(a_uint32_t dev_id, a_uint32_t index); -a_uint32_t ssdk_dt_global_set_mac_mode(a_uint32_t dev_id, a_uint32_t index, a_uint32_t mode); - -a_uint32_t -qca_hppe_port_mac_type_get(a_uint32_t dev_id, a_uint32_t port_id); -a_uint32_t -qca_hppe_port_mac_type_set(a_uint32_t dev_id, a_uint32_t port_id, a_uint32_t port_type); - -void ssdk_portvlan_init(a_uint32_t dev_id); -sw_error_t ssdk_dess_trunk_init(a_uint32_t dev_id, a_uint32_t wan_bitmap); - -void -qca_mac_port_status_init(a_uint32_t dev_id, a_uint32_t port_id); -void -qca_mac_sw_sync_port_status_init(a_uint32_t dev_id); -/*qca808x_start*/ -struct qca_phy_priv* ssdk_phy_priv_data_get(a_uint32_t dev_id); -/*qca808x_end*/ -sw_error_t qca_switch_init(a_uint32_t dev_id); -void qca_mac_sw_sync_work_stop(struct qca_phy_priv *priv); -void qca_mac_sw_sync_work_resume(struct qca_phy_priv *priv); -int qca_mac_sw_sync_work_start(struct qca_phy_priv *priv); -/*qca808x_start*/ -#ifdef __cplusplus -} -#endif /* __cplusplus */ - -#endif /* _SSDK_INIT_H */ -/*qca808x_end*/ diff --git a/feeds/ipq807x/qca-ssdk/src/include/init/ssdk_interrupt.h b/feeds/ipq807x/qca-ssdk/src/include/init/ssdk_interrupt.h deleted file mode 100755 index fb5ed629f..000000000 --- a/feeds/ipq807x/qca-ssdk/src/include/init/ssdk_interrupt.h +++ /dev/null @@ -1,29 +0,0 @@ -/* - * Copyright (c) 2017, The Linux Foundation. All rights reserved. - * Permission to use, copy, modify, and/or distribute this software for - * any purpose with or without fee is hereby granted, provided that the - * above copyright notice and this permission notice appear in all copies. - * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES - * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR - * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES - * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN - * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT - * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. - */ - -#include "ssdk_plat.h" - -#ifndef _SSDK_INTERRUPT_H_ -#define _SSDK_INTERRUPT_H_ - -#ifdef __cplusplus -extern "C" { -#endif /* __cplusplus */ -int qca_mac_enable_intr(struct qca_phy_priv *priv); -int qca_intr_init(struct qca_phy_priv *priv); - -#ifdef __cplusplus -} -#endif /* __cplusplus */ -#endif /* _SSDK_INTERRUPT_H */ diff --git a/feeds/ipq807x/qca-ssdk/src/include/init/ssdk_led.h b/feeds/ipq807x/qca-ssdk/src/include/init/ssdk_led.h deleted file mode 100644 index 748ea5716..000000000 --- a/feeds/ipq807x/qca-ssdk/src/include/init/ssdk_led.h +++ /dev/null @@ -1,53 +0,0 @@ -/* - * Copyright (c) 2019,2020, The Linux Foundation. All rights reserved. - * Permission to use, copy, modify, and/or distribute this software for - * any purpose with or without fee is hereby granted, provided that the - * above copyright notice and this permission notice appear in all copies. - * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES - * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR - * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES - * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN - * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT - * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. - */ - -#ifndef _SSDK_LED_H_ -#define _SSDK_LED_H_ - -#ifdef __cplusplus -extern "C" { -#endif /* __cplusplus */ - -#define SRC_SELECTION_0 0x0 -#define SRC_SELECTION_1 0x1 -#define SRC_SELECTION_2 0x2 -#define LED_SRC_ID_1 0x1 -#define LED_SRC_ID_2 0x2 -#define LED_SRC_ID_3 0x3 -#define LED_SRC_ID_4 0x4 -#define LED_SRC_ID_5 0x5 -#define LED_SRC_ID_6 0x6 -#define LED_SRC_ID_7 0x7 -#define LED_SRC_ID_8 0x8 -#define LED_SRC_ID_9 0x9 -#define LED_SRC_ID_10 0xa -#define LED_SRC_ID_11 0xb -#define LED_SRC_ID_12 0xc -#define LED_SRC_ID_13 0xd -#define LED_SRC_ID_14 0xe -#define LED_SRC_ID_15 0xf - - -#ifdef DESS -int ssdk_dess_led_init(ssdk_init_cfg *cfg); -#endif - -#ifdef IN_LED -sw_error_t ssdk_led_init(a_uint32_t dev_id, ssdk_init_cfg *cfg); -#endif -#ifdef __cplusplus -} -#endif /* __cplusplus */ -#endif /* _SSDK_LED_H */ - diff --git a/feeds/ipq807x/qca-ssdk/src/include/init/ssdk_mp.h b/feeds/ipq807x/qca-ssdk/src/include/init/ssdk_mp.h deleted file mode 100644 index 90d6062f6..000000000 --- a/feeds/ipq807x/qca-ssdk/src/include/init/ssdk_mp.h +++ /dev/null @@ -1,35 +0,0 @@ -/* - * Copyright (c) 2019-2020, The Linux Foundation. All rights reserved. - * - * Permission to use, copy, modify, and/or distribute this software for any - * purpose with or without fee is hereby granted, provided that the above - * copyright notice and this permission notice appear in all copies. - * - * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES - * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR - * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES - * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN - * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF - * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. - */ - - -#ifndef _SSDK_MP_H_ -#define _SSDK_MP_H_ - -#ifdef __cplusplus -extern "C" { -#endif /* __cplusplus */ - -#include "sw.h" - -#define MP_LPI_WAKEUP_TIMER 0x46 - -sw_error_t qca_mp_hw_init(a_uint32_t dev_id, ssdk_init_cfg *cfg); - -#ifdef __cplusplus -} -#endif /* __cplusplus */ -#endif /* _SSDK_MP_H */ - diff --git a/feeds/ipq807x/qca-ssdk/src/include/init/ssdk_phy_i2c.h b/feeds/ipq807x/qca-ssdk/src/include/init/ssdk_phy_i2c.h deleted file mode 100755 index e682c8a9f..000000000 --- a/feeds/ipq807x/qca-ssdk/src/include/init/ssdk_phy_i2c.h +++ /dev/null @@ -1,76 +0,0 @@ -/* - * Copyright (c) 2018, The Linux Foundation. All rights reserved. - * Permission to use, copy, modify, and/or distribute this software for - * any purpose with or without fee is hereby granted, provided that the - * above copyright notice and this permission notice appear in all copies. - * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES - * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR - * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES - * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN - * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT - * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. - */ - -#ifndef _SSDK_PHY_I2C_H_ -#define _SSDK_PHY_I2C_H_ - -#ifdef __cplusplus -extern "C" -{ -#endif /* __cplusplus */ - -#define QCA_PHY_I2C_MMD_OR_MII_SHIFT 6 -#define QCA_PHY_I2C_IS_MMD 1 -#define QCA_PHY_I2C_IS_MII 0 -#define QCA_PHY_I2C_MMD_ADDR_OR_DATA_SHIFT 5 -#define QCA_PHY_I2C_MMD_IS_ADDR 1 -#define QCA_PHY_I2C_MMD_IS_DATA 0 - -#define QCA_PHY_MII_ADDR_C45 (1<<30) -#define QCA_PHY_MII_ADDR_C45_IS_MMD(reg_addr_c45) ((reg_addr_c45) & QCA_PHY_MII_ADDR_C45) -#define QCA_PHY_MII_ADDR_C45_MMD_NUM(reg_addr_c45) (((reg_addr_c45) >> 16) & 0x1f) -#define QCA_PHY_MII_ADDR_C45_REG_ADDR(reg_addr_c45) ((reg_addr_c45) & 0xffff) - -#define QCA_PHY_I2C_PHYCORE_DEVADDR 0x44 -#define QCA_PHY_I2C_SERDES_DEVADDR 0x45 -#define QCA_PHY_I2C_DEVADDR_MASK 0x47 - -#define QCA_PHY_MMD1_NUM 1 -#define QCA_PHY_MMD3_NUM 3 -#define QCA_PHY_MMD7_NUM 7 - -sw_error_t -qca_phy_i2c_mii_read(a_uint32_t dev_id, a_uint32_t phy_addr, - a_uint32_t reg_addr, a_uint16_t *reg_data); -sw_error_t -qca_phy_i2c_mii_write(a_uint32_t dev_id, a_uint32_t phy_addr, - a_uint32_t reg_addr, a_uint16_t reg_data); -sw_error_t -qca_i2c_data_get(a_uint32_t dev_id, a_uint32_t i2c_slave, - a_uint32_t data_addr, a_uint8_t *buf, a_uint32_t count); - -sw_error_t -qca_i2c_data_set(a_uint32_t dev_id, a_uint32_t i2c_slave, - a_uint32_t data_addr, a_uint8_t *buf, a_uint32_t count); - -#ifdef IN_PHY_I2C_MODE -sw_error_t -qca_phy_i2c_mmd_read(a_uint32_t dev_id, a_uint32_t phy_addr, a_uint16_t mmd_num, - a_uint32_t reg_addr, a_uint16_t *reg_data); -sw_error_t -qca_phy_i2c_mmd_write(a_uint32_t dev_id, a_uint32_t phy_addr, a_uint16_t mmd_num, - a_uint32_t reg_addr, a_uint16_t reg_data); -a_bool_t -qca_phy_is_i2c_addr(a_uint32_t phy_addr); -sw_error_t -qca_phy_i2c_read(a_uint32_t dev_id, a_uint32_t phy_addr, - a_uint32_t reg_addr_c45, a_uint16_t *reg_data); -sw_error_t -qca_phy_i2c_write(a_uint32_t dev_id, a_uint32_t phy_addr, - a_uint32_t reg_addr_c45, a_uint16_t reg_data); -#endif -#ifdef __cplusplus -} -#endif /* __cplusplus */ -#endif /* _SSDK_PHY_I2C_H_ */ diff --git a/feeds/ipq807x/qca-ssdk/src/include/init/ssdk_plat.h b/feeds/ipq807x/qca-ssdk/src/include/init/ssdk_plat.h deleted file mode 100755 index 1463102ed..000000000 --- a/feeds/ipq807x/qca-ssdk/src/include/init/ssdk_plat.h +++ /dev/null @@ -1,414 +0,0 @@ -/* - * Copyright (c) 2012, 2014-2015, 2017-2020, The Linux Foundation. All rights reserved. - * Permission to use, copy, modify, and/or distribute this software for - * any purpose with or without fee is hereby granted, provided that the - * above copyright notice and this permission notice appear in all copies. - * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES - * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR - * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES - * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN - * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT - * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. - */ -/*qca808x_start*/ -#ifndef __SSDK_PLAT_H -#define __SSDK_PLAT_H - -#include "sw.h" -/*qca808x_end*/ -#include -#include -#include -#include -#if defined(IN_SWCONFIG) -#if defined(CONFIG_OF) && (LINUX_VERSION_CODE >= KERNEL_VERSION(3,14,0)) -#include -#else -#include -#endif -#endif -/*qca808x_start*/ -#include - -#ifndef BIT -#define BIT(_n) (1UL << (_n)) -#endif - - -#ifndef BITS -#define BITS(_s, _n) (((1UL << (_n)) - 1) << _s) -#endif - -/* Atheros specific MII registers */ -#define QCA_MII_MMD_ADDR 0x0d -#define QCA_MII_MMD_DATA 0x0e -#define QCA_MII_DBG_ADDR 0x1d -#define QCA_MII_DBG_DATA 0x1e -/*qca808x_end*/ -#define AR8327_REG_CTRL 0x0000 -#define AR8327_CTRL_REVISION BITS(0, 8) -#define AR8327_CTRL_REVISION_S 0 -#define AR8327_CTRL_VERSION BITS(8, 8) -#define AR8327_CTRL_VERSION_S 8 -#define AR8327_CTRL_RESET BIT(31) - -#define AR8327_REG_LED_CTRL_0 0x50 -#define AR8327_REG_LED_CTRL_1 0x54 -#define AR8327_REG_LED_CTRL_2 0x58 -#define AR8327_REG_LED_CTRL_3 0x5c - -#define AR8327_REG_PORT_STATUS(_i) (0x07c + (_i) * 4) - -#define AR8327_PORT_STATUS_SPEED BITS(0,2) -#define AR8327_PORT_STATUS_SPEED_S 0 -#define AR8327_PORT_STATUS_TXMAC BIT(2) -#define AR8327_PORT_STATUS_RXMAC BIT(3) -#define AR8327_PORT_STATUS_TXFLOW BIT(4) -#define AR8327_PORT_STATUS_RXFLOW BIT(5) -#define AR8327_PORT_STATUS_DUPLEX BIT(6) -#define AR8327_PORT_STATUS_LINK_UP BIT(8) -#define AR8327_PORT_STATUS_LINK_AUTO BIT(9) -#define AR8327_PORT_STATUS_LINK_PAUSE BIT(10) - -#define AR8327_REG_PAD0_CTRL 0x4 -#define AR8327_REG_PAD5_CTRL 0x8 -#define AR8327_REG_PAD6_CTRL 0xc -#define AR8327_PAD_CTRL_MAC_MII_RXCLK_SEL BIT(0) -#define AR8327_PAD_CTRL_MAC_MII_TXCLK_SEL BIT(1) -#define AR8327_PAD_CTRL_MAC_MII_EN BIT(2) -#define AR8327_PAD_CTRL_MAC_GMII_RXCLK_SEL BIT(4) -#define AR8327_PAD_CTRL_MAC_GMII_TXCLK_SEL BIT(5) -#define AR8327_PAD_CTRL_MAC_GMII_EN BIT(6) -#define AR8327_PAD_CTRL_SGMII_EN BIT(7) -#define AR8327_PAD_CTRL_PHY_MII_RXCLK_SEL BIT(8) -#define AR8327_PAD_CTRL_PHY_MII_TXCLK_SEL BIT(9) -#define AR8327_PAD_CTRL_PHY_MII_EN BIT(10) -#define AR8327_PAD_CTRL_PHY_GMII_PIPE_RXCLK_SEL BIT(11) -#define AR8327_PAD_CTRL_PHY_GMII_RXCLK_SEL BIT(12) -#define AR8327_PAD_CTRL_PHY_GMII_TXCLK_SEL BIT(13) -#define AR8327_PAD_CTRL_PHY_GMII_EN BIT(14) -#define AR8327_PAD_CTRL_PHYX_GMII_EN BIT(16) -#define AR8327_PAD_CTRL_PHYX_RGMII_EN BIT(17) -#define AR8327_PAD_CTRL_PHYX_MII_EN BIT(18) -#define AR8327_PAD_CTRL_RGMII_RXCLK_DELAY_SEL BITS(20, 2) -#define AR8327_PAD_CTRL_RGMII_RXCLK_DELAY_SEL_S 20 -#define AR8327_PAD_CTRL_RGMII_TXCLK_DELAY_SEL BITS(22, 2) -#define AR8327_PAD_CTRL_RGMII_TXCLK_DELAY_SEL_S 22 -#define AR8327_PAD_CTRL_RGMII_RXCLK_DELAY_EN BIT(24) -#define AR8327_PAD_CTRL_RGMII_TXCLK_DELAY_EN BIT(25) -#define AR8327_PAD_CTRL_RGMII_EN BIT(26) - -#define AR8327_PORT5_PHY_ADDR 4 -/*AR8327 inner phy debug register for RGMII mode*/ -#define AR8327_PHY_REG_MODE_SEL 0x12 -#define AR8327_PHY_RGMII_MODE BIT(3) -#define AR8327_PHY_REG_TEST_CTRL 0x0 -#define AR8327_PHY_RGMII_RX_DELAY BIT(15) -#define AR8327_PHY_REG_SYS_CTRL 0x5 -#define AR8327_PHY_RGMII_TX_DELAY BIT(8) - - -#define AR8327_REG_POS 0x10 -#define AR8327_REG_POS_HW_INIT 0x261320 -#define AR8327_POS_POWER_ON_SEL BIT(31) -#define AR8327_POS_LED_OPEN_EN BIT(24) -#define AR8327_POS_SERDES_AEN BIT(7) - -#define AR8327_REG_MODULE_EN 0x30 -#define AR8327_REG_MODULE_EN_QM_ERR BIT(8) -#define AR8327_REG_MODULE_EN_LOOKUP_ERR BIT(9) - -#define AR8327_REG_MAC_SFT_RST 0x68 - -#define AR8327_REG_PAD_SGMII_CTRL 0xe0 -#define AR8327_REG_PAD_SGMII_CTRL_HW_INIT 0xc70164c0 -#define AR8327_PAD_SGMII_CTRL_MODE_CTRL BITS(22, 2) -#define AR8327_PAD_SGMII_CTRL_MODE_CTRL_S 22 -#define AR8327_PAD_SGMII_CTRL_EN_SD BIT(4) -#define AR8327_PAD_SGMII_CTRL_EN_TX BIT(3) -#define AR8327_PAD_SGMII_CTRL_EN_RX BIT(2) -#define AR8327_PAD_SGMII_CTRL_EN_PLL BIT(1) -#define AR8327_PAD_SGMII_CTRL_EN_LCKDT BIT(0) - -#define AR8327_REG_PAD_MAC_PWR_SEL 0x0e4 -#define AR8327_PAD_MAC_PWR_RGMII0_1_8V BIT(18) -#define AR8327_PAD_MAC_PWR_RGMII1_1_8V BIT(19) - -#define AR8327_REG_PORT_LOOKUP(_i) (0x660 + (_i) * 0xc) -#define AR8327_REG_PORT_VLAN0(_i) (0x420 + (_i) * 0x8) - -#define DESS_PSGMII_MODE_CONTROL 0x1b4 -#define DESS_PSGMII_ATHR_CSCO_MODE_25M BIT(0) - -#define DESS_PSGMIIPHY_TX_CONTROL 0x288 - -#define DESS_PSGMII_PLL_VCO_RELATED_CONTROL_1 0x78c -#define DESS_PSGMII_MII_REG_UPHY_PLL_LCKDT_EN BIT(0) - -#define DESS_PSGMII_VCO_CALIBRATION_CONTROL_1 0x9c - -#define SSDK_PSGMII_ID 5 -/*qca808x_start*/ -#define SSDK_PHY_BCAST_ID 0x1f -#define SSDK_PHY_MIN_ID 0x0 -#define SSDK_PORT_CPU 0 -/*qca808x_end*/ -#define SSDK_PORT0_FC_THRESH_ON_DFLT 0x60 -#define SSDK_PORT0_FC_THRESH_OFF_DFLT 0x90 - -#define AR8327_NUM_PHYS 5 -#define AR8327_PORT_CPU 0 -#define AR8327_NUM_PORTS 7 -#define AR8327_MAX_VLANS 128 - -#define MII_PHYADDR_C45 (1<<30) - -#define SSDK_GPIO_RESET 0 -#define SSDK_GPIO_RELEASE 1 -#define SSDK_INVALID_GPIO 0 - -enum { - AR8327_PORT_SPEED_10M = 0, - AR8327_PORT_SPEED_100M = 1, - AR8327_PORT_SPEED_1000M = 2, - AR8327_PORT_SPEED_NONE = 3, -}; -/*qca808x_start*/ -enum { - QCA_VER_AR8216 = 0x01, - QCA_VER_AR8227 = 0x02, - QCA_VER_AR8236 = 0x03, - QCA_VER_AR8316 = 0x10, - QCA_VER_AR8327 = 0x12, - QCA_VER_AR8337 = 0x13, - QCA_VER_DESS = 0x14, - QCA_VER_HPPE = 0x15, - QCA_VER_SCOMPHY = 0xEE -}; -/*qca808x_end*/ -/*poll mib per 120secs*/ -#define QCA_PHY_MIB_WORK_DELAY 120000 -#define QCA_MIB_ITEM_NUMBER \ - (sizeof(fal_mib_counter_t)/sizeof(a_uint64_t)) - -#define SSDK_MAX_UNIPHY_INSTANCE 3 -#define SSDK_UNIPHY_INSTANCE0 0 -#define SSDK_UNIPHY_INSTANCE1 1 -#define SSDK_UNIPHY_INSTANCE2 2 -#define SSDK_UNIPHY_CHANNEL0 0 -#define SSDK_UNIPHY_CHANNEL1 1 -#define SSDK_UNIPHY_CHANNEL4 4 - -/*qca808x_start*/ -#define SSDK_PHYSICAL_PORT0 0 -#define SSDK_PHYSICAL_PORT1 1 -#define SSDK_PHYSICAL_PORT2 2 -#define SSDK_PHYSICAL_PORT3 3 -#define SSDK_PHYSICAL_PORT4 4 -#define SSDK_PHYSICAL_PORT5 5 -#define SSDK_PHYSICAL_PORT6 6 -#define SSDK_PHYSICAL_PORT7 7 -/*qca808x_end*/ -#define SSDK_GLOBAL_INT0_ACL_INI_INT (1<<29) -#define SSDK_GLOBAL_INT0_LOOKUP_INI_INT (1<<28) -#define SSDK_GLOBAL_INT0_QM_INI_INT (1<<27) -#define SSDK_GLOBAL_INT0_MIB_INI_INT (1<<26) -#define SSDK_GLOBAL_INT0_OFFLOAD_INI_INT (1<<25) -#define SSDK_GLOBAL_INT0_HARDWARE_INI_DONE (1<<24) - -#define SSDK_GLOBAL_INITIALIZED_STATUS \ - ( \ - SSDK_GLOBAL_INT0_ACL_INI_INT | \ - SSDK_GLOBAL_INT0_LOOKUP_INI_INT | \ - SSDK_GLOBAL_INT0_QM_INI_INT | \ - SSDK_GLOBAL_INT0_MIB_INI_INT | \ - SSDK_GLOBAL_INT0_OFFLOAD_INI_INT | \ - SSDK_GLOBAL_INT0_HARDWARE_INI_DONE \ - ) -/*qca808x_start*/ -#define SSDK_LOG_LEVEL_ERROR 0 -#define SSDK_LOG_LEVEL_WARN 1 -#define SSDK_LOG_LEVEL_INFO 2 -#define SSDK_LOG_LEVEL_DEBUG 3 -#define SSDK_LOG_LEVEL_DEFAULT SSDK_LOG_LEVEL_INFO - -extern a_uint32_t ssdk_log_level; - -#define __SSDK_LOG_FUN(lev, fmt, ...) \ - do { \ - if (SSDK_LOG_LEVEL_##lev <= ssdk_log_level) { \ - printk("%s[%u]:"#lev":"fmt, \ - __FUNCTION__, __LINE__, ##__VA_ARGS__); \ - } \ - } while(0) -#define SSDK_DUMP_BUF(lev, buf, len) \ - do {\ - if (SSDK_LOG_LEVEL_##lev <= ssdk_log_level) {\ - a_uint32_t i_buf = 0;\ - for(i_buf=0; i_buf<(len); i_buf++) {\ - printk(KERN_CONT "%08lx ", *((buf)+i_buf));\ - }\ - printk(KERN_CONT "\n");\ - }\ - } while(0) - -#define SSDK_ERROR(fmt, ...) __SSDK_LOG_FUN(ERROR, fmt, ##__VA_ARGS__) -#define SSDK_WARN(fmt, ...) __SSDK_LOG_FUN(WARN, fmt, ##__VA_ARGS__) -#define SSDK_INFO(fmt, ...) __SSDK_LOG_FUN(INFO, fmt, ##__VA_ARGS__) -#define SSDK_DEBUG(fmt, ...) __SSDK_LOG_FUN(DEBUG, fmt, ##__VA_ARGS__) - -struct qca_phy_priv { - struct phy_device *phy; -#if defined(IN_SWCONFIG) - struct switch_dev sw_dev; -#endif - a_uint8_t version; - a_uint8_t revision; - a_uint32_t (*mii_read)(a_uint32_t dev_id, a_uint32_t reg); - void (*mii_write)(a_uint32_t dev_id, a_uint32_t reg, a_uint32_t val); - void (*phy_dbg_write)(a_uint32_t dev_id, a_uint32_t phy_addr, - a_uint16_t dbg_addr, a_uint16_t dbg_data); - void (*phy_dbg_read)(a_uint32_t dev_id, a_uint32_t phy_addr, - a_uint16_t dbg_addr, a_uint16_t *dbg_data); - void (*phy_mmd_write)(a_uint32_t dev_id, a_uint32_t phy_addr, - a_uint16_t addr, a_uint16_t data); - sw_error_t (*phy_write)(a_uint32_t dev_id, a_uint32_t phy_addr, - a_uint32_t reg, a_uint16_t data); - sw_error_t (*phy_read)(a_uint32_t dev_id, a_uint32_t phy_addr, - a_uint32_t reg, a_uint16_t* data); - - bool init; -/*qca808x_end*/ - a_bool_t qca_ssdk_sw_dev_registered; - a_bool_t ess_switch_flag; - struct mutex reg_mutex; - struct mutex mib_lock; - struct delayed_work mib_dwork; - /*qm_err_check*/ - struct mutex qm_lock; - a_uint32_t port_link_down[SW_MAX_NR_PORT]; - a_uint32_t port_link_up[SW_MAX_NR_PORT]; - a_uint32_t port_old_link[SW_MAX_NR_PORT]; - a_uint32_t port_old_speed[SW_MAX_NR_PORT]; - a_uint32_t port_old_duplex[SW_MAX_NR_PORT]; - a_uint32_t port_old_phy_status[SW_MAX_NR_PORT]; - a_uint32_t port_qm_buf[SW_MAX_NR_PORT]; - a_bool_t port_old_tx_flowctrl[SW_MAX_NR_PORT]; - a_bool_t port_old_rx_flowctrl[SW_MAX_NR_PORT]; - a_bool_t port_tx_flowctrl_forcemode[SW_MAX_NR_PORT]; - a_bool_t port_rx_flowctrl_forcemode[SW_MAX_NR_PORT]; - struct delayed_work qm_dwork_polling; - struct work_struct intr_workqueue; - /*qm_err_check end*/ -/*qca808x_start*/ - a_uint8_t device_id; - struct device_node *of_node; -/*qca808x_end*/ - /*dess_rgmii_mac*/ - struct mutex rgmii_lock; - struct delayed_work rgmii_dwork; - /*dess_rgmii_mac end*/ - /*hppe_mac_sw_sync*/ - struct mutex mac_sw_sync_lock; - struct delayed_work mac_sw_sync_dwork; - /*hppe_mac_sw_sync end*/ -/*qca808x_start*/ - struct mii_bus *miibus; -/*qca808x_end*/ - u64 *mib_counters; - /* dump buf */ - a_uint8_t buf[2048]; - a_uint32_t link_polling_required; - /* it is valid only when link_polling_required is false*/ - a_uint32_t link_interrupt_no; - a_uint32_t interrupt_flag; - char link_intr_name[IFNAMSIZ]; - /* VLAN database */ - bool vlan; /* True: 1q vlan mode, False: port vlan mode */ - a_uint16_t vlan_id[AR8327_MAX_VLANS]; - a_uint8_t vlan_table[AR8327_MAX_VLANS]; - a_uint8_t vlan_tagged[AR8327_MAX_VLANS]; - a_uint16_t pvid[SSDK_MAX_PORT_NUM]; - a_uint32_t ports; - u8 __iomem *hw_addr; - u8 __iomem *psgmii_hw_addr; - u8 __iomem *uniphy_hw_addr; -/*qca808x_start*/ -}; - -struct ipq40xx_mdio_data { - struct mii_bus *mii_bus; - void __iomem *membase; - int phy_irq[PHY_MAX_ADDR]; -}; - -#if defined(IN_SWCONFIG) -#define qca_phy_priv_get(_dev) \ - container_of(_dev, struct qca_phy_priv, sw_dev) -#endif - -/*qca808x_end*/ -a_uint32_t -qca_ar8216_mii_read(a_uint32_t dev_id, a_uint32_t reg); -void -qca_ar8216_mii_write(a_uint32_t dev_id, a_uint32_t reg, a_uint32_t val); -/*qca808x_start*/ -sw_error_t -qca_ar8327_phy_read(a_uint32_t dev_id, a_uint32_t phy_addr, - a_uint32_t reg, a_uint16_t* data); -sw_error_t -qca_ar8327_phy_write(a_uint32_t dev_id, a_uint32_t phy_addr, - a_uint32_t reg, a_uint16_t data); -void -qca_ar8327_mmd_write(a_uint32_t dev_id, a_uint32_t phy_addr, - a_uint16_t addr, a_uint16_t data); -void -qca_ar8327_phy_dbg_write(a_uint32_t dev_id, a_uint32_t phy_addr, - a_uint16_t dbg_addr, a_uint16_t dbg_data); -void -qca_ar8327_phy_dbg_read(a_uint32_t dev_id, a_uint32_t phy_addr, - a_uint16_t dbg_addr, a_uint16_t *dbg_data); - -void -qca_phy_mmd_write(u32 dev_id, u32 phy_id, - u16 mmd_num, u16 reg_id, u16 reg_val); - -u16 -qca_phy_mmd_read(u32 dev_id, u32 phy_id, - u16 mmd_num, u16 reg_id); -/*qca808x_end*/ -sw_error_t -qca_switch_reg_read(a_uint32_t dev_id, a_uint32_t reg_addr, - a_uint8_t * reg_data, a_uint32_t len); - -sw_error_t -qca_switch_reg_write(a_uint32_t dev_id, a_uint32_t reg_addr, - a_uint8_t * reg_data, a_uint32_t len); - -sw_error_t -qca_psgmii_reg_read(a_uint32_t dev_id, a_uint32_t reg_addr, - a_uint8_t * reg_data, a_uint32_t len); - -sw_error_t -qca_psgmii_reg_write(a_uint32_t dev_id, a_uint32_t reg_addr, - a_uint8_t * reg_data, a_uint32_t len); - -sw_error_t -qca_uniphy_reg_write(a_uint32_t dev_id, a_uint32_t uniphy_index, - a_uint32_t reg_addr, a_uint8_t * reg_data, a_uint32_t len); - -sw_error_t -qca_uniphy_reg_read(a_uint32_t dev_id, a_uint32_t uniphy_index, - a_uint32_t reg_addr, a_uint8_t * reg_data, a_uint32_t len); - -struct mii_bus *ssdk_miibus_get_by_device(a_uint32_t dev_id); - -int ssdk_sysfs_init (void); -void ssdk_sysfs_exit (void); -/*qca808x_start*/ -int ssdk_plat_init(ssdk_init_cfg *cfg, a_uint32_t dev_id); -void ssdk_plat_exit(a_uint32_t dev_id); - -#endif -/*qca808x_end*/ diff --git a/feeds/ipq807x/qca-ssdk/src/include/init/ssdk_scomphy.h b/feeds/ipq807x/qca-ssdk/src/include/init/ssdk_scomphy.h deleted file mode 100755 index 45ef0ffa6..000000000 --- a/feeds/ipq807x/qca-ssdk/src/include/init/ssdk_scomphy.h +++ /dev/null @@ -1,33 +0,0 @@ -/* - * Copyright (c) 2019, The Linux Foundation. All rights reserved. - * - * Permission to use, copy, modify, and/or distribute this software for any - * purpose with or without fee is hereby granted, provided that the above - * copyright notice and this permission notice appear in all copies. - * - * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES - * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR - * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES - * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN - * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF - * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. - */ - - -#ifndef _SSDK_SCOMPHY_H_ -#define _SSDK_SCOMPHY_H_ - -#ifdef __cplusplus -extern "C" { -#endif /* __cplusplus */ - -#include "ssdk_init.h" - -sw_error_t qca_scomphy_hw_init(ssdk_init_cfg *cfg, a_uint32_t dev_id); - -#ifdef __cplusplus -} -#endif /* __cplusplus */ -#endif /* _SSDK_SCOMPY_H */ - diff --git a/feeds/ipq807x/qca-ssdk/src/include/init/ssdk_uci.h b/feeds/ipq807x/qca-ssdk/src/include/init/ssdk_uci.h deleted file mode 100755 index 52cc0a969..000000000 --- a/feeds/ipq807x/qca-ssdk/src/include/init/ssdk_uci.h +++ /dev/null @@ -1,31 +0,0 @@ -/* - * Copyright (c) 2014, The Linux Foundation. All rights reserved. - * Permission to use, copy, modify, and/or distribute this software for - * any purpose with or without fee is hereby granted, provided that the - * above copyright notice and this permission notice appear in all copies. - * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES - * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR - * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES - * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN - * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT - * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. - */ - -#ifndef _SSDK_UCI_H_ -#define _SSDK_UCI_H_ - -#ifdef BOARD_AR71XX -int ssdk_uci_takeover_init(void); -void ssdk_uci_takeover_exit(void); -int ssdk_uci_sw_set_vlan(const struct switch_attr *attr, - struct switch_val *val); -int ssdk_uci_sw_set_vid(const struct switch_attr *attr, - struct switch_val *val); -int ssdk_uci_sw_set_pvid(int port, int vlan); -int ssdk_uci_sw_set_ports(struct switch_val *val); - - -#endif - -#endif diff --git a/feeds/ipq807x/qca-ssdk/src/include/ref/ref_api.h b/feeds/ipq807x/qca-ssdk/src/include/ref/ref_api.h deleted file mode 100755 index ec3d9371a..000000000 --- a/feeds/ipq807x/qca-ssdk/src/include/ref/ref_api.h +++ /dev/null @@ -1,47 +0,0 @@ -/* - * Copyright (c) 2019, The Linux Foundation. All rights reserved. - * - * Permission to use, copy, modify, and/or distribute this software for any - * purpose with or without fee is hereby granted, provided that the above - * copyright notice and this permission notice appear in all copies. - * - * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES - * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR - * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES - * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN - * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF - * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. - */ - -#ifndef _REF_API_H_ -#define _REF_API_H_ - -#ifdef __cplusplus -extern "C" { -#endif /* __cplusplus */ - -#if defined(IN_VLAN) && !defined(IN_VLAN_MINI) -#define REF_VLAN_API \ - SW_API_DEF(SW_API_LAN_WAN_CFG_SET, qca_lan_wan_cfg_set), \ - SW_API_DEF(SW_API_LAN_WAN_CFG_GET, qca_lan_wan_cfg_get), - -#define REF_VLAN_API_PARAM \ - SW_API_DESC(SW_API_LAN_WAN_CFG_SET) \ - SW_API_DESC(SW_API_LAN_WAN_CFG_GET) - -#else -#define REF_VLAN_API -#define REF_VLAN_API_PARAM -#endif - -#define SSDK_REF_API \ - REF_VLAN_API - -#define SSDK_REF_PARAM \ - REF_VLAN_API_PARAM - -#ifdef __cplusplus -} -#endif /* __cplusplus */ -#endif /* _REF_API_H_ */ diff --git a/feeds/ipq807x/qca-ssdk/src/include/ref/ref_fdb.h b/feeds/ipq807x/qca-ssdk/src/include/ref/ref_fdb.h deleted file mode 100755 index 31592c8f4..000000000 --- a/feeds/ipq807x/qca-ssdk/src/include/ref/ref_fdb.h +++ /dev/null @@ -1,54 +0,0 @@ -/* - * Copyright (c) 2012,2018, The Linux Foundation. All rights reserved. - * Permission to use, copy, modify, and/or distribute this software for - * any purpose with or without fee is hereby granted, provided that the - * above copyright notice and this permission notice appear in all copies. - * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES - * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR - * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES - * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN - * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT - * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. - */ - -#ifndef _REF_FDB_H_ -#define _REF_FDB_H_ - -#ifdef __cplusplus -extern "C" { -#endif /* __cplusplus */ - -#include -#if defined(IN_SWCONFIG) -#if defined(CONFIG_OF) && (LINUX_VERSION_CODE >= KERNEL_VERSION(3,14,0)) -#include -#else -#include -#endif -#endif - -#include -#include "sw.h" -#include "fal/fal_type.h" - -#if defined(IN_SWCONFIG) -int - qca_ar8327_sw_atu_flush(struct switch_dev *dev, - const struct switch_attr *attr, - struct switch_val *val); - -int -qca_ar8327_sw_atu_dump(struct switch_dev *dev, - const struct switch_attr *attr, - struct switch_val *val); -#endif - -fal_port_t -ref_fdb_get_port_by_mac(unsigned int vid, const char * addr); - -#ifdef __cplusplus -} -#endif /* __cplusplus */ -#endif /* _REF_FDB_H_ */ - diff --git a/feeds/ipq807x/qca-ssdk/src/include/ref/ref_mib.h b/feeds/ipq807x/qca-ssdk/src/include/ref/ref_mib.h deleted file mode 100755 index 6cb063956..000000000 --- a/feeds/ipq807x/qca-ssdk/src/include/ref/ref_mib.h +++ /dev/null @@ -1,50 +0,0 @@ -/* - * Copyright (c) 2012, The Linux Foundation. All rights reserved. - * Permission to use, copy, modify, and/or distribute this software for - * any purpose with or without fee is hereby granted, provided that the - * above copyright notice and this permission notice appear in all copies. - * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES - * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR - * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES - * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN - * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT - * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. - */ - -#ifndef _REF_MIB_H_ -#define _REF_MIB_H_ - -#ifdef __cplusplus -extern "C" { -#endif /* __cplusplus */ - -#if defined(IN_SWCONFIG) -#if defined(CONFIG_OF) && (LINUX_VERSION_CODE >= KERNEL_VERSION(3,14,0)) -#include -#else -#include -#endif - -int -qca_ar8327_sw_set_reset_mibs(struct switch_dev *dev, - const struct switch_attr *attr, - struct switch_val *val); - -int -qca_ar8327_sw_set_port_reset_mib(struct switch_dev *dev, - const struct switch_attr *attr, - struct switch_val *val); - - -int -qca_ar8327_sw_get_port_mib(struct switch_dev *dev, - const struct switch_attr *attr, - struct switch_val *val); - -#endif -#ifdef __cplusplus -} -#endif /* __cplusplus */ -#endif /* _REF_MIB_H_ */ - diff --git a/feeds/ipq807x/qca-ssdk/src/include/ref/ref_misc.h b/feeds/ipq807x/qca-ssdk/src/include/ref/ref_misc.h deleted file mode 100755 index 70ab4b9b8..000000000 --- a/feeds/ipq807x/qca-ssdk/src/include/ref/ref_misc.h +++ /dev/null @@ -1,41 +0,0 @@ -/* - * Copyright (c) 2012, The Linux Foundation. All rights reserved. - * Permission to use, copy, modify, and/or distribute this software for - * any purpose with or without fee is hereby granted, provided that the - * above copyright notice and this permission notice appear in all copies. - * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES - * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR - * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES - * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN - * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT - * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. - */ - -#ifndef _REF_MISC_H_ -#define _REF_MISC_H_ - -#ifdef __cplusplus -extern "C" { -#endif /* __cplusplus */ - -#if defined(IN_SWCONFIG) -int -qca_ar8327_sw_set_max_frame_size(struct switch_dev *dev, - const struct switch_attr *attr, - struct switch_val *val); - -int -qca_ar8327_sw_get_max_frame_size(struct switch_dev *dev, - const struct switch_attr *attr, - struct switch_val *val); - -int -qca_ar8327_sw_reset_switch(struct switch_dev *dev); -#endif - -#ifdef __cplusplus -} -#endif /* __cplusplus */ -#endif /* _REF_MISC_H_ */ - diff --git a/feeds/ipq807x/qca-ssdk/src/include/ref/ref_port_ctrl.h b/feeds/ipq807x/qca-ssdk/src/include/ref/ref_port_ctrl.h deleted file mode 100755 index b614c95d6..000000000 --- a/feeds/ipq807x/qca-ssdk/src/include/ref/ref_port_ctrl.h +++ /dev/null @@ -1,62 +0,0 @@ -/* - * Copyright (c) 2012, The Linux Foundation. All rights reserved. - * Permission to use, copy, modify, and/or distribute this software for - * any purpose with or without fee is hereby granted, provided that the - * above copyright notice and this permission notice appear in all copies. - * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES - * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR - * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES - * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN - * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT - * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. - */ - -#ifndef _REF_PORT_CTRL_H_ -#define _REF_PORT_CTRL_H_ - -#ifdef __cplusplus -extern "C" { -#endif /* __cplusplus */ - -#include -#if defined(IN_SWCONFIG) -#if defined(CONFIG_OF) && (LINUX_VERSION_CODE >= KERNEL_VERSION(3,14,0)) -#include -#else -#include -#endif -#endif - -#include - -/** - * @brief QCA SSDK port link context - */ - -typedef struct{ - unsigned char port_id;/*port 1-5*/ - unsigned char port_link; /*0:linkdown, 1:linkup*/ - unsigned char speed; /*0:10M, 1:100M, 2:1000M*/ - unsigned char duplex;/*0:half, 1:full*/ -}ssdk_port_status; - -#if defined(IN_SWCONFIG) -int -qca_ar8327_sw_get_port_link(struct switch_dev *dev, int port, - struct switch_port_link *link); -int qca_ar8327_sw_set_eee(struct switch_dev *dev, - const struct switch_attr *attr, struct switch_val *val); -int qca_ar8327_sw_get_eee(struct switch_dev *dev, - const struct switch_attr *attr, struct switch_val *val); -#endif - -int ssdk_port_link_notify_register(struct notifier_block *nb); -int ssdk_port_link_notify_unregister(struct notifier_block *nb); -int ssdk_port_link_notify(unsigned char port_id, - unsigned char link, unsigned char speed, unsigned char duplex); -#ifdef __cplusplus -} -#endif /* __cplusplus */ -#endif /* _REF_PORT_CTRL_H_ */ - diff --git a/feeds/ipq807x/qca-ssdk/src/include/ref/ref_uci.h b/feeds/ipq807x/qca-ssdk/src/include/ref/ref_uci.h deleted file mode 100755 index 107a9e7c9..000000000 --- a/feeds/ipq807x/qca-ssdk/src/include/ref/ref_uci.h +++ /dev/null @@ -1,35 +0,0 @@ -/* - * Copyright (c) 2012, The Linux Foundation. All rights reserved. - * Permission to use, copy, modify, and/or distribute this software for - * any purpose with or without fee is hereby granted, provided that the - * above copyright notice and this permission notice appear in all copies. - * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES - * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR - * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES - * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN - * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT - * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. - */ - -#ifndef _REF_UCI_H_ -#define _REF_UCI_H_ - -#ifdef __cplusplus -extern "C" { -#endif /* __cplusplus */ - - -#if defined(IN_SWCONFIG) -int -qca_ar8327_sw_switch_ext(struct switch_dev *dev, - const struct switch_attr *attr, - struct switch_val *val); -#endif - - -#ifdef __cplusplus -} -#endif /* __cplusplus */ -#endif /* _REF_FDB_H_ */ - diff --git a/feeds/ipq807x/qca-ssdk/src/include/ref/ref_vlan.h b/feeds/ipq807x/qca-ssdk/src/include/ref/ref_vlan.h deleted file mode 100755 index e76bbac3b..000000000 --- a/feeds/ipq807x/qca-ssdk/src/include/ref/ref_vlan.h +++ /dev/null @@ -1,88 +0,0 @@ -/* - * Copyright (c) 2012, The Linux Foundation. All rights reserved. - * Permission to use, copy, modify, and/or distribute this software for - * any purpose with or without fee is hereby granted, provided that the - * above copyright notice and this permission notice appear in all copies. - * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES - * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR - * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES - * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN - * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT - * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. - */ - -#ifndef _REF_VLAN_H_ -#define _REF_VLAN_H_ - -#ifdef __cplusplus -extern "C" { -#endif /* __cplusplus */ - -#if defined(IN_SWCONFIG) -#include -#if defined(CONFIG_OF) && (LINUX_VERSION_CODE >= KERNEL_VERSION(3,14,0)) -#include -#else -#include -#endif - -int -qca_ar8327_sw_set_vlan(struct switch_dev *dev, - const struct switch_attr *attr, - struct switch_val *val); - -int -qca_ar8327_sw_get_vlan(struct switch_dev *dev, - const struct switch_attr *attr, - struct switch_val *val); - -int -qca_ar8327_sw_set_vid(struct switch_dev *dev, - const struct switch_attr *attr, - struct switch_val *val); - -int -qca_ar8327_sw_get_vid(struct switch_dev *dev, - const struct switch_attr *attr, - struct switch_val *val); - -int -qca_ar8327_sw_get_pvid(struct switch_dev *dev, int port, int *vlan); - -int -qca_ar8327_sw_set_pvid(struct switch_dev *dev, int port, int vlan); - -int -qca_ar8327_sw_get_ports(struct switch_dev *dev, struct switch_val *val); - -int -qca_ar8327_sw_set_ports(struct switch_dev *dev, struct switch_val *val); - -int -qca_ar8327_sw_hw_apply(struct switch_dev *dev); -#endif - -typedef struct { - fal_port_t port_id; /* port id */ - a_uint32_t vid; /* vlan id */ - a_bool_t is_wan_port; /* belong to wan port */ - a_bool_t valid; /* valid or not */ -} qca_lan_wan_port_info; - -typedef struct { - a_bool_t lan_only_mode; - qca_lan_wan_port_info v_port_info[SW_MAX_NR_PORT]; -} qca_lan_wan_cfg_t; - -sw_error_t -qca_lan_wan_cfg_set(a_uint32_t dev_id, qca_lan_wan_cfg_t *lan_wan_cfg); - -sw_error_t -qca_lan_wan_cfg_get(a_uint32_t dev_id, qca_lan_wan_cfg_t *lan_wan_cfg); - -#ifdef __cplusplus -} -#endif /* __cplusplus */ -#endif /* _REF_VLAN_H_ */ - diff --git a/feeds/ipq807x/qca-ssdk/src/include/ref/ref_vsi.h b/feeds/ipq807x/qca-ssdk/src/include/ref/ref_vsi.h deleted file mode 100755 index 0698f933f..000000000 --- a/feeds/ipq807x/qca-ssdk/src/include/ref/ref_vsi.h +++ /dev/null @@ -1,73 +0,0 @@ -/* - * Copyright (c) 2016-2018, The Linux Foundation. All rights reserved. - * Permission to use, copy, modify, and/or distribute this software for - * any purpose with or without fee is hereby granted, provided that the - * above copyright notice and this permission notice appear in all copies. - * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES - * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR - * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES - * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN - * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT - * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. - */ -#ifndef REF_VSI_H -#define REF_VSI_H -#include "sw.h" -#include "fal/fal_type.h" -#include "fal/fal_vsi.h" - - -#define REF_DEV_ID_CHECK(dev_id) \ -do { \ - if (dev_id >= SW_MAX_NR_DEV) \ - return SW_OUT_OF_RANGE; \ -} while (0) - -#define REF_PORT_ID_CHECK(port_id) \ -do { \ - if (port_id >= SW_MAX_NR_PORT) \ - return SW_OUT_OF_RANGE; \ -} while (0) - -#define REF_NULL_POINT_CHECK(point) \ -do { \ - if (point == NULL) \ - return SW_BAD_PTR; \ -} while (0) - - -enum{ - PPE_VSI_ADD, - PPE_VSI_DEL -}; -typedef struct REF_VLAN_INFO_T { - a_uint32_t stag_vid; - a_uint32_t ctag_vid; - a_uint32_t vport_bitmap; /*vlan based vsi*/ - struct REF_VLAN_INFO_T *pNext; -}ref_vlan_info_t; - -typedef struct{ - a_uint32_t valid; - a_uint32_t pport_bitmap; /*port based vsi*/ - ref_vlan_info_t *pHead; -}ref_vsi_t; - -#define PPE_VSI_PPORT_NR 7 -#define PPE_VSI_INVALID FAL_VSI_INVALID - -sw_error_t ppe_port_vlan_vsi_set(a_uint32_t dev_id, fal_port_t port_id, - a_uint32_t stag_vid, a_uint32_t ctag_vid, a_uint32_t vsi_id); -sw_error_t ppe_port_vlan_vsi_get(a_uint32_t dev_id, fal_port_t port_id, - a_uint32_t stag_vid, a_uint32_t ctag_vid, a_uint32_t *vsi_id); -sw_error_t ppe_port_vsi_set(a_uint32_t dev_id, fal_port_t port_id, - a_uint32_t vsi_id); -sw_error_t ppe_port_vsi_get(a_uint32_t dev_id, fal_port_t port_id, - a_uint32_t *vsi_id); -sw_error_t ppe_vsi_alloc(a_uint32_t dev_id, a_uint32_t *vsi); -sw_error_t ppe_vsi_free(a_uint32_t dev_id, a_uint32_t vsi_id); -sw_error_t ppe_vsi_tbl_dump(a_uint32_t dev_id); -sw_error_t ppe_vsi_init(a_uint32_t dev_id); -#endif - diff --git a/feeds/ipq807x/qca-ssdk/src/include/sal/os/aos_lock.h b/feeds/ipq807x/qca-ssdk/src/include/sal/os/aos_lock.h deleted file mode 100755 index 830151e95..000000000 --- a/feeds/ipq807x/qca-ssdk/src/include/sal/os/aos_lock.h +++ /dev/null @@ -1,47 +0,0 @@ -/* - * Copyright (c) 2012,2018, The Linux Foundation. All rights reserved. - * Permission to use, copy, modify, and/or distribute this software for - * any purpose with or without fee is hereby granted, provided that the - * above copyright notice and this permission notice appear in all copies. - * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES - * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR - * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES - * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN - * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT - * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. - */ - -#ifndef _AOS_LOCK_H -#define _AOS_LOCK_H - - -#include "aos_lock_pvt.h" - - -typedef aos_lock_pvt_t aos_lock_t; - - -#define aos_lock_init(lock) __aos_lock_init(lock) - - -#define aos_lock(lock) __aos_lock(lock) - - -#define aos_unlock(lock) __aos_unlock(lock) - -#define aos_lock_bh(lock) __aos_lock_bh(lock) - -#define aos_unlock_bh(lock) __aos_unlock_bh(lock) - - -#define aos_irq_save(flags) __aos_irq_save(flags) - - -#define aos_irq_restore(flags) __aos_irq_restore(flags) - - -#define aos_default_unlock __aos_default_unlock - - -#endif diff --git a/feeds/ipq807x/qca-ssdk/src/include/sal/os/aos_mem.h b/feeds/ipq807x/qca-ssdk/src/include/sal/os/aos_mem.h deleted file mode 100755 index b9365b955..000000000 --- a/feeds/ipq807x/qca-ssdk/src/include/sal/os/aos_mem.h +++ /dev/null @@ -1,112 +0,0 @@ -/* - * Copyright (c) 2012,2018, The Linux Foundation. All rights reserved. - * Permission to use, copy, modify, and/or distribute this software for - * any purpose with or without fee is hereby granted, provided that the - * above copyright notice and this permission notice appear in all copies. - * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES - * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR - * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES - * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN - * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT - * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. - */ - -#ifndef _AOS_MEM_H -#define _AOS_MEM_H - -#include "aos_types.h" -#include "aos_mem_pvt.h" - -/** - * @g aos_mem mem - * @{ - * - * @ig shim_ext - */ - -/** - * @brief Allocate a memory buffer. Note it's a non-blocking call. - * This call can block. - * - * @param[in] size buffer size - * - * @return Buffer pointer or NULL if there's not enough memory. - */ -static inline void * -aos_mem_alloc(aos_size_t size) -{ - return __aos_mem_alloc(size); -} - -/** - * @brief Free malloc'ed buffer - * - * @param[in] buf buffer pointer allocated by aos_alloc() - * @param[in] size buffer size - */ -static inline void -aos_mem_free(void *buf) -{ - __aos_mem_free(buf); -} - -/** - * @brief Move a memory buffer - * - * @param[in] dst destination address - * @param[in] src source address - * @param[in] size buffer size - */ -static inline void -aos_mem_copy(void *dst, void *src, aos_size_t size) -{ - __aos_mem_copy(dst, src, size); -} - -/** - * @brief Fill a memory buffer - * - * @param[in] buf buffer to be filled - * @param[in] b byte to fill - * @param[in] size buffer size - */ -static inline void -aos_mem_set(void *buf, a_uint8_t b, aos_size_t size) -{ - __aos_mem_set(buf, b, size); -} - -/** - * @brief Zero a memory buffer - * - * @param[in] buf buffer to be zeroed - * @param[in] size buffer size - */ -static inline void -aos_mem_zero(void *buf, aos_size_t size) -{ - __aos_mem_zero(buf, size); -} - -/** - * @brief Compare two memory buffers - * - * @param[in] buf1 first buffer - * @param[in] buf2 second buffer - * @param[in] size buffer size - * - * @retval 0 equal - * @retval 1 not equal - */ -static inline int -aos_mem_cmp(void *buf1, void *buf2, aos_size_t size) -{ - return __aos_mem_cmp(buf1, buf2, size); -} - -/** - * @} - */ - -#endif diff --git a/feeds/ipq807x/qca-ssdk/src/include/sal/os/aos_timer.h b/feeds/ipq807x/qca-ssdk/src/include/sal/os/aos_timer.h deleted file mode 100755 index 3b4161b9b..000000000 --- a/feeds/ipq807x/qca-ssdk/src/include/sal/os/aos_timer.h +++ /dev/null @@ -1,46 +0,0 @@ -/* - * Copyright (c) 2012,2018, The Linux Foundation. All rights reserved. - * Permission to use, copy, modify, and/or distribute this software for - * any purpose with or without fee is hereby granted, provided that the - * above copyright notice and this permission notice appear in all copies. - * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES - * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR - * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES - * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN - * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT - * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. - */ - - -#ifndef _AOS_TIMER_H -#define _AOS_TIMER_H - -#include "aos_types.h" -#include "aos_timer_pvt.h" - - -typedef __aos_timer_t aos_timer_t; - - -/* - * Delay in microseconds - */ -static inline void -aos_udelay(int usecs) -{ - return __aos_udelay(usecs); -} - -/* - * Delay in milliseconds. - */ -static inline void -aos_mdelay(int msecs) -{ - return __aos_mdelay(msecs); -} - - -#endif - diff --git a/feeds/ipq807x/qca-ssdk/src/include/sal/os/aos_types.h b/feeds/ipq807x/qca-ssdk/src/include/sal/os/aos_types.h deleted file mode 100755 index c26fb1805..000000000 --- a/feeds/ipq807x/qca-ssdk/src/include/sal/os/aos_types.h +++ /dev/null @@ -1,180 +0,0 @@ -/* - * Copyright (c) 2012,2018, The Linux Foundation. All rights reserved. - * Permission to use, copy, modify, and/or distribute this software for - * any purpose with or without fee is hereby granted, provided that the - * above copyright notice and this permission notice appear in all copies. - * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES - * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR - * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES - * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN - * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT - * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. - */ - -#ifndef _AOS_TYPES_H -#define _AOS_TYPES_H - -#include "aos_types_pvt.h" - -#ifndef NULL -#define NULL 0 -#endif - -/** - * @g aos_types types - * @{ - * - * @ig shim_ext - */ -/* - *@ basic data types. - */ -typedef enum -{ - A_FALSE, - A_TRUE -} a_bool_t; - -typedef __a_uint8_t a_uint8_t; -typedef __a_int8_t a_int8_t; -typedef __a_uint16_t a_uint16_t; -typedef __a_int16_t a_int16_t; -typedef __a_uint32_t a_uint32_t; -typedef __a_int32_t a_int32_t; -typedef __a_uint64_t a_uint64_t; -typedef __a_int64_t a_int64_t; -typedef unsigned long a_ulong_t; - - -typedef void * acore_t; - -/** - * @brief Platform/bus generic handle. Used for bus specific functions. - */ -typedef __aos_device_t aos_device_t; - -/** - * @brief size of an object - */ -typedef __aos_size_t aos_size_t; - -/** - * @brief Generic status to be used by acore. - */ -typedef enum -{ - A_STATUS_OK, - A_STATUS_FAILED, - A_STATUS_ENOENT, - A_STATUS_ENOMEM, - A_STATUS_EINVAL, - A_STATUS_EINPROGRESS, - A_STATUS_ENOTSUPP, - A_STATUS_EBUSY, -} a_status_t; - -/* - * An ecore needs to provide a table of all pci device/vendor id's it - * supports - * - * This table should be terminated by a NULL entry , i.e. {0} - */ -typedef struct -{ - a_uint32_t vendor; - a_uint32_t device; - a_uint32_t subvendor; - a_uint32_t subdevice; -} aos_pci_dev_id_t; - -#define AOS_PCI_ANY_ID (~0) - -/* - * Typically core's can use this macro to create a table of various device - * ID's - */ -#define AOS_PCI_DEVICE(_vendor, _device) \ - (_vendor), (_device), AOS_PCI_ANY_ID, AOS_PCI_ANY_ID - - -typedef __aos_iomem_t aos_iomem_t; -/* - * These define the hw resources the OS has allocated for the device - * Note that start defines a mapped area. - */ -typedef enum -{ - AOS_RESOURCE_TYPE_MEM, - AOS_RESOURCE_TYPE_IO, -} aos_resource_type_t; - -typedef struct -{ - a_uint32_t start; - a_uint32_t end; - aos_resource_type_t type; -} aos_resource_t; - -#define AOS_DEV_ID_TABLE_MAX 256 - -typedef union -{ - aos_pci_dev_id_t *pci; - void *raw; -} aos_bus_reg_data_t; - -typedef void *aos_attach_data_t; - -#define AOS_REGIONS_MAX 5 - -typedef enum -{ - AOS_BUS_TYPE_PCI = 1, - AOS_BUS_TYPE_GENERIC, -} aos_bus_type_t; - -typedef enum -{ - AOS_IRQ_NONE, - AOS_IRQ_HANDLED, -} aos_irq_resp_t; - -typedef enum -{ - AOS_DMA_MASK_32BIT, - AOS_DMA_MASK_64BIT, -} aos_dma_mask_t; - - -/** - * @brief DMA directions - */ -typedef enum -{ - AOS_DMA_TO_DEVICE = 0, /**< Data is transfered from device to memory */ - AOS_DMA_FROM_DEVICE, /**< Data is transfered from memory to device */ -} aos_dma_dir_t; - -/* - * Protoypes shared between public and private headers - */ - - -/* - * work queue(kernel thread) function callback - */ -typedef void (*aos_work_func_t)(void *); - -/** - * @brief Prototype of the critical region function that is to be - * executed with spinlock held and interrupt disalbed - */ -typedef a_bool_t (*aos_irqlocked_func_t)(void *); - -/** - * @brief Prototype of timer function - */ -typedef void (*aos_timer_func_t)(void *); - -#endif diff --git a/feeds/ipq807x/qca-ssdk/src/include/sal/os/linux/aos_lock_pvt.h b/feeds/ipq807x/qca-ssdk/src/include/sal/os/linux/aos_lock_pvt.h deleted file mode 100755 index fe220abd3..000000000 --- a/feeds/ipq807x/qca-ssdk/src/include/sal/os/linux/aos_lock_pvt.h +++ /dev/null @@ -1,47 +0,0 @@ -/* - * Copyright (c) 2012, The Linux Foundation. All rights reserved. - * Permission to use, copy, modify, and/or distribute this software for - * any purpose with or without fee is hereby granted, provided that the - * above copyright notice and this permission notice appear in all copies. - * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES - * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR - * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES - * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN - * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT - * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. - */ - -#ifndef _AOS_LOCK_PVT_H -#define _AOS_LOCK_PVT_H - - -#include -#include - - -typedef spinlock_t aos_lock_pvt_t; - - -#define __aos_lock_init(lock) spin_lock_init(lock) - - -#define __aos_lock(lock) spin_lock(lock) - - -#define __aos_unlock(lock) spin_unlock(lock) - -#define __aos_lock_bh(lock) spin_lock_bh(lock) - -#define __aos_unlock_bh(lock) spin_unlock_bh(lock) - -#define __aos_irq_save(flags) local_irq_save(flags) - -#define __aos_irq_restore(flags) local_irq_restore(flags) - -#ifndef KVER32 -#define __aos_default_unlock SPIN_LOCK_UNLOCKED -#endif - -#endif /*_AOS_LOCK_PVT_H*/ - diff --git a/feeds/ipq807x/qca-ssdk/src/include/sal/os/linux/aos_mem_pvt.h b/feeds/ipq807x/qca-ssdk/src/include/sal/os/linux/aos_mem_pvt.h deleted file mode 100755 index f81e23c50..000000000 --- a/feeds/ipq807x/qca-ssdk/src/include/sal/os/linux/aos_mem_pvt.h +++ /dev/null @@ -1,60 +0,0 @@ -/* - * Copyright (c) 2012, The Linux Foundation. All rights reserved. - * Permission to use, copy, modify, and/or distribute this software for - * any purpose with or without fee is hereby granted, provided that the - * above copyright notice and this permission notice appear in all copies. - * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES - * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR - * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES - * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN - * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT - * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. - */ - -#ifndef _AOS_MEM_PVT_H -#define _AOS_MEM_PVT_H - -#include - -static inline void *__aos_mem_alloc(aos_size_t size) -{ - return (kmalloc(size, GFP_KERNEL | __GFP_ZERO)); -} - -static inline void __aos_mem_free(void *buf) -{ - kfree(buf); -} - -/* move a memory buffer */ -static inline void -__aos_mem_copy(void *dst, void *src, aos_size_t size) -{ - memcpy(dst, src, size); -} - -/* set a memory buffer */ -static inline void -__aos_mem_set(void *buf, a_uint8_t b, aos_size_t size) -{ - memset(buf, b, size); -} - -/* zero a memory buffer */ -static inline void -__aos_mem_zero(void *buf, aos_size_t size) -{ - memset(buf, 0, size); -} - -/* compare two memory buffers */ -static inline int -__aos_mem_cmp(void *buf1, void *buf2, aos_size_t size) -{ - return (memcmp(buf1, buf2, size) == 0) ? 0 : 1; -} - - - -#endif /*_AOS_MEM_PVT_H*/ diff --git a/feeds/ipq807x/qca-ssdk/src/include/sal/os/linux/aos_timer_pvt.h b/feeds/ipq807x/qca-ssdk/src/include/sal/os/linux/aos_timer_pvt.h deleted file mode 100755 index 8bb49bc06..000000000 --- a/feeds/ipq807x/qca-ssdk/src/include/sal/os/linux/aos_timer_pvt.h +++ /dev/null @@ -1,43 +0,0 @@ -/* - * Copyright (c) 2012, The Linux Foundation. All rights reserved. - * Permission to use, copy, modify, and/or distribute this software for - * any purpose with or without fee is hereby granted, provided that the - * above copyright notice and this permission notice appear in all copies. - * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES - * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR - * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES - * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN - * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT - * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. - */ - -#ifndef _AOS_TIMER_PVT_H -#define _AOS_TIMER_PVT_H - -#ifdef KVER26 -#include -#endif -#include -#include - - -/* - * timer data type - */ -typedef struct timer_list __aos_timer_t; - - -static inline void -__aos_udelay(int usecs) -{ - udelay(usecs); -} - -static inline void -__aos_mdelay(int msecs) -{ - mdelay(msecs); -} - -#endif /*_AOS_TIMER_PVT_H*/ diff --git a/feeds/ipq807x/qca-ssdk/src/include/sal/os/linux/aos_types_pvt.h b/feeds/ipq807x/qca-ssdk/src/include/sal/os/linux/aos_types_pvt.h deleted file mode 100755 index 6d85ecb89..000000000 --- a/feeds/ipq807x/qca-ssdk/src/include/sal/os/linux/aos_types_pvt.h +++ /dev/null @@ -1,70 +0,0 @@ -/* - * Copyright (c) 2012, The Linux Foundation. All rights reserved. - * Permission to use, copy, modify, and/or distribute this software for - * any purpose with or without fee is hereby granted, provided that the - * above copyright notice and this permission notice appear in all copies. - * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES - * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR - * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES - * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN - * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT - * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. - */ - -#ifndef _AOS_PVTTYPES_H -#define _AOS_PVTTYPES_H - -#include -#include -#include -/* - * Private definitions of general data types - */ - -/* generic data types */ -typedef struct device * __aos_device_t; -typedef int __aos_size_t; - -#ifdef KVER26 -#ifdef LNX26_22 -typedef __u8 * __aos_iomem_t; -#else -typedef u8 __iomem * __aos_iomem_t; -#endif -#else /*Linux Kernel 2.4 */ -typedef u8 * __aos_iomem_t; -#endif - -#ifdef KVER32 -typedef u8 __iomem * __aos_iomem_t; -#endif - -#ifdef LNX26_22 /* > Linux 2.6.22 */ -typedef __u8 __a_uint8_t; -typedef __s8 __a_int8_t; -typedef __u16 __a_uint16_t; -typedef __s16 __a_int16_t; -typedef __u32 __a_uint32_t; -typedef __s32 __a_int32_t; -typedef __u64 __a_uint64_t; -typedef __s64 __a_int64_t; -#else -typedef u8 __a_uint8_t; -typedef s8 __a_int8_t; -typedef u16 __a_uint16_t; -typedef s16 __a_int16_t; -typedef u32 __a_uint32_t; -typedef s32 __a_int32_t; -typedef u64 __a_uint64_t; -typedef s64 __a_int64_t; -#endif - -#define aos_printk printk - -#define AUTO_UPDATE_PPPOE_INFO 1 -#if 0 -#undef AUTO_UPDATE_PPPOE_INFO -#endif - -#endif diff --git a/feeds/ipq807x/qca-ssdk/src/include/sal/sd/linux/uk_interface/sw_api_ks.h b/feeds/ipq807x/qca-ssdk/src/include/sal/sd/linux/uk_interface/sw_api_ks.h deleted file mode 100755 index fcc05521e..000000000 --- a/feeds/ipq807x/qca-ssdk/src/include/sal/sd/linux/uk_interface/sw_api_ks.h +++ /dev/null @@ -1,34 +0,0 @@ -/* - * Copyright (c) 2012,2018, The Linux Foundation. All rights reserved. - * Permission to use, copy, modify, and/or distribute this software for - * any purpose with or without fee is hereby granted, provided that the - * above copyright notice and this permission notice appear in all copies. - * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES - * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR - * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES - * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN - * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT - * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. - */ - - - -#ifndef _SW_API_KS_H -#define _SW_API_KS_H - -#ifdef __cplusplus -extern "C" { -#endif /* __cplusplus */ - -#include "sw.h" - - sw_error_t sw_uk_init(a_uint32_t nl_prot); - - sw_error_t sw_uk_cleanup(void); - -#ifdef __cplusplus -} -#endif /* __cplusplus */ - -#endif /* _SW_API_KS_H */ diff --git a/feeds/ipq807x/qca-ssdk/src/include/sal/sd/sd.h b/feeds/ipq807x/qca-ssdk/src/include/sal/sd/sd.h deleted file mode 100755 index ada85ac6a..000000000 --- a/feeds/ipq807x/qca-ssdk/src/include/sal/sd/sd.h +++ /dev/null @@ -1,77 +0,0 @@ -/* - * Copyright (c) 2012, 2017-2018, The Linux Foundation. All rights reserved. - * Permission to use, copy, modify, and/or distribute this software for - * any purpose with or without fee is hereby granted, provided that the - * above copyright notice and this permission notice appear in all copies. - * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES - * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR - * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES - * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN - * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT - * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. - */ - - -/*qca808x_start*/ -#ifndef _SD_H_ -#define _SD_H_ - -#ifdef __cplusplus -extern "C" { -#endif /* __cplusplus */ - - sw_error_t - sd_reg_mdio_set(a_uint32_t dev_id, a_uint32_t phy, a_uint32_t reg, - a_uint16_t data); - - sw_error_t - sd_reg_mdio_get(a_uint32_t dev_id, a_uint32_t phy, a_uint32_t reg, - a_uint16_t * data); - - sw_error_t - sd_reg_i2c_set(a_uint32_t dev_id, a_uint32_t phy, a_uint32_t reg, - a_uint16_t data); - - sw_error_t - sd_reg_i2c_get(a_uint32_t dev_id, a_uint32_t phy, a_uint32_t reg, - a_uint16_t * data); -/*qca808x_end*/ - sw_error_t - sd_reg_hdr_set(a_uint32_t dev_id, a_uint32_t reg_addr, - a_uint8_t * reg_data, a_uint32_t len); - - sw_error_t - sd_reg_hdr_get(a_uint32_t dev_id, a_uint32_t reg_addr, - a_uint8_t * reg_data, a_uint32_t len); - - sw_error_t - sd_reg_psgmii_set(a_uint32_t dev_id, a_uint32_t reg_addr, - a_uint8_t * reg_data, a_uint32_t len); - - sw_error_t - sd_reg_psgmii_get(a_uint32_t dev_id, a_uint32_t reg_addr, - a_uint8_t * reg_data, a_uint32_t len); - - sw_error_t - sd_reg_uniphy_set(a_uint32_t dev_id, a_uint32_t index, - a_uint32_t reg_addr, a_uint8_t * reg_data, a_uint32_t len); - - sw_error_t - sd_reg_uniphy_get(a_uint32_t dev_id, a_uint32_t index, - a_uint32_t reg_addr, a_uint8_t * reg_data, a_uint32_t len); - - void - sd_reg_mii_set(a_uint32_t dev_id, a_uint32_t reg, a_uint32_t val); - - a_uint32_t - sd_reg_mii_get(a_uint32_t dev_id, a_uint32_t reg); -/*qca808x_start*/ - sw_error_t sd_init(a_uint32_t dev_id, ssdk_init_cfg * cfg); - -#ifdef __cplusplus -} -#endif /* __cplusplus */ -#endif /* _SD_H_ */ -/*qca808x_end*/ - diff --git a/feeds/ipq807x/qca-ssdk/src/include/shell_lib/shell.h b/feeds/ipq807x/qca-ssdk/src/include/shell_lib/shell.h deleted file mode 100755 index 5bdcfb480..000000000 --- a/feeds/ipq807x/qca-ssdk/src/include/shell_lib/shell.h +++ /dev/null @@ -1,43 +0,0 @@ -/* - * Copyright (c) 2013, The Linux Foundation. All rights reserved. - * - * Permission to use, copy, modify, and/or distribute this software for any - * purpose with or without fee is hereby granted, provided that the above - * copyright notice and this permission notice appear in all copies. - * - * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES - * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR - * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES - * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN - * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF - * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. - */ - -#ifndef _SW_SHELL_H -#define _SW_SHELL_H - -#ifdef __cplusplus -extern "C" { -#endif - - -#include "sw.h" -#include "sw_api.h" -#include "ssdk_init.h" - - -#define IOCTL_BUF_SIZE 2048 -#define CMDSTR_BUF_SIZE 1024 -#define CMDSTR_ARGS_MAX 128 -#define dprintf - -int cmd_run_one(char *cmd_str); -extern void cmd_print(char *fmt, ...); -void cmd_print_error(sw_error_t rtn); - -#ifdef __cplusplus -} -#endif /* __cplusplus */ - -#endif /* _SW_SHELL_H */ diff --git a/feeds/ipq807x/qca-ssdk/src/include/shell_lib/shell_config.h b/feeds/ipq807x/qca-ssdk/src/include/shell_lib/shell_config.h deleted file mode 100755 index 173c75587..000000000 --- a/feeds/ipq807x/qca-ssdk/src/include/shell_lib/shell_config.h +++ /dev/null @@ -1,78 +0,0 @@ -/* - * Copyright (c) 2013, The Linux Foundation. All rights reserved. - * - * Permission to use, copy, modify, and/or distribute this software for any - * purpose with or without fee is hereby granted, provided that the above - * copyright notice and this permission notice appear in all copies. - * - * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES - * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR - * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES - * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN - * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF - * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. - */ - -#ifndef _SHELL_CONFIG_H_ -#define _SHELL_CONFIG_H_ - -#ifdef __cplusplus -extern "C" { -#endif - -#include "sw.h" -#include "sw_ioctl.h" -#include "sw_api.h" - -#define SW_CMD_SET_DEVID (SW_API_MAX + 1) -#define SW_CMD_VLAN_SHOW (SW_API_MAX + 2) -#define SW_CMD_FDB_SHOW (SW_API_MAX + 3) -#define SW_CMD_RESV_FDB_SHOW (SW_API_MAX + 4) -#define SW_CMD_HOST_SHOW (SW_API_MAX + 5) -#define SW_CMD_NAT_SHOW (SW_API_MAX + 6) -#define SW_CMD_NAPT_SHOW (SW_API_MAX + 7) -#define SW_CMD_INTFMAC_SHOW (SW_API_MAX + 8) -#define SW_CMD_PUBADDR_SHOW (SW_API_MAX + 9) -#define SW_CMD_FLOW_SHOW (SW_API_MAX + 10) -#define SW_CMD_MAX (SW_API_MAX + 11) - -#define MAX_SUB_CMD_DES_NUM 40 - - struct sub_cmd_des_t - { - char *sub_name; - char *sub_act; - int sub_api; - sw_error_t (*sub_func) (void); - }; - struct cmd_des_t - { - char *name; - struct sub_cmd_des_t *sub_cmd_des; - }; - extern struct cmd_des_t gcmd_des[]; - -#define GCMD_DES gcmd_des - -#define GCMD_NAME(cmd_nr) GCMD_DES[cmd_nr].name -#define GCMD_MEMO(cmd_nr) GCMD_DES[cmd_nr].memo - -#define GCMD_SUB_NAME(cmd_nr, sub_cmd_nr) GCMD_DES[cmd_nr].sub_cmd_des[sub_cmd_nr].sub_name -#define GCMD_SUB_ACT(cmd_nr, sub_cmd_nr) GCMD_DES[cmd_nr].sub_cmd_des[sub_cmd_nr].sub_act -#define GCMD_SUB_MEMO(cmd_nr, sub_cmd_nr) GCMD_DES[cmd_nr].sub_cmd_des[sub_cmd_nr].sub_memo -#define GCMD_SUB_USAGE(cmd_nr, sub_cmd_nr) GCMD_DES[cmd_nr].sub_cmd_des[sub_cmd_nr].sub_usage -#define GCMD_SUB_API(cmd_nr, sub_cmd_nr) GCMD_DES[cmd_nr].sub_cmd_des[sub_cmd_nr].sub_api -#define GCMD_SUB_FUNC(cmd_nr, sub_cmd_nr) GCMD_DES[cmd_nr].sub_cmd_des[sub_cmd_nr].sub_func - -#define GCMD_DESC_VALID(cmd_nr) GCMD_NAME(cmd_nr) -#define GCMD_SUB_DESC_VALID(cmd_nr, sub_cmd_nr) GCMD_SUB_API(cmd_nr, sub_cmd_nr) - - -#define GCMD_DESC_NO_MATCH 0xffffffff - -#ifdef __cplusplus -} -#endif /* __cplusplus */ - -#endif /* _SHELL_CONFIG_H_ */ diff --git a/feeds/ipq807x/qca-ssdk/src/include/shell_lib/shell_io.h b/feeds/ipq807x/qca-ssdk/src/include/shell_lib/shell_io.h deleted file mode 100644 index 7a8d3196b..000000000 --- a/feeds/ipq807x/qca-ssdk/src/include/shell_lib/shell_io.h +++ /dev/null @@ -1,484 +0,0 @@ -/* - * Copyright (c) 2013, 2015-2017, 2019, The Linux Foundation. All rights reserved. - * - * Permission to use, copy, modify, and/or distribute this software for any - * purpose with or without fee is hereby granted, provided that the above - * copyright notice and this permission notice appear in all copies. - * - * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES - * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR - * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES - * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN - * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF - * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. - */ - -#ifndef _SHELL_IO_H -#define _SHELL_IO_H - -#include "sw.h" -#include "sw_api.h" -#include "fal.h" - -#define SW_TYPE_DEF(type, parser, show) {type, parser, show} -typedef sw_error_t - (*param_check_t)(char *, a_uint32_t *, a_uint32_t); -typedef sw_error_t - (*param_check_range_t)(char *, a_uint32_t *, a_uint32_t, a_uint32_t); -typedef sw_error_t - (*param_check_boolean_t)(char *, a_bool_t, a_bool_t *, a_uint32_t); -typedef struct -{ - sw_data_type_e data_type; - param_check_t param_check; - void (*show_func) (void); -} sw_data_type_t; - -void set_talk_mode(int mode); -int get_talk_mode(void); -void set_full_cmdstrp(char **cmdstrp); -int get_jump(void); -sw_data_type_t * cmd_data_type_find(sw_data_type_e type); -void cmd_strtol(char *str, a_uint32_t * arg_val); -sw_error_t cmd_data_check_portmap(char *cmdstr, fal_pbmp_t * val, a_uint32_t size); -sw_error_t cmd_data_check_confirm(char *cmdstr, a_bool_t def, a_bool_t * val, a_uint32_t size); - -sw_error_t cmd_data_check_uint32(char *cmd_str, a_uint32_t * arg_val, - a_uint32_t size); -sw_error_t cmd_data_check_uint16(char *cmd_str, a_uint32_t * arg_val, - a_uint32_t size); -sw_error_t cmd_data_check_uint8(char *cmd_str, a_uint32_t * arg_val, - a_uint32_t size); -sw_error_t cmd_data_check_enable(char *cmd_str, a_uint32_t * arg_val, - a_uint32_t size); -sw_error_t cmd_data_check_pbmp(char *cmd_str, a_uint32_t * arg_val, - a_uint32_t size); -#ifdef IN_PORTCONTROL -sw_error_t cmd_data_check_duplex(char *cmd_str, a_uint32_t * arg_val, - a_uint32_t size); -sw_error_t cmd_data_check_speed(char *cmd_str, a_uint32_t * arg_val, - a_uint32_t size); -#ifndef IN_PORTCONTROL_MINI -sw_error_t -cmd_data_check_port_eee_config(char *cmd_str, void * val, a_uint32_t size); -sw_error_t -cmd_data_check_switch_port_loopback_config(char *cmd_str, void * val, - a_uint32_t size); -#endif -#endif -#ifdef IN_PORTVLAN -sw_error_t cmd_data_check_1qmode(char *cmd_str, a_uint32_t * arg_val, - a_uint32_t size); -sw_error_t cmd_data_check_egmode(char *cmd_str, a_uint32_t * arg_val, - a_uint32_t size); -#ifdef HPPE -sw_error_t -cmd_data_check_global_qinqmode(char *info, void *val, a_uint32_t size); -sw_error_t -cmd_data_check_port_qinqmode(char *info, void *val, a_uint32_t size); -sw_error_t -cmd_data_check_tpid(char *info, void *val, a_uint32_t size); -sw_error_t -cmd_data_check_ingress_filter(char *info, void *val, a_uint32_t size); -sw_error_t -cmd_data_check_port_vlan_direction(char *cmd_str, a_uint32_t * arg_val, a_uint32_t size); -sw_error_t -cmd_data_check_port_default_vid_en(char *info, void *val, a_uint32_t size); -sw_error_t -cmd_data_check_port_vlan_tag(char *info, void *val, a_uint32_t size); -sw_error_t -cmd_data_check_tag_propagation(char *info, void *val, a_uint32_t size); -sw_error_t -cmd_data_check_egress_mode(char *info, void *val, a_uint32_t size); -sw_error_t -cmd_data_check_port_vlan_translation_adv_rule(char *info, void *val, - a_uint32_t size); -sw_error_t -cmd_data_check_port_vlan_translation_adv_action(char *info, void *val, - a_uint32_t size); -#endif -#endif -#ifdef IN_PORTCONTROL -sw_error_t cmd_data_check_capable(char *cmd_str, a_uint32_t * arg_val, - a_uint32_t size); -#endif -#ifdef IN_FDB -sw_error_t cmd_data_check_fdbentry(char *cmdstr, void *val, a_uint32_t size); -#ifndef IN_FDB_MINI -sw_error_t cmd_data_check_maclimit_ctrl(char *info, void *val, a_uint32_t size); -#endif -#endif -sw_error_t cmd_data_check_macaddr(char *cmdstr, void *val, a_uint32_t size); -#ifdef IN_VLAN -sw_error_t cmd_data_check_vlan(char *cmdstr, fal_vlan_t * val, a_uint32_t size); -#endif -#ifdef IN_QOS -#ifndef IN_QOS_MINI -sw_error_t cmd_data_check_qos_sch(char *cmdstr, fal_sch_mode_t * val, - a_uint32_t size); -sw_error_t cmd_data_check_qos_pt(char *cmdstr, fal_qos_mode_t * val, - a_uint32_t size); -sw_error_t -cmd_data_check_port_group(char *cmd_str, void * val, a_uint32_t size); -sw_error_t -cmd_data_check_port_pri(char *cmd_str, void * val, a_uint32_t size); -sw_error_t -cmd_data_check_port_remark(char *cmd_str, void * val, a_uint32_t size); -sw_error_t -cmd_data_check_cosmap(char *cmd_str, void * val, a_uint32_t size); -sw_error_t -cmd_data_check_queue_scheduler(char *cmd_str, void * val, a_uint32_t size); -sw_error_t -cmd_data_check_ring_queue(char *cmd_str, void * val, a_uint32_t size); -#endif -#endif -#ifdef IN_RATE -sw_error_t cmd_data_check_storm(char *cmdstr, fal_storm_type_t * val, - a_uint32_t size); -#endif -#ifdef IN_STP -sw_error_t cmd_data_check_stp_state(char *cmdstr, fal_stp_state_t * val, - a_uint32_t size); -#endif -#ifdef IN_LEAKY -sw_error_t cmd_data_check_leaky(char *cmdstr, fal_leaky_ctrl_mode_t * val, - a_uint32_t size); -#endif -sw_error_t cmd_data_check_uinta(char *cmdstr, a_uint32_t * val, - a_uint32_t size); -sw_error_t cmd_data_check_maccmd(char *cmdstr, fal_fwd_cmd_t * val, - a_uint32_t size); -#ifdef IN_IP -#ifndef IN_IP_MINI -sw_error_t cmd_data_check_flowcmd(char *cmdstr, fal_default_flow_cmd_t * val, - a_uint32_t size); -sw_error_t cmd_data_check_flowtype(char *cmdstr, fal_flow_type_t * val, - a_uint32_t size); -#endif -#endif -#ifdef IN_LED -sw_error_t cmd_data_check_ledpattern(char *info, void * val, a_uint32_t size); -#endif -#ifdef IN_PORTVLAN -sw_error_t -cmd_data_check_invlan_mode(char *cmd_str, a_uint32_t * arg_val, a_uint32_t size); -sw_error_t -cmd_data_check_vlan_propagation(char *cmd_str, a_uint32_t * arg_val, a_uint32_t size); -#ifndef IN_PORTVLAN_MINI -sw_error_t -cmd_data_check_vlan_translation(char *info, fal_vlan_trans_entry_t *val, a_uint32_t size); -#endif -sw_error_t -cmd_data_check_qinq_mode(char *cmd_str, a_uint32_t * arg_val, a_uint32_t size); -sw_error_t -cmd_data_check_qinq_role(char *cmd_str, a_uint32_t * arg_val, a_uint32_t size); -#endif -#ifdef IN_PORTCONTROL -sw_error_t -cmd_data_check_hdrmode(char *cmd_str, a_uint32_t * arg_val, a_uint32_t size); -#endif -#ifdef IN_FDB -sw_error_t -cmd_data_check_fdboperation(char *cmd_str, void * val, a_uint32_t size); -#endif -#ifdef IN_PPPOE -sw_error_t -cmd_data_check_pppoe(char *cmd_str, void * val, a_uint32_t size); -sw_error_t -cmd_data_check_pppoe_less(char *cmd_str, void * val, a_uint32_t size); -#endif -#if defined(IN_IP) || defined(IN_NAT) -sw_error_t -cmd_data_check_host_entry(char *cmd_str, void * val, a_uint32_t size); -sw_error_t -cmd_data_check_arp_learn_mode(char *cmd_str, fal_arp_learn_mode_t * arg_val, - a_uint32_t size); - -sw_error_t -cmd_data_check_ip_guard_mode(char *cmd_str, fal_source_guard_mode_t * arg_val, a_uint32_t size); - - -sw_error_t -cmd_data_check_nat_entry(char *cmd_str, void * val, a_uint32_t size); - - -sw_error_t -cmd_data_check_napt_entry(char *cmd_str, void * val, a_uint32_t size); - -sw_error_t -cmd_data_check_flow_entry(char *cmd_str, void * val, a_uint32_t size); - -sw_error_t -cmd_data_check_napt_mode(char *cmd_str, fal_napt_mode_t * arg_val, a_uint32_t size); - - -sw_error_t -cmd_data_check_intf_mac_entry(char *cmd_str, void * val, a_uint32_t size); - -sw_error_t -cmd_data_check_pub_addr_entry(char *cmd_str, void * val, a_uint32_t size); -#endif - -sw_error_t -cmd_data_check_ip4addr(char *cmdstr, void * val, a_uint32_t size); - -sw_error_t -cmd_data_check_ip6addr(char *cmdstr, void * val, a_uint32_t size); - - -sw_error_t -cmd_data_check_egress_shaper(char *cmd_str, void * val, a_uint32_t size); - -#ifdef IN_RATE -sw_error_t -cmd_data_check_port_policer(char *cmd_str, void * val, a_uint32_t size); - -sw_error_t -cmd_data_check_policer_timesslot(char *cmd_str, a_uint32_t * val, a_uint32_t size); - -sw_error_t -cmd_data_check_acl_policer(char *cmd_str, void * val, a_uint32_t size); -#endif -#ifdef IN_FDB -#ifndef IN_FDB_MINI -sw_error_t -cmd_data_check_fdb_smode(char *cmd_str, a_uint32_t * arg_val, a_uint32_t size); -#endif -#endif -#ifdef IN_IGMP -sw_error_t -cmd_data_check_multi(char *info, void *val, a_uint32_t size); -#endif -#ifdef IN_SEC -sw_error_t -cmd_data_check_sec_mac(char *cmd_str, a_uint32_t * arg_val, a_uint32_t size); - -sw_error_t -cmd_data_check_sec_ip(char *cmd_str, a_uint32_t * arg_val, a_uint32_t size); - -sw_error_t -cmd_data_check_sec_ip4(char *cmd_str, a_uint32_t * arg_val, a_uint32_t size); - -sw_error_t -cmd_data_check_sec_ip6(char *cmd_str, a_uint32_t * arg_val, a_uint32_t size); - -sw_error_t -cmd_data_check_sec_tcp(char *cmd_str, a_uint32_t * arg_val, a_uint32_t size); - -sw_error_t -cmd_data_check_sec_udp(char *cmd_str, a_uint32_t * arg_val, a_uint32_t size); - -sw_error_t -cmd_data_check_sec_icmp4(char *cmd_str, a_uint32_t * arg_val, a_uint32_t size); - -sw_error_t -cmd_data_check_sec_icmp6(char *cmd_str, a_uint32_t * arg_val, a_uint32_t size); -#ifdef HPPE -sw_error_t -cmd_data_check_l3_parser(char *cmd_str, void * val, a_uint32_t size); - -sw_error_t -cmd_data_check_l4_parser(char *cmd_str, void * val, a_uint32_t size); - -sw_error_t -cmd_data_check_exp_ctrl(char *cmd_str, void * val, a_uint32_t size); -#endif -#endif -#ifdef IN_COSMAP -#ifndef IN_COSMAP_MINI -sw_error_t -cmd_data_check_remark_entry(char *info, void *val, a_uint32_t size); -#endif -#endif -#ifdef IN_IP -#ifndef IN_IP_MINI -sw_error_t -cmd_data_check_default_route_entry(char *cmd_str, void * val, a_uint32_t size); - -sw_error_t -cmd_data_check_host_route_entry(char *cmd_str, void * val, a_uint32_t size); - -sw_error_t -cmd_data_check_ip4_rfs_entry(char *cmd_str, void * val, a_uint32_t size); -sw_error_t -cmd_data_check_ip6_rfs_entry(char *cmd_str, void * val, a_uint32_t size); -sw_error_t -cmd_data_check_arp_sg(char *cmd_str, void * val, a_uint32_t size); -sw_error_t -cmd_data_check_network_route(char *cmd_str, void * val, a_uint32_t size); -sw_error_t -cmd_data_check_intf(char *cmd_str, void * val, a_uint32_t size); -sw_error_t -cmd_data_check_vsi_intf(char *cmd_str, void * val, a_uint32_t size); -sw_error_t -cmd_data_check_nexthop(char *cmd_str, void * val, a_uint32_t size); -sw_error_t -cmd_data_check_ip_sg(char *cmd_str, void * val, a_uint32_t size); -sw_error_t -cmd_data_check_ip_pub(char *cmd_str, void * val, a_uint32_t size); -sw_error_t -cmd_data_check_ip_portmac(char *cmd_str, void * val, a_uint32_t size); -sw_error_t -cmd_data_check_ip_mcmode(char *cmd_str, void * val, a_uint32_t size); -sw_error_t -cmd_data_check_ip_global(char *cmd_str, void * val, a_uint32_t size); -#endif -#endif -#if defined(IN_IP) || defined(IN_NAT) -sw_error_t -cmd_data_check_flow_cookie(char *cmd_str, void * val, a_uint32_t size); - -sw_error_t -cmd_data_check_flow_rfs(char *cmd_str, void * val, a_uint32_t size); -#endif -#ifdef IN_PORTCONTROL -#ifndef IN_PORTCONTROL_MINI -sw_error_t -cmd_data_check_crossover_mode(char *cmd_str, a_uint32_t * arg_val, a_uint32_t size); - -sw_error_t -cmd_data_check_crossover_status(char *cmd_str, a_uint32_t * arg_val, a_uint32_t size); - -sw_error_t -cmd_data_check_prefer_medium(char *cmd_str, a_uint32_t * arg_val, a_uint32_t size); - -sw_error_t -cmd_data_check_fiber_mode(char *cmd_str, a_uint32_t * arg_val, a_uint32_t size); - -sw_error_t -cmd_data_check_src_filter_config(char *cmd_str, a_uint32_t * arg_val, a_uint32_t size); - -sw_error_t -cmd_data_check_mtu_entry(char *cmd_str, void * val, a_uint32_t size); - -sw_error_t -cmd_data_check_mru_entry(char *cmd_str, void * val, a_uint32_t size); - - -#endif -#endif -#ifdef IN_INTERFACECONTROL -sw_error_t -cmd_data_check_interface_mode(char *cmd_str, a_uint32_t * arg_val, a_uint32_t size); -#endif -#ifdef IN_VSI -sw_error_t -cmd_data_check_newadr_lrn(char *cmd_str, void * val, a_uint32_t size); - -sw_error_t -cmd_data_check_stamove(char *cmd_str, void * val, a_uint32_t size); - -sw_error_t -cmd_data_check_vsi_member(char *cmd_str, void * val, a_uint32_t size); - -#endif -#ifdef IN_BM -sw_error_t -cmd_data_check_bm_dynamic_thresh(char *cmd_str, void * val, a_uint32_t size); -sw_error_t -cmd_data_check_bm_static_thresh(char *cmd_str, void * val, a_uint32_t size); -#endif -#ifdef IN_QM -sw_error_t -cmd_data_check_u_qmap(char *cmd_str, void * val, a_uint32_t size); - -sw_error_t -cmd_data_check_ac_static_thresh(char *cmd_str, void * val, a_uint32_t size); - -sw_error_t -cmd_data_check_ac_dynamic_thresh(char *cmd_str, void * val, a_uint32_t size); - -sw_error_t -cmd_data_check_ac_group_buff(char *cmd_str, void * val, a_uint32_t size); - -sw_error_t -cmd_data_check_ac_ctrl(char *cmd_str, void * val, a_uint32_t size); - -sw_error_t -cmd_data_check_ac_obj(char *cmd_str, void * val, a_uint32_t size); - -#endif -#ifdef IN_FLOW -sw_error_t -cmd_data_check_flow_age(char *cmd_str, void * val, a_uint32_t size); -sw_error_t -cmd_data_check_flow_ctrl(char *cmd_str, void * val, a_uint32_t size); -sw_error_t -cmd_data_check_flow(char *cmd_str, void * val, a_uint32_t size); -sw_error_t -cmd_data_check_flow_global(char *cmd_str, void * val, a_uint32_t size); -sw_error_t -cmd_data_check_flow_host(char *cmd_str, void * val, a_uint32_t size); -#endif - -#ifdef IN_POLICER -sw_error_t -cmd_data_check_port_policer_config(char *cmd_str, void * val, a_uint32_t size); - -sw_error_t -cmd_data_check_policer_cmd_config(char *cmd_str, void * val, a_uint32_t size); - -sw_error_t -cmd_data_check_acl_policer_config(char *cmd_str, void * val, a_uint32_t size); - -#endif - -#ifdef IN_SHAPER -sw_error_t -cmd_data_check_port_shaper_token_config(char *cmd_str, void * val, a_uint32_t size); - -sw_error_t -cmd_data_check_shaper_token_config(char *cmd_str, void * val, a_uint32_t size); - -sw_error_t -cmd_data_check_port_shaper_config(char *cmd_str, void * val, a_uint32_t size); - -sw_error_t -cmd_data_check_shaper_config(char *cmd_str, void * val, a_uint32_t size); - -#endif - -#ifdef IN_SERVCODE -sw_error_t -cmd_data_check_servcode_config(char *info, fal_servcode_config_t *val, a_uint32_t size); -#endif - -#ifdef IN_RSS_HASH -sw_error_t -cmd_data_check_rss_hash_mode(char *cmd_str, a_uint32_t * arg_val, a_uint32_t size); -sw_error_t -cmd_data_check_rss_hash_config(char *info, fal_rss_hash_config_t *val, a_uint32_t size); -#endif - -#ifdef IN_MIRROR -sw_error_t -cmd_data_check_mirr_analy_cfg(char *info, void *val, a_uint32_t size); -sw_error_t -cmd_data_check_mirr_direction(char *cmd_str, a_uint32_t * arg_val, a_uint32_t size); -#endif -sw_error_t -cmd_data_check_integer(char *cmd_str, a_uint32_t * arg_val, a_uint32_t max_val, a_uint32_t min_val); -#ifdef IN_CTRLPKT -sw_error_t -cmd_data_check_ctrlpkt_appprofile(char *info, void *val, a_uint32_t size); -#endif -#ifdef IN_ACL -sw_error_t -cmd_data_check_ruletype(char *cmd_str, fal_acl_rule_type_t * arg_val, a_uint32_t size); -sw_error_t -cmd_data_check_udf_pkt_type(char *cmdstr, fal_acl_udf_pkt_type_t * arg_val, a_uint32_t size); -sw_error_t -cmd_data_check_udf_type(char *cmdstr, fal_acl_udf_type_t * arg_val, a_uint32_t size); -sw_error_t -cmd_data_check_udf_element(char *cmdstr, a_uint8_t * val, a_uint32_t * len); -sw_error_t -cmd_data_check_fieldop(char *cmdstr, fal_acl_field_op_t def, fal_acl_field_op_t * val); - -#endif -sw_error_t -cmd_data_check_module(char *cmd_str, a_uint32_t * arg_val, a_uint32_t size); -sw_error_t -cmd_data_check_func_ctrl(char *cmd_str, void * val, a_uint32_t size); -#endif - diff --git a/feeds/ipq807x/qca-ssdk/src/include/shell_lib/shell_sw.h b/feeds/ipq807x/qca-ssdk/src/include/shell_lib/shell_sw.h deleted file mode 100755 index 80d3acb32..000000000 --- a/feeds/ipq807x/qca-ssdk/src/include/shell_lib/shell_sw.h +++ /dev/null @@ -1,32 +0,0 @@ -/* - * Copyright (c) 2013, 2017, The Linux Foundation. All rights reserved. - * - * Permission to use, copy, modify, and/or distribute this software for any - * purpose with or without fee is hereby granted, provided that the above - * copyright notice and this permission notice appear in all copies. - * - * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES - * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR - * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES - * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN - * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF - * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. - */ - -#ifndef _SHELL_SW_H_ -#define _SHELL_SW_H_ - -#ifdef __cplusplus -extern "C" { -#endif - - int get_devid(void); - sw_error_t cmd_set_devid(a_uint32_t *arg_val); - sw_error_t uci_set_devid(a_uint32_t dev_id); - -#ifdef __cplusplus -} -#endif /* __cplusplus */ - -#endif /* _SHELL_SW_H_ */ diff --git a/feeds/ipq807x/qca-ssdk/src/ko_Makefile b/feeds/ipq807x/qca-ssdk/src/ko_Makefile deleted file mode 100755 index 5cfb1f37d..000000000 --- a/feeds/ipq807x/qca-ssdk/src/ko_Makefile +++ /dev/null @@ -1,3 +0,0 @@ -obj-m := qca-ssdk.o -OBJ_LIST:=$(notdir $(wildcard $(PRJ_PATH)/temp/*.o)) -qca-ssdk-objs := $(OBJ_LIST) diff --git a/feeds/ipq807x/qca-ssdk/src/make/.build_number b/feeds/ipq807x/qca-ssdk/src/make/.build_number deleted file mode 100644 index 0cfbf0888..000000000 --- a/feeds/ipq807x/qca-ssdk/src/make/.build_number +++ /dev/null @@ -1 +0,0 @@ -2 diff --git a/feeds/ipq807x/qca-ssdk/src/make/components.mk b/feeds/ipq807x/qca-ssdk/src/make/components.mk deleted file mode 100755 index 01970652a..000000000 --- a/feeds/ipq807x/qca-ssdk/src/make/components.mk +++ /dev/null @@ -1,36 +0,0 @@ - -ifeq (linux, $(OS)) - ifeq (KSLIB, $(MODULE_TYPE)) - ifeq (TRUE, $(KERNEL_MODE)) - COMPONENTS = HSL SAL INIT UTIL REF SHELIB - ifeq (TRUE, $(FAL)) - COMPONENTS += FAL ADPT - endif - else - COMPONENTS = HSL SAL INIT REF - endif - - ifeq (TRUE, $(UK_IF)) - COMPONENTS += API - endif - endif - - ifeq (USLIB, $(MODULE_TYPE)) - ifneq (TRUE, $(KERNEL_MODE)) - COMPONENTS = HSL SAL INIT UTIL REF - ifeq (TRUE, $(FAL)) - COMPONENTS += FAL ADPT - endif - else - COMPONENTS = UK_IF SAL - endif - - ifeq (TRUE, $(UK_IF)) - COMPONENTS += API - endif - endif - - ifeq (SHELL, $(MODULE_TYPE)) - COMPONENTS = SHELL - endif -endif diff --git a/feeds/ipq807x/qca-ssdk/src/make/config.mk b/feeds/ipq807x/qca-ssdk/src/make/config.mk deleted file mode 100755 index e357259a1..000000000 --- a/feeds/ipq807x/qca-ssdk/src/make/config.mk +++ /dev/null @@ -1,119 +0,0 @@ - -include $(PRJ_PATH)/config --include $(SYS_PATH)/include/config/auto.conf - -ifndef SYS_PATH - $(error SYS_PATH isn't defined!) -endif - -ifndef TOOL_PATH - $(error TOOL_PATH isn't defined!) -endif - -#define cpu type such as PPC MIPS ARM X86 -ifndef CPU - CPU=mips -endif - -#define os type such as linux netbsd vxworks -ifndef OS - OS=linux -endif - -ifndef OS_VER - OS_VER=2_6 -endif - -#support chip type such as ATHENA GARUDA -ifndef CHIP_TYPE - SUPPORT_CHIP = GARUDA -else - ifeq (GARUDA, $(CHIP_TYPE)) - SUPPORT_CHIP = GARUDA - endif - - ifeq (ATHENA, $(CHIP_TYPE)) - SUPPORT_CHIP = ATHENA - endif - - ifeq (SHIVA, $(CHIP_TYPE)) - SUPPORT_CHIP = SHIVA - endif - - ifeq (HORUS, $(CHIP_TYPE)) - SUPPORT_CHIP = HORUS - endif - - ifeq (ISIS, $(CHIP_TYPE)) - SUPPORT_CHIP = ISIS - endif - - ifeq (ISISC, $(CHIP_TYPE)) - SUPPORT_CHIP = ISISC - endif - - ifeq (DESS, $(CHIP_TYPE)) - SUPPORT_CHIP = DESS - endif - - ifeq (HPPE, $(CHIP_TYPE)) - SUPPORT_CHIP = HPPE - endif - - ifeq (CPPE, $(CHIP_TYPE)) - SUPPORT_CHIP = HPPE CPPE - endif - - ifeq (MP, $(CHIP_TYPE)) - SUPPORT_CHIP = SCOMPHY MP - endif - - ifeq ($(ISISC_ENABLE), enable) - SUPPORT_CHIP += ISISC - endif - - ifeq (ALL_CHIP, $(CHIP_TYPE)) - ifneq (TRUE, $(FAL)) - $(error FAL must be TRUE when CHIP_TYPE is defined as ALL_CHIP!) - endif - SUPPORT_CHIP = ISIS ISISC SHIVA DESS HPPE CPPE SCOMPHY MP - endif - - ifeq (NONHK_CHIP, $(CHIP_TYPE)) - ifneq (TRUE, $(FAL)) - $(error FAL must be TRUE when CHIP_TYPE is defined as ALL_CHIP!) - endif - SUPPORT_CHIP = ISIS ISISC SHIVA DESS - endif - - ifndef SUPPORT_CHIP - $(error defined CHIP_TYPE isn't supported!) - endif -endif - -#define compile tool prefix -ifndef TOOLPREFIX - TOOLPREFIX=$(CPU)-$(OS)-uclibc- -endif - -DEBUG_ON=FALSE -OPT_FLAG= -LD_FLAG= - -SHELLOBJ=ssdk_sh -US_MOD=ssdk_us -KS_MOD=ssdk_ks - -ifeq (TRUE, $(KERNEL_MODE)) - RUNMODE=km -else - RUNMODE=um -endif - -BLD_DIR=$(PRJ_PATH)/build/$(OS) -BIN_DIR=$(PRJ_PATH)/build/bin - -VER=2.0.0 -BUILD_NUMBER=$(shell cat $(PRJ_PATH)/make/.build_number) -VERSION=$(VER).$(BUILD_NUMBER) -BUILD_DATE=$(shell date -u +%F-%T) diff --git a/feeds/ipq807x/qca-ssdk/src/make/defs.mk b/feeds/ipq807x/qca-ssdk/src/make/defs.mk deleted file mode 100755 index 7d1c75bb9..000000000 --- a/feeds/ipq807x/qca-ssdk/src/make/defs.mk +++ /dev/null @@ -1,28 +0,0 @@ -DST_DIR=$(BLD_DIR)/$(MODULE_TYPE) - -SUB_DIR=$(patsubst %/, %, $(dir $(wildcard ./*/Makefile))) - -ifeq (,$(findstring $(LIB), $(COMPONENTS))) - SRC_LIST= -endif - -SRC_FILE=$(addprefix $(PRJ_PATH)/$(LOC_DIR)/, $(SRC_LIST)) - -OBJ_LIST=$(SRC_LIST:.c=.o) -OBJ_FILE=$(addprefix $(DST_DIR)/, $(OBJ_LIST)) - -DEP_LIST=$(SRC_LIST:.c=.d) -DEP_FILE=$(addprefix $(DST_DIR)/, $(DEP_LIST)) - -vpath %.c $(PRJ_PATH)/$(LOC_DIR) -vpath %.c $(PRJ_PATH)/app/nathelper/linux -vpath %.c $(PRJ_PATH)/app/nathelper/linux/lib -vpath %.o $(DST_DIR) -vpath %.d $(DST_DIR) - -DEP_LOOP=$(foreach i, $(SUB_DIR), $(MAKE) -C $(i) dep || exit 1;) -OBJ_LOOP=$(foreach i, $(SUB_DIR), $(MAKE) -C $(i) obj || exit 1;) -CLEAN_LOOP=$(foreach i, $(SUB_DIR), $(MAKE) -C $(i) clean;) -CLEAN_OBJ_LOOP=$(foreach i, $(SUB_DIR), $(MAKE) -C $(i) clean_o;) -CLEAN_DEP_LOOP=$(foreach i, $(SUB_DIR), $(MAKE) -C $(i) clean_d;) - diff --git a/feeds/ipq807x/qca-ssdk/src/make/linux_opt.mk b/feeds/ipq807x/qca-ssdk/src/make/linux_opt.mk deleted file mode 100755 index 17c75dd6e..000000000 --- a/feeds/ipq807x/qca-ssdk/src/make/linux_opt.mk +++ /dev/null @@ -1,698 +0,0 @@ -MODULE_CFLAG := -LOCAL_CFLAGS := - -ifeq (TRUE, $(SWCONFIG)) - MODULE_CFLAG += -DIN_SWCONFIG -endif - -ifeq (TRUE, $(IN_ACL)) - MODULE_CFLAG += -DIN_ACL -endif - -ifeq (TRUE, $(IN_FDB)) - MODULE_CFLAG += -DIN_FDB -endif - -ifeq (TRUE, $(IN_FDB_MINI)) - MODULE_CFLAG += -DIN_FDB_MINI -endif - -ifeq (TRUE, $(IN_IGMP)) - MODULE_CFLAG += -DIN_IGMP -endif - -ifeq (TRUE, $(IN_LEAKY)) - MODULE_CFLAG += -DIN_LEAKY -endif - -ifeq (TRUE, $(IN_LED)) - MODULE_CFLAG += -DIN_LED -endif - -ifeq (TRUE, $(IN_MIB)) - MODULE_CFLAG += -DIN_MIB -endif - -ifeq (TRUE, $(IN_MIRROR)) - MODULE_CFLAG += -DIN_MIRROR -endif - -ifeq (TRUE, $(IN_MISC)) - MODULE_CFLAG += -DIN_MISC -endif - -ifeq (TRUE, $(IN_MISC_MINI)) - MODULE_CFLAG += -DIN_MISC_MINI -endif - -ifeq (TRUE, $(IN_PORTCONTROL)) - MODULE_CFLAG += -DIN_PORTCONTROL -endif - -ifeq (TRUE, $(IN_PORTCONTROL_MINI)) - MODULE_CFLAG += -DIN_PORTCONTROL_MINI -endif - -ifeq (TRUE, $(IN_PORTVLAN)) - MODULE_CFLAG += -DIN_PORTVLAN -endif - -ifeq (TRUE, $(IN_PORTVLAN_MINI)) - MODULE_CFLAG += -DIN_PORTVLAN_MINI -endif - -ifeq (TRUE, $(IN_QOS)) - MODULE_CFLAG += -DIN_QOS -endif - -ifeq (TRUE, $(IN_QOS_MINI)) - MODULE_CFLAG += -DIN_QOS_MINI -endif - -ifeq (TRUE, $(IN_RATE)) - MODULE_CFLAG += -DIN_RATE -endif - -ifeq (TRUE, $(IN_STP)) - MODULE_CFLAG += -DIN_STP -endif - -ifeq (TRUE, $(IN_VLAN)) - MODULE_CFLAG += -DIN_VLAN -endif - -ifeq (TRUE, $(IN_VLAN_MINI)) - MODULE_CFLAG += -DIN_VLAN_MINI -endif - -ifeq (TRUE, $(IN_REDUCED_ACL)) - MODULE_CFLAG += -DIN_REDUCED_ACL -endif - -ifeq (TRUE, $(IN_COSMAP)) - MODULE_CFLAG += -DIN_COSMAP -endif - -ifeq (TRUE, $(IN_COSMAP_MINI)) - MODULE_CFLAG += -DIN_COSMAP_MINI -endif - -ifeq (TRUE, $(IN_IP)) - MODULE_CFLAG += -DIN_IP -endif - -ifeq (TRUE, $(IN_IP_MINI)) - MODULE_CFLAG += -DIN_IP_MINI -endif - -ifeq (TRUE, $(IN_NAT)) - MODULE_CFLAG += -DIN_NAT -endif - -ifeq (TRUE, $(IN_FLOW)) - MODULE_CFLAG += -DIN_FLOW -endif - -ifeq (TRUE, $(IN_FLOW_MINI)) - MODULE_CFLAG += -DIN_FLOW_MINI -endif - -ifeq (TRUE, $(IN_SFE)) - MODULE_CFLAG += -DIN_SFE -endif - -ifeq (TRUE, $(IN_TRUNK)) - MODULE_CFLAG += -DIN_TRUNK -endif - -ifeq (TRUE, $(IN_SEC)) - MODULE_CFLAG += -DIN_SEC -endif - -ifeq (TRUE, $(IN_QM)) - MODULE_CFLAG += -DIN_QM -endif - -ifeq (TRUE, $(IN_QM_MINI)) - MODULE_CFLAG += -DIN_QM_MINI -endif - -ifeq (TRUE, $(IN_NAT_HELPER)) - MODULE_CFLAG += -DIN_NAT_HELPER -endif - -ifeq (TRUE, $(IN_INTERFACECONTROL)) - MODULE_CFLAG += -DIN_INTERFACECONTROL -endif - -ifeq (TRUE, $(IN_CTRLPKT)) - MODULE_CFLAG += -DIN_CTRLPKT -endif - -ifeq (TRUE, $(IN_SERVCODE)) - MODULE_CFLAG += -DIN_SERVCODE -endif - -ifeq (TRUE, $(IN_RSS_HASH)) - MODULE_CFLAG += -DIN_RSS_HASH -endif - -ifeq (TRUE, $(IN_MACBLOCK)) - MODULE_CFLAG += -DIN_MACBLOCK -endif - -ifeq (TRUE, $(IN_RFS)) - MODULE_CFLAG += -DIN_RFS -endif - -ifeq (TRUE, $(IN_MALIBU_PHY)) - MODULE_CFLAG += -DIN_MALIBU_PHY -endif -ifeq (TRUE, $(IN_AQUANTIA_PHY)) - MODULE_CFLAG += -DIN_AQUANTIA_PHY -endif - -ifeq (TRUE, $(IN_QCA803X_PHY)) - MODULE_CFLAG += -DIN_QCA803X_PHY -endif - -ifeq (TRUE, $(IN_QCA808X_PHY)) - MODULE_CFLAG += -DIN_QCA808X_PHY -endif -ifeq (TRUE, $(IN_SFP_PHY)) - MODULE_CFLAG += -DIN_SFP_PHY -endif - -ifeq (TRUE, $(IN_PHY_I2C_MODE)) - MODULE_CFLAG += -DIN_PHY_I2C_MODE -endif - -ifeq (TRUE, $(IN_VSI)) - MODULE_CFLAG += -DIN_VSI -endif - -ifeq (TRUE, $(IN_VSI_MINI)) - MODULE_CFLAG += -DIN_VSI_MINI -endif - -ifeq (TRUE, $(IN_PPPOE)) - MODULE_CFLAG += -DIN_PPPOE -endif - -ifeq (TRUE, $(IN_BM)) - MODULE_CFLAG += -DIN_BM -endif - -ifeq (TRUE, $(IN_BM_MINI)) - MODULE_CFLAG += -DIN_BM_MINI -endif - -ifeq (TRUE, $(IN_SHAPER)) - MODULE_CFLAG += -DIN_SHAPER -endif - -ifeq (TRUE, $(IN_SHAPER_MINI)) - MODULE_CFLAG += -DIN_SHAPER_MINI -endif - -ifeq (TRUE, $(IN_POLICER)) - MODULE_CFLAG += -DIN_POLICER -endif - -ifeq (TRUE, $(IN_POLICER_MINI)) - MODULE_CFLAG += -DIN_POLICER_MINI -endif - -ifeq (TRUE, $(IN_UNIPHY)) - MODULE_CFLAG += -DIN_UNIPHY -endif - -ifeq (TRUE, $(IN_UNIPHY_MINI)) - MODULE_CFLAG += -DIN_UNIPHY_MINI -endif - -ifeq (TRUE, $(RUMI_EMULATION)) - MODULE_CFLAG += -DRUMI_EMULATION -endif - -ifeq (TRUE, $(IN_PTP)) - MODULE_CFLAG += -DIN_PTP -endif - -ifneq (TRUE, $(FAL)) - MODULE_CFLAG += -DHSL_STANDALONG -endif - -ifeq (TRUE, $(UK_IF)) - MODULE_CFLAG += -DUK_IF -endif - -#ifdef UK_NL_PROT - MODULE_CFLAG += -DUK_NL_PROT=$(UK_NL_PROT) -#endif - -#ifdef UK_MINOR_DEV - MODULE_CFLAG += -DUK_MINOR_DEV=$(UK_MINOR_DEV) -#endif - -ifeq (TRUE, $(API_LOCK)) - MODULE_CFLAG += -DAPI_LOCK -endif - -ifeq (TRUE, $(REG_ACCESS_SPEEDUP)) - MODULE_CFLAG += -DREG_ACCESS_SPEEDUP -endif - -ifeq (TRUE, $(DEBUG_ON)) - MODULE_CFLAG += -g -endif - -MODULE_CFLAG += $(OPT_FLAG) -Wall -DVERSION=\"$(VERSION)\" -DBUILD_DATE=\"$(BUILD_DATE)\" -DOS=\"$(OS)\" -D"KBUILD_STR(s)=\#s" -D"KBUILD_MODNAME=KBUILD_STR(qca-ssdk)" - -MODULE_INC += -I$(PRJ_PATH)/include \ - -I$(PRJ_PATH)/include/common \ - -I$(PRJ_PATH)/include/api \ - -I$(PRJ_PATH)/include/fal \ - -I$(PRJ_PATH)/include/ref \ - -I$(PRJ_PATH)/include/adpt \ - -I$(PRJ_PATH)/include/hsl \ - -I$(PRJ_PATH)/include/hsl/phy \ - -I$(PRJ_PATH)/include/sal/os \ - -I$(PRJ_PATH)/include/sal/os/linux \ - -I$(PRJ_PATH)/include/sal/sd \ - -I$(PRJ_PATH)/include/sal/sd/linux/hydra_howl \ - -I$(PRJ_PATH)/include/sal/sd/linux/uk_interface \ - -I$(PRJ_PATH)/include/init - -ifneq (,$(findstring ATHENA, $(SUPPORT_CHIP))) - MODULE_INC += -I$(PRJ_PATH)/include/hsl/athena - MODULE_CFLAG += -DATHENA -endif - -ifneq (,$(findstring GARUDA, $(SUPPORT_CHIP))) - MODULE_INC += -I$(PRJ_PATH)/include/hsl/garuda - MODULE_CFLAG += -DGARUDA -endif - -ifneq (,$(findstring SHIVA, $(SUPPORT_CHIP))) - MODULE_INC += -I$(PRJ_PATH)/include/hsl/shiva - MODULE_CFLAG += -DSHIVA -endif - -ifneq (,$(findstring HORUS, $(SUPPORT_CHIP))) - MODULE_INC += -I$(PRJ_PATH)/include/hsl/horus - MODULE_CFLAG += -DHORUS -endif - -ifneq (,$(filter ISIS, $(SUPPORT_CHIP))) - MODULE_INC += -I$(PRJ_PATH)/include/hsl/isis - MODULE_CFLAG += -DISIS -endif - -ifneq (,$(findstring ISISC, $(SUPPORT_CHIP))) - MODULE_INC += -I$(PRJ_PATH)/include/hsl/isisc - MODULE_CFLAG += -DISISC -endif - -ifneq (,$(findstring DESS, $(SUPPORT_CHIP))) - MODULE_INC += -I$(PRJ_PATH)/include/hsl/dess - MODULE_CFLAG += -DDESS -endif - -ifneq (,$(findstring HPPE, $(SUPPORT_CHIP))) - MODULE_INC += -I$(PRJ_PATH)/include/hsl/hppe - MODULE_INC += -I$(PRJ_PATH)/include/adpt/hppe - MODULE_CFLAG += -DHPPE -endif - -ifneq (,$(filter MP, $(SUPPORT_CHIP))) - MODULE_INC += -I$(PRJ_PATH)/include/hsl/hppe - MODULE_INC += -I$(PRJ_PATH)/include/adpt/mp - MODULE_INC += -I$(PRJ_PATH)/include/hsl/mp - MODULE_CFLAG += -DMP -endif - -ifneq (,$(findstring CPPE, $(SUPPORT_CHIP))) - MODULE_INC += -I$(PRJ_PATH)/include/hsl/cppe - MODULE_INC += -I$(PRJ_PATH)/include/adpt/cppe - MODULE_CFLAG += -DCPPE -endif - - -ifneq (,$(findstring SCOMPHY, $(SUPPORT_CHIP))) - MODULE_INC += -I$(PRJ_PATH)/include/hsl/scomphy - MODULE_CFLAG += -DSCOMPHY -endif - -ifeq (TRUE, $(IN_SFP)) - MODULE_INC += -I$(PRJ_PATH)/include/hsl/sfp - MODULE_INC += -I$(PRJ_PATH)/include/adpt/sfp - MODULE_CFLAG += -DIN_SFP -endif - -# check for GCC version -ifeq (4, $(GCC_VER)) - MODULE_CFLAG += -DGCCV4 -endif - -ifeq (TRUE, $(IN_PTP)) -ifeq ($(CONFIG_PTP_1588_CLOCK), y) - MODULE_CFLAG += -DIN_LINUX_STD_PTP -endif -endif - -ifeq (KSLIB, $(MODULE_TYPE)) - - MODULE_INC += -I$(PRJ_PATH)/include/shell_lib - ifndef TARGET_NAME - TARGET_NAME=arm-openwrt-linux-$(TARGET_SUFFIX) - endif - - ifeq ($(CONFIG_KASAN_INLINE),y) - CALL_THRESHOLD=10000 - else - CALL_THRESHOLD=0 - endif - ifneq ($(CONFIG_KASAN_SHADOW_OFFSET),) - SHADOW_OFFSET=$(CONFIG_KASAN_SHADOW_OFFSET) - else - SHADOW_OFFSET=0xdfffff9000000000 - endif - KASAN_OPTION=-fsanitize=kernel-address -fasan-shadow-offset=$(SHADOW_OFFSET) \ - --param asan-stack=1 --param asan-globals=1 \ - --param asan-instrumentation-with-call-threshold=$(CALL_THRESHOLD) - - ifeq ($(CONFIG_KASAN_SW_TAGS), y) - KASAN_SHADOW_SCALE_SHIFT := 4 - else - KASAN_SHADOW_SCALE_SHIFT := 3 - endif - - ifeq (5_4, $(OS_VER)) - ifeq ($(ARCH), arm64) - KASAN_OPTION += -DKASAN_SHADOW_SCALE_SHIFT=$(KASAN_SHADOW_SCALE_SHIFT) - endif - endif - ifeq ($(CONFIG_KASAN),y) - MODULE_CFLAG += $(KASAN_OPTION) - endif - - ifeq (3_18, $(OS_VER)) - MODULE_CFLAG += -DKVER34 - MODULE_CFLAG += -DKVER32 - MODULE_CFLAG += -DLNX26_22 - MODULE_INC += -I$(SYS_PATH) \ - -I$(TOOL_PATH)/../lib/gcc/$(TARGET_NAME)/$(GCC_VERSION)/include/ \ - -I$(SYS_PATH)/include \ - -I$(SYS_PATH)/source/include \ - -I$(SYS_PATH)/source/arch/arm/mach-msm/include \ - -I$(SYS_PATH)/arch/arm/mach-msm/include \ - -I$(SYS_PATH)/source/arch/arm/include \ - -I$(SYS_PATH)/arch/arm/include \ - -I$(SYS_PATH)/source/arch/arm/include/asm \ - -I$(SYS_PATH)/arch/arm/include/generated \ - -I$(SYS_PATH)/include/generated/uapi \ - -I$(SYS_PATH)/include/uapi \ - -I$(SYS_PATH)/arch/arm/include/uapi \ - -I$(SYS_PATH)/source/arch/arm/include/asm/mach \ - -include $(SYS_PATH)/include/linux/kconfig.h - - endif - - ifeq ($(OS_VER),$(filter 4_4 5_4, $(OS_VER))) - MODULE_CFLAG += -DKVER34 - MODULE_CFLAG += -DKVER32 - MODULE_CFLAG += -DLNX26_22 - ifeq ($(ARCH), arm64) - MODULE_INC += -I$(SYS_PATH) \ - -I$(TOOL_PATH)/../lib/gcc/$(TARGET_NAME)/$(GCC_VERSION)/include/ \ - -I$(SYS_PATH)/include \ - -I$(SYS_PATH)/source \ - -I$(SYS_PATH)/source/include \ - -I$(SYS_PATH)/source/arch/arm64/mach-msm/include \ - -I$(SYS_PATH)/arch/arm64/mach-msm/include \ - -I$(SYS_PATH)/source/arch/arm64/include \ - -I$(SYS_PATH)/arch/arm64/include \ - -I$(SYS_PATH)/source/arch/arm64/include/asm \ - -I$(SYS_PATH)/arch/arm64/include/generated \ - -I$(SYS_PATH)/include/generated/uapi \ - -I$(SYS_PATH)/include/uapi \ - -I$(SYS_PATH)/arch/arm64/include/uapi \ - -I$(SYS_PATH)/source/arch/arm64/include/asm/mach - - ifneq ($(wildcard $(SYS_PATH)/include/linux/kconfig.h),) - MODULE_INC += -include $(SYS_PATH)/include/linux/kconfig.h - else - MODULE_INC += -include $(KERNEL_SRC)/include/linux/kconfig.h - endif - - else ifeq ($(ARCH), arm) - MODULE_INC += -I$(SYS_PATH) \ - -I$(TOOL_PATH)/../lib/gcc/$(TARGET_NAME)/$(GCC_VERSION)/include/ \ - -I$(TOOL_PATH)/../lib/gcc/$(TARGET_NAME)/7.5.0/include/ \ - -I$(TOOL_PATH)/../../lib/armv7a-vfp-neon-rdk-linux-gnueabi/gcc/arm-rdk-linux-gnueabi/4.8.4/include/ \ - -I$(TOOL_PATH)/../../lib/arm-rdk-linux-musleabi/gcc/arm-rdk-linux-musleabi/6.4.0/include/ \ - -I$(SYS_PATH)/include \ - -I$(SYS_PATH)/source \ - -I$(SYS_PATH)/source/include \ - -I$(SYS_PATH)/source/arch/arm/mach-msm/include \ - -I$(SYS_PATH)/arch/arm/mach-msm/include \ - -I$(SYS_PATH)/source/arch/arm/include \ - -I$(SYS_PATH)/arch/arm/include \ - -I$(SYS_PATH)/source/arch/arm/include/asm \ - -I$(SYS_PATH)/arch/arm/include/generated \ - -I$(SYS_PATH)/arch/arm/include/generated/uapi \ - -I$(SYS_PATH)/source/include/uapi \ - -I$(SYS_PATH)/include/generated/uapi \ - -I$(SYS_PATH)/include/uapi \ - -I$(SYS_PATH)/arch/arm/include/uapi \ - -I$(SYS_PATH)/source/arch/arm/include/asm/mach - - ifneq ($(wildcard $(SYS_PATH)/include/linux/kconfig.h),) - MODULE_INC += -include $(SYS_PATH)/include/linux/kconfig.h - else - MODULE_INC += -include $(KERNEL_SRC)/include/linux/kconfig.h - endif - - else - MODULE_INC += -I$(SYS_PATH) \ - -I$(TOOL_PATH)/../lib/gcc/$(TARGET_NAME)/$(GCC_VERSION)/include/ \ - -I$(SYS_PATH)/include \ - -I$(SYS_PATH)/source \ - -I$(SYS_PATH)/source/include \ - -I$(SYS_PATH)/source/arch/mips/mach-msm/include \ - -I$(SYS_PATH)/arch/mips/mach-msm/include \ - -I$(SYS_PATH)/source/arch/mips/include \ - -I$(SYS_PATH)/arch/mips/include \ - -I$(SYS_PATH)/source/arch/mips/include/asm \ - -I$(SYS_PATH)/arch/mips/include/generated \ - -I$(SYS_PATH)/include/generated/uapi \ - -I$(SYS_PATH)/include/uapi \ - -I$(SYS_PATH)/arch/mips/include/uapi \ - -I$(SYS_PATH)/source/arch/mips/include/asm/mach \ - -include $(SYS_PATH)/include/linux/kconfig.h \ - -I$(SYS_PATH)/arch/mips/include/asm/mach-ar7240 \ - -I$(SYS_PATH)/arch/mips/include/asm/mach-generic \ - -I$(SYS_PATH)/arch/mips/include/asm/mach-ar7 \ - -I$(SYS_PATH)/usr/include - - #CPU_CFLAG = -G 0 -mno-abicalls -fno-pic -pipe -mabi=32 -march=mips32r2 - ifndef CPU_CFLAG - CPU_CFLAG = -Wstrict-prototypes -fomit-frame-pointer -G 0 -mno-abicalls -fno-strict-aliasing \ - -O2 -fno-pic -pipe -mabi=32 -march=mips32r2 -DMODULE -mlong-calls -DEXPORT_SYMTAB - endif - endif - - endif - - ifeq ($(OS_VER),$(filter 4_9 4_1, $(OS_VER))) - MODULE_CFLAG += -DKVER34 - MODULE_CFLAG += -DKVER32 - MODULE_CFLAG += -DLNX26_22 - ifeq ($(ARCH), arm64) - KCONF_FILE = $(SYS_PATH)/source/include/linux/kconfig.h - MODULE_INC += -I$(SYS_PATH) \ - -I$(TOOL_PATH)/../lib/gcc/$(TARGET_NAME)/$(GCC_VERSION)/include/ \ - -I$(SYS_PATH)/include \ - -I$(SYS_PATH)/source/include \ - -I$(SYS_PATH)/source/arch/arm64/mach-msm/include \ - -I$(SYS_PATH)/arch/arm64/mach-msm/include \ - -I$(SYS_PATH)/source/arch/arm64/include \ - -I$(SYS_PATH)/arch/arm64/include \ - -I$(SYS_PATH)/source/arch/arm64/include/asm \ - -I$(SYS_PATH)/arch/arm64/include/generated \ - -I$(SYS_PATH)/include/generated/uapi \ - -I$(SYS_PATH)/include/uapi \ - -I$(SYS_PATH)/arch/arm64/include/uapi \ - -I$(SYS_PATH)/source/include/uapi \ - -I$(SYS_PATH)/source/arch/arm64/include/asm/mach \ - -include $(KCONF_FILE) - else ifeq ($(ARCH), arm) - MODULE_INC += -I$(SYS_PATH) \ - -I$(TOOL_PATH)/../lib/gcc/$(TARGET_NAME)/$(GCC_VERSION)/include/ \ - -I$(TOOL_PATH)/../../lib/armv7a-vfp-neon-rdk-linux-gnueabi/gcc/arm-rdk-linux-gnueabi/4.8.4/include/ \ - -I$(SYS_PATH)/include \ - -I$(SYS_PATH)/source/include \ - -I$(SYS_PATH)/source/arch/arm/mach-msm/include \ - -I$(SYS_PATH)/arch/arm/mach-msm/include \ - -I$(SYS_PATH)/source/arch/arm/include \ - -I$(SYS_PATH)/arch/arm/include \ - -I$(SYS_PATH)/source/arch/arm/include/asm \ - -I$(SYS_PATH)/arch/arm/include/generated \ - -I$(SYS_PATH)/include/generated/uapi \ - -I$(SYS_PATH)/include/uapi \ - -I$(SYS_PATH)/arch/arm/include/uapi \ - -I$(SYS_PATH)/source/arch/arm/include/asm/mach \ - -include $(SYS_PATH)/include/linux/kconfig.h - endif - endif - - ifeq (3_14, $(OS_VER)) - MODULE_CFLAG += -DKVER34 - MODULE_CFLAG += -DKVER32 - MODULE_CFLAG += -DLNX26_22 - MODULE_INC += -I$(SYS_PATH) \ - -I$(TOOL_PATH)/../lib/gcc/$(TARGET_NAME)/$(GCC_VERSION)/include/ \ - -I$(TOOL_PATH)/../../lib/arm-poky-linux-gnueabi/gcc/arm-poky-linux-gnueabi/5.3.0/include/ \ - -I$(TOOL_PATH)/../../lib/armv7a-vfp-neon-rdk-linux-gnueabi/gcc/arm-rdk-linux-gnueabi/4.8.4/include/ \ - -I$(SYS_PATH)/include \ - -I$(SYS_PATH)/source/ \ - -I$(SYS_PATH)/source/include \ - -I$(SYS_PATH)/source/arch/arm/mach-msm/include \ - -I$(SYS_PATH)/arch/arm/mach-msm/include \ - -I$(SYS_PATH)/source/arch/arm/include \ - -I$(SYS_PATH)/arch/arm/include \ - -I$(SYS_PATH)/source/arch/arm/include/asm \ - -I$(SYS_PATH)/arch/arm/include/generated \ - -I$(SYS_PATH)/include/generated/uapi \ - -I$(SYS_PATH)/include/uapi \ - -I$(SYS_PATH)/source/include/uapi \ - -I$(SYS_PATH)/source/include/generated \ - -I$(SYS_PATH)/include/genearted \ - -I$(SYS_PATH)/arch/arm/include/uapi \ - -I$(SYS_PATH)/source/arch/arm/include/uapi \ - -I$(EXT_PATH) \ - -I$(SYS_PATH)/source/arch/arm/include/asm/mach - ifneq ($(wildcard $(SYS_PATH)/include/linux/kconfig.h),) - MODULE_INC += \ - -include $(SYS_PATH)/include/linux/kconfig.h - else - MODULE_INC += \ - -include $(SYS_PATH)/source/include/linux/kconfig.h - endif - - endif - - ifeq (3_4, $(OS_VER)) - MODULE_CFLAG += -DKVER34 - MODULE_CFLAG += -DKVER32 - MODULE_CFLAG += -DLNX26_22 - MODULE_CFLAG += -Werror - MODULE_INC += -I$(SYS_PATH) \ - -I$(SYS_PATH)/include \ - -I$(SYS_PATH)/source/include \ - -I$(SYS_PATH)/source/arch/arm/mach-msm/include \ - -I$(SYS_PATH)/source/arch/arm/include \ - -I$(SYS_PATH)/source/arch/arm/include/asm \ - -I$(SYS_PATH)/arch/arm/include/generated \ - -I$(SYS_PATH)/source/arch/arm/include/asm/mach \ - -I$(SYS_PATH)/usr/include - - endif - - ifeq (3_2, $(OS_VER)) - MODULE_CFLAG += -DKVER32 - MODULE_CFLAG += -DLNX26_22 - ifeq (mips, $(CPU)) - MODULE_INC += -I$(SYS_PATH) \ - -I$(SYS_PATH)/include \ - -I$(SYS_PATH)/arch/mips/include \ - -I$(SYS_PATH)/arch/mips/include/asm/mach-ar7240 \ - -I$(SYS_PATH)/arch/mips/include/asm/mach-generic \ - -I$(SYS_PATH)/arch/mips/include/asm/mach-ar7 \ - -I$(SYS_PATH)/usr/include \ - -I${KERN_SRC_PATH} \ - -I${KERN_SRC_PATH}/include \ - -I$(KERN_SRC_PATH)/arch/mips/include \ - -I$(KERN_SRC_PATH)/arch/mips/include/asm/mach-ar7240 \ - -I$(KERN_SRC_PATH)/arch/mips/include/asm/mach-generic \ - -I$(KERN_SRC_PATH)/arch/mips/include/asm/mach-ar7 \ - -I$(KERN_SRC_PATH)/usr/include - - #CPU_CFLAG = -G 0 -mno-abicalls -fno-pic -pipe -mabi=32 -march=mips32r2 - ifndef CPU_CFLAG - CPU_CFLAG = -Wstrict-prototypes -fomit-frame-pointer -G 0 -mno-abicalls -fno-strict-aliasing \ - -O2 -fno-pic -pipe -mabi=32 -march=mips32r2 -DMODULE -mlong-calls -DEXPORT_SYMTAB - endif - else - MODULE_INC += -I$(SYS_PATH) \ - -I$(SYS_PATH)/include \ - -I$(SYS_PATH)/arch/arm/include \ - -I$(SYS_PATH)/arch/arm/include/asm \ - -I$(SYS_PATH)/arch/arm/mach-fv16xx/include \ - -I$(SYS_PATH)/arch/arm/include/generated \ - -I$(SYS_PATH)/include/generated \ - -I$(SYS_PATH)/usr/include - endif - - - endif - - ifeq (2_6, $(OS_VER)) - MODULE_CFLAG += -DKVER26 - MODULE_CFLAG += -DLNX26_22 - ifeq (mips, $(CPU)) - MODULE_INC += -I$(SYS_PATH) \ - -I$(SYS_PATH)/include \ - -I$(SYS_PATH)/arch/mips/include \ - -I$(SYS_PATH)/arch/mips/include/asm/mach-ar7240 \ - -I$(SYS_PATH)/arch/mips/include/asm/mach-generic \ - -I$(SYS_PATH)/usr/include - - #CPU_CFLAG = -G 0 -mno-abicalls -fno-pic -pipe -mabi=32 -march=mips32r2 - ifndef CPU_CFLAG - CPU_CFLAG = -Wstrict-prototypes -fomit-frame-pointer -G 0 -mno-abicalls -fno-strict-aliasing \ - -O2 -fno-pic -pipe -mabi=32 -march=mips32r2 -DMODULE -mlong-calls -DEXPORT_SYMTAB - endif - else - MODULE_INC += -I$(SYS_PATH) \ - -I$(SYS_PATH)/include \ - -I$(SYS_PATH)/arch/arm/include \ - -I$(SYS_PATH)/arch/arm/include/asm \ - -I$(SYS_PATH)/arch/arm/mach-fv16xx/include \ - -I$(SYS_PATH)/arch/arm/include/generated \ - -I$(SYS_PATH)/include/generated \ - -I$(SYS_PATH)/usr/include - endif - - - endif - - MODULE_CFLAG += -D__KERNEL__ -DKERNEL_MODULE $(CPU_CFLAG) - - -endif - -ifeq (SHELL, $(MODULE_TYPE)) - MODULE_INC += -I$(PRJ_PATH)/include/shell - - ifeq (2_6, $(OS_VER)) - MODULE_CFLAG += -DKVER26 - else - MODULE_CFLAG += -DKVER24 - endif - - ifeq (TRUE, $(KERNEL_MODE)) - MODULE_CFLAG += -static - else - MODULE_CFLAG += -static -DUSER_MODE - endif -endif - -ifneq (TRUE, $(KERNEL_MODE)) - ifneq (SHELL, $(MODULE_TYPE)) - MODULE_CFLAG += -DUSER_MODE - endif -endif - -LOCAL_CFLAGS += $(MODULE_INC) $(MODULE_CFLAG) $(EXTRA_CFLAGS) diff --git a/feeds/ipq807x/qca-ssdk/src/make/target.mk b/feeds/ipq807x/qca-ssdk/src/make/target.mk deleted file mode 100755 index 72264f5cf..000000000 --- a/feeds/ipq807x/qca-ssdk/src/make/target.mk +++ /dev/null @@ -1,49 +0,0 @@ - -include $(PRJ_PATH)/make/$(OS)_opt.mk - -include $(PRJ_PATH)/make/tools.mk - -obj: $(OBJ_LIST) - $(OBJ_LOOP) - -dep: build_dir $(DEP_LIST) - $(DEP_LOOP) - -$(OBJ_LIST): %.o : %.c %.d - $(CC) $(CFLAGS) $(LOCAL_CFLAGS) -c $< -o $(DST_DIR)/$@ - -$(DEP_LIST) : %.d : %.c - $(CC) $(CFLAGS) $(LOCAL_CFLAGS) -MM $< > $(DST_DIR)/$@.tmp - sed 's,\($*\)\.o[ :]*,\1.o $@ : ,g' < $(DST_DIR)/$@.tmp > $(DST_DIR)/$@ - $(RM) -f $(DST_DIR)/$@.tmp; - -build_dir: $(DST_DIR) - -$(DST_DIR): - $(MKDIR) -p $(DST_DIR) - -.PHONY: clean -clean: clean_o clean_d - $(CLEAN_LOOP) - -.PHONY: clean_o -clean_o: clean_obj - $(CLEAN_OBJ_LOOP) - -.PHONY: clean_d -clean_d: clean_dep - $(CLEAN_DEP_LOOP) - -clean_obj: -ifneq (,$(word 1, $(OBJ_FILE))) - $(RM) -f $(OBJ_FILE) -endif - -clean_dep: -ifneq (,$(word 1, $(DEP_FILE))) - $(RM) -f $(DEP_FILE) -endif - -ifneq (,$(word 1, $(DEP_FILE))) - sinclude $(DEP_FILE) -endif diff --git a/feeds/ipq807x/qca-ssdk/src/make/tools.mk b/feeds/ipq807x/qca-ssdk/src/make/tools.mk deleted file mode 100755 index 6ed387298..000000000 --- a/feeds/ipq807x/qca-ssdk/src/make/tools.mk +++ /dev/null @@ -1,12 +0,0 @@ - -ifeq (linux, $(OS)) - CC=$(TOOL_PATH)/$(TOOLPREFIX)gcc - AR=$(TOOL_PATH)/$(TOOLPREFIX)ar - LD=$(TOOL_PATH)/$(TOOLPREFIX)ld - STRIP=$(TOOL_PATH)/$(TOOLPREFIX)strip - MAKE=make -S - CP=cp - MKDIR=mkdir - RM=rm - PERL=perl -endif diff --git a/feeds/ipq807x/qca-ssdk/src/src/adpt/Makefile b/feeds/ipq807x/qca-ssdk/src/src/adpt/Makefile deleted file mode 100755 index de3c0c095..000000000 --- a/feeds/ipq807x/qca-ssdk/src/src/adpt/Makefile +++ /dev/null @@ -1,12 +0,0 @@ -LOC_DIR=/src/adpt -LIB=ADPT - -include $(PRJ_PATH)/make/config.mk - -SRC_LIST=adpt.c - -include $(PRJ_PATH)/make/components.mk -include $(PRJ_PATH)/make/defs.mk -include $(PRJ_PATH)/make/target.mk - -all: dep obj diff --git a/feeds/ipq807x/qca-ssdk/src/src/adpt/adpt.c b/feeds/ipq807x/qca-ssdk/src/src/adpt/adpt.c deleted file mode 100644 index 77d577496..000000000 --- a/feeds/ipq807x/qca-ssdk/src/src/adpt/adpt.c +++ /dev/null @@ -1,658 +0,0 @@ -/* - * Copyright (c) 2016-2020, The Linux Foundation. All rights reserved. - * Permission to use, copy, modify, and/or distribute this software for - * any purpose with or without fee is hereby granted, provided that the - * above copyright notice and this permission notice appear in all copies. - * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES - * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR - * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES - * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN - * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT - * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. - */ - -#include "adpt.h" -#include "ssdk_init.h" -#if defined(HPPE) -#include "adpt_hppe.h" -#endif -#if defined(IN_SFP) -#include "adpt_sfp.h" -#endif -#if defined(MP) -#include "adpt_mp.h" -#endif -#include "hsl_phy.h" - -adpt_api_t *g_adpt_api[SW_MAX_NR_DEV] = {NULL}; - -adpt_chip_ver_t g_chip_ver[SW_MAX_NR_DEV] = {0}; - -adpt_api_t *adpt_api_ptr_get(a_uint32_t dev_id) -{ - if (dev_id >= SW_MAX_NR_DEV) - return NULL; - - return g_adpt_api[dev_id]; -} -#if defined (SCOMPHY) -a_uint32_t adapt_scomphy_revision_get(a_uint32_t dev_id) -{ - return g_chip_ver[dev_id].chip_revision; -} -#endif -#if defined(HPPE) -a_uint32_t adpt_hppe_chip_revision_get(a_uint32_t dev_id) -{ - return g_chip_ver[dev_id].chip_revision; -} - -static sw_error_t adpt_hppe_module_func_register(a_uint32_t dev_id, a_uint32_t module) -{ - sw_error_t rv= SW_OK; - - switch (module) - { - case FAL_MODULE_ACL: -#if defined(IN_ACL) - rv = adpt_hppe_acl_init(dev_id); -#endif - break; - case FAL_MODULE_VSI: -#if defined(IN_VSI) - rv = adpt_hppe_vsi_init(dev_id); -#endif - break; - case FAL_MODULE_IP: -#if defined(IN_IP) - rv = adpt_hppe_ip_init(dev_id); -#endif - break; - case FAL_MODULE_FLOW: -#if defined(IN_FLOW) - rv = adpt_hppe_flow_init(dev_id); -#endif - break; - case FAL_MODULE_QM: -#if defined(IN_QM) - rv = adpt_hppe_qm_init(dev_id); -#endif - break; - case FAL_MODULE_QOS: -#if defined(IN_QOS) - rv = adpt_hppe_qos_init(dev_id); -#endif - break; - case FAL_MODULE_BM: -#if defined(IN_BM) - rv = adpt_hppe_bm_init(dev_id); -#endif - break; - case FAL_MODULE_SERVCODE: -#if defined(IN_SERVCODE) - rv = adpt_hppe_servcode_init( dev_id); -#endif - break; - case FAL_MODULE_RSS_HASH: -#if defined(IN_RSS_HASH) - rv = adpt_hppe_rss_hash_init( dev_id); -#endif - break; - case FAL_MODULE_PPPOE: -#if defined(IN_PPPOE) - rv = adpt_hppe_pppoe_init(dev_id); -#endif - break; - case FAL_MODULE_PORTCTRL: -#if defined(IN_PORTCONTROL) - rv = adpt_hppe_port_ctrl_init(dev_id); -#endif - break; - case FAL_MODULE_SHAPER: -#if defined(IN_SHAPER) - rv = adpt_hppe_shaper_init( dev_id); -#endif - break; - case FAL_MODULE_MIB: -#if defined(IN_MIB) - rv = adpt_hppe_mib_init(dev_id); -#endif - break; - case FAL_MODULE_MIRROR: -#if defined(IN_MIRROR) - rv = adpt_hppe_mirror_init( dev_id); -#endif - break; - case FAL_MODULE_FDB: -#if defined(IN_FDB) - rv = adpt_hppe_fdb_init(dev_id); -#endif - break; - case FAL_MODULE_STP: -#if defined(IN_STP) - rv = adpt_hppe_stp_init(dev_id); -#endif - break; - case FAL_MODULE_TRUNK: -#if defined(IN_TRUNK) - rv = adpt_hppe_trunk_init( dev_id); -#endif - break; - case FAL_MODULE_PORTVLAN: -#if defined(IN_PORTVLAN) - rv = adpt_hppe_portvlan_init(dev_id); -#endif - break; - case FAL_MODULE_CTRLPKT: -#if defined(IN_CTRLPKT) - rv = adpt_hppe_ctrlpkt_init( dev_id); -#endif - break; - case FAL_MODULE_SEC: -#if defined(IN_SEC) - rv = adpt_hppe_sec_init(dev_id); -#endif - break; - case FAL_MODULE_POLICER: -#if defined(IN_POLICER) - rv = adpt_hppe_policer_init(dev_id); -#endif - break; - case FAL_MODULE_MISC: -#if defined(IN_MISC) - rv = adpt_hppe_misc_init(dev_id); -#endif - break; - case FAL_MODULE_PTP: -#if defined(IN_PTP) - rv = adpt_hppe_ptp_init(dev_id); -#endif - break; - case FAL_MODULE_SFP: -#if defined(IN_SFP) - rv = adpt_sfp_init(dev_id); -#endif - break; - default: - break; - } - - return rv; -} -#endif - -sw_error_t adpt_module_func_ctrl_set(a_uint32_t dev_id, - a_uint32_t module, fal_func_ctrl_t *func_ctrl) -{ - sw_error_t rv= SW_OK; - - adpt_api_t *p_adpt_api = NULL; - - p_adpt_api = adpt_api_ptr_get(dev_id); - - if(p_adpt_api == NULL) - return SW_FAIL; - - if(module == FAL_MODULE_ACL){ - p_adpt_api->adpt_acl_func_bitmap = func_ctrl->bitmap[0]; - } else if (module == FAL_MODULE_VSI) { - p_adpt_api->adpt_vsi_func_bitmap = func_ctrl->bitmap[0]; - }else if (module == FAL_MODULE_IP) { - p_adpt_api->adpt_ip_func_bitmap[0] = func_ctrl->bitmap[0]; - p_adpt_api->adpt_ip_func_bitmap[1] = func_ctrl->bitmap[1]; - } else if (module == FAL_MODULE_FLOW) { - p_adpt_api->adpt_flow_func_bitmap = func_ctrl->bitmap[0]; - } else if (module == FAL_MODULE_QM) { - p_adpt_api->adpt_qm_func_bitmap[0] = func_ctrl->bitmap[0]; - p_adpt_api->adpt_qm_func_bitmap[1] = func_ctrl->bitmap[1]; - } else if (module == FAL_MODULE_QOS) { - p_adpt_api->adpt_qos_func_bitmap = func_ctrl->bitmap[0]; - } else if (module == FAL_MODULE_BM) { - p_adpt_api->adpt_bm_func_bitmap = func_ctrl->bitmap[0]; - } else if (module == FAL_MODULE_SERVCODE) { - p_adpt_api->adpt_servcode_func_bitmap = func_ctrl->bitmap[0]; - } else if (module == FAL_MODULE_RSS_HASH) { - p_adpt_api->adpt_rss_hash_func_bitmap = func_ctrl->bitmap[0]; - } else if (module == FAL_MODULE_PPPOE) { - p_adpt_api->adpt_pppoe_func_bitmap = func_ctrl->bitmap[0]; - } else if (module == FAL_MODULE_PORTCTRL) { - p_adpt_api->adpt_port_ctrl_func_bitmap[0] = func_ctrl->bitmap[0]; - p_adpt_api->adpt_port_ctrl_func_bitmap[1] = func_ctrl->bitmap[1]; - p_adpt_api->adpt_port_ctrl_func_bitmap[2] = func_ctrl->bitmap[2]; - } else if (module == FAL_MODULE_SHAPER) { - p_adpt_api->adpt_shaper_func_bitmap = func_ctrl->bitmap[0]; - } else if(module == FAL_MODULE_MIB){ - p_adpt_api->adpt_mib_func_bitmap = func_ctrl->bitmap[0]; - } else if(module == FAL_MODULE_MIRROR){ - p_adpt_api->adpt_mirror_func_bitmap = func_ctrl->bitmap[0]; - } else if(module == FAL_MODULE_FDB){ - p_adpt_api->adpt_fdb_func_bitmap[0] = func_ctrl->bitmap[0]; - p_adpt_api->adpt_fdb_func_bitmap[1] = func_ctrl->bitmap[1]; - } else if(module == FAL_MODULE_STP){ - p_adpt_api->adpt_stp_func_bitmap = func_ctrl->bitmap[0]; - } else if(module == FAL_MODULE_TRUNK){ - p_adpt_api->adpt_trunk_func_bitmap = func_ctrl->bitmap[0]; - } else if(module == FAL_MODULE_PORTVLAN){ - p_adpt_api->adpt_portvlan_func_bitmap[0] = func_ctrl->bitmap[0]; - p_adpt_api->adpt_portvlan_func_bitmap[1] = func_ctrl->bitmap[1]; - } else if(module == FAL_MODULE_CTRLPKT){ - p_adpt_api->adpt_ctrlpkt_func_bitmap = func_ctrl->bitmap[0]; - } else if(module == FAL_MODULE_SEC){ - p_adpt_api->adpt_sec_func_bitmap = func_ctrl->bitmap[0]; - } else if(module == FAL_MODULE_POLICER){ - p_adpt_api->adpt_policer_func_bitmap = func_ctrl->bitmap[0]; - } - - - switch (g_chip_ver[dev_id].chip_type) - { - #if defined(HPPE) - case CHIP_HPPE: - rv = adpt_hppe_module_func_register(dev_id, module); - break; - #endif - default: - break; - } - - return rv; -} - -sw_error_t adpt_module_func_ctrl_get(a_uint32_t dev_id, - a_uint32_t module, fal_func_ctrl_t *func_ctrl) -{ - adpt_api_t *p_adpt_api = NULL; - - p_adpt_api = adpt_api_ptr_get(dev_id); - - if(p_adpt_api == NULL) - return SW_FAIL; - - if(module == FAL_MODULE_ACL){ - func_ctrl->bitmap[0] = p_adpt_api->adpt_acl_func_bitmap; - } else if (module == FAL_MODULE_VSI) { - func_ctrl->bitmap[0] = p_adpt_api->adpt_vsi_func_bitmap; - } else if (module == FAL_MODULE_IP) { - func_ctrl->bitmap[0] = p_adpt_api->adpt_ip_func_bitmap[0]; - func_ctrl->bitmap[1] = p_adpt_api->adpt_ip_func_bitmap[1]; - } else if (module == FAL_MODULE_FLOW) { - func_ctrl->bitmap[0] = p_adpt_api->adpt_flow_func_bitmap; - } else if (module == FAL_MODULE_QM) { - func_ctrl->bitmap[0] = p_adpt_api->adpt_qm_func_bitmap[0]; - func_ctrl->bitmap[1] = p_adpt_api->adpt_qm_func_bitmap[1]; - } else if (module == FAL_MODULE_QOS) { - func_ctrl->bitmap[0] = p_adpt_api->adpt_qos_func_bitmap; - } else if (module == FAL_MODULE_BM) { - func_ctrl->bitmap[0] = p_adpt_api->adpt_bm_func_bitmap; - } else if (module == FAL_MODULE_SERVCODE) { - func_ctrl->bitmap[0] = p_adpt_api->adpt_servcode_func_bitmap; - } else if (module == FAL_MODULE_RSS_HASH) { - func_ctrl->bitmap[0] = p_adpt_api->adpt_rss_hash_func_bitmap; - } else if (module == FAL_MODULE_PPPOE) { - func_ctrl->bitmap[0] = p_adpt_api->adpt_pppoe_func_bitmap; - } else if (module == FAL_MODULE_PORTCTRL) { - func_ctrl->bitmap[0] = p_adpt_api->adpt_port_ctrl_func_bitmap[0]; - func_ctrl->bitmap[1] = p_adpt_api->adpt_port_ctrl_func_bitmap[1]; - func_ctrl->bitmap[2] = p_adpt_api->adpt_port_ctrl_func_bitmap[2]; - } else if (module == FAL_MODULE_SHAPER) { - func_ctrl->bitmap[0] = p_adpt_api->adpt_shaper_func_bitmap; - } else if(module == FAL_MODULE_MIB) { - func_ctrl->bitmap[0] = p_adpt_api->adpt_mib_func_bitmap; - } else if(module == FAL_MODULE_MIRROR) { - func_ctrl->bitmap[0] = p_adpt_api->adpt_mirror_func_bitmap; - } else if(module == FAL_MODULE_FDB) { - func_ctrl->bitmap[0] = p_adpt_api->adpt_fdb_func_bitmap[0]; - func_ctrl->bitmap[1] = p_adpt_api->adpt_fdb_func_bitmap[1]; - } else if(module == FAL_MODULE_STP) { - func_ctrl->bitmap[0] = p_adpt_api->adpt_stp_func_bitmap; - } else if(module == FAL_MODULE_TRUNK) { - func_ctrl->bitmap[0] = p_adpt_api->adpt_trunk_func_bitmap; - } else if(module == FAL_MODULE_PORTVLAN) { - func_ctrl->bitmap[0] = p_adpt_api->adpt_portvlan_func_bitmap[0]; - func_ctrl->bitmap[1] = p_adpt_api->adpt_portvlan_func_bitmap[1]; - } else if(module == FAL_MODULE_CTRLPKT) { - func_ctrl->bitmap[0] = p_adpt_api->adpt_ctrlpkt_func_bitmap; - } else if(module == FAL_MODULE_SEC) { - func_ctrl->bitmap[0] = p_adpt_api->adpt_sec_func_bitmap; - } else if(module == FAL_MODULE_POLICER) { - func_ctrl->bitmap[0] = p_adpt_api->adpt_policer_func_bitmap; - } - - return SW_OK; -} - -sw_error_t adpt_init(a_uint32_t dev_id, ssdk_init_cfg *cfg) -{ - sw_error_t rv= SW_OK; - - switch (cfg->chip_type) - { -#if defined(HPPE) - case CHIP_HPPE: - g_adpt_api[dev_id] = aos_mem_alloc(sizeof(adpt_api_t)); - if(g_adpt_api[dev_id] == NULL) - { - printk("%s, %d:malloc fail for adpt api\n", __FUNCTION__, __LINE__); - return SW_FAIL; - } - aos_mem_zero(g_adpt_api[dev_id], sizeof(adpt_api_t)); - - g_chip_ver[dev_id].chip_type = cfg->chip_type; - g_chip_ver[dev_id].chip_revision = cfg->chip_revision; - g_adpt_api[dev_id]->adpt_mirror_func_bitmap = 0xffffffff; - rv = adpt_hppe_module_func_register(dev_id, FAL_MODULE_MIRROR); - SW_RTN_ON_ERROR(rv); - - g_adpt_api[dev_id]->adpt_fdb_func_bitmap[0] = 0xffffffff; - g_adpt_api[dev_id]->adpt_fdb_func_bitmap[1] = 0xffffffff; - rv = adpt_hppe_module_func_register(dev_id, FAL_MODULE_FDB); - SW_RTN_ON_ERROR(rv); - - g_adpt_api[dev_id]->adpt_stp_func_bitmap = 0xffffffff; - rv = adpt_hppe_module_func_register(dev_id, FAL_MODULE_STP); - SW_RTN_ON_ERROR(rv); - - g_adpt_api[dev_id]->adpt_trunk_func_bitmap = 0xffffffff; - rv = adpt_hppe_module_func_register(dev_id, FAL_MODULE_TRUNK); - SW_RTN_ON_ERROR(rv); - - g_adpt_api[dev_id]->adpt_portvlan_func_bitmap[0] = 0xffffffff; - g_adpt_api[dev_id]->adpt_portvlan_func_bitmap[1] = 0xffffffff; - rv = adpt_hppe_module_func_register(dev_id, FAL_MODULE_PORTVLAN); - SW_RTN_ON_ERROR(rv); - - g_adpt_api[dev_id]->adpt_ctrlpkt_func_bitmap = 0xffffffff; - rv = adpt_hppe_module_func_register(dev_id, FAL_MODULE_CTRLPKT); - SW_RTN_ON_ERROR(rv); - - g_adpt_api[dev_id]->adpt_sec_func_bitmap = 0xffffffff; - rv = adpt_hppe_module_func_register(dev_id, FAL_MODULE_SEC); - SW_RTN_ON_ERROR(rv); - - g_adpt_api[dev_id]->adpt_acl_func_bitmap = 0xffffffff; - rv = adpt_hppe_module_func_register(dev_id, FAL_MODULE_ACL); - SW_RTN_ON_ERROR(rv); - - g_adpt_api[dev_id]->adpt_vsi_func_bitmap = 0xffffffff; - rv = adpt_hppe_module_func_register(dev_id, FAL_MODULE_VSI); - SW_RTN_ON_ERROR(rv); - - g_adpt_api[dev_id]->adpt_ip_func_bitmap[0] = 0xffffffff; - g_adpt_api[dev_id]->adpt_ip_func_bitmap[1] = 0xffffffff; - rv = adpt_hppe_module_func_register(dev_id, FAL_MODULE_IP); - SW_RTN_ON_ERROR(rv); - - g_adpt_api[dev_id]->adpt_flow_func_bitmap = 0xffffffff; - rv = adpt_hppe_module_func_register(dev_id, FAL_MODULE_FLOW); - SW_RTN_ON_ERROR(rv); - - g_adpt_api[dev_id]->adpt_qm_func_bitmap[0] = 0xffffffff; - g_adpt_api[dev_id]->adpt_qm_func_bitmap[1] = 0xffffffff; - rv = adpt_hppe_module_func_register(dev_id, FAL_MODULE_QM); - SW_RTN_ON_ERROR(rv); - - g_adpt_api[dev_id]->adpt_qos_func_bitmap = 0xffffffff; - rv = adpt_hppe_module_func_register(dev_id, FAL_MODULE_QOS); - SW_RTN_ON_ERROR(rv); - - g_adpt_api[dev_id]->adpt_bm_func_bitmap = 0xffffffff; - rv = adpt_hppe_module_func_register(dev_id, FAL_MODULE_BM); - SW_RTN_ON_ERROR(rv); - - g_adpt_api[dev_id]->adpt_servcode_func_bitmap = 0xffffffff; - rv = adpt_hppe_module_func_register(dev_id, FAL_MODULE_SERVCODE); - SW_RTN_ON_ERROR(rv); - - g_adpt_api[dev_id]->adpt_rss_hash_func_bitmap = 0xffffffff; - rv = adpt_hppe_module_func_register(dev_id, FAL_MODULE_RSS_HASH); - SW_RTN_ON_ERROR(rv); - - g_adpt_api[dev_id]->adpt_pppoe_func_bitmap = 0xffffffff; - rv = adpt_hppe_module_func_register(dev_id, FAL_MODULE_PPPOE); - SW_RTN_ON_ERROR(rv); - - g_adpt_api[dev_id]->adpt_port_ctrl_func_bitmap[0] = 0xffffffff; - g_adpt_api[dev_id]->adpt_port_ctrl_func_bitmap[1] = 0xffffffff; - g_adpt_api[dev_id]->adpt_port_ctrl_func_bitmap[2] = 0xffffffff; - rv = adpt_hppe_module_func_register(dev_id, FAL_MODULE_PORTCTRL); - SW_RTN_ON_ERROR(rv); - - g_adpt_api[dev_id]->adpt_shaper_func_bitmap = 0xffffffff; - rv = adpt_hppe_module_func_register(dev_id, FAL_MODULE_SHAPER); - SW_RTN_ON_ERROR(rv); - - g_adpt_api[dev_id]->adpt_mib_func_bitmap = 0xffffffff; - rv = adpt_hppe_module_func_register(dev_id, FAL_MODULE_MIB); - SW_RTN_ON_ERROR(rv); - - g_adpt_api[dev_id]->adpt_policer_func_bitmap = 0xffffffff; - rv = adpt_hppe_module_func_register(dev_id, FAL_MODULE_POLICER); - SW_RTN_ON_ERROR(rv); - - rv = adpt_hppe_module_func_register(dev_id, FAL_MODULE_MISC); - SW_RTN_ON_ERROR(rv); - - rv = adpt_hppe_module_func_register(dev_id, FAL_MODULE_PTP); - SW_RTN_ON_ERROR(rv); - - rv = adpt_hppe_module_func_register(dev_id, FAL_MODULE_SFP); - SW_RTN_ON_ERROR(rv); - - /* uniphy */ - rv = adpt_hppe_uniphy_init(dev_id); - SW_RTN_ON_ERROR(rv); - - break; -#endif -#if defined (SCOMPHY) - case CHIP_SCOMPHY: - g_chip_ver[dev_id].chip_type = cfg->chip_type; - g_chip_ver[dev_id].chip_revision = cfg->phy_id; -#if defined (MP) - if(cfg->phy_id == MP_GEPHY) - { - g_adpt_api[dev_id] = aos_mem_alloc(sizeof(adpt_api_t)); - if(g_adpt_api[dev_id] == NULL) - { - SSDK_ERROR("malloc fail for adpt api\n"); - return SW_FAIL; - } - aos_mem_zero(g_adpt_api[dev_id], sizeof(adpt_api_t)); - rv = adpt_mp_intr_init(dev_id); - SW_RTN_ON_ERROR(rv); -#if defined (IN_MIB) - rv = adpt_mp_mib_init(dev_id); - SW_RTN_ON_ERROR(rv); -#endif -#if defined (IN_PORTCONTROL) - rv = adpt_mp_portctrl_init(dev_id); - SW_RTN_ON_ERROR(rv); -#endif -#if defined (IN_UNIPHY) - rv = adpt_mp_uniphy_init(dev_id); - SW_RTN_ON_ERROR(rv); -#endif -#if defined (IN_LED) - rv = adpt_mp_led_init(dev_id); - SW_RTN_ON_ERROR(rv); -#endif - } -#endif - break; -#endif - default: - break; - } - return rv; -} - -sw_error_t adpt_module_func_init(a_uint32_t dev_id, ssdk_init_cfg *cfg) -{ - sw_error_t rv= SW_OK; - - switch (cfg->chip_type) - { - #if defined(HPPE) - case CHIP_HPPE: - g_adpt_api[dev_id]->adpt_mirror_func_bitmap = 0; -#if defined(IN_MIRROR) - adpt_hppe_mirror_func_bitmap_init(dev_id); - rv = adpt_hppe_module_func_register(dev_id, FAL_MODULE_MIRROR); - SW_RTN_ON_ERROR(rv); -#endif - - g_adpt_api[dev_id]->adpt_fdb_func_bitmap[0] = 0; - g_adpt_api[dev_id]->adpt_fdb_func_bitmap[1] = 0; -#if defined(IN_FDB) - adpt_hppe_fdb_func_bitmap_init(dev_id); - rv = adpt_hppe_module_func_register(dev_id, FAL_MODULE_FDB); - SW_RTN_ON_ERROR(rv); -#endif - - g_adpt_api[dev_id]->adpt_stp_func_bitmap = 0; -#if defined(IN_STP) - adpt_hppe_stp_func_bitmap_init(dev_id); - rv = adpt_hppe_module_func_register(dev_id, FAL_MODULE_STP); - SW_RTN_ON_ERROR(rv); -#endif - - g_adpt_api[dev_id]->adpt_trunk_func_bitmap = 0; -#if defined(IN_TRUNK) - adpt_hppe_trunk_func_bitmap_init(dev_id); - rv = adpt_hppe_module_func_register(dev_id, FAL_MODULE_TRUNK); - SW_RTN_ON_ERROR(rv); -#endif - - g_adpt_api[dev_id]->adpt_portvlan_func_bitmap[0] = 0; - g_adpt_api[dev_id]->adpt_portvlan_func_bitmap[1] = 0; -#if defined(IN_PORTVLAN) - adpt_hppe_portvlan_func_bitmap_init(dev_id); - rv = adpt_hppe_module_func_register(dev_id, FAL_MODULE_PORTVLAN); - SW_RTN_ON_ERROR(rv); -#endif - - g_adpt_api[dev_id]->adpt_ctrlpkt_func_bitmap = 0; -#if defined(IN_CTRLPKT) - adpt_hppe_ctrlpkt_func_bitmap_init(dev_id); - rv = adpt_hppe_module_func_register(dev_id, FAL_MODULE_CTRLPKT); - SW_RTN_ON_ERROR(rv); -#endif - - g_adpt_api[dev_id]->adpt_sec_func_bitmap = 0; -#if defined(IN_SEC) - adpt_hppe_sec_func_bitmap_init(dev_id); - rv = adpt_hppe_module_func_register(dev_id, FAL_MODULE_SEC); - SW_RTN_ON_ERROR(rv); -#endif - - g_adpt_api[dev_id]->adpt_acl_func_bitmap = 0; -#if defined(IN_ACL) - adpt_hppe_acl_func_bitmap_init(dev_id); - rv = adpt_hppe_module_func_register(dev_id, FAL_MODULE_ACL); - SW_RTN_ON_ERROR(rv); -#endif - - g_adpt_api[dev_id]->adpt_vsi_func_bitmap = 0; -#if defined(IN_VSI) - adpt_hppe_vsi_func_bitmap_init(dev_id); - rv = adpt_hppe_module_func_register(dev_id, FAL_MODULE_VSI); - SW_RTN_ON_ERROR(rv); -#endif - - g_adpt_api[dev_id]->adpt_ip_func_bitmap[0] = 0; - g_adpt_api[dev_id]->adpt_ip_func_bitmap[1] = 0; -#if defined(IN_IP) - adpt_hppe_ip_func_bitmap_init(dev_id); - rv = adpt_hppe_module_func_register(dev_id, FAL_MODULE_IP); - SW_RTN_ON_ERROR(rv); -#endif - - g_adpt_api[dev_id]->adpt_flow_func_bitmap = 0; -#if defined(IN_FLOW) - adpt_hppe_flow_func_bitmap_init(dev_id); - rv = adpt_hppe_module_func_register(dev_id, FAL_MODULE_FLOW); - SW_RTN_ON_ERROR(rv); -#endif - - g_adpt_api[dev_id]->adpt_qm_func_bitmap[0] = 0; - g_adpt_api[dev_id]->adpt_qm_func_bitmap[1] = 0; -#if defined(IN_QM) - adpt_hppe_qm_func_bitmap_init(dev_id); - rv = adpt_hppe_module_func_register(dev_id, FAL_MODULE_QM); - SW_RTN_ON_ERROR(rv); -#endif - - g_adpt_api[dev_id]->adpt_qos_func_bitmap = 0; -#if defined(IN_QOS) - adpt_hppe_qos_func_bitmap_init(dev_id); - rv = adpt_hppe_module_func_register(dev_id, FAL_MODULE_QOS); - SW_RTN_ON_ERROR(rv); -#endif - - g_adpt_api[dev_id]->adpt_bm_func_bitmap = 0; -#if defined(IN_BM) - adpt_hppe_bm_func_bitmap_init(dev_id); - rv = adpt_hppe_module_func_register(dev_id, FAL_MODULE_BM); - SW_RTN_ON_ERROR(rv); -#endif - - g_adpt_api[dev_id]->adpt_servcode_func_bitmap = 0; -#if defined(IN_SERVCODE) - adpt_hppe_servcode_func_bitmap_init(dev_id); - rv = adpt_hppe_module_func_register(dev_id, FAL_MODULE_SERVCODE); - SW_RTN_ON_ERROR(rv); -#endif - - g_adpt_api[dev_id]->adpt_rss_hash_func_bitmap = 0; -#if defined(IN_RSS_HASH) - adpt_hppe_rss_hash_func_bitmap_init(dev_id); - rv = adpt_hppe_module_func_register(dev_id, FAL_MODULE_RSS_HASH); - SW_RTN_ON_ERROR(rv); -#endif - - g_adpt_api[dev_id]->adpt_pppoe_func_bitmap = 0; -#if defined(IN_PPPOE) - adpt_hppe_pppoe_func_bitmap_init(dev_id); - rv = adpt_hppe_module_func_register(dev_id, FAL_MODULE_PPPOE); - SW_RTN_ON_ERROR(rv); -#endif - - g_adpt_api[dev_id]->adpt_port_ctrl_func_bitmap[0] = 0; - g_adpt_api[dev_id]->adpt_port_ctrl_func_bitmap[1] = 0; - g_adpt_api[dev_id]->adpt_port_ctrl_func_bitmap[2] = 0; -#if defined(IN_PORTCONTROL) - adpt_hppe_port_ctrl_func_bitmap_init(dev_id); - rv = adpt_hppe_module_func_register(dev_id, FAL_MODULE_PORTCTRL); - SW_RTN_ON_ERROR(rv); -#endif - - g_adpt_api[dev_id]->adpt_shaper_func_bitmap = 0; -#if defined(IN_SHAPER) - adpt_hppe_shaper_func_bitmap_init(dev_id); - rv = adpt_hppe_module_func_register(dev_id, FAL_MODULE_SHAPER); - SW_RTN_ON_ERROR(rv); -#endif - - g_adpt_api[dev_id]->adpt_mib_func_bitmap = 0; -#if defined(IN_MIB) - adpt_hppe_mib_func_bitmap_init(dev_id); - rv = adpt_hppe_module_func_register(dev_id, FAL_MODULE_MIB); - SW_RTN_ON_ERROR(rv); -#endif - - g_adpt_api[dev_id]->adpt_policer_func_bitmap = 0; -#if defined(IN_POLICER) - adpt_hppe_policer_func_bitmap_init(dev_id); - rv = adpt_hppe_module_func_register(dev_id, FAL_MODULE_POLICER); - SW_RTN_ON_ERROR(rv); -#endif - - break; - #endif - default: - break; - } - return rv; -} - diff --git a/feeds/ipq807x/qca-ssdk/src/src/adpt/cppe/Makefile b/feeds/ipq807x/qca-ssdk/src/src/adpt/cppe/Makefile deleted file mode 100755 index 990c62937..000000000 --- a/feeds/ipq807x/qca-ssdk/src/src/adpt/cppe/Makefile +++ /dev/null @@ -1,48 +0,0 @@ -LOC_DIR=src/adpt/cppe -LIB=ADPT - -include $(PRJ_PATH)/make/config.mk - -SRC_LIST= - -ifeq (TRUE, $(IN_PORTCONTROL)) - SRC_LIST += adpt_cppe_portctrl.c -endif - -ifeq (TRUE, $(IN_QM)) - SRC_LIST += adpt_cppe_qm.c -endif - -ifeq (TRUE, $(IN_QOS)) - SRC_LIST += adpt_cppe_qos.c -endif - -ifeq (TRUE, $(IN_UNIPHY)) - SRC_LIST += adpt_cppe_uniphy.c -endif - -ifeq (TRUE, $(IN_MISC)) -ifneq (TRUE, $(IN_MISC_MINI)) - SRC_LIST += adpt_cppe_misc.c -endif -endif - -ifeq (TRUE, $(IN_FLOW)) -ifneq (TRUE, $(IN_FLOW_MINI)) - SRC_LIST += adpt_cppe_flow.c -endif -endif - -ifeq (TRUE, $(IN_MIB)) - SRC_LIST += adpt_cppe_mib.c -endif - -ifeq (, $(findstring CPPE, $(SUPPORT_CHIP))) - SRC_LIST= -endif - -include $(PRJ_PATH)/make/components.mk -include $(PRJ_PATH)/make/defs.mk -include $(PRJ_PATH)/make/target.mk - -all: dep obj diff --git a/feeds/ipq807x/qca-ssdk/src/src/adpt/cppe/adpt_cppe_flow.c b/feeds/ipq807x/qca-ssdk/src/src/adpt/cppe/adpt_cppe_flow.c deleted file mode 100755 index ea3877d34..000000000 --- a/feeds/ipq807x/qca-ssdk/src/src/adpt/cppe/adpt_cppe_flow.c +++ /dev/null @@ -1,77 +0,0 @@ -/* - * Copyright (c) 2019, The Linux Foundation. All rights reserved. - * Permission to use, copy, modify, and/or distribute this software for - * any purpose with or without fee is hereby granted, provided that the - * above copyright notice and this permission notice appear in all copies. - * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES - * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR - * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES - * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN - * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT - * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. - */ - - -/** - * @defgroup - * @{ - */ -#include "sw.h" -#include "hppe_fdb_reg.h" -#include "hppe_fdb.h" -#include "hppe_ip_reg.h" -#include "hppe_ip.h" -#include "adpt.h" - -sw_error_t -adpt_cppe_flow_copy_escape_set(a_uint32_t dev_id, a_bool_t enable) -{ - sw_error_t rv = SW_OK; - union l2_global_conf_u l2_global_conf; - union l3_route_ctrl_ext_u l3_route_ctrl_ext; - - ADPT_DEV_ID_CHECK(dev_id); - - memset(&l2_global_conf, 0, sizeof(l2_global_conf)); - rv = hppe_l2_global_conf_get(dev_id, &l2_global_conf); - SW_RTN_ON_ERROR(rv); - l2_global_conf.bf.l2_flow_copy_escape = enable; - rv = hppe_l2_global_conf_set(dev_id, &l2_global_conf); - SW_RTN_ON_ERROR(rv); - - memset(&l3_route_ctrl_ext, 0, sizeof(l3_route_ctrl_ext)); - rv = hppe_l3_route_ctrl_ext_get(dev_id, &l3_route_ctrl_ext); - SW_RTN_ON_ERROR(rv); - l3_route_ctrl_ext.bf.l3_flow_copy_escape = enable; - rv = hppe_l3_route_ctrl_ext_set(dev_id, &l3_route_ctrl_ext); - - return rv; -} - -sw_error_t -adpt_cppe_flow_copy_escape_get(a_uint32_t dev_id, a_bool_t *enable) -{ - - sw_error_t rv = SW_OK; - union l2_global_conf_u l2_global_conf; - union l3_route_ctrl_ext_u l3_route_ctrl_ext; - - ADPT_DEV_ID_CHECK(dev_id); - ADPT_NULL_POINT_CHECK(enable); - - memset(&l2_global_conf, 0, sizeof(l2_global_conf)); - rv = hppe_l2_global_conf_get(dev_id, &l2_global_conf); - SW_RTN_ON_ERROR(rv); - - memset(&l3_route_ctrl_ext, 0, sizeof(l3_route_ctrl_ext)); - rv = hppe_l3_route_ctrl_ext_get(dev_id, &l3_route_ctrl_ext); - SW_RTN_ON_ERROR(rv); - - *enable = l2_global_conf.bf.l2_flow_copy_escape & l3_route_ctrl_ext.bf.l3_flow_copy_escape; - return rv; -} - -/** - * @} - */ diff --git a/feeds/ipq807x/qca-ssdk/src/src/adpt/cppe/adpt_cppe_mib.c b/feeds/ipq807x/qca-ssdk/src/src/adpt/cppe/adpt_cppe_mib.c deleted file mode 100755 index 60c4f622d..000000000 --- a/feeds/ipq807x/qca-ssdk/src/src/adpt/cppe/adpt_cppe_mib.c +++ /dev/null @@ -1,181 +0,0 @@ -/* - * Copyright (c) 2019, The Linux Foundation. All rights reserved. - * Permission to use, copy, modify, and/or distribute this software for - * any purpose with or without fee is hereby granted, provided that the - * above copyright notice and this permission notice appear in all copies. - * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES - * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR - * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES - * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN - * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT - * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. - */ -/** - * @defgroup - * @{ - */ -#include "sw.h" -#include "adpt.h" -#include "cppe_loopback_reg.h" -#include "cppe_loopback.h" -#include "hppe_init.h" - -sw_error_t -adpt_cppe_lpbk_mib_cpukeep_get(a_uint32_t dev_id, a_uint32_t port_id, - a_bool_t *enable) -{ - sw_error_t rv = SW_OK; - union lpbk_mib_ctrl_u reg_value; - - ADPT_DEV_ID_CHECK(dev_id); - ADPT_NULL_POINT_CHECK(enable); - - rv = cppe_lpbk_mib_ctrl_get(dev_id, port_id, ®_value); - SW_RTN_ON_ERROR(rv); - - if (reg_value.bf.mib_rd_clr == A_TRUE) - { - *enable = A_FALSE; - } - else - { - *enable = A_TRUE; - } - - return SW_OK; -} - -sw_error_t -adpt_cppe_lpbk_mib_cpukeep_set(a_uint32_t dev_id, a_uint32_t port_id, - a_bool_t enable) -{ - union lpbk_mib_ctrl_u reg_value; - sw_error_t rv = SW_OK; - - ADPT_DEV_ID_CHECK(dev_id); - port_id = HPPE_TO_GMAC_PORT_ID(port_id); - rv = cppe_lpbk_mib_ctrl_get(dev_id, port_id, ®_value); - SW_RTN_ON_ERROR(rv); - if(!enable) - { - reg_value.bf.mib_rd_clr = A_TRUE; - } - else - { - reg_value.bf.mib_rd_clr = A_FALSE; - } - rv = cppe_lpbk_mib_ctrl_set(dev_id, port_id, ®_value); - - return rv; -} - -sw_error_t -adpt_hppe_lpbk_mib_status_get(a_uint32_t dev_id, a_uint32_t port_id, - a_bool_t *enable) -{ - sw_error_t rv = SW_OK; - union lpbk_mib_ctrl_u reg_value; - - ADPT_DEV_ID_CHECK(dev_id); - ADPT_NULL_POINT_CHECK(enable); - - rv = cppe_lpbk_mib_ctrl_get(dev_id, port_id, ®_value); - SW_RTN_ON_ERROR(rv); - *enable = reg_value.bf.mib_en; - - return rv; -} - -sw_error_t -adpt_cppe_lpbk_mib_status_set(a_uint32_t dev_id, a_uint32_t port_id, - a_bool_t enable) -{ - union lpbk_mib_ctrl_u reg_value; - sw_error_t rv = SW_OK; - - ADPT_DEV_ID_CHECK(dev_id); - - port_id = HPPE_TO_GMAC_PORT_ID(port_id); - rv = cppe_lpbk_mib_ctrl_get(dev_id, port_id, ®_value); - SW_RTN_ON_ERROR(rv); - reg_value.bf.mib_en = enable; - rv = cppe_lpbk_mib_ctrl_set(dev_id, port_id, ®_value); - - return rv; -} - -sw_error_t -adpt_cppe_lpbk_mib_flush_counters(a_uint32_t dev_id, fal_port_t port_id) -{ - union lpbk_mib_ctrl_u reg_value; - sw_error_t rv = SW_OK; - - ADPT_DEV_ID_CHECK(dev_id); - port_id = HPPE_TO_GMAC_PORT_ID(port_id); - rv = cppe_lpbk_mib_ctrl_get(dev_id, port_id, ®_value); - SW_RTN_ON_ERROR(rv); - reg_value.bf.mib_reset = A_TRUE; - rv = cppe_lpbk_mib_ctrl_set(dev_id, port_id, ®_value); - SW_RTN_ON_ERROR(rv); - reg_value.bf.mib_reset = A_FALSE; - rv = cppe_lpbk_mib_ctrl_set(dev_id, port_id, ®_value); - - return rv; -} - -sw_error_t -adpt_cppe_lpbk_get_mib_info(a_uint32_t dev_id, fal_port_t port_id, - fal_mib_info_t * mib_info ) -{ - ADPT_DEV_ID_CHECK(dev_id); - ADPT_NULL_POINT_CHECK(mib_info); - memset(mib_info, 0, sizeof(*mib_info)); - - port_id = HPPE_TO_GMAC_PORT_ID(port_id); - cppe_lpbk_mib_uni_get(dev_id, (a_uint32_t)port_id, - (union lpbkuni_u *)&mib_info->RxUniCast); - cppe_lpbk_mib_multi_get(dev_id, (a_uint32_t)port_id, - (union lpbkmulti_u *)&mib_info->RxMulti); - cppe_lpbk_mib_broad_get(dev_id, (a_uint32_t)port_id, - (union lpbkbroad_u *)&mib_info->RxBroad); - cppe_lpbk_mib_pkt64_get(dev_id, (a_uint32_t)port_id, - (union lpbkpkt64_u *)&mib_info->Rx64Byte); - cppe_lpbk_mib_pkt65to127_get(dev_id, (a_uint32_t)port_id, - (union lpbkpkt65to127_u *)&mib_info->Rx128Byte); - cppe_lpbk_mib_pkt128to255_get(dev_id, (a_uint32_t)port_id, - (union lpbkpkt128to255_u *)&mib_info->Rx256Byte); - cppe_lpbk_mib_pkt256to511_get(dev_id, (a_uint32_t)port_id, - (union lpbkpkt256to511_u *)&mib_info->Rx512Byte); - cppe_lpbk_mib_pkt512to1023_get(dev_id, (a_uint32_t)port_id, - (union lpbkpkt512to1023_u *)&mib_info->Rx1024Byte); - cppe_lpbk_mib_pkt1024to1518_get(dev_id, (a_uint32_t)port_id, - (union lpbkpkt1024to1518_u *)&mib_info->Rx1518Byte); - cppe_lpbk_mib_pkt1519tox_get(dev_id, (a_uint32_t)port_id, - (union lpbkpkt1519tox_u *)&mib_info->RxMaxByte); - cppe_lpbk_mib_toolong_get(dev_id, (a_uint32_t)port_id, - (union lpbkpkttoolong_u *)&mib_info->RxTooLong); - cppe_lpbk_mib_byte_l_get(dev_id, (a_uint32_t)port_id, - (union lpbkbyte_l_u *)&mib_info->RxGoodByte_lo); - cppe_lpbk_mib_byte_h_get(dev_id, (a_uint32_t)port_id, - (union lpbkbyte_h_u *)&mib_info->RxGoodByte_hi); - cppe_lpbk_mib_drop_get(dev_id, (a_uint32_t)port_id, - (union lpbkdropcounter_u *)&mib_info->Filtered); - cppe_lpbk_mib_tooshort_get(dev_id, (a_uint32_t)port_id, - (union lpbkpkttooshort_u *)&mib_info->RxRunt); - cppe_lpbk_mib_pkt14to63_get(dev_id, (a_uint32_t)port_id, - (union lpbkpkt14to63_u *)&mib_info->Rx14To63); - cppe_lpbk_mib_toolongbyte_l_get(dev_id, (a_uint32_t)port_id, - (union lpbktoolongbyte_l_u *)&mib_info->RxTooLongByte_lo); - cppe_lpbk_mib_toolongbyte_h_get(dev_id, (a_uint32_t)port_id, - (union lpbktoolongbyte_h_u *)&mib_info->RxTooLongByte_hi); - cppe_lpbk_mib_tooshortbyte_l_get(dev_id, (a_uint32_t)port_id, - (union lpbktooshortbyte_l_u *)&mib_info->RxRuntByte_lo); - cppe_lpbk_mib_tooshortbyte_h_get(dev_id, (a_uint32_t)port_id, - (union lpbktooshortbyte_h_u *)&mib_info->RxRuntByte_hi); - - return SW_OK; -} -/** - * @} - */ diff --git a/feeds/ipq807x/qca-ssdk/src/src/adpt/cppe/adpt_cppe_misc.c b/feeds/ipq807x/qca-ssdk/src/src/adpt/cppe/adpt_cppe_misc.c deleted file mode 100755 index f7c257607..000000000 --- a/feeds/ipq807x/qca-ssdk/src/src/adpt/cppe/adpt_cppe_misc.c +++ /dev/null @@ -1,121 +0,0 @@ -/* - * Copyright (c) 2019, The Linux Foundation. All rights reserved. - * Permission to use, copy, modify, and/or distribute this software for - * any purpose with or without fee is hereby granted, provided that the - * above copyright notice and this permission notice appear in all copies. - * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES - * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR - * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES - * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN - * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT - * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. - */ - - -/** - * @defgroup - * @{ - */ -#include "sw.h" -#include "hppe_portctrl_reg.h" -#include "hppe_portctrl.h" -#include "hppe_portvlan_reg.h" -#include "hppe_portvlan.h" -#include "cppe_portctrl_reg.h" -#include "cppe_portctrl.h" -#include "adpt.h" - -sw_error_t -adpt_cppe_debug_port_counter_enable(a_uint32_t dev_id, fal_port_t port_id, - fal_counter_en_t *cnt_en) -{ - union cppe_mru_mtu_ctrl_tbl_u mru_mtu_ctrl_tbl; - union mc_mtu_ctrl_tbl_u mc_mtu_ctrl_tbl; - union port_eg_vlan_u port_eg_vlan; - sw_error_t rv = SW_OK; - - ADPT_DEV_ID_CHECK(dev_id); - ADPT_NULL_POINT_CHECK(cnt_en); - - port_id = FAL_PORT_ID_VALUE(port_id); - - if (port_id < SSDK_MAX_PORT_NUM) { - rv = cppe_mru_mtu_ctrl_tbl_get(dev_id, port_id, &mru_mtu_ctrl_tbl); - SW_RTN_ON_ERROR(rv); - rv = hppe_mc_mtu_ctrl_tbl_get(dev_id, port_id, &mc_mtu_ctrl_tbl); - SW_RTN_ON_ERROR(rv); - rv = hppe_port_eg_vlan_get(dev_id, port_id, &port_eg_vlan); - SW_RTN_ON_ERROR(rv); - - mru_mtu_ctrl_tbl.bf.rx_cnt_en = cnt_en->rx_counter_en; - mru_mtu_ctrl_tbl.bf.tx_cnt_en = cnt_en->vp_uni_tx_counter_en; - mc_mtu_ctrl_tbl.bf.tx_cnt_en = cnt_en->port_mc_tx_counter_en; - port_eg_vlan.bf.tx_counting_en = cnt_en->port_tx_counter_en; - - rv = cppe_mru_mtu_ctrl_tbl_set(dev_id, port_id, &mru_mtu_ctrl_tbl); - SW_RTN_ON_ERROR(rv); - rv = hppe_mc_mtu_ctrl_tbl_set(dev_id, port_id, &mc_mtu_ctrl_tbl); - SW_RTN_ON_ERROR(rv); - rv = hppe_port_eg_vlan_set(dev_id, port_id, &port_eg_vlan); - SW_RTN_ON_ERROR(rv); - } else if (port_id >= SSDK_MAX_PORT_NUM && - port_id < SSDK_MAX_VIRTUAL_PORT_NUM) { - rv = cppe_mru_mtu_ctrl_tbl_get(dev_id, port_id, &mru_mtu_ctrl_tbl); - SW_RTN_ON_ERROR(rv); - - mru_mtu_ctrl_tbl.bf.rx_cnt_en = cnt_en->rx_counter_en; - mru_mtu_ctrl_tbl.bf.tx_cnt_en = cnt_en->vp_uni_tx_counter_en; - - rv = cppe_mru_mtu_ctrl_tbl_set(dev_id, port_id, &mru_mtu_ctrl_tbl); - SW_RTN_ON_ERROR(rv); - } else { - return SW_OUT_OF_RANGE; - } - - return rv; -} - -sw_error_t -adpt_cppe_debug_port_counter_status_get(a_uint32_t dev_id, fal_port_t port_id, - fal_counter_en_t *cnt_en) -{ - union cppe_mru_mtu_ctrl_tbl_u mru_mtu_ctrl_tbl; - union mc_mtu_ctrl_tbl_u mc_mtu_ctrl_tbl; - union port_eg_vlan_u port_eg_vlan; - sw_error_t rv = SW_OK; - - ADPT_DEV_ID_CHECK(dev_id); - ADPT_NULL_POINT_CHECK(cnt_en); - - port_id = FAL_PORT_ID_VALUE(port_id); - - if (port_id < SSDK_MAX_PORT_NUM) { - rv = cppe_mru_mtu_ctrl_tbl_get(dev_id, port_id, &mru_mtu_ctrl_tbl); - SW_RTN_ON_ERROR(rv); - rv = hppe_mc_mtu_ctrl_tbl_get(dev_id, port_id, &mc_mtu_ctrl_tbl); - SW_RTN_ON_ERROR(rv); - rv = hppe_port_eg_vlan_get(dev_id, port_id, &port_eg_vlan); - SW_RTN_ON_ERROR(rv); - - cnt_en->rx_counter_en = mru_mtu_ctrl_tbl.bf.rx_cnt_en; - cnt_en->vp_uni_tx_counter_en = mru_mtu_ctrl_tbl.bf.tx_cnt_en; - cnt_en->port_mc_tx_counter_en = mc_mtu_ctrl_tbl.bf.tx_cnt_en; - cnt_en->port_tx_counter_en = port_eg_vlan.bf.tx_counting_en; - } else if (port_id >= SSDK_MAX_PORT_NUM && - port_id < SSDK_MAX_VIRTUAL_PORT_NUM) { - rv = cppe_mru_mtu_ctrl_tbl_get(dev_id, port_id, &mru_mtu_ctrl_tbl); - SW_RTN_ON_ERROR(rv); - - cnt_en->rx_counter_en = mru_mtu_ctrl_tbl.bf.rx_cnt_en; - cnt_en->vp_uni_tx_counter_en = mru_mtu_ctrl_tbl.bf.tx_cnt_en; - } else { - return SW_OUT_OF_RANGE; - } - - return rv; -} - -/** - * @} - */ diff --git a/feeds/ipq807x/qca-ssdk/src/src/adpt/cppe/adpt_cppe_portctrl.c b/feeds/ipq807x/qca-ssdk/src/src/adpt/cppe/adpt_cppe_portctrl.c deleted file mode 100755 index aad289da7..000000000 --- a/feeds/ipq807x/qca-ssdk/src/src/adpt/cppe/adpt_cppe_portctrl.c +++ /dev/null @@ -1,541 +0,0 @@ -/* - * Copyright (c) 2018-2019, The Linux Foundation. All rights reserved. - * Permission to use, copy, modify, and/or distribute this software for - * any purpose with or without fee is hereby granted, provided that the - * above copyright notice and this permission notice appear in all copies. - * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES - * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR - * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES - * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN - * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT - * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. - */ - - -/** - * @defgroup - * @{ - */ -#include "sw.h" -#include "hppe_global_reg.h" -#include "hppe_global.h" -#include "hppe_portctrl_reg.h" -#include "hppe_portctrl.h" -#include "cppe_portctrl_reg.h" -#include "cppe_portctrl.h" -#include "hppe_fdb_reg.h" -#include "hppe_fdb.h" -#include "cppe_loopback_reg.h" -#include "cppe_loopback.h" -#include "hsl.h" -#include "hsl_dev.h" -#include "hsl_phy.h" -#include "hsl_port_prop.h" -#include "hppe_init.h" -#include "adpt.h" -#include "adpt_hppe.h" -#include "adpt_cppe_portctrl.h" - -sw_error_t -_adpt_cppe_port_mux_mac_set(a_uint32_t dev_id, fal_port_t port_id, - a_uint32_t port_type) -{ - sw_error_t rv = SW_OK; - a_uint32_t mode0, mode1; - union cppe_port_mux_ctrl_u cppe_port_mux_ctrl; - - ADPT_DEV_ID_CHECK(dev_id); - memset(&cppe_port_mux_ctrl, 0, sizeof(cppe_port_mux_ctrl)); - - rv = cppe_port_mux_ctrl_get(dev_id, &cppe_port_mux_ctrl); - SW_RTN_ON_ERROR (rv); - - mode0 = ssdk_dt_global_get_mac_mode(dev_id, SSDK_UNIPHY_INSTANCE0); - mode1 = ssdk_dt_global_get_mac_mode(dev_id, SSDK_UNIPHY_INSTANCE1); - - switch (port_id) { - case SSDK_PHYSICAL_PORT3: - case SSDK_PHYSICAL_PORT4: - if (mode0 == PORT_WRAPPER_PSGMII) { - if (hsl_port_phyid_get(dev_id, - SSDK_PHYSICAL_PORT3) == MALIBU2PORT_PHY) { - cppe_port_mux_ctrl.bf.port3_pcs_sel = - CPPE_PORT3_PCS_SEL_PCS0_CHANNEL4; - cppe_port_mux_ctrl.bf.port4_pcs_sel = - CPPE_PORT4_PCS_SEL_PCS0_CHANNEL3; - } else { - cppe_port_mux_ctrl.bf.port3_pcs_sel = - CPPE_PORT3_PCS_SEL_PCS0_CHANNEL2; - cppe_port_mux_ctrl.bf.port4_pcs_sel = - CPPE_PORT4_PCS_SEL_PCS0_CHANNEL3; - } - } else if (mode0 == PORT_WRAPPER_QSGMII) { - cppe_port_mux_ctrl.bf.port3_pcs_sel = - CPPE_PORT3_PCS_SEL_PCS0_CHANNEL2; - cppe_port_mux_ctrl.bf.port4_pcs_sel = - CPPE_PORT4_PCS_SEL_PCS0_CHANNEL3; - } else if (mode0 == PORT_WRAPPER_SGMII_PLUS) { - cppe_port_mux_ctrl.bf.port3_pcs_sel = - CPPE_PORT3_PCS_SEL_PCS0_CHANNEL2; - cppe_port_mux_ctrl.bf.port4_pcs_sel = - CPPE_PORT4_PCS_SEL_PCS0_SGMIIPLUS; - } else if (mode0 ==PORT_WRAPPER_SGMII_CHANNEL0) { - if (hsl_port_prop_check(dev_id, SSDK_PHYSICAL_PORT4, - HSL_PP_EXCL_CPU) == A_TRUE) { - cppe_port_mux_ctrl.bf.port3_pcs_sel = - CPPE_PORT3_PCS_SEL_PCS0_CHANNEL2; - cppe_port_mux_ctrl.bf.port4_pcs_sel = - CPPE_PORT4_PCS_SEL_PCS0_SGMIIPLUS; - } else { - cppe_port_mux_ctrl.bf.port3_pcs_sel = - CPPE_PORT3_PCS_SEL_PCS0_CHANNEL2; - cppe_port_mux_ctrl.bf.port4_pcs_sel = - CPPE_PORT4_PCS_SEL_PCS0_CHANNEL3; - } - } else if ((mode0 == PORT_WRAPPER_SGMII_CHANNEL4) || - (mode0 == PORT_WRAPPER_SGMII0_RGMII4)) { - cppe_port_mux_ctrl.bf.port3_pcs_sel = - CPPE_PORT3_PCS_SEL_PCS0_CHANNEL2; - cppe_port_mux_ctrl.bf.port4_pcs_sel = - CPPE_PORT4_PCS_SEL_PCS0_CHANNEL3; - cppe_port_mux_ctrl.bf.port5_pcs_sel = - CPPE_PORT5_PCS_SEL_PCS0_CHANNEL4; - cppe_port_mux_ctrl.bf.port5_gmac_sel = - CPPE_PORT5_GMAC_SEL_GMAC; - } else if ((mode0 == PORT_WRAPPER_SGMII_CHANNEL1) || - (mode0 == PORT_WRAPPER_SGMII1_RGMII4)) { - cppe_port_mux_ctrl.bf.port3_pcs_sel = - CPPE_PORT3_PCS_SEL_PCS0_CHANNEL2; - cppe_port_mux_ctrl.bf.port4_pcs_sel = - CPPE_PORT4_PCS_SEL_PCS0_CHANNEL3; - } - break; - case SSDK_PHYSICAL_PORT5: - if (mode0 == PORT_WRAPPER_PSGMII) { - if (hsl_port_phyid_get(dev_id, - SSDK_PHYSICAL_PORT3) != MALIBU2PORT_PHY) { - cppe_port_mux_ctrl.bf.port5_pcs_sel = - CPPE_PORT5_PCS_SEL_PCS0_CHANNEL4; - cppe_port_mux_ctrl.bf.port5_gmac_sel = - CPPE_PORT5_GMAC_SEL_GMAC; - } - } - if ((mode1 == PORT_WRAPPER_SGMII_PLUS) || - (mode1 == PORT_WRAPPER_SGMII0_RGMII4) || - (mode1 == PORT_WRAPPER_SGMII_CHANNEL0) || - (mode1 == PORT_WRAPPER_SGMII_FIBER)) { - cppe_port_mux_ctrl.bf.port5_pcs_sel = - CPPE_PORT5_PCS_SEL_PCS1_CHANNEL0; - cppe_port_mux_ctrl.bf.port5_gmac_sel = - CPPE_PORT5_GMAC_SEL_GMAC; - } else if ((mode1 == PORT_WRAPPER_USXGMII) || - (mode1 == PORT_WRAPPER_10GBASE_R)) { - cppe_port_mux_ctrl.bf.port5_pcs_sel = - CPPE_PORT5_PCS_SEL_PCS1_CHANNEL0; - cppe_port_mux_ctrl.bf.port5_gmac_sel = - CPPE_PORT5_GMAC_SEL_XGMAC; - } - break; - default: - break; - } - - rv = cppe_port_mux_ctrl_set(dev_id, &cppe_port_mux_ctrl); - - return rv; -} - -sw_error_t -adpt_cppe_port_mru_set(a_uint32_t dev_id, fal_port_t port_id, - fal_mru_ctrl_t *ctrl) -{ - sw_error_t rv = SW_OK; - union cppe_mru_mtu_ctrl_tbl_u mru_mtu_ctrl_tbl; - - memset(&mru_mtu_ctrl_tbl, 0, sizeof(mru_mtu_ctrl_tbl)); - ADPT_DEV_ID_CHECK(dev_id); - ADPT_NULL_POINT_CHECK(ctrl); - - rv = cppe_mru_mtu_ctrl_tbl_get(dev_id, port_id, &mru_mtu_ctrl_tbl); - SW_RTN_ON_ERROR (rv); - - mru_mtu_ctrl_tbl.bf.mru = ctrl->mru_size; - mru_mtu_ctrl_tbl.bf.mru_cmd = (a_uint32_t)ctrl->action; - rv = cppe_mru_mtu_ctrl_tbl_set(dev_id, port_id, &mru_mtu_ctrl_tbl); - - return rv; -} - -sw_error_t -adpt_cppe_port_mru_get(a_uint32_t dev_id, fal_port_t port_id, - fal_mru_ctrl_t *ctrl) -{ - sw_error_t rv = SW_OK; - union cppe_mru_mtu_ctrl_tbl_u mru_mtu_ctrl_tbl; - - memset(&mru_mtu_ctrl_tbl, 0, sizeof(mru_mtu_ctrl_tbl)); - ADPT_DEV_ID_CHECK(dev_id); - ADPT_NULL_POINT_CHECK(ctrl); - - rv = cppe_mru_mtu_ctrl_tbl_get(dev_id, port_id, &mru_mtu_ctrl_tbl); - SW_RTN_ON_ERROR (rv); - - ctrl->mru_size = mru_mtu_ctrl_tbl.bf.mru; - ctrl->action = (fal_fwd_cmd_t)mru_mtu_ctrl_tbl.bf.mru_cmd; - - return SW_OK; -} - -#ifndef IN_PORTCONTROL_MINI -sw_error_t -adpt_cppe_port_mtu_set(a_uint32_t dev_id, fal_port_t port_id, - fal_mtu_ctrl_t *ctrl) -{ - sw_error_t rv = SW_OK; - union cppe_mru_mtu_ctrl_tbl_u mru_mtu_ctrl_tbl; - - memset(&mru_mtu_ctrl_tbl, 0, sizeof(mru_mtu_ctrl_tbl)); - ADPT_DEV_ID_CHECK(dev_id); - ADPT_NULL_POINT_CHECK(ctrl); - - rv = cppe_mru_mtu_ctrl_tbl_get(dev_id, port_id, &mru_mtu_ctrl_tbl); - SW_RTN_ON_ERROR (rv); - - mru_mtu_ctrl_tbl.bf.mtu = ctrl->mtu_size; - mru_mtu_ctrl_tbl.bf.mtu_cmd = (a_uint32_t)ctrl->action; - rv = cppe_mru_mtu_ctrl_tbl_set(dev_id, port_id, &mru_mtu_ctrl_tbl); - SW_RTN_ON_ERROR (rv); - - if ((port_id >= SSDK_PHYSICAL_PORT0) && (port_id <= SSDK_PHYSICAL_PORT7)) - { - rv = hppe_mc_mtu_ctrl_tbl_mtu_set(dev_id, port_id, ctrl->mtu_size); - SW_RTN_ON_ERROR (rv); - rv = hppe_mc_mtu_ctrl_tbl_mtu_cmd_set(dev_id, port_id, (a_uint32_t)ctrl->action); - SW_RTN_ON_ERROR (rv); - } - - return rv; -} - -sw_error_t -adpt_cppe_port_mtu_get(a_uint32_t dev_id, fal_port_t port_id, - fal_mtu_ctrl_t *ctrl) -{ - sw_error_t rv = SW_OK; - union cppe_mru_mtu_ctrl_tbl_u mru_mtu_ctrl_tbl; - - memset(&mru_mtu_ctrl_tbl, 0, sizeof(mru_mtu_ctrl_tbl)); - ADPT_DEV_ID_CHECK(dev_id); - ADPT_NULL_POINT_CHECK(ctrl); - - rv = cppe_mru_mtu_ctrl_tbl_get(dev_id, port_id, &mru_mtu_ctrl_tbl); - SW_RTN_ON_ERROR (rv); - - ctrl->mtu_size = mru_mtu_ctrl_tbl.bf.mtu; - ctrl->action = (fal_fwd_cmd_t)mru_mtu_ctrl_tbl.bf.mtu_cmd; - - return SW_OK; -} -#endif - -sw_error_t -adpt_cppe_port_to_channel_convert(a_uint32_t dev_id, a_uint32_t port_id, - a_uint32_t *channel_id) -{ - ADPT_DEV_ID_CHECK(dev_id); - ADPT_NULL_POINT_CHECK(channel_id); - - *channel_id = port_id; - - if (port_id == SSDK_PHYSICAL_PORT3) { - if (hsl_port_phyid_get(dev_id, - port_id) == MALIBU2PORT_PHY) { - *channel_id = SSDK_PHYSICAL_PORT5; - } - } - return SW_OK; -} - -#ifndef IN_PORTCONTROL_MINI -sw_error_t -adpt_cppe_port_source_filter_set(a_uint32_t dev_id, - fal_port_t port_id, a_bool_t enable) -{ - sw_error_t rv = SW_OK; - fal_src_filter_config_t src_filter_config; - - ADPT_DEV_ID_CHECK(dev_id); - - rv = adpt_cppe_port_source_filter_config_get(dev_id, - port_id, &src_filter_config); - SW_RTN_ON_ERROR(rv); - src_filter_config.src_filter_enable = enable; - rv = adpt_cppe_port_source_filter_config_set(dev_id, port_id, - &src_filter_config); - - return rv; -} - -sw_error_t -adpt_cppe_port_source_filter_get(a_uint32_t dev_id, - fal_port_t port_id, a_bool_t *enable) -{ - sw_error_t rv = SW_OK; - fal_src_filter_config_t src_filter_config; - - ADPT_DEV_ID_CHECK(dev_id); - ADPT_NULL_POINT_CHECK(enable); - - rv = adpt_cppe_port_source_filter_config_get(dev_id, port_id, - &src_filter_config); - SW_RTN_ON_ERROR(rv); - *enable = src_filter_config.src_filter_enable; - - return rv; -} - -sw_error_t -adpt_cppe_port_source_filter_config_set(a_uint32_t dev_id, - fal_port_t port_id, fal_src_filter_config_t *src_filter_config) -{ - sw_error_t rv = SW_OK; - a_bool_t src_filter_bypass; - - ADPT_DEV_ID_CHECK(dev_id); - ADPT_NULL_POINT_CHECK(src_filter_config); - - port_id = FAL_PORT_ID_VALUE(port_id); - if(src_filter_config->src_filter_enable == A_TRUE) - { - src_filter_bypass = A_FALSE; - } - else - { - src_filter_bypass = A_TRUE; - } - rv = cppe_mru_mtu_ctrl_tbl_source_filter_set(dev_id, port_id, - src_filter_bypass); - SW_RTN_ON_ERROR(rv); - rv = cppe_mru_mtu_ctrl_tbl_source_filter_mode_set(dev_id, port_id, - src_filter_config->src_filter_mode); - - return rv; -} - -sw_error_t -adpt_cppe_port_source_filter_config_get(a_uint32_t dev_id, - fal_port_t port_id, fal_src_filter_config_t *src_filter_config) -{ - sw_error_t rv = SW_OK; - a_bool_t src_filter_bypass; - - ADPT_DEV_ID_CHECK(dev_id); - ADPT_NULL_POINT_CHECK(src_filter_config); - - port_id = FAL_PORT_ID_VALUE(port_id); - rv = cppe_mru_mtu_ctrl_tbl_source_filter_get(dev_id, port_id, - &src_filter_bypass); - SW_RTN_ON_ERROR(rv); - if(src_filter_bypass == A_TRUE) - { - src_filter_config->src_filter_enable = A_FALSE; - } - else - { - src_filter_config->src_filter_enable = A_TRUE; - } - - rv = cppe_mru_mtu_ctrl_tbl_source_filter_mode_get(dev_id, - port_id, &(src_filter_config->src_filter_mode)); - - return rv; -} -#endif - -static a_uint32_t port_loopback_rate[SW_MAX_NR_DEV][CPPE_LOOPBACK_PORT_NUM] = { - {14}, - {14}, - {14}, -}; /* unit is Mpps*/ - -sw_error_t -adpt_cppe_switch_port_loopback_set(a_uint32_t dev_id, fal_port_t port_id, - fal_loopback_config_t *loopback_cfg) -{ - sw_error_t rv = SW_OK; - union lpbk_enable_u loopback_cfg_tbl; - union lpbk_pps_ctrl_u loopback_rate_ctrl_tbl; - union port_bridge_ctrl_u port_bridge_ctrl; - a_uint32_t physical_port = 0; - - if (port_id != SSDK_PHYSICAL_PORT6) { - return SW_BAD_PARAM; - } - - memset(&loopback_cfg_tbl, 0, sizeof(loopback_cfg_tbl)); - memset(&loopback_rate_ctrl_tbl, 0, sizeof(loopback_rate_ctrl_tbl)); - memset(&port_bridge_ctrl, 0, sizeof(port_bridge_ctrl)); - ADPT_DEV_ID_CHECK(dev_id); - ADPT_NULL_POINT_CHECK(loopback_cfg); - - physical_port = port_id; - rv = hppe_port_bridge_ctrl_get(dev_id, physical_port, &port_bridge_ctrl); - SW_RTN_ON_ERROR (rv); - port_bridge_ctrl.bf.txmac_en = loopback_cfg->enable; - - port_id = HPPE_TO_GMAC_PORT_ID(port_id); - rv = cppe_lpbk_pps_ctrl_get(dev_id, port_id, &loopback_rate_ctrl_tbl); - SW_RTN_ON_ERROR (rv); - - loopback_rate_ctrl_tbl.bf.lpbk_pps_threshold = - CPPE_LOOPBACK_PORT_RATE_FREQUENCY / loopback_cfg->loopback_rate; - - rv = cppe_lpbk_enable_get(dev_id, port_id, &loopback_cfg_tbl); - SW_RTN_ON_ERROR (rv); - loopback_cfg_tbl.bf.lpbk_en = loopback_cfg->enable; - loopback_cfg_tbl.bf.crc_strip_en = loopback_cfg->crc_stripped; - - if (loopback_cfg->enable == A_TRUE) { - rv = cppe_lpbk_pps_ctrl_set(dev_id, port_id, &loopback_rate_ctrl_tbl); - SW_RTN_ON_ERROR (rv); - rv = cppe_lpbk_enable_set(dev_id, port_id, &loopback_cfg_tbl); - SW_RTN_ON_ERROR (rv); - msleep(100); - rv = hppe_port_bridge_ctrl_set(dev_id, physical_port, - &port_bridge_ctrl); - SW_RTN_ON_ERROR (rv); - } else { - rv = hppe_port_bridge_ctrl_set(dev_id, physical_port, - &port_bridge_ctrl); - SW_RTN_ON_ERROR (rv); - msleep(100); - rv = cppe_lpbk_pps_ctrl_set(dev_id, port_id, &loopback_rate_ctrl_tbl); - SW_RTN_ON_ERROR (rv); - rv = cppe_lpbk_enable_set(dev_id, port_id, &loopback_cfg_tbl); - SW_RTN_ON_ERROR (rv); - } - - port_loopback_rate[dev_id][CPPE_LOOPBACK_PORT_NUM - 1] = - loopback_cfg->loopback_rate; - return rv; -} - -sw_error_t -adpt_cppe_switch_port_loopback_get(a_uint32_t dev_id, fal_port_t port_id, - fal_loopback_config_t *loopback_cfg) -{ - sw_error_t rv = SW_OK; - union lpbk_enable_u loopback_cfg_tbl; - union lpbk_pps_ctrl_u loopback_rate_ctrl_tbl; - - if (port_id != SSDK_PHYSICAL_PORT6) { - return SW_BAD_PARAM; - } - - memset(&loopback_cfg_tbl, 0, sizeof(loopback_cfg_tbl)); - memset(&loopback_rate_ctrl_tbl, 0, sizeof(loopback_rate_ctrl_tbl)); - ADPT_DEV_ID_CHECK(dev_id); - ADPT_NULL_POINT_CHECK(loopback_cfg); - - port_id = HPPE_TO_GMAC_PORT_ID(port_id); - rv = cppe_lpbk_enable_get(dev_id, port_id, &loopback_cfg_tbl); - SW_RTN_ON_ERROR (rv); - rv = cppe_lpbk_pps_ctrl_get(dev_id, port_id, &loopback_rate_ctrl_tbl); - SW_RTN_ON_ERROR (rv); - - loopback_cfg->enable = loopback_cfg_tbl.bf.lpbk_en; - loopback_cfg->crc_stripped = loopback_cfg_tbl.bf.crc_strip_en; - loopback_cfg->loopback_rate = - port_loopback_rate[dev_id][CPPE_LOOPBACK_PORT_NUM - 1]; - - return rv; -} - -sw_error_t -adpt_cppe_switch_port_loopback_flowctrl_set(a_uint32_t dev_id, - fal_port_t port_id, a_bool_t enable) -{ - sw_error_t rv = SW_OK; - union lpbk_enable_u loopback_cfg_tbl; - - memset(&loopback_cfg_tbl, 0, sizeof(loopback_cfg_tbl)); - ADPT_DEV_ID_CHECK(dev_id); - - if (port_id != SSDK_PHYSICAL_PORT6) { - return SW_BAD_PARAM; - } - - port_id = HPPE_TO_GMAC_PORT_ID(port_id); - rv = cppe_lpbk_enable_get(dev_id, port_id, &loopback_cfg_tbl); - SW_RTN_ON_ERROR (rv); - loopback_cfg_tbl.bf.flowctrl_en = enable; - rv = cppe_lpbk_enable_set(dev_id, port_id, &loopback_cfg_tbl); - - return rv; -} - -sw_error_t -adpt_cppe_switch_port_loopback_flowctrl_get(a_uint32_t dev_id, - fal_port_t port_id, a_bool_t *enable) -{ - sw_error_t rv = SW_OK; - union lpbk_enable_u loopback_cfg_tbl; - - memset(&loopback_cfg_tbl, 0, sizeof(loopback_cfg_tbl)); - ADPT_DEV_ID_CHECK(dev_id); - ADPT_NULL_POINT_CHECK(enable); - - if (port_id != SSDK_PHYSICAL_PORT6) { - return SW_BAD_PARAM; - } - - port_id = HPPE_TO_GMAC_PORT_ID(port_id); - rv = cppe_lpbk_enable_get(dev_id, port_id, &loopback_cfg_tbl); - SW_RTN_ON_ERROR (rv); - *enable = loopback_cfg_tbl.bf.flowctrl_en; - - return rv; -} - -sw_error_t -adpt_cppe_lpbk_max_frame_size_get(a_uint32_t dev_id, fal_port_t port_id, - a_uint32_t *max_frame) -{ - sw_error_t rv = SW_OK; - union lpbk_mac_junmo_size_u lpbk_mac_junmo_size; - - ADPT_DEV_ID_CHECK(dev_id); - ADPT_NULL_POINT_CHECK(max_frame); - port_id = HPPE_TO_GMAC_PORT_ID(port_id); - rv = cppe_lpbk_mac_junmo_size_get(dev_id, port_id, &lpbk_mac_junmo_size); - SW_RTN_ON_ERROR(rv); - *max_frame = lpbk_mac_junmo_size.bf.lpbk_mac_jumbo_size; - - return rv; -} - -sw_error_t -adpt_cppe_lpbk_max_frame_size_set(a_uint32_t dev_id, fal_port_t port_id, - a_uint32_t max_frame) -{ - sw_error_t rv = SW_OK; - union lpbk_mac_junmo_size_u lpbk_mac_junmo_size; - - ADPT_DEV_ID_CHECK(dev_id); - memset(&lpbk_mac_junmo_size, 0, sizeof(lpbk_mac_junmo_size)); - if (max_frame > SSDK_MAX_FRAME_SIZE) - { - return SW_BAD_VALUE; - } - port_id = HPPE_TO_GMAC_PORT_ID(port_id); - rv = cppe_lpbk_mac_junmo_size_get(dev_id, port_id, &lpbk_mac_junmo_size); - SW_RTN_ON_ERROR(rv); - lpbk_mac_junmo_size.bf.lpbk_mac_jumbo_size = max_frame; - rv = cppe_lpbk_mac_junmo_size_set(dev_id, port_id, &lpbk_mac_junmo_size); - - return rv; -} -/** - * @} - */ diff --git a/feeds/ipq807x/qca-ssdk/src/src/adpt/cppe/adpt_cppe_qm.c b/feeds/ipq807x/qca-ssdk/src/src/adpt/cppe/adpt_cppe_qm.c deleted file mode 100755 index d4317d513..000000000 --- a/feeds/ipq807x/qca-ssdk/src/src/adpt/cppe/adpt_cppe_qm.c +++ /dev/null @@ -1,60 +0,0 @@ -/* - * Copyright (c) 2018, The Linux Foundation. All rights reserved. - * Permission to use, copy, modify, and/or distribute this software for - * any purpose with or without fee is hereby granted, provided that the - * above copyright notice and this permission notice appear in all copies. - * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES - * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR - * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES - * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN - * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT - * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. - */ - - -/** - * @defgroup - * @{ - */ -#include "sw.h" -#include "fal_qos.h" -#include "cppe_portctrl_reg.h" -#include "cppe_portctrl.h" -#include "adpt.h" - -#ifndef IN_QM_MINI -sw_error_t -adpt_cppe_qm_port_source_profile_set( - a_uint32_t dev_id, fal_port_t port, a_uint32_t src_profile) -{ - union cppe_mru_mtu_ctrl_tbl_u mru_mtu_ctrl_tbl; - a_uint32_t index = FAL_PORT_ID_VALUE(port); - - ADPT_DEV_ID_CHECK(dev_id); - memset(&mru_mtu_ctrl_tbl, 0, sizeof(mru_mtu_ctrl_tbl)); - - - return cppe_mru_mtu_ctrl_tbl_src_profile_set(dev_id, index, - src_profile); -} - -sw_error_t -adpt_cppe_qm_port_source_profile_get( - a_uint32_t dev_id, fal_port_t port, a_uint32_t *src_profile) -{ - union cppe_mru_mtu_ctrl_tbl_u mru_mtu_ctrl_tbl; - a_uint32_t index = FAL_PORT_ID_VALUE(port); - - ADPT_DEV_ID_CHECK(dev_id); - ADPT_NULL_POINT_CHECK(src_profile); - memset(&mru_mtu_ctrl_tbl, 0, sizeof(mru_mtu_ctrl_tbl)); - - return cppe_mru_mtu_ctrl_tbl_src_profile_get(dev_id, index, - src_profile); -} -#endif - -/** - * @} - */ diff --git a/feeds/ipq807x/qca-ssdk/src/src/adpt/cppe/adpt_cppe_qos.c b/feeds/ipq807x/qca-ssdk/src/src/adpt/cppe/adpt_cppe_qos.c deleted file mode 100644 index c0e0209cd..000000000 --- a/feeds/ipq807x/qca-ssdk/src/src/adpt/cppe/adpt_cppe_qos.c +++ /dev/null @@ -1,289 +0,0 @@ -/* - * Copyright (c) 2018, The Linux Foundation. All rights reserved. - * Permission to use, copy, modify, and/or distribute this software for - * any purpose with or without fee is hereby granted, provided that the - * above copyright notice and this permission notice appear in all copies. - * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES - * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR - * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES - * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN - * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT - * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. - */ - - -/** - * @defgroup - * @{ - */ -#include "sw.h" -#include "fal_qos.h" -#include "cppe_portctrl_reg.h" -#include "cppe_portctrl.h" -#include "cppe_qos_reg.h" -#include "cppe_qos.h" -#include "adpt.h" - -static sw_error_t -adpt_cppe_qos_mapping_get(a_uint32_t dev_id, a_uint32_t index, - fal_qos_cosmap_t *cosmap) -{ - sw_error_t rv = SW_OK; - union qos_mapping_tbl_u qos_mapping_tbl; - - ADPT_DEV_ID_CHECK(dev_id); - ADPT_NULL_POINT_CHECK(cosmap); - - rv = cppe_qos_mapping_tbl_get(dev_id, index, &qos_mapping_tbl); - if (rv != SW_OK) - return rv; - - cosmap->internal_pcp = qos_mapping_tbl.bf.int_pcp; - cosmap->internal_dei = qos_mapping_tbl.bf.int_dei; - cosmap->internal_pri = qos_mapping_tbl.bf.int_pri; - cosmap->internal_dscp = qos_mapping_tbl.bf.int_dscp_tc; - cosmap->internal_dp = qos_mapping_tbl.bf.int_dp; - cosmap->dscp_mask = qos_mapping_tbl.bf.dscp_tc_mask; - cosmap->dscp_en = qos_mapping_tbl.bf.int_dscp_en; - cosmap->pcp_en = qos_mapping_tbl.bf.int_pcp_en; - cosmap->dei_en = qos_mapping_tbl.bf.int_dei_en; - cosmap->pri_en = qos_mapping_tbl.bf.int_pri_en; - cosmap->dp_en = qos_mapping_tbl.bf.int_dp_en; - cosmap->qos_prec = qos_mapping_tbl.bf.qos_res_prec_0 | - qos_mapping_tbl.bf.qos_res_prec_1 << 1; - - return SW_OK; -} - -static sw_error_t -adpt_cppe_qos_mapping_set(a_uint32_t dev_id, a_uint32_t index, - fal_qos_cosmap_t *cosmap) -{ - union qos_mapping_tbl_u qos_mapping_tbl; - - ADPT_DEV_ID_CHECK(dev_id); - ADPT_NULL_POINT_CHECK(cosmap); - - memset(&qos_mapping_tbl, 0, sizeof(qos_mapping_tbl)); - - qos_mapping_tbl.bf.int_pcp = cosmap->internal_pcp; - qos_mapping_tbl.bf.int_dei = cosmap->internal_dei; - qos_mapping_tbl.bf.int_pri = cosmap->internal_pri; - qos_mapping_tbl.bf.int_dscp_tc = cosmap->internal_dscp; - qos_mapping_tbl.bf.int_dp = cosmap->internal_dp; - qos_mapping_tbl.bf.dscp_tc_mask = cosmap->dscp_mask; - qos_mapping_tbl.bf.int_dscp_en = cosmap->dscp_en; - qos_mapping_tbl.bf.int_pcp_en = cosmap->pcp_en; - qos_mapping_tbl.bf.int_dei_en = cosmap->dei_en; - qos_mapping_tbl.bf.int_pri_en = cosmap->pri_en; - qos_mapping_tbl.bf.int_dp_en = cosmap->dp_en; - qos_mapping_tbl.bf.qos_res_prec_0 = cosmap->qos_prec & 1; - qos_mapping_tbl.bf.qos_res_prec_1 = (cosmap->qos_prec >> 1) & 3; - - return cppe_qos_mapping_tbl_set(dev_id, index, &qos_mapping_tbl); -} - -sw_error_t -adpt_cppe_qos_port_pri_set(a_uint32_t dev_id, fal_port_t port_id, - fal_qos_pri_precedence_t *pri) -{ - union cppe_mru_mtu_ctrl_tbl_u cppe_mru_mtu_ctrl; - - memset(&cppe_mru_mtu_ctrl, 0, sizeof(cppe_mru_mtu_ctrl)); - ADPT_DEV_ID_CHECK(dev_id); - ADPT_NULL_POINT_CHECK(pri); - - cppe_mru_mtu_ctrl_tbl_get(dev_id, port_id, &cppe_mru_mtu_ctrl); - - cppe_mru_mtu_ctrl.bf.pcp_res_prec = pri->pcp_pri; - cppe_mru_mtu_ctrl.bf.dscp_res_prec = pri->dscp_pri; - cppe_mru_mtu_ctrl.bf.preheader_res_prec = pri->preheader_pri; - cppe_mru_mtu_ctrl.bf.flow_res_prec = pri->flow_pri; - cppe_mru_mtu_ctrl.bf.pre_acl_res_prec = pri->acl_pri; - cppe_mru_mtu_ctrl.bf.post_acl_res_prec = pri->post_acl_pri; - cppe_mru_mtu_ctrl.bf.pcp_res_prec_force = pri->pcp_pri_force; - cppe_mru_mtu_ctrl.bf.dscp_res_prec_force = pri->dscp_pri_force; - - return cppe_mru_mtu_ctrl_tbl_set(dev_id, port_id, &cppe_mru_mtu_ctrl); -} - -sw_error_t -adpt_cppe_qos_port_pri_get(a_uint32_t dev_id, fal_port_t port_id, - fal_qos_pri_precedence_t *pri) -{ - sw_error_t rv = SW_OK; - union cppe_mru_mtu_ctrl_tbl_u cppe_mru_mtu_ctrl; - - memset(&cppe_mru_mtu_ctrl, 0, sizeof(cppe_mru_mtu_ctrl)); - ADPT_DEV_ID_CHECK(dev_id); - ADPT_NULL_POINT_CHECK(pri); - - rv = cppe_mru_mtu_ctrl_tbl_get(dev_id, port_id, &cppe_mru_mtu_ctrl); - if( rv != SW_OK ) - return rv; - - pri->pcp_pri = cppe_mru_mtu_ctrl.bf.pcp_res_prec; - pri->dscp_pri = cppe_mru_mtu_ctrl.bf.dscp_res_prec; - pri->preheader_pri = cppe_mru_mtu_ctrl.bf.preheader_res_prec; - pri->flow_pri = cppe_mru_mtu_ctrl.bf.flow_res_prec; - pri->acl_pri = cppe_mru_mtu_ctrl.bf.pre_acl_res_prec; - pri->post_acl_pri = cppe_mru_mtu_ctrl.bf.post_acl_res_prec; - pri->pcp_pri_force = cppe_mru_mtu_ctrl.bf.pcp_res_prec_force; - pri->dscp_pri_force = cppe_mru_mtu_ctrl.bf.dscp_res_prec_force; - - return SW_OK; -} - -sw_error_t -adpt_cppe_qos_cosmap_pcp_get(a_uint32_t dev_id, a_uint8_t group_id, - a_uint8_t pcp, - fal_qos_cosmap_t *cosmap) -{ - a_uint32_t index = 0; - - ADPT_DEV_ID_CHECK(dev_id); - ADPT_NULL_POINT_CHECK(cosmap); - - if (group_id >= QOS_MAPPING_TBL_MAX_GROUP) - return SW_BAD_PARAM; - - index = QOS_MAPPING_FLOW_TBL_MAX_ENTRY + - 2 * QOS_MAPPING_DSCP_TBL_MAX_ENTRY + - group_id * QOS_MAPPING_PCP_TBL_MAX_ENTRY + pcp; - - return adpt_cppe_qos_mapping_get(dev_id, index, cosmap); -} - -sw_error_t -adpt_cppe_qos_cosmap_pcp_set(a_uint32_t dev_id, a_uint8_t group_id, - a_uint8_t pcp, - fal_qos_cosmap_t *cosmap) -{ - a_uint32_t index = 0; - - ADPT_DEV_ID_CHECK(dev_id); - ADPT_NULL_POINT_CHECK(cosmap); - - if (group_id >= QOS_MAPPING_TBL_MAX_GROUP) - return SW_BAD_PARAM; - - index = QOS_MAPPING_FLOW_TBL_MAX_ENTRY + - 2 * QOS_MAPPING_DSCP_TBL_MAX_ENTRY + - group_id * QOS_MAPPING_PCP_TBL_MAX_ENTRY + pcp; - - return adpt_cppe_qos_mapping_set(dev_id, index, cosmap); -} - -sw_error_t -adpt_cppe_qos_cosmap_dscp_get(a_uint32_t dev_id, a_uint8_t group_id, - a_uint8_t dscp, - fal_qos_cosmap_t *cosmap) -{ - a_uint32_t index = 0; - - ADPT_DEV_ID_CHECK(dev_id); - ADPT_NULL_POINT_CHECK(cosmap); - - if (group_id >= QOS_MAPPING_TBL_MAX_GROUP) - return SW_BAD_PARAM; - - index = QOS_MAPPING_FLOW_TBL_MAX_ENTRY + - group_id * QOS_MAPPING_DSCP_TBL_MAX_ENTRY + - dscp; - - return adpt_cppe_qos_mapping_get(dev_id, index, cosmap); -} - -sw_error_t -adpt_cppe_qos_cosmap_flow_set(a_uint32_t dev_id, a_uint8_t group_id, - a_uint16_t flow, - fal_qos_cosmap_t *cosmap) -{ - ADPT_DEV_ID_CHECK(dev_id); - ADPT_NULL_POINT_CHECK(cosmap); - - if (flow >= QOS_MAPPING_FLOW_TBL_MAX_ENTRY) - return SW_BAD_PARAM; - - return adpt_cppe_qos_mapping_set(dev_id, flow, cosmap); -} - -sw_error_t -adpt_cppe_qos_port_group_set(a_uint32_t dev_id, fal_port_t port_id, - fal_qos_group_t *group) -{ - union cppe_mru_mtu_ctrl_tbl_u cppe_mru_mtu_ctrl; - - memset(&cppe_mru_mtu_ctrl, 0, sizeof(cppe_mru_mtu_ctrl)); - ADPT_DEV_ID_CHECK(dev_id); - ADPT_NULL_POINT_CHECK(group); - - cppe_mru_mtu_ctrl_tbl_get(dev_id, port_id, &cppe_mru_mtu_ctrl); - - cppe_mru_mtu_ctrl.bf.pcp_qos_group_id = group->pcp_group; - cppe_mru_mtu_ctrl.bf.dscp_qos_group_id = group->dscp_group; - - return cppe_mru_mtu_ctrl_tbl_set(dev_id, port_id, &cppe_mru_mtu_ctrl); -} - -sw_error_t -adpt_cppe_qos_cosmap_dscp_set(a_uint32_t dev_id, a_uint8_t group_id, - a_uint8_t dscp, - fal_qos_cosmap_t *cosmap) -{ - a_uint32_t index = 0; - - ADPT_DEV_ID_CHECK(dev_id); - ADPT_NULL_POINT_CHECK(cosmap); - - if (group_id >= QOS_MAPPING_TBL_MAX_GROUP) - return SW_BAD_PARAM; - - index = QOS_MAPPING_FLOW_TBL_MAX_ENTRY + - group_id * QOS_MAPPING_DSCP_TBL_MAX_ENTRY + - dscp; - - return adpt_cppe_qos_mapping_set(dev_id, index, cosmap); -} - -sw_error_t -adpt_cppe_qos_cosmap_flow_get(a_uint32_t dev_id, a_uint8_t group_id, - a_uint16_t flow, - fal_qos_cosmap_t *cosmap) -{ - ADPT_DEV_ID_CHECK(dev_id); - ADPT_NULL_POINT_CHECK(cosmap); - - if (flow >= QOS_MAPPING_FLOW_TBL_MAX_ENTRY) - return SW_BAD_PARAM; - - return adpt_cppe_qos_mapping_get(dev_id, flow, cosmap); -} - -sw_error_t -adpt_cppe_qos_port_group_get(a_uint32_t dev_id, fal_port_t port_id, - fal_qos_group_t *group) -{ - sw_error_t rv = SW_OK; - union cppe_mru_mtu_ctrl_tbl_u cppe_mru_mtu_ctrl; - - memset(&cppe_mru_mtu_ctrl, 0, sizeof(cppe_mru_mtu_ctrl)); - ADPT_DEV_ID_CHECK(dev_id); - ADPT_NULL_POINT_CHECK(group); - - rv = cppe_mru_mtu_ctrl_tbl_get(dev_id, port_id, &cppe_mru_mtu_ctrl); - if( rv != SW_OK ) - return rv; - - group->pcp_group = cppe_mru_mtu_ctrl.bf.pcp_qos_group_id; - group->dscp_group = cppe_mru_mtu_ctrl.bf.dscp_qos_group_id; - - return SW_OK; -} - - -/** - * @} - */ - diff --git a/feeds/ipq807x/qca-ssdk/src/src/adpt/cppe/adpt_cppe_uniphy.c b/feeds/ipq807x/qca-ssdk/src/src/adpt/cppe/adpt_cppe_uniphy.c deleted file mode 100755 index cf38c00fe..000000000 --- a/feeds/ipq807x/qca-ssdk/src/src/adpt/cppe/adpt_cppe_uniphy.c +++ /dev/null @@ -1,304 +0,0 @@ -/* - * Copyright (c) 2019, The Linux Foundation. All rights reserved. - * Permission to use, copy, modify, and/or distribute this software for - * any purpose with or without fee is hereby granted, provided that the - * above copyright notice and this permission notice appear in all copies. - * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES - * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR - * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES - * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN - * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT - * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. - */ - - -/** - * @defgroup - * @{ - */ -#include "sw.h" -#include "hppe_global_reg.h" -#include "hppe_global.h" -#include "hppe_uniphy_reg.h" -#include "hppe_uniphy.h" -#include "hppe_init.h" -#include "ssdk_init.h" -#include "ssdk_clk.h" -#include "adpt_hppe.h" -#include "adpt.h" -#include "hppe_reg_access.h" -#include "hsl_phy.h" -#include "adpt_cppe_portctrl.h" -#include "adpt_cppe_uniphy.h" - -static sw_error_t -__adpt_cppe_uniphy_reset(a_uint32_t dev_id, a_uint32_t uniphy_index) -{ - sw_error_t rv = SW_OK; - union pll_power_on_and_reset_u pll_software_reset; - - memset(&pll_software_reset, 0, sizeof(pll_software_reset)); - ADPT_DEV_ID_CHECK(dev_id); - - rv = hppe_uniphy_pll_reset_ctrl_get(dev_id, uniphy_index, - &pll_software_reset); - SW_RTN_ON_ERROR (rv); - pll_software_reset.bf.software_reset_analog_reset = 0; - rv = hppe_uniphy_pll_reset_ctrl_set(dev_id, uniphy_index, - &pll_software_reset); - SW_RTN_ON_ERROR (rv); - msleep(500); - pll_software_reset.bf.software_reset_analog_reset = 1; - rv = hppe_uniphy_pll_reset_ctrl_set(dev_id, uniphy_index, - &pll_software_reset); - SW_RTN_ON_ERROR (rv); - msleep(500); - - return SW_OK; -} - -static sw_error_t -__adpt_cppe_uniphy_port_disable(a_uint32_t dev_id, a_uint32_t uniphy_index, - a_uint32_t port_id) -{ - enum unphy_rst_type rst_type = 0; - - if (uniphy_index != SSDK_UNIPHY_INSTANCE0) { - return SW_BAD_VALUE; - } - - switch (port_id) { - case SSDK_PHYSICAL_PORT1: - rst_type = UNIPHY0_PORT1_DISABLE_E; - break; - case SSDK_PHYSICAL_PORT2: - rst_type = UNIPHY0_PORT2_DISABLE_E; - break; - case SSDK_PHYSICAL_PORT3: - rst_type = UNIPHY0_PORT3_DISABLE_E; - break; - case SSDK_PHYSICAL_PORT4: - rst_type = UNIPHY0_PORT4_DISABLE_E; - break; - case SSDK_PHYSICAL_PORT5: - rst_type = UNIPHY0_PORT5_DISABLE_E; - break; - default: - break; - } - ssdk_uniphy_reset(dev_id, rst_type, SSDK_RESET_ASSERT); - - return SW_OK; -} - -void -__adpt_cppe_gcc_uniphy_software_reset(a_uint32_t dev_id, - a_uint32_t uniphy_index) -{ - a_uint32_t phy_type = 0; - enum unphy_rst_type rst_type = 0; - - if (uniphy_index >= SSDK_UNIPHY_INSTANCE2) { - return; - } - - if (uniphy_index == SSDK_UNIPHY_INSTANCE0) { - phy_type = hsl_port_phyid_get(dev_id, SSDK_PHYSICAL_PORT4); - if (phy_type == MALIBU2PORT_PHY) { - rst_type = UNIPHY0_PORT_4_5_RESET_E; - } else if (phy_type == QCA8081_PHY_V1_1) { - rst_type = UNIPHY0_PORT_4_RESET_E; - } else { - rst_type = UNIPHY0_SOFT_RESET_E; - } - } else { - rst_type = UNIPHY1_SOFT_RESET_E; - } - - ssdk_uniphy_reset(dev_id, rst_type, SSDK_RESET_ASSERT); - - msleep(100); - - ssdk_uniphy_reset(dev_id, rst_type, SSDK_RESET_DEASSERT); - - return; -} - -sw_error_t -__adpt_cppe_uniphy_channel_selection_set(a_uint32_t dev_id, - a_uint32_t ch0_selection, a_uint32_t ch4_selection) -{ - sw_error_t rv = SW_OK; - union cppe_port_mux_ctrl_u cppe_port_mux_ctrl; - - memset(&cppe_port_mux_ctrl, 0, sizeof(cppe_port_mux_ctrl)); - ADPT_DEV_ID_CHECK(dev_id); - - rv = cppe_port_mux_ctrl_get(dev_id, &cppe_port_mux_ctrl); - SW_RTN_ON_ERROR (rv); - cppe_port_mux_ctrl.bf.pcs0_ch0_sel = ch0_selection; - cppe_port_mux_ctrl.bf.pcs0_ch4_sel = ch4_selection; - rv = cppe_port_mux_ctrl_set(dev_id, &cppe_port_mux_ctrl); - SW_RTN_ON_ERROR (rv); - - return rv; -} - -static sw_error_t -__adpt_cppe_uniphy_mode_ctrl_set(a_uint32_t dev_id, - a_uint32_t uniphy_index, a_uint32_t mode) -{ - sw_error_t rv = SW_OK; - union uniphy_mode_ctrl_u uniphy_mode_ctrl; - - memset(&uniphy_mode_ctrl, 0, sizeof(uniphy_mode_ctrl)); - - /* configure uniphy mode ctrl to psgmii/sgmii/sgmiiplus */ - rv = hppe_uniphy_mode_ctrl_get(dev_id, uniphy_index, &uniphy_mode_ctrl); - SW_RTN_ON_ERROR (rv); - uniphy_mode_ctrl.bf.newaddedfromhere_ch0_autoneg_mode = - UNIPHY_ATHEROS_NEGOTIATION; - if (mode == PORT_WRAPPER_PSGMII) { - uniphy_mode_ctrl.bf.newaddedfromhere_ch0_psgmii_qsgmii = - UNIPHY_CH0_PSGMII_MODE; - uniphy_mode_ctrl.bf.newaddedfromhere_sg_mode = - UNIPHY_SGMII_MODE_DISABLE; - uniphy_mode_ctrl.bf.newaddedfromhere_sgplus_mode = - UNIPHY_SGMIIPLUS_MODE_DISABLE; - } else if (mode == PORT_WRAPPER_SGMII_CHANNEL0) { - uniphy_mode_ctrl.bf.newaddedfromhere_ch0_psgmii_qsgmii = - UNIPHY_CH0_QSGMII_SGMII_MODE; - uniphy_mode_ctrl.bf.newaddedfromhere_sg_mode = - UNIPHY_SGMII_MODE_ENABLE; - uniphy_mode_ctrl.bf.newaddedfromhere_sgplus_mode = - UNIPHY_SGMIIPLUS_MODE_DISABLE; - } else { - uniphy_mode_ctrl.bf.newaddedfromhere_ch0_psgmii_qsgmii = - UNIPHY_CH0_QSGMII_SGMII_MODE; - uniphy_mode_ctrl.bf.newaddedfromhere_sg_mode = - UNIPHY_SGMII_MODE_DISABLE; - uniphy_mode_ctrl.bf.newaddedfromhere_sgplus_mode = - UNIPHY_SGMIIPLUS_MODE_ENABLE; - } - uniphy_mode_ctrl.bf.newaddedfromhere_ch0_qsgmii_sgmii = - UNIPHY_CH0_SGMII_MODE; - uniphy_mode_ctrl.bf.newaddedfromhere_xpcs_mode = - UNIPHY_XPCS_MODE_DISABLE; - rv = hppe_uniphy_mode_ctrl_set(dev_id, uniphy_index, &uniphy_mode_ctrl); - - return rv; -} - -sw_error_t -__adpt_cppe_uniphy_mode_set(a_uint32_t dev_id, - a_uint32_t uniphy_index, a_uint32_t mode) -{ - sw_error_t rv = SW_OK; - a_uint32_t i = 0; - union uniphy_misc2_phy_mode_u uniphy_misc2_phy_mode; - - memset(&uniphy_misc2_phy_mode, 0, sizeof(uniphy_misc2_phy_mode)); - - ADPT_DEV_ID_CHECK(dev_id); - - if (uniphy_index != SSDK_UNIPHY_INSTANCE0) { - SSDK_ERROR("uniphy index is %d\n", uniphy_index); - return SW_BAD_VALUE; - } - - if ((mode == PORT_WRAPPER_SGMII_CHANNEL0) || - (mode == PORT_WRAPPER_SGMII_PLUS)) { - /*set the PHY mode to SGMII or SGMIIPLUS*/ - rv = hppe_uniphy_phy_mode_ctrl_get(dev_id, uniphy_index, - &uniphy_misc2_phy_mode); - SW_RTN_ON_ERROR (rv); - if (mode == PORT_WRAPPER_SGMII_CHANNEL0) { - uniphy_misc2_phy_mode.bf.phy_mode = - UNIPHY_PHY_SGMII_MODE; - } else { - uniphy_misc2_phy_mode.bf.phy_mode = - UNIPHY_PHY_SGMIIPLUS_MODE; - } - rv = hppe_uniphy_phy_mode_ctrl_set(dev_id, uniphy_index, - &uniphy_misc2_phy_mode); - SW_RTN_ON_ERROR (rv); - - /*reset uniphy*/ - rv = __adpt_cppe_uniphy_reset(dev_id, uniphy_index); - SW_RTN_ON_ERROR (rv); - } - /* keep xpcs to reset status */ - __adpt_hppe_gcc_uniphy_xpcs_reset(dev_id, uniphy_index, A_TRUE); - - SW_RTN_ON_ERROR (rv); - if (mode == PORT_WRAPPER_PSGMII) { - /* disable GCC_UNIPHY0_MISC port 1, 2 and 3*/ - for (i = SSDK_PHYSICAL_PORT1; i < SSDK_PHYSICAL_PORT4; i++) { - rv = __adpt_cppe_uniphy_port_disable(dev_id, uniphy_index, i); - SW_RTN_ON_ERROR (rv); - } - - /* disable instance0 port 4 and 5 clock */ - for (i = SSDK_PHYSICAL_PORT4; i < SSDK_PHYSICAL_PORT6; i++) { - qca_gcc_uniphy_port_clock_set(dev_id, uniphy_index, - i, A_FALSE); - } - rv = __adpt_cppe_uniphy_channel_selection_set(dev_id, - CPPE_PCS0_CHANNEL0_SEL_PSGMII, - CPPE_PCS0_CHANNEL4_SEL_PORT3_CLOCK); - SW_RTN_ON_ERROR (rv); - } else { - /* disable GCC_UNIPHY0_MISC port 2, 3 and 5*/ - for (i = SSDK_PHYSICAL_PORT1; i < SSDK_PHYSICAL_PORT6; i++) { - if ((i == SSDK_PHYSICAL_PORT1) || (i == SSDK_PHYSICAL_PORT4)) { - continue; - } - rv = __adpt_cppe_uniphy_port_disable(dev_id, uniphy_index, i); - SW_RTN_ON_ERROR (rv); - } - /* disable instance0 port 4 clock */ - qca_gcc_uniphy_port_clock_set(dev_id, uniphy_index, - SSDK_PHYSICAL_PORT4, A_FALSE); - rv = __adpt_cppe_uniphy_channel_selection_set(dev_id, - CPPE_PCS0_CHANNEL0_SEL_SGMIIPLUS, - CPPE_PCS0_CHANNEL4_SEL_PORT5_CLOCK); - SW_RTN_ON_ERROR (rv); - } - - rv = __adpt_cppe_uniphy_mode_ctrl_set(dev_id, uniphy_index, mode); - SW_RTN_ON_ERROR (rv); - - __adpt_cppe_gcc_uniphy_software_reset(dev_id, uniphy_index); - - /* wait uniphy calibration done */ - rv = __adpt_hppe_uniphy_calibrate(dev_id, uniphy_index); - SW_RTN_ON_ERROR (rv); - - if (mode == PORT_WRAPPER_PSGMII) { - rv = hsl_port_phy_serdes_reset(dev_id); - SW_RTN_ON_ERROR (rv); - /* enable instance0 clock */ - for (i = SSDK_PHYSICAL_PORT4; i < SSDK_PHYSICAL_PORT6; i++) { - qca_gcc_uniphy_port_clock_set(dev_id, uniphy_index, - i, A_TRUE); - } - } else { - /* enable instance clock */ - qca_gcc_uniphy_port_clock_set(dev_id, uniphy_index, - SSDK_PHYSICAL_PORT4, A_TRUE); - } - if (mode == PORT_WRAPPER_PSGMII) { - SSDK_DEBUG("cypress uniphy %d psgmii configuration is done!\n", uniphy_index); - } else if (mode == PORT_WRAPPER_SGMII_CHANNEL0) { - SSDK_DEBUG("cypress uniphy %d sgmii configuration is done!\n", uniphy_index); - } else { - SSDK_DEBUG("cypress uniphy %d sgmiiplus configuration is done!\n", uniphy_index); - } - - return rv; -} - -/** - * @} - */ diff --git a/feeds/ipq807x/qca-ssdk/src/src/adpt/hppe/Makefile b/feeds/ipq807x/qca-ssdk/src/src/adpt/hppe/Makefile deleted file mode 100755 index 8a81feed7..000000000 --- a/feeds/ipq807x/qca-ssdk/src/src/adpt/hppe/Makefile +++ /dev/null @@ -1,112 +0,0 @@ -LOC_DIR=src/adpt/hppe -LIB=ADPT - -include $(PRJ_PATH)/make/config.mk - -SRC_LIST= - -ifeq (TRUE, $(IN_FDB)) - SRC_LIST += adpt_hppe_fdb.c -endif - -ifeq (TRUE, $(IN_MIB)) - SRC_LIST += adpt_hppe_mib.c -endif - -ifeq (TRUE, $(IN_STP)) - SRC_LIST += adpt_hppe_stp.c -endif - -ifeq (TRUE, $(IN_VSI)) - SRC_LIST += adpt_hppe_vsi.c -endif - -ifeq (TRUE, $(IN_PORTCONTROL)) - SRC_LIST += adpt_hppe_portctrl.c -endif - -ifeq (TRUE, $(IN_MIRROR)) - SRC_LIST += adpt_hppe_mirror.c -endif - -ifeq (TRUE, $(IN_TRUNK)) - SRC_LIST += adpt_hppe_trunk.c -endif - -ifeq (TRUE, $(IN_IP)) - SRC_LIST += adpt_hppe_ip.c -endif - -ifeq (TRUE, $(IN_FLOW)) - SRC_LIST += adpt_hppe_flow.c -endif - -ifeq (TRUE, $(IN_QM)) - SRC_LIST += adpt_hppe_qm.c -endif - -ifeq (TRUE, $(IN_PPPOE)) - SRC_LIST += adpt_hppe_pppoe.c -endif - -ifeq (TRUE, $(IN_PORTVLAN)) - SRC_LIST += adpt_hppe_portvlan.c -endif - -ifeq (TRUE, $(IN_CTRLPKT)) - SRC_LIST += adpt_hppe_ctrlpkt.c -endif - -ifeq (TRUE, $(IN_SERVCODE)) - SRC_LIST += adpt_hppe_servcode.c -endif - -ifeq (TRUE, $(IN_RSS_HASH)) - SRC_LIST += adpt_hppe_rss_hash.c -endif - -ifeq (TRUE, $(IN_SEC)) - SRC_LIST += adpt_hppe_sec.c -endif - -ifeq (TRUE, $(IN_ACL)) - SRC_LIST += adpt_hppe_acl.c -endif - -ifeq (TRUE, $(IN_QOS)) - SRC_LIST += adpt_hppe_qos.c -endif - -ifeq (TRUE, $(IN_BM)) - SRC_LIST += adpt_hppe_bm.c -endif - -ifeq (TRUE, $(IN_SHAPER)) - SRC_LIST += adpt_hppe_shaper.c -endif - -ifeq (TRUE, $(IN_POLICER)) - SRC_LIST += adpt_hppe_policer.c -endif - -ifeq (TRUE, $(IN_MISC)) - SRC_LIST += adpt_hppe_misc.c -endif - -ifeq (TRUE, $(IN_UNIPHY)) - SRC_LIST += adpt_hppe_uniphy.c -endif - -ifeq (TRUE, $(IN_PTP)) - SRC_LIST += adpt_hppe_ptp.c -endif - -ifeq (, $(findstring HPPE, $(SUPPORT_CHIP))) - SRC_LIST= -endif - -include $(PRJ_PATH)/make/components.mk -include $(PRJ_PATH)/make/defs.mk -include $(PRJ_PATH)/make/target.mk - -all: dep obj diff --git a/feeds/ipq807x/qca-ssdk/src/src/adpt/hppe/adpt_hppe_acl.c b/feeds/ipq807x/qca-ssdk/src/src/adpt/hppe/adpt_hppe_acl.c deleted file mode 100755 index b0e682cde..000000000 --- a/feeds/ipq807x/qca-ssdk/src/src/adpt/hppe/adpt_hppe_acl.c +++ /dev/null @@ -1,4013 +0,0 @@ -/* - * Copyright (c) 2016-2018, The Linux Foundation. All rights reserved. - * Permission to use, copy, modify, and/or distribute this software for - * any purpose with or without fee is hereby granted, provided that the - * above copyright notice and this permission notice appear in all copies. - * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES - * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR - * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES - * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN - * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT - * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. - */ - - -/** - * @defgroup - * @{ - */ -#include "sw.h" -#include "adpt.h" -#include "adpt_hppe.h" -#include "hppe_acl_reg.h" -#include "hppe_acl.h" -#include - -#define ADPT_ACL_HPPE_MAC_DA_RULE 0 -#define ADPT_ACL_HPPE_MAC_SA_RULE 1 -#define ADPT_ACL_HPPE_VLAN_RULE 2 -#define ADPT_ACL_HPPE_L2_MISC_RULE 3 -#define ADPT_ACL_HPPE_IPV4_DIP_RULE 4 -#define ADPT_ACL_HPPE_IPV4_SIP_RULE 5 -#define ADPT_ACL_HPPE_IPV6_DIP0_RULE 6 -#define ADPT_ACL_HPPE_IPV6_DIP1_RULE 7 -#define ADPT_ACL_HPPE_IPV6_DIP2_RULE 8 -#define ADPT_ACL_HPPE_IPV6_SIP0_RULE 9 -#define ADPT_ACL_HPPE_IPV6_SIP1_RULE 10 -#define ADPT_ACL_HPPE_IPV6_SIP2_RULE 11 -#define ADPT_ACL_HPPE_IPMISC_RULE 12 -#define ADPT_ACL_HPPE_UDF0_RULE 13 -#define ADPT_ACL_HPPE_UDF1_RULE 14 -#define ADPT_ACL_HPPE_RULE_TYPE_NUM 15 - - -#define ADPT_ACL_SW_LIST_NUM 512 -#define ADPT_ACL_HW_LIST_NUM 64 -#define ADPT_ACL_RULE_NUM_PER_LIST 8 /* can change this MACRO to support more rules per ACL list */ -#define ADPT_ACL_ENTRY_NUM_PER_LIST 8 - -typedef struct{ - struct list_head list; - a_uint16_t rule_id; - a_uint8_t rule_type; - a_uint8_t rule_hw_entry; - a_uint8_t rule_hw_list_id; - a_uint8_t ext1_val; - a_uint8_t ext2_val; - a_uint8_t ext4_val; -}ADPT_HPPE_ACL_SW_RULE; - -typedef struct{ - struct list_head list; - struct list_head list_sw_rule; - a_uint32_t list_pri; - a_uint16_t list_id; -}ADPT_HPPE_ACL_SW_LIST; - -typedef struct{ - struct list_head list_sw_list; -}ADPT_HPPE_ACL_SW_LIST_HEAD; - -typedef struct{ - a_bool_t hw_list_valid; - a_uint8_t hw_list_id; - a_uint8_t free_hw_entry_bitmap; - a_uint8_t free_hw_entry_count; -}ADPT_HPPE_ACL_HW_LIST; - -typedef struct{ - a_uint8_t mac[6]; - a_uint32_t is_ip:1; - a_uint32_t is_ipv6:1; - a_uint32_t is_ethernet:1; - a_uint32_t is_snap:1; - a_uint32_t is_fake_mac_header:1; -}ADPT_HPPE_ACL_MAC_RULE; -typedef struct{ - a_uint8_t mac_mask[6]; - a_uint32_t is_ip_mask:1; - a_uint32_t is_ipv6_mask:1; - a_uint32_t is_ethernet_mask:1; - a_uint32_t is_snap_mask:1; - a_uint32_t is_fake_mac_header_mask:1; -}ADPT_HPPE_ACL_MAC_RULE_MASK; - -typedef struct{ - a_uint32_t cvid:12;/*it is min cvid when range is enable*/ - a_uint32_t reserved:4; - a_uint32_t cpcp:3; - a_uint32_t cdei:1; - a_uint32_t svid:12; - a_uint32_t spcp:3; - a_uint32_t sdei:1; - a_uint32_t ctag_fmt:3; - a_uint32_t stag_fmt:3; - a_uint32_t vsi:5; - a_uint32_t vsi_valid:1; - a_uint32_t is_ip:1; - a_uint32_t is_ipv6:1; - a_uint32_t is_ethernet:1; - a_uint32_t is_snap:1; - a_uint32_t is_fake_mac_header:1; -}ADPT_HPPE_ACL_VLAN_RULE; - -typedef struct{ - a_uint32_t cvid_mask:12;/*it is max cvid when range is enable*/ - a_uint32_t reserved:4; - a_uint32_t cpcp_mask:3; - a_uint32_t cdei_mask:1; - a_uint32_t svid_mask:12; - a_uint32_t spcp_mask:3; - a_uint32_t sdei_mask:1; - a_uint32_t ctag_fmt_mask:3; - a_uint32_t stag_fmt_mask:3; - a_uint32_t vsi_mask:5; - a_uint32_t vsi_valid_mask:1; - a_uint32_t is_ip_mask:1; - a_uint32_t is_ipv6_mask:1; - a_uint32_t is_ethernet_mask:1; - a_uint32_t is_snap_mask:1; - a_uint32_t is_fake_mac_header_mask:1; -}ADPT_HPPE_ACL_VLAN_RULE_MASK; - -typedef struct{ - a_uint32_t svid:12;/*it is min svid when range is enable*/ - a_uint32_t reserved:4; - a_uint32_t l2prot:16; - a_uint32_t pppoe_sessionid:16; - a_uint32_t is_ip:1; - a_uint32_t is_ipv6:1; - a_uint32_t is_ethernet:1; - a_uint32_t is_snap:1; - a_uint32_t is_fake_mac_header:1; -}ADPT_HPPE_ACL_L2MISC_RULE; - -typedef struct{ - a_uint32_t svid_mask:12;/*it is max svid when range is enable*/ - a_uint32_t reserved:4; - a_uint32_t l2prot_mask:16; - a_uint32_t pppoe_sessionid_mask:16; - a_uint32_t is_ip_mask:1; - a_uint32_t is_ipv6_mask:1; - a_uint32_t is_ethernet_mask:1; - a_uint32_t is_snap_mask:1; - a_uint32_t is_fake_mac_header_mask:1; -}ADPT_HPPE_ACL_L2MISC_RULE_MASK; - -typedef struct{ - a_uint32_t l4_port:16;/*it is min dport when range is enable*/ - a_uint32_t ip_0:16; - a_uint32_t ip_1:16; - a_uint32_t l3_fragment:1; - a_uint32_t l3_packet_type:3; - a_uint32_t is_ip:1; - a_uint32_t reserved:11; -}ADPT_HPPE_ACL_IPV4_RULE; - -typedef struct{ - a_uint32_t l4_port_mask:16;/*it is min dport when range is enable*/ - a_uint32_t ip_mask_0:16; - a_uint32_t ip_mask_1:16; - a_uint32_t l3_fragment_mask:1; - a_uint32_t l3_packet_type_mask:3; - a_uint32_t is_ip_mask:1; - a_uint32_t reserved:11; -}ADPT_HPPE_ACL_IPV4_RULE_MASK; - -typedef struct{ - a_uint32_t udf0:16; - a_uint32_t udf1:16; - a_uint32_t udf2:16; - a_uint32_t udf0_valid:1; - a_uint32_t udf1_valid:1; - a_uint32_t udf2_valid:1; - a_uint32_t is_ipv6:1; - a_uint32_t is_ip:1; -}ADPT_HPPE_ACL_UDF_RULE; - -typedef struct{ - a_uint32_t udf0_mask:16; - a_uint32_t udf1_mask:16; - a_uint32_t udf2_mask:16; - a_uint32_t udf0_valid:1; - a_uint32_t udf1_valid:1; - a_uint32_t udf2_valid:1; - a_uint32_t is_ipv6:1; - a_uint32_t is_ip:1; -}ADPT_HPPE_ACL_UDF_RULE_MASK; - - -typedef struct{ - a_uint32_t ip_port:16; /*it is port when DIP_2_RULE or SIP_2_RULE*/ - a_uint32_t ip_ext_1:16; - a_uint32_t ip_ext_2:16; - a_uint32_t l3_fragment:1; - a_uint32_t l3_packet_type:3; - a_uint32_t reserved:1; -}ADPT_HPPE_ACL_IPV6_RULE; - -typedef struct{ - a_uint32_t ip_port_mask:16; /*it is port when DIP_2_RULE or SIP_2_RULE*/ - a_uint32_t ip_ext_1_mask:16; - a_uint32_t ip_ext_2_mask:16; - a_uint32_t l3_fragment_mask:1; - a_uint32_t l3_packet_type_mask:3; - a_uint32_t reserved:1; -}ADPT_HPPE_ACL_IPV6_RULE_MASK; - -typedef struct{ - a_uint32_t l3_length:16;/*it is min length when range is enable*/ - a_uint32_t l3_prot:8; /*ipv4 protocol or ipv6 next header*/ - a_uint32_t l3_dscp_tc:8; - a_uint32_t first_fragment:1; - a_uint32_t tcp_flags:6; - a_uint32_t ipv4_option_state:1; - a_uint32_t l3_ttl:2; /*ipv4 ttl, ipv6 hop limit*/ - a_uint32_t ah_header:1; - a_uint32_t esp_header:1; - a_uint32_t mobility_header:1; - a_uint32_t fragment_header:1; - a_uint32_t other_header:1; - a_uint32_t reserved0:1; - a_uint32_t l3_fragment:1; - a_uint32_t is_ipv6:1; - a_uint32_t reserved1:3; -}ADPT_HPPE_ACL_IPMISC_RULE; - -typedef struct{ - a_uint32_t l3_length_mask:16;/*it is max length when range is enable*/ - a_uint32_t l3_prot_mask:8; /*ipv4 protocol or ipv6 next header*/ - a_uint32_t l3_dscp_tc_mask:8; - a_uint32_t first_fragment_mask:1; - a_uint32_t tcp_flags_mask:6; - a_uint32_t ipv4_option_state_mask:1; - a_uint32_t l3_ttl_mask:2; /*ipv4 ttl, ipv6 hop limit*/ - a_uint32_t ah_header_mask:1; - a_uint32_t esp_header_mask:1; - a_uint32_t mobility_header_mask:1; - a_uint32_t fragment_header_mask:1; - a_uint32_t other_header_mask:1; - a_uint32_t reserved0:1; - a_uint32_t l3_fragment_mask:1; - a_uint32_t is_ipv6_mask:1; - a_uint32_t reserved1:3; -}ADPT_HPPE_ACL_IPMISC_RULE_MASK; - -static ADPT_HPPE_ACL_SW_LIST_HEAD g_acl_sw_list[SW_MAX_NR_DEV]; -static ADPT_HPPE_ACL_HW_LIST g_acl_hw_list[SW_MAX_NR_DEV][ADPT_ACL_HW_LIST_NUM]; -static aos_lock_t hppe_acl_lock[SW_MAX_NR_DEV]; - -const a_uint8_t s_acl_ext2[7][2] = { - {0,1},{2,3},{4,5},{6,7},{0,2},{4,6},{0,4} -}; -typedef struct -{ - a_uint8_t num; - a_uint8_t ext_1; - a_uint8_t ext_2; - a_uint8_t ext_4; - a_uint8_t entries; -}ADPT_HPPE_ACL_ENTRY_EXTEND_INFO; -const ADPT_HPPE_ACL_ENTRY_EXTEND_INFO s_acl_entries[] = { - /*num ext_1 ext_2 ext_4 entries*/ - {1, 0, 0, 0, 0x2}, - {1, 0, 0, 0, 0x8}, - {1, 0, 0, 0, 0x20}, - {1, 0, 0, 0, 0x80}, - {1, 0, 0, 0, 0x1}, - {1, 0, 0, 0, 0x4}, - {1, 0, 0, 0, 0x10}, - {1, 0, 0, 0, 0x40}, - {2, 0x1, 0, 0, 0x3}, - {2, 0x2, 0, 0, 0xc}, - {2, 0x4, 0, 0, 0x30}, - {2, 0x8, 0, 0, 0xc0}, - {2, 0, 0x1, 0, 0x5}, - {2, 0, 0x2, 0, 0x50}, - {2, 0, 0, 0x1, 0x11}, - {3, 0x1, 0x1, 0x0, 0x7}, - {3, 0x1, 0x0, 0x1, 0x13}, - {3, 0x2, 0x1, 0x0, 0xd}, - {3, 0x4, 0x2, 0x0, 0x70}, - {3, 0x4, 0x0, 0x1, 0x31}, - {3, 0x8, 0x2, 0x0, 0xd0}, - {3, 0x0, 0x1, 0x1, 0x15}, - {3, 0x0, 0x2, 0x1, 0x51}, - {4, 0x3, 0x1, 0x0, 0xf}, - {4, 0x5, 0x0, 0x1, 0x33}, - {4, 0x2, 0x1, 0x1, 0x1d}, - {4, 0xc, 0x2, 0x0, 0xf0}, - {4, 0x4, 0x1, 0x1, 0x35}, - {4, 0x8, 0x2, 0x1, 0xd1}, - {4, 0x0, 0x3, 0x1, 0x55}, - {5, 0x3, 0x1, 0x1, 0x1f}, - {5, 0x6, 0x1, 0x1, 0x3d}, - {5, 0xc, 0x2, 0x1, 0xf1}, - {5, 0x8, 0x3, 0x1, 0xd5}, - {6, 0x7, 0x1, 0x1, 0x3f}, - {6, 0x6, 0x3, 0x1, 0x7d}, - {6, 0xc, 0x3, 0x1, 0xf5}, - {7, 0x7, 0x3, 0x1, 0x7f}, - {7, 0xe, 0x3, 0x1, 0xfd}, - {8, 0xf, 0x3, 0x1, 0xff}, -}; - -static void _adpt_acl_reg_dump(a_uint8_t *reg, a_uint32_t len) -{ - a_int32_t i = 0; - - for(i = 0; i < len; i++) - { - printk(KERN_CONT "%02x ", reg[i]); - if((i+1)%32 == 0 || (i == len-1)) - printk(KERN_CONT "\n"); - } - - return; -} - -/*type = 0, count all; type = 1 count odd; type = 2 count even*/ -static a_uint32_t _acl_bits_count(a_uint32_t bits, a_uint32_t max, a_uint32_t type) -{ - a_uint32_t i = 0, count = 0; - while(i < max) - { - if((bits >> i) &0x1) - { - if(type == 1) - { - if(i%2!=0) - count++; - } - else if(type == 2) - { - if(i%2==0) - count++; - } - else - count++; - } - i++; - } - return count; -} - -/*type = 0, count all; type = 1 count odd; type = 2 count even*/ -static a_uint32_t _acl_bit_index(a_uint32_t bits, a_uint32_t max, a_uint32_t type) -{ - a_uint32_t i = 0; - while(i < max) - { - if((bits >> i) &0x1) - { - if(type == 1)/*odd*/ - { - if(i%2!=0) - break; - } - else if(type == 2)/*even*/ - { - if(i%2==0) - break; - } - else - break; - } - i++; - } - if(i>12)&0x3) -#define HPPE_ACL_DEST_VALUE(dest) ((dest)&0xfff) - -static a_uint32_t _adpt_hppe_acl_srctype_to_hw(fal_acl_bind_obj_t obj_t) -{ - a_uint32_t src_type = HPPE_ACL_TYPE_INVALID; - - switch(obj_t) - { - case FAL_ACL_BIND_PORTBITMAP: - src_type = HPPE_ACL_TYPE_PORTBITMAP; - break; - case FAL_ACL_BIND_PORT: - src_type = HPPE_ACL_TYPE_PORT; - break; - case FAL_ACL_BIND_SERVICE_CODE: - src_type = HPPE_ACL_TYPE_SERVICE_CODE; - break; - case FAL_ACL_BIND_L3_IF: - src_type = HPPE_ACL_TYPE_L3_IF; - break; - } - return src_type; -} - -static sw_error_t -_adpt_hppe_acl_rule_bind(a_uint32_t dev_id, a_uint32_t list_id, ADPT_HPPE_ACL_SW_RULE *rule_entry, - fal_acl_direc_t direc, fal_acl_bind_obj_t obj_t, a_uint32_t obj_idx) -{ - a_uint32_t hw_index = 0, hw_entries = 0, hw_srctype = 0, hw_list_id = 0; - union ipo_rule_reg_u hw_reg = {0}; - - hw_entries = rule_entry->rule_hw_entry; - hw_list_id = rule_entry->rule_hw_list_id; - /* msg for debug */ - SSDK_DEBUG("ACL bind rule: list_id=%d, rule_id=%d, hw_entries=0x%x, hw_list_id=%d\n", - list_id, rule_entry->rule_id, hw_entries, hw_list_id); - - while(hw_entries != 0) - { - hw_index = _acl_bit_index(hw_entries, ADPT_ACL_ENTRY_NUM_PER_LIST, 0); - if(hw_index >= ADPT_ACL_ENTRY_NUM_PER_LIST) - { - break; - } - - hppe_ipo_rule_reg_get(dev_id, hw_list_id*ADPT_ACL_ENTRY_NUM_PER_LIST+hw_index, - &hw_reg); - - if(obj_t == FAL_ACL_BIND_PORT && obj_idx < SSDK_MAX_PORT_NUM) - { - /*convert port to bitmap if it is physical port*/ - obj_t = FAL_ACL_BIND_PORTBITMAP; - obj_idx = (1<>3)&0x1f; - } - else - { - hw_reg.bf.src_0 = obj_idx&0x7; - hw_reg.bf.src_1 = (obj_idx>>3)&0x1f; - } - hw_reg.bf.src_type = hw_srctype; - - hppe_ipo_rule_reg_set(dev_id, hw_list_id*ADPT_ACL_ENTRY_NUM_PER_LIST+hw_index, - &hw_reg); - SSDK_DEBUG("ACL bind entry %d source type %d, source value 0x%x\n", - hw_list_id*ADPT_ACL_ENTRY_NUM_PER_LIST+hw_index, obj_t, obj_idx); - hw_entries &= (~(1<list_id == list_id) - { - break; - } - } - if(list_pos == &g_acl_sw_list[dev_id].list_sw_list) - { - return NULL; - } - else - { - return list_entry; - } -} - -sw_error_t -adpt_hppe_acl_list_bind(a_uint32_t dev_id, a_uint32_t list_id, fal_acl_direc_t direc, - fal_acl_bind_obj_t obj_t, a_uint32_t obj_idx) -{ - struct list_head *rule_pos = NULL; - ADPT_HPPE_ACL_SW_RULE *rule_bind_entry = NULL; - ADPT_HPPE_ACL_SW_LIST *list_bind_entry = NULL; - - ADPT_DEV_ID_CHECK(dev_id); - - if(list_id >= ADPT_ACL_SW_LIST_NUM) - { - return SW_OUT_OF_RANGE; - } - - aos_lock_bh(&hppe_acl_lock[dev_id]); - list_bind_entry = _adpt_hppe_acl_list_entry_get(dev_id, list_id); - if(list_bind_entry == NULL) - { - aos_unlock_bh(&hppe_acl_lock[dev_id]); - return SW_NOT_FOUND; - } - - list_for_each(rule_pos, &list_bind_entry->list_sw_rule) - { - rule_bind_entry = list_entry(rule_pos, ADPT_HPPE_ACL_SW_RULE, list); - if(rule_bind_entry->rule_hw_entry) - { - sw_error_t rc; - rc = _adpt_hppe_acl_rule_bind(dev_id, list_id, rule_bind_entry, - direc, obj_t, obj_idx); - if(rc != SW_OK) - { - SSDK_ERROR("rule %d bind fail\n", rule_bind_entry->rule_id); - aos_unlock_bh(&hppe_acl_lock[dev_id]); - return SW_FAIL; - } - } - } - aos_unlock_bh(&hppe_acl_lock[dev_id]); - return SW_OK; -} - -static sw_error_t _adpt_hppe_acl_mac_rule_hw_2_sw(a_uint32_t is_mac_da, - union ipo_rule_reg_u *hw_reg, union ipo_mask_reg_u *hw_mask, fal_acl_rule_t * rule) -{ - ADPT_HPPE_ACL_MAC_RULE *macrule = (ADPT_HPPE_ACL_MAC_RULE *)hw_reg; - ADPT_HPPE_ACL_MAC_RULE_MASK *macrule_mask = (ADPT_HPPE_ACL_MAC_RULE_MASK *)hw_mask; - - if(is_mac_da) - { - rule->dest_mac_val.uc[0] = macrule->mac[5]; - rule->dest_mac_val.uc[1] = macrule->mac[4]; - rule->dest_mac_val.uc[2] = macrule->mac[3]; - rule->dest_mac_val.uc[3] = macrule->mac[2]; - rule->dest_mac_val.uc[4] = macrule->mac[1]; - rule->dest_mac_val.uc[5] = macrule->mac[0]; - rule->dest_mac_mask.uc[0] = macrule_mask->mac_mask[5]; - rule->dest_mac_mask.uc[1] = macrule_mask->mac_mask[4]; - rule->dest_mac_mask.uc[2] = macrule_mask->mac_mask[3]; - rule->dest_mac_mask.uc[3] = macrule_mask->mac_mask[2]; - rule->dest_mac_mask.uc[4] = macrule_mask->mac_mask[1]; - rule->dest_mac_mask.uc[5] = macrule_mask->mac_mask[0]; - } - else - { - rule->src_mac_val.uc[0] = macrule->mac[5]; - rule->src_mac_val.uc[1] = macrule->mac[4]; - rule->src_mac_val.uc[2] = macrule->mac[3]; - rule->src_mac_val.uc[3] = macrule->mac[2]; - rule->src_mac_val.uc[4] = macrule->mac[1]; - rule->src_mac_val.uc[5] = macrule->mac[0]; - rule->src_mac_mask.uc[0] = macrule_mask->mac_mask[5]; - rule->src_mac_mask.uc[1] = macrule_mask->mac_mask[4]; - rule->src_mac_mask.uc[2] = macrule_mask->mac_mask[3]; - rule->src_mac_mask.uc[3] = macrule_mask->mac_mask[2]; - rule->src_mac_mask.uc[4] = macrule_mask->mac_mask[1]; - rule->src_mac_mask.uc[5] = macrule_mask->mac_mask[0]; - } - if(A_FALSE == _adpt_acl_zero_addr(rule->dest_mac_mask)) - { - FAL_FIELD_FLG_SET(rule->field_flg, FAL_ACL_FIELD_MAC_DA); - } - if(A_FALSE == _adpt_acl_zero_addr(rule->src_mac_mask)) - { - FAL_FIELD_FLG_SET(rule->field_flg, FAL_ACL_FIELD_MAC_SA); - } - - if(macrule_mask->is_ip_mask) - { - FAL_FIELD_FLG_SET(rule->field_flg, FAL_ACL_FIELD_IP); - rule->is_ip_val = macrule->is_ip; - } - - if(macrule_mask->is_ipv6_mask) - { - FAL_FIELD_FLG_SET(rule->field_flg, FAL_ACL_FIELD_IPV6); - rule->is_ipv6_val = macrule->is_ipv6; - } - - if(macrule_mask->is_ethernet_mask) - { - FAL_FIELD_FLG_SET(rule->field_flg, FAL_ACL_FIELD_ETHERNET); - rule->is_ethernet_val = macrule->is_ethernet; - } - - if(macrule_mask->is_snap_mask) - { - FAL_FIELD_FLG_SET(rule->field_flg, FAL_ACL_FIELD_SNAP); - rule->is_snap_val = macrule->is_snap; - } - - if(macrule_mask->is_fake_mac_header_mask) - { - FAL_FIELD_FLG_SET(rule->field_flg, FAL_ACL_FIELD_FAKE_MAC_HEADER); - rule->is_fake_mac_header_val = macrule->is_fake_mac_header; - } - - return SW_OK; -} - -static sw_error_t _adpt_hppe_acl_vlan_rule_hw_2_sw(union ipo_rule_reg_u *hw_reg, - union ipo_mask_reg_u *hw_mask, fal_acl_rule_t * rule) -{ - ADPT_HPPE_ACL_VLAN_RULE * vlanrule = (ADPT_HPPE_ACL_VLAN_RULE *)hw_reg; - ADPT_HPPE_ACL_VLAN_RULE_MASK *vlanrule_mask = (ADPT_HPPE_ACL_VLAN_RULE_MASK *)hw_mask; - - /*ctag*/ - if(vlanrule_mask->cvid_mask) - { - FAL_FIELD_FLG_SET(rule->field_flg, FAL_ACL_FIELD_MAC_CTAG_VID); - rule->ctag_vid_mask = vlanrule_mask->cvid_mask; - } - if(hw_reg->bf.range_en) - { - if(vlanrule->cvid == 0) - { - rule->ctag_vid_op = FAL_ACL_FIELD_LE; - rule->ctag_vid_val = vlanrule_mask->cvid_mask; - } - else if(vlanrule_mask->cvid_mask == 0xfff) - { - rule->ctag_vid_op = FAL_ACL_FIELD_GE; - rule->ctag_vid_val = vlanrule->cvid; - } - else - { - rule->ctag_vid_op = FAL_ACL_FIELD_RANGE; - rule->ctag_vid_val = vlanrule->cvid; - } - - } - else - { - rule->ctag_vid_op = FAL_ACL_FIELD_MASK; - rule->ctag_vid_val = vlanrule->cvid; - } - - if(vlanrule_mask->cpcp_mask) - { - FAL_FIELD_FLG_SET(rule->field_flg, FAL_ACL_FIELD_MAC_CTAG_PRI); - rule->ctag_pri_val = vlanrule->cpcp; - rule->ctag_pri_mask = vlanrule_mask->cpcp_mask; - } - - if(vlanrule_mask->cdei_mask) - { - FAL_FIELD_FLG_SET(rule->field_flg, FAL_ACL_FIELD_MAC_CTAG_CFI); - rule->ctag_cfi_val = vlanrule->cdei; - rule->ctag_cfi_mask = vlanrule_mask->cdei_mask; - } - - if(vlanrule_mask->ctag_fmt_mask) - { - FAL_FIELD_FLG_SET(rule->field_flg, FAL_ACL_FIELD_MAC_CTAGGED); - rule->ctagged_val = vlanrule->ctag_fmt; - rule->ctagged_mask = vlanrule_mask->ctag_fmt_mask; - } - - /*stag*/ - if(vlanrule_mask->svid_mask) - { - FAL_FIELD_FLG_SET(rule->field_flg, FAL_ACL_FIELD_MAC_STAG_VID); - rule->stag_vid_val = vlanrule->svid; - rule->stag_vid_mask = vlanrule_mask->svid_mask; - } - if(vlanrule_mask->spcp_mask) - { - FAL_FIELD_FLG_SET(rule->field_flg, FAL_ACL_FIELD_MAC_STAG_PRI); - rule->stag_pri_val = vlanrule->spcp; - rule->stag_pri_mask = vlanrule_mask->spcp_mask; - } - if(vlanrule_mask->sdei_mask) - { - FAL_FIELD_FLG_SET(rule->field_flg, FAL_ACL_FIELD_MAC_STAG_DEI); - rule->stag_dei_val = vlanrule->sdei; - rule->stag_dei_mask = vlanrule_mask->sdei_mask; - } - if(vlanrule_mask->stag_fmt_mask) - { - FAL_FIELD_FLG_SET(rule->field_flg, FAL_ACL_FIELD_MAC_STAGGED); - rule->stagged_val = vlanrule->stag_fmt; - rule->stagged_mask = vlanrule_mask->stag_fmt_mask; - } - /*vsi*/ - if(vlanrule_mask->vsi_valid_mask) - { - FAL_FIELD_FLG_SET(rule->field_flg, FAL_ACL_FIELD_VSI_VALID); - rule->vsi_valid = vlanrule->vsi_valid; - rule->vsi_valid_mask = vlanrule_mask->vsi_valid_mask; - } - if(vlanrule_mask->vsi_mask) - { - FAL_FIELD_FLG_SET(rule->field_flg, FAL_ACL_FIELD_VSI); - rule->vsi = vlanrule->vsi; - rule->vsi_mask = vlanrule_mask->vsi_mask; - } - - if(vlanrule_mask->is_ip_mask) - { - FAL_FIELD_FLG_SET(rule->field_flg, FAL_ACL_FIELD_IP); - rule->is_ip_val = vlanrule->is_ip; - } - - if(vlanrule_mask->is_ipv6_mask) - { - FAL_FIELD_FLG_SET(rule->field_flg, FAL_ACL_FIELD_IPV6); - rule->is_ipv6_val = vlanrule->is_ipv6; - } - - if(vlanrule_mask->is_ethernet_mask) - { - FAL_FIELD_FLG_SET(rule->field_flg, FAL_ACL_FIELD_ETHERNET); - rule->is_ethernet_val = vlanrule->is_ethernet; - } - - if(vlanrule_mask->is_snap_mask) - { - FAL_FIELD_FLG_SET(rule->field_flg, FAL_ACL_FIELD_SNAP); - rule->is_snap_val = vlanrule->is_snap; - } - - if(vlanrule_mask->is_fake_mac_header_mask) - { - FAL_FIELD_FLG_SET(rule->field_flg, FAL_ACL_FIELD_FAKE_MAC_HEADER); - rule->is_fake_mac_header_val = vlanrule->is_fake_mac_header; - } - - return SW_OK; -} -static sw_error_t _adpt_hppe_acl_l2_misc_rule_hw_2_sw(union ipo_rule_reg_u *hw_reg, - union ipo_mask_reg_u *hw_mask, fal_acl_rule_t * rule) -{ - ADPT_HPPE_ACL_L2MISC_RULE * l2misc_rule = (ADPT_HPPE_ACL_L2MISC_RULE *)hw_reg; - ADPT_HPPE_ACL_L2MISC_RULE_MASK *l2misc_mask = (ADPT_HPPE_ACL_L2MISC_RULE_MASK *)hw_mask; - - /*stag*/ - if(l2misc_mask->svid_mask) - { - FAL_FIELD_FLG_SET(rule->field_flg, FAL_ACL_FIELD_MAC_STAG_VID); - rule->stag_vid_mask = l2misc_mask->svid_mask; - } - if(hw_reg->bf.range_en) - { - if(l2misc_rule->svid == 0) - { - rule->stag_vid_op = FAL_ACL_FIELD_LE; - rule->stag_vid_val = l2misc_mask->svid_mask; - } - else if(l2misc_mask->svid_mask == 0xfff) - { - rule->stag_vid_op = FAL_ACL_FIELD_GE; - rule->stag_vid_val = l2misc_rule->svid; - } - else - { - rule->stag_vid_op = FAL_ACL_FIELD_RANGE; - rule->stag_vid_val = l2misc_rule->svid; - } - - } - else - { - rule->stag_vid_op = FAL_ACL_FIELD_MASK; - rule->stag_vid_val = l2misc_rule->svid; - } - - if(l2misc_mask->l2prot_mask) - { - FAL_FIELD_FLG_SET(rule->field_flg, FAL_ACL_FIELD_MAC_ETHTYPE); - rule->ethtype_val = l2misc_rule->l2prot; - rule->ethtype_mask = l2misc_mask->l2prot_mask; - } - - if(l2misc_mask->pppoe_sessionid_mask) - { - FAL_FIELD_FLG_SET(rule->field_flg, FAL_ACL_FIELD_PPPOE_SESSIONID); - rule->pppoe_sessionid = l2misc_rule->pppoe_sessionid; - rule->pppoe_sessionid_mask = l2misc_mask->pppoe_sessionid_mask; - } - - if(l2misc_mask->is_ip_mask) - { - FAL_FIELD_FLG_SET(rule->field_flg, FAL_ACL_FIELD_IP); - rule->is_ip_val = l2misc_rule->is_ip; - } - - if(l2misc_mask->is_ipv6_mask) - { - FAL_FIELD_FLG_SET(rule->field_flg, FAL_ACL_FIELD_IPV6); - rule->is_ipv6_val = l2misc_rule->is_ipv6; - } - - if(l2misc_mask->is_ethernet_mask) - { - FAL_FIELD_FLG_SET(rule->field_flg, FAL_ACL_FIELD_ETHERNET); - rule->is_ethernet_val = l2misc_rule->is_ethernet; - } - - if(l2misc_mask->is_snap_mask) - { - FAL_FIELD_FLG_SET(rule->field_flg, FAL_ACL_FIELD_SNAP); - rule->is_snap_val = l2misc_rule->is_snap; - } - - if(l2misc_mask->is_fake_mac_header_mask) - { - FAL_FIELD_FLG_SET(rule->field_flg, FAL_ACL_FIELD_FAKE_MAC_HEADER); - rule->is_fake_mac_header_val = l2misc_rule->is_fake_mac_header; - } - - return SW_OK; -} - -static sw_error_t _adpt_hppe_acl_ipv4_rule_hw_2_sw(a_uint32_t is_ip_da, - union ipo_rule_reg_u *hw_reg, union ipo_mask_reg_u *hw_mask, fal_acl_rule_t *rule) -{ - ADPT_HPPE_ACL_IPV4_RULE * ipv4rule = (ADPT_HPPE_ACL_IPV4_RULE *)hw_reg; - ADPT_HPPE_ACL_IPV4_RULE_MASK *ipv4rule_mask = (ADPT_HPPE_ACL_IPV4_RULE_MASK *)hw_mask; - - if(is_ip_da) - { - if(ipv4rule_mask->ip_mask_0 || ipv4rule_mask->ip_mask_1) - { - FAL_FIELD_FLG_SET(rule->field_flg, FAL_ACL_FIELD_IP4_DIP); - rule->dest_ip4_val = ipv4rule->ip_1<<16|ipv4rule->ip_0; - rule->dest_ip4_mask = (ipv4rule_mask->ip_mask_1<<16)|ipv4rule_mask->ip_mask_0; - } - if(ipv4rule_mask->l4_port_mask) - { - FAL_FIELD_FLG_SET(rule->field_flg, FAL_ACL_FIELD_L4_DPORT); - rule->dest_l4port_mask = ipv4rule_mask->l4_port_mask; - } - if(hw_reg->bf.range_en) - { - if(ipv4rule->l4_port == 0) - { - rule->dest_l4port_op = FAL_ACL_FIELD_LE; - rule->dest_l4port_val = ipv4rule_mask->l4_port_mask; - } - else if(ipv4rule_mask->l4_port_mask == 0xffff) - { - rule->dest_l4port_op = FAL_ACL_FIELD_GE; - rule->dest_l4port_val = ipv4rule->l4_port; - } - else - { - rule->dest_l4port_op = FAL_ACL_FIELD_RANGE; - rule->dest_l4port_val = ipv4rule->l4_port; - } - } - else - { - rule->dest_l4port_op = FAL_ACL_FIELD_MASK; - rule->dest_l4port_val = ipv4rule->l4_port; - } - } - else - { - if(ipv4rule_mask->ip_mask_0 || ipv4rule_mask->ip_mask_1) - { - FAL_FIELD_FLG_SET(rule->field_flg, FAL_ACL_FIELD_IP4_SIP); - rule->src_ip4_val = ipv4rule->ip_1<<16|ipv4rule->ip_0; - rule->src_ip4_mask = ipv4rule_mask->ip_mask_1<<16|ipv4rule_mask->ip_mask_0; - } - if(ipv4rule_mask->l4_port_mask) - { - FAL_FIELD_FLG_SET(rule->field_flg, FAL_ACL_FIELD_L4_SPORT); - rule->src_l4port_mask = ipv4rule_mask->l4_port_mask; - } - if(hw_reg->bf.range_en) - { - if(ipv4rule->l4_port == 0) - { - rule->src_l4port_op = FAL_ACL_FIELD_LE; - rule->src_l4port_val = ipv4rule_mask->l4_port_mask; - } - else if(ipv4rule_mask->l4_port_mask == 0xffff) - { - rule->src_l4port_op = FAL_ACL_FIELD_GE; - rule->src_l4port_val = ipv4rule->l4_port; - } - else - { - rule->src_l4port_op = FAL_ACL_FIELD_RANGE; - rule->src_l4port_val = ipv4rule->l4_port; - } - } - else - { - rule->src_l4port_op = FAL_ACL_FIELD_MASK; - rule->src_l4port_val = ipv4rule->l4_port; - } - } - - if(ipv4rule_mask->is_ip_mask) - { - FAL_FIELD_FLG_SET(rule->field_flg, FAL_ACL_FIELD_IP); - rule->is_ip_val = ipv4rule->is_ip; - } - if(ipv4rule_mask->l3_fragment_mask) - { - FAL_FIELD_FLG_SET(rule->field_flg, FAL_ACL_FIELD_L3_FRAGMENT); - rule->is_fragement_val = ipv4rule->l3_fragment; - rule->is_fragement_mask = ipv4rule_mask->l3_fragment_mask; - } - if(ipv4rule_mask->l3_packet_type_mask) - { - FAL_FIELD_FLG_SET(rule->field_flg, FAL_ACL_FIELD_IP_PKT_TYPE); - rule->l3_pkt_type = ipv4rule->l3_packet_type; - rule->l3_pkt_type_mask = ipv4rule_mask->l3_packet_type_mask; - } - - return SW_OK; -} - -/*ip_bit_range: 0 mean DIP0 or SIP0, 1 mean DIP1 or SIP1, 2 mean DIP2 or SIP2,*/ -static sw_error_t _adpt_hppe_acl_ipv6_rule_hw_2_sw(a_uint32_t is_ip_da, a_uint32_t ip_bit_range, - union ipo_rule_reg_u *hw_reg, union ipo_mask_reg_u *hw_mask, fal_acl_rule_t *rule) -{ - ADPT_HPPE_ACL_IPV6_RULE * ipv6rule = (ADPT_HPPE_ACL_IPV6_RULE *)hw_reg; - ADPT_HPPE_ACL_IPV6_RULE_MASK *ipv6rule_mask = (ADPT_HPPE_ACL_IPV6_RULE_MASK *)hw_mask; - - if(is_ip_da) - { - if(ip_bit_range == 0) - { - if(ipv6rule_mask->ip_port_mask - || ipv6rule_mask->ip_ext_1_mask - || ipv6rule_mask->ip_ext_2_mask) - { - FAL_FIELD_FLG_SET(rule->field_flg, FAL_ACL_FIELD_IP6_DIP); - } - - rule->dest_ip6_val.ul[3] = ipv6rule->ip_ext_1<<16|ipv6rule->ip_port; - rule->dest_ip6_val.ul[2] |= (ipv6rule->ip_ext_2)&0xffff; - rule->dest_ip6_mask.ul[3] = - ipv6rule_mask->ip_ext_1_mask<<16|ipv6rule_mask->ip_port_mask; - rule->dest_ip6_mask.ul[2] |= (ipv6rule_mask->ip_ext_2_mask)&0xffff; - } - else if(ip_bit_range == 1) - { - if(ipv6rule_mask->ip_port_mask - || ipv6rule_mask->ip_ext_1_mask - || ipv6rule_mask->ip_ext_2_mask) - { - FAL_FIELD_FLG_SET(rule->field_flg, FAL_ACL_FIELD_IP6_DIP); - } - rule->dest_ip6_val.ul[2] |= (ipv6rule->ip_port<<16)&0xffff0000; - rule->dest_ip6_val.ul[1] = ipv6rule->ip_ext_2<<16|ipv6rule->ip_ext_1; - rule->dest_ip6_mask.ul[2] |= (ipv6rule_mask->ip_port_mask<<16)&0xffff0000; - rule->dest_ip6_mask.ul[1] = - ipv6rule_mask->ip_ext_2_mask<<16|ipv6rule_mask->ip_ext_1_mask; - } - else if(ip_bit_range == 2) - { - if(ipv6rule_mask->ip_ext_1_mask - || ipv6rule_mask->ip_ext_2_mask) - { - FAL_FIELD_FLG_SET(rule->field_flg, FAL_ACL_FIELD_IP6_DIP); - rule->dest_ip6_val.ul[0] = - ipv6rule->ip_ext_2<<16|ipv6rule->ip_ext_1; - rule->dest_ip6_mask.ul[0] = ipv6rule_mask->ip_ext_2_mask<<16| - ipv6rule_mask->ip_ext_1_mask; - } - if(ipv6rule_mask->ip_port_mask) - { - FAL_FIELD_FLG_SET(rule->field_flg, FAL_ACL_FIELD_L4_DPORT); - rule->dest_l4port_mask = ipv6rule_mask->ip_port_mask; - } - if(hw_reg->bf.range_en) - { - if(ipv6rule->ip_port == 0) - { - rule->dest_l4port_op = FAL_ACL_FIELD_LE; - rule->dest_l4port_val = ipv6rule_mask->ip_port_mask; - } - else if(ipv6rule_mask->ip_port_mask == 0xffff) - { - rule->dest_l4port_op = FAL_ACL_FIELD_GE; - rule->dest_l4port_val= ipv6rule->ip_port; - } - else - { - rule->dest_l4port_op = FAL_ACL_FIELD_RANGE; - rule->dest_l4port_val= ipv6rule->ip_port; - } - } - else - { - rule->dest_l4port_op = FAL_ACL_FIELD_MASK; - rule->dest_l4port_val = ipv6rule->ip_port; - } - - } - } - else - { - if(ip_bit_range == 0) - { - if(ipv6rule_mask->ip_port_mask - || ipv6rule_mask->ip_ext_1_mask - || ipv6rule_mask->ip_ext_2_mask) - { - FAL_FIELD_FLG_SET(rule->field_flg, FAL_ACL_FIELD_IP6_SIP); - } - rule->src_ip6_val.ul[3] = ipv6rule->ip_ext_1<<16|ipv6rule->ip_port; - rule->src_ip6_val.ul[2] |= (ipv6rule->ip_ext_2)&0xffff; - rule->src_ip6_mask.ul[3] = - ipv6rule_mask->ip_ext_1_mask<<16|ipv6rule_mask->ip_port_mask; - rule->src_ip6_mask.ul[2] |= (ipv6rule_mask->ip_ext_2_mask)&0xffff; - } - else if(ip_bit_range == 1) - { - if(ipv6rule_mask->ip_port_mask - || ipv6rule_mask->ip_ext_1_mask - || ipv6rule_mask->ip_ext_2_mask) - { - FAL_FIELD_FLG_SET(rule->field_flg, FAL_ACL_FIELD_IP6_SIP); - } - rule->src_ip6_val.ul[2] |= (ipv6rule->ip_port<<16)&0xffff0000; - rule->src_ip6_val.ul[1] = ipv6rule->ip_ext_2<<16|ipv6rule->ip_ext_1; - rule->src_ip6_mask.ul[2] |= (ipv6rule_mask->ip_port_mask<<16)&0xffff0000; - rule->src_ip6_mask.ul[1] = - ipv6rule_mask->ip_ext_2_mask<<16|ipv6rule_mask->ip_ext_1_mask; - } - else if(ip_bit_range == 2) - { - if(ipv6rule_mask->ip_ext_1_mask - || ipv6rule_mask->ip_ext_2_mask) - { - FAL_FIELD_FLG_SET(rule->field_flg, FAL_ACL_FIELD_IP6_SIP); - rule->src_ip6_val.ul[0] = ipv6rule->ip_ext_2<<16|ipv6rule->ip_ext_1; - rule->src_ip6_mask.ul[0] = ipv6rule_mask->ip_ext_2_mask<<16| - ipv6rule_mask->ip_ext_1_mask; - } - if(ipv6rule_mask->ip_port_mask) - { - FAL_FIELD_FLG_SET(rule->field_flg, FAL_ACL_FIELD_L4_SPORT); - rule->src_l4port_mask = ipv6rule_mask->ip_port_mask; - } - if(hw_reg->bf.range_en) - { - if(ipv6rule->ip_port == 0) - { - rule->src_l4port_op = FAL_ACL_FIELD_LE; - rule->src_l4port_val = ipv6rule_mask->ip_port_mask; - } - else if(ipv6rule_mask->ip_port_mask == 0xffff) - { - rule->src_l4port_op = FAL_ACL_FIELD_GE; - rule->src_l4port_val= ipv6rule->ip_port; - } - else - { - rule->src_l4port_op = FAL_ACL_FIELD_RANGE; - rule->src_l4port_val= ipv6rule->ip_port; - } - } - else - { - rule->src_l4port_op = FAL_ACL_FIELD_MASK; - rule->src_l4port_val = ipv6rule->ip_port; - } - - } - } - - if(ipv6rule_mask->l3_fragment_mask) - { - FAL_FIELD_FLG_SET(rule->field_flg, FAL_ACL_FIELD_L3_FRAGMENT); - rule->is_fragement_val = ipv6rule->l3_fragment; - rule->is_fragement_mask = ipv6rule_mask->l3_fragment_mask; - } - if(ipv6rule_mask->l3_packet_type_mask) - { - FAL_FIELD_FLG_SET(rule->field_flg, FAL_ACL_FIELD_IP_PKT_TYPE); - rule->l3_pkt_type = ipv6rule->l3_packet_type; - rule->l3_pkt_type_mask = ipv6rule_mask->l3_packet_type_mask; - } - return SW_OK; -} - -static sw_error_t _adpt_hppe_acl_ipmisc_rule_hw_2_sw(union ipo_rule_reg_u *hw_reg, - union ipo_mask_reg_u *hw_mask, fal_acl_rule_t *rule) -{ - ADPT_HPPE_ACL_IPMISC_RULE * ipmisc_rule = (ADPT_HPPE_ACL_IPMISC_RULE *)hw_reg; - ADPT_HPPE_ACL_IPMISC_RULE_MASK *ipmisc_mask = (ADPT_HPPE_ACL_IPMISC_RULE_MASK *)hw_mask; - - if(ipmisc_mask->l3_length_mask) - { - FAL_FIELD_FLG_SET(rule->field_flg, FAL_ACL_FIELD_L3_LENGTH); - rule->l3_length_mask = ipmisc_mask->l3_length_mask; - } - if(hw_reg->bf.range_en) - { - if(ipmisc_rule->l3_length == 0) - { - rule->l3_length_op = FAL_ACL_FIELD_LE; - rule->l3_length = ipmisc_mask->l3_length_mask; - } - else if(ipmisc_mask->l3_length_mask == 0xffff) - { - rule->l3_length_op = FAL_ACL_FIELD_GE; - rule->l3_length = ipmisc_rule->l3_length; - } - else - { - rule->l3_length_op = FAL_ACL_FIELD_RANGE; - rule->l3_length = ipmisc_rule->l3_length; - } - } - else - { - rule->l3_length_op = FAL_ACL_FIELD_MASK; - rule->l3_length = ipmisc_rule->l3_length; - } - - if(ipmisc_mask->l3_prot_mask) - { - FAL_FIELD_FLG_SET(rule->field_flg, FAL_ACL_FIELD_IP_PROTO); - rule->ip_proto_val = ipmisc_rule->l3_prot; - rule->ip_proto_mask = ipmisc_mask->l3_prot_mask; - } - if(ipmisc_mask->l3_dscp_tc_mask) - { - FAL_FIELD_FLG_SET(rule->field_flg, FAL_ACL_FIELD_IP_DSCP); - rule->ip_dscp_val = ipmisc_rule->l3_dscp_tc; - rule->ip_dscp_mask = ipmisc_mask->l3_dscp_tc_mask; - } - - if(ipmisc_mask->first_fragment_mask) - { - FAL_FIELD_FLG_SET(rule->field_flg, FAL_ACL_FIELD_FIRST_FRAGMENT); - rule->is_first_frag_val = ipmisc_rule->first_fragment; - } - if(ipmisc_mask->tcp_flags_mask) - { - FAL_FIELD_FLG_SET(rule->field_flg, FAL_ACL_FIELD_TCP_FLAG); - rule->tcp_flag_val = ipmisc_rule->tcp_flags; - rule->tcp_flag_mask = ipmisc_mask->tcp_flags_mask; - } - if(ipmisc_mask->ipv4_option_state_mask) - { - FAL_FIELD_FLG_SET(rule->field_flg, FAL_ACL_FIELD_IPV4_OPTION); - rule->is_ipv4_option_val = ipmisc_rule->ipv4_option_state; - } - if(ipmisc_mask->l3_ttl_mask) - { - FAL_FIELD_FLG_SET(rule->field_flg, FAL_ACL_FIELD_L3_TTL); - rule->l3_ttl = ipmisc_rule->l3_ttl; - rule->l3_ttl_mask = ipmisc_mask->l3_ttl_mask; - } - if(ipmisc_mask->ah_header_mask) - { - FAL_FIELD_FLG_SET(rule->field_flg, FAL_ACL_FIELD_AH_HEADER); - rule->is_ah_header_val = ipmisc_rule->ah_header; - } - if(ipmisc_mask->esp_header_mask) - { - FAL_FIELD_FLG_SET(rule->field_flg, FAL_ACL_FIELD_ESP_HEADER); - rule->is_esp_header_val = ipmisc_rule->esp_header; - } - if(ipmisc_mask->mobility_header_mask) - { - FAL_FIELD_FLG_SET(rule->field_flg, FAL_ACL_FIELD_MOBILITY_HEADER); - rule->is_mobility_header_val = ipmisc_rule->mobility_header; - } - if(ipmisc_mask->fragment_header_mask) - { - FAL_FIELD_FLG_SET(rule->field_flg, FAL_ACL_FIELD_FRAGMENT_HEADER); - rule->is_fragment_header_val = ipmisc_rule->fragment_header; - } - if(ipmisc_mask->other_header_mask) - { - FAL_FIELD_FLG_SET(rule->field_flg, FAL_ACL_FIELD_OTHER_EXT_HEADER); - rule->is_other_header_val = ipmisc_rule->other_header; - } - if(ipmisc_mask->is_ipv6_mask) - { - FAL_FIELD_FLG_SET(rule->field_flg, FAL_ACL_FIELD_IPV6); - rule->is_ipv6_val = ipmisc_rule->is_ipv6; - } - if(ipmisc_mask->l3_fragment_mask) - { - FAL_FIELD_FLG_SET(rule->field_flg, FAL_ACL_FIELD_L3_FRAGMENT); - rule->is_fragement_val = ipmisc_rule->l3_fragment; - } - return SW_OK; -} - -static sw_error_t _adpt_hppe_acl_udf_rule_hw_2_sw(union ipo_rule_reg_u *hw_reg, a_uint32_t is_win1, - union ipo_mask_reg_u *hw_mask, fal_acl_rule_t *rule) -{ - ADPT_HPPE_ACL_UDF_RULE * udfrule = (ADPT_HPPE_ACL_UDF_RULE *)hw_reg; - ADPT_HPPE_ACL_UDF_RULE_MASK *udfrule_mask = (ADPT_HPPE_ACL_UDF_RULE_MASK *)hw_mask; - - if(is_win1) - { - if(udfrule->udf2_valid == 1) - { - FAL_FIELD_FLG_SET(rule->field_flg, FAL_ACL_FIELD_UDF3); - rule->udf3_val = udfrule->udf2; - rule->udf3_mask = udfrule_mask->udf2_mask; - } - if(udfrule->udf1_valid == 1) - { - FAL_FIELD_FLG_SET(rule->field_flg, FAL_ACL_FIELD_UDF2); - rule->udf2_val = udfrule->udf1; - rule->udf2_mask = udfrule_mask->udf1_mask; - } - if(udfrule->udf0_valid == 1) - { - FAL_FIELD_FLG_SET(rule->field_flg, FAL_ACL_FIELD_UDF1); - if(hw_reg->bf.range_en == 1) - { - if(udfrule->udf0 == 0) - { - rule->udf1_op = FAL_ACL_FIELD_LE; - rule->udf1_val = udfrule_mask->udf0_mask; - } - else if(rule->udf1_mask == 0xffff) - { - rule->udf1_op = FAL_ACL_FIELD_GE; - rule->udf1_val = udfrule->udf0; - } - else - { - rule->udf1_op = FAL_ACL_FIELD_RANGE; - rule->udf1_val = udfrule->udf0; - rule->udf1_mask = udfrule_mask->udf0_mask; - } - } - else - { - rule->udf1_op = FAL_ACL_FIELD_MASK; - rule->udf1_val = udfrule->udf0; - rule->udf1_mask = udfrule_mask->udf0_mask; - } - - } - } - else - { - if(udfrule->udf2_valid == 1) - { - FAL_FIELD_FLG_SET(rule->field_flg, FAL_ACL_FIELD_UDF2); - rule->udf2_val = udfrule->udf2; - rule->udf2_mask = udfrule_mask->udf2_mask; - } - if(udfrule->udf1_valid == 1) - { - FAL_FIELD_FLG_SET(rule->field_flg, FAL_ACL_FIELD_UDF1); - rule->udf1_val = udfrule->udf1; - rule->udf1_mask = udfrule_mask->udf1_mask; - } - if(udfrule->udf0_valid == 1) - { - FAL_FIELD_FLG_SET(rule->field_flg, FAL_ACL_FIELD_UDF0); - if(hw_reg->bf.range_en == 1) - { - if(udfrule->udf0 == 0) - { - rule->udf0_op = FAL_ACL_FIELD_LE; - rule->udf0_val = udfrule_mask->udf0_mask; - } - else if(rule->udf0_mask == 0xffff) - { - rule->udf0_op = FAL_ACL_FIELD_GE; - rule->udf0_val = udfrule->udf0; - } - else - { - rule->udf0_op = FAL_ACL_FIELD_RANGE; - rule->udf0_val = udfrule->udf0; - rule->udf0_mask = udfrule_mask->udf0_mask; - } - } - else - { - rule->udf0_op = FAL_ACL_FIELD_MASK; - rule->udf0_val = udfrule->udf0; - rule->udf0_mask = udfrule_mask->udf0_mask; - } - - } - } - - if(udfrule_mask->is_ip) - { - rule->is_ip_val = udfrule->is_ip; - FAL_FIELD_FLG_SET(rule->field_flg, FAL_ACL_FIELD_IP); - } - if(udfrule_mask->is_ipv6) - { - udfrule->is_ipv6= rule->is_ipv6_val; - FAL_FIELD_FLG_SET(rule->field_flg, FAL_ACL_FIELD_IPV6); - } - return SW_OK; -} - -static sw_error_t -_adpt_hppe_acl_action_hw_2_sw(a_uint32_t dev_id,union ipo_action_u *hw_act, fal_acl_rule_t *rule) -{ - if(hw_act->bf.dest_info_change_en) - { - a_uint32_t dest_type = HPPE_ACL_DEST_TYPE(hw_act->bf.dest_info); - a_uint32_t dest_val = HPPE_ACL_DEST_VALUE(hw_act->bf.dest_info); - SSDK_DEBUG("hw_act->bf.dest_info = %x\n", hw_act->bf.dest_info); - if(dest_type == HPPE_ACL_DEST_NEXTHOP) /*nexthop*/ - { - rule->ports = FAL_ACL_DEST_OFFSET(FAL_ACL_DEST_NEXTHOP, - dest_val); - } - else if(dest_type == HPPE_ACL_DEST_PORT_ID) /*vp or trunk*/ - { - rule->ports = FAL_ACL_DEST_OFFSET(FAL_ACL_DEST_PORT_ID, - dest_val); - } - else if(dest_type == HPPE_ACL_DEST_PORT_BMP) /*bitmap*/ - { - rule->ports = FAL_ACL_DEST_OFFSET(FAL_ACL_DEST_PORT_BMP, - dest_val); - } - if(rule->ports != 0) - { - FAL_ACTION_FLG_SET(rule->action_flg, FAL_ACL_ACTION_REDPT); - } - else if(hw_act->bf.fwd_cmd == HPPE_ACL_ACTION_RDTCPU) - { - FAL_ACTION_FLG_SET(rule->action_flg, FAL_ACL_ACTION_RDTCPU); - } - else if(hw_act->bf.fwd_cmd == HPPE_ACL_ACTION_COPYCPU) - { - FAL_ACTION_FLG_SET(rule->action_flg, FAL_ACL_ACTION_CPYCPU); - } - else if(hw_act->bf.fwd_cmd == HPPE_ACL_ACTION_DROP) - { - FAL_ACTION_FLG_SET(rule->action_flg, FAL_ACL_ACTION_DENY); - } - else if(hw_act->bf.fwd_cmd == HPPE_ACL_ACTION_FWD) - { - FAL_ACTION_FLG_SET(rule->action_flg, FAL_ACL_ACTION_PERMIT); - } - } - - if(hw_act->bf.mirror_en == 1) - { - FAL_ACTION_FLG_SET(rule->action_flg, FAL_ACL_ACTION_MIRROR); - } - if(hw_act->bf.bypass_bitmap_0 != 0 || - hw_act->bf.bypass_bitmap_1 != 0) - { - rule->bypass_bitmap = (hw_act->bf.bypass_bitmap_1<<14)|hw_act->bf.bypass_bitmap_0; - } - if(hw_act->bf.svid_change_en == 1) - { - FAL_ACTION_FLG_SET(rule->action_flg, FAL_ACL_ACTION_REMARK_STAG_VID); - rule->stag_fmt = hw_act->bf.stag_fmt; - rule->stag_vid = hw_act->bf.svid; - } - if(hw_act->bf.stag_pcp_change_en == 1) - { - FAL_ACTION_FLG_SET(rule->action_flg, FAL_ACL_ACTION_REMARK_STAG_PRI); - rule->stag_pri = hw_act->bf.stag_pcp; - } - if(hw_act->bf.stag_dei_change_en == 1) - { - FAL_ACTION_FLG_SET(rule->action_flg, FAL_ACL_ACTION_REMARK_STAG_DEI); - rule->stag_dei = hw_act->bf.stag_dei; - } - if(hw_act->bf.cvid_change_en == 1) - { - FAL_ACTION_FLG_SET(rule->action_flg, FAL_ACL_ACTION_REMARK_CTAG_VID); - rule->ctag_fmt = hw_act->bf.ctag_fmt; - rule->ctag_vid = hw_act->bf.cvid; - } - if(hw_act->bf.ctag_pcp_change_en == 1) - { - FAL_ACTION_FLG_SET(rule->action_flg, FAL_ACL_ACTION_REMARK_CTAG_PRI); - rule->ctag_pri = (hw_act->bf.ctag_pcp_1<<2)|hw_act->bf.ctag_pcp_0; - } - if(hw_act->bf.ctag_dei_change_en == 1) - { - FAL_ACTION_FLG_SET(rule->action_flg, FAL_ACL_ACTION_REMARK_CTAG_CFI); - rule->ctag_cfi = hw_act->bf.ctag_dei; - } - if(hw_act->bf.dscp_tc_change_en == 1) - { - FAL_ACTION_FLG_SET(rule->action_flg, FAL_ACL_ACTION_REMARK_DSCP); - rule->dscp = hw_act->bf.dscp_tc; -#if defined(CPPE) - if(adpt_hppe_chip_revision_get(dev_id) == CPPE_REVISION) - { - rule->dscp_mask = hw_act->bf.dscp_tc_mask; - } -#endif - } - if(hw_act->bf.int_dp_change_en == 1) - { - FAL_ACTION_FLG_SET(rule->action_flg, FAL_ACL_ACTION_INT_DP); - rule->int_dp = hw_act->bf.int_dp; - } - if(hw_act->bf.policer_en == 1) - { - FAL_ACTION_FLG_SET(rule->action_flg, FAL_ACL_ACTION_POLICER_EN); - rule->policer_ptr = hw_act->bf.policer_index; - } - if(hw_act->bf.qid_en == 1) - { - FAL_ACTION_FLG_SET(rule->action_flg, FAL_ACL_ACTION_REMARK_QUEUE); - rule->queue = hw_act->bf.qid; - } - if(hw_act->bf.enqueue_pri_change_en == 1) - { - FAL_ACTION_FLG_SET(rule->action_flg, FAL_ACL_ACTION_ENQUEUE_PRI); - rule->enqueue_pri = hw_act->bf.enqueue_pri; - } - if(hw_act->bf.service_code_en == 1) - { - FAL_ACTION_FLG_SET(rule->action_flg, FAL_ACL_ACTION_SERVICE_CODE); - rule->service_code = (hw_act->bf.service_code_1<<1)|hw_act->bf.service_code_0; - } - if(hw_act->bf.syn_toggle) - { - FAL_ACTION_FLG_SET(rule->action_flg, FAL_ACL_ACTION_SYN_TOGGLE); - } - if(hw_act->bf.cpu_code_en == 1) - { - FAL_ACTION_FLG_SET(rule->action_flg, FAL_ACL_ACTION_CPU_CODE); - rule->cpu_code = hw_act->bf.cpu_code; - } - if(hw_act->bf.metadata_en == 1) - { - FAL_ACTION_FLG_SET(rule->action_flg, FAL_ACL_ACTION_METADATA_EN); - } -#if defined(CPPE) - if(adpt_hppe_chip_revision_get(dev_id) == CPPE_REVISION) - { - rule->qos_res_prec = hw_act->bf.qos_res_prec; - } -#endif - return SW_OK; -} -sw_error_t -adpt_hppe_acl_rule_query(a_uint32_t dev_id, a_uint32_t list_id, a_uint32_t rule_id, - fal_acl_rule_t * rule) -{ - sw_error_t rv = 0; - a_uint32_t hw_index = 0, hw_entries = 0, hw_list_id = 0; - union ipo_rule_reg_u hw_reg = {0}; - union ipo_mask_reg_u hw_mask = {0}; - union ipo_action_u hw_act = {0}; - union ipo_cnt_tbl_u hw_match = {0}; - struct list_head *rule_pos = NULL; - ADPT_HPPE_ACL_SW_RULE *rule_query_entry = NULL; - ADPT_HPPE_ACL_SW_LIST *list_query_entry = NULL; - - ADPT_DEV_ID_CHECK(dev_id); - ADPT_NULL_POINT_CHECK(rule); - - if(list_id >= ADPT_ACL_SW_LIST_NUM) - { - return SW_OUT_OF_RANGE; - } - - if(rule_id >= ADPT_ACL_RULE_NUM_PER_LIST) - { - return SW_OUT_OF_RANGE; - } - - aos_lock_bh(&hppe_acl_lock[dev_id]); - list_query_entry = _adpt_hppe_acl_list_entry_get(dev_id, list_id); - if(list_query_entry == NULL) - { - aos_unlock_bh(&hppe_acl_lock[dev_id]); - return SW_NOT_FOUND; - } - - list_for_each(rule_pos, &list_query_entry->list_sw_rule) - { - rule_query_entry = list_entry(rule_pos, ADPT_HPPE_ACL_SW_RULE, list); - if((rule_query_entry->rule_id == rule_id) && (rule_query_entry->rule_hw_entry != 0)) - { - rule->rule_type = rule_query_entry->rule_type; - hw_entries = rule_query_entry->rule_hw_entry; - hw_list_id = rule_query_entry->rule_hw_list_id; - break; - } - } - if(rule_pos == &list_query_entry->list_sw_rule) - { - aos_unlock_bh(&hppe_acl_lock[dev_id]); - return SW_NOT_FOUND; - } - aos_unlock_bh(&hppe_acl_lock[dev_id]); - - hw_index = _acl_bit_index(hw_entries, ADPT_ACL_ENTRY_NUM_PER_LIST, 0); - if(hw_index >= ADPT_ACL_ENTRY_NUM_PER_LIST) - { - return SW_FAIL; - } - hppe_ipo_cnt_tbl_get(dev_id, hw_list_id*ADPT_ACL_ENTRY_NUM_PER_LIST+hw_index, &hw_match); - - rule->match_cnt = hw_match.bf.hit_pkt_cnt; - rule->match_bytes = hw_match.bf.hit_byte_cnt_1; - rule->match_bytes = rule->match_bytes<<32|hw_match.bf.hit_byte_cnt_0; - while(hw_entries != 0) - { - hw_index = _acl_bit_index(hw_entries, ADPT_ACL_ENTRY_NUM_PER_LIST, 0); - if(hw_index >= ADPT_ACL_ENTRY_NUM_PER_LIST) - { - break; - } - rv |= hppe_ipo_rule_reg_get(dev_id, hw_list_id*ADPT_ACL_ENTRY_NUM_PER_LIST+hw_index, - &hw_reg); - rv |= hppe_ipo_mask_reg_get(dev_id, hw_list_id*ADPT_ACL_ENTRY_NUM_PER_LIST+hw_index, - &hw_mask); - rv |= hppe_ipo_action_get(dev_id, hw_list_id*ADPT_ACL_ENTRY_NUM_PER_LIST+hw_index, - &hw_act); - rule->post_routing = hw_reg.bf.post_routing_en; - rule->acl_pool = hw_reg.bf.res_chain; - rule->pri = hw_reg.bf.pri&0x7; - - if(hw_reg.bf.rule_type == ADPT_ACL_HPPE_MAC_DA_RULE) - { - _adpt_hppe_acl_mac_rule_hw_2_sw(1, &hw_reg, &hw_mask, rule); - } - if(hw_reg.bf.rule_type == ADPT_ACL_HPPE_MAC_SA_RULE) - { - _adpt_hppe_acl_mac_rule_hw_2_sw(0, &hw_reg, &hw_mask, rule); - } - if(hw_reg.bf.rule_type == ADPT_ACL_HPPE_VLAN_RULE) - { - _adpt_hppe_acl_vlan_rule_hw_2_sw(&hw_reg, &hw_mask, rule); - } - if(hw_reg.bf.rule_type == ADPT_ACL_HPPE_L2_MISC_RULE) - { - _adpt_hppe_acl_l2_misc_rule_hw_2_sw(&hw_reg, &hw_mask, rule); - } - if(hw_reg.bf.rule_type == ADPT_ACL_HPPE_IPV4_DIP_RULE) - { - _adpt_hppe_acl_ipv4_rule_hw_2_sw(1, &hw_reg, &hw_mask, rule); - } - if(hw_reg.bf.rule_type == ADPT_ACL_HPPE_IPV4_SIP_RULE) - { - _adpt_hppe_acl_ipv4_rule_hw_2_sw(0, &hw_reg, &hw_mask, rule); - } - if(hw_reg.bf.rule_type == ADPT_ACL_HPPE_IPV6_DIP0_RULE) - { - _adpt_hppe_acl_ipv6_rule_hw_2_sw(1, 0, &hw_reg, &hw_mask, rule); - } - if(hw_reg.bf.rule_type == ADPT_ACL_HPPE_IPV6_DIP1_RULE) - { - _adpt_hppe_acl_ipv6_rule_hw_2_sw(1, 1, &hw_reg, &hw_mask, rule); - } - if(hw_reg.bf.rule_type == ADPT_ACL_HPPE_IPV6_DIP2_RULE) - { - _adpt_hppe_acl_ipv6_rule_hw_2_sw(1, 2, &hw_reg, &hw_mask, rule); - } - if(hw_reg.bf.rule_type == ADPT_ACL_HPPE_IPV6_SIP0_RULE) - { - _adpt_hppe_acl_ipv6_rule_hw_2_sw(0, 0, &hw_reg, &hw_mask, rule); - } - if(hw_reg.bf.rule_type == ADPT_ACL_HPPE_IPV6_SIP1_RULE) - { - _adpt_hppe_acl_ipv6_rule_hw_2_sw(0, 1, &hw_reg, &hw_mask, rule); - } - if(hw_reg.bf.rule_type == ADPT_ACL_HPPE_IPV6_SIP2_RULE) - { - _adpt_hppe_acl_ipv6_rule_hw_2_sw(0, 2, &hw_reg, &hw_mask, rule); - } - if(hw_reg.bf.rule_type == ADPT_ACL_HPPE_IPMISC_RULE) - { - _adpt_hppe_acl_ipmisc_rule_hw_2_sw(&hw_reg, &hw_mask, rule); - } - if(hw_reg.bf.rule_type == ADPT_ACL_HPPE_UDF0_RULE) - { - _adpt_hppe_acl_udf_rule_hw_2_sw(&hw_reg, 0, &hw_mask, rule); - } - if(hw_reg.bf.rule_type == ADPT_ACL_HPPE_UDF1_RULE) - { - _adpt_hppe_acl_udf_rule_hw_2_sw(&hw_reg, 1, &hw_mask, rule); - } - - if(hw_reg.bf.inverse_en == 1) - { - FAL_FIELD_FLG_SET(rule->field_flg, FAL_ACL_FIELD_INVERSE_ALL); - } - - _adpt_hppe_acl_action_hw_2_sw(dev_id,&hw_act, rule); - hw_entries &= (~(1<rule_hw_entry; - hw_list_id = rule_entry->rule_hw_list_id; - /* msg for debug */ - SSDK_DEBUG("ACL unbind rule: list_id=%d, rule_id=%d, hw_entries=0x%x, hw_list_id=%d\n", - list_id, rule_entry->rule_id, hw_entries, hw_list_id); - - while(hw_entries != 0) - { - hw_index = _acl_bit_index(hw_entries, ADPT_ACL_ENTRY_NUM_PER_LIST, 0); - if(hw_index >= ADPT_ACL_ENTRY_NUM_PER_LIST) - { - break; - } - - hppe_ipo_rule_reg_get(dev_id, hw_list_id*ADPT_ACL_ENTRY_NUM_PER_LIST+hw_index, - &hw_reg); - - if(obj_t == FAL_ACL_BIND_PORT && obj_idx < SSDK_MAX_PORT_NUM) - { - /*convert port to bitmap if it is physical port*/ - obj_t = FAL_ACL_BIND_PORTBITMAP; - obj_idx = (1<>3))&0x1f); - } - else - { - hw_reg.bf.src_type = HPPE_ACL_TYPE_PORTBITMAP; - hw_reg.bf.src_0 = 0; - hw_reg.bf.src_1 = 0; - } - hppe_ipo_rule_reg_set(dev_id, hw_list_id*ADPT_ACL_ENTRY_NUM_PER_LIST+hw_index, - &hw_reg); - SSDK_DEBUG("ACL unbind entry %d source type %d, source value 0x%x\n", - hw_list_id*ADPT_ACL_ENTRY_NUM_PER_LIST+hw_index, obj_t, obj_idx); - hw_entries &= (~(1<= ADPT_ACL_SW_LIST_NUM) - { - return SW_OUT_OF_RANGE; - } - - aos_lock_bh(&hppe_acl_lock[dev_id]); - list_unbind_entry = _adpt_hppe_acl_list_entry_get(dev_id, list_id); - if(list_unbind_entry != NULL) - { - list_for_each(rule_pos, &list_unbind_entry->list_sw_rule) - { - rule_unbind_entry = list_entry(rule_pos, ADPT_HPPE_ACL_SW_RULE, list); - if(rule_unbind_entry->rule_hw_entry) - { - _adpt_hppe_acl_rule_unbind(dev_id, list_id, rule_unbind_entry, - direc, obj_t, obj_idx); - } - } - } - aos_unlock_bh(&hppe_acl_lock[dev_id]); - return SW_OK; -} -sw_error_t -adpt_hppe_acl_rule_active(a_uint32_t dev_id, a_uint32_t list_id, - a_uint32_t rule_id, a_uint32_t rule_nr) -{ - - ADPT_DEV_ID_CHECK(dev_id); - - return SW_NOT_SUPPORTED; -} - -static sw_error_t _adpt_hppe_acl_rule_range_match(a_uint32_t dev_id, a_uint32_t hw_list_index, - a_uint32_t rule_id, a_uint32_t rule_nr, fal_acl_rule_t * rule, a_uint8_t entries) -{ - a_uint8_t rangecount = 0, even_entry_count = 0; - if(FAL_FIELD_FLG_TST(rule->field_flg, FAL_ACL_FIELD_MAC_STAG_VID)) - { - if (FAL_ACL_FIELD_MASK != rule->stag_vid_op) - { - rangecount++; - } - } - if(FAL_FIELD_FLG_TST(rule->field_flg, FAL_ACL_FIELD_MAC_CTAG_VID)) - { - if (FAL_ACL_FIELD_MASK != rule->ctag_vid_op) - { - rangecount++; - } - } - if(FAL_FIELD_FLG_TST(rule->field_flg, FAL_ACL_FIELD_L4_DPORT)) - { - if (FAL_ACL_FIELD_MASK != rule->dest_l4port_op) - { - rangecount++; - } - } - if(FAL_FIELD_FLG_TST(rule->field_flg, FAL_ACL_FIELD_L4_SPORT)) - { - if (FAL_ACL_FIELD_MASK != rule->src_l4port_op) - { - rangecount++; - } - } - - if(FAL_FIELD_FLG_TST(rule->field_flg, FAL_ACL_FIELD_L3_LENGTH)) - { - if (FAL_ACL_FIELD_MASK != rule->l3_length_op) - { - rangecount++; - } - } - - if(FAL_FIELD_FLG_TST(rule->field_flg, FAL_ACL_FIELD_UDF0)) - { - if (FAL_ACL_FIELD_MASK != rule->udf0_op) - { - rangecount++; - } - } - - if(FAL_FIELD_FLG_TST(rule->field_flg, FAL_ACL_FIELD_UDF1)) - { - if (FAL_ACL_FIELD_MASK != rule->udf1_op) - { - rangecount++; - } - } - - if(FAL_FIELD_FLG_TST(rule->field_flg, FAL_ACL_FIELD_ICMP_TYPE)) - { - if (FAL_ACL_FIELD_MASK != rule->icmp_type_code_op) - { - rangecount++; - } - } - - even_entry_count = _acl_bits_count(entries, ADPT_ACL_ENTRY_NUM_PER_LIST, 2); - - if(rangecount <= even_entry_count) - { - return SW_OK; - } - return SW_NO_RESOURCE; -} -sw_error_t _adpt_hppe_acl_alloc_entries(a_uint32_t dev_id, a_uint32_t *hw_list_index, - a_uint32_t rule_id, a_uint32_t rule_nr, fal_acl_rule_t * rule, - a_uint32_t rule_type_map, a_uint32_t rule_type_count, a_uint32_t *index) -{ - a_uint8_t free_hw_entry_bitmap = 0, free_hw_entry_count = 0, i = 0; - a_uint32_t j = 0; - a_uint8_t map_info_count = sizeof(s_acl_entries)/sizeof(ADPT_HPPE_ACL_ENTRY_EXTEND_INFO); - - for(j = 0 ; j < ADPT_ACL_HW_LIST_NUM; j++) - { - free_hw_entry_bitmap = g_acl_hw_list[dev_id][j].free_hw_entry_bitmap; - free_hw_entry_count = g_acl_hw_list[dev_id][j].free_hw_entry_count; - /* msg for debug */ - SSDK_DEBUG("_adpt_hppe_acl_alloc_entries():hw_list_index=%d, hw_list_id=%d, " - "free_hw_entry_bitmap=0x%x, free_hw_entry_count=%d\n", j, - g_acl_hw_list[dev_id][j].hw_list_id, free_hw_entry_bitmap, - free_hw_entry_count); - if(free_hw_entry_count < rule_type_count) - { - continue; - } - for(i = 0; i < map_info_count; i++) - { - if((rule_type_count == s_acl_entries[i].num) && - ((free_hw_entry_bitmap & s_acl_entries[i].entries) == - s_acl_entries[i].entries)) - { - if(SW_OK == _adpt_hppe_acl_rule_range_match(dev_id, j, - rule_id, rule_nr, rule, s_acl_entries[i].entries)) - { - SSDK_DEBUG("\n{%d, 0x%x, 0x%x, 0x%x, 0x%x},\n", - s_acl_entries[i].num, s_acl_entries[i].ext_1, - s_acl_entries[i].ext_2, s_acl_entries[i].ext_4, - s_acl_entries[i].entries); - *index = i; - *hw_list_index = j; - return SW_OK; - } - } - } - } - return SW_NO_RESOURCE; -} - -static sw_error_t -_adpt_hppe_acl_l2_fields_check(a_uint32_t dev_id, a_uint32_t list_id, a_uint32_t rule_id, a_uint32_t rule_nr, - fal_acl_rule_t * rule, a_uint32_t *rule_type_map) -{ - a_uint32_t l2_rule_type_map = 0; - SSDK_DEBUG("fields[0] = 0x%x, fields[1] = 0x%x\n", rule->field_flg[0], rule->field_flg[1]); - - if(FAL_FIELD_FLG_TST(rule->field_flg, FAL_ACL_FIELD_MAC_DA)) - { - SSDK_DEBUG("select MAC DA rule\n"); - l2_rule_type_map |= (1<field_flg, FAL_ACL_FIELD_MAC_SA)) - { - SSDK_DEBUG("select MAC SA rule\n"); - l2_rule_type_map |= (1<field_flg, FAL_ACL_FIELD_MAC_STAG_PRI)) || - (FAL_FIELD_FLG_TST(rule->field_flg, FAL_ACL_FIELD_MAC_STAG_DEI)) || - (FAL_FIELD_FLG_TST(rule->field_flg, FAL_ACL_FIELD_MAC_STAGGED)) || - (FAL_FIELD_FLG_TST(rule->field_flg, FAL_ACL_FIELD_MAC_CTAG_VID)) || - (FAL_FIELD_FLG_TST(rule->field_flg, FAL_ACL_FIELD_MAC_CTAG_PRI)) || - (FAL_FIELD_FLG_TST(rule->field_flg, FAL_ACL_FIELD_MAC_CTAG_CFI)) || - (FAL_FIELD_FLG_TST(rule->field_flg, FAL_ACL_FIELD_MAC_CTAGGED)) || - (FAL_FIELD_FLG_TST(rule->field_flg, FAL_ACL_FIELD_VSI)) || - (FAL_FIELD_FLG_TST(rule->field_flg, FAL_ACL_FIELD_VSI_VALID))) - { - SSDK_DEBUG("select VLAN rule\n"); - l2_rule_type_map |= (1<field_flg, FAL_ACL_FIELD_MAC_ETHTYPE)) || - (FAL_FIELD_FLG_TST(rule->field_flg, FAL_ACL_FIELD_PPPOE_SESSIONID)) || - ((FAL_FIELD_FLG_TST(rule->field_flg, FAL_ACL_FIELD_MAC_STAG_VID)) && - (rule->stag_vid_op != FAL_ACL_FIELD_MASK))) - { - SSDK_DEBUG("select L2 MISC rule\n"); - l2_rule_type_map |= (1<field_flg, FAL_ACL_FIELD_MAC_STAG_VID)) - { - SSDK_DEBUG("select VLAN rule\n"); - l2_rule_type_map |= (1<field_flg, FAL_ACL_FIELD_SNAP)) || - (FAL_FIELD_FLG_TST(rule->field_flg, FAL_ACL_FIELD_ETHERNET)) || - (FAL_FIELD_FLG_TST(rule->field_flg, FAL_ACL_FIELD_FAKE_MAC_HEADER))) - { - SSDK_DEBUG("select MAC DA rule\n"); - l2_rule_type_map |= (1<field_flg[0], rule->field_flg[1]); - - if(FAL_FIELD_FLG_TST(rule->field_flg, FAL_ACL_FIELD_L4_SPORT) || - FAL_FIELD_FLG_TST(rule->field_flg, FAL_ACL_FIELD_IP4_SIP) || - FAL_FIELD_FLG_TST(rule->field_flg, FAL_ACL_FIELD_ICMP_TYPE) || - FAL_FIELD_FLG_TST(rule->field_flg, FAL_ACL_FIELD_ICMP_CODE)) - { - *rule_type_map |= (1<field_flg, FAL_ACL_FIELD_L4_DPORT) || - FAL_FIELD_FLG_TST(rule->field_flg, FAL_ACL_FIELD_IP4_DIP)) - { - *rule_type_map |= (1<field_flg, FAL_ACL_FIELD_L3_LENGTH) || - FAL_FIELD_FLG_TST(rule->field_flg, FAL_ACL_FIELD_IP_DSCP) || - FAL_FIELD_FLG_TST(rule->field_flg, FAL_ACL_FIELD_FIRST_FRAGMENT) || - FAL_FIELD_FLG_TST(rule->field_flg, FAL_ACL_FIELD_TCP_FLAG) || - FAL_FIELD_FLG_TST(rule->field_flg, FAL_ACL_FIELD_IPV4_OPTION) || - FAL_FIELD_FLG_TST(rule->field_flg, FAL_ACL_FIELD_L3_TTL) || - FAL_FIELD_FLG_TST(rule->field_flg, FAL_ACL_FIELD_L3_FRAGMENT) || - FAL_FIELD_FLG_TST(rule->field_flg, FAL_ACL_FIELD_AH_HEADER) || - FAL_FIELD_FLG_TST(rule->field_flg, FAL_ACL_FIELD_ESP_HEADER) || - FAL_FIELD_FLG_TST(rule->field_flg, FAL_ACL_FIELD_IP_PROTO)) - { - *rule_type_map |= (1<field_flg, FAL_ACL_FIELD_IP_PKT_TYPE)) - { - *rule_type_map |= (1<field_flg, FAL_ACL_FIELD_L3_FRAGMENT)) - { - *rule_type_map |= (1<field_flg[0], rule->field_flg[1]); - - if(FAL_FIELD_FLG_TST(rule->field_flg, FAL_ACL_FIELD_L4_SPORT) || - FAL_FIELD_FLG_TST(rule->field_flg, FAL_ACL_FIELD_ICMP_TYPE) || - FAL_FIELD_FLG_TST(rule->field_flg, FAL_ACL_FIELD_ICMP_CODE)) - { - *rule_type_map |= (1<field_flg, FAL_ACL_FIELD_IP6_SIP)) - { - if(rule->src_ip6_mask.ul[3] != 0 || rule->src_ip6_mask.ul[2]&0x0000ffff) - *rule_type_map |= (1<src_ip6_mask.ul[1] != 0 || rule->src_ip6_mask.ul[2]&0xffff0000) - *rule_type_map |= (1<src_ip6_mask.ul[0] != 0 ) - *rule_type_map |= (1<field_flg, FAL_ACL_FIELD_L4_DPORT)) - { - *rule_type_map |= (1<field_flg, FAL_ACL_FIELD_IP6_DIP)) - { - if(rule->dest_ip6_mask.ul[3] != 0 || rule->dest_ip6_mask.ul[2]&0x0000ffff) - *rule_type_map |= (1<dest_ip6_mask.ul[1] != 0 || rule->dest_ip6_mask.ul[2]&0xffff0000) - *rule_type_map |= (1<dest_ip6_mask.ul[0] != 0 ) - *rule_type_map |= (1<field_flg, FAL_ACL_FIELD_L3_LENGTH) || - FAL_FIELD_FLG_TST(rule->field_flg, FAL_ACL_FIELD_IP_DSCP) || - FAL_FIELD_FLG_TST(rule->field_flg, FAL_ACL_FIELD_FIRST_FRAGMENT) || - FAL_FIELD_FLG_TST(rule->field_flg, FAL_ACL_FIELD_TCP_FLAG) || - FAL_FIELD_FLG_TST(rule->field_flg, FAL_ACL_FIELD_L3_TTL) || - FAL_FIELD_FLG_TST(rule->field_flg, FAL_ACL_FIELD_L3_FRAGMENT)|| - FAL_FIELD_FLG_TST(rule->field_flg, FAL_ACL_FIELD_ESP_HEADER) || - FAL_FIELD_FLG_TST(rule->field_flg, FAL_ACL_FIELD_MOBILITY_HEADER) || - FAL_FIELD_FLG_TST(rule->field_flg, FAL_ACL_FIELD_FRAGMENT_HEADER)|| - FAL_FIELD_FLG_TST(rule->field_flg, FAL_ACL_FIELD_OTHER_EXT_HEADER)|| - FAL_FIELD_FLG_TST(rule->field_flg, FAL_ACL_FIELD_AH_HEADER) || - FAL_FIELD_FLG_TST(rule->field_flg, FAL_ACL_FIELD_IP_PROTO)) - { - *rule_type_map |= (1<field_flg, FAL_ACL_FIELD_IP_PKT_TYPE)) - { - *rule_type_map |= (1<field_flg, FAL_ACL_FIELD_L3_FRAGMENT)) - { - *rule_type_map |= (1<field_flg[0], rule->field_flg[1]); - - if(FAL_FIELD_FLG_TST(rule->field_flg, FAL_ACL_FIELD_UDF0)) - { - *rule_type_map |= (1<field_flg, FAL_ACL_FIELD_UDF3)) - { - *rule_type_map |= (1<field_flg, FAL_ACL_FIELD_UDF1) && - rule->udf1_op != FAL_ACL_FIELD_MASK) - { - *rule_type_map |= (1<field_flg, FAL_ACL_FIELD_UDF1) || - FAL_FIELD_FLG_TST(rule->field_flg, FAL_ACL_FIELD_UDF2)) - { - *rule_type_map |= (1<field_flg, FAL_ACL_FIELD_MAC_DA)) - { - macrule->mac[5] = rule->dest_mac_val.uc[0]; - macrule->mac[4] = rule->dest_mac_val.uc[1]; - macrule->mac[3] = rule->dest_mac_val.uc[2]; - macrule->mac[2] = rule->dest_mac_val.uc[3]; - macrule->mac[1] = rule->dest_mac_val.uc[4]; - macrule->mac[0] = rule->dest_mac_val.uc[5]; - macrule_mask->mac_mask[5] = rule->dest_mac_mask.uc[0]; - macrule_mask->mac_mask[4] = rule->dest_mac_mask.uc[1]; - macrule_mask->mac_mask[3] = rule->dest_mac_mask.uc[2]; - macrule_mask->mac_mask[2] = rule->dest_mac_mask.uc[3]; - macrule_mask->mac_mask[1] = rule->dest_mac_mask.uc[4]; - macrule_mask->mac_mask[0] = rule->dest_mac_mask.uc[5]; - } - } - else - { - if(FAL_FIELD_FLG_TST(rule->field_flg, FAL_ACL_FIELD_MAC_SA)) - { - macrule->mac[5] = rule->src_mac_val.uc[0]; - macrule->mac[4] = rule->src_mac_val.uc[1]; - macrule->mac[3] = rule->src_mac_val.uc[2]; - macrule->mac[2] = rule->src_mac_val.uc[3]; - macrule->mac[1] = rule->src_mac_val.uc[4]; - macrule->mac[0] = rule->src_mac_val.uc[5]; - macrule_mask->mac_mask[5] = rule->src_mac_mask.uc[0]; - macrule_mask->mac_mask[4] = rule->src_mac_mask.uc[1]; - macrule_mask->mac_mask[3] = rule->src_mac_mask.uc[2]; - macrule_mask->mac_mask[2] = rule->src_mac_mask.uc[3]; - macrule_mask->mac_mask[1] = rule->src_mac_mask.uc[4]; - macrule_mask->mac_mask[0] = rule->src_mac_mask.uc[5]; - } - } - - if(FAL_FIELD_FLG_TST(rule->field_flg, FAL_ACL_FIELD_IP)) - { - macrule->is_ip = rule->is_ip_val; - macrule_mask->is_ip_mask = 1; - } - if(FAL_FIELD_FLG_TST(rule->field_flg, FAL_ACL_FIELD_IPV6)) - { - macrule->is_ipv6 = rule->is_ipv6_val; - macrule_mask->is_ipv6_mask = 1; - } - if(FAL_FIELD_FLG_TST(rule->field_flg, FAL_ACL_FIELD_ETHERNET)) - { - macrule->is_ethernet = rule->is_ethernet_val; - macrule_mask->is_ethernet_mask = 1; - } - if(FAL_FIELD_FLG_TST(rule->field_flg, FAL_ACL_FIELD_SNAP)) - { - macrule->is_snap = rule->is_snap_val; - macrule_mask->is_snap_mask = 1; - } - if(FAL_FIELD_FLG_TST(rule->field_flg, FAL_ACL_FIELD_FAKE_MAC_HEADER)) - { - macrule->is_fake_mac_header = rule->is_fake_mac_header_val; - macrule_mask->is_fake_mac_header_mask = 1; - } - - return SW_OK; -} - -static sw_error_t _adpt_hppe_acl_vlan_rule_sw_2_hw(fal_acl_rule_t *rule, - union ipo_rule_reg_u *hw_reg, union ipo_mask_reg_u *hw_mask) -{ - ADPT_HPPE_ACL_VLAN_RULE * vlanrule = (ADPT_HPPE_ACL_VLAN_RULE *)hw_reg; - ADPT_HPPE_ACL_VLAN_RULE_MASK *vlanrule_mask = (ADPT_HPPE_ACL_VLAN_RULE_MASK *)hw_mask; - - /*ctag*/ - if(FAL_FIELD_FLG_TST(rule->field_flg, FAL_ACL_FIELD_MAC_CTAG_VID)) - { - if(FAL_ACL_FIELD_MASK == rule->ctag_vid_op) - { - vlanrule->cvid = rule->ctag_vid_val; - vlanrule_mask->cvid_mask = rule->ctag_vid_mask; - } - else - { - a_uint16_t min, max; - if(FAL_ACL_FIELD_LE == rule->ctag_vid_op) - { - min = 0; - max = rule->ctag_vid_val; - } - else if(FAL_ACL_FIELD_GE == rule->ctag_vid_op) - { - min = rule->ctag_vid_val; - max = 0xfff; - } - else if(FAL_ACL_FIELD_RANGE == rule->ctag_vid_op) - { - min = rule->ctag_vid_val; - max = rule->ctag_vid_mask; - } - else - return SW_NOT_SUPPORTED; - vlanrule->cvid = min; - vlanrule_mask->cvid_mask = max; - hw_reg->bf.range_en = 1; - } - } - if(FAL_FIELD_FLG_TST(rule->field_flg, FAL_ACL_FIELD_MAC_CTAG_PRI)) - { - vlanrule->cpcp = rule->ctag_pri_val; - vlanrule_mask->cpcp_mask = rule->ctag_pri_mask; - } - if(FAL_FIELD_FLG_TST(rule->field_flg, FAL_ACL_FIELD_MAC_CTAG_CFI)) - { - vlanrule->cdei = rule->ctag_cfi_val; - vlanrule_mask->cdei_mask = rule->ctag_cfi_mask; - } - if(FAL_FIELD_FLG_TST(rule->field_flg, FAL_ACL_FIELD_MAC_CTAGGED)) - { - vlanrule->ctag_fmt = rule->ctagged_val; - vlanrule_mask->ctag_fmt_mask = rule->ctagged_mask; - } - /*stag*/ - if(FAL_FIELD_FLG_TST(rule->field_flg, FAL_ACL_FIELD_MAC_STAG_VID) && - (rule->stag_vid_op == FAL_ACL_FIELD_MASK)) - { - vlanrule->svid = rule->stag_vid_val; - vlanrule_mask->svid_mask = rule->stag_vid_mask; - } - if(FAL_FIELD_FLG_TST(rule->field_flg, FAL_ACL_FIELD_MAC_STAG_PRI)) - { - vlanrule->spcp = rule->stag_pri_val; - vlanrule_mask->spcp_mask = rule->stag_pri_mask; - } - if(FAL_FIELD_FLG_TST(rule->field_flg, FAL_ACL_FIELD_MAC_STAG_DEI)) - { - vlanrule->sdei = rule->stag_dei_val; - vlanrule_mask->sdei_mask = rule->stag_dei_mask; - } - if(FAL_FIELD_FLG_TST(rule->field_flg, FAL_ACL_FIELD_MAC_STAGGED)) - { - vlanrule->stag_fmt = rule->stagged_val; - vlanrule_mask->stag_fmt_mask = rule->stagged_mask; - } - /*vsi*/ - if(FAL_FIELD_FLG_TST(rule->field_flg, FAL_ACL_FIELD_VSI_VALID)) - { - vlanrule->vsi_valid= rule->vsi_valid; - vlanrule_mask->vsi_valid_mask = rule->vsi_valid_mask; - } - if(FAL_FIELD_FLG_TST(rule->field_flg, FAL_ACL_FIELD_VSI)) - { - vlanrule->vsi= rule->vsi; - vlanrule_mask->vsi_mask = rule->vsi_mask; - } - if(FAL_FIELD_FLG_TST(rule->field_flg, FAL_ACL_FIELD_IP)) - { - vlanrule->is_ip = rule->is_ip_val; - vlanrule_mask->is_ip_mask = 1; - } - if(FAL_FIELD_FLG_TST(rule->field_flg, FAL_ACL_FIELD_IPV6)) - { - vlanrule->is_ipv6 = rule->is_ipv6_val; - vlanrule_mask->is_ipv6_mask = 1; - } - if(FAL_FIELD_FLG_TST(rule->field_flg, FAL_ACL_FIELD_ETHERNET)) - { - vlanrule->is_ethernet = rule->is_ethernet_val; - vlanrule_mask->is_ethernet_mask = 1; - } - if(FAL_FIELD_FLG_TST(rule->field_flg, FAL_ACL_FIELD_SNAP)) - { - vlanrule->is_snap = rule->is_snap_val; - vlanrule_mask->is_snap_mask = 1; - } - if(FAL_FIELD_FLG_TST(rule->field_flg, FAL_ACL_FIELD_FAKE_MAC_HEADER)) - { - vlanrule->is_fake_mac_header = rule->is_fake_mac_header_val; - vlanrule_mask->is_fake_mac_header_mask = 1; - } - - return SW_OK; -} - - -static sw_error_t _adpt_hppe_acl_l2_misc_rule_sw_2_hw(fal_acl_rule_t *rule, - union ipo_rule_reg_u *hw_reg, union ipo_mask_reg_u *hw_mask) -{ - ADPT_HPPE_ACL_L2MISC_RULE * l2misc_rule = (ADPT_HPPE_ACL_L2MISC_RULE *)hw_reg; - ADPT_HPPE_ACL_L2MISC_RULE_MASK *l2misc_mask = (ADPT_HPPE_ACL_L2MISC_RULE_MASK *)hw_mask; - - /*stag*/ - if(FAL_FIELD_FLG_TST(rule->field_flg, FAL_ACL_FIELD_MAC_STAG_VID)) - { - if(FAL_ACL_FIELD_MASK == rule->stag_vid_op) - { - l2misc_rule->svid = rule->stag_vid_val; - l2misc_mask->svid_mask = rule->stag_vid_mask; - } - else - { - a_uint16_t min, max; - if(FAL_ACL_FIELD_LE == rule->stag_vid_op) - { - min = 0; - max = rule->stag_vid_val; - } - else if(FAL_ACL_FIELD_GE == rule->stag_vid_op) - { - min = rule->stag_vid_val; - max = 0xfff; - } - else if(FAL_ACL_FIELD_RANGE == rule->stag_vid_op) - { - min = rule->stag_vid_val; - max = rule->stag_vid_mask; - } - else - { - return SW_NOT_SUPPORTED; - } - l2misc_rule->svid = min; - l2misc_mask->svid_mask = max; - hw_reg->bf.range_en = 1; - } - } - if(FAL_FIELD_FLG_TST(rule->field_flg, FAL_ACL_FIELD_MAC_ETHTYPE)) - { - l2misc_rule->l2prot = rule->ethtype_val; - l2misc_mask->l2prot_mask = rule->ethtype_mask; - } - if(FAL_FIELD_FLG_TST(rule->field_flg, FAL_ACL_FIELD_PPPOE_SESSIONID)) - { - l2misc_rule->pppoe_sessionid = rule->pppoe_sessionid; - l2misc_mask->pppoe_sessionid_mask = rule->pppoe_sessionid_mask; - } - if(FAL_FIELD_FLG_TST(rule->field_flg, FAL_ACL_FIELD_IP)) - { - l2misc_rule->is_ip = rule->is_ip_val; - l2misc_mask->is_ip_mask = 1; - } - if(FAL_FIELD_FLG_TST(rule->field_flg, FAL_ACL_FIELD_IPV6)) - { - l2misc_rule->is_ipv6 = rule->is_ipv6_val; - l2misc_mask->is_ipv6_mask = 1; - } - if(FAL_FIELD_FLG_TST(rule->field_flg, FAL_ACL_FIELD_ETHERNET)) - { - l2misc_rule->is_ethernet = rule->is_ethernet_val; - l2misc_mask->is_ethernet_mask = 1; - } - if(FAL_FIELD_FLG_TST(rule->field_flg, FAL_ACL_FIELD_SNAP)) - { - l2misc_rule->is_snap = rule->is_snap_val; - l2misc_mask->is_snap_mask = 1; - } - if(FAL_FIELD_FLG_TST(rule->field_flg, FAL_ACL_FIELD_FAKE_MAC_HEADER)) - { - l2misc_rule->is_fake_mac_header = rule->is_fake_mac_header_val; - l2misc_mask->is_fake_mac_header_mask = 1; - } - - return SW_OK; -} - -static sw_error_t _adpt_hppe_acl_ipv4_rule_sw_2_hw(fal_acl_rule_t *rule, a_uint32_t is_ip_da, - union ipo_rule_reg_u *hw_reg, union ipo_mask_reg_u *hw_mask) -{ - ADPT_HPPE_ACL_IPV4_RULE * ipv4rule = (ADPT_HPPE_ACL_IPV4_RULE *)hw_reg; - ADPT_HPPE_ACL_IPV4_RULE_MASK *ipv4rule_mask = (ADPT_HPPE_ACL_IPV4_RULE_MASK *)hw_mask; - - if(is_ip_da) - { - if(FAL_FIELD_FLG_TST(rule->field_flg, FAL_ACL_FIELD_IP4_DIP)) - { - ipv4rule->ip_0 = rule->dest_ip4_val&0xffff; - ipv4rule->ip_1 = (rule->dest_ip4_val>>16)&0xffff; - ipv4rule_mask->ip_mask_0 = rule->dest_ip4_mask&0xffff; - ipv4rule_mask->ip_mask_1 = (rule->dest_ip4_mask)>>16&0xffff; - } - if(FAL_FIELD_FLG_TST(rule->field_flg, FAL_ACL_FIELD_L4_DPORT)) - { - if(FAL_ACL_FIELD_MASK == rule->dest_l4port_op) - { - ipv4rule->l4_port = rule->dest_l4port_val; - ipv4rule_mask->l4_port_mask = rule->dest_l4port_mask; - } - else - { - a_uint16_t min, max; - if(FAL_ACL_FIELD_LE == rule->dest_l4port_op) - { - min = 0; - max = rule->dest_l4port_val; - } - else if(FAL_ACL_FIELD_GE == rule->dest_l4port_op) - { - min = rule->dest_l4port_val; - max = 0xffff; - } - else if(FAL_ACL_FIELD_RANGE == rule->dest_l4port_op) - { - min = rule->dest_l4port_val; - max = rule->dest_l4port_mask; - } - else - return SW_NOT_SUPPORTED; - ipv4rule->l4_port = min; - ipv4rule_mask->l4_port_mask = max; - hw_reg->bf.range_en = 1; - } - } - } - else - { - if(FAL_FIELD_FLG_TST(rule->field_flg, FAL_ACL_FIELD_IP4_SIP)) - { - ipv4rule->ip_0 = rule->src_ip4_val&0xffff; - ipv4rule->ip_1 = (rule->src_ip4_val>>16)&0xffff; - ipv4rule_mask->ip_mask_0 = rule->src_ip4_mask&0xffff; - ipv4rule_mask->ip_mask_1 = (rule->src_ip4_mask>>16)&0xffff; - } - if(FAL_FIELD_FLG_TST(rule->field_flg, FAL_ACL_FIELD_L4_SPORT)) - { - if(FAL_ACL_FIELD_MASK == rule->src_l4port_op) - { - ipv4rule->l4_port = rule->src_l4port_val; - ipv4rule_mask->l4_port_mask = rule->src_l4port_mask; - } - else - { - a_uint16_t min, max; - if(FAL_ACL_FIELD_LE == rule->src_l4port_op) - { - min = 0; - max = rule->src_l4port_val; - } - else if(FAL_ACL_FIELD_GE == rule->src_l4port_op) - { - min = rule->src_l4port_val; - max = 0xffff; - } - else if(FAL_ACL_FIELD_RANGE == rule->src_l4port_op) - { - min = rule->src_l4port_val; - max = rule->src_l4port_mask; - } - else - return SW_NOT_SUPPORTED; - ipv4rule->l4_port = min; - ipv4rule_mask->l4_port_mask = max; - hw_reg->bf.range_en = 1; - } - } - } - - if(FAL_FIELD_FLG_TST(rule->field_flg, FAL_ACL_FIELD_ICMP_CODE) || - FAL_FIELD_FLG_TST(rule->field_flg, FAL_ACL_FIELD_ICMP_TYPE)) - { - if(FAL_ACL_FIELD_MASK == rule->icmp_type_code_op) - { - ipv4rule->l4_port = (rule->icmp_type_val<<8)|rule->icmp_code_val; - ipv4rule_mask->l4_port_mask = (rule->icmp_type_mask<<8)|rule->icmp_code_mask; - } - else - { - a_uint16_t min, max; - if(FAL_ACL_FIELD_LE == rule->icmp_type_code_op) - { - min = 0; - max = (rule->icmp_type_val<<8)|rule->icmp_code_val; - } - else if(FAL_ACL_FIELD_GE == rule->icmp_type_code_op) - { - min = (rule->icmp_type_val<<8)|rule->icmp_code_val; - max = 0xffff; - } - else if(FAL_ACL_FIELD_RANGE == rule->icmp_type_code_op) - { - min = (rule->icmp_type_val<<8)|rule->icmp_code_val; - max = (rule->icmp_type_mask<<8)|rule->icmp_code_mask; - } - else - return SW_NOT_SUPPORTED; - ipv4rule->l4_port = min; - ipv4rule_mask->l4_port_mask = max; - hw_reg->bf.range_en = 1; - } - } - - if(FAL_FIELD_FLG_TST(rule->field_flg, FAL_ACL_FIELD_IP)) - { - ipv4rule->is_ip = rule->is_ip_val; - ipv4rule_mask->is_ip_mask = 1; - } - if(FAL_FIELD_FLG_TST(rule->field_flg, FAL_ACL_FIELD_L3_FRAGMENT)) - { - ipv4rule->l3_fragment = rule->is_fragement_val; - ipv4rule_mask->l3_fragment_mask = rule->is_fragement_mask; - } - if(FAL_FIELD_FLG_TST(rule->field_flg, FAL_ACL_FIELD_IP_PKT_TYPE)) - { - ipv4rule->l3_packet_type = rule->l3_pkt_type; - ipv4rule_mask->l3_packet_type_mask = rule->l3_pkt_type_mask; - } - - return SW_OK; -} - -/*ip_bit_range: 0 mean DIP0 or SIP0, 1 mean DIP1 or SIP1, 2 mean DIP2 or SIP2,*/ -static sw_error_t _adpt_hppe_acl_ipv6_rule_sw_2_hw(fal_acl_rule_t *rule, a_uint32_t is_ip_da, a_uint32_t ip_bit_range, - union ipo_rule_reg_u *hw_reg, union ipo_mask_reg_u *hw_mask) -{ - ADPT_HPPE_ACL_IPV6_RULE * ipv6rule = (ADPT_HPPE_ACL_IPV6_RULE *)hw_reg; - ADPT_HPPE_ACL_IPV6_RULE_MASK *ipv6rule_mask = (ADPT_HPPE_ACL_IPV6_RULE_MASK *)hw_mask; - - if(is_ip_da) - { - if(FAL_FIELD_FLG_TST(rule->field_flg, FAL_ACL_FIELD_IP6_DIP)) - { - if(ip_bit_range == 0) - { - ipv6rule->ip_port = rule->dest_ip6_val.ul[3]&0xffff; - ipv6rule->ip_ext_1 = (rule->dest_ip6_val.ul[3]>>16)&0xffff; - ipv6rule->ip_ext_2 = (rule->dest_ip6_val.ul[2])&0xffff; - ipv6rule_mask->ip_port_mask = rule->dest_ip6_mask.ul[3]&0xffff; - ipv6rule_mask->ip_ext_1_mask = (rule->dest_ip6_mask.ul[3]>>16)&0xffff; - ipv6rule_mask->ip_ext_2_mask = (rule->dest_ip6_mask.ul[2])&0xffff; - } - else if(ip_bit_range == 1) - { - ipv6rule->ip_port = (rule->dest_ip6_val.ul[2]>>16)&0xffff; - ipv6rule->ip_ext_1 = (rule->dest_ip6_val.ul[1])&0xffff; - ipv6rule->ip_ext_2 = (rule->dest_ip6_val.ul[1]>>16)&0xffff; - ipv6rule_mask->ip_port_mask = (rule->dest_ip6_mask.ul[2]>>16)&0xffff; - ipv6rule_mask->ip_ext_1_mask = (rule->dest_ip6_mask.ul[1])&0xffff; - ipv6rule_mask->ip_ext_2_mask = (rule->dest_ip6_mask.ul[1]>>16)&0xffff; - } - else if(ip_bit_range == 2) - { - ipv6rule->ip_ext_1 = (rule->dest_ip6_val.ul[0])&0xffff; - ipv6rule->ip_ext_2 = (rule->dest_ip6_val.ul[0]>>16)&0xffff; - ipv6rule_mask->ip_ext_1_mask = (rule->dest_ip6_mask.ul[0])&0xffff; - ipv6rule_mask->ip_ext_2_mask = (rule->dest_ip6_mask.ul[0]>>16)&0xffff; - } - } - if((ip_bit_range == 2) && (FAL_FIELD_FLG_TST(rule->field_flg, FAL_ACL_FIELD_L4_DPORT))) - { - if(FAL_ACL_FIELD_MASK == rule->dest_l4port_op) - { - ipv6rule->ip_port = rule->dest_l4port_val; - ipv6rule_mask->ip_port_mask = rule->dest_l4port_mask; - } - else - { - a_uint16_t min, max; - if(FAL_ACL_FIELD_LE == rule->dest_l4port_op) - { - min = 0; - max = rule->dest_l4port_val; - } - else if(FAL_ACL_FIELD_GE == rule->dest_l4port_op) - { - min = rule->dest_l4port_val; - max = 0xffff; - } - else if(FAL_ACL_FIELD_RANGE == rule->dest_l4port_op) - { - min = rule->dest_l4port_val; - max = rule->dest_l4port_mask; - } - else - return SW_NOT_SUPPORTED; - ipv6rule->ip_port = min; - ipv6rule_mask->ip_port_mask = max; - hw_reg->bf.range_en = 1; - } - } - } - else - { - if(FAL_FIELD_FLG_TST(rule->field_flg, FAL_ACL_FIELD_IP6_SIP)) - { - if(ip_bit_range == 0) - { - ipv6rule->ip_port = rule->src_ip6_val.ul[3]&0xffff; - ipv6rule->ip_ext_1 = (rule->src_ip6_val.ul[3]>>16)&0xffff; - ipv6rule->ip_ext_2 = (rule->src_ip6_val.ul[2])&0xffff; - ipv6rule_mask->ip_port_mask = rule->src_ip6_mask.ul[3]&0xffff; - ipv6rule_mask->ip_ext_1_mask = (rule->src_ip6_mask.ul[3]>>16)&0xffff; - ipv6rule_mask->ip_ext_2_mask = (rule->src_ip6_mask.ul[2])&0xffff; - } - else if(ip_bit_range == 1) - { - ipv6rule->ip_port = (rule->src_ip6_val.ul[2]>>16)&0xffff; - ipv6rule->ip_ext_1 = (rule->src_ip6_val.ul[1])&0xffff; - ipv6rule->ip_ext_2 = (rule->src_ip6_val.ul[1]>>16)&0xffff; - ipv6rule_mask->ip_port_mask = (rule->src_ip6_mask.ul[2]>>16)&0xffff; - ipv6rule_mask->ip_ext_1_mask = (rule->src_ip6_mask.ul[1])&0xffff; - ipv6rule_mask->ip_ext_2_mask = (rule->src_ip6_mask.ul[1]>>16)&0xffff; - } - else if(ip_bit_range == 2) - { - ipv6rule->ip_ext_1 = (rule->src_ip6_val.ul[0])&0xffff; - ipv6rule->ip_ext_2 = (rule->src_ip6_val.ul[0]>>16)&0xffff; - ipv6rule_mask->ip_ext_1_mask = (rule->src_ip6_mask.ul[0])&0xffff; - ipv6rule_mask->ip_ext_2_mask = (rule->src_ip6_mask.ul[0]>>16)&0xffff; - } - } - if((ip_bit_range == 2) && (FAL_FIELD_FLG_TST(rule->field_flg, FAL_ACL_FIELD_L4_SPORT))) - { - if(FAL_ACL_FIELD_MASK == rule->src_l4port_op) - { - ipv6rule->ip_port = rule->src_l4port_val; - ipv6rule_mask->ip_port_mask = rule->src_l4port_mask; - } - else - { - a_uint16_t min, max; - if(FAL_ACL_FIELD_LE == rule->src_l4port_op) - { - min = 0; - max = rule->src_l4port_val; - } - else if(FAL_ACL_FIELD_GE == rule->src_l4port_op) - { - min = rule->src_l4port_val; - max = 0xffff; - } - else if(FAL_ACL_FIELD_RANGE == rule->src_l4port_op) - { - min = rule->src_l4port_val; - max = rule->src_l4port_mask; - } - else - return SW_NOT_SUPPORTED; - ipv6rule->ip_port = min; - ipv6rule_mask->ip_port_mask = max; - hw_reg->bf.range_en = 1; - } - } - } - - if(FAL_FIELD_FLG_TST(rule->field_flg, FAL_ACL_FIELD_ICMP_CODE) || - FAL_FIELD_FLG_TST(rule->field_flg, FAL_ACL_FIELD_ICMP_TYPE)) - { - if(FAL_ACL_FIELD_MASK == rule->icmp_type_code_op) - { - ipv6rule->ip_port = (rule->icmp_type_val<<8)|rule->icmp_code_val; - ipv6rule_mask->ip_port_mask = (rule->icmp_type_mask<<8)|rule->icmp_code_mask; - } - else - { - a_uint16_t min, max; - if(FAL_ACL_FIELD_LE == rule->icmp_type_code_op) - { - min = 0; - max = (rule->icmp_type_val<<8)|rule->icmp_code_val; - } - else if(FAL_ACL_FIELD_GE == rule->icmp_type_code_op) - { - min = (rule->icmp_type_val<<8)|rule->icmp_code_val; - max = 0xffff; - } - else if(FAL_ACL_FIELD_RANGE == rule->icmp_type_code_op) - { - min = (rule->icmp_type_val<<8)|rule->icmp_code_val; - max = (rule->icmp_type_mask<<8)|rule->icmp_code_mask; - } - else - return SW_NOT_SUPPORTED; - ipv6rule->ip_port = min; - ipv6rule_mask->ip_port_mask = max; - hw_reg->bf.range_en = 1; - } - } - if(FAL_FIELD_FLG_TST(rule->field_flg, FAL_ACL_FIELD_L3_FRAGMENT)) - { - ipv6rule->l3_fragment = rule->is_fragement_val; - ipv6rule_mask->l3_fragment_mask = rule->is_fragement_mask; - } - if(FAL_FIELD_FLG_TST(rule->field_flg, FAL_ACL_FIELD_IP_PKT_TYPE)) - { - ipv6rule->l3_packet_type = rule->l3_pkt_type; - ipv6rule_mask->l3_packet_type_mask = rule->l3_pkt_type_mask; - } - return SW_OK; -} - -static sw_error_t _adpt_hppe_acl_ipmisc_rule_sw_2_hw(fal_acl_rule_t *rule, - union ipo_rule_reg_u *hw_reg, union ipo_mask_reg_u *hw_mask) -{ - ADPT_HPPE_ACL_IPMISC_RULE * ipmisc_rule = (ADPT_HPPE_ACL_IPMISC_RULE *)hw_reg; - ADPT_HPPE_ACL_IPMISC_RULE_MASK *ipmisc_mask = (ADPT_HPPE_ACL_IPMISC_RULE_MASK *)hw_mask; - - if(FAL_FIELD_FLG_TST(rule->field_flg, FAL_ACL_FIELD_L3_LENGTH)) - { - if(FAL_ACL_FIELD_MASK == rule->l3_length_op) - { - ipmisc_rule->l3_length = rule->l3_length; - ipmisc_mask->l3_length_mask = rule->l3_length_mask; - } - else - { - a_uint16_t min, max; - if(FAL_ACL_FIELD_LE == rule->l3_length_op) - { - min = 0; - max = rule->l3_length; - } - else if(FAL_ACL_FIELD_GE == rule->l3_length_op) - { - min = rule->l3_length; - max = 0xffff; - } - else if(FAL_ACL_FIELD_RANGE == rule->l3_length_op) - { - min = rule->l3_length; - max = rule->l3_length_mask; - } - else - return SW_NOT_SUPPORTED; - ipmisc_rule->l3_length = min; - ipmisc_mask->l3_length_mask = max; - hw_reg->bf.range_en = 1; - } - } - if(FAL_FIELD_FLG_TST(rule->field_flg, FAL_ACL_FIELD_IP_PROTO)) - { - ipmisc_rule->l3_prot = rule->ip_proto_val; - ipmisc_mask->l3_prot_mask = rule->ip_proto_mask; - } - if(FAL_FIELD_FLG_TST(rule->field_flg, FAL_ACL_FIELD_IP_DSCP)) - { - ipmisc_rule->l3_dscp_tc = rule->ip_dscp_val; - ipmisc_mask->l3_dscp_tc_mask = rule->ip_dscp_mask; - } - if(FAL_FIELD_FLG_TST(rule->field_flg, FAL_ACL_FIELD_FIRST_FRAGMENT)) - { - ipmisc_rule->first_fragment = rule->is_first_frag_val; - ipmisc_mask->first_fragment_mask = 1; - } - if(FAL_FIELD_FLG_TST(rule->field_flg, FAL_ACL_FIELD_TCP_FLAG)) - { - ipmisc_rule->tcp_flags = rule->tcp_flag_val; - ipmisc_mask->tcp_flags_mask = rule->tcp_flag_mask; - } - if(FAL_FIELD_FLG_TST(rule->field_flg, FAL_ACL_FIELD_IPV4_OPTION)) - { - ipmisc_rule->ipv4_option_state = rule->is_ipv4_option_val; - ipmisc_mask->ipv4_option_state_mask = 1; - } - if(FAL_FIELD_FLG_TST(rule->field_flg, FAL_ACL_FIELD_L3_TTL)) - { - ipmisc_rule->l3_ttl = rule->l3_ttl; - ipmisc_mask->l3_ttl_mask = rule->l3_ttl_mask; - } - if(FAL_FIELD_FLG_TST(rule->field_flg, FAL_ACL_FIELD_AH_HEADER)) - { - ipmisc_rule->ah_header = rule->is_ah_header_val; - ipmisc_mask->ah_header_mask = 1; - } - if(FAL_FIELD_FLG_TST(rule->field_flg, FAL_ACL_FIELD_ESP_HEADER)) - { - ipmisc_rule->esp_header = rule->is_esp_header_val; - ipmisc_mask->esp_header_mask = 1; - } - if(FAL_FIELD_FLG_TST(rule->field_flg, FAL_ACL_FIELD_MOBILITY_HEADER)) - { - ipmisc_rule->mobility_header = rule->is_mobility_header_val; - ipmisc_mask->mobility_header_mask = 1; - } - if(FAL_FIELD_FLG_TST(rule->field_flg, FAL_ACL_FIELD_FRAGMENT_HEADER)) - { - ipmisc_rule->fragment_header = rule->is_fragment_header_val; - ipmisc_mask->fragment_header_mask= 1; - } - if(FAL_FIELD_FLG_TST(rule->field_flg, FAL_ACL_FIELD_OTHER_EXT_HEADER)) - { - ipmisc_rule->other_header = rule->is_other_header_val; - ipmisc_mask->other_header_mask = 1; - } - if(FAL_FIELD_FLG_TST(rule->field_flg, FAL_ACL_FIELD_IPV6)) - { - ipmisc_rule->is_ipv6 = rule->is_ipv6_val; - ipmisc_mask->is_ipv6_mask = 1; - } - if(FAL_FIELD_FLG_TST(rule->field_flg, FAL_ACL_FIELD_L3_FRAGMENT)) - { - ipmisc_rule->l3_fragment = rule->is_fragement_val; - ipmisc_mask->l3_fragment_mask = 1; - } - return SW_OK; -} - -static sw_error_t _adpt_hppe_acl_udf_rule_sw_2_hw(fal_acl_rule_t *rule, a_uint32_t is_win1, - union ipo_rule_reg_u *hw_reg, union ipo_mask_reg_u *hw_mask) -{ - ADPT_HPPE_ACL_UDF_RULE * udfrule = (ADPT_HPPE_ACL_UDF_RULE *)hw_reg; - ADPT_HPPE_ACL_UDF_RULE_MASK *udfrule_mask = (ADPT_HPPE_ACL_UDF_RULE_MASK *)hw_mask; - - if(is_win1) - { - if(FAL_FIELD_FLG_TST(rule->field_flg, FAL_ACL_FIELD_UDF3)) - { - udfrule->udf2_valid = 1; - udfrule->udf2 = rule->udf3_val; - udfrule_mask->udf2_valid = 1; - udfrule_mask->udf2_mask = rule->udf3_mask; - } - if(FAL_FIELD_FLG_TST(rule->field_flg, FAL_ACL_FIELD_UDF2)) - { - udfrule->udf1_valid = 1; - udfrule->udf1 = rule->udf2_val; - udfrule_mask->udf1_valid = 1; - udfrule_mask->udf1_mask = rule->udf2_mask; - } - - if(FAL_FIELD_FLG_TST(rule->field_flg, FAL_ACL_FIELD_UDF1)) - { - udfrule->udf0_valid = 1; - udfrule_mask->udf0_valid = 1; - if(FAL_ACL_FIELD_MASK == rule->udf1_op) - { - udfrule->udf0 = rule->udf1_val; - udfrule_mask->udf0_mask = rule->udf1_mask; - } - else - { - a_uint16_t min, max; - if(FAL_ACL_FIELD_LE == rule->udf1_op) - { - min = 0; - max = rule->udf1_val; - } - else if(FAL_ACL_FIELD_GE == rule->udf1_op) - { - min = rule->udf1_val; - max = 0xffff; - } - else if(FAL_ACL_FIELD_RANGE == rule->udf1_op) - { - min = rule->udf1_val; - max = rule->udf1_mask; - } - else - return SW_NOT_SUPPORTED; - udfrule->udf0 = min; - udfrule_mask->udf0_mask = max; - hw_reg->bf.range_en = 1; - } - } - } - else - { - if(FAL_FIELD_FLG_TST(rule->field_flg, FAL_ACL_FIELD_UDF1) && - FAL_ACL_FIELD_MASK == rule->udf1_op) - { - udfrule->udf1_valid = 1; - udfrule->udf1 = rule->udf1_val; - udfrule_mask->udf1_valid = 1; - udfrule_mask->udf1_mask = rule->udf1_mask; - } - if(FAL_FIELD_FLG_TST(rule->field_flg, FAL_ACL_FIELD_UDF2)) - { - udfrule->udf2_valid = 1; - udfrule->udf2 = rule->udf2_val; - udfrule_mask->udf2_valid = 1; - udfrule_mask->udf2_mask = rule->udf2_mask; - } - - if(FAL_FIELD_FLG_TST(rule->field_flg, FAL_ACL_FIELD_UDF0)) - { - udfrule->udf0_valid = 1; - udfrule_mask->udf0_valid = 1; - if(FAL_ACL_FIELD_MASK == rule->udf0_op) - { - udfrule->udf0 = rule->udf0_val; - udfrule_mask->udf0_mask = rule->udf0_mask; - } - else - { - a_uint16_t min, max; - if(FAL_ACL_FIELD_LE == rule->udf0_op) - { - min = 0; - max = rule->udf0_val; - } - else if(FAL_ACL_FIELD_GE == rule->udf0_op) - { - min = rule->udf0_val; - max = 0xffff; - } - else if(FAL_ACL_FIELD_RANGE == rule->udf0_op) - { - min = rule->udf0_val; - max = rule->udf0_mask; - } - else - return SW_NOT_SUPPORTED; - udfrule->udf0 = min; - udfrule_mask->udf0_mask = max; - hw_reg->bf.range_en = 1; - } - } - } - - if(FAL_FIELD_FLG_TST(rule->field_flg, FAL_ACL_FIELD_IP)) - { - udfrule->is_ip = rule->is_ip_val; - udfrule_mask->is_ip = 1; - } - if(FAL_FIELD_FLG_TST(rule->field_flg, FAL_ACL_FIELD_IPV6)) - { - udfrule->is_ipv6= rule->is_ipv6_val; - udfrule_mask->is_ipv6 = 1; - } - return SW_OK; -} -static sw_error_t -_adpt_hppe_acl_action_sw_2_hw(a_uint32_t dev_id,fal_acl_rule_t *rule, union ipo_action_u *hw_act) -{ - if(FAL_ACTION_FLG_TST(rule->action_flg, FAL_ACL_ACTION_REDPT)) - { - a_uint32_t dest_type = FAL_ACL_DEST_TYPE(rule->ports); - a_uint32_t dest_val = FAL_ACL_DEST_VALUE(rule->ports); - - SSDK_DEBUG("rule->ports = %x\n", rule->ports); - - hw_act->bf.dest_info_change_en = 1; - if(dest_type == FAL_ACL_DEST_NEXTHOP) /*nexthop*/ - { - hw_act->bf.dest_info = - HPPE_ACL_DEST_INFO(HPPE_ACL_DEST_NEXTHOP, dest_val); - } - else if(FAL_ACL_DEST_TYPE(rule->ports) == FAL_ACL_DEST_PORT_ID)/*vp*/ - { - hw_act->bf.dest_info = - HPPE_ACL_DEST_INFO(HPPE_ACL_DEST_PORT_ID, dest_val); - } - else if(FAL_ACL_DEST_TYPE(rule->ports) == FAL_ACL_DEST_PORT_BMP)/*bitmap*/ - { - hw_act->bf.dest_info = - HPPE_ACL_DEST_INFO(HPPE_ACL_DEST_PORT_BMP, dest_val); - } - } - if(FAL_ACTION_FLG_TST(rule->action_flg, FAL_ACL_ACTION_PERMIT)) - { - hw_act->bf.dest_info_change_en = 1; - hw_act->bf.fwd_cmd = 0;/*forward*/ - } - if(FAL_ACTION_FLG_TST(rule->action_flg, FAL_ACL_ACTION_DENY)) - { - hw_act->bf.dest_info_change_en = 1; - hw_act->bf.fwd_cmd = 1;/*drop*/ - } - if(FAL_ACTION_FLG_TST(rule->action_flg, FAL_ACL_ACTION_CPYCPU)) - { - hw_act->bf.dest_info_change_en = 1; - hw_act->bf.fwd_cmd = 2;/*copy to cpu*/ - } - if(FAL_ACTION_FLG_TST(rule->action_flg, FAL_ACL_ACTION_RDTCPU)) - { - hw_act->bf.dest_info_change_en = 1; - hw_act->bf.fwd_cmd = 3;/*redirect to cpu*/ - } - if(FAL_ACTION_FLG_TST(rule->action_flg, FAL_ACL_ACTION_MIRROR)) - { - hw_act->bf.mirror_en= 1; - } - hw_act->bf.bypass_bitmap_0 = rule->bypass_bitmap & 0x3fff; - hw_act->bf.bypass_bitmap_1 = (rule->bypass_bitmap>>14) & 0x3ffff; - if(FAL_ACTION_FLG_TST(rule->action_flg, FAL_ACL_ACTION_REMARK_STAG_VID)) - { - hw_act->bf.svid_change_en = 1; - hw_act->bf.stag_fmt = rule->stag_fmt; - hw_act->bf.svid = rule->stag_vid; - } - if(FAL_ACTION_FLG_TST(rule->action_flg, FAL_ACL_ACTION_REMARK_STAG_PRI)) - { - hw_act->bf.stag_pcp_change_en = 1; - hw_act->bf.stag_pcp = rule->stag_pri; - } - if(FAL_ACTION_FLG_TST(rule->action_flg, FAL_ACL_ACTION_REMARK_STAG_DEI)) - { - hw_act->bf.stag_dei_change_en = 1; - hw_act->bf.stag_dei = rule->stag_dei; - } - if(FAL_ACTION_FLG_TST(rule->action_flg, FAL_ACL_ACTION_REMARK_CTAG_VID)) - { - hw_act->bf.cvid_change_en = 1; - hw_act->bf.ctag_fmt = rule->ctag_fmt; - hw_act->bf.cvid = rule->ctag_vid; - } - if(FAL_ACTION_FLG_TST(rule->action_flg, FAL_ACL_ACTION_REMARK_CTAG_PRI)) - { - hw_act->bf.ctag_pcp_change_en = 1; - hw_act->bf.ctag_pcp_0 = rule->ctag_pri&0x3; - hw_act->bf.ctag_pcp_1 = (rule->ctag_pri>>2)&0x1; - } - if(FAL_ACTION_FLG_TST(rule->action_flg, FAL_ACL_ACTION_REMARK_CTAG_CFI)) - { - hw_act->bf.ctag_dei_change_en = 1; - hw_act->bf.ctag_dei = rule->ctag_cfi; - } - if(FAL_ACTION_FLG_TST(rule->action_flg, FAL_ACL_ACTION_REMARK_DSCP)) - { - hw_act->bf.dscp_tc_change_en = 1; - hw_act->bf.dscp_tc = rule->dscp; -#if defined(CPPE) - if(adpt_hppe_chip_revision_get(dev_id) == CPPE_REVISION) - { - hw_act->bf.dscp_tc_mask = rule->dscp_mask; - } -#endif - } - if(FAL_ACTION_FLG_TST(rule->action_flg, FAL_ACL_ACTION_INT_DP)) - { - hw_act->bf.int_dp_change_en = 1; - hw_act->bf.int_dp = rule->int_dp; - } - if(FAL_ACTION_FLG_TST(rule->action_flg, FAL_ACL_ACTION_POLICER_EN)) - { - hw_act->bf.policer_en = 1; - hw_act->bf.policer_index = rule->policer_ptr; - } - if(FAL_ACTION_FLG_TST(rule->action_flg, FAL_ACL_ACTION_REMARK_QUEUE)) - { - hw_act->bf.qid_en = 1; - hw_act->bf.qid = rule->queue; - } - if(FAL_ACTION_FLG_TST(rule->action_flg, FAL_ACL_ACTION_ENQUEUE_PRI)) - { - hw_act->bf.enqueue_pri_change_en = 1; - hw_act->bf.enqueue_pri = rule->enqueue_pri; - } - if(FAL_ACTION_FLG_TST(rule->action_flg, FAL_ACL_ACTION_SERVICE_CODE)) - { - hw_act->bf.service_code_en = 1; - hw_act->bf.service_code_0 = rule->service_code&0x1; - hw_act->bf.service_code_1 = (rule->service_code>>1)&0x7f; - } - if(FAL_ACTION_FLG_TST(rule->action_flg, FAL_ACL_ACTION_SYN_TOGGLE)) - { - hw_act->bf.syn_toggle = 1; - } - if(FAL_ACTION_FLG_TST(rule->action_flg, FAL_ACL_ACTION_CPU_CODE)) - { - hw_act->bf.cpu_code_en = 1; - hw_act->bf.cpu_code = rule->cpu_code; - } - if(FAL_ACTION_FLG_TST(rule->action_flg, FAL_ACL_ACTION_METADATA_EN)) - { - hw_act->bf.metadata_en = 1; - } -#if defined(CPPE) - if(adpt_hppe_chip_revision_get(dev_id) == CPPE_REVISION) - { - hw_act->bf.qos_res_prec = rule->qos_res_prec; - } -#endif - return SW_OK; -} - -sw_error_t -_adpt_hppe_acl_rule_hw_add(a_uint32_t dev_id, ADPT_HPPE_ACL_SW_LIST *list_entry, - a_uint32_t hw_list_id, a_uint32_t rule_id, a_uint32_t rule_nr, - fal_acl_rule_t * rule, a_uint32_t rule_type_map, a_uint32_t allocated_entries) -{ - union ipo_rule_reg_u hw_reg = {0}; - union ipo_mask_reg_u hw_mask = {0}; - union ipo_action_u hw_act = {0}; - sw_error_t rv = 0; - a_uint32_t hw_entry = 0; - a_uint32_t i = 0; - - hw_reg.bf.post_routing_en = rule->post_routing; - hw_reg.bf.res_chain = rule->acl_pool; - hw_reg.bf.pri = ((list_entry->list_pri)<<3)|rule->pri; - - for( i = 0; i < ADPT_ACL_HPPE_RULE_TYPE_NUM; i++) - { - if(!((1<field_flg, FAL_ACL_FIELD_INVERSE_ALL)) - { - hw_reg.bf.inverse_en = 1; - } - - SSDK_DEBUG("rule and mask set hw_entry = %d\n", - hw_list_id*ADPT_ACL_ENTRY_NUM_PER_LIST+hw_entry); - SSDK_DEBUG("post_route %d, chain %d, pri %d, src_1 %d, src_0 %d, src_type %d " - "rule_type %d, inverse %d, range %d\n", hw_reg.bf.post_routing_en, - hw_reg.bf.res_chain, hw_reg.bf.pri, hw_reg.bf.src_1, hw_reg.bf.src_0, - hw_reg.bf.src_type, hw_reg.bf.rule_type, hw_reg.bf.inverse_en, - hw_reg.bf.range_en); - /*_adpt_acl_reg_dump((a_uint8_t *)&hw_reg, sizeof(hw_reg));*/ - rv |= hppe_ipo_rule_reg_set(dev_id, hw_list_id*ADPT_ACL_ENTRY_NUM_PER_LIST+hw_entry, - &hw_reg); - /*_adpt_acl_reg_dump((a_uint8_t *)&hw_mask, sizeof(hw_mask));*/ - rv |= hppe_ipo_mask_reg_set(dev_id, hw_list_id*ADPT_ACL_ENTRY_NUM_PER_LIST+hw_entry, - &hw_mask); - _adpt_hppe_acl_action_sw_2_hw(dev_id,rule, &hw_act); - /*_adpt_acl_reg_dump((a_uint8_t *)&hw_act, sizeof(hw_act));*/ - rv |= hppe_ipo_action_set(dev_id, hw_list_id*ADPT_ACL_ENTRY_NUM_PER_LIST+hw_entry, - &hw_act); - - if(rv != SW_OK) - { - return rv; - } - } - - return SW_OK; -} - -static sw_error_t -_adpt_hppe_acl_hw_list_resort(a_uint32_t dev_id, a_uint32_t hw_list_index, a_bool_t move_up) -{ - a_uint32_t i = 0; - ADPT_HPPE_ACL_HW_LIST temp = {0}; - - if(hw_list_index >= ADPT_ACL_HW_LIST_NUM) - { - return SW_OUT_OF_RANGE; - } - - if(move_up) - { - temp.hw_list_id = g_acl_hw_list[dev_id][hw_list_index].hw_list_id; - temp.free_hw_entry_bitmap = - g_acl_hw_list[dev_id][hw_list_index].free_hw_entry_bitmap; - temp.free_hw_entry_count = - g_acl_hw_list[dev_id][hw_list_index].free_hw_entry_count; - for(i = hw_list_index; i > 0; i--) - { - if(temp.free_hw_entry_count < - g_acl_hw_list[dev_id][i-1].free_hw_entry_count) - { - g_acl_hw_list[dev_id][i].hw_list_id = - g_acl_hw_list[dev_id][i-1].hw_list_id; - g_acl_hw_list[dev_id][i].free_hw_entry_bitmap = - g_acl_hw_list[dev_id][i-1].free_hw_entry_bitmap; - g_acl_hw_list[dev_id][i].free_hw_entry_count = - g_acl_hw_list[dev_id][i-1].free_hw_entry_count; - } - else - { - break; - } - } - g_acl_hw_list[dev_id][i].hw_list_id = temp.hw_list_id; - g_acl_hw_list[dev_id][i].free_hw_entry_bitmap = temp.free_hw_entry_bitmap; - g_acl_hw_list[dev_id][i].free_hw_entry_count = temp.free_hw_entry_count; - } - else - { - temp.hw_list_id = g_acl_hw_list[dev_id][hw_list_index].hw_list_id; - temp.free_hw_entry_bitmap = - g_acl_hw_list[dev_id][hw_list_index].free_hw_entry_bitmap; - temp.free_hw_entry_count = - g_acl_hw_list[dev_id][hw_list_index].free_hw_entry_count; - for(i = hw_list_index; i < ADPT_ACL_HW_LIST_NUM-1; i++) - { - if(temp.free_hw_entry_count > - g_acl_hw_list[dev_id][i+1].free_hw_entry_count) - { - g_acl_hw_list[dev_id][i].hw_list_id = - g_acl_hw_list[dev_id][i+1].hw_list_id; - g_acl_hw_list[dev_id][i].free_hw_entry_bitmap = - g_acl_hw_list[dev_id][i+1].free_hw_entry_bitmap; - g_acl_hw_list[dev_id][i].free_hw_entry_count = - g_acl_hw_list[dev_id][i+1].free_hw_entry_count; - } - else - { - break; - } - } - g_acl_hw_list[dev_id][i].hw_list_id = temp.hw_list_id; - g_acl_hw_list[dev_id][i].free_hw_entry_bitmap = temp.free_hw_entry_bitmap; - g_acl_hw_list[dev_id][i].free_hw_entry_count = temp.free_hw_entry_count; - } - return SW_OK; -} - -sw_error_t -adpt_hppe_acl_rule_add(a_uint32_t dev_id, a_uint32_t list_id, - a_uint32_t rule_id, a_uint32_t rule_nr, fal_acl_rule_t * rule) -{ - a_uint32_t rule_type_map = 0; - a_uint32_t rule_type_count = 0; - a_uint32_t index = 0, hw_list_index = 0, hw_list_id = 0; - sw_error_t rv = 0; - union rule_ext_1_reg_u ext_1 = {0}; - union rule_ext_2_reg_u ext_2 = {0}; - union rule_ext_4_reg_u ext_4 = {0}; - struct list_head *rule_pos = NULL; - ADPT_HPPE_ACL_SW_RULE *rule_exist_entry = NULL, *rule_add_entry = NULL; - ADPT_HPPE_ACL_SW_LIST *list_find_entry = NULL; - - ADPT_DEV_ID_CHECK(dev_id); - ADPT_NULL_POINT_CHECK(rule); - - if(list_id >= ADPT_ACL_SW_LIST_NUM) - { - return SW_OUT_OF_RANGE; - } - - if(rule_id >= ADPT_ACL_RULE_NUM_PER_LIST) - { - return SW_OUT_OF_RANGE; - } - - aos_lock_bh(&hppe_acl_lock[dev_id]); - list_find_entry = _adpt_hppe_acl_list_entry_get(dev_id, list_id); - if(list_find_entry == NULL) - { - SSDK_ERROR("List %d not create, no resource to insert rules into it\n", list_id); - aos_unlock_bh(&hppe_acl_lock[dev_id]); - return SW_NO_RESOURCE; - } - - list_for_each(rule_pos, &list_find_entry->list_sw_rule) - { - rule_exist_entry = list_entry(rule_pos, ADPT_HPPE_ACL_SW_RULE, list); - if((rule_exist_entry->rule_id == rule_id) && (rule_exist_entry->rule_hw_entry != 0)) - { - aos_unlock_bh(&hppe_acl_lock[dev_id]); - return SW_ALREADY_EXIST; - } - } - - SSDK_DEBUG("fields[0] = 0x%x, fields[1] = 0x%x\n", - rule->field_flg[0], rule->field_flg[1]); - if(rule->rule_type == FAL_ACL_RULE_IP4)/*input ipv4 type*/ - { - _adpt_hppe_acl_ipv4_fields_check(dev_id, list_id, rule_id, rule_nr, rule, - &rule_type_map); - } - else if(rule->rule_type == FAL_ACL_RULE_IP6)/*input ipv6 type*/ - { - _adpt_hppe_acl_ipv6_fields_check(dev_id, list_id, rule_id, rule_nr, rule, - &rule_type_map); - } - _adpt_hppe_acl_udf_fields_check(dev_id, list_id, rule_id, rule_nr, rule, &rule_type_map); - _adpt_hppe_acl_l2_fields_check(dev_id, list_id, rule_id, rule_nr, rule, &rule_type_map); - - if(rule_type_map == 0) - { - rule_type_map |= (1< ADPT_ACL_ENTRY_NUM_PER_LIST) - { - SSDK_ERROR("rule_type_count = %d\n", rule_type_count); - aos_unlock_bh(&hppe_acl_lock[dev_id]); - return SW_NOT_SUPPORTED; - } - - rv = _adpt_hppe_acl_alloc_entries(dev_id, &hw_list_index, rule_id, rule_nr, rule, - rule_type_map, rule_type_count, &index); - if(rv != SW_OK) - { - SSDK_ERROR("Alloc hw entries fail for rule %d\n", rule_id); - aos_unlock_bh(&hppe_acl_lock[dev_id]); - return rv; - } - /* msg for debug */ - SSDK_DEBUG("ACL rule add before:list_id=%d, hw_list_index=%d, hw_list_id=%d, " - "free_hw_entry_bitmap=0x%x, free_hw_entry_count=%d\n", list_id, hw_list_index, - g_acl_hw_list[dev_id][hw_list_index].hw_list_id, - g_acl_hw_list[dev_id][hw_list_index].free_hw_entry_bitmap, - g_acl_hw_list[dev_id][hw_list_index].free_hw_entry_count); - - hw_list_id = g_acl_hw_list[dev_id][hw_list_index].hw_list_id; - rv = _adpt_hppe_acl_rule_hw_add(dev_id, list_find_entry, hw_list_id, rule_id, rule_nr, rule, - rule_type_map, s_acl_entries[index].entries); - if(rv != SW_OK) - { - aos_unlock_bh(&hppe_acl_lock[dev_id]); - return rv; - } - - if(s_acl_entries[index].ext_1 != 0) - { - rv |= hppe_rule_ext_1_reg_get(dev_id, hw_list_id, &ext_1); - ext_1.val |= s_acl_entries[index].ext_1; - SSDK_DEBUG("ext_1.val = 0x%x\n", ext_1.val); - rv |= hppe_rule_ext_1_reg_set(dev_id, hw_list_id, &ext_1); - } - if(s_acl_entries[index].ext_2 != 0) - { - rv |= hppe_rule_ext_2_reg_get(dev_id, hw_list_id, &ext_2); - ext_2.val |= s_acl_entries[index].ext_2; - SSDK_DEBUG("ext_2.val = 0x%x\n", ext_2.val); - rv |= hppe_rule_ext_2_reg_set(dev_id, hw_list_id, &ext_2); - } - if(s_acl_entries[index].ext_4 != 0) - { - rv |= hppe_rule_ext_4_reg_get(dev_id, hw_list_id, &ext_4); - ext_4.val |= s_acl_entries[index].ext_4; - SSDK_DEBUG("ext_4.val = 0x%x\n", ext_4.val); - rv |= hppe_rule_ext_4_reg_set(dev_id, hw_list_id, &ext_4); - } - - /*record sw info and insert the sw rule entry to the sw list entry*/ - rule_add_entry = (ADPT_HPPE_ACL_SW_RULE*)aos_mem_alloc(sizeof(ADPT_HPPE_ACL_SW_RULE)); - if(rule_add_entry == NULL) - { - SSDK_ERROR("%s, %d:malloc fail for rule add entry\n", __FUNCTION__, __LINE__); - aos_unlock_bh(&hppe_acl_lock[dev_id]); - return SW_FAIL; - } - rule_add_entry->rule_id = rule_id; - rule_add_entry->rule_type = rule->rule_type; - rule_add_entry->rule_hw_entry = s_acl_entries[index].entries; - rule_add_entry->rule_hw_list_id = hw_list_id; - rule_add_entry->ext1_val = s_acl_entries[index].ext_1; - rule_add_entry->ext2_val = s_acl_entries[index].ext_2; - rule_add_entry->ext4_val = s_acl_entries[index].ext_4; - list_add(&rule_add_entry->list, &list_find_entry->list_sw_rule); - - /*update hw list info */ - g_acl_hw_list[dev_id][hw_list_index].free_hw_entry_bitmap &= - (~(s_acl_entries[index].entries)); - g_acl_hw_list[dev_id][hw_list_index].free_hw_entry_count -= s_acl_entries[index].num; - - /* msg for debug */ - SSDK_DEBUG("ACL rule add after:list_id=%d, hw_list_index=%d, hw_list_id=%d, " - "free_hw_entry_bitmap=0x%x, free_hw_entry_count=%d\n", list_id, hw_list_index, - hw_list_id, g_acl_hw_list[dev_id][hw_list_index].free_hw_entry_bitmap, - g_acl_hw_list[dev_id][hw_list_index].free_hw_entry_count); - /*resort hw list */ - _adpt_hppe_acl_hw_list_resort(dev_id, hw_list_index, A_TRUE); - - aos_unlock_bh(&hppe_acl_lock[dev_id]); - return SW_OK; -} - -static sw_error_t -_adpt_hppe_acl_rule_delete(a_uint32_t dev_id, a_uint32_t list_id, - ADPT_HPPE_ACL_SW_RULE *rule_entry, a_uint32_t rule_nr) -{ - sw_error_t rv = 0; - a_uint32_t hw_index = 0, hw_entries = 0, hw_list_id = 0, hw_list_index = 0, i = 0; - union ipo_rule_reg_u hw_reg = {0}; - union ipo_mask_reg_u hw_mask = {0}; - union ipo_action_u hw_act = {0}; - union rule_ext_1_reg_u ext_1 = {0}; - union rule_ext_2_reg_u ext_2 = {0}; - union rule_ext_4_reg_u ext_4 = {0}; - - hw_entries = rule_entry->rule_hw_entry; - hw_list_id = rule_entry->rule_hw_list_id; - /* msg for debug */ - SSDK_DEBUG("ACL delete rule entry before:list_id=%d, rule_id=%d, " - "hw_entries=0x%x, hw_list_id=%d\n", list_id, - rule_entry->rule_id, rule_entry->rule_hw_entry, - rule_entry->rule_hw_list_id); - while(hw_entries != 0) - { - union ipo_cnt_tbl_u counters = {0}; - hw_index = _acl_bit_index(hw_entries, ADPT_ACL_ENTRY_NUM_PER_LIST, 0); - if(hw_index >= ADPT_ACL_ENTRY_NUM_PER_LIST) - { - break; - } - - rv |= hppe_ipo_rule_reg_set(dev_id, - hw_list_id*ADPT_ACL_ENTRY_NUM_PER_LIST+hw_index, &hw_reg); - rv |= hppe_ipo_mask_reg_set(dev_id, - hw_list_id*ADPT_ACL_ENTRY_NUM_PER_LIST+hw_index, &hw_mask); - rv |= hppe_ipo_action_set(dev_id, - hw_list_id*ADPT_ACL_ENTRY_NUM_PER_LIST+hw_index, &hw_act); - SSDK_DEBUG("ACL destroy entry %d\n", - hw_list_id*ADPT_ACL_ENTRY_NUM_PER_LIST+hw_index); - hw_entries &= (~(1<ext1_val) - { - rv |= hppe_rule_ext_1_reg_get(dev_id, hw_list_id, &ext_1); - ext_1.val &= (~rule_entry->ext1_val); - SSDK_DEBUG("ext_1.val = 0x%x\n", ext_1.val); - rv |= hppe_rule_ext_1_reg_set(dev_id, hw_list_id, &ext_1); - } - if(rule_entry->ext2_val) - { - rv |= hppe_rule_ext_2_reg_get(dev_id, hw_list_id, &ext_2); - ext_2.val &= (~rule_entry->ext2_val); - SSDK_DEBUG("ext_2.val = 0x%x\n", ext_2.val); - rv |= hppe_rule_ext_2_reg_set(dev_id, hw_list_id, &ext_2); - } - if(rule_entry->ext4_val) - { - rv |= hppe_rule_ext_4_reg_get(dev_id, hw_list_id, &ext_4); - ext_4.val &= (~rule_entry->ext4_val); - SSDK_DEBUG("ext_4.val = 0x%x\n", ext_4.val); - rv |= hppe_rule_ext_4_reg_set(dev_id, hw_list_id, &ext_4); - } - - /*find hw_list_index*/ - for(i = 0; i < ADPT_ACL_HW_LIST_NUM; i++) - { - if(g_acl_hw_list[dev_id][i].hw_list_id == hw_list_id) - { - hw_list_index = i; - break; - } - } - - /*update hw list info and resort hw list*/ - g_acl_hw_list[dev_id][hw_list_index].free_hw_entry_bitmap |= rule_entry->rule_hw_entry; - g_acl_hw_list[dev_id][hw_list_index].free_hw_entry_count += - _acl_bits_count(rule_entry->rule_hw_entry, ADPT_ACL_ENTRY_NUM_PER_LIST, 0); - /* msg for debug */ - SSDK_DEBUG("ACL delete rule entry after:hw_list_index=%d, list_id=%d, " - "rule_id=%d, hw_entries=0x%x, hw_list_id=%d\n", hw_list_index, - list_id, rule_entry->rule_id, rule_entry->rule_hw_entry, - rule_entry->rule_hw_list_id); - _adpt_hppe_acl_hw_list_resort(dev_id, hw_list_index, A_FALSE); - - /*delete rule entry from the sw list*/ - list_del(&rule_entry->list); - aos_mem_free(rule_entry); - rule_entry = NULL; - - return rv; -} - -sw_error_t -adpt_hppe_acl_rule_delete(a_uint32_t dev_id, a_uint32_t list_id, - a_uint32_t rule_id, a_uint32_t rule_nr) -{ - struct list_head *rule_pos = NULL; - ADPT_HPPE_ACL_SW_RULE *rule_delete_entry = NULL; - ADPT_HPPE_ACL_SW_LIST *list_find_entry = NULL; - - ADPT_DEV_ID_CHECK(dev_id); - - if(list_id >= ADPT_ACL_SW_LIST_NUM) - { - return SW_OUT_OF_RANGE; - } - - if(rule_id >= ADPT_ACL_RULE_NUM_PER_LIST) - { - return SW_OUT_OF_RANGE; - } - - aos_lock_bh(&hppe_acl_lock[dev_id]); - list_find_entry = _adpt_hppe_acl_list_entry_get(dev_id, list_id); - if(list_find_entry != NULL) - { - list_for_each(rule_pos, &list_find_entry->list_sw_rule) - { - rule_delete_entry = list_entry(rule_pos, ADPT_HPPE_ACL_SW_RULE, list); - if(rule_delete_entry->rule_id == rule_id) - { - _adpt_hppe_acl_rule_delete(dev_id, list_id, - rule_delete_entry, rule_nr); - break; - } - } - } - aos_unlock_bh(&hppe_acl_lock[dev_id]); - return SW_OK; -} - -static sw_error_t -_adpt_hppe_acl_rule_dump(a_uint32_t dev_id, a_uint32_t list_id, ADPT_HPPE_ACL_SW_RULE *rule_entry) -{ - a_uint8_t i = 0; - a_uint8_t hw_entries = rule_entry->rule_hw_entry; - a_uint32_t hw_list_id = rule_entry->rule_hw_list_id; - union ipo_rule_reg_u hw_reg = {0}; - union ipo_mask_reg_u hw_mask = {0}; - union ipo_action_u hw_act = {0}; - - if(hw_entries != 0) - { - printk("######list_id %d, rule_id %d, hw_list_id %d\n", list_id, - rule_entry->rule_id, hw_list_id); - for(i = 0; i < ADPT_ACL_ENTRY_NUM_PER_LIST; i++) - { - if((1<list_sw_rule) - { - rule_dump_entry = list_entry(rule_pos, ADPT_HPPE_ACL_SW_RULE, list); - _adpt_hppe_acl_rule_dump(dev_id, list_dump_entry->list_id, rule_dump_entry); - } - } - aos_unlock_bh(&hppe_acl_lock[dev_id]); - return SW_OK; -} - -sw_error_t -adpt_hppe_acl_list_dump(a_uint32_t dev_id) -{ - adpt_hppe_acl_rule_dump(dev_id); - - return SW_OK; -} - - -sw_error_t -adpt_hppe_acl_list_creat(a_uint32_t dev_id, a_uint32_t list_id, a_uint32_t list_pri) -{ - ADPT_HPPE_ACL_SW_LIST *list_create_entry = NULL; - - ADPT_DEV_ID_CHECK(dev_id); - - if(list_id >= ADPT_ACL_SW_LIST_NUM) - { - return SW_OUT_OF_RANGE; - } - - aos_lock_bh(&hppe_acl_lock[dev_id]); - list_create_entry = _adpt_hppe_acl_list_entry_get(dev_id, list_id); - if(list_create_entry != NULL) - { - aos_unlock_bh(&hppe_acl_lock[dev_id]); - return SW_ALREADY_EXIST; - } - - list_create_entry = (ADPT_HPPE_ACL_SW_LIST*)aos_mem_alloc(sizeof(ADPT_HPPE_ACL_SW_LIST)); - if(list_create_entry == NULL) - { - SSDK_ERROR("%s, %d:malloc fail for list create entry\n", __FUNCTION__, __LINE__); - aos_unlock_bh(&hppe_acl_lock[dev_id]); - return SW_FAIL; - } - INIT_LIST_HEAD(&list_create_entry->list_sw_rule); - list_create_entry->list_id = list_id; - list_create_entry->list_pri = list_pri; - list_add(&list_create_entry->list, &g_acl_sw_list[dev_id].list_sw_list); - aos_unlock_bh(&hppe_acl_lock[dev_id]); - return SW_OK; -} - -sw_error_t -adpt_hppe_acl_list_destroy(a_uint32_t dev_id, a_uint32_t list_id) -{ - struct list_head *rule_pos=NULL, *rule_pos_temp = NULL; - ADPT_HPPE_ACL_SW_RULE *rule_delete_entry = NULL; - ADPT_HPPE_ACL_SW_LIST *list_destroy_entry = NULL; - - ADPT_DEV_ID_CHECK(dev_id); - - if(list_id >= ADPT_ACL_SW_LIST_NUM) - { - return SW_OUT_OF_RANGE; - } - - aos_lock_bh(&hppe_acl_lock[dev_id]); - list_destroy_entry = _adpt_hppe_acl_list_entry_get(dev_id, list_id); - if(list_destroy_entry != NULL) - { - list_for_each_safe(rule_pos, rule_pos_temp, &list_destroy_entry->list_sw_rule) - { - rule_delete_entry = list_entry(rule_pos, ADPT_HPPE_ACL_SW_RULE, list); - _adpt_hppe_acl_rule_delete(dev_id, list_id, rule_delete_entry, 1); - } - list_del(&list_destroy_entry->list); - aos_mem_free(list_destroy_entry); - list_destroy_entry = NULL; - } - aos_unlock_bh(&hppe_acl_lock[dev_id]); - return SW_OK; -} - -typedef sw_error_t (*hppe_acl_udp_set_func)(a_uint32_t dev_id, union udf_ctrl_reg_u *udf_ctrl); -typedef sw_error_t (*hppe_acl_udp_get_func)(a_uint32_t dev_id, union udf_ctrl_reg_u *udf_ctrl); - -hppe_acl_udp_set_func g_udf_set_func[FAL_ACL_UDF_BUTT][4] = { - {hppe_non_ip_udf0_ctrl_reg_set, hppe_non_ip_udf1_ctrl_reg_set, - hppe_non_ip_udf2_ctrl_reg_set, hppe_non_ip_udf3_ctrl_reg_set}, - {hppe_ipv4_udf0_ctrl_reg_set, hppe_ipv4_udf1_ctrl_reg_set, hppe_ipv4_udf2_ctrl_reg_set, - hppe_ipv4_udf3_ctrl_reg_set}, - {hppe_ipv6_udf0_ctrl_reg_set, hppe_ipv6_udf1_ctrl_reg_set, hppe_ipv6_udf2_ctrl_reg_set, - hppe_ipv6_udf3_ctrl_reg_set}, -}; - -hppe_acl_udp_get_func g_udf_get_func[FAL_ACL_UDF_BUTT][4] = { - {hppe_non_ip_udf0_ctrl_reg_get, hppe_non_ip_udf1_ctrl_reg_get, - hppe_non_ip_udf2_ctrl_reg_get, hppe_non_ip_udf3_ctrl_reg_get}, - {hppe_ipv4_udf0_ctrl_reg_get, hppe_ipv4_udf1_ctrl_reg_get, hppe_ipv4_udf2_ctrl_reg_get, - hppe_ipv4_udf3_ctrl_reg_get}, - {hppe_ipv6_udf0_ctrl_reg_get, hppe_ipv6_udf1_ctrl_reg_get, hppe_ipv6_udf2_ctrl_reg_get, - hppe_ipv6_udf3_ctrl_reg_get}, -}; - -sw_error_t -adpt_hppe_acl_udf_profile_get(a_uint32_t dev_id, fal_acl_udf_pkt_type_t pkt_type,a_uint32_t udf_idx, - fal_acl_udf_type_t *udf_type, a_uint32_t *offset) -{ - union udf_ctrl_reg_u udf_ctrl = {0}; - sw_error_t rv = SW_OK; - - ADPT_DEV_ID_CHECK(dev_id); - ADPT_NULL_POINT_CHECK(udf_type); - ADPT_NULL_POINT_CHECK(offset); - - rv = g_udf_get_func[pkt_type][udf_idx](dev_id, &udf_ctrl); - - if(rv != SW_OK) - return rv; - - if(udf_ctrl.bf.udf_base == 0) - { - *udf_type = FAL_ACL_UDF_TYPE_L2; - } - else if(udf_ctrl.bf.udf_base == 1) - { - *udf_type = FAL_ACL_UDF_TYPE_L3; - } - else if(udf_ctrl.bf.udf_base == 2) - { - *udf_type = FAL_ACL_UDF_TYPE_L4; - } - - *offset = udf_ctrl.bf.udf_offset*2; - - return SW_OK; -} - - -sw_error_t -adpt_hppe_acl_udf_profile_set(a_uint32_t dev_id, fal_acl_udf_pkt_type_t pkt_type,a_uint32_t udf_idx, - fal_acl_udf_type_t udf_type, a_uint32_t offset) -{ - union udf_ctrl_reg_u udf_ctrl = {0}; - ADPT_DEV_ID_CHECK(dev_id); - - if(udf_type == FAL_ACL_UDF_TYPE_L2) - { - udf_ctrl.bf.udf_base = 0; - } - else if(udf_type == FAL_ACL_UDF_TYPE_L3) - { - udf_ctrl.bf.udf_base = 1; - } - else if(udf_type == FAL_ACL_UDF_TYPE_L4) - { - udf_ctrl.bf.udf_base = 2; - } - else - return SW_NOT_SUPPORTED; - - if(offset % 2)/*only support even data*/ - return SW_BAD_VALUE; - udf_ctrl.bf.udf_offset = offset/2; - - return g_udf_set_func[pkt_type][udf_idx](dev_id, &udf_ctrl); -} - -void adpt_hppe_acl_func_bitmap_init(a_uint32_t dev_id) -{ - adpt_api_t *p_adpt_api = NULL; - - p_adpt_api = adpt_api_ptr_get(dev_id); - - if(p_adpt_api == NULL) - return; - - p_adpt_api->adpt_acl_func_bitmap = ((1<adpt_acl_list_creat = NULL; - p_adpt_api->adpt_acl_list_destroy = NULL; - p_adpt_api->adpt_acl_rule_add = NULL; - p_adpt_api->adpt_acl_rule_delete = NULL; - p_adpt_api->adpt_acl_rule_query = NULL; - p_adpt_api->adpt_acl_rule_dump = NULL; - p_adpt_api->adpt_acl_list_dump = NULL; - p_adpt_api->adpt_acl_list_bind = NULL; - p_adpt_api->adpt_acl_list_unbind = NULL; - p_adpt_api->adpt_acl_udf_profile_set = NULL; - p_adpt_api->adpt_acl_udf_profile_get = NULL; - - return; -} - -sw_error_t adpt_hppe_acl_init(a_uint32_t dev_id) -{ - adpt_api_t *p_adpt_api = NULL; - a_uint8_t hw_list_index = 0; - p_adpt_api = adpt_api_ptr_get(dev_id); - - if(p_adpt_api == NULL) - { - return SW_FAIL; - } - - for(hw_list_index = 0; hw_list_index < ADPT_ACL_HW_LIST_NUM; hw_list_index++) - { - if(g_acl_hw_list[dev_id][hw_list_index].hw_list_valid == A_FALSE) - { - g_acl_hw_list[dev_id][hw_list_index].free_hw_entry_bitmap = 0xff; - g_acl_hw_list[dev_id][hw_list_index].free_hw_entry_count = - ADPT_ACL_ENTRY_NUM_PER_LIST; - g_acl_hw_list[dev_id][hw_list_index].hw_list_id = - ADPT_ACL_HW_LIST_NUM - 1 - hw_list_index; - g_acl_hw_list [dev_id][hw_list_index].hw_list_valid = A_TRUE; - INIT_LIST_HEAD(&g_acl_sw_list[dev_id].list_sw_list); - } - } - - adpt_hppe_acl_func_unregister(dev_id, p_adpt_api); - - if(p_adpt_api->adpt_acl_func_bitmap & (1<adpt_acl_list_bind = adpt_hppe_acl_list_bind; - } - if(p_adpt_api->adpt_acl_func_bitmap & (1<adpt_acl_list_dump = adpt_hppe_acl_list_dump; - } - if(p_adpt_api->adpt_acl_func_bitmap & (1<adpt_acl_rule_query = adpt_hppe_acl_rule_query; - } - if(p_adpt_api->adpt_acl_func_bitmap & (1<adpt_acl_list_unbind = adpt_hppe_acl_list_unbind; - } - if(p_adpt_api->adpt_acl_func_bitmap & (1<adpt_acl_rule_add = adpt_hppe_acl_rule_add; - } - if(p_adpt_api->adpt_acl_func_bitmap & (1<adpt_acl_rule_delete = adpt_hppe_acl_rule_delete; - } - if(p_adpt_api->adpt_acl_func_bitmap & (1<adpt_acl_rule_dump = adpt_hppe_acl_rule_dump; - } - if(p_adpt_api->adpt_acl_func_bitmap & (1<adpt_acl_list_creat = adpt_hppe_acl_list_creat; - } - if(p_adpt_api->adpt_acl_func_bitmap & (1<adpt_acl_list_destroy = adpt_hppe_acl_list_destroy; - } - if(p_adpt_api->adpt_acl_func_bitmap & (1<adpt_acl_udf_profile_set = adpt_hppe_acl_udf_profile_set; - } - if(p_adpt_api->adpt_acl_func_bitmap & (1<adpt_acl_udf_profile_get = adpt_hppe_acl_udf_profile_get; - } - - aos_lock_init(&hppe_acl_lock[dev_id]); - - return SW_OK; -} - -/** - * @} - */ diff --git a/feeds/ipq807x/qca-ssdk/src/src/adpt/hppe/adpt_hppe_bm.c b/feeds/ipq807x/qca-ssdk/src/src/adpt/hppe/adpt_hppe_bm.c deleted file mode 100755 index 1c6f08782..000000000 --- a/feeds/ipq807x/qca-ssdk/src/src/adpt/hppe/adpt_hppe_bm.c +++ /dev/null @@ -1,452 +0,0 @@ -/* - * Copyright (c) 2016-2017, The Linux Foundation. All rights reserved. - * Permission to use, copy, modify, and/or distribute this software for - * any purpose with or without fee is hereby granted, provided that the - * above copyright notice and this permission notice appear in all copies. - * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES - * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR - * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES - * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN - * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT - * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. - */ - - -/** - * @defgroup - * @{ - */ -#include "sw.h" -#include "fal_bm.h" -#include "hppe_bm_reg.h" -#include "hppe_bm.h" -#include "hppe_portctrl_reg.h" -#include "hppe_portctrl.h" -#include "adpt.h" - -#ifndef IN_BM_MINI -sw_error_t -adpt_hppe_port_bufgroup_map_get(a_uint32_t dev_id, fal_port_t port, - a_uint8_t *group) -{ - sw_error_t rv = SW_OK; - union port_group_id_u port_group_id; - - ADPT_DEV_ID_CHECK(dev_id); - ADPT_NULL_POINT_CHECK(group); - memset(&port_group_id, 0, sizeof(port_group_id)); - - rv = hppe_port_group_id_get(dev_id, port, &port_group_id); - if( rv != SW_OK ) - return rv; - - *group = port_group_id.bf.port_shared_group_id; - - return SW_OK; -} - -sw_error_t -adpt_hppe_bm_port_reserved_buffer_get(a_uint32_t dev_id, fal_port_t port, - a_uint16_t *prealloc_buff, a_uint16_t *react_buff) -{ - sw_error_t rv = SW_OK; - union port_fc_cfg_u port_fc_cfg; - - ADPT_DEV_ID_CHECK(dev_id); - ADPT_NULL_POINT_CHECK(prealloc_buff); - ADPT_NULL_POINT_CHECK(react_buff); - memset(&port_fc_cfg, 0, sizeof(port_fc_cfg)); - - rv = hppe_port_fc_cfg_get(dev_id, port, &port_fc_cfg); - if (rv) - return rv; - - *prealloc_buff = port_fc_cfg.bf.port_pre_alloc; - *react_buff = port_fc_cfg.bf.port_react_limit; - - return SW_OK; -} - -sw_error_t -adpt_hppe_bm_bufgroup_buffer_get(a_uint32_t dev_id, a_uint8_t group, - a_uint16_t *buff_num) -{ - sw_error_t rv = SW_OK; - union shared_group_cfg_u shared_group_cfg; - - ADPT_DEV_ID_CHECK(dev_id); - ADPT_NULL_POINT_CHECK(buff_num); - memset(&shared_group_cfg, 0, sizeof(shared_group_cfg)); - - rv = hppe_shared_group_cfg_get(dev_id, group, &shared_group_cfg); - if( rv != SW_OK ) - return rv; - - *buff_num = shared_group_cfg.bf.shared_group_limit; - - return SW_OK; -} - -sw_error_t -adpt_hppe_bm_port_dynamic_thresh_get(a_uint32_t dev_id, fal_port_t port, - fal_bm_dynamic_cfg_t *cfg) -{ - sw_error_t rv = SW_OK; - union port_fc_cfg_u port_fc_cfg; - - ADPT_DEV_ID_CHECK(dev_id); - ADPT_NULL_POINT_CHECK(cfg); - memset(&port_fc_cfg, 0, sizeof(port_fc_cfg)); - - rv = hppe_port_fc_cfg_get(dev_id, port, &port_fc_cfg); - if( rv != SW_OK ) - return rv; - - if (!port_fc_cfg.bf.port_shared_dynamic) - return SW_FAIL; - - cfg->weight = port_fc_cfg.bf.port_shared_weight; - cfg->shared_ceiling = port_fc_cfg.bf.port_shared_ceiling_0 | - port_fc_cfg.bf.port_shared_ceiling_1 << 3; - cfg->resume_off = port_fc_cfg.bf.port_resume_offset; - cfg->resume_min_thresh = port_fc_cfg.bf.port_resume_floor_th; - - return SW_OK; -} - -sw_error_t -adpt_hppe_port_bm_ctrl_get(a_uint32_t dev_id, fal_port_t port, a_bool_t *enable) -{ - sw_error_t rv = SW_OK; - union port_fc_mode_u port_fc_mode; - - ADPT_DEV_ID_CHECK(dev_id); - ADPT_NULL_POINT_CHECK(enable); - memset(&port_fc_mode, 0, sizeof(port_fc_mode)); - - rv = hppe_port_fc_mode_get(dev_id, port, &port_fc_mode); - if( rv != SW_OK ) - return rv; - - *enable = port_fc_mode.bf.fc_en; - - return SW_OK; -} -#endif - -sw_error_t -adpt_hppe_bm_bufgroup_buffer_set(a_uint32_t dev_id, a_uint8_t group, - a_uint16_t buff_num) -{ - sw_error_t rv = SW_OK; - union shared_group_cfg_u shared_group_cfg; - - ADPT_DEV_ID_CHECK(dev_id); - memset(&shared_group_cfg, 0, sizeof(shared_group_cfg)); - - shared_group_cfg.bf.shared_group_limit = buff_num; - rv = hppe_shared_group_cfg_set(dev_id, group, &shared_group_cfg); - if( rv != SW_OK ) - return rv; - - return SW_OK; -} - -sw_error_t -adpt_hppe_port_bufgroup_map_set(a_uint32_t dev_id, fal_port_t port, - a_uint8_t group) -{ - sw_error_t rv = SW_OK; - union port_group_id_u port_group_id; - - ADPT_DEV_ID_CHECK(dev_id); - memset(&port_group_id, 0, sizeof(port_group_id)); - - port_group_id.bf.port_shared_group_id = group; - rv = hppe_port_group_id_set(dev_id, port, &port_group_id); - if( rv != SW_OK ) - return rv; - - return SW_OK; -} - -#ifndef IN_BM_MINI -sw_error_t -adpt_hppe_bm_port_static_thresh_get(a_uint32_t dev_id, fal_port_t port, - fal_bm_static_cfg_t *cfg) -{ - sw_error_t rv = SW_OK; - union port_fc_cfg_u port_fc_cfg; - - ADPT_DEV_ID_CHECK(dev_id); - ADPT_NULL_POINT_CHECK(cfg); - memset(&port_fc_cfg, 0, sizeof(port_fc_cfg)); - - rv = hppe_port_fc_cfg_get(dev_id, port, &port_fc_cfg); - if( rv != SW_OK ) - return rv; - - if (port_fc_cfg.bf.port_shared_dynamic) - return SW_FAIL; - - cfg->resume_off = port_fc_cfg.bf.port_resume_offset; - cfg->max_thresh = port_fc_cfg.bf.port_shared_ceiling_0 | - port_fc_cfg.bf.port_shared_ceiling_1 << 3; - - return SW_OK; -} -#endif - -sw_error_t -adpt_hppe_bm_port_reserved_buffer_set(a_uint32_t dev_id, fal_port_t port, - a_uint16_t prealloc_buff, a_uint16_t react_buff) -{ - sw_error_t rv = SW_OK; - union port_fc_cfg_u port_fc_cfg; - - ADPT_DEV_ID_CHECK(dev_id); - memset(&port_fc_cfg, 0, sizeof(port_fc_cfg)); - - rv = hppe_port_fc_cfg_get(dev_id, port, &port_fc_cfg); - if (rv) - return rv; - - port_fc_cfg.bf.port_pre_alloc = prealloc_buff; - port_fc_cfg.bf.port_react_limit = react_buff; - - return hppe_port_fc_cfg_set(dev_id, port, &port_fc_cfg); -} - -sw_error_t -adpt_hppe_bm_port_static_thresh_set(a_uint32_t dev_id, fal_port_t port, - fal_bm_static_cfg_t *cfg) -{ - sw_error_t rv = SW_OK; - union port_fc_cfg_u port_fc_cfg; - - ADPT_DEV_ID_CHECK(dev_id); - ADPT_NULL_POINT_CHECK(cfg); - memset(&port_fc_cfg, 0, sizeof(port_fc_cfg)); - - rv = hppe_port_fc_cfg_get(dev_id, port, &port_fc_cfg); - if( rv != SW_OK ) - return rv; - - port_fc_cfg.bf.port_resume_offset = cfg->resume_off; - port_fc_cfg.bf.port_shared_ceiling_0 = cfg->max_thresh; - port_fc_cfg.bf.port_shared_ceiling_1 = cfg->max_thresh >> 3; - port_fc_cfg.bf.port_shared_dynamic = 0; - - return hppe_port_fc_cfg_set(dev_id, port, &port_fc_cfg);; -} - -sw_error_t -adpt_hppe_bm_port_dynamic_thresh_set(a_uint32_t dev_id, fal_port_t port, - fal_bm_dynamic_cfg_t *cfg) -{ - sw_error_t rv = SW_OK; - union port_fc_cfg_u port_fc_cfg; - - ADPT_DEV_ID_CHECK(dev_id); - ADPT_NULL_POINT_CHECK(cfg); - memset(&port_fc_cfg, 0, sizeof(port_fc_cfg)); - - rv = hppe_port_fc_cfg_get(dev_id, port, &port_fc_cfg); - if( rv != SW_OK ) - return rv; - - port_fc_cfg.bf.port_shared_weight = cfg->weight; - port_fc_cfg.bf.port_shared_ceiling_0 = cfg->shared_ceiling; - port_fc_cfg.bf.port_shared_ceiling_1 = cfg->shared_ceiling >> 3; - port_fc_cfg.bf.port_resume_offset = cfg->resume_off; - port_fc_cfg.bf.port_resume_floor_th = cfg->resume_min_thresh; - port_fc_cfg.bf.port_shared_dynamic = 1; - - return hppe_port_fc_cfg_set(dev_id, port, &port_fc_cfg);; -} - -sw_error_t -adpt_hppe_port_bm_ctrl_set(a_uint32_t dev_id, fal_port_t port, a_bool_t enable) -{ - union port_fc_mode_u port_fc_mode; - - ADPT_DEV_ID_CHECK(dev_id); - memset(&port_fc_mode, 0, sizeof(port_fc_mode)); - - port_fc_mode.bf.fc_en = enable; - return hppe_port_fc_mode_set(dev_id, port, &port_fc_mode); -} - -sw_error_t -adpt_hppe_port_tdm_ctrl_set(a_uint32_t dev_id, fal_port_tdm_ctrl_t *ctrl) -{ - union tdm_ctrl_u tdm_ctrl; - - ADPT_DEV_ID_CHECK(dev_id); - memset(&tdm_ctrl, 0, sizeof(tdm_ctrl)); - - tdm_ctrl.bf.tdm_en = ctrl->enable; - tdm_ctrl.bf.tdm_offset = ctrl->offset; - tdm_ctrl.bf.tdm_depth = ctrl->depth; - return hppe_tdm_ctrl_set(dev_id, &tdm_ctrl); -} - -sw_error_t -adpt_hppe_port_tdm_tick_cfg_set(a_uint32_t dev_id, a_uint32_t tick_index, - fal_port_tdm_tick_cfg_t *cfg) -{ - union tdm_cfg_u tdm_cfg; - - ADPT_DEV_ID_CHECK(dev_id); - memset(&tdm_cfg, 0, sizeof(tdm_cfg)); - - tdm_cfg.bf.valid = cfg->valid; - tdm_cfg.bf.dir = cfg->direction; - tdm_cfg.bf.port_num = cfg->port; - return hppe_tdm_cfg_set(dev_id, tick_index, &tdm_cfg); -} - -#ifndef IN_BM_MINI -sw_error_t -adpt_hppe_bm_port_counter_get(a_uint32_t dev_id, fal_port_t port, - fal_bm_port_counter_t *counter) -{ - sw_error_t rv = SW_OK; - union port_cnt_u port_cnt; - union port_reacted_cnt_u reacted_cnt; - union drop_stat_u drop_stat; - a_uint32_t index = FAL_PORT_ID_VALUE(port); - - ADPT_DEV_ID_CHECK(dev_id); - ADPT_NULL_POINT_CHECK(counter); - memset(&port_cnt, 0, sizeof(port_cnt)); - memset(&reacted_cnt, 0, sizeof(reacted_cnt)); - - rv = hppe_port_cnt_get(dev_id, index, &port_cnt); - if( rv != SW_OK ) - return rv; - counter->used_counter = port_cnt.bf.port_cnt; - - rv = hppe_port_reacted_cnt_get(dev_id, index, &reacted_cnt); - if( rv != SW_OK ) - return rv; - counter->react_counter = reacted_cnt.bf.port_reacted_cnt; - - rv = hppe_drop_stat_get(dev_id, index, &drop_stat); - if( rv != SW_OK ) - return rv; - counter->drop_byte_counter = drop_stat.bf.bytes_0 | ((a_uint64_t)drop_stat.bf.bytes_1 << 32); - counter->drop_packet_counter = drop_stat.bf.pkts; - rv = hppe_drop_stat_get(dev_id, index + 15, &drop_stat); - if( rv != SW_OK ) - return rv; - counter->fc_drop_byte_counter = drop_stat.bf.bytes_0 | ((a_uint64_t)drop_stat.bf.bytes_1 << 32); - counter->fc_drop_packet_counter = drop_stat.bf.pkts; - - return SW_OK; -} -#endif - -void adpt_hppe_bm_func_bitmap_init(a_uint32_t dev_id) -{ - adpt_api_t *p_adpt_api = NULL; - - p_adpt_api = adpt_api_ptr_get(dev_id); - - if(p_adpt_api == NULL) - return; - - p_adpt_api->adpt_bm_func_bitmap = ((1 << FUNC_PORT_BUFGROUP_MAP_GET) | - (1 << FUNC_BM_PORT_RESERVED_BUFFER_GET) | - (1 << FUNC_BM_BUFGROUP_BUFFER_GET) | - (1 << FUNC_BM_PORT_DYNAMIC_THRESH_GET) | - (1 << FUNC_PORT_BM_CTRL_GET) | - (1 << FUNC_BM_BUFGROUP_BUFFER_SET) | - (1 << FUNC_PORT_BUFGROUP_MAP_SET) | - (1 << FUNC_BM_PORT_STATIC_THRESH_GET) | - (1 << FUNC_BM_PORT_RESERVED_BUFFER_SET) | - (1 << FUNC_BM_PORT_STATIC_THRESH_SET) | - (1 << FUNC_BM_PORT_DYNAMIC_THRESH_SET) | - (1 << FUNC_PORT_BM_CTRL_SET) | - (1 << FUNC_PORT_TDM_CTRL_SET) | - (1 << FUNC_PORT_TDM_TICK_CFG_SET) | - (1 << FUNC_BM_PORT_COUNTER_GET)); - return; -} - -static void adpt_hppe_bm_func_unregister(a_uint32_t dev_id, adpt_api_t *p_adpt_api) -{ - if(p_adpt_api == NULL) - return; - - p_adpt_api->adpt_port_bufgroup_map_get = NULL; - p_adpt_api->adpt_bm_port_reserved_buffer_get = NULL; - p_adpt_api->adpt_bm_bufgroup_buffer_get = NULL; - p_adpt_api->adpt_bm_port_dynamic_thresh_get = NULL; - p_adpt_api->adpt_port_bm_ctrl_get = NULL; - p_adpt_api->adpt_bm_bufgroup_buffer_set = NULL; - p_adpt_api->adpt_port_bufgroup_map_set = NULL; - p_adpt_api->adpt_bm_port_static_thresh_get = NULL; - p_adpt_api->adpt_bm_port_reserved_buffer_set = NULL; - p_adpt_api->adpt_bm_port_static_thresh_set = NULL; - p_adpt_api->adpt_bm_port_dynamic_thresh_set = NULL; - p_adpt_api->adpt_port_bm_ctrl_set = NULL; - p_adpt_api->adpt_port_tdm_ctrl_set = NULL; - p_adpt_api->adpt_port_tdm_tick_cfg_set = NULL; - p_adpt_api->adpt_bm_port_counter_get = NULL; - - return; -} - - -sw_error_t adpt_hppe_bm_init(a_uint32_t dev_id) -{ - adpt_api_t *p_adpt_api = NULL; - - p_adpt_api = adpt_api_ptr_get(dev_id); - - if(p_adpt_api == NULL) - return SW_FAIL; - - adpt_hppe_bm_func_unregister(dev_id, p_adpt_api); - -#ifndef IN_BM_MINI - if (p_adpt_api->adpt_bm_func_bitmap & (1 << FUNC_PORT_BUFGROUP_MAP_GET)) - p_adpt_api->adpt_port_bufgroup_map_get = adpt_hppe_port_bufgroup_map_get; - if (p_adpt_api->adpt_bm_func_bitmap & (1 << FUNC_BM_PORT_RESERVED_BUFFER_GET)) - p_adpt_api->adpt_bm_port_reserved_buffer_get = adpt_hppe_bm_port_reserved_buffer_get; - if (p_adpt_api->adpt_bm_func_bitmap & (1 << FUNC_BM_BUFGROUP_BUFFER_GET)) - p_adpt_api->adpt_bm_bufgroup_buffer_get = adpt_hppe_bm_bufgroup_buffer_get; - if (p_adpt_api->adpt_bm_func_bitmap & (1 << FUNC_BM_PORT_DYNAMIC_THRESH_GET)) - p_adpt_api->adpt_bm_port_dynamic_thresh_get = adpt_hppe_bm_port_dynamic_thresh_get; - if (p_adpt_api->adpt_bm_func_bitmap & (1 << FUNC_PORT_BM_CTRL_GET)) - p_adpt_api->adpt_port_bm_ctrl_get = adpt_hppe_port_bm_ctrl_get; - if (p_adpt_api->adpt_bm_func_bitmap & (1 << FUNC_BM_PORT_STATIC_THRESH_GET)) - p_adpt_api->adpt_bm_port_static_thresh_get = adpt_hppe_bm_port_static_thresh_get; - if (p_adpt_api->adpt_bm_func_bitmap & (1 << FUNC_BM_PORT_COUNTER_GET)) - p_adpt_api->adpt_bm_port_counter_get = adpt_hppe_bm_port_counter_get; -#endif - if (p_adpt_api->adpt_bm_func_bitmap & (1 << FUNC_BM_BUFGROUP_BUFFER_SET)) - p_adpt_api->adpt_bm_bufgroup_buffer_set = adpt_hppe_bm_bufgroup_buffer_set; - if (p_adpt_api->adpt_bm_func_bitmap & (1 << FUNC_PORT_BUFGROUP_MAP_SET)) - p_adpt_api->adpt_port_bufgroup_map_set = adpt_hppe_port_bufgroup_map_set; - if (p_adpt_api->adpt_bm_func_bitmap & (1 << FUNC_BM_PORT_RESERVED_BUFFER_SET)) - p_adpt_api->adpt_bm_port_reserved_buffer_set = adpt_hppe_bm_port_reserved_buffer_set; - if (p_adpt_api->adpt_bm_func_bitmap & (1 << FUNC_BM_PORT_STATIC_THRESH_SET)) - p_adpt_api->adpt_bm_port_static_thresh_set = adpt_hppe_bm_port_static_thresh_set; - if (p_adpt_api->adpt_bm_func_bitmap & (1 << FUNC_BM_PORT_DYNAMIC_THRESH_SET)) - p_adpt_api->adpt_bm_port_dynamic_thresh_set = adpt_hppe_bm_port_dynamic_thresh_set; - if (p_adpt_api->adpt_bm_func_bitmap & (1 << FUNC_PORT_BM_CTRL_SET)) - p_adpt_api->adpt_port_bm_ctrl_set = adpt_hppe_port_bm_ctrl_set; - if (p_adpt_api->adpt_bm_func_bitmap & (1 << FUNC_PORT_TDM_CTRL_SET)) - p_adpt_api->adpt_port_tdm_ctrl_set = adpt_hppe_port_tdm_ctrl_set; - if (p_adpt_api->adpt_bm_func_bitmap & (1 << FUNC_PORT_TDM_TICK_CFG_SET)) - p_adpt_api->adpt_port_tdm_tick_cfg_set = adpt_hppe_port_tdm_tick_cfg_set; - - return SW_OK; -} - -/** - * @} - */ diff --git a/feeds/ipq807x/qca-ssdk/src/src/adpt/hppe/adpt_hppe_ctrlpkt.c b/feeds/ipq807x/qca-ssdk/src/src/adpt/hppe/adpt_hppe_ctrlpkt.c deleted file mode 100755 index d4659f15d..000000000 --- a/feeds/ipq807x/qca-ssdk/src/src/adpt/hppe/adpt_hppe_ctrlpkt.c +++ /dev/null @@ -1,385 +0,0 @@ -/* - * Copyright (c) 2016-2017, The Linux Foundation. All rights reserved. - * Permission to use, copy, modify, and/or distribute this software for - * any purpose with or without fee is hereby granted, provided that the - * above copyright notice and this permission notice appear in all copies. - * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES - * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR - * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES - * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN - * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT - * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. - */ - - -/** - * @defgroup - * @{ - */ -#include "sw.h" -#include "hppe_ctrlpkt_reg.h" -#include "hppe_ctrlpkt.h" -#include "hppe_fdb_reg.h" -#include "hppe_fdb.h" -#include "adpt.h" - -a_uint32_t -_get_mgmtctrl_ctrlpkt_profile_by_index(a_uint32_t dev_id, a_uint32_t index, fal_ctrlpkt_profile_t *ctrlpkt) -{ - union app_ctrl_u entry; - - SW_RTN_ON_ERROR(hppe_app_ctrl_get(dev_id, index, &entry)); - - ctrlpkt->action.action = entry.bf.cmd; - ctrlpkt->action.sg_bypass = entry.bf.sg_byp; - ctrlpkt->action.l2_filter_bypass = entry.bf.l2_sec_byp; - ctrlpkt->action.in_stp_bypass = entry.bf.in_stg_byp; - ctrlpkt->action.in_vlan_fltr_bypass = entry.bf.in_vlan_fltr_byp; - - if (entry.bf.portbitmap_include) - ctrlpkt->port_map = entry.bf.portbitmap; - - if (entry.bf.ethertype_include) - ctrlpkt->ethtype_profile_bitmap = entry.bf.ethertype_index_bitmap_0 | (entry.bf.ethertype_index_bitmap_1 << 2); - - if (entry.bf.rfdb_include) - ctrlpkt->rfdb_profile_bitmap = entry.bf.rfdb_index_bitmap_0| (entry.bf.rfdb_index_bitmap_1 << 30); - - if (entry.bf.protocol_include) { - ctrlpkt->protocol_types.mgt_eapol = (entry.bf.protocol_bitmap & (0x1 << 0))?1:0; - ctrlpkt->protocol_types.mgt_pppoe = (entry.bf.protocol_bitmap & (0x1 << 1))?1:0; - ctrlpkt->protocol_types.mgt_igmp = (entry.bf.protocol_bitmap & (0x1 << 2))?1:0; - ctrlpkt->protocol_types.mgt_arp_req = (entry.bf.protocol_bitmap & (0x1 << 3))?1:0; - ctrlpkt->protocol_types.mgt_arp_rep = (entry.bf.protocol_bitmap & (0x1 << 4))?1:0; - ctrlpkt->protocol_types.mgt_dhcp4 = (entry.bf.protocol_bitmap & (0x1 << 5))?1:0; - ctrlpkt->protocol_types.mgt_mld = (entry.bf.protocol_bitmap & (0x1 << 6))?1:0; - ctrlpkt->protocol_types.mgt_ns = (entry.bf.protocol_bitmap & (0x1 << 7))?1:0; - ctrlpkt->protocol_types.mgt_na = (entry.bf.protocol_bitmap & (0x1 << 8))?1:0; - ctrlpkt->protocol_types.mgt_dhcp6 = (entry.bf.protocol_bitmap & (0x1 << 9))?1:0; - } - - return entry.bf.valid; -} - -a_uint32_t -_check_if_ctrlpkt_equal(fal_ctrlpkt_profile_t *ctrlpkt1, fal_ctrlpkt_profile_t *ctrlpkt2) -{ - if (ctrlpkt1->action.action == ctrlpkt2->action.action && - ctrlpkt1->action.sg_bypass == ctrlpkt2->action.sg_bypass && - ctrlpkt1->action.l2_filter_bypass == ctrlpkt2->action.l2_filter_bypass && - ctrlpkt1->action.in_stp_bypass == ctrlpkt2->action.in_stp_bypass && - ctrlpkt1->action.in_vlan_fltr_bypass == ctrlpkt2->action.in_vlan_fltr_bypass && - ctrlpkt1->port_map == ctrlpkt2->port_map && - ctrlpkt1->ethtype_profile_bitmap == ctrlpkt2->ethtype_profile_bitmap && - ctrlpkt1->rfdb_profile_bitmap == ctrlpkt2->rfdb_profile_bitmap && - ctrlpkt1->protocol_types.mgt_eapol == ctrlpkt2->protocol_types.mgt_eapol && - ctrlpkt1->protocol_types.mgt_pppoe == ctrlpkt2->protocol_types.mgt_pppoe && - ctrlpkt1->protocol_types.mgt_igmp == ctrlpkt2->protocol_types.mgt_igmp && - ctrlpkt1->protocol_types.mgt_arp_req == ctrlpkt2->protocol_types.mgt_arp_req && - ctrlpkt1->protocol_types.mgt_arp_rep == ctrlpkt2->protocol_types.mgt_arp_rep && - ctrlpkt1->protocol_types.mgt_dhcp4 == ctrlpkt2->protocol_types.mgt_dhcp4 && - ctrlpkt1->protocol_types.mgt_mld == ctrlpkt2->protocol_types.mgt_mld && - ctrlpkt1->protocol_types.mgt_ns == ctrlpkt2->protocol_types.mgt_ns && - ctrlpkt1->protocol_types.mgt_na == ctrlpkt2->protocol_types.mgt_na && - ctrlpkt1->protocol_types.mgt_dhcp6 == ctrlpkt2->protocol_types.mgt_dhcp6) - return 1; - - return 0; -} - -sw_error_t -adpt_hppe_mgmtctrl_ethtype_profile_set(a_uint32_t dev_id, a_uint32_t profile_id, a_uint32_t ethtype) -{ - sw_error_t rtn = SW_OK; - - ADPT_DEV_ID_CHECK(dev_id); - - SW_RTN_ON_ERROR(hppe_ethertype_ctrl_ethertype_set(dev_id, profile_id, ethtype)); - SW_RTN_ON_ERROR(hppe_ethertype_ctrl_ethertype_en_set(dev_id, profile_id, A_TRUE)); - - return rtn; -} - -sw_error_t -adpt_hppe_mgmtctrl_ethtype_profile_get(a_uint32_t dev_id, a_uint32_t profile_id, a_uint32_t *ethtype) -{ - sw_error_t rtn = SW_OK; - - ADPT_DEV_ID_CHECK(dev_id); - ADPT_NULL_POINT_CHECK(ethtype); - - SW_RTN_ON_ERROR(hppe_ethertype_ctrl_ethertype_get(dev_id, profile_id, ethtype)); - - return rtn; -} - -sw_error_t -adpt_hppe_mgmtctrl_rfdb_profile_set(a_uint32_t dev_id, a_uint32_t profile_id, fal_mac_addr_t *addr) -{ - sw_error_t rtn = SW_OK; - a_uint64_t value = 0; - - ADPT_DEV_ID_CHECK(dev_id); - - if (profile_id >= RFDB_TBL_MAX_ENTRY) - return SW_OUT_OF_RANGE; - - value = ((((a_uint64_t)(addr->uc[5])) << 0) | - (((a_uint64_t)(addr->uc[4])) << 8) | - (((a_uint64_t)(addr->uc[3])) << 16) | - (((a_uint64_t)(addr->uc[2])) << 24) | - (((a_uint64_t)(addr->uc[1])) << 32) | - (((a_uint64_t)(addr->uc[0])) << 40)); - - SW_RTN_ON_ERROR(hppe_rfdb_tbl_mac_addr_set(dev_id, profile_id, value)); - SW_RTN_ON_ERROR(hppe_rfdb_tbl_valid_set(dev_id, profile_id, A_TRUE)); - - return rtn; -} - -sw_error_t -adpt_hppe_mgmtctrl_rfdb_profile_get(a_uint32_t dev_id, a_uint32_t profile_id, fal_mac_addr_t *addr) -{ - sw_error_t rtn = SW_OK; - a_uint64_t value = 0; - - ADPT_DEV_ID_CHECK(dev_id); - ADPT_NULL_POINT_CHECK(addr); - - if (profile_id >= RFDB_TBL_MAX_ENTRY) - return SW_OUT_OF_RANGE; - - SW_RTN_ON_ERROR(hppe_rfdb_tbl_mac_addr_get(dev_id, profile_id, &value)); - addr->uc[0] = (a_uint8_t)((value >> 40)& 0xff); - addr->uc[1] = (a_uint8_t)((value >> 32) & 0xff); - addr->uc[2] = (a_uint8_t)((value >> 24) & 0xff); - addr->uc[3] = (a_uint8_t)((value >> 16) & 0xff); - addr->uc[4] = (a_uint8_t)((value >> 8) & 0xff); - addr->uc[5] = (a_uint8_t)((value >> 0) & 0xff); - - return rtn; -} - -sw_error_t -adpt_hppe_mgmtctrl_ctrlpkt_profile_add(a_uint32_t dev_id, fal_ctrlpkt_profile_t *ctrlpkt) -{ - union app_ctrl_u entry; - a_uint32_t index, ctrlpkt_valid, entry_sign, entry_index; - fal_ctrlpkt_profile_t ctrlpkt_temp; - - ADPT_DEV_ID_CHECK(dev_id); - - entry_index = 0; - entry_sign = 0; - for (index = 0; index < APP_CTRL_MAX_ENTRY; index++) - { - memset(&ctrlpkt_temp, 0, sizeof(fal_ctrlpkt_profile_t)); - ctrlpkt_valid = _get_mgmtctrl_ctrlpkt_profile_by_index(dev_id, index, &ctrlpkt_temp); - if (ctrlpkt_valid == 1) - { - if (_check_if_ctrlpkt_equal(&ctrlpkt_temp, ctrlpkt)) - return SW_ALREADY_EXIST; - } - else - { - if (entry_sign == 0) { - entry_index = index; - entry_sign = 1; - } - } - } - - if (entry_sign == 0) - return SW_NO_RESOURCE; - - memset(&entry, 0, sizeof(union app_ctrl_u)); - - entry.bf.valid = A_TRUE; - entry.bf.rfdb_include = ctrlpkt->rfdb_profile_bitmap?1:0; - entry.bf.rfdb_index_bitmap_0 = (ctrlpkt->rfdb_profile_bitmap & 0x3fffffff); - entry.bf.rfdb_index_bitmap_1 = (ctrlpkt->rfdb_profile_bitmap >> 30); - - if (ctrlpkt->protocol_types.mgt_eapol) - entry.bf.protocol_bitmap |= (0x1 << 0); - if (ctrlpkt->protocol_types.mgt_pppoe) - entry.bf.protocol_bitmap |= (0x1 << 1); - if (ctrlpkt->protocol_types.mgt_igmp) - entry.bf.protocol_bitmap |= (0x1 << 2); - if (ctrlpkt->protocol_types.mgt_arp_req) - entry.bf.protocol_bitmap |= (0x1 << 3); - if (ctrlpkt->protocol_types.mgt_arp_rep) - entry.bf.protocol_bitmap |= (0x1 << 4); - if (ctrlpkt->protocol_types.mgt_dhcp4) - entry.bf.protocol_bitmap |= (0x1 << 5); - if (ctrlpkt->protocol_types.mgt_mld) - entry.bf.protocol_bitmap |= (0x1 << 6); - if (ctrlpkt->protocol_types.mgt_ns) - entry.bf.protocol_bitmap |= (0x1 << 7); - if (ctrlpkt->protocol_types.mgt_na) - entry.bf.protocol_bitmap |= (0x1 << 8); - if (ctrlpkt->protocol_types.mgt_dhcp6) - entry.bf.protocol_bitmap |= (0x1 << 9); - - entry.bf.protocol_include = entry.bf.protocol_bitmap?1:0; - - entry.bf.ethertype_include = ctrlpkt->ethtype_profile_bitmap?1:0; - entry.bf.ethertype_index_bitmap_0 = (ctrlpkt->ethtype_profile_bitmap & 0x3); - entry.bf.ethertype_index_bitmap_1 = (ctrlpkt->ethtype_profile_bitmap >> 2); - - entry.bf.portbitmap_include = ctrlpkt->port_map?1:0; - entry.bf.portbitmap = ctrlpkt->port_map; - - entry.bf.in_vlan_fltr_byp = ctrlpkt->action.in_vlan_fltr_bypass?1:0; - entry.bf.in_stg_byp = ctrlpkt->action.in_stp_bypass?1:0; - entry.bf.l2_sec_byp = ctrlpkt->action.l2_filter_bypass?1:0; - entry.bf.sg_byp = ctrlpkt->action.sg_bypass?1:0; - entry.bf.cmd = (a_uint32_t)ctrlpkt->action.action; - SW_RTN_ON_ERROR(hppe_app_ctrl_set(dev_id, entry_index, &entry)); - - return SW_OK; -} - -sw_error_t -adpt_hppe_mgmtctrl_ctrlpkt_profile_del(a_uint32_t dev_id, fal_ctrlpkt_profile_t *ctrlpkt) -{ - a_uint32_t index, ctrlpkt_valid; - union app_ctrl_u entry; - fal_ctrlpkt_profile_t ctrlpkt_temp; - - memset(&entry, 0, sizeof(union app_ctrl_u)); - - ADPT_DEV_ID_CHECK(dev_id); - ADPT_NULL_POINT_CHECK(ctrlpkt); - - for (index = 0; index < APP_CTRL_MAX_ENTRY; index++) - { - memset(&ctrlpkt_temp, 0, sizeof(fal_ctrlpkt_profile_t)); - ctrlpkt_valid = _get_mgmtctrl_ctrlpkt_profile_by_index(dev_id, index, &ctrlpkt_temp); - if (ctrlpkt_valid == 1) - { - if (_check_if_ctrlpkt_equal(&ctrlpkt_temp, ctrlpkt)) - { - SW_RTN_ON_ERROR(hppe_app_ctrl_set(dev_id, index, &entry)); - return SW_OK; - } - } - } - - return SW_NOT_FOUND; -} - -sw_error_t -adpt_hppe_mgmtctrl_ctrlpkt_profile_getfirst(a_uint32_t dev_id, fal_ctrlpkt_profile_t *ctrlpkt) -{ - a_uint32_t index, ctrlpkt_valid; - - for (index = 0; index < APP_CTRL_MAX_ENTRY; index++) - { - ctrlpkt_valid = _get_mgmtctrl_ctrlpkt_profile_by_index(dev_id, index, ctrlpkt); - if (ctrlpkt_valid == 1) - return SW_OK; - } - - return SW_NO_MORE; -} - -sw_error_t -adpt_hppe_mgmtctrl_ctrlpkt_profile_getnext(a_uint32_t dev_id, fal_ctrlpkt_profile_t *ctrlpkt) -{ - a_uint32_t index, ctrlpkt_valid, sign_tag; - fal_ctrlpkt_profile_t ctrlpkt_temp; - - sign_tag = 0; - - for (index = 0; index < APP_CTRL_MAX_ENTRY; index++) - { - memset(&ctrlpkt_temp, 0, sizeof(fal_ctrlpkt_profile_t)); - ctrlpkt_valid = _get_mgmtctrl_ctrlpkt_profile_by_index(dev_id, index, &ctrlpkt_temp); - if (ctrlpkt_valid == 1) - { - if (sign_tag == 1) { - aos_mem_copy(ctrlpkt, &ctrlpkt_temp, sizeof(fal_ctrlpkt_profile_t)); - return SW_OK; - } - if (_check_if_ctrlpkt_equal(&ctrlpkt_temp, ctrlpkt)) - sign_tag = 1; - } - } - - return SW_NO_MORE; -} - -void adpt_hppe_ctrlpkt_func_bitmap_init(a_uint32_t dev_id) -{ - adpt_api_t *p_adpt_api = NULL; - - p_adpt_api = adpt_api_ptr_get(dev_id); - - if(p_adpt_api == NULL) - return; - - p_adpt_api->adpt_ctrlpkt_func_bitmap = ((1 << FUNC_MGMTCTRL_ETHTYPE_PROFILE_SET) | - (1 << FUNC_MGMTCTRL_ETHTYPE_PROFILE_GET) | - (1 << FUNC_MGMTCTRL_RFDB_PROFILE_SET) | - (1 << FUNC_MGMTCTRL_RFDB_PROFILE_GET) | - (1 << FUNC_MGMTCTRL_CTRLPKT_PROFILE_ADD) | - (1 << FUNC_MGMTCTRL_CTRLPKT_PROFILE_DEL) | - (1 << FUNC_MGMTCTRL_CTRLPKT_PROFILE_GETFIRST) | - (1 << FUNC_MGMTCTRL_CTRLPKT_PROFILE_GETNEXT)); - - return; -} - -static void adpt_hppe_ctrlpkt_func_unregister(a_uint32_t dev_id, adpt_api_t *p_adpt_api) -{ - if(p_adpt_api == NULL) - return; - - p_adpt_api->adpt_mgmtctrl_ethtype_profile_set = NULL; - p_adpt_api->adpt_mgmtctrl_ethtype_profile_get = NULL; - p_adpt_api->adpt_mgmtctrl_rfdb_profile_set = NULL; - p_adpt_api->adpt_mgmtctrl_rfdb_profile_get = NULL; - p_adpt_api->adpt_mgmtctrl_ctrlpkt_profile_add = NULL; - p_adpt_api->adpt_mgmtctrl_ctrlpkt_profile_del = NULL; - p_adpt_api->adpt_mgmtctrl_ctrlpkt_profile_getfirst = NULL; - p_adpt_api->adpt_mgmtctrl_ctrlpkt_profile_getnext = NULL; - - return; -} - -sw_error_t adpt_hppe_ctrlpkt_init(a_uint32_t dev_id) -{ - adpt_api_t *p_adpt_api = NULL; - - p_adpt_api = adpt_api_ptr_get(dev_id); - - if(p_adpt_api == NULL) - return SW_FAIL; - - adpt_hppe_ctrlpkt_func_unregister(dev_id, p_adpt_api); - - if (p_adpt_api->adpt_ctrlpkt_func_bitmap & (1 << FUNC_MGMTCTRL_ETHTYPE_PROFILE_SET)) - p_adpt_api->adpt_mgmtctrl_ethtype_profile_set = adpt_hppe_mgmtctrl_ethtype_profile_set; - if (p_adpt_api->adpt_ctrlpkt_func_bitmap & (1 << FUNC_MGMTCTRL_ETHTYPE_PROFILE_GET)) - p_adpt_api->adpt_mgmtctrl_ethtype_profile_get = adpt_hppe_mgmtctrl_ethtype_profile_get; - if (p_adpt_api->adpt_ctrlpkt_func_bitmap & (1 << FUNC_MGMTCTRL_RFDB_PROFILE_SET)) - p_adpt_api->adpt_mgmtctrl_rfdb_profile_set = adpt_hppe_mgmtctrl_rfdb_profile_set; - if (p_adpt_api->adpt_ctrlpkt_func_bitmap & (1 << FUNC_MGMTCTRL_RFDB_PROFILE_GET)) - p_adpt_api->adpt_mgmtctrl_rfdb_profile_get = adpt_hppe_mgmtctrl_rfdb_profile_get; - if (p_adpt_api->adpt_ctrlpkt_func_bitmap & (1 << FUNC_MGMTCTRL_CTRLPKT_PROFILE_ADD)) - p_adpt_api->adpt_mgmtctrl_ctrlpkt_profile_add = adpt_hppe_mgmtctrl_ctrlpkt_profile_add; - if (p_adpt_api->adpt_ctrlpkt_func_bitmap & (1 << FUNC_MGMTCTRL_CTRLPKT_PROFILE_DEL)) - p_adpt_api->adpt_mgmtctrl_ctrlpkt_profile_del = adpt_hppe_mgmtctrl_ctrlpkt_profile_del; - if (p_adpt_api->adpt_ctrlpkt_func_bitmap & (1 << FUNC_MGMTCTRL_CTRLPKT_PROFILE_GETFIRST)) - p_adpt_api->adpt_mgmtctrl_ctrlpkt_profile_getfirst = adpt_hppe_mgmtctrl_ctrlpkt_profile_getfirst; - if (p_adpt_api->adpt_ctrlpkt_func_bitmap & (1 << FUNC_MGMTCTRL_CTRLPKT_PROFILE_GETNEXT)) - p_adpt_api->adpt_mgmtctrl_ctrlpkt_profile_getnext = adpt_hppe_mgmtctrl_ctrlpkt_profile_getnext; - - return SW_OK; -} - -/** - * @} - */ - diff --git a/feeds/ipq807x/qca-ssdk/src/src/adpt/hppe/adpt_hppe_fdb.c b/feeds/ipq807x/qca-ssdk/src/src/adpt/hppe/adpt_hppe_fdb.c deleted file mode 100755 index 2d8a6352d..000000000 --- a/feeds/ipq807x/qca-ssdk/src/src/adpt/hppe/adpt_hppe_fdb.c +++ /dev/null @@ -1,1520 +0,0 @@ -/* - * Copyright (c) 2016-2018, The Linux Foundation. All rights reserved. - * Permission to use, copy, modify, and/or distribute this software for - * any purpose with or without fee is hereby granted, provided that the - * above copyright notice and this permission notice appear in all copies. - * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES - * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR - * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES - * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN - * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT - * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. - */ - - -/** - * @defgroup - * @{ - */ -#include "sw.h" -#include "hppe_fdb_reg.h" -#include "hppe_fdb.h" -#include "adpt.h" - -#define OP_TYPE_ADD 0x0 -#define OP_TYPE_DEL 0x1 -#define OP_TYPE_GET 0x2 -#define OP_TYPE_FLUSH 0x4 -#define OP_TYPE_AGE 0x5 - -#define OP_MODE_HASH 0x0 -#define OP_MODE_INDEX 0x1 - -#define OP_CMD_ID_SIZE 0xf - -#define OP_FIFO_CNT_SIZE 0x8 - -#define ARL_FIRST_ENTRY 0x0 -#define ARL_NEXT_ENTRY 0x1 -#define ARL_EXTENDFIRST_ENTRY 0x2 -#define ARL_EXTENDNEXT_ENTRY 0x3 - - -static aos_lock_t hppe_fdb_lock; - -/* - * Remove port type. - * Current fal_port_t format: - * 1) highest 8 bits is defined as port type. - * 2) lowest 24 bits for port id value. - * The range of physical port id is 0-7, the range of trunk id is 32-33, and the range of virtual port is 64-255. - * Port type: 0 is physical port, 1 is trunk port, 2 is virtual port. - */ -sw_error_t -_remove_port_type(fal_port_t * port_id) -{ - *port_id = FAL_PORT_ID_VALUE(*port_id); - return SW_OK; -} - -/* - * Add port type. - * Current fal_port_t format: - * 1) highest 8 bits is defined as port type. - * 2) lowest 24 bits for port id value. - * The range of physical port id is 0-7, the range of trunk id is 32-33, and the range of virtual port is 64-255. - * Port type: 0 is physical port, 1 is trunk port, 2 is virtual port. - */ -sw_error_t -_add_port_type(a_bool_t bitmap, fal_port_t * port_id) -{ - if (bitmap == A_TRUE) - return SW_OK; - - if (*port_id == 32 || *port_id == 33) - *port_id = FAL_PORT_ID(FAL_PORT_TYPE_TRUNK, *port_id); - else if (*port_id >= 64) - *port_id = FAL_PORT_ID(FAL_PORT_TYPE_VPORT, *port_id); - return SW_OK; -} - -/* - * set values to register FDB_TBL_OP - */ -sw_error_t -_adpt_hppe_fdb_tbl_op_reg_set(a_uint32_t dev_id, a_uint32_t cmd_id, a_uint32_t op_type) -{ - sw_error_t rv = SW_OK; - union fdb_tbl_op_u reg_val_op; - a_uint32_t op_mode = OP_MODE_HASH; - a_uint32_t entry_index = 0x0; - - reg_val_op.bf.cmd_id = cmd_id; - reg_val_op.bf.byp_rslt_en = 0x0; - reg_val_op.bf.op_type = op_type; - reg_val_op.bf.hash_block_bitmap = 0x3; - reg_val_op.bf.op_mode = op_mode; - reg_val_op.bf.entry_index = entry_index; - rv = hppe_fdb_tbl_op_set(dev_id, ®_val_op); - - return rv; -} - -/* - * get results from register FDB_TBL_OP_RSLT - */ -sw_error_t -_adpt_hppe_fdb_tbl_op_rslt_reg_get(a_uint32_t dev_id, a_uint32_t cmd_id) -{ - sw_error_t rv = SW_OK; - union fdb_tbl_op_rslt_u reg_val_op_rslt; - - rv = hppe_fdb_tbl_op_rslt_get(dev_id, ®_val_op_rslt); - - if (rv != SW_OK || reg_val_op_rslt.bf.cmd_id != cmd_id || reg_val_op_rslt.bf.valid_cnt > OP_FIFO_CNT_SIZE) - return SW_FAIL; - - return SW_OK; -} - -/* - * set values to register FDB_TBL_RD_OP - */ -sw_error_t -_adpt_hppe_fdb_tbl_rd_op_reg_set(a_uint32_t dev_id, a_uint32_t cmd_id, a_uint32_t op_mode, a_uint32_t entry_index) -{ - sw_error_t rv = SW_OK; - union fdb_tbl_rd_op_u reg_val_rd_op; - a_uint32_t op_type = OP_TYPE_GET; - - reg_val_rd_op.bf.cmd_id = cmd_id; - reg_val_rd_op.bf.byp_rslt_en = 0x0; - reg_val_rd_op.bf.op_type = op_type; - reg_val_rd_op.bf.hash_block_bitmap = 0x3; - reg_val_rd_op.bf.op_mode = op_mode; - reg_val_rd_op.bf.entry_index = entry_index; - rv = hppe_fdb_tbl_rd_op_set(dev_id, ®_val_rd_op); - - return rv; -} - -/* - * get results from register FDB_TBL_RD_OP_RSLT - */ -sw_error_t -_adpt_hppe_fdb_tbl_rd_op_rslt_reg_get(a_uint32_t dev_id, a_uint32_t cmd_id, a_uint32_t *entry_index) -{ - sw_error_t rv = SW_OK; - union fdb_tbl_rd_op_rslt_u reg_val_rd_op_rslt; - - rv = hppe_fdb_tbl_rd_op_rslt_get(dev_id, ®_val_rd_op_rslt); - - if (rv != SW_OK || reg_val_rd_op_rslt.bf.cmd_id != cmd_id || - reg_val_rd_op_rslt.bf.valid_cnt > OP_FIFO_CNT_SIZE) - { - return SW_FAIL; - } - - *entry_index = reg_val_rd_op_rslt.bf.entry_index; - - return SW_OK; -} - -/* - * set values to register FDB_TBL_OP_DATA0/FDB_TBL_OP_DATA1/FDB_TBL_OP_DATA2 - */ -sw_error_t -_adpt_hppe_fdb_tbl_op_data_reg_set(a_uint32_t dev_id, fal_fdb_entry_t * entry) -{ - sw_error_t rv = SW_OK; - a_uint32_t i, port_value, dst_type = 0x0; - a_uint32_t reg_value[3] = {0}; - - ADPT_DEV_ID_CHECK(dev_id); - ADPT_NULL_POINT_CHECK(entry); - - for (i = 2; i < 6; i++) - { - reg_value[0] = (reg_value[0] << 8) + entry->addr.uc[i]; - } - rv = hppe_fdb_tbl_op_data0_data_set(dev_id, reg_value[0]); - if (rv != SW_OK) - return rv; - - for (i = 0; i < 2; i++) - { - reg_value[1] = (reg_value[1] << 8) + entry->addr.uc[i]; - } - reg_value[1] += (0x1 << (FDB_TBL_ENTRY_VALID_OFFSET - 32)) + (0x1 << (FDB_TBL_LOOKUP_VALID_OFFSET -32)) + - (entry->fid << (FDB_TBL_VSI_OFFSET - 32)); - if (entry->portmap_en == A_TRUE) - { - port_value = entry->port.map; - dst_type = 0x3; - } - else - { - port_value = entry->port.id; - dst_type = 0x2; - } - reg_value[1] += ((port_value & 0x1ff) << (FDB_TBL_DST_INFO_OFFSET - 32)); - rv = hppe_fdb_tbl_op_data1_data_set(dev_id, reg_value[1]); - if (rv != SW_OK) - return rv; - - reg_value[2] = ((port_value >> 0x9) & 0x7) + ((dst_type & 0x3) << 3) + - ((entry->sacmd & 0x3) << (FDB_TBL_SA_CMD_OFFSET - 64)) + - ((entry->dacmd & 0x3) << (FDB_TBL_DA_CMD_OFFSET - 64)); - if (entry->static_en == A_TRUE) - reg_value[2] += (0x3 << (FDB_TBL_HIT_AGE_OFFSET - 64)); - else - reg_value[2] += (0x2 << (FDB_TBL_HIT_AGE_OFFSET - 64)); - rv = hppe_fdb_tbl_op_data2_data_set(dev_id, reg_value[2]); - if (rv != SW_OK) - return rv; - - return SW_OK; -} - -/* - * set values to register FDB_TBL_RD_OP_DATA0/FDB_TBL_RD_OP_DATA1/FDB_TBL_RD_OP_DATA2 - */ -sw_error_t -_adpt_hppe_fdb_tbl_rd_op_data_reg_set(a_uint32_t dev_id, fal_fdb_entry_t * entry) -{ - sw_error_t rv = SW_OK; - a_uint32_t i, reg_value[3] = {0}; - - for (i = 2; i < 6; i++) - { - reg_value[0] = (reg_value[0] << 8) + entry->addr.uc[i]; - } - rv = hppe_fdb_tbl_rd_op_data0_data_set(dev_id, reg_value[0]); - if (rv != SW_OK) - return rv; - - for (i = 0; i < 2; i++) - { - reg_value[1] = (reg_value[1] << 8) + entry->addr.uc[i]; - } - reg_value[1] += (entry->fid << (FDB_TBL_VSI_OFFSET - 32)); - rv = hppe_fdb_tbl_rd_op_data1_data_set(dev_id, reg_value[1]); - if (rv != SW_OK) - return rv; - - rv = hppe_fdb_tbl_rd_op_data2_data_set(dev_id, reg_value[2]); - if (rv != SW_OK) - return rv; - - return SW_OK; -} - -/* - * get values from register FDB_TBL_RD_OP_RSLT_DATA0/FDB_TBL_RD_OP_RSLT_DATA1/FDB_TBL_RD_OP_RSLT_DATA2 - */ -sw_error_t -_adpt_hppe_fdb_tbl_rd_op_rslt_data_reg_get(a_uint32_t dev_id, fal_fdb_entry_t * entry) -{ - a_uint32_t rslt_data[3]; - a_uint32_t entry_valid, lookup_valid; - a_uint32_t i, dst_info_encode; - - hppe_fdb_tbl_rd_op_rslt_data0_data_get(dev_id, &rslt_data[0]); - hppe_fdb_tbl_rd_op_rslt_data1_data_get(dev_id, &rslt_data[1]); - hppe_fdb_tbl_rd_op_rslt_data2_data_get(dev_id, &rslt_data[2]); - - entry_valid = (rslt_data[1] >> (FDB_TBL_ENTRY_VALID_OFFSET - 32)) & 0x1; - lookup_valid = (rslt_data[1] >> (FDB_TBL_LOOKUP_VALID_OFFSET - 32)) & 0x1; - dst_info_encode = (rslt_data[2] >> (FDB_TBL_DST_INFO_OFFSET + 12 -64)) & 0x3; - - if (entry_valid == 0x0 || dst_info_encode == 0x0) - { - return SW_NOT_FOUND; - } - else - { - entry->entry_valid = A_TRUE; - if (lookup_valid == 0x1) - entry->lookup_valid = A_TRUE; - else - entry->lookup_valid = A_FALSE; - entry->fid = (rslt_data[1] >> (FDB_TBL_VSI_OFFSET - 32)) & 0x1f; - entry->sacmd = (rslt_data[2] >> (FDB_TBL_SA_CMD_OFFSET - 64)) & 0x3; - entry->dacmd = (rslt_data[2] >> (FDB_TBL_DA_CMD_OFFSET - 64)) & 0x3; - if (((rslt_data[2] >> (FDB_TBL_HIT_AGE_OFFSET - 64)) & 0x3) == 0x3) - entry->static_en = A_TRUE; - else - entry->static_en = A_FALSE; - if (dst_info_encode == 0x2) - { - entry->portmap_en = A_FALSE; - entry->port.id = ((rslt_data[2] & 0x7) << 9) + ((rslt_data[1] >> (FDB_TBL_DST_INFO_OFFSET - 32)) & 0x1ff); - } - else - { - entry->portmap_en = A_TRUE; - entry->port.map = ((rslt_data[2] & 0x7) << 9) + ((rslt_data[1] >> (FDB_TBL_DST_INFO_OFFSET - 32)) & 0x1ff); - } - for (i = 2; i < 6; i++) - entry->addr.uc[i] = (rslt_data[0] >> ((5 - i) << 3)) & 0xff; - for (i = 0; i < 2; i++) - entry->addr.uc[i] = (rslt_data[1] >> ((1 - i) << 3)) & 0xff; - } - - return SW_OK; -} - -sw_error_t -_get_fdb_table_entryindex_by_entry(a_uint32_t dev_id, fal_fdb_entry_t * entry, - a_uint32_t *entry_index, a_uint32_t cmd_id) -{ - sw_error_t rv = SW_OK; - a_uint32_t init_entry_index = 0; - fal_fdb_entry_t temp_entry; - - aos_lock_bh(&hppe_fdb_lock); - rv = _adpt_hppe_fdb_tbl_rd_op_data_reg_set(dev_id, entry); - if (rv != SW_OK) - { - aos_unlock_bh(&hppe_fdb_lock); - return rv; - } - - rv = _adpt_hppe_fdb_tbl_rd_op_reg_set(dev_id, cmd_id, OP_MODE_HASH, init_entry_index); - if (rv != SW_OK) - { - aos_unlock_bh(&hppe_fdb_lock); - return rv; - } - - rv = _adpt_hppe_fdb_tbl_rd_op_rslt_data_reg_get(dev_id, &temp_entry); - - rv = _adpt_hppe_fdb_tbl_rd_op_rslt_reg_get(dev_id, cmd_id, entry_index); - if (rv != SW_OK) - { - aos_unlock_bh(&hppe_fdb_lock); - return rv; - } - - aos_unlock_bh(&hppe_fdb_lock); - - if (*entry_index == 0) - { - if (!(temp_entry.addr.uc[0] == entry->addr.uc[0] && temp_entry.addr.uc[1] == entry->addr.uc[1] && - temp_entry.addr.uc[2] == entry->addr.uc[2] && temp_entry.addr.uc[3] == entry->addr.uc[3] && - temp_entry.addr.uc[4] == entry->addr.uc[4] && temp_entry.addr.uc[5] == entry->addr.uc[5] && - temp_entry.fid == entry->fid)) - return SW_NOT_FOUND; - } - - return SW_OK; -} - -sw_error_t -_get_fdb_table_entry_by_entryindex(a_uint32_t dev_id, fal_fdb_entry_t * entry, - a_uint32_t entry_index, a_uint32_t cmd_id) -{ - sw_error_t rv = SW_OK, rv1 = SW_OK; - fal_fdb_entry_t init_entry; - a_uint32_t rslt_entry_index = 0; - - aos_mem_zero(&init_entry, sizeof (fal_fdb_entry_t)); - - aos_lock_bh(&hppe_fdb_lock); - rv = _adpt_hppe_fdb_tbl_rd_op_data_reg_set(dev_id, &init_entry); - if (rv != SW_OK) - { - aos_unlock_bh(&hppe_fdb_lock); - return rv; - } - - rv = _adpt_hppe_fdb_tbl_rd_op_reg_set(dev_id, cmd_id, OP_MODE_INDEX, entry_index); - if (rv != SW_OK) - { - aos_unlock_bh(&hppe_fdb_lock); - return rv; - } - - rv = _adpt_hppe_fdb_tbl_rd_op_rslt_data_reg_get(dev_id, entry); - if (rv != SW_OK && rv != SW_NOT_FOUND) - { - aos_unlock_bh(&hppe_fdb_lock); - return rv; - } - else - rv1 = rv; - - rv = _adpt_hppe_fdb_tbl_rd_op_rslt_reg_get(dev_id, cmd_id, &rslt_entry_index); - if (rv != SW_OK) - { - aos_unlock_bh(&hppe_fdb_lock); - return rv; - } - - aos_unlock_bh(&hppe_fdb_lock); - - return rv1; -} - -sw_error_t -_modify_fdb_table_entry(a_uint32_t dev_id, fal_fdb_entry_t * entry, a_uint32_t op_type, - a_uint32_t cmd_id) -{ - sw_error_t rv = SW_OK; - fal_fdb_entry_t temp_entry; - - aos_lock_bh(&hppe_fdb_lock); - rv = _adpt_hppe_fdb_tbl_op_data_reg_set(dev_id, entry); - if (rv != SW_OK) - { - aos_unlock_bh(&hppe_fdb_lock); - return rv; - } - - rv = _adpt_hppe_fdb_tbl_op_reg_set(dev_id, cmd_id, op_type); - if (rv != SW_OK) - { - aos_unlock_bh(&hppe_fdb_lock); - return rv; - } - - rv = _adpt_hppe_fdb_tbl_rd_op_rslt_data_reg_get(dev_id, &temp_entry); - - rv = _adpt_hppe_fdb_tbl_op_rslt_reg_get(dev_id, cmd_id); - if (rv != SW_OK) - { - aos_unlock_bh(&hppe_fdb_lock); - return rv; - } - - aos_unlock_bh(&hppe_fdb_lock); - - return SW_OK; -} - -sw_error_t -_adpt_hppe_fdb_extend_first_next(a_uint32_t dev_id, fal_fdb_entry_t * entry, fal_fdb_op_t * option, a_uint32_t hwop) -{ - sw_error_t rv; - a_uint32_t cmd_id = 0x0; - a_uint32_t entry_index = 0x0; - fal_fdb_entry_t ori_entry; - - aos_mem_zero(&ori_entry, sizeof (fal_fdb_entry_t)); - - if (hwop == ARL_EXTENDFIRST_ENTRY || hwop == ARL_EXTENDNEXT_ENTRY) - { - ori_entry.portmap_en = entry->portmap_en; - ori_entry.port.id = entry->port.id; - ori_entry.fid = entry->fid; - } - - if (hwop == ARL_FIRST_ENTRY || hwop == ARL_EXTENDFIRST_ENTRY) - aos_mem_zero(entry, sizeof (fal_fdb_entry_t)); - - rv = _get_fdb_table_entryindex_by_entry(dev_id, entry, &entry_index, cmd_id); - if (rv != SW_OK && rv != SW_NOT_FOUND) - return rv; - - if (rv != SW_NOT_FOUND) - entry_index += 1; - - for (; entry_index < FDB_TBL_NUM; entry_index++) - { - cmd_id = entry_index % OP_CMD_ID_SIZE; - rv = _get_fdb_table_entry_by_entryindex(dev_id, entry, entry_index, cmd_id); - if (rv == SW_NOT_FOUND) - continue; - else if (rv == SW_OK) - { - if (hwop == ARL_EXTENDFIRST_ENTRY || hwop == ARL_EXTENDNEXT_ENTRY) - { - if (option->fid_en == A_TRUE && ori_entry.fid != entry->fid) - continue; - if (option->port_en == A_TRUE && !(ori_entry.portmap_en == entry->portmap_en && - ori_entry.port.id == entry->port.id)) - continue; - } - break; - } - else - return rv; - } - - if (entry_index == FDB_TBL_NUM) - return SW_NO_MORE; - return SW_OK; -} - -void _fdb_copy(fal_fdb_entry_t *new, const fal_fdb_entry_t *old) -{ - a_uint32_t i; - - aos_mem_zero(new, sizeof (fal_fdb_entry_t)); - - for (i = 0; i < 6; i++) - new->addr.uc[i] = old->addr.uc[i]; - - new->fid = old->fid; - new->dacmd = old->dacmd; - new->sacmd = old->sacmd; - new->port.id = old->port.id; - new->portmap_en = old->portmap_en; - new->is_multicast = old->is_multicast; - new->static_en = old->static_en; - -} - -sw_error_t -adpt_hppe_fdb_first(a_uint32_t dev_id, fal_fdb_entry_t * entry) -{ - fal_fdb_op_t option; - sw_error_t rv; - - ADPT_DEV_ID_CHECK(dev_id); - ADPT_NULL_POINT_CHECK(entry); - - aos_mem_zero(&option, sizeof (fal_fdb_op_t)); - - _remove_port_type(&entry->port.id); - rv = _adpt_hppe_fdb_extend_first_next(dev_id, entry, &option, ARL_FIRST_ENTRY); - _add_port_type(entry->portmap_en, &entry->port.id); - - return rv; -} -#ifndef IN_FDB_MINI -sw_error_t -adpt_hppe_fdb_next(a_uint32_t dev_id, fal_fdb_entry_t * entry) -{ - fal_fdb_op_t option; - sw_error_t rv; - - ADPT_DEV_ID_CHECK(dev_id); - ADPT_NULL_POINT_CHECK(entry); - - aos_mem_zero(&option, sizeof (fal_fdb_op_t)); - - _remove_port_type(&entry->port.id); - rv = _adpt_hppe_fdb_extend_first_next(dev_id, entry, &option, ARL_NEXT_ENTRY); - _add_port_type(entry->portmap_en, &entry->port.id); - - return rv; -} -#endif -sw_error_t -adpt_hppe_fdb_add(a_uint32_t dev_id, const fal_fdb_entry_t * entry) -{ - sw_error_t rv = SW_OK; - fal_fdb_entry_t entry_temp; - - ADPT_DEV_ID_CHECK(dev_id); - ADPT_NULL_POINT_CHECK(entry); - - _fdb_copy(&entry_temp, entry); - - _remove_port_type(&entry_temp.port.id); - rv = _modify_fdb_table_entry(dev_id, &entry_temp, OP_TYPE_ADD, 0x0); - _add_port_type(entry_temp.portmap_en, &entry_temp.port.id); - - return rv; -} - -sw_error_t -adpt_hppe_fdb_del_by_mac(a_uint32_t dev_id, const fal_fdb_entry_t *entry) -{ - sw_error_t rv = SW_OK; - fal_fdb_entry_t entry_temp; - ADPT_DEV_ID_CHECK(dev_id); - ADPT_NULL_POINT_CHECK(entry); - - _fdb_copy(&entry_temp, entry); - _remove_port_type(&entry_temp.port.id); - rv = _modify_fdb_table_entry(dev_id, &entry_temp, OP_TYPE_DEL, 0x0); - _add_port_type(entry_temp.portmap_en, &entry_temp.port.id); - - return rv; -} - -sw_error_t -adpt_hppe_fdb_del_by_port(a_uint32_t dev_id, a_uint32_t port_id, a_uint32_t flag) -{ - a_uint32_t entry_index, id, cmd_id = 0; - sw_error_t rv = SW_OK; - fal_fdb_entry_t entry; - - ADPT_DEV_ID_CHECK(dev_id); - - _remove_port_type(&port_id); - - for (entry_index = 0; entry_index < FDB_TBL_NUM; entry_index++) - { - cmd_id = entry_index % OP_CMD_ID_SIZE; - aos_mem_zero(&entry, sizeof (fal_fdb_entry_t)); - rv = _get_fdb_table_entry_by_entryindex(dev_id, &entry, entry_index, cmd_id); - - if (rv == SW_NOT_FOUND) - continue; - else if (rv == SW_OK) - { - if (entry.portmap_en == A_TRUE) - { - if (((entry.port.map >> port_id) & 0x1) == 1) - { - if ((!flag && entry.static_en == A_FALSE) || (flag & FAL_FDB_DEL_STATIC)) - { - id = entry.port.map & (~(0x1 << port_id)); - if (id == 0) - { - rv = _modify_fdb_table_entry(dev_id, &entry, OP_TYPE_DEL, 0x0); - if (rv != SW_OK) - return rv; - } - else - { - entry.port.map &= (~(0x1 << port_id)); - rv = adpt_hppe_fdb_add(dev_id, &entry); - if (rv != SW_OK) - return rv; - } - } - } - } - else - { - if (entry.port.id == port_id && - ((!flag && entry.static_en == A_FALSE) || (flag & FAL_FDB_DEL_STATIC))) - { - rv = _modify_fdb_table_entry(dev_id, &entry, OP_TYPE_DEL, 0x0); - if (rv != SW_OK) - return rv; - } - } - } - else - return rv; - } - - return SW_OK; -} - -sw_error_t -adpt_hppe_fdb_del_all(a_uint32_t dev_id, a_uint32_t flag) -{ - sw_error_t rv; - fal_fdb_entry_t entry; - a_uint32_t entry_index = 0, cmd_id; - - ADPT_DEV_ID_CHECK(dev_id); - - if (FAL_FDB_DEL_STATIC & flag) - { - aos_mem_zero(&entry, sizeof (fal_fdb_entry_t)); - return _modify_fdb_table_entry(dev_id, &entry, OP_TYPE_FLUSH, 0x0); - } - else - { - for (entry_index = 0; entry_index < FDB_TBL_NUM; entry_index++) - { - cmd_id = entry_index % OP_CMD_ID_SIZE; - aos_mem_zero(&entry, sizeof (fal_fdb_entry_t)); - rv = _get_fdb_table_entry_by_entryindex(dev_id, &entry, entry_index, cmd_id); - if (rv != SW_OK && rv != SW_NOT_FOUND) - return rv; - - if (entry.static_en == A_FALSE) - { - rv = _modify_fdb_table_entry(dev_id, &entry, OP_TYPE_DEL, 0x0); - if (rv != SW_OK) - return rv; - } - } - } - - return SW_OK; -} -#ifndef IN_FDB_MINI -sw_error_t -adpt_hppe_fdb_transfer(a_uint32_t dev_id, fal_port_t old_port, fal_port_t new_port, - a_uint32_t fid, fal_fdb_op_t * option) -{ - a_uint32_t entry_index, cmd_id = 0; - sw_error_t rv = SW_OK; - fal_fdb_entry_t entry; - - ADPT_DEV_ID_CHECK(dev_id); - ADPT_NULL_POINT_CHECK(option); - - if (option->port_en == A_TRUE) - return SW_NOT_SUPPORTED; - - _remove_port_type(&old_port); - _remove_port_type(&new_port); - - for (entry_index = 0; entry_index < FDB_TBL_NUM; entry_index++) - { - cmd_id = entry_index % OP_CMD_ID_SIZE; - aos_mem_zero(&entry, sizeof (fal_fdb_entry_t)); - rv = _get_fdb_table_entry_by_entryindex(dev_id, &entry, entry_index, cmd_id); - - if (rv == SW_NOT_FOUND) - continue; - else if (rv == SW_OK) - { - if (option->fid_en == A_TRUE && entry.fid != fid) - continue; - if (entry.portmap_en == A_TRUE) - { - if (((entry.port.map >> old_port) & 0x1) == 1) - { - entry.port.map &= (~(0x1 << old_port)); - entry.port.map |= (0x1 << new_port); - rv = adpt_hppe_fdb_add(dev_id, &entry); - if (rv != SW_OK) - return rv; - } - } - else - { - if (entry.port.id == old_port) - { - entry.port.id = new_port; - rv = adpt_hppe_fdb_add(dev_id, &entry); - if (rv != SW_OK) - return rv; - } - } - } - else - return rv; - } - - return SW_OK; -} -#endif -sw_error_t -adpt_hppe_fdb_find(a_uint32_t dev_id, fal_fdb_entry_t * entry) -{ - sw_error_t rv; - a_uint32_t cmd_id = 0x0; - a_uint32_t entry_index = 0x0; - - _remove_port_type(&entry->port.id); - rv = _get_fdb_table_entryindex_by_entry(dev_id, entry, &entry_index, cmd_id); - if (rv != SW_OK) - return rv; - - cmd_id = entry_index % OP_CMD_ID_SIZE; - - rv = _get_fdb_table_entry_by_entryindex(dev_id, entry, entry_index, cmd_id); - _add_port_type(entry->portmap_en, &entry->port.id); - - return rv; -} - -sw_error_t -adpt_hppe_fdb_iterate(a_uint32_t dev_id, a_uint32_t * iterator, fal_fdb_entry_t * entry) -{ - sw_error_t rv; - a_uint32_t cmd_id = 0x0; - a_uint32_t entry_index = 0x0; - - ADPT_DEV_ID_CHECK(dev_id); - ADPT_NULL_POINT_CHECK(iterator); - ADPT_NULL_POINT_CHECK(entry); - - _remove_port_type(&entry->port.id); - for (entry_index = *iterator; entry_index < FDB_TBL_NUM; entry_index++) - { - cmd_id = entry_index % OP_CMD_ID_SIZE; - rv = _get_fdb_table_entry_by_entryindex(dev_id, entry, entry_index, cmd_id); - if (rv == SW_NOT_FOUND) - continue; - else if (rv == SW_OK) - break; - else - return rv; - } - - if (entry_index == FDB_TBL_NUM) - return SW_NO_MORE; - - _add_port_type(entry->portmap_en, &entry->port.id); - *iterator = entry_index + 1; - return SW_OK; -} -#ifndef IN_FDB_MINI -sw_error_t -adpt_hppe_fdb_age_time_set(a_uint32_t dev_id, a_uint32_t * time) -{ - union age_timer_u age_timer = {0}; - - ADPT_DEV_ID_CHECK(dev_id); - ADPT_NULL_POINT_CHECK(time); - - if (*time < 1 || *time > 1048575) - return SW_BAD_PARAM; - - age_timer.bf.age_val = *time; - - return hppe_age_timer_set(dev_id, &age_timer); -} - -sw_error_t -adpt_hppe_fdb_age_time_get(a_uint32_t dev_id, a_uint32_t * time) -{ - sw_error_t rv = SW_OK; - union age_timer_u age_timer = {0}; - - ADPT_DEV_ID_CHECK(dev_id); - ADPT_NULL_POINT_CHECK(time); - - rv = hppe_age_timer_get(dev_id, &age_timer); - - if( rv != SW_OK ) - return rv; - - *time = age_timer.bf.age_val; - - return SW_OK; -} -#endif -sw_error_t -adpt_hppe_fdb_extend_first(a_uint32_t dev_id, fal_fdb_op_t * option, - fal_fdb_entry_t * entry) -{ - sw_error_t rv; - - ADPT_DEV_ID_CHECK(dev_id); - ADPT_NULL_POINT_CHECK(option); - ADPT_NULL_POINT_CHECK(entry); - - _remove_port_type(&entry->port.id); - rv = _adpt_hppe_fdb_extend_first_next(dev_id, entry, option, ARL_EXTENDFIRST_ENTRY); - _add_port_type(entry->portmap_en, &entry->port.id); - - return rv; -} - -sw_error_t -adpt_hppe_fdb_extend_next(a_uint32_t dev_id, fal_fdb_op_t * option, - fal_fdb_entry_t * entry) -{ - sw_error_t rv; - - ADPT_DEV_ID_CHECK(dev_id); - ADPT_NULL_POINT_CHECK(option); - ADPT_NULL_POINT_CHECK(entry); - - _remove_port_type(&entry->port.id); - rv = _adpt_hppe_fdb_extend_first_next(dev_id, entry, option, ARL_EXTENDNEXT_ENTRY); - _add_port_type(entry->portmap_en, &entry->port.id); - - return rv; -} - -sw_error_t -adpt_hppe_fdb_learn_ctrl_set(a_uint32_t dev_id, a_bool_t enable) -{ - sw_error_t rv = SW_OK; - union l2_global_conf_u l2_global_conf = {0}; - - ADPT_DEV_ID_CHECK(dev_id); - - rv = hppe_l2_global_conf_get(dev_id, &l2_global_conf); - - if( rv != SW_OK ) - return rv; - - l2_global_conf.bf.lrn_en = enable; - - return hppe_l2_global_conf_set(dev_id, &l2_global_conf); -} -#ifndef IN_FDB_MINI -sw_error_t -adpt_hppe_fdb_learn_ctrl_get(a_uint32_t dev_id, a_bool_t * enable) -{ - sw_error_t rv = SW_OK; - union l2_global_conf_u l2_global_conf = {0}; - - ADPT_DEV_ID_CHECK(dev_id); - ADPT_NULL_POINT_CHECK(enable); - - - rv = hppe_l2_global_conf_get(dev_id, &l2_global_conf); - - if( rv != SW_OK ) - return rv; - - *enable = l2_global_conf.bf.lrn_en; - - return SW_OK; -} - -sw_error_t -adpt_hppe_fdb_port_maclimit_ctrl_set(a_uint32_t dev_id, fal_port_t port_id, fal_maclimit_ctrl_t * maclimit_ctrl) -{ - sw_error_t rv = SW_OK; - union port_lrn_limit_ctrl_u port_lrn_limit_ctrl = {0}; - - ADPT_DEV_ID_CHECK(dev_id); - - rv = hppe_port_lrn_limit_ctrl_get(dev_id, port_id, &port_lrn_limit_ctrl); - - if( rv != SW_OK ) - return rv; - - port_lrn_limit_ctrl.bf.lrn_lmt_en = maclimit_ctrl->enable; - port_lrn_limit_ctrl.bf.lrn_lmt_cnt = maclimit_ctrl->limit_num; - port_lrn_limit_ctrl.bf.lrn_lmt_exceed_fwd = maclimit_ctrl->action; - - return hppe_port_lrn_limit_ctrl_set(dev_id, port_id, &port_lrn_limit_ctrl); -} - -sw_error_t -adpt_hppe_fdb_port_maclimit_ctrl_get(a_uint32_t dev_id, fal_port_t port_id, fal_maclimit_ctrl_t * maclimit_ctrl) -{ - sw_error_t rv = SW_OK; - union port_lrn_limit_ctrl_u port_lrn_limit_ctrl = {0}; - - ADPT_DEV_ID_CHECK(dev_id); - ADPT_NULL_POINT_CHECK(maclimit_ctrl); - - rv = hppe_port_lrn_limit_ctrl_get(dev_id, port_id, &port_lrn_limit_ctrl); - - if( rv != SW_OK ) - return rv; - - maclimit_ctrl->enable = port_lrn_limit_ctrl.bf.lrn_lmt_en; - maclimit_ctrl->limit_num = port_lrn_limit_ctrl.bf.lrn_lmt_cnt; - maclimit_ctrl->action = port_lrn_limit_ctrl.bf.lrn_lmt_exceed_fwd; - - return SW_OK; -} - -sw_error_t -adpt_hppe_port_fdb_learn_limit_set(a_uint32_t dev_id, fal_port_t port_id, - a_bool_t enable, a_uint32_t cnt) -{ - sw_error_t rv = SW_OK; - fal_maclimit_ctrl_t maclimit_ctrl; - - ADPT_DEV_ID_CHECK(dev_id); - - rv = adpt_hppe_fdb_port_maclimit_ctrl_get(dev_id, port_id, &maclimit_ctrl); - if( rv != SW_OK ) - return rv; - - maclimit_ctrl.enable = enable; - maclimit_ctrl.limit_num = cnt; - - return adpt_hppe_fdb_port_maclimit_ctrl_set(dev_id, port_id, &maclimit_ctrl); -} - -sw_error_t -adpt_hppe_port_fdb_learn_limit_get(a_uint32_t dev_id, fal_port_t port_id, - a_bool_t * enable, a_uint32_t * cnt) -{ - sw_error_t rv = SW_OK; - fal_maclimit_ctrl_t maclimit_ctrl; - - ADPT_DEV_ID_CHECK(dev_id); - ADPT_NULL_POINT_CHECK(enable); - ADPT_NULL_POINT_CHECK(cnt); - - rv = adpt_hppe_fdb_port_maclimit_ctrl_get(dev_id, port_id, &maclimit_ctrl); - if( rv != SW_OK ) - return rv; - - *enable = maclimit_ctrl.enable; - *cnt = maclimit_ctrl.limit_num; - - return SW_OK; -} - -sw_error_t -adpt_hppe_fdb_port_add(a_uint32_t dev_id, a_uint32_t fid, fal_mac_addr_t * addr, fal_port_t port_id) -{ - sw_error_t rv = SW_OK; - fal_fdb_entry_t entry; - int i, cmd_id = 0x0, entry_index = 0x0, id; - - ADPT_DEV_ID_CHECK(dev_id); - ADPT_NULL_POINT_CHECK(addr); - - _remove_port_type(&port_id); - - aos_mem_zero(&entry, sizeof (fal_fdb_entry_t)); - - entry.fid = fid; - for (i = 0; i < 6; i++) - entry.addr.uc[i] = addr->uc[i]; - - rv = _get_fdb_table_entryindex_by_entry(dev_id, &entry, &entry_index, cmd_id); - if (rv != SW_OK) - return rv; - - cmd_id = entry_index % OP_CMD_ID_SIZE; - rv = _get_fdb_table_entry_by_entryindex(dev_id, &entry, entry_index, cmd_id); - if (rv != SW_OK) - return rv; - - if (entry.portmap_en == A_TRUE) - { - if (port_id >= 12) - return SW_FAIL; - entry.port.map |= (0x1 << port_id); - } - else - { - if (port_id >= 12 || entry.port.id >= 12) - return SW_FAIL; - entry.portmap_en = A_TRUE; - id = entry.port.id; - entry.port.map = 0; - entry.port.map |= (0x1 << id); - entry.port.map |= (0x1 << port_id); - } - - return adpt_hppe_fdb_add(dev_id, &entry); -} - -sw_error_t -adpt_hppe_fdb_port_del(a_uint32_t dev_id, a_uint32_t fid, fal_mac_addr_t * addr, fal_port_t port_id) -{ - sw_error_t rv = SW_OK; - fal_fdb_entry_t entry; - int i, cmd_id = 0x0, entry_index = 0x0, id; - - ADPT_DEV_ID_CHECK(dev_id); - ADPT_NULL_POINT_CHECK(addr); - - _remove_port_type(&port_id); - - aos_mem_zero(&entry, sizeof (fal_fdb_entry_t)); - - entry.fid = fid; - for (i = 0; i < 6; i++) - entry.addr.uc[i] = addr->uc[i]; - - rv = _get_fdb_table_entryindex_by_entry(dev_id, &entry, &entry_index, cmd_id); - if (rv != SW_OK) - return rv; - - cmd_id = entry_index % OP_CMD_ID_SIZE; - rv = _get_fdb_table_entry_by_entryindex(dev_id, &entry, entry_index, cmd_id); - if (rv != SW_OK) - return rv; - - if (entry.portmap_en == A_TRUE) - { - if (((entry.port.map >> port_id) & 0x1) == 1) - { - id = entry.port.map & (~(0x1 << port_id)); - if (id == 0) - { - rv = _modify_fdb_table_entry(dev_id, &entry, OP_TYPE_DEL, 0x0); - } - else - { - entry.port.map &= (~(0x1 << port_id)); - rv = adpt_hppe_fdb_add(dev_id, &entry); - } - } - } - else - { - if (entry.port.id == port_id) - rv = _modify_fdb_table_entry(dev_id, &entry, OP_TYPE_DEL, 0x0); - } - - return rv; -} -#endif -sw_error_t -adpt_hppe_fdb_port_learn_set(a_uint32_t dev_id, fal_port_t port_id, a_bool_t enable) -{ - sw_error_t rv = SW_OK; - union port_bridge_ctrl_u port_bridge_ctrl = {0}; - - ADPT_DEV_ID_CHECK(dev_id); - - rv = hppe_port_bridge_ctrl_get(dev_id, port_id, &port_bridge_ctrl); - - if( rv != SW_OK ) - return rv; - - port_bridge_ctrl.bf.new_addr_lrn_en = enable; - port_bridge_ctrl.bf.station_move_lrn_en = enable; - - return hppe_port_bridge_ctrl_set(dev_id, port_id, &port_bridge_ctrl); -} -#ifndef IN_FDB_MINI -sw_error_t -adpt_hppe_fdb_port_learn_get(a_uint32_t dev_id, fal_port_t port_id, a_bool_t *enable) -{ - sw_error_t rv = SW_OK; - union port_bridge_ctrl_u port_bridge_ctrl = {0}; - - ADPT_DEV_ID_CHECK(dev_id); - ADPT_NULL_POINT_CHECK(enable); - - rv = hppe_port_bridge_ctrl_get(dev_id, port_id, &port_bridge_ctrl); - - if( rv != SW_OK ) - return rv; - - *enable = port_bridge_ctrl.bf.new_addr_lrn_en; - - return SW_OK; -} -#endif -sw_error_t -adpt_hppe_fdb_port_newaddr_lrn_set(a_uint32_t dev_id, fal_port_t port_id, a_bool_t enable, fal_fwd_cmd_t cmd) -{ - sw_error_t rv = SW_OK; - union port_bridge_ctrl_u port_bridge_ctrl; - - memset(&port_bridge_ctrl, 0, sizeof(port_bridge_ctrl)); - ADPT_DEV_ID_CHECK(dev_id); - - rv = hppe_port_bridge_ctrl_get(dev_id, port_id, &port_bridge_ctrl); - - if( rv != SW_OK ) - return rv; - - port_bridge_ctrl.bf.new_addr_lrn_en = enable; - port_bridge_ctrl.bf.new_addr_fwd_cmd = cmd; - - return hppe_port_bridge_ctrl_set(dev_id, port_id, &port_bridge_ctrl); -} -#ifndef IN_FDB_MINI -sw_error_t -adpt_hppe_fdb_port_newaddr_lrn_get(a_uint32_t dev_id, fal_port_t port_id, a_bool_t *enable, fal_fwd_cmd_t *cmd) -{ - sw_error_t rv = SW_OK; - union port_bridge_ctrl_u port_bridge_ctrl; - - memset(&port_bridge_ctrl, 0, sizeof(port_bridge_ctrl)); - ADPT_DEV_ID_CHECK(dev_id); - ADPT_NULL_POINT_CHECK(enable); - ADPT_NULL_POINT_CHECK(cmd); - - rv = hppe_port_bridge_ctrl_get(dev_id, port_id, &port_bridge_ctrl); - - if( rv != SW_OK ) - return rv; - - *enable = port_bridge_ctrl.bf.new_addr_lrn_en; - *cmd = port_bridge_ctrl.bf.new_addr_fwd_cmd; - - return SW_OK; -} -#endif -sw_error_t -adpt_hppe_fdb_port_stamove_set(a_uint32_t dev_id, fal_port_t port_id, a_bool_t enable, fal_fwd_cmd_t cmd) -{ - sw_error_t rv = SW_OK; - union port_bridge_ctrl_u port_bridge_ctrl; - - memset(&port_bridge_ctrl, 0, sizeof(port_bridge_ctrl)); - ADPT_DEV_ID_CHECK(dev_id); - - rv = hppe_port_bridge_ctrl_get(dev_id, port_id, &port_bridge_ctrl); - - if( rv != SW_OK ) - return rv; - - port_bridge_ctrl.bf.station_move_lrn_en = enable; - port_bridge_ctrl.bf.station_move_fwd_cmd = cmd; - - return hppe_port_bridge_ctrl_set(dev_id, port_id, &port_bridge_ctrl); -} -#ifndef IN_FDB_MINI -sw_error_t -adpt_hppe_fdb_port_stamove_get(a_uint32_t dev_id, fal_port_t port_id, a_bool_t *enable, fal_fwd_cmd_t *cmd) -{ - sw_error_t rv = SW_OK; - union port_bridge_ctrl_u port_bridge_ctrl; - - memset(&port_bridge_ctrl, 0, sizeof(port_bridge_ctrl)); - ADPT_DEV_ID_CHECK(dev_id); - ADPT_NULL_POINT_CHECK(enable); - ADPT_NULL_POINT_CHECK(cmd); - - rv = hppe_port_bridge_ctrl_get(dev_id, port_id, &port_bridge_ctrl); - - if( rv != SW_OK ) - return rv; - - *enable = port_bridge_ctrl.bf.station_move_lrn_en; - *cmd = port_bridge_ctrl.bf.station_move_fwd_cmd; - - return SW_OK; -} - -sw_error_t -adpt_hppe_port_fdb_learn_counter_get(a_uint32_t dev_id, fal_port_t port_id, - a_uint32_t * cnt) -{ - sw_error_t rv = SW_OK; - union port_lrn_limit_counter_u port_lrn_limit_counter = {0}; - - ADPT_DEV_ID_CHECK(dev_id); - ADPT_NULL_POINT_CHECK(cnt); - - rv = hppe_port_lrn_limit_counter_get(dev_id, port_id, &port_lrn_limit_counter); - - if( rv != SW_OK ) - return rv; - - *cnt = port_lrn_limit_counter.bf.lrn_cnt; - - return SW_OK; -} - -sw_error_t -adpt_hppe_port_fdb_learn_exceed_cmd_set(a_uint32_t dev_id, fal_port_t port_id, - fal_fwd_cmd_t cmd) -{ - sw_error_t rv = SW_OK; - fal_maclimit_ctrl_t maclimit_ctrl; - - ADPT_DEV_ID_CHECK(dev_id); - - rv = adpt_hppe_fdb_port_maclimit_ctrl_get(dev_id, port_id, &maclimit_ctrl); - if( rv != SW_OK ) - return rv; - - maclimit_ctrl.action = cmd; - - return adpt_hppe_fdb_port_maclimit_ctrl_set(dev_id, port_id, &maclimit_ctrl); -} - -sw_error_t -adpt_hppe_port_fdb_learn_exceed_cmd_get(a_uint32_t dev_id, fal_port_t port_id, - fal_fwd_cmd_t * cmd) -{ - sw_error_t rv = SW_OK; - fal_maclimit_ctrl_t maclimit_ctrl; - - ADPT_DEV_ID_CHECK(dev_id); - ADPT_NULL_POINT_CHECK(cmd); - - rv = adpt_hppe_fdb_port_maclimit_ctrl_get(dev_id, port_id, &maclimit_ctrl); - if( rv != SW_OK ) - return rv; - - *cmd = maclimit_ctrl.action; - - return SW_OK; -} -#endif -sw_error_t -adpt_hppe_fdb_age_ctrl_set(a_uint32_t dev_id, a_bool_t enable) -{ - sw_error_t rv = SW_OK; - union l2_global_conf_u l2_global_conf = {0}; - - ADPT_DEV_ID_CHECK(dev_id); - - rv = hppe_l2_global_conf_get(dev_id, &l2_global_conf); - - if( rv != SW_OK ) - return rv; - - l2_global_conf.bf.age_en = enable; - - return hppe_l2_global_conf_set(dev_id, &l2_global_conf); -} -#ifndef IN_FDB_MINI -sw_error_t -adpt_hppe_fdb_age_ctrl_get(a_uint32_t dev_id, a_bool_t * enable) -{ - sw_error_t rv = SW_OK; - union l2_global_conf_u l2_global_conf = {0}; - - ADPT_DEV_ID_CHECK(dev_id); - ADPT_NULL_POINT_CHECK(enable); - - rv = hppe_l2_global_conf_get(dev_id, &l2_global_conf); - - if( rv != SW_OK ) - return rv; - - *enable = l2_global_conf.bf.age_en; - - return SW_OK; -} -#endif -sw_error_t -adpt_hppe_fdb_del_by_fid(a_uint32_t dev_id, a_uint16_t fid, a_uint32_t flag) -{ - a_uint32_t entry_index, cmd_id = 0; - sw_error_t rv = SW_OK; - fal_fdb_entry_t entry; - - ADPT_DEV_ID_CHECK(dev_id); - - for (entry_index = 0; entry_index < FDB_TBL_NUM; entry_index++) - { - cmd_id = entry_index % OP_CMD_ID_SIZE; - aos_mem_zero(&entry, sizeof (fal_fdb_entry_t)); - rv = _get_fdb_table_entry_by_entryindex(dev_id, &entry, entry_index, cmd_id); - - if (rv == SW_NOT_FOUND) - { - continue; - } - else if (rv == SW_OK) - { - if (entry.fid == fid && - ((!flag && entry.static_en == A_FALSE) || (flag & FAL_FDB_DEL_STATIC))) - { - rv = _modify_fdb_table_entry(dev_id, &entry, OP_TYPE_DEL, 0x0); - if (rv != SW_OK) - { - return rv; - } - } - } - else - { - return rv; - } - } - - return SW_OK; -} - -void adpt_hppe_fdb_func_bitmap_init(a_uint32_t dev_id) -{ - adpt_api_t *p_adpt_api = NULL; - - p_adpt_api = adpt_api_ptr_get(dev_id); - - if(p_adpt_api == NULL) - return; - - p_adpt_api->adpt_fdb_func_bitmap[0] = ((1 << FUNC_FDB_ENTRY_ADD) | - (1 << FUNC_FDB_ENTRY_FLUSH) | - (1 << FUNC_FDB_ENTRY_DEL_BYPORT) | - (1 << FUNC_FDB_ENTRY_DEL_BYMAC) | - (1 << FUNC_FDB_ENTRY_GETFIRST) | - (1 << FUNC_FDB_ENTRY_GETNEXT) | - (1 << FUNC_FDB_ENTRY_SEARCH) | - (1 << FUNC_FDB_PORT_LEARN_SET) | - (1 << FUNC_FDB_PORT_LEARN_GET) | - (1 << FUNC_FDB_PORT_LEARNING_CTRL_SET) | - (1 << FUNC_FDB_PORT_LEARNING_CTRL_GET) | - (1 << FUNC_FDB_PORT_STAMOVE_CTRL_SET) | - (1 << FUNC_FDB_PORT_STAMOVE_CTRL_GET) | - (1 << FUNC_FDB_AGING_CTRL_SET) | - (1 << FUNC_FDB_AGING_CTRL_GET) | - (1 << FUNC_FDB_LEARNING_CTRL_SET) | - (1 << FUNC_FDB_LEARNING_CTRL_GET) | - (1 << FUNC_FDB_AGING_TIME_SET) | - (1 << FUNC_FDB_AGING_TIME_GET) | - (1 << FUNC_FDB_ENTRY_GETNEXT_BYINDEX) | - (1 << FUNC_FDB_ENTRY_EXTEND_GETNEXT) | - (1 << FUNC_FDB_ENTRY_EXTEND_GETFIRST) | - (1 << FUNC_FDB_ENTRY_UPDATE_BYPORT) | - (1 << FUNC_PORT_FDB_LEARN_LIMIT_SET) | - (1 << FUNC_PORT_FDB_LEARN_LIMIT_GET) | - (1 << FUNC_PORT_FDB_LEARN_EXCEED_CMD_SET) | - (1 << FUNC_PORT_FDB_LEARN_EXCEED_CMD_GET) | - (1 << FUNC_FDB_PORT_LEARNED_MAC_COUNTER_GET) | - (1 << FUNC_FDB_PORT_ADD) | - (1 << FUNC_FDB_PORT_DEL) | - (1 << FUNC_FDB_PORT_MACLIMIT_CTRL_SET) | - (1 << FUNC_FDB_PORT_MACLIMIT_CTRL_GET)); - p_adpt_api->adpt_fdb_func_bitmap[1] = ((1 << (FUNC_FDB_DEL_BY_FID % 32))); - - return; -} - -static void adpt_hppe_fdb_func_unregister(a_uint32_t dev_id, adpt_api_t *p_adpt_api) -{ - if(p_adpt_api == NULL) - return; - - p_adpt_api->adpt_fdb_first = NULL; - p_adpt_api->adpt_fdb_next = NULL; - p_adpt_api->adpt_fdb_add = NULL; - p_adpt_api->adpt_fdb_del_by_port = NULL; - p_adpt_api->adpt_fdb_del_by_mac = NULL; - p_adpt_api->adpt_fdb_del_all = NULL; - p_adpt_api->adpt_fdb_transfer = NULL; - p_adpt_api->adpt_fdb_find = NULL; - p_adpt_api->adpt_fdb_iterate = NULL; - p_adpt_api->adpt_fdb_age_time_set = NULL; - p_adpt_api->adpt_fdb_age_time_get = NULL; - p_adpt_api->adpt_fdb_extend_first = NULL; - p_adpt_api->adpt_fdb_extend_next = NULL; - p_adpt_api->adpt_fdb_learn_ctrl_set = NULL; - p_adpt_api->adpt_fdb_learn_ctrl_get = NULL; - p_adpt_api->adpt_port_fdb_learn_limit_set = NULL; - p_adpt_api->adpt_port_fdb_learn_limit_get = NULL; - p_adpt_api->adpt_fdb_port_add = NULL; - p_adpt_api->adpt_fdb_port_del = NULL; - p_adpt_api->adpt_fdb_port_learn_set = NULL; - p_adpt_api->adpt_fdb_port_learn_get = NULL; - p_adpt_api->adpt_fdb_port_newaddr_lrn_set = NULL; - p_adpt_api->adpt_fdb_port_newaddr_lrn_get = NULL; - p_adpt_api->adpt_fdb_port_stamove_set = NULL; - p_adpt_api->adpt_fdb_port_stamove_get = NULL; - p_adpt_api->adpt_port_fdb_learn_counter_get = NULL; - p_adpt_api->adpt_port_fdb_learn_exceed_cmd_set = NULL; - p_adpt_api->adpt_port_fdb_learn_exceed_cmd_get = NULL; - p_adpt_api->adpt_fdb_age_ctrl_set = NULL; - p_adpt_api->adpt_fdb_age_ctrl_get = NULL; - p_adpt_api->adpt_fdb_port_maclimit_ctrl_set = NULL; - p_adpt_api->adpt_fdb_port_maclimit_ctrl_get = NULL; - p_adpt_api->adpt_fdb_del_by_fid = NULL; - - return; -} - -sw_error_t adpt_hppe_fdb_init(a_uint32_t dev_id) -{ - adpt_api_t *p_adpt_api = NULL; - - p_adpt_api = adpt_api_ptr_get(dev_id); - - if(p_adpt_api == NULL) - return SW_FAIL; - - adpt_hppe_fdb_func_unregister(dev_id, p_adpt_api); - - if (p_adpt_api->adpt_fdb_func_bitmap[0] & (1 << FUNC_FDB_ENTRY_GETFIRST)) - p_adpt_api->adpt_fdb_first = adpt_hppe_fdb_first; -#ifndef IN_FDB_MINI - if (p_adpt_api->adpt_fdb_func_bitmap[0] & (1 << FUNC_FDB_ENTRY_GETNEXT)) - p_adpt_api->adpt_fdb_next = adpt_hppe_fdb_next; -#endif - if (p_adpt_api->adpt_fdb_func_bitmap[0] & (1 << FUNC_FDB_ENTRY_ADD)) - p_adpt_api->adpt_fdb_add = adpt_hppe_fdb_add; - if (p_adpt_api->adpt_fdb_func_bitmap[0] & (1 << FUNC_FDB_ENTRY_DEL_BYPORT)) - p_adpt_api->adpt_fdb_del_by_port = adpt_hppe_fdb_del_by_port; - if (p_adpt_api->adpt_fdb_func_bitmap[0] & (1 << FUNC_FDB_ENTRY_DEL_BYMAC)) - p_adpt_api->adpt_fdb_del_by_mac = adpt_hppe_fdb_del_by_mac; - if (p_adpt_api->adpt_fdb_func_bitmap[0] & (1 << FUNC_FDB_ENTRY_FLUSH)) - p_adpt_api->adpt_fdb_del_all = adpt_hppe_fdb_del_all; -#ifndef IN_FDB_MINI - if (p_adpt_api->adpt_fdb_func_bitmap[0] & (1 << FUNC_FDB_ENTRY_UPDATE_BYPORT)) - p_adpt_api->adpt_fdb_transfer = adpt_hppe_fdb_transfer; -#endif - if (p_adpt_api->adpt_fdb_func_bitmap[0] & (1 << FUNC_FDB_ENTRY_SEARCH)) - p_adpt_api->adpt_fdb_find = adpt_hppe_fdb_find; - if (p_adpt_api->adpt_fdb_func_bitmap[0] & (1 << FUNC_FDB_ENTRY_GETNEXT_BYINDEX)) - p_adpt_api->adpt_fdb_iterate = adpt_hppe_fdb_iterate; -#ifndef IN_FDB_MINI - if (p_adpt_api->adpt_fdb_func_bitmap[0] & (1 << FUNC_FDB_AGING_TIME_SET)) - p_adpt_api->adpt_fdb_age_time_set = adpt_hppe_fdb_age_time_set; - if (p_adpt_api->adpt_fdb_func_bitmap[0] & (1 << FUNC_FDB_AGING_TIME_GET)) - p_adpt_api->adpt_fdb_age_time_get = adpt_hppe_fdb_age_time_get; -#endif - if (p_adpt_api->adpt_fdb_func_bitmap[0] & (1 << FUNC_FDB_ENTRY_EXTEND_GETFIRST)) - p_adpt_api->adpt_fdb_extend_first = adpt_hppe_fdb_extend_first; - if (p_adpt_api->adpt_fdb_func_bitmap[0] & (1 << FUNC_FDB_ENTRY_EXTEND_GETNEXT)) - p_adpt_api->adpt_fdb_extend_next = adpt_hppe_fdb_extend_next; - if (p_adpt_api->adpt_fdb_func_bitmap[0] & (1 << FUNC_FDB_LEARNING_CTRL_SET)) - p_adpt_api->adpt_fdb_learn_ctrl_set = adpt_hppe_fdb_learn_ctrl_set; -#ifndef IN_FDB_MINI - if (p_adpt_api->adpt_fdb_func_bitmap[0] & (1 << FUNC_FDB_LEARNING_CTRL_GET)) - p_adpt_api->adpt_fdb_learn_ctrl_get = adpt_hppe_fdb_learn_ctrl_get; - if (p_adpt_api->adpt_fdb_func_bitmap[0] & (1 << FUNC_PORT_FDB_LEARN_LIMIT_SET)) - p_adpt_api->adpt_port_fdb_learn_limit_set = adpt_hppe_port_fdb_learn_limit_set; - if (p_adpt_api->adpt_fdb_func_bitmap[0] & (1 << FUNC_PORT_FDB_LEARN_LIMIT_GET)) - p_adpt_api->adpt_port_fdb_learn_limit_get = adpt_hppe_port_fdb_learn_limit_get; - if (p_adpt_api->adpt_fdb_func_bitmap[0] & (1 << FUNC_FDB_PORT_ADD)) - p_adpt_api->adpt_fdb_port_add = adpt_hppe_fdb_port_add; - if (p_adpt_api->adpt_fdb_func_bitmap[0] & (1 << FUNC_FDB_PORT_DEL)) - p_adpt_api->adpt_fdb_port_del = adpt_hppe_fdb_port_del; -#endif - if (p_adpt_api->adpt_fdb_func_bitmap[0] & (1 << FUNC_FDB_PORT_LEARN_SET)) - p_adpt_api->adpt_fdb_port_learn_set = adpt_hppe_fdb_port_learn_set; -#ifndef IN_FDB_MINI - if (p_adpt_api->adpt_fdb_func_bitmap[0] & (1 << FUNC_FDB_PORT_LEARN_GET)) - p_adpt_api->adpt_fdb_port_learn_get = adpt_hppe_fdb_port_learn_get; -#endif - if (p_adpt_api->adpt_fdb_func_bitmap[0] & (1 << FUNC_FDB_PORT_LEARNING_CTRL_SET)) - p_adpt_api->adpt_fdb_port_newaddr_lrn_set = adpt_hppe_fdb_port_newaddr_lrn_set; -#ifndef IN_FDB_MINI - if (p_adpt_api->adpt_fdb_func_bitmap[0] & (1 << FUNC_FDB_PORT_LEARNING_CTRL_GET)) - p_adpt_api->adpt_fdb_port_newaddr_lrn_get = adpt_hppe_fdb_port_newaddr_lrn_get; -#endif - if (p_adpt_api->adpt_fdb_func_bitmap[0] & (1 << FUNC_FDB_PORT_STAMOVE_CTRL_SET)) - p_adpt_api->adpt_fdb_port_stamove_set = adpt_hppe_fdb_port_stamove_set; -#ifndef IN_FDB_MINI - if (p_adpt_api->adpt_fdb_func_bitmap[0] & (1 << FUNC_FDB_PORT_STAMOVE_CTRL_GET)) - p_adpt_api->adpt_fdb_port_stamove_get = adpt_hppe_fdb_port_stamove_get; - if (p_adpt_api->adpt_fdb_func_bitmap[0] & (1 << FUNC_FDB_PORT_LEARNED_MAC_COUNTER_GET)) - p_adpt_api->adpt_port_fdb_learn_counter_get = adpt_hppe_port_fdb_learn_counter_get; - if (p_adpt_api->adpt_fdb_func_bitmap[0] & (1 << FUNC_PORT_FDB_LEARN_EXCEED_CMD_SET)) - p_adpt_api->adpt_port_fdb_learn_exceed_cmd_set = adpt_hppe_port_fdb_learn_exceed_cmd_set; - if (p_adpt_api->adpt_fdb_func_bitmap[0] & (1 << FUNC_PORT_FDB_LEARN_EXCEED_CMD_GET)) - p_adpt_api->adpt_port_fdb_learn_exceed_cmd_get = adpt_hppe_port_fdb_learn_exceed_cmd_get; -#endif - if (p_adpt_api->adpt_fdb_func_bitmap[0] & (1 << FUNC_FDB_AGING_CTRL_SET)) - p_adpt_api->adpt_fdb_age_ctrl_set = adpt_hppe_fdb_age_ctrl_set; -#ifndef IN_FDB_MINI - if (p_adpt_api->adpt_fdb_func_bitmap[0] & (1 << FUNC_FDB_AGING_CTRL_GET)) - p_adpt_api->adpt_fdb_age_ctrl_get = adpt_hppe_fdb_age_ctrl_get; - if (p_adpt_api->adpt_fdb_func_bitmap[0] & (1 << FUNC_FDB_PORT_MACLIMIT_CTRL_SET)) - p_adpt_api->adpt_fdb_port_maclimit_ctrl_set = adpt_hppe_fdb_port_maclimit_ctrl_set; - if (p_adpt_api->adpt_fdb_func_bitmap[0] & (1 << FUNC_FDB_PORT_MACLIMIT_CTRL_GET)) - p_adpt_api->adpt_fdb_port_maclimit_ctrl_get = adpt_hppe_fdb_port_maclimit_ctrl_get; -#endif - if (p_adpt_api->adpt_fdb_func_bitmap[1] & (1 << (FUNC_FDB_DEL_BY_FID % 32))) - p_adpt_api->adpt_fdb_del_by_fid = adpt_hppe_fdb_del_by_fid; - - aos_lock_init(&hppe_fdb_lock); - - return SW_OK; -} - -/** - * @} - */ - diff --git a/feeds/ipq807x/qca-ssdk/src/src/adpt/hppe/adpt_hppe_flow.c b/feeds/ipq807x/qca-ssdk/src/src/adpt/hppe/adpt_hppe_flow.c deleted file mode 100755 index 9302a4cb0..000000000 --- a/feeds/ipq807x/qca-ssdk/src/src/adpt/hppe/adpt_hppe_flow.c +++ /dev/null @@ -1,1850 +0,0 @@ -/* - * Copyright (c) 2016-2017, 2019, The Linux Foundation. All rights reserved. - * Permission to use, copy, modify, and/or distribute this software for - * any purpose with or without fee is hereby granted, provided that the - * above copyright notice and this permission notice appear in all copies. - * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES - * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR - * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES - * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN - * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT - * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. - */ - - -/** - * @defgroup - * @{ - */ -#include "sw.h" -#include "fal_flow.h" -#include "hppe_ip_reg.h" -#include "hppe_ip.h" -#include "hppe_flow_reg.h" -#include "hppe_flow.h" -#include "adpt_hppe.h" -#include "adpt.h" - -#if defined(CPPE) -#include "adpt_cppe_flow.h" -#endif - - -#define FLOW_ENTRY_TYPE_IPV4 0 -#define FLOW_ENTRY_TYPE_IPV6 1 -#define FLOW_TUPLE_TYPE_3 0 - -#ifndef IN_FLOW_MINI -sw_error_t -adpt_hppe_ip_flow_host_data_rd_add(a_uint32_t dev_id, fal_host_entry_t * host_entry) - -{ - a_uint8_t mode = 0, type = 0; - sw_error_t rv = SW_OK; - ADPT_DEV_ID_CHECK(dev_id); - ADPT_NULL_POINT_CHECK(host_entry); - - mode = host_entry->flags >> 24; - type = host_entry->flags & 0xff; - - if ((type & FAL_IP_IP4_ADDR) == FAL_IP_IP4_ADDR) { - union host_tbl_u entry; - entry.bf.valid= host_entry->status; - entry.bf.key_type = 0; - entry.bf.fwd_cmd = host_entry->action; - entry.bf.syn_toggle = host_entry->syn_toggle; - entry.bf.dst_info = host_entry->port_id; - entry.bf.lan_wan = host_entry->lan_wan; - entry.bf.ip_addr = host_entry->ip4_addr; - rv = hppe_flow_host_ipv4_data_rd_add(dev_id, (a_uint32_t)mode, &host_entry->entry_id, &entry); - } else if ((type & FAL_IP_IP6_ADDR) == FAL_IP_IP6_ADDR) { - union host_ipv6_tbl_u entry; - entry.bf.valid= host_entry->status; - entry.bf.key_type = 2; - entry.bf.fwd_cmd = host_entry->action; - entry.bf.syn_toggle = host_entry->syn_toggle; - entry.bf.dst_info = host_entry->port_id; - entry.bf.lan_wan = host_entry->lan_wan; - entry.bf.ipv6_addr_0 = host_entry->ip6_addr.ul[3]; - entry.bf.ipv6_addr_1 = host_entry->ip6_addr.ul[3] >> 10 | \ - host_entry->ip6_addr.ul[2] << 22; - entry.bf.ipv6_addr_2 = host_entry->ip6_addr.ul[2] >> 10 | \ - host_entry->ip6_addr.ul[1] << 22; - entry.bf.ipv6_addr_3 = host_entry->ip6_addr.ul[1] >> 10 | \ - host_entry->ip6_addr.ul[0] << 22; - entry.bf.ipv6_addr_4 = host_entry->ip6_addr.ul[0] >> 10; - rv = hppe_flow_host_ipv6_data_rd_add(dev_id, (a_uint32_t)mode, &host_entry->entry_id, &entry); - } - - return SW_OK; -} - -sw_error_t -adpt_hppe_ip_flow_host_data_add(a_uint32_t dev_id, fal_host_entry_t * host_entry) -{ - a_uint8_t mode = 0, type = 0; - sw_error_t rv = SW_OK; - ADPT_DEV_ID_CHECK(dev_id); - ADPT_NULL_POINT_CHECK(host_entry); - - mode = host_entry->flags >> 24; - type = host_entry->flags & 0xff; - - if ((type & FAL_IP_IP4_ADDR) == FAL_IP_IP4_ADDR) { - union host_tbl_u entry; - entry.bf.valid= host_entry->status; - entry.bf.key_type = 0; - entry.bf.fwd_cmd = host_entry->action; - entry.bf.syn_toggle = host_entry->syn_toggle; - entry.bf.dst_info = host_entry->port_id; - entry.bf.lan_wan = host_entry->lan_wan; - entry.bf.ip_addr = host_entry->ip4_addr; - rv = hppe_flow_host_ipv4_data_add(dev_id, (a_uint32_t)mode, &host_entry->entry_id, &entry); - } else if ((type & FAL_IP_IP6_ADDR) == FAL_IP_IP6_ADDR) { - union host_ipv6_tbl_u entry; - entry.bf.valid= host_entry->status; - entry.bf.key_type = 2; - entry.bf.fwd_cmd = host_entry->action; - entry.bf.syn_toggle = host_entry->syn_toggle; - entry.bf.dst_info = host_entry->port_id; - entry.bf.lan_wan = host_entry->lan_wan; - entry.bf.ipv6_addr_0 = host_entry->ip6_addr.ul[3]; - entry.bf.ipv6_addr_1 = host_entry->ip6_addr.ul[3] >> 10 | \ - host_entry->ip6_addr.ul[2] << 22; - entry.bf.ipv6_addr_2 = host_entry->ip6_addr.ul[2] >> 10 | \ - host_entry->ip6_addr.ul[1] << 22; - entry.bf.ipv6_addr_3 = host_entry->ip6_addr.ul[1] >> 10 | \ - host_entry->ip6_addr.ul[0] << 22; - entry.bf.ipv6_addr_4 = host_entry->ip6_addr.ul[0] >> 10; - rv = hppe_flow_host_ipv6_data_add(dev_id, (a_uint32_t)mode, &host_entry->entry_id, &entry); - } - - return SW_OK; -} - -sw_error_t -adpt_hppe_ip_flow_host_data_get(a_uint32_t dev_id, a_uint32_t get_mode, - fal_host_entry_t *host_entry) -{ - a_uint8_t mode = 0, type = 0; - sw_error_t rv = SW_OK; - ADPT_DEV_ID_CHECK(dev_id); - ADPT_NULL_POINT_CHECK(host_entry); - - mode = host_entry->flags >> 24; - type = host_entry->flags & 0xff; - - if (get_mode & FAL_IP_ENTRY_ID_EN) - mode = 1; - else if (get_mode & FAL_IP_ENTRY_IPADDR_EN) - mode = 0; - - if ((type & FAL_IP_IP4_ADDR) == FAL_IP_IP4_ADDR) { - union host_tbl_u entry; - entry.bf.key_type = 0; - entry.bf.ip_addr = host_entry->ip4_addr; - rv = hppe_flow_host_ipv4_data_get(dev_id, (a_uint32_t)mode, &host_entry->entry_id, &entry); - host_entry->ip4_addr = entry.bf.ip_addr; - host_entry->lan_wan = entry.bf.lan_wan; - host_entry->port_id = entry.bf.dst_info; - host_entry->syn_toggle = entry.bf.syn_toggle; - host_entry->action = entry.bf.fwd_cmd; - host_entry->status = entry.bf.valid; - } else if ((type & FAL_IP_IP6_ADDR) == FAL_IP_IP6_ADDR) { - union host_ipv6_tbl_u entry; - entry.bf.key_type = 2; - entry.bf.ipv6_addr_0 = host_entry->ip6_addr.ul[3]; - entry.bf.ipv6_addr_1 = host_entry->ip6_addr.ul[3] >> 10 | \ - host_entry->ip6_addr.ul[2] << 22; - entry.bf.ipv6_addr_2 = host_entry->ip6_addr.ul[2] >> 10 | \ - host_entry->ip6_addr.ul[1] << 22; - entry.bf.ipv6_addr_3 = host_entry->ip6_addr.ul[1] >> 10 | \ - host_entry->ip6_addr.ul[0] << 22; - entry.bf.ipv6_addr_4 = host_entry->ip6_addr.ul[0] >> 10; - rv = hppe_flow_host_ipv6_data_get(dev_id, (a_uint32_t)mode, &host_entry->entry_id, &entry); - host_entry->ip6_addr.ul[3] = entry.bf.ipv6_addr_0 | entry.bf.ipv6_addr_1 << 10; - host_entry->ip6_addr.ul[2] = entry.bf.ipv6_addr_1 >> 22 | entry.bf.ipv6_addr_2 << 10; - host_entry->ip6_addr.ul[1] = entry.bf.ipv6_addr_2 >> 22 | entry.bf.ipv6_addr_3 << 10; - host_entry->ip6_addr.ul[0] = entry.bf.ipv6_addr_3 >> 22 | entry.bf.ipv6_addr_4 << 10; - host_entry->lan_wan = entry.bf.lan_wan; - host_entry->port_id = entry.bf.dst_info; - host_entry->syn_toggle = entry.bf.syn_toggle; - host_entry->action = entry.bf.fwd_cmd; - host_entry->status = entry.bf.valid; - } - return rv; -} - -sw_error_t -adpt_hppe_ip_flow_host_data_del(a_uint32_t dev_id, a_uint32_t del_mode, - fal_host_entry_t * host_entry) -{ - a_uint8_t mode = 0, type = 0; - sw_error_t rv = SW_OK; - ADPT_DEV_ID_CHECK(dev_id); - ADPT_NULL_POINT_CHECK(host_entry); - - mode = host_entry->flags >> 24; - type = host_entry->flags & 0xff; - - if (del_mode & FAL_IP_ENTRY_ID_EN) - mode = 1; - else if (del_mode & FAL_IP_ENTRY_IPADDR_EN) - mode = 0; - else if (del_mode & FAL_IP_ENTRY_ALL_EN) { - return hppe_flow_host_flush_common(dev_id); - } - - if ((type & FAL_IP_IP4_ADDR) == FAL_IP_IP4_ADDR) { - union host_tbl_u entry; - entry.bf.valid= 1; - entry.bf.key_type = 0; - entry.bf.fwd_cmd = host_entry->action; - entry.bf.syn_toggle = host_entry->syn_toggle; - entry.bf.dst_info = host_entry->port_id; - entry.bf.lan_wan = host_entry->lan_wan; - entry.bf.ip_addr = host_entry->ip4_addr; - rv = hppe_flow_host_ipv4_data_del(dev_id, (a_uint32_t)mode, &host_entry->entry_id, &entry); - } else if ((type & FAL_IP_IP6_ADDR) == FAL_IP_IP6_ADDR) { - union host_ipv6_tbl_u entry; - entry.bf.valid= 1; - entry.bf.key_type = 2; - entry.bf.fwd_cmd = host_entry->action; - entry.bf.syn_toggle = host_entry->syn_toggle; - entry.bf.dst_info = host_entry->port_id; - entry.bf.lan_wan = host_entry->lan_wan; - entry.bf.ipv6_addr_0 = host_entry->ip6_addr.ul[3]; - entry.bf.ipv6_addr_1 = host_entry->ip6_addr.ul[3] >> 10 | \ - host_entry->ip6_addr.ul[2] << 22; - entry.bf.ipv6_addr_2 = host_entry->ip6_addr.ul[2] >> 10 | \ - host_entry->ip6_addr.ul[1] << 22; - entry.bf.ipv6_addr_3 = host_entry->ip6_addr.ul[1] >> 10 | \ - host_entry->ip6_addr.ul[0] << 22; - entry.bf.ipv6_addr_4 = host_entry->ip6_addr.ul[0] >> 10; - rv = hppe_flow_host_ipv6_data_del(dev_id, (a_uint32_t)mode, &host_entry->entry_id, &entry); - } - return rv; -} - - -sw_error_t -adpt_hppe_flow_entry_host_op_add( - a_uint32_t dev_id, - a_uint32_t add_mode, /*index or hash*/ - fal_flow_entry_t *flow_entry) -{ - sw_error_t rv = SW_OK; - a_uint32_t type = 0; - ADPT_DEV_ID_CHECK(dev_id); - ADPT_NULL_POINT_CHECK(flow_entry); - - type = flow_entry->entry_type; - if ((type & FAL_FLOW_IP4_5TUPLE_ADDR) == FAL_FLOW_IP4_5TUPLE_ADDR) { - union in_flow_tbl_u entry; - entry.bf0.valid= 1; - entry.bf0.entry_type = FLOW_ENTRY_TYPE_IPV4; - entry.bf0.host_addr_index_type = flow_entry->host_addr_type; - entry.bf0.host_addr_index = flow_entry->host_addr_index; - entry.bf0.protocol_type = flow_entry->protocol; - entry.bf0.age = flow_entry->age; - entry.bf0.src_l3_if_valid = flow_entry->src_intf_valid; - entry.bf0.src_l3_if = flow_entry->src_intf_index; - entry.bf0.fwd_type = flow_entry->fwd_type; - if (flow_entry->fwd_type == FAL_FLOW_SNAT) { - entry.bf0.next_hop1 = flow_entry->snat_nexthop; - entry.bf0.l4_port1 = flow_entry->snat_srcport; - } else if (flow_entry->fwd_type == FAL_FLOW_DNAT) { - entry.bf3.next_hop2 = flow_entry->dnat_nexthop; - entry.bf3.l4_port2 = flow_entry->dnat_dstport; - } else if (flow_entry->fwd_type == FAL_FLOW_ROUTE) { - entry.bf2.next_hop3 = flow_entry->route_nexthop; - entry.bf2.port_vp_valid1= flow_entry->port_valid; - entry.bf2.port_vp1 = flow_entry->route_port; - } else if (flow_entry->fwd_type == FAL_FLOW_BRIDGE) { - entry.bf1.port_vp2 = flow_entry->bridge_port; - } - entry.bf0.de_acce = flow_entry->deacclr_en; - entry.bf0.copy_to_cpu_en = flow_entry->copy_tocpu_en; - entry.bf0.syn_toggle = flow_entry->syn_toggle; - entry.bf0.pri_profile_0 = flow_entry->pri_profile; - entry.bf0.pri_profile_1 = flow_entry->pri_profile >> 1; - entry.bf0.service_code = flow_entry->sevice_code; - entry.bf0.ip_addr_0 = flow_entry->flow_ip.ipv4; - entry.bf0.ip_addr_1 = flow_entry->flow_ip.ipv4 >> 20; - entry.bf0.l4_sport = flow_entry->src_port; - entry.bf0.l4_dport_0 = flow_entry->dst_port; - entry.bf0.l4_dport_1 = flow_entry->dst_port >> 4; - rv = hppe_flow_entry_host_op_ipv4_5tuple_add(dev_id, (a_uint32_t)add_mode, &flow_entry->entry_id, &entry); - } else if ((type & FAL_FLOW_IP6_5TUPLE_ADDR) == FAL_FLOW_IP6_5TUPLE_ADDR) { - union in_flow_ipv6_5tuple_tbl_u entry; - entry.bf0.valid= 1; - entry.bf0.entry_type = FLOW_ENTRY_TYPE_IPV6; - entry.bf0.host_addr_index_type = flow_entry->host_addr_type; - entry.bf0.host_addr_index = flow_entry->host_addr_index; - entry.bf0.protocol_type = flow_entry->protocol; - entry.bf0.age = flow_entry->age; - entry.bf0.src_l3_if_valid = flow_entry->src_intf_valid; - entry.bf0.src_l3_if = flow_entry->src_intf_index; - entry.bf0.fwd_type = flow_entry->fwd_type; - if (flow_entry->fwd_type == FAL_FLOW_SNAT) { - entry.bf0.next_hop1 = flow_entry->snat_nexthop; - } else if (flow_entry->fwd_type == FAL_FLOW_DNAT) { - entry.bf3.next_hop2 = flow_entry->dnat_nexthop; - } else if (flow_entry->fwd_type == FAL_FLOW_ROUTE) { - entry.bf2.next_hop3 = flow_entry->route_nexthop; - entry.bf2.port_vp_valid1= flow_entry->port_valid; - entry.bf2.port_vp1 = flow_entry->route_port; - } else if (flow_entry->fwd_type == FAL_FLOW_BRIDGE) { - entry.bf1.port_vp2 = flow_entry->bridge_port; - } - entry.bf0.de_acce = flow_entry->deacclr_en; - entry.bf0.copy_to_cpu_en = flow_entry->copy_tocpu_en; - entry.bf0.syn_toggle = flow_entry->syn_toggle; - entry.bf0.pri_profile_0 = flow_entry->pri_profile; - entry.bf0.pri_profile_1 = flow_entry->pri_profile >> 1; - entry.bf0.service_code = flow_entry->sevice_code; - entry.bf0.ip_addr_0 = flow_entry->flow_ip.ipv6.ul[3]; - entry.bf0.ip_addr_1 = flow_entry->flow_ip.ipv6.ul[3] >> 20 |\ - flow_entry->flow_ip.ipv6.ul[2] << 12; - entry.bf0.ip_addr_2 = flow_entry->flow_ip.ipv6.ul[2] >> 20 |\ - flow_entry->flow_ip.ipv6.ul[1] << 12; - entry.bf0.ip_addr_3 = flow_entry->flow_ip.ipv6.ul[1] >> 20 |\ - flow_entry->flow_ip.ipv6.ul[0] << 12; - entry.bf0.ip_addr_4 = flow_entry->flow_ip.ipv6.ul[0] >> 20; - entry.bf0.l4_sport = flow_entry->src_port; - entry.bf0.l4_dport_0 = flow_entry->dst_port; - entry.bf0.l4_dport_1 = flow_entry->dst_port >> 4; - rv = hppe_flow_entry_host_op_ipv6_5tuple_add(dev_id, (a_uint32_t)add_mode, &flow_entry->entry_id, &entry); - } else if ((type & FAL_FLOW_IP4_3TUPLE_ADDR) == FAL_FLOW_IP4_3TUPLE_ADDR) { - union in_flow_3tuple_tbl_u entry; - entry.bf0.valid= 1; - entry.bf0.entry_type = FLOW_ENTRY_TYPE_IPV4; - entry.bf0.host_addr_index_type = flow_entry->host_addr_type; - entry.bf0.host_addr_index = flow_entry->host_addr_index; - entry.bf0.protocol_type = flow_entry->protocol; - entry.bf0.age = flow_entry->age; - entry.bf0.src_l3_if_valid = flow_entry->src_intf_valid; - entry.bf0.src_l3_if = flow_entry->src_intf_index; - entry.bf0.fwd_type = flow_entry->fwd_type; - if (flow_entry->fwd_type == FAL_FLOW_SNAT) { - entry.bf0.next_hop1 = flow_entry->snat_nexthop; - } else if (flow_entry->fwd_type == FAL_FLOW_DNAT) { - entry.bf3.next_hop2 = flow_entry->dnat_nexthop; - } else if (flow_entry->fwd_type == FAL_FLOW_ROUTE) { - entry.bf2.next_hop3 = flow_entry->route_nexthop; - entry.bf2.port_vp_valid1= flow_entry->port_valid; - entry.bf2.port_vp1 = flow_entry->route_port; - } else if (flow_entry->fwd_type == FAL_FLOW_BRIDGE) { - entry.bf1.port_vp2 = flow_entry->bridge_port; - } - entry.bf0.de_acce = flow_entry->deacclr_en; - entry.bf0.copy_to_cpu_en = flow_entry->copy_tocpu_en; - entry.bf0.syn_toggle = flow_entry->syn_toggle; - entry.bf0.pri_profile_0 = flow_entry->pri_profile; - entry.bf0.pri_profile_1 = flow_entry->pri_profile >> 1; - entry.bf0.service_code = flow_entry->sevice_code; - entry.bf0.ip_addr_0 = flow_entry->flow_ip.ipv4; - entry.bf0.ip_addr_1 = flow_entry->flow_ip.ipv4 >> 20; - entry.bf0.ip_protocol = flow_entry->ip_type; - rv = hppe_flow_entry_host_op_ipv4_3tuple_add(dev_id, (a_uint32_t)add_mode, &flow_entry->entry_id, &entry); - } else if ((type & FAL_FLOW_IP6_3TUPLE_ADDR) == FAL_FLOW_IP6_3TUPLE_ADDR) { - union in_flow_ipv6_3tuple_tbl_u entry; - entry.bf0.valid= 1; - entry.bf0.entry_type = FLOW_ENTRY_TYPE_IPV6; - entry.bf0.host_addr_index_type = flow_entry->host_addr_type; - entry.bf0.host_addr_index = flow_entry->host_addr_index; - entry.bf0.protocol_type = flow_entry->protocol; - entry.bf0.age = flow_entry->age; - entry.bf0.src_l3_if_valid = flow_entry->src_intf_valid; - entry.bf0.src_l3_if = flow_entry->src_intf_index; - entry.bf0.fwd_type = flow_entry->fwd_type; - if (flow_entry->fwd_type == FAL_FLOW_SNAT) { - entry.bf1.next_hop1 = flow_entry->snat_nexthop; - } else if (flow_entry->fwd_type == FAL_FLOW_DNAT) { - entry.bf3.next_hop2 = flow_entry->dnat_nexthop; - } else if (flow_entry->fwd_type == FAL_FLOW_ROUTE) { - entry.bf2.next_hop3 = flow_entry->route_nexthop; - entry.bf2.port_vp_valid1= flow_entry->port_valid; - entry.bf2.port_vp1 = flow_entry->route_port; - } else if (flow_entry->fwd_type == FAL_FLOW_BRIDGE) { - entry.bf0.port_vp2 = flow_entry->bridge_port; - } - entry.bf0.de_acce = flow_entry->deacclr_en; - entry.bf0.copy_to_cpu_en = flow_entry->copy_tocpu_en; - entry.bf0.syn_toggle = flow_entry->syn_toggle; - entry.bf0.pri_profile_0 = flow_entry->pri_profile; - entry.bf0.pri_profile_1 = flow_entry->pri_profile >> 1; - entry.bf0.service_code = flow_entry->sevice_code; - entry.bf0.ip_addr_0 = flow_entry->flow_ip.ipv6.ul[3]; - entry.bf0.ip_addr_1 = flow_entry->flow_ip.ipv6.ul[3] >> 20 |\ - flow_entry->flow_ip.ipv6.ul[2] << 12; - entry.bf0.ip_addr_2 = flow_entry->flow_ip.ipv6.ul[2] >> 20 |\ - flow_entry->flow_ip.ipv6.ul[1] << 12; - entry.bf0.ip_addr_3 = flow_entry->flow_ip.ipv6.ul[1] >> 20 |\ - flow_entry->flow_ip.ipv6.ul[0] << 12; - entry.bf0.ip_addr_4 = flow_entry->flow_ip.ipv6.ul[0] >> 20; - entry.bf0.ip_protocol = flow_entry->ip_type; - rv = hppe_flow_entry_host_op_ipv6_3tuple_add(dev_id, (a_uint32_t)add_mode, &flow_entry->entry_id, &entry); - } else - return SW_FAIL; - if (rv == SW_OK) { - union eg_flow_tree_map_tbl_u eg_treemap; - eg_treemap.bf.tree_id = flow_entry->tree_id; - rv = hppe_eg_flow_tree_map_tbl_set(dev_id, flow_entry->entry_id, &eg_treemap); - } - return rv; -} - -sw_error_t -adpt_hppe_flow_entry_host_op_get( - a_uint32_t dev_id, - a_uint32_t get_mode, - fal_flow_entry_t *flow_entry) -{ - sw_error_t rv = SW_OK; - a_uint32_t type = 0; - a_uint32_t entry_id = 0; - ADPT_DEV_ID_CHECK(dev_id); - ADPT_NULL_POINT_CHECK(flow_entry); - - type = flow_entry->entry_type; - if ((type & FAL_FLOW_IP4_5TUPLE_ADDR) == FAL_FLOW_IP4_5TUPLE_ADDR) { - union in_flow_tbl_u entry; - entry.bf0.valid= 1; - entry.bf0.entry_type = FLOW_ENTRY_TYPE_IPV4; - entry.bf0.host_addr_index_type = flow_entry->host_addr_type; - entry.bf0.host_addr_index = flow_entry->host_addr_index; - entry.bf0.protocol_type = flow_entry->protocol; - entry.bf0.ip_addr_0 = flow_entry->flow_ip.ipv4; - entry.bf0.ip_addr_1 = flow_entry->flow_ip.ipv4 >> 20; - entry.bf0.l4_sport = flow_entry->src_port; - entry.bf0.l4_dport_0 = flow_entry->dst_port; - entry.bf0.l4_dport_1 = flow_entry->dst_port >> 4; - rv = hppe_flow_entry_host_op_ipv4_5tuple_get(dev_id, get_mode, &entry_id, &entry); - flow_entry->entry_id = entry_id; - flow_entry->host_addr_type = entry.bf0.host_addr_index_type; - flow_entry->host_addr_index = entry.bf0.host_addr_index; - flow_entry->protocol = entry.bf0.protocol_type; - flow_entry->age = entry.bf0.age; - flow_entry->src_intf_valid = entry.bf0.src_l3_if_valid; - flow_entry->src_intf_index = entry.bf0.src_l3_if; - flow_entry->fwd_type = entry.bf0.fwd_type; - if (flow_entry->fwd_type == FAL_FLOW_SNAT) { - flow_entry->snat_nexthop = entry.bf0.next_hop1; - flow_entry->snat_srcport = entry.bf0.l4_port1; - } else if (flow_entry->fwd_type == FAL_FLOW_DNAT) { - flow_entry->dnat_nexthop = entry.bf3.next_hop2; - flow_entry->dnat_dstport = entry.bf3.l4_port2; - } else if (flow_entry->fwd_type == FAL_FLOW_ROUTE) { - flow_entry->route_nexthop = entry.bf2.next_hop3; - flow_entry->port_valid = entry.bf2.port_vp_valid1; - flow_entry->route_port = entry.bf2.port_vp1; - } else if (flow_entry->fwd_type == FAL_FLOW_BRIDGE) { - flow_entry->bridge_port = entry.bf1.port_vp2; - } - flow_entry->deacclr_en = entry.bf0.de_acce; - flow_entry->copy_tocpu_en = entry.bf0.copy_to_cpu_en; - flow_entry->syn_toggle = entry.bf0.syn_toggle; - flow_entry->pri_profile = entry.bf0.pri_profile_0 |\ - entry.bf0.pri_profile_1 << 1; - flow_entry->sevice_code = entry.bf0.service_code; - flow_entry->flow_ip.ipv4 = entry.bf0.ip_addr_0 |\ - entry.bf0.ip_addr_1 << 20; - flow_entry->src_port = entry.bf0.l4_sport; - flow_entry->dst_port = entry.bf0.l4_dport_0 |\ - entry.bf0.l4_dport_1 << 4; - } else if ((type & FAL_FLOW_IP6_5TUPLE_ADDR) == FAL_FLOW_IP6_5TUPLE_ADDR) { - union in_flow_ipv6_5tuple_tbl_u entry; - entry.bf0.valid= 1; - entry.bf0.entry_type = FLOW_ENTRY_TYPE_IPV6; - entry.bf0.host_addr_index_type = flow_entry->host_addr_type; - entry.bf0.host_addr_index = flow_entry->host_addr_index; - entry.bf0.protocol_type = flow_entry->protocol; - entry.bf0.ip_addr_0 = flow_entry->flow_ip.ipv6.ul[3]; - entry.bf0.ip_addr_1 = flow_entry->flow_ip.ipv6.ul[3] >> 20 |\ - flow_entry->flow_ip.ipv6.ul[2] << 12; - entry.bf0.ip_addr_2 = flow_entry->flow_ip.ipv6.ul[2] >> 20 |\ - flow_entry->flow_ip.ipv6.ul[1] << 12; - entry.bf0.ip_addr_3 = flow_entry->flow_ip.ipv6.ul[1] >> 20 |\ - flow_entry->flow_ip.ipv6.ul[0] << 12; - entry.bf0.ip_addr_4 = flow_entry->flow_ip.ipv6.ul[0] >> 20; - entry.bf0.l4_sport = flow_entry->src_port; - entry.bf0.l4_dport_0 = flow_entry->dst_port; - entry.bf0.l4_dport_1 = flow_entry->dst_port >> 4; - rv = hppe_flow_entry_host_op_ipv6_5tuple_get(dev_id, get_mode, &entry_id, &entry); - flow_entry->entry_id = entry_id; - flow_entry->host_addr_type = entry.bf0.host_addr_index_type; - flow_entry->host_addr_index = entry.bf0.host_addr_index; - flow_entry->protocol = entry.bf0.protocol_type; - flow_entry->age = entry.bf0.age; - flow_entry->src_intf_valid = entry.bf0.src_l3_if_valid; - flow_entry->src_intf_index = entry.bf0.src_l3_if; - flow_entry->fwd_type = entry.bf0.fwd_type; - if (flow_entry->fwd_type == FAL_FLOW_SNAT) { - flow_entry->snat_nexthop = entry.bf0.next_hop1; - } else if (flow_entry->fwd_type == FAL_FLOW_DNAT) { - flow_entry->dnat_nexthop = entry.bf3.next_hop2; - } else if (flow_entry->fwd_type == FAL_FLOW_ROUTE) { - flow_entry->route_nexthop = entry.bf2.next_hop3; - flow_entry->port_valid = entry.bf2.port_vp_valid1; - flow_entry->route_port = entry.bf2.port_vp1; - } else if (flow_entry->fwd_type == FAL_FLOW_BRIDGE) { - flow_entry->bridge_port = entry.bf1.port_vp2; - } - flow_entry->deacclr_en = entry.bf0.de_acce; - flow_entry->copy_tocpu_en = entry.bf0.copy_to_cpu_en; - flow_entry->syn_toggle = entry.bf0.syn_toggle; - flow_entry->pri_profile = entry.bf0.pri_profile_0 |\ - entry.bf0.pri_profile_1 << 1; - flow_entry->sevice_code = entry.bf0.service_code; - flow_entry->flow_ip.ipv6.ul[3] = entry.bf0.ip_addr_0 |\ - entry.bf0.ip_addr_1 << 20; - flow_entry->flow_ip.ipv6.ul[2] = entry.bf0.ip_addr_1 >> 12 |\ - entry.bf0.ip_addr_2 << 20; - flow_entry->flow_ip.ipv6.ul[1] = entry.bf0.ip_addr_2 >> 12 |\ - entry.bf0.ip_addr_3 << 20; - flow_entry->flow_ip.ipv6.ul[0] = entry.bf0.ip_addr_3 >> 12 |\ - entry.bf0.ip_addr_4 << 20; - flow_entry->src_port = entry.bf0.l4_sport; - flow_entry->dst_port = entry.bf0.l4_dport_0 |\ - entry.bf0.l4_dport_1 << 4; - } else if ((type & FAL_FLOW_IP4_3TUPLE_ADDR) == FAL_FLOW_IP4_3TUPLE_ADDR) { - union in_flow_3tuple_tbl_u entry; - entry.bf0.valid= 1; - entry.bf0.entry_type = FLOW_ENTRY_TYPE_IPV4; - entry.bf0.host_addr_index_type = flow_entry->host_addr_type; - entry.bf0.host_addr_index = flow_entry->host_addr_index; - entry.bf0.protocol_type = flow_entry->protocol; - entry.bf0.ip_addr_0 = flow_entry->flow_ip.ipv4; - entry.bf0.ip_addr_1 = flow_entry->flow_ip.ipv4 >> 20; - entry.bf0.ip_protocol = flow_entry->ip_type; - rv = hppe_flow_entry_host_op_ipv4_3tuple_get(dev_id, get_mode, &entry_id, &entry); - flow_entry->entry_id = entry_id; - flow_entry->host_addr_type = entry.bf0.host_addr_index_type; - flow_entry->host_addr_index = entry.bf0.host_addr_index; - flow_entry->protocol = entry.bf0.protocol_type; - flow_entry->age = entry.bf0.age; - flow_entry->src_intf_valid = entry.bf0.src_l3_if_valid; - flow_entry->src_intf_index = entry.bf0.src_l3_if; - flow_entry->fwd_type = entry.bf0.fwd_type; - if (flow_entry->fwd_type == FAL_FLOW_SNAT) { - flow_entry->snat_nexthop = entry.bf0.next_hop1; - } else if (flow_entry->fwd_type == FAL_FLOW_DNAT) { - flow_entry->dnat_nexthop = entry.bf3.next_hop2; - } else if (flow_entry->fwd_type == FAL_FLOW_ROUTE) { - flow_entry->route_nexthop = entry.bf2.next_hop3; - flow_entry->port_valid = entry.bf2.port_vp_valid1; - flow_entry->route_port = entry.bf2.port_vp1; - } else if (flow_entry->fwd_type == FAL_FLOW_BRIDGE) { - flow_entry->bridge_port = entry.bf1.port_vp2; - } - flow_entry->deacclr_en = entry.bf0.de_acce; - flow_entry->copy_tocpu_en = entry.bf0.copy_to_cpu_en; - flow_entry->syn_toggle = entry.bf0.syn_toggle; - flow_entry->pri_profile = entry.bf0.pri_profile_0 |\ - entry.bf0.pri_profile_1 << 1; - flow_entry->sevice_code = entry.bf0.service_code; - flow_entry->flow_ip.ipv4 = entry.bf0.ip_addr_0 |\ - entry.bf0.ip_addr_1 << 20; - flow_entry->ip_type = entry.bf0.ip_protocol; - } else if ((type & FAL_FLOW_IP6_3TUPLE_ADDR) == FAL_FLOW_IP6_3TUPLE_ADDR) { - union in_flow_ipv6_3tuple_tbl_u entry; - entry.bf0.valid= 1; - entry.bf0.entry_type = FLOW_ENTRY_TYPE_IPV6; - entry.bf0.host_addr_index_type = flow_entry->host_addr_type; - entry.bf0.host_addr_index = flow_entry->host_addr_index; - entry.bf0.protocol_type = flow_entry->protocol; - entry.bf0.ip_addr_0 = flow_entry->flow_ip.ipv6.ul[3]; - entry.bf0.ip_addr_1 = flow_entry->flow_ip.ipv6.ul[3] >> 20 |\ - flow_entry->flow_ip.ipv6.ul[2] << 12; - entry.bf0.ip_addr_2 = flow_entry->flow_ip.ipv6.ul[2] >> 20 |\ - flow_entry->flow_ip.ipv6.ul[1] << 12; - entry.bf0.ip_addr_3 = flow_entry->flow_ip.ipv6.ul[1] >> 20 |\ - flow_entry->flow_ip.ipv6.ul[0] << 12; - entry.bf0.ip_addr_4 = flow_entry->flow_ip.ipv6.ul[0] >> 20; - entry.bf0.ip_protocol = flow_entry->ip_type; - rv = hppe_flow_entry_host_op_ipv6_3tuple_get(dev_id, get_mode, &entry_id, &entry); - flow_entry->entry_id = entry_id; - flow_entry->host_addr_type = entry.bf0.host_addr_index_type; - flow_entry->host_addr_index = entry.bf0.host_addr_index; - flow_entry->protocol = entry.bf0.protocol_type; - flow_entry->age = entry.bf0.age; - flow_entry->src_intf_valid = entry.bf0.src_l3_if_valid; - flow_entry->src_intf_index = entry.bf0.src_l3_if; - flow_entry->fwd_type = entry.bf0.fwd_type; - if (flow_entry->fwd_type == FAL_FLOW_SNAT) { - flow_entry->snat_nexthop = entry.bf1.next_hop1; - } else if (flow_entry->fwd_type == FAL_FLOW_DNAT) { - flow_entry->dnat_nexthop = entry.bf3.next_hop2; - } else if (flow_entry->fwd_type == FAL_FLOW_ROUTE) { - flow_entry->route_nexthop = entry.bf2.next_hop3; - flow_entry->port_valid = entry.bf2.port_vp_valid1; - flow_entry->route_port = entry.bf2.port_vp1; - } else if (flow_entry->fwd_type == FAL_FLOW_BRIDGE) { - flow_entry->bridge_port = entry.bf0.port_vp2; - } - flow_entry->deacclr_en = entry.bf0.de_acce; - flow_entry->copy_tocpu_en = entry.bf0.copy_to_cpu_en; - flow_entry->syn_toggle = entry.bf0.syn_toggle; - flow_entry->pri_profile = entry.bf0.pri_profile_0 |\ - entry.bf0.pri_profile_1 << 1; - flow_entry->sevice_code = entry.bf0.service_code; - flow_entry->flow_ip.ipv6.ul[3] = entry.bf0.ip_addr_0 |\ - entry.bf0.ip_addr_1 << 20; - flow_entry->flow_ip.ipv6.ul[2] = entry.bf0.ip_addr_1 >> 12 |\ - entry.bf0.ip_addr_2 << 20; - flow_entry->flow_ip.ipv6.ul[1] = entry.bf0.ip_addr_2 >> 12 |\ - entry.bf0.ip_addr_3 << 20; - flow_entry->flow_ip.ipv6.ul[0] = entry.bf0.ip_addr_3 >> 12 |\ - entry.bf0.ip_addr_4 << 20; - flow_entry->ip_type = entry.bf0.ip_protocol; - } else - return SW_FAIL; - - if (rv == SW_OK) { - union eg_flow_tree_map_tbl_u eg_treemap; - union in_flow_cnt_tbl_u cnt; - rv = hppe_eg_flow_tree_map_tbl_get(dev_id, flow_entry->entry_id, &eg_treemap); - flow_entry->tree_id = eg_treemap.bf.tree_id; - rv = hppe_in_flow_cnt_tbl_get(dev_id, flow_entry->entry_id, &cnt); - flow_entry->pkt_counter = cnt.bf.hit_pkt_counter; - flow_entry->byte_counter = cnt.bf.hit_byte_counter_0 | \ - ((a_uint64_t)cnt.bf.hit_byte_counter_1 << 32); - } - return rv; -} - -sw_error_t -adpt_hppe_flow_entry_host_op_del( - a_uint32_t dev_id, - a_uint32_t del_mode, - fal_flow_entry_t *flow_entry) -{ - sw_error_t rv = SW_OK; - a_uint32_t type = 0; - ADPT_DEV_ID_CHECK(dev_id); - ADPT_NULL_POINT_CHECK(flow_entry); - - if (del_mode == FAL_FLOW_OP_MODE_FLUSH) - return hppe_flow_host_flush_common(dev_id); - //return hppe_flow_flush_common(dev_id); - - type = flow_entry->entry_type; - if ((type & FAL_FLOW_IP4_5TUPLE_ADDR) == FAL_FLOW_IP4_5TUPLE_ADDR) { - union in_flow_tbl_u entry; - entry.bf0.entry_type = FLOW_ENTRY_TYPE_IPV4; - entry.bf0.host_addr_index_type = flow_entry->host_addr_type; - entry.bf0.host_addr_index = flow_entry->host_addr_index; - entry.bf0.protocol_type = flow_entry->protocol; - entry.bf0.age = flow_entry->age; - entry.bf0.src_l3_if_valid = flow_entry->src_intf_valid; - entry.bf0.src_l3_if = flow_entry->src_intf_index; - entry.bf0.fwd_type = flow_entry->fwd_type; - if (flow_entry->fwd_type == FAL_FLOW_SNAT) { - entry.bf0.next_hop1 = flow_entry->snat_nexthop; - entry.bf0.l4_port1 = flow_entry->snat_srcport; - } else if (flow_entry->fwd_type == FAL_FLOW_DNAT) { - entry.bf3.next_hop2 = flow_entry->dnat_nexthop; - entry.bf3.l4_port2 = flow_entry->dnat_dstport; - } else if (flow_entry->fwd_type == FAL_FLOW_ROUTE) { - entry.bf2.next_hop3 = flow_entry->route_nexthop; - entry.bf2.port_vp_valid1= flow_entry->port_valid; - entry.bf2.port_vp1 = flow_entry->route_port; - } else if (flow_entry->fwd_type == FAL_FLOW_BRIDGE) { - entry.bf1.port_vp2 = flow_entry->bridge_port; - } - entry.bf0.de_acce = flow_entry->deacclr_en; - entry.bf0.copy_to_cpu_en = flow_entry->copy_tocpu_en; - entry.bf0.syn_toggle = flow_entry->syn_toggle; - entry.bf0.pri_profile_0 = flow_entry->pri_profile; - entry.bf0.pri_profile_1 = flow_entry->pri_profile >> 1; - entry.bf0.service_code = flow_entry->sevice_code; - entry.bf0.ip_addr_0 = flow_entry->flow_ip.ipv4; - entry.bf0.ip_addr_1 = flow_entry->flow_ip.ipv4 >> 20; - entry.bf0.l4_sport = flow_entry->src_port; - entry.bf0.l4_dport_0 = flow_entry->dst_port; - entry.bf0.l4_dport_1 = flow_entry->dst_port >> 4; - rv = hppe_flow_entry_host_op_ipv4_5tuple_del(dev_id, del_mode, &flow_entry->entry_id, &entry); - } else if ((type & FAL_FLOW_IP6_5TUPLE_ADDR) == FAL_FLOW_IP6_5TUPLE_ADDR) { - union in_flow_ipv6_5tuple_tbl_u entry; - entry.bf0.entry_type = FLOW_ENTRY_TYPE_IPV6; - entry.bf0.host_addr_index_type = flow_entry->host_addr_type; - entry.bf0.host_addr_index = flow_entry->host_addr_index; - entry.bf0.protocol_type = flow_entry->protocol; - entry.bf0.age = flow_entry->age; - entry.bf0.src_l3_if_valid = flow_entry->src_intf_valid; - entry.bf0.src_l3_if = flow_entry->src_intf_index; - entry.bf0.fwd_type = flow_entry->fwd_type; - if (flow_entry->fwd_type == FAL_FLOW_SNAT) { - entry.bf0.next_hop1 = flow_entry->snat_nexthop; - } else if (flow_entry->fwd_type == FAL_FLOW_DNAT) { - entry.bf3.next_hop2 = flow_entry->dnat_nexthop; - } else if (flow_entry->fwd_type == FAL_FLOW_ROUTE) { - entry.bf2.next_hop3 = flow_entry->route_nexthop; - entry.bf2.port_vp_valid1= flow_entry->port_valid; - entry.bf2.port_vp1 = flow_entry->route_port; - } else if (flow_entry->fwd_type == FAL_FLOW_BRIDGE) { - entry.bf1.port_vp2 = flow_entry->bridge_port; - } - entry.bf0.de_acce = flow_entry->deacclr_en; - entry.bf0.copy_to_cpu_en = flow_entry->copy_tocpu_en; - entry.bf0.syn_toggle = flow_entry->syn_toggle; - entry.bf0.pri_profile_0 = flow_entry->pri_profile; - entry.bf0.pri_profile_1 = flow_entry->pri_profile >> 1; - entry.bf0.service_code = flow_entry->sevice_code; - entry.bf0.ip_addr_0 = flow_entry->flow_ip.ipv6.ul[3]; - entry.bf0.ip_addr_1 = flow_entry->flow_ip.ipv6.ul[3] >> 20 |\ - flow_entry->flow_ip.ipv6.ul[2] << 12; - entry.bf0.ip_addr_2 = flow_entry->flow_ip.ipv6.ul[2] >> 20 |\ - flow_entry->flow_ip.ipv6.ul[1] << 12; - entry.bf0.ip_addr_3 = flow_entry->flow_ip.ipv6.ul[1] >> 20 |\ - flow_entry->flow_ip.ipv6.ul[0] << 12; - entry.bf0.ip_addr_4 = flow_entry->flow_ip.ipv6.ul[0] >> 20; - entry.bf0.l4_sport = flow_entry->src_port; - entry.bf0.l4_dport_0 = flow_entry->dst_port; - entry.bf0.l4_dport_1 = flow_entry->dst_port >> 4; - rv = hppe_flow_entry_host_op_ipv6_5tuple_del(dev_id, del_mode, &flow_entry->entry_id, &entry); - } else if ((type & FAL_FLOW_IP4_3TUPLE_ADDR) == FAL_FLOW_IP4_3TUPLE_ADDR) { - union in_flow_3tuple_tbl_u entry; - entry.bf0.entry_type = FLOW_ENTRY_TYPE_IPV4; - entry.bf0.host_addr_index_type = flow_entry->host_addr_type; - entry.bf0.host_addr_index = flow_entry->host_addr_index; - entry.bf0.protocol_type = flow_entry->protocol; - entry.bf0.age = flow_entry->age; - entry.bf0.src_l3_if_valid = flow_entry->src_intf_valid; - entry.bf0.src_l3_if = flow_entry->src_intf_index; - entry.bf0.fwd_type = flow_entry->fwd_type; - if (flow_entry->fwd_type == FAL_FLOW_SNAT) { - entry.bf0.next_hop1 = flow_entry->snat_nexthop; - } else if (flow_entry->fwd_type == FAL_FLOW_DNAT) { - entry.bf3.next_hop2 = flow_entry->dnat_nexthop; - } else if (flow_entry->fwd_type == FAL_FLOW_ROUTE) { - entry.bf2.next_hop3 = flow_entry->route_nexthop; - entry.bf2.port_vp_valid1= flow_entry->port_valid; - entry.bf2.port_vp1 = flow_entry->route_port; - } else if (flow_entry->fwd_type == FAL_FLOW_BRIDGE) { - entry.bf1.port_vp2 = flow_entry->bridge_port; - } - entry.bf0.de_acce = flow_entry->deacclr_en; - entry.bf0.copy_to_cpu_en = flow_entry->copy_tocpu_en; - entry.bf0.syn_toggle = flow_entry->syn_toggle; - entry.bf0.pri_profile_0 = flow_entry->pri_profile; - entry.bf0.pri_profile_1 = flow_entry->pri_profile >> 1; - entry.bf0.service_code = flow_entry->sevice_code; - entry.bf0.ip_addr_0 = flow_entry->flow_ip.ipv4; - entry.bf0.ip_addr_1 = flow_entry->flow_ip.ipv4 >> 20; - entry.bf0.ip_protocol = flow_entry->ip_type; - rv = hppe_flow_entry_host_op_ipv4_3tuple_del(dev_id, del_mode, &flow_entry->entry_id, &entry); - } else if ((type & FAL_FLOW_IP6_3TUPLE_ADDR) == FAL_FLOW_IP6_3TUPLE_ADDR) { - union in_flow_ipv6_3tuple_tbl_u entry; - entry.bf0.entry_type = FLOW_ENTRY_TYPE_IPV6; - entry.bf0.host_addr_index_type = flow_entry->host_addr_type; - entry.bf0.host_addr_index = flow_entry->host_addr_index; - entry.bf0.protocol_type = flow_entry->protocol; - entry.bf0.age = flow_entry->age; - entry.bf0.src_l3_if_valid = flow_entry->src_intf_valid; - entry.bf0.src_l3_if = flow_entry->src_intf_index; - entry.bf0.fwd_type = flow_entry->fwd_type; - if (flow_entry->fwd_type == FAL_FLOW_SNAT) { - entry.bf1.next_hop1 = flow_entry->snat_nexthop; - } else if (flow_entry->fwd_type == FAL_FLOW_DNAT) { - entry.bf3.next_hop2 = flow_entry->dnat_nexthop; - } else if (flow_entry->fwd_type == FAL_FLOW_ROUTE) { - entry.bf2.next_hop3 = flow_entry->route_nexthop; - entry.bf2.port_vp_valid1= flow_entry->port_valid; - entry.bf2.port_vp1 = flow_entry->route_port; - } else if (flow_entry->fwd_type == FAL_FLOW_BRIDGE) { - entry.bf0.port_vp2 = flow_entry->bridge_port; - } - entry.bf0.de_acce = flow_entry->deacclr_en; - entry.bf0.copy_to_cpu_en = flow_entry->copy_tocpu_en; - entry.bf0.syn_toggle = flow_entry->syn_toggle; - entry.bf0.pri_profile_0 = flow_entry->pri_profile; - entry.bf0.pri_profile_1 = flow_entry->pri_profile >> 1; - entry.bf0.service_code = flow_entry->sevice_code; - entry.bf0.ip_addr_0 = flow_entry->flow_ip.ipv6.ul[3]; - entry.bf0.ip_addr_1 = flow_entry->flow_ip.ipv6.ul[3] >> 20 |\ - flow_entry->flow_ip.ipv6.ul[2] << 12; - entry.bf0.ip_addr_2 = flow_entry->flow_ip.ipv6.ul[2] >> 20 |\ - flow_entry->flow_ip.ipv6.ul[1] << 12; - entry.bf0.ip_addr_3 = flow_entry->flow_ip.ipv6.ul[1] >> 20 |\ - flow_entry->flow_ip.ipv6.ul[0] << 12; - entry.bf0.ip_addr_4 = flow_entry->flow_ip.ipv6.ul[0] >> 20; - entry.bf0.ip_protocol = flow_entry->ip_type; - rv = hppe_flow_entry_host_op_ipv6_3tuple_del(dev_id, del_mode, &flow_entry->entry_id, &entry); - } else - return SW_FAIL; - return rv; -} - -sw_error_t -adpt_hppe_flow_host_add( - a_uint32_t dev_id, - a_uint32_t add_mode, - fal_flow_host_entry_t *flow_host) -{ - sw_error_t rv = SW_OK; - fal_flow_entry_t *flow_entry = &(flow_host->flow_entry); - fal_host_entry_t *host_entry = &(flow_host->host_entry); - ADPT_DEV_ID_CHECK(dev_id); - ADPT_NULL_POINT_CHECK(flow_host); - - rv = adpt_hppe_ip_flow_host_data_add(dev_id, host_entry); - SW_RTN_ON_ERROR(rv); - rv = adpt_hppe_flow_entry_host_op_add(dev_id, add_mode, flow_entry); - SW_RTN_ON_ERROR(rv); - - rv = hppe_flow_host_tbl_op_rslt_host_entry_index_get(dev_id, &host_entry->entry_id); - return rv; -} - -sw_error_t -adpt_hppe_flow_host_get( - a_uint32_t dev_id, - a_uint32_t get_mode, - fal_flow_host_entry_t *flow_host) -{ - sw_error_t rv = SW_OK; - fal_flow_entry_t *flow_entry = &(flow_host->flow_entry); - fal_host_entry_t *host_entry = &(flow_host->host_entry); - ADPT_DEV_ID_CHECK(dev_id); - ADPT_NULL_POINT_CHECK(flow_host); - - rv = adpt_hppe_ip_flow_host_data_rd_add(dev_id, host_entry); - rv = adpt_hppe_flow_entry_host_op_get(dev_id, get_mode, flow_entry); - if(rv != SW_OK) - return rv; - - rv = hppe_flow_host_tbl_rd_op_rslt_host_entry_index_get(dev_id, &host_entry->entry_id); - if(rv != SW_OK) - return rv; - - rv = adpt_hppe_ip_flow_host_data_get(dev_id, get_mode, host_entry); - - return rv; -} - -sw_error_t -adpt_hppe_flow_host_del( - a_uint32_t dev_id, - a_uint32_t del_mode, - fal_flow_host_entry_t *flow_host) -{ - fal_flow_entry_t *flow_entry = &(flow_host->flow_entry); - fal_host_entry_t *host_entry = &(flow_host->host_entry); - ADPT_DEV_ID_CHECK(dev_id); - ADPT_NULL_POINT_CHECK(flow_host); - - adpt_hppe_ip_flow_host_data_del(dev_id, del_mode, host_entry); - adpt_hppe_flow_entry_host_op_del(dev_id, del_mode, flow_entry); - return SW_OK; -} - - -sw_error_t -adpt_hppe_flow_entry_get( - a_uint32_t dev_id, - a_uint32_t get_mode, - fal_flow_entry_t *flow_entry) -{ - sw_error_t rv = SW_OK; - a_uint32_t type = 0; - ADPT_DEV_ID_CHECK(dev_id); - ADPT_NULL_POINT_CHECK(flow_entry); - - - type = flow_entry->entry_type; - if ((type & FAL_FLOW_IP4_5TUPLE_ADDR) == FAL_FLOW_IP4_5TUPLE_ADDR) { - union in_flow_tbl_u entry; - entry.bf0.entry_type = FLOW_ENTRY_TYPE_IPV4; - entry.bf0.host_addr_index_type = flow_entry->host_addr_type; - entry.bf0.host_addr_index = flow_entry->host_addr_index; - entry.bf0.protocol_type = flow_entry->protocol; - entry.bf0.ip_addr_0 = flow_entry->flow_ip.ipv4; - entry.bf0.ip_addr_1 = flow_entry->flow_ip.ipv4 >> 20; - entry.bf0.l4_sport = flow_entry->src_port; - entry.bf0.l4_dport_0 = flow_entry->dst_port; - entry.bf0.l4_dport_1 = flow_entry->dst_port >> 4; - rv = hppe_flow_ipv4_5tuple_get(dev_id, get_mode, &flow_entry->entry_id, &entry); - if (entry.bf0.entry_type != FLOW_ENTRY_TYPE_IPV4 || - entry.bf0.protocol_type == FLOW_TUPLE_TYPE_3) { - return SW_BAD_VALUE; - } - flow_entry->host_addr_type = entry.bf0.host_addr_index_type; - flow_entry->host_addr_index = entry.bf0.host_addr_index; - flow_entry->protocol = entry.bf0.protocol_type; - flow_entry->age = entry.bf0.age; - flow_entry->src_intf_valid = entry.bf0.src_l3_if_valid; - flow_entry->src_intf_index = entry.bf0.src_l3_if; - flow_entry->fwd_type = entry.bf0.fwd_type; - if (flow_entry->fwd_type == FAL_FLOW_SNAT) { - flow_entry->snat_nexthop = entry.bf0.next_hop1; - flow_entry->snat_srcport = entry.bf0.l4_port1; - } else if (flow_entry->fwd_type == FAL_FLOW_DNAT) { - flow_entry->dnat_nexthop = entry.bf3.next_hop2; - flow_entry->dnat_dstport = entry.bf3.l4_port2; - } else if (flow_entry->fwd_type == FAL_FLOW_ROUTE) { - flow_entry->route_nexthop = entry.bf2.next_hop3; - flow_entry->port_valid = entry.bf2.port_vp_valid1; - flow_entry->route_port = entry.bf2.port_vp1; - if (entry.bf2.port_vp1 >= 64) - flow_entry->route_port |= 0x1000000; - } else if (flow_entry->fwd_type == FAL_FLOW_BRIDGE) { - flow_entry->bridge_port = entry.bf1.port_vp2; - if (entry.bf1.port_vp2 >= 64) - flow_entry->bridge_port |= 0x1000000; - } - flow_entry->deacclr_en = entry.bf0.de_acce; - flow_entry->copy_tocpu_en = entry.bf0.copy_to_cpu_en; - flow_entry->syn_toggle = entry.bf0.syn_toggle; - flow_entry->pri_profile = entry.bf0.pri_profile_0 |\ - entry.bf0.pri_profile_1 << 1; - flow_entry->sevice_code = entry.bf0.service_code; - flow_entry->flow_ip.ipv4 = entry.bf0.ip_addr_0 |\ - entry.bf0.ip_addr_1 << 20; - flow_entry->src_port = entry.bf0.l4_sport; - flow_entry->dst_port = entry.bf0.l4_dport_0 |\ - entry.bf0.l4_dport_1 << 4; - - } else if ((type & FAL_FLOW_IP6_5TUPLE_ADDR) == FAL_FLOW_IP6_5TUPLE_ADDR) { - union in_flow_ipv6_5tuple_tbl_u entry; - entry.bf0.entry_type = FLOW_ENTRY_TYPE_IPV6; - entry.bf0.host_addr_index_type = flow_entry->host_addr_type; - entry.bf0.host_addr_index = flow_entry->host_addr_index; - entry.bf0.protocol_type = flow_entry->protocol; - entry.bf0.ip_addr_0 = flow_entry->flow_ip.ipv6.ul[3]; - entry.bf0.ip_addr_1 = flow_entry->flow_ip.ipv6.ul[3] >> 20 |\ - flow_entry->flow_ip.ipv6.ul[2] << 12; - entry.bf0.ip_addr_2 = flow_entry->flow_ip.ipv6.ul[2] >> 20 |\ - flow_entry->flow_ip.ipv6.ul[1] << 12; - entry.bf0.ip_addr_3 = flow_entry->flow_ip.ipv6.ul[1] >> 20 |\ - flow_entry->flow_ip.ipv6.ul[0] << 12; - entry.bf0.ip_addr_4 = flow_entry->flow_ip.ipv6.ul[0] >> 20; - entry.bf0.l4_sport = flow_entry->src_port; - entry.bf0.l4_dport_0 = flow_entry->dst_port; - entry.bf0.l4_dport_1 = flow_entry->dst_port >> 4; - rv = hppe_flow_ipv6_5tuple_get(dev_id, get_mode, &flow_entry->entry_id, &entry); - if (entry.bf0.entry_type != FLOW_ENTRY_TYPE_IPV6 || - entry.bf0.protocol_type == FLOW_TUPLE_TYPE_3) { - return SW_BAD_VALUE; - } - flow_entry->host_addr_type = entry.bf0.host_addr_index_type; - flow_entry->host_addr_index = entry.bf0.host_addr_index; - flow_entry->protocol = entry.bf0.protocol_type; - flow_entry->age = entry.bf0.age; - flow_entry->src_intf_valid = entry.bf0.src_l3_if_valid; - flow_entry->src_intf_index = entry.bf0.src_l3_if; - flow_entry->fwd_type = entry.bf0.fwd_type; - if (flow_entry->fwd_type == FAL_FLOW_SNAT) { - flow_entry->snat_nexthop = entry.bf0.next_hop1; - } else if (flow_entry->fwd_type == FAL_FLOW_DNAT) { - flow_entry->dnat_nexthop = entry.bf3.next_hop2; - } else if (flow_entry->fwd_type == FAL_FLOW_ROUTE) { - flow_entry->route_nexthop = entry.bf2.next_hop3; - flow_entry->port_valid = entry.bf2.port_vp_valid1; - flow_entry->route_port = entry.bf2.port_vp1; - if (entry.bf2.port_vp1 >= 64) - flow_entry->route_port |= 0x1000000; - } else if (flow_entry->fwd_type == FAL_FLOW_BRIDGE) { - flow_entry->bridge_port = entry.bf1.port_vp2; - if (entry.bf1.port_vp2 >= 64) - flow_entry->bridge_port |= 0x1000000; - } - flow_entry->deacclr_en = entry.bf0.de_acce; - flow_entry->copy_tocpu_en = entry.bf0.copy_to_cpu_en; - flow_entry->syn_toggle = entry.bf0.syn_toggle; - flow_entry->pri_profile = entry.bf0.pri_profile_0 |\ - entry.bf0.pri_profile_1 << 1; - flow_entry->sevice_code = entry.bf0.service_code; - flow_entry->flow_ip.ipv6.ul[3] = entry.bf0.ip_addr_0 |\ - entry.bf0.ip_addr_1 << 20; - flow_entry->flow_ip.ipv6.ul[2] = entry.bf0.ip_addr_1 >> 12 |\ - entry.bf0.ip_addr_2 << 20; - flow_entry->flow_ip.ipv6.ul[1] = entry.bf0.ip_addr_2 >> 12 |\ - entry.bf0.ip_addr_3 << 20; - flow_entry->flow_ip.ipv6.ul[0] = entry.bf0.ip_addr_3 >> 12 |\ - entry.bf0.ip_addr_4 << 20; - flow_entry->src_port = entry.bf0.l4_sport; - flow_entry->dst_port = entry.bf0.l4_dport_0 |\ - entry.bf0.l4_dport_1 << 4; - - } else if ((type & FAL_FLOW_IP4_3TUPLE_ADDR) == FAL_FLOW_IP4_3TUPLE_ADDR) { - union in_flow_3tuple_tbl_u entry; - entry.bf0.entry_type = FLOW_ENTRY_TYPE_IPV4; - entry.bf0.host_addr_index_type = flow_entry->host_addr_type; - entry.bf0.host_addr_index = flow_entry->host_addr_index; - entry.bf0.protocol_type = flow_entry->protocol; - entry.bf0.ip_addr_0 = flow_entry->flow_ip.ipv4; - entry.bf0.ip_addr_1 = flow_entry->flow_ip.ipv4 >> 20; - entry.bf0.ip_protocol = flow_entry->ip_type; - rv = hppe_flow_ipv4_3tuple_get(dev_id, get_mode, &flow_entry->entry_id, &entry); - if (entry.bf0.entry_type != FLOW_ENTRY_TYPE_IPV4 || - entry.bf0.protocol_type != FLOW_TUPLE_TYPE_3) { - return SW_BAD_VALUE; - } - flow_entry->host_addr_type = entry.bf0.host_addr_index_type; - flow_entry->host_addr_index = entry.bf0.host_addr_index; - flow_entry->protocol = entry.bf0.protocol_type; - flow_entry->age = entry.bf0.age; - flow_entry->src_intf_valid = entry.bf0.src_l3_if_valid; - flow_entry->src_intf_index = entry.bf0.src_l3_if; - flow_entry->fwd_type = entry.bf0.fwd_type; - if (flow_entry->fwd_type == FAL_FLOW_SNAT) { - flow_entry->snat_nexthop = entry.bf0.next_hop1; - } else if (flow_entry->fwd_type == FAL_FLOW_DNAT) { - flow_entry->dnat_nexthop = entry.bf3.next_hop2; - } else if (flow_entry->fwd_type == FAL_FLOW_ROUTE) { - flow_entry->route_nexthop = entry.bf2.next_hop3; - flow_entry->port_valid = entry.bf2.port_vp_valid1; - flow_entry->route_port = entry.bf2.port_vp1; - if (entry.bf2.port_vp1 >= 64) - flow_entry->route_port |= 0x1000000; - } else if (flow_entry->fwd_type == FAL_FLOW_BRIDGE) { - flow_entry->bridge_port = entry.bf1.port_vp2; - if (entry.bf1.port_vp2 >= 64) - flow_entry->bridge_port |= 0x1000000; - } - flow_entry->deacclr_en = entry.bf0.de_acce; - flow_entry->copy_tocpu_en = entry.bf0.copy_to_cpu_en; - flow_entry->syn_toggle = entry.bf0.syn_toggle; - flow_entry->pri_profile = entry.bf0.pri_profile_0 |\ - entry.bf0.pri_profile_1 << 1; - flow_entry->sevice_code = entry.bf0.service_code; - flow_entry->flow_ip.ipv4 = entry.bf0.ip_addr_0 |\ - entry.bf0.ip_addr_1 << 20; - flow_entry->ip_type = entry.bf0.ip_protocol; - } else if ((type & FAL_FLOW_IP6_3TUPLE_ADDR) == FAL_FLOW_IP6_3TUPLE_ADDR) { - union in_flow_ipv6_3tuple_tbl_u entry; - entry.bf0.entry_type = FLOW_ENTRY_TYPE_IPV6; - entry.bf0.host_addr_index_type = flow_entry->host_addr_type; - entry.bf0.host_addr_index = flow_entry->host_addr_index; - entry.bf0.protocol_type = flow_entry->protocol; - entry.bf0.ip_addr_0 = flow_entry->flow_ip.ipv6.ul[3]; - entry.bf0.ip_addr_1 = flow_entry->flow_ip.ipv6.ul[3] >> 20 |\ - flow_entry->flow_ip.ipv6.ul[2] << 12; - entry.bf0.ip_addr_2 = flow_entry->flow_ip.ipv6.ul[2] >> 20 |\ - flow_entry->flow_ip.ipv6.ul[1] << 12; - entry.bf0.ip_addr_3 = flow_entry->flow_ip.ipv6.ul[1] >> 20 |\ - flow_entry->flow_ip.ipv6.ul[0] << 12; - entry.bf0.ip_addr_4 = flow_entry->flow_ip.ipv6.ul[0] >> 20; - entry.bf0.ip_protocol = flow_entry->ip_type; - rv = hppe_flow_ipv6_3tuple_get(dev_id, get_mode, &flow_entry->entry_id, &entry); - if (entry.bf0.entry_type != FLOW_ENTRY_TYPE_IPV6 || - entry.bf0.protocol_type != FLOW_TUPLE_TYPE_3) { - return SW_BAD_VALUE; - } - flow_entry->host_addr_type = entry.bf0.host_addr_index_type; - flow_entry->host_addr_index = entry.bf0.host_addr_index; - flow_entry->protocol = entry.bf0.protocol_type; - flow_entry->age = entry.bf0.age; - flow_entry->src_intf_valid = entry.bf0.src_l3_if_valid; - flow_entry->src_intf_index = entry.bf0.src_l3_if; - flow_entry->fwd_type = entry.bf0.fwd_type; - if (flow_entry->fwd_type == FAL_FLOW_SNAT) { - flow_entry->snat_nexthop = entry.bf1.next_hop1; - } else if (flow_entry->fwd_type == FAL_FLOW_DNAT) { - flow_entry->dnat_nexthop = entry.bf3.next_hop2; - } else if (flow_entry->fwd_type == FAL_FLOW_ROUTE) { - flow_entry->route_nexthop = entry.bf2.next_hop3; - flow_entry->port_valid = entry.bf2.port_vp_valid1; - flow_entry->route_port = entry.bf2.port_vp1; - if (entry.bf2.port_vp1 >= 64) - flow_entry->route_port |= 0x1000000; - } else if (flow_entry->fwd_type == FAL_FLOW_BRIDGE) { - flow_entry->bridge_port = entry.bf0.port_vp2; - if (entry.bf0.port_vp2 >= 64) - flow_entry->bridge_port |= 0x1000000; - } - flow_entry->deacclr_en = entry.bf0.de_acce; - flow_entry->copy_tocpu_en = entry.bf0.copy_to_cpu_en; - flow_entry->syn_toggle = entry.bf0.syn_toggle; - flow_entry->pri_profile = entry.bf0.pri_profile_0 |\ - entry.bf0.pri_profile_1 << 1; - flow_entry->sevice_code = entry.bf0.service_code; - flow_entry->flow_ip.ipv6.ul[3] = entry.bf0.ip_addr_0 |\ - entry.bf0.ip_addr_1 << 20; - flow_entry->flow_ip.ipv6.ul[2] = entry.bf0.ip_addr_1 >> 12 |\ - entry.bf0.ip_addr_2 << 20; - flow_entry->flow_ip.ipv6.ul[1] = entry.bf0.ip_addr_2 >> 12 |\ - entry.bf0.ip_addr_3 << 20; - flow_entry->flow_ip.ipv6.ul[0] = entry.bf0.ip_addr_3 >> 12 |\ - entry.bf0.ip_addr_4 << 20; - flow_entry->ip_type = entry.bf0.ip_protocol; - } else - return SW_FAIL; - - if (rv == SW_OK) { - union eg_flow_tree_map_tbl_u eg_treemap; - union in_flow_cnt_tbl_u cnt; - rv = hppe_eg_flow_tree_map_tbl_get(dev_id, flow_entry->entry_id, &eg_treemap); - flow_entry->tree_id = eg_treemap.bf.tree_id; - rv = hppe_in_flow_cnt_tbl_get(dev_id, flow_entry->entry_id, &cnt); - flow_entry->pkt_counter = cnt.bf.hit_pkt_counter; - flow_entry->byte_counter = cnt.bf.hit_byte_counter_0 | \ - ((a_uint64_t)cnt.bf.hit_byte_counter_1 << 32); - } - return rv; -} - -sw_error_t -adpt_hppe_flow_entry_next( - a_uint32_t dev_id, - a_uint32_t next_mode, - fal_flow_entry_t *flow_entry) -{ - a_uint32_t i = 0, step = 0; - sw_error_t rv = SW_OK; - - ADPT_DEV_ID_CHECK(dev_id); - ADPT_NULL_POINT_CHECK(flow_entry); - - if (FAL_NEXT_ENTRY_FIRST_ID == flow_entry->entry_id) - i = 0; - - if (next_mode == FAL_FLOW_IP4_3TUPLE_ADDR || - next_mode == FAL_FLOW_IP4_5TUPLE_ADDR) { - if (FAL_NEXT_ENTRY_FIRST_ID != flow_entry->entry_id) - i = flow_entry->entry_id + 1; - step = 1; - } else if (next_mode == FAL_FLOW_IP6_5TUPLE_ADDR || - next_mode == FAL_FLOW_IP6_3TUPLE_ADDR) { - if (FAL_NEXT_ENTRY_FIRST_ID != flow_entry->entry_id) - i = (flow_entry->entry_id & ~1) + 2; - step = 2; - } - for (; i < IN_FLOW_TBL_MAX_ENTRY;) { - flow_entry->entry_type = next_mode; - flow_entry->entry_id = i; - rv = adpt_hppe_flow_entry_get(dev_id, 1, flow_entry); - if (!rv) { - return rv; - } - i += step; - } - - return SW_FAIL; - -} - -sw_error_t -adpt_hppe_flow_entry_del( - a_uint32_t dev_id, - a_uint32_t del_mode, - fal_flow_entry_t *flow_entry) -{ - sw_error_t rv = SW_OK; - a_uint32_t type = 0; - ADPT_DEV_ID_CHECK(dev_id); - ADPT_NULL_POINT_CHECK(flow_entry); - - if (del_mode == FAL_FLOW_OP_MODE_FLUSH) - return hppe_flow_flush_common(dev_id); - - type = flow_entry->entry_type; - if ((type & FAL_FLOW_IP4_5TUPLE_ADDR) == FAL_FLOW_IP4_5TUPLE_ADDR) { - union in_flow_tbl_u entry; - entry.bf0.entry_type = FLOW_ENTRY_TYPE_IPV4; - entry.bf0.host_addr_index_type = flow_entry->host_addr_type; - entry.bf0.host_addr_index = flow_entry->host_addr_index; - entry.bf0.protocol_type = flow_entry->protocol; - entry.bf0.age = flow_entry->age; - entry.bf0.src_l3_if_valid = flow_entry->src_intf_valid; - entry.bf0.src_l3_if = flow_entry->src_intf_index; - entry.bf0.fwd_type = flow_entry->fwd_type; - if (flow_entry->fwd_type == FAL_FLOW_SNAT) { - entry.bf0.next_hop1 = flow_entry->snat_nexthop; - entry.bf0.l4_port1 = flow_entry->snat_srcport; - } else if (flow_entry->fwd_type == FAL_FLOW_DNAT) { - entry.bf3.next_hop2 = flow_entry->dnat_nexthop; - entry.bf3.l4_port2 = flow_entry->dnat_dstport; - } else if (flow_entry->fwd_type == FAL_FLOW_ROUTE) { - entry.bf2.next_hop3 = flow_entry->route_nexthop; - entry.bf2.port_vp_valid1= flow_entry->port_valid; - entry.bf2.port_vp1 = flow_entry->route_port & 0xffffff; - } else if (flow_entry->fwd_type == FAL_FLOW_BRIDGE) { - entry.bf1.port_vp2 = flow_entry->bridge_port & 0xffffff; - } - entry.bf0.de_acce = flow_entry->deacclr_en; - entry.bf0.copy_to_cpu_en = flow_entry->copy_tocpu_en; - entry.bf0.syn_toggle = flow_entry->syn_toggle; - entry.bf0.pri_profile_0 = flow_entry->pri_profile; - entry.bf0.pri_profile_1 = flow_entry->pri_profile >> 1; - entry.bf0.service_code = flow_entry->sevice_code; - entry.bf0.ip_addr_0 = flow_entry->flow_ip.ipv4; - entry.bf0.ip_addr_1 = flow_entry->flow_ip.ipv4 >> 20; - entry.bf0.l4_sport = flow_entry->src_port; - entry.bf0.l4_dport_0 = flow_entry->dst_port; - entry.bf0.l4_dport_1 = flow_entry->dst_port >> 4; - rv = hppe_flow_ipv4_5tuple_del(dev_id, del_mode, &flow_entry->entry_id, &entry); - } else if ((type & FAL_FLOW_IP6_5TUPLE_ADDR) == FAL_FLOW_IP6_5TUPLE_ADDR) { - union in_flow_ipv6_5tuple_tbl_u entry; - entry.bf0.entry_type = FLOW_ENTRY_TYPE_IPV6; - entry.bf0.host_addr_index_type = flow_entry->host_addr_type; - entry.bf0.host_addr_index = flow_entry->host_addr_index; - entry.bf0.protocol_type = flow_entry->protocol; - entry.bf0.age = flow_entry->age; - entry.bf0.src_l3_if_valid = flow_entry->src_intf_valid; - entry.bf0.src_l3_if = flow_entry->src_intf_index; - entry.bf0.fwd_type = flow_entry->fwd_type; - if (flow_entry->fwd_type == FAL_FLOW_SNAT) { - entry.bf0.next_hop1 = flow_entry->snat_nexthop; - } else if (flow_entry->fwd_type == FAL_FLOW_DNAT) { - entry.bf3.next_hop2 = flow_entry->dnat_nexthop; - } else if (flow_entry->fwd_type == FAL_FLOW_ROUTE) { - entry.bf2.next_hop3 = flow_entry->route_nexthop; - entry.bf2.port_vp_valid1= flow_entry->port_valid; - entry.bf2.port_vp1 = flow_entry->route_port & 0xffffff; - } else if (flow_entry->fwd_type == FAL_FLOW_BRIDGE) { - entry.bf1.port_vp2 = flow_entry->bridge_port & 0xffffff; - } - entry.bf0.de_acce = flow_entry->deacclr_en; - entry.bf0.copy_to_cpu_en = flow_entry->copy_tocpu_en; - entry.bf0.syn_toggle = flow_entry->syn_toggle; - entry.bf0.pri_profile_0 = flow_entry->pri_profile; - entry.bf0.pri_profile_1 = flow_entry->pri_profile >> 1; - entry.bf0.service_code = flow_entry->sevice_code; - entry.bf0.ip_addr_0 = flow_entry->flow_ip.ipv6.ul[3]; - entry.bf0.ip_addr_1 = flow_entry->flow_ip.ipv6.ul[3] >> 20 |\ - flow_entry->flow_ip.ipv6.ul[2] << 12; - entry.bf0.ip_addr_2 = flow_entry->flow_ip.ipv6.ul[2] >> 20 |\ - flow_entry->flow_ip.ipv6.ul[1] << 12; - entry.bf0.ip_addr_3 = flow_entry->flow_ip.ipv6.ul[1] >> 20 |\ - flow_entry->flow_ip.ipv6.ul[0] << 12; - entry.bf0.ip_addr_4 = flow_entry->flow_ip.ipv6.ul[0] >> 20; - entry.bf0.l4_sport = flow_entry->src_port; - entry.bf0.l4_dport_0 = flow_entry->dst_port; - entry.bf0.l4_dport_1 = flow_entry->dst_port >> 4; - rv = hppe_flow_ipv6_5tuple_del(dev_id, del_mode, &flow_entry->entry_id, &entry); - } else if ((type & FAL_FLOW_IP4_3TUPLE_ADDR) == FAL_FLOW_IP4_3TUPLE_ADDR) { - union in_flow_3tuple_tbl_u entry; - entry.bf0.entry_type = FLOW_ENTRY_TYPE_IPV4; - entry.bf0.host_addr_index_type = flow_entry->host_addr_type; - entry.bf0.host_addr_index = flow_entry->host_addr_index; - entry.bf0.protocol_type = flow_entry->protocol; - entry.bf0.age = flow_entry->age; - entry.bf0.src_l3_if_valid = flow_entry->src_intf_valid; - entry.bf0.src_l3_if = flow_entry->src_intf_index; - entry.bf0.fwd_type = flow_entry->fwd_type; - if (flow_entry->fwd_type == FAL_FLOW_SNAT) { - entry.bf0.next_hop1 = flow_entry->snat_nexthop; - } else if (flow_entry->fwd_type == FAL_FLOW_DNAT) { - entry.bf3.next_hop2 = flow_entry->dnat_nexthop; - } else if (flow_entry->fwd_type == FAL_FLOW_ROUTE) { - entry.bf2.next_hop3 = flow_entry->route_nexthop; - entry.bf2.port_vp_valid1= flow_entry->port_valid; - entry.bf2.port_vp1 = flow_entry->route_port & 0xffffff; - } else if (flow_entry->fwd_type == FAL_FLOW_BRIDGE) { - entry.bf1.port_vp2 = flow_entry->bridge_port & 0xffffff; - } - entry.bf0.de_acce = flow_entry->deacclr_en; - entry.bf0.copy_to_cpu_en = flow_entry->copy_tocpu_en; - entry.bf0.syn_toggle = flow_entry->syn_toggle; - entry.bf0.pri_profile_0 = flow_entry->pri_profile; - entry.bf0.pri_profile_1 = flow_entry->pri_profile >> 1; - entry.bf0.service_code = flow_entry->sevice_code; - entry.bf0.ip_addr_0 = flow_entry->flow_ip.ipv4; - entry.bf0.ip_addr_1 = flow_entry->flow_ip.ipv4 >> 20; - entry.bf0.ip_protocol = flow_entry->ip_type; - rv = hppe_flow_ipv4_3tuple_del(dev_id, del_mode, &flow_entry->entry_id, &entry); - } else if ((type & FAL_FLOW_IP6_3TUPLE_ADDR) == FAL_FLOW_IP6_3TUPLE_ADDR) { - union in_flow_ipv6_3tuple_tbl_u entry; - entry.bf0.entry_type = FLOW_ENTRY_TYPE_IPV6; - entry.bf0.host_addr_index_type = flow_entry->host_addr_type; - entry.bf0.host_addr_index = flow_entry->host_addr_index; - entry.bf0.protocol_type = flow_entry->protocol; - entry.bf0.age = flow_entry->age; - entry.bf0.src_l3_if_valid = flow_entry->src_intf_valid; - entry.bf0.src_l3_if = flow_entry->src_intf_index; - entry.bf0.fwd_type = flow_entry->fwd_type; - if (flow_entry->fwd_type == FAL_FLOW_SNAT) { - entry.bf1.next_hop1 = flow_entry->snat_nexthop; - } else if (flow_entry->fwd_type == FAL_FLOW_DNAT) { - entry.bf3.next_hop2 = flow_entry->dnat_nexthop; - } else if (flow_entry->fwd_type == FAL_FLOW_ROUTE) { - entry.bf2.next_hop3 = flow_entry->route_nexthop; - entry.bf2.port_vp_valid1= flow_entry->port_valid; - entry.bf2.port_vp1 = flow_entry->route_port & 0xffffff; - } else if (flow_entry->fwd_type == FAL_FLOW_BRIDGE) { - entry.bf0.port_vp2 = flow_entry->bridge_port & 0xffffff; - } - entry.bf0.de_acce = flow_entry->deacclr_en; - entry.bf0.copy_to_cpu_en = flow_entry->copy_tocpu_en; - entry.bf0.syn_toggle = flow_entry->syn_toggle; - entry.bf0.pri_profile_0 = flow_entry->pri_profile; - entry.bf0.pri_profile_1 = flow_entry->pri_profile >> 1; - entry.bf0.service_code = flow_entry->sevice_code; - entry.bf0.ip_addr_0 = flow_entry->flow_ip.ipv6.ul[3]; - entry.bf0.ip_addr_1 = flow_entry->flow_ip.ipv6.ul[3] >> 20 |\ - flow_entry->flow_ip.ipv6.ul[2] << 12; - entry.bf0.ip_addr_2 = flow_entry->flow_ip.ipv6.ul[2] >> 20 |\ - flow_entry->flow_ip.ipv6.ul[1] << 12; - entry.bf0.ip_addr_3 = flow_entry->flow_ip.ipv6.ul[1] >> 20 |\ - flow_entry->flow_ip.ipv6.ul[0] << 12; - entry.bf0.ip_addr_4 = flow_entry->flow_ip.ipv6.ul[0] >> 20; - entry.bf0.ip_protocol = flow_entry->ip_type; - rv = hppe_flow_ipv6_3tuple_del(dev_id, del_mode, &flow_entry->entry_id, &entry); - } else - return SW_FAIL; - return rv; -} -sw_error_t -adpt_hppe_flow_status_get(a_uint32_t dev_id, a_bool_t *enable) -{ - sw_error_t rv = SW_OK; - union flow_ctrl0_u flow_ctrl0; - - ADPT_DEV_ID_CHECK(dev_id); - ADPT_NULL_POINT_CHECK(enable); - - memset(&flow_ctrl0, 0, sizeof(flow_ctrl0)); - - rv = hppe_flow_ctrl0_get(dev_id, &flow_ctrl0); - if( rv != SW_OK ) - return rv; - - *enable = flow_ctrl0.bf.flow_en; - return SW_OK; -} -#endif - -sw_error_t -adpt_hppe_flow_ctrl_set( - a_uint32_t dev_id, - fal_flow_pkt_type_t type, - fal_flow_direction_t dir, - fal_flow_mgmt_t *ctrl) -{ - sw_error_t rv = SW_OK; - union flow_ctrl1_u flow_ctrl1; - - ADPT_DEV_ID_CHECK(dev_id); - ADPT_NULL_POINT_CHECK(ctrl); - - memset(&flow_ctrl1, 0, sizeof(flow_ctrl1)); - rv = hppe_flow_ctrl1_get(dev_id, type, &flow_ctrl1); - if( rv != SW_OK ) - return rv; - - if (dir == FAL_FLOW_LAN_TO_LAN_DIR) { - flow_ctrl1.bf.flow_ctl0_miss_action = ctrl->miss_action; - flow_ctrl1.bf.flow_ctl0_frag_bypass = ctrl->frag_bypass_en; - flow_ctrl1.bf.flow_ctl0_tcp_special = ctrl->tcp_spec_bypass_en; - flow_ctrl1.bf.flow_ctl0_bypass = ctrl->all_bypass_en; - flow_ctrl1.bf.flow_ctl0_key_sel = ctrl->key_sel; - } else if (dir == FAL_FLOW_LAN_TO_WAN_DIR) { - flow_ctrl1.bf.flow_ctl1_miss_action = ctrl->miss_action; - flow_ctrl1.bf.flow_ctl1_frag_bypass = ctrl->frag_bypass_en; - flow_ctrl1.bf.flow_ctl1_tcp_special = ctrl->tcp_spec_bypass_en; - flow_ctrl1.bf.flow_ctl1_bypass = ctrl->all_bypass_en; - flow_ctrl1.bf.flow_ctl1_key_sel = ctrl->key_sel; - } else if (dir == FAL_FLOW_WAN_TO_LAN_DIR) { - flow_ctrl1.bf.flow_ctl2_miss_action = ctrl->miss_action; - flow_ctrl1.bf.flow_ctl2_frag_bypass = ctrl->frag_bypass_en; - flow_ctrl1.bf.flow_ctl2_tcp_special = ctrl->tcp_spec_bypass_en; - flow_ctrl1.bf.flow_ctl2_bypass = ctrl->all_bypass_en; - flow_ctrl1.bf.flow_ctl2_key_sel = ctrl->key_sel; - } else if (dir == FAL_FLOW_WAN_TO_WAN_DIR) { - flow_ctrl1.bf.flow_ctl3_miss_action = ctrl->miss_action; - flow_ctrl1.bf.flow_ctl3_frag_bypass = ctrl->frag_bypass_en; - flow_ctrl1.bf.flow_ctl3_tcp_special = ctrl->tcp_spec_bypass_en; - flow_ctrl1.bf.flow_ctl3_bypass = ctrl->all_bypass_en; - flow_ctrl1.bf.flow_ctl3_key_sel = ctrl->key_sel; - } else if (dir == FAL_FLOW_UNKOWN_DIR_DIR) { - flow_ctrl1.bf.flow_ctl4_miss_action = ctrl->miss_action; - flow_ctrl1.bf.flow_ctl4_frag_bypass = ctrl->frag_bypass_en; - flow_ctrl1.bf.flow_ctl4_tcp_special = ctrl->tcp_spec_bypass_en; - flow_ctrl1.bf.flow_ctl4_bypass = ctrl->all_bypass_en; - flow_ctrl1.bf.flow_ctl4_key_sel = ctrl->key_sel; - } else - return SW_FAIL; - - return hppe_flow_ctrl1_set(dev_id, type, &flow_ctrl1);; -} - -#ifndef IN_FLOW_MINI -sw_error_t -adpt_hppe_flow_age_timer_get(a_uint32_t dev_id, fal_flow_age_timer_t *age_timer) -{ - sw_error_t rv = SW_OK; - union flow_ctrl0_u flow_ctrl0; - - ADPT_DEV_ID_CHECK(dev_id); - ADPT_NULL_POINT_CHECK(age_timer); - - memset(&flow_ctrl0, 0, sizeof(flow_ctrl0)); - - rv = hppe_flow_ctrl0_get(dev_id, &flow_ctrl0); - if( rv != SW_OK ) - return rv; - - age_timer->age_time = flow_ctrl0.bf.flow_age_timer; - age_timer->unit = flow_ctrl0.bf.flow_age_timer_unit; - return SW_OK; -} - -sw_error_t -adpt_hppe_flow_status_set(a_uint32_t dev_id, a_bool_t enable) -{ - sw_error_t rv = SW_OK; - union flow_ctrl0_u flow_ctrl0; - - ADPT_DEV_ID_CHECK(dev_id); - - memset(&flow_ctrl0, 0, sizeof(flow_ctrl0)); - - rv = hppe_flow_ctrl0_get(dev_id, &flow_ctrl0); - if( rv != SW_OK ) - return rv; - - flow_ctrl0.bf.flow_en = enable; - return hppe_flow_ctrl0_set(dev_id, &flow_ctrl0); -} -#endif - -sw_error_t -adpt_hppe_flow_ctrl_get( - a_uint32_t dev_id, - fal_flow_pkt_type_t type, - fal_flow_direction_t dir, - fal_flow_mgmt_t *ctrl) -{ - sw_error_t rv = SW_OK; - union flow_ctrl1_u flow_ctrl1; - - ADPT_DEV_ID_CHECK(dev_id); - ADPT_NULL_POINT_CHECK(ctrl); - - memset(&flow_ctrl1, 0, sizeof(flow_ctrl1)); - rv = hppe_flow_ctrl1_get(dev_id, type, &flow_ctrl1); - if( rv != SW_OK ) - return rv; - - if (dir == FAL_FLOW_LAN_TO_LAN_DIR) { - ctrl->miss_action = flow_ctrl1.bf.flow_ctl0_miss_action; - ctrl->frag_bypass_en = flow_ctrl1.bf.flow_ctl0_frag_bypass; - ctrl->tcp_spec_bypass_en = flow_ctrl1.bf.flow_ctl0_tcp_special; - ctrl->all_bypass_en = flow_ctrl1.bf.flow_ctl0_bypass; - ctrl->key_sel = flow_ctrl1.bf.flow_ctl0_key_sel; - } else if (dir == FAL_FLOW_LAN_TO_WAN_DIR) { - ctrl->miss_action = flow_ctrl1.bf.flow_ctl1_miss_action; - ctrl->frag_bypass_en = flow_ctrl1.bf.flow_ctl1_frag_bypass; - ctrl->tcp_spec_bypass_en = flow_ctrl1.bf.flow_ctl1_tcp_special; - ctrl->all_bypass_en = flow_ctrl1.bf.flow_ctl1_bypass; - ctrl->key_sel = flow_ctrl1.bf.flow_ctl1_key_sel; - } else if (dir == FAL_FLOW_WAN_TO_LAN_DIR) { - ctrl->miss_action = flow_ctrl1.bf.flow_ctl2_miss_action; - ctrl->frag_bypass_en = flow_ctrl1.bf.flow_ctl2_frag_bypass; - ctrl->tcp_spec_bypass_en = flow_ctrl1.bf.flow_ctl2_tcp_special; - ctrl->all_bypass_en = flow_ctrl1.bf.flow_ctl2_bypass; - ctrl->key_sel = flow_ctrl1.bf.flow_ctl2_key_sel; - } else if (dir == FAL_FLOW_WAN_TO_WAN_DIR) { - ctrl->miss_action = flow_ctrl1.bf.flow_ctl3_miss_action; - ctrl->frag_bypass_en = flow_ctrl1.bf.flow_ctl3_frag_bypass; - ctrl->tcp_spec_bypass_en = flow_ctrl1.bf.flow_ctl3_tcp_special; - ctrl->all_bypass_en = flow_ctrl1.bf.flow_ctl3_bypass; - ctrl->key_sel = flow_ctrl1.bf.flow_ctl3_key_sel; - } else if (dir == FAL_FLOW_UNKOWN_DIR_DIR) { - ctrl->miss_action = flow_ctrl1.bf.flow_ctl4_miss_action; - ctrl->frag_bypass_en = flow_ctrl1.bf.flow_ctl4_frag_bypass; - ctrl->tcp_spec_bypass_en = flow_ctrl1.bf.flow_ctl4_tcp_special; - ctrl->all_bypass_en = flow_ctrl1.bf.flow_ctl4_bypass; - ctrl->key_sel = flow_ctrl1.bf.flow_ctl4_key_sel; - } else - return SW_FAIL; - - return SW_OK; -} - -#ifndef IN_FLOW_MINI -sw_error_t -adpt_hppe_flow_age_timer_set(a_uint32_t dev_id, fal_flow_age_timer_t *age_timer) -{ - sw_error_t rv = SW_OK; - union flow_ctrl0_u flow_ctrl0; - - ADPT_DEV_ID_CHECK(dev_id); - ADPT_NULL_POINT_CHECK(age_timer); - - memset(&flow_ctrl0, 0, sizeof(flow_ctrl0)); - - rv = hppe_flow_ctrl0_get(dev_id, &flow_ctrl0); - if( rv != SW_OK ) - return rv; - - flow_ctrl0.bf.flow_age_timer = age_timer->age_time; - flow_ctrl0.bf.flow_age_timer_unit = age_timer->unit; - return hppe_flow_ctrl0_set(dev_id, &flow_ctrl0); -} - -sw_error_t -adpt_hppe_flow_entry_add( - a_uint32_t dev_id, - a_uint32_t add_mode, /*index or hash*/ - fal_flow_entry_t *flow_entry) -{ - sw_error_t rv = SW_OK; - a_uint32_t type = 0; - ADPT_DEV_ID_CHECK(dev_id); - ADPT_NULL_POINT_CHECK(flow_entry); - - type = flow_entry->entry_type; - if ((type & FAL_FLOW_IP4_5TUPLE_ADDR) == FAL_FLOW_IP4_5TUPLE_ADDR) { - union in_flow_tbl_u entry; - entry.bf0.valid= 1; - entry.bf0.entry_type = FLOW_ENTRY_TYPE_IPV4; - entry.bf0.host_addr_index_type = flow_entry->host_addr_type; - entry.bf0.host_addr_index = flow_entry->host_addr_index; - entry.bf0.protocol_type = flow_entry->protocol; - entry.bf0.age = flow_entry->age; - entry.bf0.src_l3_if_valid = flow_entry->src_intf_valid; - entry.bf0.src_l3_if = flow_entry->src_intf_index; - entry.bf0.fwd_type = flow_entry->fwd_type; - if (flow_entry->fwd_type == FAL_FLOW_SNAT) { - entry.bf0.next_hop1 = flow_entry->snat_nexthop; - entry.bf0.l4_port1 = flow_entry->snat_srcport; - } else if (flow_entry->fwd_type == FAL_FLOW_DNAT) { - entry.bf3.next_hop2 = flow_entry->dnat_nexthop; - entry.bf3.l4_port2 = flow_entry->dnat_dstport; - } else if (flow_entry->fwd_type == FAL_FLOW_ROUTE) { - entry.bf2.next_hop3 = flow_entry->route_nexthop; - entry.bf2.port_vp_valid1= flow_entry->port_valid; - entry.bf2.port_vp1 = flow_entry->route_port & 0xffffff; - } else if (flow_entry->fwd_type == FAL_FLOW_BRIDGE) { - entry.bf1.port_vp2 = flow_entry->bridge_port & 0xffffff; - } - entry.bf0.de_acce = flow_entry->deacclr_en; - entry.bf0.copy_to_cpu_en = flow_entry->copy_tocpu_en; - entry.bf0.syn_toggle = flow_entry->syn_toggle; - entry.bf0.pri_profile_0 = flow_entry->pri_profile; - entry.bf0.pri_profile_1 = flow_entry->pri_profile >> 1; - entry.bf0.service_code = flow_entry->sevice_code; - entry.bf0.ip_addr_0 = flow_entry->flow_ip.ipv4; - entry.bf0.ip_addr_1 = flow_entry->flow_ip.ipv4 >> 20; - entry.bf0.l4_sport = flow_entry->src_port; - entry.bf0.l4_dport_0 = flow_entry->dst_port; - entry.bf0.l4_dport_1 = flow_entry->dst_port >> 4; - rv = hppe_flow_ipv4_5tuple_add(dev_id, (a_uint32_t)add_mode, &flow_entry->entry_id, &entry); - } else if ((type & FAL_FLOW_IP6_5TUPLE_ADDR) == FAL_FLOW_IP6_5TUPLE_ADDR) { - union in_flow_ipv6_5tuple_tbl_u entry; - entry.bf0.valid= 1; - entry.bf0.entry_type = FLOW_ENTRY_TYPE_IPV6; - entry.bf0.host_addr_index_type = flow_entry->host_addr_type; - entry.bf0.host_addr_index = flow_entry->host_addr_index; - entry.bf0.protocol_type = flow_entry->protocol; - entry.bf0.age = flow_entry->age; - entry.bf0.src_l3_if_valid = flow_entry->src_intf_valid; - entry.bf0.src_l3_if = flow_entry->src_intf_index; - entry.bf0.fwd_type = flow_entry->fwd_type; - if (flow_entry->fwd_type == FAL_FLOW_SNAT) { - entry.bf0.next_hop1 = flow_entry->snat_nexthop; - } else if (flow_entry->fwd_type == FAL_FLOW_DNAT) { - entry.bf3.next_hop2 = flow_entry->dnat_nexthop; - } else if (flow_entry->fwd_type == FAL_FLOW_ROUTE) { - entry.bf2.next_hop3 = flow_entry->route_nexthop; - entry.bf2.port_vp_valid1= flow_entry->port_valid; - entry.bf2.port_vp1 = flow_entry->route_port & 0xffffff; - } else if (flow_entry->fwd_type == FAL_FLOW_BRIDGE) { - entry.bf1.port_vp2 = flow_entry->bridge_port & 0xffffff; - } - entry.bf0.de_acce = flow_entry->deacclr_en; - entry.bf0.copy_to_cpu_en = flow_entry->copy_tocpu_en; - entry.bf0.syn_toggle = flow_entry->syn_toggle; - entry.bf0.pri_profile_0 = flow_entry->pri_profile; - entry.bf0.pri_profile_1 = flow_entry->pri_profile >> 1; - entry.bf0.service_code = flow_entry->sevice_code; - entry.bf0.ip_addr_0 = flow_entry->flow_ip.ipv6.ul[3]; - entry.bf0.ip_addr_1 = flow_entry->flow_ip.ipv6.ul[3] >> 20 |\ - flow_entry->flow_ip.ipv6.ul[2] << 12; - entry.bf0.ip_addr_2 = flow_entry->flow_ip.ipv6.ul[2] >> 20 |\ - flow_entry->flow_ip.ipv6.ul[1] << 12; - entry.bf0.ip_addr_3 = flow_entry->flow_ip.ipv6.ul[1] >> 20 |\ - flow_entry->flow_ip.ipv6.ul[0] << 12; - entry.bf0.ip_addr_4 = flow_entry->flow_ip.ipv6.ul[0] >> 20; - entry.bf0.l4_sport = flow_entry->src_port; - entry.bf0.l4_dport_0 = flow_entry->dst_port; - entry.bf0.l4_dport_1 = flow_entry->dst_port >> 4; - rv = hppe_flow_ipv6_5tuple_add(dev_id, (a_uint32_t)add_mode, &flow_entry->entry_id, &entry); - } else if ((type & FAL_FLOW_IP4_3TUPLE_ADDR) == FAL_FLOW_IP4_3TUPLE_ADDR) { - union in_flow_3tuple_tbl_u entry; - entry.bf0.valid= 1; - entry.bf0.entry_type = FLOW_ENTRY_TYPE_IPV4; - entry.bf0.host_addr_index_type = flow_entry->host_addr_type; - entry.bf0.host_addr_index = flow_entry->host_addr_index; - entry.bf0.protocol_type = flow_entry->protocol; - entry.bf0.age = flow_entry->age; - entry.bf0.src_l3_if_valid = flow_entry->src_intf_valid; - entry.bf0.src_l3_if = flow_entry->src_intf_index; - entry.bf0.fwd_type = flow_entry->fwd_type; - if (flow_entry->fwd_type == FAL_FLOW_SNAT) { - entry.bf0.next_hop1 = flow_entry->snat_nexthop; - } else if (flow_entry->fwd_type == FAL_FLOW_DNAT) { - entry.bf3.next_hop2 = flow_entry->dnat_nexthop; - } else if (flow_entry->fwd_type == FAL_FLOW_ROUTE) { - entry.bf2.next_hop3 = flow_entry->route_nexthop; - entry.bf2.port_vp_valid1= flow_entry->port_valid; - entry.bf2.port_vp1 = flow_entry->route_port & 0xffffff; - } else if (flow_entry->fwd_type == FAL_FLOW_BRIDGE) { - entry.bf1.port_vp2 = flow_entry->bridge_port & 0xffffff; - } - entry.bf0.de_acce = flow_entry->deacclr_en; - entry.bf0.copy_to_cpu_en = flow_entry->copy_tocpu_en; - entry.bf0.syn_toggle = flow_entry->syn_toggle; - entry.bf0.pri_profile_0 = flow_entry->pri_profile; - entry.bf0.pri_profile_1 = flow_entry->pri_profile >> 1; - entry.bf0.service_code = flow_entry->sevice_code; - entry.bf0.ip_addr_0 = flow_entry->flow_ip.ipv4; - entry.bf0.ip_addr_1 = flow_entry->flow_ip.ipv4 >> 20; - entry.bf0.ip_protocol = flow_entry->ip_type; - rv = hppe_flow_ipv4_3tuple_add(dev_id, (a_uint32_t)add_mode, &flow_entry->entry_id, &entry); - } else if ((type & FAL_FLOW_IP6_3TUPLE_ADDR) == FAL_FLOW_IP6_3TUPLE_ADDR) { - union in_flow_ipv6_3tuple_tbl_u entry; - entry.bf0.valid= 1; - entry.bf0.entry_type = FLOW_ENTRY_TYPE_IPV6; - entry.bf0.host_addr_index_type = flow_entry->host_addr_type; - entry.bf0.host_addr_index = flow_entry->host_addr_index; - entry.bf0.protocol_type = flow_entry->protocol; - entry.bf0.age = flow_entry->age; - entry.bf0.src_l3_if_valid = flow_entry->src_intf_valid; - entry.bf0.src_l3_if = flow_entry->src_intf_index; - entry.bf0.fwd_type = flow_entry->fwd_type; - if (flow_entry->fwd_type == FAL_FLOW_SNAT) { - entry.bf1.next_hop1 = flow_entry->snat_nexthop; - } else if (flow_entry->fwd_type == FAL_FLOW_DNAT) { - entry.bf3.next_hop2 = flow_entry->dnat_nexthop; - } else if (flow_entry->fwd_type == FAL_FLOW_ROUTE) { - entry.bf2.next_hop3 = flow_entry->route_nexthop; - entry.bf2.port_vp_valid1= flow_entry->port_valid; - entry.bf2.port_vp1 = flow_entry->route_port & 0xffffff; - } else if (flow_entry->fwd_type == FAL_FLOW_BRIDGE) { - entry.bf0.port_vp2 = flow_entry->bridge_port & 0xffffff; - } - entry.bf0.de_acce = flow_entry->deacclr_en; - entry.bf0.copy_to_cpu_en = flow_entry->copy_tocpu_en; - entry.bf0.syn_toggle = flow_entry->syn_toggle; - entry.bf0.pri_profile_0 = flow_entry->pri_profile; - entry.bf0.pri_profile_1 = flow_entry->pri_profile >> 1; - entry.bf0.service_code = flow_entry->sevice_code; - entry.bf0.ip_addr_0 = flow_entry->flow_ip.ipv6.ul[3]; - entry.bf0.ip_addr_1 = flow_entry->flow_ip.ipv6.ul[3] >> 20 |\ - flow_entry->flow_ip.ipv6.ul[2] << 12; - entry.bf0.ip_addr_2 = flow_entry->flow_ip.ipv6.ul[2] >> 20 |\ - flow_entry->flow_ip.ipv6.ul[1] << 12; - entry.bf0.ip_addr_3 = flow_entry->flow_ip.ipv6.ul[1] >> 20 |\ - flow_entry->flow_ip.ipv6.ul[0] << 12; - entry.bf0.ip_addr_4 = flow_entry->flow_ip.ipv6.ul[0] >> 20; - entry.bf0.ip_protocol = flow_entry->ip_type; - rv = hppe_flow_ipv6_3tuple_add(dev_id, (a_uint32_t)add_mode, &flow_entry->entry_id, &entry); - } else - return SW_FAIL; - if (rv == SW_OK) { - union eg_flow_tree_map_tbl_u eg_treemap; - eg_treemap.bf.tree_id = flow_entry->tree_id; - rv = hppe_eg_flow_tree_map_tbl_set(dev_id, flow_entry->entry_id, &eg_treemap); - } - return rv; -} - -sw_error_t -adpt_hppe_flow_global_cfg_get( - a_uint32_t dev_id, - fal_flow_global_cfg_t *cfg) -{ - sw_error_t rv = SW_OK; -#if defined(CPPE) - a_uint32_t chip_ver = 0; - a_bool_t flow_cpy_escape = A_FALSE; -#endif - union flow_ctrl0_u flow_ctrl0; - union l3_route_ctrl_u route_ctrl; - union l3_route_ctrl_ext_u route_ctrl_ext; - - ADPT_DEV_ID_CHECK(dev_id); - ADPT_NULL_POINT_CHECK(cfg); - - memset(&flow_ctrl0, 0, sizeof(flow_ctrl0)); - memset(&route_ctrl, 0, sizeof(route_ctrl)); - memset(&route_ctrl_ext, 0, sizeof(route_ctrl_ext)); - - rv = hppe_flow_ctrl0_get(dev_id, &flow_ctrl0); - if( rv != SW_OK ) - return rv; - rv = hppe_l3_route_ctrl_get(dev_id, &route_ctrl); - if( rv != SW_OK ) - return rv; - rv = hppe_l3_route_ctrl_ext_get(dev_id, &route_ctrl_ext); - if( rv != SW_OK ) - return rv; - -#if defined(CPPE) - chip_ver = adpt_hppe_chip_revision_get(dev_id); - if (chip_ver == CPPE_REVISION) { - rv = adpt_cppe_flow_copy_escape_get(dev_id, &flow_cpy_escape); - SW_RTN_ON_ERROR(rv); - cfg->flow_mismatch_copy_escape_en = flow_cpy_escape; - } -#endif - - cfg->src_if_check_action= route_ctrl.bf.flow_src_if_check_cmd; - cfg->src_if_check_deacclr_en= route_ctrl.bf.flow_src_if_check_de_acce; - cfg->service_loop_en = route_ctrl_ext.bf.flow_service_code_loop_en; - cfg->service_loop_action = route_ctrl.bf.flow_service_code_loop; - cfg->service_loop_deacclr_en = route_ctrl.bf.flow_service_code_loop_de_acce; - cfg->flow_deacclr_action = route_ctrl.bf.flow_de_acce_cmd; - cfg->sync_mismatch_action = route_ctrl.bf.flow_sync_mismatch_cmd; - cfg->sync_mismatch_deacclr_en = route_ctrl.bf.flow_sync_mismatch_de_acce; - cfg->hash_mode_0 = flow_ctrl0.bf.flow_hash_mode_0; - cfg->hash_mode_1 = flow_ctrl0.bf.flow_hash_mode_1; - - return SW_OK; -} - -sw_error_t -adpt_hppe_flow_global_cfg_set( - a_uint32_t dev_id, - fal_flow_global_cfg_t *cfg) -{ - sw_error_t rv = SW_OK; -#if defined(CPPE) - a_uint32_t chip_ver = 0; -#endif - union flow_ctrl0_u flow_ctrl0; - union l3_route_ctrl_u route_ctrl; - union l3_route_ctrl_ext_u route_ctrl_ext; - - ADPT_DEV_ID_CHECK(dev_id); - ADPT_NULL_POINT_CHECK(cfg); - - memset(&flow_ctrl0, 0, sizeof(flow_ctrl0)); - memset(&route_ctrl, 0, sizeof(route_ctrl)); - memset(&route_ctrl_ext, 0, sizeof(route_ctrl_ext)); - - rv = hppe_flow_ctrl0_get(dev_id, &flow_ctrl0); - SW_RTN_ON_ERROR(rv); - - rv = hppe_l3_route_ctrl_get(dev_id, &route_ctrl); - SW_RTN_ON_ERROR(rv); - - rv = hppe_l3_route_ctrl_ext_get(dev_id, &route_ctrl_ext); - SW_RTN_ON_ERROR(rv); - - route_ctrl.bf.flow_src_if_check_cmd = cfg->src_if_check_action; - route_ctrl.bf.flow_src_if_check_de_acce = cfg->src_if_check_deacclr_en; - route_ctrl_ext.bf.flow_service_code_loop_en = cfg->service_loop_en; - route_ctrl.bf.flow_service_code_loop = cfg->service_loop_action; - route_ctrl.bf.flow_service_code_loop_de_acce = cfg->service_loop_deacclr_en; - route_ctrl.bf.flow_de_acce_cmd = cfg->flow_deacclr_action; - route_ctrl.bf.flow_sync_mismatch_cmd = cfg->sync_mismatch_action; - route_ctrl.bf.flow_sync_mismatch_de_acce = cfg->sync_mismatch_deacclr_en; - flow_ctrl0.bf.flow_hash_mode_0 = cfg->hash_mode_0; - flow_ctrl0.bf.flow_hash_mode_1 = cfg->hash_mode_1; - - rv = hppe_flow_ctrl0_set(dev_id, &flow_ctrl0); - SW_RTN_ON_ERROR(rv); - - rv = hppe_l3_route_ctrl_set(dev_id, &route_ctrl); - SW_RTN_ON_ERROR(rv); - - rv = hppe_l3_route_ctrl_ext_set(dev_id, &route_ctrl_ext); - SW_RTN_ON_ERROR(rv); - -#if defined(CPPE) - chip_ver = adpt_hppe_chip_revision_get(dev_id); - if (chip_ver == CPPE_REVISION) { - rv = adpt_cppe_flow_copy_escape_set(dev_id, - cfg->flow_mismatch_copy_escape_en); - SW_RTN_ON_ERROR(rv); - } -#endif - - return SW_OK; -} -#endif - -void adpt_hppe_flow_func_bitmap_init(a_uint32_t dev_id) -{ - adpt_api_t *p_adpt_api = NULL; - - p_adpt_api = adpt_api_ptr_get(dev_id); - - if(p_adpt_api == NULL) - return; - - p_adpt_api->adpt_flow_func_bitmap = 0; - return; -} - -static void adpt_hppe_flow_func_unregister(a_uint32_t dev_id, adpt_api_t *p_adpt_api) -{ - if(p_adpt_api == NULL) - return; - - p_adpt_api->adpt_flow_host_add = NULL; - p_adpt_api->adpt_flow_entry_get = NULL; - p_adpt_api->adpt_flow_entry_del = NULL; - p_adpt_api->adpt_flow_status_get = NULL; - p_adpt_api->adpt_flow_ctrl_set = NULL; - p_adpt_api->adpt_flow_age_timer_get = NULL; - p_adpt_api->adpt_flow_status_set = NULL; - p_adpt_api->adpt_flow_host_get = NULL; - p_adpt_api->adpt_flow_host_del = NULL; - p_adpt_api->adpt_flow_ctrl_get = NULL; - p_adpt_api->adpt_flow_age_timer_set = NULL; - p_adpt_api->adpt_flow_entry_add = NULL; - p_adpt_api->adpt_flow_global_cfg_get = NULL; - p_adpt_api->adpt_flow_global_cfg_set = NULL; - p_adpt_api->adpt_flow_entry_next = NULL; - - return; -} - -sw_error_t adpt_hppe_flow_init(a_uint32_t dev_id) -{ - adpt_api_t *p_adpt_api = NULL; - - p_adpt_api = adpt_api_ptr_get(dev_id); - - if(p_adpt_api == NULL) - return SW_FAIL; - - adpt_hppe_flow_func_unregister(dev_id, p_adpt_api); - -#ifndef IN_FLOW_MINI - if (p_adpt_api->adpt_flow_func_bitmap & (1 << FUNC_FLOW_HOST_ADD)) - p_adpt_api->adpt_flow_host_add = adpt_hppe_flow_host_add; - if (p_adpt_api->adpt_flow_func_bitmap & (1 << FUNC_FLOW_ENTRY_GET)) - p_adpt_api->adpt_flow_entry_get = adpt_hppe_flow_entry_get; - if (p_adpt_api->adpt_flow_func_bitmap & (1 << FUNC_FLOW_ENTRY_DEL)) - p_adpt_api->adpt_flow_entry_del = adpt_hppe_flow_entry_del; - if (p_adpt_api->adpt_flow_func_bitmap & (1 << FUNC_FLOW_STATUS_GET)) - p_adpt_api->adpt_flow_status_get = adpt_hppe_flow_status_get; - if (p_adpt_api->adpt_flow_func_bitmap & (1 << FUNC_FLOW_AGE_TIMER_GET)) - p_adpt_api->adpt_flow_age_timer_get = adpt_hppe_flow_age_timer_get; - if (p_adpt_api->adpt_flow_func_bitmap & (1 << FUNC_FLOW_STATUS_SET)) - p_adpt_api->adpt_flow_status_set = adpt_hppe_flow_status_set; - if (p_adpt_api->adpt_flow_func_bitmap & (1 << FUNC_FLOW_HOST_GET)) - p_adpt_api->adpt_flow_host_get = adpt_hppe_flow_host_get; - if (p_adpt_api->adpt_flow_func_bitmap & (1 << FUNC_FLOW_HOST_DEL)) - p_adpt_api->adpt_flow_host_del = adpt_hppe_flow_host_del; - if (p_adpt_api->adpt_flow_func_bitmap & (1 << FUNC_FLOW_AGE_TIMER_SET)) - p_adpt_api->adpt_flow_age_timer_set = adpt_hppe_flow_age_timer_set; - if (p_adpt_api->adpt_flow_func_bitmap & (1 << FUNC_FLOW_ENTRY_ADD)) - p_adpt_api->adpt_flow_entry_add = adpt_hppe_flow_entry_add; - if (p_adpt_api->adpt_flow_func_bitmap & (1 << FUNC_FLOW_GLOBAL_CFG_GET)) - p_adpt_api->adpt_flow_global_cfg_get = adpt_hppe_flow_global_cfg_get; - if (p_adpt_api->adpt_flow_func_bitmap & (1 << FUNC_FLOW_GLOBAL_CFG_SET)) - p_adpt_api->adpt_flow_global_cfg_set = adpt_hppe_flow_global_cfg_set; - if (p_adpt_api->adpt_flow_func_bitmap & (1 << FUNC_FLOW_ENTRY_NEXT)) - p_adpt_api->adpt_flow_entry_next = adpt_hppe_flow_entry_next; -#endif - if (p_adpt_api->adpt_flow_func_bitmap & (1 << FUNC_FLOW_CTRL_GET)) - p_adpt_api->adpt_flow_ctrl_get = adpt_hppe_flow_ctrl_get; - if (p_adpt_api->adpt_flow_func_bitmap & (1 << FUNC_FLOW_CTRL_SET)) - p_adpt_api->adpt_flow_ctrl_set = adpt_hppe_flow_ctrl_set; - - return SW_OK; -} - -/** - * @} - */ diff --git a/feeds/ipq807x/qca-ssdk/src/src/adpt/hppe/adpt_hppe_ip.c b/feeds/ipq807x/qca-ssdk/src/src/adpt/hppe/adpt_hppe_ip.c deleted file mode 100755 index f4a40dd50..000000000 --- a/feeds/ipq807x/qca-ssdk/src/src/adpt/hppe/adpt_hppe_ip.c +++ /dev/null @@ -1,1355 +0,0 @@ -/* - * Copyright (c) 2016-2017, The Linux Foundation. All rights reserved. - * Permission to use, copy, modify, and/or distribute this software for - * any purpose with or without fee is hereby granted, provided that the - * above copyright notice and this permission notice appear in all copies. - * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES - * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR - * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES - * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN - * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT - * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. - */ - - -/** - * @defgroup - * @{ - */ -#include "sw.h" -#include "fal_ip.h" -#include "hppe_ip_reg.h" -#include "hppe_ip.h" -#include "adpt.h" - -#ifndef IN_IP_MINI -sw_error_t -adpt_hppe_ip_network_route_get(a_uint32_t dev_id, - a_uint32_t index, a_uint8_t type, - fal_network_route_entry_t *entry) -{ - sw_error_t rv = SW_OK; - union network_route_ip_u network_route_ip; - union network_route_ip_ext_u network_route_ip_ext; - union network_route_action_u network_route_action; - fal_ip6_addr_t ipv6, ipv6_mask; - - ADPT_DEV_ID_CHECK(dev_id); - ADPT_NULL_POINT_CHECK(entry); - memset(&network_route_ip, 0, sizeof(network_route_ip)); - memset(&network_route_ip_ext, 0, sizeof(network_route_ip_ext)); - memset(&network_route_action, 0, sizeof(network_route_action)); - - if (type > 1 || (type == 0 && index > 31) || (type == 1 && index > 7)) - return SW_BAD_VALUE; - - if (type == 0) { - rv = hppe_network_route_ip_get(dev_id, index, - &network_route_ip); - if( rv != SW_OK ) - return rv; - rv = hppe_network_route_ip_ext_get(dev_id, index, - &network_route_ip_ext); - if( rv != SW_OK ) - return rv; - rv = hppe_network_route_action_get(dev_id, index, - &network_route_action); - if( rv != SW_OK ) - return rv; - } else { - rv = hppe_network_route_ip_get(dev_id, index * 4, &network_route_ip); - if( rv != SW_OK ) - return rv; - ipv6.ul[3] = network_route_ip.val[0]; - ipv6.ul[2] = network_route_ip.val[1]; - rv = hppe_network_route_ip_get(dev_id, index * 4 + 1, &network_route_ip); - if( rv != SW_OK ) - return rv; - ipv6.ul[1] = network_route_ip.val[0]; - ipv6.ul[0] = network_route_ip.val[1]; - rv = hppe_network_route_ip_get(dev_id, index * 4 + 2, &network_route_ip); - if( rv != SW_OK ) - return rv; - ipv6_mask.ul[3] = network_route_ip.val[0]; - ipv6_mask.ul[2] = network_route_ip.val[1]; - rv = hppe_network_route_ip_get(dev_id, index * 4 + 3, &network_route_ip); - if( rv != SW_OK ) - return rv; - ipv6_mask.ul[1] = network_route_ip.val[0]; - ipv6_mask.ul[0] = network_route_ip.val[1]; - rv = hppe_network_route_ip_ext_get(dev_id, index * 4, - &network_route_ip_ext); - if( rv != SW_OK ) - return rv; - rv = hppe_network_route_action_get(dev_id, index * 4, - &network_route_action); - if( rv != SW_OK ) - return rv; - } - - if (!network_route_ip_ext.bf.valid) - return SW_FAIL; - entry->action = (fal_fwd_cmd_t)network_route_action.bf.fwd_cmd; - entry->lan_wan = network_route_action.bf.lan_wan; - entry->dst_info = network_route_action.bf.dst_info; - entry->type = network_route_ip_ext.bf.entry_type; - if (type == 0) { - entry->route_addr.ip4_addr = network_route_ip.bf.ip_addr; - entry->route_addr_mask.ip4_addr_mask = network_route_ip.bf.ip_addr_mask; - } else { - memcpy(&entry->route_addr.ip6_addr , &ipv6, sizeof(ipv6)); - memcpy(&entry->route_addr_mask.ip6_addr_mask, - &ipv6_mask, sizeof(ipv6_mask)); - } - - return SW_OK; -} - -sw_error_t -adpt_hppe_ip_host_add(a_uint32_t dev_id, fal_host_entry_t * host_entry) -{ - a_uint8_t mode = 0, type = 0; - sw_error_t rv = SW_OK; - ADPT_DEV_ID_CHECK(dev_id); - ADPT_NULL_POINT_CHECK(host_entry); - - mode = host_entry->flags >> 24; - type = host_entry->flags & 0xff; - - if ((type & FAL_IP_IP4_ADDR) == FAL_IP_IP4_ADDR) { - union host_tbl_u entry; - entry.bf.valid= host_entry->status; - entry.bf.key_type = 0; - entry.bf.fwd_cmd = host_entry->action; - entry.bf.syn_toggle = host_entry->syn_toggle; - entry.bf.dst_info = host_entry->dst_info; - entry.bf.lan_wan = host_entry->lan_wan; - entry.bf.ip_addr = host_entry->ip4_addr; - rv = hppe_host_ipv4_add(dev_id, (a_uint32_t)mode, &host_entry->entry_id, &entry); - } else if ((type & FAL_IP_IP6_ADDR) == FAL_IP_IP6_ADDR) { - union host_ipv6_tbl_u entry; - entry.bf.valid= host_entry->status; - entry.bf.key_type = 2; - entry.bf.fwd_cmd = host_entry->action; - entry.bf.syn_toggle = host_entry->syn_toggle; - entry.bf.dst_info = host_entry->dst_info; - entry.bf.lan_wan = host_entry->lan_wan; - entry.bf.ipv6_addr_0 = host_entry->ip6_addr.ul[3]; - entry.bf.ipv6_addr_1 = host_entry->ip6_addr.ul[3] >> 10 | \ - host_entry->ip6_addr.ul[2] << 22; - entry.bf.ipv6_addr_2 = host_entry->ip6_addr.ul[2] >> 10 | \ - host_entry->ip6_addr.ul[1] << 22; - entry.bf.ipv6_addr_3 = host_entry->ip6_addr.ul[1] >> 10 | \ - host_entry->ip6_addr.ul[0] << 22; - entry.bf.ipv6_addr_4 = host_entry->ip6_addr.ul[0] >> 10; - rv = hppe_host_ipv6_add(dev_id, (a_uint32_t)mode, &host_entry->entry_id, &entry); - } else if ((type & FAL_IP_IP4_ADDR_MCAST) == FAL_IP_IP4_ADDR_MCAST) { - union host_ipv4_mcast_tbl_u entry; - entry.bf.valid= host_entry->status; - entry.bf.key_type = 1; - entry.bf.fwd_cmd = host_entry->action; - entry.bf.syn_toggle = host_entry->syn_toggle; - entry.bf.dst_info = host_entry->dst_info; - entry.bf.lan_wan = host_entry->lan_wan; - entry.bf.gip_addr_0 = host_entry->ip4_addr; - entry.bf.gip_addr_1 = host_entry->ip4_addr >> 11; - entry.bf.vsi = host_entry->mcast_info.vsi; - entry.bf.sip_addr_0 = host_entry->mcast_info.sip4_addr; - entry.bf.sip_addr_1 = host_entry->mcast_info.sip4_addr >> 11; - rv = hppe_host_ipv4_mcast_add(dev_id, (a_uint32_t)mode, &host_entry->entry_id, &entry); - } else if ((type & FAL_IP_IP6_ADDR_MCAST) == FAL_IP_IP6_ADDR_MCAST) { - union host_ipv6_mcast_tbl_u entry; - entry.bf.valid= host_entry->status; - entry.bf.key_type = 3; - entry.bf.fwd_cmd = host_entry->action; - entry.bf.syn_toggle = host_entry->syn_toggle; - entry.bf.dst_info = host_entry->dst_info; - entry.bf.lan_wan = host_entry->lan_wan; - entry.bf.gipv6_addr_0 = host_entry->ip6_addr.ul[3]; - entry.bf.gipv6_addr_1 = host_entry->ip6_addr.ul[3] >> 20 | \ - host_entry->ip6_addr.ul[2] << 12; - entry.bf.gipv6_addr_2 = host_entry->ip6_addr.ul[2] >> 20 | \ - host_entry->ip6_addr.ul[1] << 12; - entry.bf.gipv6_addr_3 = host_entry->ip6_addr.ul[1] >> 20 | \ - host_entry->ip6_addr.ul[0] << 12; - entry.bf.gipv6_addr_4 = host_entry->ip6_addr.ul[0] >> 20; - entry.bf.vsi = host_entry->mcast_info.vsi; - entry.bf.sipv6_addr_0 = host_entry->mcast_info.sip6_addr.ul[3]; - entry.bf.sipv6_addr_1 = host_entry->mcast_info.sip6_addr.ul[3] >> 20 | \ - host_entry->mcast_info.sip6_addr.ul[2] << 12; - entry.bf.sipv6_addr_2 = host_entry->mcast_info.sip6_addr.ul[2] >> 20 | \ - host_entry->mcast_info.sip6_addr.ul[1] << 12; - entry.bf.sipv6_addr_3 = host_entry->mcast_info.sip6_addr.ul[1] >> 20 | \ - host_entry->mcast_info.sip6_addr.ul[0] << 12; - entry.bf.sipv6_addr_4 = host_entry->mcast_info.sip6_addr.ul[0] >> 20; - rv = hppe_host_ipv6_mcast_add(dev_id, (a_uint32_t)mode, &host_entry->entry_id, &entry); - } - return rv; -} -sw_error_t -adpt_hppe_ip_vsi_sg_cfg_get(a_uint32_t dev_id, a_uint32_t vsi, - fal_sg_cfg_t *sg_cfg) -{ - sw_error_t rv = SW_OK; - union l3_vsi_ext_u l3_vsi_ext; - - ADPT_DEV_ID_CHECK(dev_id); - ADPT_NULL_POINT_CHECK(sg_cfg); - memset(&l3_vsi_ext, 0, sizeof(l3_vsi_ext)); - - rv = hppe_l3_vsi_ext_get(dev_id, vsi, &l3_vsi_ext); - if( rv != SW_OK ) - return rv; - - sg_cfg->ipv4_sg_en = l3_vsi_ext.bf.ipv4_sg_en; - sg_cfg->ipv4_sg_vio_action = l3_vsi_ext.bf.ipv4_sg_vio_cmd; - sg_cfg->ipv4_sg_port_en = l3_vsi_ext.bf.ipv4_sg_port_en; - sg_cfg->ipv4_sg_svlan_en = l3_vsi_ext.bf.ipv4_sg_svlan_en; - sg_cfg->ipv4_sg_cvlan_en = l3_vsi_ext.bf.ipv4_sg_cvlan_en; - sg_cfg->ipv4_src_unk_action = l3_vsi_ext.bf.ipv4_src_unk_cmd; - sg_cfg->ipv6_sg_en = l3_vsi_ext.bf.ipv6_sg_en; - sg_cfg->ipv6_sg_vio_action = l3_vsi_ext.bf.ipv6_sg_vio_cmd; - sg_cfg->ipv6_sg_port_en = l3_vsi_ext.bf.ipv6_sg_port_en; - sg_cfg->ipv6_sg_svlan_en = l3_vsi_ext.bf.ipv6_sg_svlan_en; - sg_cfg->ipv6_sg_cvlan_en = l3_vsi_ext.bf.ipv6_sg_cvlan_en; - sg_cfg->ipv6_src_unk_action = l3_vsi_ext.bf.ipv6_src_unk_cmd; - - return SW_OK; -} - -sw_error_t -adpt_hppe_ip_port_sg_cfg_set(a_uint32_t dev_id, fal_port_t port_id, - fal_sg_cfg_t *sg_cfg) -{ - union l3_vp_port_tbl_u l3_vp_port_tbl; - - memset(&l3_vp_port_tbl, 0, sizeof(l3_vp_port_tbl)); - ADPT_DEV_ID_CHECK(dev_id); - - hppe_l3_vp_port_tbl_get(dev_id, port_id, &l3_vp_port_tbl); - - l3_vp_port_tbl.bf.ipv4_sg_en = sg_cfg->ipv4_sg_en; - l3_vp_port_tbl.bf.ipv4_sg_vio_cmd = sg_cfg->ipv4_sg_vio_action; - l3_vp_port_tbl.bf.ipv4_sg_port_en = sg_cfg->ipv4_sg_port_en; - l3_vp_port_tbl.bf.ipv4_sg_svlan_en = sg_cfg->ipv4_sg_svlan_en; - l3_vp_port_tbl.bf.ipv4_sg_cvlan_en = sg_cfg->ipv4_sg_cvlan_en; - l3_vp_port_tbl.bf.ipv4_src_unk_cmd = sg_cfg->ipv4_src_unk_action; - l3_vp_port_tbl.bf.ipv6_sg_en = sg_cfg->ipv6_sg_en; - l3_vp_port_tbl.bf.ipv6_sg_vio_cmd = sg_cfg->ipv6_sg_vio_action; - l3_vp_port_tbl.bf.ipv6_sg_port_en = sg_cfg->ipv6_sg_port_en; - l3_vp_port_tbl.bf.ipv6_sg_svlan_en = sg_cfg->ipv6_sg_svlan_en; - l3_vp_port_tbl.bf.ipv6_sg_cvlan_en = sg_cfg->ipv6_sg_cvlan_en; - l3_vp_port_tbl.bf.ipv6_src_unk_cmd = sg_cfg->ipv6_src_unk_action; - - return hppe_l3_vp_port_tbl_set(dev_id, port_id, &l3_vp_port_tbl); -} -sw_error_t -adpt_hppe_ip_port_intf_get(a_uint32_t dev_id, fal_port_t port_id, fal_intf_id_t *id) -{ - sw_error_t rv = SW_OK; - union l3_vp_port_tbl_u l3_vp_port_tbl; - - memset(&l3_vp_port_tbl, 0, sizeof(l3_vp_port_tbl)); - ADPT_DEV_ID_CHECK(dev_id); - ADPT_NULL_POINT_CHECK(id); - - rv = hppe_l3_vp_port_tbl_get(dev_id, port_id, &l3_vp_port_tbl); - if( rv != SW_OK ) - return rv; - - id->l3_if_valid = l3_vp_port_tbl.bf.l3_if_valid; - id->l3_if_index = l3_vp_port_tbl.bf.l3_if_index; - - return SW_OK; -} - -sw_error_t -adpt_hppe_ip_vsi_arp_sg_cfg_set(a_uint32_t dev_id, a_uint32_t vsi, - fal_arp_sg_cfg_t *arp_sg_cfg) -{ - union l3_vsi_ext_u l3_vsi_ext; - - memset(&l3_vsi_ext, 0, sizeof(l3_vsi_ext)); - ADPT_DEV_ID_CHECK(dev_id); - - hppe_l3_vsi_ext_get(dev_id, vsi, &l3_vsi_ext); - - l3_vsi_ext.bf.ip_arp_sg_en = arp_sg_cfg->ipv4_arp_sg_en; - l3_vsi_ext.bf.ip_arp_sg_vio_cmd = arp_sg_cfg->ipv4_arp_sg_vio_action; - l3_vsi_ext.bf.ip_arp_sg_port_en = arp_sg_cfg->ipv4_arp_sg_port_en; - l3_vsi_ext.bf.ip_arp_sg_svlan_en = arp_sg_cfg->ipv4_arp_sg_svlan_en; - l3_vsi_ext.bf.ip_arp_sg_cvlan_en = arp_sg_cfg->ipv4_arp_sg_cvlan_en; - l3_vsi_ext.bf.ip_arp_src_unk_cmd = arp_sg_cfg->ipv4_arp_src_unk_action; - l3_vsi_ext.bf.ip_nd_sg_en = arp_sg_cfg->ip_nd_sg_en; - l3_vsi_ext.bf.ip_nd_sg_vio_cmd = arp_sg_cfg->ip_nd_sg_vio_action; - l3_vsi_ext.bf.ip_nd_sg_port_en = arp_sg_cfg->ip_nd_sg_port_en; - l3_vsi_ext.bf.ip_nd_sg_svlan_en = arp_sg_cfg->ip_nd_sg_svlan_en; - l3_vsi_ext.bf.ip_nd_sg_cvlan_en = arp_sg_cfg->ip_nd_sg_cvlan_en; - l3_vsi_ext.bf.ip_nd_src_unk_cmd = arp_sg_cfg->ip_nd_src_unk_action; - - return hppe_l3_vsi_ext_set(dev_id, vsi, &l3_vsi_ext); -} -sw_error_t -adpt_hppe_ip_pub_addr_get(a_uint32_t dev_id, - a_uint32_t index, fal_ip_pub_addr_t *entry) -{ - sw_error_t rv = SW_OK; - union in_pub_ip_addr_tbl_u in_pub_ip_addr_tbl; - - memset(&in_pub_ip_addr_tbl, 0, sizeof(in_pub_ip_addr_tbl)); - ADPT_DEV_ID_CHECK(dev_id); - ADPT_NULL_POINT_CHECK(entry); - - rv = hppe_in_pub_ip_addr_tbl_get(dev_id, index, &in_pub_ip_addr_tbl); - if( rv != SW_OK ) - return rv; - - entry->pub_ip_addr = in_pub_ip_addr_tbl.bf.ip_addr; - return SW_OK; -} - -sw_error_t -adpt_hppe_ip_port_intf_set(a_uint32_t dev_id, fal_port_t port_id, fal_intf_id_t *id) -{ - union l3_vp_port_tbl_u l3_vp_port_tbl; - - memset(&l3_vp_port_tbl, 0, sizeof(l3_vp_port_tbl)); - ADPT_DEV_ID_CHECK(dev_id); - - hppe_l3_vp_port_tbl_get(dev_id, port_id, &l3_vp_port_tbl); - - l3_vp_port_tbl.bf.l3_if_valid = id->l3_if_valid; - l3_vp_port_tbl.bf.l3_if_index = id->l3_if_index; - - return hppe_l3_vp_port_tbl_set(dev_id, port_id, &l3_vp_port_tbl); -} - -sw_error_t -adpt_hppe_ip_vsi_sg_cfg_set(a_uint32_t dev_id, a_uint32_t vsi, - fal_sg_cfg_t *sg_cfg) -{ - union l3_vsi_ext_u l3_vsi_ext; - - memset(&l3_vsi_ext, 0, sizeof(l3_vsi_ext)); - ADPT_DEV_ID_CHECK(dev_id); - - hppe_l3_vsi_ext_get(dev_id, vsi, &l3_vsi_ext); - - l3_vsi_ext.bf.ipv4_sg_en = sg_cfg->ipv4_sg_en; - l3_vsi_ext.bf.ipv4_sg_vio_cmd = sg_cfg->ipv4_sg_vio_action; - l3_vsi_ext.bf.ipv4_sg_port_en = sg_cfg->ipv4_sg_port_en; - l3_vsi_ext.bf.ipv4_sg_svlan_en = sg_cfg->ipv4_sg_svlan_en; - l3_vsi_ext.bf.ipv4_sg_cvlan_en = sg_cfg->ipv4_sg_cvlan_en; - l3_vsi_ext.bf.ipv4_src_unk_cmd = sg_cfg->ipv4_src_unk_action; - l3_vsi_ext.bf.ipv6_sg_en = sg_cfg->ipv6_sg_en; - l3_vsi_ext.bf.ipv6_sg_vio_cmd = sg_cfg->ipv6_sg_vio_action; - l3_vsi_ext.bf.ipv6_sg_port_en = sg_cfg->ipv6_sg_port_en; - l3_vsi_ext.bf.ipv6_sg_svlan_en = sg_cfg->ipv6_sg_svlan_en; - l3_vsi_ext.bf.ipv6_sg_cvlan_en = sg_cfg->ipv6_sg_cvlan_en; - l3_vsi_ext.bf.ipv6_src_unk_cmd = sg_cfg->ipv6_src_unk_action; - - return hppe_l3_vsi_ext_set(dev_id, vsi, &l3_vsi_ext); -} -sw_error_t -adpt_hppe_ip_port_macaddr_set(a_uint32_t dev_id, fal_port_t port_id, - fal_macaddr_entry_t *macaddr) -{ - union l3_vp_port_tbl_u l3_vp_port_tbl; - - memset(&l3_vp_port_tbl, 0, sizeof(l3_vp_port_tbl)); - ADPT_DEV_ID_CHECK(dev_id); - - hppe_l3_vp_port_tbl_get(dev_id, port_id, &l3_vp_port_tbl); - - l3_vp_port_tbl.bf.mac_valid = macaddr->valid; - l3_vp_port_tbl.bf.mac_da_0 = macaddr->mac_addr.uc[4] << 8 | \ - macaddr->mac_addr.uc[5]; - l3_vp_port_tbl.bf.mac_da_1 = macaddr->mac_addr.uc[0] << 24 | \ - macaddr->mac_addr.uc[1] << 16 | \ - macaddr->mac_addr.uc[2] << 8 | \ - macaddr->mac_addr.uc[3]; - - return hppe_l3_vp_port_tbl_set(dev_id, port_id, &l3_vp_port_tbl); -} -sw_error_t -adpt_hppe_ip_vsi_intf_get(a_uint32_t dev_id, a_uint32_t vsi, fal_intf_id_t *id) -{ - sw_error_t rv = SW_OK; - union l3_vsi_u l3_vsi; - - memset(&l3_vsi, 0, sizeof(l3_vsi)); - ADPT_DEV_ID_CHECK(dev_id); - ADPT_NULL_POINT_CHECK(id); - - - rv = hppe_l3_vsi_get(dev_id, vsi, &l3_vsi); - - if( rv != SW_OK ) - return rv; - - id->l3_if_valid = l3_vsi.bf.l3_if_valid; - id->l3_if_index = l3_vsi.bf.l3_if_index; - - return SW_OK; -} - -sw_error_t -adpt_hppe_ip_network_route_add(a_uint32_t dev_id, - a_uint32_t index, - fal_network_route_entry_t *entry) -{ - union network_route_ip_u network_route_ip; - union network_route_ip_ext_u network_route_ip_ext; - union network_route_action_u network_route_action; - - memset(&network_route_ip, 0, sizeof(network_route_ip)); - memset(&network_route_ip_ext, 0, sizeof(network_route_ip_ext)); - memset(&network_route_action, 0, sizeof(network_route_action)); - ADPT_DEV_ID_CHECK(dev_id); - ADPT_NULL_POINT_CHECK(entry); - - if (entry->type > 1 || (entry->type == 0 && index > 31) || (entry->type == 1 && index > 7)) - return SW_BAD_VALUE; - - if (entry->type == 0) { - network_route_ip.bf.ip_addr = entry->route_addr.ip4_addr; - network_route_ip.bf.ip_addr_mask = entry->route_addr_mask.ip4_addr_mask; - network_route_ip_ext.bf.valid = 1; - network_route_ip_ext.bf.entry_type = entry->type; - network_route_action.bf.dst_info = entry->dst_info; - network_route_action.bf.fwd_cmd = entry->action; - network_route_action.bf.lan_wan = entry->lan_wan; - hppe_network_route_ip_set(dev_id, index, &network_route_ip); - hppe_network_route_ip_ext_set(dev_id, index, &network_route_ip_ext); - hppe_network_route_action_set(dev_id, index, &network_route_action); - } else { - network_route_ip_ext.bf.valid = 1; - network_route_ip_ext.bf.entry_type = entry->type; - network_route_action.bf.dst_info = entry->dst_info; - network_route_action.bf.fwd_cmd = entry->action; - network_route_action.bf.lan_wan = entry->lan_wan; - hppe_network_route_ip_ext_set(dev_id, index * 4, &network_route_ip_ext); - hppe_network_route_action_set(dev_id, index * 4, &network_route_action); - network_route_ip.bf.ip_addr = entry->route_addr.ip6_addr.ul[3]; - network_route_ip.bf.ip_addr_mask = entry->route_addr.ip6_addr.ul[2]; - hppe_network_route_ip_set(dev_id, index * 4, &network_route_ip); - network_route_ip.bf.ip_addr = entry->route_addr.ip6_addr.ul[1]; - network_route_ip.bf.ip_addr_mask = entry->route_addr.ip6_addr.ul[0]; - hppe_network_route_ip_set(dev_id, index * 4 + 1, &network_route_ip); - network_route_ip.bf.ip_addr = entry->route_addr_mask.ip6_addr_mask.ul[3]; - network_route_ip.bf.ip_addr_mask = entry->route_addr_mask.ip6_addr_mask.ul[2]; - hppe_network_route_ip_set(dev_id, index * 4 + 2, &network_route_ip); - network_route_ip.bf.ip_addr = entry->route_addr_mask.ip6_addr_mask.ul[1]; - network_route_ip.bf.ip_addr_mask = entry->route_addr_mask.ip6_addr_mask.ul[0]; - hppe_network_route_ip_set(dev_id, index * 4 + 3, &network_route_ip); - } - return SW_OK; -} - -sw_error_t -adpt_hppe_ip_network_route_del(a_uint32_t dev_id, - a_uint32_t index, a_uint8_t type) -{ - union network_route_ip_u network_route_ip; - union network_route_ip_ext_u network_route_ip_ext; - union network_route_action_u network_route_action; - - memset(&network_route_ip, 0, sizeof(network_route_ip)); - memset(&network_route_ip_ext, 0, sizeof(network_route_ip_ext)); - memset(&network_route_action, 0, sizeof(network_route_action)); - ADPT_DEV_ID_CHECK(dev_id); - - if (type > 1 || (type == 0 && index > 31) || (type == 1 && index > 7)) - return SW_BAD_VALUE; - - network_route_ip_ext.bf.valid = 0; - if (type == 0) { - hppe_network_route_ip_ext_set(dev_id, index, &network_route_ip_ext); - } else { - hppe_network_route_ip_ext_set(dev_id, index * 4, &network_route_ip_ext); - } - return SW_OK; -} - -sw_error_t -adpt_hppe_ip_port_sg_cfg_get(a_uint32_t dev_id, fal_port_t port_id, - fal_sg_cfg_t *sg_cfg) -{ - sw_error_t rv = SW_OK; - union l3_vp_port_tbl_u l3_vp_port_tbl; - - memset(&l3_vp_port_tbl, 0, sizeof(l3_vp_port_tbl)); - ADPT_DEV_ID_CHECK(dev_id); - ADPT_NULL_POINT_CHECK(sg_cfg); - - rv = hppe_l3_vp_port_tbl_get(dev_id, port_id, &l3_vp_port_tbl); - if( rv != SW_OK ) - return rv; - - sg_cfg->ipv4_sg_en = l3_vp_port_tbl.bf.ipv4_sg_en; - sg_cfg->ipv4_sg_vio_action= l3_vp_port_tbl.bf.ipv4_sg_vio_cmd; - sg_cfg->ipv4_sg_port_en = l3_vp_port_tbl.bf.ipv4_sg_port_en; - sg_cfg->ipv4_sg_svlan_en = l3_vp_port_tbl.bf.ipv4_sg_svlan_en; - sg_cfg->ipv4_sg_cvlan_en = l3_vp_port_tbl.bf.ipv4_sg_cvlan_en; - sg_cfg->ipv4_src_unk_action = l3_vp_port_tbl.bf.ipv4_src_unk_cmd; - sg_cfg->ipv6_sg_en = l3_vp_port_tbl.bf.ipv6_sg_en; - sg_cfg->ipv6_sg_vio_action = l3_vp_port_tbl.bf.ipv6_sg_vio_cmd; - sg_cfg->ipv6_sg_port_en = l3_vp_port_tbl.bf.ipv6_sg_port_en; - sg_cfg->ipv6_sg_svlan_en = l3_vp_port_tbl.bf.ipv6_sg_svlan_en; - sg_cfg->ipv6_sg_cvlan_en = l3_vp_port_tbl.bf.ipv6_sg_cvlan_en; - sg_cfg->ipv6_src_unk_action = l3_vp_port_tbl.bf.ipv6_src_unk_cmd; - - return SW_OK; -} - -sw_error_t -adpt_hppe_ip_intf_get( - a_uint32_t dev_id, - a_uint32_t index, - fal_intf_entry_t *entry) -{ - sw_error_t rv = SW_OK; - union in_l3_if_tbl_u in_l3_if_tbl; - union eg_l3_if_tbl_u eg_l3_if_tbl; - - memset(&in_l3_if_tbl, 0, sizeof(in_l3_if_tbl)); - memset(&eg_l3_if_tbl, 0, sizeof(eg_l3_if_tbl)); - ADPT_DEV_ID_CHECK(dev_id); - ADPT_NULL_POINT_CHECK(entry); - - rv = hppe_in_l3_if_tbl_get(dev_id, index, &in_l3_if_tbl); - if( rv != SW_OK ) - return rv; - rv = hppe_eg_l3_if_tbl_get(dev_id, index, &eg_l3_if_tbl); - if( rv != SW_OK ) - return rv; - - entry->mru = in_l3_if_tbl.bf.mru; - entry->mtu = in_l3_if_tbl.bf.mtu; - entry->ttl_dec_bypass_en = in_l3_if_tbl.bf.ttl_dec_bypass; - entry->ipv4_uc_route_en = in_l3_if_tbl.bf.ipv4_uc_route_en; - entry->ipv6_uc_route_en = in_l3_if_tbl.bf.ipv6_uc_route_en; - entry->icmp_trigger_en = in_l3_if_tbl.bf.icmp_trigger_en; - entry->ttl_exceed_action = in_l3_if_tbl.bf.ttl_exceed_cmd; - entry->ttl_exceed_deacclr_en = in_l3_if_tbl.bf.ttl_exceed_de_acce; - entry->mac_addr_bitmap = in_l3_if_tbl.bf.mac_bitmap; - entry->mac_addr.uc[5] = eg_l3_if_tbl.bf.mac_addr_0; - entry->mac_addr.uc[4] = eg_l3_if_tbl.bf.mac_addr_0 >> 8; - entry->mac_addr.uc[3] = eg_l3_if_tbl.bf.mac_addr_0 >> 16; - entry->mac_addr.uc[2] = eg_l3_if_tbl.bf.mac_addr_0 >> 24; - entry->mac_addr.uc[1] = eg_l3_if_tbl.bf.mac_addr_1; - entry->mac_addr.uc[0] = eg_l3_if_tbl.bf.mac_addr_1 >> 8; - - if (rv == SW_OK) { - union rt_interface_cnt_tbl_u cnt_ingress, cnt_egress; - hppe_rt_interface_cnt_tbl_get(dev_id, index, &cnt_ingress); - hppe_rt_interface_cnt_tbl_get(dev_id, index + 256, &cnt_egress); - entry->counter.rx_pkt_counter = cnt_ingress.bf.pkt_cnt; - entry->counter.rx_byte_counter = cnt_ingress.bf.byte_cnt_0 | ((a_uint64_t)cnt_ingress.bf.byte_cnt_1 << 32); - entry->counter.rx_drop_pkt_counter = cnt_ingress.bf.drop_pkt_cnt_0 | (cnt_ingress.bf.drop_pkt_cnt_1 << 24); - entry->counter.rx_drop_byte_counter = cnt_ingress.bf.drop_byte_cnt_0 | \ - ((a_uint64_t)cnt_ingress.bf.drop_byte_cnt_1 << 24); - - entry->counter.tx_pkt_counter = cnt_egress.bf.pkt_cnt; - entry->counter.tx_byte_counter = cnt_egress.bf.byte_cnt_0 | ((a_uint64_t)cnt_egress.bf.byte_cnt_1 << 32); - entry->counter.tx_drop_pkt_counter = cnt_egress.bf.drop_pkt_cnt_0 | (cnt_egress.bf.drop_pkt_cnt_1 << 24); - entry->counter.tx_drop_byte_counter = cnt_egress.bf.drop_byte_cnt_0 | \ - ((a_uint64_t)cnt_egress.bf.drop_byte_cnt_1 << 24); - } - - return SW_OK; -} - -sw_error_t -adpt_hppe_ip_pub_addr_set(a_uint32_t dev_id, - a_uint32_t index, fal_ip_pub_addr_t *entry) -{ - union in_pub_ip_addr_tbl_u in_pub_ip_addr_tbl; - - memset(&in_pub_ip_addr_tbl, 0, sizeof(in_pub_ip_addr_tbl)); - ADPT_DEV_ID_CHECK(dev_id); - ADPT_NULL_POINT_CHECK(entry); - - in_pub_ip_addr_tbl.bf.ip_addr = entry->pub_ip_addr; - return hppe_in_pub_ip_addr_tbl_set(dev_id, index, &in_pub_ip_addr_tbl); -} - -sw_error_t -adpt_hppe_ip_host_del(a_uint32_t dev_id, a_uint32_t del_mode, - fal_host_entry_t * host_entry) -{ - a_uint8_t mode = 0, type = 0; - sw_error_t rv = SW_OK; - ADPT_DEV_ID_CHECK(dev_id); - ADPT_NULL_POINT_CHECK(host_entry); - - mode = host_entry->flags >> 24; - type = host_entry->flags & 0xff; - - if (del_mode & FAL_IP_ENTRY_ID_EN) - mode = 1; - else if (del_mode & FAL_IP_ENTRY_IPADDR_EN) - mode = 0; - else if (del_mode & FAL_IP_ENTRY_ALL_EN) { - return hppe_host_flush_common(dev_id); - } - - if ((type & FAL_IP_IP4_ADDR) == FAL_IP_IP4_ADDR) { - union host_tbl_u entry; - entry.bf.valid= 1; - entry.bf.key_type = 0; - entry.bf.fwd_cmd = host_entry->action; - entry.bf.syn_toggle = host_entry->syn_toggle; - entry.bf.dst_info = host_entry->dst_info; - entry.bf.lan_wan = host_entry->lan_wan; - entry.bf.ip_addr = host_entry->ip4_addr; - rv = hppe_host_ipv4_del(dev_id, (a_uint32_t)mode, &host_entry->entry_id, &entry); - } else if ((type & FAL_IP_IP6_ADDR) == FAL_IP_IP6_ADDR) { - union host_ipv6_tbl_u entry; - entry.bf.valid= 1; - entry.bf.key_type = 2; - entry.bf.fwd_cmd = host_entry->action; - entry.bf.syn_toggle = host_entry->syn_toggle; - entry.bf.dst_info = host_entry->dst_info; - entry.bf.lan_wan = host_entry->lan_wan; - entry.bf.ipv6_addr_0 = host_entry->ip6_addr.ul[3]; - entry.bf.ipv6_addr_1 = host_entry->ip6_addr.ul[3] >> 10 | \ - host_entry->ip6_addr.ul[2] << 22; - entry.bf.ipv6_addr_2 = host_entry->ip6_addr.ul[2] >> 10 | \ - host_entry->ip6_addr.ul[1] << 22; - entry.bf.ipv6_addr_3 = host_entry->ip6_addr.ul[1] >> 10 | \ - host_entry->ip6_addr.ul[0] << 22; - entry.bf.ipv6_addr_4 = host_entry->ip6_addr.ul[0] >> 10; - rv = hppe_host_ipv6_del(dev_id, (a_uint32_t)mode, &host_entry->entry_id, &entry); - } else if ((type & FAL_IP_IP4_ADDR_MCAST) == FAL_IP_IP4_ADDR_MCAST) { - union host_ipv4_mcast_tbl_u entry; - entry.bf.valid= 1; - entry.bf.key_type = 1; - entry.bf.fwd_cmd = host_entry->action; - entry.bf.syn_toggle = host_entry->syn_toggle; - entry.bf.dst_info = host_entry->dst_info; - entry.bf.lan_wan = host_entry->lan_wan; - entry.bf.gip_addr_0 = host_entry->ip4_addr; - entry.bf.gip_addr_1 = host_entry->ip4_addr >> 11; - entry.bf.vsi = host_entry->mcast_info.vsi; - entry.bf.sip_addr_0 = host_entry->mcast_info.sip4_addr; - entry.bf.sip_addr_1 = host_entry->mcast_info.sip4_addr >> 11; - rv = hppe_host_ipv4_mcast_del(dev_id, (a_uint32_t)mode, &host_entry->entry_id, &entry); - } else if ((type & FAL_IP_IP6_ADDR_MCAST) == FAL_IP_IP6_ADDR_MCAST) { - union host_ipv6_mcast_tbl_u entry; - entry.bf.valid= 1; - entry.bf.key_type = 3; - entry.bf.fwd_cmd = host_entry->action; - entry.bf.syn_toggle = host_entry->syn_toggle; - entry.bf.dst_info = host_entry->dst_info; - entry.bf.lan_wan = host_entry->lan_wan; - entry.bf.gipv6_addr_0 = host_entry->ip6_addr.ul[3]; - entry.bf.gipv6_addr_1 = host_entry->ip6_addr.ul[3] >> 20 | \ - host_entry->ip6_addr.ul[2] << 12; - entry.bf.gipv6_addr_2 = host_entry->ip6_addr.ul[2] >> 20 | \ - host_entry->ip6_addr.ul[1] << 12; - entry.bf.gipv6_addr_3 = host_entry->ip6_addr.ul[1] >> 20 | \ - host_entry->ip6_addr.ul[0] << 12; - entry.bf.gipv6_addr_4 = host_entry->ip6_addr.ul[0] >> 20; - entry.bf.vsi = host_entry->mcast_info.vsi; - entry.bf.sipv6_addr_0 = host_entry->mcast_info.sip6_addr.ul[3]; - entry.bf.sipv6_addr_1 = host_entry->mcast_info.sip6_addr.ul[3] >> 20 | \ - host_entry->mcast_info.sip6_addr.ul[2] << 12; - entry.bf.sipv6_addr_2 = host_entry->mcast_info.sip6_addr.ul[2] >> 20 | \ - host_entry->mcast_info.sip6_addr.ul[1] << 12; - entry.bf.sipv6_addr_3 = host_entry->mcast_info.sip6_addr.ul[1] >> 20 | \ - host_entry->mcast_info.sip6_addr.ul[0] << 12; - entry.bf.sipv6_addr_4 = host_entry->mcast_info.sip6_addr.ul[0] >> 20; - rv = hppe_host_ipv6_mcast_del(dev_id, (a_uint32_t)mode, &host_entry->entry_id, &entry); - } - return rv; -} -sw_error_t -adpt_hppe_ip_route_mismatch_get(a_uint32_t dev_id, fal_fwd_cmd_t *cmd) -{ - sw_error_t rv = SW_OK; - union l3_route_ctrl_ext_u l3_route_ctrl_ext; - - memset(&l3_route_ctrl_ext, 0, sizeof(l3_route_ctrl_ext)); - ADPT_DEV_ID_CHECK(dev_id); - ADPT_NULL_POINT_CHECK(cmd); - - rv = hppe_l3_route_ctrl_ext_get(dev_id, &l3_route_ctrl_ext); - if( rv != SW_OK ) - return rv; - - *cmd = (fal_fwd_cmd_t)l3_route_ctrl_ext.bf.ip_route_mismatch; - return rv; -} - -sw_error_t -adpt_hppe_ip_vsi_arp_sg_cfg_get(a_uint32_t dev_id, a_uint32_t vsi, - fal_arp_sg_cfg_t *arp_sg_cfg) -{ - sw_error_t rv = SW_OK; - union l3_vsi_ext_u l3_vsi_ext; - - memset(&l3_vsi_ext, 0, sizeof(l3_vsi_ext)); - ADPT_DEV_ID_CHECK(dev_id); - ADPT_NULL_POINT_CHECK(arp_sg_cfg); - - rv = hppe_l3_vsi_ext_get(dev_id, vsi, &l3_vsi_ext); - if( rv != SW_OK ) - return rv; - - arp_sg_cfg->ipv4_arp_sg_en = l3_vsi_ext.bf.ip_arp_sg_en; - arp_sg_cfg->ipv4_arp_sg_vio_action = l3_vsi_ext.bf.ip_arp_sg_vio_cmd; - arp_sg_cfg->ipv4_arp_sg_port_en = l3_vsi_ext.bf.ip_arp_sg_port_en; - arp_sg_cfg->ipv4_arp_sg_svlan_en = l3_vsi_ext.bf.ip_arp_sg_svlan_en; - arp_sg_cfg->ipv4_arp_sg_cvlan_en = l3_vsi_ext.bf.ip_arp_sg_cvlan_en; - arp_sg_cfg->ipv4_arp_src_unk_action = l3_vsi_ext.bf.ip_arp_src_unk_cmd; - arp_sg_cfg->ip_nd_sg_en = l3_vsi_ext.bf.ip_nd_sg_en; - arp_sg_cfg->ip_nd_sg_vio_action = l3_vsi_ext.bf.ip_nd_sg_vio_cmd; - arp_sg_cfg->ip_nd_sg_port_en = l3_vsi_ext.bf.ip_nd_sg_port_en; - arp_sg_cfg->ip_nd_sg_svlan_en = l3_vsi_ext.bf.ip_nd_sg_svlan_en; - arp_sg_cfg->ip_nd_sg_cvlan_en = l3_vsi_ext.bf.ip_nd_sg_cvlan_en; - arp_sg_cfg->ip_nd_src_unk_action = l3_vsi_ext.bf.ip_nd_src_unk_cmd; - - return rv; -} - -sw_error_t -adpt_hppe_ip_port_arp_sg_cfg_set(a_uint32_t dev_id, fal_port_t port_id, - fal_arp_sg_cfg_t *arp_sg_cfg) -{ - union l3_vp_port_tbl_u l3_vp_port_tbl; - - memset(&l3_vp_port_tbl, 0, sizeof(l3_vp_port_tbl)); - ADPT_DEV_ID_CHECK(dev_id); - - hppe_l3_vp_port_tbl_get(dev_id, port_id, &l3_vp_port_tbl); - - l3_vp_port_tbl.bf.ip_arp_sg_en = arp_sg_cfg->ipv4_arp_sg_en; - l3_vp_port_tbl.bf.ip_arp_sg_vio_cmd = arp_sg_cfg->ipv4_arp_sg_vio_action; - l3_vp_port_tbl.bf.ip_arp_sg_port_en = arp_sg_cfg->ipv4_arp_sg_port_en; - l3_vp_port_tbl.bf.ip_arp_sg_svlan_en = arp_sg_cfg->ipv4_arp_sg_svlan_en; - l3_vp_port_tbl.bf.ip_arp_sg_cvlan_en = arp_sg_cfg->ipv4_arp_sg_cvlan_en; - l3_vp_port_tbl.bf.ip_arp_src_unk_cmd = arp_sg_cfg->ipv4_arp_src_unk_action; - l3_vp_port_tbl.bf.ip_nd_sg_en = arp_sg_cfg->ip_nd_sg_en; - l3_vp_port_tbl.bf.ip_nd_sg_vio_cmd = arp_sg_cfg->ip_nd_sg_vio_action; - l3_vp_port_tbl.bf.ip_nd_sg_port_en = arp_sg_cfg->ip_nd_sg_port_en; - l3_vp_port_tbl.bf.ip_nd_sg_svlan_en = arp_sg_cfg->ip_nd_sg_svlan_en; - l3_vp_port_tbl.bf.ip_nd_sg_cvlan_en = arp_sg_cfg->ip_nd_sg_cvlan_en; - l3_vp_port_tbl.bf.ip_nd_src_unk_cmd = arp_sg_cfg->ip_nd_src_unk_action; - - return hppe_l3_vp_port_tbl_set(dev_id, port_id, &l3_vp_port_tbl); -} -sw_error_t -adpt_hppe_ip_vsi_mc_mode_set(a_uint32_t dev_id, a_uint32_t vsi, - fal_mc_mode_cfg_t *cfg) -{ - union l3_vsi_u l3_vsi; - - memset(&l3_vsi, 0, sizeof(l3_vsi)); - ADPT_DEV_ID_CHECK(dev_id); - - hppe_l3_vsi_get(dev_id, vsi, &l3_vsi); - - l3_vsi.bf.l2_ipv4_mc_en = cfg->l2_ipv4_mc_en; - l3_vsi.bf.l2_ipv4_mc_mode = cfg->l2_ipv4_mc_mode; - l3_vsi.bf.l2_ipv6_mc_en = cfg->l2_ipv6_mc_en; - l3_vsi.bf.l2_ipv6_mc_mode = cfg->l2_ipv6_mc_mode; - - return hppe_l3_vsi_set(dev_id, vsi, &l3_vsi); -} - -sw_error_t -adpt_hppe_ip_vsi_intf_set(a_uint32_t dev_id, a_uint32_t vsi, fal_intf_id_t *id) -{ - union l3_vsi_u l3_vsi; - - memset(&l3_vsi, 0, sizeof(l3_vsi)); - ADPT_DEV_ID_CHECK(dev_id); - - hppe_l3_vsi_get(dev_id, vsi, &l3_vsi); - - l3_vsi.bf.l3_if_valid = id->l3_if_valid; - l3_vsi.bf.l3_if_index = id->l3_if_index; - - return hppe_l3_vsi_set(dev_id, vsi, &l3_vsi); -} - -sw_error_t -adpt_hppe_ip_nexthop_get(a_uint32_t dev_id, - a_uint32_t index, fal_ip_nexthop_t *entry) -{ - sw_error_t rv = SW_OK; - union in_nexthop_tbl_u in_nexthop_tbl; - - memset(&in_nexthop_tbl, 0, sizeof(in_nexthop_tbl)); - ADPT_DEV_ID_CHECK(dev_id); - ADPT_NULL_POINT_CHECK(entry); - - rv = hppe_in_nexthop_tbl_get(dev_id, index, &in_nexthop_tbl); - if( rv != SW_OK ) - return rv; - - entry->type = in_nexthop_tbl.bf0.type; - entry->vsi = in_nexthop_tbl.bf1.vsi; - entry->port = in_nexthop_tbl.bf0.port; - entry->if_index = in_nexthop_tbl.bf0.post_l3_if; - entry->ip_to_me_en = in_nexthop_tbl.bf0.ip_to_me; - entry->pub_ip_index = in_nexthop_tbl.bf1.ip_pub_addr_index; - entry->stag_fmt = in_nexthop_tbl.bf0.stag_fmt; - entry->svid = in_nexthop_tbl.bf0.svid; - entry->ctag_fmt = in_nexthop_tbl.bf0.ctag_fmt; - entry->cvid = in_nexthop_tbl.bf0.cvid; - entry->mac_addr.uc[5] = in_nexthop_tbl.bf1.mac_addr_0; - entry->mac_addr.uc[4] = in_nexthop_tbl.bf1.mac_addr_0 >> 8; - entry->mac_addr.uc[3] = in_nexthop_tbl.bf1.mac_addr_1; - entry->mac_addr.uc[2] = in_nexthop_tbl.bf1.mac_addr_1 >> 8; - entry->mac_addr.uc[1] = in_nexthop_tbl.bf1.mac_addr_1 >> 16; - entry->mac_addr.uc[0] = in_nexthop_tbl.bf1.mac_addr_1 >> 24; - entry->dnat_ip = in_nexthop_tbl.bf0.ip_addr_dnat; - - return SW_OK; -} - -sw_error_t -adpt_hppe_ip_route_mismatch_set(a_uint32_t dev_id, fal_fwd_cmd_t cmd) -{ - union l3_route_ctrl_ext_u l3_route_ctrl_ext; - - memset(&l3_route_ctrl_ext, 0, sizeof(l3_route_ctrl_ext)); - ADPT_DEV_ID_CHECK(dev_id); - - hppe_l3_route_ctrl_ext_get(dev_id, &l3_route_ctrl_ext); - l3_route_ctrl_ext.bf.ip_route_mismatch = cmd; - - return hppe_l3_route_ctrl_ext_set(dev_id, &l3_route_ctrl_ext); -} -sw_error_t -adpt_hppe_ip_host_get(a_uint32_t dev_id, a_uint32_t get_mode, - fal_host_entry_t *host_entry) -{ - a_uint8_t mode = 0, type = 0; - sw_error_t rv = SW_OK; - ADPT_DEV_ID_CHECK(dev_id); - ADPT_NULL_POINT_CHECK(host_entry); - - mode = host_entry->flags >> 24; - type = host_entry->flags & 0xff; - - if (get_mode & FAL_IP_ENTRY_ID_EN) - mode = 1; - else if (get_mode & FAL_IP_ENTRY_IPADDR_EN) - mode = 0; - - if ((type & FAL_IP_IP4_ADDR) == FAL_IP_IP4_ADDR) { - union host_tbl_u entry; - entry.bf.key_type = 0; - entry.bf.ip_addr = host_entry->ip4_addr; - rv = hppe_host_ipv4_get(dev_id, (a_uint32_t)mode, &host_entry->entry_id, &entry); - if (!rv && (entry.bf.key_type != 0)) - rv = SW_FAIL; - host_entry->ip4_addr = entry.bf.ip_addr; - host_entry->lan_wan = entry.bf.lan_wan; - host_entry->dst_info = entry.bf.dst_info; - host_entry->syn_toggle = entry.bf.syn_toggle; - host_entry->action = entry.bf.fwd_cmd; - host_entry->status = entry.bf.valid; - } else if ((type & FAL_IP_IP6_ADDR) == FAL_IP_IP6_ADDR) { - union host_ipv6_tbl_u entry; - entry.bf.key_type = 2; - entry.bf.ipv6_addr_0 = host_entry->ip6_addr.ul[3]; - entry.bf.ipv6_addr_1 = host_entry->ip6_addr.ul[3] >> 10 | \ - host_entry->ip6_addr.ul[2] << 22; - entry.bf.ipv6_addr_2 = host_entry->ip6_addr.ul[2] >> 10 | \ - host_entry->ip6_addr.ul[1] << 22; - entry.bf.ipv6_addr_3 = host_entry->ip6_addr.ul[1] >> 10 | \ - host_entry->ip6_addr.ul[0] << 22; - entry.bf.ipv6_addr_4 = host_entry->ip6_addr.ul[0] >> 10; - rv = hppe_host_ipv6_get(dev_id, (a_uint32_t)mode, &host_entry->entry_id, &entry); - if (!rv && (entry.bf.key_type != 2)) - rv = SW_FAIL; - host_entry->ip6_addr.ul[3] = entry.bf.ipv6_addr_0 | entry.bf.ipv6_addr_1 << 10; - host_entry->ip6_addr.ul[2] = entry.bf.ipv6_addr_1 >> 22 | entry.bf.ipv6_addr_2 << 10; - host_entry->ip6_addr.ul[1] = entry.bf.ipv6_addr_2 >> 22 | entry.bf.ipv6_addr_3 << 10; - host_entry->ip6_addr.ul[0] = entry.bf.ipv6_addr_3 >> 22 | entry.bf.ipv6_addr_4 << 10; - host_entry->lan_wan = entry.bf.lan_wan; - host_entry->dst_info = entry.bf.dst_info; - host_entry->syn_toggle = entry.bf.syn_toggle; - host_entry->action = entry.bf.fwd_cmd; - host_entry->status = entry.bf.valid; - } else if ((type & FAL_IP_IP4_ADDR_MCAST) == FAL_IP_IP4_ADDR_MCAST) { - union host_ipv4_mcast_tbl_u entry; - entry.bf.key_type = 1; - entry.bf.gip_addr_0 = host_entry->ip4_addr; - entry.bf.gip_addr_1 = host_entry->ip4_addr >> 11; - entry.bf.vsi = host_entry->mcast_info.vsi; - entry.bf.sip_addr_0 = host_entry->mcast_info.sip4_addr; - entry.bf.sip_addr_1 = host_entry->mcast_info.sip4_addr >> 11; - rv = hppe_host_ipv4_mcast_get(dev_id, (a_uint32_t)mode, &host_entry->entry_id, &entry); - if (!rv && (entry.bf.key_type != 1)) - rv = SW_FAIL; - host_entry->lan_wan = entry.bf.lan_wan; - host_entry->dst_info = entry.bf.dst_info; - host_entry->syn_toggle = entry.bf.syn_toggle; - host_entry->action = entry.bf.fwd_cmd; - host_entry->status = entry.bf.valid; - host_entry->ip4_addr = entry.bf.gip_addr_0 | entry.bf.gip_addr_1 << 11; - host_entry->mcast_info.vsi = entry.bf.vsi; - host_entry->mcast_info.sip4_addr = entry.bf.sip_addr_0 | entry.bf.sip_addr_1 << 11; - } else if ((type & FAL_IP_IP6_ADDR_MCAST) == FAL_IP_IP6_ADDR_MCAST) { - union host_ipv6_mcast_tbl_u entry; - entry.bf.key_type = 3; - entry.bf.vsi = host_entry->mcast_info.vsi; - entry.bf.gipv6_addr_0 = host_entry->ip6_addr.ul[3]; - entry.bf.gipv6_addr_1 = host_entry->ip6_addr.ul[3] >> 20 | \ - host_entry->ip6_addr.ul[2] << 12; - entry.bf.gipv6_addr_2 = host_entry->ip6_addr.ul[2] >> 20 | \ - host_entry->ip6_addr.ul[1] << 12; - entry.bf.gipv6_addr_3 = host_entry->ip6_addr.ul[1] >> 20 | \ - host_entry->ip6_addr.ul[0] << 12; - entry.bf.gipv6_addr_4 = host_entry->ip6_addr.ul[0] >> 20; - entry.bf.sipv6_addr_0 = host_entry->mcast_info.sip6_addr.ul[3]; - entry.bf.sipv6_addr_1 = host_entry->mcast_info.sip6_addr.ul[3] >> 20 | \ - host_entry->mcast_info.sip6_addr.ul[2] << 12; - entry.bf.sipv6_addr_2 = host_entry->mcast_info.sip6_addr.ul[2] >> 20 | \ - host_entry->mcast_info.sip6_addr.ul[1] << 12; - entry.bf.sipv6_addr_3 = host_entry->mcast_info.sip6_addr.ul[1] >> 20 | \ - host_entry->mcast_info.sip6_addr.ul[0] << 12; - entry.bf.sipv6_addr_4 = host_entry->mcast_info.sip6_addr.ul[0] >> 20; - rv = hppe_host_ipv6_mcast_get(dev_id, (a_uint32_t)mode, &host_entry->entry_id, &entry); - if (!rv && (entry.bf.key_type != 3)) - rv = SW_FAIL; - host_entry->lan_wan = entry.bf.lan_wan; - host_entry->dst_info = entry.bf.dst_info; - host_entry->syn_toggle = entry.bf.syn_toggle; - host_entry->action = entry.bf.fwd_cmd; - host_entry->status = entry.bf.valid; - host_entry->ip6_addr.ul[3] = entry.bf.gipv6_addr_0 | entry.bf.gipv6_addr_1 << 20; - host_entry->ip6_addr.ul[2] = entry.bf.gipv6_addr_1 >> 12 | entry.bf.gipv6_addr_2 << 20; - host_entry->ip6_addr.ul[1] = entry.bf.gipv6_addr_2 >> 12 | entry.bf.gipv6_addr_3 << 20; - host_entry->ip6_addr.ul[0] = entry.bf.gipv6_addr_3 >> 12 | entry.bf.gipv6_addr_4 << 20; - host_entry->mcast_info.vsi = entry.bf.vsi; - host_entry->mcast_info.sip6_addr.ul[3] = entry.bf.sipv6_addr_0 | entry.bf.sipv6_addr_1 << 20; - host_entry->mcast_info.sip6_addr.ul[2] = entry.bf.sipv6_addr_1 >> 12 | entry.bf.sipv6_addr_2 << 20; - host_entry->mcast_info.sip6_addr.ul[1] = entry.bf.sipv6_addr_2 >> 12 | entry.bf.sipv6_addr_3 << 20; - host_entry->mcast_info.sip6_addr.ul[0] = entry.bf.sipv6_addr_3 >> 12 | entry.bf.sipv6_addr_4 << 20; - } - - return rv; -} - -sw_error_t -adpt_hppe_ip_host_next(a_uint32_t dev_id, a_uint32_t next_mode, - fal_host_entry_t * host_entry) -{ - a_uint32_t i = 0, step = 0; - sw_error_t rv = SW_OK; - - ADPT_DEV_ID_CHECK(dev_id); - ADPT_NULL_POINT_CHECK(host_entry); - - if (FAL_NEXT_ENTRY_FIRST_ID == host_entry->entry_id) - i = 0; - - if (next_mode == FAL_IP_IP6_ADDR_MCAST) { - if (FAL_NEXT_ENTRY_FIRST_ID != host_entry->entry_id) - i = (host_entry->entry_id & ~3) + 4; - step = 4; - } else if (next_mode == FAL_IP_IP4_ADDR_MCAST) { - if (FAL_NEXT_ENTRY_FIRST_ID != host_entry->entry_id) - i = (host_entry->entry_id & ~1) + 2; - step = 2; - } else if (next_mode == FAL_IP_IP4_ADDR) { - if (FAL_NEXT_ENTRY_FIRST_ID != host_entry->entry_id) - i = host_entry->entry_id + 1; - step = 1; - } else if (next_mode == FAL_IP_IP6_ADDR) { - if (FAL_NEXT_ENTRY_FIRST_ID != host_entry->entry_id) - i = (host_entry->entry_id & ~1) + 2; - step = 2; - } - for (; i < HOST_TBL_MAX_ENTRY;) { - host_entry->flags = next_mode; - host_entry->entry_id = i; - rv = adpt_hppe_ip_host_get(dev_id, FAL_IP_ENTRY_ID_EN, host_entry); - if (!rv) { - return rv; - } - i += step; - } - - return SW_FAIL; - -} -sw_error_t -adpt_hppe_ip_intf_set( - a_uint32_t dev_id, - a_uint32_t index, - fal_intf_entry_t *entry) -{ - union in_l3_if_tbl_u in_l3_if_tbl; - union eg_l3_if_tbl_u eg_l3_if_tbl; - a_uint8_t i = 0; - - memset(&in_l3_if_tbl, 0, sizeof(in_l3_if_tbl)); - memset(&eg_l3_if_tbl, 0, sizeof(eg_l3_if_tbl)); - ADPT_DEV_ID_CHECK(dev_id); - ADPT_NULL_POINT_CHECK(entry); - - in_l3_if_tbl.bf.mru = entry->mru; - in_l3_if_tbl.bf.mtu = entry->mtu; - in_l3_if_tbl.bf.ttl_dec_bypass = entry->ttl_dec_bypass_en; - in_l3_if_tbl.bf.ipv4_uc_route_en = entry->ipv4_uc_route_en; - in_l3_if_tbl.bf.ipv6_uc_route_en = entry->ipv6_uc_route_en; - in_l3_if_tbl.bf.icmp_trigger_en = entry->icmp_trigger_en; - in_l3_if_tbl.bf.ttl_exceed_cmd = entry->ttl_exceed_action; - in_l3_if_tbl.bf.ttl_exceed_de_acce = entry->ttl_exceed_deacclr_en; - in_l3_if_tbl.bf.mac_bitmap = entry->mac_addr_bitmap; - eg_l3_if_tbl.bf.mac_addr_0 = entry->mac_addr.uc[5] | \ - entry->mac_addr.uc[4] << 8 | \ - entry->mac_addr.uc[3] << 16 | \ - entry->mac_addr.uc[2] << 24; - eg_l3_if_tbl.bf.mac_addr_1 = entry->mac_addr.uc[1] | \ - entry->mac_addr.uc[0] << 8; - - for (i = 0; i < 8; i++) { - if ((entry->mac_addr_bitmap >> i) & 0x1) { - union my_mac_tbl_u mymac; - mymac.bf.valid = 1; - mymac.bf.mac_da_0 = eg_l3_if_tbl.bf.mac_addr_0; - mymac.bf.mac_da_1 = eg_l3_if_tbl.bf.mac_addr_1; - hppe_my_mac_tbl_set(dev_id, i, &mymac); - break; - } - } - - hppe_in_l3_if_tbl_set(dev_id, index, &in_l3_if_tbl); - hppe_eg_l3_if_tbl_set(dev_id, index, &eg_l3_if_tbl); - return SW_OK; -} - -sw_error_t -adpt_hppe_ip_vsi_mc_mode_get(a_uint32_t dev_id, a_uint32_t vsi, - fal_mc_mode_cfg_t *cfg) -{ - sw_error_t rv = SW_OK; - union l3_vsi_u l3_vsi; - - memset(&l3_vsi, 0, sizeof(l3_vsi)); - ADPT_DEV_ID_CHECK(dev_id); - ADPT_NULL_POINT_CHECK(cfg); - - rv = hppe_l3_vsi_get(dev_id, vsi, &l3_vsi); - if( rv != SW_OK ) - return rv; - - cfg->l2_ipv4_mc_en = l3_vsi.bf.l2_ipv4_mc_en; - cfg->l2_ipv4_mc_mode = l3_vsi.bf.l2_ipv4_mc_mode; - cfg->l2_ipv6_mc_en = l3_vsi.bf.l2_ipv6_mc_en; - cfg->l2_ipv6_mc_mode = l3_vsi.bf.l2_ipv6_mc_mode; - - return SW_OK; -} - -sw_error_t -adpt_hppe_ip_port_macaddr_get(a_uint32_t dev_id, fal_port_t port_id, - fal_macaddr_entry_t *macaddr) -{ - sw_error_t rv = SW_OK; - union l3_vp_port_tbl_u l3_vp_port_tbl; - - memset(&l3_vp_port_tbl, 0, sizeof(l3_vp_port_tbl)); - ADPT_DEV_ID_CHECK(dev_id); - ADPT_NULL_POINT_CHECK(macaddr); - - rv = hppe_l3_vp_port_tbl_get(dev_id, port_id, &l3_vp_port_tbl); - if( rv != SW_OK ) - return rv; - - macaddr->valid = l3_vp_port_tbl.bf.mac_valid; - macaddr->mac_addr.uc[5] = l3_vp_port_tbl.bf.mac_da_0; - macaddr->mac_addr.uc[4] = l3_vp_port_tbl.bf.mac_da_0 >> 8; - macaddr->mac_addr.uc[3] = l3_vp_port_tbl.bf.mac_da_1; - macaddr->mac_addr.uc[2] = l3_vp_port_tbl.bf.mac_da_1 >> 8; - macaddr->mac_addr.uc[1] = l3_vp_port_tbl.bf.mac_da_1 >> 16; - macaddr->mac_addr.uc[0] = l3_vp_port_tbl.bf.mac_da_1 >> 24; - - return SW_OK; -} - -sw_error_t -adpt_hppe_ip_port_arp_sg_cfg_get(a_uint32_t dev_id, fal_port_t port_id, - fal_arp_sg_cfg_t *arp_sg_cfg) -{ - sw_error_t rv = SW_OK; - union l3_vp_port_tbl_u l3_vp_port_tbl; - - memset(&l3_vp_port_tbl, 0, sizeof(l3_vp_port_tbl)); - ADPT_DEV_ID_CHECK(dev_id); - ADPT_NULL_POINT_CHECK(arp_sg_cfg); - - rv = hppe_l3_vp_port_tbl_get(dev_id, port_id, &l3_vp_port_tbl); - if( rv != SW_OK ) - return rv; - - arp_sg_cfg->ipv4_arp_sg_en = l3_vp_port_tbl.bf.ip_arp_sg_en; - arp_sg_cfg->ipv4_arp_sg_vio_action = l3_vp_port_tbl.bf.ip_arp_sg_vio_cmd; - arp_sg_cfg->ipv4_arp_sg_port_en = l3_vp_port_tbl.bf.ip_arp_sg_port_en; - arp_sg_cfg->ipv4_arp_sg_svlan_en = l3_vp_port_tbl.bf.ip_arp_sg_svlan_en; - arp_sg_cfg->ipv4_arp_sg_cvlan_en = l3_vp_port_tbl.bf.ip_arp_sg_cvlan_en; - arp_sg_cfg->ipv4_arp_src_unk_action = l3_vp_port_tbl.bf.ip_arp_src_unk_cmd; - arp_sg_cfg->ip_nd_sg_en = l3_vp_port_tbl.bf.ip_nd_sg_en; - arp_sg_cfg->ip_nd_sg_vio_action = l3_vp_port_tbl.bf.ip_nd_sg_vio_cmd; - arp_sg_cfg->ip_nd_sg_port_en = l3_vp_port_tbl.bf.ip_nd_sg_port_en; - arp_sg_cfg->ip_nd_sg_svlan_en = l3_vp_port_tbl.bf.ip_nd_sg_svlan_en; - arp_sg_cfg->ip_nd_sg_cvlan_en = l3_vp_port_tbl.bf.ip_nd_sg_cvlan_en; - arp_sg_cfg->ip_nd_src_unk_action = l3_vp_port_tbl.bf.ip_nd_src_unk_cmd; - - return SW_OK; -} - -sw_error_t -adpt_hppe_ip_global_ctrl_get(a_uint32_t dev_id, fal_ip_global_cfg_t *cfg) -{ - sw_error_t rv = SW_OK; - union l3_route_ctrl_u l3_route_ctrl; - union l3_route_ctrl_ext_u l3_route_ctrl_ext; - - ADPT_DEV_ID_CHECK(dev_id); - ADPT_NULL_POINT_CHECK(cfg); - memset(&l3_route_ctrl, 0, sizeof(l3_route_ctrl)); - memset(&l3_route_ctrl, 0, sizeof(l3_route_ctrl_ext)); - - rv = hppe_l3_route_ctrl_get(dev_id, &l3_route_ctrl); - if( rv != SW_OK ) - return rv; - - rv = hppe_l3_route_ctrl_ext_get(dev_id, &l3_route_ctrl_ext); - if( rv != SW_OK ) - return rv; - - cfg->mru_fail_action = l3_route_ctrl.bf.ip_mru_check_fail; - cfg->mru_deacclr_en = l3_route_ctrl.bf.ip_mru_check_fail_de_acce; - cfg->mtu_fail_action = l3_route_ctrl.bf.ip_mtu_fail; - cfg->mtu_deacclr_en = l3_route_ctrl.bf.ip_mtu_fail_de_acce; - cfg->mtu_nonfrag_fail_action = l3_route_ctrl.bf.ip_mtu_df_fail; - cfg->mtu_df_deacclr_en = l3_route_ctrl.bf.ip_mtu_df_fail_de_acce; - cfg->prefix_bc_action = l3_route_ctrl.bf.ip_prefix_bc_cmd; - cfg->prefix_deacclr_en = l3_route_ctrl.bf.ip_prefix_bc_de_acce; - cfg->icmp_rdt_action = l3_route_ctrl.bf.icmp_rdt_cmd; - cfg->icmp_rdt_deacclr_en = l3_route_ctrl.bf.icmp_rdt_de_acce; - cfg->hash_mode_0 = l3_route_ctrl_ext.bf.host_hash_mode_0; - cfg->hash_mode_1 = l3_route_ctrl_ext.bf.host_hash_mode_1; - - return SW_OK; -} - -sw_error_t -adpt_hppe_ip_global_ctrl_set(a_uint32_t dev_id, fal_ip_global_cfg_t *cfg) -{ - sw_error_t rv = SW_OK; - union l3_route_ctrl_u l3_route_ctrl; - union l3_route_ctrl_ext_u l3_route_ctrl_ext; - - ADPT_DEV_ID_CHECK(dev_id); - ADPT_NULL_POINT_CHECK(cfg); - memset(&l3_route_ctrl, 0, sizeof(l3_route_ctrl)); - memset(&l3_route_ctrl, 0, sizeof(l3_route_ctrl_ext)); - - rv = hppe_l3_route_ctrl_get(dev_id, &l3_route_ctrl); - if( rv != SW_OK ) - return rv; - - rv = hppe_l3_route_ctrl_ext_get(dev_id, &l3_route_ctrl_ext); - if( rv != SW_OK ) - return rv; - - l3_route_ctrl.bf.ip_mru_check_fail = cfg->mru_fail_action; - l3_route_ctrl.bf.ip_mru_check_fail_de_acce = cfg->mru_deacclr_en; - l3_route_ctrl.bf.ip_mtu_fail = cfg->mtu_fail_action; - l3_route_ctrl.bf.ip_mtu_fail_de_acce = cfg->mtu_deacclr_en; - l3_route_ctrl.bf.ip_mtu_df_fail = cfg->mtu_nonfrag_fail_action; - l3_route_ctrl.bf.ip_mtu_df_fail_de_acce = cfg->mtu_df_deacclr_en; - l3_route_ctrl.bf.ip_prefix_bc_cmd =cfg->prefix_bc_action; - l3_route_ctrl.bf.ip_prefix_bc_de_acce = cfg->prefix_deacclr_en; - l3_route_ctrl.bf.icmp_rdt_cmd = cfg->icmp_rdt_action; - l3_route_ctrl.bf.icmp_rdt_de_acce = cfg->icmp_rdt_deacclr_en; - l3_route_ctrl_ext.bf.host_hash_mode_0 = cfg->hash_mode_0; - l3_route_ctrl_ext.bf.host_hash_mode_1 = cfg->hash_mode_1; - - hppe_l3_route_ctrl_set(dev_id, &l3_route_ctrl); - hppe_l3_route_ctrl_ext_set(dev_id, &l3_route_ctrl_ext); - return SW_OK; -} - -sw_error_t -adpt_hppe_ip_nexthop_set(a_uint32_t dev_id, - a_uint32_t index, fal_ip_nexthop_t *entry) -{ - union in_nexthop_tbl_u in_nexthop_tbl; - - memset(&in_nexthop_tbl, 0, sizeof(in_nexthop_tbl)); - ADPT_DEV_ID_CHECK(dev_id); - ADPT_NULL_POINT_CHECK(entry); - - in_nexthop_tbl.bf0.type = entry->type; - if (entry->type == 0) - in_nexthop_tbl.bf1.vsi = entry->vsi; - else - in_nexthop_tbl.bf0.port = entry->port; - in_nexthop_tbl.bf0.post_l3_if = entry->if_index; - in_nexthop_tbl.bf0.ip_to_me = entry->ip_to_me_en; - in_nexthop_tbl.bf0.ip_pub_addr_index = entry->pub_ip_index; - in_nexthop_tbl.bf0.stag_fmt = entry->stag_fmt; - in_nexthop_tbl.bf0.svid = entry->svid; - in_nexthop_tbl.bf0.ctag_fmt = entry->ctag_fmt; - in_nexthop_tbl.bf0.cvid = entry->cvid; - in_nexthop_tbl.bf0.mac_addr_0 = entry->mac_addr.uc[5] | - entry->mac_addr.uc[4] << 8; - in_nexthop_tbl.bf0.mac_addr_1 = entry->mac_addr.uc[3] | - entry->mac_addr.uc[2] << 8 | - entry->mac_addr.uc[1] << 16 | - entry->mac_addr.uc[0] << 24; - in_nexthop_tbl.bf0.ip_addr_dnat = entry->dnat_ip; - - return hppe_in_nexthop_tbl_set(dev_id, index, &in_nexthop_tbl); -} -#endif -void adpt_hppe_ip_func_bitmap_init(a_uint32_t dev_id) -{ - adpt_api_t *p_adpt_api = NULL; - - p_adpt_api = adpt_api_ptr_get(dev_id); - - if(p_adpt_api == NULL) - return; - - p_adpt_api->adpt_ip_func_bitmap[0] = 0; - p_adpt_api->adpt_ip_func_bitmap[1] = 0; - return; -} - -static void adpt_hppe_ip_func_unregister(a_uint32_t dev_id, adpt_api_t *p_adpt_api) -{ - if(p_adpt_api == NULL) - return; - - p_adpt_api->adpt_ip_network_route_get = NULL; - p_adpt_api->adpt_ip_host_add = NULL; - p_adpt_api->adpt_ip_vsi_sg_cfg_get = NULL; - p_adpt_api->adpt_ip_pub_addr_set = NULL; - p_adpt_api->adpt_ip_port_sg_cfg_set = NULL; - p_adpt_api->adpt_ip_port_intf_get = NULL; - p_adpt_api->adpt_ip_vsi_arp_sg_cfg_set = NULL; - p_adpt_api->adpt_ip_pub_addr_get = NULL; - p_adpt_api->adpt_ip_port_intf_set = NULL; - p_adpt_api->adpt_ip_vsi_sg_cfg_set = NULL; - p_adpt_api->adpt_ip_host_next = NULL; - p_adpt_api->adpt_ip_port_macaddr_set = NULL; - p_adpt_api->adpt_ip_vsi_intf_get = NULL; - p_adpt_api->adpt_ip_network_route_add = NULL; - p_adpt_api->adpt_ip_port_sg_cfg_get = NULL; - p_adpt_api->adpt_ip_intf_get = NULL; - p_adpt_api->adpt_ip_network_route_del = NULL; - p_adpt_api->adpt_ip_host_del = NULL; - p_adpt_api->adpt_ip_route_mismatch_get = NULL; - p_adpt_api->adpt_ip_vsi_arp_sg_cfg_get = NULL; - p_adpt_api->adpt_ip_port_arp_sg_cfg_set = NULL; - p_adpt_api->adpt_ip_vsi_mc_mode_set = NULL; - p_adpt_api->adpt_ip_vsi_intf_set = NULL; - p_adpt_api->adpt_ip_nexthop_get = NULL; - p_adpt_api->adpt_ip_route_mismatch_set = NULL; - p_adpt_api->adpt_ip_host_get = NULL; - p_adpt_api->adpt_ip_intf_set = NULL; - p_adpt_api->adpt_ip_vsi_mc_mode_get = NULL; - p_adpt_api->adpt_ip_port_macaddr_get = NULL; - p_adpt_api->adpt_ip_port_arp_sg_cfg_get = NULL; - p_adpt_api->adpt_ip_nexthop_set = NULL; - p_adpt_api->adpt_ip_global_ctrl_get = NULL; - p_adpt_api->adpt_ip_global_ctrl_set = NULL; - - return; -} -sw_error_t adpt_hppe_ip_init(a_uint32_t dev_id) -{ - adpt_api_t *p_adpt_api = NULL; - - p_adpt_api = adpt_api_ptr_get(dev_id); - - if(p_adpt_api == NULL) - return SW_FAIL; - - adpt_hppe_ip_func_unregister(dev_id, p_adpt_api); -#ifndef IN_IP_MINI - if (p_adpt_api->adpt_ip_func_bitmap[0] & (1 << FUNC_IP_NETWORK_ROUTE_GET)) - p_adpt_api->adpt_ip_network_route_get = adpt_hppe_ip_network_route_get; - if (p_adpt_api->adpt_ip_func_bitmap[0] & (1 << FUNC_IP_HOST_ADD)) - p_adpt_api->adpt_ip_host_add = adpt_hppe_ip_host_add; - if (p_adpt_api->adpt_ip_func_bitmap[0] & (1 << FUNC_IP_VSI_SG_CFG_GET)) - p_adpt_api->adpt_ip_vsi_sg_cfg_get = adpt_hppe_ip_vsi_sg_cfg_get; - if (p_adpt_api->adpt_ip_func_bitmap[0] & (1 << FUNC_IP_PUB_ADDR_SET)) - p_adpt_api->adpt_ip_pub_addr_set = adpt_hppe_ip_pub_addr_set; - if (p_adpt_api->adpt_ip_func_bitmap[0] & (1 << FUNC_IP_PORT_SG_CFG_SET)) - p_adpt_api->adpt_ip_port_sg_cfg_set = adpt_hppe_ip_port_sg_cfg_set; - if (p_adpt_api->adpt_ip_func_bitmap[0] & (1 << FUNC_IP_PORT_INTF_GET)) - p_adpt_api->adpt_ip_port_intf_get = adpt_hppe_ip_port_intf_get; - if (p_adpt_api->adpt_ip_func_bitmap[0] & (1 << FUNC_IP_VSI_ARP_SG_CFG_SET)) - p_adpt_api->adpt_ip_vsi_arp_sg_cfg_set = adpt_hppe_ip_vsi_arp_sg_cfg_set; - if (p_adpt_api->adpt_ip_func_bitmap[0] & (1 << FUNC_IP_PUB_ADDR_GET)) - p_adpt_api->adpt_ip_pub_addr_get = adpt_hppe_ip_pub_addr_get; - if (p_adpt_api->adpt_ip_func_bitmap[0] & (1 << FUNC_IP_PORT_INTF_SET)) - p_adpt_api->adpt_ip_port_intf_set = adpt_hppe_ip_port_intf_set; - if (p_adpt_api->adpt_ip_func_bitmap[0] & (1 << FUNC_IP_VSI_SG_CFG_SET)) - p_adpt_api->adpt_ip_vsi_sg_cfg_set = adpt_hppe_ip_vsi_sg_cfg_set; - if (p_adpt_api->adpt_ip_func_bitmap[0] & (1 << FUNC_IP_HOST_NEXT)) - p_adpt_api->adpt_ip_host_next = adpt_hppe_ip_host_next; - if (p_adpt_api->adpt_ip_func_bitmap[0] & (1 << FUNC_IP_PORT_MACADDR_SET)) - p_adpt_api->adpt_ip_port_macaddr_set = adpt_hppe_ip_port_macaddr_set; - if (p_adpt_api->adpt_ip_func_bitmap[0] & (1 << FUNC_IP_VSI_INTF_GET)) - p_adpt_api->adpt_ip_vsi_intf_get = adpt_hppe_ip_vsi_intf_get; - if (p_adpt_api->adpt_ip_func_bitmap[0] & (1 << FUNC_IP_NETWORK_ROUTE_ADD)) - p_adpt_api->adpt_ip_network_route_add = adpt_hppe_ip_network_route_add; - if (p_adpt_api->adpt_ip_func_bitmap[0] & (1 << FUNC_IP_PORT_SG_CFG_GET)) - p_adpt_api->adpt_ip_port_sg_cfg_get = adpt_hppe_ip_port_sg_cfg_get; - if (p_adpt_api->adpt_ip_func_bitmap[0] & (1 << FUNC_IP_INTF_GET)) - p_adpt_api->adpt_ip_intf_get = adpt_hppe_ip_intf_get; - if (p_adpt_api->adpt_ip_func_bitmap[0] & (1 << FUNC_IP_NETWORK_ROUTE_DEL)) - p_adpt_api->adpt_ip_network_route_del = adpt_hppe_ip_network_route_del; - if (p_adpt_api->adpt_ip_func_bitmap[0] & (1 << FUNC_IP_HOST_DEL)) - p_adpt_api->adpt_ip_host_del = adpt_hppe_ip_host_del; - if (p_adpt_api->adpt_ip_func_bitmap[0] & (1 << FUNC_IP_ROUTE_MISMATCH_GET)) - p_adpt_api->adpt_ip_route_mismatch_get = adpt_hppe_ip_route_mismatch_get; - if (p_adpt_api->adpt_ip_func_bitmap[0] & (1 << FUNC_IP_VSI_ARP_SG_CFG_GET)) - p_adpt_api->adpt_ip_vsi_arp_sg_cfg_get = adpt_hppe_ip_vsi_arp_sg_cfg_get; - if (p_adpt_api->adpt_ip_func_bitmap[0] & (1 << FUNC_IP_PORT_ARP_SG_CFG_SET)) - p_adpt_api->adpt_ip_port_arp_sg_cfg_set = adpt_hppe_ip_port_arp_sg_cfg_set; - if (p_adpt_api->adpt_ip_func_bitmap[0] & (1 << FUNC_IP_VSI_MC_MODE_SET)) - p_adpt_api->adpt_ip_vsi_mc_mode_set = adpt_hppe_ip_vsi_mc_mode_set; - if (p_adpt_api->adpt_ip_func_bitmap[0] & (1 << FUNC_IP_VSI_INTF_SET)) - p_adpt_api->adpt_ip_vsi_intf_set = adpt_hppe_ip_vsi_intf_set; - if (p_adpt_api->adpt_ip_func_bitmap[0] & (1 << FUNC_IP_NEXTHOP_GET)) - p_adpt_api->adpt_ip_nexthop_get = adpt_hppe_ip_nexthop_get; - if (p_adpt_api->adpt_ip_func_bitmap[0] & (1 << FUNC_IP_ROUTE_MISMATCH_SET)) - p_adpt_api->adpt_ip_route_mismatch_set = adpt_hppe_ip_route_mismatch_set; - if (p_adpt_api->adpt_ip_func_bitmap[0] & (1 << FUNC_IP_HOST_GET)) - p_adpt_api->adpt_ip_host_get = adpt_hppe_ip_host_get; - if (p_adpt_api->adpt_ip_func_bitmap[0] & (1 << FUNC_IP_INTF_SET)) - p_adpt_api->adpt_ip_intf_set = adpt_hppe_ip_intf_set; - if (p_adpt_api->adpt_ip_func_bitmap[0] & (1 << FUNC_IP_VSI_MC_MODE_GET)) - p_adpt_api->adpt_ip_vsi_mc_mode_get = adpt_hppe_ip_vsi_mc_mode_get; - if (p_adpt_api->adpt_ip_func_bitmap[0] & (1 << FUNC_IP_PORT_MACADDR_GET)) - p_adpt_api->adpt_ip_port_macaddr_get = adpt_hppe_ip_port_macaddr_get; - if (p_adpt_api->adpt_ip_func_bitmap[0] & (1 << FUNC_IP_PORT_ARP_SG_CFG_GET)) - p_adpt_api->adpt_ip_port_arp_sg_cfg_get = adpt_hppe_ip_port_arp_sg_cfg_get; - if (p_adpt_api->adpt_ip_func_bitmap[0] & (1 << FUNC_IP_NEXTHOP_SET)) - p_adpt_api->adpt_ip_nexthop_set = adpt_hppe_ip_nexthop_set; - if (p_adpt_api->adpt_ip_func_bitmap[0] & (1 << FUNC_IP_GLOBAL_CTRL_GET)) - p_adpt_api->adpt_ip_global_ctrl_get = adpt_hppe_ip_global_ctrl_get; - if (p_adpt_api->adpt_ip_func_bitmap[1] & (1 << (FUNC_IP_GLOBAL_CTRL_SET % 32))) - p_adpt_api->adpt_ip_global_ctrl_set = adpt_hppe_ip_global_ctrl_set; -#endif - return SW_OK; -} -/** - * @} - */ diff --git a/feeds/ipq807x/qca-ssdk/src/src/adpt/hppe/adpt_hppe_mib.c b/feeds/ipq807x/qca-ssdk/src/src/adpt/hppe/adpt_hppe_mib.c deleted file mode 100755 index 523707213..000000000 --- a/feeds/ipq807x/qca-ssdk/src/src/adpt/hppe/adpt_hppe_mib.c +++ /dev/null @@ -1,1019 +0,0 @@ -/* - * Copyright (c) 2016-2019, The Linux Foundation. All rights reserved. - * Permission to use, copy, modify, and/or distribute this software for - * any purpose with or without fee is hereby granted, provided that the - * above copyright notice and this permission notice appear in all copies. - * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES - * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR - * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES - * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN - * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT - * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. - */ - - -/** - * @defgroup - * @{ - */ -#include "sw.h" -#include "hppe_mib_reg.h" -#include "hppe_mib.h" -#include "adpt.h" -#include "hppe_xgmacmib_reg.h" -#include "hppe_xgmacmib.h" - -#include "hppe_init.h" -#include "adpt_hppe.h" -#ifdef CPPE -#include "adpt_cppe_mib.h" -#endif - -sw_error_t -adpt_hppe_mib_cpukeep_get(a_uint32_t dev_id, a_bool_t *enable) -{ - sw_error_t rv = SW_OK; - a_uint32_t port_id = 0, status = 0; - - ADPT_DEV_ID_CHECK(dev_id); - ADPT_NULL_POINT_CHECK(enable); - - rv = hppe_mac_mib_ctrl_mib_rd_clr_get(dev_id, port_id, &status); - - if (status == A_TRUE) - { - *enable = A_FALSE; - } - else - { - *enable = A_TRUE; - } - - if( rv != SW_OK ) - { - return rv; - } - - return SW_OK; -} - -sw_error_t -adpt_ppe_mib_cpukeep_set(a_uint32_t dev_id, a_bool_t enable) -{ - a_uint32_t port_id = 0, g_port_id = 0; - sw_error_t rv = SW_OK; - - ADPT_DEV_ID_CHECK(dev_id); - - for (port_id = SSDK_PHYSICAL_PORT1; port_id <= SSDK_PHYSICAL_PORT6; port_id++) - { -#ifdef CPPE - if (adpt_hppe_chip_revision_get(dev_id) == CPPE_REVISION && - port_id == SSDK_PHYSICAL_PORT6) - { - rv = adpt_cppe_lpbk_mib_cpukeep_set(dev_id, port_id, enable); - SW_RTN_ON_ERROR(rv); - continue; - } -#endif - g_port_id = HPPE_TO_GMAC_PORT_ID(port_id); - hppe_mac_mib_ctrl_mib_rd_clr_set(dev_id, g_port_id, (a_uint32_t)(!enable)); - } - - return rv; -} - -static sw_error_t -adpt_hppe_get_mib_info(a_uint32_t dev_id, fal_port_t port_id, - fal_mib_info_t * mib_info ) -{ - ADPT_DEV_ID_CHECK(dev_id); - ADPT_NULL_POINT_CHECK(mib_info); - memset(mib_info, 0, sizeof(fal_mib_info_t)); - - port_id = HPPE_TO_GMAC_PORT_ID(port_id); - hppe_rxbroad_get(dev_id, (a_uint32_t)port_id, (union rxbroad_u *)&mib_info->RxBroad); - hppe_rxpause_get(dev_id, (a_uint32_t)port_id, (union rxpause_u *)&mib_info->RxPause); - hppe_rxmulti_get(dev_id, (a_uint32_t)port_id, (union rxmulti_u *)&mib_info->RxMulti); - hppe_rxfcserr_get(dev_id, (a_uint32_t)port_id, (union rxfcserr_u *)&mib_info->RxFcsErr); - hppe_rxalignerr_get(dev_id, (a_uint32_t)port_id, - (union rxalignerr_u *)&mib_info->RxAllignErr); - hppe_rxrunt_get(dev_id, (a_uint32_t)port_id, (union rxrunt_u *)&mib_info->RxRunt); - hppe_rxfrag_get(dev_id, (a_uint32_t)port_id, (union rxfrag_u *)&mib_info->RxFragment); - hppe_rxjumbofcserr_get(dev_id, (a_uint32_t)port_id, - (union rxjumbofcserr_u *)&mib_info->RxJumboFcsErr); - hppe_rxjumboalignerr_get(dev_id, (a_uint32_t)port_id, - (union rxjumboalignerr_u *)&mib_info->RxJumboAligenErr); - hppe_rxpkt64_get(dev_id, (a_uint32_t)port_id, (union rxpkt64_u *)&mib_info->Rx64Byte); - hppe_rxpkt65to127_get(dev_id, (a_uint32_t)port_id, - (union rxpkt65to127_u *)&mib_info->Rx128Byte); - hppe_rxpkt128to255_get(dev_id, (a_uint32_t)port_id, - (union rxpkt128to255_u *)&mib_info->Rx256Byte); - hppe_rxpkt256to511_get(dev_id, (a_uint32_t)port_id, - (union rxpkt256to511_u *)&mib_info->Rx512Byte); - hppe_rxpkt512to1023_get(dev_id, (a_uint32_t)port_id, - (union rxpkt512to1023_u *)&mib_info->Rx1024Byte); - hppe_rxpkt1024to1518_get(dev_id, (a_uint32_t)port_id, - (union rxpkt1024to1518_u *)&mib_info->Rx1518Byte); - hppe_rxpkt1519tox_get(dev_id, (a_uint32_t)port_id, - (union rxpkt1519tox_u *)&mib_info->RxMaxByte); - hppe_rxtoolong_get(dev_id, (a_uint32_t)port_id, - (union rxtoolong_u *)&mib_info->RxTooLong); - hppe_rxgoodbyte_l_get(dev_id, (a_uint32_t)port_id, - (union rxgoodbyte_l_u *)&mib_info->RxGoodByte_lo); - hppe_rxgoodbyte_h_get(dev_id, (a_uint32_t)port_id, - (union rxgoodbyte_h_u *)&mib_info->RxGoodByte_hi); - hppe_rxbadbyte_l_get(dev_id, (a_uint32_t)port_id, - (union rxbadbyte_l_u *)&mib_info->RxBadByte_lo); - hppe_rxbadbyte_h_get(dev_id, (a_uint32_t)port_id, - (union rxbadbyte_h_u *)&mib_info->RxBadByte_hi); - hppe_rxuni_get(dev_id, (a_uint32_t)port_id, (union rxuni_u *)&mib_info->RxUniCast); - hppe_txbroad_get(dev_id, (a_uint32_t)port_id, (union txbroad_u *)&mib_info->TxBroad); - hppe_txpause_get(dev_id, (a_uint32_t)port_id, (union txpause_u *)&mib_info->TxPause); - hppe_txmulti_get(dev_id, (a_uint32_t)port_id, (union txmulti_u *)&mib_info->TxMulti); - hppe_txunderrun_get(dev_id, (a_uint32_t)port_id, - (union txunderrun_u *)&mib_info->TxUnderRun); - hppe_txpkt64_get(dev_id, (a_uint32_t)port_id, (union txpkt64_u *)&mib_info->Tx64Byte); - hppe_txpkt65to127_get(dev_id, (a_uint32_t)port_id, - (union txpkt65to127_u *)&mib_info->Tx128Byte); - hppe_txpkt128to255_get(dev_id, (a_uint32_t)port_id, - (union txpkt128to255_u *)&mib_info->Tx256Byte); - hppe_txpkt256to511_get(dev_id, (a_uint32_t)port_id, - (union txpkt256to511_u *)&mib_info->Tx512Byte); - hppe_txpkt512to1023_get(dev_id, (a_uint32_t)port_id, - (union txpkt512to1023_u *)&mib_info->Tx1024Byte); - hppe_txpkt1024to1518_get(dev_id, (a_uint32_t)port_id, - (union txpkt1024to1518_u *)&mib_info->Tx1518Byte); - hppe_txpkt1519tox_get(dev_id, (a_uint32_t)port_id, - (union txpkt1519tox_u *)&mib_info->TxMaxByte); - hppe_txbyte_l_get(dev_id, (a_uint32_t)port_id, - (union txbyte_l_u *)&mib_info->TxByte_lo); - hppe_txbyte_h_get(dev_id, (a_uint32_t)port_id, - (union txbyte_h_u *)&mib_info->TxByte_hi); - hppe_txcollisions_get(dev_id, (a_uint32_t)port_id, - (union txcollisions_u *)&mib_info->TxCollision); - hppe_txabortcol_get(dev_id, (a_uint32_t)port_id, - (union txabortcol_u *)&mib_info->TxAbortCol); - hppe_txmulticol_get(dev_id, (a_uint32_t)port_id, - (union txmulticol_u *)&mib_info->TxMultiCol); - hppe_txsinglecol_get(dev_id, (a_uint32_t)port_id, - (union txsinglecol_u *)&mib_info->TxSingalCol); - hppe_txexcessivedefer_get(dev_id, (a_uint32_t)port_id, - (union txexcessivedefer_u *)&mib_info->TxExcDefer); - hppe_txdefer_get(dev_id, (a_uint32_t)port_id, (union txdefer_u *)&mib_info->TxDefer); - hppe_txlatecol_get(dev_id, (a_uint32_t)port_id, (union txlatecol_u *)&mib_info->TxLateCol); - hppe_txuni_get(dev_id, (a_uint32_t)port_id, (union txuni_u *)&mib_info->TxUniCast); - - return SW_OK; -} - -sw_error_t -adpt_ppe_get_mib_info(a_uint32_t dev_id, fal_port_t port_id, - fal_mib_info_t * mib_info) -{ - ADPT_DEV_ID_CHECK(dev_id); - ADPT_NULL_POINT_CHECK(mib_info); -#ifdef CPPE - if (adpt_hppe_chip_revision_get(dev_id) == CPPE_REVISION && - port_id == SSDK_PHYSICAL_PORT6) - { - return adpt_cppe_lpbk_get_mib_info(dev_id, port_id, mib_info); - } -#endif - return adpt_hppe_get_mib_info(dev_id, port_id, mib_info); -} - -sw_error_t -adpt_hppe_get_tx_mib_info(a_uint32_t dev_id, fal_port_t port_id, - fal_mib_info_t * mib_info ) -{ - ADPT_DEV_ID_CHECK(dev_id); - ADPT_NULL_POINT_CHECK(mib_info); - memset(mib_info, 0, sizeof(fal_mib_info_t)); - - port_id = HPPE_TO_GMAC_PORT_ID(port_id); - hppe_txbroad_get(dev_id, (a_uint32_t)port_id, (union txbroad_u *)&mib_info->TxBroad); - hppe_txpause_get(dev_id, (a_uint32_t)port_id, (union txpause_u *)&mib_info->TxPause); - hppe_txmulti_get(dev_id, (a_uint32_t)port_id, (union txmulti_u *)&mib_info->TxMulti); - hppe_txunderrun_get(dev_id, (a_uint32_t)port_id, - (union txunderrun_u *)&mib_info->TxUnderRun); - hppe_txpkt64_get(dev_id, (a_uint32_t)port_id, (union txpkt64_u *)&mib_info->Tx64Byte); - hppe_txpkt65to127_get(dev_id, (a_uint32_t)port_id, - (union txpkt65to127_u *)&mib_info->Tx128Byte); - hppe_txpkt128to255_get(dev_id, (a_uint32_t)port_id, - (union txpkt128to255_u *)&mib_info->Tx256Byte); - hppe_txpkt256to511_get(dev_id, (a_uint32_t)port_id, - (union txpkt256to511_u *)&mib_info->Tx512Byte); - hppe_txpkt512to1023_get(dev_id, (a_uint32_t)port_id, - (union txpkt512to1023_u *)&mib_info->Tx1024Byte); - hppe_txpkt1024to1518_get(dev_id, (a_uint32_t)port_id, - (union txpkt1024to1518_u *)&mib_info->Tx1518Byte); - hppe_txpkt1519tox_get(dev_id, (a_uint32_t)port_id, - (union txpkt1519tox_u *)&mib_info->TxMaxByte); - hppe_txbyte_l_get(dev_id, (a_uint32_t)port_id, (union txbyte_l_u *)&mib_info->TxByte_lo); - hppe_txbyte_h_get(dev_id, (a_uint32_t)port_id, (union txbyte_h_u *)&mib_info->TxByte_hi); - hppe_txcollisions_get(dev_id, (a_uint32_t)port_id, - (union txcollisions_u *)&mib_info->TxCollision); - hppe_txabortcol_get(dev_id, (a_uint32_t)port_id, - (union txabortcol_u *)&mib_info->TxAbortCol); - hppe_txmulticol_get(dev_id, (a_uint32_t)port_id, - (union txmulticol_u *)&mib_info->TxMultiCol); - hppe_txsinglecol_get(dev_id, (a_uint32_t)port_id, - (union txsinglecol_u *)&mib_info->TxSingalCol); - hppe_txexcessivedefer_get(dev_id, (a_uint32_t)port_id, - (union txexcessivedefer_u *)&mib_info->TxExcDefer); - hppe_txdefer_get(dev_id, (a_uint32_t)port_id, (union txdefer_u *)&mib_info->TxDefer); - hppe_txlatecol_get(dev_id, (a_uint32_t)port_id, - (union txlatecol_u *)&mib_info->TxLateCol); - hppe_txuni_get(dev_id, (a_uint32_t)port_id, (union txuni_u *)&mib_info->TxUniCast); - - return SW_OK; -} - -sw_error_t -adpt_ppe_mib_status_set(a_uint32_t dev_id, a_bool_t enable) -{ - a_uint32_t port_id = 0, xg_port_id = 0, g_port_id = 0; - a_uint32_t port_num = SSDK_PHYSICAL_PORT6; - union mmc_control_u mmc_control; - sw_error_t rv = SW_OK; - - memset(&mmc_control, 0, sizeof(mmc_control)); - ADPT_DEV_ID_CHECK(dev_id); -#ifdef CPPE - if (adpt_hppe_chip_revision_get(dev_id) == CPPE_REVISION) - { - port_num = SSDK_PHYSICAL_PORT5; - rv = adpt_cppe_lpbk_mib_status_set(dev_id, SSDK_PHYSICAL_PORT6, enable); - SW_RTN_ON_ERROR(rv); - } -#endif - for (port_id = SSDK_PHYSICAL_PORT1; port_id <= port_num; port_id++) { - g_port_id = HPPE_TO_GMAC_PORT_ID(port_id); - hppe_mac_mib_ctrl_mib_en_set(dev_id, g_port_id, (a_uint32_t)enable); - } - - for (port_id = SSDK_PHYSICAL_PORT5; port_id <= port_num; port_id++) { - xg_port_id = HPPE_TO_XGMAC_PORT_ID(port_id); - hppe_mmc_control_get(dev_id, xg_port_id, &mmc_control); - - if(A_TRUE == enable) - mmc_control.bf.mcf = 0; - else - mmc_control.bf.mcf = 1; - - hppe_mmc_control_set(dev_id, xg_port_id, &mmc_control); - } - - return rv; -} - -sw_error_t -adpt_hppe_mib_port_flush_counters(a_uint32_t dev_id, fal_port_t port_id) -{ - union mmc_control_u mmc_control; - - memset(&mmc_control, 0, sizeof(mmc_control)); - ADPT_DEV_ID_CHECK(dev_id); - - if(port_id < SSDK_PHYSICAL_PORT1 || port_id > SSDK_PHYSICAL_PORT6) - return SW_BAD_PARAM; - /*GMAC*/ - if(!hppe_xgmac_port_check(port_id)) - { - port_id = HPPE_TO_GMAC_PORT_ID(port_id); - hppe_mac_mib_ctrl_mib_reset_set(dev_id, port_id, A_TRUE); - hppe_mac_mib_ctrl_mib_reset_set(dev_id, port_id, A_FALSE); - } - /*XGMAC*/ - else - { - port_id = HPPE_TO_XGMAC_PORT_ID(port_id); - hppe_mmc_control_get(dev_id, port_id, &mmc_control); - mmc_control.bf.cntrst = 1; - hppe_mmc_control_set(dev_id, port_id, &mmc_control); - } - - return SW_OK; -} - -sw_error_t -adpt_ppe_mib_port_flush_counters(a_uint32_t dev_id, fal_port_t port_id) -{ -#ifdef CPPE - if (adpt_hppe_chip_revision_get(dev_id) == CPPE_REVISION && - port_id == SSDK_PHYSICAL_PORT6) - { - return adpt_cppe_lpbk_mib_flush_counters(dev_id, port_id); - } -#endif - return adpt_hppe_mib_port_flush_counters(dev_id, port_id); -} - -sw_error_t -adpt_hppe_mib_status_get(a_uint32_t dev_id, a_bool_t * enable) -{ - sw_error_t rv = SW_OK; - a_uint32_t port_id = 0, status = 0; - - ADPT_DEV_ID_CHECK(dev_id); - ADPT_NULL_POINT_CHECK(enable); - - rv = hppe_mac_mib_ctrl_mib_en_get(dev_id, port_id, &status); - *enable = status; - - if( rv != SW_OK ) - return rv; - - return SW_OK; -} - -sw_error_t -adpt_hppe_get_rx_mib_info(a_uint32_t dev_id, fal_port_t port_id, - fal_mib_info_t * mib_info ) -{ - ADPT_DEV_ID_CHECK(dev_id); - ADPT_NULL_POINT_CHECK(mib_info); - memset(mib_info, 0, sizeof(fal_mib_info_t)); - - port_id = HPPE_TO_GMAC_PORT_ID(port_id); - hppe_rxbroad_get(dev_id, (a_uint32_t)port_id, (union rxbroad_u *)&mib_info->RxBroad); - hppe_rxpause_get(dev_id, (a_uint32_t)port_id, (union rxpause_u *)&mib_info->RxPause); - hppe_rxmulti_get(dev_id, (a_uint32_t)port_id, (union rxmulti_u *)&mib_info->RxMulti); - hppe_rxfcserr_get(dev_id, (a_uint32_t)port_id, (union rxfcserr_u *)&mib_info->RxFcsErr); - hppe_rxalignerr_get(dev_id, (a_uint32_t)port_id, - (union rxalignerr_u *)&mib_info->RxAllignErr); - hppe_rxrunt_get(dev_id, (a_uint32_t)port_id, (union rxrunt_u *)&mib_info->RxRunt); - hppe_rxfrag_get(dev_id, (a_uint32_t)port_id, (union rxfrag_u *)&mib_info->RxFragment); - hppe_rxjumbofcserr_get(dev_id, (a_uint32_t)port_id, - (union rxjumbofcserr_u *)&mib_info->RxJumboFcsErr); - hppe_rxjumboalignerr_get(dev_id, (a_uint32_t)port_id, - (union rxjumboalignerr_u *)&mib_info->RxJumboAligenErr); - hppe_rxpkt64_get(dev_id, (a_uint32_t)port_id, (union rxpkt64_u *)&mib_info->Rx64Byte); - hppe_rxpkt65to127_get(dev_id, (a_uint32_t)port_id, - (union rxpkt65to127_u *)&mib_info->Rx128Byte); - hppe_rxpkt128to255_get(dev_id, (a_uint32_t)port_id, - (union rxpkt128to255_u *)&mib_info->Rx256Byte); - hppe_rxpkt256to511_get(dev_id, (a_uint32_t)port_id, - (union rxpkt256to511_u *)&mib_info->Rx512Byte); - hppe_rxpkt512to1023_get(dev_id, (a_uint32_t)port_id, - (union rxpkt512to1023_u *)&mib_info->Rx1024Byte); - hppe_rxpkt1024to1518_get(dev_id, (a_uint32_t)port_id, - (union rxpkt1024to1518_u *)&mib_info->Rx1518Byte); - hppe_rxpkt1519tox_get(dev_id, (a_uint32_t)port_id, - (union rxpkt1519tox_u *)&mib_info->RxMaxByte); - hppe_rxtoolong_get(dev_id, (a_uint32_t)port_id, - (union rxtoolong_u *)&mib_info->RxTooLong); - hppe_rxgoodbyte_l_get(dev_id, (a_uint32_t)port_id, - (union rxgoodbyte_l_u *)&mib_info->RxGoodByte_lo); - hppe_rxgoodbyte_h_get(dev_id, (a_uint32_t)port_id, - (union rxgoodbyte_h_u *)&mib_info->RxGoodByte_hi); - hppe_rxbadbyte_l_get(dev_id, (a_uint32_t)port_id, - (union rxbadbyte_l_u *)&mib_info->RxBadByte_lo); - hppe_rxbadbyte_h_get(dev_id, (a_uint32_t)port_id, - (union rxbadbyte_h_u *)&mib_info->RxBadByte_hi); - hppe_rxuni_get(dev_id, (a_uint32_t)port_id, (union rxuni_u *)&mib_info->RxUniCast); - - return SW_OK; -} - -sw_error_t -adpt_ppe_get_rx_mib_info(a_uint32_t dev_id, fal_port_t port_id, - fal_mib_info_t * mib_info) -{ - ADPT_DEV_ID_CHECK(dev_id); - ADPT_NULL_POINT_CHECK(mib_info); -#ifdef CPPE - if (adpt_hppe_chip_revision_get(dev_id) == CPPE_REVISION && - port_id == SSDK_PHYSICAL_PORT6) - { - return adpt_cppe_lpbk_get_mib_info(dev_id, port_id, mib_info); - } -#endif - return adpt_hppe_get_rx_mib_info(dev_id, port_id, mib_info); -} - -void adpt_hppe_mib_func_bitmap_init(a_uint32_t dev_id) -{ - adpt_api_t *p_adpt_api = NULL; - - p_adpt_api = adpt_api_ptr_get(dev_id); - - if(p_adpt_api == NULL) - return; - - p_adpt_api->adpt_mib_func_bitmap = ((1<adpt_get_mib_info = NULL; - p_adpt_api->adpt_get_rx_mib_info = NULL; - p_adpt_api->adpt_get_tx_mib_info = NULL; - p_adpt_api->adpt_mib_status_set = NULL; - p_adpt_api->adpt_mib_status_get = NULL; - p_adpt_api->adpt_mib_port_flush_counters = NULL; - p_adpt_api->adpt_mib_cpukeep_set = NULL; - p_adpt_api->adpt_mib_cpukeep_get = NULL; - p_adpt_api->adpt_get_xgmib_info = NULL; - p_adpt_api->adpt_get_tx_xgmib_info = NULL; - p_adpt_api->adpt_get_rx_xgmib_info = NULL; - - return; -} - -sw_error_t -adpt_hppe_get_xgmib_info(a_uint32_t dev_id, fal_port_t port_id, - fal_xgmib_info_t * mib_info ) -{ - a_uint64_t data_low , data_high ; - - ADPT_DEV_ID_CHECK(dev_id); - ADPT_NULL_POINT_CHECK(mib_info); - memset(mib_info, 0, sizeof( * mib_info )); - - if(!(hppe_xgmac_port_check(port_id))) - { - printk("this port is not xg port!\n"); - return SW_FAIL; - } - port_id = HPPE_TO_XGMAC_PORT_ID(port_id); - - /*get tx xgmib information*/ - data_low = 0; data_high = 0; - hppe_tx_octet_count_good_bad_low_get(dev_id, port_id, (union tx_octet_count_good_bad_low_u*)&data_low); - hppe_tx_octet_count_good_bad_high_get(dev_id, port_id, (union tx_octet_count_good_bad_high_u *)&data_high); - mib_info->TxByte = (data_high<<32) |data_low; - - data_low = 0; data_high = 0; - hppe_tx_frame_count_good_bad_low_get(dev_id, port_id, (union tx_frame_count_good_bad_low_u *)&data_low); - hppe_tx_frame_count_good_bad_high_get(dev_id, port_id, (union tx_frame_count_good_bad_high_u *)&data_high); - mib_info->TxFrame = (data_high<<32) |data_low; - - data_low = 0; data_high = 0; - hppe_tx_broadcast_frames_good_low_get(dev_id, port_id, (union tx_broadcast_frames_good_low_u *)&data_low); - hppe_tx_broadcast_frames_good_high_get(dev_id, port_id, (union tx_broadcast_frames_good_high_u*)&data_high); - mib_info->TxBroadGood = (data_high<<32) |data_low; - - data_low = 0; data_high = 0; - hppe_tx_multicast_frames_good_low_get(dev_id, port_id, (union tx_multicast_frames_good_low_u*)&data_low); - hppe_tx_multicast_frames_good_high_get(dev_id, port_id, (union tx_multicast_frames_good_high_u*)&data_high); - mib_info->TxMultiGood = (data_high<<32) |data_low; - - data_low = 0; data_high = 0; - hppe_tx_64octets_frames_good_bad_low_get(dev_id, port_id, (union tx_64octets_frames_good_bad_low_u*)&data_low); - hppe_tx_64octets_frames_good_bad_high_get(dev_id, port_id, (union tx_64octets_frames_good_bad_high_u*)&data_high); - mib_info->Tx64Byte = (data_high<<32) |data_low; - - data_low = 0; data_high = 0; - hppe_tx_65to127octets_frames_good_bad_low_get(dev_id, port_id, (union tx_65to127octets_frames_good_bad_low_u *)&data_low); - hppe_tx_65to127octets_frames_good_bad_high_get(dev_id, port_id, (union tx_65to127octets_frames_good_bad_high_u *)&data_high); - mib_info->Tx128Byte = (data_high<<32) |data_low; - - data_low = 0; data_high = 0; - hppe_tx_128to255octets_frames_good_bad_low_get(dev_id, port_id, (union tx_128to255octets_frames_good_bad_low_u *)&data_low); - hppe_tx_128to255octets_frames_good_bad_high_get(dev_id, port_id, (union tx_128to255octets_frames_good_bad_high_u *)&data_high); - mib_info->Tx256Byte = (data_high<<32) |data_low; - - data_low = 0; data_high = 0; - hppe_tx_256to511octets_frames_good_bad_low_get(dev_id, port_id, (union tx_256to511octets_frames_good_bad_low_u *)&data_low); - hppe_tx_256to511octets_frames_good_bad_high_get(dev_id, port_id, (union tx_256to511octets_frames_good_bad_high_u *)&data_high); - mib_info->Tx512Byte = (data_high<<32) |data_low; - - data_low = 0; data_high = 0; - hppe_tx_512to1023octets_frames_good_bad_low_get(dev_id, port_id, (union tx_512to1023octets_frames_good_bad_low_u*)&data_low); - hppe_tx_512to1023octets_frames_good_bad_high_get(dev_id, port_id, (union tx_512to1023octets_frames_good_bad_high_u*)&data_high); - mib_info->Tx1024Byte = (data_high<<32) |data_low; - - data_low = 0; data_high = 0; - hppe_tx_1024tomaxoctets_frames_good_bad_low_get(dev_id, port_id, (union tx_1024tomaxoctets_frames_good_bad_low_u*)&data_low); - hppe_tx_1024tomaxoctets_frames_good_bad_high_get(dev_id, port_id, (union tx_1024tomaxoctets_frames_good_bad_high_u*)&data_high); - mib_info->TxMaxByte = (data_high<<32) |data_low; - - data_low = 0; data_high = 0; - hppe_tx_unicast_frames_good_bad_low_get(dev_id, port_id, (union tx_unicast_frames_good_bad_low_u*)&data_low); - hppe_tx_unicast_frames_good_bad_high_get(dev_id, port_id, (union tx_unicast_frames_good_bad_high_u*)&data_high); - mib_info->TxUnicast = (data_high<<32) |data_low; - - data_low = 0; data_high = 0; - hppe_tx_multicast_frames_good_bad_low_get(dev_id, port_id, (union tx_multicast_frames_good_bad_low_u *)&data_low); - hppe_tx_multicast_frames_good_bad_high_get(dev_id, port_id, (union tx_multicast_frames_good_bad_high_u *)&data_high); - mib_info->TxMulti = (data_high<<32) |data_low; - - data_low = 0; data_high = 0; - hppe_tx_broadcast_frames_good_bad_low_get(dev_id, port_id, (union tx_broadcast_frames_good_bad_low_u*)&data_low); - hppe_tx_broadcast_frames_good_bad_high_get(dev_id, port_id, (union tx_broadcast_frames_good_bad_high_u*)&data_high); - mib_info->TxBroad = (data_high<<32) |data_low; - - data_low = 0; data_high = 0; - hppe_tx_underflow_error_frames_low_get(dev_id, port_id, (union tx_underflow_error_frames_low_u*)&data_low); - hppe_tx_underflow_error_frames_high_get(dev_id, port_id, (union tx_underflow_error_frames_high_u*)&data_high); - mib_info->TxUnderFlowError = (data_high<<32) |data_low; - - data_low = 0; data_high = 0; - hppe_tx_octet_count_good_low_get(dev_id, port_id, (union tx_octet_count_good_low_u*)&data_low); - hppe_tx_octet_count_good_high_get(dev_id, port_id, (union tx_octet_count_good_high_u*)&data_high); - mib_info->TxByteGood = (data_high<<32) |data_low; - - data_low = 0; data_high = 0; - hppe_tx_frame_count_good_low_get(dev_id, port_id, (union tx_frame_count_good_low_u*)&data_low); - hppe_tx_frame_count_good_high_get(dev_id, port_id, (union tx_frame_count_good_high_u*)&data_high); - mib_info->TxFrameGood = (data_high<<32) |data_low; - - data_low = 0; data_high = 0; - hppe_tx_pause_frames_low_get(dev_id, port_id, (union tx_pause_frames_low_u *)&data_low); - hppe_tx_pause_frames_high_get(dev_id, port_id, (union tx_pause_frames_high_u *)&data_high); - mib_info->TxPause = (data_high<<32) |data_low; - - data_low = 0; data_high = 0; - hppe_tx_vlan_frames_good_low_get(dev_id, port_id, (union tx_vlan_frames_good_low_u *)&data_low); - hppe_tx_vlan_frames_good_high_get(dev_id, port_id, (union tx_vlan_frames_good_high_u *)&data_high); - mib_info->TxVLANFrameGood = (data_high<<32) |data_low; - - data_low = 0; - hppe_tx_lpi_usec_cntr_get(dev_id, port_id, (union tx_lpi_usec_cntr_u *)&data_low); - mib_info->TxLPIUsec = data_low; - - data_low = 0; - hppe_tx_lpi_tran_cntr_get(dev_id, port_id, (union tx_lpi_tran_cntr_u *)&data_low); - mib_info->TxLPITran = data_low; - - /*get rx xgmib information*/ - data_low = 0; data_high = 0; - hppe_rx_frame_count_good_bad_low_get(dev_id, port_id, (union rx_frame_count_good_bad_low_u *)&data_low); - hppe_rx_frame_count_good_bad_high_get(dev_id, port_id, (union rx_frame_count_good_bad_high_u *)&data_high); - mib_info->RxFrame = (data_high<<32) |data_low; - - data_low = 0; data_high = 0; - hppe_rx_octet_count_good_bad_low_get(dev_id, port_id, (union rx_octet_count_good_bad_low_u*)&data_low); - hppe_rx_octet_count_good_bad_high_get(dev_id, port_id, (union rx_octet_count_good_bad_high_u*)&data_high); - mib_info->RxByte = (data_high<<32) |data_low; - - data_low = 0; data_high = 0; - hppe_rx_octet_count_good_low_get(dev_id, port_id, (union rx_octet_count_good_low_u *)&data_low); - hppe_rx_octet_count_good_high_get(dev_id, port_id, (union rx_octet_count_good_high_u *)&data_high); - mib_info->RxByteGood = (data_high<<32) |data_low; - - data_low = 0; data_high = 0; - hppe_rx_broadcast_frames_good_low_get(dev_id, port_id, (union rx_broadcast_frames_good_low_u *)&data_low); - hppe_rx_broadcast_frames_good_high_get(dev_id, port_id, (union rx_broadcast_frames_good_high_u*)&data_high); - mib_info->RxBroadGood = (data_high<<32) |data_low; - - data_low = 0; data_high = 0; - hppe_rx_multicast_frames_good_low_get(dev_id, port_id, (union rx_multicast_frames_good_low_u*)&data_low); - hppe_rx_multicast_frames_good_high_get(dev_id, port_id, (union rx_multicast_frames_good_high_u*)&data_high); - mib_info->RxMultiGood = (data_high<<32) |data_low; - - data_low = 0; data_high = 0; - hppe_rx_crc_error_frames_low_get(dev_id, port_id, (union rx_crc_error_frames_low_u *)&data_low); - hppe_rx_crc_error_frames_high_get(dev_id, port_id, (union rx_crc_error_frames_high_u *)&data_high); - mib_info->RxFcsErr = (data_high<<32) |data_low; - - data_low = 0; - hppe_rx_runt_error_frames_get(dev_id, port_id, (union rx_runt_error_frames_u *)&data_low); - mib_info->RxRuntErr = data_low; - - data_low = 0; - hppe_rx_jabber_error_frames_get(dev_id, port_id, (union rx_jabber_error_frames_u *)&data_low); - mib_info->RxJabberError = data_low; - - data_low = 0; - hppe_rx_undersize_frames_good_get(dev_id, port_id, (union rx_undersize_frames_good_u *)&data_low); - mib_info->RxUndersizeGood = data_low; - - data_low = 0; - hppe_rx_oversize_frames_good_get(dev_id, port_id, (union rx_oversize_frames_good_u *)&data_low); - mib_info->RxOversizeGood = data_low; - - data_low = 0; data_high = 0; - hppe_rx_64octets_frames_good_bad_low_get(dev_id, port_id, (union rx_64octets_frames_good_bad_low_u *)&data_low); - hppe_rx_64octets_frames_good_bad_high_get(dev_id, port_id, (union rx_64octets_frames_good_bad_high_u *)&data_high); - mib_info->Rx64Byte = (data_high<<32) |data_low; - - data_low = 0; data_high = 0; - hppe_rx_65to127octets_frames_good_bad_low_get(dev_id, port_id, (union rx_65to127octets_frames_good_bad_low_u *)&data_low); - hppe_rx_65to127octets_frames_good_bad_high_get(dev_id, port_id, (union rx_65to127octets_frames_good_bad_high_u *)&data_high); - mib_info->Rx128Byte = (data_high<<32) |data_low; - - data_low = 0; data_high = 0; - hppe_rx_128to255octets_frames_good_bad_low_get(dev_id, port_id, (union rx_128to255octets_frames_good_bad_low_u *)&data_low); - hppe_rx_128to255octets_frames_good_bad_high_get(dev_id, port_id, (union rx_128to255octets_frames_good_bad_high_u *)&data_high); - mib_info->Rx256Byte = (data_high<<32) |data_low; - - data_low = 0; data_high = 0; - hppe_rx_256to511octets_frames_good_bad_low_get (dev_id, port_id, (union rx_256to511octets_frames_good_bad_low_u *)&data_low); - hppe_rx_256to511octets_frames_good_bad_high_get(dev_id, port_id, (union rx_256to511octets_frames_good_bad_high_u *)&data_high); - mib_info->Rx512Byte = (data_high<<32) |data_low; - - data_low = 0; data_high = 0; - hppe_rx_512to1023octets_frames_good_bad_low_get(dev_id, port_id, (union rx_512to1023octets_frames_good_bad_low_u *)&data_low); - hppe_rx_512to1023octets_frames_good_bad_high_get(dev_id, port_id, (union rx_512to1023octets_frames_good_bad_high_u *)&data_high); - mib_info->Rx1024Byte = (data_high<<32) |data_low; - - data_low = 0; data_high = 0; - hppe_rx_1024tomaxoctets_frames_good_bad_low_get(dev_id, port_id, (union rx_1024tomaxoctets_frames_good_bad_low_u *)&data_low); - hppe_rx_1024tomaxoctets_frames_good_bad_high_get(dev_id, port_id, (union rx_1024tomaxoctets_frames_good_bad_high_u *)&data_high); - mib_info->RxMaxByte = (data_high<<32) |data_low; - - data_low = 0; data_high = 0; - hppe_rx_unicast_frames_good_low_get(dev_id, port_id, (union rx_unicast_frames_good_low_u *)&data_low); - hppe_rx_unicast_frames_good_high_get(dev_id, port_id, (union rx_unicast_frames_good_high_u *)&data_high); - mib_info->RxUnicastGood = (data_high<<32) |data_low; - - data_low = 0; data_high = 0; - hppe_rx_length_error_frames_low_get(dev_id, port_id, (union rx_length_error_frames_low_u *)&data_low); - hppe_rx_length_error_frames_high_get(dev_id, port_id, (union rx_length_error_frames_high_u *)&data_high); - mib_info->RxLengthError = (data_high<<32) |data_low; - - data_low = 0; data_high = 0; - hppe_rx_outofrange_frames_low_get(dev_id, port_id, (union rx_outofrange_frames_low_u*)&data_low); - hppe_rx_outofrange_frames_high_get(dev_id, port_id, (union rx_outofrange_frames_high_u*)&data_high); - mib_info->RxOutOfRangeError = (data_high<<32) |data_low; - - data_low = 0; data_high = 0; - hppe_rx_pause_frames_low_get(dev_id, port_id, (union rx_pause_frames_low_u *)&data_low); - hppe_rx_pause_frames_high_get(dev_id, port_id, (union rx_pause_frames_high_u *)&data_high); - mib_info->RxPause = (data_high<<32) |data_low; - - data_low = 0; data_high = 0; - hppe_rx_fifooverflow_frames_low_get(dev_id, port_id, (union rx_fifooverflow_frames_low_u *)&data_low); - hppe_rx_fifooverflow_frames_high_get(dev_id, port_id, (union rx_fifooverflow_frames_high_u *)&data_high); - mib_info->RxOverFlow = (data_high<<32) |data_low; - - data_low = 0; data_high = 0; - hppe_rx_vlan_frames_good_bad_low_get(dev_id, port_id, (union rx_vlan_frames_good_bad_low_u *)&data_low); - hppe_rx_vlan_frames_good_bad_high_get(dev_id, port_id, (union rx_vlan_frames_good_bad_high_u*)&data_high); - mib_info->RxVLANFrameGoodBad = (data_high<<32) |data_low; - - data_low = 0; - hppe_rx_watchdog_error_frames_get(dev_id, port_id, (union rx_watchdog_error_frames_u*)&data_low); - mib_info->RxWatchDogError = data_low; - - data_low = 0; - hppe_rx_lpi_usec_cntr_get(dev_id, port_id, (union rx_lpi_usec_cntr_u *)&data_low); - mib_info->RxLPIUsec = data_low; - - data_low = 0; - hppe_rx_lpi_tran_cntr_get(dev_id, port_id, (union rx_lpi_tran_cntr_u *)&data_low); - mib_info->RxLPITran = data_low; - - data_low = 0; data_high = 0; - hppe_rx_discard_frame_count_good_bad_low_get(dev_id, port_id, (union rx_discard_frame_count_good_bad_low_u *)&data_low); - hppe_rx_discard_frame_count_good_bad_high_get(dev_id, port_id, (union rx_discard_frame_count_good_bad_high_u *)&data_high); - mib_info->RxDropFrameGoodBad = (data_high<<32) |data_low; - - data_low = 0; data_high = 0; - hppe_rx_discard_octet_count_good_bad_low_get(dev_id, port_id, (union rx_discard_octet_count_good_bad_low_u *)&data_low); - hppe_rx_discard_octet_count_good_bad_high_get(dev_id, port_id, (union rx_discard_octet_count_good_bad_high_u *)&data_high); - mib_info->RxDropByteGoodBad = (data_high<<32) |data_low; - - return SW_OK; -} - -sw_error_t -adpt_hppe_get_tx_xgmib_info(a_uint32_t dev_id, fal_port_t port_id, - fal_xgmib_info_t * mib_info ) -{ - - a_uint64_t data_low , data_high ; - - ADPT_DEV_ID_CHECK(dev_id); - ADPT_NULL_POINT_CHECK(mib_info); - memset(mib_info, 0, sizeof(* mib_info)); - - if(!(hppe_xgmac_port_check(port_id))) - { - printk("this port is not xg port!\n"); - return SW_FAIL; - } - port_id = HPPE_TO_XGMAC_PORT_ID(port_id); - - /*get tx xgmib information*/ - data_low = 0; data_high = 0; - hppe_tx_octet_count_good_bad_low_get(dev_id, port_id, (union tx_octet_count_good_bad_low_u*)&data_low); - hppe_tx_octet_count_good_bad_high_get(dev_id, port_id, (union tx_octet_count_good_bad_high_u *)&data_high); - mib_info->TxByte = (data_high<<32) |data_low; - - data_low = 0; data_high = 0; - hppe_tx_frame_count_good_bad_low_get(dev_id, port_id, (union tx_frame_count_good_bad_low_u *)&data_low); - hppe_tx_frame_count_good_bad_high_get(dev_id, port_id, (union tx_frame_count_good_bad_high_u *)&data_high); - mib_info->TxFrame = (data_high<<32) |data_low; - - data_low = 0; data_high = 0; - hppe_tx_broadcast_frames_good_low_get(dev_id, port_id, (union tx_broadcast_frames_good_low_u *)&data_low); - hppe_tx_broadcast_frames_good_high_get(dev_id, port_id, (union tx_broadcast_frames_good_high_u*)&data_high); - mib_info->TxBroadGood = (data_high<<32) |data_low; - - data_low = 0; data_high = 0; - hppe_tx_multicast_frames_good_low_get(dev_id, port_id, (union tx_multicast_frames_good_low_u*)&data_low); - hppe_tx_multicast_frames_good_high_get(dev_id, port_id, (union tx_multicast_frames_good_high_u*)&data_high); - mib_info->TxMultiGood = (data_high<<32) |data_low; - - data_low = 0; data_high = 0; - hppe_tx_64octets_frames_good_bad_low_get(dev_id, port_id, (union tx_64octets_frames_good_bad_low_u*)&data_low); - hppe_tx_64octets_frames_good_bad_high_get(dev_id, port_id, (union tx_64octets_frames_good_bad_high_u*)&data_high); - mib_info->Tx64Byte = (data_high<<32) |data_low; - - data_low = 0; data_high = 0; - hppe_tx_65to127octets_frames_good_bad_low_get(dev_id, port_id, (union tx_65to127octets_frames_good_bad_low_u *)&data_low); - hppe_tx_65to127octets_frames_good_bad_high_get(dev_id, port_id, (union tx_65to127octets_frames_good_bad_high_u *)&data_high); - mib_info->Tx128Byte = (data_high<<32) |data_low; - - data_low = 0; data_high = 0; - hppe_tx_128to255octets_frames_good_bad_low_get(dev_id, port_id, (union tx_128to255octets_frames_good_bad_low_u *)&data_low); - hppe_tx_128to255octets_frames_good_bad_high_get(dev_id, port_id, (union tx_128to255octets_frames_good_bad_high_u *)&data_high); - mib_info->Tx256Byte = (data_high<<32) |data_low; - - data_low = 0; data_high = 0; - hppe_tx_256to511octets_frames_good_bad_low_get(dev_id, port_id, (union tx_256to511octets_frames_good_bad_low_u *)&data_low); - hppe_tx_256to511octets_frames_good_bad_high_get(dev_id, port_id, (union tx_256to511octets_frames_good_bad_high_u *)&data_high); - mib_info->Tx512Byte = (data_high<<32) |data_low; - - data_low = 0; data_high = 0; - hppe_tx_512to1023octets_frames_good_bad_low_get(dev_id, port_id, (union tx_512to1023octets_frames_good_bad_low_u*)&data_low); - hppe_tx_512to1023octets_frames_good_bad_high_get(dev_id, port_id, (union tx_512to1023octets_frames_good_bad_high_u*)&data_high); - mib_info->Tx1024Byte = (data_high<<32) |data_low; - - data_low = 0; data_high = 0; - hppe_tx_1024tomaxoctets_frames_good_bad_low_get(dev_id, port_id, (union tx_1024tomaxoctets_frames_good_bad_low_u*)&data_low); - hppe_tx_1024tomaxoctets_frames_good_bad_high_get(dev_id, port_id, (union tx_1024tomaxoctets_frames_good_bad_high_u*)&data_high); - mib_info->TxMaxByte = (data_high<<32) |data_low; - - data_low = 0; data_high = 0; - hppe_tx_unicast_frames_good_bad_low_get(dev_id, port_id, (union tx_unicast_frames_good_bad_low_u*)&data_low); - hppe_tx_unicast_frames_good_bad_high_get(dev_id, port_id, (union tx_unicast_frames_good_bad_high_u*)&data_high); - mib_info->TxUnicast = (data_high<<32) |data_low; - - data_low = 0; data_high = 0; - hppe_tx_multicast_frames_good_bad_low_get(dev_id, port_id, (union tx_multicast_frames_good_bad_low_u *)&data_low); - hppe_tx_multicast_frames_good_bad_high_get(dev_id, port_id, (union tx_multicast_frames_good_bad_high_u *)&data_high); - mib_info->TxMulti = (data_high<<32) |data_low; - - data_low = 0; data_high = 0; - hppe_tx_broadcast_frames_good_bad_low_get(dev_id, port_id, (union tx_broadcast_frames_good_bad_low_u*)&data_low); - hppe_tx_broadcast_frames_good_bad_high_get(dev_id, port_id, (union tx_broadcast_frames_good_bad_high_u*)&data_high); - mib_info->TxBroad = (data_high<<32) |data_low; - - data_low = 0; data_high = 0; - hppe_tx_underflow_error_frames_low_get(dev_id, port_id, (union tx_underflow_error_frames_low_u*)&data_low); - hppe_tx_underflow_error_frames_high_get(dev_id, port_id, (union tx_underflow_error_frames_high_u*)&data_high); - mib_info->TxUnderFlowError = (data_high<<32) |data_low; - - data_low = 0; data_high = 0; - hppe_tx_octet_count_good_low_get(dev_id, port_id, (union tx_octet_count_good_low_u*)&data_low); - hppe_tx_octet_count_good_high_get(dev_id, port_id, (union tx_octet_count_good_high_u*)&data_high); - mib_info->TxByteGood = (data_high<<32) |data_low; - - data_low = 0; data_high = 0; - hppe_tx_frame_count_good_low_get(dev_id, port_id, (union tx_frame_count_good_low_u*)&data_low); - hppe_tx_frame_count_good_high_get(dev_id, port_id, (union tx_frame_count_good_high_u*)&data_high); - mib_info->TxFrameGood = (data_high<<32) |data_low; - - data_low = 0; data_high = 0; - hppe_tx_pause_frames_low_get(dev_id, port_id, (union tx_pause_frames_low_u *)&data_low); - hppe_tx_pause_frames_high_get(dev_id, port_id, (union tx_pause_frames_high_u *)&data_high); - mib_info->TxPause = (data_high<<32) |data_low; - - data_low = 0; data_high = 0; - hppe_tx_vlan_frames_good_low_get(dev_id, port_id, (union tx_vlan_frames_good_low_u *)&data_low); - hppe_tx_vlan_frames_good_high_get(dev_id, port_id, (union tx_vlan_frames_good_high_u *)&data_high); - mib_info->TxVLANFrameGood = (data_high<<32) |data_low; - - data_low = 0; - hppe_tx_lpi_usec_cntr_get(dev_id, port_id, (union tx_lpi_usec_cntr_u *)&data_low); - mib_info->TxLPIUsec = data_low; - - data_low = 0; - hppe_tx_lpi_tran_cntr_get(dev_id, port_id, (union tx_lpi_tran_cntr_u *)&data_low); - mib_info->TxLPITran = data_low; - - return SW_OK; -} - -sw_error_t -adpt_hppe_get_rx_xgmib_info(a_uint32_t dev_id, fal_port_t port_id, - fal_xgmib_info_t * mib_info ) -{ - a_uint64_t data_low , data_high ; - - ADPT_DEV_ID_CHECK(dev_id); - ADPT_NULL_POINT_CHECK(mib_info); - memset(mib_info, 0, sizeof(* mib_info)); - - if(!(hppe_xgmac_port_check(port_id))) - { - printk("this port is not xg port!\n"); - return SW_FAIL; - } - port_id = HPPE_TO_XGMAC_PORT_ID(port_id); - - /*get tx xgmib information*/ - data_low = 0; data_high = 0; - hppe_rx_frame_count_good_bad_low_get(dev_id, port_id, (union rx_frame_count_good_bad_low_u *)&data_low); - hppe_rx_frame_count_good_bad_high_get(dev_id, port_id, (union rx_frame_count_good_bad_high_u *)&data_high); - mib_info->RxFrame = (data_high<<32) |data_low; - - data_low = 0; data_high = 0; - hppe_rx_octet_count_good_bad_low_get(dev_id, port_id, (union rx_octet_count_good_bad_low_u*)&data_low); - hppe_rx_octet_count_good_bad_high_get(dev_id, port_id, (union rx_octet_count_good_bad_high_u*)&data_high); - mib_info->RxByte = (data_high<<32) |data_low; - - data_low = 0; data_high = 0; - hppe_rx_octet_count_good_low_get(dev_id, port_id, (union rx_octet_count_good_low_u *)&data_low); - hppe_rx_octet_count_good_high_get(dev_id, port_id, (union rx_octet_count_good_high_u *)&data_high); - mib_info->RxByteGood = (data_high<<32) |data_low; - - data_low = 0; data_high = 0; - hppe_rx_broadcast_frames_good_low_get(dev_id, port_id, (union rx_broadcast_frames_good_low_u *)&data_low); - hppe_rx_broadcast_frames_good_high_get(dev_id, port_id, (union rx_broadcast_frames_good_high_u*)&data_high); - mib_info->RxBroadGood = (data_high<<32) |data_low; - - data_low = 0; data_high = 0; - hppe_rx_multicast_frames_good_low_get(dev_id, port_id, (union rx_multicast_frames_good_low_u*)&data_low); - hppe_rx_multicast_frames_good_high_get(dev_id, port_id, (union rx_multicast_frames_good_high_u*)&data_high); - mib_info->RxMultiGood = (data_high<<32) |data_low; - - data_low = 0; data_high = 0; - hppe_rx_crc_error_frames_low_get(dev_id, port_id, (union rx_crc_error_frames_low_u *)&data_low); - hppe_rx_crc_error_frames_high_get(dev_id, port_id, (union rx_crc_error_frames_high_u *)&data_high); - mib_info->RxFcsErr = (data_high<<32) |data_low; - - data_low = 0; - hppe_rx_runt_error_frames_get(dev_id, port_id, (union rx_runt_error_frames_u *)&data_low); - mib_info->RxRuntErr = data_low; - - data_low = 0; - hppe_rx_jabber_error_frames_get(dev_id, port_id, (union rx_jabber_error_frames_u *)&data_low); - mib_info->RxJabberError = data_low; - - data_low = 0; - hppe_rx_undersize_frames_good_get(dev_id, port_id, (union rx_undersize_frames_good_u *)&data_low); - mib_info->RxUndersizeGood = data_low; - - data_low = 0; - hppe_rx_oversize_frames_good_get(dev_id, port_id, (union rx_oversize_frames_good_u *)&data_low); - mib_info->RxOversizeGood = data_low; - - data_low = 0; data_high = 0; - hppe_rx_64octets_frames_good_bad_low_get(dev_id, port_id, (union rx_64octets_frames_good_bad_low_u *)&data_low); - hppe_rx_64octets_frames_good_bad_high_get(dev_id, port_id, (union rx_64octets_frames_good_bad_high_u *)&data_high); - mib_info->Rx64Byte = (data_high<<32) |data_low; - - data_low = 0; data_high = 0; - hppe_rx_65to127octets_frames_good_bad_low_get(dev_id, port_id, (union rx_65to127octets_frames_good_bad_low_u *)&data_low); - hppe_rx_65to127octets_frames_good_bad_high_get(dev_id, port_id, (union rx_65to127octets_frames_good_bad_high_u *)&data_high); - mib_info->Rx128Byte = (data_high<<32) |data_low; - - data_low = 0; data_high = 0; - hppe_rx_128to255octets_frames_good_bad_low_get(dev_id, port_id, (union rx_128to255octets_frames_good_bad_low_u *)&data_low); - hppe_rx_128to255octets_frames_good_bad_high_get(dev_id, port_id, (union rx_128to255octets_frames_good_bad_high_u *)&data_high); - mib_info->Rx256Byte = (data_high<<32) |data_low; - - data_low = 0; data_high = 0; - hppe_rx_256to511octets_frames_good_bad_low_get (dev_id, port_id, (union rx_256to511octets_frames_good_bad_low_u *)&data_low); - hppe_rx_256to511octets_frames_good_bad_high_get(dev_id, port_id, (union rx_256to511octets_frames_good_bad_high_u *)&data_high); - mib_info->Rx512Byte = (data_high<<32) |data_low; - - data_low = 0; data_high = 0; - hppe_rx_512to1023octets_frames_good_bad_low_get(dev_id, port_id, (union rx_512to1023octets_frames_good_bad_low_u *)&data_low); - hppe_rx_512to1023octets_frames_good_bad_high_get(dev_id, port_id, (union rx_512to1023octets_frames_good_bad_high_u *)&data_high); - mib_info->Rx1024Byte = (data_high<<32) |data_low; - - data_low = 0; data_high = 0; - hppe_rx_1024tomaxoctets_frames_good_bad_low_get(dev_id, port_id, (union rx_1024tomaxoctets_frames_good_bad_low_u *)&data_low); - hppe_rx_1024tomaxoctets_frames_good_bad_high_get(dev_id, port_id, (union rx_1024tomaxoctets_frames_good_bad_high_u *)&data_high); - mib_info->RxMaxByte = (data_high<<32) |data_low; - - data_low = 0; data_high = 0; - hppe_rx_unicast_frames_good_low_get(dev_id, port_id, (union rx_unicast_frames_good_low_u *)&data_low); - hppe_rx_unicast_frames_good_high_get(dev_id, port_id, (union rx_unicast_frames_good_high_u *)&data_high); - mib_info->RxUnicastGood = (data_high<<32) |data_low; - - data_low = 0; data_high = 0; - hppe_rx_length_error_frames_low_get(dev_id, port_id, (union rx_length_error_frames_low_u *)&data_low); - hppe_rx_length_error_frames_high_get(dev_id, port_id, (union rx_length_error_frames_high_u *)&data_high); - mib_info->RxLengthError = (data_high<<32) |data_low; - - data_low = 0; data_high = 0; - hppe_rx_outofrange_frames_low_get(dev_id, port_id, (union rx_outofrange_frames_low_u*)&data_low); - hppe_rx_outofrange_frames_high_get(dev_id, port_id, (union rx_outofrange_frames_high_u*)&data_high); - mib_info->RxOutOfRangeError = (data_high<<32) |data_low; - - data_low = 0; data_high = 0; - hppe_rx_pause_frames_low_get(dev_id, port_id, (union rx_pause_frames_low_u *)&data_low); - hppe_rx_pause_frames_high_get(dev_id, port_id, (union rx_pause_frames_high_u *)&data_high); - mib_info->RxPause = (data_high<<32) |data_low; - - data_low = 0; data_high = 0; - hppe_rx_fifooverflow_frames_low_get(dev_id, port_id, (union rx_fifooverflow_frames_low_u *)&data_low); - hppe_rx_fifooverflow_frames_high_get(dev_id, port_id, (union rx_fifooverflow_frames_high_u *)&data_high); - mib_info->RxOverFlow = (data_high<<32) |data_low; - - data_low = 0; data_high = 0; - hppe_rx_vlan_frames_good_bad_low_get(dev_id, port_id, (union rx_vlan_frames_good_bad_low_u *)&data_low); - hppe_rx_vlan_frames_good_bad_high_get(dev_id, port_id, (union rx_vlan_frames_good_bad_high_u*)&data_high); - mib_info->RxVLANFrameGoodBad = (data_high<<32) |data_low; - - data_low = 0; - hppe_rx_watchdog_error_frames_get(dev_id, port_id, (union rx_watchdog_error_frames_u*)&data_low); - mib_info->RxWatchDogError = data_low; - - data_low = 0; - hppe_rx_lpi_usec_cntr_get(dev_id, port_id, (union rx_lpi_usec_cntr_u *)&data_low); - mib_info->RxLPIUsec = data_low; - - data_low = 0; - hppe_rx_lpi_tran_cntr_get(dev_id, port_id, (union rx_lpi_tran_cntr_u *)&data_low); - mib_info->RxLPITran = (data_high<<32) & data_low; - - data_low = 0; data_high = 0; - hppe_rx_discard_frame_count_good_bad_low_get(dev_id, port_id, (union rx_discard_frame_count_good_bad_low_u *)&data_low); - hppe_rx_discard_frame_count_good_bad_high_get(dev_id, port_id, (union rx_discard_frame_count_good_bad_high_u *)&data_high); - mib_info->RxDropFrameGoodBad = (data_high<<32) |data_low; - - data_low = 0; data_high = 0; - hppe_rx_discard_octet_count_good_bad_low_get(dev_id, port_id, (union rx_discard_octet_count_good_bad_low_u *)&data_low); - hppe_rx_discard_octet_count_good_bad_high_get(dev_id, port_id, (union rx_discard_octet_count_good_bad_high_u *)&data_high); - mib_info->RxDropByteGoodBad = (data_high<<32) |data_low; - - return SW_OK; -} - -sw_error_t adpt_hppe_mib_init(a_uint32_t dev_id) -{ - adpt_api_t *p_adpt_api = NULL; - - p_adpt_api = adpt_api_ptr_get(dev_id); - - if(p_adpt_api == NULL) - return SW_FAIL; - - adpt_hppe_mib_func_unregister(dev_id, p_adpt_api); - - if(p_adpt_api->adpt_mib_func_bitmap & (1<adpt_get_mib_info = adpt_ppe_get_mib_info; - } - if(p_adpt_api->adpt_mib_func_bitmap & (1<adpt_get_rx_mib_info = adpt_ppe_get_rx_mib_info; - } - if(p_adpt_api->adpt_mib_func_bitmap & (1<adpt_get_tx_mib_info = adpt_hppe_get_tx_mib_info; - } - if(p_adpt_api->adpt_mib_func_bitmap & (1<adpt_mib_status_set = adpt_ppe_mib_status_set; - } - if(p_adpt_api->adpt_mib_func_bitmap & (1<adpt_mib_status_get = adpt_hppe_mib_status_get; - } - if(p_adpt_api->adpt_mib_func_bitmap & (1<adpt_mib_port_flush_counters = adpt_ppe_mib_port_flush_counters; - } - if(p_adpt_api->adpt_mib_func_bitmap & (1<adpt_mib_cpukeep_set = adpt_ppe_mib_cpukeep_set; - } - if(p_adpt_api->adpt_mib_func_bitmap & (1<adpt_mib_cpukeep_get = adpt_hppe_mib_cpukeep_get; - } - if(p_adpt_api->adpt_mib_func_bitmap & (1<adpt_get_xgmib_info= adpt_hppe_get_xgmib_info; - } - if(p_adpt_api->adpt_mib_func_bitmap & (1<adpt_get_tx_xgmib_info = adpt_hppe_get_tx_xgmib_info; - } - if(p_adpt_api->adpt_mib_func_bitmap & (1<adpt_get_rx_xgmib_info = adpt_hppe_get_rx_xgmib_info; - } - - return SW_OK; -} - -/** - * @} - */ diff --git a/feeds/ipq807x/qca-ssdk/src/src/adpt/hppe/adpt_hppe_mirror.c b/feeds/ipq807x/qca-ssdk/src/src/adpt/hppe/adpt_hppe_mirror.c deleted file mode 100755 index 346e95e60..000000000 --- a/feeds/ipq807x/qca-ssdk/src/src/adpt/hppe/adpt_hppe_mirror.c +++ /dev/null @@ -1,345 +0,0 @@ -/* - * Copyright (c) 2016-2017, The Linux Foundation. All rights reserved. - * Permission to use, copy, modify, and/or distribute this software for - * any purpose with or without fee is hereby granted, provided that the - * above copyright notice and this permission notice appear in all copies. - * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES - * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR - * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES - * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN - * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT - * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. - */ - - -/** - * @defgroup - * @{ - */ -#include "sw.h" -#include "hppe_mirror_reg.h" -#include "hppe_mirror.h" -#include "hppe_qm_reg.h" -#include "hppe_qm.h" -#include "adpt.h" - -sw_error_t -adpt_hppe_mirr_port_in_get(a_uint32_t dev_id, fal_port_t port_id, - a_bool_t * enable) -{ - sw_error_t rv = SW_OK; - union port_mirror_u port_mirror; - - memset(&port_mirror, 0, sizeof(port_mirror)); - ADPT_DEV_ID_CHECK(dev_id); - ADPT_NULL_POINT_CHECK(enable); - - /* mirror port just support physical port, not support trunk and virtual port */ - if (FAL_PORT_ID_TYPE(port_id) != 0) - return SW_BAD_PARAM; - - rv = hppe_port_mirror_get(dev_id, port_id, &port_mirror); - - if( rv != SW_OK ) - return rv; - - *enable = port_mirror.bf.in_mirr_en; - - return SW_OK; -} - -sw_error_t -adpt_hppe_mirr_port_eg_get(a_uint32_t dev_id, fal_port_t port_id, - a_bool_t * enable) -{ - sw_error_t rv = SW_OK; - union port_mirror_u port_mirror; - - memset(&port_mirror, 0, sizeof(port_mirror)); - ADPT_DEV_ID_CHECK(dev_id); - ADPT_NULL_POINT_CHECK(enable); - - /* mirror port just support physical port, not support trunk and virtual port */ - if (FAL_PORT_ID_TYPE(port_id) != 0) - return SW_BAD_PARAM; - - rv = hppe_port_mirror_get(dev_id, port_id, &port_mirror); - - if( rv != SW_OK ) - return rv; - - *enable = port_mirror.bf.eg_mirr_en; - - return SW_OK; -} - -sw_error_t -adpt_hppe_mirr_analysis_port_get(a_uint32_t dev_id, fal_port_t * port_id) -{ - sw_error_t rv = SW_OK; - union mirror_analyzer_u mirror_analyzer; - - memset(&mirror_analyzer, 0, sizeof(mirror_analyzer)); - ADPT_DEV_ID_CHECK(dev_id); - ADPT_NULL_POINT_CHECK(port_id); - - /* analysis port just support physical port and trunk port, not support virtual port */ - if (FAL_PORT_ID_TYPE(*port_id) != 0 && FAL_PORT_ID_TYPE(*port_id) != 1) - return SW_BAD_PARAM; - - rv = hppe_mirror_analyzer_get(dev_id, &mirror_analyzer); - - if( rv != SW_OK ) - return rv; - - if (mirror_analyzer.bf.in_analyzer_port != mirror_analyzer.bf.eg_analyzer_port) - return SW_FAIL; - - *port_id = mirror_analyzer.bf.eg_analyzer_port; - - if (*port_id == 32 || *port_id == 33) - *port_id = FAL_PORT_ID(FAL_PORT_TYPE_TRUNK, *port_id); - - return SW_OK; -} - -sw_error_t -adpt_hppe_mirr_port_in_set(a_uint32_t dev_id, fal_port_t port_id, - a_bool_t enable) -{ - union port_mirror_u port_mirror; - - memset(&port_mirror, 0, sizeof(port_mirror)); - ADPT_DEV_ID_CHECK(dev_id); - - /* mirror port just support physical port, not support trunk and virtual port */ - if (FAL_PORT_ID_TYPE(port_id) != 0) - return SW_BAD_PARAM; - - hppe_port_mirror_get(dev_id, port_id, &port_mirror); - port_mirror.bf.in_mirr_en = enable; - - hppe_port_mirror_set(dev_id, port_id, &port_mirror); - - return SW_OK; -} -sw_error_t -adpt_hppe_mirr_port_eg_set(a_uint32_t dev_id, fal_port_t port_id, - a_bool_t enable) -{ - union port_mirror_u port_mirror; - - memset(&port_mirror, 0, sizeof(port_mirror)); - ADPT_DEV_ID_CHECK(dev_id); - - /* mirror port just support physical port, not support trunk and virtual port */ - if (FAL_PORT_ID_TYPE(port_id) != 0) - return SW_BAD_PARAM; - - hppe_port_mirror_get(dev_id, port_id, &port_mirror); - port_mirror.bf.eg_mirr_en = enable; - - hppe_port_mirror_set(dev_id, port_id, &port_mirror); - - return SW_OK; -} -sw_error_t -adpt_hppe_mirr_analysis_port_set(a_uint32_t dev_id, fal_port_t port_id) -{ - union mirror_analyzer_u mirror_analyzer; - - memset(&mirror_analyzer, 0, sizeof(mirror_analyzer)); - ADPT_DEV_ID_CHECK(dev_id); - - /* analysis port just support physical port and trunk port, not support port */ - if (FAL_PORT_ID_TYPE(port_id) != 0 && FAL_PORT_ID_TYPE(port_id) != 1) - return SW_BAD_PARAM; - - port_id = FAL_PORT_ID_VALUE(port_id); - - hppe_mirror_analyzer_get(dev_id, &mirror_analyzer); - - mirror_analyzer.bf.in_analyzer_port = port_id; - mirror_analyzer.bf.eg_analyzer_port = port_id; - - hppe_mirror_analyzer_set(dev_id, &mirror_analyzer); - - return SW_OK; -} - -sw_error_t -adpt_hppe_mirr_analysis_config_set(a_uint32_t dev_id, fal_mirr_direction_t direction, fal_mirr_analysis_config_t * config) -{ - union mirror_analyzer_u mirror_analyzer; - union in_mirror_priority_ctrl_u in_mirror_priority_ctrl; - union eg_mirror_priority_ctrl_u eg_mirror_priority_ctrl; - - memset(&mirror_analyzer, 0, sizeof(mirror_analyzer)); - memset(&in_mirror_priority_ctrl, 0, sizeof(in_mirror_priority_ctrl)); - memset(&eg_mirror_priority_ctrl, 0, sizeof(eg_mirror_priority_ctrl)); - - ADPT_DEV_ID_CHECK(dev_id); - - /* analysis port just support physical port and trunk port, not support port */ - if (FAL_PORT_ID_TYPE(config->port_id) != 0 && FAL_PORT_ID_TYPE(config->port_id) != 1) - return SW_BAD_PARAM; - - config->port_id = FAL_PORT_ID_VALUE(config->port_id); - - hppe_mirror_analyzer_get(dev_id, &mirror_analyzer); - - if (direction == FAL_MIRR_BOTH) - { - mirror_analyzer.bf.in_analyzer_port = config->port_id; - mirror_analyzer.bf.eg_analyzer_port = config->port_id; - in_mirror_priority_ctrl.bf.priority = config->priority; - eg_mirror_priority_ctrl.bf.priority = config->priority; - hppe_mirror_analyzer_set(dev_id, &mirror_analyzer); - hppe_in_mirror_priority_ctrl_set(dev_id, &in_mirror_priority_ctrl); - hppe_eg_mirror_priority_ctrl_set(dev_id, &eg_mirror_priority_ctrl); - } - else if (direction == FAL_MIRR_INGRESS) - { - mirror_analyzer.bf.in_analyzer_port = config->port_id; - in_mirror_priority_ctrl.bf.priority = config->priority; - hppe_mirror_analyzer_set(dev_id, &mirror_analyzer); - hppe_in_mirror_priority_ctrl_set(dev_id, &in_mirror_priority_ctrl); - } - else if (direction == FAL_MIRR_EGRESS) - { - mirror_analyzer.bf.eg_analyzer_port = config->port_id; - eg_mirror_priority_ctrl.bf.priority = config->priority; - hppe_mirror_analyzer_set(dev_id, &mirror_analyzer); - hppe_eg_mirror_priority_ctrl_set(dev_id, &eg_mirror_priority_ctrl); - } - else - return SW_NOT_SUPPORTED; - - return SW_OK; -} - -sw_error_t -adpt_hppe_mirr_analysis_config_get(a_uint32_t dev_id, fal_mirr_direction_t direction, fal_mirr_analysis_config_t * config) -{ - union mirror_analyzer_u mirror_analyzer; - union in_mirror_priority_ctrl_u in_mirror_priority_ctrl; - union eg_mirror_priority_ctrl_u eg_mirror_priority_ctrl; - - memset(&mirror_analyzer, 0, sizeof(mirror_analyzer)); - memset(&in_mirror_priority_ctrl, 0, sizeof(in_mirror_priority_ctrl)); - memset(&eg_mirror_priority_ctrl, 0, sizeof(eg_mirror_priority_ctrl)); - - ADPT_DEV_ID_CHECK(dev_id); - ADPT_NULL_POINT_CHECK(config); - /* analysis port just support physical port and trunk port, not support virtual port */ - if (FAL_PORT_ID_TYPE(config->port_id) != 0 && FAL_PORT_ID_TYPE(config->port_id) != 1) - return SW_BAD_PARAM; - - hppe_mirror_analyzer_get(dev_id, &mirror_analyzer); - hppe_in_mirror_priority_ctrl_get(dev_id, &in_mirror_priority_ctrl); - hppe_eg_mirror_priority_ctrl_get(dev_id, &eg_mirror_priority_ctrl); - - if (direction == FAL_MIRR_BOTH) - { - if ((mirror_analyzer.bf.in_analyzer_port != mirror_analyzer.bf.eg_analyzer_port) || - (in_mirror_priority_ctrl.bf.priority != eg_mirror_priority_ctrl.bf.priority)) - return SW_FAIL; - - config->port_id = mirror_analyzer.bf.in_analyzer_port; - config->priority = in_mirror_priority_ctrl.bf.priority; - } - else if (direction == FAL_MIRR_INGRESS) - { - config->port_id = mirror_analyzer.bf.in_analyzer_port; - config->priority = in_mirror_priority_ctrl.bf.priority; - } - else if (direction == FAL_MIRR_EGRESS) - { - config->port_id = mirror_analyzer.bf.eg_analyzer_port; - config->priority = eg_mirror_priority_ctrl.bf.priority; - } - else - return SW_NOT_SUPPORTED; - - if (config->port_id == 32 || config->port_id == 33) - config->port_id = FAL_PORT_ID(FAL_PORT_TYPE_TRUNK, config->port_id); - - return SW_OK; -} - -void adpt_hppe_mirror_func_bitmap_init(a_uint32_t dev_id) -{ - adpt_api_t *p_adpt_api = NULL; - - p_adpt_api = adpt_api_ptr_get(dev_id); - - if(p_adpt_api == NULL) - return; - - p_adpt_api->adpt_mirror_func_bitmap = ((1 << FUNC_MIRR_ANALYSIS_PORT_SET) | - (1 << FUNC_MIRR_ANALYSIS_PORT_GET) | - (1 << FUNC_MIRR_PORT_IN_SET) | - (1 << FUNC_MIRR_PORT_IN_GET) | - (1 << FUNC_MIRR_PORT_EG_SET) | - (1 << FUNC_MIRR_PORT_EG_GET) | - (1 << FUNC_MIRR_ANALYSIS_CONFIG_SET) | - (1 << FUNC_MIRR_ANALYSIS_CONFIG_GET)); - - return; -} - -static void adpt_hppe_mirror_func_unregister(a_uint32_t dev_id, adpt_api_t *p_adpt_api) -{ - if(p_adpt_api == NULL) - return; - - p_adpt_api->adpt_mirr_port_in_set = NULL; - p_adpt_api->adpt_mirr_port_in_get = NULL; - p_adpt_api->adpt_mirr_port_eg_set = NULL; - p_adpt_api->adpt_mirr_port_eg_get = NULL; - p_adpt_api->adpt_mirr_analysis_port_set = NULL; - p_adpt_api->adpt_mirr_analysis_port_get = NULL; - p_adpt_api->adpt_mirr_analysis_config_set = NULL; - p_adpt_api->adpt_mirr_analysis_config_get = NULL; - - return; -} - - - - -sw_error_t adpt_hppe_mirror_init(a_uint32_t dev_id) -{ - adpt_api_t *p_adpt_api = NULL; - - p_adpt_api = adpt_api_ptr_get(dev_id); - - if(p_adpt_api == NULL) - return SW_FAIL; - - adpt_hppe_mirror_func_unregister(dev_id, p_adpt_api); - - if (p_adpt_api->adpt_mirror_func_bitmap & (1 << FUNC_MIRR_PORT_IN_SET)) - p_adpt_api->adpt_mirr_port_in_set = adpt_hppe_mirr_port_in_set; - if (p_adpt_api->adpt_mirror_func_bitmap & (1 << FUNC_MIRR_PORT_IN_GET)) - p_adpt_api->adpt_mirr_port_in_get = adpt_hppe_mirr_port_in_get; - if (p_adpt_api->adpt_mirror_func_bitmap & (1 << FUNC_MIRR_PORT_EG_SET)) - p_adpt_api->adpt_mirr_port_eg_set = adpt_hppe_mirr_port_eg_set; - if (p_adpt_api->adpt_mirror_func_bitmap & (1 << FUNC_MIRR_PORT_EG_GET)) - p_adpt_api->adpt_mirr_port_eg_get = adpt_hppe_mirr_port_eg_get; - if (p_adpt_api->adpt_mirror_func_bitmap & (1 << FUNC_MIRR_ANALYSIS_PORT_SET)) - p_adpt_api->adpt_mirr_analysis_port_set = adpt_hppe_mirr_analysis_port_set; - if (p_adpt_api->adpt_mirror_func_bitmap & (1 << FUNC_MIRR_ANALYSIS_PORT_GET)) - p_adpt_api->adpt_mirr_analysis_port_get = adpt_hppe_mirr_analysis_port_get; - if (p_adpt_api->adpt_mirror_func_bitmap & (1 << FUNC_MIRR_ANALYSIS_CONFIG_SET)) - p_adpt_api->adpt_mirr_analysis_config_set = adpt_hppe_mirr_analysis_config_set; - if (p_adpt_api->adpt_mirror_func_bitmap & (1 << FUNC_MIRR_ANALYSIS_CONFIG_GET)) - p_adpt_api->adpt_mirr_analysis_config_get = adpt_hppe_mirr_analysis_config_get; - - return SW_OK; -} - -/** - * @} - */ diff --git a/feeds/ipq807x/qca-ssdk/src/src/adpt/hppe/adpt_hppe_misc.c b/feeds/ipq807x/qca-ssdk/src/src/adpt/hppe/adpt_hppe_misc.c deleted file mode 100755 index e3dbd31e1..000000000 --- a/feeds/ipq807x/qca-ssdk/src/src/adpt/hppe/adpt_hppe_misc.c +++ /dev/null @@ -1,1011 +0,0 @@ -/* - * Copyright (c) 2017, 2019, The Linux Foundation. All rights reserved. - * Permission to use, copy, modify, and/or distribute this software for - * any purpose with or without fee is hereby granted, provided that the - * above copyright notice and this permission notice appear in all copies. - * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES - * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR - * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES - * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN - * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT - * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. - */ - - -/** - * @defgroup - * @{ - */ -#include "sw.h" -#include "hppe_portctrl_reg.h" -#include "hppe_portctrl.h" -#include "hppe_portvlan_reg.h" -#include "hppe_portvlan.h" -#include "hppe_vsi_reg.h" -#include "hppe_vsi.h" -#include "hppe_policer_reg.h" -#include "hppe_policer.h" -#include "hppe_qm_reg.h" -#include "hppe_qm.h" -#include "adpt_hppe.h" -#include "adpt.h" -#if defined(CPPE) -#include "adpt_cppe_misc.h" -#endif - - -#ifndef IN_MISC_MINI -char cpucode[][85] = { -"Forwarding to CPU", -"Unkown L2 protocol exception redirect/copy to CPU", -"PPPoE wrong version or wrong type exception redirect/copy to CPU", -"PPPoE wrong code exception redirect/copy to CPU", -"PPPoE unsupported PPP protocol exception redirect/copy to CPU", -"IPv4 wrong version exception redirect/copy to CPU", -"IPv4 small IHL exception redirect/copy to CPU", -"IPv4 with option exception redirect/copy to CPU", -"IPv4 header incomplete exception redirect/copy to CPU", -"IPv4 bad total length exception redirect/copy to CPU", -"IPv4 data incomplete exception redirect/copy to CPU", -"IPv4 fragment exception redirect/copy to CPU", -"IPv4 ping of death exception redirect/copy to CPU", -"IPv4 small TTL exception redirect/copy to CPU", -"IPv4 unknown IP protocol exception redirect/copy to CPU", -"IPv4 checksum error exception redirect/copy to CPU", -"IPv4 invalid SIP exception redirect/copy to CPU", -"IPv4 invalid DIP exception redirect/copy to CPU", -"IPv4 LAND attack exception redirect/copy to CPU", -"IPv4 AH header incomplete exception redirect/copy to CPU", -"IPv4 AH header cross 128-byte exception redirect/copy to CPU", -"IPv4 ESP header incomplete exception redirect/copy to CPU", -"IPv6 wrong version exception redirect/copy to CPU", -"IPv6 header incomplete exception redirect/copy to CPU", -"IPv6 bad total length exception redirect/copy to CPU", -"IPv6 data incomplete exception redirect/copy to CPU", -"IPv6 with extension header exception redirect/copy to CPU", -"IPv6 small hop limit exception redirect/copy to CPU", -"IPv6 invalid SIP exception redirect/copy to CPU", -"IPv6 invalid DIP exception redirect/copy to CPU", -"IPv6 LAND attack exception redirect/copy to CPU", -"IPv6 fragment exception redirect/copy to CPU", -"IPv6 ping of death exception redirect/copy to CPU", -"IPv6 with more than 2 extension headers exception redirect/copy to CPU", -"IPv6 unknown last next header exception redirect/copy to CPU", -"IPv6 mobility header incomplete exception redirect/copy to CPU", -"IPv6 mobility header cross 128-byte exception redirect/copy to CPU", -"IPv6 AH header incomplete exception redirect/copy to CPU", -"IPv6 AH header cross 128-byte exception redirect/copy to CPU", -"IPv6 ESP header incomplete exception redirect/copy to CPU", -"IPv6 ESP header cross 128-byte exception redirect/copy to CPU", -"IPv6 other extension header incomplete exception redirect/copy to CPU", -"IPv6 other extension header cross 128-byte exception redirect/copy to CPU", -"TCP header incomplete exception redirect/copy to CPU", -"TCP header cross 128-byte exception redirect/copy to CPU", -"TCP same SP and DP exception redirect/copy to CPU", -"TCP small data offset redirect/copy to CPU", -"TCP flags VALUE/MASK group 0 exception redirect/copy to CPU", -"TCP flags VALUE/MASK group 1 exception redirect/copy to CPU", -"TCP flags VALUE/MASK group 2 exception redirect/copy to CPU", -"TCP flags VALUE/MASK group 3 exception redirect/copy to CPU", -"TCP flags VALUE/MASK group 4 exception redirect/copy to CPU", -"TCP flags VALUE/MASK group 5 exception redirect/copy to CPU", -"TCP flags VALUE/MASK group 6 exception redirect/copy to CPU", -"TCP flags VALUE/MASK group 7 exception redirect/copy to CPU", -"TCP checksum error exception redirect/copy to CPU", -"UDP header incomplete exception redirect/copy to CPU", -"UDP header cross 128-byte exception redirect/copy to CPU", -"UDP same SP and DP exception redirect/copy to CPU", -"UDP bad length exception redirect/copy to CPU", -"UDP data incomplete exception redirect/copy to CPU", -"UDP checksum error exception redirect/copy to CPU", -"UDP-Lite header incomplete exception redirect/copy to CPU", -"UDP-Lite header cross 128-byte exception redirect/copy to CPU", -"UDP-Lite same SP and DP exception redirect/copy to CPU", -"UDP-Lite checksum coverage value 0-7 exception redirect/copy to CPU", -"UDP-Lite checksum coverage value too big exception redirect/copy to CPU", -"UDP-Lite checksum coverage value cross 128-byte exception redirect/copy to CPU", -"UDP-Lite checksum error exception redirect/copy to CPU", -"Fake L2 protocol packet redirect/copy to CPU", -"Fake MAC header packet redirect/copy to CPU", -"L2 MRU checking fail redirect/copy to CPU", -"L2 MTU checking fail redirect/copy to CPU", -"IP prefix broadcast redirect/copy to CPU", -"L3 MTU checking fail redirect/copy to CPU", -"L3 MRU checking fail redirect/copy to CPU", -"ICMP redirect/copy to CPU", -"IP to me routing TTL 1 redirect/copy to CPU", -"IP to me routing TTL 0 redirect/copy to CPU", -"Flow service code loop redirect/copy to CPU", -"Flow de-accelearate redirect/copy to CPU", -"Flow source interface check fail redirect/copy to CPU", -"Flow sync toggle mismatch redirect/copy to CPU", -"MTU check fail if DF set redirect/copy to CPU", -"PPPoE multicast redirect/copy to CPU", -"EAPoL packet redirect/copy to CPU", -"PPPoE discovery packet redirect/copy to CPU", -"IGMP packet redirect/copy to CPU", -"ARP request packet redirect/copy to CPU", -"ARP reply packet redirect/copy to CPU", -"DHCPv4 packet redirect/copy to CPU", -"MLD packet redirect/copy to CPU", -"NS packet redirect/copy to CPU", -"NA packet redirect/copy to CPU", -"DHCPv6 packet redirect/copy to CPU", -"PTP sync packet redirect/copy to CPU", -"PTP follow up packet redirect/copy to CPU", -"PTP delay request packet redirect/copy to CPU", -"PTP delay response packet redirect/copy to CPU", -"PTP pdelay request packet redirect/copy to CPU", -"PTP pdelay response packet redirect/copy to CPU", -"PTP pdelay response follow up packet redirect/copy to CPU", -"PTP announce packet redirect/copy to CPU", -"PTP management packet redirect/copy to CPU", -"PTP signaling packet redirect/copy to CPU", -"PTP message reserved type 0 packet redirect/copy to CPU", -"PTP message reserved type 1 packet redirect/copy to CPU", -"PTP message reserved type 2 packet redirect/copy to CPU", -"PTP message reserved type 3 packet redirect/copy to CPU", -"PTP message reserved type packet redirect/copy to CPU", -"IPv4 source guard unknown packet redirect/copy to CPU", -"IPv6 source guard unknown packet redirect/copy to CPU", -"ARP source guard unknown packet redirect/copy to CPU", -"ND source guard unknown packet redirect/copy to CPU", -"IPv4 source guard violation packet redirect/copy to CPU", -"IPv6 source guard violation packet redirect/copy to CPU", -"ARP source guard violation packet redirect/copy to CPU", -"ND source guard violation packet redirect/copy to CPU", -"L3 route host mismatch action redirect/copy to CPU", -"L3 flow SNAT action redirect/copy to CPU", -"L3 flow DNAT action redirect/copy to CPU", -"L3 flow routing action redirect/copy to CPU", -"L3 flow bridging action redirect/copy to CPU", -"L3 multicast bridging action redirect/copy to CPU", -"L3 route Preheader routing action redirect/copy to CPU", -"L3 route Preheader SNAPT action redirect/copy to CPU", -"L3 route Preheader DNAPT action redirect/copy to CPU", -"L3 route Preheader SNAT action redirect/copy to CPU", -"L3 route Preheader DNAT action redirect/copy to CPU", -"L3 no route preheader NAT action redirect/copy to CPU", -"L3 no route preheader NAT error redirect/copy to CPU", -"L3 route action redirect/copy to CPU", -"L3 no route action redirect/copy to CPU", -"L3 no route next hop invalid action redirect/copy to CPU", -"L3 no route preheader action redirect/copy to CPU", -"L3 bridge action redirect/copy to CPU", -"L3 flow action redirect/copy to CPU", -"L3 flow miss action redirect/copy to CPU", -"L2 new MAC address redirect/copy to CPU", -"L2 hash violation redirect/copy to CPU", -"L2 station move redirect/copy to CPU", -"L2 learn limit redirect/copy to CPU", -"L2 SA lookup action redirect/copy to CPU", -"L2 DA lookup action redirect/copy to CPU", -"APP_CTRL action redirect/copy to CPU", -"Pre-IPO action", -"Post-IPO action", -"Service code action", -"Egress mirror to CPU", -"Ingress mirror to CPU", -}; - -char dropcode[][75] = { -"None", -"Unkown L2 protocol exception drop", -"PPPoE wrong version or wrong type exception drop", -"PPPoE wrong code exception drop", -"PPPoE unsupported PPP protocol exception drop", -"IPv4 wrong version exception drop", -"IPv4 small IHL exception drop", -"IPv4 with option exception drop", -"IPv4 header incomplete exception drop", -"IPv4 bad total length exception drop", -"IPv4 data incomplete exception drop", -"IPv4 fragment exception drop", -"IPv4 ping of death exception drop", -"IPv4 small TTL exception drop", -"IPv4 unknown IP protocol exception drop", -"IPv4 checksum error exception drop", -"IPv4 invalid SIP exception drop", -"IPv4 invalid DIP exception drop", -"IPv4 LAND attack exception drop", -"IPv4 AH header incomplete exception drop", -"IPv4 AH header cross 128-byte exception drop", -"IPv4 ESP header incomplete exception drop", -"IPv6 wrong version exception drop", -"IPv6 header incomplete exception drop", -"IPv6 bad total length exception drop", -"IPv6 data incomplete exception drop", -"IPv6 with extension header exception drop", -"IPv6 small hop limit exception drop", -"IPv6 invalid SIP exception drop", -"IPv6 invalid DIP exception drop", -"IPv6 LAND attack exception drop", -"IPv6 fragment exception drop", -"IPv6 ping of death exception drop", -"IPv6 with more than 2 extension headers exception drop", -"IPv6 unknown last next header exception drop", -"IPv6 mobility header incomplete exception drop", -"IPv6 mobility header cross 128-byte exception drop", -"IPv6 AH header incomplete exception drop", -"IPv6 AH header cross 128-byte exception drop", -"IPv6 ESP header incomplete exception drop", -"IPv6 ESP header cross 128-byte exception drop", -"IPv6 other extension header incomplete exception drop", -"IPv6 other extension header cross 128-byte exception drop", -"TCP header incomplete exception drop", -"TCP header cross 128-byte exception drop", -"TCP same SP and DP exception drop", -"TCP small data offset drop", -"TCP flags VALUE/MASK group 0 exception drop", -"TCP flags VALUE/MASK group 1 exception drop", -"TCP flags VALUE/MASK group 2 exception drop", -"TCP flags VALUE/MASK group 3 exception drop", -"TCP flags VALUE/MASK group 4 exception drop", -"TCP flags VALUE/MASK group 5 exception drop", -"TCP flags VALUE/MASK group 6 exception drop", -"TCP flags VALUE/MASK group 7 exception drop", -"TCP checksum error exception drop", -"UDP header incomplete exception drop", -"UDP header cross 128-byte exception drop", -"UDP same SP and DP exception drop", -"UDP bad length exception drop", -"UDP data incomplete exception drop", -"UDP checksum error exception drop", -"UDP-Lite header incomplete exception drop", -"UDP-Lite header cross 128-byte exception drop", -"UDP-Lite same SP and DP exception drop", -"UDP-Lite checksum coverage value 0-7 exception drop", -"UDP-Lite checksum coverage value too big exception drop", -"UDP-Lite checksum coverage value cross 128-byte exception drop", -"UDP-Lite checksum error exception drop", -"L3 multicast bridging action", -"L3 no route with Preheader NAT action", -"L3 no route with Preheader NAT action error configuration", -"L3 route action drop", -"L3 no route action drop", -"L3 no route next hop invalid action drop", -"L3 no route preheader action drop", -"L3 bridge action drop", -"L3 flow action drop", -"L3 flow miss action drop", -"L2 MRU checking fail drop", -"L2 MTU checking fail drop", -"L3 IP prefix broadcast drop", -"L3 MTU checking fail drop", -"L3 MRU checking fail drop", -"L3 ICMP redirect drop", -"Fake MAC header indicated packet not routing or bypass L3 edit drop", -"L3 IP route TTL zero drop", -"L3 flow service code loop drop", -"L3 flow de-accelerate drop", -"L3 flow source interface check fail drop", -"Flow toggle mismatch exception drop", -"MTU check exception if DF set drop", -"PPPoE multicast packet with IP routing enabled drop", -"IPv4 SG unkown drop", -"IPv6 SG unkown drop", -"ARP SG unkown drop", -"ND SG unkown drop", -"IPv4 SG violation drop", -"IPv6 SG violation drop", -"ARP SG violation drop", -"ND SG violation drop", -"L2 new MAC address drop", -"L2 hash violation drop", -"L2 station move drop", -"L2 learn limit drop", -"L2 SA lookup action drop", -"L2 DA lookup action drop", -"APP_CTRL action drop", -"Ingress VLAN filtering action drop", -"Ingress VLAN translation miss drop", -"Egress VLAN filtering drop", -"Pre-IPO entry hit action drop", -"Post-IPO entry hit action drop", -"Multicast SA or broadcast SA drop", -"No destination drop", -"STG ingress filtering drop", -"STG egress filtering drop", -"Source port filter drop", -"Trunk select fail drop", -"TX MAC disable drop", -"Ingress VLAN tag format drop", -"CRC error drop", -"PAUSE frame drop", -"Promisc drop", -"Isolation drop", -"Magagement packet APP_CTRL drop", -"Fake L2 protocol indicated packet not routing or bypass L3 edit drop", -"Policing drop" -}; - -sw_error_t -adpt_hppe_debug_port_counter_enable(a_uint32_t dev_id, fal_port_t port_id, - fal_counter_en_t *cnt_en) -{ - union mru_mtu_ctrl_tbl_u mru_mtu_ctrl_tbl; - union mc_mtu_ctrl_tbl_u mc_mtu_ctrl_tbl; - union port_eg_vlan_u port_eg_vlan; - - ADPT_DEV_ID_CHECK(dev_id); - ADPT_NULL_POINT_CHECK(cnt_en); - - port_id = FAL_PORT_ID_VALUE(port_id); - - if (port_id < SSDK_MAX_PORT_NUM) { - SW_RTN_ON_ERROR(hppe_mru_mtu_ctrl_tbl_get(dev_id, port_id, &mru_mtu_ctrl_tbl)); - SW_RTN_ON_ERROR(hppe_mc_mtu_ctrl_tbl_get(dev_id, port_id, &mc_mtu_ctrl_tbl)); - SW_RTN_ON_ERROR(hppe_port_eg_vlan_get(dev_id, port_id, &port_eg_vlan)); - mru_mtu_ctrl_tbl.bf.rx_cnt_en = cnt_en->rx_counter_en; - mru_mtu_ctrl_tbl.bf.tx_cnt_en = cnt_en->vp_uni_tx_counter_en; - mc_mtu_ctrl_tbl.bf.tx_cnt_en = cnt_en->port_mc_tx_counter_en; - port_eg_vlan.bf.tx_counting_en = cnt_en->port_tx_counter_en; - SW_RTN_ON_ERROR(hppe_mru_mtu_ctrl_tbl_set(dev_id, port_id, &mru_mtu_ctrl_tbl)); - SW_RTN_ON_ERROR(hppe_mc_mtu_ctrl_tbl_set(dev_id, port_id, &mc_mtu_ctrl_tbl)); - SW_RTN_ON_ERROR(hppe_port_eg_vlan_set(dev_id, port_id, &port_eg_vlan)); - } - else if (port_id >= SSDK_MAX_PORT_NUM && - port_id < SSDK_MAX_VIRTUAL_PORT_NUM) { - SW_RTN_ON_ERROR(hppe_mru_mtu_ctrl_tbl_get(dev_id, port_id, &mru_mtu_ctrl_tbl)); - mru_mtu_ctrl_tbl.bf.rx_cnt_en = cnt_en->rx_counter_en; - mru_mtu_ctrl_tbl.bf.tx_cnt_en = cnt_en->vp_uni_tx_counter_en; - SW_RTN_ON_ERROR(hppe_mru_mtu_ctrl_tbl_set(dev_id, port_id, &mru_mtu_ctrl_tbl)); - } else { - return SW_OUT_OF_RANGE; - } - - return SW_OK; -} - -sw_error_t -adpt_ppe_debug_port_counter_enable(a_uint32_t dev_id, fal_port_t port_id, - fal_counter_en_t *cnt_en) -{ - a_uint32_t chip_ver = 0; - - chip_ver = adpt_hppe_chip_revision_get(dev_id); -#if defined(CPPE) - if (chip_ver == CPPE_REVISION) { - return adpt_cppe_debug_port_counter_enable(dev_id, port_id, cnt_en); - } else -#endif - { - return adpt_hppe_debug_port_counter_enable(dev_id, port_id, cnt_en); - } -} - -sw_error_t -adpt_hppe_debug_port_counter_status_get(a_uint32_t dev_id, fal_port_t port_id, - fal_counter_en_t *cnt_en) -{ - union mru_mtu_ctrl_tbl_u mru_mtu_ctrl_tbl; - union mc_mtu_ctrl_tbl_u mc_mtu_ctrl_tbl; - union port_eg_vlan_u port_eg_vlan; - - ADPT_DEV_ID_CHECK(dev_id); - ADPT_NULL_POINT_CHECK(cnt_en); - - port_id = FAL_PORT_ID_VALUE(port_id); - - if (port_id < SSDK_MAX_PORT_NUM) { - SW_RTN_ON_ERROR(hppe_mru_mtu_ctrl_tbl_get(dev_id, port_id, &mru_mtu_ctrl_tbl)); - SW_RTN_ON_ERROR(hppe_mc_mtu_ctrl_tbl_get(dev_id, port_id, &mc_mtu_ctrl_tbl)); - SW_RTN_ON_ERROR(hppe_port_eg_vlan_get(dev_id, port_id, &port_eg_vlan)); - cnt_en->rx_counter_en = mru_mtu_ctrl_tbl.bf.rx_cnt_en; - cnt_en->vp_uni_tx_counter_en = mru_mtu_ctrl_tbl.bf.tx_cnt_en; - cnt_en->port_mc_tx_counter_en = mc_mtu_ctrl_tbl.bf.tx_cnt_en; - cnt_en->port_tx_counter_en = port_eg_vlan.bf.tx_counting_en; - } else if (port_id >= SSDK_MAX_PORT_NUM && - port_id < SSDK_MAX_VIRTUAL_PORT_NUM) { - SW_RTN_ON_ERROR(hppe_mru_mtu_ctrl_tbl_get(dev_id, port_id, &mru_mtu_ctrl_tbl)); - cnt_en->rx_counter_en = mru_mtu_ctrl_tbl.bf.rx_cnt_en; - cnt_en->vp_uni_tx_counter_en = mru_mtu_ctrl_tbl.bf.tx_cnt_en; - } else { - return SW_OUT_OF_RANGE; - } - - return SW_OK; -} - -sw_error_t -adpt_ppe_debug_port_counter_status_get(a_uint32_t dev_id, fal_port_t port_id, - fal_counter_en_t *cnt_en) -{ - a_uint32_t chip_ver = 0; - - chip_ver = adpt_hppe_chip_revision_get(dev_id); -#if defined(CPPE) - if (chip_ver == CPPE_REVISION) { - return adpt_cppe_debug_port_counter_status_get(dev_id, port_id, cnt_en); - } else -#endif - { - return adpt_hppe_debug_port_counter_status_get(dev_id, port_id, cnt_en); - } -} - -sw_error_t -adpt_hppe_debug_counter_set(void) -{ - union vlan_cnt_tbl_u vlan_cnt_tbl = {0}; - union pre_l2_cnt_tbl_u pre_l2_cnt_tbl = {0}; - union port_tx_drop_cnt_tbl_u port_tx_drop_cnt_tbl = {0}; - union eg_vsi_counter_tbl_u eg_vsi_counter_tbl = {0}; - union port_tx_counter_tbl_reg_u port_tx_counter_tbl = {0}; - union vp_tx_counter_tbl_reg_u vp_tx_counter_tbl = {0}; - union queue_tx_counter_tbl_u queue_tx_counter_tbl = {0}; - union epe_dbg_in_cnt_reg_u epe_dbg_in_cnt = {0}; - union epe_dbg_out_cnt_reg_u epe_dbg_out_cnt = {0}; - union vp_tx_drop_cnt_tbl_u vp_tx_drop_cnt_tbl = {0}; - union drop_cpu_cnt_tbl_u drop_cpu_cnt_tbl = {0}; - - a_uint32_t i; - - /* clear PRX DROP_CNT */ - for (i = 0; i < DROP_CNT_MAX_ENTRY; i++) - hppe_drop_cnt_drop_cnt_set(0, i, 0); - - /* clear PRX DROP_PKT_STAT */ - for (i = 0; i < DROP_PKT_STAT_MAX_ENTRY; i++) { - hppe_drop_stat_pkts_set(0, i, 0); - hppe_drop_stat_bytes_set(0, i, 0); - } - - /* clear IPR_PKT_NUM */ - for (i = 0; i < IPR_PKT_NUM_TBL_REG_MAX_ENTRY; i++) { - hppe_ipr_pkt_num_tbl_reg_packets_set(0, i, 0); - hppe_ipr_byte_low_reg_reg_bytes_set(0, i, 0); - hppe_ipr_byte_high_reg_bytes_set(0, i, 0); - } - - /* clear VLAN_CNT_TBL */ - for (i = 0; i < VLAN_CNT_TBL_MAX_ENTRY; i++) - hppe_vlan_cnt_tbl_set(0, i, &vlan_cnt_tbl); - - /* clear PRE_L2_CNT_TBL */ - for (i = 0; i < PRE_L2_CNT_TBL_MAX_ENTRY; i++) - hppe_pre_l2_cnt_tbl_set(0, i, &pre_l2_cnt_tbl); - - /* clear PORT_TX_DROP_CNT_TBL */ - for (i = 0; i < PORT_TX_DROP_CNT_TBL_MAX_ENTRY; i++) - hppe_port_tx_drop_cnt_tbl_set(0, i, &port_tx_drop_cnt_tbl); - - /* clear EG_VSI_COUNTER_TBL */ - for (i = 0; i < EG_VSI_COUNTER_TBL_MAX_ENTRY; i++) - hppe_eg_vsi_counter_tbl_set(0, i, &eg_vsi_counter_tbl); - - /* clear PORT_TX_COUNTER_TBL */ - for (i = 0; i < PORT_TX_COUNTER_TBL_REG_MAX_ENTRY; i++) - hppe_port_tx_counter_tbl_reg_set(0, i, &port_tx_counter_tbl); - - /* clear VP_TX_COUNTER_TBL */ - for (i = 0; i < VP_TX_COUNTER_TBL_REG_MAX_ENTRY; i++) - hppe_vp_tx_counter_tbl_reg_set(0, i, &vp_tx_counter_tbl); - - /* clear QUEUE_TX_COUNTER_TBL */ - for (i = 0; i < QUEUE_TX_COUNTER_TBL_MAX_ENTRY; i++) - hppe_queue_tx_counter_tbl_set(0, i, &queue_tx_counter_tbl); - - /* clear EPE_DBG_IN_CNT & EPE_DBG_OUT_CNT */ - hppe_epe_dbg_in_cnt_reg_set(0, &epe_dbg_in_cnt); - hppe_epe_dbg_out_cnt_reg_set(0, &epe_dbg_out_cnt); - - /* clear VP_TX_DROP_CNT_TBL */ - for (i = 0; i < VP_TX_DROP_CNT_TBL_MAX_ENTRY; i++) - hppe_vp_tx_drop_cnt_tbl_set(0, i, &vp_tx_drop_cnt_tbl); - - /* clear DROP_CPU_CNT_TBL */ - for (i = 0; i < DROP_CPU_CNT_TBL_MAX_ENTRY; i++) - hppe_drop_cpu_cnt_tbl_set(0, i, &drop_cpu_cnt_tbl); - - return SW_OK; -} - -void -adpt_hppe_debug_prx_drop_cnt_get(void) -{ - a_uint32_t value; - int i, tags, sign; - - sign = tags = 0; - printk("%-35s", "PRX_DROP_CNT RX:"); - for (i = 0; i < DROP_CNT_MAX_ENTRY; i++) - { - hppe_drop_cnt_drop_cnt_get(0, i, &value); - if (value > 0) - { - if (sign) { - printk(KERN_CONT "\n"); - printk(KERN_CONT "%-35s", ""); - } - sign = 0; - printk(KERN_CONT "%15u(port=%04d)", value, i); - if (++tags % 3 == 0) - sign = 1; - } - } - printk(KERN_CONT "\n"); -} - -void -adpt_hppe_debug_prx_drop_pkt_stat_get(a_bool_t show_type) -{ - a_uint32_t value32; - a_uint64_t value; - int i, tags, sign; - - sign = tags = 0; - printk("%-35s", "PRX_DROP_PKT_STAT RX:"); - for (i = 0; i < DROP_PKT_STAT_MAX_ENTRY; i++) - { - if (show_type == A_FALSE) - { - hppe_drop_stat_pkts_get(0, i, &value32); - value = (a_uint64_t)value32; - } - else - hppe_drop_stat_bytes_get(0, i, &value); - if (value > 0) - { - if (sign) { - printk(KERN_CONT "\n"); - printk(KERN_CONT "%-35s", ""); - } - sign = 0; - printk(KERN_CONT "%15llu(port=%04d)", value, i); - if (++tags % 3 == 0) - sign = 1; - } - } - printk(KERN_CONT "\n"); -} - -void -adpt_hppe_debug_ipx_pkt_num_get(a_bool_t show_type) -{ - union ipr_pkt_num_tbl_reg_u ipr_pkt_num_tbl_reg; - union ipr_byte_low_reg_reg_u ipr_byte_low_reg; - union ipr_byte_high_reg_u ipr_byte_high_reg; - a_uint64_t value; - int i, tags, sign; - - sign = tags = 0; - printk("%-35s", "IPR_PKT_NUM RX:"); - for (i = 0; i < IPR_PKT_NUM_TBL_REG_MAX_ENTRY; i++) - { - hppe_ipr_pkt_num_tbl_reg_get(0, i, &ipr_pkt_num_tbl_reg); - hppe_ipr_byte_low_reg_reg_get(0, i, &ipr_byte_low_reg); - hppe_ipr_byte_high_reg_get(0, i, &ipr_byte_high_reg); - if (show_type == A_FALSE) - value = (a_uint64_t)ipr_pkt_num_tbl_reg.bf.packets; - else - value = ipr_byte_low_reg.bf.bytes | ((a_uint64_t)ipr_byte_high_reg.bf.bytes << 32); - - if (value > 0) - { - if (sign) { - printk(KERN_CONT "\n"); - printk(KERN_CONT "%-35s", ""); - } - sign = 0; - printk(KERN_CONT "%15llu(port=%04d)", value, i); - if (++tags % 3 == 0) - sign = 1; - } - } - printk(KERN_CONT "\n"); -} - -void -adpt_hppe_debug_vlan_counter_get(a_bool_t show_type) -{ - union vlan_cnt_tbl_u vlan_cnt_tbl; - a_uint64_t value; - int i, tags, sign; - - sign = tags = 0; - printk("%-35s", "VLAN_CNT_TBL RX:"); - for (i = 0; i < VLAN_CNT_TBL_MAX_ENTRY; i++) - { - hppe_vlan_cnt_tbl_get(0, i, &vlan_cnt_tbl); - if (show_type == A_FALSE) - value = (a_uint64_t)vlan_cnt_tbl.bf.rx_pkt_cnt; - else - value = vlan_cnt_tbl.bf.rx_byte_cnt_0 | ((a_uint64_t)vlan_cnt_tbl.bf.rx_byte_cnt_1 << 32); - if (value > 0) - { - if (sign) { - printk(KERN_CONT "\n"); - printk(KERN_CONT "%-35s", ""); - } - sign = 0; - printk(KERN_CONT "%15llu(vsi=%04d)", value, i); - if (++tags % 3 == 0) - sign = 1; - } - } - printk(KERN_CONT "\n"); -} - -void -adpt_hppe_debug_pre_l2_counter_get(a_bool_t show_type) -{ - union pre_l2_cnt_tbl_u pre_l2_cnt_tbl; - a_uint64_t value; - int i, tags, sign; - - sign = tags = 0; - printk("%-35s", "PRE_L2_CNT_TBL RX:"); - for (i = 0; i < PRE_L2_CNT_TBL_MAX_ENTRY; i++) - { - hppe_pre_l2_cnt_tbl_get(0, i, &pre_l2_cnt_tbl); - if (show_type == A_FALSE) - value = (a_uint64_t)pre_l2_cnt_tbl.bf.rx_pkt_cnt; - else - value = pre_l2_cnt_tbl.bf.rx_byte_cnt_0 | ((a_uint64_t)pre_l2_cnt_tbl.bf.rx_byte_cnt_1 << 32); - if (value > 0) - { - if (sign) { - printk(KERN_CONT "\n"); - printk(KERN_CONT "%-35s", ""); - } - sign = 0; - printk(KERN_CONT "%15llu(vsi=%04d)", value, i); - if (++tags % 3 == 0) - sign = 1; - } - } - printk(KERN_CONT "\n"); - - sign = tags = 0; - printk("%-35s", "PRE_L2_CNT_TBL RX_DROP:"); - for (i = 0; i < PRE_L2_CNT_TBL_MAX_ENTRY; i++) - { - hppe_pre_l2_cnt_tbl_get(0, i, &pre_l2_cnt_tbl); - if (show_type == A_FALSE) - value = pre_l2_cnt_tbl.bf.rx_drop_pkt_cnt_0 | ((a_uint64_t)pre_l2_cnt_tbl.bf.rx_drop_pkt_cnt_1 << 24); - else - value = pre_l2_cnt_tbl.bf.rx_drop_byte_cnt_0 | ((a_uint64_t)pre_l2_cnt_tbl.bf.rx_drop_byte_cnt_1 << 24); - if (value > 0) - { - if (sign) { - printk(KERN_CONT "\n"); - printk(KERN_CONT "%-35s", ""); - } - sign = 0; - printk(KERN_CONT "%15llu(vsi=%04d)", value, i); - if (++tags % 3 == 0) - sign = 1; - } - } - printk(KERN_CONT "\n"); -} - -void adpt_hppe_debug_port_tx_drop_counter_get(a_bool_t show_type) -{ - union port_tx_drop_cnt_tbl_u port_tx_drop_cnt_tbl; - a_uint64_t value; - int i, tags, sign; - - sign = tags = 0; - printk("%-35s", "PORT_TX_DROP_CNT_TBL TX_DROP:"); - for (i = 0; i < PORT_TX_DROP_CNT_TBL_MAX_ENTRY; i++) - { - hppe_port_tx_drop_cnt_tbl_get(0, i, &port_tx_drop_cnt_tbl); - if (show_type == A_FALSE) - value = (a_uint64_t)port_tx_drop_cnt_tbl.bf.tx_drop_pkt_cnt; - else - value = port_tx_drop_cnt_tbl.bf.tx_drop_byte_cnt_0 | ((a_uint64_t)port_tx_drop_cnt_tbl.bf.tx_drop_byte_cnt_1 << 32); - if (value > 0) - { - if (sign) { - printk(KERN_CONT "\n"); - printk(KERN_CONT "%-35s", ""); - } - sign = 0; - printk(KERN_CONT "%15llu(port=%04d)", value, i); - if (++tags % 3 == 0) - sign = 1; - } - } - printk(KERN_CONT "\n"); -} - -void -adpt_hppe_debug_eg_vsi_counter_get(a_bool_t show_type) -{ - union eg_vsi_counter_tbl_u eg_vsi_counter_tbl; - a_uint64_t value; - int i, tags, sign; - - sign = tags = 0; - printk("%-35s", "EG_VSI_COUNTER_TBL TX:"); - for (i = 0; i < EG_VSI_COUNTER_TBL_MAX_ENTRY; i++) - { - hppe_eg_vsi_counter_tbl_get(0, i, &eg_vsi_counter_tbl); - if (show_type == A_FALSE) - value = (a_uint64_t)eg_vsi_counter_tbl.bf.tx_packets; - else - value = eg_vsi_counter_tbl.bf.tx_bytes_0 | ((a_uint64_t)eg_vsi_counter_tbl.bf.tx_bytes_1 << 32); - if (value > 0) - { - if (sign) { - printk(KERN_CONT "\n"); - printk(KERN_CONT "%-35s", ""); - } - sign = 0; - printk(KERN_CONT "%15llu(vsi=%04d)", value, i); - if (++tags % 3 == 0) - sign = 1; - } - } - printk(KERN_CONT "\n"); -} - -void -adpt_hppe_debug_port_tx_counter_get(a_bool_t show_type) -{ - union port_tx_counter_tbl_reg_u port_tx_counter_tbl; - a_uint64_t value; - int i, tags, sign; - - sign = tags = 0; - printk("%-35s", "PORT_TX_COUNTER_TBL TX:"); - for (i = 0; i < PORT_TX_COUNTER_TBL_REG_MAX_ENTRY; i++) - { - hppe_port_tx_counter_tbl_reg_get(0, i, &port_tx_counter_tbl); - if (show_type == A_FALSE) - value = (a_uint64_t)port_tx_counter_tbl.bf.tx_packets; - else - value = port_tx_counter_tbl.bf.tx_bytes_0 | ((a_uint64_t)port_tx_counter_tbl.bf.tx_bytes_1 << 32); - if (value > 0) - { - if (sign) { - printk(KERN_CONT "\n"); - printk(KERN_CONT "%-35s", ""); - } - sign = 0; - printk(KERN_CONT "%15llu(port=%04d)", value, i); - if (++tags % 3 == 0) - sign = 1; - } - } - printk(KERN_CONT "\n"); -} - -void -adpt_hppe_debug_vp_tx_counter_get(a_bool_t show_type) -{ - union vp_tx_counter_tbl_reg_u vp_tx_counter_tbl; - a_uint64_t value; - int i, tags, sign; - - sign = tags = 0; - printk("%-35s", "VP_TX_COUNTER_TBL TX:"); - for (i = 0; i < VP_TX_COUNTER_TBL_REG_MAX_ENTRY; i++) - { - hppe_vp_tx_counter_tbl_reg_get(0, i, &vp_tx_counter_tbl); - if (show_type == A_FALSE) - value = (a_uint64_t)vp_tx_counter_tbl.bf.tx_packets; - else - value = vp_tx_counter_tbl.bf.tx_bytes_0 | ((a_uint64_t)vp_tx_counter_tbl.bf.tx_bytes_1 << 32); - if (value > 0) - { - if (sign) { - printk(KERN_CONT "\n"); - printk(KERN_CONT "%-35s", ""); - } - sign = 0; - printk(KERN_CONT "%15llu(port=%04d)", value, i); - if (++tags % 3 == 0) - sign = 1; - } - } - printk(KERN_CONT "\n"); -} - -void -adpt_hppe_debug_queue_tx_counter_get(a_bool_t show_type) -{ - union queue_tx_counter_tbl_u queue_tx_counter_tbl; - a_uint64_t value; - int i, tags, sign; - - sign = tags = 0; - printk("%-35s", "QUEUE_TX_COUNTER_TBL TX:"); - for (i = 0; i < QUEUE_TX_COUNTER_TBL_MAX_ENTRY; i++) - { - hppe_queue_tx_counter_tbl_get(0, i, &queue_tx_counter_tbl); - if (show_type == A_FALSE) - value = (a_uint64_t)queue_tx_counter_tbl.bf.tx_packets; - else - value = queue_tx_counter_tbl.bf.tx_bytes_0 | ((a_uint64_t)queue_tx_counter_tbl.bf.tx_bytes_1 << 32); - if (value > 0) - { - if (sign) { - printk(KERN_CONT "\n"); - printk(KERN_CONT "%-35s", ""); - } - sign = 0; - printk(KERN_CONT "%15llu(queue=%04d)", value, i); - if (++tags % 3 == 0) - sign = 1; - } - } - printk(KERN_CONT "\n"); -} - -void -adpt_hppe_debug_vp_tx_drop_counter_get(a_bool_t show_type) -{ - union vp_tx_drop_cnt_tbl_u vp_tx_drop_cnt_tbl; - a_uint64_t value; - int i, tags, sign; - - sign = tags = 0; - printk("%-35s", "VP_TX_DROP_CNT_TBL TX_DROP:"); - for (i = 0; i < VP_TX_DROP_CNT_TBL_MAX_ENTRY; i++) - { - hppe_vp_tx_drop_cnt_tbl_get(0, i, &vp_tx_drop_cnt_tbl); - if (show_type == A_FALSE) - value = (a_uint64_t)vp_tx_drop_cnt_tbl.bf.tx_drop_pkt_cnt; - else - value = vp_tx_drop_cnt_tbl.bf.tx_drop_byte_cnt_0 | ((a_uint64_t)vp_tx_drop_cnt_tbl.bf.tx_drop_byte_cnt_1 << 32); - if (value > 0) - { - if (sign) { - printk(KERN_CONT "\n"); - printk(KERN_CONT "%-35s", ""); - } - sign = 0; - printk(KERN_CONT "%15llu(port=%04d)", value, i); - if (++tags % 3 == 0) - sign = 1; - } - } - printk(KERN_CONT "\n"); -} - -void -adpt_hppe_debug_cpu_code_counter_get(a_bool_t show_type) -{ - union drop_cpu_cnt_tbl_u drop_cpu_cnt_tbl; - a_uint64_t value; - int i, tags, sign; - - sign = tags = 0; - printk("%-35s", "CPU_CODE_CNT_TBL:"); - for (i = 0; i < CPU_CODE_CNT_TBL_MAX_ENTRY; i++) - { - hppe_drop_cpu_cnt_tbl_get(0, i, &drop_cpu_cnt_tbl); - if (show_type == A_FALSE) - value = (a_uint64_t)drop_cpu_cnt_tbl.bf.pkt_cnt; - else - value = drop_cpu_cnt_tbl.bf.byte_cnt_0 | ((a_uint64_t)drop_cpu_cnt_tbl.bf.byte_cnt_1 << 32); - if (value > 0) - { - printk(KERN_CONT "\n"); - printk(KERN_CONT "%-35s", ""); - if (i >=0 && i <= 70) - printk(KERN_CONT "%15llu(%s)", value, cpucode[i]); - else if (i >= 79 && i <= 92) - printk(KERN_CONT "%15llu(%s)", value, cpucode[i - 8]); - else if (i >= 97 && i <= 102) - printk(KERN_CONT "%15llu(%s)", value, cpucode[i - 12]); - else if (i >= 107 && i <= 110) - printk(KERN_CONT "%15llu(%s)", value, cpucode[i - 16]); - else if (i >= 113 && i <= 127) - printk(KERN_CONT "%15llu(%s)", value, cpucode[i - 18]); - else if (i >= 136 && i <= 143) - printk(KERN_CONT "%15llu(%s)", value, cpucode[i - 26]); - else if (i >= 148 && i <= 174) - printk(KERN_CONT "%15llu(%s)", value, cpucode[i - 30]); - else if (i >= 178 && i <= 180) - printk(KERN_CONT "%15llu(%s)", value, cpucode[i - 33]); - else if (i >= 254 && i <= 255) - printk(KERN_CONT "%15llu(%s)", value, cpucode[i - 106]); - else - printk(KERN_CONT "%15llu(Reserved)", value); - } - } - printk(KERN_CONT "\n"); -} - -void -adpt_hppe_debug_drop_cpu_counter_get(a_bool_t show_type) -{ - union drop_cpu_cnt_tbl_u drop_cpu_cnt_tbl; - a_uint64_t value; - int i, tags, sign; - - sign = tags = 0; - printk("%-35s", "DROP_CPU_CNT_TBL:"); - for (i = CPU_CODE_CNT_TBL_MAX_ENTRY; i < DROP_CPU_CNT_TBL_MAX_ENTRY; i++) - { - hppe_drop_cpu_cnt_tbl_get(0, i, &drop_cpu_cnt_tbl); - if (show_type == A_FALSE) - value = (a_uint64_t)drop_cpu_cnt_tbl.bf.pkt_cnt; - else - value = drop_cpu_cnt_tbl.bf.byte_cnt_0 | ((a_uint64_t)drop_cpu_cnt_tbl.bf.byte_cnt_1 << 32); - if (value > 0) - { - printk(KERN_CONT "\n"); - printk(KERN_CONT "%-35s", ""); - printk(KERN_CONT "%15llu(port=%d:%s)", value, (i - 256) % 8, dropcode[(i - 256) / 8]); - } - } - printk(KERN_CONT "\n"); -} - -/* if show_type = A_FALSE, show packets. - * if show_type = A_TRUE, show bytes. - */ -sw_error_t -adpt_hppe_debug_counter_get(a_bool_t show_type) -{ - /* show PRX DROP_CNT */ - adpt_hppe_debug_prx_drop_cnt_get(); - - /* show PRX DROP_PKT_STAT */ - adpt_hppe_debug_prx_drop_pkt_stat_get(show_type); - - /* show IPR_PKT_NUM */ - adpt_hppe_debug_ipx_pkt_num_get(show_type); - - /* show VLAN_CNT_TBL */ - adpt_hppe_debug_vlan_counter_get(show_type); - - /* show PRE_L2_CNT_TBL */ - adpt_hppe_debug_pre_l2_counter_get(show_type); - - /* show PORT_TX_DROP_CNT_TBL */ - adpt_hppe_debug_port_tx_drop_counter_get(show_type); - - /* show EG_VSI_COUNTER_TBL */ - adpt_hppe_debug_eg_vsi_counter_get(show_type); - - /* show PORT_TX_COUNTER_TBL */ - adpt_hppe_debug_port_tx_counter_get(show_type); - - /* show VP_TX_COUNTER_TBL */ - adpt_hppe_debug_vp_tx_counter_get(show_type); - - /* show QUEUE_TX_COUNTER_TBL */ - adpt_hppe_debug_queue_tx_counter_get(show_type); - - /* show VP_TX_DROP_CNT_TBL */ - adpt_hppe_debug_vp_tx_drop_counter_get(show_type); - - /* show CPU_CODE_CNT */ - adpt_hppe_debug_cpu_code_counter_get(show_type); - - /* show DROP_CPU_CNT_TBL */ - adpt_hppe_debug_drop_cpu_counter_get(show_type); - - return SW_OK; -} -#endif -sw_error_t adpt_hppe_misc_init(a_uint32_t dev_id) -{ - adpt_api_t *p_adpt_api = NULL; - - p_adpt_api = adpt_api_ptr_get(dev_id); - - if(p_adpt_api == NULL) { - return SW_FAIL; - } - -#ifndef IN_MISC_MINI - p_adpt_api->adpt_debug_port_counter_enable = adpt_ppe_debug_port_counter_enable; - p_adpt_api->adpt_debug_port_counter_status_get = adpt_ppe_debug_port_counter_status_get; - - p_adpt_api->adpt_debug_counter_set = adpt_hppe_debug_counter_set; - p_adpt_api->adpt_debug_counter_get = adpt_hppe_debug_counter_get; -#endif - return SW_OK; -} - -/** - * @} - */ diff --git a/feeds/ipq807x/qca-ssdk/src/src/adpt/hppe/adpt_hppe_policer.c b/feeds/ipq807x/qca-ssdk/src/src/adpt/hppe/adpt_hppe_policer.c deleted file mode 100755 index cf6191a1b..000000000 --- a/feeds/ipq807x/qca-ssdk/src/src/adpt/hppe/adpt_hppe_policer.c +++ /dev/null @@ -1,1138 +0,0 @@ -/* - * Copyright (c) 2016-2017, 2021, The Linux Foundation. All rights reserved. - * Permission to use, copy, modify, and/or distribute this software for - * any purpose with or without fee is hereby granted, provided that the - * above copyright notice and this permission notice appear in all copies. - * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES - * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR - * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES - * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN - * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT - * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. - */ - - -/** - * @defgroup - * @{ - */ -#include "sw.h" -#include "hppe_policer_reg.h" -#include "hppe_policer.h" -#include "adpt.h" - -#define NR_ADPT_HPPE_POLICER_METER_UNIT 2 -#define NR_ADPT_HPPE_POLICER_METER_TOKEN_UNIT 8 -#define ADPT_HPPE_POLICER_METER_UNIT_BYTE 0 -#define ADPT_HPPE_POLICER_METER_UNIT_FRAME 1 -#define ADPT_HPPE_FREQUENCY 300 /*MHZ*/ -#define ADPT_HPPE_POLICER_BURST_SIZE_UNIT 65536 -#define ADPT_HPPE_POLICER_REFRESH_BITS 18 -#define ADPT_HPPE_POLICER_BUCKET_SIZE_BITS 16 -#define ADPT_HPPE_POLICER_REFRESH_MAX ((1 << ADPT_HPPE_POLICER_REFRESH_BITS) - 1) -#define ADPT_HPPE_POLICER_BUCKET_SIZE_MAX ((1 << ADPT_HPPE_POLICER_BUCKET_SIZE_BITS) - 1) -#define BYTE_POLICER_MAX_RATE 10000000 -#define BYTE_POLICER_MIN_RATE 64 -#define FRAME_POLICER_MAX_RATE 14881000 -#define FRAME_POLICER_MIN_RATE 6 - - -static a_uint32_t hppe_policer_token_unit[NR_ADPT_HPPE_POLICER_METER_UNIT] - [NR_ADPT_HPPE_POLICER_METER_TOKEN_UNIT] = {{2048 * 8, - 512 * 8,128 * 8,32 * 8,8 * 8,2 * 8, 4, 1}, - {2097152,524288,131072,32768,8192,2048,512,128}}; - -typedef struct -{ - a_uint64_t rate_1bit; - a_uint64_t rate_max; -} adpt_hppe_policer_rate_t; - -typedef struct -{ - a_uint64_t burst_size_1bit; - a_uint64_t burst_size_max; -} adpt_hppe_policer_burst_size_t; - -static adpt_hppe_policer_rate_t -hppe_policer_rate[NR_ADPT_HPPE_POLICER_METER_UNIT][NR_ADPT_HPPE_POLICER_METER_TOKEN_UNIT] = -{ - /* byte based*/ - { - {0,0}, - {0,0}, - {0,0}, - {0,0}, - {0,0}, - {0,0}, - {0,0}, - {0,0}, - }, - - /*frame based */ - { - {0,0}, - {0,0}, - {0,0}, - {0,0}, - {0,0}, - {0,0}, - {0,0}, - {0,0}, - }, -}; - -static adpt_hppe_policer_burst_size_t -hppe_policer_burst_size[NR_ADPT_HPPE_POLICER_METER_UNIT][NR_ADPT_HPPE_POLICER_METER_TOKEN_UNIT] = -{ - { {0,0}, - {0,0}, - {0,0}, - {0,0}, - {0,0}, - {0,0}, - {0,0}, - {0,0}, - }, - { {0,0}, - {0,0}, - {0,0}, - {0,0}, - {0,0}, - {0,0}, - {0,0}, - {0,0}, - }, -}; - -#ifndef IN_POLICER_MINI -sw_error_t -adpt_hppe_acl_policer_counter_get(a_uint32_t dev_id, a_uint32_t index, - fal_policer_counter_t *counter) -{ - union in_acl_meter_cnt_tbl_u in_acl_meter_cnt_tbl; - - memset(&in_acl_meter_cnt_tbl, 0, sizeof(in_acl_meter_cnt_tbl)); - ADPT_DEV_ID_CHECK(dev_id); - ADPT_NULL_POINT_CHECK(counter); - - if (index < 0 || index > 511) - return SW_BAD_PARAM; - - hppe_in_acl_meter_cnt_tbl_get(dev_id, index * 3, &in_acl_meter_cnt_tbl); - counter->green_packet_counter = in_acl_meter_cnt_tbl.bf.pkt_cnt; - counter->green_byte_counter = in_acl_meter_cnt_tbl.bf.byte_cnt_1; - counter->green_byte_counter = (counter->green_byte_counter << 32) | in_acl_meter_cnt_tbl.bf.byte_cnt_0; - - hppe_in_acl_meter_cnt_tbl_get(dev_id, index * 3 + 1, &in_acl_meter_cnt_tbl); - counter->yellow_packet_counter = in_acl_meter_cnt_tbl.bf.pkt_cnt; - counter->yellow_byte_counter = in_acl_meter_cnt_tbl.bf.byte_cnt_1; - counter->yellow_byte_counter = (counter->yellow_byte_counter << 32) | in_acl_meter_cnt_tbl.bf.byte_cnt_0; - - hppe_in_acl_meter_cnt_tbl_get(dev_id, index * 3 + 2, &in_acl_meter_cnt_tbl); - counter->red_packet_counter = in_acl_meter_cnt_tbl.bf.pkt_cnt; - counter->red_byte_counter = in_acl_meter_cnt_tbl.bf.byte_cnt_1; - counter->red_byte_counter = (counter->red_byte_counter << 32) | in_acl_meter_cnt_tbl.bf.byte_cnt_0; - - return SW_OK; -} - -sw_error_t -adpt_hppe_port_policer_counter_get(a_uint32_t dev_id, fal_port_t port_id, - fal_policer_counter_t *counter) -{ - union in_port_meter_cnt_tbl_u in_port_meter_cnt_tbl; - - memset(&in_port_meter_cnt_tbl, 0, sizeof(in_port_meter_cnt_tbl)); - ADPT_DEV_ID_CHECK(dev_id); - ADPT_NULL_POINT_CHECK(counter); - - if (port_id < 0 || port_id > 7) - return SW_BAD_PARAM; - - hppe_in_port_meter_cnt_tbl_get(dev_id, port_id * 3, &in_port_meter_cnt_tbl); - counter->green_packet_counter = in_port_meter_cnt_tbl.bf.pkt_cnt; - counter->green_byte_counter = in_port_meter_cnt_tbl.bf.byte_cnt_1; - counter->green_byte_counter = (counter->green_byte_counter << 32) | in_port_meter_cnt_tbl.bf.byte_cnt_0; - - hppe_in_port_meter_cnt_tbl_get(dev_id, port_id * 3 + 1, &in_port_meter_cnt_tbl); - counter->yellow_packet_counter = in_port_meter_cnt_tbl.bf.pkt_cnt; - counter->yellow_byte_counter = in_port_meter_cnt_tbl.bf.byte_cnt_1; - counter->yellow_byte_counter = (counter->yellow_byte_counter << 32) | in_port_meter_cnt_tbl.bf.byte_cnt_0; - - hppe_in_port_meter_cnt_tbl_get(dev_id, port_id * 3 + 2, &in_port_meter_cnt_tbl); - counter->red_packet_counter = in_port_meter_cnt_tbl.bf.pkt_cnt; - counter->red_byte_counter = in_port_meter_cnt_tbl.bf.byte_cnt_1; - counter->red_byte_counter = (counter->red_byte_counter << 32) | in_port_meter_cnt_tbl.bf.byte_cnt_0; - - return SW_OK; -} - -sw_error_t -adpt_hppe_port_compensation_byte_get(a_uint32_t dev_id, fal_port_t port_id, - a_uint32_t *length) -{ - sw_error_t rv = SW_OK; - union meter_cmpst_length_reg_u meter_cmpst_length_reg; - - memset(&meter_cmpst_length_reg, 0, sizeof(meter_cmpst_length_reg)); - ADPT_DEV_ID_CHECK(dev_id); - ADPT_NULL_POINT_CHECK(length); - - if (port_id < 0 || port_id > 7) - return SW_BAD_PARAM; - - rv = hppe_meter_cmpst_length_reg_get(dev_id, port_id, &meter_cmpst_length_reg); - - if( rv != SW_OK ) - return rv; - - *length = meter_cmpst_length_reg.bf.cmpst_length; - - return SW_OK; -} - -static sw_error_t -__adpt_hppe_policer_rate_to_refresh(a_uint32_t rate, - a_uint32_t *refresh, - a_bool_t meter_unit, - a_uint32_t token_unit) -{ - a_uint32_t temp_refresh; - a_uint64_t temp_rate; - - if(hppe_policer_rate[meter_unit][token_unit].rate_1bit > 0) - { - temp_rate = ((a_uint64_t)rate) * 1000; - do_div(temp_rate, hppe_policer_rate[meter_unit][token_unit].rate_1bit); - temp_refresh = temp_rate; - } - else - { - return SW_BAD_PARAM;; - } - - if (temp_refresh > ADPT_HPPE_POLICER_REFRESH_MAX) - { - temp_refresh = ADPT_HPPE_POLICER_REFRESH_MAX; - } - - *refresh = temp_refresh; - - return SW_OK; -} - -static sw_error_t -__adpt_hppe_policer_burst_size_to_bucket_size(a_uint32_t burst_size, - a_uint32_t *bucket_size, - a_bool_t meter_unit, - a_uint32_t token_unit) -{ - a_uint32_t temp_bucket_size; - a_uint64_t temp_burst_size; - - if(hppe_policer_burst_size[meter_unit][token_unit].burst_size_1bit > 0) - { - temp_burst_size = ((a_uint64_t)burst_size) * 1000; - do_div(temp_burst_size, hppe_policer_burst_size[meter_unit][token_unit].burst_size_1bit); - temp_bucket_size = temp_burst_size; - } - else - { - return SW_BAD_PARAM; - } - - if(temp_bucket_size > ADPT_HPPE_POLICER_BUCKET_SIZE_MAX) - { - temp_bucket_size = ADPT_HPPE_POLICER_BUCKET_SIZE_MAX; - } - - *bucket_size = temp_bucket_size; - - return SW_OK; -} - -static sw_error_t -__adpt_hppe_policer_refresh_to_rate(a_uint32_t refresh, - a_uint32_t *rate, - a_bool_t meter_unit, - a_uint32_t token_unit) -{ - a_uint32_t temp_rate; - a_uint64_t temp_refresh; - - if(hppe_policer_rate[meter_unit][token_unit].rate_1bit > 0) - { - temp_refresh = ((a_uint64_t)refresh) * hppe_policer_rate[meter_unit][token_unit].rate_1bit; - do_div(temp_refresh, 1000); - temp_rate = temp_refresh; - } - else - { - return SW_BAD_PARAM;; - } - - *rate = temp_rate; - - return SW_OK; -} - -static sw_error_t -__adpt_hppe_policer_bucket_size_to_burst_size(a_uint32_t bucket_size, - a_uint32_t *burst_size, - a_bool_t meter_unit, - a_uint32_t token_unit) -{ - a_uint32_t temp_burst_size; - a_uint64_t temp_bucket_size; - - if(hppe_policer_burst_size[meter_unit][token_unit].burst_size_1bit > 0) - { - temp_bucket_size = ((a_uint64_t)bucket_size) * hppe_policer_burst_size[meter_unit][token_unit].burst_size_1bit; - do_div(temp_bucket_size, 1000); - temp_burst_size = temp_bucket_size; - } - else - { - return SW_BAD_PARAM; - } - - *burst_size = temp_burst_size; - - return SW_OK; -} -#endif - -static sw_error_t -__adpt_hppe_policer_max_rate(a_uint32_t time_slot) -{ - a_uint32_t i = 0, j = 0; - a_uint32_t time_cycle = 0; - a_uint64_t temp = 0, temp1 = 0, temp2 = 0; - - - /* time_cycle is ns*/ - time_cycle = ( time_slot * 8)/ ADPT_HPPE_FREQUENCY; - - for (j = 0; j < 8; j++) - { - /*max rate is bps*/ - temp1 = (a_uint64_t)(ADPT_HPPE_POLICER_REFRESH_MAX * 1000 * 8) * 1000; - temp2 = hppe_policer_token_unit[i][j] * time_cycle; - - do_div(temp1, temp2); - hppe_policer_rate[i][j].rate_max= temp1; - - temp = temp1; - do_div(temp, ADPT_HPPE_POLICER_REFRESH_MAX); - hppe_policer_rate[i][j].rate_1bit = temp; - - // printk("hppe policer byte max_rate generating =%llu\n", hppe_policer_rate[i][j].rate_max); - // printk("hppe policer byte based step =%llu\n", hppe_policer_rate[i][j].rate_1bit); - } - - i = i + 1; - for (j = 0; j < 8; j++) - { - /* max rate unit is 1/1000 pps*/ - temp1 = (a_uint64_t)(ADPT_HPPE_POLICER_REFRESH_MAX * 1000) * 1000 * 1000; - temp2 = (a_uint64_t)hppe_policer_token_unit[i][j] * time_cycle; - - do_div(temp1, temp2); - hppe_policer_rate[i][j].rate_max = temp1; - - temp = temp1; - do_div(temp, ADPT_HPPE_POLICER_REFRESH_MAX); - hppe_policer_rate[i][j].rate_1bit = temp; - - // printk("policer frame hppe_max_rate generating =%llu\n", hppe_policer_rate[i][j].rate_max); - // printk("policer frame step rate =%llu\n", hppe_policer_rate[i][j].rate_1bit); - } - - return SW_OK; -} - -static sw_error_t -__adpt_hppe_policer_max_burst_size(void) -{ - a_uint32_t i = 0, j = 0; - a_uint64_t temp = 0, temp1 = 0; - - - for (j = 0; j < 8; j++) - { - /*max size unit is 1/1000 byte based*/ - temp = ((a_uint64_t)(ADPT_HPPE_POLICER_BURST_SIZE_UNIT)) * - ADPT_HPPE_POLICER_BUCKET_SIZE_MAX; - do_div(temp, hppe_policer_token_unit[i][j]); - hppe_policer_burst_size[i][j].burst_size_max = (a_uint64_t)(temp * 1000); - - temp1 = hppe_policer_burst_size[i][j].burst_size_max; - do_div(temp1, ADPT_HPPE_POLICER_BUCKET_SIZE_MAX); - hppe_policer_burst_size[i][j].burst_size_1bit = temp1; - - /* - printk("policer byte hppe_max_burst_size generating =%llu\n", - hppe_policer_burst_size[i][j].burst_size_max); - printk("policer byte hppe_max_burst_size step =%llu\n", - hppe_policer_burst_size[i][j].burst_size_1bit); - */ - - } - - i = i + 1; - for (j = 0; j < 8; j++) - { - /* max size unit is 1/1000 frame based */ - temp = ((a_uint64_t)(ADPT_HPPE_POLICER_BURST_SIZE_UNIT)) * - ADPT_HPPE_POLICER_BUCKET_SIZE_MAX; - do_div(temp, hppe_policer_token_unit[i][j]); - hppe_policer_burst_size[i][j].burst_size_max = (a_uint64_t)(temp * 1000); - - temp1 = hppe_policer_burst_size[i][j].burst_size_max; - do_div(temp1, ADPT_HPPE_POLICER_BUCKET_SIZE_MAX); - hppe_policer_burst_size[i][j].burst_size_1bit = temp1; - - /* - printk("policer frame hppe_max_burst_size generating =%llu\n", - hppe_policer_burst_size[i][j].burst_size_max); - printk("policer frame hppe_max_burst_size step =%llu\n", - hppe_policer_burst_size[i][j].burst_size_1bit); - */ - - } - - return SW_OK; -} - -#ifndef IN_POLICER_MINI -static sw_error_t -__adpt_hppe_policer_two_bucket_parameter_select(a_uint64_t c_rate, - a_uint64_t c_burst_size, - a_uint64_t e_rate, - a_uint64_t e_burst_size, - a_uint32_t meter_unit, - a_uint32_t *token_unit) -{ - a_uint32_t temp_token_unit; - a_uint32_t match = A_FALSE; - a_uint64_t temp_rate = 0, temp_burst_size = 0; - - if(c_rate > e_rate) - temp_rate = c_rate; - else - temp_rate = e_rate; - - if(c_burst_size > e_burst_size) - temp_burst_size = c_burst_size; - else - temp_burst_size = e_burst_size; - - for (temp_token_unit = 0; temp_token_unit < 8; temp_token_unit++) - { - if (temp_rate > hppe_policer_rate[meter_unit][temp_token_unit].rate_max) - { - continue; - } - else if(temp_burst_size <= hppe_policer_burst_size[meter_unit][temp_token_unit].burst_size_max) - { - *token_unit = temp_token_unit; - match = A_TRUE; - break; - } - } - - if (match == A_FALSE) - { - printk("Not match C and E token bucket parameter rate configuration \n"); - return SW_BAD_PARAM; - } - - return SW_OK; -} - -#if 0 -static sw_error_t -__adpt_hppe_policer_one_bucket_parameter_select(a_uint64_t c_rate, - a_uint64_t c_burst_size, - a_uint32_t meter_unit, - a_uint32_t *token_unit) -{ - a_uint32_t temp_token_unit; - a_uint32_t match = A_FALSE; - - for (temp_token_unit = 0; temp_token_unit < 8; temp_token_unit++) - { - if (c_rate > hppe_policer_rate[meter_unit][temp_token_unit].rate_max) - { - continue; - } - else if (c_burst_size <= hppe_policer_burst_size[meter_unit][temp_token_unit].burst_size_max) - { - *token_unit = temp_token_unit; - match = A_TRUE; - break; - } - } - - if (match == A_FALSE) - { - printk("Not match policer C token bucket parameter rate configuration \n"); - return SW_BAD_PARAM; - } - - return SW_OK; -} -#endif - -sw_error_t -adpt_hppe_port_policer_entry_get(a_uint32_t dev_id, fal_port_t port_id, - fal_policer_config_t *policer, fal_policer_action_t *action) -{ - union in_port_meter_cfg_tbl_u in_port_meter_cfg_tbl; - a_uint32_t hppe_cir =0, hppe_cbs = 0, hppe_eir = 0,hppe_ebs = 0; - - memset(&in_port_meter_cfg_tbl, 0, sizeof(in_port_meter_cfg_tbl)); - - ADPT_DEV_ID_CHECK(dev_id); - ADPT_NULL_POINT_CHECK(policer); - ADPT_NULL_POINT_CHECK(action); - - if (port_id < 0 || port_id > 7) - return SW_BAD_PARAM; - - hppe_in_port_meter_cfg_tbl_get(dev_id, port_id, &in_port_meter_cfg_tbl); - - hppe_cir = (in_port_meter_cfg_tbl.bf.cir_1 << 3) | in_port_meter_cfg_tbl.bf.cir_0; - hppe_cbs = in_port_meter_cfg_tbl.bf.cbs; - hppe_eir = (in_port_meter_cfg_tbl.bf.eir_1 << 1) | in_port_meter_cfg_tbl.bf.eir_0; - hppe_ebs = in_port_meter_cfg_tbl.bf.ebs; - - - __adpt_hppe_policer_refresh_to_rate(hppe_cir, - &policer->cir, - in_port_meter_cfg_tbl.bf.meter_unit, - in_port_meter_cfg_tbl.bf.token_unit); - - __adpt_hppe_policer_refresh_to_rate(hppe_eir, - &policer->eir, - in_port_meter_cfg_tbl.bf.meter_unit, - in_port_meter_cfg_tbl.bf.token_unit); - - __adpt_hppe_policer_bucket_size_to_burst_size(hppe_cbs, - &policer->cbs, - in_port_meter_cfg_tbl.bf.meter_unit, - in_port_meter_cfg_tbl.bf.token_unit); - - __adpt_hppe_policer_bucket_size_to_burst_size(hppe_ebs, - &policer->ebs, - in_port_meter_cfg_tbl.bf.meter_unit, - in_port_meter_cfg_tbl.bf.token_unit); - - policer->meter_en = in_port_meter_cfg_tbl.bf.meter_en; - policer->color_mode = in_port_meter_cfg_tbl.bf.color_mode; - policer->frame_type = in_port_meter_cfg_tbl.bf.meter_flag; - policer->couple_en = in_port_meter_cfg_tbl.bf.coupling_flag; - policer->meter_mode = in_port_meter_cfg_tbl.bf.meter_mode; - policer->meter_unit = in_port_meter_cfg_tbl.bf.meter_unit; - action->yellow_priority_en = in_port_meter_cfg_tbl.bf.exceed_chg_pri_cmd; - action->yellow_drop_priority_en = in_port_meter_cfg_tbl.bf.exceed_chg_dp_cmd; - action->yellow_pcp_en = in_port_meter_cfg_tbl.bf.exceed_chg_pcp_cmd; - action->yellow_dei_en = in_port_meter_cfg_tbl.bf.exceed_chg_dei_cmd; - action->yellow_priority = in_port_meter_cfg_tbl.bf.exceed_pri; - action->yellow_drop_priority = in_port_meter_cfg_tbl.bf.exceed_dp; - action->yellow_pcp = in_port_meter_cfg_tbl.bf.exceed_pcp; - action->yellow_dei = in_port_meter_cfg_tbl.bf.exceed_dei; - if (in_port_meter_cfg_tbl.bf.violate_cmd == 0) - action->red_action = FAL_MAC_DROP; - else - action->red_action = FAL_MAC_FRWRD; - action->red_priority_en = in_port_meter_cfg_tbl.bf.violate_chg_pri_cmd; - action->red_drop_priority_en = in_port_meter_cfg_tbl.bf.violate_chg_dp_cmd; - action->red_pcp_en = in_port_meter_cfg_tbl.bf.violate_chg_pcp_cmd; - action->red_dei_en = in_port_meter_cfg_tbl.bf.violate_chg_dei_cmd; - action->red_priority = in_port_meter_cfg_tbl.bf.violate_pri; - action->red_drop_priority = in_port_meter_cfg_tbl.bf.violate_dp; - action->red_pcp = in_port_meter_cfg_tbl.bf.violate_pcp; - action->red_dei = in_port_meter_cfg_tbl.bf.violate_dei; - - return SW_OK; -} - -sw_error_t -adpt_hppe_port_policer_entry_set(a_uint32_t dev_id, fal_port_t port_id, - fal_policer_config_t *policer, fal_policer_action_t *action) -{ - union in_port_meter_cfg_tbl_u in_port_meter_cfg_tbl; - a_uint32_t hppe_cir = 0, hppe_cbs = 0, hppe_eir = 0,hppe_ebs = 0; - a_uint64_t temp_cir = 0, temp_eir =0, temp_cbs =0, temp_ebs = 0; - a_uint32_t token_unit = 0; - sw_error_t rv = SW_OK; - - memset(&in_port_meter_cfg_tbl, 0, sizeof(in_port_meter_cfg_tbl)); - - ADPT_DEV_ID_CHECK(dev_id); - ADPT_NULL_POINT_CHECK(policer); - ADPT_NULL_POINT_CHECK(action); - - if (port_id < 0 || port_id > 7) - return SW_BAD_PARAM; - - if(ADPT_HPPE_POLICER_METER_UNIT_BYTE == policer->meter_unit) - { - if ((policer->cir > BYTE_POLICER_MAX_RATE) || (policer->eir > BYTE_POLICER_MAX_RATE)) - return SW_BAD_PARAM; - if ((policer->cir < BYTE_POLICER_MIN_RATE) && (policer->cir != 0)) - return SW_BAD_PARAM; - if ((policer->eir < BYTE_POLICER_MIN_RATE) && (policer->eir != 0)) - return SW_BAD_PARAM; - } - - if(ADPT_HPPE_POLICER_METER_UNIT_FRAME == policer->meter_unit) - { - if ((policer->cir > FRAME_POLICER_MAX_RATE) || (policer->eir > FRAME_POLICER_MAX_RATE)) - return SW_BAD_PARAM; - if ((policer->cir < FRAME_POLICER_MIN_RATE) && (policer->cir != 0)) - return SW_BAD_PARAM; - if ((policer->eir < FRAME_POLICER_MIN_RATE) && (policer->eir != 0)) - return SW_BAD_PARAM; - } - - if((0 == policer->meter_mode) && (policer->cir > policer->eir)) - return SW_BAD_PARAM; - - temp_cir = ((a_uint64_t)policer->cir) * 1000; - temp_cbs = ((a_uint64_t)policer->cbs) * 1000; - temp_eir = ((a_uint64_t)policer->eir) * 1000; - temp_ebs = ((a_uint64_t)policer->ebs) * 1000; - - rv = __adpt_hppe_policer_two_bucket_parameter_select(temp_cir, - temp_cbs, - temp_eir, - temp_ebs, - policer->meter_unit, - &token_unit); - if( rv != SW_OK ) - return rv; - -// printk("current meter unit is = %d\n", policer->meter_unit); -// printk("current token unit is = %d\n", token_unit); - - __adpt_hppe_policer_rate_to_refresh(policer->cir, - &hppe_cir, - policer->meter_unit, - token_unit); - - __adpt_hppe_policer_rate_to_refresh(policer->eir, - &hppe_eir, - policer->meter_unit, - token_unit); - - __adpt_hppe_policer_burst_size_to_bucket_size(policer->cbs, - &hppe_cbs, - policer->meter_unit, - token_unit); - - __adpt_hppe_policer_burst_size_to_bucket_size(policer->ebs, - &hppe_ebs, - policer->meter_unit, - token_unit); - - in_port_meter_cfg_tbl.bf.meter_en = policer->meter_en; - in_port_meter_cfg_tbl.bf.color_mode = policer->color_mode; - in_port_meter_cfg_tbl.bf.meter_flag = policer->frame_type; - in_port_meter_cfg_tbl.bf.coupling_flag = policer->couple_en; - in_port_meter_cfg_tbl.bf.meter_mode = policer->meter_mode; - in_port_meter_cfg_tbl.bf.token_unit = token_unit; - in_port_meter_cfg_tbl.bf.meter_unit = (a_uint32_t)policer->meter_unit; - in_port_meter_cfg_tbl.bf.cbs = hppe_cbs; - in_port_meter_cfg_tbl.bf.cir_0 = hppe_cir & 0x7; - in_port_meter_cfg_tbl.bf.cir_1 = hppe_cir >> 3; - in_port_meter_cfg_tbl.bf.ebs = hppe_ebs; - in_port_meter_cfg_tbl.bf.eir_0 = hppe_eir & 0x1; - in_port_meter_cfg_tbl.bf.eir_1 = hppe_eir >> 1; - in_port_meter_cfg_tbl.bf.exceed_chg_pri_cmd = action->yellow_priority_en; - in_port_meter_cfg_tbl.bf.exceed_chg_dp_cmd = action->yellow_drop_priority_en; - in_port_meter_cfg_tbl.bf.exceed_chg_pcp_cmd = action->yellow_pcp_en; - in_port_meter_cfg_tbl.bf.exceed_chg_dei_cmd = action->yellow_dei_en; - in_port_meter_cfg_tbl.bf.exceed_pri = action->yellow_priority; - in_port_meter_cfg_tbl.bf.exceed_dp = action->yellow_drop_priority; - in_port_meter_cfg_tbl.bf.exceed_pcp = action->yellow_pcp; - in_port_meter_cfg_tbl.bf.exceed_dei = action->yellow_dei; - if (action->red_action == FAL_MAC_DROP) - in_port_meter_cfg_tbl.bf.violate_cmd = 0; - else - in_port_meter_cfg_tbl.bf.violate_cmd = 1; - in_port_meter_cfg_tbl.bf.violate_chg_pri_cmd = action->red_priority_en; - in_port_meter_cfg_tbl.bf.violate_chg_dp_cmd = action->red_drop_priority_en; - in_port_meter_cfg_tbl.bf.violate_chg_pcp_cmd = action->red_pcp_en; - in_port_meter_cfg_tbl.bf.violate_chg_dei_cmd = action->red_dei_en; - in_port_meter_cfg_tbl.bf.violate_pri = action->red_priority; - in_port_meter_cfg_tbl.bf.violate_dp = action->red_drop_priority; - in_port_meter_cfg_tbl.bf.violate_pcp = action->red_pcp; - in_port_meter_cfg_tbl.bf.violate_dei = action->red_dei; - - hppe_in_port_meter_cfg_tbl_set(dev_id, port_id, &in_port_meter_cfg_tbl); - - return SW_OK; - -} -sw_error_t -adpt_hppe_acl_policer_entry_get(a_uint32_t dev_id, a_uint32_t index, - fal_policer_config_t *policer, fal_policer_action_t *action) -{ - union in_acl_meter_cfg_tbl_u in_acl_meter_cfg_tbl; - a_uint32_t hppe_cir =0, hppe_cbs = 0, hppe_eir = 0,hppe_ebs = 0; - - memset(&in_acl_meter_cfg_tbl, 0, sizeof(in_acl_meter_cfg_tbl)); - - ADPT_DEV_ID_CHECK(dev_id); - ADPT_NULL_POINT_CHECK(policer); - ADPT_NULL_POINT_CHECK(action); - - if (index < 0 || index > 511) - return SW_BAD_PARAM; - - hppe_in_acl_meter_cfg_tbl_get(dev_id, index, &in_acl_meter_cfg_tbl); - - hppe_cir = (in_acl_meter_cfg_tbl.bf.cir_1 << 8) | in_acl_meter_cfg_tbl.bf.cir_0; - hppe_cbs = in_acl_meter_cfg_tbl.bf.cbs; - hppe_eir = (in_acl_meter_cfg_tbl.bf.eir_1 << 6) | in_acl_meter_cfg_tbl.bf.eir_0; - hppe_ebs = in_acl_meter_cfg_tbl.bf.ebs; - - __adpt_hppe_policer_refresh_to_rate(hppe_cir, - &policer->cir, - in_acl_meter_cfg_tbl.bf.meter_unit, - in_acl_meter_cfg_tbl.bf.token_unit); - - __adpt_hppe_policer_refresh_to_rate(hppe_eir, - &policer->eir, - in_acl_meter_cfg_tbl.bf.meter_unit, - in_acl_meter_cfg_tbl.bf.token_unit); - - __adpt_hppe_policer_bucket_size_to_burst_size(hppe_cbs, - &policer->cbs, - in_acl_meter_cfg_tbl.bf.meter_unit, - in_acl_meter_cfg_tbl.bf.token_unit); - - __adpt_hppe_policer_bucket_size_to_burst_size(hppe_ebs, - &policer->ebs, - in_acl_meter_cfg_tbl.bf.meter_unit, - in_acl_meter_cfg_tbl.bf.token_unit); - - policer->meter_en = in_acl_meter_cfg_tbl.bf.meter_en; - policer->color_mode = in_acl_meter_cfg_tbl.bf.color_mode; - policer->couple_en= in_acl_meter_cfg_tbl.bf.coupling_flag; - policer->meter_mode = in_acl_meter_cfg_tbl.bf.meter_mode; - policer->meter_unit = in_acl_meter_cfg_tbl.bf.meter_unit; - action->yellow_priority_en = in_acl_meter_cfg_tbl.bf.exceed_chg_pri_cmd; - action->yellow_drop_priority_en = in_acl_meter_cfg_tbl.bf.exceed_chg_dp_cmd; - action->yellow_pcp_en = in_acl_meter_cfg_tbl.bf.exceed_chg_pcp_cmd; - action->yellow_dei_en = in_acl_meter_cfg_tbl.bf.exceed_chg_dei_cmd; - action->yellow_priority = in_acl_meter_cfg_tbl.bf.exceed_pri; - action->yellow_drop_priority = in_acl_meter_cfg_tbl.bf.exceed_dp; - action->yellow_pcp = in_acl_meter_cfg_tbl.bf.exceed_pcp; - action->yellow_dei = in_acl_meter_cfg_tbl.bf.exceed_dei; - if (in_acl_meter_cfg_tbl.bf.violate_cmd == 0) - action->red_action = FAL_MAC_DROP; - else - action->red_action = FAL_MAC_FRWRD; - action->red_priority_en = in_acl_meter_cfg_tbl.bf.violate_chg_pri_cmd; - action->red_drop_priority_en = in_acl_meter_cfg_tbl.bf.violate_chg_dp_cmd; - action->red_pcp_en = in_acl_meter_cfg_tbl.bf.violate_chg_pcp_cmd; - action->red_dei_en = in_acl_meter_cfg_tbl.bf.violate_chg_dei_cmd; - action->red_priority = (in_acl_meter_cfg_tbl.bf.violate_pri_1 << 1) |in_acl_meter_cfg_tbl.bf.violate_pri_0; - action->red_drop_priority = in_acl_meter_cfg_tbl.bf.violate_dp; - action->red_pcp = in_acl_meter_cfg_tbl.bf.violate_pcp; - action->red_dei = in_acl_meter_cfg_tbl.bf.violate_dei; - - return SW_OK; -} - -sw_error_t -adpt_hppe_acl_policer_entry_set(a_uint32_t dev_id, a_uint32_t index, - fal_policer_config_t *policer, fal_policer_action_t *action) -{ - union in_acl_meter_cfg_tbl_u in_acl_meter_cfg_tbl; - a_uint32_t hppe_cir =0, hppe_cbs = 0, hppe_eir = 0,hppe_ebs = 0; - a_uint64_t temp_cir = 0, temp_eir =0, temp_cbs =0, temp_ebs = 0; - a_uint32_t token_unit = 0; - sw_error_t rv = SW_OK; - - memset(&in_acl_meter_cfg_tbl, 0, sizeof(in_acl_meter_cfg_tbl)); - - ADPT_DEV_ID_CHECK(dev_id); - ADPT_NULL_POINT_CHECK(policer); - ADPT_NULL_POINT_CHECK(action); - - if (index < 0 || index > 511) - return SW_BAD_PARAM; - - if(ADPT_HPPE_POLICER_METER_UNIT_BYTE == policer->meter_unit) - { - if ((policer->cir > BYTE_POLICER_MAX_RATE) || (policer->eir > BYTE_POLICER_MAX_RATE)) - return SW_BAD_PARAM; - if ((policer->cir < BYTE_POLICER_MIN_RATE) && (policer->cir != 0)) - return SW_BAD_PARAM; - if ((policer->eir < BYTE_POLICER_MIN_RATE) && (policer->eir != 0)) - return SW_BAD_PARAM; - } - - if(ADPT_HPPE_POLICER_METER_UNIT_FRAME == policer->meter_unit) - { - if ((policer->cir > FRAME_POLICER_MAX_RATE) || (policer->eir > FRAME_POLICER_MAX_RATE)) - return SW_BAD_PARAM; - if ((policer->cir < FRAME_POLICER_MIN_RATE) && (policer->cir != 0)) - return SW_BAD_PARAM; - if ((policer->eir < FRAME_POLICER_MIN_RATE) && (policer->eir != 0)) - return SW_BAD_PARAM; - } - - if((0 == policer->meter_mode) && (policer->cir > policer->eir)) - return SW_BAD_PARAM; - - temp_cir = ((a_uint64_t)policer->cir) * 1000; - temp_cbs = ((a_uint64_t)policer->cbs) * 1000; - temp_eir = ((a_uint64_t)policer->eir) * 1000; - temp_ebs = ((a_uint64_t)policer->ebs) * 1000; - - rv = __adpt_hppe_policer_two_bucket_parameter_select(temp_cir, - temp_cbs, - temp_eir, - temp_ebs, - policer->meter_unit, - &token_unit); - if( rv != SW_OK ) - return rv; - -// printk("current meter unit is = %d\n", policer->meter_unit); -// printk("current token unit is = %d\n", token_unit); - - __adpt_hppe_policer_rate_to_refresh(policer->cir, - &hppe_cir, - policer->meter_unit, - token_unit); - - __adpt_hppe_policer_rate_to_refresh(policer->eir, - &hppe_eir, - policer->meter_unit, - token_unit); - - __adpt_hppe_policer_burst_size_to_bucket_size(policer->cbs, - &hppe_cbs, - policer->meter_unit, - token_unit); - - __adpt_hppe_policer_burst_size_to_bucket_size(policer->ebs, - &hppe_ebs, - policer->meter_unit, - token_unit); - - in_acl_meter_cfg_tbl.bf.meter_en = policer->meter_en; - in_acl_meter_cfg_tbl.bf.color_mode = policer->color_mode; - in_acl_meter_cfg_tbl.bf.coupling_flag = policer->couple_en; - in_acl_meter_cfg_tbl.bf.meter_mode = policer->meter_mode; - in_acl_meter_cfg_tbl.bf.token_unit = token_unit; - in_acl_meter_cfg_tbl.bf.meter_unit = policer->meter_unit; - in_acl_meter_cfg_tbl.bf.cbs = hppe_cbs; - in_acl_meter_cfg_tbl.bf.cir_0 = hppe_cir & 0xff; - in_acl_meter_cfg_tbl.bf.cir_1 = hppe_cir >> 8; - in_acl_meter_cfg_tbl.bf.ebs = hppe_ebs; - in_acl_meter_cfg_tbl.bf.eir_0 = hppe_eir & 0x3f; - in_acl_meter_cfg_tbl.bf.eir_1 = hppe_eir >> 6; - in_acl_meter_cfg_tbl.bf.exceed_chg_pri_cmd = action->yellow_priority_en; - in_acl_meter_cfg_tbl.bf.exceed_chg_dp_cmd = action->yellow_drop_priority_en; - in_acl_meter_cfg_tbl.bf.exceed_chg_pcp_cmd = action->yellow_pcp_en; - in_acl_meter_cfg_tbl.bf.exceed_chg_dei_cmd = action->yellow_dei_en; - in_acl_meter_cfg_tbl.bf.exceed_pri = action->yellow_priority; - in_acl_meter_cfg_tbl.bf.exceed_dp = action->yellow_drop_priority; - in_acl_meter_cfg_tbl.bf.exceed_pcp = action->yellow_pcp; - in_acl_meter_cfg_tbl.bf.exceed_dei = action->yellow_dei; - if (action->red_action == FAL_MAC_DROP) - in_acl_meter_cfg_tbl.bf.violate_cmd = 0; - else - in_acl_meter_cfg_tbl.bf.violate_cmd = 1; - in_acl_meter_cfg_tbl.bf.violate_chg_pri_cmd = action->red_priority_en; - in_acl_meter_cfg_tbl.bf.violate_chg_dp_cmd = action->red_drop_priority_en; - in_acl_meter_cfg_tbl.bf.violate_chg_pcp_cmd = action->red_pcp_en; - in_acl_meter_cfg_tbl.bf.violate_chg_dei_cmd = action->red_dei_en; - in_acl_meter_cfg_tbl.bf.violate_pri_0 = action->red_priority & 0x1; - in_acl_meter_cfg_tbl.bf.violate_pri_1 = action->red_priority >>1; - in_acl_meter_cfg_tbl.bf.violate_dp = action->red_drop_priority; - in_acl_meter_cfg_tbl.bf.violate_pcp = action->red_pcp; - in_acl_meter_cfg_tbl.bf.violate_dei = action->red_dei; - - hppe_in_acl_meter_cfg_tbl_set(dev_id, index, &in_acl_meter_cfg_tbl); - - return SW_OK; -} - -sw_error_t -adpt_hppe_policer_time_slot_get(a_uint32_t dev_id, a_uint32_t *time_slot) -{ - sw_error_t rv = SW_OK; - union time_slot_reg_u time_slot_reg; - - memset(&time_slot_reg, 0, sizeof(time_slot_reg)); - ADPT_DEV_ID_CHECK(dev_id); - ADPT_NULL_POINT_CHECK(time_slot); - - - rv = hppe_time_slot_reg_get(dev_id, &time_slot_reg); - - if( rv != SW_OK ) - return rv; - - *time_slot = time_slot_reg.bf.time_slot; - - return SW_OK; -} -#endif - -sw_error_t -adpt_hppe_port_compensation_byte_set(a_uint32_t dev_id, fal_port_t port_id, - a_uint32_t length) -{ - union meter_cmpst_length_reg_u meter_cmpst_length_reg; - - memset(&meter_cmpst_length_reg, 0, sizeof(meter_cmpst_length_reg)); - ADPT_DEV_ID_CHECK(dev_id); - - if (port_id < 0 || port_id > 7) - return SW_BAD_PARAM; - - if (length > 0x1f) - return SW_BAD_PARAM; - - hppe_meter_cmpst_length_reg_get(dev_id, port_id, &meter_cmpst_length_reg); - meter_cmpst_length_reg.bf.cmpst_length = length; - - hppe_meter_cmpst_length_reg_set(dev_id, port_id, &meter_cmpst_length_reg); - - return SW_OK; -} -sw_error_t -adpt_hppe_policer_time_slot_set(a_uint32_t dev_id, a_uint32_t time_slot) -{ - union time_slot_reg_u time_slot_reg; - - memset(&time_slot_reg, 0, sizeof(time_slot_reg)); - ADPT_DEV_ID_CHECK(dev_id); - - if ((time_slot > 1024) || (time_slot < 512)) - return SW_BAD_PARAM; - - time_slot_reg.bf.time_slot = time_slot; - hppe_time_slot_reg_set(dev_id, &time_slot_reg); - - __adpt_hppe_policer_max_rate(time_slot); - - __adpt_hppe_policer_max_burst_size(); - - return SW_OK; -} -#ifndef IN_POLICER_MINI -sw_error_t -adpt_hppe_policer_global_counter_get(a_uint32_t dev_id, - fal_policer_global_counter_t *counter) -{ - union pc_global_cnt_tbl_u pc_global_cnt_tbl; - a_uint32_t index = 0; - - memset(&pc_global_cnt_tbl, 0, sizeof(pc_global_cnt_tbl)); - ADPT_DEV_ID_CHECK(dev_id); - ADPT_NULL_POINT_CHECK(counter); - - hppe_pc_global_cnt_tbl_get(dev_id, index, &pc_global_cnt_tbl); - counter->policer_drop_packet_counter = pc_global_cnt_tbl.bf.pkt_cnt; - counter->policer_drop_byte_counter = pc_global_cnt_tbl.bf.byte_cnt_1; - counter->policer_drop_byte_counter = (counter->policer_drop_byte_counter << 32) | - pc_global_cnt_tbl.bf.byte_cnt_0; - - hppe_pc_global_cnt_tbl_get(dev_id, index + 1, &pc_global_cnt_tbl); - counter->policer_forward_packet_counter = pc_global_cnt_tbl.bf.pkt_cnt; - counter->policer_forward_byte_counter = pc_global_cnt_tbl.bf.byte_cnt_1; - counter->policer_forward_byte_counter = (counter->policer_forward_byte_counter << 32) | - pc_global_cnt_tbl.bf.byte_cnt_0; - - hppe_pc_global_cnt_tbl_get(dev_id, index + 2, &pc_global_cnt_tbl); - counter->policer_bypass_packet_counter = pc_global_cnt_tbl.bf.pkt_cnt; - counter->policer_bypass_byte_counter = pc_global_cnt_tbl.bf.byte_cnt_1; - counter->policer_bypass_byte_counter = (counter->policer_bypass_byte_counter << 32) | - pc_global_cnt_tbl.bf.byte_cnt_0; - - return SW_OK; -} - -sw_error_t -adpt_hppe_policer_bypass_en_get(a_uint32_t dev_id, fal_policer_frame_type_t frame_type, - a_bool_t *enable) -{ - sw_error_t rv = SW_OK; - union pc_drop_bypass_reg_u drop_bypass_reg; - - memset(&drop_bypass_reg, 0, sizeof(drop_bypass_reg)); - ADPT_DEV_ID_CHECK(dev_id); - ADPT_NULL_POINT_CHECK(enable); - - rv = hppe_pc_drop_bypass_reg_get(dev_id, &drop_bypass_reg); - SW_RTN_ON_ERROR (rv); - - if (frame_type == FAL_FRAME_DROPPED) { - *enable = drop_bypass_reg.bf.drop_bypass_en; - } else { - return SW_BAD_PARAM; - } - - return SW_OK; -} - -#endif - -sw_error_t -adpt_hppe_policer_bypass_en_set(a_uint32_t dev_id, fal_policer_frame_type_t frame_type, - a_bool_t enable) -{ - sw_error_t rv = SW_OK; - union pc_drop_bypass_reg_u drop_bypass_reg; - - memset(&drop_bypass_reg, 0, sizeof(drop_bypass_reg)); - ADPT_DEV_ID_CHECK(dev_id); - - if (frame_type == FAL_FRAME_DROPPED) { - drop_bypass_reg.bf.drop_bypass_en = enable; - } else { - return SW_BAD_PARAM; - } - - rv = hppe_pc_drop_bypass_reg_set(dev_id, &drop_bypass_reg); - SW_RTN_ON_ERROR (rv); - - return SW_OK; -} - -void adpt_hppe_policer_func_bitmap_init(a_uint32_t dev_id) -{ - adpt_api_t *p_adpt_api = NULL; - - p_adpt_api = adpt_api_ptr_get(dev_id); - - if(p_adpt_api == NULL) - return; - - p_adpt_api->adpt_policer_func_bitmap = ((1 << FUNC_ADPT_ACL_POLICER_COUNTER_GET)| - (1 << FUNC_ADPT_PORT_POLICER_COUNTER_GET)| - (1 << FUNC_ADPT_PORT_COMPENSATION_BYTE_GET)| - (1 << FUNC_ADPT_PORT_POLICER_ENTRY_GET)| - (1 << FUNC_ADPT_PORT_POLICER_ENTRY_SET)| - (1 << FUNC_ADPT_ACL_POLICER_ENTRY_GET)| - (1 << FUNC_ADPT_ACL_POLICER_ENTRY_SET)| - (1 << FUNC_ADPT_POLICER_TIME_SLOT_GET)| - (1 << FUNC_ADPT_PORT_COMPENSATION_BYTE_SET)| - (1 << FUNC_ADPT_POLICER_TIME_SLOT_SET) | - (1 << FUNC_ADPT_POLICER_GLOBAL_COUNTER_GET)| - (1 << FUNC_ADPT_POLICER_BYPASS_EN_SET)| - (1 << FUNC_ADPT_POLICER_BYPASS_EN_GET)); - - return; - -} - -static void adpt_hppe_policer_func_unregister(a_uint32_t dev_id, adpt_api_t *p_adpt_api) -{ - if(p_adpt_api == NULL) - return; - - p_adpt_api->adpt_acl_policer_counter_get = NULL; - p_adpt_api->adpt_port_policer_counter_get = NULL; - p_adpt_api->adpt_port_compensation_byte_get = NULL; - p_adpt_api->adpt_port_policer_entry_get = NULL; - p_adpt_api->adpt_port_policer_entry_set = NULL; - p_adpt_api->adpt_acl_policer_entry_get = NULL; - p_adpt_api->adpt_acl_policer_entry_set = NULL; - p_adpt_api->adpt_policer_time_slot_get = NULL; - p_adpt_api->adpt_port_compensation_byte_set = NULL; - p_adpt_api->adpt_policer_time_slot_set = NULL; - p_adpt_api->adpt_policer_global_counter_get = NULL; - p_adpt_api->adpt_policer_bypass_en_set = NULL; - p_adpt_api->adpt_policer_bypass_en_get = NULL; - - return; - -} - - -sw_error_t adpt_hppe_policer_init(a_uint32_t dev_id) -{ - adpt_api_t *p_adpt_api = NULL; - - p_adpt_api = adpt_api_ptr_get(dev_id); - - if(p_adpt_api == NULL) - return SW_FAIL; - - adpt_hppe_policer_func_unregister(dev_id, p_adpt_api); - -#ifndef IN_POLICER_MINI - if(p_adpt_api->adpt_policer_func_bitmap & (1 << FUNC_ADPT_ACL_POLICER_COUNTER_GET)) - { - p_adpt_api->adpt_acl_policer_counter_get = adpt_hppe_acl_policer_counter_get; - } - if(p_adpt_api->adpt_policer_func_bitmap & (1 << FUNC_ADPT_PORT_POLICER_COUNTER_GET)) - { - p_adpt_api->adpt_port_policer_counter_get = adpt_hppe_port_policer_counter_get; - } - if(p_adpt_api->adpt_policer_func_bitmap & (1 << FUNC_ADPT_PORT_COMPENSATION_BYTE_GET)) - { - p_adpt_api->adpt_port_compensation_byte_get = adpt_hppe_port_compensation_byte_get; - } - if(p_adpt_api->adpt_policer_func_bitmap & (1 << FUNC_ADPT_PORT_POLICER_ENTRY_GET)) - { - p_adpt_api->adpt_port_policer_entry_get = adpt_hppe_port_policer_entry_get; - } - if(p_adpt_api->adpt_policer_func_bitmap & (1 << FUNC_ADPT_PORT_POLICER_ENTRY_SET)) - { - p_adpt_api->adpt_port_policer_entry_set = adpt_hppe_port_policer_entry_set; - } - if(p_adpt_api->adpt_policer_func_bitmap & (1 << FUNC_ADPT_ACL_POLICER_ENTRY_GET)) - { - p_adpt_api->adpt_acl_policer_entry_get = adpt_hppe_acl_policer_entry_get; - } - if(p_adpt_api->adpt_policer_func_bitmap & (1 << FUNC_ADPT_ACL_POLICER_ENTRY_SET)) - { - p_adpt_api->adpt_acl_policer_entry_set = adpt_hppe_acl_policer_entry_set; - } - if(p_adpt_api->adpt_policer_func_bitmap & (1 << FUNC_ADPT_POLICER_TIME_SLOT_GET)) - { - p_adpt_api->adpt_policer_time_slot_get = adpt_hppe_policer_time_slot_get; - } - if(p_adpt_api->adpt_policer_func_bitmap & (1 << FUNC_ADPT_POLICER_GLOBAL_COUNTER_GET)) - { - p_adpt_api->adpt_policer_global_counter_get = adpt_hppe_policer_global_counter_get; - } - if(p_adpt_api->adpt_policer_func_bitmap & (1 << FUNC_ADPT_POLICER_BYPASS_EN_GET)) - { - p_adpt_api->adpt_policer_bypass_en_get = adpt_hppe_policer_bypass_en_get; - } -#endif - if(p_adpt_api->adpt_policer_func_bitmap & (1 << FUNC_ADPT_PORT_COMPENSATION_BYTE_SET)) - { - p_adpt_api->adpt_port_compensation_byte_set = adpt_hppe_port_compensation_byte_set; - } - if(p_adpt_api->adpt_policer_func_bitmap & (1 << FUNC_ADPT_POLICER_TIME_SLOT_SET)) - { - p_adpt_api->adpt_policer_time_slot_set = adpt_hppe_policer_time_slot_set; - } - if(p_adpt_api->adpt_policer_func_bitmap & (1 << FUNC_ADPT_POLICER_BYPASS_EN_SET)) - { - p_adpt_api->adpt_policer_bypass_en_set = adpt_hppe_policer_bypass_en_set; - } - - return SW_OK; -} - -/** - * @} - */ - diff --git a/feeds/ipq807x/qca-ssdk/src/src/adpt/hppe/adpt_hppe_portctrl.c b/feeds/ipq807x/qca-ssdk/src/src/adpt/hppe/adpt_hppe_portctrl.c deleted file mode 100755 index 4102fbea1..000000000 --- a/feeds/ipq807x/qca-ssdk/src/src/adpt/hppe/adpt_hppe_portctrl.c +++ /dev/null @@ -1,5591 +0,0 @@ -/* - * Copyright (c) 2016-2020, The Linux Foundation. All rights reserved. - * Permission to use, copy, modify, and/or distribute this software for - * any purpose with or without fee is hereby granted, provided that the - * above copyright notice and this permission notice appear in all copies. - * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES - * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR - * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES - * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN - * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT - * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. - */ - - -/** - * @defgroup - * @{ - */ -#include "sw.h" -#include "hppe_portctrl_reg.h" -#include "hppe_portctrl.h" -#include "hppe_xgportctrl_reg.h" -#include "hppe_xgportctrl.h" -#include "hppe_uniphy_reg.h" -#include "hppe_uniphy.h" -#include "hppe_fdb_reg.h" -#include "hppe_fdb.h" -#include "hppe_global_reg.h" -#include "hppe_global.h" -#include "adpt.h" -#include "hsl.h" -#include "hsl_dev.h" -#include "hsl_port_prop.h" -#include "hsl_phy.h" -#include "hppe_init.h" -#include "ssdk_init.h" -#include "ssdk_dts.h" -#include "ssdk_clk.h" -#include "adpt_hppe.h" -#if defined(CPPE) -#include "adpt_cppe_portctrl.h" -#include "cppe_portctrl.h" -#endif -#include "sfp_phy.h" - -#define PORT4_PCS_SEL_GMII_FROM_PCS0 1 -#define PORT4_PCS_SEL_RGMII 0 - -#define PORT5_PCS_SEL_RGMII 0 -#define PORT5_PCS_SEL_GMII_FROM_PCS0 1 -#define PORT5_PCS_SEL_GMII_FROM_PCS1 2 -#define PORT5_GMAC_SEL_GMAC 1 -#define PORT5_GMAC_SEL_XGMAC 0 - -#define PORT6_PCS_SEL_RGMII 0 -#define PORT6_PCS_SEL_GMII_FROM_PCS2 1 -#define PORT6_GMAC_SEL_GMAC 1 -#define PORT6_GMAC_SEL_XGMAC 0 - -#define MAC_SPEED_10M 0 -#define MAC_SPEED_100M 1 -#define MAC_SPEED_1000M 2 -#define MAC_SPEED_10000M 3 - -#define XGMAC_USXGMII_ENABLE 1 -#define XGMAC_USXGMII_CLEAR 0 - -#define XGMAC_SPEED_SELECT_10000M 0 -#define XGMAC_SPEED_SELECT_5000M 1 -#define XGMAC_SPEED_SELECT_2500M 2 -#define XGMAC_SPEED_SELECT_1000M 3 -#define LPI_WAKEUP_TIMER 0x20 -#define LPI_SLEEP_TIMER 0x100 -#define PROMISCUOUS_MODE 0x1 -#define PASS_CONTROL_PACKET 0x2 -#define XGMAC_PAUSE_TIME 0xffff -#define CARRIER_SENSE_SIGNAL_FROM_MAC 0x0 - -#define PHY_PORT_TO_BM_PORT(port) (port + 7) -#define GMAC_IPG_CHECK 0xc -#define LPI_EEE_TIMER_FREQUENCY 300 /* 300MHZ*/ -#define LPI_EEE_TIMER_UNIT 256 - -/* This register is used to adjust the write timing for reserving - * some bandwidth of the memory to read operation. - */ -#define GMAC_TX_THD 0x1 - -static a_uint32_t port_interface_mode[SW_MAX_NR_DEV][SW_MAX_NR_PORT] = {0}; - -static a_bool_t -_adpt_hppe_port_phy_connected (a_uint32_t dev_id, fal_port_t port_id) -{ - a_uint32_t mode1, mode2; - a_bool_t force_port = 0; - - ADPT_DEV_ID_CHECK(dev_id); - - /* force port which connect s17c or other device chip*/ - force_port = ssdk_port_feature_get(dev_id, port_id, PHY_F_FORCE); - if (force_port == A_TRUE) { - SSDK_DEBUG("port_id %d is a force port!\n", port_id); - return A_FALSE; - } - - mode1 = ssdk_dt_global_get_mac_mode(dev_id, SSDK_UNIPHY_INSTANCE1); - mode2 = ssdk_dt_global_get_mac_mode(dev_id, SSDK_UNIPHY_INSTANCE2); - - if ((SSDK_PHYSICAL_PORT0 == port_id) || (SSDK_PHYSICAL_PORT7 == port_id)|| - ((SSDK_PHYSICAL_PORT5 == port_id) && ((mode1 == PORT_WRAPPER_10GBASE_R) || - mode1 == PORT_WRAPPER_SGMII_FIBER)) || - ((SSDK_PHYSICAL_PORT6 == port_id) && ((mode2 == PORT_WRAPPER_10GBASE_R) || - mode2 == PORT_WRAPPER_SGMII_FIBER))) - return A_FALSE; - else - return hppe_mac_port_valid_check (dev_id, port_id); -} - -static sw_error_t -_adpt_phy_status_get_from_ppe(a_uint32_t dev_id, a_uint32_t port_id, - struct port_phy_status *phy_status) -{ - sw_error_t rv = SW_OK; - a_uint32_t reg_field = 0; - - ADPT_DEV_ID_CHECK(dev_id); - - if (port_id == SSDK_PHYSICAL_PORT5) - { - - if (adpt_hppe_chip_revision_get(dev_id) - == HPPE_REVISION) - { - rv = hppe_port_phy_status_1_port5_1_phy_status_get(dev_id, - ®_field); - SW_RTN_ON_ERROR (rv); - } -#ifdef CPPE - else - { - rv = cppe_port5_pcs1_phy_status_get(dev_id, - ®_field); - SW_RTN_ON_ERROR (rv); - } -#endif - } - else - { - rv = hppe_port_phy_status_1_port6_phy_status_get(dev_id, - ®_field); - SW_RTN_ON_ERROR (rv); - } - - phy_status->tx_flowctrl = A_TRUE; - phy_status->rx_flowctrl = A_TRUE; - - if ((reg_field >> 7) & 0x1) - { - phy_status->link_status = PORT_LINK_UP; - switch (reg_field & 0x7) - { - case MAC_SPEED_10M: - phy_status->speed = FAL_SPEED_10; - break; - case MAC_SPEED_100M: - phy_status->speed = FAL_SPEED_100; - break; - case MAC_SPEED_1000M: - phy_status->speed = FAL_SPEED_1000; - break; - case MAC_SPEED_10000M: - phy_status->speed = FAL_SPEED_10000; - break; - default: - phy_status->speed = FAL_SPEED_BUTT; - break; - } - phy_status->duplex = FAL_FULL_DUPLEX; - } - else - { - phy_status->link_status = PORT_LINK_DOWN; - phy_status->speed = FAL_SPEED_BUTT; - phy_status->duplex = FAL_DUPLEX_BUTT; - } - - return rv; -} -#ifndef IN_PORTCONTROL_MINI -static sw_error_t -_adpt_hppe_port_xgmac_loopback_get(a_uint32_t dev_id, fal_port_t port_id, - a_bool_t * enable) -{ - sw_error_t rv = SW_OK; - - port_id = HPPE_TO_XGMAC_PORT_ID(port_id); - rv = hppe_mac_rx_configuration_lm_get(dev_id, port_id, (a_uint32_t*)enable); - - return rv; -} - -static sw_error_t -_adpt_hppe_port_gmac_loopback_get(a_uint32_t dev_id, fal_port_t port_id, - a_bool_t * enable) -{ - sw_error_t rv = SW_OK; - - port_id = HPPE_TO_GMAC_PORT_ID(port_id); - rv = hppe_mac_ctrl2_mac_loop_back_get(dev_id, port_id, (a_uint32_t*)enable); - - return rv; -} - -static sw_error_t -_adpt_hppe_port_xgmac_loopback_set(a_uint32_t dev_id, fal_port_t port_id, - a_bool_t enable) -{ - sw_error_t rv = SW_OK; - - port_id = HPPE_TO_XGMAC_PORT_ID(port_id); - rv = hppe_mac_rx_configuration_lm_set(dev_id, port_id, (a_uint32_t)enable); - - return rv; -} - -static sw_error_t -_adpt_hppe_port_gmac_loopback_set(a_uint32_t dev_id, fal_port_t port_id, - a_bool_t enable) -{ - sw_error_t rv = SW_OK; - - port_id = HPPE_TO_GMAC_PORT_ID(port_id); - rv = hppe_mac_ctrl2_mac_loop_back_set(dev_id, port_id, (a_uint32_t)enable); - - return rv; -} -#endif -static sw_error_t -_adpt_hppe_port_jumbo_size_set(a_uint32_t dev_id, fal_port_t port_id, - a_uint32_t jumbo_size) -{ - sw_error_t rv = SW_OK; - - port_id = HPPE_TO_GMAC_PORT_ID(port_id); - rv = hppe_mac_jumbo_size_mac_jumbo_size_set(dev_id, port_id, jumbo_size); - - return rv; -} - -static sw_error_t -_adpt_xgmac_port_max_frame_size_get(a_uint32_t dev_id, fal_port_t port_id, - a_uint32_t *max_frame) -{ - sw_error_t rv = SW_OK; - - port_id = HPPE_TO_XGMAC_PORT_ID(port_id); - rv = hppe_mac_rx_configuration_gpsl_get(dev_id,port_id, max_frame); - - return rv; -} - -static sw_error_t -_adpt_gmac_port_max_frame_size_get(a_uint32_t dev_id, fal_port_t port_id, - a_uint32_t *max_frame) -{ - sw_error_t rv = SW_OK; - - port_id = HPPE_TO_GMAC_PORT_ID(port_id); - rv = hppe_mac_jumbo_size_mac_jumbo_size_get(dev_id, port_id, max_frame); - - return rv; -} - -static sw_error_t -_adpt_xgmac_port_max_frame_size_set(a_uint32_t dev_id, fal_port_t port_id, - a_uint32_t max_frame) -{ - sw_error_t rv = SW_OK; - - port_id = HPPE_TO_XGMAC_PORT_ID(port_id); - rv |= hppe_mac_tx_configuration_jd_set(dev_id, port_id, (a_uint32_t)A_TRUE); - rv |= hppe_mac_rx_configuration_gpsl_set(dev_id, port_id, max_frame); - rv |= hppe_mac_rx_configuration_wd_set(dev_id, port_id, 1); - rv |= hppe_mac_rx_configuration_gmpslce_set(dev_id, port_id, 1); - rv |= hppe_mac_packet_filter_pr_set(dev_id, port_id, PROMISCUOUS_MODE); - rv |= hppe_mac_packet_filter_pcf_set(dev_id, port_id, PASS_CONTROL_PACKET); - - return rv; -} - -static sw_error_t -_adpt_gmac_port_max_frame_size_set(a_uint32_t dev_id, fal_port_t port_id, - a_uint32_t max_frame) -{ - sw_error_t rv = SW_OK; - - port_id = HPPE_TO_GMAC_PORT_ID(port_id); - rv |= hppe_mac_ctrl2_maxfr_set(dev_id, port_id, max_frame); - rv |= hppe_mac_ctrl2_crs_sel_set(dev_id, port_id, CARRIER_SENSE_SIGNAL_FROM_MAC); - rv |= hppe_mac_dbg_ctrl_hihg_ipg_set(dev_id, port_id, GMAC_IPG_CHECK); - rv |= hppe_mac_ctrl2_mac_tx_thd_set(dev_id, port_id, GMAC_TX_THD); - - return rv; -} -#ifndef IN_PORTCONTROL_MINI -static sw_error_t -_adpt_xgmac_port_rx_status_get(a_uint32_t dev_id, fal_port_t port_id, a_uint32_t* port_rxmac_status) -{ - sw_error_t rv = SW_OK; - union mac_rx_configuration_u xgmac_rx_enable; - - memset(&xgmac_rx_enable, 0, sizeof(xgmac_rx_enable)); - port_id = HPPE_TO_XGMAC_PORT_ID(port_id); - rv = hppe_mac_rx_configuration_get(dev_id, port_id, &xgmac_rx_enable); - if( rv != SW_OK ) - return rv; - *port_rxmac_status = xgmac_rx_enable.bf.re; - - return rv; -} -static sw_error_t -_adpt_gmac_port_rx_status_get(a_uint32_t dev_id, fal_port_t port_id, a_uint32_t* port_rxmac_status) -{ - sw_error_t rv = SW_OK; - union mac_enable_u gmac_rx_enable; - - memset(&gmac_rx_enable, 0, sizeof(gmac_rx_enable)); - port_id = HPPE_TO_GMAC_PORT_ID(port_id); - rv = hppe_mac_enable_get(dev_id, port_id, &gmac_rx_enable); - if( rv != SW_OK ) - return rv; - * port_rxmac_status = gmac_rx_enable.bf.rxmac_en; - - return rv; -} -#endif -static sw_error_t -_adpt_xgmac_port_rx_status_set(a_uint32_t dev_id, fal_port_t port_id, a_bool_t enable) -{ - sw_error_t rv = SW_OK; - union mac_rx_configuration_u xgmac_rx_enable; - - memset(&xgmac_rx_enable, 0, sizeof(xgmac_rx_enable)); - port_id = HPPE_TO_XGMAC_PORT_ID(port_id); - rv |= hppe_mac_rx_configuration_get(dev_id, port_id, &xgmac_rx_enable); - - xgmac_rx_enable.bf.acs = 1; - xgmac_rx_enable.bf.cst = 1; - if (A_TRUE == enable) - { - xgmac_rx_enable.bf.re = 1; - } - else { - xgmac_rx_enable.bf.re = 0; - } - rv |= hppe_mac_rx_configuration_set(dev_id, port_id, &xgmac_rx_enable); - - return rv; -} - -static sw_error_t -_adpt_gmac_port_rx_status_set(a_uint32_t dev_id, fal_port_t port_id, a_bool_t enable) -{ - sw_error_t rv = SW_OK; - union mac_enable_u gmac_rx_enable; - - memset(&gmac_rx_enable, 0, sizeof(gmac_rx_enable)); - port_id = HPPE_TO_GMAC_PORT_ID(port_id); - rv |= hppe_mac_enable_get(dev_id, port_id, &gmac_rx_enable); - if (A_TRUE == enable) - gmac_rx_enable.bf.rxmac_en = 1; - if (A_FALSE == enable) - gmac_rx_enable.bf.rxmac_en = 0; - rv |= hppe_mac_enable_set(dev_id, port_id, &gmac_rx_enable); - - return rv; -} -#ifndef IN_PORTCONTROL_MINI -static sw_error_t -_adpt_xgmac_port_tx_status_get(a_uint32_t dev_id, fal_port_t port_id, a_uint32_t *port_txmac_status) -{ - sw_error_t rv = SW_OK; - union mac_tx_configuration_u xgmac_tx_enable; - - memset(&xgmac_tx_enable, 0, sizeof(xgmac_tx_enable)); - port_id = HPPE_TO_XGMAC_PORT_ID(port_id); - rv = hppe_mac_tx_configuration_get(dev_id, port_id, &xgmac_tx_enable); - if( rv != SW_OK ) - return rv; - *port_txmac_status = xgmac_tx_enable.bf.te; - - return SW_OK; -} - -static sw_error_t -_adpt_gmac_port_tx_status_get(a_uint32_t dev_id, fal_port_t port_id, a_uint32_t *port_txmac_status) -{ - sw_error_t rv = SW_OK; - union mac_enable_u gmac_tx_enable; - - memset(&gmac_tx_enable, 0, sizeof(gmac_tx_enable)); - port_id = HPPE_TO_GMAC_PORT_ID(port_id); - rv = hppe_mac_enable_get(dev_id, port_id, &gmac_tx_enable); - if( rv != SW_OK ) - return rv; - *port_txmac_status = gmac_tx_enable.bf.txmac_en; - - return SW_OK; -} -#endif -static sw_error_t -_adpt_xgmac_port_tx_status_set (a_uint32_t dev_id, fal_port_t port_id, a_bool_t enable) -{ - sw_error_t rv = SW_OK; - union mac_tx_configuration_u xgmac_tx_enable; - - memset(&xgmac_tx_enable, 0, sizeof(xgmac_tx_enable)); - port_id = HPPE_TO_XGMAC_PORT_ID(port_id); - rv |=hppe_mac_tx_configuration_get(dev_id, port_id, &xgmac_tx_enable); - if (A_TRUE == enable) - xgmac_tx_enable.bf.te = 1; - if (A_FALSE == enable) - xgmac_tx_enable.bf.te = 0; - rv |= hppe_mac_tx_configuration_set(dev_id, port_id, &xgmac_tx_enable); - - return SW_OK; -} - -static sw_error_t -_adpt_gmac_port_tx_status_set (a_uint32_t dev_id, fal_port_t port_id, a_bool_t enable) -{ - sw_error_t rv = SW_OK; - union mac_enable_u gmac_tx_enable; - - memset(&gmac_tx_enable, 0, sizeof(gmac_tx_enable)); - port_id = HPPE_TO_GMAC_PORT_ID(port_id); - rv |= hppe_mac_enable_get(dev_id, port_id, &gmac_tx_enable); - if (A_TRUE == enable) - gmac_tx_enable.bf.txmac_en = 1; - if (A_FALSE == enable) - gmac_tx_enable.bf.txmac_en = 0; - rv |= hppe_mac_enable_set(dev_id, port_id, &gmac_tx_enable); - - return SW_OK; -} - -static sw_error_t -_adpt_xgmac_port_txfc_status_get(a_uint32_t dev_id, fal_port_t port_id, a_uint32_t* txfc_status) -{ - sw_error_t rv = SW_OK; - union mac_q0_tx_flow_ctrl_u xgmac_txfc_enable; - - memset(&xgmac_txfc_enable, 0, sizeof(xgmac_txfc_enable)); - port_id = HPPE_TO_XGMAC_PORT_ID(port_id); - rv = hppe_mac_q0_tx_flow_ctrl_get(dev_id, port_id, &xgmac_txfc_enable); - if( rv != SW_OK ) - return rv; - *txfc_status = xgmac_txfc_enable.bf.tfe; - - return SW_OK; -} - -static sw_error_t -_adpt_gmac_port_txfc_status_get(a_uint32_t dev_id, fal_port_t port_id, a_uint32_t* txfc_status) -{ - sw_error_t rv = SW_OK; - union mac_enable_u gmac_txfc_enable; - - memset(&gmac_txfc_enable, 0, sizeof(gmac_txfc_enable)); - port_id = HPPE_TO_GMAC_PORT_ID(port_id); - rv = hppe_mac_enable_get(dev_id, port_id, &gmac_txfc_enable); - if( rv != SW_OK ) - return rv; - *txfc_status = gmac_txfc_enable.bf.tx_flow_en; - - return SW_OK; -} - -static sw_error_t -_adpt_xgmac_port_txfc_status_set(a_uint32_t dev_id, fal_port_t port_id, a_bool_t enable) -{ - sw_error_t rv = SW_OK; - union mac_q0_tx_flow_ctrl_u xgmac_txfc_enable; - - memset(&xgmac_txfc_enable, 0, sizeof(xgmac_txfc_enable)); - port_id = HPPE_TO_XGMAC_PORT_ID(port_id); - rv |= hppe_mac_q0_tx_flow_ctrl_get(dev_id, port_id, &xgmac_txfc_enable); - if (A_TRUE == enable) - { - xgmac_txfc_enable.bf.tfe = 1; - xgmac_txfc_enable.bf.pt = XGMAC_PAUSE_TIME; - } - if (A_FALSE == enable) - xgmac_txfc_enable.bf.tfe = 0; - rv |= hppe_mac_q0_tx_flow_ctrl_set(dev_id, port_id, &xgmac_txfc_enable); - - return SW_OK; -} - -static sw_error_t -_adpt_gmac_port_txfc_status_set(a_uint32_t dev_id, fal_port_t port_id, a_bool_t enable) -{ - sw_error_t rv = SW_OK; - union mac_enable_u gmac_txfc_enable; - - memset(&gmac_txfc_enable, 0, sizeof(gmac_txfc_enable)); - port_id = HPPE_TO_GMAC_PORT_ID(port_id); - rv |= hppe_mac_enable_get(dev_id, port_id, &gmac_txfc_enable); - if (A_TRUE == enable) - gmac_txfc_enable.bf.tx_flow_en = 1; - if (A_FALSE == enable) - gmac_txfc_enable.bf.tx_flow_en = 0; - rv |= hppe_mac_enable_set(dev_id, port_id, &gmac_txfc_enable); - - return SW_OK; -} - -static sw_error_t -_adpt_xgmac_port_rxfc_status_get(a_uint32_t dev_id, fal_port_t port_id, a_uint32_t* rxfc_status) -{ - sw_error_t rv = SW_OK; - union mac_rx_flow_ctrl_u xgmac_rxfc_enable; - - memset(&xgmac_rxfc_enable, 0, sizeof(xgmac_rxfc_enable)); - port_id = HPPE_TO_XGMAC_PORT_ID(port_id); - rv = hppe_mac_rx_flow_ctrl_get(dev_id, port_id, &xgmac_rxfc_enable); - if(rv != SW_OK) - return rv; - *rxfc_status = xgmac_rxfc_enable.bf.rfe; - - return SW_OK; -} - -static sw_error_t -_adpt_gmac_port_rxfc_status_get(a_uint32_t dev_id, fal_port_t port_id, a_uint32_t* rxfc_status) -{ - sw_error_t rv = SW_OK; - union mac_enable_u gmac_rxfc_enable; - - memset(&gmac_rxfc_enable, 0, sizeof(gmac_rxfc_enable)); - port_id = HPPE_TO_GMAC_PORT_ID(port_id); - rv = hppe_mac_enable_get(dev_id, port_id, &gmac_rxfc_enable); - if( rv != SW_OK) - return rv; - *rxfc_status = gmac_rxfc_enable.bf.rx_flow_en; - - return SW_OK; -} - -static sw_error_t -_adpt_xgmac_port_rxfc_status_set(a_uint32_t dev_id,fal_port_t port_id, a_bool_t enable) -{ - sw_error_t rv = SW_OK; - union mac_rx_flow_ctrl_u xgmac_rxfc_enable; - - memset(&xgmac_rxfc_enable, 0, sizeof(xgmac_rxfc_enable)); - port_id = HPPE_TO_XGMAC_PORT_ID(port_id); - rv |= hppe_mac_rx_flow_ctrl_get(dev_id, port_id, &xgmac_rxfc_enable); - if (A_TRUE == enable) - xgmac_rxfc_enable.bf.rfe= 1; - if (A_FALSE == enable) - xgmac_rxfc_enable.bf.rfe = 0; - rv |= hppe_mac_rx_flow_ctrl_set(dev_id, port_id, &xgmac_rxfc_enable); - - return SW_OK; -} - -static sw_error_t -_adpt_gmac_port_rxfc_status_set(a_uint32_t dev_id,fal_port_t port_id, a_bool_t enable) -{ - sw_error_t rv = SW_OK; - union mac_enable_u gmac_rxfc_enable; - - memset(&gmac_rxfc_enable, 0, sizeof(gmac_rxfc_enable)); - port_id = HPPE_TO_GMAC_PORT_ID(port_id); - rv |= hppe_mac_enable_get(dev_id, port_id, &gmac_rxfc_enable); - if (A_TRUE == enable) - gmac_rxfc_enable.bf.rx_flow_en = 1; - if (A_FALSE == enable) - gmac_rxfc_enable.bf.rx_flow_en = 0; - rv |= hppe_mac_enable_set(dev_id, port_id, &gmac_rxfc_enable); - - return SW_OK; -} - -#ifndef IN_PORTCONTROL_MINI -sw_error_t -adpt_hppe_port_local_loopback_get(a_uint32_t dev_id, fal_port_t port_id, - a_bool_t * enable) -{ - - sw_error_t rv = 0; - a_uint32_t phy_id = 0; - hsl_phy_ops_t *phy_drv; - - ADPT_DEV_ID_CHECK(dev_id); - ADPT_NULL_POINT_CHECK(enable); - - if (A_TRUE != hsl_port_prop_check (dev_id, port_id, HSL_PP_PHY)) - { - return SW_BAD_PARAM; - } - if (A_FALSE == _adpt_hppe_port_phy_connected (dev_id, port_id)) - return SW_NOT_SUPPORTED; - - SW_RTN_ON_NULL (phy_drv = hsl_phy_api_ops_get (dev_id, port_id)); - if (NULL == phy_drv->phy_local_loopback_get) - return SW_NOT_SUPPORTED; - - rv = hsl_port_prop_get_phyid (dev_id, port_id, &phy_id); - SW_RTN_ON_ERROR (rv); - - rv = phy_drv->phy_local_loopback_get (dev_id, phy_id, enable); - - return rv; - -} -#endif -sw_error_t -adpt_hppe_port_autoneg_restart(a_uint32_t dev_id, fal_port_t port_id) -{ - - sw_error_t rv = 0; - a_uint32_t phy_id; - hsl_phy_ops_t *phy_drv; - - ADPT_DEV_ID_CHECK(dev_id); - - if (A_TRUE != hsl_port_prop_check (dev_id, port_id, HSL_PP_PHY)) - { - return SW_BAD_PARAM; - } - if (A_FALSE == _adpt_hppe_port_phy_connected (dev_id, port_id)) - return SW_NOT_SUPPORTED; - - SW_RTN_ON_NULL (phy_drv = hsl_phy_api_ops_get (dev_id, port_id)); - if (NULL == phy_drv->phy_restart_autoneg) - return SW_NOT_SUPPORTED; - - rv = hsl_port_prop_get_phyid (dev_id, port_id, &phy_id); - SW_RTN_ON_ERROR (rv); - - rv = phy_drv->phy_restart_autoneg (dev_id, phy_id); - return rv; - -} -sw_error_t -adpt_hppe_port_duplex_set(a_uint32_t dev_id, fal_port_t port_id, - fal_port_duplex_t duplex) -{ - union mac_enable_u mac_enable; - sw_error_t rv = 0; - a_uint32_t phy_id = 0; - hsl_phy_ops_t *phy_drv; - - memset(&mac_enable, 0, sizeof(mac_enable)); - ADPT_DEV_ID_CHECK(dev_id); - - if (A_TRUE != hsl_port_prop_check (dev_id, port_id, HSL_PP_INCL_CPU)) - { - return SW_BAD_PARAM; - } - if (A_FALSE == _adpt_hppe_port_phy_connected (dev_id, port_id)) - return SW_NOT_SUPPORTED; - - SW_RTN_ON_NULL (phy_drv = hsl_phy_api_ops_get (dev_id, port_id)); - if (NULL == phy_drv->phy_duplex_set) - return SW_NOT_SUPPORTED; - - if (FAL_DUPLEX_BUTT <= duplex) - { - return SW_BAD_PARAM; - } - rv = hsl_port_prop_get_phyid (dev_id, port_id, &phy_id); - SW_RTN_ON_ERROR (rv); - - rv = phy_drv->phy_duplex_set (dev_id, phy_id, duplex); - SW_RTN_ON_ERROR (rv); - -#if 0 - port_id = port_id - 1; - hppe_mac_enable_get(dev_id, port_id, &mac_enable); - - if (FAL_HALF_DUPLEX == duplex) - mac_enable.bf.duplex = 0; - if (FAL_FULL_DUPLEX == duplex) - mac_enable.bf.duplex = 1; - - hppe_mac_enable_set(dev_id, port_id, &mac_enable); - -#endif - - return rv; -} -#ifndef IN_PORTCONTROL_MINI -sw_error_t -adpt_hppe_port_rxmac_status_get(a_uint32_t dev_id, fal_port_t port_id, - a_bool_t * enable) -{ - sw_error_t rv = SW_OK; - a_uint32_t port_rxmac_status = 0, port_mac_type; - - ADPT_DEV_ID_CHECK(dev_id); - ADPT_NULL_POINT_CHECK(enable); - - port_mac_type = qca_hppe_port_mac_type_get(dev_id, port_id); - if (port_mac_type == PORT_XGMAC_TYPE) - _adpt_xgmac_port_rx_status_get( dev_id, port_id, &port_rxmac_status); - else if (port_mac_type == PORT_GMAC_TYPE) - _adpt_gmac_port_rx_status_get( dev_id, port_id, &port_rxmac_status); - else - return SW_BAD_VALUE; - - if (port_rxmac_status) - *enable = A_TRUE; - else - *enable = A_FALSE; - - return rv; -} - -sw_error_t -adpt_hppe_port_cdt(a_uint32_t dev_id, fal_port_t port_id, - a_uint32_t mdi_pair, fal_cable_status_t * cable_status, - a_uint32_t * cable_len) -{ - - sw_error_t rv = 0; - a_uint32_t phy_id = 0; - hsl_phy_ops_t *phy_drv; - - ADPT_DEV_ID_CHECK(dev_id); - ADPT_NULL_POINT_CHECK(cable_status); - ADPT_NULL_POINT_CHECK(cable_len); - - if (A_TRUE != hsl_port_prop_check (dev_id, port_id, HSL_PP_PHY)) - { - return SW_BAD_PARAM; - } - if (A_FALSE == _adpt_hppe_port_phy_connected (dev_id, port_id)) - return SW_NOT_SUPPORTED; - - SW_RTN_ON_NULL (phy_drv = hsl_phy_api_ops_get (dev_id, port_id)); - if (NULL == phy_drv->phy_cdt) - return SW_NOT_SUPPORTED; - - rv = hsl_port_prop_get_phyid (dev_id, port_id, &phy_id); - SW_RTN_ON_ERROR (rv); - - rv = phy_drv->phy_cdt (dev_id, phy_id, mdi_pair, cable_status, cable_len); - - return rv; - -} -#endif -sw_error_t -adpt_hppe_port_txmac_status_set(a_uint32_t dev_id, fal_port_t port_id, - a_bool_t enable) -{ - a_uint32_t port_mac_type; - - ADPT_DEV_ID_CHECK(dev_id); - - port_mac_type =qca_hppe_port_mac_type_get(dev_id, port_id); - if (port_mac_type == PORT_XGMAC_TYPE) - _adpt_xgmac_port_tx_status_set( dev_id, port_id, enable); - else if (port_mac_type == PORT_GMAC_TYPE) - _adpt_gmac_port_tx_status_set( dev_id, port_id, enable); - else - return SW_BAD_VALUE; - - return SW_OK; -} -#ifndef IN_PORTCONTROL_MINI -sw_error_t -adpt_hppe_port_combo_fiber_mode_set(a_uint32_t dev_id, - a_uint32_t port_id, - fal_port_fiber_mode_t mode) -{ - - sw_error_t rv = 0; - a_uint32_t phy_id = 0; - hsl_phy_ops_t *phy_drv; - - ADPT_DEV_ID_CHECK(dev_id); - - if (A_TRUE != hsl_port_prop_check (dev_id, port_id, HSL_PP_PHY)) - { - return SW_BAD_PARAM; - } - if (A_FALSE == _adpt_hppe_port_phy_connected (dev_id, port_id)) - return SW_NOT_SUPPORTED; - - SW_RTN_ON_NULL (phy_drv = hsl_phy_api_ops_get (dev_id, port_id)); - if (NULL == phy_drv->phy_combo_fiber_mode_set) - return SW_NOT_SUPPORTED; - - rv = hsl_port_prop_get_phyid (dev_id, port_id, &phy_id); - SW_RTN_ON_ERROR (rv); - - rv = phy_drv->phy_combo_fiber_mode_set (dev_id, phy_id, mode); - - return rv; - -} -sw_error_t -adpt_hppe_port_combo_medium_status_get(a_uint32_t dev_id, - a_uint32_t port_id, - fal_port_medium_t * - medium) -{ - - sw_error_t rv = 0; - a_uint32_t phy_id = 0; - hsl_phy_ops_t *phy_drv; - - ADPT_DEV_ID_CHECK(dev_id); - ADPT_NULL_POINT_CHECK(medium); - - if (A_TRUE != hsl_port_prop_check (dev_id, port_id, HSL_PP_PHY)) - { - return SW_BAD_PARAM; - } - if (A_FALSE == _adpt_hppe_port_phy_connected (dev_id, port_id)) - return SW_NOT_SUPPORTED; - - SW_RTN_ON_NULL (phy_drv = hsl_phy_api_ops_get (dev_id, port_id)); - if (NULL == phy_drv->phy_combo_medium_status_get) - return SW_NOT_SUPPORTED; - - rv = hsl_port_prop_get_phyid (dev_id, port_id, &phy_id); - SW_RTN_ON_ERROR (rv); - - rv = phy_drv->phy_combo_medium_status_get (dev_id, phy_id, medium); - - return rv; - -} - -sw_error_t -adpt_hppe_port_magic_frame_mac_set(a_uint32_t dev_id, fal_port_t port_id, - fal_mac_addr_t * mac) -{ - sw_error_t rv; - a_uint32_t phy_id = 0; - hsl_phy_ops_t *phy_drv; - - ADPT_DEV_ID_CHECK(dev_id); - ADPT_NULL_POINT_CHECK(mac); - - if (A_TRUE != hsl_port_prop_check (dev_id, port_id, HSL_PP_PHY)) - { - return SW_BAD_PARAM; - } - if (A_FALSE == _adpt_hppe_port_phy_connected (dev_id, port_id)) - return SW_NOT_SUPPORTED; - - SW_RTN_ON_NULL (phy_drv = hsl_phy_api_ops_get (dev_id, port_id)); - if (NULL == phy_drv->phy_magic_frame_mac_set) - return SW_NOT_SUPPORTED; - - rv = hsl_port_prop_get_phyid (dev_id, port_id, &phy_id); - SW_RTN_ON_ERROR (rv); - - rv = phy_drv->phy_magic_frame_mac_set (dev_id, phy_id,mac); - - return rv; - -} -sw_error_t -adpt_hppe_port_powersave_set(a_uint32_t dev_id, fal_port_t port_id, - a_bool_t enable) -{ - sw_error_t rv = 0; - a_uint32_t phy_id = 0; - hsl_phy_ops_t *phy_drv; - - ADPT_DEV_ID_CHECK(dev_id); - - if (A_TRUE != hsl_port_prop_check (dev_id, port_id, HSL_PP_PHY)) - { - return SW_BAD_PARAM; - } - if (A_FALSE == _adpt_hppe_port_phy_connected (dev_id, port_id)) - return SW_NOT_SUPPORTED; - - SW_RTN_ON_NULL (phy_drv = hsl_phy_api_ops_get (dev_id, port_id)); - if (NULL == phy_drv->phy_powersave_set) - return SW_NOT_SUPPORTED; - - rv = hsl_port_prop_get_phyid (dev_id, port_id, &phy_id); - SW_RTN_ON_ERROR (rv); - - rv = phy_drv->phy_powersave_set (dev_id, phy_id, enable); - - return rv; - -} -sw_error_t -adpt_hppe_port_hibernate_set(a_uint32_t dev_id, fal_port_t port_id, - a_bool_t enable) -{ - - sw_error_t rv = 0; - a_uint32_t phy_id = 0; - hsl_phy_ops_t *phy_drv; - - ADPT_DEV_ID_CHECK(dev_id); - - if (A_TRUE != hsl_port_prop_check (dev_id, port_id, HSL_PP_PHY)) - { - return SW_BAD_PARAM; - } - if (A_FALSE == _adpt_hppe_port_phy_connected (dev_id, port_id)) - return SW_NOT_SUPPORTED; - - SW_RTN_ON_NULL (phy_drv = hsl_phy_api_ops_get (dev_id, port_id)); - if (NULL == phy_drv->phy_hibernation_set) - return SW_NOT_SUPPORTED; - - rv = hsl_port_prop_get_phyid (dev_id, port_id, &phy_id); - SW_RTN_ON_ERROR (rv); - - rv = phy_drv->phy_hibernation_set (dev_id, phy_id, enable); - - return rv; - -} - -sw_error_t -adpt_hppe_port_mru_set(a_uint32_t dev_id, fal_port_t port_id, - fal_mru_ctrl_t *ctrl) -{ - ADPT_DEV_ID_CHECK(dev_id); - ADPT_NULL_POINT_CHECK(ctrl); - - hppe_mru_mtu_ctrl_tbl_mru_set(dev_id, port_id, ctrl->mru_size); - hppe_mru_mtu_ctrl_tbl_mru_cmd_set(dev_id, port_id, (a_uint32_t)ctrl->action); - - return SW_OK; -} - -sw_error_t -adpt_ppe_port_mru_set(a_uint32_t dev_id, fal_port_t port_id, - fal_mru_ctrl_t *ctrl) -{ - a_uint32_t chip_ver = 0; - - ADPT_DEV_ID_CHECK(dev_id); - ADPT_NULL_POINT_CHECK(ctrl); - - chip_ver = adpt_hppe_chip_revision_get(dev_id); - if (chip_ver == CPPE_REVISION) { -#if defined(CPPE) - return adpt_cppe_port_mru_set(dev_id, port_id, ctrl); -#endif - } else { - return adpt_hppe_port_mru_set(dev_id, port_id, ctrl); - } - - return SW_NOT_SUPPORTED; -} - -sw_error_t -adpt_hppe_port_mtu_set(a_uint32_t dev_id, fal_port_t port_id, - fal_mtu_ctrl_t *ctrl) -{ - union mru_mtu_ctrl_tbl_u mru_mtu_ctrl_tbl; - - memset(&mru_mtu_ctrl_tbl, 0, sizeof(mru_mtu_ctrl_tbl)); - ADPT_DEV_ID_CHECK(dev_id); - ADPT_NULL_POINT_CHECK(ctrl); - - hppe_mru_mtu_ctrl_tbl_get(dev_id, port_id, &mru_mtu_ctrl_tbl); - mru_mtu_ctrl_tbl.bf.mtu = ctrl->mtu_size; - mru_mtu_ctrl_tbl.bf.mtu_cmd = (a_uint32_t)ctrl->action; - hppe_mru_mtu_ctrl_tbl_set(dev_id, port_id, &mru_mtu_ctrl_tbl); - - if ((port_id >= SSDK_PHYSICAL_PORT0) && (port_id <= SSDK_PHYSICAL_PORT7)) - { - hppe_mc_mtu_ctrl_tbl_mtu_set(dev_id, port_id, ctrl->mtu_size); - hppe_mc_mtu_ctrl_tbl_mtu_cmd_set(dev_id, port_id, (a_uint32_t)ctrl->action); - } - - return SW_OK; -} - -sw_error_t -adpt_ppe_port_mtu_set(a_uint32_t dev_id, fal_port_t port_id, - fal_mtu_ctrl_t *ctrl) -{ - a_uint32_t chip_ver = 0; - - ADPT_DEV_ID_CHECK(dev_id); - ADPT_NULL_POINT_CHECK(ctrl); - - chip_ver = adpt_hppe_chip_revision_get(dev_id); - if (chip_ver == CPPE_REVISION) { -#if defined(CPPE) - return adpt_cppe_port_mtu_set(dev_id, port_id, ctrl); -#endif - } else { - return adpt_hppe_port_mtu_set(dev_id, port_id, ctrl); - } - - return SW_NOT_SUPPORTED; -} -#endif - -sw_error_t -adpt_hppe_port_max_frame_size_set(a_uint32_t dev_id, fal_port_t port_id, - a_uint32_t max_frame) -{ - a_uint32_t port_mac_type = 0; - sw_error_t rv = SW_OK; - - ADPT_DEV_ID_CHECK(dev_id); - - if (max_frame > SSDK_MAX_FRAME_SIZE) { - return SW_BAD_VALUE; - } - - port_mac_type =qca_hppe_port_mac_type_get(dev_id, port_id); - if (port_mac_type == PORT_XGMAC_TYPE) - rv |= _adpt_xgmac_port_max_frame_size_set( dev_id, port_id, max_frame); - else if (port_mac_type == PORT_GMAC_TYPE) - { - /*for gmac, rxtoolong have counters when package length is longer than jumbo size and shorter than max frame size, - when package length is longer than max frame size, the rxbadbyte have counters.*/ - rv |= _adpt_hppe_port_jumbo_size_set(dev_id, port_id, max_frame); - rv |= _adpt_gmac_port_max_frame_size_set( dev_id, port_id, max_frame); - } - else - return SW_BAD_VALUE; - - return rv; -} - -sw_error_t -adpt_ppe_port_max_frame_size_set(a_uint32_t dev_id, fal_port_t port_id, - a_uint32_t max_frame) -{ -#ifdef CPPE - if (adpt_hppe_chip_revision_get(dev_id) == CPPE_REVISION && - port_id == SSDK_PHYSICAL_PORT6) - { - return adpt_cppe_lpbk_max_frame_size_set(dev_id, port_id, max_frame); - } -#endif - return adpt_hppe_port_max_frame_size_set(dev_id, port_id, max_frame); -} - -#ifndef IN_PORTCONTROL_MINI -sw_error_t -adpt_hppe_port_8023az_get(a_uint32_t dev_id, fal_port_t port_id, - a_bool_t * enable) -{ - - sw_error_t rv = 0; - a_uint32_t phy_id = 0; - hsl_phy_ops_t *phy_drv; - - ADPT_DEV_ID_CHECK(dev_id); - ADPT_NULL_POINT_CHECK(enable); - - if (A_TRUE != hsl_port_prop_check (dev_id, port_id, HSL_PP_PHY)) - { - return SW_BAD_PARAM; - } - if (A_FALSE == _adpt_hppe_port_phy_connected (dev_id, port_id)) - return SW_NOT_SUPPORTED; - - SW_RTN_ON_NULL (phy_drv = hsl_phy_api_ops_get (dev_id, port_id)); - if (NULL == phy_drv->phy_8023az_get) - return SW_NOT_SUPPORTED; - - rv = hsl_port_prop_get_phyid (dev_id, port_id, &phy_id); - SW_RTN_ON_ERROR (rv); - - rv = phy_drv->phy_8023az_get (dev_id, phy_id, enable); - - return rv; - -} -#endif -sw_error_t -adpt_hppe_port_rxfc_status_get(a_uint32_t dev_id, fal_port_t port_id, - a_bool_t * enable) -{ - sw_error_t rv = SW_OK; - a_uint32_t rxfc_status = 0, port_mac_type; - - ADPT_DEV_ID_CHECK(dev_id); - ADPT_NULL_POINT_CHECK(enable); - - port_mac_type =qca_hppe_port_mac_type_get(dev_id, port_id); - if (port_mac_type == PORT_XGMAC_TYPE) - _adpt_xgmac_port_rxfc_status_get( dev_id, port_id, &rxfc_status); - else if (port_mac_type == PORT_GMAC_TYPE) - _adpt_gmac_port_rxfc_status_get( dev_id, port_id, &rxfc_status); - else - return SW_BAD_VALUE; - - if (rxfc_status) - *enable = A_TRUE; - else - *enable = A_FALSE; - - return rv; -} - -sw_error_t -adpt_hppe_port_txfc_status_get(a_uint32_t dev_id, fal_port_t port_id, - a_bool_t * enable) -{ - a_uint32_t txfc_status = 0, port_mac_type; - - ADPT_DEV_ID_CHECK(dev_id); - ADPT_NULL_POINT_CHECK(enable); - - port_mac_type =qca_hppe_port_mac_type_get(dev_id, port_id); - if (port_mac_type == PORT_XGMAC_TYPE) - _adpt_xgmac_port_txfc_status_get( dev_id, port_id, &txfc_status); - else if (port_mac_type == PORT_GMAC_TYPE) - _adpt_gmac_port_txfc_status_get( dev_id, port_id, &txfc_status); - else - return SW_BAD_VALUE; - - if (txfc_status) - *enable = A_TRUE; - else - *enable = A_FALSE; - - return SW_OK; -} -#ifndef IN_PORTCONTROL_MINI -sw_error_t -adpt_hppe_port_remote_loopback_set(a_uint32_t dev_id, fal_port_t port_id, - a_bool_t enable) -{ - - sw_error_t rv = 0; - a_uint32_t phy_id = 0; - hsl_phy_ops_t *phy_drv; - - ADPT_DEV_ID_CHECK(dev_id); - - if (A_TRUE != hsl_port_prop_check (dev_id, port_id, HSL_PP_PHY)) - { - return SW_BAD_PARAM; - } - if (A_FALSE == _adpt_hppe_port_phy_connected (dev_id, port_id)) - return SW_NOT_SUPPORTED; - - SW_RTN_ON_NULL (phy_drv = hsl_phy_api_ops_get (dev_id, port_id)); - if (NULL == phy_drv->phy_remote_loopback_set) - return SW_NOT_SUPPORTED; - - rv = hsl_port_prop_get_phyid (dev_id, port_id, &phy_id); - SW_RTN_ON_ERROR (rv); - - rv = phy_drv->phy_remote_loopback_set (dev_id, phy_id, enable); - - return rv; - -} -#endif -sw_error_t -adpt_hppe_port_autoneg_status_get(a_uint32_t dev_id, fal_port_t port_id, - a_bool_t * status) -{ - - a_uint32_t phy_id = 0; - sw_error_t rv = 0; - hsl_phy_ops_t *phy_drv; - - ADPT_DEV_ID_CHECK(dev_id); - ADPT_NULL_POINT_CHECK(status); - - if (A_TRUE != hsl_port_prop_check (dev_id, port_id, HSL_PP_PHY)) - { - return SW_BAD_PARAM; - } - if (A_FALSE == _adpt_hppe_port_phy_connected (dev_id, port_id)) - return SW_NOT_SUPPORTED; - - SW_RTN_ON_NULL (phy_drv = hsl_phy_api_ops_get (dev_id, port_id)); - if (NULL == phy_drv->phy_autoneg_status_get) - return SW_NOT_SUPPORTED; - - rv = hsl_port_prop_get_phyid (dev_id, port_id, &phy_id); - SW_RTN_ON_ERROR (rv); - - *status = phy_drv->phy_autoneg_status_get (dev_id, phy_id); - - return SW_OK; - -} -#ifndef IN_PORTCONTROL_MINI -sw_error_t -adpt_hppe_port_txmac_status_get(a_uint32_t dev_id, fal_port_t port_id, - a_bool_t * enable) -{ - sw_error_t rv = SW_OK; - a_uint32_t port_txmac_status = 0, port_mac_type; - - ADPT_DEV_ID_CHECK(dev_id); - ADPT_NULL_POINT_CHECK(enable); - - port_mac_type =qca_hppe_port_mac_type_get(dev_id, port_id); - if (port_mac_type == PORT_XGMAC_TYPE) - _adpt_xgmac_port_tx_status_get( dev_id, port_id, &port_txmac_status); - else if (port_mac_type == PORT_GMAC_TYPE) - _adpt_gmac_port_tx_status_get( dev_id, port_id, &port_txmac_status); - else - return SW_BAD_VALUE; - - if (port_txmac_status) - *enable = A_TRUE; - else - *enable = A_FALSE; - - return rv; -} - -sw_error_t -adpt_hppe_port_mdix_get(a_uint32_t dev_id, fal_port_t port_id, - fal_port_mdix_mode_t * mode) -{ - - sw_error_t rv = 0; - a_uint32_t phy_id = 0; - hsl_phy_ops_t *phy_drv; - - ADPT_DEV_ID_CHECK(dev_id); - ADPT_NULL_POINT_CHECK(mode); - - if (A_TRUE != hsl_port_prop_check (dev_id, port_id, HSL_PP_PHY)) - { - return SW_BAD_PARAM; - } - if (A_FALSE == _adpt_hppe_port_phy_connected (dev_id, port_id)) - return SW_NOT_SUPPORTED; - - SW_RTN_ON_NULL (phy_drv = hsl_phy_api_ops_get (dev_id, port_id)); - if (NULL == phy_drv->phy_mdix_get) - return SW_NOT_SUPPORTED; - - rv = hsl_port_prop_get_phyid (dev_id, port_id, &phy_id); - SW_RTN_ON_ERROR (rv); - - rv = phy_drv->phy_mdix_get (dev_id, phy_id, mode); - - return rv; - -} - -sw_error_t -adpt_hppe_ports_link_status_get(a_uint32_t dev_id, a_uint32_t * status) -{ - - sw_error_t rv = 0; - a_uint32_t port_id; - a_uint32_t phy_id; - hsl_dev_t *pdev = NULL; - hsl_phy_ops_t *phy_drv; - struct port_phy_status phy_status = {0}; - - ADPT_DEV_ID_CHECK(dev_id); - ADPT_NULL_POINT_CHECK(status); - - pdev = hsl_dev_ptr_get(dev_id); - if (pdev == NULL) - return SW_NOT_INITIALIZED; - - *status = 0x0; - for (port_id = 0; port_id < SW_MAX_NR_PORT; port_id++) - { - /* for those ports without PHY device should be sfp port */ - if (A_FALSE == _adpt_hppe_port_phy_connected(dev_id, port_id)) - { - if (hsl_port_prop_check(dev_id, port_id, HSL_PP_CPU) || - hsl_port_prop_check(dev_id, port_id, HSL_PP_INNER)) - { - *status |= (0x1 << port_id); - } - else - { - if(!hsl_port_prop_check(dev_id, port_id, HSL_PP_PHY)) - { - continue; - } - rv = _adpt_phy_status_get_from_ppe(dev_id, - port_id, &phy_status); - SW_RTN_ON_ERROR (rv); - - if (phy_status.link_status == PORT_LINK_UP) - { - *status |= (0x1 << port_id); - } - else - { - *status &= ~(0x1 << port_id); - } - } - } - else - { - SW_RTN_ON_NULL (phy_drv = hsl_phy_api_ops_get (dev_id, port_id)); - if (NULL == phy_drv->phy_link_status_get) - { - return SW_NOT_SUPPORTED; - } - rv = hsl_port_prop_get_phyid(dev_id, port_id, &phy_id); - SW_RTN_ON_ERROR(rv); - - if (A_TRUE == phy_drv->phy_link_status_get (dev_id, phy_id)) - { - *status |= (0x1 << port_id); - } - else - { - *status &= ~(0x1 << port_id); - } - } - } - return SW_OK; - -} - -sw_error_t -adpt_hppe_port_mac_loopback_set(a_uint32_t dev_id, fal_port_t port_id, - a_bool_t enable) -{ - sw_error_t rv = SW_OK; - a_uint32_t port_mac_type = 0; - - ADPT_DEV_ID_CHECK(dev_id); - port_mac_type = qca_hppe_port_mac_type_get(dev_id, port_id); - if (port_mac_type == PORT_XGMAC_TYPE) - rv = _adpt_hppe_port_xgmac_loopback_set( dev_id, port_id, enable); - else if(port_mac_type == PORT_GMAC_TYPE) - rv = _adpt_hppe_port_gmac_loopback_set( dev_id, port_id, enable); - else - return SW_BAD_VALUE; - - return rv; -} - -sw_error_t -adpt_hppe_port_phy_id_get(a_uint32_t dev_id, fal_port_t port_id, - a_uint16_t * org_id, a_uint16_t * rev_id) -{ - sw_error_t rv = 0; - a_uint32_t phy_id = 0; - hsl_phy_ops_t *phy_drv; - a_uint32_t phy_data; - - ADPT_DEV_ID_CHECK(dev_id); - ADPT_NULL_POINT_CHECK(org_id); - ADPT_NULL_POINT_CHECK(rev_id); - - if (A_TRUE != hsl_port_prop_check (dev_id, port_id, HSL_PP_PHY)) - { - return SW_BAD_PARAM; - } - if (A_FALSE == _adpt_hppe_port_phy_connected (dev_id, port_id)) - return SW_NOT_SUPPORTED; - - SW_RTN_ON_NULL (phy_drv = hsl_phy_api_ops_get (dev_id, port_id)); - if (NULL == phy_drv->phy_id_get) - return SW_NOT_SUPPORTED; - - rv = hsl_port_prop_get_phyid (dev_id, port_id, &phy_id); - SW_RTN_ON_ERROR (rv); - - rv = phy_drv->phy_id_get (dev_id, phy_id, &phy_data); - SW_RTN_ON_ERROR (rv); - - *org_id = (phy_data >> 16) & 0xffff; - *rev_id = phy_data & 0xffff; - - return rv; - -} -sw_error_t -adpt_hppe_port_mru_get(a_uint32_t dev_id, fal_port_t port_id, - fal_mru_ctrl_t *ctrl) -{ - sw_error_t rv = SW_OK; - union mru_mtu_ctrl_tbl_u mru_mtu_ctrl_tbl; - - memset(&mru_mtu_ctrl_tbl, 0, sizeof(mru_mtu_ctrl_tbl)); - ADPT_DEV_ID_CHECK(dev_id); - ADPT_NULL_POINT_CHECK(ctrl); - - rv = hppe_mru_mtu_ctrl_tbl_get(dev_id, port_id, &mru_mtu_ctrl_tbl); - - if( rv != SW_OK ) - return rv; - - ctrl->mru_size = mru_mtu_ctrl_tbl.bf.mru; - ctrl->action = (fal_fwd_cmd_t)mru_mtu_ctrl_tbl.bf.mru_cmd; - - return SW_OK; -} - -sw_error_t -adpt_ppe_port_mru_get(a_uint32_t dev_id, fal_port_t port_id, - fal_mru_ctrl_t *ctrl) -{ - a_uint32_t chip_ver = 0; - - ADPT_DEV_ID_CHECK(dev_id); - ADPT_NULL_POINT_CHECK(ctrl); - - chip_ver = adpt_hppe_chip_revision_get(dev_id); - if (chip_ver == CPPE_REVISION) { -#if defined(CPPE) - return adpt_cppe_port_mru_get(dev_id, port_id, ctrl); -#endif - } else { - return adpt_hppe_port_mru_get(dev_id, port_id, ctrl); - } - - return SW_NOT_SUPPORTED; -} -#endif - -sw_error_t -adpt_hppe_port_power_on(a_uint32_t dev_id, fal_port_t port_id) -{ - - sw_error_t rv = 0; - a_uint32_t phy_id = 0; - hsl_phy_ops_t *phy_drv; - - ADPT_DEV_ID_CHECK(dev_id); - - if (A_TRUE != hsl_port_prop_check (dev_id, port_id, HSL_PP_PHY)) - { - return SW_BAD_PARAM; - } - if (A_FALSE == _adpt_hppe_port_phy_connected (dev_id, port_id)) - return SW_NOT_SUPPORTED; - - SW_RTN_ON_NULL (phy_drv = hsl_phy_api_ops_get (dev_id, port_id)); - if (NULL == phy_drv->phy_power_on) - return SW_NOT_SUPPORTED; - - rv = hsl_port_prop_get_phyid (dev_id, port_id, &phy_id); - SW_RTN_ON_ERROR (rv); - - rv = phy_drv->phy_power_on(dev_id, phy_id); - - return rv; - -} -sw_error_t -adpt_hppe_port_speed_set(a_uint32_t dev_id, fal_port_t port_id, - fal_port_speed_t speed) -{ - sw_error_t rv = 0; - a_uint32_t phy_id = 0; - hsl_phy_ops_t *phy_drv; - - ADPT_DEV_ID_CHECK(dev_id); - - if (A_TRUE != hsl_port_prop_check (dev_id, port_id, HSL_PP_INCL_CPU)) - { - return SW_BAD_PARAM; - } - if (A_FALSE == _adpt_hppe_port_phy_connected (dev_id, port_id)) - return SW_NOT_SUPPORTED; - - SW_RTN_ON_NULL (phy_drv = hsl_phy_api_ops_get (dev_id, port_id)); - if (NULL == phy_drv->phy_speed_set) - return SW_NOT_SUPPORTED; - - rv = hsl_port_prop_get_phyid (dev_id, port_id, &phy_id); - SW_RTN_ON_ERROR (rv); - - rv = phy_drv->phy_speed_set (dev_id, phy_id, speed); - SW_RTN_ON_ERROR (rv); - - return rv; -} -sw_error_t -adpt_hppe_port_interface_mode_get(a_uint32_t dev_id, fal_port_t port_id, - fal_port_interface_mode_t * mode) -{ - sw_error_t rv = 0; - if (A_TRUE != hsl_port_prop_check (dev_id, port_id, HSL_PP_EXCL_CPU)) - { - return SW_BAD_PARAM; - } - *mode = port_interface_mode[dev_id][port_id]; - - return rv; -} - -sw_error_t -adpt_hppe_port_duplex_get(a_uint32_t dev_id, fal_port_t port_id, - fal_port_duplex_t * pduplex) -{ - sw_error_t rv = 0; - a_uint32_t phy_id = 0; - hsl_phy_ops_t *phy_drv; - struct port_phy_status phy_status = {0}; - - ADPT_DEV_ID_CHECK(dev_id); - ADPT_NULL_POINT_CHECK(pduplex); - - if (port_id == SSDK_PHYSICAL_PORT0 || port_id == SSDK_PHYSICAL_PORT7) - { - *pduplex = FAL_FULL_DUPLEX; - return SW_OK; - } - - if (A_TRUE != hsl_port_prop_check (dev_id, port_id, HSL_PP_INCL_CPU)) - { - return SW_BAD_PARAM; - } - - /* for those ports without PHY device should be sfp port */ - if (A_FALSE == _adpt_hppe_port_phy_connected (dev_id, port_id)) - { - - rv = _adpt_phy_status_get_from_ppe(dev_id, - port_id, &phy_status); - SW_RTN_ON_ERROR (rv); - *pduplex = phy_status.duplex; - - } - else - { - SW_RTN_ON_NULL (phy_drv = hsl_phy_api_ops_get (dev_id, port_id)); - if (NULL == phy_drv->phy_duplex_get) - return SW_NOT_SUPPORTED; - - rv = hsl_port_prop_get_phyid (dev_id, port_id, &phy_id); - SW_RTN_ON_ERROR (rv); - rv = phy_drv->phy_duplex_get (dev_id, phy_id, pduplex); - SW_RTN_ON_ERROR (rv); - } - - return rv; -} - -sw_error_t -adpt_hppe_port_autoneg_adv_get(a_uint32_t dev_id, fal_port_t port_id, - a_uint32_t * autoadv) -{ - - sw_error_t rv = 0; - a_uint32_t phy_id; - hsl_phy_ops_t *phy_drv; - - ADPT_DEV_ID_CHECK(dev_id); - ADPT_NULL_POINT_CHECK(autoadv); - - if (A_TRUE != hsl_port_prop_check (dev_id, port_id, HSL_PP_PHY)) - { - return SW_BAD_PARAM; - } - if (A_FALSE == _adpt_hppe_port_phy_connected (dev_id, port_id)) - return SW_NOT_SUPPORTED; - - SW_RTN_ON_NULL (phy_drv = hsl_phy_api_ops_get (dev_id, port_id)); - if (NULL == phy_drv->phy_autoneg_adv_get) - return SW_NOT_SUPPORTED; - - rv = hsl_port_prop_get_phyid (dev_id, port_id, &phy_id); - SW_RTN_ON_ERROR (rv); - - *autoadv = 0; - rv = phy_drv->phy_autoneg_adv_get (dev_id, phy_id, autoadv); - SW_RTN_ON_ERROR (rv); - - return SW_OK; - -} -#ifndef IN_PORTCONTROL_MINI -sw_error_t -adpt_hppe_port_mdix_status_get(a_uint32_t dev_id, fal_port_t port_id, - fal_port_mdix_status_t * mode) -{ - - sw_error_t rv = 0; - a_uint32_t phy_id = 0; - hsl_phy_ops_t *phy_drv; - - ADPT_DEV_ID_CHECK(dev_id); - ADPT_NULL_POINT_CHECK(mode); - - if (A_TRUE != hsl_port_prop_check (dev_id, port_id, HSL_PP_PHY)) - { - return SW_BAD_PARAM; - } - if (A_FALSE == _adpt_hppe_port_phy_connected (dev_id, port_id)) - return SW_NOT_SUPPORTED; - - SW_RTN_ON_NULL (phy_drv = hsl_phy_api_ops_get (dev_id, port_id)); - if (NULL == phy_drv->phy_mdix_status_get) - return SW_NOT_SUPPORTED; - - rv = hsl_port_prop_get_phyid (dev_id, port_id, &phy_id); - SW_RTN_ON_ERROR (rv); - - rv = phy_drv->phy_mdix_status_get (dev_id, phy_id, mode); - - return rv; - -} -#endif -sw_error_t -adpt_hppe_port_link_status_get(a_uint32_t dev_id, fal_port_t port_id, - a_bool_t * status) -{ - - sw_error_t rv = 0; - a_uint32_t phy_id; - hsl_phy_ops_t *phy_drv; - struct port_phy_status phy_status = {0}; - - ADPT_DEV_ID_CHECK(dev_id); - ADPT_NULL_POINT_CHECK(status); - - if (port_id == SSDK_PHYSICAL_PORT0 || port_id == SSDK_PHYSICAL_PORT7) - { - *status = A_TRUE; - return SW_OK; - } - if (A_TRUE != hsl_port_prop_check (dev_id, port_id, HSL_PP_INCL_CPU)) - { - return SW_BAD_PARAM; - } - - /* for those ports without PHY device should be sfp port */ - if (A_FALSE == _adpt_hppe_port_phy_connected (dev_id, port_id)) - { - rv = _adpt_phy_status_get_from_ppe(dev_id, - port_id, &phy_status); - SW_RTN_ON_ERROR (rv); - *status = (a_bool_t) phy_status.link_status; - } - else - { - SW_RTN_ON_NULL (phy_drv = hsl_phy_api_ops_get (dev_id, port_id)); - if (NULL == phy_drv->phy_link_status_get) - return SW_NOT_SUPPORTED; - - rv = hsl_port_prop_get_phyid (dev_id, port_id, &phy_id); - SW_RTN_ON_ERROR (rv); - - if (A_TRUE == phy_drv->phy_link_status_get (dev_id, phy_id)) - { - *status = A_TRUE; - } - else - { - *status = A_FALSE; - } - } - - return SW_OK; - -} -#ifndef IN_PORTCONTROL_MINI -sw_error_t -adpt_hppe_port_8023az_set(a_uint32_t dev_id, fal_port_t port_id, - a_bool_t enable) -{ - - sw_error_t rv = 0; - a_uint32_t phy_id = 0; - hsl_phy_ops_t *phy_drv; - - ADPT_DEV_ID_CHECK(dev_id); - - if (A_TRUE != hsl_port_prop_check (dev_id, port_id, HSL_PP_PHY)) - { - return SW_BAD_PARAM; - } - if (A_FALSE == _adpt_hppe_port_phy_connected (dev_id, port_id)) - return SW_NOT_SUPPORTED; - - SW_RTN_ON_NULL (phy_drv = hsl_phy_api_ops_get (dev_id, port_id)); - if (NULL == phy_drv->phy_8023az_set) - return SW_NOT_SUPPORTED; - - rv = hsl_port_prop_get_phyid (dev_id, port_id, &phy_id); - SW_RTN_ON_ERROR (rv); - - rv = phy_drv->phy_8023az_set (dev_id, phy_id, enable); - - return rv; - -} -sw_error_t -adpt_hppe_port_powersave_get(a_uint32_t dev_id, fal_port_t port_id, - a_bool_t * enable) -{ - - sw_error_t rv = 0; - a_uint32_t phy_id = 0; - hsl_phy_ops_t *phy_drv; - - ADPT_DEV_ID_CHECK(dev_id); - ADPT_NULL_POINT_CHECK(enable); - - if (A_TRUE != hsl_port_prop_check (dev_id, port_id, HSL_PP_PHY)) - { - return SW_BAD_PARAM; - } - if (A_FALSE == _adpt_hppe_port_phy_connected (dev_id, port_id)) - return SW_NOT_SUPPORTED; - - SW_RTN_ON_NULL (phy_drv = hsl_phy_api_ops_get (dev_id, port_id)); - if (NULL == phy_drv->phy_powersave_get) - return SW_NOT_SUPPORTED; - - rv = hsl_port_prop_get_phyid (dev_id, port_id, &phy_id); - SW_RTN_ON_ERROR (rv); - - rv = phy_drv->phy_powersave_get (dev_id, phy_id, enable); - - return rv; - -} - -sw_error_t -adpt_hppe_port_combo_prefer_medium_get(a_uint32_t dev_id, - a_uint32_t port_id, - fal_port_medium_t * - medium) -{ - sw_error_t rv = 0; - a_uint32_t phy_id = 0; - hsl_phy_ops_t *phy_drv; - - ADPT_DEV_ID_CHECK(dev_id); - ADPT_NULL_POINT_CHECK(medium); - - if (A_TRUE != hsl_port_prop_check (dev_id, port_id, HSL_PP_PHY)) - { - return SW_BAD_PARAM; - } - if (A_FALSE == _adpt_hppe_port_phy_connected (dev_id, port_id)) - return SW_NOT_SUPPORTED; - - SW_RTN_ON_NULL (phy_drv = hsl_phy_api_ops_get (dev_id, port_id)); - if (NULL == phy_drv->phy_combo_prefer_medium_get) - return SW_NOT_SUPPORTED; - - rv = hsl_port_prop_get_phyid (dev_id, port_id, &phy_id); - SW_RTN_ON_ERROR (rv); - - rv = phy_drv->phy_combo_prefer_medium_get (dev_id, phy_id, medium); - - return rv; - -} -#endif -sw_error_t -adpt_hppe_port_max_frame_size_get(a_uint32_t dev_id, fal_port_t port_id, - a_uint32_t *max_frame) -{ - sw_error_t rv = SW_OK; - a_uint32_t port_mac_type = 0; - - ADPT_DEV_ID_CHECK(dev_id); - ADPT_NULL_POINT_CHECK(max_frame); - - port_mac_type =qca_hppe_port_mac_type_get(dev_id, port_id); - if (port_mac_type == PORT_XGMAC_TYPE) - { - rv = _adpt_xgmac_port_max_frame_size_get( dev_id, port_id, max_frame); - } - else if (port_mac_type == PORT_GMAC_TYPE) - { - rv = _adpt_gmac_port_max_frame_size_get( dev_id, port_id, max_frame); - } - else - { - return SW_BAD_VALUE; - } - - return rv; -} - -sw_error_t -adpt_ppe_port_max_frame_size_get(a_uint32_t dev_id, fal_port_t port_id, - a_uint32_t *max_frame) -{ -#ifdef CPPE - if (adpt_hppe_chip_revision_get(dev_id) == CPPE_REVISION && - port_id == SSDK_PHYSICAL_PORT6) - { - return adpt_cppe_lpbk_max_frame_size_get(dev_id, port_id, max_frame); - } -#endif - return adpt_hppe_port_max_frame_size_get(dev_id, port_id, max_frame); - -} - -#ifndef IN_PORTCONTROL_MINI -sw_error_t -adpt_hppe_port_combo_prefer_medium_set(a_uint32_t dev_id, - a_uint32_t port_id, - fal_port_medium_t medium) -{ - - sw_error_t rv = 0; - a_uint32_t phy_id = 0; - hsl_phy_ops_t *phy_drv; - - ADPT_DEV_ID_CHECK(dev_id); - - if (A_TRUE != hsl_port_prop_check (dev_id, port_id, HSL_PP_PHY)) - { - return SW_BAD_PARAM; - } - if (A_FALSE == _adpt_hppe_port_phy_connected (dev_id, port_id)) - return SW_NOT_SUPPORTED; - - SW_RTN_ON_NULL (phy_drv = hsl_phy_api_ops_get (dev_id, port_id)); - if (NULL == phy_drv->phy_combo_prefer_medium_set) - return SW_NOT_SUPPORTED; - - rv = hsl_port_prop_get_phyid (dev_id, port_id, &phy_id); - SW_RTN_ON_ERROR (rv); - - rv = phy_drv->phy_combo_prefer_medium_set (dev_id, phy_id, medium); - - return rv; - -} -#endif -sw_error_t -adpt_hppe_port_power_off(a_uint32_t dev_id, fal_port_t port_id) -{ - - sw_error_t rv = 0; - a_uint32_t phy_id = 0; - hsl_phy_ops_t *phy_drv; - - ADPT_DEV_ID_CHECK(dev_id); - - if (A_TRUE != hsl_port_prop_check (dev_id, port_id, HSL_PP_PHY)) - { - return SW_BAD_PARAM; - } - if (A_FALSE == _adpt_hppe_port_phy_connected (dev_id, port_id)) - return SW_NOT_SUPPORTED; - - SW_RTN_ON_NULL (phy_drv = hsl_phy_api_ops_get (dev_id, port_id)); - if (NULL == phy_drv->phy_power_off) - return SW_NOT_SUPPORTED; - - rv = hsl_port_prop_get_phyid (dev_id, port_id, &phy_id); - SW_RTN_ON_ERROR (rv); - - rv = phy_drv->phy_power_off(dev_id, phy_id); - - return rv; - -} -sw_error_t -adpt_hppe_port_txfc_status_set(a_uint32_t dev_id, fal_port_t port_id, - a_bool_t enable) -{ - sw_error_t rv = SW_OK; - a_uint32_t port_mac_type; - struct qca_phy_priv *priv = ssdk_phy_priv_data_get(dev_id); - adpt_api_t *p_adpt_api; - - ADPT_DEV_ID_CHECK(dev_id); - - if (!priv) - return SW_FAIL; - - if ((port_id < SSDK_PHYSICAL_PORT1) || (port_id > SSDK_PHYSICAL_PORT6)) - return SW_BAD_VALUE; - - port_mac_type =qca_hppe_port_mac_type_get(dev_id, port_id); - if (port_mac_type == PORT_XGMAC_TYPE) - rv = _adpt_xgmac_port_txfc_status_set( dev_id, port_id, enable); - else if (port_mac_type == PORT_GMAC_TYPE) - rv = _adpt_gmac_port_txfc_status_set( dev_id, port_id, enable); - else - return SW_BAD_VALUE; - - if (rv != SW_OK) - return rv; - - priv->port_old_tx_flowctrl[port_id - 1] = enable; - - /*keep bm status same with port*/ - p_adpt_api = adpt_api_ptr_get(dev_id); - if (p_adpt_api && p_adpt_api->adpt_port_bm_ctrl_set) - rv = p_adpt_api->adpt_port_bm_ctrl_set(dev_id, - PHY_PORT_TO_BM_PORT(port_id), - enable); - - return rv; -} - -sw_error_t -adpt_hppe_port_rxfc_status_set(a_uint32_t dev_id, fal_port_t port_id, - a_bool_t enable) -{ - sw_error_t rv = SW_OK; - a_uint32_t port_mac_type; - struct qca_phy_priv *priv = ssdk_phy_priv_data_get(dev_id); - - ADPT_DEV_ID_CHECK(dev_id); - - if (!priv) - return SW_FAIL; - - if ((port_id < SSDK_PHYSICAL_PORT1) || (port_id > SSDK_PHYSICAL_PORT6)) - return SW_BAD_VALUE; - - port_mac_type =qca_hppe_port_mac_type_get(dev_id, port_id); - if(port_mac_type == PORT_XGMAC_TYPE) - rv = _adpt_xgmac_port_rxfc_status_set( dev_id, port_id, enable); - else if (port_mac_type == PORT_GMAC_TYPE) - rv = _adpt_gmac_port_rxfc_status_set( dev_id, port_id, enable); - else - return SW_BAD_VALUE; - - if (rv != SW_OK) - return rv; - - priv->port_old_rx_flowctrl[port_id - 1] = enable; - - return SW_OK; -} - -#ifndef IN_PORTCONTROL_MINI -sw_error_t -adpt_hppe_port_counter_set(a_uint32_t dev_id, fal_port_t port_id, - a_bool_t enable) -{ - - sw_error_t rv = 0; - a_uint32_t phy_id = 0; - hsl_phy_ops_t *phy_drv; - - ADPT_DEV_ID_CHECK(dev_id); - - if (A_TRUE != hsl_port_prop_check (dev_id, port_id, HSL_PP_PHY)) - { - return SW_BAD_PARAM; - } - if (A_FALSE == _adpt_hppe_port_phy_connected (dev_id, port_id)) - return SW_NOT_SUPPORTED; - - SW_RTN_ON_NULL (phy_drv = hsl_phy_api_ops_get (dev_id, port_id)); - if (NULL == phy_drv->phy_counter_set) - return SW_NOT_SUPPORTED; - - rv = hsl_port_prop_get_phyid (dev_id, port_id, &phy_id); - SW_RTN_ON_ERROR (rv); - - rv = phy_drv->phy_counter_set (dev_id, phy_id, enable); - - return rv; -} -sw_error_t -adpt_hppe_port_combo_fiber_mode_get(a_uint32_t dev_id, - a_uint32_t port_id, - fal_port_fiber_mode_t * mode) -{ - sw_error_t rv = 0; - a_uint32_t phy_id = 0; - hsl_phy_ops_t *phy_drv; - - ADPT_DEV_ID_CHECK(dev_id); - ADPT_NULL_POINT_CHECK(mode); - - if (A_TRUE != hsl_port_prop_check (dev_id, port_id, HSL_PP_PHY)) - { - return SW_BAD_PARAM; - } - if (A_FALSE == _adpt_hppe_port_phy_connected (dev_id, port_id)) - return SW_NOT_SUPPORTED; - - SW_RTN_ON_NULL (phy_drv = hsl_phy_api_ops_get (dev_id, port_id)); - if (NULL == phy_drv->phy_combo_fiber_mode_get) - return SW_NOT_SUPPORTED; - - rv = hsl_port_prop_get_phyid (dev_id, port_id, &phy_id); - SW_RTN_ON_ERROR (rv); - - rv = phy_drv->phy_combo_fiber_mode_get (dev_id, phy_id, mode); - - return rv; - -} - -sw_error_t -adpt_hppe_port_local_loopback_set(a_uint32_t dev_id, - fal_port_t port_id, - a_bool_t enable) -{ - - sw_error_t rv = 0; - a_uint32_t phy_id = 0; - hsl_phy_ops_t *phy_drv; - - ADPT_DEV_ID_CHECK(dev_id); - - if (A_TRUE != hsl_port_prop_check (dev_id, port_id, HSL_PP_PHY)) - { - return SW_BAD_PARAM; - } - if (A_FALSE == _adpt_hppe_port_phy_connected (dev_id, port_id)) - return SW_NOT_SUPPORTED; - - SW_RTN_ON_NULL (phy_drv = hsl_phy_api_ops_get (dev_id, port_id)); - if (NULL == phy_drv->phy_local_loopback_set) - return SW_NOT_SUPPORTED; - - rv = hsl_port_prop_get_phyid (dev_id, port_id, &phy_id); - SW_RTN_ON_ERROR (rv); - - rv = phy_drv->phy_local_loopback_set (dev_id, phy_id, enable); - - return rv; - -} -sw_error_t -adpt_hppe_port_wol_status_set(a_uint32_t dev_id, fal_port_t port_id, - a_bool_t enable) -{ - - sw_error_t rv = 0; - a_uint32_t phy_id = 0; - hsl_phy_ops_t *phy_drv; - - ADPT_DEV_ID_CHECK(dev_id); - - if (A_TRUE != hsl_port_prop_check (dev_id, port_id, HSL_PP_PHY)) - { - return SW_BAD_PARAM; - } - if (A_FALSE == _adpt_hppe_port_phy_connected (dev_id, port_id)) - return SW_NOT_SUPPORTED; - - SW_RTN_ON_NULL (phy_drv = hsl_phy_api_ops_get (dev_id, port_id)); - if (NULL == phy_drv->phy_wol_status_set) - return SW_NOT_SUPPORTED; - - rv = hsl_port_prop_get_phyid (dev_id, port_id, &phy_id); - SW_RTN_ON_ERROR (rv); - - rv = phy_drv->phy_wol_status_set (dev_id, phy_id, enable); - - return rv; - - -} -sw_error_t -adpt_hppe_port_magic_frame_mac_get(a_uint32_t dev_id, fal_port_t port_id, - fal_mac_addr_t * mac) -{ - - sw_error_t rv; - a_uint32_t phy_id = 0; - hsl_phy_ops_t *phy_drv; - - ADPT_DEV_ID_CHECK(dev_id); - ADPT_NULL_POINT_CHECK(mac); - - if (A_TRUE != hsl_port_prop_check (dev_id, port_id, HSL_PP_PHY)) - { - return SW_BAD_PARAM; - } - if (A_FALSE == _adpt_hppe_port_phy_connected (dev_id, port_id)) - return SW_NOT_SUPPORTED; - - SW_RTN_ON_NULL (phy_drv = hsl_phy_api_ops_get (dev_id, port_id)); - if (NULL == phy_drv->phy_magic_frame_mac_get) - return SW_NOT_SUPPORTED; - - rv = hsl_port_prop_get_phyid (dev_id, port_id, &phy_id); - SW_RTN_ON_ERROR (rv); - - rv = phy_drv->phy_magic_frame_mac_get (dev_id, phy_id,mac); - - return rv; - -} - -sw_error_t -adpt_hppe_port_flowctrl_get(a_uint32_t dev_id, fal_port_t port_id, - a_bool_t * enable) -{ - sw_error_t rv = SW_OK; - a_bool_t txfc_enable, rxfc_enable; - -#if defined(CPPE) - if ((adpt_hppe_chip_revision_get(dev_id) == CPPE_REVISION) && - (port_id == SSDK_PHYSICAL_PORT6)) { - return adpt_cppe_switch_port_loopback_flowctrl_get(dev_id, - port_id, enable); - } -#endif - rv = adpt_hppe_port_txfc_status_get(dev_id, port_id, &txfc_enable); - rv |= adpt_hppe_port_rxfc_status_get(dev_id, port_id, &rxfc_enable); - if(rv != SW_OK) - return rv; - *enable = txfc_enable & rxfc_enable; - - return SW_OK; -} -#endif -sw_error_t -adpt_hppe_port_rxmac_status_set(a_uint32_t dev_id, fal_port_t port_id, - a_bool_t enable) -{ - a_uint32_t port_mac_type; - - ADPT_DEV_ID_CHECK(dev_id); - - port_mac_type =qca_hppe_port_mac_type_get(dev_id, port_id); - if (port_mac_type == PORT_XGMAC_TYPE) - _adpt_xgmac_port_rx_status_set(dev_id, port_id, enable); - else if (port_mac_type == PORT_GMAC_TYPE) - _adpt_gmac_port_rx_status_set(dev_id, port_id, enable); - else - return SW_BAD_VALUE; - - return SW_OK; -} -#ifndef IN_PORTCONTROL_MINI -sw_error_t -adpt_hppe_port_counter_get(a_uint32_t dev_id, fal_port_t port_id, - a_bool_t * enable) -{ - - sw_error_t rv; - a_uint32_t phy_id = 0; - hsl_phy_ops_t *phy_drv; - - ADPT_DEV_ID_CHECK(dev_id); - ADPT_NULL_POINT_CHECK(enable); - - if (A_TRUE != hsl_port_prop_check (dev_id, port_id, HSL_PP_PHY)) - { - return SW_BAD_PARAM; - } - if (A_FALSE == _adpt_hppe_port_phy_connected (dev_id, port_id)) - return SW_NOT_SUPPORTED; - - SW_RTN_ON_NULL (phy_drv = hsl_phy_api_ops_get (dev_id, port_id)); - if (NULL == phy_drv->phy_counter_get) - return SW_NOT_SUPPORTED; - - rv = hsl_port_prop_get_phyid (dev_id, port_id, &phy_id); - SW_RTN_ON_ERROR (rv); - - rv = phy_drv->phy_counter_get (dev_id, phy_id, enable); - - return rv; - -} -#endif - -static sw_error_t -_adpt_hppe_port_interface_mode_set(a_uint32_t dev_id, fal_port_t port_id, - fal_port_interface_mode_t mode) -{ - sw_error_t rv = SW_OK; - - ADPT_DEV_ID_CHECK(dev_id); - if (A_TRUE != hsl_port_prop_check (dev_id, port_id, HSL_PP_EXCL_CPU) && - mode != PORT_INTERFACE_MODE_MAX) - { - return SW_BAD_PARAM; - } - - port_interface_mode[dev_id][port_id] = mode; - - return rv; -} - -sw_error_t -adpt_hppe_port_interface_mode_set(a_uint32_t dev_id, fal_port_t port_id, - fal_port_interface_mode_t mode) -{ - sw_error_t rv = SW_OK; - struct qca_phy_priv *priv; - - priv = ssdk_phy_priv_data_get(dev_id); - SW_RTN_ON_NULL(priv); - qca_mac_sw_sync_work_stop(priv); - - rv = _adpt_hppe_port_interface_mode_set(dev_id, port_id, mode); - - return rv; -} - -static sw_error_t -_adpt_hppe_gmac_speed_set(a_uint32_t dev_id, a_uint32_t port_id, fal_port_speed_t speed) -{ - sw_error_t rv = SW_OK; - union mac_speed_u mac_speed; - - memset(&mac_speed, 0, sizeof(mac_speed)); - ADPT_DEV_ID_CHECK(dev_id); - - port_id = HPPE_TO_GMAC_PORT_ID(port_id); - hppe_mac_speed_get(dev_id, port_id, &mac_speed); - - if(FAL_SPEED_10 == speed) - mac_speed.bf.mac_speed = MAC_SPEED_10M; - else if(FAL_SPEED_100 == speed) - mac_speed.bf.mac_speed = MAC_SPEED_100M; - else if(FAL_SPEED_1000 == speed || FAL_SPEED_2500 == speed) - mac_speed.bf.mac_speed = MAC_SPEED_1000M; - - rv = hppe_mac_speed_set(dev_id, port_id, &mac_speed); - - return rv; -} - -static sw_error_t -_adpt_hppe_xgmac_speed_set(a_uint32_t dev_id, a_uint32_t port_id, fal_port_speed_t speed) -{ - sw_error_t rv = SW_OK; - union mac_tx_configuration_u mac_tx_configuration; - a_uint32_t mode = 0; - - memset(&mac_tx_configuration, 0, sizeof(mac_tx_configuration)); - ADPT_DEV_ID_CHECK(dev_id); - - port_id = HPPE_TO_XGMAC_PORT_ID(port_id); - hppe_mac_tx_configuration_get(dev_id, port_id, &mac_tx_configuration); - - if(FAL_SPEED_1000 == speed) - { - mac_tx_configuration.bf.uss= XGMAC_USXGMII_CLEAR; - mac_tx_configuration.bf.ss= XGMAC_SPEED_SELECT_1000M; - } - else if(FAL_SPEED_10000 == speed) - { - if (port_id == SSDK_PHYSICAL_PORT0) - { - mode = ssdk_dt_global_get_mac_mode(dev_id, SSDK_UNIPHY_INSTANCE1); - } - else - { - mode = ssdk_dt_global_get_mac_mode(dev_id, SSDK_UNIPHY_INSTANCE2); - } - if (mode == PORT_WRAPPER_USXGMII) - { - mac_tx_configuration.bf.uss= XGMAC_USXGMII_ENABLE; - mac_tx_configuration.bf.ss= XGMAC_SPEED_SELECT_10000M; - } - else - { - mac_tx_configuration.bf.uss= XGMAC_USXGMII_CLEAR; - mac_tx_configuration.bf.ss= XGMAC_SPEED_SELECT_10000M; - } - } - else if(FAL_SPEED_5000 == speed) - { - mac_tx_configuration.bf.uss= XGMAC_USXGMII_ENABLE; - mac_tx_configuration.bf.ss= XGMAC_SPEED_SELECT_5000M; - } - else if(FAL_SPEED_2500 == speed) - { - if (port_id == SSDK_PHYSICAL_PORT0) - { - mode = ssdk_dt_global_get_mac_mode(dev_id, SSDK_UNIPHY_INSTANCE1); - } - else - { - mode = ssdk_dt_global_get_mac_mode(dev_id, SSDK_UNIPHY_INSTANCE2); - } - if (mode == PORT_WRAPPER_USXGMII) - { - mac_tx_configuration.bf.uss= XGMAC_USXGMII_ENABLE; - mac_tx_configuration.bf.ss= XGMAC_SPEED_SELECT_2500M; - } - else - { - mac_tx_configuration.bf.uss= XGMAC_USXGMII_CLEAR; - mac_tx_configuration.bf.ss= XGMAC_SPEED_SELECT_2500M; - } - } - else if(FAL_SPEED_100 == speed) - { - mac_tx_configuration.bf.uss= XGMAC_USXGMII_CLEAR; - mac_tx_configuration.bf.ss= XGMAC_SPEED_SELECT_1000M; - } - else if(FAL_SPEED_10 == speed) - { - mac_tx_configuration.bf.uss= XGMAC_USXGMII_CLEAR; - mac_tx_configuration.bf.ss= XGMAC_SPEED_SELECT_1000M; - } - - rv = hppe_mac_tx_configuration_set(dev_id, port_id, &mac_tx_configuration); - - return rv; -} - -static sw_error_t -_adpt_hppe_gmac_duplex_set(a_uint32_t dev_id, a_uint32_t port_id, fal_port_duplex_t duplex) -{ - sw_error_t rv = SW_OK; - union mac_enable_u mac_enable; - - memset(&mac_enable, 0, sizeof(mac_enable)); - ADPT_DEV_ID_CHECK(dev_id); - - port_id = HPPE_TO_GMAC_PORT_ID(port_id); - hppe_mac_enable_get(dev_id, port_id, &mac_enable); - - if (FAL_FULL_DUPLEX == duplex) - mac_enable.bf.duplex = 1; - else - mac_enable.bf.duplex = 0; - - rv = hppe_mac_enable_set(dev_id, port_id, &mac_enable); - - return rv; -} - -sw_error_t -adpt_hppe_port_mac_duplex_set(a_uint32_t dev_id, a_uint32_t port_id, fal_port_duplex_t duplex) -{ - sw_error_t rv = SW_OK; - a_uint32_t port_mac_type; - - port_mac_type = qca_hppe_port_mac_type_get(dev_id, port_id); - if (port_mac_type == PORT_XGMAC_TYPE) - { - return rv; - } - else if (port_mac_type == PORT_GMAC_TYPE) - { - rv = _adpt_hppe_gmac_duplex_set(dev_id, port_id, duplex); - } - else - { - return SW_BAD_VALUE; - } - - return rv; -} - -static sw_error_t -_adpt_hppe_port_mux_mac_set(a_uint32_t dev_id, fal_port_t port_id, a_uint32_t port_type) -{ - sw_error_t rv = SW_OK; - union port_mux_ctrl_u port_mux_ctrl; - a_uint32_t mode0, mode1; - - memset(&port_mux_ctrl, 0, sizeof(port_mux_ctrl)); - ADPT_DEV_ID_CHECK(dev_id); - - rv = hppe_port_mux_ctrl_get(dev_id, &port_mux_ctrl); - port_mux_ctrl.bf.port4_pcs_sel = PORT4_PCS_SEL_GMII_FROM_PCS0; - - if (port_id == HPPE_MUX_PORT1) - { - if (port_type == PORT_GMAC_TYPE) - { - mode0 = ssdk_dt_global_get_mac_mode(dev_id, SSDK_UNIPHY_INSTANCE0); - mode1 = ssdk_dt_global_get_mac_mode(dev_id, SSDK_UNIPHY_INSTANCE1); - if ((mode0 == PORT_WRAPPER_PSGMII) || - (mode0 == PORT_WRAPPER_PSGMII_FIBER) || - (mode0 == PORT_WRAPPER_SGMII4_RGMII4) || - (mode0 == PORT_WRAPPER_SGMII_CHANNEL4)) - { - port_mux_ctrl.bf.port5_pcs_sel = PORT5_PCS_SEL_GMII_FROM_PCS0; - port_mux_ctrl.bf.port5_gmac_sel = PORT5_GMAC_SEL_GMAC; - } - if (mode1 == PORT_WRAPPER_SGMII0_RGMII4 || - mode1 == PORT_WRAPPER_SGMII_CHANNEL0 || - mode1 == PORT_WRAPPER_SGMII_PLUS || - mode1 == PORT_WRAPPER_SGMII_FIBER) - { - port_mux_ctrl.bf.port5_pcs_sel = PORT5_PCS_SEL_GMII_FROM_PCS1; - port_mux_ctrl.bf.port5_gmac_sel = PORT5_GMAC_SEL_GMAC; - } - } - else if (port_type == PORT_XGMAC_TYPE) - { - port_mux_ctrl.bf.port5_pcs_sel = PORT5_PCS_SEL_GMII_FROM_PCS1; - port_mux_ctrl.bf.port5_gmac_sel = PORT5_GMAC_SEL_XGMAC; - } - else - return SW_NOT_SUPPORTED; - } - else if (port_id == HPPE_MUX_PORT2) - { - if (port_type == PORT_GMAC_TYPE) - { - port_mux_ctrl.bf.port6_pcs_sel = PORT6_PCS_SEL_GMII_FROM_PCS2; - port_mux_ctrl.bf.port6_gmac_sel = PORT6_GMAC_SEL_GMAC; - } - else if (port_type == PORT_XGMAC_TYPE) - { - port_mux_ctrl.bf.port6_pcs_sel = PORT6_PCS_SEL_GMII_FROM_PCS2; - port_mux_ctrl.bf.port6_gmac_sel = PORT6_GMAC_SEL_XGMAC; - } - else - return SW_NOT_SUPPORTED; - } - else - return SW_OK; - - rv = hppe_port_mux_ctrl_set(dev_id, &port_mux_ctrl); - - return rv; -} - -static sw_error_t -adpt_hppe_port_xgmac_promiscuous_mode_set(a_uint32_t dev_id, - a_uint32_t port_id) -{ - sw_error_t rv = 0; - - port_id = HPPE_TO_XGMAC_PORT_ID(port_id); - - rv = hppe_mac_packet_filter_pr_set(dev_id, port_id, PROMISCUOUS_MODE); - - SW_RTN_ON_ERROR (rv); - - rv = hppe_mac_packet_filter_pcf_set(dev_id, port_id, PASS_CONTROL_PACKET); - - return rv; -} -static sw_error_t -adpt_hppe_port_speed_change_mac_reset(a_uint32_t dev_id, a_uint32_t port_id) -{ - a_uint32_t uniphy_index = 0, mode = 0; - a_uint32_t rxfc_status = 0, txfc_status = 0; - sw_error_t rv = 0; - - if (port_id == HPPE_MUX_PORT1) { - uniphy_index = SSDK_UNIPHY_INSTANCE1; - } else if (port_id == HPPE_MUX_PORT2) { - uniphy_index = SSDK_UNIPHY_INSTANCE2; - } else { - return SW_OK; - } - mode = ssdk_dt_global_get_mac_mode(dev_id, uniphy_index); - if (mode == PORT_WRAPPER_USXGMII) { - ssdk_port_mac_clock_reset(dev_id, port_id); - /*restore xgmac's pr and pcf setting after reset operation*/ - rv = adpt_hppe_port_xgmac_promiscuous_mode_set(dev_id, - port_id); - SW_RTN_ON_ERROR(rv); - /*flowctrl need to be configured when reset XGMAC*/ - rv = _adpt_xgmac_port_rxfc_status_get(dev_id, port_id, - &rxfc_status); - SW_RTN_ON_ERROR(rv); - rv = _adpt_xgmac_port_rxfc_status_set(dev_id, port_id, - rxfc_status); - SW_RTN_ON_ERROR(rv); - - rv = _adpt_xgmac_port_txfc_status_get(dev_id, port_id, - &txfc_status); - SW_RTN_ON_ERROR(rv); - rv = _adpt_xgmac_port_txfc_status_set(dev_id, port_id, - txfc_status); - } - return rv; -} -static sw_error_t -adpt_hppe_port_interface_mode_switch_mac_reset(a_uint32_t dev_id, - a_uint32_t port_id) -{ - a_uint32_t uniphy_index = 0, mode = 0; - sw_error_t rv = 0; - phy_type_t phy_type; - a_uint32_t port_mac_type; - - phy_type = hsl_phy_type_get(dev_id, port_id); - if (phy_type != AQUANTIA_PHY_CHIP && phy_type != SFP_PHY_CHIP) { - return SW_OK; - } - - if (port_id == HPPE_MUX_PORT1) { - uniphy_index = SSDK_UNIPHY_INSTANCE1; - } else if (port_id == HPPE_MUX_PORT2) { - uniphy_index = SSDK_UNIPHY_INSTANCE2; - } else { - return SW_OK; - } - - mode = ssdk_dt_global_get_mac_mode(dev_id, uniphy_index); - if ((mode == PORT_WRAPPER_USXGMII) || - (mode == PORT_WRAPPER_SGMII_CHANNEL0) || - (mode == PORT_WRAPPER_SGMII0_RGMII4) || - (mode == PORT_WRAPPER_SGMII_FIBER) || - (mode == PORT_WRAPPER_10GBASE_R)) { - ssdk_port_mac_clock_reset(dev_id, port_id); - port_mac_type = qca_hppe_port_mac_type_get(dev_id, port_id); - if (port_mac_type == PORT_XGMAC_TYPE) { - /*restore xgmac's pr and pcf setting after reset operation*/ - rv = adpt_hppe_port_xgmac_promiscuous_mode_set(dev_id, - port_id); - } - } - return rv; -} - -sw_error_t -adpt_hppe_port_mac_speed_set(a_uint32_t dev_id, a_uint32_t port_id, - fal_port_speed_t speed) -{ - sw_error_t rv = SW_OK; - a_uint32_t port_mac_type; - - port_mac_type = qca_hppe_port_mac_type_get(dev_id, port_id); - if (port_mac_type == PORT_XGMAC_TYPE) - { - rv = _adpt_hppe_xgmac_speed_set(dev_id, port_id, speed); - - } - else if (port_mac_type == PORT_GMAC_TYPE) - { - rv = _adpt_hppe_gmac_speed_set(dev_id, port_id, speed); - } - else - { - return SW_BAD_VALUE; - } - return rv; -} -static sw_error_t -_adpt_hppe_port_mux_set(a_uint32_t dev_id, fal_port_t port_id, - a_uint32_t mode1, a_uint32_t mode2) -{ - a_uint32_t mode = 0, port_type; - sw_error_t rv = SW_OK; - - port_type = qca_hppe_port_mac_type_get(dev_id, port_id); - if (port_type == PORT_GMAC_TYPE) - { - rv = adpt_hppe_port_mac_speed_set(dev_id, port_id, FAL_SPEED_1000); - rv = adpt_hppe_port_mac_duplex_set(dev_id, port_id, FAL_FULL_DUPLEX); - } - else if (port_type == PORT_XGMAC_TYPE) - { - if (port_id == HPPE_MUX_PORT1) - mode = mode1; - else if (port_id == HPPE_MUX_PORT2) - mode = mode2; - else - return SW_NOT_SUPPORTED; - if (mode == PORT_WRAPPER_SGMII_PLUS) - { - rv = adpt_hppe_port_mac_speed_set(dev_id, port_id, FAL_SPEED_2500); - rv = adpt_hppe_port_mac_duplex_set(dev_id, port_id, FAL_FULL_DUPLEX); - } - else - { - rv = adpt_hppe_port_mac_speed_set(dev_id, port_id, FAL_SPEED_10000); - rv = adpt_hppe_port_mac_duplex_set(dev_id, port_id, FAL_FULL_DUPLEX); - } - } - if ((port_type == PORT_GMAC_TYPE) ||(port_type == PORT_XGMAC_TYPE)) { - if (adpt_hppe_chip_revision_get(dev_id) == HPPE_REVISION) { - rv = _adpt_hppe_port_mux_mac_set(dev_id, port_id, port_type); - } else if (adpt_hppe_chip_revision_get(dev_id) == CPPE_REVISION) { -#if defined(CPPE) - rv = _adpt_cppe_port_mux_mac_set(dev_id, port_id, port_type); -#endif - } - } - - if (port_id >= HPPE_MUX_PORT1) { - if (port_type == PORT_GMAC_TYPE) { - rv = _adpt_xgmac_port_txfc_status_set( dev_id, port_id, A_FALSE); - SW_RTN_ON_ERROR(rv); - rv = _adpt_xgmac_port_rxfc_status_set( dev_id, port_id, A_FALSE); - SW_RTN_ON_ERROR(rv); - } else if (port_type == PORT_XGMAC_TYPE) { - rv = _adpt_gmac_port_txfc_status_set( dev_id, port_id, A_FALSE); - SW_RTN_ON_ERROR(rv); - rv = _adpt_gmac_port_rxfc_status_set( dev_id, port_id, A_FALSE); - SW_RTN_ON_ERROR(rv); - } else { - return SW_NOT_SUPPORTED; - } - rv = adpt_hppe_port_interface_mode_switch_mac_reset(dev_id, port_id); - } - - return rv; -} - -sw_error_t -adpt_hppe_port_mux_mac_type_set(a_uint32_t dev_id, fal_port_t port_id, - a_uint32_t mode0, a_uint32_t mode1, a_uint32_t mode2) -{ - sw_error_t rv = SW_OK; - a_uint32_t mode_tmp; - - /*init the port interface mode before set it according to three mac modes*/ - rv = _adpt_hppe_port_interface_mode_set(dev_id, port_id, PORT_INTERFACE_MODE_MAX); - SW_RTN_ON_ERROR(rv); - - switch (mode0) { - case PORT_WRAPPER_PSGMII_FIBER: - if(port_id >= SSDK_PHYSICAL_PORT1 && port_id <= SSDK_PHYSICAL_PORT5) - { - qca_hppe_port_mac_type_set(dev_id, port_id, PORT_GMAC_TYPE); - if (port_id == SSDK_PHYSICAL_PORT5) { - _adpt_hppe_port_interface_mode_set(dev_id, - SSDK_PHYSICAL_PORT5, PHY_PSGMII_FIBER); - } else { - _adpt_hppe_port_interface_mode_set(dev_id, - port_id, PHY_PSGMII_BASET); - } - } - break; - case PORT_WRAPPER_PSGMII: - if((port_id >= SSDK_PHYSICAL_PORT1 && port_id <= SSDK_PHYSICAL_PORT4) || - (port_id == SSDK_PHYSICAL_PORT5 && - mode1 == PORT_WRAPPER_MAX)) - { - qca_hppe_port_mac_type_set(dev_id, port_id, PORT_GMAC_TYPE); - _adpt_hppe_port_interface_mode_set(dev_id, port_id, PHY_PSGMII_BASET); - } - break; - case PORT_WRAPPER_QSGMII: - if(port_id >= SSDK_PHYSICAL_PORT1 && port_id <= SSDK_PHYSICAL_PORT4) - { - qca_hppe_port_mac_type_set(dev_id, port_id, PORT_GMAC_TYPE); - _adpt_hppe_port_interface_mode_set(dev_id, port_id, PORT_QSGMII); - } - break; - case PORT_WRAPPER_SGMII0_RGMII4: - case PORT_WRAPPER_SGMII_CHANNEL0: - case PORT_WRAPPER_SGMII_FIBER: -#ifdef CPPE - case PORT_WRAPPER_SGMII_PLUS: - if(adpt_hppe_chip_revision_get(dev_id) == CPPE_REVISION - && port_id == SSDK_PHYSICAL_PORT4) - { - qca_hppe_port_mac_type_set(dev_id, port_id, - PORT_GMAC_TYPE); - if((mode0 == PORT_WRAPPER_SGMII0_RGMII4 || - mode0 == PORT_WRAPPER_SGMII_CHANNEL0)) - { - if(hsl_port_prop_check (dev_id, port_id, - HSL_PP_EXCL_CPU)) - { - _adpt_hppe_port_interface_mode_set(dev_id, port_id, - PHY_SGMII_BASET); - } - else - { - SSDK_ERROR("Port bitmap is incorrect when port 4" - "support sgmii for CPPE\n"); - return SW_NOT_SUPPORTED; - } - } - else if(mode0 == PORT_WRAPPER_SGMII_PLUS) - { - _adpt_hppe_port_interface_mode_set(dev_id, port_id, - PORT_SGMII_PLUS); - } - else - { - SSDK_ERROR("CPPE doesn't support mode0 : %x\n", - mode0); - return SW_NOT_SUPPORTED; - } - break; - } -#endif - if(port_id == SSDK_PHYSICAL_PORT1) - { - qca_hppe_port_mac_type_set(dev_id, SSDK_PHYSICAL_PORT1, - PORT_GMAC_TYPE); - if(mode0 == PORT_WRAPPER_SGMII_FIBER) - { - _adpt_hppe_port_interface_mode_set(dev_id, - SSDK_PHYSICAL_PORT1, PORT_SGMII_FIBER); - } - else - { - _adpt_hppe_port_interface_mode_set(dev_id, - SSDK_PHYSICAL_PORT1, PHY_SGMII_BASET); - } - } - break; - case PORT_WRAPPER_SGMII1_RGMII4: - case PORT_WRAPPER_SGMII_CHANNEL1: - if(port_id == SSDK_PHYSICAL_PORT2) - { - qca_hppe_port_mac_type_set(dev_id, SSDK_PHYSICAL_PORT2, - PORT_GMAC_TYPE); - _adpt_hppe_port_interface_mode_set(dev_id, - SSDK_PHYSICAL_PORT2, PHY_SGMII_BASET); - } - break; - case PORT_WRAPPER_SGMII4_RGMII4: - case PORT_WRAPPER_SGMII_CHANNEL4: - if(port_id == SSDK_PHYSICAL_PORT5) - { - qca_hppe_port_mac_type_set(dev_id, SSDK_PHYSICAL_PORT5, - PORT_GMAC_TYPE); - _adpt_hppe_port_interface_mode_set(dev_id, - SSDK_PHYSICAL_PORT5, PHY_SGMII_BASET); - } - break; - default: - break; - } - if(port_id == SSDK_PHYSICAL_PORT5 ||port_id == SSDK_PHYSICAL_PORT6) - { - if(port_id == SSDK_PHYSICAL_PORT5) - mode_tmp = mode1; - else - mode_tmp = mode2; - - switch(mode_tmp) - { - case PORT_WRAPPER_SGMII_CHANNEL0: - case PORT_WRAPPER_SGMII0_RGMII4: - case PORT_WRAPPER_SGMII_FIBER: - qca_hppe_port_mac_type_set(dev_id, port_id, PORT_GMAC_TYPE); - if(mode_tmp == PORT_WRAPPER_SGMII_FIBER) - { - _adpt_hppe_port_interface_mode_set(dev_id, port_id, - PORT_SGMII_FIBER); - } - else - { - _adpt_hppe_port_interface_mode_set(dev_id, port_id, - PHY_SGMII_BASET); - } - break; - case PORT_WRAPPER_SGMII_PLUS: - if (ssdk_port_feature_get(dev_id, port_id, PHY_F_QGMAC)) { - qca_hppe_port_mac_type_set(dev_id, port_id, - PORT_GMAC_TYPE); - } else { - qca_hppe_port_mac_type_set(dev_id, port_id, - PORT_XGMAC_TYPE); - } - _adpt_hppe_port_interface_mode_set(dev_id, port_id, PORT_SGMII_PLUS); - break; - case PORT_WRAPPER_USXGMII: - qca_hppe_port_mac_type_set(dev_id, port_id, PORT_XGMAC_TYPE); - _adpt_hppe_port_interface_mode_set(dev_id, port_id, PORT_USXGMII); - break; - case PORT_WRAPPER_10GBASE_R: - qca_hppe_port_mac_type_set(dev_id, port_id, PORT_XGMAC_TYPE); - _adpt_hppe_port_interface_mode_set(dev_id, port_id, PORT_10GBASE_R); - break; - default: - break; - } - } - - rv = _adpt_hppe_port_mux_set(dev_id, port_id,mode1, mode2); - - return rv; -} - -static sw_error_t -_adpt_hppe_instance0_mode_get(a_uint32_t dev_id, a_uint32_t *mode0) -{ - a_uint32_t port_id = 0; - - for(port_id = SSDK_PHYSICAL_PORT1; port_id <= SSDK_PHYSICAL_PORT5; port_id++) - { - if (A_TRUE != hsl_port_prop_check (dev_id, port_id, HSL_PP_EXCL_CPU)) - { - continue; - } - SSDK_DEBUG("port_id:%d, port_interface_mode:%d\n", port_id, - port_interface_mode[dev_id][port_id]); - if(port_interface_mode[dev_id][port_id] == PHY_PSGMII_BASET) - { - if(*mode0 != PORT_WRAPPER_MAX && *mode0 != PORT_WRAPPER_PSGMII) - { - SSDK_ERROR("when the port_interface_mode of port %d is %d, " - "mode0:%d cannot be supported\n", - port_id, port_interface_mode[dev_id][port_id], *mode0); - return SW_NOT_SUPPORTED; - } - *mode0 = PORT_WRAPPER_PSGMII; - } - - if(port_interface_mode[dev_id][port_id] == PHY_PSGMII_FIBER && - port_id == SSDK_PHYSICAL_PORT5) - { - *mode0 = PORT_WRAPPER_PSGMII_FIBER; - } - - if(port_interface_mode[dev_id][port_id] == PORT_QSGMII) - { - if((*mode0 != PORT_WRAPPER_MAX && *mode0 != PORT_WRAPPER_QSGMII) || - port_id == SSDK_PHYSICAL_PORT5) - { - SSDK_ERROR("when the port_interface_mode of port %d is %d, " - "mode0:%d cannot be supported\n", - port_id, port_interface_mode[dev_id][port_id], *mode0); - return SW_NOT_SUPPORTED; - } - *mode0 = PORT_WRAPPER_QSGMII; - } - - if(port_interface_mode[dev_id][port_id] == PHY_SGMII_BASET || - port_interface_mode[dev_id][port_id] == PORT_SGMII_FIBER) - { - if(*mode0 !=PORT_WRAPPER_MAX) - { - if(port_id != SSDK_PHYSICAL_PORT5) - { - SSDK_ERROR("when the port_interface_mode of port %d is %d, " - "mode0:%d cannot be supported\n", - port_id, port_interface_mode[dev_id][port_id], - *mode0); - return SW_NOT_SUPPORTED; - } - else - { - return SW_OK; - } - } - switch(port_id) - { - case SSDK_PHYSICAL_PORT1: - if(port_interface_mode[dev_id][port_id] == PORT_SGMII_FIBER) - { - *mode0 = PORT_WRAPPER_SGMII_FIBER; - } - else - { - *mode0 = PORT_WRAPPER_SGMII_CHANNEL0; - } - break; - case SSDK_PHYSICAL_PORT2: - *mode0 = PORT_WRAPPER_SGMII_CHANNEL1; - break; -#ifdef CPPE - case SSDK_PHYSICAL_PORT4: - if(adpt_hppe_chip_revision_get(dev_id) == CPPE_REVISION) - { - *mode0 = PORT_WRAPPER_SGMII_CHANNEL0; - } - break; -#endif - case SSDK_PHYSICAL_PORT5: - if(ssdk_dt_global_get_mac_mode(dev_id, - SSDK_UNIPHY_INSTANCE1) == PORT_WRAPPER_MAX) - { - *mode0 = PORT_WRAPPER_SGMII_CHANNEL4; - } - break; - default: - SSDK_ERROR("port %d doesn't support " - "port_interface_mode %d\n", - port_id, port_interface_mode[dev_id][port_id]); - return SW_NOT_SUPPORTED; - } - } - if(port_id != SSDK_PHYSICAL_PORT5 && - (port_interface_mode[dev_id][port_id] == PORT_SGMII_PLUS || - port_interface_mode[dev_id][port_id] ==PORT_USXGMII || - port_interface_mode[dev_id][port_id] == PORT_10GBASE_R)) - { -#ifdef CPPE - if(port_interface_mode[dev_id][port_id] == PORT_SGMII_PLUS - && adpt_hppe_chip_revision_get(dev_id) == CPPE_REVISION - && port_id == SSDK_PHYSICAL_PORT4) - { - *mode0 = PORT_WRAPPER_SGMII_PLUS; - continue; - } -#endif - SSDK_ERROR("port %d doesn't support port_interface_mode %d\n", - port_id, port_interface_mode[dev_id][port_id]); - return SW_NOT_SUPPORTED; - } - } - - return SW_OK; -} - -static sw_error_t -_adpt_hppe_instance1_mode_get(a_uint32_t dev_id, a_uint32_t port_id, a_uint32_t *mode) -{ - if ((A_TRUE != hsl_port_prop_check (dev_id, port_id, HSL_PP_EXCL_CPU)) || - A_TRUE == hsl_port_prop_check (dev_id, port_id, HSL_PP_INNER)) - { - return SW_OK; - } - SSDK_DEBUG("port_id:%x: %x\n", port_id, port_interface_mode[dev_id][port_id]); - switch(port_interface_mode[dev_id][port_id]) - { - case PHY_SGMII_BASET: - *mode = PORT_WRAPPER_SGMII_CHANNEL0; - break; - case PORT_SGMII_PLUS: - *mode = PORT_WRAPPER_SGMII_PLUS; - break; - case PORT_USXGMII: - *mode = PORT_WRAPPER_USXGMII; - break; - case PORT_10GBASE_R: - *mode = PORT_WRAPPER_10GBASE_R; - break; - case PORT_SGMII_FIBER: - *mode = PORT_WRAPPER_SGMII_FIBER; - break; - case PHY_PSGMII_BASET: - case PHY_PSGMII_FIBER: - if(port_id == SSDK_PHYSICAL_PORT6) - { - SSDK_ERROR("port %d doesn't support port_interface_mode %d\n", - port_id, port_interface_mode[dev_id][port_id]); - return SW_NOT_SUPPORTED; - } - *mode = PORT_INTERFACE_MODE_MAX; - break; - case PORT_INTERFACE_MODE_MAX: - break; - default: - SSDK_ERROR("port %d doesn't support port_interface_mode %d\n", - port_id, port_interface_mode[dev_id][port_id]); - return SW_NOT_SUPPORTED; - } - - return SW_OK; -} - -static sw_error_t -_adpt_hppe_instance_mode_get(a_uint32_t dev_id, a_uint32_t uniphy_index, - a_uint32_t *interface_mode) -{ - sw_error_t rv = SW_OK; - - switch(uniphy_index) - { - case SSDK_UNIPHY_INSTANCE0: - rv = _adpt_hppe_instance0_mode_get(dev_id, interface_mode); - SW_RTN_ON_ERROR(rv); - break; - case SSDK_UNIPHY_INSTANCE1: - rv =_adpt_hppe_instance1_mode_get(dev_id, SSDK_PHYSICAL_PORT5, - interface_mode); - SW_RTN_ON_ERROR(rv); - break; - case SSDK_UNIPHY_INSTANCE2: - rv =_adpt_hppe_instance1_mode_get(dev_id, SSDK_PHYSICAL_PORT6, - interface_mode); - SW_RTN_ON_ERROR(rv); - break; - default: - return SW_NOT_SUPPORTED; - } - - return rv; -} - -extern sw_error_t -adpt_hppe_uniphy_mode_set(a_uint32_t dev_id, a_uint32_t index, a_uint32_t mode); - -static sw_error_t -_adpt_hppe_port_interface_mode_phy_config(a_uint32_t dev_id, a_uint32_t port_id, - fal_port_interface_mode_t mode) -{ - sw_error_t rv; - a_uint32_t phy_id = 0; - hsl_phy_ops_t *phy_drv; - - ADPT_DEV_ID_CHECK(dev_id); - - if (A_TRUE != hsl_port_prop_check (dev_id, port_id, HSL_PP_PHY)) - { - SSDK_ERROR("port %d is not in bitmap\n", port_id); - return SW_BAD_PARAM; - } - SW_RTN_ON_NULL (phy_drv = hsl_phy_api_ops_get (dev_id, port_id)); - if (NULL == phy_drv->phy_interface_mode_set) - { - SSDK_ERROR("the phy_interface_mode_set api is null for port %d\n", - port_id); - return SW_NOT_SUPPORTED; - } - - rv = hsl_port_prop_get_phyid (dev_id, port_id, &phy_id); - SW_RTN_ON_ERROR (rv); - SSDK_DEBUG("port_id:%d, phy_id:%d, mode:%d\n", port_id, phy_id, mode); - rv = phy_drv->phy_interface_mode_set (dev_id, phy_id,mode); - - return rv; -} - -static sw_error_t _adpt_hppe_port_mac_set(a_uint32_t dev_id, a_uint32_t port_id, a_bool_t enable) -{ - sw_error_t rv = SW_OK; - - rv = adpt_hppe_port_txmac_status_set(dev_id, port_id, enable); - SW_RTN_ON_ERROR(rv); - rv = adpt_hppe_port_rxmac_status_set(dev_id, port_id, enable); - - return rv; -} - -static sw_error_t -_adpt_hppe_port_phyaddr_update(a_uint32_t dev_id, a_uint32_t port_id, - a_uint32_t mode) -{ - sw_error_t rv = SW_OK; - a_uint32_t phy_addr = 0, mode0 = PORT_WRAPPER_MAX; - ssdk_port_phyinfo *port_phyinfo = NULL; - - if(port_id != SSDK_PHYSICAL_PORT5) - { - return rv; - } - if(mode == PORT_WRAPPER_10GBASE_R) - { - port_phyinfo = ssdk_port_phyinfo_get(dev_id, port_id); - if (!port_phyinfo) - { - SSDK_ERROR("port_phyinfo of port%d is null\n", port_id); - return SW_FAIL; - } - phy_addr = port_phyinfo->phy_addr; - qca_ssdk_phy_address_set(dev_id, port_id, phy_addr); - hsl_port_phy_access_type_set(dev_id, port_id, PHY_I2C_ACCESS); - SSDK_DEBUG("port %x phy_addr is %x\n", port_id, phy_addr); - } - else - { - mode0 = ssdk_dt_global_get_mac_mode(dev_id, SSDK_UNIPHY_INSTANCE0); - if((mode0 == PORT_WRAPPER_PSGMII || mode0 == PORT_WRAPPER_PSGMII_FIBER) && - mode == PORT_WRAPPER_MAX) - { - rv = hsl_port_prop_get_phyid (dev_id, SSDK_PHYSICAL_PORT4, &phy_addr); - SW_RTN_ON_ERROR (rv); - phy_addr++; - qca_ssdk_phy_address_set(dev_id, port_id, phy_addr); - hsl_port_phy_access_type_set(dev_id, port_id, PHY_MDIO_ACCESS); - SSDK_DEBUG("port %x phy_addr is %x\n", port_id, phy_addr); - } - } - - return rv; -} - -static sw_error_t -_adpt_hppe_sfp_copper_phydriver_switch(a_uint32_t dev_id, a_uint32_t port_id, - a_uint32_t mode) -{ - sw_error_t rv = SW_OK; - - rv = _adpt_hppe_port_phyaddr_update(dev_id, port_id, mode); - SW_RTN_ON_ERROR(rv); - rv = hsl_phydriver_update(dev_id, port_id, mode); - - return rv; -} - -static sw_error_t -_adpt_hppe_port_phy_config(a_uint32_t dev_id, a_uint32_t index, a_uint32_t mode) -{ - sw_error_t rv = SW_OK; - - switch(mode) - { - case PORT_WRAPPER_PSGMII: - /*interface mode changed form psgmii+usxgmii to psgmii+10gbase-r+usxgmii, cannot - use port 5 to configure malibu*/ - rv = _adpt_hppe_port_interface_mode_phy_config(dev_id, - SSDK_PHYSICAL_PORT4, PHY_PSGMII_BASET); - break; - case PORT_WRAPPER_PSGMII_FIBER: - rv = _adpt_hppe_port_interface_mode_phy_config(dev_id, - SSDK_PHYSICAL_PORT4, PHY_PSGMII_FIBER); - break; - case PORT_WRAPPER_SGMII_CHANNEL4: - rv = _adpt_hppe_port_interface_mode_phy_config(dev_id, - SSDK_PHYSICAL_PORT5, PHY_SGMII_BASET); - break; - case PORT_WRAPPER_QSGMII: - rv = _adpt_hppe_port_interface_mode_phy_config(dev_id, - SSDK_PHYSICAL_PORT4, PORT_QSGMII); - break; - case PORT_WRAPPER_SGMII_CHANNEL0: -#ifdef CPPE - if(index == SSDK_UNIPHY_INSTANCE0 && - adpt_hppe_chip_revision_get(dev_id) == CPPE_REVISION && - (hsl_port_prop_check (dev_id, SSDK_PHYSICAL_PORT4, - HSL_PP_EXCL_CPU))) - { - rv = _adpt_hppe_port_interface_mode_phy_config(dev_id, - SSDK_PHYSICAL_PORT4, PHY_SGMII_BASET); - } -#endif - if(index == SSDK_UNIPHY_INSTANCE1) - { - rv = _adpt_hppe_port_interface_mode_phy_config(dev_id, - SSDK_PHYSICAL_PORT5, PHY_SGMII_BASET); - } - if(index == SSDK_UNIPHY_INSTANCE2) - { - rv = _adpt_hppe_port_interface_mode_phy_config(dev_id, - SSDK_PHYSICAL_PORT6, PHY_SGMII_BASET); - } - break; - case PORT_WRAPPER_USXGMII: - if(index == SSDK_UNIPHY_INSTANCE1) - { - rv = _adpt_hppe_port_interface_mode_phy_config(dev_id, - SSDK_PHYSICAL_PORT5, PORT_USXGMII); - } - if(index == SSDK_UNIPHY_INSTANCE2) - { - rv = _adpt_hppe_port_interface_mode_phy_config(dev_id, - SSDK_PHYSICAL_PORT6, PORT_USXGMII); - } - break; - case PORT_WRAPPER_SGMII_PLUS: -#ifdef CPPE - if(index == SSDK_UNIPHY_INSTANCE0 && - adpt_hppe_chip_revision_get(dev_id) == CPPE_REVISION) - { - rv = _adpt_hppe_port_interface_mode_phy_config(dev_id, - SSDK_PHYSICAL_PORT4, PORT_SGMII_PLUS); - } -#endif - if(index == SSDK_UNIPHY_INSTANCE1) - { - rv = _adpt_hppe_port_interface_mode_phy_config(dev_id, - SSDK_PHYSICAL_PORT5, PORT_SGMII_PLUS); - } - if(index == SSDK_UNIPHY_INSTANCE2) - { - rv = _adpt_hppe_port_interface_mode_phy_config(dev_id, - SSDK_PHYSICAL_PORT6, PORT_SGMII_PLUS); - } - break; - default: - break; - } - - return rv; -} - -static sw_error_t -adpt_hppe_port_mac_uniphy_phy_config(a_uint32_t dev_id, a_uint32_t mode_index, - a_uint32_t mode[], a_bool_t force_switch) -{ - sw_error_t rv = SW_OK; - a_uint32_t port_id = 0, port_id_from = 0, port_id_end = 0; - - if(mode_index == SSDK_UNIPHY_INSTANCE0) - { - switch (mode[SSDK_UNIPHY_INSTANCE0]) - { - case PORT_WRAPPER_PSGMII: - case PORT_WRAPPER_PSGMII_FIBER: - port_id_from = SSDK_PHYSICAL_PORT1; - /*qsgmii+10gbase-r+usxgmii --> psgmii+10gbase-r+usxgmii*/ - if(mode[SSDK_UNIPHY_INSTANCE1] != PORT_WRAPPER_MAX) - { - port_id_end = SSDK_PHYSICAL_PORT4; - } - else - { - port_id_end = SSDK_PHYSICAL_PORT5; - } - break; - case PORT_WRAPPER_QSGMII: - port_id_from = SSDK_PHYSICAL_PORT1; - port_id_end = SSDK_PHYSICAL_PORT4; - break; - case PORT_WRAPPER_SGMII0_RGMII4: - case PORT_WRAPPER_SGMII_CHANNEL0: - case PORT_WRAPPER_SGMII_FIBER: -#ifdef CPPE - case PORT_WRAPPER_SGMII_PLUS: - if(adpt_hppe_chip_revision_get(dev_id) == CPPE_REVISION) - { - a_uint32_t mode_tmp = 0; - mode_tmp = mode[SSDK_UNIPHY_INSTANCE0]; - if (mode_tmp == PORT_WRAPPER_SGMII_PLUS || - ((mode_tmp == PORT_WRAPPER_SGMII0_RGMII4 || - mode_tmp == PORT_WRAPPER_SGMII_CHANNEL0) && - (hsl_port_prop_check (dev_id, SSDK_PHYSICAL_PORT4, - HSL_PP_EXCL_CPU)))) - { - port_id_from = SSDK_PHYSICAL_PORT4; - port_id_end = SSDK_PHYSICAL_PORT4; - break; - } - } -#endif - port_id_from = SSDK_PHYSICAL_PORT1; - port_id_end = SSDK_PHYSICAL_PORT1; - break; - case PORT_WRAPPER_SGMII1_RGMII4: - case PORT_WRAPPER_SGMII_CHANNEL1: - port_id_from = SSDK_PHYSICAL_PORT2; - port_id_end = SSDK_PHYSICAL_PORT2; - break; - case PORT_WRAPPER_SGMII4_RGMII4: - case PORT_WRAPPER_SGMII_CHANNEL4: - port_id_from = SSDK_PHYSICAL_PORT5; - port_id_end = SSDK_PHYSICAL_PORT5; - break; - default: - SSDK_INFO ("uniphy %d interface mode is 0x%x\n", - mode_index, mode[SSDK_UNIPHY_INSTANCE0]); - return SW_OK; - } - } - else if(mode_index == SSDK_UNIPHY_INSTANCE1) - { - port_id_from = SSDK_PHYSICAL_PORT5; - port_id_end = SSDK_PHYSICAL_PORT5; - } - else if(mode_index == SSDK_UNIPHY_INSTANCE2) - { - port_id_from = SSDK_PHYSICAL_PORT6; - port_id_end = SSDK_PHYSICAL_PORT6; - } - else - { - return SW_NOT_SUPPORTED; - } - /*disable mac tx and rx for special ports*/ - for(port_id = port_id_from; port_id <= port_id_end; port_id++) - { - rv = _adpt_hppe_port_mac_set(dev_id, port_id, A_FALSE); - } - - /*configure the uniphy*/ - rv = adpt_hppe_uniphy_mode_set(dev_id, mode_index, mode[mode_index]); - SSDK_DEBUG("configure uniphy mode_index:%x, mode:%x, rv:%x\n", - mode_index, mode[mode_index], rv); - SW_RTN_ON_ERROR(rv); - - /*configure the mac*/ - for(port_id = port_id_from; port_id <= port_id_end; port_id++) - { - rv = adpt_hppe_port_mux_mac_type_set(dev_id, port_id, mode[SSDK_UNIPHY_INSTANCE0], - mode[SSDK_UNIPHY_INSTANCE1], mode[SSDK_UNIPHY_INSTANCE2]); - SSDK_DEBUG("configure mac, port_id is %x,mode0:%x,mode1:%x,mode2:%x, rv:%x\n", - port_id, mode[SSDK_UNIPHY_INSTANCE0], mode[SSDK_UNIPHY_INSTANCE1], - mode[SSDK_UNIPHY_INSTANCE2], rv); - SW_RTN_ON_ERROR(rv); - } - - /*configure the phy*/ - if(SSDK_PHYSICAL_PORT5 >= port_id_from && SSDK_PHYSICAL_PORT5 <= port_id_end) - { - rv = _adpt_hppe_sfp_copper_phydriver_switch(dev_id, SSDK_PHYSICAL_PORT5, - mode[SSDK_UNIPHY_INSTANCE1]); - } - SW_RTN_ON_ERROR(rv); - if (force_switch != A_FALSE) { - rv = _adpt_hppe_port_phy_config(dev_id, mode_index, mode[mode_index]); - SSDK_DEBUG("configure phy, mode_index:%x,interface_mode:%x, rv:%x\n", - mode_index, mode[mode_index], rv); - } - - /*init port status for special ports to triger polling*/ - for(port_id = port_id_from; port_id <= port_id_end; port_id++) - { - adpt_hppe_port_txfc_status_set(dev_id, port_id, A_FALSE); - adpt_hppe_port_rxfc_status_set(dev_id, port_id, A_FALSE); - qca_mac_port_status_init(dev_id, port_id); - } - - return rv; -} - -sw_error_t -_adpt_hppe_port_interface_mode_apply(a_uint32_t dev_id, a_bool_t force_switch) -{ - sw_error_t rv = SW_OK; - a_uint32_t mode_index = 0, mode_old[3] = {0}; - a_uint32_t mode_new[3] = {PORT_WRAPPER_MAX,PORT_WRAPPER_MAX,PORT_WRAPPER_MAX}; - - /*get three intances mode, include old mode and new mode*/ - for(mode_index = SSDK_UNIPHY_INSTANCE0; mode_index <= SSDK_UNIPHY_INSTANCE2; mode_index++) - { - mode_old[mode_index] = ssdk_dt_global_get_mac_mode(dev_id, mode_index); - if(mode_index == SSDK_UNIPHY_INSTANCE1 && - mode_new[SSDK_UNIPHY_INSTANCE0] == PORT_WRAPPER_SGMII_CHANNEL4) - { - mode_new[SSDK_UNIPHY_INSTANCE1] = PORT_WRAPPER_MAX; - } - else - { - rv = _adpt_hppe_instance_mode_get(dev_id, mode_index, &mode_new[mode_index]); - SW_RTN_ON_ERROR(rv); - } - } - SSDK_DEBUG("mode0_old: %x, mode1_old:%x, mode2_old:%x\n", - mode_old[0], mode_old[1], mode_old[2]); - SSDK_DEBUG("mode0_new: %x, mode1_new:%x, mode2_new:%x\n", - mode_new[0], mode_new[1], mode_new[2]); - /*set three new intances mode*/ - for(mode_index = SSDK_UNIPHY_INSTANCE0; mode_index <= SSDK_UNIPHY_INSTANCE2; mode_index++) - { - ssdk_dt_global_set_mac_mode(dev_id, mode_index, mode_new[mode_index]); - } - - for (mode_index = SSDK_UNIPHY_INSTANCE0; mode_index <= SSDK_UNIPHY_INSTANCE2; mode_index++) - { - ssdk_gcc_uniphy_sys_set(dev_id, mode_index, A_TRUE); - } - ssdk_uniphy_port5_clock_source_set(); - - /*configure the mode according to mode_new*/ - for(mode_index = SSDK_UNIPHY_INSTANCE0; mode_index <= SSDK_UNIPHY_INSTANCE2; mode_index++) - { - if(mode_new[mode_index] != mode_old[mode_index]) - { - SSDK_DEBUG("need to configure instance%x\n", mode_index); - rv = adpt_hppe_port_mac_uniphy_phy_config(dev_id, - mode_index, mode_new, force_switch); - if(rv) - { - SSDK_ERROR("config instance%x, rv:%x faild\n", mode_index,rv); - return rv; - } - } - if (mode_new[mode_index] == PORT_WRAPPER_MAX) { - ssdk_gcc_uniphy_sys_set(dev_id, mode_index, A_FALSE); - } - } - - return rv; -} -#ifndef IN_PORTCONTROL_MINI -sw_error_t -adpt_hppe_port_interface_mode_apply(a_uint32_t dev_id) -{ - struct qca_phy_priv *priv; - sw_error_t rv = SW_OK; - - ADPT_DEV_ID_CHECK(dev_id); - priv = ssdk_phy_priv_data_get(dev_id); - if (!priv) - { - return SW_FAIL; - } - - mutex_lock(&priv->mac_sw_sync_lock); - rv = _adpt_hppe_port_interface_mode_apply(dev_id, A_TRUE); - mutex_unlock(&priv->mac_sw_sync_lock); - - qca_mac_sw_sync_work_resume(priv); - - return rv; -} - -sw_error_t -adpt_hppe_port_mac_loopback_get(a_uint32_t dev_id, fal_port_t port_id, - a_bool_t * enable) -{ - sw_error_t rv = SW_OK; - a_uint32_t port_mac_type = 0; - - ADPT_DEV_ID_CHECK(dev_id); - ADPT_NULL_POINT_CHECK(enable); - - port_mac_type = qca_hppe_port_mac_type_get(dev_id, port_id); - if (port_mac_type == PORT_XGMAC_TYPE) - rv = _adpt_hppe_port_xgmac_loopback_get( dev_id, port_id, enable); - else if (port_mac_type == PORT_GMAC_TYPE) - rv = _adpt_hppe_port_gmac_loopback_get( dev_id, port_id, enable); - else - return SW_BAD_VALUE; - - return rv; -} - -sw_error_t -adpt_hppe_port_hibernate_get(a_uint32_t dev_id, fal_port_t port_id, - a_bool_t * enable) -{ - - sw_error_t rv = 0; - a_uint32_t phy_id = 0; - hsl_phy_ops_t *phy_drv; - - ADPT_DEV_ID_CHECK(dev_id); - ADPT_NULL_POINT_CHECK(enable); - - if (A_TRUE != hsl_port_prop_check (dev_id, port_id, HSL_PP_PHY)) - { - return SW_BAD_PARAM; - } - if (A_FALSE == _adpt_hppe_port_phy_connected (dev_id, port_id)) - return SW_NOT_SUPPORTED; - - SW_RTN_ON_NULL (phy_drv = hsl_phy_api_ops_get (dev_id, port_id)); - if (NULL == phy_drv->phy_hibernation_get) - return SW_NOT_SUPPORTED; - - rv = hsl_port_prop_get_phyid (dev_id, port_id, &phy_id); - SW_RTN_ON_ERROR (rv); - - rv = phy_drv->phy_hibernation_get (dev_id, phy_id, enable); - - return rv; - -} -#endif -sw_error_t -adpt_hppe_port_autoneg_adv_set(a_uint32_t dev_id, fal_port_t port_id, - a_uint32_t autoadv) -{ - sw_error_t rv = 0; - a_uint32_t phy_id; - hsl_phy_ops_t *phy_drv; - - ADPT_DEV_ID_CHECK(dev_id); - - if (A_TRUE != hsl_port_prop_check (dev_id, port_id, HSL_PP_PHY)) - { - return SW_BAD_PARAM; - } - if (A_FALSE == _adpt_hppe_port_phy_connected (dev_id, port_id)) - return SW_NOT_SUPPORTED; - - SW_RTN_ON_NULL (phy_drv = hsl_phy_api_ops_get (dev_id, port_id)); - if (NULL == phy_drv->phy_autoneg_adv_set) - return SW_NOT_SUPPORTED; - - rv = hsl_port_prop_get_phyid (dev_id, port_id, &phy_id); - SW_RTN_ON_ERROR (rv); - - rv = phy_drv->phy_autoneg_adv_set (dev_id, phy_id, autoadv); - SW_RTN_ON_ERROR (rv); -#if (LINUX_VERSION_CODE >= KERNEL_VERSION(5, 0, 0)) - rv = hsl_port_phydev_adv_update (dev_id, port_id, autoadv); - SW_RTN_ON_ERROR (rv); -#endif - - return SW_OK; - -} -#ifndef IN_PORTCONTROL_MINI -sw_error_t -adpt_hppe_port_remote_loopback_get(a_uint32_t dev_id, fal_port_t port_id, - a_bool_t * enable) -{ - - sw_error_t rv = 0; - a_uint32_t phy_id = 0; - hsl_phy_ops_t *phy_drv; - - ADPT_DEV_ID_CHECK(dev_id); - ADPT_NULL_POINT_CHECK(enable); - - if (A_TRUE != hsl_port_prop_check (dev_id, port_id, HSL_PP_PHY)) - { - return SW_BAD_PARAM; - } - if (A_FALSE == _adpt_hppe_port_phy_connected (dev_id, port_id)) - return SW_NOT_SUPPORTED; - - SW_RTN_ON_NULL (phy_drv = hsl_phy_api_ops_get (dev_id, port_id)); - if (NULL == phy_drv->phy_remote_loopback_get) - return SW_NOT_SUPPORTED; - - rv = hsl_port_prop_get_phyid (dev_id, port_id, &phy_id); - SW_RTN_ON_ERROR (rv); - - rv = phy_drv->phy_remote_loopback_get (dev_id, phy_id, enable); - - return rv; - -} - -sw_error_t -adpt_hppe_port_counter_show(a_uint32_t dev_id, fal_port_t port_id, - fal_port_counter_info_t * counter_info) -{ - - sw_error_t rv = 0; - a_uint32_t phy_id = 0; - hsl_phy_ops_t *phy_drv; - - ADPT_DEV_ID_CHECK(dev_id); - ADPT_NULL_POINT_CHECK(counter_info); - - if (A_TRUE != hsl_port_prop_check (dev_id, port_id, HSL_PP_PHY)) - { - return SW_BAD_PARAM; - } - if (A_FALSE == _adpt_hppe_port_phy_connected (dev_id, port_id)) - return SW_NOT_SUPPORTED; - - SW_RTN_ON_NULL (phy_drv = hsl_phy_api_ops_get (dev_id, port_id)); - if (NULL == phy_drv->phy_counter_show) - return SW_NOT_SUPPORTED; - - rv = hsl_port_prop_get_phyid (dev_id, port_id, &phy_id); - SW_RTN_ON_ERROR (rv); - - rv = phy_drv->phy_counter_show (dev_id, phy_id,counter_info); - - return rv; - -} -sw_error_t -adpt_hppe_port_mtu_get(a_uint32_t dev_id, fal_port_t port_id, - fal_mtu_ctrl_t *ctrl) -{ - sw_error_t rv = SW_OK; - union mru_mtu_ctrl_tbl_u mru_mtu_ctrl_tbl; - - memset(&mru_mtu_ctrl_tbl, 0, sizeof(mru_mtu_ctrl_tbl)); - ADPT_DEV_ID_CHECK(dev_id); - ADPT_NULL_POINT_CHECK(ctrl); - - rv = hppe_mru_mtu_ctrl_tbl_get(dev_id, port_id, &mru_mtu_ctrl_tbl); - - if( rv != SW_OK ) - return rv; - - ctrl->mtu_size = mru_mtu_ctrl_tbl.bf.mtu; - ctrl->action = (fal_fwd_cmd_t)mru_mtu_ctrl_tbl.bf.mtu_cmd; - - return SW_OK; -} - -#endif -sw_error_t -adpt_hppe_port_autoneg_enable(a_uint32_t dev_id, fal_port_t port_id) -{ - - sw_error_t rv = 0; - a_uint32_t phy_id; - hsl_phy_ops_t *phy_drv; - - ADPT_DEV_ID_CHECK(dev_id); - - if (A_TRUE != hsl_port_prop_check (dev_id, port_id, HSL_PP_PHY)) - { - return SW_BAD_PARAM; - } - if (A_FALSE == _adpt_hppe_port_phy_connected (dev_id, port_id)) - return SW_NOT_SUPPORTED; - - SW_RTN_ON_NULL (phy_drv = hsl_phy_api_ops_get (dev_id, port_id)); - if (NULL == phy_drv->phy_autoneg_enable_set) - return SW_NOT_SUPPORTED; - - rv = hsl_port_prop_get_phyid (dev_id, port_id, &phy_id); - SW_RTN_ON_ERROR (rv); - - rv = phy_drv->phy_autoneg_enable_set (dev_id, phy_id); - return rv; - -} - -#ifndef IN_PORTCONTROL_MINI -sw_error_t -adpt_ppe_port_mtu_get(a_uint32_t dev_id, fal_port_t port_id, - fal_mtu_ctrl_t *ctrl) -{ - a_uint32_t chip_ver = 0; - - ADPT_DEV_ID_CHECK(dev_id); - ADPT_NULL_POINT_CHECK(ctrl); - - chip_ver = adpt_hppe_chip_revision_get(dev_id); - if (chip_ver == CPPE_REVISION) { -#if defined(CPPE) - return adpt_cppe_port_mtu_get(dev_id, port_id, ctrl); -#endif - } else { - return adpt_hppe_port_mtu_get(dev_id, port_id, ctrl); - } - - return SW_NOT_SUPPORTED; -} -#endif - -sw_error_t -adpt_hppe_port_interface_mode_status_get(a_uint32_t dev_id, fal_port_t port_id, - fal_port_interface_mode_t * mode) -{ - - sw_error_t rv = SW_OK; - a_uint32_t phy_id = 0; - hsl_phy_ops_t *phy_drv; - - ADPT_DEV_ID_CHECK(dev_id); - ADPT_NULL_POINT_CHECK(mode); - - if (A_TRUE != hsl_port_prop_check (dev_id, port_id, HSL_PP_PHY)) - { - return SW_BAD_PARAM; - } - - /* for those ports without PHY device should be sfp port */ - if (A_FALSE == _adpt_hppe_port_phy_connected (dev_id, port_id)) { - rv = sfp_phy_interface_get_mode_status(dev_id, port_id, mode); - SW_RTN_ON_ERROR (rv); - } else { - SW_RTN_ON_NULL(phy_drv = hsl_phy_api_ops_get (dev_id, port_id)); - if (NULL == phy_drv->phy_interface_mode_status_get) - return SW_NOT_SUPPORTED; - - rv = hsl_port_prop_get_phyid (dev_id, port_id, &phy_id); - SW_RTN_ON_ERROR (rv); - - rv = phy_drv->phy_interface_mode_status_get (dev_id, phy_id,mode); - } - return rv; -} -#ifndef IN_PORTCONTROL_MINI -sw_error_t -adpt_hppe_port_reset(a_uint32_t dev_id, fal_port_t port_id) -{ - - sw_error_t rv; - a_uint32_t phy_id = 0; - hsl_phy_ops_t *phy_drv; - - ADPT_DEV_ID_CHECK(dev_id); - - if (A_TRUE != hsl_port_prop_check (dev_id, port_id, HSL_PP_PHY)) - { - return SW_BAD_PARAM; - } - if (A_FALSE == _adpt_hppe_port_phy_connected (dev_id, port_id)) - return SW_NOT_SUPPORTED; - - SW_RTN_ON_NULL (phy_drv = hsl_phy_api_ops_get (dev_id, port_id)); - if (NULL == phy_drv->phy_reset) - return SW_NOT_SUPPORTED; - - rv = hsl_port_prop_get_phyid (dev_id, port_id, &phy_id); - SW_RTN_ON_ERROR (rv); - - rv = phy_drv->phy_reset(dev_id, phy_id); - - return rv; - -} -#endif - -sw_error_t -adpt_hppe_port_flowctrl_set(a_uint32_t dev_id, fal_port_t port_id, - a_bool_t enable) -{ - sw_error_t rv = SW_OK; - struct qca_phy_priv *priv = ssdk_phy_priv_data_get(dev_id); - - if (!priv) - return SW_FAIL; - - if ((port_id < SSDK_PHYSICAL_PORT1) || (port_id > SSDK_PHYSICAL_PORT6)) - return SW_BAD_VALUE; -#if defined(CPPE) - if ((adpt_hppe_chip_revision_get(dev_id) == CPPE_REVISION) && - (port_id == SSDK_PHYSICAL_PORT6)) { - return adpt_cppe_switch_port_loopback_flowctrl_set(dev_id, - port_id, enable); - } -#endif - rv = adpt_hppe_port_txfc_status_set(dev_id, port_id, enable); - rv |= adpt_hppe_port_rxfc_status_set(dev_id, port_id, enable); - - if(rv != SW_OK) - return rv; - - priv->port_old_tx_flowctrl[port_id - 1] = enable; - priv->port_old_rx_flowctrl[port_id - 1] = enable; - - return SW_OK; -} -sw_error_t -adpt_hppe_port_speed_get(a_uint32_t dev_id, fal_port_t port_id, - fal_port_speed_t * pspeed) -{ - sw_error_t rv = 0; - a_uint32_t phy_id; - hsl_phy_ops_t *phy_drv; - struct port_phy_status phy_status = {0}; - - ADPT_DEV_ID_CHECK(dev_id); - ADPT_NULL_POINT_CHECK(pspeed); - - if (A_TRUE != hsl_port_prop_check (dev_id, port_id, HSL_PP_INCL_CPU)) - { - return SW_BAD_PARAM; - } - - /* for those ports without PHY device should be sfp port */ - if (A_FALSE == _adpt_hppe_port_phy_connected (dev_id, port_id)) - { - if (port_id == SSDK_PHYSICAL_PORT0) - *pspeed = FAL_SPEED_10000; - else { - rv = _adpt_phy_status_get_from_ppe(dev_id, - port_id, &phy_status); - SW_RTN_ON_ERROR (rv); - *pspeed= phy_status.speed; - } - } - else - { - SW_RTN_ON_NULL (phy_drv = hsl_phy_api_ops_get (dev_id, port_id)); - if (NULL == phy_drv->phy_speed_get) - return SW_NOT_SUPPORTED; - - rv = hsl_port_prop_get_phyid (dev_id, port_id, &phy_id); - SW_RTN_ON_ERROR (rv); - rv = phy_drv->phy_speed_get (dev_id, phy_id, pspeed); - SW_RTN_ON_ERROR (rv); - } - - return rv; -} -#ifndef IN_PORTCONTROL_MINI -sw_error_t -adpt_hppe_port_mdix_set(a_uint32_t dev_id, fal_port_t port_id, - fal_port_mdix_mode_t mode) -{ - - sw_error_t rv = 0; - a_uint32_t phy_id = 0; - hsl_phy_ops_t *phy_drv; - - ADPT_DEV_ID_CHECK(dev_id); - - if (A_TRUE != hsl_port_prop_check (dev_id, port_id, HSL_PP_PHY)) - { - return SW_BAD_PARAM; - } - if (A_FALSE == _adpt_hppe_port_phy_connected (dev_id, port_id)) - return SW_NOT_SUPPORTED; - - SW_RTN_ON_NULL (phy_drv = hsl_phy_api_ops_get (dev_id, port_id)); - if (NULL == phy_drv->phy_mdix_set) - return SW_NOT_SUPPORTED; - - rv = hsl_port_prop_get_phyid (dev_id, port_id, &phy_id); - SW_RTN_ON_ERROR (rv); - - rv = phy_drv->phy_mdix_set (dev_id, phy_id, mode); - - return rv; - -} -sw_error_t -adpt_hppe_port_wol_status_get(a_uint32_t dev_id, fal_port_t port_id, - a_bool_t * enable) -{ - - sw_error_t rv = 0; - a_uint32_t phy_id = 0; - hsl_phy_ops_t *phy_drv; - - ADPT_DEV_ID_CHECK(dev_id); - ADPT_NULL_POINT_CHECK(enable); - - if (A_TRUE != hsl_port_prop_check (dev_id, port_id, HSL_PP_PHY)) - { - return SW_BAD_PARAM; - } - if (A_FALSE == _adpt_hppe_port_phy_connected (dev_id, port_id)) - return SW_NOT_SUPPORTED; - - SW_RTN_ON_NULL (phy_drv = hsl_phy_api_ops_get (dev_id, port_id)); - if (NULL == phy_drv->phy_wol_status_get) - return SW_NOT_SUPPORTED; - - rv = hsl_port_prop_get_phyid (dev_id, port_id, &phy_id); - SW_RTN_ON_ERROR (rv); - - rv = phy_drv->phy_wol_status_get (dev_id, phy_id, enable); - - return rv; - -} - -sw_error_t -adpt_hppe_port_source_filter_get(a_uint32_t dev_id, - fal_port_t port_id, a_bool_t * enable) -{ - sw_error_t rv = SW_OK; - union port_in_forward_u port_in_forward = {0}; - - ADPT_DEV_ID_CHECK(dev_id); - - rv = hppe_port_in_forward_get(dev_id, port_id, &port_in_forward); - - if (rv != SW_OK) - return rv; - - if (port_in_forward.bf.source_filtering_bypass == A_TRUE) - *enable = A_FALSE; - else - *enable = A_TRUE; - - return SW_OK; -} - -sw_error_t -adpt_hppe_port_source_filter_set(a_uint32_t dev_id, - fal_port_t port_id, a_bool_t enable) -{ - union port_in_forward_u port_in_forward = {0}; - - ADPT_DEV_ID_CHECK(dev_id); - - if (enable == A_TRUE) - port_in_forward.bf.source_filtering_bypass = A_FALSE; - else - port_in_forward.bf.source_filtering_bypass = A_TRUE; - - return hppe_port_in_forward_set(dev_id, port_id, &port_in_forward); -} - -sw_error_t -adpt_ppe_port_source_filter_get(a_uint32_t dev_id, - fal_port_t port_id, a_bool_t * enable) -{ - ADPT_DEV_ID_CHECK(dev_id); -#ifdef CPPE - if (adpt_hppe_chip_revision_get(dev_id) == CPPE_REVISION) { - return adpt_cppe_port_source_filter_get(dev_id, port_id, enable); - } -#endif - return adpt_hppe_port_source_filter_get(dev_id, port_id, enable); -} - -sw_error_t -adpt_ppe_port_source_filter_set(a_uint32_t dev_id, - fal_port_t port_id, a_bool_t enable) - -{ - ADPT_DEV_ID_CHECK(dev_id); -#ifdef CPPE - if (adpt_hppe_chip_revision_get(dev_id) == CPPE_REVISION) { - return adpt_cppe_port_source_filter_set(dev_id, port_id, enable); - } -#endif - return adpt_hppe_port_source_filter_set(dev_id, port_id, enable); -} - -sw_error_t -adpt_ppe_port_source_filter_config_get(a_uint32_t dev_id, - fal_port_t port_id, fal_src_filter_config_t* src_filter_config) -{ - ADPT_DEV_ID_CHECK(dev_id); -#ifdef CPPE - if (adpt_hppe_chip_revision_get(dev_id) == CPPE_REVISION) { - return adpt_cppe_port_source_filter_config_get(dev_id, port_id, - src_filter_config); - } -#endif - return SW_NOT_SUPPORTED; -} - -sw_error_t -adpt_ppe_port_source_filter_config_set(a_uint32_t dev_id, - fal_port_t port_id, fal_src_filter_config_t *src_filter_config) - -{ - ADPT_DEV_ID_CHECK(dev_id); -#ifdef CPPE - if (adpt_hppe_chip_revision_get(dev_id) == CPPE_REVISION) { - return adpt_cppe_port_source_filter_config_set(dev_id, port_id, src_filter_config); - } -#endif - return SW_NOT_SUPPORTED; -} - -static sw_error_t -adpt_hppe_port_interface_3az_set(a_uint32_t dev_id, fal_port_t port_id, a_bool_t enable) -{ - sw_error_t rv = 0; - union lpi_enable_u lpi_enable = {0}; - union lpi_port_timer_u lpi_port_timer = {0}; - a_uint32_t phy_id = 0; - hsl_phy_ops_t *phy_drv; - - ADPT_DEV_ID_CHECK(dev_id); - - if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_PHY)) - { - return SW_BAD_PARAM; - } - if (A_FALSE == _adpt_hppe_port_phy_connected (dev_id, port_id)) - return SW_NOT_SUPPORTED; - - SW_RTN_ON_NULL(phy_drv = hsl_phy_api_ops_get(dev_id, port_id)); - if (NULL == phy_drv->phy_8023az_set) - return SW_NOT_SUPPORTED; - - rv = hsl_port_prop_get_phyid(dev_id, port_id, &phy_id); - SW_RTN_ON_ERROR (rv); - - rv = phy_drv->phy_8023az_set(dev_id, phy_id, enable); - SW_RTN_ON_ERROR (rv); - - hppe_lpi_enable_get(dev_id, port_id, &lpi_enable); - - lpi_enable.val &= ~(0x1 << (port_id - 1)); - lpi_enable.val |= (((a_uint32_t)enable) << (port_id - 1)); - hppe_lpi_enable_set(dev_id, port_id, &lpi_enable); - - lpi_port_timer.bf.lpi_port_wakeup_timer = LPI_WAKEUP_TIMER; - lpi_port_timer.bf.lpi_port_sleep_timer = LPI_SLEEP_TIMER; - hppe_lpi_timer_set(dev_id, port_id, &lpi_port_timer); - - return SW_OK; -} -static sw_error_t -adpt_hppe_port_interface_3az_get(a_uint32_t dev_id, fal_port_t port_id, a_bool_t *enable) -{ - sw_error_t rv = 0; - union lpi_enable_u lpi_enable = {0}; - a_uint32_t phy_id = 0; - hsl_phy_ops_t *phy_drv; - a_bool_t phy_status = 0, mac_status = 0; - - ADPT_DEV_ID_CHECK(dev_id); - ADPT_NULL_POINT_CHECK(enable); - - if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_PHY)) - { - return SW_BAD_PARAM; - } - if (A_FALSE == _adpt_hppe_port_phy_connected (dev_id, port_id)) - return SW_NOT_SUPPORTED; - - SW_RTN_ON_NULL (phy_drv =hsl_phy_api_ops_get (dev_id, port_id)); - if (NULL == phy_drv->phy_8023az_get) - return SW_NOT_SUPPORTED; - - rv = hsl_port_prop_get_phyid(dev_id, port_id, &phy_id); - SW_RTN_ON_ERROR (rv); - - rv = phy_drv->phy_8023az_get(dev_id, phy_id, &phy_status); - SW_RTN_ON_ERROR (rv); - - rv = hppe_lpi_enable_get(dev_id, port_id, &lpi_enable); - - if(((lpi_enable.val >> (port_id - 1)) & 0x1) == A_TRUE) - mac_status = A_TRUE; - else - mac_status = A_FALSE; - - *enable = (phy_status & mac_status); - - return SW_OK; -} - -sw_error_t -adpt_hppe_port_promisc_mode_get(a_uint32_t dev_id, fal_port_t port_id, a_bool_t *enable) -{ - sw_error_t rv = SW_OK; - union port_bridge_ctrl_u port_bridge_ctrl = {0}; - - ADPT_DEV_ID_CHECK(dev_id); - ADPT_NULL_POINT_CHECK(enable); - - rv = hppe_port_bridge_ctrl_get(dev_id, port_id, &port_bridge_ctrl); - - if( rv != SW_OK ) - return rv; - - *enable = port_bridge_ctrl.bf.promisc_en; - - return SW_OK; -} -#endif - -sw_error_t -adpt_hppe_port_promisc_mode_set(a_uint32_t dev_id, fal_port_t port_id, a_bool_t enable) -{ - sw_error_t rv = SW_OK; - union port_bridge_ctrl_u port_bridge_ctrl = {0}; - - ADPT_DEV_ID_CHECK(dev_id); - - rv = hppe_port_bridge_ctrl_get(dev_id, port_id, &port_bridge_ctrl); - - if( rv != SW_OK ) - return rv; - - port_bridge_ctrl.bf.promisc_en = enable; - - return hppe_port_bridge_ctrl_set(dev_id, port_id, &port_bridge_ctrl); -} - -static sw_error_t -adpt_hppe_port_bridge_txmac_set(a_uint32_t dev_id, fal_port_t port_id, a_bool_t enable) -{ - sw_error_t rv = SW_OK; - union port_bridge_ctrl_u port_bridge_ctrl = {0}; - - ADPT_DEV_ID_CHECK(dev_id); - - rv = hppe_port_bridge_ctrl_get(dev_id, port_id, &port_bridge_ctrl); - - if( rv != SW_OK ) - return rv; - - if(enable == A_TRUE) - port_bridge_ctrl.bf.txmac_en= 1; - else - port_bridge_ctrl.bf.txmac_en= 0; - - return hppe_port_bridge_ctrl_set(dev_id, port_id, &port_bridge_ctrl); -} - -sw_error_t -adpt_hppe_port_mux_set(a_uint32_t dev_id, fal_port_t port_id, a_uint32_t port_type) -{ - sw_error_t rv = SW_OK; - union port_mux_ctrl_u port_mux_ctrl; - a_uint32_t mode, mode1; - - memset(&port_mux_ctrl, 0, sizeof(port_mux_ctrl)); - ADPT_DEV_ID_CHECK(dev_id); - - rv = hppe_port_mux_ctrl_get(dev_id, &port_mux_ctrl); - port_mux_ctrl.bf.port4_pcs_sel = 1; - - if (port_id == HPPE_MUX_PORT1) - { - if (port_type == PORT_GMAC_TYPE) - { - mode = ssdk_dt_global_get_mac_mode(dev_id, SSDK_UNIPHY_INSTANCE0); - mode1 = ssdk_dt_global_get_mac_mode(dev_id, SSDK_UNIPHY_INSTANCE1); - if ((((mode == PORT_WRAPPER_PSGMII) || - (mode == PORT_WRAPPER_PSGMII_FIBER)) && - (mode1 == PORT_WRAPPER_MAX)) || - ((mode == PORT_WRAPPER_SGMII4_RGMII4) && (mode1 == PORT_WRAPPER_MAX))) - { - port_mux_ctrl.bf.port5_pcs_sel = 1; - port_mux_ctrl.bf.port5_gmac_sel = 1; - } - else if (mode1 == PORT_WRAPPER_SGMII0_RGMII4 || - mode1 == PORT_WRAPPER_SGMII_CHANNEL0 || - mode1 == PORT_WRAPPER_SGMII_FIBER) - { - port_mux_ctrl.bf.port5_pcs_sel = 2; - port_mux_ctrl.bf.port5_gmac_sel = 1; - } - } - else if (port_type == PORT_XGMAC_TYPE) - { - port_mux_ctrl.bf.port5_pcs_sel = 2; - port_mux_ctrl.bf.port5_gmac_sel = 0; - } - } - else if (port_id == HPPE_MUX_PORT2) - { - if (port_type == PORT_GMAC_TYPE) - { - port_mux_ctrl.bf.port6_pcs_sel = 1; - port_mux_ctrl.bf.port6_gmac_sel = 1; - } - else if (port_type == PORT_XGMAC_TYPE) - { - port_mux_ctrl.bf.port6_pcs_sel = 1; - port_mux_ctrl.bf.port6_gmac_sel = 0; - } - } - else - { - return SW_OK; - } - rv = hppe_port_mux_ctrl_set(dev_id, &port_mux_ctrl); - - return rv; -} - -static sw_error_t -adpt_hppe_port_flowctrl_forcemode_set(a_uint32_t dev_id, - fal_port_t port_id, a_bool_t enable) -{ - sw_error_t rv = SW_OK; - struct qca_phy_priv *priv = ssdk_phy_priv_data_get(dev_id); - - ADPT_DEV_ID_CHECK(dev_id); - - if (!priv) - return SW_FAIL; - - if ((port_id < SSDK_PHYSICAL_PORT1) || (port_id > SSDK_PHYSICAL_PORT6)) - return SW_BAD_VALUE; - - priv->port_tx_flowctrl_forcemode[port_id - 1] = enable; - priv->port_rx_flowctrl_forcemode[port_id - 1] = enable; - - return rv; -} -#ifndef IN_PORTCONTROL_MINI -static sw_error_t -adpt_hppe_port_flowctrl_forcemode_get(a_uint32_t dev_id, - fal_port_t port_id, a_bool_t *enable) -{ - sw_error_t rv = SW_OK; - struct qca_phy_priv *priv = ssdk_phy_priv_data_get(dev_id); - - - ADPT_DEV_ID_CHECK(dev_id); - ADPT_NULL_POINT_CHECK(enable); - - if ((port_id < SSDK_PHYSICAL_PORT1) || (port_id > SSDK_PHYSICAL_PORT6)) - return SW_BAD_VALUE; - - if (!priv) - return SW_FAIL; - - *enable = (priv->port_tx_flowctrl_forcemode[port_id - 1] & - priv->port_rx_flowctrl_forcemode[port_id - 1]); - - return rv; -} -#endif -static a_uint32_t port_lpi_sleep_timer[SW_MAX_NR_DEV][SSDK_PHYSICAL_PORT6] = { - {218, 218, 218, 218, 218, 218}, - {218, 218, 218, 218, 218, 218}, - {218, 218, 218, 218, 218, 218}, -}; /* unit is us*/ -static a_uint32_t port_lpi_wakeup_timer[SW_MAX_NR_DEV][SSDK_PHYSICAL_PORT6] = { - {27, 27, 27, 27, 27, 27}, - {27, 27, 27, 27, 27, 27}, - {27, 27, 27, 27, 27, 27}, -}; /* unit is us*/ -static sw_error_t -adpt_hppe_port_interface_eee_cfg_set(a_uint32_t dev_id, fal_port_t port_id, - fal_port_eee_cfg_t *port_eee_cfg) -{ - sw_error_t rv = 0; - union lpi_enable_u lpi_enable = {0}; - union lpi_port_timer_u lpi_port_timer = {0}; - a_uint32_t phy_id = 0; - a_uint32_t adv, enable; - hsl_phy_ops_t *phy_drv; - - ADPT_DEV_ID_CHECK(dev_id); - - if ((port_id < SSDK_PHYSICAL_PORT1) || (port_id > SSDK_PHYSICAL_PORT6)) { - return SW_BAD_PARAM; - } - if (port_eee_cfg->enable) { - adv = port_eee_cfg->advertisement; - } else { - adv = 0; - } - if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_PHY)) { - return SW_BAD_PARAM; - } - if (A_FALSE == _adpt_hppe_port_phy_connected (dev_id, port_id)) { - return SW_NOT_SUPPORTED; - } - - SW_RTN_ON_NULL(phy_drv = hsl_phy_api_ops_get(dev_id, port_id)); - if (NULL == phy_drv->phy_eee_adv_set) { - return SW_NOT_SUPPORTED; - } - - rv = hsl_port_prop_get_phyid(dev_id, port_id, &phy_id); - SW_RTN_ON_ERROR (rv); - - rv = phy_drv->phy_eee_adv_set(dev_id, phy_id, adv); - SW_RTN_ON_ERROR (rv); - - hppe_lpi_enable_get(dev_id, port_id, &lpi_enable); - - enable = port_eee_cfg->lpi_tx_enable; - lpi_enable.val &= ~(0x1 << (port_id - 1)); - lpi_enable.val |= (enable << (port_id - 1)); - hppe_lpi_enable_set(dev_id, port_id, &lpi_enable); - - lpi_port_timer.bf.lpi_port_wakeup_timer = - (port_eee_cfg->lpi_wakeup_timer * LPI_EEE_TIMER_FREQUENCY) /LPI_EEE_TIMER_UNIT; - lpi_port_timer.bf.lpi_port_sleep_timer = - (port_eee_cfg->lpi_sleep_timer * LPI_EEE_TIMER_FREQUENCY) /LPI_EEE_TIMER_UNIT; - rv = hppe_lpi_timer_set(dev_id, port_id, &lpi_port_timer); - SW_RTN_ON_ERROR (rv); - port_lpi_wakeup_timer[dev_id][port_id - 1] = port_eee_cfg->lpi_wakeup_timer; - port_lpi_sleep_timer[dev_id][port_id - 1] = port_eee_cfg->lpi_sleep_timer; - - return rv; -} -static sw_error_t -adpt_hppe_port_interface_eee_cfg_get(a_uint32_t dev_id, fal_port_t port_id, - fal_port_eee_cfg_t *port_eee_cfg) -{ - sw_error_t rv = 0; - union lpi_enable_u lpi_enable = {0}; - a_uint32_t phy_id = 0; - hsl_phy_ops_t *phy_drv; - a_uint32_t adv, lp_adv, cap, status; - - if ((port_id < SSDK_PHYSICAL_PORT1) || (port_id > SSDK_PHYSICAL_PORT6)) { - return SW_BAD_PARAM; - } - - ADPT_DEV_ID_CHECK(dev_id); - ADPT_NULL_POINT_CHECK(port_eee_cfg); - memset(port_eee_cfg, 0, sizeof(*port_eee_cfg)); - - if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_PHY)) { - return SW_BAD_PARAM; - } - if (A_FALSE == _adpt_hppe_port_phy_connected (dev_id, port_id)) { - return SW_NOT_SUPPORTED; - } - - SW_RTN_ON_NULL (phy_drv =hsl_phy_api_ops_get (dev_id, port_id)); - if ((NULL == phy_drv->phy_eee_adv_get) || (NULL == phy_drv->phy_eee_partner_adv_get) || - (NULL == phy_drv->phy_eee_cap_get) || (NULL == phy_drv->phy_eee_status_get)) { - return SW_NOT_SUPPORTED; - } - - rv = hsl_port_prop_get_phyid(dev_id, port_id, &phy_id); - SW_RTN_ON_ERROR (rv); - - rv = phy_drv->phy_eee_adv_get(dev_id, phy_id, &adv); - SW_RTN_ON_ERROR (rv); - port_eee_cfg->advertisement = adv; - rv = phy_drv->phy_eee_partner_adv_get(dev_id, phy_id, &lp_adv); - SW_RTN_ON_ERROR (rv); - port_eee_cfg->link_partner_advertisement = lp_adv; - rv = phy_drv->phy_eee_cap_get(dev_id, phy_id, &cap); - SW_RTN_ON_ERROR (rv); - port_eee_cfg->capability = cap; - rv = phy_drv->phy_eee_status_get(dev_id, phy_id, &status); - SW_RTN_ON_ERROR (rv); - port_eee_cfg->eee_status = status; - - if (port_eee_cfg->advertisement) { - port_eee_cfg->enable = A_TRUE; - } else { - port_eee_cfg->enable = A_FALSE; - } - rv = hppe_lpi_enable_get(dev_id, port_id, &lpi_enable); - SW_RTN_ON_ERROR (rv); - - if(((lpi_enable.val >> (port_id - 1)) & 0x1) == A_TRUE) { - port_eee_cfg->lpi_tx_enable = A_TRUE; - } else { - port_eee_cfg->lpi_tx_enable = A_FALSE; - } - port_eee_cfg->lpi_wakeup_timer = port_lpi_wakeup_timer[dev_id][port_id - 1]; - port_eee_cfg->lpi_sleep_timer = port_lpi_sleep_timer[dev_id][port_id - 1]; - - return rv; -} - -static sw_error_t -adpt_hppe_port_phy_status_get(a_uint32_t dev_id, a_uint32_t port_id, - struct port_phy_status *phy_status) -{ - sw_error_t rv = 0; - a_uint32_t phy_id; - hsl_phy_ops_t *phy_drv; - - ADPT_DEV_ID_CHECK(dev_id); - ADPT_NULL_POINT_CHECK(phy_status); - - /* for those ports without PHY device should be sfp port or a internal port*/ - if (A_FALSE == _adpt_hppe_port_phy_connected (dev_id, port_id)) { - if (port_id != SSDK_PHYSICAL_PORT0) { - rv = _adpt_phy_status_get_from_ppe(dev_id, - port_id, phy_status); - SW_RTN_ON_ERROR (rv); - } else { - return SW_NOT_SUPPORTED; - } - } else { - SW_RTN_ON_NULL (phy_drv = hsl_phy_api_ops_get (dev_id, port_id)); - if (NULL == phy_drv->phy_get_status) - return SW_NOT_SUPPORTED; - - rv = hsl_port_prop_get_phyid (dev_id, port_id, &phy_id); - SW_RTN_ON_ERROR (rv); - rv = phy_drv->phy_get_status (dev_id, phy_id, phy_status); - SW_RTN_ON_ERROR (rv); - } - - return rv; - -} -static void -adpt_hppe_uniphy_psgmii_port_reset(a_uint32_t dev_id, a_uint32_t uniphy_index, - a_uint32_t port_id) -{ - union uniphy_channel0_input_output_4_u uniphy_channel0_input_output_4; - union uniphy_channel1_input_output_4_u uniphy_channel1_input_output_4; - union uniphy_channel2_input_output_4_u uniphy_channel2_input_output_4; - union uniphy_channel3_input_output_4_u uniphy_channel3_input_output_4; - union uniphy_channel4_input_output_4_u uniphy_channel4_input_output_4; - - memset(&uniphy_channel0_input_output_4, 0, sizeof(uniphy_channel0_input_output_4)); - memset(&uniphy_channel1_input_output_4, 0, sizeof(uniphy_channel1_input_output_4)); - memset(&uniphy_channel2_input_output_4, 0, sizeof(uniphy_channel2_input_output_4)); - memset(&uniphy_channel3_input_output_4, 0, sizeof(uniphy_channel3_input_output_4)); - memset(&uniphy_channel4_input_output_4, 0, sizeof(uniphy_channel4_input_output_4)); - - if (port_id == SSDK_PHYSICAL_PORT1) - { - hppe_uniphy_channel0_input_output_4_get(dev_id, uniphy_index, - &uniphy_channel0_input_output_4); - uniphy_channel0_input_output_4.bf.newaddedfromhere_ch0_adp_sw_rstn = 0; - hppe_uniphy_channel0_input_output_4_set(dev_id, uniphy_index, - &uniphy_channel0_input_output_4); - uniphy_channel0_input_output_4.bf.newaddedfromhere_ch0_adp_sw_rstn = 1; - hppe_uniphy_channel0_input_output_4_set(dev_id, uniphy_index, - &uniphy_channel0_input_output_4); - } - else if (port_id == SSDK_PHYSICAL_PORT2) - { - hppe_uniphy_channel1_input_output_4_get(dev_id, uniphy_index, - &uniphy_channel1_input_output_4); - uniphy_channel1_input_output_4.bf.newaddedfromhere_ch1_adp_sw_rstn = 0; - hppe_uniphy_channel1_input_output_4_set(dev_id, uniphy_index, - &uniphy_channel1_input_output_4); - uniphy_channel1_input_output_4.bf.newaddedfromhere_ch1_adp_sw_rstn = 1; - hppe_uniphy_channel1_input_output_4_set(dev_id, uniphy_index, - &uniphy_channel1_input_output_4); - } - else if (port_id == SSDK_PHYSICAL_PORT3) - { - hppe_uniphy_channel2_input_output_4_get(dev_id, uniphy_index, - &uniphy_channel2_input_output_4); - uniphy_channel2_input_output_4.bf.newaddedfromhere_ch2_adp_sw_rstn = 0; - hppe_uniphy_channel2_input_output_4_set(dev_id, uniphy_index, - &uniphy_channel2_input_output_4); - uniphy_channel2_input_output_4.bf.newaddedfromhere_ch2_adp_sw_rstn = 1; - hppe_uniphy_channel2_input_output_4_set(dev_id, uniphy_index, - &uniphy_channel2_input_output_4); - } - else if (port_id == SSDK_PHYSICAL_PORT4) - { - hppe_uniphy_channel3_input_output_4_get(dev_id, uniphy_index, - &uniphy_channel3_input_output_4); - uniphy_channel3_input_output_4.bf.newaddedfromhere_ch3_adp_sw_rstn = 0; - hppe_uniphy_channel3_input_output_4_set(dev_id, uniphy_index, - &uniphy_channel3_input_output_4); - uniphy_channel3_input_output_4.bf.newaddedfromhere_ch3_adp_sw_rstn = 1; - hppe_uniphy_channel3_input_output_4_set(dev_id, uniphy_index, - &uniphy_channel3_input_output_4); - } - else if (port_id == SSDK_PHYSICAL_PORT5) - { - hppe_uniphy_channel4_input_output_4_get(dev_id, uniphy_index, - &uniphy_channel4_input_output_4); - uniphy_channel4_input_output_4.bf.newaddedfromhere_ch4_adp_sw_rstn = 0; - hppe_uniphy_channel4_input_output_4_set(dev_id, uniphy_index, - &uniphy_channel4_input_output_4); - uniphy_channel4_input_output_4.bf.newaddedfromhere_ch4_adp_sw_rstn = 1; - hppe_uniphy_channel4_input_output_4_set(dev_id, uniphy_index, - &uniphy_channel4_input_output_4); - } - - return; -} -static void -adpt_hppe_uniphy_usxgmii_port_reset(a_uint32_t dev_id, a_uint32_t uniphy_index, - a_uint32_t port_id) -{ - union vr_xs_pcs_dig_ctrl1_u vr_xs_pcs_dig_ctrl1; - - memset(&vr_xs_pcs_dig_ctrl1, 0, sizeof(vr_xs_pcs_dig_ctrl1)); - - hppe_vr_xs_pcs_dig_ctrl1_get(dev_id, uniphy_index, &vr_xs_pcs_dig_ctrl1); - vr_xs_pcs_dig_ctrl1.bf.usra_rst = 1; - hppe_vr_xs_pcs_dig_ctrl1_set(dev_id, uniphy_index, &vr_xs_pcs_dig_ctrl1); - - return; -} - -static void -adpt_hppe_uniphy_port_adapter_reset(a_uint32_t dev_id, a_uint32_t port_id) -{ - a_uint32_t uniphy_index, mode, mode1; -#if defined(CPPE) - a_uint32_t channel_id = 0; -#endif - - if (port_id < HPPE_MUX_PORT1) - { - uniphy_index = SSDK_UNIPHY_INSTANCE0; -#if defined(CPPE) - adpt_cppe_port_to_channel_convert(dev_id, port_id, - &channel_id); - port_id = channel_id; -#endif - adpt_hppe_uniphy_psgmii_port_reset(dev_id, uniphy_index, - port_id); - } - else - { - if (port_id == HPPE_MUX_PORT1) - { - mode = ssdk_dt_global_get_mac_mode(dev_id, SSDK_UNIPHY_INSTANCE0); - mode1 = ssdk_dt_global_get_mac_mode(dev_id, SSDK_UNIPHY_INSTANCE1); - if ((((mode == PORT_WRAPPER_PSGMII) || - (mode == PORT_WRAPPER_PSGMII_FIBER)) && - (mode1 == PORT_WRAPPER_MAX)) || - ((mode == PORT_WRAPPER_SGMII4_RGMII4) && (mode1 == PORT_WRAPPER_MAX))) - { - uniphy_index = SSDK_UNIPHY_INSTANCE0; - adpt_hppe_uniphy_psgmii_port_reset(dev_id, uniphy_index, - port_id); - return; - } - else - uniphy_index = SSDK_UNIPHY_INSTANCE1; - } - else - uniphy_index = SSDK_UNIPHY_INSTANCE2; - - mode = ssdk_dt_global_get_mac_mode(dev_id, uniphy_index); - - if ((mode == PORT_WRAPPER_SGMII_PLUS) || (mode == PORT_WRAPPER_SGMII0_RGMII4) - || (mode == PORT_WRAPPER_SGMII_CHANNEL0) - || (mode == PORT_WRAPPER_SGMII_FIBER)) - { - /* only reset channel 0 */ - adpt_hppe_uniphy_psgmii_port_reset(dev_id, uniphy_index, 1); - } - else if (mode == PORT_WRAPPER_USXGMII) - { - adpt_hppe_uniphy_usxgmii_port_reset(dev_id, uniphy_index, - port_id); - } - } - - return; -} -static void -adpt_hppe_uniphy_usxgmii_speed_set(a_uint32_t dev_id, a_uint32_t uniphy_index, - fal_port_speed_t speed) -{ - union sr_mii_ctrl_u sr_mii_ctrl; - memset(&sr_mii_ctrl, 0, sizeof(sr_mii_ctrl)); - - hppe_sr_mii_ctrl_get(0, uniphy_index, &sr_mii_ctrl); - sr_mii_ctrl.bf.duplex_mode = 1; - if (speed == FAL_SPEED_10) - { - sr_mii_ctrl.bf.ss5 = 0; - sr_mii_ctrl.bf.ss6 = 0; - sr_mii_ctrl.bf.ss13 = 0; - } - else if (speed == FAL_SPEED_100) - { - sr_mii_ctrl.bf.ss5 = 0; - sr_mii_ctrl.bf.ss6 = 0; - sr_mii_ctrl.bf.ss13 = 1; - } - else if (speed == FAL_SPEED_1000) - { - sr_mii_ctrl.bf.ss5 = 0; - sr_mii_ctrl.bf.ss6 = 1; - sr_mii_ctrl.bf.ss13 = 0; - } - else if (speed == FAL_SPEED_10000) - { - sr_mii_ctrl.bf.ss5 = 0; - sr_mii_ctrl.bf.ss6 = 1; - sr_mii_ctrl.bf.ss13 = 1; - } - else if (speed == FAL_SPEED_2500) - { - sr_mii_ctrl.bf.ss5 = 1; - sr_mii_ctrl.bf.ss6 = 0; - sr_mii_ctrl.bf.ss13 = 0; - } - else if (speed == FAL_SPEED_5000) - { - sr_mii_ctrl.bf.ss5 = 1; - sr_mii_ctrl.bf.ss6 = 0; - sr_mii_ctrl.bf.ss13 = 1; - } - hppe_sr_mii_ctrl_set(0, uniphy_index, &sr_mii_ctrl); - - return; -} -static void -adpt_hppe_uniphy_usxgmii_duplex_set(a_uint32_t dev_id, a_uint32_t uniphy_index, - fal_port_duplex_t duplex) -{ - union sr_mii_ctrl_u sr_mii_ctrl; - memset(&sr_mii_ctrl, 0, sizeof(sr_mii_ctrl)); - - hppe_sr_mii_ctrl_get(dev_id, uniphy_index, &sr_mii_ctrl); - - if (duplex == FAL_FULL_DUPLEX) - sr_mii_ctrl.bf.duplex_mode = 1; - else - sr_mii_ctrl.bf.duplex_mode = 0; - - hppe_sr_mii_ctrl_set(dev_id, uniphy_index, &sr_mii_ctrl); - - return; -} -sw_error_t -adpt_hppe_uniphy_usxgmii_autoneg_completed(a_uint32_t dev_id, - a_uint32_t uniphy_index) -{ - a_uint32_t autoneg_complete = 0, retries = 100; - union vr_mii_an_intr_sts_u vr_mii_an_intr_sts; - - memset(&vr_mii_an_intr_sts, 0, sizeof(vr_mii_an_intr_sts)); - - // swith uniphy xpcs auto-neg complete and clear interrupt - while (autoneg_complete != 0x1) { - mdelay(1); - if (retries-- == 0) - { - printk("uniphy autoneg time out!\n"); - return SW_TIMEOUT; - } - hppe_vr_mii_an_intr_sts_get(dev_id, uniphy_index, &vr_mii_an_intr_sts); - autoneg_complete = vr_mii_an_intr_sts.bf.cl37_ancmplt_intr; - } - - vr_mii_an_intr_sts.bf.cl37_ancmplt_intr = 0; - hppe_vr_mii_an_intr_sts_set(dev_id, uniphy_index, &vr_mii_an_intr_sts); - - return SW_OK; -} -static void -adpt_hppe_uniphy_speed_set(a_uint32_t dev_id, a_uint32_t port_id, fal_port_speed_t speed) -{ - a_uint32_t uniphy_index = 0, mode = 0; - - if (port_id == HPPE_MUX_PORT1) - uniphy_index = SSDK_UNIPHY_INSTANCE1; - else if (port_id == HPPE_MUX_PORT2) - uniphy_index = SSDK_UNIPHY_INSTANCE2; - - mode = ssdk_dt_global_get_mac_mode(dev_id, uniphy_index); - if (mode == PORT_WRAPPER_USXGMII) - { - /* adpt_hppe_uniphy_usxgmii_autoneg_completed(dev_id,uniphy_index); */ - /* configure xpcs speed at usxgmii mode */ - adpt_hppe_uniphy_usxgmii_speed_set(dev_id, uniphy_index, speed); - } - - return; -} -static void -adpt_hppe_uniphy_duplex_set(a_uint32_t dev_id, a_uint32_t port_id, fal_port_duplex_t duplex) -{ - a_uint32_t uniphy_index = 0, mode = 0; - - if (port_id == HPPE_MUX_PORT1) - uniphy_index = SSDK_UNIPHY_INSTANCE1; - else if (port_id == HPPE_MUX_PORT2) - uniphy_index = SSDK_UNIPHY_INSTANCE2; - - mode = ssdk_dt_global_get_mac_mode(dev_id, uniphy_index); - if (mode == PORT_WRAPPER_USXGMII) - { - /* adpt_hppe_uniphy_usxgmii_autoneg_completed(0,uniphy_index); */ - /* configure xpcs duplex at usxgmii mode */ - adpt_hppe_uniphy_usxgmii_duplex_set(dev_id, uniphy_index, duplex); - } - - return; -} -static void -adpt_hppe_uniphy_autoneg_status_check(a_uint32_t dev_id, a_uint32_t port_id) -{ - a_uint32_t uniphy_index = 0, mode = 0; - - if (port_id == HPPE_MUX_PORT1) - uniphy_index = SSDK_UNIPHY_INSTANCE1; - else if (port_id == HPPE_MUX_PORT2) - uniphy_index = SSDK_UNIPHY_INSTANCE2; - - mode = ssdk_dt_global_get_mac_mode(dev_id, uniphy_index); - if (mode == PORT_WRAPPER_USXGMII) - { - adpt_hppe_uniphy_usxgmii_autoneg_completed(dev_id,uniphy_index);; - } - return; -} - -static void -adpt_hppe_sgmii_speed_clock_set( - a_uint32_t dev_id, - a_uint32_t port_id, - fal_port_speed_t phy_speed) -{ - switch (phy_speed) { - case FAL_SPEED_10: - ssdk_port_speed_clock_set(dev_id, - port_id, SGMII_SPEED_10M_CLK); - break; - case FAL_SPEED_100: - ssdk_port_speed_clock_set(dev_id, - port_id, SGMII_SPEED_100M_CLK); - break; - case FAL_SPEED_1000: - ssdk_port_speed_clock_set(dev_id, - port_id, SGMII_SPEED_1000M_CLK); - break; - default: - break; - } -} -static void -adpt_hppe_pqsgmii_speed_clock_set( - a_uint32_t dev_id, - a_uint32_t port_id, - fal_port_speed_t phy_speed) -{ - switch (phy_speed) { - case FAL_SPEED_10: - ssdk_port_speed_clock_set(dev_id, - port_id, PQSGMII_SPEED_10M_CLK); - break; - case FAL_SPEED_100: - ssdk_port_speed_clock_set(dev_id, - port_id, PQSGMII_SPEED_100M_CLK); - break; - case FAL_SPEED_1000: - ssdk_port_speed_clock_set(dev_id, - port_id, PQSGMII_SPEED_1000M_CLK); - break; - default: - break; - } -} - -static void -adpt_hppe_usxgmii_speed_clock_set( - a_uint32_t dev_id, - a_uint32_t port_id, - fal_port_speed_t phy_speed) -{ - switch (phy_speed) { - case FAL_SPEED_10: - ssdk_port_speed_clock_set(dev_id, - port_id, USXGMII_SPEED_10M_CLK); - break; - case FAL_SPEED_100: - ssdk_port_speed_clock_set(dev_id, - port_id, USXGMII_SPEED_100M_CLK); - break; - case FAL_SPEED_1000: - ssdk_port_speed_clock_set(dev_id, - port_id, USXGMII_SPEED_1000M_CLK); - break; - case FAL_SPEED_2500: - ssdk_port_speed_clock_set(dev_id, - port_id, USXGMII_SPEED_2500M_CLK); - break; - case FAL_SPEED_5000: - ssdk_port_speed_clock_set(dev_id, - port_id, USXGMII_SPEED_5000M_CLK); - break; - case FAL_SPEED_10000: - ssdk_port_speed_clock_set(dev_id, - port_id, USXGMII_SPEED_10000M_CLK); - break; - default: - break; - } - -} - -static void -adpt_hppe_sgmiiplus_speed_clock_set( - a_uint32_t dev_id, - a_uint32_t port_id, - fal_port_speed_t phy_speed) -{ - ssdk_port_speed_clock_set(dev_id, port_id, SGMII_PLUS_SPEED_2500M_CLK); -} - - -void -adpt_hppe_gcc_port_speed_clock_set(a_uint32_t dev_id, a_uint32_t port_id, - fal_port_speed_t phy_speed) -{ - a_uint32_t mode = 0, uniphy_index = 0, mode1 = 0; - - if (port_id < HPPE_MUX_PORT1) - { -#if defined(CPPE) - if (port_id == SSDK_PHYSICAL_PORT4) { - mode = ssdk_dt_global_get_mac_mode(dev_id, SSDK_UNIPHY_INSTANCE0); - if (mode == PORT_WRAPPER_SGMII_PLUS) { - adpt_hppe_sgmiiplus_speed_clock_set(dev_id, port_id, phy_speed); - return; - } - } -#endif - adpt_hppe_pqsgmii_speed_clock_set(dev_id, port_id, phy_speed); - } - else - { - if (port_id == HPPE_MUX_PORT1) - { - uniphy_index = SSDK_UNIPHY_INSTANCE0; - mode = ssdk_dt_global_get_mac_mode(dev_id, uniphy_index); - mode1 = ssdk_dt_global_get_mac_mode(dev_id, SSDK_UNIPHY_INSTANCE1); - if ((((mode == PORT_WRAPPER_PSGMII) || - (mode == PORT_WRAPPER_PSGMII_FIBER)) && - (mode1 == PORT_WRAPPER_MAX)) || - ((mode == PORT_WRAPPER_SGMII4_RGMII4 || - mode == PORT_WRAPPER_SGMII_CHANNEL4) - && (mode1 == PORT_WRAPPER_MAX))) - { - adpt_hppe_pqsgmii_speed_clock_set(dev_id, port_id, phy_speed); - return; - } - } - if (port_id == HPPE_MUX_PORT1) - uniphy_index = SSDK_UNIPHY_INSTANCE1; - else - uniphy_index = SSDK_UNIPHY_INSTANCE2; - - mode = ssdk_dt_global_get_mac_mode(dev_id, uniphy_index); - if (mode == PORT_WRAPPER_SGMII0_RGMII4 || mode == PORT_WRAPPER_SGMII_CHANNEL0 - || mode == PORT_WRAPPER_SGMII_FIBER) - adpt_hppe_sgmii_speed_clock_set(dev_id, port_id, phy_speed); - else if (mode == PORT_WRAPPER_SGMII_PLUS) - adpt_hppe_sgmiiplus_speed_clock_set(dev_id, port_id, phy_speed); - else if ((mode == PORT_WRAPPER_USXGMII) || (mode == PORT_WRAPPER_10GBASE_R)) - adpt_hppe_usxgmii_speed_clock_set(dev_id,port_id, phy_speed); - } - return; -} - -void -adpt_hppe_gcc_uniphy_clock_status_set(a_uint32_t dev_id, a_uint32_t port_id, - a_bool_t enable) -{ - a_uint32_t mode = 0, uniphy_index = 0, mode1 = 0; -#if defined(CPPE) - a_uint32_t channel_id = 0; -#endif - - if (port_id < HPPE_MUX_PORT1) - { - uniphy_index = SSDK_UNIPHY_INSTANCE0; -#if defined(CPPE) - adpt_cppe_port_to_channel_convert(dev_id, port_id, - &channel_id); - port_id = channel_id; -#endif - qca_gcc_uniphy_port_clock_set(dev_id, uniphy_index, - port_id, enable); - } - else - { - if (port_id == HPPE_MUX_PORT1) - { - uniphy_index = SSDK_UNIPHY_INSTANCE0; - mode = ssdk_dt_global_get_mac_mode(dev_id, uniphy_index); - mode1 = ssdk_dt_global_get_mac_mode(dev_id, SSDK_UNIPHY_INSTANCE1); - if ((((mode == PORT_WRAPPER_PSGMII) || - (mode == PORT_WRAPPER_PSGMII_FIBER)) && - (mode1 == PORT_WRAPPER_MAX)) || - ((mode == PORT_WRAPPER_SGMII4_RGMII4 || - mode == PORT_WRAPPER_SGMII_CHANNEL4) - && (mode1 == PORT_WRAPPER_MAX))) - { - qca_gcc_uniphy_port_clock_set(dev_id, uniphy_index, - port_id, enable); - return; - } - } - if (port_id == HPPE_MUX_PORT1) - uniphy_index = SSDK_UNIPHY_INSTANCE1; - else - uniphy_index = SSDK_UNIPHY_INSTANCE2; - - qca_gcc_uniphy_port_clock_set(dev_id, uniphy_index, - 1, enable); - } - return; -} - -static sw_error_t -adpt_hppe_sfp_interface_mode_switch(a_uint32_t dev_id, - a_uint32_t port_id) -{ - sw_error_t rv = SW_OK; - fal_port_interface_mode_t port_mode_old = PORT_INTERFACE_MODE_MAX, - port_mode_new= PORT_INTERFACE_MODE_MAX; - - if (A_FALSE == _adpt_hppe_port_phy_connected(dev_id, port_id)) - { - rv = adpt_hppe_port_interface_mode_get(dev_id, port_id, &port_mode_old); - SW_RTN_ON_ERROR(rv); - rv = adpt_hppe_port_interface_mode_status_get(dev_id, port_id, - &port_mode_new); - SW_RTN_ON_ERROR (rv); - if(port_mode_old != port_mode_new) - { - SSDK_DEBUG("Port %d change interface mode to %d from %d\n", port_id, - port_mode_new, port_mode_old); - rv = _adpt_hppe_port_interface_mode_set(dev_id, port_id, port_mode_new); - SW_RTN_ON_ERROR(rv); - rv = _adpt_hppe_port_interface_mode_apply(dev_id, A_FALSE); - SW_RTN_ON_ERROR(rv); - } - } - - return rv; -} - -static sw_error_t -adpt_hppe_port_interface_mode_switch(a_uint32_t dev_id, a_uint32_t port_id) -{ - sw_error_t rv = SW_OK; - fal_port_interface_mode_t port_mode_old = PORT_INTERFACE_MODE_MAX; - fal_port_interface_mode_t port_mode_new = PORT_INTERFACE_MODE_MAX; - - rv = adpt_hppe_port_interface_mode_status_get(dev_id, - port_id, &port_mode_new); - SW_RTN_ON_ERROR(rv); - - rv = adpt_hppe_port_interface_mode_get(dev_id, port_id, &port_mode_old); - SW_RTN_ON_ERROR(rv); - - if (port_mode_new != port_mode_old) { - rv = _adpt_hppe_port_interface_mode_set(dev_id, - port_id, port_mode_new); - SW_RTN_ON_ERROR(rv); - rv = _adpt_hppe_port_interface_mode_apply(dev_id, A_FALSE); - } - return rv; -} - -void -adpt_hppe_gcc_mac_clock_status_set(a_uint32_t dev_id, a_uint32_t port_id, - a_bool_t enable) -{ - - qca_gcc_mac_port_clock_set(dev_id, port_id, enable); - - return; -} -a_bool_t -adpt_hppe_port_phy_status_change(struct qca_phy_priv *priv, a_uint32_t port_id, - struct port_phy_status phy_status) -{ - if ((a_uint32_t)phy_status.speed != priv->port_old_speed[port_id - 1]) - return A_TRUE; - if ((a_uint32_t)phy_status.duplex != priv->port_old_duplex[port_id - 1]) - return A_TRUE; - if (phy_status.tx_flowctrl != priv->port_old_tx_flowctrl[port_id - 1]) - return A_TRUE; - if (phy_status.rx_flowctrl != priv->port_old_rx_flowctrl[port_id - 1]) - return A_TRUE; - return A_FALSE; -} -sw_error_t -qca_hppe_mac_sw_sync_task(struct qca_phy_priv *priv) -{ - a_uint32_t port_id; - struct port_phy_status phy_status = {0}; - a_bool_t status; - a_uint32_t portbmp[SW_MAX_NR_DEV] = {0}; - sw_error_t rv = SW_OK; - - portbmp[priv->device_id] = qca_ssdk_port_bmp_get(priv->device_id); - - for (port_id = 1; port_id < SW_MAX_NR_PORT; port_id ++) { - - if(!(portbmp[priv->device_id] & (0x1 << port_id))) - continue; - - rv = adpt_hppe_port_phy_status_get(priv->device_id, - port_id, &phy_status); - if (rv != SW_OK) { - SSDK_DEBUG("failed to get port %d status return value is %d\n", - port_id, rv); - continue; - } - rv = adpt_hppe_sfp_interface_mode_switch(priv->device_id, port_id); - if(rv) { - SSDK_DEBUG("port %d sfp interface mode change failed\n", port_id); - } - SSDK_DEBUG("polling task external phy %d link status is %d and speed is %d\n", - port_id, phy_status.link_status, phy_status.speed); - /* link status from up to down */ - if ((phy_status.link_status == PORT_LINK_DOWN) && - (priv->port_old_link[port_id - 1] == PORT_LINK_UP)) - { - SSDK_DEBUG("Port %d change to link down status\n", port_id); - /* disable ppe port bridge txmac */ - adpt_hppe_port_bridge_txmac_set(priv->device_id, port_id, A_FALSE); - /* disable rx mac */ - adpt_hppe_port_rxmac_status_set(priv->device_id, port_id, A_FALSE); - priv->port_old_link[port_id - 1] = phy_status.link_status; - /* switch interface mode if necessary */ - if (adpt_hppe_port_interface_mode_switch(priv->device_id, - port_id) == SW_OK) { - SSDK_DEBUG("Port %d the interface mode switched\n", - port_id); - } -#ifdef IN_FDB - adpt_hppe_fdb_del_by_port(priv->device_id, port_id, !(FAL_FDB_DEL_STATIC)); -#endif - continue; - } - /* link status from down to up*/ - if ((phy_status.link_status == PORT_LINK_UP) && - (priv->port_old_link[port_id - 1] == PORT_LINK_DOWN)) - { - SSDK_DEBUG("Port %d change to link up status\n", port_id); - status = adpt_hppe_port_phy_status_change(priv, port_id, phy_status); - /*disable tx mac*/ - adpt_hppe_port_txmac_status_set(priv->device_id, port_id, A_FALSE); - /* switch interface mode if necessary */ - if (adpt_hppe_port_interface_mode_switch(priv->device_id, - port_id) == SW_OK) { - SSDK_DEBUG("Port %d the interface mode switched\n", - port_id); - } - /* first check uniphy auto-neg complete interrupt to usxgmii */ - adpt_hppe_uniphy_autoneg_status_check(priv->device_id, port_id); - if (status == A_TRUE) - { - adpt_hppe_gcc_uniphy_clock_status_set(priv->device_id, - port_id, A_FALSE); - if ((a_uint32_t)phy_status.speed != - priv->port_old_speed[port_id - 1]) - { - /* configure gcc speed clock according to current speed */ - adpt_hppe_gcc_port_speed_clock_set(priv->device_id, port_id, - phy_status.speed); - - /* config uniphy speed to usxgmii mode */ - adpt_hppe_uniphy_speed_set(priv->device_id, port_id, - phy_status.speed); - - /* reset port mac when speed change under usxgmii mode */ - adpt_hppe_port_speed_change_mac_reset(priv->device_id, port_id); - - /* config mac speed */ - adpt_hppe_port_mac_speed_set(priv->device_id, port_id, - phy_status.speed); - priv->port_old_speed[port_id - 1] = - (a_uint32_t)phy_status.speed; - - SSDK_DEBUG("Port %d is link up and speed change to %d\n", - port_id, priv->port_old_speed[port_id - 1]); - } - if ((a_uint32_t)phy_status.duplex != - priv->port_old_duplex[port_id - 1]) - { - adpt_hppe_uniphy_duplex_set(priv->device_id, port_id, - phy_status.duplex); - adpt_hppe_port_mac_duplex_set(priv->device_id, port_id, - phy_status.duplex); - priv->port_old_duplex[port_id - 1] = - (a_uint32_t)phy_status.duplex; - - SSDK_DEBUG("Port %d is link up and duplex change to %d\n", - port_id, - priv->port_old_duplex[port_id - 1]); - } - if (priv->port_tx_flowctrl_forcemode[port_id - 1] != A_TRUE) - { - if (phy_status.duplex == FAL_HALF_DUPLEX) - { - phy_status.tx_flowctrl = A_TRUE; - } - if (phy_status.tx_flowctrl != - priv->port_old_tx_flowctrl[port_id - 1]) - { - adpt_hppe_port_txfc_status_set(priv->device_id, - port_id, phy_status.tx_flowctrl); - priv->port_old_tx_flowctrl[port_id - 1] = - phy_status.tx_flowctrl; - - SSDK_DEBUG("Port %d is link up and tx flowctrl" - " change to %d\n", port_id, - priv->port_old_tx_flowctrl[port_id - 1]); - } - } - if (priv->port_rx_flowctrl_forcemode[port_id - 1] != A_TRUE) - { - if (phy_status.duplex == FAL_HALF_DUPLEX) - { - phy_status.rx_flowctrl = A_TRUE; - } - if (phy_status.rx_flowctrl != - priv->port_old_rx_flowctrl[port_id - 1]) - { - adpt_hppe_port_rxfc_status_set(priv->device_id, - port_id, phy_status.rx_flowctrl); - priv->port_old_rx_flowctrl[port_id - 1] = - phy_status.rx_flowctrl; - - SSDK_DEBUG("Port %d is link up and rx flowctrl" - " change to %d\n", port_id, - priv->port_old_rx_flowctrl[port_id-1]); - } - } - adpt_hppe_gcc_uniphy_clock_status_set(priv->device_id, - port_id, A_TRUE); - adpt_hppe_uniphy_port_adapter_reset(priv->device_id, port_id); - } - /* enable mac and ppe txmac*/ - adpt_hppe_port_txmac_status_set(priv->device_id, port_id, A_TRUE); - adpt_hppe_port_rxmac_status_set(priv->device_id, port_id, A_TRUE); - adpt_hppe_port_bridge_txmac_set(priv->device_id, port_id, A_TRUE); - priv->port_old_link[port_id - 1] = phy_status.link_status; - } - SSDK_DEBUG("polling task PPE port %d link status is %d and speed is %d\n", - port_id, priv->port_old_link[port_id - 1], - priv->port_old_speed[port_id - 1]); - } - return 0; -} - -void adpt_hppe_port_ctrl_func_bitmap_init(a_uint32_t dev_id) -{ - adpt_api_t *p_adpt_api = NULL; - - p_adpt_api = adpt_api_ptr_get(dev_id); - - if(p_adpt_api == NULL) - return; - - p_adpt_api->adpt_port_ctrl_func_bitmap[0] = \ - ((1 << FUNC_ADPT_PORT_LOCAL_LOOPBACK_GET)| - (1 << FUNC_ADPT_PORT_AUTONEG_RESTART)| - (1 << FUNC_ADPT_PORT_DUPLEX_SET)| - (1 << FUNC_ADPT_PORT_RXMAC_STATUS_GET)| - (1 << FUNC_ADPT_PORT_CDT)| - (1 << FUNC_ADPT_PORT_TXMAC_STATUS_SET)| - (1 << FUNC_ADPT_PORT_COMBO_FIBER_MODE_SET)| - (1 << FUNC_ADPT_PORT_COMBO_MEDIUM_STATUS_GET)| - (1 << FUNC_ADPT_PORT_MAGIC_FRAME_MAC_SET)| - (1 << FUNC_ADPT_PORT_POWERSAVE_SET)| - (1 << FUNC_ADPT_PORT_HIBERNATE_SET)| - (1 << FUNC_ADPT_PORT_8023AZ_GET)| - (1 << FUNC_ADPT_PORT_RXFC_STATUS_GET)| - (1 << FUNC_ADPT_PORT_TXFC_STATUS_GET)| - (1 << FUNC_ADPT_PORT_REMOTE_LOOPBACK_SET)| - (1 << FUNC_ADPT_PORT_FLOWCTRL_SET)| - (1 << FUNC_ADPT_PORT_MRU_SET)| - (1 << FUNC_ADPT_PORT_AUTONEG_STATUS_GET)| - (1 << FUNC_ADPT_PORT_TXMAC_STATUS_GET)| - (1 << FUNC_ADPT_PORT_MDIX_GET)| - (1 << FUNC_ADPT_PORTS_LINK_STATUS_GET)| - (1 << FUNC_ADPT_PORT_MAC_LOOPBACK_SET)| - (1 << FUNC_ADPT_PORT_PHY_ID_GET)| - (1 << FUNC_ADPT_PORT_MRU_GET)| - (1 << FUNC_ADPT_PORT_POWER_ON)| - (1 << FUNC_ADPT_PORT_SPEED_SET)| - (1 << FUNC_ADPT_PORT_INTERFACE_MODE_GET)| - (1 << FUNC_ADPT_PORT_DUPLEX_GET)| - (1 << FUNC_ADPT_PORT_AUTONEG_ADV_GET)| - (1 << FUNC_ADPT_PORT_MDIX_STATUS_GET)| - (1 << FUNC_ADPT_PORT_MTU_SET)| - (1 << FUNC_ADPT_PORT_LINK_STATUS_GET)); - - p_adpt_api->adpt_port_ctrl_func_bitmap[1] = \ - ((1 << (FUNC_ADPT_PORT_8023AZ_SET % 32))| - (1 << (FUNC_ADPT_PORT_POWERSAVE_GET % 32))| - (1 << (FUNC_ADPT_PORT_COMBO_PREFER_MEDIUM_GET % 32))| - (1 << (FUNC_ADPT_PORT_COMBO_PREFER_MEDIUM_SET % 32))| - (1 << (FUNC_ADPT_PORT_POWER_OFF % 32))| - (1 << (FUNC_ADPT_PORT_TXFC_STATUS_SET % 32))| - (1 << (FUNC_ADPT_PORT_COUNTER_SET % 32))| - (1 << (FUNC_ADPT_PORT_COMBO_FIBER_MODE_GET % 32))| - (1 << (FUNC_ADPT_PORT_LOCAL_LOOPBACK_SET % 32))| - (1 << (FUNC_ADPT_PORT_WOL_STATUS_SET % 32))| - (1 << (FUNC_ADPT_PORT_MAGIC_FRAME_MAC_GET % 32))| - (1 << (FUNC_ADPT_PORT_FLOWCTRL_GET % 32))| - (1 << (FUNC_ADPT_PORT_RXMAC_STATUS_SET % 32))| - (1 << (FUNC_ADPT_PORT_COUNTER_GET % 32))| - (1 << (FUNC_ADPT_PORT_INTERFACE_MODE_SET % 32))| - (1 << (FUNC_ADPT_PORT_MAC_LOOPBACK_GET % 32))| - (1 << (FUNC_ADPT_PORT_HIBERNATE_GET % 32))| - (1 << (FUNC_ADPT_PORT_AUTONEG_ADV_SET % 32))| - (1 << (FUNC_ADPT_PORT_REMOTE_LOOPBACK_GET % 32))| - (1 << (FUNC_ADPT_PORT_COUNTER_SHOW % 32))| - (1 << (FUNC_ADPT_PORT_AUTONEG_ENABLE % 32))| - (1 << (FUNC_ADPT_PORT_MTU_GET % 32))| - (1 << (FUNC_ADPT_PORT_INTERFACE_MODE_STATUS_GET % 32))| - (1 << (FUNC_ADPT_PORT_RESET % 32))| - (1 << (FUNC_ADPT_PORT_RXFC_STATUS_SET % 32))| - (1 << (FUNC_ADPT_PORT_SPEED_GET % 32))| - (1 << (FUNC_ADPT_PORT_MDIX_SET % 32))| - (1 << (FUNC_ADPT_PORT_WOL_STATUS_GET % 32))| - (1 << (FUNC_ADPT_PORT_MAX_FRAME_SIZE_SET % 32))| - (1 << (FUNC_ADPT_PORT_MAX_FRAME_SIZE_GET % 32))| - (1 << (FUNC_ADPT_PORT_SOURCE_FILTER_GET % 32))| - (1 << (FUNC_ADPT_PORT_SOURCE_FILTER_SET % 32))); - - p_adpt_api->adpt_port_ctrl_func_bitmap[2] = \ - ((1 << (FUNC_ADPT_PORT_INTERFACE_MODE_APPLY% 32))| - (1 << (FUNC_ADPT_PORT_INTERFACE_3AZ_STATUS_SET% 32))| - (1 << (FUNC_ADPT_PORT_INTERFACE_3AZ_STATUS_GET% 32))| - (1 << (FUNC_ADPT_PORT_PROMISC_MODE_SET% 32))| - (1 << (FUNC_ADPT_PORT_PROMISC_MODE_GET% 32))| - (1 << (FUNC_ADPT_PORT_FLOWCTRL_FORCEMODE_SET% 32))| - (1 << (FUNC_ADPT_PORT_FLOWCTRL_FORCEMODE_GET% 32))); - - return; - -} - -static void adpt_hppe_port_ctrl_func_unregister(a_uint32_t dev_id, adpt_api_t *p_adpt_api) -{ - if(p_adpt_api == NULL) - return; - - p_adpt_api->adpt_port_local_loopback_get = NULL; - p_adpt_api->adpt_port_autoneg_restart = NULL; - p_adpt_api->adpt_port_duplex_set = NULL; - p_adpt_api->adpt_port_rxmac_status_get = NULL; - p_adpt_api->adpt_port_cdt = NULL; - p_adpt_api->adpt_port_txmac_status_set = NULL; - p_adpt_api->adpt_port_combo_fiber_mode_set = NULL; - p_adpt_api->adpt_port_combo_medium_status_get = NULL; - p_adpt_api->adpt_port_magic_frame_mac_set = NULL; - p_adpt_api->adpt_port_powersave_set = NULL; - p_adpt_api->adpt_port_hibernate_set = NULL; - p_adpt_api->adpt_port_8023az_get = NULL; - p_adpt_api->adpt_port_rxfc_status_get = NULL; - p_adpt_api->adpt_port_txfc_status_get = NULL; - p_adpt_api->adpt_port_remote_loopback_set = NULL; - p_adpt_api->adpt_port_flowctrl_set = NULL; - p_adpt_api->adpt_port_mru_set = NULL; - p_adpt_api->adpt_port_autoneg_status_get = NULL; - p_adpt_api->adpt_port_txmac_status_get = NULL; - p_adpt_api->adpt_port_mdix_get = NULL; - p_adpt_api->adpt_ports_link_status_get = NULL; - p_adpt_api->adpt_port_mac_loopback_set = NULL; - p_adpt_api->adpt_port_phy_id_get = NULL; - p_adpt_api->adpt_port_mru_get = NULL; - p_adpt_api->adpt_port_power_on = NULL; - p_adpt_api->adpt_port_speed_set = NULL; - p_adpt_api->adpt_port_interface_mode_get = NULL; - p_adpt_api->adpt_port_duplex_get = NULL; - p_adpt_api->adpt_port_autoneg_adv_get = NULL; - p_adpt_api->adpt_port_mdix_status_get = NULL; - p_adpt_api->adpt_port_mtu_set = NULL; - p_adpt_api->adpt_port_link_status_get = NULL; - p_adpt_api->adpt_port_8023az_set = NULL; - p_adpt_api->adpt_port_powersave_get = NULL; - p_adpt_api->adpt_port_combo_prefer_medium_get = NULL; - p_adpt_api->adpt_port_combo_prefer_medium_set = NULL; - p_adpt_api->adpt_port_power_off = NULL; - p_adpt_api->adpt_port_txfc_status_set = NULL; - p_adpt_api->adpt_port_counter_set = NULL; - p_adpt_api->adpt_port_combo_fiber_mode_get = NULL; - p_adpt_api->adpt_port_local_loopback_set = NULL; - p_adpt_api->adpt_port_wol_status_set = NULL; - p_adpt_api->adpt_port_magic_frame_mac_get = NULL; - p_adpt_api->adpt_port_flowctrl_get = NULL; - p_adpt_api->adpt_port_rxmac_status_set = NULL; - p_adpt_api->adpt_port_counter_get = NULL; - p_adpt_api->adpt_port_interface_mode_set = NULL; - p_adpt_api->adpt_port_interface_mode_apply = NULL; - p_adpt_api->adpt_port_mac_loopback_get = NULL; - p_adpt_api->adpt_port_hibernate_get = NULL; - p_adpt_api->adpt_port_autoneg_adv_set = NULL; - p_adpt_api->adpt_port_remote_loopback_get = NULL; - p_adpt_api->adpt_port_counter_show = NULL; - p_adpt_api->adpt_port_autoneg_enable = NULL; - p_adpt_api->adpt_port_mtu_get = NULL; - p_adpt_api->adpt_port_interface_mode_status_get = NULL; - p_adpt_api->adpt_port_reset = NULL; - p_adpt_api->adpt_port_rxfc_status_set = NULL; - p_adpt_api->adpt_port_speed_get = NULL; - p_adpt_api->adpt_port_mdix_set = NULL; - p_adpt_api->adpt_port_wol_status_get = NULL; - p_adpt_api->adpt_port_max_frame_size_set = NULL; - p_adpt_api->adpt_port_max_frame_size_get = NULL; - p_adpt_api->adpt_port_source_filter_get = NULL; - p_adpt_api->adpt_port_source_filter_set = NULL; - p_adpt_api->adpt_port_interface_3az_status_set = NULL; - p_adpt_api->adpt_port_interface_3az_status_get = NULL; - p_adpt_api->adpt_port_promisc_mode_set = NULL; - p_adpt_api->adpt_port_promisc_mode_get = NULL; - p_adpt_api->adpt_port_flowctrl_forcemode_set = NULL; - p_adpt_api->adpt_port_flowctrl_forcemode_get = NULL; - - return; - -} - -sw_error_t adpt_hppe_port_ctrl_init(a_uint32_t dev_id) -{ - adpt_api_t *p_adpt_api = NULL; - - p_adpt_api = adpt_api_ptr_get(dev_id); - - if(p_adpt_api == NULL) - return SW_FAIL; - - adpt_hppe_port_ctrl_func_unregister(dev_id, p_adpt_api); -#ifndef IN_PORTCONTROL_MINI - if(p_adpt_api->adpt_port_ctrl_func_bitmap[0] & (1 << FUNC_ADPT_PORT_LOCAL_LOOPBACK_GET)) - { - p_adpt_api->adpt_port_local_loopback_get = adpt_hppe_port_local_loopback_get; - } -#endif - if(p_adpt_api->adpt_port_ctrl_func_bitmap[0] & (1 << FUNC_ADPT_PORT_AUTONEG_RESTART)) - { - p_adpt_api->adpt_port_autoneg_restart = adpt_hppe_port_autoneg_restart; - } - if(p_adpt_api->adpt_port_ctrl_func_bitmap[0] & (1 << FUNC_ADPT_PORT_DUPLEX_SET)) - { - p_adpt_api->adpt_port_duplex_set = adpt_hppe_port_duplex_set; - } -#ifndef IN_PORTCONTROL_MINI - if(p_adpt_api->adpt_port_ctrl_func_bitmap[0] & (1 << FUNC_ADPT_PORT_RXMAC_STATUS_GET)) - { - p_adpt_api->adpt_port_rxmac_status_get = adpt_hppe_port_rxmac_status_get; - } - if(p_adpt_api->adpt_port_ctrl_func_bitmap[0] & (1 << FUNC_ADPT_PORT_CDT)) - { - p_adpt_api->adpt_port_cdt = adpt_hppe_port_cdt; - } -#endif - if(p_adpt_api->adpt_port_ctrl_func_bitmap[0] & (1 << FUNC_ADPT_PORT_TXMAC_STATUS_SET)) - { - p_adpt_api->adpt_port_txmac_status_set = adpt_hppe_port_txmac_status_set; - } -#ifndef IN_PORTCONTROL_MINI - if(p_adpt_api->adpt_port_ctrl_func_bitmap[0] & (1 << FUNC_ADPT_PORT_COMBO_FIBER_MODE_SET)) - { - p_adpt_api->adpt_port_combo_fiber_mode_set = adpt_hppe_port_combo_fiber_mode_set; - } - if(p_adpt_api->adpt_port_ctrl_func_bitmap[0] & - (1 << FUNC_ADPT_PORT_COMBO_MEDIUM_STATUS_GET)) - { - p_adpt_api->adpt_port_combo_medium_status_get = - adpt_hppe_port_combo_medium_status_get; - } - if(p_adpt_api->adpt_port_ctrl_func_bitmap[0] & (1 << FUNC_ADPT_PORT_MAGIC_FRAME_MAC_SET)) - { - p_adpt_api->adpt_port_magic_frame_mac_set = adpt_hppe_port_magic_frame_mac_set; - } - if(p_adpt_api->adpt_port_ctrl_func_bitmap[0] & (1 << FUNC_ADPT_PORT_POWERSAVE_SET)) - { - p_adpt_api->adpt_port_powersave_set = adpt_hppe_port_powersave_set; - } - if(p_adpt_api->adpt_port_ctrl_func_bitmap[0] & (1 << FUNC_ADPT_PORT_HIBERNATE_SET)) - { - p_adpt_api->adpt_port_hibernate_set = adpt_hppe_port_hibernate_set; - } - if(p_adpt_api->adpt_port_ctrl_func_bitmap[0] & (1 << FUNC_ADPT_PORT_8023AZ_GET)) - { - p_adpt_api->adpt_port_8023az_get = adpt_hppe_port_8023az_get; - } -#endif - if(p_adpt_api->adpt_port_ctrl_func_bitmap[0] & (1 << FUNC_ADPT_PORT_RXFC_STATUS_GET)) - { - p_adpt_api->adpt_port_rxfc_status_get = adpt_hppe_port_rxfc_status_get; - } - if(p_adpt_api->adpt_port_ctrl_func_bitmap[0] & (1 << FUNC_ADPT_PORT_TXFC_STATUS_GET)) - { - p_adpt_api->adpt_port_txfc_status_get = adpt_hppe_port_txfc_status_get; - } -#ifndef IN_PORTCONTROL_MINI - if(p_adpt_api->adpt_port_ctrl_func_bitmap[0] & (1 << FUNC_ADPT_PORT_REMOTE_LOOPBACK_SET)) - { - p_adpt_api->adpt_port_remote_loopback_set = adpt_hppe_port_remote_loopback_set; - } -#endif - if(p_adpt_api->adpt_port_ctrl_func_bitmap[0] & (1 << FUNC_ADPT_PORT_FLOWCTRL_SET)) - { - p_adpt_api->adpt_port_flowctrl_set = adpt_hppe_port_flowctrl_set; - } -#ifndef IN_PORTCONTROL_MINI - if(p_adpt_api->adpt_port_ctrl_func_bitmap[0] & (1 << FUNC_ADPT_PORT_MRU_SET)) - { - p_adpt_api->adpt_port_mru_set = adpt_ppe_port_mru_set; - } -#endif - if(p_adpt_api->adpt_port_ctrl_func_bitmap[0] & (1 << FUNC_ADPT_PORT_AUTONEG_STATUS_GET)) - { - p_adpt_api->adpt_port_autoneg_status_get = adpt_hppe_port_autoneg_status_get; - } -#ifndef IN_PORTCONTROL_MINI - if(p_adpt_api->adpt_port_ctrl_func_bitmap[0] & (1 << FUNC_ADPT_PORT_TXMAC_STATUS_GET)) - { - p_adpt_api->adpt_port_txmac_status_get = adpt_hppe_port_txmac_status_get; - } - if(p_adpt_api->adpt_port_ctrl_func_bitmap[0] & (1 << FUNC_ADPT_PORT_MDIX_GET)) - { - p_adpt_api->adpt_port_mdix_get = adpt_hppe_port_mdix_get; - } - if(p_adpt_api->adpt_port_ctrl_func_bitmap[0] & (1 << FUNC_ADPT_PORTS_LINK_STATUS_GET)) - { - p_adpt_api->adpt_ports_link_status_get = adpt_hppe_ports_link_status_get; - } - if(p_adpt_api->adpt_port_ctrl_func_bitmap[0] & (1 << FUNC_ADPT_PORT_MAC_LOOPBACK_SET)) - { - p_adpt_api->adpt_port_mac_loopback_set = adpt_hppe_port_mac_loopback_set; - } - if(p_adpt_api->adpt_port_ctrl_func_bitmap[0] & (1 << FUNC_ADPT_PORT_PHY_ID_GET)) - { - p_adpt_api->adpt_port_phy_id_get = adpt_hppe_port_phy_id_get; - } - if(p_adpt_api->adpt_port_ctrl_func_bitmap[0] & (1 << FUNC_ADPT_PORT_MRU_GET)) - { - p_adpt_api->adpt_port_mru_get = adpt_ppe_port_mru_get; - } -#endif - if(p_adpt_api->adpt_port_ctrl_func_bitmap[0] & (1 << FUNC_ADPT_PORT_POWER_ON)) - { - p_adpt_api->adpt_port_power_on = adpt_hppe_port_power_on; - } - if(p_adpt_api->adpt_port_ctrl_func_bitmap[0] & (1 << FUNC_ADPT_PORT_SPEED_SET)) - { - p_adpt_api->adpt_port_speed_set = adpt_hppe_port_speed_set; - } - if(p_adpt_api->adpt_port_ctrl_func_bitmap[0] & (1 << FUNC_ADPT_PORT_INTERFACE_MODE_GET)) - { - p_adpt_api->adpt_port_interface_mode_get = adpt_hppe_port_interface_mode_get; - } - if(p_adpt_api->adpt_port_ctrl_func_bitmap[0] & (1 << FUNC_ADPT_PORT_DUPLEX_GET)) - { - p_adpt_api->adpt_port_duplex_get = adpt_hppe_port_duplex_get; - } - if(p_adpt_api->adpt_port_ctrl_func_bitmap[0] & (1 << FUNC_ADPT_PORT_AUTONEG_ADV_GET)) - { - p_adpt_api->adpt_port_autoneg_adv_get = adpt_hppe_port_autoneg_adv_get; - } -#ifndef IN_PORTCONTROL_MINI - if(p_adpt_api->adpt_port_ctrl_func_bitmap[0] & (1 << FUNC_ADPT_PORT_MDIX_STATUS_GET)) - { - p_adpt_api->adpt_port_mdix_status_get = adpt_hppe_port_mdix_status_get; - } - if(p_adpt_api->adpt_port_ctrl_func_bitmap[0] & (1 << FUNC_ADPT_PORT_MTU_SET)) - { - p_adpt_api->adpt_port_mtu_set = adpt_ppe_port_mtu_set; - } -#endif - if(p_adpt_api->adpt_port_ctrl_func_bitmap[0] & (1 << FUNC_ADPT_PORT_LINK_STATUS_GET)) - { - p_adpt_api->adpt_port_link_status_get = adpt_hppe_port_link_status_get; - } -#ifndef IN_PORTCONTROL_MINI - if(p_adpt_api->adpt_port_ctrl_func_bitmap[1] & (1 << (FUNC_ADPT_PORT_8023AZ_SET % 32))) - { - p_adpt_api->adpt_port_8023az_set = adpt_hppe_port_8023az_set; - } - if(p_adpt_api->adpt_port_ctrl_func_bitmap[1] & (1 << (FUNC_ADPT_PORT_POWERSAVE_GET % 32))) - { - p_adpt_api->adpt_port_powersave_get = adpt_hppe_port_powersave_get; - } - if(p_adpt_api->adpt_port_ctrl_func_bitmap[1] & - (1 << (FUNC_ADPT_PORT_COMBO_PREFER_MEDIUM_GET % 32))) - { - p_adpt_api->adpt_port_combo_prefer_medium_get = - adpt_hppe_port_combo_prefer_medium_get; - } - if(p_adpt_api->adpt_port_ctrl_func_bitmap[1] & - (1 << (FUNC_ADPT_PORT_COMBO_PREFER_MEDIUM_SET % 32))) - { - p_adpt_api->adpt_port_combo_prefer_medium_set = - adpt_hppe_port_combo_prefer_medium_set; - } -#endif - if(p_adpt_api->adpt_port_ctrl_func_bitmap[1] & (1 << (FUNC_ADPT_PORT_POWER_OFF % 32))) - { - p_adpt_api->adpt_port_power_off = adpt_hppe_port_power_off; - } - if(p_adpt_api->adpt_port_ctrl_func_bitmap[1] & - (1 << (FUNC_ADPT_PORT_TXFC_STATUS_SET % 32))) - { - p_adpt_api->adpt_port_txfc_status_set = adpt_hppe_port_txfc_status_set; - } -#ifndef IN_PORTCONTROL_MINI - if(p_adpt_api->adpt_port_ctrl_func_bitmap[1] & (1 << (FUNC_ADPT_PORT_COUNTER_SET % 32))) - { - p_adpt_api->adpt_port_counter_set = adpt_hppe_port_counter_set; - } - if(p_adpt_api->adpt_port_ctrl_func_bitmap[1] & - (1 << (FUNC_ADPT_PORT_COMBO_FIBER_MODE_GET % 32))) - { - p_adpt_api->adpt_port_combo_fiber_mode_get = adpt_hppe_port_combo_fiber_mode_get; - } - if(p_adpt_api->adpt_port_ctrl_func_bitmap[1] & - (1 << (FUNC_ADPT_PORT_LOCAL_LOOPBACK_SET % 32))) - { - p_adpt_api->adpt_port_local_loopback_set = adpt_hppe_port_local_loopback_set; - } - if(p_adpt_api->adpt_port_ctrl_func_bitmap[1] & (1 << (FUNC_ADPT_PORT_WOL_STATUS_SET % 32))) - { - p_adpt_api->adpt_port_wol_status_set = adpt_hppe_port_wol_status_set; - } - if(p_adpt_api->adpt_port_ctrl_func_bitmap[1] & - (1 << (FUNC_ADPT_PORT_MAGIC_FRAME_MAC_GET % 32))) - { - p_adpt_api->adpt_port_magic_frame_mac_get = adpt_hppe_port_magic_frame_mac_get; - } - if(p_adpt_api->adpt_port_ctrl_func_bitmap[1] & (1 << (FUNC_ADPT_PORT_FLOWCTRL_GET % 32))) - { - p_adpt_api->adpt_port_flowctrl_get = adpt_hppe_port_flowctrl_get; - } -#endif - if(p_adpt_api->adpt_port_ctrl_func_bitmap[1] & - (1 << (FUNC_ADPT_PORT_RXMAC_STATUS_SET % 32))) - { - p_adpt_api->adpt_port_rxmac_status_set = adpt_hppe_port_rxmac_status_set; - } -#ifndef IN_PORTCONTROL_MINI - if(p_adpt_api->adpt_port_ctrl_func_bitmap[1] & (1 << (FUNC_ADPT_PORT_COUNTER_GET % 32))) - { - p_adpt_api->adpt_port_counter_get = adpt_hppe_port_counter_get; - } -#endif - if(p_adpt_api->adpt_port_ctrl_func_bitmap[1] & - (1 << (FUNC_ADPT_PORT_INTERFACE_MODE_SET % 32))) - { - p_adpt_api->adpt_port_interface_mode_set = adpt_hppe_port_interface_mode_set; - } -#ifndef IN_PORTCONTROL_MINI - if(p_adpt_api->adpt_port_ctrl_func_bitmap[1] & - (1 << (FUNC_ADPT_PORT_MAC_LOOPBACK_GET % 32))) - { - p_adpt_api->adpt_port_mac_loopback_get = adpt_hppe_port_mac_loopback_get; - } - if(p_adpt_api->adpt_port_ctrl_func_bitmap[1] & (1 << (FUNC_ADPT_PORT_HIBERNATE_GET % 32))) - { - p_adpt_api->adpt_port_hibernate_get = adpt_hppe_port_hibernate_get; - } -#endif - if(p_adpt_api->adpt_port_ctrl_func_bitmap[1] & - (1 << (FUNC_ADPT_PORT_AUTONEG_ADV_SET % 32))) - { - p_adpt_api->adpt_port_autoneg_adv_set = adpt_hppe_port_autoneg_adv_set; - } -#ifndef IN_PORTCONTROL_MINI - if(p_adpt_api->adpt_port_ctrl_func_bitmap[1] & - (1 << (FUNC_ADPT_PORT_REMOTE_LOOPBACK_GET % 32))) - { - p_adpt_api->adpt_port_remote_loopback_get = adpt_hppe_port_remote_loopback_get; - } - if(p_adpt_api->adpt_port_ctrl_func_bitmap[1] & (1 << (FUNC_ADPT_PORT_COUNTER_SHOW % 32))) - { - p_adpt_api->adpt_port_counter_show = adpt_hppe_port_counter_show; - } -#endif - if(p_adpt_api->adpt_port_ctrl_func_bitmap[1] & (1 << (FUNC_ADPT_PORT_AUTONEG_ENABLE % 32))) - { - p_adpt_api->adpt_port_autoneg_enable = adpt_hppe_port_autoneg_enable; - } -#ifndef IN_PORTCONTROL_MINI - if(p_adpt_api->adpt_port_ctrl_func_bitmap[1] & (1 << (FUNC_ADPT_PORT_MTU_GET % 32))) - { - p_adpt_api->adpt_port_mtu_get = adpt_ppe_port_mtu_get; - } -#endif - if(p_adpt_api->adpt_port_ctrl_func_bitmap[1] & - (1 << (FUNC_ADPT_PORT_INTERFACE_MODE_STATUS_GET % 32))) - { - p_adpt_api->adpt_port_interface_mode_status_get = - adpt_hppe_port_interface_mode_status_get; - } -#ifndef IN_PORTCONTROL_MINI - if(p_adpt_api->adpt_port_ctrl_func_bitmap[1] & (1 << (FUNC_ADPT_PORT_RESET % 32))) - { - p_adpt_api->adpt_port_reset = adpt_hppe_port_reset; - } -#endif - if(p_adpt_api->adpt_port_ctrl_func_bitmap[1] & - (1 << (FUNC_ADPT_PORT_RXFC_STATUS_SET % 32))) - { - p_adpt_api->adpt_port_rxfc_status_set = adpt_hppe_port_rxfc_status_set; - } - if(p_adpt_api->adpt_port_ctrl_func_bitmap[1] & (1 << (FUNC_ADPT_PORT_SPEED_GET % 32))) - { - p_adpt_api->adpt_port_speed_get = adpt_hppe_port_speed_get; - } -#ifndef IN_PORTCONTROL_MINI - if(p_adpt_api->adpt_port_ctrl_func_bitmap[1] & (1 << (FUNC_ADPT_PORT_MDIX_SET % 32))) - { - p_adpt_api->adpt_port_mdix_set = adpt_hppe_port_mdix_set; - } - if(p_adpt_api->adpt_port_ctrl_func_bitmap[1] & (1 << (FUNC_ADPT_PORT_WOL_STATUS_GET % 32))) - { - p_adpt_api->adpt_port_wol_status_get = adpt_hppe_port_wol_status_get; - } -#endif - if(p_adpt_api->adpt_port_ctrl_func_bitmap[1] & - (1 << (FUNC_ADPT_PORT_MAX_FRAME_SIZE_SET % 32))) - { - p_adpt_api->adpt_port_max_frame_size_set = adpt_ppe_port_max_frame_size_set; - } - if(p_adpt_api->adpt_port_ctrl_func_bitmap[1] & - (1 << (FUNC_ADPT_PORT_MAX_FRAME_SIZE_GET % 32))) - { - p_adpt_api->adpt_port_max_frame_size_get = adpt_ppe_port_max_frame_size_get; - } -#ifndef IN_PORTCONTROL_MINI - if(p_adpt_api->adpt_port_ctrl_func_bitmap[1] & - (1 << (FUNC_ADPT_PORT_SOURCE_FILTER_GET % 32))) - { - p_adpt_api->adpt_port_source_filter_get = adpt_ppe_port_source_filter_get; - } - if(p_adpt_api->adpt_port_ctrl_func_bitmap[1] & - (1 << (FUNC_ADPT_PORT_SOURCE_FILTER_SET % 32))) - { - p_adpt_api->adpt_port_source_filter_set = adpt_ppe_port_source_filter_set; - } - if(p_adpt_api->adpt_port_ctrl_func_bitmap[2] & - (1 << (FUNC_ADPT_PORT_INTERFACE_MODE_APPLY% 32))) - { - p_adpt_api->adpt_port_interface_mode_apply = adpt_hppe_port_interface_mode_apply; - } - if(p_adpt_api->adpt_port_ctrl_func_bitmap[2] & - (1 << (FUNC_ADPT_PORT_INTERFACE_3AZ_STATUS_SET% 32))) - { - p_adpt_api->adpt_port_interface_3az_status_set = adpt_hppe_port_interface_3az_set; - } - if(p_adpt_api->adpt_port_ctrl_func_bitmap[2] & - (1 << (FUNC_ADPT_PORT_INTERFACE_3AZ_STATUS_GET% 32))) - { - p_adpt_api->adpt_port_interface_3az_status_get = adpt_hppe_port_interface_3az_get; - } -#endif - if(p_adpt_api->adpt_port_ctrl_func_bitmap[2] & - (1 << (FUNC_ADPT_PORT_PROMISC_MODE_SET% 32))) - { - p_adpt_api->adpt_port_promisc_mode_set = adpt_hppe_port_promisc_mode_set; - } -#ifndef IN_PORTCONTROL_MINI - - if(p_adpt_api->adpt_port_ctrl_func_bitmap[2] & - (1 << (FUNC_ADPT_PORT_PROMISC_MODE_GET% 32))) - { - p_adpt_api->adpt_port_promisc_mode_get = adpt_hppe_port_promisc_mode_get; - } -#endif - if(p_adpt_api->adpt_port_ctrl_func_bitmap[2] & - (1 << (FUNC_ADPT_PORT_FLOWCTRL_FORCEMODE_SET% 32))) - { - p_adpt_api->adpt_port_flowctrl_forcemode_set = - adpt_hppe_port_flowctrl_forcemode_set; - } -#ifndef IN_PORTCONTROL_MINI - if(p_adpt_api->adpt_port_ctrl_func_bitmap[2] & - (1 << (FUNC_ADPT_PORT_FLOWCTRL_FORCEMODE_GET% 32))) - { - p_adpt_api->adpt_port_flowctrl_forcemode_get = - adpt_hppe_port_flowctrl_forcemode_get; - } - p_adpt_api->adpt_port_source_filter_config_get = adpt_ppe_port_source_filter_config_get; - p_adpt_api->adpt_port_source_filter_config_set = adpt_ppe_port_source_filter_config_set; -#endif - p_adpt_api->adpt_port_mux_mac_type_set = adpt_hppe_port_mux_mac_type_set; - p_adpt_api->adpt_port_mac_speed_set = adpt_hppe_port_mac_speed_set; - p_adpt_api->adpt_port_mac_duplex_set = adpt_hppe_port_mac_duplex_set; - p_adpt_api->adpt_port_polling_sw_sync_set = qca_hppe_mac_sw_sync_task; - p_adpt_api->adpt_port_bridge_txmac_set = adpt_hppe_port_bridge_txmac_set; - p_adpt_api->adpt_port_interface_eee_cfg_set = adpt_hppe_port_interface_eee_cfg_set; - p_adpt_api->adpt_port_interface_eee_cfg_get = adpt_hppe_port_interface_eee_cfg_get; - p_adpt_api->adpt_port_phy_status_get = adpt_hppe_port_phy_status_get; -#if defined(CPPE) - if (adpt_hppe_chip_revision_get(dev_id) == CPPE_REVISION) { - p_adpt_api->adpt_switch_port_loopback_set = adpt_cppe_switch_port_loopback_set; - p_adpt_api->adpt_switch_port_loopback_get = adpt_cppe_switch_port_loopback_get; - } -#endif - return SW_OK; -} - -/** - * @} - */ diff --git a/feeds/ipq807x/qca-ssdk/src/src/adpt/hppe/adpt_hppe_portvlan.c b/feeds/ipq807x/qca-ssdk/src/src/adpt/hppe/adpt_hppe_portvlan.c deleted file mode 100755 index aebb8857c..000000000 --- a/feeds/ipq807x/qca-ssdk/src/src/adpt/hppe/adpt_hppe_portvlan.c +++ /dev/null @@ -1,2235 +0,0 @@ -/* - * Copyright (c) 2016-2017, The Linux Foundation. All rights reserved. - * Permission to use, copy, modify, and/or distribute this software for - * any purpose with or without fee is hereby granted, provided that the - * above copyright notice and this permission notice appear in all copies. - * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES - * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR - * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES - * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN - * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT - * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. - */ - - -/** - * @defgroup - * @{ - */ -#include "sw.h" -#include "hppe_portvlan_reg.h" -#include "hppe_portvlan.h" -#include "hppe_portctrl_reg.h" -#include "hppe_portctrl.h" -#include "hppe_policer_reg.h" -#include "hppe_policer.h" -#include "hppe_fdb_reg.h" -#include "hppe_fdb.h" -#include "adpt.h" - -#ifndef IN_PORTVLAN_MINI -a_uint32_t -_get_port_vlan_ingress_trans_by_index(a_uint32_t dev_id, - a_uint32_t index, fal_vlan_trans_entry_t *entry) -{ - union xlt_rule_tbl_u in_vlan_xlt_rule; - union xlt_action_tbl_u in_vlan_xlt_action; - - /*rule part*/ - SW_RTN_ON_ERROR(hppe_xlt_rule_tbl_get(dev_id, index, &in_vlan_xlt_rule)); - if (!in_vlan_xlt_rule.bf.valid) { - memset(&in_vlan_xlt_rule, 0, sizeof(struct xlt_rule_tbl)); - } - - entry->trans_direction = 0; - entry->frmtype_enable = in_vlan_xlt_rule.bf.frm_type_incl; - entry->frmtype = in_vlan_xlt_rule.bf.frm_type; - entry->protocol_enable = in_vlan_xlt_rule.bf.prot_incl; - entry->protocol = ((in_vlan_xlt_rule.bf.prot_value_1 << 7) | - (in_vlan_xlt_rule.bf.prot_value_0)); - - entry->port_bitmap = in_vlan_xlt_rule.bf.port_bitmap; - entry->c_tagged = in_vlan_xlt_rule.bf.ckey_fmt_0 | (in_vlan_xlt_rule.bf.ckey_fmt_1 << 1); - entry->s_tagged = in_vlan_xlt_rule.bf.skey_fmt; - - entry->c_vid_enable = in_vlan_xlt_rule.bf.ckey_vid_incl; - entry->c_vid = in_vlan_xlt_rule.bf.ckey_vid; - entry->c_pcp_enable = in_vlan_xlt_rule.bf.ckey_pcp_incl; - entry->c_pcp = in_vlan_xlt_rule.bf.ckey_pcp; - entry->c_dei_enable = in_vlan_xlt_rule.bf.ckey_dei_incl; - entry->c_dei = in_vlan_xlt_rule.bf.ckey_dei; - - entry->s_vid_enable = in_vlan_xlt_rule.bf.skey_vid_incl; - entry->s_vid = in_vlan_xlt_rule.bf.skey_vid; - entry->s_pcp_enable = in_vlan_xlt_rule.bf.skey_pcp_incl; - entry->s_pcp = in_vlan_xlt_rule.bf.skey_pcp; - entry->s_dei_enable = in_vlan_xlt_rule.bf.skey_dei_incl; - entry->s_dei = in_vlan_xlt_rule.bf.skey_dei; - - /*action part*/ - SW_RTN_ON_ERROR(hppe_xlt_action_tbl_get(dev_id, index, &in_vlan_xlt_action)); - if (!in_vlan_xlt_rule.bf.valid) { - memset(&in_vlan_xlt_action, 0, sizeof(struct xlt_action_tbl)); - } - - entry->counter_enable = in_vlan_xlt_action.bf.counter_en; - entry->counter_id = in_vlan_xlt_action.bf.counter_id; - entry->vsi_action_enable = in_vlan_xlt_action.bf.vsi_cmd; - entry->vsi_action = in_vlan_xlt_action.bf.vsi; - - entry->cdei_xlt_enable = in_vlan_xlt_action.bf.xlt_cdei_cmd; - entry->cdei_xlt = in_vlan_xlt_action.bf.xlt_cdei; - entry->sdei_xlt_enable = in_vlan_xlt_action.bf.xlt_sdei_cmd; - entry->sdei_xlt = in_vlan_xlt_action.bf.xlt_sdei; - entry->swap_sdei_cdei = in_vlan_xlt_action.bf.dei_swap_cmd; - - entry->cpcp_xlt_enable = in_vlan_xlt_action.bf.xlt_cpcp_cmd; - entry->cpcp_xlt = in_vlan_xlt_action.bf.xlt_cpcp; - entry->spcp_xlt_enable = in_vlan_xlt_action.bf.xlt_spcp_cmd; - entry->spcp_xlt = (in_vlan_xlt_action.bf.xlt_spcp_0 | - (in_vlan_xlt_action.bf.xlt_spcp_1 << 1)); - entry->swap_spcp_cpcp = in_vlan_xlt_action.bf.pcp_swap_cmd; - - entry->cvid_xlt_cmd = in_vlan_xlt_action.bf.xlt_cvid_cmd; - entry->cvid_xlt = in_vlan_xlt_action.bf.xlt_cvid; - entry->svid_xlt_cmd = in_vlan_xlt_action.bf.xlt_svid_cmd; - entry->svid_xlt = in_vlan_xlt_action.bf.xlt_svid; - entry->swap_svid_cvid = in_vlan_xlt_action.bf.vid_swap_cmd; - - return in_vlan_xlt_rule.bf.valid; -} - -a_uint32_t -_get_port_vlan_egress_trans_by_index(a_uint32_t dev_id, - a_uint32_t index, fal_vlan_trans_entry_t *entry) -{ - union eg_vlan_xlt_rule_u eg_vlan_xlt_rule; - union eg_vlan_xlt_action_u eg_vlan_xlt_action; - - /*rule part*/ - SW_RTN_ON_ERROR(hppe_eg_vlan_xlt_rule_get(dev_id, index, &eg_vlan_xlt_rule)); - if (!eg_vlan_xlt_rule.bf.valid) { - memset(&eg_vlan_xlt_rule, 0, sizeof(struct eg_vlan_xlt_rule)); - } - - entry->trans_direction = 1; - - entry->port_bitmap = eg_vlan_xlt_rule.bf.port_bitmap; - - entry->vsi_enable = eg_vlan_xlt_rule.bf.vsi_incl; - entry->vsi = eg_vlan_xlt_rule.bf.vsi; - entry->vsi_valid = eg_vlan_xlt_rule.bf.vsi_valid; - - entry->c_tagged = eg_vlan_xlt_rule.bf.ckey_fmt; - entry->s_tagged = eg_vlan_xlt_rule.bf.skey_fmt; - - entry->c_vid_enable = eg_vlan_xlt_rule.bf.ckey_vid_incl; - entry->c_vid = eg_vlan_xlt_rule.bf.ckey_vid; - entry->c_pcp_enable = eg_vlan_xlt_rule.bf.ckey_pcp_incl; - entry->c_pcp = eg_vlan_xlt_rule.bf.ckey_pcp; - entry->c_dei_enable = eg_vlan_xlt_rule.bf.ckey_dei_incl; - entry->c_dei = eg_vlan_xlt_rule.bf.ckey_dei; - - entry->s_vid_enable = eg_vlan_xlt_rule.bf.skey_vid_incl; - entry->s_vid = eg_vlan_xlt_rule.bf.skey_vid; - entry->s_pcp_enable = eg_vlan_xlt_rule.bf.skey_pcp_incl; - entry->s_pcp = eg_vlan_xlt_rule.bf.skey_pcp; - entry->s_dei_enable = eg_vlan_xlt_rule.bf.skey_dei_incl; - entry->s_dei = eg_vlan_xlt_rule.bf.skey_dei; - - /*action part*/ - SW_RTN_ON_ERROR(hppe_eg_vlan_xlt_action_get(dev_id, index, &eg_vlan_xlt_action)); - if (!eg_vlan_xlt_rule.bf.valid) { - memset(&eg_vlan_xlt_action, 0, sizeof(struct eg_vlan_xlt_action)); - } - - entry->counter_enable = eg_vlan_xlt_action.bf.counter_en; - entry->counter_id = eg_vlan_xlt_action.bf.counter_id; - - entry->cdei_xlt_enable = eg_vlan_xlt_action.bf.xlt_cdei_cmd; - entry->cdei_xlt = eg_vlan_xlt_action.bf.xlt_cdei; - entry->sdei_xlt_enable = eg_vlan_xlt_action.bf.xlt_sdei_cmd; - entry->sdei_xlt = eg_vlan_xlt_action.bf.xlt_sdei; - entry->swap_sdei_cdei = eg_vlan_xlt_action.bf.dei_swap_cmd; - - entry->cpcp_xlt_enable = eg_vlan_xlt_action.bf.xlt_cpcp_cmd; - entry->cpcp_xlt = eg_vlan_xlt_action.bf.xlt_cpcp; - entry->spcp_xlt_enable = eg_vlan_xlt_action.bf.xlt_spcp_cmd; - entry->spcp_xlt = (eg_vlan_xlt_action.bf.xlt_spcp_0 | - (eg_vlan_xlt_action.bf.xlt_spcp_1 << 1)); - entry->swap_spcp_cpcp = eg_vlan_xlt_action.bf.pcp_swap_cmd; - - entry->cvid_xlt_cmd = eg_vlan_xlt_action.bf.xlt_cvid_cmd; - entry->cvid_xlt = eg_vlan_xlt_action.bf.xlt_cvid; - entry->svid_xlt_cmd = eg_vlan_xlt_action.bf.xlt_svid_cmd; - entry->svid_xlt = eg_vlan_xlt_action.bf.xlt_svid; - entry->swap_svid_cvid = eg_vlan_xlt_action.bf.vid_swap_cmd; - - return eg_vlan_xlt_rule.bf.valid; -} -#endif - -a_uint32_t -_get_port_vlan_trans_adv_rule_by_index(a_uint32_t dev_id, - a_uint32_t index, fal_port_vlan_direction_t direction, - fal_vlan_trans_adv_rule_t *rule, fal_vlan_trans_adv_action_t * action) -{ - union xlt_rule_tbl_u in_vlan_xlt_rule; - union xlt_action_tbl_u in_vlan_xlt_action; - union eg_vlan_xlt_rule_u eg_vlan_xlt_rule; - union eg_vlan_xlt_action_u eg_vlan_xlt_action; - - if (direction == FAL_PORT_VLAN_INGRESS) { - /*rule part*/ - SW_RTN_ON_ERROR(hppe_xlt_rule_tbl_get(dev_id, index, &in_vlan_xlt_rule)); - if (!in_vlan_xlt_rule.bf.valid) { - memset(&in_vlan_xlt_rule, 0, sizeof(struct xlt_rule_tbl)); - } - - rule->port_bitmap = in_vlan_xlt_rule.bf.port_bitmap; - - rule->s_tagged = in_vlan_xlt_rule.bf.skey_fmt; - rule->s_vid_enable = in_vlan_xlt_rule.bf.skey_vid_incl; - rule->s_vid = in_vlan_xlt_rule.bf.skey_vid; - rule->s_pcp_enable = in_vlan_xlt_rule.bf.skey_pcp_incl; - rule->s_pcp = in_vlan_xlt_rule.bf.skey_pcp; - rule->s_dei_enable = in_vlan_xlt_rule.bf.skey_dei_incl; - rule->s_dei = in_vlan_xlt_rule.bf.skey_dei; - - rule->c_tagged = in_vlan_xlt_rule.bf.ckey_fmt_0 | - (in_vlan_xlt_rule.bf.ckey_fmt_1 << 1); - rule->c_vid_enable = in_vlan_xlt_rule.bf.ckey_vid_incl; - rule->c_vid = in_vlan_xlt_rule.bf.ckey_vid; - rule->c_pcp_enable = in_vlan_xlt_rule.bf.ckey_pcp_incl; - rule->c_pcp = in_vlan_xlt_rule.bf.ckey_pcp; - rule->c_dei_enable = in_vlan_xlt_rule.bf.ckey_dei_incl; - rule->c_dei = in_vlan_xlt_rule.bf.ckey_dei; - - rule->frmtype_enable = in_vlan_xlt_rule.bf.frm_type_incl; - rule->frmtype = in_vlan_xlt_rule.bf.frm_type; - rule->protocol_enable = in_vlan_xlt_rule.bf.prot_incl; - rule->protocol = ((in_vlan_xlt_rule.bf.prot_value_1 << 7) | - (in_vlan_xlt_rule.bf.prot_value_0)); - - /*action part*/ - SW_RTN_ON_ERROR(hppe_xlt_action_tbl_get(dev_id, index, &in_vlan_xlt_action)); - if (!in_vlan_xlt_rule.bf.valid) { - memset(&in_vlan_xlt_action, 0, sizeof(struct xlt_action_tbl)); - } - - action->swap_svid_cvid = in_vlan_xlt_action.bf.vid_swap_cmd; - action->svid_xlt_cmd = in_vlan_xlt_action.bf.xlt_svid_cmd; - action->svid_xlt = in_vlan_xlt_action.bf.xlt_svid; - action->cvid_xlt_cmd = in_vlan_xlt_action.bf.xlt_cvid_cmd; - action->cvid_xlt = in_vlan_xlt_action.bf.xlt_cvid; - - action->swap_spcp_cpcp = in_vlan_xlt_action.bf.pcp_swap_cmd; - action->spcp_xlt_enable = in_vlan_xlt_action.bf.xlt_spcp_cmd; - action->spcp_xlt = (in_vlan_xlt_action.bf.xlt_spcp_0 | - (in_vlan_xlt_action.bf.xlt_spcp_1 << 1)); - action->cpcp_xlt_enable = in_vlan_xlt_action.bf.xlt_cpcp_cmd; - action->cpcp_xlt = in_vlan_xlt_action.bf.xlt_cpcp; - - action->swap_sdei_cdei = in_vlan_xlt_action.bf.dei_swap_cmd; - action->sdei_xlt_enable = in_vlan_xlt_action.bf.xlt_sdei_cmd; - action->sdei_xlt = in_vlan_xlt_action.bf.xlt_sdei; - action->cdei_xlt_enable = in_vlan_xlt_action.bf.xlt_cdei_cmd; - action->cdei_xlt = in_vlan_xlt_action.bf.xlt_cdei; - - action->counter_enable = in_vlan_xlt_action.bf.counter_en; - action->counter_id = in_vlan_xlt_action.bf.counter_id; - action->vsi_xlt_enable = in_vlan_xlt_action.bf.vsi_cmd; - action->vsi_xlt = in_vlan_xlt_action.bf.vsi; - - return in_vlan_xlt_rule.bf.valid; - } - else - { - /*rule part*/ - SW_RTN_ON_ERROR(hppe_eg_vlan_xlt_rule_get(dev_id, index, &eg_vlan_xlt_rule)); - if (!eg_vlan_xlt_rule.bf.valid) { - memset(&eg_vlan_xlt_rule, 0, sizeof(struct eg_vlan_xlt_rule)); - } - - rule->port_bitmap = eg_vlan_xlt_rule.bf.port_bitmap; - - rule->s_tagged = eg_vlan_xlt_rule.bf.skey_fmt; - rule->s_vid_enable = eg_vlan_xlt_rule.bf.skey_vid_incl; - rule->s_vid = eg_vlan_xlt_rule.bf.skey_vid; - rule->s_pcp_enable = eg_vlan_xlt_rule.bf.skey_pcp_incl; - rule->s_pcp = eg_vlan_xlt_rule.bf.skey_pcp; - rule->s_dei_enable = eg_vlan_xlt_rule.bf.skey_dei_incl; - rule->s_dei = eg_vlan_xlt_rule.bf.skey_dei; - - rule->c_tagged = eg_vlan_xlt_rule.bf.ckey_fmt; - rule->c_vid_enable = eg_vlan_xlt_rule.bf.ckey_vid_incl; - rule->c_vid = eg_vlan_xlt_rule.bf.ckey_vid; - rule->c_pcp_enable = eg_vlan_xlt_rule.bf.ckey_pcp_incl; - rule->c_pcp = eg_vlan_xlt_rule.bf.ckey_pcp; - rule->c_dei_enable = eg_vlan_xlt_rule.bf.ckey_dei_incl; - rule->c_dei = eg_vlan_xlt_rule.bf.ckey_dei; - - rule->vsi_valid = eg_vlan_xlt_rule.bf.vsi_valid; - rule->vsi_enable = eg_vlan_xlt_rule.bf.vsi_incl; - rule->vsi = eg_vlan_xlt_rule.bf.vsi; - - /*action part*/ - SW_RTN_ON_ERROR(hppe_eg_vlan_xlt_action_get(dev_id, index, &eg_vlan_xlt_action)); - if (!eg_vlan_xlt_rule.bf.valid) { - memset(&eg_vlan_xlt_action, 0, sizeof(struct eg_vlan_xlt_action)); - } - - action->swap_svid_cvid = eg_vlan_xlt_action.bf.vid_swap_cmd; - action->svid_xlt_cmd = eg_vlan_xlt_action.bf.xlt_svid_cmd; - action->svid_xlt = eg_vlan_xlt_action.bf.xlt_svid; - action->cvid_xlt_cmd = eg_vlan_xlt_action.bf.xlt_cvid_cmd; - action->cvid_xlt = eg_vlan_xlt_action.bf.xlt_cvid; - - action->swap_spcp_cpcp = eg_vlan_xlt_action.bf.pcp_swap_cmd; - action->spcp_xlt_enable = eg_vlan_xlt_action.bf.xlt_spcp_cmd; - action->spcp_xlt = (eg_vlan_xlt_action.bf.xlt_spcp_0 | - (eg_vlan_xlt_action.bf.xlt_spcp_1 << 1)); - action->cpcp_xlt_enable = eg_vlan_xlt_action.bf.xlt_cpcp_cmd; - action->cpcp_xlt = eg_vlan_xlt_action.bf.xlt_cpcp; - - action->swap_sdei_cdei = eg_vlan_xlt_action.bf.dei_swap_cmd; - action->sdei_xlt_enable = eg_vlan_xlt_action.bf.xlt_sdei_cmd; - action->sdei_xlt = eg_vlan_xlt_action.bf.xlt_sdei; - action->cdei_xlt_enable = eg_vlan_xlt_action.bf.xlt_cdei_cmd; - action->cdei_xlt = eg_vlan_xlt_action.bf.xlt_cdei; - - action->counter_enable = eg_vlan_xlt_action.bf.counter_en; - action->counter_id = eg_vlan_xlt_action.bf.counter_id; - - return eg_vlan_xlt_rule.bf.valid; - } -} - -a_uint32_t -_check_if_rule_equal(fal_port_vlan_direction_t direction, fal_vlan_trans_adv_rule_t * rule1, - fal_vlan_trans_adv_rule_t * rule2) -{ - if (!(rule1->s_tagged == rule2->s_tagged && - rule1->s_vid_enable == rule2->s_vid_enable && rule1->s_vid == rule2->s_vid && - rule1->s_pcp_enable == rule2->s_pcp_enable && rule1->s_pcp == rule2->s_pcp && - rule1->s_dei_enable == rule2->s_dei_enable && rule1->s_dei == rule2->s_dei && - rule1->c_tagged == rule2->c_tagged && - rule1->c_vid_enable == rule2->c_vid_enable && rule1->c_vid == rule2->c_vid && - rule1->c_pcp_enable == rule2->c_pcp_enable && rule1->c_pcp == rule2->c_pcp && - rule1->c_dei_enable == rule2->c_dei_enable && rule1->c_dei == rule2->c_dei)) - return 1; - - if (direction == FAL_PORT_VLAN_INGRESS) - { - if (!(rule1->frmtype_enable == rule2->frmtype_enable && - rule1->frmtype == rule2->frmtype && - rule1->protocol_enable == rule2->protocol_enable && - rule1->protocol == rule2->protocol)) - return 1; - } - else - { - if (!(rule1->vsi_valid == rule2->vsi_valid && - rule1->vsi_enable == rule2->vsi_enable && - rule1->vsi == rule2->vsi)) - return 1; - } - - return 0; -} - -a_uint32_t -_check_if_action_equal(fal_port_vlan_direction_t direction, fal_vlan_trans_adv_action_t * action1, - fal_vlan_trans_adv_action_t * action2) -{ - if (!(action1->swap_svid_cvid == action2->swap_svid_cvid && - action1->svid_xlt_cmd == action2->svid_xlt_cmd && - action1->svid_xlt == action2->svid_xlt && - action1->cvid_xlt_cmd == action2->cvid_xlt_cmd && - action1->cvid_xlt == action2->cvid_xlt && - action1->swap_sdei_cdei == action2->swap_sdei_cdei && - action1->sdei_xlt_enable == action2->sdei_xlt_enable && - action1->sdei_xlt == action2->sdei_xlt && - action1->cdei_xlt_enable == action2->cdei_xlt_enable && - action1->cdei_xlt == action2->cdei_xlt && - action1->swap_spcp_cpcp == action2->swap_spcp_cpcp && - action1->spcp_xlt_enable == action2->spcp_xlt_enable && - action1->spcp_xlt == action2->spcp_xlt && - action1->cpcp_xlt_enable == action2->cpcp_xlt_enable && - action1->cpcp_xlt == action2->cpcp_xlt && - action1->counter_enable == action2->counter_enable && - action1->counter_id == action2->counter_id)) - return 1; - - if (direction == FAL_PORT_VLAN_INGRESS) - { - if (!(action1->vsi_xlt_enable == action2->vsi_xlt_enable && - action1->vsi_xlt == action2->vsi_xlt)) - return 1; - } - - return 0; -} - -a_uint32_t -_insert_vlan_trans_adv_rule_action(a_uint32_t dev_id, a_uint32_t index, - fal_port_vlan_direction_t direction, - fal_vlan_trans_adv_rule_t * rule, fal_vlan_trans_adv_action_t * action) -{ - a_uint32_t rtn = SW_OK; - union xlt_rule_tbl_u in_vlan_xlt_rule; - union eg_vlan_xlt_rule_u eg_vlan_xlt_rule; - union xlt_action_tbl_u in_vlan_xlt_action; - union eg_vlan_xlt_action_u eg_vlan_xlt_action; - - if (direction == FAL_PORT_VLAN_INGRESS) - { - in_vlan_xlt_rule.bf.valid = A_TRUE; - in_vlan_xlt_rule.bf.port_bitmap = rule->port_bitmap; - - in_vlan_xlt_rule.bf.skey_fmt = rule->s_tagged; - in_vlan_xlt_rule.bf.skey_vid_incl = rule->s_vid_enable; - in_vlan_xlt_rule.bf.skey_vid = rule->s_vid; - in_vlan_xlt_rule.bf.skey_pcp_incl = rule->s_pcp_enable; - in_vlan_xlt_rule.bf.skey_pcp = rule->s_pcp; - in_vlan_xlt_rule.bf.skey_dei_incl = rule->s_dei_enable; - in_vlan_xlt_rule.bf.skey_dei = rule->s_dei; - - in_vlan_xlt_rule.bf.ckey_fmt_0 = (rule->c_tagged & 0x1); - in_vlan_xlt_rule.bf.ckey_fmt_1 = (rule->c_tagged >> 1); - in_vlan_xlt_rule.bf.ckey_vid_incl = rule->c_vid_enable; - in_vlan_xlt_rule.bf.ckey_vid = rule->c_vid; - in_vlan_xlt_rule.bf.ckey_pcp_incl = rule->c_pcp_enable; - in_vlan_xlt_rule.bf.ckey_pcp = rule->c_pcp; - in_vlan_xlt_rule.bf.ckey_dei_incl = rule->c_dei_enable; - in_vlan_xlt_rule.bf.ckey_dei = rule->c_dei; - - in_vlan_xlt_rule.bf.prot_incl = rule->protocol_enable; - in_vlan_xlt_rule.bf.prot_value_0 = (rule->protocol & 0x7f); - in_vlan_xlt_rule.bf.prot_value_1 = (rule->protocol >> 7); - in_vlan_xlt_rule.bf.frm_type_incl = rule->frmtype_enable; - in_vlan_xlt_rule.bf.frm_type = rule->frmtype; - - SW_RTN_ON_ERROR(hppe_xlt_rule_tbl_set(dev_id, index, &in_vlan_xlt_rule)); - - /*action part*/ - in_vlan_xlt_action.bf.vid_swap_cmd = action->swap_svid_cvid; - in_vlan_xlt_action.bf.xlt_svid_cmd = action->svid_xlt_cmd; - in_vlan_xlt_action.bf.xlt_svid = action->svid_xlt; - in_vlan_xlt_action.bf.xlt_cvid_cmd = action->cvid_xlt_cmd; - in_vlan_xlt_action.bf.xlt_cvid = action->cvid_xlt; - - in_vlan_xlt_action.bf.pcp_swap_cmd = action->swap_spcp_cpcp; - in_vlan_xlt_action.bf.xlt_spcp_cmd = action->spcp_xlt_enable; - in_vlan_xlt_action.bf.xlt_spcp_0 = (action->spcp_xlt & 0x1); - in_vlan_xlt_action.bf.xlt_spcp_1 = (action->spcp_xlt >> 1); - in_vlan_xlt_action.bf.xlt_cpcp_cmd = action->cpcp_xlt_enable; - in_vlan_xlt_action.bf.xlt_cpcp = action->cpcp_xlt; - - in_vlan_xlt_action.bf.dei_swap_cmd = action->swap_sdei_cdei; - in_vlan_xlt_action.bf.xlt_cdei_cmd = action->cdei_xlt_enable; - in_vlan_xlt_action.bf.xlt_cdei = action->cdei_xlt; - in_vlan_xlt_action.bf.xlt_sdei_cmd = action->sdei_xlt_enable; - in_vlan_xlt_action.bf.xlt_sdei = action->sdei_xlt; - - in_vlan_xlt_action.bf.counter_en = action->counter_enable; - in_vlan_xlt_action.bf.counter_id = action->counter_id; - in_vlan_xlt_action.bf.vsi_cmd = action->vsi_xlt_enable; - in_vlan_xlt_action.bf.vsi = action->vsi_xlt; - - SW_RTN_ON_ERROR(hppe_xlt_action_tbl_set(dev_id, index, &in_vlan_xlt_action)); - } - else - { - eg_vlan_xlt_rule.bf.valid = A_TRUE; - eg_vlan_xlt_rule.bf.port_bitmap = rule->port_bitmap; - - eg_vlan_xlt_rule.bf.skey_fmt = rule->s_tagged; - eg_vlan_xlt_rule.bf.skey_vid_incl = rule->s_vid_enable; - eg_vlan_xlt_rule.bf.skey_vid = rule->s_vid; - eg_vlan_xlt_rule.bf.skey_pcp_incl = rule->s_pcp_enable; - eg_vlan_xlt_rule.bf.skey_pcp = rule->s_pcp; - eg_vlan_xlt_rule.bf.skey_dei_incl = rule->s_dei_enable; - eg_vlan_xlt_rule.bf.skey_dei = rule->s_dei; - - eg_vlan_xlt_rule.bf.ckey_fmt = rule->c_tagged; - eg_vlan_xlt_rule.bf.ckey_vid_incl = rule->c_vid_enable; - eg_vlan_xlt_rule.bf.ckey_vid = rule->c_vid; - eg_vlan_xlt_rule.bf.ckey_pcp_incl = rule->c_pcp_enable; - eg_vlan_xlt_rule.bf.ckey_pcp = rule->c_pcp; - eg_vlan_xlt_rule.bf.ckey_dei_incl = rule->c_dei_enable; - eg_vlan_xlt_rule.bf.ckey_dei = rule->c_dei; - - eg_vlan_xlt_rule.bf.vsi_valid = rule->vsi_valid; - eg_vlan_xlt_rule.bf.vsi_incl = rule->vsi_enable; - eg_vlan_xlt_rule.bf.vsi = rule->vsi; - - SW_RTN_ON_ERROR(hppe_eg_vlan_xlt_rule_set(dev_id, index, &eg_vlan_xlt_rule)); - - /*action part*/ - eg_vlan_xlt_action.bf.vid_swap_cmd = action->swap_svid_cvid; - eg_vlan_xlt_action.bf.xlt_svid_cmd = action->svid_xlt_cmd; - eg_vlan_xlt_action.bf.xlt_svid = action->svid_xlt; - eg_vlan_xlt_action.bf.xlt_cvid_cmd = action->cvid_xlt_cmd; - eg_vlan_xlt_action.bf.xlt_cvid = action->cvid_xlt; - - eg_vlan_xlt_action.bf.pcp_swap_cmd = action->swap_spcp_cpcp; - eg_vlan_xlt_action.bf.xlt_spcp_cmd = action->spcp_xlt_enable; - eg_vlan_xlt_action.bf.xlt_spcp_0 = (action->spcp_xlt & 0x1); - eg_vlan_xlt_action.bf.xlt_spcp_1 = (action->spcp_xlt >> 1); - eg_vlan_xlt_action.bf.xlt_cpcp_cmd = action->cpcp_xlt_enable; - eg_vlan_xlt_action.bf.xlt_cpcp = action->cpcp_xlt; - - eg_vlan_xlt_action.bf.dei_swap_cmd = action->swap_sdei_cdei; - eg_vlan_xlt_action.bf.xlt_sdei_cmd = action->sdei_xlt_enable; - eg_vlan_xlt_action.bf.xlt_sdei = action->sdei_xlt; - eg_vlan_xlt_action.bf.xlt_cdei_cmd = action->cdei_xlt_enable; - eg_vlan_xlt_action.bf.xlt_cdei = action->cdei_xlt; - - eg_vlan_xlt_action.bf.counter_en = action->counter_enable; - eg_vlan_xlt_action.bf.counter_id = action->counter_id; - - SW_RTN_ON_ERROR(hppe_eg_vlan_xlt_action_set(dev_id, index, &eg_vlan_xlt_action)); - } - - return rtn; -} - -sw_error_t -adpt_hppe_global_qinq_mode_set(a_uint32_t dev_id, fal_global_qinq_mode_t *mode) -{ - sw_error_t rtn = SW_OK; - - ADPT_DEV_ID_CHECK(dev_id); - - if (FAL_FLG_TST(mode->mask, FAL_GLOBAL_QINQ_MODE_INGRESS_EN)) { - SW_RTN_ON_ERROR(hppe_bridge_config_bridge_type_set(dev_id, - (a_uint32_t)mode->ingress_mode)); - } - - if (FAL_FLG_TST(mode->mask, FAL_GLOBAL_QINQ_MODE_EGRESS_EN)) { - SW_RTN_ON_ERROR(hppe_eg_bridge_config_bridge_type_set(dev_id, - (a_uint32_t)mode->egress_mode)); - } - - if (FAL_FLG_TST(mode->mask, FAL_GLOBAL_QINQ_MODE_EGRESS_UNTOUCHED_FOR_CPU_CODE)) { - SW_RTN_ON_ERROR(hppe_eg_bridge_config_pkt_l2_edit_en_set(dev_id, - (a_uint32_t)!mode->untouched_for_cpucode)); - } - return rtn; -} - -sw_error_t -adpt_hppe_global_qinq_mode_get(a_uint32_t dev_id, fal_global_qinq_mode_t *mode) -{ - sw_error_t rtn = SW_OK; - a_uint32_t l2_edit_en = 0; - - ADPT_DEV_ID_CHECK(dev_id); - ADPT_NULL_POINT_CHECK(mode); - - SW_RTN_ON_ERROR(hppe_bridge_config_bridge_type_get(dev_id, - (a_uint32_t *)&mode->ingress_mode)); - - SW_RTN_ON_ERROR(hppe_eg_bridge_config_bridge_type_get(dev_id, - (a_uint32_t *)&mode->egress_mode)); - - SW_RTN_ON_ERROR(hppe_eg_bridge_config_pkt_l2_edit_en_get(dev_id, &l2_edit_en)); - - mode->untouched_for_cpucode = !l2_edit_en; - - return rtn; -} - -sw_error_t -adpt_hppe_port_qinq_mode_set(a_uint32_t dev_id, fal_port_t port_id, fal_port_qinq_role_t *mode) -{ - sw_error_t rtn = SW_OK; - - ADPT_DEV_ID_CHECK(dev_id); - - if (FAL_FLG_TST(mode->mask, FAL_PORT_QINQ_ROLE_INGRESS_EN)) { - SW_RTN_ON_ERROR(hppe_port_parsing_reg_port_role_set(dev_id, port_id, - (a_uint32_t)mode->ingress_port_role)); - } - - if (FAL_FLG_TST(mode->mask, FAL_PORT_QINQ_ROLE_EGRESS_EN)) { - SW_RTN_ON_ERROR(hppe_port_eg_vlan_port_vlan_type_set(dev_id, port_id, - (a_uint32_t)mode->egress_port_role)); - } - - return rtn; -} - -sw_error_t -adpt_hppe_port_qinq_mode_get(a_uint32_t dev_id, fal_port_t port_id, fal_port_qinq_role_t *mode) -{ - sw_error_t rtn = SW_OK; - - ADPT_DEV_ID_CHECK(dev_id); - ADPT_NULL_POINT_CHECK(mode); - - SW_RTN_ON_ERROR(hppe_port_parsing_reg_port_role_get(dev_id, port_id, - (a_uint32_t *)&mode->ingress_port_role)); - - SW_RTN_ON_ERROR(hppe_port_eg_vlan_port_vlan_type_get(dev_id, port_id, - (a_uint32_t *)&mode->egress_port_role)); - - return rtn; -} - -sw_error_t -adpt_hppe_tpid_set(a_uint32_t dev_id, fal_tpid_t *tpid) -{ - sw_error_t rtn = SW_OK; - union edma_vlan_tpid_reg_u edma_tpid; - union vlan_tpid_reg_u ppe_tpid; - - ADPT_DEV_ID_CHECK(dev_id); - - rtn = hppe_edma_vlan_tpid_reg_get(dev_id, &edma_tpid); - SW_RTN_ON_ERROR(rtn); - - rtn = hppe_vlan_tpid_reg_get(dev_id, &ppe_tpid); - SW_RTN_ON_ERROR(rtn); - - if (FAL_FLG_TST(tpid->mask, FAL_TPID_CTAG_EN)) { - edma_tpid.bf.ctag_tpid = tpid->ctpid; - ppe_tpid.bf.ctag_tpid = tpid->ctpid; - } - - if (FAL_FLG_TST(tpid->mask, FAL_TPID_STAG_EN)) { - edma_tpid.bf.stag_tpid = tpid->stpid; - ppe_tpid.bf.stag_tpid = tpid->stpid; - } - - rtn = hppe_edma_vlan_tpid_reg_set(dev_id, &edma_tpid); - SW_RTN_ON_ERROR(rtn); - - rtn = hppe_vlan_tpid_reg_set(dev_id, &ppe_tpid); - - return rtn; -} - -sw_error_t -adpt_hppe_tpid_get(a_uint32_t dev_id, fal_tpid_t *tpid) -{ - sw_error_t rtn = SW_OK; - union vlan_tpid_reg_u ppe_tpid; - - ADPT_DEV_ID_CHECK(dev_id); - ADPT_NULL_POINT_CHECK(tpid); - - rtn = hppe_vlan_tpid_reg_get(dev_id, &ppe_tpid); - SW_RTN_ON_ERROR(rtn); - - tpid->ctpid = ppe_tpid.bf.ctag_tpid; - tpid->stpid = ppe_tpid.bf.stag_tpid; - - return rtn; -} - -sw_error_t -adpt_hppe_egress_tpid_set(a_uint32_t dev_id, fal_tpid_t *tpid) -{ - sw_error_t rtn = SW_OK; - - ADPT_DEV_ID_CHECK(dev_id); - - if (FAL_FLG_TST(tpid->mask, FAL_TPID_CTAG_EN)) { - SW_RTN_ON_ERROR(hppe_eg_vlan_tpid_ctpid_set(dev_id, - (a_uint32_t)tpid->ctpid)); - } - - if (FAL_FLG_TST(tpid->mask, FAL_TPID_STAG_EN)) { - SW_RTN_ON_ERROR(hppe_eg_vlan_tpid_stpid_set(dev_id, - (a_uint32_t)tpid->stpid)); - } - - return rtn; -} - -sw_error_t -adpt_hppe_egress_tpid_get(a_uint32_t dev_id, fal_tpid_t *tpid) -{ - sw_error_t rtn = SW_OK; - - ADPT_DEV_ID_CHECK(dev_id); - ADPT_NULL_POINT_CHECK(tpid); - - SW_RTN_ON_ERROR(hppe_eg_vlan_tpid_ctpid_get(dev_id, - (a_uint32_t *)&tpid->ctpid)); - - SW_RTN_ON_ERROR(hppe_eg_vlan_tpid_stpid_get(dev_id, - (a_uint32_t *)&tpid->stpid)); - - return rtn; -} - -sw_error_t -adpt_hppe_port_ingress_vlan_filter_set(a_uint32_t dev_id, fal_port_t port_id, - fal_ingress_vlan_filter_t *filter) -{ - sw_error_t rtn = SW_OK; - - ADPT_DEV_ID_CHECK(dev_id); - - SW_RTN_ON_ERROR(hppe_port_vlan_config_port_in_vlan_fltr_cmd_set(dev_id, - port_id, (a_uint32_t)filter->membership_filter)); - SW_RTN_ON_ERROR(hppe_port_vlan_config_port_untag_fltr_cmd_set(dev_id, - port_id, (a_uint32_t)filter->untagged_filter)); - SW_RTN_ON_ERROR(hppe_port_vlan_config_port_tag_fltr_cmd_set(dev_id, - port_id, (a_uint32_t)filter->tagged_filter)); - SW_RTN_ON_ERROR(hppe_port_vlan_config_port_pri_tag_fltr_cmd_set(dev_id, - port_id, (a_uint32_t)filter->priority_filter)); - - return rtn; -} - -sw_error_t -adpt_hppe_port_ingress_vlan_filter_get(a_uint32_t dev_id, fal_port_t port_id, - fal_ingress_vlan_filter_t *filter) -{ - sw_error_t rtn = SW_OK; - - ADPT_DEV_ID_CHECK(dev_id); - ADPT_NULL_POINT_CHECK(filter); - - SW_RTN_ON_ERROR(hppe_port_vlan_config_port_in_vlan_fltr_cmd_get(dev_id, - port_id, (a_uint32_t *)&filter->membership_filter)); - SW_RTN_ON_ERROR(hppe_port_vlan_config_port_untag_fltr_cmd_get(dev_id, - port_id, (a_uint32_t *)&filter->untagged_filter)); - SW_RTN_ON_ERROR(hppe_port_vlan_config_port_tag_fltr_cmd_get(dev_id, - port_id, (a_uint32_t *)&filter->tagged_filter)); - SW_RTN_ON_ERROR(hppe_port_vlan_config_port_pri_tag_fltr_cmd_get(dev_id, - port_id, (a_uint32_t *)&filter->priority_filter)); - - return rtn; -} - -sw_error_t -adpt_hppe_port_default_vlantag_set(a_uint32_t dev_id, - fal_port_t port_id, fal_port_vlan_direction_t direction, - fal_port_default_vid_enable_t *default_vid_en, fal_port_vlan_tag_t *default_tag) -{ - sw_error_t rtn = SW_OK; - - ADPT_DEV_ID_CHECK(dev_id); - - if (direction == FAL_PORT_VLAN_EGRESS) - { - if (!FAL_FLG_TST(default_tag->mask, FAL_PORT_VLAN_TAG_CVID_EN) && - !FAL_FLG_TST(default_tag->mask, FAL_PORT_VLAN_TAG_SVID_EN)) - return SW_NOT_SUPPORTED; - } - - if (direction == FAL_PORT_VLAN_ALL || direction == FAL_PORT_VLAN_INGRESS) - { - SW_RTN_ON_ERROR(hppe_port_def_vid_port_def_cvid_en_set(dev_id, port_id, - (a_uint32_t)default_vid_en->default_cvid_en)); - SW_RTN_ON_ERROR(hppe_port_def_vid_port_def_svid_en_set(dev_id, port_id, - (a_uint32_t)default_vid_en->default_svid_en)); - - if (FAL_FLG_TST(default_tag->mask, FAL_PORT_VLAN_TAG_CVID_EN)) { - SW_RTN_ON_ERROR(hppe_port_def_vid_port_def_cvid_set(dev_id, port_id, - (a_uint32_t)default_tag->cvid)); - } - - if (FAL_FLG_TST(default_tag->mask, FAL_PORT_VLAN_TAG_SVID_EN)) { - SW_RTN_ON_ERROR(hppe_port_def_vid_port_def_svid_set(dev_id, port_id, - (a_uint32_t)default_tag->svid)); - } - - if (FAL_FLG_TST(default_tag->mask, FAL_PORT_VLAN_TAG_CPCP_EN)) { - SW_RTN_ON_ERROR(hppe_port_def_pcp_port_def_cpcp_set(dev_id, port_id, - (a_uint32_t)default_tag->cpri)); - } - - if (FAL_FLG_TST(default_tag->mask, FAL_PORT_VLAN_TAG_SPCP_EN)) { - SW_RTN_ON_ERROR(hppe_port_def_pcp_port_def_spcp_set(dev_id, port_id, - (a_uint32_t)default_tag->spri)); - } - - if (FAL_FLG_TST(default_tag->mask, FAL_PORT_VLAN_TAG_CDEI_EN)) { - SW_RTN_ON_ERROR(hppe_port_def_pcp_port_def_cdei_set(dev_id, port_id, - (a_uint32_t)default_tag->cdei)); - } - - if (FAL_FLG_TST(default_tag->mask, FAL_PORT_VLAN_TAG_SDEI_EN)) { - SW_RTN_ON_ERROR(hppe_port_def_pcp_port_def_sdei_set(dev_id, port_id, - (a_uint32_t)default_tag->sdei)); - } - } - - if (direction == FAL_PORT_VLAN_ALL || direction == FAL_PORT_VLAN_EGRESS) - { - SW_RTN_ON_ERROR(hppe_port_eg_def_vid_port_def_cvid_en_set(dev_id, - port_id, (a_uint32_t)default_vid_en->default_cvid_en)); - SW_RTN_ON_ERROR(hppe_port_eg_def_vid_port_def_svid_en_set(dev_id, - port_id, (a_uint32_t)default_vid_en->default_svid_en)); - - if (FAL_FLG_TST(default_tag->mask, FAL_PORT_VLAN_TAG_CVID_EN)) { - SW_RTN_ON_ERROR(hppe_port_eg_def_vid_port_def_cvid_set(dev_id, port_id, - (a_uint32_t)default_tag->cvid)); - } - - if (FAL_FLG_TST(default_tag->mask, FAL_PORT_VLAN_TAG_SVID_EN)) { - SW_RTN_ON_ERROR(hppe_port_eg_def_vid_port_def_svid_set(dev_id, port_id, - (a_uint32_t)default_tag->svid)); - } - } - - return rtn; -} - -sw_error_t -adpt_hppe_port_default_vlantag_get(a_uint32_t dev_id, - fal_port_t port_id, fal_port_vlan_direction_t direction, - fal_port_default_vid_enable_t *default_vid_en, fal_port_vlan_tag_t *default_tag) -{ - sw_error_t rtn = SW_OK; - - ADPT_DEV_ID_CHECK(dev_id); - ADPT_NULL_POINT_CHECK(default_vid_en); - ADPT_NULL_POINT_CHECK(default_tag); - - if (direction == FAL_PORT_VLAN_ALL) - return SW_NOT_SUPPORTED; - - if (direction == FAL_PORT_VLAN_INGRESS) { - SW_RTN_ON_ERROR(hppe_port_def_vid_port_def_cvid_en_get(dev_id, port_id, - (a_uint32_t *)&default_vid_en->default_cvid_en)); - - SW_RTN_ON_ERROR(hppe_port_def_vid_port_def_svid_en_get(dev_id, port_id, - (a_uint32_t *)&default_vid_en->default_svid_en)); - - SW_RTN_ON_ERROR(hppe_port_def_vid_port_def_cvid_get(dev_id, port_id, - (a_uint32_t *)&default_tag->cvid)); - - SW_RTN_ON_ERROR(hppe_port_def_vid_port_def_svid_get(dev_id, port_id, - (a_uint32_t *)&default_tag->svid)); - - SW_RTN_ON_ERROR(hppe_port_def_pcp_port_def_cpcp_get(dev_id, port_id, - (a_uint32_t *)&default_tag->cpri)); - - SW_RTN_ON_ERROR(hppe_port_def_pcp_port_def_spcp_get(dev_id, port_id, - (a_uint32_t *)&default_tag->spri)); - - SW_RTN_ON_ERROR(hppe_port_def_pcp_port_def_cdei_get(dev_id, port_id, - (a_uint32_t *)&default_tag->cdei)); - - SW_RTN_ON_ERROR(hppe_port_def_pcp_port_def_sdei_get(dev_id, port_id, - (a_uint32_t *)&default_tag->sdei)); - } - else if (direction == FAL_PORT_VLAN_EGRESS) { - SW_RTN_ON_ERROR(hppe_port_eg_def_vid_port_def_cvid_en_get(dev_id, port_id, - (a_uint32_t *)&default_vid_en->default_cvid_en)); - - SW_RTN_ON_ERROR(hppe_port_eg_def_vid_port_def_svid_en_get(dev_id, port_id, - (a_uint32_t *)&default_vid_en->default_svid_en)); - - SW_RTN_ON_ERROR(hppe_port_eg_def_vid_port_def_cvid_get(dev_id, port_id, - (a_uint32_t *)&default_tag->cvid)); - - SW_RTN_ON_ERROR(hppe_port_eg_def_vid_port_def_svid_get(dev_id, port_id, - (a_uint32_t *)&default_tag->svid)); - - } - else - return SW_NOT_SUPPORTED; - - return rtn; -} - -sw_error_t -adpt_hppe_port_tag_propagation_set(a_uint32_t dev_id, - fal_port_t port_id, fal_port_vlan_direction_t direction, - fal_vlantag_propagation_t *prop) -{ - sw_error_t rtn = SW_OK; - a_uint32_t value_pcp, value_dei = 0; - - ADPT_DEV_ID_CHECK(dev_id); - - if (prop->pri_propagation == FAL_VLAN_PROPAGATION_DISABLE) - value_pcp = 0; - else if (prop->pri_propagation == FAL_VLAN_PROPAGATION_CLONE) - value_pcp = 1; - else - return SW_NOT_SUPPORTED; - - if (prop->dei_propagation == FAL_VLAN_PROPAGATION_DISABLE) - value_dei = 0; - else if (prop->dei_propagation == FAL_VLAN_PROPAGATION_CLONE) - value_dei = 1; - else - return SW_NOT_SUPPORTED; - - if (direction == FAL_PORT_VLAN_ALL || direction == FAL_PORT_VLAN_INGRESS) - { - if (FAL_FLG_TST(prop->mask, FAL_PORT_PROPAGATION_PCP_EN)) { - SW_RTN_ON_ERROR(hppe_port_vlan_config_port_in_pcp_prop_cmd_set(dev_id, - port_id, value_pcp)); - } - if (FAL_FLG_TST(prop->mask, FAL_PORT_PROPAGATION_DEI_EN)) { - SW_RTN_ON_ERROR(hppe_port_vlan_config_port_in_dei_prop_cmd_set(dev_id, - port_id, value_dei)); - } - } - - if (direction == FAL_PORT_VLAN_ALL || direction == FAL_PORT_VLAN_EGRESS) - { - if (FAL_FLG_TST(prop->mask, FAL_PORT_PROPAGATION_PCP_EN)) { - SW_RTN_ON_ERROR(hppe_port_eg_vlan_port_eg_pcp_prop_cmd_set(dev_id, - port_id, value_pcp)); - } - if (FAL_FLG_TST(prop->mask, FAL_PORT_PROPAGATION_DEI_EN)) { - SW_RTN_ON_ERROR(hppe_port_eg_vlan_port_eg_dei_prop_cmd_set(dev_id, - port_id, value_dei)); - } - } - - return rtn; -} - -sw_error_t -adpt_hppe_port_tag_propagation_get(a_uint32_t dev_id, - fal_port_t port_id, fal_port_vlan_direction_t direction, - fal_vlantag_propagation_t *prop) -{ - sw_error_t rtn = SW_OK; - a_uint32_t value_pcp = 0, value_dei = 0; - - ADPT_DEV_ID_CHECK(dev_id); - ADPT_NULL_POINT_CHECK(prop); - - if (direction == FAL_PORT_VLAN_ALL) - return SW_NOT_SUPPORTED; - - if (direction == FAL_PORT_VLAN_INGRESS) { - SW_RTN_ON_ERROR(hppe_port_vlan_config_port_in_pcp_prop_cmd_get(dev_id, - port_id, &value_pcp)); - - SW_RTN_ON_ERROR(hppe_port_vlan_config_port_in_dei_prop_cmd_get(dev_id, - port_id, &value_dei)); - } - else if (direction == FAL_PORT_VLAN_EGRESS) { - SW_RTN_ON_ERROR(hppe_port_eg_vlan_port_eg_pcp_prop_cmd_get(dev_id, - port_id, &value_pcp)); - - SW_RTN_ON_ERROR(hppe_port_eg_vlan_port_eg_dei_prop_cmd_get(dev_id, - port_id, &value_dei)); - } - else - return SW_NOT_SUPPORTED; - - if (value_pcp == 0) - prop->pri_propagation = FAL_VLAN_PROPAGATION_DISABLE; - else if (value_pcp == 1) - prop->pri_propagation = FAL_VLAN_PROPAGATION_CLONE; - else - return SW_FAIL; - - if (value_dei == 0) - prop->dei_propagation = FAL_VLAN_PROPAGATION_DISABLE; - else if (value_dei == 1) - prop->dei_propagation = FAL_VLAN_PROPAGATION_CLONE; - else - return SW_FAIL; - - - return rtn; -} - -sw_error_t -adpt_hppe_port_vlantag_egmode_set(a_uint32_t dev_id, fal_port_t port_id, - fal_vlantag_egress_mode_t *port_egvlanmode) -{ - sw_error_t rtn = SW_OK; - a_uint32_t value = 0; - - ADPT_DEV_ID_CHECK(dev_id); - - if (FAL_FLG_TST(port_egvlanmode->mask, FAL_EGRESSMODE_CTAG_EN)) { - if (port_egvlanmode->ctag_mode == FAL_EG_UNMODIFIED) { - value = 2; - } else if (port_egvlanmode->ctag_mode == FAL_EG_UNTOUCHED) { - value = 3; - } else if (port_egvlanmode->ctag_mode == FAL_EG_UNTAGGED) { - value = 0; - } else if (port_egvlanmode->ctag_mode == FAL_EG_TAGGED) { - value = 1; - } else { - return SW_FAIL; - } - - SW_RTN_ON_ERROR(hppe_port_eg_vlan_port_eg_vlan_ctag_mode_set(dev_id, - port_id, value)); - } - - if (FAL_FLG_TST(port_egvlanmode->mask, FAL_EGRESSMODE_STAG_EN)) { - if (port_egvlanmode->stag_mode == FAL_EG_UNMODIFIED) { - value = 2; - } else if (port_egvlanmode->stag_mode == FAL_EG_UNTOUCHED) { - value = 3; - } else if (port_egvlanmode->stag_mode == FAL_EG_UNTAGGED) { - value = 0; - } else if (port_egvlanmode->stag_mode == FAL_EG_TAGGED) { - value = 1; - } else { - return SW_FAIL; - } - - SW_RTN_ON_ERROR(hppe_port_eg_vlan_port_eg_vlan_stag_mode_set(dev_id, - port_id, value)); - } - - return rtn; -} - -sw_error_t -adpt_hppe_port_vlantag_egmode_get(a_uint32_t dev_id, fal_port_t port_id, - fal_vlantag_egress_mode_t *port_egvlanmode) -{ - sw_error_t rtn = SW_OK; - a_uint32_t value = 0; - - ADPT_DEV_ID_CHECK(dev_id); - ADPT_NULL_POINT_CHECK(port_egvlanmode); - - - SW_RTN_ON_ERROR(hppe_port_eg_vlan_port_eg_vlan_ctag_mode_get(dev_id, - port_id, &value)); - - if (value == 2) { - port_egvlanmode->ctag_mode = FAL_EG_UNMODIFIED; - } else if (value == 3) { - port_egvlanmode->ctag_mode = FAL_EG_UNTOUCHED; - } else if (value == 0) { - port_egvlanmode->ctag_mode = FAL_EG_UNTAGGED; - } else if (value == 1) { - port_egvlanmode->ctag_mode = FAL_EG_TAGGED; - } else { - return SW_FAIL; - } - - SW_RTN_ON_ERROR(hppe_port_eg_vlan_port_eg_vlan_stag_mode_get(dev_id, - port_id, &value)); - - if (value == 2) { - port_egvlanmode->stag_mode = FAL_EG_UNMODIFIED; - } else if (value == 3) { - port_egvlanmode->stag_mode = FAL_EG_UNTOUCHED; - } else if (value == 0) { - port_egvlanmode->stag_mode = FAL_EG_UNTAGGED; - } else if (value == 1) { - port_egvlanmode->stag_mode = FAL_EG_TAGGED; - } else { - return SW_FAIL; - } - - return rtn; -} - -sw_error_t -adpt_hppe_port_vlan_xlt_miss_cmd_set(a_uint32_t dev_id, fal_port_t port_id, - fal_fwd_cmd_t cmd) -{ - sw_error_t rtn = SW_OK; - a_uint32_t value = 0; - - ADPT_DEV_ID_CHECK(dev_id); - - if (cmd == FAL_MAC_FRWRD) { - value = 0; - } else if (cmd == FAL_MAC_DROP) { - value = 1; - } else if (cmd == FAL_MAC_CPY_TO_CPU) { - value = 2; - } else if (cmd == FAL_MAC_RDT_TO_CPU) { - value = 3; - } else { - return SW_FAIL; - } - - SW_RTN_ON_ERROR(hppe_port_vlan_config_port_vlan_xlt_miss_fwd_cmd_set(dev_id, - port_id, value)); - - return rtn; -} - -sw_error_t -adpt_hppe_port_vlan_xlt_miss_cmd_get(a_uint32_t dev_id, fal_port_t port_id, - fal_fwd_cmd_t *cmd) -{ - sw_error_t rtn = SW_OK; - a_uint32_t value = 0; - - ADPT_DEV_ID_CHECK(dev_id); - ADPT_NULL_POINT_CHECK(cmd); - - SW_RTN_ON_ERROR(hppe_port_vlan_config_port_vlan_xlt_miss_fwd_cmd_get(dev_id, - port_id, &value)); - - if (value == 0) { - *cmd = FAL_MAC_FRWRD; - } else if (value == 1) { - *cmd = FAL_MAC_DROP; - } else if (value == 2) { - *cmd = FAL_MAC_CPY_TO_CPU; - } else if (value == 3) { - *cmd = FAL_MAC_RDT_TO_CPU; - } else { - return SW_FAIL; - } - - return rtn; -} - -#ifndef IN_PORTVLAN_MINI -sw_error_t -adpt_hppe_port_vlan_trans_iterate(a_uint32_t dev_id, fal_port_t port_id, - a_uint32_t * iterator, fal_vlan_trans_entry_t *entry) -{ - a_uint32_t idx, eg_tbl_num, rule_valid; - - ADPT_DEV_ID_CHECK(dev_id); - ADPT_NULL_POINT_CHECK(iterator); - ADPT_NULL_POINT_CHECK(entry); - - eg_tbl_num = XLT_RULE_TBL_NUM * 2; - - if (*iterator < XLT_RULE_TBL_NUM) { - for (idx = *iterator; idx < XLT_RULE_TBL_NUM; idx++) { - aos_mem_zero(entry, sizeof (fal_vlan_trans_entry_t)); - rule_valid = _get_port_vlan_ingress_trans_by_index(dev_id, idx, entry); - if (rule_valid == 1) { - if (SW_IS_PBMP_MEMBER(entry->port_bitmap, port_id)) - break; - } - } - - if (idx == XLT_RULE_TBL_NUM) - return SW_NO_MORE; - } - else if (*iterator < eg_tbl_num) { - for (idx = *iterator; idx < eg_tbl_num; idx++) { - aos_mem_zero(entry, sizeof (fal_vlan_trans_entry_t)); - rule_valid = _get_port_vlan_egress_trans_by_index(dev_id, - idx - XLT_RULE_TBL_NUM, entry); - if (rule_valid == 1) { - if (SW_IS_PBMP_MEMBER(entry->port_bitmap, port_id)) - break; - } - } - - if (idx == eg_tbl_num) - return SW_NO_MORE; - } - else { - return SW_OUT_OF_RANGE; - } - - *iterator = idx + 1; - - return SW_OK; -} - -sw_error_t -adpt_hppe_port_vlan_trans_add(a_uint32_t dev_id, fal_port_t port_id, fal_vlan_trans_entry_t *entry) -{ - sw_error_t rtn = SW_OK; - union xlt_rule_tbl_u in_vlan_xlt_rule; - union eg_vlan_xlt_rule_u eg_vlan_xlt_rule; - union xlt_action_tbl_u in_vlan_xlt_action; - union eg_vlan_xlt_action_u eg_vlan_xlt_action; - a_uint32_t idx, entry_idx, entry_sign, rule_valid; - fal_vlan_trans_entry_t temp; - - ADPT_DEV_ID_CHECK(dev_id); - ADPT_NULL_POINT_CHECK(entry); - - entry_idx = 0; - - if (entry->trans_direction == 0) { - /*rule part*/ - entry_sign = 0; - for (idx = 0; idx < XLT_RULE_TBL_NUM; idx++) { - aos_mem_zero(&temp, sizeof (fal_vlan_trans_entry_t)); - rule_valid = _get_port_vlan_ingress_trans_by_index(dev_id, idx, &temp); - if (rule_valid == 1) { - if (!aos_mem_cmp(entry, &temp, sizeof (fal_vlan_trans_entry_t))) { - if (SW_IS_PBMP_MEMBER(temp.port_bitmap, port_id)) - return SW_ALREADY_EXIST; - entry_idx = idx; - entry_sign = 1; - break; - } - } - else { - if (entry_sign == 0) { - entry_idx = idx; - entry_sign = 1; - } - } - } - - if (entry_sign == 0) - return SW_NO_RESOURCE; - - in_vlan_xlt_rule.bf.valid = A_TRUE; - in_vlan_xlt_rule.bf.port_bitmap = entry->port_bitmap | (0x1 << port_id); - - in_vlan_xlt_rule.bf.prot_incl = entry->protocol_enable; - in_vlan_xlt_rule.bf.prot_value_0 = (entry->protocol & 0x7f); - in_vlan_xlt_rule.bf.prot_value_1 = (entry->protocol >> 7); - in_vlan_xlt_rule.bf.frm_type_incl = entry->frmtype_enable; - in_vlan_xlt_rule.bf.frm_type = entry->frmtype; - - in_vlan_xlt_rule.bf.ckey_fmt_0 = (entry->c_tagged & 0x1); - in_vlan_xlt_rule.bf.ckey_fmt_1 = (entry->c_tagged >> 1); - in_vlan_xlt_rule.bf.skey_fmt = entry->s_tagged; - - in_vlan_xlt_rule.bf.ckey_vid_incl = entry->c_vid_enable; - in_vlan_xlt_rule.bf.ckey_vid = entry->c_vid; - in_vlan_xlt_rule.bf.ckey_pcp_incl = entry->c_pcp_enable; - in_vlan_xlt_rule.bf.ckey_pcp = entry->c_pcp; - in_vlan_xlt_rule.bf.ckey_dei_incl = entry->c_dei_enable; - in_vlan_xlt_rule.bf.ckey_dei = entry->c_dei; - - in_vlan_xlt_rule.bf.skey_vid_incl = entry->s_vid_enable; - in_vlan_xlt_rule.bf.skey_vid = entry->s_vid; - in_vlan_xlt_rule.bf.skey_pcp_incl = entry->s_pcp_enable; - in_vlan_xlt_rule.bf.skey_pcp = entry->s_pcp; - in_vlan_xlt_rule.bf.skey_dei_incl = entry->s_dei_enable; - in_vlan_xlt_rule.bf.skey_dei = entry->s_dei; - - SW_RTN_ON_ERROR(hppe_xlt_rule_tbl_set(dev_id, entry_idx, &in_vlan_xlt_rule)); - - /*action part*/ - in_vlan_xlt_action.bf.counter_en = entry->counter_enable; - in_vlan_xlt_action.bf.counter_id = entry->counter_id; - in_vlan_xlt_action.bf.vsi_cmd = entry->vsi_action_enable; - in_vlan_xlt_action.bf.vsi = entry->vsi_action; - - in_vlan_xlt_action.bf.xlt_cdei_cmd = entry->cdei_xlt_enable; - in_vlan_xlt_action.bf.xlt_cdei = entry->cdei_xlt; - in_vlan_xlt_action.bf.xlt_sdei_cmd = entry->sdei_xlt_enable; - in_vlan_xlt_action.bf.xlt_sdei = entry->sdei_xlt; - in_vlan_xlt_action.bf.dei_swap_cmd = entry->swap_sdei_cdei; - - in_vlan_xlt_action.bf.xlt_cpcp_cmd = entry->cpcp_xlt_enable; - in_vlan_xlt_action.bf.xlt_cpcp = entry->cpcp_xlt; - in_vlan_xlt_action.bf.xlt_spcp_cmd = entry->spcp_xlt_enable; - in_vlan_xlt_action.bf.xlt_spcp_0 = (entry->spcp_xlt & 0x1); - in_vlan_xlt_action.bf.xlt_spcp_1 = (entry->spcp_xlt >> 1); - in_vlan_xlt_action.bf.pcp_swap_cmd = entry->swap_spcp_cpcp; - - in_vlan_xlt_action.bf.xlt_cvid_cmd = entry->cvid_xlt_cmd; - in_vlan_xlt_action.bf.xlt_cvid = entry->cvid_xlt; - in_vlan_xlt_action.bf.xlt_svid_cmd = entry->svid_xlt_cmd; - in_vlan_xlt_action.bf.xlt_svid = entry->svid_xlt; - in_vlan_xlt_action.bf.vid_swap_cmd = entry->swap_svid_cvid; - - SW_RTN_ON_ERROR(hppe_xlt_action_tbl_set(dev_id, entry_idx, &in_vlan_xlt_action)); - } - else { - /*rule part*/ - entry_sign = 0; - for (idx = 0; idx < XLT_RULE_TBL_NUM; idx++) { - aos_mem_zero(&temp, sizeof (fal_vlan_trans_entry_t)); - rule_valid = _get_port_vlan_egress_trans_by_index(dev_id, idx, &temp); - if (rule_valid == 1) { - if (!aos_mem_cmp(entry, &temp, sizeof (fal_vlan_trans_entry_t))) { - if (SW_IS_PBMP_MEMBER(temp.port_bitmap, port_id)) - return SW_ALREADY_EXIST; - entry_idx = idx; - entry_sign = 1; - break; - } - } - else { - if (entry_sign == 0) { - entry_idx = idx; - entry_sign = 1; - } - } - } - - if (entry_sign == 0) - return SW_NO_RESOURCE; - - eg_vlan_xlt_rule.bf.valid = A_TRUE; - eg_vlan_xlt_rule.bf.port_bitmap = entry->port_bitmap | (0x1 << port_id); - - eg_vlan_xlt_rule.bf.vsi_incl = entry->vsi_enable; - eg_vlan_xlt_rule.bf.vsi = entry->vsi; - eg_vlan_xlt_rule.bf.vsi_valid = entry->vsi_valid; - - eg_vlan_xlt_rule.bf.ckey_fmt = entry->c_tagged; - eg_vlan_xlt_rule.bf.skey_fmt = entry->s_tagged; - - eg_vlan_xlt_rule.bf.ckey_vid_incl = entry->c_vid_enable; - eg_vlan_xlt_rule.bf.ckey_vid = entry->c_vid; - eg_vlan_xlt_rule.bf.ckey_pcp_incl = entry->c_pcp_enable; - eg_vlan_xlt_rule.bf.ckey_pcp = entry->c_pcp; - eg_vlan_xlt_rule.bf.ckey_dei_incl = entry->c_dei_enable; - eg_vlan_xlt_rule.bf.ckey_dei = entry->c_dei; - - eg_vlan_xlt_rule.bf.skey_vid_incl = entry->s_vid_enable; - eg_vlan_xlt_rule.bf.skey_vid = entry->s_vid; - eg_vlan_xlt_rule.bf.skey_pcp_incl = entry->s_pcp_enable; - eg_vlan_xlt_rule.bf.skey_pcp = entry->s_pcp; - eg_vlan_xlt_rule.bf.skey_dei_incl = entry->s_dei_enable; - eg_vlan_xlt_rule.bf.skey_dei = entry->s_dei; - - SW_RTN_ON_ERROR(hppe_eg_vlan_xlt_rule_set(dev_id, entry_idx, &eg_vlan_xlt_rule)); - - /*action part*/ - eg_vlan_xlt_action.bf.counter_en = entry->counter_enable; - eg_vlan_xlt_action.bf.counter_id = entry->counter_id; - - eg_vlan_xlt_action.bf.xlt_cdei_cmd = entry->cdei_xlt_enable; - eg_vlan_xlt_action.bf.xlt_cdei = entry->cdei_xlt; - eg_vlan_xlt_action.bf.xlt_sdei_cmd = entry->sdei_xlt_enable; - eg_vlan_xlt_action.bf.xlt_sdei = entry->sdei_xlt; - eg_vlan_xlt_action.bf.dei_swap_cmd = entry->swap_sdei_cdei; - - eg_vlan_xlt_action.bf.xlt_cpcp_cmd = entry->cpcp_xlt_enable; - eg_vlan_xlt_action.bf.xlt_cpcp = entry->cpcp_xlt; - eg_vlan_xlt_action.bf.xlt_spcp_cmd = entry->spcp_xlt_enable; - eg_vlan_xlt_action.bf.xlt_spcp_0 = (entry->spcp_xlt & 0x1); - eg_vlan_xlt_action.bf.xlt_spcp_1 = (entry->spcp_xlt >> 1); - eg_vlan_xlt_action.bf.pcp_swap_cmd = entry->swap_spcp_cpcp; - - eg_vlan_xlt_action.bf.xlt_cvid_cmd = entry->cvid_xlt_cmd; - eg_vlan_xlt_action.bf.xlt_cvid = entry->cvid_xlt; - eg_vlan_xlt_action.bf.xlt_svid_cmd = entry->svid_xlt_cmd; - eg_vlan_xlt_action.bf.xlt_svid = entry->svid_xlt; - eg_vlan_xlt_action.bf.vid_swap_cmd = entry->swap_svid_cvid; - - SW_RTN_ON_ERROR(hppe_eg_vlan_xlt_action_set(dev_id, - entry_idx, &eg_vlan_xlt_action)); - } - - return rtn; -} - -sw_error_t -adpt_hppe_port_vlan_trans_get(a_uint32_t dev_id, fal_port_t port_id, fal_vlan_trans_entry_t *entry) -{ - a_uint32_t idx, rule_valid; - fal_vlan_trans_entry_t temp; - - ADPT_DEV_ID_CHECK(dev_id); - ADPT_NULL_POINT_CHECK(entry); - - if (entry->trans_direction == 0) { - for (idx = 0; idx < XLT_RULE_TBL_NUM; idx++) { - aos_mem_zero(&temp, sizeof (fal_vlan_trans_entry_t)); - rule_valid = _get_port_vlan_ingress_trans_by_index(dev_id, idx, &temp); - if (rule_valid == 1) { - if (!aos_mem_cmp(entry, &temp, sizeof(fal_vlan_trans_entry_t))) { - if (SW_IS_PBMP_MEMBER(temp.port_bitmap, port_id)) { - aos_mem_copy(entry, &temp, - sizeof(fal_vlan_trans_entry_t)); - return SW_OK; - } - } - } - } - } - else { - for (idx = 0; idx < XLT_RULE_TBL_NUM; idx++) { - aos_mem_zero(&temp, sizeof (fal_vlan_trans_entry_t)); - rule_valid = _get_port_vlan_egress_trans_by_index(dev_id, idx, &temp); - if (rule_valid == 1) { - if (!aos_mem_cmp(entry, &temp, sizeof(fal_vlan_trans_entry_t))) { - if (SW_IS_PBMP_MEMBER(temp.port_bitmap, port_id)) { - aos_mem_copy(entry, &temp, - sizeof(fal_vlan_trans_entry_t)); - return SW_OK; - } - } - } - } - } - - return SW_NOT_FOUND; -} - -sw_error_t -adpt_hppe_port_vlan_trans_del(a_uint32_t dev_id, fal_port_t port_id, fal_vlan_trans_entry_t *entry) -{ - a_uint32_t idx, rule_valid; - fal_vlan_trans_entry_t temp; - - union xlt_rule_tbl_u in_vlan_xlt_rule; - union eg_vlan_xlt_rule_u eg_vlan_xlt_rule; - union xlt_action_tbl_u in_vlan_xlt_action; - union eg_vlan_xlt_action_u eg_vlan_xlt_action; - - memset(&in_vlan_xlt_rule, 0, sizeof(struct xlt_rule_tbl)); - memset(&eg_vlan_xlt_rule, 0, sizeof(struct eg_vlan_xlt_rule)); - memset(&in_vlan_xlt_action, 0, sizeof(struct xlt_action_tbl)); - memset(&eg_vlan_xlt_action, 0, sizeof(struct eg_vlan_xlt_action)); - - ADPT_DEV_ID_CHECK(dev_id); - ADPT_NULL_POINT_CHECK(entry); - - if (entry->trans_direction == 0) { - for (idx = 0; idx < XLT_RULE_TBL_NUM; idx++) { - aos_mem_zero(&temp, sizeof (fal_vlan_trans_entry_t)); - rule_valid = _get_port_vlan_ingress_trans_by_index(dev_id, idx, &temp); - if (rule_valid == 1) { - if (!aos_mem_cmp(entry, &temp, sizeof (fal_vlan_trans_entry_t))) { - if (SW_IS_PBMP_MEMBER(temp.port_bitmap, port_id)) { - SW_RTN_ON_ERROR(hppe_xlt_rule_tbl_set(dev_id, - idx, &in_vlan_xlt_rule)); - SW_RTN_ON_ERROR(hppe_xlt_action_tbl_set(dev_id, - idx, &in_vlan_xlt_action)); - return SW_OK; - } - } - } - } - } - else { - for (idx = 0; idx < XLT_RULE_TBL_NUM; idx++) { - aos_mem_zero(&temp, sizeof (fal_vlan_trans_entry_t)); - rule_valid = _get_port_vlan_egress_trans_by_index(dev_id, idx, &temp); - if (rule_valid == 1) { - if (!aos_mem_cmp(entry, &temp, sizeof (fal_vlan_trans_entry_t))) { - if (SW_IS_PBMP_MEMBER(temp.port_bitmap, port_id)) { - SW_RTN_ON_ERROR(hppe_eg_vlan_xlt_rule_set(dev_id, - idx, &eg_vlan_xlt_rule)); - SW_RTN_ON_ERROR(hppe_eg_vlan_xlt_action_set(dev_id, - idx, &eg_vlan_xlt_action)); - return SW_OK; - } - } - } - } - } - - return SW_NOT_FOUND; -} -#endif - -sw_error_t -adpt_hppe_port_vsi_egmode_set(a_uint32_t dev_id, - a_uint32_t vsi, a_uint32_t port_id, fal_pt_1q_egmode_t egmode) -{ - sw_error_t rtn = SW_OK; - a_uint32_t value, tag_value; - - ADPT_DEV_ID_CHECK(dev_id); - - - if (egmode == FAL_EG_UNMODIFIED) { - value = 2; - } else if (egmode == FAL_EG_UNTOUCHED) { - value = 3; - } else if (egmode == FAL_EG_UNTAGGED) { - value = 0; - } else if (egmode == FAL_EG_TAGGED) { - value = 1; - } else { - return SW_FAIL; - } - - SW_RTN_ON_ERROR(hppe_eg_vsi_tag_tagged_mode_port_bitmap_get(dev_id, vsi, &tag_value)); - - tag_value &= ~(0x3 << (port_id * 2)); - tag_value |= (value << (port_id * 2)); - - SW_RTN_ON_ERROR(hppe_eg_vsi_tag_tagged_mode_port_bitmap_set(dev_id, vsi, tag_value)); - - return rtn; -} - -sw_error_t -adpt_hppe_port_vsi_egmode_get(a_uint32_t dev_id, - a_uint32_t vsi, a_uint32_t port_id, fal_pt_1q_egmode_t * egmode) -{ - sw_error_t rtn = SW_OK; - a_uint32_t value, tag_value; - - ADPT_DEV_ID_CHECK(dev_id); - ADPT_NULL_POINT_CHECK(egmode); - - SW_RTN_ON_ERROR(hppe_eg_vsi_tag_tagged_mode_port_bitmap_get(dev_id, vsi, &tag_value)); - - value = (tag_value >> (port_id * 2)) & 0x3; - - if (value == 0) - *egmode = FAL_EG_UNTAGGED; - else if (value == 1) - *egmode = FAL_EG_TAGGED; - else if (value == 2) - *egmode = FAL_EG_UNMODIFIED; - else if (value == 3) - *egmode = FAL_EG_UNTOUCHED; - else - return SW_FAIL; - - return rtn; -} - -sw_error_t -adpt_hppe_port_vlantag_vsi_egmode_enable_set(a_uint32_t dev_id, - fal_port_t port_id, a_bool_t enable) -{ - sw_error_t rtn = SW_OK; - - ADPT_DEV_ID_CHECK(dev_id); - - SW_RTN_ON_ERROR(hppe_port_eg_vlan_vsi_tag_mode_en_set(dev_id, port_id, enable)); - - return rtn; -} - -sw_error_t -adpt_hppe_port_vlantag_vsi_egmode_enable_get(a_uint32_t dev_id, - fal_port_t port_id, a_bool_t * enable) -{ - sw_error_t rtn = SW_OK; - - ADPT_DEV_ID_CHECK(dev_id); - ADPT_NULL_POINT_CHECK(enable); - - SW_RTN_ON_ERROR(hppe_port_eg_vlan_vsi_tag_mode_en_get(dev_id, port_id, enable)); - - return rtn; -} - -#ifndef IN_PORTVLAN_MINI -sw_error_t -adpt_hppe_qinq_mode_set(a_uint32_t dev_id, fal_qinq_mode_t mode) -{ - sw_error_t rtn = SW_OK; - fal_global_qinq_mode_t global_mode; - - ADPT_DEV_ID_CHECK(dev_id); - - global_mode.mask = 0x3; - global_mode.ingress_mode = mode; - global_mode.egress_mode = mode; - adpt_hppe_global_qinq_mode_set(dev_id, &global_mode); - - return rtn; -} - -sw_error_t -adpt_hppe_qinq_mode_get(a_uint32_t dev_id, fal_qinq_mode_t * mode) -{ - sw_error_t rtn = SW_OK; - fal_global_qinq_mode_t global_mode; - - ADPT_DEV_ID_CHECK(dev_id); - - adpt_hppe_global_qinq_mode_get(dev_id, &global_mode); - - if (global_mode.ingress_mode == global_mode.egress_mode) - *mode = global_mode.ingress_mode; - else - return SW_FAIL; - - return rtn; -} - -sw_error_t -adpt_hppe_port_qinq_role_set(a_uint32_t dev_id, fal_port_t port_id, fal_qinq_port_role_t role) -{ - sw_error_t rtn = SW_OK; - fal_port_qinq_role_t port_role; - - ADPT_DEV_ID_CHECK(dev_id); - - port_role.mask = 0x3; - port_role.ingress_port_role = role; - port_role.egress_port_role = role; - adpt_hppe_port_qinq_mode_set(dev_id, port_id, &port_role); - - return rtn; -} - -sw_error_t -adpt_hppe_port_qinq_role_get(a_uint32_t dev_id, fal_port_t port_id, fal_qinq_port_role_t * role) -{ - sw_error_t rtn = SW_OK; - fal_port_qinq_role_t port_role; - - ADPT_DEV_ID_CHECK(dev_id); - - adpt_hppe_port_qinq_mode_get(dev_id, port_id, &port_role); - - if (port_role.ingress_port_role == port_role.egress_port_role) - *role = port_role.ingress_port_role; - else - return SW_FAIL; - - return rtn; -} -#endif - -sw_error_t -adpt_hppe_port_invlan_mode_set(a_uint32_t dev_id, fal_port_t port_id, fal_pt_invlan_mode_t mode) -{ - sw_error_t rtn = SW_OK; - fal_ingress_vlan_filter_t filter; - - ADPT_DEV_ID_CHECK(dev_id); - - if (mode == FAL_INVLAN_ADMIT_ALL) - { - filter.tagged_filter = A_FALSE; - filter.untagged_filter = A_FALSE; - filter.priority_filter = A_FALSE; - } - else if (mode == FAL_INVLAN_ADMIT_TAGGED) - { - filter.tagged_filter = A_FALSE; - filter.untagged_filter = A_TRUE; - filter.priority_filter = A_TRUE; - } - else if (mode == FAL_INVLAN_ADMIT_UNTAGGED) - { - filter.tagged_filter = A_TRUE; - filter.untagged_filter = A_FALSE; - filter.priority_filter = A_FALSE; - } - else - return SW_FAIL; - - adpt_hppe_port_ingress_vlan_filter_set(dev_id, port_id, &filter); - - return rtn; -} - -#ifndef IN_PORTVLAN_MINI -sw_error_t -adpt_hppe_port_invlan_mode_get(a_uint32_t dev_id, fal_port_t port_id, fal_pt_invlan_mode_t * mode) -{ - sw_error_t rtn = SW_OK; - fal_ingress_vlan_filter_t filter; - - ADPT_DEV_ID_CHECK(dev_id); - - adpt_hppe_port_ingress_vlan_filter_get(dev_id, port_id, &filter); - - if (filter.tagged_filter == A_FALSE && filter.untagged_filter == A_FALSE && - filter.priority_filter == A_FALSE) - *mode = FAL_INVLAN_ADMIT_ALL; - else if (filter.tagged_filter == A_FALSE && filter.untagged_filter == A_TRUE && - filter.priority_filter == A_TRUE) - *mode = FAL_INVLAN_ADMIT_TAGGED; - else if (filter.tagged_filter == A_TRUE && filter.untagged_filter == A_FALSE && - filter.priority_filter == A_FALSE) - *mode = FAL_INVLAN_ADMIT_UNTAGGED; - else - return SW_FAIL; - - return rtn; -} -#endif - -sw_error_t -adpt_hppe_port_vlan_trans_adv_add(a_uint32_t dev_id, - fal_port_t port_id, fal_port_vlan_direction_t direction, - fal_vlan_trans_adv_rule_t * rule, fal_vlan_trans_adv_action_t * action) -{ - sw_error_t rtn = SW_OK; - a_uint32_t entry_idx, entry_sign, rule_valid; - a_int32_t idx; - fal_vlan_trans_adv_rule_t temp_rule; - fal_vlan_trans_adv_action_t temp_action; - - ADPT_DEV_ID_CHECK(dev_id); - - if (direction == FAL_PORT_VLAN_ALL) - return SW_FAIL; - - entry_sign = 0; - for (idx = XLT_RULE_TBL_NUM - 1; idx >= 0; idx--) { - aos_mem_zero(&temp_rule, sizeof (fal_vlan_trans_adv_rule_t)); - aos_mem_zero(&temp_action, sizeof (fal_vlan_trans_adv_action_t)); - rule_valid = _get_port_vlan_trans_adv_rule_by_index(dev_id, - idx, direction, &temp_rule, &temp_action); - if (rule_valid == 1) - { /* existing rule */ - if (!_check_if_rule_equal(direction, &temp_rule, rule)) - { /* rule equal */ - if (!_check_if_action_equal(direction, &temp_action, action)) - { /* action equal */ - if (SW_IS_PBMP_MEMBER(temp_rule.port_bitmap, port_id)) - { /* current port_bitmap includes this port_id, - nothing need to do */ - return SW_ALREADY_EXIST; - } - else - { /* current port_bitmap doesn't include this port_id, - add this port_id */ - temp_rule.port_bitmap |= (0x1 << port_id); - _insert_vlan_trans_adv_rule_action(dev_id, - idx, direction, &temp_rule, - &temp_action); - return SW_OK; - } - } - else - { /* action not equal */ - if (temp_rule.port_bitmap == (0x1 << port_id)) - { /* port equal, need update action */ - _insert_vlan_trans_adv_rule_action(dev_id, - idx, direction, &temp_rule, - action); - return SW_OK; - } - else - { /* port not equal, need remove port from existing rule - bitmap, insert new rule and action later */ - temp_rule.port_bitmap &= ~(0x1 << port_id); - _insert_vlan_trans_adv_rule_action(dev_id, idx, - direction, &temp_rule, - &temp_action); - } - } - } - else - { /* rule not equal, nothing need to do */ - ; - } - } - else - { /* nonexist rule */ - if (entry_sign == 0) { - entry_idx = idx; - entry_sign = 1; - } - } - } - - if (entry_sign == 0) - return SW_NO_RESOURCE; - - /* insert new rule and action */ - rule->port_bitmap |= (0x1 << port_id); - _insert_vlan_trans_adv_rule_action(dev_id, entry_idx, direction, rule, action); - - return rtn; -} - -sw_error_t -adpt_hppe_port_vlan_trans_adv_del(a_uint32_t dev_id, - fal_port_t port_id, fal_port_vlan_direction_t direction, - fal_vlan_trans_adv_rule_t * rule, fal_vlan_trans_adv_action_t * action) -{ - sw_error_t rtn = SW_OK; - a_uint32_t idx, rule_valid; - fal_vlan_trans_adv_rule_t temp_rule; - fal_vlan_trans_adv_action_t temp_action; - union xlt_rule_tbl_u in_vlan_xlt_rule; - union eg_vlan_xlt_rule_u eg_vlan_xlt_rule; - union xlt_action_tbl_u in_vlan_xlt_action; - union eg_vlan_xlt_action_u eg_vlan_xlt_action; - - memset(&in_vlan_xlt_rule, 0, sizeof(struct xlt_rule_tbl)); - memset(&eg_vlan_xlt_rule, 0, sizeof(struct eg_vlan_xlt_rule)); - memset(&in_vlan_xlt_action, 0, sizeof(struct xlt_action_tbl)); - memset(&eg_vlan_xlt_action, 0, sizeof(struct eg_vlan_xlt_action)); - - ADPT_DEV_ID_CHECK(dev_id); - - if (direction == FAL_PORT_VLAN_ALL) - return SW_FAIL; - - for (idx = 0; idx < XLT_RULE_TBL_NUM; idx++) { - aos_mem_zero(&temp_rule, sizeof (fal_vlan_trans_adv_rule_t)); - aos_mem_zero(&temp_action, sizeof (fal_vlan_trans_adv_action_t)); - rule_valid = _get_port_vlan_trans_adv_rule_by_index(dev_id, - idx, direction, &temp_rule, &temp_action); - if (rule_valid == 1) - { /* existing rule */ - if (!_check_if_rule_equal(direction, &temp_rule, rule)) - { /* rule equal */ - if (!_check_if_action_equal(direction, &temp_action, action)) - { /* action equal */ - if (temp_rule.port_bitmap == (0x1 << port_id)) - { /* port equal, need delete existing rule and action */ - if (direction == FAL_PORT_VLAN_INGRESS) - { - rtn = hppe_xlt_rule_tbl_set(dev_id, - idx, &in_vlan_xlt_rule); - SW_RTN_ON_ERROR(rtn); - rtn = hppe_xlt_action_tbl_set(dev_id, - idx, &in_vlan_xlt_action); - SW_RTN_ON_ERROR(rtn); - } - else - { - rtn = hppe_eg_vlan_xlt_rule_set(dev_id, - idx, &eg_vlan_xlt_rule); - SW_RTN_ON_ERROR(rtn); - rtn = hppe_eg_vlan_xlt_action_set(dev_id, - idx, &eg_vlan_xlt_action); - SW_RTN_ON_ERROR(rtn); - } - } - else if (SW_IS_PBMP_MEMBER(temp_rule.port_bitmap, port_id)) - { /* current port_bitmap includes this port_id, - remove port from port_bitmap and update rule - and action */ - temp_rule.port_bitmap &= ~(0x1 << port_id); - _insert_vlan_trans_adv_rule_action(dev_id, - idx, direction, &temp_rule, - &temp_action); - } - else - { /* current port_bitmap doesn't include port_id, - return SW_NOT_FOUND */ - return SW_NOT_FOUND; - } - break; - } - } - } - } - - if (idx == XLT_RULE_TBL_NUM) - return SW_NOT_FOUND; - - return rtn; -} - -sw_error_t -adpt_hppe_port_vlan_trans_adv_getfirst(a_uint32_t dev_id, - fal_port_t port_id, fal_port_vlan_direction_t direction, - fal_vlan_trans_adv_rule_t * rule, fal_vlan_trans_adv_action_t * action) -{ - sw_error_t rtn = SW_OK; - a_uint32_t idx, rule_valid; - fal_vlan_trans_adv_rule_t temp_rule; - fal_vlan_trans_adv_action_t temp_action; - - ADPT_DEV_ID_CHECK(dev_id); - ADPT_NULL_POINT_CHECK(rule); - ADPT_NULL_POINT_CHECK(action); - - if (direction == FAL_PORT_VLAN_ALL) - return SW_FAIL; - - for (idx = 0; idx < XLT_RULE_TBL_NUM; idx++) { - aos_mem_zero(&temp_rule, sizeof (fal_vlan_trans_adv_rule_t)); - aos_mem_zero(&temp_action, sizeof (fal_vlan_trans_adv_action_t)); - rule_valid = _get_port_vlan_trans_adv_rule_by_index(dev_id, - idx, direction, &temp_rule, &temp_action); - if (rule_valid == 1 && SW_IS_PBMP_MEMBER(temp_rule.port_bitmap, port_id)) - { - aos_mem_copy(rule, &temp_rule, sizeof (fal_vlan_trans_adv_rule_t)); - aos_mem_copy(action, &temp_action, sizeof (fal_vlan_trans_adv_action_t)); - break; - } - } - - if (idx == XLT_RULE_TBL_NUM) - return SW_NOT_FOUND; - - return rtn; -} - -sw_error_t -adpt_hppe_port_vlan_trans_adv_getnext(a_uint32_t dev_id, - fal_port_t port_id, fal_port_vlan_direction_t direction, - fal_vlan_trans_adv_rule_t * rule, fal_vlan_trans_adv_action_t * action) -{ - sw_error_t rtn = SW_OK, sign_tag = 0; - a_uint32_t idx, rule_valid; - fal_vlan_trans_adv_rule_t temp_rule; - fal_vlan_trans_adv_action_t temp_action; - - ADPT_DEV_ID_CHECK(dev_id); - ADPT_NULL_POINT_CHECK(rule); - ADPT_NULL_POINT_CHECK(action); - - if (direction == FAL_PORT_VLAN_ALL) - return SW_FAIL; - - for (idx = 0; idx < XLT_RULE_TBL_NUM; idx++) { - aos_mem_zero(&temp_rule, sizeof (fal_vlan_trans_adv_rule_t)); - aos_mem_zero(&temp_action, sizeof (fal_vlan_trans_adv_action_t)); - rule_valid = _get_port_vlan_trans_adv_rule_by_index(dev_id, idx, - direction, &temp_rule, &temp_action); - if (rule_valid == 1) - { /* existing rule */ - if (sign_tag == 1 && SW_IS_PBMP_MEMBER(temp_rule.port_bitmap, port_id)) - { - aos_mem_copy(rule, &temp_rule, - sizeof (fal_vlan_trans_adv_rule_t)); - aos_mem_copy(action, &temp_action, - sizeof (fal_vlan_trans_adv_action_t)); - break; - } - if (!_check_if_rule_equal(direction, &temp_rule, rule)) - { /* rule equal */ - if (!_check_if_action_equal(direction, &temp_action, action)) - { /* action equal */ - if (SW_IS_PBMP_MEMBER(temp_rule.port_bitmap, port_id)) - sign_tag = 1; - } - } - } - } - - if (idx == XLT_RULE_TBL_NUM) - return SW_NOT_FOUND; - - return rtn; -} - -sw_error_t -adpt_hppe_port_vlan_counter_get(a_uint32_t dev_id, - a_uint32_t cnt_index, fal_port_vlan_counter_t * counter) -{ - union vlan_dev_cnt_tbl_u vlan_dev_cnt_tbl; - union vlan_dev_tx_counter_tbl_u vlan_dev_tx_counter_tbl; - - SW_RTN_ON_ERROR(hppe_vlan_dev_cnt_tbl_get(dev_id, cnt_index, &vlan_dev_cnt_tbl)); - SW_RTN_ON_ERROR(hppe_vlan_dev_tx_counter_tbl_get(dev_id, - cnt_index, &vlan_dev_tx_counter_tbl)); - - counter->rx_packet_counter = vlan_dev_cnt_tbl.bf.rx_pkt_cnt; - counter->rx_byte_counter = ((a_uint64_t)vlan_dev_cnt_tbl.bf.rx_byte_cnt_1 << 32) | - vlan_dev_cnt_tbl.bf.rx_byte_cnt_0; - counter->tx_packet_counter = vlan_dev_tx_counter_tbl.bf.tx_pkt_cnt; - counter->tx_byte_counter = ((a_uint64_t)vlan_dev_tx_counter_tbl.bf.tx_byte_cnt_1 << 32) | - vlan_dev_tx_counter_tbl.bf.tx_byte_cnt_0; - - return SW_OK; -} - -sw_error_t -adpt_hppe_port_vlan_counter_cleanup(a_uint32_t dev_id, a_uint32_t cnt_index) -{ - union vlan_dev_cnt_tbl_u vlan_dev_cnt_tbl; - union vlan_dev_tx_counter_tbl_u vlan_dev_tx_counter_tbl; - - memset(&vlan_dev_cnt_tbl, 0, sizeof(union vlan_dev_cnt_tbl_u)); - memset(&vlan_dev_tx_counter_tbl, 0, sizeof(union vlan_dev_tx_counter_tbl_u)); - - SW_RTN_ON_ERROR(hppe_vlan_dev_cnt_tbl_set(dev_id, cnt_index, &vlan_dev_cnt_tbl)); - SW_RTN_ON_ERROR(hppe_vlan_dev_tx_counter_tbl_set(dev_id, - cnt_index, &vlan_dev_tx_counter_tbl)); - - return SW_OK; -} - -sw_error_t -adpt_hppe_portvlan_member_add(a_uint32_t dev_id, fal_port_t port_id, fal_port_t mem_port_id) -{ - union port_bridge_ctrl_u port_bridge_ctrl; - - port_id = FAL_PORT_ID_VALUE(port_id); - mem_port_id = FAL_PORT_ID_VALUE(mem_port_id); - - memset(&port_bridge_ctrl, 0, sizeof(port_bridge_ctrl)); - ADPT_DEV_ID_CHECK(dev_id); - - hppe_port_bridge_ctrl_get(dev_id, port_id, &port_bridge_ctrl); - - port_bridge_ctrl.bf.port_isolation_bitmap |= (0x1 << mem_port_id); - - SW_RTN_ON_ERROR(hppe_port_bridge_ctrl_set(dev_id, port_id, &port_bridge_ctrl)); - - return SW_OK; -} - -sw_error_t -adpt_hppe_portvlan_member_del(a_uint32_t dev_id, fal_port_t port_id, fal_port_t mem_port_id) -{ - union port_bridge_ctrl_u port_bridge_ctrl; - - port_id = FAL_PORT_ID_VALUE(port_id); - mem_port_id = FAL_PORT_ID_VALUE(mem_port_id); - - memset(&port_bridge_ctrl, 0, sizeof(port_bridge_ctrl)); - ADPT_DEV_ID_CHECK(dev_id); - - hppe_port_bridge_ctrl_get(dev_id, port_id, &port_bridge_ctrl); - - port_bridge_ctrl.bf.port_isolation_bitmap &= ~(0x1 << mem_port_id); - - SW_RTN_ON_ERROR(hppe_port_bridge_ctrl_set(dev_id, port_id, &port_bridge_ctrl)); - - return SW_OK; -} - -sw_error_t -adpt_hppe_portvlan_member_update(a_uint32_t dev_id, fal_port_t port_id, fal_pbmp_t mem_port_map) -{ - union port_bridge_ctrl_u port_bridge_ctrl; - - port_id = FAL_PORT_ID_VALUE(port_id); - - memset(&port_bridge_ctrl, 0, sizeof(port_bridge_ctrl)); - ADPT_DEV_ID_CHECK(dev_id); - - hppe_port_bridge_ctrl_get(dev_id, port_id, &port_bridge_ctrl); - - port_bridge_ctrl.bf.port_isolation_bitmap = mem_port_map; - - SW_RTN_ON_ERROR(hppe_port_bridge_ctrl_set(dev_id, port_id, &port_bridge_ctrl)); - - return SW_OK; -} - -sw_error_t -adpt_hppe_portvlan_member_get(a_uint32_t dev_id, fal_port_t port_id, fal_pbmp_t * mem_port_map) -{ - union port_bridge_ctrl_u port_bridge_ctrl; - - port_id = FAL_PORT_ID_VALUE(port_id); - - memset(&port_bridge_ctrl, 0, sizeof(port_bridge_ctrl)); - ADPT_DEV_ID_CHECK(dev_id); - - hppe_port_bridge_ctrl_get(dev_id, port_id, &port_bridge_ctrl); - - *mem_port_map = port_bridge_ctrl.bf.port_isolation_bitmap; - - return SW_OK; -} - -void adpt_hppe_portvlan_func_bitmap_init(a_uint32_t dev_id) -{ - adpt_api_t *p_adpt_api = NULL; - - p_adpt_api = adpt_api_ptr_get(dev_id); - - if(p_adpt_api == NULL) - return; - - p_adpt_api->adpt_portvlan_func_bitmap[0] = ((1 << FUNC_PORT_INVLAN_MODE_SET) | - (1 << FUNC_PORT_INVLAN_MODE_GET) | - (1 << FUNC_PORT_VLAN_TRANS_ADD) | - (1 << FUNC_PORT_VLAN_TRANS_DEL) | - (1 << FUNC_PORT_VLAN_TRANS_GET) | - (1 << FUNC_QINQ_MODE_SET) | - (1 << FUNC_QINQ_MODE_GET) | - (1 << FUNC_PORT_QINQ_ROLE_SET) | - (1 << FUNC_PORT_QINQ_ROLE_GET) | - (1 << FUNC_PORT_VLAN_TRANS_ITERATE) | - (1 << FUNC_GLOBAL_QINQ_MODE_SET) | - (1 << FUNC_GLOBAL_QINQ_MODE_GET) | - (1 << FUNC_PORT_QINQ_MODE_SET) | - (1 << FUNC_PORT_QINQ_MODE_GET) | - (1 << FUNC_INGRESS_TPID_SET) | - (1 << FUNC_INGRESS_TPID_GET) | - (1 << FUNC_EGRESS_TPID_SET) | - (1 << FUNC_EGRESS_TPID_GET) | - (1 << FUNC_PORT_INGRESS_VLAN_FILTER_SET) | - (1 << FUNC_PORT_INGRESS_VLAN_FILTER_GET) | - (1 << FUNC_PORT_DEFAULT_VLANTAG_SET) | - (1 << FUNC_PORT_DEFAULT_VLANTAG_GET) | - (1 << FUNC_PORT_TAG_PROPAGATION_SET) | - (1 << FUNC_PORT_TAG_PROPAGATION_GET) | - (1 << FUNC_PORT_VLANTAG_EGMODE_SET) | - (1 << FUNC_PORT_VLANTAG_EGMODE_GET) | - (1 << FUNC_PORT_VLAN_XLT_MISS_CMD_SET) | - (1 << FUNC_PORT_VLAN_XLT_MISS_CMD_GET) | - (1 << FUNC_PORT_VSI_EGMODE_SET) | - (1 << FUNC_PORT_VSI_EGMODE_GET) | - (1 << FUNC_PORT_VLANTAG_VSI_EGMODE_ENABLE_SET) | - (1 << FUNC_PORT_VLANTAG_VSI_EGMODE_ENABLE_GET)); - - p_adpt_api->adpt_portvlan_func_bitmap[1] = ((1 << (FUNC_PORT_VLAN_TRANS_ADV_ADD % 32)) | - (1 << (FUNC_PORT_VLAN_TRANS_ADV_DEL % 32)) | - (1 << (FUNC_PORT_VLAN_TRANS_ADV_GETFIRST % 32)) | - (1 << (FUNC_PORT_VLAN_TRANS_ADV_GETNEXT % 32)) | - (1 << (FUNC_PORT_VLAN_COUNTER_GET % 32)) | - (1 << (FUNC_PORT_VLAN_COUNTER_CLEANUP % 32)) | - (1 << (FUNC_PORT_VLAN_MEMBER_ADD % 32)) | - (1 << (FUNC_PORT_VLAN_MEMBER_DEL % 32)) | - (1 << (FUNC_PORT_VLAN_MEMBER_UPDATE % 32)) | - (1 << (FUNC_PORT_VLAN_MEMBER_GET % 32))); - - return; -} - -static void adpt_hppe_portvlan_func_unregister(a_uint32_t dev_id, adpt_api_t *p_adpt_api) -{ - if(p_adpt_api == NULL) - return; - - p_adpt_api->adpt_global_qinq_mode_set = NULL; - p_adpt_api->adpt_global_qinq_mode_get = NULL; - p_adpt_api->adpt_port_qinq_mode_set = NULL; - p_adpt_api->adpt_port_qinq_mode_get = NULL; - p_adpt_api->adpt_tpid_set = NULL; - p_adpt_api->adpt_tpid_get = NULL; - p_adpt_api->adpt_egress_tpid_set = NULL; - p_adpt_api->adpt_egress_tpid_get = NULL; - p_adpt_api->adpt_port_ingress_vlan_filter_set = NULL; - p_adpt_api->adpt_port_ingress_vlan_filter_get = NULL; - p_adpt_api->adpt_port_default_vlantag_set = NULL; - p_adpt_api->adpt_port_default_vlantag_get = NULL; - p_adpt_api->adpt_port_tag_propagation_set = NULL; - p_adpt_api->adpt_port_tag_propagation_get = NULL; - p_adpt_api->adpt_port_vlantag_egmode_set = NULL; - p_adpt_api->adpt_port_vlantag_egmode_get = NULL; - p_adpt_api->adpt_port_vlan_xlt_miss_cmd_set = NULL; - p_adpt_api->adpt_port_vlan_xlt_miss_cmd_get = NULL; - p_adpt_api->adpt_port_vlan_trans_iterate = NULL; - p_adpt_api->adpt_port_vlan_trans_add = NULL; - p_adpt_api->adpt_port_vlan_trans_get = NULL; - p_adpt_api->adpt_port_vlan_trans_del = NULL; - - p_adpt_api->adpt_port_vsi_egmode_set = NULL; - p_adpt_api->adpt_port_vsi_egmode_get = NULL; - p_adpt_api->adpt_port_vlantag_vsi_egmode_enable_set = NULL; - p_adpt_api->adpt_port_vlantag_vsi_egmode_enable_get = NULL; - - p_adpt_api->adpt_qinq_mode_set = NULL; - p_adpt_api->adpt_qinq_mode_get = NULL; - p_adpt_api->adpt_port_qinq_role_set = NULL; - p_adpt_api->adpt_port_qinq_role_get = NULL; - p_adpt_api->adpt_port_invlan_mode_set = NULL; - p_adpt_api->adpt_port_invlan_mode_get = NULL; - - p_adpt_api->adpt_port_vlan_trans_adv_add = NULL; - p_adpt_api->adpt_port_vlan_trans_adv_del = NULL; - p_adpt_api->adpt_port_vlan_trans_adv_getfirst = NULL; - p_adpt_api->adpt_port_vlan_trans_adv_getnext = NULL; - - p_adpt_api->adpt_port_vlan_counter_get = NULL; - p_adpt_api->adpt_port_vlan_counter_cleanup = NULL; - - p_adpt_api->adpt_portvlan_member_add = NULL; - p_adpt_api->adpt_portvlan_member_del = NULL; - p_adpt_api->adpt_portvlan_member_update = NULL; - p_adpt_api->adpt_portvlan_member_get = NULL; - - return; -} - -sw_error_t adpt_hppe_portvlan_init(a_uint32_t dev_id) -{ - adpt_api_t *p_adpt_api = NULL; - - p_adpt_api = adpt_api_ptr_get(dev_id); - - if(p_adpt_api == NULL) - return SW_FAIL; - - adpt_hppe_portvlan_func_unregister(dev_id, p_adpt_api); - - if (p_adpt_api->adpt_portvlan_func_bitmap[0] & (1 << FUNC_GLOBAL_QINQ_MODE_SET)) - p_adpt_api->adpt_global_qinq_mode_set = adpt_hppe_global_qinq_mode_set; - if (p_adpt_api->adpt_portvlan_func_bitmap[0] & (1 << FUNC_GLOBAL_QINQ_MODE_GET)) - p_adpt_api->adpt_global_qinq_mode_get = adpt_hppe_global_qinq_mode_get; - if (p_adpt_api->adpt_portvlan_func_bitmap[0] & (1 << FUNC_PORT_QINQ_MODE_SET)) - p_adpt_api->adpt_port_qinq_mode_set = adpt_hppe_port_qinq_mode_set; - if (p_adpt_api->adpt_portvlan_func_bitmap[0] & (1 << FUNC_PORT_QINQ_MODE_GET)) - p_adpt_api->adpt_port_qinq_mode_get = adpt_hppe_port_qinq_mode_get; - if (p_adpt_api->adpt_portvlan_func_bitmap[0] & (1 << FUNC_INGRESS_TPID_SET)) - p_adpt_api->adpt_tpid_set = adpt_hppe_tpid_set; - if (p_adpt_api->adpt_portvlan_func_bitmap[0] & (1 << FUNC_INGRESS_TPID_GET)) - p_adpt_api->adpt_tpid_get = adpt_hppe_tpid_get; - if (p_adpt_api->adpt_portvlan_func_bitmap[0] & (1 << FUNC_EGRESS_TPID_SET)) - p_adpt_api->adpt_egress_tpid_set = adpt_hppe_egress_tpid_set; - if (p_adpt_api->adpt_portvlan_func_bitmap[0] & (1 << FUNC_EGRESS_TPID_GET)) - p_adpt_api->adpt_egress_tpid_get = adpt_hppe_egress_tpid_get; - if (p_adpt_api->adpt_portvlan_func_bitmap[0] & (1 << FUNC_PORT_INGRESS_VLAN_FILTER_SET)) - p_adpt_api->adpt_port_ingress_vlan_filter_set = - adpt_hppe_port_ingress_vlan_filter_set; - if (p_adpt_api->adpt_portvlan_func_bitmap[0] & (1 << FUNC_PORT_INGRESS_VLAN_FILTER_GET)) - p_adpt_api->adpt_port_ingress_vlan_filter_get = - adpt_hppe_port_ingress_vlan_filter_get; - if (p_adpt_api->adpt_portvlan_func_bitmap[0] & (1 << FUNC_PORT_DEFAULT_VLANTAG_SET)) - p_adpt_api->adpt_port_default_vlantag_set = adpt_hppe_port_default_vlantag_set; - if (p_adpt_api->adpt_portvlan_func_bitmap[0] & (1 << FUNC_PORT_DEFAULT_VLANTAG_GET)) - p_adpt_api->adpt_port_default_vlantag_get = adpt_hppe_port_default_vlantag_get; - if (p_adpt_api->adpt_portvlan_func_bitmap[0] & (1 << FUNC_PORT_TAG_PROPAGATION_SET)) - p_adpt_api->adpt_port_tag_propagation_set = adpt_hppe_port_tag_propagation_set; - if (p_adpt_api->adpt_portvlan_func_bitmap[0] & (1 << FUNC_PORT_TAG_PROPAGATION_GET)) - p_adpt_api->adpt_port_tag_propagation_get = adpt_hppe_port_tag_propagation_get; - if (p_adpt_api->adpt_portvlan_func_bitmap[0] & (1 << FUNC_PORT_VLANTAG_EGMODE_SET)) - p_adpt_api->adpt_port_vlantag_egmode_set = adpt_hppe_port_vlantag_egmode_set; - if (p_adpt_api->adpt_portvlan_func_bitmap[0] & (1 << FUNC_PORT_VLANTAG_EGMODE_GET)) - p_adpt_api->adpt_port_vlantag_egmode_get = adpt_hppe_port_vlantag_egmode_get; - if (p_adpt_api->adpt_portvlan_func_bitmap[0] & (1 << FUNC_PORT_VLAN_XLT_MISS_CMD_SET)) - p_adpt_api->adpt_port_vlan_xlt_miss_cmd_set = adpt_hppe_port_vlan_xlt_miss_cmd_set; - if (p_adpt_api->adpt_portvlan_func_bitmap[0] & (1 << FUNC_PORT_VLAN_XLT_MISS_CMD_GET)) - p_adpt_api->adpt_port_vlan_xlt_miss_cmd_get = adpt_hppe_port_vlan_xlt_miss_cmd_get; -#ifndef IN_PORTVLAN_MINI - if (p_adpt_api->adpt_portvlan_func_bitmap[0] & (1 << FUNC_PORT_VLAN_TRANS_ITERATE)) - p_adpt_api->adpt_port_vlan_trans_iterate = adpt_hppe_port_vlan_trans_iterate; - if (p_adpt_api->adpt_portvlan_func_bitmap[0] & (1 << FUNC_PORT_VLAN_TRANS_ADD)) - p_adpt_api->adpt_port_vlan_trans_add = adpt_hppe_port_vlan_trans_add; - if (p_adpt_api->adpt_portvlan_func_bitmap[0] & (1 << FUNC_PORT_VLAN_TRANS_GET)) - p_adpt_api->adpt_port_vlan_trans_get = adpt_hppe_port_vlan_trans_get; - if (p_adpt_api->adpt_portvlan_func_bitmap[0] & (1 << FUNC_PORT_VLAN_TRANS_DEL)) - p_adpt_api->adpt_port_vlan_trans_del = adpt_hppe_port_vlan_trans_del; -#endif - - if (p_adpt_api->adpt_portvlan_func_bitmap[0] & (1 << FUNC_PORT_VSI_EGMODE_SET)) - p_adpt_api->adpt_port_vsi_egmode_set = adpt_hppe_port_vsi_egmode_set; - if (p_adpt_api->adpt_portvlan_func_bitmap[0] & (1 << FUNC_PORT_VSI_EGMODE_GET)) - p_adpt_api->adpt_port_vsi_egmode_get = adpt_hppe_port_vsi_egmode_get; - if (p_adpt_api->adpt_portvlan_func_bitmap[0] & - (1 << FUNC_PORT_VLANTAG_VSI_EGMODE_ENABLE_SET)) - p_adpt_api->adpt_port_vlantag_vsi_egmode_enable_set = - adpt_hppe_port_vlantag_vsi_egmode_enable_set; - if (p_adpt_api->adpt_portvlan_func_bitmap[0] & - (1 << FUNC_PORT_VLANTAG_VSI_EGMODE_ENABLE_GET)) - p_adpt_api->adpt_port_vlantag_vsi_egmode_enable_get = - adpt_hppe_port_vlantag_vsi_egmode_enable_get; -#ifndef IN_PORTVLAN_MINI - if (p_adpt_api->adpt_portvlan_func_bitmap[0] & (1 << FUNC_QINQ_MODE_SET)) - p_adpt_api->adpt_qinq_mode_set = adpt_hppe_qinq_mode_set; - if (p_adpt_api->adpt_portvlan_func_bitmap[0] & (1 << FUNC_QINQ_MODE_GET)) - p_adpt_api->adpt_qinq_mode_get = adpt_hppe_qinq_mode_get; - if (p_adpt_api->adpt_portvlan_func_bitmap[0] & (1 << FUNC_PORT_QINQ_ROLE_SET)) - p_adpt_api->adpt_port_qinq_role_set = adpt_hppe_port_qinq_role_set; - if (p_adpt_api->adpt_portvlan_func_bitmap[0] & (1 << FUNC_PORT_QINQ_ROLE_GET)) - p_adpt_api->adpt_port_qinq_role_get = adpt_hppe_port_qinq_role_get; - if (p_adpt_api->adpt_portvlan_func_bitmap[0] & (1 << FUNC_PORT_INVLAN_MODE_GET)) - p_adpt_api->adpt_port_invlan_mode_get = adpt_hppe_port_invlan_mode_get; -#endif - if (p_adpt_api->adpt_portvlan_func_bitmap[0] & (1 << FUNC_PORT_INVLAN_MODE_SET)) - p_adpt_api->adpt_port_invlan_mode_set = adpt_hppe_port_invlan_mode_set; - - if (p_adpt_api->adpt_portvlan_func_bitmap[1] & (1 << (FUNC_PORT_VLAN_TRANS_ADV_ADD % 32))) - p_adpt_api->adpt_port_vlan_trans_adv_add = adpt_hppe_port_vlan_trans_adv_add; - if (p_adpt_api->adpt_portvlan_func_bitmap[1] & (1 << (FUNC_PORT_VLAN_TRANS_ADV_DEL % 32))) - p_adpt_api->adpt_port_vlan_trans_adv_del = adpt_hppe_port_vlan_trans_adv_del; - if (p_adpt_api->adpt_portvlan_func_bitmap[1] & - (1 << (FUNC_PORT_VLAN_TRANS_ADV_GETFIRST % 32))) - p_adpt_api->adpt_port_vlan_trans_adv_getfirst = - adpt_hppe_port_vlan_trans_adv_getfirst; - if (p_adpt_api->adpt_portvlan_func_bitmap[1] & - (1 << (FUNC_PORT_VLAN_TRANS_ADV_GETNEXT % 32))) - p_adpt_api->adpt_port_vlan_trans_adv_getnext = - adpt_hppe_port_vlan_trans_adv_getnext; - - if (p_adpt_api->adpt_portvlan_func_bitmap[1] & (1 << (FUNC_PORT_VLAN_COUNTER_GET % 32))) - p_adpt_api->adpt_port_vlan_counter_get = adpt_hppe_port_vlan_counter_get; - if (p_adpt_api->adpt_portvlan_func_bitmap[1] & - (1 << (FUNC_PORT_VLAN_COUNTER_CLEANUP % 32))) - p_adpt_api->adpt_port_vlan_counter_cleanup = adpt_hppe_port_vlan_counter_cleanup; - if (p_adpt_api->adpt_portvlan_func_bitmap[1] & (1 << (FUNC_PORT_VLAN_MEMBER_ADD % 32))) - p_adpt_api->adpt_portvlan_member_add = adpt_hppe_portvlan_member_add; - if (p_adpt_api->adpt_portvlan_func_bitmap[1] & (1 << (FUNC_PORT_VLAN_MEMBER_DEL % 32))) - p_adpt_api->adpt_portvlan_member_del = adpt_hppe_portvlan_member_del; - if (p_adpt_api->adpt_portvlan_func_bitmap[1] & (1 << (FUNC_PORT_VLAN_MEMBER_UPDATE % 32))) - p_adpt_api->adpt_portvlan_member_update = adpt_hppe_portvlan_member_update; - if (p_adpt_api->adpt_portvlan_func_bitmap[1] & (1 << (FUNC_PORT_VLAN_MEMBER_GET % 32))) - p_adpt_api->adpt_portvlan_member_get = adpt_hppe_portvlan_member_get; - - return SW_OK; -} - -/** - * @} - */ diff --git a/feeds/ipq807x/qca-ssdk/src/src/adpt/hppe/adpt_hppe_pppoe.c b/feeds/ipq807x/qca-ssdk/src/src/adpt/hppe/adpt_hppe_pppoe.c deleted file mode 100755 index 059cae6d7..000000000 --- a/feeds/ipq807x/qca-ssdk/src/src/adpt/hppe/adpt_hppe_pppoe.c +++ /dev/null @@ -1,330 +0,0 @@ -/* - * Copyright (c) 2016-2017, The Linux Foundation. All rights reserved. - * Permission to use, copy, modify, and/or distribute this software for - * any purpose with or without fee is hereby granted, provided that the - * above copyright notice and this permission notice appear in all copies. - * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES - * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR - * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES - * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN - * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT - * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. - */ - - -/** - * @defgroup - * @{ - */ -#include "sw.h" -#include "hppe_pppoe_reg.h" -#include "hppe_pppoe.h" -#include "hppe_ip_reg.h" -#include "hppe_ip.h" -#include "adpt.h" - -#define MAX_SESSION_ID 0xffff - -sw_error_t -adpt_hppe_pppoe_session_table_add(a_uint32_t dev_id, fal_pppoe_session_t * session_tbl) -{ - sw_error_t rv = SW_OK; - union pppoe_session_u pppoe_session = {0}; - union pppoe_session_ext_u pppoe_session_ext = {0}; - union pppoe_session_ext1_u pppoe_session_ext1 = {0}; - union eg_l3_if_tbl_u eg_l3_if_tbl = {0}; - a_uint32_t num, index, entry_idx = PPPOE_SESSION_MAX_ENTRY; - a_uint16_t smac_ext = 0; - a_uint32_t smac_ext1 = 0; - - ADPT_DEV_ID_CHECK(dev_id); - ADPT_NULL_POINT_CHECK(session_tbl); - - if (session_tbl->session_id > MAX_SESSION_ID) - return SW_BAD_PARAM; - if (session_tbl->multi_session == A_FALSE && session_tbl->uni_session == A_FALSE) - return SW_BAD_PARAM; - if (session_tbl->l3_if_index >= IN_L3_IF_TBL_MAX_ENTRY) - return SW_BAD_PARAM; - for (num = 0; num < PPPOE_SESSION_MAX_ENTRY; num++) - { - hppe_pppoe_session_get(dev_id, num, &pppoe_session); - hppe_pppoe_session_ext_get(dev_id, num, &pppoe_session_ext); - hppe_pppoe_session_ext1_get(dev_id, num, &pppoe_session_ext1); - - for (index = 0; index <= 3; index++) { - smac_ext1 = (smac_ext1 << 8) + session_tbl->smac_addr.uc[index]; - - } - for (index = 4; index <= 5; index++) { - smac_ext = (smac_ext << 8) + session_tbl->smac_addr.uc[index]; - } - - if (pppoe_session_ext.bf.mc_valid == A_FALSE && - pppoe_session_ext.bf.uc_valid == A_FALSE) - { - if (entry_idx == PPPOE_SESSION_MAX_ENTRY) - entry_idx = num; - } - else if (pppoe_session.bf.session_id == session_tbl->session_id && - pppoe_session_ext.bf.smac_valid == session_tbl->smac_valid) { - if (session_tbl->smac_valid == A_FALSE || - (session_tbl->smac_valid == A_TRUE && - smac_ext == pppoe_session_ext.bf.smac && - smac_ext1 == pppoe_session_ext1.bf.smac)) { - return SW_ALREADY_EXIST; - } - } - } - if (entry_idx == PPPOE_SESSION_MAX_ENTRY) - return SW_NO_RESOURCE; - - pppoe_session.bf.session_id = session_tbl->session_id; - pppoe_session.bf.port_bitmap = session_tbl->port_bitmap; - pppoe_session.bf.l3_if_index = session_tbl->l3_if_index; - - pppoe_session_ext.bf.l3_if_valid = session_tbl->l3_if_valid; - pppoe_session_ext.bf.mc_valid = session_tbl->multi_session; - pppoe_session_ext.bf.uc_valid = session_tbl->uni_session; - pppoe_session_ext.bf.smac_valid = session_tbl->smac_valid; - - pppoe_session_ext.bf.smac = smac_ext; - pppoe_session_ext1.bf.smac = smac_ext1; - - hppe_pppoe_session_set(dev_id, entry_idx, &pppoe_session); - hppe_pppoe_session_ext_set(dev_id, entry_idx, &pppoe_session_ext); - hppe_pppoe_session_ext1_set(dev_id, entry_idx, &pppoe_session_ext1); - - rv = hppe_eg_l3_if_tbl_get(dev_id, session_tbl->l3_if_index, &eg_l3_if_tbl); - SW_RTN_ON_ERROR(rv); - - eg_l3_if_tbl.bf.session_id = session_tbl->session_id; - rv = hppe_eg_l3_if_tbl_set(dev_id, session_tbl->l3_if_index, &eg_l3_if_tbl); - SW_RTN_ON_ERROR(rv); - - session_tbl->entry_id = entry_idx; - - return rv; -} - -sw_error_t -adpt_hppe_pppoe_session_table_del(a_uint32_t dev_id, fal_pppoe_session_t * session_tbl) -{ - sw_error_t rv = SW_OK; - union pppoe_session_u pppoe_session = {0}; - union pppoe_session_ext_u pppoe_session_ext = {0}; - union pppoe_session_ext1_u pppoe_session_ext1 = {0}; - union pppoe_session_u pppoe_session_zero = {0}; - union pppoe_session_ext_u pppoe_session_ext_zero = {0}; - union pppoe_session_ext1_u pppoe_session_ext1_zero = {0}; - union eg_l3_if_tbl_u eg_l3_if_tbl = {0}; - a_uint16_t smac_ext = 0; - a_uint32_t smac_ext1 = 0; - a_uint32_t num, index; - - ADPT_DEV_ID_CHECK(dev_id); - ADPT_NULL_POINT_CHECK(session_tbl); - - if (session_tbl->session_id > MAX_SESSION_ID) - return SW_BAD_PARAM; - - for (num = 0; num < PPPOE_SESSION_MAX_ENTRY; num++) - { - hppe_pppoe_session_get(dev_id, num, &pppoe_session); - hppe_pppoe_session_ext_get(dev_id, num, &pppoe_session_ext); - hppe_pppoe_session_ext1_get(dev_id, num, &pppoe_session_ext1); - - for (index = 0; index <= 3; index++) { - smac_ext1 = (smac_ext1 << 8) + session_tbl->smac_addr.uc[index]; - } - for (index = 4; index <= 5; index++) { - smac_ext = (smac_ext << 8) + session_tbl->smac_addr.uc[index]; - } - - if ((pppoe_session_ext.bf.mc_valid == A_TRUE || - pppoe_session_ext.bf.uc_valid == A_TRUE) && - (pppoe_session.bf.session_id == session_tbl->session_id && - pppoe_session_ext.bf.smac_valid == session_tbl->smac_valid && - (session_tbl->smac_valid == A_FALSE || - (session_tbl->smac_valid == A_TRUE && - smac_ext == pppoe_session_ext.bf.smac && - smac_ext1 == pppoe_session_ext1.bf.smac)))) - { - hppe_pppoe_session_set(dev_id, num, &pppoe_session_zero); - hppe_pppoe_session_ext_set(dev_id, num, &pppoe_session_ext_zero); - hppe_pppoe_session_ext1_set(dev_id, num, &pppoe_session_ext1_zero); - - rv = hppe_eg_l3_if_tbl_get(dev_id, - pppoe_session.bf.l3_if_index, &eg_l3_if_tbl); - SW_RTN_ON_ERROR(rv); - - eg_l3_if_tbl.bf.session_id = 0; - rv = hppe_eg_l3_if_tbl_set(dev_id, - pppoe_session.bf.l3_if_index, &eg_l3_if_tbl); - - return rv; - } - } - - return SW_NOT_FOUND; -} - -sw_error_t -adpt_hppe_pppoe_session_table_get(a_uint32_t dev_id, fal_pppoe_session_t * session_tbl) -{ - union pppoe_session_u pppoe_session = {0}; - union pppoe_session_ext_u pppoe_session_ext = {0}; - union pppoe_session_ext1_u pppoe_session_ext1 = {0}; - a_uint16_t smac_ext = 0; - a_uint32_t smac_ext1 = 0; - a_uint32_t num, index; - - ADPT_DEV_ID_CHECK(dev_id); - ADPT_NULL_POINT_CHECK(session_tbl); - - if (session_tbl->session_id > MAX_SESSION_ID) - return SW_BAD_PARAM; - - for (num = 0; num < PPPOE_SESSION_MAX_ENTRY; num++) - { - hppe_pppoe_session_get(dev_id, num, &pppoe_session); - hppe_pppoe_session_ext_get(dev_id, num, &pppoe_session_ext); - hppe_pppoe_session_ext1_get(dev_id, num, &pppoe_session_ext1); - - for (index = 0; index <= 3; index++) { - smac_ext1 = (smac_ext1 << 8) + session_tbl->smac_addr.uc[index]; - } - for (index = 4; index <= 5; index++) { - smac_ext = (smac_ext << 8) + session_tbl->smac_addr.uc[index]; - } - if ((pppoe_session_ext.bf.mc_valid == A_TRUE || - pppoe_session_ext.bf.uc_valid == A_TRUE) && - (pppoe_session.bf.session_id == session_tbl->session_id && - pppoe_session_ext.bf.smac_valid == session_tbl->smac_valid && - (session_tbl->smac_valid == A_FALSE || - (session_tbl->smac_valid == A_TRUE && - smac_ext == pppoe_session_ext.bf.smac && - smac_ext1 == pppoe_session_ext1.bf.smac)))) - { - session_tbl->entry_id = num; - session_tbl->session_id = pppoe_session.bf.session_id; - session_tbl->port_bitmap = pppoe_session.bf.port_bitmap; - session_tbl->l3_if_index = pppoe_session.bf.l3_if_index; - session_tbl->l3_if_valid = pppoe_session_ext.bf.l3_if_valid; - session_tbl->multi_session = pppoe_session_ext.bf.mc_valid; - session_tbl->uni_session = pppoe_session_ext.bf.uc_valid; - session_tbl->smac_valid = pppoe_session_ext.bf.smac_valid; - session_tbl->smac_addr.uc[0] = (pppoe_session_ext1.bf.smac >> 24) & 0xff; - session_tbl->smac_addr.uc[1] = (pppoe_session_ext1.bf.smac >> 16) & 0xff; - session_tbl->smac_addr.uc[2] = (pppoe_session_ext1.bf.smac >> 8) & 0xff; - session_tbl->smac_addr.uc[3] = pppoe_session_ext1.bf.smac & 0xff; - session_tbl->smac_addr.uc[4] = (pppoe_session_ext.bf.smac >> 8) & 0xff; - session_tbl->smac_addr.uc[5] = pppoe_session_ext.bf.smac & 0xff; - return SW_OK; - } - } - - return SW_NOT_FOUND; -} - -sw_error_t -adpt_hppe_pppoe_en_set(a_uint32_t dev_id, a_uint32_t l3_if, a_uint32_t enable) -{ - sw_error_t rv = SW_OK; - union in_l3_if_tbl_u in_l3_if_tbl = {0}; - union eg_l3_if_tbl_u eg_l3_if_tbl = {0}; - - ADPT_DEV_ID_CHECK(dev_id); - - rv = hppe_in_l3_if_tbl_get(dev_id, l3_if, &in_l3_if_tbl); - SW_RTN_ON_ERROR(rv); - - rv = hppe_eg_l3_if_tbl_get(dev_id, l3_if, &eg_l3_if_tbl); - SW_RTN_ON_ERROR(rv); - - in_l3_if_tbl.bf.pppoe_en = enable; - eg_l3_if_tbl.bf.pppoe_en = enable; - - rv = hppe_in_l3_if_tbl_set(dev_id, l3_if, &in_l3_if_tbl); - SW_RTN_ON_ERROR(rv); - - rv = hppe_eg_l3_if_tbl_set(dev_id, l3_if, &eg_l3_if_tbl); - - return rv; -} - -sw_error_t -adpt_hppe_pppoe_en_get(a_uint32_t dev_id, a_uint32_t l3_if, a_uint32_t *enable) -{ - sw_error_t rv = SW_OK; - union in_l3_if_tbl_u in_l3_if_tbl = {0}; - - ADPT_DEV_ID_CHECK(dev_id); - ADPT_NULL_POINT_CHECK(enable); - - rv = hppe_in_l3_if_tbl_get(dev_id, l3_if, &in_l3_if_tbl); - SW_RTN_ON_ERROR(rv); - - *enable = in_l3_if_tbl.bf.pppoe_en; - - return rv; -} - -void adpt_hppe_pppoe_func_bitmap_init(a_uint32_t dev_id) -{ - adpt_api_t *p_adpt_api = NULL; - - p_adpt_api = adpt_api_ptr_get(dev_id); - - if(p_adpt_api == NULL) - return; - - p_adpt_api->adpt_pppoe_func_bitmap = 0x0; - - return; -} - -static void adpt_hppe_pppoe_func_unregister(a_uint32_t dev_id, adpt_api_t *p_adpt_api) -{ - if(p_adpt_api == NULL) - return; - - p_adpt_api->adpt_pppoe_session_table_add = NULL; - p_adpt_api->adpt_pppoe_session_table_del = NULL; - p_adpt_api->adpt_pppoe_session_table_get = NULL; - p_adpt_api->adpt_pppoe_en_set = NULL; - p_adpt_api->adpt_pppoe_en_get = NULL; - - return; -} - -sw_error_t adpt_hppe_pppoe_init(a_uint32_t dev_id) -{ - adpt_api_t *p_adpt_api = NULL; - - p_adpt_api = adpt_api_ptr_get(dev_id); - - if(p_adpt_api == NULL) - return SW_FAIL; - - adpt_hppe_pppoe_func_unregister(dev_id, p_adpt_api); - - if (p_adpt_api->adpt_pppoe_func_bitmap & (1 << FUNC_PPPOE_SESSION_TABLE_ADD)) - p_adpt_api->adpt_pppoe_session_table_add = adpt_hppe_pppoe_session_table_add; - if (p_adpt_api->adpt_pppoe_func_bitmap & (1 << FUNC_PPPOE_SESSION_TABLE_DEL)) - p_adpt_api->adpt_pppoe_session_table_del = adpt_hppe_pppoe_session_table_del; - if (p_adpt_api->adpt_pppoe_func_bitmap & (1 << FUNC_PPPOE_SESSION_TABLE_GET)) - p_adpt_api->adpt_pppoe_session_table_get = adpt_hppe_pppoe_session_table_get; - if (p_adpt_api->adpt_pppoe_func_bitmap & (1 << FUNC_PPPOE_EN_SET)) - p_adpt_api->adpt_pppoe_en_set = adpt_hppe_pppoe_en_set; - if (p_adpt_api->adpt_pppoe_func_bitmap & (1 << FUNC_PPPOE_EN_GET)) - p_adpt_api->adpt_pppoe_en_get = adpt_hppe_pppoe_en_get; - - - return SW_OK; -} - -/** - * @} - */ diff --git a/feeds/ipq807x/qca-ssdk/src/src/adpt/hppe/adpt_hppe_ptp.c b/feeds/ipq807x/qca-ssdk/src/src/adpt/hppe/adpt_hppe_ptp.c deleted file mode 100755 index 6e86261e4..000000000 --- a/feeds/ipq807x/qca-ssdk/src/src/adpt/hppe/adpt_hppe_ptp.c +++ /dev/null @@ -1,1382 +0,0 @@ -/* - * Copyright (c) 2018, The Linux Foundation. All rights reserved. - * Permission to use, copy, modify, and/or distribute this software for - * any purpose with or without fee is hereby granted, provided that the - * above copyright notice and this permission notice appear in all copies. - * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES - * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR - * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES - * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN - * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT - * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. - */ - - -/** - * @defgroup - * @{ - */ -#include "sw.h" -#include "adpt.h" -#include "hsl.h" -#include "hsl_dev.h" -#include "hsl_port_prop.h" -#include "hsl_phy.h" - -sw_error_t -adpt_hppe_ptp_config_set(a_uint32_t dev_id, a_uint32_t port_id, fal_ptp_config_t *config) -{ - sw_error_t rv = 0; - a_uint32_t phy_id = 0; - hsl_phy_ops_t *phy_drv; - - ADPT_DEV_ID_CHECK(dev_id); - ADPT_NULL_POINT_CHECK(config); - - if (A_TRUE != hsl_port_prop_check (dev_id, port_id, HSL_PP_PHY)) - { - return SW_BAD_PARAM; - } - - SW_RTN_ON_NULL (phy_drv = hsl_phy_api_ops_get (dev_id, port_id)); - if (NULL == phy_drv->phy_ptp_ops.phy_ptp_config_set) - { - return SW_NOT_SUPPORTED; - } - - rv = hsl_port_prop_get_phyid (dev_id, port_id, &phy_id); - SW_RTN_ON_ERROR (rv); - - rv = phy_drv->phy_ptp_ops.phy_ptp_config_set(dev_id, phy_id, config); - - return rv; -} - -sw_error_t -adpt_hppe_ptp_config_get(a_uint32_t dev_id, a_uint32_t port_id, fal_ptp_config_t *config) -{ - sw_error_t rv = 0; - a_uint32_t phy_id = 0; - hsl_phy_ops_t *phy_drv; - - ADPT_DEV_ID_CHECK(dev_id); - ADPT_NULL_POINT_CHECK(config); - - if (A_TRUE != hsl_port_prop_check (dev_id, port_id, HSL_PP_PHY)) - { - return SW_BAD_PARAM; - } - - SW_RTN_ON_NULL (phy_drv = hsl_phy_api_ops_get (dev_id, port_id)); - if (NULL == phy_drv->phy_ptp_ops.phy_ptp_config_get) - { - return SW_NOT_SUPPORTED; - } - - rv = hsl_port_prop_get_phyid (dev_id, port_id, &phy_id); - SW_RTN_ON_ERROR (rv); - - rv = phy_drv->phy_ptp_ops.phy_ptp_config_get(dev_id, phy_id, config); - - return rv; -} - -sw_error_t -adpt_hppe_ptp_reference_clock_set(a_uint32_t dev_id, a_uint32_t port_id, fal_ptp_reference_clock_t ref_clock) -{ - sw_error_t rv = 0; - a_uint32_t phy_id = 0; - hsl_phy_ops_t *phy_drv; - - ADPT_DEV_ID_CHECK(dev_id); - - if (A_TRUE != hsl_port_prop_check (dev_id, port_id, HSL_PP_PHY)) - { - return SW_BAD_PARAM; - } - - SW_RTN_ON_NULL (phy_drv = hsl_phy_api_ops_get (dev_id, port_id)); - if (NULL == phy_drv->phy_ptp_ops.phy_ptp_reference_clock_set) - { - return SW_NOT_SUPPORTED; - } - - rv = hsl_port_prop_get_phyid (dev_id, port_id, &phy_id); - SW_RTN_ON_ERROR (rv); - - rv = phy_drv->phy_ptp_ops.phy_ptp_reference_clock_set(dev_id, phy_id, ref_clock); - - return rv; -} - -sw_error_t -adpt_hppe_ptp_reference_clock_get(a_uint32_t dev_id, a_uint32_t port_id, fal_ptp_reference_clock_t *ref_clock) -{ - sw_error_t rv = 0; - a_uint32_t phy_id = 0; - hsl_phy_ops_t *phy_drv; - - ADPT_DEV_ID_CHECK(dev_id); - ADPT_NULL_POINT_CHECK(ref_clock); - - if (A_TRUE != hsl_port_prop_check (dev_id, port_id, HSL_PP_PHY)) - { - return SW_BAD_PARAM; - } - - SW_RTN_ON_NULL (phy_drv = hsl_phy_api_ops_get (dev_id, port_id)); - if (NULL == phy_drv->phy_ptp_ops.phy_ptp_reference_clock_get) - { - return SW_NOT_SUPPORTED; - } - - rv = hsl_port_prop_get_phyid (dev_id, port_id, &phy_id); - SW_RTN_ON_ERROR (rv); - - rv = phy_drv->phy_ptp_ops.phy_ptp_reference_clock_get(dev_id, phy_id, ref_clock); - - return rv; -} - -sw_error_t -adpt_hppe_ptp_rx_timestamp_mode_set(a_uint32_t dev_id, - a_uint32_t port_id, - fal_ptp_rx_timestamp_mode_t ts_mode) -{ - sw_error_t rv = 0; - a_uint32_t phy_id = 0; - hsl_phy_ops_t *phy_drv; - - ADPT_DEV_ID_CHECK(dev_id); - - if (A_TRUE != hsl_port_prop_check (dev_id, port_id, HSL_PP_PHY)) - { - return SW_BAD_PARAM; - } - - SW_RTN_ON_NULL (phy_drv = hsl_phy_api_ops_get (dev_id, port_id)); - if (NULL == phy_drv->phy_ptp_ops.phy_ptp_rx_timestamp_mode_set) - { - return SW_NOT_SUPPORTED; - } - - rv = hsl_port_prop_get_phyid (dev_id, port_id, &phy_id); - SW_RTN_ON_ERROR (rv); - - rv = phy_drv->phy_ptp_ops.phy_ptp_rx_timestamp_mode_set(dev_id, phy_id, ts_mode); - - return rv; -} - -sw_error_t -adpt_hppe_ptp_rx_timestamp_mode_get(a_uint32_t dev_id, - a_uint32_t port_id, - fal_ptp_rx_timestamp_mode_t *ts_mode) -{ - sw_error_t rv = 0; - a_uint32_t phy_id = 0; - hsl_phy_ops_t *phy_drv; - - ADPT_DEV_ID_CHECK(dev_id); - ADPT_NULL_POINT_CHECK(ts_mode); - - if (A_TRUE != hsl_port_prop_check (dev_id, port_id, HSL_PP_PHY)) - { - return SW_BAD_PARAM; - } - - SW_RTN_ON_NULL (phy_drv = hsl_phy_api_ops_get (dev_id, port_id)); - if (NULL == phy_drv->phy_ptp_ops.phy_ptp_rx_timestamp_mode_get) - { - return SW_NOT_SUPPORTED; - } - - rv = hsl_port_prop_get_phyid (dev_id, port_id, &phy_id); - SW_RTN_ON_ERROR (rv); - - rv = phy_drv->phy_ptp_ops.phy_ptp_rx_timestamp_mode_get(dev_id, phy_id, ts_mode); - - return rv; -} - -sw_error_t -adpt_hppe_ptp_timestamp_get(a_uint32_t dev_id, a_uint32_t port_id, - fal_ptp_direction_t direction, - fal_ptp_pkt_info_t *pkt_info, - fal_ptp_time_t *time) -{ - sw_error_t rv = 0; - a_uint32_t phy_id = 0; - hsl_phy_ops_t *phy_drv; - - ADPT_DEV_ID_CHECK(dev_id); - ADPT_NULL_POINT_CHECK(time); - - if (A_TRUE != hsl_port_prop_check (dev_id, port_id, HSL_PP_PHY)) - { - return SW_BAD_PARAM; - } - - SW_RTN_ON_NULL (phy_drv = hsl_phy_api_ops_get (dev_id, port_id)); - if (NULL == phy_drv->phy_ptp_ops.phy_ptp_timestamp_get) - { - return SW_NOT_SUPPORTED; - } - - rv = hsl_port_prop_get_phyid (dev_id, port_id, &phy_id); - SW_RTN_ON_ERROR (rv); - - rv = phy_drv->phy_ptp_ops.phy_ptp_timestamp_get(dev_id, phy_id, direction, pkt_info, time); - - return rv; -} - -sw_error_t -adpt_hppe_ptp_pkt_timestamp_set(a_uint32_t dev_id, a_uint32_t port_id, - fal_ptp_time_t *time) -{ - sw_error_t rv = 0; - a_uint32_t phy_id = 0; - hsl_phy_ops_t *phy_drv; - - ADPT_DEV_ID_CHECK(dev_id); - ADPT_NULL_POINT_CHECK(time); - - if (A_TRUE != hsl_port_prop_check (dev_id, port_id, HSL_PP_PHY)) - { - return SW_BAD_PARAM; - } - - SW_RTN_ON_NULL (phy_drv = hsl_phy_api_ops_get (dev_id, port_id)); - if (NULL == phy_drv->phy_ptp_ops.phy_ptp_pkt_timestamp_set) - { - return SW_NOT_SUPPORTED; - } - - rv = hsl_port_prop_get_phyid (dev_id, port_id, &phy_id); - SW_RTN_ON_ERROR (rv); - - rv = phy_drv->phy_ptp_ops.phy_ptp_pkt_timestamp_set(dev_id, phy_id, time); - - return rv; -} - -sw_error_t -adpt_hppe_ptp_pkt_timestamp_get(a_uint32_t dev_id, a_uint32_t port_id, - fal_ptp_time_t *time) -{ - sw_error_t rv = 0; - a_uint32_t phy_id = 0; - hsl_phy_ops_t *phy_drv; - - ADPT_DEV_ID_CHECK(dev_id); - ADPT_NULL_POINT_CHECK(time); - - if (A_TRUE != hsl_port_prop_check (dev_id, port_id, HSL_PP_PHY)) - { - return SW_BAD_PARAM; - } - - SW_RTN_ON_NULL (phy_drv = hsl_phy_api_ops_get (dev_id, port_id)); - if (NULL == phy_drv->phy_ptp_ops.phy_ptp_pkt_timestamp_get) - { - return SW_NOT_SUPPORTED; - } - - rv = hsl_port_prop_get_phyid (dev_id, port_id, &phy_id); - SW_RTN_ON_ERROR (rv); - - rv = phy_drv->phy_ptp_ops.phy_ptp_pkt_timestamp_get(dev_id, phy_id, time); - - return rv; -} - -sw_error_t -adpt_hppe_ptp_grandmaster_mode_set(a_uint32_t dev_id, a_uint32_t port_id, - fal_ptp_grandmaster_mode_t *gm_mode) -{ - sw_error_t rv = 0; - a_uint32_t phy_id = 0; - hsl_phy_ops_t *phy_drv; - - ADPT_DEV_ID_CHECK(dev_id); - ADPT_NULL_POINT_CHECK(gm_mode); - - if (A_TRUE != hsl_port_prop_check (dev_id, port_id, HSL_PP_PHY)) - { - return SW_BAD_PARAM; - } - - SW_RTN_ON_NULL (phy_drv = hsl_phy_api_ops_get (dev_id, port_id)); - if (NULL == phy_drv->phy_ptp_ops.phy_ptp_grandmaster_mode_set) - { - return SW_NOT_SUPPORTED; - } - - rv = hsl_port_prop_get_phyid (dev_id, port_id, &phy_id); - SW_RTN_ON_ERROR (rv); - - rv = phy_drv->phy_ptp_ops.phy_ptp_grandmaster_mode_set(dev_id, phy_id, gm_mode); - - return rv; -} - -sw_error_t -adpt_hppe_ptp_grandmaster_mode_get(a_uint32_t dev_id, a_uint32_t port_id, - fal_ptp_grandmaster_mode_t *gm_mode) -{ - sw_error_t rv = 0; - a_uint32_t phy_id = 0; - hsl_phy_ops_t *phy_drv; - - ADPT_DEV_ID_CHECK(dev_id); - ADPT_NULL_POINT_CHECK(gm_mode); - - if (A_TRUE != hsl_port_prop_check (dev_id, port_id, HSL_PP_PHY)) - { - return SW_BAD_PARAM; - } - - SW_RTN_ON_NULL (phy_drv = hsl_phy_api_ops_get (dev_id, port_id)); - if (NULL == phy_drv->phy_ptp_ops.phy_ptp_grandmaster_mode_get) - { - return SW_NOT_SUPPORTED; - } - - rv = hsl_port_prop_get_phyid (dev_id, port_id, &phy_id); - SW_RTN_ON_ERROR (rv); - - rv = phy_drv->phy_ptp_ops.phy_ptp_grandmaster_mode_get(dev_id, phy_id, gm_mode); - - return rv; -} - -sw_error_t -adpt_hppe_ptp_rtc_time_get(a_uint32_t dev_id, a_uint32_t port_id, - fal_ptp_time_t *time) -{ - sw_error_t rv = 0; - a_uint32_t phy_id = 0; - hsl_phy_ops_t *phy_drv; - - ADPT_DEV_ID_CHECK(dev_id); - ADPT_NULL_POINT_CHECK(time); - - if (A_TRUE != hsl_port_prop_check (dev_id, port_id, HSL_PP_PHY)) - { - return SW_BAD_PARAM; - } - - SW_RTN_ON_NULL (phy_drv = hsl_phy_api_ops_get (dev_id, port_id)); - if (NULL == phy_drv->phy_ptp_ops.phy_ptp_rtc_time_get) - { - return SW_NOT_SUPPORTED; - } - - rv = hsl_port_prop_get_phyid (dev_id, port_id, &phy_id); - SW_RTN_ON_ERROR (rv); - - rv = phy_drv->phy_ptp_ops.phy_ptp_rtc_time_get(dev_id, phy_id, time); - - return rv; -} - -sw_error_t -adpt_hppe_ptp_rtc_time_set(a_uint32_t dev_id, a_uint32_t port_id, - fal_ptp_time_t *time) -{ - sw_error_t rv = 0; - a_uint32_t phy_id = 0; - hsl_phy_ops_t *phy_drv; - - ADPT_DEV_ID_CHECK(dev_id); - ADPT_NULL_POINT_CHECK(time); - - if (A_TRUE != hsl_port_prop_check (dev_id, port_id, HSL_PP_PHY)) - { - return SW_BAD_PARAM; - } - - SW_RTN_ON_NULL (phy_drv = hsl_phy_api_ops_get (dev_id, port_id)); - if (NULL == phy_drv->phy_ptp_ops.phy_ptp_rtc_time_set) - { - return SW_NOT_SUPPORTED; - } - - rv = hsl_port_prop_get_phyid (dev_id, port_id, &phy_id); - SW_RTN_ON_ERROR (rv); - - rv = phy_drv->phy_ptp_ops.phy_ptp_rtc_time_set(dev_id, phy_id, time); - - return rv; -} - -sw_error_t -adpt_hppe_ptp_rtc_time_clear(a_uint32_t dev_id, a_uint32_t port_id) -{ - sw_error_t rv = 0; - a_uint32_t phy_id = 0; - hsl_phy_ops_t *phy_drv; - - ADPT_DEV_ID_CHECK(dev_id); - - if (A_TRUE != hsl_port_prop_check (dev_id, port_id, HSL_PP_PHY)) - { - return SW_BAD_PARAM; - } - - SW_RTN_ON_NULL (phy_drv = hsl_phy_api_ops_get (dev_id, port_id)); - if (NULL == phy_drv->phy_ptp_ops.phy_ptp_rtc_time_clear) - { - return SW_NOT_SUPPORTED; - } - - rv = hsl_port_prop_get_phyid (dev_id, port_id, &phy_id); - SW_RTN_ON_ERROR (rv); - - rv = phy_drv->phy_ptp_ops.phy_ptp_rtc_time_clear(dev_id, phy_id); - - return rv; -} - -sw_error_t -adpt_hppe_ptp_rtc_adjtime_set(a_uint32_t dev_id, a_uint32_t port_id, - fal_ptp_time_t *time) -{ - sw_error_t rv = 0; - a_uint32_t phy_id = 0; - hsl_phy_ops_t *phy_drv; - - ADPT_DEV_ID_CHECK(dev_id); - ADPT_NULL_POINT_CHECK(time); - - if (A_TRUE != hsl_port_prop_check (dev_id, port_id, HSL_PP_PHY)) - { - return SW_BAD_PARAM; - } - - SW_RTN_ON_NULL (phy_drv = hsl_phy_api_ops_get (dev_id, port_id)); - if (NULL == phy_drv->phy_ptp_ops.phy_ptp_rtc_adjtime_set) - { - return SW_NOT_SUPPORTED; - } - - rv = hsl_port_prop_get_phyid (dev_id, port_id, &phy_id); - SW_RTN_ON_ERROR (rv); - - rv = phy_drv->phy_ptp_ops.phy_ptp_rtc_adjtime_set(dev_id, phy_id, time); - - return rv; -} - -sw_error_t -adpt_hppe_ptp_rtc_adjfreq_set(a_uint32_t dev_id, a_uint32_t port_id, - fal_ptp_time_t *time) -{ - sw_error_t rv = 0; - a_uint32_t phy_id = 0; - hsl_phy_ops_t *phy_drv; - - ADPT_DEV_ID_CHECK(dev_id); - ADPT_NULL_POINT_CHECK(time); - - if (A_TRUE != hsl_port_prop_check (dev_id, port_id, HSL_PP_PHY)) - { - return SW_BAD_PARAM; - } - - SW_RTN_ON_NULL (phy_drv = hsl_phy_api_ops_get (dev_id, port_id)); - if (NULL == phy_drv->phy_ptp_ops.phy_ptp_rtc_adjfreq_set) - { - return SW_NOT_SUPPORTED; - } - - rv = hsl_port_prop_get_phyid (dev_id, port_id, &phy_id); - SW_RTN_ON_ERROR (rv); - - rv = phy_drv->phy_ptp_ops.phy_ptp_rtc_adjfreq_set(dev_id, phy_id, time); - - return rv; -} - -sw_error_t -adpt_hppe_ptp_rtc_adjfreq_get(a_uint32_t dev_id, a_uint32_t port_id, - fal_ptp_time_t *time) -{ - sw_error_t rv = 0; - a_uint32_t phy_id = 0; - hsl_phy_ops_t *phy_drv; - - ADPT_DEV_ID_CHECK(dev_id); - ADPT_NULL_POINT_CHECK(time); - - if (A_TRUE != hsl_port_prop_check (dev_id, port_id, HSL_PP_PHY)) - { - return SW_BAD_PARAM; - } - - SW_RTN_ON_NULL (phy_drv = hsl_phy_api_ops_get (dev_id, port_id)); - if (NULL == phy_drv->phy_ptp_ops.phy_ptp_rtc_adjfreq_get) - { - return SW_NOT_SUPPORTED; - } - - rv = hsl_port_prop_get_phyid (dev_id, port_id, &phy_id); - SW_RTN_ON_ERROR (rv); - - rv = phy_drv->phy_ptp_ops.phy_ptp_rtc_adjfreq_get(dev_id, phy_id, time); - - return rv; -} - -sw_error_t -adpt_hppe_ptp_link_delay_set(a_uint32_t dev_id, a_uint32_t port_id, - fal_ptp_time_t *time) -{ - sw_error_t rv = 0; - a_uint32_t phy_id = 0; - hsl_phy_ops_t *phy_drv; - - ADPT_DEV_ID_CHECK(dev_id); - ADPT_NULL_POINT_CHECK(time); - - if (A_TRUE != hsl_port_prop_check (dev_id, port_id, HSL_PP_PHY)) - { - return SW_BAD_PARAM; - } - - SW_RTN_ON_NULL (phy_drv = hsl_phy_api_ops_get (dev_id, port_id)); - if (NULL == phy_drv->phy_ptp_ops.phy_ptp_link_delay_set) - { - return SW_NOT_SUPPORTED; - } - - rv = hsl_port_prop_get_phyid (dev_id, port_id, &phy_id); - SW_RTN_ON_ERROR (rv); - - rv = phy_drv->phy_ptp_ops.phy_ptp_link_delay_set(dev_id, phy_id, time); - - return rv; -} - -sw_error_t -adpt_hppe_ptp_link_delay_get(a_uint32_t dev_id, a_uint32_t port_id, - fal_ptp_time_t *time) -{ - sw_error_t rv = 0; - a_uint32_t phy_id = 0; - hsl_phy_ops_t *phy_drv; - - ADPT_DEV_ID_CHECK(dev_id); - ADPT_NULL_POINT_CHECK(time); - - if (A_TRUE != hsl_port_prop_check (dev_id, port_id, HSL_PP_PHY)) - { - return SW_BAD_PARAM; - } - - SW_RTN_ON_NULL (phy_drv = hsl_phy_api_ops_get (dev_id, port_id)); - if (NULL == phy_drv->phy_ptp_ops.phy_ptp_link_delay_get) - { - return SW_NOT_SUPPORTED; - } - - rv = hsl_port_prop_get_phyid (dev_id, port_id, &phy_id); - SW_RTN_ON_ERROR (rv); - - rv = phy_drv->phy_ptp_ops.phy_ptp_link_delay_get(dev_id, phy_id, time); - - return rv; -} - -sw_error_t -adpt_hppe_ptp_security_set(a_uint32_t dev_id, a_uint32_t port_id, - fal_ptp_security_t *sec) -{ - sw_error_t rv = 0; - a_uint32_t phy_id = 0; - hsl_phy_ops_t *phy_drv; - - ADPT_DEV_ID_CHECK(dev_id); - ADPT_NULL_POINT_CHECK(sec); - - if (A_TRUE != hsl_port_prop_check (dev_id, port_id, HSL_PP_PHY)) - { - return SW_BAD_PARAM; - } - - SW_RTN_ON_NULL (phy_drv = hsl_phy_api_ops_get (dev_id, port_id)); - if (NULL == phy_drv->phy_ptp_ops.phy_ptp_security_set) - { - return SW_NOT_SUPPORTED; - } - - rv = hsl_port_prop_get_phyid (dev_id, port_id, &phy_id); - SW_RTN_ON_ERROR (rv); - - rv = phy_drv->phy_ptp_ops.phy_ptp_security_set(dev_id, phy_id, sec); - - return rv; -} - -sw_error_t -adpt_hppe_ptp_security_get(a_uint32_t dev_id, a_uint32_t port_id, - fal_ptp_security_t *sec) -{ - sw_error_t rv = 0; - a_uint32_t phy_id = 0; - hsl_phy_ops_t *phy_drv; - - ADPT_DEV_ID_CHECK(dev_id); - ADPT_NULL_POINT_CHECK(sec); - - if (A_TRUE != hsl_port_prop_check (dev_id, port_id, HSL_PP_PHY)) - { - return SW_BAD_PARAM; - } - - SW_RTN_ON_NULL (phy_drv = hsl_phy_api_ops_get (dev_id, port_id)); - if (NULL == phy_drv->phy_ptp_ops.phy_ptp_security_get) - { - return SW_NOT_SUPPORTED; - } - - rv = hsl_port_prop_get_phyid (dev_id, port_id, &phy_id); - SW_RTN_ON_ERROR (rv); - - rv = phy_drv->phy_ptp_ops.phy_ptp_security_get(dev_id, phy_id, sec); - - return rv; -} - -sw_error_t -adpt_hppe_ptp_pps_signal_control_set(a_uint32_t dev_id, - a_uint32_t port_id, - fal_ptp_pps_signal_control_t *sig_control) -{ - sw_error_t rv = 0; - a_uint32_t phy_id = 0; - hsl_phy_ops_t *phy_drv; - - ADPT_DEV_ID_CHECK(dev_id); - ADPT_NULL_POINT_CHECK(sig_control); - - if (A_TRUE != hsl_port_prop_check (dev_id, port_id, HSL_PP_PHY)) - { - return SW_BAD_PARAM; - } - - SW_RTN_ON_NULL (phy_drv = hsl_phy_api_ops_get (dev_id, port_id)); - if (NULL == phy_drv->phy_ptp_ops.phy_ptp_pps_signal_control_set) - { - return SW_NOT_SUPPORTED; - } - - rv = hsl_port_prop_get_phyid (dev_id, port_id, &phy_id); - SW_RTN_ON_ERROR (rv); - - rv = phy_drv->phy_ptp_ops.phy_ptp_pps_signal_control_set(dev_id, phy_id, sig_control); - - return rv; -} - -sw_error_t -adpt_hppe_ptp_pps_signal_control_get(a_uint32_t dev_id, - a_uint32_t port_id, - fal_ptp_pps_signal_control_t *sig_control) -{ - sw_error_t rv = 0; - a_uint32_t phy_id = 0; - hsl_phy_ops_t *phy_drv; - - ADPT_DEV_ID_CHECK(dev_id); - ADPT_NULL_POINT_CHECK(sig_control); - - if (A_TRUE != hsl_port_prop_check (dev_id, port_id, HSL_PP_PHY)) - { - return SW_BAD_PARAM; - } - - SW_RTN_ON_NULL (phy_drv = hsl_phy_api_ops_get (dev_id, port_id)); - if (NULL == phy_drv->phy_ptp_ops.phy_ptp_pps_signal_control_get) - { - return SW_NOT_SUPPORTED; - } - - rv = hsl_port_prop_get_phyid (dev_id, port_id, &phy_id); - SW_RTN_ON_ERROR (rv); - - rv = phy_drv->phy_ptp_ops.phy_ptp_pps_signal_control_get(dev_id, phy_id, sig_control); - - return rv; -} - -sw_error_t -adpt_hppe_ptp_rx_crc_recalc_enable(a_uint32_t dev_id, a_uint32_t port_id, - a_bool_t status) -{ - sw_error_t rv = 0; - a_uint32_t phy_id = 0; - hsl_phy_ops_t *phy_drv; - - ADPT_DEV_ID_CHECK(dev_id); - - if (A_TRUE != hsl_port_prop_check (dev_id, port_id, HSL_PP_PHY)) - { - return SW_BAD_PARAM; - } - - SW_RTN_ON_NULL (phy_drv = hsl_phy_api_ops_get (dev_id, port_id)); - if (NULL == phy_drv->phy_ptp_ops.phy_ptp_rx_crc_recalc_enable) - { - return SW_NOT_SUPPORTED; - } - - rv = hsl_port_prop_get_phyid (dev_id, port_id, &phy_id); - SW_RTN_ON_ERROR (rv); - - rv = phy_drv->phy_ptp_ops.phy_ptp_rx_crc_recalc_enable(dev_id, phy_id, status); - - return rv; -} - -sw_error_t -adpt_hppe_ptp_rx_crc_recalc_status_get(a_uint32_t dev_id, - a_uint32_t port_id, a_bool_t *status) -{ - sw_error_t rv = 0; - a_uint32_t phy_id = 0; - hsl_phy_ops_t *phy_drv; - - ADPT_DEV_ID_CHECK(dev_id); - ADPT_NULL_POINT_CHECK(status); - - if (A_TRUE != hsl_port_prop_check (dev_id, port_id, HSL_PP_PHY)) - { - return SW_BAD_PARAM; - } - - SW_RTN_ON_NULL (phy_drv = hsl_phy_api_ops_get (dev_id, port_id)); - if (NULL == phy_drv->phy_ptp_ops.phy_ptp_rx_crc_recalc_status_get) - { - return SW_NOT_SUPPORTED; - } - - rv = hsl_port_prop_get_phyid (dev_id, port_id, &phy_id); - SW_RTN_ON_ERROR (rv); - - rv = phy_drv->phy_ptp_ops.phy_ptp_rx_crc_recalc_status_get(dev_id, phy_id, status); - - return rv; -} - -sw_error_t -adpt_hppe_ptp_asym_correction_set(a_uint32_t dev_id, a_uint32_t port_id, - fal_ptp_asym_correction_t *asym_cf) -{ - sw_error_t rv = 0; - a_uint32_t phy_id = 0; - hsl_phy_ops_t *phy_drv; - - ADPT_DEV_ID_CHECK(dev_id); - ADPT_NULL_POINT_CHECK(asym_cf); - - if (A_TRUE != hsl_port_prop_check (dev_id, port_id, HSL_PP_PHY)) - { - return SW_BAD_PARAM; - } - - SW_RTN_ON_NULL (phy_drv = hsl_phy_api_ops_get (dev_id, port_id)); - if (NULL == phy_drv->phy_ptp_ops.phy_ptp_asym_correction_set) - { - return SW_NOT_SUPPORTED; - } - - rv = hsl_port_prop_get_phyid (dev_id, port_id, &phy_id); - SW_RTN_ON_ERROR (rv); - - rv = phy_drv->phy_ptp_ops.phy_ptp_asym_correction_set(dev_id, phy_id, asym_cf); - - return rv; -} - -sw_error_t -adpt_hppe_ptp_asym_correction_get(a_uint32_t dev_id, a_uint32_t port_id, - fal_ptp_asym_correction_t* asym_cf) -{ - sw_error_t rv = 0; - a_uint32_t phy_id = 0; - hsl_phy_ops_t *phy_drv; - - ADPT_DEV_ID_CHECK(dev_id); - ADPT_NULL_POINT_CHECK(asym_cf); - - if (A_TRUE != hsl_port_prop_check (dev_id, port_id, HSL_PP_PHY)) - { - return SW_BAD_PARAM; - } - - SW_RTN_ON_NULL (phy_drv = hsl_phy_api_ops_get (dev_id, port_id)); - if (NULL == phy_drv->phy_ptp_ops.phy_ptp_asym_correction_get) - { - return SW_NOT_SUPPORTED; - } - - rv = hsl_port_prop_get_phyid (dev_id, port_id, &phy_id); - SW_RTN_ON_ERROR (rv); - - rv = phy_drv->phy_ptp_ops.phy_ptp_asym_correction_get(dev_id, phy_id, asym_cf); - - return rv; -} - -sw_error_t -adpt_hppe_ptp_output_waveform_set(a_uint32_t dev_id, a_uint32_t port_id, - fal_ptp_output_waveform_t *waveform) -{ - sw_error_t rv = 0; - a_uint32_t phy_id = 0; - hsl_phy_ops_t *phy_drv; - - ADPT_DEV_ID_CHECK(dev_id); - ADPT_NULL_POINT_CHECK(waveform); - - if (A_TRUE != hsl_port_prop_check (dev_id, port_id, HSL_PP_PHY)) - { - return SW_BAD_PARAM; - } - - SW_RTN_ON_NULL (phy_drv = hsl_phy_api_ops_get (dev_id, port_id)); - if (NULL == phy_drv->phy_ptp_ops.phy_ptp_output_waveform_set) - { - return SW_NOT_SUPPORTED; - } - - rv = hsl_port_prop_get_phyid (dev_id, port_id, &phy_id); - SW_RTN_ON_ERROR (rv); - - rv = phy_drv->phy_ptp_ops.phy_ptp_output_waveform_set(dev_id, phy_id, waveform); - - return rv; -} - -sw_error_t -adpt_hppe_ptp_output_waveform_get(a_uint32_t dev_id, a_uint32_t port_id, - fal_ptp_output_waveform_t *waveform) -{ - sw_error_t rv = 0; - a_uint32_t phy_id = 0; - hsl_phy_ops_t *phy_drv; - - ADPT_DEV_ID_CHECK(dev_id); - ADPT_NULL_POINT_CHECK(waveform); - - if (A_TRUE != hsl_port_prop_check (dev_id, port_id, HSL_PP_PHY)) - { - return SW_BAD_PARAM; - } - - SW_RTN_ON_NULL (phy_drv = hsl_phy_api_ops_get (dev_id, port_id)); - if (NULL == phy_drv->phy_ptp_ops.phy_ptp_output_waveform_get) - { - return SW_NOT_SUPPORTED; - } - - rv = hsl_port_prop_get_phyid (dev_id, port_id, &phy_id); - SW_RTN_ON_ERROR (rv); - - rv = phy_drv->phy_ptp_ops.phy_ptp_output_waveform_get(dev_id, phy_id, waveform); - - return rv; -} - -sw_error_t -adpt_hppe_ptp_rtc_time_snapshot_enable(a_uint32_t dev_id, - a_uint32_t port_id, a_bool_t status) -{ - sw_error_t rv = 0; - a_uint32_t phy_id = 0; - hsl_phy_ops_t *phy_drv; - - ADPT_DEV_ID_CHECK(dev_id); - - if (A_TRUE != hsl_port_prop_check (dev_id, port_id, HSL_PP_PHY)) - { - return SW_BAD_PARAM; - } - - SW_RTN_ON_NULL (phy_drv = hsl_phy_api_ops_get (dev_id, port_id)); - if (NULL == phy_drv->phy_ptp_ops.phy_ptp_rtc_time_snapshot_enable) - { - return SW_NOT_SUPPORTED; - } - - rv = hsl_port_prop_get_phyid (dev_id, port_id, &phy_id); - SW_RTN_ON_ERROR (rv); - - rv = phy_drv->phy_ptp_ops.phy_ptp_rtc_time_snapshot_enable(dev_id, phy_id, status); - - return rv; -} - -sw_error_t -adpt_hppe_ptp_rtc_time_snapshot_status_get(a_uint32_t dev_id, - a_uint32_t port_id, a_bool_t *status) -{ - sw_error_t rv = 0; - a_uint32_t phy_id = 0; - hsl_phy_ops_t *phy_drv; - - ADPT_DEV_ID_CHECK(dev_id); - ADPT_NULL_POINT_CHECK(status); - - if (A_TRUE != hsl_port_prop_check (dev_id, port_id, HSL_PP_PHY)) - { - return SW_BAD_PARAM; - } - - SW_RTN_ON_NULL (phy_drv = hsl_phy_api_ops_get (dev_id, port_id)); - if (NULL == phy_drv->phy_ptp_ops.phy_ptp_rtc_time_snapshot_status_get) - { - return SW_NOT_SUPPORTED; - } - - rv = hsl_port_prop_get_phyid (dev_id, port_id, &phy_id); - SW_RTN_ON_ERROR (rv); - - rv = phy_drv->phy_ptp_ops.phy_ptp_rtc_time_snapshot_status_get(dev_id, phy_id, status); - - return rv; -} - -sw_error_t -adpt_hppe_ptp_increment_sync_from_clock_enable(a_uint32_t dev_id, - a_uint32_t port_id, a_bool_t status) -{ - sw_error_t rv = 0; - a_uint32_t phy_id = 0; - hsl_phy_ops_t *phy_drv; - - ADPT_DEV_ID_CHECK(dev_id); - - if (A_TRUE != hsl_port_prop_check (dev_id, port_id, HSL_PP_PHY)) - { - return SW_BAD_PARAM; - } - - SW_RTN_ON_NULL (phy_drv = hsl_phy_api_ops_get (dev_id, port_id)); - if (NULL == phy_drv->phy_ptp_ops.phy_ptp_increment_sync_from_clock_enable) - { - return SW_NOT_SUPPORTED; - } - - rv = hsl_port_prop_get_phyid (dev_id, port_id, &phy_id); - SW_RTN_ON_ERROR (rv); - - rv = phy_drv->phy_ptp_ops.phy_ptp_increment_sync_from_clock_enable(dev_id, phy_id, status); - - return rv; -} - -sw_error_t -adpt_hppe_ptp_increment_sync_from_clock_status_get(a_uint32_t dev_id, - a_uint32_t port_id, a_bool_t *status) -{ - sw_error_t rv = 0; - a_uint32_t phy_id = 0; - hsl_phy_ops_t *phy_drv; - - ADPT_DEV_ID_CHECK(dev_id); - ADPT_NULL_POINT_CHECK(status); - - if (A_TRUE != hsl_port_prop_check (dev_id, port_id, HSL_PP_PHY)) - { - return SW_BAD_PARAM; - } - - SW_RTN_ON_NULL (phy_drv = hsl_phy_api_ops_get (dev_id, port_id)); - if (NULL == phy_drv->phy_ptp_ops.phy_ptp_increment_sync_from_clock_status_get) - { - return SW_NOT_SUPPORTED; - } - - rv = hsl_port_prop_get_phyid (dev_id, port_id, &phy_id); - SW_RTN_ON_ERROR (rv); - - rv = phy_drv->phy_ptp_ops.phy_ptp_increment_sync_from_clock_status_get(dev_id, - phy_id, status); - - return rv; -} - -sw_error_t -adpt_hppe_ptp_tod_uart_set(a_uint32_t dev_id, a_uint32_t port_id, - fal_ptp_tod_uart_t *tod_uart) -{ - sw_error_t rv = 0; - a_uint32_t phy_id = 0; - hsl_phy_ops_t *phy_drv; - - ADPT_DEV_ID_CHECK(dev_id); - ADPT_NULL_POINT_CHECK(tod_uart); - - if (A_TRUE != hsl_port_prop_check (dev_id, port_id, HSL_PP_PHY)) - { - return SW_BAD_PARAM; - } - - SW_RTN_ON_NULL (phy_drv = hsl_phy_api_ops_get (dev_id, port_id)); - if (NULL == phy_drv->phy_ptp_ops.phy_ptp_tod_uart_set) - { - return SW_NOT_SUPPORTED; - } - - rv = hsl_port_prop_get_phyid (dev_id, port_id, &phy_id); - SW_RTN_ON_ERROR (rv); - - rv = phy_drv->phy_ptp_ops.phy_ptp_tod_uart_set(dev_id, phy_id, tod_uart); - - return rv; -} - -sw_error_t -adpt_hppe_ptp_tod_uart_get(a_uint32_t dev_id, a_uint32_t port_id, - fal_ptp_tod_uart_t *tod_uart) -{ - sw_error_t rv = 0; - a_uint32_t phy_id = 0; - hsl_phy_ops_t *phy_drv; - - ADPT_DEV_ID_CHECK(dev_id); - ADPT_NULL_POINT_CHECK(tod_uart); - - if (A_TRUE != hsl_port_prop_check (dev_id, port_id, HSL_PP_PHY)) - { - return SW_BAD_PARAM; - } - - SW_RTN_ON_NULL (phy_drv = hsl_phy_api_ops_get (dev_id, port_id)); - if (NULL == phy_drv->phy_ptp_ops.phy_ptp_tod_uart_get) - { - return SW_NOT_SUPPORTED; - } - - rv = hsl_port_prop_get_phyid (dev_id, port_id, &phy_id); - SW_RTN_ON_ERROR (rv); - - rv = phy_drv->phy_ptp_ops.phy_ptp_tod_uart_get(dev_id, phy_id, tod_uart); - - return rv; -} - -sw_error_t -adpt_hppe_ptp_enhanced_timestamp_engine_set(a_uint32_t dev_id, - a_uint32_t port_id, fal_ptp_direction_t direction, - fal_ptp_enhanced_ts_engine_t *ts_engine) -{ - sw_error_t rv = 0; - a_uint32_t phy_id = 0; - hsl_phy_ops_t *phy_drv; - - ADPT_DEV_ID_CHECK(dev_id); - ADPT_NULL_POINT_CHECK(ts_engine); - - if (A_TRUE != hsl_port_prop_check (dev_id, port_id, HSL_PP_PHY)) - { - return SW_BAD_PARAM; - } - - SW_RTN_ON_NULL (phy_drv = hsl_phy_api_ops_get (dev_id, port_id)); - if (NULL == phy_drv->phy_ptp_ops.phy_ptp_enhanced_timestamp_engine_set) - { - return SW_NOT_SUPPORTED; - } - - rv = hsl_port_prop_get_phyid (dev_id, port_id, &phy_id); - SW_RTN_ON_ERROR (rv); - - rv = phy_drv->phy_ptp_ops.phy_ptp_enhanced_timestamp_engine_set(dev_id, - phy_id, direction, ts_engine); - - return rv; -} - -sw_error_t -adpt_hppe_ptp_enhanced_timestamp_engine_get(a_uint32_t dev_id, - a_uint32_t port_id, fal_ptp_direction_t direction, - fal_ptp_enhanced_ts_engine_t *ts_engine) -{ - sw_error_t rv = 0; - a_uint32_t phy_id = 0; - hsl_phy_ops_t *phy_drv; - - ADPT_DEV_ID_CHECK(dev_id); - ADPT_NULL_POINT_CHECK(ts_engine); - - if (A_TRUE != hsl_port_prop_check (dev_id, port_id, HSL_PP_PHY)) - { - return SW_BAD_PARAM; - } - - SW_RTN_ON_NULL (phy_drv = hsl_phy_api_ops_get (dev_id, port_id)); - if (NULL == phy_drv->phy_ptp_ops.phy_ptp_enhanced_timestamp_engine_get) - { - return SW_NOT_SUPPORTED; - } - - rv = hsl_port_prop_get_phyid (dev_id, port_id, &phy_id); - SW_RTN_ON_ERROR (rv); - - rv = phy_drv->phy_ptp_ops.phy_ptp_enhanced_timestamp_engine_get(dev_id, - phy_id, direction, ts_engine); - - return rv; -} - -sw_error_t -adpt_hppe_ptp_trigger_set(a_uint32_t dev_id, a_uint32_t port_id, - a_uint32_t trigger_id, fal_ptp_trigger_t *triger) -{ - sw_error_t rv = 0; - a_uint32_t phy_id = 0; - hsl_phy_ops_t *phy_drv; - - ADPT_DEV_ID_CHECK(dev_id); - ADPT_NULL_POINT_CHECK(triger); - - if (A_TRUE != hsl_port_prop_check (dev_id, port_id, HSL_PP_PHY)) - { - return SW_BAD_PARAM; - } - - SW_RTN_ON_NULL (phy_drv = hsl_phy_api_ops_get (dev_id, port_id)); - if (NULL == phy_drv->phy_ptp_ops.phy_ptp_trigger_set) - { - return SW_NOT_SUPPORTED; - } - - rv = hsl_port_prop_get_phyid (dev_id, port_id, &phy_id); - SW_RTN_ON_ERROR (rv); - - rv = phy_drv->phy_ptp_ops.phy_ptp_trigger_set(dev_id, phy_id, trigger_id, triger); - - return rv; -} - -sw_error_t -adpt_hppe_ptp_trigger_get(a_uint32_t dev_id, a_uint32_t port_id, - a_uint32_t trigger_id, fal_ptp_trigger_t *triger) -{ - sw_error_t rv = 0; - a_uint32_t phy_id = 0; - hsl_phy_ops_t *phy_drv; - - ADPT_DEV_ID_CHECK(dev_id); - ADPT_NULL_POINT_CHECK(triger); - - if (A_TRUE != hsl_port_prop_check (dev_id, port_id, HSL_PP_PHY)) - { - return SW_BAD_PARAM; - } - - SW_RTN_ON_NULL (phy_drv = hsl_phy_api_ops_get (dev_id, port_id)); - if (NULL == phy_drv->phy_ptp_ops.phy_ptp_trigger_get) - { - return SW_NOT_SUPPORTED; - } - - rv = hsl_port_prop_get_phyid (dev_id, port_id, &phy_id); - SW_RTN_ON_ERROR (rv); - - rv = phy_drv->phy_ptp_ops.phy_ptp_trigger_get(dev_id, phy_id, trigger_id, triger); - - return rv; -} - -sw_error_t -adpt_hppe_ptp_capture_set(a_uint32_t dev_id, a_uint32_t port_id, - a_uint32_t capture_id, fal_ptp_capture_t *capture) -{ - sw_error_t rv = 0; - a_uint32_t phy_id = 0; - hsl_phy_ops_t *phy_drv; - - ADPT_DEV_ID_CHECK(dev_id); - ADPT_NULL_POINT_CHECK(capture); - - if (A_TRUE != hsl_port_prop_check (dev_id, port_id, HSL_PP_PHY)) - { - return SW_BAD_PARAM; - } - - SW_RTN_ON_NULL (phy_drv = hsl_phy_api_ops_get (dev_id, port_id)); - if (NULL == phy_drv->phy_ptp_ops.phy_ptp_capture_set) - { - return SW_NOT_SUPPORTED; - } - - rv = hsl_port_prop_get_phyid (dev_id, port_id, &phy_id); - SW_RTN_ON_ERROR (rv); - - rv = phy_drv->phy_ptp_ops.phy_ptp_capture_set(dev_id, phy_id, capture_id, capture); - - return rv; -} - -sw_error_t -adpt_hppe_ptp_capture_get(a_uint32_t dev_id, a_uint32_t port_id, - a_uint32_t capture_id, fal_ptp_capture_t *capture) -{ - sw_error_t rv = 0; - a_uint32_t phy_id = 0; - hsl_phy_ops_t *phy_drv; - - ADPT_DEV_ID_CHECK(dev_id); - ADPT_NULL_POINT_CHECK(capture); - - if (A_TRUE != hsl_port_prop_check (dev_id, port_id, HSL_PP_PHY)) - { - return SW_BAD_PARAM; - } - - SW_RTN_ON_NULL (phy_drv = hsl_phy_api_ops_get (dev_id, port_id)); - if (NULL == phy_drv->phy_ptp_ops.phy_ptp_capture_get) - { - return SW_NOT_SUPPORTED; - } - - rv = hsl_port_prop_get_phyid (dev_id, port_id, &phy_id); - SW_RTN_ON_ERROR (rv); - - rv = phy_drv->phy_ptp_ops.phy_ptp_capture_get(dev_id, phy_id, capture_id, capture); - - return rv; -} - -sw_error_t -adpt_hppe_ptp_interrupt_set(a_uint32_t dev_id, a_uint32_t port_id, - fal_ptp_interrupt_t *interrupt) -{ - sw_error_t rv = 0; - a_uint32_t phy_id = 0; - hsl_phy_ops_t *phy_drv; - - ADPT_DEV_ID_CHECK(dev_id); - ADPT_NULL_POINT_CHECK(interrupt); - - if (A_TRUE != hsl_port_prop_check (dev_id, port_id, HSL_PP_PHY)) - { - return SW_BAD_PARAM; - } - - SW_RTN_ON_NULL (phy_drv = hsl_phy_api_ops_get (dev_id, port_id)); - if (NULL == phy_drv->phy_ptp_ops.phy_ptp_interrupt_set) - { - return SW_NOT_SUPPORTED; - } - - rv = hsl_port_prop_get_phyid (dev_id, port_id, &phy_id); - SW_RTN_ON_ERROR (rv); - - rv = phy_drv->phy_ptp_ops.phy_ptp_interrupt_set(dev_id, phy_id, interrupt); - - return rv; -} - -sw_error_t -adpt_hppe_ptp_interrupt_get(a_uint32_t dev_id, a_uint32_t port_id, - fal_ptp_interrupt_t *interrupt) -{ - sw_error_t rv = 0; - a_uint32_t phy_id = 0; - hsl_phy_ops_t *phy_drv; - - ADPT_DEV_ID_CHECK(dev_id); - ADPT_NULL_POINT_CHECK(interrupt); - - if (A_TRUE != hsl_port_prop_check (dev_id, port_id, HSL_PP_PHY)) - { - return SW_BAD_PARAM; - } - - SW_RTN_ON_NULL (phy_drv = hsl_phy_api_ops_get (dev_id, port_id)); - if (NULL == phy_drv->phy_ptp_ops.phy_ptp_interrupt_get) - { - return SW_NOT_SUPPORTED; - } - - rv = hsl_port_prop_get_phyid (dev_id, port_id, &phy_id); - SW_RTN_ON_ERROR (rv); - - rv = phy_drv->phy_ptp_ops.phy_ptp_interrupt_get(dev_id, phy_id, interrupt); - - return rv; -} - -sw_error_t adpt_hppe_ptp_init(a_uint32_t dev_id) -{ - adpt_api_t *p_adpt_api = NULL; - - p_adpt_api = adpt_api_ptr_get(dev_id); - - if(p_adpt_api == NULL) - { - return SW_FAIL; - } - - p_adpt_api->adpt_ptp_config_set = adpt_hppe_ptp_config_set; - p_adpt_api->adpt_ptp_config_get = adpt_hppe_ptp_config_get; - p_adpt_api->adpt_ptp_reference_clock_set = adpt_hppe_ptp_reference_clock_set; - p_adpt_api->adpt_ptp_reference_clock_get = adpt_hppe_ptp_reference_clock_get; - p_adpt_api->adpt_ptp_rx_timestamp_mode_set = adpt_hppe_ptp_rx_timestamp_mode_set; - p_adpt_api->adpt_ptp_rx_timestamp_mode_get = adpt_hppe_ptp_rx_timestamp_mode_get; - p_adpt_api->adpt_ptp_timestamp_get = adpt_hppe_ptp_timestamp_get; - p_adpt_api->adpt_ptp_pkt_timestamp_set = adpt_hppe_ptp_pkt_timestamp_set; - p_adpt_api->adpt_ptp_pkt_timestamp_get = adpt_hppe_ptp_pkt_timestamp_get; - p_adpt_api->adpt_ptp_grandmaster_mode_set = adpt_hppe_ptp_grandmaster_mode_set; - p_adpt_api->adpt_ptp_grandmaster_mode_get = adpt_hppe_ptp_grandmaster_mode_get; - p_adpt_api->adpt_ptp_rtc_time_set = adpt_hppe_ptp_rtc_time_set; - p_adpt_api->adpt_ptp_rtc_time_get = adpt_hppe_ptp_rtc_time_get; - p_adpt_api->adpt_ptp_rtc_time_clear = adpt_hppe_ptp_rtc_time_clear; - p_adpt_api->adpt_ptp_rtc_adjtime_set = adpt_hppe_ptp_rtc_adjtime_set; - p_adpt_api->adpt_ptp_rtc_adjfreq_set = adpt_hppe_ptp_rtc_adjfreq_set; - p_adpt_api->adpt_ptp_rtc_adjfreq_get = adpt_hppe_ptp_rtc_adjfreq_get; - p_adpt_api->adpt_ptp_link_delay_set = adpt_hppe_ptp_link_delay_set; - p_adpt_api->adpt_ptp_link_delay_get = adpt_hppe_ptp_link_delay_get; - p_adpt_api->adpt_ptp_security_set = adpt_hppe_ptp_security_set; - p_adpt_api->adpt_ptp_security_get = adpt_hppe_ptp_security_get; - p_adpt_api->adpt_ptp_pps_signal_control_set = adpt_hppe_ptp_pps_signal_control_set; - p_adpt_api->adpt_ptp_pps_signal_control_get = adpt_hppe_ptp_pps_signal_control_get; - p_adpt_api->adpt_ptp_rx_crc_recalc_enable = adpt_hppe_ptp_rx_crc_recalc_enable; - p_adpt_api->adpt_ptp_rx_crc_recalc_status_get = adpt_hppe_ptp_rx_crc_recalc_status_get; - p_adpt_api->adpt_ptp_asym_correction_set = adpt_hppe_ptp_asym_correction_set; - p_adpt_api->adpt_ptp_asym_correction_get = adpt_hppe_ptp_asym_correction_get; - p_adpt_api->adpt_ptp_output_waveform_set = adpt_hppe_ptp_output_waveform_set; - p_adpt_api->adpt_ptp_output_waveform_get = adpt_hppe_ptp_output_waveform_get; - p_adpt_api->adpt_ptp_rtc_time_snapshot_enable = adpt_hppe_ptp_rtc_time_snapshot_enable; - p_adpt_api->adpt_ptp_tod_uart_set = adpt_hppe_ptp_tod_uart_set; - p_adpt_api->adpt_ptp_tod_uart_get = adpt_hppe_ptp_tod_uart_get; - p_adpt_api->adpt_ptp_trigger_set = adpt_hppe_ptp_trigger_set; - p_adpt_api->adpt_ptp_trigger_get = adpt_hppe_ptp_trigger_get; - p_adpt_api->adpt_ptp_capture_set = adpt_hppe_ptp_capture_set; - p_adpt_api->adpt_ptp_capture_get = adpt_hppe_ptp_capture_get; - p_adpt_api->adpt_ptp_interrupt_set = adpt_hppe_ptp_interrupt_set; - p_adpt_api->adpt_ptp_interrupt_get = adpt_hppe_ptp_interrupt_get; - p_adpt_api->adpt_ptp_rtc_time_snapshot_status_get = - adpt_hppe_ptp_rtc_time_snapshot_status_get; - p_adpt_api->adpt_ptp_increment_sync_from_clock_enable = - adpt_hppe_ptp_increment_sync_from_clock_enable; - p_adpt_api->adpt_ptp_increment_sync_from_clock_status_get = - adpt_hppe_ptp_increment_sync_from_clock_status_get; - p_adpt_api->adpt_ptp_enhanced_timestamp_engine_set = - adpt_hppe_ptp_enhanced_timestamp_engine_set; - p_adpt_api->adpt_ptp_enhanced_timestamp_engine_get = - adpt_hppe_ptp_enhanced_timestamp_engine_get; - - return SW_OK; -} - -/** - * @} - */ diff --git a/feeds/ipq807x/qca-ssdk/src/src/adpt/hppe/adpt_hppe_qm.c b/feeds/ipq807x/qca-ssdk/src/src/adpt/hppe/adpt_hppe_qm.c deleted file mode 100755 index 9c33c1946..000000000 --- a/feeds/ipq807x/qca-ssdk/src/src/adpt/hppe/adpt_hppe_qm.c +++ /dev/null @@ -1,1413 +0,0 @@ -/* - * Copyright (c) 2016-2017, The Linux Foundation. All rights reserved. - * Permission to use, copy, modify, and/or distribute this software for - * any purpose with or without fee is hereby granted, provided that the - * above copyright notice and this permission notice appear in all copies. - * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES - * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR - * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES - * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN - * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT - * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. - */ - - -/** - * @defgroup - * @{ - */ -#include "sw.h" -#include "fal_qm.h" -#include "hppe_reg_access.h" -#include "hppe_qm_reg.h" -#include "hppe_qm.h" -#include "hppe_qos_reg.h" -#include "hppe_qos.h" -#include "hppe_portvlan_reg.h" -#include "hppe_portvlan.h" -#include "hppe_portctrl_reg.h" -#include "hppe_portctrl.h" -#include "adpt.h" -#include "adpt_hppe.h" -#if defined(CPPE) -#include "adpt_cppe_qm.h" -#endif - -#define SERVICE_CODE_QUEUE_OFFSET 2048 -#define CPU_CODE_QUEUE_OFFSET 1024 -#define VP_PORT_QUEUE_OFFSET 0 - -#define UCAST_QUEUE_ID_MAX 256 -#define ALL_QUEUE_ID_MAX 300 -#define MCAST_QUEUE_PORT7_START 296 -#define MCAST_QUEUE_PORT6_START 292 -#define MCAST_QUEUE_PORT5_START 288 -#define MCAST_QUEUE_PORT4_START 284 -#define MCAST_QUEUE_PORT3_START 280 -#define MCAST_QUEUE_PORT2_START 276 -#define MCAST_QUEUE_PORT1_START 272 -#define MCAST_QUEUE_PORT0_START 256 -#define MCAST_QUEUE_OFFSET (3*0x10) -#define UCAST_QUEUE_ITEMS 6 -#define MCAST_QUEUE_ITEMS 3 -#define DROP_INC 0x10 - -#ifndef IN_QM_MINI -sw_error_t -adpt_hppe_ucast_hash_map_set( - a_uint32_t dev_id, - a_uint8_t profile, - a_uint8_t rss_hash, - a_int8_t queue_hash) -{ - union ucast_hash_map_tbl_u ucast_hash_map_tbl; - a_uint32_t index = 0; - - memset(&ucast_hash_map_tbl, 0, sizeof(ucast_hash_map_tbl)); - ADPT_DEV_ID_CHECK(dev_id); - - index = profile << 8 | rss_hash; - ucast_hash_map_tbl.bf.hash = queue_hash; - - return hppe_ucast_hash_map_tbl_set(dev_id, index, &ucast_hash_map_tbl); -} - -sw_error_t -adpt_hppe_ac_dynamic_threshold_get( - a_uint32_t dev_id, - a_uint32_t queue_id, - fal_ac_dynamic_threshold_t *cfg) -{ - sw_error_t rv = SW_OK; - union ac_uni_queue_cfg_tbl_u ac_uni_queue_cfg_tbl; - - memset(&ac_uni_queue_cfg_tbl, 0, sizeof(ac_uni_queue_cfg_tbl)); - ADPT_DEV_ID_CHECK(dev_id); - ADPT_NULL_POINT_CHECK(cfg); - - rv = hppe_ac_uni_queue_cfg_tbl_get(dev_id, queue_id, &ac_uni_queue_cfg_tbl); - if( rv != SW_OK ) - return rv; - - cfg->wred_enable = ac_uni_queue_cfg_tbl.bf.ac_cfg_wred_en; - cfg->color_enable = ac_uni_queue_cfg_tbl.bf.ac_cfg_color_aware; - cfg->shared_weight = ac_uni_queue_cfg_tbl.bf.ac_cfg_shared_weight; - cfg->green_min_off = ac_uni_queue_cfg_tbl.bf.ac_cfg_gap_grn_grn_min; - cfg->yel_max_off = ac_uni_queue_cfg_tbl.bf.ac_cfg_gap_grn_yel_max; - cfg->yel_min_off = ac_uni_queue_cfg_tbl.bf.ac_cfg_gap_grn_yel_min_0 | \ - ac_uni_queue_cfg_tbl.bf.ac_cfg_gap_grn_yel_min_1 << 10; - cfg->red_max_off = ac_uni_queue_cfg_tbl.bf.ac_cfg_gap_grn_red_max; - cfg->red_min_off = ac_uni_queue_cfg_tbl.bf.ac_cfg_gap_grn_red_min; - cfg->green_resume_off = ac_uni_queue_cfg_tbl.bf.ac_cfg_grn_resume_offset; - cfg->yel_resume_off = ac_uni_queue_cfg_tbl.bf.ac_cfg_yel_resume_offset; - cfg->red_resume_off = ac_uni_queue_cfg_tbl.bf.ac_cfg_red_resume_offset_0 | \ - ac_uni_queue_cfg_tbl.bf.ac_cfg_red_resume_offset_1 << 9; - cfg->ceiling = ac_uni_queue_cfg_tbl.bf.ac_cfg_shared_ceiling; - - return SW_OK; -} - -sw_error_t -adpt_hppe_ucast_queue_base_profile_get( - a_uint32_t dev_id, - fal_ucast_queue_dest_t *queue_dest, - a_uint32_t *queue_base, a_uint8_t *profile) -{ - sw_error_t rv = SW_OK; - union ucast_queue_map_tbl_u ucast_queue_map_tbl; - a_uint32_t index = 0; - - memset(&ucast_queue_map_tbl, 0, sizeof(ucast_queue_map_tbl)); - ADPT_DEV_ID_CHECK(dev_id); - ADPT_NULL_POINT_CHECK(queue_dest); - ADPT_NULL_POINT_CHECK(queue_base); - ADPT_NULL_POINT_CHECK(profile); - - if (queue_dest ->service_code_en) { - index = SERVICE_CODE_QUEUE_OFFSET + (queue_dest->src_profile << 8) \ - + queue_dest->service_code; - } else if (queue_dest ->cpu_code_en) { - index = CPU_CODE_QUEUE_OFFSET + (queue_dest->src_profile << 8) \ - + queue_dest->cpu_code; - } else { - index = VP_PORT_QUEUE_OFFSET + (queue_dest->src_profile << 8) \ - + queue_dest->dst_port; - } - - rv = hppe_ucast_queue_map_tbl_get(dev_id, index, &ucast_queue_map_tbl); - if (rv) - return rv; - *queue_base = ucast_queue_map_tbl.bf.queue_id; - *profile = ucast_queue_map_tbl.bf.profile_id; - - return SW_OK; -} - -sw_error_t -adpt_hppe_port_mcast_priority_class_get( - a_uint32_t dev_id, - fal_port_t port, - a_uint8_t priority, - a_uint8_t *queue_class) -{ - sw_error_t rv = SW_OK; - union mcast_priority_map0_u mcast_priority_map0; - - ADPT_DEV_ID_CHECK(dev_id); - ADPT_NULL_POINT_CHECK(queue_class); - - - if (port == 0){ - rv = hppe_mcast_priority_map0_get(dev_id, priority, &mcast_priority_map0); - } else if (port == 1) { - rv = hppe_mcast_priority_map1_get(dev_id, priority, - (union mcast_priority_map1_u *)&mcast_priority_map0); - } else if (port == 2) { - rv = hppe_mcast_priority_map2_get(dev_id, priority, - (union mcast_priority_map2_u *)&mcast_priority_map0); - } else if (port == 3) { - rv = hppe_mcast_priority_map3_get(dev_id, priority, - (union mcast_priority_map3_u *)&mcast_priority_map0); - } else if (port == 4) { - rv = hppe_mcast_priority_map4_get(dev_id, priority, - (union mcast_priority_map4_u *)&mcast_priority_map0); - } else if (port == 5) { - rv = hppe_mcast_priority_map5_get(dev_id, priority, - (union mcast_priority_map5_u *)&mcast_priority_map0); - } else if (port == 6) { - rv = hppe_mcast_priority_map6_get(dev_id, priority, - (union mcast_priority_map6_u *)&mcast_priority_map0); - } else if (port == 7) { - rv = hppe_mcast_priority_map7_get(dev_id, priority, - (union mcast_priority_map7_u *)&mcast_priority_map0); - } - - if( rv != SW_OK ) - return rv; - - *queue_class = mcast_priority_map0.bf.class; - return SW_OK; -} -#endif - -sw_error_t -adpt_hppe_ac_dynamic_threshold_set( - a_uint32_t dev_id, - a_uint32_t queue_id, - fal_ac_dynamic_threshold_t *cfg) -{ - sw_error_t rv = SW_OK; - union ac_uni_queue_cfg_tbl_u ac_uni_queue_cfg_tbl; - - memset(&ac_uni_queue_cfg_tbl, 0, sizeof(ac_uni_queue_cfg_tbl)); - ADPT_DEV_ID_CHECK(dev_id); - ADPT_NULL_POINT_CHECK(cfg); - - rv = hppe_ac_uni_queue_cfg_tbl_get(dev_id, queue_id, &ac_uni_queue_cfg_tbl); - if( rv != SW_OK ) - return rv; - - ac_uni_queue_cfg_tbl.bf.ac_cfg_wred_en = cfg->wred_enable; - ac_uni_queue_cfg_tbl.bf.ac_cfg_color_aware = cfg->color_enable; - ac_uni_queue_cfg_tbl.bf.ac_cfg_shared_dynamic = 1; - ac_uni_queue_cfg_tbl.bf.ac_cfg_gap_grn_grn_min = cfg->green_min_off; - ac_uni_queue_cfg_tbl.bf.ac_cfg_gap_grn_yel_max = cfg->yel_max_off; - ac_uni_queue_cfg_tbl.bf.ac_cfg_gap_grn_yel_min_0 = cfg->yel_min_off; - ac_uni_queue_cfg_tbl.bf.ac_cfg_gap_grn_yel_min_1 = cfg->yel_min_off >> 20; - ac_uni_queue_cfg_tbl.bf.ac_cfg_gap_grn_red_max = cfg->red_max_off; - ac_uni_queue_cfg_tbl.bf.ac_cfg_gap_grn_red_min = cfg->red_min_off; - ac_uni_queue_cfg_tbl.bf.ac_cfg_grn_resume_offset = cfg->green_resume_off; - ac_uni_queue_cfg_tbl.bf.ac_cfg_yel_resume_offset = cfg->yel_resume_off; - ac_uni_queue_cfg_tbl.bf.ac_cfg_red_resume_offset_0 = cfg->red_resume_off; - ac_uni_queue_cfg_tbl.bf.ac_cfg_red_resume_offset_1 = cfg->red_resume_off >> 9; - ac_uni_queue_cfg_tbl.bf.ac_cfg_shared_weight = cfg->shared_weight; - ac_uni_queue_cfg_tbl.bf.ac_cfg_shared_ceiling = cfg->ceiling; - - return hppe_ac_uni_queue_cfg_tbl_set(dev_id, queue_id, &ac_uni_queue_cfg_tbl); -} - -sw_error_t -adpt_hppe_ac_prealloc_buffer_set( - a_uint32_t dev_id, - fal_ac_obj_t *obj, - a_uint16_t num) -{ - ADPT_DEV_ID_CHECK(dev_id); - - if (obj->type == FAL_AC_GROUP) { - union ac_grp_cfg_tbl_u ac_grp_cfg_tbl; - - memset(&ac_grp_cfg_tbl, 0, sizeof(ac_grp_cfg_tbl)); - hppe_ac_grp_cfg_tbl_get(dev_id, obj->obj_id, &ac_grp_cfg_tbl); - - ac_grp_cfg_tbl.bf.ac_grp_palloc_limit = num; - - return hppe_ac_grp_cfg_tbl_set(dev_id, obj->obj_id, &ac_grp_cfg_tbl); - - } else if (obj->type == FAL_AC_QUEUE) { - if (obj->obj_id < UCAST_QUEUE_ID_MAX) { - union ac_uni_queue_cfg_tbl_u ac_uni_queue_cfg_tbl; - hppe_ac_uni_queue_cfg_tbl_get(dev_id, - obj->obj_id, - &ac_uni_queue_cfg_tbl); - ac_uni_queue_cfg_tbl.bf.ac_cfg_pre_alloc_limit = num; - return hppe_ac_uni_queue_cfg_tbl_set(dev_id, - obj->obj_id, - &ac_uni_queue_cfg_tbl);; - - } else { - union ac_mul_queue_cfg_tbl_u ac_mul_queue_cfg_tbl; - hppe_ac_mul_queue_cfg_tbl_get(dev_id, - obj->obj_id - UCAST_QUEUE_ID_MAX, - &ac_mul_queue_cfg_tbl); - ac_mul_queue_cfg_tbl.bf.ac_cfg_pre_alloc_limit = num; - return hppe_ac_mul_queue_cfg_tbl_set(dev_id, - obj->obj_id -UCAST_QUEUE_ID_MAX, - &ac_mul_queue_cfg_tbl); - } - } else - return SW_FAIL; -} -#ifndef IN_QM_MINI -sw_error_t -adpt_hppe_ucast_default_hash_get( - a_uint32_t dev_id, - a_uint8_t *hash_value) -{ - sw_error_t rv = SW_OK; - union ucast_default_hash_u ucast_default_hash; - - memset(&ucast_default_hash, 0, sizeof(ucast_default_hash)); - ADPT_DEV_ID_CHECK(dev_id); - ADPT_NULL_POINT_CHECK(hash_value); - - rv = hppe_ucast_default_hash_get(dev_id, &ucast_default_hash); - if( rv != SW_OK ) - return rv; - - *hash_value = ucast_default_hash.bf.hash; - return SW_OK; -} - -sw_error_t -adpt_hppe_ucast_default_hash_set( - a_uint32_t dev_id, - a_uint8_t hash_value) -{ - sw_error_t rv = SW_OK; - union ucast_default_hash_u ucast_default_hash; - - memset(&ucast_default_hash, 0, sizeof(ucast_default_hash)); - ADPT_DEV_ID_CHECK(dev_id); - - ucast_default_hash.bf.hash = hash_value; - rv = hppe_ucast_default_hash_set(dev_id, &ucast_default_hash); - - return rv; -} - -sw_error_t -adpt_hppe_ac_queue_group_get( - a_uint32_t dev_id, - a_uint32_t queue_id, - a_uint8_t *group_id) -{ - sw_error_t rv = SW_OK; - - ADPT_DEV_ID_CHECK(dev_id); - ADPT_NULL_POINT_CHECK(group_id); - - - if (queue_id < UCAST_QUEUE_ID_MAX) { - union ac_uni_queue_cfg_tbl_u ac_uni_queue_cfg_tbl; - rv = hppe_ac_uni_queue_cfg_tbl_get(dev_id, - queue_id, - &ac_uni_queue_cfg_tbl); - *group_id = ac_uni_queue_cfg_tbl.bf.ac_cfg_grp_id; - - } else { - union ac_mul_queue_cfg_tbl_u ac_mul_queue_cfg_tbl; - rv = hppe_ac_mul_queue_cfg_tbl_get(dev_id, - queue_id - UCAST_QUEUE_ID_MAX, - &ac_mul_queue_cfg_tbl); - *group_id = ac_mul_queue_cfg_tbl.bf.ac_cfg_grp_id; - } - - return rv; -} - -sw_error_t -adpt_hppe_ac_ctrl_get( - a_uint32_t dev_id, - fal_ac_obj_t *obj, - fal_ac_ctrl_t *cfg) -{ - sw_error_t rv = SW_OK; - ADPT_DEV_ID_CHECK(dev_id); - ADPT_NULL_POINT_CHECK(cfg); - - if (obj->type == FAL_AC_GROUP) { - union ac_grp_cfg_tbl_u ac_grp_cfg_tbl; - - memset(&ac_grp_cfg_tbl, 0, sizeof(ac_grp_cfg_tbl)); - rv = hppe_ac_grp_cfg_tbl_get(dev_id, obj->obj_id, &ac_grp_cfg_tbl); - - cfg->ac_en = ac_grp_cfg_tbl.bf.ac_cfg_ac_en; - cfg->ac_fc_en = ac_grp_cfg_tbl.bf.ac_cfg_force_ac_en; - } else if (obj->type == FAL_AC_QUEUE) { - if (obj->obj_id < UCAST_QUEUE_ID_MAX) { - union ac_uni_queue_cfg_tbl_u ac_uni_queue_cfg_tbl; - rv = hppe_ac_uni_queue_cfg_tbl_get(dev_id, - obj->obj_id, - &ac_uni_queue_cfg_tbl); - cfg->ac_en = ac_uni_queue_cfg_tbl.bf.ac_cfg_ac_en; - cfg->ac_fc_en = ac_uni_queue_cfg_tbl.bf.ac_cfg_force_ac_en; - - } else { - union ac_mul_queue_cfg_tbl_u ac_mul_queue_cfg_tbl; - rv = hppe_ac_mul_queue_cfg_tbl_get(dev_id, - obj->obj_id - UCAST_QUEUE_ID_MAX, - &ac_mul_queue_cfg_tbl); - cfg->ac_en = ac_mul_queue_cfg_tbl.bf.ac_cfg_ac_en; - cfg->ac_fc_en = ac_mul_queue_cfg_tbl.bf.ac_cfg_force_ac_en; - } - } else - return SW_FAIL; - - return rv; -} - -sw_error_t -adpt_hppe_ac_prealloc_buffer_get( - a_uint32_t dev_id, - fal_ac_obj_t *obj, - a_uint16_t *num) -{ - sw_error_t rv = SW_OK; - ADPT_DEV_ID_CHECK(dev_id); - ADPT_NULL_POINT_CHECK(num); - - if (obj->type == FAL_AC_GROUP) { - union ac_grp_cfg_tbl_u ac_grp_cfg_tbl; - - rv = hppe_ac_grp_cfg_tbl_get(dev_id, obj->obj_id, &ac_grp_cfg_tbl); - - *num = ac_grp_cfg_tbl.bf.ac_grp_palloc_limit; - - return rv; - - } else if (obj->type == FAL_AC_QUEUE) { - if (obj->obj_id < UCAST_QUEUE_ID_MAX) { - union ac_uni_queue_cfg_tbl_u ac_uni_queue_cfg_tbl; - rv = hppe_ac_uni_queue_cfg_tbl_get(dev_id, - obj->obj_id, - &ac_uni_queue_cfg_tbl); - *num = ac_uni_queue_cfg_tbl.bf.ac_cfg_pre_alloc_limit; - } else { - union ac_mul_queue_cfg_tbl_u ac_mul_queue_cfg_tbl; - rv = hppe_ac_mul_queue_cfg_tbl_get(dev_id, - obj->obj_id - UCAST_QUEUE_ID_MAX, - &ac_mul_queue_cfg_tbl); - *num = ac_mul_queue_cfg_tbl.bf.ac_cfg_pre_alloc_limit; - } - return rv; - } else - return SW_FAIL; -} - -sw_error_t -adpt_hppe_port_mcast_priority_class_set( - a_uint32_t dev_id, - fal_port_t port, - a_uint8_t priority, - a_uint8_t queue_class) -{ - sw_error_t rv = SW_OK; - union mcast_priority_map0_u mcast_priority_map0; - - ADPT_DEV_ID_CHECK(dev_id); - - mcast_priority_map0.bf.class = queue_class; - - if (port == 0){ - rv = hppe_mcast_priority_map0_set(dev_id, priority, &mcast_priority_map0); - } else if (port == 1) { - rv = hppe_mcast_priority_map1_set(dev_id, priority, - (union mcast_priority_map1_u *)&mcast_priority_map0); - } else if (port == 2) { - rv = hppe_mcast_priority_map2_set(dev_id, priority, - (union mcast_priority_map2_u *)&mcast_priority_map0); - } else if (port == 3) { - rv = hppe_mcast_priority_map3_set(dev_id, priority, - (union mcast_priority_map3_u *)&mcast_priority_map0); - } else if (port == 4) { - rv = hppe_mcast_priority_map4_set(dev_id, priority, - (union mcast_priority_map4_u *)&mcast_priority_map0); - } else if (port == 5) { - rv = hppe_mcast_priority_map5_set(dev_id, priority, - (union mcast_priority_map5_u *)&mcast_priority_map0); - } else if (port == 6) { - rv = hppe_mcast_priority_map6_set(dev_id, priority, - (union mcast_priority_map6_u *)&mcast_priority_map0); - } else if (port == 7) { - rv = hppe_mcast_priority_map7_set(dev_id, priority, - (union mcast_priority_map7_u *)&mcast_priority_map0); - } - - return rv; -} - -sw_error_t -adpt_hppe_ucast_hash_map_get( - a_uint32_t dev_id, - a_uint8_t profile, - a_uint8_t rss_hash, - a_int8_t *queue_hash) -{ - union ucast_hash_map_tbl_u ucast_hash_map_tbl; - sw_error_t rv = SW_OK; - a_uint32_t index = 0; - - memset(&ucast_hash_map_tbl, 0, sizeof(ucast_hash_map_tbl)); - ADPT_DEV_ID_CHECK(dev_id); - - index = profile << 8 | rss_hash; - - rv = hppe_ucast_hash_map_tbl_get(dev_id, index, &ucast_hash_map_tbl); - if (rv) - return rv; - - *queue_hash = ucast_hash_map_tbl.bf.hash; - return rv; -} -#endif - -sw_error_t -adpt_hppe_ac_static_threshold_set( - a_uint32_t dev_id, - fal_ac_obj_t *obj, - fal_ac_static_threshold_t *cfg) -{ - ADPT_DEV_ID_CHECK(dev_id); - - if (obj->type == FAL_AC_GROUP) { - union ac_grp_cfg_tbl_u ac_grp_cfg_tbl; - - hppe_ac_grp_cfg_tbl_get(dev_id, obj->obj_id, &ac_grp_cfg_tbl); - - ac_grp_cfg_tbl.bf.ac_cfg_color_aware = cfg->color_enable; - ac_grp_cfg_tbl.bf.ac_grp_dp_thrd_0 = cfg->green_max; - ac_grp_cfg_tbl.bf.ac_grp_dp_thrd_1 = cfg->green_max >> 7; - ac_grp_cfg_tbl.bf.ac_grp_gap_grn_yel = cfg->yel_max_off; - ac_grp_cfg_tbl.bf.ac_grp_gap_grn_red = cfg->red_max_off; - ac_grp_cfg_tbl.bf.ac_grp_grn_resume_offset = cfg->green_resume_off; - ac_grp_cfg_tbl.bf.ac_grp_yel_resume_offset_0 = cfg->yel_resume_off; - ac_grp_cfg_tbl.bf.ac_grp_yel_resume_offset_1 = cfg->yel_resume_off >> 6; - ac_grp_cfg_tbl.bf.ac_grp_red_resume_offset = cfg->red_resume_off; - - return hppe_ac_grp_cfg_tbl_set(dev_id, obj->obj_id, &ac_grp_cfg_tbl); - - } else if (obj->type == FAL_AC_QUEUE) { - if (obj->obj_id < UCAST_QUEUE_ID_MAX) { - union ac_uni_queue_cfg_tbl_u ac_uni_queue_cfg_tbl; - hppe_ac_uni_queue_cfg_tbl_get(dev_id, - obj->obj_id, - &ac_uni_queue_cfg_tbl); - ac_uni_queue_cfg_tbl.bf.ac_cfg_wred_en = cfg->wred_enable; - ac_uni_queue_cfg_tbl.bf.ac_cfg_color_aware = cfg->color_enable; - ac_uni_queue_cfg_tbl.bf.ac_cfg_shared_dynamic = 0; - ac_uni_queue_cfg_tbl.bf.ac_cfg_gap_grn_grn_min = cfg->green_min_off; - ac_uni_queue_cfg_tbl.bf.ac_cfg_gap_grn_yel_max = cfg->yel_max_off; - ac_uni_queue_cfg_tbl.bf.ac_cfg_gap_grn_yel_min_0 = cfg->yel_min_off; - ac_uni_queue_cfg_tbl.bf.ac_cfg_gap_grn_yel_min_1 = cfg->yel_min_off >> 10; - ac_uni_queue_cfg_tbl.bf.ac_cfg_gap_grn_red_max = cfg->red_max_off; - ac_uni_queue_cfg_tbl.bf.ac_cfg_gap_grn_red_min = cfg->red_min_off; - ac_uni_queue_cfg_tbl.bf.ac_cfg_grn_resume_offset = cfg->green_resume_off; - ac_uni_queue_cfg_tbl.bf.ac_cfg_yel_resume_offset = cfg->yel_resume_off; - ac_uni_queue_cfg_tbl.bf.ac_cfg_red_resume_offset_0 = cfg->red_resume_off; - ac_uni_queue_cfg_tbl.bf.ac_cfg_red_resume_offset_1 = cfg->red_resume_off >> 9; - ac_uni_queue_cfg_tbl.bf.ac_cfg_shared_ceiling = cfg->green_max; - return hppe_ac_uni_queue_cfg_tbl_set(dev_id, - obj->obj_id, - &ac_uni_queue_cfg_tbl);; - - } else { - union ac_mul_queue_cfg_tbl_u ac_mul_queue_cfg_tbl; - hppe_ac_mul_queue_cfg_tbl_get(dev_id, - obj->obj_id - UCAST_QUEUE_ID_MAX, - &ac_mul_queue_cfg_tbl); - ac_mul_queue_cfg_tbl.bf.ac_cfg_color_aware = cfg->color_enable; - ac_mul_queue_cfg_tbl.bf.ac_cfg_grn_resume_offset = cfg->green_resume_off; - ac_mul_queue_cfg_tbl.bf.ac_cfg_yel_resume_offset_0 = cfg->yel_resume_off; - ac_mul_queue_cfg_tbl.bf.ac_cfg_yel_resume_offset_1 = cfg->yel_resume_off >> 4; - ac_mul_queue_cfg_tbl.bf.ac_cfg_red_resume_offset = cfg->red_resume_off; - ac_mul_queue_cfg_tbl.bf.ac_cfg_gap_grn_red = cfg->red_max_off; - ac_mul_queue_cfg_tbl.bf.ac_cfg_gap_grn_yel_0 = cfg->yel_max_off; - ac_mul_queue_cfg_tbl.bf.ac_cfg_gap_grn_yel_1 = cfg->yel_max_off >> 5; - ac_mul_queue_cfg_tbl.bf.ac_cfg_shared_ceiling = cfg->green_max; - return hppe_ac_mul_queue_cfg_tbl_set(dev_id, - obj->obj_id -UCAST_QUEUE_ID_MAX, - &ac_mul_queue_cfg_tbl); - } - } else - return SW_FAIL; -} - -sw_error_t -adpt_hppe_ac_queue_group_set( - a_uint32_t dev_id, - a_uint32_t queue_id, - a_uint8_t group_id) -{ - sw_error_t rv = SW_OK; - - ADPT_DEV_ID_CHECK(dev_id); - - - if (queue_id < UCAST_QUEUE_ID_MAX) { - union ac_uni_queue_cfg_tbl_u ac_uni_queue_cfg_tbl; - hppe_ac_uni_queue_cfg_tbl_get(dev_id, - queue_id, - &ac_uni_queue_cfg_tbl); - ac_uni_queue_cfg_tbl.bf.ac_cfg_grp_id = group_id; - return hppe_ac_uni_queue_cfg_tbl_set(dev_id, - queue_id, - &ac_uni_queue_cfg_tbl); - - } else { - union ac_mul_queue_cfg_tbl_u ac_mul_queue_cfg_tbl; - hppe_ac_mul_queue_cfg_tbl_get(dev_id, - queue_id - UCAST_QUEUE_ID_MAX, - &ac_mul_queue_cfg_tbl); - ac_mul_queue_cfg_tbl.bf.ac_cfg_grp_id = group_id; - return hppe_ac_mul_queue_cfg_tbl_set(dev_id, - queue_id - UCAST_QUEUE_ID_MAX, - &ac_mul_queue_cfg_tbl); - } - - return rv; -} - -#ifndef IN_QM_MINI -sw_error_t -adpt_hppe_ac_group_buffer_get( - a_uint32_t dev_id, - a_uint8_t group_id, - fal_ac_group_buffer_t *cfg) -{ - sw_error_t rv = SW_OK; - union ac_grp_cfg_tbl_u ac_grp_cfg_tbl; - - memset(&ac_grp_cfg_tbl, 0, sizeof(ac_grp_cfg_tbl)); - ADPT_DEV_ID_CHECK(dev_id); - ADPT_NULL_POINT_CHECK(cfg); - - rv = hppe_ac_grp_cfg_tbl_get(dev_id, group_id, &ac_grp_cfg_tbl); - if( rv != SW_OK ) - return rv; - - cfg->prealloc_buffer = ac_grp_cfg_tbl.bf.ac_grp_palloc_limit; - cfg->total_buffer = ac_grp_cfg_tbl.bf.ac_grp_limit; - - return SW_OK; -} - -sw_error_t -adpt_hppe_mcast_cpu_code_class_get( - a_uint32_t dev_id, - a_uint8_t cpu_code, - a_uint8_t *queue_class) -{ - sw_error_t rv = SW_OK; - union mcast_queue_map_tbl_u mcast_queue_map_tbl; - - memset(&mcast_queue_map_tbl, 0, sizeof(mcast_queue_map_tbl)); - ADPT_DEV_ID_CHECK(dev_id); - ADPT_NULL_POINT_CHECK(queue_class); - - rv = hppe_mcast_queue_map_tbl_get(dev_id, cpu_code, &mcast_queue_map_tbl); - if( rv != SW_OK ) - return rv; - - *queue_class = mcast_queue_map_tbl.bf.class; - - return SW_OK; -} -#endif - -sw_error_t -adpt_hppe_ac_ctrl_set( - a_uint32_t dev_id, - fal_ac_obj_t *obj, - fal_ac_ctrl_t *cfg) -{ - ADPT_DEV_ID_CHECK(dev_id); - ADPT_NULL_POINT_CHECK(cfg); - - if (obj->type == FAL_AC_GROUP) { - union ac_grp_cfg_tbl_u ac_grp_cfg_tbl; - - memset(&ac_grp_cfg_tbl, 0, sizeof(ac_grp_cfg_tbl)); - hppe_ac_grp_cfg_tbl_get(dev_id, obj->obj_id, &ac_grp_cfg_tbl); - - ac_grp_cfg_tbl.bf.ac_cfg_ac_en = cfg->ac_en; - ac_grp_cfg_tbl.bf.ac_cfg_force_ac_en = cfg->ac_fc_en; - return hppe_ac_grp_cfg_tbl_set(dev_id, obj->obj_id, &ac_grp_cfg_tbl); - } else if (obj->type == FAL_AC_QUEUE) { - if (obj->obj_id < UCAST_QUEUE_ID_MAX) { - union ac_uni_queue_cfg_tbl_u ac_uni_queue_cfg_tbl; - hppe_ac_uni_queue_cfg_tbl_get(dev_id, - obj->obj_id, - &ac_uni_queue_cfg_tbl); - ac_uni_queue_cfg_tbl.bf.ac_cfg_ac_en = cfg->ac_en; - ac_uni_queue_cfg_tbl.bf.ac_cfg_force_ac_en = cfg->ac_fc_en; - return hppe_ac_uni_queue_cfg_tbl_set(dev_id, - obj->obj_id, - &ac_uni_queue_cfg_tbl); - - } else { - union ac_mul_queue_cfg_tbl_u ac_mul_queue_cfg_tbl; - hppe_ac_mul_queue_cfg_tbl_get(dev_id, - obj->obj_id - UCAST_QUEUE_ID_MAX, - &ac_mul_queue_cfg_tbl); - ac_mul_queue_cfg_tbl.bf.ac_cfg_ac_en = cfg->ac_en; - ac_mul_queue_cfg_tbl.bf.ac_cfg_force_ac_en = cfg->ac_fc_en; - return hppe_ac_mul_queue_cfg_tbl_set(dev_id, - obj->obj_id - UCAST_QUEUE_ID_MAX, - &ac_mul_queue_cfg_tbl); - } - } else - return SW_FAIL; - -} - -#ifndef IN_QM_MINI -sw_error_t -adpt_hppe_ucast_priority_class_get( - a_uint32_t dev_id, - a_uint8_t profile, - a_uint8_t priority, - a_uint8_t *class) -{ - sw_error_t rv = SW_OK; - union ucast_priority_map_tbl_u ucast_priority_map_tbl; - a_uint32_t index = 0; - - memset(&ucast_priority_map_tbl, 0, sizeof(ucast_priority_map_tbl)); - ADPT_DEV_ID_CHECK(dev_id); - ADPT_NULL_POINT_CHECK(class); - - index = profile << 4 | priority; - rv = hppe_ucast_priority_map_tbl_get(dev_id, index, &ucast_priority_map_tbl); - - if( rv != SW_OK ) - return rv; - - *class = ucast_priority_map_tbl.bf.class; - return rv; -} -#endif - -sw_error_t -adpt_hppe_queue_flush( - a_uint32_t dev_id, - fal_port_t port, - a_uint16_t queue_id) -{ - union flush_cfg_u flush_cfg; - a_uint32_t i = 0x100; - sw_error_t rv; - - memset(&flush_cfg, 0, sizeof(flush_cfg)); - ADPT_DEV_ID_CHECK(dev_id); - - #if 0 - /* disable queue firstly */ - if (queue_id == 0xffff) { - /* all queue in this port */ - a_uint32_t i, j, k, tmp; - enq.bf.enq_disable = 1; - deq.bf.deq_dis = 1; - p_api = adpt_api_ptr_get(0); - if (!p_api || !p_api->adpt_port_queues_get) - return SW_FAIL; - p_api->adpt_port_queues_get(dev_id, port, &queue_bmp); - for (i = 0; i < ALL_QUEUE_ID_MAX; i++) { - j = i / 32; - k = i % 32; - tmp = queue_bmp.bmp[j]; - if ((tmp & (1 << k)) == 0) - continue; - hppe_oq_enq_opr_tbl_set(dev_id, i, &enq); - hppe_deq_dis_tbl_set(dev_id, i, &deq); - } - } else { - /* single queue in this port */ - enq.bf.enq_disable = 1; - deq.bf.deq_dis = 1; - if (queue_id >= ALL_QUEUE_ID_MAX) - return SW_BAD_VALUE; - hppe_oq_enq_opr_tbl_set(dev_id, queue_id, &enq); - hppe_deq_dis_tbl_set(dev_id, queue_id, &deq); - } - #endif - - hppe_flush_cfg_get(dev_id, &flush_cfg); - - if (queue_id == 0xffff) { - flush_cfg.bf.flush_all_queues = 1; - flush_cfg.bf.flush_qid = 0; - i = 0x1000; - } - else { - flush_cfg.bf.flush_all_queues = 0; - flush_cfg.bf.flush_qid = queue_id; - } - flush_cfg.bf.flush_dst_port = port; - flush_cfg.bf.flush_busy = 1; - - hppe_flush_cfg_set(dev_id, &flush_cfg); - rv = hppe_flush_cfg_get(dev_id, &flush_cfg); - if (SW_OK != rv) - return rv; - while (flush_cfg.bf.flush_busy && --i) { - hppe_flush_cfg_get(dev_id, &flush_cfg); - } - if (i == 0) - return SW_BUSY; - if (!flush_cfg.bf.flush_status) - return SW_FAIL; - - #if 0 - /* enable queue again */ - if (queue_id == 0xffff) { - /* all queue in this port */ - a_uint32_t i, j, k, tmp; - enq.bf.enq_disable = 0; - deq.bf.deq_dis = 0; - for (i = 0; i < ALL_QUEUE_ID_MAX; i++) { - j = i / 32; - k = i % 32; - tmp = queue_bmp.bmp[j]; - if ((tmp & (1 << k)) == 0) - continue; - hppe_oq_enq_opr_tbl_set(dev_id, i, &enq); - hppe_deq_dis_tbl_set(dev_id, i, &deq); - } - } else { - /* single queue in this port */ - enq.bf.enq_disable = 0; - deq.bf.deq_dis = 0; - hppe_oq_enq_opr_tbl_set(dev_id, queue_id, &enq); - hppe_deq_dis_tbl_set(dev_id, queue_id, &deq); - } - #endif - return SW_OK; -} - -#ifndef IN_QM_MINI -sw_error_t -adpt_hppe_mcast_cpu_code_class_set( - a_uint32_t dev_id, - a_uint8_t cpu_code, - a_uint8_t queue_class) -{ - union mcast_queue_map_tbl_u mcast_queue_map_tbl; - - memset(&mcast_queue_map_tbl, 0, sizeof(mcast_queue_map_tbl)); - ADPT_DEV_ID_CHECK(dev_id); - - mcast_queue_map_tbl.bf.class = queue_class; - return hppe_mcast_queue_map_tbl_set(dev_id, cpu_code, &mcast_queue_map_tbl); -} - -sw_error_t -adpt_hppe_ucast_priority_class_set( - a_uint32_t dev_id, - a_uint8_t profile, - a_uint8_t priority, - a_uint8_t class) -{ - union ucast_priority_map_tbl_u ucast_priority_map_tbl; - a_int32_t index = 0; - - memset(&ucast_priority_map_tbl, 0, sizeof(ucast_priority_map_tbl)); - ADPT_DEV_ID_CHECK(dev_id); - - index = profile << 4 | priority; - ucast_priority_map_tbl.bf.class = class; - - return hppe_ucast_priority_map_tbl_set(dev_id, index, &ucast_priority_map_tbl); -} - -sw_error_t -adpt_hppe_ac_static_threshold_get( - a_uint32_t dev_id, - fal_ac_obj_t *obj, - fal_ac_static_threshold_t *cfg) -{ - sw_error_t rv; - ADPT_DEV_ID_CHECK(dev_id); - - if (obj->type == FAL_AC_GROUP) { - union ac_grp_cfg_tbl_u ac_grp_cfg_tbl; - - rv = hppe_ac_grp_cfg_tbl_get(dev_id, obj->obj_id, &ac_grp_cfg_tbl); - - cfg->color_enable = ac_grp_cfg_tbl.bf.ac_cfg_color_aware; - cfg->green_max = ac_grp_cfg_tbl.bf.ac_grp_dp_thrd_0 | - ac_grp_cfg_tbl.bf.ac_grp_dp_thrd_1 << 7; - cfg->yel_max_off = ac_grp_cfg_tbl.bf.ac_grp_gap_grn_yel; - cfg->red_max_off = ac_grp_cfg_tbl.bf.ac_grp_gap_grn_red; - cfg->green_resume_off = ac_grp_cfg_tbl.bf.ac_grp_grn_resume_offset; - cfg->yel_resume_off = ac_grp_cfg_tbl.bf.ac_grp_yel_resume_offset_0 | - ac_grp_cfg_tbl.bf.ac_grp_yel_resume_offset_1 << 6; - cfg->red_resume_off = ac_grp_cfg_tbl.bf.ac_grp_red_resume_offset; - - return rv; - - } else if (obj->type == FAL_AC_QUEUE) { - if (obj->obj_id < UCAST_QUEUE_ID_MAX) { - union ac_uni_queue_cfg_tbl_u ac_uni_queue_cfg_tbl; - rv = hppe_ac_uni_queue_cfg_tbl_get(dev_id, - obj->obj_id, - &ac_uni_queue_cfg_tbl); - cfg->wred_enable = ac_uni_queue_cfg_tbl.bf.ac_cfg_wred_en; - cfg->color_enable = ac_uni_queue_cfg_tbl.bf.ac_cfg_color_aware; - cfg->green_min_off = ac_uni_queue_cfg_tbl.bf.ac_cfg_gap_grn_grn_min; - cfg->yel_max_off = ac_uni_queue_cfg_tbl.bf.ac_cfg_gap_grn_yel_max; - cfg->yel_min_off = ac_uni_queue_cfg_tbl.bf.ac_cfg_gap_grn_yel_min_0 | - ac_uni_queue_cfg_tbl.bf.ac_cfg_gap_grn_yel_min_1 << 10; - cfg->red_max_off = ac_uni_queue_cfg_tbl.bf.ac_cfg_gap_grn_red_max; - cfg->red_min_off = ac_uni_queue_cfg_tbl.bf.ac_cfg_gap_grn_red_min; - cfg->green_resume_off = ac_uni_queue_cfg_tbl.bf.ac_cfg_grn_resume_offset; - cfg->yel_resume_off = ac_uni_queue_cfg_tbl.bf.ac_cfg_yel_resume_offset; - cfg->red_resume_off = ac_uni_queue_cfg_tbl.bf.ac_cfg_red_resume_offset_0 | - ac_uni_queue_cfg_tbl.bf.ac_cfg_red_resume_offset_1 << 9; - cfg->green_max = ac_uni_queue_cfg_tbl.bf.ac_cfg_shared_ceiling; - return rv; - - } else { - union ac_mul_queue_cfg_tbl_u ac_mul_queue_cfg_tbl; - rv = hppe_ac_mul_queue_cfg_tbl_get(dev_id, - obj->obj_id - UCAST_QUEUE_ID_MAX, - &ac_mul_queue_cfg_tbl); - cfg->color_enable = ac_mul_queue_cfg_tbl.bf.ac_cfg_color_aware; - cfg->green_max = ac_mul_queue_cfg_tbl.bf.ac_cfg_shared_ceiling; - cfg->red_max_off = ac_mul_queue_cfg_tbl.bf.ac_cfg_gap_grn_red; - cfg->yel_max_off= ac_mul_queue_cfg_tbl.bf.ac_cfg_gap_grn_yel_0 | - ac_mul_queue_cfg_tbl.bf.ac_cfg_gap_grn_yel_1 << 5; - cfg->green_resume_off = ac_mul_queue_cfg_tbl.bf.ac_cfg_grn_resume_offset; - cfg->yel_resume_off = ac_mul_queue_cfg_tbl.bf.ac_cfg_yel_resume_offset_0 | - ac_mul_queue_cfg_tbl.bf.ac_cfg_yel_resume_offset_1 << 4; - cfg->red_resume_off = ac_mul_queue_cfg_tbl.bf.ac_cfg_red_resume_offset; - - return rv; - } - } else - return SW_FAIL; -} -#endif - -sw_error_t -adpt_hppe_ucast_queue_base_profile_set( - a_uint32_t dev_id, - fal_ucast_queue_dest_t *queue_dest, - a_uint32_t queue_base, a_uint8_t profile) -{ - union ucast_queue_map_tbl_u ucast_queue_map_tbl; - a_uint32_t index = 0; - - memset(&ucast_queue_map_tbl, 0, sizeof(ucast_queue_map_tbl)); - ADPT_DEV_ID_CHECK(dev_id); - ADPT_NULL_POINT_CHECK(queue_dest); - - if (queue_dest ->service_code_en) { - index = SERVICE_CODE_QUEUE_OFFSET + (queue_dest->src_profile << 8) \ - + queue_dest->service_code; - } else if (queue_dest ->cpu_code_en) { - index = CPU_CODE_QUEUE_OFFSET + (queue_dest->src_profile << 8) \ - + queue_dest->cpu_code; - } else { - index = VP_PORT_QUEUE_OFFSET + (queue_dest->src_profile << 8) \ - + queue_dest->dst_port; - } - - ucast_queue_map_tbl.bf.queue_id = queue_base; - ucast_queue_map_tbl.bf.profile_id = profile; - - return hppe_ucast_queue_map_tbl_set(dev_id, index, &ucast_queue_map_tbl); -} - -sw_error_t -adpt_hppe_ac_group_buffer_set( - a_uint32_t dev_id, - a_uint8_t group_id, - fal_ac_group_buffer_t *cfg) -{ - sw_error_t rv = SW_OK; - union ac_grp_cfg_tbl_u ac_grp_cfg_tbl; - - memset(&ac_grp_cfg_tbl, 0, sizeof(ac_grp_cfg_tbl)); - ADPT_DEV_ID_CHECK(dev_id); - ADPT_NULL_POINT_CHECK(cfg); - - rv = hppe_ac_grp_cfg_tbl_get(dev_id, group_id, &ac_grp_cfg_tbl); - if( rv != SW_OK ) - return rv; - - ac_grp_cfg_tbl.bf.ac_grp_palloc_limit = cfg->prealloc_buffer; - ac_grp_cfg_tbl.bf.ac_grp_limit = cfg->total_buffer; - - return hppe_ac_grp_cfg_tbl_set(dev_id, group_id, &ac_grp_cfg_tbl);; -} - -#ifndef IN_QM_MINI -static a_uint32_t -adpt_hppe_mcast_queue_dropcnt_start_addr_get(a_uint32_t queue_id) -{ - a_uint32_t start_addr = QUEUE_MANAGER_BASE_ADDR; - - if (queue_id >= MCAST_QUEUE_PORT7_START) { - start_addr += MUL_P7_DROP_CNT_TBL_ADDRESS; - start_addr += (queue_id - MCAST_QUEUE_PORT7_START)*MCAST_QUEUE_OFFSET; - } else if (queue_id >= MCAST_QUEUE_PORT6_START) { - start_addr += MUL_P6_DROP_CNT_TBL_ADDRESS; - start_addr += (queue_id - MCAST_QUEUE_PORT6_START)*MCAST_QUEUE_OFFSET; - } else if (queue_id >= MCAST_QUEUE_PORT5_START) { - start_addr += MUL_P5_DROP_CNT_TBL_ADDRESS; - start_addr += (queue_id - MCAST_QUEUE_PORT5_START)*MCAST_QUEUE_OFFSET; - } else if (queue_id >= MCAST_QUEUE_PORT4_START) { - start_addr += MUL_P4_DROP_CNT_TBL_ADDRESS; - start_addr += (queue_id - MCAST_QUEUE_PORT4_START)*MCAST_QUEUE_OFFSET; - } else if (queue_id >= MCAST_QUEUE_PORT3_START) { - start_addr += MUL_P3_DROP_CNT_TBL_ADDRESS; - start_addr += (queue_id - MCAST_QUEUE_PORT3_START)*MCAST_QUEUE_OFFSET; - } else if (queue_id >= MCAST_QUEUE_PORT2_START) { - start_addr += MUL_P2_DROP_CNT_TBL_ADDRESS; - start_addr += (queue_id - MCAST_QUEUE_PORT2_START)*MCAST_QUEUE_OFFSET; - } else if (queue_id >= MCAST_QUEUE_PORT1_START) { - start_addr += MUL_P1_DROP_CNT_TBL_ADDRESS; - start_addr += (queue_id - MCAST_QUEUE_PORT1_START)*MCAST_QUEUE_OFFSET; - } else if (queue_id >= MCAST_QUEUE_PORT0_START) { - start_addr += MUL_P0_DROP_CNT_TBL_ADDRESS; - start_addr += (queue_id - MCAST_QUEUE_PORT0_START)*MCAST_QUEUE_OFFSET; - } - - return start_addr; -} - -sw_error_t -adpt_hppe_queue_counter_cleanup(a_uint32_t dev_id, a_uint32_t queue_id) -{ - union queue_tx_counter_tbl_u tx_cnt; - a_uint32_t i = 0; - a_uint32_t val[3] = {0}; - - ADPT_DEV_ID_CHECK(dev_id); - - if (queue_id >= ALL_QUEUE_ID_MAX) - return SW_BAD_VALUE; - - tx_cnt.bf.tx_packets = 0; - tx_cnt.bf.tx_bytes_0 = 0; - tx_cnt.bf.tx_bytes_1 = 0; - - hppe_queue_tx_counter_tbl_set(dev_id, queue_id, &tx_cnt); - - if (queue_id >= UCAST_QUEUE_ID_MAX) { - a_uint32_t start_addr = 0; - - start_addr = adpt_hppe_mcast_queue_dropcnt_start_addr_get(queue_id); - for (i = 0; i < MCAST_QUEUE_ITEMS; i++) { - hppe_reg_tbl_set(dev_id, start_addr + i*DROP_INC, val, 3); - } - } else { - union uni_drop_cnt_tbl_u uni_drop_cnt; - - memset(&uni_drop_cnt, 0, sizeof(uni_drop_cnt)); - for (i = 0; i < UCAST_QUEUE_ITEMS; i++) { - hppe_uni_drop_cnt_tbl_set(dev_id, queue_id*UCAST_QUEUE_ITEMS+i, &uni_drop_cnt); - } - } - - return SW_OK; -} -sw_error_t -adpt_hppe_queue_counter_get(a_uint32_t dev_id, a_uint32_t queue_id, fal_queue_stats_t *info) -{ - sw_error_t rv = SW_OK; - union queue_tx_counter_tbl_u tx_cnt; - union ac_mul_queue_cnt_tbl_u mul_cnt; - union ac_uni_queue_cnt_tbl_u uni_cnt; - a_uint32_t i = 0; - - ADPT_DEV_ID_CHECK(dev_id); - ADPT_NULL_POINT_CHECK(info); - - if (queue_id >= ALL_QUEUE_ID_MAX) - return SW_BAD_VALUE; - - rv = hppe_queue_tx_counter_tbl_get(dev_id, queue_id, &tx_cnt); - if( rv != SW_OK ) - return rv; - if (queue_id >= UCAST_QUEUE_ID_MAX) { - a_uint32_t start_addr = 0; - union mul_p7_drop_cnt_tbl_u drop_cnt; - - rv = hppe_ac_mul_queue_cnt_tbl_get(dev_id, - queue_id - UCAST_QUEUE_ID_MAX, &mul_cnt); - if( rv != SW_OK ) - return rv; - info->pending_buff_num = mul_cnt.bf.ac_mul_queue_cnt; - start_addr = adpt_hppe_mcast_queue_dropcnt_start_addr_get(queue_id); - for (i = 0; i < MCAST_QUEUE_ITEMS; i++) { - hppe_reg_tbl_get(dev_id, start_addr + i*DROP_INC, drop_cnt.val, 3); - info->drop_packets[i+3] = drop_cnt.bf.mul_p7_drop_pkt; - info->drop_bytes[i+3] = (a_uint64_t)drop_cnt.bf.mul_p7_drop_byte_0 | - (a_uint64_t)drop_cnt.bf.mul_p7_drop_byte_1 <<32; - } - } else { - union uni_drop_cnt_tbl_u uni_drop_cnt; - - rv = hppe_ac_uni_queue_cnt_tbl_get(dev_id, queue_id, &uni_cnt); - if( rv != SW_OK ) - return rv; - info->pending_buff_num = uni_cnt.bf.ac_uni_queue_cnt; - for (i = 0; i < UCAST_QUEUE_ITEMS; i++) { - hppe_uni_drop_cnt_tbl_get(dev_id, queue_id*UCAST_QUEUE_ITEMS+i, &uni_drop_cnt); - info->drop_packets[i] = uni_drop_cnt.bf.uni_drop_pkt; - info->drop_bytes[i] = (a_uint64_t)uni_drop_cnt.bf.uni_drop_byte_0 | - (a_uint64_t)uni_drop_cnt.bf.uni_drop_byte_1 <<32; - } - } - info->tx_packets = tx_cnt.bf.tx_packets; - info->tx_bytes = (a_uint64_t)tx_cnt.bf.tx_bytes_0 | (a_uint64_t)tx_cnt.bf.tx_bytes_1 << 32; - - return SW_OK; -} - -sw_error_t -adpt_hppe_queue_counter_ctrl_get(a_uint32_t dev_id, a_bool_t *cnt_en) -{ - sw_error_t rv = SW_OK; - union eg_bridge_config_u eg_bridge_config; - - memset(&eg_bridge_config, 0, sizeof(eg_bridge_config)); - ADPT_DEV_ID_CHECK(dev_id); - ADPT_NULL_POINT_CHECK(cnt_en); - - rv = hppe_eg_bridge_config_get(dev_id, &eg_bridge_config); - if( rv != SW_OK ) - return rv; - - *cnt_en = eg_bridge_config.bf.queue_cnt_en; - - return SW_OK; -} - -sw_error_t -adpt_hppe_queue_counter_ctrl_set(a_uint32_t dev_id, a_bool_t cnt_en) -{ - sw_error_t rv = SW_OK; - union eg_bridge_config_u eg_bridge_config; - - memset(&eg_bridge_config, 0, sizeof(eg_bridge_config)); - ADPT_DEV_ID_CHECK(dev_id); - - - rv = hppe_eg_bridge_config_get(dev_id, &eg_bridge_config); - if( rv != SW_OK ) - return rv; - - eg_bridge_config.bf.queue_cnt_en = cnt_en; - return hppe_eg_bridge_config_set(dev_id, &eg_bridge_config); -} -#endif - -sw_error_t -adpt_hppe_qm_enqueue_ctrl_set( - a_uint32_t dev_id, - a_uint32_t queue_id, - a_bool_t enable) -{ - union oq_enq_opr_tbl_u enq; - - ADPT_DEV_ID_CHECK(dev_id); - memset(&enq, 0, sizeof(enq)); - - enq.bf.enq_disable = !enable; - return hppe_oq_enq_opr_tbl_set(dev_id, queue_id, &enq); -} - -#ifndef IN_QM_MINI -sw_error_t -adpt_hppe_qm_enqueue_ctrl_get( - a_uint32_t dev_id, - a_uint32_t queue_id, - a_bool_t *enable) -{ - sw_error_t rv = SW_OK; - union oq_enq_opr_tbl_u enq; - - ADPT_DEV_ID_CHECK(dev_id); - memset(&enq, 0, sizeof(enq)); - - rv = hppe_oq_enq_opr_tbl_get(dev_id, queue_id, &enq); - if( rv != SW_OK ) - return rv; - - *enable = !(enq.bf.enq_disable); - - return SW_OK; -} - -static sw_error_t -adpt_hppe_qm_port_source_profile_set( - a_uint32_t dev_id, fal_port_t port, a_uint32_t src_profile) -{ - union mru_mtu_ctrl_tbl_u mru_mtu_ctrl_tbl; - a_uint32_t index = FAL_PORT_ID_VALUE(port); - - ADPT_DEV_ID_CHECK(dev_id); - memset(&mru_mtu_ctrl_tbl, 0, sizeof(mru_mtu_ctrl_tbl)); - - - return hppe_mru_mtu_ctrl_tbl_src_profile_set(dev_id, index, - src_profile); -} - -sw_error_t -adpt_ppe_qm_port_source_profile_set( - a_uint32_t dev_id, fal_port_t port, a_uint32_t src_profile) -{ - a_uint32_t chip_ver = 0; - - chip_ver = adpt_hppe_chip_revision_get(dev_id); - if (chip_ver == CPPE_REVISION) { -#if defined(CPPE) - return adpt_cppe_qm_port_source_profile_set(dev_id, port, - src_profile); -#endif - } else { - return adpt_hppe_qm_port_source_profile_set(dev_id, port, - src_profile); - } - - return SW_NOT_SUPPORTED; -} - -static sw_error_t -adpt_hppe_qm_port_source_profile_get( - a_uint32_t dev_id, fal_port_t port, a_uint32_t *src_profile) -{ - union mru_mtu_ctrl_tbl_u mru_mtu_ctrl_tbl; - a_uint32_t index = FAL_PORT_ID_VALUE(port); - - ADPT_DEV_ID_CHECK(dev_id); - ADPT_NULL_POINT_CHECK(src_profile); - memset(&mru_mtu_ctrl_tbl, 0, sizeof(mru_mtu_ctrl_tbl)); - - return hppe_mru_mtu_ctrl_tbl_src_profile_get(dev_id, index, - src_profile); -} - -sw_error_t -adpt_ppe_qm_port_source_profile_get( - a_uint32_t dev_id, fal_port_t port, a_uint32_t *src_profile) -{ - a_uint32_t chip_ver = 0; - - chip_ver = adpt_hppe_chip_revision_get(dev_id); - if (chip_ver == CPPE_REVISION) { -#if defined(CPPE) - return adpt_cppe_qm_port_source_profile_get(dev_id, port, - src_profile); -#endif - } else { - return adpt_hppe_qm_port_source_profile_get(dev_id, port, - src_profile); - } - - return SW_NOT_SUPPORTED; -} -#endif - -void adpt_hppe_qm_func_bitmap_init(a_uint32_t dev_id) -{ - adpt_api_t *p_adpt_api = NULL; - - p_adpt_api = adpt_api_ptr_get(dev_id); - - if(p_adpt_api == NULL) - return; - - p_adpt_api->adpt_qm_func_bitmap[0] = ((1 << FUNC_UCAST_HASH_MAP_SET) | - (1 << FUNC_AC_DYNAMIC_THRESHOLD_GET) | - (1 << FUNC_UCAST_QUEUE_BASE_PROFILE_GET) | - (1 << FUNC_PORT_MCAST_PRIORITY_CLASS_GET) | - (1 << FUNC_AC_DYNAMIC_THRESHOLD_SET) | - (1 << FUNC_AC_PREALLOC_BUFFER_SET) | - (1 << FUNC_UCAST_DEFAULT_HASH_GET) | - (1 << FUNC_UCAST_DEFAULT_HASH_SET) | - (1 << FUNC_AC_QUEUE_GROUP_GET) | - (1 << FUNC_AC_CTRL_GET) | - (1 << FUNC_AC_PREALLOC_BUFFER_GET) | - (1 << FUNC_PORT_MCAST_PRIORITY_CLASS_SET) | - (1 << FUNC_UCAST_HASH_MAP_GET) | - (1 << FUNC_AC_STATIC_THRESHOLD_SET) | - (1 << FUNC_AC_QUEUE_GROUP_SET) | - (1 << FUNC_AC_GROUP_BUFFER_GET) | - (1 << FUNC_MCAST_CPU_CODE_CLASS_GET) | - (1 << FUNC_AC_CTRL_SET) | - (1 << FUNC_UCAST_PRIORITY_CLASS_GET) | - (1 << FUNC_QUEUE_FLUSH) | - (1 << FUNC_MCAST_CPU_CODE_CLASS_SET) | - (1 << FUNC_UCAST_PRIORITY_CLASS_SET) | - (1 << FUNC_AC_STATIC_THRESHOLD_GET) | - (1 << FUNC_UCAST_QUEUE_BASE_PROFILE_SET) | - (1 << FUNC_AC_GROUP_BUFFER_SET) | - (1 << FUNC_QUEUE_COUNTER_CLEANUP) | - (1 << FUNC_QUEUE_COUNTER_GET) | - (1 << FUNC_QUEUE_COUNTER_CTRL_GET) | - (1 << FUNC_QUEUE_COUNTER_CTRL_SET) | - (1 << FUNC_QM_ENQUEUE_CTRL_GET) | - (1 << FUNC_QM_ENQUEUE_CTRL_SET) | - (1 << FUNC_QM_PORT_SRCPROFILE_GET)); - p_adpt_api->adpt_qm_func_bitmap[1] = 1 << (FUNC_QM_PORT_SRCPROFILE_SET % 32); - return; -} - -static void adpt_hppe_qm_func_unregister(a_uint32_t dev_id, adpt_api_t *p_adpt_api) -{ - if(p_adpt_api == NULL) - return; - - p_adpt_api->adpt_ucast_hash_map_set = NULL; - p_adpt_api->adpt_ac_dynamic_threshold_get = NULL; - p_adpt_api->adpt_ucast_queue_base_profile_get = NULL; - p_adpt_api->adpt_port_mcast_priority_class_get = NULL; - p_adpt_api->adpt_ac_dynamic_threshold_set = NULL; - p_adpt_api->adpt_ac_prealloc_buffer_set = NULL; - p_adpt_api->adpt_ucast_default_hash_get = NULL; - p_adpt_api->adpt_ucast_default_hash_set = NULL; - p_adpt_api->adpt_ac_queue_group_get = NULL; - p_adpt_api->adpt_ac_ctrl_get = NULL; - p_adpt_api->adpt_ac_prealloc_buffer_get = NULL; - p_adpt_api->adpt_port_mcast_priority_class_set = NULL; - p_adpt_api->adpt_ucast_hash_map_get = NULL; - p_adpt_api->adpt_ac_static_threshold_set = NULL; - p_adpt_api->adpt_ac_queue_group_set = NULL; - p_adpt_api->adpt_ac_group_buffer_get = NULL; - p_adpt_api->adpt_mcast_cpu_code_class_get = NULL; - p_adpt_api->adpt_ac_ctrl_set = NULL; - p_adpt_api->adpt_ucast_priority_class_get = NULL; - p_adpt_api->adpt_queue_flush = NULL; - p_adpt_api->adpt_mcast_cpu_code_class_set = NULL; - p_adpt_api->adpt_ucast_priority_class_set = NULL; - p_adpt_api->adpt_ac_static_threshold_get = NULL; - p_adpt_api->adpt_ucast_queue_base_profile_set = NULL; - p_adpt_api->adpt_ac_group_buffer_set = NULL; - p_adpt_api->adpt_queue_counter_cleanup = NULL; - p_adpt_api->adpt_queue_counter_get = NULL; - p_adpt_api->adpt_queue_counter_ctrl_get = NULL; - p_adpt_api->adpt_queue_counter_ctrl_set = NULL; - p_adpt_api->adpt_qm_enqueue_ctrl_set = NULL; - p_adpt_api->adpt_qm_enqueue_ctrl_get = NULL; - p_adpt_api->adpt_qm_port_source_profile_get = NULL; - p_adpt_api->adpt_qm_port_source_profile_set = NULL; - - return; -} - -sw_error_t adpt_hppe_qm_init(a_uint32_t dev_id) -{ - adpt_api_t *p_adpt_api = NULL; - - p_adpt_api = adpt_api_ptr_get(dev_id); - - if(p_adpt_api == NULL) - return SW_FAIL; - - adpt_hppe_qm_func_unregister(dev_id, p_adpt_api); - - if (p_adpt_api->adpt_qm_func_bitmap[0] & (1 << FUNC_AC_CTRL_SET)) - p_adpt_api->adpt_ac_ctrl_set = adpt_hppe_ac_ctrl_set; - if (p_adpt_api->adpt_qm_func_bitmap[0] & (1 << FUNC_AC_PREALLOC_BUFFER_SET)) - p_adpt_api->adpt_ac_prealloc_buffer_set = adpt_hppe_ac_prealloc_buffer_set; - if (p_adpt_api->adpt_qm_func_bitmap[0] & (1 << FUNC_AC_QUEUE_GROUP_SET)) - p_adpt_api->adpt_ac_queue_group_set = adpt_hppe_ac_queue_group_set; - if (p_adpt_api->adpt_qm_func_bitmap[0] & (1 << FUNC_AC_STATIC_THRESHOLD_SET)) - p_adpt_api->adpt_ac_static_threshold_set = adpt_hppe_ac_static_threshold_set; - if (p_adpt_api->adpt_qm_func_bitmap[0] & (1 << FUNC_AC_DYNAMIC_THRESHOLD_SET)) - p_adpt_api->adpt_ac_dynamic_threshold_set = adpt_hppe_ac_dynamic_threshold_set; - if (p_adpt_api->adpt_qm_func_bitmap[0] & (1 << FUNC_AC_GROUP_BUFFER_SET)) - p_adpt_api->adpt_ac_group_buffer_set = adpt_hppe_ac_group_buffer_set; - if (p_adpt_api->adpt_qm_func_bitmap[0] & (1 << FUNC_UCAST_QUEUE_BASE_PROFILE_SET)) - p_adpt_api->adpt_ucast_queue_base_profile_set = - adpt_hppe_ucast_queue_base_profile_set; - if (p_adpt_api->adpt_qm_func_bitmap[0] & (1 << FUNC_QUEUE_FLUSH)) - p_adpt_api->adpt_queue_flush = adpt_hppe_queue_flush; - if (p_adpt_api->adpt_qm_func_bitmap[0] & (1 << FUNC_QM_ENQUEUE_CTRL_SET)) - p_adpt_api->adpt_qm_enqueue_ctrl_set = adpt_hppe_qm_enqueue_ctrl_set; -#ifndef IN_QM_MINI - if (p_adpt_api->adpt_qm_func_bitmap[0] & (1 << FUNC_UCAST_HASH_MAP_SET)) - p_adpt_api->adpt_ucast_hash_map_set = adpt_hppe_ucast_hash_map_set; - if (p_adpt_api->adpt_qm_func_bitmap[0] & (1 << FUNC_AC_DYNAMIC_THRESHOLD_GET)) - p_adpt_api->adpt_ac_dynamic_threshold_get = adpt_hppe_ac_dynamic_threshold_get; - if (p_adpt_api->adpt_qm_func_bitmap[0] & (1 << FUNC_UCAST_QUEUE_BASE_PROFILE_GET)) - p_adpt_api->adpt_ucast_queue_base_profile_get = - adpt_hppe_ucast_queue_base_profile_get; - if (p_adpt_api->adpt_qm_func_bitmap[0] & (1 << FUNC_PORT_MCAST_PRIORITY_CLASS_GET)) - p_adpt_api->adpt_port_mcast_priority_class_get = - adpt_hppe_port_mcast_priority_class_get; - if (p_adpt_api->adpt_qm_func_bitmap[0] & (1 << FUNC_UCAST_DEFAULT_HASH_GET)) - p_adpt_api->adpt_ucast_default_hash_get = adpt_hppe_ucast_default_hash_get; - if (p_adpt_api->adpt_qm_func_bitmap[0] & (1 << FUNC_UCAST_DEFAULT_HASH_SET)) - p_adpt_api->adpt_ucast_default_hash_set = adpt_hppe_ucast_default_hash_set; - if (p_adpt_api->adpt_qm_func_bitmap[0] & (1 << FUNC_AC_QUEUE_GROUP_GET)) - p_adpt_api->adpt_ac_queue_group_get = adpt_hppe_ac_queue_group_get; - if (p_adpt_api->adpt_qm_func_bitmap[0] & (1 << FUNC_AC_CTRL_GET)) - p_adpt_api->adpt_ac_ctrl_get = adpt_hppe_ac_ctrl_get; - if (p_adpt_api->adpt_qm_func_bitmap[0] & (1 << FUNC_AC_PREALLOC_BUFFER_GET)) - p_adpt_api->adpt_ac_prealloc_buffer_get = adpt_hppe_ac_prealloc_buffer_get; - if (p_adpt_api->adpt_qm_func_bitmap[0] & (1 << FUNC_PORT_MCAST_PRIORITY_CLASS_SET)) - p_adpt_api->adpt_port_mcast_priority_class_set = - adpt_hppe_port_mcast_priority_class_set; - if (p_adpt_api->adpt_qm_func_bitmap[0] & (1 << FUNC_UCAST_HASH_MAP_GET)) - p_adpt_api->adpt_ucast_hash_map_get = adpt_hppe_ucast_hash_map_get; - if (p_adpt_api->adpt_qm_func_bitmap[0] & (1 << FUNC_AC_GROUP_BUFFER_GET)) - p_adpt_api->adpt_ac_group_buffer_get = adpt_hppe_ac_group_buffer_get; - if (p_adpt_api->adpt_qm_func_bitmap[0] & (1 << FUNC_MCAST_CPU_CODE_CLASS_GET)) - p_adpt_api->adpt_mcast_cpu_code_class_get = adpt_hppe_mcast_cpu_code_class_get; - if (p_adpt_api->adpt_qm_func_bitmap[0] & (1 << FUNC_UCAST_PRIORITY_CLASS_GET)) - p_adpt_api->adpt_ucast_priority_class_get = adpt_hppe_ucast_priority_class_get; - if (p_adpt_api->adpt_qm_func_bitmap[0] & (1 << FUNC_MCAST_CPU_CODE_CLASS_SET)) - p_adpt_api->adpt_mcast_cpu_code_class_set = adpt_hppe_mcast_cpu_code_class_set; - if (p_adpt_api->adpt_qm_func_bitmap[0] & (1 << FUNC_UCAST_PRIORITY_CLASS_SET)) - p_adpt_api->adpt_ucast_priority_class_set = adpt_hppe_ucast_priority_class_set; - if (p_adpt_api->adpt_qm_func_bitmap[0] & (1 << FUNC_AC_STATIC_THRESHOLD_GET)) - p_adpt_api->adpt_ac_static_threshold_get = adpt_hppe_ac_static_threshold_get; - if (p_adpt_api->adpt_qm_func_bitmap[0] & (1 << FUNC_QUEUE_COUNTER_CLEANUP)) - p_adpt_api->adpt_queue_counter_cleanup = adpt_hppe_queue_counter_cleanup; - if (p_adpt_api->adpt_qm_func_bitmap[0] & (1 << FUNC_QUEUE_COUNTER_GET)) - p_adpt_api->adpt_queue_counter_get = adpt_hppe_queue_counter_get; - if (p_adpt_api->adpt_qm_func_bitmap[0] & (1 << FUNC_QUEUE_COUNTER_CTRL_GET)) - p_adpt_api->adpt_queue_counter_ctrl_get = adpt_hppe_queue_counter_ctrl_get; - if (p_adpt_api->adpt_qm_func_bitmap[0] & (1 << FUNC_QUEUE_COUNTER_CTRL_SET)) - p_adpt_api->adpt_queue_counter_ctrl_set = adpt_hppe_queue_counter_ctrl_set; - if (p_adpt_api->adpt_qm_func_bitmap[0] & (1 << FUNC_QM_ENQUEUE_CTRL_GET)) - p_adpt_api->adpt_qm_enqueue_ctrl_get = adpt_hppe_qm_enqueue_ctrl_get; - if (p_adpt_api->adpt_qm_func_bitmap[0] & (1 << FUNC_QM_PORT_SRCPROFILE_GET)) - p_adpt_api->adpt_qm_port_source_profile_get = adpt_ppe_qm_port_source_profile_get; - if (p_adpt_api->adpt_qm_func_bitmap[1] & (1 << (FUNC_QM_PORT_SRCPROFILE_SET % 32))) - p_adpt_api->adpt_qm_port_source_profile_set = adpt_ppe_qm_port_source_profile_set; -#endif - - return SW_OK; -} - -/** - * @} - */ diff --git a/feeds/ipq807x/qca-ssdk/src/src/adpt/hppe/adpt_hppe_qos.c b/feeds/ipq807x/qca-ssdk/src/src/adpt/hppe/adpt_hppe_qos.c deleted file mode 100644 index ca48de653..000000000 --- a/feeds/ipq807x/qca-ssdk/src/src/adpt/hppe/adpt_hppe_qos.c +++ /dev/null @@ -1,1235 +0,0 @@ -/* - * Copyright (c) 2016-2017, The Linux Foundation. All rights reserved. - * Permission to use, copy, modify, and/or distribute this software for - * any purpose with or without fee is hereby granted, provided that the - * above copyright notice and this permission notice appear in all copies. - * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES - * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR - * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES - * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN - * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT - * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. - */ - - -/** - * @defgroup - * @{ - */ -#include "sw.h" -#include "ssdk_dts.h" -#include "fal_qos.h" -#include "hppe_qos_reg.h" -#include "hppe_qos.h" -#include "hppe_shaper_reg.h" -#include "hppe_shaper.h" -#include "adpt.h" -#include "adpt_hppe.h" -#if defined(CPPE) -#include "adpt_cppe_qos.h" -#endif - -static fal_queue_bmp_t port_queue_map[8] = {0}; - -sw_error_t -adpt_hppe_l1_flow_map_get(a_uint32_t dev_id, - a_uint32_t node_id, - fal_port_t *port_id, - fal_qos_scheduler_cfg_t *scheduler_cfg) -{ - union l1_flow_map_tbl_u l1_flow_map_tbl; - union l1_c_sp_cfg_tbl_u l1_c_sp_cfg_tbl; - union l1_e_sp_cfg_tbl_u l1_e_sp_cfg_tbl; - union l1_flow_port_map_tbl_u port_map; - union l1_comp_cfg_tbl_u l1_comp_cfg_tbl; - a_uint32_t c_sp_id, e_sp_id; - - memset(&l1_flow_map_tbl, 0, sizeof(l1_flow_map_tbl)); - ADPT_DEV_ID_CHECK(dev_id); - ADPT_NULL_POINT_CHECK(scheduler_cfg); - if (node_id >= L1_FLOW_MAP_TBL_MAX_ENTRY) - return SW_BAD_PARAM; - - hppe_l1_flow_map_tbl_get(dev_id, node_id, &l1_flow_map_tbl); - scheduler_cfg->e_drr_wt = l1_flow_map_tbl.bf.e_drr_wt; - scheduler_cfg->c_drr_wt = l1_flow_map_tbl.bf.c_drr_wt; - scheduler_cfg->e_pri = l1_flow_map_tbl.bf.e_pri; - scheduler_cfg->c_pri = l1_flow_map_tbl.bf.c_pri; - scheduler_cfg->sp_id = l1_flow_map_tbl.bf.sp_id; - - c_sp_id = scheduler_cfg->sp_id * 8 + scheduler_cfg->c_pri; - hppe_l1_c_sp_cfg_tbl_get(dev_id, c_sp_id, &l1_c_sp_cfg_tbl); - scheduler_cfg->c_drr_unit = l1_c_sp_cfg_tbl.bf.drr_credit_unit; - scheduler_cfg->c_drr_id = l1_c_sp_cfg_tbl.bf.drr_id; - - e_sp_id = scheduler_cfg->sp_id * 8 + scheduler_cfg->e_pri; - hppe_l1_e_sp_cfg_tbl_get(dev_id, e_sp_id, &l1_e_sp_cfg_tbl); - scheduler_cfg->e_drr_unit = l1_e_sp_cfg_tbl.bf.drr_credit_unit; - scheduler_cfg->e_drr_id = l1_e_sp_cfg_tbl.bf.drr_id; - - hppe_l1_flow_port_map_tbl_get(dev_id, node_id, &port_map); - *port_id = port_map.bf.port_num; - - hppe_l1_comp_cfg_tbl_get(dev_id, node_id, &l1_comp_cfg_tbl); - scheduler_cfg->drr_frame_mode = l1_comp_cfg_tbl.bf.drr_meter_len; - - return SW_OK; -} -#ifndef IN_QOS_MINI -sw_error_t -adpt_hppe_qos_port_mode_pri_set(a_uint32_t dev_id, fal_port_t port_id, - fal_qos_mode_t mode, a_uint32_t pri) -{ - union port_qos_ctrl_u port_qos_ctrl; - - memset(&port_qos_ctrl, 0, sizeof(port_qos_ctrl)); - ADPT_DEV_ID_CHECK(dev_id); - - hppe_port_qos_ctrl_get(dev_id, port_id, &port_qos_ctrl); - - if (mode == FAL_QOS_UP_MODE) - port_qos_ctrl.bf.port_pcp_qos_pri = pri; - else if (mode == FAL_QOS_DSCP_MODE) - port_qos_ctrl.bf.port_dscp_qos_pri = pri; - else if (mode == FAL_QOS_FLOW_MODE) - port_qos_ctrl.bf.port_flow_qos_pri = pri; - else - return SW_NOT_SUPPORTED; - - return hppe_port_qos_ctrl_set(dev_id, port_id, &port_qos_ctrl); -} - -sw_error_t -adpt_hppe_qos_port_mode_pri_get(a_uint32_t dev_id, fal_port_t port_id, - fal_qos_mode_t mode, a_uint32_t *pri) -{ - union port_qos_ctrl_u port_qos_ctrl; - - memset(&port_qos_ctrl, 0, sizeof(port_qos_ctrl)); - ADPT_DEV_ID_CHECK(dev_id); - - hppe_port_qos_ctrl_get(dev_id, port_id, &port_qos_ctrl); - - if (mode == FAL_QOS_UP_MODE) - *pri = port_qos_ctrl.bf.port_pcp_qos_pri; - else if (mode == FAL_QOS_DSCP_MODE) - *pri = port_qos_ctrl.bf.port_dscp_qos_pri; - else if (mode == FAL_QOS_FLOW_MODE) - *pri = port_qos_ctrl.bf.port_flow_qos_pri; - else - return SW_NOT_SUPPORTED; - - return SW_OK; -} -#endif - -static sw_error_t -adpt_hppe_qos_port_pri_set(a_uint32_t dev_id, fal_port_t port_id, - fal_qos_pri_precedence_t *pri) -{ - union port_qos_ctrl_u port_qos_ctrl; - - memset(&port_qos_ctrl, 0, sizeof(port_qos_ctrl)); - ADPT_DEV_ID_CHECK(dev_id); - ADPT_NULL_POINT_CHECK(pri); - - hppe_port_qos_ctrl_get(dev_id, port_id, &port_qos_ctrl); - - port_qos_ctrl.bf.port_pcp_qos_pri = pri->pcp_pri; - port_qos_ctrl.bf.port_dscp_qos_pri = pri->dscp_pri; - port_qos_ctrl.bf.port_preheader_qos_pri = pri->preheader_pri; - port_qos_ctrl.bf.port_flow_qos_pri = pri->flow_pri; - port_qos_ctrl.bf.port_acl_qos_pri = pri->acl_pri; - - return hppe_port_qos_ctrl_set(dev_id, port_id, &port_qos_ctrl); -} - -sw_error_t -adpt_ppe_qos_port_pri_set(a_uint32_t dev_id, fal_port_t port_id, - fal_qos_pri_precedence_t *pri) -{ - a_uint32_t chip_ver = 0; - - ADPT_DEV_ID_CHECK(dev_id); - ADPT_NULL_POINT_CHECK(pri); - - chip_ver = adpt_hppe_chip_revision_get(dev_id); - if (chip_ver == CPPE_REVISION) { -#if defined(CPPE) - return adpt_cppe_qos_port_pri_set(dev_id, port_id, pri); -#endif - } else { - return adpt_hppe_qos_port_pri_set(dev_id, port_id, pri); - } - - return SW_NOT_SUPPORTED; -} - -static sw_error_t -adpt_hppe_qos_port_pri_get(a_uint32_t dev_id, fal_port_t port_id, - fal_qos_pri_precedence_t *pri) -{ - sw_error_t rv = SW_OK; - union port_qos_ctrl_u port_qos_ctrl; - - memset(&port_qos_ctrl, 0, sizeof(port_qos_ctrl)); - ADPT_DEV_ID_CHECK(dev_id); - ADPT_NULL_POINT_CHECK(pri); - - rv = hppe_port_qos_ctrl_get(dev_id, port_id, &port_qos_ctrl); - if( rv != SW_OK ) - return rv; - - pri->pcp_pri = port_qos_ctrl.bf.port_pcp_qos_pri; - pri->dscp_pri = port_qos_ctrl.bf.port_dscp_qos_pri; - pri->preheader_pri = port_qos_ctrl.bf.port_preheader_qos_pri; - pri->flow_pri = port_qos_ctrl.bf.port_flow_qos_pri; - pri->acl_pri = port_qos_ctrl.bf.port_acl_qos_pri; - - return SW_OK; -} - -sw_error_t -adpt_ppe_qos_port_pri_get(a_uint32_t dev_id, fal_port_t port_id, - fal_qos_pri_precedence_t *pri) -{ - a_uint32_t chip_ver = 0; - - ADPT_DEV_ID_CHECK(dev_id); - ADPT_NULL_POINT_CHECK(pri); - - chip_ver = adpt_hppe_chip_revision_get(dev_id); - if (chip_ver == CPPE_REVISION) { -#if defined(CPPE) - return adpt_cppe_qos_port_pri_get(dev_id, port_id, pri); -#endif - } else { - return adpt_hppe_qos_port_pri_get(dev_id, port_id, pri); - } - - return SW_NOT_SUPPORTED; -} - -static sw_error_t -adpt_hppe_qos_cosmap_pcp_get(a_uint32_t dev_id, a_uint8_t group_id, - a_uint8_t pcp, fal_qos_cosmap_t *cosmap) -{ - sw_error_t rv = SW_OK; - union pcp_qos_group_0_u pcp_qos_group_0; - union pcp_qos_group_1_u pcp_qos_group_1; - - ADPT_DEV_ID_CHECK(dev_id); - ADPT_NULL_POINT_CHECK(cosmap); - - if (pcp >= PCP_QOS_GROUP_0_MAX_ENTRY) - return SW_BAD_PARAM; - - if (group_id == 0) { - rv = hppe_pcp_qos_group_0_get(dev_id, pcp, &pcp_qos_group_0); - if( rv != SW_OK ) - return rv; - cosmap->internal_pcp = pcp_qos_group_0.bf.qos_info & 7; - cosmap->internal_dei = (pcp_qos_group_0.bf.qos_info >> 3) & 1; - cosmap->internal_pri = (pcp_qos_group_0.bf.qos_info >> 4) & 0xf; - cosmap->internal_dscp = (pcp_qos_group_0.bf.qos_info >> 8) & 0x3f; - cosmap->internal_dp = (pcp_qos_group_0.bf.qos_info >> 14) & 0x3; - } else if (group_id == 1) { - rv = hppe_pcp_qos_group_1_get(dev_id, pcp, &pcp_qos_group_1); - if( rv != SW_OK ) - return rv; - cosmap->internal_pcp = pcp_qos_group_1.bf.qos_info & 7; - cosmap->internal_dei = (pcp_qos_group_1.bf.qos_info >> 3) & 1; - cosmap->internal_pri = (pcp_qos_group_1.bf.qos_info >> 4) & 0xf; - cosmap->internal_dscp = (pcp_qos_group_1.bf.qos_info >> 8) & 0x3f; - cosmap->internal_dp = (pcp_qos_group_1.bf.qos_info >> 14) & 0x3; - } else - return SW_BAD_PARAM; - - return SW_OK; -} - -sw_error_t -adpt_ppe_qos_cosmap_pcp_get(a_uint32_t dev_id, a_uint8_t group_id, - a_uint8_t pcp, fal_qos_cosmap_t *cosmap) -{ - a_uint32_t chip_ver = 0; - - ADPT_DEV_ID_CHECK(dev_id); - ADPT_NULL_POINT_CHECK(cosmap); - - chip_ver = adpt_hppe_chip_revision_get(dev_id); - if (chip_ver == CPPE_REVISION) { -#if defined(CPPE) - return adpt_cppe_qos_cosmap_pcp_get(dev_id, group_id, - pcp, cosmap); -#endif - } else { - return adpt_hppe_qos_cosmap_pcp_get(dev_id, group_id, - pcp, cosmap); - } - - return SW_NOT_SUPPORTED; -} - -sw_error_t -adpt_hppe_l0_queue_map_set(a_uint32_t dev_id, - a_uint32_t node_id, - fal_port_t port_id, - fal_qos_scheduler_cfg_t *scheduler_cfg) -{ - union l0_flow_map_tbl_u l0_flow_map_tbl; - union l0_c_sp_cfg_tbl_u l0_c_sp_cfg_tbl; - union l0_e_sp_cfg_tbl_u l0_e_sp_cfg_tbl; - union l0_flow_port_map_tbl_u l0_flow_port_map_tbl; - union l0_comp_cfg_tbl_u l0_comp_cfg_tbl; - a_uint32_t c_sp_id, e_sp_id; - a_uint32_t i, j, k; - - memset(&l0_flow_map_tbl, 0, sizeof(l0_flow_map_tbl)); - ADPT_DEV_ID_CHECK(dev_id); - ADPT_NULL_POINT_CHECK(scheduler_cfg); - if (node_id >= L0_FLOW_MAP_TBL_MAX_ENTRY) - return SW_BAD_PARAM; - - l0_flow_map_tbl.bf.e_drr_wt= scheduler_cfg->e_drr_wt; - l0_flow_map_tbl.bf.c_drr_wt = scheduler_cfg->c_drr_wt; - l0_flow_map_tbl.bf.e_pri = scheduler_cfg->e_pri; - l0_flow_map_tbl.bf.c_pri = scheduler_cfg->c_pri; - l0_flow_map_tbl.bf.sp_id = scheduler_cfg->sp_id; - hppe_l0_flow_map_tbl_set(dev_id, node_id, &l0_flow_map_tbl); - - c_sp_id = scheduler_cfg->sp_id * 8 + scheduler_cfg->c_pri; - l0_c_sp_cfg_tbl.bf.drr_credit_unit = scheduler_cfg->c_drr_unit; - l0_c_sp_cfg_tbl.bf.drr_id = scheduler_cfg->c_drr_id; - hppe_l0_c_sp_cfg_tbl_set(dev_id, c_sp_id, &l0_c_sp_cfg_tbl); - - e_sp_id = scheduler_cfg->sp_id * 8 + scheduler_cfg->e_pri; - l0_e_sp_cfg_tbl.bf.drr_credit_unit = scheduler_cfg->e_drr_unit; - l0_e_sp_cfg_tbl.bf.drr_id = scheduler_cfg->e_drr_id; - hppe_l0_e_sp_cfg_tbl_set(dev_id, e_sp_id, &l0_e_sp_cfg_tbl); - - l0_flow_port_map_tbl.bf.port_num = port_id; - hppe_l0_flow_port_map_tbl_set(dev_id, node_id, &l0_flow_port_map_tbl); - - hppe_l0_comp_cfg_tbl_get(dev_id, node_id, &l0_comp_cfg_tbl); - l0_comp_cfg_tbl.bf.drr_meter_len = scheduler_cfg->drr_frame_mode; - hppe_l0_comp_cfg_tbl_set(dev_id, node_id, &l0_comp_cfg_tbl); - - i = node_id / 32; - j = node_id % 32; - port_queue_map[port_id].bmp[i] |= 1 << j; - for (k = 0; k < 8; k++) { - if (k != port_id) { - port_queue_map[k].bmp[i] &= ~(1 << j); - } - } - - return SW_OK; -} - -sw_error_t -adpt_hppe_l0_queue_map_get(a_uint32_t dev_id, - a_uint32_t node_id, - fal_port_t *port_id, - fal_qos_scheduler_cfg_t *scheduler_cfg) -{ - union l0_flow_map_tbl_u l0_flow_map_tbl; - union l0_c_sp_cfg_tbl_u l0_c_sp_cfg_tbl; - union l0_e_sp_cfg_tbl_u l0_e_sp_cfg_tbl; - union l0_flow_port_map_tbl_u l0_flow_port_map_tbl; - union l0_comp_cfg_tbl_u l0_comp_cfg_tbl; - a_uint32_t c_sp_id, e_sp_id; - - memset(&l0_flow_map_tbl, 0, sizeof(l0_flow_map_tbl)); - ADPT_DEV_ID_CHECK(dev_id); - ADPT_NULL_POINT_CHECK(scheduler_cfg); - if (node_id >= L0_FLOW_MAP_TBL_MAX_ENTRY) - return SW_BAD_PARAM; - - hppe_l0_flow_map_tbl_get(dev_id, node_id, &l0_flow_map_tbl); - scheduler_cfg->e_drr_wt = l0_flow_map_tbl.bf.e_drr_wt; - scheduler_cfg->c_drr_wt = l0_flow_map_tbl.bf.c_drr_wt; - scheduler_cfg->e_pri = l0_flow_map_tbl.bf.e_pri; - scheduler_cfg->c_pri = l0_flow_map_tbl.bf.c_pri; - scheduler_cfg->sp_id = l0_flow_map_tbl.bf.sp_id; - - c_sp_id = scheduler_cfg->sp_id * 8 + scheduler_cfg->c_pri; - hppe_l0_c_sp_cfg_tbl_get(dev_id, c_sp_id, &l0_c_sp_cfg_tbl); - scheduler_cfg->c_drr_unit = l0_c_sp_cfg_tbl.bf.drr_credit_unit; - scheduler_cfg->c_drr_id = l0_c_sp_cfg_tbl.bf.drr_id; - - e_sp_id = scheduler_cfg->sp_id * 8 + scheduler_cfg->e_pri; - hppe_l0_e_sp_cfg_tbl_get(dev_id, e_sp_id, &l0_e_sp_cfg_tbl); - scheduler_cfg->e_drr_unit = l0_e_sp_cfg_tbl.bf.drr_credit_unit; - scheduler_cfg->e_drr_id = l0_e_sp_cfg_tbl.bf.drr_id; - - hppe_l0_flow_port_map_tbl_get(dev_id, node_id, &l0_flow_port_map_tbl); - *port_id = l0_flow_port_map_tbl.bf.port_num; - - hppe_l0_comp_cfg_tbl_get(dev_id, node_id, &l0_comp_cfg_tbl); - scheduler_cfg->drr_frame_mode = l0_comp_cfg_tbl.bf.drr_meter_len; - - return SW_OK; -} - -static sw_error_t -adpt_hppe_qos_cosmap_pcp_set(a_uint32_t dev_id, a_uint8_t group_id, - a_uint8_t pcp, fal_qos_cosmap_t *cosmap) -{ - sw_error_t rv = SW_OK; - union pcp_qos_group_0_u pcp_qos_group_0; - union pcp_qos_group_1_u pcp_qos_group_1; - - ADPT_DEV_ID_CHECK(dev_id); - ADPT_NULL_POINT_CHECK(cosmap); - - if (pcp >= PCP_QOS_GROUP_0_MAX_ENTRY) - return SW_BAD_PARAM; - - if (group_id == 0) { - pcp_qos_group_0.bf.qos_info = cosmap->internal_pcp | \ - (cosmap->internal_dei << 3) | \ - (cosmap->internal_pri << 4) | \ - (cosmap->internal_dscp << 8) | \ - (cosmap->internal_dp << 14); - rv = hppe_pcp_qos_group_0_set(dev_id, pcp, &pcp_qos_group_0); - } else if (group_id == 1) { - pcp_qos_group_1.bf.qos_info = cosmap->internal_pcp | \ - (cosmap->internal_dei << 3) | \ - (cosmap->internal_pri << 4) | \ - (cosmap->internal_dscp << 8) | \ - (cosmap->internal_dp << 14); - rv = hppe_pcp_qos_group_1_set(dev_id, pcp, &pcp_qos_group_1); - } else - return SW_BAD_PARAM; - - return rv; -} - -sw_error_t -adpt_ppe_qos_cosmap_pcp_set(a_uint32_t dev_id, a_uint8_t group_id, - a_uint8_t pcp, fal_qos_cosmap_t *cosmap) -{ - a_uint32_t chip_ver = 0; - - ADPT_DEV_ID_CHECK(dev_id); - ADPT_NULL_POINT_CHECK(cosmap); - - chip_ver = adpt_hppe_chip_revision_get(dev_id); - if (chip_ver == CPPE_REVISION) { -#if defined(CPPE) - return adpt_cppe_qos_cosmap_pcp_set(dev_id, group_id, - pcp, cosmap); -#endif - } else { - return adpt_hppe_qos_cosmap_pcp_set(dev_id, group_id, - pcp, cosmap); - } - - return SW_NOT_SUPPORTED;; -} -sw_error_t -adpt_hppe_qos_port_remark_get(a_uint32_t dev_id, fal_port_t port_id, - fal_qos_remark_enable_t *remark) -{ - sw_error_t rv = SW_OK; - union port_qos_ctrl_u port_qos_ctrl; - - memset(&port_qos_ctrl, 0, sizeof(port_qos_ctrl)); - ADPT_DEV_ID_CHECK(dev_id); - ADPT_NULL_POINT_CHECK(remark); - - rv = hppe_port_qos_ctrl_get(dev_id, port_id, &port_qos_ctrl); - - if( rv != SW_OK ) - return rv; - - remark->pcp_change_en = port_qos_ctrl.bf.port_pcp_change_en; - remark->dei_chage_en = port_qos_ctrl.bf.port_dei_change_en; - remark->dscp_change_en = port_qos_ctrl.bf.port_dscp_change_en; - - return SW_OK; -} - -static sw_error_t -adpt_hppe_qos_cosmap_dscp_get(a_uint32_t dev_id, a_uint8_t group_id, - a_uint8_t dscp, fal_qos_cosmap_t *cosmap) -{ - sw_error_t rv = SW_OK; - union dscp_qos_group_0_u dscp_qos_group_0; - union dscp_qos_group_1_u dscp_qos_group_1; - - ADPT_DEV_ID_CHECK(dev_id); - ADPT_NULL_POINT_CHECK(cosmap); - - if (dscp >= DSCP_QOS_GROUP_0_MAX_ENTRY) - return SW_BAD_PARAM; - - if (group_id == 0) { - rv = hppe_dscp_qos_group_0_get(dev_id, dscp, &dscp_qos_group_0); - if( rv != SW_OK ) - return rv; - cosmap->internal_pcp = dscp_qos_group_0.bf.qos_info & 7; - cosmap->internal_dei = (dscp_qos_group_0.bf.qos_info >> 3) & 1; - cosmap->internal_pri = (dscp_qos_group_0.bf.qos_info >> 4) & 0xf; - cosmap->internal_dscp = (dscp_qos_group_0.bf.qos_info >> 8) & 0x3f; - cosmap->internal_dp = (dscp_qos_group_0.bf.qos_info >> 14) & 0x3; - } else if (group_id == 1) { - rv = hppe_dscp_qos_group_1_get(dev_id, dscp, &dscp_qos_group_1); - if( rv != SW_OK ) - return rv; - cosmap->internal_pcp = dscp_qos_group_1.bf.qos_info & 7; - cosmap->internal_dei = (dscp_qos_group_1.bf.qos_info >> 3) & 1; - cosmap->internal_pri = (dscp_qos_group_1.bf.qos_info >> 4) & 0xf; - cosmap->internal_dscp = (dscp_qos_group_1.bf.qos_info >> 8) & 0x3f; - cosmap->internal_dp = (dscp_qos_group_1.bf.qos_info >> 14) & 0x3; - } else - return SW_BAD_PARAM; - - return SW_OK; -} - -sw_error_t -adpt_ppe_qos_cosmap_dscp_get(a_uint32_t dev_id, a_uint8_t group_id, - a_uint8_t dscp, fal_qos_cosmap_t *cosmap) -{ - a_uint32_t chip_ver = 0; - - ADPT_DEV_ID_CHECK(dev_id); - ADPT_NULL_POINT_CHECK(cosmap); - - chip_ver = adpt_hppe_chip_revision_get(dev_id); - if (chip_ver == CPPE_REVISION) { -#if defined(CPPE) - return adpt_cppe_qos_cosmap_dscp_get(dev_id, group_id, - dscp, cosmap); -#endif - } else { - return adpt_hppe_qos_cosmap_dscp_get(dev_id, group_id, - dscp, cosmap); - } - - return SW_NOT_SUPPORTED; -} - -static sw_error_t -adpt_hppe_qos_cosmap_flow_set(a_uint32_t dev_id, a_uint8_t group_id, - a_uint16_t flow, fal_qos_cosmap_t *cosmap) -{ - sw_error_t rv = SW_OK; - union flow_qos_group_0_u flow_qos_group_0; - union flow_qos_group_1_u flow_qos_group_1; - - ADPT_DEV_ID_CHECK(dev_id); - ADPT_NULL_POINT_CHECK(cosmap); - - if (flow >= FLOW_QOS_GROUP_0_MAX_ENTRY) - return SW_BAD_PARAM; - - if (group_id == 0) { - flow_qos_group_0.bf.qos_info = cosmap->internal_pcp | \ - (cosmap->internal_dei << 3) | \ - (cosmap->internal_pri << 4) | \ - (cosmap->internal_dscp << 8) | \ - (cosmap->internal_dp << 14); - rv = hppe_flow_qos_group_0_set(dev_id, flow, &flow_qos_group_0); - } else if (group_id == 1) { - flow_qos_group_1.bf.qos_info = cosmap->internal_pcp | \ - (cosmap->internal_dei << 3) | \ - (cosmap->internal_pri << 4) | \ - (cosmap->internal_dscp << 8) | \ - (cosmap->internal_dp << 14); - rv = hppe_flow_qos_group_1_set(dev_id, flow, &flow_qos_group_1); - } else - return SW_BAD_PARAM; - - return rv; -} - -sw_error_t -adpt_ppe_qos_cosmap_flow_set(a_uint32_t dev_id, a_uint8_t group_id, - a_uint16_t flow, fal_qos_cosmap_t *cosmap) -{ - a_uint32_t chip_ver = 0; - - ADPT_DEV_ID_CHECK(dev_id); - ADPT_NULL_POINT_CHECK(cosmap); - - chip_ver = adpt_hppe_chip_revision_get(dev_id); - if (chip_ver == CPPE_REVISION) { -#if defined(CPPE) - return adpt_cppe_qos_cosmap_flow_set(dev_id, group_id, - flow, cosmap); -#endif - } else { - return adpt_hppe_qos_cosmap_flow_set(dev_id, group_id, - flow, cosmap); - } - - return SW_NOT_SUPPORTED; -} - -static sw_error_t -adpt_hppe_qos_port_group_set(a_uint32_t dev_id, fal_port_t port_id, - fal_qos_group_t *group) -{ - union port_qos_ctrl_u port_qos_ctrl; - - memset(&port_qos_ctrl, 0, sizeof(port_qos_ctrl)); - ADPT_DEV_ID_CHECK(dev_id); - ADPT_NULL_POINT_CHECK(group); - - hppe_port_qos_ctrl_get(dev_id, port_id, &port_qos_ctrl); - - port_qos_ctrl.bf.pcp_qos_group_id = group->pcp_group; - port_qos_ctrl.bf.dscp_qos_group_id = group->dscp_group; - port_qos_ctrl.bf.flow_qos_group_id = group->flow_group; - - return hppe_port_qos_ctrl_set(dev_id, port_id, &port_qos_ctrl); -} - -sw_error_t -adpt_ppe_qos_port_group_set(a_uint32_t dev_id, fal_port_t port_id, - fal_qos_group_t *group) -{ - a_uint32_t chip_ver = 0; - - ADPT_DEV_ID_CHECK(dev_id); - ADPT_NULL_POINT_CHECK(group); - - chip_ver = adpt_hppe_chip_revision_get(dev_id); - if (chip_ver == CPPE_REVISION) { -#if defined(CPPE) - return adpt_cppe_qos_port_group_set(dev_id, port_id, group); -#endif - } else { - return adpt_hppe_qos_port_group_set(dev_id, port_id, group); - } - - return SW_NOT_SUPPORTED; -} - -sw_error_t -adpt_hppe_ring_queue_map_set(a_uint32_t dev_id, - a_uint32_t ring_id, fal_queue_bmp_t *queue_bmp) -{ - union ring_q_map_tbl_u ring_q_map_tbl; - - memset(&ring_q_map_tbl, 0, sizeof(ring_q_map_tbl)); - ADPT_DEV_ID_CHECK(dev_id); - ADPT_NULL_POINT_CHECK(queue_bmp); - if (ring_id >= RING_Q_MAP_TBL_MAX_ENTRY) - return SW_BAD_PARAM; - - memcpy(ring_q_map_tbl.val, queue_bmp->bmp, sizeof(ring_q_map_tbl.val)); - return hppe_ring_q_map_tbl_set(dev_id, ring_id, &ring_q_map_tbl); -} - -static sw_error_t -adpt_hppe_qos_cosmap_dscp_set(a_uint32_t dev_id, a_uint8_t group_id, - a_uint8_t dscp, fal_qos_cosmap_t *cosmap) -{ - sw_error_t rv = SW_OK; - union dscp_qos_group_0_u dscp_qos_group_0; - union dscp_qos_group_1_u dscp_qos_group_1; - - ADPT_DEV_ID_CHECK(dev_id); - ADPT_NULL_POINT_CHECK(cosmap); - - if (dscp >= DSCP_QOS_GROUP_0_MAX_ENTRY) - return SW_BAD_PARAM; - - if (group_id == 0) { - dscp_qos_group_0.bf.qos_info = cosmap->internal_pcp | \ - (cosmap->internal_dei << 3) | \ - (cosmap->internal_pri << 4) | \ - (cosmap->internal_dscp << 8) | \ - (cosmap->internal_dp << 14); - rv = hppe_dscp_qos_group_0_set(dev_id, dscp, &dscp_qos_group_0); - } else if (group_id == 1) { - dscp_qos_group_1.bf.qos_info = cosmap->internal_pcp | \ - (cosmap->internal_dei << 3) | \ - (cosmap->internal_pri << 4) | \ - (cosmap->internal_dscp << 8) | \ - (cosmap->internal_dp << 14); - rv = hppe_dscp_qos_group_1_set(dev_id, dscp, &dscp_qos_group_1); - } else - return SW_BAD_PARAM; - - return rv; -} - -sw_error_t -adpt_ppe_qos_cosmap_dscp_set(a_uint32_t dev_id, a_uint8_t group_id, - a_uint8_t dscp, fal_qos_cosmap_t *cosmap) -{ - a_uint32_t chip_ver = 0; - - ADPT_DEV_ID_CHECK(dev_id); - ADPT_NULL_POINT_CHECK(cosmap); - - chip_ver = adpt_hppe_chip_revision_get(dev_id); - if (chip_ver == CPPE_REVISION) { -#if defined(CPPE) - return adpt_cppe_qos_cosmap_dscp_set(dev_id, group_id, - dscp, cosmap); -#endif - } else { - return adpt_hppe_qos_cosmap_dscp_set(dev_id, group_id, - dscp, cosmap); - } - - return SW_NOT_SUPPORTED; -} - -sw_error_t -adpt_hppe_qos_port_remark_set(a_uint32_t dev_id, fal_port_t port_id, - fal_qos_remark_enable_t *remark) -{ - union port_qos_ctrl_u port_qos_ctrl; - - memset(&port_qos_ctrl, 0, sizeof(port_qos_ctrl)); - ADPT_DEV_ID_CHECK(dev_id); - ADPT_NULL_POINT_CHECK(remark); - - hppe_port_qos_ctrl_get(dev_id, port_id, &port_qos_ctrl); - - port_qos_ctrl.bf.port_pcp_change_en = remark->pcp_change_en; - port_qos_ctrl.bf.port_dei_change_en = remark->dei_chage_en; - port_qos_ctrl.bf.port_dscp_change_en = remark->dscp_change_en; - - return hppe_port_qos_ctrl_set(dev_id, port_id, &port_qos_ctrl); -} -sw_error_t -adpt_hppe_l1_flow_map_set(a_uint32_t dev_id, - a_uint32_t node_id, - fal_port_t port_id, - fal_qos_scheduler_cfg_t *scheduler_cfg) -{ - union l1_flow_map_tbl_u l1_flow_map_tbl; - union l1_c_sp_cfg_tbl_u l1_c_sp_cfg_tbl; - union l1_e_sp_cfg_tbl_u l1_e_sp_cfg_tbl; - union l1_flow_port_map_tbl_u l1_flow_port_map_tbl; - union l1_comp_cfg_tbl_u l1_comp_cfg_tbl; - a_uint32_t c_sp_id, e_sp_id; - - memset(&l1_flow_map_tbl, 0, sizeof(l1_flow_map_tbl)); - ADPT_DEV_ID_CHECK(dev_id); - ADPT_NULL_POINT_CHECK(scheduler_cfg); - if (node_id >= L1_FLOW_MAP_TBL_MAX_ENTRY) - return SW_BAD_PARAM; - - l1_flow_map_tbl.bf.e_drr_wt= scheduler_cfg->e_drr_wt; - l1_flow_map_tbl.bf.c_drr_wt = scheduler_cfg->c_drr_wt; - l1_flow_map_tbl.bf.e_pri = scheduler_cfg->e_pri; - l1_flow_map_tbl.bf.c_pri = scheduler_cfg->c_pri; - l1_flow_map_tbl.bf.sp_id = scheduler_cfg->sp_id; - hppe_l1_flow_map_tbl_set(dev_id, node_id, &l1_flow_map_tbl); - - c_sp_id = scheduler_cfg->sp_id * 8 + scheduler_cfg->c_pri; - l1_c_sp_cfg_tbl.bf.drr_credit_unit = scheduler_cfg->c_drr_unit; - l1_c_sp_cfg_tbl.bf.drr_id = scheduler_cfg->c_drr_id; - hppe_l1_c_sp_cfg_tbl_set(dev_id, c_sp_id, &l1_c_sp_cfg_tbl); - - e_sp_id = scheduler_cfg->sp_id * 8 + scheduler_cfg->e_pri; - l1_e_sp_cfg_tbl.bf.drr_credit_unit = scheduler_cfg->e_drr_unit; - l1_e_sp_cfg_tbl.bf.drr_id = scheduler_cfg->e_drr_id; - hppe_l1_e_sp_cfg_tbl_set(dev_id, e_sp_id, &l1_e_sp_cfg_tbl); - - l1_flow_port_map_tbl.bf.port_num = port_id; - hppe_l1_flow_port_map_tbl_set(dev_id, node_id, &l1_flow_port_map_tbl); - - hppe_l1_comp_cfg_tbl_get(dev_id, node_id, &l1_comp_cfg_tbl); - l1_comp_cfg_tbl.bf.drr_meter_len = scheduler_cfg->drr_frame_mode; - hppe_l1_comp_cfg_tbl_set(dev_id, node_id, &l1_comp_cfg_tbl); - - return SW_OK; -} - -sw_error_t -adpt_hppe_queue_scheduler_set(a_uint32_t dev_id, a_uint32_t node_id, - fal_queue_scheduler_level_t level, - fal_port_t port_id, - fal_qos_scheduler_cfg_t *scheduler_cfg) -{ - if (level == FAL_QUEUE_SCHEDULER_LEVEL0) - return adpt_hppe_l0_queue_map_set(dev_id, node_id, port_id, scheduler_cfg); - else if ((level == FAL_QUEUE_SCHEDULER_LEVEL1)) - return adpt_hppe_l1_flow_map_set(dev_id, node_id, port_id, scheduler_cfg); - else - return SW_FAIL; -} - -sw_error_t -adpt_hppe_queue_scheduler_get(a_uint32_t dev_id, a_uint32_t node_id, - fal_queue_scheduler_level_t level, - fal_port_t *port_id, - fal_qos_scheduler_cfg_t *scheduler_cfg) -{ - if (level == FAL_QUEUE_SCHEDULER_LEVEL0) - return adpt_hppe_l0_queue_map_get(dev_id, node_id, port_id, scheduler_cfg); - else if ((level == FAL_QUEUE_SCHEDULER_LEVEL1)) - return adpt_hppe_l1_flow_map_get(dev_id, node_id, port_id, scheduler_cfg); - else - return SW_FAIL; -} - -static sw_error_t -adpt_hppe_qos_cosmap_flow_get(a_uint32_t dev_id, a_uint8_t group_id, - a_uint16_t flow, fal_qos_cosmap_t *cosmap) -{ - sw_error_t rv = SW_OK; - union flow_qos_group_0_u flow_qos_group_0; - union flow_qos_group_1_u flow_qos_group_1; - - ADPT_DEV_ID_CHECK(dev_id); - ADPT_NULL_POINT_CHECK(cosmap); - - if (flow >= FLOW_QOS_GROUP_0_MAX_ENTRY) - return SW_BAD_PARAM; - - if (group_id == 0) { - rv = hppe_flow_qos_group_0_get(dev_id, flow, &flow_qos_group_0); - if( rv != SW_OK ) - return rv; - cosmap->internal_pcp = flow_qos_group_0.bf.qos_info & 7; - cosmap->internal_dei = (flow_qos_group_0.bf.qos_info >> 3) & 1; - cosmap->internal_pri = (flow_qos_group_0.bf.qos_info >> 4) & 0xf; - cosmap->internal_dscp = (flow_qos_group_0.bf.qos_info >> 8) & 0x3f; - cosmap->internal_dp = (flow_qos_group_0.bf.qos_info >> 14) & 0x3; - } else if (group_id == 1) { - rv = hppe_flow_qos_group_1_get(dev_id, flow, &flow_qos_group_1); - if( rv != SW_OK ) - return rv; - cosmap->internal_pcp = flow_qos_group_1.bf.qos_info & 7; - cosmap->internal_dei = (flow_qos_group_1.bf.qos_info >> 3) & 1; - cosmap->internal_pri = (flow_qos_group_1.bf.qos_info >> 4) & 0xf; - cosmap->internal_dscp = (flow_qos_group_1.bf.qos_info >> 8) & 0x3f; - cosmap->internal_dp = (flow_qos_group_1.bf.qos_info >> 14) & 0x3; - } else - return SW_BAD_PARAM; - - return SW_OK; -} - -sw_error_t -adpt_ppe_qos_cosmap_flow_get(a_uint32_t dev_id, a_uint8_t group_id, - a_uint16_t flow, fal_qos_cosmap_t *cosmap) -{ - a_uint32_t chip_ver = 0; - - ADPT_DEV_ID_CHECK(dev_id); - ADPT_NULL_POINT_CHECK(cosmap); - - chip_ver = adpt_hppe_chip_revision_get(dev_id); - if (chip_ver == CPPE_REVISION) { -#if defined(CPPE) - return adpt_cppe_qos_cosmap_flow_get(dev_id, group_id, - flow, cosmap); -#endif - } else { - return adpt_hppe_qos_cosmap_flow_get(dev_id, group_id, - flow, cosmap); - } - - return SW_NOT_SUPPORTED; -} - -static sw_error_t -adpt_hppe_qos_port_group_get(a_uint32_t dev_id, fal_port_t port_id, - fal_qos_group_t *group) -{ - sw_error_t rv = SW_OK; - union port_qos_ctrl_u port_qos_ctrl; - - memset(&port_qos_ctrl, 0, sizeof(port_qos_ctrl)); - ADPT_DEV_ID_CHECK(dev_id); - ADPT_NULL_POINT_CHECK(group); - - rv = hppe_port_qos_ctrl_get(dev_id, port_id, &port_qos_ctrl); - if( rv != SW_OK ) - return rv; - - group->pcp_group = port_qos_ctrl.bf.pcp_qos_group_id; - group->dscp_group = port_qos_ctrl.bf.dscp_qos_group_id; - group->flow_group = port_qos_ctrl.bf.flow_qos_group_id; - - return SW_OK; -} - -sw_error_t -adpt_ppe_qos_port_group_get(a_uint32_t dev_id, fal_port_t port_id, - fal_qos_group_t *group) -{ - a_uint32_t chip_ver = 0; - - ADPT_DEV_ID_CHECK(dev_id); - ADPT_NULL_POINT_CHECK(group); - - chip_ver = adpt_hppe_chip_revision_get(dev_id); - if (chip_ver == CPPE_REVISION) { -#if defined(CPPE) - return adpt_cppe_qos_port_group_get(dev_id, port_id, group); -#endif - } else { - return adpt_hppe_qos_port_group_get(dev_id, port_id, group); - } - - return SW_NOT_SUPPORTED; -} - -sw_error_t -adpt_hppe_ring_queue_map_get(a_uint32_t dev_id, - a_uint32_t ring_id, fal_queue_bmp_t *queue_bmp) -{ - union ring_q_map_tbl_u ring_q_map_tbl; - - memset(&ring_q_map_tbl, 0, sizeof(ring_q_map_tbl)); - ADPT_DEV_ID_CHECK(dev_id); - ADPT_NULL_POINT_CHECK(queue_bmp); - if (ring_id >= RING_Q_MAP_TBL_MAX_ENTRY) - return SW_BAD_PARAM; - - hppe_ring_q_map_tbl_get(dev_id, ring_id, &ring_q_map_tbl); - memcpy(queue_bmp->bmp, ring_q_map_tbl.val, sizeof(ring_q_map_tbl.val)); - return SW_OK; -} - -sw_error_t -adpt_hppe_port_queues_get(a_uint32_t dev_id, - fal_port_t port_id, fal_queue_bmp_t *queue_bmp) -{ - ADPT_DEV_ID_CHECK(dev_id); - ADPT_NULL_POINT_CHECK(queue_bmp); - - *queue_bmp = port_queue_map[port_id]; - - return SW_OK; -} - -sw_error_t -adpt_hppe_tdm_tick_num_set(a_uint32_t dev_id, a_uint32_t tick_num) -{ - union tdm_depth_cfg_u tdm_depth_cfg; - - ADPT_DEV_ID_CHECK(dev_id); - - tdm_depth_cfg.bf.tdm_depth = tick_num; - return hppe_tdm_depth_cfg_set(dev_id, &tdm_depth_cfg); -} -#ifndef IN_QOS_MINI -sw_error_t -adpt_hppe_tdm_tick_num_get(a_uint32_t dev_id, a_uint32_t *tick_num) -{ - union tdm_depth_cfg_u tdm_depth_cfg; - - ADPT_DEV_ID_CHECK(dev_id); - ADPT_NULL_POINT_CHECK(tick_num); - - hppe_tdm_depth_cfg_get(dev_id, &tdm_depth_cfg); - *tick_num = tdm_depth_cfg.bf.tdm_depth; - - return SW_OK; -} -#endif -sw_error_t -adpt_hppe_port_scheduler_cfg_reset(a_uint32_t dev_id, - fal_port_t port_id) -{ - ssdk_dt_scheduler_cfg *dt_cfg; - fal_qos_scheduler_cfg_t cfg; - a_uint32_t i; - - dt_cfg = ssdk_bootup_shceduler_cfg_get(dev_id); - if (!dt_cfg) - return SW_FAIL; - - /* L1 shceduler */ - for (i = 0; i < SSDK_L1SCHEDULER_CFG_MAX; i++) { - if (dt_cfg->l1cfg[i].valid && dt_cfg->l1cfg[i].port_id == port_id) { - cfg.sp_id = dt_cfg->l1cfg[i].port_id; - cfg.c_pri = dt_cfg->l1cfg[i].cpri; - cfg.e_pri = dt_cfg->l1cfg[i].epri; - cfg.c_drr_id = dt_cfg->l1cfg[i].cdrr_id; - cfg.e_drr_id = dt_cfg->l1cfg[i].edrr_id; - cfg.c_drr_wt = 1; - cfg.e_drr_wt = 1; - adpt_hppe_queue_scheduler_set(dev_id, i, 1, - dt_cfg->l1cfg[i].port_id, &cfg); - } - } - - /* L0 shceduler */ - for (i = 0; i < SSDK_L0SCHEDULER_CFG_MAX; i++) { - if (dt_cfg->l0cfg[i].valid && dt_cfg->l0cfg[i].port_id == port_id) { - cfg.sp_id = dt_cfg->l0cfg[i].sp_id; - cfg.c_pri = dt_cfg->l0cfg[i].cpri; - cfg.e_pri = dt_cfg->l0cfg[i].epri; - cfg.c_drr_id = dt_cfg->l0cfg[i].cdrr_id; - cfg.e_drr_id = dt_cfg->l0cfg[i].edrr_id; - cfg.c_drr_wt = 1; - cfg.e_drr_wt = 1; - adpt_hppe_queue_scheduler_set(dev_id, i, - 0, dt_cfg->l0cfg[i].port_id, &cfg); - } - } - - return SW_OK; -} - -sw_error_t -adpt_hppe_port_scheduler_cfg_set(a_uint32_t dev_id, - a_uint32_t tick_index, - fal_port_scheduler_cfg_t *cfg) -{ - union psch_tdm_cfg_tbl_u psch_tdm_cfg; - - ADPT_DEV_ID_CHECK(dev_id); - ADPT_NULL_POINT_CHECK(cfg); - - psch_tdm_cfg.bf.ens_port_bitmap = cfg->en_scheduler_port_bmp; - psch_tdm_cfg.bf.ens_port = cfg->en_scheduler_port; - psch_tdm_cfg.bf.des_port = cfg->de_scheduler_port; - return hppe_psch_tdm_cfg_tbl_set(dev_id, tick_index, &psch_tdm_cfg); -} -#ifndef IN_QOS_MINI -sw_error_t -adpt_hppe_port_scheduler_cfg_get(a_uint32_t dev_id, - a_uint32_t tick_index, - fal_port_scheduler_cfg_t *cfg) -{ - union psch_tdm_cfg_tbl_u psch_tdm_cfg; - - ADPT_DEV_ID_CHECK(dev_id); - ADPT_NULL_POINT_CHECK(cfg); - - hppe_psch_tdm_cfg_tbl_get(dev_id, tick_index, &psch_tdm_cfg); - cfg->en_scheduler_port_bmp = psch_tdm_cfg.bf.ens_port_bitmap; - cfg->en_scheduler_port = psch_tdm_cfg.bf.ens_port; - cfg->de_scheduler_port = psch_tdm_cfg.bf.des_port; - - return SW_OK; -} -#endif -sw_error_t -adpt_hppe_scheduler_dequeue_ctrl_get(a_uint32_t dev_id, - a_uint32_t queue_id, - a_bool_t *enable) -{ - union deq_dis_tbl_u deq; - - ADPT_DEV_ID_CHECK(dev_id); - ADPT_NULL_POINT_CHECK(enable); - - hppe_deq_dis_tbl_get(dev_id, queue_id, &deq); - *enable = !(deq.bf.deq_dis); - - return SW_OK; -} - -sw_error_t -adpt_hppe_scheduler_dequeue_ctrl_set(a_uint32_t dev_id, - a_uint32_t queue_id, - a_bool_t enable) -{ - union deq_dis_tbl_u deq; - - ADPT_DEV_ID_CHECK(dev_id); - - deq.bf.deq_dis = !enable; - return hppe_deq_dis_tbl_set(dev_id, queue_id, &deq); -} - -sw_error_t -adpt_hppe_port_scheduler_resource_get(a_uint32_t dev_id, - fal_port_t port_id, - fal_portscheduler_resource_t *cfg) -{ - ssdk_dt_scheduler_cfg *dt_cfg; - ssdk_dt_portscheduler_cfg *port_resource; - - ADPT_DEV_ID_CHECK(dev_id); - ADPT_NULL_POINT_CHECK(cfg); - - if (port_id >= SSDK_MAX_PORT_NUM) - return SW_BAD_PARAM; - - dt_cfg = ssdk_bootup_shceduler_cfg_get(dev_id); - if (!dt_cfg) - return SW_NOT_SUPPORTED; - - port_resource = &dt_cfg->pool[port_id]; - cfg->ucastq_start = port_resource->ucastq_start; - cfg->ucastq_num = port_resource->ucastq_end - port_resource->ucastq_start + 1; - cfg->mcastq_start = port_resource->mcastq_start; - cfg->mcastq_num = port_resource->mcastq_end - port_resource->mcastq_start + 1; - cfg->l0sp_start = port_resource->l0sp_start; - cfg->l0sp_num = port_resource->l0sp_end - port_resource->l0sp_start + 1; - cfg->l0cdrr_start = port_resource->l0cdrr_start; - cfg->l0cdrr_num = port_resource->l0cdrr_end - port_resource->l0cdrr_start + 1; - cfg->l0edrr_start = port_resource->l0edrr_start; - cfg->l0edrr_num = port_resource->l0edrr_end - port_resource->l0edrr_start + 1; - cfg->l1sp_start = port_id; - cfg->l1sp_num = 1; - cfg->l1cdrr_start = port_resource->l1cdrr_start; - cfg->l1cdrr_num = port_resource->l1cdrr_end - port_resource->l1cdrr_start + 1; - cfg->l1edrr_start = port_resource->l1edrr_start; - cfg->l1edrr_num = port_resource->l1edrr_end - port_resource->l1edrr_start + 1; - - return SW_OK; -} - -void adpt_hppe_qos_func_bitmap_init(a_uint32_t dev_id) -{ - adpt_api_t *p_adpt_api = NULL; - - p_adpt_api = adpt_api_ptr_get(dev_id); - - if(p_adpt_api == NULL) - return; - - p_adpt_api->adpt_qos_func_bitmap = ((1 << FUNC_QOS_PORT_PRI_SET) | - (1 << FUNC_QOS_PORT_PRI_GET) | - (1 << FUNC_QOS_COSMAP_PCP_GET) | - (1 << FUNC_QUEUE_SCHEDULER_SET) | - (1 << FUNC_QUEUE_SCHEDULER_GET) | - (1 << FUNC_PORT_QUEUES_GET) | - (1 << FUNC_QOS_COSMAP_PCP_SET) | - (1 << FUNC_QOS_PORT_REMARK_GET) | - (1 << FUNC_QOS_COSMAP_DSCP_GET) | - (1 << FUNC_QOS_COSMAP_FLOW_SET) | - (1 << FUNC_QOS_PORT_GROUP_SET) | - (1 << FUNC_RING_QUEUE_MAP_SET) | - (1 << FUNC_QOS_COSMAP_DSCP_SET) | - (1 << FUNC_QOS_PORT_REMARK_SET) | - (1 << FUNC_QOS_COSMAP_FLOW_GET) | - (1 << FUNC_QOS_PORT_GROUP_GET) | - (1 << FUNC_RING_QUEUE_MAP_GET) | - (1 << FUNC_TDM_TICK_NUM_SET) | - (1 << FUNC_TDM_TICK_NUM_GET) | - (1 << FUNC_PORT_SCHEDULER_CFG_SET) | - (1 << FUNC_PORT_SCHEDULER_CFG_GET) | - (1 << FUNC_SCHEDULER_DEQUEUE_CTRL_GET) | - (1 << FUNC_SCHEDULER_DEQUEUE_CTRL_SET) | - (1 << FUNC_QOS_PORT_MODE_PRI_GET) | - (1 << FUNC_QOS_PORT_MODE_PRI_SET) | - (1 << FUNC_QOS_PORT_SCHEDULER_CFG_RESET) | - (1 << FUNC_QOS_PORT_SCHEDULER_RESOURCE_GET)); - return; -} - -static void adpt_hppe_qos_func_unregister(a_uint32_t dev_id, adpt_api_t *p_adpt_api) -{ - if(p_adpt_api == NULL) - return; - - p_adpt_api->adpt_qos_port_pri_set = NULL; - p_adpt_api->adpt_qos_port_pri_get = NULL; - p_adpt_api->adpt_qos_cosmap_pcp_get = NULL; - p_adpt_api->adpt_queue_scheduler_set = NULL; - p_adpt_api->adpt_queue_scheduler_get = NULL; - p_adpt_api->adpt_port_queues_get = NULL; - p_adpt_api->adpt_qos_cosmap_pcp_set = NULL; - p_adpt_api->adpt_qos_port_remark_get = NULL; - p_adpt_api->adpt_qos_cosmap_dscp_get = NULL; - p_adpt_api->adpt_qos_cosmap_flow_set = NULL; - p_adpt_api->adpt_qos_port_group_set = NULL; - p_adpt_api->adpt_ring_queue_map_set = NULL; - p_adpt_api->adpt_qos_cosmap_dscp_set = NULL; - p_adpt_api->adpt_qos_port_remark_set = NULL; - p_adpt_api->adpt_qos_cosmap_flow_get = NULL; - p_adpt_api->adpt_qos_port_group_get = NULL; - p_adpt_api->adpt_ring_queue_map_get = NULL; - p_adpt_api->adpt_tdm_tick_num_set = NULL; - p_adpt_api->adpt_tdm_tick_num_get = NULL; - p_adpt_api->adpt_port_scheduler_cfg_set = NULL; - p_adpt_api->adpt_port_scheduler_cfg_get = NULL; - p_adpt_api->adpt_scheduler_dequeue_ctrl_get = NULL; - p_adpt_api->adpt_scheduler_dequeue_ctrl_set = NULL; - p_adpt_api->adpt_qos_port_mode_pri_get = NULL; - p_adpt_api->adpt_qos_port_mode_pri_set = NULL; - p_adpt_api->adpt_port_scheduler_cfg_reset = NULL; - p_adpt_api->adpt_port_scheduler_resource_get = NULL; - - return; -} - -sw_error_t adpt_hppe_qos_init(a_uint32_t dev_id) -{ - adpt_api_t *p_adpt_api = NULL; - - p_adpt_api = adpt_api_ptr_get(dev_id); - - if(p_adpt_api == NULL) - return SW_FAIL; - - adpt_hppe_qos_func_unregister(dev_id, p_adpt_api); - - if (p_adpt_api->adpt_qos_func_bitmap & (1 << FUNC_QOS_PORT_PRI_SET)) - p_adpt_api->adpt_qos_port_pri_set = adpt_ppe_qos_port_pri_set; - if (p_adpt_api->adpt_qos_func_bitmap & (1 << FUNC_QOS_PORT_PRI_GET)) - p_adpt_api->adpt_qos_port_pri_get = adpt_ppe_qos_port_pri_get; - if (p_adpt_api->adpt_qos_func_bitmap & (1 << FUNC_QOS_COSMAP_PCP_GET)) - p_adpt_api->adpt_qos_cosmap_pcp_get = adpt_ppe_qos_cosmap_pcp_get; - if (p_adpt_api->adpt_qos_func_bitmap & (1 << FUNC_QUEUE_SCHEDULER_SET)) - p_adpt_api->adpt_queue_scheduler_set = adpt_hppe_queue_scheduler_set; - if (p_adpt_api->adpt_qos_func_bitmap & (1 << FUNC_QUEUE_SCHEDULER_GET)) - p_adpt_api->adpt_queue_scheduler_get = adpt_hppe_queue_scheduler_get; - if (p_adpt_api->adpt_qos_func_bitmap & (1 << FUNC_PORT_QUEUES_GET)) - p_adpt_api->adpt_port_queues_get = adpt_hppe_port_queues_get; - if (p_adpt_api->adpt_qos_func_bitmap & (1 << FUNC_QOS_COSMAP_PCP_SET)) - p_adpt_api->adpt_qos_cosmap_pcp_set = adpt_ppe_qos_cosmap_pcp_set; - if (p_adpt_api->adpt_qos_func_bitmap & (1 << FUNC_QOS_PORT_REMARK_GET)) - p_adpt_api->adpt_qos_port_remark_get = adpt_hppe_qos_port_remark_get; - if (p_adpt_api->adpt_qos_func_bitmap & (1 << FUNC_QOS_COSMAP_DSCP_GET)) - p_adpt_api->adpt_qos_cosmap_dscp_get = adpt_ppe_qos_cosmap_dscp_get; - if (p_adpt_api->adpt_qos_func_bitmap & (1 << FUNC_QOS_COSMAP_FLOW_SET)) - p_adpt_api->adpt_qos_cosmap_flow_set = adpt_ppe_qos_cosmap_flow_set; - if (p_adpt_api->adpt_qos_func_bitmap & (1 << FUNC_QOS_PORT_GROUP_SET)) - p_adpt_api->adpt_qos_port_group_set = adpt_ppe_qos_port_group_set; - if (p_adpt_api->adpt_qos_func_bitmap & (1 << FUNC_RING_QUEUE_MAP_SET)) - p_adpt_api->adpt_ring_queue_map_set = adpt_hppe_ring_queue_map_set; - if (p_adpt_api->adpt_qos_func_bitmap & (1 << FUNC_QOS_COSMAP_DSCP_SET)) - p_adpt_api->adpt_qos_cosmap_dscp_set = adpt_ppe_qos_cosmap_dscp_set; - if (p_adpt_api->adpt_qos_func_bitmap & (1 << FUNC_QOS_PORT_REMARK_SET)) - p_adpt_api->adpt_qos_port_remark_set = adpt_hppe_qos_port_remark_set; - if (p_adpt_api->adpt_qos_func_bitmap & (1 << FUNC_QOS_COSMAP_FLOW_GET)) - p_adpt_api->adpt_qos_cosmap_flow_get = adpt_ppe_qos_cosmap_flow_get; - if (p_adpt_api->adpt_qos_func_bitmap & (1 << FUNC_QOS_PORT_GROUP_GET)) - p_adpt_api->adpt_qos_port_group_get = adpt_ppe_qos_port_group_get; - if (p_adpt_api->adpt_qos_func_bitmap & (1 << FUNC_RING_QUEUE_MAP_GET)) - p_adpt_api->adpt_ring_queue_map_get = adpt_hppe_ring_queue_map_get; - if (p_adpt_api->adpt_qos_func_bitmap & (1 << FUNC_TDM_TICK_NUM_SET)) - p_adpt_api->adpt_tdm_tick_num_set = adpt_hppe_tdm_tick_num_set; -#ifndef IN_QOS_MINI - if (p_adpt_api->adpt_qos_func_bitmap & (1 << FUNC_TDM_TICK_NUM_GET)) - p_adpt_api->adpt_tdm_tick_num_get = adpt_hppe_tdm_tick_num_get; -#endif - if (p_adpt_api->adpt_qos_func_bitmap & (1 << FUNC_PORT_SCHEDULER_CFG_SET)) - p_adpt_api->adpt_port_scheduler_cfg_set = adpt_hppe_port_scheduler_cfg_set; -#ifndef IN_QOS_MINI - if (p_adpt_api->adpt_qos_func_bitmap & (1 << FUNC_PORT_SCHEDULER_CFG_GET)) - p_adpt_api->adpt_port_scheduler_cfg_get = adpt_hppe_port_scheduler_cfg_get; -#endif - if (p_adpt_api->adpt_qos_func_bitmap & (1 << FUNC_SCHEDULER_DEQUEUE_CTRL_GET)) - p_adpt_api->adpt_scheduler_dequeue_ctrl_get = adpt_hppe_scheduler_dequeue_ctrl_get; - if (p_adpt_api->adpt_qos_func_bitmap & (1 << FUNC_SCHEDULER_DEQUEUE_CTRL_SET)) - p_adpt_api->adpt_scheduler_dequeue_ctrl_set = adpt_hppe_scheduler_dequeue_ctrl_set; -#ifndef IN_QOS_MINI - if (p_adpt_api->adpt_qos_func_bitmap & (1 << FUNC_QOS_PORT_MODE_PRI_GET)) - p_adpt_api->adpt_qos_port_mode_pri_get = adpt_hppe_qos_port_mode_pri_get; - if (p_adpt_api->adpt_qos_func_bitmap & (1 << FUNC_QOS_PORT_MODE_PRI_SET)) - p_adpt_api->adpt_qos_port_mode_pri_set = adpt_hppe_qos_port_mode_pri_set; -#endif - if (p_adpt_api->adpt_qos_func_bitmap & (1 << FUNC_QOS_PORT_SCHEDULER_CFG_RESET)) - p_adpt_api->adpt_port_scheduler_cfg_reset = adpt_hppe_port_scheduler_cfg_reset; - if (p_adpt_api->adpt_qos_func_bitmap & (1 << FUNC_QOS_PORT_SCHEDULER_RESOURCE_GET)) - p_adpt_api->adpt_port_scheduler_resource_get = adpt_hppe_port_scheduler_resource_get; - - return SW_OK; -} - -/** - * @} - */ diff --git a/feeds/ipq807x/qca-ssdk/src/src/adpt/hppe/adpt_hppe_rss_hash.c b/feeds/ipq807x/qca-ssdk/src/src/adpt/hppe/adpt_hppe_rss_hash.c deleted file mode 100755 index 1834b3950..000000000 --- a/feeds/ipq807x/qca-ssdk/src/src/adpt/hppe/adpt_hppe_rss_hash.c +++ /dev/null @@ -1,296 +0,0 @@ -/* - * Copyright (c) 2017, The Linux Foundation. All rights reserved. - * Permission to use, copy, modify, and/or distribute this software for - * any purpose with or without fee is hereby granted, provided that the - * above copyright notice and this permission notice appear in all copies. - * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES - * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR - * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES - * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN - * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT - * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. - */ - - -/** - * @defgroup - * @{ - */ -#include "sw.h" -#include "hppe_rss_reg.h" -#include "hppe_rss.h" -#include "adpt.h" - -sw_error_t -adpt_hppe_rss_hash_config_set(a_uint32_t dev_id, fal_rss_hash_mode_t mode, - fal_rss_hash_config_t * config) -{ - a_uint32_t index; - union rss_hash_mask_reg_u rss_hash_mask_ipv6 = {0}; - union rss_hash_seed_reg_u rss_hash_seed_ipv6 = {0}; - union rss_hash_mix_reg_u rss_hash_mix_ipv6[11] = {0}; - union rss_hash_fin_reg_u rss_hash_fin_ipv6[5] = {0}; - union rss_hash_mask_ipv4_reg_u rss_hash_mask_ipv4 = {0}; - union rss_hash_seed_ipv4_reg_u rss_hash_seed_ipv4 = {0}; - union rss_hash_mix_ipv4_reg_u rss_hash_mix_ipv4[5] = {0}; - union rss_hash_fin_ipv4_reg_u rss_hash_fin_ipv4[5] = {0}; - - ADPT_DEV_ID_CHECK(dev_id); - - if (mode == FAL_RSS_HASH_IPV4V6 || mode == FAL_RSS_HASH_IPV4ONLY) - { - rss_hash_mask_ipv4.bf.mask = config->hash_mask & 0x1fffff; - rss_hash_mask_ipv4.bf.fragment = config->hash_fragment_mode; - - rss_hash_seed_ipv4.bf.seed = config->hash_seed; - - rss_hash_mix_ipv4[0].bf.hash_mix = config->hash_sip_mix & 0x1f; - rss_hash_mix_ipv4[1].bf.hash_mix = config->hash_dip_mix & 0x1f; - rss_hash_mix_ipv4[2].bf.hash_mix = config->hash_protocol_mix & 0x1f; - rss_hash_mix_ipv4[3].bf.hash_mix = config->hash_dport_mix & 0x1f; - rss_hash_mix_ipv4[4].bf.hash_mix = config->hash_sport_mix & 0x1f; - - rss_hash_fin_ipv4[0].bf.fin_inner = config->hash_fin_inner & 0x1f; - rss_hash_fin_ipv4[0].bf.fin_outer = config->hash_fin_outer & 0x1f; - rss_hash_fin_ipv4[1].bf.fin_inner = (config->hash_fin_inner >> 0x5) & 0x1f; - rss_hash_fin_ipv4[1].bf.fin_outer = (config->hash_fin_outer >> 0x5) & 0x1f; - rss_hash_fin_ipv4[2].bf.fin_inner = (config->hash_fin_inner >> 0xa) & 0x1f; - rss_hash_fin_ipv4[2].bf.fin_outer = (config->hash_fin_outer >> 0xa) & 0x1f; - rss_hash_fin_ipv4[3].bf.fin_inner = (config->hash_fin_inner >> 0xf) & 0x1f; - rss_hash_fin_ipv4[3].bf.fin_outer = (config->hash_fin_outer >> 0xf) & 0x1f; - rss_hash_fin_ipv4[4].bf.fin_inner = (config->hash_fin_inner >> 0x14) & 0x1f; - rss_hash_fin_ipv4[4].bf.fin_outer = (config->hash_fin_outer >> 0x14) & 0x1f; - - SW_RTN_ON_ERROR(hppe_rss_hash_mask_ipv4_reg_set(dev_id, &rss_hash_mask_ipv4)); - SW_RTN_ON_ERROR(hppe_rss_hash_seed_ipv4_reg_set(dev_id, &rss_hash_seed_ipv4)); - for (index = 0; index < 5; index++) - SW_RTN_ON_ERROR(hppe_rss_hash_mix_ipv4_reg_set(dev_id, index, &rss_hash_mix_ipv4[index])); - for (index = 0; index < 5; index++) - SW_RTN_ON_ERROR(hppe_rss_hash_fin_ipv4_reg_set(dev_id, index, &rss_hash_fin_ipv4[index])); - } - - if (mode == FAL_RSS_HASH_IPV4V6 || mode == FAL_RSS_HASH_IPV6ONLY) - { - rss_hash_mask_ipv6.bf.mask = config->hash_mask & 0x1fffff; - rss_hash_mask_ipv6.bf.fragment = config->hash_fragment_mode; - - rss_hash_seed_ipv6.bf.seed = config->hash_seed; - - rss_hash_mix_ipv6[0].bf.hash_mix = config->hash_sip_mix & 0x1f; - rss_hash_mix_ipv6[1].bf.hash_mix = (config->hash_sip_mix >> 0x5) & 0x1f; - rss_hash_mix_ipv6[2].bf.hash_mix = (config->hash_sip_mix >> 0xa) & 0x1f; - rss_hash_mix_ipv6[3].bf.hash_mix = (config->hash_sip_mix >> 0xf) & 0x1f; - - rss_hash_mix_ipv6[4].bf.hash_mix = config->hash_dip_mix & 0x1f; - rss_hash_mix_ipv6[5].bf.hash_mix = (config->hash_dip_mix >> 0x5) & 0x1f; - rss_hash_mix_ipv6[6].bf.hash_mix = (config->hash_dip_mix >> 0xa) & 0x1f; - rss_hash_mix_ipv6[7].bf.hash_mix = (config->hash_dip_mix >> 0xf) & 0x1f; - - rss_hash_mix_ipv6[8].bf.hash_mix = config->hash_protocol_mix & 0x1f; - rss_hash_mix_ipv6[9].bf.hash_mix = config->hash_dport_mix & 0x1f; - rss_hash_mix_ipv6[10].bf.hash_mix = config->hash_sport_mix & 0x1f; - - rss_hash_fin_ipv6[0].bf.fin_inner = config->hash_fin_inner & 0x1f; - rss_hash_fin_ipv6[0].bf.fin_outer = config->hash_fin_outer & 0x1f; - rss_hash_fin_ipv6[1].bf.fin_inner = (config->hash_fin_inner >> 0x5) & 0x1f; - rss_hash_fin_ipv6[1].bf.fin_outer = (config->hash_fin_outer >> 0x5) & 0x1f; - rss_hash_fin_ipv6[2].bf.fin_inner = (config->hash_fin_inner >> 0xa) & 0x1f; - rss_hash_fin_ipv6[2].bf.fin_outer = (config->hash_fin_outer >> 0xa) & 0x1f; - rss_hash_fin_ipv6[3].bf.fin_inner = (config->hash_fin_inner >> 0xf) & 0x1f; - rss_hash_fin_ipv6[3].bf.fin_outer = (config->hash_fin_outer >> 0xf) & 0x1f; - rss_hash_fin_ipv6[4].bf.fin_inner = (config->hash_fin_inner >> 0x14) & 0x1f; - rss_hash_fin_ipv6[4].bf.fin_outer = (config->hash_fin_outer >> 0x14) & 0x1f; - - SW_RTN_ON_ERROR(hppe_rss_hash_mask_reg_set(dev_id, &rss_hash_mask_ipv6)); - SW_RTN_ON_ERROR(hppe_rss_hash_seed_reg_set(dev_id, &rss_hash_seed_ipv6)); - for (index = 0; index < 11; index++) - SW_RTN_ON_ERROR(hppe_rss_hash_mix_reg_set(dev_id, index, &rss_hash_mix_ipv6[index])); - for (index = 0; index < 5; index++) - SW_RTN_ON_ERROR(hppe_rss_hash_fin_reg_set(dev_id, index, &rss_hash_fin_ipv6[index])); - } - - return SW_OK; -} - -sw_error_t -adpt_hppe_rss_hash_config_get(a_uint32_t dev_id, fal_rss_hash_mode_t mode, - fal_rss_hash_config_t * config) -{ - a_uint32_t index; - union rss_hash_mask_reg_u rss_hash_mask_ipv6 = {0}; - union rss_hash_seed_reg_u rss_hash_seed_ipv6 = {0}; - union rss_hash_mix_reg_u rss_hash_mix_ipv6[11] = {0}; - union rss_hash_fin_reg_u rss_hash_fin_ipv6[5] = {0}; - union rss_hash_mask_ipv4_reg_u rss_hash_mask_ipv4 = {0}; - union rss_hash_seed_ipv4_reg_u rss_hash_seed_ipv4 = {0}; - union rss_hash_mix_ipv4_reg_u rss_hash_mix_ipv4[5] = {0}; - union rss_hash_fin_ipv4_reg_u rss_hash_fin_ipv4[5] = {0}; - - ADPT_DEV_ID_CHECK(dev_id); - - SW_RTN_ON_ERROR(hppe_rss_hash_mask_ipv4_reg_get(dev_id, &rss_hash_mask_ipv4)); - SW_RTN_ON_ERROR(hppe_rss_hash_seed_ipv4_reg_get(dev_id, &rss_hash_seed_ipv4)); - for (index = 0; index < 5; index++) - SW_RTN_ON_ERROR(hppe_rss_hash_mix_ipv4_reg_get(dev_id, index, &rss_hash_mix_ipv4[index])); - for (index = 0; index < 5; index++) - SW_RTN_ON_ERROR(hppe_rss_hash_fin_ipv4_reg_get(dev_id, index, &rss_hash_fin_ipv4[index])); - - SW_RTN_ON_ERROR(hppe_rss_hash_mask_reg_get(dev_id, &rss_hash_mask_ipv6)); - SW_RTN_ON_ERROR(hppe_rss_hash_seed_reg_get(dev_id, &rss_hash_seed_ipv6)); - for (index = 0; index < 11; index++) - SW_RTN_ON_ERROR(hppe_rss_hash_mix_reg_get(dev_id, index, &rss_hash_mix_ipv6[index])); - for (index = 0; index < 5; index++) - SW_RTN_ON_ERROR(hppe_rss_hash_fin_reg_get(dev_id, index, &rss_hash_fin_ipv6[index])); - - if (mode == FAL_RSS_HASH_IPV4ONLY) - { - config->hash_mask = rss_hash_mask_ipv4.bf.mask; - config->hash_fragment_mode = rss_hash_mask_ipv4.bf.fragment; - config->hash_seed = rss_hash_seed_ipv4.bf.seed; - config->hash_sip_mix = rss_hash_mix_ipv4[0].bf.hash_mix; - config->hash_dip_mix = rss_hash_mix_ipv4[1].bf.hash_mix; - config->hash_protocol_mix = rss_hash_mix_ipv4[2].bf.hash_mix; - config->hash_dport_mix = rss_hash_mix_ipv4[3].bf.hash_mix; - config->hash_sport_mix = rss_hash_mix_ipv4[4].bf.hash_mix; - config->hash_fin_inner = rss_hash_fin_ipv4[0].bf.fin_inner + - (rss_hash_fin_ipv4[1].bf.fin_inner << 0x5) + - (rss_hash_fin_ipv4[2].bf.fin_inner << 0xa) + - (rss_hash_fin_ipv4[3].bf.fin_inner << 0xf) + - (rss_hash_fin_ipv4[4].bf.fin_inner << 0x14); - config->hash_fin_outer = rss_hash_fin_ipv4[0].bf.fin_outer + - (rss_hash_fin_ipv4[1].bf.fin_outer << 0x5) + - (rss_hash_fin_ipv4[2].bf.fin_outer << 0xa) + - (rss_hash_fin_ipv4[3].bf.fin_outer << 0xf) + - (rss_hash_fin_ipv4[4].bf.fin_outer << 0x14); - } - else if (mode == FAL_RSS_HASH_IPV6ONLY) - { - config->hash_mask = rss_hash_mask_ipv6.bf.mask; - config->hash_fragment_mode = rss_hash_mask_ipv6.bf.fragment; - config->hash_seed = rss_hash_seed_ipv6.bf.seed; - config->hash_sip_mix = rss_hash_mix_ipv6[0].bf.hash_mix + - (rss_hash_mix_ipv6[1].bf.hash_mix << 0x5) + - (rss_hash_mix_ipv6[2].bf.hash_mix << 0xa) + - (rss_hash_mix_ipv6[3].bf.hash_mix << 0xf); - config->hash_dip_mix = rss_hash_mix_ipv6[4].bf.hash_mix + - (rss_hash_mix_ipv6[5].bf.hash_mix << 0x5) + - (rss_hash_mix_ipv6[6].bf.hash_mix << 0xa) + - (rss_hash_mix_ipv6[7].bf.hash_mix << 0xf); - config->hash_protocol_mix = rss_hash_mix_ipv6[8].bf.hash_mix; - config->hash_dport_mix = rss_hash_mix_ipv6[9].bf.hash_mix; - config->hash_sport_mix = rss_hash_mix_ipv6[10].bf.hash_mix; - config->hash_fin_inner = rss_hash_fin_ipv6[0].bf.fin_inner + - (rss_hash_fin_ipv6[1].bf.fin_inner << 0x5) + - (rss_hash_fin_ipv6[2].bf.fin_inner << 0xa) + - (rss_hash_fin_ipv6[3].bf.fin_inner << 0xf) + - (rss_hash_fin_ipv6[4].bf.fin_inner << 0x14); - config->hash_fin_outer = rss_hash_fin_ipv6[0].bf.fin_outer + - (rss_hash_fin_ipv6[1].bf.fin_outer << 0x5) + - (rss_hash_fin_ipv6[2].bf.fin_outer << 0xa) + - (rss_hash_fin_ipv6[3].bf.fin_outer << 0xf) + - (rss_hash_fin_ipv6[4].bf.fin_outer << 0x14); - } - else - { - if ((rss_hash_mask_ipv4.bf.mask == rss_hash_mask_ipv6.bf.mask) && - (rss_hash_mask_ipv4.bf.fragment == rss_hash_mask_ipv6.bf.fragment) && - (rss_hash_seed_ipv4.bf.seed == rss_hash_seed_ipv6.bf.seed) && - (rss_hash_mix_ipv4[0].bf.hash_mix == rss_hash_mix_ipv6[0].bf.hash_mix) && - (rss_hash_mix_ipv4[1].bf.hash_mix == rss_hash_mix_ipv6[4].bf.hash_mix) && - (rss_hash_mix_ipv4[2].bf.hash_mix == rss_hash_mix_ipv6[8].bf.hash_mix) && - (rss_hash_mix_ipv4[3].bf.hash_mix == rss_hash_mix_ipv6[9].bf.hash_mix) && - (rss_hash_mix_ipv4[4].bf.hash_mix == rss_hash_mix_ipv6[10].bf.hash_mix) && - (rss_hash_fin_ipv4[0].bf.fin_inner == rss_hash_fin_ipv6[0].bf.fin_inner) && - (rss_hash_fin_ipv4[1].bf.fin_inner == rss_hash_fin_ipv6[1].bf.fin_inner) && - (rss_hash_fin_ipv4[2].bf.fin_inner == rss_hash_fin_ipv6[2].bf.fin_inner) && - (rss_hash_fin_ipv4[3].bf.fin_inner == rss_hash_fin_ipv6[3].bf.fin_inner) && - (rss_hash_fin_ipv4[4].bf.fin_inner == rss_hash_fin_ipv6[4].bf.fin_inner) && - (rss_hash_fin_ipv4[0].bf.fin_outer == rss_hash_fin_ipv6[0].bf.fin_outer) && - (rss_hash_fin_ipv4[1].bf.fin_outer == rss_hash_fin_ipv6[1].bf.fin_outer) && - (rss_hash_fin_ipv4[2].bf.fin_outer == rss_hash_fin_ipv6[2].bf.fin_outer) && - (rss_hash_fin_ipv4[3].bf.fin_outer == rss_hash_fin_ipv6[3].bf.fin_outer) && - (rss_hash_fin_ipv4[4].bf.fin_outer == rss_hash_fin_ipv6[4].bf.fin_outer)) - { - config->hash_mask = rss_hash_mask_ipv6.bf.mask; - config->hash_fragment_mode = rss_hash_mask_ipv6.bf.fragment; - config->hash_seed = rss_hash_seed_ipv6.bf.seed; - config->hash_sip_mix = rss_hash_mix_ipv6[0].bf.hash_mix + - (rss_hash_mix_ipv6[1].bf.hash_mix << 0x5) + - (rss_hash_mix_ipv6[2].bf.hash_mix << 0xa) + - (rss_hash_mix_ipv6[3].bf.hash_mix << 0xf); - config->hash_dip_mix = rss_hash_mix_ipv6[4].bf.hash_mix + - (rss_hash_mix_ipv6[5].bf.hash_mix << 0x5) + - (rss_hash_mix_ipv6[6].bf.hash_mix << 0xa) + - (rss_hash_mix_ipv6[7].bf.hash_mix << 0xf); - config->hash_protocol_mix = rss_hash_mix_ipv6[8].bf.hash_mix; - config->hash_dport_mix = rss_hash_mix_ipv6[9].bf.hash_mix; - config->hash_sport_mix = rss_hash_mix_ipv6[10].bf.hash_mix; - config->hash_fin_inner = rss_hash_fin_ipv6[0].bf.fin_inner + - (rss_hash_fin_ipv6[1].bf.fin_inner << 0x5) + - (rss_hash_fin_ipv6[2].bf.fin_inner << 0xa) + - (rss_hash_fin_ipv6[3].bf.fin_inner << 0xf) + - (rss_hash_fin_ipv6[4].bf.fin_inner << 0x14); - config->hash_fin_outer = rss_hash_fin_ipv6[0].bf.fin_outer + - (rss_hash_fin_ipv6[1].bf.fin_outer << 0x5) + - (rss_hash_fin_ipv6[2].bf.fin_outer << 0xa) + - (rss_hash_fin_ipv6[3].bf.fin_outer << 0xf) + - (rss_hash_fin_ipv6[4].bf.fin_outer << 0x14); - } - else - return SW_FAIL; - } - - return SW_OK; -} - -void adpt_hppe_rss_hash_func_bitmap_init(a_uint32_t dev_id) -{ - adpt_api_t *p_adpt_api = NULL; - - p_adpt_api = adpt_api_ptr_get(dev_id); - - if(p_adpt_api == NULL) - return; - - p_adpt_api->adpt_rss_hash_func_bitmap = ((1 << FUNC_RSS_HASH_CONFIG_SET) | - (1 << FUNC_RSS_HASH_CONFIG_GET)); - - return; -} - -static void adpt_hppe_rss_hash_func_unregister(a_uint32_t dev_id, adpt_api_t *p_adpt_api) -{ - if(p_adpt_api == NULL) - return; - - p_adpt_api->adpt_rss_hash_config_set = NULL; - p_adpt_api->adpt_rss_hash_config_get = NULL; - - return; -} - -sw_error_t adpt_hppe_rss_hash_init(a_uint32_t dev_id) -{ - adpt_api_t *p_adpt_api = NULL; - - p_adpt_api = adpt_api_ptr_get(dev_id); - - if(p_adpt_api == NULL) - return SW_FAIL; - - adpt_hppe_rss_hash_func_unregister(dev_id, p_adpt_api); - - if(p_adpt_api->adpt_rss_hash_func_bitmap & (1<adpt_rss_hash_config_set = adpt_hppe_rss_hash_config_set; - if(p_adpt_api->adpt_rss_hash_func_bitmap & (1<adpt_rss_hash_config_get = adpt_hppe_rss_hash_config_get; - - return SW_OK; -} - -/** - * @} - */ - - diff --git a/feeds/ipq807x/qca-ssdk/src/src/adpt/hppe/adpt_hppe_sec.c b/feeds/ipq807x/qca-ssdk/src/src/adpt/hppe/adpt_hppe_sec.c deleted file mode 100755 index e8f599117..000000000 --- a/feeds/ipq807x/qca-ssdk/src/src/adpt/hppe/adpt_hppe_sec.c +++ /dev/null @@ -1,261 +0,0 @@ -/* - * Copyright (c) 2016-2017, The Linux Foundation. All rights reserved. - * Permission to use, copy, modify, and/or distribute this software for - * any purpose with or without fee is hereby granted, provided that the - * above copyright notice and this permission notice appear in all copies. - * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES - * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR - * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES - * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN - * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT - * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. - */ - - -/** - * @defgroup - * @{ - */ -#include "sw.h" -#include "fal_sec.h" -#include "hppe_sec_reg.h" -#include "hppe_sec.h" -#include "adpt.h" - -sw_error_t -adpt_hppe_sec_l3_excep_parser_ctrl_set(a_uint32_t dev_id, fal_l3_excep_parser_ctrl *ctrl) -{ - union l3_exception_parsing_ctrl_reg_u l3_exception_parsing_ctrl; - - ADPT_DEV_ID_CHECK(dev_id); - ADPT_NULL_POINT_CHECK(ctrl); - - memset(&l3_exception_parsing_ctrl, 0, sizeof(l3_exception_parsing_ctrl)); - - l3_exception_parsing_ctrl.bf.small_ttl = ctrl->small_ip4ttl; - l3_exception_parsing_ctrl.bf.small_hop_limit = ctrl->small_ip6hoplimit; - - return hppe_l3_exception_parsing_ctrl_reg_set(dev_id, &l3_exception_parsing_ctrl); -} -sw_error_t -adpt_hppe_sec_l3_excep_ctrl_get(a_uint32_t dev_id, a_uint32_t excep_type, fal_l3_excep_ctrl_t *ctrl) -{ - union l3_exception_cmd_u l3_exception_cmd; - union l3_exp_l3_only_ctrl_u l3_only_ctrl; - union l3_exp_l2_only_ctrl_u l2_only_ctrl; - union l3_exp_l2_flow_ctrl_u l2_flow_ctrl; - union l3_exp_l3_flow_ctrl_u l3_flow_ctrl; - union l3_exp_multicast_ctrl_u multicast_ctrl; - - ADPT_DEV_ID_CHECK(dev_id); - ADPT_NULL_POINT_CHECK(ctrl); - if (excep_type >= L3_EXCEPTION_CMD_MAX_ENTRY) - return SW_BAD_VALUE; - - hppe_l3_exception_cmd_get(dev_id, excep_type, &l3_exception_cmd); - hppe_l3_exp_l3_only_ctrl_get(dev_id, excep_type, &l3_only_ctrl); - hppe_l3_exp_l2_only_ctrl_get(dev_id, excep_type, &l2_only_ctrl); - hppe_l3_exp_l3_flow_ctrl_get(dev_id, excep_type, &l3_flow_ctrl); - hppe_l3_exp_l2_flow_ctrl_get(dev_id, excep_type, &l2_flow_ctrl); - hppe_l3_exp_multicast_ctrl_get(dev_id, excep_type, &multicast_ctrl); - - ctrl->cmd = l3_exception_cmd.bf.l3_excep_cmd; - ctrl->deacclr_en = l3_exception_cmd.bf.de_acce; - ctrl->l3route_only_en = l3_only_ctrl.bf.excep_en; - ctrl->l2fwd_only_en = l2_only_ctrl.bf.excep_en; - ctrl->l3flow_en = l3_flow_ctrl.bf.excep_en; - ctrl->l2flow_en = l2_flow_ctrl.bf.excep_en; - ctrl->multicast_en = multicast_ctrl.bf.excep_en; - - return SW_OK; -} - -sw_error_t -adpt_hppe_sec_l3_excep_parser_ctrl_get(a_uint32_t dev_id, fal_l3_excep_parser_ctrl *ctrl) -{ - sw_error_t rv = SW_OK; - union l3_exception_parsing_ctrl_reg_u l3_exception_parsing_ctrl; - - ADPT_DEV_ID_CHECK(dev_id); - ADPT_NULL_POINT_CHECK(ctrl); - - rv = hppe_l3_exception_parsing_ctrl_reg_get(dev_id, &l3_exception_parsing_ctrl); - if( rv != SW_OK ) - return rv; - - ctrl->small_ip4ttl = l3_exception_parsing_ctrl.bf.small_ttl; - ctrl->small_ip6hoplimit = l3_exception_parsing_ctrl.bf.small_hop_limit; - - return SW_OK; -} - -sw_error_t -adpt_hppe_sec_l4_excep_parser_ctrl_set(a_uint32_t dev_id, fal_l4_excep_parser_ctrl *ctrl) -{ - union l4_exception_parsing_ctrl_0_reg_u l4_exception_parsing_ctrl_0; - union l4_exception_parsing_ctrl_1_reg_u l4_exception_parsing_ctrl_1; - union l4_exception_parsing_ctrl_2_reg_u l4_exception_parsing_ctrl_2; - union l4_exception_parsing_ctrl_3_reg_u l4_exception_parsing_ctrl_3; - - ADPT_DEV_ID_CHECK(dev_id); - ADPT_NULL_POINT_CHECK(ctrl); - - - l4_exception_parsing_ctrl_0.bf.tcp_flags0 = ctrl->tcp_flags[0]; - l4_exception_parsing_ctrl_0.bf.tcp_flags0_mask = ctrl->tcp_flags_mask[0]; - l4_exception_parsing_ctrl_0.bf.tcp_flags1 = ctrl->tcp_flags[1]; - l4_exception_parsing_ctrl_0.bf.tcp_flags1_mask = ctrl->tcp_flags_mask[1]; - l4_exception_parsing_ctrl_1.bf.tcp_flags2 = ctrl->tcp_flags[2]; - l4_exception_parsing_ctrl_1.bf.tcp_flags2_mask = ctrl->tcp_flags_mask[2]; - l4_exception_parsing_ctrl_1.bf.tcp_flags3 = ctrl->tcp_flags[3]; - l4_exception_parsing_ctrl_1.bf.tcp_flags3_mask = ctrl->tcp_flags_mask[3]; - l4_exception_parsing_ctrl_2.bf.tcp_flags4 = ctrl->tcp_flags[4]; - l4_exception_parsing_ctrl_2.bf.tcp_flags4_mask = ctrl->tcp_flags_mask[4]; - l4_exception_parsing_ctrl_2.bf.tcp_flags5 = ctrl->tcp_flags[5]; - l4_exception_parsing_ctrl_2.bf.tcp_flags5_mask = ctrl->tcp_flags_mask[5]; - l4_exception_parsing_ctrl_3.bf.tcp_flags6 = ctrl->tcp_flags[6]; - l4_exception_parsing_ctrl_3.bf.tcp_flags6_mask = ctrl->tcp_flags_mask[6]; - l4_exception_parsing_ctrl_3.bf.tcp_flags7 = ctrl->tcp_flags[7]; - l4_exception_parsing_ctrl_3.bf.tcp_flags7_mask = ctrl->tcp_flags_mask[7]; - - hppe_l4_exception_parsing_ctrl_0_reg_set(dev_id, &l4_exception_parsing_ctrl_0); - hppe_l4_exception_parsing_ctrl_1_reg_set(dev_id, &l4_exception_parsing_ctrl_1); - hppe_l4_exception_parsing_ctrl_2_reg_set(dev_id, &l4_exception_parsing_ctrl_2); - hppe_l4_exception_parsing_ctrl_3_reg_set(dev_id, &l4_exception_parsing_ctrl_3); - return SW_OK; -} -sw_error_t -adpt_hppe_sec_l3_excep_ctrl_set(a_uint32_t dev_id, a_uint32_t excep_type, fal_l3_excep_ctrl_t *ctrl) -{ - union l3_exception_cmd_u l3_exception_cmd; - union l3_exp_l3_only_ctrl_u l3_only_ctrl; - union l3_exp_l2_only_ctrl_u l2_only_ctrl; - union l3_exp_l2_flow_ctrl_u l2_flow_ctrl; - union l3_exp_l3_flow_ctrl_u l3_flow_ctrl; - union l3_exp_multicast_ctrl_u multicast_ctrl; - - ADPT_DEV_ID_CHECK(dev_id); - ADPT_NULL_POINT_CHECK(ctrl); - if (excep_type >= L3_EXCEPTION_CMD_MAX_ENTRY) - return SW_BAD_VALUE; - - l3_exception_cmd.bf.l3_excep_cmd= ctrl->cmd; - l3_exception_cmd.bf.de_acce= ctrl->deacclr_en; - l3_only_ctrl.bf.excep_en = ctrl->l3route_only_en; - l2_only_ctrl.bf.excep_en = ctrl->l2fwd_only_en; - l3_flow_ctrl.bf.excep_en = ctrl->l3flow_en; - l2_flow_ctrl.bf.excep_en = ctrl->l2flow_en; - multicast_ctrl.bf.excep_en = ctrl->multicast_en; - - hppe_l3_exception_cmd_set(dev_id, excep_type, &l3_exception_cmd); - hppe_l3_exp_l3_only_ctrl_set(dev_id, excep_type, &l3_only_ctrl); - hppe_l3_exp_l2_only_ctrl_set(dev_id, excep_type, &l2_only_ctrl); - hppe_l3_exp_l3_flow_ctrl_set(dev_id, excep_type, &l3_flow_ctrl); - hppe_l3_exp_l2_flow_ctrl_set(dev_id, excep_type, &l2_flow_ctrl); - hppe_l3_exp_multicast_ctrl_set(dev_id, excep_type, &multicast_ctrl); - - return SW_OK; -} - -sw_error_t -adpt_hppe_sec_l4_excep_parser_ctrl_get(a_uint32_t dev_id, fal_l4_excep_parser_ctrl *ctrl) -{ - union l4_exception_parsing_ctrl_0_reg_u l4_exception_parsing_ctrl_0; - union l4_exception_parsing_ctrl_1_reg_u l4_exception_parsing_ctrl_1; - union l4_exception_parsing_ctrl_2_reg_u l4_exception_parsing_ctrl_2; - union l4_exception_parsing_ctrl_3_reg_u l4_exception_parsing_ctrl_3; - - ADPT_DEV_ID_CHECK(dev_id); - ADPT_NULL_POINT_CHECK(ctrl); - - hppe_l4_exception_parsing_ctrl_0_reg_get(dev_id, &l4_exception_parsing_ctrl_0); - hppe_l4_exception_parsing_ctrl_1_reg_get(dev_id, &l4_exception_parsing_ctrl_1); - hppe_l4_exception_parsing_ctrl_2_reg_get(dev_id, &l4_exception_parsing_ctrl_2); - hppe_l4_exception_parsing_ctrl_3_reg_get(dev_id, &l4_exception_parsing_ctrl_3); - - ctrl->tcp_flags[0] = l4_exception_parsing_ctrl_0.bf.tcp_flags0; - ctrl->tcp_flags_mask[0] = l4_exception_parsing_ctrl_0.bf.tcp_flags0_mask; - ctrl->tcp_flags[1] = l4_exception_parsing_ctrl_0.bf.tcp_flags1; - ctrl->tcp_flags_mask[1] = l4_exception_parsing_ctrl_0.bf.tcp_flags1_mask; - ctrl->tcp_flags[2] = l4_exception_parsing_ctrl_1.bf.tcp_flags2; - ctrl->tcp_flags_mask[2] = l4_exception_parsing_ctrl_1.bf.tcp_flags2_mask; - ctrl->tcp_flags[3] = l4_exception_parsing_ctrl_1.bf.tcp_flags3; - ctrl->tcp_flags_mask[3] = l4_exception_parsing_ctrl_1.bf.tcp_flags3_mask; - ctrl->tcp_flags[4] = l4_exception_parsing_ctrl_2.bf.tcp_flags4; - ctrl->tcp_flags_mask[4] = l4_exception_parsing_ctrl_2.bf.tcp_flags4_mask; - ctrl->tcp_flags[5] = l4_exception_parsing_ctrl_2.bf.tcp_flags5; - ctrl->tcp_flags_mask[5] = l4_exception_parsing_ctrl_2.bf.tcp_flags5_mask; - ctrl->tcp_flags[6] = l4_exception_parsing_ctrl_3.bf.tcp_flags6; - ctrl->tcp_flags_mask[6] = l4_exception_parsing_ctrl_3.bf.tcp_flags6_mask; - ctrl->tcp_flags[7] = l4_exception_parsing_ctrl_3.bf.tcp_flags7; - ctrl->tcp_flags_mask[7] = l4_exception_parsing_ctrl_3.bf.tcp_flags7_mask; - - return SW_OK; -} - -void adpt_hppe_sec_func_bitmap_init(a_uint32_t dev_id) -{ - adpt_api_t *p_adpt_api = NULL; - - p_adpt_api = adpt_api_ptr_get(dev_id); - - if(p_adpt_api == NULL) - return; - - p_adpt_api->adpt_sec_func_bitmap = ((1 << FUNC_SEC_L3_EXCEP_CTRL_SET) | - (1 << FUNC_SEC_L3_EXCEP_CTRL_GET) | - (1 << FUNC_SEC_L3_EXCEP_PARSER_CTRL_SET) | - (1 << FUNC_SEC_L3_EXCEP_PARSER_CTRL_GET) | - (1 << FUNC_SEC_L4_EXCEP_PARSER_CTRL_SET) | - (1 << FUNC_SEC_L4_EXCEP_PARSER_CTRL_GET)); - - return; -} - -static void adpt_hppe_sec_func_unregister(a_uint32_t dev_id, adpt_api_t *p_adpt_api) -{ - if(p_adpt_api == NULL) - return; - - p_adpt_api->adpt_sec_l3_excep_parser_ctrl_set = NULL; - p_adpt_api->adpt_sec_l3_excep_ctrl_get = NULL; - p_adpt_api->adpt_sec_l3_excep_parser_ctrl_get = NULL; - p_adpt_api->adpt_sec_l4_excep_parser_ctrl_set = NULL; - p_adpt_api->adpt_sec_l3_excep_ctrl_set = NULL; - p_adpt_api->adpt_sec_l4_excep_parser_ctrl_get = NULL; - - return; -} - -sw_error_t adpt_hppe_sec_init(a_uint32_t dev_id) -{ - adpt_api_t *p_adpt_api = NULL; - - p_adpt_api = adpt_api_ptr_get(dev_id); - - if(p_adpt_api == NULL) - return SW_FAIL; - - adpt_hppe_sec_func_unregister(dev_id, p_adpt_api); - - if (p_adpt_api->adpt_sec_func_bitmap & (1 << FUNC_SEC_L3_EXCEP_PARSER_CTRL_SET)) - p_adpt_api->adpt_sec_l3_excep_parser_ctrl_set = adpt_hppe_sec_l3_excep_parser_ctrl_set; - if (p_adpt_api->adpt_sec_func_bitmap & (1 << FUNC_SEC_L3_EXCEP_CTRL_GET)) - p_adpt_api->adpt_sec_l3_excep_ctrl_get = adpt_hppe_sec_l3_excep_ctrl_get; - if (p_adpt_api->adpt_sec_func_bitmap & (1 << FUNC_SEC_L3_EXCEP_PARSER_CTRL_GET)) - p_adpt_api->adpt_sec_l3_excep_parser_ctrl_get = adpt_hppe_sec_l3_excep_parser_ctrl_get; - if (p_adpt_api->adpt_sec_func_bitmap & (1 << FUNC_SEC_L4_EXCEP_PARSER_CTRL_SET)) - p_adpt_api->adpt_sec_l4_excep_parser_ctrl_set = adpt_hppe_sec_l4_excep_parser_ctrl_set; - if (p_adpt_api->adpt_sec_func_bitmap & (1 << FUNC_SEC_L3_EXCEP_CTRL_SET)) - p_adpt_api->adpt_sec_l3_excep_ctrl_set = adpt_hppe_sec_l3_excep_ctrl_set; - if (p_adpt_api->adpt_sec_func_bitmap & (1 << FUNC_SEC_L4_EXCEP_PARSER_CTRL_GET)) - p_adpt_api->adpt_sec_l4_excep_parser_ctrl_get = adpt_hppe_sec_l4_excep_parser_ctrl_get; - - - return SW_OK; -} - -/** - * @} - */ diff --git a/feeds/ipq807x/qca-ssdk/src/src/adpt/hppe/adpt_hppe_servcode.c b/feeds/ipq807x/qca-ssdk/src/src/adpt/hppe/adpt_hppe_servcode.c deleted file mode 100755 index 2696356cb..000000000 --- a/feeds/ipq807x/qca-ssdk/src/src/adpt/hppe/adpt_hppe_servcode.c +++ /dev/null @@ -1,172 +0,0 @@ -/* - * Copyright (c) 2016-2017, The Linux Foundation. All rights reserved. - * Permission to use, copy, modify, and/or distribute this software for - * any purpose with or without fee is hereby granted, provided that the - * above copyright notice and this permission notice appear in all copies. - * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES - * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR - * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES - * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN - * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT - * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. - */ - - -/** - * @defgroup - * @{ - */ -#include "sw.h" -#include "hppe_servcode_reg.h" -#include "hppe_servcode.h" -#include "hppe_fdb_reg.h" -#include "hppe_fdb.h" -#include "adpt.h" - -#define MAX_PHYSICAL_PORT 8 - -sw_error_t adpt_hppe_servcode_config_set(a_uint32_t dev_id, a_uint32_t servcode_index, - fal_servcode_config_t *entry) -{ - union in_l2_service_tbl_u in_l2_service_tbl; - union service_tbl_u service_tbl; - union eg_service_tbl_u eg_service_tbl; - - ADPT_DEV_ID_CHECK(dev_id); - ADPT_NULL_POINT_CHECK(entry); - - if (servcode_index >= IN_L2_SERVICE_TBL_MAX_ENTRY || entry->dest_port_id >= MAX_PHYSICAL_PORT) - return SW_OUT_OF_RANGE; - - in_l2_service_tbl.bf.dst_port_id_valid = entry->dest_port_valid; - in_l2_service_tbl.bf.dst_port_id = entry->dest_port_id; - in_l2_service_tbl.bf.direction = entry->direction; - in_l2_service_tbl.bf.bypass_bitmap = entry->bypass_bitmap[1]; - in_l2_service_tbl.bf.rx_cnt_en = (entry->bypass_bitmap[2] >> 1) & 0x1; - in_l2_service_tbl.bf.tx_cnt_en = (entry->bypass_bitmap[2] >> 3) & 0x1; - SW_RTN_ON_ERROR(hppe_in_l2_service_tbl_set(dev_id, servcode_index, &in_l2_service_tbl)); - - service_tbl.bf.bypass_bitmap = entry->bypass_bitmap[0]; - service_tbl.bf.rx_counting_en = entry->bypass_bitmap[2] & 0x1; - SW_RTN_ON_ERROR(hppe_service_tbl_set(dev_id, servcode_index, &service_tbl)); - - eg_service_tbl.bf.field_update_action = entry->field_update_bitmap; - eg_service_tbl.bf.next_service_code = entry->next_service_code; - eg_service_tbl.bf.hw_services = entry->hw_services; - eg_service_tbl.bf.offset_sel = entry->offset_sel; - eg_service_tbl.bf.tx_counting_en = (entry->bypass_bitmap[2] >> 2) & 0x1; - SW_RTN_ON_ERROR(hppe_eg_service_tbl_set(dev_id, servcode_index, &eg_service_tbl)); - - return SW_OK; -} - -sw_error_t adpt_hppe_servcode_config_get(a_uint32_t dev_id, a_uint32_t servcode_index, - fal_servcode_config_t *entry) -{ - union in_l2_service_tbl_u in_l2_service_tbl; - union service_tbl_u service_tbl; - union eg_service_tbl_u eg_service_tbl; - - ADPT_DEV_ID_CHECK(dev_id); - ADPT_NULL_POINT_CHECK(entry); - - if (servcode_index >= IN_L2_SERVICE_TBL_MAX_ENTRY) - return SW_OUT_OF_RANGE; - - SW_RTN_ON_ERROR(hppe_in_l2_service_tbl_get(dev_id, servcode_index, &in_l2_service_tbl)); - entry->dest_port_valid = in_l2_service_tbl.bf.dst_port_id_valid; - entry->dest_port_id = in_l2_service_tbl.bf.dst_port_id; - entry->direction = in_l2_service_tbl.bf.direction; - entry->bypass_bitmap[1] = in_l2_service_tbl.bf.bypass_bitmap; - entry->bypass_bitmap[2] |= in_l2_service_tbl.bf.rx_cnt_en << 1; - entry->bypass_bitmap[2] |= in_l2_service_tbl.bf.tx_cnt_en << 3; - - SW_RTN_ON_ERROR(hppe_service_tbl_get(dev_id, servcode_index, &service_tbl)); - entry->bypass_bitmap[0] = service_tbl.bf.bypass_bitmap; - entry->bypass_bitmap[2] |= service_tbl.bf.rx_counting_en; - - SW_RTN_ON_ERROR(hppe_eg_service_tbl_get(dev_id, servcode_index, &eg_service_tbl)); - entry->field_update_bitmap = eg_service_tbl.bf.field_update_action; - entry->next_service_code = eg_service_tbl.bf.next_service_code; - entry->hw_services = eg_service_tbl.bf.hw_services; - entry->offset_sel = eg_service_tbl.bf.offset_sel; - entry->bypass_bitmap[2] |= eg_service_tbl.bf.tx_counting_en << 2; - - return SW_OK; -} - -sw_error_t adpt_hppe_servcode_loopcheck_en(a_uint32_t dev_id, a_bool_t enable) -{ - ADPT_DEV_ID_CHECK(dev_id); -#ifndef IN_FDB_MINI - SW_RTN_ON_ERROR(hppe_l2_global_conf_service_code_loop_set(dev_id, enable)); -#endif - return SW_OK; -} - -sw_error_t adpt_hppe_servcode_loopcheck_status_get(a_uint32_t dev_id, a_bool_t *enable) -{ - ADPT_DEV_ID_CHECK(dev_id); - ADPT_NULL_POINT_CHECK(enable); -#ifndef IN_FDB_MINI - SW_RTN_ON_ERROR(hppe_l2_global_conf_service_code_loop_get(dev_id, enable)); -#endif - return SW_OK; -} - -void adpt_hppe_servcode_func_bitmap_init(a_uint32_t dev_id) -{ - adpt_api_t *p_adpt_api = NULL; - - p_adpt_api = adpt_api_ptr_get(dev_id); - - if(p_adpt_api == NULL) - return; - - p_adpt_api->adpt_servcode_func_bitmap = 0x0; - - return; -} - -static void adpt_hppe_servcode_func_unregister(a_uint32_t dev_id, adpt_api_t *p_adpt_api) -{ - if(p_adpt_api == NULL) - return; - - p_adpt_api->adpt_servcode_config_set = NULL; - p_adpt_api->adpt_servcode_config_get = NULL; - p_adpt_api->adpt_servcode_loopcheck_en = NULL; - p_adpt_api->adpt_servcode_loopcheck_status_get = NULL; - - return; -} - -sw_error_t adpt_hppe_servcode_init(a_uint32_t dev_id) -{ - adpt_api_t *p_adpt_api = NULL; - - p_adpt_api = adpt_api_ptr_get(dev_id); - - if(p_adpt_api == NULL) - return SW_FAIL; - - adpt_hppe_servcode_func_unregister(dev_id, p_adpt_api); - - if(p_adpt_api->adpt_servcode_func_bitmap & (1<adpt_servcode_config_set = adpt_hppe_servcode_config_set; - if(p_adpt_api->adpt_servcode_func_bitmap & (1<adpt_servcode_config_get = adpt_hppe_servcode_config_get; - if(p_adpt_api->adpt_servcode_func_bitmap & (1<adpt_servcode_loopcheck_en = adpt_hppe_servcode_loopcheck_en; - if(p_adpt_api->adpt_servcode_func_bitmap & (1<adpt_servcode_loopcheck_status_get = adpt_hppe_servcode_loopcheck_status_get; - - return SW_OK; -} - -/** - * @} - */ - - diff --git a/feeds/ipq807x/qca-ssdk/src/src/adpt/hppe/adpt_hppe_shaper.c b/feeds/ipq807x/qca-ssdk/src/src/adpt/hppe/adpt_hppe_shaper.c deleted file mode 100755 index af88d165e..000000000 --- a/feeds/ipq807x/qca-ssdk/src/src/adpt/hppe/adpt_hppe_shaper.c +++ /dev/null @@ -1,1591 +0,0 @@ -/* - * Copyright (c) 2016-2017, The Linux Foundation. All rights reserved. - * Permission to use, copy, modify, and/or distribute this software for - * any purpose with or without fee is hereby granted, provided that the - * above copyright notice and this permission notice appear in all copies. - * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES - * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR - * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES - * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN - * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT - * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. - */ - - -/** - * @defgroup - * @{ - */ -#include "sw.h" -#include "hppe_shaper_reg.h" -#include "hppe_shaper.h" -#include "adpt.h" - -#define NR_ADPT_HPPE_SHAPER_METER_UNIT 2 -#define NR_ADPT_HPPE_SHAPER_METER_TOKEN_UNIT 8 -#define ADPT_HPPE_SHAPER_METER_UNIT_BYTE 0 -#define ADPT_HPPE_SHAPER_METER_UNIT_FRAME 1 -#define ADPT_HPPE_FREQUENCY 300 /*MHZ*/ -#define ADPT_HPPE_SHAPER_BURST_SIZE_UNIT 65536 -#define ADPT_HPPE_SHAPER_REFRESH_BITS 18 -#define ADPT_HPPE_SHAPER_BUCKET_SIZE_BITS 14 -#define ADPT_HPPE_SHAPER_REFRESH_MAX ((1 << ADPT_HPPE_SHAPER_REFRESH_BITS) - 1) -#define ADPT_HPPE_SHAPER_BUCKET_SIZE_MAX ((1 << ADPT_HPPE_SHAPER_BUCKET_SIZE_BITS) - 1) -#define ADPT_HPPE_PORT_SHAPER 0 -#define ADPT_HPPE_FLOW_SHAPER 1 -#define ADPT_HPPE_QUEUE_SHAPER 2 -#define BYTE_SHAPER_MAX_RATE 10000000 -#define BYTE_SHAPER_MIN_RATE 64 -#define FRAME_SHAPER_MAX_RATE 14881000 -#define FRAME_SHAPER_MIN_RATE 6 - - - -static a_uint32_t hppe_shaper_token_unit[NR_ADPT_HPPE_SHAPER_METER_UNIT] - [NR_ADPT_HPPE_SHAPER_METER_TOKEN_UNIT] = {{2048 * 8, - 512 * 8,128 * 8,32 * 8,8 * 8,2 * 8, 4, 1}, - {2097152,524288,131072,32768,8192,2048,512,128}}; - -typedef struct -{ - a_uint64_t rate_1bit; - a_uint64_t rate_max; -} adpt_hppe_shaper_rate_t; - -typedef struct -{ - a_uint64_t burst_size_1bit; - a_uint64_t burst_size_max; -} adpt_hppe_shaper_burst_size_t; - -static adpt_hppe_shaper_rate_t -hppe_port_shaper_rate[NR_ADPT_HPPE_SHAPER_METER_UNIT][NR_ADPT_HPPE_SHAPER_METER_TOKEN_UNIT] = -{ - /* byte based*/ - { - {0,0}, - {0,0}, - {0,0}, - {0,0}, - {0,0}, - {0,0}, - {0,0}, - {0,0}, - }, - - /*frame based */ - { - {0,0}, - {0,0}, - {0,0}, - {0,0}, - {0,0}, - {0,0}, - {0,0}, - {0,0}, - }, -}; - -static adpt_hppe_shaper_rate_t -hppe_flow_shaper_rate[NR_ADPT_HPPE_SHAPER_METER_UNIT][NR_ADPT_HPPE_SHAPER_METER_TOKEN_UNIT] = -{ - /* byte based*/ - { - {0,0}, - {0,0}, - {0,0}, - {0,0}, - {0,0}, - {0,0}, - {0,0}, - {0,0}, - }, - - /*frame based */ - { - {0,0}, - {0,0}, - {0,0}, - {0,0}, - {0,0}, - {0,0}, - {0,0}, - {0,0}, - }, -}; - -static adpt_hppe_shaper_rate_t -hppe_queue_shaper_rate[NR_ADPT_HPPE_SHAPER_METER_UNIT][NR_ADPT_HPPE_SHAPER_METER_TOKEN_UNIT] = -{ - /* byte based*/ - { - {0,0}, - {0,0}, - {0,0}, - {0,0}, - {0,0}, - {0,0}, - {0,0}, - {0,0}, - }, - - /*frame based */ - { - {0,0}, - {0,0}, - {0,0}, - {0,0}, - {0,0}, - {0,0}, - {0,0}, - {0,0}, - }, -}; - -static adpt_hppe_shaper_burst_size_t -hppe_shaper_burst_size[NR_ADPT_HPPE_SHAPER_METER_UNIT][NR_ADPT_HPPE_SHAPER_METER_TOKEN_UNIT] = -{ - { {0,0}, - {0,0}, - {0,0}, - {0,0}, - {0,0}, - {0,0}, - {0,0}, - {0,0}, - }, - { {0,0}, - {0,0}, - {0,0}, - {0,0}, - {0,0}, - {0,0}, - {0,0}, - {0,0}, - }, -}; - -static sw_error_t -__adpt_hppe_port_shaper_max_rate(a_uint32_t time_slot) -{ - a_uint32_t i = 0, j = 0; - a_uint32_t time_cycle; - a_uint64_t temp, temp1,temp2; - - /* time_cycle is ns*/ - time_cycle = ( time_slot * 8); - - for (j = 0; j < 8; j++) - { - /*max rate unit is bps*/ - temp1 = (a_uint64_t)(ADPT_HPPE_SHAPER_REFRESH_MAX * 1000 * 8) * (a_uint64_t)(ADPT_HPPE_FREQUENCY * 1000); - temp2 = hppe_shaper_token_unit[i][j] * time_cycle; - - do_div(temp1, temp2); - hppe_port_shaper_rate[i][j].rate_max = temp1; - - temp = temp1; - do_div(temp, ADPT_HPPE_SHAPER_REFRESH_MAX); - hppe_port_shaper_rate[i][j].rate_1bit = temp; - - //printk("port shaper hppe_max_rate generating =%llu\n", hppe_port_shaper_rate[i][j].rate_max); - //printk("port shaper byte step rate =%llu\n", hppe_port_shaper_rate[i][j].rate_1bit); - } - - i = i + 1; - for (j = 0; j < 8; j++) - { - /* max rate unit is 1/1000 pps*/ - temp1 = (a_uint64_t)(ADPT_HPPE_SHAPER_REFRESH_MAX * 1000) * 1000 * (a_uint64_t)(ADPT_HPPE_FREQUENCY * 1000); - temp2 = (a_uint64_t)hppe_shaper_token_unit[i][j] * time_cycle; - - do_div(temp1, temp2); - hppe_port_shaper_rate[i][j].rate_max = temp1; - - temp = temp1; - do_div(temp, ADPT_HPPE_SHAPER_REFRESH_MAX); - hppe_port_shaper_rate[i][j].rate_1bit = temp; - - //printk("port shaper hppe_max_rate generating =%llu\n", hppe_port_shaper_rate[i][j].rate_max); - //printk("port shaper frame step rate =%llu\n", hppe_port_shaper_rate[i][j].rate_1bit); - } - - return SW_OK; -} - -static sw_error_t -__adpt_hppe_flow_shaper_max_rate(a_uint32_t time_slot) -{ - a_uint32_t i = 0, j = 0; - a_uint32_t time_cycle; - a_uint64_t temp, temp1,temp2; - - /* time_cycle is ns*/ - time_cycle = ( time_slot * 8); - - for (j = 0; j < 8; j++) - { - /*max rate unit is bps*/ - temp1 = (a_uint64_t)(ADPT_HPPE_SHAPER_REFRESH_MAX * 1000 * 8) * (a_uint64_t)(ADPT_HPPE_FREQUENCY * 1000); - temp2 = hppe_shaper_token_unit[i][j] * time_cycle; - - do_div(temp1, temp2); - hppe_flow_shaper_rate[i][j].rate_max = temp1; - - temp = temp1; - do_div(temp, ADPT_HPPE_SHAPER_REFRESH_MAX); - hppe_flow_shaper_rate[i][j].rate_1bit = temp; - - //printk("flow shaper hppe_max_rate generating =%llu\n", hppe_flow_shaper_rate[i][j].rate_max); - //printk("flow shaper byte step rate =%llu\n", hppe_flow_shaper_rate[i][j].rate_1bit); - } - - i = i + 1; - for (j = 0; j < 8; j++) - { - /* max rate unit is 1/1000 pps*/ - temp1 = (a_uint64_t)(ADPT_HPPE_SHAPER_REFRESH_MAX * 1000) * 1000 * (a_uint64_t)(ADPT_HPPE_FREQUENCY * 1000); - temp2 = (a_uint64_t)hppe_shaper_token_unit[i][j] * time_cycle; - - do_div(temp1, temp2); - hppe_flow_shaper_rate[i][j].rate_max = temp1; - - temp = temp1; - do_div(temp, ADPT_HPPE_SHAPER_REFRESH_MAX); - hppe_flow_shaper_rate[i][j].rate_1bit = temp; - - //printk("flow shaper hppe_max_rate generating =%llu\n", hppe_flow_shaper_rate[i][j].rate_max); - //printk("flow shaper frame step rate =%llu\n", hppe_flow_shaper_rate[i][j].rate_1bit); - } - - return SW_OK; -} - -static sw_error_t -__adpt_hppe_queue_shaper_max_rate(a_uint32_t time_slot) -{ - a_uint32_t i = 0, j = 0; - a_uint32_t time_cycle; - a_uint64_t temp, temp1,temp2; - - - /* time_cycle is ns*/ - time_cycle = ( time_slot * 8) /ADPT_HPPE_FREQUENCY; - - for (j = 0; j < 8; j++) - { - /*max rate unit is bps*/ - temp1 = (a_uint64_t)(ADPT_HPPE_SHAPER_REFRESH_MAX * 1000 * 8) * 1000; - temp2 = hppe_shaper_token_unit[i][j] * time_cycle; - - do_div(temp1, temp2); - hppe_queue_shaper_rate[i][j].rate_max = temp1; - - temp = temp1; - do_div(temp, ADPT_HPPE_SHAPER_REFRESH_MAX); - hppe_queue_shaper_rate[i][j].rate_1bit = temp; - - //printk("queue shaper hppe_max_rate generating =%llu\n", hppe_queue_shaper_rate[i][j].rate_max); - //printk("queue shaper byte step rate =%llu\n", hppe_queue_shaper_rate[i][j].rate_1bit); - } - - i = i + 1; - for (j = 0; j < 8; j++) - { - /* max rate unit is 1/1000 pps*/ - temp1 = (a_uint64_t)(ADPT_HPPE_SHAPER_REFRESH_MAX * 1000) * 1000 * 1000; - temp2 = (a_uint64_t)hppe_shaper_token_unit[i][j] * time_cycle; - - do_div(temp1, temp2); - hppe_queue_shaper_rate[i][j].rate_max = temp1; - - temp = temp1; - do_div(temp, ADPT_HPPE_SHAPER_REFRESH_MAX); - hppe_queue_shaper_rate[i][j].rate_1bit = temp; - - //printk("queue shaper hppe_max_rate generating =%llu\n", hppe_queue_shaper_rate[i][j].rate_max); - //printk("queue shaper frame step rate =%llu\n", hppe_queue_shaper_rate[i][j].rate_1bit); - } - - return SW_OK; -} - -static sw_error_t -__adpt_hppe_shaper_max_burst_size(void) -{ - a_uint32_t i = 0, j = 0; - a_uint64_t temp = 0, temp1 = 0; - - for (j = 0; j < 8; j++) - { - /*max size unit is 1/1000 byte based*/ - temp = (a_uint64_t)(ADPT_HPPE_SHAPER_BURST_SIZE_UNIT * ADPT_HPPE_SHAPER_BUCKET_SIZE_MAX); - do_div(temp, hppe_shaper_token_unit[i][j]); - hppe_shaper_burst_size[i][j].burst_size_max = (a_uint64_t)(temp * 1000); - - temp1 = hppe_shaper_burst_size[i][j].burst_size_max; - do_div(temp1, ADPT_HPPE_SHAPER_BUCKET_SIZE_MAX); - hppe_shaper_burst_size[i][j].burst_size_1bit = temp1; - - //printk("shpaer byte hppe_max_burst_size generating =%llu\n", hppe_shaper_burst_size[i][j].burst_size_max); - //printk("shpaer byte hppe_max_burst_size step =%llu\n", hppe_shaper_burst_size[i][j].burst_size_1bit); - } - - i = i + 1; - for (j = 0; j < 8; j++) - { - /* max size unit is 1/1000 frame based */ - temp = (a_uint64_t)(ADPT_HPPE_SHAPER_BURST_SIZE_UNIT * ADPT_HPPE_SHAPER_BUCKET_SIZE_MAX); - do_div(temp, hppe_shaper_token_unit[i][j]); - hppe_shaper_burst_size[i][j].burst_size_max = (a_uint64_t)(temp * 1000); - - temp1 = hppe_shaper_burst_size[i][j].burst_size_max; - do_div(temp1, ADPT_HPPE_SHAPER_BUCKET_SIZE_MAX); - hppe_shaper_burst_size[i][j].burst_size_1bit = temp1; - - //printk("shaper frame hppe_max_burst_size generating =%llu\n", hppe_shaper_burst_size[i][j].burst_size_max); - //printk("shpaer frame hppe_max_burst_size step =%llu\n", hppe_shaper_burst_size[i][j].burst_size_1bit); - } - - return SW_OK; -} - -static sw_error_t -__adpt_hppe_shaper_one_bucket_parameter_select(a_uint32_t shaper_type, - a_uint64_t c_rate, - a_uint64_t c_burst_size, - a_uint32_t meter_unit, - a_uint32_t *token_unit) -{ - a_uint32_t temp_token_unit = 0; - a_uint32_t match = A_FALSE; - a_uint64_t max_rate =0; - - for (temp_token_unit = 0; temp_token_unit < 8; temp_token_unit++) - { - if (ADPT_HPPE_PORT_SHAPER == shaper_type) - max_rate = hppe_port_shaper_rate[meter_unit][temp_token_unit].rate_max; - - if (ADPT_HPPE_FLOW_SHAPER == shaper_type) - max_rate = hppe_flow_shaper_rate[meter_unit][temp_token_unit].rate_max; - - if (ADPT_HPPE_QUEUE_SHAPER == shaper_type) - max_rate = hppe_queue_shaper_rate[meter_unit][temp_token_unit].rate_max; - - if (c_rate > max_rate) - { - continue; - } - else if (c_burst_size <= hppe_shaper_burst_size[meter_unit][temp_token_unit].burst_size_max) - { - *token_unit = temp_token_unit; - match = A_TRUE; - break; - } - } - - if (match == A_FALSE) - { - printk("Not match shaper C token bucket parameter rate configuration\n"); - return SW_BAD_PARAM; - } - - return SW_OK; -} - -static sw_error_t -__adpt_hppe_shaper_two_bucket_parameter_select(a_uint32_t shaper_type, - a_uint64_t c_rate, - a_uint64_t c_burst_size, - a_uint64_t e_rate, - a_uint64_t e_burst_size, - a_uint32_t meter_unit, - a_uint32_t *token_unit) -{ - a_uint32_t temp_token_unit; - a_uint32_t match = A_FALSE; - a_uint64_t max_rate = 0, temp_rate = 0, temp_burst_size = 0; - - if(c_rate > e_rate) - temp_rate = c_rate; - else - temp_rate = e_rate; - - if(c_burst_size > e_burst_size) - temp_burst_size = c_burst_size; - else - temp_burst_size = e_burst_size; - - for (temp_token_unit = 0; temp_token_unit < 8; temp_token_unit++) - { - if (ADPT_HPPE_PORT_SHAPER == shaper_type) - max_rate = hppe_port_shaper_rate[meter_unit][temp_token_unit].rate_max; - - if (ADPT_HPPE_FLOW_SHAPER == shaper_type) - max_rate = hppe_flow_shaper_rate[meter_unit][temp_token_unit].rate_max; - - if (ADPT_HPPE_QUEUE_SHAPER == shaper_type) - max_rate = hppe_queue_shaper_rate[meter_unit][temp_token_unit].rate_max; - - if (temp_rate > max_rate) - { - continue; - } - else if(temp_burst_size <= hppe_shaper_burst_size[meter_unit][temp_token_unit].burst_size_max) - { - *token_unit = temp_token_unit; - match = A_TRUE; - break; - } - } - - if (match == A_FALSE) - { - printk("Not match shaper C and E token bucket parameter rate configuration \n"); - return SW_BAD_PARAM; - } - - return SW_OK; -} - -static sw_error_t -__adpt_hppe_shaper_rate_to_refresh(a_uint32_t shaper_type, - a_uint32_t rate, - a_uint32_t *refresh, - a_bool_t meter_unit, - a_uint32_t token_unit) -{ - a_uint32_t temp_refresh; - a_uint64_t temp_rate, temp_rate_1bit; - - temp_rate_1bit = 0; - - if (ADPT_HPPE_PORT_SHAPER == shaper_type) - { - temp_rate_1bit = hppe_port_shaper_rate[meter_unit][token_unit].rate_1bit; - } - - if (ADPT_HPPE_FLOW_SHAPER == shaper_type) - { - temp_rate_1bit = hppe_flow_shaper_rate[meter_unit][token_unit].rate_1bit; - } - - if (ADPT_HPPE_QUEUE_SHAPER == shaper_type) - { - temp_rate_1bit = hppe_queue_shaper_rate[meter_unit][token_unit].rate_1bit; - } - - if(temp_rate_1bit > 0) - { - temp_rate = ((a_uint64_t)rate) * 1000; - do_div(temp_rate, temp_rate_1bit); - temp_refresh = temp_rate; - } - else - { - return SW_BAD_PARAM; - } - - if (temp_refresh > ADPT_HPPE_SHAPER_REFRESH_MAX) - { - temp_refresh = ADPT_HPPE_SHAPER_REFRESH_MAX; - } - - *refresh = temp_refresh; - - return SW_OK; -} - -static sw_error_t -__adpt_hppe_shaper_burst_size_to_bucket_size(a_uint32_t burst_size, - a_uint32_t *bucket_size, - a_bool_t meter_unit, - a_uint32_t token_unit) -{ - a_uint32_t temp_bucket_size; - a_uint64_t temp_burst_size; - - if(hppe_shaper_burst_size[meter_unit][token_unit].burst_size_1bit > 0) - { - temp_burst_size = ((a_uint64_t)burst_size) * 1000; - do_div(temp_burst_size, hppe_shaper_burst_size[meter_unit][token_unit].burst_size_1bit); - temp_bucket_size = temp_burst_size; - } - else - { - return SW_BAD_PARAM; - } - - if(temp_bucket_size > ADPT_HPPE_SHAPER_BUCKET_SIZE_MAX) - { - temp_bucket_size = ADPT_HPPE_SHAPER_BUCKET_SIZE_MAX; - } - - *bucket_size = temp_bucket_size; - - return SW_OK; -} - -static sw_error_t -__adpt_hppe_shaper_refresh_to_rate(a_uint32_t shaper_type, - a_uint32_t refresh, - a_uint32_t *rate, - a_bool_t meter_unit, - a_uint32_t token_unit) -{ - a_uint32_t temp_rate; - a_uint64_t temp_refresh, temp_rate_1bit; - - temp_rate_1bit = 0; - - if (ADPT_HPPE_PORT_SHAPER == shaper_type) - { - temp_rate_1bit = hppe_port_shaper_rate[meter_unit][token_unit].rate_1bit; - } - - if (ADPT_HPPE_FLOW_SHAPER == shaper_type) - { - temp_rate_1bit = hppe_flow_shaper_rate[meter_unit][token_unit].rate_1bit; - } - - if (ADPT_HPPE_QUEUE_SHAPER == shaper_type) - { - temp_rate_1bit = hppe_queue_shaper_rate[meter_unit][token_unit].rate_1bit; - } - - if(temp_rate_1bit > 0) - { - temp_refresh = ((a_uint64_t)refresh) * temp_rate_1bit; - do_div(temp_refresh, 1000); - temp_rate = temp_refresh; - } - else - { - return SW_BAD_PARAM; - } - - *rate = temp_rate; - - return SW_OK; -} -static sw_error_t -__adpt_hppe_shaper_bucket_size_to_burst_size(a_uint32_t bucket_size, - a_uint32_t *burst_size, - a_bool_t meter_unit, - a_uint32_t token_unit) -{ - a_uint32_t temp_burst_size; - a_uint64_t temp_bucket_size; - - if(hppe_shaper_burst_size[meter_unit][token_unit].burst_size_1bit > 0) - { - temp_bucket_size = ((a_uint64_t)bucket_size) * hppe_shaper_burst_size[meter_unit][token_unit].burst_size_1bit; - do_div(temp_bucket_size, 1000); - temp_burst_size = temp_bucket_size; - } - else - { - return SW_BAD_PARAM; - } - - *burst_size = temp_burst_size; - - return SW_OK; -} - -sw_error_t -adpt_hppe_queue_shaper_get(a_uint32_t dev_id, a_uint32_t queue_id, - fal_shaper_config_t * shaper) -{ - sw_error_t rv = SW_OK; - union l0_shp_cfg_tbl_u l0_shp_cfg_tbl; - union l0_comp_cfg_tbl_u l0_comp_cfg_tbl; - a_uint32_t hppe_cir =0, hppe_cbs = 0, hppe_eir = 0, hppe_ebs = 0; - - memset(&l0_shp_cfg_tbl, 0, sizeof(l0_shp_cfg_tbl)); - memset(&l0_comp_cfg_tbl, 0, sizeof(l0_comp_cfg_tbl)); - ADPT_DEV_ID_CHECK(dev_id); - ADPT_NULL_POINT_CHECK(shaper); - - if ((queue_id < 0) || (queue_id > 299)) - return SW_BAD_PARAM; - - hppe_l0_comp_cfg_tbl_get(dev_id, queue_id, &l0_comp_cfg_tbl); - - - rv = hppe_l0_shp_cfg_tbl_get(dev_id, queue_id, &l0_shp_cfg_tbl); - - if( rv != SW_OK ) - return rv; - - hppe_cir = l0_shp_cfg_tbl.bf.cir; - hppe_cbs = l0_shp_cfg_tbl.bf.cbs; - hppe_eir = l0_shp_cfg_tbl.bf.eir; - hppe_ebs = l0_shp_cfg_tbl.bf.ebs; - - __adpt_hppe_shaper_refresh_to_rate(ADPT_HPPE_QUEUE_SHAPER, - hppe_cir, - &shaper->cir, - l0_shp_cfg_tbl.bf.meter_unit, - l0_shp_cfg_tbl.bf.token_unit); - - __adpt_hppe_shaper_refresh_to_rate(ADPT_HPPE_QUEUE_SHAPER, - hppe_eir, - &shaper->eir, - l0_shp_cfg_tbl.bf.meter_unit, - l0_shp_cfg_tbl.bf.token_unit); - - - __adpt_hppe_shaper_bucket_size_to_burst_size(hppe_cbs, - &shaper->cbs, - l0_shp_cfg_tbl.bf.meter_unit, - l0_shp_cfg_tbl.bf.token_unit); - - __adpt_hppe_shaper_bucket_size_to_burst_size(hppe_ebs, - &shaper->ebs, - l0_shp_cfg_tbl.bf.meter_unit, - l0_shp_cfg_tbl.bf.token_unit); - - - shaper->couple_en = l0_shp_cfg_tbl.bf.cf; - shaper->meter_unit = l0_shp_cfg_tbl.bf.meter_unit; - shaper->c_shaper_en = l0_shp_cfg_tbl.bf.c_shaper_enable; - shaper->e_shaper_en = l0_shp_cfg_tbl.bf.e_shaper_enable; - shaper->shaper_frame_mode = l0_comp_cfg_tbl.bf.shaper_meter_len; - - return SW_OK; -} - -sw_error_t -adpt_hppe_queue_shaper_token_number_set(a_uint32_t dev_id,a_uint32_t queue_id, - fal_shaper_token_number_t *token_number) -{ - union l0_shp_credit_tbl_u l0_shp_credit_tbl; - - memset(&l0_shp_credit_tbl, 0, sizeof(l0_shp_credit_tbl)); - ADPT_DEV_ID_CHECK(dev_id); - ADPT_NULL_POINT_CHECK(token_number); - - if ((queue_id < 0) || (queue_id > 299)) - return SW_BAD_PARAM; - - hppe_l0_shp_credit_tbl_get(dev_id, queue_id, &l0_shp_credit_tbl); - - - l0_shp_credit_tbl.bf.c_shaper_credit_neg = token_number->c_token_number_negative_en; - l0_shp_credit_tbl.bf.c_shaper_credit = token_number->c_token_number; - l0_shp_credit_tbl.bf.e_shaper_credit_neg = token_number->e_token_number_negative_en; - l0_shp_credit_tbl.bf.e_shaper_credit_0 = token_number->e_token_number & 0x1; - l0_shp_credit_tbl.bf.e_shaper_credit_1 = token_number->e_token_number >> 1; - - hppe_l0_shp_credit_tbl_set(dev_id, queue_id, &l0_shp_credit_tbl); - - return SW_OK; -} -#ifndef IN_SHAPER_MINI -sw_error_t -adpt_hppe_port_shaper_get(a_uint32_t dev_id, fal_port_t port_id, - fal_shaper_config_t * shaper) -{ - union psch_shp_cfg_tbl_u psch_shp_cfg_tbl; - union psch_comp_cfg_tbl_u psch_comp_cfg_tbl; - a_uint32_t hppe_cir =0, hppe_cbs = 0; - - memset(&psch_shp_cfg_tbl, 0, sizeof(psch_shp_cfg_tbl)); - memset(&psch_comp_cfg_tbl, 0, sizeof(psch_comp_cfg_tbl)); - ADPT_DEV_ID_CHECK(dev_id); - ADPT_NULL_POINT_CHECK(shaper); - - if (port_id < 0 || port_id > 7) - return SW_BAD_PARAM; - - hppe_psch_shp_cfg_tbl_get(dev_id, port_id, &psch_shp_cfg_tbl); - - hppe_cir = psch_shp_cfg_tbl.bf.cir; - hppe_cbs = psch_shp_cfg_tbl.bf.cbs; - - hppe_psch_comp_cfg_tbl_get(dev_id, port_id, &psch_comp_cfg_tbl); - - - __adpt_hppe_shaper_refresh_to_rate(ADPT_HPPE_PORT_SHAPER, - hppe_cir, - &shaper->cir, - psch_shp_cfg_tbl.bf.meter_unit, - psch_shp_cfg_tbl.bf.token_unit); - - - __adpt_hppe_shaper_bucket_size_to_burst_size(hppe_cbs, - &shaper->cbs, - psch_shp_cfg_tbl.bf.meter_unit, - psch_shp_cfg_tbl.bf.token_unit); - - shaper->meter_unit = psch_shp_cfg_tbl.bf.meter_unit; - shaper->c_shaper_en = psch_shp_cfg_tbl.bf.shaper_enable; - - shaper->shaper_frame_mode = psch_comp_cfg_tbl.bf.shaper_meter_len; - - return SW_OK; -} - -sw_error_t -adpt_hppe_flow_shaper_time_slot_get(a_uint32_t dev_id, a_uint32_t *time_slot) -{ - sw_error_t rv = SW_OK; - union shp_slot_cfg_l1_u shp_slot_cfg_l1; - - memset(&shp_slot_cfg_l1, 0, sizeof(shp_slot_cfg_l1)); - ADPT_DEV_ID_CHECK(dev_id); - ADPT_NULL_POINT_CHECK(time_slot); - - - rv = hppe_shp_slot_cfg_l1_get(dev_id, &shp_slot_cfg_l1); - - if( rv != SW_OK ) - return rv; - - *time_slot = shp_slot_cfg_l1.bf.l1_shp_slot_time; - - return SW_OK; -} - -sw_error_t -adpt_hppe_port_shaper_time_slot_get(a_uint32_t dev_id, a_uint32_t *time_slot) -{ - sw_error_t rv = SW_OK; - union shp_slot_cfg_port_u shp_slot_cfg_port; - - memset(&shp_slot_cfg_port, 0, sizeof(shp_slot_cfg_port)); - ADPT_DEV_ID_CHECK(dev_id); - ADPT_NULL_POINT_CHECK(time_slot); - - rv = hppe_shp_slot_cfg_port_get(dev_id, &shp_slot_cfg_port); - - if( rv != SW_OK ) - return rv; - - *time_slot = shp_slot_cfg_port.bf.port_shp_slot_time; - - return SW_OK; -} -#endif - -sw_error_t -adpt_hppe_flow_shaper_time_slot_set(a_uint32_t dev_id, a_uint32_t time_slot) -{ - union shp_slot_cfg_l1_u shp_slot_cfg_l1; - sw_error_t rv = SW_OK; - - memset(&shp_slot_cfg_l1, 0, sizeof(shp_slot_cfg_l1)); - ADPT_DEV_ID_CHECK(dev_id); - - if ((time_slot < 0x40) || (time_slot > 0xfff)) - return SW_BAD_PARAM; - - rv = hppe_shp_slot_cfg_l1_get(dev_id, &shp_slot_cfg_l1); - - if( rv != SW_OK ) - return rv; - - shp_slot_cfg_l1.bf.l1_shp_slot_time = time_slot; - hppe_shp_slot_cfg_l1_set(dev_id, &shp_slot_cfg_l1); - - __adpt_hppe_flow_shaper_max_rate(time_slot); - - return SW_OK; - -} -sw_error_t -adpt_hppe_port_shaper_token_number_set(a_uint32_t dev_id, fal_port_t port_id, - fal_shaper_token_number_t *token_number) -{ - union psch_shp_credit_tbl_u psch_shp_credit_tbl; - union psch_shp_sign_tbl_u psch_shp_sign_tbl; - - memset(&psch_shp_credit_tbl, 0, sizeof(psch_shp_credit_tbl)); - memset(&psch_shp_sign_tbl, 0, sizeof(psch_shp_sign_tbl)); - ADPT_DEV_ID_CHECK(dev_id); - ADPT_NULL_POINT_CHECK(token_number); - - if (port_id < 0 || port_id > 7) - return SW_BAD_PARAM; - - hppe_psch_shp_credit_tbl_get(dev_id, port_id, &psch_shp_credit_tbl); - hppe_psch_shp_sign_tbl_get(dev_id, port_id, &psch_shp_sign_tbl); - - - psch_shp_sign_tbl.bf.shaper_credit_neg = token_number->c_token_number_negative_en; - - psch_shp_credit_tbl.bf.shaper_credit = token_number->c_token_number; - - hppe_psch_shp_credit_tbl_set(dev_id, port_id, &psch_shp_credit_tbl); - - hppe_psch_shp_sign_tbl_set(dev_id, port_id, &psch_shp_sign_tbl); - - return SW_OK; -} -#ifndef IN_SHAPER_MINI -sw_error_t -adpt_hppe_queue_shaper_token_number_get(a_uint32_t dev_id, a_uint32_t queue_id, - fal_shaper_token_number_t *token_number) -{ - sw_error_t rv = SW_OK; - union l0_shp_credit_tbl_u l0_shp_credit_tbl; - - memset(&l0_shp_credit_tbl, 0, sizeof(l0_shp_credit_tbl)); - ADPT_DEV_ID_CHECK(dev_id); - ADPT_NULL_POINT_CHECK(token_number); - - if ((queue_id < 0) || (queue_id > 299)) - return SW_BAD_PARAM; - - rv = hppe_l0_shp_credit_tbl_get(dev_id, queue_id, &l0_shp_credit_tbl); - - if( rv != SW_OK ) - return rv; - - token_number->c_token_number_negative_en = l0_shp_credit_tbl.bf.c_shaper_credit_neg; - token_number->c_token_number = l0_shp_credit_tbl.bf.c_shaper_credit; - token_number->e_token_number_negative_en = l0_shp_credit_tbl.bf.e_shaper_credit_neg; - token_number->e_token_number = l0_shp_credit_tbl.bf.e_shaper_credit_0 | (l0_shp_credit_tbl.bf.e_shaper_credit_1 << 1); - - - return SW_OK; -} - -sw_error_t -adpt_hppe_queue_shaper_time_slot_get(a_uint32_t dev_id, a_uint32_t *time_slot) -{ - sw_error_t rv = SW_OK; - union shp_slot_cfg_l0_u shp_slot_cfg_l0; - - memset(&shp_slot_cfg_l0, 0, sizeof(shp_slot_cfg_l0)); - ADPT_DEV_ID_CHECK(dev_id); - ADPT_NULL_POINT_CHECK(time_slot); - - - rv = hppe_shp_slot_cfg_l0_get(dev_id, &shp_slot_cfg_l0); - - if( rv != SW_OK ) - return rv; - - *time_slot = shp_slot_cfg_l0.bf.l0_shp_slot_time; - - return SW_OK; -} - -sw_error_t -adpt_hppe_port_shaper_token_number_get(a_uint32_t dev_id, fal_port_t port_id, - fal_shaper_token_number_t *token_number) -{ - union psch_shp_credit_tbl_u psch_shp_credit_tbl; - union psch_shp_sign_tbl_u psch_shp_sign_tbl; - - memset(&psch_shp_credit_tbl, 0, sizeof(psch_shp_credit_tbl)); - memset(&psch_shp_sign_tbl, 0, sizeof(psch_shp_sign_tbl)); - - ADPT_DEV_ID_CHECK(dev_id); - ADPT_NULL_POINT_CHECK(token_number); - - if (port_id < 0 || port_id > 7) - return SW_BAD_PARAM; - - hppe_psch_shp_credit_tbl_get(dev_id, port_id, &psch_shp_credit_tbl); - - hppe_psch_shp_sign_tbl_get(dev_id, port_id, &psch_shp_sign_tbl); - - - token_number->c_token_number_negative_en = psch_shp_sign_tbl.bf.shaper_credit_neg; - token_number->c_token_number = psch_shp_credit_tbl.bf.shaper_credit; - - return SW_OK; -} -#endif - -sw_error_t -adpt_hppe_flow_shaper_token_number_set(a_uint32_t dev_id, a_uint32_t flow_id, - fal_shaper_token_number_t *token_number) -{ - union l1_shp_credit_tbl_u l1_shp_credit_tbl; - - memset(&l1_shp_credit_tbl, 0, sizeof(l1_shp_credit_tbl)); - ADPT_DEV_ID_CHECK(dev_id); - ADPT_NULL_POINT_CHECK(token_number); - - if ((flow_id < 0) || (flow_id > 63)) - return SW_BAD_PARAM; - - - l1_shp_credit_tbl.bf.c_shaper_credit_neg = token_number->c_token_number_negative_en; - l1_shp_credit_tbl.bf.c_shaper_credit = token_number->c_token_number; - l1_shp_credit_tbl.bf.e_shaper_credit_neg = token_number->e_token_number_negative_en; - l1_shp_credit_tbl.bf.e_shaper_credit_0 = token_number->e_token_number & 0x1; - l1_shp_credit_tbl.bf.e_shaper_credit_1 = token_number->e_token_number >> 1; - - hppe_l1_shp_credit_tbl_set(dev_id, flow_id, &l1_shp_credit_tbl); - - return SW_OK; -} -#ifndef IN_SHAPER_MINI -sw_error_t -adpt_hppe_flow_shaper_token_number_get(a_uint32_t dev_id, a_uint32_t flow_id, - fal_shaper_token_number_t *token_number) -{ - sw_error_t rv = SW_OK; - union l1_shp_credit_tbl_u l1_shp_credit_tbl; - - memset(&l1_shp_credit_tbl, 0, sizeof(l1_shp_credit_tbl)); - ADPT_DEV_ID_CHECK(dev_id); - ADPT_NULL_POINT_CHECK(token_number); - - if ((flow_id < 0) || (flow_id > 63)) - return SW_BAD_PARAM; - - rv = hppe_l1_shp_credit_tbl_get(dev_id, flow_id, &l1_shp_credit_tbl); - - if( rv != SW_OK ) - return rv; - - token_number->c_token_number_negative_en = l1_shp_credit_tbl.bf.c_shaper_credit_neg; - token_number->c_token_number = l1_shp_credit_tbl.bf.c_shaper_credit; - token_number->e_token_number_negative_en = l1_shp_credit_tbl.bf.e_shaper_credit_neg; - token_number->e_token_number = l1_shp_credit_tbl.bf.e_shaper_credit_0 | - (l1_shp_credit_tbl.bf.e_shaper_credit_1 << 1); - - return SW_OK; -} -#endif - -sw_error_t -adpt_hppe_flow_shaper_set(a_uint32_t dev_id, a_uint32_t flow_id, - fal_shaper_config_t * shaper) -{ - sw_error_t rv = SW_OK; - union l1_shp_cfg_tbl_u l1_shp_cfg_tbl; - union l1_comp_cfg_tbl_u l1_comp_cfg_tbl; - a_uint32_t hppe_cir = 0, hppe_cbs = 0, hppe_eir= 0, hppe_ebs = 0; - a_uint64_t temp_cir = 0, temp_eir =0, temp_cbs =0, temp_ebs = 0; - a_uint32_t token_unit = 0; - fal_shaper_token_number_t token_number; - - memset(&l1_shp_cfg_tbl, 0, sizeof(l1_shp_cfg_tbl)); - memset(&l1_comp_cfg_tbl, 0, sizeof(l1_comp_cfg_tbl)); - ADPT_DEV_ID_CHECK(dev_id); - ADPT_NULL_POINT_CHECK(shaper); - - if ((flow_id < 0) || (flow_id > 63)) - return SW_BAD_PARAM; - - if(ADPT_HPPE_SHAPER_METER_UNIT_BYTE == shaper->meter_unit) - { - if ((shaper->cir > BYTE_SHAPER_MAX_RATE) || (shaper->eir > BYTE_SHAPER_MAX_RATE)) - return SW_BAD_PARAM; - if ((shaper->cir < BYTE_SHAPER_MIN_RATE) && (shaper->cir != 0)) - return SW_BAD_PARAM; - if ((shaper->eir < BYTE_SHAPER_MIN_RATE) && (shaper->eir != 0)) - return SW_BAD_PARAM; - } - if(ADPT_HPPE_SHAPER_METER_UNIT_FRAME == shaper->meter_unit) - { - if ((shaper->cir > FRAME_SHAPER_MAX_RATE) || (shaper->eir > FRAME_SHAPER_MAX_RATE)) - return SW_BAD_PARAM; - if ((shaper->cir < FRAME_SHAPER_MIN_RATE) && (shaper->cir != 0)) - return SW_BAD_PARAM; - if ((shaper->eir < FRAME_SHAPER_MIN_RATE) && (shaper->eir != 0)) - return SW_BAD_PARAM; - } - - hppe_l1_comp_cfg_tbl_get(dev_id, flow_id, &l1_comp_cfg_tbl); - - temp_cir = ((a_uint64_t)shaper->cir) * 1000; - temp_cbs = ((a_uint64_t)shaper->cbs) * 1000; - temp_eir = ((a_uint64_t)shaper->eir) * 1000; - temp_ebs = ((a_uint64_t)shaper->ebs) * 1000; - - rv = __adpt_hppe_shaper_two_bucket_parameter_select(ADPT_HPPE_FLOW_SHAPER, - temp_cir, - temp_cbs, - temp_eir, - temp_ebs, - shaper->meter_unit, - &token_unit); - if( rv != SW_OK ) - return rv; - //printk("flow shaper meter unit is = %d\n", shaper->meter_unit); - //printk("flow shaper token unit is = %d\n", token_unit); - - __adpt_hppe_shaper_rate_to_refresh(ADPT_HPPE_FLOW_SHAPER, - shaper->cir, - &hppe_cir, - shaper->meter_unit, - token_unit); - - __adpt_hppe_shaper_rate_to_refresh(ADPT_HPPE_FLOW_SHAPER, - shaper->eir, - &hppe_eir, - shaper->meter_unit, - token_unit); - - __adpt_hppe_shaper_burst_size_to_bucket_size(shaper->cbs, - &hppe_cbs, - shaper->meter_unit, - token_unit); - - __adpt_hppe_shaper_burst_size_to_bucket_size(shaper->ebs, - &hppe_ebs, - shaper->meter_unit, - token_unit); - - l1_shp_cfg_tbl.bf.cf = shaper->couple_en; - l1_shp_cfg_tbl.bf.meter_unit = shaper->meter_unit; - l1_shp_cfg_tbl.bf.c_shaper_enable = shaper->c_shaper_en; - l1_shp_cfg_tbl.bf.cbs = hppe_cbs; - l1_shp_cfg_tbl.bf.cir = hppe_cir; - l1_shp_cfg_tbl.bf.e_shaper_enable = shaper->e_shaper_en; - l1_shp_cfg_tbl.bf.ebs = hppe_ebs; - l1_shp_cfg_tbl.bf.eir = hppe_eir; - l1_shp_cfg_tbl.bf.token_unit = token_unit; - l1_comp_cfg_tbl.bf.shaper_meter_len = shaper->shaper_frame_mode; - - hppe_l1_shp_cfg_tbl_set(dev_id, flow_id, &l1_shp_cfg_tbl); - - hppe_l1_comp_cfg_tbl_set(dev_id, flow_id, &l1_comp_cfg_tbl); - - if( A_FALSE == shaper->c_shaper_en) - { - token_number.c_token_number_negative_en = 0; - token_number.c_token_number = 0; - adpt_hppe_flow_shaper_token_number_set(dev_id, flow_id, &token_number); - } - if( A_FALSE == shaper->e_shaper_en) - { - token_number.e_token_number_negative_en = 0; - token_number.e_token_number = 0; - adpt_hppe_flow_shaper_token_number_set(dev_id, flow_id, &token_number); - } - - return SW_OK; -} -sw_error_t -adpt_hppe_port_shaper_set(a_uint32_t dev_id, fal_port_t port_id, - fal_shaper_config_t * shaper) -{ - sw_error_t rv = SW_OK; - union psch_shp_cfg_tbl_u psch_shp_cfg_tbl; - union psch_comp_cfg_tbl_u psch_comp_cfg_tbl; - a_uint64_t temp_cir = 0,temp_cbs; - a_uint32_t hppe_cir = 0, hppe_cbs = 0; - a_uint32_t token_unit = 0; - fal_shaper_token_number_t token_number; - - memset(&psch_shp_cfg_tbl, 0, sizeof(psch_shp_cfg_tbl)); - memset(&psch_comp_cfg_tbl, 0, sizeof(psch_comp_cfg_tbl)); - ADPT_DEV_ID_CHECK(dev_id); - ADPT_NULL_POINT_CHECK(shaper); - - if (port_id < 0 || port_id > 7) - return SW_BAD_PARAM; - - if(ADPT_HPPE_SHAPER_METER_UNIT_BYTE == shaper->meter_unit) - { - if (shaper->cir > BYTE_SHAPER_MAX_RATE) - return SW_BAD_PARAM; - if ((shaper->cir < BYTE_SHAPER_MIN_RATE) && (shaper->cir != 0)) - return SW_BAD_PARAM; - } - if(ADPT_HPPE_SHAPER_METER_UNIT_FRAME == shaper->meter_unit) - { - if (shaper->cir > FRAME_SHAPER_MAX_RATE) - return SW_BAD_PARAM; - if ((shaper->cir < FRAME_SHAPER_MIN_RATE) && (shaper->cir != 0)) - return SW_BAD_PARAM; - } - - temp_cir = ((a_uint64_t)shaper->cir) * 1000; - temp_cbs = ((a_uint64_t)shaper->cbs) * 1000; - - rv = __adpt_hppe_shaper_one_bucket_parameter_select(ADPT_HPPE_PORT_SHAPER, - temp_cir, - temp_cbs, - shaper->meter_unit, - &token_unit); - if( rv != SW_OK ) - return rv; - - // printk("current shaper meter unit is = %d\n", shaper->meter_unit); - // printk("current shaper token unit is = %d\n", token_unit); - - __adpt_hppe_shaper_rate_to_refresh(ADPT_HPPE_PORT_SHAPER, - shaper->cir, - &hppe_cir, - shaper->meter_unit, - token_unit); - - __adpt_hppe_shaper_burst_size_to_bucket_size(shaper->cbs, - &hppe_cbs, - shaper->meter_unit, - token_unit); - - psch_shp_cfg_tbl.bf.meter_unit = shaper->meter_unit; - psch_shp_cfg_tbl.bf.shaper_enable = shaper->c_shaper_en; - psch_shp_cfg_tbl.bf.cbs = hppe_cbs; - psch_shp_cfg_tbl.bf.cir = hppe_cir; - psch_shp_cfg_tbl.bf.token_unit = token_unit; - - psch_comp_cfg_tbl.bf.shaper_meter_len = shaper->shaper_frame_mode; - - hppe_psch_shp_cfg_tbl_set(dev_id, port_id, &psch_shp_cfg_tbl); - - hppe_psch_comp_cfg_tbl_set(dev_id, port_id, &psch_comp_cfg_tbl); - - if( A_FALSE == shaper->c_shaper_en) - { - token_number.c_token_number_negative_en = 0; - token_number.c_token_number = 0; - adpt_hppe_port_shaper_token_number_set(dev_id, port_id, &token_number); - } - - return SW_OK; -} -sw_error_t -adpt_hppe_port_shaper_time_slot_set(a_uint32_t dev_id, a_uint32_t time_slot) -{ - sw_error_t rv = SW_OK; - union shp_slot_cfg_port_u shp_slot_cfg_port; - - memset(&shp_slot_cfg_port, 0, sizeof(shp_slot_cfg_port)); - ADPT_DEV_ID_CHECK(dev_id); - - if ((time_slot < 0x8) || (time_slot > 0xfff)) - return SW_BAD_PARAM; - - rv = hppe_shp_slot_cfg_port_get(dev_id, &shp_slot_cfg_port); - - if( rv != SW_OK ) - return rv; - - shp_slot_cfg_port.bf.port_shp_slot_time = time_slot; - hppe_shp_slot_cfg_port_set(dev_id, &shp_slot_cfg_port); - - __adpt_hppe_port_shaper_max_rate(time_slot); - - __adpt_hppe_shaper_max_burst_size(); - - return SW_OK; - -} -#ifndef IN_SHAPER_MINI -sw_error_t -adpt_hppe_flow_shaper_get(a_uint32_t dev_id, a_uint32_t flow_id, - fal_shaper_config_t * shaper) -{ - sw_error_t rv = SW_OK; - union l1_shp_cfg_tbl_u l1_shp_cfg_tbl; - union l1_comp_cfg_tbl_u l1_comp_cfg_tbl; - a_uint32_t hppe_cir =0, hppe_cbs = 0, hppe_eir = 0, hppe_ebs = 0; - - memset(&l1_shp_cfg_tbl, 0, sizeof(l1_shp_cfg_tbl)); - memset(&l1_comp_cfg_tbl, 0, sizeof(l1_comp_cfg_tbl)); - - ADPT_DEV_ID_CHECK(dev_id); - ADPT_NULL_POINT_CHECK(shaper); - - if (flow_id < 0 || flow_id > 63) - return SW_BAD_PARAM; - - hppe_l1_comp_cfg_tbl_get(dev_id, flow_id, &l1_comp_cfg_tbl); - - rv = hppe_l1_shp_cfg_tbl_get(dev_id, flow_id, &l1_shp_cfg_tbl); - - if( rv != SW_OK ) - return rv; - - hppe_cir = l1_shp_cfg_tbl.bf.cir; - hppe_cbs = l1_shp_cfg_tbl.bf.cbs; - hppe_eir = l1_shp_cfg_tbl.bf.eir; - hppe_ebs= l1_shp_cfg_tbl.bf.ebs; - - __adpt_hppe_shaper_refresh_to_rate(ADPT_HPPE_FLOW_SHAPER, - hppe_cir, - &shaper->cir, - l1_shp_cfg_tbl.bf.meter_unit, - l1_shp_cfg_tbl.bf.token_unit); - - __adpt_hppe_shaper_refresh_to_rate(ADPT_HPPE_FLOW_SHAPER, - hppe_eir, - &shaper->eir, - l1_shp_cfg_tbl.bf.meter_unit, - l1_shp_cfg_tbl.bf.token_unit); - - - __adpt_hppe_shaper_bucket_size_to_burst_size(hppe_cbs, - &shaper->cbs, - l1_shp_cfg_tbl.bf.meter_unit, - l1_shp_cfg_tbl.bf.token_unit); - - __adpt_hppe_shaper_bucket_size_to_burst_size(hppe_ebs, - &shaper->ebs, - l1_shp_cfg_tbl.bf.meter_unit, - l1_shp_cfg_tbl.bf.token_unit); - - shaper->couple_en = l1_shp_cfg_tbl.bf.cf; - shaper->meter_unit = l1_shp_cfg_tbl.bf.meter_unit; - shaper->c_shaper_en = l1_shp_cfg_tbl.bf.c_shaper_enable; - shaper->e_shaper_en = l1_shp_cfg_tbl.bf.e_shaper_enable; - - shaper->shaper_frame_mode = l1_comp_cfg_tbl.bf.shaper_meter_len; - - return SW_OK; -} -#endif - -sw_error_t -adpt_hppe_queue_shaper_set(a_uint32_t dev_id,a_uint32_t queue_id, - fal_shaper_config_t * shaper) -{ - sw_error_t rv = SW_OK; - union l0_shp_cfg_tbl_u l0_shp_cfg_tbl; - union l0_comp_cfg_tbl_u l0_comp_cfg_tbl; - a_uint32_t hppe_cir = 0, hppe_cbs = 0, hppe_eir= 0, hppe_ebs = 0; - a_uint32_t token_unit = 0; - a_uint64_t temp_cir = 0, temp_eir =0, temp_cbs =0, temp_ebs = 0; - fal_shaper_token_number_t token_number; - - memset(&l0_shp_cfg_tbl, 0, sizeof(l0_shp_cfg_tbl)); - memset(&l0_comp_cfg_tbl, 0, sizeof(l0_comp_cfg_tbl)); - ADPT_DEV_ID_CHECK(dev_id); - ADPT_NULL_POINT_CHECK(shaper); - - if (queue_id < 0 || queue_id > 299) - return SW_BAD_PARAM; - - if(ADPT_HPPE_SHAPER_METER_UNIT_BYTE == shaper->meter_unit) - { - if ((shaper->cir > BYTE_SHAPER_MAX_RATE) || (shaper->eir > BYTE_SHAPER_MAX_RATE)) - return SW_BAD_PARAM; - if ((shaper->cir < BYTE_SHAPER_MIN_RATE) && (shaper->cir != 0)) - return SW_BAD_PARAM; - if ((shaper->eir < BYTE_SHAPER_MIN_RATE) && (shaper->eir != 0)) - return SW_BAD_PARAM; - } - if(ADPT_HPPE_SHAPER_METER_UNIT_FRAME == shaper->meter_unit) - { - if ((shaper->cir > FRAME_SHAPER_MAX_RATE) || (shaper->eir > FRAME_SHAPER_MAX_RATE)) - return SW_BAD_PARAM; - if ((shaper->cir < FRAME_SHAPER_MIN_RATE) && (shaper->cir != 0)) - return SW_BAD_PARAM; - if ((shaper->eir < FRAME_SHAPER_MIN_RATE) && (shaper->eir != 0)) - return SW_BAD_PARAM; - } - - hppe_l0_comp_cfg_tbl_get(dev_id, queue_id, &l0_comp_cfg_tbl); - - temp_cir = ((a_uint64_t)shaper->cir) * 1000; - temp_cbs = ((a_uint64_t)shaper->cbs) * 1000; - temp_eir = ((a_uint64_t)shaper->eir) * 1000; - temp_ebs = ((a_uint64_t)shaper->ebs) * 1000; - - rv = __adpt_hppe_shaper_two_bucket_parameter_select(ADPT_HPPE_QUEUE_SHAPER, - temp_cir, - temp_cbs, - temp_eir, - temp_ebs, - shaper->meter_unit, - &token_unit); - if( rv != SW_OK ) - return rv; - //printk("queue shaper meter unit is = %d\n", shaper->meter_unit); - //printk("queue shaper token unit is = %d\n", token_unit); - - __adpt_hppe_shaper_rate_to_refresh(ADPT_HPPE_QUEUE_SHAPER, - shaper->cir, - &hppe_cir, - shaper->meter_unit, - token_unit); - - __adpt_hppe_shaper_rate_to_refresh(ADPT_HPPE_QUEUE_SHAPER, - shaper->eir, - &hppe_eir, - shaper->meter_unit, - token_unit); - - __adpt_hppe_shaper_burst_size_to_bucket_size(shaper->cbs, - &hppe_cbs, - shaper->meter_unit, - token_unit); - - __adpt_hppe_shaper_burst_size_to_bucket_size(shaper->ebs, - &hppe_ebs, - shaper->meter_unit, - token_unit); - - l0_shp_cfg_tbl.bf.cf = shaper->couple_en; - l0_shp_cfg_tbl.bf.meter_unit = shaper->meter_unit; - l0_shp_cfg_tbl.bf.c_shaper_enable = shaper->c_shaper_en; - l0_shp_cfg_tbl.bf.cbs = hppe_cbs; - l0_shp_cfg_tbl.bf.cir = hppe_cir; - l0_shp_cfg_tbl.bf.e_shaper_enable = shaper->e_shaper_en; - l0_shp_cfg_tbl.bf.ebs = hppe_ebs; - l0_shp_cfg_tbl.bf.eir = hppe_eir; - l0_shp_cfg_tbl.bf.token_unit = token_unit; - l0_comp_cfg_tbl.bf.shaper_meter_len = shaper->shaper_frame_mode; - - hppe_l0_shp_cfg_tbl_set(dev_id, queue_id, &l0_shp_cfg_tbl); - - hppe_l0_comp_cfg_tbl_set(dev_id, queue_id, &l0_comp_cfg_tbl); - - if( A_FALSE == shaper->c_shaper_en) - { - token_number.c_token_number_negative_en = 0; - token_number.c_token_number = 0; - adpt_hppe_queue_shaper_token_number_set(dev_id, queue_id, &token_number); - } - if( A_FALSE == shaper->e_shaper_en) - { - token_number.e_token_number_negative_en = 0; - token_number.e_token_number = 0; - adpt_hppe_queue_shaper_token_number_set(dev_id, queue_id, &token_number); - } - - return SW_OK; - -} -sw_error_t -adpt_hppe_queue_shaper_time_slot_set(a_uint32_t dev_id, a_uint32_t time_slot) -{ - union shp_slot_cfg_l0_u shp_slot_cfg_l0; - sw_error_t rv = SW_OK; - - memset(&shp_slot_cfg_l0, 0, sizeof(shp_slot_cfg_l0)); - ADPT_DEV_ID_CHECK(dev_id); - - if ((time_slot < 0x12c) || (time_slot > 0xfff)) - return SW_BAD_PARAM; - - rv = hppe_shp_slot_cfg_l0_get(dev_id, &shp_slot_cfg_l0); - - if( rv != SW_OK ) - return rv; - - shp_slot_cfg_l0.bf.l0_shp_slot_time = time_slot; - hppe_shp_slot_cfg_l0_set(dev_id, &shp_slot_cfg_l0); - - __adpt_hppe_queue_shaper_max_rate(time_slot); - - return SW_OK; - -} - -sw_error_t -adpt_hppe_shaper_ipg_preamble_length_set(a_uint32_t dev_id, a_uint32_t ipg_pre_length) -{ - union ipg_pre_len_cfg_u ipg_pre_len_cfg; - - memset(&ipg_pre_len_cfg, 0, sizeof(ipg_pre_len_cfg)); - ADPT_DEV_ID_CHECK(dev_id); - - if (ipg_pre_length > 0x1f) - return SW_BAD_PARAM; - - hppe_ipg_pre_len_cfg_get(dev_id, &ipg_pre_len_cfg); - ipg_pre_len_cfg.bf.ipg_pre_len = ipg_pre_length; - - hppe_ipg_pre_len_cfg_set(dev_id, &ipg_pre_len_cfg); - - return SW_OK; -} - -#ifndef IN_SHAPER_MINI -sw_error_t -adpt_hppe_shaper_ipg_preamble_length_get(a_uint32_t dev_id, a_uint32_t *ipg_pre_length) -{ - sw_error_t rv = SW_OK; - union ipg_pre_len_cfg_u ipg_pre_len_cfg; - - memset(&ipg_pre_len_cfg, 0, sizeof(ipg_pre_len_cfg)); - ADPT_DEV_ID_CHECK(dev_id); - ADPT_NULL_POINT_CHECK(ipg_pre_length); - - rv = hppe_ipg_pre_len_cfg_get(dev_id, &ipg_pre_len_cfg); - - if( rv != SW_OK ) - return rv; - - *ipg_pre_length = ipg_pre_len_cfg.bf.ipg_pre_len; - - return SW_OK; -} -#endif - -void adpt_hppe_shaper_func_bitmap_init(a_uint32_t dev_id) -{ - adpt_api_t *p_adpt_api = NULL; - - p_adpt_api = adpt_api_ptr_get(dev_id); - - if(p_adpt_api == NULL) - return; - - p_adpt_api->adpt_shaper_func_bitmap = ((1 << FUNC_ADPT_FLOW_SHAPER_SET)| - (1 << FUNC_ADPT_QUEUE_SHAPER_GET)| - (1 << FUNC_ADPT_QUEUE_SHAPER_TOKEN_NUMBER_SET)| - (1 << FUNC_ADPT_PORT_SHAPER_GET)| - (1 << FUNC_ADPT_FLOW_SHAPER_TIME_SLOT_GET)| - (1 << FUNC_ADPT_PORT_SHAPER_TIME_SLOT_GET)| - (1 << FUNC_ADPT_FLOW_SHAPER_TIME_SLOT_SET)| - (1 << FUNC_ADPT_PORT_SHAPER_TOKEN_NUMBER_SET)| - (1 << FUNC_ADPT_QUEUE_SHAPER_TOKEN_NUMBER_GET)| - (1 << FUNC_ADPT_QUEUE_SHAPER_TIME_SLOT_GET)| - (1 << FUNC_ADPT_PORT_SHAPER_TOKEN_NUMBER_GET)| - (1 << FUNC_ADPT_FLOW_SHAPER_TOKEN_NUMBER_SET)| - (1 << FUNC_ADPT_FLOW_SHAPER_TOKEN_NUMBER_GET)| - (1 << FUNC_ADPT_PORT_SHAPER_SET)| - (1 << FUNC_ADPT_PORT_SHAPER_TIME_SLOT_SET)| - (1 << FUNC_ADPT_FLOW_SHAPER_GET)| - (1 << FUNC_ADPT_QUEUE_SHAPER_SET)| - (1 << FUNC_ADPT_QUEUE_SHAPER_TIME_SLOT_SET)| - (1 << FUNC_ADPT_SHAPER_IPG_PREAMBLE_LENGTH_SET)| - (1 << FUNC_ADPT_SHAPER_IPG_PREAMBLE_LENGTH_GET)); - - return; - -} - -static void adpt_hppe_shaper_func_unregister(a_uint32_t dev_id, adpt_api_t *p_adpt_api) -{ - if(p_adpt_api == NULL) - return; - - p_adpt_api->adpt_flow_shaper_set = NULL; - p_adpt_api->adpt_queue_shaper_get = NULL; - p_adpt_api->adpt_queue_shaper_token_number_set = NULL; - p_adpt_api->adpt_port_shaper_get = NULL; - p_adpt_api->adpt_flow_shaper_time_slot_get = NULL; - p_adpt_api->adpt_port_shaper_time_slot_get = NULL; - p_adpt_api->adpt_flow_shaper_time_slot_set = NULL; - p_adpt_api->adpt_port_shaper_token_number_set = NULL; - p_adpt_api->adpt_queue_shaper_token_number_get = NULL; - p_adpt_api->adpt_queue_shaper_time_slot_get = NULL; - p_adpt_api->adpt_port_shaper_token_number_get = NULL; - p_adpt_api->adpt_flow_shaper_token_number_set = NULL; - p_adpt_api->adpt_flow_shaper_token_number_get = NULL; - p_adpt_api->adpt_port_shaper_set = NULL; - p_adpt_api->adpt_port_shaper_time_slot_set = NULL; - p_adpt_api->adpt_flow_shaper_get = NULL; - p_adpt_api->adpt_queue_shaper_set = NULL; - p_adpt_api->adpt_queue_shaper_time_slot_set = NULL; - p_adpt_api->adpt_shaper_ipg_preamble_length_set = NULL; - p_adpt_api->adpt_shaper_ipg_preamble_length_get = NULL; - - return; - -} - -sw_error_t adpt_hppe_shaper_init(a_uint32_t dev_id) -{ - adpt_api_t *p_adpt_api = NULL; - - p_adpt_api = adpt_api_ptr_get(dev_id); - - if(p_adpt_api == NULL) - return SW_FAIL; - - adpt_hppe_shaper_func_unregister(dev_id, p_adpt_api); - -#ifndef IN_SHAPER_MINI - if(p_adpt_api->adpt_shaper_func_bitmap & (1 << FUNC_ADPT_PORT_SHAPER_GET)) - { - p_adpt_api->adpt_port_shaper_get = adpt_hppe_port_shaper_get; - } - if(p_adpt_api->adpt_shaper_func_bitmap & (1 << FUNC_ADPT_FLOW_SHAPER_TIME_SLOT_GET)) - { - p_adpt_api->adpt_flow_shaper_time_slot_get = adpt_hppe_flow_shaper_time_slot_get; - } - if(p_adpt_api->adpt_shaper_func_bitmap & (1 << FUNC_ADPT_PORT_SHAPER_TIME_SLOT_GET)) - { - p_adpt_api->adpt_port_shaper_time_slot_get = adpt_hppe_port_shaper_time_slot_get; - } - if(p_adpt_api->adpt_shaper_func_bitmap & (1 << FUNC_ADPT_QUEUE_SHAPER_TOKEN_NUMBER_GET)) - { - p_adpt_api->adpt_queue_shaper_token_number_get = - adpt_hppe_queue_shaper_token_number_get; - } - if(p_adpt_api->adpt_shaper_func_bitmap & (1 << FUNC_ADPT_QUEUE_SHAPER_TIME_SLOT_GET)) - { - p_adpt_api->adpt_queue_shaper_time_slot_get = adpt_hppe_queue_shaper_time_slot_get; - } - if(p_adpt_api->adpt_shaper_func_bitmap & (1 << FUNC_ADPT_PORT_SHAPER_TOKEN_NUMBER_GET)) - { - p_adpt_api->adpt_port_shaper_token_number_get = - adpt_hppe_port_shaper_token_number_get; - } - if(p_adpt_api->adpt_shaper_func_bitmap & (1 << FUNC_ADPT_FLOW_SHAPER_TOKEN_NUMBER_GET)) - { - p_adpt_api->adpt_flow_shaper_token_number_get = - adpt_hppe_flow_shaper_token_number_get; - } - if(p_adpt_api->adpt_shaper_func_bitmap & (1 << FUNC_ADPT_FLOW_SHAPER_GET)) - { - p_adpt_api->adpt_flow_shaper_get = adpt_hppe_flow_shaper_get; - } - if(p_adpt_api->adpt_shaper_func_bitmap & (1 << FUNC_ADPT_SHAPER_IPG_PREAMBLE_LENGTH_GET)) - { - p_adpt_api->adpt_shaper_ipg_preamble_length_get = - adpt_hppe_shaper_ipg_preamble_length_get; - } -#endif - if(p_adpt_api->adpt_shaper_func_bitmap & (1 << FUNC_ADPT_FLOW_SHAPER_SET)) - { - p_adpt_api->adpt_flow_shaper_set = adpt_hppe_flow_shaper_set; - } - if(p_adpt_api->adpt_shaper_func_bitmap & (1 << FUNC_ADPT_QUEUE_SHAPER_SET)) - { - p_adpt_api->adpt_queue_shaper_set = adpt_hppe_queue_shaper_set; - } - if(p_adpt_api->adpt_shaper_func_bitmap & (1 << FUNC_ADPT_QUEUE_SHAPER_GET)) - { - p_adpt_api->adpt_queue_shaper_get = adpt_hppe_queue_shaper_get; - } - if(p_adpt_api->adpt_shaper_func_bitmap & (1 << FUNC_ADPT_PORT_SHAPER_SET)) - { - p_adpt_api->adpt_port_shaper_set = adpt_hppe_port_shaper_set; - } - if(p_adpt_api->adpt_shaper_func_bitmap & (1 << FUNC_ADPT_SHAPER_IPG_PREAMBLE_LENGTH_SET)) - { - p_adpt_api->adpt_shaper_ipg_preamble_length_set = - adpt_hppe_shaper_ipg_preamble_length_set; - } - if(p_adpt_api->adpt_shaper_func_bitmap & (1 << FUNC_ADPT_QUEUE_SHAPER_TOKEN_NUMBER_SET)) - { - p_adpt_api->adpt_queue_shaper_token_number_set = - adpt_hppe_queue_shaper_token_number_set; - } - if(p_adpt_api->adpt_shaper_func_bitmap & (1 << FUNC_ADPT_PORT_SHAPER_TOKEN_NUMBER_SET)) - { - p_adpt_api->adpt_port_shaper_token_number_set = - adpt_hppe_port_shaper_token_number_set; - } - if(p_adpt_api->adpt_shaper_func_bitmap & (1 << FUNC_ADPT_FLOW_SHAPER_TOKEN_NUMBER_SET)) - { - p_adpt_api->adpt_flow_shaper_token_number_set = - adpt_hppe_flow_shaper_token_number_set; - } - if(p_adpt_api->adpt_shaper_func_bitmap & (1 << FUNC_ADPT_PORT_SHAPER_TIME_SLOT_SET)) - { - p_adpt_api->adpt_port_shaper_time_slot_set = adpt_hppe_port_shaper_time_slot_set; - } - if(p_adpt_api->adpt_shaper_func_bitmap & (1 << FUNC_ADPT_FLOW_SHAPER_TIME_SLOT_SET)) - { - p_adpt_api->adpt_flow_shaper_time_slot_set = adpt_hppe_flow_shaper_time_slot_set; - } - if(p_adpt_api->adpt_shaper_func_bitmap & (1 << FUNC_ADPT_QUEUE_SHAPER_TIME_SLOT_SET)) - { - p_adpt_api->adpt_queue_shaper_time_slot_set = adpt_hppe_queue_shaper_time_slot_set; - } - - return SW_OK; -} - -/** - * @} - */ diff --git a/feeds/ipq807x/qca-ssdk/src/src/adpt/hppe/adpt_hppe_stp.c b/feeds/ipq807x/qca-ssdk/src/src/adpt/hppe/adpt_hppe_stp.c deleted file mode 100755 index 634c3c4f6..000000000 --- a/feeds/ipq807x/qca-ssdk/src/src/adpt/hppe/adpt_hppe_stp.c +++ /dev/null @@ -1,135 +0,0 @@ -/* - * Copyright (c) 2016-2017, The Linux Foundation. All rights reserved. - * Permission to use, copy, modify, and/or distribute this software for - * any purpose with or without fee is hereby granted, provided that the - * above copyright notice and this permission notice appear in all copies. - * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES - * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR - * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES - * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN - * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT - * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. - */ - - -/** - * @defgroup - * @{ - */ -#include "sw.h" -#include "hppe_stp_reg.h" -#include "hppe_stp.h" -#include "adpt.h" - -sw_error_t -adpt_hppe_stp_port_state_get(a_uint32_t dev_id, a_uint32_t st_id, - fal_port_t port_id, fal_stp_state_t * state) -{ - union cst_state_u cst_state; - - memset(&cst_state, 0, sizeof(cst_state)); - ADPT_DEV_ID_CHECK(dev_id); - ADPT_NULL_POINT_CHECK(state); - if (FAL_SINGLE_STP_ID != st_id) - return SW_BAD_PARAM; - - SW_RTN_ON_ERROR(hppe_cst_state_get(dev_id, port_id, &cst_state)); - - if (cst_state.bf.port_state == 0) - *state = FAL_STP_DISABLED; - else if (cst_state.bf.port_state == 1) - *state = FAL_STP_BLOKING; - else if (cst_state.bf.port_state == 2) - *state = FAL_STP_LEARNING; - else if (cst_state.bf.port_state == 3) - *state = FAL_STP_FARWARDING; - else - *state = FAL_STP_STATE_BUTT; - - return SW_OK; -} - -sw_error_t -adpt_hppe_stp_port_state_set(a_uint32_t dev_id, a_uint32_t st_id, - fal_port_t port_id, fal_stp_state_t state) -{ - union cst_state_u cst_state; - - memset(&cst_state, 0, sizeof(cst_state)); - - /* stp port_id just support physical port, not support trunk and virtual port */ - if (FAL_PORT_ID_TYPE(port_id) != 0) - return SW_BAD_PARAM; - - if (port_id >= CST_STATE_MAX_ENTRY) - return SW_OUT_OF_RANGE; - - ADPT_DEV_ID_CHECK(dev_id); - if (FAL_SINGLE_STP_ID != st_id) - return SW_BAD_PARAM; - - if (state == FAL_STP_DISABLED) - cst_state.bf.port_state = 0; - else if (state == FAL_STP_BLOKING || state == FAL_STP_LISTENING) - cst_state.bf.port_state = 1; - else if (state == FAL_STP_LEARNING) - cst_state.bf.port_state = 2; - else if (state == FAL_STP_FARWARDING) - cst_state.bf.port_state = 3; - - SW_RTN_ON_ERROR(hppe_cst_state_set(dev_id, port_id, &cst_state)); - - return SW_OK; -} - -void adpt_hppe_stp_func_bitmap_init(a_uint32_t dev_id) -{ - adpt_api_t *p_adpt_api = NULL; - - p_adpt_api = adpt_api_ptr_get(dev_id); - - if(p_adpt_api == NULL) - return; - - p_adpt_api->adpt_stp_func_bitmap = ((1 << FUNC_STP_PORT_STATE_SET) | - (1 << FUNC_STP_PORT_STATE_GET)); - - return; -} - -static void adpt_hppe_stp_func_unregister(a_uint32_t dev_id, adpt_api_t *p_adpt_api) -{ - if(p_adpt_api == NULL) - return; - - p_adpt_api->adpt_stp_port_state_get = NULL; - p_adpt_api->adpt_stp_port_state_set = NULL; - - return; -} - -sw_error_t -adpt_hppe_stp_init(a_uint32_t dev_id) -{ - adpt_api_t *p_adpt_api = NULL; - - p_adpt_api = adpt_api_ptr_get(dev_id); - - if(p_adpt_api == NULL) - return SW_FAIL; - - adpt_hppe_stp_func_unregister(dev_id, p_adpt_api); - - if (p_adpt_api->adpt_stp_func_bitmap & (1 << FUNC_STP_PORT_STATE_GET)) - p_adpt_api->adpt_stp_port_state_get = adpt_hppe_stp_port_state_get; - if (p_adpt_api->adpt_stp_func_bitmap & (1 << FUNC_STP_PORT_STATE_SET)) - p_adpt_api->adpt_stp_port_state_set = adpt_hppe_stp_port_state_set; - - - return SW_OK; -} - -/** - * @} - */ diff --git a/feeds/ipq807x/qca-ssdk/src/src/adpt/hppe/adpt_hppe_trunk.c b/feeds/ipq807x/qca-ssdk/src/src/adpt/hppe/adpt_hppe_trunk.c deleted file mode 100644 index 976625542..000000000 --- a/feeds/ipq807x/qca-ssdk/src/src/adpt/hppe/adpt_hppe_trunk.c +++ /dev/null @@ -1,345 +0,0 @@ -/* - * Copyright (c) 2016-2017, 2020, The Linux Foundation. All rights reserved. - * Permission to use, copy, modify, and/or distribute this software for - * any purpose with or without fee is hereby granted, provided that the - * above copyright notice and this permission notice appear in all copies. - * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES - * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR - * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES - * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN - * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT - * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. - */ - - -/** - * @defgroup - * @{ - */ -#include "sw.h" - -#include "hppe_trunk_reg.h" -#include "hppe_trunk.h" -#include "adpt.h" -#include "hppe_fdb_reg.h" -#include "hppe_fdb.h" - -sw_error_t -adpt_hppe_trunk_fail_over_en_get(a_uint32_t dev_id, a_bool_t * fail_over) -{ - union l2_global_conf_u l2_global_conf; - - memset(&l2_global_conf, 0, sizeof(l2_global_conf)); - ADPT_DEV_ID_CHECK(dev_id); - ADPT_NULL_POINT_CHECK(fail_over); - - SW_RTN_ON_ERROR(hppe_l2_global_conf_get(dev_id, &l2_global_conf)); - - *fail_over = l2_global_conf.bf.failover_en; - - return SW_OK; -} - -sw_error_t -adpt_hppe_trunk_hash_mode_get(a_uint32_t dev_id, a_uint32_t * hash_mode) -{ - union trunk_hash_field_reg_u trunk_hash_field; - - memset(&trunk_hash_field, 0, sizeof(trunk_hash_field)); - ADPT_DEV_ID_CHECK(dev_id); - ADPT_NULL_POINT_CHECK(hash_mode); - - SW_RTN_ON_ERROR(hppe_trunk_hash_field_reg_get(dev_id, &trunk_hash_field)); - - *hash_mode = 0; - - if (trunk_hash_field.bf.mac_da_incl) - *hash_mode |= FAL_TRUNK_HASH_KEY_DA; - - if (trunk_hash_field.bf.mac_sa_incl) - *hash_mode |= FAL_TRUNK_HASH_KEY_SA; - - if (trunk_hash_field.bf.src_ip_incl) - *hash_mode |= FAL_TRUNK_HASH_KEY_SIP; - - if (trunk_hash_field.bf.dst_ip_incl) - *hash_mode |= FAL_TRUNK_HASH_KEY_DIP; - - if (trunk_hash_field.bf.src_port_incl) - *hash_mode |= FAL_TRUNK_HASH_KEY_SRC_PORT; - - if (trunk_hash_field.bf.l4_src_port_incl) - *hash_mode |= FAL_TRUNK_HASH_KEY_L4_SRC_PORT; - - if (trunk_hash_field.bf.l4_dst_port_incl) - *hash_mode |= FAL_TRUNK_HASH_KEY_L4_DST_PORT; - - if (trunk_hash_field.bf.udf0_incl) - *hash_mode |= FAL_TRUNK_HASH_KEY_UDF0; - - if (trunk_hash_field.bf.udf1_incl) - *hash_mode |= FAL_TRUNK_HASH_KEY_UDF1; - - if (trunk_hash_field.bf.udf2_incl) - *hash_mode |= FAL_TRUNK_HASH_KEY_UDF2; - - if (trunk_hash_field.bf.udf3_incl) - *hash_mode |= FAL_TRUNK_HASH_KEY_UDF3; - - return SW_OK; -} - -sw_error_t -adpt_hppe_trunk_group_get(a_uint32_t dev_id, a_uint32_t trunk_id, - a_bool_t * enable, fal_pbmp_t * member) -{ - union trunk_filter_u trunk_filter; - union port_trunk_id_u port_trunk_id; - a_uint32_t port_id; - - memset(&trunk_filter, 0, sizeof(trunk_filter)); - memset(&port_trunk_id, 0, sizeof(port_trunk_id)); - - ADPT_DEV_ID_CHECK(dev_id); - ADPT_NULL_POINT_CHECK(enable); - ADPT_NULL_POINT_CHECK(member); - - *enable = A_FALSE; - for (port_id = 0; port_id < FAL_MAX_PORT_NUMBER; port_id ++) - { - SW_RTN_ON_ERROR(hppe_port_trunk_id_get(dev_id, port_id, &port_trunk_id)); - if ((trunk_id == port_trunk_id.bf.trunk_id) && (A_TRUE == port_trunk_id.bf.trunk_en)) - { - *enable = A_TRUE; - break; - } - } - - SW_RTN_ON_ERROR(hppe_trunk_filter_get(dev_id, trunk_id, &trunk_filter)); - - *member = trunk_filter.bf.mem_bitmap; - - return SW_OK; -} - -sw_error_t -adpt_hppe_trunk_group_set(a_uint32_t dev_id, a_uint32_t trunk_id, - a_bool_t enable, fal_pbmp_t member) -{ - union trunk_filter_u trunk_filter; - union port_trunk_id_u port_trunk_id; - union trunk_member_u trunk_member; - a_uint32_t i, j, cnt = 0, data[FAL_MAX_PORT_NUMBER] = {0}; - - memset(&trunk_filter, 0, sizeof(trunk_filter)); - memset(&port_trunk_id, 0, sizeof(port_trunk_id)); - memset(&trunk_member, 0, sizeof(trunk_member)); - - ADPT_DEV_ID_CHECK(dev_id); - - if (trunk_id >= TRUNK_FILTER_MAX_ENTRY) - { - return SW_OUT_OF_RANGE; - } - - if(enable == A_TRUE && member == 0) - { - SSDK_ERROR("trunk member cannot be 0 when trunk group was enabled\n"); - return SW_BAD_PARAM; - } - - if (A_TRUE == enable) - { - for (i = 0; i < FAL_MAX_PORT_NUMBER; i++) - { - if (member & (0x1 << i)) - { - if (FAL_TRUNK_GROUP_MAX_MEMEBER <= cnt) - { - return SW_BAD_PARAM; - } - data[cnt] = i; - cnt++; - } - } - } - - for (i = 0; i < FAL_MAX_PORT_NUMBER; i++) - { - SW_RTN_ON_ERROR(hppe_port_trunk_id_get(dev_id, i, &port_trunk_id)); - if (port_trunk_id.bf.trunk_id == trunk_id) { - port_trunk_id.bf.trunk_en = A_FALSE; - SW_RTN_ON_ERROR(hppe_port_trunk_id_set(dev_id, i, &port_trunk_id)); - } - } - - for (j = 0; j < FAL_MAX_PORT_NUMBER; j++) - { - if (member & (0x1 << j)) - { - port_trunk_id.bf.trunk_en = enable; - port_trunk_id.bf.trunk_id = trunk_id; - SW_RTN_ON_ERROR(hppe_port_trunk_id_set(dev_id, j, &port_trunk_id)); - } - } - - if (A_TRUE == enable) - trunk_filter.bf.mem_bitmap = member; - else - trunk_filter.bf.mem_bitmap = 0; - - SW_RTN_ON_ERROR(hppe_trunk_filter_set(dev_id, trunk_id, &trunk_filter)); - - if (A_TRUE == enable) - { - for(i = SSDK_PHYSICAL_PORT0; i <= SSDK_PHYSICAL_PORT7; i+=cnt) - { - for(j = 0; j < cnt; j++) - { - if((i+j) < FAL_MAX_PORT_NUMBER) - { - data[i+j] = data[j]; - } - } - } - } - trunk_member.bf.member_0_port_id = data[0]; - trunk_member.bf.member_1_port_id = data[1]; - trunk_member.bf.member_2_port_id = data[2]; - trunk_member.bf.member_3_port_id = data[3]; - trunk_member.bf.member_4_port_id = data[4]; - trunk_member.bf.member_5_port_id = data[5]; - trunk_member.bf.member_6_port_id = data[6]; - trunk_member.bf.member_7_port_id = data[7]; - - SW_RTN_ON_ERROR(hppe_trunk_member_set(dev_id, trunk_id, &trunk_member)); - - return SW_OK; -} -sw_error_t -adpt_hppe_trunk_fail_over_en_set(a_uint32_t dev_id, a_bool_t fail_over) -{ - union l2_global_conf_u l2_global_conf; - - memset(&l2_global_conf, 0, sizeof(l2_global_conf)); - ADPT_DEV_ID_CHECK(dev_id); - - SW_RTN_ON_ERROR(hppe_l2_global_conf_get(dev_id, &l2_global_conf)); - - l2_global_conf.bf.failover_en = fail_over; - - SW_RTN_ON_ERROR(hppe_l2_global_conf_set(dev_id, &l2_global_conf)); - - return SW_OK; -} -sw_error_t -adpt_hppe_trunk_hash_mode_set(a_uint32_t dev_id, a_uint32_t hash_mode) -{ - union trunk_hash_field_reg_u trunk_hash_field; - - memset(&trunk_hash_field, 0, sizeof(trunk_hash_field)); - ADPT_DEV_ID_CHECK(dev_id); - - if (FAL_TRUNK_HASH_KEY_DA & hash_mode) - trunk_hash_field.bf.mac_da_incl = 1; - - if (FAL_TRUNK_HASH_KEY_SA & hash_mode) - trunk_hash_field.bf.mac_sa_incl = 1; - - if (FAL_TRUNK_HASH_KEY_DIP & hash_mode) - trunk_hash_field.bf.dst_ip_incl = 1; - - if (FAL_TRUNK_HASH_KEY_SIP & hash_mode) - trunk_hash_field.bf.src_ip_incl = 1; - - if (FAL_TRUNK_HASH_KEY_SRC_PORT & hash_mode) - trunk_hash_field.bf.src_port_incl = 1; - - if (FAL_TRUNK_HASH_KEY_L4_SRC_PORT & hash_mode) - trunk_hash_field.bf.l4_src_port_incl = 1; - - if (FAL_TRUNK_HASH_KEY_L4_DST_PORT & hash_mode) - trunk_hash_field.bf.l4_dst_port_incl = 1; - - if (FAL_TRUNK_HASH_KEY_UDF0 & hash_mode) - trunk_hash_field.bf.udf0_incl = 1; - - if (FAL_TRUNK_HASH_KEY_UDF1 & hash_mode) - trunk_hash_field.bf.udf1_incl = 1; - - if (FAL_TRUNK_HASH_KEY_UDF2 & hash_mode) - trunk_hash_field.bf.udf2_incl = 1; - - if (FAL_TRUNK_HASH_KEY_UDF3 & hash_mode) - trunk_hash_field.bf.udf3_incl = 1; - - SW_RTN_ON_ERROR(hppe_trunk_hash_field_reg_set(dev_id, &trunk_hash_field)); - - return SW_OK; -} - -void adpt_hppe_trunk_func_bitmap_init(a_uint32_t dev_id) -{ - adpt_api_t *p_adpt_api = NULL; - - p_adpt_api = adpt_api_ptr_get(dev_id); - - if(p_adpt_api == NULL) - return; - - p_adpt_api->adpt_trunk_func_bitmap = ((1 << FUNC_TRUNK_GROUP_SET) | - (1 << FUNC_TRUNK_GROUP_GET) | - (1 << FUNC_TRUNK_HASH_MODE_SET) | - (1 << FUNC_TRUNK_HASH_MODE_GET) | - (1 << FUNC_TRUNK_FAILOVER_ENABLE) | - (1 << FUNC_TRUNK_FAILOVER_STATUS_GET)); - - return; -} - -static void adpt_hppe_trunk_func_unregister(a_uint32_t dev_id, adpt_api_t *p_adpt_api) -{ - if(p_adpt_api == NULL) - return; - - p_adpt_api->adpt_trunk_fail_over_en_get = NULL; - p_adpt_api->adpt_trunk_hash_mode_get = NULL; - p_adpt_api->adpt_trunk_group_get = NULL; - p_adpt_api->adpt_trunk_group_set = NULL; - p_adpt_api->adpt_trunk_fail_over_en_set = NULL; - p_adpt_api->adpt_trunk_hash_mode_set = NULL; - - return; -} - -sw_error_t adpt_hppe_trunk_init(a_uint32_t dev_id) -{ - adpt_api_t *p_adpt_api = NULL; - - p_adpt_api = adpt_api_ptr_get(dev_id); - - if(p_adpt_api == NULL) - return SW_FAIL; - - adpt_hppe_trunk_func_unregister(dev_id, p_adpt_api); - - if (p_adpt_api->adpt_trunk_func_bitmap & (1 << FUNC_TRUNK_FAILOVER_STATUS_GET)) - p_adpt_api->adpt_trunk_fail_over_en_get = adpt_hppe_trunk_fail_over_en_get; - if (p_adpt_api->adpt_trunk_func_bitmap & (1 << FUNC_TRUNK_HASH_MODE_GET)) - p_adpt_api->adpt_trunk_hash_mode_get = adpt_hppe_trunk_hash_mode_get; - if (p_adpt_api->adpt_trunk_func_bitmap & (1 << FUNC_TRUNK_GROUP_GET)) - p_adpt_api->adpt_trunk_group_get = adpt_hppe_trunk_group_get; - if (p_adpt_api->adpt_trunk_func_bitmap & (1 << FUNC_TRUNK_GROUP_SET)) - p_adpt_api->adpt_trunk_group_set = adpt_hppe_trunk_group_set; - if (p_adpt_api->adpt_trunk_func_bitmap & (1 << FUNC_TRUNK_FAILOVER_ENABLE)) - p_adpt_api->adpt_trunk_fail_over_en_set = adpt_hppe_trunk_fail_over_en_set; - if (p_adpt_api->adpt_trunk_func_bitmap & (1 << FUNC_TRUNK_HASH_MODE_SET)) - p_adpt_api->adpt_trunk_hash_mode_set = adpt_hppe_trunk_hash_mode_set; - - return SW_OK; -} - -/** - * @} - */ diff --git a/feeds/ipq807x/qca-ssdk/src/src/adpt/hppe/adpt_hppe_uniphy.c b/feeds/ipq807x/qca-ssdk/src/src/adpt/hppe/adpt_hppe_uniphy.c deleted file mode 100755 index 531d3fbef..000000000 --- a/feeds/ipq807x/qca-ssdk/src/src/adpt/hppe/adpt_hppe_uniphy.c +++ /dev/null @@ -1,765 +0,0 @@ -/* - * Copyright (c) 2017-2020, The Linux Foundation. All rights reserved. - * Permission to use, copy, modify, and/or distribute this software for - * any purpose with or without fee is hereby granted, provided that the - * above copyright notice and this permission notice appear in all copies. - * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES - * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR - * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES - * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN - * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT - * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. - */ - - -/** - * @defgroup - * @{ - */ -#include "sw.h" -#include "hppe_uniphy_reg.h" -#include "hppe_uniphy.h" -#include "hppe_init.h" -#include "ssdk_init.h" -#include "ssdk_clk.h" -#include "ssdk_dts.h" -#include "adpt.h" -#include "hppe_reg_access.h" -#include "hsl_phy.h" -#include "hsl_port_prop.h" -#include "adpt_hppe.h" -#if defined(CPPE) -#include "adpt_cppe_uniphy.h" -#include "adpt_cppe_portctrl.h" -#endif - -extern void adpt_hppe_gcc_port_speed_clock_set(a_uint32_t dev_id, - a_uint32_t port_id, fal_port_speed_t phy_speed); - -static sw_error_t -__adpt_hppe_uniphy_10g_r_linkup(a_uint32_t dev_id, a_uint32_t uniphy_index) -{ - a_uint32_t reg_value = 0; - a_uint32_t retries = 100, linkup = 0; - - union sr_xs_pcs_kr_sts1_u sr_xs_pcs_kr_sts1; - - memset(&sr_xs_pcs_kr_sts1, 0, sizeof(sr_xs_pcs_kr_sts1)); - ADPT_DEV_ID_CHECK(dev_id); - - /* wait 10G_R link up to uniphy */ - while (linkup != UNIPHY_10GR_LINKUP) { - mdelay(1); - if (retries-- == 0) - return SW_TIMEOUT; - reg_value = 0; - hppe_sr_xs_pcs_kr_sts1_get(dev_id, uniphy_index, &sr_xs_pcs_kr_sts1); - reg_value = sr_xs_pcs_kr_sts1.bf.plu; - linkup = (reg_value & UNIPHY_10GR_LINKUP); - } - - return SW_OK; -} - -sw_error_t -__adpt_hppe_uniphy_calibrate(a_uint32_t dev_id, a_uint32_t uniphy_index) -{ - a_uint32_t reg_value = 0; - a_uint32_t retries = 100, calibration_done = 0; - - union uniphy_offset_calib_4_u uniphy_offset_calib_4; - - memset(&uniphy_offset_calib_4, 0, sizeof(uniphy_offset_calib_4)); - ADPT_DEV_ID_CHECK(dev_id); - - /* wait calibration done to uniphy */ - while (calibration_done != UNIPHY_CALIBRATION_DONE) { - mdelay(1); - if (retries-- == 0) - { - SSDK_ERROR("uniphy callibration time out!\n"); - return SW_TIMEOUT; - } - reg_value = 0; - hppe_uniphy_offset_calib_4_get(dev_id, uniphy_index, &uniphy_offset_calib_4); - reg_value = uniphy_offset_calib_4.bf.mmd1_reg_calibration_done_reg; - - calibration_done = (reg_value & UNIPHY_CALIBRATION_DONE); - } - - return SW_OK; -} - -void -__adpt_hppe_gcc_uniphy_xpcs_reset(a_uint32_t dev_id, a_uint32_t uniphy_index, a_bool_t enable) -{ - enum unphy_rst_type rst_type; - enum ssdk_rst_action rst_action; - - if (uniphy_index == SSDK_UNIPHY_INSTANCE0) - rst_type = UNIPHY0_XPCS_RESET_E; - else if (uniphy_index == SSDK_UNIPHY_INSTANCE1) - rst_type = UNIPHY1_XPCS_RESET_E; - else - rst_type = UNIPHY2_XPCS_RESET_E; - - if (enable == A_TRUE) - rst_action = SSDK_RESET_ASSERT; - else - rst_action = SSDK_RESET_DEASSERT; - - ssdk_uniphy_reset(dev_id, rst_type, rst_action); - - return; -} - -void -__adpt_hppe_gcc_uniphy_software_reset(a_uint32_t dev_id, a_uint32_t uniphy_index) -{ - - enum unphy_rst_type rst_type; - - if (uniphy_index == SSDK_UNIPHY_INSTANCE0) - rst_type = UNIPHY0_SOFT_RESET_E; - else if (uniphy_index == SSDK_UNIPHY_INSTANCE1) - rst_type = UNIPHY1_SOFT_RESET_E; - else - rst_type = UNIPHY2_SOFT_RESET_E; - - ssdk_uniphy_reset(dev_id, rst_type, SSDK_RESET_ASSERT); - - msleep(100); - - ssdk_uniphy_reset(dev_id, rst_type, SSDK_RESET_DEASSERT); - - return; -} - -static sw_error_t -__adpt_hppe_uniphy_usxgmii_mode_set(a_uint32_t dev_id, a_uint32_t uniphy_index) -{ - sw_error_t rv = SW_OK; - - union uniphy_mode_ctrl_u uniphy_mode_ctrl; - union vr_xs_pcs_dig_ctrl1_u vr_xs_pcs_dig_ctrl1; - union vr_mii_an_ctrl_u vr_mii_an_ctrl; - union sr_mii_ctrl_u sr_mii_ctrl; - - memset(&uniphy_mode_ctrl, 0, sizeof(uniphy_mode_ctrl)); - memset(&vr_xs_pcs_dig_ctrl1, 0, sizeof(vr_xs_pcs_dig_ctrl1)); - memset(&vr_mii_an_ctrl, 0, sizeof(vr_mii_an_ctrl)); - memset(&sr_mii_ctrl, 0, sizeof(sr_mii_ctrl)); - ADPT_DEV_ID_CHECK(dev_id); - - hppe_uniphy_reg_set(dev_id, UNIPHY_MISC2_REG_OFFSET, - uniphy_index, UNIPHY_MISC2_REG_VALUE); - /*reset uniphy*/ - hppe_uniphy_reg_set(dev_id, UNIPHY_PLL_RESET_REG_OFFSET, - uniphy_index, UNIPHY_PLL_RESET_REG_VALUE); - msleep(500); - hppe_uniphy_reg_set(dev_id, UNIPHY_PLL_RESET_REG_OFFSET, - uniphy_index, UNIPHY_PLL_RESET_REG_DEFAULT_VALUE); - msleep(500); - - /* disable instance clock */ - qca_gcc_uniphy_port_clock_set(dev_id, uniphy_index, - 1, A_FALSE); - - /* keep xpcs to reset status */ - __adpt_hppe_gcc_uniphy_xpcs_reset(dev_id, uniphy_index, A_TRUE); - - /* configure uniphy to usxgmii mode */ - hppe_uniphy_mode_ctrl_get(dev_id, uniphy_index, &uniphy_mode_ctrl); - uniphy_mode_ctrl.bf.newaddedfromhere_ch0_psgmii_qsgmii = - UNIPHY_CH0_QSGMII_SGMII_MODE; - uniphy_mode_ctrl.bf.newaddedfromhere_ch0_qsgmii_sgmii = - UNIPHY_CH0_SGMII_MODE; - uniphy_mode_ctrl.bf.newaddedfromhere_sg_mode = - UNIPHY_SGMII_MODE_DISABLE; - uniphy_mode_ctrl.bf.newaddedfromhere_sgplus_mode = - UNIPHY_SGMIIPLUS_MODE_DISABLE; - uniphy_mode_ctrl.bf.newaddedfromhere_xpcs_mode = - UNIPHY_XPCS_MODE_ENABLE; - hppe_uniphy_mode_ctrl_set(dev_id, uniphy_index, &uniphy_mode_ctrl); - - /* configure uniphy usxgmii gcc software reset */ - if (adpt_hppe_chip_revision_get(dev_id) == CPPE_REVISION) { -#if defined(CPPE) - __adpt_cppe_gcc_uniphy_software_reset(dev_id, uniphy_index); -#endif - } else { - __adpt_hppe_gcc_uniphy_software_reset(dev_id, uniphy_index); - } - - msleep(100); - - /* wait calibration done to uniphy */ - __adpt_hppe_uniphy_calibrate(dev_id, uniphy_index); - - /* enable instance clock */ - qca_gcc_uniphy_port_clock_set(dev_id, uniphy_index, - 1, A_TRUE); - - /* release xpcs reset status */ - __adpt_hppe_gcc_uniphy_xpcs_reset(dev_id, uniphy_index, A_FALSE); - - /* wait 10g base_r link up */ - __adpt_hppe_uniphy_10g_r_linkup(dev_id, uniphy_index); - - /* enable uniphy usxgmii */ - hppe_vr_xs_pcs_dig_ctrl1_get(dev_id, uniphy_index, &vr_xs_pcs_dig_ctrl1); - vr_xs_pcs_dig_ctrl1.bf.usxg_en = 1; - hppe_vr_xs_pcs_dig_ctrl1_set(dev_id, uniphy_index, &vr_xs_pcs_dig_ctrl1); - - /* enable uniphy autoneg complete interrupt and 10M/100M 8-bits MII width */ - hppe_vr_mii_an_ctrl_get(dev_id, uniphy_index, &vr_mii_an_ctrl); - vr_mii_an_ctrl.bf.mii_an_intr_en = 1; - vr_mii_an_ctrl.bf.mii_ctrl = 1; - hppe_vr_mii_an_ctrl_set(dev_id, uniphy_index, &vr_mii_an_ctrl); - - /* enable uniphy autoneg ability and usxgmii 10g speed and full duplex */ - hppe_sr_mii_ctrl_get(dev_id, uniphy_index, &sr_mii_ctrl); - sr_mii_ctrl.bf.an_enable = 1; - sr_mii_ctrl.bf.ss5 = 0; - sr_mii_ctrl.bf.ss6 = 1; - sr_mii_ctrl.bf.ss13 = 1; - sr_mii_ctrl.bf.duplex_mode = 1; - hppe_sr_mii_ctrl_set(dev_id, uniphy_index, &sr_mii_ctrl); - - return rv; -} - -static sw_error_t -__adpt_hppe_uniphy_10g_r_mode_set(a_uint32_t dev_id, a_uint32_t uniphy_index) -{ - a_uint32_t port_id = 0; - sw_error_t rv = SW_OK; - - union uniphy_mode_ctrl_u uniphy_mode_ctrl; - union uniphy_instance_link_detect_u uniphy_instance_link_detect; - - memset(&uniphy_mode_ctrl, 0, sizeof(uniphy_mode_ctrl)); - memset(&uniphy_instance_link_detect, 0, sizeof(uniphy_instance_link_detect)); - ADPT_DEV_ID_CHECK(dev_id); - - /* keep xpcs to reset status */ - __adpt_hppe_gcc_uniphy_xpcs_reset(dev_id, uniphy_index, A_TRUE); - - /* disable instance clock */ - qca_gcc_uniphy_port_clock_set(dev_id, uniphy_index, - 1, A_FALSE); - - /* configure uniphy to 10g_r mode */ - hppe_uniphy_mode_ctrl_get(dev_id, uniphy_index, &uniphy_mode_ctrl); - - uniphy_mode_ctrl.bf.newaddedfromhere_ch0_psgmii_qsgmii = - UNIPHY_CH0_QSGMII_SGMII_MODE; - uniphy_mode_ctrl.bf.newaddedfromhere_ch0_qsgmii_sgmii = - UNIPHY_CH0_SGMII_MODE; - uniphy_mode_ctrl.bf.newaddedfromhere_sg_mode = - UNIPHY_SGMII_MODE_DISABLE; - uniphy_mode_ctrl.bf.newaddedfromhere_sgplus_mode = - UNIPHY_SGMIIPLUS_MODE_DISABLE; - uniphy_mode_ctrl.bf.newaddedfromhere_xpcs_mode = - UNIPHY_XPCS_MODE_ENABLE; - - hppe_uniphy_mode_ctrl_set(dev_id, uniphy_index, &uniphy_mode_ctrl); - - hppe_uniphy_instance_link_detect_get(dev_id, uniphy_index, &uniphy_instance_link_detect); - uniphy_instance_link_detect.bf.detect_los_from_sfp = UNIPHY_10GR_LINK_LOSS; - hppe_uniphy_instance_link_detect_set(dev_id, uniphy_index, &uniphy_instance_link_detect); - - /* configure uniphy gcc software reset */ - __adpt_hppe_gcc_uniphy_software_reset(dev_id, uniphy_index); - - /* wait uniphy calibration done */ - rv = __adpt_hppe_uniphy_calibrate(dev_id, uniphy_index); - - /* configure gcc speed clock to 10g r mode*/ - if (uniphy_index == SSDK_UNIPHY_INSTANCE1) - port_id = HPPE_MUX_PORT1; - else if (uniphy_index == SSDK_UNIPHY_INSTANCE2) - port_id = HPPE_MUX_PORT2; - adpt_hppe_gcc_port_speed_clock_set(dev_id, port_id, FAL_SPEED_10000); - - /* enable instance clock */ - qca_gcc_uniphy_port_clock_set(dev_id, uniphy_index, - 1, A_TRUE); - - /* release xpcs reset status */ - __adpt_hppe_gcc_uniphy_xpcs_reset(dev_id, uniphy_index, A_FALSE); - - return rv; -} - -static sw_error_t -__adpt_hppe_uniphy_sgmiiplus_mode_set(a_uint32_t dev_id, a_uint32_t uniphy_index) -{ - sw_error_t rv = SW_OK; - - union uniphy_mode_ctrl_u uniphy_mode_ctrl; - - memset(&uniphy_mode_ctrl, 0, sizeof(uniphy_mode_ctrl)); - ADPT_DEV_ID_CHECK(dev_id); - - SSDK_DEBUG("uniphy %d is sgmiiplus mode\n", uniphy_index); -#if defined(CPPE) - if ((adpt_hppe_chip_revision_get(dev_id) == CPPE_REVISION) - && (uniphy_index == SSDK_UNIPHY_INSTANCE0)) { - SSDK_DEBUG("cypress uniphy %d is sgmiiplus mode\n", uniphy_index); - rv = __adpt_cppe_uniphy_mode_set(dev_id, uniphy_index, - PORT_WRAPPER_SGMII_PLUS); - return rv; - } -#endif - - hppe_uniphy_reg_set(dev_id, UNIPHY_MISC2_REG_OFFSET, - uniphy_index, UNIPHY_MISC2_REG_SGMII_PLUS_MODE); - /*reset uniphy*/ - hppe_uniphy_reg_set(dev_id, UNIPHY_PLL_RESET_REG_OFFSET, - uniphy_index, UNIPHY_PLL_RESET_REG_VALUE); - msleep(500); - hppe_uniphy_reg_set(dev_id, UNIPHY_PLL_RESET_REG_OFFSET, - uniphy_index, UNIPHY_PLL_RESET_REG_DEFAULT_VALUE); - msleep(500); - - /* keep xpcs to reset status */ - __adpt_hppe_gcc_uniphy_xpcs_reset(dev_id, uniphy_index, A_TRUE); - - /* disable instance clock */ - qca_gcc_uniphy_port_clock_set(dev_id, uniphy_index, - 1, A_FALSE); - - /* configure uniphy to Athr mode and sgmiiplus mode */ - hppe_uniphy_mode_ctrl_get(dev_id, uniphy_index, &uniphy_mode_ctrl); - - uniphy_mode_ctrl.bf.newaddedfromhere_ch0_autoneg_mode = - UNIPHY_ATHEROS_NEGOTIATION; - uniphy_mode_ctrl.bf.newaddedfromhere_ch0_psgmii_qsgmii = - UNIPHY_CH0_QSGMII_SGMII_MODE; - uniphy_mode_ctrl.bf.newaddedfromhere_ch0_qsgmii_sgmii = - UNIPHY_CH0_SGMII_MODE; - uniphy_mode_ctrl.bf.newaddedfromhere_sg_mode = - UNIPHY_SGMII_MODE_DISABLE; - uniphy_mode_ctrl.bf.newaddedfromhere_sgplus_mode = - UNIPHY_SGMIIPLUS_MODE_ENABLE; - uniphy_mode_ctrl.bf.newaddedfromhere_xpcs_mode = - UNIPHY_XPCS_MODE_DISABLE; - - hppe_uniphy_mode_ctrl_set(dev_id, uniphy_index, &uniphy_mode_ctrl); - - /* configure uniphy gcc software reset */ - if (adpt_hppe_chip_revision_get(dev_id) == CPPE_REVISION) { -#if defined(CPPE) - __adpt_cppe_gcc_uniphy_software_reset(dev_id, uniphy_index); -#endif - } else { - __adpt_hppe_gcc_uniphy_software_reset(dev_id, uniphy_index); - } - - /* wait uniphy calibration done */ - rv = __adpt_hppe_uniphy_calibrate(dev_id, uniphy_index); - - /* enable instance clock */ - qca_gcc_uniphy_port_clock_set(dev_id, uniphy_index, - 1, A_TRUE); - return rv; -} - -static sw_error_t -__adpt_hppe_uniphy_sgmii_mode_set(a_uint32_t dev_id, a_uint32_t uniphy_index, a_uint32_t channel) -{ - a_uint32_t i, max_port, mode, ssdk_port; - sw_error_t rv = SW_OK; - - union uniphy_mode_ctrl_u uniphy_mode_ctrl; - a_bool_t force_port = 0; - - memset(&uniphy_mode_ctrl, 0, sizeof(uniphy_mode_ctrl)); - ADPT_DEV_ID_CHECK(dev_id); - - SSDK_DEBUG("uniphy %d is sgmii mode\n", uniphy_index); -#if defined(CPPE) - if ((uniphy_index == SSDK_UNIPHY_INSTANCE0) && - (channel == SSDK_UNIPHY_CHANNEL0)) { - if (adpt_hppe_chip_revision_get(dev_id) == CPPE_REVISION) { - if (hsl_port_prop_check(dev_id, SSDK_PHYSICAL_PORT4, - HSL_PP_EXCL_CPU) == A_TRUE) { - SSDK_DEBUG("cypress uniphy %d is sgmii mode\n", uniphy_index); - rv = __adpt_cppe_uniphy_mode_set(dev_id, - uniphy_index, PORT_WRAPPER_SGMII_CHANNEL0); - return rv; - } - } - } -#endif - - /*set the PHY mode to SGMII*/ - hppe_uniphy_reg_set(dev_id, UNIPHY_MISC2_REG_OFFSET, - uniphy_index, UNIPHY_MISC2_REG_SGMII_MODE); - /*reset uniphy*/ - hppe_uniphy_reg_set(dev_id, UNIPHY_PLL_RESET_REG_OFFSET, - uniphy_index, UNIPHY_PLL_RESET_REG_VALUE); - msleep(500); - hppe_uniphy_reg_set(dev_id, UNIPHY_PLL_RESET_REG_OFFSET, - uniphy_index, UNIPHY_PLL_RESET_REG_DEFAULT_VALUE); - msleep(500); - - /* keep xpcs to reset status */ - __adpt_hppe_gcc_uniphy_xpcs_reset(dev_id, uniphy_index, A_TRUE); - - /* disable instance clock */ - if (uniphy_index == SSDK_UNIPHY_INSTANCE0) - max_port = SSDK_PHYSICAL_PORT5; - else - max_port = SSDK_PHYSICAL_PORT1; - - for (i = SSDK_PHYSICAL_PORT1; i <= max_port; i++) - { - qca_gcc_uniphy_port_clock_set(dev_id, uniphy_index, - i, A_FALSE); - } - -#if defined(CPPE) - if ((adpt_hppe_chip_revision_get(dev_id) == CPPE_REVISION) && - (uniphy_index == SSDK_UNIPHY_INSTANCE0)) { - SSDK_DEBUG("uniphy %d sgmii channel selection\n", uniphy_index); - rv = __adpt_cppe_uniphy_channel_selection_set(dev_id, - CPPE_PCS0_CHANNEL0_SEL_PSGMII, - CPPE_PCS0_CHANNEL4_SEL_PORT5_CLOCK); - SW_RTN_ON_ERROR (rv); - } -#endif - - /* configure uniphy to Athr mode and sgmii mode */ - hppe_uniphy_mode_ctrl_get(dev_id, uniphy_index, &uniphy_mode_ctrl); - mode = ssdk_dt_global_get_mac_mode(dev_id, uniphy_index); - if(mode == PORT_WRAPPER_SGMII_FIBER) - { - uniphy_mode_ctrl.bf.newaddedfromhere_ch0_mode_ctrl_25m = 0; - } - uniphy_mode_ctrl.bf.newaddedfromhere_ch0_autoneg_mode = - UNIPHY_ATHEROS_NEGOTIATION; - uniphy_mode_ctrl.bf.newaddedfromhere_ch0_psgmii_qsgmii = - UNIPHY_CH0_QSGMII_SGMII_MODE; - uniphy_mode_ctrl.bf.newaddedfromhere_ch0_qsgmii_sgmii = - UNIPHY_CH0_SGMII_MODE; - uniphy_mode_ctrl.bf.newaddedfromhere_sgplus_mode = - UNIPHY_SGMIIPLUS_MODE_DISABLE; - uniphy_mode_ctrl.bf.newaddedfromhere_xpcs_mode = - UNIPHY_XPCS_MODE_DISABLE; - if (uniphy_index == SSDK_UNIPHY_INSTANCE0) { - uniphy_mode_ctrl.bf.newaddedfromhere_sg_mode = - UNIPHY_SGMII_MODE_DISABLE; - /* select channel as a sgmii interface */ - if (channel == SSDK_UNIPHY_CHANNEL0) - { - uniphy_mode_ctrl.bf.newaddedfromhere_ch1_ch0_sgmii = - UNIPHY_SGMII_CHANNEL1_DISABLE; - uniphy_mode_ctrl.bf.newaddedfromhere_ch4_ch1_0_sgmii = - UNIPHY_SGMII_CHANNEL4_DISABLE; - } - else if (channel == SSDK_UNIPHY_CHANNEL1) - { - uniphy_mode_ctrl.bf.newaddedfromhere_ch1_ch0_sgmii = - UNIPHY_SGMII_CHANNEL1_ENABLE; - uniphy_mode_ctrl.bf.newaddedfromhere_ch4_ch1_0_sgmii = - UNIPHY_SGMII_CHANNEL4_DISABLE; - } - else if (channel == SSDK_UNIPHY_CHANNEL4) - { - uniphy_mode_ctrl.bf.newaddedfromhere_ch1_ch0_sgmii = - UNIPHY_SGMII_CHANNEL1_DISABLE; - uniphy_mode_ctrl.bf.newaddedfromhere_ch4_ch1_0_sgmii = - UNIPHY_SGMII_CHANNEL4_ENABLE; - } - } - else - { - uniphy_mode_ctrl.bf.newaddedfromhere_sg_mode = - UNIPHY_SGMII_MODE_ENABLE; - } - hppe_uniphy_mode_ctrl_set(dev_id, uniphy_index, &uniphy_mode_ctrl); - - if (uniphy_index != SSDK_UNIPHY_INSTANCE0) { - if (uniphy_index == SSDK_UNIPHY_INSTANCE1) { - ssdk_port = SSDK_PHYSICAL_PORT5; - } else { - ssdk_port = SSDK_PHYSICAL_PORT6; - } - force_port = ssdk_port_feature_get(dev_id, - ssdk_port, PHY_F_FORCE); - if (force_port == A_TRUE) { - rv = hppe_uniphy_channel0_force_speed_mode_set(dev_id, - uniphy_index, UNIPHY_FORCE_SPEED_MODE_ENABLE); - SW_RTN_ON_ERROR (rv); - SSDK_INFO("ssdk uniphy %d connects force port\n", - uniphy_index); - } - } - /* configure uniphy gcc software reset */ - if (adpt_hppe_chip_revision_get(dev_id) == CPPE_REVISION) { -#if defined(CPPE) - __adpt_cppe_gcc_uniphy_software_reset(dev_id, uniphy_index); -#endif - } else { - __adpt_hppe_gcc_uniphy_software_reset(dev_id, uniphy_index); - } - - /* wait uniphy calibration done */ - rv = __adpt_hppe_uniphy_calibrate(dev_id, uniphy_index); - - /* enable instance clock */ - if (uniphy_index == SSDK_UNIPHY_INSTANCE0) - max_port = SSDK_PHYSICAL_PORT5; - else - max_port = SSDK_PHYSICAL_PORT1; - - for (i = SSDK_PHYSICAL_PORT1; i <= max_port; i++) - { - qca_gcc_uniphy_port_clock_set(dev_id, uniphy_index, - i, A_TRUE); - } - - return rv; -} - -static sw_error_t -__adpt_hppe_uniphy_qsgmii_mode_set(a_uint32_t dev_id, a_uint32_t uniphy_index) -{ - a_uint32_t i; - sw_error_t rv = SW_OK; - - union uniphy_mode_ctrl_u uniphy_mode_ctrl; - - memset(&uniphy_mode_ctrl, 0, sizeof(uniphy_mode_ctrl)); - ADPT_DEV_ID_CHECK(dev_id); - - /* configure malibu phy to qsgmii mode*/ - rv = hsl_port_phy_mode_set(dev_id, PORT_QSGMII); - SW_RTN_ON_ERROR (rv); - - /* keep xpcs to reset status */ - __adpt_hppe_gcc_uniphy_xpcs_reset(dev_id, uniphy_index, A_TRUE); - - /* disable instance0 clock */ - for (i = SSDK_PHYSICAL_PORT1; i < SSDK_PHYSICAL_PORT6; i++) - { - qca_gcc_uniphy_port_clock_set(dev_id, uniphy_index, - i, A_FALSE); - } - - /* configure uniphy to Athr mode and qsgmii mode */ - hppe_uniphy_mode_ctrl_get(dev_id, uniphy_index, &uniphy_mode_ctrl); - uniphy_mode_ctrl.bf.newaddedfromhere_ch0_autoneg_mode = - UNIPHY_ATHEROS_NEGOTIATION; - uniphy_mode_ctrl.bf.newaddedfromhere_ch0_psgmii_qsgmii = - UNIPHY_CH0_QSGMII_SGMII_MODE; - uniphy_mode_ctrl.bf.newaddedfromhere_ch0_qsgmii_sgmii = - UNIPHY_CH0_QSGMII_MODE; - uniphy_mode_ctrl.bf.newaddedfromhere_sg_mode = - UNIPHY_SGMII_MODE_DISABLE; - uniphy_mode_ctrl.bf.newaddedfromhere_sgplus_mode = - UNIPHY_SGMII_MODE_DISABLE; - uniphy_mode_ctrl.bf.newaddedfromhere_xpcs_mode = - UNIPHY_XPCS_MODE_DISABLE; - hppe_uniphy_mode_ctrl_set(dev_id, uniphy_index, &uniphy_mode_ctrl); - - /* configure uniphy gcc software reset */ - if (adpt_hppe_chip_revision_get(dev_id) == CPPE_REVISION) { -#if defined(CPPE) - __adpt_cppe_gcc_uniphy_software_reset(dev_id, uniphy_index); -#endif - } else { - __adpt_hppe_gcc_uniphy_software_reset(dev_id, uniphy_index); - } - - /* wait uniphy calibration done */ - rv = __adpt_hppe_uniphy_calibrate(dev_id, uniphy_index); - - rv = hsl_port_phy_serdes_reset(dev_id); - SW_RTN_ON_ERROR (rv); - - /* enable instance0 clock */ - for (i = SSDK_PHYSICAL_PORT1; i < SSDK_PHYSICAL_PORT6; i++) - { - qca_gcc_uniphy_port_clock_set(dev_id, uniphy_index, - i, A_TRUE); - } - - return rv; -} - -static sw_error_t -__adpt_hppe_uniphy_psgmii_mode_set(a_uint32_t dev_id, a_uint32_t uniphy_index) -{ - a_uint32_t i; - sw_error_t rv = SW_OK; -#if defined(CPPE) - a_uint32_t phy_type = 0; -#endif - - union uniphy_mode_ctrl_u uniphy_mode_ctrl; - - memset(&uniphy_mode_ctrl, 0, sizeof(uniphy_mode_ctrl)); - ADPT_DEV_ID_CHECK(dev_id); - - SSDK_DEBUG("uniphy %d is psgmii mode\n", uniphy_index); -#if defined(CPPE) - if (adpt_hppe_chip_revision_get(dev_id) == CPPE_REVISION) { - phy_type = hsl_port_phyid_get(dev_id, - SSDK_PHYSICAL_PORT3); - if (phy_type == MALIBU2PORT_PHY) { - SSDK_INFO("cypress uniphy %d is qca8072 psgmii mode\n", uniphy_index); - rv = __adpt_cppe_uniphy_mode_set(dev_id, uniphy_index, - PORT_WRAPPER_PSGMII); - return rv; - } - } -#endif - - /* keep xpcs to reset status */ - __adpt_hppe_gcc_uniphy_xpcs_reset(dev_id, uniphy_index, A_TRUE); - - /* disable instance0 clock */ - for (i = SSDK_PHYSICAL_PORT1; i < SSDK_PHYSICAL_PORT6; i++) - { - qca_gcc_uniphy_port_clock_set(dev_id, uniphy_index, - i, A_FALSE); - } - -#if defined(CPPE) - if ((adpt_hppe_chip_revision_get(dev_id) == CPPE_REVISION) && - (uniphy_index == SSDK_UNIPHY_INSTANCE0)) { - SSDK_INFO("uniphy %d psgmii channel selection\n", uniphy_index); - rv = __adpt_cppe_uniphy_channel_selection_set(dev_id, - CPPE_PCS0_CHANNEL0_SEL_PSGMII, - CPPE_PCS0_CHANNEL4_SEL_PORT5_CLOCK); - SW_RTN_ON_ERROR (rv); - } -#endif - - /* configure uniphy to Athr mode and psgmii mode */ - hppe_uniphy_mode_ctrl_get(dev_id, uniphy_index, &uniphy_mode_ctrl); - uniphy_mode_ctrl.bf.newaddedfromhere_ch0_autoneg_mode = - UNIPHY_ATHEROS_NEGOTIATION; - uniphy_mode_ctrl.bf.newaddedfromhere_ch0_psgmii_qsgmii = - UNIPHY_CH0_PSGMII_MODE; - uniphy_mode_ctrl.bf.newaddedfromhere_ch0_qsgmii_sgmii = - UNIPHY_CH0_SGMII_MODE; - uniphy_mode_ctrl.bf.newaddedfromhere_sg_mode = - UNIPHY_SGMII_MODE_DISABLE; - uniphy_mode_ctrl.bf.newaddedfromhere_sgplus_mode = - UNIPHY_SGMIIPLUS_MODE_DISABLE; - uniphy_mode_ctrl.bf.newaddedfromhere_xpcs_mode = - UNIPHY_XPCS_MODE_DISABLE; - hppe_uniphy_mode_ctrl_set(dev_id, uniphy_index, &uniphy_mode_ctrl); - - /* configure uniphy gcc software reset */ - if (adpt_hppe_chip_revision_get(dev_id) == CPPE_REVISION) { -#if defined(CPPE) - __adpt_cppe_gcc_uniphy_software_reset(dev_id, uniphy_index); -#endif - } else { - - __adpt_hppe_gcc_uniphy_software_reset(dev_id, uniphy_index); - } - - /* wait uniphy calibration done */ - rv = __adpt_hppe_uniphy_calibrate(dev_id, uniphy_index); - - rv = hsl_port_phy_serdes_reset(dev_id); - SW_RTN_ON_ERROR (rv); - - /* enable instance0 clock */ - for (i = SSDK_PHYSICAL_PORT1; i < SSDK_PHYSICAL_PORT6; i++) - { - qca_gcc_uniphy_port_clock_set(dev_id, uniphy_index, - i, A_TRUE); - } - - return rv; -} - -sw_error_t -adpt_hppe_uniphy_mode_set(a_uint32_t dev_id, a_uint32_t index, a_uint32_t mode) -{ - sw_error_t rv = SW_OK; - a_uint32_t clock = UNIPHY_CLK_RATE_125M; - - if (mode == PORT_WRAPPER_MAX) { - ssdk_uniphy_raw_clock_reset(index); - return SW_OK; - } - - switch(mode) { - case PORT_WRAPPER_PSGMII: - case PORT_WRAPPER_PSGMII_FIBER: - rv = __adpt_hppe_uniphy_psgmii_mode_set(dev_id, index); - break; - - case PORT_WRAPPER_QSGMII: - rv = __adpt_hppe_uniphy_qsgmii_mode_set(dev_id, index); - break; - - case PORT_WRAPPER_SGMII0_RGMII4: - case PORT_WRAPPER_SGMII_CHANNEL0: - case PORT_WRAPPER_SGMII_FIBER: - rv = __adpt_hppe_uniphy_sgmii_mode_set(dev_id, index, - SSDK_UNIPHY_CHANNEL0); - break; - - case PORT_WRAPPER_SGMII1_RGMII4: - case PORT_WRAPPER_SGMII_CHANNEL1: - rv = __adpt_hppe_uniphy_sgmii_mode_set(dev_id, index, - SSDK_UNIPHY_CHANNEL1); - break; - - case PORT_WRAPPER_SGMII4_RGMII4: - case PORT_WRAPPER_SGMII_CHANNEL4: - rv = __adpt_hppe_uniphy_sgmii_mode_set(dev_id, index, - SSDK_UNIPHY_CHANNEL4); - break; - - case PORT_WRAPPER_SGMII_PLUS: - rv = __adpt_hppe_uniphy_sgmiiplus_mode_set(dev_id, index); - clock = UNIPHY_CLK_RATE_312M; - break; - - case PORT_WRAPPER_10GBASE_R: - rv = __adpt_hppe_uniphy_10g_r_mode_set(dev_id, index); - clock = UNIPHY_CLK_RATE_312M; - break; - - case PORT_WRAPPER_USXGMII: - rv = __adpt_hppe_uniphy_usxgmii_mode_set(dev_id, index); - clock = UNIPHY_CLK_RATE_312M; - break; - - default: - rv = SW_FAIL; - } - if (SW_OK == rv) { - ssdk_uniphy_raw_clock_set(index, UNIPHY_RX, clock); - ssdk_uniphy_raw_clock_set(index, UNIPHY_TX, clock); - } - return rv; -} -sw_error_t adpt_hppe_uniphy_init(a_uint32_t dev_id) -{ - adpt_api_t *p_adpt_api = NULL; - - p_adpt_api = adpt_api_ptr_get(dev_id); - - if(p_adpt_api == NULL) - return SW_FAIL; - - p_adpt_api->adpt_uniphy_mode_set = adpt_hppe_uniphy_mode_set; - - return SW_OK; -} - -/** - * @} - */ diff --git a/feeds/ipq807x/qca-ssdk/src/src/adpt/hppe/adpt_hppe_vsi.c b/feeds/ipq807x/qca-ssdk/src/src/adpt/hppe/adpt_hppe_vsi.c deleted file mode 100755 index a81f32677..000000000 --- a/feeds/ipq807x/qca-ssdk/src/src/adpt/hppe/adpt_hppe_vsi.c +++ /dev/null @@ -1,637 +0,0 @@ -/* - * Copyright (c) 2016-2018, The Linux Foundation. All rights reserved. - * Permission to use, copy, modify, and/or distribute this software for - * any purpose with or without fee is hereby granted, provided that the - * above copyright notice and this permission notice appear in all copies. - * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES - * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR - * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES - * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN - * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT - * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. - */ - - -/** - * @defgroup - * @{ - */ -#include "sw.h" -#include "fal_type.h" -#include "adpt.h" -#include "hppe_vsi_reg.h" -#include "hppe_vsi.h" -#include "hppe_portvlan_reg.h" -#include "hppe_portvlan.h" -#include "hppe_ip_reg.h" -#include "hppe_ip.h" - -#define ADPT_VSI_MAX FAL_VSI_MAX -#define ADPT_VSI_STRIP_VLAN_TAG 2 - -enum{ - ADPT_VSI_ADD, - ADPT_VSI_DEL -}; - -static a_bool_t _adpt_hppe_vsi_xlt_match(a_uint32_t dev_id, fal_port_t port_id, - a_uint32_t stag_vid, a_uint32_t ctag_vid, union xlt_rule_tbl_u *xlt_rule) -{ - if(stag_vid != FAL_VLAN_INVALID) - { - if((xlt_rule->bf.skey_vid_incl) && - (xlt_rule->bf.skey_vid == stag_vid)) - { - if(ctag_vid != FAL_VLAN_INVALID) - { - if((xlt_rule->bf.ckey_vid_incl) && - (xlt_rule->bf.ckey_vid == ctag_vid)) - { - return A_TRUE; - } - } - else - { - if(!(xlt_rule->bf.ckey_vid_incl)) - { - return A_TRUE; - } - } - } - } - else - { - if(!(xlt_rule->bf.skey_vid_incl)) - { - if(ctag_vid != FAL_VLAN_INVALID) - { - if((xlt_rule->bf.ckey_vid_incl) && - (xlt_rule->bf.ckey_vid == ctag_vid)) - { - return A_TRUE; - } - } - else - { - if(!(xlt_rule->bf.ckey_vid_incl)) - { - return A_TRUE; - } - } - } - } - return A_FALSE; -} - -static sw_error_t _adpt_hppe_vsi_xlt_update(a_uint32_t dev_id, - a_uint32_t vsi_id, a_uint32_t port_id, - a_uint32_t stag_vid, a_uint32_t ctag_vid, - a_uint32_t op) -{ - a_int32_t index = 0; - a_uint32_t new_entry = 0; - sw_error_t rv; - union xlt_rule_tbl_u xlt_rule; - union xlt_action_tbl_u xlt_action; - - /*printk("%s,%d: port_id 0x%x svlan %d cvlan %d vsi %d op %d\n", - __FUNCTION__, __LINE__, port_id, stag_vid, ctag_vid, vsi_id, op);*/ - - for(index = XLT_RULE_TBL_NUM - 1; index >= 0; index--) - { - rv = hppe_xlt_rule_tbl_get(dev_id, index, &xlt_rule); - if( rv != SW_OK ) - return rv; - rv = hppe_xlt_action_tbl_get(dev_id, index, &xlt_action); - if( rv != SW_OK ) - return rv; - if(xlt_rule.bf.valid == A_FALSE && index >= new_entry) - { - new_entry = index; - } - if(xlt_rule.bf.valid == A_TRUE) - { - if(_adpt_hppe_vsi_xlt_match(dev_id, port_id, - stag_vid, ctag_vid, &xlt_rule)) - { - if((xlt_action.bf.vsi_cmd == A_TRUE) && - (xlt_action.bf.vsi == vsi_id)) - break; - } - } - } - - if(index >= 0) /*found*/ - { - if(op == ADPT_VSI_DEL)/*Delete*/ - { - /*printk("%s,%d: port_id 0x%x svlan %d cvlan %d vsi %d op %d\n", - __FUNCTION__, __LINE__, port_id, stag_vid, ctag_vid, vsi_id, op);*/ - if(!(xlt_rule.bf.port_bitmap & (1<= XLT_RULE_TBL_NUM) - { - printk("%s,%d: port_id 0x%x svlan %d cvlan %d vsi %d xlt table is full\n", - __FUNCTION__, __LINE__, port_id, stag_vid, ctag_vid, vsi_id); - return SW_NO_RESOURCE; - } - else/*new entry exist*/ - { - aos_mem_zero(&xlt_rule, sizeof(union xlt_rule_tbl_u)); - /*printk("%s,%d: port_id 0x%x svlan %d cvlan %d vsi %d xlt table add index %d\n", - __FUNCTION__, __LINE__, port_id, stag_vid, ctag_vid, vsi_id, new_entry);*/ - xlt_rule.bf.valid = A_TRUE; - if(ctag_vid != FAL_VLAN_INVALID) - { - xlt_rule.bf.ckey_vid_incl = A_TRUE; - xlt_rule.bf.ckey_vid = ctag_vid; - if(ctag_vid == 0) - xlt_rule.bf.ckey_fmt_1 = 0x1; - else - xlt_rule.bf.ckey_fmt_1 = 0x2; - } - else - xlt_rule.bf.ckey_fmt_0 = 0x1; - if(stag_vid != FAL_VLAN_INVALID) - { - xlt_rule.bf.skey_vid_incl = A_TRUE; - xlt_rule.bf.skey_vid = stag_vid; - if(stag_vid == 0) - xlt_rule.bf.skey_fmt = 0x2; - else - xlt_rule.bf.skey_fmt = 0x4; - } - else - xlt_rule.bf.skey_fmt = 0x1; - xlt_rule.bf.port_bitmap = (1< FAL_VLAN_MAX)|| - (ctag_vid != FAL_VLAN_INVALID && ctag_vid > FAL_VLAN_MAX)) - return SW_OUT_OF_RANGE; - - adpt_hppe_port_vlan_vsi_get(dev_id, port_id, stag_vid, ctag_vid, &org_vsi); - - if(org_vsi == vsi_id) - return SW_OK; - - if(FAL_VSI_INVALID == vsi_id || org_vsi != FAL_VSI_INVALID) - { - rv = _adpt_hppe_vsi_xlt_update(dev_id, org_vsi, port_id, - stag_vid, ctag_vid, ADPT_VSI_DEL); - if(rv != SW_OK) - return rv; - } - if(vsi_id != FAL_VSI_INVALID) - { - rv = _adpt_hppe_vsi_xlt_update(dev_id, vsi_id, port_id, - stag_vid, ctag_vid, ADPT_VSI_ADD); - } - - return rv; -} - - -#ifndef IN_VSI_MINI -sw_error_t -adpt_hppe_port_vsi_get(a_uint32_t dev_id, fal_port_t port_id, a_uint32_t *vsi_id) -{ - union l3_vp_port_tbl_u l3_vp_port_tbl; - sw_error_t rv; - - ADPT_DEV_ID_CHECK(dev_id); - //printk("%s, %d: port %d, vsi %d\n", __FUNCTION__, __LINE__, port_id, vsi_id); - if(!(FAL_IS_PPORT(port_id)) && !(FAL_IS_VPORT(port_id))) - return SW_BAD_VALUE; - - rv = hppe_l3_vp_port_tbl_get(dev_id, FAL_PORT_ID_VALUE(port_id), &l3_vp_port_tbl); - if (SW_OK != rv) - return rv; - if(l3_vp_port_tbl.bf.vsi_valid) - *vsi_id = l3_vp_port_tbl.bf.vsi; - else - *vsi_id = FAL_VSI_INVALID; - - return rv; -} -#endif - -sw_error_t -adpt_hppe_port_vsi_set(a_uint32_t dev_id, fal_port_t port_id, a_uint32_t vsi_id) -{ - union l3_vp_port_tbl_u l3_vp_port_tbl; - sw_error_t rv; - - ADPT_DEV_ID_CHECK(dev_id); - //printk("%s, %d: port %d, vsi %d\n", __FUNCTION__, __LINE__, port_id, vsi_id); - if(!(FAL_IS_PPORT(port_id)) && !(FAL_IS_VPORT(port_id))) - return SW_BAD_VALUE; - - rv = hppe_l3_vp_port_tbl_get(dev_id, FAL_PORT_ID_VALUE(port_id), &l3_vp_port_tbl); - if (SW_OK != rv) - return rv; - if(FAL_VSI_INVALID == vsi_id) - { - l3_vp_port_tbl.bf.vsi_valid = A_FALSE; - l3_vp_port_tbl.bf.vsi = 0; - } - else - { - l3_vp_port_tbl.bf.vsi_valid = A_TRUE; - l3_vp_port_tbl.bf.vsi = vsi_id; - } - rv = hppe_l3_vp_port_tbl_set(dev_id, FAL_PORT_ID_VALUE(port_id), &l3_vp_port_tbl); - if( rv != SW_OK ) - return rv; - //printk("%s, %d: port %d, vsi %d\n", __FUNCTION__, __LINE__, port_id, vsi_id); - - return rv; -} - -sw_error_t -adpt_hppe_vsi_stamove_set(a_uint32_t dev_id, a_uint32_t vsi_id, fal_vsi_stamove_t *stamove) -{ - sw_error_t rv; - union vsi_tbl_u vsi_tbl; - - ADPT_DEV_ID_CHECK(dev_id); - ADPT_NULL_POINT_CHECK(stamove); - - rv = hppe_vsi_tbl_get( dev_id, vsi_id, &vsi_tbl); - if( rv != SW_OK ) - return rv; - - vsi_tbl.bf.station_move_lrn_en = stamove->stamove_en; - vsi_tbl.bf.station_move_fwd_cmd = stamove->action; - - rv = hppe_vsi_tbl_set( dev_id, vsi_id, &vsi_tbl); - if( rv != SW_OK ) - return rv; - - return SW_OK; -} -#ifndef IN_VSI_MINI -sw_error_t -adpt_hppe_vsi_stamove_get(a_uint32_t dev_id, a_uint32_t vsi_id, fal_vsi_stamove_t *stamove) -{ - sw_error_t rv; - union vsi_tbl_u vsi_tbl; - - ADPT_DEV_ID_CHECK(dev_id); - ADPT_NULL_POINT_CHECK(stamove); - - rv = hppe_vsi_tbl_get( dev_id, vsi_id, &vsi_tbl); - if( rv != SW_OK ) - return rv; - - stamove->stamove_en = vsi_tbl.bf.station_move_lrn_en; - stamove->action = vsi_tbl.bf.station_move_fwd_cmd; - - return SW_OK; -} - -sw_error_t -adpt_hppe_vsi_newaddr_lrn_get(a_uint32_t dev_id, a_uint32_t vsi_id, fal_vsi_newaddr_lrn_t *newaddr_lrn) -{ - sw_error_t rv; - union vsi_tbl_u vsi_tbl; - - ADPT_DEV_ID_CHECK(dev_id); - ADPT_NULL_POINT_CHECK(newaddr_lrn); - - rv = hppe_vsi_tbl_get( dev_id, vsi_id, &vsi_tbl); - if( rv != SW_OK ) - return rv; - - newaddr_lrn->lrn_en = vsi_tbl.bf.new_addr_lrn_en; - newaddr_lrn->action = vsi_tbl.bf.new_addr_fwd_cmd; - - return SW_OK; -} -#endif - -sw_error_t -adpt_hppe_vsi_newaddr_lrn_set(a_uint32_t dev_id, a_uint32_t vsi_id, fal_vsi_newaddr_lrn_t *newaddr_lrn) -{ - sw_error_t rv; - union vsi_tbl_u vsi_tbl; - - ADPT_DEV_ID_CHECK(dev_id); - ADPT_NULL_POINT_CHECK(newaddr_lrn); - - rv = hppe_vsi_tbl_get( dev_id, vsi_id, &vsi_tbl); - if( rv != SW_OK ) - return rv; - - vsi_tbl.bf.new_addr_lrn_en = newaddr_lrn->lrn_en; - vsi_tbl.bf.new_addr_fwd_cmd = newaddr_lrn->action; - - rv = hppe_vsi_tbl_set( dev_id, vsi_id, &vsi_tbl); - if( rv != SW_OK ) - return rv; - - return SW_OK; -} - -sw_error_t -adpt_hppe_vsi_member_set(a_uint32_t dev_id, a_uint32_t vsi_id, fal_vsi_member_t *vsi_member) -{ - sw_error_t rv; - union vsi_tbl_u vsi_tbl; - - ADPT_DEV_ID_CHECK(dev_id); - ADPT_NULL_POINT_CHECK(vsi_member); - - rv = hppe_vsi_tbl_get( dev_id, vsi_id, &vsi_tbl); - if( rv != SW_OK ) - return rv; - - vsi_tbl.bf.bc_bitmap = vsi_member->bc_ports & 0xff; - vsi_tbl.bf.member_port_bitmap = vsi_member->member_ports & 0xff; - vsi_tbl.bf.umc_bitmap = vsi_member->umc_ports & 0xff; - vsi_tbl.bf.uuc_bitmap = vsi_member->uuc_ports & 0xff; - - rv = hppe_vsi_tbl_set(dev_id, vsi_id, &vsi_tbl); - if( rv != SW_OK ) - return rv; - - return SW_OK; - -} - -sw_error_t -adpt_hppe_vsi_member_get(a_uint32_t dev_id, a_uint32_t vsi_id, fal_vsi_member_t *vsi_member) -{ - sw_error_t rv; - union vsi_tbl_u vsi_tbl; - - ADPT_DEV_ID_CHECK(dev_id); - ADPT_NULL_POINT_CHECK(vsi_member); - - rv = hppe_vsi_tbl_get( dev_id, vsi_id, &vsi_tbl); - if( rv != SW_OK ) - return rv; - - vsi_member->bc_ports = vsi_tbl.bf.bc_bitmap; - vsi_member->member_ports = vsi_tbl.bf.member_port_bitmap; - vsi_member->umc_ports = vsi_tbl.bf.umc_bitmap; - vsi_member->uuc_ports = vsi_tbl.bf.uuc_bitmap; - - rv = hppe_vsi_tbl_set(dev_id, vsi_id, &vsi_tbl); - if( rv != SW_OK ) - return rv; - - return SW_OK; - -} - -#ifndef IN_VSI_MINI -sw_error_t -adpt_hppe_vsi_counter_get(a_uint32_t dev_id, a_uint32_t vsi_id, fal_vsi_counter_t *counter) -{ - sw_error_t rv; - union vlan_cnt_tbl_u in_cnt; - union eg_vsi_counter_tbl_u eg_cnt; - union pre_l2_cnt_tbl_u pre_l2_cnt; - - ADPT_DEV_ID_CHECK(dev_id); - ADPT_NULL_POINT_CHECK(counter); - - rv = hppe_vlan_cnt_tbl_get(dev_id, vsi_id, &in_cnt); - if( rv != SW_OK ) - return rv; - - counter->rx_packet_counter = in_cnt.bf.rx_pkt_cnt; - counter->rx_byte_counter = in_cnt.bf.rx_byte_cnt_1; - counter->rx_byte_counter = (counter->rx_byte_counter<<32)|in_cnt.bf.rx_byte_cnt_0; - - rv = hppe_eg_vsi_counter_tbl_get(dev_id, vsi_id, &eg_cnt); - if( rv != SW_OK ) - return rv; - - counter->tx_packet_counter = eg_cnt.bf.tx_packets; - counter->tx_byte_counter = eg_cnt.bf.tx_bytes_1; - counter->tx_byte_counter = (counter->tx_byte_counter<<32)|eg_cnt.bf.tx_bytes_0; - - rv = hppe_pre_l2_cnt_tbl_get(dev_id, vsi_id, &pre_l2_cnt); - if( rv != SW_OK ) - return rv; - - counter->fwd_packet_counter = pre_l2_cnt.bf.rx_pkt_cnt; - counter->fwd_byte_counter = pre_l2_cnt.bf.rx_byte_cnt_1; - counter->fwd_byte_counter = (counter->fwd_byte_counter<<32)|pre_l2_cnt.bf.rx_byte_cnt_0; - counter->drop_packet_counter = pre_l2_cnt.bf.rx_drop_pkt_cnt_1<<24|pre_l2_cnt.bf.rx_drop_pkt_cnt_0; - counter->drop_byte_counter = pre_l2_cnt.bf.rx_drop_byte_cnt_1; - counter->drop_byte_counter = (counter->drop_byte_counter<<24)|pre_l2_cnt.bf.rx_drop_byte_cnt_0; - - return SW_OK; -} - -sw_error_t -adpt_hppe_vsi_counter_cleanup(a_uint32_t dev_id, a_uint32_t vsi_id) -{ - sw_error_t rv; - union vlan_cnt_tbl_u in_cnt; - union eg_vsi_counter_tbl_u eg_cnt; - union pre_l2_cnt_tbl_u pre_l2_cnt; - - ADPT_DEV_ID_CHECK(dev_id); - - memset(&in_cnt, 0, sizeof(in_cnt)); - rv = hppe_vlan_cnt_tbl_set(dev_id, vsi_id, &in_cnt); - if( rv != SW_OK ) - return rv; - - memset(&eg_cnt, 0, sizeof(eg_cnt)); - rv = hppe_eg_vsi_counter_tbl_set(dev_id, vsi_id, &eg_cnt); - if( rv != SW_OK ) - return rv; - - memset(&pre_l2_cnt, 0, sizeof(pre_l2_cnt)); - rv = hppe_pre_l2_cnt_tbl_set(dev_id, vsi_id, &pre_l2_cnt); - if( rv != SW_OK ) - return rv; - - return SW_OK; -} -#endif - - -void adpt_hppe_vsi_func_bitmap_init(a_uint32_t dev_id) -{ - adpt_api_t *p_adpt_api = NULL; - - p_adpt_api = adpt_api_ptr_get(dev_id); - - if(p_adpt_api == NULL) - return; - - - p_adpt_api->adpt_vsi_func_bitmap = ((1<adpt_port_vlan_vsi_set = NULL; - p_adpt_api->adpt_port_vlan_vsi_get = NULL; - p_adpt_api->adpt_port_vsi_set = NULL; - p_adpt_api->adpt_port_vsi_get = NULL; - p_adpt_api->adpt_vsi_stamove_set = NULL; - p_adpt_api->adpt_vsi_stamove_get = NULL; - p_adpt_api->adpt_vsi_newaddr_lrn_get = NULL; - p_adpt_api->adpt_vsi_newaddr_lrn_set = NULL; - p_adpt_api->adpt_vsi_member_set = NULL; - p_adpt_api->adpt_vsi_member_get = NULL; - p_adpt_api->adpt_vsi_counter_get = NULL; - p_adpt_api->adpt_vsi_counter_cleanup = NULL; - - return; -} - - -sw_error_t adpt_hppe_vsi_init(a_uint32_t dev_id) -{ - adpt_api_t *p_adpt_api = NULL; - - p_adpt_api = adpt_api_ptr_get(dev_id); - - if(p_adpt_api == NULL) - return SW_FAIL; - - adpt_hppe_vsi_func_unregister(dev_id, p_adpt_api); - -#ifndef IN_VSI_MINI - if(p_adpt_api->adpt_vsi_func_bitmap & (1<adpt_port_vsi_get = adpt_hppe_port_vsi_get; - if(p_adpt_api->adpt_vsi_func_bitmap & (1<adpt_vsi_stamove_get = adpt_hppe_vsi_stamove_get; - if(p_adpt_api->adpt_vsi_func_bitmap & (1<adpt_vsi_newaddr_lrn_get = adpt_hppe_vsi_newaddr_lrn_get; - if(p_adpt_api->adpt_vsi_func_bitmap & (1<adpt_vsi_counter_get = adpt_hppe_vsi_counter_get; - if(p_adpt_api->adpt_vsi_func_bitmap & (1<adpt_vsi_counter_cleanup = adpt_hppe_vsi_counter_cleanup; -#endif - if(p_adpt_api->adpt_vsi_func_bitmap & (1<adpt_port_vlan_vsi_set = adpt_hppe_port_vlan_vsi_set; - if(p_adpt_api->adpt_vsi_func_bitmap & (1<adpt_port_vlan_vsi_get = adpt_hppe_port_vlan_vsi_get; - if(p_adpt_api->adpt_vsi_func_bitmap & (1<adpt_port_vsi_set = adpt_hppe_port_vsi_set; - if(p_adpt_api->adpt_vsi_func_bitmap & (1<adpt_vsi_stamove_set = adpt_hppe_vsi_stamove_set; - if(p_adpt_api->adpt_vsi_func_bitmap & (1<adpt_vsi_newaddr_lrn_set = adpt_hppe_vsi_newaddr_lrn_set; - if(p_adpt_api->adpt_vsi_func_bitmap & (1<adpt_vsi_member_set = adpt_hppe_vsi_member_set; - if(p_adpt_api->adpt_vsi_func_bitmap & (1<adpt_vsi_member_get = adpt_hppe_vsi_member_get; - - return SW_OK; -} - -/** - * @} - */ diff --git a/feeds/ipq807x/qca-ssdk/src/src/adpt/mp/Makefile b/feeds/ipq807x/qca-ssdk/src/src/adpt/mp/Makefile deleted file mode 100644 index df13503d5..000000000 --- a/feeds/ipq807x/qca-ssdk/src/src/adpt/mp/Makefile +++ /dev/null @@ -1,32 +0,0 @@ -LOC_DIR=src/adpt/mp -LIB=ADPT - -include $(PRJ_PATH)/make/config.mk - -SRC_LIST=adpt_mp_interrupt.c - -ifeq (TRUE, $(IN_MIB)) - SRC_LIST += adpt_mp_mib.c -endif - -ifeq (TRUE, $(IN_PORTCONTROL)) - SRC_LIST += adpt_mp_portctrl.c -endif - -ifeq (TRUE, $(IN_UNIPHY)) - SRC_LIST += adpt_mp_uniphy.c -endif - -ifeq (TRUE, $(IN_LED)) - SRC_LIST += adpt_mp_led.c -endif - -ifeq (, $(filter MP, $(SUPPORT_CHIP))) - SRC_LIST= -endif - -include $(PRJ_PATH)/make/components.mk -include $(PRJ_PATH)/make/defs.mk -include $(PRJ_PATH)/make/target.mk - -all: dep obj diff --git a/feeds/ipq807x/qca-ssdk/src/src/adpt/mp/adpt_mp_interrupt.c b/feeds/ipq807x/qca-ssdk/src/src/adpt/mp/adpt_mp_interrupt.c deleted file mode 100755 index 3e8ca50c2..000000000 --- a/feeds/ipq807x/qca-ssdk/src/src/adpt/mp/adpt_mp_interrupt.c +++ /dev/null @@ -1,119 +0,0 @@ -/* - * Copyright (c) 2020, The Linux Foundation. All rights reserved. - * - * Permission to use, copy, modify, and/or distribute this software for any - * purpose with or without fee is hereby granted, provided that the above - * copyright notice and this permission notice appear in all copies. - * - * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES - * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR - * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES - * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN - * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF - * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. - */ - -#include "sw.h" -#include "adpt.h" -#include "hsl.h" -#include "hsl_dev.h" -#include "hsl_phy.h" -#include "hsl_port_prop.h" -#include "adpt_mp.h" - -static sw_error_t -adpt_mp_intr_port_link_mask_set(a_uint32_t dev_id, a_uint32_t port_id, - a_uint32_t intr_mask_flag) -{ - sw_error_t rv; - a_uint32_t phy_id; - hsl_phy_ops_t *phy_drv; - - HSL_DEV_ID_CHECK(dev_id); - - if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_PHY)) - { - return SW_BAD_PARAM; - } - - SW_RTN_ON_NULL (phy_drv = hsl_phy_api_ops_get (dev_id, port_id)); - SW_RTN_ON_NULL (phy_drv->phy_intr_mask_set); - - rv = hsl_port_prop_get_phyid(dev_id, port_id, &phy_id); - SW_RTN_ON_ERROR(rv); - - rv = phy_drv->phy_intr_mask_set(dev_id, phy_id, intr_mask_flag); - - return rv; -} - -static sw_error_t -adpt_mp_intr_port_link_mask_get(a_uint32_t dev_id, a_uint32_t port_id, - a_uint32_t * intr_mask_flag) -{ - sw_error_t rv; - a_uint32_t phy_id; - hsl_phy_ops_t *phy_drv; - - HSL_DEV_ID_CHECK(dev_id); - - if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_PHY)) - { - return SW_BAD_PARAM; - } - - SW_RTN_ON_NULL (phy_drv = hsl_phy_api_ops_get (dev_id, port_id)); - SW_RTN_ON_NULL (phy_drv->phy_intr_mask_get); - - rv = hsl_port_prop_get_phyid(dev_id, port_id, &phy_id); - SW_RTN_ON_ERROR(rv); - - rv = phy_drv->phy_intr_mask_get(dev_id, phy_id, intr_mask_flag); - - return rv; -} - -static sw_error_t -adpt_mp_intr_port_link_status_get(a_uint32_t dev_id, a_uint32_t port_id, - a_uint32_t * intr_status) -{ - sw_error_t rv; - a_uint32_t phy_id; - hsl_phy_ops_t *phy_drv; - - HSL_DEV_ID_CHECK(dev_id); - - if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_PHY)) - { - return SW_BAD_PARAM; - } - - SW_RTN_ON_NULL (phy_drv = hsl_phy_api_ops_get (dev_id, port_id)); - SW_RTN_ON_NULL (phy_drv->phy_intr_status_get); - - rv = hsl_port_prop_get_phyid(dev_id, port_id, &phy_id); - SW_RTN_ON_ERROR(rv); - - rv = phy_drv->phy_intr_status_get(dev_id, phy_id, intr_status); - - return rv; -} - -sw_error_t adpt_mp_intr_init(a_uint32_t dev_id) -{ - adpt_api_t *p_adpt_api = NULL; - - p_adpt_api = adpt_api_ptr_get(dev_id); - - SW_RTN_ON_NULL (p_adpt_api); - - p_adpt_api->adpt_intr_port_link_mask_set = adpt_mp_intr_port_link_mask_set; - p_adpt_api->adpt_intr_port_link_mask_get = adpt_mp_intr_port_link_mask_get; - p_adpt_api->adpt_intr_port_link_status_get = adpt_mp_intr_port_link_status_get; - - return SW_OK; -} -/** - * @} - */ diff --git a/feeds/ipq807x/qca-ssdk/src/src/adpt/mp/adpt_mp_led.c b/feeds/ipq807x/qca-ssdk/src/src/adpt/mp/adpt_mp_led.c deleted file mode 100644 index 335d2ce09..000000000 --- a/feeds/ipq807x/qca-ssdk/src/src/adpt/mp/adpt_mp_led.c +++ /dev/null @@ -1,138 +0,0 @@ -/* - * Copyright (c) 2020, The Linux Foundation. All rights reserved. - * - * Permission to use, copy, modify, and/or distribute this software for any - * purpose with or without fee is hereby granted, provided that the above - * copyright notice and this permission notice appear in all copies. - * - * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES - * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR - * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES - * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN - * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF - * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. - */ - -#include "sw.h" -#include "adpt.h" -#include "hsl.h" -#include "hsl_dev.h" -#include "hsl_phy.h" -#include "hsl_port_prop.h" -#include "adpt_mp.h" - -static sw_error_t -adpt_mp_led_ctrl_pattern_set(a_uint32_t dev_id, led_pattern_group_t group, - led_pattern_id_t led_pattern_id, led_ctrl_pattern_t * pattern) -{ - sw_error_t rv; - a_uint32_t phy_addr, port_id; - hsl_phy_ops_t *phy_drv; - - HSL_DEV_ID_CHECK(dev_id); - - if(group != LED_LAN_PORT_GROUP && group != LED_WAN_PORT_GROUP) - { - SSDK_ERROR("group %x is not supported\n", group); - return SW_NOT_SUPPORTED; - } - port_id = led_pattern_id; - if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_PHY)) - { - return SW_BAD_PARAM; - } - - SW_RTN_ON_NULL (phy_drv = hsl_phy_api_ops_get (dev_id, port_id)); - SW_RTN_ON_NULL (phy_drv->phy_led_ctrl_pattern_set); - - rv = hsl_port_prop_get_phyid(dev_id, port_id, &phy_addr); - SW_RTN_ON_ERROR(rv); - - rv = phy_drv->phy_led_ctrl_pattern_set(dev_id, phy_addr, pattern); - - return rv; -} - -static sw_error_t -adpt_mp_led_ctrl_pattern_get(a_uint32_t dev_id, led_pattern_group_t group, - led_pattern_id_t led_pattern_id, led_ctrl_pattern_t * pattern) -{ - sw_error_t rv; - a_uint32_t phy_addr, port_id; - hsl_phy_ops_t *phy_drv; - - HSL_DEV_ID_CHECK(dev_id); - - if(group != LED_LAN_PORT_GROUP && group != LED_WAN_PORT_GROUP) - { - SSDK_ERROR("group %x is not supported\n", group); - return SW_NOT_SUPPORTED; - } - - port_id = led_pattern_id; - - if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_PHY)) - { - return SW_BAD_PARAM; - } - - SW_RTN_ON_NULL (phy_drv = hsl_phy_api_ops_get (dev_id, port_id)); - SW_RTN_ON_NULL (phy_drv->phy_led_ctrl_pattern_get); - - rv = hsl_port_prop_get_phyid(dev_id, port_id, &phy_addr); - SW_RTN_ON_ERROR(rv); - - rv = phy_drv->phy_led_ctrl_pattern_get(dev_id, phy_addr, pattern); - - return rv; -} - -static sw_error_t -adpt_mp_led_ctrl_source_set(a_uint32_t dev_id, a_uint32_t source_id, - led_ctrl_pattern_t *pattern) -{ - sw_error_t rv; - a_uint32_t phy_addr, port_id; - hsl_phy_ops_t *phy_drv; - - HSL_DEV_ID_CHECK(dev_id); - - /*one port can support max three led source*/ - port_id = source_id/PORT_LED_SOURCE_MAX+1; - source_id = source_id%PORT_LED_SOURCE_MAX; - - if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_PHY)) - { - return SW_BAD_PARAM; - } - - SW_RTN_ON_NULL (phy_drv = hsl_phy_api_ops_get (dev_id, port_id)); - SW_RTN_ON_NULL (phy_drv->phy_led_ctrl_source_set); - - rv = hsl_port_prop_get_phyid(dev_id, port_id, &phy_addr); - SW_RTN_ON_ERROR(rv); - - rv = phy_drv->phy_led_ctrl_source_set(dev_id, phy_addr, source_id, - pattern); - - return rv; -} - -sw_error_t adpt_mp_led_init(a_uint32_t dev_id) -{ - adpt_api_t *p_adpt_api = NULL; - - p_adpt_api = adpt_api_ptr_get(dev_id); - - SW_RTN_ON_NULL (p_adpt_api); - - p_adpt_api->adpt_led_ctrl_pattern_set = adpt_mp_led_ctrl_pattern_set; - p_adpt_api->adpt_led_ctrl_pattern_get = adpt_mp_led_ctrl_pattern_get; - p_adpt_api->adpt_led_ctrl_source_set = adpt_mp_led_ctrl_source_set; - - return SW_OK; -} -/** - * @} - */ diff --git a/feeds/ipq807x/qca-ssdk/src/src/adpt/mp/adpt_mp_mib.c b/feeds/ipq807x/qca-ssdk/src/src/adpt/mp/adpt_mp_mib.c deleted file mode 100755 index 8aa84d01e..000000000 --- a/feeds/ipq807x/qca-ssdk/src/src/adpt/mp/adpt_mp_mib.c +++ /dev/null @@ -1,360 +0,0 @@ -/* - * Copyright (c) 2020, The Linux Foundation. All rights reserved. - * - * Permission to use, copy, modify, and/or distribute this software for any - * purpose with or without fee is hereby granted, provided that the above - * copyright notice and this permission notice appear in all copies. - * - * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES - * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR - * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES - * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN - * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF - * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. - */ - -#include "sw.h" -#include "mp_mib_reg.h" -#include "mp_mib.h" -#include "adpt.h" -#include "adpt_mp.h" - -sw_error_t -adpt_mp_mib_cpukeep_get(a_uint32_t dev_id, a_bool_t *enable) -{ - sw_error_t rv = SW_OK; - union mmc_control_u mmc_control; - - ADPT_DEV_ID_CHECK(dev_id); - ADPT_NULL_POINT_CHECK(enable); - - rv = mp_mmc_control_get(dev_id, MP_GMAC0, &mmc_control); - SW_RTN_ON_ERROR(rv); - if(mmc_control.bf.rstonrd) - { - *enable = A_FALSE; - } - else - { - *enable = A_TRUE; - } - - return rv; -} - -sw_error_t -adpt_mp_mib_cpukeep_set(a_uint32_t dev_id, a_bool_t enable) -{ - sw_error_t rv = SW_OK; - a_uint32_t gmac_id = 0, status = 0; - union mmc_control_u mmc_control; - - ADPT_DEV_ID_CHECK(dev_id); - - if (enable == A_TRUE) - { - status = A_FALSE; - } - else - { - status = A_TRUE; - } - for(gmac_id = MP_GMAC0; gmac_id <= MP_GMAC1; gmac_id++) - { - rv = mp_mmc_control_get(dev_id, gmac_id, &mmc_control); - SW_RTN_ON_ERROR(rv); - mmc_control.bf.rstonrd = status; - rv = mp_mmc_control_set(dev_id, gmac_id, &mmc_control); - SW_RTN_ON_ERROR(rv); - } - - return rv; -} - -sw_error_t -adpt_mp_mib_status_get(a_uint32_t dev_id, a_bool_t *enable) -{ - sw_error_t rv = SW_OK; - union mmc_control_u mmc_control; - - ADPT_DEV_ID_CHECK(dev_id); - ADPT_NULL_POINT_CHECK(enable); - - rv = mp_mmc_control_get(dev_id, MP_GMAC0, &mmc_control); - SW_RTN_ON_ERROR(rv); - if(mmc_control.bf.cntfreez) - { - *enable = A_FALSE; - } - else - { - *enable = A_TRUE; - } - - return rv; -} - -sw_error_t -adpt_mp_mib_status_set(a_uint32_t dev_id, a_bool_t enable) -{ - sw_error_t rv = SW_OK; - a_uint32_t gmac_id = 0, status = 0; - union mmc_control_u mmc_control; - - ADPT_DEV_ID_CHECK(dev_id); - - if (enable == A_TRUE) - { - status = A_FALSE; - } - else - { - status = A_TRUE; - } - for(gmac_id = MP_GMAC0; gmac_id <= MP_GMAC1; gmac_id++) - { - rv = mp_mmc_control_get(dev_id, gmac_id, &mmc_control); - SW_RTN_ON_ERROR(rv); - mmc_control.bf.cntfreez = status; - rv = mp_mmc_control_set(dev_id, gmac_id, &mmc_control); - SW_RTN_ON_ERROR(rv); - } - - return rv; -} - -sw_error_t -adpt_mp_mib_port_flush_counters(a_uint32_t dev_id, fal_port_t port_id) -{ - sw_error_t rv = SW_OK; - a_uint32_t gmac_id = 0; - union mmc_control_u mmc_control; - - ADPT_DEV_ID_CHECK(dev_id); - MP_PORT_ID_CHECK(port_id); - - gmac_id = MP_PORT_TO_GMAC_ID(port_id); - rv = mp_mmc_control_get(dev_id, gmac_id, &mmc_control); - SW_RTN_ON_ERROR(rv); - mmc_control.bf.cntrst = A_TRUE; - rv = mp_mmc_control_set(dev_id, gmac_id, &mmc_control); - - return rv; -} - -static sw_error_t -adpt_mp_get_mib_info(a_uint32_t dev_id, fal_port_t port_id, - fal_mib_info_t * mib_info) -{ - a_uint32_t gmac_id = 0; - - ADPT_DEV_ID_CHECK(dev_id); - ADPT_NULL_POINT_CHECK(mib_info); - MP_PORT_ID_CHECK(port_id); - memset(mib_info, 0, sizeof(fal_mib_info_t)); - - gmac_id = MP_PORT_TO_GMAC_ID(port_id); - mp_tx_broadcast_frames_good_get(dev_id, gmac_id, - (union tx_broadcast_frames_good_u *)&mib_info->TxBroad); - mp_tx_multicast_frames_good_get(dev_id, gmac_id, - (union tx_multicast_frames_good_u *)&mib_info->TxMulti); - mp_tx_64octets_frames_good_bad_get(dev_id, gmac_id, - (union tx_64octets_frames_good_bad_u *)&mib_info->Tx64Byte); - mp_tx_65to127octets_frames_good_bad_get(dev_id, gmac_id, - (union tx_65to127octets_frames_good_bad_u *)&mib_info->Tx128Byte); - mp_tx_128to255octets_frames_good_bad_get(dev_id, gmac_id, - (union tx_128to255octets_frames_good_bad_u *)&mib_info->Tx256Byte); - mp_tx_256to511octets_frames_good_bad_get(dev_id, gmac_id, - (union tx_256to511octets_frames_good_bad_u *)&mib_info->Tx512Byte); - mp_tx_512to1023octets_frames_good_bad_get(dev_id, gmac_id, - (union tx_512to1023octets_frames_good_bad_u *)&mib_info->Tx1024Byte); - mp_tx_1024tomaxoctets_frames_good_bad_get(dev_id, gmac_id, - (union tx_1024tomaxoctets_frames_good_bad_u *)&mib_info->TxMaxByte); - mp_tx_unicast_frames_good_bad_get(dev_id, gmac_id, - (union tx_unicast_frames_good_bad_u *)&mib_info->TxUniCast); - mp_tx_underflow_error_frames_get(dev_id, gmac_id, - (union tx_underflow_error_frames_u *)&mib_info->TxUnderRun); - mp_tx_single_col_good_frames_get(dev_id, gmac_id, - (union tx_single_collision_good_frames_u *)&mib_info->TxSingalCol); - mp_t_multi_col_good_frames_get(dev_id, gmac_id, - (union tx_multiple_collision_good_frames_u *)&mib_info->TxMultiCol); - mp_tx_defer_frames_get(dev_id, gmac_id, - (union tx_deferred_frames_u *)&mib_info->TxDefer); - mp_tx_late_col_frames_get(dev_id, gmac_id, - (union tx_late_collision_frames_u *)&mib_info->TxLateCol); - mp_tx_excessive_col_frames_get(dev_id, gmac_id, - (union tx_excessive_collision_frames_u *)&mib_info->TxExcDefer); - mp_tx_octet_count_good_get(dev_id, gmac_id, - (union tx_octet_count_good_u *) &mib_info->TxByte_lo); - mp_tx_pause_frames_get(dev_id, gmac_id, - (union tx_pause_frames_u *)&mib_info->TxPause); - mp_tx_osize_frames_good_get(dev_id, gmac_id, - (union tx_osize_frames_good_u *)&mib_info->TxOverSize); - - mp_rx_octet_count_good_get(dev_id, gmac_id, - (union rx_octet_count_good_u *)&mib_info->RxGoodByte_lo); - mp_rx_broadcast_frames_good_get(dev_id, gmac_id, - (union rx_broadcast_frames_good_u *)&mib_info->RxBroad); - mp_rx_multicast_frames_good_get(dev_id, gmac_id, - (union rx_multicast_frames_good_u *)&mib_info->RxMulti); - mp_rx_crc_error_frames_get(dev_id, gmac_id, - (union rx_crc_error_frames_u *)&mib_info->RxFcsErr); - mp_rx_alignment_error_frames_get(dev_id, gmac_id, - (union rx_crc_error_frames_u *)&mib_info->RxAllignErr); - mp_rx_runt_error_frames_get(dev_id, gmac_id, - (union rx_runt_error_frames_u *)&mib_info->RxFragment); - mp_rx_jabber_error_frames_get(dev_id, gmac_id, - (union rx_jabber_error_frames_u *)&mib_info->RxJumboFcsErr); - mp_rx_undersize_frames_good_get(dev_id, gmac_id, - (union rx_undersize_frames_good_u *)&mib_info->RxRunt); - mp_rx_oversize_frames_good_get(dev_id, gmac_id, - (union rx_oversize_frames_good_u *)&mib_info->RxTooLong); - mp_rx_64octets_frames_good_bad_get(dev_id, gmac_id, - (union rx_64octets_frames_good_bad_u *)&mib_info->Rx64Byte); - mp_rx_65to127octets_frames_good_bad_get(dev_id,gmac_id, - (union rx_65to127octets_frames_good_bad_u *)&mib_info->Rx128Byte); - mp_rx_128to255octets_frames_good_bad_get(dev_id, gmac_id, - (union rx_128to255octets_frames_good_bad_u *)&mib_info->Rx256Byte); - mp_rx_256to511octets_frames_good_bad_get(dev_id, gmac_id, - (union rx_256to511octets_frames_good_bad_u *)&mib_info->Rx512Byte); - mp_rx_512to1023octets_frames_good_bad_get(dev_id, gmac_id, - (union rx_512to1023octets_frames_good_bad_u *)&mib_info->Rx1024Byte); - mp_rx_1024tomaxoctets_frames_good_bad_get(dev_id, gmac_id, - (union rx_1024tomaxoctets_frames_good_bad_u *)&mib_info->RxMaxByte); - mp_rx_unicast_frames_good_get(dev_id, gmac_id, - (union rx_unicast_frames_good_u *)&mib_info->RxUniCast); - mp_rx_pause_frames_get(dev_id, gmac_id, - (union rx_pause_frames_u *)&mib_info->RxPause); - mp_rx_fifo_over_flow_frames_get(dev_id, gmac_id, - (union rx_fifo_over_flow_frames_u *)&mib_info->RxOverFlow); - - return SW_OK; -} - -sw_error_t -adpt_mp_get_tx_mib_info(a_uint32_t dev_id, fal_port_t port_id, - fal_mib_info_t * mib_info) -{ - a_uint32_t gmac_id = 0; - - ADPT_DEV_ID_CHECK(dev_id); - ADPT_NULL_POINT_CHECK(mib_info); - MP_PORT_ID_CHECK(port_id); - memset(mib_info, 0, sizeof(fal_mib_info_t)); - - gmac_id = MP_PORT_TO_GMAC_ID(port_id); - mp_tx_broadcast_frames_good_get(dev_id, gmac_id, - (union tx_broadcast_frames_good_u *)&mib_info->TxBroad); - mp_tx_multicast_frames_good_get(dev_id, gmac_id, - (union tx_multicast_frames_good_u *)&mib_info->TxMulti); - mp_tx_64octets_frames_good_bad_get(dev_id, gmac_id, - (union tx_64octets_frames_good_bad_u *)&mib_info->Tx64Byte); - mp_tx_65to127octets_frames_good_bad_get(dev_id, gmac_id, - (union tx_65to127octets_frames_good_bad_u *)&mib_info->Tx128Byte); - mp_tx_128to255octets_frames_good_bad_get(dev_id, gmac_id, - (union tx_128to255octets_frames_good_bad_u *)&mib_info->Tx256Byte); - mp_tx_256to511octets_frames_good_bad_get(dev_id, gmac_id, - (union tx_256to511octets_frames_good_bad_u *)&mib_info->Tx512Byte); - mp_tx_512to1023octets_frames_good_bad_get(dev_id, gmac_id, - (union tx_512to1023octets_frames_good_bad_u *)&mib_info->Tx1024Byte); - mp_tx_1024tomaxoctets_frames_good_bad_get(dev_id, gmac_id, - (union tx_1024tomaxoctets_frames_good_bad_u *)&mib_info->TxMaxByte); - mp_tx_unicast_frames_good_bad_get(dev_id, gmac_id, - (union tx_unicast_frames_good_bad_u *)&mib_info->TxUniCast); - mp_tx_underflow_error_frames_get(dev_id, gmac_id, - (union tx_underflow_error_frames_u *)&mib_info->TxUnderRun); - mp_tx_single_col_good_frames_get(dev_id, gmac_id, - (union tx_single_collision_good_frames_u *)&mib_info->TxSingalCol); - mp_t_multi_col_good_frames_get(dev_id, gmac_id, - (union tx_multiple_collision_good_frames_u *)&mib_info->TxMultiCol); - mp_tx_defer_frames_get(dev_id, gmac_id, - (union tx_deferred_frames_u *)&mib_info->TxDefer); - mp_tx_late_col_frames_get(dev_id, gmac_id, - (union tx_late_collision_frames_u *)&mib_info->TxLateCol); - mp_tx_excessive_col_frames_get(dev_id, gmac_id, - (union tx_excessive_collision_frames_u *)&mib_info->TxExcDefer); - mp_tx_octet_count_good_get(dev_id, gmac_id, - (union tx_octet_count_good_u *) &mib_info->TxByte_lo); - mp_tx_pause_frames_get(dev_id, gmac_id, - (union tx_pause_frames_u *)&mib_info->TxPause); - mp_tx_osize_frames_good_get(dev_id, gmac_id, - (union tx_osize_frames_good_u *)&mib_info->TxOverSize); - - return SW_OK; -} - -sw_error_t -adpt_mp_get_rx_mib_info(a_uint32_t dev_id, fal_port_t port_id, - fal_mib_info_t * mib_info ) -{ - a_uint32_t gmac_id = 0; - - ADPT_DEV_ID_CHECK(dev_id); - ADPT_NULL_POINT_CHECK(mib_info); - MP_PORT_ID_CHECK(port_id); - memset(mib_info, 0, sizeof(fal_mib_info_t)); - - gmac_id = MP_PORT_TO_GMAC_ID(port_id); - mp_rx_octet_count_good_get(dev_id, gmac_id, - (union rx_octet_count_good_u *)&mib_info->RxGoodByte_lo); - mp_rx_broadcast_frames_good_get(dev_id, gmac_id, - (union rx_broadcast_frames_good_u *)&mib_info->RxBroad); - mp_rx_multicast_frames_good_get(dev_id, gmac_id, - (union rx_multicast_frames_good_u *)&mib_info->RxMulti); - mp_rx_crc_error_frames_get(dev_id, gmac_id, - (union rx_crc_error_frames_u *)&mib_info->RxFcsErr); - mp_rx_alignment_error_frames_get(dev_id, gmac_id, - (union rx_crc_error_frames_u *)&mib_info->RxAllignErr); - mp_rx_runt_error_frames_get(dev_id, gmac_id, - (union rx_runt_error_frames_u *)&mib_info->RxFragment); - mp_rx_jabber_error_frames_get(dev_id, gmac_id, - (union rx_jabber_error_frames_u *)&mib_info->RxJumboFcsErr); - mp_rx_undersize_frames_good_get(dev_id, gmac_id, - (union rx_undersize_frames_good_u *)&mib_info->RxRunt); - mp_rx_oversize_frames_good_get(dev_id, gmac_id, - (union rx_oversize_frames_good_u *)&mib_info->RxTooLong); - mp_rx_64octets_frames_good_bad_get(dev_id, gmac_id, - (union rx_64octets_frames_good_bad_u *)&mib_info->Rx64Byte); - mp_rx_65to127octets_frames_good_bad_get(dev_id,gmac_id, - (union rx_65to127octets_frames_good_bad_u *)&mib_info->Rx128Byte); - mp_rx_128to255octets_frames_good_bad_get(dev_id, gmac_id, - (union rx_128to255octets_frames_good_bad_u *)&mib_info->Rx256Byte); - mp_rx_256to511octets_frames_good_bad_get(dev_id, gmac_id, - (union rx_256to511octets_frames_good_bad_u *)&mib_info->Rx512Byte); - mp_rx_512to1023octets_frames_good_bad_get(dev_id, gmac_id, - (union rx_512to1023octets_frames_good_bad_u *)&mib_info->Rx1024Byte); - mp_rx_1024tomaxoctets_frames_good_bad_get(dev_id, gmac_id, - (union rx_1024tomaxoctets_frames_good_bad_u *)&mib_info->RxMaxByte); - mp_rx_unicast_frames_good_get(dev_id, gmac_id, - (union rx_unicast_frames_good_u *)&mib_info->RxUniCast); - mp_rx_pause_frames_get(dev_id, gmac_id, - (union rx_pause_frames_u *)&mib_info->RxPause); - mp_rx_fifo_over_flow_frames_get(dev_id, gmac_id, - (union rx_fifo_over_flow_frames_u *)&mib_info->RxOverFlow); - - return SW_OK; -} - -sw_error_t adpt_mp_mib_init(a_uint32_t dev_id) -{ - adpt_api_t *p_adpt_api = NULL; - - p_adpt_api = adpt_api_ptr_get(dev_id); - - SW_RTN_ON_NULL(p_adpt_api); - - p_adpt_api->adpt_mib_cpukeep_get = adpt_mp_mib_cpukeep_get; - p_adpt_api->adpt_mib_cpukeep_set = adpt_mp_mib_cpukeep_set; - p_adpt_api->adpt_mib_status_get = adpt_mp_mib_status_get; - p_adpt_api->adpt_mib_status_set = adpt_mp_mib_status_set; - p_adpt_api->adpt_mib_port_flush_counters = adpt_mp_mib_port_flush_counters; - p_adpt_api->adpt_get_mib_info = adpt_mp_get_mib_info; - p_adpt_api->adpt_get_tx_mib_info = adpt_mp_get_tx_mib_info; - p_adpt_api->adpt_get_rx_mib_info = adpt_mp_get_rx_mib_info; - - return SW_OK; -} -/** - * @} - */ diff --git a/feeds/ipq807x/qca-ssdk/src/src/adpt/mp/adpt_mp_portctrl.c b/feeds/ipq807x/qca-ssdk/src/src/adpt/mp/adpt_mp_portctrl.c deleted file mode 100755 index 955e8e03e..000000000 --- a/feeds/ipq807x/qca-ssdk/src/src/adpt/mp/adpt_mp_portctrl.c +++ /dev/null @@ -1,1344 +0,0 @@ -/* - * Copyright (c) 2020, The Linux Foundation. All rights reserved. - * - * Permission to use, copy, modify, and/or distribute this software for any - * purpose with or without fee is hereby granted, provided that the above - * copyright notice and this permission notice appear in all copies. - * - * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES - * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR - * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES - * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN - * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF - * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. - */ - -#include "sw.h" -#include "mp_portctrl_reg.h" -#include "mp_portctrl.h" -#include "adpt.h" -#include "adpt_mp.h" -#include "adpt_mp_portctrl.h" -#include "adpt_mp_uniphy.h" -#include "hsl_port_prop.h" -#include "hsl_phy.h" -#include "ssdk_dts.h" -#include "ssdk_clk.h" - -static a_uint32_t port_lpi_status[SW_MAX_NR_DEV] = {0}; - -static sw_error_t -_adpt_mp_gcc_mac_clock_set(a_uint32_t dev_id, - a_uint32_t port_id, a_bool_t enable) -{ - sw_error_t rv = 0; - - qca_gcc_mac_port_clock_set(dev_id, port_id, enable); - - return rv; -} - -static a_bool_t -_adpt_mp_port_phy_connected (a_uint32_t dev_id, fal_port_t port_id) -{ - a_bool_t force_port = 0; - - ADPT_DEV_ID_CHECK(dev_id); - - /* force port which connect s17c or other device chip*/ - force_port = ssdk_port_feature_get(dev_id, port_id, PHY_F_FORCE); - if (force_port == A_TRUE) { - SSDK_DEBUG("port_id %d is a force port!\n", port_id); - return A_FALSE; - } else { - return A_TRUE; - } -} - -static sw_error_t -_adpt_mp_port_gcc_speed_clock_set( - a_uint32_t dev_id, - a_uint32_t port_id, - fal_port_speed_t phy_speed) -{ - sw_error_t rv = 0; - - switch (phy_speed) { - case FAL_SPEED_10: - ssdk_port_speed_clock_set(dev_id, - port_id, SGMII_SPEED_10M_CLK); - break; - case FAL_SPEED_100: - ssdk_port_speed_clock_set(dev_id, - port_id, SGMII_SPEED_100M_CLK); - break; - case FAL_SPEED_1000: - ssdk_port_speed_clock_set(dev_id, - port_id, SGMII_SPEED_1000M_CLK); - break; - case FAL_SPEED_2500: - ssdk_port_speed_clock_set(dev_id, - port_id, SGMII_PLUS_SPEED_2500M_CLK); - break; - default: - break; - } - - return rv; -} - -static sw_error_t -adpt_mp_port_reset_set(a_uint32_t dev_id, a_uint32_t port_id) -{ - sw_error_t rv = 0; - a_uint32_t phy_addr; - hsl_phy_ops_t *phy_drv; - - ADPT_DEV_ID_CHECK(dev_id); - - if (port_id == SSDK_PHYSICAL_PORT1) { - /*internal gephy reset*/ - SW_RTN_ON_NULL (phy_drv = hsl_phy_api_ops_get(dev_id, - port_id)); - if (NULL == phy_drv->phy_function_reset) - return SW_NOT_SUPPORTED; - rv = hsl_port_prop_get_phyid (dev_id, port_id, &phy_addr); - SW_RTN_ON_ERROR (rv); - rv = phy_drv->phy_function_reset(dev_id, phy_addr, PHY_FIFO_RESET); - SW_RTN_ON_ERROR (rv); - } else if (port_id == SSDK_PHYSICAL_PORT2) { - rv = adpt_mp_uniphy_adapter_port_reset(dev_id, port_id); - } else { - return SW_NOT_SUPPORTED; - } - - return rv; -} - -static sw_error_t -adpt_mp_port_txmac_status_set(a_uint32_t dev_id, fal_port_t port_id, - a_bool_t enable) -{ - sw_error_t rv = SW_OK; - a_uint32_t gmac_id = 0; - union mac_configuration_u configuration; - - ADPT_DEV_ID_CHECK(dev_id); - MP_PORT_ID_CHECK(port_id); - - memset(&configuration, 0, sizeof(configuration)); - gmac_id = MP_PORT_TO_GMAC_ID(port_id); - - rv = mp_mac_configuration_get(dev_id, gmac_id, &configuration); - SW_RTN_ON_ERROR(rv); - - configuration.bf.tx_enable = enable; - rv = mp_mac_configuration_set(dev_id, gmac_id, &configuration); - - return rv; -} - -#ifndef IN_PORTCONTROL_MINI -static sw_error_t -adpt_mp_port_txmac_status_get(a_uint32_t dev_id, fal_port_t port_id, - a_bool_t *enable) -{ - sw_error_t rv = SW_OK; - a_uint32_t gmac_id = 0; - union mac_configuration_u configuration; - - ADPT_DEV_ID_CHECK(dev_id); - MP_PORT_ID_CHECK(port_id); - ADPT_NULL_POINT_CHECK(enable); - - memset(&configuration, 0, sizeof(configuration)); - gmac_id = MP_PORT_TO_GMAC_ID(port_id); - - rv = mp_mac_configuration_get(dev_id, gmac_id, &configuration); - SW_RTN_ON_ERROR(rv); - - *enable = configuration.bf.tx_enable; - - return rv; -} -#endif - -static sw_error_t -adpt_mp_port_rxmac_status_set(a_uint32_t dev_id, fal_port_t port_id, - a_bool_t enable) -{ - sw_error_t rv = SW_OK; - a_uint32_t gmac_id = 0; - union mac_configuration_u configuration; - - ADPT_DEV_ID_CHECK(dev_id); - MP_PORT_ID_CHECK(port_id); - - memset(&configuration, 0, sizeof(configuration)); - gmac_id = MP_PORT_TO_GMAC_ID(port_id); - - rv = mp_mac_configuration_get(dev_id, gmac_id, &configuration); - SW_RTN_ON_ERROR(rv); - - configuration.bf.rx_enable = enable; - rv = mp_mac_configuration_set(dev_id, gmac_id, &configuration); - - return rv; -} - -#ifndef IN_PORTCONTROL_MINI -static sw_error_t -adpt_mp_port_rxmac_status_get(a_uint32_t dev_id, fal_port_t port_id, - a_bool_t *enable) -{ - sw_error_t rv = SW_OK; - a_uint32_t gmac_id = 0; - union mac_configuration_u configuration; - - ADPT_DEV_ID_CHECK(dev_id); - MP_PORT_ID_CHECK(port_id); - ADPT_NULL_POINT_CHECK(enable); - - memset(&configuration, 0, sizeof(configuration)); - gmac_id = MP_PORT_TO_GMAC_ID(port_id); - - rv = mp_mac_configuration_get(dev_id, gmac_id, &configuration); - SW_RTN_ON_ERROR(rv); - - *enable = configuration.bf.rx_enable; - - return rv; -} -#endif - -static sw_error_t -adpt_mp_port_txfc_status_set(a_uint32_t dev_id, fal_port_t port_id, - a_bool_t enable) -{ - sw_error_t rv = SW_OK; - a_uint32_t gmac_id = 0; - union mac_flow_ctrl_u mac_flow_ctrl; - struct qca_phy_priv *priv = ssdk_phy_priv_data_get(dev_id); - union mac_operation_mode_ctrl_u mac_operation_mode_ctrl; - - ADPT_DEV_ID_CHECK(dev_id); - MP_PORT_ID_CHECK(port_id); - ADPT_NULL_POINT_CHECK(priv); - - memset(&mac_flow_ctrl, 0, sizeof(mac_flow_ctrl)); - memset(&mac_operation_mode_ctrl, 0, sizeof(mac_operation_mode_ctrl)); - gmac_id = MP_PORT_TO_GMAC_ID(port_id); - - rv = mp_mac_flowctrl_get(dev_id, gmac_id, &mac_flow_ctrl); - SW_RTN_ON_ERROR(rv); - - rv = mp_mac_operation_mode_ctrl_get(dev_id, gmac_id, - &mac_operation_mode_ctrl); - SW_RTN_ON_ERROR(rv); - - if (A_TRUE == enable) { - mac_flow_ctrl.bf.flowctrl_tx_enable = 1; - mac_flow_ctrl.bf.pause_time = GMAC_PAUSE_TIME; - mac_flow_ctrl.bf.disable_zero_quanta_pause = - GMAC_PAUSE_ZERO_QUANTA_ENABLE; - mac_operation_mode_ctrl.bf.enable_hw_flowctrl = - GMAC_HW_FLOWCTRL_ENABLE; - mac_operation_mode_ctrl.bf.disable_flushing_receiving_frame = - GMAC_FLUSH_RECEIVED_FRAMES_DISABLE; - /*activate flowctrl when 6KB FIFO is available*/ - mac_operation_mode_ctrl.val &= ~(GMAC_ACTIVATE_FLOWCTRL_MASK); - mac_operation_mode_ctrl.val |= GMAC_ACTIVATE_FLOWCTRL_WITH_6KB; - /*dactivate flowctrl when 7KB FIFO is available*/ - mac_operation_mode_ctrl.val &= ~(GMAC_DACTIVATE_FLOWCTRL_MASK); - mac_operation_mode_ctrl.val |= GMAC_DACTIVATE_FLOWCTRL_WITH_7KB; - } else { - mac_flow_ctrl.bf.flowctrl_tx_enable = 0; - mac_operation_mode_ctrl.bf.enable_hw_flowctrl = - GMAC_HW_FLOWCTRL_DISABLE; - } - - rv = mp_mac_operation_mode_ctrl_set(dev_id, gmac_id, - &mac_operation_mode_ctrl); - SW_RTN_ON_ERROR(rv); - - rv = mp_mac_flowctrl_set(dev_id, gmac_id, &mac_flow_ctrl); - SW_RTN_ON_ERROR(rv); - - priv->port_old_tx_flowctrl[port_id - 1] = enable; - - return rv; -} - -#ifndef IN_PORTCONTROL_MINI -static sw_error_t -adpt_mp_port_txfc_status_get(a_uint32_t dev_id, fal_port_t port_id, - a_bool_t * enable) -{ - sw_error_t rv = SW_OK; - a_uint32_t gmac_id = 0; - union mac_flow_ctrl_u mac_flow_ctrl; - - ADPT_DEV_ID_CHECK(dev_id); - MP_PORT_ID_CHECK(port_id); - ADPT_NULL_POINT_CHECK(enable); - - memset(&mac_flow_ctrl, 0, sizeof(mac_flow_ctrl)); - gmac_id = MP_PORT_TO_GMAC_ID(port_id); - - rv = mp_mac_flowctrl_get(dev_id, gmac_id, &mac_flow_ctrl); - SW_RTN_ON_ERROR(rv); - - if (mac_flow_ctrl.bf.flowctrl_tx_enable) { - *enable = A_TRUE; - } else { - *enable = A_FALSE; - } - - return rv; -} -#endif - -static sw_error_t -adpt_mp_port_rxfc_status_set(a_uint32_t dev_id, fal_port_t port_id, - a_bool_t enable) -{ - sw_error_t rv = SW_OK; - a_uint32_t gmac_id = 0; - union mac_flow_ctrl_u mac_flow_ctrl; - struct qca_phy_priv *priv = ssdk_phy_priv_data_get(dev_id); - - ADPT_DEV_ID_CHECK(dev_id); - MP_PORT_ID_CHECK(port_id); - ADPT_NULL_POINT_CHECK(priv); - - memset(&mac_flow_ctrl, 0, sizeof(mac_flow_ctrl)); - gmac_id = MP_PORT_TO_GMAC_ID(port_id); - - rv = mp_mac_flowctrl_get(dev_id, gmac_id, &mac_flow_ctrl); - SW_RTN_ON_ERROR(rv); - - if (A_TRUE == enable) { - mac_flow_ctrl.bf.flowctrl_rx_enable = 1; - } else { - mac_flow_ctrl.bf.flowctrl_rx_enable = 0; - } - - rv = mp_mac_flowctrl_set(dev_id, gmac_id, &mac_flow_ctrl); - - priv->port_old_rx_flowctrl[port_id - 1] = enable; - - return rv; -} - -#ifndef IN_PORTCONTROL_MINI -static sw_error_t -adpt_mp_port_rxfc_status_get(a_uint32_t dev_id, fal_port_t port_id, - a_bool_t * enable) -{ - sw_error_t rv = SW_OK; - a_uint32_t gmac_id = 0; - union mac_flow_ctrl_u mac_flow_ctrl; - - ADPT_DEV_ID_CHECK(dev_id); - MP_PORT_ID_CHECK(port_id); - ADPT_NULL_POINT_CHECK(enable); - - memset(&mac_flow_ctrl, 0, sizeof(mac_flow_ctrl)); - gmac_id = MP_PORT_TO_GMAC_ID(port_id); - - rv = mp_mac_flowctrl_get(dev_id, gmac_id, &mac_flow_ctrl); - SW_RTN_ON_ERROR(rv); - - if (mac_flow_ctrl.bf.flowctrl_rx_enable) { - *enable = A_TRUE; - } else { - *enable = A_FALSE; - } - - return rv; -} -#endif - -static sw_error_t -adpt_mp_port_flowctrl_set(a_uint32_t dev_id, fal_port_t port_id, - a_bool_t enable) -{ - sw_error_t rv = SW_OK; - struct qca_phy_priv *priv = ssdk_phy_priv_data_get(dev_id); - - ADPT_DEV_ID_CHECK(dev_id); - MP_PORT_ID_CHECK(port_id); - ADPT_NULL_POINT_CHECK(priv); - - rv = adpt_mp_port_txfc_status_set(dev_id, port_id, enable); - SW_RTN_ON_ERROR(rv); - - rv = adpt_mp_port_rxfc_status_set(dev_id, port_id, enable); - SW_RTN_ON_ERROR(rv); - - priv->port_old_tx_flowctrl[port_id - 1] = enable; - priv->port_old_rx_flowctrl[port_id - 1] = enable; - - return rv; -} - -#ifndef IN_PORTCONTROL_MINI -static sw_error_t -adpt_mp_port_flowctrl_get(a_uint32_t dev_id, fal_port_t port_id, - a_bool_t * enable) -{ - sw_error_t rv = SW_OK; - a_bool_t txfc_enable, rxfc_enable; - - ADPT_DEV_ID_CHECK(dev_id); - MP_PORT_ID_CHECK(port_id); - ADPT_NULL_POINT_CHECK(enable); - - rv = adpt_mp_port_txfc_status_get(dev_id, port_id, &txfc_enable); - SW_RTN_ON_ERROR(rv); - rv = adpt_mp_port_rxfc_status_get(dev_id, port_id, &rxfc_enable); - SW_RTN_ON_ERROR(rv); - - *enable = txfc_enable & rxfc_enable; - - return rv; -} -#endif - -static sw_error_t -adpt_mp_port_flowctrl_forcemode_set(a_uint32_t dev_id, - fal_port_t port_id, a_bool_t enable) -{ - sw_error_t rv = SW_OK; - struct qca_phy_priv *priv = ssdk_phy_priv_data_get(dev_id); - - ADPT_DEV_ID_CHECK(dev_id); - MP_PORT_ID_CHECK(port_id); - ADPT_NULL_POINT_CHECK(priv); - - priv->port_tx_flowctrl_forcemode[port_id - 1] = enable; - priv->port_rx_flowctrl_forcemode[port_id - 1] = enable; - - return rv; -} - -#ifndef IN_PORTCONTROL_MINI -static sw_error_t -adpt_mp_port_flowctrl_forcemode_get(a_uint32_t dev_id, - fal_port_t port_id, a_bool_t *enable) -{ - sw_error_t rv = SW_OK; - struct qca_phy_priv *priv = ssdk_phy_priv_data_get(dev_id); - - - ADPT_DEV_ID_CHECK(dev_id); - MP_PORT_ID_CHECK(port_id); - ADPT_NULL_POINT_CHECK(enable); - ADPT_NULL_POINT_CHECK(priv); - - *enable = (priv->port_tx_flowctrl_forcemode[port_id - 1] & - priv->port_rx_flowctrl_forcemode[port_id - 1]); - - return rv; -} -#endif - -static sw_error_t -adpt_mp_port_mac_status_get(a_uint32_t dev_id, a_uint32_t port_id, - struct port_phy_status *port_mac_status) -{ - sw_error_t rv = SW_OK; - a_uint32_t gmac_id = 0; - union mac_configuration_u configuration; - - ADPT_DEV_ID_CHECK(dev_id); - MP_PORT_ID_CHECK(port_id); - ADPT_NULL_POINT_CHECK(port_mac_status); - - memset(&configuration, 0, sizeof(configuration)); - gmac_id = MP_PORT_TO_GMAC_ID(port_id); - - rv = mp_mac_configuration_get(dev_id, gmac_id, &configuration); - SW_RTN_ON_ERROR(rv); - - if (configuration.bf.port_select == GMAC_SPEED_1000M) { - port_mac_status->speed = FAL_SPEED_1000; - } else { - if (configuration.bf.mii_speed == GMAC_SPEED_100M) { - port_mac_status->speed = FAL_SPEED_100; - } else { - port_mac_status->speed = FAL_SPEED_10; - } - } - - if (configuration.bf.duplex == GMAC_FULL_DUPLEX) { - port_mac_status->duplex = FAL_FULL_DUPLEX; - } else { - port_mac_status->duplex = FAL_HALF_DUPLEX; - } - - return rv; - -} - -static sw_error_t -adpt_mp_port_mac_speed_set(a_uint32_t dev_id, a_uint32_t port_id, - fal_port_speed_t speed) -{ - sw_error_t rv = SW_OK; - a_uint32_t gmac_id = 0; - union mac_configuration_u configuration; - a_bool_t force_port; - - ADPT_DEV_ID_CHECK(dev_id); - MP_PORT_ID_CHECK(port_id); - - memset(&configuration, 0, sizeof(configuration)); - gmac_id = MP_PORT_TO_GMAC_ID(port_id); - - rv = mp_mac_configuration_get(dev_id, gmac_id, &configuration); - SW_RTN_ON_ERROR(rv); - - if ((FAL_SPEED_1000 == speed) || (FAL_SPEED_2500 == speed)) { - configuration.bf.port_select = GMAC_SPEED_1000M; - } else if (FAL_SPEED_100 == speed) { - configuration.bf.port_select = (~GMAC_SPEED_1000M) & 0x1; - configuration.bf.mii_speed = GMAC_SPEED_100M; - } else if (FAL_SPEED_10== speed) { - configuration.bf.port_select = (~GMAC_SPEED_1000M) & 0x1; - configuration.bf.mii_speed = GMAC_SPEED_10M; - } - - rv = mp_mac_configuration_set(dev_id, gmac_id, &configuration); - SW_RTN_ON_ERROR(rv); - - force_port = ssdk_port_feature_get(dev_id, port_id, PHY_F_FORCE); - /* enable force port configuration */ - if (force_port == A_TRUE) { - rv = _adpt_mp_port_gcc_speed_clock_set(dev_id, - port_id, speed); - SW_RTN_ON_ERROR(rv); - rv = adpt_mp_gcc_uniphy_port_clock_set(dev_id, - port_id, A_TRUE); - SW_RTN_ON_ERROR(rv); - rv = _adpt_mp_gcc_mac_clock_set(dev_id, - port_id, A_TRUE); - SW_RTN_ON_ERROR(rv); - rv = adpt_mp_port_reset_set(dev_id, port_id); - SW_RTN_ON_ERROR(rv); - } - return rv; - -} - -static sw_error_t -adpt_mp_port_mac_duplex_set(a_uint32_t dev_id, a_uint32_t port_id, - fal_port_duplex_t duplex) -{ - sw_error_t rv = SW_OK; - a_uint32_t gmac_id = 0; - union mac_configuration_u configuration; - - ADPT_DEV_ID_CHECK(dev_id); - MP_PORT_ID_CHECK(port_id); - - memset(&configuration, 0, sizeof(configuration)); - gmac_id = MP_PORT_TO_GMAC_ID(port_id); - - rv = mp_mac_configuration_get(dev_id, gmac_id, &configuration); - SW_RTN_ON_ERROR(rv); - - if (FAL_FULL_DUPLEX == duplex) { - configuration.bf.duplex = GMAC_FULL_DUPLEX; - } else { - configuration.bf.duplex = GMAC_HALF_DUPLEX; - } - - rv = mp_mac_configuration_set(dev_id, gmac_id, &configuration); - - return rv; -} - -static sw_error_t -adpt_mp_port_promisc_mode_set(a_uint32_t dev_id, fal_port_t port_id, - a_bool_t enable) -{ - sw_error_t rv = SW_OK; - a_uint32_t gmac_id = 0; - union mac_frame_filter_u mac_frame_filter; - - ADPT_DEV_ID_CHECK(dev_id); - MP_PORT_ID_CHECK(port_id); - - memset(&mac_frame_filter, 0, sizeof(mac_frame_filter)); - gmac_id = MP_PORT_TO_GMAC_ID(port_id); - - rv = mp_mac_frame_filter_get(dev_id, gmac_id, &mac_frame_filter); - SW_RTN_ON_ERROR(rv); - - mac_frame_filter.bf.promiscuous_mode = enable; - - rv = mp_mac_frame_filter_set(dev_id, gmac_id, &mac_frame_filter); - - return rv; -} - -#ifndef IN_PORTCONTROL_MINI -static sw_error_t -adpt_mp_port_promisc_mode_get(a_uint32_t dev_id, fal_port_t port_id, - a_bool_t *enable) -{ - sw_error_t rv = SW_OK; - a_uint32_t gmac_id = 0; - union mac_frame_filter_u mac_frame_filter; - - ADPT_DEV_ID_CHECK(dev_id); - MP_PORT_ID_CHECK(port_id); - ADPT_NULL_POINT_CHECK(enable); - - memset(&mac_frame_filter, 0, sizeof(mac_frame_filter)); - gmac_id = MP_PORT_TO_GMAC_ID(port_id); - - rv = mp_mac_frame_filter_get(dev_id, gmac_id, &mac_frame_filter); - SW_RTN_ON_ERROR(rv); - - *enable = mac_frame_filter.bf.promiscuous_mode; - - return rv; -} -#endif - -static sw_error_t -adpt_mp_port_max_frame_size_set(a_uint32_t dev_id, fal_port_t port_id, - a_uint32_t max_frame) -{ - sw_error_t rv = SW_OK; - a_uint32_t gmac_id = 0; - union mac_max_frame_ctrl_u mac_max_frame_ctrl; - union mac_configuration_u configuration; - union mac_operation_mode_ctrl_u mac_operation_mode_ctrl; - - ADPT_DEV_ID_CHECK(dev_id); - MP_PORT_ID_CHECK(port_id); - - memset(&configuration, 0, sizeof(configuration)); - memset(&mac_max_frame_ctrl, 0, sizeof(mac_max_frame_ctrl)); - memset(&mac_operation_mode_ctrl, 0, sizeof(mac_operation_mode_ctrl)); - gmac_id = MP_PORT_TO_GMAC_ID(port_id); - - rv = mp_mac_max_frame_ctrl_get(dev_id, gmac_id, &mac_max_frame_ctrl); - SW_RTN_ON_ERROR(rv); - rv = mp_mac_configuration_get(dev_id, gmac_id, &configuration); - SW_RTN_ON_ERROR(rv); - - configuration.bf.jabber_disable = GMAC_JD_ENABLE; - configuration.bf.watchdog_disable = GMAC_WD_DISABLE; - configuration.bf.jumbo_frame_enable = GMAC_JUMBO_FRAME_ENABLE; - configuration.bf.frame_burst_enable = GMAC_FRAME_BURST_ENABLE; - rv = mp_mac_configuration_set(dev_id, gmac_id, &configuration); - SW_RTN_ON_ERROR(rv); - - mac_max_frame_ctrl.bf.max_frame_ctrl_enable = GMAC_MAX_FRAME_CTRL_ENABLE; - /* default max_frame 1518 byte doesn't include vlan tag */ - mac_max_frame_ctrl.bf.max_frame_ctrl = max_frame + 8; - rv = mp_mac_max_frame_ctrl_set(dev_id, gmac_id, &mac_max_frame_ctrl); - - rv = mp_mac_operation_mode_ctrl_get(dev_id, gmac_id, - &mac_operation_mode_ctrl); - mac_operation_mode_ctrl.bf.receive_store_and_foward = - GMAC_RX_STORE_FORWAD_ENABLE; - mac_operation_mode_ctrl.bf.transmit_store_and_foward = - GMAC_TX_STORE_FORWAD_ENABLE; - mac_operation_mode_ctrl.bf.forward_error_frame = - GMAC_FORWARD_ERROR_FRAME_DISABLE; - mac_operation_mode_ctrl.bf.drop_gaint_frame = - GMAC_DROP_GAINT_FRAME_DISABLE; - rv = mp_mac_operation_mode_ctrl_set(dev_id, gmac_id, - &mac_operation_mode_ctrl); - - return rv; -} - -static sw_error_t -adpt_mp_port_max_frame_size_get(a_uint32_t dev_id, fal_port_t port_id, - a_uint32_t *max_frame) -{ - sw_error_t rv = SW_OK; - a_uint32_t gmac_id = 0; - union mac_max_frame_ctrl_u mac_max_frame_ctrl; - - ADPT_DEV_ID_CHECK(dev_id); - MP_PORT_ID_CHECK(port_id); - ADPT_NULL_POINT_CHECK(max_frame); - - memset(&mac_max_frame_ctrl, 0, sizeof(mac_max_frame_ctrl)); - gmac_id = MP_PORT_TO_GMAC_ID(port_id); - - rv = mp_mac_max_frame_ctrl_get(dev_id, gmac_id, &mac_max_frame_ctrl); - SW_RTN_ON_ERROR(rv); - - *max_frame = mac_max_frame_ctrl.bf.max_frame_ctrl; - - return rv; -} - -static sw_error_t -adpt_mp_port_mac_eee_enable_set(a_uint32_t dev_id, fal_port_t port_id, - a_bool_t enable) -{ - sw_error_t rv = 0; - a_uint32_t gmac_id = 0; - union mac_lpi_ctrl_status_u mac_lpi_ctrl_status; - - ADPT_DEV_ID_CHECK(dev_id); - MP_PORT_ID_CHECK(port_id); - - memset(&mac_lpi_ctrl_status, 0, sizeof(mac_lpi_ctrl_status)); - gmac_id = MP_PORT_TO_GMAC_ID(port_id); - - rv = mp_mac_lpi_ctrl_status_get(dev_id, gmac_id, &mac_lpi_ctrl_status); - SW_RTN_ON_ERROR(rv); - mac_lpi_ctrl_status.bf.lpi_enable = enable; - - rv = mp_mac_lpi_ctrl_status_set(dev_id, gmac_id, &mac_lpi_ctrl_status); - - return rv; -} - -#ifndef IN_PORTCONTROL_MINI -static sw_error_t -adpt_mp_port_mac_eee_enable_get(a_uint32_t dev_id, fal_port_t port_id, - a_bool_t *enable) -{ - sw_error_t rv = 0; - a_uint32_t gmac_id = 0; - union mac_lpi_ctrl_status_u mac_lpi_ctrl_status; - - ADPT_DEV_ID_CHECK(dev_id); - MP_PORT_ID_CHECK(port_id); - ADPT_NULL_POINT_CHECK(enable); - - memset(&mac_lpi_ctrl_status, 0, sizeof(mac_lpi_ctrl_status)); - gmac_id = MP_PORT_TO_GMAC_ID(port_id); - - rv = mp_mac_lpi_ctrl_status_get(dev_id, gmac_id, &mac_lpi_ctrl_status); - SW_RTN_ON_ERROR(rv); - - *enable = mac_lpi_ctrl_status.bf.lpi_enable; - - return rv; - -} -#endif - -static sw_error_t -adpt_mp_port_interface_eee_cfg_set(a_uint32_t dev_id, fal_port_t port_id, - fal_port_eee_cfg_t *port_eee_cfg) -{ - sw_error_t rv = 0; - union mac_lpi_timer_ctrl_u mac_lpi_timer_ctrl; - union mac_lpi_ctrl_status_u mac_lpi_ctrl_status; - - a_uint32_t phy_addr = 0, gmac_id = 0; - a_uint32_t adv; - hsl_phy_ops_t *phy_drv; - struct qca_phy_priv *priv; - - ADPT_DEV_ID_CHECK(dev_id); - MP_PORT_ID_CHECK(port_id); - - memset(&mac_lpi_timer_ctrl, 0, sizeof(mac_lpi_timer_ctrl)); - memset(&mac_lpi_ctrl_status, 0, sizeof(mac_lpi_ctrl_status)); - gmac_id = MP_PORT_TO_GMAC_ID(port_id); - - priv = ssdk_phy_priv_data_get(dev_id); - SW_RTN_ON_NULL(priv); - - if (port_eee_cfg->enable) { - adv = port_eee_cfg->advertisement; - } else { - adv = 0; - } - - if (port_eee_cfg->lpi_tx_enable) { - port_lpi_status[dev_id] |= BIT(port_id-1); - } else { - port_lpi_status[dev_id] &= ~BIT(port_id-1); - } - - SW_RTN_ON_NULL(phy_drv = hsl_phy_api_ops_get(dev_id, port_id)); - if (NULL == phy_drv->phy_eee_adv_set) { - return SW_NOT_SUPPORTED; - } - - rv = hsl_port_prop_get_phyid(dev_id, port_id, &phy_addr); - SW_RTN_ON_ERROR (rv); - - rv = phy_drv->phy_eee_adv_set(dev_id, phy_addr, adv); - SW_RTN_ON_ERROR (rv); - - rv = mp_mac_lpi_timer_ctrl_get(dev_id, gmac_id, &mac_lpi_timer_ctrl); - SW_RTN_ON_ERROR (rv); - mac_lpi_timer_ctrl.bf.lpi_tw_timer = port_eee_cfg->lpi_wakeup_timer; - rv = mp_mac_lpi_timer_ctrl_set(dev_id, gmac_id, &mac_lpi_timer_ctrl); - SW_RTN_ON_ERROR (rv); - - rv = mp_mac_lpi_ctrl_status_get(dev_id, gmac_id, &mac_lpi_ctrl_status); - SW_RTN_ON_ERROR (rv); - mac_lpi_ctrl_status.bf.lpi_tx_auto_enable = GMAC_LPI_AUTO_MODE; - mac_lpi_ctrl_status.bf.link_status = GMAC_LPI_LINK_UP; - mac_lpi_ctrl_status.bf.lpi_enable = port_eee_cfg->lpi_tx_enable; - rv = mp_mac_lpi_ctrl_status_set(dev_id, gmac_id, &mac_lpi_ctrl_status); - SW_RTN_ON_ERROR (rv); - - if (port_lpi_status[dev_id] & PORT_LPI_ENABLE_STATUS) { - if (!(port_lpi_status[dev_id] & PORT_LPI_TASK_RUNNING)) { - if (!(port_lpi_status[dev_id] & PORT_LPI_TASK_START)) { - qca_mac_sw_sync_work_start(priv); - port_lpi_status[dev_id] |= PORT_LPI_TASK_START; - } else { - qca_mac_sw_sync_work_resume(priv); - } - port_lpi_status[dev_id] |= PORT_LPI_TASK_RUNNING; - } - } else { - qca_mac_sw_sync_work_stop(priv); - port_lpi_status[dev_id] &= ~PORT_LPI_TASK_RUNNING; - } - - return rv; -} -static sw_error_t -adpt_mp_port_interface_eee_cfg_get(a_uint32_t dev_id, fal_port_t port_id, - fal_port_eee_cfg_t *port_eee_cfg) -{ - sw_error_t rv = 0; - union mac_lpi_timer_ctrl_u mac_lpi_timer_ctrl; - union mac_lpi_ctrl_status_u mac_lpi_ctrl_status; - a_uint32_t phy_addr = 0, gmac_id = 0; - a_uint32_t adv, lp_adv, cap, status; - hsl_phy_ops_t *phy_drv; - - ADPT_DEV_ID_CHECK(dev_id); - MP_PORT_ID_CHECK(port_id); - ADPT_NULL_POINT_CHECK(port_eee_cfg); - - memset(&mac_lpi_timer_ctrl, 0, sizeof(mac_lpi_timer_ctrl)); - memset(&mac_lpi_ctrl_status, 0, sizeof(mac_lpi_ctrl_status)); - memset(port_eee_cfg, 0, sizeof(*port_eee_cfg)); - gmac_id = MP_PORT_TO_GMAC_ID(port_id); - - SW_RTN_ON_NULL(phy_drv =hsl_phy_api_ops_get (dev_id, port_id)); - if ((NULL == phy_drv->phy_eee_adv_get) || - (NULL == phy_drv->phy_eee_partner_adv_get) || - (NULL == phy_drv->phy_eee_cap_get) || - (NULL == phy_drv->phy_eee_status_get)) { - return SW_NOT_SUPPORTED; - } - rv = hsl_port_prop_get_phyid(dev_id, port_id, &phy_addr); - SW_RTN_ON_ERROR (rv); - rv = phy_drv->phy_eee_adv_get(dev_id, phy_addr, &adv); - SW_RTN_ON_ERROR (rv); - port_eee_cfg->advertisement = adv; - rv = phy_drv->phy_eee_partner_adv_get(dev_id, phy_addr, &lp_adv); - SW_RTN_ON_ERROR (rv); - port_eee_cfg->link_partner_advertisement = lp_adv; - rv = phy_drv->phy_eee_cap_get(dev_id, phy_addr, &cap); - SW_RTN_ON_ERROR (rv); - port_eee_cfg->capability = cap; - rv = phy_drv->phy_eee_status_get(dev_id, phy_addr, &status); - SW_RTN_ON_ERROR (rv); - port_eee_cfg->eee_status = status; - - if (port_eee_cfg->advertisement) { - port_eee_cfg->enable = A_TRUE; - } else { - port_eee_cfg->enable = A_FALSE; - } - rv = mp_mac_lpi_ctrl_status_get(dev_id, gmac_id, &mac_lpi_ctrl_status); - SW_RTN_ON_ERROR (rv); - port_eee_cfg->lpi_tx_enable = mac_lpi_ctrl_status.bf.lpi_enable; - - rv = mp_mac_lpi_timer_ctrl_get(dev_id, gmac_id, &mac_lpi_timer_ctrl); - SW_RTN_ON_ERROR (rv); - port_eee_cfg->lpi_wakeup_timer = mac_lpi_timer_ctrl.bf.lpi_tw_timer; - - return rv; -} - -static sw_error_t -adpt_mp_port_interface_mode_status_get(a_uint32_t dev_id, - a_uint32_t port_id, fal_port_interface_mode_t * mode) -{ - sw_error_t rv = SW_OK; - a_uint32_t phy_id = 0; - hsl_phy_ops_t *phy_drv; - - ADPT_DEV_ID_CHECK(dev_id); - ADPT_NULL_POINT_CHECK(mode); - - SW_RTN_ON_NULL(phy_drv = hsl_phy_api_ops_get(dev_id, port_id)); - SW_RTN_ON_NULL(phy_drv->phy_interface_mode_status_get); - - rv = hsl_port_prop_get_phyid(dev_id, port_id, &phy_id); - SW_RTN_ON_ERROR (rv); - - rv = phy_drv->phy_interface_mode_status_get(dev_id, phy_id,mode); - - return rv; -} - -static sw_error_t -adpt_mp_port_interface_mode_switch(a_uint32_t dev_id, a_uint32_t port_id) -{ - sw_error_t rv = SW_OK; - fal_port_interface_mode_t port_mode_new = PORT_INTERFACE_MODE_MAX; - a_uint32_t uniphy_mode_old = PORT_WRAPPER_MAX; - a_uint32_t uniphy_mode_new = PORT_WRAPPER_MAX; - a_bool_t force_port; - - force_port = ssdk_port_feature_get(dev_id, port_id, PHY_F_FORCE); - if ((port_id == SSDK_PHYSICAL_PORT1) || (force_port == A_TRUE)) { - return SW_OK; - } - rv = adpt_mp_port_interface_mode_status_get(dev_id, - port_id, &port_mode_new); - SW_RTN_ON_ERROR(rv); - - if (port_mode_new == PHY_SGMII_BASET) { - uniphy_mode_new = PORT_WRAPPER_SGMII_CHANNEL0; - } else if (port_mode_new == PORT_SGMII_PLUS) { - uniphy_mode_new = PORT_WRAPPER_SGMII_PLUS; - } else { - return SW_NOT_SUPPORTED; - } - uniphy_mode_old = ssdk_dt_global_get_mac_mode(dev_id, - SSDK_UNIPHY_INSTANCE0); - if (uniphy_mode_new != uniphy_mode_old) { - rv = adpt_mp_uniphy_mode_configure(dev_id, - SSDK_UNIPHY_INSTANCE0, uniphy_mode_new); - SW_RTN_ON_ERROR(rv); - ssdk_dt_global_set_mac_mode(dev_id, - SSDK_UNIPHY_INSTANCE0, uniphy_mode_new); - } - - return rv; -} - -static sw_error_t -_adpt_mp_port_phy_status_get(a_uint32_t dev_id, a_uint32_t port_id, - struct port_phy_status *phy_status) -{ - sw_error_t rv = 0; - a_uint32_t phy_addr; - hsl_phy_ops_t *phy_drv; - - ADPT_DEV_ID_CHECK(dev_id); - ADPT_NULL_POINT_CHECK(phy_status); - - SW_RTN_ON_NULL (phy_drv = hsl_phy_api_ops_get (dev_id, port_id)); - SW_RTN_ON_NULL (phy_drv->phy_get_status); - - rv = hsl_port_prop_get_phyid (dev_id, port_id, &phy_addr); - SW_RTN_ON_ERROR (rv); - rv = phy_drv->phy_get_status (dev_id, phy_addr, phy_status); - SW_RTN_ON_ERROR (rv); - - return rv; -} - -static sw_error_t -_adpt_mp_port_link_down_update(struct qca_phy_priv *priv, - a_uint32_t port_id) -{ - sw_error_t rv = 0; - - /* disable rx mac, gcc uniphy port and gcc mac port status */ - rv = adpt_mp_port_rxmac_status_set(priv->device_id, port_id, A_FALSE); - SW_RTN_ON_ERROR (rv); - rv = adpt_mp_gcc_uniphy_port_clock_set(priv->device_id, port_id, A_FALSE); - SW_RTN_ON_ERROR (rv); - _adpt_mp_gcc_mac_clock_set(priv->device_id, port_id, A_FALSE); - SW_RTN_ON_ERROR (rv); - - /* switch interface mode if necessary under link down*/ - rv = adpt_mp_port_interface_mode_switch(priv->device_id, port_id); - SW_RTN_ON_ERROR (rv); - SSDK_DEBUG("MP port %d interface mode switch under link down!\n", - port_id); - return rv; -} - -static a_bool_t -_adpt_mp_port_status_change(struct qca_phy_priv *priv, a_uint32_t port_id, - struct port_phy_status phy_status) -{ - if ((a_uint32_t)phy_status.speed != priv->port_old_speed[port_id - 1]) - return A_TRUE; - if ((a_uint32_t)phy_status.duplex != priv->port_old_duplex[port_id - 1]) - return A_TRUE; - if (phy_status.tx_flowctrl != priv->port_old_tx_flowctrl[port_id - 1]) - return A_TRUE; - if (phy_status.rx_flowctrl != priv->port_old_rx_flowctrl[port_id - 1]) - return A_TRUE; - return A_FALSE; -} - -sw_error_t -adpt_mp_port_link_up_change_update(struct qca_phy_priv *priv, - a_uint32_t port_id, struct port_phy_status phy_status) -{ - sw_error_t rv = 0; - - if ((a_uint32_t)phy_status.speed != - priv->port_old_speed[port_id - 1]) { - - /* configure gcc speed clock frequency */ - rv = _adpt_mp_port_gcc_speed_clock_set(priv->device_id, - port_id, phy_status.speed); - SW_RTN_ON_ERROR (rv); - - /* config mac speed */ - rv = adpt_mp_port_mac_speed_set(priv->device_id, - port_id, phy_status.speed); - SW_RTN_ON_ERROR (rv); - - priv->port_old_speed[port_id - 1] = - (a_uint32_t)phy_status.speed; - - SSDK_DEBUG("Port %d up and speed is %d\n", port_id, - priv->port_old_speed[port_id - 1]); - } - /* link up duplex change configuration */ - if ((a_uint32_t)phy_status.duplex != - priv->port_old_duplex[port_id - 1]) { - - rv = adpt_mp_port_mac_duplex_set(priv->device_id, - port_id, phy_status.duplex); - - priv->port_old_duplex[port_id - 1] = - (a_uint32_t)phy_status.duplex; - SW_RTN_ON_ERROR (rv); - - SSDK_DEBUG("Port %d up and duplex is %d\n", port_id, - priv->port_old_duplex[port_id - 1]); - } - /* tx flowctrl configuration*/ - if (priv->port_tx_flowctrl_forcemode[port_id - 1] != A_TRUE) { - if (phy_status.duplex == FAL_HALF_DUPLEX) { - phy_status.tx_flowctrl = A_TRUE; - } - if (phy_status.tx_flowctrl != - priv->port_old_tx_flowctrl[port_id - 1]) { - rv = adpt_mp_port_txfc_status_set(priv->device_id, - port_id, phy_status.tx_flowctrl); - SW_RTN_ON_ERROR (rv); - priv->port_old_tx_flowctrl[port_id - 1] = - phy_status.tx_flowctrl; - - SSDK_DEBUG("Port %d up and tx flowctrl is %d\n", - port_id, - priv->port_old_tx_flowctrl[port_id - 1]); - } - } - /*rx flowctrl configuration*/ - if (priv->port_rx_flowctrl_forcemode[port_id - 1] != A_TRUE) { - if (phy_status.duplex == FAL_HALF_DUPLEX) { - phy_status.rx_flowctrl = A_TRUE; - } - if (phy_status.rx_flowctrl != - priv->port_old_rx_flowctrl[port_id - 1]) { - rv = adpt_mp_port_rxfc_status_set(priv->device_id, - port_id, phy_status.rx_flowctrl); - SW_RTN_ON_ERROR (rv); - priv->port_old_rx_flowctrl[port_id - 1] = - phy_status.rx_flowctrl; - - SSDK_DEBUG("Port %d up and rx flowctrl is %d\n", - port_id, - priv->port_old_rx_flowctrl[port_id-1]); - } - } - - return rv; -} - -sw_error_t -adpt_mp_port_link_up_update(struct qca_phy_priv *priv, - a_uint32_t port_id, struct port_phy_status phy_status) -{ - sw_error_t rv = 0; - a_bool_t change; - - /* port phy status change check*/ - change = _adpt_mp_port_status_change(priv, port_id, - phy_status); - - rv = adpt_mp_port_txmac_status_set(priv->device_id, port_id, - A_FALSE); - SW_RTN_ON_ERROR (rv); - - /* switch interface mode if necessary under link up */ - rv = adpt_mp_port_interface_mode_switch(priv->device_id, port_id); - SW_RTN_ON_ERROR (rv); - SSDK_DEBUG("MP port %d interface mode switch under link up!\n", - port_id); - /* link up status change*/ - if (change == A_TRUE) { - rv = adpt_mp_port_link_up_change_update(priv, - port_id, phy_status); - SW_RTN_ON_ERROR (rv); - } - - rv = adpt_mp_gcc_uniphy_port_clock_set(priv->device_id, - port_id, A_TRUE); - SW_RTN_ON_ERROR (rv); - rv =_adpt_mp_gcc_mac_clock_set(priv->device_id, - port_id, A_TRUE); - SW_RTN_ON_ERROR (rv); - - msleep(50); - - rv = adpt_mp_port_reset_set(priv->device_id, port_id); - SW_RTN_ON_ERROR (rv); - rv = adpt_mp_port_txmac_status_set(priv->device_id, - port_id, A_TRUE); - SW_RTN_ON_ERROR (rv); - rv = adpt_mp_port_rxmac_status_set(priv->device_id, - port_id, A_TRUE); - SW_RTN_ON_ERROR (rv); - - return rv; -} - -sw_error_t -adpt_mp_port_netdev_change_notify(struct qca_phy_priv *priv, - a_uint32_t port_id) -{ - sw_error_t rv = 0; - struct port_phy_status phy_status = {0}; - a_uint32_t portbmp[SW_MAX_NR_DEV] = {0}; - - portbmp[priv->device_id] = qca_ssdk_port_bmp_get(priv->device_id); - - if(!(portbmp[priv->device_id] & (0x1 << port_id))) { - SSDK_ERROR("netdev change notify with incorrect port %d\n", - port_id); - return SW_BAD_VALUE; - } - - rv = _adpt_mp_port_phy_status_get(priv->device_id, port_id, - &phy_status); - if (rv != SW_OK) { - SSDK_ERROR("failed to get port %d status return value is %d\n", - port_id, rv); - return rv; - } - /* link status from up to down*/ - if ((phy_status.link_status == PORT_LINK_DOWN) && - (priv->port_old_link[port_id - 1] == PORT_LINK_UP)) { - SSDK_DEBUG("MP port %d change to link down status\n", port_id); - /* link down configuration*/ - rv = _adpt_mp_port_link_down_update(priv, port_id); - SW_RTN_ON_ERROR (rv); - priv->port_old_link[port_id - 1] = phy_status.link_status ; - } - /* link status from down to up */ - if ((phy_status.link_status == PORT_LINK_UP) && - (priv->port_old_link[port_id - 1] == PORT_LINK_DOWN)) { - SSDK_DEBUG("Port %d change to link up status\n", port_id); - rv = adpt_mp_port_link_up_update(priv, port_id, phy_status); - SW_RTN_ON_ERROR (rv); - priv->port_old_link[port_id - 1] = phy_status.link_status; - } - SSDK_DEBUG("MP port %d link is %d speed is %d duplex is %d" - " tx_flowctrl is %d rx_flowctrl is %d\n", - port_id, priv->port_old_link[port_id - 1], - priv->port_old_speed[port_id - 1], - priv->port_old_duplex[port_id - 1], - priv->port_old_tx_flowctrl[port_id - 1], - priv->port_old_rx_flowctrl[port_id - 1]); - - return rv; -} - -static sw_error_t -adpt_mp_port_lpi_polling_task(struct qca_phy_priv *priv) -{ - a_uint32_t port_id; - a_uint32_t portbmp[SW_MAX_NR_DEV] = {0}; - sw_error_t rv = SW_OK; - - portbmp[priv->device_id] = qca_ssdk_port_bmp_get(priv->device_id); - - for (port_id = SSDK_PHYSICAL_PORT1; port_id < SW_MAX_NR_PORT; port_id ++) { - - if(!(portbmp[priv->device_id] & BIT(port_id))) - continue; - if (port_lpi_status[priv->device_id] & BIT(port_id-1)) { - rv = adpt_mp_port_mac_eee_enable_set(priv->device_id, - port_id, A_TRUE); - SW_RTN_ON_ERROR(rv); - } - } - return SW_OK; -} - -static sw_error_t -adpt_mp_port_speed_get(a_uint32_t dev_id, fal_port_t port_id, - fal_port_speed_t * pspeed) -{ - sw_error_t rv = 0; - a_uint32_t phy_id = 0; - hsl_phy_ops_t *phy_drv; - struct port_phy_status port_mac_status = {0}; - - ADPT_DEV_ID_CHECK(dev_id); - ADPT_NULL_POINT_CHECK(pspeed); - - if (A_TRUE != hsl_port_prop_check (dev_id, port_id, HSL_PP_PHY)) { - return SW_BAD_PARAM; - } - - /* for those ports without PHY device should be s17c port */ - if (A_FALSE == _adpt_mp_port_phy_connected (dev_id, port_id)) { - rv = adpt_mp_port_mac_status_get(dev_id, port_id, &port_mac_status); - SW_RTN_ON_ERROR (rv); - *pspeed= port_mac_status.speed; - } else { - SW_RTN_ON_NULL (phy_drv = hsl_phy_api_ops_get (dev_id, - port_id)); - if (NULL == phy_drv->phy_speed_get) { - return SW_NOT_SUPPORTED; - } - - rv = hsl_port_prop_get_phyid (dev_id, port_id, &phy_id); - SW_RTN_ON_ERROR (rv); - rv = phy_drv->phy_speed_get (dev_id, phy_id, pspeed); - SW_RTN_ON_ERROR (rv); - } - - return rv; -} - -static sw_error_t -adpt_mp_port_duplex_get(a_uint32_t dev_id, fal_port_t port_id, - fal_port_duplex_t * pduplex) -{ - sw_error_t rv = 0; - a_uint32_t phy_id = 0; - hsl_phy_ops_t *phy_drv; - struct port_phy_status port_mac_status = {0}; - - ADPT_DEV_ID_CHECK(dev_id); - ADPT_NULL_POINT_CHECK(pduplex); - - if (A_TRUE != hsl_port_prop_check (dev_id, port_id, HSL_PP_PHY)) { - return SW_BAD_PARAM; - } - - /* for those ports without PHY device should be s17c port */ - if (A_FALSE == _adpt_mp_port_phy_connected (dev_id, port_id)) { - rv = adpt_mp_port_mac_status_get(dev_id, port_id, &port_mac_status); - SW_RTN_ON_ERROR (rv); - *pduplex = port_mac_status.duplex; - } else { - SW_RTN_ON_NULL (phy_drv = hsl_phy_api_ops_get (dev_id, - port_id)); - if (NULL == phy_drv->phy_duplex_get) { - return SW_NOT_SUPPORTED; - } - - rv = hsl_port_prop_get_phyid (dev_id, port_id, &phy_id); - SW_RTN_ON_ERROR (rv); - rv = phy_drv->phy_duplex_get (dev_id, phy_id, pduplex); - SW_RTN_ON_ERROR (rv); - } - - return rv; -} - -static sw_error_t -adpt_mp_port_link_status_get(a_uint32_t dev_id, fal_port_t port_id, - a_bool_t * status) -{ - sw_error_t rv = 0; - a_uint32_t phy_id = 0; - hsl_phy_ops_t *phy_drv; - - ADPT_DEV_ID_CHECK(dev_id); - ADPT_NULL_POINT_CHECK(status); - - if (A_TRUE != hsl_port_prop_check (dev_id, port_id, HSL_PP_PHY)) { - return SW_BAD_PARAM; - } - - /* for those ports without PHY device should be s17c port */ - if (A_FALSE == _adpt_mp_port_phy_connected (dev_id, port_id)) { - *status = A_TRUE; - } else { - SW_RTN_ON_NULL (phy_drv = hsl_phy_api_ops_get (dev_id, - port_id)); - if (NULL == phy_drv->phy_link_status_get) { - return SW_NOT_SUPPORTED; - } - - rv = hsl_port_prop_get_phyid (dev_id, port_id, &phy_id); - SW_RTN_ON_ERROR (rv); - - *status = phy_drv->phy_link_status_get (dev_id, phy_id); - } - - return SW_OK; - -} - -sw_error_t -adpt_mp_portctrl_init(a_uint32_t dev_id) -{ - adpt_api_t *p_adpt_api = NULL; - - p_adpt_api = adpt_api_ptr_get(dev_id); - - if(p_adpt_api == NULL) - { - return SW_FAIL; - } -#ifndef IN_PORTCONTROL_MINI - p_adpt_api->adpt_port_txmac_status_get = adpt_mp_port_txmac_status_get; - p_adpt_api->adpt_port_rxmac_status_get = adpt_mp_port_rxmac_status_get; - p_adpt_api->adpt_port_rxfc_status_get = adpt_mp_port_rxfc_status_get; - p_adpt_api->adpt_port_txfc_status_get = adpt_mp_port_txfc_status_get; - p_adpt_api->adpt_port_flowctrl_get = adpt_mp_port_flowctrl_get; - p_adpt_api->adpt_port_flowctrl_forcemode_get = - adpt_mp_port_flowctrl_forcemode_get; - p_adpt_api->adpt_port_promisc_mode_get = adpt_mp_port_promisc_mode_get; - p_adpt_api->adpt_port_interface_3az_status_get = adpt_mp_port_mac_eee_enable_get; -#endif - p_adpt_api->adpt_port_txmac_status_set = adpt_mp_port_txmac_status_set; - p_adpt_api->adpt_port_rxmac_status_set = adpt_mp_port_rxmac_status_set; - p_adpt_api->adpt_port_rxfc_status_set = adpt_mp_port_rxfc_status_set; - p_adpt_api->adpt_port_txfc_status_set = adpt_mp_port_txfc_status_set; - p_adpt_api->adpt_port_flowctrl_set = adpt_mp_port_flowctrl_set; - p_adpt_api->adpt_port_flowctrl_forcemode_set = - adpt_mp_port_flowctrl_forcemode_set; - p_adpt_api->adpt_port_max_frame_size_set = adpt_mp_port_max_frame_size_set; - p_adpt_api->adpt_port_max_frame_size_get = adpt_mp_port_max_frame_size_get; - p_adpt_api->adpt_port_promisc_mode_set = adpt_mp_port_promisc_mode_set; - p_adpt_api->adpt_port_mac_speed_set = adpt_mp_port_mac_speed_set; - p_adpt_api->adpt_port_speed_get = adpt_mp_port_speed_get; - p_adpt_api->adpt_port_mac_duplex_set = adpt_mp_port_mac_duplex_set; - p_adpt_api->adpt_port_duplex_get = adpt_mp_port_duplex_get; - p_adpt_api->adpt_port_link_status_get = adpt_mp_port_link_status_get; - p_adpt_api->adpt_port_interface_3az_status_set = adpt_mp_port_mac_eee_enable_set; - p_adpt_api->adpt_port_interface_eee_cfg_set = adpt_mp_port_interface_eee_cfg_set; - p_adpt_api->adpt_port_interface_eee_cfg_get = adpt_mp_port_interface_eee_cfg_get; - p_adpt_api->adpt_port_netdev_notify_set = adpt_mp_port_netdev_change_notify; - p_adpt_api->adpt_port_polling_sw_sync_set = adpt_mp_port_lpi_polling_task; - - return SW_OK; -} -/** - * @} - */ diff --git a/feeds/ipq807x/qca-ssdk/src/src/adpt/mp/adpt_mp_uniphy.c b/feeds/ipq807x/qca-ssdk/src/src/adpt/mp/adpt_mp_uniphy.c deleted file mode 100644 index 77acad02b..000000000 --- a/feeds/ipq807x/qca-ssdk/src/src/adpt/mp/adpt_mp_uniphy.c +++ /dev/null @@ -1,398 +0,0 @@ -/* - * Copyright (c) 2020, The Linux Foundation. All rights reserved. - * - * Permission to use, copy, modify, and/or distribute this software for any - * purpose with or without fee is hereby granted, provided that the above - * copyright notice and this permission notice appear in all copies. - * - * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES - * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR - * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES - * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN - * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF - * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. - */ - -/** - * @defgroup - * @{ - */ -#include "sw.h" -#include "hppe_uniphy_reg.h" -#include "hppe_uniphy.h" -#include "hppe_init.h" -#include "ssdk_init.h" -#include "ssdk_clk.h" -#include "ssdk_dts.h" -#include "adpt.h" -#include "mp_uniphy_reg.h" -#include "mp_uniphy.h" -#include "hsl_phy.h" - -static sw_error_t -_adpt_mp_uniphy_calibrate(a_uint32_t dev_id, a_uint32_t uniphy_index) -{ - a_uint32_t reg_value = 0; - a_uint32_t retries = 100, calibration_done = 0; - union uniphy_offset_calib_4_u uniphy_offset_calib_4; - - memset(&uniphy_offset_calib_4, 0, sizeof(uniphy_offset_calib_4)); - ADPT_DEV_ID_CHECK(dev_id); - - if(ssdk_is_emulation(dev_id)){ - SSDK_INFO("uniphy_index %d on emulation platform\n", uniphy_index); - return SW_OK; - } - /*wait calibration done to uniphy*/ - while (calibration_done != UNIPHY_CALIBRATION_DONE) { - mdelay(1); - if (retries-- == 0) - { - SSDK_ERROR("uniphy callibration time out!\n"); - return SW_TIMEOUT; - } - reg_value = 0; - hppe_uniphy_offset_calib_4_get(dev_id, uniphy_index, &uniphy_offset_calib_4); - reg_value = uniphy_offset_calib_4.bf.mmd1_reg_calibration_done_reg; - - calibration_done = (reg_value & UNIPHY_CALIBRATION_DONE); - } - - return SW_OK; -} - -sw_error_t -adpt_mp_uniphy_adapter_port_reset(a_uint32_t dev_id, - a_uint32_t port_id) -{ - sw_error_t rv = SW_OK; - a_uint32_t uniphy_index = 0; - union uniphy_channel0_input_output_4_u uniphy_channel0_input_output_4; - - memset(&uniphy_channel0_input_output_4, 0, sizeof(uniphy_channel0_input_output_4)); - - if (port_id == SSDK_PHYSICAL_PORT2) { - uniphy_index = SSDK_UNIPHY_INSTANCE0; - } else { - SSDK_ERROR("uniphy adapter reset port_id is %d\n", port_id); - return SW_BAD_VALUE; - } - - rv = hppe_uniphy_channel0_input_output_4_get(dev_id, uniphy_index, - &uniphy_channel0_input_output_4); - SW_RTN_ON_ERROR (rv); - uniphy_channel0_input_output_4.bf.newaddedfromhere_ch0_adp_sw_rstn = 0; - rv = hppe_uniphy_channel0_input_output_4_set(dev_id, uniphy_index, - &uniphy_channel0_input_output_4); - SW_RTN_ON_ERROR (rv); - uniphy_channel0_input_output_4.bf.newaddedfromhere_ch0_adp_sw_rstn = 1; - rv = hppe_uniphy_channel0_input_output_4_set(dev_id, uniphy_index, - &uniphy_channel0_input_output_4); - SW_RTN_ON_ERROR (rv); - - return rv; -} - -sw_error_t -adpt_mp_gcc_uniphy_port_clock_set(a_uint32_t dev_id, a_uint32_t port_id, - a_bool_t enable) -{ - sw_error_t rv = SW_OK; - - if (port_id == SSDK_PHYSICAL_PORT1) { - qca_gcc_uniphy_port_clock_set(dev_id, SSDK_UNIPHY_INSTANCE0, - port_id, enable); - } else if (port_id == SSDK_PHYSICAL_PORT2) { - qca_gcc_uniphy_port_clock_set(dev_id, SSDK_UNIPHY_INSTANCE1, - port_id, enable); - } else { - return SW_BAD_VALUE; - } - - return rv; -} - -void -adpt_mp_gcc_uniphy_port_set(a_uint32_t dev_id, a_uint32_t port_id, - a_bool_t enable) -{ - enum unphy_rst_type rst_type; - - if (port_id == SSDK_PHYSICAL_PORT2) { - rst_type = UNIPHY1_SOFT_RESET_E; - } else { - return; - } - - if (enable == A_TRUE) { - ssdk_uniphy_reset(dev_id, rst_type, SSDK_RESET_DEASSERT); - } else { - ssdk_uniphy_reset(dev_id, rst_type, SSDK_RESET_ASSERT); - } - - return; -} - -void -adpt_mp_gcc_uniphy_port_reset(a_uint32_t dev_id, a_uint32_t port_id) -{ - adpt_mp_gcc_uniphy_port_set(dev_id, port_id, A_FALSE); - - msleep(100); - - adpt_mp_gcc_uniphy_port_set(dev_id, port_id, A_TRUE); - - return; -} - -static sw_error_t -adpt_mp_uniphy_reset(a_uint32_t dev_id, a_uint32_t uniphy_index) -{ - sw_error_t rv = SW_OK; - union pll_power_on_and_reset_u pll_software_reset; - - memset(&pll_software_reset, 0, sizeof(pll_software_reset)); - ADPT_DEV_ID_CHECK(dev_id); - - rv = hppe_uniphy_pll_reset_ctrl_get(dev_id, uniphy_index, - &pll_software_reset); - SW_RTN_ON_ERROR (rv); - pll_software_reset.bf.software_reset_analog_reset = 0; - rv = hppe_uniphy_pll_reset_ctrl_set(dev_id, uniphy_index, - &pll_software_reset); - SW_RTN_ON_ERROR (rv); - msleep(500); - pll_software_reset.bf.software_reset_analog_reset = 1; - rv = hppe_uniphy_pll_reset_ctrl_set(dev_id, uniphy_index, - &pll_software_reset); - SW_RTN_ON_ERROR (rv); - msleep(500); - - return SW_OK; -} - -static sw_error_t -adpt_mp_uniphy_mode_ctrl_set(a_uint32_t dev_id, - a_uint32_t uniphy_index, a_uint32_t mode) -{ - sw_error_t rv = SW_OK; - union uniphy_mode_ctrl_u uniphy_mode_ctrl; - union uniphy_channel0_input_output_4_u uniphy_force_ctrl; - a_bool_t force_port = 0; - - memset(&uniphy_mode_ctrl, 0, sizeof(uniphy_mode_ctrl)); - memset(&uniphy_force_ctrl, 0, sizeof(uniphy_force_ctrl)); - - force_port = ssdk_port_feature_get(dev_id, SSDK_PHYSICAL_PORT2, - PHY_F_FORCE); - /* configure uniphy mode ctrl to sgmii/sgmiiplus */ - rv = hppe_uniphy_mode_ctrl_get(dev_id, uniphy_index, &uniphy_mode_ctrl); - SW_RTN_ON_ERROR (rv); - if (mode == PORT_WRAPPER_SGMII_CHANNEL0) { - uniphy_mode_ctrl.bf.newaddedfromhere_sg_mode = - UNIPHY_SGMII_MODE_ENABLE; - uniphy_mode_ctrl.bf.newaddedfromhere_sgplus_mode = - UNIPHY_SGMIIPLUS_MODE_DISABLE; - if (force_port == A_TRUE) { - rv = hppe_uniphy_channel0_input_output_4_get(dev_id, - uniphy_index, &uniphy_force_ctrl); - SW_RTN_ON_ERROR (rv); - uniphy_force_ctrl.bf.newaddedfromhere_ch0_force_speed_25m = - UNIPHY_FORCE_SPEED_ENABLE; - rv = hppe_uniphy_channel0_input_output_4_set(dev_id, - uniphy_index, &uniphy_force_ctrl); - SW_RTN_ON_ERROR (rv); - } - } else { - uniphy_mode_ctrl.bf.newaddedfromhere_sg_mode = - UNIPHY_SGMII_MODE_DISABLE; - uniphy_mode_ctrl.bf.newaddedfromhere_sgplus_mode = - UNIPHY_SGMIIPLUS_MODE_ENABLE; - } - uniphy_mode_ctrl.bf.newaddedfromhere_ch0_autoneg_mode = - UNIPHY_ATHEROS_NEGOTIATION; - uniphy_mode_ctrl.bf.newaddedfromhere_ch0_psgmii_qsgmii = - UNIPHY_CH0_QSGMII_SGMII_MODE; - uniphy_mode_ctrl.bf.newaddedfromhere_ch0_qsgmii_sgmii = - UNIPHY_CH0_SGMII_MODE; - uniphy_mode_ctrl.bf.newaddedfromhere_xpcs_mode = - UNIPHY_XPCS_MODE_DISABLE; - rv = hppe_uniphy_mode_ctrl_set(dev_id, uniphy_index, &uniphy_mode_ctrl); - - return rv; -} - -static sw_error_t -_adpt_mp_uniphy_clk_output_ctrl_set(a_uint32_t dev_id, a_uint32_t index, - a_uint32_t clk_rate) -{ - sw_error_t rv = SW_OK; - union uniphy_clock_output_control_u clock_output; - - memset(&clock_output, 0, sizeof(union uniphy_clock_output_control_u)); - clock_output.bf.ref_clk_output_drv = UNIPHY_CLK_DRV_1; - clock_output.bf.ref_clk_output_en = A_TRUE; - SSDK_INFO("uniphy will output clock as %dHz\n", clk_rate); - if(clk_rate == UNIPHY_CLK_RATE_25M) - { - clock_output.bf.ref_clk_output_div = UNIPHY_CLK_DIV_25M; - } - else if(clk_rate == UNIPHY_CLK_RATE_50M) - { - clock_output.bf.ref_clk_output_div = UNIPHY_CLK_DIV_50M; - } - else - { - return SW_NOT_SUPPORTED; - } - rv = mp_uniphy_clock_output_control_set(dev_id, index, - &clock_output); - - return rv; -} - -static void -_adpt_mp_uniphy_clk_output_set(a_uint32_t dev_id, a_uint32_t index) -{ - a_uint32_t phy_id =0; - a_bool_t force_port = A_FALSE; - a_uint32_t force_speed = 0; - - /*when MP connect s17c or qca803x, need to reconfigure reference clock - as 25M for port 2*/ - force_port = ssdk_port_feature_get(dev_id, SSDK_PHYSICAL_PORT2, PHY_F_FORCE); - force_speed = ssdk_port_force_speed_get(dev_id, SSDK_PHYSICAL_PORT2); - - if ((force_port) && (force_speed == FAL_SPEED_1000)) - { - _adpt_mp_uniphy_clk_output_ctrl_set(dev_id, index, UNIPHY_CLK_RATE_25M); - } - phy_id = hsl_port_phyid_get(dev_id, SSDK_PHYSICAL_PORT2); - if (phy_id == QCA8030_PHY || phy_id == QCA8033_PHY || phy_id == QCA8035_PHY) - { - _adpt_mp_uniphy_clk_output_ctrl_set(dev_id, index, UNIPHY_CLK_RATE_25M); - } - - return; -} - -sw_error_t -adpt_mp_uniphy_mode_configure(a_uint32_t dev_id, a_uint32_t index, a_uint32_t mode) -{ - sw_error_t rv = SW_OK; - a_uint32_t clock = UNIPHY_CLK_RATE_125M; - - union uniphy_misc2_phy_mode_u uniphy_misc2_phy_mode; - - memset(&uniphy_misc2_phy_mode, 0, sizeof(uniphy_misc2_phy_mode)); - - ADPT_DEV_ID_CHECK(dev_id); - - if (index != SSDK_UNIPHY_INSTANCE0) { - SSDK_ERROR("uniphy index is %d\n", index); - return SW_BAD_VALUE; - } - - if (mode == PORT_WRAPPER_MAX) { - adpt_mp_gcc_uniphy_port_set(dev_id, SSDK_PHYSICAL_PORT2, - A_FALSE); - return SW_OK; - } else if ((mode == PORT_WRAPPER_SGMII_CHANNEL0) || - (mode == PORT_WRAPPER_SGMII_PLUS)) { - adpt_mp_gcc_uniphy_port_set(dev_id, SSDK_PHYSICAL_PORT2, - A_TRUE); - } else { - return SW_NOT_SUPPORTED; - } - - /*set the PHY mode to SGMII or SGMIIPLUS*/ - rv = hppe_uniphy_phy_mode_ctrl_get(dev_id, index, - &uniphy_misc2_phy_mode); - SW_RTN_ON_ERROR (rv); - if (mode == PORT_WRAPPER_SGMII_CHANNEL0) { - uniphy_misc2_phy_mode.bf.phy_mode = - UNIPHY_PHY_SGMII_MODE; - clock = UNIPHY_CLK_RATE_125M; - } else { - uniphy_misc2_phy_mode.bf.phy_mode = - UNIPHY_PHY_SGMIIPLUS_MODE; - clock = UNIPHY_CLK_RATE_312M; - } - rv = hppe_uniphy_phy_mode_ctrl_set(dev_id, index, - &uniphy_misc2_phy_mode); - SW_RTN_ON_ERROR (rv); - - /* reset uniphy */ - rv = adpt_mp_uniphy_reset(dev_id, index); - SW_RTN_ON_ERROR (rv); - - /* disable uniphy port clock */ - rv = adpt_mp_gcc_uniphy_port_clock_set(dev_id, SSDK_PHYSICAL_PORT2, - A_FALSE); - SW_RTN_ON_ERROR (rv); - - rv = adpt_mp_uniphy_mode_ctrl_set(dev_id, index, mode); - SW_RTN_ON_ERROR (rv); - - adpt_mp_gcc_uniphy_port_reset(dev_id, SSDK_PHYSICAL_PORT2); - - /* wait uniphy calibration done */ - rv = _adpt_mp_uniphy_calibrate(dev_id, index); - SW_RTN_ON_ERROR (rv); - - /* enable instance clock */ - rv = adpt_mp_gcc_uniphy_port_clock_set(dev_id, SSDK_PHYSICAL_PORT2, - A_TRUE); - SW_RTN_ON_ERROR (rv); - - if (SW_OK == rv) { - /* index + 1 point to mp uniphy clock */ - ssdk_mp_raw_clock_set(index + 1, UNIPHY_RX, clock); - ssdk_mp_raw_clock_set(index + 1, UNIPHY_TX, clock); - } - - if (mode == PORT_WRAPPER_SGMII_CHANNEL0) { - SSDK_DEBUG("mp uniphy %d sgmii configuration is done!\n", index); - } else { - SSDK_DEBUG("mp uniphy %d sgmiiplus configuration is done!\n", index); - } - - return rv; -} - -sw_error_t -adpt_mp_uniphy_mode_set(a_uint32_t dev_id, a_uint32_t index, a_uint32_t mode) -{ - sw_error_t rv = SW_OK; - - rv = adpt_mp_uniphy_mode_configure(dev_id, index, mode); - SW_RTN_ON_ERROR(rv); - _adpt_mp_uniphy_clk_output_set(dev_id, index); - - /*port2 is connected with PHY, need gpio reset*/ - if(!ssdk_port_feature_get(dev_id, SSDK_PHYSICAL_PORT2, PHY_F_FORCE)) - { - hsl_port_phy_gpio_reset(dev_id, SSDK_PHYSICAL_PORT2); - msleep(100); - hsl_port_phy_hw_init(dev_id, SSDK_PHYSICAL_PORT2); - } - - return rv; -} - -sw_error_t adpt_mp_uniphy_init(a_uint32_t dev_id) -{ - adpt_api_t *p_adpt_api = NULL; - - ADPT_DEV_ID_CHECK(dev_id); - SW_RTN_ON_NULL(p_adpt_api = adpt_api_ptr_get(dev_id)); - - p_adpt_api->adpt_uniphy_mode_set = adpt_mp_uniphy_mode_set; - - return SW_OK; -} - -/** - * @} - */ diff --git a/feeds/ipq807x/qca-ssdk/src/src/adpt/sfp/Makefile b/feeds/ipq807x/qca-ssdk/src/src/adpt/sfp/Makefile deleted file mode 100755 index fdf2ab6b2..000000000 --- a/feeds/ipq807x/qca-ssdk/src/src/adpt/sfp/Makefile +++ /dev/null @@ -1,16 +0,0 @@ -LOC_DIR=src/adpt/sfp -LIB=ADPT - -include $(PRJ_PATH)/make/config.mk - -SRC_LIST= - -ifeq (TRUE, $(IN_SFP)) - SRC_LIST += adpt_sfp.c -endif - -include $(PRJ_PATH)/make/components.mk -include $(PRJ_PATH)/make/defs.mk -include $(PRJ_PATH)/make/target.mk - -all: dep obj diff --git a/feeds/ipq807x/qca-ssdk/src/src/adpt/sfp/adpt_sfp.c b/feeds/ipq807x/qca-ssdk/src/src/adpt/sfp/adpt_sfp.c deleted file mode 100755 index f55512790..000000000 --- a/feeds/ipq807x/qca-ssdk/src/src/adpt/sfp/adpt_sfp.c +++ /dev/null @@ -1,668 +0,0 @@ -/* - * Copyright (c) 2019, The Linux Foundation. All rights reserved. - * Permission to use, copy, modify, and/or distribute this software for - * any purpose with or without fee is hereby granted, provided that the - * above copyright notice and this permission notice appear in all copies. - * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES - * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR - * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES - * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN - * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT - * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. - */ - - -/** - * @defgroup - * @{ - */ -#include "sw.h" -#include "adpt.h" -#include "sfp_reg.h" -#include "sfp.h" -#include "hsl_phy.h" - - -#define ADPT_RTN_ON_INVALID_DATA_OFFSET(offset) \ - do { if (offset > 0xff) return(SW_BAD_PARAM); } while(0); - -#define ADPT_PORT_I2C_CAP_CHECK(dev_id, port_id) \ - do { if (PHY_I2C_ACCESS != hsl_port_phy_access_type_get(dev_id, port_id)) \ - return(SW_NOT_SUPPORTED); } while(0); - -sw_error_t -adpt_sfp_diag_ctrl_status_get(a_uint32_t dev_id, a_uint32_t port_id, - fal_sfp_ctrl_status_t *ctrl_status) -{ - sw_error_t rv = SW_OK; - union sfp_diag_optional_ctrl_status_u sfp_diag_optional_ctrl_status; - union sfp_diag_extended_ctrl_status_u sfp_diag_extended_ctrl_status; - - ADPT_DEV_ID_CHECK(dev_id); - ADPT_PORT_I2C_CAP_CHECK(dev_id, port_id); - ADPT_NULL_POINT_CHECK(ctrl_status); - - memset(&sfp_diag_optional_ctrl_status, 0, sizeof(sfp_diag_optional_ctrl_status)); - memset(&sfp_diag_extended_ctrl_status, 0, sizeof(sfp_diag_extended_ctrl_status)); - - rv = sfp_diag_optional_ctrl_status_get(dev_id, - port_id, &sfp_diag_optional_ctrl_status); - SW_RTN_ON_ERROR(rv); - - rv = sfp_diag_extended_ctrl_status_get(dev_id, - port_id, &sfp_diag_extended_ctrl_status); - SW_RTN_ON_ERROR(rv); - - ctrl_status->data_ready = sfp_diag_optional_ctrl_status.bf.data_ready; - ctrl_status->rx_los = sfp_diag_optional_ctrl_status.bf.rx_los; - ctrl_status->tx_fault = sfp_diag_optional_ctrl_status.bf.tx_fault; - ctrl_status->soft_rate_sel = sfp_diag_optional_ctrl_status.bf.soft_rate_sel; - ctrl_status->rate_sel = sfp_diag_optional_ctrl_status.bf.rate_sel; - ctrl_status->rs_state = sfp_diag_optional_ctrl_status.bf.rs; - ctrl_status->soft_tx_disable = sfp_diag_optional_ctrl_status.bf.soft_tx_disable_sel; - ctrl_status->tx_disable = sfp_diag_optional_ctrl_status.bf.tx_disable; - - ctrl_status->pwr_level_sel = sfp_diag_extended_ctrl_status.bf.pwr_level_sel; - ctrl_status->pwr_level_op_state = sfp_diag_extended_ctrl_status.bf.pwr_level_op_state; - ctrl_status->soft_rs_sel = sfp_diag_extended_ctrl_status.bf.soft_rs_sel; - - return SW_OK; -} - -sw_error_t -adpt_sfp_diag_extenal_calibration_const_get(a_uint32_t dev_id, a_uint32_t port_id, - fal_sfp_cal_const_t *cal_const) -{ - sw_error_t rv = SW_OK; - union sfp_diag_cal_const_u sfp_diag_cal_const; - - ADPT_DEV_ID_CHECK(dev_id); - ADPT_PORT_I2C_CAP_CHECK(dev_id, port_id); - ADPT_NULL_POINT_CHECK(cal_const); - - memset(&sfp_diag_cal_const, 0, sizeof(sfp_diag_cal_const)); - - rv = sfp_diag_cal_const_get(dev_id, port_id, &sfp_diag_cal_const); - SW_RTN_ON_ERROR(rv); - - cal_const->rx_power4 = sfp_diag_cal_const.bf.rx_pwr_4_0 << 24 - | sfp_diag_cal_const.bf.rx_pwr_4_1 << 16 - | sfp_diag_cal_const.bf.rx_pwr_4_2 << 8 - | sfp_diag_cal_const.bf.rx_pwr_4_3; - cal_const->rx_power3 = sfp_diag_cal_const.bf.rx_pwr_3_0 << 24 - | sfp_diag_cal_const.bf.rx_pwr_3_1 << 16 - | sfp_diag_cal_const.bf.rx_pwr_3_2 << 8 - | sfp_diag_cal_const.bf.rx_pwr_3_3; - cal_const->rx_power2 = sfp_diag_cal_const.bf.rx_pwr_2_0 << 24 - | sfp_diag_cal_const.bf.rx_pwr_2_1 << 16 - | sfp_diag_cal_const.bf.rx_pwr_2_2 << 8 - | sfp_diag_cal_const.bf.rx_pwr_2_3; - cal_const->rx_power1 = sfp_diag_cal_const.bf.rx_pwr_1_0 << 24 - | sfp_diag_cal_const.bf.rx_pwr_1_1 << 16 - | sfp_diag_cal_const.bf.rx_pwr_1_2 << 8 - | sfp_diag_cal_const.bf.rx_pwr_1_3; - cal_const->rx_power0 = sfp_diag_cal_const.bf.rx_pwr_0_0 << 24 - | sfp_diag_cal_const.bf.rx_pwr_0_1 << 16 - | sfp_diag_cal_const.bf.rx_pwr_0_2 << 8 - | sfp_diag_cal_const.bf.rx_pwr_0_3; - - cal_const->tx_bias_slope = sfp_diag_cal_const.bf.tx_i_slope_0 << 8 - | sfp_diag_cal_const.bf.tx_i_slope_1; - cal_const->tx_bias_offset = sfp_diag_cal_const.bf.tx_i_offset_0 << 8 - | sfp_diag_cal_const.bf.tx_i_offset_1; - - cal_const->tx_power_slope = sfp_diag_cal_const.bf.tx_pwr_slope_0 << 8 - | sfp_diag_cal_const.bf.tx_pwr_slope_1; - cal_const->tx_power_offset = sfp_diag_cal_const.bf.tx_pwr_offset_0 << 8 - | sfp_diag_cal_const.bf.tx_pwr_offset_1; - - cal_const->temp_slope = sfp_diag_cal_const.bf.t_slope_0 << 8 - | sfp_diag_cal_const.bf.t_slope_1; - cal_const->temp_offset = sfp_diag_cal_const.bf.t_offset_0 << 8 - | sfp_diag_cal_const.bf.t_offset_1; - - cal_const->vol_slope = sfp_diag_cal_const.bf.v_slope_0 << 8 - | sfp_diag_cal_const.bf.v_slope_1; - cal_const->vol_offset = sfp_diag_cal_const.bf.v_offset_0 << 8 - | sfp_diag_cal_const.bf.v_offset_1; - - return SW_OK; -} - -sw_error_t -adpt_sfp_link_length_get(a_uint32_t dev_id, a_uint32_t port_id, - fal_sfp_link_length_t *link_len) -{ - sw_error_t rv = SW_OK; - union sfp_link_len_u sfp_link_len; - - ADPT_DEV_ID_CHECK(dev_id); - ADPT_PORT_I2C_CAP_CHECK(dev_id, port_id); - ADPT_NULL_POINT_CHECK(link_len); - - memset(&sfp_link_len, 0, sizeof(sfp_link_len)); - - rv = sfp_link_len_get(dev_id, port_id, &sfp_link_len); - SW_RTN_ON_ERROR(rv); - - link_len->single_mode_length_km = sfp_link_len.bf.single_mode_km; - link_len->single_mode_length_100m = sfp_link_len.bf.single_mode_100m; - link_len->om2_mode_length_10m = sfp_link_len.bf.om2_mode_10m; - link_len->om1_mode_length_10m = sfp_link_len.bf.om1_mode_10m; - link_len->copper_mode_length_1m = sfp_link_len.bf.copper_mode_1m; - link_len->om3_mode_length_1m = sfp_link_len.bf.om3_mode_1m; - - return SW_OK; -} - -sw_error_t -adpt_sfp_diag_internal_threshold_get(a_uint32_t dev_id, a_uint32_t port_id, - fal_sfp_internal_threshold_t *threshold) -{ - sw_error_t rv = SW_OK; - union sfp_diag_threshold_u sfp_diag_threshold; - - ADPT_DEV_ID_CHECK(dev_id); - ADPT_PORT_I2C_CAP_CHECK(dev_id, port_id); - ADPT_NULL_POINT_CHECK(threshold); - - memset(&sfp_diag_threshold, 0, sizeof(sfp_diag_threshold)); - - rv = sfp_diag_threshold_get(dev_id, port_id, &sfp_diag_threshold); - SW_RTN_ON_ERROR(rv); - - threshold->temp_high_alarm = sfp_diag_threshold.bf.temp_high_alarm_0 << 8 - | sfp_diag_threshold.bf.temp_high_alarm_1; - threshold->temp_low_alarm = sfp_diag_threshold.bf.temp_low_alarm_0 << 8 - | sfp_diag_threshold.bf.temp_low_alarm_1; - threshold->temp_high_warning = sfp_diag_threshold.bf.temp_high_warning_0 << 8 - | sfp_diag_threshold.bf.temp_high_warning_1; - threshold->temp_low_warning = sfp_diag_threshold.bf.temp_low_warning_0 << 8 - | sfp_diag_threshold.bf.temp_low_warning_1; - threshold->vol_high_alarm = sfp_diag_threshold.bf.vol_high_alarm_0 << 8 - | sfp_diag_threshold.bf.vol_high_alarm_1; - threshold->vol_low_alarm = sfp_diag_threshold.bf.vol_low_alarm_0 << 8 - | sfp_diag_threshold.bf.vol_low_alarm_1; - threshold->vol_high_warning = sfp_diag_threshold.bf.vol_high_warning_0 << 8 - | sfp_diag_threshold.bf.vol_high_warning_1; - threshold->vol_low_warning = sfp_diag_threshold.bf.vol_low_warning_0 << 8 - | sfp_diag_threshold.bf.vol_low_warning_1; - threshold->bias_high_alarm = sfp_diag_threshold.bf.bias_high_alarm_0 << 8 - | sfp_diag_threshold.bf.bias_high_alarm_1; - threshold->bias_low_alarm = sfp_diag_threshold.bf.bias_low_alarm_0 << 8 - | sfp_diag_threshold.bf.bias_low_alarm_1; - threshold->bias_high_warning = sfp_diag_threshold.bf.bias_high_warning_0 << 8 - | sfp_diag_threshold.bf.bias_high_warning_1; - threshold->bias_low_warning = sfp_diag_threshold.bf.bias_low_warning_0 << 8 - | sfp_diag_threshold.bf.bias_low_warning_1; - threshold->tx_power_high_alarm = sfp_diag_threshold.bf.tx_pwr_high_alarm_0 << 8 - | sfp_diag_threshold.bf.tx_pwr_high_alarm_1; - threshold->tx_power_low_alarm = sfp_diag_threshold.bf.tx_pwr_low_alarm_0 << 8 - | sfp_diag_threshold.bf.tx_pwr_low_alarm_1; - threshold->tx_power_high_warning = sfp_diag_threshold.bf.tx_pwr_high_warning_0 << 8 - | sfp_diag_threshold.bf.tx_pwr_high_warning_1; - threshold->tx_power_low_warning = sfp_diag_threshold.bf.tx_pwr_low_warning_0 << 8 - | sfp_diag_threshold.bf.tx_pwr_low_warning_1; - threshold->rx_power_high_alarm = sfp_diag_threshold.bf.rx_pwr_high_alarm_0 << 8 - | sfp_diag_threshold.bf.rx_pwr_high_alarm_1; - threshold->rx_power_low_alarm = sfp_diag_threshold.bf.rx_pwr_low_alarm_0 << 8 - | sfp_diag_threshold.bf.rx_pwr_low_alarm_1; - threshold->rx_power_high_warning = sfp_diag_threshold.bf.rx_pwr_high_warning_0 << 8 - | sfp_diag_threshold.bf.rx_pwr_high_warning_1; - threshold->rx_power_low_warning = sfp_diag_threshold.bf.rx_pwr_low_warning_0 << 8 - | sfp_diag_threshold.bf.rx_pwr_low_warning_1; - - return SW_OK; -} - -sw_error_t -adpt_sfp_diag_realtime_get(a_uint32_t dev_id, a_uint32_t port_id, - fal_sfp_realtime_diag_t *real_diag) -{ - sw_error_t rv = SW_OK; - union sfp_diag_realtime_u sfp_diag_realtime; - - ADPT_DEV_ID_CHECK(dev_id); - ADPT_PORT_I2C_CAP_CHECK(dev_id, port_id); - ADPT_NULL_POINT_CHECK(real_diag); - - memset(&sfp_diag_realtime, 0, sizeof(sfp_diag_realtime)); - - rv = sfp_diag_realtime_get(dev_id, port_id, &sfp_diag_realtime); - SW_RTN_ON_ERROR(rv); - - real_diag->cur_temp = sfp_diag_realtime.bf.tmp_0 << 8 - | sfp_diag_realtime.bf.tmp_1; - real_diag->cur_vol = sfp_diag_realtime.bf.vcc_0 << 8 - | sfp_diag_realtime.bf.vcc_1; - real_diag->tx_cur_bias = sfp_diag_realtime.bf.tx_bias_0 << 8 - | sfp_diag_realtime.bf.tx_bias_1; - real_diag->tx_cur_power = sfp_diag_realtime.bf.tx_pwr_0 << 8 - | sfp_diag_realtime.bf.tx_pwr_1; - real_diag->rx_cur_power = sfp_diag_realtime.bf.rx_pwr_0 << 8 - | sfp_diag_realtime.bf.rx_pwr_1; - - return SW_OK; -} - -sw_error_t -adpt_sfp_laser_wavelength_get(a_uint32_t dev_id, a_uint32_t port_id, - fal_sfp_laser_wavelength_t *laser_wavelen) -{ - sw_error_t rv = SW_OK; - union sfp_laser_u sfp_laser; - - ADPT_DEV_ID_CHECK(dev_id); - ADPT_PORT_I2C_CAP_CHECK(dev_id, port_id); - ADPT_NULL_POINT_CHECK(laser_wavelen); - - memset(&sfp_laser, 0, sizeof(sfp_laser)); - - rv = sfp_laser_get(dev_id, port_id, &sfp_laser); - SW_RTN_ON_ERROR(rv); - - laser_wavelen->laser_wavelength = sfp_laser.bf.wavelength_0 << 8 - | sfp_laser.bf.wavelength_1; - - return SW_OK; -} - -sw_error_t -adpt_sfp_option_get(a_uint32_t dev_id, a_uint32_t port_id, - fal_sfp_option_t *option) -{ - sw_error_t rv = SW_OK; - union sfp_option_u sfp_option; - - ADPT_DEV_ID_CHECK(dev_id); - ADPT_PORT_I2C_CAP_CHECK(dev_id, port_id); - ADPT_NULL_POINT_CHECK(option); - - memset(&sfp_option, 0, sizeof(sfp_option)); - - rv = sfp_option_get(dev_id, port_id, &sfp_option); - SW_RTN_ON_ERROR(rv); - - option->linear_recv_output = sfp_option.bf.linear_recv_output; - option->pwr_level_declar = sfp_option.bf.pwr_level_declar; - option->cool_transc_declar = sfp_option.bf.cool_transc_declar; - option->loss_signal = sfp_option.bf.loss_signal; - option->loss_invert_signal = sfp_option.bf.loss_invert_signal; - option->tx_fault_signal = sfp_option.bf.tx_fault_signal; - option->tx_disable = sfp_option.bf.tx_disable; - option->rate_sel = sfp_option.bf.rate_sel; - - return SW_OK; -} - -sw_error_t -adpt_sfp_checkcode_get(a_uint32_t dev_id, a_uint32_t port_id, - fal_sfp_cc_type_t cc_type, a_uint8_t *ccode) -{ - sw_error_t rv = SW_OK; - union sfp_base_u sfp_base; - union sfp_ext_u sfp_ext; - union sfp_diag_dmi_u sfp_dmi; - - ADPT_DEV_ID_CHECK(dev_id); - ADPT_PORT_I2C_CAP_CHECK(dev_id, port_id); - ADPT_NULL_POINT_CHECK(ccode); - - memset(&sfp_base, 0, sizeof(sfp_base)); - memset(&sfp_ext, 0, sizeof(sfp_ext)); - memset(&sfp_dmi, 0, sizeof(sfp_dmi)); - - switch (cc_type) { - case FAL_SFP_CC_BASE: - rv = sfp_base_get(dev_id, port_id, &sfp_base); - SW_RTN_ON_ERROR(rv); - *ccode = sfp_base.bf.check_code; - break; - case FAL_SFP_CC_EXT: - rv = sfp_ext_get(dev_id, port_id, &sfp_ext); - SW_RTN_ON_ERROR(rv); - *ccode = sfp_ext.bf.check_code; - break; - case FAL_SFP_CC_DMI: - rv = sfp_diag_dmi_get(dev_id, - port_id, &sfp_dmi); - SW_RTN_ON_ERROR(rv); - *ccode = sfp_dmi.bf.check_code; - break; - default: - return SW_BAD_PARAM; - } - - return SW_OK; -} - -sw_error_t -adpt_sfp_diag_alarm_warning_flag_get(a_uint32_t dev_id, a_uint32_t port_id, - fal_sfp_alarm_warn_flag_t *alarm_warn_flag) -{ - sw_error_t rv = SW_OK; - union sfp_diag_flag_u sfp_diag_flag; - - ADPT_DEV_ID_CHECK(dev_id); - ADPT_PORT_I2C_CAP_CHECK(dev_id, port_id); - ADPT_NULL_POINT_CHECK(alarm_warn_flag); - - memset(&sfp_diag_flag, 0, sizeof(sfp_diag_flag)); - - rv = sfp_diag_flag_get(dev_id, port_id, &sfp_diag_flag); - SW_RTN_ON_ERROR(rv); - - alarm_warn_flag->tx_pwr_low_alarm = sfp_diag_flag.bf.tx_pwr_low_alarm; - alarm_warn_flag->tx_pwr_high_alarm = sfp_diag_flag.bf.tx_pwr_high_alarm; - alarm_warn_flag->tx_bias_low_alarm = sfp_diag_flag.bf.tx_bias_low_alarm; - alarm_warn_flag->tx_bias_high_alarm = sfp_diag_flag.bf.tx_bias_high_alarm; - alarm_warn_flag->vcc_low_alarm = sfp_diag_flag.bf.vcc_low_alarm; - alarm_warn_flag->vcc_high_alarm = sfp_diag_flag.bf.vcc_high_alarm; - alarm_warn_flag->tmp_low_alarm = sfp_diag_flag.bf.tmp_low_alarm; - alarm_warn_flag->tmp_high_alarm = sfp_diag_flag.bf.tmp_high_alarm; - alarm_warn_flag->rx_pwr_low_alarm = sfp_diag_flag.bf.rx_pwr_low_alarm; - alarm_warn_flag->rx_pwr_high_alarm = sfp_diag_flag.bf.rx_pwr_high_alarm; - - alarm_warn_flag->tx_pwr_low_warning = sfp_diag_flag.bf.tx_pwr_low_warning; - alarm_warn_flag->tx_pwr_high_warning = sfp_diag_flag.bf.tx_pwr_high_warning; - alarm_warn_flag->tx_bias_low_warning = sfp_diag_flag.bf.tx_bias_low_warning; - alarm_warn_flag->tx_bias_high_warning = sfp_diag_flag.bf.tx_bias_high_warning; - alarm_warn_flag->vcc_low_warning = sfp_diag_flag.bf.vcc_low_warning; - alarm_warn_flag->vcc_high_warning = sfp_diag_flag.bf.vcc_high_warning; - alarm_warn_flag->tmp_low_warning = sfp_diag_flag.bf.tmp_low_warning; - alarm_warn_flag->tmp_high_warning = sfp_diag_flag.bf.tmp_high_warning; - alarm_warn_flag->rx_pwr_low_warning = sfp_diag_flag.bf.rx_pwr_low_warning; - alarm_warn_flag->rx_pwr_high_warning = sfp_diag_flag.bf.rx_pwr_high_warning; - - return SW_OK; -} - -sw_error_t -adpt_sfp_device_type_get(a_uint32_t dev_id, a_uint32_t port_id, - fal_sfp_dev_type_t *sfp_id) -{ - sw_error_t rv = SW_OK; - union sfp_dev_type_u sfp_dev_type; - union sfp_dev_type_ext_u sfp_dev_type_ext; - union sfp_dev_connector_type_u sfp_dev_connector_type; - - ADPT_DEV_ID_CHECK(dev_id); - ADPT_PORT_I2C_CAP_CHECK(dev_id, port_id); - ADPT_NULL_POINT_CHECK(sfp_id); - - memset(&sfp_dev_type, 0, sizeof(sfp_dev_type)); - memset(&sfp_dev_type_ext, 0, sizeof(sfp_dev_type_ext)); - memset(&sfp_dev_connector_type, 0, sizeof(sfp_dev_connector_type)); - - rv = sfp_dev_type_get(dev_id, port_id, &sfp_dev_type); - SW_RTN_ON_ERROR(rv); - - rv = sfp_dev_type_ext_get(dev_id, port_id, &sfp_dev_type_ext); - SW_RTN_ON_ERROR(rv); - - rv = sfp_dev_connector_type_get(dev_id, port_id, &sfp_dev_connector_type); - SW_RTN_ON_ERROR(rv); - - sfp_id->identifier = sfp_dev_type.bf.id; - sfp_id->ext_indentifier = sfp_dev_type_ext.bf.id; - sfp_id->connector_type = sfp_dev_connector_type.bf.code; - - return SW_OK; -} - -sw_error_t -adpt_sfp_vendor_info_get(a_uint32_t dev_id, a_uint32_t port_id, - fal_sfp_vendor_info_t *vender_info) -{ - sw_error_t rv = SW_OK; - a_uint32_t index, i; - union sfp_vendor_u sfp_vendor; - union sfp_vendor_ext_u sfp_vendor_ext; - - ADPT_DEV_ID_CHECK(dev_id); - ADPT_PORT_I2C_CAP_CHECK(dev_id, port_id); - ADPT_NULL_POINT_CHECK(vender_info); - - memset(&sfp_vendor, 0, sizeof(sfp_vendor)); - memset(&sfp_vendor_ext, 0, sizeof(sfp_vendor_ext)); - - rv = sfp_vendor_get(dev_id, port_id, &sfp_vendor); - SW_RTN_ON_ERROR(rv); - - rv = sfp_vendor_ext_get(dev_id, port_id, &sfp_vendor_ext); - SW_RTN_ON_ERROR(rv); - - /* vendor basic info */ - for (index = 0, i = 0; i < sizeof(vender_info->vendor_name); index++) { - vender_info->vendor_name[i++] = *(sfp_vendor.val + index); - } - - /* skip Transceiver Code for electronic or optical compatibility */ - index++; - - for (i = 0; i < sizeof(vender_info->vendor_oui); index++) { - vender_info->vendor_oui[i++] = *(sfp_vendor.val + index); - } - - for (i = 0; i < sizeof(vender_info->vendor_pn); index++) { - vender_info->vendor_pn[i++] = *(sfp_vendor.val + index); - } - - for (i = 0; i < sizeof(vender_info->vendor_rev); index++) { - vender_info->vendor_rev[i++] = *(sfp_vendor.val + index); - } - - /* vendor extended info */ - for (index = 0, i = 0; i < sizeof(vender_info->vendor_sn); index++) { - vender_info->vendor_sn[i++] = *(sfp_vendor_ext.val + index); - } - - for (i = 0; i < sizeof(vender_info->vendor_date_code); index++) { - vender_info->vendor_date_code[i++] = *(sfp_vendor_ext.val + index); - } - - return SW_OK; -} - -sw_error_t -adpt_sfp_transceiver_code_get(a_uint32_t dev_id, a_uint32_t port_id, - fal_sfp_transc_code_t *transc_code) -{ - sw_error_t rv = SW_OK; - union sfp_transc_u sfp_transc; - - ADPT_DEV_ID_CHECK(dev_id); - ADPT_PORT_I2C_CAP_CHECK(dev_id, port_id); - ADPT_NULL_POINT_CHECK(transc_code); - - memset(&sfp_transc, 0, sizeof(sfp_transc)); - - rv = sfp_transc_get(dev_id, port_id, &sfp_transc); - SW_RTN_ON_ERROR(rv); - - transc_code->eth_10g_ccode = sfp_transc.bf.eth_10g_ccode; - transc_code->infiniband_ccode = sfp_transc.bf.infiniband_ccode; - transc_code->escon_ccode = sfp_transc.bf.escon_ccode; - transc_code->sonet_ccode = sfp_transc.bf.sonet_ccode_1 << 8 - | sfp_transc.bf.sonet_ccode_2; - transc_code->eth_ccode = sfp_transc.bf.eth_ccode; - transc_code->fibre_chan_link_length = sfp_transc.bf.fiber_ch_link_len; - transc_code->fibre_chan_tech = sfp_transc.bf.fiber_ch_tech_1 << 4 - | sfp_transc.bf.fiber_ch_tech_2; - transc_code->sfp_cable_tech = sfp_transc.bf.cable_tech; - transc_code->fibre_chan_trans_md = sfp_transc.bf.fiber_chan_tm_media; - transc_code->fibre_chan_speed = sfp_transc.bf.fiber_ch_speed; - - return SW_OK; -} - -sw_error_t -adpt_sfp_ctrl_rate_get(a_uint32_t dev_id, a_uint32_t port_id, - fal_sfp_rate_t *rate_limit) -{ - sw_error_t rv = SW_OK; - union sfp_rate_ctrl_u sfp_rate_ctrl; - - ADPT_DEV_ID_CHECK(dev_id); - ADPT_PORT_I2C_CAP_CHECK(dev_id, port_id); - ADPT_NULL_POINT_CHECK(rate_limit); - - memset(&sfp_rate_ctrl, 0, sizeof(sfp_rate_ctrl)); - - rv = sfp_rate_ctrl_get(dev_id, port_id, &sfp_rate_ctrl); - SW_RTN_ON_ERROR(rv); - - rate_limit->upper_rate_limit = sfp_rate_ctrl.bf.upper; - rate_limit->lower_rate_limit = sfp_rate_ctrl.bf.lower; - - return SW_OK; -} - -sw_error_t -adpt_sfp_enhanced_cfg_get(a_uint32_t dev_id, a_uint32_t port_id, - fal_sfp_enhanced_cfg_t *enhanced_feature) -{ - sw_error_t rv = SW_OK; - union sfp_enhanced_u sfp_enhanced; - - ADPT_DEV_ID_CHECK(dev_id); - ADPT_PORT_I2C_CAP_CHECK(dev_id, port_id); - ADPT_NULL_POINT_CHECK(enhanced_feature); - - memset(&sfp_enhanced, 0, sizeof(sfp_enhanced)); - - rv = sfp_enhanced_get(dev_id, port_id, &sfp_enhanced); - SW_RTN_ON_ERROR(rv); - - enhanced_feature->addr_mode = sfp_enhanced.bf.addr_mode; - enhanced_feature->rec_pwr_type = sfp_enhanced.bf.re_pwr_type; - enhanced_feature->external_cal = sfp_enhanced.bf.external_cal; - enhanced_feature->internal_cal = sfp_enhanced.bf.internal_cal; - enhanced_feature->diag_mon_flag = sfp_enhanced.bf.diag_mon_flag; - enhanced_feature->legacy_type = sfp_enhanced.bf.legacy_type; - - enhanced_feature->soft_rate_sel_op = sfp_enhanced.bf.soft_rate_sel_op; - enhanced_feature->app_sel_op = sfp_enhanced.bf.app_sel_op; - enhanced_feature->soft_rate_ctrl_op = sfp_enhanced.bf.soft_rate_ctrl_op; - enhanced_feature->rx_los_op = sfp_enhanced.bf.rx_los_op; - enhanced_feature->tx_fault_op = sfp_enhanced.bf.tx_fault_op; - enhanced_feature-> tx_disable_ctrl_op = sfp_enhanced.bf.tx_disable_ctrl_op; - enhanced_feature->alarm_warning_flag_op = sfp_enhanced.bf.alarm_warning_flag_op; - - enhanced_feature->compliance_feature = sfp_enhanced.bf.cmpl_feature; - - return SW_OK; -} - -sw_error_t -adpt_sfp_rate_encode_get(a_uint32_t dev_id, a_uint32_t port_id, - fal_sfp_rate_encode_t *encode) -{ - sw_error_t rv = SW_OK; - union sfp_encoding_u sfp_encoding; - union sfp_br_u sfp_br; - union sfp_rate_u sfp_rate; - - ADPT_DEV_ID_CHECK(dev_id); - ADPT_PORT_I2C_CAP_CHECK(dev_id, port_id); - ADPT_NULL_POINT_CHECK(encode); - - memset(&sfp_encoding, 0, sizeof(sfp_encoding)); - memset(&sfp_br, 0, sizeof(sfp_br)); - memset(&sfp_rate, 0, sizeof(sfp_rate)); - - rv = sfp_encoding_get(dev_id, port_id, &sfp_encoding); - SW_RTN_ON_ERROR(rv); - - rv = sfp_br_get(dev_id, port_id, &sfp_br); - SW_RTN_ON_ERROR(rv); - - rv = sfp_rate_get(dev_id, port_id, &sfp_rate); - SW_RTN_ON_ERROR(rv); - - encode->encode = sfp_encoding.bf.code; - encode->nominal_bit_rate = sfp_br.bf.bit; - encode->rate_id = sfp_rate.bf.id; - - return SW_OK; -} - -sw_error_t -adpt_sfp_eeprom_data_get(a_uint32_t dev_id, a_uint32_t port_id, fal_sfp_data_t *entry) -{ - sw_error_t rv = SW_OK; - - ADPT_DEV_ID_CHECK(dev_id); - ADPT_PORT_I2C_CAP_CHECK(dev_id, port_id); - ADPT_NULL_POINT_CHECK(entry); - - ADPT_RTN_ON_INVALID_DATA_OFFSET(entry->offset + entry->count); - - rv = sfp_eeprom_data_get(dev_id, port_id, entry->addr, - entry->offset, entry->data, entry->count); - SW_RTN_ON_ERROR(rv); - - return SW_OK; -} - -sw_error_t -adpt_sfp_eeprom_data_set(a_uint32_t dev_id, a_uint32_t port_id, fal_sfp_data_t *entry) -{ - sw_error_t rv = SW_OK; - - ADPT_DEV_ID_CHECK(dev_id); - ADPT_PORT_I2C_CAP_CHECK(dev_id, port_id); - ADPT_NULL_POINT_CHECK(entry); - - ADPT_RTN_ON_INVALID_DATA_OFFSET(entry->offset + entry->count); - - rv = sfp_eeprom_data_set(dev_id, port_id, entry->addr, - entry->offset, entry->data, entry->count); - SW_RTN_ON_ERROR(rv); - - /* retrieve the data */ - rv = sfp_eeprom_data_get(dev_id, port_id, entry->addr, - entry->offset, entry->data, entry->count); - SW_RTN_ON_ERROR(rv); - - return SW_OK; -} - -sw_error_t adpt_sfp_init(a_uint32_t dev_id) -{ - adpt_api_t *p_adpt_api = NULL; - - p_adpt_api = adpt_api_ptr_get(dev_id); - - if(p_adpt_api == NULL) - return SW_FAIL; - - p_adpt_api->adpt_sfp_diag_ctrl_status_get = adpt_sfp_diag_ctrl_status_get; - p_adpt_api->adpt_sfp_diag_extenal_calibration_const_get = - adpt_sfp_diag_extenal_calibration_const_get; - p_adpt_api->adpt_sfp_link_length_get = adpt_sfp_link_length_get; - p_adpt_api->adpt_sfp_diag_internal_threshold_get = - adpt_sfp_diag_internal_threshold_get; - p_adpt_api->adpt_sfp_diag_realtime_get = adpt_sfp_diag_realtime_get; - p_adpt_api->adpt_sfp_laser_wavelength_get = adpt_sfp_laser_wavelength_get; - p_adpt_api->adpt_sfp_option_get = adpt_sfp_option_get; - p_adpt_api->adpt_sfp_checkcode_get = adpt_sfp_checkcode_get; - p_adpt_api->adpt_sfp_diag_alarm_warning_flag_get = - adpt_sfp_diag_alarm_warning_flag_get; - p_adpt_api->adpt_sfp_device_type_get = adpt_sfp_device_type_get; - p_adpt_api->adpt_sfp_vendor_info_get = adpt_sfp_vendor_info_get; - p_adpt_api->adpt_sfp_transceiver_code_get = adpt_sfp_transceiver_code_get; - p_adpt_api->adpt_sfp_ctrl_rate_get = adpt_sfp_ctrl_rate_get; - p_adpt_api->adpt_sfp_enhanced_cfg_get = adpt_sfp_enhanced_cfg_get; - p_adpt_api->adpt_sfp_rate_encode_get = adpt_sfp_rate_encode_get; - p_adpt_api->adpt_sfp_eeprom_data_get = adpt_sfp_eeprom_data_get; - p_adpt_api->adpt_sfp_eeprom_data_set = adpt_sfp_eeprom_data_set; - - - return SW_OK; -} - -/** - * @} - */ diff --git a/feeds/ipq807x/qca-ssdk/src/src/api/Makefile b/feeds/ipq807x/qca-ssdk/src/src/api/Makefile deleted file mode 100755 index 25c788a90..000000000 --- a/feeds/ipq807x/qca-ssdk/src/src/api/Makefile +++ /dev/null @@ -1,12 +0,0 @@ -LOC_DIR=src/sal -LIB=API - -include $(PRJ_PATH)/make/config.mk - -SRC_LIST=$(wildcard *.c) - -include $(PRJ_PATH)/make/components.mk -include $(PRJ_PATH)/make/defs.mk -include $(PRJ_PATH)/make/target.mk - -all: dep obj \ No newline at end of file diff --git a/feeds/ipq807x/qca-ssdk/src/src/api/api_access.c b/feeds/ipq807x/qca-ssdk/src/src/api/api_access.c deleted file mode 100755 index 3fd2fc2e6..000000000 --- a/feeds/ipq807x/qca-ssdk/src/src/api/api_access.c +++ /dev/null @@ -1,177 +0,0 @@ -/* - * Copyright (c) 2012, 2017-2019, The Linux Foundation. All rights reserved. - * Permission to use, copy, modify, and/or distribute this software for - * any purpose with or without fee is hereby granted, provided that the - * above copyright notice and this permission notice appear in all copies. - * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES - * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR - * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES - * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN - * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT - * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. - */ -/*qca808x_start*/ -#include "sw.h" -#include "fal.h" -#include "hsl.h" -#include "hsl_dev.h" - -#include "sw_api.h" -#include "api_desc.h" -/*qca808x_end*/ -#if (((!defined(USER_MODE)) && defined(KERNEL_MODULE)) || (defined(USER_MODE) && (!defined(KERNEL_MODULE)))) -#ifdef HSL_STANDALONG -#if defined ATHENA -#include "athena_api.h" -#elif defined GARUDA -#include "garuda_api.h" -#elif defined SHIVA -#include "shiva_api.h" -#elif defined HORUS -#include "horus_api.h" -#elif defined ISIS -#include "isis_api.h" -#elif defined ISISC -#include "isisc_api.h" -#endif -#else -#include "ref_api.h" -#include "fal_api.h" -#endif -#elif (defined(USER_MODE)) -#if defined ATHENA -#include "athena_api.h" -#elif defined GARUDA -#include "garuda_api.h" -#elif defined SHIVA -#include "shiva_api.h" -#elif defined HORUS -#include "horus_api.h" -#elif defined ISIS -#include "isis_api.h" -#elif defined ISISC -#include "isisc_api.h" -#endif -#else -#include "ref_api.h" -/*qca808x_start*/ -#include "fal_api.h" -/*qca808x_end*/ -#endif -#include "ref_vsi.h" -#include "ref_vlan.h" - -/*qca808x_start*/ -static sw_api_func_t sw_api_func[] = { -/*qca808x_end*/ - SSDK_REF_API -/*qca808x_start*/ - SSDK_API }; -static sw_api_param_t sw_api_param[] = { -/*qca808x_end*/ - SSDK_REF_PARAM -/*qca808x_start*/ - SSDK_PARAM }; - -sw_api_func_t * -sw_api_func_find(a_uint32_t api_id) -{ - a_uint32_t i = 0; - static a_uint32_t save = 0; - - if(api_id == sw_api_func[save].api_id) - return &sw_api_func[save]; - - do - { - if (api_id == sw_api_func[i].api_id) - { - save = i; - return &sw_api_func[i]; - } - - } - while (++i < (sizeof(sw_api_func)/sizeof(sw_api_func[0]))); - - return NULL; -} - -sw_api_param_t * -sw_api_param_find(a_uint32_t api_id) -{ - a_uint32_t i = 0; - static a_uint32_t save = 0; - - if(api_id == sw_api_param[save].api_id) - return &sw_api_param[save]; - - do - { - if (api_id == sw_api_param[i].api_id) - { - save = i; - return &sw_api_param[i]; - } - } - while (++i < (sizeof(sw_api_param)/sizeof(sw_api_param[0]))); - - return NULL; -} - -a_uint32_t -sw_api_param_nums(a_uint32_t api_id) -{ - a_uint32_t i = 0; - sw_api_param_t *p = NULL; - static sw_api_param_t *savep = NULL; - static a_uint32_t save = 0; - - p = sw_api_param_find(api_id); - if (!p) - { - return 0; - } - - if (p == savep) - { - return save; - } - - savep = p; - while (api_id == p->api_id) - { - p++; - i++; - } - - /*error*/ - if(i >= sizeof(sw_api_param)/sizeof(sw_api_param[0])) - { - savep = NULL; - save = 0; - return 0; - } - save = i; - - return i; -} - -sw_error_t -sw_api_get(sw_api_t *sw_api) -{ - if(!sw_api) - return SW_FAIL; - - if ((sw_api->api_fp = sw_api_func_find(sw_api->api_id)) == NULL) - return SW_NOT_SUPPORTED; - - if ((sw_api->api_pp = sw_api_param_find(sw_api->api_id)) == NULL) - return SW_NOT_SUPPORTED; - - if((sw_api->api_nr = sw_api_param_nums(sw_api->api_id)) == 0) - return SW_NOT_SUPPORTED; - - return SW_OK; -} -/*qca808x_end*/ diff --git a/feeds/ipq807x/qca-ssdk/src/src/fal/Makefile b/feeds/ipq807x/qca-ssdk/src/src/fal/Makefile deleted file mode 100755 index 9e711e677..000000000 --- a/feeds/ipq807x/qca-ssdk/src/src/fal/Makefile +++ /dev/null @@ -1,140 +0,0 @@ -LOC_DIR=src/fal -LIB=FAL - -include $(PRJ_PATH)/make/config.mk - -SRC_LIST=fal_init.c fal_reg_access.c - -ifeq (TRUE, $(IN_ACL)) - SRC_LIST += fal_acl.c -endif - -ifeq (TRUE, $(IN_FDB)) - SRC_LIST += fal_fdb.c -endif - -ifeq (TRUE, $(IN_IGMP)) - SRC_LIST += fal_igmp.c -endif - -ifeq (TRUE, $(IN_LEAKY)) - SRC_LIST += fal_leaky.c -endif - -ifeq (TRUE, $(IN_LED)) - SRC_LIST += fal_led.c -endif - -ifeq (TRUE, $(IN_MIB)) - SRC_LIST += fal_mib.c -endif - -ifeq (TRUE, $(IN_MIRROR)) - SRC_LIST += fal_mirror.c -endif - -ifeq (TRUE, $(IN_MISC)) - SRC_LIST += fal_misc.c -endif - -ifeq (TRUE, $(IN_PORTCONTROL)) - SRC_LIST += fal_port_ctrl.c -endif - -ifeq (TRUE, $(IN_PORTVLAN)) - SRC_LIST += fal_portvlan.c -endif - -ifeq (TRUE, $(IN_QOS)) - SRC_LIST += fal_qos.c -endif - -ifeq (TRUE, $(IN_RATE)) - SRC_LIST += fal_rate.c -endif - -ifeq (TRUE, $(IN_STP)) - SRC_LIST += fal_stp.c -endif - -ifeq (TRUE, $(IN_VLAN)) - SRC_LIST += fal_vlan.c -endif - -ifeq (TRUE, $(IN_COSMAP)) - SRC_LIST += fal_cosmap.c -endif - -ifeq (TRUE, $(IN_IP)) - SRC_LIST += fal_ip.c -endif - -ifeq (TRUE, $(IN_NAT)) - SRC_LIST += fal_nat.c -endif - -ifeq (TRUE, $(IN_FLOW)) - SRC_LIST += fal_flow.c -endif - -ifeq (TRUE, $(IN_SEC)) - SRC_LIST += fal_sec.c -endif - -ifeq (TRUE, $(IN_TRUNK)) - SRC_LIST += fal_trunk.c -endif - -ifeq (TRUE, $(IN_VSI)) - SRC_LIST += fal_vsi.c -endif - -ifeq (TRUE, $(IN_INTERFACECONTROL)) - SRC_LIST += fal_interface_ctrl.c -endif - -ifeq (TRUE, $(IN_QM)) - SRC_LIST += fal_qm.c -endif - -ifeq (TRUE, $(IN_BM)) - SRC_LIST += fal_bm.c -endif - -ifeq (TRUE, $(IN_CTRLPKT)) - SRC_LIST += fal_ctrlpkt.c -endif - -ifeq (TRUE, $(IN_SERVCODE)) - SRC_LIST += fal_servcode.c -endif - -ifeq (TRUE, $(IN_RSS_HASH)) - SRC_LIST += fal_rss_hash.c -endif - -ifeq (TRUE, $(IN_PPPOE)) - SRC_LIST += fal_pppoe.c -endif - -ifeq (TRUE, $(IN_SHAPER)) - SRC_LIST += fal_shaper.c -endif - -ifeq (TRUE, $(IN_POLICER)) - SRC_LIST += fal_policer.c -endif - -ifeq (TRUE, $(IN_PTP)) - SRC_LIST += fal_ptp.c -endif - -ifeq (TRUE, $(IN_SFP)) - SRC_LIST += fal_sfp.c -endif - -include $(PRJ_PATH)/make/components.mk -include $(PRJ_PATH)/make/defs.mk -include $(PRJ_PATH)/make/target.mk - -all: dep obj diff --git a/feeds/ipq807x/qca-ssdk/src/src/fal/fal_acl.c b/feeds/ipq807x/qca-ssdk/src/src/fal/fal_acl.c deleted file mode 100755 index 22fbeb145..000000000 --- a/feeds/ipq807x/qca-ssdk/src/src/fal/fal_acl.c +++ /dev/null @@ -1,741 +0,0 @@ -/* - * Copyright (c) 2012, 2016-2017, The Linux Foundation. All rights reserved. - * Permission to use, copy, modify, and/or distribute this software for - * any purpose with or without fee is hereby granted, provided that the - * above copyright notice and this permission notice appear in all copies. - * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES - * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR - * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES - * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN - * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT - * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. - */ - - -/** - * @defgroup fal_acl FAL_ACL - * @{ - */ -#include "sw.h" -#include "fal_acl.h" -#include "hsl_api.h" -#include "adpt.h" - -static sw_error_t -_fal_acl_list_creat(a_uint32_t dev_id, a_uint32_t list_id, a_uint32_t prio) -{ - sw_error_t rv; - hsl_api_t *p_api; - adpt_api_t *p_adpt_api; - - if((p_adpt_api = adpt_api_ptr_get(dev_id)) != NULL) { - if (NULL == p_adpt_api->adpt_acl_list_creat) - return SW_NOT_SUPPORTED; - - rv = p_adpt_api->adpt_acl_list_creat(dev_id, list_id, prio); - return rv; - } - - SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id)); - - if (NULL == p_api->acl_list_creat) - return SW_NOT_SUPPORTED; - - rv = p_api->acl_list_creat(dev_id, list_id, prio); - return rv; -} - -static sw_error_t -_fal_acl_list_destroy(a_uint32_t dev_id, a_uint32_t list_id) -{ - sw_error_t rv; - hsl_api_t *p_api; - adpt_api_t *p_adpt_api; - - if((p_adpt_api = adpt_api_ptr_get(dev_id)) != NULL) { - if (NULL == p_adpt_api->adpt_acl_list_destroy) - return SW_NOT_SUPPORTED; - - rv = p_adpt_api->adpt_acl_list_destroy(dev_id, list_id); - return rv; - } - - SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id)); - - if (NULL == p_api->acl_list_destroy) - return SW_NOT_SUPPORTED; - - rv = p_api->acl_list_destroy(dev_id, list_id); - return rv; -} - -static sw_error_t -_fal_acl_rule_add(a_uint32_t dev_id, a_uint32_t list_id, a_uint32_t rule_id, - a_uint32_t rule_nr, fal_acl_rule_t * rule) -{ - sw_error_t rv; - hsl_api_t *p_api; - adpt_api_t *p_adpt_api; - - if((p_adpt_api = adpt_api_ptr_get(dev_id)) != NULL) { - if (NULL == p_adpt_api->adpt_acl_rule_add) - return SW_NOT_SUPPORTED; - rv = p_adpt_api->adpt_acl_rule_add(dev_id, list_id, rule_id, rule_nr, rule); - return rv; - } - - SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id)); - - if (NULL == p_api->acl_rule_add) - return SW_NOT_SUPPORTED; - - rv = p_api->acl_rule_add(dev_id, list_id, rule_id, rule_nr, rule); - return rv; -} - -static sw_error_t -_fal_acl_rule_delete(a_uint32_t dev_id, a_uint32_t list_id, a_uint32_t rule_id, - a_uint32_t rule_nr) -{ - sw_error_t rv; - hsl_api_t *p_api; - adpt_api_t *p_adpt_api; - - if((p_adpt_api = adpt_api_ptr_get(dev_id)) != NULL) { - if (NULL == p_adpt_api->adpt_acl_rule_delete) - return SW_NOT_SUPPORTED; - - rv = p_adpt_api->adpt_acl_rule_delete(dev_id, list_id, rule_id, rule_nr); - return rv; - } - - SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id)); - - if (NULL == p_api->acl_rule_delete) - return SW_NOT_SUPPORTED; - - rv = p_api->acl_rule_delete(dev_id, list_id, rule_id, rule_nr); - return rv; -} - -static sw_error_t -_fal_acl_rule_query(a_uint32_t dev_id, a_uint32_t list_id, a_uint32_t rule_id, - fal_acl_rule_t * rule) -{ - sw_error_t rv; - hsl_api_t *p_api; - adpt_api_t *p_adpt_api; - - if((p_adpt_api = adpt_api_ptr_get(dev_id)) != NULL) { - if (NULL == p_adpt_api->adpt_acl_rule_query) - return SW_NOT_SUPPORTED; - - rv = p_adpt_api->adpt_acl_rule_query(dev_id, list_id, rule_id, rule); - return rv; - } - - SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id)); - - if (NULL == p_api->acl_rule_query) - return SW_NOT_SUPPORTED; - - rv = p_api->acl_rule_query(dev_id, list_id, rule_id, rule); - return rv; -} - -static sw_error_t -_fal_acl_list_bind(a_uint32_t dev_id, a_uint32_t list_id, - fal_acl_direc_t direc, fal_acl_bind_obj_t obj_t, - a_uint32_t obj_idx) -{ - sw_error_t rv; - hsl_api_t *p_api; - adpt_api_t *p_adpt_api; - - if((p_adpt_api = adpt_api_ptr_get(dev_id)) != NULL) { - if (NULL == p_adpt_api->adpt_acl_list_bind) - return SW_NOT_SUPPORTED; - - rv = p_adpt_api->adpt_acl_list_bind(dev_id, list_id, direc, obj_t, obj_idx); - return rv; - } - - SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id)); - - if (NULL == p_api->acl_list_bind) - return SW_NOT_SUPPORTED; - - rv = p_api->acl_list_bind(dev_id, list_id, direc, obj_t, obj_idx); - return rv; -} - -static sw_error_t -_fal_acl_list_unbind(a_uint32_t dev_id, a_uint32_t list_id, - fal_acl_direc_t direc, fal_acl_bind_obj_t obj_t, - a_uint32_t obj_idx) -{ - sw_error_t rv; - hsl_api_t *p_api; - adpt_api_t *p_adpt_api; - - if((p_adpt_api = adpt_api_ptr_get(dev_id)) != NULL) { - if (NULL == p_adpt_api->adpt_acl_list_unbind) - return SW_NOT_SUPPORTED; - - rv = p_adpt_api->adpt_acl_list_unbind(dev_id, list_id, direc, obj_t, obj_idx); - return rv; - } - - SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id)); - - if (NULL == p_api->acl_list_unbind) - return SW_NOT_SUPPORTED; - - rv = p_api->acl_list_unbind(dev_id, list_id, direc, obj_t, obj_idx); - return rv; -} - -static sw_error_t -_fal_acl_status_set(a_uint32_t dev_id, a_bool_t enable) -{ - sw_error_t rv; - hsl_api_t *p_api; - - SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id)); - - if (NULL == p_api->acl_status_set) - return SW_NOT_SUPPORTED; - - rv = p_api->acl_status_set(dev_id, enable); - return rv; -} - -static sw_error_t -_fal_acl_status_get(a_uint32_t dev_id, a_bool_t * enable) -{ - sw_error_t rv; - hsl_api_t *p_api; - - SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id)); - - if (NULL == p_api->acl_status_get) - return SW_NOT_SUPPORTED; - - rv = p_api->acl_status_get(dev_id, enable); - return rv; -} - -static sw_error_t -_fal_acl_port_udf_profile_set(a_uint32_t dev_id, fal_port_t port_id, - fal_acl_udf_type_t udf_type, a_uint32_t offset, - a_uint32_t length) -{ - sw_error_t rv; - hsl_api_t *p_api; - - SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id)); - - if (NULL == p_api->acl_port_udf_profile_set) - return SW_NOT_SUPPORTED; - - rv = p_api->acl_port_udf_profile_set(dev_id, port_id, udf_type, offset, length); - return rv; -} - -static sw_error_t -_fal_acl_port_udf_profile_get(a_uint32_t dev_id, fal_port_t port_id, - fal_acl_udf_type_t udf_type, a_uint32_t * offset, - a_uint32_t * length) -{ - sw_error_t rv; - hsl_api_t *p_api; - - SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id)); - - if (NULL == p_api->acl_port_udf_profile_get) - return SW_NOT_SUPPORTED; - - rv = p_api->acl_port_udf_profile_get(dev_id, port_id, udf_type, offset, length); - return rv; -} - -static sw_error_t -_fal_acl_rule_active(a_uint32_t dev_id, a_uint32_t list_id, - a_uint32_t rule_id, a_uint32_t rule_nr) -{ - sw_error_t rv; - hsl_api_t *p_api; - - SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id)); - - if (NULL == p_api->acl_rule_active) - return SW_NOT_SUPPORTED; - - rv = p_api->acl_rule_active(dev_id, list_id, rule_id, rule_nr); - return rv; -} - -static sw_error_t -_fal_acl_rule_deactive(a_uint32_t dev_id, a_uint32_t list_id, - a_uint32_t rule_id, a_uint32_t rule_nr) -{ - sw_error_t rv; - hsl_api_t *p_api; - - SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id)); - - if (NULL == p_api->acl_rule_deactive) - return SW_NOT_SUPPORTED; - - rv = p_api->acl_rule_deactive(dev_id, list_id, rule_id, rule_nr); - return rv; -} - -static sw_error_t -_fal_acl_rule_src_filter_sts_set(a_uint32_t dev_id, - a_uint32_t rule_id, a_bool_t enable) -{ - sw_error_t rv; - hsl_api_t *p_api; - - SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id)); - - if (NULL == p_api->acl_rule_src_filter_sts_set) - return SW_NOT_SUPPORTED; - - rv = p_api->acl_rule_src_filter_sts_set(dev_id, rule_id, enable); - return rv; -} - -static sw_error_t -_fal_acl_rule_src_filter_sts_get(a_uint32_t dev_id, - a_uint32_t rule_id, a_bool_t* enable) -{ - sw_error_t rv; - hsl_api_t *p_api; - - SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id)); - - if (NULL == p_api->acl_rule_src_filter_sts_get) - return SW_NOT_SUPPORTED; - - rv = p_api->acl_rule_src_filter_sts_get(dev_id, rule_id, enable); - return rv; -} - -sw_error_t -_fal_acl_udf_profile_set(a_uint32_t dev_id, fal_acl_udf_pkt_type_t pkt_type,a_uint32_t udf_idx, fal_acl_udf_type_t udf_type, a_uint32_t offset) -{ - adpt_api_t *p_api; - sw_error_t rv = SW_OK; - - SW_RTN_ON_NULL(p_api = adpt_api_ptr_get(dev_id)); - - if (NULL == p_api->adpt_acl_udf_profile_set) - return SW_NOT_SUPPORTED; - - rv = p_api->adpt_acl_udf_profile_set(dev_id, pkt_type, udf_idx, udf_type, offset); - return rv; -} -sw_error_t -_fal_acl_udf_profile_get(a_uint32_t dev_id, fal_acl_udf_pkt_type_t pkt_type,a_uint32_t udf_idx, fal_acl_udf_type_t *udf_type, a_uint32_t *offset) -{ - adpt_api_t *p_api; - sw_error_t rv = SW_OK; - - SW_RTN_ON_NULL(p_api = adpt_api_ptr_get(dev_id)); - - if (NULL == p_api->adpt_acl_udf_profile_get) - return SW_NOT_SUPPORTED; - - rv = p_api->adpt_acl_udf_profile_get(dev_id, pkt_type, udf_idx, udf_type, offset); - return rv; -} -/*insert flag for inner fal, don't remove it*/ - -sw_error_t -fal_acl_list_dump(a_uint32_t dev_id) -{ - sw_error_t rv; - hsl_api_t *p_api; - - SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id)); - - if (NULL == p_api->acl_list_dump) - return SW_NOT_SUPPORTED; - - rv = p_api->acl_list_dump(dev_id); - return rv; -} - -sw_error_t -fal_acl_rule_dump(a_uint32_t dev_id) -{ - sw_error_t rv; - hsl_api_t *p_api; - adpt_api_t *p_adpt_api; - - if((p_adpt_api = adpt_api_ptr_get(dev_id)) != NULL) { - if (NULL == p_adpt_api->adpt_acl_rule_dump) - return SW_NOT_SUPPORTED; - - rv = p_adpt_api->adpt_acl_rule_dump(dev_id); - return rv; - } - - SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id)); - - if (NULL == p_api->acl_rule_dump) - return SW_NOT_SUPPORTED; - - rv = p_api->acl_rule_dump(dev_id); - return rv; -} - -/** - * @brief Creat an acl list - * @details Comments: - * If the priority of a list is more small then the priority is more high, - * that means the list could be first matched. - * @param[in] dev_id device id - * @param[in] list_id acl list id - * @param[in] list_pri acl list priority - * @return SW_OK or error code - */ -sw_error_t -fal_acl_list_creat(a_uint32_t dev_id, a_uint32_t list_id, a_uint32_t prio) -{ - sw_error_t rv; - - FAL_API_LOCK; - rv = _fal_acl_list_creat(dev_id, list_id, prio); - FAL_API_UNLOCK; - return rv; -} - -/** - * @brief Destroy an acl list - * @param[in] dev_id device id - * @param[in] list_id acl list id - * @return SW_OK or error code - */ -sw_error_t -fal_acl_list_destroy(a_uint32_t dev_id, a_uint32_t list_id) -{ - sw_error_t rv; - - FAL_API_LOCK; - rv = _fal_acl_list_destroy(dev_id, list_id); - FAL_API_UNLOCK; - return rv; -} - -/** - * @brief Add one rule or more rules to an existing acl list - * @param[in] dev_id device id - * @param[in] list_id acl list id - * @param[in] rule_id first rule id of this adding operation in list - * @param[in] rule_nr rule number of this adding operation - * @param[in] rule rules content of this adding operation - * @return SW_OK or error code - */ -sw_error_t -fal_acl_rule_add(a_uint32_t dev_id, a_uint32_t list_id, a_uint32_t rule_id, - a_uint32_t rule_nr, fal_acl_rule_t * rule) -{ - sw_error_t rv; - - FAL_API_LOCK; - rv = _fal_acl_rule_add(dev_id, list_id, rule_id, rule_nr, rule); - FAL_API_UNLOCK; - return rv; -} - -/** - * @brief Delete one rule or more rules from an existing acl list - * @param[in] dev_id device id - * @param[in] list_id acl list id - * @param[in] rule_id first rule id of this deleteing operation in list - * @param[in] rule_nr rule number of this deleteing operation - * @return SW_OK or error code - */ -sw_error_t -fal_acl_rule_delete(a_uint32_t dev_id, a_uint32_t list_id, a_uint32_t rule_id, - a_uint32_t rule_nr) -{ - sw_error_t rv; - - FAL_API_LOCK; - rv = _fal_acl_rule_delete(dev_id, list_id, rule_id, rule_nr); - FAL_API_UNLOCK; - return rv; -} - -/** - * @brief Query one particular rule in a particular acl list - * @param[in] dev_id device id - * @param[in] list_id acl list id - * @param[in] rule_id first rule id of this deleteing operation in list - * @param[out] rule rule content of this operation - * @return SW_OK or error code - */ -sw_error_t -fal_acl_rule_query(a_uint32_t dev_id, a_uint32_t list_id, a_uint32_t rule_id, - fal_acl_rule_t * rule) -{ - sw_error_t rv; - - FAL_API_LOCK; - rv = _fal_acl_rule_query(dev_id, list_id, rule_id, rule); - FAL_API_UNLOCK; - return rv; -} - -/** - * @brief Bind an acl list to a particular object - * @details Comments: - * If obj_t equals FAL_ACL_BIND_PORT then obj_idx means port id - * @param[in] dev_id device id - * @param[in] list_id acl list id - * @param[in] direc direction of this binding operation - * @param[in] obj_t object type of this binding operation - * @param[in] obj_idx object index of this binding operation - * @return SW_OK or error code - */ -sw_error_t -fal_acl_list_bind(a_uint32_t dev_id, a_uint32_t list_id, - fal_acl_direc_t direc, fal_acl_bind_obj_t obj_t, - a_uint32_t obj_idx) -{ - sw_error_t rv; - - FAL_API_LOCK; - rv = _fal_acl_list_bind(dev_id, list_id, direc, obj_t, obj_idx); - FAL_API_UNLOCK; - return rv; -} - -/** - * @brief Unbind an acl list from a particular object - * @details Comments: - * If obj_t equals FAL_ACL_BIND_PORT then obj_idx means port id - * @param[in] dev_id device id - * @param[in] list_id acl list id - * @param[in] direc direction of this unbinding operation - * @param[in] obj_t object type of this unbinding operation - * @param[in] obj_idx object index of this unbinding operation - * @return SW_OK or error code - */ -sw_error_t -fal_acl_list_unbind(a_uint32_t dev_id, a_uint32_t list_id, - fal_acl_direc_t direc, fal_acl_bind_obj_t obj_t, - a_uint32_t obj_idx) -{ - sw_error_t rv; - - FAL_API_LOCK; - rv = _fal_acl_list_unbind(dev_id, list_id, direc, obj_t, obj_idx); - FAL_API_UNLOCK; - return rv; -} - -/** - * @brief Set working status of ACL engine on a particular device - * @param[in] dev_id device id - * @param[in] enable A_TRUE or A_FALSE - * @return SW_OK or error code - */ -sw_error_t -fal_acl_status_set(a_uint32_t dev_id, a_bool_t enable) -{ - sw_error_t rv; - - FAL_API_LOCK; - rv = _fal_acl_status_set(dev_id, enable); - FAL_API_UNLOCK; - return rv; -} - -/** - * @brief Get working status of ACL engine on a particular device - * @param[in] dev_id device id - * @param[out] enable A_TRUE or A_FALSE - * @return SW_OK or error code - */ -sw_error_t -fal_acl_status_get(a_uint32_t dev_id, a_bool_t * enable) -{ - sw_error_t rv; - - FAL_API_LOCK; - rv = _fal_acl_status_get(dev_id, enable); - FAL_API_UNLOCK; - return rv; -} - -/** - * @brief Set user define fields profile on a particular port - * @param[in] dev_id device id - * @param[in] port_id port id - * @param[in] udf_type udf type - * @param[in] offset udf offset - * @param[in] length udf length - * @return SW_OK or error code - */ -sw_error_t -fal_acl_port_udf_profile_set(a_uint32_t dev_id, fal_port_t port_id, - fal_acl_udf_type_t udf_type, a_uint32_t offset, - a_uint32_t length) -{ - sw_error_t rv; - - FAL_API_LOCK; - rv = _fal_acl_port_udf_profile_set(dev_id, port_id, udf_type, offset, - length); - FAL_API_UNLOCK; - return rv; -} - -/** - * @brief Get user define fields profile on a particular port - * @param[in] dev_id device id - * @param[in] port_id port id - * @param[in] udf_type udf type - * @param[out] offset udf offset - * @param[out] length udf length - * @return SW_OK or error code - */ -sw_error_t -fal_acl_port_udf_profile_get(a_uint32_t dev_id, fal_port_t port_id, - fal_acl_udf_type_t udf_type, a_uint32_t * offset, - a_uint32_t * length) -{ - sw_error_t rv; - - FAL_API_LOCK; - rv = _fal_acl_port_udf_profile_get(dev_id, port_id, udf_type, offset, - length); - FAL_API_UNLOCK; - return rv; -} - -/** - * @brief Active one or more rules in an existing acl list - * @param[in] dev_id device id - * @param[in] list_id acl list id - * @param[in] rule_id first rule id of this deactive operation in list - * @param[in] rule_nr rule number of this deactive operation - * @return SW_OK or error code - */ -sw_error_t -fal_acl_rule_active(a_uint32_t dev_id, a_uint32_t list_id, - a_uint32_t rule_id, a_uint32_t rule_nr) -{ - sw_error_t rv; - - FAL_API_LOCK; - rv = _fal_acl_rule_active(dev_id, list_id, rule_id, rule_nr); - FAL_API_UNLOCK; - return rv; -} - -/** - * @brief Deactive one or more rules in an existing acl list - * @param[in] dev_id device id - * @param[in] list_id acl list id - * @param[in] rule_id first rule id of this deactive operation in list - * @param[in] rule_nr rule number of this deactive operation - * @return SW_OK or error code - */ -sw_error_t -fal_acl_rule_deactive(a_uint32_t dev_id, a_uint32_t list_id, - a_uint32_t rule_id, a_uint32_t rule_nr) -{ - sw_error_t rv; - - FAL_API_LOCK; - rv = _fal_acl_rule_deactive(dev_id, list_id, rule_id, rule_nr); - FAL_API_UNLOCK; - return rv; -} - -/** - * @brief set status of one rule source filter - * @param[in] dev_id device id - * @param[in] rule_id first rule id of this deactive operation in list - * @param[in] enable A_TRUE or A_FALSE - * @return SW_OK or error code - */ -sw_error_t -fal_acl_rule_src_filter_sts_set(a_uint32_t dev_id, - a_uint32_t rule_id, a_bool_t enable) -{ - sw_error_t rv; - - FAL_API_LOCK; - rv = _fal_acl_rule_src_filter_sts_set(dev_id, rule_id, enable); - FAL_API_UNLOCK; - return rv; -} - -/** - * @brief get status of one rule source filter - * @param[in] dev_id device id - * @param[in] rule_id first rule id of this deactive operation in list - * @param[out] enable A_TRUE or A_FALSE - * @return SW_OK or error code - */ -sw_error_t -fal_acl_rule_src_filter_sts_get(a_uint32_t dev_id, - a_uint32_t rule_id, a_bool_t* enable) -{ - sw_error_t rv; - - FAL_API_LOCK; - rv = _fal_acl_rule_src_filter_sts_get(dev_id, rule_id, enable); - FAL_API_UNLOCK; - return rv; -} - -sw_error_t -fal_acl_udf_profile_set(a_uint32_t dev_id, fal_acl_udf_pkt_type_t pkt_type,a_uint32_t udf_idx, fal_acl_udf_type_t udf_type, a_uint32_t offset) -{ - sw_error_t rv = SW_OK; - - FAL_API_LOCK; - rv = _fal_acl_udf_profile_set(dev_id, pkt_type, udf_idx, udf_type, offset); - FAL_API_UNLOCK; - return rv; -} -sw_error_t -fal_acl_udf_profile_get(a_uint32_t dev_id, fal_acl_udf_pkt_type_t pkt_type,a_uint32_t udf_idx, fal_acl_udf_type_t *udf_type, a_uint32_t *offset) -{ - sw_error_t rv = SW_OK; - - FAL_API_LOCK; - rv = _fal_acl_udf_profile_get(dev_id, pkt_type, udf_idx, udf_type, offset); - FAL_API_UNLOCK; - return rv; -} - -/*insert flag for outter fal, don't remove it*/ - -EXPORT_SYMBOL(fal_acl_list_creat); -EXPORT_SYMBOL(fal_acl_list_destroy); -EXPORT_SYMBOL(fal_acl_rule_add); -EXPORT_SYMBOL(fal_acl_rule_delete); -EXPORT_SYMBOL(fal_acl_rule_query); -EXPORT_SYMBOL(fal_acl_list_bind); -EXPORT_SYMBOL(fal_acl_list_unbind); -EXPORT_SYMBOL(fal_acl_status_set); -EXPORT_SYMBOL(fal_acl_status_get); -EXPORT_SYMBOL(fal_acl_port_udf_profile_set); -EXPORT_SYMBOL(fal_acl_port_udf_profile_get); -EXPORT_SYMBOL(fal_acl_rule_active); -EXPORT_SYMBOL(fal_acl_rule_deactive); -EXPORT_SYMBOL(fal_acl_rule_src_filter_sts_set); -EXPORT_SYMBOL(fal_acl_rule_src_filter_sts_get); -EXPORT_SYMBOL(fal_acl_udf_profile_set); -EXPORT_SYMBOL(fal_acl_udf_profile_get); - diff --git a/feeds/ipq807x/qca-ssdk/src/src/fal/fal_bm.c b/feeds/ipq807x/qca-ssdk/src/src/fal/fal_bm.c deleted file mode 100755 index dc2373477..000000000 --- a/feeds/ipq807x/qca-ssdk/src/src/fal/fal_bm.c +++ /dev/null @@ -1,422 +0,0 @@ -/* - * Copyright (c) 2016-2017, The Linux Foundation. All rights reserved. - * Permission to use, copy, modify, and/or distribute this software for - * any purpose with or without fee is hereby granted, provided that the - * above copyright notice and this permission notice appear in all copies. - * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES - * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR - * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES - * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN - * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT - * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. - */ - - -/** - * @defgroup fal_qm FAL_BM - * @{ - */ -#include "sw.h" -#include "fal_bm.h" -#include "hsl_api.h" -#include "adpt.h" - -#ifndef IN_BM_MINI -sw_error_t -_fal_port_bufgroup_map_get(a_uint32_t dev_id, fal_port_t port, - a_uint8_t *group) -{ - adpt_api_t *p_api; - sw_error_t rv = SW_OK; - - SW_RTN_ON_NULL(p_api = adpt_api_ptr_get(dev_id)); - - if (NULL == p_api->adpt_port_bufgroup_map_get) - return SW_NOT_SUPPORTED; - - rv = p_api->adpt_port_bufgroup_map_get(dev_id, port, group); - return rv; -} -sw_error_t -_fal_bm_port_reserved_buffer_get(a_uint32_t dev_id, fal_port_t port, - a_uint16_t *prealloc_buff, a_uint16_t *react_buff) -{ - adpt_api_t *p_api; - sw_error_t rv = SW_OK; - - SW_RTN_ON_NULL(p_api = adpt_api_ptr_get(dev_id)); - - if (NULL == p_api->adpt_bm_port_reserved_buffer_get) - return SW_NOT_SUPPORTED; - - rv = p_api->adpt_bm_port_reserved_buffer_get(dev_id, port, prealloc_buff, react_buff); - return rv; -} -sw_error_t -_fal_bm_bufgroup_buffer_get(a_uint32_t dev_id, a_uint8_t group, - a_uint16_t *buff_num) -{ - adpt_api_t *p_api; - sw_error_t rv = SW_OK; - - SW_RTN_ON_NULL(p_api = adpt_api_ptr_get(dev_id)); - - if (NULL == p_api->adpt_bm_bufgroup_buffer_get) - return SW_NOT_SUPPORTED; - - rv = p_api->adpt_bm_bufgroup_buffer_get(dev_id, group, buff_num); - return rv; -} -sw_error_t -_fal_bm_port_dynamic_thresh_get(a_uint32_t dev_id, fal_port_t port, - fal_bm_dynamic_cfg_t *cfg) -{ - adpt_api_t *p_api; - sw_error_t rv = SW_OK; - - SW_RTN_ON_NULL(p_api = adpt_api_ptr_get(dev_id)); - - if (NULL == p_api->adpt_bm_port_dynamic_thresh_get) - return SW_NOT_SUPPORTED; - - rv = p_api->adpt_bm_port_dynamic_thresh_get(dev_id, port, cfg); - return rv; -} -sw_error_t -_fal_port_bm_ctrl_get(a_uint32_t dev_id, fal_port_t port, a_bool_t *enable) -{ - adpt_api_t *p_api; - sw_error_t rv = SW_OK; - - SW_RTN_ON_NULL(p_api = adpt_api_ptr_get(dev_id)); - - if (NULL == p_api->adpt_port_bm_ctrl_get) - return SW_NOT_SUPPORTED; - - rv = p_api->adpt_port_bm_ctrl_get(dev_id, port, enable); - return rv; -} -#endif -sw_error_t -_fal_bm_bufgroup_buffer_set(a_uint32_t dev_id, a_uint8_t group, - a_uint16_t buff_num) -{ - adpt_api_t *p_api; - sw_error_t rv = SW_OK; - - SW_RTN_ON_NULL(p_api = adpt_api_ptr_get(dev_id)); - - if (NULL == p_api->adpt_bm_bufgroup_buffer_set) - return SW_NOT_SUPPORTED; - - rv = p_api->adpt_bm_bufgroup_buffer_set(dev_id, group, buff_num); - return rv; -} -sw_error_t -_fal_port_bufgroup_map_set(a_uint32_t dev_id, fal_port_t port, - a_uint8_t group) -{ - adpt_api_t *p_api; - sw_error_t rv = SW_OK; - - SW_RTN_ON_NULL(p_api = adpt_api_ptr_get(dev_id)); - - if (NULL == p_api->adpt_port_bufgroup_map_set) - return SW_NOT_SUPPORTED; - - rv = p_api->adpt_port_bufgroup_map_set(dev_id, port, group); - return rv; -} -#ifndef IN_BM_MINI -sw_error_t -_fal_bm_port_static_thresh_get(a_uint32_t dev_id, fal_port_t port, - fal_bm_static_cfg_t *cfg) -{ - adpt_api_t *p_api; - hsl_api_t *p_hsl_api; - sw_error_t rv = SW_OK; - - if((p_api = adpt_api_ptr_get(dev_id)) != NULL) { - if (NULL == p_api->adpt_bm_port_static_thresh_get) - return SW_NOT_SUPPORTED; - - rv = p_api->adpt_bm_port_static_thresh_get(dev_id, port, cfg); - return rv; - } - - SW_RTN_ON_NULL(p_hsl_api = hsl_api_ptr_get(dev_id)); - - if (NULL == p_hsl_api->port_static_thresh_get) - return SW_NOT_SUPPORTED; - - rv = p_hsl_api->port_static_thresh_get(dev_id, port, cfg); - return rv; -} -#endif -sw_error_t -_fal_bm_port_reserved_buffer_set(a_uint32_t dev_id, fal_port_t port, - a_uint16_t prealloc_buff, a_uint16_t react_buff) -{ - adpt_api_t *p_api; - sw_error_t rv = SW_OK; - - SW_RTN_ON_NULL(p_api = adpt_api_ptr_get(dev_id)); - - if (NULL == p_api->adpt_bm_port_reserved_buffer_set) - return SW_NOT_SUPPORTED; - - rv = p_api->adpt_bm_port_reserved_buffer_set(dev_id, port, prealloc_buff, react_buff); - return rv; -} -sw_error_t -_fal_bm_port_static_thresh_set(a_uint32_t dev_id, fal_port_t port, - fal_bm_static_cfg_t *cfg) -{ - adpt_api_t *p_api; - hsl_api_t *p_hsl_api; - sw_error_t rv = SW_OK; - - if((p_api = adpt_api_ptr_get(dev_id)) != NULL) { - if (NULL == p_api->adpt_bm_port_static_thresh_set) - return SW_NOT_SUPPORTED; - - rv = p_api->adpt_bm_port_static_thresh_set(dev_id, port, cfg); - return rv; - } - - SW_RTN_ON_NULL(p_hsl_api = hsl_api_ptr_get(dev_id)); - - if (NULL == p_hsl_api->port_static_thresh_set) - return SW_NOT_SUPPORTED; - - rv = p_hsl_api->port_static_thresh_set(dev_id, port, cfg); - return rv; -} -sw_error_t -_fal_bm_port_dynamic_thresh_set(a_uint32_t dev_id, fal_port_t port, - fal_bm_dynamic_cfg_t *cfg) -{ - adpt_api_t *p_api; - sw_error_t rv = SW_OK; - - SW_RTN_ON_NULL(p_api = adpt_api_ptr_get(dev_id)); - - if (NULL == p_api->adpt_bm_port_dynamic_thresh_set) - return SW_NOT_SUPPORTED; - - rv = p_api->adpt_bm_port_dynamic_thresh_set(dev_id, port, cfg); - return rv; -} -sw_error_t -_fal_port_bm_ctrl_set(a_uint32_t dev_id, fal_port_t port, a_bool_t enable) -{ - adpt_api_t *p_api; - sw_error_t rv = SW_OK; - - SW_RTN_ON_NULL(p_api = adpt_api_ptr_get(dev_id)); - - if (NULL == p_api->adpt_port_bm_ctrl_set) - return SW_NOT_SUPPORTED; - - rv = p_api->adpt_port_bm_ctrl_set(dev_id, port, enable); - return rv; -} - -#ifndef IN_BM_MINI -sw_error_t -_fal_bm_port_counter_get(a_uint32_t dev_id, fal_port_t port, - fal_bm_port_counter_t *counter) -{ - adpt_api_t *p_api; - sw_error_t rv = SW_OK; - - SW_RTN_ON_NULL(p_api = adpt_api_ptr_get(dev_id)); - - if (NULL == p_api->adpt_bm_port_counter_get) - return SW_NOT_SUPPORTED; - - rv = p_api->adpt_bm_port_counter_get(dev_id, port, counter); - return rv; -} -/*insert flag for inner fal, don't remove it*/ - -sw_error_t -fal_port_bufgroup_map_get(a_uint32_t dev_id, fal_port_t port, - a_uint8_t *group) -{ - sw_error_t rv = SW_OK; - - FAL_API_LOCK; - rv = _fal_port_bufgroup_map_get(dev_id, port, group); - FAL_API_UNLOCK; - return rv; -} -sw_error_t -fal_bm_port_reserved_buffer_get(a_uint32_t dev_id, fal_port_t port, - a_uint16_t *prealloc_buff, a_uint16_t *react_buff) -{ - sw_error_t rv = SW_OK; - - FAL_API_LOCK; - rv = _fal_bm_port_reserved_buffer_get(dev_id, port, prealloc_buff, react_buff); - FAL_API_UNLOCK; - return rv; -} -sw_error_t -fal_bm_bufgroup_buffer_get(a_uint32_t dev_id, a_uint8_t group, - a_uint16_t *buff_num) -{ - sw_error_t rv = SW_OK; - - FAL_API_LOCK; - rv = _fal_bm_bufgroup_buffer_get(dev_id, group, buff_num); - FAL_API_UNLOCK; - return rv; -} -sw_error_t -fal_bm_port_dynamic_thresh_get(a_uint32_t dev_id, fal_port_t port, - fal_bm_dynamic_cfg_t *cfg) -{ - sw_error_t rv = SW_OK; - - FAL_API_LOCK; - rv = _fal_bm_port_dynamic_thresh_get(dev_id, port, cfg); - FAL_API_UNLOCK; - return rv; -} -sw_error_t -fal_port_bm_ctrl_get(a_uint32_t dev_id, fal_port_t port, a_bool_t *enable) -{ - sw_error_t rv = SW_OK; - - FAL_API_LOCK; - rv = _fal_port_bm_ctrl_get(dev_id, port, enable); - FAL_API_UNLOCK; - return rv; -} -#endif - -sw_error_t -fal_bm_bufgroup_buffer_set(a_uint32_t dev_id, a_uint8_t group, - a_uint16_t buff_num) -{ - sw_error_t rv = SW_OK; - - FAL_API_LOCK; - rv = _fal_bm_bufgroup_buffer_set(dev_id, group, buff_num); - FAL_API_UNLOCK; - return rv; -} - -sw_error_t -fal_port_bufgroup_map_set(a_uint32_t dev_id, fal_port_t port, - a_uint8_t group) -{ - sw_error_t rv = SW_OK; - - FAL_API_LOCK; - rv = _fal_port_bufgroup_map_set(dev_id, port, group); - FAL_API_UNLOCK; - return rv; -} -#ifndef IN_BM_MINI -sw_error_t -fal_bm_port_static_thresh_get(a_uint32_t dev_id, fal_port_t port, - fal_bm_static_cfg_t *cfg) -{ - sw_error_t rv = SW_OK; - - FAL_API_LOCK; - rv = _fal_bm_port_static_thresh_get(dev_id, port, cfg); - FAL_API_UNLOCK; - return rv; -} -#endif -sw_error_t -fal_bm_port_reserved_buffer_set(a_uint32_t dev_id, fal_port_t port, - a_uint16_t prealloc_buff, a_uint16_t react_buff) -{ - sw_error_t rv = SW_OK; - - FAL_API_LOCK; - rv = _fal_bm_port_reserved_buffer_set(dev_id, port, prealloc_buff, react_buff); - FAL_API_UNLOCK; - return rv; -} -sw_error_t -fal_bm_port_static_thresh_set(a_uint32_t dev_id, fal_port_t port, - fal_bm_static_cfg_t *cfg) -{ - sw_error_t rv = SW_OK; - - FAL_API_LOCK; - rv = _fal_bm_port_static_thresh_set(dev_id, port, cfg); - FAL_API_UNLOCK; - return rv; -} -sw_error_t -fal_bm_port_dynamic_thresh_set(a_uint32_t dev_id, fal_port_t port, - fal_bm_dynamic_cfg_t *cfg) -{ - sw_error_t rv = SW_OK; - - FAL_API_LOCK; - rv = _fal_bm_port_dynamic_thresh_set(dev_id, port, cfg); - FAL_API_UNLOCK; - return rv; -} -sw_error_t -fal_port_bm_ctrl_set(a_uint32_t dev_id, fal_port_t port, a_bool_t enable) -{ - sw_error_t rv = SW_OK; - - FAL_API_LOCK; - rv = _fal_port_bm_ctrl_set(dev_id, port, enable); - FAL_API_UNLOCK; - return rv; -} - -#ifndef IN_BM_MINI -sw_error_t -fal_bm_port_counter_get(a_uint32_t dev_id, fal_port_t port, - fal_bm_port_counter_t *counter) -{ - sw_error_t rv = SW_OK; - - FAL_API_LOCK; - rv = _fal_bm_port_counter_get(dev_id, port, counter); - FAL_API_UNLOCK; - return rv; -} -#endif - -EXPORT_SYMBOL(fal_port_bm_ctrl_set); - -EXPORT_SYMBOL(fal_port_bufgroup_map_set); - -EXPORT_SYMBOL(fal_bm_bufgroup_buffer_set); - -EXPORT_SYMBOL(fal_bm_port_reserved_buffer_set); - -EXPORT_SYMBOL(fal_bm_port_dynamic_thresh_set); - -#ifndef IN_BM_MINI -EXPORT_SYMBOL(fal_port_bm_ctrl_get); - -EXPORT_SYMBOL(fal_port_bufgroup_map_get); - -EXPORT_SYMBOL(fal_bm_bufgroup_buffer_get); - -EXPORT_SYMBOL(fal_bm_port_reserved_buffer_get); - -EXPORT_SYMBOL(fal_bm_port_static_thresh_set); - -EXPORT_SYMBOL(fal_bm_port_static_thresh_get); - -EXPORT_SYMBOL(fal_bm_port_dynamic_thresh_get); - -EXPORT_SYMBOL(fal_bm_port_counter_get); -#endif - -/*insert flag for outter fal, don't remove it*/ diff --git a/feeds/ipq807x/qca-ssdk/src/src/fal/fal_cosmap.c b/feeds/ipq807x/qca-ssdk/src/src/fal/fal_cosmap.c deleted file mode 100755 index 4d7d84ffa..000000000 --- a/feeds/ipq807x/qca-ssdk/src/src/fal/fal_cosmap.c +++ /dev/null @@ -1,783 +0,0 @@ -/* - * Copyright (c) 2012, The Linux Foundation. All rights reserved. - * Permission to use, copy, modify, and/or distribute this software for - * any purpose with or without fee is hereby granted, provided that the - * above copyright notice and this permission notice appear in all copies. - * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES - * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR - * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES - * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN - * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT - * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. - */ - - -/** - * @defgroup fal_cosmap FAL_COSMAP - * @{ - */ -#include "sw.h" -#include "fal_cosmap.h" -#include "hsl_api.h" - -#ifndef IN_COSMAP_MINI -static sw_error_t -_fal_cosmap_dscp_to_pri_set(a_uint32_t dev_id, a_uint32_t dscp, a_uint32_t pri) -{ - sw_error_t rv; - hsl_api_t *p_api; - - SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id)); - - if (NULL == p_api->cosmap_dscp_to_pri_set) - return SW_NOT_SUPPORTED; - - rv = p_api->cosmap_dscp_to_pri_set(dev_id, dscp, pri); - return rv; -} - -static sw_error_t -_fal_cosmap_dscp_to_pri_get(a_uint32_t dev_id, a_uint32_t dscp, - a_uint32_t * pri) -{ - sw_error_t rv; - hsl_api_t *p_api; - - SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id)); - - if (NULL == p_api->cosmap_dscp_to_pri_get) - return SW_NOT_SUPPORTED; - - rv = p_api->cosmap_dscp_to_pri_get(dev_id, dscp, pri); - return rv; -} - -static sw_error_t -_fal_cosmap_dscp_to_dp_set(a_uint32_t dev_id, a_uint32_t dscp, a_uint32_t dp) -{ - sw_error_t rv; - hsl_api_t *p_api; - - SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id)); - - if (NULL == p_api->cosmap_dscp_to_dp_set) - return SW_NOT_SUPPORTED; - - rv = p_api->cosmap_dscp_to_dp_set(dev_id, dscp, dp); - return rv; -} - -static sw_error_t -_fal_cosmap_dscp_to_dp_get(a_uint32_t dev_id, a_uint32_t dscp, a_uint32_t * dp) -{ - sw_error_t rv; - hsl_api_t *p_api; - - SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id)); - - if (NULL == p_api->cosmap_dscp_to_dp_get) - return SW_NOT_SUPPORTED; - - rv = p_api->cosmap_dscp_to_dp_get(dev_id, dscp, dp); - return rv; -} - -static sw_error_t -_fal_cosmap_up_to_pri_set(a_uint32_t dev_id, a_uint32_t up, a_uint32_t pri) -{ - sw_error_t rv; - hsl_api_t *p_api; - - SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id)); - - if (NULL == p_api->cosmap_up_to_pri_set) - return SW_NOT_SUPPORTED; - - rv = p_api->cosmap_up_to_pri_set(dev_id, up, pri); - return rv; -} - -static sw_error_t -_fal_cosmap_up_to_pri_get(a_uint32_t dev_id, a_uint32_t up, a_uint32_t * pri) -{ - sw_error_t rv; - hsl_api_t *p_api; - - SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id)); - - if (NULL == p_api->cosmap_up_to_pri_get) - return SW_NOT_SUPPORTED; - - rv = p_api->cosmap_up_to_pri_get(dev_id, up, pri); - return rv; -} - -static sw_error_t -_fal_cosmap_up_to_dp_set(a_uint32_t dev_id, a_uint32_t up, a_uint32_t dp) -{ - sw_error_t rv; - hsl_api_t *p_api; - - SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id)); - - if (NULL == p_api->cosmap_up_to_dp_set) - return SW_NOT_SUPPORTED; - - rv = p_api->cosmap_up_to_dp_set(dev_id, up, dp); - return rv; -} - -static sw_error_t -_fal_cosmap_up_to_dp_get(a_uint32_t dev_id, a_uint32_t up, a_uint32_t * dp) -{ - sw_error_t rv; - hsl_api_t *p_api; - - SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id)); - - if (NULL == p_api->cosmap_up_to_dp_get) - return SW_NOT_SUPPORTED; - - rv = p_api->cosmap_up_to_dp_get(dev_id, up, dp); - return rv; -} - -static sw_error_t -_fal_cosmap_dscp_to_ehpri_set(a_uint32_t dev_id, a_uint32_t dscp, a_uint32_t pri) -{ - sw_error_t rv; - hsl_api_t *p_api; - - SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id)); - - if (NULL == p_api->cosmap_dscp_to_ehpri_set) - return SW_NOT_SUPPORTED; - - rv = p_api->cosmap_dscp_to_ehpri_set(dev_id, dscp, pri); - return rv; -} - -static sw_error_t -_fal_cosmap_dscp_to_ehpri_get(a_uint32_t dev_id, a_uint32_t dscp, - a_uint32_t * pri) -{ - sw_error_t rv; - hsl_api_t *p_api; - - SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id)); - - if (NULL == p_api->cosmap_dscp_to_ehpri_get) - return SW_NOT_SUPPORTED; - - rv = p_api->cosmap_dscp_to_ehpri_get(dev_id, dscp, pri); - return rv; -} - -static sw_error_t -_fal_cosmap_dscp_to_ehdp_set(a_uint32_t dev_id, a_uint32_t dscp, a_uint32_t dp) -{ - sw_error_t rv; - hsl_api_t *p_api; - - SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id)); - - if (NULL == p_api->cosmap_dscp_to_ehdp_set) - return SW_NOT_SUPPORTED; - - rv = p_api->cosmap_dscp_to_ehdp_set(dev_id, dscp, dp); - return rv; -} - -static sw_error_t -_fal_cosmap_dscp_to_ehdp_get(a_uint32_t dev_id, a_uint32_t dscp, a_uint32_t * dp) -{ - sw_error_t rv; - hsl_api_t *p_api; - - SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id)); - - if (NULL == p_api->cosmap_dscp_to_ehdp_get) - return SW_NOT_SUPPORTED; - - rv = p_api->cosmap_dscp_to_ehdp_get(dev_id, dscp, dp); - return rv; -} - -static sw_error_t -_fal_cosmap_up_to_ehpri_set(a_uint32_t dev_id, a_uint32_t up, a_uint32_t pri) -{ - sw_error_t rv; - hsl_api_t *p_api; - - SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id)); - - if (NULL == p_api->cosmap_up_to_ehpri_set) - return SW_NOT_SUPPORTED; - - rv = p_api->cosmap_up_to_ehpri_set(dev_id, up, pri); - return rv; -} - -static sw_error_t -_fal_cosmap_up_to_ehpri_get(a_uint32_t dev_id, a_uint32_t up, a_uint32_t * pri) -{ - sw_error_t rv; - hsl_api_t *p_api; - - SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id)); - - if (NULL == p_api->cosmap_up_to_ehpri_get) - return SW_NOT_SUPPORTED; - - rv = p_api->cosmap_up_to_ehpri_get(dev_id, up, pri); - return rv; -} - -static sw_error_t -_fal_cosmap_up_to_ehdp_set(a_uint32_t dev_id, a_uint32_t up, a_uint32_t dp) -{ - sw_error_t rv; - hsl_api_t *p_api; - - SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id)); - - if (NULL == p_api->cosmap_up_to_ehdp_set) - return SW_NOT_SUPPORTED; - - rv = p_api->cosmap_up_to_ehdp_set(dev_id, up, dp); - return rv; -} - -static sw_error_t -_fal_cosmap_up_to_ehdp_get(a_uint32_t dev_id, a_uint32_t up, a_uint32_t * dp) -{ - sw_error_t rv; - hsl_api_t *p_api; - - SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id)); - - if (NULL == p_api->cosmap_up_to_ehdp_get) - return SW_NOT_SUPPORTED; - - rv = p_api->cosmap_up_to_ehdp_get(dev_id, up, dp); - return rv; -} -#endif - -static sw_error_t -_fal_cosmap_pri_to_queue_set(a_uint32_t dev_id, a_uint32_t pri, - a_uint32_t queue) -{ - sw_error_t rv; - hsl_api_t *p_api; - - SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id)); - - if (NULL == p_api->cosmap_pri_to_queue_set) - return SW_NOT_SUPPORTED; - - rv = p_api->cosmap_pri_to_queue_set(dev_id, pri, queue); - return rv; -} - -static sw_error_t -_fal_cosmap_pri_to_ehqueue_set(a_uint32_t dev_id, a_uint32_t pri, - a_uint32_t queue) -{ - sw_error_t rv; - hsl_api_t *p_api; - - SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id)); - - if (NULL == p_api->cosmap_pri_to_ehqueue_set) - return SW_NOT_SUPPORTED; - - rv = p_api->cosmap_pri_to_ehqueue_set(dev_id, pri, queue); - return rv; -} - -#ifndef IN_COSMAP_MINI -static sw_error_t -_fal_cosmap_pri_to_queue_get(a_uint32_t dev_id, a_uint32_t pri, - a_uint32_t * queue) -{ - sw_error_t rv; - hsl_api_t *p_api; - - SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id)); - - if (NULL == p_api->cosmap_pri_to_queue_get) - return SW_NOT_SUPPORTED; - - rv = p_api->cosmap_pri_to_queue_get(dev_id, pri, queue); - return rv; -} - -static sw_error_t -_fal_cosmap_pri_to_ehqueue_get(a_uint32_t dev_id, a_uint32_t pri, - a_uint32_t * queue) -{ - sw_error_t rv; - hsl_api_t *p_api; - - SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id)); - - if (NULL == p_api->cosmap_pri_to_ehqueue_get) - return SW_NOT_SUPPORTED; - - rv = p_api->cosmap_pri_to_ehqueue_get(dev_id, pri, queue); - return rv; -} - -static sw_error_t -_fal_cosmap_egress_remark_set(a_uint32_t dev_id, a_uint32_t tbl_id, - fal_egress_remark_table_t * tbl) -{ - sw_error_t rv; - hsl_api_t *p_api; - - SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id)); - - if (NULL == p_api->cosmap_egress_remark_set) - return SW_NOT_SUPPORTED; - - rv = p_api->cosmap_egress_remark_set(dev_id, tbl_id, tbl); - return rv; -} - -static sw_error_t -_fal_cosmap_egress_remark_get(a_uint32_t dev_id, a_uint32_t tbl_id, - fal_egress_remark_table_t * tbl) -{ - sw_error_t rv; - hsl_api_t *p_api; - - SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id)); - - if (NULL == p_api->cosmap_egress_remark_get) - return SW_NOT_SUPPORTED; - - rv = p_api->cosmap_egress_remark_get(dev_id, tbl_id, tbl); - return rv; -} - -/** - * @brief Set dscp to internal priority mapping on one particular device. - * @param[in] dev_id device id - * @param[in] dscp dscp - * @param[in] pri internal priority - * @return SW_OK or error code - */ -sw_error_t -fal_cosmap_dscp_to_pri_set(a_uint32_t dev_id, a_uint32_t dscp, a_uint32_t pri) -{ - sw_error_t rv; - - FAL_API_LOCK; - rv = _fal_cosmap_dscp_to_pri_set(dev_id, dscp, pri); - FAL_API_UNLOCK; - return rv; -} - -/** - * @brief Get dscp to internal priority mapping on one particular device. - * @param[in] dev_id device id - * @param[in] dscp dscp - * @param[out] pri internal priority - * @return SW_OK or error code - */ -sw_error_t -fal_cosmap_dscp_to_pri_get(a_uint32_t dev_id, a_uint32_t dscp, - a_uint32_t * pri) -{ - sw_error_t rv; - - FAL_API_LOCK; - rv = _fal_cosmap_dscp_to_pri_get(dev_id, dscp, pri); - FAL_API_UNLOCK; - return rv; -} - -/** - * @brief Set dscp to internal drop precedence mapping on one particular device. - * @param[in] dev_id device id - * @param[in] dscp dscp - * @param[in] dp internal drop precedence - * @return SW_OK or error code - */ -sw_error_t -fal_cosmap_dscp_to_dp_set(a_uint32_t dev_id, a_uint32_t dscp, a_uint32_t dp) -{ - sw_error_t rv; - - FAL_API_LOCK; - rv = _fal_cosmap_dscp_to_dp_set(dev_id, dscp, dp); - FAL_API_UNLOCK; - return rv; -} - -/** - * @brief Get dscp to internal drop precedence mapping on one particular device. - * @param[in] dev_id device id - * @param[in] dscp dscp - * @param[out] dp internal drop precedence - * @return SW_OK or error code - */ -sw_error_t -fal_cosmap_dscp_to_dp_get(a_uint32_t dev_id, a_uint32_t dscp, a_uint32_t * dp) -{ - sw_error_t rv; - - FAL_API_LOCK; - rv = _fal_cosmap_dscp_to_dp_get(dev_id, dscp, dp); - FAL_API_UNLOCK; - return rv; -} - -/** - * @brief Set dot1p to internal priority mapping on one particular device. - * @param[in] dev_id device id - * @param[in] up dot1p - * @param[in] pri internal priority - * @return SW_OK or error code - */ -sw_error_t -fal_cosmap_up_to_pri_set(a_uint32_t dev_id, a_uint32_t up, a_uint32_t pri) -{ - sw_error_t rv; - - FAL_API_LOCK; - rv = _fal_cosmap_up_to_pri_set(dev_id, up, pri); - FAL_API_UNLOCK; - return rv; -} - -/** - * @brief Get dot1p to internal priority mapping on one particular device. - * @param[in] dev_id device id - * @param[in] up dot1p - * @param[out] pri internal priority - * @return SW_OK or error code - */ -sw_error_t -fal_cosmap_up_to_pri_get(a_uint32_t dev_id, a_uint32_t up, a_uint32_t * pri) -{ - sw_error_t rv; - - FAL_API_LOCK; - rv = _fal_cosmap_up_to_pri_get(dev_id, up, pri); - FAL_API_UNLOCK; - return rv; -} - -/** - * @brief Set dot1p to internal drop precedence mapping on one particular device. - * @param[in] dev_id device id - * @param[in] up dot1p - * @param[in] dp internal drop precedence - * @return SW_OK or error code - */ -sw_error_t -fal_cosmap_up_to_dp_set(a_uint32_t dev_id, a_uint32_t up, a_uint32_t dp) -{ - sw_error_t rv; - - FAL_API_LOCK; - rv = _fal_cosmap_up_to_dp_set(dev_id, up, dp); - FAL_API_UNLOCK; - return rv; -} - -/** - * @brief Get dot1p to internal drop precedence mapping on one particular device. - * @param[in] dev_id device id - * @param[in] up dot1p - * @param[in] dp internal drop precedence - * @return SW_OK or error code - */ -sw_error_t -fal_cosmap_up_to_dp_get(a_uint32_t dev_id, a_uint32_t up, a_uint32_t * dp) -{ - sw_error_t rv; - - FAL_API_LOCK; - rv = _fal_cosmap_up_to_dp_get(dev_id, up, dp); - FAL_API_UNLOCK; - return rv; -} - -/** - * @brief Set dscp to internal priority mapping on one particular device for WAN port. - * @param[in] dev_id device id - * @param[in] dscp dscp - * @param[in] pri internal priority - * @return SW_OK or error code - */ -sw_error_t -fal_cosmap_dscp_to_ehpri_set(a_uint32_t dev_id, a_uint32_t dscp, a_uint32_t pri) -{ - sw_error_t rv; - - FAL_API_LOCK; - rv = _fal_cosmap_dscp_to_ehpri_set(dev_id, dscp, pri); - FAL_API_UNLOCK; - return rv; -} - -/** - * @brief Get dscp to internal priority mapping on one particular device for WAN port. - * @param[in] dev_id device id - * @param[in] dscp dscp - * @param[out] pri internal priority - * @return SW_OK or error code - */ -sw_error_t -fal_cosmap_dscp_to_ehpri_get(a_uint32_t dev_id, a_uint32_t dscp, - a_uint32_t * pri) -{ - sw_error_t rv; - - FAL_API_LOCK; - rv = _fal_cosmap_dscp_to_ehpri_get(dev_id, dscp, pri); - FAL_API_UNLOCK; - return rv; -} - -/** - * @brief Set dscp to internal drop precedence mapping on one particular device for WAN port. - * @param[in] dev_id device id - * @param[in] dscp dscp - * @param[in] dp internal drop precedence - * @return SW_OK or error code - */ -sw_error_t -fal_cosmap_dscp_to_ehdp_set(a_uint32_t dev_id, a_uint32_t dscp, a_uint32_t dp) -{ - sw_error_t rv; - - FAL_API_LOCK; - rv = _fal_cosmap_dscp_to_ehdp_set(dev_id, dscp, dp); - FAL_API_UNLOCK; - return rv; -} - -/** - * @brief Get dscp to internal drop precedence mapping on one particular device for WAN port. - * @param[in] dev_id device id - * @param[in] dscp dscp - * @param[out] dp internal drop precedence - * @return SW_OK or error code - */ -sw_error_t -fal_cosmap_dscp_to_ehdp_get(a_uint32_t dev_id, a_uint32_t dscp, a_uint32_t * dp) -{ - sw_error_t rv; - - FAL_API_LOCK; - rv = _fal_cosmap_dscp_to_ehdp_get(dev_id, dscp, dp); - FAL_API_UNLOCK; - return rv; -} - -/** - * @brief Set dot1p to internal priority mapping on one particular device for WAN port. - * @param[in] dev_id device id - * @param[in] up dot1p - * @param[in] pri internal priority - * @return SW_OK or error code - */ -sw_error_t -fal_cosmap_up_to_ehpri_set(a_uint32_t dev_id, a_uint32_t up, a_uint32_t pri) -{ - sw_error_t rv; - - FAL_API_LOCK; - rv = _fal_cosmap_up_to_ehpri_set(dev_id, up, pri); - FAL_API_UNLOCK; - return rv; -} - -/** - * @brief Get dot1p to internal priority mapping on one particular device for WAN port. - * @param[in] dev_id device id - * @param[in] up dot1p - * @param[out] pri internal priority - * @return SW_OK or error code - */ -sw_error_t -fal_cosmap_up_to_ehpri_get(a_uint32_t dev_id, a_uint32_t up, a_uint32_t * pri) -{ - sw_error_t rv; - - FAL_API_LOCK; - rv = _fal_cosmap_up_to_ehpri_get(dev_id, up, pri); - FAL_API_UNLOCK; - return rv; -} - -/** - * @brief Set dot1p to internal drop precedence mapping on one particular device for WAN port. - * @param[in] dev_id device id - * @param[in] up dot1p - * @param[in] dp internal drop precedence - * @return SW_OK or error code - */ -sw_error_t -fal_cosmap_up_to_ehdp_set(a_uint32_t dev_id, a_uint32_t up, a_uint32_t dp) -{ - sw_error_t rv; - - FAL_API_LOCK; - rv = _fal_cosmap_up_to_ehdp_set(dev_id, up, dp); - FAL_API_UNLOCK; - return rv; -} - -/** - * @brief Get dot1p to internal drop precedence mapping on one particular device for WAN port. - * @param[in] dev_id device id - * @param[in] up dot1p - * @param[in] dp internal drop precedence - * @return SW_OK or error code - */ -sw_error_t -fal_cosmap_up_to_ehdp_get(a_uint32_t dev_id, a_uint32_t up, a_uint32_t * dp) -{ - sw_error_t rv; - - FAL_API_LOCK; - rv = _fal_cosmap_up_to_ehdp_get(dev_id, up, dp); - FAL_API_UNLOCK; - return rv; -} -#endif - -/** - * @brief Set internal priority to queue mapping on one particular device. - * @details Comments: - * This function is for port 1/2/3/4 which have four egress queues - * @param[in] dev_id device id - * @param[in] pri internal priority - * @param[in] queue queue id - * @return SW_OK or error code - */ -sw_error_t -fal_cosmap_pri_to_queue_set(a_uint32_t dev_id, a_uint32_t pri, - a_uint32_t queue) -{ - sw_error_t rv; - - FAL_API_LOCK; - rv = _fal_cosmap_pri_to_queue_set(dev_id, pri, queue); - FAL_API_UNLOCK; - return rv; -} - -/** - * @brief Set internal priority to queue mapping on one particular device. - * @details Comments: - * This function is for port 0/5/6 which have six egress queues - * @param[in] dev_id device id - * @param[in] pri internal priority - * @param[in] queue queue id - * @return SW_OK or error code - */ -sw_error_t -fal_cosmap_pri_to_ehqueue_set(a_uint32_t dev_id, a_uint32_t pri, - a_uint32_t queue) -{ - sw_error_t rv; - - FAL_API_LOCK; - rv = _fal_cosmap_pri_to_ehqueue_set(dev_id, pri, queue); - FAL_API_UNLOCK; - return rv; -} - -#ifndef IN_COSMAP_MINI -/** - * @brief Get internal priority to queue mapping on one particular device. - * @details Comments: - * This function is for port 1/2/3/4 which have four egress queues - * @param[in] dev_id device id - * @param[in] pri internal priority - * @param[out] queue queue id - * @return SW_OK or error code - */ -sw_error_t -fal_cosmap_pri_to_queue_get(a_uint32_t dev_id, a_uint32_t pri, - a_uint32_t * queue) -{ - sw_error_t rv; - - FAL_API_LOCK; - rv = _fal_cosmap_pri_to_queue_get(dev_id, pri, queue); - FAL_API_UNLOCK; - return rv; -} - -/** - * @brief Get internal priority to queue mapping on one particular device. - * @details Comments: - * This function is for port 0/5/6 which have six egress queues - * @param[in] dev_id device id - * @param[in] pri internal priority - * @param[in] queue queue id - * @return SW_OK or error code - */ -sw_error_t -fal_cosmap_pri_to_ehqueue_get(a_uint32_t dev_id, a_uint32_t pri, - a_uint32_t * queue) -{ - sw_error_t rv; - - FAL_API_LOCK; - rv = _fal_cosmap_pri_to_ehqueue_get(dev_id, pri, queue); - FAL_API_UNLOCK; - return rv; -} - -/** - * @brief Set egress queue based CoS remap table on one particular device. - * @param[in] dev_id device id - * @param[in] tbl_id CoS remap table id - * @param[in] tbl CoS remap table - * @return SW_OK or error code - */ -sw_error_t -fal_cosmap_egress_remark_set(a_uint32_t dev_id, a_uint32_t tbl_id, - fal_egress_remark_table_t * tbl) -{ - sw_error_t rv; - - FAL_API_LOCK; - rv = _fal_cosmap_egress_remark_set(dev_id, tbl_id, tbl); - FAL_API_UNLOCK; - return rv; -} - -/** - * @brief Get egress queue based CoS remap table on one particular device. - * @param[in] dev_id device id - * @param[in] tbl_id CoS remap table id - * @param[out] tbl CoS remap table - * @return SW_OK or error code - */ -sw_error_t -fal_cosmap_egress_remark_get(a_uint32_t dev_id, a_uint32_t tbl_id, - fal_egress_remark_table_t * tbl) -{ - sw_error_t rv; - - FAL_API_LOCK; - rv = _fal_cosmap_egress_remark_get(dev_id, tbl_id, tbl); - FAL_API_UNLOCK; - return rv; -} -#endif - -/** - * @} - */ - diff --git a/feeds/ipq807x/qca-ssdk/src/src/fal/fal_ctrlpkt.c b/feeds/ipq807x/qca-ssdk/src/src/fal/fal_ctrlpkt.c deleted file mode 100755 index cfcf5a245..000000000 --- a/feeds/ipq807x/qca-ssdk/src/src/fal/fal_ctrlpkt.c +++ /dev/null @@ -1,248 +0,0 @@ -/* - * Copyright (c) 2016-2017, The Linux Foundation. All rights reserved. - * Permission to use, copy, modify, and/or distribute this software for - * any purpose with or without fee is hereby granted, provided that the - * above copyright notice and this permission notice appear in all copies. - * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES - * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR - * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES - * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN - * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT - * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. - */ - - -/** - * @defgroup fal_ctrlpkt FAL_CTRLPKT - * @{ - */ -#include "sw.h" -#include "fal_ctrlpkt.h" -#include "hsl_api.h" -#include "adpt.h" - -#include -#include - - -/** - * @} - */ -sw_error_t -_fal_mgmtctrl_ethtype_profile_set(a_uint32_t dev_id, a_uint32_t profile_id, a_uint32_t ethtype) -{ - sw_error_t rv; - adpt_api_t *p_api; - - SW_RTN_ON_NULL(p_api = adpt_api_ptr_get(dev_id)); - - if (NULL == p_api->adpt_mgmtctrl_ethtype_profile_set) - return SW_NOT_SUPPORTED; - - rv = p_api->adpt_mgmtctrl_ethtype_profile_set(dev_id, profile_id, ethtype); - return rv; -} - -sw_error_t -_fal_mgmtctrl_ethtype_profile_get(a_uint32_t dev_id, a_uint32_t profile_id, a_uint32_t * ethtype) -{ - sw_error_t rv; - adpt_api_t *p_api; - - SW_RTN_ON_NULL(p_api = adpt_api_ptr_get(dev_id)); - - if (NULL == p_api->adpt_mgmtctrl_ethtype_profile_get) - return SW_NOT_SUPPORTED; - - rv = p_api->adpt_mgmtctrl_ethtype_profile_get(dev_id, profile_id, ethtype); - return rv; -} - -sw_error_t -_fal_mgmtctrl_rfdb_profile_set(a_uint32_t dev_id, a_uint32_t profile_id, fal_mac_addr_t *addr) -{ - sw_error_t rv; - adpt_api_t *p_api; - - SW_RTN_ON_NULL(p_api = adpt_api_ptr_get(dev_id)); - - if (NULL == p_api->adpt_mgmtctrl_rfdb_profile_set) - return SW_NOT_SUPPORTED; - - rv = p_api->adpt_mgmtctrl_rfdb_profile_set(dev_id, profile_id, addr); - return rv; -} - -sw_error_t -_fal_mgmtctrl_rfdb_profile_get(a_uint32_t dev_id, a_uint32_t profile_id, fal_mac_addr_t *addr) -{ - sw_error_t rv; - adpt_api_t *p_api; - - SW_RTN_ON_NULL(p_api = adpt_api_ptr_get(dev_id)); - - if (NULL == p_api->adpt_mgmtctrl_rfdb_profile_get) - return SW_NOT_SUPPORTED; - - rv = p_api->adpt_mgmtctrl_rfdb_profile_get(dev_id, profile_id, addr); - return rv; -} - -sw_error_t -_fal_mgmtctrl_ctrlpkt_profile_add(a_uint32_t dev_id, fal_ctrlpkt_profile_t *ctrlpkt) -{ - sw_error_t rv; - adpt_api_t *p_api; - - SW_RTN_ON_NULL(p_api = adpt_api_ptr_get(dev_id)); - - if (NULL == p_api->adpt_mgmtctrl_ctrlpkt_profile_add) - return SW_NOT_SUPPORTED; - - rv = p_api->adpt_mgmtctrl_ctrlpkt_profile_add(dev_id, ctrlpkt); - return rv; -} - -sw_error_t -_fal_mgmtctrl_ctrlpkt_profile_del(a_uint32_t dev_id, fal_ctrlpkt_profile_t *ctrlpkt) -{ - sw_error_t rv; - adpt_api_t *p_api; - - SW_RTN_ON_NULL(p_api = adpt_api_ptr_get(dev_id)); - - if (NULL == p_api->adpt_mgmtctrl_ctrlpkt_profile_del) - return SW_NOT_SUPPORTED; - - rv = p_api->adpt_mgmtctrl_ctrlpkt_profile_del(dev_id, ctrlpkt); - return rv; -} - -sw_error_t -_fal_mgmtctrl_ctrlpkt_profile_getfirst(a_uint32_t dev_id, fal_ctrlpkt_profile_t *ctrlpkt) -{ - sw_error_t rv; - adpt_api_t *p_api; - - SW_RTN_ON_NULL(p_api = adpt_api_ptr_get(dev_id)); - - if (NULL == p_api->adpt_mgmtctrl_ctrlpkt_profile_getfirst) - return SW_NOT_SUPPORTED; - - rv = p_api->adpt_mgmtctrl_ctrlpkt_profile_getfirst(dev_id, ctrlpkt); - return rv; -} - -sw_error_t -_fal_mgmtctrl_ctrlpkt_profile_getnext(a_uint32_t dev_id, fal_ctrlpkt_profile_t *ctrlpkt) -{ - sw_error_t rv; - adpt_api_t *p_api; - - SW_RTN_ON_NULL(p_api = adpt_api_ptr_get(dev_id)); - - if (NULL == p_api->adpt_mgmtctrl_ctrlpkt_profile_getnext) - return SW_NOT_SUPPORTED; - - rv = p_api->adpt_mgmtctrl_ctrlpkt_profile_getnext(dev_id, ctrlpkt); - return rv; -} - -sw_error_t -fal_mgmtctrl_ethtype_profile_set(a_uint32_t dev_id, a_uint32_t profile_id, a_uint32_t ethtype) -{ - sw_error_t rv = SW_OK; - - FAL_CTRLPKT_API_LOCK; - rv = _fal_mgmtctrl_ethtype_profile_set(dev_id, profile_id, ethtype); - FAL_CTRLPKT_API_UNLOCK; - return rv; -} - -sw_error_t -fal_mgmtctrl_ethtype_profile_get(a_uint32_t dev_id, a_uint32_t profile_id, a_uint32_t * ethtype) -{ - sw_error_t rv = SW_OK; - - FAL_CTRLPKT_API_LOCK; - rv = _fal_mgmtctrl_ethtype_profile_get(dev_id, profile_id, ethtype); - FAL_CTRLPKT_API_UNLOCK; - return rv; -} - -sw_error_t -fal_mgmtctrl_rfdb_profile_set(a_uint32_t dev_id, a_uint32_t profile_id, fal_mac_addr_t *addr) -{ - sw_error_t rv = SW_OK; - - FAL_CTRLPKT_API_LOCK; - rv = _fal_mgmtctrl_rfdb_profile_set(dev_id, profile_id, addr); - FAL_CTRLPKT_API_UNLOCK; - return rv; -} - -sw_error_t -fal_mgmtctrl_rfdb_profile_get(a_uint32_t dev_id, a_uint32_t profile_id, fal_mac_addr_t *addr) -{ - sw_error_t rv = SW_OK; - - FAL_CTRLPKT_API_LOCK; - rv = _fal_mgmtctrl_rfdb_profile_get(dev_id, profile_id, addr); - FAL_CTRLPKT_API_UNLOCK; - return rv; -} - -sw_error_t -fal_mgmtctrl_ctrlpkt_profile_add(a_uint32_t dev_id, fal_ctrlpkt_profile_t *ctrlpkt) -{ - sw_error_t rv = SW_OK; - - FAL_CTRLPKT_API_LOCK; - rv = _fal_mgmtctrl_ctrlpkt_profile_add(dev_id, ctrlpkt); - FAL_CTRLPKT_API_UNLOCK; - return rv; -} - -sw_error_t -fal_mgmtctrl_ctrlpkt_profile_del(a_uint32_t dev_id, fal_ctrlpkt_profile_t *ctrlpkt) -{ - sw_error_t rv = SW_OK; - - FAL_CTRLPKT_API_LOCK; - rv = _fal_mgmtctrl_ctrlpkt_profile_del(dev_id, ctrlpkt); - FAL_CTRLPKT_API_UNLOCK; - return rv; -} - -sw_error_t -fal_mgmtctrl_ctrlpkt_profile_getfirst(a_uint32_t dev_id, fal_ctrlpkt_profile_t *ctrlpkt) -{ - sw_error_t rv = SW_OK; - - FAL_CTRLPKT_API_LOCK; - rv = _fal_mgmtctrl_ctrlpkt_profile_getfirst(dev_id, ctrlpkt); - FAL_CTRLPKT_API_UNLOCK; - return rv; -} - -sw_error_t -fal_mgmtctrl_ctrlpkt_profile_getnext(a_uint32_t dev_id, fal_ctrlpkt_profile_t *ctrlpkt) -{ - sw_error_t rv = SW_OK; - - FAL_CTRLPKT_API_LOCK; - rv = _fal_mgmtctrl_ctrlpkt_profile_getnext(dev_id, ctrlpkt); - FAL_CTRLPKT_API_UNLOCK; - return rv; -} - -EXPORT_SYMBOL(fal_mgmtctrl_ethtype_profile_set); -EXPORT_SYMBOL(fal_mgmtctrl_ethtype_profile_get); -EXPORT_SYMBOL(fal_mgmtctrl_rfdb_profile_set); -EXPORT_SYMBOL(fal_mgmtctrl_rfdb_profile_get); -EXPORT_SYMBOL(fal_mgmtctrl_ctrlpkt_profile_add); -EXPORT_SYMBOL(fal_mgmtctrl_ctrlpkt_profile_del); -EXPORT_SYMBOL(fal_mgmtctrl_ctrlpkt_profile_getfirst); -EXPORT_SYMBOL(fal_mgmtctrl_ctrlpkt_profile_getnext); - diff --git a/feeds/ipq807x/qca-ssdk/src/src/fal/fal_fdb.c b/feeds/ipq807x/qca-ssdk/src/src/fal/fal_fdb.c deleted file mode 100755 index 02dc74a4f..000000000 --- a/feeds/ipq807x/qca-ssdk/src/src/fal/fal_fdb.c +++ /dev/null @@ -1,1942 +0,0 @@ -/* - * Copyright (c) 2012, 2015-2018, The Linux Foundation. All rights reserved. - * Permission to use, copy, modify, and/or distribute this software for - * any purpose with or without fee is hereby granted, provided that the - * above copyright notice and this permission notice appear in all copies. - * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES - * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR - * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES - * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN - * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT - * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. - */ - - -/** - * @defgroup fal_fdb FAL_FDB - * @{ - */ -#include "sw.h" -#include "fal_fdb.h" -#include "hsl_api.h" -#include "adpt.h" - -#include -#include - - -#ifndef IN_FDB_MINI -static sw_error_t -_fal_fdb_entry_add(a_uint32_t dev_id, const fal_fdb_entry_t * entry) -{ - sw_error_t rv; - hsl_api_t *p_api; - adpt_api_t *p_adpt_api; - - if((p_adpt_api = adpt_api_ptr_get(dev_id)) != NULL) { - if (NULL == p_adpt_api->adpt_fdb_add) - return SW_NOT_SUPPORTED; - - rv = p_adpt_api->adpt_fdb_add(dev_id, entry); - return rv; - } - - SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id)); - - if (NULL == p_api->fdb_add) - return SW_NOT_SUPPORTED; - - rv = p_api->fdb_add(dev_id, entry); - return rv; -} -#endif - -static sw_error_t -_fal_fdb_entry_flush(a_uint32_t dev_id, a_uint32_t flag) -{ - sw_error_t rv; - hsl_api_t *p_api; - adpt_api_t *p_adpt_api; - - if((p_adpt_api = adpt_api_ptr_get(dev_id)) != NULL) { - if (NULL == p_adpt_api->adpt_fdb_del_all) - return SW_NOT_SUPPORTED; - - rv = p_adpt_api->adpt_fdb_del_all(dev_id, flag); - return rv; - } - - SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id)); - - if (NULL == p_api->fdb_del_all) - return SW_NOT_SUPPORTED; - - rv = p_api->fdb_del_all(dev_id, flag); - return rv; -} - -static sw_error_t -_fal_fdb_entry_del_byport(a_uint32_t dev_id, fal_port_t port_id, a_uint32_t flag) -{ - sw_error_t rv; - hsl_api_t *p_api; - adpt_api_t *p_adpt_api; - - if((p_adpt_api = adpt_api_ptr_get(dev_id)) != NULL) { - if (NULL == p_adpt_api->adpt_fdb_del_by_port) - return SW_NOT_SUPPORTED; - - rv = p_adpt_api->adpt_fdb_del_by_port(dev_id, port_id, flag); - return rv; - } - - SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id)); - - if (NULL == p_api->fdb_del_by_port) - return SW_NOT_SUPPORTED; - - rv = p_api->fdb_del_by_port(dev_id, port_id, flag); - return rv; -} - - -static sw_error_t -_fal_fdb_entry_del_bymac(a_uint32_t dev_id, const fal_fdb_entry_t * entry) -{ - sw_error_t rv; - hsl_api_t *p_api; - adpt_api_t *p_adpt_api; - - if((p_adpt_api = adpt_api_ptr_get(dev_id)) != NULL) { - if (NULL == p_adpt_api->adpt_fdb_del_by_mac) - return SW_NOT_SUPPORTED; - - rv = p_adpt_api->adpt_fdb_del_by_mac(dev_id, entry); - return rv; - } - - SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id)); - - if (NULL == p_api->fdb_del_by_mac) - return SW_NOT_SUPPORTED; - - rv = p_api->fdb_del_by_mac(dev_id, entry); - return rv; -} - -static sw_error_t -_fal_fdb_entry_getfirst(a_uint32_t dev_id, fal_fdb_entry_t * entry) -{ - sw_error_t rv; - hsl_api_t *p_api; - adpt_api_t *p_adpt_api; - - if((p_adpt_api = adpt_api_ptr_get(dev_id)) != NULL) { - if (NULL == p_adpt_api->adpt_fdb_first) - return SW_NOT_SUPPORTED; - - rv = p_adpt_api->adpt_fdb_first(dev_id, entry); - return rv; - } - - SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id)); - - if (NULL == p_api->fdb_first) - return SW_NOT_SUPPORTED; - - rv = p_api->fdb_first(dev_id, entry); - return rv; -} - -#ifndef IN_FDB_MINI -static sw_error_t -_fal_fdb_entry_getnext(a_uint32_t dev_id, fal_fdb_entry_t * entry) -{ - sw_error_t rv; - hsl_api_t *p_api; - adpt_api_t *p_adpt_api; - - if((p_adpt_api = adpt_api_ptr_get(dev_id)) != NULL) { - if (NULL == p_adpt_api->adpt_fdb_next) - return SW_NOT_SUPPORTED; - - rv = p_adpt_api->adpt_fdb_next(dev_id, entry); - return rv; - } - - SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id)); - - if (NULL == p_api->fdb_next) - return SW_NOT_SUPPORTED; - - rv = p_api->fdb_next(dev_id, entry); - return rv; -} -#endif - -static sw_error_t -_fal_fdb_entry_search(a_uint32_t dev_id, fal_fdb_entry_t * entry) -{ - sw_error_t rv; - hsl_api_t *p_api; - adpt_api_t *p_adpt_api; - - if((p_adpt_api = adpt_api_ptr_get(dev_id)) != NULL) { - if (NULL == p_adpt_api->adpt_fdb_find) - return SW_NOT_SUPPORTED; - - rv = p_adpt_api->adpt_fdb_find(dev_id, entry); - return rv; - } - - SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id)); - - if (NULL == p_api->fdb_find) - return SW_NOT_SUPPORTED; - - rv = p_api->fdb_find(dev_id, entry); - return rv; -} - -static sw_error_t -_fal_fdb_port_learn_set(a_uint32_t dev_id, fal_port_t port_id, a_bool_t enable) -{ - sw_error_t rv; - hsl_api_t *p_api; - adpt_api_t *p_adpt_api; - - if((p_adpt_api = adpt_api_ptr_get(dev_id)) != NULL) { - if (NULL == p_adpt_api->adpt_fdb_port_learn_set) - return SW_NOT_SUPPORTED; - - rv = p_adpt_api->adpt_fdb_port_learn_set(dev_id, port_id, enable); - return rv; - } - - SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id)); - - if (NULL == p_api->port_learn_set) - return SW_NOT_SUPPORTED; - - rv = p_api->port_learn_set(dev_id, port_id, enable); - return rv; -} - -#ifndef IN_FDB_MINI -static sw_error_t -_fal_fdb_port_learn_get(a_uint32_t dev_id, fal_port_t port_id, a_bool_t * enable) -{ - sw_error_t rv; - hsl_api_t *p_api; - adpt_api_t *p_adpt_api; - - if((p_adpt_api = adpt_api_ptr_get(dev_id)) != NULL) { - if (NULL == p_adpt_api->adpt_fdb_port_learn_get) - return SW_NOT_SUPPORTED; - - rv = p_adpt_api->adpt_fdb_port_learn_get(dev_id, port_id, enable); - return rv; - } - - SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id)); - - if (NULL == p_api->port_learn_get) - return SW_NOT_SUPPORTED; - - rv = p_api->port_learn_get(dev_id, port_id, enable); - return rv; -} -#endif - -static sw_error_t -_fal_fdb_port_learning_ctrl_set(a_uint32_t dev_id, fal_port_t port_id, a_bool_t enable, fal_fwd_cmd_t cmd) -{ - adpt_api_t *p_api; - sw_error_t rv = SW_OK; - - SW_RTN_ON_NULL(p_api = adpt_api_ptr_get(dev_id)); - - if (NULL == p_api->adpt_fdb_port_newaddr_lrn_set) - return SW_NOT_SUPPORTED; - - rv = p_api->adpt_fdb_port_newaddr_lrn_set(dev_id, port_id, enable, cmd); - return rv; -} - -#ifndef IN_FDB_MINI -static sw_error_t -_fal_fdb_port_learning_ctrl_get(a_uint32_t dev_id, fal_port_t port_id, a_bool_t *enable, fal_fwd_cmd_t *cmd) -{ - adpt_api_t *p_api; - sw_error_t rv = SW_OK; - - SW_RTN_ON_NULL(p_api = adpt_api_ptr_get(dev_id)); - - if (NULL == p_api->adpt_fdb_port_newaddr_lrn_get) - return SW_NOT_SUPPORTED; - - rv = p_api->adpt_fdb_port_newaddr_lrn_get(dev_id, port_id, enable, cmd); - return rv; -} -#endif - -static sw_error_t -_fal_fdb_port_stamove_ctrl_set(a_uint32_t dev_id, fal_port_t port_id, a_bool_t enable, fal_fwd_cmd_t cmd) -{ - adpt_api_t *p_api; - sw_error_t rv = SW_OK; - - SW_RTN_ON_NULL(p_api = adpt_api_ptr_get(dev_id)); - - if (NULL == p_api->adpt_fdb_port_stamove_set) - return SW_NOT_SUPPORTED; - - rv = p_api->adpt_fdb_port_stamove_set(dev_id, port_id, enable, cmd); - return rv; -} - -#ifndef IN_FDB_MINI -static sw_error_t -_fal_fdb_port_stamove_ctrl_get(a_uint32_t dev_id, fal_port_t port_id, a_bool_t *enable, fal_fwd_cmd_t *cmd) -{ - adpt_api_t *p_api; - sw_error_t rv = SW_OK; - - SW_RTN_ON_NULL(p_api = adpt_api_ptr_get(dev_id)); - - if (NULL == p_api->adpt_fdb_port_stamove_get) - return SW_NOT_SUPPORTED; - - rv = p_api->adpt_fdb_port_stamove_get(dev_id, port_id, enable, cmd); - return rv; -} -#endif - -static sw_error_t -_fal_fdb_aging_ctrl_set(a_uint32_t dev_id, a_bool_t enable) -{ - sw_error_t rv; - hsl_api_t *p_api; - adpt_api_t *p_adpt_api; - - if((p_adpt_api = adpt_api_ptr_get(dev_id)) != NULL) { - if (NULL == p_adpt_api->adpt_fdb_age_ctrl_set) - return SW_NOT_SUPPORTED; - - rv = p_adpt_api->adpt_fdb_age_ctrl_set(dev_id, enable); - return rv; - } - - SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id)); - - if (NULL == p_api->age_ctrl_set) - return SW_NOT_SUPPORTED; - - rv = p_api->age_ctrl_set(dev_id, enable); - return rv; -} - -#ifndef IN_FDB_MINI -static sw_error_t -_fal_fdb_aging_ctrl_get(a_uint32_t dev_id, a_bool_t * enable) -{ - sw_error_t rv; - hsl_api_t *p_api; - adpt_api_t *p_adpt_api; - - if((p_adpt_api = adpt_api_ptr_get(dev_id)) != NULL) { - if (NULL == p_adpt_api->adpt_fdb_age_ctrl_get) - return SW_NOT_SUPPORTED; - - rv = p_adpt_api->adpt_fdb_age_ctrl_get(dev_id, enable); - return rv; - } - - SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id)); - - if (NULL == p_api->age_ctrl_get) - return SW_NOT_SUPPORTED; - - rv = p_api->age_ctrl_get(dev_id, enable); - return rv; -} - -static sw_error_t -_fal_fdb_vlan_ivl_svl_set(a_uint32_t dev_id, fal_fdb_smode smode) -{ - sw_error_t rv; - hsl_api_t *p_api; - - SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id)); - - if (NULL == p_api->vlan_ivl_svl_set) - return SW_NOT_SUPPORTED; - - rv = p_api->vlan_ivl_svl_set(dev_id, smode); - return rv; -} - -static sw_error_t -_fal_fdb_vlan_ivl_svl_get(a_uint32_t dev_id, fal_fdb_smode* smode) -{ - sw_error_t rv; - hsl_api_t *p_api; - - SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id)); - - if (NULL == p_api->vlan_ivl_svl_get) - return SW_NOT_SUPPORTED; - - rv = p_api->vlan_ivl_svl_get(dev_id, smode); - return rv; -} - -static sw_error_t -_fal_fdb_aging_time_set(a_uint32_t dev_id, a_uint32_t * time) -{ - sw_error_t rv; - hsl_api_t *p_api; - adpt_api_t *p_adpt_api; - - if((p_adpt_api = adpt_api_ptr_get(dev_id)) != NULL) { - if (NULL == p_adpt_api->adpt_fdb_age_time_set) - return SW_NOT_SUPPORTED; - - rv = p_adpt_api->adpt_fdb_age_time_set(dev_id, time); - return rv; - } - - SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id)); - - if (NULL == p_api->age_time_set) - return SW_NOT_SUPPORTED; - - rv = p_api->age_time_set(dev_id, time); - return rv; -} - - -static sw_error_t -_fal_fdb_aging_time_get(a_uint32_t dev_id, a_uint32_t * time) -{ - sw_error_t rv; - hsl_api_t *p_api; - adpt_api_t *p_adpt_api; - - if((p_adpt_api = adpt_api_ptr_get(dev_id)) != NULL) { - if (NULL == p_adpt_api->adpt_fdb_age_time_get) - return SW_NOT_SUPPORTED; - - rv = p_adpt_api->adpt_fdb_age_time_get(dev_id, time); - return rv; - } - - SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id)); - - if (NULL == p_api->age_time_get) - return SW_NOT_SUPPORTED; - - rv = p_api->age_time_get(dev_id, time); - return rv; -} -#endif - -static sw_error_t -_fal_fdb_entry_getnext_byindex(a_uint32_t dev_id, a_uint32_t * iterator, fal_fdb_entry_t * entry) -{ - sw_error_t rv; - hsl_api_t *p_api; - adpt_api_t *p_adpt_api; - - if((p_adpt_api = adpt_api_ptr_get(dev_id)) != NULL) { - if (NULL == p_adpt_api->adpt_fdb_iterate) - return SW_NOT_SUPPORTED; - - rv = p_adpt_api->adpt_fdb_iterate(dev_id, iterator, entry); - return rv; - } - - SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id)); - - if (NULL == p_api->fdb_iterate) - return SW_NOT_SUPPORTED; - - rv = p_api->fdb_iterate(dev_id, iterator, entry); - return rv; -} - -static sw_error_t -_fal_fdb_entry_extend_getnext(a_uint32_t dev_id, fal_fdb_op_t * option, - fal_fdb_entry_t * entry) -{ - sw_error_t rv; - hsl_api_t *p_api; - adpt_api_t *p_adpt_api; - - if((p_adpt_api = adpt_api_ptr_get(dev_id)) != NULL) { - if (NULL == p_adpt_api->adpt_fdb_extend_next) - return SW_NOT_SUPPORTED; - - rv = p_adpt_api->adpt_fdb_extend_next(dev_id, option, entry); - return rv; - } - - SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id)); - - if (NULL == p_api->fdb_extend_next) - return SW_NOT_SUPPORTED; - - rv = p_api->fdb_extend_next(dev_id, option, entry); - return rv; -} - -static sw_error_t -_fal_fdb_entry_extend_getfirst(a_uint32_t dev_id, fal_fdb_op_t * option, - fal_fdb_entry_t * entry) -{ - sw_error_t rv; - hsl_api_t *p_api; - adpt_api_t *p_adpt_api; - - if((p_adpt_api = adpt_api_ptr_get(dev_id)) != NULL) { - if (NULL == p_adpt_api->adpt_fdb_extend_first) - return SW_NOT_SUPPORTED; - - rv = p_adpt_api->adpt_fdb_extend_first(dev_id, option, entry); - return rv; - } - - SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id)); - - if (NULL == p_api->fdb_extend_first) - return SW_NOT_SUPPORTED; - - rv = p_api->fdb_extend_first(dev_id, option, entry); - return rv; -} - -#ifndef IN_FDB_MINI -static sw_error_t -_fal_fdb_entry_update_byport(a_uint32_t dev_id, fal_port_t old_port, fal_port_t new_port, - a_uint32_t fid, fal_fdb_op_t * option) -{ - sw_error_t rv; - hsl_api_t *p_api; - adpt_api_t *p_adpt_api; - - if((p_adpt_api = adpt_api_ptr_get(dev_id)) != NULL) { - if (NULL == p_adpt_api->adpt_fdb_transfer) - return SW_NOT_SUPPORTED; - - rv = p_adpt_api->adpt_fdb_transfer(dev_id, old_port, new_port, fid, option); - return rv; - } - - SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id)); - - if (NULL == p_api->fdb_transfer) - return SW_NOT_SUPPORTED; - - rv = p_api->fdb_transfer(dev_id, old_port, new_port, fid, option); - return rv; -} - -static sw_error_t -_fal_port_fdb_learn_limit_set(a_uint32_t dev_id, fal_port_t port_id, - a_bool_t enable, a_uint32_t cnt) -{ - sw_error_t rv; - hsl_api_t *p_api; - adpt_api_t *p_adpt_api; - - if((p_adpt_api = adpt_api_ptr_get(dev_id)) != NULL) { - if (NULL == p_adpt_api->adpt_port_fdb_learn_limit_set) - return SW_NOT_SUPPORTED; - - rv = p_adpt_api->adpt_port_fdb_learn_limit_set(dev_id, port_id, enable, cnt); - return rv; - } - - SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id)); - - if (NULL == p_api->port_fdb_learn_limit_set) - return SW_NOT_SUPPORTED; - - rv = p_api->port_fdb_learn_limit_set(dev_id, port_id, enable, cnt); - return rv; -} - -static sw_error_t -_fal_port_fdb_learn_limit_get(a_uint32_t dev_id, fal_port_t port_id, - a_bool_t * enable, a_uint32_t * cnt) -{ - sw_error_t rv; - hsl_api_t *p_api; - adpt_api_t *p_adpt_api; - - if((p_adpt_api = adpt_api_ptr_get(dev_id)) != NULL) { - if (NULL == p_adpt_api->adpt_port_fdb_learn_limit_get) - return SW_NOT_SUPPORTED; - - rv = p_adpt_api->adpt_port_fdb_learn_limit_get(dev_id, port_id, enable, cnt); - return rv; - } - - SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id)); - - if (NULL == p_api->port_fdb_learn_limit_get) - return SW_NOT_SUPPORTED; - - rv = p_api->port_fdb_learn_limit_get(dev_id, port_id, enable, cnt); - return rv; -} - -static sw_error_t -_fal_port_fdb_learn_exceed_cmd_set(a_uint32_t dev_id, fal_port_t port_id, - fal_fwd_cmd_t cmd) -{ - sw_error_t rv; - hsl_api_t *p_api; - adpt_api_t *p_adpt_api; - - if((p_adpt_api = adpt_api_ptr_get(dev_id)) != NULL) { - if (NULL == p_adpt_api->adpt_port_fdb_learn_exceed_cmd_set) - return SW_NOT_SUPPORTED; - - rv = p_adpt_api->adpt_port_fdb_learn_exceed_cmd_set(dev_id, port_id, cmd); - return rv; - } - - SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id)); - - if (NULL == p_api->port_fdb_learn_exceed_cmd_set) - return SW_NOT_SUPPORTED; - - rv = p_api->port_fdb_learn_exceed_cmd_set(dev_id, port_id, cmd); - return rv; -} - -static sw_error_t -_fal_port_fdb_learn_exceed_cmd_get(a_uint32_t dev_id, fal_port_t port_id, - fal_fwd_cmd_t * cmd) -{ - sw_error_t rv; - hsl_api_t *p_api; - adpt_api_t *p_adpt_api; - - if((p_adpt_api = adpt_api_ptr_get(dev_id)) != NULL) { - if (NULL == p_adpt_api->adpt_port_fdb_learn_exceed_cmd_get) - return SW_NOT_SUPPORTED; - - rv = p_adpt_api->adpt_port_fdb_learn_exceed_cmd_get(dev_id, port_id, cmd); - return rv; - } - - SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id)); - - if (NULL == p_api->port_fdb_learn_exceed_cmd_get) - return SW_NOT_SUPPORTED; - - rv = p_api->port_fdb_learn_exceed_cmd_get(dev_id, port_id, cmd); - return rv; -} - -static sw_error_t -_fal_fdb_learn_limit_set(a_uint32_t dev_id, a_bool_t enable, a_uint32_t cnt) -{ - sw_error_t rv; - hsl_api_t *p_api; - - SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id)); - - if (NULL == p_api->fdb_learn_limit_set) - return SW_NOT_SUPPORTED; - - rv = p_api->fdb_learn_limit_set(dev_id, enable, cnt); - return rv; -} - -static sw_error_t -_fal_fdb_learn_limit_get(a_uint32_t dev_id, a_bool_t * enable, a_uint32_t * cnt) -{ - sw_error_t rv; - hsl_api_t *p_api; - - SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id)); - - if (NULL == p_api->fdb_learn_limit_get) - return SW_NOT_SUPPORTED; - - rv = p_api->fdb_learn_limit_get(dev_id, enable, cnt); - return rv; -} - -static sw_error_t -_fal_fdb_learn_exceed_cmd_set(a_uint32_t dev_id, fal_fwd_cmd_t cmd) -{ - sw_error_t rv; - hsl_api_t *p_api; - - SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id)); - - if (NULL == p_api->fdb_learn_exceed_cmd_set) - return SW_NOT_SUPPORTED; - - rv = p_api->fdb_learn_exceed_cmd_set(dev_id, cmd); - return rv; -} - -static sw_error_t -_fal_fdb_learn_exceed_cmd_get(a_uint32_t dev_id, fal_fwd_cmd_t * cmd) -{ - sw_error_t rv; - hsl_api_t *p_api; - - SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id)); - - if (NULL == p_api->fdb_learn_exceed_cmd_get) - return SW_NOT_SUPPORTED; - - rv = p_api->fdb_learn_exceed_cmd_get(dev_id, cmd); - return rv; -} - -static sw_error_t -_fal_fdb_resv_add(a_uint32_t dev_id, fal_fdb_entry_t * entry) -{ - sw_error_t rv; - hsl_api_t *p_api; - - SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id)); - - if (NULL == p_api->fdb_resv_add) - return SW_NOT_SUPPORTED; - - rv = p_api->fdb_resv_add(dev_id, entry); - return rv; -} - -static sw_error_t -_fal_fdb_resv_del(a_uint32_t dev_id, fal_fdb_entry_t * entry) -{ - sw_error_t rv; - hsl_api_t *p_api; - - SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id)); - - if (NULL == p_api->fdb_resv_del) - return SW_NOT_SUPPORTED; - - rv = p_api->fdb_resv_del(dev_id, entry); - return rv; -} - -static sw_error_t -_fal_fdb_resv_find(a_uint32_t dev_id, fal_fdb_entry_t * entry) -{ - sw_error_t rv; - hsl_api_t *p_api; - - SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id)); - - if (NULL == p_api->fdb_resv_find) - return SW_NOT_SUPPORTED; - - rv = p_api->fdb_resv_find(dev_id, entry); - return rv; -} - -static sw_error_t -_fal_fdb_resv_iterate(a_uint32_t dev_id, a_uint32_t * iterator, - fal_fdb_entry_t * entry) -{ - sw_error_t rv; - hsl_api_t *p_api; - - SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id)); - - if (NULL == p_api->fdb_resv_iterate) - return SW_NOT_SUPPORTED; - - rv = p_api->fdb_resv_iterate(dev_id, iterator, entry); - return rv; -} - -static sw_error_t -_fal_fdb_port_learn_static_set(a_uint32_t dev_id, fal_port_t port_id, - a_bool_t enable) -{ - sw_error_t rv; - hsl_api_t *p_api; - - SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id)); - - if (NULL == p_api->fdb_port_learn_static_set) - return SW_NOT_SUPPORTED; - - rv = p_api->fdb_port_learn_static_set(dev_id, port_id, enable); - return rv; -} - -static sw_error_t -_fal_fdb_port_learn_static_get(a_uint32_t dev_id, fal_port_t port_id, - a_bool_t * enable) -{ - sw_error_t rv; - hsl_api_t *p_api; - - SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id)); - - if (NULL == p_api->fdb_port_learn_static_get) - return SW_NOT_SUPPORTED; - - rv = p_api->fdb_port_learn_static_get(dev_id, port_id, enable); - return rv; -} - -static sw_error_t -_fal_fdb_port_add(a_uint32_t dev_id, a_uint32_t fid, fal_mac_addr_t * addr, fal_port_t port_id) -{ - sw_error_t rv; - hsl_api_t *p_api; - adpt_api_t *p_adpt_api; - - if((p_adpt_api = adpt_api_ptr_get(dev_id)) != NULL) { - if (NULL == p_adpt_api->adpt_fdb_port_add) - return SW_NOT_SUPPORTED; - - rv = p_adpt_api->adpt_fdb_port_add(dev_id, fid, addr, port_id); - return rv; - } - - SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id)); - - if (NULL == p_api->fdb_port_add) - return SW_NOT_SUPPORTED; - - rv = p_api->fdb_port_add(dev_id, fid, addr, port_id); - return rv; -} - -static sw_error_t -_fal_fdb_port_del(a_uint32_t dev_id, a_uint32_t fid, fal_mac_addr_t * addr, fal_port_t port_id) -{ - sw_error_t rv; - hsl_api_t *p_api; - adpt_api_t *p_adpt_api; - - if((p_adpt_api = adpt_api_ptr_get(dev_id)) != NULL) { - if (NULL == p_adpt_api->adpt_fdb_port_del) - return SW_NOT_SUPPORTED; - - rv = p_adpt_api->adpt_fdb_port_del(dev_id, fid, addr, port_id); - return rv; - } - - SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id)); - - if (NULL == p_api->fdb_port_del) - return SW_NOT_SUPPORTED; - - rv = p_api->fdb_port_del(dev_id, fid, addr, port_id); - return rv; -} - -sw_error_t -_fal_fdb_rfs_set(a_uint32_t dev_id, const fal_fdb_rfs_t * entry) -{ - sw_error_t rv; - hsl_api_t *p_api; - - SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id)); - - if (NULL == p_api->fdb_rfs_set) - return SW_NOT_SUPPORTED; - - rv = p_api->fdb_rfs_set(dev_id, entry); - return rv; -} - -sw_error_t -_fal_fdb_rfs_del(a_uint32_t dev_id, const fal_fdb_rfs_t * entry) -{ - sw_error_t rv; - hsl_api_t *p_api; - - SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id)); - - if (NULL == p_api->fdb_rfs_del) - return SW_NOT_SUPPORTED; - - rv = p_api->fdb_rfs_del(dev_id, entry); - return rv; -} -#endif - -sw_error_t -_fal_fdb_learning_ctrl_set(a_uint32_t dev_id, a_bool_t enable) -{ - adpt_api_t *p_api; - sw_error_t rv = SW_OK; - - SW_RTN_ON_NULL(p_api = adpt_api_ptr_get(dev_id)); - - if (NULL == p_api->adpt_fdb_learn_ctrl_set) - return SW_NOT_SUPPORTED; - - rv = p_api->adpt_fdb_learn_ctrl_set(dev_id, enable); - return rv; -} - -#ifndef IN_FDB_MINI -sw_error_t -_fal_fdb_learning_ctrl_get(a_uint32_t dev_id, a_bool_t * enable) -{ - adpt_api_t *p_api; - sw_error_t rv = SW_OK; - - SW_RTN_ON_NULL(p_api = adpt_api_ptr_get(dev_id)); - - if (NULL == p_api->adpt_fdb_learn_ctrl_get) - return SW_NOT_SUPPORTED; - - rv = p_api->adpt_fdb_learn_ctrl_get(dev_id, enable); - return rv; -} -sw_error_t -_fal_fdb_port_learned_mac_counter_get(a_uint32_t dev_id, fal_port_t port_id, - a_uint32_t * cnt) -{ - adpt_api_t *p_api; - sw_error_t rv = SW_OK; - - SW_RTN_ON_NULL(p_api = adpt_api_ptr_get(dev_id)); - - if (NULL == p_api->adpt_port_fdb_learn_counter_get) - return SW_NOT_SUPPORTED; - - rv = p_api->adpt_port_fdb_learn_counter_get(dev_id, port_id, cnt); - return rv; -} -sw_error_t -_fal_fdb_port_maclimit_ctrl_set(a_uint32_t dev_id, fal_port_t port_id, fal_maclimit_ctrl_t * maclimit_ctrl) -{ - adpt_api_t *p_api; - sw_error_t rv = SW_OK; - - SW_RTN_ON_NULL(p_api = adpt_api_ptr_get(dev_id)); - - if (NULL == p_api->adpt_fdb_port_maclimit_ctrl_set) - return SW_NOT_SUPPORTED; - - rv = p_api->adpt_fdb_port_maclimit_ctrl_set(dev_id, port_id, maclimit_ctrl); - return rv; -} -sw_error_t -_fal_fdb_port_maclimit_ctrl_get(a_uint32_t dev_id, fal_port_t port_id, fal_maclimit_ctrl_t * maclimit_ctrl) -{ - adpt_api_t *p_api; - sw_error_t rv = SW_OK; - - SW_RTN_ON_NULL(p_api = adpt_api_ptr_get(dev_id)); - - if (NULL == p_api->adpt_fdb_port_maclimit_ctrl_get) - return SW_NOT_SUPPORTED; - - rv = p_api->adpt_fdb_port_maclimit_ctrl_get(dev_id, port_id, maclimit_ctrl); - return rv; -} -#endif -sw_error_t -_fal_fdb_entry_del_byfid(a_uint32_t dev_id, a_uint16_t fid, a_uint32_t flag) -{ - adpt_api_t *p_api; - sw_error_t rv = SW_OK; - - SW_RTN_ON_NULL(p_api = adpt_api_ptr_get(dev_id)); - - if (NULL == p_api->adpt_fdb_del_by_fid) - return SW_NOT_SUPPORTED; - - rv = p_api->adpt_fdb_del_by_fid(dev_id, fid, flag); - return rv; -} -#ifndef IN_FDB_MINI -/*insert flag for inner fal, don't remove it*/ - -/** - * @brief Add a Fdb entry - * @param[in] dev_id device id - * @param[in] entry fdb entry - * @return SW_OK or error code - */ -sw_error_t -fal_fdb_entry_add(a_uint32_t dev_id, const fal_fdb_entry_t * entry) -{ - sw_error_t rv; - - FAL_API_LOCK; - rv = _fal_fdb_entry_add(dev_id, entry); - FAL_API_UNLOCK; - return rv; -} -#endif - -/** - * @brief Delete all Fdb entries - * @details Comments: - * If set FAL_FDB_DEL_STATIC bit in flag which means delete all fdb - * entries otherwise only delete dynamic entries. - * @param[in] dev_id device id - * @param[in] flag delete operation option - * @return SW_OK or error code - */ -sw_error_t -fal_fdb_entry_flush(a_uint32_t dev_id, a_uint32_t flag) -{ - sw_error_t rv; - - FAL_API_LOCK; - rv = _fal_fdb_entry_flush(dev_id, flag); - FAL_API_UNLOCK; - return rv; -} - -/** - * @brief Delete Fdb entries on a particular port - * @details Comments: - * If set FAL_FDB_DEL_STATIC bit in flag which means delete all fdb - * entries otherwise only delete dynamic entries. - * @param[in] dev_id device id - * @param[in] port_id port id - * @param[in] flag delete operation option - * @return SW_OK or error code - */ -sw_error_t -fal_fdb_entry_del_byport(a_uint32_t dev_id, fal_port_t port_id, a_uint32_t flag) -{ - sw_error_t rv; - - FAL_API_LOCK; - rv = _fal_fdb_entry_del_byport(dev_id, port_id, flag); - FAL_API_UNLOCK; - return rv; -} - -/** - * @brief Delete a particular Fdb entry through mac address - * @details Comments: - * Only addr field in entry is meaning. For IVL learning vid or fid field - * also is meaning. - * @param[in] dev_id device id - * @param[in] entry fdb entry - * @return SW_OK or error code - */ -sw_error_t -fal_fdb_entry_del_bymac(a_uint32_t dev_id, const fal_fdb_entry_t * entry) -{ - sw_error_t rv; - - FAL_API_LOCK; - rv = _fal_fdb_entry_del_bymac(dev_id, entry); - FAL_API_UNLOCK; - return rv; -} - -/** - * @brief Get first Fdb entry from particular device - * @param[in] dev_id device id - * @param[out] entry fdb entry - * @return SW_OK or error code - */ -sw_error_t -fal_fdb_entry_getfirst(a_uint32_t dev_id, fal_fdb_entry_t * entry) -{ - sw_error_t rv; - - FAL_API_LOCK; - rv = _fal_fdb_entry_getfirst(dev_id, entry); - FAL_API_UNLOCK; - return rv; -} - -#ifndef IN_FDB_MINI -/** - * @brief Get next Fdb entry from particular device - * @details Comments: - For input parameter only addr field in entry is meaning. - * @param[in] dev_id device id - * @param entry fdb entry - * @return SW_OK or error code - */ -sw_error_t -fal_fdb_entry_getnext(a_uint32_t dev_id, fal_fdb_entry_t * entry) -{ - sw_error_t rv; - - FAL_API_LOCK; - rv = _fal_fdb_entry_getnext(dev_id, entry); - FAL_API_UNLOCK; - return rv; -} -#endif - -/** - * @brief Find a particular Fdb entry from device through mac address. - * @details Comments: - For input parameter only addr field in entry is meaning. - * @param[in] dev_id device id - * @param[in] entry fdb entry - * @param[out] entry fdb entry - * @return SW_OK or error code - */ -sw_error_t -fal_fdb_entry_search(a_uint32_t dev_id, fal_fdb_entry_t * entry) -{ - sw_error_t rv; - - FAL_API_LOCK; - rv = _fal_fdb_entry_search(dev_id, entry); - FAL_API_UNLOCK; - return rv; -} - -/** - * @brief Set dynamic address and station move learning status on a particular port. - * @details Comments: - * This operation will enable or disable dynamic address and - * station move learning feature on a particular port. - * @param[in] dev_id device id - * @param[in] port_id port id - * @param[in] enable enable or disable - * @return SW_OK or error code - */ -sw_error_t -fal_fdb_port_learn_set(a_uint32_t dev_id, fal_port_t port_id, a_bool_t enable) -{ - sw_error_t rv; - - FAL_API_LOCK; - rv = _fal_fdb_port_learn_set(dev_id, port_id, enable); - FAL_API_UNLOCK; - return rv; -} - -#ifndef IN_FDB_MINI -/** - * @brief Get dynamic address and station move learning status on a particular port. - * @param[in] dev_id device id - * @param[in] port_id port id - * @param[out] enable A_TRUE or A_FALSE - * @return SW_OK or error code - */ -sw_error_t -fal_fdb_port_learn_get(a_uint32_t dev_id, fal_port_t port_id, a_bool_t * enable) -{ - sw_error_t rv; - - FAL_API_LOCK; - rv = _fal_fdb_port_learn_get(dev_id, port_id, enable); - FAL_API_UNLOCK; - return rv; -} -#endif - -/** - * @brief Set dynamic address learning and forward command on a particular port. - * @param[in] dev_id device id - * @param[in] port_id port id - * @param[in] learning status - * @param[in] forward command - * @return SW_OK or error code - */ -sw_error_t -fal_fdb_port_learning_ctrl_set(a_uint32_t dev_id, fal_port_t port_id, a_bool_t enable, fal_fwd_cmd_t cmd) -{ - sw_error_t rv = SW_OK; - - FAL_API_LOCK; - rv = _fal_fdb_port_learning_ctrl_set(dev_id, port_id, enable, cmd); - FAL_API_UNLOCK; - return rv; -} - -#ifndef IN_FDB_MINI -/** - * @brief Get dynamic address learning and forward command on a particular port. - * @param[in] dev_id device id - * @param[in] port_id port id - * @param[out] learning status - * @param[out] forward command - * @return SW_OK or error code - */ -sw_error_t -fal_fdb_port_learning_ctrl_get(a_uint32_t dev_id, fal_port_t port_id, a_bool_t *enable, fal_fwd_cmd_t *cmd) -{ - sw_error_t rv = SW_OK; - - FAL_API_LOCK; - rv = _fal_fdb_port_learning_ctrl_get(dev_id, port_id, enable, cmd); - FAL_API_UNLOCK; - return rv; -} -#endif - -/** - * @brief Set station move learning and forward command on a particular port. - * @param[in] dev_id device id - * @param[in] port_id port id - * @param[in] learning status - * @param[in] forward command - * @return SW_OK or error code - */ -sw_error_t -fal_fdb_port_stamove_ctrl_set(a_uint32_t dev_id, fal_port_t port_id, a_bool_t enable, fal_fwd_cmd_t cmd) -{ - sw_error_t rv = SW_OK; - - FAL_API_LOCK; - rv = _fal_fdb_port_stamove_ctrl_set(dev_id, port_id, enable, cmd); - FAL_API_UNLOCK; - return rv; -} - -#ifndef IN_FDB_MINI -/** - * @brief Get station move learning and forward command on a particular port. - * @param[in] dev_id device id - * @param[in] port_id port id - * @param[out] learning status - * @param[out] forward command - * @return SW_OK or error code - */ -sw_error_t -fal_fdb_port_stamove_ctrl_get(a_uint32_t dev_id, fal_port_t port_id, a_bool_t *enable, fal_fwd_cmd_t *cmd) -{ - sw_error_t rv = SW_OK; - - FAL_API_LOCK; - rv = _fal_fdb_port_stamove_ctrl_get(dev_id, port_id, enable, cmd); - FAL_API_UNLOCK; - return rv; -} -#endif - -/** - * @brief Set dynamic address aging status on particular device. - * @details Comments: - * This operation will enable or disable dynamic address aging - * feature on particular device. - * @param[in] dev_id device id - * @param[in] enable enable or disable - * @return SW_OK or error code - */ -sw_error_t -fal_fdb_aging_ctrl_set(a_uint32_t dev_id, a_bool_t enable) -{ - sw_error_t rv; - - FAL_API_LOCK; - rv = _fal_fdb_aging_ctrl_set(dev_id, enable); - FAL_API_UNLOCK; - return rv; -} - -#ifndef IN_FDB_MINI -/** - * @brief Get dynamic address aging status on particular device. - * @param[in] dev_id device id - * @param[in] enable enable or disable - * @return SW_OK or error code - */ -sw_error_t -fal_fdb_aging_ctrl_get(a_uint32_t dev_id, a_bool_t * enable) -{ - sw_error_t rv; - - FAL_API_LOCK; - rv = _fal_fdb_aging_ctrl_get(dev_id, enable); - FAL_API_UNLOCK; - return rv; -} - -/** - * @brief set arl search mode as ivl or svl when vlan invalid. - * @param[in] dev_id device id - * @param[in] smode INVALID_VLAN_IVL or INVALID_VLAN_SVL - * @return SW_OK or error code - */ -sw_error_t -fal_fdb_vlan_ivl_svl_set(a_uint32_t dev_id, fal_fdb_smode smode) -{ - sw_error_t rv; - - FAL_API_LOCK; - rv = _fal_fdb_vlan_ivl_svl_set(dev_id, smode); - FAL_API_UNLOCK; - return rv; -} - -/** - * @brief get arl search mode when vlan invalid. - * @param[in] dev_id device id - * @param[out] smode INVALID_VLAN_IVL or INVALID_VLAN_SVL - * @return SW_OK or error code - */ -sw_error_t -fal_fdb_vlan_ivl_svl_get(a_uint32_t dev_id, fal_fdb_smode* smode) -{ - sw_error_t rv; - - FAL_API_LOCK; - rv = _fal_fdb_vlan_ivl_svl_get(dev_id, smode); - FAL_API_UNLOCK; - return rv; -} - - - - -/** - * @brief Set dynamic address aging time on a particular device. - * @details Comments: - * This operation will set dynamic address aging time on a particular device. - * The unit of time is second. Because different device has differnet - * hardware granularity function will return actual time in hardware. - * @param[in] dev_id device id - * @param time aging time - * @return SW_OK or error code - */ -sw_error_t -fal_fdb_aging_time_set(a_uint32_t dev_id, a_uint32_t * time) -{ - sw_error_t rv; - - FAL_API_LOCK; - rv = _fal_fdb_aging_time_set(dev_id, time); - FAL_API_UNLOCK; - return rv; -} - -/** - * @brief Get dynamic address aging time on a particular device. - * @param[in] dev_id device id - * @param[out] time aging time - * @return SW_OK or error code - */ -sw_error_t -fal_fdb_aging_time_get(a_uint32_t dev_id, a_uint32_t * time) -{ - sw_error_t rv; - - FAL_API_LOCK; - rv = _fal_fdb_aging_time_get(dev_id, time); - FAL_API_UNLOCK; - return rv; -} -#endif - -/** - * @brief Iterate all fdb entries on a particular device. - * @param[in] dev_id device id - * @param[in] iterator fdb entry index if it's zero means get the first entry - * @param[out] iterator next valid fdb entry index - * @param[out] entry fdb entry - * @return SW_OK or error code - */ -sw_error_t -fal_fdb_entry_getnext_byindex(a_uint32_t dev_id, a_uint32_t * iterator, fal_fdb_entry_t * entry) -{ - sw_error_t rv; - - FAL_API_LOCK; - rv = _fal_fdb_entry_getnext_byindex(dev_id, iterator, entry); - FAL_API_UNLOCK; - return rv; -} - -/** - * @brief Get next Fdb entry from a particular device - * @param[in] dev_id device id - * @param[in] option next operation options - * @param[out] entry fdb entry - * @return SW_OK or error code - */ -sw_error_t -fal_fdb_entry_extend_getnext(a_uint32_t dev_id, fal_fdb_op_t * option, - fal_fdb_entry_t * entry) -{ - sw_error_t rv; - - FAL_API_LOCK; - rv = _fal_fdb_entry_extend_getnext(dev_id, option, entry); - FAL_API_UNLOCK; - return rv; -} - -/** - * @brief Get first Fdb entry from a particular device - * @param[in] dev_id device id - * @param[in] option first operation options - * @param[out] entry fdb entry - * @return SW_OK or error code - */ -sw_error_t -fal_fdb_entry_extend_getfirst(a_uint32_t dev_id, fal_fdb_op_t * option, - fal_fdb_entry_t * entry) -{ - sw_error_t rv; - - FAL_API_LOCK; - rv = _fal_fdb_entry_extend_getfirst(dev_id, option, entry); - FAL_API_UNLOCK; - return rv; -} - -#ifndef IN_FDB_MINI -/** - * @brief Transfer fdb entries port information on a particular device. - * @param[in] dev_id device id - * @param[in] old_port source port id - * @param[in] new_port destination port id - * @param[in] fid filter database id - * @param[in] option transfer operation options - * @return SW_OK or error code - */ -sw_error_t -fal_fdb_entry_update_byport(a_uint32_t dev_id, fal_port_t old_port, fal_port_t new_port, - a_uint32_t fid, fal_fdb_op_t * option) -{ - sw_error_t rv; - - FAL_API_LOCK; - rv = _fal_fdb_entry_update_byport(dev_id, old_port, new_port, fid, option); - FAL_API_UNLOCK; - return rv; -} - -/** - * @brief Set dynamic address learning count limit on a particular port. - * @param[in] dev_id device id - * @param[in] port_id port id - * @param[in] enable A_TRUE or A_FALSE - * @param[in] cnt limit count - * @return SW_OK or error code - */ -sw_error_t -fal_port_fdb_learn_limit_set(a_uint32_t dev_id, fal_port_t port_id, - a_bool_t enable, a_uint32_t cnt) -{ - sw_error_t rv; - - FAL_API_LOCK; - rv = _fal_port_fdb_learn_limit_set(dev_id, port_id, enable, cnt); - FAL_API_UNLOCK; - return rv; -} - -/** - * @brief Get dynamic address learning count limit on a particular port. - * @param[in] dev_id device id - * @param[in] port_id port id - * @param[out] enable A_TRUE or A_FALSE - * @param[out] cnt limit count - * @return SW_OK or error code - */ -sw_error_t -fal_port_fdb_learn_limit_get(a_uint32_t dev_id, fal_port_t port_id, - a_bool_t * enable, a_uint32_t * cnt) -{ - sw_error_t rv; - - FAL_API_LOCK; - rv = _fal_port_fdb_learn_limit_get(dev_id, port_id, enable, cnt); - FAL_API_UNLOCK; - return rv; -} - -/** - * @brief Set dynamic address learning count exceed command on a particular port. - * @param[in] dev_id device id - * @param[in] port_id port id - * @param[in] cmd forwarding command - * @return SW_OK or error code - */ -sw_error_t -fal_port_fdb_learn_exceed_cmd_set(a_uint32_t dev_id, fal_port_t port_id, - fal_fwd_cmd_t cmd) -{ - sw_error_t rv; - - FAL_API_LOCK; - rv = _fal_port_fdb_learn_exceed_cmd_set(dev_id, port_id, cmd); - FAL_API_UNLOCK; - return rv; -} - -/** - * @brief Get dynamic address learning count exceed command on a particular port. - * @param[in] dev_id device id - * @param[in] port_id port id - * @param[out] cmd forwarding command - * @return SW_OK or error code - */ -sw_error_t -fal_port_fdb_learn_exceed_cmd_get(a_uint32_t dev_id, fal_port_t port_id, - fal_fwd_cmd_t * cmd) -{ - sw_error_t rv; - - FAL_API_LOCK; - rv = _fal_port_fdb_learn_exceed_cmd_get(dev_id, port_id, cmd); - FAL_API_UNLOCK; - return rv; -} - -/** - * @brief Set dynamic address learning count limit on a particular device. - * @param[in] dev_id device id - * @param[in] enable A_TRUE or A_FALSE - * @param[in] cnt limit count - * @return SW_OK or error code - */ -sw_error_t -fal_fdb_learn_limit_set(a_uint32_t dev_id, a_bool_t enable, a_uint32_t cnt) -{ - sw_error_t rv; - - FAL_API_LOCK; - rv = _fal_fdb_learn_limit_set(dev_id, enable, cnt); - FAL_API_UNLOCK; - return rv; -} - -/** - * @brief Get dynamic address learning count limit on a particular device. - * @param[in] dev_id device id - * @param[in] enable A_TRUE or A_FALSE - * @param[in] cnt limit count - * @return SW_OK or error code - */ -sw_error_t -fal_fdb_learn_limit_get(a_uint32_t dev_id, a_bool_t * enable, a_uint32_t * cnt) -{ - sw_error_t rv; - - FAL_API_LOCK; - rv = _fal_fdb_learn_limit_get(dev_id, enable, cnt); - FAL_API_UNLOCK; - return rv; -} - -/** - * @brief Set dynamic address learning count exceed command on a particular device. - * @param[in] dev_id device id - * @param[in] cmd forwarding command - * @return SW_OK or error code - */ -sw_error_t -fal_fdb_learn_exceed_cmd_set(a_uint32_t dev_id, fal_fwd_cmd_t cmd) -{ - sw_error_t rv; - - FAL_API_LOCK; - rv = _fal_fdb_learn_exceed_cmd_set(dev_id, cmd); - FAL_API_UNLOCK; - return rv; -} - -/** - * @brief Get dynamic address learning count exceed command on a particular device. - * @param[in] dev_id device id - * @param[out] cmd forwarding command - * @return SW_OK or error code - */ -sw_error_t -fal_fdb_learn_exceed_cmd_get(a_uint32_t dev_id, fal_fwd_cmd_t * cmd) -{ - sw_error_t rv; - - FAL_API_LOCK; - rv = _fal_fdb_learn_exceed_cmd_get(dev_id, cmd); - FAL_API_UNLOCK; - return rv; -} - -/** - * @brief Add a particular reserve Fdb entry - * @param[in] dev_id device id - * @param[in] entry reserve fdb entry - * @return SW_OK or error code - */ -sw_error_t -fal_fdb_resv_add(a_uint32_t dev_id, fal_fdb_entry_t * entry) -{ - sw_error_t rv; - - FAL_API_LOCK; - rv = _fal_fdb_resv_add(dev_id, entry); - FAL_API_UNLOCK; - return rv; -} - -/** - * @brief Delete a particular reserve Fdb entry through mac address - * @param[in] dev_id device id - * @param[in] entry reserve fdb entry - * @return SW_OK or error code - */ -sw_error_t -fal_fdb_resv_del(a_uint32_t dev_id, fal_fdb_entry_t * entry) -{ - sw_error_t rv; - - FAL_API_LOCK; - rv = _fal_fdb_resv_del(dev_id, entry); - FAL_API_UNLOCK; - return rv; -} - -/** - * @brief Find a particular reserve Fdb entry through mac address - * @param[in] dev_id device id - * @param[in] entry reserve fdb entry - * @param[out] entry reserve fdb entry - * @return SW_OK or error code - */ -sw_error_t -fal_fdb_resv_find(a_uint32_t dev_id, fal_fdb_entry_t * entry) -{ - sw_error_t rv; - - FAL_API_LOCK; - rv = _fal_fdb_resv_find(dev_id, entry); - FAL_API_UNLOCK; - return rv; -} - -/** - * @brief Iterate all reserve fdb entries on a particular device. - * @param[in] dev_id device id - * @param[in] iterator reserve fdb entry index if it's zero means get the first entry - * @param[out] iterator next valid fdb entry index - * @param[out] entry reserve fdb entry - * @return SW_OK or error code - */ -sw_error_t -fal_fdb_resv_iterate(a_uint32_t dev_id, a_uint32_t * iterator, - fal_fdb_entry_t * entry) -{ - sw_error_t rv; - - FAL_API_LOCK; - rv = _fal_fdb_resv_iterate(dev_id, iterator, entry); - FAL_API_UNLOCK; - return rv; -} - -sw_error_t -fal_fdb_port_learn_static_set(a_uint32_t dev_id, fal_port_t port_id, - a_bool_t enable) -{ - sw_error_t rv; - - FAL_API_LOCK; - rv = _fal_fdb_port_learn_static_set(dev_id, port_id, enable); - FAL_API_UNLOCK; - return rv; -} - -sw_error_t -fal_fdb_port_learn_static_get(a_uint32_t dev_id, fal_port_t port_id, - a_bool_t * enable) -{ - sw_error_t rv; - - FAL_API_LOCK; - rv = _fal_fdb_port_learn_static_get(dev_id, port_id, enable); - FAL_API_UNLOCK; - return rv; -} - -/** - * @brief Add a port to an exsiting entry - * @param[in] dev_id device id - * @param[in] fid filtering database id - * @param[in] addr MAC address - * @param[in] port_id port id - * @return SW_OK or error code, If entry not exist will return error. - */ -sw_error_t -fal_fdb_port_add(a_uint32_t dev_id, a_uint32_t fid, fal_mac_addr_t * addr, fal_port_t port_id) -{ - sw_error_t rv; - - FAL_API_LOCK; - rv = _fal_fdb_port_add(dev_id, fid, addr, port_id); - FAL_API_UNLOCK; - return rv; -} - -/** - * @brief Delete a port from an exsiting entry - * @param[in] dev_id device id - * @param[in] fid filtering database id - * @param[in] addr MAC address - * @param[in] port_id port id - * @return SW_OK or error code, If entry not exist will return error. - */ -sw_error_t -fal_fdb_port_del(a_uint32_t dev_id, a_uint32_t fid, fal_mac_addr_t * addr, fal_port_t port_id) -{ - sw_error_t rv; - - FAL_API_LOCK; - rv = _fal_fdb_port_del(dev_id, fid, addr, port_id); - FAL_API_UNLOCK; - return rv; -} - -/** - * @brief Add a Fdb rfs entry - * @param[in] dev_id device id - * @param[in] entry fdb entry - * @return SW_OK or error code - */ -sw_error_t -fal_fdb_rfs_set(a_uint32_t dev_id, const fal_fdb_rfs_t * entry) -{ - sw_error_t rv; - - FAL_API_LOCK; - rv = _fal_fdb_rfs_set(dev_id, entry); - FAL_API_UNLOCK; - return rv; -} - -/** - * @brief Del a Fdb rfs entry - * @param[in] dev_id device id - * @param[in] entry fdb entry - * @return SW_OK or error code - */ -sw_error_t -fal_fdb_rfs_del(a_uint32_t dev_id, const fal_fdb_rfs_t * entry) -{ - sw_error_t rv; - - FAL_API_LOCK; - rv = _fal_fdb_rfs_del(dev_id, entry); - FAL_API_UNLOCK; - return rv; -} - -int ssdk_rfs_mac_rule_set(u16 vid, u8* mac, u8 ldb, int is_set) -{ - fal_fdb_rfs_t entry; - memcpy(&entry.addr, mac, 6); - entry.fid = vid; - entry.load_balance = ldb; - if(is_set) - return fal_fdb_rfs_set(0, &entry); - else - return fal_fdb_rfs_del(0, &entry); -} -#endif - -#if 0 -int ssdk_rfs_mac_rule_set(ssdk_fdb_rfs_t *rfs) -{ - fal_fdb_rfs_t entry; - memcpy(&entry.addr, rfs->addr, 6); - entry.fid = rfs->fid; - entry.load_balance = rfs->load_balance; - return fal_fdb_rfs_set(0, &entry); -} - -int ssdk_rfs_mac_rule_del(ssdk_fdb_rfs_t *rfs) -{ - fal_fdb_rfs_t entry; - memcpy(&entry.addr, rfs->addr, 6); - entry.fid = rfs->fid; - entry.load_balance = rfs->load_balance; - return fal_fdb_rfs_del(0, &entry); -} - - -EXPORT_SYMBOL(ssdk_rfs_mac_rule_set); -EXPORT_SYMBOL(ssdk_rfs_mac_rule_del); -#endif - -sw_error_t -fal_fdb_learning_ctrl_set(a_uint32_t dev_id, a_bool_t enable) -{ - sw_error_t rv = SW_OK; - - FAL_API_LOCK; - rv = _fal_fdb_learning_ctrl_set(dev_id, enable); - FAL_API_UNLOCK; - return rv; -} - -#ifndef IN_FDB_MINI -sw_error_t -fal_fdb_learning_ctrl_get(a_uint32_t dev_id, a_bool_t * enable) -{ - sw_error_t rv = SW_OK; - - FAL_API_LOCK; - rv = _fal_fdb_learning_ctrl_get(dev_id, enable); - FAL_API_UNLOCK; - return rv; -} -sw_error_t -fal_fdb_port_learned_mac_counter_get(a_uint32_t dev_id, fal_port_t port_id, - a_uint32_t * cnt) -{ - sw_error_t rv = SW_OK; - - FAL_API_LOCK; - rv = _fal_fdb_port_learned_mac_counter_get(dev_id, port_id, cnt); - FAL_API_UNLOCK; - return rv; -} -sw_error_t -fal_fdb_port_maclimit_ctrl_set(a_uint32_t dev_id, fal_port_t port_id, fal_maclimit_ctrl_t * maclimit_ctrl) -{ - sw_error_t rv = SW_OK; - - FAL_API_LOCK; - rv = _fal_fdb_port_maclimit_ctrl_set(dev_id, port_id, maclimit_ctrl); - FAL_API_UNLOCK; - return rv; -} -sw_error_t -fal_fdb_port_maclimit_ctrl_get(a_uint32_t dev_id, fal_port_t port_id, fal_maclimit_ctrl_t * maclimit_ctrl) -{ - sw_error_t rv = SW_OK; - - FAL_API_LOCK; - rv = _fal_fdb_port_maclimit_ctrl_get(dev_id, port_id, maclimit_ctrl); - FAL_API_UNLOCK; - return rv; -} -#endif -sw_error_t -fal_fdb_entry_del_byfid(a_uint32_t dev_id, a_uint16_t fid, a_uint32_t flag) -{ - sw_error_t rv = SW_OK; - - FAL_API_LOCK; - rv = _fal_fdb_entry_del_byfid(dev_id, fid, flag); - FAL_API_UNLOCK; - return rv; -} - -#ifndef IN_FDB_MINI - - EXPORT_SYMBOL(fal_fdb_entry_add); - -#endif - - EXPORT_SYMBOL(fal_fdb_entry_del_byport); - - - EXPORT_SYMBOL(fal_fdb_entry_del_bymac); - - - EXPORT_SYMBOL(fal_fdb_entry_search); - -#ifndef IN_FDB_MINI - - EXPORT_SYMBOL(fal_fdb_port_learn_get); - -#endif - - EXPORT_SYMBOL(fal_fdb_port_learning_ctrl_set); - - EXPORT_SYMBOL(fal_fdb_entry_flush); - - EXPORT_SYMBOL(fal_fdb_entry_getfirst); - -#ifndef IN_FDB_MINI - - EXPORT_SYMBOL(fal_fdb_entry_getnext); - -#endif - - EXPORT_SYMBOL(fal_fdb_port_learn_set); - - EXPORT_SYMBOL(fal_fdb_learning_ctrl_set); - -#ifndef IN_FDB_MINI - - EXPORT_SYMBOL(fal_fdb_learning_ctrl_get); - -#endif - - EXPORT_SYMBOL(fal_fdb_entry_getnext_byindex); - - EXPORT_SYMBOL(fal_fdb_entry_extend_getnext); - - EXPORT_SYMBOL(fal_fdb_entry_extend_getfirst); - -#ifndef IN_FDB_MINI - - EXPORT_SYMBOL(fal_fdb_port_learning_ctrl_get); - -#endif - - EXPORT_SYMBOL(fal_fdb_port_stamove_ctrl_set); - -#ifndef IN_FDB_MINI - - EXPORT_SYMBOL(fal_fdb_port_stamove_ctrl_get); - -#endif - - EXPORT_SYMBOL(fal_fdb_aging_ctrl_set); - -#ifndef IN_FDB_MINI - - EXPORT_SYMBOL(fal_fdb_aging_ctrl_get); - - EXPORT_SYMBOL(fal_fdb_aging_time_set); - - EXPORT_SYMBOL(fal_fdb_aging_time_get); - - EXPORT_SYMBOL(fal_fdb_entry_update_byport); - - EXPORT_SYMBOL(fal_port_fdb_learn_limit_set); - - EXPORT_SYMBOL(fal_port_fdb_learn_limit_get); - - EXPORT_SYMBOL(fal_port_fdb_learn_exceed_cmd_set); - - EXPORT_SYMBOL(fal_port_fdb_learn_exceed_cmd_get); - - EXPORT_SYMBOL(fal_fdb_port_add); - - EXPORT_SYMBOL(fal_fdb_port_del); - - EXPORT_SYMBOL(fal_fdb_port_maclimit_ctrl_set); - - EXPORT_SYMBOL(fal_fdb_port_maclimit_ctrl_get); - -#endif - - EXPORT_SYMBOL(fal_fdb_entry_del_byfid); - -#ifndef IN_FDB_MINI - - EXPORT_SYMBOL(fal_fdb_port_learned_mac_counter_get); - -#endif - -/*insert flag for outter fal, don't remove it*/ - -/** - * @} - */ - diff --git a/feeds/ipq807x/qca-ssdk/src/src/fal/fal_flow.c b/feeds/ipq807x/qca-ssdk/src/src/fal/fal_flow.c deleted file mode 100755 index 4178e7d12..000000000 --- a/feeds/ipq807x/qca-ssdk/src/src/fal/fal_flow.c +++ /dev/null @@ -1,467 +0,0 @@ -/* - * Copyright (c) 2016-2017, The Linux Foundation. All rights reserved. - * Permission to use, copy, modify, and/or distribute this software for - * any purpose with or without fee is hereby granted, provided that the - * above copyright notice and this permission notice appear in all copies. - * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES - * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR - * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES - * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN - * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT - * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. - */ - - -/** - * @defgroup fal_flow FAL_FLOW - * @{ - */ -#include "sw.h" -#include "fal_flow.h" -#include "hsl_api.h" -#include "adpt.h" - -#ifndef IN_FLOW_MINI -sw_error_t -_fal_flow_host_add( - a_uint32_t dev_id, - a_uint32_t add_mode, - fal_flow_host_entry_t *flow_host_entry) -{ - adpt_api_t *p_api; - sw_error_t rv = SW_OK; - - SW_RTN_ON_NULL(p_api = adpt_api_ptr_get(dev_id)); - - if (NULL == p_api->adpt_flow_host_add) - return SW_NOT_SUPPORTED; - - rv = p_api->adpt_flow_host_add(dev_id, add_mode, flow_host_entry); - return rv; -} -sw_error_t -_fal_flow_entry_get( - a_uint32_t dev_id, - a_uint32_t get_mode, - fal_flow_entry_t *flow_entry) -{ - adpt_api_t *p_api; - sw_error_t rv = SW_OK; - - SW_RTN_ON_NULL(p_api = adpt_api_ptr_get(dev_id)); - - if (NULL == p_api->adpt_flow_entry_get) - return SW_NOT_SUPPORTED; - - rv = p_api->adpt_flow_entry_get(dev_id, get_mode, flow_entry); - return rv; -} -sw_error_t -_fal_flow_entry_del( - a_uint32_t dev_id, - a_uint32_t del_mode, - fal_flow_entry_t *flow_entry) -{ - adpt_api_t *p_api; - sw_error_t rv = SW_OK; - - SW_RTN_ON_NULL(p_api = adpt_api_ptr_get(dev_id)); - - if (NULL == p_api->adpt_flow_entry_del) - return SW_NOT_SUPPORTED; - - rv = p_api->adpt_flow_entry_del(dev_id, del_mode, flow_entry); - return rv; -} -sw_error_t -_fal_flow_entry_next( - a_uint32_t dev_id, - a_uint32_t next_mode, - fal_flow_entry_t *flow_entry) -{ - adpt_api_t *p_api; - sw_error_t rv = SW_OK; - - SW_RTN_ON_NULL(p_api = adpt_api_ptr_get(dev_id)); - - if (NULL == p_api->adpt_flow_entry_next) - return SW_NOT_SUPPORTED; - - rv = p_api->adpt_flow_entry_next(dev_id, next_mode, flow_entry); - return rv; -} -sw_error_t -_fal_flow_status_get(a_uint32_t dev_id, a_bool_t *enable) -{ - adpt_api_t *p_api; - sw_error_t rv = SW_OK; - - SW_RTN_ON_NULL(p_api = adpt_api_ptr_get(dev_id)); - - if (NULL == p_api->adpt_flow_status_get) - return SW_NOT_SUPPORTED; - - rv = p_api->adpt_flow_status_get(dev_id, enable); - return rv; -} -#endif -sw_error_t -_fal_flow_mgmt_set( - a_uint32_t dev_id, - fal_flow_pkt_type_t type, - fal_flow_direction_t dir, - fal_flow_mgmt_t *mgmt) -{ - adpt_api_t *p_api; - sw_error_t rv = SW_OK; - - SW_RTN_ON_NULL(p_api = adpt_api_ptr_get(dev_id)); - - if (NULL == p_api->adpt_flow_ctrl_set) - return SW_NOT_SUPPORTED; - - rv = p_api->adpt_flow_ctrl_set(dev_id, type, dir, mgmt); - return rv; -} -#ifndef IN_FLOW_MINI -sw_error_t -_fal_flow_age_timer_get(a_uint32_t dev_id, fal_flow_age_timer_t *age_timer) -{ - adpt_api_t *p_api; - sw_error_t rv = SW_OK; - - SW_RTN_ON_NULL(p_api = adpt_api_ptr_get(dev_id)); - - if (NULL == p_api->adpt_flow_age_timer_get) - return SW_NOT_SUPPORTED; - - rv = p_api->adpt_flow_age_timer_get(dev_id, age_timer); - return rv; -} -sw_error_t -_fal_flow_status_set(a_uint32_t dev_id, a_bool_t enable) -{ - adpt_api_t *p_api; - sw_error_t rv = SW_OK; - - SW_RTN_ON_NULL(p_api = adpt_api_ptr_get(dev_id)); - - if (NULL == p_api->adpt_flow_status_set) - return SW_NOT_SUPPORTED; - - rv = p_api->adpt_flow_status_set(dev_id, enable); - return rv; -} -sw_error_t -_fal_flow_host_get( - a_uint32_t dev_id, - a_uint32_t get_mode, - fal_flow_host_entry_t *flow_host_entry) -{ - adpt_api_t *p_api; - sw_error_t rv = SW_OK; - - SW_RTN_ON_NULL(p_api = adpt_api_ptr_get(dev_id)); - - if (NULL == p_api->adpt_flow_host_get) - return SW_NOT_SUPPORTED; - - rv = p_api->adpt_flow_host_get(dev_id, get_mode, flow_host_entry); - return rv; -} -sw_error_t -_fal_flow_host_del( - a_uint32_t dev_id, - a_uint32_t del_mode, - fal_flow_host_entry_t *flow_host_entry) -{ - adpt_api_t *p_api; - sw_error_t rv = SW_OK; - - SW_RTN_ON_NULL(p_api = adpt_api_ptr_get(dev_id)); - - if (NULL == p_api->adpt_flow_host_del) - return SW_NOT_SUPPORTED; - - rv = p_api->adpt_flow_host_del(dev_id, del_mode, flow_host_entry); - return rv; -} -#endif -sw_error_t -_fal_flow_mgmt_get( - a_uint32_t dev_id, - fal_flow_pkt_type_t type, - fal_flow_direction_t dir, - fal_flow_mgmt_t *mgmt) -{ - adpt_api_t *p_api; - sw_error_t rv = SW_OK; - - SW_RTN_ON_NULL(p_api = adpt_api_ptr_get(dev_id)); - - if (NULL == p_api->adpt_flow_ctrl_get) - return SW_NOT_SUPPORTED; - - rv = p_api->adpt_flow_ctrl_get(dev_id, type, dir, mgmt); - return rv; -} -#ifndef IN_FLOW_MINI -sw_error_t -_fal_flow_age_timer_set(a_uint32_t dev_id, fal_flow_age_timer_t *age_timer) -{ - adpt_api_t *p_api; - sw_error_t rv = SW_OK; - - SW_RTN_ON_NULL(p_api = adpt_api_ptr_get(dev_id)); - - if (NULL == p_api->adpt_flow_age_timer_set) - return SW_NOT_SUPPORTED; - - rv = p_api->adpt_flow_age_timer_set(dev_id, age_timer); - return rv; -} -sw_error_t -_fal_flow_entry_add( - a_uint32_t dev_id, - a_uint32_t add_mode, /*index or hash*/ - fal_flow_entry_t *flow_entry) -{ - adpt_api_t *p_api; - sw_error_t rv = SW_OK; - - SW_RTN_ON_NULL(p_api = adpt_api_ptr_get(dev_id)); - - if (NULL == p_api->adpt_flow_entry_add) - return SW_NOT_SUPPORTED; - - rv = p_api->adpt_flow_entry_add(dev_id, add_mode, flow_entry); - return rv; -} - -sw_error_t -_fal_flow_global_cfg_get( - a_uint32_t dev_id, - fal_flow_global_cfg_t *cfg) -{ - adpt_api_t *p_api; - sw_error_t rv = SW_OK; - - SW_RTN_ON_NULL(p_api = adpt_api_ptr_get(dev_id)); - - if (NULL == p_api->adpt_flow_global_cfg_get) - return SW_NOT_SUPPORTED; - - rv = p_api->adpt_flow_global_cfg_get(dev_id, cfg); - return rv; -} - -sw_error_t -_fal_flow_global_cfg_set( - a_uint32_t dev_id, - fal_flow_global_cfg_t *cfg) -{ - adpt_api_t *p_api; - sw_error_t rv = SW_OK; - - SW_RTN_ON_NULL(p_api = adpt_api_ptr_get(dev_id)); - - if (NULL == p_api->adpt_flow_global_cfg_set) - return SW_NOT_SUPPORTED; - - rv = p_api->adpt_flow_global_cfg_set(dev_id, cfg); - return rv; -} -/*insert flag for inner fal, don't remove it*/ - -sw_error_t -fal_flow_host_add( - a_uint32_t dev_id, - a_uint32_t add_mode, - fal_flow_host_entry_t *flow_host_entry) -{ - sw_error_t rv = SW_OK; - - FAL_API_LOCK; - rv = _fal_flow_host_add(dev_id, add_mode, flow_host_entry); - FAL_API_UNLOCK; - return rv; -} -sw_error_t -fal_flow_entry_get( - a_uint32_t dev_id, - a_uint32_t get_mode, - fal_flow_entry_t *flow_entry) -{ - sw_error_t rv = SW_OK; - - FAL_API_LOCK; - rv = _fal_flow_entry_get(dev_id, get_mode, flow_entry); - FAL_API_UNLOCK; - return rv; -} -sw_error_t -fal_flow_entry_del( - a_uint32_t dev_id, - a_uint32_t del_mode, - fal_flow_entry_t *flow_entry) -{ - sw_error_t rv = SW_OK; - - FAL_API_LOCK; - rv = _fal_flow_entry_del(dev_id, del_mode, flow_entry); - FAL_API_UNLOCK; - return rv; -} -sw_error_t -fal_flow_entry_next( - a_uint32_t dev_id, - a_uint32_t next_mode, - fal_flow_entry_t *flow_entry) -{ - sw_error_t rv = SW_OK; - - FAL_API_LOCK; - rv = _fal_flow_entry_next(dev_id, next_mode, flow_entry); - FAL_API_UNLOCK; - return rv; -} -sw_error_t -fal_flow_status_get(a_uint32_t dev_id, a_bool_t *enable) -{ - sw_error_t rv = SW_OK; - - FAL_API_LOCK; - rv = _fal_flow_status_get(dev_id, enable); - FAL_API_UNLOCK; - return rv; -} -#endif -sw_error_t -fal_flow_mgmt_set( - a_uint32_t dev_id, - fal_flow_pkt_type_t type, - fal_flow_direction_t dir, - fal_flow_mgmt_t *mgmt) -{ - sw_error_t rv = SW_OK; - - FAL_API_LOCK; - rv = _fal_flow_mgmt_set(dev_id, type, dir, mgmt); - FAL_API_UNLOCK; - return rv; -} -#ifndef IN_FLOW_MINI -sw_error_t -fal_flow_age_timer_get(a_uint32_t dev_id, fal_flow_age_timer_t *age_timer) -{ - sw_error_t rv = SW_OK; - - FAL_API_LOCK; - rv = _fal_flow_age_timer_get(dev_id, age_timer); - FAL_API_UNLOCK; - return rv; -} -sw_error_t -fal_flow_status_set(a_uint32_t dev_id, a_bool_t enable) -{ - sw_error_t rv = SW_OK; - - FAL_API_LOCK; - rv = _fal_flow_status_set(dev_id, enable); - FAL_API_UNLOCK; - return rv; -} -sw_error_t -fal_flow_host_get( - a_uint32_t dev_id, - a_uint32_t get_mode, - fal_flow_host_entry_t *flow_host_entry) -{ - sw_error_t rv = SW_OK; - - FAL_API_LOCK; - rv = _fal_flow_host_get(dev_id, get_mode, flow_host_entry); - FAL_API_UNLOCK; - return rv; -} -sw_error_t -fal_flow_host_del( - a_uint32_t dev_id, - a_uint32_t del_mode, - fal_flow_host_entry_t *flow_host_entry) -{ - sw_error_t rv = SW_OK; - - FAL_API_LOCK; - rv = _fal_flow_host_del(dev_id, del_mode, flow_host_entry); - FAL_API_UNLOCK; - return rv; -} -#endif -sw_error_t -fal_flow_mgmt_get( - a_uint32_t dev_id, - fal_flow_pkt_type_t type, - fal_flow_direction_t dir, - fal_flow_mgmt_t *mgmt) -{ - sw_error_t rv = SW_OK; - - FAL_API_LOCK; - rv = _fal_flow_mgmt_get(dev_id, type, dir, mgmt); - FAL_API_UNLOCK; - return rv; -} -#ifndef IN_FLOW_MINI -sw_error_t -fal_flow_age_timer_set(a_uint32_t dev_id, fal_flow_age_timer_t *age_timer) -{ - sw_error_t rv = SW_OK; - - FAL_API_LOCK; - rv = _fal_flow_age_timer_set(dev_id, age_timer); - FAL_API_UNLOCK; - return rv; -} -sw_error_t -fal_flow_entry_add( - a_uint32_t dev_id, - a_uint32_t add_mode, /*index or hash*/ - fal_flow_entry_t *flow_entry) -{ - sw_error_t rv = SW_OK; - - FAL_API_LOCK; - rv = _fal_flow_entry_add(dev_id, add_mode, flow_entry); - FAL_API_UNLOCK; - return rv; -} - -sw_error_t -fal_flow_global_cfg_get( - a_uint32_t dev_id, - fal_flow_global_cfg_t *cfg) -{ - sw_error_t rv = SW_OK; - - FAL_API_LOCK; - rv = _fal_flow_global_cfg_get(dev_id, cfg); - FAL_API_UNLOCK; - return rv; -} - -sw_error_t -fal_flow_global_cfg_set( - a_uint32_t dev_id, - fal_flow_global_cfg_t *cfg) -{ - sw_error_t rv = SW_OK; - - FAL_API_LOCK; - rv = _fal_flow_global_cfg_set(dev_id, cfg); - FAL_API_UNLOCK; - return rv; -} -#endif -/*insert flag for outter fal, don't remove it*/ diff --git a/feeds/ipq807x/qca-ssdk/src/src/fal/fal_igmp.c b/feeds/ipq807x/qca-ssdk/src/src/fal/fal_igmp.c deleted file mode 100755 index c861fc879..000000000 --- a/feeds/ipq807x/qca-ssdk/src/src/fal/fal_igmp.c +++ /dev/null @@ -1,961 +0,0 @@ -/* - * Copyright (c) 2012, The Linux Foundation. All rights reserved. - * Permission to use, copy, modify, and/or distribute this software for - * any purpose with or without fee is hereby granted, provided that the - * above copyright notice and this permission notice appear in all copies. - * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES - * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR - * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES - * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN - * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT - * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. - */ - - - -/** -* @defgroup fal_igmp FAL_IGMP -* @{ -*/ -#include "sw.h" -#include "fal_igmp.h" -#include "hsl_api.h" - -static sw_error_t -_fal_port_igmps_status_set(a_uint32_t dev_id, fal_port_t port_id, a_bool_t enable) -{ - sw_error_t rv; - hsl_api_t *p_api; - - SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id)); - - if (NULL == p_api->port_igmps_status_set) - return SW_NOT_SUPPORTED; - - rv = p_api->port_igmps_status_set(dev_id, port_id, enable); - return rv; -} - - -static sw_error_t -_fal_port_igmps_status_get(a_uint32_t dev_id, fal_port_t port_id, a_bool_t *enable) -{ - sw_error_t rv; - hsl_api_t *p_api; - - SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id)); - - if (NULL == p_api->port_igmps_status_get) - return SW_NOT_SUPPORTED; - - rv = p_api->port_igmps_status_get(dev_id, port_id, enable); - return rv; -} - - -static sw_error_t -_fal_igmp_mld_cmd_set(a_uint32_t dev_id, fal_fwd_cmd_t cmd) -{ - sw_error_t rv; - hsl_api_t *p_api; - - SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id)); - - if (NULL == p_api->igmp_mld_cmd_set) - return SW_NOT_SUPPORTED; - - rv = p_api->igmp_mld_cmd_set(dev_id, cmd); - return rv; -} - - -static sw_error_t -_fal_igmp_mld_cmd_get(a_uint32_t dev_id, fal_fwd_cmd_t * cmd) -{ - sw_error_t rv; - hsl_api_t *p_api; - - SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id)); - - if (NULL == p_api->igmp_mld_cmd_get) - return SW_NOT_SUPPORTED; - - rv = p_api->igmp_mld_cmd_get(dev_id, cmd); - return rv; -} - - -static sw_error_t -_fal_port_igmp_mld_join_set(a_uint32_t dev_id, fal_port_t port_id, a_bool_t enable) -{ - sw_error_t rv; - hsl_api_t *p_api; - - SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id)); - - if (NULL == p_api->port_igmp_join_set) - return SW_NOT_SUPPORTED; - - rv = p_api->port_igmp_join_set(dev_id, port_id, enable); - return rv; -} - - -static sw_error_t -_fal_port_igmp_mld_join_get(a_uint32_t dev_id, fal_port_t port_id, a_bool_t * enable) -{ - sw_error_t rv; - hsl_api_t *p_api; - - SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id)); - - if (NULL == p_api->port_igmp_join_get) - return SW_NOT_SUPPORTED; - - rv = p_api->port_igmp_join_get(dev_id, port_id, enable); - return rv; -} - - -static sw_error_t -_fal_port_igmp_mld_leave_set(a_uint32_t dev_id, fal_port_t port_id, a_bool_t enable) -{ - sw_error_t rv; - hsl_api_t *p_api; - - SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id)); - - if (NULL == p_api->port_igmp_leave_set) - return SW_NOT_SUPPORTED; - - rv = p_api->port_igmp_leave_set(dev_id, port_id, enable); - return rv; -} - - -static sw_error_t -_fal_port_igmp_mld_leave_get(a_uint32_t dev_id, fal_port_t port_id, a_bool_t * enable) -{ - sw_error_t rv; - hsl_api_t *p_api; - - SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id)); - - if (NULL == p_api->port_igmp_leave_get) - return SW_NOT_SUPPORTED; - - rv = p_api->port_igmp_leave_get(dev_id, port_id, enable); - return rv; -} - - -static sw_error_t -_fal_igmp_mld_rp_set(a_uint32_t dev_id, fal_pbmp_t pts) -{ - sw_error_t rv; - hsl_api_t *p_api; - - SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id)); - - if (NULL == p_api->igmp_rp_set) - return SW_NOT_SUPPORTED; - - rv = p_api->igmp_rp_set(dev_id, pts); - return rv; -} - - -static sw_error_t -_fal_igmp_mld_rp_get(a_uint32_t dev_id, fal_pbmp_t * pts) -{ - sw_error_t rv; - hsl_api_t *p_api; - - SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id)); - - if (NULL == p_api->igmp_rp_get) - return SW_NOT_SUPPORTED; - - rv = p_api->igmp_rp_get(dev_id, pts); - return rv; -} - - -static sw_error_t -_fal_igmp_mld_entry_creat_set(a_uint32_t dev_id, a_bool_t enable) -{ - sw_error_t rv; - hsl_api_t *p_api; - - SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id)); - - if (NULL == p_api->igmp_entry_creat_set) - return SW_NOT_SUPPORTED; - - rv = p_api->igmp_entry_creat_set(dev_id, enable); - return rv; -} - - -static sw_error_t -_fal_igmp_mld_entry_creat_get(a_uint32_t dev_id, a_bool_t * enable) -{ - sw_error_t rv; - hsl_api_t *p_api; - - SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id)); - - if (NULL == p_api->igmp_entry_creat_get) - return SW_NOT_SUPPORTED; - - rv = p_api->igmp_entry_creat_get(dev_id, enable); - return rv; -} - -static sw_error_t -_fal_igmp_mld_entry_static_set(a_uint32_t dev_id, a_bool_t enable) -{ - sw_error_t rv; - hsl_api_t *p_api; - - SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id)); - - if (NULL == p_api->igmp_entry_static_set) - return SW_NOT_SUPPORTED; - - rv = p_api->igmp_entry_static_set(dev_id, enable); - return rv; -} - -static sw_error_t -_fal_igmp_mld_entry_static_get(a_uint32_t dev_id, a_bool_t * enable) -{ - sw_error_t rv; - hsl_api_t *p_api; - - SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id)); - - if (NULL == p_api->igmp_entry_static_get) - return SW_NOT_SUPPORTED; - - rv = p_api->igmp_entry_static_get(dev_id, enable); - return rv; -} - -static sw_error_t -_fal_igmp_mld_entry_leaky_set(a_uint32_t dev_id, a_bool_t enable) -{ - sw_error_t rv; - hsl_api_t *p_api; - - SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id)); - - if (NULL == p_api->igmp_entry_leaky_set) - return SW_NOT_SUPPORTED; - - rv = p_api->igmp_entry_leaky_set(dev_id, enable); - return rv; -} - -static sw_error_t -_fal_igmp_mld_entry_leaky_get(a_uint32_t dev_id, a_bool_t * enable) -{ - sw_error_t rv; - hsl_api_t *p_api; - - SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id)); - - if (NULL == p_api->igmp_entry_leaky_get) - return SW_NOT_SUPPORTED; - - rv = p_api->igmp_entry_leaky_get(dev_id, enable); - return rv; -} - -static sw_error_t -_fal_igmp_mld_entry_v3_set(a_uint32_t dev_id, a_bool_t enable) -{ - sw_error_t rv; - hsl_api_t *p_api; - - SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id)); - - if (NULL == p_api->igmp_entry_v3_set) - return SW_NOT_SUPPORTED; - - rv = p_api->igmp_entry_v3_set(dev_id, enable); - return rv; -} - -static sw_error_t -_fal_igmp_mld_entry_v3_get(a_uint32_t dev_id, a_bool_t * enable) -{ - sw_error_t rv; - hsl_api_t *p_api; - - SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id)); - - if (NULL == p_api->igmp_entry_v3_get) - return SW_NOT_SUPPORTED; - - rv = p_api->igmp_entry_v3_get(dev_id, enable); - return rv; -} - -static sw_error_t -_fal_igmp_mld_entry_queue_set(a_uint32_t dev_id, a_bool_t enable, a_uint32_t queue) -{ - sw_error_t rv; - hsl_api_t *p_api; - - SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id)); - - if (NULL == p_api->igmp_entry_queue_set) - return SW_NOT_SUPPORTED; - - rv = p_api->igmp_entry_queue_set(dev_id, enable, queue); - return rv; -} - -static sw_error_t -_fal_igmp_mld_entry_queue_get(a_uint32_t dev_id, a_bool_t * enable, a_uint32_t * queue) -{ - sw_error_t rv; - hsl_api_t *p_api; - - SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id)); - - if (NULL == p_api->igmp_entry_queue_get) - return SW_NOT_SUPPORTED; - - rv = p_api->igmp_entry_queue_get(dev_id, enable, queue); - return rv; -} - -static sw_error_t -_fal_port_igmp_mld_learn_limit_set(a_uint32_t dev_id, fal_port_t port_id, - a_bool_t enable, a_uint32_t cnt) -{ - sw_error_t rv; - hsl_api_t *p_api; - - SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id)); - - if (NULL == p_api->port_igmp_mld_learn_limit_set) - return SW_NOT_SUPPORTED; - - rv = p_api->port_igmp_mld_learn_limit_set(dev_id, port_id, enable, cnt); - return rv; -} - -static sw_error_t -_fal_port_igmp_mld_learn_limit_get(a_uint32_t dev_id, fal_port_t port_id, - a_bool_t * enable, a_uint32_t * cnt) -{ - sw_error_t rv; - hsl_api_t *p_api; - - SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id)); - - if (NULL == p_api->port_igmp_mld_learn_limit_get) - return SW_NOT_SUPPORTED; - - rv = p_api->port_igmp_mld_learn_limit_get(dev_id, port_id, enable, cnt); - return rv; -} - -static sw_error_t -_fal_port_igmp_mld_learn_exceed_cmd_set(a_uint32_t dev_id, fal_port_t port_id, - fal_fwd_cmd_t cmd) -{ - sw_error_t rv; - hsl_api_t *p_api; - - SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id)); - - if (NULL == p_api->port_igmp_mld_learn_exceed_cmd_set) - return SW_NOT_SUPPORTED; - - rv = p_api->port_igmp_mld_learn_exceed_cmd_set(dev_id, port_id, cmd); - return rv; -} - -static sw_error_t -_fal_port_igmp_mld_learn_exceed_cmd_get(a_uint32_t dev_id, fal_port_t port_id, - fal_fwd_cmd_t * cmd) -{ - sw_error_t rv; - hsl_api_t *p_api; - - SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id)); - - if (NULL == p_api->port_igmp_mld_learn_exceed_cmd_get) - return SW_NOT_SUPPORTED; - - rv = p_api->port_igmp_mld_learn_exceed_cmd_get(dev_id, port_id, cmd); - return rv; -} - -static sw_error_t -_fal_igmp_sg_entry_set(a_uint32_t dev_id, fal_igmp_sg_entry_t * entry) -{ - sw_error_t rv; - hsl_api_t *p_api; - - SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id)); - - if (NULL == p_api->igmp_sg_entry_set) - return SW_NOT_SUPPORTED; - - rv = p_api->igmp_sg_entry_set(dev_id, entry); - return rv; -} -static sw_error_t -_fal_igmp_sg_entry_clear(a_uint32_t dev_id, fal_igmp_sg_entry_t * entry) -{ - sw_error_t rv; - hsl_api_t *p_api; - - SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id)); - - if (NULL == p_api->igmp_sg_entry_clear) - return SW_NOT_SUPPORTED; - - rv = p_api->igmp_sg_entry_clear(dev_id, entry); - return rv; -} -static sw_error_t -_fal_igmp_sg_entry_show(a_uint32_t dev_id) -{ - sw_error_t rv; - hsl_api_t *p_api; - - SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id)); - - if (NULL == p_api->igmp_sg_entry_show) - return SW_NOT_SUPPORTED; - - rv = p_api->igmp_sg_entry_show(dev_id); - return rv; -} -static sw_error_t -_fal_igmp_sg_entry_query(a_uint32_t dev_id, fal_igmp_sg_info_t * info) -{ - sw_error_t rv; - hsl_api_t *p_api; - - SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id)); - - if (NULL == p_api->igmp_sg_entry_query) - return SW_NOT_SUPPORTED; - - rv = p_api->igmp_sg_entry_query(dev_id, info); - return rv; -} -/** - * @brief Set igmp/mld packets snooping status on a particular port. - * @details Comments: - * After enabling igmp/mld snooping feature on a particular port all kinds - * igmp/mld packets received on this port would be acknowledged by hardware. - * Particular forwarding decision could be setted by fal_igmp_mld_cmd_set. - * @param[in] dev_id device id - * @param[in] port_id port id - * @param[in] enable A_TRUE or A_FALSE - * @return SW_OK or error code - */ -sw_error_t -fal_port_igmps_status_set(a_uint32_t dev_id, fal_port_t port_id, a_bool_t enable) -{ - sw_error_t rv; - - FAL_API_LOCK; - rv = _fal_port_igmps_status_set(dev_id, port_id, enable); - FAL_API_UNLOCK; - return rv; -} - -/** - * @brief Get igmp/mld packets snooping status on particular port. - * @param[in] dev_id device id - * @param[in] port_id port id - * @param[out] enable A_TRUE or A_FALSE - * @return SW_OK or error code - */ -sw_error_t -fal_port_igmps_status_get(a_uint32_t dev_id, fal_port_t port_id, a_bool_t *enable) -{ - sw_error_t rv; - - FAL_API_LOCK; - rv = _fal_port_igmps_status_get(dev_id, port_id, enable); - FAL_API_UNLOCK; - return rv; -} - -/** - * @brief Set igmp/mld packets forwarding command on a particular device. - * @details Comments: - * Particular device may only support parts of forwarding commands. - * This operation will take effect only after enabling igmp/mld snooping - * @param[in] dev_id device id - * @param[in] cmd forwarding command - * @return SW_OK or error code - */ -sw_error_t -fal_igmp_mld_cmd_set(a_uint32_t dev_id, fal_fwd_cmd_t cmd) -{ - sw_error_t rv; - - FAL_API_LOCK; - rv = _fal_igmp_mld_cmd_set(dev_id, cmd); - FAL_API_UNLOCK; - return rv; -} - -/** - * @brief Get igmp/mld packets forwarding command on a particular device. - * @param[in] dev_id device id - * @param[out] cmd forwarding command - * @return SW_OK or error code - */ -sw_error_t -fal_igmp_mld_cmd_get(a_uint32_t dev_id, fal_fwd_cmd_t * cmd) -{ - sw_error_t rv; - - FAL_API_LOCK; - rv = _fal_igmp_mld_cmd_get(dev_id, cmd); - FAL_API_UNLOCK; - return rv; -} - -/** - * @brief Set igmp/mld join packets hardware acknowledgement status on particular port. - * @details Comments: - * After enabling igmp/mld join feature on a particular port hardware will - * dynamic learning or changing multicast entry. - * @param[in] dev_id device id - * @param[in] port_id port id - * @param[in] enable A_TRUE or A_FALSE - * @return SW_OK or error code - */ -sw_error_t -fal_port_igmp_mld_join_set(a_uint32_t dev_id, fal_port_t port_id, a_bool_t enable) -{ - sw_error_t rv; - - FAL_API_LOCK; - rv = _fal_port_igmp_mld_join_set(dev_id, port_id, enable); - FAL_API_UNLOCK; - return rv; -} - -/** - * @brief Get igmp/mld join packets hardware acknowledgement status on a particular port. - * @param[in] dev_id device id - * @param[in] port_id port id - * @param[out] enable A_TRUE or A_FALSE - * @return SW_OK or error code - */ -sw_error_t -fal_port_igmp_mld_join_get(a_uint32_t dev_id, fal_port_t port_id, a_bool_t * enable) -{ - sw_error_t rv; - - FAL_API_LOCK; - rv = _fal_port_igmp_mld_join_get(dev_id, port_id, enable); - FAL_API_UNLOCK; - return rv; -} - -/** - * @brief Set igmp/mld leave packets hardware acknowledgement status on a particular port. - * @details Comments: - * After enabling igmp join feature on a particular port hardware will dynamic - * deleting or changing multicast entry. - * @param[in] dev_id device id - * @param[in] port_id port id - * @param[in] enable A_TRUE or A_FALSE - * @return SW_OK or error code - */ -sw_error_t -fal_port_igmp_mld_leave_set(a_uint32_t dev_id, fal_port_t port_id, a_bool_t enable) -{ - sw_error_t rv; - - FAL_API_LOCK; - rv = _fal_port_igmp_mld_leave_set(dev_id, port_id, enable); - FAL_API_UNLOCK; - return rv; -} - -/** - * @brief Get igmp/mld leave packets hardware acknowledgement status on a particular port. - * @param[in] dev_id device id - * @param[in] port_id port id - * @param[out] enable A_TRUE or A_FALSE - * @return SW_OK or error code - */ -sw_error_t -fal_port_igmp_mld_leave_get(a_uint32_t dev_id, fal_port_t port_id, a_bool_t * enable) -{ - sw_error_t rv; - - FAL_API_LOCK; - rv = _fal_port_igmp_mld_leave_get(dev_id, port_id, enable); - FAL_API_UNLOCK; - return rv; -} - -/** - * @brief Set igmp/mld router ports on a particular device. - * @details Comments: - * After enabling igmp/mld join/leave feature on a particular port igmp/mld - * join/leave packets received on this port will be forwarded to router ports. - * @param[in] dev_id device id - * @param[in] pts dedicates ports - * @return SW_OK or error code - */ -sw_error_t -fal_igmp_mld_rp_set(a_uint32_t dev_id, fal_pbmp_t pts) -{ - sw_error_t rv; - - FAL_API_LOCK; - rv = _fal_igmp_mld_rp_set(dev_id, pts); - FAL_API_UNLOCK; - return rv; -} - -/** - * @brief Get igmp/mld router ports on a particular device. - * @param[in] dev_id device id - * @param[out] pts dedicates ports - * @return SW_OK or error code - */ -sw_error_t -fal_igmp_mld_rp_get(a_uint32_t dev_id, fal_pbmp_t * pts) -{ - sw_error_t rv; - - FAL_API_LOCK; - rv = _fal_igmp_mld_rp_get(dev_id, pts); - FAL_API_UNLOCK; - return rv; -} - -/** - * @brief Set the status of creating multicast entry during igmp/mld join/leave procedure. - * @details Comments: - * After enabling igmp/mld join/leave feature on a particular port if enable - * entry creat hardware will dynamic creat and delete multicast entry, - * otherwise hardware only can change destination ports of existing muticast entry. - * @param[in] dev_id device id - * @param[in] enable A_TRUE or A_FALSE - * @return SW_OK or error code - */ -sw_error_t -fal_igmp_mld_entry_creat_set(a_uint32_t dev_id, a_bool_t enable) -{ - sw_error_t rv; - - FAL_API_LOCK; - rv = _fal_igmp_mld_entry_creat_set(dev_id, enable); - FAL_API_UNLOCK; - return rv; -} - -/** - * @brief Get the status of creating multicast entry during igmp/mld join/leave procedure. - * @param[in] dev_id device id - * @param[out] enable A_TRUE or A_FALSE - * @return SW_OK or error code - */ -sw_error_t -fal_igmp_mld_entry_creat_get(a_uint32_t dev_id, a_bool_t * enable) -{ - sw_error_t rv; - - FAL_API_LOCK; - rv = _fal_igmp_mld_entry_creat_get(dev_id, enable); - FAL_API_UNLOCK; - return rv; -} - -/** - * @brief Set the static status of multicast entry which learned by hardware. - * @details Comments: - * After enabling igmp/mld join/leave feature on a particular port if enable - * static status hardware will not age out multicast entry which leardned by hardware, - * otherwise hardware will age out multicast entry which leardned by hardware. - * @param[in] dev_id device id - * @param[in] enable A_TRUE or A_FALSE - * @return SW_OK or error code - */ -sw_error_t -fal_igmp_mld_entry_static_set(a_uint32_t dev_id, a_bool_t enable) -{ - sw_error_t rv; - - FAL_API_LOCK; - rv = _fal_igmp_mld_entry_static_set(dev_id, enable); - FAL_API_UNLOCK; - return rv; -} - -/** - * @brief Get the static status of multicast entry which learned by hardware. - * @param[in] dev_id device id - * @param[out] enable A_TRUE or A_FALSE - * @return SW_OK or error code - */ -sw_error_t -fal_igmp_mld_entry_static_get(a_uint32_t dev_id, a_bool_t * enable) -{ - sw_error_t rv; - - FAL_API_LOCK; - rv = _fal_igmp_mld_entry_static_get(dev_id, enable); - FAL_API_UNLOCK; - return rv; -} - -/** - * @brief Set the leaky status of multicast entry which learned by hardware. - * @details Comments: - * After enabling igmp/mld join/leave feature on a particular port if enable - * leaky status hardware will set leaky flag of multicast entry which leardned by hardware, - * otherwise hardware will not set leaky flag of multicast entry which leardned by hardware. - * @param[in] dev_id device id - * @param[in] enable A_TRUE or A_FALSE - * @return SW_OK or error code - */ -sw_error_t -fal_igmp_mld_entry_leaky_set(a_uint32_t dev_id, a_bool_t enable) -{ - sw_error_t rv; - - FAL_API_LOCK; - rv = _fal_igmp_mld_entry_leaky_set(dev_id, enable); - FAL_API_UNLOCK; - return rv; -} - -/** - * @brief Get the leaky status of multicast entry which learned by hardware. - * @param[in] dev_id device id - * @param[out] enable A_TRUE or A_FALSE - * @return SW_OK or error code - */ -sw_error_t -fal_igmp_mld_entry_leaky_get(a_uint32_t dev_id, a_bool_t * enable) -{ - sw_error_t rv; - - FAL_API_LOCK; - rv = _fal_igmp_mld_entry_leaky_get(dev_id, enable); - FAL_API_UNLOCK; - return rv; -} - -/** - * @brief Set igmpv3/mldv2 packets hardware acknowledgement status on a particular device. - * @details Comments: - * After enabling igmp join/leave feature on a particular port hardware will dynamic - * creating or changing multicast entry after receiving igmpv3/mldv2 packets. - * @param[in] dev_id device id - * @param[in] enable A_TRUE or A_FALSE - * @return SW_OK or error code - */ -sw_error_t -fal_igmp_mld_entry_v3_set(a_uint32_t dev_id, a_bool_t enable) -{ - sw_error_t rv; - - FAL_API_LOCK; - rv = _fal_igmp_mld_entry_v3_set(dev_id, enable); - FAL_API_UNLOCK; - return rv; -} - -/** - * @brief Get igmpv3/mldv2 packets hardware acknowledgement status on a particular device. - * @param[in] dev_id device id - * @param[out] enable A_TRUE or A_FALSE - * @return SW_OK or error code - */ -sw_error_t -fal_igmp_mld_entry_v3_get(a_uint32_t dev_id, a_bool_t * enable) -{ - sw_error_t rv; - - FAL_API_LOCK; - rv = _fal_igmp_mld_entry_v3_get(dev_id, enable); - FAL_API_UNLOCK; - return rv; -} - -/** - * @brief Set the queue status of multicast entry which learned by hardware. - * @details Comments: - * After enabling igmp/mld join/leave feature on a particular port if enable - * leaky status hardware will set queue flag of multicast entry which leardned by hardware, - * otherwise hardware will not set queue flag of multicast entry which leardned by hardware. - * @param[in] dev_id device id - * @param[in] enable A_TRUE or A_FALSE - * @param[in] queue queue id - * @return SW_OK or error code - */ -sw_error_t -fal_igmp_mld_entry_queue_set(a_uint32_t dev_id, a_bool_t enable, a_uint32_t queue) -{ - sw_error_t rv; - - FAL_API_LOCK; - rv = _fal_igmp_mld_entry_queue_set(dev_id, enable, queue); - FAL_API_UNLOCK; - return rv; -} - -/** - * @brief Get the queue status of multicast entry which learned by hardware. - * @param[in] dev_id device id - * @param[out] enable A_TRUE or A_FALSE - * @param[out] queue queue id - * @return SW_OK or error code - */ -sw_error_t -fal_igmp_mld_entry_queue_get(a_uint32_t dev_id, a_bool_t * enable, a_uint32_t * queue) -{ - sw_error_t rv; - - FAL_API_LOCK; - rv = _fal_igmp_mld_entry_queue_get(dev_id, enable, queue); - FAL_API_UNLOCK; - return rv; -} - -/** - * @brief Set IGMP hardware learning count limit on a particular port. - * @param[in] dev_id device id - * @param[in] port_id port id - * @param[in] enable A_TRUE or A_FALSE - * @param[in] cnt limit count - * @return SW_OK or error code - */ -sw_error_t -fal_port_igmp_mld_learn_limit_set(a_uint32_t dev_id, fal_port_t port_id, - a_bool_t enable, a_uint32_t cnt) -{ - sw_error_t rv; - - FAL_API_LOCK; - rv = _fal_port_igmp_mld_learn_limit_set(dev_id, port_id, enable, cnt); - FAL_API_UNLOCK; - return rv; -} - -/** - * @brief Get IGMP hardware learning count limit on a particular port. - * @param[in] dev_id device id - * @param[in] port_id port id - * @param[out] enable A_TRUE or A_FALSE - * @param[out] cnt limit count - * @return SW_OK or error code - */ -sw_error_t -fal_port_igmp_mld_learn_limit_get(a_uint32_t dev_id, fal_port_t port_id, - a_bool_t * enable, a_uint32_t * cnt) -{ - sw_error_t rv; - - FAL_API_LOCK; - rv = _fal_port_igmp_mld_learn_limit_get(dev_id, port_id, enable, cnt); - FAL_API_UNLOCK; - return rv; -} - -/** - * @brief Set IGMP hardware learning count exceed command on a particular port. - * @param[in] dev_id device id - * @param[in] port_id port id - * @param[in] cmd forwarding command - * @return SW_OK or error code - */ -sw_error_t -fal_port_igmp_mld_learn_exceed_cmd_set(a_uint32_t dev_id, fal_port_t port_id, - fal_fwd_cmd_t cmd) -{ - sw_error_t rv; - - FAL_API_LOCK; - rv = _fal_port_igmp_mld_learn_exceed_cmd_set(dev_id, port_id, cmd); - FAL_API_UNLOCK; - return rv; -} - -/** - * @brief Get IGMP hardware learning count exceed command on a particular port. - * @param[in] dev_id device id - * @param[in] port_id port id - * @param[out] cmd forwarding command - * @return SW_OK or error code - */ -sw_error_t -fal_port_igmp_mld_learn_exceed_cmd_get(a_uint32_t dev_id, fal_port_t port_id, - fal_fwd_cmd_t * cmd) -{ - sw_error_t rv; - - FAL_API_LOCK; - rv = _fal_port_igmp_mld_learn_exceed_cmd_get(dev_id, port_id, cmd); - FAL_API_UNLOCK; - return rv; -} - -sw_error_t -fal_igmp_sg_entry_set(a_uint32_t dev_id, fal_igmp_sg_entry_t * entry) -{ - sw_error_t rv; - - FAL_API_LOCK; - rv = _fal_igmp_sg_entry_set(dev_id, entry); - FAL_API_UNLOCK; - return rv; -} -sw_error_t -fal_igmp_sg_entry_clear(a_uint32_t dev_id, fal_igmp_sg_entry_t * entry) -{ - sw_error_t rv; - - FAL_API_LOCK; - rv = _fal_igmp_sg_entry_clear(dev_id, entry); - FAL_API_UNLOCK; - return rv; -} -sw_error_t -fal_igmp_sg_entry_show(a_uint32_t dev_id) -{ - sw_error_t rv; - - FAL_API_LOCK; - rv = _fal_igmp_sg_entry_show(dev_id); - FAL_API_UNLOCK; - return rv; -} -sw_error_t -fal_igmp_sg_entry_query(a_uint32_t dev_id, fal_igmp_sg_info_t * info) -{ - sw_error_t rv; - - FAL_API_LOCK; - rv = _fal_igmp_sg_entry_query(dev_id, info); - FAL_API_UNLOCK; - return rv; -} - -/** - * @} - */ - diff --git a/feeds/ipq807x/qca-ssdk/src/src/fal/fal_init.c b/feeds/ipq807x/qca-ssdk/src/src/fal/fal_init.c deleted file mode 100755 index 16882a1fa..000000000 --- a/feeds/ipq807x/qca-ssdk/src/src/fal/fal_init.c +++ /dev/null @@ -1,212 +0,0 @@ -/* - * Copyright (c) 2012, 2016-2018, The Linux Foundation. All rights reserved. - * Permission to use, copy, modify, and/or distribute this software for - * any purpose with or without fee is hereby granted, provided that the - * above copyright notice and this permission notice appear in all copies. - * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES - * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR - * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES - * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN - * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT - * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. - */ - -/*qca808x_start*/ -/** - * @defgroup fal_init FAL_INIT - * @{ - */ -#include "sw.h" -#include "hsl.h" -#include "hsl_dev.h" -#include "hsl_api.h" -/*qca808x_end*/ -#include "fal_vlan.h" -#include "adpt.h" -/*qca808x_start*/ -/** - * @brief Init fal layer. - * @details Comments: - * This operation will init fal layer and hsl layer - * @param[in] dev_id device id - * @param[in] cfg configuration for initialization - * @return SW_OK or error code - */ -sw_error_t -fal_init(a_uint32_t dev_id, ssdk_init_cfg *cfg) -{ - sw_error_t rv; - HSL_DEV_ID_CHECK(dev_id); - - rv = hsl_api_init(dev_id); - SW_RTN_ON_ERROR(rv); - - rv = hsl_dev_init(dev_id, cfg); - SW_RTN_ON_ERROR(rv); -/*qca808x_end*/ -#ifdef IN_VLAN - rv = fal_vlan_init(dev_id); - SW_RTN_ON_ERROR(rv); -#endif - - rv = adpt_init(dev_id, cfg); - SW_RTN_ON_ERROR(rv); -/*qca808x_start*/ - - return rv; -} -/*qca808x_end*/ - -static sw_error_t -_fal_reset(a_uint32_t dev_id) -{ - sw_error_t rv; - hsl_api_t *p_api; - - SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id)); - - if (NULL == p_api->dev_reset) - return SW_NOT_SUPPORTED; - -#ifdef IN_VLAN - rv = fal_vlan_reset(dev_id); - SW_RTN_ON_ERROR(rv); -#endif - - rv = p_api->dev_reset(dev_id); - return rv; -} - -static sw_error_t -_fal_ssdk_cfg(a_uint32_t dev_id, ssdk_cfg_t *ssdk_cfg) -{ - sw_error_t rv; - HSL_DEV_ID_CHECK(dev_id); - - rv = hsl_ssdk_cfg(dev_id, ssdk_cfg); - - return rv; -} - -static sw_error_t -_fal_module_func_ctrl_set(a_uint32_t dev_id, a_uint32_t module, fal_func_ctrl_t *func_ctrl) -{ - return adpt_module_func_ctrl_set(dev_id, module, func_ctrl); -} - -static sw_error_t -_fal_module_func_ctrl_get(a_uint32_t dev_id, a_uint32_t module, fal_func_ctrl_t *func_ctrl) -{ - return adpt_module_func_ctrl_get(dev_id, module, func_ctrl); -} -/*qca808x_start*/ -sw_error_t -fal_cleanup(void) -{ - sw_error_t rv; - - rv = hsl_dev_cleanup(); - SW_RTN_ON_ERROR(rv); -/*qca808x_end*/ -#ifdef IN_VLAN - rv = fal_vlan_cleanup(); - SW_RTN_ON_ERROR(rv); -#endif -/*qca808x_start*/ - return SW_OK; -} -/*qca808x_end*/ -/** - * @brief Reset fal layer. - * @details Comments: - * This operation will reset fal layer and hsl layer - * @param[in] dev_id device id - * @return SW_OK or error code - */ -sw_error_t -fal_reset(a_uint32_t dev_id) -{ - sw_error_t rv; - - FAL_API_LOCK; - rv = _fal_reset(dev_id); - FAL_API_UNLOCK; - return rv; -} - -/** - * @brief Get SSDK config infomation. - * @param[in] dev_id device id - * @param[out] ssdk_cfg SSDK config infomation - * @return SW_OK or error code - */ -sw_error_t -fal_ssdk_cfg(a_uint32_t dev_id, ssdk_cfg_t *ssdk_cfg) -{ - sw_error_t rv; - - FAL_API_LOCK; - rv = _fal_ssdk_cfg(dev_id, ssdk_cfg); - FAL_API_UNLOCK; - return rv; -} - -sw_error_t -fal_switch_devid_get(ssdk_chip_type chip_type, a_uint32_t *pdev_id) -{ - sw_error_t rv = SW_OK; - ssdk_cfg_t cfg = {0}; - a_uint32_t dev_id = 0; - - for(dev_id = 0; dev_id < SW_MAX_NR_DEV; dev_id++) { - rv = _fal_ssdk_cfg(dev_id, &cfg); - if(rv == SW_OK && cfg.init_cfg.chip_type == chip_type) { - *pdev_id = dev_id; - return rv; - } - } - return SW_FAIL; -} - -sw_error_t -fal_module_func_ctrl_set(a_uint32_t dev_id, a_uint32_t module, fal_func_ctrl_t *func_ctrl) -{ - sw_error_t rv; - - FAL_API_LOCK; - rv = _fal_module_func_ctrl_set(dev_id, module, func_ctrl); - FAL_API_UNLOCK; - return rv; -} - -sw_error_t -fal_module_func_ctrl_get(a_uint32_t dev_id, a_uint32_t module, fal_func_ctrl_t *func_ctrl) -{ - sw_error_t rv; - - FAL_API_LOCK; - rv = _fal_module_func_ctrl_get(dev_id, module, func_ctrl); - FAL_API_UNLOCK; - return rv; -} - -sw_error_t -fal_module_func_init(a_uint32_t dev_id, ssdk_init_cfg *cfg) -{ - sw_error_t rv; - HSL_DEV_ID_CHECK(dev_id); - - rv = adpt_module_func_init(dev_id, cfg); - SW_RTN_ON_ERROR(rv); - - return rv; -} - -EXPORT_SYMBOL(fal_switch_devid_get); -EXPORT_SYMBOL(fal_module_func_ctrl_set); -EXPORT_SYMBOL(fal_module_func_ctrl_get); - -/** - * @} - */ diff --git a/feeds/ipq807x/qca-ssdk/src/src/fal/fal_interface_ctrl.c b/feeds/ipq807x/qca-ssdk/src/src/fal/fal_interface_ctrl.c deleted file mode 100755 index 85cc1008e..000000000 --- a/feeds/ipq807x/qca-ssdk/src/src/fal/fal_interface_ctrl.c +++ /dev/null @@ -1,386 +0,0 @@ -/* - * Copyright (c) 2012, The Linux Foundation. All rights reserved. - * Permission to use, copy, modify, and/or distribute this software for - * any purpose with or without fee is hereby granted, provided that the - * above copyright notice and this permission notice appear in all copies. - * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES - * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR - * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES - * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN - * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT - * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. - */ - - -/** - * @defgroup fal_interface_ctrl FAL_INTERFACE_CONTROL - * @{ - */ -#include "sw.h" -#include "fal_interface_ctrl.h" -#include "hsl_api.h" - -static sw_error_t -_fal_port_3az_status_set(a_uint32_t dev_id, fal_port_t port_id, a_bool_t enable) -{ - sw_error_t rv; - hsl_api_t *p_api; - - SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id)); - - if (NULL == p_api->port_3az_status_set) - return SW_NOT_SUPPORTED; - - rv = p_api->port_3az_status_set(dev_id, port_id, enable); - return rv; -} - -static sw_error_t -_fal_port_3az_status_get(a_uint32_t dev_id, fal_port_t port_id, a_bool_t * enable) -{ - sw_error_t rv; - hsl_api_t *p_api; - - SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id)); - - if (NULL == p_api->port_3az_status_get) - return SW_NOT_SUPPORTED; - - rv = p_api->port_3az_status_get(dev_id, port_id, enable); - return rv; -} - -static sw_error_t -_fal_interface_mac_mode_set(a_uint32_t dev_id, fal_port_t port_id, fal_mac_config_t * config) -{ - sw_error_t rv; - hsl_api_t *p_api; - - SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id)); - - if (NULL == p_api->interface_mac_mode_set) - return SW_NOT_SUPPORTED; - - rv = p_api->interface_mac_mode_set(dev_id, port_id, config); - return rv; -} - -static sw_error_t -_fal_interface_mac_mode_get(a_uint32_t dev_id, fal_port_t port_id, fal_mac_config_t * config) -{ - sw_error_t rv; - hsl_api_t *p_api; - - SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id)); - - if (NULL == p_api->interface_mac_mode_get) - return SW_NOT_SUPPORTED; - - rv = p_api->interface_mac_mode_get(dev_id, port_id, config); - return rv; -} - -static sw_error_t -_fal_interface_phy_mode_set(a_uint32_t dev_id, a_uint32_t phy_id, fal_phy_config_t * config) -{ - sw_error_t rv; - hsl_api_t *p_api; - - SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id)); - - if (NULL == p_api->interface_phy_mode_set) - return SW_NOT_SUPPORTED; - - rv = p_api->interface_phy_mode_set(dev_id, phy_id, config); - return rv; -} - -static sw_error_t -_fal_interface_phy_mode_get(a_uint32_t dev_id, a_uint32_t phy_id, fal_phy_config_t * config) -{ - sw_error_t rv; - hsl_api_t *p_api; - - SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id)); - - if (NULL == p_api->interface_phy_mode_get) - return SW_NOT_SUPPORTED; - - rv = p_api->interface_phy_mode_get(dev_id, phy_id, config); - return rv; -} - -static sw_error_t -_fal_interface_fx100_ctrl_set(a_uint32_t dev_id, fal_fx100_ctrl_config_t * config) -{ - sw_error_t rv; - hsl_api_t *p_api; - - SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id)); - - if (NULL == p_api->interface_fx100_ctrl_set) - return SW_NOT_SUPPORTED; - - rv = p_api->interface_fx100_ctrl_set(dev_id, config); - return rv; -} - -static sw_error_t -_fal_interface_fx100_ctrl_get(a_uint32_t dev_id, fal_fx100_ctrl_config_t * config) -{ - sw_error_t rv; - hsl_api_t *p_api; - - SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id)); - - if (NULL == p_api->interface_fx100_ctrl_get) - return SW_NOT_SUPPORTED; - - rv = p_api->interface_fx100_ctrl_get(dev_id, config); - return rv; -} - -static sw_error_t -_fal_interface_fx100_status_get(a_uint32_t dev_id, a_uint32_t* status) -{ - sw_error_t rv; - hsl_api_t *p_api; - - SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id)); - - if (NULL == p_api->interface_fx100_status_get) - return SW_NOT_SUPPORTED; - - rv = p_api->interface_fx100_status_get(dev_id, status); - return rv; -} - -static sw_error_t -_fal_interface_mac06_exch_set(a_uint32_t dev_id, a_bool_t enable) -{ - sw_error_t rv; - hsl_api_t *p_api; - - SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id)); - - if (NULL == p_api->interface_mac06_exch_set) - return SW_NOT_SUPPORTED; - - rv = p_api->interface_mac06_exch_set(dev_id, enable); - return rv; -} - -static sw_error_t -_fal_interface_mac06_exch_get(a_uint32_t dev_id, a_bool_t* enable) -{ - sw_error_t rv; - hsl_api_t *p_api; - - SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id)); - - if (NULL == p_api->interface_mac06_exch_get) - return SW_NOT_SUPPORTED; - - rv = p_api->interface_mac06_exch_get(dev_id, enable); - return rv; -} - -/** - * @brief Set 802.3az status on a particular port. - * @param[in] dev_id device id - * @param[in] port_id port id - * @param[in] enable A_TRUE or A_FALSE - * @return SW_OK or error code - */ -sw_error_t -fal_port_3az_status_set(a_uint32_t dev_id, fal_port_t port_id, a_bool_t enable) -{ - sw_error_t rv; - - FAL_API_LOCK; - rv = _fal_port_3az_status_set(dev_id, port_id, enable); - FAL_API_UNLOCK; - return rv; -} - -/** - * @brief Get 802.3az status on a particular port. - * @param[in] dev_id device id - * @param[in] port_id port id - * @param[out] enable A_TRUE or A_FALSE - * @return SW_OK or error code - */ -sw_error_t -fal_port_3az_status_get(a_uint32_t dev_id, fal_port_t port_id, a_bool_t * enable) -{ - sw_error_t rv; - - FAL_API_LOCK; - rv = _fal_port_3az_status_get(dev_id, port_id, enable); - FAL_API_UNLOCK; - return rv; -} - -/** - * @brief Set interface mode on a particular MAC device. - * @param[in] dev_id device id - * @param[in] mca_id MAC device ID - * @param[in] config interface configuration - * @return SW_OK or error code - */ -sw_error_t -fal_interface_mac_mode_set(a_uint32_t dev_id, fal_port_t port_id, fal_mac_config_t * config) -{ - sw_error_t rv; - - FAL_API_LOCK; - rv = _fal_interface_mac_mode_set(dev_id, port_id, config); - FAL_API_UNLOCK; - return rv; -} - -/** - * @brief Get interface mode on a particular MAC device. - * @param[in] dev_id device id - * @param[in] mca_id MAC device ID - * @param[out] config interface configuration - * @return SW_OK or error code - */ -sw_error_t -fal_interface_mac_mode_get(a_uint32_t dev_id, fal_port_t port_id, fal_mac_config_t * config) -{ - sw_error_t rv; - - FAL_API_LOCK; - rv = _fal_interface_mac_mode_get(dev_id, port_id, config); - FAL_API_UNLOCK; - return rv; -} - -/** - * @brief Set interface phy mode on a particular PHY device. - * @param[in] dev_id device id - * @param[in] phy_id PHY device ID - * @param[in] config interface configuration - * @return SW_OK or error code - */ -sw_error_t -fal_interface_phy_mode_set(a_uint32_t dev_id, a_uint32_t phy_id, fal_phy_config_t * config) -{ - sw_error_t rv; - - FAL_API_LOCK; - rv = _fal_interface_phy_mode_set(dev_id, phy_id, config); - FAL_API_UNLOCK; - return rv; -} - -/** - * @brief Get interface phy mode on a particular PHY device. - * @param[in] dev_id device id - * @param[in] phy_id PHY device ID - * @param[out] config interface configuration - * @return SW_OK or error code - */ -sw_error_t -fal_interface_phy_mode_get(a_uint32_t dev_id, a_uint32_t phy_id, fal_phy_config_t * config) -{ - sw_error_t rv; - - FAL_API_LOCK; - rv = _fal_interface_phy_mode_get(dev_id, phy_id, config); - FAL_API_UNLOCK; - return rv; -} - -/** - * @brief Set fx100 control configuration. - * @param[in] dev_id device id - * @param[in] config fx100 control configuration - * @return SW_OK or error code - */ -sw_error_t -fal_interface_fx100_ctrl_set(a_uint32_t dev_id, fal_fx100_ctrl_config_t * config) -{ - sw_error_t rv; - - FAL_API_LOCK; - rv = _fal_interface_fx100_ctrl_set(dev_id, config); - FAL_API_UNLOCK; - return rv; -} - - -/** - * @brief Get fx100 control configuration. - * @param[in] dev_id device id - * @param[out] config fx100 control configuration - * @return SW_OK or error code - */ -sw_error_t -fal_interface_fx100_ctrl_get(a_uint32_t dev_id, fal_fx100_ctrl_config_t * config) -{ - sw_error_t rv; - - FAL_API_LOCK; - rv = _fal_interface_fx100_ctrl_get(dev_id, config); - FAL_API_UNLOCK; - return rv; -} - -/** - * @brief Get fx100 control configuration. - * @param[in] dev_id device id - * @param[out] fx100 status - * @return SW_OK or error code - */ -sw_error_t -fal_interface_fx100_status_get(a_uint32_t dev_id, a_uint32_t* status) -{ - sw_error_t rv; - - FAL_API_LOCK; - rv = _fal_interface_fx100_status_get(dev_id, status); - FAL_API_UNLOCK; - return rv; -} - - -/** - * @brief Set mac0 and mac6 exchange status. - * @param[in] dev_id device id - * @param[in] enable A_TRUE or A_FALSE - * @return SW_OK or error code - */ -sw_error_t -fal_interface_mac06_exch_set(a_uint32_t dev_id, a_bool_t enable) -{ - sw_error_t rv; - - FAL_API_LOCK; - rv = _fal_interface_mac06_exch_set(dev_id, enable); - FAL_API_UNLOCK; - return rv; -} - -/** - * @brief Get mac0 and mac6 exchange status. - * @param[in] dev_id device id - * @param[out] enable A_TRUE or A_FALSE - * @return SW_OK or error code - */ -sw_error_t -fal_interface_mac06_exch_get(a_uint32_t dev_id, a_bool_t* enable) -{ - sw_error_t rv; - - FAL_API_LOCK; - rv = _fal_interface_mac06_exch_get(dev_id, enable); - FAL_API_UNLOCK; - return rv; -} -/** - * @} - */ - diff --git a/feeds/ipq807x/qca-ssdk/src/src/fal/fal_ip.c b/feeds/ipq807x/qca-ssdk/src/src/fal/fal_ip.c deleted file mode 100755 index 917d31232..000000000 --- a/feeds/ipq807x/qca-ssdk/src/src/fal/fal_ip.c +++ /dev/null @@ -1,2370 +0,0 @@ -/* - * Copyright (c) 2012, 2015, 2017, The Linux Foundation. All rights reserved. - * Permission to use, copy, modify, and/or distribute this software for - * any purpose with or without fee is hereby granted, provided that the - * above copyright notice and this permission notice appear in all copies. - * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES - * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR - * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES - * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN - * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT - * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. - */ - - -/** - * @defgroup fal_ip FAL_IP - * @{ - */ -#include "sw.h" -#include "fal_ip.h" -#include "hsl_api.h" -#include "adpt.h" - -#include -#include - -#ifndef IN_IP_MINI -static sw_error_t -_fal_ip_host_add(a_uint32_t dev_id, fal_host_entry_t * host_entry) -{ - sw_error_t rv; - hsl_api_t *p_api; - adpt_api_t *p_adpt_api; - - if((p_adpt_api = adpt_api_ptr_get(dev_id)) != NULL) { - if (NULL == p_adpt_api->adpt_ip_host_add) - return SW_NOT_SUPPORTED; - - rv = p_adpt_api->adpt_ip_host_add(dev_id, host_entry); - return rv; - } - - SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id)); - - if (NULL == p_api->ip_host_add) - return SW_NOT_SUPPORTED; - - rv = p_api->ip_host_add(dev_id, host_entry); - return rv; -} - -static sw_error_t -_fal_ip_host_del(a_uint32_t dev_id, a_uint32_t del_mode, - fal_host_entry_t * host_entry) -{ - sw_error_t rv; - hsl_api_t *p_api; - adpt_api_t *p_adpt_api; - - if((p_adpt_api = adpt_api_ptr_get(dev_id)) != NULL) { - if (NULL == p_adpt_api->adpt_ip_host_del) - return SW_NOT_SUPPORTED; - - rv = p_adpt_api->adpt_ip_host_del(dev_id, del_mode, host_entry); - return rv; - } - - SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id)); - - if (NULL == p_api->ip_host_del) - return SW_NOT_SUPPORTED; - - rv = p_api->ip_host_del(dev_id, del_mode, host_entry); - return rv; -} - -static sw_error_t -_fal_ip_host_get(a_uint32_t dev_id, a_uint32_t get_mode, - fal_host_entry_t * host_entry) -{ - sw_error_t rv; - hsl_api_t *p_api; - adpt_api_t *p_adpt_api; - - if((p_adpt_api = adpt_api_ptr_get(dev_id)) != NULL) { - if (NULL == p_adpt_api->adpt_ip_host_get) - return SW_NOT_SUPPORTED; - - rv = p_adpt_api->adpt_ip_host_get(dev_id, get_mode, host_entry); - return rv; - } - - SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id)); - - if (NULL == p_api->ip_host_get) - return SW_NOT_SUPPORTED; - - rv = p_api->ip_host_get(dev_id, get_mode, host_entry); - return rv; -} - -static sw_error_t -_fal_ip_host_next(a_uint32_t dev_id, a_uint32_t next_mode, - fal_host_entry_t * host_entry) -{ - sw_error_t rv; - hsl_api_t *p_api; - adpt_api_t *p_adpt_api; - - if((p_adpt_api = adpt_api_ptr_get(dev_id)) != NULL) { - if (NULL == p_adpt_api->adpt_ip_host_next) - return SW_NOT_SUPPORTED; - - rv = p_adpt_api->adpt_ip_host_next(dev_id, next_mode, host_entry); - return rv; - } - - SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id)); - - if (NULL == p_api->ip_host_next) - return SW_NOT_SUPPORTED; - - rv = p_api->ip_host_next(dev_id, next_mode, host_entry); - return rv; -} - -static sw_error_t -_fal_ip_host_counter_bind(a_uint32_t dev_id, a_uint32_t entry_id, - a_uint32_t cnt_id, a_bool_t enable) -{ - sw_error_t rv; - hsl_api_t *p_api; - - SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id)); - - if (NULL == p_api->ip_host_counter_bind) - return SW_NOT_SUPPORTED; - - rv = p_api->ip_host_counter_bind(dev_id, entry_id, cnt_id, enable); - return rv; -} - -static sw_error_t -_fal_ip_host_pppoe_bind(a_uint32_t dev_id, a_uint32_t entry_id, - a_uint32_t pppoe_id, a_bool_t enable) -{ - sw_error_t rv; - hsl_api_t *p_api; - - SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id)); - - if (NULL == p_api->ip_host_pppoe_bind) - return SW_NOT_SUPPORTED; - - rv = p_api->ip_host_pppoe_bind(dev_id, entry_id, pppoe_id, enable); - return rv; -} - -static sw_error_t -_fal_ip_pt_arp_learn_set(a_uint32_t dev_id, fal_port_t port_id, a_uint32_t flags) -{ - sw_error_t rv; - hsl_api_t *p_api; - - SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id)); - - if (NULL == p_api->ip_pt_arp_learn_set) - return SW_NOT_SUPPORTED; - - rv = p_api->ip_pt_arp_learn_set(dev_id, port_id, flags); - return rv; -} - -static sw_error_t -_fal_ip_pt_arp_learn_get(a_uint32_t dev_id, fal_port_t port_id, - a_uint32_t * flags) -{ - sw_error_t rv; - hsl_api_t *p_api; - - SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id)); - - if (NULL == p_api->ip_pt_arp_learn_get) - return SW_NOT_SUPPORTED; - - rv = p_api->ip_pt_arp_learn_get(dev_id, port_id, flags); - return rv; -} - -static sw_error_t -_fal_ip_arp_learn_set(a_uint32_t dev_id, fal_arp_learn_mode_t mode) -{ - sw_error_t rv; - hsl_api_t *p_api; - - SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id)); - - if (NULL == p_api->ip_arp_learn_set) - return SW_NOT_SUPPORTED; - - rv = p_api->ip_arp_learn_set(dev_id, mode); - return rv; -} - -static sw_error_t -_fal_ip_arp_learn_get(a_uint32_t dev_id, fal_arp_learn_mode_t * mode) -{ - sw_error_t rv; - hsl_api_t *p_api; - - SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id)); - - if (NULL == p_api->ip_arp_learn_get) - return SW_NOT_SUPPORTED; - - rv = p_api->ip_arp_learn_get(dev_id, mode); - return rv; -} - -static sw_error_t -_fal_ip_source_guard_set(a_uint32_t dev_id, fal_port_t port_id, - fal_source_guard_mode_t mode) -{ - sw_error_t rv; - hsl_api_t *p_api; - - SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id)); - - if (NULL == p_api->ip_source_guard_set) - return SW_NOT_SUPPORTED; - - rv = p_api->ip_source_guard_set(dev_id, port_id, mode); - return rv; -} - -static sw_error_t -_fal_ip_source_guard_get(a_uint32_t dev_id, fal_port_t port_id, - fal_source_guard_mode_t * mode) -{ - sw_error_t rv; - hsl_api_t *p_api; - - SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id)); - - if (NULL == p_api->ip_source_guard_get) - return SW_NOT_SUPPORTED; - - rv = p_api->ip_source_guard_get(dev_id, port_id, mode); - return rv; -} - -static sw_error_t -_fal_ip_unk_source_cmd_set(a_uint32_t dev_id, fal_fwd_cmd_t cmd) -{ - sw_error_t rv; - hsl_api_t *p_api; - - SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id)); - - if (NULL == p_api->ip_unk_source_cmd_set) - return SW_NOT_SUPPORTED; - - rv = p_api->ip_unk_source_cmd_set(dev_id, cmd); - return rv; -} - -static sw_error_t -_fal_ip_unk_source_cmd_get(a_uint32_t dev_id, fal_fwd_cmd_t * cmd) -{ - sw_error_t rv; - hsl_api_t *p_api; - - SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id)); - - if (NULL == p_api->ip_unk_source_cmd_get) - return SW_NOT_SUPPORTED; - - rv = p_api->ip_unk_source_cmd_get(dev_id, cmd); - return rv; -} - -static sw_error_t -_fal_ip_arp_guard_set(a_uint32_t dev_id, fal_port_t port_id, - fal_source_guard_mode_t mode) -{ - sw_error_t rv; - hsl_api_t *p_api; - - SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id)); - - if (NULL == p_api->ip_arp_guard_set) - return SW_NOT_SUPPORTED; - - rv = p_api->ip_arp_guard_set(dev_id, port_id, mode); - return rv; -} - -static sw_error_t -_fal_ip_arp_guard_get(a_uint32_t dev_id, fal_port_t port_id, - fal_source_guard_mode_t * mode) -{ - sw_error_t rv; - hsl_api_t *p_api; - - SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id)); - - if (NULL == p_api->ip_arp_guard_get) - return SW_NOT_SUPPORTED; - - rv = p_api->ip_arp_guard_get(dev_id, port_id, mode); - return rv; -} - -static sw_error_t -_fal_arp_unk_source_cmd_set(a_uint32_t dev_id, fal_fwd_cmd_t cmd) -{ - sw_error_t rv; - hsl_api_t *p_api; - - SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id)); - - if (NULL == p_api->arp_unk_source_cmd_set) - return SW_NOT_SUPPORTED; - - rv = p_api->arp_unk_source_cmd_set(dev_id, cmd); - return rv; -} - -static sw_error_t -_fal_arp_unk_source_cmd_get(a_uint32_t dev_id, fal_fwd_cmd_t * cmd) -{ - sw_error_t rv; - hsl_api_t *p_api; - - SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id)); - - if (NULL == p_api->arp_unk_source_cmd_get) - return SW_NOT_SUPPORTED; - - rv = p_api->arp_unk_source_cmd_get(dev_id, cmd); - return rv; -} - -static sw_error_t -_fal_ip_route_status_set(a_uint32_t dev_id, a_bool_t enable) -{ - sw_error_t rv; - hsl_api_t *p_api; - - SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id)); - - if (NULL == p_api->ip_route_status_set) - return SW_NOT_SUPPORTED; - - rv = p_api->ip_route_status_set(dev_id, enable); - return rv; -} - -static sw_error_t -_fal_ip_route_status_get(a_uint32_t dev_id, a_bool_t * enable) -{ - sw_error_t rv; - hsl_api_t *p_api; - - SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id)); - - if (NULL == p_api->ip_route_status_get) - return SW_NOT_SUPPORTED; - - rv = p_api->ip_route_status_get(dev_id, enable); - return rv; -} - -static sw_error_t -_fal_ip_intf_entry_add(a_uint32_t dev_id, fal_intf_mac_entry_t * entry) -{ - sw_error_t rv; - hsl_api_t *p_api; - - SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id)); - - if (NULL == p_api->ip_intf_entry_add) - return SW_NOT_SUPPORTED; - - rv = p_api->ip_intf_entry_add(dev_id, entry); - return rv; -} - -static sw_error_t -_fal_ip_intf_entry_del(a_uint32_t dev_id, a_uint32_t del_mode, - fal_intf_mac_entry_t * entry) -{ - sw_error_t rv; - hsl_api_t *p_api; - - SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id)); - - if (NULL == p_api->ip_intf_entry_del) - return SW_NOT_SUPPORTED; - - rv = p_api->ip_intf_entry_del(dev_id, del_mode, entry); - return rv; -} - -static sw_error_t -_fal_ip_intf_entry_next(a_uint32_t dev_id, a_uint32_t next_mode, - fal_intf_mac_entry_t * entry) -{ - sw_error_t rv; - hsl_api_t *p_api; - - SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id)); - - if (NULL == p_api->ip_intf_entry_next) - return SW_NOT_SUPPORTED; - - rv = p_api->ip_intf_entry_next(dev_id, next_mode, entry); - return rv; -} - -static sw_error_t -_fal_ip_age_time_set(a_uint32_t dev_id, a_uint32_t * time) -{ - sw_error_t rv; - hsl_api_t *p_api; - - SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id)); - - if (NULL == p_api->ip_age_time_set) - return SW_NOT_SUPPORTED; - - rv = p_api->ip_age_time_set(dev_id, time); - return rv; -} - -static sw_error_t -_fal_ip_age_time_get(a_uint32_t dev_id, a_uint32_t * time) -{ - sw_error_t rv; - hsl_api_t *p_api; - - SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id)); - - if (NULL == p_api->ip_age_time_get) - return SW_NOT_SUPPORTED; - - rv = p_api->ip_age_time_get(dev_id, time); - return rv; -} - -static sw_error_t -_fal_ip_wcmp_hash_mode_set(a_uint32_t dev_id, a_uint32_t hash_mode) -{ - sw_error_t rv; - hsl_api_t *p_api; - - SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id)); - - if (NULL == p_api->ip_wcmp_hash_mode_set) - return SW_NOT_SUPPORTED; - - rv = p_api->ip_wcmp_hash_mode_set(dev_id, hash_mode); - return rv; -} - -static sw_error_t -_fal_ip_wcmp_hash_mode_get(a_uint32_t dev_id, a_uint32_t * hash_mode) -{ - sw_error_t rv; - hsl_api_t *p_api; - - SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id)); - - if (NULL == p_api->ip_wcmp_hash_mode_get) - return SW_NOT_SUPPORTED; - - rv = p_api->ip_wcmp_hash_mode_get(dev_id, hash_mode); - return rv; -} - -static sw_error_t -_fal_ip_vrf_base_addr_set(a_uint32_t dev_id, - a_uint32_t vrf_id, fal_ip4_addr_t addr) -{ - sw_error_t rv; - hsl_api_t *p_api; - - SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id)); - - if (NULL == p_api->ip_vrf_base_addr_set) - return SW_NOT_SUPPORTED; - - rv = p_api->ip_vrf_base_addr_set(dev_id, vrf_id, addr); - return rv; -} - -static sw_error_t -_fal_ip_vrf_base_addr_get(a_uint32_t dev_id, - a_uint32_t vrf_id, fal_ip4_addr_t * addr) -{ - sw_error_t rv; - hsl_api_t *p_api; - - SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id)); - - if (NULL == p_api->ip_vrf_base_addr_get) - return SW_NOT_SUPPORTED; - - rv = p_api->ip_vrf_base_addr_get(dev_id, vrf_id, addr); - return rv; -} - -static sw_error_t -_fal_ip_vrf_base_mask_set(a_uint32_t dev_id, - a_uint32_t vrf_id, fal_ip4_addr_t addr) -{ - sw_error_t rv; - hsl_api_t *p_api; - - SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id)); - - if (NULL == p_api->ip_vrf_base_mask_set) - return SW_NOT_SUPPORTED; - - rv = p_api->ip_vrf_base_mask_set(dev_id, vrf_id, addr); - return rv; -} - -static sw_error_t -_fal_ip_vrf_base_mask_get(a_uint32_t dev_id, - a_uint32_t vrf_id, fal_ip4_addr_t * addr) -{ - sw_error_t rv; - hsl_api_t *p_api; - - SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id)); - - if (NULL == p_api->ip_vrf_base_mask_get) - return SW_NOT_SUPPORTED; - - rv = p_api->ip_vrf_base_mask_get(dev_id, vrf_id, addr); - return rv; -} - -static sw_error_t -_fal_ip_default_route_set(a_uint32_t dev_id, - a_uint32_t droute_id, fal_default_route_t * entry) -{ - sw_error_t rv; - hsl_api_t *p_api; - - SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id)); - - if (NULL == p_api->ip_default_route_set) - return SW_NOT_SUPPORTED; - - rv = p_api->ip_default_route_set(dev_id, droute_id, entry); - return rv; -} - -static sw_error_t -_fal_ip_default_route_get(a_uint32_t dev_id, - a_uint32_t droute_id, fal_default_route_t * entry) -{ - sw_error_t rv; - hsl_api_t *p_api; - - SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id)); - - if (NULL == p_api->ip_default_route_get) - return SW_NOT_SUPPORTED; - - rv = p_api->ip_default_route_get(dev_id, droute_id, entry); - return rv; -} - -static sw_error_t -_fal_ip_host_route_set(a_uint32_t dev_id, - a_uint32_t hroute_id, fal_host_route_t * entry) -{ - sw_error_t rv; - hsl_api_t *p_api; - - SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id)); - - if (NULL == p_api->ip_host_route_set) - return SW_NOT_SUPPORTED; - - rv = p_api->ip_host_route_set(dev_id, hroute_id, entry); - return rv; -} - -static sw_error_t -_fal_ip_host_route_get(a_uint32_t dev_id, - a_uint32_t hroute_id, fal_host_route_t * entry) -{ - sw_error_t rv; - hsl_api_t *p_api; - - SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id)); - - if (NULL == p_api->ip_host_route_get) - return SW_NOT_SUPPORTED; - - rv = p_api->ip_host_route_get(dev_id, hroute_id, entry); - return rv; -} - -static sw_error_t -_fal_ip_wcmp_entry_set(a_uint32_t dev_id, - a_uint32_t wcmp_id, fal_ip_wcmp_t * wcmp) -{ - sw_error_t rv; - hsl_api_t *p_api; - - SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id)); - - if (NULL == p_api->ip_wcmp_entry_set) - return SW_NOT_SUPPORTED; - - rv = p_api->ip_wcmp_entry_set(dev_id, wcmp_id, wcmp); - return rv; -} - -static sw_error_t -_fal_ip_wcmp_entry_get(a_uint32_t dev_id, - a_uint32_t wcmp_id, fal_ip_wcmp_t * wcmp) -{ - sw_error_t rv; - hsl_api_t *p_api; - - SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id)); - - if (NULL == p_api->ip_wcmp_entry_get) - return SW_NOT_SUPPORTED; - - rv = p_api->ip_wcmp_entry_get(dev_id, wcmp_id, wcmp); - return rv; -} - -static sw_error_t -_fal_ip_rfs_ip4_rule_set(a_uint32_t dev_id, fal_ip4_rfs_t * rfs) -{ - sw_error_t rv; - hsl_api_t *p_api; - - SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id)); - - if (NULL == p_api->ip_rfs_ip4_set) - return SW_NOT_SUPPORTED; - - rv = p_api->ip_rfs_ip4_set(dev_id, rfs); - return rv; -} - -static sw_error_t -_fal_ip_rfs_ip6_rule_set(a_uint32_t dev_id, fal_ip6_rfs_t * rfs) -{ - sw_error_t rv; - hsl_api_t *p_api; - - SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id)); - - if (NULL == p_api->ip_rfs_ip6_set) - return SW_NOT_SUPPORTED; - - rv = p_api->ip_rfs_ip6_set(dev_id, rfs); - return rv; -} - -static sw_error_t -_fal_ip_rfs_ip4_rule_del(a_uint32_t dev_id, fal_ip4_rfs_t * rfs) -{ - sw_error_t rv; - hsl_api_t *p_api; - - SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id)); - - if (NULL == p_api->ip_rfs_ip4_del) - return SW_NOT_SUPPORTED; - - rv = p_api->ip_rfs_ip4_del(dev_id, rfs); - return rv; -} - -static sw_error_t -_fal_ip_rfs_ip6_rule_del(a_uint32_t dev_id, fal_ip6_rfs_t * rfs) -{ - sw_error_t rv; - hsl_api_t *p_api; - - SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id)); - - if (NULL == p_api->ip_rfs_ip6_del) - return SW_NOT_SUPPORTED; - - rv = p_api->ip_rfs_ip6_del(dev_id, rfs); - return rv; -} - -static sw_error_t -_fal_default_flow_cmd_set(a_uint32_t dev_id, a_uint32_t vrf_id, - fal_flow_type_t type, fal_default_flow_cmd_t cmd) -{ - sw_error_t rv; - hsl_api_t *p_api; - - SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id)); - - if (NULL == p_api->ip_default_flow_cmd_set) - return SW_NOT_SUPPORTED; - - rv = p_api->ip_default_flow_cmd_set(dev_id, vrf_id, type, cmd); - return rv; -} - -sw_error_t -_fal_default_flow_cmd_get(a_uint32_t dev_id, a_uint32_t vrf_id, - fal_flow_type_t type, fal_default_flow_cmd_t * cmd) -{ - sw_error_t rv; - hsl_api_t *p_api; - - SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id)); - - if (NULL == p_api->ip_default_flow_cmd_get) - return SW_NOT_SUPPORTED; - - rv = p_api->ip_default_flow_cmd_get(dev_id, vrf_id, type, cmd); - return rv; -} - -sw_error_t -_fal_default_rt_flow_cmd_set(a_uint32_t dev_id, a_uint32_t vrf_id, - fal_flow_type_t type, fal_default_flow_cmd_t cmd) -{ - sw_error_t rv; - hsl_api_t *p_api; - - SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id)); - - if (NULL == p_api->ip_default_rt_flow_cmd_set) - return SW_NOT_SUPPORTED; - - rv = p_api->ip_default_rt_flow_cmd_set(dev_id, vrf_id, type, cmd); - return rv; -} - -sw_error_t -_fal_default_rt_flow_cmd_get(a_uint32_t dev_id, a_uint32_t vrf_id, - fal_flow_type_t type, fal_default_flow_cmd_t * cmd) -{ - sw_error_t rv; - hsl_api_t *p_api; - - SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id)); - - if (NULL == p_api->ip_default_rt_flow_cmd_get) - return SW_NOT_SUPPORTED; - - rv = p_api->ip_default_rt_flow_cmd_get(dev_id, vrf_id, type, cmd); - return rv; -} - -sw_error_t -_fal_ip_network_route_get(a_uint32_t dev_id, - a_uint32_t index, a_uint8_t type, - fal_network_route_entry_t *entry) -{ - adpt_api_t *p_api; - sw_error_t rv = SW_OK; - - SW_RTN_ON_NULL(p_api = adpt_api_ptr_get(dev_id)); - - if (NULL == p_api->adpt_ip_network_route_get) - return SW_NOT_SUPPORTED; - - rv = p_api->adpt_ip_network_route_get(dev_id, index, type, entry); - return rv; -} -sw_error_t -_fal_ip_vsi_sg_cfg_get(a_uint32_t dev_id, a_uint32_t vsi, - fal_sg_cfg_t *sg_cfg) -{ - adpt_api_t *p_api; - sw_error_t rv = SW_OK; - - SW_RTN_ON_NULL(p_api = adpt_api_ptr_get(dev_id)); - - if (NULL == p_api->adpt_ip_vsi_sg_cfg_get) - return SW_NOT_SUPPORTED; - - rv = p_api->adpt_ip_vsi_sg_cfg_get(dev_id, vsi, sg_cfg); - return rv; -} - -sw_error_t -_fal_ip_network_route_del(a_uint32_t dev_id, - a_uint32_t index, a_uint8_t type) -{ - adpt_api_t *p_api; - sw_error_t rv = SW_OK; - - SW_RTN_ON_NULL(p_api = adpt_api_ptr_get(dev_id)); - - if (NULL == p_api->adpt_ip_network_route_del) - return SW_NOT_SUPPORTED; - - rv = p_api->adpt_ip_network_route_del(dev_id, index, type); - return rv; -} -sw_error_t -_fal_ip_port_sg_cfg_set(a_uint32_t dev_id, fal_port_t port_id, - fal_sg_cfg_t *sg_cfg) -{ - adpt_api_t *p_api; - sw_error_t rv = SW_OK; - - SW_RTN_ON_NULL(p_api = adpt_api_ptr_get(dev_id)); - - if (NULL == p_api->adpt_ip_port_sg_cfg_set) - return SW_NOT_SUPPORTED; - - rv = p_api->adpt_ip_port_sg_cfg_set(dev_id, port_id, sg_cfg); - return rv; -} -sw_error_t -_fal_ip_port_intf_get(a_uint32_t dev_id, fal_port_t port_id, fal_intf_id_t *id) -{ - adpt_api_t *p_api; - sw_error_t rv = SW_OK; - - SW_RTN_ON_NULL(p_api = adpt_api_ptr_get(dev_id)); - - if (NULL == p_api->adpt_ip_port_intf_get) - return SW_NOT_SUPPORTED; - - rv = p_api->adpt_ip_port_intf_get(dev_id, port_id, id); - return rv; -} -sw_error_t -_fal_ip_vsi_arp_sg_cfg_set(a_uint32_t dev_id, a_uint32_t vsi, - fal_arp_sg_cfg_t *arp_sg_cfg) -{ - adpt_api_t *p_api; - sw_error_t rv = SW_OK; - - SW_RTN_ON_NULL(p_api = adpt_api_ptr_get(dev_id)); - - if (NULL == p_api->adpt_ip_vsi_arp_sg_cfg_set) - return SW_NOT_SUPPORTED; - - rv = p_api->adpt_ip_vsi_arp_sg_cfg_set(dev_id, vsi, arp_sg_cfg); - return rv; -} -sw_error_t -_fal_ip_pub_addr_get(a_uint32_t dev_id, - a_uint32_t index, fal_ip_pub_addr_t *entry) -{ - adpt_api_t *p_api; - sw_error_t rv = SW_OK; - - SW_RTN_ON_NULL(p_api = adpt_api_ptr_get(dev_id)); - - if (NULL == p_api->adpt_ip_pub_addr_get) - return SW_NOT_SUPPORTED; - - rv = p_api->adpt_ip_pub_addr_get(dev_id, index, entry); - return rv; -} -sw_error_t -_fal_ip_port_intf_set(a_uint32_t dev_id, fal_port_t port_id, fal_intf_id_t *id) -{ - adpt_api_t *p_api; - sw_error_t rv = SW_OK; - - SW_RTN_ON_NULL(p_api = adpt_api_ptr_get(dev_id)); - - if (NULL == p_api->adpt_ip_port_intf_set) - return SW_NOT_SUPPORTED; - - rv = p_api->adpt_ip_port_intf_set(dev_id, port_id, id); - return rv; -} -sw_error_t -_fal_ip_vsi_sg_cfg_set(a_uint32_t dev_id, a_uint32_t vsi, - fal_sg_cfg_t *sg_cfg) -{ - adpt_api_t *p_api; - sw_error_t rv = SW_OK; - - SW_RTN_ON_NULL(p_api = adpt_api_ptr_get(dev_id)); - - if (NULL == p_api->adpt_ip_vsi_sg_cfg_set) - return SW_NOT_SUPPORTED; - - rv = p_api->adpt_ip_vsi_sg_cfg_set(dev_id, vsi, sg_cfg); - return rv; -} -sw_error_t -_fal_ip_port_macaddr_set(a_uint32_t dev_id, fal_port_t port_id, - fal_macaddr_entry_t *macaddr) -{ - adpt_api_t *p_api; - sw_error_t rv = SW_OK; - - SW_RTN_ON_NULL(p_api = adpt_api_ptr_get(dev_id)); - - if (NULL == p_api->adpt_ip_port_macaddr_set) - return SW_NOT_SUPPORTED; - - rv = p_api->adpt_ip_port_macaddr_set(dev_id, port_id, macaddr); - return rv; -} -sw_error_t -_fal_ip_vsi_intf_get(a_uint32_t dev_id, a_uint32_t vsi, fal_intf_id_t *id) -{ - adpt_api_t *p_api; - sw_error_t rv = SW_OK; - - SW_RTN_ON_NULL(p_api = adpt_api_ptr_get(dev_id)); - - if (NULL == p_api->adpt_ip_vsi_intf_get) - return SW_NOT_SUPPORTED; - - rv = p_api->adpt_ip_vsi_intf_get(dev_id, vsi, id); - return rv; -} - -sw_error_t -_fal_ip_network_route_add(a_uint32_t dev_id, - a_uint32_t index, - fal_network_route_entry_t *entry) -{ - adpt_api_t *p_api; - sw_error_t rv = SW_OK; - - SW_RTN_ON_NULL(p_api = adpt_api_ptr_get(dev_id)); - - if (NULL == p_api->adpt_ip_network_route_add) - return SW_NOT_SUPPORTED; - - rv = p_api->adpt_ip_network_route_add(dev_id, index, entry); - return rv; -} -sw_error_t -_fal_ip_port_sg_cfg_get(a_uint32_t dev_id, fal_port_t port_id, - fal_sg_cfg_t *sg_cfg) -{ - adpt_api_t *p_api; - sw_error_t rv = SW_OK; - - SW_RTN_ON_NULL(p_api = adpt_api_ptr_get(dev_id)); - - if (NULL == p_api->adpt_ip_port_sg_cfg_get) - return SW_NOT_SUPPORTED; - - rv = p_api->adpt_ip_port_sg_cfg_get(dev_id, port_id, sg_cfg); - return rv; -} -sw_error_t -_fal_ip_intf_get( - a_uint32_t dev_id, - a_uint32_t index, - fal_intf_entry_t *entry) -{ - adpt_api_t *p_api; - sw_error_t rv = SW_OK; - - SW_RTN_ON_NULL(p_api = adpt_api_ptr_get(dev_id)); - - if (NULL == p_api->adpt_ip_intf_get) - return SW_NOT_SUPPORTED; - - rv = p_api->adpt_ip_intf_get(dev_id, index, entry); - return rv; -} -sw_error_t -_fal_ip_pub_addr_set(a_uint32_t dev_id, - a_uint32_t index, fal_ip_pub_addr_t *entry) -{ - adpt_api_t *p_api; - sw_error_t rv = SW_OK; - - SW_RTN_ON_NULL(p_api = adpt_api_ptr_get(dev_id)); - - if (NULL == p_api->adpt_ip_pub_addr_set) - return SW_NOT_SUPPORTED; - - rv = p_api->adpt_ip_pub_addr_set(dev_id, index, entry); - return rv; -} -sw_error_t -_fal_ip_route_mismatch_get(a_uint32_t dev_id, fal_fwd_cmd_t *cmd) -{ - adpt_api_t *p_api; - sw_error_t rv = SW_OK; - - SW_RTN_ON_NULL(p_api = adpt_api_ptr_get(dev_id)); - - if (NULL == p_api->adpt_ip_route_mismatch_get) - return SW_NOT_SUPPORTED; - - rv = p_api->adpt_ip_route_mismatch_get(dev_id, cmd); - return rv; -} -sw_error_t -_fal_ip_vsi_arp_sg_cfg_get(a_uint32_t dev_id, a_uint32_t vsi, - fal_arp_sg_cfg_t *arp_sg_cfg) -{ - adpt_api_t *p_api; - sw_error_t rv = SW_OK; - - SW_RTN_ON_NULL(p_api = adpt_api_ptr_get(dev_id)); - - if (NULL == p_api->adpt_ip_vsi_arp_sg_cfg_get) - return SW_NOT_SUPPORTED; - - rv = p_api->adpt_ip_vsi_arp_sg_cfg_get(dev_id, vsi, arp_sg_cfg); - return rv; -} -sw_error_t -_fal_ip_port_arp_sg_cfg_set(a_uint32_t dev_id, fal_port_t port_id, - fal_arp_sg_cfg_t *arp_sg_cfg) -{ - adpt_api_t *p_api; - sw_error_t rv = SW_OK; - - SW_RTN_ON_NULL(p_api = adpt_api_ptr_get(dev_id)); - - if (NULL == p_api->adpt_ip_port_arp_sg_cfg_set) - return SW_NOT_SUPPORTED; - - rv = p_api->adpt_ip_port_arp_sg_cfg_set(dev_id, port_id, arp_sg_cfg); - return rv; -} -sw_error_t -_fal_ip_vsi_mc_mode_set(a_uint32_t dev_id, a_uint32_t vsi, - fal_mc_mode_cfg_t *cfg) -{ - adpt_api_t *p_api; - sw_error_t rv = SW_OK; - - SW_RTN_ON_NULL(p_api = adpt_api_ptr_get(dev_id)); - - if (NULL == p_api->adpt_ip_vsi_mc_mode_set) - return SW_NOT_SUPPORTED; - - rv = p_api->adpt_ip_vsi_mc_mode_set(dev_id, vsi, cfg); - return rv; -} -sw_error_t -_fal_ip_vsi_intf_set(a_uint32_t dev_id, a_uint32_t vsi, fal_intf_id_t *id) -{ - adpt_api_t *p_api; - sw_error_t rv = SW_OK; - - SW_RTN_ON_NULL(p_api = adpt_api_ptr_get(dev_id)); - - if (NULL == p_api->adpt_ip_vsi_intf_set) - return SW_NOT_SUPPORTED; - - rv = p_api->adpt_ip_vsi_intf_set(dev_id, vsi, id); - return rv; -} -sw_error_t -_fal_ip_nexthop_get(a_uint32_t dev_id, a_uint32_t index, fal_ip_nexthop_t *entry) -{ - adpt_api_t *p_api; - sw_error_t rv = SW_OK; - - SW_RTN_ON_NULL(p_api = adpt_api_ptr_get(dev_id)); - - if (NULL == p_api->adpt_ip_nexthop_get) - return SW_NOT_SUPPORTED; - - rv = p_api->adpt_ip_nexthop_get(dev_id, index, entry); - return rv; -} -sw_error_t -_fal_ip_route_mismatch_set(a_uint32_t dev_id, fal_fwd_cmd_t cmd) -{ - adpt_api_t *p_api; - sw_error_t rv = SW_OK; - - SW_RTN_ON_NULL(p_api = adpt_api_ptr_get(dev_id)); - - if (NULL == p_api->adpt_ip_route_mismatch_set) - return SW_NOT_SUPPORTED; - - rv = p_api->adpt_ip_route_mismatch_set(dev_id, cmd); - return rv; -} -sw_error_t -_fal_ip_intf_set( - a_uint32_t dev_id, - a_uint32_t index, - fal_intf_entry_t *entry) -{ - adpt_api_t *p_api; - sw_error_t rv = SW_OK; - - SW_RTN_ON_NULL(p_api = adpt_api_ptr_get(dev_id)); - - if (NULL == p_api->adpt_ip_intf_set) - return SW_NOT_SUPPORTED; - - rv = p_api->adpt_ip_intf_set(dev_id, index, entry); - return rv; -} -sw_error_t -_fal_ip_vsi_mc_mode_get(a_uint32_t dev_id, a_uint32_t vsi, - fal_mc_mode_cfg_t *cfg) -{ - adpt_api_t *p_api; - sw_error_t rv = SW_OK; - - SW_RTN_ON_NULL(p_api = adpt_api_ptr_get(dev_id)); - - if (NULL == p_api->adpt_ip_vsi_mc_mode_get) - return SW_NOT_SUPPORTED; - - rv = p_api->adpt_ip_vsi_mc_mode_get(dev_id, vsi, cfg); - return rv; -} -sw_error_t -_fal_ip_port_macaddr_get(a_uint32_t dev_id, fal_port_t port_id, - fal_macaddr_entry_t *macaddr) -{ - adpt_api_t *p_api; - sw_error_t rv = SW_OK; - - SW_RTN_ON_NULL(p_api = adpt_api_ptr_get(dev_id)); - - if (NULL == p_api->adpt_ip_port_macaddr_get) - return SW_NOT_SUPPORTED; - - rv = p_api->adpt_ip_port_macaddr_get(dev_id, port_id, macaddr); - return rv; -} -sw_error_t -_fal_ip_port_arp_sg_cfg_get(a_uint32_t dev_id, fal_port_t port_id, - fal_arp_sg_cfg_t *arp_sg_cfg) -{ - adpt_api_t *p_api; - sw_error_t rv = SW_OK; - - SW_RTN_ON_NULL(p_api = adpt_api_ptr_get(dev_id)); - - if (NULL == p_api->adpt_ip_port_arp_sg_cfg_get) - return SW_NOT_SUPPORTED; - - rv = p_api->adpt_ip_port_arp_sg_cfg_get(dev_id, port_id, arp_sg_cfg); - return rv; -} -sw_error_t -_fal_ip_nexthop_set(a_uint32_t dev_id, - a_uint32_t index, fal_ip_nexthop_t *entry) -{ - adpt_api_t *p_api; - sw_error_t rv = SW_OK; - - SW_RTN_ON_NULL(p_api = adpt_api_ptr_get(dev_id)); - - if (NULL == p_api->adpt_ip_nexthop_set) - return SW_NOT_SUPPORTED; - - rv = p_api->adpt_ip_nexthop_set(dev_id, index, entry); - return rv; -} - -sw_error_t -_fal_ip_global_ctrl_set(a_uint32_t dev_id, fal_ip_global_cfg_t *cfg) -{ - adpt_api_t *p_api; - sw_error_t rv = SW_OK; - - SW_RTN_ON_NULL(p_api = adpt_api_ptr_get(dev_id)); - - if (NULL == p_api->adpt_ip_global_ctrl_set) - return SW_NOT_SUPPORTED; - - rv = p_api->adpt_ip_global_ctrl_set(dev_id, cfg); - return rv; -} - -sw_error_t -_fal_ip_global_ctrl_get(a_uint32_t dev_id, fal_ip_global_cfg_t *cfg) -{ - adpt_api_t *p_api; - sw_error_t rv = SW_OK; - - SW_RTN_ON_NULL(p_api = adpt_api_ptr_get(dev_id)); - - if (NULL == p_api->adpt_ip_global_ctrl_get) - return SW_NOT_SUPPORTED; - - rv = p_api->adpt_ip_global_ctrl_get(dev_id, cfg); - return rv; -} - -/*insert flag for inner fal, don't remove it*/ - -/** - * @brief Add one host entry to one particular device. - * @details Comments: - * For ISIS the intf_id parameter in host_entry means vlan id. - Before host entry added related interface entry and ip6 base address - must be set at first. - Hardware entry id will be returned. - * @param[in] dev_id device id - * @param[in] host_entry host entry parameter - * @return SW_OK or error code - */ -sw_error_t -fal_ip_host_add(a_uint32_t dev_id, fal_host_entry_t * host_entry) -{ - sw_error_t rv; - - FAL_API_LOCK; - rv = _fal_ip_host_add(dev_id, host_entry); - FAL_API_UNLOCK; - return rv; -} - -/** - * @brief Delete one host entry from one particular device. - * @details Comments: - * For ISIS the intf_id parameter in host_entry means vlan id. - Before host entry deleted related interface entry and ip6 base address - must be set atfirst. - For del_mode please refer IP entry operation flags. - * @param[in] dev_id device id - * @param[in] del_mode delete operation mode - * @param[in] host_entry host entry parameter - * @return SW_OK or error code - */ -sw_error_t -fal_ip_host_del(a_uint32_t dev_id, a_uint32_t del_mode, - fal_host_entry_t * host_entry) -{ - sw_error_t rv; - - FAL_API_LOCK; - rv = _fal_ip_host_del(dev_id, del_mode, host_entry); - FAL_API_UNLOCK; - return rv; -} - -/** - * @brief Get one host entry from one particular device. - * @details Comments: - * For ISIS the intf_id parameter in host_entry means vlan id. - Before host entry deleted related interface entry and ip6 base address - must be set atfirst. - For get_mode please refer IP entry operation flags. - * @param[in] dev_id device id - * @param[in] get_mode get operation mode - * @param[out] host_entry host entry parameter - * @return SW_OK or error code - */ -sw_error_t -fal_ip_host_get(a_uint32_t dev_id, a_uint32_t get_mode, - fal_host_entry_t * host_entry) -{ - sw_error_t rv; - - FAL_API_LOCK; - rv = _fal_ip_host_get(dev_id, get_mode, host_entry); - FAL_API_UNLOCK; - return rv; -} - -/** - * @brief Next one host entry from one particular device. - * @details Comments: - * For ISIS the intf_id parameter in host_entry means vlan id. - Before host entry deleted related interface entry and ip6 base address - must be set atfirst. - For next_mode please refer IP entry operation flags. - For get the first entry please set entry id as FAL_NEXT_ENTRY_FIRST_ID - * @param[in] dev_id device id - * @param[in] next_mode next operation mode - * @param[out] host_entry host entry parameter - * @return SW_OK or error code - */ -sw_error_t -fal_ip_host_next(a_uint32_t dev_id, a_uint32_t next_mode, - fal_host_entry_t * host_entry) -{ - sw_error_t rv; - - FAL_API_LOCK; - rv = _fal_ip_host_next(dev_id, next_mode, host_entry); - FAL_API_UNLOCK; - return rv; -} - -/** - * @brief Bind one counter entry to one host entry on one particular device. - * @param[in] dev_id device id - * @param[in] entry_id host entry id - * @param[in] cnt_id counter entry id - * @param[in] enable A_TRUE means bind, A_FALSE means unbind - * @return SW_OK or error code - */ -sw_error_t -fal_ip_host_counter_bind(a_uint32_t dev_id, a_uint32_t entry_id, - a_uint32_t cnt_id, a_bool_t enable) -{ - sw_error_t rv; - - FAL_API_LOCK; - rv = _fal_ip_host_counter_bind(dev_id, entry_id, cnt_id, enable); - FAL_API_UNLOCK; - return rv; -} - -/** - * @brief Bind one pppoe session entry to one host entry on one particular device. - * @param[in] dev_id device id - * @param[in] entry_id host entry id - * @param[in] pppoe_id pppoe session entry id - * @param[in] enable A_TRUE means bind, A_FALSE means unbind - * @return SW_OK or error code - */ -sw_error_t -fal_ip_host_pppoe_bind(a_uint32_t dev_id, a_uint32_t entry_id, - a_uint32_t pppoe_id, a_bool_t enable) -{ - sw_error_t rv; - - FAL_API_LOCK; - rv = _fal_ip_host_pppoe_bind(dev_id, entry_id, pppoe_id, enable); - FAL_API_UNLOCK; - return rv; -} - -/** - * @brief Set arp packets type to learn on one particular port. - * @param[in] dev_id device id - * @param[in] port_id port id - * @param[in] flags arp type FAL_ARP_LEARN_REQ and/or FAL_ARP_LEARN_ACK - * @return SW_OK or error code - */ -sw_error_t -fal_ip_pt_arp_learn_set(a_uint32_t dev_id, fal_port_t port_id, a_uint32_t flags) -{ - sw_error_t rv; - - FAL_API_LOCK; - rv = _fal_ip_pt_arp_learn_set(dev_id, port_id, flags); - FAL_API_UNLOCK; - return rv; -} - -/** - * @brief Get arp packets type to learn on one particular port. - * @param[in] dev_id device id - * @param[in] port_id port id - * @param[out] flags arp type FAL_ARP_LEARN_REQ and/or FAL_ARP_LEARN_ACK - * @return SW_OK or error code - */ -sw_error_t -fal_ip_pt_arp_learn_get(a_uint32_t dev_id, fal_port_t port_id, - a_uint32_t * flags) -{ - sw_error_t rv; - - FAL_API_LOCK; - rv = _fal_ip_pt_arp_learn_get(dev_id, port_id, flags); - FAL_API_UNLOCK; - return rv; -} - -/** - * @brief Set arp packets type to learn on one particular device. - * @param[in] dev_id device id - * @param[in] mode learning mode - * @return SW_OK or error code - */ -sw_error_t -fal_ip_arp_learn_set(a_uint32_t dev_id, fal_arp_learn_mode_t mode) -{ - sw_error_t rv; - - FAL_API_LOCK; - rv = _fal_ip_arp_learn_set(dev_id, mode); - FAL_API_UNLOCK; - return rv; -} - -/** - * @brief Get arp packets type to learn on one particular device. - * @param[in] dev_id device id - * @param[out] mode learning mode - * @return SW_OK or error code - */ -sw_error_t -fal_ip_arp_learn_get(a_uint32_t dev_id, fal_arp_learn_mode_t * mode) -{ - sw_error_t rv; - - FAL_API_LOCK; - rv = _fal_ip_arp_learn_get(dev_id, mode); - FAL_API_UNLOCK; - return rv; -} - -/** - * @brief Set ip packets source guarding mode on one particular port. - * @param[in] dev_id device id - * @param[in] port_id port id - * @param[in] mode source guarding mode - * @return SW_OK or error code - */ -sw_error_t -fal_ip_source_guard_set(a_uint32_t dev_id, fal_port_t port_id, - fal_source_guard_mode_t mode) -{ - sw_error_t rv; - - FAL_API_LOCK; - rv = _fal_ip_source_guard_set(dev_id, port_id, mode); - FAL_API_UNLOCK; - return rv; -} - -/** - * @brief Get ip packets source guarding mode on one particular port. - * @param[in] dev_id device id - * @param[in] port_id port id - * @param[out] mode source guarding mode - * @return SW_OK or error code - */ -sw_error_t -fal_ip_source_guard_get(a_uint32_t dev_id, fal_port_t port_id, - fal_source_guard_mode_t * mode) -{ - sw_error_t rv; - - FAL_API_LOCK; - rv = _fal_ip_source_guard_get(dev_id, port_id, mode); - FAL_API_UNLOCK; - return rv; -} - -/** - * @brief Set unkonw source ip packets forwarding command on one particular device. - * @details Comments: - * This settin is no meaning when ip source guard not enable - * @param[in] dev_id device id - * @param[in] cmd forwarding command - * @return SW_OK or error code - */ -sw_error_t -fal_ip_unk_source_cmd_set(a_uint32_t dev_id, fal_fwd_cmd_t cmd) -{ - sw_error_t rv; - - FAL_API_LOCK; - rv = _fal_ip_unk_source_cmd_set(dev_id, cmd); - FAL_API_UNLOCK; - return rv; -} - -/** - * @brief Get unkonw source ip packets forwarding command on one particular device. - * @param[in] dev_id device id - * @param[out] cmd forwarding command - * @return SW_OK or error code - */ -sw_error_t -fal_ip_unk_source_cmd_get(a_uint32_t dev_id, fal_fwd_cmd_t * cmd) -{ - sw_error_t rv; - - FAL_API_LOCK; - rv = _fal_ip_unk_source_cmd_get(dev_id, cmd); - FAL_API_UNLOCK; - return rv; -} - -/** - * @brief Set arp packets source guarding mode on one particular port. - * @param[in] dev_id device id - * @param[in] port_id port id - * @param[in] mode source guarding mode - * @return SW_OK or error code - */ -sw_error_t -fal_ip_arp_guard_set(a_uint32_t dev_id, fal_port_t port_id, - fal_source_guard_mode_t mode) -{ - sw_error_t rv; - - FAL_API_LOCK; - rv = _fal_ip_arp_guard_set(dev_id, port_id, mode); - FAL_API_UNLOCK; - return rv; -} - -/** - * @brief Get arp packets source guarding mode on one particular port. - * @param[in] dev_id device id - * @param[in] port_id port id - * @param[out] mode source guarding mode - * @return SW_OK or error code - */ -sw_error_t -fal_ip_arp_guard_get(a_uint32_t dev_id, fal_port_t port_id, - fal_source_guard_mode_t * mode) -{ - sw_error_t rv; - - FAL_API_LOCK; - rv = _fal_ip_arp_guard_get(dev_id, port_id, mode); - FAL_API_UNLOCK; - return rv; -} - -/** - * @brief Set unkonw source arp packets forwarding command on one particular device. - * @details Comments: - * This settin is no meaning when arp source guard not enable - * @param[in] dev_id device id - * @param[in] cmd forwarding command - * @return SW_OK or error code - */ -sw_error_t -fal_arp_unk_source_cmd_set(a_uint32_t dev_id, fal_fwd_cmd_t cmd) -{ - sw_error_t rv; - - FAL_API_LOCK; - rv = _fal_arp_unk_source_cmd_set(dev_id, cmd); - FAL_API_UNLOCK; - return rv; -} - -/** - * @brief Get unkonw source arp packets forwarding command on one particular device. - * @param[in] dev_id device id - * @param[out] cmd forwarding command - * @return SW_OK or error code - */ -sw_error_t -fal_arp_unk_source_cmd_get(a_uint32_t dev_id, fal_fwd_cmd_t * cmd) -{ - sw_error_t rv; - - FAL_API_LOCK; - rv = _fal_arp_unk_source_cmd_get(dev_id, cmd); - FAL_API_UNLOCK; - return rv; -} - -/** - * @brief Set IP unicast routing status on one particular device. - * @param[in] dev_id device id - * @param[in] enable A_TRUE or A_FALSE - * @return SW_OK or error code - */ -sw_error_t -fal_ip_route_status_set(a_uint32_t dev_id, a_bool_t enable) -{ - sw_error_t rv; - - FAL_API_LOCK; - rv = _fal_ip_route_status_set(dev_id, enable); - FAL_API_UNLOCK; - return rv; -} - -/** - * @brief Get IP unicast routing status on one particular device. - * @param[in] dev_id device id - * @param[out] enable A_TRUE or A_FALSE - * @return SW_OK or error code - */ -sw_error_t -fal_ip_route_status_get(a_uint32_t dev_id, a_bool_t * enable) -{ - sw_error_t rv; - - FAL_API_LOCK; - rv = _fal_ip_route_status_get(dev_id, enable); - FAL_API_UNLOCK; - return rv; -} - -/** - * @brief Add one interface entry to one particular device. - * @param[in] dev_id device id - * @param[in] entry interface entry - * @return SW_OK or error code - */ -sw_error_t -fal_ip_intf_entry_add(a_uint32_t dev_id, fal_intf_mac_entry_t * entry) -{ - sw_error_t rv; - - FAL_API_LOCK; - rv = _fal_ip_intf_entry_add(dev_id, entry); - FAL_API_UNLOCK; - return rv; -} - -/** - * @brief Delete one interface entry from one particular device. - * @param[in] dev_id device id - * @param[in] del_mode delete operation mode - * @param[in] entry interface entry - * @return SW_OK or error code - */ -sw_error_t -fal_ip_intf_entry_del(a_uint32_t dev_id, a_uint32_t del_mode, - fal_intf_mac_entry_t * entry) -{ - sw_error_t rv; - - FAL_API_LOCK; - rv = _fal_ip_intf_entry_del(dev_id, del_mode, entry); - FAL_API_UNLOCK; - return rv; -} - -/** - * @brief Next one interface entry from one particular device. - * @param[in] dev_id device id - * @param[in] next_mode next operation mode - * @param[out] entry interface entry - * @return SW_OK or error code - */ -sw_error_t -fal_ip_intf_entry_next(a_uint32_t dev_id, a_uint32_t next_mode, - fal_intf_mac_entry_t * entry) -{ - sw_error_t rv; - - FAL_API_LOCK; - rv = _fal_ip_intf_entry_next(dev_id, next_mode, entry); - FAL_API_UNLOCK; - return rv; -} - -/** - * @brief Set IP host entry aging time on one particular device. - * @details Comments: - * This operation will set dynamic entry aging time on a particular device. - * The unit of time is second. Because different device has differnet - * hardware granularity function will return actual time in hardware. - * @param[in] dev_id device id - * @param[in] time aging time - * @param[out] time actual aging time - * @return SW_OK or error code - */ -sw_error_t -fal_ip_age_time_set(a_uint32_t dev_id, a_uint32_t * time) -{ - sw_error_t rv; - - FAL_API_LOCK; - rv = _fal_ip_age_time_set(dev_id, time); - FAL_API_UNLOCK; - return rv; -} - -/** - * @brief Get IP host entry aging time on one particular device. - * @param[in] dev_id device id - * @param[out] time aging time - * @return SW_OK or error code - */ -sw_error_t -fal_ip_age_time_get(a_uint32_t dev_id, a_uint32_t * time) -{ - sw_error_t rv; - - FAL_API_LOCK; - rv = _fal_ip_age_time_get(dev_id, time); - FAL_API_UNLOCK; - return rv; -} - -/** - * @brief Set IP WCMP hash key mode. - * @param[in] dev_id device id - * @param[in] hash_mode hash mode - * @return SW_OK or error code - */ -sw_error_t -fal_ip_wcmp_hash_mode_set(a_uint32_t dev_id, a_uint32_t hash_mode) -{ - sw_error_t rv; - - FAL_API_LOCK; - rv = _fal_ip_wcmp_hash_mode_set(dev_id, hash_mode); - FAL_API_UNLOCK; - return rv; -} - -/** - * @brief Get IP WCMP hash key mode. - * @param[in] dev_id device id - * @param[out] hash_mode hash mode - * @return SW_OK or error code - */ -sw_error_t -fal_ip_wcmp_hash_mode_get(a_uint32_t dev_id, a_uint32_t * hash_mode) -{ - sw_error_t rv; - - FAL_API_LOCK; - rv = _fal_ip_wcmp_hash_mode_get(dev_id, hash_mode); - FAL_API_UNLOCK; - return rv; -} - -sw_error_t -fal_ip_vrf_base_addr_set(a_uint32_t dev_id, - a_uint32_t vrf_id, fal_ip4_addr_t addr) -{ - sw_error_t rv; - - FAL_API_LOCK; - rv = _fal_ip_vrf_base_addr_set(dev_id, vrf_id, addr); - FAL_API_UNLOCK; - return rv; -} - -sw_error_t -fal_ip_vrf_base_addr_get(a_uint32_t dev_id, - a_uint32_t vrf_id, fal_ip4_addr_t * addr) -{ - sw_error_t rv; - - FAL_API_LOCK; - rv = _fal_ip_vrf_base_addr_get(dev_id, vrf_id, addr); - FAL_API_UNLOCK; - return rv; -} - -sw_error_t -fal_ip_vrf_base_mask_set(a_uint32_t dev_id, - a_uint32_t vrf_id, fal_ip4_addr_t addr) -{ - sw_error_t rv; - - FAL_API_LOCK; - rv = _fal_ip_vrf_base_mask_set(dev_id, vrf_id, addr); - FAL_API_UNLOCK; - return rv; -} - -sw_error_t -fal_ip_vrf_base_mask_get(a_uint32_t dev_id, - a_uint32_t vrf_id, fal_ip4_addr_t * addr) -{ - sw_error_t rv; - - FAL_API_LOCK; - rv = _fal_ip_vrf_base_mask_get(dev_id, vrf_id, addr); - FAL_API_UNLOCK; - return rv; -} - -sw_error_t -fal_ip_default_route_set(a_uint32_t dev_id, - a_uint32_t droute_id, fal_default_route_t * entry) -{ - sw_error_t rv; - - FAL_API_LOCK; - rv = _fal_ip_default_route_set(dev_id, droute_id, entry); - FAL_API_UNLOCK; - return rv; -} - -sw_error_t -fal_ip_default_route_get(a_uint32_t dev_id, - a_uint32_t droute_id, fal_default_route_t * entry) -{ - sw_error_t rv; - - FAL_API_LOCK; - rv = _fal_ip_default_route_get(dev_id, droute_id, entry); - FAL_API_UNLOCK; - return rv; -} - -sw_error_t -fal_ip_host_route_set(a_uint32_t dev_id, - a_uint32_t hroute_id, fal_host_route_t * entry) -{ - sw_error_t rv; - - FAL_API_LOCK; - rv = _fal_ip_host_route_set(dev_id, hroute_id, entry); - FAL_API_UNLOCK; - return rv; -} - -sw_error_t -fal_ip_host_route_get(a_uint32_t dev_id, - a_uint32_t hroute_id, fal_host_route_t * entry) -{ - sw_error_t rv; - - FAL_API_LOCK; - rv = _fal_ip_host_route_get(dev_id, hroute_id, entry); - FAL_API_UNLOCK; - return rv; -} - -sw_error_t -fal_ip_wcmp_entry_set(a_uint32_t dev_id, a_uint32_t wcmp_id, - fal_ip_wcmp_t * wcmp) -{ - sw_error_t rv; - - FAL_API_LOCK; - rv = _fal_ip_wcmp_entry_set(dev_id, wcmp_id, wcmp); - FAL_API_UNLOCK; - return rv; -} - -sw_error_t -fal_ip_wcmp_entry_get(a_uint32_t dev_id, a_uint32_t wcmp_id, - fal_ip_wcmp_t * wcmp) -{ - sw_error_t rv; - - FAL_API_LOCK; - rv = _fal_ip_wcmp_entry_get(dev_id, wcmp_id, wcmp); - FAL_API_UNLOCK; - return rv; -} - -sw_error_t -fal_ip_rfs_ip4_rule_set(a_uint32_t dev_id, fal_ip4_rfs_t * rfs) -{ - sw_error_t rv; - - FAL_API_LOCK; - rv = _fal_ip_rfs_ip4_rule_set(dev_id, rfs); - FAL_API_UNLOCK; - return rv; -} - -sw_error_t -fal_ip_rfs_ip6_rule_set(a_uint32_t dev_id, fal_ip6_rfs_t * rfs) -{ - sw_error_t rv; - - FAL_API_LOCK; - rv = _fal_ip_rfs_ip6_rule_set(dev_id, rfs); - FAL_API_UNLOCK; - return rv; -} - -sw_error_t -fal_ip_rfs_ip4_rule_del(a_uint32_t dev_id, fal_ip4_rfs_t * rfs) -{ - sw_error_t rv; - - FAL_API_LOCK; - rv = _fal_ip_rfs_ip4_rule_del(dev_id, rfs); - FAL_API_UNLOCK; - return rv; -} - -sw_error_t -fal_ip_rfs_ip6_rule_del(a_uint32_t dev_id, fal_ip6_rfs_t * rfs) -{ - sw_error_t rv; - - FAL_API_LOCK; - rv = _fal_ip_rfs_ip6_rule_del(dev_id, rfs); - FAL_API_UNLOCK; - return rv; -} - -int ssdk_rfs_ip4_rule_set(u16 vid, u32 ip, u8* mac, u8 ldb, int is_set) -{ - fal_ip4_rfs_t entry; - memcpy(&entry.mac_addr, mac, 6); - entry.ip4_addr = ip; - entry.load_balance = ldb; - entry.vid = vid; - if(is_set) - return fal_ip_rfs_ip4_rule_set(0, &entry); - else - return fal_ip_rfs_ip4_rule_del(0, &entry); -} - -int ssdk_rfs_ip6_rule_set(u16 vid, u8* ip, u8* mac, u8 ldb, int is_set) -{ - fal_ip6_rfs_t entry; - memcpy(&entry.mac_addr, mac, 6); - memcpy(&entry.ip6_addr, ip, sizeof(entry.ip6_addr)); - entry.load_balance = ldb; - entry.vid = vid; - if(is_set) - return fal_ip_rfs_ip6_rule_set(0, &entry); - else - return fal_ip_rfs_ip6_rule_del(0, &entry); -} - - -#if 0 -int -ssdk_ip_rfs_ip4_rule_set(ssdk_ip4_rfs_t * rfs) -{ - fal_ip4_rfs_t entry; - memcpy(&entry.mac_addr, rfs->mac_addr, 6); - entry.ip4_addr = rfs->ip4_addr; - entry.load_balance = rfs->load_balance; - entry.vid = rfs->vid; - return fal_ip_rfs_ip4_rule_set(0, &entry); -} - -int -ssdk_ip_rfs_ip4_rule_del(ssdk_ip4_rfs_t * rfs) -{ - fal_ip4_rfs_t entry; - memcpy(&entry.mac_addr, rfs->mac_addr, 6); - entry.ip4_addr = rfs->ip4_addr; - entry.load_balance = rfs->load_balance; - entry.vid = rfs->vid; - return fal_ip_rfs_ip4_rule_del(0, &entry); -} - -int -ssdk_ip_rfs_ip6_rule_set(ssdk_ip6_rfs_t * rfs) -{ - fal_ip6_rfs_t entry; - memcpy(&entry.mac_addr, rfs->mac_addr, 6); - memcpy(&entry.ip6_addr, rfs->ip6_addr, sizeof(rfs->ip6_addr)); - entry.load_balance = rfs->load_balance; - entry.vid = rfs->vid; - return fal_ip_rfs_ip6_rule_set(0, &entry); -} - -int -ssdk_ip_rfs_ip6_rule_del(ssdk_ip6_rfs_t * rfs) -{ - fal_ip6_rfs_t entry; - memcpy(&entry.mac_addr, rfs->mac_addr, 6); - memcpy(&entry.ip6_addr, rfs->ip6_addr, sizeof(rfs->ip6_addr)); - entry.load_balance = rfs->load_balance; - entry.vid = rfs->vid; - return fal_ip_rfs_ip6_rule_del(0, &entry); -} - - - -EXPORT_SYMBOL(ssdk_ip_rfs_ip4_rule_set); -EXPORT_SYMBOL(ssdk_ip_rfs_ip4_rule_del); -EXPORT_SYMBOL(ssdk_ip_rfs_ip6_rule_set); -EXPORT_SYMBOL(ssdk_ip_rfs_ip6_rule_del); -#endif -/** - * @brief Set default flow forward command - * @param[in] dev_id device id - * @param[in] vrf_id VRF route index, from 0~7 - * @param[in] type traffic flow type pass through switch core - * @param[in] fal_default_flow_cmd_t default flow forward command when flow table mismatch - * @return SW_OK or error code - */ -sw_error_t -fal_default_flow_cmd_set(a_uint32_t dev_id, a_uint32_t vrf_id, - fal_flow_type_t type, fal_default_flow_cmd_t cmd) -{ - sw_error_t rv; - - FAL_API_LOCK; - rv = _fal_default_flow_cmd_set(dev_id, vrf_id, type, cmd); - FAL_API_UNLOCK; - return rv; -} - -/** - * @brief Get flow type traffic default forward command. - * @param[in] dev_id device id - * @param[in] vrf_id VRF route index, from 0~7 - * @param[in] type traffic flow type pass through switch core - * @param[out] fal_default_flow_cmd_t default flow forward command when flow table mismatch - * @return SW_OK or error code - */ -sw_error_t -fal_default_flow_cmd_get(a_uint32_t dev_id, a_uint32_t vrf_id, - fal_flow_type_t type, fal_default_flow_cmd_t * cmd) -{ - sw_error_t rv; - - FAL_API_LOCK; - rv = _fal_default_flow_cmd_get(dev_id, vrf_id, type, cmd); - FAL_API_UNLOCK; - return rv; -} - -/** - * @brief Set default route flow forward command - * @param[in] dev_id device id - * @param[in] vrf_id VRF route index, from 0~7 - * @param[in] type traffic flow type pass through switch core - * @param[in] fal_default_flow_cmd_t default route flow forward command when flow table mismatch - * @return SW_OK or error code - */ -sw_error_t -fal_default_rt_flow_cmd_set(a_uint32_t dev_id, a_uint32_t vrf_id, - fal_flow_type_t type, fal_default_flow_cmd_t cmd) -{ - sw_error_t rv; - - FAL_API_LOCK; - rv = _fal_default_rt_flow_cmd_set(dev_id, vrf_id, type, cmd); - FAL_API_UNLOCK; - return rv; -} - -/** - * @brief Get flow type traffic default forward command. - * @param[in] dev_id device id - * @param[in] vrf_id VRF route index, from 0~7 - * @param[in] type traffic flow type pass through switch core - * @param[out] fal_default_flow_cmd_t default route flow forward command when flow table mismatch - * @return SW_OK or error code - */ -sw_error_t -fal_default_rt_flow_cmd_get(a_uint32_t dev_id, a_uint32_t vrf_id, - fal_flow_type_t type, fal_default_flow_cmd_t * cmd) -{ - sw_error_t rv; - - FAL_API_LOCK; - rv = _fal_default_rt_flow_cmd_get(dev_id, vrf_id, type, cmd); - FAL_API_UNLOCK; - return rv; -} - -sw_error_t -fal_ip_network_route_get(a_uint32_t dev_id, - a_uint32_t index, a_uint8_t type, - fal_network_route_entry_t *entry) -{ - sw_error_t rv = SW_OK; - - FAL_API_LOCK; - rv = _fal_ip_network_route_get(dev_id, index, type, entry); - FAL_API_UNLOCK; - return rv; -} -sw_error_t -fal_ip_vsi_sg_cfg_get(a_uint32_t dev_id, a_uint32_t vsi, - fal_sg_cfg_t *sg_cfg) -{ - sw_error_t rv = SW_OK; - - FAL_API_LOCK; - rv = _fal_ip_vsi_sg_cfg_get(dev_id, vsi, sg_cfg); - FAL_API_UNLOCK; - return rv; -} - -sw_error_t -fal_ip_network_route_del(a_uint32_t dev_id, - a_uint32_t index, a_uint8_t type) -{ - sw_error_t rv = SW_OK; - - FAL_API_LOCK; - rv = _fal_ip_network_route_del(dev_id, index, type); - FAL_API_UNLOCK; - return rv; -} -sw_error_t -fal_ip_port_sg_cfg_set(a_uint32_t dev_id, fal_port_t port_id, - fal_sg_cfg_t *sg_cfg) -{ - sw_error_t rv = SW_OK; - - FAL_API_LOCK; - rv = _fal_ip_port_sg_cfg_set(dev_id, port_id, sg_cfg); - FAL_API_UNLOCK; - return rv; -} -sw_error_t -fal_ip_port_intf_get(a_uint32_t dev_id, fal_port_t port_id, fal_intf_id_t *id) -{ - sw_error_t rv = SW_OK; - - FAL_API_LOCK; - rv = _fal_ip_port_intf_get(dev_id, port_id, id); - FAL_API_UNLOCK; - return rv; -} -sw_error_t -fal_ip_vsi_arp_sg_cfg_set(a_uint32_t dev_id, a_uint32_t vsi, - fal_arp_sg_cfg_t *arp_sg_cfg) -{ - sw_error_t rv = SW_OK; - - FAL_API_LOCK; - rv = _fal_ip_vsi_arp_sg_cfg_set(dev_id, vsi, arp_sg_cfg); - FAL_API_UNLOCK; - return rv; -} -sw_error_t -fal_ip_pub_addr_get(a_uint32_t dev_id, - a_uint32_t index, fal_ip_pub_addr_t *entry) -{ - sw_error_t rv = SW_OK; - - FAL_API_LOCK; - rv = _fal_ip_pub_addr_get(dev_id, index, entry); - FAL_API_UNLOCK; - return rv; -} -sw_error_t -fal_ip_port_intf_set(a_uint32_t dev_id, fal_port_t port_id, fal_intf_id_t *id) -{ - sw_error_t rv = SW_OK; - - FAL_API_LOCK; - rv = _fal_ip_port_intf_set(dev_id, port_id, id); - FAL_API_UNLOCK; - return rv; -} -sw_error_t -fal_ip_vsi_sg_cfg_set(a_uint32_t dev_id, a_uint32_t vsi, - fal_sg_cfg_t *sg_cfg) -{ - sw_error_t rv = SW_OK; - - FAL_API_LOCK; - rv = _fal_ip_vsi_sg_cfg_set(dev_id, vsi, sg_cfg); - FAL_API_UNLOCK; - return rv; -} -sw_error_t -fal_ip_port_macaddr_set(a_uint32_t dev_id, fal_port_t port_id, - fal_macaddr_entry_t *macaddr) -{ - sw_error_t rv = SW_OK; - - FAL_API_LOCK; - rv = _fal_ip_port_macaddr_set(dev_id, port_id, macaddr); - FAL_API_UNLOCK; - return rv; -} -sw_error_t -fal_ip_vsi_intf_get(a_uint32_t dev_id, a_uint32_t vsi, fal_intf_id_t *id) -{ - sw_error_t rv = SW_OK; - - FAL_API_LOCK; - rv = _fal_ip_vsi_intf_get(dev_id, vsi, id); - FAL_API_UNLOCK; - return rv; -} - -sw_error_t -fal_ip_network_route_add(a_uint32_t dev_id, - a_uint32_t index, - fal_network_route_entry_t *entry) -{ - sw_error_t rv = SW_OK; - - FAL_API_LOCK; - rv = _fal_ip_network_route_add(dev_id, index, entry); - FAL_API_UNLOCK; - return rv; -} -sw_error_t -fal_ip_port_sg_cfg_get(a_uint32_t dev_id, fal_port_t port_id, - fal_sg_cfg_t *sg_cfg) -{ - sw_error_t rv = SW_OK; - - FAL_API_LOCK; - rv = _fal_ip_port_sg_cfg_get(dev_id, port_id, sg_cfg); - FAL_API_UNLOCK; - return rv; -} -sw_error_t -fal_ip_intf_get( - a_uint32_t dev_id, - a_uint32_t index, - fal_intf_entry_t *entry) -{ - sw_error_t rv = SW_OK; - - FAL_API_LOCK; - rv = _fal_ip_intf_get(dev_id, index, entry); - FAL_API_UNLOCK; - return rv; -} -sw_error_t -fal_ip_pub_addr_set(a_uint32_t dev_id, - a_uint32_t index, fal_ip_pub_addr_t *entry) -{ - sw_error_t rv = SW_OK; - - FAL_API_LOCK; - rv = _fal_ip_pub_addr_set(dev_id, index, entry); - FAL_API_UNLOCK; - return rv; -} -sw_error_t -fal_ip_route_mismatch_action_get(a_uint32_t dev_id, fal_fwd_cmd_t *action) -{ - sw_error_t rv = SW_OK; - - FAL_API_LOCK; - rv = _fal_ip_route_mismatch_get(dev_id, action); - FAL_API_UNLOCK; - return rv; -} -sw_error_t -fal_ip_vsi_arp_sg_cfg_get(a_uint32_t dev_id, a_uint32_t vsi, - fal_arp_sg_cfg_t *arp_sg_cfg) -{ - sw_error_t rv = SW_OK; - - FAL_API_LOCK; - rv = _fal_ip_vsi_arp_sg_cfg_get(dev_id, vsi, arp_sg_cfg); - FAL_API_UNLOCK; - return rv; -} -sw_error_t -fal_ip_port_arp_sg_cfg_set(a_uint32_t dev_id, fal_port_t port_id, - fal_arp_sg_cfg_t *arp_sg_cfg) -{ - sw_error_t rv = SW_OK; - - FAL_API_LOCK; - rv = _fal_ip_port_arp_sg_cfg_set(dev_id, port_id, arp_sg_cfg); - FAL_API_UNLOCK; - return rv; -} -sw_error_t -fal_ip_vsi_mc_mode_set(a_uint32_t dev_id, a_uint32_t vsi, - fal_mc_mode_cfg_t *cfg) -{ - sw_error_t rv = SW_OK; - - FAL_API_LOCK; - rv = _fal_ip_vsi_mc_mode_set(dev_id, vsi, cfg); - FAL_API_UNLOCK; - return rv; -} -sw_error_t -fal_ip_vsi_intf_set(a_uint32_t dev_id, a_uint32_t vsi, fal_intf_id_t *id) -{ - sw_error_t rv = SW_OK; - - FAL_API_LOCK; - rv = _fal_ip_vsi_intf_set(dev_id, vsi, id); - FAL_API_UNLOCK; - return rv; -} -sw_error_t -fal_ip_nexthop_get(a_uint32_t dev_id, - a_uint32_t index, fal_ip_nexthop_t *entry) -{ - sw_error_t rv = SW_OK; - - FAL_API_LOCK; - rv = _fal_ip_nexthop_get(dev_id, index, entry); - FAL_API_UNLOCK; - return rv; -} -sw_error_t -fal_ip_route_mismatch_action_set(a_uint32_t dev_id, fal_fwd_cmd_t action) -{ - sw_error_t rv = SW_OK; - - FAL_API_LOCK; - rv = _fal_ip_route_mismatch_set(dev_id, action); - FAL_API_UNLOCK; - return rv; -} -sw_error_t -fal_ip_intf_set( - a_uint32_t dev_id, - a_uint32_t index, - fal_intf_entry_t *entry) -{ - sw_error_t rv = SW_OK; - - FAL_API_LOCK; - rv = _fal_ip_intf_set(dev_id, index, entry); - FAL_API_UNLOCK; - return rv; -} -sw_error_t -fal_ip_vsi_mc_mode_get(a_uint32_t dev_id, a_uint32_t vsi, - fal_mc_mode_cfg_t *cfg) -{ - sw_error_t rv = SW_OK; - - FAL_API_LOCK; - rv = _fal_ip_vsi_mc_mode_get(dev_id, vsi, cfg); - FAL_API_UNLOCK; - return rv; -} -sw_error_t -fal_ip_port_macaddr_get(a_uint32_t dev_id, fal_port_t port_id, - fal_macaddr_entry_t *macaddr) -{ - sw_error_t rv = SW_OK; - - FAL_API_LOCK; - rv = _fal_ip_port_macaddr_get(dev_id, port_id, macaddr); - FAL_API_UNLOCK; - return rv; -} -sw_error_t -fal_ip_port_arp_sg_cfg_get(a_uint32_t dev_id, fal_port_t port_id, - fal_arp_sg_cfg_t *arp_sg_cfg) -{ - sw_error_t rv = SW_OK; - - FAL_API_LOCK; - rv = _fal_ip_port_arp_sg_cfg_get(dev_id, port_id, arp_sg_cfg); - FAL_API_UNLOCK; - return rv; -} -sw_error_t -fal_ip_nexthop_set(a_uint32_t dev_id, - a_uint32_t index, fal_ip_nexthop_t *entry) -{ - sw_error_t rv = SW_OK; - - FAL_API_LOCK; - rv = _fal_ip_nexthop_set(dev_id, index, entry); - FAL_API_UNLOCK; - return rv; -} - -sw_error_t -fal_ip_global_ctrl_set(a_uint32_t dev_id, fal_ip_global_cfg_t *cfg) -{ - sw_error_t rv = SW_OK; - - FAL_API_LOCK; - rv = _fal_ip_global_ctrl_set(dev_id, cfg); - FAL_API_UNLOCK; - return rv; -} - -sw_error_t -fal_ip_global_ctrl_get(a_uint32_t dev_id, fal_ip_global_cfg_t *cfg) -{ - sw_error_t rv = SW_OK; - - FAL_API_LOCK; - rv = _fal_ip_global_ctrl_get(dev_id, cfg); - FAL_API_UNLOCK; - return rv; -} -#endif -/*insert flag for outter fal, don't remove it*/ - -/** - * @} - */ diff --git a/feeds/ipq807x/qca-ssdk/src/src/fal/fal_leaky.c b/feeds/ipq807x/qca-ssdk/src/src/fal/fal_leaky.c deleted file mode 100755 index db4321281..000000000 --- a/feeds/ipq807x/qca-ssdk/src/src/fal/fal_leaky.c +++ /dev/null @@ -1,353 +0,0 @@ -/* - * Copyright (c) 2012, The Linux Foundation. All rights reserved. - * Permission to use, copy, modify, and/or distribute this software for - * any purpose with or without fee is hereby granted, provided that the - * above copyright notice and this permission notice appear in all copies. - * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES - * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR - * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES - * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN - * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT - * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. - */ - - -/** - * @defgroup fal_leaky FAL_LEAKY - * @{ - */ -#include "sw.h" -#include "fal_leaky.h" -#include "hsl_api.h" - -static sw_error_t -_fal_uc_leaky_mode_set(a_uint32_t dev_id, fal_leaky_ctrl_mode_t ctrl_mode) -{ - sw_error_t rv; - hsl_api_t *p_api; - - SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id)); - - if (NULL == p_api->uc_leaky_mode_set) - return SW_NOT_SUPPORTED; - - rv = p_api->uc_leaky_mode_set(dev_id, ctrl_mode); - return rv; -} - -static sw_error_t -_fal_uc_leaky_mode_get(a_uint32_t dev_id, fal_leaky_ctrl_mode_t * ctrl_mode) -{ - sw_error_t rv; - hsl_api_t *p_api; - - SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id)); - - if (NULL == p_api->uc_leaky_mode_get) - return SW_NOT_SUPPORTED; - - rv = p_api->uc_leaky_mode_get(dev_id, ctrl_mode); - return rv; -} - - -static sw_error_t -_fal_mc_leaky_mode_set(a_uint32_t dev_id, fal_leaky_ctrl_mode_t ctrl_mode) -{ - sw_error_t rv; - hsl_api_t *p_api; - - SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id)); - - if (NULL == p_api->mc_leaky_mode_set) - return SW_NOT_SUPPORTED; - - rv = p_api->mc_leaky_mode_set(dev_id, ctrl_mode); - return rv; -} - - -static sw_error_t -_fal_mc_leaky_mode_get(a_uint32_t dev_id, fal_leaky_ctrl_mode_t * ctrl_mode) -{ - sw_error_t rv; - hsl_api_t *p_api; - - SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id)); - - if (NULL == p_api->mc_leaky_mode_get) - return SW_NOT_SUPPORTED; - - rv = p_api->mc_leaky_mode_get(dev_id, ctrl_mode); - return rv; -} - - -static sw_error_t -_fal_port_arp_leaky_set(a_uint32_t dev_id, fal_port_t port_id, a_bool_t enable) -{ - sw_error_t rv; - hsl_api_t *p_api; - - SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id)); - - if (NULL == p_api->port_arp_leaky_set) - return SW_NOT_SUPPORTED; - - rv = p_api->port_arp_leaky_set(dev_id, port_id, enable); - return rv; -} - - -static sw_error_t -_fal_port_arp_leaky_get(a_uint32_t dev_id, fal_port_t port_id, a_bool_t * enable) -{ - sw_error_t rv; - hsl_api_t *p_api; - - SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id)); - - if (NULL == p_api->port_arp_leaky_get) - return SW_NOT_SUPPORTED; - - rv = p_api->port_arp_leaky_get(dev_id, port_id, enable); - return rv; -} - -static sw_error_t -_fal_port_uc_leaky_set(a_uint32_t dev_id, fal_port_t port_id, a_bool_t enable) -{ - sw_error_t rv; - hsl_api_t *p_api; - - SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id)); - - if (NULL == p_api->port_uc_leaky_set) - return SW_NOT_SUPPORTED; - - rv = p_api->port_uc_leaky_set(dev_id, port_id, enable); - return rv; -} - - -static sw_error_t -_fal_port_uc_leaky_get(a_uint32_t dev_id, fal_port_t port_id, a_bool_t * enable) -{ - sw_error_t rv; - hsl_api_t *p_api; - - SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id)); - - if (NULL == p_api->port_uc_leaky_get) - return SW_NOT_SUPPORTED; - - rv = p_api->port_uc_leaky_get(dev_id, port_id, enable); - return rv; -} - - - -static sw_error_t -_fal_port_mc_leaky_set(a_uint32_t dev_id, fal_port_t port_id, a_bool_t enable) -{ - sw_error_t rv; - hsl_api_t *p_api; - - SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id)); - - if (NULL == p_api->port_mc_leaky_set) - return SW_NOT_SUPPORTED; - - rv = p_api->port_mc_leaky_set(dev_id, port_id, enable); - return rv; -} - - -static sw_error_t -_fal_port_mc_leaky_get(a_uint32_t dev_id, fal_port_t port_id, a_bool_t * enable) -{ - sw_error_t rv; - hsl_api_t *p_api; - - SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id)); - - if (NULL == p_api->port_mc_leaky_get) - return SW_NOT_SUPPORTED; - - rv = p_api->port_mc_leaky_get(dev_id, port_id, enable); - return rv; -} -/** -* @brief Set unicast packets leaky control mode on a particular device. -* @param[in] dev_id device id -* @param[in] ctrl_mode leaky control mode -* @return SW_OK or error code -*/ -sw_error_t -fal_uc_leaky_mode_set(a_uint32_t dev_id, fal_leaky_ctrl_mode_t ctrl_mode) -{ - sw_error_t rv; - - FAL_API_LOCK; - rv = _fal_uc_leaky_mode_set(dev_id, ctrl_mode); - FAL_API_UNLOCK; - return rv; -} - -/** - * @brief Get unicast packets leaky control mode on a particular device. - * @param[in] dev_id device id - * @param[out] ctrl_mode leaky control mode - * @return SW_OK or error code - */ -sw_error_t -fal_uc_leaky_mode_get(a_uint32_t dev_id, fal_leaky_ctrl_mode_t * ctrl_mode) -{ - sw_error_t rv; - - FAL_API_LOCK; - rv = _fal_uc_leaky_mode_get(dev_id, ctrl_mode); - FAL_API_UNLOCK; - return rv; -} - -/** -* @brief Set multicast packets leaky control mode on a particular device. -* @param[in] dev_id device id -* @param[in] ctrl_mode leaky control mode -* @return SW_OK or error code -*/ -sw_error_t -fal_mc_leaky_mode_set(a_uint32_t dev_id, fal_leaky_ctrl_mode_t ctrl_mode) -{ - sw_error_t rv; - - FAL_API_LOCK; - rv = _fal_mc_leaky_mode_set(dev_id, ctrl_mode); - FAL_API_UNLOCK; - return rv; -} - -/** - * @brief Get multicast packets leaky control mode on a particular device. - * @param[in] dev_id device id - * @param[out] ctrl_mode leaky control mode - * @return SW_OK or error code - */ -sw_error_t -fal_mc_leaky_mode_get(a_uint32_t dev_id, fal_leaky_ctrl_mode_t * ctrl_mode) -{ - sw_error_t rv; - - FAL_API_LOCK; - rv = _fal_mc_leaky_mode_get(dev_id, ctrl_mode); - FAL_API_UNLOCK; - return rv; -} - -/** - * @brief Set arp packets leaky status on a particular port. - * @param[in] dev_id device id - * @param[in] enable A_TRUE or A_FALSE - * @return SW_OK or error code - */ -sw_error_t -fal_port_arp_leaky_set(a_uint32_t dev_id, fal_port_t port_id, a_bool_t enable) -{ - sw_error_t rv; - - FAL_API_LOCK; - rv = _fal_port_arp_leaky_set(dev_id, port_id, enable); - FAL_API_UNLOCK; - return rv; -} - -/** - * @brief Get arp packets leaky status on a particular port. - * @param[in] dev_id device id - * @param[out] enable A_TRUE or A_FALSE - * @return SW_OK or error code - */ -sw_error_t -fal_port_arp_leaky_get(a_uint32_t dev_id, fal_port_t port_id, a_bool_t * enable) -{ - sw_error_t rv; - - FAL_API_LOCK; - rv = _fal_port_arp_leaky_get(dev_id, port_id, enable); - FAL_API_UNLOCK; - return rv; -} - -/** - * @brief Set unicast packets leaky status on a particular port. - * @param[in] dev_id device id - * @param[in] enable A_TRUE or A_FALSE - * @return SW_OK or error code - */ -sw_error_t -fal_port_uc_leaky_set(a_uint32_t dev_id, fal_port_t port_id, a_bool_t enable) -{ - sw_error_t rv; - - FAL_API_LOCK; - rv = _fal_port_uc_leaky_set(dev_id, port_id, enable); - FAL_API_UNLOCK; - return rv; -} - -/** - * @brief Get unicast packets leaky status on a particular port. - * @param[in] dev_id device id - * @param[out] enable A_TRUE or A_FALSE - * @return SW_OK or error code - */ -sw_error_t -fal_port_uc_leaky_get(a_uint32_t dev_id, fal_port_t port_id, a_bool_t * enable) -{ - sw_error_t rv; - - FAL_API_LOCK; - rv = _fal_port_uc_leaky_get(dev_id, port_id, enable); - FAL_API_UNLOCK; - return rv; -} - -/** - * @brief Set multicast packets leaky status on a particular port. - * @param[in] dev_id device id - * @param[in] enable A_TRUE or A_FALSE - * @return SW_OK or error code - */ -sw_error_t -fal_port_mc_leaky_set(a_uint32_t dev_id, fal_port_t port_id, a_bool_t enable) -{ - sw_error_t rv; - - FAL_API_LOCK; - rv = _fal_port_mc_leaky_set(dev_id, port_id, enable); - FAL_API_UNLOCK; - return rv; -} - -/** - * @brief Get multicast packets leaky status on a particular port. - * @param[in] dev_id device id - * @param[out] enable A_TRUE or A_FALSE - * @return SW_OK or error code - */ -sw_error_t -fal_port_mc_leaky_get(a_uint32_t dev_id, fal_port_t port_id, a_bool_t * enable) -{ - sw_error_t rv; - - FAL_API_LOCK; - rv = _fal_port_mc_leaky_get(dev_id, port_id, enable); - FAL_API_UNLOCK; - return rv; -} - -/** - * @} - */ diff --git a/feeds/ipq807x/qca-ssdk/src/src/fal/fal_led.c b/feeds/ipq807x/qca-ssdk/src/src/fal/fal_led.c deleted file mode 100644 index c11587572..000000000 --- a/feeds/ipq807x/qca-ssdk/src/src/fal/fal_led.c +++ /dev/null @@ -1,158 +0,0 @@ -/* - * Copyright (c) 2012, 2020, The Linux Foundation. All rights reserved. - * Permission to use, copy, modify, and/or distribute this software for - * any purpose with or without fee is hereby granted, provided that the - * above copyright notice and this permission notice appear in all copies. - * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES - * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR - * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES - * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN - * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT - * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. - */ - - -/** - * @defgroup fal_led FAL_LED - * @{ - */ - -#include "sw.h" -#include "fal_led.h" -#include "hsl_api.h" -#include "adpt.h" - -static sw_error_t -_fal_led_ctrl_pattern_set(a_uint32_t dev_id, led_pattern_group_t group, - led_pattern_id_t id, led_ctrl_pattern_t * pattern) -{ - sw_error_t rv; - hsl_api_t *p_api; - adpt_api_t *p_adpt_api; - - if((p_adpt_api = adpt_api_ptr_get(dev_id)) != NULL && - p_adpt_api->adpt_led_ctrl_pattern_set != NULL) { - rv = p_adpt_api->adpt_led_ctrl_pattern_set(dev_id, group, id, pattern); - return rv; - } - SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id)); - - if (NULL == p_api->led_ctrl_pattern_set) - return SW_NOT_SUPPORTED; - - rv = p_api->led_ctrl_pattern_set(dev_id, group, id, pattern); - return rv; -} - - - -static sw_error_t -_fal_led_ctrl_pattern_get(a_uint32_t dev_id, led_pattern_group_t group, - led_pattern_id_t id, led_ctrl_pattern_t * pattern) -{ - sw_error_t rv; - hsl_api_t *p_api; - adpt_api_t *p_adpt_api; - - if((p_adpt_api = adpt_api_ptr_get(dev_id)) != NULL && - p_adpt_api->adpt_led_ctrl_pattern_get != NULL) { - rv = p_adpt_api->adpt_led_ctrl_pattern_get(dev_id, group, id, pattern); - return rv; - } - SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id)); - - if (NULL == p_api->led_ctrl_pattern_get) - return SW_NOT_SUPPORTED; - - rv = p_api->led_ctrl_pattern_get(dev_id, group, id, pattern); - return rv; -} - -static sw_error_t -_fal_led_source_pattern_set(a_uint32_t dev_id, a_uint32_t source_id, - led_ctrl_pattern_t * pattern) -{ - sw_error_t rv; - hsl_api_t *p_api; - adpt_api_t *p_adpt_api; - - if((p_adpt_api = adpt_api_ptr_get(dev_id)) != NULL && - p_adpt_api->adpt_led_ctrl_source_set != NULL) { - rv = p_adpt_api->adpt_led_ctrl_source_set(dev_id, source_id, pattern); - return rv; - } - SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id)); - - if (NULL == p_api->led_ctrl_source_set) - return SW_NOT_SUPPORTED; - - rv = p_api->led_ctrl_source_set(dev_id, source_id, pattern); - return rv; -} - - -/** -* @brief Set led control pattern on a particular device. -* @param[in] dev_id device id -* @param[in] group pattern group, lan or wan -* @param[in] id pattern id -* @param[in] pattern led control pattern -* @return SW_OK or error code -*/ -sw_error_t -fal_led_ctrl_pattern_set(a_uint32_t dev_id, led_pattern_group_t group, - led_pattern_id_t id, led_ctrl_pattern_t * pattern) -{ - sw_error_t rv; - - FAL_API_LOCK; - rv = _fal_led_ctrl_pattern_set(dev_id, group, id, pattern); - FAL_API_UNLOCK; - return rv; -} - -/** -* @brief Get led control pattern on a particular device. -* @param[in] dev_id device id -* @param[in] group pattern group, lan or wan -* @param[in] id pattern id -* @param[out] pattern led control pattern -* @return SW_OK or error code -*/ -sw_error_t -fal_led_ctrl_pattern_get(a_uint32_t dev_id, led_pattern_group_t group, - led_pattern_id_t id, led_ctrl_pattern_t * pattern) -{ - sw_error_t rv; - - FAL_API_LOCK; - rv = _fal_led_ctrl_pattern_get(dev_id, group, id, pattern); - FAL_API_UNLOCK; - return rv; -} - -/** -* @brief Set led control source on a particular device. -* @param[in] dev_id device id -* @param[in] source id -* @param[in] id pattern id -* @param[in] pattern led control pattern -* @return SW_OK or error code -*/ -sw_error_t -fal_led_source_pattern_set(a_uint32_t dev_id, a_uint32_t source_id, - led_ctrl_pattern_t * pattern) -{ - sw_error_t rv; - - FAL_API_LOCK; - rv = _fal_led_source_pattern_set(dev_id, source_id, pattern); - FAL_API_UNLOCK; - return rv; -} - - -/** - * @} - */ diff --git a/feeds/ipq807x/qca-ssdk/src/src/fal/fal_mib.c b/feeds/ipq807x/qca-ssdk/src/src/fal/fal_mib.c deleted file mode 100755 index 0e8b39e4f..000000000 --- a/feeds/ipq807x/qca-ssdk/src/src/fal/fal_mib.c +++ /dev/null @@ -1,688 +0,0 @@ -/* - * Copyright (c) 2012, 2017, The Linux Foundation. All rights reserved. - * Permission to use, copy, modify, and/or distribute this software for - * any purpose with or without fee is hereby granted, provided that the - * above copyright notice and this permission notice appear in all copies. - * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES - * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR - * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES - * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN - * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT - * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. - */ - - -/** - * @defgroup fal_mib FAL_MIB - * @{ - */ - -#include "sw.h" -#include "fal_mib.h" -#include "hsl_api.h" -#include "adpt.h" - -#include -#include - - -static sw_error_t -_fal_get_mib_info(a_uint32_t dev_id, fal_port_t port_id, - fal_mib_info_t * mib_Info) -{ - sw_error_t rv; - hsl_api_t *p_api; - adpt_api_t *p_adpt_api; - - if((p_adpt_api = adpt_api_ptr_get(dev_id)) != NULL) { - if (NULL == p_adpt_api->adpt_get_mib_info) - return SW_NOT_SUPPORTED; - - rv = p_adpt_api->adpt_get_mib_info(dev_id, port_id, mib_Info); - return rv; - } - - SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id)); - - if (NULL == p_api->get_mib_info) - return SW_NOT_SUPPORTED; - - rv = p_api->get_mib_info(dev_id, port_id, mib_Info); - return rv; -} - -static sw_error_t -_fal_get_rx_mib_info(a_uint32_t dev_id, fal_port_t port_id, - fal_mib_info_t * mib_Info) -{ - sw_error_t rv; - hsl_api_t *p_api; - adpt_api_t *p_adpt_api; - - if((p_adpt_api = adpt_api_ptr_get(dev_id)) != NULL) { - if (NULL == p_adpt_api->adpt_get_rx_mib_info) - return SW_NOT_SUPPORTED; - - rv = p_adpt_api->adpt_get_rx_mib_info(dev_id, port_id, mib_Info); - return rv; - } - - SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id)); - - if (NULL == p_api->get_rx_mib_info) - return SW_NOT_SUPPORTED; - - rv = p_api->get_rx_mib_info(dev_id, port_id, mib_Info); - return rv; -} - -static sw_error_t -_fal_get_tx_mib_info(a_uint32_t dev_id, fal_port_t port_id, - fal_mib_info_t * mib_Info) -{ - sw_error_t rv; - hsl_api_t *p_api; - adpt_api_t *p_adpt_api; - - if((p_adpt_api = adpt_api_ptr_get(dev_id)) != NULL) { - if (NULL == p_adpt_api->adpt_get_tx_mib_info) - return SW_NOT_SUPPORTED; - - rv = p_adpt_api->adpt_get_tx_mib_info(dev_id, port_id, mib_Info); - return rv; - } - - SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id)); - - if (NULL == p_api->get_tx_mib_info) - return SW_NOT_SUPPORTED; - - rv = p_api->get_tx_mib_info(dev_id, port_id, mib_Info); - return rv; -} - -static sw_error_t -_fal_mib_status_set(a_uint32_t dev_id, a_bool_t enable) -{ - sw_error_t rv; - hsl_api_t *p_api; - adpt_api_t *p_adpt_api; - - if((p_adpt_api = adpt_api_ptr_get(dev_id)) != NULL) { - if (NULL == p_adpt_api->adpt_mib_status_set) - return SW_NOT_SUPPORTED; - - rv = p_adpt_api->adpt_mib_status_set(dev_id, enable); - return rv; - } - - SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id)); - - if (NULL == p_api->mib_status_set) - return SW_NOT_SUPPORTED; - - rv = p_api->mib_status_set(dev_id, enable); - return rv; -} - - -static sw_error_t -_fal_mib_status_get(a_uint32_t dev_id, a_bool_t * enable) -{ - sw_error_t rv; - hsl_api_t *p_api; - adpt_api_t *p_adpt_api; - - if((p_adpt_api = adpt_api_ptr_get(dev_id)) != NULL) { - if (NULL == p_adpt_api->adpt_mib_status_get) - return SW_NOT_SUPPORTED; - - rv = p_adpt_api->adpt_mib_status_get(dev_id, enable); - return rv; - } - - SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id)); - - if (NULL == p_api->mib_status_get) - return SW_NOT_SUPPORTED; - - rv = p_api->mib_status_get(dev_id, enable); - return rv; -} - -static sw_error_t -_fal_mib_port_flush_counters(a_uint32_t dev_id, fal_port_t port_id) -{ - sw_error_t rv; - hsl_api_t *p_api; - adpt_api_t *p_adpt_api; - - if((p_adpt_api = adpt_api_ptr_get(dev_id)) != NULL) { - if (NULL == p_adpt_api->adpt_mib_port_flush_counters) - return SW_NOT_SUPPORTED; - - rv = p_adpt_api->adpt_mib_port_flush_counters(dev_id, port_id); - return rv; - } - - SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id)); - - if (NULL == p_api->mib_port_flush_counters) - return SW_NOT_SUPPORTED; - - rv = p_api->mib_port_flush_counters(dev_id, port_id); - return rv; -} - -static sw_error_t -_fal_mib_cpukeep_set(a_uint32_t dev_id, a_bool_t enable) -{ - sw_error_t rv; - hsl_api_t *p_api; - adpt_api_t *p_adpt_api; - - if((p_adpt_api = adpt_api_ptr_get(dev_id)) != NULL) { - if (NULL == p_adpt_api->adpt_mib_cpukeep_set) - return SW_NOT_SUPPORTED; - - rv = p_adpt_api->adpt_mib_cpukeep_set(dev_id, enable); - return rv; - } - - SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id)); - - if (NULL == p_api->mib_cpukeep_set) - return SW_NOT_SUPPORTED; - - rv = p_api->mib_cpukeep_set(dev_id, enable); - return rv; -} - - -static sw_error_t -_fal_mib_cpukeep_get(a_uint32_t dev_id, a_bool_t * enable) -{ - sw_error_t rv; - hsl_api_t *p_api; - adpt_api_t *p_adpt_api; - - if((p_adpt_api = adpt_api_ptr_get(dev_id)) != NULL) { - if (NULL == p_adpt_api->adpt_mib_cpukeep_get) - return SW_NOT_SUPPORTED; - - rv = p_adpt_api->adpt_mib_cpukeep_get(dev_id, enable); - return rv; - } - - SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id)); - - if (NULL == p_api->mib_cpukeep_get) - return SW_NOT_SUPPORTED; - - rv = p_api->mib_cpukeep_get(dev_id, enable); - return rv; -} -static sw_error_t -_fal_get_xgmib_info(a_uint32_t dev_id, fal_port_t port_id, - fal_xgmib_info_t * mib_Info) -{ - sw_error_t rv = SW_OK; - adpt_api_t *p_api; - - SW_RTN_ON_NULL(p_api = adpt_api_ptr_get(dev_id)); - - if (NULL == p_api->adpt_get_xgmib_info) - return SW_NOT_SUPPORTED; - - rv = p_api->adpt_get_xgmib_info(dev_id, port_id, mib_Info); - return rv; -} - -static sw_error_t -_fal_get_rx_xgmib_info(a_uint32_t dev_id, fal_port_t port_id, - fal_xgmib_info_t * mib_Info) -{ - sw_error_t rv = SW_OK; - adpt_api_t *p_api; - - SW_RTN_ON_NULL(p_api = adpt_api_ptr_get(dev_id)); - - if (NULL == p_api->adpt_get_rx_xgmib_info) - return SW_NOT_SUPPORTED; - - rv = p_api->adpt_get_rx_xgmib_info(dev_id, port_id, mib_Info); - return rv; -} - -static sw_error_t -_fal_get_tx_xgmib_info(a_uint32_t dev_id, fal_port_t port_id, - fal_xgmib_info_t * mib_Info) -{ - sw_error_t rv = SW_OK; - adpt_api_t *p_api; - - SW_RTN_ON_NULL(p_api = adpt_api_ptr_get(dev_id)); - - if (NULL == p_api->adpt_get_tx_xgmib_info) - return SW_NOT_SUPPORTED; - - rv = p_api->adpt_get_tx_xgmib_info(dev_id, port_id, mib_Info); - return rv; -} - -static fal_mib_counter_t *g_mibcounter[SW_MAX_NR_DEV]; - -sw_error_t -fal_mib_counter_alloc(a_uint32_t dev_id, a_uint64_t **p_mibcounter) -{ - *p_mibcounter = kzalloc(SW_MAX_NR_PORT * sizeof(fal_mib_counter_t), - GFP_KERNEL); - - if(NULL == *p_mibcounter) - return SW_OUT_OF_MEM; - - g_mibcounter[dev_id] = (fal_mib_counter_t*)*p_mibcounter; - - return SW_OK; -} - -static void _fal_rx_mib_update(a_uint32_t dev_id, fal_port_t port_id, - fal_mib_info_t * mib_Info) -{ - if(NULL == g_mibcounter[dev_id]) - return; - - g_mibcounter[dev_id][port_id].RxBroad += mib_Info->RxBroad; - g_mibcounter[dev_id][port_id].RxPause += mib_Info->RxPause; - g_mibcounter[dev_id][port_id].RxMulti += mib_Info->RxMulti; - g_mibcounter[dev_id][port_id].RxFcsErr += mib_Info->RxFcsErr; - g_mibcounter[dev_id][port_id].RxAllignErr += mib_Info->RxAllignErr; - g_mibcounter[dev_id][port_id].RxRunt += mib_Info->RxRunt; - g_mibcounter[dev_id][port_id].RxFragment += mib_Info->RxFragment; - g_mibcounter[dev_id][port_id].Rx64Byte += mib_Info->Rx64Byte; - g_mibcounter[dev_id][port_id].Rx128Byte += mib_Info->Rx128Byte; - g_mibcounter[dev_id][port_id].Rx256Byte += mib_Info->Rx256Byte; - g_mibcounter[dev_id][port_id].Rx512Byte += mib_Info->Rx512Byte; - g_mibcounter[dev_id][port_id].Rx1024Byte += mib_Info->Rx1024Byte; - g_mibcounter[dev_id][port_id].Rx1518Byte += mib_Info->Rx1518Byte; - g_mibcounter[dev_id][port_id].RxMaxByte += mib_Info->RxMaxByte; - g_mibcounter[dev_id][port_id].RxTooLong += mib_Info->RxTooLong; - g_mibcounter[dev_id][port_id].RxGoodByte += - (((u64)mib_Info->RxGoodByte_hi) << 32) | mib_Info->RxGoodByte_lo; - g_mibcounter[dev_id][port_id].RxBadByte += - (((u64)mib_Info->RxBadByte_hi) << 32) | mib_Info->RxBadByte_lo; - g_mibcounter[dev_id][port_id].RxOverFlow += mib_Info->RxOverFlow; - g_mibcounter[dev_id][port_id].Filtered += mib_Info->Filtered; - g_mibcounter[dev_id][port_id].RxUniCast += mib_Info->RxUniCast; - g_mibcounter[dev_id][port_id].RxTooLongByte += - (((u64)mib_Info->RxTooLongByte_hi) << 32) | mib_Info->RxTooLongByte_lo; - g_mibcounter[dev_id][port_id].RxRuntByte += - (((u64)mib_Info->RxRuntByte_hi) << 32) | mib_Info->RxRuntByte_lo; - g_mibcounter[dev_id][port_id].Rx14To63 += mib_Info->Rx14To63; - - return; -} - -static void _fal_tx_mib_update(a_uint32_t dev_id, fal_port_t port_id, - fal_mib_info_t * mib_Info) -{ - if(NULL == g_mibcounter[dev_id]) - return; - - g_mibcounter[dev_id][port_id].TxBroad += mib_Info->TxBroad; - g_mibcounter[dev_id][port_id].TxPause += mib_Info->TxPause; - g_mibcounter[dev_id][port_id].TxMulti += mib_Info->TxMulti; - g_mibcounter[dev_id][port_id].TxUnderRun += mib_Info->TxUnderRun; - g_mibcounter[dev_id][port_id].Tx64Byte += mib_Info->Tx64Byte; - g_mibcounter[dev_id][port_id].Tx128Byte += mib_Info->Tx128Byte; - g_mibcounter[dev_id][port_id].Tx256Byte += mib_Info->Tx256Byte; - g_mibcounter[dev_id][port_id].Tx512Byte += mib_Info->Tx512Byte; - g_mibcounter[dev_id][port_id].Tx1024Byte += mib_Info->Tx1024Byte; - g_mibcounter[dev_id][port_id].Tx1518Byte += mib_Info->Tx1518Byte; - g_mibcounter[dev_id][port_id].TxMaxByte += mib_Info->TxMaxByte; - g_mibcounter[dev_id][port_id].TxOverSize += mib_Info->TxOverSize; - g_mibcounter[dev_id][port_id].TxByte += - (((u64)mib_Info->TxByte_hi) << 32) | mib_Info->TxByte_lo; - g_mibcounter[dev_id][port_id].TxCollision += mib_Info->TxCollision; - g_mibcounter[dev_id][port_id].TxAbortCol += mib_Info->TxAbortCol; - g_mibcounter[dev_id][port_id].TxMultiCol += mib_Info->TxMultiCol; - g_mibcounter[dev_id][port_id].TxSingalCol += mib_Info->TxSingalCol; - g_mibcounter[dev_id][port_id].TxExcDefer += mib_Info->TxExcDefer; - g_mibcounter[dev_id][port_id].TxDefer += mib_Info->TxDefer; - g_mibcounter[dev_id][port_id].TxLateCol += mib_Info->TxLateCol; - g_mibcounter[dev_id][port_id].TxUniCast += mib_Info->TxUniCast; - - return; -} - -/*insert flag for inner fal, don't remove it*/ -/** - * @brief Get mib infomation on particular port. - * @param[in] dev_id device id - * @param[in] port_id port id - * @param[out] mib_info mib infomation - * @return SW_OK or error code - */ -sw_error_t -fal_get_mib_info(a_uint32_t dev_id, fal_port_t port_id, - fal_mib_info_t * mib_Info) -{ - sw_error_t rv; - - FAL_API_LOCK; - rv = _fal_get_mib_info(dev_id, port_id, mib_Info); - _fal_rx_mib_update(dev_id, port_id, mib_Info); - _fal_tx_mib_update(dev_id, port_id, mib_Info); - FAL_API_UNLOCK; - return rv; -} - -sw_error_t -fal_mib_counter_get(a_uint32_t dev_id, fal_port_t port_id, - fal_mib_counter_t *mib_counter) -{ - sw_error_t rv; - fal_mib_info_t mib_info = {0}; - - if(NULL == g_mibcounter[dev_id]) - return SW_BAD_PTR; - - rv = fal_get_mib_info(dev_id, port_id, &mib_info); - - if(rv != SW_OK) - return rv; - - mib_counter->RxBroad = g_mibcounter[dev_id][port_id].RxBroad; - mib_counter->RxPause = g_mibcounter[dev_id][port_id].RxPause; - mib_counter->RxMulti = g_mibcounter[dev_id][port_id].RxMulti; - mib_counter->RxFcsErr = g_mibcounter[dev_id][port_id].RxFcsErr; - mib_counter->RxAllignErr = g_mibcounter[dev_id][port_id].RxAllignErr; - mib_counter->RxRunt = g_mibcounter[dev_id][port_id].RxRunt; - mib_counter->RxFragment = g_mibcounter[dev_id][port_id].RxFragment ; - mib_counter->Rx64Byte = g_mibcounter[dev_id][port_id].Rx64Byte ; - mib_counter->Rx128Byte = g_mibcounter[dev_id][port_id].Rx128Byte; - mib_counter->Rx256Byte = g_mibcounter[dev_id][port_id].Rx256Byte; - mib_counter->Rx512Byte = g_mibcounter[dev_id][port_id].Rx512Byte; - mib_counter->Rx1024Byte = g_mibcounter[dev_id][port_id].Rx1024Byte; - mib_counter->Rx1518Byte = g_mibcounter[dev_id][port_id].Rx1518Byte; - mib_counter->RxMaxByte = g_mibcounter[dev_id][port_id].RxMaxByte; - mib_counter->RxTooLong = g_mibcounter[dev_id][port_id].RxTooLong; - mib_counter->RxGoodByte = g_mibcounter[dev_id][port_id].RxGoodByte; - mib_counter->RxBadByte = g_mibcounter[dev_id][port_id].RxBadByte; - mib_counter->RxOverFlow = g_mibcounter[dev_id][port_id].RxOverFlow; - mib_counter->Filtered = g_mibcounter[dev_id][port_id].Filtered; - mib_counter->TxBroad = g_mibcounter[dev_id][port_id].TxBroad; - mib_counter->TxPause = g_mibcounter[dev_id][port_id].TxPause; - mib_counter->TxMulti = g_mibcounter[dev_id][port_id].TxMulti; - mib_counter->TxUnderRun = g_mibcounter[dev_id][port_id].TxUnderRun; - mib_counter->Tx64Byte = g_mibcounter[dev_id][port_id].Tx64Byte; - mib_counter->Tx128Byte = g_mibcounter[dev_id][port_id].Tx128Byte; - mib_counter->Tx256Byte = g_mibcounter[dev_id][port_id].Tx256Byte; - mib_counter->Tx512Byte = g_mibcounter[dev_id][port_id].Tx512Byte; - mib_counter->Tx1024Byte = g_mibcounter[dev_id][port_id].Tx1024Byte; - mib_counter->Tx1518Byte = g_mibcounter[dev_id][port_id].Tx1518Byte; - mib_counter->TxMaxByte = g_mibcounter[dev_id][port_id].TxMaxByte; - mib_counter->TxOverSize = g_mibcounter[dev_id][port_id].TxOverSize; - mib_counter->TxByte = g_mibcounter[dev_id][port_id].TxByte; - mib_counter->TxCollision = g_mibcounter[dev_id][port_id].TxCollision; - mib_counter->TxAbortCol = g_mibcounter[dev_id][port_id].TxAbortCol; - mib_counter->TxMultiCol = g_mibcounter[dev_id][port_id].TxMultiCol; - mib_counter->TxSingalCol = g_mibcounter[dev_id][port_id].TxSingalCol; - mib_counter->TxExcDefer = g_mibcounter[dev_id][port_id].TxExcDefer; - mib_counter->TxDefer = g_mibcounter[dev_id][port_id].TxDefer; - mib_counter->TxLateCol = g_mibcounter[dev_id][port_id].TxLateCol; - mib_counter->RxUniCast = g_mibcounter[dev_id][port_id].RxUniCast; - mib_counter->TxUniCast = g_mibcounter[dev_id][port_id].TxUniCast; - mib_counter->Rx14To63 = g_mibcounter[dev_id][port_id].Rx14To63; - mib_counter->RxTooLongByte = g_mibcounter[dev_id][port_id].RxTooLongByte; - mib_counter->RxRuntByte = g_mibcounter[dev_id][port_id].RxRuntByte; - - return SW_OK; -} - -/** - * @brief Get RX mib infomation on particular port. - * @param[in] dev_id device id - * @param[in] port_id port id - * @param[out] mib_info mib infomation - * @return SW_OK or error code - */ -sw_error_t -fal_get_rx_mib_info(a_uint32_t dev_id, fal_port_t port_id, - fal_mib_info_t * mib_Info) -{ - sw_error_t rv; - - FAL_API_LOCK; - rv = _fal_get_rx_mib_info(dev_id, port_id, mib_Info); - _fal_rx_mib_update(dev_id, port_id, mib_Info); - FAL_API_UNLOCK; - - return rv; -} - -/** - * @brief Get TX mib infomation on particular port. - * @param[in] dev_id device id - * @param[in] port_id port id - * @param[out] mib_info mib infomation - * @return SW_OK or error code - */ -sw_error_t -fal_get_tx_mib_info(a_uint32_t dev_id, fal_port_t port_id, - fal_mib_info_t * mib_Info) -{ - sw_error_t rv; - - FAL_API_LOCK; - rv = _fal_get_tx_mib_info(dev_id, port_id, mib_Info); - _fal_tx_mib_update(dev_id, port_id, mib_Info); - FAL_API_UNLOCK; - - return rv; -} - -/** - * @brief Set mib status on a particular device. - * @param[in] dev_id device id - * @param[in] enable A_TRUE or A_FALSE - * @return SW_OK or error code - */ -sw_error_t -fal_mib_status_set(a_uint32_t dev_id, a_bool_t enable) -{ - sw_error_t rv; - - FAL_API_LOCK; - rv = _fal_mib_status_set(dev_id, enable); - FAL_API_UNLOCK; - return rv; -} - -/** - * @brief Get mib status on a particular device. - * @param[in] dev_id device id - * @param[in] enable A_TRUE or A_FALSE - * @return SW_OK or error code - */ -sw_error_t -fal_mib_status_get(a_uint32_t dev_id, a_bool_t * enable) -{ - sw_error_t rv; - - FAL_API_LOCK; - rv = _fal_mib_status_get(dev_id, enable); - FAL_API_UNLOCK; - return rv; -} - -/** - * @brief Flush mib counters on particular port. - * @param[in] dev_id device id - * @param[in] port_id port id - * @return SW_OK or error code - */ -sw_error_t -fal_mib_port_flush_counters(a_uint32_t dev_id, fal_port_t port_id ) -{ - sw_error_t rv; - - FAL_API_LOCK; - rv = _fal_mib_port_flush_counters(dev_id, port_id); - FAL_API_UNLOCK; - return rv; -} - -/** - * @brief Set mib status on a particular device. - * @param[in] dev_id device id - * @param[in] enable A_TRUE or A_FALSE - * @return SW_OK or error code - */ -sw_error_t -fal_mib_cpukeep_set(a_uint32_t dev_id, a_bool_t enable) -{ - sw_error_t rv; - - FAL_API_LOCK; - rv = _fal_mib_cpukeep_set(dev_id, enable); - FAL_API_UNLOCK; - return rv; -} - -/** - * @brief Get mib status on a particular device. - * @param[in] dev_id device id - * @param[in] enable A_TRUE or A_FALSE - * @return SW_OK or error code - */ -sw_error_t -fal_mib_cpukeep_get(a_uint32_t dev_id, a_bool_t * enable) -{ - sw_error_t rv; - - FAL_API_LOCK; - rv = _fal_mib_cpukeep_get(dev_id, enable); - FAL_API_UNLOCK; - return rv; -} - -/** - * @brief Get xgmacmib infomation on particular port. - * @param[in] dev_id device id - * @param[in] port_id port id - * @param[out] mib_info mib infomation - * @return SW_OK or error code - */ -sw_error_t -fal_get_xgmib_info(a_uint32_t dev_id, fal_port_t port_id, - fal_xgmib_info_t * mib_Info) -{ - sw_error_t rv; - fal_mib_counter_t gmac_mib = { 0 }; - - FAL_API_LOCK; - rv = _fal_get_xgmib_info(dev_id, port_id, mib_Info); - FAL_API_UNLOCK; - SW_RTN_ON_ERROR(rv); - - rv = fal_mib_counter_get(dev_id, port_id, &gmac_mib); - SW_RTN_ON_ERROR(rv); - - mib_Info->RxFrame += (gmac_mib.RxBroad + - gmac_mib.RxMulti + gmac_mib.RxUniCast); - mib_Info->RxByte += (gmac_mib.RxGoodByte+gmac_mib.RxBadByte); - mib_Info->RxByteGood += gmac_mib.RxGoodByte; - mib_Info->RxBroadGood += gmac_mib.RxBroad; - mib_Info->RxMultiGood += gmac_mib.RxMulti; - mib_Info->RxFcsErr += gmac_mib.RxFcsErr; - mib_Info->RxRuntErr += gmac_mib.RxRunt; - mib_Info->Rx64Byte += gmac_mib.Rx64Byte; - mib_Info->Rx128Byte += gmac_mib.Rx128Byte; - mib_Info->Rx256Byte += gmac_mib.Rx256Byte; - mib_Info->Rx512Byte += gmac_mib.Rx512Byte; - mib_Info->Rx1024Byte += gmac_mib.Rx1024Byte; - mib_Info->RxMaxByte += (gmac_mib.Rx1518Byte + gmac_mib.RxMaxByte); - mib_Info->RxUnicastGood += gmac_mib.RxUniCast; - mib_Info->RxLengthError += gmac_mib.RxTooLong; - mib_Info->RxPause += gmac_mib.RxPause; - mib_Info->RxOverFlow += gmac_mib.RxOverFlow; - - mib_Info->TxByte += gmac_mib.TxByte; - mib_Info->TxFrame += (gmac_mib.TxBroad + - gmac_mib.TxMulti + gmac_mib.TxUniCast); - mib_Info->TxBroadGood += gmac_mib.TxBroad; - mib_Info->TxMultiGood += gmac_mib.TxMulti; - mib_Info->Tx64Byte += gmac_mib.Tx64Byte; - mib_Info->Tx128Byte += gmac_mib.Tx128Byte; - mib_Info->Tx256Byte += gmac_mib.Tx256Byte; - mib_Info->Tx512Byte += gmac_mib.Tx512Byte; - mib_Info->Tx1024Byte += gmac_mib.Tx1024Byte; - mib_Info->TxMaxByte += (gmac_mib.Tx1518Byte + gmac_mib.TxMaxByte); - mib_Info->TxUnicast += gmac_mib.TxUniCast; - mib_Info->TxMulti += gmac_mib.TxMulti; - mib_Info->TxBroad += gmac_mib.TxBroad; - mib_Info->TxByteGood += gmac_mib.TxByte; - mib_Info->TxFrameGood += (gmac_mib.TxBroad + - gmac_mib.TxMulti + gmac_mib.TxUniCast); - mib_Info->TxPause += gmac_mib.TxPause; - - return rv; -} - -/** - * @brief Get RX xgmacmib infomation on particular port. - * @param[in] dev_id device id - * @param[in] port_id port id - * @param[out] mib_info mib infomation - * @return SW_OK or error code - */ -sw_error_t -fal_get_rx_xgmib_info(a_uint32_t dev_id, fal_port_t port_id, - fal_xgmib_info_t * mib_Info) -{ - sw_error_t rv; - - FAL_API_LOCK; - rv = _fal_get_rx_xgmib_info(dev_id, port_id, mib_Info); - FAL_API_UNLOCK; - return rv; -} - -/** - * @brief Get TX xgmacmib infomation on particular port. - * @param[in] dev_id device id - * @param[in] port_id port id - * @param[out] mib_info mib infomation - * @return SW_OK or error code - */ -sw_error_t -fal_get_tx_xgmib_info(a_uint32_t dev_id, fal_port_t port_id, - fal_xgmib_info_t * mib_Info) -{ - sw_error_t rv; - - FAL_API_LOCK; - rv = _fal_get_tx_xgmib_info(dev_id, port_id, mib_Info); - FAL_API_UNLOCK; - return rv; -} - -EXPORT_SYMBOL(fal_get_mib_info); -EXPORT_SYMBOL(fal_get_rx_mib_info); -EXPORT_SYMBOL(fal_get_tx_mib_info); -EXPORT_SYMBOL(fal_get_xgmib_info); -EXPORT_SYMBOL(fal_get_rx_xgmib_info); -EXPORT_SYMBOL(fal_get_tx_xgmib_info); -EXPORT_SYMBOL(fal_mib_status_set); -EXPORT_SYMBOL(fal_mib_status_get); -EXPORT_SYMBOL(fal_mib_port_flush_counters); -EXPORT_SYMBOL(fal_mib_cpukeep_set); -EXPORT_SYMBOL(fal_mib_cpukeep_get); -EXPORT_SYMBOL(fal_mib_counter_get); - -/*insert flag for outter fal, don't remove it*/ -/** - * @} - */ diff --git a/feeds/ipq807x/qca-ssdk/src/src/fal/fal_mirror.c b/feeds/ipq807x/qca-ssdk/src/src/fal/fal_mirror.c deleted file mode 100755 index 21856a39b..000000000 --- a/feeds/ipq807x/qca-ssdk/src/src/fal/fal_mirror.c +++ /dev/null @@ -1,344 +0,0 @@ -/* - * Copyright (c) 2012, 2016-2017, The Linux Foundation. All rights reserved. - * Permission to use, copy, modify, and/or distribute this software for - * any purpose with or without fee is hereby granted, provided that the - * above copyright notice and this permission notice appear in all copies. - * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES - * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR - * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES - * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN - * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT - * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. - */ - - -/** - * @defgroup fal_mirror FAL_MIRROR - * @{ - */ -#include "sw.h" -#include "fal_mirror.h" -#include "hsl_api.h" -#include "adpt.h" - -#include -#include - - - -static sw_error_t -_fal_mirr_analysis_port_set(a_uint32_t dev_id, fal_port_t port_id) -{ - sw_error_t rv; - hsl_api_t *p_api; - adpt_api_t *p_adpt_api; - - if((p_adpt_api = adpt_api_ptr_get(dev_id)) != NULL) { - if (NULL == p_adpt_api->adpt_mirr_analysis_port_set) - return SW_NOT_SUPPORTED; - - rv = p_adpt_api->adpt_mirr_analysis_port_set(dev_id, port_id); - return rv; - } - - SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id)); - - if (NULL == p_api->mirr_analysis_port_set) - return SW_NOT_SUPPORTED; - - rv = p_api->mirr_analysis_port_set(dev_id, port_id); - return rv; -} - -static sw_error_t -_fal_mirr_analysis_port_get(a_uint32_t dev_id, fal_port_t * port_id) -{ - sw_error_t rv; - hsl_api_t *p_api; - adpt_api_t *p_adpt_api; - - if((p_adpt_api = adpt_api_ptr_get(dev_id)) != NULL) { - if (NULL == p_adpt_api->adpt_mirr_analysis_port_get) - return SW_NOT_SUPPORTED; - - rv = p_adpt_api->adpt_mirr_analysis_port_get(dev_id, port_id); - return rv; - } - - SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id)); - - if (NULL == p_api->mirr_analysis_port_get) - return SW_NOT_SUPPORTED; - - rv = p_api->mirr_analysis_port_get(dev_id, port_id); - return rv; -} - -static sw_error_t -_fal_mirr_port_in_set(a_uint32_t dev_id, fal_port_t port_id, a_bool_t enable) -{ - sw_error_t rv; - hsl_api_t *p_api; - adpt_api_t *p_adpt_api; - - if((p_adpt_api = adpt_api_ptr_get(dev_id)) != NULL) { - if (NULL == p_adpt_api->adpt_mirr_port_in_set) - return SW_NOT_SUPPORTED; - - rv = p_adpt_api->adpt_mirr_port_in_set(dev_id, port_id, enable); - return rv; - } - - SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id)); - - if (NULL == p_api->mirr_port_in_set) - return SW_NOT_SUPPORTED; - - rv = p_api->mirr_port_in_set(dev_id, port_id, enable); - return rv; -} - - -static sw_error_t -_fal_mirr_port_in_get(a_uint32_t dev_id, fal_port_t port_id, a_bool_t * enable) -{ - sw_error_t rv; - hsl_api_t *p_api; - adpt_api_t *p_adpt_api; - - if((p_adpt_api = adpt_api_ptr_get(dev_id)) != NULL) { - if (NULL == p_adpt_api->adpt_mirr_port_in_get) - return SW_NOT_SUPPORTED; - - rv = p_adpt_api->adpt_mirr_port_in_get(dev_id, port_id, enable); - return rv; - } - - SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id)); - - if (NULL == p_api->mirr_port_in_get) - return SW_NOT_SUPPORTED; - - rv = p_api->mirr_port_in_get(dev_id, port_id, enable); - return rv; -} - -static sw_error_t -_fal_mirr_port_eg_set(a_uint32_t dev_id, fal_port_t port_id, a_bool_t enable) -{ - sw_error_t rv; - hsl_api_t *p_api; - adpt_api_t *p_adpt_api; - - if((p_adpt_api = adpt_api_ptr_get(dev_id)) != NULL) { - if (NULL == p_adpt_api->adpt_mirr_port_eg_set) - return SW_NOT_SUPPORTED; - - rv = p_adpt_api->adpt_mirr_port_eg_set(dev_id, port_id, enable); - return rv; - } - - SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id)); - - if (NULL == p_api->mirr_port_eg_set) - return SW_NOT_SUPPORTED; - - rv = p_api->mirr_port_eg_set(dev_id, port_id, enable); - return rv; -} - - -static sw_error_t -_fal_mirr_port_eg_get(a_uint32_t dev_id, fal_port_t port_id, a_bool_t * enable) -{ - sw_error_t rv; - hsl_api_t *p_api; - adpt_api_t *p_adpt_api; - - if((p_adpt_api = adpt_api_ptr_get(dev_id)) != NULL) { - if (NULL == p_adpt_api->adpt_mirr_port_eg_get) - return SW_NOT_SUPPORTED; - - rv = p_adpt_api->adpt_mirr_port_eg_get(dev_id, port_id, enable); - return rv; - } - - SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id)); - - if (NULL == p_api->mirr_port_eg_get) - return SW_NOT_SUPPORTED; - - rv = p_api->mirr_port_eg_get(dev_id, port_id, enable); - return rv; -} -sw_error_t -_fal_mirr_analysis_config_set(a_uint32_t dev_id, fal_mirr_direction_t direction, fal_mirr_analysis_config_t * config) -{ - adpt_api_t *p_api; - sw_error_t rv = SW_OK; - - SW_RTN_ON_NULL(p_api = adpt_api_ptr_get(dev_id)); - - if (NULL == p_api->adpt_mirr_analysis_config_set) - return SW_NOT_SUPPORTED; - - rv = p_api->adpt_mirr_analysis_config_set(dev_id, direction, config); - return rv; -} -sw_error_t -_fal_mirr_analysis_config_get(a_uint32_t dev_id, fal_mirr_direction_t direction, fal_mirr_analysis_config_t * config) -{ - adpt_api_t *p_api; - sw_error_t rv = SW_OK; - - SW_RTN_ON_NULL(p_api = adpt_api_ptr_get(dev_id)); - - if (NULL == p_api->adpt_mirr_analysis_config_get) - return SW_NOT_SUPPORTED; - - rv = p_api->adpt_mirr_analysis_config_get(dev_id, direction, config); - return rv; -} -/*insert flag for inner fal, don't remove it*/ -/** - * @details Comments: - * The analysis port works for both ingress and egress mirror. - * @brief Set mirror analyzer port on particular a device. - * @param[in] dev_id device id - * @param[in] port_id port id - * @return SW_OK or error code - */ -sw_error_t -fal_mirr_analysis_port_set(a_uint32_t dev_id, fal_port_t port_id) -{ - sw_error_t rv; - - FAL_API_LOCK; - rv = _fal_mirr_analysis_port_set(dev_id, port_id); - FAL_API_UNLOCK; - return rv; -} - -/** - * @brief Get mirror analysis port on particular a device. - * @param[in] dev_id device id - * @param[out] port_id port id - * @return SW_OK or error code - */ -sw_error_t -fal_mirr_analysis_port_get(a_uint32_t dev_id, fal_port_t * port_id) -{ - sw_error_t rv; - - FAL_API_LOCK; - rv = _fal_mirr_analysis_port_get(dev_id, port_id); - FAL_API_UNLOCK; - return rv; -} - -/** - * @brief Set ingress mirror status on particular a port. - * @param[in] dev_id device id - * @param[in] port_id port id - * @param[in] enable A_TRUE or A_FALSE - * @return SW_OK or error code - */ -sw_error_t -fal_mirr_port_in_set(a_uint32_t dev_id, fal_port_t port_id, a_bool_t enable) -{ - sw_error_t rv; - - FAL_API_LOCK; - rv = _fal_mirr_port_in_set(dev_id, port_id, enable); - FAL_API_UNLOCK; - return rv; -} - -/** - * @brief Get ingress mirror status on particular a port. - * @param[in] dev_id device id - * @param[in] port_id port id - * @param[out] enable A_TRUE or A_FALSE - * @return SW_OK or error code - */ -sw_error_t -fal_mirr_port_in_get(a_uint32_t dev_id, fal_port_t port_id, a_bool_t * enable) -{ - sw_error_t rv; - - FAL_API_LOCK; - rv = _fal_mirr_port_in_get(dev_id, port_id, enable); - FAL_API_UNLOCK; - return rv; -} - -/** - * @brief Set egress mirror status on a particular port. - * @param[in] dev_id device id - * @param[in] port_id port id - * @param[in] enable A_TRUE or A_FALSE - * @return SW_OK or error code - */ -sw_error_t -fal_mirr_port_eg_set(a_uint32_t dev_id, fal_port_t port_id, a_bool_t enable) -{ - sw_error_t rv; - - FAL_API_LOCK; - rv = _fal_mirr_port_eg_set(dev_id, port_id, enable); - FAL_API_UNLOCK; - return rv; -} - -/** - * @brief Get egress mirror status on a particular port. - * @param[in] dev_id device id - * @param[in] port_id port id - * @param[out] enable A_TRUE or A_FALSE - * @return SW_OK or error code - */ -sw_error_t -fal_mirr_port_eg_get(a_uint32_t dev_id, fal_port_t port_id, a_bool_t * enable) -{ - sw_error_t rv; - - FAL_API_LOCK; - rv = _fal_mirr_port_eg_get(dev_id, port_id, enable); - FAL_API_UNLOCK; - return rv; -} -sw_error_t -fal_mirr_analysis_config_set(a_uint32_t dev_id, fal_mirr_direction_t direction, fal_mirr_analysis_config_t * config) -{ - sw_error_t rv = SW_OK; - - FAL_API_LOCK; - rv = _fal_mirr_analysis_config_set(dev_id, direction, config); - FAL_API_UNLOCK; - return rv; -} -sw_error_t -fal_mirr_analysis_config_get(a_uint32_t dev_id, fal_mirr_direction_t direction, fal_mirr_analysis_config_t * config) -{ - sw_error_t rv = SW_OK; - - FAL_API_LOCK; - rv = _fal_mirr_analysis_config_get(dev_id, direction, config); - FAL_API_UNLOCK; - return rv; -} -/*insert flag for outter fal, don't remove it*/ - -EXPORT_SYMBOL(fal_mirr_analysis_port_set); -EXPORT_SYMBOL(fal_mirr_analysis_port_get); -EXPORT_SYMBOL(fal_mirr_port_in_set); -EXPORT_SYMBOL(fal_mirr_port_in_get); -EXPORT_SYMBOL(fal_mirr_port_eg_set); -EXPORT_SYMBOL(fal_mirr_port_eg_get); -EXPORT_SYMBOL(fal_mirr_analysis_config_set); -EXPORT_SYMBOL(fal_mirr_analysis_config_get); - -/** - * @} - */ diff --git a/feeds/ipq807x/qca-ssdk/src/src/fal/fal_misc.c b/feeds/ipq807x/qca-ssdk/src/src/fal/fal_misc.c deleted file mode 100755 index 66623a8b4..000000000 --- a/feeds/ipq807x/qca-ssdk/src/src/fal/fal_misc.c +++ /dev/null @@ -1,1772 +0,0 @@ -/* - * Copyright (c) 2012, 2017, 2020, The Linux Foundation. All rights reserved. - * Permission to use, copy, modify, and/or distribute this software for - * any purpose with or without fee is hereby granted, provided that the - * above copyright notice and this permission notice appear in all copies. - * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES - * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR - * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES - * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN - * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT - * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. - */ - - - -/** -* @defgroup fal_gen FAL_MISC -* @{ -*/ -#include "sw.h" -#include "fal_misc.h" -#include "hsl_api.h" -#include "adpt.h" - -#ifndef IN_MISC_MINI -static sw_error_t -_fal_arp_status_set(a_uint32_t dev_id, a_bool_t enable) -{ - sw_error_t rv; - hsl_api_t *p_api; - - SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id)); - - if (NULL == p_api->arp_status_set) - return SW_NOT_SUPPORTED; - - rv = p_api->arp_status_set(dev_id, enable); - return rv; -} - - -static sw_error_t -_fal_arp_status_get(a_uint32_t dev_id, a_bool_t * enable) -{ - sw_error_t rv; - hsl_api_t *p_api; - - SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id)); - - if (NULL == p_api->arp_status_get) - return SW_NOT_SUPPORTED; - - rv = p_api->arp_status_get(dev_id, enable); - return rv; -} -#endif - -static sw_error_t -_fal_frame_max_size_set(a_uint32_t dev_id, a_uint32_t size) -{ - sw_error_t rv; - hsl_api_t *p_api; - - SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id)); - - if (NULL == p_api->frame_max_size_set) - return SW_NOT_SUPPORTED; - - rv = p_api->frame_max_size_set(dev_id, size); - return rv; -} - - -static sw_error_t -_fal_frame_max_size_get(a_uint32_t dev_id, a_uint32_t * size) -{ - sw_error_t rv; - hsl_api_t *p_api; - - SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id)); - - if (NULL == p_api->frame_max_size_get) - return SW_NOT_SUPPORTED; - - rv = p_api->frame_max_size_get(dev_id, size); - return rv; -} - - -static sw_error_t -_fal_port_unk_sa_cmd_set(a_uint32_t dev_id, fal_port_t port_id, - fal_fwd_cmd_t cmd) -{ - sw_error_t rv; - hsl_api_t *p_api; - - SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id)); - - if (NULL == p_api->port_unk_sa_cmd_set) - return SW_NOT_SUPPORTED; - - rv = p_api->port_unk_sa_cmd_set(dev_id, port_id, cmd); - return rv; -} - -static sw_error_t -_fal_port_unk_uc_filter_set(a_uint32_t dev_id, fal_port_t port_id, - a_bool_t enable) -{ - sw_error_t rv; - hsl_api_t *p_api; - - SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id)); - - if (NULL == p_api->port_unk_uc_filter_set) - return SW_NOT_SUPPORTED; - - rv = p_api->port_unk_uc_filter_set(dev_id, port_id, enable); - return rv; -} - -static sw_error_t -_fal_port_unk_mc_filter_set(a_uint32_t dev_id, fal_port_t port_id, - a_bool_t enable) -{ - sw_error_t rv; - hsl_api_t *p_api; - - SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id)); - - if (NULL == p_api->port_unk_mc_filter_set) - return SW_NOT_SUPPORTED; - - rv = p_api->port_unk_mc_filter_set(dev_id, port_id, enable); - return rv; -} - -static sw_error_t -_fal_port_bc_filter_set(a_uint32_t dev_id, fal_port_t port_id, - a_bool_t enable) -{ - sw_error_t rv; - hsl_api_t *p_api; - - SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id)); - - if (NULL == p_api->port_bc_filter_set) - return SW_NOT_SUPPORTED; - - rv = p_api->port_bc_filter_set(dev_id, port_id, enable); - return rv; -} - -static sw_error_t -_fal_cpu_port_status_set(a_uint32_t dev_id, a_bool_t enable) -{ - sw_error_t rv; - hsl_api_t *p_api; - - SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id)); - - if (NULL == p_api->cpu_port_status_set) - return SW_NOT_SUPPORTED; - - rv = p_api->cpu_port_status_set(dev_id, enable); - return rv; -} - -#ifndef IN_MISC_MINI -static sw_error_t -_fal_port_unk_sa_cmd_get(a_uint32_t dev_id, fal_port_t port_id, - fal_fwd_cmd_t * cmd) -{ - sw_error_t rv; - hsl_api_t *p_api; - - SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id)); - - if (NULL == p_api->port_unk_sa_cmd_get) - return SW_NOT_SUPPORTED; - - rv = p_api->port_unk_sa_cmd_get(dev_id, port_id, cmd); - return rv; -} - - -static sw_error_t -_fal_port_unk_uc_filter_get(a_uint32_t dev_id, fal_port_t port_id, - a_bool_t * enable) -{ - sw_error_t rv; - hsl_api_t *p_api; - - SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id)); - - if (NULL == p_api->port_unk_uc_filter_get) - return SW_NOT_SUPPORTED; - - rv = p_api->port_unk_uc_filter_get(dev_id, port_id, enable); - return rv; -} - - -static sw_error_t -_fal_port_unk_mc_filter_get(a_uint32_t dev_id, fal_port_t port_id, - a_bool_t * enable) -{ - sw_error_t rv; - hsl_api_t *p_api; - - SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id)); - - if (NULL == p_api->port_unk_mc_filter_get) - return SW_NOT_SUPPORTED; - - rv = p_api->port_unk_mc_filter_get(dev_id, port_id, enable); - return rv; -} - - -static sw_error_t -_fal_port_bc_filter_get(a_uint32_t dev_id, fal_port_t port_id, - a_bool_t * enable) -{ - sw_error_t rv; - hsl_api_t *p_api; - - SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id)); - - if (NULL == p_api->port_bc_filter_get) - return SW_NOT_SUPPORTED; - - rv = p_api->port_bc_filter_get(dev_id, port_id, enable); - return rv; -} - -static sw_error_t -_fal_cpu_port_status_get(a_uint32_t dev_id, a_bool_t * enable) -{ - sw_error_t rv; - hsl_api_t *p_api; - - SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id)); - - if (NULL == p_api->cpu_port_status_get) - return SW_NOT_SUPPORTED; - - rv = p_api->cpu_port_status_get(dev_id, enable); - return rv; -} - - -static sw_error_t -_fal_bc_to_cpu_port_set(a_uint32_t dev_id, a_bool_t enable) -{ - sw_error_t rv; - hsl_api_t *p_api; - - SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id)); - - if (NULL == p_api->bc_to_cpu_port_set) - return SW_NOT_SUPPORTED; - - rv = p_api->bc_to_cpu_port_set(dev_id, enable); - return rv; -} - - -static sw_error_t -_fal_bc_to_cpu_port_get(a_uint32_t dev_id, a_bool_t * enable) -{ - sw_error_t rv; - hsl_api_t *p_api; - - SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id)); - - if (NULL == p_api->bc_to_cpu_port_get) - return SW_NOT_SUPPORTED; - - rv = p_api->bc_to_cpu_port_get(dev_id, enable); - return rv; -} - - -static sw_error_t -_fal_port_dhcp_set(a_uint32_t dev_id, fal_port_t port_id, a_bool_t enable) -{ - sw_error_t rv; - hsl_api_t *p_api; - - SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id)); - - if (NULL == p_api->port_dhcp_set) - return SW_NOT_SUPPORTED; - - rv = p_api->port_dhcp_set(dev_id, port_id, enable); - return rv; -} - -static sw_error_t -_fal_port_dhcp_get(a_uint32_t dev_id, fal_port_t port_id, a_bool_t * enable) -{ - sw_error_t rv; - hsl_api_t *p_api; - - SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id)); - - if (NULL == p_api->port_dhcp_get) - return SW_NOT_SUPPORTED; - - rv = p_api->port_dhcp_get(dev_id, port_id, enable); - return rv; -} - -static sw_error_t -_fal_arp_cmd_set(a_uint32_t dev_id, fal_fwd_cmd_t cmd) -{ - sw_error_t rv; - hsl_api_t *p_api; - - SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id)); - - if (NULL == p_api->arp_cmd_set) - return SW_NOT_SUPPORTED; - - rv = p_api->arp_cmd_set(dev_id, cmd); - return rv; -} - -static sw_error_t -_fal_arp_cmd_get(a_uint32_t dev_id, fal_fwd_cmd_t * cmd) -{ - sw_error_t rv; - hsl_api_t *p_api; - - SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id)); - - if (NULL == p_api->arp_cmd_get) - return SW_NOT_SUPPORTED; - - rv = p_api->arp_cmd_get(dev_id, cmd); - return rv; -} -#endif - -static sw_error_t -_fal_eapol_cmd_set(a_uint32_t dev_id, fal_fwd_cmd_t cmd) -{ - sw_error_t rv; - hsl_api_t *p_api; - - SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id)); - - if (NULL == p_api->eapol_cmd_set) - return SW_NOT_SUPPORTED; - - rv = p_api->eapol_cmd_set(dev_id, cmd); - return rv; -} - -#ifndef IN_MISC_MINI -static sw_error_t -_fal_eapol_cmd_get(a_uint32_t dev_id, fal_fwd_cmd_t * cmd) -{ - sw_error_t rv; - hsl_api_t *p_api; - - SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id)); - - if (NULL == p_api->eapol_cmd_get) - return SW_NOT_SUPPORTED; - - rv = p_api->eapol_cmd_get(dev_id, cmd); - return rv; -} -#endif - -static sw_error_t -_fal_eapol_status_set(a_uint32_t dev_id, a_uint32_t port_id, a_bool_t enable) -{ - sw_error_t rv; - hsl_api_t *p_api; - - SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id)); - - if (NULL == p_api->eapol_status_set) - return SW_NOT_SUPPORTED; - - rv = p_api->eapol_status_set(dev_id, port_id, enable); - return rv; -} - -#ifndef IN_MISC_MINI -static sw_error_t -_fal_eapol_status_get(a_uint32_t dev_id, a_uint32_t port_id, a_bool_t * enable) -{ - sw_error_t rv; - hsl_api_t *p_api; - - SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id)); - - if (NULL == p_api->eapol_status_get) - return SW_NOT_SUPPORTED; - - rv = p_api->eapol_status_get(dev_id, port_id, enable); - return rv; -} - -static sw_error_t -_fal_ripv1_status_set(a_uint32_t dev_id, a_bool_t enable) -{ - sw_error_t rv; - hsl_api_t *p_api; - - SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id)); - - if (NULL == p_api->ripv1_status_set) - return SW_NOT_SUPPORTED; - - rv = p_api->ripv1_status_set(dev_id, enable); - return rv; -} - -static sw_error_t -_fal_ripv1_status_get(a_uint32_t dev_id, a_bool_t * enable) -{ - sw_error_t rv; - hsl_api_t *p_api; - - SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id)); - - if (NULL == p_api->ripv1_status_get) - return SW_NOT_SUPPORTED; - - rv = p_api->ripv1_status_get(dev_id, enable); - return rv; -} - -static sw_error_t -_fal_port_arp_req_status_set(a_uint32_t dev_id, fal_port_t port_id, - a_bool_t enable) -{ - sw_error_t rv; - hsl_api_t *p_api; - - SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id)); - - if (NULL == p_api->port_arp_req_status_set) - return SW_NOT_SUPPORTED; - - rv = p_api->port_arp_req_status_set(dev_id, port_id, enable); - return rv; -} - -static sw_error_t -_fal_port_arp_req_status_get(a_uint32_t dev_id, fal_port_t port_id, - a_bool_t * enable) -{ - sw_error_t rv; - hsl_api_t *p_api; - - SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id)); - - if (NULL == p_api->port_arp_req_status_get) - return SW_NOT_SUPPORTED; - - rv = p_api->port_arp_req_status_get(dev_id, port_id, enable); - return rv; -} - -static sw_error_t -_fal_port_arp_ack_status_set(a_uint32_t dev_id, fal_port_t port_id, - a_bool_t enable) -{ - sw_error_t rv; - hsl_api_t *p_api; - - SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id)); - - if (NULL == p_api->port_arp_ack_status_set) - return SW_NOT_SUPPORTED; - - rv = p_api->port_arp_ack_status_set(dev_id, port_id, enable); - return rv; -} - -static sw_error_t -_fal_port_arp_ack_status_get(a_uint32_t dev_id, fal_port_t port_id, - a_bool_t * enable) -{ - sw_error_t rv; - hsl_api_t *p_api; - - SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id)); - - if (NULL == p_api->port_arp_ack_status_get) - return SW_NOT_SUPPORTED; - - rv = p_api->port_arp_ack_status_get(dev_id, port_id, enable); - return rv; -} - -static sw_error_t -_fal_intr_mask_set(a_uint32_t dev_id, a_uint32_t intr_mask) -{ - sw_error_t rv; - hsl_api_t *p_api; - - SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id)); - - if (NULL == p_api->intr_mask_set) - return SW_NOT_SUPPORTED; - - rv = p_api->intr_mask_set(dev_id, intr_mask); - return rv; -} - -static sw_error_t -_fal_intr_mask_get(a_uint32_t dev_id, a_uint32_t * intr_mask) -{ - sw_error_t rv; - hsl_api_t *p_api; - - SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id)); - - if (NULL == p_api->intr_mask_get) - return SW_NOT_SUPPORTED; - - rv = p_api->intr_mask_get(dev_id, intr_mask); - return rv; -} - -static sw_error_t -_fal_intr_status_get(a_uint32_t dev_id, a_uint32_t * intr_status) -{ - sw_error_t rv; - hsl_api_t *p_api; - - SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id)); - - if (NULL == p_api->intr_status_get) - return SW_NOT_SUPPORTED; - - rv = p_api->intr_status_get(dev_id, intr_status); - return rv; -} - -static sw_error_t -_fal_intr_status_clear(a_uint32_t dev_id, a_uint32_t intr_status) -{ - sw_error_t rv; - hsl_api_t *p_api; - - SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id)); - - if (NULL == p_api->intr_status_clear) - return SW_NOT_SUPPORTED; - - rv = p_api->intr_status_clear(dev_id, intr_status); - return rv; -} - -static sw_error_t -_fal_intr_port_link_mask_set(a_uint32_t dev_id, fal_port_t port_id, a_uint32_t intr_mask) -{ - sw_error_t rv; - hsl_api_t *p_api; - adpt_api_t *p_adpt_api; - - if((p_adpt_api = adpt_api_ptr_get(dev_id)) != NULL && - p_adpt_api->adpt_intr_port_link_mask_set != NULL) { - rv = p_adpt_api->adpt_intr_port_link_mask_set(dev_id, port_id, intr_mask); - return rv; - } - - SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id)); - - if (NULL == p_api->intr_port_link_mask_set) - return SW_NOT_SUPPORTED; - - rv = p_api->intr_port_link_mask_set(dev_id, port_id, intr_mask); - return rv; -} - -static sw_error_t -_fal_intr_port_link_mask_get(a_uint32_t dev_id, fal_port_t port_id, a_uint32_t * intr_mask) -{ - sw_error_t rv; - hsl_api_t *p_api; - adpt_api_t *p_adpt_api; - - if((p_adpt_api = adpt_api_ptr_get(dev_id)) != NULL && - p_adpt_api->adpt_intr_port_link_mask_get != NULL) { - rv = p_adpt_api->adpt_intr_port_link_mask_get(dev_id, port_id, intr_mask); - return rv; - } - - SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id)); - - if (NULL == p_api->intr_port_link_mask_get) - return SW_NOT_SUPPORTED; - - rv = p_api->intr_port_link_mask_get(dev_id, port_id, intr_mask); - return rv; -} - -static sw_error_t -_fal_intr_port_link_status_get(a_uint32_t dev_id, fal_port_t port_id, a_uint32_t * intr_mask) -{ - sw_error_t rv; - hsl_api_t *p_api; - adpt_api_t *p_adpt_api; - - if((p_adpt_api = adpt_api_ptr_get(dev_id)) != NULL && - p_adpt_api->adpt_intr_port_link_status_get != NULL) { - rv = p_adpt_api->adpt_intr_port_link_status_get(dev_id, port_id, intr_mask); - return rv; - } - - SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id)); - - if (NULL == p_api->intr_port_link_status_get) - return SW_NOT_SUPPORTED; - - rv = p_api->intr_port_link_status_get(dev_id, port_id, intr_mask); - return rv; -} - - - -static sw_error_t -_fal_intr_mask_mac_linkchg_set(a_uint32_t dev_id, a_uint32_t port_id, a_bool_t enable) -{ - sw_error_t rv; - hsl_api_t *p_api; - - SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id)); - - if (NULL == p_api->intr_mask_mac_linkchg_set) - return SW_NOT_SUPPORTED; - - rv = p_api->intr_mask_mac_linkchg_set(dev_id, port_id, enable); - return rv; -} - - -static sw_error_t -_fal_intr_mask_mac_linkchg_get(a_uint32_t dev_id, a_uint32_t port_id, a_bool_t * enable) -{ - sw_error_t rv; - hsl_api_t *p_api; - - SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id)); - - if (NULL == p_api->intr_mask_mac_linkchg_get) - return SW_NOT_SUPPORTED; - - rv = p_api->intr_mask_mac_linkchg_get(dev_id, port_id, enable); - return rv; -} - - -static sw_error_t -_fal_intr_status_mac_linkchg_get(a_uint32_t dev_id, fal_pbmp_t* port_bitmap) -{ - sw_error_t rv; - hsl_api_t *p_api; - - SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id)); - - if (NULL == p_api->intr_status_mac_linkchg_get) - return SW_NOT_SUPPORTED; - - rv = p_api->intr_status_mac_linkchg_get(dev_id, port_bitmap); - return rv; -} - -static sw_error_t -_fal_cpu_vid_en_set(a_uint32_t dev_id, a_bool_t enable) -{ - sw_error_t rv; - hsl_api_t *p_api; - - SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id)); - - if (NULL == p_api->cpu_vid_en_set) - return SW_NOT_SUPPORTED; - - rv = p_api->cpu_vid_en_set(dev_id, enable); - return rv; -} - - -static sw_error_t -_fal_cpu_vid_en_get(a_uint32_t dev_id, a_bool_t * enable) -{ - sw_error_t rv; - hsl_api_t *p_api; - - SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id)); - - if (NULL == p_api->cpu_vid_en_get) - return SW_NOT_SUPPORTED; - - rv = p_api->cpu_vid_en_get(dev_id, enable); - return rv; -} - -static sw_error_t -_fal_intr_status_mac_linkchg_clear(a_uint32_t dev_id) -{ - sw_error_t rv; - hsl_api_t *p_api; - - SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id)); - - if (NULL == p_api->intr_status_mac_linkchg_clear) - return SW_NOT_SUPPORTED; - - rv = p_api->intr_status_mac_linkchg_clear(dev_id); - return rv; -} - - -static sw_error_t -_fal_global_macaddr_set(a_uint32_t dev_id, fal_mac_addr_t * addr) -{ - sw_error_t rv; - hsl_api_t *p_api; - - SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id)); - - if (NULL == p_api->global_macaddr_set) - return SW_NOT_SUPPORTED; - - rv = p_api->global_macaddr_set(dev_id, addr); - return rv; -} - -static sw_error_t -_fal_global_macaddr_get(a_uint32_t dev_id, fal_mac_addr_t * addr) -{ - sw_error_t rv; - hsl_api_t *p_api; - - SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id)); - - if (NULL == p_api->global_macaddr_get) - return SW_NOT_SUPPORTED; - - rv = p_api->global_macaddr_get(dev_id, addr); - return rv; -} - -static sw_error_t -_fal_lldp_status_set(a_uint32_t dev_id, a_bool_t enable) -{ - sw_error_t rv; - hsl_api_t *p_api; - - SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id)); - - if (NULL == p_api->lldp_status_set) - return SW_NOT_SUPPORTED; - - rv = p_api->lldp_status_set(dev_id, enable); - return rv; -} - -static sw_error_t -_fal_lldp_status_get(a_uint32_t dev_id, a_bool_t * enable) -{ - sw_error_t rv; - hsl_api_t *p_api; - - SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id)); - - if (NULL == p_api->lldp_status_get) - return SW_NOT_SUPPORTED; - - rv = p_api->lldp_status_get(dev_id, enable); - return rv; -} - -static sw_error_t -_fal_frame_crc_reserve_set(a_uint32_t dev_id, a_bool_t enable) -{ - sw_error_t rv; - hsl_api_t *p_api; - - SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id)); - - if (NULL == p_api->frame_crc_reserve_set) - return SW_NOT_SUPPORTED; - - rv = p_api->frame_crc_reserve_set(dev_id, enable); - return rv; -} - -static sw_error_t -_fal_frame_crc_reserve_get(a_uint32_t dev_id, a_bool_t * enable) -{ - sw_error_t rv; - hsl_api_t *p_api; - - SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id)); - - if (NULL == p_api->frame_crc_reserve_get) - return SW_NOT_SUPPORTED; - - rv = p_api->frame_crc_reserve_get(dev_id, enable); - return rv; -} - -sw_error_t -_fal_debug_port_counter_enable(a_uint32_t dev_id, fal_port_t port_id, fal_counter_en_t * cnt_en) -{ - sw_error_t rv; - adpt_api_t *p_api; - - SW_RTN_ON_NULL(p_api = adpt_api_ptr_get(dev_id)); - - if (NULL == p_api->adpt_debug_port_counter_enable) - return SW_NOT_SUPPORTED; - - rv = p_api->adpt_debug_port_counter_enable(dev_id, port_id, cnt_en); - return rv; -} - -sw_error_t -_fal_debug_port_counter_status_get(a_uint32_t dev_id, fal_port_t port_id, fal_counter_en_t * cnt_en) -{ - sw_error_t rv; - adpt_api_t *p_api; - - SW_RTN_ON_NULL(p_api = adpt_api_ptr_get(dev_id)); - - if (NULL == p_api->adpt_debug_port_counter_status_get) - return SW_NOT_SUPPORTED; - - rv = p_api->adpt_debug_port_counter_status_get(dev_id, port_id, cnt_en); - return rv; -} - -/** - * @brief Set arp packets hardware acknowledgement status on a particular device. - * @param[in] dev_id device id - * @param[in] enable A_TRUE or A_FALSE - * @return SW_OK or error code - */ -sw_error_t -fal_arp_status_set(a_uint32_t dev_id, a_bool_t enable) -{ - sw_error_t rv; - - FAL_API_LOCK; - rv = _fal_arp_status_set(dev_id, enable); - FAL_API_UNLOCK; - return rv; -} - -/** - * @brief Get arp packets hardware acknowledgement status on a particular device. - * @param[in] dev_id device id - * @param[out] enable A_TRUE or A_FALSE - * @return SW_OK or error code - */ -sw_error_t -fal_arp_status_get(a_uint32_t dev_id, a_bool_t * enable) -{ - sw_error_t rv; - - FAL_API_LOCK; - rv = _fal_arp_status_get(dev_id, enable); - FAL_API_UNLOCK; - return rv; -} -#endif - -/** - * @brief Set max frame size which device can received on a particular device. - * @details Comments: - * The granularity of packets size is byte. - * @param[in] dev_id device id - * @param[in] size packet size - * @return SW_OK or error code - */ -sw_error_t -fal_frame_max_size_set(a_uint32_t dev_id, a_uint32_t size) -{ - sw_error_t rv; - - FAL_API_LOCK; - rv = _fal_frame_max_size_set(dev_id, size); - FAL_API_UNLOCK; - return rv; -} - -/** - * @brief Get max frame size which device can received on a particular device. - * @details Comments: - * The unit of packets size is byte. - * @param[in] dev_id device id - * @param[out] size packet size - * @return SW_OK or error code - */ -sw_error_t -fal_frame_max_size_get(a_uint32_t dev_id, a_uint32_t * size) -{ - sw_error_t rv; - - FAL_API_LOCK; - rv = _fal_frame_max_size_get(dev_id, size); - FAL_API_UNLOCK; - return rv; -} - -/** - * @brief Set forwarding command for packets which source address is unknown on a particular port. - * @details Comments: - * Particular device may only support parts of forwarding commands. - * @param[in] dev_id device id - * @param[in] port_id port id - * @param[in] cmd forwarding command - * @return SW_OK or error code - */ -sw_error_t -fal_port_unk_sa_cmd_set(a_uint32_t dev_id, fal_port_t port_id, - fal_fwd_cmd_t cmd) -{ - sw_error_t rv; - - FAL_API_LOCK; - rv = _fal_port_unk_sa_cmd_set(dev_id, port_id, cmd); - FAL_API_UNLOCK; - return rv; -} - -/** - * @brief Set flooding status of unknown unicast packets on a particular port. - * @details Comments: - * If enable unknown unicast packets filter on one port then unknown - * unicast packets can't flood out from this port. - * @param[in] dev_id device id - * @param[in] port_id port id - * @param[in] enable A_TRUE or A_FALSE - * @return SW_OK or error code - */ -sw_error_t -fal_port_unk_uc_filter_set(a_uint32_t dev_id, fal_port_t port_id, - a_bool_t enable) -{ - sw_error_t rv; - - FAL_API_LOCK; - rv = _fal_port_unk_uc_filter_set(dev_id, port_id, enable); - FAL_API_UNLOCK; - return rv; -} - -/** - * @brief Set flooding status of unknown multicast packets on a particular port. - * @details Comments: - * If enable unknown multicast packets filter on one port then unknown - * multicast packets can't flood out from this port. - * @param[in] dev_id device id - * @param[in] port_id port id - * @param[in] enable A_TRUE or A_FALSE - * @return SW_OK or error code - */ -sw_error_t -fal_port_unk_mc_filter_set(a_uint32_t dev_id, fal_port_t port_id, - a_bool_t enable) -{ - sw_error_t rv; - - FAL_API_LOCK; - rv = _fal_port_unk_mc_filter_set(dev_id, port_id, enable); - FAL_API_UNLOCK; - return rv; -} - -/** - * @brief Set flooding status of broadcast packets on a particular port. - * @details Comments: - * If enable unknown multicast packets filter on one port then unknown - * multicast packets can't flood out from this port. - * @param[in] dev_id device id - * @param[in] port_id port id - * @param[in] enable A_TRUE or A_FALSE - * @return SW_OK or error code - */ -sw_error_t -fal_port_bc_filter_set(a_uint32_t dev_id, fal_port_t port_id, - a_bool_t enable) -{ - sw_error_t rv; - - FAL_API_LOCK; - rv = _fal_port_bc_filter_set(dev_id, port_id, enable); - FAL_API_UNLOCK; - return rv; -} - -/** - * @brief Set cpu port status on a particular device. - * @param[in] dev_id device id - * @param[in] enable A_TRUE or A_FALSE - * @return SW_OK or error code - */ -sw_error_t -fal_cpu_port_status_set(a_uint32_t dev_id, a_bool_t enable) -{ - sw_error_t rv; - - FAL_API_LOCK; - rv = _fal_cpu_port_status_set(dev_id, enable); - FAL_API_UNLOCK; - return rv; -} - -#ifndef IN_MISC_MINI -/** - * @brief Get forwarding command for packets which source address is unknown on a particular port. - * @param[in] dev_id device id - * @param[in] port_id port id - * @param[out] cmd forwarding command - * @return SW_OK or error code - */ -sw_error_t -fal_port_unk_sa_cmd_get(a_uint32_t dev_id, fal_port_t port_id, - fal_fwd_cmd_t * cmd) -{ - sw_error_t rv; - - FAL_API_LOCK; - rv = _fal_port_unk_sa_cmd_get(dev_id, port_id, cmd); - FAL_API_UNLOCK; - return rv; -} - -/** - * @brief Get flooding status of unknown unicast packets on a particular port. - * @param[in] dev_id device id - * @param[in] port_id port id - * @param[out] enable A_TRUE or A_FALSE - * @return SW_OK or error code - */ -sw_error_t -fal_port_unk_uc_filter_get(a_uint32_t dev_id, fal_port_t port_id, - a_bool_t * enable) -{ - sw_error_t rv; - - FAL_API_LOCK; - rv = _fal_port_unk_uc_filter_get(dev_id, port_id, enable); - FAL_API_UNLOCK; - return rv; -} - - - -/** - * @brief Get flooding status of unknown multicast packets on a particular port. - * @param[in] dev_id device id - * @param[in] port_id port id - * @param[out] enable A_TRUE or A_FALSE - * @return SW_OK or error code - */ -sw_error_t -fal_port_unk_mc_filter_get(a_uint32_t dev_id, fal_port_t port_id, - a_bool_t * enable) -{ - sw_error_t rv; - - FAL_API_LOCK; - rv = _fal_port_unk_mc_filter_get(dev_id, port_id, enable); - FAL_API_UNLOCK; - return rv; -} - - - -/** - * @brief Get flooding status of broadcast packets on a particular port. - * @param[in] dev_id device id - * @param[in] port_id port id - * @param[out] enable A_TRUE or A_FALSE - * @return SW_OK or error code - */ -sw_error_t -fal_port_bc_filter_get(a_uint32_t dev_id, fal_port_t port_id, - a_bool_t * enable) -{ - sw_error_t rv; - - FAL_API_LOCK; - rv = _fal_port_bc_filter_get(dev_id, port_id, enable); - FAL_API_UNLOCK; - return rv; -} - -/** - * @brief Get cpu port status on a particular device. - * @param[in] dev_id device id - * @param[in] enable A_TRUE or A_FALSE - * @return SW_OK or error code - */ -sw_error_t -fal_cpu_port_status_get(a_uint32_t dev_id, a_bool_t * enable) -{ - sw_error_t rv; - - FAL_API_LOCK; - rv = _fal_cpu_port_status_get(dev_id, enable); - FAL_API_UNLOCK; - return rv; -} - -/** - * @brief Set status of braodcast packets broadcasting to cpu on a particular device. - * @param[in] dev_id device id - * @param[in] enable A_TRUE or A_FALSE - * @return SW_OK or error code - */ -sw_error_t -fal_bc_to_cpu_port_set(a_uint32_t dev_id, a_bool_t enable) -{ - sw_error_t rv; - - FAL_API_LOCK; - rv = _fal_bc_to_cpu_port_set(dev_id, enable); - FAL_API_UNLOCK; - return rv; -} - -/** - * @brief Get status of braodcast packets broadcasting to cpu on a particular device. - * @param[in] dev_id device id - * @param[in] enable A_TRUE or A_FALSE - * @return SW_OK or error code - */ -sw_error_t -fal_bc_to_cpu_port_get(a_uint32_t dev_id, a_bool_t * enable) -{ - sw_error_t rv; - - FAL_API_LOCK; - rv = _fal_bc_to_cpu_port_get(dev_id, enable); - FAL_API_UNLOCK; - return rv; -} - -/** - * @brief Set dhcp packets hardware acknowledgement status on a particular device. - * @param[in] dev_id device id - * @param[in] enable A_TRUE or A_FALSE - * @return SW_OK or error code - */ -sw_error_t -fal_port_dhcp_set(a_uint32_t dev_id, fal_port_t port_id, a_bool_t enable) -{ - sw_error_t rv; - - FAL_API_LOCK; - rv = _fal_port_dhcp_set(dev_id, port_id, enable); - FAL_API_UNLOCK; - return rv; -} - -/** - * @brief Get dhcp packets hardware acknowledgement status on a particular device. - * @param[in] dev_id device id - * @param[out] enable A_TRUE or A_FALSE - * @return SW_OK or error code - */ -sw_error_t -fal_port_dhcp_get(a_uint32_t dev_id, fal_port_t port_id, a_bool_t * enable) -{ - sw_error_t rv; - - FAL_API_LOCK; - rv = _fal_port_dhcp_get(dev_id, port_id, enable); - FAL_API_UNLOCK; - return rv; -} - -/** - * @brief Set arp packets forwarding command on a particular device. - * @details Comments: - * Particular device may only support parts of forwarding commands. - * This operation will take effect only after enabling arp - * @param[in] dev_id device id - * @param[in] cmd forwarding command - * @return SW_OK or error code - */ -sw_error_t -fal_arp_cmd_set(a_uint32_t dev_id, fal_fwd_cmd_t cmd) -{ - sw_error_t rv; - - FAL_API_LOCK; - rv = _fal_arp_cmd_set(dev_id, cmd); - FAL_API_UNLOCK; - return rv; -} - -/** - * @brief Get arp packets forwarding command on a particular device. - * @param[in] dev_id device id - * @param[out] cmd forwarding command - * @return SW_OK or error code - */ -sw_error_t -fal_arp_cmd_get(a_uint32_t dev_id, fal_fwd_cmd_t * cmd) -{ - sw_error_t rv; - - FAL_API_LOCK; - rv = _fal_arp_cmd_get(dev_id, cmd); - FAL_API_UNLOCK; - return rv; -} -#endif -/** - * @brief Set eapol packets forwarding command on a particular device. - * @details Comments: - * Particular device may only support parts of forwarding commands. - * This operation will take effect only after enabling eapol - * @param[in] dev_id device id - * @param[in] cmd forwarding command - * @return SW_OK or error code - */ -sw_error_t -fal_eapol_cmd_set(a_uint32_t dev_id, fal_fwd_cmd_t cmd) -{ - sw_error_t rv; - - FAL_API_LOCK; - rv = _fal_eapol_cmd_set(dev_id, cmd); - FAL_API_UNLOCK; - return rv; -} - -#ifndef IN_MISC_MINI -/** - * @brief Get eapol packets forwarding command on a particular device. - * @param[in] dev_id device id - * @param[out] cmd forwarding command - * @return SW_OK or error code - */ -sw_error_t -fal_eapol_cmd_get(a_uint32_t dev_id, fal_fwd_cmd_t * cmd) -{ - sw_error_t rv; - - FAL_API_LOCK; - rv = _fal_eapol_cmd_get(dev_id, cmd); - FAL_API_UNLOCK; - return rv; -} -#endif -/** - * @brief Set eapol packets hardware acknowledgement on a particular port. - * @details Comments: - * Particular device may only support parts of forwarding commands. - * This operation will take effect only after enabling eapol - * @param[in] dev_id device id - * @param[in] port_id port id - * @param[in] enable A_TRUE or A_FALSE - * @return SW_OK or error code - */ -sw_error_t -fal_eapol_status_set(a_uint32_t dev_id, a_uint32_t port_id, a_bool_t enable) -{ - sw_error_t rv; - - FAL_API_LOCK; - rv = _fal_eapol_status_set(dev_id, port_id, enable); - FAL_API_UNLOCK; - return rv; -} -#ifndef IN_MISC_MINI -/** - * @brief Get eapol packets hardware acknowledgement on a particular port. - * @param[in] dev_id device id - * @param[in] port_id port id - * @param[out] enable A_TRUE or A_FALSE - * @return SW_OK or error code - */ -sw_error_t -fal_eapol_status_get(a_uint32_t dev_id, a_uint32_t port_id, a_bool_t * enable) -{ - sw_error_t rv; - - FAL_API_LOCK; - rv = _fal_eapol_status_get(dev_id, port_id, enable); - FAL_API_UNLOCK; - return rv; -} - -/** - * @brief Set ripv1 packets hardware acknowledgement on a particular port. - * @details Comments: - * Particular device may only support parts of forwarding commands. - * This operation will take effect only after enabling eapol - * @param[in] dev_id device id - * @param[in] enable A_TRUE or A_FALSE - * @return SW_OK or error code - */ -sw_error_t -fal_ripv1_status_set(a_uint32_t dev_id, a_bool_t enable) -{ - sw_error_t rv; - - FAL_API_LOCK; - rv = _fal_ripv1_status_set(dev_id, enable); - FAL_API_UNLOCK; - return rv; -} - -/** - * @brief Get ripv1 packets hardware acknowledgement on a particular port. - * @param[in] dev_id device id - * @param[out] enable A_TRUE or A_FALSE - * @return SW_OK or error code - */ -sw_error_t -fal_ripv1_status_get(a_uint32_t dev_id, a_bool_t * enable) -{ - sw_error_t rv; - - FAL_API_LOCK; - rv = _fal_ripv1_status_get(dev_id, enable); - FAL_API_UNLOCK; - return rv; -} - -/** - * @brief Set arp req packets hardware acknowledgement status on a particular device. - * @param[in] dev_id device id - * @param[in] enable A_TRUE or A_FALSE - * @return SW_OK or error code - */ -sw_error_t -fal_port_arp_req_status_set(a_uint32_t dev_id, fal_port_t port_id, - a_bool_t enable) -{ - sw_error_t rv; - - FAL_API_LOCK; - rv = _fal_port_arp_req_status_set(dev_id, port_id, enable); - FAL_API_UNLOCK; - return rv; -} - -/** - * @brief Get arp req packets hardware acknowledgement status on a particular device. - * @param[in] dev_id device id - * @param[out] enable A_TRUE or A_FALSE - * @return SW_OK or error code - */ -sw_error_t -fal_port_arp_req_status_get(a_uint32_t dev_id, fal_port_t port_id, - a_bool_t * enable) -{ - sw_error_t rv; - - FAL_API_LOCK; - rv = _fal_port_arp_req_status_get(dev_id, port_id, enable); - FAL_API_UNLOCK; - return rv; -} - -/** - * @brief Set arp ack packets hardware acknowledgement status on a particular device. - * @param[in] dev_id device id - * @param[in] enable A_TRUE or A_FALSE - * @return SW_OK or error code - */ -sw_error_t -fal_port_arp_ack_status_set(a_uint32_t dev_id, fal_port_t port_id, - a_bool_t enable) -{ - sw_error_t rv; - - FAL_API_LOCK; - rv = _fal_port_arp_ack_status_set(dev_id, port_id, enable); - FAL_API_UNLOCK; - return rv; -} - -/** - * @brief Get arp ack packets hardware acknowledgement status on a particular device. - * @param[in] dev_id device id - * @param[out] enable A_TRUE or A_FALSE - * @return SW_OK or error code - */ -sw_error_t -fal_port_arp_ack_status_get(a_uint32_t dev_id, fal_port_t port_id, - a_bool_t * enable) -{ - sw_error_t rv; - - FAL_API_LOCK; - rv = _fal_port_arp_ack_status_get(dev_id, port_id, enable); - FAL_API_UNLOCK; - return rv; -} - -/** - * @brief Set switch interrupt mask on one particular device. - * @param[in] dev_id device id - * @param[in] intr_mask mask - * @return SW_OK or error code - */ -sw_error_t -fal_intr_mask_set(a_uint32_t dev_id, a_uint32_t intr_mask) -{ - sw_error_t rv; - - FAL_API_LOCK; - rv = _fal_intr_mask_set(dev_id, intr_mask); - FAL_API_UNLOCK; - return rv; -} - -/** - * @brief Get switch interrupt mask on one particular device. - * @param[in] dev_id device id - * @param[in] intr_mask mask - * @return SW_OK or error code - */ -sw_error_t -fal_intr_mask_get(a_uint32_t dev_id, a_uint32_t * intr_mask) -{ - sw_error_t rv; - - FAL_API_LOCK; - rv = _fal_intr_mask_get(dev_id, intr_mask); - FAL_API_UNLOCK; - return rv; -} - -/** - * @brief Get switch interrupt status on one particular device. - * @param[in] dev_id device id - * @param[in] intr_status status - * @return SW_OK or error code - */ -sw_error_t -fal_intr_status_get(a_uint32_t dev_id, a_uint32_t * intr_status) -{ - sw_error_t rv; - - FAL_API_LOCK; - rv = _fal_intr_status_get(dev_id, intr_status); - FAL_API_UNLOCK; - return rv; -} - -/** - * @brief Clear switch interrupt status on one particular device. - * @param[in] dev_id device id - * @param[in] intr_status status - * @return SW_OK or error code - */ -sw_error_t -fal_intr_status_clear(a_uint32_t dev_id, a_uint32_t intr_status) -{ - sw_error_t rv; - - FAL_API_LOCK; - rv = _fal_intr_status_clear(dev_id, intr_status); - FAL_API_UNLOCK; - return rv; -} - -/** - * @brief Set link interrupt mask on particular port. - * @param[in] dev_id device id - * @param[in] port_id port id - * @param[in] intr_mask_flag interrupt mask - * @return SW_OK or error code - */ -sw_error_t -fal_intr_port_link_mask_set(a_uint32_t dev_id, a_uint32_t port_id, a_uint32_t intr_mask_flag) -{ - sw_error_t rv; - FAL_API_LOCK; - rv = _fal_intr_port_link_mask_set(dev_id, port_id, intr_mask_flag); - FAL_API_UNLOCK; - return rv; -} - -/** - * @brief Get link interrupt mask on particular port. - * @param[in] dev_id device id - * @param[in] port_id port id - * @param[out] intr_mask_flag interrupt mask - * @return SW_OK or error code - */ -sw_error_t -fal_intr_port_link_mask_get(a_uint32_t dev_id, a_uint32_t port_id, a_uint32_t * intr_mask_flag) -{ - sw_error_t rv; - - FAL_API_LOCK; - rv = _fal_intr_port_link_mask_get(dev_id, port_id, intr_mask_flag); - FAL_API_UNLOCK; - return rv; -} - -/** - * @brief Get link interrupt status on particular port. - * @param[in] dev_id device id - * @param[in] port_id port id - * @param[out] intr_mask_flag interrupt mask - * @return SW_OK or error code - */ -sw_error_t -fal_intr_port_link_status_get(a_uint32_t dev_id, a_uint32_t port_id, a_uint32_t * intr_mask_flag) -{ - sw_error_t rv; - - FAL_API_LOCK; - rv = _fal_intr_port_link_status_get(dev_id, port_id, intr_mask_flag); - FAL_API_UNLOCK; - return rv; -} - -/** - * @brief Set mac link change interrupt mask on particular port. - * @param[in] dev_id device id - * @param[in] port_id port id - * @param[in] enable ports intr mask enabled - * @return SW_OK or error code - */ -sw_error_t -fal_intr_mask_mac_linkchg_set(a_uint32_t dev_id, a_uint32_t port_id, a_bool_t enable) -{ - sw_error_t rv; - FAL_API_LOCK; - rv = _fal_intr_mask_mac_linkchg_set(dev_id, port_id, enable); - FAL_API_UNLOCK; - return rv; -} - -/** - * @brief Get mac link change interrupt mask on particular port. - * @param[in] dev_id device id - * @param[in] port_id port id - * @param[out] port interrupt mask or not - * @return SW_OK or error code - */ -sw_error_t -fal_intr_mask_mac_linkchg_get(a_uint32_t dev_id, a_uint32_t port_id, a_bool_t * enable) -{ - sw_error_t rv; - - FAL_API_LOCK; - rv = _fal_intr_mask_mac_linkchg_get(dev_id, port_id, enable); - FAL_API_UNLOCK; - return rv; -} - -/** - * @brief Get link change interrupt status for all ports. - * @param[in] dev_id device id - * @param[in] port_id port id - * @param[out] ports bitmap which generates interrupt - * @return SW_OK or error code - */ -sw_error_t -fal_intr_status_mac_linkchg_get(a_uint32_t dev_id, fal_pbmp_t* port_bitmap) -{ - sw_error_t rv; - - FAL_API_LOCK; - rv = _fal_intr_status_mac_linkchg_get(dev_id, port_bitmap); - FAL_API_UNLOCK; - return rv; -} - -/** - * @brief Set to cpu vid enable status on a particular device. - * @param[in] dev_id device id - * @param[in] enable A_TRUE or A_FALSE - * @return SW_OK or error code - */ -sw_error_t -fal_cpu_vid_en_set(a_uint32_t dev_id, a_bool_t enable) -{ - sw_error_t rv; - - FAL_API_LOCK; - rv = _fal_cpu_vid_en_set(dev_id, enable); - FAL_API_UNLOCK; - return rv; -} - -/** - * @brief Get to cpu vid enable status on a particular device. - * @param[in] dev_id device id - * @param[in] enable A_TRUE or A_FALSE - * @return SW_OK or error code - */ -sw_error_t -fal_cpu_vid_en_get(a_uint32_t dev_id, a_bool_t * enable) -{ - sw_error_t rv; - - FAL_API_LOCK; - rv = _fal_cpu_vid_en_get(dev_id, enable); - FAL_API_UNLOCK; - return rv; -} - -/** - * @brief Get mac link change interrupt mask on particular port. - * @param[in] dev_id device id - * @return SW_OK or error code - */ -sw_error_t -fal_intr_status_mac_linkchg_clear(a_uint32_t dev_id) -{ - sw_error_t rv; - - FAL_API_LOCK; - rv = _fal_intr_status_mac_linkchg_clear(dev_id); - FAL_API_UNLOCK; - return rv; -} - -/** - * @brief Set global macaddr on particular device. - * @param[in] dev_id device id - * @param[in] addr addr - * @return SW_OK or error code - */ -sw_error_t -fal_global_macaddr_set(a_uint32_t dev_id, fal_mac_addr_t * addr) -{ - sw_error_t rv; - - FAL_API_LOCK; - rv = _fal_global_macaddr_set(dev_id, addr); - FAL_API_UNLOCK; - return rv; -} - -/** - * @brief Get global macaddr on particular device. - * @param[in] dev_id device id - * @param[out] addr addr - * @return SW_OK or error code - */ -sw_error_t -fal_global_macaddr_get(a_uint32_t dev_id, fal_mac_addr_t * addr) -{ - sw_error_t rv; - - FAL_API_LOCK; - rv = _fal_global_macaddr_get(dev_id, addr); - FAL_API_UNLOCK; - return rv; -} - -/** - * @brief Set lldp packets hardware acknowledgement status on particular device. - * @details comments: - * Particular device may only support parts of pppoe packets. - * @param[in] dev_id device id - * @param[in] enable A_TRUE or A_FALSE - * @return SW_OK or error code - */ -sw_error_t -fal_lldp_status_set(a_uint32_t dev_id, a_bool_t enable) -{ - sw_error_t rv; - - FAL_API_LOCK; - rv = _fal_lldp_status_set(dev_id, enable); - FAL_API_UNLOCK; - return rv; -} - -/** - * @brief Get lldp packets hardware acknowledgement status on a particular device. - * @param[in] dev_id device id - * @param[out] enable A_TRUE or A_FALSE - * @return SW_OK or error code - */ -sw_error_t -fal_lldp_status_get(a_uint32_t dev_id, a_bool_t * enable) -{ - sw_error_t rv; - - FAL_API_LOCK; - rv = _fal_lldp_status_get(dev_id, enable); - FAL_API_UNLOCK; - return rv; -} - -/** - * @brief Set frame crc reserve enable on particular device. - * @details comments: - * CRC reseve enable. - * @param[in] dev_id device id - * @param[in] enable A_TRUE or A_FALSE - * @return SW_OK or error code - */ -sw_error_t -fal_frame_crc_reserve_set(a_uint32_t dev_id, a_bool_t enable) -{ - sw_error_t rv; - - FAL_API_LOCK; - rv = _fal_frame_crc_reserve_set(dev_id, enable); - FAL_API_UNLOCK; - return rv; -} - -/** - * @brief Get frame crc reserve enable on particular device. - * @details comments: - * CRC reseve enable. - * @param[in] dev_id device id - * @param[in] enable A_TRUE or A_FALSE - * @return SW_OK or error code - */ -sw_error_t -fal_frame_crc_reserve_get(a_uint32_t dev_id, a_bool_t * enable) -{ - sw_error_t rv; - - FAL_API_LOCK; - rv = _fal_frame_crc_reserve_get(dev_id, enable); - FAL_API_UNLOCK; - return rv; -} - -sw_error_t -fal_debug_port_counter_enable(a_uint32_t dev_id, fal_port_t port_id, fal_counter_en_t * cnt_en) -{ - sw_error_t rv = SW_OK; - - FAL_API_LOCK; - rv = _fal_debug_port_counter_enable(dev_id, port_id, cnt_en); - FAL_API_UNLOCK; - return rv; -} - -sw_error_t -fal_debug_port_counter_status_get(a_uint32_t dev_id, fal_port_t port_id, fal_counter_en_t * cnt_en) -{ - sw_error_t rv = SW_OK; - - FAL_API_LOCK; - rv = _fal_debug_port_counter_status_get(dev_id, port_id, cnt_en); - FAL_API_UNLOCK; - return rv; -} -#endif - - - -/** - * @} - */ - diff --git a/feeds/ipq807x/qca-ssdk/src/src/fal/fal_nat.c b/feeds/ipq807x/qca-ssdk/src/src/fal/fal_nat.c deleted file mode 100755 index 6110628b3..000000000 --- a/feeds/ipq807x/qca-ssdk/src/src/fal/fal_nat.c +++ /dev/null @@ -1,1341 +0,0 @@ -/* - * Copyright (c) 2012, 2015, The Linux Foundation. All rights reserved. - * Permission to use, copy, modify, and/or distribute this software for - * any purpose with or without fee is hereby granted, provided that the - * above copyright notice and this permission notice appear in all copies. - * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES - * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR - * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES - * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN - * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT - * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. - */ - - -/** - * @defgroup fal_nat FAL_NAT - * @{ - */ - -#include "sw.h" -#include "fal_nat.h" -#include "hsl_api.h" - -#include -#include - -int nf_athrs17_hnat_sync_counter_en = 0; - -static sw_error_t -_fal_nat_add(a_uint32_t dev_id, fal_nat_entry_t * nat_entry) -{ - sw_error_t rv; - hsl_api_t *p_api; - - SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id)); - - if (NULL == p_api->nat_add) - return SW_NOT_SUPPORTED; - - rv = p_api->nat_add(dev_id, nat_entry); - return rv; -} - -static sw_error_t -_fal_nat_del(a_uint32_t dev_id, a_uint32_t del_mode, - fal_nat_entry_t * nat_entry) -{ - sw_error_t rv; - hsl_api_t *p_api; - - SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id)); - - if (NULL == p_api->nat_del) - return SW_NOT_SUPPORTED; - - rv = p_api->nat_del(dev_id, del_mode, nat_entry); - return rv; -} - -static sw_error_t -_fal_nat_get(a_uint32_t dev_id, a_uint32_t get_mode, - fal_nat_entry_t * nat_entry) -{ - sw_error_t rv; - hsl_api_t *p_api; - - SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id)); - - if (NULL == p_api->nat_get) - return SW_NOT_SUPPORTED; - - rv = p_api->nat_get(dev_id, get_mode, nat_entry); - return rv; -} - -static sw_error_t -_fal_nat_next(a_uint32_t dev_id, a_uint32_t next_mode, - fal_nat_entry_t * nat_entry) -{ - sw_error_t rv; - hsl_api_t *p_api; - - SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id)); - - if (NULL == p_api->nat_next) - return SW_NOT_SUPPORTED; - - rv = p_api->nat_next(dev_id, next_mode, nat_entry); - return rv; -} - -static sw_error_t -_fal_nat_counter_bind(a_uint32_t dev_id, a_uint32_t entry_id, a_uint32_t cnt_id, - a_bool_t enable) -{ - sw_error_t rv; - hsl_api_t *p_api; - - SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id)); - - if (NULL == p_api->nat_counter_bind) - return SW_NOT_SUPPORTED; - - rv = p_api->nat_counter_bind(dev_id, entry_id, cnt_id, enable); - return rv; -} - -static sw_error_t -_fal_napt_add(a_uint32_t dev_id, fal_napt_entry_t * napt_entry) -{ - sw_error_t rv; - hsl_api_t *p_api; - - SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id)); - - if (NULL == p_api->napt_add) - return SW_NOT_SUPPORTED; - - rv = p_api->napt_add(dev_id, napt_entry); - return rv; -} - -static sw_error_t -_fal_napt_del(a_uint32_t dev_id, a_uint32_t del_mode, - fal_napt_entry_t * napt_entry) -{ - sw_error_t rv; - hsl_api_t *p_api; - - SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id)); - - if (NULL == p_api->napt_del) - return SW_NOT_SUPPORTED; - - rv = p_api->napt_del(dev_id, del_mode, napt_entry); - return rv; -} - -static sw_error_t -_fal_napt_get(a_uint32_t dev_id, a_uint32_t get_mode, - fal_napt_entry_t * napt_entry) -{ - sw_error_t rv; - hsl_api_t *p_api; - - SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id)); - - if (NULL == p_api->napt_get) - return SW_NOT_SUPPORTED; - - rv = p_api->napt_get(dev_id, get_mode, napt_entry); - return rv; -} - -static sw_error_t -_fal_napt_next(a_uint32_t dev_id, a_uint32_t next_mode, - fal_napt_entry_t * napt_entry) -{ - sw_error_t rv; - hsl_api_t *p_api; - - SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id)); - - if (NULL == p_api->napt_next) - return SW_NOT_SUPPORTED; - - rv = p_api->napt_next(dev_id, next_mode, napt_entry); - return rv; -} - -static sw_error_t -_fal_napt_counter_bind(a_uint32_t dev_id, a_uint32_t entry_id, - a_uint32_t cnt_id, a_bool_t enable) -{ - sw_error_t rv; - hsl_api_t *p_api; - - SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id)); - - if (NULL == p_api->napt_counter_bind) - return SW_NOT_SUPPORTED; - - rv = p_api->napt_counter_bind(dev_id, entry_id, cnt_id, enable); - return rv; -} - -static sw_error_t -_fal_flow_add(a_uint32_t dev_id, fal_napt_entry_t * napt_entry) -{ - sw_error_t rv; - hsl_api_t *p_api; - - SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id)); - - if (NULL == p_api->flow_add) - return SW_NOT_SUPPORTED; - - rv = p_api->flow_add(dev_id, napt_entry); - return rv; -} - -static sw_error_t - -_fal_flow_cookie_set(a_uint32_t dev_id, fal_flow_cookie_t * flow_cookie) -{ - sw_error_t rv; - hsl_api_t *p_api; - - SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id)); - - if (NULL == p_api->flow_cookie_set) - return SW_NOT_SUPPORTED; - - rv = p_api->flow_cookie_set(dev_id, flow_cookie); - return rv; -} - -static sw_error_t - -_fal_flow_rfs_set(a_uint32_t dev_id, a_uint8_t action, fal_flow_rfs_t * rfs) -{ - sw_error_t rv; - hsl_api_t *p_api; - - SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id)); - - if (NULL == p_api->flow_rfs_set) - return SW_NOT_SUPPORTED; - - rv = p_api->flow_rfs_set(dev_id, action, rfs); - return rv; -} - - - -static sw_error_t -_fal_flow_del(a_uint32_t dev_id, a_uint32_t del_mode, - fal_napt_entry_t * napt_entry) -{ - sw_error_t rv; - hsl_api_t *p_api; - - SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id)); - - if (NULL == p_api->flow_del) - return SW_NOT_SUPPORTED; - - rv = p_api->flow_del(dev_id, del_mode, napt_entry); - return rv; -} - -static sw_error_t -_fal_flow_get(a_uint32_t dev_id, a_uint32_t get_mode, - fal_napt_entry_t * napt_entry) -{ - sw_error_t rv; - hsl_api_t *p_api; - - SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id)); - - if (NULL == p_api->flow_get) - return SW_NOT_SUPPORTED; - - rv = p_api->flow_get(dev_id, get_mode, napt_entry); - return rv; -} - -static sw_error_t -_fal_flow_next(a_uint32_t dev_id, a_uint32_t next_mode, - fal_napt_entry_t * napt_entry) -{ - sw_error_t rv; - hsl_api_t *p_api; - - SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id)); - - if (NULL == p_api->flow_next) - return SW_NOT_SUPPORTED; - - rv = p_api->flow_next(dev_id, next_mode, napt_entry); - return rv; -} - -static sw_error_t -_fal_flow_counter_bind(a_uint32_t dev_id, a_uint32_t entry_id, - a_uint32_t cnt_id, a_bool_t enable) -{ - sw_error_t rv; - hsl_api_t *p_api; - - SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id)); - - if (NULL == p_api->flow_counter_bind) - return SW_NOT_SUPPORTED; - - rv = p_api->flow_counter_bind(dev_id, entry_id, cnt_id, enable); - return rv; -} - -static sw_error_t -_fal_nat_status_set(a_uint32_t dev_id, a_bool_t enable) -{ - sw_error_t rv; - hsl_api_t *p_api; - - SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id)); - - if (NULL == p_api->nat_status_set) - return SW_NOT_SUPPORTED; - - rv = p_api->nat_status_set(dev_id, enable); - return rv; -} - -static sw_error_t -_fal_nat_status_get(a_uint32_t dev_id, a_bool_t * enable) -{ - sw_error_t rv; - hsl_api_t *p_api; - - SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id)); - - if (NULL == p_api->nat_status_get) - return SW_NOT_SUPPORTED; - - rv = p_api->nat_status_get(dev_id, enable); - return rv; -} - -static sw_error_t -_fal_nat_hash_mode_set(a_uint32_t dev_id, a_uint32_t mode) -{ - sw_error_t rv; - hsl_api_t *p_api; - - SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id)); - - if (NULL == p_api->nat_hash_mode_set) - return SW_NOT_SUPPORTED; - - rv = p_api->nat_hash_mode_set(dev_id, mode); - return rv; -} - -static sw_error_t -_fal_nat_hash_mode_get(a_uint32_t dev_id, a_uint32_t * mode) -{ - sw_error_t rv; - hsl_api_t *p_api; - - SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id)); - - if (NULL == p_api->nat_hash_mode_get) - return SW_NOT_SUPPORTED; - - rv = p_api->nat_hash_mode_get(dev_id, mode); - return rv; -} - -static sw_error_t -_fal_napt_status_set(a_uint32_t dev_id, a_bool_t enable) -{ - sw_error_t rv; - hsl_api_t *p_api; - - SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id)); - - if (NULL == p_api->napt_status_set) - return SW_NOT_SUPPORTED; - - rv = p_api->napt_status_set(dev_id, enable); - return rv; -} - -static sw_error_t -_fal_napt_status_get(a_uint32_t dev_id, a_bool_t * enable) -{ - sw_error_t rv; - hsl_api_t *p_api; - - SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id)); - - if (NULL == p_api->napt_status_get) - return SW_NOT_SUPPORTED; - - rv = p_api->napt_status_get(dev_id, enable); - return rv; -} - -static sw_error_t -_fal_napt_mode_set(a_uint32_t dev_id, fal_napt_mode_t mode) -{ - sw_error_t rv; - hsl_api_t *p_api; - - SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id)); - - if (NULL == p_api->napt_mode_set) - return SW_NOT_SUPPORTED; - - rv = p_api->napt_mode_set(dev_id, mode); - return rv; -} - -static sw_error_t -_fal_napt_mode_get(a_uint32_t dev_id, fal_napt_mode_t * mode) -{ - sw_error_t rv; - hsl_api_t *p_api; - - SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id)); - - if (NULL == p_api->napt_mode_get) - return SW_NOT_SUPPORTED; - - rv = p_api->napt_mode_get(dev_id, mode); - return rv; -} - -static sw_error_t -_fal_nat_prv_base_addr_set(a_uint32_t dev_id, fal_ip4_addr_t addr) -{ - sw_error_t rv; - hsl_api_t *p_api; - - SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id)); - - if (NULL == p_api->nat_prv_base_addr_set) - return SW_NOT_SUPPORTED; - - rv = p_api->nat_prv_base_addr_set(dev_id, addr); - return rv; -} - -static sw_error_t -_fal_nat_prv_base_addr_get(a_uint32_t dev_id, fal_ip4_addr_t * addr) -{ - sw_error_t rv; - hsl_api_t *p_api; - - SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id)); - - if (NULL == p_api->nat_prv_base_addr_get) - return SW_NOT_SUPPORTED; - - rv = p_api->nat_prv_base_addr_get(dev_id, addr); - return rv; -} - -static sw_error_t -_fal_nat_prv_base_mask_set(a_uint32_t dev_id, fal_ip4_addr_t addr) -{ - sw_error_t rv; - hsl_api_t *p_api; - - SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id)); - - if (NULL == p_api->nat_prv_base_mask_set) - return SW_NOT_SUPPORTED; - - rv = p_api->nat_prv_base_mask_set(dev_id, addr); - return rv; -} - -static sw_error_t -_fal_nat_prv_base_mask_get(a_uint32_t dev_id, fal_ip4_addr_t * addr) -{ - sw_error_t rv; - hsl_api_t *p_api; - - SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id)); - - if (NULL == p_api->nat_prv_base_mask_get) - return SW_NOT_SUPPORTED; - - rv = p_api->nat_prv_base_mask_get(dev_id, addr); - return rv; -} - -static sw_error_t -_fal_nat_prv_addr_mode_set(a_uint32_t dev_id, a_bool_t map_en) -{ - sw_error_t rv; - hsl_api_t *p_api; - - SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id)); - - if (NULL == p_api->nat_prv_addr_mode_set) - return SW_NOT_SUPPORTED; - - rv = p_api->nat_prv_addr_mode_set(dev_id, map_en); - return rv; -} - -static sw_error_t -_fal_nat_prv_addr_mode_get(a_uint32_t dev_id, a_bool_t * map_en) -{ - sw_error_t rv; - hsl_api_t *p_api; - - SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id)); - - if (NULL == p_api->nat_prv_addr_mode_get) - return SW_NOT_SUPPORTED; - - rv = p_api->nat_prv_addr_mode_get(dev_id, map_en); - return rv; -} - -static sw_error_t -_fal_nat_pub_addr_add(a_uint32_t dev_id, fal_nat_pub_addr_t * entry) -{ - sw_error_t rv; - hsl_api_t *p_api; - - SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id)); - - if (NULL == p_api->nat_pub_addr_add) - return SW_NOT_SUPPORTED; - - rv = p_api->nat_pub_addr_add(dev_id, entry); - return rv; -} - -static sw_error_t -_fal_nat_pub_addr_del(a_uint32_t dev_id, a_uint32_t del_mode, - fal_nat_pub_addr_t * entry) -{ - sw_error_t rv; - hsl_api_t *p_api; - - SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id)); - - if (NULL == p_api->nat_pub_addr_del) - return SW_NOT_SUPPORTED; - - rv = p_api->nat_pub_addr_del(dev_id, del_mode, entry); - return rv; -} - -static sw_error_t -_fal_nat_pub_addr_next(a_uint32_t dev_id, a_uint32_t next_mode, - fal_nat_pub_addr_t * entry) -{ - sw_error_t rv; - hsl_api_t *p_api; - - SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id)); - - if (NULL == p_api->nat_pub_addr_next) - return SW_NOT_SUPPORTED; - - rv = p_api->nat_pub_addr_next(dev_id, next_mode, entry); - return rv; -} - -static sw_error_t -_fal_nat_unk_session_cmd_set(a_uint32_t dev_id, fal_fwd_cmd_t cmd) -{ - sw_error_t rv; - hsl_api_t *p_api; - - SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id)); - - if (NULL == p_api->nat_unk_session_cmd_set) - return SW_NOT_SUPPORTED; - - rv = p_api->nat_unk_session_cmd_set(dev_id, cmd); - return rv; -} - -static sw_error_t -_fal_nat_unk_session_cmd_get(a_uint32_t dev_id, fal_fwd_cmd_t * cmd) -{ - sw_error_t rv; - hsl_api_t *p_api; - - SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id)); - - if (NULL == p_api->nat_unk_session_cmd_get) - return SW_NOT_SUPPORTED; - - rv = p_api->nat_unk_session_cmd_get(dev_id, cmd); - return rv; -} - -static sw_error_t -_fal_nat_global_set(a_uint32_t dev_id, a_bool_t enable, a_uint32_t portbmp) -{ - sw_error_t rv; - hsl_api_t *p_api; - - SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id)); - - if (NULL == p_api->nat_global_set) - return SW_NOT_SUPPORTED; - - rv = p_api->nat_global_set(dev_id, enable, portbmp); - return rv; -} - -/** - * @brief Add one NAT entry to one particular device. - * @details Comments: - Before NAT entry added ip4 private base address must be set - at first. - In parameter nat_entry entry flags must be set - Hardware entry id will be returned. - * @param[in] dev_id device id - * @param[in] nat_entry NAT entry parameter - * @return SW_OK or error code - */ -sw_error_t -fal_nat_add(a_uint32_t dev_id, fal_nat_entry_t * nat_entry) -{ - sw_error_t rv; - - FAL_API_LOCK; - rv = _fal_nat_add(dev_id, nat_entry); - FAL_API_UNLOCK; - return rv; -} - -/** - * @brief Del NAT entries from one particular device. - * @param[in] dev_id device id - * @param[in] del_mode NAT entry delete operation mode - * @param[in] nat_entry NAT entry parameter - * @return SW_OK or error code - */ -sw_error_t -fal_nat_del(a_uint32_t dev_id, a_uint32_t del_mode, - fal_nat_entry_t * nat_entry) -{ - sw_error_t rv; - - FAL_API_LOCK; - rv = _fal_nat_del(dev_id, del_mode, nat_entry); - FAL_API_UNLOCK; - return rv; -} - -/** - * @brief Get one NAT entry from one particular device. - * @param[in] dev_id device id - * @param[in] get_mode NAT entry get operation mode - * @param[in] nat_entry NAT entry parameter - * @param[out] nat_entry NAT entry parameter - * @return SW_OK or error code - */ -sw_error_t -fal_nat_get(a_uint32_t dev_id, a_uint32_t get_mode, - fal_nat_entry_t * nat_entry) -{ - sw_error_t rv; - - FAL_API_LOCK; - rv = _fal_nat_get(dev_id, get_mode, nat_entry); - FAL_API_UNLOCK; - return rv; -} - -/** - * @brief Next NAT entries from one particular device. - * @param[in] dev_id device id - * @param[in] next_mode NAT entry next operation mode - * @param[in] nat_entry NAT entry parameter - * @param[out] nat_entry NAT entry parameter - * @return SW_OK or error code - */ -sw_error_t -fal_nat_next(a_uint32_t dev_id, a_uint32_t next_mode, - fal_nat_entry_t * nat_entry) -{ - sw_error_t rv; - - FAL_API_LOCK; - rv = _fal_nat_next(dev_id, next_mode, nat_entry); - FAL_API_UNLOCK; - return rv; -} - -/** - * @brief Bind one counter entry to one NAT entry to one particular device. - * @param[in] dev_id device id - * @param[in] entry_id NAT entry id - * @param[in] cnt_id counter entry id - * @param[in] enable A_TRUE or A_FALSE - * @return SW_OK or error code - */ -sw_error_t -fal_nat_counter_bind(a_uint32_t dev_id, a_uint32_t entry_id, a_uint32_t cnt_id, - a_bool_t enable) -{ - sw_error_t rv; - - FAL_API_LOCK; - rv = _fal_nat_counter_bind(dev_id, entry_id, cnt_id, enable); - FAL_API_UNLOCK; - return rv; -} - -/** - * @brief Add one NAPT entry to one particular device. - * @details Comments: - Before NAPT entry added related ip4 private base address must be set - at first. - In parameter napt_entry related entry flags must be set - Hardware entry id will be returned. - * @param[in] dev_id device id - * @param[in] napt_entry NAPT entry parameter - * @return SW_OK or error code - */ -sw_error_t -fal_napt_add(a_uint32_t dev_id, fal_napt_entry_t * napt_entry) -{ - sw_error_t rv; - - FAL_API_LOCK; - rv = _fal_napt_add(dev_id, napt_entry); - FAL_API_UNLOCK; - return rv; -} - -/** - * @brief Del NAPT entries from one particular device. - * @param[in] dev_id device id - * @param[in] del_mode NAPT entry delete operation mode - * @param[in] napt_entry NAPT entry parameter - * @return SW_OK or error code - */ -sw_error_t -fal_napt_del(a_uint32_t dev_id, a_uint32_t del_mode, - fal_napt_entry_t * napt_entry) -{ - sw_error_t rv; - - FAL_API_LOCK; - rv = _fal_napt_del(dev_id, del_mode, napt_entry); - FAL_API_UNLOCK; - return rv; -} - -/** - * @brief Get one NAPT entry from one particular device. - * @param[in] dev_id device id - * @param[in] get_mode NAPT entry get operation mode - * @param[in] nat_entry NAPT entry parameter - * @param[out] nat_entry NAPT entry parameter - * @return SW_OK or error code - */ -sw_error_t -fal_napt_get(a_uint32_t dev_id, a_uint32_t get_mode, - fal_napt_entry_t * napt_entry) -{ - sw_error_t rv; - - FAL_API_LOCK; - rv = _fal_napt_get(dev_id, get_mode, napt_entry); - FAL_API_UNLOCK; - return rv; -} - -/** - * @brief Next NAPT entries from one particular device. - * @param[in] dev_id device id - * @param[in] next_mode NAPT entry next operation mode - * @param[in] napt_entry NAPT entry parameter - * @param[out] napt_entry NAPT entry parameter - * @return SW_OK or error code - */ -sw_error_t -fal_napt_next(a_uint32_t dev_id, a_uint32_t next_mode, - fal_napt_entry_t * napt_entry) -{ - sw_error_t rv; - - FAL_API_LOCK; - rv = _fal_napt_next(dev_id, next_mode, napt_entry); - FAL_API_UNLOCK; - return rv; -} - -/** - * @brief Bind one counter entry to one NAPT entry to one particular device. - * @param[in] dev_id device id - * @param[in] entry_id NAPT entry id - * @param[in] cnt_id counter entry id - * @param[in] enable A_TRUE or A_FALSE - * @return SW_OK or error code - */ -sw_error_t -fal_napt_counter_bind(a_uint32_t dev_id, a_uint32_t entry_id, - a_uint32_t cnt_id, a_bool_t enable) -{ - sw_error_t rv; - - FAL_API_LOCK; - rv = _fal_napt_counter_bind(dev_id, entry_id, cnt_id, enable); - FAL_API_UNLOCK; - return rv; -} - -/** - * @brief Add one FLOW entry to one particular device. - * @details Comments: - Before FLOW entry added related ip4 private base address must be set - at first. - In parameter napt_entry related entry flags must be set - Hardware entry id will be returned. - * @param[in] dev_id device id - * @param[in] napt_entry FLOW entry parameter - * @return SW_OK or error code - */ -sw_error_t -fal_flow_add(a_uint32_t dev_id, fal_napt_entry_t * napt_entry) -{ - sw_error_t rv; - - FAL_API_LOCK; - rv = _fal_flow_add(dev_id, napt_entry); - FAL_API_UNLOCK; - return rv; -} - -/** - * @brief Del FLOW entries from one particular device. - * @param[in] dev_id device id - * @param[in] del_mode NAPT entry delete operation mode - * @param[in] napt_entry NAPT entry parameter - * @return SW_OK or error code - */ -sw_error_t -fal_flow_del(a_uint32_t dev_id, a_uint32_t del_mode, - fal_napt_entry_t * napt_entry) -{ - sw_error_t rv; - - FAL_API_LOCK; - rv = _fal_flow_del(dev_id, del_mode, napt_entry); - FAL_API_UNLOCK; - return rv; -} - -/** - * @brief Get one FLOW entry from one particular device. - * @param[in] dev_id device id - * @param[in] get_mode FLOW entry get operation mode - * @param[in] nat_entry FLOW entry parameter - * @param[out] nat_entry FLOW entry parameter - * @return SW_OK or error code - */ -sw_error_t -fal_flow_get(a_uint32_t dev_id, a_uint32_t get_mode, - fal_napt_entry_t * napt_entry) -{ - sw_error_t rv; - - FAL_API_LOCK; - rv = _fal_flow_get(dev_id, get_mode, napt_entry); - FAL_API_UNLOCK; - return rv; -} - -/** - * @brief Next FLOW entries from one particular device. - * @param[in] dev_id device id - * @param[in] next_mode FLOW entry next operation mode - * @param[in] napt_entry FLOW entry parameter - * @param[out] napt_entry FLOW entry parameter - * @return SW_OK or error code - */ -sw_error_t -fal_flow_next(a_uint32_t dev_id, a_uint32_t next_mode, - fal_napt_entry_t * napt_entry) -{ - sw_error_t rv; - - FAL_API_LOCK; - rv = _fal_flow_next(dev_id, next_mode, napt_entry); - FAL_API_UNLOCK; - return rv; -} - -/** - * @brief Bind one counter entry to one FLOW entry to one particular device. - * @param[in] dev_id device id - * @param[in] entry_id FLOW entry id - * @param[in] cnt_id counter entry id - * @param[in] enable A_TRUE or A_FALSE - * @return SW_OK or error code - */ -sw_error_t -fal_flow_counter_bind(a_uint32_t dev_id, a_uint32_t entry_id, - a_uint32_t cnt_id, a_bool_t enable) -{ - sw_error_t rv; - - FAL_API_LOCK; - rv = _fal_flow_counter_bind(dev_id, entry_id, cnt_id, enable); - FAL_API_UNLOCK; - return rv; -} - -/** - * @brief Set working status of NAT engine on a particular device - * @param[in] dev_id device id - * @param[in] enable A_TRUE or A_FALSE - * @return SW_OK or error code - */ -sw_error_t -fal_nat_status_set(a_uint32_t dev_id, a_bool_t enable) -{ - sw_error_t rv; - - FAL_API_LOCK; - rv = _fal_nat_status_set(dev_id, enable); - FAL_API_UNLOCK; - return rv; -} - -/** - * @brief Get working status of NAT engine on a particular device - * @param[in] dev_id device id - * @param[out] enable A_TRUE or A_FALSE - * @return SW_OK or error code - */ -sw_error_t -fal_nat_status_get(a_uint32_t dev_id, a_bool_t * enable) -{ - sw_error_t rv; - - FAL_API_LOCK; - rv = _fal_nat_status_get(dev_id, enable); - FAL_API_UNLOCK; - return rv; -} - -/** - * @brief Set NAT hash mode on a particular device - * @param[in] dev_id device id - * @param[in] mode NAT hash mode - * @return SW_OK or error code - */ -sw_error_t -fal_nat_hash_mode_set(a_uint32_t dev_id, a_uint32_t mode) -{ - sw_error_t rv; - - FAL_API_LOCK; - rv = _fal_nat_hash_mode_set(dev_id, mode); - FAL_API_UNLOCK; - return rv; -} - -/** - * @brief Get NAT hash mode on a particular device - * @param[in] dev_id device id - * @param[out] mode NAT hash mode - * @return SW_OK or error code - */ -sw_error_t -fal_nat_hash_mode_get(a_uint32_t dev_id, a_uint32_t * mode) -{ - sw_error_t rv; - - FAL_API_LOCK; - rv = _fal_nat_hash_mode_get(dev_id, mode); - FAL_API_UNLOCK; - return rv; -} - -/** - * @brief Set working status of NAPT engine on a particular device - * @param[in] dev_id device id - * @param[in] enable A_TRUE or A_FALSE - * @return SW_OK or error code - */ -sw_error_t -fal_napt_status_set(a_uint32_t dev_id, a_bool_t enable) -{ - sw_error_t rv; - - FAL_API_LOCK; - rv = _fal_napt_status_set(dev_id, enable); - FAL_API_UNLOCK; - return rv; -} - -/** - * @brief Get working status of NAPT engine on a particular device - * @param[in] dev_id device id - * @param[out] enable A_TRUE or A_FALSE - * @return SW_OK or error code - */ -sw_error_t -fal_napt_status_get(a_uint32_t dev_id, a_bool_t * enable) -{ - sw_error_t rv; - - FAL_API_LOCK; - rv = _fal_napt_status_get(dev_id, enable); - FAL_API_UNLOCK; - return rv; -} - -/** - * @brief Set working mode of NAPT engine on a particular device - * @param[in] dev_id device id - * @param[in] mode NAPT mode - * @return SW_OK or error code - */ -sw_error_t -fal_napt_mode_set(a_uint32_t dev_id, fal_napt_mode_t mode) -{ - sw_error_t rv; - - FAL_API_LOCK; - rv = _fal_napt_mode_set(dev_id, mode); - FAL_API_UNLOCK; - return rv; -} - -/** - * @brief Get working mode of NAPT engine on a particular device - * @param[in] dev_id device id - * @param[out] mode NAPT mode - * @return SW_OK or error code - */ -sw_error_t -fal_napt_mode_get(a_uint32_t dev_id, fal_napt_mode_t * mode) -{ - sw_error_t rv; - - FAL_API_LOCK; - rv = _fal_napt_mode_get(dev_id, mode); - FAL_API_UNLOCK; - return rv; -} - -/** - * @brief Set IP4 private base address on a particular device - * @details Comments: - Only 20bits is meaning which 20bits is determined by private address mode. - * @param[in] dev_id device id - * @param[in] addr private base address - * @return SW_OK or error code - */ -sw_error_t -fal_nat_prv_base_addr_set(a_uint32_t dev_id, fal_ip4_addr_t addr) -{ - sw_error_t rv; - - FAL_API_LOCK; - rv = _fal_nat_prv_base_addr_set(dev_id, addr); - FAL_API_UNLOCK; - return rv; -} - -/** - * @brief Get IP4 private base address on a particular device - * @param[in] dev_id device id - * @param[out] addr private base address - * @return SW_OK or error code - */ -sw_error_t -fal_nat_prv_base_addr_get(a_uint32_t dev_id, fal_ip4_addr_t * addr) -{ - sw_error_t rv; - - FAL_API_LOCK; - rv = _fal_nat_prv_base_addr_get(dev_id, addr); - FAL_API_UNLOCK; - return rv; -} - -sw_error_t -fal_nat_prv_base_mask_set(a_uint32_t dev_id, fal_ip4_addr_t addr) -{ - sw_error_t rv; - - FAL_API_LOCK; - rv = _fal_nat_prv_base_mask_set(dev_id, addr); - FAL_API_UNLOCK; - return rv; -} - -sw_error_t -fal_nat_prv_base_mask_get(a_uint32_t dev_id, fal_ip4_addr_t * addr) -{ - sw_error_t rv; - - FAL_API_LOCK; - rv = _fal_nat_prv_base_mask_get(dev_id, addr); - FAL_API_UNLOCK; - return rv; -} - -/** - * @brief Set IP4 private base address mode on a particular device - * @details Comments: - If map_en equal true means bits31-20 bits15-8 are base address - else bits31-12 are base address. - * @param[in] dev_id device id - * @param[in] map_en private base mapping mode - * @return SW_OK or error code - */ -sw_error_t -fal_nat_prv_addr_mode_set(a_uint32_t dev_id, a_bool_t map_en) -{ - sw_error_t rv; - - FAL_API_LOCK; - rv = _fal_nat_prv_addr_mode_set(dev_id, map_en); - FAL_API_UNLOCK; - return rv; -} - -/** - * @brief Get IP4 private base address mode on a particular device - * @param[in] dev_id device id - * @param[out] map_en private base mapping mode - * @return SW_OK or error code - */ -sw_error_t -fal_nat_prv_addr_mode_get(a_uint32_t dev_id, a_bool_t * map_en) -{ - sw_error_t rv; - - FAL_API_LOCK; - rv = _fal_nat_prv_addr_mode_get(dev_id, map_en); - FAL_API_UNLOCK; - return rv; -} - -/** - * @brief Add one public address entry to one particular device. - * @details Comments: - Hardware entry id will be returned. - * @param[in] dev_id device id - * @param[in] entry public address entry parameter - * @return SW_OK or error code - */ -sw_error_t -fal_nat_pub_addr_add(a_uint32_t dev_id, fal_nat_pub_addr_t * entry) -{ - sw_error_t rv; - - FAL_API_LOCK; - rv = _fal_nat_pub_addr_add(dev_id, entry); - FAL_API_UNLOCK; - return rv; -} - -/** - * @brief Delete one public address entry from one particular device. - * @param[in] dev_id device id - * @param[in] del_mode delete operaton mode - * @param[in] entry public address entry parameter - * @return SW_OK or error code - */ -sw_error_t -fal_nat_pub_addr_del(a_uint32_t dev_id, a_uint32_t del_mode, - fal_nat_pub_addr_t * entry) -{ - sw_error_t rv; - - FAL_API_LOCK; - rv = _fal_nat_pub_addr_del(dev_id, del_mode, entry); - FAL_API_UNLOCK; - return rv; -} - -/** - * @brief Next public address entries from one particular device. - * @param[in] dev_id device id - * @param[in] next_mode next operaton mode - * @param[out] entry public address entry parameter - * @return SW_OK or error code - */ -sw_error_t -fal_nat_pub_addr_next(a_uint32_t dev_id, a_uint32_t next_mode, - fal_nat_pub_addr_t * entry) -{ - sw_error_t rv; - - FAL_API_LOCK; - rv = _fal_nat_pub_addr_next(dev_id, next_mode, entry); - FAL_API_UNLOCK; - return rv; -} - -/** - * @brief Set forwarding command for those packets miss NAT entries on a particular device. - * @param[in] dev_id device id - * @param[in] cmd forwarding command - * @return SW_OK or error code - */ -sw_error_t -fal_nat_unk_session_cmd_set(a_uint32_t dev_id, fal_fwd_cmd_t cmd) -{ - sw_error_t rv; - - FAL_API_LOCK; - rv = _fal_nat_unk_session_cmd_set(dev_id, cmd); - FAL_API_UNLOCK; - return rv; -} - -/** - * @brief Get forwarding command for those packets miss NAT entries on a particular device. - * @param[in] dev_id device id - * @param[out] cmd forwarding command - * @return SW_OK or error code - */ -sw_error_t -fal_nat_unk_session_cmd_get(a_uint32_t dev_id, fal_fwd_cmd_t * cmd) -{ - sw_error_t rv; - - FAL_API_LOCK; - rv = _fal_nat_unk_session_cmd_get(dev_id, cmd); - FAL_API_UNLOCK; - return rv; -} - -/** - * @brief Set working status of NAPT engine on a particular device - * @param[in] dev_id device id - * @param[in] enable A_TRUE or A_FALSE - * @param[in] sync_cnt_enable A_TRUE or A_FALSE - * @param[in] portbmp port bitmap - * @return SW_OK or error code - */ -sw_error_t -fal_nat_global_set(a_uint32_t dev_id, a_bool_t enable, - a_bool_t sync_cnt_enable, a_uint32_t portbmp) -{ - sw_error_t rv; - - FAL_API_LOCK; - nf_athrs17_hnat_sync_counter_en = (int)sync_cnt_enable; - rv = _fal_nat_global_set(dev_id, enable, portbmp); - FAL_API_UNLOCK; - return rv; -} - -/** - * @brief Add/del one FLOW cookie entry to one particular device. - * @details Comments: - Before FLOW entry added related ip4 private base address must be set - at first. - In parameter napt_entry related entry flags must be set - Hardware entry id will be returned. - * @param[in] dev_id device id - * @param[in] napt_entry FLOW entry parameter - * @return SW_OK or error code - */ -sw_error_t -fal_flow_cookie_set(a_uint32_t dev_id, fal_flow_cookie_t * flow_cookie) -{ - sw_error_t rv; - - FAL_API_LOCK; - rv = _fal_flow_cookie_set(dev_id, flow_cookie); - FAL_API_UNLOCK; - return rv; -} - -/** - * @brief Add/del one FLOW rfs entry to one particular device. - * @details Comments: - Before FLOW entry added related ip4 private base address must be set - at first. - In parameter napt_entry related entry flags must be set - Hardware entry id will be returned. - * @param[in] dev_id device id - * @param[in] napt_entry FLOW entry parameter - * @return SW_OK or error code - */ -sw_error_t -fal_flow_rfs_set(a_uint32_t dev_id, a_uint8_t action, fal_flow_rfs_t * rfs) -{ - sw_error_t rv; - - FAL_API_LOCK; - rv = _fal_flow_rfs_set(dev_id, action, rfs); - FAL_API_UNLOCK; - return rv; -} - - -int ssdk_flow_cookie_set( - u32 protocol, __be32 src_ip, - __be16 src_port, __be32 dst_ip, - __be16 dst_port, u16 flowcookie) -{ - fal_flow_cookie_t flow_cookie; - if(protocol == 17) { - flow_cookie.proto = 0x2; - } else { - flow_cookie.proto = 0x1; - } - flow_cookie.src_addr = ntohl(src_ip); - flow_cookie.dst_addr = ntohl(dst_ip); - flow_cookie.src_port = ntohs(src_port); - flow_cookie.dst_port = ntohs(dst_port); - flow_cookie.flow_cookie = flowcookie; - return fal_flow_cookie_set(0, &flow_cookie); -} - -int ssdk_rfs_ipct_rule_set( - __be32 ip_src, __be32 ip_dst, - __be16 sport, __be16 dport, uint8_t proto, - u16 loadbalance, bool action) -{ - fal_flow_rfs_t rfs; - if(proto == 17) { - rfs.proto = 0x2; - } else { - rfs.proto = 0x1; - } - rfs.src_addr = ntohl(ip_src); - rfs.dst_addr = ntohl(ip_dst); - rfs.src_port = ntohs(sport); - rfs.dst_port = ntohs(dport); - rfs.load_balance = loadbalance; - if(fal_flow_rfs_set(0, action, &rfs)) - return -1; - return 0; -} - -#if 0 -EXPORT_SYMBOL(ssdk_flow_cookie_set); -EXPORT_SYMBOL(ssdk_rfs_ipct_rule_set); -#endif - -/** - * @} - */ diff --git a/feeds/ipq807x/qca-ssdk/src/src/fal/fal_policer.c b/feeds/ipq807x/qca-ssdk/src/src/fal/fal_policer.c deleted file mode 100755 index 6e9e68fb6..000000000 --- a/feeds/ipq807x/qca-ssdk/src/src/fal/fal_policer.c +++ /dev/null @@ -1,402 +0,0 @@ -/* - * Copyright (c) 2016-2017, 2021, The Linux Foundation. All rights reserved. - * Permission to use, copy, modify, and/or distribute this software for - * any purpose with or without fee is hereby granted, provided that the - * above copyright notice and this permission notice appear in all copies. - * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES - * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR - * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES - * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN - * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT - * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. - */ - - -/** - * @defgroup fal_policer FAL_POLICER - * @{ - */ -#include "sw.h" -#include "fal_policer.h" -#include "hsl_api.h" -#include "adpt.h" - -#include -#include - - -#ifndef IN_POLICER_MINI -sw_error_t -_fal_acl_policer_counter_get(a_uint32_t dev_id, a_uint32_t index, - fal_policer_counter_t *counter) -{ - adpt_api_t *p_api; - sw_error_t rv = SW_OK; - - SW_RTN_ON_NULL(p_api = adpt_api_ptr_get(dev_id)); - - if (NULL == p_api->adpt_acl_policer_counter_get) - return SW_NOT_SUPPORTED; - - rv = p_api->adpt_acl_policer_counter_get(dev_id, index, counter); - return rv; -} -sw_error_t -_fal_port_policer_counter_get(a_uint32_t dev_id, fal_port_t port_id, - fal_policer_counter_t *counter) -{ - adpt_api_t *p_api; - sw_error_t rv = SW_OK; - - SW_RTN_ON_NULL(p_api = adpt_api_ptr_get(dev_id)); - - if (NULL == p_api->adpt_port_policer_counter_get) - return SW_NOT_SUPPORTED; - - rv = p_api->adpt_port_policer_counter_get(dev_id, port_id, counter); - return rv; -} -sw_error_t -_fal_port_policer_entry_get(a_uint32_t dev_id, fal_port_t port_id, - fal_policer_config_t *policer, fal_policer_action_t *action) -{ - adpt_api_t *p_api; - sw_error_t rv = SW_OK; - - SW_RTN_ON_NULL(p_api = adpt_api_ptr_get(dev_id)); - - if (NULL == p_api->adpt_port_policer_entry_get) - return SW_NOT_SUPPORTED; - - rv = p_api->adpt_port_policer_entry_get(dev_id, port_id, policer, action); - return rv; -} -sw_error_t -_fal_port_policer_entry_set(a_uint32_t dev_id, fal_port_t port_id, - fal_policer_config_t *policer, fal_policer_action_t *action) -{ - adpt_api_t *p_api; - sw_error_t rv = SW_OK; - - SW_RTN_ON_NULL(p_api = adpt_api_ptr_get(dev_id)); - - if (NULL == p_api->adpt_port_policer_entry_set) - return SW_NOT_SUPPORTED; - - rv = p_api->adpt_port_policer_entry_set(dev_id, port_id, policer, action); - return rv; -} -sw_error_t -_fal_acl_policer_entry_get(a_uint32_t dev_id, a_uint32_t index, - fal_policer_config_t *policer, fal_policer_action_t *action) -{ - adpt_api_t *p_api; - sw_error_t rv = SW_OK; - - SW_RTN_ON_NULL(p_api = adpt_api_ptr_get(dev_id)); - - if (NULL == p_api->adpt_acl_policer_entry_get) - return SW_NOT_SUPPORTED; - - rv = p_api->adpt_acl_policer_entry_get(dev_id, index, policer, action); - return rv; -} -sw_error_t -_fal_acl_policer_entry_set(a_uint32_t dev_id, a_uint32_t index, - fal_policer_config_t *policer, fal_policer_action_t *action) -{ - adpt_api_t *p_api; - sw_error_t rv = SW_OK; - - SW_RTN_ON_NULL(p_api = adpt_api_ptr_get(dev_id)); - - if (NULL == p_api->adpt_acl_policer_entry_set) - return SW_NOT_SUPPORTED; - - rv = p_api->adpt_acl_policer_entry_set(dev_id, index, policer, action); - return rv; -} -sw_error_t -_fal_policer_timeslot_get(a_uint32_t dev_id, a_uint32_t *timeslot) -{ - adpt_api_t *p_api; - sw_error_t rv = SW_OK; - - SW_RTN_ON_NULL(p_api = adpt_api_ptr_get(dev_id)); - - if (NULL == p_api->adpt_policer_time_slot_get) - return SW_NOT_SUPPORTED; - - rv = p_api->adpt_policer_time_slot_get(dev_id, timeslot); - return rv; -} - -sw_error_t -_fal_policer_bypass_en_get(a_uint32_t dev_id, fal_policer_frame_type_t frame_type, - a_bool_t *enable) -{ - adpt_api_t *p_api; - sw_error_t rv = SW_OK; - - SW_RTN_ON_NULL(p_api = adpt_api_ptr_get(dev_id)); - - if (NULL == p_api->adpt_policer_bypass_en_get) - return SW_NOT_SUPPORTED; - - rv = p_api->adpt_policer_bypass_en_get(dev_id, frame_type, enable); - return rv; -} - -#endif -sw_error_t -_fal_policer_timeslot_set(a_uint32_t dev_id, a_uint32_t timeslot) -{ - adpt_api_t *p_api; - sw_error_t rv = SW_OK; - - SW_RTN_ON_NULL(p_api = adpt_api_ptr_get(dev_id)); - - if (NULL == p_api->adpt_policer_time_slot_set) - return SW_NOT_SUPPORTED; - - rv = p_api->adpt_policer_time_slot_set(dev_id, timeslot); - return rv; -} - -sw_error_t -_fal_policer_bypass_en_set(a_uint32_t dev_id, fal_policer_frame_type_t frame_type, - a_bool_t enable) -{ - adpt_api_t *p_api; - sw_error_t rv = SW_OK; - - SW_RTN_ON_NULL(p_api = adpt_api_ptr_get(dev_id)); - - if (NULL == p_api->adpt_policer_bypass_en_set) - return SW_NOT_SUPPORTED; - - rv = p_api->adpt_policer_bypass_en_set(dev_id, frame_type, enable); - return rv; -} - -#ifndef IN_POLICER_MINI -sw_error_t -_fal_port_policer_compensation_byte_get(a_uint32_t dev_id, a_uint32_t port_id, - a_uint32_t *length) -{ - adpt_api_t *p_api; - sw_error_t rv = SW_OK; - - SW_RTN_ON_NULL(p_api = adpt_api_ptr_get(dev_id)); - - if (NULL == p_api->adpt_port_compensation_byte_get) - return SW_NOT_SUPPORTED; - - rv = p_api->adpt_port_compensation_byte_get(dev_id, port_id, length); - return rv; -} -#endif -sw_error_t -_fal_port_policer_compensation_byte_set(a_uint32_t dev_id, a_uint32_t port_id, - a_uint32_t length) - -{ - adpt_api_t *p_api; - sw_error_t rv = SW_OK; - - SW_RTN_ON_NULL(p_api = adpt_api_ptr_get(dev_id)); - - if (NULL == p_api->adpt_port_compensation_byte_set) - return SW_NOT_SUPPORTED; - - rv = p_api->adpt_port_compensation_byte_set(dev_id, port_id, length); - return rv; -} - -#ifndef IN_POLICER_MINI -sw_error_t -_fal_policer_global_counter_get(a_uint32_t dev_id, - fal_policer_global_counter_t *counter) -{ - adpt_api_t *p_api; - sw_error_t rv = SW_OK; - - SW_RTN_ON_NULL(p_api = adpt_api_ptr_get(dev_id)); - - if (NULL == p_api->adpt_policer_global_counter_get) - return SW_NOT_SUPPORTED; - - rv = p_api->adpt_policer_global_counter_get(dev_id, counter); - return rv; -} - -/*insert flag for inner fal, don't remove it*/ - -sw_error_t -fal_acl_policer_counter_get(a_uint32_t dev_id, a_uint32_t index, - fal_policer_counter_t *counter) -{ - sw_error_t rv = SW_OK; - - FAL_API_LOCK; - rv = _fal_acl_policer_counter_get(dev_id, index, counter); - FAL_API_UNLOCK; - return rv; -} -sw_error_t -fal_port_policer_counter_get(a_uint32_t dev_id, fal_port_t port_id, - fal_policer_counter_t *counter) -{ - sw_error_t rv = SW_OK; - - FAL_API_LOCK; - rv = _fal_port_policer_counter_get(dev_id, port_id, counter); - FAL_API_UNLOCK; - return rv; -} -sw_error_t -fal_port_policer_entry_get(a_uint32_t dev_id, fal_port_t port_id, - fal_policer_config_t *policer, fal_policer_action_t *action) -{ - sw_error_t rv = SW_OK; - - FAL_API_LOCK; - rv = _fal_port_policer_entry_get(dev_id, port_id, policer, action); - FAL_API_UNLOCK; - return rv; -} -sw_error_t -fal_port_policer_entry_set(a_uint32_t dev_id, fal_port_t port_id, - fal_policer_config_t *policer, fal_policer_action_t *action) -{ - sw_error_t rv = SW_OK; - - FAL_API_LOCK; - rv = _fal_port_policer_entry_set(dev_id, port_id, policer, action); - FAL_API_UNLOCK; - return rv; -} -sw_error_t -fal_acl_policer_entry_get(a_uint32_t dev_id, a_uint32_t index, - fal_policer_config_t *policer, fal_policer_action_t *action) -{ - sw_error_t rv = SW_OK; - - FAL_API_LOCK; - rv = _fal_acl_policer_entry_get(dev_id, index, policer, action); - FAL_API_UNLOCK; - return rv; -} -sw_error_t -fal_acl_policer_entry_set(a_uint32_t dev_id, a_uint32_t index, - fal_policer_config_t *policer, fal_policer_action_t *action) -{ - sw_error_t rv = SW_OK; - - FAL_API_LOCK; - rv = _fal_acl_policer_entry_set(dev_id, index, policer, action); - FAL_API_UNLOCK; - return rv; -} -sw_error_t -fal_policer_timeslot_get(a_uint32_t dev_id, a_uint32_t *timeslot) -{ - sw_error_t rv = SW_OK; - - FAL_API_LOCK; - rv = _fal_policer_timeslot_get(dev_id, timeslot); - FAL_API_UNLOCK; - return rv; -} - -sw_error_t -fal_policer_bypass_en_get(a_uint32_t dev_id, fal_policer_frame_type_t frame_type, - a_bool_t *enable) -{ - sw_error_t rv = SW_OK; - - FAL_API_LOCK; - rv = _fal_policer_bypass_en_get(dev_id, frame_type, enable); - FAL_API_UNLOCK; - return rv; -} -#endif -sw_error_t -fal_policer_timeslot_set(a_uint32_t dev_id, a_uint32_t timeslot) -{ - sw_error_t rv = SW_OK; - - FAL_API_LOCK; - rv = _fal_policer_timeslot_set(dev_id, timeslot); - FAL_API_UNLOCK; - return rv; -} - -sw_error_t -fal_policer_bypass_en_set(a_uint32_t dev_id, fal_policer_frame_type_t frame_type, - a_bool_t enable) -{ - sw_error_t rv = SW_OK; - - FAL_API_LOCK; - rv = _fal_policer_bypass_en_set(dev_id, frame_type, enable); - FAL_API_UNLOCK; - return rv; -} - -#ifndef IN_POLICER_MINI -sw_error_t -fal_port_policer_compensation_byte_get(a_uint32_t dev_id, fal_port_t port_id, - a_uint32_t *length) -{ - sw_error_t rv = SW_OK; - - FAL_API_LOCK; - rv = _fal_port_policer_compensation_byte_get(dev_id, port_id, length); - FAL_API_UNLOCK; - return rv; -} -#endif -sw_error_t -fal_port_policer_compensation_byte_set(a_uint32_t dev_id, fal_port_t port_id, - a_uint32_t length) -{ - sw_error_t rv = SW_OK; - - FAL_API_LOCK; - rv = _fal_port_policer_compensation_byte_set(dev_id, port_id, length); - FAL_API_UNLOCK; - return rv; -} -#ifndef IN_POLICER_MINI -sw_error_t -fal_policer_global_counter_get(a_uint32_t dev_id, - fal_policer_global_counter_t *counter) -{ - sw_error_t rv = SW_OK; - - FAL_API_LOCK; - rv = _fal_policer_global_counter_get(dev_id, counter); - FAL_API_UNLOCK; - return rv; -} -#endif - -#ifndef IN_POLICER_MINI -EXPORT_SYMBOL(fal_acl_policer_counter_get); -EXPORT_SYMBOL(fal_port_policer_counter_get); -EXPORT_SYMBOL(fal_port_policer_entry_get); -EXPORT_SYMBOL(fal_port_policer_entry_set); -EXPORT_SYMBOL(fal_acl_policer_entry_get); -EXPORT_SYMBOL(fal_acl_policer_entry_set); -EXPORT_SYMBOL(fal_policer_timeslot_get); -EXPORT_SYMBOL(fal_port_policer_compensation_byte_get); -EXPORT_SYMBOL(fal_policer_global_counter_get); -EXPORT_SYMBOL(fal_policer_bypass_en_get); -#endif -EXPORT_SYMBOL(fal_policer_timeslot_set); -EXPORT_SYMBOL(fal_port_policer_compensation_byte_set); -EXPORT_SYMBOL(fal_policer_bypass_en_set); - -/*insert flag for outter fal, don't remove it*/ diff --git a/feeds/ipq807x/qca-ssdk/src/src/fal/fal_port_ctrl.c b/feeds/ipq807x/qca-ssdk/src/src/fal/fal_port_ctrl.c deleted file mode 100644 index 8f3d92a66..000000000 --- a/feeds/ipq807x/qca-ssdk/src/src/fal/fal_port_ctrl.c +++ /dev/null @@ -1,3728 +0,0 @@ -/* - * Copyright (c) 2012, 2015-2019, The Linux Foundation. All rights reserved. - * Permission to use, copy, modify, and/or distribute this software for - * any purpose with or without fee is hereby granted, provided that the - * above copyright notice and this permission notice appear in all copies. - * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES - * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR - * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES - * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN - * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT - * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. - */ - -/*qca808x_start*/ -/** - * @defgroup fal_port_ctrl FAL_PORT_CONTROL - * @{ - */ -#include "sw.h" -#include "fal_port_ctrl.h" -#include "hsl_api.h" -/*qca808x_end*/ -#include "adpt.h" - -#include -#include -/*qca808x_start*/ -static sw_error_t -_fal_port_duplex_set (a_uint32_t dev_id, fal_port_t port_id, - fal_port_duplex_t duplex) -{ - sw_error_t rv; - hsl_api_t *p_api; -/*qca808x_end*/ - adpt_api_t *p_adpt_api; - - if((p_adpt_api = adpt_api_ptr_get(dev_id)) != NULL && - p_adpt_api->adpt_port_duplex_set != NULL) { - rv = p_adpt_api->adpt_port_duplex_set(dev_id, port_id, duplex); - return rv; - } -/*qca808x_start*/ - SW_RTN_ON_NULL (p_api = hsl_api_ptr_get (dev_id)); - - if (NULL == p_api->port_duplex_set) - return SW_NOT_SUPPORTED; - - rv = p_api->port_duplex_set (dev_id, port_id, duplex); - return rv; -} - -static sw_error_t -_fal_port_speed_set (a_uint32_t dev_id, fal_port_t port_id, - fal_port_speed_t speed) -{ - sw_error_t rv; - hsl_api_t *p_api; -/*qca808x_end*/ - adpt_api_t *p_adpt_api; - - if((p_adpt_api = adpt_api_ptr_get(dev_id)) != NULL && - p_adpt_api->adpt_port_speed_set != NULL) { - rv = p_adpt_api->adpt_port_speed_set(dev_id, port_id, speed); - return rv; - } -/*qca808x_start*/ - SW_RTN_ON_NULL (p_api = hsl_api_ptr_get (dev_id)); - - if (NULL == p_api->port_speed_set) - return SW_NOT_SUPPORTED; - - rv = p_api->port_speed_set (dev_id, port_id, speed); - return rv; -} -/*qca808x_end*/ -static sw_error_t -_fal_port_flowctrl_set (a_uint32_t dev_id, fal_port_t port_id, - a_bool_t enable) -{ - sw_error_t rv; - hsl_api_t *p_api; - adpt_api_t *p_adpt_api; - - if((p_adpt_api = adpt_api_ptr_get(dev_id)) != NULL) { - if (NULL == p_adpt_api->adpt_port_flowctrl_set) - return SW_NOT_SUPPORTED; - - rv = p_adpt_api->adpt_port_flowctrl_set(dev_id, port_id, enable); - return rv; - } - - SW_RTN_ON_NULL (p_api = hsl_api_ptr_get (dev_id)); - - if (NULL == p_api->port_flowctrl_set) - return SW_NOT_SUPPORTED; - - rv = p_api->port_flowctrl_set (dev_id, port_id, enable); - return rv; -} - -static sw_error_t -_fal_port_flowctrl_forcemode_set (a_uint32_t dev_id, fal_port_t port_id, - a_bool_t enable) -{ - sw_error_t rv; - hsl_api_t *p_api; - adpt_api_t *p_adpt_api; - - if((p_adpt_api = adpt_api_ptr_get(dev_id)) != NULL) { - if (NULL == p_adpt_api->adpt_port_flowctrl_forcemode_set) - return SW_NOT_SUPPORTED; - - rv = p_adpt_api->adpt_port_flowctrl_forcemode_set(dev_id, port_id, enable); - return rv; - } - - SW_RTN_ON_NULL (p_api = hsl_api_ptr_get (dev_id)); - - if (NULL == p_api->port_flowctrl_forcemode_set) - return SW_NOT_SUPPORTED; - - rv = p_api->port_flowctrl_forcemode_set (dev_id, port_id, enable); - return rv; -} -/*qca808x_start*/ -static sw_error_t -_fal_port_speed_get (a_uint32_t dev_id, fal_port_t port_id, - fal_port_speed_t * pspeed) -{ - sw_error_t rv; - hsl_api_t *p_api; -/*qca808x_end*/ - adpt_api_t *p_adpt_api; - - if((p_adpt_api = adpt_api_ptr_get(dev_id)) != NULL && - p_adpt_api->adpt_port_speed_get != NULL) { - rv = p_adpt_api->adpt_port_speed_get(dev_id, port_id, pspeed); - return rv; - } -/*qca808x_start*/ - SW_RTN_ON_NULL (p_api = hsl_api_ptr_get (dev_id)); - - if (NULL == p_api->port_speed_get) - return SW_NOT_SUPPORTED; - - rv = p_api->port_speed_get (dev_id, port_id, pspeed); - return rv; -} - -static sw_error_t -_fal_port_duplex_get (a_uint32_t dev_id, fal_port_t port_id, - fal_port_duplex_t * pduplex) -{ - sw_error_t rv; - hsl_api_t *p_api; -/*qca808x_end*/ - adpt_api_t *p_adpt_api; - - if((p_adpt_api = adpt_api_ptr_get(dev_id)) != NULL && - p_adpt_api->adpt_port_duplex_get != NULL) { - rv = p_adpt_api->adpt_port_duplex_get(dev_id, port_id, pduplex); - return rv; - } -/*qca808x_start*/ - SW_RTN_ON_NULL (p_api = hsl_api_ptr_get (dev_id)); - - if (NULL == p_api->port_duplex_get) - return SW_NOT_SUPPORTED; - - rv = p_api->port_duplex_get (dev_id, port_id, pduplex); - return rv; -} - -static sw_error_t -_fal_port_autoneg_enable (a_uint32_t dev_id, fal_port_t port_id) -{ - sw_error_t rv; - hsl_api_t *p_api; -/*qca808x_end*/ - adpt_api_t *p_adpt_api; - - if((p_adpt_api = adpt_api_ptr_get(dev_id)) != NULL && - p_adpt_api->adpt_port_autoneg_enable != NULL) { - rv = p_adpt_api->adpt_port_autoneg_enable(dev_id, port_id); - return rv; - } -/*qca808x_start*/ - SW_RTN_ON_NULL (p_api = hsl_api_ptr_get (dev_id)); - - if (NULL == p_api->port_autoneg_enable) - return SW_NOT_SUPPORTED; - - rv = p_api->port_autoneg_enable (dev_id, port_id); - return rv; -} - -static sw_error_t -_fal_port_autoneg_restart (a_uint32_t dev_id, fal_port_t port_id) -{ - sw_error_t rv; - hsl_api_t *p_api; -/*qca808x_end*/ - adpt_api_t *p_adpt_api; - - if((p_adpt_api = adpt_api_ptr_get(dev_id)) != NULL && - p_adpt_api->adpt_port_autoneg_restart != NULL) { - rv = p_adpt_api->adpt_port_autoneg_restart(dev_id, port_id); - return rv; - } -/*qca808x_start*/ - SW_RTN_ON_NULL (p_api = hsl_api_ptr_get (dev_id)); - - if (NULL == p_api->port_autoneg_restart) - return SW_NOT_SUPPORTED; - - rv = p_api->port_autoneg_restart (dev_id, port_id); - return rv; -} - - -static sw_error_t -_fal_port_autoneg_adv_set (a_uint32_t dev_id, fal_port_t port_id, - a_uint32_t autoadv) -{ - sw_error_t rv; - hsl_api_t *p_api; -/*qca808x_end*/ - adpt_api_t *p_adpt_api; - - if((p_adpt_api = adpt_api_ptr_get(dev_id)) != NULL && - p_adpt_api->adpt_port_autoneg_adv_set != NULL) { - rv = p_adpt_api->adpt_port_autoneg_adv_set(dev_id, port_id, autoadv); - return rv; - } -/*qca808x_start*/ - SW_RTN_ON_NULL (p_api = hsl_api_ptr_get (dev_id)); - - if (NULL == p_api->port_autoneg_adv_set) - return SW_NOT_SUPPORTED; - - rv = p_api->port_autoneg_adv_set (dev_id, port_id, autoadv); - return rv; -} - -static sw_error_t -_fal_port_autoneg_status_get (a_uint32_t dev_id, fal_port_t port_id, - a_bool_t * status) -{ - sw_error_t rv; - hsl_api_t *p_api; -/*qca808x_end*/ - adpt_api_t *p_adpt_api; - - if((p_adpt_api = adpt_api_ptr_get(dev_id)) != NULL && - p_adpt_api->adpt_port_autoneg_status_get != NULL) { - rv = p_adpt_api->adpt_port_autoneg_status_get(dev_id, port_id, status); - return rv; - } -/*qca808x_start*/ - SW_RTN_ON_NULL (p_api = hsl_api_ptr_get (dev_id)); - - if (NULL == p_api->port_autoneg_status_get) - return SW_NOT_SUPPORTED; - - rv = p_api->port_autoneg_status_get (dev_id, port_id, status); - return rv; -} - -static sw_error_t -_fal_port_autoneg_adv_get (a_uint32_t dev_id, fal_port_t port_id, - a_uint32_t * autoadv) -{ - sw_error_t rv; - hsl_api_t *p_api; -/*qca808x_end*/ - adpt_api_t *p_adpt_api; - - if((p_adpt_api = adpt_api_ptr_get(dev_id)) != NULL && - p_adpt_api->adpt_port_autoneg_adv_get != NULL) { - rv = p_adpt_api->adpt_port_autoneg_adv_get(dev_id, port_id, autoadv); - return rv; - } -/*qca808x_start*/ - SW_RTN_ON_NULL (p_api = hsl_api_ptr_get (dev_id)); - - if (NULL == p_api->port_autoneg_adv_get) - return SW_NOT_SUPPORTED; - - rv = p_api->port_autoneg_adv_get (dev_id, port_id, autoadv); - return rv; -} -/*qca808x_end*/ -#ifndef IN_PORTCONTROL_MINI -static sw_error_t -_fal_port_hdr_status_set (a_uint32_t dev_id, fal_port_t port_id, - a_bool_t enable) -{ - sw_error_t rv; - hsl_api_t *p_api; - - SW_RTN_ON_NULL (p_api = hsl_api_ptr_get (dev_id)); - - if (NULL == p_api->port_hdr_status_set) - return SW_NOT_SUPPORTED; - - rv = p_api->port_hdr_status_set (dev_id, port_id, enable); - return rv; -} - - -static sw_error_t -_fal_port_hdr_status_get (a_uint32_t dev_id, fal_port_t port_id, - a_bool_t * enable) -{ - sw_error_t rv; - hsl_api_t *p_api; - - SW_RTN_ON_NULL (p_api = hsl_api_ptr_get (dev_id)); - - if (NULL == p_api->port_hdr_status_get) - return SW_NOT_SUPPORTED; - - rv = p_api->port_hdr_status_get (dev_id, port_id, enable); - return rv; -} - -static sw_error_t -_fal_port_flowctrl_get (a_uint32_t dev_id, fal_port_t port_id, - a_bool_t * enable) -{ - sw_error_t rv; - hsl_api_t *p_api; - adpt_api_t *p_adpt_api; - - if((p_adpt_api = adpt_api_ptr_get(dev_id)) != NULL) { - if (NULL == p_adpt_api->adpt_port_flowctrl_get) - return SW_NOT_SUPPORTED; - - rv = p_adpt_api->adpt_port_flowctrl_get(dev_id, port_id, enable); - return rv; - } - - SW_RTN_ON_NULL (p_api = hsl_api_ptr_get (dev_id)); - - if (NULL == p_api->port_flowctrl_get) - return SW_NOT_SUPPORTED; - - rv = p_api->port_flowctrl_get (dev_id, port_id, enable); - return rv; -} - - - -static sw_error_t -_fal_port_flowctrl_forcemode_get (a_uint32_t dev_id, fal_port_t port_id, - a_bool_t * enable) -{ - sw_error_t rv; - hsl_api_t *p_api; - adpt_api_t *p_adpt_api; - - if((p_adpt_api = adpt_api_ptr_get(dev_id)) != NULL) { - if (NULL == p_adpt_api->adpt_port_flowctrl_forcemode_get) - return SW_NOT_SUPPORTED; - - rv = p_adpt_api->adpt_port_flowctrl_forcemode_get(dev_id, port_id, enable); - return rv; - } - - SW_RTN_ON_NULL (p_api = hsl_api_ptr_get (dev_id)); - - if (NULL == p_api->port_flowctrl_forcemode_get) - return SW_NOT_SUPPORTED; - - rv = p_api->port_flowctrl_forcemode_get (dev_id, port_id, enable); - return rv; -} - -static sw_error_t -_fal_port_powersave_set (a_uint32_t dev_id, fal_port_t port_id, - a_bool_t enable) -{ - sw_error_t rv; - hsl_api_t *p_api; - adpt_api_t *p_adpt_api; - - if((p_adpt_api = adpt_api_ptr_get(dev_id)) != NULL && - p_adpt_api->adpt_port_powersave_set != NULL) { - rv = p_adpt_api->adpt_port_powersave_set(dev_id, port_id, enable); - return rv; - } - - SW_RTN_ON_NULL (p_api = hsl_api_ptr_get (dev_id)); - - if (NULL == p_api->port_powersave_set) - return SW_NOT_SUPPORTED; - - rv = p_api->port_powersave_set (dev_id, port_id, enable); - return rv; -} - - -static sw_error_t -_fal_port_powersave_get (a_uint32_t dev_id, fal_port_t port_id, - a_bool_t * enable) -{ - sw_error_t rv; - hsl_api_t *p_api; - adpt_api_t *p_adpt_api; - - if((p_adpt_api = adpt_api_ptr_get(dev_id)) != NULL && - p_adpt_api->adpt_port_powersave_get != NULL) { - rv = p_adpt_api->adpt_port_powersave_get(dev_id, port_id, enable); - return rv; - } - - SW_RTN_ON_NULL (p_api = hsl_api_ptr_get (dev_id)); - - if (NULL == p_api->port_powersave_get) - return SW_NOT_SUPPORTED; - - rv = p_api->port_powersave_get (dev_id, port_id, enable); - return rv; -} -/*qca808x_start*/ -static sw_error_t -_fal_port_hibernate_set (a_uint32_t dev_id, fal_port_t port_id, - a_bool_t enable) -{ - sw_error_t rv; - hsl_api_t *p_api; -/*qca808x_end*/ - adpt_api_t *p_adpt_api; - - if((p_adpt_api = adpt_api_ptr_get(dev_id)) != NULL && - p_adpt_api->adpt_port_hibernate_set != NULL) { - rv = p_adpt_api->adpt_port_hibernate_set(dev_id, port_id, enable); - return rv; - } -/*qca808x_start*/ - SW_RTN_ON_NULL (p_api = hsl_api_ptr_get (dev_id)); - - if (NULL == p_api->port_hibernate_set) - return SW_NOT_SUPPORTED; - - rv = p_api->port_hibernate_set (dev_id, port_id, enable); - return rv; -} - - -static sw_error_t -_fal_port_hibernate_get (a_uint32_t dev_id, fal_port_t port_id, - a_bool_t * enable) -{ - sw_error_t rv; - hsl_api_t *p_api; -/*qca808x_end*/ - adpt_api_t *p_adpt_api; - - if((p_adpt_api = adpt_api_ptr_get(dev_id)) != NULL && - p_adpt_api->adpt_port_hibernate_get != NULL) { - rv = p_adpt_api->adpt_port_hibernate_get(dev_id, port_id, enable); - return rv; - } -/*qca808x_start*/ - SW_RTN_ON_NULL (p_api = hsl_api_ptr_get (dev_id)); - - if (NULL == p_api->port_hibernate_get) - return SW_NOT_SUPPORTED; - - rv = p_api->port_hibernate_get (dev_id, port_id, enable); - return rv; -} - -static sw_error_t -_fal_port_cdt (a_uint32_t dev_id, fal_port_t port_id, a_uint32_t mdi_pair, - a_uint32_t * cable_status, a_uint32_t * cable_len) -{ - sw_error_t rv; - hsl_api_t *p_api; -/*qca808x_end*/ - adpt_api_t *p_adpt_api; - - if((p_adpt_api = adpt_api_ptr_get(dev_id)) != NULL && - p_adpt_api->adpt_port_cdt != NULL) { - rv = p_adpt_api->adpt_port_cdt(dev_id, port_id, mdi_pair, cable_status, cable_len); - return rv; - } -/*qca808x_start*/ - SW_RTN_ON_NULL (p_api = hsl_api_ptr_get (dev_id)); - - if (NULL == p_api->port_cdt) - return SW_NOT_SUPPORTED; - - rv = p_api->port_cdt (dev_id, port_id, mdi_pair, cable_status, cable_len); - return rv; -} -/*qca808x_end*/ -static sw_error_t -_fal_port_rxhdr_mode_get (a_uint32_t dev_id, fal_port_t port_id, - fal_port_header_mode_t * mode) -{ - sw_error_t rv; - hsl_api_t *p_api; - - SW_RTN_ON_NULL (p_api = hsl_api_ptr_get (dev_id)); - - if (NULL == p_api->port_rxhdr_mode_get) - return SW_NOT_SUPPORTED; - - rv = p_api->port_rxhdr_mode_get (dev_id, port_id, mode); - return rv; -} -static sw_error_t -_fal_port_txhdr_mode_get (a_uint32_t dev_id, fal_port_t port_id, - fal_port_header_mode_t * mode) -{ - sw_error_t rv; - hsl_api_t *p_api; - - SW_RTN_ON_NULL (p_api = hsl_api_ptr_get (dev_id)); - - if (NULL == p_api->port_txhdr_mode_get) - return SW_NOT_SUPPORTED; - - rv = p_api->port_txhdr_mode_get (dev_id, port_id, mode); - return rv; -} -static sw_error_t -_fal_header_type_get (a_uint32_t dev_id, a_bool_t * enable, a_uint32_t * type) -{ - sw_error_t rv; - hsl_api_t *p_api; - - SW_RTN_ON_NULL (p_api = hsl_api_ptr_get (dev_id)); - - if (NULL == p_api->header_type_get) - return SW_NOT_SUPPORTED; - - rv = p_api->header_type_get (dev_id, enable, type); - return rv; -} -#endif -static sw_error_t -_fal_port_rxhdr_mode_set (a_uint32_t dev_id, fal_port_t port_id, - fal_port_header_mode_t mode) -{ - sw_error_t rv; - hsl_api_t *p_api; - - SW_RTN_ON_NULL (p_api = hsl_api_ptr_get (dev_id)); - - if (NULL == p_api->port_rxhdr_mode_set) - return SW_NOT_SUPPORTED; - - rv = p_api->port_rxhdr_mode_set (dev_id, port_id, mode); - return rv; -} - - - -static sw_error_t -_fal_port_txhdr_mode_set (a_uint32_t dev_id, fal_port_t port_id, - fal_port_header_mode_t mode) -{ - sw_error_t rv; - hsl_api_t *p_api; - - SW_RTN_ON_NULL (p_api = hsl_api_ptr_get (dev_id)); - - if (NULL == p_api->port_txhdr_mode_set) - return SW_NOT_SUPPORTED; - - rv = p_api->port_txhdr_mode_set (dev_id, port_id, mode); - return rv; -} - - - -static sw_error_t -_fal_header_type_set (a_uint32_t dev_id, a_bool_t enable, a_uint32_t type) -{ - sw_error_t rv; - hsl_api_t *p_api; - - SW_RTN_ON_NULL (p_api = hsl_api_ptr_get (dev_id)); - - if (NULL == p_api->header_type_set) - return SW_NOT_SUPPORTED; - - rv = p_api->header_type_set (dev_id, enable, type); - return rv; -} - - - -static sw_error_t -_fal_port_txmac_status_set (a_uint32_t dev_id, fal_port_t port_id, - a_bool_t enable) -{ - sw_error_t rv; - hsl_api_t *p_api; - adpt_api_t *p_adpt_api; - - if((p_adpt_api = adpt_api_ptr_get(dev_id)) != NULL) { - if (NULL == p_adpt_api->adpt_port_txmac_status_set) - return SW_NOT_SUPPORTED; - - rv = p_adpt_api->adpt_port_txmac_status_set(dev_id, port_id, enable); - return rv; - } - - SW_RTN_ON_NULL (p_api = hsl_api_ptr_get (dev_id)); - - if (NULL == p_api->port_txmac_status_set) - return SW_NOT_SUPPORTED; - - rv = p_api->port_txmac_status_set (dev_id, port_id, enable); - return rv; -} - - - -static sw_error_t -_fal_port_rxmac_status_set (a_uint32_t dev_id, fal_port_t port_id, - a_bool_t enable) -{ - sw_error_t rv; - hsl_api_t *p_api; - adpt_api_t *p_adpt_api; - - if((p_adpt_api = adpt_api_ptr_get(dev_id)) != NULL) { - if (NULL == p_adpt_api->adpt_port_rxmac_status_set) - return SW_NOT_SUPPORTED; - - rv = p_adpt_api->adpt_port_rxmac_status_set(dev_id, port_id, enable); - return rv; - } - - SW_RTN_ON_NULL (p_api = hsl_api_ptr_get (dev_id)); - - if (NULL == p_api->port_rxmac_status_set) - return SW_NOT_SUPPORTED; - - rv = p_api->port_rxmac_status_set (dev_id, port_id, enable); - return rv; -} - - - -static sw_error_t -_fal_port_txfc_status_set (a_uint32_t dev_id, fal_port_t port_id, - a_bool_t enable) -{ - sw_error_t rv; - hsl_api_t *p_api; - adpt_api_t *p_adpt_api; - - if((p_adpt_api = adpt_api_ptr_get(dev_id)) != NULL) { - if (NULL == p_adpt_api->adpt_port_txfc_status_set) - return SW_NOT_SUPPORTED; - - rv = p_adpt_api->adpt_port_txfc_status_set(dev_id, port_id, enable); - return rv; - } - - SW_RTN_ON_NULL (p_api = hsl_api_ptr_get (dev_id)); - - if (NULL == p_api->port_txfc_status_set) - return SW_NOT_SUPPORTED; - - rv = p_api->port_txfc_status_set (dev_id, port_id, enable); - return rv; -} - - - -static sw_error_t -_fal_port_rxfc_status_set (a_uint32_t dev_id, fal_port_t port_id, - a_bool_t enable) -{ - sw_error_t rv; - hsl_api_t *p_api; - adpt_api_t *p_adpt_api; - - if((p_adpt_api = adpt_api_ptr_get(dev_id)) != NULL) { - if (NULL == p_adpt_api->adpt_port_rxfc_status_set) - return SW_NOT_SUPPORTED; - - rv = p_adpt_api->adpt_port_rxfc_status_set(dev_id, port_id, enable); - return rv; - } - - SW_RTN_ON_NULL (p_api = hsl_api_ptr_get (dev_id)); - - if (NULL == p_api->port_rxfc_status_set) - return SW_NOT_SUPPORTED; - - rv = p_api->port_rxfc_status_set (dev_id, port_id, enable); - return rv; -} -static sw_error_t -_fal_port_txfc_status_get (a_uint32_t dev_id, fal_port_t port_id, - a_bool_t * enable) -{ - sw_error_t rv; - hsl_api_t *p_api; - adpt_api_t *p_adpt_api; - - if((p_adpt_api = adpt_api_ptr_get(dev_id)) != NULL) { - if (NULL == p_adpt_api->adpt_port_txfc_status_get) - return SW_NOT_SUPPORTED; - - rv = p_adpt_api->adpt_port_txfc_status_get(dev_id, port_id, enable); - return rv; - } - - SW_RTN_ON_NULL (p_api = hsl_api_ptr_get (dev_id)); - - if (NULL == p_api->port_txfc_status_get) - return SW_NOT_SUPPORTED; - - rv = p_api->port_txfc_status_get (dev_id, port_id, enable); - return rv; -} -static sw_error_t -_fal_port_rxfc_status_get (a_uint32_t dev_id, fal_port_t port_id, - a_bool_t * enable) -{ - sw_error_t rv; - hsl_api_t *p_api; - adpt_api_t *p_adpt_api; - - if((p_adpt_api = adpt_api_ptr_get(dev_id)) != NULL) { - if (NULL == p_adpt_api->adpt_port_rxfc_status_get) - return SW_NOT_SUPPORTED; - - rv = p_adpt_api->adpt_port_rxfc_status_get(dev_id, port_id, enable); - return rv; - } - - SW_RTN_ON_NULL (p_api = hsl_api_ptr_get (dev_id)); - - if (NULL == p_api->port_rxfc_status_get) - return SW_NOT_SUPPORTED; - - rv = p_api->port_rxfc_status_get (dev_id, port_id, enable); - return rv; -} -/*qca808x_start*/ -static sw_error_t -_fal_port_link_status_get (a_uint32_t dev_id, fal_port_t port_id, - a_bool_t * status) -{ - sw_error_t rv; - hsl_api_t *p_api; -/*qca808x_end*/ - adpt_api_t *p_adpt_api; - - if((p_adpt_api = adpt_api_ptr_get(dev_id)) != NULL && - p_adpt_api->adpt_port_link_status_get != NULL) { - rv = p_adpt_api->adpt_port_link_status_get(dev_id, port_id, status); - return rv; - } -/*qca808x_start*/ - SW_RTN_ON_NULL (p_api = hsl_api_ptr_get (dev_id)); - - if (NULL == p_api->port_link_status_get) - return SW_NOT_SUPPORTED; - - rv = p_api->port_link_status_get (dev_id, port_id, status); - return rv; -} - -static sw_error_t -_fal_port_power_off (a_uint32_t dev_id, fal_port_t port_id) -{ - sw_error_t rv; - hsl_api_t *p_api; -/*qca808x_end*/ - adpt_api_t *p_adpt_api; - - if((p_adpt_api = adpt_api_ptr_get(dev_id)) != NULL && - p_adpt_api->adpt_port_power_off != NULL) { - rv = p_adpt_api->adpt_port_power_off(dev_id, port_id); - return rv; - } -/*qca808x_start*/ - SW_RTN_ON_NULL (p_api = hsl_api_ptr_get (dev_id)); - - if (NULL == p_api->port_power_off) - return SW_NOT_SUPPORTED; - - rv = p_api->port_power_off (dev_id, port_id); - return rv; -} - -static sw_error_t -_fal_port_power_on (a_uint32_t dev_id, fal_port_t port_id) -{ - sw_error_t rv; - hsl_api_t *p_api; -/*qca808x_end*/ - adpt_api_t *p_adpt_api; - - if((p_adpt_api = adpt_api_ptr_get(dev_id)) != NULL && - p_adpt_api->adpt_port_power_on != NULL) { - rv = p_adpt_api->adpt_port_power_on(dev_id, port_id); - return rv; - } -/*qca808x_start*/ - SW_RTN_ON_NULL (p_api = hsl_api_ptr_get (dev_id)); - - if (NULL == p_api->port_power_on) - return SW_NOT_SUPPORTED; - - rv = p_api->port_power_on (dev_id, port_id); - return rv; -} -/*qca808x_end*/ -static sw_error_t -_fal_port_link_forcemode_set (a_uint32_t dev_id, fal_port_t port_id, - a_bool_t enable) -{ - sw_error_t rv; - hsl_api_t *p_api; - - SW_RTN_ON_NULL (p_api = hsl_api_ptr_get (dev_id)); - - if (NULL == p_api->port_link_forcemode_set) - return SW_NOT_SUPPORTED; - - rv = p_api->port_link_forcemode_set (dev_id, port_id, enable); - return rv; -} - -static sw_error_t -_fal_port_link_forcemode_get (a_uint32_t dev_id, fal_port_t port_id, - a_bool_t * enable) -{ - sw_error_t rv; - hsl_api_t *p_api; - - SW_RTN_ON_NULL (p_api = hsl_api_ptr_get (dev_id)); - - if (NULL == p_api->port_link_forcemode_get) - return SW_NOT_SUPPORTED; - - rv = p_api->port_link_forcemode_get (dev_id, port_id, enable); - return rv; -} -#ifndef IN_PORTCONTROL_MINI -static sw_error_t -_fal_port_txmac_status_get (a_uint32_t dev_id, fal_port_t port_id, - a_bool_t * enable) -{ - sw_error_t rv; - hsl_api_t *p_api; - adpt_api_t *p_adpt_api; - - if((p_adpt_api = adpt_api_ptr_get(dev_id)) != NULL) { - if (NULL == p_adpt_api->adpt_port_txmac_status_get) - return SW_NOT_SUPPORTED; - - rv = p_adpt_api->adpt_port_txmac_status_get(dev_id, port_id, enable); - return rv; - } - - SW_RTN_ON_NULL (p_api = hsl_api_ptr_get (dev_id)); - - if (NULL == p_api->port_txmac_status_get) - return SW_NOT_SUPPORTED; - - rv = p_api->port_txmac_status_get (dev_id, port_id, enable); - return rv; -} -static sw_error_t -_fal_port_rxmac_status_get (a_uint32_t dev_id, fal_port_t port_id, - a_bool_t * enable) -{ - sw_error_t rv; - hsl_api_t *p_api; - adpt_api_t *p_adpt_api; - - if((p_adpt_api = adpt_api_ptr_get(dev_id)) != NULL) { - if (NULL == p_adpt_api->adpt_port_rxmac_status_get) - return SW_NOT_SUPPORTED; - - rv = p_adpt_api->adpt_port_rxmac_status_get(dev_id, port_id, enable); - return rv; - } - - SW_RTN_ON_NULL (p_api = hsl_api_ptr_get (dev_id)); - - if (NULL == p_api->port_rxmac_status_get) - return SW_NOT_SUPPORTED; - - rv = p_api->port_rxmac_status_get (dev_id, port_id, enable); - return rv; -} - -static sw_error_t -_fal_port_bp_status_set (a_uint32_t dev_id, fal_port_t port_id, - a_bool_t enable) -{ - sw_error_t rv; - hsl_api_t *p_api; - - SW_RTN_ON_NULL (p_api = hsl_api_ptr_get (dev_id)); - - if (NULL == p_api->port_bp_status_set) - return SW_NOT_SUPPORTED; - - rv = p_api->port_bp_status_set (dev_id, port_id, enable); - return rv; -} - -static sw_error_t -_fal_port_bp_status_get (a_uint32_t dev_id, fal_port_t port_id, - a_bool_t * enable) -{ - sw_error_t rv; - hsl_api_t *p_api; - - SW_RTN_ON_NULL (p_api = hsl_api_ptr_get (dev_id)); - - if (NULL == p_api->port_bp_status_get) - return SW_NOT_SUPPORTED; - - rv = p_api->port_bp_status_get (dev_id, port_id, enable); - return rv; -} - -static sw_error_t -_fal_ports_link_status_get (a_uint32_t dev_id, a_uint32_t * status) -{ - sw_error_t rv; - hsl_api_t *p_api; - adpt_api_t *p_adpt_api; - - if((p_adpt_api = adpt_api_ptr_get(dev_id)) != NULL && - p_adpt_api->adpt_ports_link_status_get != NULL) { - rv = p_adpt_api->adpt_ports_link_status_get(dev_id, status); - return rv; - } - - SW_RTN_ON_NULL (p_api = hsl_api_ptr_get (dev_id)); - - if (NULL == p_api->ports_link_status_get) - return SW_NOT_SUPPORTED; - - rv = p_api->ports_link_status_get (dev_id, status); - return rv; -} - -static sw_error_t -_fal_port_mac_loopback_set (a_uint32_t dev_id, fal_port_t port_id, - a_bool_t enable) -{ - sw_error_t rv; - hsl_api_t *p_api; - adpt_api_t *p_adpt_api; - - if((p_adpt_api = adpt_api_ptr_get(dev_id)) != NULL) { - if (NULL == p_adpt_api->adpt_port_mac_loopback_set) - return SW_NOT_SUPPORTED; - - rv = p_adpt_api->adpt_port_mac_loopback_set(dev_id, port_id, enable); - return rv; - } - - SW_RTN_ON_NULL (p_api = hsl_api_ptr_get (dev_id)); - - if (NULL == p_api->port_mac_loopback_set) - return SW_NOT_SUPPORTED; - - rv = p_api->port_mac_loopback_set (dev_id, port_id, enable); - return rv; -} - -static sw_error_t -_fal_port_mac_loopback_get (a_uint32_t dev_id, fal_port_t port_id, - a_bool_t * enable) -{ - sw_error_t rv; - hsl_api_t *p_api; - adpt_api_t *p_adpt_api; - - if((p_adpt_api = adpt_api_ptr_get(dev_id)) != NULL) { - if (NULL == p_adpt_api->adpt_port_mac_loopback_get) - return SW_NOT_SUPPORTED; - - rv = p_adpt_api->adpt_port_mac_loopback_get(dev_id, port_id, enable); - return rv; - } - - SW_RTN_ON_NULL (p_api = hsl_api_ptr_get (dev_id)); - - if (NULL == p_api->port_mac_loopback_get) - return SW_NOT_SUPPORTED; - - rv = p_api->port_mac_loopback_get (dev_id, port_id, enable); - return rv; -} - -static sw_error_t -_fal_port_congestion_drop_set (a_uint32_t dev_id, fal_port_t port_id, - a_uint32_t queue_id, a_bool_t enable) -{ - sw_error_t rv; - hsl_api_t *p_api; - - SW_RTN_ON_NULL (p_api = hsl_api_ptr_get (dev_id)); - - if (NULL == p_api->port_congestion_drop_set) - return SW_NOT_SUPPORTED; - - rv = p_api->port_congestion_drop_set (dev_id, port_id, queue_id, enable); - return rv; -} - -static sw_error_t -_fal_port_congestion_drop_get (a_uint32_t dev_id, fal_port_t port_id, - a_uint32_t queue_id, a_bool_t * enable) -{ - sw_error_t rv; - hsl_api_t *p_api; - - SW_RTN_ON_NULL (p_api = hsl_api_ptr_get (dev_id)); - - if (NULL == p_api->port_congestion_drop_get) - return SW_NOT_SUPPORTED; - - rv = p_api->port_congestion_drop_get (dev_id, port_id, queue_id, enable); - return rv; -} - -static sw_error_t -_fal_ring_flow_ctrl_thres_set (a_uint32_t dev_id, a_uint32_t ring_id, - a_uint8_t on_thres, a_uint8_t off_thres) -{ - sw_error_t rv; - hsl_api_t *p_api; - - SW_RTN_ON_NULL (p_api = hsl_api_ptr_get (dev_id)); - - if (NULL == p_api->ring_flow_ctrl_thres_set) - return SW_NOT_SUPPORTED; - - rv = p_api->ring_flow_ctrl_thres_set (dev_id, ring_id, on_thres, off_thres); - return rv; -} - -static sw_error_t -_fal_ring_flow_ctrl_thres_get (a_uint32_t dev_id, a_uint32_t ring_id, - a_uint8_t * on_thres, a_uint8_t * off_thres) -{ - sw_error_t rv; - hsl_api_t *p_api; - - SW_RTN_ON_NULL (p_api = hsl_api_ptr_get (dev_id)); - - if (NULL == p_api->ring_flow_ctrl_thres_get) - return SW_NOT_SUPPORTED; - - rv = p_api->ring_flow_ctrl_thres_get (dev_id, ring_id, on_thres, off_thres); - return rv; -} -/*qca808x_start*/ -static sw_error_t -_fal_port_8023az_set (a_uint32_t dev_id, fal_port_t port_id, a_bool_t enable) -{ - sw_error_t rv; - hsl_api_t *p_api; -/*qca808x_end*/ - adpt_api_t *p_adpt_api; - - if((p_adpt_api = adpt_api_ptr_get(dev_id)) != NULL && - p_adpt_api->adpt_port_8023az_set != NULL) { - rv = p_adpt_api->adpt_port_8023az_set(dev_id, port_id, enable); - return rv; - } -/*qca808x_start*/ - SW_RTN_ON_NULL (p_api = hsl_api_ptr_get (dev_id)); - - if (NULL == p_api->port_8023az_set) - return SW_NOT_SUPPORTED; - - rv = p_api->port_8023az_set (dev_id, port_id, enable); - return rv; -} - - -static sw_error_t -_fal_port_8023az_get (a_uint32_t dev_id, fal_port_t port_id, - a_bool_t * enable) -{ - sw_error_t rv; - hsl_api_t *p_api; -/*qca808x_end*/ - adpt_api_t *p_adpt_api; - - if((p_adpt_api = adpt_api_ptr_get(dev_id)) != NULL && - p_adpt_api->adpt_port_8023az_get != NULL) { - rv = p_adpt_api->adpt_port_8023az_get(dev_id, port_id, enable); - return rv; - } -/*qca808x_start*/ - SW_RTN_ON_NULL (p_api = hsl_api_ptr_get (dev_id)); - - if (NULL == p_api->port_8023az_get) - return SW_NOT_SUPPORTED; - - rv = p_api->port_8023az_get (dev_id, port_id, enable); - return rv; -} - -static sw_error_t -_fal_port_mdix_set (a_uint32_t dev_id, fal_port_t port_id, - fal_port_mdix_mode_t mode) -{ - sw_error_t rv; - hsl_api_t *p_api; -/*qca808x_end*/ - adpt_api_t *p_adpt_api; - - if((p_adpt_api = adpt_api_ptr_get(dev_id)) != NULL && - p_adpt_api->adpt_port_mdix_set != NULL) { - rv = p_adpt_api->adpt_port_mdix_set(dev_id, port_id, mode); - return rv; - } -/*qca808x_start*/ - SW_RTN_ON_NULL (p_api = hsl_api_ptr_get (dev_id)); - - if (NULL == p_api->port_mdix_set) - return SW_NOT_SUPPORTED; - - rv = p_api->port_mdix_set (dev_id, port_id, mode); - return rv; -} - -static sw_error_t -_fal_port_mdix_get (a_uint32_t dev_id, fal_port_t port_id, - fal_port_mdix_mode_t * mode) -{ - sw_error_t rv; - hsl_api_t *p_api; -/*qca808x_end*/ - adpt_api_t *p_adpt_api; - - if((p_adpt_api = adpt_api_ptr_get(dev_id)) != NULL && - p_adpt_api->adpt_port_mdix_get != NULL) { - rv = p_adpt_api->adpt_port_mdix_get(dev_id, port_id, mode); - return rv; - } -/*qca808x_start*/ - SW_RTN_ON_NULL (p_api = hsl_api_ptr_get (dev_id)); - - if (NULL == p_api->port_mdix_get) - return SW_NOT_SUPPORTED; - - rv = p_api->port_mdix_get (dev_id, port_id, mode); - return rv; -} - -static sw_error_t -_fal_port_mdix_status_get (a_uint32_t dev_id, fal_port_t port_id, - fal_port_mdix_status_t * mode) -{ - sw_error_t rv; - hsl_api_t *p_api; -/*qca808x_end*/ - adpt_api_t *p_adpt_api; - - if((p_adpt_api = adpt_api_ptr_get(dev_id)) != NULL && - p_adpt_api->adpt_port_mdix_status_get != NULL) { - rv = p_adpt_api->adpt_port_mdix_status_get(dev_id, port_id, mode); - return rv; - } -/*qca808x_start*/ - SW_RTN_ON_NULL (p_api = hsl_api_ptr_get (dev_id)); - - if (NULL == p_api->port_mdix_status_get) - return SW_NOT_SUPPORTED; - - rv = p_api->port_mdix_status_get (dev_id, port_id, mode); - return rv; -} -/*qca808x_end*/ -static sw_error_t -_fal_port_combo_prefer_medium_set (a_uint32_t dev_id, fal_port_t port_id, - fal_port_medium_t medium) -{ - sw_error_t rv; - hsl_api_t *p_api; - adpt_api_t *p_adpt_api; - - if((p_adpt_api = adpt_api_ptr_get(dev_id)) != NULL && - p_adpt_api->adpt_port_combo_prefer_medium_set != NULL) { - rv = p_adpt_api->adpt_port_combo_prefer_medium_set(dev_id, port_id, medium); - return rv; - } - - SW_RTN_ON_NULL (p_api = hsl_api_ptr_get (dev_id)); - - if (NULL == p_api->port_combo_prefer_medium_set) - return SW_NOT_SUPPORTED; - - rv = p_api->port_combo_prefer_medium_set (dev_id, port_id, medium); - return rv; -} - -static sw_error_t -_fal_port_combo_prefer_medium_get (a_uint32_t dev_id, fal_port_t port_id, - fal_port_medium_t * medium) -{ - sw_error_t rv; - hsl_api_t *p_api; - adpt_api_t *p_adpt_api; - - if((p_adpt_api = adpt_api_ptr_get(dev_id)) != NULL && - p_adpt_api->adpt_port_combo_prefer_medium_get != NULL) { - rv = p_adpt_api->adpt_port_combo_prefer_medium_get(dev_id, port_id, medium); - return rv; - } - - SW_RTN_ON_NULL (p_api = hsl_api_ptr_get (dev_id)); - - if (NULL == p_api->port_combo_prefer_medium_get) - return SW_NOT_SUPPORTED; - - rv = p_api->port_combo_prefer_medium_get (dev_id, port_id, medium); - return rv; -} - -static sw_error_t -_fal_port_combo_medium_status_get (a_uint32_t dev_id, fal_port_t port_id, - fal_port_medium_t * medium) -{ - sw_error_t rv; - hsl_api_t *p_api; - adpt_api_t *p_adpt_api; - - if((p_adpt_api = adpt_api_ptr_get(dev_id)) != NULL && - p_adpt_api->adpt_port_combo_medium_status_get != NULL) { - rv = p_adpt_api->adpt_port_combo_medium_status_get(dev_id, port_id, medium); - return rv; - } - - SW_RTN_ON_NULL (p_api = hsl_api_ptr_get (dev_id)); - - if (NULL == p_api->port_combo_medium_status_get) - return SW_NOT_SUPPORTED; - - rv = p_api->port_combo_medium_status_get (dev_id, port_id, medium); - return rv; -} - -static sw_error_t -_fal_port_combo_fiber_mode_set (a_uint32_t dev_id, fal_port_t port_id, - fal_port_fiber_mode_t mode) -{ - sw_error_t rv; - hsl_api_t *p_api; - adpt_api_t *p_adpt_api; - - if((p_adpt_api = adpt_api_ptr_get(dev_id)) != NULL && - p_adpt_api->adpt_port_combo_fiber_mode_set != NULL) { - rv = p_adpt_api->adpt_port_combo_fiber_mode_set(dev_id, port_id, mode); - return rv; - } - - SW_RTN_ON_NULL (p_api = hsl_api_ptr_get (dev_id)); - - if (NULL == p_api->port_combo_fiber_mode_set) - return SW_NOT_SUPPORTED; - - rv = p_api->port_combo_fiber_mode_set (dev_id, port_id, mode); - return rv; -} - -static sw_error_t -_fal_port_combo_fiber_mode_get (a_uint32_t dev_id, fal_port_t port_id, - fal_port_fiber_mode_t * mode) -{ - sw_error_t rv; - hsl_api_t *p_api; - adpt_api_t *p_adpt_api; - - if((p_adpt_api = adpt_api_ptr_get(dev_id)) != NULL && - p_adpt_api->adpt_port_combo_fiber_mode_get != NULL) { - rv = p_adpt_api->adpt_port_combo_fiber_mode_get(dev_id, port_id, mode); - return rv; - } - - SW_RTN_ON_NULL (p_api = hsl_api_ptr_get (dev_id)); - - if (NULL == p_api->port_combo_fiber_mode_get) - return SW_NOT_SUPPORTED; - - rv = p_api->port_combo_fiber_mode_get (dev_id, port_id, mode); - return rv; -} -/*qca808x_start*/ -static sw_error_t -_fal_port_local_loopback_set (a_uint32_t dev_id, fal_port_t port_id, - a_bool_t enable) -{ - sw_error_t rv; - hsl_api_t *p_api; -/*qca808x_end*/ - adpt_api_t *p_adpt_api; - - if((p_adpt_api = adpt_api_ptr_get(dev_id)) != NULL && - p_adpt_api->adpt_port_local_loopback_set != NULL) { - rv = p_adpt_api->adpt_port_local_loopback_set(dev_id, port_id, enable); - return rv; - } -/*qca808x_start*/ - SW_RTN_ON_NULL (p_api = hsl_api_ptr_get (dev_id)); - - if (NULL == p_api->port_local_loopback_set) - return SW_NOT_SUPPORTED; - - rv = p_api->port_local_loopback_set (dev_id, port_id, enable); - return rv; -} - - -static sw_error_t -_fal_port_local_loopback_get (a_uint32_t dev_id, fal_port_t port_id, - a_bool_t * enable) -{ - sw_error_t rv; - hsl_api_t *p_api; -/*qca808x_end*/ - adpt_api_t *p_adpt_api; - - if((p_adpt_api = adpt_api_ptr_get(dev_id)) != NULL && - p_adpt_api->adpt_port_local_loopback_get != NULL) { - rv = p_adpt_api->adpt_port_local_loopback_get(dev_id, port_id, enable); - return rv; - } -/*qca808x_start*/ - SW_RTN_ON_NULL (p_api = hsl_api_ptr_get (dev_id)); - - if (NULL == p_api->port_local_loopback_get) - return SW_NOT_SUPPORTED; - - rv = p_api->port_local_loopback_get (dev_id, port_id, enable); - return rv; -} - -static sw_error_t -_fal_port_remote_loopback_set (a_uint32_t dev_id, fal_port_t port_id, - a_bool_t enable) -{ - sw_error_t rv; - hsl_api_t *p_api; -/*qca808x_end*/ - adpt_api_t *p_adpt_api; - - if((p_adpt_api = adpt_api_ptr_get(dev_id)) != NULL && - p_adpt_api->adpt_port_remote_loopback_set != NULL) { - rv = p_adpt_api->adpt_port_remote_loopback_set(dev_id, port_id, enable); - return rv; - } -/*qca808x_start*/ - SW_RTN_ON_NULL (p_api = hsl_api_ptr_get (dev_id)); - - if (NULL == p_api->port_remote_loopback_set) - return SW_NOT_SUPPORTED; - - rv = p_api->port_remote_loopback_set (dev_id, port_id, enable); - return rv; -} - - -static sw_error_t -_fal_port_remote_loopback_get (a_uint32_t dev_id, fal_port_t port_id, - a_bool_t * enable) -{ - sw_error_t rv; - hsl_api_t *p_api; -/*qca808x_end*/ - adpt_api_t *p_adpt_api; - - if((p_adpt_api = adpt_api_ptr_get(dev_id)) != NULL && - p_adpt_api->adpt_port_remote_loopback_get!= NULL) { - rv = p_adpt_api->adpt_port_remote_loopback_get(dev_id, port_id, enable); - return rv; - } -/*qca808x_start*/ - SW_RTN_ON_NULL (p_api = hsl_api_ptr_get (dev_id)); - - if (NULL == p_api->port_remote_loopback_get) - return SW_NOT_SUPPORTED; - - rv = p_api->port_remote_loopback_get (dev_id, port_id, enable); - return rv; -} - -static sw_error_t -_fal_port_reset (a_uint32_t dev_id, fal_port_t port_id) -{ - sw_error_t rv; - hsl_api_t *p_api; -/*qca808x_end*/ - adpt_api_t *p_adpt_api; - - if((p_adpt_api = adpt_api_ptr_get(dev_id)) != NULL && - p_adpt_api->adpt_port_reset != NULL) { - rv = p_adpt_api->adpt_port_reset(dev_id, port_id); - return rv; - } -/*qca808x_start*/ - SW_RTN_ON_NULL (p_api = hsl_api_ptr_get (dev_id)); - - if (NULL == p_api->port_reset) - return SW_NOT_SUPPORTED; - - rv = p_api->port_reset (dev_id, port_id); - return rv; -} - - -static sw_error_t -_fal_port_phy_id_get (a_uint32_t dev_id, fal_port_t port_id,a_uint16_t * org_id, a_uint16_t * rev_id) -{ - sw_error_t rv; - hsl_api_t *p_api; -/*qca808x_end*/ - adpt_api_t *p_adpt_api; - - if((p_adpt_api = adpt_api_ptr_get(dev_id)) != NULL && - p_adpt_api->adpt_port_phy_id_get != NULL) { - rv = p_adpt_api->adpt_port_phy_id_get(dev_id, port_id, org_id, rev_id); - return rv; - } -/*qca808x_start*/ - SW_RTN_ON_NULL (p_api = hsl_api_ptr_get (dev_id)); - - if (NULL == p_api->port_phy_id_get) - return SW_NOT_SUPPORTED; - - rv = p_api->port_phy_id_get (dev_id, port_id,org_id,rev_id); - return rv; -} - -static sw_error_t -_fal_port_wol_status_set (a_uint32_t dev_id, fal_port_t port_id, a_bool_t enable) -{ - sw_error_t rv; - hsl_api_t *p_api; -/*qca808x_end*/ - adpt_api_t *p_adpt_api; - - if((p_adpt_api = adpt_api_ptr_get(dev_id)) != NULL && - p_adpt_api->adpt_port_wol_status_set != NULL) { - rv = p_adpt_api->adpt_port_wol_status_set(dev_id, port_id, enable); - return rv; - } -/*qca808x_start*/ - SW_RTN_ON_NULL (p_api = hsl_api_ptr_get (dev_id)); - - if (NULL == p_api->port_wol_status_set) - return SW_NOT_SUPPORTED; - - rv = p_api->port_wol_status_set (dev_id, port_id,enable); - return rv; -} - -static sw_error_t -_fal_port_wol_status_get (a_uint32_t dev_id, fal_port_t port_id, a_bool_t *enable) -{ - sw_error_t rv; - hsl_api_t *p_api; -/*qca808x_end*/ - adpt_api_t *p_adpt_api; - - if((p_adpt_api = adpt_api_ptr_get(dev_id)) != NULL && - p_adpt_api->adpt_port_wol_status_get != NULL) { - rv = p_adpt_api->adpt_port_wol_status_get(dev_id, port_id, enable); - return rv; - } -/*qca808x_start*/ - SW_RTN_ON_NULL (p_api = hsl_api_ptr_get (dev_id)); - - if (NULL == p_api->port_wol_status_get) - return SW_NOT_SUPPORTED; - - rv = p_api->port_wol_status_get (dev_id, port_id,enable); - return rv; -} - -static sw_error_t -_fal_port_magic_frame_mac_set (a_uint32_t dev_id, fal_port_t port_id, fal_mac_addr_t * mac) -{ - sw_error_t rv; - hsl_api_t *p_api; -/*qca808x_end*/ - adpt_api_t *p_adpt_api; - - if((p_adpt_api = adpt_api_ptr_get(dev_id)) != NULL && - p_adpt_api->adpt_port_magic_frame_mac_set != NULL) { - rv = p_adpt_api->adpt_port_magic_frame_mac_set(dev_id, port_id, mac); - return rv; - } -/*qca808x_start*/ - SW_RTN_ON_NULL (p_api = hsl_api_ptr_get (dev_id)); - - if (NULL == p_api->port_magic_frame_mac_set) - return SW_NOT_SUPPORTED; - - rv = p_api->port_magic_frame_mac_set (dev_id, port_id, mac); - return rv; -} - -static sw_error_t -_fal_port_magic_frame_mac_get (a_uint32_t dev_id, fal_port_t port_id, fal_mac_addr_t * mac) -{ - sw_error_t rv; - hsl_api_t *p_api; -/*qca808x_end*/ - adpt_api_t *p_adpt_api; - - if((p_adpt_api = adpt_api_ptr_get(dev_id)) != NULL && - p_adpt_api->adpt_port_magic_frame_mac_get != NULL) { - rv = p_adpt_api->adpt_port_magic_frame_mac_get(dev_id, port_id, mac); - return rv; - } -/*qca808x_start*/ - SW_RTN_ON_NULL (p_api = hsl_api_ptr_get (dev_id)); - - if (NULL == p_api->port_magic_frame_mac_get) - return SW_NOT_SUPPORTED; - - rv = p_api->port_magic_frame_mac_get (dev_id, port_id, mac); - return rv; -} -/*qca808x_end*/ -static sw_error_t -_fal_port_interface_mode_set (a_uint32_t dev_id, fal_port_t port_id, fal_port_interface_mode_t mode) -{ - sw_error_t rv; - hsl_api_t *p_api; - adpt_api_t *p_adpt_api; - if((p_adpt_api = adpt_api_ptr_get(dev_id)) != NULL && - p_adpt_api->adpt_port_interface_mode_set != NULL) { - rv = p_adpt_api->adpt_port_interface_mode_set(dev_id, port_id, mode); - return rv; - } - - SW_RTN_ON_NULL (p_api = hsl_api_ptr_get (dev_id)); - - if (NULL == p_api->port_interface_mode_set) - return SW_NOT_SUPPORTED; - - rv = p_api->port_interface_mode_set (dev_id, port_id, mode); - return rv; -} - -static sw_error_t -_fal_port_interface_mode_get (a_uint32_t dev_id, fal_port_t port_id, fal_port_interface_mode_t * mode) -{ - sw_error_t rv; - hsl_api_t *p_api; - adpt_api_t *p_adpt_api; - - if((p_adpt_api = adpt_api_ptr_get(dev_id)) != NULL && - p_adpt_api->adpt_port_interface_mode_get != NULL) { - rv = p_adpt_api->adpt_port_interface_mode_get(dev_id, port_id, mode); - return rv; - } - - SW_RTN_ON_NULL (p_api = hsl_api_ptr_get (dev_id)); - - if (NULL == p_api->port_interface_mode_get) - return SW_NOT_SUPPORTED; - - rv = p_api->port_interface_mode_get (dev_id, port_id, mode); - return rv; -} -/*qca808x_start*/ -static sw_error_t -_fal_port_interface_mode_status_get (a_uint32_t dev_id, fal_port_t port_id, fal_port_interface_mode_t * mode) -{ - sw_error_t rv; - hsl_api_t *p_api; -/*qca808x_end*/ - adpt_api_t *p_adpt_api; - - if((p_adpt_api = adpt_api_ptr_get(dev_id)) != NULL && - p_adpt_api->adpt_port_interface_mode_status_get != NULL) { - rv = p_adpt_api->adpt_port_interface_mode_status_get(dev_id, port_id, mode); - return rv; - } -/*qca808x_start*/ - SW_RTN_ON_NULL (p_api = hsl_api_ptr_get (dev_id)); - - if (NULL == p_api->port_interface_mode_status_get) - return SW_NOT_SUPPORTED; - - rv = p_api->port_interface_mode_status_get (dev_id, port_id, mode); - return rv; -} - -static sw_error_t -_fal_port_counter_set (a_uint32_t dev_id, fal_port_t port_id, a_bool_t enable) -{ - sw_error_t rv; - hsl_api_t *p_api; -/*qca808x_end*/ - adpt_api_t *p_adpt_api; - - if((p_adpt_api = adpt_api_ptr_get(dev_id)) != NULL && - p_adpt_api->adpt_port_counter_set != NULL) { - rv = p_adpt_api->adpt_port_counter_set(dev_id, port_id, enable); - return rv; - } -/*qca808x_start*/ - SW_RTN_ON_NULL (p_api = hsl_api_ptr_get (dev_id)); - - if (NULL == p_api->port_counter_set) - return SW_NOT_SUPPORTED; - - rv = p_api->port_counter_set (dev_id, port_id, enable); - return rv; -} - - -static sw_error_t -_fal_port_counter_get (a_uint32_t dev_id, fal_port_t port_id, - a_bool_t * enable) -{ - sw_error_t rv; - hsl_api_t *p_api; -/*qca808x_end*/ - adpt_api_t *p_adpt_api; - - if((p_adpt_api = adpt_api_ptr_get(dev_id)) != NULL && - p_adpt_api->adpt_port_counter_get != NULL) { - rv = p_adpt_api->adpt_port_counter_get(dev_id, port_id, enable); - return rv; - } -/*qca808x_start*/ - SW_RTN_ON_NULL (p_api = hsl_api_ptr_get (dev_id)); - - if (NULL == p_api->port_counter_get) - return SW_NOT_SUPPORTED; - - rv = p_api->port_counter_get (dev_id, port_id, enable); - return rv; -} - -static sw_error_t -_fal_port_counter_show (a_uint32_t dev_id, fal_port_t port_id, fal_port_counter_info_t * counter_info) -{ - sw_error_t rv; - hsl_api_t *p_api; -/*qca808x_end*/ - adpt_api_t *p_adpt_api; - - if((p_adpt_api = adpt_api_ptr_get(dev_id)) != NULL && - p_adpt_api->adpt_port_counter_show != NULL) { - rv = p_adpt_api->adpt_port_counter_show(dev_id, port_id, counter_info); - return rv; - } -/*qca808x_start*/ - SW_RTN_ON_NULL (p_api = hsl_api_ptr_get (dev_id)); - - if (NULL == p_api->port_counter_show) - return SW_NOT_SUPPORTED; - - rv = p_api->port_counter_show (dev_id, port_id, counter_info); - return rv; -} -/*qca808x_end*/ -#endif - -sw_error_t -_fal_port_max_frame_size_set(a_uint32_t dev_id, fal_port_t port_id, - a_uint32_t max_frame) -{ - adpt_api_t *p_api; - sw_error_t rv = SW_OK; - - SW_RTN_ON_NULL(p_api = adpt_api_ptr_get(dev_id)); - - if (NULL == p_api->adpt_port_max_frame_size_set) - return SW_NOT_SUPPORTED; - - rv = p_api->adpt_port_max_frame_size_set(dev_id, port_id, max_frame); - return rv; -} - -sw_error_t -_fal_port_max_frame_size_get(a_uint32_t dev_id, fal_port_t port_id, - a_uint32_t *max_frame) -{ - adpt_api_t *p_api; - sw_error_t rv = SW_OK; - - SW_RTN_ON_NULL(p_api = adpt_api_ptr_get(dev_id)); - - if (NULL == p_api->adpt_port_max_frame_size_get) - return SW_NOT_SUPPORTED; - - rv = p_api->adpt_port_max_frame_size_get(dev_id, port_id, max_frame); - return rv; -} - -#ifndef IN_PORTCONTROL_MINI -sw_error_t -_fal_port_mru_set(a_uint32_t dev_id, fal_port_t port_id, - fal_mru_ctrl_t *ctrl) -{ - adpt_api_t *p_api; - sw_error_t rv = SW_OK; - - SW_RTN_ON_NULL(p_api = adpt_api_ptr_get(dev_id)); - - if (NULL == p_api->adpt_port_mru_set) - return SW_NOT_SUPPORTED; - - rv = p_api->adpt_port_mru_set(dev_id, port_id, ctrl); - return rv; -} -sw_error_t -_fal_port_mru_get(a_uint32_t dev_id, fal_port_t port_id, - fal_mru_ctrl_t *ctrl) -{ - adpt_api_t *p_api; - sw_error_t rv = SW_OK; - - SW_RTN_ON_NULL(p_api = adpt_api_ptr_get(dev_id)); - - if (NULL == p_api->adpt_port_mru_get) - return SW_NOT_SUPPORTED; - - rv = p_api->adpt_port_mru_get(dev_id, port_id, ctrl); - return rv; -} -sw_error_t -_fal_port_mtu_set(a_uint32_t dev_id, fal_port_t port_id, - fal_mtu_ctrl_t *ctrl) -{ - adpt_api_t *p_api; - sw_error_t rv = SW_OK; - - SW_RTN_ON_NULL(p_api = adpt_api_ptr_get(dev_id)); - - if (NULL == p_api->adpt_port_mtu_set) - return SW_NOT_SUPPORTED; - - rv = p_api->adpt_port_mtu_set(dev_id, port_id, ctrl); - return rv; -} - -sw_error_t -_fal_port_mtu_get(a_uint32_t dev_id, fal_port_t port_id, - fal_mtu_ctrl_t *ctrl) -{ - adpt_api_t *p_api; - sw_error_t rv = SW_OK; - - SW_RTN_ON_NULL(p_api = adpt_api_ptr_get(dev_id)); - - if (NULL == p_api->adpt_port_mtu_get) - return SW_NOT_SUPPORTED; - - rv = p_api->adpt_port_mtu_get(dev_id, port_id, ctrl); - return rv; -} - -sw_error_t -_fal_port_source_filter_get(a_uint32_t dev_id, - fal_port_t port_id, a_bool_t * enable) -{ - adpt_api_t *p_api; - sw_error_t rv = SW_OK; - - SW_RTN_ON_NULL(p_api = adpt_api_ptr_get(dev_id)); - - if (NULL == p_api->adpt_port_source_filter_get) - return SW_NOT_SUPPORTED; - - rv = p_api->adpt_port_source_filter_get(dev_id, port_id, enable); - return rv; -} - -sw_error_t -_fal_port_source_filter_set(a_uint32_t dev_id, - fal_port_t port_id, a_bool_t enable) -{ - adpt_api_t *p_api; - sw_error_t rv = SW_OK; - - SW_RTN_ON_NULL(p_api = adpt_api_ptr_get(dev_id)); - - if (NULL == p_api->adpt_port_source_filter_set) - return SW_NOT_SUPPORTED; - - rv = p_api->adpt_port_source_filter_set(dev_id, port_id, enable); - return rv; -} - -static sw_error_t -_fal_port_source_filter_config_set(a_uint32_t dev_id, - fal_port_t port_id, fal_src_filter_config_t *src_filter_config) -{ - adpt_api_t *p_api; - sw_error_t rv = SW_OK; - - SW_RTN_ON_NULL(p_api = adpt_api_ptr_get(dev_id)); - - if (NULL == p_api->adpt_port_source_filter_config_set) - return SW_NOT_SUPPORTED; - - rv = p_api->adpt_port_source_filter_config_set(dev_id, port_id, - src_filter_config); - return rv; -} - -static sw_error_t -_fal_port_source_filter_config_get(a_uint32_t dev_id, - fal_port_t port_id, fal_src_filter_config_t *src_filter_config) -{ - adpt_api_t *p_api; - sw_error_t rv = SW_OK; - - SW_RTN_ON_NULL(p_api = adpt_api_ptr_get(dev_id)); - - if (NULL == p_api->adpt_port_source_filter_config_get) - return SW_NOT_SUPPORTED; - - rv = p_api->adpt_port_source_filter_config_get(dev_id, port_id, - src_filter_config); - return rv; -} - -static sw_error_t -_fal_port_interface_3az_status_set(a_uint32_t dev_id, fal_port_t port_id, - a_bool_t enable) -{ - - adpt_api_t *p_api; - sw_error_t rv = SW_OK; - - SW_RTN_ON_NULL(p_api = adpt_api_ptr_get(dev_id)); - - if (NULL == p_api->adpt_port_interface_3az_status_set) - return SW_NOT_SUPPORTED; - - rv = p_api->adpt_port_interface_3az_status_set(dev_id, port_id, enable); - return rv; - -} - -static sw_error_t -_fal_port_interface_3az_status_get(a_uint32_t dev_id, fal_port_t port_id, - a_bool_t * enable) -{ - adpt_api_t *p_api; - sw_error_t rv = SW_OK; - - SW_RTN_ON_NULL(p_api = adpt_api_ptr_get(dev_id)); - - if (NULL == p_api->adpt_port_interface_3az_status_get) - return SW_NOT_SUPPORTED; - - rv = p_api->adpt_port_interface_3az_status_get(dev_id, port_id, enable); - return rv; - -} - -static sw_error_t -_fal_port_promisc_mode_get(a_uint32_t dev_id, fal_port_t port_id, a_bool_t *enable) -{ - sw_error_t rv = SW_OK; - adpt_api_t *p_adpt_api; - - if((p_adpt_api = adpt_api_ptr_get(dev_id)) != NULL) { - if (NULL == p_adpt_api->adpt_port_promisc_mode_get) { - return SW_NOT_SUPPORTED; - } - - rv = p_adpt_api->adpt_port_promisc_mode_get(dev_id, port_id, enable); - return rv; - } - - return rv; -} -#endif - -static sw_error_t -_fal_port_promisc_mode_set(a_uint32_t dev_id, fal_port_t port_id, a_bool_t enable) -{ - sw_error_t rv = SW_OK; - adpt_api_t *p_adpt_api; - - if((p_adpt_api = adpt_api_ptr_get(dev_id)) != NULL) { - if (NULL == p_adpt_api->adpt_port_promisc_mode_set) { - return SW_NOT_SUPPORTED; - } - - rv = p_adpt_api->adpt_port_promisc_mode_set(dev_id, port_id, enable); - return rv; - } - - return rv; -} - -static sw_error_t -_fal_port_interface_eee_cfg_set(a_uint32_t dev_id, fal_port_t port_id, - fal_port_eee_cfg_t *port_eee_cfg) -{ - - adpt_api_t *p_api; - sw_error_t rv = SW_OK; - - SW_RTN_ON_NULL(p_api = adpt_api_ptr_get(dev_id)); - - if (NULL == p_api->adpt_port_interface_eee_cfg_set) - return SW_NOT_SUPPORTED; - - rv = p_api->adpt_port_interface_eee_cfg_set(dev_id, port_id, port_eee_cfg); - return rv; - -} - -static sw_error_t -_fal_port_interface_eee_cfg_get(a_uint32_t dev_id, fal_port_t port_id, - fal_port_eee_cfg_t *port_eee_cfg) -{ - adpt_api_t *p_api; - sw_error_t rv = SW_OK; - - SW_RTN_ON_NULL(p_api = adpt_api_ptr_get(dev_id)); - - if (NULL == p_api->adpt_port_interface_eee_cfg_get) - return SW_NOT_SUPPORTED; - - rv = p_api->adpt_port_interface_eee_cfg_get(dev_id, port_id, port_eee_cfg); - return rv; - -} -static sw_error_t -_fal_switch_port_loopback_set(a_uint32_t dev_id, fal_port_t port_id, - fal_loopback_config_t *loopback_cfg) -{ - - adpt_api_t *p_api; - sw_error_t rv = SW_OK; - - SW_RTN_ON_NULL(p_api = adpt_api_ptr_get(dev_id)); - - if (NULL == p_api->adpt_switch_port_loopback_set) - return SW_NOT_SUPPORTED; - - rv = p_api->adpt_switch_port_loopback_set(dev_id, port_id, loopback_cfg); - return rv; - -} - -static sw_error_t -_fal_switch_port_loopback_get(a_uint32_t dev_id, fal_port_t port_id, - fal_loopback_config_t *loopback_cfg) -{ - adpt_api_t *p_api; - sw_error_t rv = SW_OK; - - SW_RTN_ON_NULL(p_api = adpt_api_ptr_get(dev_id)); - if (NULL == p_api->adpt_switch_port_loopback_get) - return SW_NOT_SUPPORTED; - - rv = p_api->adpt_switch_port_loopback_get(dev_id, port_id, loopback_cfg); - return rv; - -} - -/*qca808x_start*/ -/*insert flag for inner fal, don't remove it*/ -/** - * @brief Set duplex mode on a particular port. - * @param[in] dev_id device id - * @param[in] port_id port id - * @param[in] duplex duplex mode - * @return SW_OK or error code - */ -sw_error_t -fal_port_duplex_set (a_uint32_t dev_id, fal_port_t port_id, - fal_port_duplex_t duplex) -{ - sw_error_t rv; - - FAL_API_LOCK; - rv = _fal_port_duplex_set (dev_id, port_id, duplex); - FAL_API_UNLOCK; - return rv; -} - - - -/** - * @brief Set speed on a particular port. - * @param[in] dev_id device id - * @param[in] port_id port id - * @param[in] speed port speed - * @return SW_OK or error code - */ -sw_error_t -fal_port_speed_set (a_uint32_t dev_id, fal_port_t port_id, - fal_port_speed_t speed) -{ - sw_error_t rv; - - FAL_API_LOCK; - rv = _fal_port_speed_set (dev_id, port_id, speed); - FAL_API_UNLOCK; - return rv; -} -/** - * @brief Get duplex mode on a particular port. - * @param[in] dev_id device id - * @param[in] port_id port id - * @param[out] duplex duplex mode - * @return SW_OK or error code - */ -sw_error_t -fal_port_duplex_get (a_uint32_t dev_id, fal_port_t port_id, - fal_port_duplex_t * pduplex) -{ - sw_error_t rv; - - FAL_API_LOCK; - rv = _fal_port_duplex_get (dev_id, port_id, pduplex); - FAL_API_UNLOCK; - return rv; -} - -/** - * @brief Get speed on a particular port. - * @param[in] dev_id device id - * @param[in] port_id port id - * @param[out] speed port speed - * @return SW_OK or error code - */ -sw_error_t -fal_port_speed_get (a_uint32_t dev_id, fal_port_t port_id, - fal_port_speed_t * pspeed) -{ - sw_error_t rv; - - FAL_API_LOCK; - rv = _fal_port_speed_get (dev_id, port_id, pspeed); - FAL_API_UNLOCK; - return rv; -} - -/** - * @brief Enable auto negotiation status on a particular port. - * @param[in] dev_id device id - * @param[in] port_id port id - * @return SW_OK or error code - */ -sw_error_t -fal_port_autoneg_enable (a_uint32_t dev_id, fal_port_t port_id) -{ - sw_error_t rv; - - FAL_API_LOCK; - rv = _fal_port_autoneg_enable (dev_id, port_id); - FAL_API_UNLOCK; - return rv; -} - -/** - * @brief Restart auto negotiation procedule on a particular port. - * @param[in] dev_id device id - * @param[in] port_id port id - * @return SW_OK or error code - */ -sw_error_t -fal_port_autoneg_restart (a_uint32_t dev_id, fal_port_t port_id) -{ - sw_error_t rv; - - FAL_API_LOCK; - rv = _fal_port_autoneg_restart (dev_id, port_id); - FAL_API_UNLOCK; - return rv; -} - -/** - * @brief Set auto negotiation advtisement ability on a particular port. - * @details Comments: - * auto negotiation advtisement ability is defined by macro such as - * FAL_PHY_ADV_10T_HD, FAL_PHY_ADV_PAUSE... - * @param[in] dev_id device id - * @param[in] port_id port id - * @param[in] autoadv auto negotiation advtisement ability bit map - * @return SW_OK or error code - */ -sw_error_t -fal_port_autoneg_adv_set (a_uint32_t dev_id, fal_port_t port_id, - a_uint32_t autoadv) -{ - sw_error_t rv; - - FAL_API_LOCK; - rv = _fal_port_autoneg_adv_set (dev_id, port_id, autoadv); - FAL_API_UNLOCK; - return rv; -} - -/** - * @brief Get auto negotiation status on a particular port. - * @param[in] dev_id device id - * @param[in] port_id port id - * @param[out] status A_TRUE or A_FALSE - * @return SW_OK or error code - */ -sw_error_t -fal_port_autoneg_status_get (a_uint32_t dev_id, fal_port_t port_id, - a_bool_t * status) -{ - sw_error_t rv; - - FAL_API_LOCK; - rv = _fal_port_autoneg_status_get (dev_id, port_id, status); - FAL_API_UNLOCK; - return rv; -} - -/** - * @brief Get auto negotiation advtisement ability on a particular port. - * @param[in] dev_id device id - * @param[in] port_id port id - * @param[out] autoadv auto negotiation advtisement ability bit map - * @return SW_OK or error code - */ -sw_error_t -fal_port_autoneg_adv_get (a_uint32_t dev_id, fal_port_t port_id, - a_uint32_t * autoadv) -{ - sw_error_t rv; - - FAL_API_LOCK; - rv = _fal_port_autoneg_adv_get (dev_id, port_id, autoadv); - FAL_API_UNLOCK; - return rv; -} -/*qca808x_end*/ -#ifndef IN_PORTCONTROL_MINI -/** - * @brief Set status of Atheros header packets parsed on a particular port. - * @param[in] dev_id device id - * @param[in] port_id port id - * @param[in] enable A_TRUE or A_FALSE - * @return SW_OK or error code - */ -sw_error_t -fal_port_hdr_status_set (a_uint32_t dev_id, fal_port_t port_id, - a_bool_t enable) -{ - sw_error_t rv; - - FAL_API_LOCK; - rv = _fal_port_hdr_status_set (dev_id, port_id, enable); - FAL_API_UNLOCK; - return rv; -} - -/** - * @brief Get status of Atheros header packets parsed on a particular port. - * @param[in] dev_id device id - * @param[in] port_id port id - * @param[out] enable A_TRUE or A_FALSE - * @return SW_OK or error code - */ -sw_error_t -fal_port_hdr_status_get (a_uint32_t dev_id, fal_port_t port_id, - a_bool_t * enable) -{ - sw_error_t rv; - - FAL_API_LOCK; - rv = _fal_port_hdr_status_get (dev_id, port_id, enable); - FAL_API_UNLOCK; - return rv; -} - - -/** - * @brief Get flow control status on a particular port. - * @param[in] dev_id device id - * @param[in] port_id port id - * @param[out] enable A_TRUE or A_FALSE - * @return SW_OK or error code - */ -sw_error_t -fal_port_flowctrl_get (a_uint32_t dev_id, fal_port_t port_id, - a_bool_t * enable) -{ - sw_error_t rv; - - FAL_API_LOCK; - rv = _fal_port_flowctrl_get (dev_id, port_id, enable); - FAL_API_UNLOCK; - return rv; -} - - - -/** - * @brief Get flow control force mode on a particular port. - * @param[in] dev_id device id - * @param[in] port_id port id - * @param[out] enable A_TRUE or A_FALSE - * @return SW_OK or error code - */ -sw_error_t -fal_port_flowctrl_forcemode_get (a_uint32_t dev_id, fal_port_t port_id, - a_bool_t * enable) -{ - sw_error_t rv; - - FAL_API_LOCK; - rv = _fal_port_flowctrl_forcemode_get (dev_id, port_id, enable); - FAL_API_UNLOCK; - return rv; -} - -/** - * @brief Set powersaving status on a particular port. - * @param[in] dev_id device id - * @param[in] port_id port id - * @param[in] enable A_TRUE or A_FALSE - * @return SW_OK or error code - */ -sw_error_t -fal_port_powersave_set (a_uint32_t dev_id, fal_port_t port_id, - a_bool_t enable) -{ - sw_error_t rv; - - FAL_API_LOCK; - rv = _fal_port_powersave_set (dev_id, port_id, enable); - FAL_API_UNLOCK; - return rv; -} - -/** - * @brief Get powersaving status on a particular port. - * @param[in] dev_id device id - * @param[in] port_id port id - * @param[out] enable A_TRUE or A_FALSE - * @return SW_OK or error code - */ -sw_error_t -fal_port_powersave_get (a_uint32_t dev_id, fal_port_t port_id, - a_bool_t * enable) -{ - sw_error_t rv; - - FAL_API_LOCK; - rv = _fal_port_powersave_get (dev_id, port_id, enable); - FAL_API_UNLOCK; - return rv; -} -/*qca808x_start*/ -/** - * @brief Set hibernate status on a particular port. - * @param[in] dev_id device id - * @param[in] port_id port id - * @param[in] enable A_TRUE or A_FALSE - * @return SW_OK or error code - */ -sw_error_t -fal_port_hibernate_set (a_uint32_t dev_id, fal_port_t port_id, - a_bool_t enable) -{ - sw_error_t rv; - - FAL_API_LOCK; - rv = _fal_port_hibernate_set (dev_id, port_id, enable); - FAL_API_UNLOCK; - return rv; -} - -/** - * @brief Get hibernate status on a particular port. - * @param[in] dev_id device id - * @param[in] port_id port id - * @param[out] enable A_TRUE or A_FALSE - * @return SW_OK or error code - */ -sw_error_t -fal_port_hibernate_get (a_uint32_t dev_id, fal_port_t port_id, - a_bool_t * enable) -{ - sw_error_t rv; - - FAL_API_LOCK; - rv = _fal_port_hibernate_get (dev_id, port_id, enable); - FAL_API_UNLOCK; - return rv; -} - -/** - * @brief cable diagnostic test. - * @param[in] dev_id device id - * @param[in] port_id port id - * @param[in] mdi_pair mdi pair id - * @param[out] cable_status cable status - * @param[out] cable_len cable len - * @return SW_OK or error code - */ -sw_error_t -fal_port_cdt (a_uint32_t dev_id, fal_port_t port_id, a_uint32_t mdi_pair, - a_uint32_t * cable_status, a_uint32_t * cable_len) -{ - sw_error_t rv; - - FAL_API_LOCK; - rv = _fal_port_cdt (dev_id, port_id, mdi_pair, cable_status, cable_len); - FAL_API_UNLOCK; - return rv; -} -/*qca808x_end*/ -/** - * @brief Get status of Atheros header packets parsed on a particular port. - * @param[in] dev_id device id - * @param[in] port_id port id - * @param[out] enable A_TRUE or A_FALSE - * @return SW_OK or error code - */ -sw_error_t -fal_port_rxhdr_mode_get (a_uint32_t dev_id, fal_port_t port_id, - fal_port_header_mode_t * mode) -{ - sw_error_t rv; - - FAL_API_LOCK; - rv = _fal_port_rxhdr_mode_get (dev_id, port_id, mode); - FAL_API_UNLOCK; - return rv; -} -/** - * @brief Get status of Atheros header packets parsed on a particular port. - * @param[in] dev_id device id - * @param[in] port_id port id - * @param[out] enable A_TRUE or A_FALSE - * @return SW_OK or error code - */ -sw_error_t -fal_port_txhdr_mode_get (a_uint32_t dev_id, fal_port_t port_id, - fal_port_header_mode_t * mode) -{ - sw_error_t rv; - - FAL_API_LOCK; - rv = _fal_port_txhdr_mode_get (dev_id, port_id, mode); - FAL_API_UNLOCK; - return rv; -} -/** - * @brief Get status of Atheros header type value on a particular device. - * @param[in] dev_id device id - * @param[out] enable A_TRUE or A_FALSE - * @param[out] type header type value - * @return SW_OK or error code - */ -sw_error_t -fal_header_type_get (a_uint32_t dev_id, a_bool_t * enable, a_uint32_t * type) -{ - sw_error_t rv; - - FAL_API_LOCK; - rv = _fal_header_type_get (dev_id, enable, type); - FAL_API_UNLOCK; - return rv; -} -/** - * @brief Get status of txmac on a particular port. - * @param[in] dev_id device id - * @param[in] port_id port id - * @param[out] enable A_TRUE or A_FALSE - * @return SW_OK or error code - */ -sw_error_t -fal_port_txmac_status_get (a_uint32_t dev_id, fal_port_t port_id, - a_bool_t * enable) -{ - sw_error_t rv; - - FAL_API_LOCK; - rv = _fal_port_txmac_status_get (dev_id, port_id, enable); - FAL_API_UNLOCK; - return rv; -} -/** - * @brief Get status of rxmac on a particular port. - * @param[in] dev_id device id - * @param[in] port_id port id - * @param[out] enable A_TRUE or A_FALSE - * @return SW_OK or error code - */ -sw_error_t -fal_port_rxmac_status_get (a_uint32_t dev_id, fal_port_t port_id, - a_bool_t * enable) -{ - sw_error_t rv; - - FAL_API_LOCK; - rv = _fal_port_rxmac_status_get (dev_id, port_id, enable); - FAL_API_UNLOCK; - return rv; -} -#endif -/** - * @brief Set flow control status on a particular port. - * @param[in] dev_id device id - * @param[in] port_id port id - * @param[in] enable A_TRUE or A_FALSE - * @return SW_OK or error code - */ -sw_error_t -fal_port_flowctrl_set (a_uint32_t dev_id, fal_port_t port_id, a_bool_t enable) -{ - sw_error_t rv; - - FAL_API_LOCK; - rv = _fal_port_flowctrl_set (dev_id, port_id, enable); - FAL_API_UNLOCK; - return rv; -} - -/** - * @brief Set flow control force mode on a particular port. - * @param[in] dev_id device id - * @param[in] port_id port id - * @param[in] enable A_TRUE or A_FALSE - * @return SW_OK or error code - */ -sw_error_t -fal_port_flowctrl_forcemode_set (a_uint32_t dev_id, fal_port_t port_id, - a_bool_t enable) -{ - sw_error_t rv; - - FAL_API_LOCK; - rv = _fal_port_flowctrl_forcemode_set (dev_id, port_id, enable); - FAL_API_UNLOCK; - return rv; -} - -/** - * @brief Set status of Atheros header packets parsed on a particular port. - * @param[in] dev_id device id - * @param[in] port_id port id - * @param[in] enable A_TRUE or A_FALSE - * @return SW_OK or error code - */ -sw_error_t -fal_port_rxhdr_mode_set (a_uint32_t dev_id, fal_port_t port_id, - fal_port_header_mode_t mode) -{ - sw_error_t rv; - - FAL_API_LOCK; - rv = _fal_port_rxhdr_mode_set (dev_id, port_id, mode); - FAL_API_UNLOCK; - return rv; -} - - - -/** - * @brief Set status of Atheros header packets parsed on a particular port. - * @param[in] dev_id device id - * @param[in] port_id port id - * @param[in] enable A_TRUE or A_FALSE - * @return SW_OK or error code - */ -sw_error_t -fal_port_txhdr_mode_set (a_uint32_t dev_id, fal_port_t port_id, - fal_port_header_mode_t mode) -{ - sw_error_t rv; - - FAL_API_LOCK; - rv = _fal_port_txhdr_mode_set (dev_id, port_id, mode); - FAL_API_UNLOCK; - return rv; -} - - - -/** - * @brief Set status of Atheros header type value on a particular device. - * @param[in] dev_id device id - * @param[in] enable A_TRUE or A_FALSE - * @param[in] type header type value - * @return SW_OK or error code - */ -sw_error_t -fal_header_type_set (a_uint32_t dev_id, a_bool_t enable, a_uint32_t type) -{ - sw_error_t rv; - FAL_API_LOCK; - rv = _fal_header_type_set (dev_id, enable, type); - FAL_API_UNLOCK; - return rv; -} - - - -/** - * @brief Set status of txmac on a particular port. - * @param[in] dev_id device id - * @param[in] port_id port id - * @param[in] enable A_TRUE or A_FALSE - * @return SW_OK or error code - */ -sw_error_t -fal_port_txmac_status_set (a_uint32_t dev_id, fal_port_t port_id, - a_bool_t enable) -{ - sw_error_t rv; - FAL_API_LOCK; - rv = _fal_port_txmac_status_set (dev_id, port_id, enable); - FAL_API_UNLOCK; - return rv; -} - - - -/** - * @brief Set status of rxmac on a particular port. - * @param[in] dev_id device id - * @param[in] port_id port id - * @param[in] enable A_TRUE or A_FALSE - * @return SW_OK or error code - */ -sw_error_t -fal_port_rxmac_status_set (a_uint32_t dev_id, fal_port_t port_id, - a_bool_t enable) -{ - sw_error_t rv; - FAL_API_LOCK; - rv = _fal_port_rxmac_status_set (dev_id, port_id, enable); - FAL_API_UNLOCK; - return rv; -} - - - -/** - * @brief Set status of tx flow control on a particular port. - * @param[in] dev_id device id - * @param[in] port_id port id - * @param[in] enable A_TRUE or A_FALSE - * @return SW_OK or error code - */ -sw_error_t -fal_port_txfc_status_set (a_uint32_t dev_id, fal_port_t port_id, - a_bool_t enable) -{ - sw_error_t rv; - FAL_API_LOCK; - rv = _fal_port_txfc_status_set (dev_id, port_id, enable); - FAL_API_UNLOCK; - return rv; -} - - - -/** - * @brief Set status of rx flow control on a particular port. - * @param[in] dev_id device id - * @param[in] port_id port id - * @param[in] enable A_TRUE or A_FALSE - * @return SW_OK or error code - */ -sw_error_t -fal_port_rxfc_status_set (a_uint32_t dev_id, fal_port_t port_id, - a_bool_t enable) -{ - sw_error_t rv; - - FAL_API_LOCK; - rv = _fal_port_rxfc_status_set (dev_id, port_id, enable); - FAL_API_UNLOCK; - return rv; -} -/** - * @brief Set status of rx flow control on a particular port. - * @param[in] dev_id device id - * @param[in] port_id port id - * @param[out] enable A_TRUE or A_FALSE - * @return SW_OK or error code - */ -sw_error_t -fal_port_rxfc_status_get (a_uint32_t dev_id, fal_port_t port_id, - a_bool_t * enable) -{ - sw_error_t rv; - - FAL_API_LOCK; - rv = _fal_port_rxfc_status_get (dev_id, port_id, enable); - FAL_API_UNLOCK; - return rv; -} -/** - * @brief Get status of tx flow control on a particular port. - * @param[in] dev_id device id - * @param[in] port_id port id - * @param[out] enable A_TRUE or A_FALSE - * @return SW_OK or error code - */ -sw_error_t -fal_port_txfc_status_get (a_uint32_t dev_id, fal_port_t port_id, - a_bool_t * enable) -{ - sw_error_t rv; - - FAL_API_LOCK; - rv = _fal_port_txfc_status_get (dev_id, port_id, enable); - FAL_API_UNLOCK; - return rv; -} -/*qca808x_start*/ -/** - * @brief Get link status on particular port. - * @param[in] dev_id device id - * @param[in] port_id port id - * @param[out] status link status up (A_TRUE) or down (A_FALSE) - * @return SW_OK or error code - */ -sw_error_t -fal_port_link_status_get (a_uint32_t dev_id, fal_port_t port_id, - a_bool_t * status) -{ - sw_error_t rv; - - FAL_API_LOCK; - rv = _fal_port_link_status_get (dev_id, port_id, status); - FAL_API_UNLOCK; - return rv; -} - -/** - * @brief power off on a particular port. - * @param[in] dev_id device id - * @param[in] port_id port id - * @param[out] - * @return SW_OK or error code - */ -sw_error_t -fal_port_power_off (a_uint32_t dev_id, fal_port_t port_id) -{ - sw_error_t rv; - - FAL_API_LOCK; - rv = _fal_port_power_off (dev_id, port_id); - FAL_API_UNLOCK; - return rv; -} - -/** - * @brief power on on a particular port. - * @param[in] dev_id device id - * @param[in] port_id port id - * @param[out] - * @return SW_OK or error code - */ -sw_error_t -fal_port_power_on (a_uint32_t dev_id, fal_port_t port_id) -{ - sw_error_t rv; - - FAL_API_LOCK; - rv = _fal_port_power_on (dev_id, port_id); - FAL_API_UNLOCK; - return rv; -} -/*qca808x_end*/ -/** - * @brief Set link force mode on a particular port. - * @param[in] dev_id device id - * @param[in] port_id port id - * @param[in] enable A_TRUE or A_FALSE - * @return SW_OK or error code - */ -sw_error_t -fal_port_link_forcemode_set (a_uint32_t dev_id, fal_port_t port_id, - a_bool_t enable) -{ - sw_error_t rv; - - FAL_API_LOCK; - rv = _fal_port_link_forcemode_set (dev_id, port_id, enable); - FAL_API_UNLOCK; - return rv; -} - -/** - * @brief Get link force mode on a particular port. - * @param[in] dev_id device id - * @param[in] port_id port id - * @param[out] enable A_TRUE or A_FALSE - * @return SW_OK or error code - */ -sw_error_t -fal_port_link_forcemode_get (a_uint32_t dev_id, fal_port_t port_id, - a_bool_t * enable) -{ - sw_error_t rv; - - FAL_API_LOCK; - rv = _fal_port_link_forcemode_get (dev_id, port_id, enable); - FAL_API_UNLOCK; - return rv; -} -#ifndef IN_PORTCONTROL_MINI -/** - * @brief Set status of back pressure on a particular port. - * @param[in] dev_id device id - * @param[in] port_id port id - * @param[in] enable A_TRUE or A_FALSE - * @return SW_OK or error code - */ -sw_error_t -fal_port_bp_status_set (a_uint32_t dev_id, fal_port_t port_id, - a_bool_t enable) -{ - sw_error_t rv; - - FAL_API_LOCK; - rv = _fal_port_bp_status_set (dev_id, port_id, enable); - FAL_API_UNLOCK; - return rv; -} - -/** - * @brief Set status of back pressure on a particular port. - * @param[in] dev_id device id - * @param[in] port_id port id - * @param[out] enable A_TRUE or A_FALSE - * @return SW_OK or error code - */ -sw_error_t -fal_port_bp_status_get (a_uint32_t dev_id, fal_port_t port_id, - a_bool_t * enable) -{ - sw_error_t rv; - - FAL_API_LOCK; - rv = _fal_port_bp_status_get (dev_id, port_id, enable); - FAL_API_UNLOCK; - return rv; -} - -/** - * @brief Get link status on all ports. - * @param[in] dev_id device id - * @param[out] status link status bitmap and bit 0 for port 0, bit 1 for port 1, ...etc. - * @return SW_OK or error code - */ -sw_error_t -fal_ports_link_status_get (a_uint32_t dev_id, a_uint32_t * status) -{ - sw_error_t rv; - - FAL_API_LOCK; - rv = _fal_ports_link_status_get (dev_id, status); - FAL_API_UNLOCK; - return rv; -} - - -/** - * @brief Set loopback on a particular port. - * @param[in] dev_id device id - * @param[in] port_id port id - * @param[in] enable A_TRUE or A_FALSE - * @return SW_OK or error code - */ -sw_error_t -fal_port_mac_loopback_set (a_uint32_t dev_id, fal_port_t port_id, - a_bool_t enable) -{ - sw_error_t rv; - - FAL_API_LOCK; - rv = _fal_port_mac_loopback_set (dev_id, port_id, enable); - FAL_API_UNLOCK; - return rv; -} - -/** - * @brief Get link force mode on a particular port. - * @param[in] dev_id device id - * @param[in] port_id port id - * @param[out] enable A_TRUE or A_FALSE - * @return SW_OK or error code - */ -sw_error_t -fal_port_mac_loopback_get (a_uint32_t dev_id, fal_port_t port_id, - a_bool_t * enable) -{ - sw_error_t rv; - - FAL_API_LOCK; - rv = _fal_port_mac_loopback_get (dev_id, port_id, enable); - FAL_API_UNLOCK; - return rv; -} - -/** - * @brief Set congestion drop on a particular port queue. - * @param[in] dev_id device id - * @param[in] port_id port id - * @param[in] enable A_TRUE or A_FALSE - * @return SW_OK or error code - */ -sw_error_t -fal_port_congestion_drop_set (a_uint32_t dev_id, fal_port_t port_id, - a_uint32_t queue_id, a_bool_t enable) -{ - sw_error_t rv; - - FAL_API_LOCK; - rv = _fal_port_congestion_drop_set (dev_id, port_id, queue_id, enable); - FAL_API_UNLOCK; - return rv; -} - -/** - * @brief Get congestion drop on a particular port queue. - * @param[in] dev_id device id - * @param[in] port_id port id - * @param[in] queue_id queue_id - * @param[out] enable A_TRUE or A_FALSE - * @return SW_OK or error code - */ -sw_error_t -fal_port_congestion_drop_get (a_uint32_t dev_id, fal_port_t port_id, - a_uint32_t queue_id, a_bool_t * enable) -{ - sw_error_t rv; - - FAL_API_LOCK; - rv = _fal_port_congestion_drop_get (dev_id, port_id, queue_id, enable); - FAL_API_UNLOCK; - return rv; -} - -/** - * @brief Set flow control threshold on a DMA ring. - * @param[in] dev_id device id - * @param[in] ring_id ring_id - * @param[in] on_thres on_thres - * @param[in] off_thres on_thres - * @return SW_OK or error code - */ -sw_error_t -fal_ring_flow_ctrl_thres_set (a_uint32_t dev_id, a_uint32_t ring_id, - a_uint8_t on_thres, a_uint8_t off_thres) -{ - sw_error_t rv; - - FAL_API_LOCK; - rv = _fal_ring_flow_ctrl_thres_set (dev_id, ring_id, on_thres, off_thres); - FAL_API_UNLOCK; - return rv; -} - -/** - * @brief Get flow control threshold on a DMA ring. - * @param[in] dev_id device id - * @param[in] ring_id ring_id - * @param[out] on_thres on_thres - * @param[out] off_thres on_thres - * @return SW_OK or error code - */ -sw_error_t -fal_ring_flow_ctrl_thres_get (a_uint32_t dev_id, a_uint32_t ring_id, - a_uint8_t * on_thres, a_uint8_t * off_thres) -{ - sw_error_t rv; - - FAL_API_LOCK; - rv = _fal_ring_flow_ctrl_thres_get (dev_id, ring_id, on_thres, off_thres); - FAL_API_UNLOCK; - return rv; -} -/*qca808x_start*/ -/** - * @brief Set 8023az status on a particular port. - * @param[in] dev_id device id - * @param[in] port_id port id - * @param[in] enable A_TRUE or A_FALSE - * @return SW_OK or error code - */ -sw_error_t -fal_port_8023az_set (a_uint32_t dev_id, fal_port_t port_id, a_bool_t enable) -{ - sw_error_t rv; - - FAL_API_LOCK; - rv = _fal_port_8023az_set (dev_id, port_id, enable); - FAL_API_UNLOCK; - return rv; -} - -/** - * @brief Get 8023az status on a particular port. - * @param[in] dev_id device id - * @param[in] port_id port id - * @param[out] enable A_TRUE or A_FALSE - * @return SW_OK or error code - */ -sw_error_t -fal_port_8023az_get (a_uint32_t dev_id, fal_port_t port_id, a_bool_t * enable) -{ - sw_error_t rv; - - FAL_API_LOCK; - rv = _fal_port_8023az_get (dev_id, port_id, enable); - FAL_API_UNLOCK; - return rv; -} - -/** - * @brief Set mdix mode on a particular port. - * @param[in] dev_id device id - * @param[in] port_id port id - * @param[in] set mdix mode [mdx , mdix or auto] - * @return SW_OK or error code - */ -sw_error_t -fal_port_mdix_set (a_uint32_t dev_id, fal_port_t port_id, - fal_port_mdix_mode_t mode) -{ - sw_error_t rv; - - FAL_API_LOCK; - rv = _fal_port_mdix_set (dev_id, port_id, mode); - FAL_API_UNLOCK; - return rv; -} - -/** - * @brief Get mdix on a particular port. - * @param[in] dev_id device id - * @param[in] port_id port id - * @param[out] set mdx ,mdix or auto - * @return SW_OK or error code - */ -sw_error_t -fal_port_mdix_get (a_uint32_t dev_id, fal_port_t port_id, - fal_port_mdix_mode_t * mode) -{ - sw_error_t rv; - - FAL_API_LOCK; - rv = _fal_port_mdix_get (dev_id, port_id, mode); - FAL_API_UNLOCK; - return rv; -} - -/** - * @brief Get mdix status on a particular port. - * @param[in] dev_id device id - * @param[in] port_id port id - * @param[out] set mdx ,mdix - * @return SW_OK or error code - */ -sw_error_t -fal_port_mdix_status_get (a_uint32_t dev_id, fal_port_t port_id, - fal_port_mdix_status_t * mode) -{ - sw_error_t rv; - - FAL_API_LOCK; - rv = _fal_port_mdix_status_get (dev_id, port_id, mode); - FAL_API_UNLOCK; - return rv; -} -/*qca808x_end*/ -/** - * @brief Set combo prefer medium on a particular port. - * @param[in] dev_id device id - * @param[in] port_id port id - * @param[in] set combo prefer medium [fiber for copper] - * @return SW_OK or error code - */ -sw_error_t -fal_port_combo_prefer_medium_set (a_uint32_t dev_id, a_uint32_t port_id, - fal_port_medium_t medium) -{ - sw_error_t rv; - - FAL_API_LOCK; - rv = _fal_port_combo_prefer_medium_set (dev_id, port_id, medium); - FAL_API_UNLOCK; - return rv; -} - -/** - * @brief Get combo prefer medium on a particular port. - * @param[in] dev_id device id - * @param[in] port_id port id - * @param[in] set combo prefer medium [fiber for copper] - * @return SW_OK or error code - */ -sw_error_t -fal_port_combo_prefer_medium_get (a_uint32_t dev_id, a_uint32_t port_id, - fal_port_medium_t * medium) -{ - sw_error_t rv; - - FAL_API_LOCK; - rv = _fal_port_combo_prefer_medium_get (dev_id, port_id, medium); - FAL_API_UNLOCK; - return rv; -} - -/** - * @brief Get combo medium status on a particular port. - * @param[in] dev_id device id - * @param[in] port_id port id - * @param[in] get combo [fiber for copper] - * @return SW_OK or error code - */ -sw_error_t -fal_port_combo_medium_status_get (a_uint32_t dev_id, a_uint32_t port_id, - fal_port_medium_t * medium) -{ - sw_error_t rv; - - FAL_API_LOCK; - rv = _fal_port_combo_medium_status_get (dev_id, port_id, medium); - FAL_API_UNLOCK; - return rv; -} - -/** - * @brief Set combo fiber mode on a particular port. - * @param[in] dev_id device id - * @param[in] port_id port id - * @param[in] get combo fiber mode [1000bx or 100fx] - * @return SW_OK or error code - */ -sw_error_t -fal_port_combo_fiber_mode_set (a_uint32_t dev_id, a_uint32_t port_id, - fal_port_fiber_mode_t mode) -{ - sw_error_t rv; - - FAL_API_LOCK; - rv = _fal_port_combo_fiber_mode_set (dev_id, port_id, mode); - FAL_API_UNLOCK; - return rv; -} - -/** - * @brief Get combo fiber mode on a particular port. - * @param[in] dev_id device id - * @param[in] port_id port id - * @param[in] get combo fiber mode [1000bx or 100fx] - * @return SW_OK or error code - */ -sw_error_t -fal_port_combo_fiber_mode_get (a_uint32_t dev_id, a_uint32_t port_id, - fal_port_fiber_mode_t * mode) -{ - sw_error_t rv; - - FAL_API_LOCK; - rv = _fal_port_combo_fiber_mode_get (dev_id, port_id, mode); - FAL_API_UNLOCK; - return rv; -} -/*qca808x_start*/ -/** - * @brief Set local loopback on a particular port. - * @param[in] dev_id device id - * @param[in] port_id port id - * @param[in] enable A_TRUE or A_FALSE - * @return SW_OK or error code - */ -sw_error_t -fal_port_local_loopback_set (a_uint32_t dev_id, fal_port_t port_id, - a_bool_t enable) -{ - sw_error_t rv; - - FAL_API_LOCK; - rv = _fal_port_local_loopback_set (dev_id, port_id, enable); - FAL_API_UNLOCK; - return rv; -} - -/** - * @brief Get local loopback status on a particular port. - * @param[in] dev_id device id - * @param[in] port_id port id - * @param[out] enable A_TRUE or A_FALSE - * @return SW_OK or error code - */ -sw_error_t -fal_port_local_loopback_get (a_uint32_t dev_id, fal_port_t port_id, - a_bool_t * enable) -{ - sw_error_t rv; - - FAL_API_LOCK; - rv = _fal_port_local_loopback_get (dev_id, port_id, enable); - FAL_API_UNLOCK; - return rv; -} - -/** - * @brief Set remote loopback on a particular port. - * @param[in] dev_id device id - * @param[in] port_id port id - * @param[in] enable A_TRUE or A_FALSE - * @return SW_OK or error code - */ -sw_error_t -fal_port_remote_loopback_set (a_uint32_t dev_id, fal_port_t port_id, - a_bool_t enable) -{ - sw_error_t rv; - - FAL_API_LOCK; - rv = _fal_port_remote_loopback_set (dev_id, port_id, enable); - FAL_API_UNLOCK; - return rv; -} - -/** - * @brief Get remote loopback status on a particular port. - * @param[in] dev_id device id - * @param[in] port_id port id - * @param[out] enable A_TRUE or A_FALSE - * @return SW_OK or error code - */ -sw_error_t -fal_port_remote_loopback_get (a_uint32_t dev_id, fal_port_t port_id, - a_bool_t * enable) -{ - sw_error_t rv; - - FAL_API_LOCK; - rv = _fal_port_remote_loopback_get (dev_id, port_id, enable); - FAL_API_UNLOCK; - return rv; -} - -/** - * @brief software reset on a particular port. - * @param[in] dev_id device id - * @param[in] port_id port id - * @param[out] - * @return SW_OK or error code - */ -sw_error_t -fal_port_reset (a_uint32_t dev_id, fal_port_t port_id) -{ - sw_error_t rv; - - FAL_API_LOCK; - rv = _fal_port_reset (dev_id, port_id); - FAL_API_UNLOCK; - return rv; -} - -/** - * @brief phy id on a particular port. - * @param[in] dev_id device id - * @param[in] port_id port id - * @param[out] - * @return SW_OK or error code - */ -sw_error_t -fal_port_phy_id_get (a_uint32_t dev_id, fal_port_t port_id, a_uint16_t * org_id, a_uint16_t * rev_id) -{ - sw_error_t rv; - - FAL_API_LOCK; - rv = _fal_port_phy_id_get (dev_id, port_id,org_id,rev_id); - FAL_API_UNLOCK; - return rv; -} - -/** - * @brief wol status on a particular port. - * @param[in] dev_id device id - * @param[in] port_id port id - * @param[out] - * @return SW_OK or error code - */ -sw_error_t -fal_port_wol_status_set (a_uint32_t dev_id, fal_port_t port_id, a_bool_t enable) -{ - sw_error_t rv; - - FAL_API_LOCK; - rv = _fal_port_wol_status_set (dev_id, port_id,enable); - FAL_API_UNLOCK; - return rv; -} - -/** - * @brief wol status on a particular port. - * @param[in] dev_id device id - * @param[in] port_id port id - * @param[out] - * @return SW_OK or error code - */ -sw_error_t -fal_port_wol_status_get (a_uint32_t dev_id, fal_port_t port_id, a_bool_t *enable) -{ - sw_error_t rv; - - FAL_API_LOCK; - rv = _fal_port_wol_status_get (dev_id, port_id,enable); - FAL_API_UNLOCK; - return rv; -} - -/** - * @brief magic frame mac on a particular port. - * @param[in] dev_id device id - * @param[in] port_id port id - * @param[out] - * @return SW_OK or error code - */ -sw_error_t -fal_port_magic_frame_mac_set (a_uint32_t dev_id, fal_port_t port_id, fal_mac_addr_t * mac) -{ - sw_error_t rv; - - FAL_API_LOCK; - rv = _fal_port_magic_frame_mac_set (dev_id, port_id,mac); - FAL_API_UNLOCK; - return rv; -} - -/** - * @brief magic frame mac on a particular port. - * @param[in] dev_id device id - * @param[in] port_id port id - * @param[out] - * @return SW_OK or error code - */ -sw_error_t -fal_port_magic_frame_mac_get (a_uint32_t dev_id, fal_port_t port_id, fal_mac_addr_t * mac) -{ - sw_error_t rv; - - FAL_API_LOCK; - rv = _fal_port_magic_frame_mac_get (dev_id, port_id,mac); - FAL_API_UNLOCK; - return rv; -} -/*qca808x_end*/ -/** - * @brief interface mode on a particular port. - * @param[in] dev_id device id - * @param[in] port_id port id - * @param[out] - * @return SW_OK or error code - */ -sw_error_t -fal_port_interface_mode_set (a_uint32_t dev_id, fal_port_t port_id, fal_port_interface_mode_t mode) -{ - sw_error_t rv; - - FAL_API_LOCK; - rv = _fal_port_interface_mode_set (dev_id, port_id,mode); - FAL_API_UNLOCK; - return rv; -} - -/** - * @brief interface mode on a particular port. - * @param[in] dev_id device id - * @return SW_OK or error code - */ - static sw_error_t -_fal_port_interface_mode_apply (a_uint32_t dev_id) -{ - sw_error_t rv = SW_OK; - adpt_api_t *p_adpt_api; - - if((p_adpt_api = adpt_api_ptr_get(dev_id)) != NULL) { - if (NULL == p_adpt_api->adpt_port_interface_mode_apply) - return SW_NOT_SUPPORTED; - - rv = p_adpt_api->adpt_port_interface_mode_apply(dev_id); - return rv; - } - - return rv; -} - -sw_error_t -fal_port_interface_mode_apply (a_uint32_t dev_id) -{ - sw_error_t rv = SW_OK; - - FAL_API_LOCK; - rv = _fal_port_interface_mode_apply (dev_id); - FAL_API_UNLOCK; - return rv; -} - -/** - * @brief interface mode on a particular port. - * @param[in] dev_id device id - * @param[in] port_id port id - * @param[out] - * @return SW_OK or error code - */ -sw_error_t -fal_port_interface_mode_get (a_uint32_t dev_id, fal_port_t port_id, fal_port_interface_mode_t * mode) -{ - sw_error_t rv = SW_OK; - - FAL_API_LOCK; - rv = _fal_port_interface_mode_get (dev_id, port_id,mode); - FAL_API_UNLOCK; - return rv; -} -/*qca808x_start*/ -/** - * @brief interface mode status on a particular port. - * @param[in] dev_id device id - * @param[in] port_id port id - * @param[out] - * @return SW_OK or error code - */ -sw_error_t -fal_port_interface_mode_status_get (a_uint32_t dev_id, fal_port_t port_id, fal_port_interface_mode_t * mode) -{ - sw_error_t rv; - - FAL_API_LOCK; - rv = _fal_port_interface_mode_status_get (dev_id, port_id,mode); - FAL_API_UNLOCK; - return rv; -} - -/** - * @brief Set counter status on a particular port. - * @param[in] dev_id device id - * @param[in] port_id port id - * @param[in] enable A_TRUE or A_FALSE - * @return SW_OK or error code - */ -sw_error_t -fal_debug_phycounter_set (a_uint32_t dev_id, fal_port_t port_id, a_bool_t enable) -{ - sw_error_t rv; - - FAL_API_LOCK; - rv = _fal_port_counter_set (dev_id, port_id, enable); - FAL_API_UNLOCK; - return rv; -} - -/** - * @brief Get counter status on a particular port. - * @param[in] dev_id device id - * @param[in] port_id port id - * @param[out] enable A_TRUE or A_FALSE - * @return SW_OK or error code - */ -sw_error_t -fal_debug_phycounter_get (a_uint32_t dev_id, fal_port_t port_id, a_bool_t * enable) -{ - sw_error_t rv; - - FAL_API_LOCK; - rv = _fal_port_counter_get (dev_id, port_id, enable); - FAL_API_UNLOCK; - return rv; -} - -/** - * @brief Get counter statistics on a particular port. - * @param[in] dev_id device id - * @param[in] port_id port id - * @param[out] counter frame number - * @return SW_OK or error code - */ -sw_error_t -fal_debug_phycounter_show (a_uint32_t dev_id, fal_port_t port_id, fal_port_counter_info_t* port_counter_info) -{ - sw_error_t rv; - - FAL_API_LOCK; - rv = _fal_port_counter_show (dev_id, port_id, port_counter_info); - FAL_API_UNLOCK; - return rv; -} -/*qca808x_end*/ -#endif - -sw_error_t -fal_port_max_frame_size_set(a_uint32_t dev_id, fal_port_t port_id, - a_uint32_t max_frame) -{ - sw_error_t rv = SW_OK; - - FAL_API_LOCK; - rv = _fal_port_max_frame_size_set(dev_id, port_id, max_frame); - FAL_API_UNLOCK; - return rv; -} - -sw_error_t -fal_port_max_frame_size_get(a_uint32_t dev_id, fal_port_t port_id, - a_uint32_t *max_frame) -{ - sw_error_t rv = SW_OK; - - FAL_API_LOCK; - rv = _fal_port_max_frame_size_get(dev_id, port_id, max_frame); - FAL_API_UNLOCK; - return rv; -} - -#ifndef IN_PORTCONTROL_MINI -sw_error_t -fal_port_mru_set(a_uint32_t dev_id, fal_port_t port_id, - fal_mru_ctrl_t *ctrl) -{ - sw_error_t rv = SW_OK; - - FAL_API_LOCK; - rv = _fal_port_mru_set(dev_id, port_id, ctrl); - FAL_API_UNLOCK; - return rv; -} -sw_error_t -fal_port_mru_get(a_uint32_t dev_id, fal_port_t port_id, - fal_mru_ctrl_t *ctrl) -{ - sw_error_t rv = SW_OK; - - FAL_API_LOCK; - rv = _fal_port_mru_get(dev_id, port_id, ctrl); - FAL_API_UNLOCK; - return rv; -} -sw_error_t -fal_port_mtu_set(a_uint32_t dev_id, fal_port_t port_id, - fal_mtu_ctrl_t *ctrl) -{ - sw_error_t rv = SW_OK; - - FAL_API_LOCK; - rv = _fal_port_mtu_set(dev_id, port_id, ctrl); - FAL_API_UNLOCK; - return rv; -} -sw_error_t -fal_port_mtu_get(a_uint32_t dev_id, fal_port_t port_id, - fal_mtu_ctrl_t *ctrl) -{ - sw_error_t rv = SW_OK; - - FAL_API_LOCK; - rv = _fal_port_mtu_get(dev_id, port_id, ctrl); - FAL_API_UNLOCK; - return rv; -} - -sw_error_t -fal_port_source_filter_status_get(a_uint32_t dev_id, - fal_port_t port_id, a_bool_t * enable) -{ - sw_error_t rv = SW_OK; - - FAL_API_LOCK; - rv = _fal_port_source_filter_get(dev_id, - port_id, enable); - FAL_API_UNLOCK; - return rv; -} - -sw_error_t -fal_port_source_filter_enable(a_uint32_t dev_id, - fal_port_t port_id, a_bool_t enable) -{ - sw_error_t rv = SW_OK; - - FAL_API_LOCK; - rv = _fal_port_source_filter_set(dev_id, - port_id, enable); - FAL_API_UNLOCK; - return rv; -} - -sw_error_t -fal_port_source_filter_config_set(a_uint32_t dev_id, - fal_port_t port_id, fal_src_filter_config_t *src_filter_config) -{ - sw_error_t rv = SW_OK; - - FAL_API_LOCK; - rv = _fal_port_source_filter_config_set(dev_id, port_id, src_filter_config); - FAL_API_UNLOCK; - return rv; -} - -sw_error_t -fal_port_source_filter_config_get(a_uint32_t dev_id, - fal_port_t port_id, fal_src_filter_config_t *src_filter_config) -{ - sw_error_t rv = SW_OK; - - FAL_API_LOCK; - rv = _fal_port_source_filter_config_get(dev_id, port_id, src_filter_config); - FAL_API_UNLOCK; - return rv; -} - -sw_error_t -fal_port_interface_3az_status_set(a_uint32_t dev_id, fal_port_t port_id, - a_bool_t enable) -{ - sw_error_t rv; - - FAL_API_LOCK; - rv = _fal_port_interface_3az_status_set(dev_id, port_id, enable); - FAL_API_UNLOCK; - return rv; -} -sw_error_t -fal_port_interface_3az_status_get(a_uint32_t dev_id, fal_port_t port_id, - a_bool_t * enable) -{ - sw_error_t rv; - - FAL_API_LOCK; - rv = _fal_port_interface_3az_status_get(dev_id, port_id, enable); - FAL_API_UNLOCK; - return rv; -} - -sw_error_t -fal_port_promisc_mode_get(a_uint32_t dev_id, fal_port_t port_id, a_bool_t *enable) -{ - sw_error_t rv = SW_OK; - - FAL_API_LOCK; - rv = _fal_port_promisc_mode_get(dev_id, port_id, enable); - FAL_API_UNLOCK; - return rv; -} -#endif - -sw_error_t -fal_port_promisc_mode_set(a_uint32_t dev_id, fal_port_t port_id, a_bool_t enable) -{ - sw_error_t rv = SW_OK; - - FAL_API_LOCK; - rv = _fal_port_promisc_mode_set(dev_id, port_id, enable); - FAL_API_UNLOCK; - return rv; -} - -sw_error_t -fal_port_interface_eee_cfg_set(a_uint32_t dev_id, fal_port_t port_id, - fal_port_eee_cfg_t *port_eee_cfg) -{ - sw_error_t rv = SW_OK; - - FAL_API_LOCK; - rv = _fal_port_interface_eee_cfg_set(dev_id, port_id, port_eee_cfg); - FAL_API_UNLOCK; - return rv; -} - -sw_error_t -fal_port_interface_eee_cfg_get(a_uint32_t dev_id, fal_port_t port_id, - fal_port_eee_cfg_t *port_eee_cfg) -{ - sw_error_t rv = SW_OK; - - FAL_API_LOCK; - rv = _fal_port_interface_eee_cfg_get(dev_id, port_id, port_eee_cfg); - FAL_API_UNLOCK; - return rv; -} - -sw_error_t -fal_switch_port_loopback_set(a_uint32_t dev_id, fal_port_t port_id, - fal_loopback_config_t *loopback_cfg) -{ - sw_error_t rv = SW_OK; - - FAL_API_LOCK; - rv = _fal_switch_port_loopback_set(dev_id, port_id, loopback_cfg); - FAL_API_UNLOCK; - return rv; -} - -sw_error_t -fal_switch_port_loopback_get(a_uint32_t dev_id, fal_port_t port_id, - fal_loopback_config_t *loopback_cfg) -{ - sw_error_t rv = SW_OK; - - FAL_API_LOCK; - rv = _fal_switch_port_loopback_get(dev_id, port_id, loopback_cfg); - FAL_API_UNLOCK; - return rv; -} - -/*insert flag for outter fal, don't remove it*/ -/** - * @} - */ - #ifndef IN_PORTCONTROL_MINI -EXPORT_SYMBOL(fal_port_mtu_set); -EXPORT_SYMBOL(fal_port_mtu_get); -EXPORT_SYMBOL(fal_port_mru_set); -EXPORT_SYMBOL(fal_port_mru_get); -#endif -EXPORT_SYMBOL(fal_port_duplex_set); -EXPORT_SYMBOL(fal_port_duplex_get); -EXPORT_SYMBOL(fal_port_speed_set); -EXPORT_SYMBOL(fal_port_speed_get); -EXPORT_SYMBOL(fal_port_autoneg_status_get); -EXPORT_SYMBOL(fal_port_autoneg_enable); -EXPORT_SYMBOL(fal_port_autoneg_restart); -EXPORT_SYMBOL(fal_port_autoneg_adv_set); -EXPORT_SYMBOL(fal_port_autoneg_adv_get); -EXPORT_SYMBOL(fal_port_flowctrl_set); -#ifndef IN_PORTCONTROL_MINI -EXPORT_SYMBOL(fal_port_flowctrl_get); -EXPORT_SYMBOL(fal_port_powersave_set); -EXPORT_SYMBOL(fal_port_powersave_get); -EXPORT_SYMBOL(fal_port_hibernate_set); -EXPORT_SYMBOL(fal_port_hibernate_get); -EXPORT_SYMBOL(fal_port_cdt); -EXPORT_SYMBOL(fal_port_txmac_status_get); -#endif -EXPORT_SYMBOL(fal_port_txmac_status_set); -EXPORT_SYMBOL(fal_port_rxmac_status_set); -#ifndef IN_PORTCONTROL_MINI -EXPORT_SYMBOL(fal_port_rxmac_status_get); -#endif -EXPORT_SYMBOL(fal_port_txfc_status_set); -EXPORT_SYMBOL(fal_port_txfc_status_get); -EXPORT_SYMBOL(fal_port_rxfc_status_set); -EXPORT_SYMBOL(fal_port_rxfc_status_get); -#ifndef IN_PORTCONTROL_MINI -EXPORT_SYMBOL(fal_port_bp_status_set); -EXPORT_SYMBOL(fal_port_bp_status_get); -#endif -EXPORT_SYMBOL(fal_port_link_status_get); -#ifndef IN_PORTCONTROL_MINI -EXPORT_SYMBOL(fal_ports_link_status_get); -EXPORT_SYMBOL(fal_port_mac_loopback_set); -EXPORT_SYMBOL(fal_port_mac_loopback_get); -EXPORT_SYMBOL(fal_port_8023az_set); -EXPORT_SYMBOL(fal_port_8023az_get); -EXPORT_SYMBOL(fal_port_mdix_set); -EXPORT_SYMBOL(fal_port_mdix_get); -EXPORT_SYMBOL(fal_port_mdix_status_get); -EXPORT_SYMBOL(fal_port_combo_prefer_medium_set); -EXPORT_SYMBOL(fal_port_combo_prefer_medium_get); -EXPORT_SYMBOL(fal_port_combo_medium_status_get); -EXPORT_SYMBOL(fal_port_combo_fiber_mode_set); -EXPORT_SYMBOL(fal_port_combo_fiber_mode_get); -EXPORT_SYMBOL(fal_port_local_loopback_set); -EXPORT_SYMBOL(fal_port_local_loopback_get); -EXPORT_SYMBOL(fal_port_remote_loopback_set); -EXPORT_SYMBOL(fal_port_remote_loopback_get); -EXPORT_SYMBOL(fal_port_reset); -#endif -EXPORT_SYMBOL(fal_port_power_off); -EXPORT_SYMBOL(fal_port_power_on); -#ifndef IN_PORTCONTROL_MINI -EXPORT_SYMBOL(fal_port_magic_frame_mac_set ); -EXPORT_SYMBOL(fal_port_magic_frame_mac_get ); -EXPORT_SYMBOL(fal_port_phy_id_get ); -EXPORT_SYMBOL(fal_port_wol_status_set ); -EXPORT_SYMBOL(fal_port_wol_status_get ); -EXPORT_SYMBOL(fal_port_interface_mode_set); -EXPORT_SYMBOL(fal_port_interface_mode_apply); - -EXPORT_SYMBOL(fal_port_interface_mode_get ); -EXPORT_SYMBOL(fal_port_interface_mode_status_get ); -EXPORT_SYMBOL(fal_port_source_filter_enable); -EXPORT_SYMBOL(fal_port_source_filter_status_get); -EXPORT_SYMBOL(fal_port_source_filter_config_get); -EXPORT_SYMBOL(fal_port_source_filter_config_set); -#endif -EXPORT_SYMBOL(fal_port_max_frame_size_set); -EXPORT_SYMBOL(fal_port_max_frame_size_get); -#ifndef IN_PORTCONTROL_MINI -EXPORT_SYMBOL(fal_port_interface_3az_status_set); -EXPORT_SYMBOL(fal_port_interface_3az_status_get); -#endif -EXPORT_SYMBOL(fal_port_flowctrl_forcemode_set); -#ifndef IN_PORTCONTROL_MINI -EXPORT_SYMBOL(fal_port_flowctrl_forcemode_get); -EXPORT_SYMBOL(fal_port_promisc_mode_set); -EXPORT_SYMBOL(fal_port_promisc_mode_get); -#endif -EXPORT_SYMBOL(fal_port_interface_eee_cfg_set); -EXPORT_SYMBOL(fal_port_interface_eee_cfg_get); -EXPORT_SYMBOL(fal_switch_port_loopback_set); -EXPORT_SYMBOL(fal_switch_port_loopback_get); - diff --git a/feeds/ipq807x/qca-ssdk/src/src/fal/fal_portvlan.c b/feeds/ipq807x/qca-ssdk/src/src/fal/fal_portvlan.c deleted file mode 100755 index 0b82accd5..000000000 --- a/feeds/ipq807x/qca-ssdk/src/src/fal/fal_portvlan.c +++ /dev/null @@ -1,2550 +0,0 @@ -/* - * Copyright (c) 2012, 2016-2017, The Linux Foundation. All rights reserved. - * Permission to use, copy, modify, and/or distribute this software for - * any purpose with or without fee is hereby granted, provided that the - * above copyright notice and this permission notice appear in all copies. - * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES - * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR - * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES - * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN - * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT - * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. - */ - - -/** - * @defgroup fal_port_vlan FAL_PORT_VLAN - * @{ - */ -#include "sw.h" -#include "fal_portvlan.h" -#include "hsl_api.h" -#include "adpt.h" - -#include -#include - -static sw_error_t -_fal_port_1qmode_set(a_uint32_t dev_id, fal_port_t port_id, - fal_pt_1qmode_t port_1qmode) -{ - sw_error_t rv; - hsl_api_t *p_api; - - SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id)); - - if (NULL == p_api->port_1qmode_set) - return SW_NOT_SUPPORTED; - - rv = p_api->port_1qmode_set(dev_id, port_id, port_1qmode); - return rv; -} - - - - - -static sw_error_t -_fal_port_egvlanmode_set(a_uint32_t dev_id, fal_port_t port_id, - fal_pt_1q_egmode_t port_egvlanmode) -{ - sw_error_t rv; - hsl_api_t *p_api; - - SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id)); - - if (NULL == p_api->port_egvlanmode_set) - return SW_NOT_SUPPORTED; - - rv = p_api->port_egvlanmode_set(dev_id, port_id, port_egvlanmode); - return rv; -} - - - -static sw_error_t -_fal_portvlan_member_add(a_uint32_t dev_id, fal_port_t port_id, - a_uint32_t mem_port_id) -{ - sw_error_t rv; - hsl_api_t *p_api; - adpt_api_t *p_adpt_api; - - if((p_adpt_api = adpt_api_ptr_get(dev_id)) != NULL) { - if (NULL == p_adpt_api->adpt_portvlan_member_add) - return SW_NOT_SUPPORTED; - - rv = p_adpt_api->adpt_portvlan_member_add(dev_id, port_id, mem_port_id); - return rv; - } - - - SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id)); - - if (NULL == p_api->portvlan_member_add) - return SW_NOT_SUPPORTED; - - rv = p_api->portvlan_member_add(dev_id, port_id, mem_port_id); - return rv; -} - - -static sw_error_t -_fal_portvlan_member_del(a_uint32_t dev_id, fal_port_t port_id, - a_uint32_t mem_port_id) -{ - sw_error_t rv; - hsl_api_t *p_api; - adpt_api_t *p_adpt_api; - - if((p_adpt_api = adpt_api_ptr_get(dev_id)) != NULL) { - if (NULL == p_adpt_api->adpt_portvlan_member_del) - return SW_NOT_SUPPORTED; - - rv = p_adpt_api->adpt_portvlan_member_del(dev_id, port_id, mem_port_id); - return rv; - } - - - SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id)); - - if (NULL == p_api->portvlan_member_del) - return SW_NOT_SUPPORTED; - - rv = p_api->portvlan_member_del(dev_id, port_id, mem_port_id); - return rv; -} - - -static sw_error_t -_fal_portvlan_member_update(a_uint32_t dev_id, fal_port_t port_id, - fal_pbmp_t mem_port_map) -{ - sw_error_t rv; - hsl_api_t *p_api; - adpt_api_t *p_adpt_api; - - if((p_adpt_api = adpt_api_ptr_get(dev_id)) != NULL) { - if (NULL == p_adpt_api->adpt_portvlan_member_update) - return SW_NOT_SUPPORTED; - - rv = p_adpt_api->adpt_portvlan_member_update(dev_id, port_id, mem_port_map); - return rv; - } - - - SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id)); - - if (NULL == p_api->portvlan_member_update) - return SW_NOT_SUPPORTED; - - rv = p_api->portvlan_member_update(dev_id, port_id, mem_port_map); - return rv; -} - - - -static sw_error_t -_fal_port_default_vid_set(a_uint32_t dev_id, fal_port_t port_id, a_uint32_t vid) -{ - sw_error_t rv; - hsl_api_t *p_api; - - SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id)); - - if (NULL == p_api->port_default_vid_set) - return SW_NOT_SUPPORTED; - - rv = p_api->port_default_vid_set(dev_id, port_id, vid); - return rv; -} - - - -static sw_error_t -_fal_port_force_default_vid_set(a_uint32_t dev_id, fal_port_t port_id, - a_bool_t enable) -{ - sw_error_t rv; - hsl_api_t *p_api; - - SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id)); - - if (NULL == p_api->port_force_default_vid_set) - return SW_NOT_SUPPORTED; - - rv = p_api->port_force_default_vid_set(dev_id, port_id, enable); - return rv; -} - - -static sw_error_t -_fal_port_force_portvlan_set(a_uint32_t dev_id, fal_port_t port_id, - a_bool_t enable) -{ - sw_error_t rv; - hsl_api_t *p_api; - - SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id)); - - if (NULL == p_api->port_force_portvlan_set) - return SW_NOT_SUPPORTED; - - rv = p_api->port_force_portvlan_set(dev_id, port_id, enable); - return rv; -} - - - - -static sw_error_t -_fal_port_nestvlan_set(a_uint32_t dev_id, fal_port_t port_id, a_bool_t enable) -{ - sw_error_t rv; - hsl_api_t *p_api; - - SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id)); - - if (NULL == p_api->port_nestvlan_set) - return SW_NOT_SUPPORTED; - - rv = p_api->port_nestvlan_set(dev_id, port_id, enable); - return rv; -} - - - - - -static sw_error_t -_fal_nestvlan_tpid_set(a_uint32_t dev_id, a_uint32_t tpid) -{ - sw_error_t rv; - hsl_api_t *p_api; - - SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id)); - - if (NULL == p_api->nestvlan_tpid_set) - return SW_NOT_SUPPORTED; - - rv = p_api->nestvlan_tpid_set(dev_id, tpid); - return rv; -} - - - -static sw_error_t -_fal_port_invlan_mode_set(a_uint32_t dev_id, fal_port_t port_id, - fal_pt_invlan_mode_t mode) -{ - sw_error_t rv; - hsl_api_t *p_api; - adpt_api_t *p_adpt_api; - - if((p_adpt_api = adpt_api_ptr_get(dev_id)) != NULL) { - if (NULL == p_adpt_api->adpt_port_invlan_mode_set) - return SW_NOT_SUPPORTED; - - rv = p_adpt_api->adpt_port_invlan_mode_set(dev_id, port_id, mode); - return rv; - } - - SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id)); - - if (NULL == p_api->port_invlan_mode_set) - return SW_NOT_SUPPORTED; - - rv = p_api->port_invlan_mode_set(dev_id, port_id, mode); - return rv; -} -static sw_error_t -_fal_port_tls_set(a_uint32_t dev_id, fal_port_t port_id, - a_bool_t enable) -{ - sw_error_t rv; - hsl_api_t *p_api; - - SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id)); - - if (NULL == p_api->port_tls_set) - return SW_NOT_SUPPORTED; - - rv = p_api->port_tls_set(dev_id, port_id, enable); - return rv; -} - -#ifndef IN_PORTVLAN_MINI -static sw_error_t -_fal_port_invlan_mode_get(a_uint32_t dev_id, fal_port_t port_id, - fal_pt_invlan_mode_t * mode) -{ - sw_error_t rv; - hsl_api_t *p_api; - adpt_api_t *p_adpt_api; - - if((p_adpt_api = adpt_api_ptr_get(dev_id)) != NULL) { - if (NULL == p_adpt_api->adpt_port_invlan_mode_get) - return SW_NOT_SUPPORTED; - - rv = p_adpt_api->adpt_port_invlan_mode_get(dev_id, port_id, mode); - return rv; - } - - SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id)); - - if (NULL == p_api->port_invlan_mode_get) - return SW_NOT_SUPPORTED; - - rv = p_api->port_invlan_mode_get(dev_id, port_id, mode); - return rv; -} -static sw_error_t -_fal_nestvlan_tpid_get(a_uint32_t dev_id, a_uint32_t * tpid) -{ - sw_error_t rv; - hsl_api_t *p_api; - - SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id)); - - if (NULL == p_api->nestvlan_tpid_get) - return SW_NOT_SUPPORTED; - - rv = p_api->nestvlan_tpid_get(dev_id, tpid); - return rv; -} -static sw_error_t -_fal_port_nestvlan_get(a_uint32_t dev_id, fal_port_t port_id, a_bool_t * enable) -{ - sw_error_t rv; - hsl_api_t *p_api; - - SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id)); - - if (NULL == p_api->port_nestvlan_get) - return SW_NOT_SUPPORTED; - - rv = p_api->port_nestvlan_get(dev_id, port_id, enable); - return rv; -} -static sw_error_t -_fal_port_force_portvlan_get(a_uint32_t dev_id, fal_port_t port_id, - a_bool_t * enable) -{ - sw_error_t rv; - hsl_api_t *p_api; - - SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id)); - - if (NULL == p_api->port_force_portvlan_get) - return SW_NOT_SUPPORTED; - - rv = p_api->port_force_portvlan_get(dev_id, port_id, enable); - return rv; -} -static sw_error_t -_fal_port_force_default_vid_get(a_uint32_t dev_id, fal_port_t port_id, - a_bool_t * enable) -{ - sw_error_t rv; - hsl_api_t *p_api; - - SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id)); - - if (NULL == p_api->port_force_default_vid_get) - return SW_NOT_SUPPORTED; - - rv = p_api->port_force_default_vid_get(dev_id, port_id, enable); - return rv; -} - -static sw_error_t -_fal_port_default_vid_get(a_uint32_t dev_id, fal_port_t port_id, - a_uint32_t * vid) -{ - sw_error_t rv; - hsl_api_t *p_api; - - SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id)); - - if (NULL == p_api->port_default_vid_get) - return SW_NOT_SUPPORTED; - - rv = p_api->port_default_vid_get(dev_id, port_id, vid); - return rv; -} - -static sw_error_t -_fal_port_1qmode_get(a_uint32_t dev_id, fal_port_t port_id, - fal_pt_1qmode_t * pport_1qmode) -{ - sw_error_t rv; - hsl_api_t *p_api; - - SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id)); - - if (NULL == p_api->port_1qmode_get) - return SW_NOT_SUPPORTED; - - rv = p_api->port_1qmode_get(dev_id, port_id, pport_1qmode); - return rv; -} -static sw_error_t -_fal_port_egvlanmode_get(a_uint32_t dev_id, fal_port_t port_id, - fal_pt_1q_egmode_t * pport_egvlanmode) -{ - sw_error_t rv; - hsl_api_t *p_api; - - SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id)); - - if (NULL == p_api->port_egvlanmode_get) - return SW_NOT_SUPPORTED; - - rv = p_api->port_egvlanmode_get(dev_id, port_id, pport_egvlanmode); - return rv; -} - -static sw_error_t -_fal_portvlan_member_get(a_uint32_t dev_id, fal_port_t port_id, - fal_pbmp_t * mem_port_map) -{ - sw_error_t rv; - hsl_api_t *p_api; - adpt_api_t *p_adpt_api; - - if((p_adpt_api = adpt_api_ptr_get(dev_id)) != NULL) { - if (NULL == p_adpt_api->adpt_portvlan_member_get) - return SW_NOT_SUPPORTED; - - rv = p_adpt_api->adpt_portvlan_member_get(dev_id, port_id, mem_port_map); - return rv; - } - - - SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id)); - - if (NULL == p_api->portvlan_member_get) - return SW_NOT_SUPPORTED; - - rv = p_api->portvlan_member_get(dev_id, port_id, mem_port_map); - return rv; -} - - - -static sw_error_t -_fal_port_tls_get(a_uint32_t dev_id, fal_port_t port_id, - a_bool_t * enable) -{ - sw_error_t rv; - hsl_api_t *p_api; - - SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id)); - - if (NULL == p_api->port_tls_get) - return SW_NOT_SUPPORTED; - - rv = p_api->port_tls_get(dev_id, port_id, enable); - return rv; -} - -static sw_error_t -_fal_port_pri_propagation_set(a_uint32_t dev_id, fal_port_t port_id, - a_bool_t enable) -{ - sw_error_t rv; - hsl_api_t *p_api; - - SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id)); - - if (NULL == p_api->port_pri_propagation_set) - return SW_NOT_SUPPORTED; - - rv = p_api->port_pri_propagation_set(dev_id, port_id, enable); - return rv; -} - -static sw_error_t -_fal_port_pri_propagation_get(a_uint32_t dev_id, fal_port_t port_id, - a_bool_t * enable) -{ - sw_error_t rv; - hsl_api_t *p_api; - - SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id)); - - if (NULL == p_api->port_pri_propagation_get) - return SW_NOT_SUPPORTED; - - rv = p_api->port_pri_propagation_get(dev_id, port_id, enable); - return rv; -} -#endif -static sw_error_t -_fal_port_default_svid_set(a_uint32_t dev_id, fal_port_t port_id, - a_uint32_t vid) -{ - sw_error_t rv; - hsl_api_t *p_api; - - SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id)); - - if (NULL == p_api->port_default_svid_set) - return SW_NOT_SUPPORTED; - - rv = p_api->port_default_svid_set(dev_id, port_id, vid); - return rv; -} - - - -static sw_error_t -_fal_port_default_cvid_set(a_uint32_t dev_id, fal_port_t port_id, - a_uint32_t vid) -{ - sw_error_t rv; - hsl_api_t *p_api; - - SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id)); - - if (NULL == p_api->port_default_cvid_set) - return SW_NOT_SUPPORTED; - - rv = p_api->port_default_cvid_set(dev_id, port_id, vid); - return rv; -} - - - -static sw_error_t -_fal_port_vlan_propagation_set(a_uint32_t dev_id, fal_port_t port_id, - fal_vlan_propagation_mode_t mode) -{ - sw_error_t rv; - hsl_api_t *p_api; - - SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id)); - - if (NULL == p_api->port_vlan_propagation_set) - return SW_NOT_SUPPORTED; - - rv = p_api->port_vlan_propagation_set(dev_id, port_id, mode); - return rv; -} -#ifndef IN_PORTVLAN_MINI -static sw_error_t -_fal_port_default_cvid_get(a_uint32_t dev_id, fal_port_t port_id, - a_uint32_t * vid) -{ - sw_error_t rv; - hsl_api_t *p_api; - - SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id)); - - if (NULL == p_api->port_default_cvid_get) - return SW_NOT_SUPPORTED; - - rv = p_api->port_default_cvid_get(dev_id, port_id, vid); - return rv; -} -static sw_error_t -_fal_port_default_svid_get(a_uint32_t dev_id, fal_port_t port_id, - a_uint32_t * vid) -{ - sw_error_t rv; - hsl_api_t *p_api; - - SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id)); - - if (NULL == p_api->port_default_svid_get) - return SW_NOT_SUPPORTED; - - rv = p_api->port_default_svid_get(dev_id, port_id, vid); - return rv; -} - -static sw_error_t -_fal_port_vlan_propagation_get(a_uint32_t dev_id, fal_port_t port_id, - fal_vlan_propagation_mode_t * mode) -{ - sw_error_t rv; - hsl_api_t *p_api; - - SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id)); - - if (NULL == p_api->port_vlan_propagation_get) - return SW_NOT_SUPPORTED; - - rv = p_api->port_vlan_propagation_get(dev_id, port_id, mode); - return rv; -} -#endif - -static sw_error_t -_fal_port_vlan_trans_add(a_uint32_t dev_id, fal_port_t port_id, fal_vlan_trans_entry_t *entry) -{ - sw_error_t rv; - hsl_api_t *p_api; - adpt_api_t *p_adpt_api; - - if((p_adpt_api = adpt_api_ptr_get(dev_id)) != NULL) { - if (NULL == p_adpt_api->adpt_port_vlan_trans_add) - return SW_NOT_SUPPORTED; - - rv = p_adpt_api->adpt_port_vlan_trans_add(dev_id, port_id, entry); - return rv; - } - - SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id)); - - if (NULL == p_api->port_vlan_trans_add) - return SW_NOT_SUPPORTED; - - rv = p_api->port_vlan_trans_add(dev_id, port_id, entry); - return rv; -} - -#ifndef IN_PORTVLAN_MINI -static sw_error_t -_fal_port_vlan_trans_del(a_uint32_t dev_id, fal_port_t port_id, fal_vlan_trans_entry_t *entry) -{ - sw_error_t rv; - hsl_api_t *p_api; - adpt_api_t *p_adpt_api; - - if((p_adpt_api = adpt_api_ptr_get(dev_id)) != NULL) { - if (NULL == p_adpt_api->adpt_port_vlan_trans_del) - return SW_NOT_SUPPORTED; - - rv = p_adpt_api->adpt_port_vlan_trans_del(dev_id, port_id, entry); - return rv; - } - - SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id)); - - if (NULL == p_api->port_vlan_trans_del) - return SW_NOT_SUPPORTED; - - rv = p_api->port_vlan_trans_del(dev_id, port_id, entry); - return rv; -} - -static sw_error_t -_fal_port_vlan_trans_get(a_uint32_t dev_id, fal_port_t port_id, fal_vlan_trans_entry_t *entry) -{ - sw_error_t rv; - hsl_api_t *p_api; - adpt_api_t *p_adpt_api; - - if((p_adpt_api = adpt_api_ptr_get(dev_id)) != NULL) { - if (NULL == p_adpt_api->adpt_port_vlan_trans_get) - return SW_NOT_SUPPORTED; - - rv = p_adpt_api->adpt_port_vlan_trans_get(dev_id, port_id, entry); - return rv; - } - - SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id)); - - if (NULL == p_api->port_vlan_trans_get) - return SW_NOT_SUPPORTED; - - rv = p_api->port_vlan_trans_get(dev_id, port_id, entry); - return rv; -} -#endif - -static sw_error_t -_fal_qinq_mode_set(a_uint32_t dev_id, fal_qinq_mode_t mode) -{ - sw_error_t rv; - hsl_api_t *p_api; - adpt_api_t *p_adpt_api; - - if((p_adpt_api = adpt_api_ptr_get(dev_id)) != NULL) { - if (NULL == p_adpt_api->adpt_qinq_mode_set) - return SW_NOT_SUPPORTED; - - rv = p_adpt_api->adpt_qinq_mode_set(dev_id, mode); - return rv; - } - - SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id)); - - if (NULL == p_api->qinq_mode_set) - return SW_NOT_SUPPORTED; - - rv = p_api->qinq_mode_set(dev_id, mode); - return rv; -} - -#ifndef IN_PORTVLAN_MINI -static sw_error_t -_fal_qinq_mode_get(a_uint32_t dev_id, fal_qinq_mode_t * mode) -{ - sw_error_t rv; - hsl_api_t *p_api; - adpt_api_t *p_adpt_api; - - if((p_adpt_api = adpt_api_ptr_get(dev_id)) != NULL) { - if (NULL == p_adpt_api->adpt_qinq_mode_get) - return SW_NOT_SUPPORTED; - - rv = p_adpt_api->adpt_qinq_mode_get(dev_id, mode); - return rv; - } - - SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id)); - - if (NULL == p_api->qinq_mode_get) - return SW_NOT_SUPPORTED; - - rv = p_api->qinq_mode_get(dev_id, mode); - return rv; -} -#endif - -static sw_error_t -_fal_port_qinq_role_set(a_uint32_t dev_id, fal_port_t port_id, fal_qinq_port_role_t role) -{ - sw_error_t rv; - hsl_api_t *p_api; - adpt_api_t *p_adpt_api; - - if((p_adpt_api = adpt_api_ptr_get(dev_id)) != NULL) { - if (NULL == p_adpt_api->adpt_port_qinq_role_set) - return SW_NOT_SUPPORTED; - - rv = p_adpt_api->adpt_port_qinq_role_set(dev_id, port_id, role); - return rv; - } - - SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id)); - - if (NULL == p_api->port_qinq_role_set) - return SW_NOT_SUPPORTED; - - rv = p_api->port_qinq_role_set(dev_id, port_id, role); - return rv; -} - -#ifndef IN_PORTVLAN_MINI -static sw_error_t -_fal_port_qinq_role_get(a_uint32_t dev_id, fal_port_t port_id, fal_qinq_port_role_t * role) -{ - sw_error_t rv; - hsl_api_t *p_api; - adpt_api_t *p_adpt_api; - - if((p_adpt_api = adpt_api_ptr_get(dev_id)) != NULL) { - if (NULL == p_adpt_api->adpt_port_qinq_role_get) - return SW_NOT_SUPPORTED; - - rv = p_adpt_api->adpt_port_qinq_role_get(dev_id, port_id, role); - return rv; - } - - SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id)); - - if (NULL == p_api->port_qinq_role_get) - return SW_NOT_SUPPORTED; - - rv = p_api->port_qinq_role_get(dev_id, port_id, role); - return rv; -} - -static sw_error_t -_fal_port_vlan_trans_iterate(a_uint32_t dev_id, fal_port_t port_id, - a_uint32_t * iterator, fal_vlan_trans_entry_t *entry) -{ - sw_error_t rv; - adpt_api_t *p_adpt_api; - hsl_api_t *p_api; - - if((p_adpt_api = adpt_api_ptr_get(dev_id)) != NULL) { - if (NULL == p_adpt_api->adpt_port_vlan_trans_iterate) - return SW_NOT_SUPPORTED; - - rv = p_adpt_api->adpt_port_vlan_trans_iterate(dev_id, port_id, iterator, entry); - return rv; - } - - SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id)); - - if (NULL == p_api->port_vlan_trans_iterate) - return SW_NOT_SUPPORTED; - - rv = p_api->port_vlan_trans_iterate(dev_id, port_id, iterator, entry); - return rv; -} - -static sw_error_t -_fal_port_mac_vlan_xlt_set(a_uint32_t dev_id, fal_port_t port_id, - a_bool_t enable) -{ - sw_error_t rv; - hsl_api_t *p_api; - - SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id)); - - if (NULL == p_api->port_mac_vlan_xlt_set) - return SW_NOT_SUPPORTED; - - rv = p_api->port_mac_vlan_xlt_set(dev_id, port_id, enable); - return rv; -} - -static sw_error_t -_fal_port_mac_vlan_xlt_get(a_uint32_t dev_id, fal_port_t port_id, - a_bool_t * enable) -{ - sw_error_t rv; - hsl_api_t *p_api; - - SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id)); - - if (NULL == p_api->port_mac_vlan_xlt_get) - return SW_NOT_SUPPORTED; - - rv = p_api->port_mac_vlan_xlt_get(dev_id, port_id, enable); - return rv; -} - -static sw_error_t -_fal_netisolate_set(a_uint32_t dev_id, a_uint32_t enable) -{ - sw_error_t rv; - hsl_api_t *p_api; - - SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id)); - - if (NULL == p_api->netisolate_set) - return SW_NOT_SUPPORTED; - - rv = p_api->netisolate_set(dev_id, enable); - return rv; -} - -static sw_error_t -_fal_netisolate_get(a_uint32_t dev_id, a_uint32_t * enable) -{ - sw_error_t rv; - hsl_api_t *p_api; - - SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id)); - - if (NULL == p_api->netisolate_get) - return SW_NOT_SUPPORTED; - - rv = p_api->netisolate_get(dev_id, enable); - return rv; -} - -static sw_error_t -_fal_eg_trans_filter_bypass_en_set(a_uint32_t dev_id, a_uint32_t enable) -{ - sw_error_t rv; - hsl_api_t *p_api; - - SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id)); - - if (NULL == p_api->eg_trans_filter_bypass_en_set) - return SW_NOT_SUPPORTED; - - rv = p_api->eg_trans_filter_bypass_en_set(dev_id, enable); - return rv; -} - -static sw_error_t -_fal_eg_trans_filter_bypass_en_get(a_uint32_t dev_id, a_uint32_t* enable) -{ - sw_error_t rv; - hsl_api_t *p_api; - - SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id)); - - if (NULL == p_api->eg_trans_filter_bypass_en_set) - return SW_NOT_SUPPORTED; - - rv = p_api->eg_trans_filter_bypass_en_get(dev_id, enable); - return rv; -} - -static sw_error_t -_fal_port_vrf_id_set(a_uint32_t dev_id, fal_port_t port_id, - a_uint32_t vrf_id) -{ - sw_error_t rv; - hsl_api_t *p_api; - - SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id)); - - if (NULL == p_api->port_vrf_id_set) - return SW_NOT_SUPPORTED; - - rv = p_api->port_vrf_id_set(dev_id, port_id, vrf_id); - return rv; -} - -static sw_error_t -_fal_port_vrf_id_get(a_uint32_t dev_id, fal_port_t port_id, - a_uint32_t * vrf_id) -{ - sw_error_t rv; - hsl_api_t *p_api; - - SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id)); - - if (NULL == p_api->port_vrf_id_get) - return SW_NOT_SUPPORTED; - - rv = p_api->port_vrf_id_get(dev_id, port_id, vrf_id); - return rv; -} -#endif -/** - * @brief Set 802.1q work mode on a particular port. - * @param[in] dev_id device id - * @param[in] port_id port id - * @param[in] port_1qmode 802.1q work mode - * @return SW_OK or error code - */ -sw_error_t -fal_port_1qmode_set(a_uint32_t dev_id, fal_port_t port_id, - fal_pt_1qmode_t port_1qmode) -{ - sw_error_t rv; - - FAL_API_LOCK; - rv = _fal_port_1qmode_set(dev_id, port_id, port_1qmode); - FAL_API_UNLOCK; - return rv; -} -#ifndef IN_PORTVLAN_MINI -/** - * @brief Get 802.1q work mode on a particular port. - * @param[in] dev_id device id - * @param[in] port_id port id - * @param[out] port_1qmode 802.1q work mode - * @return SW_OK or error code - */ -sw_error_t -fal_port_1qmode_get(a_uint32_t dev_id, fal_port_t port_id, - fal_pt_1qmode_t * pport_1qmode) -{ - sw_error_t rv; - - FAL_API_LOCK; - rv = _fal_port_1qmode_get(dev_id, port_id, pport_1qmode); - FAL_API_UNLOCK; - return rv; -} -#endif -/** - * @brief Set packets transmitted out vlan tagged mode on a particular port. - * @param[in] dev_id device id - * @param[in] port_id port id - * @param[in] port_egvlanmode packets transmitted out vlan tagged mode - * @return SW_OK or error code - */ -sw_error_t -fal_port_egvlanmode_set(a_uint32_t dev_id, fal_port_t port_id, - fal_pt_1q_egmode_t port_egvlanmode) -{ - sw_error_t rv; - - FAL_API_LOCK; - rv = _fal_port_egvlanmode_set(dev_id, port_id, port_egvlanmode); - FAL_API_UNLOCK; - return rv; -} -#ifndef IN_PORTVLAN_MINI -/** - * @brief Get packets transmitted out vlan tagged mode on a particular port. - * @param[in] dev_id device id - * @param[in] port_id port id - * @param[out] port_egvlanmode packets transmitted out vlan tagged mode - * @return SW_OK or error code - */ -sw_error_t -fal_port_egvlanmode_get(a_uint32_t dev_id, fal_port_t port_id, - fal_pt_1q_egmode_t * pport_egvlanmode) -{ - sw_error_t rv; - - FAL_API_LOCK; - rv = _fal_port_egvlanmode_get(dev_id, port_id, pport_egvlanmode); - FAL_API_UNLOCK; - return rv; -} -#endif -/** - * @brief Add member of port based vlan on a particular port. - * @param[in] dev_id device id - * @param[in] port_id port id - * @param[in] mem_port_id port member - * @return SW_OK or error code - */ -sw_error_t -fal_portvlan_member_add(a_uint32_t dev_id, fal_port_t port_id, - a_uint32_t mem_port_id) -{ - sw_error_t rv; - - FAL_API_LOCK; - rv = _fal_portvlan_member_add(dev_id, port_id, mem_port_id); - FAL_API_UNLOCK; - return rv; -} - -/** - * @brief Delete member of port based vlan on a particular port. - * @param[in] dev_id device id - * @param[in] port_id port id - * @param[in] mem_port_id port member - * @return SW_OK or error code - */ -sw_error_t -fal_portvlan_member_del(a_uint32_t dev_id, fal_port_t port_id, - a_uint32_t mem_port_id) -{ - sw_error_t rv; - - FAL_API_LOCK; - rv = _fal_portvlan_member_del(dev_id, port_id, mem_port_id); - FAL_API_UNLOCK; - return rv; -} - -/** - * @brief Update member of port based vlan on a particular port. - * @param[in] dev_id device id - * @param[in] port_id port id - * @param[in] mem_port_map port members - * @return SW_OK or error code - */ -sw_error_t -fal_portvlan_member_update(a_uint32_t dev_id, fal_port_t port_id, - fal_pbmp_t mem_port_map) -{ - sw_error_t rv; - - FAL_API_LOCK; - rv = _fal_portvlan_member_update(dev_id, port_id, mem_port_map); - FAL_API_UNLOCK; - return rv; -} -#ifndef IN_PORTVLAN_MINI -/** - * @brief Get member of port based vlan on a particular port. - * @param[in] dev_id device id - * @param[in] port_id port id - * @param[out] mem_port_map port members - * @return SW_OK or error code - */ -sw_error_t -fal_portvlan_member_get(a_uint32_t dev_id, fal_port_t port_id, - fal_pbmp_t * mem_port_map) -{ - sw_error_t rv; - - FAL_API_LOCK; - rv = _fal_portvlan_member_get(dev_id, port_id, mem_port_map); - FAL_API_UNLOCK; - return rv; -} -#endif -/** - * @brief Set default vlan id on a particular port. - * @param[in] dev_id device id - * @param[in] port_id port id - * @param[in] vid default vlan id - * @return SW_OK or error code - */ -sw_error_t -fal_port_default_vid_set(a_uint32_t dev_id, fal_port_t port_id, a_uint32_t vid) -{ - sw_error_t rv; - - FAL_API_LOCK; - rv = _fal_port_default_vid_set(dev_id, port_id, vid); - FAL_API_UNLOCK; - return rv; -} -#ifndef IN_PORTVLAN_MINI -/** - * @brief Get default vlan id on a particular port. - * @param[in] dev_id device id - * @param[in] port_id port id - * @param[out] vid default vlan id - * @return SW_OK or error code - */ -sw_error_t -fal_port_default_vid_get(a_uint32_t dev_id, fal_port_t port_id, - a_uint32_t * vid) -{ - sw_error_t rv; - - FAL_API_LOCK; - rv = _fal_port_default_vid_get(dev_id, port_id, vid); - FAL_API_UNLOCK; - return rv; -} -#endif -/** - * @brief Set force default vlan id status on a particular port. - * @param[in] dev_id device id - * @param[in] port_id port id - * @param[in] enable A_TRUE or A_FALSE - * @return SW_OK or error code - */ -sw_error_t -fal_port_force_default_vid_set(a_uint32_t dev_id, fal_port_t port_id, - a_bool_t enable) -{ - sw_error_t rv; - - FAL_API_LOCK; - rv = _fal_port_force_default_vid_set(dev_id, port_id, enable); - FAL_API_UNLOCK; - return rv; -} -#ifndef IN_PORTVLAN_MINI -/** - * @brief Get force default vlan id status on a particular port. - * @param[in] dev_id device id - * @param[in] port_id port id - * @param[out] enable A_TRUE or A_FALSE - * @return SW_OK or error code - */ -sw_error_t -fal_port_force_default_vid_get(a_uint32_t dev_id, fal_port_t port_id, - a_bool_t * enable) -{ - sw_error_t rv; - - FAL_API_LOCK; - rv = _fal_port_force_default_vid_get(dev_id, port_id, enable); - FAL_API_UNLOCK; - return rv; -} -#endif -/** - * @brief Set force port based vlan status on a particular port. - * @param[in] dev_id device id - * @param[in] port_id port id - * @param[in] enable A_TRUE or A_FALSE - * @return SW_OK or error code - */ -sw_error_t -fal_port_force_portvlan_set(a_uint32_t dev_id, fal_port_t port_id, - a_bool_t enable) -{ - sw_error_t rv; - - FAL_API_LOCK; - rv = _fal_port_force_portvlan_set(dev_id, port_id, enable); - FAL_API_UNLOCK; - return rv; -} -#ifndef IN_PORTVLAN_MINI -/** - * @brief Get force port based vlan status on a particular port. - * @param[in] dev_id device id - * @param[in] port_id port id - * @param[out] enable A_TRUE or A_FALSE - * @return SW_OK or error code - */ -sw_error_t -fal_port_force_portvlan_get(a_uint32_t dev_id, fal_port_t port_id, - a_bool_t * enable) -{ - sw_error_t rv; - - FAL_API_LOCK; - rv = _fal_port_force_portvlan_get(dev_id, port_id, enable); - FAL_API_UNLOCK; - return rv; -} -#endif -/** - * @brief Set nest vlan feature status on a particular port. - * @param[in] dev_id device id - * @param[in] port_id port id - * @param[in] enable A_TRUE or A_FALSE - * @return SW_OK or error code - */ -sw_error_t -fal_port_nestvlan_set(a_uint32_t dev_id, fal_port_t port_id, a_bool_t enable) -{ - sw_error_t rv; - - FAL_API_LOCK; - rv = _fal_port_nestvlan_set(dev_id, port_id, enable); - FAL_API_UNLOCK; - return rv; -} -#ifndef IN_PORTVLAN_MINI -/** - * @brief Get nest vlan feature status on a particular port. - * @param[in] dev_id device id - * @param[in] port_id port id - * @param[out] enable A_TRUE or A_FALSE - * @return SW_OK or error code - */ -sw_error_t -fal_port_nestvlan_get(a_uint32_t dev_id, fal_port_t port_id, a_bool_t * enable) -{ - sw_error_t rv; - - FAL_API_LOCK; - rv = _fal_port_nestvlan_get(dev_id, port_id, enable); - FAL_API_UNLOCK; - return rv; -} -#endif -/** - * @brief Set nest vlan tpid on a particular device. - * @param[in] dev_id device id - * @param[in] tpid tag protocol identification - * @return SW_OK or error code - */ -sw_error_t -fal_nestvlan_tpid_set(a_uint32_t dev_id, a_uint32_t tpid) -{ - sw_error_t rv; - - FAL_API_LOCK; - rv = _fal_nestvlan_tpid_set(dev_id, tpid); - FAL_API_UNLOCK; - return rv; -} -#ifndef IN_PORTVLAN_MINI -/** - * @brief Get nest vlan tpid on a particular device. - * @param[in] dev_id device id - * @param[out] tpid tag protocol identification - * @return SW_OK or error code - */ -sw_error_t -fal_nestvlan_tpid_get(a_uint32_t dev_id, a_uint32_t * tpid) -{ - sw_error_t rv; - - FAL_API_LOCK; - rv = _fal_nestvlan_tpid_get(dev_id, tpid); - FAL_API_UNLOCK; - return rv; -} -#endif -/** - * @brief Set ingress vlan mode mode on a particular port. - * @param[in] dev_id device id - * @param[in] port_id port id - * @param[in] mode ingress vlan mode - * @return SW_OK or error code - */ -sw_error_t -fal_port_invlan_mode_set(a_uint32_t dev_id, fal_port_t port_id, - fal_pt_invlan_mode_t mode) -{ - sw_error_t rv; - - FAL_API_LOCK; - rv = _fal_port_invlan_mode_set(dev_id, port_id, mode); - FAL_API_UNLOCK; - return rv; -} -#ifndef IN_PORTVLAN_MINI -/** - * @brief Get ingress vlan mode mode on a particular port. - * @param[in] dev_id device id - * @param[in] port_id port id - * @param[out] mode ingress vlan mode - * @return SW_OK or error code - */ -sw_error_t -fal_port_invlan_mode_get(a_uint32_t dev_id, fal_port_t port_id, - fal_pt_invlan_mode_t * mode) -{ - sw_error_t rv; - - FAL_API_LOCK; - rv = _fal_port_invlan_mode_get(dev_id, port_id, mode); - FAL_API_UNLOCK; - return rv; -} -#endif -/** - * @brief Set tls status on a particular port. - * @param[in] dev_id device id - * @param[in] port_id port id - * @param[in] enable A_TRUE or A_FALSE - * @return SW_OK or error code - */ -sw_error_t -fal_port_tls_set(a_uint32_t dev_id, fal_port_t port_id, - a_bool_t enable) -{ - sw_error_t rv; - - FAL_API_LOCK; - rv = _fal_port_tls_set(dev_id, port_id, enable); - FAL_API_UNLOCK; - return rv; -} -#ifndef IN_PORTVLAN_MINI - - -/** - * @brief Get tls status on a particular port. - * @param[in] dev_id device id - * @param[in] port_id port id - * @param[out] enable A_TRUE or A_FALSE - * @return SW_OK or error code - */ -sw_error_t -fal_port_tls_get(a_uint32_t dev_id, fal_port_t port_id, - a_bool_t * enable) -{ - sw_error_t rv; - - FAL_API_LOCK; - rv = _fal_port_tls_get(dev_id, port_id, enable); - FAL_API_UNLOCK; - return rv; -} - -/** - * @brief Set priority propagation status on a particular port. - * @param[in] dev_id device id - * @param[in] port_id port id - * @param[in] enable A_TRUE or A_FALSE - * @return SW_OK or error code - */ -sw_error_t -fal_port_pri_propagation_set(a_uint32_t dev_id, fal_port_t port_id, - a_bool_t enable) -{ - sw_error_t rv; - - FAL_API_LOCK; - rv = _fal_port_pri_propagation_set(dev_id, port_id, enable); - FAL_API_UNLOCK; - return rv; -} - -/** - * @brief Get priority propagation status on a particular port. - * @param[in] dev_id device id - * @param[in] port_id port id - * @param[out] enable A_TRUE or A_FALSE - * @return SW_OK or error code - */ -sw_error_t -fal_port_pri_propagation_get(a_uint32_t dev_id, fal_port_t port_id, - a_bool_t * enable) -{ - sw_error_t rv; - - FAL_API_LOCK; - rv = _fal_port_pri_propagation_get(dev_id, port_id, enable); - FAL_API_UNLOCK; - return rv; -} -#endif -/** - * @brief Set default s-vid on a particular port. - * @param[in] dev_id device id - * @param[in] port_id port id - * @param[in] vid s-vid - * @return SW_OK or error code - */ -sw_error_t -fal_port_default_svid_set(a_uint32_t dev_id, fal_port_t port_id, - a_uint32_t vid) -{ - sw_error_t rv; - - FAL_API_LOCK; - rv = _fal_port_default_svid_set(dev_id, port_id, vid); - FAL_API_UNLOCK; - return rv; -} -#ifndef IN_PORTVLAN_MINI -/** - * @brief Get default s-vid on a particular port. - * @param[in] dev_id device id - * @param[in] port_id port id - * @param[out] vid s-vid - * @return SW_OK or error code - */ -sw_error_t -fal_port_default_svid_get(a_uint32_t dev_id, fal_port_t port_id, - a_uint32_t * vid) -{ - sw_error_t rv; - - FAL_API_LOCK; - rv = _fal_port_default_svid_get(dev_id, port_id, vid); - FAL_API_UNLOCK; - return rv; -} -#endif -/** - * @brief Set default c-vid on a particular port. - * @param[in] dev_id device id - * @param[in] port_id port id - * @param[in] vid c-vid - * @return SW_OK or error code - */ -sw_error_t -fal_port_default_cvid_set(a_uint32_t dev_id, fal_port_t port_id, - a_uint32_t vid) -{ - sw_error_t rv; - - FAL_API_LOCK; - rv = _fal_port_default_cvid_set(dev_id, port_id, vid); - FAL_API_UNLOCK; - return rv; -} -#ifndef IN_PORTVLAN_MINI -/** - * @brief Get default c-vid on a particular port. - * @param[in] dev_id device id - * @param[in] port_id port id - * @param[out] vid c-vid - * @return SW_OK or error code - */ -sw_error_t -fal_port_default_cvid_get(a_uint32_t dev_id, fal_port_t port_id, - a_uint32_t * vid) -{ - sw_error_t rv; - - FAL_API_LOCK; - rv = _fal_port_default_cvid_get(dev_id, port_id, vid); - FAL_API_UNLOCK; - return rv; -} -#endif -/** - * @brief Set vlan propagation status on a particular port. - * @param[in] dev_id device id - * @param[in] port_id port id - * @param[in] mode vlan propagation mode - * @return SW_OK or error code - */ -sw_error_t -fal_port_vlan_propagation_set(a_uint32_t dev_id, fal_port_t port_id, - fal_vlan_propagation_mode_t mode) -{ - sw_error_t rv; - - FAL_API_LOCK; - rv = _fal_port_vlan_propagation_set(dev_id, port_id, mode); - FAL_API_UNLOCK; - return rv; -} -#ifndef IN_PORTVLAN_MINI - - -/** - * @brief Get vlan propagation status on a particular port. - * @param[in] dev_id device id - * @param[in] port_id port id - * @param[out] mode vlan propagation mode - * @return SW_OK or error code - */ -sw_error_t -fal_port_vlan_propagation_get(a_uint32_t dev_id, fal_port_t port_id, - fal_vlan_propagation_mode_t * mode) -{ - sw_error_t rv; - - FAL_API_LOCK; - rv = _fal_port_vlan_propagation_get(dev_id, port_id, mode); - FAL_API_UNLOCK; - return rv; -} -#endif - -/** - * @brief Add a vlan translation entry to a particular port. - * @param[in] dev_id device id - * @param[in] port_id port id - * @param entry vlan translation entry - * @return SW_OK or error code - */ -sw_error_t -fal_port_vlan_trans_add(a_uint32_t dev_id, fal_port_t port_id, fal_vlan_trans_entry_t *entry) -{ - sw_error_t rv; - - FAL_API_LOCK; - rv = _fal_port_vlan_trans_add(dev_id, port_id, entry); - FAL_API_UNLOCK; - return rv; -} - -#ifndef IN_PORTVLAN_MINI -/** - * @brief Delete a vlan translation entry from a particular port. - * @param[in] dev_id device id - * @param[in] port_id port id - * @param entry vlan translation entry - * @return SW_OK or error code - */ -sw_error_t -fal_port_vlan_trans_del(a_uint32_t dev_id, fal_port_t port_id, fal_vlan_trans_entry_t *entry) -{ - sw_error_t rv; - - FAL_API_LOCK; - rv = _fal_port_vlan_trans_del(dev_id, port_id, entry); - FAL_API_UNLOCK; - return rv; -} - -/** - * @brief Get a vlan translation entry from a particular port. - * @param[in] dev_id device id - * @param[in] port_id port id - * @param entry vlan translation entry - * @return SW_OK or error code - */ -sw_error_t -fal_port_vlan_trans_get(a_uint32_t dev_id, fal_port_t port_id, fal_vlan_trans_entry_t *entry) -{ - sw_error_t rv; - - FAL_API_LOCK; - rv = _fal_port_vlan_trans_get(dev_id, port_id, entry); - FAL_API_UNLOCK; - return rv; -} -#endif - -/** - * @brief Set switch qinq work mode on a particular device. - * @param[in] dev_id device id - * @param[in] mode qinq work mode - * @return SW_OK or error code - */ -sw_error_t -fal_qinq_mode_set(a_uint32_t dev_id, fal_qinq_mode_t mode) -{ - sw_error_t rv; - - FAL_API_LOCK; - rv = _fal_qinq_mode_set(dev_id, mode); - FAL_API_UNLOCK; - return rv; -} - -#ifndef IN_PORTVLAN_MINI -/** - * @brief Get switch qinq work mode on a particular device. - * @param[in] dev_id device id - * @param[out] mode qinq work mode - * @return SW_OK or error code - */ -sw_error_t -fal_qinq_mode_get(a_uint32_t dev_id, fal_qinq_mode_t * mode) -{ - sw_error_t rv; - - FAL_API_LOCK; - rv = _fal_qinq_mode_get(dev_id, mode); - FAL_API_UNLOCK; - return rv; -} -#endif - -/** - * @brief Set qinq role on a particular port. - * @param[in] dev_id device id - * @param[in] port_id port id - * @param[in] role port role - * @return SW_OK or error code - */ -sw_error_t -fal_port_qinq_role_set(a_uint32_t dev_id, fal_port_t port_id, fal_qinq_port_role_t role) -{ - sw_error_t rv; - - FAL_API_LOCK; - rv = _fal_port_qinq_role_set(dev_id, port_id, role); - FAL_API_UNLOCK; - return rv; -} - -#ifndef IN_PORTVLAN_MINI -/** - * @brief Get qinq role on a particular port. - * @param[in] dev_id device id - * @param[in] port_id port id - * @param[out] role port role - * @return SW_OK or error code - */ -sw_error_t -fal_port_qinq_role_get(a_uint32_t dev_id, fal_port_t port_id, fal_qinq_port_role_t * role) -{ - sw_error_t rv; - - FAL_API_LOCK; - rv = _fal_port_qinq_role_get(dev_id, port_id, role); - FAL_API_UNLOCK; - return rv; -} - -/** - * @brief Iterate all vlan translation entries from a particular port. - * @param[in] dev_id device id - * @param[in] port_id port id - * @param[in] iterator translation entry index if it's zero means get the first entry - * @param[out] iterator next valid translation entry index - * @param[out] entry vlan translation entry - * @return SW_OK or error code - */ -sw_error_t -fal_port_vlan_trans_iterate(a_uint32_t dev_id, fal_port_t port_id, - a_uint32_t * iterator, fal_vlan_trans_entry_t * entry) -{ - sw_error_t rv; - - FAL_API_LOCK; - rv = _fal_port_vlan_trans_iterate(dev_id, port_id, iterator, entry); - FAL_API_UNLOCK; - return rv; -} - -/** - * @brief Set MAC_VLAN_XLT status on a particular port. - * @param[in] dev_id device id - * @param[in] port_id port id - * @param[in] role port role - * @return SW_OK or error code - */ -sw_error_t -fal_port_mac_vlan_xlt_set(a_uint32_t dev_id, fal_port_t port_id, - a_bool_t enable) -{ - sw_error_t rv; - - FAL_API_LOCK; - rv = _fal_port_mac_vlan_xlt_set(dev_id, port_id, enable); - FAL_API_UNLOCK; - return rv; -} - -/** - * @brief Get MAC_VLAN_XLT status on a particular port. - * @param[in] dev_id device id - * @param[in] port_id port id - * @param[out] role port role - * @return SW_OK or error code - */ -sw_error_t -fal_port_mac_vlan_xlt_get(a_uint32_t dev_id, fal_port_t port_id, - a_bool_t * enable) -{ - sw_error_t rv; - - FAL_API_LOCK; - rv = _fal_port_mac_vlan_xlt_get(dev_id, port_id, enable); - FAL_API_UNLOCK; - return rv; -} - -/** - * @brief Set net isolate function. - * @param[in] dev_id device id - * @param[in] enable tag protocol identification - * @return SW_OK or error code - */ -sw_error_t -fal_netisolate_set(a_uint32_t dev_id, a_uint32_t enable) -{ - sw_error_t rv; - - FAL_API_LOCK; - rv = _fal_netisolate_set(dev_id, enable); - FAL_API_UNLOCK; - return rv; -} - -/** - * @brief Get net isolate status. - * @param[in] dev_id device id - * @param[out] enable tag protocol identification - * @return SW_OK or error code - */ -sw_error_t -fal_netisolate_get(a_uint32_t dev_id, a_uint32_t * enable) -{ - sw_error_t rv; - - FAL_API_LOCK; - rv = _fal_netisolate_get(dev_id, enable); - FAL_API_UNLOCK; - return rv; -} - - -/** - * @brief Set egress translation filter bypass enable - * @param[in] dev_id device id - * @param[in] enable A_TRUE or A_FALSE - * @return SW_OK or error code - */ -sw_error_t -fal_eg_trans_filter_bypass_en_set(a_uint32_t dev_id, a_bool_t enable) -{ - sw_error_t rv; - - FAL_API_LOCK; - rv = _fal_eg_trans_filter_bypass_en_set(dev_id, enable); - FAL_API_UNLOCK; - return rv; -} - -/** - * @brief Get egress translation filter bypass enable - * @param[in] dev_id device id - * @param[in] enable A_TRUE or A_FALSE - * @return SW_OK or error code - */ -sw_error_t -fal_eg_trans_filter_bypass_en_get(a_uint32_t dev_id, a_bool_t* enable) -{ - sw_error_t rv; - - FAL_API_LOCK; - rv = _fal_eg_trans_filter_bypass_en_get(dev_id, enable); - FAL_API_UNLOCK; - return rv; -} - -/** - * @brief Set VRF id on a particular port. - * @param[in] dev_id device id - * @param[in] port_id port id - * @param[in] vrf_id VRF id - * @return SW_OK or error code - */ -sw_error_t -fal_port_vrf_id_set(a_uint32_t dev_id, fal_port_t port_id, - a_uint32_t vrf_id) -{ - sw_error_t rv; - - FAL_API_LOCK; - rv = _fal_port_vrf_id_set(dev_id, port_id, vrf_id); - FAL_API_UNLOCK; - return rv; -} - -/** - * @brief Get VRF id on a particular port. - * @param[in] dev_id device id - * @param[in] port_id port id - * @param[out] vrf_id VRF id - * @return SW_OK or error code - */ -sw_error_t -fal_port_vrf_id_get(a_uint32_t dev_id, fal_port_t port_id, - a_uint32_t * vrf_id) -{ - sw_error_t rv; - - FAL_API_LOCK; - rv = _fal_port_vrf_id_get(dev_id, port_id, vrf_id); - FAL_API_UNLOCK; - return rv; -} -#endif - -/** - * @} - */ -sw_error_t -_fal_global_qinq_mode_set(a_uint32_t dev_id, fal_global_qinq_mode_t *mode) -{ - sw_error_t rv; - adpt_api_t *p_api; - - SW_RTN_ON_NULL(p_api = adpt_api_ptr_get(dev_id)); - - if (NULL == p_api->adpt_global_qinq_mode_set) - return SW_NOT_SUPPORTED; - - rv = p_api->adpt_global_qinq_mode_set(dev_id, mode); - return rv; -} - -sw_error_t -_fal_global_qinq_mode_get(a_uint32_t dev_id, fal_global_qinq_mode_t *mode) -{ - sw_error_t rv; - adpt_api_t *p_api; - - SW_RTN_ON_NULL(p_api = adpt_api_ptr_get(dev_id)); - - if (NULL == p_api->adpt_global_qinq_mode_get) - return SW_NOT_SUPPORTED; - - rv = p_api->adpt_global_qinq_mode_get(dev_id, mode); - return rv; -} - -sw_error_t -_fal_port_qinq_mode_set(a_uint32_t dev_id, fal_port_t port_id, fal_port_qinq_role_t *mode) -{ - sw_error_t rv; - adpt_api_t *p_api; - - SW_RTN_ON_NULL(p_api = adpt_api_ptr_get(dev_id)); - - if (NULL == p_api->adpt_port_qinq_mode_set) - return SW_NOT_SUPPORTED; - - rv = p_api->adpt_port_qinq_mode_set(dev_id, port_id, mode); - return rv; -} - -sw_error_t -_fal_port_qinq_mode_get(a_uint32_t dev_id, fal_port_t port_id, fal_port_qinq_role_t *mode) -{ - sw_error_t rv; - adpt_api_t *p_api; - - SW_RTN_ON_NULL(p_api = adpt_api_ptr_get(dev_id)); - - if (NULL == p_api->adpt_port_qinq_mode_get) - return SW_NOT_SUPPORTED; - - rv = p_api->adpt_port_qinq_mode_get(dev_id, port_id, mode); - return rv; -} - -sw_error_t -_fal_ingress_tpid_set(a_uint32_t dev_id, fal_tpid_t *tpid) -{ - sw_error_t rv; - adpt_api_t *p_api; - - SW_RTN_ON_NULL(p_api = adpt_api_ptr_get(dev_id)); - - if (NULL == p_api->adpt_tpid_set) - return SW_NOT_SUPPORTED; - - rv = p_api->adpt_tpid_set(dev_id, tpid); - return rv; -} - -sw_error_t -_fal_ingress_tpid_get(a_uint32_t dev_id, fal_tpid_t * tpid) -{ - sw_error_t rv; - adpt_api_t *p_api; - - SW_RTN_ON_NULL(p_api = adpt_api_ptr_get(dev_id)); - - if (NULL == p_api->adpt_tpid_get) - return SW_NOT_SUPPORTED; - - rv = p_api->adpt_tpid_get(dev_id, tpid); - return rv; -} - -sw_error_t -_fal_egress_tpid_set(a_uint32_t dev_id, fal_tpid_t *tpid) -{ - sw_error_t rv; - adpt_api_t *p_api; - - SW_RTN_ON_NULL(p_api = adpt_api_ptr_get(dev_id)); - - if (NULL == p_api->adpt_egress_tpid_set) - return SW_NOT_SUPPORTED; - - rv = p_api->adpt_egress_tpid_set(dev_id, tpid); - return rv; -} - -sw_error_t -_fal_egress_tpid_get(a_uint32_t dev_id, fal_tpid_t * tpid) -{ - sw_error_t rv; - adpt_api_t *p_api; - - SW_RTN_ON_NULL(p_api = adpt_api_ptr_get(dev_id)); - - if (NULL == p_api->adpt_egress_tpid_get) - return SW_NOT_SUPPORTED; - - rv = p_api->adpt_egress_tpid_get(dev_id, tpid); - return rv; -} - -sw_error_t -_fal_port_ingress_vlan_filter_set(a_uint32_t dev_id, fal_port_t port_id, fal_ingress_vlan_filter_t *filter) -{ - sw_error_t rv; - adpt_api_t *p_api; - - SW_RTN_ON_NULL(p_api = adpt_api_ptr_get(dev_id)); - - if (NULL == p_api->adpt_port_ingress_vlan_filter_set) - return SW_NOT_SUPPORTED; - - rv = p_api->adpt_port_ingress_vlan_filter_set(dev_id, port_id, filter); - return rv; -} - -sw_error_t -_fal_port_ingress_vlan_filter_get(a_uint32_t dev_id, fal_port_t port_id, fal_ingress_vlan_filter_t * filter) -{ - sw_error_t rv; - adpt_api_t *p_api; - - SW_RTN_ON_NULL(p_api = adpt_api_ptr_get(dev_id)); - - if (NULL == p_api->adpt_port_ingress_vlan_filter_get) - return SW_NOT_SUPPORTED; - - rv = p_api->adpt_port_ingress_vlan_filter_get(dev_id, port_id, filter); - return rv; -} - -sw_error_t -_fal_port_default_vlantag_set(a_uint32_t dev_id, fal_port_t port_id, fal_port_vlan_direction_t direction, - fal_port_default_vid_enable_t *default_vid_en, fal_port_vlan_tag_t *default_tag) -{ - sw_error_t rv; - adpt_api_t *p_api; - - SW_RTN_ON_NULL(p_api = adpt_api_ptr_get(dev_id)); - - if (NULL == p_api->adpt_port_default_vlantag_set) - return SW_NOT_SUPPORTED; - - rv = p_api->adpt_port_default_vlantag_set(dev_id, port_id, direction, default_vid_en, default_tag); - return rv; -} - -sw_error_t -_fal_port_default_vlantag_get(a_uint32_t dev_id, fal_port_t port_id, fal_port_vlan_direction_t direction, - fal_port_default_vid_enable_t *default_vid_en, fal_port_vlan_tag_t *default_tag) -{ - sw_error_t rv; - adpt_api_t *p_api; - - SW_RTN_ON_NULL(p_api = adpt_api_ptr_get(dev_id)); - - if (NULL == p_api->adpt_port_default_vlantag_get) - return SW_NOT_SUPPORTED; - - rv = p_api->adpt_port_default_vlantag_get(dev_id, port_id, direction, default_vid_en, default_tag); - return rv; -} - -sw_error_t -_fal_port_tag_propagation_set(a_uint32_t dev_id, fal_port_t port_id, fal_port_vlan_direction_t direction, - fal_vlantag_propagation_t *prop) -{ - sw_error_t rv; - adpt_api_t *p_api; - - SW_RTN_ON_NULL(p_api = adpt_api_ptr_get(dev_id)); - - if (NULL == p_api->adpt_port_tag_propagation_set) - return SW_NOT_SUPPORTED; - - rv = p_api->adpt_port_tag_propagation_set(dev_id, port_id, direction, prop); - return rv; -} - -sw_error_t -_fal_port_tag_propagation_get(a_uint32_t dev_id, fal_port_t port_id, fal_port_vlan_direction_t direction, - fal_vlantag_propagation_t *prop) -{ - sw_error_t rv; - adpt_api_t *p_api; - - SW_RTN_ON_NULL(p_api = adpt_api_ptr_get(dev_id)); - - if (NULL == p_api->adpt_port_tag_propagation_get) - return SW_NOT_SUPPORTED; - - rv = p_api->adpt_port_tag_propagation_get(dev_id, port_id, direction, prop); - return rv; -} - -sw_error_t -_fal_port_vlantag_egmode_set(a_uint32_t dev_id, fal_port_t port_id, - fal_vlantag_egress_mode_t *port_egvlanmode) -{ - sw_error_t rv; - adpt_api_t *p_api; - - SW_RTN_ON_NULL(p_api = adpt_api_ptr_get(dev_id)); - - if (NULL == p_api->adpt_port_vlantag_egmode_set) - return SW_NOT_SUPPORTED; - - rv = p_api->adpt_port_vlantag_egmode_set(dev_id, port_id, port_egvlanmode); - return rv; -} - -sw_error_t -_fal_port_vlantag_egmode_get(a_uint32_t dev_id, fal_port_t port_id, - fal_vlantag_egress_mode_t *port_egvlanmode) -{ - sw_error_t rv; - adpt_api_t *p_api; - - SW_RTN_ON_NULL(p_api = adpt_api_ptr_get(dev_id)); - - if (NULL == p_api->adpt_port_vlantag_egmode_get) - return SW_NOT_SUPPORTED; - - rv = p_api->adpt_port_vlantag_egmode_get(dev_id, port_id, port_egvlanmode); - return rv; -} - -sw_error_t -_fal_port_vlan_xlt_miss_cmd_set(a_uint32_t dev_id, fal_port_t port_id, - fal_fwd_cmd_t cmd) -{ - sw_error_t rv; - adpt_api_t *p_api; - - SW_RTN_ON_NULL(p_api = adpt_api_ptr_get(dev_id)); - - if (NULL == p_api->adpt_port_vlan_xlt_miss_cmd_set) - return SW_NOT_SUPPORTED; - - rv = p_api->adpt_port_vlan_xlt_miss_cmd_set(dev_id, port_id, cmd); - return rv; -} - -sw_error_t -_fal_port_vlan_xlt_miss_cmd_get(a_uint32_t dev_id, fal_port_t port_id, - fal_fwd_cmd_t *cmd) -{ - sw_error_t rv; - adpt_api_t *p_api; - - SW_RTN_ON_NULL(p_api = adpt_api_ptr_get(dev_id)); - - if (NULL == p_api->adpt_port_vlan_xlt_miss_cmd_get) - return SW_NOT_SUPPORTED; - - rv = p_api->adpt_port_vlan_xlt_miss_cmd_get(dev_id, port_id, cmd); - return rv; -} - -sw_error_t -_fal_port_vsi_egmode_set(a_uint32_t dev_id, a_uint32_t vsi, a_uint32_t port_id, fal_pt_1q_egmode_t egmode) -{ - sw_error_t rv; - adpt_api_t *p_api; - - SW_RTN_ON_NULL(p_api = adpt_api_ptr_get(dev_id)); - - if (NULL == p_api->adpt_port_vsi_egmode_set) - return SW_NOT_SUPPORTED; - - rv = p_api->adpt_port_vsi_egmode_set(dev_id, vsi, port_id, egmode); - return rv; -} -sw_error_t -_fal_port_vsi_egmode_get(a_uint32_t dev_id, a_uint32_t vsi, a_uint32_t port_id, fal_pt_1q_egmode_t * egmode) -{ - sw_error_t rv; - adpt_api_t *p_api; - - SW_RTN_ON_NULL(p_api = adpt_api_ptr_get(dev_id)); - - if (NULL == p_api->adpt_port_vsi_egmode_get) - return SW_NOT_SUPPORTED; - - rv = p_api->adpt_port_vsi_egmode_get(dev_id, vsi, port_id, egmode); - return rv; -} -sw_error_t -_fal_port_vlantag_vsi_egmode_enable(a_uint32_t dev_id, fal_port_t port_id, a_bool_t enable) -{ - sw_error_t rv; - adpt_api_t *p_api; - - SW_RTN_ON_NULL(p_api = adpt_api_ptr_get(dev_id)); - - if (NULL == p_api->adpt_port_vlantag_vsi_egmode_enable_set) - return SW_NOT_SUPPORTED; - - rv = p_api->adpt_port_vlantag_vsi_egmode_enable_set(dev_id, port_id, enable); - return rv; -} -sw_error_t -_fal_port_vlantag_vsi_egmode_status_get(a_uint32_t dev_id, fal_port_t port_id, a_bool_t * enable) -{ - sw_error_t rv; - adpt_api_t *p_api; - - SW_RTN_ON_NULL(p_api = adpt_api_ptr_get(dev_id)); - - if (NULL == p_api->adpt_port_vlantag_vsi_egmode_enable_get) - return SW_NOT_SUPPORTED; - - rv = p_api->adpt_port_vlantag_vsi_egmode_enable_get(dev_id, port_id, enable); - return rv; -} -sw_error_t -_fal_port_vlan_trans_adv_add(a_uint32_t dev_id, fal_port_t port_id, fal_port_vlan_direction_t direction, - fal_vlan_trans_adv_rule_t * rule, fal_vlan_trans_adv_action_t * action) -{ - sw_error_t rv; - adpt_api_t *p_api; - - SW_RTN_ON_NULL(p_api = adpt_api_ptr_get(dev_id)); - - if (NULL == p_api->adpt_port_vlan_trans_adv_add) - return SW_NOT_SUPPORTED; - - rv = p_api->adpt_port_vlan_trans_adv_add(dev_id, port_id, direction, rule, action); - return rv; -} -sw_error_t -_fal_port_vlan_trans_adv_del(a_uint32_t dev_id, fal_port_t port_id, fal_port_vlan_direction_t direction, - fal_vlan_trans_adv_rule_t * rule, fal_vlan_trans_adv_action_t * action) -{ - sw_error_t rv; - adpt_api_t *p_api; - - SW_RTN_ON_NULL(p_api = adpt_api_ptr_get(dev_id)); - - if (NULL == p_api->adpt_port_vlan_trans_adv_del) - return SW_NOT_SUPPORTED; - - rv = p_api->adpt_port_vlan_trans_adv_del(dev_id, port_id, direction, rule, action); - return rv; -} -sw_error_t -_fal_port_vlan_trans_adv_getfirst(a_uint32_t dev_id, fal_port_t port_id, fal_port_vlan_direction_t direction, - fal_vlan_trans_adv_rule_t * rule, fal_vlan_trans_adv_action_t * action) -{ - sw_error_t rv; - adpt_api_t *p_api; - - SW_RTN_ON_NULL(p_api = adpt_api_ptr_get(dev_id)); - - if (NULL == p_api->adpt_port_vlan_trans_adv_getfirst) - return SW_NOT_SUPPORTED; - - rv = p_api->adpt_port_vlan_trans_adv_getfirst(dev_id, port_id, direction, rule, action); - return rv; -} -sw_error_t -_fal_port_vlan_trans_adv_getnext(a_uint32_t dev_id, fal_port_t port_id, fal_port_vlan_direction_t direction, - fal_vlan_trans_adv_rule_t * rule, fal_vlan_trans_adv_action_t * action) -{ - sw_error_t rv; - adpt_api_t *p_api; - - SW_RTN_ON_NULL(p_api = adpt_api_ptr_get(dev_id)); - - if (NULL == p_api->adpt_port_vlan_trans_adv_getnext) - return SW_NOT_SUPPORTED; - - rv = p_api->adpt_port_vlan_trans_adv_getnext(dev_id, port_id, direction, rule, action); - return rv; -} -sw_error_t -_fal_port_vlan_counter_get(a_uint32_t dev_id, a_uint32_t cnt_index, fal_port_vlan_counter_t * counter) -{ - sw_error_t rv; - adpt_api_t *p_api; - - SW_RTN_ON_NULL(p_api = adpt_api_ptr_get(dev_id)); - - if (NULL == p_api->adpt_port_vlan_counter_get) - return SW_NOT_SUPPORTED; - - rv = p_api->adpt_port_vlan_counter_get(dev_id, cnt_index, counter); - return rv; -} -sw_error_t -_fal_port_vlan_counter_cleanup(a_uint32_t dev_id, a_uint32_t cnt_index) -{ - sw_error_t rv; - adpt_api_t *p_api; - - SW_RTN_ON_NULL(p_api = adpt_api_ptr_get(dev_id)); - - if (NULL == p_api->adpt_port_vlan_counter_cleanup) - return SW_NOT_SUPPORTED; - - rv = p_api->adpt_port_vlan_counter_cleanup(dev_id, cnt_index); - return rv; -} - -sw_error_t -fal_global_qinq_mode_set(a_uint32_t dev_id, fal_global_qinq_mode_t *mode) -{ - sw_error_t rv = SW_OK; - - FAL_PORTVLAN_API_LOCK; - rv = _fal_global_qinq_mode_set(dev_id, mode); - FAL_PORTVLAN_API_UNLOCK; - return rv; -} - -sw_error_t -fal_global_qinq_mode_get(a_uint32_t dev_id, fal_global_qinq_mode_t *mode) -{ - sw_error_t rv = SW_OK; - - FAL_PORTVLAN_API_LOCK; - rv = _fal_global_qinq_mode_get(dev_id, mode); - FAL_PORTVLAN_API_UNLOCK; - return rv; -} - -sw_error_t -fal_port_qinq_mode_set(a_uint32_t dev_id, fal_port_t port_id, fal_port_qinq_role_t *mode) -{ - sw_error_t rv = SW_OK; - - FAL_PORTVLAN_API_LOCK; - rv = _fal_port_qinq_mode_set(dev_id, port_id, mode); - FAL_PORTVLAN_API_UNLOCK; - return rv; -} - -sw_error_t -fal_port_qinq_mode_get(a_uint32_t dev_id, fal_port_t port_id, fal_port_qinq_role_t *mode) -{ - sw_error_t rv = SW_OK; - - FAL_PORTVLAN_API_LOCK; - rv = _fal_port_qinq_mode_get(dev_id, port_id, mode); - FAL_PORTVLAN_API_UNLOCK; - return rv; -} - -sw_error_t -fal_ingress_tpid_set(a_uint32_t dev_id, fal_tpid_t *tpid) -{ - sw_error_t rv = SW_OK; - - FAL_PORTVLAN_API_LOCK; - rv = _fal_ingress_tpid_set(dev_id, tpid); - FAL_PORTVLAN_API_UNLOCK; - return rv; -} - -sw_error_t -fal_ingress_tpid_get(a_uint32_t dev_id, fal_tpid_t * tpid) -{ - sw_error_t rv = SW_OK; - - FAL_PORTVLAN_API_LOCK; - rv = _fal_ingress_tpid_get(dev_id, tpid); - FAL_PORTVLAN_API_UNLOCK; - return rv; -} - -sw_error_t -fal_egress_tpid_set(a_uint32_t dev_id, fal_tpid_t *tpid) -{ - sw_error_t rv = SW_OK; - - FAL_PORTVLAN_API_LOCK; - rv = _fal_egress_tpid_set(dev_id, tpid); - FAL_PORTVLAN_API_UNLOCK; - return rv; -} - -sw_error_t -fal_egress_tpid_get(a_uint32_t dev_id, fal_tpid_t * tpid) -{ - sw_error_t rv = SW_OK; - - FAL_PORTVLAN_API_LOCK; - rv = _fal_egress_tpid_get(dev_id, tpid); - FAL_PORTVLAN_API_UNLOCK; - return rv; -} - -sw_error_t -fal_port_ingress_vlan_filter_set(a_uint32_t dev_id, fal_port_t port_id, fal_ingress_vlan_filter_t *filter) -{ - sw_error_t rv = SW_OK; - - FAL_PORTVLAN_API_LOCK; - rv = _fal_port_ingress_vlan_filter_set(dev_id, port_id, filter); - FAL_PORTVLAN_API_UNLOCK; - return rv; -} - -sw_error_t -fal_port_ingress_vlan_filter_get(a_uint32_t dev_id, fal_port_t port_id, fal_ingress_vlan_filter_t * filter) -{ - sw_error_t rv = SW_OK; - - FAL_PORTVLAN_API_LOCK; - rv = _fal_port_ingress_vlan_filter_get(dev_id, port_id, filter); - FAL_PORTVLAN_API_UNLOCK; - return rv; -} - -sw_error_t -fal_port_default_vlantag_set(a_uint32_t dev_id, fal_port_t port_id, fal_port_vlan_direction_t direction, - fal_port_default_vid_enable_t *default_vid_en, fal_port_vlan_tag_t *default_tag) -{ - sw_error_t rv = SW_OK; - - FAL_PORTVLAN_API_LOCK; - rv = _fal_port_default_vlantag_set(dev_id, port_id, direction, default_vid_en, default_tag); - FAL_PORTVLAN_API_UNLOCK; - return rv; -} - -sw_error_t -fal_port_default_vlantag_get(a_uint32_t dev_id, fal_port_t port_id, fal_port_vlan_direction_t direction, - fal_port_default_vid_enable_t *default_vid_en, fal_port_vlan_tag_t *default_tag) -{ - sw_error_t rv = SW_OK; - - FAL_PORTVLAN_API_LOCK; - rv = _fal_port_default_vlantag_get(dev_id, port_id, direction, default_vid_en, default_tag); - FAL_PORTVLAN_API_UNLOCK; - return rv; -} - -sw_error_t -fal_port_tag_propagation_set(a_uint32_t dev_id, fal_port_t port_id, fal_port_vlan_direction_t direction, - fal_vlantag_propagation_t *prop) -{ - sw_error_t rv = SW_OK; - - FAL_PORTVLAN_API_LOCK; - rv = _fal_port_tag_propagation_set(dev_id, port_id, direction, prop); - FAL_PORTVLAN_API_UNLOCK; - return rv; -} - -sw_error_t -fal_port_tag_propagation_get(a_uint32_t dev_id, fal_port_t port_id, fal_port_vlan_direction_t direction, - fal_vlantag_propagation_t *prop) -{ - sw_error_t rv = SW_OK; - - FAL_PORTVLAN_API_LOCK; - rv = _fal_port_tag_propagation_get(dev_id, port_id, direction, prop); - FAL_PORTVLAN_API_UNLOCK; - return rv; -} - -sw_error_t -fal_port_vlantag_egmode_set(a_uint32_t dev_id, fal_port_t port_id, - fal_vlantag_egress_mode_t *port_egvlanmode) -{ - sw_error_t rv = SW_OK; - - FAL_PORTVLAN_API_LOCK; - rv = _fal_port_vlantag_egmode_set(dev_id, port_id, port_egvlanmode); - FAL_PORTVLAN_API_UNLOCK; - return rv; -} - -sw_error_t -fal_port_vlantag_egmode_get(a_uint32_t dev_id, fal_port_t port_id, - fal_vlantag_egress_mode_t *port_egvlanmode) -{ - sw_error_t rv = SW_OK; - - FAL_PORTVLAN_API_LOCK; - rv = _fal_port_vlantag_egmode_get(dev_id, port_id, port_egvlanmode); - FAL_PORTVLAN_API_UNLOCK; - return rv; -} - -sw_error_t -fal_port_vlan_xlt_miss_cmd_set(a_uint32_t dev_id, fal_port_t port_id, - fal_fwd_cmd_t cmd) -{ - sw_error_t rv = SW_OK; - - FAL_PORTVLAN_API_LOCK; - rv = _fal_port_vlan_xlt_miss_cmd_set(dev_id, port_id, cmd); - FAL_PORTVLAN_API_UNLOCK; - return rv; -} - -sw_error_t -fal_port_vlan_xlt_miss_cmd_get(a_uint32_t dev_id, fal_port_t port_id, - fal_fwd_cmd_t *cmd) -{ - sw_error_t rv = SW_OK; - - FAL_PORTVLAN_API_LOCK; - rv = _fal_port_vlan_xlt_miss_cmd_get(dev_id, port_id, cmd); - FAL_PORTVLAN_API_UNLOCK; - return rv; -} - -sw_error_t -fal_port_vsi_egmode_set(a_uint32_t dev_id, a_uint32_t vsi, a_uint32_t port_id, fal_pt_1q_egmode_t egmode) -{ - sw_error_t rv = SW_OK; - - FAL_PORTVLAN_API_LOCK; - rv = _fal_port_vsi_egmode_set(dev_id, vsi, port_id, egmode); - FAL_PORTVLAN_API_UNLOCK; - return rv; -} -sw_error_t -fal_port_vsi_egmode_get(a_uint32_t dev_id, a_uint32_t vsi, a_uint32_t port_id, fal_pt_1q_egmode_t * egmode) -{ - sw_error_t rv = SW_OK; - - FAL_PORTVLAN_API_LOCK; - rv = _fal_port_vsi_egmode_get(dev_id, vsi, port_id, egmode); - FAL_PORTVLAN_API_UNLOCK; - return rv; -} -sw_error_t -fal_port_vlantag_vsi_egmode_enable(a_uint32_t dev_id, fal_port_t port_id, a_bool_t enable) -{ - sw_error_t rv = SW_OK; - - FAL_PORTVLAN_API_LOCK; - rv = _fal_port_vlantag_vsi_egmode_enable(dev_id, port_id, enable); - FAL_PORTVLAN_API_UNLOCK; - return rv; -} -sw_error_t -fal_port_vlantag_vsi_egmode_status_get(a_uint32_t dev_id, fal_port_t port_id, a_bool_t * enable) -{ - sw_error_t rv = SW_OK; - - FAL_PORTVLAN_API_LOCK; - rv = _fal_port_vlantag_vsi_egmode_status_get(dev_id, port_id, enable); - FAL_PORTVLAN_API_UNLOCK; - return rv; -} -sw_error_t -fal_port_vlan_trans_adv_add(a_uint32_t dev_id, fal_port_t port_id, fal_port_vlan_direction_t direction, - fal_vlan_trans_adv_rule_t * rule, fal_vlan_trans_adv_action_t * action) -{ - sw_error_t rv = SW_OK; - - FAL_PORTVLAN_API_LOCK; - rv = _fal_port_vlan_trans_adv_add(dev_id, port_id, direction, rule, action); - FAL_PORTVLAN_API_UNLOCK; - return rv; -} -sw_error_t -fal_port_vlan_trans_adv_del(a_uint32_t dev_id, fal_port_t port_id, fal_port_vlan_direction_t direction, - fal_vlan_trans_adv_rule_t * rule, fal_vlan_trans_adv_action_t * action) -{ - sw_error_t rv = SW_OK; - - FAL_PORTVLAN_API_LOCK; - rv = _fal_port_vlan_trans_adv_del(dev_id, port_id, direction, rule, action); - FAL_PORTVLAN_API_UNLOCK; - return rv; -} -sw_error_t -fal_port_vlan_trans_adv_getfirst(a_uint32_t dev_id, fal_port_t port_id, fal_port_vlan_direction_t direction, - fal_vlan_trans_adv_rule_t * rule, fal_vlan_trans_adv_action_t * action) -{ - sw_error_t rv = SW_OK; - - FAL_PORTVLAN_API_LOCK; - rv = _fal_port_vlan_trans_adv_getfirst(dev_id, port_id, direction, rule, action); - FAL_PORTVLAN_API_UNLOCK; - return rv; -} -sw_error_t -fal_port_vlan_trans_adv_getnext(a_uint32_t dev_id, fal_port_t port_id, fal_port_vlan_direction_t direction, - fal_vlan_trans_adv_rule_t * rule, fal_vlan_trans_adv_action_t * action) -{ - sw_error_t rv = SW_OK; - - FAL_PORTVLAN_API_LOCK; - rv = _fal_port_vlan_trans_adv_getnext(dev_id, port_id, direction, rule, action); - FAL_PORTVLAN_API_UNLOCK; - return rv; -} -sw_error_t -fal_port_vlan_counter_get(a_uint32_t dev_id, a_uint32_t cnt_index, fal_port_vlan_counter_t * counter) -{ - sw_error_t rv = SW_OK; - - FAL_PORTVLAN_API_LOCK; - rv = _fal_port_vlan_counter_get(dev_id, cnt_index, counter); - FAL_PORTVLAN_API_UNLOCK; - return rv; -} -sw_error_t -fal_port_vlan_counter_cleanup(a_uint32_t dev_id, a_uint32_t cnt_index) -{ - sw_error_t rv = SW_OK; - - FAL_PORTVLAN_API_LOCK; - rv = _fal_port_vlan_counter_cleanup(dev_id, cnt_index); - FAL_PORTVLAN_API_UNLOCK; - return rv; -} - -EXPORT_SYMBOL(fal_port_invlan_mode_set); -EXPORT_SYMBOL(fal_global_qinq_mode_set); -EXPORT_SYMBOL(fal_global_qinq_mode_get); -EXPORT_SYMBOL(fal_port_qinq_mode_set); -EXPORT_SYMBOL(fal_port_qinq_mode_get); -EXPORT_SYMBOL(fal_ingress_tpid_set); -EXPORT_SYMBOL(fal_ingress_tpid_get); -EXPORT_SYMBOL(fal_egress_tpid_set); -EXPORT_SYMBOL(fal_egress_tpid_get); -EXPORT_SYMBOL(fal_port_ingress_vlan_filter_set); -EXPORT_SYMBOL(fal_port_ingress_vlan_filter_get); -EXPORT_SYMBOL(fal_port_default_vlantag_set); -EXPORT_SYMBOL(fal_port_default_vlantag_get); -EXPORT_SYMBOL(fal_port_tag_propagation_set); -EXPORT_SYMBOL(fal_port_tag_propagation_get); -EXPORT_SYMBOL(fal_port_vlantag_egmode_set); -EXPORT_SYMBOL(fal_port_vlantag_egmode_get); -EXPORT_SYMBOL(fal_port_vlan_xlt_miss_cmd_set); -EXPORT_SYMBOL(fal_port_vlan_xlt_miss_cmd_get); -EXPORT_SYMBOL(fal_port_vsi_egmode_set); -EXPORT_SYMBOL(fal_port_vsi_egmode_get); -EXPORT_SYMBOL(fal_port_vlantag_vsi_egmode_enable); -EXPORT_SYMBOL(fal_port_vlantag_vsi_egmode_status_get); -EXPORT_SYMBOL(fal_port_vlan_trans_adv_add); -EXPORT_SYMBOL(fal_port_vlan_trans_adv_del); -EXPORT_SYMBOL(fal_port_vlan_trans_adv_getfirst); -EXPORT_SYMBOL(fal_port_vlan_trans_adv_getnext); -EXPORT_SYMBOL(fal_port_vlan_counter_get); -EXPORT_SYMBOL(fal_port_vlan_counter_cleanup); -EXPORT_SYMBOL(fal_portvlan_member_add); -EXPORT_SYMBOL(fal_portvlan_member_del); -EXPORT_SYMBOL(fal_portvlan_member_update); -EXPORT_SYMBOL(fal_qinq_mode_set); -EXPORT_SYMBOL(fal_port_qinq_role_set); -EXPORT_SYMBOL(fal_port_vlan_trans_add); -#ifndef IN_PORTVLAN_MINI -EXPORT_SYMBOL(fal_qinq_mode_get); -EXPORT_SYMBOL(fal_port_qinq_role_get); -EXPORT_SYMBOL(fal_port_vlan_trans_iterate); -EXPORT_SYMBOL(fal_port_vlan_trans_del); -EXPORT_SYMBOL(fal_port_vlan_trans_get); -EXPORT_SYMBOL(fal_portvlan_member_get); -EXPORT_SYMBOL(fal_port_invlan_mode_get); -#endif diff --git a/feeds/ipq807x/qca-ssdk/src/src/fal/fal_pppoe.c b/feeds/ipq807x/qca-ssdk/src/src/fal/fal_pppoe.c deleted file mode 100755 index 1552b8cbf..000000000 --- a/feeds/ipq807x/qca-ssdk/src/src/fal/fal_pppoe.c +++ /dev/null @@ -1,609 +0,0 @@ -/* - * Copyright (c) 2012, 2015-2017, The Linux Foundation. All rights reserved. - * Permission to use, copy, modify, and/or distribute this software for - * any purpose with or without fee is hereby granted, provided that the - * above copyright notice and this permission notice appear in all copies. - * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES - * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR - * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES - * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN - * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT - * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. - */ - - -/** - * @defgroup fal_pppoe FAL_PPPOE - * @{ - */ -#include "sw.h" -#include "fal_pppoe.h" -#include "hsl_api.h" -#include "adpt.h" - -#include -#include - - -static sw_error_t -_fal_pppoe_cmd_set(a_uint32_t dev_id, fal_fwd_cmd_t cmd) -{ - sw_error_t rv; - hsl_api_t *p_api; - - SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id)); - - if (NULL == p_api->pppoe_cmd_set) - return SW_NOT_SUPPORTED; - - rv = p_api->pppoe_cmd_set(dev_id, cmd); - return rv; -} - - -static sw_error_t -_fal_pppoe_cmd_get(a_uint32_t dev_id, fal_fwd_cmd_t * cmd) -{ - sw_error_t rv; - hsl_api_t *p_api; - - SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id)); - - if (NULL == p_api->pppoe_cmd_get) - return SW_NOT_SUPPORTED; - - rv = p_api->pppoe_cmd_get(dev_id, cmd); - return rv; -} - - -static sw_error_t -_fal_pppoe_status_set(a_uint32_t dev_id, a_bool_t enable) -{ - sw_error_t rv; - hsl_api_t *p_api; - - SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id)); - - if (NULL == p_api->pppoe_status_set) - return SW_NOT_SUPPORTED; - - rv = p_api->pppoe_status_set(dev_id, enable); - return rv; -} - - -static sw_error_t -_fal_pppoe_status_get(a_uint32_t dev_id, a_bool_t * enable) -{ - sw_error_t rv; - hsl_api_t *p_api; - - SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id)); - - if (NULL == p_api->pppoe_status_get) - return SW_NOT_SUPPORTED; - - rv = p_api->pppoe_status_get(dev_id, enable); - return rv; -} - -static sw_error_t -_fal_pppoe_session_add(a_uint32_t dev_id, a_uint32_t session_id, a_bool_t strip_hdr) -{ - sw_error_t rv; - hsl_api_t *p_api; - - SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id)); - - if (NULL == p_api->pppoe_session_add) - return SW_NOT_SUPPORTED; - - rv = p_api->pppoe_session_add(dev_id, session_id, strip_hdr); - return rv; -} - -static sw_error_t -_fal_pppoe_session_del(a_uint32_t dev_id, a_uint32_t session_id) -{ - sw_error_t rv; - hsl_api_t *p_api; - - SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id)); - - if (NULL == p_api->pppoe_session_del) - return SW_NOT_SUPPORTED; - - rv = p_api->pppoe_session_del(dev_id, session_id); - return rv; -} - -static sw_error_t -_fal_pppoe_session_get(a_uint32_t dev_id, a_uint32_t session_id, a_bool_t * strip_hdr) -{ - sw_error_t rv; - hsl_api_t *p_api; - - SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id)); - - if (NULL == p_api->pppoe_session_get) - return SW_NOT_SUPPORTED; - - rv = p_api->pppoe_session_get(dev_id, session_id, strip_hdr); - return rv; -} - -static sw_error_t -_fal_pppoe_session_table_add(a_uint32_t dev_id, - fal_pppoe_session_t * session_tbl) -{ - sw_error_t rv; - hsl_api_t *p_api; - adpt_api_t *p_adpt_api; - - if((p_adpt_api = adpt_api_ptr_get(dev_id)) != NULL) { - if (NULL == p_adpt_api->adpt_pppoe_session_table_add) - return SW_NOT_SUPPORTED; - - rv = p_adpt_api->adpt_pppoe_session_table_add(dev_id, session_tbl); - return rv; - } - - SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id)); - - if (NULL == p_api->pppoe_session_table_add) - return SW_NOT_SUPPORTED; - - rv = p_api->pppoe_session_table_add(dev_id, session_tbl); - return rv; -} - - -static sw_error_t -_fal_pppoe_session_table_del(a_uint32_t dev_id, - fal_pppoe_session_t * session_tbl) -{ - sw_error_t rv; - hsl_api_t *p_api; - adpt_api_t *p_adpt_api; - - if((p_adpt_api = adpt_api_ptr_get(dev_id)) != NULL) { - if (NULL == p_adpt_api->adpt_pppoe_session_table_del) - return SW_NOT_SUPPORTED; - - rv = p_adpt_api->adpt_pppoe_session_table_del(dev_id, session_tbl); - return rv; - } - - SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id)); - - if (NULL == p_api->pppoe_session_table_del) - return SW_NOT_SUPPORTED; - - rv = p_api->pppoe_session_table_del(dev_id, session_tbl); - return rv; -} - -static sw_error_t -_fal_pppoe_session_table_get(a_uint32_t dev_id, - fal_pppoe_session_t * session_tbl) -{ - sw_error_t rv; - hsl_api_t *p_api; - adpt_api_t *p_adpt_api; - - if((p_adpt_api = adpt_api_ptr_get(dev_id)) != NULL) { - if (NULL == p_adpt_api->adpt_pppoe_session_table_get) - return SW_NOT_SUPPORTED; - - rv = p_adpt_api->adpt_pppoe_session_table_get(dev_id, session_tbl); - return rv; - } - - SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id)); - - if (NULL == p_api->pppoe_session_table_get) - return SW_NOT_SUPPORTED; - - rv = p_api->pppoe_session_table_get(dev_id, session_tbl); - return rv; -} - -static sw_error_t -_fal_pppoe_session_id_set(a_uint32_t dev_id, a_uint32_t index, - a_uint32_t id) -{ - sw_error_t rv; - hsl_api_t *p_api; - - SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id)); - - if (NULL == p_api->pppoe_session_id_set) - return SW_NOT_SUPPORTED; - - rv = p_api->pppoe_session_id_set(dev_id, index, id); - return rv; -} - -static sw_error_t -_fal_pppoe_session_id_get(a_uint32_t dev_id, a_uint32_t index, - a_uint32_t * id) -{ - sw_error_t rv; - hsl_api_t *p_api; - - SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id)); - - if (NULL == p_api->pppoe_session_id_get) - return SW_NOT_SUPPORTED; - - rv = p_api->pppoe_session_id_get(dev_id, index, id); - return rv; -} - -static sw_error_t -_fal_rtd_pppoe_en_set(a_uint32_t dev_id, a_bool_t enable) -{ - sw_error_t rv; - hsl_api_t *p_api; - - SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id)); - - if (NULL == p_api->rtd_pppoe_en_set) - return SW_NOT_SUPPORTED; - - rv = p_api->rtd_pppoe_en_set(dev_id, enable); - return rv; -} - - -static sw_error_t -_fal_rtd_pppoe_en_get(a_uint32_t dev_id, a_bool_t * enable) -{ - sw_error_t rv; - hsl_api_t *p_api; - - SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id)); - - if (NULL == p_api->rtd_pppoe_en_get) - return SW_NOT_SUPPORTED; - - rv = p_api->rtd_pppoe_en_get(dev_id, enable); - return rv; -} - -static sw_error_t -_fal_pppoe_l3intf_status_get(a_uint32_t dev_id, a_uint32_t l3_if, a_uint32_t *enable) -{ - adpt_api_t *p_api; - sw_error_t rv = SW_OK; - - SW_RTN_ON_NULL(p_api = adpt_api_ptr_get(dev_id)); - - if (NULL == p_api->adpt_pppoe_en_get) - return SW_NOT_SUPPORTED; - - rv = p_api->adpt_pppoe_en_get(dev_id, l3_if, enable); - return rv; -} - -static sw_error_t -_fal_pppoe_l3intf_enable(a_uint32_t dev_id, a_uint32_t l3_if, a_uint32_t enable) -{ - adpt_api_t *p_api; - sw_error_t rv = SW_OK; - - SW_RTN_ON_NULL(p_api = adpt_api_ptr_get(dev_id)); - - if (NULL == p_api->adpt_pppoe_en_set) - return SW_NOT_SUPPORTED; - - rv = p_api->adpt_pppoe_en_set(dev_id, l3_if, enable); - return rv; -} -/*insert flag for inner fal, don't remove it*/ - -/** - * @brief Set pppoe packets forwarding command on a particular device. - * @details comments: - * Particular device may only support parts of forwarding commands. - * Ihis operation will take effect only after enabling pppoe packets - * hardware acknowledgement - * @param[in] dev_id device id - * @param[in] cmd forwarding command - * @return SW_OK or error code - */ -sw_error_t -fal_pppoe_cmd_set(a_uint32_t dev_id, fal_fwd_cmd_t cmd) -{ - sw_error_t rv; - - FAL_API_LOCK; - rv = _fal_pppoe_cmd_set(dev_id, cmd); - FAL_API_UNLOCK; - return rv; -} - -/** - * @brief Get pppoe packets forwarding command on a particular device. - * @param[in] dev_id device id - * @param[out] cmd forwarding command - * @return SW_OK or error code - */ -sw_error_t -fal_pppoe_cmd_get(a_uint32_t dev_id, fal_fwd_cmd_t * cmd) -{ - sw_error_t rv; - - FAL_API_LOCK; - rv = _fal_pppoe_cmd_get(dev_id, cmd); - FAL_API_UNLOCK; - return rv; -} - -/** - * @brief Set pppoe packets hardware acknowledgement status on particular device. - * @details comments: - * Particular device may only support parts of pppoe packets. - * @param[in] dev_id device id - * @param[in] enable A_TRUE or A_FALSE - * @return SW_OK or error code - */ -sw_error_t -fal_pppoe_status_set(a_uint32_t dev_id, a_bool_t enable) -{ - sw_error_t rv; - - FAL_API_LOCK; - rv = _fal_pppoe_status_set(dev_id, enable); - FAL_API_UNLOCK; - return rv; -} - -/** - * @brief Get pppoe packets hardware acknowledgement status on a particular device. - * @param[in] dev_id device id - * @param[out] enable A_TRUE or A_FALSE - * @return SW_OK or error code - */ -sw_error_t -fal_pppoe_status_get(a_uint32_t dev_id, a_bool_t * enable) -{ - sw_error_t rv; - - FAL_API_LOCK; - rv = _fal_pppoe_status_get(dev_id, enable); - FAL_API_UNLOCK; - return rv; -} - -/** - * @brief Add a pppoe session entry to a particular device. - * @param[in] dev_id device id - * @param[in] session_id pppoe session id - * @param[in] strip_hdr strip or not strip pppoe header - * @return SW_OK or error code - */ -sw_error_t -fal_pppoe_session_add(a_uint32_t dev_id, a_uint32_t session_id, a_bool_t strip_hdr) -{ - sw_error_t rv; - - FAL_API_LOCK; - rv = _fal_pppoe_session_add(dev_id, session_id, strip_hdr); - FAL_API_UNLOCK; - return rv; -} - -/** - * @brief Delete a pppoe session entry from a particular device. - * @param[in] dev_id device id - * @param[in] session_id pppoe session id - * @return SW_OK or error code - */ -sw_error_t -fal_pppoe_session_del(a_uint32_t dev_id, a_uint32_t session_id) -{ - sw_error_t rv; - - FAL_API_LOCK; - rv = _fal_pppoe_session_del(dev_id, session_id); - FAL_API_UNLOCK; - return rv; -} - -/** - * @brief Get a pppoe session entry from a particular device. - * @param[in] dev_id device id - * @param[in] session_id pppoe session id - * @param[out] strip_hdr strip or not strip pppoe header - * @return SW_OK or error code - */ -sw_error_t -fal_pppoe_session_get(a_uint32_t dev_id, a_uint32_t session_id, a_bool_t * strip_hdr) -{ - sw_error_t rv; - - FAL_API_LOCK; - rv = _fal_pppoe_session_get(dev_id, session_id, strip_hdr); - FAL_API_UNLOCK; - return rv; -} - -/** - * @brief Add a pppoe session entry to a particular device. - * The entry only for pppoe/ppp header remove. - * @param[in] dev_id device id - * @param[in] session_tbl pppoe session table - * @return SW_OK or error code - */ -sw_error_t -fal_pppoe_session_table_add(a_uint32_t dev_id, - fal_pppoe_session_t * session_tbl) -{ - sw_error_t rv; - - FAL_API_LOCK; - rv = _fal_pppoe_session_table_add(dev_id, session_tbl); - FAL_API_UNLOCK; - return rv; -} - -/** - * @brief Delete a pppoe session entry from a particular device. - * The entry only for pppoe/ppp header remove. - * @param[in] dev_id device id - * @param[in] session_tbl pppoe session table - * @return SW_OK or error code - */ -sw_error_t -fal_pppoe_session_table_del(a_uint32_t dev_id, - fal_pppoe_session_t * session_tbl) -{ - sw_error_t rv; - - FAL_API_LOCK; - rv = _fal_pppoe_session_table_del(dev_id, session_tbl); - FAL_API_UNLOCK; - return rv; -} - -/** - * @brief Get a pppoe session entry from a particular device. - * The entry only for pppoe/ppp header remove. - * @param[in] dev_id device id - * @param[out] session_tbl pppoe session table - * @return SW_OK or error code - */ -sw_error_t -fal_pppoe_session_table_get(a_uint32_t dev_id, - fal_pppoe_session_t * session_tbl) -{ - sw_error_t rv; - - FAL_API_LOCK; - rv = _fal_pppoe_session_table_get(dev_id, session_tbl); - FAL_API_UNLOCK; - return rv; -} - -/** - * @brief Set a pppoe session id entry to a particular device. - * The entry only for pppoe/ppp header add. - * @param[in] dev_id device id - * @param[in] session_tbl pppoe session table - * @return SW_OK or error code - */ -sw_error_t -fal_pppoe_session_id_set(a_uint32_t dev_id, a_uint32_t index, - a_uint32_t id) -{ - sw_error_t rv; - - FAL_API_LOCK; - rv = _fal_pppoe_session_id_set(dev_id, index, id); - FAL_API_UNLOCK; - return rv; -} - -/** - * @brief Get a pppoe session id entry to a particular device. - * The entry only for pppoe/ppp header add. - * @param[in] dev_id device id - * @param[out] session_tbl pppoe session table - * @return SW_OK or error code - */ -sw_error_t -fal_pppoe_session_id_get(a_uint32_t dev_id, a_uint32_t index, - a_uint32_t * id) -{ - sw_error_t rv; - - FAL_API_LOCK; - rv = _fal_pppoe_session_id_get(dev_id, index, id); - FAL_API_UNLOCK; - return rv; -} - -/** - * @brief Set RM_RTD_PPPOE_EN status on a particular device. - * @param[in] dev_id device id - * @param[in] enable A_TRUE or A_FALSE - * @return SW_OK or error code - */ -sw_error_t -fal_rtd_pppoe_en_set(a_uint32_t dev_id, a_bool_t enable) -{ - sw_error_t rv; - - FAL_API_LOCK; - rv = _fal_rtd_pppoe_en_set(dev_id, enable); - FAL_API_UNLOCK; - return rv; -} - -/** - * @brief Get RM_RTD_PPPOE_EN status on a particular device. - * @param[in] dev_id device id - * @param[in] enable A_TRUE or A_FALSE - * @return SW_OK or error code - */ -sw_error_t -fal_rtd_pppoe_en_get(a_uint32_t dev_id, a_bool_t * enable) -{ - sw_error_t rv; - - FAL_API_LOCK; - rv = _fal_rtd_pppoe_en_get(dev_id, enable); - FAL_API_UNLOCK; - return rv; -} - -/** - * @brief Set a l3 interface pppoe status - * @param[in] dev_id device id - * @param[in] l3 interface name - * @param[in] pppoe status enable or disable - * @return SW_OK or error code - */ -sw_error_t -fal_pppoe_l3intf_status_get(a_uint32_t dev_id, a_uint32_t l3_if, a_uint32_t *enable) -{ - sw_error_t rv = SW_OK; - - FAL_API_LOCK; - rv = _fal_pppoe_l3intf_status_get(dev_id, l3_if, enable); - FAL_API_UNLOCK; - return rv; -} - -/** - * @brief Get a l3 interface pppoe status - * @param[in] dev_id device id - * @param[in] l3 interface name - * @param[out] pppoe status enable or disable - * @return SW_OK or error code - */ -sw_error_t -fal_pppoe_l3intf_enable(a_uint32_t dev_id, a_uint32_t l3_if, a_uint32_t enable) -{ - sw_error_t rv = SW_OK; - - FAL_API_LOCK; - rv = _fal_pppoe_l3intf_enable(dev_id, l3_if, enable); - FAL_API_UNLOCK; - return rv; -} -/*insert flag for outter fal, don't remove it*/ - -EXPORT_SYMBOL(fal_pppoe_session_table_add); -EXPORT_SYMBOL(fal_pppoe_session_table_del); -EXPORT_SYMBOL(fal_pppoe_session_table_get); -EXPORT_SYMBOL(fal_pppoe_l3intf_status_get); -EXPORT_SYMBOL(fal_pppoe_l3intf_enable); - -/** - * @} - */ - diff --git a/feeds/ipq807x/qca-ssdk/src/src/fal/fal_ptp.c b/feeds/ipq807x/qca-ssdk/src/src/fal/fal_ptp.c deleted file mode 100755 index c00df9a29..000000000 --- a/feeds/ipq807x/qca-ssdk/src/src/fal/fal_ptp.c +++ /dev/null @@ -1,1208 +0,0 @@ -/* - * Copyright (c) 2018, The Linux Foundation. All rights reserved. - * Permission to use, copy, modify, and/or distribute this software for - * any purpose with or without fee is hereby granted, provided that the - * above copyright notice and this permission notice appear in all copies. - * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES - * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR - * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES - * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN - * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT - * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. - */ - - -/** - * @defgroup fal_ptp FAL_PTP - * @{ - */ -#include "sw.h" -#include "fal_ptp.h" -#include "hsl_api.h" -#include "adpt.h" - -#include -#include - -sw_error_t -_fal_ptp_security_set(a_uint32_t dev_id, a_uint32_t port_id, - fal_ptp_security_t *sec) -{ - adpt_api_t *p_api; - sw_error_t rv = SW_OK; - - SW_RTN_ON_NULL(p_api = adpt_api_ptr_get(dev_id)); - - if (NULL == p_api->adpt_ptp_security_set) - return SW_NOT_SUPPORTED; - - rv = p_api->adpt_ptp_security_set(dev_id, port_id, sec); - return rv; -} -sw_error_t -_fal_ptp_link_delay_set(a_uint32_t dev_id, a_uint32_t port_id, - fal_ptp_time_t *time) -{ - adpt_api_t *p_api; - sw_error_t rv = SW_OK; - - SW_RTN_ON_NULL(p_api = adpt_api_ptr_get(dev_id)); - - if (NULL == p_api->adpt_ptp_link_delay_set) - return SW_NOT_SUPPORTED; - - rv = p_api->adpt_ptp_link_delay_set(dev_id, port_id, time); - return rv; -} -sw_error_t -_fal_ptp_rx_crc_recalc_status_get(a_uint32_t dev_id, - a_uint32_t port_id, a_bool_t *status) -{ - adpt_api_t *p_api; - sw_error_t rv = SW_OK; - - SW_RTN_ON_NULL(p_api = adpt_api_ptr_get(dev_id)); - - if (NULL == p_api->adpt_ptp_rx_crc_recalc_status_get) - return SW_NOT_SUPPORTED; - - rv = p_api->adpt_ptp_rx_crc_recalc_status_get(dev_id, port_id, status); - return rv; -} -sw_error_t -_fal_ptp_tod_uart_set(a_uint32_t dev_id, a_uint32_t port_id, - fal_ptp_tod_uart_t *tod_uart) -{ - adpt_api_t *p_api; - sw_error_t rv = SW_OK; - - SW_RTN_ON_NULL(p_api = adpt_api_ptr_get(dev_id)); - - if (NULL == p_api->adpt_ptp_tod_uart_set) - return SW_NOT_SUPPORTED; - - rv = p_api->adpt_ptp_tod_uart_set(dev_id, port_id, tod_uart); - return rv; -} -sw_error_t -_fal_ptp_enhanced_timestamp_engine_get(a_uint32_t dev_id, - a_uint32_t port_id, fal_ptp_direction_t direction, - fal_ptp_enhanced_ts_engine_t *ts_engine) -{ - adpt_api_t *p_api; - sw_error_t rv = SW_OK; - - SW_RTN_ON_NULL(p_api = adpt_api_ptr_get(dev_id)); - - if (NULL == p_api->adpt_ptp_enhanced_timestamp_engine_get) - return SW_NOT_SUPPORTED; - - rv = p_api->adpt_ptp_enhanced_timestamp_engine_get(dev_id, port_id, direction, ts_engine); - return rv; -} -sw_error_t -_fal_ptp_pps_signal_control_set(a_uint32_t dev_id, - a_uint32_t port_id, - fal_ptp_pps_signal_control_t *sig_control) -{ - adpt_api_t *p_api; - sw_error_t rv = SW_OK; - - SW_RTN_ON_NULL(p_api = adpt_api_ptr_get(dev_id)); - - if (NULL == p_api->adpt_ptp_pps_signal_control_set) - return SW_NOT_SUPPORTED; - - rv = p_api->adpt_ptp_pps_signal_control_set(dev_id, port_id, sig_control); - return rv; -} -sw_error_t -_fal_ptp_timestamp_get(a_uint32_t dev_id, a_uint32_t port_id, - fal_ptp_direction_t direction, - fal_ptp_pkt_info_t *pkt_info, - fal_ptp_time_t *time) -{ - adpt_api_t *p_api; - sw_error_t rv = SW_OK; - - SW_RTN_ON_NULL(p_api = adpt_api_ptr_get(dev_id)); - - if (NULL == p_api->adpt_ptp_timestamp_get) - return SW_NOT_SUPPORTED; - - rv = p_api->adpt_ptp_timestamp_get(dev_id, port_id, direction, pkt_info, time); - return rv; -} -sw_error_t -_fal_ptp_asym_correction_get(a_uint32_t dev_id, a_uint32_t port_id, - fal_ptp_asym_correction_t* asym_cf) -{ - adpt_api_t *p_api; - sw_error_t rv = SW_OK; - - SW_RTN_ON_NULL(p_api = adpt_api_ptr_get(dev_id)); - - if (NULL == p_api->adpt_ptp_asym_correction_get) - return SW_NOT_SUPPORTED; - - rv = p_api->adpt_ptp_asym_correction_get(dev_id, port_id, asym_cf); - return rv; -} -sw_error_t -_fal_ptp_rtc_time_snapshot_status_get(a_uint32_t dev_id, - a_uint32_t port_id, a_bool_t *status) -{ - adpt_api_t *p_api; - sw_error_t rv = SW_OK; - - SW_RTN_ON_NULL(p_api = adpt_api_ptr_get(dev_id)); - - if (NULL == p_api->adpt_ptp_rtc_time_snapshot_status_get) - return SW_NOT_SUPPORTED; - - rv = p_api->adpt_ptp_rtc_time_snapshot_status_get(dev_id, port_id, status); - return rv; -} -sw_error_t -_fal_ptp_capture_set(a_uint32_t dev_id, a_uint32_t port_id, - a_uint32_t capture_id, fal_ptp_capture_t *capture) -{ - adpt_api_t *p_api; - sw_error_t rv = SW_OK; - - SW_RTN_ON_NULL(p_api = adpt_api_ptr_get(dev_id)); - - if (NULL == p_api->adpt_ptp_capture_set) - return SW_NOT_SUPPORTED; - - rv = p_api->adpt_ptp_capture_set(dev_id, port_id, capture_id, capture); - return rv; -} -sw_error_t -_fal_ptp_rtc_adjfreq_set(a_uint32_t dev_id, a_uint32_t port_id, - fal_ptp_time_t *time) -{ - adpt_api_t *p_api; - sw_error_t rv = SW_OK; - - SW_RTN_ON_NULL(p_api = adpt_api_ptr_get(dev_id)); - - if (NULL == p_api->adpt_ptp_rtc_adjfreq_set) - return SW_NOT_SUPPORTED; - - rv = p_api->adpt_ptp_rtc_adjfreq_set(dev_id, port_id, time); - return rv; -} -sw_error_t -_fal_ptp_asym_correction_set(a_uint32_t dev_id, a_uint32_t port_id, - fal_ptp_asym_correction_t *asym_cf) -{ - adpt_api_t *p_api; - sw_error_t rv = SW_OK; - - SW_RTN_ON_NULL(p_api = adpt_api_ptr_get(dev_id)); - - if (NULL == p_api->adpt_ptp_asym_correction_set) - return SW_NOT_SUPPORTED; - - rv = p_api->adpt_ptp_asym_correction_set(dev_id, port_id, asym_cf); - return rv; -} -sw_error_t -_fal_ptp_pkt_timestamp_set(a_uint32_t dev_id, a_uint32_t port_id, - fal_ptp_time_t *time) -{ - adpt_api_t *p_api; - sw_error_t rv = SW_OK; - - SW_RTN_ON_NULL(p_api = adpt_api_ptr_get(dev_id)); - - if (NULL == p_api->adpt_ptp_pkt_timestamp_set) - return SW_NOT_SUPPORTED; - - rv = p_api->adpt_ptp_pkt_timestamp_set(dev_id, port_id, time); - return rv; -} -sw_error_t -_fal_ptp_rtc_time_get(a_uint32_t dev_id, a_uint32_t port_id, - fal_ptp_time_t *time) -{ - adpt_api_t *p_api; - sw_error_t rv = SW_OK; - - SW_RTN_ON_NULL(p_api = adpt_api_ptr_get(dev_id)); - - if (NULL == p_api->adpt_ptp_rtc_time_get) - return SW_NOT_SUPPORTED; - - rv = p_api->adpt_ptp_rtc_time_get(dev_id, port_id, time); - return rv; -} -sw_error_t -_fal_ptp_rtc_time_set(a_uint32_t dev_id, a_uint32_t port_id, - fal_ptp_time_t *time) -{ - adpt_api_t *p_api; - sw_error_t rv = SW_OK; - - SW_RTN_ON_NULL(p_api = adpt_api_ptr_get(dev_id)); - - if (NULL == p_api->adpt_ptp_rtc_time_set) - return SW_NOT_SUPPORTED; - - rv = p_api->adpt_ptp_rtc_time_set(dev_id, port_id, time); - return rv; -} -sw_error_t -_fal_ptp_pkt_timestamp_get(a_uint32_t dev_id, a_uint32_t port_id, - fal_ptp_time_t *time) -{ - adpt_api_t *p_api; - sw_error_t rv = SW_OK; - - SW_RTN_ON_NULL(p_api = adpt_api_ptr_get(dev_id)); - - if (NULL == p_api->adpt_ptp_pkt_timestamp_get) - return SW_NOT_SUPPORTED; - - rv = p_api->adpt_ptp_pkt_timestamp_get(dev_id, port_id, time); - return rv; -} -sw_error_t -_fal_ptp_interrupt_set(a_uint32_t dev_id, a_uint32_t port_id, - fal_ptp_interrupt_t *interrupt) -{ - adpt_api_t *p_api; - sw_error_t rv = SW_OK; - - SW_RTN_ON_NULL(p_api = adpt_api_ptr_get(dev_id)); - - if (NULL == p_api->adpt_ptp_interrupt_set) - return SW_NOT_SUPPORTED; - - rv = p_api->adpt_ptp_interrupt_set(dev_id, port_id, interrupt); - return rv; -} -sw_error_t -_fal_ptp_trigger_set(a_uint32_t dev_id, a_uint32_t port_id, - a_uint32_t trigger_id, fal_ptp_trigger_t *triger) -{ - adpt_api_t *p_api; - sw_error_t rv = SW_OK; - - SW_RTN_ON_NULL(p_api = adpt_api_ptr_get(dev_id)); - - if (NULL == p_api->adpt_ptp_trigger_set) - return SW_NOT_SUPPORTED; - - rv = p_api->adpt_ptp_trigger_set(dev_id, port_id, trigger_id, triger); - return rv; -} -sw_error_t -_fal_ptp_pps_signal_control_get(a_uint32_t dev_id, - a_uint32_t port_id, - fal_ptp_pps_signal_control_t *sig_control) -{ - adpt_api_t *p_api; - sw_error_t rv = SW_OK; - - SW_RTN_ON_NULL(p_api = adpt_api_ptr_get(dev_id)); - - if (NULL == p_api->adpt_ptp_pps_signal_control_get) - return SW_NOT_SUPPORTED; - - rv = p_api->adpt_ptp_pps_signal_control_get(dev_id, port_id, sig_control); - return rv; -} -sw_error_t -_fal_ptp_capture_get(a_uint32_t dev_id, a_uint32_t port_id, - a_uint32_t capture_id, fal_ptp_capture_t *capture) -{ - adpt_api_t *p_api; - sw_error_t rv = SW_OK; - - SW_RTN_ON_NULL(p_api = adpt_api_ptr_get(dev_id)); - - if (NULL == p_api->adpt_ptp_capture_get) - return SW_NOT_SUPPORTED; - - rv = p_api->adpt_ptp_capture_get(dev_id, port_id, capture_id, capture); - return rv; -} -sw_error_t -_fal_ptp_rx_crc_recalc_enable(a_uint32_t dev_id, a_uint32_t port_id, - a_bool_t status) -{ - adpt_api_t *p_api; - sw_error_t rv = SW_OK; - - SW_RTN_ON_NULL(p_api = adpt_api_ptr_get(dev_id)); - - if (NULL == p_api->adpt_ptp_rx_crc_recalc_enable) - return SW_NOT_SUPPORTED; - - rv = p_api->adpt_ptp_rx_crc_recalc_enable(dev_id, port_id, status); - return rv; -} -sw_error_t -_fal_ptp_security_get(a_uint32_t dev_id, a_uint32_t port_id, - fal_ptp_security_t *sec) -{ - adpt_api_t *p_api; - sw_error_t rv = SW_OK; - - SW_RTN_ON_NULL(p_api = adpt_api_ptr_get(dev_id)); - - if (NULL == p_api->adpt_ptp_security_get) - return SW_NOT_SUPPORTED; - - rv = p_api->adpt_ptp_security_get(dev_id, port_id, sec); - return rv; -} -sw_error_t -_fal_ptp_increment_sync_from_clock_status_get(a_uint32_t dev_id, - a_uint32_t port_id, a_bool_t *status) -{ - adpt_api_t *p_api; - sw_error_t rv = SW_OK; - - SW_RTN_ON_NULL(p_api = adpt_api_ptr_get(dev_id)); - - if (NULL == p_api->adpt_ptp_increment_sync_from_clock_status_get) - return SW_NOT_SUPPORTED; - - rv = p_api->adpt_ptp_increment_sync_from_clock_status_get(dev_id, port_id, status); - return rv; -} -sw_error_t -_fal_ptp_tod_uart_get(a_uint32_t dev_id, a_uint32_t port_id, - fal_ptp_tod_uart_t *tod_uart) -{ - adpt_api_t *p_api; - sw_error_t rv = SW_OK; - - SW_RTN_ON_NULL(p_api = adpt_api_ptr_get(dev_id)); - - if (NULL == p_api->adpt_ptp_tod_uart_get) - return SW_NOT_SUPPORTED; - - rv = p_api->adpt_ptp_tod_uart_get(dev_id, port_id, tod_uart); - return rv; -} -sw_error_t -_fal_ptp_enhanced_timestamp_engine_set(a_uint32_t dev_id, - a_uint32_t port_id, fal_ptp_direction_t direction, - fal_ptp_enhanced_ts_engine_t *ts_engine) -{ - adpt_api_t *p_api; - sw_error_t rv = SW_OK; - - SW_RTN_ON_NULL(p_api = adpt_api_ptr_get(dev_id)); - - if (NULL == p_api->adpt_ptp_enhanced_timestamp_engine_set) - return SW_NOT_SUPPORTED; - - rv = p_api->adpt_ptp_enhanced_timestamp_engine_set(dev_id, port_id, direction, ts_engine); - return rv; -} -sw_error_t -_fal_ptp_rtc_time_clear(a_uint32_t dev_id, a_uint32_t port_id) -{ - adpt_api_t *p_api; - sw_error_t rv = SW_OK; - - SW_RTN_ON_NULL(p_api = adpt_api_ptr_get(dev_id)); - - if (NULL == p_api->adpt_ptp_rtc_time_clear) - return SW_NOT_SUPPORTED; - - rv = p_api->adpt_ptp_rtc_time_clear(dev_id, port_id); - return rv; -} -sw_error_t -_fal_ptp_reference_clock_set(a_uint32_t dev_id, a_uint32_t port_id, - fal_ptp_reference_clock_t ref_clock) -{ - adpt_api_t *p_api; - sw_error_t rv = SW_OK; - - SW_RTN_ON_NULL(p_api = adpt_api_ptr_get(dev_id)); - - if (NULL == p_api->adpt_ptp_reference_clock_set) - return SW_NOT_SUPPORTED; - - rv = p_api->adpt_ptp_reference_clock_set(dev_id, port_id, ref_clock); - return rv; -} -sw_error_t -_fal_ptp_output_waveform_set(a_uint32_t dev_id, a_uint32_t port_id, - fal_ptp_output_waveform_t *waveform) -{ - adpt_api_t *p_api; - sw_error_t rv = SW_OK; - - SW_RTN_ON_NULL(p_api = adpt_api_ptr_get(dev_id)); - - if (NULL == p_api->adpt_ptp_output_waveform_set) - return SW_NOT_SUPPORTED; - - rv = p_api->adpt_ptp_output_waveform_set(dev_id, port_id, waveform); - return rv; -} -sw_error_t -_fal_ptp_rx_timestamp_mode_set(a_uint32_t dev_id, - a_uint32_t port_id, - fal_ptp_rx_timestamp_mode_t ts_mode) -{ - adpt_api_t *p_api; - sw_error_t rv = SW_OK; - - SW_RTN_ON_NULL(p_api = adpt_api_ptr_get(dev_id)); - - if (NULL == p_api->adpt_ptp_rx_timestamp_mode_set) - return SW_NOT_SUPPORTED; - - rv = p_api->adpt_ptp_rx_timestamp_mode_set(dev_id, port_id, ts_mode); - return rv; -} -sw_error_t -_fal_ptp_grandmaster_mode_set(a_uint32_t dev_id, a_uint32_t port_id, - fal_ptp_grandmaster_mode_t *gm_mode) -{ - adpt_api_t *p_api; - sw_error_t rv = SW_OK; - - SW_RTN_ON_NULL(p_api = adpt_api_ptr_get(dev_id)); - - if (NULL == p_api->adpt_ptp_grandmaster_mode_set) - return SW_NOT_SUPPORTED; - - rv = p_api->adpt_ptp_grandmaster_mode_set(dev_id, port_id, gm_mode); - return rv; -} -sw_error_t -_fal_ptp_config_set(a_uint32_t dev_id, a_uint32_t port_id, - fal_ptp_config_t *config) -{ - adpt_api_t *p_api; - sw_error_t rv = SW_OK; - - SW_RTN_ON_NULL(p_api = adpt_api_ptr_get(dev_id)); - - if (NULL == p_api->adpt_ptp_config_set) - return SW_NOT_SUPPORTED; - - rv = p_api->adpt_ptp_config_set(dev_id, port_id, config); - return rv; -} -sw_error_t -_fal_ptp_trigger_get(a_uint32_t dev_id, a_uint32_t port_id, - a_uint32_t trigger_id, fal_ptp_trigger_t *triger) -{ - adpt_api_t *p_api; - sw_error_t rv = SW_OK; - - SW_RTN_ON_NULL(p_api = adpt_api_ptr_get(dev_id)); - - if (NULL == p_api->adpt_ptp_trigger_get) - return SW_NOT_SUPPORTED; - - rv = p_api->adpt_ptp_trigger_get(dev_id, port_id, trigger_id, triger); - return rv; -} -sw_error_t -_fal_ptp_rtc_adjfreq_get(a_uint32_t dev_id, a_uint32_t port_id, - fal_ptp_time_t *time) -{ - adpt_api_t *p_api; - sw_error_t rv = SW_OK; - - SW_RTN_ON_NULL(p_api = adpt_api_ptr_get(dev_id)); - - if (NULL == p_api->adpt_ptp_rtc_adjfreq_get) - return SW_NOT_SUPPORTED; - - rv = p_api->adpt_ptp_rtc_adjfreq_get(dev_id, port_id, time); - return rv; -} -sw_error_t -_fal_ptp_grandmaster_mode_get(a_uint32_t dev_id, a_uint32_t port_id, - fal_ptp_grandmaster_mode_t *gm_mode) -{ - adpt_api_t *p_api; - sw_error_t rv = SW_OK; - - SW_RTN_ON_NULL(p_api = adpt_api_ptr_get(dev_id)); - - if (NULL == p_api->adpt_ptp_grandmaster_mode_get) - return SW_NOT_SUPPORTED; - - rv = p_api->adpt_ptp_grandmaster_mode_get(dev_id, port_id, gm_mode); - return rv; -} -sw_error_t -_fal_ptp_rx_timestamp_mode_get(a_uint32_t dev_id, - a_uint32_t port_id, - fal_ptp_rx_timestamp_mode_t *ts_mode) -{ - adpt_api_t *p_api; - sw_error_t rv = SW_OK; - - SW_RTN_ON_NULL(p_api = adpt_api_ptr_get(dev_id)); - - if (NULL == p_api->adpt_ptp_rx_timestamp_mode_get) - return SW_NOT_SUPPORTED; - - rv = p_api->adpt_ptp_rx_timestamp_mode_get(dev_id, port_id, ts_mode); - return rv; -} -sw_error_t -_fal_ptp_rtc_adjtime_set(a_uint32_t dev_id, a_uint32_t port_id, - fal_ptp_time_t *time) -{ - adpt_api_t *p_api; - sw_error_t rv = SW_OK; - - SW_RTN_ON_NULL(p_api = adpt_api_ptr_get(dev_id)); - - if (NULL == p_api->adpt_ptp_rtc_adjtime_set) - return SW_NOT_SUPPORTED; - - rv = p_api->adpt_ptp_rtc_adjtime_set(dev_id, port_id, time); - return rv; -} -sw_error_t -_fal_ptp_link_delay_get(a_uint32_t dev_id, a_uint32_t port_id, - fal_ptp_time_t *time) -{ - adpt_api_t *p_api; - sw_error_t rv = SW_OK; - - SW_RTN_ON_NULL(p_api = adpt_api_ptr_get(dev_id)); - - if (NULL == p_api->adpt_ptp_link_delay_get) - return SW_NOT_SUPPORTED; - - rv = p_api->adpt_ptp_link_delay_get(dev_id, port_id, time); - return rv; -} -sw_error_t -_fal_ptp_increment_sync_from_clock_enable(a_uint32_t dev_id, - a_uint32_t port_id, a_bool_t status) -{ - adpt_api_t *p_api; - sw_error_t rv = SW_OK; - - SW_RTN_ON_NULL(p_api = adpt_api_ptr_get(dev_id)); - - if (NULL == p_api->adpt_ptp_increment_sync_from_clock_enable) - return SW_NOT_SUPPORTED; - - rv = p_api->adpt_ptp_increment_sync_from_clock_enable(dev_id, port_id, status); - return rv; -} -sw_error_t -_fal_ptp_config_get(a_uint32_t dev_id, a_uint32_t port_id, - fal_ptp_config_t *config) -{ - adpt_api_t *p_api; - sw_error_t rv = SW_OK; - - SW_RTN_ON_NULL(p_api = adpt_api_ptr_get(dev_id)); - - if (NULL == p_api->adpt_ptp_config_get) - return SW_NOT_SUPPORTED; - - rv = p_api->adpt_ptp_config_get(dev_id, port_id, config); - return rv; -} -sw_error_t -_fal_ptp_output_waveform_get(a_uint32_t dev_id, a_uint32_t port_id, - fal_ptp_output_waveform_t *waveform) -{ - adpt_api_t *p_api; - sw_error_t rv = SW_OK; - - SW_RTN_ON_NULL(p_api = adpt_api_ptr_get(dev_id)); - - if (NULL == p_api->adpt_ptp_output_waveform_get) - return SW_NOT_SUPPORTED; - - rv = p_api->adpt_ptp_output_waveform_get(dev_id, port_id, waveform); - return rv; -} -sw_error_t -_fal_ptp_interrupt_get(a_uint32_t dev_id, a_uint32_t port_id, - fal_ptp_interrupt_t *interrupt) -{ - adpt_api_t *p_api; - sw_error_t rv = SW_OK; - - SW_RTN_ON_NULL(p_api = adpt_api_ptr_get(dev_id)); - - if (NULL == p_api->adpt_ptp_interrupt_get) - return SW_NOT_SUPPORTED; - - rv = p_api->adpt_ptp_interrupt_get(dev_id, port_id, interrupt); - return rv; -} -sw_error_t -_fal_ptp_rtc_time_snapshot_enable(a_uint32_t dev_id, - a_uint32_t port_id, a_bool_t status) -{ - adpt_api_t *p_api; - sw_error_t rv = SW_OK; - - SW_RTN_ON_NULL(p_api = adpt_api_ptr_get(dev_id)); - - if (NULL == p_api->adpt_ptp_rtc_time_snapshot_enable) - return SW_NOT_SUPPORTED; - - rv = p_api->adpt_ptp_rtc_time_snapshot_enable(dev_id, port_id, status); - return rv; -} -sw_error_t -_fal_ptp_reference_clock_get(a_uint32_t dev_id, a_uint32_t port_id, - fal_ptp_reference_clock_t *ref_clock) -{ - adpt_api_t *p_api; - sw_error_t rv = SW_OK; - - SW_RTN_ON_NULL(p_api = adpt_api_ptr_get(dev_id)); - - if (NULL == p_api->adpt_ptp_reference_clock_get) - return SW_NOT_SUPPORTED; - - rv = p_api->adpt_ptp_reference_clock_get(dev_id, port_id, ref_clock); - return rv; -} - -sw_error_t -fal_ptp_security_set(a_uint32_t dev_id, a_uint32_t port_id, - fal_ptp_security_t *sec) -{ - sw_error_t rv = SW_OK; - - FAL_API_LOCK; - rv = _fal_ptp_security_set(dev_id, port_id, sec); - FAL_API_UNLOCK; - return rv; -} - sw_error_t -fal_ptp_link_delay_set(a_uint32_t dev_id, a_uint32_t port_id, - fal_ptp_time_t *time) -{ - sw_error_t rv = SW_OK; - - FAL_API_LOCK; - rv = _fal_ptp_link_delay_set(dev_id, port_id, time); - FAL_API_UNLOCK; - return rv; -} -sw_error_t -fal_ptp_rx_crc_recalc_status_get(a_uint32_t dev_id, - a_uint32_t port_id, a_bool_t *status) -{ - sw_error_t rv = SW_OK; - - FAL_API_LOCK; - rv = _fal_ptp_rx_crc_recalc_status_get(dev_id, port_id, status); - FAL_API_UNLOCK; - return rv; -} -sw_error_t -fal_ptp_tod_uart_set(a_uint32_t dev_id, a_uint32_t port_id, - fal_ptp_tod_uart_t *tod_uart) -{ - sw_error_t rv = SW_OK; - - FAL_API_LOCK; - rv = _fal_ptp_tod_uart_set(dev_id, port_id, tod_uart); - FAL_API_UNLOCK; - return rv; -} -sw_error_t -fal_ptp_enhanced_timestamp_engine_get(a_uint32_t dev_id, - a_uint32_t port_id, fal_ptp_direction_t direction, - fal_ptp_enhanced_ts_engine_t *ts_engine) -{ - sw_error_t rv = SW_OK; - - FAL_API_LOCK; - rv = _fal_ptp_enhanced_timestamp_engine_get(dev_id, port_id, direction, ts_engine); - FAL_API_UNLOCK; - return rv; -} -sw_error_t -fal_ptp_pps_signal_control_set(a_uint32_t dev_id, - a_uint32_t port_id, - fal_ptp_pps_signal_control_t *sig_control) -{ - sw_error_t rv = SW_OK; - - FAL_API_LOCK; - rv = _fal_ptp_pps_signal_control_set(dev_id, port_id, sig_control); - FAL_API_UNLOCK; - return rv; -} -sw_error_t -fal_ptp_timestamp_get(a_uint32_t dev_id, a_uint32_t port_id, - fal_ptp_direction_t direction, - fal_ptp_pkt_info_t *pkt_info, - fal_ptp_time_t *time) -{ - sw_error_t rv = SW_OK; - - FAL_API_LOCK; - rv = _fal_ptp_timestamp_get(dev_id, port_id, direction, pkt_info, time); - FAL_API_UNLOCK; - return rv; -} -sw_error_t -fal_ptp_asym_correction_get(a_uint32_t dev_id, a_uint32_t port_id, - fal_ptp_asym_correction_t* asym_cf) -{ - sw_error_t rv = SW_OK; - - FAL_API_LOCK; - rv = _fal_ptp_asym_correction_get(dev_id, port_id, asym_cf); - FAL_API_UNLOCK; - return rv; -} -sw_error_t -fal_ptp_rtc_time_snapshot_status_get(a_uint32_t dev_id, - a_uint32_t port_id, a_bool_t *status) -{ - sw_error_t rv = SW_OK; - - FAL_API_LOCK; - rv = _fal_ptp_rtc_time_snapshot_status_get(dev_id, port_id, status); - FAL_API_UNLOCK; - return rv; -} -sw_error_t -fal_ptp_capture_set(a_uint32_t dev_id, a_uint32_t port_id, - a_uint32_t capture_id, fal_ptp_capture_t *capture) -{ - sw_error_t rv = SW_OK; - - FAL_API_LOCK; - rv = _fal_ptp_capture_set(dev_id, port_id, capture_id, capture); - FAL_API_UNLOCK; - return rv; -} -sw_error_t -fal_ptp_rtc_adjfreq_set(a_uint32_t dev_id, a_uint32_t port_id, - fal_ptp_time_t *time) -{ - sw_error_t rv = SW_OK; - - FAL_API_LOCK; - rv = _fal_ptp_rtc_adjfreq_set(dev_id, port_id, time); - FAL_API_UNLOCK; - return rv; -} -sw_error_t -fal_ptp_asym_correction_set(a_uint32_t dev_id, a_uint32_t port_id, - fal_ptp_asym_correction_t *asym_cf) -{ - sw_error_t rv = SW_OK; - - FAL_API_LOCK; - rv = _fal_ptp_asym_correction_set(dev_id, port_id, asym_cf); - FAL_API_UNLOCK; - return rv; -} -sw_error_t -fal_ptp_pkt_timestamp_set(a_uint32_t dev_id, a_uint32_t port_id, - fal_ptp_time_t *time) -{ - sw_error_t rv = SW_OK; - - FAL_API_LOCK; - rv = _fal_ptp_pkt_timestamp_set(dev_id, port_id, time); - FAL_API_UNLOCK; - return rv; -} -sw_error_t -fal_ptp_rtc_time_get(a_uint32_t dev_id, a_uint32_t port_id, - fal_ptp_time_t *time) -{ - sw_error_t rv = SW_OK; - - FAL_API_LOCK; - rv = _fal_ptp_rtc_time_get(dev_id, port_id, time); - FAL_API_UNLOCK; - return rv; -} -sw_error_t -fal_ptp_rtc_time_set(a_uint32_t dev_id, a_uint32_t port_id, - fal_ptp_time_t *time) -{ - sw_error_t rv = SW_OK; - - FAL_API_LOCK; - rv = _fal_ptp_rtc_time_set(dev_id, port_id, time); - FAL_API_UNLOCK; - return rv; -} -sw_error_t -fal_ptp_pkt_timestamp_get(a_uint32_t dev_id, a_uint32_t port_id, - fal_ptp_time_t *time) -{ - sw_error_t rv = SW_OK; - - FAL_API_LOCK; - rv = _fal_ptp_pkt_timestamp_get(dev_id, port_id, time); - FAL_API_UNLOCK; - return rv; -} -sw_error_t -fal_ptp_interrupt_set(a_uint32_t dev_id, a_uint32_t port_id, - fal_ptp_interrupt_t *interrupt) -{ - sw_error_t rv = SW_OK; - - FAL_API_LOCK; - rv = _fal_ptp_interrupt_set(dev_id, port_id, interrupt); - FAL_API_UNLOCK; - return rv; -} -sw_error_t -fal_ptp_trigger_set(a_uint32_t dev_id, a_uint32_t port_id, - a_uint32_t trigger_id, fal_ptp_trigger_t *triger) -{ - sw_error_t rv = SW_OK; - - FAL_API_LOCK; - rv = _fal_ptp_trigger_set(dev_id, port_id, trigger_id, triger); - FAL_API_UNLOCK; - return rv; -} -sw_error_t -fal_ptp_pps_signal_control_get(a_uint32_t dev_id, - a_uint32_t port_id, - fal_ptp_pps_signal_control_t *sig_control) -{ - sw_error_t rv = SW_OK; - - FAL_API_LOCK; - rv = _fal_ptp_pps_signal_control_get(dev_id, port_id, sig_control); - FAL_API_UNLOCK; - return rv; -} -sw_error_t -fal_ptp_capture_get(a_uint32_t dev_id, a_uint32_t port_id, - a_uint32_t capture_id, fal_ptp_capture_t *capture) -{ - sw_error_t rv = SW_OK; - - FAL_API_LOCK; - rv = _fal_ptp_capture_get(dev_id, port_id, capture_id, capture); - FAL_API_UNLOCK; - return rv; -} -sw_error_t -fal_ptp_rx_crc_recalc_enable(a_uint32_t dev_id, a_uint32_t port_id, - a_bool_t status) -{ - sw_error_t rv = SW_OK; - - FAL_API_LOCK; - rv = _fal_ptp_rx_crc_recalc_enable(dev_id, port_id, status); - FAL_API_UNLOCK; - return rv; -} -sw_error_t -fal_ptp_security_get(a_uint32_t dev_id, a_uint32_t port_id, - fal_ptp_security_t *sec) -{ - sw_error_t rv = SW_OK; - - FAL_API_LOCK; - rv = _fal_ptp_security_get(dev_id, port_id, sec); - FAL_API_UNLOCK; - return rv; -} -sw_error_t -fal_ptp_increment_sync_from_clock_status_get(a_uint32_t dev_id, - a_uint32_t port_id, a_bool_t *status) -{ - sw_error_t rv = SW_OK; - - FAL_API_LOCK; - rv = _fal_ptp_increment_sync_from_clock_status_get(dev_id, port_id, status); - FAL_API_UNLOCK; - return rv; -} -sw_error_t -fal_ptp_tod_uart_get(a_uint32_t dev_id, a_uint32_t port_id, - fal_ptp_tod_uart_t *tod_uart) -{ - sw_error_t rv = SW_OK; - - FAL_API_LOCK; - rv = _fal_ptp_tod_uart_get(dev_id, port_id, tod_uart); - FAL_API_UNLOCK; - return rv; -} -sw_error_t -fal_ptp_enhanced_timestamp_engine_set(a_uint32_t dev_id, - a_uint32_t port_id, fal_ptp_direction_t direction, - fal_ptp_enhanced_ts_engine_t *ts_engine) -{ - sw_error_t rv = SW_OK; - - FAL_API_LOCK; - rv = _fal_ptp_enhanced_timestamp_engine_set(dev_id, port_id, direction, ts_engine); - FAL_API_UNLOCK; - return rv; -} - sw_error_t -fal_ptp_rtc_time_clear(a_uint32_t dev_id, a_uint32_t port_id) -{ - sw_error_t rv = SW_OK; - - FAL_API_LOCK; - rv = _fal_ptp_rtc_time_clear(dev_id, port_id); - FAL_API_UNLOCK; - return rv; -} -sw_error_t -fal_ptp_reference_clock_set(a_uint32_t dev_id, a_uint32_t port_id, - fal_ptp_reference_clock_t ref_clock) -{ - sw_error_t rv = SW_OK; - - FAL_API_LOCK; - rv = _fal_ptp_reference_clock_set(dev_id, port_id, ref_clock); - FAL_API_UNLOCK; - return rv; -} -sw_error_t -fal_ptp_output_waveform_set(a_uint32_t dev_id, a_uint32_t port_id, - fal_ptp_output_waveform_t *waveform) -{ - sw_error_t rv = SW_OK; - - FAL_API_LOCK; - rv = _fal_ptp_output_waveform_set(dev_id, port_id, waveform); - FAL_API_UNLOCK; - return rv; -} -sw_error_t -fal_ptp_rx_timestamp_mode_set(a_uint32_t dev_id, - a_uint32_t port_id, - fal_ptp_rx_timestamp_mode_t ts_mode) -{ - sw_error_t rv = SW_OK; - - FAL_API_LOCK; - rv = _fal_ptp_rx_timestamp_mode_set(dev_id, port_id, ts_mode); - FAL_API_UNLOCK; - return rv; -} -sw_error_t -fal_ptp_grandmaster_mode_set(a_uint32_t dev_id, a_uint32_t port_id, - fal_ptp_grandmaster_mode_t *gm_mode) -{ - sw_error_t rv = SW_OK; - - FAL_API_LOCK; - rv = _fal_ptp_grandmaster_mode_set(dev_id, port_id, gm_mode); - FAL_API_UNLOCK; - return rv; -} -sw_error_t -fal_ptp_config_set(a_uint32_t dev_id, a_uint32_t port_id, - fal_ptp_config_t *config) -{ - sw_error_t rv = SW_OK; - - FAL_API_LOCK; - rv = _fal_ptp_config_set(dev_id, port_id, config); - FAL_API_UNLOCK; - return rv; -} -sw_error_t -fal_ptp_trigger_get(a_uint32_t dev_id, a_uint32_t port_id, - a_uint32_t trigger_id, fal_ptp_trigger_t *triger) -{ - sw_error_t rv = SW_OK; - - FAL_API_LOCK; - rv = _fal_ptp_trigger_get(dev_id, port_id, trigger_id, triger); - FAL_API_UNLOCK; - return rv; -} -sw_error_t -fal_ptp_rtc_adjfreq_get(a_uint32_t dev_id, a_uint32_t port_id, - fal_ptp_time_t *time) -{ - sw_error_t rv = SW_OK; - - FAL_API_LOCK; - rv = _fal_ptp_rtc_adjfreq_get(dev_id, port_id, time); - FAL_API_UNLOCK; - return rv; -} -sw_error_t -fal_ptp_grandmaster_mode_get(a_uint32_t dev_id, a_uint32_t port_id, - fal_ptp_grandmaster_mode_t *gm_mode) -{ - sw_error_t rv = SW_OK; - - FAL_API_LOCK; - rv = _fal_ptp_grandmaster_mode_get(dev_id, port_id, gm_mode); - FAL_API_UNLOCK; - return rv; -} -sw_error_t -fal_ptp_rx_timestamp_mode_get(a_uint32_t dev_id, - a_uint32_t port_id, - fal_ptp_rx_timestamp_mode_t *ts_mode) -{ - sw_error_t rv = SW_OK; - - FAL_API_LOCK; - rv = _fal_ptp_rx_timestamp_mode_get(dev_id, port_id, ts_mode); - FAL_API_UNLOCK; - return rv; -} -sw_error_t -fal_ptp_rtc_adjtime_set(a_uint32_t dev_id, a_uint32_t port_id, - fal_ptp_time_t *time) -{ - sw_error_t rv = SW_OK; - - FAL_API_LOCK; - rv = _fal_ptp_rtc_adjtime_set(dev_id, port_id, time); - FAL_API_UNLOCK; - return rv; -} -sw_error_t -fal_ptp_link_delay_get(a_uint32_t dev_id, a_uint32_t port_id, - fal_ptp_time_t *time) -{ - sw_error_t rv = SW_OK; - - FAL_API_LOCK; - rv = _fal_ptp_link_delay_get(dev_id, port_id, time); - FAL_API_UNLOCK; - return rv; -} -sw_error_t -fal_ptp_increment_sync_from_clock_enable(a_uint32_t dev_id, - a_uint32_t port_id, a_bool_t status) -{ - sw_error_t rv = SW_OK; - - FAL_API_LOCK; - rv = _fal_ptp_increment_sync_from_clock_enable(dev_id, port_id, status); - FAL_API_UNLOCK; - return rv; -} -sw_error_t -fal_ptp_config_get(a_uint32_t dev_id, a_uint32_t port_id, - fal_ptp_config_t *config) -{ - sw_error_t rv = SW_OK; - - FAL_API_LOCK; - rv = _fal_ptp_config_get(dev_id, port_id, config); - FAL_API_UNLOCK; - return rv; -} -sw_error_t -fal_ptp_output_waveform_get(a_uint32_t dev_id, a_uint32_t port_id, - fal_ptp_output_waveform_t *waveform) -{ - sw_error_t rv = SW_OK; - - FAL_API_LOCK; - rv = _fal_ptp_output_waveform_get(dev_id, port_id, waveform); - FAL_API_UNLOCK; - return rv; -} -sw_error_t -fal_ptp_interrupt_get(a_uint32_t dev_id, a_uint32_t port_id, - fal_ptp_interrupt_t *interrupt) -{ - sw_error_t rv = SW_OK; - - FAL_API_LOCK; - rv = _fal_ptp_interrupt_get(dev_id, port_id, interrupt); - FAL_API_UNLOCK; - return rv; -} -sw_error_t -fal_ptp_rtc_time_snapshot_enable(a_uint32_t dev_id, - a_uint32_t port_id, a_bool_t status) -{ - sw_error_t rv = SW_OK; - - FAL_API_LOCK; - rv = _fal_ptp_rtc_time_snapshot_enable(dev_id, port_id, status); - FAL_API_UNLOCK; - return rv; -} -sw_error_t -fal_ptp_reference_clock_get(a_uint32_t dev_id, a_uint32_t port_id, - fal_ptp_reference_clock_t *ref_clock) -{ - sw_error_t rv = SW_OK; - - FAL_API_LOCK; - rv = _fal_ptp_reference_clock_get(dev_id, port_id, ref_clock); - FAL_API_UNLOCK; - return rv; -} - -EXPORT_SYMBOL(fal_ptp_config_set); -EXPORT_SYMBOL(fal_ptp_config_get); -EXPORT_SYMBOL(fal_ptp_reference_clock_set); -EXPORT_SYMBOL(fal_ptp_reference_clock_get); -EXPORT_SYMBOL(fal_ptp_rx_timestamp_mode_set); -EXPORT_SYMBOL(fal_ptp_rx_timestamp_mode_get); -EXPORT_SYMBOL(fal_ptp_timestamp_get); -EXPORT_SYMBOL(fal_ptp_pkt_timestamp_set); -EXPORT_SYMBOL(fal_ptp_pkt_timestamp_get); -EXPORT_SYMBOL(fal_ptp_grandmaster_mode_set); -EXPORT_SYMBOL(fal_ptp_grandmaster_mode_get); -EXPORT_SYMBOL(fal_ptp_rtc_time_get); -EXPORT_SYMBOL(fal_ptp_rtc_time_set); -EXPORT_SYMBOL(fal_ptp_rtc_time_clear); -EXPORT_SYMBOL(fal_ptp_rtc_adjtime_set); -EXPORT_SYMBOL(fal_ptp_rtc_adjfreq_set); -EXPORT_SYMBOL(fal_ptp_rtc_adjfreq_get); -EXPORT_SYMBOL(fal_ptp_link_delay_set); -EXPORT_SYMBOL(fal_ptp_link_delay_get); -EXPORT_SYMBOL(fal_ptp_security_set); -EXPORT_SYMBOL(fal_ptp_security_get); -EXPORT_SYMBOL(fal_ptp_pps_signal_control_set); -EXPORT_SYMBOL(fal_ptp_pps_signal_control_get); -EXPORT_SYMBOL(fal_ptp_rx_crc_recalc_enable); -EXPORT_SYMBOL(fal_ptp_rx_crc_recalc_status_get); -EXPORT_SYMBOL(fal_ptp_asym_correction_set); -EXPORT_SYMBOL(fal_ptp_asym_correction_get); -EXPORT_SYMBOL(fal_ptp_output_waveform_set); -EXPORT_SYMBOL(fal_ptp_output_waveform_get); -EXPORT_SYMBOL(fal_ptp_rtc_time_snapshot_enable); -EXPORT_SYMBOL(fal_ptp_rtc_time_snapshot_status_get); -EXPORT_SYMBOL(fal_ptp_increment_sync_from_clock_enable); -EXPORT_SYMBOL(fal_ptp_increment_sync_from_clock_status_get); -EXPORT_SYMBOL(fal_ptp_tod_uart_set); -EXPORT_SYMBOL(fal_ptp_tod_uart_get); -EXPORT_SYMBOL(fal_ptp_enhanced_timestamp_engine_set); -EXPORT_SYMBOL(fal_ptp_enhanced_timestamp_engine_get); -EXPORT_SYMBOL(fal_ptp_trigger_set); -EXPORT_SYMBOL(fal_ptp_trigger_get); -EXPORT_SYMBOL(fal_ptp_capture_set); -EXPORT_SYMBOL(fal_ptp_capture_get); -EXPORT_SYMBOL(fal_ptp_interrupt_set); -EXPORT_SYMBOL(fal_ptp_interrupt_get); - -/** - * @} - */ diff --git a/feeds/ipq807x/qca-ssdk/src/src/fal/fal_qm.c b/feeds/ipq807x/qca-ssdk/src/src/fal/fal_qm.c deleted file mode 100755 index e2f1dc768..000000000 --- a/feeds/ipq807x/qca-ssdk/src/src/fal/fal_qm.c +++ /dev/null @@ -1,1089 +0,0 @@ -/* - * Copyright (c) 2016-2017, The Linux Foundation. All rights reserved. - * Permission to use, copy, modify, and/or distribute this software for - * any purpose with or without fee is hereby granted, provided that the - * above copyright notice and this permission notice appear in all copies. - * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES - * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR - * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES - * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN - * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT - * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. - */ - - -/** - * @defgroup fal_qm FAL_QM - * @{ - */ -#include "sw.h" -#include "fal_qm.h" -#include "hsl_api.h" -#include "adpt.h" - -#ifndef IN_QM_MINI -sw_error_t -_fal_ucast_hash_map_set( - a_uint32_t dev_id, - a_uint8_t profile, - a_uint8_t rss_hash, - a_int8_t queue_hash) -{ - adpt_api_t *p_api; - sw_error_t rv = SW_OK; - - SW_RTN_ON_NULL(p_api = adpt_api_ptr_get(dev_id)); - - if (NULL == p_api->adpt_ucast_hash_map_set) - return SW_NOT_SUPPORTED; - - rv = p_api->adpt_ucast_hash_map_set(dev_id, profile, rss_hash, queue_hash); - return rv; -} -sw_error_t -_fal_ac_dynamic_threshold_get( - a_uint32_t dev_id, - a_uint32_t queue_id, - fal_ac_dynamic_threshold_t *cfg) -{ - adpt_api_t *p_api; - sw_error_t rv = SW_OK; - - SW_RTN_ON_NULL(p_api = adpt_api_ptr_get(dev_id)); - - if (NULL == p_api->adpt_ac_dynamic_threshold_get) - return SW_NOT_SUPPORTED; - - rv = p_api->adpt_ac_dynamic_threshold_get(dev_id, queue_id, cfg); - return rv; -} -sw_error_t -_fal_ucast_queue_base_profile_get( - a_uint32_t dev_id, - fal_ucast_queue_dest_t *queue_dest, - a_uint32_t *queue_base, a_uint8_t *profile) -{ - adpt_api_t *p_api; - sw_error_t rv = SW_OK; - - SW_RTN_ON_NULL(p_api = adpt_api_ptr_get(dev_id)); - - if (NULL == p_api->adpt_ucast_queue_base_profile_get) - return SW_NOT_SUPPORTED; - - rv = p_api->adpt_ucast_queue_base_profile_get(dev_id, queue_dest, queue_base, profile); - return rv; -} -sw_error_t -_fal_port_mcast_priority_class_get( - a_uint32_t dev_id, - fal_port_t port, - a_uint8_t priority, - a_uint8_t *queue_class) -{ - adpt_api_t *p_api; - sw_error_t rv = SW_OK; - - SW_RTN_ON_NULL(p_api = adpt_api_ptr_get(dev_id)); - - if (NULL == p_api->adpt_port_mcast_priority_class_get) - return SW_NOT_SUPPORTED; - - rv = p_api->adpt_port_mcast_priority_class_get(dev_id, port, priority, queue_class); - return rv; -} -#endif -sw_error_t -_fal_ac_dynamic_threshold_set( - a_uint32_t dev_id, - a_uint32_t queue_id, - fal_ac_dynamic_threshold_t *cfg) -{ - adpt_api_t *p_api; - sw_error_t rv = SW_OK; - - SW_RTN_ON_NULL(p_api = adpt_api_ptr_get(dev_id)); - - if (NULL == p_api->adpt_ac_dynamic_threshold_set) - return SW_NOT_SUPPORTED; - - rv = p_api->adpt_ac_dynamic_threshold_set(dev_id, queue_id, cfg); - return rv; -} -sw_error_t -_fal_ac_prealloc_buffer_set( - a_uint32_t dev_id, - fal_ac_obj_t *obj, - a_uint16_t num) -{ - adpt_api_t *p_api; - sw_error_t rv = SW_OK; - - SW_RTN_ON_NULL(p_api = adpt_api_ptr_get(dev_id)); - - if (NULL == p_api->adpt_ac_prealloc_buffer_set) - return SW_NOT_SUPPORTED; - - rv = p_api->adpt_ac_prealloc_buffer_set(dev_id, obj, num); - return rv; -} -#ifndef IN_QM_MINI -sw_error_t -_fal_ucast_default_hash_get( - a_uint32_t dev_id, - a_uint8_t *hash_value) -{ - adpt_api_t *p_api; - sw_error_t rv = SW_OK; - - SW_RTN_ON_NULL(p_api = adpt_api_ptr_get(dev_id)); - - if (NULL == p_api->adpt_ucast_default_hash_get) - return SW_NOT_SUPPORTED; - - rv = p_api->adpt_ucast_default_hash_get(dev_id, hash_value); - return rv; -} -sw_error_t -_fal_ucast_default_hash_set( - a_uint32_t dev_id, - a_uint8_t hash_value) -{ - adpt_api_t *p_api; - sw_error_t rv = SW_OK; - - SW_RTN_ON_NULL(p_api = adpt_api_ptr_get(dev_id)); - - if (NULL == p_api->adpt_ucast_default_hash_set) - return SW_NOT_SUPPORTED; - - rv = p_api->adpt_ucast_default_hash_set(dev_id, hash_value); - return rv; -} -sw_error_t -_fal_ac_queue_group_get( - a_uint32_t dev_id, - a_uint32_t queue_id, - a_uint8_t *group_id) -{ - adpt_api_t *p_api; - sw_error_t rv = SW_OK; - - SW_RTN_ON_NULL(p_api = adpt_api_ptr_get(dev_id)); - - if (NULL == p_api->adpt_ac_queue_group_get) - return SW_NOT_SUPPORTED; - - rv = p_api->adpt_ac_queue_group_get(dev_id, queue_id, group_id); - return rv; -} -sw_error_t -_fal_ac_ctrl_get( - a_uint32_t dev_id, - fal_ac_obj_t *obj, - fal_ac_ctrl_t *cfg) -{ - adpt_api_t *p_api; - sw_error_t rv = SW_OK; - - SW_RTN_ON_NULL(p_api = adpt_api_ptr_get(dev_id)); - - if (NULL == p_api->adpt_ac_ctrl_get) - return SW_NOT_SUPPORTED; - - rv = p_api->adpt_ac_ctrl_get(dev_id, obj, cfg); - return rv; -} -sw_error_t -_fal_ac_prealloc_buffer_get( - a_uint32_t dev_id, - fal_ac_obj_t *obj, - a_uint16_t *num) -{ - adpt_api_t *p_api; - sw_error_t rv = SW_OK; - - SW_RTN_ON_NULL(p_api = adpt_api_ptr_get(dev_id)); - - if (NULL == p_api->adpt_ac_prealloc_buffer_get) - return SW_NOT_SUPPORTED; - - rv = p_api->adpt_ac_prealloc_buffer_get(dev_id, obj, num); - return rv; -} -sw_error_t -_fal_port_mcast_priority_class_set( - a_uint32_t dev_id, - fal_port_t port, - a_uint8_t priority, - a_uint8_t queue_class) -{ - adpt_api_t *p_api; - sw_error_t rv = SW_OK; - - SW_RTN_ON_NULL(p_api = adpt_api_ptr_get(dev_id)); - - if (NULL == p_api->adpt_port_mcast_priority_class_set) - return SW_NOT_SUPPORTED; - - rv = p_api->adpt_port_mcast_priority_class_set(dev_id, port, priority, queue_class); - return rv; -} -sw_error_t -_fal_ucast_hash_map_get( - a_uint32_t dev_id, - a_uint8_t profile, - a_uint8_t rss_hash, - a_int8_t *queue_hash) -{ - adpt_api_t *p_api; - sw_error_t rv = SW_OK; - - SW_RTN_ON_NULL(p_api = adpt_api_ptr_get(dev_id)); - - if (NULL == p_api->adpt_ucast_hash_map_get) - return SW_NOT_SUPPORTED; - - rv = p_api->adpt_ucast_hash_map_get(dev_id, profile, rss_hash, queue_hash); - return rv; -} -#endif -sw_error_t -_fal_ac_static_threshold_set( - a_uint32_t dev_id, - fal_ac_obj_t *obj, - fal_ac_static_threshold_t *cfg) -{ - adpt_api_t *p_api; - sw_error_t rv = SW_OK; - - SW_RTN_ON_NULL(p_api = adpt_api_ptr_get(dev_id)); - - if (NULL == p_api->adpt_ac_static_threshold_set) - return SW_NOT_SUPPORTED; - - rv = p_api->adpt_ac_static_threshold_set(dev_id, obj, cfg); - return rv; -} -sw_error_t -_fal_ac_queue_group_set( - a_uint32_t dev_id, - a_uint32_t queue_id, - a_uint8_t group_id) -{ - adpt_api_t *p_api; - sw_error_t rv = SW_OK; - - SW_RTN_ON_NULL(p_api = adpt_api_ptr_get(dev_id)); - - if (NULL == p_api->adpt_ac_queue_group_set) - return SW_NOT_SUPPORTED; - - rv = p_api->adpt_ac_queue_group_set(dev_id, queue_id, group_id); - return rv; -} -#ifndef IN_QM_MINI -sw_error_t -_fal_ac_group_buffer_get( - a_uint32_t dev_id, - a_uint8_t group_id, - fal_ac_group_buffer_t *cfg) -{ - adpt_api_t *p_api; - sw_error_t rv = SW_OK; - - SW_RTN_ON_NULL(p_api = adpt_api_ptr_get(dev_id)); - - if (NULL == p_api->adpt_ac_group_buffer_get) - return SW_NOT_SUPPORTED; - - rv = p_api->adpt_ac_group_buffer_get(dev_id, group_id, cfg); - return rv; -} -sw_error_t -_fal_mcast_cpu_code_class_get( - a_uint32_t dev_id, - a_uint8_t cpu_code, - a_uint8_t *queue_class) -{ - adpt_api_t *p_api; - sw_error_t rv = SW_OK; - - SW_RTN_ON_NULL(p_api = adpt_api_ptr_get(dev_id)); - - if (NULL == p_api->adpt_mcast_cpu_code_class_get) - return SW_NOT_SUPPORTED; - - rv = p_api->adpt_mcast_cpu_code_class_get(dev_id, cpu_code, queue_class); - return rv; -} -#endif -sw_error_t -_fal_ac_ctrl_set( - a_uint32_t dev_id, - fal_ac_obj_t *obj, - fal_ac_ctrl_t *cfg) -{ - adpt_api_t *p_api; - sw_error_t rv = SW_OK; - - SW_RTN_ON_NULL(p_api = adpt_api_ptr_get(dev_id)); - - if (NULL == p_api->adpt_ac_ctrl_set) - return SW_NOT_SUPPORTED; - - rv = p_api->adpt_ac_ctrl_set(dev_id, obj, cfg); - return rv; -} -#ifndef IN_QM_MINI -sw_error_t -_fal_ucast_priority_class_get( - a_uint32_t dev_id, - a_uint8_t profile, - a_uint8_t priority, - a_uint8_t *class) -{ - adpt_api_t *p_api; - sw_error_t rv = SW_OK; - - SW_RTN_ON_NULL(p_api = adpt_api_ptr_get(dev_id)); - - if (NULL == p_api->adpt_ucast_priority_class_get) - return SW_NOT_SUPPORTED; - - rv = p_api->adpt_ucast_priority_class_get(dev_id, profile, priority, class); - return rv; -} -#endif -sw_error_t -_fal_queue_flush( - a_uint32_t dev_id, - fal_port_t port, - a_uint16_t queue_id) -{ - adpt_api_t *p_api; - sw_error_t rv = SW_OK; - - SW_RTN_ON_NULL(p_api = adpt_api_ptr_get(dev_id)); - - if (NULL == p_api->adpt_queue_flush) - return SW_NOT_SUPPORTED; - - rv = p_api->adpt_queue_flush(dev_id, port, queue_id); - return rv; -} -#ifndef IN_QM_MINI -sw_error_t -_fal_mcast_cpu_code_class_set( - a_uint32_t dev_id, - a_uint8_t cpu_code, - a_uint8_t queue_class) -{ - adpt_api_t *p_api; - sw_error_t rv = SW_OK; - - SW_RTN_ON_NULL(p_api = adpt_api_ptr_get(dev_id)); - - if (NULL == p_api->adpt_mcast_cpu_code_class_set) - return SW_NOT_SUPPORTED; - - rv = p_api->adpt_mcast_cpu_code_class_set(dev_id, cpu_code, queue_class); - return rv; -} -sw_error_t -_fal_ucast_priority_class_set( - a_uint32_t dev_id, - a_uint8_t profile, - a_uint8_t priority, - a_uint8_t class) -{ - adpt_api_t *p_api; - sw_error_t rv = SW_OK; - - SW_RTN_ON_NULL(p_api = adpt_api_ptr_get(dev_id)); - - if (NULL == p_api->adpt_ucast_priority_class_set) - return SW_NOT_SUPPORTED; - - rv = p_api->adpt_ucast_priority_class_set(dev_id, profile, priority, class); - return rv; -} -sw_error_t -_fal_ac_static_threshold_get( - a_uint32_t dev_id, - fal_ac_obj_t *obj, - fal_ac_static_threshold_t *cfg) -{ - adpt_api_t *p_api; - sw_error_t rv = SW_OK; - - SW_RTN_ON_NULL(p_api = adpt_api_ptr_get(dev_id)); - - if (NULL == p_api->adpt_ac_static_threshold_get) - return SW_NOT_SUPPORTED; - - rv = p_api->adpt_ac_static_threshold_get(dev_id, obj, cfg); - return rv; -} -#endif -sw_error_t -_fal_ucast_queue_base_profile_set( - a_uint32_t dev_id, - fal_ucast_queue_dest_t *queue_dest, - a_uint32_t queue_base, a_uint8_t profile) -{ - adpt_api_t *p_api; - sw_error_t rv = SW_OK; - - SW_RTN_ON_NULL(p_api = adpt_api_ptr_get(dev_id)); - - if (NULL == p_api->adpt_ucast_queue_base_profile_set) - return SW_NOT_SUPPORTED; - - rv = p_api->adpt_ucast_queue_base_profile_set(dev_id, queue_dest, queue_base, profile); - return rv; -} -sw_error_t -_fal_ac_group_buffer_set( - a_uint32_t dev_id, - a_uint8_t group_id, - fal_ac_group_buffer_t *cfg) -{ - adpt_api_t *p_api; - sw_error_t rv = SW_OK; - - SW_RTN_ON_NULL(p_api = adpt_api_ptr_get(dev_id)); - - if (NULL == p_api->adpt_ac_group_buffer_set) - return SW_NOT_SUPPORTED; - - rv = p_api->adpt_ac_group_buffer_set(dev_id, group_id, cfg); - return rv; -} - -#ifndef IN_QM_MINI -sw_error_t -_fal_queue_counter_ctrl_set(a_uint32_t dev_id, a_bool_t cnt_en) -{ - adpt_api_t *p_api; - sw_error_t rv = SW_OK; - - SW_RTN_ON_NULL(p_api = adpt_api_ptr_get(dev_id)); - - if (NULL == p_api->adpt_queue_counter_ctrl_set) - return SW_NOT_SUPPORTED; - - rv = p_api->adpt_queue_counter_ctrl_set(dev_id, cnt_en); - return rv; -} - -sw_error_t -_fal_queue_counter_ctrl_get(a_uint32_t dev_id, a_bool_t *cnt_en) -{ - adpt_api_t *p_api; - sw_error_t rv = SW_OK; - - SW_RTN_ON_NULL(p_api = adpt_api_ptr_get(dev_id)); - - if (NULL == p_api->adpt_queue_counter_ctrl_get) - return SW_NOT_SUPPORTED; - - rv = p_api->adpt_queue_counter_ctrl_get(dev_id, cnt_en); - return rv; -} - -sw_error_t -_fal_queue_counter_get( - a_uint32_t dev_id, - a_uint32_t queue_id, - fal_queue_stats_t *info) -{ - adpt_api_t *p_api; - sw_error_t rv = SW_OK; - - SW_RTN_ON_NULL(p_api = adpt_api_ptr_get(dev_id)); - - if (NULL == p_api->adpt_queue_counter_get) - return SW_NOT_SUPPORTED; - - rv = p_api->adpt_queue_counter_get(dev_id, queue_id, info); - return rv; -} - -sw_error_t -_fal_queue_counter_cleanup(a_uint32_t dev_id, a_uint32_t queue_id) -{ - adpt_api_t *p_api; - sw_error_t rv = SW_OK; - - SW_RTN_ON_NULL(p_api = adpt_api_ptr_get(dev_id)); - - if (NULL == p_api->adpt_queue_counter_cleanup) - return SW_NOT_SUPPORTED; - - rv = p_api->adpt_queue_counter_cleanup(dev_id, queue_id); - return rv; -} -#endif - -sw_error_t -_fal_qm_enqueue_ctrl_set(a_uint32_t dev_id, a_uint32_t queue_id, a_bool_t enable) -{ - adpt_api_t *p_api; - sw_error_t rv = SW_OK; - - SW_RTN_ON_NULL(p_api = adpt_api_ptr_get(dev_id)); - - if (NULL == p_api->adpt_qm_enqueue_ctrl_set) - return SW_NOT_SUPPORTED; - - rv = p_api->adpt_qm_enqueue_ctrl_set(dev_id, queue_id, enable); - return rv; -} - -#ifndef IN_QM_MINI -sw_error_t -_fal_qm_enqueue_ctrl_get(a_uint32_t dev_id, a_uint32_t queue_id, a_bool_t *enable) -{ - adpt_api_t *p_api; - sw_error_t rv = SW_OK; - - SW_RTN_ON_NULL(p_api = adpt_api_ptr_get(dev_id)); - - if (NULL == p_api->adpt_qm_enqueue_ctrl_get) - return SW_NOT_SUPPORTED; - - rv = p_api->adpt_qm_enqueue_ctrl_get(dev_id, queue_id, enable); - return rv; -} - -sw_error_t -_fal_qm_port_source_profile_set(a_uint32_t dev_id, fal_port_t port, a_uint32_t src_profile) -{ - adpt_api_t *p_api; - sw_error_t rv = SW_OK; - - SW_RTN_ON_NULL(p_api = adpt_api_ptr_get(dev_id)); - - if (NULL == p_api->adpt_qm_port_source_profile_set) - return SW_NOT_SUPPORTED; - - rv = p_api->adpt_qm_port_source_profile_set(dev_id, port, src_profile); - return rv; -} -sw_error_t -_fal_qm_port_source_profile_get(a_uint32_t dev_id, fal_port_t port, a_uint32_t *src_profile) -{ - adpt_api_t *p_api; - sw_error_t rv = SW_OK; - - SW_RTN_ON_NULL(p_api = adpt_api_ptr_get(dev_id)); - - if (NULL == p_api->adpt_qm_port_source_profile_get) - return SW_NOT_SUPPORTED; - - rv = p_api->adpt_qm_port_source_profile_get(dev_id, port, src_profile); - return rv; -} - -/*insert flag for inner fal, don't remove it*/ - -sw_error_t -fal_ucast_hash_map_set( - a_uint32_t dev_id, - a_uint8_t profile, - a_uint8_t rss_hash, - a_int8_t queue_hash) -{ - sw_error_t rv = SW_OK; - - FAL_API_LOCK; - rv = _fal_ucast_hash_map_set(dev_id, profile, rss_hash, queue_hash); - FAL_API_UNLOCK; - return rv; -} -sw_error_t -fal_ac_dynamic_threshold_get( - a_uint32_t dev_id, - a_uint32_t queue_id, - fal_ac_dynamic_threshold_t *cfg) -{ - sw_error_t rv = SW_OK; - - FAL_API_LOCK; - rv = _fal_ac_dynamic_threshold_get(dev_id, queue_id, cfg); - FAL_API_UNLOCK; - return rv; -} -sw_error_t -fal_ucast_queue_base_profile_get( - a_uint32_t dev_id, - fal_ucast_queue_dest_t *queue_dest, - a_uint32_t *queue_base, a_uint8_t *profile) -{ - sw_error_t rv = SW_OK; - - FAL_API_LOCK; - rv = _fal_ucast_queue_base_profile_get(dev_id, queue_dest, queue_base, profile); - FAL_API_UNLOCK; - return rv; -} -sw_error_t -fal_port_mcast_priority_class_get( - a_uint32_t dev_id, - fal_port_t port, - a_uint8_t priority, - a_uint8_t *queue_class) -{ - sw_error_t rv = SW_OK; - - FAL_API_LOCK; - rv = _fal_port_mcast_priority_class_get(dev_id, port, priority, queue_class); - FAL_API_UNLOCK; - return rv; -} -#endif -sw_error_t -fal_ac_dynamic_threshold_set( - a_uint32_t dev_id, - a_uint32_t queue_id, - fal_ac_dynamic_threshold_t *cfg) -{ - sw_error_t rv = SW_OK; - - FAL_API_LOCK; - rv = _fal_ac_dynamic_threshold_set(dev_id, queue_id, cfg); - FAL_API_UNLOCK; - return rv; -} -sw_error_t -fal_ac_prealloc_buffer_set( - a_uint32_t dev_id, - fal_ac_obj_t *obj, - a_uint16_t num) -{ - sw_error_t rv = SW_OK; - - FAL_API_LOCK; - rv = _fal_ac_prealloc_buffer_set(dev_id, obj, num); - FAL_API_UNLOCK; - return rv; -} -#ifndef IN_QM_MINI -sw_error_t -fal_ucast_default_hash_get( - a_uint32_t dev_id, - a_uint8_t *hash_value) -{ - sw_error_t rv = SW_OK; - - FAL_API_LOCK; - rv = _fal_ucast_default_hash_get(dev_id, hash_value); - FAL_API_UNLOCK; - return rv; -} -sw_error_t -fal_ucast_default_hash_set( - a_uint32_t dev_id, - a_uint8_t hash_value) -{ - sw_error_t rv = SW_OK; - - FAL_API_LOCK; - rv = _fal_ucast_default_hash_set(dev_id, hash_value); - FAL_API_UNLOCK; - return rv; -} -sw_error_t -fal_ac_queue_group_get( - a_uint32_t dev_id, - a_uint32_t queue_id, - a_uint8_t *group_id) -{ - sw_error_t rv = SW_OK; - - FAL_API_LOCK; - rv = _fal_ac_queue_group_get(dev_id, queue_id, group_id); - FAL_API_UNLOCK; - return rv; -} -sw_error_t -fal_ac_ctrl_get( - a_uint32_t dev_id, - fal_ac_obj_t *obj, - fal_ac_ctrl_t *cfg) -{ - sw_error_t rv = SW_OK; - - FAL_API_LOCK; - rv = _fal_ac_ctrl_get(dev_id, obj, cfg); - FAL_API_UNLOCK; - return rv; -} -sw_error_t -fal_ac_prealloc_buffer_get( - a_uint32_t dev_id, - fal_ac_obj_t *obj, - a_uint16_t *num) -{ - sw_error_t rv = SW_OK; - - FAL_API_LOCK; - rv = _fal_ac_prealloc_buffer_get(dev_id, obj, num); - FAL_API_UNLOCK; - return rv; -} -sw_error_t -fal_port_mcast_priority_class_set( - a_uint32_t dev_id, - fal_port_t port, - a_uint8_t priority, - a_uint8_t queue_class) -{ - sw_error_t rv = SW_OK; - - FAL_API_LOCK; - rv = _fal_port_mcast_priority_class_set(dev_id, port, priority, queue_class); - FAL_API_UNLOCK; - return rv; -} -sw_error_t -fal_ucast_hash_map_get( - a_uint32_t dev_id, - a_uint8_t profile, - a_uint8_t rss_hash, - a_int8_t *queue_hash) -{ - sw_error_t rv = SW_OK; - - FAL_API_LOCK; - rv = _fal_ucast_hash_map_get(dev_id, profile, rss_hash, queue_hash); - FAL_API_UNLOCK; - return rv; -} -#endif -sw_error_t -fal_ac_static_threshold_set( - a_uint32_t dev_id, - fal_ac_obj_t *obj, - fal_ac_static_threshold_t *cfg) -{ - sw_error_t rv = SW_OK; - - FAL_API_LOCK; - rv = _fal_ac_static_threshold_set(dev_id, obj, cfg); - FAL_API_UNLOCK; - return rv; -} -sw_error_t -fal_ac_queue_group_set( - a_uint32_t dev_id, - a_uint32_t queue_id, - a_uint8_t group_id) -{ - sw_error_t rv = SW_OK; - - FAL_API_LOCK; - rv = _fal_ac_queue_group_set(dev_id, queue_id, group_id); - FAL_API_UNLOCK; - return rv; -} -#ifndef IN_QM_MINI -sw_error_t -fal_ac_group_buffer_get( - a_uint32_t dev_id, - a_uint8_t group_id, - fal_ac_group_buffer_t *cfg) -{ - sw_error_t rv = SW_OK; - - FAL_API_LOCK; - rv = _fal_ac_group_buffer_get(dev_id, group_id, cfg); - FAL_API_UNLOCK; - return rv; -} -sw_error_t -fal_mcast_cpu_code_class_get( - a_uint32_t dev_id, - a_uint8_t cpu_code, - a_uint8_t *queue_class) -{ - sw_error_t rv = SW_OK; - - FAL_API_LOCK; - rv = _fal_mcast_cpu_code_class_get(dev_id, cpu_code, queue_class); - FAL_API_UNLOCK; - return rv; -} -#endif -sw_error_t -fal_ac_ctrl_set( - a_uint32_t dev_id, - fal_ac_obj_t *obj, - fal_ac_ctrl_t *cfg) -{ - sw_error_t rv = SW_OK; - - FAL_API_LOCK; - rv = _fal_ac_ctrl_set(dev_id, obj, cfg); - FAL_API_UNLOCK; - return rv; -} -#ifndef IN_QM_MINI -sw_error_t -fal_ucast_priority_class_get( - a_uint32_t dev_id, - a_uint8_t profile, - a_uint8_t priority, - a_uint8_t *class) -{ - sw_error_t rv = SW_OK; - - FAL_API_LOCK; - rv = _fal_ucast_priority_class_get(dev_id, profile, priority, class); - FAL_API_UNLOCK; - return rv; -} -#endif -sw_error_t -fal_queue_flush( - a_uint32_t dev_id, - fal_port_t port, - a_uint16_t queue_id) -{ - sw_error_t rv = SW_OK; - - FAL_API_LOCK; - rv = _fal_queue_flush(dev_id, port, queue_id); - FAL_API_UNLOCK; - return rv; -} -#ifndef IN_QM_MINI -sw_error_t -fal_mcast_cpu_code_class_set( - a_uint32_t dev_id, - a_uint8_t cpu_code, - a_uint8_t queue_class) -{ - sw_error_t rv = SW_OK; - - FAL_API_LOCK; - rv = _fal_mcast_cpu_code_class_set(dev_id, cpu_code, queue_class); - FAL_API_UNLOCK; - return rv; -} -sw_error_t -fal_ucast_priority_class_set( - a_uint32_t dev_id, - a_uint8_t profile, - a_uint8_t priority, - a_uint8_t class) -{ - sw_error_t rv = SW_OK; - - FAL_API_LOCK; - rv = _fal_ucast_priority_class_set(dev_id, profile, priority, class); - FAL_API_UNLOCK; - return rv; -} -sw_error_t -fal_ac_static_threshold_get( - a_uint32_t dev_id, - fal_ac_obj_t *obj, - fal_ac_static_threshold_t *cfg) -{ - sw_error_t rv = SW_OK; - - FAL_API_LOCK; - rv = _fal_ac_static_threshold_get(dev_id, obj, cfg); - FAL_API_UNLOCK; - return rv; -} -#endif -sw_error_t -fal_ucast_queue_base_profile_set( - a_uint32_t dev_id, - fal_ucast_queue_dest_t *queue_dest, - a_uint32_t queue_base, a_uint8_t profile) -{ - sw_error_t rv = SW_OK; - - FAL_API_LOCK; - rv = _fal_ucast_queue_base_profile_set(dev_id, queue_dest, queue_base, profile); - FAL_API_UNLOCK; - return rv; -} -sw_error_t -fal_ac_group_buffer_set( - a_uint32_t dev_id, - a_uint8_t group_id, - fal_ac_group_buffer_t *cfg) -{ - sw_error_t rv = SW_OK; - - FAL_API_LOCK; - rv = _fal_ac_group_buffer_set(dev_id, group_id, cfg); - FAL_API_UNLOCK; - return rv; -} - -#ifndef IN_QM_MINI -sw_error_t -fal_queue_counter_ctrl_set(a_uint32_t dev_id, a_bool_t cnt_en) -{ - sw_error_t rv = SW_OK; - - FAL_API_LOCK; - rv = _fal_queue_counter_ctrl_set(dev_id, cnt_en); - FAL_API_UNLOCK; - return rv; -} - -sw_error_t -fal_queue_counter_ctrl_get(a_uint32_t dev_id, a_bool_t *cnt_en) -{ - sw_error_t rv = SW_OK; - - FAL_API_LOCK; - rv = _fal_queue_counter_ctrl_get(dev_id, cnt_en); - FAL_API_UNLOCK; - return rv; -} - -sw_error_t -fal_queue_counter_get( - a_uint32_t dev_id, - a_uint32_t queue_id, - fal_queue_stats_t *info) -{ - sw_error_t rv = SW_OK; - - FAL_API_LOCK; - rv = _fal_queue_counter_get(dev_id, queue_id, info); - FAL_API_UNLOCK; - return rv; -} - -sw_error_t -fal_queue_counter_cleanup(a_uint32_t dev_id, a_uint32_t queue_id) -{ - sw_error_t rv = SW_OK; - - FAL_API_LOCK; - rv = _fal_queue_counter_cleanup(dev_id, queue_id); - FAL_API_UNLOCK; - return rv; -} -#endif - -sw_error_t -fal_qm_enqueue_ctrl_set(a_uint32_t dev_id, a_uint32_t queue_id, a_bool_t enable) -{ - sw_error_t rv = SW_OK; - - FAL_API_LOCK; - rv = _fal_qm_enqueue_ctrl_set(dev_id, queue_id, enable); - FAL_API_UNLOCK; - return rv; -} - -#ifndef IN_QM_MINI -sw_error_t -fal_qm_enqueue_ctrl_get(a_uint32_t dev_id, a_uint32_t queue_id, a_bool_t *enable) -{ - sw_error_t rv = SW_OK; - - FAL_API_LOCK; - rv = _fal_qm_enqueue_ctrl_get(dev_id, queue_id, enable); - FAL_API_UNLOCK; - return rv; -} - -sw_error_t -fal_qm_port_source_profile_set(a_uint32_t dev_id, fal_port_t port, a_uint32_t src_profile) -{ - sw_error_t rv = SW_OK; - - FAL_API_LOCK; - rv = _fal_qm_port_source_profile_set(dev_id, port, src_profile); - FAL_API_UNLOCK; - return rv; -} -sw_error_t -fal_qm_port_source_profile_get(a_uint32_t dev_id, fal_port_t port, a_uint32_t *src_profile) -{ - sw_error_t rv = SW_OK; - - FAL_API_LOCK; - rv = _fal_qm_port_source_profile_get(dev_id, port, src_profile); - FAL_API_UNLOCK; - return rv; -} -#endif - -EXPORT_SYMBOL(fal_ac_ctrl_set); - -EXPORT_SYMBOL(fal_ac_prealloc_buffer_set); - -EXPORT_SYMBOL(fal_ac_queue_group_set); - -EXPORT_SYMBOL(fal_ac_static_threshold_set); - -EXPORT_SYMBOL(fal_ac_dynamic_threshold_set); - -EXPORT_SYMBOL(fal_ac_group_buffer_set); - -EXPORT_SYMBOL(fal_ucast_queue_base_profile_set); - -EXPORT_SYMBOL(fal_queue_flush); - -EXPORT_SYMBOL(fal_qm_enqueue_ctrl_set); - -#ifndef IN_QM_MINI -EXPORT_SYMBOL(fal_qm_port_source_profile_set); - -EXPORT_SYMBOL(fal_qm_port_source_profile_get); - -EXPORT_SYMBOL(fal_qm_enqueue_ctrl_get); - -EXPORT_SYMBOL(fal_ac_ctrl_get); - -EXPORT_SYMBOL(fal_ac_prealloc_buffer_get); - -EXPORT_SYMBOL(fal_ac_queue_group_get); - -EXPORT_SYMBOL(fal_ac_static_threshold_get); - -EXPORT_SYMBOL(fal_ac_dynamic_threshold_get); - -EXPORT_SYMBOL(fal_ac_group_buffer_get); - -EXPORT_SYMBOL(fal_ucast_queue_base_profile_get); - -EXPORT_SYMBOL(fal_ucast_priority_class_set); - -EXPORT_SYMBOL(fal_ucast_priority_class_get); - -EXPORT_SYMBOL(fal_ucast_hash_map_set); - -EXPORT_SYMBOL(fal_ucast_hash_map_get); - -EXPORT_SYMBOL(fal_mcast_cpu_code_class_set); - -EXPORT_SYMBOL(fal_mcast_cpu_code_class_get); - -EXPORT_SYMBOL(fal_port_mcast_priority_class_set); - -EXPORT_SYMBOL(fal_port_mcast_priority_class_get); - -EXPORT_SYMBOL(fal_queue_counter_ctrl_set); - -EXPORT_SYMBOL(fal_queue_counter_ctrl_get); - -EXPORT_SYMBOL(fal_queue_counter_get); - -EXPORT_SYMBOL(fal_queue_counter_cleanup); -#endif - -/*insert flag for outter fal, don't remove it*/ diff --git a/feeds/ipq807x/qca-ssdk/src/src/fal/fal_qos.c b/feeds/ipq807x/qca-ssdk/src/src/fal/fal_qos.c deleted file mode 100644 index fcb8dc760..000000000 --- a/feeds/ipq807x/qca-ssdk/src/src/fal/fal_qos.c +++ /dev/null @@ -1,2000 +0,0 @@ -/* - * Copyright (c) 2012, 2017, The Linux Foundation. All rights reserved. - * Permission to use, copy, modify, and/or distribute this software for - * any purpose with or without fee is hereby granted, provided that the - * above copyright notice and this permission notice appear in all copies. - * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES - * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR - * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES - * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN - * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT - * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. - */ - - -/** - * @defgroup fal_qos FAL_QOS - * @{ - */ -#include "sw.h" -#include "fal_qos.h" -#include "hsl_api.h" -#include "adpt.h" - -#ifndef IN_QOS_MINI -static sw_error_t -_fal_qos_sch_mode_set(a_uint32_t dev_id, - fal_sch_mode_t mode, const a_uint32_t weight[]) -{ - sw_error_t rv; - hsl_api_t *p_api; - - SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id)); - - if (NULL == p_api->qos_sch_mode_set) - return SW_NOT_SUPPORTED; - - rv = p_api->qos_sch_mode_set(dev_id, mode, weight); - return rv; -} - - -static sw_error_t -_fal_qos_sch_mode_get(a_uint32_t dev_id, - fal_sch_mode_t * mode, a_uint32_t weight[]) -{ - sw_error_t rv; - hsl_api_t *p_api; - - SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id)); - - if (NULL == p_api->qos_sch_mode_get) - return SW_NOT_SUPPORTED; - - rv = p_api->qos_sch_mode_get(dev_id, mode, weight); - return rv; -} - - -static sw_error_t -_fal_qos_queue_tx_buf_status_set(a_uint32_t dev_id, fal_port_t port_id, - a_bool_t enable) -{ - sw_error_t rv; - hsl_api_t *p_api; - - SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id)); - - if (NULL == p_api->qos_queue_tx_buf_status_set) - return SW_NOT_SUPPORTED; - - rv = p_api->qos_queue_tx_buf_status_set(dev_id, port_id, enable); - return rv; -} - - -static sw_error_t -_fal_qos_queue_tx_buf_status_get(a_uint32_t dev_id, fal_port_t port_id, - a_bool_t * enable) -{ - sw_error_t rv; - hsl_api_t *p_api; - - SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id)); - - if (NULL == p_api->qos_queue_tx_buf_status_get) - return SW_NOT_SUPPORTED; - - rv = p_api->qos_queue_tx_buf_status_get(dev_id, port_id, enable); - return rv; -} - - - - -static sw_error_t -_fal_qos_queue_tx_buf_nr_get(a_uint32_t dev_id, fal_port_t port_id, - fal_queue_t queue_id, a_uint32_t * number) -{ - sw_error_t rv; - hsl_api_t *p_api; - - SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id)); - - if (NULL == p_api->qos_queue_tx_buf_nr_get) - return SW_NOT_SUPPORTED; - - rv = p_api->qos_queue_tx_buf_nr_get(dev_id, port_id, queue_id, number); - return rv; -} - - -static sw_error_t -_fal_qos_port_tx_buf_status_set(a_uint32_t dev_id, fal_port_t port_id, - a_bool_t enable) -{ - sw_error_t rv; - hsl_api_t *p_api; - - SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id)); - - if (NULL == p_api->qos_port_tx_buf_status_set) - return SW_NOT_SUPPORTED; - - rv = p_api->qos_port_tx_buf_status_set(dev_id, port_id, enable); - return rv; -} - - -static sw_error_t -_fal_qos_port_tx_buf_status_get(a_uint32_t dev_id, fal_port_t port_id, - a_bool_t * enable) -{ - sw_error_t rv; - hsl_api_t *p_api; - - SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id)); - - if (NULL == p_api->qos_port_tx_buf_status_get) - return SW_NOT_SUPPORTED; - - rv = p_api->qos_port_tx_buf_status_get(dev_id, port_id, enable); - return rv; -} - - - - - -static sw_error_t -_fal_qos_port_red_en_get(a_uint32_t dev_id, fal_port_t port_id, - a_bool_t* enable) -{ - sw_error_t rv; - hsl_api_t *p_api; - - SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id)); - - if (NULL == p_api->qos_port_red_en_get) - return SW_NOT_SUPPORTED; - - rv = p_api->qos_port_red_en_get(dev_id, port_id, enable); - return rv; -} - - - - -static sw_error_t -_fal_qos_port_tx_buf_nr_get(a_uint32_t dev_id, fal_port_t port_id, - a_uint32_t * number) -{ - sw_error_t rv; - hsl_api_t *p_api; - - SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id)); - - if (NULL == p_api->qos_port_tx_buf_nr_get) - return SW_NOT_SUPPORTED; - - rv = p_api->qos_port_tx_buf_nr_get(dev_id, port_id, number); - return rv; -} - - - - -static sw_error_t -_fal_qos_port_rx_buf_nr_get(a_uint32_t dev_id, fal_port_t port_id, - a_uint32_t * number) -{ - sw_error_t rv; - hsl_api_t *p_api; - - SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id)); - - if (NULL == p_api->qos_port_rx_buf_nr_get) - return SW_NOT_SUPPORTED; - - rv = p_api->qos_port_rx_buf_nr_get(dev_id, port_id, number); - return rv; -} - - -static sw_error_t -_fal_cosmap_up_queue_set(a_uint32_t dev_id, a_uint32_t up, fal_queue_t queue) -{ - sw_error_t rv; - hsl_api_t *p_api; - - SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id)); - - if (NULL == p_api->cosmap_up_queue_set) - return SW_NOT_SUPPORTED; - - rv = p_api->cosmap_up_queue_set(dev_id, up, queue); - return rv; -} - - -static sw_error_t -_fal_cosmap_up_queue_get(a_uint32_t dev_id, a_uint32_t up, - fal_queue_t * queue) -{ - sw_error_t rv; - hsl_api_t *p_api; - - SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id)); - - if (NULL == p_api->cosmap_up_queue_get) - return SW_NOT_SUPPORTED; - - rv = p_api->cosmap_up_queue_get(dev_id, up, queue); - return rv; -} - - -static sw_error_t -_fal_cosmap_dscp_queue_set(a_uint32_t dev_id, a_uint32_t dscp, fal_queue_t queue) -{ - sw_error_t rv; - hsl_api_t *p_api; - - SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id)); - - if (NULL == p_api->cosmap_dscp_queue_set) - return SW_NOT_SUPPORTED; - - rv = p_api->cosmap_dscp_queue_set(dev_id, dscp, queue); - return rv; -} - - -static sw_error_t -_fal_cosmap_dscp_queue_get(a_uint32_t dev_id, a_uint32_t dscp, - fal_queue_t * queue) -{ - sw_error_t rv; - hsl_api_t *p_api; - - SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id)); - - if (NULL == p_api->cosmap_dscp_queue_get) - return SW_NOT_SUPPORTED; - - rv = p_api->cosmap_dscp_queue_get(dev_id, dscp, queue); - return rv; -} -#endif -static sw_error_t -_fal_qos_port_red_en_set(a_uint32_t dev_id, fal_port_t port_id, - a_bool_t enable) -{ - sw_error_t rv; - hsl_api_t *p_api; - - SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id)); - - if (NULL == p_api->qos_port_red_en_set) - return SW_NOT_SUPPORTED; - - rv = p_api->qos_port_red_en_set(dev_id, port_id, enable); - return rv; -} -static sw_error_t -_fal_qos_queue_tx_buf_nr_set(a_uint32_t dev_id, fal_port_t port_id, - fal_queue_t queue_id, a_uint32_t * number) -{ - sw_error_t rv; - hsl_api_t *p_api; - - SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id)); - - if (NULL == p_api->qos_queue_tx_buf_nr_set) - return SW_NOT_SUPPORTED; - - rv = p_api->qos_queue_tx_buf_nr_set(dev_id, port_id, queue_id, number); - return rv; -} -static sw_error_t -_fal_qos_port_rx_buf_nr_set(a_uint32_t dev_id, fal_port_t port_id, - a_uint32_t * number) -{ - sw_error_t rv; - hsl_api_t *p_api; - - SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id)); - - if (NULL == p_api->qos_port_rx_buf_nr_set) - return SW_NOT_SUPPORTED; - - rv = p_api->qos_port_rx_buf_nr_set(dev_id, port_id, number); - return rv; -} -static sw_error_t -_fal_qos_port_tx_buf_nr_set(a_uint32_t dev_id, fal_port_t port_id, - a_uint32_t * number) -{ - sw_error_t rv; - hsl_api_t *p_api; - - SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id)); - - if (NULL == p_api->qos_port_tx_buf_nr_set) - return SW_NOT_SUPPORTED; - - rv = p_api->qos_port_tx_buf_nr_set(dev_id, port_id, number); - return rv; -} - -static sw_error_t -_fal_qos_port_mode_set(a_uint32_t dev_id, fal_port_t port_id, - fal_qos_mode_t mode, a_bool_t enable) -{ - sw_error_t rv; - hsl_api_t *p_api; - - SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id)); - - if (NULL == p_api->qos_port_mode_set) - return SW_NOT_SUPPORTED; - - rv = p_api->qos_port_mode_set(dev_id, port_id, mode, enable); - return rv; -} - - - - -#ifndef IN_QOS_MINI -static sw_error_t -_fal_qos_port_mode_get(a_uint32_t dev_id, fal_port_t port_id, - fal_qos_mode_t mode, a_bool_t * enable) -{ - sw_error_t rv; - hsl_api_t *p_api; - - SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id)); - - if (NULL == p_api->qos_port_mode_get) - return SW_NOT_SUPPORTED; - - rv = p_api->qos_port_mode_get(dev_id, port_id, mode, enable); - return rv; -} -static sw_error_t -_fal_qos_port_mode_pri_set(a_uint32_t dev_id, fal_port_t port_id, - fal_qos_mode_t mode, a_uint32_t pri) -{ - sw_error_t rv; - hsl_api_t *p_api; - adpt_api_t *p_adpt_api; - - if((p_adpt_api = adpt_api_ptr_get(dev_id)) != NULL) { - if (NULL == p_adpt_api->adpt_qos_port_mode_pri_set) - return SW_NOT_SUPPORTED; - rv = p_adpt_api->adpt_qos_port_mode_pri_set(dev_id, port_id, mode, pri); - return rv; - } - - SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id)); - - if (NULL == p_api->qos_port_mode_pri_set) - return SW_NOT_SUPPORTED; - - rv = p_api->qos_port_mode_pri_set(dev_id, port_id, mode, pri); - return rv; -} - - -static sw_error_t -_fal_qos_port_mode_pri_get(a_uint32_t dev_id, fal_port_t port_id, - fal_qos_mode_t mode, a_uint32_t * pri) -{ - sw_error_t rv; - hsl_api_t *p_api; - adpt_api_t *p_adpt_api; - - if((p_adpt_api = adpt_api_ptr_get(dev_id)) != NULL) { - if (NULL == p_adpt_api->adpt_qos_port_mode_pri_get) - return SW_NOT_SUPPORTED; - rv = p_adpt_api->adpt_qos_port_mode_pri_get(dev_id, port_id, mode, pri); - return rv; - } - - SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id)); - - if (NULL == p_api->qos_port_mode_pri_get) - return SW_NOT_SUPPORTED; - - rv = p_api->qos_port_mode_pri_get(dev_id, port_id, mode, pri); - return rv; -} - - -static sw_error_t -_fal_qos_port_default_up_set(a_uint32_t dev_id, fal_port_t port_id, - a_uint32_t up) -{ - sw_error_t rv; - hsl_api_t *p_api; - - SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id)); - - if (NULL == p_api->qos_port_default_up_set) - return SW_NOT_SUPPORTED; - - rv = p_api->qos_port_default_up_set(dev_id, port_id, up); - return rv; -} - - -static sw_error_t -_fal_qos_port_default_up_get(a_uint32_t dev_id, fal_port_t port_id, - a_uint32_t * up) -{ - sw_error_t rv; - hsl_api_t *p_api; - - SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id)); - - if (NULL == p_api->qos_port_default_up_get) - return SW_NOT_SUPPORTED; - - rv = p_api->qos_port_default_up_get(dev_id, port_id, up); - return rv; -} - -static sw_error_t -_fal_qos_port_sch_mode_set(a_uint32_t dev_id, a_uint32_t port_id, - fal_sch_mode_t mode, const a_uint32_t weight[]) -{ - sw_error_t rv; - hsl_api_t *p_api; - - SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id)); - - if (NULL == p_api->qos_port_sch_mode_set) - return SW_NOT_SUPPORTED; - - rv = p_api->qos_port_sch_mode_set(dev_id, port_id, mode, weight); - return rv; -} - - -static sw_error_t -_fal_qos_port_sch_mode_get(a_uint32_t dev_id, a_uint32_t port_id, - fal_sch_mode_t * mode, a_uint32_t weight[]) -{ - sw_error_t rv; - hsl_api_t *p_api; - - SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id)); - - if (NULL == p_api->qos_port_sch_mode_get) - return SW_NOT_SUPPORTED; - - rv = p_api->qos_port_sch_mode_get(dev_id, port_id, mode, weight); - return rv; -} - -static sw_error_t -_fal_qos_port_default_spri_set(a_uint32_t dev_id, fal_port_t port_id, - a_uint32_t spri) -{ - sw_error_t rv; - hsl_api_t *p_api; - - SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id)); - - if (NULL == p_api->qos_port_default_spri_set) - return SW_NOT_SUPPORTED; - - rv = p_api->qos_port_default_spri_set(dev_id, port_id, spri); - return rv; -} - -static sw_error_t -_fal_qos_port_default_spri_get(a_uint32_t dev_id, fal_port_t port_id, - a_uint32_t * spri) -{ - sw_error_t rv; - hsl_api_t *p_api; - - SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id)); - - if (NULL == p_api->qos_port_default_spri_get) - return SW_NOT_SUPPORTED; - - rv = p_api->qos_port_default_spri_get(dev_id, port_id, spri); - return rv; -} - -static sw_error_t -_fal_qos_port_default_cpri_set(a_uint32_t dev_id, fal_port_t port_id, - a_uint32_t cpri) -{ - sw_error_t rv; - hsl_api_t *p_api; - - SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id)); - - if (NULL == p_api->qos_port_default_cpri_set) - return SW_NOT_SUPPORTED; - - rv = p_api->qos_port_default_cpri_set(dev_id, port_id, cpri); - return rv; -} - -static sw_error_t -_fal_qos_port_default_cpri_get(a_uint32_t dev_id, fal_port_t port_id, - a_uint32_t * cpri) -{ - sw_error_t rv; - hsl_api_t *p_api; - - SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id)); - - if (NULL == p_api->qos_port_default_cpri_get) - return SW_NOT_SUPPORTED; - - rv = p_api->qos_port_default_cpri_get(dev_id, port_id, cpri); - return rv; -} - -static sw_error_t -_fal_qos_port_force_spri_status_set(a_uint32_t dev_id, fal_port_t port_id, - a_bool_t enable) -{ - sw_error_t rv; - hsl_api_t *p_api; - - SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id)); - - if (NULL == p_api->qos_port_force_spri_status_set) - return SW_NOT_SUPPORTED; - - rv = p_api->qos_port_force_spri_status_set(dev_id, port_id, enable); - return rv; -} - -static sw_error_t -_fal_qos_port_force_spri_status_get(a_uint32_t dev_id, fal_port_t port_id, - a_bool_t* enable) -{ - sw_error_t rv; - hsl_api_t *p_api; - - SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id)); - - if (NULL == p_api->qos_port_force_spri_status_get) - return SW_NOT_SUPPORTED; - - rv = p_api->qos_port_force_spri_status_get(dev_id, port_id, enable); - return rv; -} - -static sw_error_t -_fal_qos_port_force_cpri_status_set(a_uint32_t dev_id, fal_port_t port_id, - a_bool_t enable) -{ - sw_error_t rv; - hsl_api_t *p_api; - - SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id)); - - if (NULL == p_api->qos_port_force_cpri_status_set) - return SW_NOT_SUPPORTED; - - rv = p_api->qos_port_force_cpri_status_set(dev_id, port_id, enable); - return rv; -} - -static sw_error_t -_fal_qos_port_force_cpri_status_get(a_uint32_t dev_id, fal_port_t port_id, - a_bool_t* enable) -{ - sw_error_t rv; - hsl_api_t *p_api; - - SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id)); - - if (NULL == p_api->qos_port_force_cpri_status_get) - return SW_NOT_SUPPORTED; - - rv = p_api->qos_port_force_cpri_status_get(dev_id, port_id, enable); - return rv; -} - -static sw_error_t -_fal_qos_queue_remark_table_set(a_uint32_t dev_id, fal_port_t port_id, - fal_queue_t queue_id, a_uint32_t tbl_id, a_bool_t enable) -{ - sw_error_t rv; - hsl_api_t *p_api; - - SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id)); - - if (NULL == p_api->qos_queue_remark_table_set) - return SW_NOT_SUPPORTED; - - rv = p_api->qos_queue_remark_table_set(dev_id, port_id, queue_id, tbl_id, enable); - return rv; -} - -static sw_error_t -_fal_qos_queue_remark_table_get(a_uint32_t dev_id, fal_port_t port_id, - fal_queue_t queue_id, a_uint32_t * tbl_id, a_bool_t * enable) -{ - sw_error_t rv; - hsl_api_t *p_api; - - SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id)); - - if (NULL == p_api->qos_queue_remark_table_get) - return SW_NOT_SUPPORTED; - - rv = p_api->qos_queue_remark_table_get(dev_id, port_id, queue_id, tbl_id, enable); - return rv; -} -#endif - -sw_error_t -_fal_qos_port_pri_precedence_set(a_uint32_t dev_id, fal_port_t port_id, - fal_qos_pri_precedence_t *pri) -{ - adpt_api_t *p_api; - sw_error_t rv = SW_OK; - - SW_RTN_ON_NULL(p_api = adpt_api_ptr_get(dev_id)); - - if (NULL == p_api->adpt_qos_port_pri_set) - return SW_NOT_SUPPORTED; - - rv = p_api->adpt_qos_port_pri_set(dev_id, port_id, pri); - return rv; -} -sw_error_t -_fal_qos_port_pri_precedence_get(a_uint32_t dev_id, fal_port_t port_id, - fal_qos_pri_precedence_t *pri) -{ - adpt_api_t *p_api; - sw_error_t rv = SW_OK; - - SW_RTN_ON_NULL(p_api = adpt_api_ptr_get(dev_id)); - - if (NULL == p_api->adpt_qos_port_pri_get) - return SW_NOT_SUPPORTED; - - rv = p_api->adpt_qos_port_pri_get(dev_id, port_id, pri); - return rv; -} -sw_error_t -_fal_qos_cosmap_pcp_get(a_uint32_t dev_id, a_uint8_t group_id, - a_uint8_t pcp, fal_qos_cosmap_t *cosmap) -{ - adpt_api_t *p_api; - sw_error_t rv = SW_OK; - - SW_RTN_ON_NULL(p_api = adpt_api_ptr_get(dev_id)); - - if (NULL == p_api->adpt_qos_cosmap_pcp_get) - return SW_NOT_SUPPORTED; - - rv = p_api->adpt_qos_cosmap_pcp_get(dev_id, group_id, pcp, cosmap); - return rv; -} -sw_error_t -_fal_queue_scheduler_set(a_uint32_t dev_id, - a_uint32_t node_id, fal_queue_scheduler_level_t level, - fal_port_t port_id, - fal_qos_scheduler_cfg_t *scheduler_cfg) -{ - adpt_api_t *p_api; - sw_error_t rv = SW_OK; - - SW_RTN_ON_NULL(p_api = adpt_api_ptr_get(dev_id)); - - if (NULL == p_api->adpt_queue_scheduler_set) - return SW_NOT_SUPPORTED; - - rv = p_api->adpt_queue_scheduler_set(dev_id, node_id, - level, port_id, scheduler_cfg); - return rv; -} -sw_error_t -_fal_queue_scheduler_get(a_uint32_t dev_id, - a_uint32_t node_id, fal_queue_scheduler_level_t level, - fal_port_t *port_id, - fal_qos_scheduler_cfg_t *scheduler_cfg) -{ - adpt_api_t *p_api; - sw_error_t rv = SW_OK; - - SW_RTN_ON_NULL(p_api = adpt_api_ptr_get(dev_id)); - - if (NULL == p_api->adpt_queue_scheduler_get) - return SW_NOT_SUPPORTED; - - rv = p_api->adpt_queue_scheduler_get(dev_id, node_id, - level, port_id, scheduler_cfg); - return rv; -} -sw_error_t -_fal_qos_cosmap_pcp_set(a_uint32_t dev_id, a_uint8_t group_id, - a_uint8_t pcp, fal_qos_cosmap_t *cosmap) -{ - adpt_api_t *p_api; - sw_error_t rv = SW_OK; - - SW_RTN_ON_NULL(p_api = adpt_api_ptr_get(dev_id)); - - if (NULL == p_api->adpt_qos_cosmap_pcp_set) - return SW_NOT_SUPPORTED; - - rv = p_api->adpt_qos_cosmap_pcp_set(dev_id, group_id, pcp, cosmap); - return rv; -} -sw_error_t -_fal_qos_port_remark_get(a_uint32_t dev_id, fal_port_t port_id, - fal_qos_remark_enable_t *remark) -{ - adpt_api_t *p_api; - sw_error_t rv = SW_OK; - - SW_RTN_ON_NULL(p_api = adpt_api_ptr_get(dev_id)); - - if (NULL == p_api->adpt_qos_port_remark_get) - return SW_NOT_SUPPORTED; - - rv = p_api->adpt_qos_port_remark_get(dev_id, port_id, remark); - return rv; -} -sw_error_t -_fal_qos_cosmap_dscp_get(a_uint32_t dev_id, a_uint8_t group_id, - a_uint8_t dscp, fal_qos_cosmap_t *cosmap) -{ - adpt_api_t *p_api; - sw_error_t rv = SW_OK; - - SW_RTN_ON_NULL(p_api = adpt_api_ptr_get(dev_id)); - - if (NULL == p_api->adpt_qos_cosmap_dscp_get) - return SW_NOT_SUPPORTED; - - rv = p_api->adpt_qos_cosmap_dscp_get(dev_id, group_id, dscp, cosmap); - return rv; -} -sw_error_t -_fal_qos_cosmap_flow_set(a_uint32_t dev_id, a_uint8_t group_id, - a_uint16_t flow, fal_qos_cosmap_t *cosmap) -{ - adpt_api_t *p_api; - sw_error_t rv = SW_OK; - - SW_RTN_ON_NULL(p_api = adpt_api_ptr_get(dev_id)); - - if (NULL == p_api->adpt_qos_cosmap_flow_set) - return SW_NOT_SUPPORTED; - - rv = p_api->adpt_qos_cosmap_flow_set(dev_id, group_id, flow, cosmap); - return rv; -} -sw_error_t -_fal_qos_port_group_set(a_uint32_t dev_id, fal_port_t port_id, - fal_qos_group_t *group) -{ - adpt_api_t *p_api; - sw_error_t rv = SW_OK; - - SW_RTN_ON_NULL(p_api = adpt_api_ptr_get(dev_id)); - - if (NULL == p_api->adpt_qos_port_group_set) - return SW_NOT_SUPPORTED; - - rv = p_api->adpt_qos_port_group_set(dev_id, port_id, group); - return rv; -} -sw_error_t -_fal_edma_ring_queue_map_set(a_uint32_t dev_id, - a_uint32_t ring_id, fal_queue_bmp_t *queue_bmp) -{ - adpt_api_t *p_api; - sw_error_t rv = SW_OK; - - SW_RTN_ON_NULL(p_api = adpt_api_ptr_get(dev_id)); - - if (NULL == p_api->adpt_ring_queue_map_set) - return SW_NOT_SUPPORTED; - - rv = p_api->adpt_ring_queue_map_set(dev_id, ring_id, queue_bmp); - return rv; -} -sw_error_t -_fal_qos_cosmap_dscp_set(a_uint32_t dev_id, a_uint8_t group_id, - a_uint8_t dscp, fal_qos_cosmap_t *cosmap) -{ - adpt_api_t *p_api; - sw_error_t rv = SW_OK; - - SW_RTN_ON_NULL(p_api = adpt_api_ptr_get(dev_id)); - - if (NULL == p_api->adpt_qos_cosmap_dscp_set) - return SW_NOT_SUPPORTED; - - rv = p_api->adpt_qos_cosmap_dscp_set(dev_id, group_id, dscp, cosmap); - return rv; -} -sw_error_t -_fal_qos_port_remark_set(a_uint32_t dev_id, fal_port_t port_id, - fal_qos_remark_enable_t *remark) -{ - adpt_api_t *p_api; - sw_error_t rv = SW_OK; - - SW_RTN_ON_NULL(p_api = adpt_api_ptr_get(dev_id)); - - if (NULL == p_api->adpt_qos_port_remark_set) - return SW_NOT_SUPPORTED; - - rv = p_api->adpt_qos_port_remark_set(dev_id, port_id, remark); - return rv; -} - -sw_error_t -_fal_qos_cosmap_flow_get(a_uint32_t dev_id, a_uint8_t group_id, - a_uint16_t flow, fal_qos_cosmap_t *cosmap) -{ - adpt_api_t *p_api; - sw_error_t rv = SW_OK; - - SW_RTN_ON_NULL(p_api = adpt_api_ptr_get(dev_id)); - - if (NULL == p_api->adpt_qos_cosmap_flow_get) - return SW_NOT_SUPPORTED; - - rv = p_api->adpt_qos_cosmap_flow_get(dev_id, group_id, flow, cosmap); - return rv; -} -sw_error_t -_fal_qos_port_group_get(a_uint32_t dev_id, fal_port_t port_id, - fal_qos_group_t *group) -{ - adpt_api_t *p_api; - sw_error_t rv = SW_OK; - - SW_RTN_ON_NULL(p_api = adpt_api_ptr_get(dev_id)); - - if (NULL == p_api->adpt_qos_port_group_get) - return SW_NOT_SUPPORTED; - - rv = p_api->adpt_qos_port_group_get(dev_id, port_id, group); - return rv; -} -sw_error_t -_fal_edma_ring_queue_map_get(a_uint32_t dev_id, - a_uint32_t ring_id, fal_queue_bmp_t *queue_bmp) -{ - adpt_api_t *p_api; - sw_error_t rv = SW_OK; - - SW_RTN_ON_NULL(p_api = adpt_api_ptr_get(dev_id)); - - if (NULL == p_api->adpt_ring_queue_map_get) - return SW_NOT_SUPPORTED; - - rv = p_api->adpt_ring_queue_map_get(dev_id, ring_id, queue_bmp); - return rv; -} - -sw_error_t -_fal_port_queues_get(a_uint32_t dev_id, - fal_port_t port_id, fal_queue_bmp_t *queue_bmp) -{ - adpt_api_t *p_api; - sw_error_t rv = SW_OK; - - SW_RTN_ON_NULL(p_api = adpt_api_ptr_get(dev_id)); - - if (NULL == p_api->adpt_port_queues_get) - return SW_NOT_SUPPORTED; - - rv = p_api->adpt_port_queues_get(dev_id, port_id, queue_bmp); - return rv; -} - -sw_error_t -_fal_scheduler_dequeue_ctrl_set( - a_uint32_t dev_id, - a_uint32_t queue_id, - a_bool_t enable) -{ - adpt_api_t *p_api; - sw_error_t rv = SW_OK; - - SW_RTN_ON_NULL(p_api = adpt_api_ptr_get(dev_id)); - - if (NULL == p_api->adpt_scheduler_dequeue_ctrl_set) - return SW_NOT_SUPPORTED; - - rv = p_api->adpt_scheduler_dequeue_ctrl_set(dev_id, queue_id, enable); - return rv; -} - -sw_error_t -_fal_scheduler_dequeue_ctrl_get( - a_uint32_t dev_id, - a_uint32_t queue_id, - a_bool_t *enable) -{ - adpt_api_t *p_api; - sw_error_t rv = SW_OK; - - SW_RTN_ON_NULL(p_api = adpt_api_ptr_get(dev_id)); - - if (NULL == p_api->adpt_scheduler_dequeue_ctrl_get) - return SW_NOT_SUPPORTED; - - rv = p_api->adpt_scheduler_dequeue_ctrl_get(dev_id, queue_id, enable); - return rv; -} - -sw_error_t -_fal_port_scheduler_cfg_reset( - a_uint32_t dev_id, - fal_port_t port_id) -{ - adpt_api_t *p_api; - sw_error_t rv = SW_OK; - - SW_RTN_ON_NULL(p_api = adpt_api_ptr_get(dev_id)); - - if (NULL == p_api->adpt_port_scheduler_cfg_reset) - return SW_NOT_SUPPORTED; - - rv = p_api->adpt_port_scheduler_cfg_reset(dev_id, port_id); - return rv; -} - -sw_error_t -_fal_port_scheduler_resource_get( - a_uint32_t dev_id, - fal_port_t port_id, - fal_portscheduler_resource_t *cfg) -{ - adpt_api_t *p_api; - sw_error_t rv = SW_OK; - - SW_RTN_ON_NULL(p_api = adpt_api_ptr_get(dev_id)); - - if (NULL == p_api->adpt_port_scheduler_resource_get) - return SW_NOT_SUPPORTED; - - rv = p_api->adpt_port_scheduler_resource_get(dev_id, port_id, cfg); - return rv; -} -#ifndef IN_QOS_MINI -/*insert flag for inner fal, don't remove it*/ - -/** - * @brief Set traffic scheduling mode on particular one device. - * @details Comments: - * Particular device may only support parts of input options. Such as - * GARUDA doesn't support variable weight in wrr mode. - * When scheduling mode is sp the weight is meaningless usually it's zero - * @param[in] dev_id device id - * @param[in] fal_sch_mode_t traffic scheduling mode - * @param[in] weight[] weight value for each queue when in wrr mode - * @return SW_OK or error code - */ -sw_error_t -fal_qos_sch_mode_set(a_uint32_t dev_id, - fal_sch_mode_t mode, const a_uint32_t weight[]) -{ - sw_error_t rv; - - FAL_API_LOCK; - rv = _fal_qos_sch_mode_set(dev_id, mode, weight); - FAL_API_UNLOCK; - return rv; -} - -/** - * @brief Get traffic scheduling mode on particular device. - * @param[in] dev_id device id - * @param[in] fal_sch_mode_t traffic scheduling mode - * @param[out] weight weight value for wrr mode - * @return SW_OK or error code - */ -sw_error_t -fal_qos_sch_mode_get(a_uint32_t dev_id, - fal_sch_mode_t * mode, a_uint32_t weight[]) -{ - sw_error_t rv; - - FAL_API_LOCK; - rv = _fal_qos_sch_mode_get(dev_id, mode, weight); - FAL_API_UNLOCK; - return rv; -} - -/** - * @brief Set buffer aggsinment status of transmitting queue on one particular port. - * @details Comments: - * If enable queue tx buffer on one port that means each queue of this port - * will have fixed number buffers when transmitting packets. Otherwise they - * share the whole buffers with other queues in device. - * @param[in] dev_id device id - * @param[in] port_id port id - * @param[in] enable A_TRUE or A_FALSE - * @return SW_OK or error code - */ -sw_error_t -fal_qos_queue_tx_buf_status_set(a_uint32_t dev_id, fal_port_t port_id, - a_bool_t enable) -{ - sw_error_t rv; - - FAL_API_LOCK; - rv = _fal_qos_queue_tx_buf_status_set(dev_id, port_id, enable); - FAL_API_UNLOCK; - return rv; -} - -/** - * @brief Get buffer aggsinment status of transmitting queue on particular port. - * @param[in] dev_id device id - * @param[in] port_id port id - * @param[in] enable A_TRUE or A_FALSE - * @return SW_OK or error code - */ -sw_error_t -fal_qos_queue_tx_buf_status_get(a_uint32_t dev_id, fal_port_t port_id, - a_bool_t * enable) -{ - sw_error_t rv; - - FAL_API_LOCK; - rv = _fal_qos_queue_tx_buf_status_get(dev_id, port_id, enable); - FAL_API_UNLOCK; - return rv; -} - - - -/** - * @brief Get max occupied buffer number of transmitting queue on one particular port. - * @param[in] dev_id device id - * @param[in] port_id port id - * @param[in] queue_id queue id - * @param[out] number buffer number - * @return SW_OK or error code - */ -sw_error_t -fal_qos_queue_tx_buf_nr_get(a_uint32_t dev_id, fal_port_t port_id, - fal_queue_t queue_id, a_uint32_t * number) -{ - sw_error_t rv; - - FAL_API_LOCK; - rv = _fal_qos_queue_tx_buf_nr_get(dev_id, port_id, queue_id, number); - FAL_API_UNLOCK; - return rv; -} - -/** - * @brief Set buffer aggsinment status of transmitting port on one particular port. - * @details Comments: - * If enable tx buffer on one port that means this port will have fixed - * number buffers when transmitting packets. Otherwise they will - * share the whole buffers with other ports in device. - * @param[in] dev_id device id - * @param[in] port_id port id - * @param[in] enable A_TRUE or A_FALSE - * @return SW_OK or error code - */ -sw_error_t -fal_qos_port_tx_buf_status_set(a_uint32_t dev_id, fal_port_t port_id, - a_bool_t enable) -{ - sw_error_t rv; - - FAL_API_LOCK; - rv = _fal_qos_port_tx_buf_status_set(dev_id, port_id, enable); - FAL_API_UNLOCK; - return rv; -} - -/** - * @brief Get buffer aggsinment status of transmitting port on one particular port. - * @param[in] dev_id device id - * @param[in] port_id port id - * @param[out] enable A_TRUE or A_FALSE - * @return SW_OK or error code - */ -sw_error_t -fal_qos_port_tx_buf_status_get(a_uint32_t dev_id, fal_port_t port_id, - a_bool_t * enable) -{ - sw_error_t rv; - - FAL_API_LOCK; - rv = _fal_qos_port_tx_buf_status_get(dev_id, port_id, enable); - FAL_API_UNLOCK; - return rv; -} - - - -/** - * @brief Set status of port red on one particular port. - * @param[in] dev_id device id - * @param[in] port_id port id - * @param[in] enable A_TRUE or A_FALSE - * @return SW_OK or error code - */ -sw_error_t -fal_qos_port_red_en_get(a_uint32_t dev_id, fal_port_t port_id, - a_bool_t* enable) -{ - sw_error_t rv; - - FAL_API_LOCK; - rv = _fal_qos_port_red_en_get(dev_id, port_id, enable); - FAL_API_UNLOCK; - return rv; -} - - - - -/** - * @brief Get max occupied buffer number of transmitting port on one particular port. - * @param[in] dev_id device id - * @param[in] port_id port id - * @param[out] number buffer number - * @return SW_OK or error code - */ -sw_error_t -fal_qos_port_tx_buf_nr_get(a_uint32_t dev_id, fal_port_t port_id, - a_uint32_t * number) -{ - sw_error_t rv; - - FAL_API_LOCK; - rv = _fal_qos_port_tx_buf_nr_get(dev_id, port_id, number); - FAL_API_UNLOCK; - return rv; -} - - - -/** - * @brief Get max reserved buffer number of receiving port on one particular port. - * @param[in] dev_id device id - * @param[in] port_id port id - * @param[out] number buffer number - * @return SW_OK or error code - */ -sw_error_t -fal_qos_port_rx_buf_nr_get(a_uint32_t dev_id, fal_port_t port_id, - a_uint32_t * number) -{ - sw_error_t rv; - - FAL_API_LOCK; - rv = _fal_qos_port_rx_buf_nr_get(dev_id, port_id, number); - FAL_API_UNLOCK; - return rv; -} - -/** - * @brief Set user priority to queue mapping. - * @param[in] dev_id device id - * @param[in] up 802.1p - * @param[in] queue queue id - * @return SW_OK or error code - */ -sw_error_t -fal_cosmap_up_queue_set(a_uint32_t dev_id, a_uint32_t up, fal_queue_t queue) -{ - sw_error_t rv; - - FAL_API_LOCK; - rv = _fal_cosmap_up_queue_set(dev_id, up, queue); - FAL_API_UNLOCK; - return rv; -} - -/** - * @brief Get user priority to queue mapping. - * @param[in] dev_id device id - * @param[in] dot1p 802.1p - * @param[out] queue queue id - * @return SW_OK or error code - */ -sw_error_t -fal_cosmap_up_queue_get(a_uint32_t dev_id, a_uint32_t up, - fal_queue_t * queue) -{ - sw_error_t rv; - - FAL_API_LOCK; - rv = _fal_cosmap_up_queue_get(dev_id, up, queue); - FAL_API_UNLOCK; - return rv; -} - -/** - * @brief Set cos map dscp_2_queue item on one particular device. - * @param[in] dev_id device id - * @param[in] dscp dscp - * @param[in] queue queue id - * @return SW_OK or error code - */ -sw_error_t -fal_cosmap_dscp_queue_set(a_uint32_t dev_id, a_uint32_t dscp, fal_queue_t queue) -{ - sw_error_t rv; - - FAL_API_LOCK; - rv = _fal_cosmap_dscp_queue_set(dev_id, dscp, queue); - FAL_API_UNLOCK; - return rv; -} - -/** - * @brief Get cos map dscp_2_queue item on one particular device. - * @param[in] dev_id device id - * @param[in] dscp dscp - * @param[out] queue queue id - * @return SW_OK or error code - */ -sw_error_t -fal_cosmap_dscp_queue_get(a_uint32_t dev_id, a_uint32_t dscp, - fal_queue_t * queue) -{ - sw_error_t rv; - - FAL_API_LOCK; - rv = _fal_cosmap_dscp_queue_get(dev_id, dscp, queue); - FAL_API_UNLOCK; - return rv; -} -#endif -/** - * @brief Set max occupied buffer number of transmitting queue on one particular port. - * @details Comments: - * Because different device has differnet hardware granularity - * function will return actual buffer numbers in hardware. - * @param[in] dev_id device id - * @param[in] port_id port id - * @param[in] queue_id queue id - * @param number buffer number - * @return SW_OK or error code - */ -sw_error_t -fal_qos_queue_tx_buf_nr_set(a_uint32_t dev_id, fal_port_t port_id, - fal_queue_t queue_id, a_uint32_t * number) -{ - sw_error_t rv; - - FAL_API_LOCK; - rv = _fal_qos_queue_tx_buf_nr_set(dev_id, port_id, queue_id, number); - FAL_API_UNLOCK; - return rv; -} -/** - * @brief Set status of port red on one particular port. - * @param[in] dev_id device id - * @param[in] port_id port id - * @param[in] enable A_TRUE or A_FALSE - * @return SW_OK or error code - */ -sw_error_t -fal_qos_port_red_en_set(a_uint32_t dev_id, fal_port_t port_id, - a_bool_t enable) -{ - sw_error_t rv; - - FAL_API_LOCK; - rv = _fal_qos_port_red_en_set(dev_id, port_id, enable); - FAL_API_UNLOCK; - return rv; -} -/** - * @brief Set max occupied buffer number of transmitting port on one particular port. - * @details Comments: - * Because different device has differnet hardware granularity - * function will return actual buffer number in hardware. - * @param[in] dev_id device id - * @param[in] port_id port id - * @param number buffer number - * @return SW_OK or error code - */ -sw_error_t -fal_qos_port_tx_buf_nr_set(a_uint32_t dev_id, fal_port_t port_id, - a_uint32_t * number) -{ - sw_error_t rv; - - FAL_API_LOCK; - rv = _fal_qos_port_tx_buf_nr_set(dev_id, port_id, number); - FAL_API_UNLOCK; - return rv; -} -/** - * @brief Set max reserved buffer number of receiving port on one particular port. - * @details Comments: - * Because different device has differnet hardware granularity - * function will return actual buffer number in hardware. - * @param[in] dev_id device id - * @param[in] port_id port id - * @param number buffer number - * @return SW_OK or error code - */ -sw_error_t -fal_qos_port_rx_buf_nr_set(a_uint32_t dev_id, fal_port_t port_id, - a_uint32_t * number) -{ - sw_error_t rv; - - FAL_API_LOCK; - rv = _fal_qos_port_rx_buf_nr_set(dev_id, port_id, number); - FAL_API_UNLOCK; - return rv; -} -/** - * @brief Set port qos mode on one particular port. - * @param[in] dev_id device id - * @param[in] port_id port id - * @param[in] mode qos mode - * @param[in] enable A_TRUE of A_FALSE - * @return SW_OK or error code - */ -sw_error_t -fal_qos_port_mode_set(a_uint32_t dev_id, fal_port_t port_id, - fal_qos_mode_t mode, a_bool_t enable) -{ - sw_error_t rv; - - FAL_API_LOCK; - rv = _fal_qos_port_mode_set(dev_id, port_id, mode, enable); - FAL_API_UNLOCK; - return rv; -} - - -#ifndef IN_QOS_MINI -/** - * @brief Get port qos mode on one particular port. - * @param[in] dev_id device id - * @param[in] port_id port id - * @param[in] mode qos mode - * @param[out] enable A_TRUE of A_FALSE - * @return SW_OK or error code - */ -sw_error_t -fal_qos_port_mode_get(a_uint32_t dev_id, fal_port_t port_id, - fal_qos_mode_t mode, a_bool_t * enable) -{ - sw_error_t rv; - - FAL_API_LOCK; - rv = _fal_qos_port_mode_get(dev_id, port_id, mode, enable); - FAL_API_UNLOCK; - return rv; -} -/** - * @brief Set priority of one particular qos mode on one particular port. - * @details Comments: - * If the priority of a mode is more small then the priority is more high. - * @param[in] dev_id device id - * @param[in] port_id port id - * @param[in] mode qos mode - * @param[in] pri priority of one particular qos mode - * @return SW_OK or error code - */ -sw_error_t -fal_qos_port_mode_pri_set(a_uint32_t dev_id, fal_port_t port_id, - fal_qos_mode_t mode, a_uint32_t pri) -{ - sw_error_t rv; - - FAL_API_LOCK; - rv = _fal_qos_port_mode_pri_set(dev_id, port_id, mode, pri); - FAL_API_UNLOCK; - return rv; -} - -/** - * @brief Get priority of one particular qos mode on one particular port. - * @param[in] dev_id device id - * @param[in] port_id port id - * @param[in] mode qos mode - * @param[out] pri priority of one particular qos mode - * @return SW_OK or error code - */ -sw_error_t -fal_qos_port_mode_pri_get(a_uint32_t dev_id, fal_port_t port_id, - fal_qos_mode_t mode, a_uint32_t * pri) -{ - sw_error_t rv; - - FAL_API_LOCK; - rv = _fal_qos_port_mode_pri_get(dev_id, port_id, mode, pri); - FAL_API_UNLOCK; - return rv; -} - -/** - * @brief Set default user priority on one particular port. - * @param[in] dev_id device id - * @param[in] port_id port id - * @param[in] up 802.1p - * @return SW_OK or error code - */ -sw_error_t -fal_qos_port_default_up_set(a_uint32_t dev_id, fal_port_t port_id, - a_uint32_t up) -{ - sw_error_t rv; - - FAL_API_LOCK; - rv = _fal_qos_port_default_up_set(dev_id, port_id, up); - FAL_API_UNLOCK; - return rv; -} - -/** - * @brief Get default user priority on one particular port. - * @param[in] dev_id device id - * @param[in] port_id port id - * @param[out] up 802.1p - * @return SW_OK or error code - */ -sw_error_t -fal_qos_port_default_up_get(a_uint32_t dev_id, fal_port_t port_id, - a_uint32_t * up) -{ - sw_error_t rv; - - FAL_API_LOCK; - rv = _fal_qos_port_default_up_get(dev_id, port_id, up); - FAL_API_UNLOCK; - return rv; -} - -/** - * @brief Set traffic scheduling mode on particular one port. - * @details Comments: - * Particular device may only support parts of input options. Such as - * GARUDA doesn't support variable weight in wrr mode. - * When scheduling mode is sp the weight is meaningless usually it's zero - * @param[in] dev_id device id - * @param[in] fal_sch_mode_t traffic scheduling mode - * @param[in] weight[] weight value for each queue when in wrr mode - * @return SW_OK or error code - */ -sw_error_t -fal_qos_port_sch_mode_set(a_uint32_t dev_id, a_uint32_t port_id, - fal_sch_mode_t mode, const a_uint32_t weight[]) -{ - sw_error_t rv; - - FAL_API_LOCK; - rv = _fal_qos_port_sch_mode_set(dev_id, port_id, mode, weight); - FAL_API_UNLOCK; - return rv; -} - -/** - * @brief Get traffic scheduling mode on particular port. - * @param[in] dev_id device id - * @param[in] fal_sch_mode_t traffic scheduling mode - * @param[out] weight weight value for wrr mode - * @return SW_OK or error code - */ -sw_error_t -fal_qos_port_sch_mode_get(a_uint32_t dev_id, a_uint32_t port_id, - fal_sch_mode_t * mode, a_uint32_t weight[]) -{ - sw_error_t rv; - - FAL_API_LOCK; - rv = _fal_qos_port_sch_mode_get(dev_id, port_id, mode, weight); - FAL_API_UNLOCK; - return rv; -} - -/** - * @brief Set default stag priority on one particular port. - * @param[in] dev_id device id - * @param[in] port_id port id - * @param[in] spri vlan priority - * @return SW_OK or error code - */ -sw_error_t -fal_qos_port_default_spri_set(a_uint32_t dev_id, fal_port_t port_id, - a_uint32_t spri) -{ - sw_error_t rv; - - FAL_API_LOCK; - rv = _fal_qos_port_default_spri_set(dev_id, port_id, spri); - FAL_API_UNLOCK; - return rv; -} - -/** - * @brief Get default stag priority on one particular port. - * @param[in] dev_id device id - * @param[in] port_id port id - * @param[out] spri vlan priority - * @return SW_OK or error code - */ -sw_error_t -fal_qos_port_default_spri_get(a_uint32_t dev_id, fal_port_t port_id, - a_uint32_t * spri) -{ - sw_error_t rv; - - FAL_API_LOCK; - rv = _fal_qos_port_default_spri_get(dev_id, port_id, spri); - FAL_API_UNLOCK; - return rv; -} - -/** - * @brief Set default ctag priority on one particular port. - * @param[in] dev_id device id - * @param[in] port_id port id - * @param[in] cpri vlan priority - * @return SW_OK or error code - */ -sw_error_t -fal_qos_port_default_cpri_set(a_uint32_t dev_id, fal_port_t port_id, - a_uint32_t cpri) -{ - sw_error_t rv; - - FAL_API_LOCK; - rv = _fal_qos_port_default_cpri_set(dev_id, port_id, cpri); - FAL_API_UNLOCK; - return rv; -} - -/** - * @brief Get default ctag priority on one particular port. - * @param[in] dev_id device id - * @param[in] port_id port id - * @param[out] cpri vlan priority - * @return SW_OK or error code - */ -sw_error_t -fal_qos_port_default_cpri_get(a_uint32_t dev_id, fal_port_t port_id, - a_uint32_t * cpri) -{ - sw_error_t rv; - - FAL_API_LOCK; - rv = _fal_qos_port_default_cpri_get(dev_id, port_id, cpri); - FAL_API_UNLOCK; - return rv; -} - -/** - * @brief Set force stag priority flag on one particular port. - * @param[in] dev_id device id - * @param[in] port_id port id - * @param[in] enable A_TRUE or A_FALSE - * @return SW_OK or error code - */ -sw_error_t -fal_qos_port_force_spri_status_set(a_uint32_t dev_id, fal_port_t port_id, - a_bool_t enable) -{ - sw_error_t rv; - - FAL_API_LOCK; - rv = _fal_qos_port_force_spri_status_set(dev_id, port_id, enable); - FAL_API_UNLOCK; - return rv; -} - - -/** - * @brief Get force stag priority flag on one particular port. - * @param[in] dev_id device id - * @param[in] port_id port id - * @param[out] enable A_TRUE or A_FALSE - * @return SW_OK or error code - */ -sw_error_t -fal_qos_port_force_spri_status_get(a_uint32_t dev_id, fal_port_t port_id, - a_bool_t* enable) -{ - sw_error_t rv; - - FAL_API_LOCK; - rv = _fal_qos_port_force_spri_status_get(dev_id, port_id, enable); - FAL_API_UNLOCK; - return rv; -} - -/** - * @brief Set force ctag priority flag on one particular port. - * @param[in] dev_id device id - * @param[in] port_id port id - * @param[in] enable A_TRUE or A_FALSE - * @return SW_OK or error code - */ -sw_error_t -fal_qos_port_force_cpri_status_set(a_uint32_t dev_id, fal_port_t port_id, - a_bool_t enable) -{ - sw_error_t rv; - - FAL_API_LOCK; - rv = _fal_qos_port_force_cpri_status_set(dev_id, port_id, enable); - FAL_API_UNLOCK; - return rv; -} - -/** - * @brief Get force ctag priority flag on one particular port. - * @param[in] dev_id device id - * @param[in] port_id port id - * @param[out] enable A_TRUE or A_FALSE - * @return SW_OK or error code - */ -sw_error_t -fal_qos_port_force_cpri_status_get(a_uint32_t dev_id, fal_port_t port_id, - a_bool_t* enable) -{ - sw_error_t rv; - - FAL_API_LOCK; - rv = _fal_qos_port_force_cpri_status_get(dev_id, port_id, enable); - FAL_API_UNLOCK; - return rv; -} - -/** - * @brief Set egress queue based CoS remark on one particular port. - * @param[in] dev_id device id - * @param[in] port_id port id - * @param[in] queue_id queue id - * @param[in] tbl_id CoS remark table id - * @param[in] enable A_TRUE or A_FALSE - * @return SW_OK or error code - */ -sw_error_t -fal_qos_queue_remark_table_set(a_uint32_t dev_id, fal_port_t port_id, - fal_queue_t queue_id, a_uint32_t tbl_id, a_bool_t enable) -{ - sw_error_t rv; - - FAL_API_LOCK; - rv = _fal_qos_queue_remark_table_set(dev_id, port_id, queue_id, tbl_id, enable); - FAL_API_UNLOCK; - return rv; -} - -/** - * @brief Get egress queue based CoS remark on one particular port. - * @param[in] dev_id device id - * @param[in] port_id port id - * @param[in] queue_id queue id - * @param[out] tbl_id CoS remark table id - * @param[out] enable A_TRUE or A_FALSE - * @return SW_OK or error code - */ - -sw_error_t -fal_qos_queue_remark_table_get(a_uint32_t dev_id, fal_port_t port_id, - fal_queue_t queue_id, a_uint32_t * tbl_id, a_bool_t * enable) -{ - sw_error_t rv; - - FAL_API_LOCK; - rv = _fal_qos_queue_remark_table_get(dev_id, port_id, queue_id, tbl_id, enable); - FAL_API_UNLOCK; - return rv; -} -#endif - -sw_error_t -fal_qos_port_pri_precedence_set(a_uint32_t dev_id, fal_port_t port_id, - fal_qos_pri_precedence_t *pri) -{ - sw_error_t rv = SW_OK; - - FAL_API_LOCK; - rv = _fal_qos_port_pri_precedence_set(dev_id, port_id, pri); - FAL_API_UNLOCK; - return rv; -} -sw_error_t -fal_qos_port_pri_precedence_get(a_uint32_t dev_id, fal_port_t port_id, - fal_qos_pri_precedence_t *pri) -{ - sw_error_t rv = SW_OK; - - FAL_API_LOCK; - rv = _fal_qos_port_pri_precedence_get(dev_id, port_id, pri); - FAL_API_UNLOCK; - return rv; -} -sw_error_t -fal_qos_cosmap_pcp_get(a_uint32_t dev_id, a_uint8_t group_id, - a_uint8_t pcp, fal_qos_cosmap_t *cosmap) -{ - sw_error_t rv = SW_OK; - - FAL_API_LOCK; - rv = _fal_qos_cosmap_pcp_get(dev_id, group_id, pcp, cosmap); - FAL_API_UNLOCK; - return rv; -} -sw_error_t -fal_queue_scheduler_set(a_uint32_t dev_id, - a_uint32_t node_id, fal_queue_scheduler_level_t level, - fal_port_t port_id, - fal_qos_scheduler_cfg_t *scheduler_cfg) -{ - sw_error_t rv = SW_OK; - - FAL_API_LOCK; - rv = _fal_queue_scheduler_set(dev_id, node_id, level, port_id, scheduler_cfg); - FAL_API_UNLOCK; - return rv; -} -sw_error_t -fal_queue_scheduler_get(a_uint32_t dev_id, - a_uint32_t node_id, fal_queue_scheduler_level_t level, - fal_port_t *port_id, - fal_qos_scheduler_cfg_t *scheduler_cfg) -{ - sw_error_t rv = SW_OK; - - FAL_API_LOCK; - rv = _fal_queue_scheduler_get(dev_id, node_id, level, port_id, scheduler_cfg); - FAL_API_UNLOCK; - return rv; -} -sw_error_t -fal_qos_cosmap_pcp_set(a_uint32_t dev_id, a_uint8_t group_id, - a_uint8_t pcp, fal_qos_cosmap_t *cosmap) -{ - sw_error_t rv = SW_OK; - - FAL_API_LOCK; - rv = _fal_qos_cosmap_pcp_set(dev_id, group_id, pcp, cosmap); - FAL_API_UNLOCK; - return rv; -} -sw_error_t -fal_qos_port_remark_get(a_uint32_t dev_id, fal_port_t port_id, - fal_qos_remark_enable_t *remark) -{ - sw_error_t rv = SW_OK; - - FAL_API_LOCK; - rv = _fal_qos_port_remark_get(dev_id, port_id, remark); - FAL_API_UNLOCK; - return rv; -} -sw_error_t -fal_qos_cosmap_dscp_get(a_uint32_t dev_id, a_uint8_t group_id, - a_uint8_t dscp, fal_qos_cosmap_t *cosmap) -{ - sw_error_t rv = SW_OK; - - FAL_API_LOCK; - rv = _fal_qos_cosmap_dscp_get(dev_id, group_id, dscp, cosmap); - FAL_API_UNLOCK; - return rv; -} -sw_error_t -fal_qos_cosmap_flow_set(a_uint32_t dev_id, a_uint8_t group_id, - a_uint16_t flow, fal_qos_cosmap_t *cosmap) -{ - sw_error_t rv = SW_OK; - - FAL_API_LOCK; - rv = _fal_qos_cosmap_flow_set(dev_id, group_id, flow, cosmap); - FAL_API_UNLOCK; - return rv; -} -sw_error_t -fal_qos_port_group_set(a_uint32_t dev_id, fal_port_t port_id, - fal_qos_group_t *group) -{ - sw_error_t rv = SW_OK; - - FAL_API_LOCK; - rv = _fal_qos_port_group_set(dev_id, port_id, group); - FAL_API_UNLOCK; - return rv; -} -sw_error_t -fal_edma_ring_queue_map_set(a_uint32_t dev_id, - a_uint32_t ring_id, fal_queue_bmp_t *queue_bmp) -{ - sw_error_t rv = SW_OK; - - FAL_API_LOCK; - rv = _fal_edma_ring_queue_map_set(dev_id, ring_id, queue_bmp); - FAL_API_UNLOCK; - return rv; -} -sw_error_t -fal_qos_cosmap_dscp_set(a_uint32_t dev_id, a_uint8_t group_id, - a_uint8_t dscp, fal_qos_cosmap_t *cosmap) -{ - sw_error_t rv = SW_OK; - - FAL_API_LOCK; - rv = _fal_qos_cosmap_dscp_set(dev_id, group_id, dscp, cosmap); - FAL_API_UNLOCK; - return rv; -} -sw_error_t -fal_qos_port_remark_set(a_uint32_t dev_id, fal_port_t port_id, - fal_qos_remark_enable_t *remark) -{ - sw_error_t rv = SW_OK; - - FAL_API_LOCK; - rv = _fal_qos_port_remark_set(dev_id, port_id, remark); - FAL_API_UNLOCK; - return rv; -} - -sw_error_t -fal_qos_cosmap_flow_get(a_uint32_t dev_id, a_uint8_t group_id, - a_uint16_t flow, fal_qos_cosmap_t *cosmap) -{ - sw_error_t rv = SW_OK; - - FAL_API_LOCK; - rv = _fal_qos_cosmap_flow_get(dev_id, group_id, flow, cosmap); - FAL_API_UNLOCK; - return rv; -} -sw_error_t -fal_qos_port_group_get(a_uint32_t dev_id, fal_port_t port_id, - fal_qos_group_t *group) -{ - sw_error_t rv = SW_OK; - - FAL_API_LOCK; - rv = _fal_qos_port_group_get(dev_id, port_id, group); - FAL_API_UNLOCK; - return rv; -} -sw_error_t -fal_edma_ring_queue_map_get(a_uint32_t dev_id, - a_uint32_t ring_id, fal_queue_bmp_t *queue_bmp) -{ - sw_error_t rv = SW_OK; - - FAL_API_LOCK; - rv = _fal_edma_ring_queue_map_get(dev_id, ring_id, queue_bmp); - FAL_API_UNLOCK; - return rv; -} - -sw_error_t -fal_port_queues_get(a_uint32_t dev_id, - fal_port_t port_id, fal_queue_bmp_t *queue_bmp) -{ - sw_error_t rv = SW_OK; - - FAL_API_LOCK; - rv = _fal_port_queues_get(dev_id, port_id, queue_bmp); - FAL_API_UNLOCK; - return rv; -} - -sw_error_t -fal_scheduler_dequeue_ctrl_set( - a_uint32_t dev_id, - a_uint32_t queue_id, - a_bool_t enable) -{ - sw_error_t rv = SW_OK; - - FAL_API_LOCK; - rv = _fal_scheduler_dequeue_ctrl_set(dev_id, queue_id, enable); - FAL_API_UNLOCK; - return rv; -} - -sw_error_t -fal_scheduler_dequeue_ctrl_get( - a_uint32_t dev_id, - a_uint32_t queue_id, - a_bool_t *enable) -{ - sw_error_t rv = SW_OK; - - FAL_API_LOCK; - rv = _fal_scheduler_dequeue_ctrl_get(dev_id, queue_id, enable); - FAL_API_UNLOCK; - return rv; -} - -sw_error_t -fal_port_scheduler_cfg_reset( - a_uint32_t dev_id, - fal_port_t port_id) -{ - sw_error_t rv = SW_OK; - - FAL_API_LOCK; - rv = _fal_port_scheduler_cfg_reset(dev_id, port_id); - FAL_API_UNLOCK; - return rv; -} - -sw_error_t -fal_port_scheduler_resource_get( - a_uint32_t dev_id, - fal_port_t port_id, - fal_portscheduler_resource_t *cfg) -{ - sw_error_t rv = SW_OK; - - FAL_API_LOCK; - rv = _fal_port_scheduler_resource_get(dev_id, port_id, cfg); - FAL_API_UNLOCK; - return rv; -} - -EXPORT_SYMBOL(fal_scheduler_dequeue_ctrl_get); - -EXPORT_SYMBOL(fal_scheduler_dequeue_ctrl_set); - -EXPORT_SYMBOL(fal_queue_scheduler_set); - -EXPORT_SYMBOL(fal_queue_scheduler_get); - -EXPORT_SYMBOL(fal_port_queues_get); - -EXPORT_SYMBOL(fal_qos_port_pri_precedence_set); - -EXPORT_SYMBOL(fal_qos_port_pri_precedence_get); - -EXPORT_SYMBOL(fal_qos_port_group_set); - -EXPORT_SYMBOL(fal_qos_port_group_get); - -EXPORT_SYMBOL(fal_qos_cosmap_pcp_set); - -EXPORT_SYMBOL(fal_qos_cosmap_pcp_get); - -EXPORT_SYMBOL(fal_qos_cosmap_dscp_set); - -EXPORT_SYMBOL(fal_qos_cosmap_dscp_get); - -EXPORT_SYMBOL(fal_qos_cosmap_flow_set); - -EXPORT_SYMBOL(fal_qos_port_remark_set); - -EXPORT_SYMBOL(fal_qos_port_remark_get); - -EXPORT_SYMBOL(fal_edma_ring_queue_map_set); - -EXPORT_SYMBOL(fal_edma_ring_queue_map_get); - -EXPORT_SYMBOL(fal_port_scheduler_cfg_reset); - -EXPORT_SYMBOL(fal_port_scheduler_resource_get); - -/*insert flag for outter fal, don't remove it*/ -/** - * @} - */ diff --git a/feeds/ipq807x/qca-ssdk/src/src/fal/fal_rate.c b/feeds/ipq807x/qca-ssdk/src/src/fal/fal_rate.c deleted file mode 100755 index 1298837ac..000000000 --- a/feeds/ipq807x/qca-ssdk/src/src/fal/fal_rate.c +++ /dev/null @@ -1,840 +0,0 @@ -/* - * Copyright (c) 2012, The Linux Foundation. All rights reserved. - * Permission to use, copy, modify, and/or distribute this software for - * any purpose with or without fee is hereby granted, provided that the - * above copyright notice and this permission notice appear in all copies. - * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES - * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR - * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES - * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN - * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT - * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. - */ - - -/** - * @defgroup fal_rate FAL_RATE - * @{ - */ -#include "sw.h" -#include "fal_rate.h" -#include "hsl_api.h" - - -static sw_error_t -_fal_rate_queue_egrl_set(a_uint32_t dev_id, fal_port_t port_id, - fal_queue_t queue_id, a_uint32_t * speed, - a_bool_t enable) -{ - sw_error_t rv; - hsl_api_t *p_api; - - SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id)); - - if (NULL == p_api->rate_queue_egrl_set) - return SW_NOT_SUPPORTED; - - rv = p_api->rate_queue_egrl_set(dev_id, port_id, queue_id, speed, enable); - return rv; -} - - -static sw_error_t -_fal_rate_queue_egrl_get(a_uint32_t dev_id, fal_port_t port_id, - fal_queue_t queue_id, a_uint32_t * speed, - a_bool_t * enable) -{ - sw_error_t rv; - hsl_api_t *p_api; - - SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id)); - - if (NULL == p_api->rate_queue_egrl_get) - return SW_NOT_SUPPORTED; - - rv = p_api->rate_queue_egrl_get(dev_id, port_id, queue_id, speed, enable); - return rv; -} - - -static sw_error_t -_fal_rate_port_egrl_set(a_uint32_t dev_id, fal_port_t port_id, - a_uint32_t * speed, a_bool_t enable) -{ - sw_error_t rv; - hsl_api_t *p_api; - - SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id)); - - if (NULL == p_api->rate_port_egrl_set) - return SW_NOT_SUPPORTED; - - rv = p_api->rate_port_egrl_set(dev_id, port_id, speed, enable); - return rv; -} - - -static sw_error_t -_fal_rate_port_egrl_get(a_uint32_t dev_id, fal_port_t port_id, - a_uint32_t * speed, a_bool_t * enable) -{ - sw_error_t rv; - hsl_api_t *p_api; - - SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id)); - - if (NULL == p_api->rate_port_egrl_get) - return SW_NOT_SUPPORTED; - - rv = p_api->rate_port_egrl_get(dev_id, port_id, speed, enable); - return rv; -} - - -static sw_error_t -_fal_rate_port_inrl_set(a_uint32_t dev_id, fal_port_t port_id, - a_uint32_t * speed, a_bool_t enable) -{ - sw_error_t rv; - hsl_api_t *p_api; - - SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id)); - - if (NULL == p_api->rate_port_inrl_set) - return SW_NOT_SUPPORTED; - - rv = p_api->rate_port_inrl_set(dev_id, port_id, speed, enable); - return rv; -} - - -static sw_error_t -_fal_rate_port_inrl_get(a_uint32_t dev_id, fal_port_t port_id, - a_uint32_t * speed, a_bool_t * enable) -{ - sw_error_t rv; - hsl_api_t *p_api; - - SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id)); - - if (NULL == p_api->rate_port_inrl_get) - return SW_NOT_SUPPORTED; - - rv = p_api->rate_port_inrl_get(dev_id, port_id, speed, enable); - return rv; -} - - -static sw_error_t -_fal_storm_ctrl_frame_set(a_uint32_t dev_id, fal_port_t port_id, - fal_storm_type_t frame_type, a_bool_t enable) -{ - sw_error_t rv; - hsl_api_t *p_api; - - SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id)); - - if (NULL == p_api->storm_ctrl_frame_set) - return SW_NOT_SUPPORTED; - - rv = p_api->storm_ctrl_frame_set(dev_id, port_id, frame_type, enable); - return rv; -} - - -static sw_error_t -_fal_storm_ctrl_frame_get(a_uint32_t dev_id, fal_port_t port_id, - fal_storm_type_t frame_type, a_bool_t * enable) -{ - sw_error_t rv; - hsl_api_t *p_api; - - SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id)); - - if (NULL == p_api->storm_ctrl_frame_get) - return SW_NOT_SUPPORTED; - - rv = p_api->storm_ctrl_frame_get(dev_id, port_id, frame_type, enable); - return rv; -} - - -static sw_error_t -_fal_storm_ctrl_rate_set(a_uint32_t dev_id, fal_port_t port_id, - a_uint32_t * rate) -{ - sw_error_t rv; - hsl_api_t *p_api; - - SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id)); - - if (NULL == p_api->storm_ctrl_rate_set) - return SW_NOT_SUPPORTED; - - rv = p_api->storm_ctrl_rate_set(dev_id, port_id, rate); - return rv; -} - - -static sw_error_t -_fal_storm_ctrl_rate_get(a_uint32_t dev_id, fal_port_t port_id, - a_uint32_t * rate) -{ - sw_error_t rv; - hsl_api_t *p_api; - - SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id)); - - if (NULL == p_api->storm_ctrl_rate_get) - return SW_NOT_SUPPORTED; - - rv = p_api->storm_ctrl_rate_get(dev_id, port_id, rate); - return rv; -} - -static sw_error_t -_fal_rate_port_policer_set(a_uint32_t dev_id, fal_port_t port_id, - fal_port_policer_t * policer) -{ - sw_error_t rv; - hsl_api_t *p_api; - - SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id)); - - if (NULL == p_api->rate_port_policer_set) - return SW_NOT_SUPPORTED; - - rv = p_api->rate_port_policer_set(dev_id, port_id, policer); - return rv; -} - -static sw_error_t -_fal_rate_port_policer_get(a_uint32_t dev_id, fal_port_t port_id, - fal_port_policer_t * policer) -{ - sw_error_t rv; - hsl_api_t *p_api; - - SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id)); - - if (NULL == p_api->rate_port_policer_get) - return SW_NOT_SUPPORTED; - - rv = p_api->rate_port_policer_get(dev_id, port_id, policer); - return rv; -} - -static sw_error_t -_fal_rate_port_shaper_set(a_uint32_t dev_id, fal_port_t port_id, - a_bool_t enable, fal_egress_shaper_t * shaper) -{ - sw_error_t rv; - hsl_api_t *p_api; - - SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id)); - - if (NULL == p_api->rate_port_shaper_set) - return SW_NOT_SUPPORTED; - - rv = p_api->rate_port_shaper_set(dev_id, port_id, enable, shaper); - return rv; -} - -static sw_error_t -_fal_rate_port_shaper_get(a_uint32_t dev_id, fal_port_t port_id, - a_bool_t * enable, fal_egress_shaper_t * shaper) -{ - sw_error_t rv; - hsl_api_t *p_api; - - SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id)); - - if (NULL == p_api->rate_port_shaper_get) - return SW_NOT_SUPPORTED; - - rv = p_api->rate_port_shaper_get(dev_id, port_id, enable, shaper); - return rv; -} - -static sw_error_t -_fal_rate_queue_shaper_set(a_uint32_t dev_id, fal_port_t port_id, - fal_queue_t queue_id, a_bool_t enable, - fal_egress_shaper_t * shaper) -{ - sw_error_t rv; - hsl_api_t *p_api; - - SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id)); - - if (NULL == p_api->rate_queue_shaper_set) - return SW_NOT_SUPPORTED; - - rv = p_api->rate_queue_shaper_set(dev_id, port_id, queue_id, enable, shaper); - return rv; -} - -static sw_error_t -_fal_rate_queue_shaper_get(a_uint32_t dev_id, fal_port_t port_id, - fal_queue_t queue_id, a_bool_t * enable, - fal_egress_shaper_t * shaper) -{ - sw_error_t rv; - hsl_api_t *p_api; - - SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id)); - - if (NULL == p_api->rate_queue_shaper_get) - return SW_NOT_SUPPORTED; - - rv = p_api->rate_queue_shaper_get(dev_id, port_id, queue_id, enable, shaper); - return rv; -} - -static sw_error_t -_fal_rate_acl_policer_set(a_uint32_t dev_id, a_uint32_t policer_id, - fal_acl_policer_t * policer) -{ - sw_error_t rv; - hsl_api_t *p_api; - - SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id)); - - if (NULL == p_api->rate_acl_policer_set) - return SW_NOT_SUPPORTED; - - rv = p_api->rate_acl_policer_set(dev_id, policer_id, policer); - return rv; -} - -static sw_error_t -_fal_rate_acl_policer_get(a_uint32_t dev_id, a_uint32_t policer_id, - fal_acl_policer_t * policer) -{ - sw_error_t rv; - hsl_api_t *p_api; - - SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id)); - - if (NULL == p_api->rate_acl_policer_get) - return SW_NOT_SUPPORTED; - - rv = p_api->rate_acl_policer_get(dev_id, policer_id, policer); - return rv; -} - -sw_error_t -_fal_rate_port_add_rate_byte_set(a_uint32_t dev_id, fal_port_t port_id, - a_uint32_t number) -{ - sw_error_t rv; - hsl_api_t *p_api; - - SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id)); - - if (NULL == p_api->rate_port_add_rate_byte_set) - return SW_NOT_SUPPORTED; - - rv = p_api->rate_port_add_rate_byte_set(dev_id, port_id, number); - return rv; -} - -sw_error_t -_fal_rate_port_add_rate_byte_get(a_uint32_t dev_id, fal_port_t port_id, - a_uint32_t *number) -{ - sw_error_t rv; - hsl_api_t *p_api; - - SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id)); - - if (NULL == p_api->rate_port_add_rate_byte_set) - return SW_NOT_SUPPORTED; - - rv = p_api->rate_port_add_rate_byte_get(dev_id, port_id, number); - return rv; -} - -sw_error_t -_fal_rate_port_gol_flow_en_set(a_uint32_t dev_id, fal_port_t port_id, - a_bool_t enable) -{ - sw_error_t rv; - hsl_api_t *p_api; - - SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id)); - - if (NULL == p_api->rate_port_gol_flow_en_set) - return SW_NOT_SUPPORTED; - - rv = p_api->rate_port_gol_flow_en_set(dev_id, port_id, enable); - return rv; -} - -sw_error_t -_fal_rate_port_gol_flow_en_get(a_uint32_t dev_id, fal_port_t port_id, - a_bool_t *enable) -{ - sw_error_t rv; - hsl_api_t *p_api; - - SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id)); - - if (NULL == p_api->rate_port_gol_flow_en_get) - return SW_NOT_SUPPORTED; - - rv = p_api->rate_port_gol_flow_en_get(dev_id, port_id, enable); - return rv; -} - - - -/** - * @brief Set queue egress rate limit status on one particular port and queue. - * @details Comments: - * The granularity of speed is bps. - * Because different device has differnet hardware granularity function - * will return actual speed in hardware. - * When disable queue egress rate limit input parameter speed is meaningless. - * @param[in] dev_id device id - * @param[in] port_id port id - * @param[in] queue_id queue id - * @param speed rate limit speed - * @param[in] enable A_TRUE or A_FALSE - * @return SW_OK or error code - */ -sw_error_t -fal_rate_queue_egrl_set(a_uint32_t dev_id, fal_port_t port_id, - fal_queue_t queue_id, a_uint32_t * speed, - a_bool_t enable) -{ - sw_error_t rv; - - FAL_API_LOCK; - rv = _fal_rate_queue_egrl_set(dev_id, port_id, queue_id, speed, enable); - FAL_API_UNLOCK; - return rv; -} - -/** - * @brief Get queue egress rate limit status on one particular port and queue. - * @param[in] dev_id device id - * @param[in] port_id port id - * @param[in] queue_id queue id - * @param[out] speed rate limit speed - * @param[out] enable A_TRUE or A_FALSE - * @return SW_OK or error code - */ -sw_error_t -fal_rate_queue_egrl_get(a_uint32_t dev_id, fal_port_t port_id, - fal_queue_t queue_id, a_uint32_t * speed, - a_bool_t * enable) -{ - sw_error_t rv; - - FAL_API_LOCK; - rv = _fal_rate_queue_egrl_get(dev_id, port_id, queue_id, speed, enable); - FAL_API_UNLOCK; - return rv; -} - -/** - * @brief Set port egress rate limit status on one particular port. - * @details Comments: - * The granularity of speed is bps. - * Because different device has differnet hardware granularity function - * will return actual speed in hardware. - * When disable port egress rate limit input parameter speed is meaningless. - * @param[in] dev_id device id - * @param[in] port_id port id - * @param speed rate limit speed - * @param[in] enable A_TRUE or A_FALSE - * @return SW_OK or error code - */ -sw_error_t -fal_rate_port_egrl_set(a_uint32_t dev_id, fal_port_t port_id, - a_uint32_t * speed, a_bool_t enable) -{ - sw_error_t rv; - - FAL_API_LOCK; - rv = _fal_rate_port_egrl_set(dev_id, port_id, speed, enable); - FAL_API_UNLOCK; - return rv; -} - -/** - * @brief Get port egress rate limit status on one particular port. - * @param[in] dev_id device id - * @param[in] port_id port id - * @param[out] speed rate limit speed - * @param[out] enable A_TRUE or A_FALSE - * @return SW_OK or error code - */ -sw_error_t -fal_rate_port_egrl_get(a_uint32_t dev_id, fal_port_t port_id, - a_uint32_t * speed, a_bool_t * enable) -{ - sw_error_t rv; - - FAL_API_LOCK; - rv = _fal_rate_port_egrl_get(dev_id, port_id, speed, enable); - FAL_API_UNLOCK; - return rv; -} - -/** - * @brief Set port ingress rate limit status on one particular port. - * @details Comments: - * The granularity of speed is bps. - * Because different device has differnet hardware granularity function - * will return actual speed in hardware. - * When disable port ingress rate limit input parameter speed is meaningless. - * @param[in] dev_id device id - * @param[in] port_id port id - * @param speed rate limit speed - * @param[in] enable A_TRUE or A_FALSE - * @return SW_OK or error code - */ -sw_error_t -fal_rate_port_inrl_set(a_uint32_t dev_id, fal_port_t port_id, - a_uint32_t * speed, a_bool_t enable) -{ - sw_error_t rv; - - FAL_API_LOCK; - rv = _fal_rate_port_inrl_set(dev_id, port_id, speed, enable); - FAL_API_UNLOCK; - return rv; -} - -/** - * @brief Get port ingress rate limit status on one particular port. - * @param[in] dev_id device id - * @param[in] port_id port id - * @param[out] speed rate limit speed - * @param[out] enable A_TRUE or A_FALSE - * @return SW_OK or error code - */ -sw_error_t -fal_rate_port_inrl_get(a_uint32_t dev_id, fal_port_t port_id, - a_uint32_t * speed, a_bool_t * enable) -{ - sw_error_t rv; - - FAL_API_LOCK; - rv = _fal_rate_port_inrl_get(dev_id, port_id, speed, enable); - FAL_API_UNLOCK; - return rv; -} - -/** - * @brief Set particular type storm control status on one particular port. - * @details Comments: - * When enable one particular packets type storm control this type packets - * speed will be calculated in storm control. - * @param[in] dev_id device id - * @param[in] port_id port id - * @param[in] frame_type packets type which causes storm - * @param[in] enable A_TRUE or A_FALSE - * @return SW_OK or error code - */ -sw_error_t -fal_storm_ctrl_frame_set(a_uint32_t dev_id, fal_port_t port_id, - fal_storm_type_t frame_type, a_bool_t enable) -{ - sw_error_t rv; - - FAL_API_LOCK; - rv = _fal_storm_ctrl_frame_set(dev_id, port_id, frame_type, enable); - FAL_API_UNLOCK; - return rv; -} - -/** - * @brief Get particular type storm control status on one particular port. - * @param[in] dev_id device id - * @param[in] port_id port id - * @param[in] frame_type packets type which causes storm - * @param[out] enable A_TRUE or A_FALSE - * @return SW_OK or error code - */ -sw_error_t -fal_storm_ctrl_frame_get(a_uint32_t dev_id, fal_port_t port_id, - fal_storm_type_t frame_type, a_bool_t * enable) -{ - sw_error_t rv; - - FAL_API_LOCK; - rv = _fal_storm_ctrl_frame_get(dev_id, port_id, frame_type, enable); - FAL_API_UNLOCK; - return rv; -} - -/** - * @brief Set storm control speed on one particular port. - * @details Comments: - * The granularity of speed is packets per second. - * Because different device has differnet hardware granularity function - * will return actual speed in hardware. - * @param[in] dev_id device id - * @param[in] port_id port id - * @param speed storm control speed - * @return SW_OK or error code - */ -sw_error_t -fal_storm_ctrl_rate_set(a_uint32_t dev_id, fal_port_t port_id, - a_uint32_t * rate) -{ - sw_error_t rv; - - FAL_API_LOCK; - rv = _fal_storm_ctrl_rate_set(dev_id, port_id, rate); - FAL_API_UNLOCK; - return rv; -} - -/** - * @brief Get storm control speed on one particular port. - * @param[in] dev_id device id - * @param[in] port_id port id - * @param[out] speed storm control speed - * @return SW_OK or error code - */ -sw_error_t -fal_storm_ctrl_rate_get(a_uint32_t dev_id, fal_port_t port_id, - a_uint32_t * rate) -{ - sw_error_t rv; - - FAL_API_LOCK; - rv = _fal_storm_ctrl_rate_get(dev_id, port_id, rate); - FAL_API_UNLOCK; - return rv; -} - -/** - * @brief Set port ingress policer parameters on one particular port. - * @param[in] dev_id device id - * @param[in] port_id port id - * @param[in] policer port ingress policer parameter - * @return SW_OK or error code - */ -sw_error_t -fal_rate_port_policer_set(a_uint32_t dev_id, fal_port_t port_id, - fal_port_policer_t * policer) -{ - sw_error_t rv; - - FAL_API_LOCK; - rv = _fal_rate_port_policer_set(dev_id, port_id, policer); - FAL_API_UNLOCK; - return rv; -} - -/** - * @brief Get port ingress policer parameters on one particular port. - * @param[in] dev_id device id - * @param[in] port_id port id - * @param[out] policer port ingress policer parameter - * @return SW_OK or error code - */ -sw_error_t -fal_rate_port_policer_get(a_uint32_t dev_id, fal_port_t port_id, - fal_port_policer_t * policer) -{ - sw_error_t rv; - - FAL_API_LOCK; - rv = _fal_rate_port_policer_get(dev_id, port_id, policer); - FAL_API_UNLOCK; - return rv; -} - -/** - * @brief Set port egress shaper parameters on one particular port. - * @param[in] port_id port id - * @param[in] enable A_TRUE or A_FALSE - * @param[in] shaper port egress shaper parameter - * @return SW_OK or error code - */ -sw_error_t -fal_rate_port_shaper_set(a_uint32_t dev_id, fal_port_t port_id, - a_bool_t enable, fal_egress_shaper_t * shaper) -{ - sw_error_t rv; - - FAL_API_LOCK; - rv = _fal_rate_port_shaper_set(dev_id, port_id, enable, shaper); - FAL_API_UNLOCK; - return rv; -} - -/** - * @brief Get port egress shaper parameters on one particular port. - * @param[in] dev_id device id - * @param[in] port_id port id - * @param[out] enable A_TRUE or A_FALSE - * @param[out] shaper port egress shaper parameter - * @return SW_OK or error code - */ -sw_error_t -fal_rate_port_shaper_get(a_uint32_t dev_id, fal_port_t port_id, - a_bool_t * enable, fal_egress_shaper_t * shaper) -{ - sw_error_t rv; - - FAL_API_LOCK; - rv = _fal_rate_port_shaper_get(dev_id, port_id, enable, shaper); - FAL_API_UNLOCK; - return rv; -} - -/** - * @brief Set queue egress shaper parameters on one particular port. - * @param[in] port_id port id - * @param[in] queue_id queue id - * @param[in] enable A_TRUE or A_FALSE - * @param[in] shaper port egress shaper parameter - * @return SW_OK or error code - */ -sw_error_t -fal_rate_queue_shaper_set(a_uint32_t dev_id, fal_port_t port_id, - fal_queue_t queue_id, a_bool_t enable, - fal_egress_shaper_t * shaper) -{ - sw_error_t rv; - - FAL_API_LOCK; - rv = _fal_rate_queue_shaper_set(dev_id, port_id, queue_id, enable, shaper); - FAL_API_UNLOCK; - return rv; -} - -/** - * @brief Get queue egress shaper parameters on one particular port. - * @param[in] port_id port id - * @param[in] queue_id queue id - * @param[out] enable A_TRUE or A_FALSE - * @param[out] shaper port egress shaper parameter - * @return SW_OK or error code - */ -sw_error_t -fal_rate_queue_shaper_get(a_uint32_t dev_id, fal_port_t port_id, - fal_queue_t queue_id, a_bool_t * enable, - fal_egress_shaper_t * shaper) -{ - sw_error_t rv; - - FAL_API_LOCK; - rv = _fal_rate_queue_shaper_get(dev_id, port_id, queue_id, enable, shaper); - FAL_API_UNLOCK; - return rv; -} - -/** - * @brief Set ACL ingress policer parameters. - * @param[in] dev_id device id - * @param[in] policer_id ACL policer id - * @param[in] policer ACL ingress policer parameters - * @return SW_OK or error code - */ -sw_error_t -fal_rate_acl_policer_set(a_uint32_t dev_id, a_uint32_t policer_id, - fal_acl_policer_t * policer) -{ - sw_error_t rv; - - FAL_API_LOCK; - rv = _fal_rate_acl_policer_set(dev_id, policer_id, policer); - FAL_API_UNLOCK; - return rv; -} - -/** - * @brief Get ACL ingress policer parameters. - * @param[in] dev_id device id - * @param[in] policer_id ACL policer id - * @param[in] policer ACL ingress policer parameters - * @return SW_OK or error code - */ -sw_error_t -fal_rate_acl_policer_get(a_uint32_t dev_id, a_uint32_t policer_id, - fal_acl_policer_t * policer) -{ - sw_error_t rv; - - FAL_API_LOCK; - rv = _fal_rate_acl_policer_get(dev_id, policer_id, policer); - FAL_API_UNLOCK; - return rv; -} - - -sw_error_t -fal_rate_port_add_rate_byte_set(a_uint32_t dev_id, fal_port_t port_id, - a_uint32_t number) -{ - sw_error_t rv; - - FAL_API_LOCK; - rv = _fal_rate_port_add_rate_byte_set(dev_id, port_id, number); - FAL_API_UNLOCK; - return rv; -} - -sw_error_t -fal_rate_port_add_rate_byte_get(a_uint32_t dev_id, fal_port_t port_id, - a_uint32_t *number) -{ - sw_error_t rv; - - FAL_API_LOCK; - rv = _fal_rate_port_add_rate_byte_get(dev_id, port_id, number); - FAL_API_UNLOCK; - return rv; -} - -/** - * @brief Set status of port global flow control when global threshold is reached. - * @param[in] dev_id device id - * @param[in] port_id port id - * @param[in] enable A_TRUE or A_FALSE - * @return SW_OK or error code - */ -sw_error_t -fal_rate_port_gol_flow_en_set(a_uint32_t dev_id, fal_port_t port_id, - a_bool_t enable) -{ - sw_error_t rv; - - FAL_API_LOCK; - rv = _fal_rate_port_gol_flow_en_set(dev_id, port_id, enable); - FAL_API_UNLOCK; - return rv; -} - -/** - * @brief get status of port global flow control when global threshold is reached. - * @param[in] dev_id device id - * @param[in] port_id port id - * @param[out] enable A_TRUE or A_FALSE - * @return SW_OK or error code - */ -sw_error_t -fal_rate_port_gol_flow_en_get(a_uint32_t dev_id, fal_port_t port_id, - a_bool_t* enable) -{ - sw_error_t rv; - - FAL_API_LOCK; - rv = _fal_rate_port_gol_flow_en_get(dev_id, port_id, enable); - FAL_API_UNLOCK; - return rv; -} - - - -/** - * @} - */ diff --git a/feeds/ipq807x/qca-ssdk/src/src/fal/fal_reg_access.c b/feeds/ipq807x/qca-ssdk/src/src/fal/fal_reg_access.c deleted file mode 100755 index c578def79..000000000 --- a/feeds/ipq807x/qca-ssdk/src/src/fal/fal_reg_access.c +++ /dev/null @@ -1,570 +0,0 @@ -/* - * Copyright (c) 2012, 2017-2018, The Linux Foundation. All rights reserved. - * Permission to use, copy, modify, and/or distribute this software for - * any purpose with or without fee is hereby granted, provided that the - * above copyright notice and this permission notice appear in all copies. - * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES - * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR - * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES - * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN - * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT - * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. - */ - -/*qca808x_start*/ -/** - * @defgroup fal_reg_access FAL_REG_ACCESS - * @{ - */ -#include "sw.h" -#include "fal_reg_access.h" -#include "hsl_api.h" -#include "hsl_phy.h" - -static sw_error_t -_fal_phy_get(a_uint32_t dev_id, a_uint32_t phy_addr, - a_uint32_t reg, a_uint16_t * value) -{ - sw_error_t rv; - hsl_api_t *p_api; - a_uint8_t phy_addr_type; - hsl_phy_get phy_get_func; - - SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id)); - - /* the MSB first byte of phy_addr marks the type of - * phy address, such as the i2c address, the value of - * MSB first byte should be 1 */ - phy_addr_type = (phy_addr & 0xff000000) >> 24; - phy_addr = phy_addr & 0xff; - switch (phy_addr_type) { - case PHY_I2C_ACCESS: - phy_get_func = p_api->phy_i2c_get; - break; - default: - phy_get_func = p_api->phy_get; - break; - } - - if (NULL == phy_get_func) { - return SW_NOT_SUPPORTED; - } - - rv = phy_get_func(dev_id, phy_addr, reg, value); - return rv; -} - -static sw_error_t -_fal_phy_set(a_uint32_t dev_id, a_uint32_t phy_addr, - a_uint32_t reg, a_uint16_t value) -{ - sw_error_t rv; - hsl_api_t *p_api; - a_uint8_t phy_addr_type; - hsl_phy_set phy_set_func; - - SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id)); - - /* the MSB first byte of phy_addr marks the type of - * phy address, such as the i2c address, the value of - * MSB first byte should be 1 */ - phy_addr_type = (phy_addr & 0xff000000) >> 24; - phy_addr = phy_addr & 0xff; - switch (phy_addr_type) { - case PHY_I2C_ACCESS: - phy_set_func = p_api->phy_i2c_set; - break; - default: - phy_set_func = p_api->phy_set; - break; - } - - if (NULL == phy_set_func) { - return SW_NOT_SUPPORTED; - } - - rv = phy_set_func(dev_id, phy_addr, reg, value); - return rv; -} -/*qca808x_end*/ -static sw_error_t -_fal_reg_get(a_uint32_t dev_id, a_uint32_t reg_addr, a_uint8_t value[], - a_uint32_t value_len) -{ - sw_error_t rv; - hsl_api_t *p_api; - - SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id)); - - if (NULL == p_api->reg_get) - return SW_NOT_SUPPORTED; - - rv = p_api->reg_get(dev_id, reg_addr, value, value_len); - return rv; -} - -static sw_error_t -_fal_reg_set(a_uint32_t dev_id, a_uint32_t reg_addr, a_uint8_t value[], - a_uint32_t value_len) -{ - sw_error_t rv; - hsl_api_t *p_api; - - SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id)); - - if (NULL == p_api->reg_set) - return SW_NOT_SUPPORTED; - - rv = p_api->reg_set(dev_id, reg_addr, value, value_len); - return rv; -} - - -static sw_error_t -_fal_psgmii_reg_get(a_uint32_t dev_id, a_uint32_t reg_addr, a_uint8_t value[], - a_uint32_t value_len) -{ - sw_error_t rv; - hsl_api_t *p_api; - - SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id)); - - if (NULL == p_api->psgmii_reg_get) - return SW_NOT_SUPPORTED; - - rv = p_api->psgmii_reg_get(dev_id, reg_addr, value, value_len); - return rv; -} - -static sw_error_t -_fal_psgmii_reg_set(a_uint32_t dev_id, a_uint32_t reg_addr, a_uint8_t value[], - a_uint32_t value_len) -{ - sw_error_t rv; - hsl_api_t *p_api; - - SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id)); - - if (NULL == p_api->psgmii_reg_set) - return SW_NOT_SUPPORTED; - - rv = p_api->psgmii_reg_set(dev_id, reg_addr, value, value_len); - return rv; -} - -static sw_error_t -_fal_reg_field_get(a_uint32_t dev_id, a_uint32_t reg_addr, - a_uint32_t bit_offset, a_uint32_t field_len, - a_uint8_t value[], a_uint32_t value_len) -{ - sw_error_t rv; - hsl_api_t *p_api; - - SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id)); - - if (NULL == p_api->reg_field_get) - return SW_NOT_SUPPORTED; - - rv = p_api->reg_field_get(dev_id, reg_addr, bit_offset, field_len, value, value_len); - return rv; -} - -static sw_error_t -_fal_reg_field_set(a_uint32_t dev_id, a_uint32_t reg_addr, - a_uint32_t bit_offset, a_uint32_t field_len, - const a_uint8_t value[], a_uint32_t value_len) -{ - sw_error_t rv; - hsl_api_t *p_api; - - SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id)); - - if (NULL == p_api->reg_field_set) - return SW_NOT_SUPPORTED; - - rv = p_api->reg_field_set(dev_id, reg_addr, bit_offset, field_len, value, value_len); - return rv; -} - -static sw_error_t -_fal_reg_dump(a_uint32_t dev_id, a_uint32_t reg_idx,fal_reg_dump_t *reg_dump) -{ - sw_error_t rv; - hsl_api_t *p_api; - - SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id)); - - if (NULL == p_api->register_dump) - return SW_NOT_SUPPORTED; - - rv = p_api->register_dump(dev_id, reg_idx,reg_dump); - return rv; -} - - -static sw_error_t -_fal_debug_reg_dump(a_uint32_t dev_id, fal_debug_reg_dump_t *reg_dump) -{ - sw_error_t rv; - hsl_api_t *p_api; - - SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id)); - - if (NULL == p_api->debug_register_dump) - return SW_NOT_SUPPORTED; - - rv = p_api->debug_register_dump(dev_id, reg_dump); - return rv; -} - -static sw_error_t -_fal_debug_psgmii_self_test(a_uint32_t dev_id, a_bool_t enable, - a_uint32_t times, a_uint32_t *result) -{ - sw_error_t rv; - hsl_api_t *p_api; - - SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id)); - - if (NULL == p_api->debug_psgmii_self_test) - return SW_NOT_SUPPORTED; - - rv = p_api->debug_psgmii_self_test(dev_id, enable, times, result); - return rv; -} - -static sw_error_t -_fal_phy_dump(a_uint32_t dev_id, a_uint32_t phy_addr, a_uint32_t idx,fal_phy_dump_t *phy_dump) -{ - sw_error_t rv; - hsl_api_t *p_api; - - SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id)); - - if (NULL == p_api->phy_dump) - return SW_NOT_SUPPORTED; - - rv = p_api->phy_dump(dev_id, phy_addr,idx,phy_dump); - return rv; -} -static sw_error_t -_fal_uniphy_reg_get(a_uint32_t dev_id, a_uint32_t index, a_uint32_t reg_addr, - a_uint8_t value[], a_uint32_t value_len) -{ - sw_error_t rv; - hsl_api_t *p_api; - - SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id)); - - if (NULL == p_api->uniphy_reg_get) - return SW_NOT_SUPPORTED; - - rv = p_api->uniphy_reg_get(dev_id, index, reg_addr, value, value_len); - return rv; -} - -static sw_error_t -_fal_uniphy_reg_set(a_uint32_t dev_id, a_uint32_t index, a_uint32_t reg_addr, - a_uint8_t value[], a_uint32_t value_len) -{ - sw_error_t rv; - hsl_api_t *p_api; - - SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id)); - - if (NULL == p_api->uniphy_reg_set) - return SW_NOT_SUPPORTED; - - rv = p_api->uniphy_reg_set(dev_id, index, reg_addr, value, value_len); - return rv; -} -/*qca808x_start*/ -/** - * fal_phy_get - get value of specific phy device - * @phy_addr: id of the phy device - * @reg: register id of phy device - * @value: pointer to the memory storing the value. - * @return SW_OK or error code - */ -sw_error_t -fal_phy_get(a_uint32_t dev_id, a_uint32_t phy_addr, - a_uint32_t reg, a_uint16_t * value) -{ - sw_error_t rv; - - FAL_API_LOCK; - rv = _fal_phy_get(dev_id, phy_addr, reg, value); - FAL_API_UNLOCK; - return rv; -} - -/** - * fal_phy_set - set value of specific phy device - * @phy_addr: id of the phy device - * @reg: register id of phy device - * @value: register value. - * @return SW_OK or error code - */ -sw_error_t -fal_phy_set(a_uint32_t dev_id, a_uint32_t phy_addr, - a_uint32_t reg, a_uint16_t value) -{ - sw_error_t rv; - - FAL_API_LOCK; - rv = _fal_phy_set(dev_id, phy_addr, reg, value); - FAL_API_UNLOCK; - return rv; -} -/*qca808x_end*/ -/** - * fal_reg_get - get value of specific register - * @reg_addr: address of the register - * @value: pointer to the memory storing the value. - * @value_len: length of the value. - * - * Get the value of a specific register field with related parameter - */ -sw_error_t -fal_reg_get(a_uint32_t dev_id, a_uint32_t reg_addr, a_uint8_t value[], - a_uint32_t value_len) -{ - sw_error_t rv; - - FAL_API_LOCK; - rv = _fal_reg_get(dev_id, reg_addr, value, value_len); - FAL_API_UNLOCK; - return rv; -} - -/** - * fal_reg_set - set value of specific register - * @reg_addr: address of the register - * @value: pointer to the memory storing the value. - * @value_len: length of the value. - * - * Get the value of a specific register field with related parameter - */ -sw_error_t -fal_reg_set(a_uint32_t dev_id, a_uint32_t reg_addr, a_uint8_t value[], - a_uint32_t value_len) -{ - sw_error_t rv; - - FAL_API_LOCK; - rv = _fal_reg_set(dev_id, reg_addr, value, value_len); - FAL_API_UNLOCK; - return rv; -} - -/** - * fal_psgmii_reg_get - get value of specific register in psgmii module - * @reg_addr: address of the register - * @value: pointer to the memory storing the value. - * @value_len: length of the value. - * - * Get the value of a specific register field with related parameter - */ -sw_error_t -fal_psgmii_reg_get(a_uint32_t dev_id, a_uint32_t reg_addr, a_uint8_t value[], - a_uint32_t value_len) -{ - sw_error_t rv; - - FAL_API_LOCK; - rv = _fal_psgmii_reg_get(dev_id, reg_addr, value, value_len); - FAL_API_UNLOCK; - return rv; -} - -/** - * fal_psgmii_reg_set - set value of specific register in psgmii module - * @reg_addr: address of the register - * @value: pointer to the memory storing the value. - * @value_len: length of the value. - * - * Get the value of a specific register field with related parameter - */ -sw_error_t -fal_psgmii_reg_set(a_uint32_t dev_id, a_uint32_t reg_addr, a_uint8_t value[], - a_uint32_t value_len) -{ - sw_error_t rv; - - FAL_API_LOCK; - rv = _fal_psgmii_reg_set(dev_id, reg_addr, value, value_len); - FAL_API_UNLOCK; - return rv; -} - -/** - * fal_reg_field_get - get value of specific register field - * @reg_addr: address of the register - * @bit_offset: position of the field in bit - * @field_len: length of the field in bit - * @value: pointer to the memory storing the value. - * @value_len: length of the value. - * - * Get the value of a specific register field with related parameter - */ -sw_error_t -fal_reg_field_get(a_uint32_t dev_id, a_uint32_t reg_addr, - a_uint32_t bit_offset, a_uint32_t field_len, - a_uint8_t value[], a_uint32_t value_len) -{ - sw_error_t rv; - - FAL_API_LOCK; - rv = _fal_reg_field_get(dev_id, reg_addr, bit_offset, field_len, value, value_len); - FAL_API_UNLOCK; - return rv; -} - -/** - * fal_reg_field_set - set value of specific register field - * @reg_addr: address of the register - * @bit_offset: position of the field in bit - * @field_len: length of the field in bit - * @value: pointer to the memory storing the value. - * @value_len: length of the value. - * - * Set the value of a specific register field with related parameter - */ -sw_error_t -fal_reg_field_set(a_uint32_t dev_id, a_uint32_t reg_addr, - a_uint32_t bit_offset, a_uint32_t field_len, - const a_uint8_t value[], a_uint32_t value_len) -{ - sw_error_t rv; - - FAL_API_LOCK; - rv = _fal_reg_field_set(dev_id, reg_addr, bit_offset, field_len, value, value_len); - FAL_API_UNLOCK; - return rv; -} - -/** - * @brief dump device register group - * @details Comments: - * The unit of packets size is byte. - * @param[in] dev_id device id - * @param[out] reg_dump dump out register group - * @return SW_OK or error code - */ -sw_error_t -fal_reg_dump(a_uint32_t dev_id, a_uint32_t reg_idx,fal_reg_dump_t *reg_dump) -{ - sw_error_t rv; - - FAL_API_LOCK; - rv = _fal_reg_dump(dev_id, reg_idx,reg_dump); - FAL_API_UNLOCK; - return rv; -} - -/** - * @brief dump device debug register - * @details Comments: - * The unit of packets size is byte. - * @param[in] dev_id device id - * @param[out] reg_dump dump out debub register - * @return SW_OK or error code - */ -sw_error_t -fal_debug_reg_dump(a_uint32_t dev_id, fal_debug_reg_dump_t *reg_dump) -{ - sw_error_t rv; - - FAL_API_LOCK; - rv = _fal_debug_reg_dump(dev_id,reg_dump); - FAL_API_UNLOCK; - return rv; -} - -/** - * @brief psgmii self test - * @details Comments: - * The unit of packets size is byte. - * @param[in] dev_id device id, enable, times - * @param[out] status - * @return SW_OK or error code - */ -sw_error_t -fal_debug_psgmii_self_test(a_uint32_t dev_id, a_bool_t enable, - a_uint32_t times, a_uint32_t *result) -{ - sw_error_t rv; - - FAL_API_LOCK; - rv = _fal_debug_psgmii_self_test(dev_id, enable, times, result); - FAL_API_UNLOCK; - return rv; -} - -/** - * @brief phy dump - * @details Comments: - * The unit of packets size is byte. - * @param[in] dev_id device id, phy addr, phy reg group - * @param[out] reg value - * @return SW_OK or error code - */ -sw_error_t -fal_phy_dump(a_uint32_t dev_id, a_uint32_t phy_addr, - a_uint32_t idx, fal_phy_dump_t * phy_dump) - -{ - sw_error_t rv; - - FAL_API_LOCK; - rv = _fal_phy_dump(dev_id, phy_addr, idx, phy_dump); - FAL_API_UNLOCK; - return rv; -} - -/** - * fal_uniphy_reg_get - get value of specific register in uniphy module - * @reg_addr: address of the register - * @uniphy_index: index of uniphy - * @value: pointer to the memory storing the value. - * @value_len: length of the value. - * - * Get the value of a specific register field with related parameter - */ -sw_error_t -fal_uniphy_reg_get(a_uint32_t dev_id, a_uint32_t index, a_uint32_t reg_addr, - a_uint8_t value[], a_uint32_t value_len) -{ - sw_error_t rv; - - FAL_API_LOCK; - rv = _fal_uniphy_reg_get(dev_id, index, reg_addr, value, value_len); - FAL_API_UNLOCK; - return rv; -} - -/** - * fal_uniphy_reg_set - set value of specific register in uniphy module - * @reg_addr: address of the register - * @uniphy_index: index of uniphy - * @value: pointer to the memory storing the value. - * @value_len: length of the value. - * - * Get the value of a specific register field with related parameter - */ -sw_error_t -fal_uniphy_reg_set(a_uint32_t dev_id, a_uint32_t index, a_uint32_t reg_addr, - a_uint8_t value[], a_uint32_t value_len) -{ - sw_error_t rv; - - FAL_API_LOCK; - rv = _fal_uniphy_reg_set(dev_id, index, reg_addr, value, value_len); - FAL_API_UNLOCK; - return rv; -} - -/** - * @} - */ diff --git a/feeds/ipq807x/qca-ssdk/src/src/fal/fal_rss_hash.c b/feeds/ipq807x/qca-ssdk/src/src/fal/fal_rss_hash.c deleted file mode 100755 index 8b2eca87a..000000000 --- a/feeds/ipq807x/qca-ssdk/src/src/fal/fal_rss_hash.c +++ /dev/null @@ -1,85 +0,0 @@ -/* - * Copyright (c) 2017, The Linux Foundation. All rights reserved. - * Permission to use, copy, modify, and/or distribute this software for - * any purpose with or without fee is hereby granted, provided that the - * above copyright notice and this permission notice appear in all copies. - * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES - * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR - * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES - * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN - * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT - * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. - */ - - -/** - * @defgroup fal_rss_hash FAL_RSS_HASH - * @{ - */ -#include "sw.h" -#include "fal_rss_hash.h" -#include "hsl_api.h" -#include "adpt.h" - -#include -#include - - -/** - * @} - */ -sw_error_t -_fal_rss_hash_config_set(a_uint32_t dev_id, fal_rss_hash_mode_t mode, fal_rss_hash_config_t * config) -{ - sw_error_t rv; - adpt_api_t *p_api; - - SW_RTN_ON_NULL(p_api = adpt_api_ptr_get(dev_id)); - - if (NULL == p_api->adpt_rss_hash_config_set) - return SW_NOT_SUPPORTED; - - rv = p_api->adpt_rss_hash_config_set(dev_id, mode, config); - return rv; -} - -sw_error_t -_fal_rss_hash_config_get(a_uint32_t dev_id, fal_rss_hash_mode_t mode, fal_rss_hash_config_t * config) -{ - sw_error_t rv; - adpt_api_t *p_api; - - SW_RTN_ON_NULL(p_api = adpt_api_ptr_get(dev_id)); - - if (NULL == p_api->adpt_rss_hash_config_get) - return SW_NOT_SUPPORTED; - - rv = p_api->adpt_rss_hash_config_get(dev_id, mode, config); - return rv; -} - -sw_error_t -fal_rss_hash_config_set(a_uint32_t dev_id, fal_rss_hash_mode_t mode, fal_rss_hash_config_t * config) -{ - sw_error_t rv = SW_OK; - - FAL_RSS_HASH_API_LOCK; - rv = _fal_rss_hash_config_set(dev_id, mode, config); - FAL_RSS_HASH_API_UNLOCK; - return rv; -} - -sw_error_t -fal_rss_hash_config_get(a_uint32_t dev_id, fal_rss_hash_mode_t mode, fal_rss_hash_config_t * config) -{ - sw_error_t rv = SW_OK; - - FAL_RSS_HASH_API_LOCK; - rv = _fal_rss_hash_config_get(dev_id, mode, config); - FAL_RSS_HASH_API_UNLOCK; - return rv; -} - -EXPORT_SYMBOL(fal_rss_hash_config_set); -EXPORT_SYMBOL(fal_rss_hash_config_get); diff --git a/feeds/ipq807x/qca-ssdk/src/src/fal/fal_sec.c b/feeds/ipq807x/qca-ssdk/src/src/fal/fal_sec.c deleted file mode 100755 index 32071e4b1..000000000 --- a/feeds/ipq807x/qca-ssdk/src/src/fal/fal_sec.c +++ /dev/null @@ -1,247 +0,0 @@ -/* - * Copyright (c) 2012, 2016-2017, The Linux Foundation. All rights reserved. - * Permission to use, copy, modify, and/or distribute this software for - * any purpose with or without fee is hereby granted, provided that the - * above copyright notice and this permission notice appear in all copies. - * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES - * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR - * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES - * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN - * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT - * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. - */ - - -/** - * @defgroup fal_sec FAL_SEC - * @{ - */ -#include "sw.h" -#include "fal_sec.h" -#include "hsl_api.h" -#include "adpt.h" - -static sw_error_t -_fal_sec_norm_item_set(a_uint32_t dev_id, fal_norm_item_t item, void *value) -{ - sw_error_t rv; - hsl_api_t *p_api; - - SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id)); - - if (NULL == p_api->sec_norm_item_set) - return SW_NOT_SUPPORTED; - - rv = p_api->sec_norm_item_set(dev_id, item, value); - return rv; -} - -static sw_error_t -_fal_sec_norm_item_get(a_uint32_t dev_id, fal_norm_item_t item, void *value) -{ - sw_error_t rv; - hsl_api_t *p_api; - - SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id)); - - if (NULL == p_api->sec_norm_item_get) - return SW_NOT_SUPPORTED; - - rv = p_api->sec_norm_item_get(dev_id, item, value); - return rv; -} - -sw_error_t -_fal_sec_l3_excep_parser_ctrl_set(a_uint32_t dev_id, fal_l3_excep_parser_ctrl *ctrl) -{ - adpt_api_t *p_api; - sw_error_t rv = SW_OK; - - SW_RTN_ON_NULL(p_api = adpt_api_ptr_get(dev_id)); - - if (NULL == p_api->adpt_sec_l3_excep_parser_ctrl_set) - return SW_NOT_SUPPORTED; - - rv = p_api->adpt_sec_l3_excep_parser_ctrl_set(dev_id, ctrl); - return rv; -} -sw_error_t -_fal_sec_l3_excep_ctrl_get(a_uint32_t dev_id, a_uint32_t excep_type, fal_l3_excep_ctrl_t *ctrl) -{ - adpt_api_t *p_api; - sw_error_t rv = SW_OK; - - SW_RTN_ON_NULL(p_api = adpt_api_ptr_get(dev_id)); - - if (NULL == p_api->adpt_sec_l3_excep_ctrl_get) - return SW_NOT_SUPPORTED; - - rv = p_api->adpt_sec_l3_excep_ctrl_get(dev_id, excep_type, ctrl); - return rv; -} -sw_error_t -_fal_sec_l3_excep_parser_ctrl_get(a_uint32_t dev_id, fal_l3_excep_parser_ctrl *ctrl) -{ - adpt_api_t *p_api; - sw_error_t rv = SW_OK; - - SW_RTN_ON_NULL(p_api = adpt_api_ptr_get(dev_id)); - - if (NULL == p_api->adpt_sec_l3_excep_parser_ctrl_get) - return SW_NOT_SUPPORTED; - - rv = p_api->adpt_sec_l3_excep_parser_ctrl_get(dev_id, ctrl); - return rv; -} -sw_error_t -_fal_sec_l4_excep_parser_ctrl_set(a_uint32_t dev_id, fal_l4_excep_parser_ctrl *ctrl) -{ - adpt_api_t *p_api; - sw_error_t rv = SW_OK; - - SW_RTN_ON_NULL(p_api = adpt_api_ptr_get(dev_id)); - - if (NULL == p_api->adpt_sec_l4_excep_parser_ctrl_set) - return SW_NOT_SUPPORTED; - - rv = p_api->adpt_sec_l4_excep_parser_ctrl_set(dev_id, ctrl); - return rv; -} -sw_error_t -_fal_sec_l3_excep_ctrl_set(a_uint32_t dev_id, a_uint32_t excep_type, fal_l3_excep_ctrl_t *ctrl) -{ - adpt_api_t *p_api; - sw_error_t rv = SW_OK; - - SW_RTN_ON_NULL(p_api = adpt_api_ptr_get(dev_id)); - - if (NULL == p_api->adpt_sec_l3_excep_ctrl_set) - return SW_NOT_SUPPORTED; - - rv = p_api->adpt_sec_l3_excep_ctrl_set(dev_id, excep_type, ctrl); - return rv; -} -sw_error_t -_fal_sec_l4_excep_parser_ctrl_get(a_uint32_t dev_id, fal_l4_excep_parser_ctrl *ctrl) -{ - adpt_api_t *p_api; - sw_error_t rv = SW_OK; - - SW_RTN_ON_NULL(p_api = adpt_api_ptr_get(dev_id)); - - if (NULL == p_api->adpt_sec_l4_excep_parser_ctrl_get) - return SW_NOT_SUPPORTED; - - rv = p_api->adpt_sec_l4_excep_parser_ctrl_get(dev_id, ctrl); - return rv; -} -/*insert flag for inner fal, don't remove it*/ - -/** - * @brief Set normalization particular item types value. - * @details Comments: - * This operation will set normalization item values on a particular device. - * The prototye of value based on the item type. - * @param[in] dev_id device id - * @param[in] item normalizaton item type - * @param[in] value normalizaton item value - * @return SW_OK or error code - */ -sw_error_t -fal_sec_norm_item_set(a_uint32_t dev_id, fal_norm_item_t item, void *value) -{ - sw_error_t rv; - - FAL_API_LOCK; - rv = _fal_sec_norm_item_set(dev_id, item, value); - FAL_API_UNLOCK; - return rv; -} - -/** - * @brief Get normalization particular item types value. - * @details Comments: - * This operation will set normalization item values on a particular device. - * The prototye of value based on the item type. - * @param[in] dev_id device id - * @param[in] item normalizaton item type - * @param[out] value normalizaton item value - * @return SW_OK or error code - */ -sw_error_t -fal_sec_norm_item_get(a_uint32_t dev_id, fal_norm_item_t item, void *value) -{ - sw_error_t rv; - - FAL_API_LOCK; - rv = _fal_sec_norm_item_get(dev_id, item, value); - FAL_API_UNLOCK; - return rv; -} - -sw_error_t -fal_sec_l3_excep_parser_ctrl_set(a_uint32_t dev_id, fal_l3_excep_parser_ctrl *ctrl) -{ - sw_error_t rv = SW_OK; - - FAL_API_LOCK; - rv = _fal_sec_l3_excep_parser_ctrl_set(dev_id, ctrl); - FAL_API_UNLOCK; - return rv; -} -sw_error_t -fal_sec_l3_excep_ctrl_get(a_uint32_t dev_id, a_uint32_t excep_type, fal_l3_excep_ctrl_t *ctrl) -{ - sw_error_t rv = SW_OK; - - FAL_API_LOCK; - rv = _fal_sec_l3_excep_ctrl_get(dev_id, excep_type, ctrl); - FAL_API_UNLOCK; - return rv; -} -sw_error_t -fal_sec_l3_excep_parser_ctrl_get(a_uint32_t dev_id, fal_l3_excep_parser_ctrl *ctrl) -{ - sw_error_t rv = SW_OK; - - FAL_API_LOCK; - rv = _fal_sec_l3_excep_parser_ctrl_get(dev_id, ctrl); - FAL_API_UNLOCK; - return rv; -} -sw_error_t -fal_sec_l4_excep_parser_ctrl_set(a_uint32_t dev_id, fal_l4_excep_parser_ctrl *ctrl) -{ - sw_error_t rv = SW_OK; - - FAL_API_LOCK; - rv = _fal_sec_l4_excep_parser_ctrl_set(dev_id, ctrl); - FAL_API_UNLOCK; - return rv; -} -sw_error_t -fal_sec_l3_excep_ctrl_set(a_uint32_t dev_id, a_uint32_t excep_type, fal_l3_excep_ctrl_t *ctrl) -{ - sw_error_t rv = SW_OK; - - FAL_API_LOCK; - rv = _fal_sec_l3_excep_ctrl_set(dev_id, excep_type, ctrl); - FAL_API_UNLOCK; - return rv; -} -sw_error_t -fal_sec_l4_excep_parser_ctrl_get(a_uint32_t dev_id, fal_l4_excep_parser_ctrl *ctrl) -{ - sw_error_t rv = SW_OK; - - FAL_API_LOCK; - rv = _fal_sec_l4_excep_parser_ctrl_get(dev_id, ctrl); - FAL_API_UNLOCK; - return rv; -} -/*insert flag for outter fal, don't remove it*/ - -/** - * @} - */ diff --git a/feeds/ipq807x/qca-ssdk/src/src/fal/fal_servcode.c b/feeds/ipq807x/qca-ssdk/src/src/fal/fal_servcode.c deleted file mode 100755 index dda3deb96..000000000 --- a/feeds/ipq807x/qca-ssdk/src/src/fal/fal_servcode.c +++ /dev/null @@ -1,143 +0,0 @@ -/* - * Copyright (c) 2016-2017, The Linux Foundation. All rights reserved. - * Permission to use, copy, modify, and/or distribute this software for - * any purpose with or without fee is hereby granted, provided that the - * above copyright notice and this permission notice appear in all copies. - * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES - * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR - * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES - * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN - * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT - * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. - */ - - -/** - * @defgroup fal_ctrlpkt FAL_SERVCODE - * @{ - */ -#include "sw.h" -#include "fal_servcode.h" -#include "hsl_api.h" -#include "adpt.h" - -#include -#include - - -/** - * @} - */ -sw_error_t -_fal_servcode_config_set(a_uint32_t dev_id, a_uint32_t servcode_index, - fal_servcode_config_t *entry) -{ - sw_error_t rv; - adpt_api_t *p_api; - - SW_RTN_ON_NULL(p_api = adpt_api_ptr_get(dev_id)); - - if (NULL == p_api->adpt_servcode_config_set) - return SW_NOT_SUPPORTED; - - rv = p_api->adpt_servcode_config_set(dev_id, servcode_index, entry); - return rv; -} - -sw_error_t -_fal_servcode_config_get(a_uint32_t dev_id, a_uint32_t servcode_index, - fal_servcode_config_t *entry) -{ - sw_error_t rv; - adpt_api_t *p_api; - - SW_RTN_ON_NULL(p_api = adpt_api_ptr_get(dev_id)); - - if (NULL == p_api->adpt_servcode_config_get) - return SW_NOT_SUPPORTED; - - rv = p_api->adpt_servcode_config_get(dev_id, servcode_index, entry); - return rv; -} - -sw_error_t -_fal_servcode_loopcheck_en(a_uint32_t dev_id, a_bool_t enable) -{ - sw_error_t rv; - adpt_api_t *p_api; - - SW_RTN_ON_NULL(p_api = adpt_api_ptr_get(dev_id)); - - if (NULL == p_api->adpt_servcode_loopcheck_en) - return SW_NOT_SUPPORTED; - - rv = p_api->adpt_servcode_loopcheck_en(dev_id, enable); - return rv; -} - -sw_error_t -_fal_servcode_loopcheck_status_get(a_uint32_t dev_id, a_bool_t *enable) -{ - sw_error_t rv; - adpt_api_t *p_api; - - SW_RTN_ON_NULL(p_api = adpt_api_ptr_get(dev_id)); - - if (NULL == p_api->adpt_servcode_loopcheck_status_get) - return SW_NOT_SUPPORTED; - - rv = p_api->adpt_servcode_loopcheck_status_get(dev_id, enable); - return rv; -} - -sw_error_t -fal_servcode_config_set(a_uint32_t dev_id, a_uint32_t servcode_index, - fal_servcode_config_t *entry) -{ - sw_error_t rv = SW_OK; - - FAL_SERVCODE_API_LOCK; - rv = _fal_servcode_config_set(dev_id, servcode_index, entry); - FAL_SERVCODE_API_UNLOCK; - return rv; -} - -sw_error_t -fal_servcode_config_get(a_uint32_t dev_id, a_uint32_t servcode_index, - fal_servcode_config_t *entry) -{ - sw_error_t rv = SW_OK; - - FAL_SERVCODE_API_LOCK; - rv = _fal_servcode_config_get(dev_id, servcode_index, entry); - FAL_SERVCODE_API_UNLOCK; - return rv; -} - -sw_error_t -fal_servcode_loopcheck_en(a_uint32_t dev_id, a_bool_t enable) -{ - sw_error_t rv = SW_OK; - - FAL_SERVCODE_API_LOCK; - rv = _fal_servcode_loopcheck_en(dev_id, enable); - FAL_SERVCODE_API_UNLOCK; - return rv; -} - -sw_error_t -fal_servcode_loopcheck_status_get(a_uint32_t dev_id, a_bool_t *enable) -{ - sw_error_t rv = SW_OK; - - FAL_SERVCODE_API_LOCK; - rv = _fal_servcode_loopcheck_status_get(dev_id, enable); - FAL_SERVCODE_API_UNLOCK; - return rv; -} - -EXPORT_SYMBOL(fal_servcode_config_set); -EXPORT_SYMBOL(fal_servcode_config_get); -EXPORT_SYMBOL(fal_servcode_loopcheck_en); -EXPORT_SYMBOL(fal_servcode_loopcheck_status_get); diff --git a/feeds/ipq807x/qca-ssdk/src/src/fal/fal_sfp.c b/feeds/ipq807x/qca-ssdk/src/src/fal/fal_sfp.c deleted file mode 100755 index c3fe063ab..000000000 --- a/feeds/ipq807x/qca-ssdk/src/src/fal/fal_sfp.c +++ /dev/null @@ -1,508 +0,0 @@ -/* - * Copyright (c) 2019, The Linux Foundation. All rights reserved. - * Permission to use, copy, modify, and/or distribute this software for - * any purpose with or without fee is hereby granted, provided that the - * above copyright notice and this permission notice appear in all copies. - * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES - * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR - * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES - * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN - * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT - * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. - */ - -#include "sw.h" -#include "fal_sfp.h" -#include "adpt.h" -#include "hsl_api.h" - -sw_error_t -_fal_sfp_diag_ctrl_status_get(a_uint32_t dev_id, a_uint32_t port_id, - fal_sfp_ctrl_status_t *ctrl_status) -{ - adpt_api_t *p_api; - sw_error_t rv = SW_OK; - - SW_RTN_ON_NULL(p_api = adpt_api_ptr_get(dev_id)); - - if (NULL == p_api->adpt_sfp_diag_ctrl_status_get) - return SW_NOT_SUPPORTED; - - rv = p_api->adpt_sfp_diag_ctrl_status_get(dev_id, port_id, ctrl_status); - return rv; -} - -sw_error_t -_fal_sfp_diag_extenal_calibration_const_get(a_uint32_t dev_id, a_uint32_t port_id, - fal_sfp_cal_const_t *cal_const) -{ - adpt_api_t *p_api; - sw_error_t rv = SW_OK; - - SW_RTN_ON_NULL(p_api = adpt_api_ptr_get(dev_id)); - - if (NULL == p_api->adpt_sfp_diag_extenal_calibration_const_get) - return SW_NOT_SUPPORTED; - - rv = p_api->adpt_sfp_diag_extenal_calibration_const_get(dev_id, port_id, cal_const); - return rv; -} - -sw_error_t -_fal_sfp_link_length_get(a_uint32_t dev_id, a_uint32_t port_id, - fal_sfp_link_length_t *link_len) -{ - adpt_api_t *p_api; - sw_error_t rv = SW_OK; - - SW_RTN_ON_NULL(p_api = adpt_api_ptr_get(dev_id)); - - if (NULL == p_api->adpt_sfp_link_length_get) - return SW_NOT_SUPPORTED; - - rv = p_api->adpt_sfp_link_length_get(dev_id, port_id, link_len); - return rv; -} - -sw_error_t -_fal_sfp_diag_internal_threshold_get(a_uint32_t dev_id, a_uint32_t port_id, - fal_sfp_internal_threshold_t *threshold) -{ - adpt_api_t *p_api; - sw_error_t rv = SW_OK; - - SW_RTN_ON_NULL(p_api = adpt_api_ptr_get(dev_id)); - - if (NULL == p_api->adpt_sfp_diag_internal_threshold_get) - return SW_NOT_SUPPORTED; - - rv = p_api->adpt_sfp_diag_internal_threshold_get(dev_id, port_id, threshold); - return rv; -} - -sw_error_t -_fal_sfp_diag_realtime_get(a_uint32_t dev_id, a_uint32_t port_id, - fal_sfp_realtime_diag_t *real_diag) -{ - adpt_api_t *p_api; - sw_error_t rv = SW_OK; - - SW_RTN_ON_NULL(p_api = adpt_api_ptr_get(dev_id)); - - if (NULL == p_api->adpt_sfp_diag_realtime_get) - return SW_NOT_SUPPORTED; - - rv = p_api->adpt_sfp_diag_realtime_get(dev_id, port_id, real_diag); - return rv; -} - -sw_error_t -_fal_sfp_laser_wavelength_get(a_uint32_t dev_id, a_uint32_t port_id, - fal_sfp_laser_wavelength_t *laser_wavelen) -{ - adpt_api_t *p_api; - sw_error_t rv = SW_OK; - - SW_RTN_ON_NULL(p_api = adpt_api_ptr_get(dev_id)); - - if (NULL == p_api->adpt_sfp_laser_wavelength_get) - return SW_NOT_SUPPORTED; - - rv = p_api->adpt_sfp_laser_wavelength_get(dev_id, port_id, laser_wavelen); - return rv; -} - -sw_error_t -_fal_sfp_option_get(a_uint32_t dev_id, a_uint32_t port_id, - fal_sfp_option_t *option) -{ - adpt_api_t *p_api; - sw_error_t rv = SW_OK; - - SW_RTN_ON_NULL(p_api = adpt_api_ptr_get(dev_id)); - - if (NULL == p_api->adpt_sfp_option_get) - return SW_NOT_SUPPORTED; - - rv = p_api->adpt_sfp_option_get(dev_id, port_id, option); - return rv; -} - -sw_error_t -_fal_sfp_checkcode_get(a_uint32_t dev_id, a_uint32_t port_id, - fal_sfp_cc_type_t cc_type, a_uint8_t *ccode) -{ - adpt_api_t *p_api; - sw_error_t rv = SW_OK; - - SW_RTN_ON_NULL(p_api = adpt_api_ptr_get(dev_id)); - - if (NULL == p_api->adpt_sfp_checkcode_get) - return SW_NOT_SUPPORTED; - - rv = p_api->adpt_sfp_checkcode_get(dev_id, port_id, cc_type, ccode); - return rv; -} - -sw_error_t -_fal_sfp_diag_alarm_warning_flag_get(a_uint32_t dev_id, a_uint32_t port_id, - fal_sfp_alarm_warn_flag_t *alarm_warn_flag) -{ - adpt_api_t *p_api; - sw_error_t rv = SW_OK; - - SW_RTN_ON_NULL(p_api = adpt_api_ptr_get(dev_id)); - - if (NULL == p_api->adpt_sfp_diag_alarm_warning_flag_get) - return SW_NOT_SUPPORTED; - - rv = p_api->adpt_sfp_diag_alarm_warning_flag_get(dev_id, port_id, alarm_warn_flag); - return rv; -} - -sw_error_t -_fal_sfp_device_type_get(a_uint32_t dev_id, a_uint32_t port_id, - fal_sfp_dev_type_t *sfp_id) -{ - adpt_api_t *p_api; - sw_error_t rv = SW_OK; - - SW_RTN_ON_NULL(p_api = adpt_api_ptr_get(dev_id)); - - if (NULL == p_api->adpt_sfp_device_type_get) - return SW_NOT_SUPPORTED; - - rv = p_api->adpt_sfp_device_type_get(dev_id, port_id, sfp_id); - return rv; -} - -sw_error_t -_fal_sfp_vendor_info_get(a_uint32_t dev_id, a_uint32_t port_id, - fal_sfp_vendor_info_t *vender_info) -{ - adpt_api_t *p_api; - sw_error_t rv = SW_OK; - - SW_RTN_ON_NULL(p_api = adpt_api_ptr_get(dev_id)); - - if (NULL == p_api->adpt_sfp_vendor_info_get) - return SW_NOT_SUPPORTED; - - rv = p_api->adpt_sfp_vendor_info_get(dev_id, port_id, vender_info); - return rv; -} - -sw_error_t -_fal_sfp_transceiver_code_get(a_uint32_t dev_id, a_uint32_t port_id, - fal_sfp_transc_code_t *transc_code) -{ - adpt_api_t *p_api; - sw_error_t rv = SW_OK; - - SW_RTN_ON_NULL(p_api = adpt_api_ptr_get(dev_id)); - - if (NULL == p_api->adpt_sfp_transceiver_code_get) - return SW_NOT_SUPPORTED; - - rv = p_api->adpt_sfp_transceiver_code_get(dev_id, port_id, transc_code); - return rv; -} - -sw_error_t -_fal_sfp_ctrl_rate_get(a_uint32_t dev_id, a_uint32_t port_id, - fal_sfp_rate_t *rate_limit) -{ - adpt_api_t *p_api; - sw_error_t rv = SW_OK; - - SW_RTN_ON_NULL(p_api = adpt_api_ptr_get(dev_id)); - - if (NULL == p_api->adpt_sfp_ctrl_rate_get) - return SW_NOT_SUPPORTED; - - rv = p_api->adpt_sfp_ctrl_rate_get(dev_id, port_id, rate_limit); - return rv; -} - -sw_error_t -_fal_sfp_enhanced_cfg_get(a_uint32_t dev_id, a_uint32_t port_id, - fal_sfp_enhanced_cfg_t *enhanced_feature) -{ - adpt_api_t *p_api; - sw_error_t rv = SW_OK; - - SW_RTN_ON_NULL(p_api = adpt_api_ptr_get(dev_id)); - - if (NULL == p_api->adpt_sfp_enhanced_cfg_get) - return SW_NOT_SUPPORTED; - - rv = p_api->adpt_sfp_enhanced_cfg_get(dev_id, port_id, enhanced_feature); - return rv; -} - -sw_error_t -_fal_sfp_rate_encode_get(a_uint32_t dev_id, a_uint32_t port_id, - fal_sfp_rate_encode_t *encode) -{ - adpt_api_t *p_api; - sw_error_t rv = SW_OK; - - SW_RTN_ON_NULL(p_api = adpt_api_ptr_get(dev_id)); - - if (NULL == p_api->adpt_sfp_rate_encode_get) - return SW_NOT_SUPPORTED; - - rv = p_api->adpt_sfp_rate_encode_get(dev_id, port_id, encode); - return rv; -} - -sw_error_t -_fal_sfp_eeprom_data_get(a_uint32_t dev_id, a_uint32_t port_id, fal_sfp_data_t *entry) -{ - adpt_api_t *p_api; - sw_error_t rv = SW_OK; - - SW_RTN_ON_NULL(p_api = adpt_api_ptr_get(dev_id)); - - if (NULL == p_api->adpt_sfp_eeprom_data_get) - return SW_NOT_SUPPORTED; - - rv = p_api->adpt_sfp_eeprom_data_get(dev_id, port_id, entry); - return rv; -} - -sw_error_t -_fal_sfp_eeprom_data_set(a_uint32_t dev_id, a_uint32_t port_id, fal_sfp_data_t *entry) -{ - adpt_api_t *p_api; - sw_error_t rv = SW_OK; - - SW_RTN_ON_NULL(p_api = adpt_api_ptr_get(dev_id)); - - if (NULL == p_api->adpt_sfp_eeprom_data_set) - return SW_NOT_SUPPORTED; - - rv = p_api->adpt_sfp_eeprom_data_set(dev_id, port_id, entry); - return rv; -} - -sw_error_t -fal_sfp_diag_ctrl_status_get(a_uint32_t dev_id, a_uint32_t port_id, - fal_sfp_ctrl_status_t *ctrl_status) -{ - sw_error_t rv = SW_OK; - - FAL_API_LOCK; - rv = _fal_sfp_diag_ctrl_status_get(dev_id, port_id, ctrl_status); - FAL_API_UNLOCK; - return rv; -} - -sw_error_t -fal_sfp_diag_extenal_calibration_const_get(a_uint32_t dev_id, a_uint32_t port_id, - fal_sfp_cal_const_t *cal_const) -{ - sw_error_t rv = SW_OK; - - FAL_API_LOCK; - rv = _fal_sfp_diag_extenal_calibration_const_get(dev_id, port_id, cal_const); - FAL_API_UNLOCK; - return rv; -} - -sw_error_t -fal_sfp_link_length_get(a_uint32_t dev_id, a_uint32_t port_id, - fal_sfp_link_length_t *link_len) -{ - sw_error_t rv = SW_OK; - - FAL_API_LOCK; - rv = _fal_sfp_link_length_get(dev_id, port_id, link_len); - FAL_API_UNLOCK; - return rv; -} - -sw_error_t -fal_sfp_diag_internal_threshold_get(a_uint32_t dev_id, a_uint32_t port_id, - fal_sfp_internal_threshold_t *threshold) -{ - sw_error_t rv = SW_OK; - - FAL_API_LOCK; - rv = _fal_sfp_diag_internal_threshold_get(dev_id, port_id, threshold); - FAL_API_UNLOCK; - return rv; -} - -sw_error_t -fal_sfp_diag_realtime_get(a_uint32_t dev_id, a_uint32_t port_id, - fal_sfp_realtime_diag_t *real_diag) -{ - sw_error_t rv = SW_OK; - - FAL_API_LOCK; - rv = _fal_sfp_diag_realtime_get(dev_id, port_id, real_diag); - FAL_API_UNLOCK; - return rv; -} - -sw_error_t -fal_sfp_laser_wavelength_get(a_uint32_t dev_id, a_uint32_t port_id, - fal_sfp_laser_wavelength_t *laser_wavelen) -{ - sw_error_t rv = SW_OK; - - FAL_API_LOCK; - rv = _fal_sfp_laser_wavelength_get(dev_id, port_id, laser_wavelen); - FAL_API_UNLOCK; - return rv; -} - -sw_error_t -fal_sfp_option_get(a_uint32_t dev_id, a_uint32_t port_id, - fal_sfp_option_t *option) -{ - sw_error_t rv = SW_OK; - - FAL_API_LOCK; - rv = _fal_sfp_option_get(dev_id, port_id, option); - FAL_API_UNLOCK; - return rv; -} - -sw_error_t -fal_sfp_checkcode_get(a_uint32_t dev_id, a_uint32_t port_id, - fal_sfp_cc_type_t cc_type, a_uint8_t *ccode) -{ - sw_error_t rv = SW_OK; - - FAL_API_LOCK; - rv = _fal_sfp_checkcode_get(dev_id, port_id, cc_type, ccode); - FAL_API_UNLOCK; - return rv; -} - -sw_error_t -fal_sfp_diag_alarm_warning_flag_get(a_uint32_t dev_id, a_uint32_t port_id, - fal_sfp_alarm_warn_flag_t *alarm_warn_flag) -{ - sw_error_t rv = SW_OK; - - FAL_API_LOCK; - rv = _fal_sfp_diag_alarm_warning_flag_get(dev_id, port_id, alarm_warn_flag); - FAL_API_UNLOCK; - return rv; -} - -sw_error_t -fal_sfp_device_type_get(a_uint32_t dev_id, a_uint32_t port_id, - fal_sfp_dev_type_t *sfp_id) -{ - sw_error_t rv = SW_OK; - - FAL_API_LOCK; - rv = _fal_sfp_device_type_get(dev_id, port_id, sfp_id); - FAL_API_UNLOCK; - return rv; -} - -sw_error_t -fal_sfp_vendor_info_get(a_uint32_t dev_id, a_uint32_t port_id, - fal_sfp_vendor_info_t *vender_info) -{ - sw_error_t rv = SW_OK; - - FAL_API_LOCK; - rv = _fal_sfp_vendor_info_get(dev_id, port_id, vender_info); - FAL_API_UNLOCK; - return rv; -} - -sw_error_t -fal_sfp_transceiver_code_get(a_uint32_t dev_id, a_uint32_t port_id, - fal_sfp_transc_code_t *transc_code) -{ - sw_error_t rv = SW_OK; - - FAL_API_LOCK; - rv = _fal_sfp_transceiver_code_get(dev_id, port_id, transc_code); - FAL_API_UNLOCK; - return rv; -} - -sw_error_t -fal_sfp_ctrl_rate_get(a_uint32_t dev_id, a_uint32_t port_id, - fal_sfp_rate_t *rate_limit) -{ - sw_error_t rv = SW_OK; - - FAL_API_LOCK; - rv = _fal_sfp_ctrl_rate_get(dev_id, port_id, rate_limit); - FAL_API_UNLOCK; - return rv; -} - -sw_error_t -fal_sfp_enhanced_cfg_get(a_uint32_t dev_id, a_uint32_t port_id, - fal_sfp_enhanced_cfg_t *enhanced_feature) -{ - sw_error_t rv = SW_OK; - - FAL_API_LOCK; - rv = _fal_sfp_enhanced_cfg_get(dev_id, port_id, enhanced_feature); - FAL_API_UNLOCK; - return rv; -} - -sw_error_t -fal_sfp_rate_encode_get(a_uint32_t dev_id, a_uint32_t port_id, - fal_sfp_rate_encode_t *encode) -{ - sw_error_t rv = SW_OK; - - FAL_API_LOCK; - rv = _fal_sfp_rate_encode_get(dev_id, port_id, encode); - FAL_API_UNLOCK; - return rv; -} - -sw_error_t -fal_sfp_eeprom_data_get(a_uint32_t dev_id, a_uint32_t port_id, fal_sfp_data_t *entry) -{ - sw_error_t rv = SW_OK; - - FAL_API_LOCK; - rv = _fal_sfp_eeprom_data_get(dev_id, port_id, entry); - FAL_API_UNLOCK; - return rv; -} - -sw_error_t -fal_sfp_eeprom_data_set(a_uint32_t dev_id, a_uint32_t port_id, fal_sfp_data_t *entry) -{ - sw_error_t rv = SW_OK; - - FAL_API_LOCK; - rv = _fal_sfp_eeprom_data_set(dev_id, port_id, entry); - FAL_API_UNLOCK; - return rv; -} - -EXPORT_SYMBOL(fal_sfp_diag_ctrl_status_get); -EXPORT_SYMBOL(fal_sfp_diag_extenal_calibration_const_get); -EXPORT_SYMBOL(fal_sfp_link_length_get); -EXPORT_SYMBOL(fal_sfp_diag_internal_threshold_get); -EXPORT_SYMBOL(fal_sfp_diag_realtime_get); -EXPORT_SYMBOL(fal_sfp_laser_wavelength_get); -EXPORT_SYMBOL(fal_sfp_option_get); -EXPORT_SYMBOL(fal_sfp_checkcode_get); -EXPORT_SYMBOL(fal_sfp_diag_alarm_warning_flag_get); -EXPORT_SYMBOL(fal_sfp_device_type_get); -EXPORT_SYMBOL(fal_sfp_vendor_info_get); -EXPORT_SYMBOL(fal_sfp_transceiver_code_get); -EXPORT_SYMBOL(fal_sfp_ctrl_rate_get); -EXPORT_SYMBOL(fal_sfp_enhanced_cfg_get); -EXPORT_SYMBOL(fal_sfp_rate_encode_get); -EXPORT_SYMBOL(fal_sfp_eeprom_data_get); -EXPORT_SYMBOL(fal_sfp_eeprom_data_set); diff --git a/feeds/ipq807x/qca-ssdk/src/src/fal/fal_shaper.c b/feeds/ipq807x/qca-ssdk/src/src/fal/fal_shaper.c deleted file mode 100755 index addb0f3c7..000000000 --- a/feeds/ipq807x/qca-ssdk/src/src/fal/fal_shaper.c +++ /dev/null @@ -1,601 +0,0 @@ -/* - * Copyright (c) 2016-2017, The Linux Foundation. All rights reserved. - * Permission to use, copy, modify, and/or distribute this software for - * any purpose with or without fee is hereby granted, provided that the - * above copyright notice and this permission notice appear in all copies. - * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES - * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR - * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES - * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN - * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT - * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. - */ - - -/** - * @defgroup fal_shaper FAL_SHAPER - * @{ - */ -#include "sw.h" -#include "fal_shaper.h" -#include "hsl_api.h" -#include "adpt.h" - -#include -#include - -sw_error_t -_fal_flow_shaper_set(a_uint32_t dev_id, a_uint32_t flow_id, - fal_shaper_config_t * shaper) -{ - adpt_api_t *p_api; - sw_error_t rv = SW_OK; - - SW_RTN_ON_NULL(p_api = adpt_api_ptr_get(dev_id)); - - if (NULL == p_api->adpt_flow_shaper_set) - return SW_NOT_SUPPORTED; - - rv = p_api->adpt_flow_shaper_set(dev_id, flow_id, shaper); - return rv; -} -sw_error_t -_fal_queue_shaper_get(a_uint32_t dev_id, a_uint32_t queue_id, - fal_shaper_config_t * shaper) -{ - adpt_api_t *p_api; - sw_error_t rv = SW_OK; - - SW_RTN_ON_NULL(p_api = adpt_api_ptr_get(dev_id)); - - if (NULL == p_api->adpt_queue_shaper_get) - return SW_NOT_SUPPORTED; - - rv = p_api->adpt_queue_shaper_get(dev_id, queue_id, shaper); - return rv; -} -sw_error_t -_fal_queue_shaper_token_number_set(a_uint32_t dev_id,a_uint32_t queue_id, - fal_shaper_token_number_t *token_number) -{ - adpt_api_t *p_api; - sw_error_t rv = SW_OK; - - SW_RTN_ON_NULL(p_api = adpt_api_ptr_get(dev_id)); - - if (NULL == p_api->adpt_queue_shaper_token_number_set) - return SW_NOT_SUPPORTED; - - rv = p_api->adpt_queue_shaper_token_number_set(dev_id, queue_id, token_number); - return rv; -} -#ifndef IN_SHAPER_MINI -sw_error_t -_fal_port_shaper_get(a_uint32_t dev_id, fal_port_t port_id, - fal_shaper_config_t * shaper) -{ - adpt_api_t *p_api; - sw_error_t rv = SW_OK; - - SW_RTN_ON_NULL(p_api = adpt_api_ptr_get(dev_id)); - - if (NULL == p_api->adpt_port_shaper_get) - return SW_NOT_SUPPORTED; - - rv = p_api->adpt_port_shaper_get(dev_id, port_id, shaper); - return rv; -} -sw_error_t -_fal_flow_shaper_timeslot_get(a_uint32_t dev_id, a_uint32_t *timeslot) -{ - adpt_api_t *p_api; - sw_error_t rv = SW_OK; - - SW_RTN_ON_NULL(p_api = adpt_api_ptr_get(dev_id)); - - if (NULL == p_api->adpt_flow_shaper_time_slot_get) - return SW_NOT_SUPPORTED; - - rv = p_api->adpt_flow_shaper_time_slot_get(dev_id, timeslot); - return rv; -} -sw_error_t -_fal_port_shaper_timeslot_get(a_uint32_t dev_id, a_uint32_t *timeslot) -{ - adpt_api_t *p_api; - sw_error_t rv = SW_OK; - - SW_RTN_ON_NULL(p_api = adpt_api_ptr_get(dev_id)); - - if (NULL == p_api->adpt_port_shaper_time_slot_get) - return SW_NOT_SUPPORTED; - - rv = p_api->adpt_port_shaper_time_slot_get(dev_id, timeslot); - return rv; -} -#endif -sw_error_t -_fal_flow_shaper_timeslot_set(a_uint32_t dev_id, a_uint32_t timeslot) -{ - adpt_api_t *p_api; - sw_error_t rv = SW_OK; - - SW_RTN_ON_NULL(p_api = adpt_api_ptr_get(dev_id)); - - if (NULL == p_api->adpt_flow_shaper_time_slot_set) - return SW_NOT_SUPPORTED; - - rv = p_api->adpt_flow_shaper_time_slot_set(dev_id, timeslot); - return rv; -} -sw_error_t -_fal_port_shaper_token_number_set(a_uint32_t dev_id, fal_port_t port_id, - fal_shaper_token_number_t *token_number) -{ - adpt_api_t *p_api; - sw_error_t rv = SW_OK; - - SW_RTN_ON_NULL(p_api = adpt_api_ptr_get(dev_id)); - - if (NULL == p_api->adpt_port_shaper_token_number_set) - return SW_NOT_SUPPORTED; - - rv = p_api->adpt_port_shaper_token_number_set(dev_id, port_id, token_number); - return rv; -} -#ifndef IN_SHAPER_MINI -sw_error_t -_fal_queue_shaper_token_number_get(a_uint32_t dev_id, a_uint32_t queue_id, - fal_shaper_token_number_t *token_number) -{ - adpt_api_t *p_api; - sw_error_t rv = SW_OK; - - SW_RTN_ON_NULL(p_api = adpt_api_ptr_get(dev_id)); - - if (NULL == p_api->adpt_queue_shaper_token_number_get) - return SW_NOT_SUPPORTED; - - rv = p_api->adpt_queue_shaper_token_number_get(dev_id, queue_id, token_number); - return rv; -} -sw_error_t -_fal_queue_shaper_timeslot_get(a_uint32_t dev_id, a_uint32_t *timeslot) -{ - adpt_api_t *p_api; - sw_error_t rv = SW_OK; - - SW_RTN_ON_NULL(p_api = adpt_api_ptr_get(dev_id)); - - if (NULL == p_api->adpt_queue_shaper_time_slot_get) - return SW_NOT_SUPPORTED; - - rv = p_api->adpt_queue_shaper_time_slot_get(dev_id, timeslot); - return rv; -} -sw_error_t -_fal_port_shaper_token_number_get(a_uint32_t dev_id, fal_port_t port_id, - fal_shaper_token_number_t *token_number) -{ - adpt_api_t *p_api; - sw_error_t rv = SW_OK; - - SW_RTN_ON_NULL(p_api = adpt_api_ptr_get(dev_id)); - - if (NULL == p_api->adpt_port_shaper_token_number_get) - return SW_NOT_SUPPORTED; - - rv = p_api->adpt_port_shaper_token_number_get(dev_id, port_id, token_number); - return rv; -} -#endif -sw_error_t -_fal_flow_shaper_token_number_set(a_uint32_t dev_id, a_uint32_t flow_id, - fal_shaper_token_number_t *token_number) -{ - adpt_api_t *p_api; - sw_error_t rv = SW_OK; - - SW_RTN_ON_NULL(p_api = adpt_api_ptr_get(dev_id)); - - if (NULL == p_api->adpt_flow_shaper_token_number_set) - return SW_NOT_SUPPORTED; - - rv = p_api->adpt_flow_shaper_token_number_set(dev_id, flow_id, token_number); - return rv; -} -#ifndef IN_SHAPER_MINI -sw_error_t -_fal_flow_shaper_token_number_get(a_uint32_t dev_id, a_uint32_t flow_id, - fal_shaper_token_number_t *token_number) -{ - adpt_api_t *p_api; - sw_error_t rv = SW_OK; - - SW_RTN_ON_NULL(p_api = adpt_api_ptr_get(dev_id)); - - if (NULL == p_api->adpt_flow_shaper_token_number_get) - return SW_NOT_SUPPORTED; - - rv = p_api->adpt_flow_shaper_token_number_get(dev_id, flow_id, token_number); - return rv; -} -#endif -sw_error_t -_fal_port_shaper_set(a_uint32_t dev_id, fal_port_t port_id, - fal_shaper_config_t * shaper) -{ - adpt_api_t *p_api; - sw_error_t rv = SW_OK; - - SW_RTN_ON_NULL(p_api = adpt_api_ptr_get(dev_id)); - - if (NULL == p_api->adpt_port_shaper_set) - return SW_NOT_SUPPORTED; - - rv = p_api->adpt_port_shaper_set(dev_id, port_id, shaper); - return rv; -} -sw_error_t -_fal_port_shaper_timeslot_set(a_uint32_t dev_id, a_uint32_t timeslot) -{ - adpt_api_t *p_api; - sw_error_t rv = SW_OK; - - SW_RTN_ON_NULL(p_api = adpt_api_ptr_get(dev_id)); - - if (NULL == p_api->adpt_port_shaper_time_slot_set) - return SW_NOT_SUPPORTED; - - rv = p_api->adpt_port_shaper_time_slot_set(dev_id, timeslot); - return rv; -} -#ifndef IN_SHAPER_MINI -sw_error_t -_fal_flow_shaper_get(a_uint32_t dev_id, a_uint32_t flow_id, - fal_shaper_config_t * shaper) -{ - adpt_api_t *p_api; - sw_error_t rv = SW_OK; - - SW_RTN_ON_NULL(p_api = adpt_api_ptr_get(dev_id)); - - if (NULL == p_api->adpt_flow_shaper_get) - return SW_NOT_SUPPORTED; - - rv = p_api->adpt_flow_shaper_get(dev_id, flow_id, shaper); - return rv; -} -#endif -sw_error_t -_fal_queue_shaper_set(a_uint32_t dev_id,a_uint32_t queue_id, - fal_shaper_config_t * shaper) -{ - adpt_api_t *p_api; - sw_error_t rv = SW_OK; - - SW_RTN_ON_NULL(p_api = adpt_api_ptr_get(dev_id)); - - if (NULL == p_api->adpt_queue_shaper_set) - return SW_NOT_SUPPORTED; - - rv = p_api->adpt_queue_shaper_set(dev_id, queue_id, shaper); - return rv; -} -sw_error_t -_fal_queue_shaper_timeslot_set(a_uint32_t dev_id, a_uint32_t timeslot) -{ - adpt_api_t *p_api; - sw_error_t rv = SW_OK; - - SW_RTN_ON_NULL(p_api = adpt_api_ptr_get(dev_id)); - - if (NULL == p_api->adpt_queue_shaper_time_slot_set) - return SW_NOT_SUPPORTED; - - rv = p_api->adpt_queue_shaper_time_slot_set(dev_id, timeslot); - return rv; -} - -sw_error_t -_fal_shaper_ipg_preamble_length_set(a_uint32_t dev_id, a_uint32_t ipg_pre_length) -{ - adpt_api_t *p_api; - sw_error_t rv = SW_OK; - - SW_RTN_ON_NULL(p_api = adpt_api_ptr_get(dev_id)); - - if (NULL == p_api->adpt_shaper_ipg_preamble_length_set) - return SW_NOT_SUPPORTED; - - rv = p_api->adpt_shaper_ipg_preamble_length_set(dev_id, ipg_pre_length); - return rv; -} - -#ifndef IN_SHAPER_MINI -sw_error_t -_fal_shaper_ipg_preamble_length_get(a_uint32_t dev_id, a_uint32_t *ipg_pre_length) -{ - adpt_api_t *p_api; - sw_error_t rv = SW_OK; - - SW_RTN_ON_NULL(p_api = adpt_api_ptr_get(dev_id)); - - if (NULL == p_api->adpt_shaper_ipg_preamble_length_get) - return SW_NOT_SUPPORTED; - - rv = p_api->adpt_shaper_ipg_preamble_length_get(dev_id, ipg_pre_length); - return rv; -} -#endif - -/*insert flag for inner fal, don't remove it*/ - -sw_error_t -fal_flow_shaper_set(a_uint32_t dev_id, a_uint32_t flow_id, - fal_shaper_config_t * shaper) -{ - sw_error_t rv = SW_OK; - - FAL_API_LOCK; - rv = _fal_flow_shaper_set(dev_id, flow_id, shaper); - FAL_API_UNLOCK; - return rv; -} -sw_error_t -fal_queue_shaper_get(a_uint32_t dev_id, a_uint32_t queue_id, - fal_shaper_config_t * shaper) -{ - sw_error_t rv = SW_OK; - - FAL_API_LOCK; - rv = _fal_queue_shaper_get(dev_id, queue_id, shaper); - FAL_API_UNLOCK; - return rv; -} -sw_error_t -fal_queue_shaper_token_number_set(a_uint32_t dev_id,a_uint32_t queue_id, - fal_shaper_token_number_t *token_number) -{ - sw_error_t rv = SW_OK; - - FAL_API_LOCK; - rv = _fal_queue_shaper_token_number_set(dev_id, queue_id, token_number); - FAL_API_UNLOCK; - return rv; -} -#ifndef IN_SHAPER_MINI -sw_error_t -fal_port_shaper_get(a_uint32_t dev_id, fal_port_t port_id, - fal_shaper_config_t * shaper) -{ - sw_error_t rv = SW_OK; - - FAL_API_LOCK; - rv = _fal_port_shaper_get(dev_id, port_id, shaper); - FAL_API_UNLOCK; - return rv; -} -sw_error_t -fal_flow_shaper_timeslot_get(a_uint32_t dev_id, a_uint32_t *timeslot) -{ - sw_error_t rv = SW_OK; - - FAL_API_LOCK; - rv = _fal_flow_shaper_timeslot_get(dev_id, timeslot); - FAL_API_UNLOCK; - return rv; -} -sw_error_t -fal_port_shaper_timeslot_get(a_uint32_t dev_id, a_uint32_t *timeslot) -{ - sw_error_t rv = SW_OK; - - FAL_API_LOCK; - rv = _fal_port_shaper_timeslot_get(dev_id, timeslot); - FAL_API_UNLOCK; - return rv; -} -#endif -sw_error_t -fal_flow_shaper_timeslot_set(a_uint32_t dev_id, a_uint32_t timeslot) -{ - sw_error_t rv = SW_OK; - - FAL_API_LOCK; - rv = _fal_flow_shaper_timeslot_set(dev_id, timeslot); - FAL_API_UNLOCK; - return rv; -} -sw_error_t -fal_port_shaper_token_number_set(a_uint32_t dev_id, fal_port_t port_id, - fal_shaper_token_number_t *token_number) -{ - sw_error_t rv = SW_OK; - - FAL_API_LOCK; - rv = _fal_port_shaper_token_number_set(dev_id, port_id, token_number); - FAL_API_UNLOCK; - return rv; -} -#ifndef IN_SHAPER_MINI -sw_error_t -fal_queue_shaper_token_number_get(a_uint32_t dev_id, a_uint32_t queue_id, - fal_shaper_token_number_t *token_number) -{ - sw_error_t rv = SW_OK; - - FAL_API_LOCK; - rv = _fal_queue_shaper_token_number_get(dev_id, queue_id, token_number); - FAL_API_UNLOCK; - return rv; -} -sw_error_t -fal_queue_shaper_timeslot_get(a_uint32_t dev_id, a_uint32_t *timeslot) -{ - sw_error_t rv = SW_OK; - - FAL_API_LOCK; - rv = _fal_queue_shaper_timeslot_get(dev_id, timeslot); - FAL_API_UNLOCK; - return rv; -} -sw_error_t -fal_port_shaper_token_number_get(a_uint32_t dev_id, fal_port_t port_id, - fal_shaper_token_number_t *token_number) -{ - sw_error_t rv = SW_OK; - - FAL_API_LOCK; - rv = _fal_port_shaper_token_number_get(dev_id, port_id, token_number); - FAL_API_UNLOCK; - return rv; -} -#endif -sw_error_t -fal_flow_shaper_token_number_set(a_uint32_t dev_id, a_uint32_t flow_id, - fal_shaper_token_number_t *token_number) -{ - sw_error_t rv = SW_OK; - - FAL_API_LOCK; - rv = _fal_flow_shaper_token_number_set(dev_id, flow_id, token_number); - FAL_API_UNLOCK; - return rv; -} -#ifndef IN_SHAPER_MINI -sw_error_t -fal_flow_shaper_token_number_get(a_uint32_t dev_id, a_uint32_t flow_id, - fal_shaper_token_number_t *token_number) -{ - sw_error_t rv = SW_OK; - - FAL_API_LOCK; - rv = _fal_flow_shaper_token_number_get(dev_id, flow_id, token_number); - FAL_API_UNLOCK; - return rv; -} -#endif -sw_error_t -fal_port_shaper_set(a_uint32_t dev_id, fal_port_t port_id, - fal_shaper_config_t * shaper) -{ - sw_error_t rv = SW_OK; - - FAL_API_LOCK; - rv = _fal_port_shaper_set(dev_id, port_id, shaper); - FAL_API_UNLOCK; - return rv; -} -sw_error_t -fal_port_shaper_timeslot_set(a_uint32_t dev_id, a_uint32_t timeslot) -{ - sw_error_t rv = SW_OK; - - FAL_API_LOCK; - rv = _fal_port_shaper_timeslot_set(dev_id, timeslot); - FAL_API_UNLOCK; - return rv; -} -#ifndef IN_SHAPER_MINI -sw_error_t -fal_flow_shaper_get(a_uint32_t dev_id, a_uint32_t flow_id, - fal_shaper_config_t * shaper) -{ - sw_error_t rv = SW_OK; - - FAL_API_LOCK; - rv = _fal_flow_shaper_get(dev_id, flow_id, shaper); - FAL_API_UNLOCK; - return rv; -} -#endif -sw_error_t -fal_queue_shaper_set(a_uint32_t dev_id,a_uint32_t queue_id, - fal_shaper_config_t * shaper) -{ - sw_error_t rv = SW_OK; - - FAL_API_LOCK; - rv = _fal_queue_shaper_set(dev_id, queue_id, shaper); - FAL_API_UNLOCK; - return rv; -} -sw_error_t -fal_queue_shaper_timeslot_set(a_uint32_t dev_id, a_uint32_t timeslot) -{ - sw_error_t rv = SW_OK; - - FAL_API_LOCK; - rv = _fal_queue_shaper_timeslot_set(dev_id, timeslot); - FAL_API_UNLOCK; - return rv; -} -sw_error_t -fal_shaper_ipg_preamble_length_set(a_uint32_t dev_id, a_uint32_t ipg_pre_length) -{ - sw_error_t rv = SW_OK; - - FAL_API_LOCK; - rv = _fal_shaper_ipg_preamble_length_set(dev_id, ipg_pre_length); - FAL_API_UNLOCK; - return rv; -} -#ifndef IN_SHAPER_MINI -sw_error_t -fal_shaper_ipg_preamble_length_get(a_uint32_t dev_id, a_uint32_t *ipg_pre_length) -{ - sw_error_t rv = SW_OK; - - FAL_API_LOCK; - rv = _fal_shaper_ipg_preamble_length_get(dev_id, ipg_pre_length); - FAL_API_UNLOCK; - return rv; -} -#endif - -EXPORT_SYMBOL(fal_flow_shaper_token_number_set); - -EXPORT_SYMBOL(fal_queue_shaper_token_number_set); - -EXPORT_SYMBOL(fal_port_shaper_token_number_set); - -EXPORT_SYMBOL(fal_port_shaper_timeslot_set); - -EXPORT_SYMBOL(fal_flow_shaper_timeslot_set); - -EXPORT_SYMBOL(fal_queue_shaper_timeslot_set); - -EXPORT_SYMBOL(fal_shaper_ipg_preamble_length_set); - -EXPORT_SYMBOL(fal_port_shaper_set); - -EXPORT_SYMBOL(fal_queue_shaper_get); - -EXPORT_SYMBOL(fal_queue_shaper_set); - -EXPORT_SYMBOL(fal_flow_shaper_set); - -#ifndef IN_SHAPER_MINI - -EXPORT_SYMBOL(fal_port_shaper_get); - -EXPORT_SYMBOL(fal_flow_shaper_get); - -EXPORT_SYMBOL(fal_queue_shaper_token_number_get); - -EXPORT_SYMBOL(fal_flow_shaper_token_number_get); - -EXPORT_SYMBOL(fal_port_shaper_token_number_get); - -EXPORT_SYMBOL(fal_port_shaper_timeslot_get); - -EXPORT_SYMBOL(fal_queue_shaper_timeslot_get); - -EXPORT_SYMBOL(fal_flow_shaper_timeslot_get); - -EXPORT_SYMBOL(fal_shaper_ipg_preamble_length_get); -#endif - -/*insert flag for outter fal, don't remove it*/ diff --git a/feeds/ipq807x/qca-ssdk/src/src/fal/fal_stp.c b/feeds/ipq807x/qca-ssdk/src/src/fal/fal_stp.c deleted file mode 100755 index 882112016..000000000 --- a/feeds/ipq807x/qca-ssdk/src/src/fal/fal_stp.c +++ /dev/null @@ -1,130 +0,0 @@ -/* - * Copyright (c) 2012, 2016-2017, The Linux Foundation. All rights reserved. - * Permission to use, copy, modify, and/or distribute this software for - * any purpose with or without fee is hereby granted, provided that the - * above copyright notice and this permission notice appear in all copies. - * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES - * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR - * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES - * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN - * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT - * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. - */ - - -/** - * @defgroup fal_stp FAL_STP - * @{ - */ -#include "sw.h" -#include "fal_stp.h" -#include "hsl_api.h" -#include "adpt.h" - -static sw_error_t -_fal_stp_port_state_set(a_uint32_t dev_id, a_uint32_t st_id, - fal_port_t port_id, fal_stp_state_t state) -{ - sw_error_t rv; - hsl_api_t *p_api; - adpt_api_t *p_adpt_api; - - if((p_adpt_api = adpt_api_ptr_get(dev_id)) != NULL) { - if (NULL == p_adpt_api->adpt_stp_port_state_set) - return SW_NOT_SUPPORTED; - - rv = p_adpt_api->adpt_stp_port_state_set(dev_id, st_id, port_id, state); - return rv; - } - - SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id)); - - if (NULL == p_api->stp_port_state_set) - return SW_NOT_SUPPORTED; - - rv = p_api->stp_port_state_set(dev_id, st_id, port_id, state); - return rv; -} - -static sw_error_t -_fal_stp_port_state_get(a_uint32_t dev_id, a_uint32_t st_id, - fal_port_t port_id, fal_stp_state_t * state) -{ - sw_error_t rv; - hsl_api_t *p_api; - adpt_api_t *p_adpt_api; - - if((p_adpt_api = adpt_api_ptr_get(dev_id)) != NULL) { - if (NULL == p_adpt_api->adpt_stp_port_state_get) - return SW_NOT_SUPPORTED; - - rv = p_adpt_api->adpt_stp_port_state_get(dev_id, st_id, port_id, state); - return rv; - } - - SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id)); - - if (NULL == p_api->stp_port_state_get) - return SW_NOT_SUPPORTED; - - rv = p_api->stp_port_state_get(dev_id, st_id, port_id, state); - return rv; -} - -/*insert flag for inner fal, don't remove it*/ - -/** - * @brief Set port stp state on a particular spanning tree and port. - * @details Comments: - * For those devices which only support single spanning tree st_id should - * be FAL_SINGLE_STP_ID that is zero. - * @param[in] dev_id device id - * @param[in] st_id spanning tree id - * @param[in] port_id port id - * @param[in] state port state for spanning tree - * @return SW_OK or error code - */ -sw_error_t -fal_stp_port_state_set(a_uint32_t dev_id, a_uint32_t st_id, - fal_port_t port_id, fal_stp_state_t state) -{ - sw_error_t rv; - - FAL_API_LOCK; - rv = _fal_stp_port_state_set(dev_id, st_id, port_id, state); - FAL_API_UNLOCK; - return rv; -} - -/** - * @brief Get port stp state on a particular spanning tree and port. - * @details Comments: - * For those devices which only support single spanning tree st_id should - * be FAL_SINGLE_STP_ID that is zero. - * @param[in] dev_id device id - * @param[in] st_id spanning tree id - * @param[in] port_id port id - * @param[out] state port state for spanning tree - * @return SW_OK or error code - */ -sw_error_t -fal_stp_port_state_get(a_uint32_t dev_id, a_uint32_t st_id, - fal_port_t port_id, fal_stp_state_t * state) -{ - sw_error_t rv; - - FAL_API_LOCK; - rv = _fal_stp_port_state_get(dev_id, st_id, port_id, state); - FAL_API_UNLOCK; - return rv; -} - -/*insert flag for outter fal, don't remove it*/ - -EXPORT_SYMBOL(fal_stp_port_state_set); -EXPORT_SYMBOL(fal_stp_port_state_get); - -/** - * @} - */ diff --git a/feeds/ipq807x/qca-ssdk/src/src/fal/fal_trunk.c b/feeds/ipq807x/qca-ssdk/src/src/fal/fal_trunk.c deleted file mode 100755 index b66909658..000000000 --- a/feeds/ipq807x/qca-ssdk/src/src/fal/fal_trunk.c +++ /dev/null @@ -1,324 +0,0 @@ -/* - * Copyright (c) 2012, 2016-2017, The Linux Foundation. All rights reserved. - * Permission to use, copy, modify, and/or distribute this software for - * any purpose with or without fee is hereby granted, provided that the - * above copyright notice and this permission notice appear in all copies. - * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES - * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR - * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES - * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN - * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT - * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. - */ - - -/** - * @defgroup fal_trunk FAL_TRUNK - * @{ - */ -#include "sw.h" -#include "fal_trunk.h" -#include "hsl_api.h" -#include "adpt.h" - -#include -#include - - -static sw_error_t -_fal_trunk_group_set(a_uint32_t dev_id, a_uint32_t trunk_id, - a_bool_t enable, fal_pbmp_t member) -{ - sw_error_t rv; - hsl_api_t *p_api; - adpt_api_t *p_adpt_api; - - if((p_adpt_api = adpt_api_ptr_get(dev_id)) != NULL) { - if (NULL == p_adpt_api->adpt_trunk_group_set) - return SW_NOT_SUPPORTED; - - rv = p_adpt_api->adpt_trunk_group_set(dev_id, trunk_id, enable, member); - return rv; - } - - SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id)); - - if (NULL == p_api->trunk_group_set) - return SW_NOT_SUPPORTED; - - rv = p_api->trunk_group_set(dev_id, trunk_id, enable, member); - return rv; -} - -static sw_error_t -_fal_trunk_group_get(a_uint32_t dev_id, a_uint32_t trunk_id, - a_bool_t * enable, fal_pbmp_t * member) -{ - sw_error_t rv; - hsl_api_t *p_api; - adpt_api_t *p_adpt_api; - - if((p_adpt_api = adpt_api_ptr_get(dev_id)) != NULL) { - if (NULL == p_adpt_api->adpt_trunk_group_get) - return SW_NOT_SUPPORTED; - - rv = p_adpt_api->adpt_trunk_group_get(dev_id, trunk_id, enable, member); - return rv; - } - - SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id)); - - if (NULL == p_api->trunk_group_get) - return SW_NOT_SUPPORTED; - - rv = p_api->trunk_group_get(dev_id, trunk_id, enable, member); - return rv; -} - -static sw_error_t -_fal_trunk_hash_mode_set(a_uint32_t dev_id, a_uint32_t hash_mode) -{ - sw_error_t rv; - hsl_api_t *p_api; - adpt_api_t *p_adpt_api; - - if((p_adpt_api = adpt_api_ptr_get(dev_id)) != NULL) { - if (NULL == p_adpt_api->adpt_trunk_hash_mode_set) - return SW_NOT_SUPPORTED; - - rv = p_adpt_api->adpt_trunk_hash_mode_set(dev_id, hash_mode); - return rv; - } - - SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id)); - - if (NULL == p_api->trunk_hash_mode_set) - return SW_NOT_SUPPORTED; - - rv = p_api->trunk_hash_mode_set(dev_id, hash_mode); - return rv; -} - -static sw_error_t -_fal_trunk_hash_mode_get(a_uint32_t dev_id, a_uint32_t * hash_mode) -{ - sw_error_t rv; - hsl_api_t *p_api; - adpt_api_t *p_adpt_api; - - if((p_adpt_api = adpt_api_ptr_get(dev_id)) != NULL) { - if (NULL == p_adpt_api->adpt_trunk_hash_mode_get) - return SW_NOT_SUPPORTED; - - rv = p_adpt_api->adpt_trunk_hash_mode_get(dev_id, hash_mode); - return rv; - } - - SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id)); - - if (NULL == p_api->trunk_hash_mode_get) - return SW_NOT_SUPPORTED; - - rv = p_api->trunk_hash_mode_get(dev_id, hash_mode); - return rv; -} - -static sw_error_t -_fal_trunk_manipulate_sa_set(a_uint32_t dev_id, fal_mac_addr_t * addr) -{ - sw_error_t rv; - hsl_api_t *p_api; - - SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id)); - - if (NULL == p_api->trunk_manipulate_sa_set) - return SW_NOT_SUPPORTED; - - rv = p_api->trunk_manipulate_sa_set(dev_id, addr); - return rv; -} - -static sw_error_t -_fal_trunk_manipulate_sa_get(a_uint32_t dev_id, fal_mac_addr_t * addr) -{ - sw_error_t rv; - hsl_api_t *p_api; - - SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id)); - - if (NULL == p_api->trunk_manipulate_sa_get) - return SW_NOT_SUPPORTED; - - rv = p_api->trunk_manipulate_sa_get(dev_id, addr); - return rv; -} -sw_error_t -_fal_trunk_failover_status_get(a_uint32_t dev_id, a_bool_t * failover) -{ - adpt_api_t *p_api; - sw_error_t rv = SW_OK; - - SW_RTN_ON_NULL(p_api = adpt_api_ptr_get(dev_id)); - - if (NULL == p_api->adpt_trunk_fail_over_en_get) - return SW_NOT_SUPPORTED; - - rv = p_api->adpt_trunk_fail_over_en_get(dev_id, failover); - return rv; -} -sw_error_t -_fal_trunk_failover_enable(a_uint32_t dev_id, a_bool_t failover) -{ - adpt_api_t *p_api; - sw_error_t rv = SW_OK; - - SW_RTN_ON_NULL(p_api = adpt_api_ptr_get(dev_id)); - - if (NULL == p_api->adpt_trunk_fail_over_en_set) - return SW_NOT_SUPPORTED; - - rv = p_api->adpt_trunk_fail_over_en_set(dev_id, failover); - return rv; -} - -/*insert flag for inner fal, don't remove it*/ -/** - * @brief Set particular trunk group information on particular device. - * @param[in] dev_id device id - * @param[in] trunk_id trunk group id - * @param[in] enable trunk group status, enable or disable - * @param[in] member port member information - * @return SW_OK or error code - */ -sw_error_t -fal_trunk_group_set(a_uint32_t dev_id, a_uint32_t trunk_id, - a_bool_t enable, fal_pbmp_t member) -{ - sw_error_t rv; - - FAL_API_LOCK; - rv = _fal_trunk_group_set(dev_id, trunk_id, enable, member); - FAL_API_UNLOCK; - return rv; -} - -/** - * @brief Get particular trunk group information on particular device. - * @param[in] dev_id device id - * @param[in] trunk_id trunk group id - * @param[out] enable trunk group status, enable or disable - * @param[out] member port member information - * @return SW_OK or error code - */ -sw_error_t -fal_trunk_group_get(a_uint32_t dev_id, a_uint32_t trunk_id, - a_bool_t * enable, fal_pbmp_t * member) -{ - sw_error_t rv; - - FAL_API_LOCK; - rv = _fal_trunk_group_get(dev_id, trunk_id, enable, member); - FAL_API_UNLOCK; - return rv; -} - -/** - * @brief Set trunk hash mode on particular device. - * @param[in] dev_id device id - * @param[in] hash_mode trunk hash mode - * @return SW_OK or error code - */ -sw_error_t -fal_trunk_hash_mode_set(a_uint32_t dev_id, a_uint32_t hash_mode) -{ - sw_error_t rv; - - FAL_API_LOCK; - rv = _fal_trunk_hash_mode_set(dev_id, hash_mode); - FAL_API_UNLOCK; - return rv; -} - -/** - * @brief Get trunk hash mode on particular device. - * @param[in] dev_id device id - * @param[out] hash_mode trunk hash mode - * @return SW_OK or error code - */ -sw_error_t -fal_trunk_hash_mode_get(a_uint32_t dev_id, a_uint32_t * hash_mode) -{ - sw_error_t rv; - - FAL_API_LOCK; - rv = _fal_trunk_hash_mode_get(dev_id, hash_mode); - FAL_API_UNLOCK; - return rv; -} - -/** - * @brief Set trunk manipulate SA on particular device. - * @param[in] dev_id device id - * @param[in] addr manipulate SA - * @return SW_OK or error code - */ -sw_error_t -fal_trunk_manipulate_sa_set(a_uint32_t dev_id, fal_mac_addr_t * addr) -{ - sw_error_t rv; - - FAL_API_LOCK; - rv = _fal_trunk_manipulate_sa_set(dev_id, addr); - FAL_API_UNLOCK; - return rv; -} - -/** - * @brief Get trunk manipulate SA on particular device. - * @param[in] dev_id device id - * @param[out] addr manipulate SA - * @return SW_OK or error code - */ -sw_error_t -fal_trunk_manipulate_sa_get(a_uint32_t dev_id, fal_mac_addr_t * addr) -{ - sw_error_t rv; - - FAL_API_LOCK; - rv = _fal_trunk_manipulate_sa_get(dev_id, addr); - FAL_API_UNLOCK; - return rv; -} -sw_error_t -fal_trunk_failover_status_get(a_uint32_t dev_id, a_bool_t * failover) -{ - sw_error_t rv = SW_OK; - - FAL_API_LOCK; - rv = _fal_trunk_failover_status_get(dev_id, failover); - FAL_API_UNLOCK; - return rv; -} -sw_error_t -fal_trunk_failover_enable(a_uint32_t dev_id, a_bool_t failover) -{ - sw_error_t rv = SW_OK; - - FAL_API_LOCK; - rv = _fal_trunk_failover_enable(dev_id, failover); - FAL_API_UNLOCK; - return rv; -} -/*insert flag for outter fal, don't remove it*/ - -EXPORT_SYMBOL(fal_trunk_group_set); -EXPORT_SYMBOL(fal_trunk_group_get); -EXPORT_SYMBOL(fal_trunk_hash_mode_set); -EXPORT_SYMBOL(fal_trunk_hash_mode_get); -EXPORT_SYMBOL(fal_trunk_failover_status_get); -EXPORT_SYMBOL(fal_trunk_failover_enable); - -/** - * @} - */ diff --git a/feeds/ipq807x/qca-ssdk/src/src/fal/fal_vlan.c b/feeds/ipq807x/qca-ssdk/src/src/fal/fal_vlan.c deleted file mode 100755 index b5c37fb46..000000000 --- a/feeds/ipq807x/qca-ssdk/src/src/fal/fal_vlan.c +++ /dev/null @@ -1,933 +0,0 @@ -/* - * Copyright (c) 2012, 2016, The Linux Foundation. All rights reserved. - * Permission to use, copy, modify, and/or distribute this software for - * any purpose with or without fee is hereby granted, provided that the - * above copyright notice and this permission notice appear in all copies. - * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES - * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR - * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES - * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN - * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT - * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. - */ - - - -/** - * @defgroup fal_vlan FAL_VLAN - * @{ - */ - -#include "sw.h" -#include "util.h" -#include "fal_vlan.h" -#include "hsl.h" -#include "hsl_dev.h" -#include "hsl_api.h" - -typedef struct -{ - a_uint32_t idx; - fal_vlan_t entry; -} v_array_t; - -static v_array_t * vlan_db[SW_MAX_NR_DEV] = { 0 }; -static sid_pool_t * vlan_pool[SW_MAX_NR_DEV] = { 0 }; -static sll_head_t * vlan_list[SW_MAX_NR_DEV] = { 0 }; - - -static sw_error_t -_fal_vlan_search(a_uint32_t dev_id, fal_vlan_t * vlan_entry) -{ - a_ulong_t iterator; - v_array_t v_tbl; - v_array_t * p_tbl; - hsl_dev_t * p_dev = NULL; - - p_dev = hsl_dev_ptr_get(dev_id); - SW_RTN_ON_NULL(p_dev); - - if (A_TRUE == p_dev->hw_vlan_query) - { - return SW_NOT_FOUND; - } - - v_tbl.entry = * vlan_entry; - p_tbl = sll_nd_find(vlan_list[dev_id], &v_tbl, &iterator); - - if (NULL == p_tbl) - { - return SW_NOT_FOUND; - } - else - { - * vlan_entry = p_tbl->entry; - return SW_OK; - } -} - -static sw_error_t -_fal_vlan_following(a_uint32_t dev_id, fal_vlan_t * vlan_entry) -{ - a_ulong_t iterator = 0; - v_array_t v_tbl; - v_array_t * p_tbl; - hsl_dev_t * p_dev = NULL; - - p_dev = hsl_dev_ptr_get(dev_id); - SW_RTN_ON_NULL(p_dev); - - if (A_TRUE == p_dev->hw_vlan_query) - { - return SW_OK; - } - - sll_lock(vlan_list[dev_id]); - - v_tbl.entry = *vlan_entry; - - if (0 == v_tbl.entry.vid) - { - p_tbl = sll_nd_next(vlan_list[dev_id], &iterator); - } - else - { - p_tbl = sll_nd_find(vlan_list[dev_id], &v_tbl, &iterator); - if (NULL == p_tbl) - { - sll_unlock(vlan_list[dev_id]); - return SW_NO_MORE; - } - - p_tbl = sll_nd_next(vlan_list[dev_id], &iterator); - } - - if (NULL == p_tbl) - { - sll_unlock(vlan_list[dev_id]); - return SW_NO_MORE; - } - - * vlan_entry = p_tbl->entry; - sll_unlock(vlan_list[dev_id]); - return SW_OK; -} - -static sw_error_t -_fal_vlan_del(a_uint32_t dev_id, a_uint16_t vlan_id) -{ - v_array_t * p_tbl; - v_array_t ent; - sw_error_t rv; - a_ulong_t iterator; - a_uint32_t id; - hsl_dev_t * p_dev = NULL; - - p_dev = hsl_dev_ptr_get(dev_id); - SW_RTN_ON_NULL(p_dev); - - if (A_TRUE == p_dev->hw_vlan_query) - { - return SW_OK; - } - - ent.entry.vid = vlan_id; - p_tbl = sll_nd_find(vlan_list[dev_id], &ent, &iterator); - if (NULL == p_tbl) - { - return SW_NOT_FOUND; - } - id = p_tbl->idx; - - rv = sll_nd_delete(vlan_list[dev_id], p_tbl); - SW_RTN_ON_ERROR(rv); - - rv = sid_pool_id_free(vlan_pool[dev_id], id); - return rv; -} - -static sw_error_t -_fal_vlan_creat(a_uint32_t dev_id, const fal_vlan_t * vlan_entry) -{ - v_array_t * v_tbl; - sw_error_t rv; - a_uint32_t id; - hsl_dev_t * p_dev = NULL; - - p_dev = hsl_dev_ptr_get(dev_id); - SW_RTN_ON_NULL(p_dev); - - if (A_TRUE == p_dev->hw_vlan_query) - { - return SW_OK; - } - - rv = sid_pool_id_alloc(vlan_pool[dev_id], &id); - SW_RTN_ON_ERROR(rv); - - v_tbl = &vlan_db[dev_id][id]; - v_tbl->idx = id; - v_tbl->entry = *vlan_entry; - rv = sll_nd_insert(vlan_list[dev_id], v_tbl); - return rv; -} - -static sw_error_t -_fal_vlan_update(a_uint32_t dev_id, const fal_vlan_t * vlan_entry) -{ - a_ulong_t iterator; - v_array_t v_tbl; - v_array_t * p_tbl; - hsl_dev_t * p_dev = NULL; - - p_dev = hsl_dev_ptr_get(dev_id); - SW_RTN_ON_NULL(p_dev); - - if (A_TRUE == p_dev->hw_vlan_query) - { - return SW_OK; - } - - sll_lock(vlan_list[dev_id]); - v_tbl.entry = *vlan_entry; - p_tbl = sll_nd_find(vlan_list[dev_id], &v_tbl, &iterator); - - if (NULL == p_tbl) - { - sll_unlock(vlan_list[dev_id]); - return SW_NOT_FOUND; - } - - p_tbl->entry = * vlan_entry; - sll_unlock(vlan_list[dev_id]); - return SW_OK; -} - -static ll_cmp_rslt_t -_fal_vlan_entry_cmp(void * src, void * dest) -{ - v_array_t * src_nd, * dest_nd; - - src_nd = (v_array_t*)src; - dest_nd = (v_array_t*)dest; - - if (src_nd->entry.vid == dest_nd->entry.vid) - { - return LL_CMP_EQUAL; - } - else if (src_nd->entry.vid > dest_nd->entry.vid) - { - return LL_CMP_GREATER; - } - else - { - return LL_CMP_SMALLER; - } -} - -static void -_fal_vlan_entry_dump(void * data) -{ - v_array_t * nd; - - nd = (v_array_t*)data; - aos_printk("vid = %d member = 0x%x\n", nd->entry.vid, nd->entry.mem_ports); -} - - -static sw_error_t -_fal_vlan_entry_append(a_uint32_t dev_id, fal_vlan_t * vlan_entry) -{ - sw_error_t rv; - hsl_api_t *p_api; - - rv = _fal_vlan_search(dev_id, vlan_entry); - if (SW_OK == rv) - { - return SW_ALREADY_EXIST; - } - - SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id)); - if (NULL == p_api->vlan_entry_append) - return SW_NOT_SUPPORTED; - - rv = p_api->vlan_entry_append(dev_id, vlan_entry); - SW_RTN_ON_ERROR(rv); - - rv = _fal_vlan_creat(dev_id, vlan_entry); - return rv; -} - - -static sw_error_t -_fal_vlan_create(a_uint32_t dev_id, a_uint32_t vlan_id) -{ - sw_error_t rv; - fal_vlan_t entry; - hsl_api_t *p_api; - - aos_mem_zero(&(entry), sizeof(fal_vlan_t)); - entry.vid = vlan_id; - rv = _fal_vlan_search(dev_id, &entry); - if (SW_OK == rv) - { - return SW_ALREADY_EXIST; - } - - SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id)); - if (NULL == p_api->vlan_creat) - return SW_NOT_SUPPORTED; - - rv = p_api->vlan_creat(dev_id, vlan_id); - SW_RTN_ON_ERROR(rv); - - rv = _fal_vlan_creat(dev_id, &entry); - return rv; -} - - -static sw_error_t -_fal_vlan_next(a_uint32_t dev_id, a_uint32_t vlan_id, fal_vlan_t * p_vlan) -{ - sw_error_t rv; - hsl_api_t *p_api; - - SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id)); - - if (NULL == p_api->vlan_next) - { - p_vlan->vid = vlan_id; - rv = _fal_vlan_following(dev_id, p_vlan); - } - else - { - rv = p_api->vlan_next(dev_id, vlan_id, p_vlan); - } - return rv; -} - - -static sw_error_t -_fal_vlan_find(a_uint32_t dev_id, a_uint32_t vlan_id, fal_vlan_t * p_vlan) -{ - sw_error_t rv; - hsl_api_t *p_api; - - SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id)); - - if (NULL == p_api->vlan_find) - { - p_vlan->vid = vlan_id; - rv = _fal_vlan_search(dev_id, p_vlan); - } - else - { - rv = p_api->vlan_find(dev_id, vlan_id, p_vlan); - } - return rv; -} - - -static sw_error_t -_fal_vlan_member_update(a_uint32_t dev_id, a_uint32_t vlan_id, - fal_pbmp_t member, fal_pbmp_t u_member) -{ - sw_error_t rv; - fal_vlan_t vlan_entry = {0}; - hsl_api_t *p_api; - hsl_dev_t *p_dev = NULL; - - p_dev = hsl_dev_ptr_get(dev_id); - SW_RTN_ON_NULL(p_dev); - - if (A_FALSE == p_dev->hw_vlan_query) - { - vlan_entry.vid = vlan_id; - rv = _fal_vlan_search(dev_id, &vlan_entry); - SW_RTN_ON_ERROR(rv); - } - - vlan_entry.mem_ports = member; - vlan_entry.u_ports = u_member; - - SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id)); - if (NULL == p_api->vlan_member_update) - { - if ((NULL == p_api->vlan_entry_append) - || (NULL == p_api->vlan_delete)) - { - return SW_NOT_SUPPORTED; - } - - p_api->vlan_delete(dev_id, vlan_id); - - vlan_entry.vid = vlan_id; - vlan_entry.fid = vlan_id; - - vlan_entry.untagged_ports = u_member; - vlan_entry.tagged_ports = member & ~u_member; - - rv = p_api->vlan_entry_append(dev_id, &vlan_entry); - SW_RTN_ON_ERROR(rv); - } - else - { - - rv = p_api->vlan_member_update(dev_id, vlan_id, member, u_member); - SW_RTN_ON_ERROR(rv); - } - rv = _fal_vlan_update(dev_id, &vlan_entry); - return rv; -} - - -static sw_error_t -_fal_vlan_delete(a_uint32_t dev_id, a_uint32_t vlan_id) -{ - sw_error_t rv; - hsl_api_t *p_api; - - SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id)); - - if (NULL == p_api->vlan_delete) - return SW_NOT_SUPPORTED; - - rv = p_api->vlan_delete(dev_id, vlan_id); - SW_RTN_ON_ERROR(rv); - - rv = _fal_vlan_del(dev_id, vlan_id); - return rv; -} - -static sw_error_t -_fal_vlan_flush(a_uint32_t dev_id) -{ - sw_error_t rv; - hsl_api_t *p_api; - - SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id)); - - if (NULL == p_api->vlan_flush) - return SW_NOT_SUPPORTED; - - rv = p_api->vlan_flush(dev_id); - SW_RTN_ON_ERROR(rv); - - rv = fal_vlan_reset(dev_id); - return rv; -} - -/** - * @brief Set FID of a paticular vlan entry on a paticular device. - * @param[in] dev_id device id - * @param[in] vlan_id vlan id - * @param[in] fid FDB id - * @return SW_OK or error code - */ -static sw_error_t -_fal_vlan_fid_set(a_uint32_t dev_id, a_uint32_t vlan_id, a_uint32_t fid) -{ - sw_error_t rv; - hsl_api_t *p_api; - - SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id)); - - if (NULL == p_api->vlan_fid_set) - return SW_NOT_SUPPORTED; - - rv = p_api->vlan_fid_set(dev_id, vlan_id, fid); - return rv; -} - -/** - * @brief Get FID of a paticular vlan entry on a paticular device. - * @param[in] dev_id device id - * @param[in] vlan_id vlan id - * @param[out] fid FDB id - * @return SW_OK or error code - */ -static sw_error_t -_fal_vlan_fid_get(a_uint32_t dev_id, a_uint32_t vlan_id, a_uint32_t * fid) -{ - sw_error_t rv; - hsl_api_t *p_api; - - SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id)); - - if (NULL == p_api->vlan_fid_get) - return SW_NOT_SUPPORTED; - - rv = p_api->vlan_fid_get(dev_id, vlan_id, fid); - return rv; -} - -/** - * @brief Add a port member to a paticular vlan entry on a paticular device. - * @param[in] dev_id device id - * @param[in] vlan_id vlan id - * @param[in] port_id port id - * @param[in] port_info port tag information - * @return SW_OK or error code - */ -static sw_error_t -_fal_vlan_member_add(a_uint32_t dev_id, a_uint32_t vlan_id, - fal_port_t port_id, fal_pt_1q_egmode_t port_info) -{ - sw_error_t rv; - hsl_api_t *p_api; - - SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id)); - - if (NULL == p_api->vlan_member_add) - return SW_NOT_SUPPORTED; - - rv = p_api->vlan_member_add(dev_id, vlan_id, port_id, port_info); - return rv; -} - -/** - * @brief Del a port member from a paticular vlan entry on a paticular device. - * @param[in] dev_id device id - * @param[in] vlan_id vlan id - * @param[in] port_id port id - * @return SW_OK or error code - */ -static sw_error_t -_fal_vlan_member_del(a_uint32_t dev_id, a_uint32_t vlan_id, fal_port_t port_id) -{ - sw_error_t rv; - hsl_api_t *p_api; - - SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id)); - - if (NULL == p_api->vlan_member_del) - return SW_NOT_SUPPORTED; - - rv = p_api->vlan_member_del(dev_id, vlan_id, port_id); - return rv; -} - -/** - * @brief Set FDB learning status of a paticular vlan entry on a paticular device. - * @param[in] dev_id device id - * @param[in] vlan_id vlan id - * @param[in] enable A_TRUE or A_FALSE - * @return SW_OK or error code - */ -static sw_error_t -_fal_vlan_learning_state_set(a_uint32_t dev_id, a_uint32_t vlan_id, - a_bool_t enable) -{ - sw_error_t rv; - hsl_api_t *p_api; - - SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id)); - - if (NULL == p_api->vlan_learning_state_set) - return SW_NOT_SUPPORTED; - - rv = p_api->vlan_learning_state_set(dev_id, vlan_id, enable); - return rv; -} - -/** - * @brief Get FDB learning status of a paticular vlan entry on a paticular device. - * @param[in] dev_id device id - * @param[in] vlan_id vlan id - * @param[out] enable A_TRUE or A_FALSE - * @return SW_OK or error code - */ -static sw_error_t -_fal_vlan_learning_state_get(a_uint32_t dev_id, a_uint32_t vlan_id, - a_bool_t * enable) -{ - sw_error_t rv; - hsl_api_t *p_api; - - SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id)); - - if (NULL == p_api->vlan_learning_state_get) - return SW_NOT_SUPPORTED; - - rv = p_api->vlan_learning_state_get(dev_id, vlan_id, enable); - return rv; -} - -/** - * @brief Reset fal vlan module on a paticular device. - * @param[in] dev_id device id - * @return SW_OK or error code - */ -sw_error_t -fal_vlan_reset(a_uint32_t dev_id) -{ - a_uint32_t entry_nr; - hsl_dev_t *p_dev = NULL; - - p_dev = hsl_dev_ptr_get(dev_id); - SW_RTN_ON_NULL(p_dev); - - if (A_TRUE == p_dev->hw_vlan_query) - { - return SW_OK; - } - - entry_nr = p_dev->nr_vlans; - if ((0 == entry_nr) || (4096 < entry_nr)) - { - return SW_FAIL; - } - - if (NULL != vlan_pool[dev_id]) - { - sid_pool_destroy(vlan_pool[dev_id]); - vlan_pool[dev_id] = NULL; - } - - if (NULL != vlan_list[dev_id]) - { - sll_destroy(vlan_list[dev_id]); - vlan_list[dev_id] = NULL; - } - - aos_mem_zero(vlan_db[dev_id], entry_nr * (sizeof (v_array_t))); - - vlan_pool[dev_id] = sid_pool_creat(entry_nr, 0); - if (NULL == vlan_pool[dev_id]) - { - return SW_FAIL; - } - - vlan_list[dev_id] = sll_creat(_fal_vlan_entry_cmp, _fal_vlan_entry_dump, - LL_FIX_NDNR | LL_IN_ORDER, entry_nr); - if (NULL == vlan_list[dev_id]) - { - return SW_FAIL; - } - - return SW_OK; -} - - -/** - * @brief Init fal vlan module on a paticular device. - * @param[in] dev_id device id - * @return SW_OK or error code - */ -sw_error_t -fal_vlan_init(a_uint32_t dev_id) -{ - a_uint32_t entry_nr; - hsl_dev_t *p_dev = NULL; - - p_dev = hsl_dev_ptr_get(dev_id); - SW_RTN_ON_NULL(p_dev); - - if (A_TRUE == p_dev->hw_vlan_query) - { - return SW_OK; - } - - entry_nr = p_dev->nr_vlans; - if ((0 == entry_nr) || (4096 < entry_nr)) - { - return SW_FAIL; - } - - vlan_pool[dev_id] = sid_pool_creat(entry_nr, 0); - if (NULL == vlan_pool[dev_id]) - { - return SW_FAIL; - } - - /* allocate memory for vlan entry */ - vlan_db[dev_id] = aos_mem_alloc(entry_nr * (sizeof (v_array_t))); - if (NULL == vlan_db[dev_id]) - { - return SW_OUT_OF_MEM; - } - aos_mem_zero(vlan_db[dev_id], entry_nr * (sizeof (v_array_t))); - - vlan_list[dev_id] = sll_creat(_fal_vlan_entry_cmp, _fal_vlan_entry_dump, - LL_FIX_NDNR | LL_IN_ORDER, entry_nr); - - if (NULL == vlan_list[dev_id]) - { - return SW_FAIL; - } - - return SW_OK; -} - -sw_error_t -fal_vlan_cleanup(void) -{ - a_uint32_t dev_id; - - for (dev_id = 0; dev_id < SW_MAX_NR_DEV; dev_id++) - { - if (vlan_db[dev_id]) - { - aos_mem_free(vlan_db[dev_id]); - vlan_db[dev_id] = NULL; - } - - if (vlan_pool[dev_id]) - { - sid_pool_destroy(vlan_pool[dev_id]); - vlan_pool[dev_id] = NULL; - } - - if (vlan_list[dev_id]) - { - sll_destroy(vlan_list[dev_id]); - vlan_list[dev_id] = NULL; - } - } - - return SW_OK; -} - -/** - * @brief Append a vlan entry on paticular device. - * @param[in] dev_id device id - * @param[in] vlan_entry vlan entry - * @return SW_OK or error code - */ -sw_error_t -fal_vlan_entry_append(a_uint32_t dev_id, fal_vlan_t * vlan_entry) -{ - sw_error_t rv; - - FAL_API_LOCK; - rv = _fal_vlan_entry_append(dev_id, vlan_entry); - FAL_API_UNLOCK; - return rv; -} - -/** - * @brief Creat a vlan entry through vlan id on a paticular device. - * @details Comments: - * After this operation the member ports of the created vlan entry are null. - * @param[in] dev_id device id - * @param[in] vlan_id vlan id - * @return SW_OK or error code - */ -sw_error_t -fal_vlan_create(a_uint32_t dev_id, a_uint32_t vlan_id) -{ - sw_error_t rv; - - FAL_API_LOCK; - rv = _fal_vlan_create(dev_id, vlan_id); - FAL_API_UNLOCK; - return rv; -} - -/** - * @brief Next a vlan entry through vlan id on a paticular device. - * @details Comments: - * If the value of vid is zero this operation will get the first entry. - * @param[in] dev_id device id - * @param[in] vlan_id vlan id - * @param[out] p_vlan vlan entry - * @return SW_OK or error code - */ -sw_error_t -fal_vlan_next(a_uint32_t dev_id, a_uint32_t vlan_id, fal_vlan_t * p_vlan) -{ - sw_error_t rv; - - FAL_API_LOCK; - rv = _fal_vlan_next(dev_id, vlan_id, p_vlan); - FAL_API_UNLOCK; - return rv; -} - -/** - * @brief Find a vlan entry through vlan id on paticular device. - * @param[in] dev_id device id - * @param[in] vlan_id vlan id - * @param[out] p_vlan vlan entry - * @return SW_OK or error code - */ -sw_error_t -fal_vlan_find(a_uint32_t dev_id, a_uint32_t vlan_id, fal_vlan_t * p_vlan) -{ - sw_error_t rv; - - FAL_API_LOCK; - rv = _fal_vlan_find(dev_id, vlan_id, p_vlan); - FAL_API_UNLOCK; - return rv; -} - -/** - * @brief Update a vlan entry member port through vlan id on a paticular device. - * @param[in] dev_id device id - * @param[in] vlan_id vlan id - * @param[in] member member ports - * @param[in] u_member tagged or untagged infomation for member ports - * @return SW_OK or error code - */ -sw_error_t -fal_vlan_member_update(a_uint32_t dev_id, a_uint32_t vlan_id, - fal_pbmp_t member, fal_pbmp_t u_member) -{ - sw_error_t rv; - - FAL_API_LOCK; - rv = _fal_vlan_member_update(dev_id, vlan_id, member, u_member); - FAL_API_UNLOCK; - return rv; -} - -/** - * @brief Delete a vlan entry through vlan id on a paticular device. - * @param[in] dev_id device id - * @param[in] vlan_id vlan id - * @return SW_OK or error code - */ -sw_error_t -fal_vlan_delete(a_uint32_t dev_id, a_uint32_t vlan_id) -{ - sw_error_t rv; - - FAL_API_LOCK; - rv = _fal_vlan_delete(dev_id, vlan_id); - FAL_API_UNLOCK; - return rv; -} - -/** - * @brief Flush all vlan entries on a paticular device. - * @param[in] dev_id device id - * @return SW_OK or error code - */ -sw_error_t -fal_vlan_flush(a_uint32_t dev_id) -{ - sw_error_t rv; - - FAL_API_LOCK; - rv = _fal_vlan_flush(dev_id); - FAL_API_UNLOCK; - return rv; -} - -/** - * @brief Set FID of a paticular vlan entry on a paticular device. - * @param[in] dev_id device id - * @param[in] vlan_id vlan id - * @param[in] fid FDB id - * @return SW_OK or error code - */ -sw_error_t -fal_vlan_fid_set(a_uint32_t dev_id, a_uint32_t vlan_id, a_uint32_t fid) -{ - sw_error_t rv; - - FAL_API_LOCK; - rv = _fal_vlan_fid_set(dev_id, vlan_id, fid); - FAL_API_UNLOCK; - return rv; -} - -/** - * @brief Get FID of a paticular vlan entry on a paticular device. - * @param[in] dev_id device id - * @param[in] vlan_id vlan id - * @param[out] fid FDB id - * @return SW_OK or error code - */ -sw_error_t -fal_vlan_fid_get(a_uint32_t dev_id, a_uint32_t vlan_id, a_uint32_t * fid) -{ - sw_error_t rv; - - FAL_API_LOCK; - rv = _fal_vlan_fid_get(dev_id, vlan_id, fid); - FAL_API_UNLOCK; - return rv; -} - -/** - * @brief Add a port member to a paticular vlan entry on a paticular device. - * @param[in] dev_id device id - * @param[in] vlan_id vlan id - * @param[in] port_id port id - * @param[in] port_info port tag information - * @return SW_OK or error code - */ -sw_error_t -fal_vlan_member_add(a_uint32_t dev_id, a_uint32_t vlan_id, - fal_port_t port_id, fal_pt_1q_egmode_t port_info) -{ - sw_error_t rv; - - FAL_API_LOCK; - rv = _fal_vlan_member_add(dev_id, vlan_id, port_id, port_info); - FAL_API_UNLOCK; - return rv; -} - -/** - * @brief Del a port member from a paticular vlan entry on a paticular device. - * @param[in] dev_id device id - * @param[in] vlan_id vlan id - * @param[in] port_id port id - * @return SW_OK or error code - */ -sw_error_t -fal_vlan_member_del(a_uint32_t dev_id, a_uint32_t vlan_id, fal_port_t port_id) -{ - sw_error_t rv; - - FAL_API_LOCK; - rv = _fal_vlan_member_del(dev_id, vlan_id, port_id); - FAL_API_UNLOCK; - return rv; -} - -/** - * @brief Set FDB learning status of a paticular vlan entry on a paticular device. - * @param[in] dev_id device id - * @param[in] vlan_id vlan id - * @param[in] enable A_TRUE or A_FALSE - * @return SW_OK or error code - */ -sw_error_t -fal_vlan_learning_state_set(a_uint32_t dev_id, a_uint32_t vlan_id, - a_bool_t enable) -{ - sw_error_t rv; - - FAL_API_LOCK; - rv = _fal_vlan_learning_state_set(dev_id, vlan_id, enable); - FAL_API_UNLOCK; - return rv; -} - -/** - * @brief Get FDB learning status of a paticular vlan entry on a paticular device. - * @param[in] dev_id device id - * @param[in] vlan_id vlan id - * @param[out] enable A_TRUE or A_FALSE - * @return SW_OK or error code - */ -sw_error_t -fal_vlan_learning_state_get(a_uint32_t dev_id, a_uint32_t vlan_id, - a_bool_t * enable) -{ - sw_error_t rv; - - FAL_API_LOCK; - rv = _fal_vlan_learning_state_get(dev_id, vlan_id, enable); - FAL_API_UNLOCK; - return rv; -} - -/** - * @} - */ diff --git a/feeds/ipq807x/qca-ssdk/src/src/fal/fal_vsi.c b/feeds/ipq807x/qca-ssdk/src/src/fal/fal_vsi.c deleted file mode 100755 index a40acd5e7..000000000 --- a/feeds/ipq807x/qca-ssdk/src/src/fal/fal_vsi.c +++ /dev/null @@ -1,343 +0,0 @@ -/* - * Copyright (c) 2016-2017, The Linux Foundation. All rights reserved. - * Permission to use, copy, modify, and/or distribute this software for - * any purpose with or without fee is hereby granted, provided that the - * above copyright notice and this permission notice appear in all copies. - * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES - * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR - * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES - * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN - * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT - * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. - */ -#include "fal_vsi.h" -#include "adpt.h" -#include "hsl_api.h" - -sw_error_t -_fal_port_vlan_vsi_set(a_uint32_t dev_id, fal_port_t port_id, a_uint32_t stag_vid, a_uint32_t ctag_vid, a_uint32_t vsi_id) -{ - adpt_api_t *p_api; - sw_error_t rv = SW_OK; - - SW_RTN_ON_NULL(p_api = adpt_api_ptr_get(dev_id)); - - if (NULL == p_api->adpt_port_vlan_vsi_set) - return SW_NOT_SUPPORTED; - - rv = p_api->adpt_port_vlan_vsi_set(dev_id, port_id, stag_vid, ctag_vid, vsi_id); - return rv; -} -sw_error_t -_fal_port_vlan_vsi_get(a_uint32_t dev_id, fal_port_t port_id, a_uint32_t stag_vid, a_uint32_t ctag_vid, a_uint32_t *vsi_id) -{ - adpt_api_t *p_api; - sw_error_t rv = SW_OK; - - SW_RTN_ON_NULL(p_api = adpt_api_ptr_get(dev_id)); - - if (NULL == p_api->adpt_port_vlan_vsi_get) - return SW_NOT_SUPPORTED; - - rv = p_api->adpt_port_vlan_vsi_get(dev_id, port_id, stag_vid, ctag_vid, vsi_id); - return rv; -} - -sw_error_t -_fal_port_vsi_set(a_uint32_t dev_id, fal_port_t port_id, a_uint32_t vsi_id) -{ - adpt_api_t *p_api; - sw_error_t rv = SW_OK; - - SW_RTN_ON_NULL(p_api = adpt_api_ptr_get(dev_id)); - - if (NULL == p_api->adpt_port_vsi_set) - return SW_NOT_SUPPORTED; - - rv = p_api->adpt_port_vsi_set(dev_id, port_id, vsi_id); - return rv; -} -#ifndef IN_VSI_MINI -sw_error_t -_fal_port_vsi_get(a_uint32_t dev_id, fal_port_t port_id, a_uint32_t *vsi_id) -{ - adpt_api_t *p_api; - sw_error_t rv = SW_OK; - - SW_RTN_ON_NULL(p_api = adpt_api_ptr_get(dev_id)); - - if (NULL == p_api->adpt_port_vsi_get) - return SW_NOT_SUPPORTED; - - rv = p_api->adpt_port_vsi_get(dev_id, port_id, vsi_id); - return rv; -} -#endif -sw_error_t -_fal_vsi_stamove_set(a_uint32_t dev_id, a_uint32_t vsi_id, fal_vsi_stamove_t *stamove) -{ - adpt_api_t *p_api; - sw_error_t rv = SW_OK; - - SW_RTN_ON_NULL(p_api = adpt_api_ptr_get(dev_id)); - - if (NULL == p_api->adpt_vsi_stamove_set) - return SW_NOT_SUPPORTED; - - rv = p_api->adpt_vsi_stamove_set(dev_id, vsi_id, stamove); - return rv; -} -#ifndef IN_VSI_MINI -sw_error_t -_fal_vsi_stamove_get(a_uint32_t dev_id, a_uint32_t vsi_id, fal_vsi_stamove_t *stamove) -{ - adpt_api_t *p_api; - sw_error_t rv = SW_OK; - - SW_RTN_ON_NULL(p_api = adpt_api_ptr_get(dev_id)); - - if (NULL == p_api->adpt_vsi_stamove_get) - return SW_NOT_SUPPORTED; - - rv = p_api->adpt_vsi_stamove_get(dev_id, vsi_id, stamove); - return rv; -} -sw_error_t -_fal_vsi_newaddr_lrn_get(a_uint32_t dev_id, a_uint32_t vsi_id, fal_vsi_newaddr_lrn_t *newaddr_lrn) -{ - adpt_api_t *p_api; - sw_error_t rv = SW_OK; - - SW_RTN_ON_NULL(p_api = adpt_api_ptr_get(dev_id)); - - if (NULL == p_api->adpt_vsi_newaddr_lrn_get) - return SW_NOT_SUPPORTED; - - rv = p_api->adpt_vsi_newaddr_lrn_get(dev_id, vsi_id, newaddr_lrn); - return rv; -} -#endif -sw_error_t -_fal_vsi_newaddr_lrn_set(a_uint32_t dev_id, a_uint32_t vsi_id, fal_vsi_newaddr_lrn_t *newaddr_lrn) -{ - adpt_api_t *p_api; - sw_error_t rv = SW_OK; - - SW_RTN_ON_NULL(p_api = adpt_api_ptr_get(dev_id)); - - if (NULL == p_api->adpt_vsi_newaddr_lrn_set) - return SW_NOT_SUPPORTED; - - rv = p_api->adpt_vsi_newaddr_lrn_set(dev_id, vsi_id, newaddr_lrn); - return rv; -} -sw_error_t -_fal_vsi_member_set(a_uint32_t dev_id, a_uint32_t vsi_id, fal_vsi_member_t *vsi_member) -{ - adpt_api_t *p_api; - sw_error_t rv = SW_OK; - - SW_RTN_ON_NULL(p_api = adpt_api_ptr_get(dev_id)); - - if (NULL == p_api->adpt_vsi_member_set) - return SW_NOT_SUPPORTED; - - rv = p_api->adpt_vsi_member_set(dev_id, vsi_id, vsi_member); - return rv; -} -sw_error_t -_fal_vsi_member_get(a_uint32_t dev_id, a_uint32_t vsi_id, fal_vsi_member_t *vsi_member) -{ - adpt_api_t *p_api; - sw_error_t rv = SW_OK; - - SW_RTN_ON_NULL(p_api = adpt_api_ptr_get(dev_id)); - - if (NULL == p_api->adpt_vsi_member_get) - return SW_NOT_SUPPORTED; - - rv = p_api->adpt_vsi_member_get(dev_id, vsi_id, vsi_member); - return rv; -} - -#ifndef IN_VSI_MINI -sw_error_t -_fal_vsi_counter_get(a_uint32_t dev_id, a_uint32_t vsi_id, fal_vsi_counter_t *counter) -{ - adpt_api_t *p_api; - sw_error_t rv = SW_OK; - - SW_RTN_ON_NULL(p_api = adpt_api_ptr_get(dev_id)); - - if (NULL == p_api->adpt_vsi_counter_get) - return SW_NOT_SUPPORTED; - - rv = p_api->adpt_vsi_counter_get(dev_id, vsi_id, counter); - return rv; -} - -sw_error_t -_fal_vsi_counter_cleanup(a_uint32_t dev_id, a_uint32_t vsi_id) -{ - adpt_api_t *p_api; - sw_error_t rv = SW_OK; - - SW_RTN_ON_NULL(p_api = adpt_api_ptr_get(dev_id)); - - if (NULL == p_api->adpt_vsi_counter_cleanup) - return SW_NOT_SUPPORTED; - - rv = p_api->adpt_vsi_counter_cleanup(dev_id, vsi_id); - return rv; -} -#endif - -/*insert flag for inner fal, don't remove it*/ - -sw_error_t -fal_port_vlan_vsi_set(a_uint32_t dev_id, fal_port_t port_id, a_uint32_t stag_vid, a_uint32_t ctag_vid, a_uint32_t vsi_id) -{ - sw_error_t rv = SW_OK; - - FAL_API_LOCK; - rv = _fal_port_vlan_vsi_set(dev_id, port_id, stag_vid, ctag_vid, vsi_id); - FAL_API_UNLOCK; - return rv; -} -sw_error_t -fal_port_vlan_vsi_get(a_uint32_t dev_id, fal_port_t port_id, a_uint32_t stag_vid, a_uint32_t ctag_vid, a_uint32_t *vsi_id) -{ - sw_error_t rv = SW_OK; - - FAL_API_LOCK; - rv = _fal_port_vlan_vsi_get(dev_id, port_id, stag_vid, ctag_vid, vsi_id); - FAL_API_UNLOCK; - return rv; -} -sw_error_t -fal_port_vsi_set(a_uint32_t dev_id, fal_port_t port_id, a_uint32_t vsi_id) -{ - sw_error_t rv = SW_OK; - - FAL_API_LOCK; - rv = _fal_port_vsi_set(dev_id, port_id, vsi_id); - FAL_API_UNLOCK; - return rv; -} -#ifndef IN_VSI_MINI -sw_error_t -fal_port_vsi_get(a_uint32_t dev_id, fal_port_t port_id, a_uint32_t *vsi_id) -{ - sw_error_t rv = SW_OK; - - FAL_API_LOCK; - rv = _fal_port_vsi_get(dev_id, port_id, vsi_id); - FAL_API_UNLOCK; - return rv; -} -#endif - -sw_error_t -fal_vsi_stamove_set(a_uint32_t dev_id, a_uint32_t vsi_id, fal_vsi_stamove_t *stamove) -{ - sw_error_t rv = SW_OK; - - FAL_API_LOCK; - rv = _fal_vsi_stamove_set(dev_id, vsi_id, stamove); - FAL_API_UNLOCK; - return rv; -} -#ifndef IN_VSI_MINI -sw_error_t -fal_vsi_stamove_get(a_uint32_t dev_id, a_uint32_t vsi_id, fal_vsi_stamove_t *stamove) -{ - sw_error_t rv = SW_OK; - - FAL_API_LOCK; - rv = _fal_vsi_stamove_get(dev_id, vsi_id, stamove); - FAL_API_UNLOCK; - return rv; -} -sw_error_t -fal_vsi_newaddr_lrn_get(a_uint32_t dev_id, a_uint32_t vsi_id, fal_vsi_newaddr_lrn_t *newaddr_lrn) -{ - sw_error_t rv = SW_OK; - - FAL_API_LOCK; - rv = _fal_vsi_newaddr_lrn_get(dev_id, vsi_id, newaddr_lrn); - FAL_API_UNLOCK; - return rv; -} -#endif -sw_error_t -fal_vsi_newaddr_lrn_set(a_uint32_t dev_id, a_uint32_t vsi_id, fal_vsi_newaddr_lrn_t *newaddr_lrn) -{ - sw_error_t rv = SW_OK; - - FAL_API_LOCK; - rv = _fal_vsi_newaddr_lrn_set(dev_id, vsi_id, newaddr_lrn); - FAL_API_UNLOCK; - return rv; -} -sw_error_t -fal_vsi_member_set(a_uint32_t dev_id, a_uint32_t vsi_id, fal_vsi_member_t *vsi_member) -{ - sw_error_t rv = SW_OK; - - FAL_API_LOCK; - rv = _fal_vsi_member_set(dev_id, vsi_id, vsi_member); - FAL_API_UNLOCK; - return rv; -} - -sw_error_t -fal_vsi_member_get(a_uint32_t dev_id, a_uint32_t vsi_id, fal_vsi_member_t *vsi_member) -{ - sw_error_t rv = SW_OK; - - FAL_API_LOCK; - rv = _fal_vsi_member_get(dev_id, vsi_id, vsi_member); - FAL_API_UNLOCK; - return rv; -} - -#ifndef IN_VSI_MINI -sw_error_t -fal_vsi_counter_get(a_uint32_t dev_id, a_uint32_t vsi_id, fal_vsi_counter_t *counter) -{ - sw_error_t rv = SW_OK; - - FAL_API_LOCK; - rv = _fal_vsi_counter_get(dev_id, vsi_id, counter); - FAL_API_UNLOCK; - return rv; -} - -sw_error_t -fal_vsi_counter_cleanup(a_uint32_t dev_id, a_uint32_t vsi_id) -{ - sw_error_t rv = SW_OK; - - FAL_API_LOCK; - rv = _fal_vsi_counter_cleanup(dev_id, vsi_id); - FAL_API_UNLOCK; - return rv; -} -#endif -/*insert flag for outter fal, don't remove it*/ - -#ifndef IN_VSI_MINI -EXPORT_SYMBOL(fal_port_vsi_get); -EXPORT_SYMBOL(fal_vsi_stamove_get); -EXPORT_SYMBOL(fal_vsi_newaddr_lrn_get); -EXPORT_SYMBOL(fal_vsi_counter_get); -EXPORT_SYMBOL(fal_vsi_counter_cleanup); -#endif -EXPORT_SYMBOL(fal_port_vlan_vsi_set); -EXPORT_SYMBOL(fal_port_vlan_vsi_get); -EXPORT_SYMBOL(fal_port_vsi_set); -EXPORT_SYMBOL(fal_vsi_stamove_set); -EXPORT_SYMBOL(fal_vsi_newaddr_lrn_set); -EXPORT_SYMBOL(fal_vsi_member_set); -EXPORT_SYMBOL(fal_vsi_member_get); diff --git a/feeds/ipq807x/qca-ssdk/src/src/hsl/Makefile b/feeds/ipq807x/qca-ssdk/src/src/hsl/Makefile deleted file mode 100755 index 8fabf4c4d..000000000 --- a/feeds/ipq807x/qca-ssdk/src/src/hsl/Makefile +++ /dev/null @@ -1,39 +0,0 @@ -LOC_DIR=/src/hsl -LIB=HSL - -include $(PRJ_PATH)/make/config.mk - -SRC_LIST=hsl_dev.c hsl_port_prop.c hsl_api.c - -ifeq (TRUE, $(IN_ACL)) - ifeq (SHIVA, $(CHIP_TYPE)) - SRC_LIST += hsl_acl.c - endif - ifeq (GARUDA, $(CHIP_TYPE)) - SRC_LIST += hsl_acl.c - endif - ifeq (ALL_CHIP, $(CHIP_TYPE)) - SRC_LIST += hsl_acl.c - endif - ifeq (NONHK_CHIP, $(CHIP_TYPE)) - SRC_LIST += hsl_acl.c - endif -endif - -ifeq (linux, $(OS)) - ifeq (KSLIB, $(MODULE_TYPE)) - ifneq (TRUE, $(KERNEL_MODE)) - SRC_LIST=hsl_dev.c hsl_api.c - endif - endif -endif - -ifeq (TRUE, $(API_LOCK)) - SRC_LIST += hsl_lock.c -endif - -include $(PRJ_PATH)/make/components.mk -include $(PRJ_PATH)/make/defs.mk -include $(PRJ_PATH)/make/target.mk - -all: dep obj diff --git a/feeds/ipq807x/qca-ssdk/src/src/hsl/athena/Makefile b/feeds/ipq807x/qca-ssdk/src/src/hsl/athena/Makefile deleted file mode 100755 index 7cce5d220..000000000 --- a/feeds/ipq807x/qca-ssdk/src/src/hsl/athena/Makefile +++ /dev/null @@ -1,44 +0,0 @@ -LOC_DIR=src/hsl/athena -LIB=HSL - -include $(PRJ_PATH)/make/config.mk - -SRC_LIST=athena_reg_access.c athena_init.c - -ifeq (TRUE, $(IN_FDB)) - SRC_LIST += athena_fdb.c -endif - -ifeq (TRUE, $(IN_MIB)) - SRC_LIST += athena_mib.c -endif - -ifeq (TRUE, $(IN_PORTCONTROL)) - SRC_LIST += athena_port_ctrl.c -endif - -ifeq (TRUE, $(IN_PORTVLAN)) - SRC_LIST += athena_portvlan.c -endif - -ifeq (TRUE, $(IN_VLAN)) - SRC_LIST += athena_vlan.c -endif - -ifeq (linux, $(OS)) - ifeq (KSLIB, $(MODULE_TYPE)) - ifneq (TRUE, $(KERNEL_MODE)) - SRC_LIST=athena_reg_access.c athena_init.c - endif - endif -endif - -ifeq (, $(findstring ATHENA, $(SUPPORT_CHIP))) - SRC_LIST= -endif - -include $(PRJ_PATH)/make/components.mk -include $(PRJ_PATH)/make/defs.mk -include $(PRJ_PATH)/make/target.mk - -all: dep obj \ No newline at end of file diff --git a/feeds/ipq807x/qca-ssdk/src/src/hsl/athena/athena_fdb.c b/feeds/ipq807x/qca-ssdk/src/src/hsl/athena/athena_fdb.c deleted file mode 100755 index 5b0fc528e..000000000 --- a/feeds/ipq807x/qca-ssdk/src/src/hsl/athena/athena_fdb.c +++ /dev/null @@ -1,639 +0,0 @@ -/* - * Copyright (c) 2012, The Linux Foundation. All rights reserved. - * Permission to use, copy, modify, and/or distribute this software for - * any purpose with or without fee is hereby granted, provided that the - * above copyright notice and this permission notice appear in all copies. - * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES - * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR - * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES - * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN - * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT - * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. - */ - - -/** - * @defgroup athena_fdb ATHENA_FDB - * @{ - */ -#include "sw.h" -#include "hsl.h" -#include "hsl_dev.h" -#include "hsl_port_prop.h" -#include "athena_fdb.h" -#include "athena_reg.h" - -#define ARL_FLUSH_ALL 1 -#define ARL_LOAD_ENTRY 2 -#define ARL_PURGE_ENTRY 3 -#define ARL_FLUSH_ALL_UNLOCK 4 -#define ARL_FLUSH_PORT_UNICAST 5 -#define ARL_NEXT_ENTRY 6 - -#define ARL_FIRST_ENTRY 1001 - -static a_bool_t -athena_fdb_is_zeroaddr(fal_mac_addr_t addr) -{ - a_uint32_t i; - - for (i = 0; i < 6; i++) - { - if (addr.uc[i]) - { - return A_FALSE; - } - } - - return A_TRUE; -} - -static void -athena_fdb_fill_addr(fal_mac_addr_t addr, a_uint32_t * reg0, a_uint32_t * reg1) -{ - SW_SET_REG_BY_FIELD(ADDR_TABLE_FUNC1, AT_ADDR_BYTE0, addr.uc[0], *reg1); - SW_SET_REG_BY_FIELD(ADDR_TABLE_FUNC1, AT_ADDR_BYTE1, addr.uc[1], *reg1); - SW_SET_REG_BY_FIELD(ADDR_TABLE_FUNC1, AT_ADDR_BYTE2, addr.uc[2], *reg1); - SW_SET_REG_BY_FIELD(ADDR_TABLE_FUNC1, AT_ADDR_BYTE3, addr.uc[3], *reg1); - - SW_SET_REG_BY_FIELD(ADDR_TABLE_FUNC0, AT_ADDR_BYTE4, addr.uc[4], *reg0); - SW_SET_REG_BY_FIELD(ADDR_TABLE_FUNC0, AT_ADDR_BYTE5, addr.uc[5], *reg0); - - return; -} - -static sw_error_t -athena_atu_sw_to_hw(a_uint32_t dev_id, const fal_fdb_entry_t * entry, - a_uint32_t reg[]) -{ - a_uint32_t port; - - if (A_FALSE == entry->portmap_en) - { - if (A_TRUE != - hsl_port_prop_check(dev_id, entry->port.id, HSL_PP_INCL_CPU)) - { - return SW_BAD_PARAM; - } - - port = 0x1UL << entry->port.id; - } - else - { - if (A_FALSE == - hsl_mports_prop_check(dev_id, entry->port.map, HSL_PP_INCL_CPU)) - { - return SW_BAD_PARAM; - } - - port = entry->port.map; - } - - if (FAL_MAC_CPY_TO_CPU == entry->dacmd) - { - SW_SET_REG_BY_FIELD(ADDR_TABLE_FUNC2, COPY_TO_CPU, 1, reg[2]); - } - else if (FAL_MAC_RDT_TO_CPU == entry->dacmd) - { - SW_SET_REG_BY_FIELD(ADDR_TABLE_FUNC2, REDRCT_TO_CPU, 1, reg[2]); - } - else if (FAL_MAC_FRWRD != entry->dacmd) - { - return SW_NOT_SUPPORTED; - } - - if (FAL_MAC_DROP == entry->sacmd) - { - SW_SET_REG_BY_FIELD(ADDR_TABLE_FUNC2, SA_DROP_EN, 1, reg[2]); - } - else if (FAL_MAC_FRWRD != entry->sacmd) - { - return SW_NOT_SUPPORTED; - } - - if (A_TRUE == entry->leaky_en) - { - return SW_NOT_SUPPORTED; - } - - if (A_TRUE == entry->static_en) - { - SW_SET_REG_BY_FIELD(ADDR_TABLE_FUNC2, AT_STATUS, 1, reg[2]); - } - else - { - SW_SET_REG_BY_FIELD(ADDR_TABLE_FUNC2, AT_STATUS, 2, reg[2]); - } - - if (A_TRUE == entry->mirror_en) - { - SW_SET_REG_BY_FIELD(ADDR_TABLE_FUNC2, MIRROR_EN, 1, reg[2]); - } - - if (A_TRUE == entry->da_pri_en) - { - hsl_dev_t *p_dev; - - SW_SET_REG_BY_FIELD(ADDR_TABLE_FUNC2, AT_PRI_EN, 1, reg[2]); - - SW_RTN_ON_NULL(p_dev = hsl_dev_ptr_get(dev_id)); - - if (entry->da_queue > (p_dev->nr_queue - 1)) - return SW_BAD_PARAM; - - SW_SET_REG_BY_FIELD(ADDR_TABLE_FUNC2, AT_PRI, entry->da_queue, reg[2]); - } - - if (A_TRUE == entry->cross_pt_state) - { - return SW_NOT_SUPPORTED; - } - - SW_SET_REG_BY_FIELD(ADDR_TABLE_FUNC2, DES_PORT, port, reg[2]); - athena_fdb_fill_addr(entry->addr, ®[0], ®[1]); - - return SW_OK; -} - -static void -athena_atu_hw_to_sw(const a_uint32_t reg[], fal_fdb_entry_t * entry) -{ - a_uint32_t i, data; - - aos_mem_zero(entry, sizeof (fal_fdb_entry_t)); - - entry->dacmd = FAL_MAC_FRWRD; - SW_GET_FIELD_BY_REG(ADDR_TABLE_FUNC2, COPY_TO_CPU, data, reg[2]); - if (1 == data) - { - entry->dacmd = FAL_MAC_CPY_TO_CPU; - } - - SW_GET_FIELD_BY_REG(ADDR_TABLE_FUNC2, REDRCT_TO_CPU, data, reg[2]); - if (1 == data) - { - entry->dacmd = FAL_MAC_RDT_TO_CPU; - } - - entry->sacmd = FAL_MAC_FRWRD; - SW_GET_FIELD_BY_REG(ADDR_TABLE_FUNC2, SA_DROP_EN, data, reg[2]); - if (1 == data) - { - entry->sacmd = FAL_MAC_DROP; - } - - entry->static_en = A_FALSE; - SW_GET_FIELD_BY_REG(ADDR_TABLE_FUNC2, AT_STATUS, data, reg[2]); - if (1 == data) - { - entry->static_en = A_TRUE; - } - - entry->mirror_en = A_FALSE; - SW_GET_FIELD_BY_REG(ADDR_TABLE_FUNC2, MIRROR_EN, data, reg[2]); - if (1 == data) - { - entry->mirror_en = A_TRUE; - } - - entry->da_pri_en = A_FALSE; - SW_GET_FIELD_BY_REG(ADDR_TABLE_FUNC2, AT_PRI_EN, data, reg[2]); - if (1 == data) - { - SW_GET_FIELD_BY_REG(ADDR_TABLE_FUNC2, AT_PRI, data, reg[2]); - entry->da_pri_en = A_TRUE; - entry->da_queue = data & 0x3; - } - - entry->cross_pt_state = A_FALSE; - - SW_GET_FIELD_BY_REG(ADDR_TABLE_FUNC2, DES_PORT, data, reg[2]); - - entry->portmap_en = A_TRUE; - entry->port.map = data; - - for (i = 0; i < 4; i++) - { - entry->addr.uc[i] = (reg[1] >> ((3 - i) << 3)) & 0xff; - } - - for (i = 4; i < 6; i++) - { - entry->addr.uc[i] = (reg[0] >> ((7 - i) << 3)) & 0xff; - } - - return; -} - -static sw_error_t -athena_fdb_commit(a_uint32_t dev_id, a_uint32_t op) -{ - sw_error_t rv; - a_uint32_t busy = 1; - a_uint32_t full_vio; - a_uint32_t i = 1000; - a_uint32_t entry; - - while (busy && --i) - { - HSL_REG_FIELD_GET(rv, dev_id, ADDR_TABLE_FUNC0, 0, AT_BUSY, - (a_uint8_t *) (&busy), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - aos_udelay(5); - } - - if (0 == i) - { - return SW_BUSY; - } - - HSL_REG_ENTRY_GET(rv, dev_id, ADDR_TABLE_FUNC0, 0, - (a_uint8_t *) (&entry), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - - SW_SET_REG_BY_FIELD(ADDR_TABLE_FUNC0, AT_BUSY, 1, entry); - SW_SET_REG_BY_FIELD(ADDR_TABLE_FUNC0, AT_FUNC, op, entry); - - HSL_REG_ENTRY_SET(rv, dev_id, ADDR_TABLE_FUNC0, 0, - (a_uint8_t *) (&entry), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - - busy = 1; - i = 1000; - while (busy && --i) - { - HSL_REG_FIELD_GET(rv, dev_id, ADDR_TABLE_FUNC0, 0, AT_BUSY, - (a_uint8_t *) (&busy), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - aos_udelay(5); - } - - if (0 == i) - { - return SW_FAIL; - } - - HSL_REG_FIELD_GET(rv, dev_id, ADDR_TABLE_FUNC0, 0, AT_FULL_VIO, - (a_uint8_t *) (&full_vio), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - - if (full_vio) - { - if (ARL_LOAD_ENTRY == op) - { - return SW_FULL; - } - else if ((ARL_PURGE_ENTRY == op) - || (ARL_FLUSH_PORT_UNICAST == op)) - { - return SW_NOT_FOUND; - } - else - { - return SW_FAIL; - } - } - - return SW_OK; -} - -static sw_error_t -athena_atu_get(a_uint32_t dev_id, fal_fdb_entry_t * entry, a_uint32_t op) -{ - sw_error_t rv; - a_uint32_t reg[3] = { 0 }; - a_uint32_t destport = 0; - a_uint32_t hwop = op; - - if (ARL_NEXT_ENTRY == op) - { - athena_fdb_fill_addr(entry->addr, ®[0], ®[1]); - } - - HSL_REG_ENTRY_SET(rv, dev_id, ADDR_TABLE_FUNC0, 0, - (a_uint8_t *) (®[0]), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - - HSL_REG_ENTRY_SET(rv, dev_id, ADDR_TABLE_FUNC1, 0, - (a_uint8_t *) (®[1]), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - - /* set destport not zero */ - if (ARL_NEXT_ENTRY == op) - { - reg[2] = 0xf; - } - - if (ARL_FIRST_ENTRY == op) - { - hwop = ARL_NEXT_ENTRY; - } - - HSL_REG_ENTRY_SET(rv, dev_id, ADDR_TABLE_FUNC2, 0, - (a_uint8_t *) (®[2]), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - - rv = athena_fdb_commit(dev_id, hwop); - SW_RTN_ON_ERROR(rv); - - /* get hardware enrety */ - HSL_REG_ENTRY_GET(rv, dev_id, ADDR_TABLE_FUNC0, 0, - (a_uint8_t *) (®[0]), sizeof (a_uint32_t)); - - SW_RTN_ON_ERROR(rv); - - HSL_REG_ENTRY_GET(rv, dev_id, ADDR_TABLE_FUNC1, 0, - (a_uint8_t *) (®[1]), sizeof (a_uint32_t)); - - SW_RTN_ON_ERROR(rv); - - HSL_REG_ENTRY_GET(rv, dev_id, ADDR_TABLE_FUNC2, 0, - (a_uint8_t *) (®[2]), sizeof (a_uint32_t)); - - SW_RTN_ON_ERROR(rv); - - SW_GET_FIELD_BY_REG(ADDR_TABLE_FUNC2, DES_PORT, destport, reg[2]); - - athena_atu_hw_to_sw(reg, entry); - - /* If hardware return back with address and status all zero, - that means no other next valid entry in fdb table */ - if ((A_TRUE == athena_fdb_is_zeroaddr(entry->addr)) - && (0 == destport) - && (ARL_NEXT_ENTRY == hwop)) - { - return SW_NO_MORE; - } - else - { - return SW_OK; - } -} - -static sw_error_t -_athena_fdb_add(a_uint32_t dev_id, const fal_fdb_entry_t * entry) -{ - sw_error_t rv; - a_uint32_t reg[3] = { 0, 0, 0 }; - - HSL_DEV_ID_CHECK(dev_id); - - if ((A_TRUE == athena_fdb_is_zeroaddr(entry->addr)) - && (0 == entry->port.map) - && (0 == entry->port.id)) - { - return SW_BAD_PARAM; - } - - rv = athena_atu_sw_to_hw(dev_id, entry, reg); - SW_RTN_ON_ERROR(rv); - - HSL_REG_ENTRY_SET(rv, dev_id, ADDR_TABLE_FUNC2, 0, - (a_uint8_t *) (®[2]), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - - HSL_REG_ENTRY_SET(rv, dev_id, ADDR_TABLE_FUNC1, 0, (a_uint8_t *) (®[1]), - sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - - HSL_REG_ENTRY_SET(rv, dev_id, ADDR_TABLE_FUNC0, 0, (a_uint8_t *) (®[0]), - sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - - rv = athena_fdb_commit(dev_id, ARL_LOAD_ENTRY); - return rv; -} - -static sw_error_t -_athena_fdb_del_all(a_uint32_t dev_id, a_uint32_t flag) -{ - sw_error_t rv; - - HSL_DEV_ID_CHECK(dev_id); - - if (FAL_FDB_DEL_STATIC & flag) - { - rv = athena_fdb_commit(dev_id, ARL_FLUSH_ALL); - } - else - { - rv = athena_fdb_commit(dev_id, ARL_FLUSH_ALL_UNLOCK); - } - - return rv; -} - -static sw_error_t -_athena_fdb_del_by_port(a_uint32_t dev_id, fal_port_t port_id, a_uint32_t flag) -{ - sw_error_t rv; - a_uint32_t reg = 0; - - HSL_DEV_ID_CHECK(dev_id); - - if (A_FALSE == hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU)) - { - return SW_BAD_PARAM; - } - - SW_SET_REG_BY_FIELD(ADDR_TABLE_FUNC0, AT_PORT_NUM, port_id, reg); - - HSL_REG_ENTRY_SET(rv, dev_id, ADDR_TABLE_FUNC0, 0, (a_uint8_t *) (®), - sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - - if (FAL_FDB_DEL_STATIC & flag) - { - rv = athena_fdb_commit(dev_id, ARL_FLUSH_PORT_UNICAST); - } - else - { - return SW_NOT_SUPPORTED; - } - - return rv; -} - -static sw_error_t -_athena_fdb_del_by_mac(a_uint32_t dev_id, const fal_fdb_entry_t * entry) -{ - sw_error_t rv; - a_uint32_t reg0 = 0, reg1 = 0; - - HSL_DEV_ID_CHECK(dev_id); - - athena_fdb_fill_addr(entry->addr, ®0, ®1); - - HSL_REG_ENTRY_SET(rv, dev_id, ADDR_TABLE_FUNC1, 0, (a_uint8_t *) (®1), - sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - - HSL_REG_ENTRY_SET(rv, dev_id, ADDR_TABLE_FUNC0, 0, (a_uint8_t *) (®0), - sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - - rv = athena_fdb_commit(dev_id, ARL_PURGE_ENTRY); - return rv; -} - -static sw_error_t -_athena_fdb_first(a_uint32_t dev_id, fal_fdb_entry_t * entry) -{ - sw_error_t rv; - - HSL_DEV_ID_CHECK(dev_id); - - rv = athena_atu_get(dev_id, entry, ARL_FIRST_ENTRY); - return rv; -} - -static sw_error_t -_athena_fdb_next(a_uint32_t dev_id, fal_fdb_entry_t * entry) -{ - sw_error_t rv; - - HSL_DEV_ID_CHECK(dev_id); - - rv = athena_atu_get(dev_id, entry, ARL_NEXT_ENTRY); - return rv; -} - -/** - * @brief Add a Fdb entry - * @param[in] dev_id device id - * @param[in] entry fdb entry - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -athena_fdb_add(a_uint32_t dev_id, const fal_fdb_entry_t * entry) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _athena_fdb_add(dev_id, entry); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Delete all Fdb entries - * @details Comments: - * If set FAL_FDB_DEL_STATIC bit in flag which means delete all fdb - * entries otherwise only delete dynamic entries. - * @param[in] dev_id device id - * @param[in] flag delete operation option - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -athena_fdb_del_all(a_uint32_t dev_id, a_uint32_t flag) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _athena_fdb_del_all(dev_id, flag); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Delete Fdb entries on a particular port - * @details Comments: - * Athena doesn't support flag option, flag should be setted as zero. - * @param[in] dev_id device id - * @param[in] port_id port id - * @param[in] flag delete operation option - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -athena_fdb_del_by_port(a_uint32_t dev_id, fal_port_t port_id, a_uint32_t flag) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _athena_fdb_del_by_port(dev_id, port_id, flag); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Delete a particular Fdb entry through mac address - * @details Comments: - * Only addr field in entry is meaning. For IVL learning vid or fid field - * also is meaning. - * @param[in] dev_id device id - * @param[in] entry fdb entry - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -athena_fdb_del_by_mac(a_uint32_t dev_id, const fal_fdb_entry_t * entry) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _athena_fdb_del_by_mac(dev_id, entry); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Get first Fdb entry from particular device - * @param[in] dev_id device id - * @param[out] entry fdb entry - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -athena_fdb_first(a_uint32_t dev_id, fal_fdb_entry_t * entry) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _athena_fdb_first(dev_id, entry); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Get next Fdb entry from particular device - * @details Comments: - * For input parameter only addr field in entry is meaning. - * @param[in] dev_id device id - * @param entry fdb entry - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -athena_fdb_next(a_uint32_t dev_id, fal_fdb_entry_t * entry) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _athena_fdb_next(dev_id, entry); - HSL_API_UNLOCK; - return rv; -} - -sw_error_t -athena_fdb_init(a_uint32_t dev_id) -{ - HSL_DEV_ID_CHECK(dev_id); - -#ifndef HSL_STANDALONG - hsl_api_t *p_api; - - SW_RTN_ON_NULL (p_api = hsl_api_ptr_get(dev_id)); - - p_api->fdb_add = athena_fdb_add; - p_api->fdb_del_all = athena_fdb_del_all; - p_api->fdb_del_by_port = athena_fdb_del_by_port; - p_api->fdb_del_by_mac = athena_fdb_del_by_mac; - p_api->fdb_first = athena_fdb_first; - p_api->fdb_next = athena_fdb_next; -#endif - - return SW_OK; -} - -/** - * @} - */ - diff --git a/feeds/ipq807x/qca-ssdk/src/src/hsl/athena/athena_init.c b/feeds/ipq807x/qca-ssdk/src/src/hsl/athena/athena_init.c deleted file mode 100755 index 9e7c84d08..000000000 --- a/feeds/ipq807x/qca-ssdk/src/src/hsl/athena/athena_init.c +++ /dev/null @@ -1,290 +0,0 @@ -/* - * Copyright (c) 2012, 2017, The Linux Foundation. All rights reserved. - * Permission to use, copy, modify, and/or distribute this software for - * any purpose with or without fee is hereby granted, provided that the - * above copyright notice and this permission notice appear in all copies. - * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES - * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR - * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES - * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN - * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT - * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. - */ - - -/** - * @defgroup athena_init ATHENA_INIT - * @{ - */ -#include "sw.h" -#include "hsl.h" -#include "hsl_dev.h" -#include "hsl_port_prop.h" -#include "athena_mib.h" -#include "athena_port_ctrl.h" -#include "athena_portvlan.h" -#include "athena_vlan.h" -#include "athena_fdb.h" -#include "athena_reg_access.h" -#include "athena_reg.h" -#include "athena_init.h" - -static ssdk_init_cfg * athena_cfg[SW_MAX_NR_DEV] = { 0 }; - -#if !(defined(KERNEL_MODULE) && defined(USER_MODE)) -static sw_error_t -athena_portproperty_init(a_uint32_t dev_id, hsl_init_mode mode) -{ - hsl_port_prop_t p_type; - hsl_dev_t *pdev = NULL; - fal_port_t port_id; - - pdev = hsl_dev_ptr_get(dev_id); - if (pdev == NULL) - return SW_NOT_INITIALIZED; - - for (port_id = 0; port_id < pdev->nr_ports; port_id++) - { - hsl_port_prop_portmap_set(dev_id, port_id); - - for (p_type = HSL_PP_PHY; p_type < HSL_PP_BUTT; p_type++) - { - if (HSL_NO_CPU == mode) - { - SW_RTN_ON_ERROR(hsl_port_prop_set(dev_id, port_id, p_type)); - continue; - } - - switch (p_type) - { - case HSL_PP_PHY: - if (HSL_CPU_1_PLUS == mode) - { - if ((port_id != pdev->cpu_port_nr) - && (port_id != (pdev->nr_ports -1))) - { - SW_RTN_ON_ERROR(hsl_port_prop_set(dev_id, port_id, p_type)); - } - } - else - { - if (port_id != pdev->cpu_port_nr) - { - SW_RTN_ON_ERROR(hsl_port_prop_set(dev_id, port_id, p_type)); - } - } - break; - - case HSL_PP_INCL_CPU: - /* include cpu port but exclude wan port in some cases */ - if (!((HSL_CPU_2 == mode) && (port_id == (pdev->nr_ports - 1)))) - SW_RTN_ON_ERROR(hsl_port_prop_set(dev_id, port_id, p_type)); - - break; - - case HSL_PP_EXCL_CPU: - /* exclude cpu port and wan port in some cases */ - if ((port_id != pdev->cpu_port_nr) - && (!((HSL_CPU_2 == mode) && (port_id == (pdev->nr_ports - 1))))) - SW_RTN_ON_ERROR(hsl_port_prop_set(dev_id, port_id, p_type)); - break; - - default: - break; - } - } - - if (HSL_NO_CPU == mode) - { - SW_RTN_ON_ERROR(hsl_port_prop_set_phyid - (dev_id, port_id, port_id + 1)); - } - else - { - if (port_id != pdev->cpu_port_nr) - { - SW_RTN_ON_ERROR(hsl_port_prop_set_phyid - (dev_id, port_id, port_id - 1)); - } - } - } - - return SW_OK; -} - -static sw_error_t -athena_hw_init(a_uint32_t dev_id) -{ - hsl_dev_t *pdev = NULL; - a_uint32_t port_id, data; - sw_error_t rv; - - pdev = hsl_dev_ptr_get(dev_id); - if (NULL == pdev) - { - return SW_NOT_INITIALIZED; - } - - for (port_id = 0; port_id < pdev->nr_ports; port_id++) - { - if (port_id == pdev->cpu_port_nr) - { - continue; - } - - HSL_REG_ENTRY_GET(rv, dev_id, PORT_STATUS, port_id, - (a_uint8_t *) (&data), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - - SW_SET_REG_BY_FIELD(PORT_STATUS, LINK_EN, 1, data); - - HSL_REG_ENTRY_SET(rv, dev_id, PORT_STATUS, port_id, - (a_uint8_t *) (&data), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - } - - return SW_OK; -} - - -#endif - -static sw_error_t -athena_dev_init(a_uint32_t dev_id) -{ - hsl_dev_t *pdev = NULL; - - pdev = hsl_dev_ptr_get(dev_id); - if (pdev == NULL) - return SW_NOT_INITIALIZED; - - pdev->nr_ports = 6; - pdev->nr_phy = 5; - pdev->cpu_port_nr = 0; - pdev->nr_vlans = 16; - pdev->hw_vlan_query = A_FALSE; - pdev->nr_queue = 4; - - return SW_OK; -} - -static sw_error_t -_athena_reset(a_uint32_t dev_id) -{ -#if !(defined(KERNEL_MODULE) && defined(USER_MODE)) - a_uint32_t val; - sw_error_t rv; - - val = 0x1; - HSL_REG_FIELD_SET(rv, dev_id, MASK_CTL, 0, SOFT_RST, - (a_uint8_t *) (&val), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - - ATHENA_VLAN_RESET(rv, dev_id); - - rv = athena_hw_init(dev_id); - SW_RTN_ON_ERROR(rv); -#endif - - return SW_OK; -} - -sw_error_t -athena_cleanup(a_uint32_t dev_id) -{ - if (athena_cfg[dev_id]) - { - aos_mem_free(athena_cfg[dev_id]); - athena_cfg[dev_id] = NULL; - } - -#if !(defined(KERNEL_MODULE) && defined(USER_MODE)) - { - sw_error_t rv; - ATHENA_VLAN_CLEANUP(rv, dev_id); - } -#endif - - return SW_OK; -} - -/** - * @brief Reset Athena module. - * @details Comments: - * This operation will reset athena. - * @param[in] dev_id device id - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -athena_reset(a_uint32_t dev_id) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _athena_reset(dev_id); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Init Athena module. - * @details Comments: - * This operation will init athena. - * @param[in] dev_id device id - * @param[in] cfg configuration for initialization - * @return SW_OK or error code - */ -sw_error_t -athena_init(a_uint32_t dev_id, ssdk_init_cfg * cfg) -{ - HSL_DEV_ID_CHECK(dev_id); - - if (NULL == athena_cfg[dev_id]) - { - athena_cfg[dev_id] = (ssdk_init_cfg *)aos_mem_alloc(sizeof (ssdk_init_cfg)); - } - - if (NULL == athena_cfg[dev_id]) - { - return SW_OUT_OF_MEM; - } - - aos_mem_copy(athena_cfg[dev_id], cfg, sizeof (ssdk_init_cfg)); - - SW_RTN_ON_ERROR(athena_reg_access_init(dev_id, cfg->reg_mode)); - - SW_RTN_ON_ERROR(athena_dev_init(dev_id)); - -#if !(defined(KERNEL_MODULE) && defined(USER_MODE)) - { - sw_error_t rv; - SW_RTN_ON_ERROR(hsl_port_prop_init(dev_id)); - SW_RTN_ON_ERROR(hsl_port_prop_init_by_dev(dev_id)); - SW_RTN_ON_ERROR(athena_portproperty_init(dev_id, cfg->cpu_mode)); - - ATHENA_MIB_INIT(rv, dev_id); - ATHENA_PORT_CTRL_INIT(rv, dev_id); - ATHENA_PORTVLAN_INIT(rv, dev_id); - ATHENA_VLAN_INIT(rv, dev_id); - ATHENA_FDB_INIT(rv, dev_id); - - { - hsl_api_t *p_api; - - SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id)); - p_api->dev_reset = athena_reset; - p_api->dev_clean = athena_cleanup; - } - - SW_RTN_ON_ERROR(athena_hw_init(dev_id)); - } -#endif - - return SW_OK; -} - -/** - * @} - */ - diff --git a/feeds/ipq807x/qca-ssdk/src/src/hsl/athena/athena_mib.c b/feeds/ipq807x/qca-ssdk/src/src/hsl/athena/athena_mib.c deleted file mode 100755 index c71cbc3e2..000000000 --- a/feeds/ipq807x/qca-ssdk/src/src/hsl/athena/athena_mib.c +++ /dev/null @@ -1,406 +0,0 @@ -/* - * Copyright (c) 2012, The Linux Foundation. All rights reserved. - * Permission to use, copy, modify, and/or distribute this software for - * any purpose with or without fee is hereby granted, provided that the - * above copyright notice and this permission notice appear in all copies. - * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES - * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR - * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES - * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN - * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT - * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. - */ - - -/** - * @defgroup athena_mib ATHENA_MIB - * @{ - */ -#include "sw.h" -#include "hsl.h" -#include "hsl_dev.h" -#include "hsl_port_prop.h" -#include "athena_mib.h" -#include "athena_reg.h" - -static sw_error_t -_athena_get_mib_info(a_uint32_t dev_id, fal_port_t port_id, - fal_mib_info_t * mib_info) -{ - a_uint32_t val0 = 0, val1 = 0; - sw_error_t rv; - - HSL_DEV_ID_CHECK(dev_id); - - if (A_FALSE == hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU)) - { - return SW_OUT_OF_RANGE; - } - - HSL_REG_ENTRY_GET(rv, dev_id, MIB_RXBROAD, port_id, - (a_uint8_t *) (&val0), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - HSL_REG_ENTRY_GET(rv, dev_id, MIB_RXBROAD_2, port_id, - (a_uint8_t *) (&val1), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - mib_info->RxBroad = val0 + val1; - - HSL_REG_ENTRY_GET(rv, dev_id, MIB_RXPAUSE, port_id, - (a_uint8_t *) (&val0), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - HSL_REG_ENTRY_GET(rv, dev_id, MIB_RXPAUSE_2, port_id, - (a_uint8_t *) (&val1), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - mib_info->RxPause = val0 + val1; - - HSL_REG_ENTRY_GET(rv, dev_id, MIB_RXMULTI, port_id, - (a_uint8_t *) (&val0), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - HSL_REG_ENTRY_GET(rv, dev_id, MIB_RXMULTI_2, port_id, - (a_uint8_t *) (&val1), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - mib_info->RxMulti = val0 + val1; - - HSL_REG_ENTRY_GET(rv, dev_id, MIB_RXFCSERR, port_id, - (a_uint8_t *) (&val0), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - HSL_REG_ENTRY_GET(rv, dev_id, MIB_RXFCSERR_2, port_id, - (a_uint8_t *) (&val1), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - mib_info->RxFcsErr = val0 + val1; - - HSL_REG_ENTRY_GET(rv, dev_id, MIB_RXALLIGNERR, port_id, - (a_uint8_t *) (&val0), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - HSL_REG_ENTRY_GET(rv, dev_id, MIB_RXALLIGNERR_2, port_id, - (a_uint8_t *) (&val1), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - mib_info->RxAllignErr = val0 + val1; - - HSL_REG_ENTRY_GET(rv, dev_id, MIB_RXRUNT, port_id, (a_uint8_t *) (&val0), - sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - HSL_REG_ENTRY_GET(rv, dev_id, MIB_RXRUNT_2, port_id, - (a_uint8_t *) (&val1), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - mib_info->RxRunt = val0 + val1; - - HSL_REG_ENTRY_GET(rv, dev_id, MIB_RXFRAGMENT, port_id, - (a_uint8_t *) (&val0), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - HSL_REG_ENTRY_GET(rv, dev_id, MIB_RXFRAGMENT_2, port_id, - (a_uint8_t *) (&val1), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - mib_info->RxFragment = val0 + val1; - - HSL_REG_ENTRY_GET(rv, dev_id, MIB_RX64BYTE, port_id, - (a_uint8_t *) (&val0), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - HSL_REG_ENTRY_GET(rv, dev_id, MIB_RX64BYTE_2, port_id, - (a_uint8_t *) (&val1), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - mib_info->Rx64Byte = val0 + val1; - - HSL_REG_ENTRY_GET(rv, dev_id, MIB_RX128BYTE, port_id, - (a_uint8_t *) (&val0), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - HSL_REG_ENTRY_GET(rv, dev_id, MIB_RX128BYTE_2, port_id, - (a_uint8_t *) (&val1), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - mib_info->Rx128Byte = val0 + val1; - - HSL_REG_ENTRY_GET(rv, dev_id, MIB_RX256BYTE, port_id, - (a_uint8_t *) (&val0), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - HSL_REG_ENTRY_GET(rv, dev_id, MIB_RX256BYTE_2, port_id, - (a_uint8_t *) (&val1), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - mib_info->Rx256Byte = val0 + val1; - - HSL_REG_ENTRY_GET(rv, dev_id, MIB_RX512BYTE, port_id, - (a_uint8_t *) (&val0), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - HSL_REG_ENTRY_GET(rv, dev_id, MIB_RX512BYTE_2, port_id, - (a_uint8_t *) (&val1), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - mib_info->Rx512Byte = val0 + val1; - - HSL_REG_ENTRY_GET(rv, dev_id, MIB_RX1024BYTE, port_id, - (a_uint8_t *) (&val0), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - HSL_REG_ENTRY_GET(rv, dev_id, MIB_RX1024BYTE_2, port_id, - (a_uint8_t *) (&val1), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - mib_info->Rx1024Byte = val0 + val1; - - mib_info->Rx1518Byte = 0; //reserved for s16 - - HSL_REG_ENTRY_GET(rv, dev_id, MIB_RXMAXBYTE, port_id, - (a_uint8_t *) (&val0), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - HSL_REG_ENTRY_GET(rv, dev_id, MIB_RXMAXBYTE_2, port_id, - (a_uint8_t *) (&val1), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - mib_info->RxMaxByte = val0 + val1; - - HSL_REG_ENTRY_GET(rv, dev_id, MIB_RXTOOLONG, port_id, - (a_uint8_t *) (&val0), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - HSL_REG_ENTRY_GET(rv, dev_id, MIB_RXTOOLONG_2, port_id, - (a_uint8_t *) (&val1), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - mib_info->RxTooLong = val0 + val1; - - HSL_REG_ENTRY_GET(rv, dev_id, MIB_RXGOODBYTE_LO, port_id, - (a_uint8_t *) (&val0), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - HSL_REG_ENTRY_GET(rv, dev_id, MIB_RXGOODBYTE_LO_2, port_id, - (a_uint8_t *) (&val1), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - mib_info->RxGoodByte_lo = val0 + val1; - - HSL_REG_ENTRY_GET(rv, dev_id, MIB_RXGOODBYTE_HI, port_id, - (a_uint8_t *) (&val0), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - HSL_REG_ENTRY_GET(rv, dev_id, MIB_RXGOODBYTE_HI_2, port_id, - (a_uint8_t *) (&val1), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - mib_info->RxGoodByte_hi = val0 + val1; - - HSL_REG_ENTRY_GET(rv, dev_id, MIB_RXBADBYTE_LO, port_id, - (a_uint8_t *) (&val0), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - HSL_REG_ENTRY_GET(rv, dev_id, MIB_RXBADBYTE_LO_2, port_id, - (a_uint8_t *) (&val1), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - mib_info->RxBadByte_lo = val0 + val1; - - HSL_REG_ENTRY_GET(rv, dev_id, MIB_RXBADBYTE_HI, port_id, - (a_uint8_t *) (&val0), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - HSL_REG_ENTRY_GET(rv, dev_id, MIB_RXBADBYTE_HI_2, port_id, - (a_uint8_t *) (&val1), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - mib_info->RxBadByte_hi = val0 + val1; - - HSL_REG_ENTRY_GET(rv, dev_id, MIB_RXOVERFLOW, port_id, - (a_uint8_t *) (&val0), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - HSL_REG_ENTRY_GET(rv, dev_id, MIB_RXOVERFLOW_2, port_id, - (a_uint8_t *) (&val1), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - mib_info->RxOverFlow = val0 + val1; - - HSL_REG_ENTRY_GET(rv, dev_id, MIB_FILTERED, port_id, - (a_uint8_t *) (&val0), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - HSL_REG_ENTRY_GET(rv, dev_id, MIB_FILTERED_2, port_id, - (a_uint8_t *) (&val1), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - mib_info->Filtered = val0 + val1; - - HSL_REG_ENTRY_GET(rv, dev_id, MIB_TXBROAD, port_id, (a_uint8_t *) (&val0), - sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - HSL_REG_ENTRY_GET(rv, dev_id, MIB_TXBROAD_2, port_id, - (a_uint8_t *) (&val1), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - mib_info->TxBroad = val0 + val1; - - HSL_REG_ENTRY_GET(rv, dev_id, MIB_TXPAUSE, port_id, (a_uint8_t *) (&val0), - sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - HSL_REG_ENTRY_GET(rv, dev_id, MIB_TXPAUSE_2, port_id, - (a_uint8_t *) (&val1), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - mib_info->TxPause = val0 + val1; - - HSL_REG_ENTRY_GET(rv, dev_id, MIB_TXMULTI, port_id, (a_uint8_t *) (&val0), - sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - HSL_REG_ENTRY_GET(rv, dev_id, MIB_TXMULTI_2, port_id, - (a_uint8_t *) (&val1), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - mib_info->TxMulti = val0 + val1; - - HSL_REG_ENTRY_GET(rv, dev_id, MIB_TXUNDERRUN, port_id, - (a_uint8_t *) (&val0), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - HSL_REG_ENTRY_GET(rv, dev_id, MIB_TXUNDERRUN_2, port_id, - (a_uint8_t *) (&val1), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - mib_info->TxUnderRun = val0 + val1; - - HSL_REG_ENTRY_GET(rv, dev_id, MIB_TX64BYTE, port_id, - (a_uint8_t *) (&val0), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - HSL_REG_ENTRY_GET(rv, dev_id, MIB_TX64BYTE_2, port_id, - (a_uint8_t *) (&val1), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - mib_info->Tx64Byte = val0 + val1; - - HSL_REG_ENTRY_GET(rv, dev_id, MIB_TX128BYTE, port_id, - (a_uint8_t *) (&val0), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - HSL_REG_ENTRY_GET(rv, dev_id, MIB_TX128BYTE_2, port_id, - (a_uint8_t *) (&val1), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - mib_info->Tx128Byte = val0 + val1; - - HSL_REG_ENTRY_GET(rv, dev_id, MIB_TX256BYTE, port_id, - (a_uint8_t *) (&val0), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - HSL_REG_ENTRY_GET(rv, dev_id, MIB_TX256BYTE_2, port_id, - (a_uint8_t *) (&val1), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - mib_info->Tx256Byte = val0 + val1; - - HSL_REG_ENTRY_GET(rv, dev_id, MIB_TX512BYTE, port_id, - (a_uint8_t *) (&val0), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - HSL_REG_ENTRY_GET(rv, dev_id, MIB_TX512BYTE_2, port_id, - (a_uint8_t *) (&val1), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - mib_info->Tx512Byte = val0 + val1; - - HSL_REG_ENTRY_GET(rv, dev_id, MIB_TX1024BYTE, port_id, - (a_uint8_t *) (&val0), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - HSL_REG_ENTRY_GET(rv, dev_id, MIB_TX1024BYTE_2, port_id, - (a_uint8_t *) (&val1), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - mib_info->Tx1024Byte = val0 + val1; - - mib_info->Tx1518Byte = 0; //reserved for s16 - - HSL_REG_ENTRY_GET(rv, dev_id, MIB_TXMAXBYTE, port_id, - (a_uint8_t *) (&val0), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - HSL_REG_ENTRY_GET(rv, dev_id, MIB_TXMAXBYTE_2, port_id, - (a_uint8_t *) (&val1), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - mib_info->TxMaxByte = val0 + val1; - - HSL_REG_ENTRY_GET(rv, dev_id, MIB_TXOVERSIZE, port_id, - (a_uint8_t *) (&val0), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - HSL_REG_ENTRY_GET(rv, dev_id, MIB_TXOVERSIZE_2, port_id, - (a_uint8_t *) (&val1), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - mib_info->TxOverSize = val0 + val1; - - HSL_REG_ENTRY_GET(rv, dev_id, MIB_TXBYTE_LO, port_id, - (a_uint8_t *) (&val0), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - HSL_REG_ENTRY_GET(rv, dev_id, MIB_TXBYTE_LO_2, port_id, - (a_uint8_t *) (&val1), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - mib_info->TxByte_lo = val0 + val1; - - HSL_REG_ENTRY_GET(rv, dev_id, MIB_TXBYTE_HI, port_id, - (a_uint8_t *) (&val0), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - HSL_REG_ENTRY_GET(rv, dev_id, MIB_TXBYTE_HI_2, port_id, - (a_uint8_t *) (&val1), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - mib_info->TxByte_hi = val0 + val1; - - HSL_REG_ENTRY_GET(rv, dev_id, MIB_TXCOLLISION, port_id, - (a_uint8_t *) (&val0), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - HSL_REG_ENTRY_GET(rv, dev_id, MIB_TXCOLLISION_2, port_id, - (a_uint8_t *) (&val1), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - mib_info->TxCollision = val0 + val1; - - HSL_REG_ENTRY_GET(rv, dev_id, MIB_TXABORTCOL, port_id, - (a_uint8_t *) (&val0), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - HSL_REG_ENTRY_GET(rv, dev_id, MIB_TXABORTCOL_2, port_id, - (a_uint8_t *) (&val1), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - mib_info->TxAbortCol = val0 + val1; - - HSL_REG_ENTRY_GET(rv, dev_id, MIB_TXMULTICOL, port_id, - (a_uint8_t *) (&val0), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - HSL_REG_ENTRY_GET(rv, dev_id, MIB_TXMULTICOL_2, port_id, - (a_uint8_t *) (&val1), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - mib_info->TxMultiCol = val0 + val1; - - HSL_REG_ENTRY_GET(rv, dev_id, MIB_TXSINGALCOL, port_id, - (a_uint8_t *) (&val0), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - HSL_REG_ENTRY_GET(rv, dev_id, MIB_TXSINGALCOL_2, port_id, - (a_uint8_t *) (&val1), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - mib_info->TxSingalCol = val0 + val1; - - HSL_REG_ENTRY_GET(rv, dev_id, MIB_TXEXCDEFER, port_id, - (a_uint8_t *) (&val0), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - HSL_REG_ENTRY_GET(rv, dev_id, MIB_TXEXCDEFER_2, port_id, - (a_uint8_t *) (&val1), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - mib_info->TxExcDefer = val0 + val1; - - HSL_REG_ENTRY_GET(rv, dev_id, MIB_TXDEFER, port_id, (a_uint8_t *) (&val0), - sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - HSL_REG_ENTRY_GET(rv, dev_id, MIB_TXDEFER_2, port_id, - (a_uint8_t *) (&val1), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - mib_info->TxDefer = val0 + val1; - - HSL_REG_ENTRY_GET(rv, dev_id, MIB_TXLATECOL, port_id, - (a_uint8_t *) (&val0), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - HSL_REG_ENTRY_GET(rv, dev_id, MIB_TXLATECOL_2, port_id, - (a_uint8_t *) (&val1), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - mib_info->TxLateCol = val0 + val1; - - return SW_OK; -} - -/** - * @brief Get mib infomation on a particular port. - * @param[in] dev_id device id - * @param[in] port_id port id - * @param[out] mib_info mib infomation - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -athena_get_mib_info(a_uint32_t dev_id, fal_port_t port_id, - fal_mib_info_t * mib_info) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _athena_get_mib_info(dev_id, port_id, mib_info); - HSL_API_UNLOCK; - return rv; -} - -sw_error_t -athena_mib_init(a_uint32_t dev_id) -{ - HSL_DEV_ID_CHECK(dev_id); - -#ifndef HSL_STANDALONG - hsl_api_t *p_api; - - SW_RTN_ON_NULL (p_api = hsl_api_ptr_get(dev_id)); - - p_api->get_mib_info = athena_get_mib_info; -#endif - - return SW_OK; -} - -/** - * @} - */ - diff --git a/feeds/ipq807x/qca-ssdk/src/src/hsl/athena/athena_port_ctrl.c b/feeds/ipq807x/qca-ssdk/src/src/hsl/athena/athena_port_ctrl.c deleted file mode 100755 index 136168486..000000000 --- a/feeds/ipq807x/qca-ssdk/src/src/hsl/athena/athena_port_ctrl.c +++ /dev/null @@ -1,811 +0,0 @@ -/* - * Copyright (c) 2012, 2015, The Linux Foundation. All rights reserved. - * Permission to use, copy, modify, and/or distribute this software for - * any purpose with or without fee is hereby granted, provided that the - * above copyright notice and this permission notice appear in all copies. - * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES - * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR - * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES - * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN - * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT - * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. - */ - - -/** - * @defgroup athena_port_ctrl ATHENA_PORT_CTRL - * @{ - */ -#include "sw.h" -#include "hsl.h" -#include "hsl_dev.h" -#include "hsl_port_prop.h" -#include "athena_port_ctrl.h" -#include "athena_reg.h" -#include "hsl_phy.h" - - - -static sw_error_t -_athena_port_duplex_set(a_uint32_t dev_id, fal_port_t port_id, - fal_port_duplex_t duplex) -{ - sw_error_t rv; - a_uint32_t phy_id = 0; - a_uint32_t reg_save = 0; - a_uint32_t reg_val = 0; - hsl_phy_ops_t *phy_drv; - - HSL_DEV_ID_CHECK(dev_id); - - if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_PHY)) - { - return SW_BAD_PARAM; - } - - SW_RTN_ON_NULL (phy_drv = hsl_phy_api_ops_get (dev_id)); - if (NULL == phy_drv->phy_duplex_set) - return SW_NOT_SUPPORTED; - - - if (FAL_DUPLEX_BUTT <= duplex) - { - return SW_BAD_PARAM; - } - - rv = hsl_port_prop_get_phyid(dev_id, port_id, &phy_id); - SW_RTN_ON_ERROR(rv); - - //save reg value - HSL_REG_ENTRY_GET(rv, dev_id, PORT_STATUS, port_id, - (a_uint8_t *) (®_val), sizeof (a_uint32_t)); - reg_save = reg_val; - - SW_SET_REG_BY_FIELD(PORT_STATUS, LINK_EN, 0, reg_val); - SW_SET_REG_BY_FIELD(PORT_STATUS, RXMAC_EN, 0, reg_val); - SW_SET_REG_BY_FIELD(PORT_STATUS, TXMAC_EN, 0, reg_val); - - //set mac be config by sw and turn off RX TX MAC_EN - HSL_REG_ENTRY_SET(rv, dev_id, PORT_STATUS, port_id, - (a_uint8_t *) (®_val), sizeof (a_uint32_t)); - - rv = phy_drv->phy_duplex_set(dev_id, phy_id, duplex); - - //retore reg value - HSL_REG_ENTRY_SET(rv, dev_id, PORT_STATUS, port_id, - (a_uint8_t *) (®_save), sizeof (a_uint32_t)); - - return rv; -} - - -static sw_error_t -_athena_port_duplex_get(a_uint32_t dev_id, fal_port_t port_id, - fal_port_duplex_t * pduplex) -{ - sw_error_t rv; - a_uint32_t phy_id; - hsl_phy_ops_t *phy_drv; - - HSL_DEV_ID_CHECK(dev_id); - - if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_PHY)) - { - return SW_BAD_PARAM; - } - - SW_RTN_ON_NULL (phy_drv = hsl_phy_api_ops_get (dev_id)); - if (NULL == phy_drv->phy_duplex_get) - return SW_NOT_SUPPORTED; - - - rv = hsl_port_prop_get_phyid(dev_id, port_id, &phy_id); - SW_RTN_ON_ERROR(rv); - - rv = phy_drv->phy_duplex_get(dev_id, phy_id, pduplex); - return rv; -} - - -static sw_error_t -_athena_port_speed_set(a_uint32_t dev_id, fal_port_t port_id, - fal_port_speed_t speed) -{ - sw_error_t rv; - a_uint32_t phy_id = 0; - hsl_phy_ops_t *phy_drv; - - HSL_DEV_ID_CHECK(dev_id); - - if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_PHY)) - { - return SW_BAD_PARAM; - } - - SW_RTN_ON_NULL (phy_drv = hsl_phy_api_ops_get (dev_id)); - if (NULL == phy_drv->phy_speed_set) - return SW_NOT_SUPPORTED; - - - rv = hsl_port_prop_get_phyid(dev_id, port_id, &phy_id); - SW_RTN_ON_ERROR(rv); - - if (FAL_SPEED_100 < speed) - { - return SW_BAD_PARAM; - } - - rv = phy_drv->phy_speed_set(dev_id, phy_id, speed); - - return rv; -} - - -static sw_error_t -_athena_port_speed_get(a_uint32_t dev_id, fal_port_t port_id, - fal_port_speed_t * pspeed) -{ - sw_error_t rv; - a_uint32_t phy_id; - hsl_phy_ops_t *phy_drv; - - HSL_DEV_ID_CHECK(dev_id); - - if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_PHY)) - { - return SW_BAD_PARAM; - } - - SW_RTN_ON_NULL (phy_drv = hsl_phy_api_ops_get (dev_id)); - if (NULL == phy_drv->phy_speed_get) - return SW_NOT_SUPPORTED; - - - rv = hsl_port_prop_get_phyid(dev_id, port_id, &phy_id); - SW_RTN_ON_ERROR(rv); - - rv = phy_drv->phy_speed_get(dev_id, phy_id, pspeed); - - return rv; -} - - -static sw_error_t -_athena_port_autoneg_status_get(a_uint32_t dev_id, fal_port_t port_id, - a_bool_t * status) -{ - sw_error_t rv; - a_uint32_t phy_id; - hsl_phy_ops_t *phy_drv; - - HSL_DEV_ID_CHECK(dev_id); - - if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_PHY)) - { - return SW_BAD_PARAM; - } - - SW_RTN_ON_NULL (phy_drv = hsl_phy_api_ops_get (dev_id)); - if (NULL == phy_drv->phy_autoneg_status_get) - return SW_NOT_SUPPORTED; - - - rv = hsl_port_prop_get_phyid(dev_id, port_id, &phy_id); - SW_RTN_ON_ERROR(rv); - - *status = phy_drv->phy_autoneg_status_get(dev_id, phy_id); - - return SW_OK; -} - - -static sw_error_t -_athena_port_autoneg_enable(a_uint32_t dev_id, fal_port_t port_id) -{ - sw_error_t rv; - a_uint32_t phy_id; - hsl_phy_ops_t *phy_drv; - - HSL_DEV_ID_CHECK(dev_id); - - if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_PHY)) - { - return SW_BAD_PARAM; - } - - SW_RTN_ON_NULL (phy_drv = hsl_phy_api_ops_get (dev_id)); - if (NULL == phy_drv->phy_autoneg_enable_set) - return SW_NOT_SUPPORTED; - - - rv = hsl_port_prop_get_phyid(dev_id, port_id, &phy_id); - SW_RTN_ON_ERROR(rv); - - rv = phy_drv->phy_autoneg_enable_set(dev_id, phy_id); - return rv; -} - - -static sw_error_t -_athena_port_autoneg_restart(a_uint32_t dev_id, fal_port_t port_id) -{ - sw_error_t rv; - a_uint32_t phy_id; - hsl_phy_ops_t *phy_drv; - - HSL_DEV_ID_CHECK(dev_id); - - if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_PHY)) - { - return SW_BAD_PARAM; - } - - SW_RTN_ON_NULL (phy_drv = hsl_phy_api_ops_get (dev_id)); - if (NULL == phy_drv->phy_restart_autoneg) - return SW_NOT_SUPPORTED; - - rv = hsl_port_prop_get_phyid(dev_id, port_id, &phy_id); - SW_RTN_ON_ERROR(rv); - - rv = phy_drv->phy_restart_autoneg(dev_id, phy_id); - return rv; -} - - -static sw_error_t -_athena_port_autoneg_adv_set(a_uint32_t dev_id, fal_port_t port_id, - a_uint32_t autoadv) -{ - sw_error_t rv; - a_uint32_t phy_id; - hsl_phy_ops_t *phy_drv; - - HSL_DEV_ID_CHECK(dev_id); - - if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_PHY)) - { - return SW_BAD_PARAM; - } - - SW_RTN_ON_NULL (phy_drv = hsl_phy_api_ops_get (dev_id)); - if (NULL == phy_drv->phy_autoneg_adv_set) - return SW_NOT_SUPPORTED; - - rv = hsl_port_prop_get_phyid(dev_id, port_id, &phy_id); - SW_RTN_ON_ERROR(rv); - - rv = phy_drv->phy_autoneg_adv_set(dev_id, phy_id, autoadv); - SW_RTN_ON_ERROR(rv); - - return SW_OK; -} - - -static sw_error_t -_athena_port_autoneg_adv_get(a_uint32_t dev_id, fal_port_t port_id, - a_uint32_t * autoadv) -{ - sw_error_t rv; - a_uint32_t phy_id; - hsl_phy_ops_t *phy_drv; - - HSL_DEV_ID_CHECK(dev_id); - - if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_PHY)) - { - return SW_BAD_PARAM; - } - - SW_RTN_ON_NULL (phy_drv = hsl_phy_api_ops_get (dev_id)); - if (NULL == phy_drv->phy_autoneg_adv_get) - return SW_NOT_SUPPORTED; - - - rv = hsl_port_prop_get_phyid(dev_id, port_id, &phy_id); - SW_RTN_ON_ERROR(rv); - - *autoadv = 0; - rv = phy_drv->phy_autoneg_adv_get(dev_id, phy_id, autoadv); - SW_RTN_ON_ERROR(rv); - - return SW_OK; -} - - -static sw_error_t -_athena_port_igmps_status_set(a_uint32_t dev_id, fal_port_t port_id, - a_bool_t enable) -{ - sw_error_t rv; - a_uint32_t val; - - HSL_DEV_ID_CHECK(dev_id); - - if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_EXCL_CPU)) - { - return SW_BAD_PARAM; - } - - if (A_TRUE == enable) - { - val = 1; - } - else if (A_FALSE == enable) - { - val = 0; - } - else - { - return SW_BAD_PARAM; - } - - HSL_REG_FIELD_SET(rv, dev_id, PORT_CTL, port_id, IGMP_MLD_EN, - (a_uint8_t *) (&val), sizeof (a_uint32_t)); - - return rv; -} - - -static sw_error_t -_athena_port_igmps_status_get(a_uint32_t dev_id, fal_port_t port_id, - a_bool_t * enable) -{ - sw_error_t rv; - a_uint32_t val; - - HSL_DEV_ID_CHECK(dev_id); - - if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_EXCL_CPU)) - { - return SW_BAD_PARAM; - } - - HSL_REG_FIELD_GET(rv, dev_id, PORT_CTL, port_id, IGMP_MLD_EN, - (a_uint8_t *) (&val), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - - if (1 == val) - { - *enable = A_TRUE; - } - else - { - *enable = A_FALSE; - } - - return SW_OK; -} - -static sw_error_t -_athena_port_powersave_set(a_uint32_t dev_id, fal_port_t port_id, - a_bool_t enable) -{ - sw_error_t rv; - a_uint32_t phy_id = 0; - hsl_phy_ops_t *phy_drv; - - HSL_DEV_ID_CHECK(dev_id); - - if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_PHY)) - { - return SW_BAD_PARAM; - } - - SW_RTN_ON_NULL (phy_drv = hsl_phy_api_ops_get (dev_id)); - if (NULL == phy_drv->phy_powersave_set) - return SW_NOT_SUPPORTED; - - - rv = hsl_port_prop_get_phyid(dev_id, port_id, &phy_id); - SW_RTN_ON_ERROR(rv); - - rv = phy_drv->phy_powersave_set(dev_id, phy_id, enable); - - return rv; -} - -static sw_error_t -_athena_port_powersave_get(a_uint32_t dev_id, fal_port_t port_id, - a_bool_t *enable) -{ - sw_error_t rv; - a_uint32_t phy_id = 0; - hsl_phy_ops_t *phy_drv; - - HSL_DEV_ID_CHECK(dev_id); - - if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_PHY)) - { - return SW_BAD_PARAM; - } - - SW_RTN_ON_NULL (phy_drv = hsl_phy_api_ops_get (dev_id)); - if (NULL == phy_drv->phy_powersave_get) - return SW_NOT_SUPPORTED; - - - rv = hsl_port_prop_get_phyid(dev_id, port_id, &phy_id); - SW_RTN_ON_ERROR(rv); - - rv = phy_drv->phy_powersave_get(dev_id, phy_id, enable); - - return rv; -} - -static sw_error_t -_athena_port_hibernate_set(a_uint32_t dev_id, fal_port_t port_id, - a_bool_t enable) -{ - sw_error_t rv; - a_uint32_t phy_id = 0; - hsl_phy_ops_t *phy_drv; - - HSL_DEV_ID_CHECK(dev_id); - - if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_PHY)) - { - return SW_BAD_PARAM; - } - - SW_RTN_ON_NULL (phy_drv = hsl_phy_api_ops_get (dev_id)); - if (NULL == phy_drv->phy_hibernation_set) - return SW_NOT_SUPPORTED; - - rv = hsl_port_prop_get_phyid(dev_id, port_id, &phy_id); - SW_RTN_ON_ERROR(rv); - - rv = phy_drv->phy_hibernation_set(dev_id, phy_id, enable); - - return rv; -} - -static sw_error_t -_athena_port_hibernate_get(a_uint32_t dev_id, fal_port_t port_id, - a_bool_t *enable) -{ - sw_error_t rv; - a_uint32_t phy_id = 0; - hsl_phy_ops_t *phy_drv; - - HSL_DEV_ID_CHECK(dev_id); - - if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_PHY)) - { - return SW_BAD_PARAM; - } - - SW_RTN_ON_NULL (phy_drv = hsl_phy_api_ops_get (dev_id)); - if (NULL == phy_drv->phy_hibernation_get) - return SW_NOT_SUPPORTED; - - rv = hsl_port_prop_get_phyid(dev_id, port_id, &phy_id); - SW_RTN_ON_ERROR(rv); - - rv = phy_drv->phy_hibernation_get(dev_id, phy_id, enable); - - return rv; -} - -/** - * @brief Set duplex mode on a particular port. - * @param[in] dev_id device id - * @param[in] port_id port id - * @param[in] duplex duplex mode - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -athena_port_duplex_set(a_uint32_t dev_id, fal_port_t port_id, - fal_port_duplex_t duplex) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _athena_port_duplex_set(dev_id, port_id, duplex); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Get duplex mode on a particular port. - * @param[in] dev_id device id - * @param[in] port_id port id - * @param[out] duplex duplex mode - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -athena_port_duplex_get(a_uint32_t dev_id, fal_port_t port_id, - fal_port_duplex_t * pduplex) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _athena_port_duplex_get(dev_id, port_id, pduplex); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Set speed on a particular port. - * @param[in] dev_id device id - * @param[in] port_id port id - * @param[in] speed port speed - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -athena_port_speed_set(a_uint32_t dev_id, fal_port_t port_id, - fal_port_speed_t speed) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _athena_port_speed_set(dev_id, port_id, speed); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Get speed on a particular port. - * @param[in] dev_id device id - * @param[in] port_id port id - * @param[out] speed port speed - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -athena_port_speed_get(a_uint32_t dev_id, fal_port_t port_id, - fal_port_speed_t * pspeed) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _athena_port_speed_get(dev_id, port_id, pspeed); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Get auto negotiation status on a particular port. - * @param[in] dev_id device id - * @param[in] port_id port id - * @param[out] status A_TRUE or A_FALSE - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -athena_port_autoneg_status_get(a_uint32_t dev_id, fal_port_t port_id, - a_bool_t * status) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _athena_port_autoneg_status_get(dev_id, port_id, status); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Enable auto negotiation status on a particular port. - * @param[in] dev_id device id - * @param[in] port_id port id - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -athena_port_autoneg_enable(a_uint32_t dev_id, fal_port_t port_id) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _athena_port_autoneg_enable(dev_id, port_id); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Restart auto negotiation procedule on a particular port. - * @param[in] dev_id device id - * @param[in] port_id port id - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -athena_port_autoneg_restart(a_uint32_t dev_id, fal_port_t port_id) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _athena_port_autoneg_restart(dev_id, port_id); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Set auto negotiation advtisement ability on a particular port. - * @details Comments: - * Auto negotiation advtisement ability is defined by macro such as - * FAL_PHY_ADV_10T_HD, FAL_PHY_ADV_PAUSE... - * @param[in] dev_id device id - * @param[in] port_id port id - * @param[in] autoadv auto negotiation advtisement ability bit map - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -athena_port_autoneg_adv_set(a_uint32_t dev_id, fal_port_t port_id, - a_uint32_t autoadv) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _athena_port_autoneg_adv_set(dev_id, port_id, autoadv); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Get auto negotiation advtisement ability on a particular port. - * @param[in] dev_id device id - * @param[in] port_id port id - * @param[out] autoadv auto negotiation advtisement ability bit map - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -athena_port_autoneg_adv_get(a_uint32_t dev_id, fal_port_t port_id, - a_uint32_t * autoadv) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _athena_port_autoneg_adv_get(dev_id, port_id, autoadv); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Set igmp/mld packets snooping status on a particular port. - * @details Comments: - * After enabling igmp snooping feature on a particular port all kinds - * igmp packets received on this port would be acknowledged by hardware. - * Athena only supports igmp packets, it doesn't support mld packets. - * @param[in] dev_id device id - * @param[in] port_id port id - * @param[in] enable A_TRUE or A_FALSE - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -athena_port_igmps_status_set(a_uint32_t dev_id, fal_port_t port_id, - a_bool_t enable) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _athena_port_igmps_status_set(dev_id, port_id, enable); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Get igmp packets snooping status on a particular port. - * @param[in] dev_id device id - * @param[in] port_id port id - * @param[out] enable A_TRUE or A_FALSE - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -athena_port_igmps_status_get(a_uint32_t dev_id, fal_port_t port_id, - a_bool_t * enable) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _athena_port_igmps_status_get(dev_id, port_id, enable); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Set powersaving status on a particular port. - * @param[in] dev_id device id - * @param[in] port_id port id - * @param[out] enable A_TRUE or A_FALSE - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -athena_port_powersave_set(a_uint32_t dev_id, fal_port_t port_id, - a_bool_t enable) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _athena_port_powersave_set(dev_id, port_id, enable); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Get powersaving status on a particular port. - * @param[in] dev_id device id - * @param[in] port_id port id - * @param[out] enable A_TRUE or A_FALSE - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -athena_port_powersave_get(a_uint32_t dev_id, fal_port_t port_id, - a_bool_t *enable) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _athena_port_powersave_get(dev_id, port_id, enable); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Set hibernate status on a particular port. - * @param[in] dev_id device id - * @param[in] port_id port id - * @param[out] enable A_TRUE or A_FALSE - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -athena_port_hibernate_set(a_uint32_t dev_id, fal_port_t port_id, - a_bool_t enable) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _athena_port_hibernate_set(dev_id, port_id, enable); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Get hibernate status on a particular port. - * @param[in] dev_id device id - * @param[in] port_id port id - * @param[out] enable A_TRUE or A_FALSE - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -athena_port_hibernate_get(a_uint32_t dev_id, fal_port_t port_id, - a_bool_t *enable) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _athena_port_hibernate_get(dev_id, port_id, enable); - HSL_API_UNLOCK; - return rv; -} - -sw_error_t -athena_port_ctrl_init(a_uint32_t dev_id) -{ - HSL_DEV_ID_CHECK(dev_id); - -#ifndef HSL_STANDALONG - hsl_api_t *p_api; - - SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id)); - - p_api->port_duplex_get = athena_port_duplex_get; - p_api->port_duplex_set = athena_port_duplex_set; - p_api->port_speed_get = athena_port_speed_get; - p_api->port_speed_set = athena_port_speed_set; - p_api->port_autoneg_status_get = athena_port_autoneg_status_get; - p_api->port_autoneg_enable = athena_port_autoneg_enable; - p_api->port_autoneg_restart = athena_port_autoneg_restart; - p_api->port_autoneg_adv_get = athena_port_autoneg_adv_get; - p_api->port_autoneg_adv_set = athena_port_autoneg_adv_set; - p_api->port_igmps_status_set = athena_port_igmps_status_set; - p_api->port_igmps_status_get = athena_port_igmps_status_get; - p_api->port_powersave_set = athena_port_powersave_set; - p_api->port_powersave_get = athena_port_powersave_get; - p_api->port_hibernate_set = athena_port_hibernate_set; - p_api->port_hibernate_get = athena_port_hibernate_get; -#endif - - return SW_OK; -} - -/** - * @} - */ - diff --git a/feeds/ipq807x/qca-ssdk/src/src/hsl/athena/athena_portvlan.c b/feeds/ipq807x/qca-ssdk/src/src/hsl/athena/athena_portvlan.c deleted file mode 100755 index 74fdc3e02..000000000 --- a/feeds/ipq807x/qca-ssdk/src/src/hsl/athena/athena_portvlan.c +++ /dev/null @@ -1,451 +0,0 @@ -/* - * Copyright (c) 2012, The Linux Foundation. All rights reserved. - * Permission to use, copy, modify, and/or distribute this software for - * any purpose with or without fee is hereby granted, provided that the - * above copyright notice and this permission notice appear in all copies. - * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES - * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR - * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES - * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN - * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT - * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. - */ - - -/** - * @defgroup athena_port_vlan ATHENA_PORT_VLAN - * @{ - */ -#include "sw.h" -#include "hsl.h" -#include "hsl_dev.h" -#include "hsl_port_prop.h" -#include "athena_portvlan.h" -#include "athena_reg.h" - - -static sw_error_t -_athena_port_1qmode_set(a_uint32_t dev_id, fal_port_t port_id, - fal_pt_1qmode_t port_1qmode) -{ - sw_error_t rv; - a_uint32_t regval[FAL_1Q_MODE_BUTT] = { 0, 3, 2, 1 }; - - HSL_DEV_ID_CHECK(dev_id); - - if (A_FALSE == hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU)) - { - return SW_BAD_PARAM; - } - - if (FAL_1Q_MODE_BUTT <= port_1qmode) - { - return SW_BAD_PARAM; - } - - HSL_REG_FIELD_SET(rv, dev_id, PORT_BASE_VLAN, port_id, DOT1Q_MODE, - (a_uint8_t *) (®val[port_1qmode]), - sizeof (a_uint32_t)); - - return rv; - -} - - -static sw_error_t -_athena_port_1qmode_get(a_uint32_t dev_id, fal_port_t port_id, - fal_pt_1qmode_t * pport_1qmode) -{ - sw_error_t rv; - a_uint32_t regval = 0; - fal_pt_1qmode_t retval[4] = { FAL_1Q_DISABLE, FAL_1Q_FALLBACK, - FAL_1Q_CHECK, FAL_1Q_SECURE - }; - - HSL_DEV_ID_CHECK(dev_id); - - if (A_FALSE == hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU)) - { - return SW_BAD_PARAM; - } - - SW_RTN_ON_NULL(pport_1qmode); - - HSL_REG_FIELD_GET(rv, dev_id, PORT_BASE_VLAN, port_id, DOT1Q_MODE, - (a_uint8_t *) (®val), sizeof (a_uint32_t)); - - SW_RTN_ON_ERROR(rv); - - *pport_1qmode = retval[regval & 0x3]; - - return SW_OK; - -} - - -static sw_error_t -_athena_port_egvlanmode_set(a_uint32_t dev_id, fal_port_t port_id, - fal_pt_1q_egmode_t port_egvlanmode) -{ - sw_error_t rv; - a_uint32_t regval[FAL_EG_MODE_BUTT] = { 0, 1, 2, 3}; - - HSL_DEV_ID_CHECK(dev_id); - - if (A_FALSE == hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU)) - { - return SW_BAD_PARAM; - } - - if (FAL_EG_MODE_BUTT <= port_egvlanmode) - { - return SW_BAD_PARAM; - } - - if ((FAL_EG_TAGGED == port_egvlanmode) || (FAL_EG_HYBRID == port_egvlanmode)) - { - return SW_NOT_SUPPORTED; - } - - HSL_REG_FIELD_SET(rv, dev_id, PORT_CTL, port_id, EG_VLAN_MODE, - (a_uint8_t *) (®val[port_egvlanmode]), - sizeof (a_uint32_t)); - - return rv; - -} - - -static sw_error_t -_athena_port_egvlanmode_get(a_uint32_t dev_id, fal_port_t port_id, - fal_pt_1q_egmode_t * pport_egvlanmode) -{ - sw_error_t rv; - a_uint32_t regval = 0; - fal_pt_1q_egmode_t retval[3] = { FAL_EG_UNMODIFIED, FAL_EG_UNTAGGED, - FAL_EG_TAGGED - }; - - HSL_DEV_ID_CHECK(dev_id); - - if (A_FALSE == hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU)) - { - return SW_BAD_PARAM; - } - - SW_RTN_ON_NULL(pport_egvlanmode); - - HSL_REG_FIELD_GET(rv, dev_id, PORT_CTL, port_id, EG_VLAN_MODE, - (a_uint8_t *) (®val), sizeof (a_uint32_t)); - - SW_RTN_ON_ERROR(rv); - - *pport_egvlanmode = retval[regval & 0x3]; - - return SW_OK; - -} - - -static sw_error_t -_athena_portvlan_member_add(a_uint32_t dev_id, fal_port_t port_id, - a_uint32_t mem_port_id) -{ - sw_error_t rv; - a_uint32_t regval = 0; - - HSL_DEV_ID_CHECK(dev_id); - - if (A_FALSE == hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU)) - { - return SW_BAD_PARAM; - } - - if (A_FALSE == hsl_port_prop_check(dev_id, mem_port_id, HSL_PP_INCL_CPU)) - { - return SW_BAD_PARAM; - } - - HSL_REG_FIELD_GET(rv, dev_id, PORT_BASE_VLAN, port_id, - PORT_VID_MEM, (a_uint8_t *) (®val), - sizeof (a_uint32_t)); - - SW_RTN_ON_ERROR(rv); - - regval |= (0x1UL << mem_port_id); - - HSL_REG_FIELD_SET(rv, dev_id, PORT_BASE_VLAN, port_id, - PORT_VID_MEM, (a_uint8_t *) (®val), - sizeof (a_uint32_t)); - - return rv; - -} - - -static sw_error_t -_athena_portvlan_member_del(a_uint32_t dev_id, fal_port_t port_id, - a_uint32_t mem_port_id) -{ - sw_error_t rv; - a_uint32_t regval = 0; - - HSL_DEV_ID_CHECK(dev_id); - - if (A_FALSE == hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU)) - { - return SW_BAD_PARAM; - } - - if (A_FALSE == hsl_port_prop_check(dev_id, mem_port_id, HSL_PP_INCL_CPU)) - { - return SW_BAD_PARAM; - } - - HSL_REG_FIELD_GET(rv, dev_id, PORT_BASE_VLAN, port_id, - PORT_VID_MEM, (a_uint8_t *) (®val), - sizeof (a_uint32_t)); - - SW_RTN_ON_ERROR(rv); - - regval &= (~(0x1UL << mem_port_id)); - - HSL_REG_FIELD_SET(rv, dev_id, PORT_BASE_VLAN, port_id, - PORT_VID_MEM, (a_uint8_t *) (®val), - sizeof (a_uint32_t)); - - return rv; - -} - - -static sw_error_t -_athena_portvlan_member_update(a_uint32_t dev_id, fal_port_t port_id, - fal_pbmp_t mem_port_map) -{ - sw_error_t rv; - - HSL_DEV_ID_CHECK(dev_id); - - if (A_FALSE == hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU)) - { - return SW_BAD_PARAM; - } - - if (A_FALSE == - hsl_mports_prop_check(dev_id, mem_port_map, HSL_PP_INCL_CPU)) - { - return SW_BAD_PARAM; - } - - HSL_REG_FIELD_SET(rv, dev_id, PORT_BASE_VLAN, port_id, - PORT_VID_MEM, (a_uint8_t *) (&mem_port_map), - sizeof (a_uint32_t)); - - return rv; -} - - -static sw_error_t -_athena_portvlan_member_get(a_uint32_t dev_id, fal_port_t port_id, - fal_pbmp_t * mem_port_map) -{ - sw_error_t rv; - - HSL_DEV_ID_CHECK(dev_id); - - if (A_FALSE == hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU)) - { - return SW_BAD_PARAM; - } - - *mem_port_map = 0; - HSL_REG_FIELD_GET(rv, dev_id, PORT_BASE_VLAN, port_id, - PORT_VID_MEM, (a_uint8_t *) mem_port_map, - sizeof (a_uint32_t)); - - SW_RTN_ON_ERROR(rv); - - return SW_OK; -} - -/** - * @brief Set 802.1q work mode on a particular port. - * @param[in] dev_id device id - * @param[in] port_id port id - * @param[in] port_1qmode 802.1q work mode - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -athena_port_1qmode_set(a_uint32_t dev_id, fal_port_t port_id, - fal_pt_1qmode_t port_1qmode) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _athena_port_1qmode_set(dev_id, port_id, port_1qmode); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Get 802.1q work mode on a particular port. - * @param[in] dev_id device id - * @param[in] port_id port id - * @param[out] port_1qmode 802.1q work mode - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -athena_port_1qmode_get(a_uint32_t dev_id, fal_port_t port_id, - fal_pt_1qmode_t * pport_1qmode) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _athena_port_1qmode_get(dev_id, port_id, pport_1qmode); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Set packets transmitted out vlan tagged mode on a particular port. - * @param[in] dev_id device id - * @param[in] port_id port id - * @param[in] port_egvlanmode packets transmitted out vlan tagged mode - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -athena_port_egvlanmode_set(a_uint32_t dev_id, fal_port_t port_id, - fal_pt_1q_egmode_t port_egvlanmode) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _athena_port_egvlanmode_set(dev_id, port_id, port_egvlanmode); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Get packets transmitted out vlan tagged mode on a particular port. - * @param[in] dev_id device id - * @param[in] port_id port id - * @param[out] port_egvlanmode packets transmitted out vlan tagged mode - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -athena_port_egvlanmode_get(a_uint32_t dev_id, fal_port_t port_id, - fal_pt_1q_egmode_t * pport_egvlanmode) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _athena_port_egvlanmode_get(dev_id, port_id, pport_egvlanmode); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Add member of port based vlan on a particular port. - * @param[in] dev_id device id - * @param[in] port_id port id - * @param[in] mem_port_id port member - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -athena_portvlan_member_add(a_uint32_t dev_id, fal_port_t port_id, - a_uint32_t mem_port_id) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _athena_portvlan_member_add(dev_id, port_id, mem_port_id); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Delete member of port based vlan on a particular port. - * @param[in] dev_id device id - * @param[in] port_id port id - * @param[in] mem_port_id port member - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -athena_portvlan_member_del(a_uint32_t dev_id, fal_port_t port_id, - a_uint32_t mem_port_id) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _athena_portvlan_member_del(dev_id, port_id, mem_port_id); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Update member of port based vlan on a particular port. - * @param[in] dev_id device id - * @param[in] port_id port id - * @param[in] mem_port_map port members - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -athena_portvlan_member_update(a_uint32_t dev_id, fal_port_t port_id, - fal_pbmp_t mem_port_map) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _athena_portvlan_member_update(dev_id, port_id, mem_port_map); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Get member of port based vlan on a particular port. - * @param[in] dev_id device id - * @param[in] port_id port id - * @param[out] mem_port_map port members - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -athena_portvlan_member_get(a_uint32_t dev_id, fal_port_t port_id, - fal_pbmp_t * mem_port_map) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _athena_portvlan_member_get(dev_id, port_id, mem_port_map); - HSL_API_UNLOCK; - return rv; -} - -sw_error_t -athena_portvlan_init(a_uint32_t dev_id) -{ - HSL_DEV_ID_CHECK(dev_id); - -#ifndef HSL_STANDALONG - hsl_api_t *p_api; - - SW_RTN_ON_NULL (p_api = hsl_api_ptr_get(dev_id)); - - p_api->port_1qmode_get = athena_port_1qmode_get; - p_api->port_1qmode_set = athena_port_1qmode_set; - p_api->port_egvlanmode_get = athena_port_egvlanmode_get; - p_api->port_egvlanmode_set = athena_port_egvlanmode_set; - p_api->portvlan_member_add = athena_portvlan_member_add; - p_api->portvlan_member_del = athena_portvlan_member_del; - p_api->portvlan_member_update = athena_portvlan_member_update; - p_api->portvlan_member_get = athena_portvlan_member_get; -#endif - - return SW_OK; -} - -/** - * @} - */ - diff --git a/feeds/ipq807x/qca-ssdk/src/src/hsl/athena/athena_reg_access.c b/feeds/ipq807x/qca-ssdk/src/src/hsl/athena/athena_reg_access.c deleted file mode 100755 index be4ae4610..000000000 --- a/feeds/ipq807x/qca-ssdk/src/src/hsl/athena/athena_reg_access.c +++ /dev/null @@ -1,272 +0,0 @@ -/* - * Copyright (c) 2012, The Linux Foundation. All rights reserved. - * Permission to use, copy, modify, and/or distribute this software for - * any purpose with or without fee is hereby granted, provided that the - * above copyright notice and this permission notice appear in all copies. - * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES - * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR - * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES - * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN - * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT - * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. - */ - - -#include "sw.h" -#include "hsl.h" -#include "hsl_dev.h" -#include "sd.h" -#include "athena_reg_access.h" - -static hsl_access_mode reg_mode; - -#if defined(API_LOCK) -static aos_lock_t mdio_lock; -#define MDIO_LOCKER_INIT aos_lock_init(&mdio_lock) -#define MDIO_LOCKER_LOCK aos_lock(&mdio_lock) -#define MDIO_LOCKER_UNLOCK aos_unlock(&mdio_lock) -#else -#define MDIO_LOCKER_INIT -#define MDIO_LOCKER_LOCK -#define MDIO_LOCKER_UNLOCK -#endif - -static sw_error_t -_athena_mdio_reg_get(a_uint32_t dev_id, a_uint32_t reg_addr, - a_uint8_t value[], a_uint32_t value_len) -{ - a_uint32_t reg_word_addr; - a_uint32_t phy_addr, reg_val; - a_uint16_t phy_val, tmp_val; - a_uint8_t phy_reg; - sw_error_t rv; - - if (value_len != sizeof (a_uint32_t)) - return SW_BAD_LEN; - - /* change reg_addr to 16-bit word address, 32-bit aligned */ - reg_word_addr = (reg_addr & 0xfffffffc) >> 1; - - /* configure register high address */ - phy_addr = 0x18; - phy_reg = 0x0; - phy_val = (a_uint16_t) ((reg_word_addr >> 8) & 0x3ff); /* bit16-8 of reg address */ - - rv = sd_reg_mdio_set(dev_id, phy_addr, phy_reg, phy_val); - SW_RTN_ON_ERROR(rv); - - /* For some registers such as MIBs, since it is read/clear, we should */ - /* read the lower 16-bit register then the higher one */ - - /* read register in lower address */ - phy_addr = 0x10 | ((reg_word_addr >> 5) & 0x7); /* bit7-5 of reg address */ - phy_reg = (a_uint8_t) (reg_word_addr & 0x1f); /* bit4-0 of reg address */ - rv = sd_reg_mdio_get(dev_id, phy_addr, phy_reg, &tmp_val); - SW_RTN_ON_ERROR(rv); - reg_val = tmp_val; - - /* read register in higher address */ - reg_word_addr++; - phy_addr = 0x10 | ((reg_word_addr >> 5) & 0x7); /* bit7-5 of reg address */ - phy_reg = (a_uint8_t) (reg_word_addr & 0x1f); /* bit4-0 of reg address */ - rv = sd_reg_mdio_get(dev_id, phy_addr, phy_reg, &tmp_val); - SW_RTN_ON_ERROR(rv); - reg_val |= (((a_uint32_t)tmp_val) << 16); - - aos_mem_copy(value, ®_val, sizeof (a_uint32_t)); - - return SW_OK; -} - -static sw_error_t -_athena_mdio_reg_set(a_uint32_t dev_id, a_uint32_t reg_addr, a_uint8_t value[], - a_uint32_t value_len) -{ - a_uint32_t reg_word_addr; - a_uint32_t phy_addr, reg_val; - a_uint16_t phy_val; - a_uint8_t phy_reg; - sw_error_t rv; - - if (value_len != sizeof (a_uint32_t)) - return SW_BAD_LEN; - - aos_mem_copy(®_val, value, sizeof (a_uint32_t)); - - /* change reg_addr to 16-bit word address, 32-bit aligned */ - reg_word_addr = (reg_addr & 0xfffffffc) >> 1; - - /* configure register high address */ - phy_addr = 0x18; - phy_reg = 0x0; - phy_val = (a_uint16_t) ((reg_word_addr >> 8) & 0x3ff); /* bit16-8 of reg address */ - - rv = sd_reg_mdio_set(dev_id, phy_addr, phy_reg, phy_val); - SW_RTN_ON_ERROR(rv); - - /* For some registers such as ARL and VLAN, since they include BUSY bit */ - /* in lower address, we should write the higher 16-bit register then the */ - /* lower one */ - - /* write register in higher address */ - reg_word_addr++; - phy_addr = 0x10 | ((reg_word_addr >> 5) & 0x7); /* bit7-5 of reg address */ - phy_reg = (a_uint8_t) (reg_word_addr & 0x1f); /* bit4-0 of reg address */ - phy_val = (a_uint16_t) ((reg_val >> 16) & 0xffff); - rv = sd_reg_mdio_set(dev_id, phy_addr, phy_reg, phy_val); - SW_RTN_ON_ERROR(rv); - - /* write register in lower address */ - reg_word_addr--; - phy_addr = 0x10 | ((reg_word_addr >> 5) & 0x7); /* bit7-5 of reg address */ - phy_reg = (a_uint8_t) (reg_word_addr & 0x1f); /* bit4-0 of reg address */ - phy_val = (a_uint16_t) (reg_val & 0xffff); - rv = sd_reg_mdio_set(dev_id, phy_addr, phy_reg, phy_val); - SW_RTN_ON_ERROR(rv); - - return SW_OK; -} - -sw_error_t -athena_phy_get(a_uint32_t dev_id, a_uint32_t phy_addr, - a_uint32_t reg, a_uint16_t * value) -{ - sw_error_t rv; - - MDIO_LOCKER_LOCK; - rv = sd_reg_mdio_get(dev_id, phy_addr, reg, value); - MDIO_LOCKER_UNLOCK; - - return rv; -} - -sw_error_t -athena_phy_set(a_uint32_t dev_id, a_uint32_t phy_addr, - a_uint32_t reg, a_uint16_t value) -{ - sw_error_t rv; - - MDIO_LOCKER_LOCK; - rv = sd_reg_mdio_set(dev_id, phy_addr, reg, value); - MDIO_LOCKER_UNLOCK; - - return rv; -} - -sw_error_t -athena_reg_get(a_uint32_t dev_id, a_uint32_t reg_addr, a_uint8_t value[], - a_uint32_t value_len) -{ - sw_error_t rv; - a_uint32_t flags; - - MDIO_LOCKER_LOCK; - if (HSL_MDIO == reg_mode) - { - aos_irq_save(flags); - rv = _athena_mdio_reg_get(dev_id, reg_addr, value, value_len); - aos_irq_restore(flags); - } - else - { - rv = sd_reg_hdr_get(dev_id, reg_addr, value, value_len); - } - MDIO_LOCKER_UNLOCK; - - return rv; -} - -sw_error_t -athena_reg_set(a_uint32_t dev_id, a_uint32_t reg_addr, a_uint8_t value[], - a_uint32_t value_len) -{ - sw_error_t rv; - a_uint32_t flags; - - MDIO_LOCKER_LOCK; - if (HSL_MDIO == reg_mode) - { - aos_irq_save(flags); - rv = _athena_mdio_reg_set(dev_id, reg_addr, value, value_len); - aos_irq_restore(flags); - } - else - { - rv = sd_reg_hdr_set(dev_id, reg_addr, value, value_len); - } - MDIO_LOCKER_UNLOCK; - - return rv; -} - -sw_error_t -athena_reg_field_get(a_uint32_t dev_id, a_uint32_t reg_addr, - a_uint32_t bit_offset, a_uint32_t field_len, - a_uint8_t value[], a_uint32_t value_len) -{ - a_uint32_t reg_val = 0; - - if ((bit_offset >= 32 || (field_len > 32)) || (field_len == 0)) - return SW_OUT_OF_RANGE; - - if (value_len != sizeof (a_uint32_t)) - return SW_BAD_LEN; - - SW_RTN_ON_ERROR(athena_reg_get(dev_id, reg_addr, (a_uint8_t *) & reg_val, sizeof (a_uint32_t))); - - *((a_uint32_t *) value) = SW_REG_2_FIELD(reg_val, bit_offset, field_len); - return SW_OK; -} - -sw_error_t -athena_reg_field_set(a_uint32_t dev_id, a_uint32_t reg_addr, - a_uint32_t bit_offset, a_uint32_t field_len, - const a_uint8_t value[], a_uint32_t value_len) -{ - a_uint32_t reg_val; - a_uint32_t field_val = *((a_uint32_t *) value); - - if ((bit_offset >= 32 || (field_len > 32)) || (field_len == 0)) - return SW_OUT_OF_RANGE; - - if (value_len != sizeof (a_uint32_t)) - return SW_BAD_LEN; - - SW_RTN_ON_ERROR(athena_reg_get(dev_id, reg_addr, (a_uint8_t *) & reg_val, sizeof (a_uint32_t))); - - SW_REG_SET_BY_FIELD_U32(reg_val, field_val, bit_offset, field_len); - - SW_RTN_ON_ERROR(athena_reg_set(dev_id, reg_addr, (a_uint8_t *) & reg_val, sizeof (a_uint32_t))); - - return SW_OK; -} - -sw_error_t -athena_reg_access_init(a_uint32_t dev_id, hsl_access_mode mode) -{ - hsl_api_t *p_api; - - MDIO_LOCKER_INIT; - reg_mode = mode; - - SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id)); - p_api->phy_get = athena_phy_get; - p_api->phy_set = athena_phy_set; - p_api->reg_get = athena_reg_get; - p_api->reg_set = athena_reg_set; - p_api->reg_field_get = athena_reg_field_get; - p_api->reg_field_set = athena_reg_field_set; - p_api->dev_access_set= athena_access_mode_set; - - return SW_OK; -} - -sw_error_t -athena_access_mode_set(a_uint32_t dev_id, hsl_access_mode mode) -{ - reg_mode = mode; - return SW_OK; - -} - diff --git a/feeds/ipq807x/qca-ssdk/src/src/hsl/athena/athena_vlan.c b/feeds/ipq807x/qca-ssdk/src/src/hsl/athena/athena_vlan.c deleted file mode 100755 index a4f48f5d2..000000000 --- a/feeds/ipq807x/qca-ssdk/src/src/hsl/athena/athena_vlan.c +++ /dev/null @@ -1,622 +0,0 @@ -/* - * Copyright (c) 2012, The Linux Foundation. All rights reserved. - * Permission to use, copy, modify, and/or distribute this software for - * any purpose with or without fee is hereby granted, provided that the - * above copyright notice and this permission notice appear in all copies. - * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES - * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR - * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES - * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN - * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT - * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. - */ - - -/** - * @defgroup athena_vlan ATHENA_VLAN - * @{ - */ -#include "sw.h" -#include "hsl.h" -#include "hsl_dev.h" -#include "hsl_port_prop.h" -#include "athena_vlan.h" -#include "athena_reg.h" - -#define MAX_VLAN_ENTRY 16 -#define MAX_VLAN_ID 4094 - -#define VLAN_FLUSH 1 -#define VLAN_LOAD_ENTRY 2 -#define VLAN_PURGE_ENTRY 3 -#define VLAN_REMOVE_PORT 4 - -typedef struct -{ - fal_vlan_t vlan_entry; - a_bool_t active; -} v_array_t; - -static v_array_t *p_vlan_table[SW_MAX_NR_DEV] = { 0 }; - -static sw_error_t -athena_vlan_commit(a_uint32_t dev_id, a_uint32_t op) -{ - a_uint32_t vt_busy = 1, i = 0x1000, vt_full, val; - sw_error_t rv; - - while (vt_busy && --i) - { - HSL_REG_FIELD_GET(rv, dev_id, VLAN_TABLE_FUNC0, 0, VT_BUSY, - (a_uint8_t *) (&vt_busy), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - aos_udelay(5); - } - - if (i == 0) - return SW_BUSY; - - HSL_REG_ENTRY_GET(rv, dev_id, VLAN_TABLE_FUNC0, 0, - (a_uint8_t *) (&val), sizeof (a_uint32_t)); - SW_SET_REG_BY_FIELD(VLAN_TABLE_FUNC0, VT_FUNC, op, val); - SW_SET_REG_BY_FIELD(VLAN_TABLE_FUNC0, VT_BUSY, 1, val); - - HSL_REG_ENTRY_SET(rv, dev_id, VLAN_TABLE_FUNC0, 0, - (a_uint8_t *) (&val), sizeof (a_uint32_t)); - - SW_RTN_ON_ERROR(rv); - - HSL_REG_FIELD_GET(rv, dev_id, VLAN_TABLE_FUNC0, 0, VT_FULL_VIO, - (a_uint8_t *) (&vt_full), sizeof (a_uint32_t)); - - SW_RTN_ON_ERROR(rv); - - if (vt_full) - { - val = 0x10; - HSL_REG_ENTRY_SET(rv, dev_id, VLAN_TABLE_FUNC0, 0, - (a_uint8_t *) (&val), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - if (VLAN_LOAD_ENTRY == op) - { - return SW_FULL; - } - else if (VLAN_PURGE_ENTRY == op) - { - return SW_NOT_FOUND; - } - } - - return SW_OK; -} - -static sw_error_t -athena_vlan_table_location(a_uint32_t dev_id, a_uint16_t vlan_id, - a_int16_t * loc) -{ - a_int16_t i = 0; - v_array_t *p_v_array; - - if (p_vlan_table[dev_id] == NULL) - return SW_NOT_INITIALIZED; - - p_v_array = p_vlan_table[dev_id]; - - for (i = 0; i < MAX_VLAN_ENTRY; i++) - { - if ((p_v_array[i].active == A_TRUE) - && (p_v_array[i].vlan_entry.vid == vlan_id)) - break; - } - - if (i == MAX_VLAN_ENTRY) - return SW_NOT_FOUND; - - *loc = i; - - return SW_OK; -} - -static sw_error_t -athena_vlan_sw_to_hw(const fal_vlan_t * vlan_entry, a_uint32_t reg[]) -{ - if (A_TRUE == vlan_entry->vid_pri_en) - { - SW_SET_REG_BY_FIELD(VLAN_TABLE_FUNC0, VT_PRI_EN, 1, reg[0]); - SW_SET_REG_BY_FIELD(VLAN_TABLE_FUNC0, VT_PRI, vlan_entry->vid_pri, reg[0]); - } - else - { - SW_SET_REG_BY_FIELD(VLAN_TABLE_FUNC0, VT_PRI_EN, 0, reg[0]); - } - - SW_SET_REG_BY_FIELD(VLAN_TABLE_FUNC0, VLAN_ID, vlan_entry->vid, reg[0]); - - SW_SET_REG_BY_FIELD(VLAN_TABLE_FUNC1, VT_VALID, 1, reg[1]); - SW_SET_REG_BY_FIELD(VLAN_TABLE_FUNC1, VID_MEM, vlan_entry->mem_ports, reg[1]); - - if (0 != vlan_entry->u_ports) - { - return SW_BAD_VALUE; - } - - return SW_OK; -} - -static sw_error_t -_athena_vlan_entry_append(a_uint32_t dev_id, const fal_vlan_t * vlan_entry) -{ - sw_error_t rv; - a_uint32_t reg[2] = { 0 }; -#ifdef HSL_STANDALONG - a_int16_t i, loc = MAX_VLAN_ENTRY; - v_array_t *p_v_array; -#endif - - HSL_DEV_ID_CHECK(dev_id); - - if ((vlan_entry->vid == 0) || (vlan_entry->vid > MAX_VLAN_ID)) - return SW_OUT_OF_RANGE; - - if (A_FALSE == hsl_mports_prop_check(dev_id, vlan_entry->mem_ports, HSL_PP_INCL_CPU)) - return SW_BAD_PARAM; - -#ifdef HSL_STANDALONG - if ((p_v_array = p_vlan_table[dev_id]) == NULL) - return SW_NOT_INITIALIZED; - - for (i = 0; i < MAX_VLAN_ENTRY; i++) - { - if (p_v_array[i].active == A_FALSE) - { - loc = i; - } - else if (p_v_array[i].vlan_entry.vid == vlan_entry->vid) - { - return SW_ALREADY_EXIST; - } - } - - if (loc == MAX_VLAN_ENTRY) - return SW_FULL; -#endif - - rv = athena_vlan_sw_to_hw(vlan_entry, reg); - SW_RTN_ON_ERROR(rv); - - HSL_REG_ENTRY_SET(rv, dev_id, VLAN_TABLE_FUNC0, 0, - (a_uint8_t *) (®[0]), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - - HSL_REG_ENTRY_SET(rv, dev_id, VLAN_TABLE_FUNC1, 0, - (a_uint8_t *) (®[1]), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - - rv = athena_vlan_commit(dev_id, VLAN_LOAD_ENTRY); - SW_RTN_ON_ERROR(rv); - -#ifdef HSL_STANDALONG - p_v_array[loc].vlan_entry = *vlan_entry; - p_v_array[loc].active = A_TRUE; -#endif - - return SW_OK; -} - - -static sw_error_t -_athena_vlan_create(a_uint32_t dev_id, a_uint32_t vlan_id) -{ - sw_error_t rv; - a_uint32_t vtable_entry = 0; -#ifdef HSL_STANDALONG - a_int16_t i, loc = MAX_VLAN_ENTRY; - v_array_t *p_v_array; -#endif - - HSL_DEV_ID_CHECK(dev_id); - - if ((vlan_id == 0) || (vlan_id > MAX_VLAN_ID)) - return SW_OUT_OF_RANGE; - -#ifdef HSL_STANDALONG - if ((p_v_array = p_vlan_table[dev_id]) == NULL) - return SW_NOT_INITIALIZED; - - for (i = 0; i < MAX_VLAN_ENTRY; i++) - { - if (p_v_array[i].active == A_FALSE) - { - loc = i; - } - else if (p_v_array[i].vlan_entry.vid == vlan_id) - { - return SW_ALREADY_EXIST; - } - } - - if (loc == MAX_VLAN_ENTRY) - return SW_FULL; -#endif - - /* set default value for VLAN_TABLE_FUNC0, all 0 except vid */ - vtable_entry = 0; - SW_SET_REG_BY_FIELD(VLAN_TABLE_FUNC0, VLAN_ID, vlan_id, vtable_entry); - HSL_REG_ENTRY_SET(rv, dev_id, VLAN_TABLE_FUNC0, 0, - (a_uint8_t *) (&vtable_entry), sizeof (a_uint32_t)); - - SW_RTN_ON_ERROR(rv); - - /* set default value for VLAN_TABLE_FUNC1, all 0 */ - vtable_entry = 0; - SW_SET_REG_BY_FIELD(VLAN_TABLE_FUNC1, VT_VALID, 1, vtable_entry); - HSL_REG_ENTRY_SET(rv, dev_id, VLAN_TABLE_FUNC1, 0, - (a_uint8_t *) (&vtable_entry), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - - rv = athena_vlan_commit(dev_id, VLAN_LOAD_ENTRY); - SW_RTN_ON_ERROR(rv); - -#ifdef HSL_STANDALONG - p_v_array[loc].vlan_entry.vid = vlan_id; - p_v_array[loc].vlan_entry.mem_ports = 0; - p_v_array[loc].vlan_entry.u_ports = 0; - p_v_array[loc].vlan_entry.vid_pri_en = A_FALSE; - p_v_array[loc].vlan_entry.vid_pri = 0; - p_v_array[loc].active = A_TRUE; -#endif - - return SW_OK; -} - - -static sw_error_t -_athena_vlan_next(a_uint32_t dev_id, a_uint32_t vlan_id, fal_vlan_t * p_vlan) -{ -#ifdef HSL_STANDALONG - a_uint16_t i = 0, loc = MAX_VLAN_ENTRY; - a_uint16_t tmp_vid = MAX_VLAN_ID + 1; - v_array_t *p_v_array; - - HSL_DEV_ID_CHECK(dev_id); - - if (vlan_id > MAX_VLAN_ID) - return SW_OUT_OF_RANGE; - - if ((p_v_array = p_vlan_table[dev_id]) == NULL) - return SW_NOT_INITIALIZED; - - for (i = 0; i < MAX_VLAN_ENTRY; i++) - { - if ((p_v_array[i].active == A_TRUE) - && (p_v_array[i].vlan_entry.vid > vlan_id)) - { - if (tmp_vid > p_v_array[i].vlan_entry.vid) - { - loc = i; - tmp_vid = p_v_array[i].vlan_entry.vid; - } - } - } - - if (loc == MAX_VLAN_ENTRY) - return SW_NO_MORE; - - *p_vlan = p_v_array[loc].vlan_entry; - - return SW_OK; -#else - return SW_NOT_SUPPORTED; -#endif -} - - -static sw_error_t -_athena_vlan_find(a_uint32_t dev_id, a_uint32_t vlan_id, fal_vlan_t * p_vlan) -{ -#ifdef HSL_STANDALONG - a_int16_t loc; - v_array_t *p_v_array; - sw_error_t rv; - - HSL_DEV_ID_CHECK(dev_id); - - if ((vlan_id == 0) || (vlan_id > MAX_VLAN_ID)) - return SW_OUT_OF_RANGE; - - if ((p_v_array = p_vlan_table[dev_id]) == NULL) - return SW_NOT_INITIALIZED; - - rv = athena_vlan_table_location(dev_id, vlan_id, &loc); - SW_RTN_ON_ERROR(rv); - *p_vlan = p_v_array[loc].vlan_entry; - - return SW_OK; -#else - return SW_NOT_SUPPORTED; -#endif -} - - -static sw_error_t -_athena_vlan_member_update(a_uint32_t dev_id, a_uint32_t vlan_id, - fal_pbmp_t member, fal_pbmp_t u_member) -{ -#ifdef HSL_STANDALONG - sw_error_t rv; - a_int16_t loc; - a_uint32_t reg_tmp; - v_array_t *p_v_array; - fal_vlan_t *p_sw_vlan; - - HSL_DEV_ID_CHECK(dev_id); - - if ((vlan_id == 0) || (vlan_id > MAX_VLAN_ID)) - return SW_OUT_OF_RANGE; - - if (A_FALSE == hsl_mports_prop_check(dev_id, member, HSL_PP_INCL_CPU)) - return SW_BAD_PARAM; - - if (u_member != 0) - return SW_BAD_PARAM; - - if ((p_v_array = p_vlan_table[dev_id]) == NULL) - return SW_NOT_INITIALIZED; - - rv = athena_vlan_table_location(dev_id, vlan_id, &loc); - SW_RTN_ON_ERROR(rv); - p_sw_vlan = &p_v_array[loc].vlan_entry; - - /* set value for VLAN_TABLE_FUNC0, all 0 except vid */ - reg_tmp = 0; - SW_SET_REG_BY_FIELD(VLAN_TABLE_FUNC0, VLAN_ID, vlan_id, reg_tmp); - SW_SET_REG_BY_FIELD(VLAN_TABLE_FUNC0, VT_PRI_EN, - (a_int32_t)p_sw_vlan->vid_pri_en, reg_tmp); - SW_SET_REG_BY_FIELD(VLAN_TABLE_FUNC0, VT_PRI, p_sw_vlan->vid_pri, reg_tmp); - HSL_REG_ENTRY_SET(rv, dev_id, VLAN_TABLE_FUNC0, 0, - (a_uint8_t *) (®_tmp), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - - /* set vlan member for VLAN_TABLE_FUNC1 */ - HSL_REG_FIELD_SET(rv, dev_id, VLAN_TABLE_FUNC1, 0, VID_MEM, - (a_uint8_t *) (&member), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - - rv = athena_vlan_commit(dev_id, VLAN_LOAD_ENTRY); - SW_RTN_ON_ERROR(rv); - - p_v_array[loc].vlan_entry.mem_ports = member; - - return SW_OK; -#else - return SW_NOT_SUPPORTED; -#endif -} - - -static sw_error_t -_athena_vlan_delete(a_uint32_t dev_id, a_uint32_t vlan_id) -{ - sw_error_t rv; - a_int16_t loc; - a_uint32_t reg_tmp; -#ifdef HSL_STANDALONG - v_array_t *p_v_array; -#endif - - HSL_DEV_ID_CHECK(dev_id); - - if ((vlan_id == 0) || (vlan_id > MAX_VLAN_ID)) - return SW_OUT_OF_RANGE; - -#ifdef HSL_STANDALONG - if ((p_v_array = p_vlan_table[dev_id]) == NULL) - return SW_NOT_INITIALIZED; - - rv = athena_vlan_table_location(dev_id, vlan_id, &loc); - SW_RTN_ON_ERROR(rv); -#endif - - reg_tmp = (a_int32_t) vlan_id; - HSL_REG_FIELD_SET(rv, dev_id, VLAN_TABLE_FUNC0, 0, VLAN_ID, - (a_uint8_t *) (®_tmp), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - - rv = athena_vlan_commit(dev_id, VLAN_PURGE_ENTRY); - SW_RTN_ON_ERROR(rv); - -#ifdef HSL_STANDALONG - p_v_array[loc].active = A_FALSE; -#endif - - return SW_OK; -} - -sw_error_t -athena_vlan_reset(a_uint32_t dev_id) -{ -#ifdef HSL_STANDALONG - a_int16_t i; - v_array_t *p_v_array; - - HSL_DEV_ID_CHECK(dev_id); - - aos_mem_zero(p_vlan_table[dev_id], MAX_VLAN_ENTRY * (sizeof (v_array_t))); - - p_v_array = p_vlan_table[dev_id]; - for (i = 0; i < MAX_VLAN_ENTRY; i++) - { - p_v_array[i].active = A_FALSE; - } -#endif - - return SW_OK; -} - -sw_error_t -athena_vlan_cleanup(a_uint32_t dev_id) -{ - if (p_vlan_table[dev_id]) - { - aos_mem_free(p_vlan_table[dev_id]); - p_vlan_table[dev_id] = NULL; - } - - return SW_OK; -} - -/** - * @brief Append a vlan entry on paticular device. - * @param[in] dev_id device id - * @param[in] vlan_entry vlan entry - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -athena_vlan_entry_append(a_uint32_t dev_id, const fal_vlan_t * vlan_entry) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _athena_vlan_entry_append(dev_id, vlan_entry); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Creat a vlan entry through vlan id on a paticular device. - * @details Comments: - * After this operation the member ports of the created vlan entry are null. - * @param[in] dev_id device id - * @param[in] vlan_id vlan id - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -athena_vlan_create(a_uint32_t dev_id, a_uint32_t vlan_id) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _athena_vlan_create(dev_id, vlan_id); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Next a vlan entry through vlan id on a paticular device. - * @details Comments: - * If the value of vid is zero this operation will get the first entry. - * @param[in] dev_id device id - * @param[in] vlan_id vlan id - * @param[out] p_vlan vlan entry - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -athena_vlan_next(a_uint32_t dev_id, a_uint32_t vlan_id, fal_vlan_t * p_vlan) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _athena_vlan_next(dev_id, vlan_id, p_vlan); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Find a vlan entry through vlan id on paticular device. - * @param[in] dev_id device id - * @param[in] vlan_id vlan id - * @param[out] p_vlan vlan entry - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -athena_vlan_find(a_uint32_t dev_id, a_uint32_t vlan_id, fal_vlan_t * p_vlan) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _athena_vlan_find(dev_id, vlan_id, p_vlan); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Update a vlan entry member port through vlan id on a paticular device. - * @param[in] dev_id device id - * @param[in] vlan_id vlan id - * @param[in] member member ports - * @param[in] u_member tagged or untagged infomation for member ports - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -athena_vlan_member_update(a_uint32_t dev_id, a_uint32_t vlan_id, - fal_pbmp_t member, fal_pbmp_t u_member) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _athena_vlan_member_update(dev_id, vlan_id, member, u_member); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Delete a vlan entry through vlan id on a paticular device. - * @param[in] dev_id device id - * @param[in] vlan_id vlan id - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -athena_vlan_delete(a_uint32_t dev_id, a_uint32_t vlan_id) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _athena_vlan_delete(dev_id, vlan_id); - HSL_API_UNLOCK; - return rv; -} - -sw_error_t -athena_vlan_init(a_uint32_t dev_id) -{ -#ifdef HSL_STANDALONG - a_int16_t i; - v_array_t *p_v_array; - v_array_t *p_mem; - - HSL_DEV_ID_CHECK(dev_id); - - /* allocate memory for vlan info */ - p_mem = aos_mem_alloc(MAX_VLAN_ENTRY * (sizeof (v_array_t))); - if (p_mem == NULL) - return SW_OUT_OF_MEM; - - aos_mem_zero(p_mem, MAX_VLAN_ENTRY * (sizeof (v_array_t))); - - /* start address for vlan info */ - p_vlan_table[dev_id] = p_v_array = p_mem; - - for (i = 0; i < MAX_VLAN_ENTRY; i++) - { - p_v_array[i].active = A_FALSE; - } -#endif - -#ifndef HSL_STANDALONG - hsl_api_t *p_api; - - SW_RTN_ON_NULL (p_api = hsl_api_ptr_get(dev_id)); - - p_api->vlan_entry_append = athena_vlan_entry_append; - p_api->vlan_creat = athena_vlan_create; - p_api->vlan_delete = athena_vlan_delete; -#endif - - return SW_OK; -} - -/** - * @} - */ - diff --git a/feeds/ipq807x/qca-ssdk/src/src/hsl/cppe/Makefile b/feeds/ipq807x/qca-ssdk/src/src/hsl/cppe/Makefile deleted file mode 100755 index 73c4dd620..000000000 --- a/feeds/ipq807x/qca-ssdk/src/src/hsl/cppe/Makefile +++ /dev/null @@ -1,23 +0,0 @@ -LOC_DIR=src/hsl/cppe -LIB=HSL - -include $(PRJ_PATH)/make/config.mk - -ifeq (TRUE, $(IN_PORTCONTROL)) - SRC_LIST+=cppe_portctrl.c - SRC_LIST+=cppe_loopback.c -endif - -ifeq (TRUE, $(IN_QOS)) - SRC_LIST+=cppe_qos.c -endif - -ifeq (, $(findstring CPPE, $(SUPPORT_CHIP))) - SRC_LIST= -endif - -include $(PRJ_PATH)/make/components.mk -include $(PRJ_PATH)/make/defs.mk -include $(PRJ_PATH)/make/target.mk - -all: dep obj diff --git a/feeds/ipq807x/qca-ssdk/src/src/hsl/cppe/cppe_loopback.c b/feeds/ipq807x/qca-ssdk/src/src/hsl/cppe/cppe_loopback.c deleted file mode 100755 index 49795aecf..000000000 --- a/feeds/ipq807x/qca-ssdk/src/src/hsl/cppe/cppe_loopback.c +++ /dev/null @@ -1,440 +0,0 @@ -/* - * Copyright (c) 2019, The Linux Foundation. All rights reserved. - * Permission to use, copy, modify, and/or distribute this software for - * any purpose with or without fee is hereby granted, provided that the - * above copyright notice and this permission notice appear in all copies. - * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES - * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR - * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES - * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN - * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT - * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. - */ -/** - * @defgroup - * @{ - */ -#include "sw.h" -#include "hsl.h" -#include "hppe_reg_access.h" -#include "cppe_loopback_reg.h" -#include "cppe_loopback.h" - -sw_error_t -cppe_lpbk_enable_get( - a_uint32_t dev_id, - a_uint32_t index, - union lpbk_enable_u *value) -{ - return hppe_reg_get( - dev_id, - NSS_MAC_CSR_BASE_ADDR + LPBK_ENABLE_ADDRESS + \ - index * LPBK_ENABLEL_INC, - &value->val); -} - -sw_error_t -cppe_lpbk_enable_set( - a_uint32_t dev_id, - a_uint32_t index, - union lpbk_enable_u *value) -{ - return hppe_reg_set( - dev_id, - NSS_MAC_CSR_BASE_ADDR + LPBK_ENABLE_ADDRESS + \ - index * LPBK_ENABLEL_INC, - value->val); -} - -sw_error_t -cppe_lpbk_fifo_1_ctrl_get( - a_uint32_t dev_id, - a_uint32_t index, - union lpbk_fifo_1_ctrl_u *value) -{ - return hppe_reg_get( - dev_id, - NSS_MAC_CSR_BASE_ADDR + LPBK_FIFO_1_CTRL_ADDRESS + \ - index * LPBK_FIFO_1_CTRL_INC, - &value->val); -} - -sw_error_t -cppe_lpbk_fifo_1_ctrl_set( - a_uint32_t dev_id, - a_uint32_t index, - union lpbk_fifo_1_ctrl_u *value) -{ - return hppe_reg_set( - dev_id, - NSS_MAC_CSR_BASE_ADDR + LPBK_FIFO_1_CTRL_ADDRESS + \ - index * LPBK_FIFO_1_CTRL_INC, - value->val); -} - -sw_error_t -cppe_lpbk_fifo_2_ctrl_get( - a_uint32_t dev_id, - a_uint32_t index, - union lpbk_fifo_2_ctrl_u *value) -{ - return hppe_reg_get( - dev_id, - NSS_MAC_CSR_BASE_ADDR + LPBK_FIFO_2_CTRL_ADDRESS + \ - index * LPBK_FIFO_2_CTRL_INC, - &value->val); -} - - -sw_error_t -cppe_lpbk_fifo_2_ctrl_set( - a_uint32_t dev_id, - a_uint32_t index, - union lpbk_fifo_2_ctrl_u *value) -{ - return hppe_reg_set( - dev_id, - NSS_MAC_CSR_BASE_ADDR + LPBK_FIFO_2_CTRL_ADDRESS + \ - index * LPBK_FIFO_2_CTRL_INC, - value->val); -} - -sw_error_t -cppe_lpbk_pps_ctrl_get( - a_uint32_t dev_id, - a_uint32_t index, - union lpbk_pps_ctrl_u *value) -{ - return hppe_reg_get( - dev_id, - NSS_MAC_CSR_BASE_ADDR + LPBK_PPS_CTRL_ADDRESS + \ - index * LPBK_PPS_CTRL_INC, - &value->val); -} - -sw_error_t -cppe_lpbk_pps_ctrl_set( - a_uint32_t dev_id, - a_uint32_t index, - union lpbk_pps_ctrl_u *value) -{ - return hppe_reg_set( - dev_id, - NSS_MAC_CSR_BASE_ADDR + LPBK_PPS_CTRL_ADDRESS + \ - index * LPBK_PPS_CTRL_INC, - value->val); -} - -sw_error_t -cppe_lpbk_mac_junmo_size_get( - a_uint32_t dev_id, - a_uint32_t index, - union lpbk_mac_junmo_size_u *value) -{ - return hppe_reg_get( - dev_id, - NSS_MAC_CSR_BASE_ADDR + LPBK_MAC_JUNMO_SIZE_ADDRESS + \ - index * LPBK_MAC_JUNMO_SIZE_INC, - &value->val); -} - -sw_error_t -cppe_lpbk_mac_junmo_size_set( - a_uint32_t dev_id, - a_uint32_t index, - union lpbk_mac_junmo_size_u *value) -{ - return hppe_reg_set( - dev_id, - NSS_MAC_CSR_BASE_ADDR + LPBK_MAC_JUNMO_SIZE_ADDRESS + \ - index * LPBK_MAC_JUNMO_SIZE_INC, - value->val); -} - -sw_error_t -cppe_lpbk_mib_ctrl_get( - a_uint32_t dev_id, - a_uint32_t index, - union lpbk_mib_ctrl_u *value) -{ - return hppe_reg_get( - dev_id, - NSS_MAC_CSR_BASE_ADDR + LPBK_MIB_CTRL_ADDRESS + \ - index * LPBK_MIB_CTRL_INC, - &value->val); -} - -sw_error_t -cppe_lpbk_mib_ctrl_set( - a_uint32_t dev_id, - a_uint32_t index, - union lpbk_mib_ctrl_u *value) -{ - return hppe_reg_set( - dev_id, - NSS_MAC_CSR_BASE_ADDR + LPBK_MIB_CTRL_ADDRESS + \ - index * LPBK_MIB_CTRL_INC, - value->val); -} - -sw_error_t -cppe_lpbk_mib_uni_get( - a_uint32_t dev_id, - a_uint32_t index, - union lpbkuni_u *value) -{ - return hppe_reg_get( - dev_id, - NSS_MAC_CSR_BASE_ADDR + LPBKUNI_ADDRESS + \ - index * LPBKUNI_INC, - &value->val); -} - -sw_error_t -cppe_lpbk_mib_multi_get( - a_uint32_t dev_id, - a_uint32_t index, - union lpbkmulti_u *value) -{ - return hppe_reg_get( - dev_id, - NSS_MAC_CSR_BASE_ADDR + LPBKMULTI_ADDRESS + \ - index * LPBKMULTI_INC, - &value->val); -} - -sw_error_t -cppe_lpbk_mib_broad_get( - a_uint32_t dev_id, - a_uint32_t index, - union lpbkbroad_u *value) -{ - return hppe_reg_get( - dev_id, - NSS_MAC_CSR_BASE_ADDR + LPBKBROAD_ADDRESS + \ - index * LPBKBROAD_INC, - &value->val); -} - -sw_error_t -cppe_lpbk_mib_pkt64_get( - a_uint32_t dev_id, - a_uint32_t index, - union lpbkpkt64_u *value) -{ - return hppe_reg_get( - dev_id, - NSS_MAC_CSR_BASE_ADDR + LPBKPKT64_ADDRESS + \ - index * LPBKPKT64_INC, - &value->val); - -} - -sw_error_t -cppe_lpbk_mib_pkt65to127_get( - a_uint32_t dev_id, - a_uint32_t index, - union lpbkpkt65to127_u *value) -{ - return hppe_reg_get( - dev_id, - NSS_MAC_CSR_BASE_ADDR + LPBKPKT65TO127_ADDRESS + \ - index * LPBKPKT65TO127_INC, - &value->val); -} - -sw_error_t -cppe_lpbk_mib_pkt128to255_get( - a_uint32_t dev_id, - a_uint32_t index, - union lpbkpkt128to255_u *value) -{ - return hppe_reg_get( - dev_id, - NSS_MAC_CSR_BASE_ADDR + LPBKPKT128TO255_ADDRESS + \ - index * LPBKPKT128TO255_INC, - &value->val); -} - -sw_error_t -cppe_lpbk_mib_pkt256to511_get( - a_uint32_t dev_id, - a_uint32_t index, - union lpbkpkt256to511_u *value) -{ - return hppe_reg_get( - dev_id, - NSS_MAC_CSR_BASE_ADDR + LPBKPKT256TO511_ADDRESS + \ - index * LPBKPKT256TO511_INC, - &value->val); -} - -sw_error_t -cppe_lpbk_mib_pkt512to1023_get( - a_uint32_t dev_id, - a_uint32_t index, - union lpbkpkt512to1023_u *value) -{ - return hppe_reg_get( - dev_id, - NSS_MAC_CSR_BASE_ADDR + LPBKPKT512TO1023_ADDRESS + \ - index * LPBKPKT512TO1023_INC, - &value->val); -} - -sw_error_t -cppe_lpbk_mib_pkt1024to1518_get( - a_uint32_t dev_id, - a_uint32_t index, - union lpbkpkt1024to1518_u *value) -{ - return hppe_reg_get( - dev_id, - NSS_MAC_CSR_BASE_ADDR + LPBKPKT1024TO1518_ADDRESS + \ - index * LPBKPKT1024TO1518_INC, - &value->val); -} - -sw_error_t -cppe_lpbk_mib_pkt1519tox_get( - a_uint32_t dev_id, - a_uint32_t index, - union lpbkpkt1519tox_u *value) -{ - return hppe_reg_get( - dev_id, - NSS_MAC_CSR_BASE_ADDR + LPBKPKT1519TOX_ADDRESS + \ - index * LPBKPKT1519TOX_INC, - &value->val); -} - -sw_error_t -cppe_lpbk_mib_toolong_get( - a_uint32_t dev_id, - a_uint32_t index, - union lpbkpkttoolong_u *value) -{ - return hppe_reg_get( - dev_id, - NSS_MAC_CSR_BASE_ADDR + LPBKPKTTOOLONG_ADDRESS + \ - index * LPBKPKTTOOLONG_INC, - &value->val); -} - -sw_error_t -cppe_lpbk_mib_byte_l_get( - a_uint32_t dev_id, - a_uint32_t index, - union lpbkbyte_l_u *value) -{ - return hppe_reg_get( - dev_id, - NSS_MAC_CSR_BASE_ADDR + LPBKBYTE_L_ADDRESS + \ - index * LPBKBYTE_L_INC, - &value->val); -} - -sw_error_t -cppe_lpbk_mib_byte_h_get( - a_uint32_t dev_id, - a_uint32_t index, - union lpbkbyte_h_u *value) -{ - return hppe_reg_get( - dev_id, - NSS_MAC_CSR_BASE_ADDR + LPBKBYTE_H_ADDRESS + \ - index * LPBKBYTE_H_INC, - &value->val); -} - -sw_error_t -cppe_lpbk_mib_drop_get( - a_uint32_t dev_id, - a_uint32_t index, - union lpbkdropcounter_u *value) -{ - return hppe_reg_get( - dev_id, - NSS_MAC_CSR_BASE_ADDR + LPBKDROPCOUNTER_ADDRESS + \ - index * LPBKDROPCOUNTER_INC, - &value->val); -} - -sw_error_t -cppe_lpbk_mib_tooshort_get( - a_uint32_t dev_id, - a_uint32_t index, - union lpbkpkttooshort_u *value) -{ - return hppe_reg_get( - dev_id, - NSS_MAC_CSR_BASE_ADDR + LPBKPKTTOOSHORT_ADDRESS + \ - index * LPBKPKTTOOSHORT_INC, - &value->val); -} - -sw_error_t -cppe_lpbk_mib_pkt14to63_get( - a_uint32_t dev_id, - a_uint32_t index, - union lpbkpkt14to63_u *value) -{ - return hppe_reg_get( - dev_id, - NSS_MAC_CSR_BASE_ADDR + LPBKPKT14TO63_ADDRESS + \ - index * LPBKPKT14TO63_INC, - &value->val); -} - -sw_error_t -cppe_lpbk_mib_toolongbyte_l_get( - a_uint32_t dev_id, - a_uint32_t index, - union lpbktoolongbyte_l_u *value) -{ - return hppe_reg_get( - dev_id, - NSS_MAC_CSR_BASE_ADDR + LPBKTOOLONGBYTE_L_ADDRESS + \ - index * LPBKTOOLONGBYTE_L_INC, - &value->val); -} - -sw_error_t -cppe_lpbk_mib_toolongbyte_h_get( - a_uint32_t dev_id, - a_uint32_t index, - union lpbktoolongbyte_h_u *value) -{ - return hppe_reg_get( - dev_id, - NSS_MAC_CSR_BASE_ADDR + LPBKTOOLONGBYTE_H_ADDRESS + \ - index * LPBKTOOLONGBYTE_H_INC, - &value->val); -} - -sw_error_t -cppe_lpbk_mib_tooshortbyte_l_get( - a_uint32_t dev_id, - a_uint32_t index, - union lpbktooshortbyte_l_u *value) -{ - return hppe_reg_get( - dev_id, - NSS_MAC_CSR_BASE_ADDR + LPBKTOOSHORTBYTE_L_ADDRESS + \ - index * LPBKTOOSHORTBYTE_L_INC, - &value->val); -} - -sw_error_t -cppe_lpbk_mib_tooshortbyte_h_get( - a_uint32_t dev_id, - a_uint32_t index, - union lpbktooshortbyte_h_u *value) -{ - return hppe_reg_get( - dev_id, - NSS_MAC_CSR_BASE_ADDR + LPBKTOOSHORTBYTE_H_ADDRESS + \ - index * LPBKTOOSHORTBYTE_H_INC, - &value->val); -} diff --git a/feeds/ipq807x/qca-ssdk/src/src/hsl/cppe/cppe_portctrl.c b/feeds/ipq807x/qca-ssdk/src/src/hsl/cppe/cppe_portctrl.c deleted file mode 100755 index 31ffb24d0..000000000 --- a/feeds/ipq807x/qca-ssdk/src/src/hsl/cppe/cppe_portctrl.c +++ /dev/null @@ -1,488 +0,0 @@ -/* - * Copyright (c) 2018-2019, The Linux Foundation. All rights reserved. - * Permission to use, copy, modify, and/or distribute this software for - * any purpose with or without fee is hereby granted, provided that the - * above copyright notice and this permission notice appear in all copies. - * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES - * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR - * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES - * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN - * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT - * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. - */ - - -/** - * @defgroup - * @{ - */ -#include "sw.h" -#include "hsl.h" -#include "hppe_reg_access.h" -#include "hppe_global_reg.h" -#include "cppe_portctrl_reg.h" -#include "cppe_portctrl.h" - -sw_error_t -cppe_mru_mtu_ctrl_tbl_get( - a_uint32_t dev_id, - a_uint32_t index, - union cppe_mru_mtu_ctrl_tbl_u *value) -{ - return hppe_reg_tbl_get( - dev_id, - IPE_L2_BASE_ADDR + CPPE_MRU_MTU_CTRL_TBL_ADDRESS + \ - index * CPPE_MRU_MTU_CTRL_TBL_INC, - value->val, - 2); -} - -sw_error_t -cppe_mru_mtu_ctrl_tbl_set( - a_uint32_t dev_id, - a_uint32_t index, - union cppe_mru_mtu_ctrl_tbl_u *value) -{ - return hppe_reg_tbl_set( - dev_id, - IPE_L2_BASE_ADDR + CPPE_MRU_MTU_CTRL_TBL_ADDRESS + \ - index * CPPE_MRU_MTU_CTRL_TBL_INC, - value->val, - 2); -} - -sw_error_t -cppe_mru_mtu_ctrl_tbl_dscp_res_prec_force_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union cppe_mru_mtu_ctrl_tbl_u reg_val; - sw_error_t ret = SW_OK; - - ret = cppe_mru_mtu_ctrl_tbl_get(dev_id, index, ®_val); - *value = reg_val.bf.dscp_res_prec_force; - return ret; -} - -sw_error_t -cppe_mru_mtu_ctrl_tbl_dscp_res_prec_force_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - union cppe_mru_mtu_ctrl_tbl_u reg_val; - sw_error_t ret = SW_OK; - - ret = cppe_mru_mtu_ctrl_tbl_get(dev_id, index, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.dscp_res_prec_force = value; - ret = cppe_mru_mtu_ctrl_tbl_set(dev_id, index, ®_val); - return ret; -} - -sw_error_t -cppe_mru_mtu_ctrl_tbl_pcp_res_prec_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union cppe_mru_mtu_ctrl_tbl_u reg_val; - sw_error_t ret = SW_OK; - - ret = cppe_mru_mtu_ctrl_tbl_get(dev_id, index, ®_val); - *value = reg_val.bf.pcp_res_prec; - return ret; -} - -sw_error_t -cppe_mru_mtu_ctrl_tbl_pcp_res_prec_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - union cppe_mru_mtu_ctrl_tbl_u reg_val; - sw_error_t ret = SW_OK; - - ret = cppe_mru_mtu_ctrl_tbl_get(dev_id, index, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.pcp_res_prec = value; - ret = cppe_mru_mtu_ctrl_tbl_set(dev_id, index, ®_val); - return ret; -} - -sw_error_t -cppe_mru_mtu_ctrl_tbl_pcp_qos_group_id_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union cppe_mru_mtu_ctrl_tbl_u reg_val; - sw_error_t ret = SW_OK; - - ret = cppe_mru_mtu_ctrl_tbl_get(dev_id, index, ®_val); - *value = reg_val.bf.pcp_qos_group_id; - return ret; -} - -sw_error_t -cppe_mru_mtu_ctrl_tbl_pcp_qos_group_id_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - union cppe_mru_mtu_ctrl_tbl_u reg_val; - sw_error_t ret = SW_OK; - - ret = cppe_mru_mtu_ctrl_tbl_get(dev_id, index, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.pcp_qos_group_id = value; - ret = cppe_mru_mtu_ctrl_tbl_set(dev_id, index, ®_val); - return ret; -} - -sw_error_t -cppe_mru_mtu_ctrl_tbl_pcp_res_prec_force_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union cppe_mru_mtu_ctrl_tbl_u reg_val; - sw_error_t ret = SW_OK; - - ret = cppe_mru_mtu_ctrl_tbl_get(dev_id, index, ®_val); - *value = reg_val.bf.pcp_res_prec_force; - return ret; -} - -sw_error_t -cppe_mru_mtu_ctrl_tbl_pcp_res_prec_force_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - union cppe_mru_mtu_ctrl_tbl_u reg_val; - sw_error_t ret = SW_OK; - - ret = cppe_mru_mtu_ctrl_tbl_get(dev_id, index, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.pcp_res_prec_force = value; - ret = cppe_mru_mtu_ctrl_tbl_set(dev_id, index, ®_val); - return ret; -} - -sw_error_t -cppe_mru_mtu_ctrl_tbl_post_acl_res_prec_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union cppe_mru_mtu_ctrl_tbl_u reg_val; - sw_error_t ret = SW_OK; - - ret = cppe_mru_mtu_ctrl_tbl_get(dev_id, index, ®_val); - *value = reg_val.bf.post_acl_res_prec; - return ret; -} - -sw_error_t -cppe_mru_mtu_ctrl_tbl_post_acl_res_prec_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - union cppe_mru_mtu_ctrl_tbl_u reg_val; - sw_error_t ret = SW_OK; - - ret = cppe_mru_mtu_ctrl_tbl_get(dev_id, index, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.post_acl_res_prec = value; - ret = cppe_mru_mtu_ctrl_tbl_set(dev_id, index, ®_val); - return ret; -} - -sw_error_t -cppe_mru_mtu_ctrl_tbl_preheader_res_prec_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union cppe_mru_mtu_ctrl_tbl_u reg_val; - sw_error_t ret = SW_OK; - - ret = cppe_mru_mtu_ctrl_tbl_get(dev_id, index, ®_val); - *value = reg_val.bf.preheader_res_prec; - return ret; -} - -sw_error_t -cppe_mru_mtu_ctrl_tbl_preheader_res_prec_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - union cppe_mru_mtu_ctrl_tbl_u reg_val; - sw_error_t ret = SW_OK; - - ret = cppe_mru_mtu_ctrl_tbl_get(dev_id, index, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.preheader_res_prec = value; - ret = cppe_mru_mtu_ctrl_tbl_set(dev_id, index, ®_val); - return ret; -} - -sw_error_t -cppe_mru_mtu_ctrl_tbl_dscp_res_prec_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union cppe_mru_mtu_ctrl_tbl_u reg_val; - sw_error_t ret = SW_OK; - - ret = cppe_mru_mtu_ctrl_tbl_get(dev_id, index, ®_val); - *value = reg_val.bf.dscp_res_prec; - return ret; -} - -sw_error_t -cppe_mru_mtu_ctrl_tbl_dscp_res_prec_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - union cppe_mru_mtu_ctrl_tbl_u reg_val; - sw_error_t ret = SW_OK; - - ret = cppe_mru_mtu_ctrl_tbl_get(dev_id, index, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.dscp_res_prec = value; - ret = cppe_mru_mtu_ctrl_tbl_set(dev_id, index, ®_val); - return ret; -} - -sw_error_t -cppe_mru_mtu_ctrl_tbl_pre_acl_res_prec_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union cppe_mru_mtu_ctrl_tbl_u reg_val; - sw_error_t ret = SW_OK; - - ret = cppe_mru_mtu_ctrl_tbl_get(dev_id, index, ®_val); - *value = reg_val.bf.pre_acl_res_prec; - return ret; -} - -sw_error_t -cppe_mru_mtu_ctrl_tbl_pre_acl_res_prec_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - union cppe_mru_mtu_ctrl_tbl_u reg_val; - sw_error_t ret = SW_OK; - - ret = cppe_mru_mtu_ctrl_tbl_get(dev_id, index, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.pre_acl_res_prec = value; - ret = cppe_mru_mtu_ctrl_tbl_set(dev_id, index, ®_val); - return ret; -} - -sw_error_t -cppe_mru_mtu_ctrl_tbl_flow_res_prec_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union cppe_mru_mtu_ctrl_tbl_u reg_val; - sw_error_t ret = SW_OK; - - ret = cppe_mru_mtu_ctrl_tbl_get(dev_id, index, ®_val); - *value = reg_val.bf.flow_res_prec; - return ret; -} - -sw_error_t -cppe_mru_mtu_ctrl_tbl_flow_res_prec_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - union cppe_mru_mtu_ctrl_tbl_u reg_val; - sw_error_t ret = SW_OK; - - ret = cppe_mru_mtu_ctrl_tbl_get(dev_id, index, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.flow_res_prec = value; - ret = cppe_mru_mtu_ctrl_tbl_set(dev_id, index, ®_val); - return ret; -} - -sw_error_t -cppe_mru_mtu_ctrl_tbl_dscp_qos_group_id_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union cppe_mru_mtu_ctrl_tbl_u reg_val; - sw_error_t ret = SW_OK; - - ret = cppe_mru_mtu_ctrl_tbl_get(dev_id, index, ®_val); - *value = reg_val.bf.dscp_qos_group_id; - return ret; -} - -sw_error_t -cppe_mru_mtu_ctrl_tbl_dscp_qos_group_id_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - union cppe_mru_mtu_ctrl_tbl_u reg_val; - sw_error_t ret = SW_OK; - - ret = cppe_mru_mtu_ctrl_tbl_get(dev_id, index, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.dscp_qos_group_id = value; - ret = cppe_mru_mtu_ctrl_tbl_set(dev_id, index, ®_val); - return ret; -} - -sw_error_t -cppe_mru_mtu_ctrl_tbl_src_profile_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union cppe_mru_mtu_ctrl_tbl_u reg_val; - sw_error_t ret = SW_OK; - - ret = cppe_mru_mtu_ctrl_tbl_get(dev_id, index, ®_val); - *value = reg_val.bf.src_profile; - return ret; -} - -sw_error_t -cppe_mru_mtu_ctrl_tbl_src_profile_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - union cppe_mru_mtu_ctrl_tbl_u reg_val; - sw_error_t ret = SW_OK; - - ret = cppe_mru_mtu_ctrl_tbl_get(dev_id, index, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.src_profile = value; - ret = cppe_mru_mtu_ctrl_tbl_set(dev_id, index, ®_val); - return ret; -} - -sw_error_t -cppe_mru_mtu_ctrl_tbl_source_filter_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - union cppe_mru_mtu_ctrl_tbl_u reg_val; - sw_error_t ret = SW_OK; - - ret = cppe_mru_mtu_ctrl_tbl_get(dev_id, index, ®_val); - if (SW_OK != ret) - { - return ret; - } - reg_val.bf.source_filtering_bypass = value; - ret = cppe_mru_mtu_ctrl_tbl_set(dev_id, index, ®_val); - - return ret; -} - -sw_error_t -cppe_mru_mtu_ctrl_tbl_source_filter_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union cppe_mru_mtu_ctrl_tbl_u reg_val; - sw_error_t ret = SW_OK; - - ret = cppe_mru_mtu_ctrl_tbl_get(dev_id, index, ®_val); - *value = reg_val.bf.source_filtering_bypass; - - return ret; -} - -sw_error_t -cppe_mru_mtu_ctrl_tbl_source_filter_mode_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - union cppe_mru_mtu_ctrl_tbl_u reg_val; - sw_error_t ret = SW_OK; - - ret = cppe_mru_mtu_ctrl_tbl_get(dev_id, index, ®_val); - if (SW_OK != ret) - { - return ret; - } - reg_val.bf.source_filtering_mode = value; - ret = cppe_mru_mtu_ctrl_tbl_set(dev_id, index, ®_val); - - return ret; -} - -sw_error_t -cppe_mru_mtu_ctrl_tbl_source_filter_mode_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union cppe_mru_mtu_ctrl_tbl_u reg_val; - sw_error_t ret = SW_OK; - - ret = cppe_mru_mtu_ctrl_tbl_get(dev_id, index, ®_val); - *value = reg_val.bf.source_filtering_mode; - - return ret; -} - -sw_error_t -cppe_port_phy_status_1_get( - a_uint32_t dev_id, - union cppe_port_phy_status_1_u *value) -{ - return hppe_reg_get( - dev_id, - NSS_GLOBAL_BASE_ADDR + PORT_PHY_STATUS_1_ADDRESS, - &value->val); -} - -sw_error_t -cppe_port5_pcs1_phy_status_get( - a_uint32_t dev_id, - a_uint32_t *value) -{ - union cppe_port_phy_status_1_u reg_val; - sw_error_t ret = SW_OK; - - ret = cppe_port_phy_status_1_get(dev_id, ®_val); - *value = reg_val.bf.port5_pcs1_phy_status; - return ret; -} diff --git a/feeds/ipq807x/qca-ssdk/src/src/hsl/cppe/cppe_qos.c b/feeds/ipq807x/qca-ssdk/src/src/hsl/cppe/cppe_qos.c deleted file mode 100755 index a91919226..000000000 --- a/feeds/ipq807x/qca-ssdk/src/src/hsl/cppe/cppe_qos.c +++ /dev/null @@ -1,428 +0,0 @@ -/* - * Copyright (c) 2018, The Linux Foundation. All rights reserved. - * Permission to use, copy, modify, and/or distribute this software for - * any purpose with or without fee is hereby granted, provided that the - * above copyright notice and this permission notice appear in all copies. - * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES - * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR - * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES - * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN - * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT - * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. - */ - - -/** - * @defgroup - * @{ - */ -#include "sw.h" -#include "hsl.h" -#include "hppe_reg_access.h" -#include "hppe_qos_reg.h" -#include "hppe_qos.h" -#include "cppe_qos_reg.h" - - -sw_error_t -cppe_qos_mapping_tbl_get( - a_uint32_t dev_id, - a_uint32_t index, - union qos_mapping_tbl_u *value) -{ - return hppe_reg_tbl_get( - dev_id, - IPE_L2_BASE_ADDR + QOS_MAPPING_TBL_ADDRESS + \ - index * QOS_MAPPING_TBL_INC, - value->val, - 2); -} - -sw_error_t -cppe_qos_mapping_tbl_set( - a_uint32_t dev_id, - a_uint32_t index, - union qos_mapping_tbl_u *value) -{ - return hppe_reg_tbl_set( - dev_id, - IPE_L2_BASE_ADDR + QOS_MAPPING_TBL_ADDRESS + \ - index * QOS_MAPPING_TBL_INC, - value->val, - 2); -} - -sw_error_t -cppe_qos_mapping_tbl_int_pcp_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union qos_mapping_tbl_u reg_val; - sw_error_t ret = SW_OK; - - ret = cppe_qos_mapping_tbl_get(dev_id, index, ®_val); - *value = reg_val.bf.int_pcp; - return ret; -} - -sw_error_t -cppe_qos_mapping_tbl_int_pcp_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - union qos_mapping_tbl_u reg_val; - sw_error_t ret = SW_OK; - - ret = cppe_qos_mapping_tbl_get(dev_id, index, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.int_pcp = value; - ret = cppe_qos_mapping_tbl_set(dev_id, index, ®_val); - return ret; -} - -sw_error_t -cppe_qos_mapping_tbl_int_dei_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union qos_mapping_tbl_u reg_val; - sw_error_t ret = SW_OK; - - ret = cppe_qos_mapping_tbl_get(dev_id, index, ®_val); - *value = reg_val.bf.int_dei; - return ret; -} - -sw_error_t -cppe_qos_mapping_tbl_int_dei_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - union qos_mapping_tbl_u reg_val; - sw_error_t ret = SW_OK; - - ret = cppe_qos_mapping_tbl_get(dev_id, index, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.int_dei = value; - ret = cppe_qos_mapping_tbl_set(dev_id, index, ®_val); - return ret; -} - -sw_error_t -cppe_qos_mapping_tbl_int_dei_en_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union qos_mapping_tbl_u reg_val; - sw_error_t ret = SW_OK; - - ret = cppe_qos_mapping_tbl_get(dev_id, index, ®_val); - *value = reg_val.bf.int_dei_en; - return ret; -} - -sw_error_t -cppe_qos_mapping_tbl_int_dei_en_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - union qos_mapping_tbl_u reg_val; - sw_error_t ret = SW_OK; - - ret = cppe_qos_mapping_tbl_get(dev_id, index, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.int_dei_en = value; - ret = cppe_qos_mapping_tbl_set(dev_id, index, ®_val); - return ret; -} - -sw_error_t -cppe_qos_mapping_tbl_dscp_tc_mask_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union qos_mapping_tbl_u reg_val; - sw_error_t ret = SW_OK; - - ret = cppe_qos_mapping_tbl_get(dev_id, index, ®_val); - *value = reg_val.bf.dscp_tc_mask; - return ret; -} - -sw_error_t -cppe_qos_mapping_tbl_dscp_tc_mask_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - union qos_mapping_tbl_u reg_val; - sw_error_t ret = SW_OK; - - ret = cppe_qos_mapping_tbl_get(dev_id, index, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.dscp_tc_mask = value; - ret = cppe_qos_mapping_tbl_set(dev_id, index, ®_val); - return ret; -} - -sw_error_t -cppe_qos_mapping_tbl_int_dscp_tc_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union qos_mapping_tbl_u reg_val; - sw_error_t ret = SW_OK; - - ret = cppe_qos_mapping_tbl_get(dev_id, index, ®_val); - *value = reg_val.bf.int_dscp_tc; - return ret; -} - -sw_error_t -cppe_qos_mapping_tbl_int_dscp_tc_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - union qos_mapping_tbl_u reg_val; - sw_error_t ret = SW_OK; - - ret = cppe_qos_mapping_tbl_get(dev_id, index, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.int_dscp_tc = value; - ret = cppe_qos_mapping_tbl_set(dev_id, index, ®_val); - return ret; -} - -sw_error_t -cppe_qos_mapping_tbl_int_dp_en_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union qos_mapping_tbl_u reg_val; - sw_error_t ret = SW_OK; - - ret = cppe_qos_mapping_tbl_get(dev_id, index, ®_val); - *value = reg_val.bf.int_dp_en; - return ret; -} - -sw_error_t -cppe_qos_mapping_tbl_int_dp_en_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - union qos_mapping_tbl_u reg_val; - sw_error_t ret = SW_OK; - - ret = cppe_qos_mapping_tbl_get(dev_id, index, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.int_dp_en = value; - ret = cppe_qos_mapping_tbl_set(dev_id, index, ®_val); - return ret; -} - -sw_error_t -cppe_qos_mapping_tbl_int_dp_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union qos_mapping_tbl_u reg_val; - sw_error_t ret = SW_OK; - - ret = cppe_qos_mapping_tbl_get(dev_id, index, ®_val); - *value = reg_val.bf.int_dp; - return ret; -} - -sw_error_t -cppe_qos_mapping_tbl_int_dp_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - union qos_mapping_tbl_u reg_val; - sw_error_t ret = SW_OK; - - ret = cppe_qos_mapping_tbl_get(dev_id, index, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.int_dp = value; - ret = cppe_qos_mapping_tbl_set(dev_id, index, ®_val); - return ret; -} - -sw_error_t -cppe_qos_mapping_tbl_int_pri_en_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union qos_mapping_tbl_u reg_val; - sw_error_t ret = SW_OK; - - ret = cppe_qos_mapping_tbl_get(dev_id, index, ®_val); - *value = reg_val.bf.int_pri_en; - return ret; -} - -sw_error_t -cppe_qos_mapping_tbl_int_pri_en_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - union qos_mapping_tbl_u reg_val; - sw_error_t ret = SW_OK; - - ret = cppe_qos_mapping_tbl_get(dev_id, index, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.int_pri_en = value; - ret = cppe_qos_mapping_tbl_set(dev_id, index, ®_val); - return ret; -} - -sw_error_t -cppe_qos_mapping_tbl_qos_res_prec_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union qos_mapping_tbl_u reg_val; - sw_error_t ret = SW_OK; - - ret = cppe_qos_mapping_tbl_get(dev_id, index, ®_val); - *value = reg_val.bf.qos_res_prec_1 << 1 | \ - reg_val.bf.qos_res_prec_0; - return ret; -} - -sw_error_t -cppe_qos_mapping_tbl_qos_res_prec_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - union qos_mapping_tbl_u reg_val; - sw_error_t ret = SW_OK; - - ret = cppe_qos_mapping_tbl_get(dev_id, index, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.qos_res_prec_1 = value >> 1; - reg_val.bf.qos_res_prec_0 = value & (((a_uint64_t)1<<1)-1); - ret = cppe_qos_mapping_tbl_set(dev_id, index, ®_val); - return ret; -} - -sw_error_t -cppe_qos_mapping_tbl_int_pcp_en_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union qos_mapping_tbl_u reg_val; - sw_error_t ret = SW_OK; - - ret = cppe_qos_mapping_tbl_get(dev_id, index, ®_val); - *value = reg_val.bf.int_pcp_en; - return ret; -} - -sw_error_t -cppe_qos_mapping_tbl_int_pcp_en_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - union qos_mapping_tbl_u reg_val; - sw_error_t ret = SW_OK; - - ret = cppe_qos_mapping_tbl_get(dev_id, index, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.int_pcp_en = value; - ret = cppe_qos_mapping_tbl_set(dev_id, index, ®_val); - return ret; -} - -sw_error_t -cppe_qos_mapping_tbl_int_pri_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union qos_mapping_tbl_u reg_val; - sw_error_t ret = SW_OK; - - ret = cppe_qos_mapping_tbl_get(dev_id, index, ®_val); - *value = reg_val.bf.int_pri; - return ret; -} - -sw_error_t -cppe_qos_mapping_tbl_int_pri_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - union qos_mapping_tbl_u reg_val; - sw_error_t ret = SW_OK; - - ret = cppe_qos_mapping_tbl_get(dev_id, index, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.int_pri = value; - ret = cppe_qos_mapping_tbl_set(dev_id, index, ®_val); - return ret; -} - -sw_error_t -cppe_qos_mapping_tbl_int_dscp_en_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union qos_mapping_tbl_u reg_val; - sw_error_t ret = SW_OK; - - ret = cppe_qos_mapping_tbl_get(dev_id, index, ®_val); - *value = reg_val.bf.int_dscp_en; - return ret; -} - -sw_error_t -cppe_qos_mapping_tbl_int_dscp_en_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - union qos_mapping_tbl_u reg_val; - sw_error_t ret = SW_OK; - - ret = cppe_qos_mapping_tbl_get(dev_id, index, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.int_dscp_en = value; - ret = cppe_qos_mapping_tbl_set(dev_id, index, ®_val); - return ret; -} \ No newline at end of file diff --git a/feeds/ipq807x/qca-ssdk/src/src/hsl/dess/Makefile b/feeds/ipq807x/qca-ssdk/src/src/hsl/dess/Makefile deleted file mode 100755 index c79a503e0..000000000 --- a/feeds/ipq807x/qca-ssdk/src/src/hsl/dess/Makefile +++ /dev/null @@ -1,114 +0,0 @@ -LOC_DIR=src/hsl/dess -LIB=HSL - -include $(PRJ_PATH)/make/config.mk - -SRC_LIST=dess_reg_access.c dess_init.c - -ifeq (TRUE, $(IN_ACL)) - SRC_LIST += dess_acl.c dess_acl_parse.c dess_multicast_acl.c -endif - -ifeq (TRUE, $(IN_FDB)) - SRC_LIST += dess_fdb.c -endif - -ifeq (TRUE, $(IN_IGMP)) - SRC_LIST += dess_igmp.c -endif - -ifeq (TRUE, $(IN_LEAKY)) - SRC_LIST += dess_leaky.c -endif - -ifeq (TRUE, $(IN_LED)) - SRC_LIST += dess_led.c -endif - -ifeq (TRUE, $(IN_MIB)) - SRC_LIST += dess_mib.c -endif - -ifeq (TRUE, $(IN_MIRROR)) - SRC_LIST += dess_mirror.c -endif - -ifeq (TRUE, $(IN_MISC)) - SRC_LIST += dess_misc.c -endif - -ifeq (TRUE, $(IN_PORTCONTROL)) - SRC_LIST += dess_port_ctrl.c -endif - -ifeq (TRUE, $(IN_PORTVLAN)) - SRC_LIST += dess_portvlan.c -endif - -ifeq (TRUE, $(IN_QOS)) - SRC_LIST += dess_qos.c -endif - -ifeq (TRUE, $(IN_RATE)) - SRC_LIST += dess_rate.c -endif - -ifeq (TRUE, $(IN_STP)) - SRC_LIST += dess_stp.c -endif - -ifeq (TRUE, $(IN_VLAN)) - SRC_LIST += dess_vlan.c -endif - -ifeq (TRUE, $(IN_COSMAP)) - SRC_LIST += dess_cosmap.c -endif - -ifeq (TRUE, $(IN_IP)) - SRC_LIST += dess_ip.c -endif - -ifeq (TRUE, $(IN_NAT)) - SRC_LIST += dess_nat.c -endif - -ifeq (TRUE, $(IN_NAT_HELPER)) - SRC_LIST += nat_helper_dt.c - SRC_LIST += nat_helper_hsl.c - SRC_LIST += nat_ipt_helper.c - SRC_LIST += napt_helper.c - SRC_LIST += host_helper.c - SRC_LIST += nat_helper.c - SRC_LIST += napt_acl.c -endif - -ifeq (TRUE, $(IN_TRUNK)) - SRC_LIST += dess_trunk.c -endif - -ifeq (TRUE, $(IN_SEC)) - SRC_LIST += dess_sec.c -endif - -ifeq (TRUE, $(IN_INTERFACECONTROL)) - SRC_LIST += dess_interface_ctrl.c dess_psgmii.c -endif - -ifeq (linux, $(OS)) - ifeq (KSLIB, $(MODULE_TYPE)) - ifneq (TRUE, $(KERNEL_MODE)) - SRC_LIST=dess_reg_access.c dess_init.c - endif - endif -endif - -ifeq (, $(findstring DESS, $(SUPPORT_CHIP))) - SRC_LIST= -endif - -include $(PRJ_PATH)/make/components.mk -include $(PRJ_PATH)/make/defs.mk -include $(PRJ_PATH)/make/target.mk - -all: dep obj diff --git a/feeds/ipq807x/qca-ssdk/src/src/hsl/dess/dess_acl.c b/feeds/ipq807x/qca-ssdk/src/src/hsl/dess/dess_acl.c deleted file mode 100755 index 9783ac4ad..000000000 --- a/feeds/ipq807x/qca-ssdk/src/src/hsl/dess/dess_acl.c +++ /dev/null @@ -1,2039 +0,0 @@ -/* - * Copyright (c) 2014, 2016, 2018, The Linux Foundation. All rights reserved. - * Permission to use, copy, modify, and/or distribute this software for - * any purpose with or without fee is hereby granted, provided that the - * above copyright notice and this permission notice appear in all copies. - * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES - * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR - * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES - * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN - * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT - * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. - */ - - -/** - * @defgroup dess_acl DESS_ACL - * @{ - */ -#include "sw.h" -#include "hsl.h" -#include "hsl_dev.h" -#include "hsl_acl.h" -#include "dess_acl.h" -#include "dess_reg.h" -#include "dess_acl_prv.h" - -//#define DESS_ACL_DEBUG -//#define DESS_SW_ENTRY -#define DESS_HW_ENTRY - -static dess_acl_list_t *sw_list_ent[SW_MAX_NR_DEV]; -static dess_acl_rule_t *sw_rule_ent[SW_MAX_NR_DEV]; - -static dess_acl_rule_t *sw_rule_tmp[SW_MAX_NR_DEV]; -static dess_acl_rule_t *hw_rule_tmp[SW_MAX_NR_DEV]; -#ifdef DESS_SW_ENTRY -static a_uint8_t *sw_filter_mem = NULL; -#endif - -static sw_error_t -_dess_filter_valid_set(a_uint32_t dev_id, a_uint32_t flt_idx, a_uint32_t flag); - -#ifndef DESS_SW_ENTRY -#ifndef DESS_HW_ENTRY -static sw_error_t -_dess_filter_ports_bind(a_uint32_t dev_id, a_uint32_t flt_idx, - a_uint32_t ports); - -static sw_error_t -_dess_filter_write(a_uint32_t dev_id, a_uint32_t reg[], a_uint32_t flt_idx, - a_uint32_t op); -#endif -#endif - -//static sw_error_t -//_dess_filter_read(a_uint32_t dev_id, a_uint32_t reg[], a_uint32_t flt_idx, -// a_uint32_t op); - -static sw_error_t -_dess_filter_down_to_hw(a_uint32_t dev_id, hw_filter_t * filter, - a_uint32_t flt_idx); - -static sw_error_t -_dess_filter_up_to_sw(a_uint32_t dev_id, hw_filter_t * filter, - a_uint32_t flt_idx); - -static sw_error_t -_dess_acl_rule_src_filter_sts_set(a_uint32_t dev_id, - a_uint32_t rule_id, a_bool_t enable); - -static void -_dess_acl_list_dump(a_uint32_t dev_id) -{ - a_uint32_t i; - dess_acl_list_t *sw_list; - - aos_printk("\ndev_id=%d list control infomation:", dev_id); - for (i = 0; i < DESS_MAX_FILTER; i++) - { - sw_list = &(sw_list_ent[dev_id][i]); - if (ENT_USED & sw_list->status) - { - aos_printk - ("\nlist_id=%02d list_pri=%02d rule_nr=%02d [pts_map]:0x%02x idx=%02d ", - sw_list->list_id, sw_list->list_pri, sw_list->rule_nr, - sw_list->bind_pts, i); - } - } - aos_printk("\n"); -} - -static void -_dess_acl_sw_rule_dump(char *info, dess_acl_rule_t * sw_rule) -{ -#ifdef DESS_ACL_DEBUG - a_uint32_t flt_idx, i; - - aos_printk("\n%s", info); - for (flt_idx = 0; flt_idx < DESS_MAX_FILTER; flt_idx++) - { - aos_printk("\n%d software filter:", flt_idx); - aos_printk("\nact:"); - for (i = 0; i < 3; i++) - { - aos_printk("%08x ", sw_rule[flt_idx].filter.act[i]); - } - - aos_printk("\nvlu:"); - for (i = 0; i < 5; i++) - { - aos_printk("%08x ", sw_rule[flt_idx].filter.vlu[i]); - } - - aos_printk("\nmsk:"); - for (i = 0; i < 5; i++) - { - aos_printk("%08x ", sw_rule[flt_idx].filter.msk[i]); - } - - aos_printk("\nctl:status[%02d] list_id[%02d] rule_id[%02d]", - sw_rule[flt_idx].status, - sw_rule[flt_idx].list_id, sw_rule[flt_idx].rule_id); - - aos_printk("\n\n"); - } -#else - return; -#endif -} - -static dess_acl_list_t * -_dess_acl_list_loc(a_uint32_t dev_id, a_uint32_t list_id) -{ - a_uint32_t i; - - for (i = 0; i < DESS_MAX_FILTER; i++) - { - if ((ENT_USED & sw_list_ent[dev_id][i].status) - && (list_id == sw_list_ent[dev_id][i].list_id)) - { - return &(sw_list_ent[dev_id][i]); - } - } - return NULL; -} - -static sw_error_t -_dess_filter_valid_set(a_uint32_t dev_id, a_uint32_t flt_idx, a_uint32_t flag) -{ -#ifdef DESS_SW_ENTRY - hw_filter_t filter; - - _dess_filter_up_to_sw(dev_id, &filter, flt_idx); - - filter.msk[4] &= 0xfffffff8; - filter.msk[4] |= (flag & 0x7); - - _dess_filter_down_to_hw(dev_id, &filter, flt_idx); - - return SW_OK; -#else -#ifdef DESS_HW_ENTRY - hw_filter_t filter; - - filter = sw_rule_ent[dev_id][flt_idx].filter; - - filter.msk[4] &= 0xfffffff8; - filter.msk[4] |= (flag & 0x7); - - _dess_filter_down_to_hw(dev_id, &filter, flt_idx); - return SW_OK; -#else - sw_error_t rv; - a_uint32_t addr, data = 0; - - /* read filter mask at first */ - addr = DESS_RULE_FUNC_ADDR; - data = (flt_idx & 0x7f) | (0x1 << 8) | (0x1 << 10) | (0x1 << 31); - HSL_REG_ENTRY_GEN_SET(rv, dev_id, addr, sizeof (a_uint32_t), - (a_uint8_t *) (&data), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - - /* get filter mask and modify it */ - addr = DESS_RULE_FUNC_ADDR + 20; - HSL_REG_ENTRY_GEN_GET(rv, dev_id, addr, sizeof (a_uint32_t), - (a_uint8_t *) (&data), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - - data &= 0xfffffff8; - data |= (flag & 0x7); - HSL_REG_ENTRY_GEN_SET(rv, dev_id, addr, sizeof (a_uint32_t), - (a_uint8_t *) (&data), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - - /* write back filter mask */ - addr = DESS_RULE_FUNC_ADDR; - data = (flt_idx & 0x7f) | (0x1 << 8) | (0x1 << 31); - HSL_REG_ENTRY_GEN_SET(rv, dev_id, addr, sizeof (a_uint32_t), - (a_uint8_t *) (&data), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - - return SW_OK; -#endif -#endif -} - -static sw_error_t -_dess_filter_ports_bind(a_uint32_t dev_id, a_uint32_t flt_idx, a_uint32_t ports) -{ -#ifdef DESS_SW_ENTRY - hw_filter_t filter; - - _dess_filter_up_to_sw(dev_id, &filter, flt_idx); - - filter.vlu[4] &= 0xffffff80; - filter.vlu[4] |= (ports & 0x7f); - - _dess_filter_down_to_hw(dev_id, &filter, flt_idx); - - return SW_OK; -#else -#ifdef DESS_HW_ENTRY - hw_filter_t filter; - - filter = sw_rule_ent[dev_id][flt_idx].filter; - - filter.vlu[4] &= 0xffffff80; - filter.vlu[4] |= (ports & 0x7f); - - _dess_filter_down_to_hw(dev_id, &filter, flt_idx); - - return SW_OK; -#else - sw_error_t rv; - a_uint32_t addr, data; - - /* read filter value at first */ - addr = DESS_RULE_FUNC_ADDR; - data = (flt_idx & 0x7f) | (0x1 << 10) | (0x1 << 31); - HSL_REG_ENTRY_GEN_SET(rv, dev_id, addr, sizeof (a_uint32_t), - (a_uint8_t *) (&data), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - - /* get filter value and modify it */ - addr = DESS_RULE_FUNC_ADDR + 20; - HSL_REG_ENTRY_GEN_GET(rv, dev_id, addr, sizeof (a_uint32_t), - (a_uint8_t *) (&data), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - - data &= 0xffffff80; - data |= (ports & 0x7f); - HSL_REG_ENTRY_GEN_SET(rv, dev_id, addr, sizeof (a_uint32_t), - (a_uint8_t *) (&data), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - - /* write back filter value */ - addr = DESS_RULE_FUNC_ADDR; - data = (flt_idx & 0x7f) | (0x1 << 31); - HSL_REG_ENTRY_GEN_SET(rv, dev_id, addr, sizeof (a_uint32_t), - (a_uint8_t *) (&data), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - - return SW_OK; -#endif -#endif -} - -#ifndef DESS_SW_ENTRY -#ifndef DESS_HW_ENTRY -static sw_error_t -_dess_filter_write(a_uint32_t dev_id, a_uint32_t reg[], a_uint32_t flt_idx, - a_uint32_t op) -{ - a_uint32_t i, addr, data, idx = 6; - sw_error_t rv; - - if (DESS_FILTER_ACT_OP == op) - { - idx = 4; - } - - for (i = 1; i < idx; i++) - { - addr = DESS_RULE_FUNC_ADDR + (i << 2); - HSL_REG_ENTRY_GEN_SET(rv, dev_id, addr, sizeof (a_uint32_t), - (a_uint8_t *) (&(reg[i - 1])), - sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - } - - addr = DESS_RULE_FUNC_ADDR; - data = (flt_idx & 0x7f) | (op << 8) | (0x1 << 31); - HSL_REG_ENTRY_GEN_SET(rv, dev_id, addr, sizeof (a_uint32_t), - (a_uint8_t *) (&data), sizeof (a_uint32_t)); - - return rv; -} - -static sw_error_t -_dess_filter_read(a_uint32_t dev_id, a_uint32_t reg[], a_uint32_t flt_idx, - a_uint32_t op) -{ - a_uint32_t i, addr, data, idx = 6; - sw_error_t rv; - - addr = DESS_RULE_FUNC_ADDR; - data = (flt_idx & 0x7f) | (op << 8) | (0x1 << 10) | (0x1 << 31); - HSL_REG_ENTRY_GEN_SET(rv, dev_id, addr, sizeof (a_uint32_t), - (a_uint8_t *) (&data), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - - if (DESS_FILTER_ACT_OP == op) - { - idx = 4; - } - - for (i = 1; i < idx; i++) - { - addr = DESS_RULE_FUNC_ADDR + (i << 2); - HSL_REG_ENTRY_GEN_GET(rv, dev_id, addr, sizeof (a_uint32_t), - (a_uint8_t *) (&(reg[i - 1])), - sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - } - - return SW_OK; -} -#endif -#endif - -static sw_error_t -_dess_filter_down_to_hw(a_uint32_t dev_id, hw_filter_t * filter, - a_uint32_t flt_idx) -{ -#ifdef DESS_SW_ENTRY - a_uint8_t *tbl = sw_filter_mem + sizeof (hw_filter_t) * flt_idx; - - aos_mem_copy(tbl, filter, sizeof (hw_filter_t)); -#else -#ifdef DESS_HW_ENTRY - sw_error_t rv; - a_uint32_t i, base, addr; - - base = DESS_FILTER_ACT_ADDR + (flt_idx << 4); - for (i = 0; i < 3; i++) - { - addr = base + (i << 2); - HSL_REG_ENTRY_GEN_SET(rv, dev_id, addr, sizeof (a_uint32_t), - (a_uint8_t *) (&(filter->act[i])), - sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - } - - base = DESS_FILTER_VLU_ADDR + (flt_idx << 5); - for (i = 0; i < 5; i++) - { - addr = base + (i << 2); - HSL_REG_ENTRY_GEN_SET(rv, dev_id, addr, sizeof (a_uint32_t), - (a_uint8_t *) (&(filter->vlu[i])), - sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - } - - base = DESS_FILTER_MSK_ADDR + (flt_idx << 5); - for (i = 0; i < 5; i++) - { - addr = base + (i << 2); - HSL_REG_ENTRY_GEN_SET(rv, dev_id, addr, sizeof (a_uint32_t), - (a_uint8_t *) (&(filter->msk[i])), - sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - } -#else - sw_error_t rv; - - rv = _dess_filter_write(dev_id, &(filter->act[0]), flt_idx, - DESS_FILTER_ACT_OP); - SW_RTN_ON_ERROR(rv); - - rv = _dess_filter_write(dev_id, &(filter->vlu[0]), flt_idx, - DESS_FILTER_VLU_OP); - SW_RTN_ON_ERROR(rv); - - rv = _dess_filter_write(dev_id, &(filter->msk[0]), flt_idx, - DESS_FILTER_MSK_OP); - SW_RTN_ON_ERROR(rv); -#endif -#endif - - return SW_OK; -} - -static sw_error_t -_dess_filter_up_to_sw(a_uint32_t dev_id, hw_filter_t * filter, - a_uint32_t flt_idx) -{ -#ifdef DESS_SW_ENTRY - a_uint8_t *tbl = sw_filter_mem + sizeof (hw_filter_t) * flt_idx; - - aos_mem_copy(filter, tbl, sizeof (hw_filter_t)); -#else -#ifdef DESS_HW_ENTRY - sw_error_t rv; - a_uint32_t i, base, addr; - - base = DESS_FILTER_VLU_ADDR + (flt_idx << 5); - for (i = 0; i < 5; i++) - { - addr = base + (i << 2); - HSL_REG_ENTRY_GEN_GET(rv, dev_id, addr, sizeof (a_uint32_t), - (a_uint8_t *) (&(filter->vlu[i])), - sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - } - - base = DESS_FILTER_MSK_ADDR + (flt_idx << 5); - for (i = 0; i < 5; i++) - { - addr = base + (i << 2); - HSL_REG_ENTRY_GEN_GET(rv, dev_id, addr, sizeof (a_uint32_t), - (a_uint8_t *) (&(filter->msk[i])), - sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - } - - base = DESS_FILTER_ACT_ADDR + (flt_idx << 4); - for (i = 0; i < 3; i++) - { - addr = base + (i << 2); - HSL_REG_ENTRY_GEN_GET(rv, dev_id, addr, sizeof (a_uint32_t), - (a_uint8_t *) (&(filter->act[i])), - sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - } -#else - sw_error_t rv; - - rv = _dess_filter_read(dev_id, &(filter->vlu[0]), flt_idx, - DESS_FILTER_VLU_OP); - SW_RTN_ON_ERROR(rv); - - rv = _dess_filter_read(dev_id, &(filter->msk[0]), flt_idx, - DESS_FILTER_MSK_OP); - SW_RTN_ON_ERROR(rv); - - rv = _dess_filter_read(dev_id, &(filter->act[0]), flt_idx, - DESS_FILTER_ACT_OP); - SW_RTN_ON_ERROR(rv); -#endif -#endif - - return SW_OK; -} - -static sw_error_t -_dess_acl_list_insert(a_uint32_t dev_id, a_uint32_t * src_idx, - a_uint32_t * dst_idx, dess_acl_rule_t * src_rule, - dess_acl_rule_t * dst_rule) -{ - a_uint32_t i, data, rule_id, list_id, list_pri; - - rule_id = 0; - list_id = src_rule[*src_idx].list_id; - list_pri = src_rule[*src_idx].list_pri; - - for (i = *src_idx; i < DESS_MAX_FILTER; i++) - { - if (!(ENT_USED & src_rule[i].status)) - { - continue; // was: break; - } - - if (src_rule[i].list_id != list_id) - { - break; - } - - SW_GET_FIELD_BY_REG(MAC_RUL_M4, RULE_TYP, data, - src_rule[i].filter.msk[4]); - if (!data) - { - continue; - } - - if (DESS_MAX_FILTER <= *dst_idx) - { - return SW_NO_RESOURCE; - } - - if (ENT_USED & dst_rule[*dst_idx].status) - { - return SW_NO_RESOURCE; - } - - SW_GET_FIELD_BY_REG(MAC_RUL_M4, RULE_VALID, data, - src_rule[i].filter.msk[4]); - if ((FLT_START == data) && (*dst_idx % 2)) - { - if (*src_idx != i) - { - dst_rule[*dst_idx].src_flt_dis = src_rule[i].src_flt_dis; - dst_rule[*dst_idx].list_id = list_id; - dst_rule[*dst_idx].list_pri = list_pri; - dst_rule[*dst_idx].rule_id = rule_id - 1; - dst_rule[*dst_idx].status |= ENT_USED; - } - - (*dst_idx)++; - if (DESS_MAX_FILTER <= *dst_idx) - { - return SW_NO_RESOURCE; - } - - if (ENT_USED & dst_rule[*dst_idx].status) - { - return SW_NO_RESOURCE; - } - } - - aos_mem_copy(&(dst_rule[*dst_idx].filter), &(src_rule[i].filter), - sizeof (hw_filter_t)); - dst_rule[*dst_idx].src_flt_dis = src_rule[i].src_flt_dis; - dst_rule[*dst_idx].list_id = list_id; - dst_rule[*dst_idx].list_pri = list_pri; - dst_rule[*dst_idx].rule_id = rule_id; - dst_rule[*dst_idx].status |= ENT_USED; - if (ENT_DEACTIVE & src_rule[i].status) - { - dst_rule[*dst_idx].status |= ENT_DEACTIVE; - } - (*dst_idx)++; - - if ((FLT_END == data) && (*dst_idx % 2)) - { - if (DESS_MAX_FILTER > *dst_idx) - { - dst_rule[*dst_idx].src_flt_dis = src_rule[i].src_flt_dis; - dst_rule[*dst_idx].list_id = list_id; - dst_rule[*dst_idx].list_pri = list_pri; - dst_rule[*dst_idx].rule_id = rule_id; - dst_rule[*dst_idx].status |= ENT_USED; - (*dst_idx)++; - } - } - - if ((FLT_END == data) || (FLT_STARTEND == data)) - { - rule_id++; - } - } - - *src_idx = i; - return SW_OK; -} - -static sw_error_t -_dess_acl_rule_alloc(a_uint32_t dev_id, dess_acl_list_t * sw_list, - a_uint32_t filter_nr) -{ - a_uint32_t free_flt_nr, load_idx, begin_idx, start_idx, end_idx, i; - a_uint32_t largest_nr, largest_idx; - sw_error_t rv; - - /* calculate the proper location, [start_idx, end_idx) */ - start_idx = 0; - end_idx = DESS_MAX_FILTER; - for (i = 0; i < DESS_MAX_FILTER; i++) - { - if (ENT_USED & sw_rule_ent[dev_id][i].status) - { - if (sw_rule_ent[dev_id][i].list_pri < sw_list->list_pri) - { - start_idx = i + 1; - } - else if (sw_rule_ent[dev_id][i].list_pri > sw_list->list_pri) - { - end_idx = i; - break; - } - } - } - - /* find the larget free filters block */ - largest_nr = 0; - largest_idx = 0; - free_flt_nr = 0; - begin_idx = start_idx; - for (i = start_idx; i < end_idx; i++) - { - if (!(ENT_USED & sw_rule_ent[dev_id][i].status)) - { - free_flt_nr++; - } - else - { - if (free_flt_nr > largest_nr) - { - largest_nr = free_flt_nr; - largest_idx = begin_idx; - } - free_flt_nr = 0; - begin_idx = i + 1; - } - } - - if (free_flt_nr > largest_nr) - { - largest_nr = free_flt_nr; - largest_idx = begin_idx; - } - - if ((!largest_nr) || ((largest_nr + 1) < filter_nr)) - { - return SW_NO_RESOURCE; - } - - for (i = 0; i < DESS_MAX_FILTER; i++) - { - if (ENT_USED & sw_rule_ent[dev_id][i].status) - { - aos_mem_copy(&(sw_rule_tmp[dev_id][i]), &(sw_rule_ent[dev_id][i]), - sizeof (dess_acl_rule_t)); - } - } - - begin_idx = 0; - load_idx = largest_idx; - rv = _dess_acl_list_insert(dev_id, &begin_idx, &load_idx, - hw_rule_tmp[dev_id], sw_rule_tmp[dev_id]); - return rv; -} - -static sw_error_t -_dess_acl_rule_reorder(a_uint32_t dev_id, dess_acl_list_t * sw_list) -{ - a_uint32_t i, src_idx, dst_idx; - sw_error_t rv; - - dst_idx = 0; - for (i = 0; i < DESS_MAX_FILTER;) - { - if (ENT_USED & sw_rule_ent[dev_id][i].status) - { - if (sw_rule_ent[dev_id][i].list_pri <= sw_list->list_pri) - { - rv = _dess_acl_list_insert(dev_id, &i, &dst_idx, - sw_rule_ent[dev_id], - sw_rule_tmp[dev_id]); - SW_RTN_ON_ERROR(rv); - } - else - { - break; - } - } - else - { - i++; - } - } - - src_idx = 0; - rv = _dess_acl_list_insert(dev_id, &src_idx, &dst_idx, hw_rule_tmp[dev_id], - sw_rule_tmp[dev_id]); - SW_RTN_ON_ERROR(rv); - - for (; i < DESS_MAX_FILTER;) - { - if (ENT_USED & sw_rule_ent[dev_id][i].status) - { - rv = _dess_acl_list_insert(dev_id, &i, &dst_idx, - sw_rule_ent[dev_id], - sw_rule_tmp[dev_id]); - SW_RTN_ON_ERROR(rv); - } - else - { - i++; - } - } - - return SW_OK; -} - -static void -_dess_acl_rule_sync(a_uint32_t dev_id, a_uint32_t flt_idx, a_uint32_t flt_nr) -{ - a_uint32_t i, data; - - for (i = flt_idx; i < (flt_idx + flt_nr); i++) - { - if (aos_mem_cmp - (&(sw_rule_ent[dev_id][i]), &(sw_rule_tmp[dev_id][i]), - sizeof (dess_acl_rule_t))) - { - SW_GET_FIELD_BY_REG(MAC_RUL_M4, RULE_TYP, data, - sw_rule_tmp[dev_id][i].filter.msk[4]); - if (data) - { - _dess_filter_down_to_hw(dev_id, - &(sw_rule_tmp[dev_id][i].filter), i); - } - else - { - _dess_filter_valid_set(dev_id, i, 0); - } - - aos_mem_copy(&(sw_rule_ent[dev_id][i]), &(sw_rule_tmp[dev_id][i]), - sizeof (dess_acl_rule_t)); - _dess_acl_rule_src_filter_sts_set(dev_id, i, - !sw_rule_tmp[dev_id][i].src_flt_dis); - } - } -} - -static sw_error_t -_dess_acl_list_creat(a_uint32_t dev_id, a_uint32_t list_id, a_uint32_t list_pri) -{ - a_uint32_t i, loc = DESS_MAX_FILTER; - dess_acl_list_t *sw_list; - - HSL_DEV_ID_CHECK(dev_id); - - if ((DESS_MAX_LIST_ID < list_id) || (DESS_MAX_LIST_PRI < list_pri)) - { - return SW_NOT_SUPPORTED; - } - - for (i = 0; i < DESS_MAX_FILTER; i++) - { - sw_list = &(sw_list_ent[dev_id][i]); - if (ENT_USED & sw_list->status) - { - if (list_id == sw_list->list_id) - { - return SW_ALREADY_EXIST; - } - } - else - { - loc = i; - } - } - - if (DESS_MAX_FILTER == loc) - { - return SW_NO_RESOURCE; - } - - sw_list = &(sw_list_ent[dev_id][loc]); - aos_mem_zero(sw_list, sizeof (dess_acl_list_t)); - sw_list->list_id = list_id; - sw_list->list_pri = list_pri; - sw_list->status |= ENT_USED; - return SW_OK; -} - -static sw_error_t -_dess_acl_list_destroy(a_uint32_t dev_id, a_uint32_t list_id) -{ - dess_acl_list_t *sw_list; - - HSL_DEV_ID_CHECK(dev_id); - - if (DESS_MAX_LIST_ID < list_id) - { - return SW_NOT_SUPPORTED; - } - - sw_list = _dess_acl_list_loc(dev_id, list_id); - if (NULL == sw_list) - { - return SW_NOT_FOUND; - } - - if (0 != sw_list->bind_pts) - { - return SW_NOT_SUPPORTED; - } - - if (0 != sw_list->rule_nr) - { - return SW_NOT_SUPPORTED; - } - - aos_mem_zero(sw_list, sizeof (dess_acl_list_t)); - return SW_OK; -} - -static sw_error_t -_dess_acl_rule_add(a_uint32_t dev_id, a_uint32_t list_id, - a_uint32_t rule_id, a_uint32_t rule_nr, - fal_acl_rule_t * rule) -{ - sw_error_t rv; - dess_acl_list_t *sw_list; - dess_acl_rule_t *sw_rule; - a_uint32_t i, free_flt_nr, old_flt_nr, old_flt_idx, new_flt_nr, bind_pts; - - HSL_DEV_ID_CHECK(dev_id); - - if (DESS_MAX_LIST_ID < list_id) - { - return SW_NOT_SUPPORTED; - } - - if ((0 == rule_nr) || (NULL == rule)) - { - return SW_BAD_PARAM; - } - - sw_list = _dess_acl_list_loc(dev_id, list_id); - if (NULL == sw_list) - { - return SW_NOT_FOUND; - } - - if (rule_id != sw_list->rule_nr) - { - return SW_BAD_PARAM; - } - - old_flt_idx = 0; - old_flt_nr = 0; - free_flt_nr = 0; - aos_mem_zero(hw_rule_tmp[dev_id], - DESS_HW_RULE_TMP_CNT * sizeof (dess_acl_rule_t)); - aos_mem_zero(sw_rule_tmp[dev_id], - DESS_MAX_FILTER * sizeof (dess_acl_rule_t)); - for (i = 0; i < DESS_MAX_FILTER; i++) - { - sw_rule = &(sw_rule_ent[dev_id][i]); - if (ENT_USED & sw_rule->status) - { - if (sw_rule->list_id == sw_list->list_id) - { - aos_mem_copy(&(hw_rule_tmp[dev_id][old_flt_nr]), sw_rule, - sizeof (dess_acl_rule_t)); - if (!old_flt_nr) - { - old_flt_idx = i; - } - old_flt_nr++; - } - } - else - { - free_flt_nr++; - } - } - - if (!free_flt_nr) - { - return SW_NO_RESOURCE; - } - - /* parse rule entry and alloc rule resource */ - new_flt_nr = old_flt_nr; - for (i = 0; i < rule_nr; i++) - { - rv = _dess_acl_rule_sw_to_hw(dev_id, &rule[i], hw_rule_tmp[dev_id], - &new_flt_nr); - SW_RTN_ON_ERROR(rv); - } - - if (free_flt_nr < (new_flt_nr - old_flt_nr)) - { - return SW_NO_RESOURCE; - } - - for (i = old_flt_nr; i < new_flt_nr; i++) - { - hw_rule_tmp[dev_id][i].status |= ENT_USED; - hw_rule_tmp[dev_id][i].list_id = sw_list->list_id; - hw_rule_tmp[dev_id][i].list_pri = sw_list->list_pri; - bind_pts = sw_list->bind_pts; - SW_SET_REG_BY_FIELD(MAC_RUL_V4, SRC_PT, bind_pts, - (hw_rule_tmp[dev_id][i].filter.vlu[4])); - } - - for (i = 0; i < old_flt_nr; i++) - { - sw_rule = &(sw_rule_ent[dev_id][old_flt_idx + i]); - sw_rule->status &= (~ENT_USED); - sw_rule->status |= (ENT_TMP); - } - - rv = _dess_acl_rule_alloc(dev_id, sw_list, new_flt_nr); - if (SW_OK != rv) - { - aos_mem_zero(sw_rule_tmp[dev_id], - DESS_MAX_FILTER * sizeof (dess_acl_rule_t)); - rv = _dess_acl_rule_reorder(dev_id, sw_list); - } - - for (i = 0; i < old_flt_nr; i++) - { - sw_rule = &(sw_rule_ent[dev_id][i + old_flt_idx]); - sw_rule->status |= (ENT_USED); - sw_rule->status &= (~ENT_TMP); - } - SW_RTN_ON_ERROR(rv); - - _dess_acl_rule_sync(dev_id, 0, DESS_MAX_FILTER); - sw_list->rule_nr += rule_nr; - - _dess_acl_sw_rule_dump("sw rule after add", sw_rule_ent[dev_id]); - return SW_OK; -} - -static sw_error_t -_dess_acl_rule_delete(a_uint32_t dev_id, a_uint32_t list_id, - a_uint32_t rule_id, a_uint32_t rule_nr) -{ - dess_acl_rule_t *sw_rule; - dess_acl_list_t *sw_list; - a_uint32_t i, flt_idx = 0, src_idx, dst_idx, del_nr = 0, flt_nr = 0; - sw_error_t rv; - - HSL_DEV_ID_CHECK(dev_id); - - if (DESS_MAX_LIST_ID < list_id) - { - return SW_NOT_SUPPORTED; - } - - sw_list = _dess_acl_list_loc(dev_id, list_id); - if (NULL == sw_list) - { - return SW_NOT_FOUND; - } - - if (sw_list->rule_nr < (rule_id + rule_nr)) - { - return SW_BAD_PARAM; - } - - aos_mem_zero(hw_rule_tmp[dev_id], - DESS_HW_RULE_TMP_CNT * sizeof (dess_acl_rule_t)); - aos_mem_zero(sw_rule_tmp[dev_id], - DESS_MAX_FILTER * sizeof (dess_acl_rule_t)); - - for (i = 0; i < DESS_MAX_FILTER; i++) - { - sw_rule = &(sw_rule_ent[dev_id][i]); - if ((ENT_USED & sw_rule->status) && (sw_rule->list_id == list_id)) - { - if (!flt_nr) - { - flt_idx = i; - } - - if ((sw_rule->rule_id >= rule_id) - && (sw_rule->rule_id < (rule_id + rule_nr))) - { - del_nr++; - } - else - { - aos_mem_copy(&(hw_rule_tmp[dev_id][flt_idx + flt_nr]), sw_rule, - sizeof (dess_acl_rule_t)); - } - flt_nr++; - } - } - - if (!del_nr) - { - return SW_NOT_FOUND; - } - - _dess_acl_sw_rule_dump("hw rule before del", hw_rule_tmp[dev_id]); - - for (i = 0; i < flt_nr; i++) - { - sw_rule = &(hw_rule_tmp[dev_id][flt_idx + i]); - if (ENT_USED & sw_rule->status) - { - break; - } - } - - if (i != flt_nr) - { - src_idx = flt_idx + i; - dst_idx = flt_idx; - rv = _dess_acl_list_insert(dev_id, &src_idx, &dst_idx, - hw_rule_tmp[dev_id], sw_rule_tmp[dev_id]); - SW_RTN_ON_ERROR(rv); - } - - _dess_acl_rule_sync(dev_id, flt_idx, flt_nr); - sw_list->rule_nr -= rule_nr; - - _dess_acl_sw_rule_dump("sw rule after del", sw_rule_ent[dev_id]); - return SW_OK; -} - -static sw_error_t -_dess_acl_rule_query(a_uint32_t dev_id, a_uint32_t list_id, - a_uint32_t rule_id, fal_acl_rule_t * rule) -{ - sw_error_t rv; - dess_acl_rule_t *sw_rule; - a_uint32_t flt_nr = 0, i; - - HSL_DEV_ID_CHECK(dev_id); - - if (DESS_MAX_LIST_ID < list_id) - { - return SW_NOT_SUPPORTED; - } - - aos_mem_zero(hw_rule_tmp[dev_id], - DESS_HW_RULE_TMP_CNT * sizeof (dess_acl_rule_t)); - for (i = 0; i < DESS_MAX_FILTER; i++) - { - sw_rule = &(sw_rule_ent[dev_id][i]); - if (ENT_USED & sw_rule->status) - { - if ((sw_rule->list_id == list_id) && (sw_rule->rule_id == rule_id)) - { - aos_mem_copy(&(hw_rule_tmp[dev_id][flt_nr]), sw_rule, - sizeof (dess_acl_rule_t)); - flt_nr++; - } - } - } - - if (!flt_nr) - { - return SW_NOT_FOUND; - } - - aos_mem_zero(rule, sizeof (fal_acl_rule_t)); - rv = _dess_acl_rule_hw_to_sw(dev_id, rule, hw_rule_tmp[dev_id], 0, flt_nr); - return rv; -} - -static sw_error_t -_dess_acl_rule_bind(a_uint32_t dev_id, a_uint32_t list_id, a_uint32_t ports) -{ - sw_error_t rv; - a_uint32_t i; - dess_acl_rule_t *sw_rule; - - for (i = 0; i < DESS_MAX_FILTER; i++) - { - sw_rule = &(sw_rule_ent[dev_id][i]); - - if ((ENT_USED & sw_rule->status) - && (list_id == sw_rule->list_id) - && (!(ENT_DEACTIVE & sw_rule->status))) - { - rv = _dess_filter_ports_bind(dev_id, i, ports); - SW_RTN_ON_ERROR(rv); - - SW_SET_REG_BY_FIELD(MAC_RUL_V4, SRC_PT, ports, - (sw_rule->filter.vlu[4])); - } - } - - return SW_OK; -} - -static sw_error_t -_dess_acl_list_bind(a_uint32_t dev_id, a_uint32_t list_id, - fal_acl_direc_t direc, fal_acl_bind_obj_t obj_t, - a_uint32_t obj_idx) -{ - sw_error_t rv; - a_uint32_t ports; - dess_acl_list_t *sw_list; - - HSL_DEV_ID_CHECK(dev_id); - - if (DESS_MAX_LIST_ID < list_id) - { - return SW_NOT_SUPPORTED; - } - - if (FAL_ACL_DIREC_IN != direc) - { - return SW_NOT_SUPPORTED; - } - - sw_list = _dess_acl_list_loc(dev_id, list_id); - if (NULL == sw_list) - { - return SW_NOT_FOUND; - } - - if (FAL_ACL_BIND_PORT == obj_t) - { - ports = (sw_list->bind_pts) | (0x1 << obj_idx); - } - else if (FAL_ACL_BIND_PORTBITMAP == obj_t) - { - ports = (sw_list->bind_pts) | obj_idx; - } - else - { - return SW_NOT_SUPPORTED; - } - - rv = _dess_acl_rule_bind(dev_id, list_id, ports); - SW_RTN_ON_ERROR(rv); - - sw_list->bind_pts = ports; - return SW_OK; -} - -static sw_error_t -_dess_acl_list_unbind(a_uint32_t dev_id, a_uint32_t list_id, - fal_acl_direc_t direc, fal_acl_bind_obj_t obj_t, - a_uint32_t obj_idx) -{ - sw_error_t rv; - a_uint32_t ports; - dess_acl_list_t *sw_list; - - HSL_DEV_ID_CHECK(dev_id); - - if (DESS_MAX_LIST_ID < list_id) - { - return SW_NOT_SUPPORTED; - } - - if (FAL_ACL_DIREC_IN != direc) - { - return SW_NOT_SUPPORTED; - } - - sw_list = _dess_acl_list_loc(dev_id, list_id); - if (NULL == sw_list) - { - return SW_NOT_FOUND; - } - - if (FAL_ACL_BIND_PORT == obj_t) - { - ports = (sw_list->bind_pts) & (~(0x1UL << obj_idx)); - } - else if (FAL_ACL_BIND_PORTBITMAP == obj_t) - { - ports = (sw_list->bind_pts) & (~obj_idx); - } - else - { - return SW_NOT_SUPPORTED; - } - - rv = _dess_acl_rule_bind(dev_id, list_id, ports); - SW_RTN_ON_ERROR(rv); - - sw_list->bind_pts = ports; - return SW_OK; -} - -static sw_error_t -_dess_acl_status_set(a_uint32_t dev_id, a_bool_t enable) -{ - sw_error_t rv; - a_uint32_t val; - - HSL_DEV_ID_CHECK(dev_id); - - if (A_TRUE == enable) - { - val = 1; - } - else if (A_FALSE == enable) - { - val = 0; - } - else - { - return SW_BAD_PARAM; - } - - HSL_REG_FIELD_SET(rv, dev_id, MOD_ENABLE, 0, ACL_EN, (a_uint8_t *) (&val), - sizeof (a_uint32_t)); - return rv; -} - -static sw_error_t -_dess_acl_status_get(a_uint32_t dev_id, a_bool_t * enable) -{ - sw_error_t rv; - a_uint32_t val = 0; - - HSL_DEV_ID_CHECK(dev_id); - - HSL_REG_FIELD_GET(rv, dev_id, MOD_ENABLE, 0, ACL_EN, (a_uint8_t *) (&val), - sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - - if (val) - { - *enable = A_TRUE; - } - else - { - *enable = A_FALSE; - } - - return SW_OK; -} - -static sw_error_t -_dess_acl_port_udf_profile_set(a_uint32_t dev_id, fal_port_t port_id, - fal_acl_udf_type_t udf_type, a_uint32_t offset, - a_uint32_t length) -{ - sw_error_t rv; - a_uint32_t reg = 0; - - HSL_DEV_ID_CHECK(dev_id); - - if (DESS_UDF_MAX_OFFSET < offset) - { - return SW_BAD_PARAM; - } - - if (DESS_UDF_MAX_OFFSET < length) - { - return SW_BAD_PARAM; - } - - if ((FAL_ACL_UDF_TYPE_L2_SNAP == udf_type) - || (FAL_ACL_UDF_TYPE_L3_PLUS == udf_type)) - { - HSL_REG_ENTRY_GET(rv, dev_id, WIN_RULE_CTL1, port_id, - (a_uint8_t *) (®), sizeof (a_uint32_t)); - } - else - { - HSL_REG_ENTRY_GET(rv, dev_id, WIN_RULE_CTL0, port_id, - (a_uint8_t *) (®), sizeof (a_uint32_t)); - } - SW_RTN_ON_ERROR(rv); - - switch (udf_type) - { - case FAL_ACL_UDF_TYPE_L2: - SW_SET_REG_BY_FIELD(WIN_RULE_CTL0, L2_OFFSET, offset, reg); - SW_SET_REG_BY_FIELD(WIN_RULE_CTL0, L2_LENGTH, length, reg); - break; - case FAL_ACL_UDF_TYPE_L3: - SW_SET_REG_BY_FIELD(WIN_RULE_CTL0, L3_OFFSET, offset, reg); - SW_SET_REG_BY_FIELD(WIN_RULE_CTL0, L3_LENGTH, length, reg); - break; - case FAL_ACL_UDF_TYPE_L4: - SW_SET_REG_BY_FIELD(WIN_RULE_CTL0, L4_OFFSET, offset, reg); - SW_SET_REG_BY_FIELD(WIN_RULE_CTL0, L4_LENGTH, length, reg); - break; - case FAL_ACL_UDF_TYPE_L2_SNAP: - SW_SET_REG_BY_FIELD(WIN_RULE_CTL1, L2S_OFFSET, offset, reg); - SW_SET_REG_BY_FIELD(WIN_RULE_CTL1, L2S_LENGTH, length, reg); - break; - case FAL_ACL_UDF_TYPE_L3_PLUS: - SW_SET_REG_BY_FIELD(WIN_RULE_CTL1, L3P_OFFSET, offset, reg); - SW_SET_REG_BY_FIELD(WIN_RULE_CTL1, L3P_LENGTH, length, reg); - break; - default: - return SW_BAD_PARAM; - } - - if ((FAL_ACL_UDF_TYPE_L2_SNAP == udf_type) - || (FAL_ACL_UDF_TYPE_L3_PLUS == udf_type)) - { - HSL_REG_ENTRY_SET(rv, dev_id, WIN_RULE_CTL1, port_id, - (a_uint8_t *) (®), sizeof (a_uint32_t)); - } - else - { - HSL_REG_ENTRY_SET(rv, dev_id, WIN_RULE_CTL0, port_id, - (a_uint8_t *) (®), sizeof (a_uint32_t)); - } - - return rv; -} - -static sw_error_t -_dess_acl_port_udf_profile_get(a_uint32_t dev_id, fal_port_t port_id, - fal_acl_udf_type_t udf_type, a_uint32_t * offset, - a_uint32_t * length) -{ - sw_error_t rv; - a_uint32_t reg = 0; - - HSL_DEV_ID_CHECK(dev_id); - - if ((FAL_ACL_UDF_TYPE_L2_SNAP == udf_type) - || (FAL_ACL_UDF_TYPE_L3_PLUS == udf_type)) - { - HSL_REG_ENTRY_GET(rv, dev_id, WIN_RULE_CTL1, port_id, - (a_uint8_t *) (®), sizeof (a_uint32_t)); - } - else - { - HSL_REG_ENTRY_GET(rv, dev_id, WIN_RULE_CTL0, port_id, - (a_uint8_t *) (®), sizeof (a_uint32_t)); - } - SW_RTN_ON_ERROR(rv); - - switch (udf_type) - { - case FAL_ACL_UDF_TYPE_L2: - SW_GET_FIELD_BY_REG(WIN_RULE_CTL0, L2_OFFSET, (*offset), reg); - SW_GET_FIELD_BY_REG(WIN_RULE_CTL0, L2_LENGTH, (*length), reg); - break; - case FAL_ACL_UDF_TYPE_L3: - SW_GET_FIELD_BY_REG(WIN_RULE_CTL0, L3_OFFSET, (*offset), reg); - SW_GET_FIELD_BY_REG(WIN_RULE_CTL0, L3_LENGTH, (*length), reg); - break; - case FAL_ACL_UDF_TYPE_L4: - SW_GET_FIELD_BY_REG(WIN_RULE_CTL0, L4_OFFSET, (*offset), reg); - SW_GET_FIELD_BY_REG(WIN_RULE_CTL0, L4_LENGTH, (*length), reg); - break; - case FAL_ACL_UDF_TYPE_L2_SNAP: - SW_GET_FIELD_BY_REG(WIN_RULE_CTL1, L2S_OFFSET, (*offset), reg); - SW_GET_FIELD_BY_REG(WIN_RULE_CTL1, L2S_LENGTH, (*length), reg); - break; - case FAL_ACL_UDF_TYPE_L3_PLUS: - SW_GET_FIELD_BY_REG(WIN_RULE_CTL1, L3P_OFFSET, (*offset), reg); - SW_GET_FIELD_BY_REG(WIN_RULE_CTL1, L3P_LENGTH, (*length), reg); - break; - default: - return SW_BAD_PARAM; - } - - return SW_OK; -} - -static sw_error_t -_dess_acl_rule_active(a_uint32_t dev_id, a_uint32_t list_id, - a_uint32_t rule_id, a_uint32_t rule_nr, a_bool_t active) -{ - sw_error_t rv; - a_uint32_t i, ports; - dess_acl_list_t *sw_list; - dess_acl_rule_t *sw_rule; - - HSL_DEV_ID_CHECK(dev_id); - - sw_list = _dess_acl_list_loc(dev_id, list_id); - if (NULL == sw_list) - { - return SW_NOT_FOUND; - } - - if (sw_list->rule_nr < (rule_id + rule_nr)) - { - return SW_BAD_PARAM; - } - - if (A_TRUE == active) - { - ports = (sw_list->bind_pts); - } - else - { - ports = 0; - } - - for (i = 0; i < DESS_MAX_FILTER; i++) - { - sw_rule = &(sw_rule_ent[dev_id][i]); - - if ((ENT_USED & sw_rule->status) - && (list_id == sw_rule->list_id) - && (rule_id <= sw_rule->rule_id) - && ((rule_id + rule_nr) > sw_rule->rule_id)) - { - rv = _dess_filter_ports_bind(dev_id, i, ports); - SW_RTN_ON_ERROR(rv); - - SW_SET_REG_BY_FIELD(MAC_RUL_V4, SRC_PT, ports, - (sw_rule->filter.vlu[4])); - - if (A_TRUE == active) - { - sw_rule->status &= (~ENT_DEACTIVE); - } - else - { - sw_rule->status |= (ENT_DEACTIVE); - } - } - } - - return SW_OK; -} - -static sw_error_t -_dess_acl_rule_src_filter_sts_set(a_uint32_t dev_id, - a_uint32_t rule_id, a_bool_t enable) -{ - sw_error_t rv; - a_uint32_t reg = 0, regIdx; - dess_acl_rule_t *sw_rule; - - HSL_DEV_ID_CHECK(dev_id); - - sw_rule = &sw_rule_ent[dev_id][rule_id]; - if (!(ENT_USED & sw_rule->status)) - { - return SW_NOT_FOUND; - } - - regIdx = rule_id >> 5; - - HSL_REG_ENTRY_GET(rv, dev_id, ACL_FWD_SRC_FILTER_CTL0, regIdx, - (a_uint8_t *) (®), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - - if (A_TRUE == enable) - { - reg |= (0x1 << (rule_id & 0x1F)); - sw_rule->src_flt_dis = 0; - } - else if (A_FALSE == enable) - { - reg &= ~(0x1 << (rule_id & 0x1F)); - sw_rule->src_flt_dis = 1; - } - else - { - return SW_BAD_PARAM; - } - - HSL_REG_ENTRY_SET(rv, dev_id, ACL_FWD_SRC_FILTER_CTL0, regIdx, - (a_uint8_t *) (®), sizeof (a_uint32_t)); - - return rv; -} - -static sw_error_t -_dess_acl_rule_src_filter_sts_get(a_uint32_t dev_id, - a_uint32_t rule_id, a_bool_t* enable) -{ - sw_error_t rv; - a_uint32_t reg = 0, regIdx; - dess_acl_rule_t *sw_rule; - - HSL_DEV_ID_CHECK(dev_id); - - sw_rule = &sw_rule_ent[dev_id][rule_id]; - if (!(ENT_USED & sw_rule->status)) - { - return SW_NOT_FOUND; - } - - regIdx = rule_id >> 5; - - HSL_REG_ENTRY_GET(rv, dev_id, ACL_FWD_SRC_FILTER_CTL0, regIdx, - (a_uint8_t *) (®), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - - if (reg & (0x1 << (rule_id & 0x1F))) - { - *enable = A_TRUE; - } - else - { - *enable = A_FALSE; - } - - return rv; -} - - -HSL_LOCAL sw_error_t -dess_acl_list_dump(a_uint32_t dev_id) -{ - _dess_acl_list_dump(dev_id); - return SW_OK; -} - -HSL_LOCAL sw_error_t -dess_acl_rule_dump(a_uint32_t dev_id) -{ - a_uint32_t flt_idx, i; - sw_error_t rv; - hw_filter_t filter; - - aos_printk("\ndess_acl_rule_dump:\n"); - - for (flt_idx = 0; flt_idx < DESS_MAX_FILTER; flt_idx++) - { - aos_mem_zero(&filter, sizeof (hw_filter_t)); - - rv = _dess_filter_up_to_sw(dev_id, &filter, flt_idx); - if (SW_OK != rv) - { - continue; - } - - aos_printk("\n%d filter dump:", flt_idx); - - aos_printk("\nhardware content:"); - aos_printk("\nact:"); - for (i = 0; i < (sizeof (filter.act) / sizeof (a_uint32_t)); i++) - { - aos_printk("%08x ", filter.act[i]); - } - - aos_printk("\nvlu:"); - for (i = 0; i < (sizeof (filter.vlu) / sizeof (a_uint32_t)); i++) - { - aos_printk("%08x ", filter.vlu[i]); - } - - aos_printk("\nmsk:"); - for (i = 0; i < (sizeof (filter.msk) / sizeof (a_uint32_t)); i++) - { - aos_printk("%08x ", filter.msk[i]); - } - - aos_printk("\nsoftware content:"); - aos_printk("\nact:"); - for (i = 0; i < (sizeof (filter.act) / sizeof (a_uint32_t)); i++) - { - aos_printk("%08x ", sw_rule_ent[dev_id][flt_idx].filter.act[i]); - } - - aos_printk("\nvlu:"); - for (i = 0; i < (sizeof (filter.vlu) / sizeof (a_uint32_t)); i++) - { - aos_printk("%08x ", sw_rule_ent[dev_id][flt_idx].filter.vlu[i]); - } - - aos_printk("\nmsk:"); - for (i = 0; i < (sizeof (filter.msk) / sizeof (a_uint32_t)); i++) - { - aos_printk("%08x ", sw_rule_ent[dev_id][flt_idx].filter.msk[i]); - } - - aos_printk("\nctl:status[%02d] list_id[%02d] rule_id[%02d] src_flt_dis[%02d]", - sw_rule_ent[dev_id][flt_idx].status, - sw_rule_ent[dev_id][flt_idx].list_id, - sw_rule_ent[dev_id][flt_idx].rule_id, - sw_rule_ent[dev_id][flt_idx].src_flt_dis); - - aos_printk("\n\n"); - } - - return SW_OK; -} - -sw_error_t -dess_acl_reset(a_uint32_t dev_id) -{ - HSL_DEV_ID_CHECK(dev_id); - - aos_mem_zero(sw_list_ent[dev_id], - DESS_MAX_FILTER * sizeof (dess_acl_list_t)); - - aos_mem_zero(sw_rule_ent[dev_id], - DESS_MAX_FILTER * sizeof (dess_acl_rule_t)); - - return SW_OK; -} - -/** - * @brief Creat an acl list - * @details Comments: - * If the value of list_pri is more small then the priority is more high, - * that means the list could be first matched. - * @param[in] dev_id device id - * @param[in] list_id acl list id - * @param[in] list_pri acl list priority - * @return SW_OK or error code - */ -sw_error_t -dess_acl_list_creat(a_uint32_t dev_id, a_uint32_t list_id, a_uint32_t list_pri) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _dess_acl_list_creat(dev_id, list_id, list_pri); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Destroy an acl list - * @param[in] dev_id device id - * @param[in] list_id acl list id - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -dess_acl_list_destroy(a_uint32_t dev_id, a_uint32_t list_id) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _dess_acl_list_destroy(dev_id, list_id); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Add one rule or more rules to an existing acl list - * @param[in] dev_id device id - * @param[in] list_id acl list id - * @param[in] rule_id first rule id of this adding operation in list - * @param[in] rule_nr rule number of this adding operation - * @param[in] rule rules content of this adding operation - * @return SW_OK or error code - */ -sw_error_t -dess_acl_rule_add(a_uint32_t dev_id, a_uint32_t list_id, - a_uint32_t rule_id, a_uint32_t rule_nr, fal_acl_rule_t * rule) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _dess_acl_rule_add(dev_id, list_id, rule_id, rule_nr, rule); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Delete one rule or more rules from an existing acl list - * @param[in] dev_id device id - * @param[in] list_id acl list id - * @param[in] rule_id first rule id of this deleteing operation in list - * @param[in] rule_nr rule number of this deleteing operation - * @return SW_OK or error code - */ -sw_error_t -dess_acl_rule_delete(a_uint32_t dev_id, a_uint32_t list_id, - a_uint32_t rule_id, a_uint32_t rule_nr) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _dess_acl_rule_delete(dev_id, list_id, rule_id, rule_nr); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Query one particular rule in a particular acl list - * @param[in] dev_id device id - * @param[in] list_id acl list id - * @param[in] rule_id first rule id of this deleteing operation in list - * @param[out] rule rule content of this operation - * @return SW_OK or error code - */ -sw_error_t -dess_acl_rule_query(a_uint32_t dev_id, a_uint32_t list_id, - a_uint32_t rule_id, fal_acl_rule_t * rule) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _dess_acl_rule_query(dev_id, list_id, rule_id, rule); - HSL_API_UNLOCK; - return rv; -} - -a_uint32_t -dess_acl_rule_get_offset(a_uint32_t dev_id, a_uint32_t list_id, a_uint32_t rule_id) -{ - a_uint32_t i, pos=0; - dess_acl_rule_t *sw_rule; - - for (i = 0; i < DESS_MAX_FILTER; i++) - { - sw_rule = &(sw_rule_ent[0][i]); - - if ((ENT_USED & sw_rule->status) - && (list_id == sw_rule->list_id) && (sw_rule->rule_id == rule_id) - && (!(ENT_DEACTIVE & sw_rule->status))) - { - pos = i; - break; - - } - } - - return pos; -} - - -sw_error_t -dess_acl_rule_sync_multi_portmap(a_uint32_t dev_id, a_uint32_t pos, a_uint32_t *act) -{ - - HSL_DEV_ID_CHECK(dev_id); - - if (DESS_MAX_LIST_ID < pos) - { - return SW_NOT_SUPPORTED; - } - - sw_rule_ent[dev_id][pos].filter.act[1] = act[1]; - sw_rule_ent[dev_id][pos].filter.act[2] = act[2]; - - sw_rule_tmp[dev_id][pos].filter.act[1] = act[1]; - sw_rule_tmp[dev_id][pos].filter.act[2] = act[2]; - - hw_rule_tmp[dev_id][pos].filter.act[1] = act[1]; - hw_rule_tmp[dev_id][pos].filter.act[2] = act[2]; - - - return SW_OK; -} - -/** - * @brief Bind an acl list to a particular object - * @details Comments: - * If obj_t equals FAL_ACL_BIND_PORT then obj_idx means port id - * @param[in] dev_id device id - * @param[in] list_id acl list id - * @param[in] direc direction of this binding operation - * @param[in] obj_t object type of this binding operation - * @param[in] obj_idx object index of this binding operation - * @return SW_OK or error code - */ -sw_error_t -dess_acl_list_bind(a_uint32_t dev_id, a_uint32_t list_id, - fal_acl_direc_t direc, fal_acl_bind_obj_t obj_t, - a_uint32_t obj_idx) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _dess_acl_list_bind(dev_id, list_id, direc, obj_t, obj_idx); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Unbind an acl list from a particular object - * @details Comments: - * If obj_t equals FAL_ACL_BIND_PORT then obj_idx means port id - * @param[in] dev_id device id - * @param[in] list_id acl list id - * @param[in] direc direction of this unbinding operation - * @param[in] obj_t object type of this unbinding operation - * @param[in] obj_idx object index of this unbinding operation - * @return SW_OK or error code - */ -sw_error_t -dess_acl_list_unbind(a_uint32_t dev_id, a_uint32_t list_id, - fal_acl_direc_t direc, fal_acl_bind_obj_t obj_t, - a_uint32_t obj_idx) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _dess_acl_list_unbind(dev_id, list_id, direc, obj_t, obj_idx); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Set working status of ACL engine on a particular device - * @param[in] dev_id device id - * @param[in] enable A_TRUE or A_FALSE - * @return SW_OK or error code - */ -sw_error_t -dess_acl_status_set(a_uint32_t dev_id, a_bool_t enable) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _dess_acl_status_set(dev_id, enable); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Get working status of ACL engine on a particular device - * @param[in] dev_id device id - * @param[out] enable A_TRUE or A_FALSE - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -dess_acl_status_get(a_uint32_t dev_id, a_bool_t * enable) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _dess_acl_status_get(dev_id, enable); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Set user define fields profile on a particular port - * @param[in] dev_id device id - * @param[in] port_id port id - * @param[in] udf_type udf type - * @param[in] offset udf offset - * @param[in] length udf length - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -dess_acl_port_udf_profile_set(a_uint32_t dev_id, fal_port_t port_id, - fal_acl_udf_type_t udf_type, a_uint32_t offset, - a_uint32_t length) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _dess_acl_port_udf_profile_set(dev_id, port_id, udf_type, offset, - length); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Get user define fields profile on a particular port - * @param[in] dev_id device id - * @param[in] port_id port id - * @param[in] udf_type udf type - * @param[out] offset udf offset - * @param[out] length udf length - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -dess_acl_port_udf_profile_get(a_uint32_t dev_id, fal_port_t port_id, - fal_acl_udf_type_t udf_type, a_uint32_t * offset, - a_uint32_t * length) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _dess_acl_port_udf_profile_get(dev_id, port_id, udf_type, offset, - length); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Active one or more rules in an existing acl list - * @param[in] dev_id device id - * @param[in] list_id acl list id - * @param[in] rule_id first rule id of this deactive operation in list - * @param[in] rule_nr rule number of this deactive operation - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -dess_acl_rule_active(a_uint32_t dev_id, a_uint32_t list_id, - a_uint32_t rule_id, a_uint32_t rule_nr) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _dess_acl_rule_active(dev_id, list_id, rule_id, rule_nr, A_TRUE); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Deactive one or more rules in an existing acl list - * @param[in] dev_id device id - * @param[in] list_id acl list id - * @param[in] rule_id first rule id of this deactive operation in list - * @param[in] rule_nr rule number of this deactive operation - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -dess_acl_rule_deactive(a_uint32_t dev_id, a_uint32_t list_id, - a_uint32_t rule_id, a_uint32_t rule_nr) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _dess_acl_rule_active(dev_id, list_id, rule_id, rule_nr, A_FALSE); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief enable acl forward source filter of one rule. - * @param[in] dev_id device id - * @param[in] rule_id first rule id of this deactive operation in list - * @param[in] enable A_TRUE or A_FALSE - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -dess_acl_rule_src_filter_sts_set(a_uint32_t dev_id, - a_uint32_t rule_id, a_bool_t enable) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _dess_acl_rule_src_filter_sts_set(dev_id, rule_id, enable); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief get the status of acl forward source filter of one rule. - * @param[in] dev_id device id - * @param[in] rule_id first rule id of this deactive operation in list - * @param[out] enable A_TRUE or A_FALSE - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -dess_acl_rule_src_filter_sts_get(a_uint32_t dev_id, - a_uint32_t rule_id, a_bool_t* enable) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _dess_acl_rule_src_filter_sts_get(dev_id, rule_id, enable); - HSL_API_UNLOCK; - return rv; -} - - - -sw_error_t -dess_acl_init(a_uint32_t dev_id) -{ - HSL_DEV_ID_CHECK(dev_id); - - sw_list_ent[dev_id] = - (dess_acl_list_t *) aos_mem_alloc(DESS_MAX_FILTER * - sizeof (dess_acl_list_t)); - if (NULL == sw_list_ent[dev_id]) - { - return SW_NO_RESOURCE; - } - aos_mem_zero(sw_list_ent[dev_id], - DESS_MAX_FILTER * sizeof (dess_acl_list_t)); - - sw_rule_ent[dev_id] = - (dess_acl_rule_t *) aos_mem_alloc(DESS_MAX_FILTER * - sizeof (dess_acl_rule_t)); - if (NULL == sw_rule_ent[dev_id]) - { - return SW_NO_RESOURCE; - } - aos_mem_zero(sw_rule_ent[dev_id], - DESS_MAX_FILTER * sizeof (dess_acl_rule_t)); - - hw_rule_tmp[dev_id] = - (dess_acl_rule_t *) aos_mem_alloc(DESS_HW_RULE_TMP_CNT * - sizeof (dess_acl_rule_t)); - if (NULL == hw_rule_tmp[dev_id]) - { - return SW_NO_RESOURCE; - } - - sw_rule_tmp[dev_id] = - (dess_acl_rule_t *) aos_mem_alloc(DESS_MAX_FILTER * - sizeof (dess_acl_rule_t)); - if (NULL == sw_rule_tmp[dev_id]) - { - return SW_NO_RESOURCE; - } -#ifdef DESS_SW_ENTRY - sw_filter_mem = aos_mem_alloc(DESS_MAX_FILTER * sizeof (hw_filter_t)); - if (NULL == sw_filter_mem) - { - return SW_NO_RESOURCE; - } - aos_mem_zero(sw_filter_mem, DESS_MAX_FILTER * sizeof (hw_filter_t)); -#endif - -#ifndef HSL_STANDALONG - { - hsl_api_t *p_api; - - SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id)); - - p_api->acl_list_creat = dess_acl_list_creat; - p_api->acl_list_destroy = dess_acl_list_destroy; - p_api->acl_list_bind = dess_acl_list_bind; - p_api->acl_list_unbind = dess_acl_list_unbind; - p_api->acl_rule_add = dess_acl_rule_add; - p_api->acl_rule_delete = dess_acl_rule_delete; - p_api->acl_rule_query = dess_acl_rule_query; - p_api->acl_status_set = dess_acl_status_set; - p_api->acl_status_get = dess_acl_status_get; - p_api->acl_list_dump = dess_acl_list_dump; - p_api->acl_rule_dump = dess_acl_rule_dump; - p_api->acl_port_udf_profile_set = dess_acl_port_udf_profile_set; - p_api->acl_port_udf_profile_get = dess_acl_port_udf_profile_get; - p_api->acl_rule_active = dess_acl_rule_active; - p_api->acl_rule_deactive = dess_acl_rule_deactive; - p_api->acl_rule_src_filter_sts_set = dess_acl_rule_src_filter_sts_set; - p_api->acl_rule_src_filter_sts_get = dess_acl_rule_src_filter_sts_get; - p_api->acl_rule_get_offset = dess_acl_rule_get_offset; - p_api->acl_rule_sync_multi_portmap = dess_acl_rule_sync_multi_portmap; - } -#endif - - return SW_OK; -} - -sw_error_t -dess_acl_cleanup(a_uint32_t dev_id) -{ - HSL_DEV_ID_CHECK(dev_id); - - if (NULL != sw_list_ent[dev_id]) - { - aos_mem_free(sw_list_ent[dev_id]); - } - - if (NULL != sw_rule_ent[dev_id]) - { - aos_mem_free(sw_rule_ent[dev_id]); - } - - if (NULL != hw_rule_tmp[dev_id]) - { - aos_mem_free(hw_rule_tmp[dev_id]); - } - - if (NULL != sw_rule_tmp[dev_id]) - { - aos_mem_free(sw_rule_tmp[dev_id]); - } -#ifdef DESS_SW_ENTRY - if (NULL != sw_filter_mem) - { - aos_mem_free(sw_filter_mem); - } -#endif - - return SW_OK; -} - -/** - * @} - */ - diff --git a/feeds/ipq807x/qca-ssdk/src/src/hsl/dess/dess_acl_parse.c b/feeds/ipq807x/qca-ssdk/src/src/hsl/dess/dess_acl_parse.c deleted file mode 100755 index f38219b55..000000000 --- a/feeds/ipq807x/qca-ssdk/src/src/hsl/dess/dess_acl_parse.c +++ /dev/null @@ -1,2452 +0,0 @@ -/* - * Copyright (c) 2014, The Linux Foundation. All rights reserved. - * Permission to use, copy, modify, and/or distribute this software for - * any purpose with or without fee is hereby granted, provided that the - * above copyright notice and this permission notice appear in all copies. - * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES - * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR - * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES - * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN - * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT - * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. - */ - - - -#include "sw.h" -#include "hsl.h" -#include "hsl_dev.h" -#include "hsl_acl.h" -#include "dess_acl.h" -#include "dess_reg.h" -#include "dess_acl_prv.h" - -#define DAH 0x1 -#define SAH 0x2 -#define TAG 0x4 -#define STAG 0x8 -#define CTAG 0x10 - -typedef sw_error_t(*parse_func_t) (fal_acl_rule_t * sw, - hw_filter_t * hw_filter_snap, - a_bool_t * b_care); - -static a_bool_t -_dess_acl_zero_addr(const fal_mac_addr_t addr) -{ - a_uint32_t i; - - for (i = 0; i < 6; i++) - { - if (addr.uc[i]) - { - return A_FALSE; - } - } - return A_TRUE; -} - -static a_bool_t -_dess_acl_field_care(fal_acl_field_op_t op, a_uint32_t val, a_uint32_t mask, - a_uint32_t chkvlu) -{ - if (FAL_ACL_FIELD_MASK == op) - { - if (0 == mask) - return A_FALSE; - } - else if (FAL_ACL_FIELD_RANGE == op) - { - if ((0 == val) && (chkvlu == mask)) - return A_FALSE; - } - else if (FAL_ACL_FIELD_LE == op) - { - if (chkvlu == val) - return A_FALSE; - } - else if (FAL_ACL_FIELD_GE == op) - { - if (0 == val) - return A_FALSE; - } - else if (FAL_ACL_FIELD_NE == op) - { - return A_TRUE; - } - - return A_TRUE; -} - -static sw_error_t -_dess_acl_rule_bmac_parse(fal_acl_rule_t * sw, - hw_filter_t * hw, a_bool_t * b_care) -{ - a_uint32_t i; - - *b_care = A_FALSE; - aos_mem_zero(&(hw->vlu[0]), sizeof (hw->vlu)); - aos_mem_zero(&(hw->msk[0]), sizeof (hw->msk)); - - FIELD_SET_MASK(MAC_RUL_M4, RULE_TYP, DESS_MAC_FILTER); - - if (FAL_FIELD_FLG_TST(sw->field_flg, FAL_ACL_FIELD_MAC_DA)) - { - if (A_TRUE != _dess_acl_zero_addr(sw->dest_mac_mask)) - { - *b_care = A_TRUE; - } - - for (i = 0; i < 6; i++) - { - sw->dest_mac_val.uc[i] &= sw->dest_mac_mask.uc[i]; - } - - FIELD_SET(MAC_RUL_V0, DAV_BYTE2, sw->dest_mac_val.uc[2]); - FIELD_SET(MAC_RUL_V0, DAV_BYTE3, sw->dest_mac_val.uc[3]); - FIELD_SET(MAC_RUL_V0, DAV_BYTE4, sw->dest_mac_val.uc[4]); - FIELD_SET(MAC_RUL_V0, DAV_BYTE5, sw->dest_mac_val.uc[5]); - FIELD_SET(MAC_RUL_V1, DAV_BYTE0, sw->dest_mac_val.uc[0]); - FIELD_SET(MAC_RUL_V1, DAV_BYTE1, sw->dest_mac_val.uc[1]); - - FIELD_SET_MASK(MAC_RUL_M0, DAM_BYTE2, sw->dest_mac_mask.uc[2]); - FIELD_SET_MASK(MAC_RUL_M0, DAM_BYTE3, sw->dest_mac_mask.uc[3]); - FIELD_SET_MASK(MAC_RUL_M0, DAM_BYTE4, sw->dest_mac_mask.uc[4]); - FIELD_SET_MASK(MAC_RUL_M0, DAM_BYTE5, sw->dest_mac_mask.uc[5]); - FIELD_SET_MASK(MAC_RUL_M1, DAM_BYTE0, sw->dest_mac_mask.uc[0]); - FIELD_SET_MASK(MAC_RUL_M1, DAM_BYTE1, sw->dest_mac_mask.uc[1]); - } - - if (FAL_FIELD_FLG_TST(sw->field_flg, FAL_ACL_FIELD_MAC_SA)) - { - if (A_TRUE != _dess_acl_zero_addr(sw->src_mac_mask)) - { - *b_care = A_TRUE; - } - - for (i = 0; i < 6; i++) - { - sw->src_mac_val.uc[i] &= sw->src_mac_mask.uc[i]; - } - - FIELD_SET(MAC_RUL_V1, SAV_BYTE4, sw->src_mac_val.uc[4]); - FIELD_SET(MAC_RUL_V1, SAV_BYTE5, sw->src_mac_val.uc[5]); - FIELD_SET(MAC_RUL_V2, SAV_BYTE0, sw->src_mac_val.uc[0]); - FIELD_SET(MAC_RUL_V2, SAV_BYTE1, sw->src_mac_val.uc[1]); - FIELD_SET(MAC_RUL_V2, SAV_BYTE2, sw->src_mac_val.uc[2]); - FIELD_SET(MAC_RUL_V2, SAV_BYTE3, sw->src_mac_val.uc[3]); - - FIELD_SET_MASK(MAC_RUL_M1, SAM_BYTE4, sw->src_mac_mask.uc[4]); - FIELD_SET_MASK(MAC_RUL_M1, SAM_BYTE5, sw->src_mac_mask.uc[5]); - FIELD_SET_MASK(MAC_RUL_M2, SAM_BYTE0, sw->src_mac_mask.uc[0]); - FIELD_SET_MASK(MAC_RUL_M2, SAM_BYTE1, sw->src_mac_mask.uc[1]); - FIELD_SET_MASK(MAC_RUL_M2, SAM_BYTE2, sw->src_mac_mask.uc[2]); - FIELD_SET_MASK(MAC_RUL_M2, SAM_BYTE3, sw->src_mac_mask.uc[3]); - } - - if (FAL_FIELD_FLG_TST(sw->field_flg, FAL_ACL_FIELD_MAC_ETHTYPE)) - { - if (0x0 != sw->ethtype_mask) - { - *b_care = A_TRUE; - } - - sw->ethtype_val &= sw->ethtype_mask; - FIELD_SET(MAC_RUL_V3, ETHTYPV, sw->ethtype_val); - FIELD_SET_MASK(MAC_RUL_M3, ETHTYPM, sw->ethtype_mask); - } - - if (FAL_FIELD_FLG_TST(sw->field_flg, FAL_ACL_FIELD_MAC_TAGGED)) - { - if (0x0 != sw->tagged_mask) - { - *b_care = A_TRUE; - } - - sw->tagged_val &= sw->tagged_mask; - FIELD_SET_MASK(MAC_RUL_M4, TAGGEDV, sw->tagged_val); - FIELD_SET_MASK(MAC_RUL_M4, TAGGEDM, sw->tagged_mask); - } - - if (FAL_FIELD_FLG_TST(sw->field_flg, FAL_ACL_FIELD_MAC_UP)) - { - if (0x0 != sw->up_mask) - { - *b_care = A_TRUE; - } - - sw->up_val &= sw->up_mask; - FIELD_SET(MAC_RUL_V3, VLANPRIV, sw->up_val); - FIELD_SET_MASK(MAC_RUL_M3, VLANPRIM, sw->up_mask); - } - - FIELD_SET_MASK(MAC_RUL_M4, VIDMSK, 1); - if (FAL_FIELD_FLG_TST(sw->field_flg, FAL_ACL_FIELD_MAC_VID)) - { - if ((FAL_ACL_FIELD_MASK != sw->vid_op) - && (FAL_ACL_FIELD_RANGE != sw->vid_op) - && (FAL_ACL_FIELD_LE != sw->vid_op) - && (FAL_ACL_FIELD_GE != sw->vid_op)) - { - return SW_NOT_SUPPORTED; - } - - if (A_TRUE == - _dess_acl_field_care(sw->vid_op, sw->vid_val, sw->vid_mask, - 0xfff)) - { - *b_care = A_TRUE; - } - - FIELD_SET_MASK(MAC_RUL_M4, VIDMSK, 0); - if (FAL_ACL_FIELD_MASK == sw->vid_op) - { - sw->vid_val &= sw->vid_mask; - FIELD_SET(MAC_RUL_V3, VLANIDV, sw->vid_val); - FIELD_SET_MASK(MAC_RUL_M3, VLANIDM, sw->vid_mask); - FIELD_SET_MASK(MAC_RUL_M4, VIDMSK, 1); - } - else if (FAL_ACL_FIELD_RANGE == sw->vid_op) - { - FIELD_SET(MAC_RUL_V3, VLANIDV, sw->vid_val); - FIELD_SET_MASK(MAC_RUL_M3, VLANIDM, sw->vid_mask); - } - else if (FAL_ACL_FIELD_LE == sw->vid_op) - { - FIELD_SET(MAC_RUL_V3, VLANIDV, 0); - FIELD_SET_MASK(MAC_RUL_M3, VLANIDM, sw->vid_val); - } - else - { - FIELD_SET(MAC_RUL_V3, VLANIDV, sw->vid_val); - FIELD_SET_MASK(MAC_RUL_M3, VLANIDM, 0xfff); - } - } - - if (FAL_FIELD_FLG_TST(sw->field_flg, FAL_ACL_FIELD_MAC_CFI)) - { - if (0x0 != sw->cfi_mask) - { - *b_care = A_TRUE; - } - - sw->cfi_val &= sw->cfi_mask; - FIELD_SET(MAC_RUL_V3, VLANCFIV, sw->cfi_val); - FIELD_SET_MASK(MAC_RUL_M3, VLANCFIM, sw->cfi_mask); - } - - if (FAL_FIELD_FLG_TST(sw->field_flg, FAL_ACL_FIELD_INVERSE_ALL)) - { - FIELD_SET(MAC_RUL_V4, RULE_INV, 1); - } - - return SW_OK; -} - -static sw_error_t -_dess_acl_rule_ehmac_parse(fal_acl_rule_t * sw, - hw_filter_t * hw, a_bool_t * b_care) -{ - a_uint32_t i; - a_bool_t da_h = A_FALSE, sa_h = A_FALSE; - - *b_care = A_FALSE; - aos_mem_zero(&(hw->vlu[0]), sizeof (hw->vlu)); - aos_mem_zero(&(hw->msk[0]), sizeof (hw->msk)); - - FIELD_SET_MASK(MAC_RUL_M4, RULE_TYP, DESS_EHMAC_FILTER); - - if (FAL_FIELD_FLG_TST(sw->field_flg, FAL_ACL_FIELD_MAC_DA)) - { - for (i = 0; i < 3; i++) - { - if (sw->dest_mac_mask.uc[i]) - { - da_h = A_TRUE; - break; - } - } - } - - if (FAL_FIELD_FLG_TST(sw->field_flg, FAL_ACL_FIELD_MAC_SA)) - { - for (i = 0; i < 3; i++) - { - if (sw->src_mac_mask.uc[i]) - { - sa_h = A_TRUE; - break; - } - } - } - - /* if sa_h and da_h both are true need't process mac address fileds */ - if ((A_TRUE == da_h) && ((A_TRUE == sa_h))) - { - da_h = A_FALSE; - sa_h = A_FALSE; - } - - if (A_TRUE == da_h) - { - FIELD_SET(EHMAC_RUL_V3, DA_EN, 1); - - if (A_TRUE != _dess_acl_zero_addr(sw->dest_mac_mask)) - { - *b_care = A_TRUE; - } - - for (i = 0; i < 6; i++) - { - sw->dest_mac_val.uc[i] &= sw->dest_mac_mask.uc[i]; - } - - FIELD_SET(EHMAC_RUL_V0, DAV_BYTE2, sw->dest_mac_val.uc[2]); - FIELD_SET(EHMAC_RUL_V0, DAV_BYTE3, sw->dest_mac_val.uc[3]); - FIELD_SET(EHMAC_RUL_V0, DAV_BYTE4, sw->dest_mac_val.uc[4]); - FIELD_SET(EHMAC_RUL_V0, DAV_BYTE5, sw->dest_mac_val.uc[5]); - FIELD_SET(EHMAC_RUL_V1, DAV_BYTE0, sw->dest_mac_val.uc[0]); - FIELD_SET(EHMAC_RUL_V1, DAV_BYTE1, sw->dest_mac_val.uc[1]); - - FIELD_SET_MASK(EHMAC_RUL_M0, DAM_BYTE2, sw->dest_mac_mask.uc[2]); - FIELD_SET_MASK(EHMAC_RUL_M0, DAM_BYTE3, sw->dest_mac_mask.uc[3]); - FIELD_SET_MASK(EHMAC_RUL_M0, DAM_BYTE4, sw->dest_mac_mask.uc[4]); - FIELD_SET_MASK(EHMAC_RUL_M0, DAM_BYTE5, sw->dest_mac_mask.uc[5]); - FIELD_SET_MASK(EHMAC_RUL_M1, DAM_BYTE0, sw->dest_mac_mask.uc[0]); - FIELD_SET_MASK(EHMAC_RUL_M1, DAM_BYTE1, sw->dest_mac_mask.uc[1]); - - if (FAL_FIELD_FLG_TST(sw->field_flg, FAL_ACL_FIELD_MAC_SA)) - { - if (A_TRUE != _dess_acl_zero_addr(sw->src_mac_mask)) - { - *b_care = A_TRUE; - } - - for (i = 0; i < 6; i++) - { - sw->src_mac_val.uc[i] &= sw->src_mac_mask.uc[i]; - } - - FIELD_SET(EHMAC_RUL_V2, SAV_BYTE3, sw->src_mac_val.uc[3]); - FIELD_SET(EHMAC_RUL_V1, SAV_BYTE4, sw->src_mac_val.uc[4]); - FIELD_SET(EHMAC_RUL_V1, SAV_BYTE5, sw->src_mac_val.uc[5]); - - FIELD_SET_MASK(EHMAC_RUL_M2, SAM_BYTE3, sw->src_mac_mask.uc[3]); - FIELD_SET_MASK(EHMAC_RUL_M1, SAM_BYTE4, sw->src_mac_mask.uc[4]); - FIELD_SET_MASK(EHMAC_RUL_M1, SAM_BYTE5, sw->src_mac_mask.uc[5]); - } - } - - if (A_TRUE == sa_h) - { - if (A_TRUE != _dess_acl_zero_addr(sw->src_mac_mask)) - { - *b_care = A_TRUE; - } - - for (i = 0; i < 6; i++) - { - sw->src_mac_val.uc[i] &= sw->src_mac_mask.uc[i]; - } - - FIELD_SET(EHMAC_RUL_V0, DAV_BYTE2, sw->src_mac_val.uc[2]); - FIELD_SET(EHMAC_RUL_V0, DAV_BYTE3, sw->src_mac_val.uc[3]); - FIELD_SET(EHMAC_RUL_V0, DAV_BYTE4, sw->src_mac_val.uc[4]); - FIELD_SET(EHMAC_RUL_V0, DAV_BYTE5, sw->src_mac_val.uc[5]); - FIELD_SET(EHMAC_RUL_V1, DAV_BYTE0, sw->src_mac_val.uc[0]); - FIELD_SET(EHMAC_RUL_V1, DAV_BYTE1, sw->src_mac_val.uc[1]); - - FIELD_SET_MASK(EHMAC_RUL_M0, DAM_BYTE2, sw->src_mac_mask.uc[2]); - FIELD_SET_MASK(EHMAC_RUL_M0, DAM_BYTE3, sw->src_mac_mask.uc[3]); - FIELD_SET_MASK(EHMAC_RUL_M0, DAM_BYTE4, sw->src_mac_mask.uc[4]); - FIELD_SET_MASK(EHMAC_RUL_M0, DAM_BYTE5, sw->src_mac_mask.uc[5]); - FIELD_SET_MASK(EHMAC_RUL_M1, DAM_BYTE0, sw->src_mac_mask.uc[0]); - FIELD_SET_MASK(EHMAC_RUL_M1, DAM_BYTE1, sw->src_mac_mask.uc[1]); - - if (FAL_FIELD_FLG_TST(sw->field_flg, FAL_ACL_FIELD_MAC_DA)) - { - if (A_TRUE != _dess_acl_zero_addr(sw->dest_mac_mask)) - { - *b_care = A_TRUE; - } - - for (i = 0; i < 6; i++) - { - sw->dest_mac_val.uc[i] &= sw->dest_mac_mask.uc[i]; - } - - FIELD_SET(EHMAC_RUL_V2, SAV_BYTE3, sw->dest_mac_val.uc[3]); - FIELD_SET(EHMAC_RUL_V1, SAV_BYTE4, sw->dest_mac_val.uc[4]); - FIELD_SET(EHMAC_RUL_V1, SAV_BYTE5, sw->dest_mac_val.uc[5]); - - FIELD_SET_MASK(EHMAC_RUL_M2, SAM_BYTE3, sw->dest_mac_mask.uc[3]); - FIELD_SET_MASK(EHMAC_RUL_M1, SAM_BYTE4, sw->dest_mac_mask.uc[4]); - FIELD_SET_MASK(EHMAC_RUL_M1, SAM_BYTE5, sw->dest_mac_mask.uc[5]); - } - } - - if (FAL_FIELD_FLG_TST(sw->field_flg, FAL_ACL_FIELD_MAC_ETHTYPE)) - { - if (0x0 != sw->ethtype_mask) - { - *b_care = A_TRUE; - } - - sw->ethtype_val &= sw->ethtype_mask; - FIELD_SET(EHMAC_RUL_V3, ETHTYPV, sw->ethtype_val); - FIELD_SET_MASK(EHMAC_RUL_M3, ETHTYPM, sw->ethtype_mask); - } - - /* Process Stag Fields */ - if (FAL_FIELD_FLG_TST(sw->field_flg, FAL_ACL_FIELD_MAC_STAGGED)) - { - if (0x0 != sw->stagged_mask) - { - *b_care = A_TRUE; - } - - sw->stagged_val &= sw->stagged_mask; - FIELD_SET(EHMAC_RUL_V3, STAGGEDV, sw->stagged_val); - FIELD_SET(EHMAC_RUL_V3, STAGGEDM, sw->stagged_mask); - } - - FIELD_SET(EHMAC_RUL_V3, SVIDMSK, 1); - if (FAL_FIELD_FLG_TST(sw->field_flg, FAL_ACL_FIELD_MAC_STAG_VID)) - { - if ((FAL_ACL_FIELD_MASK != sw->stag_vid_op) - && (FAL_ACL_FIELD_RANGE != sw->stag_vid_op) - && (FAL_ACL_FIELD_LE != sw->stag_vid_op) - && (FAL_ACL_FIELD_GE != sw->stag_vid_op)) - { - return SW_NOT_SUPPORTED; - } - - if (A_TRUE == - _dess_acl_field_care(sw->stag_vid_op, sw->stag_vid_val, - sw->stag_vid_mask, 0xfff)) - { - *b_care = A_TRUE; - } - - FIELD_SET(EHMAC_RUL_V3, SVIDMSK, 0); - if (FAL_ACL_FIELD_MASK == sw->stag_vid_op) - { - sw->stag_vid_val &= sw->stag_vid_mask; - FIELD_SET(EHMAC_RUL_V2, STAG_VIDV, sw->stag_vid_val); - FIELD_SET_MASK(EHMAC_RUL_M2, STAG_VIDM, sw->stag_vid_mask); - FIELD_SET(EHMAC_RUL_V3, SVIDMSK, 1); - - } - else if (FAL_ACL_FIELD_RANGE == sw->stag_vid_op) - { - FIELD_SET(EHMAC_RUL_V2, STAG_VIDV, sw->stag_vid_val); - FIELD_SET_MASK(EHMAC_RUL_M2, STAG_VIDM, sw->stag_vid_mask); - - } - else if (FAL_ACL_FIELD_LE == sw->stag_vid_op) - { - FIELD_SET(EHMAC_RUL_V2, STAG_VIDV, 0); - FIELD_SET_MASK(EHMAC_RUL_M2, STAG_VIDM, sw->stag_vid_val); - - } - else - { - FIELD_SET(EHMAC_RUL_V2, STAG_VIDV, sw->stag_vid_val); - FIELD_SET_MASK(EHMAC_RUL_M2, STAG_VIDM, 0xfff); - } - } - - if (FAL_FIELD_FLG_TST(sw->field_flg, FAL_ACL_FIELD_MAC_STAG_PRI)) - { - if (0x0 != sw->stag_pri_mask) - { - *b_care = A_TRUE; - } - - sw->stag_pri_val &= sw->stag_pri_mask; - FIELD_SET(EHMAC_RUL_V2, STAG_PRIV, sw->stag_pri_val); - FIELD_SET_MASK(EHMAC_RUL_M2, STAG_PRIM, sw->stag_pri_mask); - } - - if (FAL_FIELD_FLG_TST(sw->field_flg, FAL_ACL_FIELD_MAC_STAG_DEI)) - { - if (0x0 != sw->stag_dei_mask) - { - *b_care = A_TRUE; - } - - sw->stag_dei_val &= sw->stag_dei_mask; - FIELD_SET(EHMAC_RUL_V2, STAG_DEIV, sw->stag_dei_val); - FIELD_SET_MASK(EHMAC_RUL_M2, STAG_DEIM, sw->stag_dei_mask); - } - - /* Process Ctag Fields */ - if (FAL_FIELD_FLG_TST(sw->field_flg, FAL_ACL_FIELD_MAC_CTAGGED)) - { - if (0x0 != sw->ctagged_mask) - { - *b_care = A_TRUE; - } - - sw->ctagged_val &= sw->ctagged_mask; - FIELD_SET_MASK(EHMAC_RUL_M4, CTAGGEDV, sw->ctagged_val); - FIELD_SET_MASK(EHMAC_RUL_M4, CTAGGEDM, sw->ctagged_mask); - } - - FIELD_SET_MASK(EHMAC_RUL_M4, CVIDMSK, 1); - if (FAL_FIELD_FLG_TST(sw->field_flg, FAL_ACL_FIELD_MAC_CTAG_VID)) - { - if ((FAL_ACL_FIELD_MASK != sw->ctag_vid_op) - && (FAL_ACL_FIELD_RANGE != sw->ctag_vid_op) - && (FAL_ACL_FIELD_LE != sw->ctag_vid_op) - && (FAL_ACL_FIELD_GE != sw->ctag_vid_op)) - { - return SW_NOT_SUPPORTED; - } - - if (A_TRUE == - _dess_acl_field_care(sw->ctag_vid_op, sw->ctag_vid_val, - sw->ctag_vid_mask, 0xfff)) - { - *b_care = A_TRUE; - } - - FIELD_SET_MASK(EHMAC_RUL_M4, CVIDMSK, 0); - if (FAL_ACL_FIELD_MASK == sw->ctag_vid_op) - { - sw->ctag_vid_val &= sw->ctag_vid_mask; - FIELD_SET(EHMAC_RUL_V2, CTAG_VIDLV, sw->ctag_vid_val); - FIELD_SET(EHMAC_RUL_V3, CTAG_VIDHV, (sw->ctag_vid_val >> 8)); - FIELD_SET_MASK(EHMAC_RUL_M2, CTAG_VIDLM, sw->ctag_vid_mask); - FIELD_SET_MASK(EHMAC_RUL_M3, CTAG_VIDHM, (sw->ctag_vid_mask >> 8)); - FIELD_SET_MASK(EHMAC_RUL_M4, CVIDMSK, 1); - - } - else if (FAL_ACL_FIELD_RANGE == sw->ctag_vid_op) - { - FIELD_SET(EHMAC_RUL_V2, CTAG_VIDLV, sw->ctag_vid_val); - FIELD_SET(EHMAC_RUL_V3, CTAG_VIDHV, (sw->ctag_vid_val >> 8)); - FIELD_SET_MASK(EHMAC_RUL_M2, CTAG_VIDLM, sw->ctag_vid_mask); - FIELD_SET_MASK(EHMAC_RUL_M3, CTAG_VIDHM, (sw->ctag_vid_mask >> 8)); - - } - else if (FAL_ACL_FIELD_LE == sw->ctag_vid_op) - { - FIELD_SET(EHMAC_RUL_V2, CTAG_VIDLV, 0); - FIELD_SET(EHMAC_RUL_V3, CTAG_VIDHV, 0); - FIELD_SET_MASK(EHMAC_RUL_M2, CTAG_VIDLM, sw->ctag_vid_val); - FIELD_SET_MASK(EHMAC_RUL_M3, CTAG_VIDHM, (sw->ctag_vid_val >> 8)); - - } - else - { - FIELD_SET(EHMAC_RUL_V2, CTAG_VIDLV, sw->ctag_vid_val); - FIELD_SET(EHMAC_RUL_V3, CTAG_VIDHV, (sw->ctag_vid_val >> 8)); - FIELD_SET_MASK(EHMAC_RUL_M2, CTAG_VIDLM, 0xff); - FIELD_SET_MASK(EHMAC_RUL_M3, CTAG_VIDHM, 0xf); - } - } - - if (FAL_FIELD_FLG_TST(sw->field_flg, FAL_ACL_FIELD_MAC_CTAG_PRI)) - { - if (0x0 != sw->ctag_pri_mask) - { - *b_care = A_TRUE; - } - - sw->ctag_pri_val &= sw->ctag_pri_mask; - FIELD_SET(EHMAC_RUL_V3, CTAG_PRIV, sw->ctag_pri_val); - FIELD_SET_MASK(EHMAC_RUL_M3, CTAG_PRIM, sw->ctag_pri_mask); - } - - if (FAL_FIELD_FLG_TST(sw->field_flg, FAL_ACL_FIELD_MAC_CTAG_CFI)) - { - if (0x0 != sw->ctag_cfi_mask) - { - *b_care = A_TRUE; - } - - sw->ctag_cfi_val &= sw->ctag_cfi_mask; - FIELD_SET(EHMAC_RUL_V3, CTAG_CFIV, sw->ctag_cfi_val); - FIELD_SET_MASK(EHMAC_RUL_M3, CTAG_CFIM, sw->ctag_cfi_mask); - } - - if (FAL_FIELD_FLG_TST(sw->field_flg, FAL_ACL_FIELD_INVERSE_ALL)) - { - FIELD_SET(MAC_RUL_V4, RULE_INV, 1); - } - - return SW_OK; -} - -static void -_dess_acl_rule_mac_preparse(fal_acl_rule_t * sw, a_bool_t * b_mac, - a_bool_t * eh_mac) -{ - a_uint32_t bm = 0, i, tmp; - - *b_mac = A_FALSE; - *eh_mac = A_FALSE; - if (FAL_FIELD_FLG_TST(sw->field_flg, FAL_ACL_FIELD_MAC_DA)) - { - for (i = 0; i < 3; i++) - { - if (sw->dest_mac_mask.uc[i]) - { - bm |= DAH; - break; - } - } - } - - if (FAL_FIELD_FLG_TST(sw->field_flg, FAL_ACL_FIELD_MAC_SA)) - { - for (i = 0; i < 3; i++) - { - if (sw->src_mac_mask.uc[i]) - { - bm |= SAH; - break; - } - } - } - - tmp = 0; - if (FAL_FIELD_FLG_TST(sw->field_flg, FAL_ACL_FIELD_MAC_TAGGED)) - { - tmp |= ((sw->tagged_mask & 0x1) << 16); - } - if (FAL_FIELD_FLG_TST(sw->field_flg, FAL_ACL_FIELD_MAC_UP)) - { - tmp |= ((sw->up_mask & 0x7) << 13); - } - if (FAL_FIELD_FLG_TST(sw->field_flg, FAL_ACL_FIELD_MAC_CFI)) - { - tmp |= ((sw->cfi_mask & 0x1) << 12); - } - if (FAL_FIELD_FLG_TST(sw->field_flg, FAL_ACL_FIELD_MAC_VID)) - { - if (A_TRUE == - _dess_acl_field_care(sw->vid_op, sw->vid_val, sw->vid_mask, - 0xfff)) - { - tmp |= 0xfff; - } - } - if (tmp) - { - bm |= TAG; - } - - tmp = 0; - if (FAL_FIELD_FLG_TST(sw->field_flg, FAL_ACL_FIELD_MAC_STAGGED)) - { - tmp |= ((sw->stagged_mask & 0x1) << 16); - } - if (FAL_FIELD_FLG_TST(sw->field_flg, FAL_ACL_FIELD_MAC_STAG_PRI)) - { - tmp |= ((sw->stag_pri_mask & 0x7) << 13); - } - if (FAL_FIELD_FLG_TST(sw->field_flg, FAL_ACL_FIELD_MAC_STAG_DEI)) - { - tmp |= ((sw->stag_dei_mask & 0x1) << 12); - } - if (FAL_FIELD_FLG_TST(sw->field_flg, FAL_ACL_FIELD_MAC_STAG_VID)) - { - if (A_TRUE == - _dess_acl_field_care(sw->stag_vid_op, sw->stag_vid_val, - sw->stag_vid_mask, 0xfff)) - { - tmp |= 0xfff; - } - } - if (tmp) - { - bm |= STAG; - } - - tmp = 0; - if (FAL_FIELD_FLG_TST(sw->field_flg, FAL_ACL_FIELD_MAC_CTAGGED)) - { - tmp |= ((sw->ctagged_mask & 0x1) << 16); - } - if (FAL_FIELD_FLG_TST(sw->field_flg, FAL_ACL_FIELD_MAC_CTAG_PRI)) - { - tmp |= ((sw->ctag_pri_mask & 0x7) << 13); - } - if (FAL_FIELD_FLG_TST(sw->field_flg, FAL_ACL_FIELD_MAC_CTAG_CFI)) - { - tmp |= ((sw->ctag_cfi_mask & 0x1) << 12); - } - if (FAL_FIELD_FLG_TST(sw->field_flg, FAL_ACL_FIELD_MAC_CTAG_VID)) - { - if (A_TRUE == - _dess_acl_field_care(sw->ctag_vid_op, sw->ctag_vid_val, - sw->ctag_vid_mask, 0xfff)) - { - tmp |= 0xfff; - } - } - if (tmp) - { - bm |= CTAG; - } - - if ((bm & CTAG) || (bm & STAG)) - { - *eh_mac = A_TRUE; - } - - if ((bm & TAG) || ((bm & DAH) && (bm & SAH))) - { - *b_mac = A_TRUE; - } -} - -static sw_error_t -_dess_acl_rule_ip4_parse(fal_acl_rule_t * sw, - hw_filter_t * hw, a_bool_t * b_care) -{ - *b_care = A_FALSE; - aos_mem_zero(&(hw->vlu[0]), sizeof (hw->vlu)); - aos_mem_zero(&(hw->msk[0]), sizeof (hw->msk)); - - FIELD_SET_MASK(MAC_RUL_M4, RULE_TYP, DESS_IP4_FILTER); - - if (FAL_FIELD_FLG_TST(sw->field_flg, FAL_ACL_FIELD_IP_DSCP)) - { - if (0x0 != sw->ip_dscp_mask) - { - *b_care = A_TRUE; - } - - sw->ip_dscp_val &= sw->ip_dscp_mask; - FIELD_SET(IP4_RUL_V2, IP4DSCPV, sw->ip_dscp_val); - FIELD_SET_MASK(IP4_RUL_M2, IP4DSCPM, sw->ip_dscp_mask); - } - - if (FAL_FIELD_FLG_TST(sw->field_flg, FAL_ACL_FIELD_IP_PROTO)) - { - if (0x0 != sw->ip_proto_mask) - { - *b_care = A_TRUE; - } - - sw->ip_proto_val &= sw->ip_proto_mask; - FIELD_SET(IP4_RUL_V2, IP4PROTV, sw->ip_proto_val); - FIELD_SET_MASK(IP4_RUL_M2, IP4PROTM, sw->ip_proto_mask); - } - - if (FAL_FIELD_FLG_TST(sw->field_flg, FAL_ACL_FIELD_IP4_SIP)) - { - if (0x0 != sw->src_ip4_mask) - { - *b_care = A_TRUE; - } - sw->src_ip4_val &= sw->src_ip4_mask; - hw->vlu[1] = sw->src_ip4_val; - hw->msk[1] = sw->src_ip4_mask; - } - - if (FAL_FIELD_FLG_TST(sw->field_flg, FAL_ACL_FIELD_IP4_DIP)) - { - if (0x0 != sw->dest_ip4_mask) - { - *b_care = A_TRUE; - } - sw->dest_ip4_val &= sw->dest_ip4_mask; - hw->vlu[0] = sw->dest_ip4_val; - hw->msk[0] = sw->dest_ip4_mask; - } - - if ((FAL_FIELD_FLG_TST(sw->field_flg, FAL_ACL_FIELD_L4_SPORT)) - && ((FAL_FIELD_FLG_TST(sw->field_flg, FAL_ACL_FIELD_ICMP_TYPE)) - || (FAL_FIELD_FLG_TST(sw->field_flg, FAL_ACL_FIELD_ICMP_CODE)))) - { - return SW_BAD_PARAM; - } - - FIELD_SET_MASK(IP4_RUL_M3, IP4SPORTM_EN, 1); - if (FAL_FIELD_FLG_TST(sw->field_flg, FAL_ACL_FIELD_L4_SPORT)) - { - if ((FAL_ACL_FIELD_MASK != sw->src_l4port_op) - && (FAL_ACL_FIELD_RANGE != sw->src_l4port_op) - && (FAL_ACL_FIELD_LE != sw->src_l4port_op) - && (FAL_ACL_FIELD_GE != sw->src_l4port_op)) - { - return SW_NOT_SUPPORTED; - } - - if (A_FALSE == - _dess_acl_field_care(sw->src_l4port_op, sw->src_l4port_val, - sw->src_l4port_mask, 0xffff)) - { - if (FAL_ACL_FIELD_MASK == sw->src_l4port_op) - { - sw->src_l4port_op = FAL_ACL_FIELD_RANGE; - sw->src_l4port_val = 0; - sw->src_l4port_mask = 0xffff; - } - } - *b_care = A_TRUE; - - FIELD_SET_MASK(IP4_RUL_M3, IP4SPORTM_EN, 0); - if (FAL_ACL_FIELD_MASK == sw->src_l4port_op) - { - sw->src_l4port_val &= sw->src_l4port_mask; - FIELD_SET(IP4_RUL_V3, IP4SPORTV, sw->src_l4port_val); - FIELD_SET_MASK(IP4_RUL_M3, IP4SPORTM, sw->src_l4port_mask); - FIELD_SET_MASK(IP4_RUL_M3, IP4SPORTM_EN, 1); - } - else if (FAL_ACL_FIELD_RANGE == sw->src_l4port_op) - { - FIELD_SET(IP4_RUL_V3, IP4SPORTV, sw->src_l4port_val); - FIELD_SET_MASK(IP4_RUL_M3, IP4SPORTM, sw->src_l4port_mask); - } - else if (FAL_ACL_FIELD_LE == sw->src_l4port_op) - { - FIELD_SET(IP4_RUL_V3, IP4SPORTV, 0); - FIELD_SET_MASK(IP4_RUL_M3, IP4SPORTM, sw->src_l4port_val); - } - else - { - FIELD_SET(IP4_RUL_V3, IP4SPORTV, sw->src_l4port_val); - FIELD_SET_MASK(IP4_RUL_M3, IP4SPORTM, 0xffff); - } - } - - FIELD_SET_MASK(IP4_RUL_M3, IP4DPORTM_EN, 1); - if (FAL_FIELD_FLG_TST(sw->field_flg, FAL_ACL_FIELD_L4_DPORT)) - { - if ((FAL_ACL_FIELD_MASK != sw->dest_l4port_op) - && (FAL_ACL_FIELD_RANGE != sw->dest_l4port_op) - && (FAL_ACL_FIELD_LE != sw->dest_l4port_op) - && (FAL_ACL_FIELD_GE != sw->dest_l4port_op)) - { - return SW_NOT_SUPPORTED; - } - - if (A_FALSE == - _dess_acl_field_care(sw->dest_l4port_op, sw->dest_l4port_val, - sw->dest_l4port_mask, 0xffff)) - { - if (FAL_ACL_FIELD_MASK == sw->dest_l4port_op) - { - sw->dest_l4port_op = FAL_ACL_FIELD_RANGE; - sw->dest_l4port_val = 0; - sw->dest_l4port_mask = 0xffff; - } - } - *b_care = A_TRUE; - - FIELD_SET_MASK(IP4_RUL_M3, IP4DPORTM_EN, 0); - if (FAL_ACL_FIELD_MASK == sw->dest_l4port_op) - { - sw->dest_l4port_val &= sw->dest_l4port_mask; - FIELD_SET(IP4_RUL_V2, IP4DPORTV, sw->dest_l4port_val); - FIELD_SET_MASK(IP4_RUL_M2, IP4DPORTM, sw->dest_l4port_mask); - FIELD_SET_MASK(IP4_RUL_M3, IP4DPORTM_EN, 1); - } - else if (FAL_ACL_FIELD_RANGE == sw->dest_l4port_op) - { - FIELD_SET(IP4_RUL_V2, IP4DPORTV, sw->dest_l4port_val); - FIELD_SET_MASK(IP4_RUL_M2, IP4DPORTM, sw->dest_l4port_mask); - } - else if (FAL_ACL_FIELD_LE == sw->dest_l4port_op) - { - FIELD_SET(IP4_RUL_V2, IP4DPORTV, 0); - FIELD_SET_MASK(IP4_RUL_M2, IP4DPORTM, sw->dest_l4port_val); - } - else - { - FIELD_SET(IP4_RUL_V2, IP4DPORTV, sw->dest_l4port_val); - FIELD_SET_MASK(IP4_RUL_M2, IP4DPORTM, 0xffff); - } - } - - if (FAL_FIELD_FLG_TST(sw->field_flg, FAL_ACL_FIELD_ICMP_TYPE)) - { - if (0x0 != sw->icmp_type_mask) - { - *b_care = A_TRUE; - } - FIELD_SET(IP4_RUL_V3, ICMP_EN, 1); - - sw->icmp_type_val &= sw->icmp_type_mask; - FIELD_SET(IP4_RUL_V3, IP4ICMPTYPV, sw->icmp_type_val); - FIELD_SET_MASK(IP4_RUL_M3, IP4ICMPTYPM, sw->icmp_type_mask); - } - - if (FAL_FIELD_FLG_TST(sw->field_flg, FAL_ACL_FIELD_ICMP_CODE)) - { - if (0x0 != sw->icmp_code_mask) - { - *b_care = A_TRUE; - } - FIELD_SET(IP4_RUL_V3, ICMP_EN, 1); - - sw->icmp_code_val &= sw->icmp_code_mask; - FIELD_SET(IP4_RUL_V3, IP4ICMPCODEV, sw->icmp_code_val); - FIELD_SET_MASK(IP4_RUL_M3, IP4ICMPCODEM, sw->icmp_code_mask); - } - - if (FAL_FIELD_FLG_TST(sw->field_flg, FAL_ACL_FIELD_TCP_FLAG)) - { - if (0x0 != sw->tcp_flag_mask) - { - *b_care = A_TRUE; - } - - sw->tcp_flag_val &= sw->tcp_flag_mask; - FIELD_SET(IP4_RUL_V3, IP4TCPFLAGV, sw->tcp_flag_val); - FIELD_SET_MASK(IP4_RUL_M3, IP4TCPFLAGM, sw->tcp_flag_mask); - } - - if (FAL_FIELD_FLG_TST(sw->field_flg, FAL_ACL_FIELD_RIPV1)) - { - if (0x0 != sw->ripv1_mask) - { - *b_care = A_TRUE; - } - - sw->ripv1_val &= sw->ripv1_mask; - FIELD_SET(IP4_RUL_V3, IP4RIPV, sw->ripv1_val); - FIELD_SET_MASK(IP4_RUL_M3, IP4RIPM, sw->ripv1_mask); - } - - if (FAL_FIELD_FLG_TST(sw->field_flg, FAL_ACL_FIELD_DHCPV4)) - { - if (0x0 != sw->dhcpv4_mask) - { - *b_care = A_TRUE; - } - - sw->dhcpv4_val &= sw->dhcpv4_mask; - FIELD_SET(IP4_RUL_V3, IP4DHCPV, sw->dhcpv4_val); - FIELD_SET_MASK(IP4_RUL_M3, IP4DHCPM, sw->dhcpv4_mask); - } - - if (FAL_FIELD_FLG_TST(sw->field_flg, FAL_ACL_FIELD_INVERSE_ALL)) - { - FIELD_SET(MAC_RUL_V4, RULE_INV, 1); - } - - return SW_OK; -} - -static sw_error_t -_dess_acl_rule_ip6r1_parse(fal_acl_rule_t * sw, - hw_filter_t * hw, a_bool_t * b_care) -{ - a_uint32_t i; - - *b_care = A_FALSE; - aos_mem_zero(&(hw->vlu[0]), sizeof (hw->vlu)); - aos_mem_zero(&(hw->msk[0]), sizeof (hw->msk)); - - FIELD_SET_MASK(MAC_RUL_M4, RULE_TYP, DESS_IP6R1_FILTER); - - if (FAL_FIELD_FLG_TST(sw->field_flg, FAL_ACL_FIELD_IP6_DIP)) - { - for (i = 0; i < 4; i++) - { - if (0x0 != sw->dest_ip6_mask.ul[i]) - { - *b_care = A_TRUE; - } - - sw->dest_ip6_val.ul[3 - i] &= sw->dest_ip6_mask.ul[3 - i]; - hw->vlu[i] = sw->dest_ip6_val.ul[3 - i]; - hw->msk[i] = sw->dest_ip6_mask.ul[3 - i]; - } - } - - if (FAL_FIELD_FLG_TST(sw->field_flg, FAL_ACL_FIELD_INVERSE_ALL)) - { - FIELD_SET(MAC_RUL_V4, RULE_INV, 1); - } - - return SW_OK; -} - -static sw_error_t -_dess_acl_rule_ip6r2_parse(fal_acl_rule_t * sw, - hw_filter_t * hw, a_bool_t * b_care) -{ - a_uint32_t i; - - *b_care = A_FALSE; - aos_mem_zero(&(hw->vlu[0]), sizeof (hw->vlu)); - aos_mem_zero(&(hw->msk[0]), sizeof (hw->msk)); - - FIELD_SET_MASK(MAC_RUL_M4, RULE_TYP, DESS_IP6R2_FILTER); - - if (FAL_FIELD_FLG_TST(sw->field_flg, FAL_ACL_FIELD_IP6_SIP)) - { - for (i = 0; i < 4; i++) - { - if (0x0 != sw->src_ip6_mask.ul[i]) - { - *b_care = A_TRUE; - } - - sw->src_ip6_val.ul[3 - i] &= sw->src_ip6_mask.ul[3 - i]; - hw->vlu[i] = sw->src_ip6_val.ul[3 - i]; - hw->msk[i] = sw->src_ip6_mask.ul[3 - i]; - } - } - - if (FAL_FIELD_FLG_TST(sw->field_flg, FAL_ACL_FIELD_INVERSE_ALL)) - { - FIELD_SET(MAC_RUL_V4, RULE_INV, 1); - } - - return SW_OK; -} - -static sw_error_t -_dess_acl_rule_ip6r3_parse(fal_acl_rule_t * sw, - hw_filter_t * hw, a_bool_t * b_care) -{ - *b_care = A_FALSE; - aos_mem_zero(&(hw->vlu[0]), sizeof (hw->vlu)); - aos_mem_zero(&(hw->msk[0]), sizeof (hw->msk)); - - FIELD_SET_MASK(MAC_RUL_M4, RULE_TYP, DESS_IP6R3_FILTER); - - if (FAL_FIELD_FLG_TST(sw->field_flg, FAL_ACL_FIELD_IP6_LABEL)) - { - if (0x0 != sw->ip6_lable_mask) - { - *b_care = A_TRUE; - } - - sw->ip6_lable_val &= sw->ip6_lable_mask; - FIELD_SET(IP6_RUL3_V1, IP6LABEL1V, sw->ip6_lable_val); - FIELD_SET_MASK(IP6_RUL3_M1, IP6LABEL1M, sw->ip6_lable_mask); - - FIELD_SET(IP6_RUL3_V2, IP6LABEL2V, (sw->ip6_lable_val >> 16)); - FIELD_SET_MASK(IP6_RUL3_M2, IP6LABEL2M, (sw->ip6_lable_mask >> 16)); - } - - if (FAL_FIELD_FLG_TST(sw->field_flg, FAL_ACL_FIELD_IP_PROTO)) - { - if (0x0 != sw->ip_proto_mask) - { - *b_care = A_TRUE; - } - - sw->ip_proto_val &= sw->ip_proto_mask; - FIELD_SET(IP6_RUL3_V0, IP6PROTV, sw->ip_proto_val); - FIELD_SET_MASK(IP6_RUL3_M0, IP6PROTM, sw->ip_proto_mask); - } - - if (FAL_FIELD_FLG_TST(sw->field_flg, FAL_ACL_FIELD_IP_DSCP)) - { - if (0x0 != sw->ip_dscp_mask) - { - *b_care = A_TRUE; - } - - sw->ip_dscp_val &= sw->ip_dscp_mask; - FIELD_SET(IP6_RUL3_V0, IP6DSCPV, sw->ip_dscp_val); - FIELD_SET_MASK(IP6_RUL3_M0, IP6DSCPM, sw->ip_dscp_mask); - } - - if ((FAL_FIELD_FLG_TST(sw->field_flg, FAL_ACL_FIELD_L4_SPORT)) - && ((FAL_FIELD_FLG_TST(sw->field_flg, FAL_ACL_FIELD_ICMP_TYPE)) - || (FAL_FIELD_FLG_TST(sw->field_flg, FAL_ACL_FIELD_ICMP_CODE)))) - { - return SW_BAD_PARAM; - } - - FIELD_SET_MASK(IP6_RUL3_M3, IP6SPORTM_EN, 1); - if (FAL_FIELD_FLG_TST(sw->field_flg, FAL_ACL_FIELD_L4_SPORT)) - { - if ((FAL_ACL_FIELD_MASK != sw->src_l4port_op) - && (FAL_ACL_FIELD_RANGE != sw->src_l4port_op) - && (FAL_ACL_FIELD_LE != sw->src_l4port_op) - && (FAL_ACL_FIELD_GE != sw->src_l4port_op)) - { - return SW_NOT_SUPPORTED; - } - - if (A_FALSE == - _dess_acl_field_care(sw->src_l4port_op, sw->src_l4port_val, - sw->src_l4port_mask, 0xffff)) - { - if (FAL_ACL_FIELD_MASK == sw->src_l4port_op) - { - sw->src_l4port_op = FAL_ACL_FIELD_RANGE; - sw->src_l4port_val = 0; - sw->src_l4port_mask = 0xffff; - } - } - *b_care = A_TRUE; - - FIELD_SET_MASK(IP6_RUL3_M3, IP6SPORTM_EN, 0); - if (FAL_ACL_FIELD_MASK == sw->src_l4port_op) - { - sw->src_l4port_val &= sw->src_l4port_mask; - FIELD_SET(IP6_RUL3_V3, IP6SPORTV, sw->src_l4port_val); - FIELD_SET_MASK(IP6_RUL3_M3, IP6SPORTM, sw->src_l4port_mask); - FIELD_SET_MASK(IP6_RUL3_M3, IP6SPORTM_EN, 1); - - } - else if (FAL_ACL_FIELD_RANGE == sw->src_l4port_op) - { - FIELD_SET(IP6_RUL3_V3, IP6SPORTV, sw->src_l4port_val); - FIELD_SET_MASK(IP6_RUL3_M3, IP6SPORTM, sw->src_l4port_mask); - - } - else if (FAL_ACL_FIELD_LE == sw->src_l4port_op) - { - FIELD_SET(IP6_RUL3_V3, IP6SPORTV, 0); - FIELD_SET_MASK(IP6_RUL3_M3, IP6SPORTM, sw->src_l4port_val); - - } - else - { - FIELD_SET(IP6_RUL3_V3, IP6SPORTV, sw->src_l4port_val); - FIELD_SET_MASK(IP6_RUL3_M3, IP6SPORTM, 0xffff); - } - } - - FIELD_SET_MASK(IP6_RUL3_M3, IP6DPORTM_EN, 1); - if (FAL_FIELD_FLG_TST(sw->field_flg, FAL_ACL_FIELD_L4_DPORT)) - { - if ((FAL_ACL_FIELD_MASK != sw->dest_l4port_op) - && (FAL_ACL_FIELD_RANGE != sw->dest_l4port_op) - && (FAL_ACL_FIELD_LE != sw->dest_l4port_op) - && (FAL_ACL_FIELD_GE != sw->dest_l4port_op)) - { - return SW_NOT_SUPPORTED; - } - - if (A_FALSE == - _dess_acl_field_care(sw->dest_l4port_op, sw->dest_l4port_val, - sw->dest_l4port_mask, 0xffff)) - { - if (FAL_ACL_FIELD_MASK == sw->dest_l4port_op) - { - sw->dest_l4port_op = FAL_ACL_FIELD_RANGE; - sw->dest_l4port_val = 0; - sw->dest_l4port_mask = 0xffff; - } - } - *b_care = A_TRUE; - - FIELD_SET_MASK(IP6_RUL3_M3, IP6DPORTM_EN, 0); - if (FAL_ACL_FIELD_MASK == sw->dest_l4port_op) - { - sw->dest_l4port_val &= sw->dest_l4port_mask; - FIELD_SET(IP6_RUL3_V2, IP6DPORTV, sw->dest_l4port_val); - FIELD_SET_MASK(IP6_RUL3_M2, IP6DPORTM, sw->dest_l4port_mask); - FIELD_SET_MASK(IP6_RUL3_M3, IP6DPORTM_EN, 1); - } - else if (FAL_ACL_FIELD_RANGE == sw->dest_l4port_op) - { - FIELD_SET(IP6_RUL3_V2, IP6DPORTV, sw->dest_l4port_val); - FIELD_SET_MASK(IP6_RUL3_M2, IP6DPORTM, sw->dest_l4port_mask); - } - else if (FAL_ACL_FIELD_LE == sw->dest_l4port_op) - { - FIELD_SET(IP6_RUL3_V2, IP6DPORTV, 0); - FIELD_SET_MASK(IP6_RUL3_M2, IP6DPORTM, sw->dest_l4port_val); - } - else - { - FIELD_SET(IP6_RUL3_V2, IP6DPORTV, sw->dest_l4port_val); - FIELD_SET_MASK(IP6_RUL3_M2, IP6DPORTM, 0xffff); - } - } - - if (FAL_FIELD_FLG_TST(sw->field_flg, FAL_ACL_FIELD_ICMP_TYPE)) - { - if (0x0 != sw->icmp_type_mask) - { - *b_care = A_TRUE; - } - FIELD_SET(IP6_RUL3_V3, ICMP6_EN, 1); - - sw->icmp_type_val &= sw->icmp_type_mask; - FIELD_SET(IP6_RUL3_V3, IP6ICMPTYPV, sw->icmp_type_val); - FIELD_SET_MASK(IP6_RUL3_M3, IP6ICMPTYPM, sw->icmp_type_mask); - } - - if (FAL_FIELD_FLG_TST(sw->field_flg, FAL_ACL_FIELD_ICMP_CODE)) - { - if (0x0 != sw->icmp_code_mask) - { - *b_care = A_TRUE; - } - FIELD_SET(IP6_RUL3_V3, ICMP6_EN, 1); - - sw->icmp_code_val &= sw->icmp_code_mask; - FIELD_SET(IP6_RUL3_V3, IP6ICMPCODEV, sw->icmp_code_val); - FIELD_SET_MASK(IP6_RUL3_M3, IP6ICMPCODEM, sw->icmp_code_mask); - } - - if (FAL_FIELD_FLG_TST(sw->field_flg, FAL_ACL_FIELD_TCP_FLAG)) - { - if (0x0 != sw->tcp_flag_mask) - { - *b_care = A_TRUE; - } - - sw->tcp_flag_val &= sw->tcp_flag_mask; - FIELD_SET(IP6_RUL3_V3, IP6TCPFLAGV, sw->tcp_flag_val); - FIELD_SET_MASK(IP6_RUL3_M3, IP6TCPFLAGM, sw->tcp_flag_mask); - } - - if (FAL_FIELD_FLG_TST(sw->field_flg, FAL_ACL_FIELD_DHCPV6)) - { - if (0x0 != sw->dhcpv6_mask) - { - *b_care = A_TRUE; - } - - sw->dhcpv6_val &= sw->dhcpv6_mask; - FIELD_SET(IP6_RUL3_V3, IP6DHCPV, sw->dhcpv6_val); - FIELD_SET_MASK(IP6_RUL3_M3, IP6DHCPM, sw->dhcpv6_mask); - } - - if (FAL_FIELD_FLG_TST(sw->field_flg, FAL_ACL_FIELD_INVERSE_ALL)) - { - FIELD_SET(MAC_RUL_V4, RULE_INV, 1); - } - - return SW_OK; -} - -static sw_error_t -_dess_acl_rule_udf_parse(fal_acl_rule_t * sw, - hw_filter_t * hw, a_bool_t * b_care) -{ - a_uint32_t i; - - *b_care = A_FALSE; - aos_mem_zero(&(hw->vlu[0]), sizeof (hw->vlu)); - aos_mem_zero(&(hw->msk[0]), sizeof (hw->msk)); - - FIELD_SET_MASK(MAC_RUL_M4, RULE_TYP, DESS_UDF_FILTER); - - if (!FAL_FIELD_FLG_TST(sw->field_flg, FAL_ACL_FIELD_UDF)) - { - if (FAL_ACL_RULE_UDF == sw->rule_type) - { - if (FAL_FIELD_FLG_TST(sw->field_flg, FAL_ACL_FIELD_INVERSE_ALL)) - { - FIELD_SET(MAC_RUL_V4, RULE_INV, 1); - } - *b_care = A_TRUE; - } - return SW_OK; - } - - if (DESS_MAX_UDF_LENGTH < sw->udf_len) - { - return SW_NOT_SUPPORTED; - } - - *b_care = A_TRUE; - for (i = 0; i < sw->udf_len; i++) - { - hw->vlu[3 - i / 4] |= - ((sw->udf_mask[i] & sw->udf_val[i]) << (24 - 8 * (i % 4))); - hw->msk[3 - i / 4] |= ((sw->udf_mask[i]) << (24 - 8 * (i % 4))); - } - - if (FAL_FIELD_FLG_TST(sw->field_flg, FAL_ACL_FIELD_INVERSE_ALL)) - { - FIELD_SET(MAC_RUL_V4, RULE_INV, 1); - } - - return SW_OK; -} - -static sw_error_t -_dess_acl_action_parse(a_uint32_t dev_id, const fal_acl_rule_t * sw, - hw_filter_t * hw) -{ - fal_pbmp_t des_pts; - - aos_mem_zero(&(hw->act[0]), sizeof (hw->act)); - - if (FAL_ACTION_FLG_TST(sw->action_flg, FAL_ACL_ACTION_MATCH_TRIGGER_INTR)) - { - FIELD_SET_ACTION(ACL_RSLT2, TRIGGER_INTR, 1); - } - - /* FAL_ACL_ACTION_PERMIT need't process */ - - if ((FAL_ACTION_FLG_TST(sw->action_flg, FAL_ACL_ACTION_RDTCPU)) - && (FAL_ACTION_FLG_TST(sw->action_flg, FAL_ACL_ACTION_CPYCPU))) - { - return SW_BAD_PARAM; - } - - if (FAL_ACTION_FLG_TST(sw->action_flg, FAL_ACL_ACTION_RDTCPU)) - { - FIELD_SET_ACTION(ACL_RSLT2, FWD_CMD, 0x3); - } - - if (FAL_ACTION_FLG_TST(sw->action_flg, FAL_ACL_ACTION_CPYCPU)) - { - FIELD_SET_ACTION(ACL_RSLT2, FWD_CMD, 0x1); - } - - if (FAL_ACTION_FLG_TST(sw->action_flg, FAL_ACL_ACTION_DENY)) - { - FIELD_SET_ACTION(ACL_RSLT2, FWD_CMD, 0x7); - } - - if (FAL_ACTION_FLG_TST(sw->action_flg, FAL_ACL_ACTION_MIRROR)) - { - FIELD_SET_ACTION(ACL_RSLT2, MIRR_EN, 1); - } - - if (FAL_ACTION_FLG_TST(sw->action_flg, FAL_ACL_ACTION_REDPT)) - { - FIELD_SET_ACTION(ACL_RSLT2, DES_PORT_EN, 1); - - des_pts = (sw->ports >> 3) & 0xf; - FIELD_SET_ACTION(ACL_RSLT2, DES_PORT1, des_pts); - - des_pts = sw->ports & 0x7; - FIELD_SET_ACTION(ACL_RSLT1, DES_PORT0, des_pts); - } - - if (FAL_ACTION_FLG_TST(sw->action_flg, FAL_ACL_ACTION_REMARK_UP)) - { - return SW_NOT_SUPPORTED; - } - - if (FAL_ACTION_FLG_TST(sw->action_flg, FAL_ACL_ACTION_REMARK_QUEUE)) - { - FIELD_SET_ACTION(ACL_RSLT1, PRI_QU_EN, 1); - FIELD_SET_ACTION(ACL_RSLT1, PRI_QU, sw->queue); - } - - if ((FAL_ACTION_FLG_TST(sw->action_flg, FAL_ACL_ACTION_MODIFY_VLAN)) - || (FAL_ACTION_FLG_TST(sw->action_flg, FAL_ACL_ACTION_NEST_VLAN))) - { - return SW_NOT_SUPPORTED; - } - - if (FAL_ACTION_FLG_TST(sw->action_flg, FAL_ACL_ACTION_REMARK_DSCP)) - { - FIELD_SET_ACTION(ACL_RSLT1, DSCPV, sw->dscp); - FIELD_SET_ACTION(ACL_RSLT1, DSCP_REMAP, 1); - } - - FIELD_SET_ACTION(ACL_RSLT0, STAGVID, sw->stag_vid); - if (FAL_ACTION_FLG_TST(sw->action_flg, FAL_ACL_ACTION_REMARK_STAG_VID)) - { - FIELD_SET_ACTION(ACL_RSLT1, TRANS_SVID_CHG, 1); - } - - if (FAL_ACTION_FLG_TST(sw->action_flg, FAL_ACL_ACTION_REMARK_STAG_PRI)) - { - FIELD_SET_ACTION(ACL_RSLT0, STAGPRI, sw->stag_pri); - FIELD_SET_ACTION(ACL_RSLT1, STAG_PRI_REMAP, 1); - } - - if (FAL_ACTION_FLG_TST(sw->action_flg, FAL_ACL_ACTION_REMARK_STAG_DEI)) - { - FIELD_SET_ACTION(ACL_RSLT0, STAGDEI, sw->stag_dei); - FIELD_SET_ACTION(ACL_RSLT1, STAG_DEI_CHG, 1); - } - - FIELD_SET_ACTION(ACL_RSLT0, CTAGVID, sw->ctag_vid); - if (FAL_ACTION_FLG_TST(sw->action_flg, FAL_ACL_ACTION_REMARK_CTAG_VID)) - { - FIELD_SET_ACTION(ACL_RSLT1, TRANS_CVID_CHG, 1); - } - - if (FAL_ACTION_FLG_TST(sw->action_flg, FAL_ACL_ACTION_REMARK_CTAG_PRI)) - { - FIELD_SET_ACTION(ACL_RSLT0, CTAGPRI, sw->ctag_pri); - FIELD_SET_ACTION(ACL_RSLT1, CTAG_PRI_REMAP, 1); - } - - if (FAL_ACTION_FLG_TST(sw->action_flg, FAL_ACL_ACTION_REMARK_CTAG_CFI)) - { - FIELD_SET_ACTION(ACL_RSLT0, CTAGCFI, sw->ctag_cfi); - FIELD_SET_ACTION(ACL_RSLT1, CTAG_CFI_CHG, 1); - } - - if (FAL_ACTION_FLG_TST(sw->action_flg, FAL_ACL_ACTION_REMARK_LOOKUP_VID)) - { - FIELD_SET_ACTION(ACL_RSLT1, LOOK_VID_CHG, 1); - } - - if (FAL_ACTION_FLG_TST(sw->action_flg, FAL_ACL_ACTION_POLICER_EN)) - { - FIELD_SET_ACTION(ACL_RSLT2, POLICER_PTR, sw->policer_ptr); - FIELD_SET_ACTION(ACL_RSLT2, POLICER_EN, 1); - } - - if ((FAL_ACTION_FLG_TST(sw->action_flg, FAL_ACL_ACTION_ARP_EN)) - && (FAL_ACTION_FLG_TST(sw->action_flg, FAL_ACL_ACTION_WCMP_EN))) - { - return SW_NOT_SUPPORTED; - } - - if (FAL_ACTION_FLG_TST(sw->action_flg, FAL_ACL_ACTION_ARP_EN)) - { - FIELD_SET_ACTION(ACL_RSLT1, ARP_PTR, sw->arp_ptr); - FIELD_SET_ACTION(ACL_RSLT1, ARP_PTR_EN, 1); - } - - if (FAL_ACTION_FLG_TST(sw->action_flg, FAL_ACL_ACTION_WCMP_EN)) - { - FIELD_SET_ACTION(ACL_RSLT1, ARP_PTR, sw->wcmp_ptr); - FIELD_SET_ACTION(ACL_RSLT1, WCMP_EN, 1); - FIELD_SET_ACTION(ACL_RSLT1, ARP_PTR_EN, 1); - } - - FIELD_SET_ACTION(ACL_RSLT1, FORCE_L3_MODE, 0x0); - if (FAL_ACTION_FLG_TST(sw->action_flg, FAL_ACL_ACTION_POLICY_FORWARD_EN)) - { - if (FAL_ACL_POLICY_ROUTE == sw->policy_fwd) - { - return SW_NOT_SUPPORTED; - } - else if (FAL_ACL_POLICY_SNAT == sw->policy_fwd) - { - FIELD_SET_ACTION(ACL_RSLT1, FORCE_L3_MODE, 0x1); - } - else if (FAL_ACL_POLICY_DNAT == sw->policy_fwd) - { - FIELD_SET_ACTION(ACL_RSLT1, FORCE_L3_MODE, 0x2); - } - else if (FAL_ACL_POLICY_RESERVE == sw->policy_fwd) - { - FIELD_SET_ACTION(ACL_RSLT1, FORCE_L3_MODE, 0x3); - } - else - { - return SW_BAD_PARAM; - } - } - - if (FAL_ACTION_FLG_TST(sw->action_flg, FAL_ACL_ACTION_BYPASS_EGRESS_TRANS)) - { - FIELD_SET_ACTION(ACL_RSLT2, EG_BYPASS, 1); - } - - if (FAL_ACTION_FLG_TST(sw->action_flg, FAL_ACL_ACTION_MATCH_TRIGGER_INTR)) - { - FIELD_SET_ACTION(ACL_RSLT2, TRIGGER_INTR, 1); - } - - return SW_OK; -} - -static sw_error_t -_dess_acl_rule_bmac_reparse(fal_acl_rule_t * sw, const hw_filter_t * hw) -{ - a_uint32_t mask_en; - - /* destnation mac address */ - FIELD_GET(MAC_RUL_V0, DAV_BYTE2, sw->dest_mac_val.uc[2]); - FIELD_GET(MAC_RUL_V0, DAV_BYTE3, sw->dest_mac_val.uc[3]); - FIELD_GET(MAC_RUL_V0, DAV_BYTE4, sw->dest_mac_val.uc[4]); - FIELD_GET(MAC_RUL_V0, DAV_BYTE5, sw->dest_mac_val.uc[5]); - FIELD_GET(MAC_RUL_V1, DAV_BYTE0, sw->dest_mac_val.uc[0]); - FIELD_GET(MAC_RUL_V1, DAV_BYTE1, sw->dest_mac_val.uc[1]); - - FIELD_GET_MASK(MAC_RUL_M0, DAM_BYTE2, sw->dest_mac_mask.uc[2]); - FIELD_GET_MASK(MAC_RUL_M0, DAM_BYTE3, sw->dest_mac_mask.uc[3]); - FIELD_GET_MASK(MAC_RUL_M0, DAM_BYTE4, sw->dest_mac_mask.uc[4]); - FIELD_GET_MASK(MAC_RUL_M0, DAM_BYTE5, sw->dest_mac_mask.uc[5]); - FIELD_GET_MASK(MAC_RUL_M1, DAM_BYTE0, sw->dest_mac_mask.uc[0]); - FIELD_GET_MASK(MAC_RUL_M1, DAM_BYTE1, sw->dest_mac_mask.uc[1]); - if (A_FALSE == _dess_acl_zero_addr(sw->dest_mac_mask)) - { - FAL_FIELD_FLG_SET(sw->field_flg, FAL_ACL_FIELD_MAC_DA); - } - - /* source mac address */ - FIELD_GET(MAC_RUL_V2, SAV_BYTE0, sw->src_mac_val.uc[0]); - FIELD_GET(MAC_RUL_V2, SAV_BYTE1, sw->src_mac_val.uc[1]); - FIELD_GET(MAC_RUL_V2, SAV_BYTE2, sw->src_mac_val.uc[2]); - FIELD_GET(MAC_RUL_V2, SAV_BYTE3, sw->src_mac_val.uc[3]); - FIELD_GET(MAC_RUL_V1, SAV_BYTE4, sw->src_mac_val.uc[4]); - FIELD_GET(MAC_RUL_V1, SAV_BYTE5, sw->src_mac_val.uc[5]); - - FIELD_GET_MASK(MAC_RUL_M2, SAM_BYTE0, sw->src_mac_mask.uc[0]); - FIELD_GET_MASK(MAC_RUL_M2, SAM_BYTE1, sw->src_mac_mask.uc[1]); - FIELD_GET_MASK(MAC_RUL_M2, SAM_BYTE2, sw->src_mac_mask.uc[2]); - FIELD_GET_MASK(MAC_RUL_M2, SAM_BYTE3, sw->src_mac_mask.uc[3]); - FIELD_GET_MASK(MAC_RUL_M1, SAM_BYTE4, sw->src_mac_mask.uc[4]); - FIELD_GET_MASK(MAC_RUL_M1, SAM_BYTE5, sw->src_mac_mask.uc[5]); - if (A_FALSE == _dess_acl_zero_addr(sw->src_mac_mask)) - { - FAL_FIELD_FLG_SET(sw->field_flg, FAL_ACL_FIELD_MAC_SA); - } - - /* ethernet type */ - FIELD_GET(MAC_RUL_V3, ETHTYPV, sw->ethtype_val); - FIELD_GET_MASK(MAC_RUL_M3, ETHTYPM, sw->ethtype_mask); - if (0x0 != sw->ethtype_mask) - { - FAL_FIELD_FLG_SET(sw->field_flg, FAL_ACL_FIELD_MAC_ETHTYPE); - } - - /* packet tagged */ - FIELD_GET_MASK(MAC_RUL_M4, TAGGEDV, sw->tagged_val); - FIELD_GET_MASK(MAC_RUL_M4, TAGGEDM, sw->tagged_mask); - if (0x0 != sw->tagged_mask) - { - FAL_FIELD_FLG_SET(sw->field_flg, FAL_ACL_FIELD_MAC_TAGGED); - } - - /* vlan priority */ - FIELD_GET(MAC_RUL_V3, VLANPRIV, sw->up_val); - FIELD_GET_MASK(MAC_RUL_M3, VLANPRIM, sw->up_mask); - if (0x0 != sw->up_mask) - { - FAL_FIELD_FLG_SET(sw->field_flg, FAL_ACL_FIELD_MAC_UP); - } - - /* vlanid */ - FIELD_GET(MAC_RUL_V3, VLANIDV, sw->vid_val); - FIELD_GET_MASK(MAC_RUL_M3, VLANIDM, sw->vid_mask); - FIELD_GET_MASK(MAC_RUL_M4, VIDMSK, mask_en); - if (mask_en) - { - sw->vid_op = FAL_ACL_FIELD_MASK; - } - else - { - sw->vid_op = FAL_ACL_FIELD_RANGE; - } - - if (A_TRUE == - _dess_acl_field_care(sw->vid_op, (a_uint32_t) sw->vid_val, - (a_uint32_t) sw->vid_mask, 0xfff)) - { - FAL_FIELD_FLG_SET(sw->field_flg, FAL_ACL_FIELD_MAC_VID); - } - - /* vlan cfi */ - FIELD_GET(MAC_RUL_V3, VLANCFIV, sw->cfi_val); - FIELD_GET_MASK(MAC_RUL_M3, VLANCFIM, sw->cfi_mask); - if (0x0 != sw->cfi_mask) - { - FAL_FIELD_FLG_SET(sw->field_flg, FAL_ACL_FIELD_MAC_CFI); - } - - FIELD_GET(MAC_RUL_V4, RULE_INV, mask_en); - if (mask_en) - { - FAL_FIELD_FLG_SET(sw->field_flg, FAL_ACL_FIELD_INVERSE_ALL); - } - - return SW_OK; -} - -static sw_error_t -_dess_acl_rule_ehmac_reparse(fal_acl_rule_t * sw, const hw_filter_t * hw) -{ - a_uint32_t i, mask_en, data; - - FIELD_GET(EHMAC_RUL_V3, DA_EN, data); - if (data) - { - for (i = 2; i < 6; i++) - { - sw->dest_mac_val.uc[i] = ((hw->vlu[0]) >> ((5 - i) << 3)) & 0xff; - sw->dest_mac_mask.uc[i] = ((hw->msk[0]) >> ((5 - i) << 3)) & 0xff; - } - - for (i = 0; i < 2; i++) - { - sw->dest_mac_val.uc[i] = ((hw->vlu[1]) >> ((1 - i) << 3)) & 0xff; - sw->dest_mac_mask.uc[i] = ((hw->msk[1]) >> ((1 - i) << 3)) & 0xff; - } - - if (A_FALSE == _dess_acl_zero_addr(sw->dest_mac_mask)) - { - FAL_FIELD_FLG_SET(sw->field_flg, FAL_ACL_FIELD_MAC_DA); - } - - FIELD_GET(EHMAC_RUL_V2, SAV_BYTE3, sw->src_mac_val.uc[3]); - FIELD_GET(EHMAC_RUL_V1, SAV_BYTE4, sw->src_mac_val.uc[4]); - FIELD_GET(EHMAC_RUL_V1, SAV_BYTE5, sw->src_mac_val.uc[5]); - - FIELD_GET_MASK(EHMAC_RUL_M2, SAM_BYTE3, sw->src_mac_mask.uc[3]); - FIELD_GET_MASK(EHMAC_RUL_M1, SAM_BYTE4, sw->src_mac_mask.uc[4]); - FIELD_GET_MASK(EHMAC_RUL_M1, SAM_BYTE5, sw->src_mac_mask.uc[5]); - - if (A_FALSE == _dess_acl_zero_addr(sw->src_mac_mask)) - { - FAL_FIELD_FLG_SET(sw->field_flg, FAL_ACL_FIELD_MAC_SA); - } - } - else - { - for (i = 2; i < 6; i++) - { - sw->src_mac_val.uc[i] = ((hw->vlu[0]) >> ((5 - i) << 3)) & 0xff; - sw->src_mac_mask.uc[i] = ((hw->msk[0]) >> ((5 - i) << 3)) & 0xff; - } - - for (i = 0; i < 2; i++) - { - sw->src_mac_val.uc[i] = ((hw->vlu[1]) >> ((1 - i) << 3)) & 0xff; - sw->src_mac_mask.uc[i] = ((hw->msk[1]) >> ((1 - i) << 3)) & 0xff; - } - - if (A_FALSE == _dess_acl_zero_addr(sw->src_mac_mask)) - { - FAL_FIELD_FLG_SET(sw->field_flg, FAL_ACL_FIELD_MAC_SA); - } - - FIELD_GET(EHMAC_RUL_V2, SAV_BYTE3, sw->dest_mac_val.uc[3]); - FIELD_GET(EHMAC_RUL_V1, SAV_BYTE4, sw->dest_mac_val.uc[4]); - FIELD_GET(EHMAC_RUL_V1, SAV_BYTE5, sw->dest_mac_val.uc[5]); - - FIELD_GET_MASK(EHMAC_RUL_M2, SAM_BYTE3, sw->dest_mac_mask.uc[3]); - FIELD_GET_MASK(EHMAC_RUL_M1, SAM_BYTE4, sw->dest_mac_mask.uc[4]); - FIELD_GET_MASK(EHMAC_RUL_M1, SAM_BYTE5, sw->dest_mac_mask.uc[5]); - if (A_FALSE == _dess_acl_zero_addr(sw->dest_mac_mask)) - { - FAL_FIELD_FLG_SET(sw->field_flg, FAL_ACL_FIELD_MAC_DA); - } - } - - /* ethernet type */ - FIELD_GET(EHMAC_RUL_V3, ETHTYPV, sw->ethtype_val); - FIELD_GET_MASK(EHMAC_RUL_M3, ETHTYPM, sw->ethtype_mask); - if (0x0 != sw->ethtype_mask) - { - FAL_FIELD_FLG_SET(sw->field_flg, FAL_ACL_FIELD_MAC_ETHTYPE); - } - - /* packet stagged */ - FIELD_GET(EHMAC_RUL_V3, STAGGEDV, sw->stagged_val); - FIELD_GET(EHMAC_RUL_V3, STAGGEDM, sw->stagged_mask); - if (0x0 != sw->stagged_mask) - { - FAL_FIELD_FLG_SET(sw->field_flg, FAL_ACL_FIELD_MAC_STAGGED); - } - - /* stag vid */ - FIELD_GET(EHMAC_RUL_V2, STAG_VIDV, sw->stag_vid_val); - FIELD_GET_MASK(EHMAC_RUL_M2, STAG_VIDM, sw->stag_vid_mask); - FIELD_GET(EHMAC_RUL_V3, SVIDMSK, mask_en); - if (mask_en) - { - sw->stag_vid_op = FAL_ACL_FIELD_MASK; - } - else - { - sw->stag_vid_op = FAL_ACL_FIELD_RANGE; - } - - if (A_TRUE == - _dess_acl_field_care(sw->stag_vid_op, (a_uint32_t) sw->stag_vid_val, - (a_uint32_t) sw->stag_vid_mask, 0xfff)) - { - FAL_FIELD_FLG_SET(sw->field_flg, FAL_ACL_FIELD_MAC_STAG_VID); - } - - /* stag priority */ - FIELD_GET(EHMAC_RUL_V2, STAG_PRIV, sw->stag_pri_val); - FIELD_GET_MASK(EHMAC_RUL_M2, STAG_PRIM, sw->stag_pri_mask); - if (0x0 != sw->stag_pri_mask) - { - FAL_FIELD_FLG_SET(sw->field_flg, FAL_ACL_FIELD_MAC_STAG_PRI); - } - - /* stag dei */ - FIELD_GET(EHMAC_RUL_V2, STAG_DEIV, sw->stag_dei_val); - FIELD_GET_MASK(EHMAC_RUL_M2, STAG_DEIM, sw->stag_dei_mask); - if (0x0 != sw->stag_dei_mask) - { - FAL_FIELD_FLG_SET(sw->field_flg, FAL_ACL_FIELD_MAC_STAG_DEI); - } - - /* packet ctagged */ - FIELD_GET_MASK(EHMAC_RUL_M4, CTAGGEDV, sw->ctagged_val); - FIELD_GET_MASK(EHMAC_RUL_M4, CTAGGEDM, sw->ctagged_mask); - if (0x0 != sw->ctagged_mask) - { - FAL_FIELD_FLG_SET(sw->field_flg, FAL_ACL_FIELD_MAC_CTAGGED); - } - - /* ctag vid */ - FIELD_GET(EHMAC_RUL_V2, CTAG_VIDLV, sw->ctag_vid_val); - FIELD_GET(EHMAC_RUL_V3, CTAG_VIDHV, data); - sw->ctag_vid_val |= (data << 8); - FIELD_GET_MASK(EHMAC_RUL_M2, CTAG_VIDLM, sw->ctag_vid_mask); - FIELD_GET_MASK(EHMAC_RUL_M3, CTAG_VIDHM, data); - sw->ctag_vid_mask |= (data << 8); - - FIELD_GET_MASK(EHMAC_RUL_M4, CVIDMSK, mask_en); - if (mask_en) - { - sw->ctag_vid_op = FAL_ACL_FIELD_MASK; - } - else - { - sw->ctag_vid_op = FAL_ACL_FIELD_RANGE; - } - - if (A_TRUE == - _dess_acl_field_care(sw->ctag_vid_op, (a_uint32_t) sw->ctag_vid_val, - (a_uint32_t) sw->ctag_vid_mask, 0xfff)) - { - FAL_FIELD_FLG_SET(sw->field_flg, FAL_ACL_FIELD_MAC_CTAG_VID); - } - - /* ctag priority */ - FIELD_GET(EHMAC_RUL_V3, CTAG_PRIV, sw->ctag_pri_val); - FIELD_GET_MASK(EHMAC_RUL_M3, CTAG_PRIM, sw->ctag_pri_mask); - if (0x0 != sw->ctag_pri_mask) - { - FAL_FIELD_FLG_SET(sw->field_flg, FAL_ACL_FIELD_MAC_CTAG_PRI); - } - - /* ctag dei */ - FIELD_GET(EHMAC_RUL_V3, CTAG_CFIV, sw->ctag_cfi_val); - FIELD_GET_MASK(EHMAC_RUL_M3, CTAG_CFIM, sw->ctag_cfi_mask); - if (0x0 != sw->ctag_cfi_mask) - { - FAL_FIELD_FLG_SET(sw->field_flg, FAL_ACL_FIELD_MAC_CTAG_CFI); - } - - FIELD_GET(MAC_RUL_V4, RULE_INV, mask_en); - if (mask_en) - { - FAL_FIELD_FLG_SET(sw->field_flg, FAL_ACL_FIELD_INVERSE_ALL); - } - - return SW_OK; -} - -static sw_error_t -_dess_acl_rule_ip4_reparse(fal_acl_rule_t * sw, const hw_filter_t * hw) -{ - a_uint32_t mask_en, icmp_en; - - sw->dest_ip4_val = hw->vlu[0]; - sw->dest_ip4_mask = hw->msk[0]; - if (0x0 != sw->dest_ip4_mask) - { - FAL_FIELD_FLG_SET(sw->field_flg, FAL_ACL_FIELD_IP4_DIP); - } - - sw->src_ip4_val = hw->vlu[1]; - sw->src_ip4_mask = hw->msk[1]; - if (0x0 != sw->src_ip4_mask) - { - FAL_FIELD_FLG_SET(sw->field_flg, FAL_ACL_FIELD_IP4_SIP); - } - - FIELD_GET(IP4_RUL_V2, IP4PROTV, sw->ip_proto_val); - FIELD_GET_MASK(IP4_RUL_M2, IP4PROTM, sw->ip_proto_mask); - if (0x0 != sw->ip_proto_mask) - { - FAL_FIELD_FLG_SET(sw->field_flg, FAL_ACL_FIELD_IP_PROTO); - } - - FIELD_GET(IP4_RUL_V2, IP4DSCPV, sw->ip_dscp_val); - FIELD_GET_MASK(IP4_RUL_M2, IP4DSCPM, sw->ip_dscp_mask); - if (0x0 != sw->ip_dscp_mask) - { - FAL_FIELD_FLG_SET(sw->field_flg, FAL_ACL_FIELD_IP_DSCP); - } - - FIELD_GET(IP4_RUL_V2, IP4DPORTV, sw->dest_l4port_val); - FIELD_GET_MASK(IP4_RUL_M2, IP4DPORTM, sw->dest_l4port_mask); - FIELD_GET_MASK(IP4_RUL_M3, IP4DPORTM_EN, mask_en); - if (mask_en) - { - sw->dest_l4port_op = FAL_ACL_FIELD_MASK; - } - else - { - sw->dest_l4port_op = FAL_ACL_FIELD_RANGE; - } - - if (A_TRUE == - _dess_acl_field_care(sw->dest_l4port_op, - (a_uint32_t) sw->dest_l4port_val, - (a_uint32_t) sw->dest_l4port_mask, 0xffff)) - { - FAL_FIELD_FLG_SET(sw->field_flg, FAL_ACL_FIELD_L4_DPORT); - } - else if (FAL_ACL_FIELD_RANGE == sw->dest_l4port_op) - { - FAL_FIELD_FLG_SET(sw->field_flg, FAL_ACL_FIELD_L4_DPORT); - } - - FIELD_GET(IP4_RUL_V3, ICMP_EN, icmp_en); - if (icmp_en) - { - FIELD_GET(IP4_RUL_V3, IP4ICMPTYPV, sw->icmp_type_val); - FIELD_GET_MASK(IP4_RUL_M3, IP4ICMPTYPM, sw->icmp_type_mask); - if (0x0 != sw->icmp_type_mask) - { - FAL_FIELD_FLG_SET(sw->field_flg, FAL_ACL_FIELD_ICMP_TYPE); - } - - FIELD_GET(IP4_RUL_V3, IP4ICMPCODEV, sw->icmp_code_val); - FIELD_GET_MASK(IP4_RUL_M3, IP4ICMPCODEM, sw->icmp_code_mask); - if (0x0 != sw->icmp_code_mask) - { - FAL_FIELD_FLG_SET(sw->field_flg, FAL_ACL_FIELD_ICMP_CODE); - } - } - else - { - FIELD_GET(IP4_RUL_V3, IP4SPORTV, sw->src_l4port_val); - FIELD_GET_MASK(IP4_RUL_M3, IP4SPORTM, sw->src_l4port_mask); - FIELD_GET_MASK(IP4_RUL_M3, IP4SPORTM_EN, mask_en); - if (mask_en) - { - sw->src_l4port_op = FAL_ACL_FIELD_MASK; - } - else - { - sw->src_l4port_op = FAL_ACL_FIELD_RANGE; - } - - if (A_TRUE == - _dess_acl_field_care(sw->src_l4port_op, - (a_uint32_t) sw->src_l4port_val, - (a_uint32_t) sw->src_l4port_mask, 0xffff)) - { - FAL_FIELD_FLG_SET(sw->field_flg, FAL_ACL_FIELD_L4_SPORT); - } - else if (FAL_ACL_FIELD_RANGE == sw->src_l4port_op) - { - FAL_FIELD_FLG_SET(sw->field_flg, FAL_ACL_FIELD_L4_SPORT); - } - } - - FIELD_GET(IP4_RUL_V3, IP4TCPFLAGV, sw->tcp_flag_val); - FIELD_GET_MASK(IP4_RUL_M3, IP4TCPFLAGM, sw->tcp_flag_mask); - if (0x0 != sw->tcp_flag_mask) - { - FAL_FIELD_FLG_SET(sw->field_flg, FAL_ACL_FIELD_TCP_FLAG); - } - - FIELD_GET(IP4_RUL_V3, IP4RIPV, sw->ripv1_val); - FIELD_GET_MASK(IP4_RUL_M3, IP4RIPM, sw->ripv1_mask); - if (0x0 != sw->ripv1_mask) - { - FAL_FIELD_FLG_SET(sw->field_flg, FAL_ACL_FIELD_RIPV1); - } - - FIELD_GET(IP4_RUL_V3, IP4DHCPV, sw->dhcpv4_val); - FIELD_GET_MASK(IP4_RUL_M3, IP4DHCPM, sw->dhcpv4_mask); - if (0x0 != sw->dhcpv4_mask) - { - FAL_FIELD_FLG_SET(sw->field_flg, FAL_ACL_FIELD_DHCPV4); - } - - FIELD_GET(MAC_RUL_V4, RULE_INV, mask_en); - if (mask_en) - { - FAL_FIELD_FLG_SET(sw->field_flg, FAL_ACL_FIELD_INVERSE_ALL); - } - - return SW_OK; -} - -static sw_error_t -_dess_acl_rule_ip6r1_reparse(fal_acl_rule_t * sw, const hw_filter_t * hw) -{ - a_uint32_t i; - - for (i = 0; i < 4; i++) - { - sw->dest_ip6_val.ul[i] = hw->vlu[3 - i]; - sw->dest_ip6_mask.ul[i] = hw->msk[3 - i]; - if (0x0 != sw->dest_ip6_mask.ul[i]) - { - FAL_FIELD_FLG_SET(sw->field_flg, FAL_ACL_FIELD_IP6_DIP); - } - } - - FIELD_GET(MAC_RUL_V4, RULE_INV, i); - if (i) - { - FAL_FIELD_FLG_SET(sw->field_flg, FAL_ACL_FIELD_INVERSE_ALL); - } - - return SW_OK; -} - -static sw_error_t -_dess_acl_rule_ip6r2_reparse(fal_acl_rule_t * sw, const hw_filter_t * hw) -{ - a_uint32_t i; - - for (i = 0; i < 4; i++) - { - sw->src_ip6_val.ul[i] = hw->vlu[3 - i]; - sw->src_ip6_mask.ul[i] = hw->msk[3 - i]; - if (0x0 != sw->src_ip6_mask.ul[i]) - { - FAL_FIELD_FLG_SET(sw->field_flg, FAL_ACL_FIELD_IP6_SIP); - } - } - - FIELD_GET(MAC_RUL_V4, RULE_INV, i); - if (i) - { - FAL_FIELD_FLG_SET(sw->field_flg, FAL_ACL_FIELD_INVERSE_ALL); - } - - return SW_OK; -} - -static sw_error_t -_dess_acl_rule_ip6r3_reparse(fal_acl_rule_t * sw, const hw_filter_t * hw) -{ - a_uint32_t mask_en, icmp6_en, tmp; - - FIELD_GET(IP6_RUL3_V0, IP6PROTV, sw->ip_proto_val); - FIELD_GET_MASK(IP6_RUL3_M0, IP6PROTM, sw->ip_proto_mask); - if (0x0 != sw->ip_proto_mask) - { - FAL_FIELD_FLG_SET(sw->field_flg, FAL_ACL_FIELD_IP_PROTO); - } - - FIELD_GET(IP6_RUL3_V0, IP6DSCPV, sw->ip_dscp_val); - FIELD_GET_MASK(IP6_RUL3_M0, IP6DSCPM, sw->ip_dscp_mask); - if (0x0 != sw->ip_dscp_mask) - { - FAL_FIELD_FLG_SET(sw->field_flg, FAL_ACL_FIELD_IP_DSCP); - } - - FIELD_GET(IP6_RUL3_V2, IP6DPORTV, sw->dest_l4port_val); - FIELD_GET_MASK(IP6_RUL3_M2, IP6DPORTM, sw->dest_l4port_mask); - FIELD_GET_MASK(IP6_RUL3_M3, IP6DPORTM_EN, mask_en); - if (mask_en) - { - sw->dest_l4port_op = FAL_ACL_FIELD_MASK; - } - else - { - sw->dest_l4port_op = FAL_ACL_FIELD_RANGE; - } - - if (A_TRUE == - _dess_acl_field_care(sw->dest_l4port_op, - (a_uint32_t) sw->dest_l4port_val, - (a_uint32_t) sw->dest_l4port_mask, 0xffff)) - { - FAL_FIELD_FLG_SET(sw->field_flg, FAL_ACL_FIELD_L4_DPORT); - } - else if (FAL_ACL_FIELD_RANGE == sw->dest_l4port_op) - { - FAL_FIELD_FLG_SET(sw->field_flg, FAL_ACL_FIELD_L4_DPORT); - } - - FIELD_GET(IP6_RUL3_V3, ICMP6_EN, icmp6_en); - if (icmp6_en) - { - FIELD_GET(IP6_RUL3_V3, IP6ICMPTYPV, sw->icmp_type_val); - FIELD_GET_MASK(IP6_RUL3_M3, IP6ICMPTYPM, sw->icmp_type_mask); - if (0x0 != sw->icmp_type_mask) - { - FAL_FIELD_FLG_SET(sw->field_flg, FAL_ACL_FIELD_ICMP_TYPE); - } - - FIELD_GET(IP6_RUL3_V3, IP6ICMPCODEV, sw->icmp_code_val); - FIELD_GET_MASK(IP6_RUL3_M3, IP6ICMPCODEM, sw->icmp_code_mask); - if (0x0 != sw->icmp_code_mask) - { - FAL_FIELD_FLG_SET(sw->field_flg, FAL_ACL_FIELD_ICMP_CODE); - } - } - else - { - FIELD_GET(IP6_RUL3_V3, IP6SPORTV, sw->src_l4port_val); - FIELD_GET_MASK(IP6_RUL3_M3, IP6SPORTM, sw->src_l4port_mask); - FIELD_GET_MASK(IP6_RUL3_M3, IP6SPORTM_EN, mask_en); - if (mask_en) - { - sw->src_l4port_op = FAL_ACL_FIELD_MASK; - } - else - { - sw->src_l4port_op = FAL_ACL_FIELD_RANGE; - } - - if (A_TRUE == - _dess_acl_field_care(sw->src_l4port_op, - (a_uint32_t) sw->src_l4port_val, - (a_uint32_t) sw->src_l4port_mask, 0xffff)) - { - FAL_FIELD_FLG_SET(sw->field_flg, FAL_ACL_FIELD_L4_SPORT); - } - else if (FAL_ACL_FIELD_RANGE == sw->src_l4port_op) - { - FAL_FIELD_FLG_SET(sw->field_flg, FAL_ACL_FIELD_L4_SPORT); - } - } - - FIELD_GET(IP6_RUL3_V1, IP6LABEL1V, sw->ip6_lable_val); - FIELD_GET_MASK(IP6_RUL3_M1, IP6LABEL1M, sw->ip6_lable_mask); - - FIELD_GET(IP6_RUL3_V2, IP6LABEL2V, tmp); - sw->ip6_lable_val |= (tmp << 16); - FIELD_GET_MASK(IP6_RUL3_M2, IP6LABEL2M, tmp); - sw->ip6_lable_mask |= (tmp << 16); - - if (0x0 != sw->ip6_lable_mask) - { - FAL_FIELD_FLG_SET(sw->field_flg, FAL_ACL_FIELD_IP6_LABEL); - } - - FIELD_GET(IP6_RUL3_V3, IP6TCPFLAGV, sw->tcp_flag_val); - FIELD_GET_MASK(IP6_RUL3_M3, IP6TCPFLAGM, sw->tcp_flag_mask); - if (0x0 != sw->tcp_flag_mask) - { - FAL_FIELD_FLG_SET(sw->field_flg, FAL_ACL_FIELD_TCP_FLAG); - } - - FIELD_GET(IP6_RUL3_V3, IP6DHCPV, sw->dhcpv6_val); - FIELD_GET_MASK(IP6_RUL3_M3, IP6DHCPM, sw->dhcpv6_mask); - if (0x0 != sw->dhcpv6_mask) - { - FAL_FIELD_FLG_SET(sw->field_flg, FAL_ACL_FIELD_DHCPV6); - } - - FIELD_GET(MAC_RUL_V4, RULE_INV, mask_en); - if (mask_en) - { - FAL_FIELD_FLG_SET(sw->field_flg, FAL_ACL_FIELD_INVERSE_ALL); - } - - return SW_OK; -} - -static sw_error_t -_dess_acl_rule_udf_reparse(fal_acl_rule_t * sw, const hw_filter_t * hw) -{ - a_uint32_t i; - - FAL_FIELD_FLG_SET(sw->field_flg, FAL_ACL_FIELD_UDF); - - /* for ISIS UDF type, length and offset no meanging in rules, just set default value */ - sw->udf_type = FAL_ACL_UDF_TYPE_L2; - sw->udf_len = 16; - sw->udf_offset = 0; - - for (i = 0; i < DESS_MAX_UDF_LENGTH; i++) - { - sw->udf_val[i] = ((hw->vlu[3 - i / 4]) >> (24 - 8 * (i % 4))) & 0xff; - sw->udf_mask[i] = ((hw->msk[3 - i / 4]) >> (24 - 8 * (i % 4))) & 0xff; - } - - FIELD_GET(MAC_RUL_V4, RULE_INV, i); - if (i) - { - FAL_FIELD_FLG_SET(sw->field_flg, FAL_ACL_FIELD_INVERSE_ALL); - } - - return SW_OK; -} - -static sw_error_t -_dess_acl_rule_action_reparse(fal_acl_rule_t * sw, const hw_filter_t * hw) -{ - a_uint32_t data; - - sw->action_flg = 0; - - FIELD_GET_ACTION(ACL_RSLT2, DES_PORT_EN, data); - if (1 == data) - { - FAL_ACTION_FLG_SET(sw->action_flg, FAL_ACL_ACTION_REDPT); - FIELD_GET_ACTION(ACL_RSLT1, DES_PORT0, sw->ports); - FIELD_GET_ACTION(ACL_RSLT2, DES_PORT1, data); - sw->ports |= (data << 3); - } - - FIELD_GET_ACTION(ACL_RSLT2, FWD_CMD, data); - if (0x7 == data) - { - FAL_ACTION_FLG_SET(sw->action_flg, FAL_ACL_ACTION_DENY); - } - else if (0x3 == data) - { - FAL_ACTION_FLG_SET(sw->action_flg, FAL_ACL_ACTION_RDTCPU); - } - else if (0x1 == data) - { - FAL_ACTION_FLG_SET(sw->action_flg, FAL_ACL_ACTION_CPYCPU); - } - else - { - /* need't set permit action */ - } - - FIELD_GET_ACTION(ACL_RSLT2, MIRR_EN, data); - if (1 == data) - { - FAL_ACTION_FLG_SET(sw->action_flg, FAL_ACL_ACTION_MIRROR); - } - - FIELD_GET_ACTION(ACL_RSLT1, PRI_QU_EN, data); - if (1 == data) - { - FAL_ACTION_FLG_SET(sw->action_flg, FAL_ACL_ACTION_REMARK_QUEUE); - FIELD_GET_ACTION(ACL_RSLT1, PRI_QU, sw->queue); - } - - FIELD_GET_ACTION(ACL_RSLT1, DSCP_REMAP, data); - if (data) - { - FAL_ACTION_FLG_SET(sw->action_flg, FAL_ACL_ACTION_REMARK_DSCP); - FIELD_GET_ACTION(ACL_RSLT1, DSCPV, sw->dscp); - } - - FIELD_GET_ACTION(ACL_RSLT0, STAGVID, sw->stag_vid); - - FIELD_GET_ACTION(ACL_RSLT1, TRANS_SVID_CHG, data); - if (data) - { - FAL_ACTION_FLG_SET(sw->action_flg, FAL_ACL_ACTION_REMARK_STAG_VID); - } - - FIELD_GET_ACTION(ACL_RSLT1, STAG_PRI_REMAP, data); - if (data) - { - FAL_ACTION_FLG_SET(sw->action_flg, FAL_ACL_ACTION_REMARK_STAG_PRI); - FIELD_GET_ACTION(ACL_RSLT0, STAGPRI, sw->stag_pri); - } - - FIELD_GET_ACTION(ACL_RSLT1, STAG_DEI_CHG, data); - if (data) - { - FAL_ACTION_FLG_SET(sw->action_flg, FAL_ACL_ACTION_REMARK_STAG_DEI); - FIELD_GET_ACTION(ACL_RSLT0, STAGDEI, sw->stag_dei); - } - - FIELD_GET_ACTION(ACL_RSLT0, CTAGVID, sw->ctag_vid); - - FIELD_GET_ACTION(ACL_RSLT1, TRANS_CVID_CHG, data); - if (data) - { - FAL_ACTION_FLG_SET(sw->action_flg, FAL_ACL_ACTION_REMARK_CTAG_VID); - } - - FIELD_GET_ACTION(ACL_RSLT1, CTAG_PRI_REMAP, data); - if (data) - { - FAL_ACTION_FLG_SET(sw->action_flg, FAL_ACL_ACTION_REMARK_CTAG_PRI); - FIELD_GET_ACTION(ACL_RSLT0, CTAGPRI, sw->ctag_pri); - } - - FIELD_GET_ACTION(ACL_RSLT1, CTAG_CFI_CHG, data); - if (data) - { - FAL_ACTION_FLG_SET(sw->action_flg, FAL_ACL_ACTION_REMARK_CTAG_CFI); - FIELD_GET_ACTION(ACL_RSLT0, CTAGCFI, sw->ctag_cfi); - } - - FIELD_GET_ACTION(ACL_RSLT1, LOOK_VID_CHG, data); - if (data) - { - FAL_ACTION_FLG_SET(sw->action_flg, FAL_ACL_ACTION_REMARK_LOOKUP_VID); - } - - FIELD_GET_ACTION(ACL_RSLT2, POLICER_EN, data); - if (data) - { - FAL_ACTION_FLG_SET(sw->action_flg, FAL_ACL_ACTION_POLICER_EN); - FIELD_GET_ACTION(ACL_RSLT2, POLICER_PTR, sw->policer_ptr); - } - - FIELD_GET_ACTION(ACL_RSLT1, ARP_PTR_EN, data); - if (data) - { - FIELD_GET_ACTION(ACL_RSLT1, WCMP_EN, data); - if (data) - { - FAL_ACTION_FLG_SET(sw->action_flg, FAL_ACL_ACTION_WCMP_EN); - FIELD_GET_ACTION(ACL_RSLT1, ARP_PTR, sw->wcmp_ptr); - } - else - { - FAL_ACTION_FLG_SET(sw->action_flg, FAL_ACL_ACTION_ARP_EN); - FIELD_GET_ACTION(ACL_RSLT1, ARP_PTR, sw->arp_ptr); - } - } - - FIELD_GET_ACTION(ACL_RSLT1, FORCE_L3_MODE, data); - if ((0 != data) && (3 != data)) - { - FAL_ACTION_FLG_SET(sw->action_flg, FAL_ACL_ACTION_POLICY_FORWARD_EN); - if (0x1 == data) - { - sw->policy_fwd = FAL_ACL_POLICY_SNAT; - } - else - { - sw->policy_fwd = FAL_ACL_POLICY_DNAT; - } - } - - FIELD_GET_ACTION(ACL_RSLT2, EG_BYPASS, data); - if (data) - { - FAL_ACTION_FLG_SET(sw->action_flg, FAL_ACL_ACTION_BYPASS_EGRESS_TRANS); - } - - FIELD_GET_ACTION(ACL_RSLT2, TRIGGER_INTR, data); - if (data) - { - FAL_ACTION_FLG_SET(sw->action_flg, FAL_ACL_ACTION_MATCH_TRIGGER_INTR); - } - - return SW_OK; -} - -sw_error_t -_dess_acl_rule_sw_to_hw(a_uint32_t dev_id, fal_acl_rule_t * sw, - dess_acl_rule_t * hw_rule_snap, a_uint32_t * idx) -{ - sw_error_t rv; - a_uint32_t tmp_idx, i, b_rule[7] = { 0 }; - parse_func_t ptr[7] = { NULL }; - a_bool_t b_care, b_mac, eh_mac; - - rv = _dess_acl_action_parse(dev_id, sw, &(hw_rule_snap[*idx].filter)); - SW_RTN_ON_ERROR(rv); - - ptr[0] = _dess_acl_rule_udf_parse; - _dess_acl_rule_mac_preparse(sw, &b_mac, &eh_mac); - - /* ehmac rule must be parsed bofore mac rule. - it's important for reparse process */ - if (A_TRUE == eh_mac) - { - ptr[1] = _dess_acl_rule_ehmac_parse; - } - - if (A_TRUE == b_mac) - { - ptr[2] = _dess_acl_rule_bmac_parse; - } - - if ((A_FALSE == b_mac) && (A_FALSE == eh_mac)) - { - ptr[2] = _dess_acl_rule_bmac_parse; - } - - if (FAL_ACL_RULE_MAC == sw->rule_type) - { - } - else if (FAL_ACL_RULE_IP4 == sw->rule_type) - { - ptr[3] = _dess_acl_rule_ip4_parse; - } - else if (FAL_ACL_RULE_IP6 == sw->rule_type) - { - ptr[4] = _dess_acl_rule_ip6r1_parse; - ptr[5] = _dess_acl_rule_ip6r2_parse; - ptr[6] = _dess_acl_rule_ip6r3_parse; - } - else if (FAL_ACL_RULE_UDF == sw->rule_type) - { - ptr[1] = NULL; - ptr[2] = NULL; - } - else - { - return SW_NOT_SUPPORTED; - } - - tmp_idx = *idx; - for (i = 0; i < 7; i++) - { - if (ptr[i]) - { - if (DESS_HW_RULE_TMP_CNT <= tmp_idx) - { - return SW_NO_RESOURCE; - } - - rv = ptr[i] (sw, &(hw_rule_snap[tmp_idx].filter), &b_care); - SW_RTN_ON_ERROR(rv); - if (A_TRUE == b_care) - { - tmp_idx++; - b_rule[i] = 1; - } - } - } - - if (FAL_ACL_RULE_IP6 == sw->rule_type) - { - if ((!b_rule[4]) && (!b_rule[5]) && (!b_rule[6])) - { - tmp_idx++; - } - } - - if (FAL_ACL_RULE_IP4 == sw->rule_type) - { - if (!b_rule[3]) - { - tmp_idx++; - } - } - - if (tmp_idx == *idx) - { - /* set type start & end */ - SW_SET_REG_BY_FIELD(MAC_RUL_M4, RULE_VALID, FLT_STARTEND, - (hw_rule_snap[*idx].filter.msk[4])); - (*idx)++; - } - else - { - if (1 == (tmp_idx - *idx)) - { - if (FAL_ACL_COMBINED_START == sw->combined) - { - SW_SET_REG_BY_FIELD(MAC_RUL_M4, RULE_VALID, FLT_START, - (hw_rule_snap[*idx].filter.msk[4])); - } - else if (FAL_ACL_COMBINED_CONTINUE == sw->combined) - { - SW_SET_REG_BY_FIELD(MAC_RUL_M4, RULE_VALID, FLT_CONTINUE, - (hw_rule_snap[*idx].filter.msk[4])); - } - else if (FAL_ACL_COMBINED_END == sw->combined) - { - SW_SET_REG_BY_FIELD(MAC_RUL_M4, RULE_VALID, FLT_END, - (hw_rule_snap[*idx].filter.msk[4])); - } - else - { - SW_SET_REG_BY_FIELD(MAC_RUL_M4, RULE_VALID, FLT_STARTEND, - (hw_rule_snap[*idx].filter.msk[4])); - } - } - else - { - for (i = *idx; i < tmp_idx; i++) - { - if (i == *idx) - { - SW_SET_REG_BY_FIELD(MAC_RUL_M4, RULE_VALID, FLT_START, - (hw_rule_snap[i].filter.msk[4])); - } - else if (i == (tmp_idx - 1)) - { - SW_SET_REG_BY_FIELD(MAC_RUL_M4, RULE_VALID, FLT_END, - (hw_rule_snap[i].filter.msk[4])); - } - else - { - SW_SET_REG_BY_FIELD(MAC_RUL_M4, RULE_VALID, FLT_CONTINUE, - (hw_rule_snap[i].filter.msk[4])); - } - aos_mem_copy(&(hw_rule_snap[i].filter.act[0]), - &(hw_rule_snap[*idx].filter.act[0]), - sizeof (hw_rule_snap[*idx].filter.act)); - } - } - *idx = tmp_idx; - } - - return SW_OK; -} - -sw_error_t -_dess_acl_rule_hw_to_sw(a_uint32_t dev_id, fal_acl_rule_t * sw, - dess_acl_rule_t * hw_rule_snap, a_uint32_t idx, - a_uint32_t ent_nr) -{ - a_bool_t b_mac = A_FALSE, b_ip4 = A_FALSE, b_ip6 = A_FALSE; - sw_error_t rv; - a_uint32_t i, flt_typ; - hw_filter_t *hw; - - rv = _dess_acl_rule_action_reparse(sw, &(hw_rule_snap[idx].filter)); - SW_RTN_ON_ERROR(rv); - - sw->rule_type = FAL_ACL_RULE_UDF; - for (i = 0; i < ent_nr; i++) - { - hw = &(hw_rule_snap[idx + i].filter); - FIELD_GET_MASK(MAC_RUL_M4, RULE_TYP, flt_typ); - - if (DESS_UDF_FILTER == flt_typ) - { - rv = _dess_acl_rule_udf_reparse(sw, hw); - SW_RTN_ON_ERROR(rv); - } - else if (DESS_MAC_FILTER == flt_typ) - { - rv = _dess_acl_rule_bmac_reparse(sw, hw); - SW_RTN_ON_ERROR(rv); - b_mac = A_TRUE; - } - else if (DESS_EHMAC_FILTER == flt_typ) - { - rv = _dess_acl_rule_ehmac_reparse(sw, hw); - SW_RTN_ON_ERROR(rv); - b_mac = A_TRUE; - } - else if (DESS_IP4_FILTER == flt_typ) - { - rv = _dess_acl_rule_ip4_reparse(sw, hw); - SW_RTN_ON_ERROR(rv); - b_ip4 = A_TRUE; - } - else if (DESS_IP6R1_FILTER == flt_typ) - { - rv = _dess_acl_rule_ip6r1_reparse(sw, hw); - SW_RTN_ON_ERROR(rv); - b_ip6 = A_TRUE; - } - else if (DESS_IP6R2_FILTER == flt_typ) - { - rv = _dess_acl_rule_ip6r2_reparse(sw, hw); - SW_RTN_ON_ERROR(rv); - b_ip6 = A_TRUE; - } - else if (DESS_IP6R3_FILTER == flt_typ) - { - rv = _dess_acl_rule_ip6r3_reparse(sw, hw); - SW_RTN_ON_ERROR(rv); - b_ip6 = A_TRUE; - } - else - { - /* ignore fill gap filters */ - } - } - - if (A_TRUE == b_mac) - { - sw->rule_type = FAL_ACL_RULE_MAC; - } - - if (A_TRUE == b_ip4) - { - sw->rule_type = FAL_ACL_RULE_IP4; - } - - if (A_TRUE == b_ip6) - { - sw->rule_type = FAL_ACL_RULE_IP6; - } - - return SW_OK; -} diff --git a/feeds/ipq807x/qca-ssdk/src/src/hsl/dess/dess_acl_prv.h b/feeds/ipq807x/qca-ssdk/src/src/hsl/dess/dess_acl_prv.h deleted file mode 100755 index 83a7d40a5..000000000 --- a/feeds/ipq807x/qca-ssdk/src/src/hsl/dess/dess_acl_prv.h +++ /dev/null @@ -1,126 +0,0 @@ -/* - * Copyright (c) 2014, The Linux Foundation. All rights reserved. - * Permission to use, copy, modify, and/or distribute this software for - * any purpose with or without fee is hereby granted, provided that the - * above copyright notice and this permission notice appear in all copies. - * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES - * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR - * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES - * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN - * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT - * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. - */ - - - -typedef struct -{ - a_uint8_t status; - a_uint8_t list_id; - a_uint8_t list_pri; - a_uint8_t rule_nr; - fal_pbmp_t bind_pts; -} dess_acl_list_t; - - -typedef struct -{ - a_uint32_t vlu[5]; - a_uint32_t msk[5]; - a_uint32_t act[3]; -} hw_filter_t; - - -typedef struct -{ - a_uint8_t status; - a_uint8_t list_id; - a_uint8_t list_pri; - a_uint8_t rule_id; - hw_filter_t filter; - a_uint32_t src_flt_dis; /* src filter disabled */ -} dess_acl_rule_t; - - -#define ENT_USED 0x1 -#define ENT_TMP 0x2 -#define ENT_DEACTIVE 0x4 - -#define FLT_START 0x0 -#define FLT_CONTINUE 0x1 -#define FLT_END 0x2 -#define FLT_STARTEND 0x3 - - -#define DESS_MAC_FILTER 1 -#define DESS_IP4_FILTER 2 -#define DESS_IP6R1_FILTER 3 -#define DESS_IP6R2_FILTER 4 -#define DESS_IP6R3_FILTER 5 -#define DESS_UDF_FILTER 6 -#define DESS_EHMAC_FILTER 7 - - -#define DESS_MAX_UDF_OFFSET 31 -#define DESS_MAX_UDF_LENGTH 16 - - -#define DESS_FILTER_VLU_OP 0x0 -#define DESS_FILTER_MSK_OP 0x1 -#define DESS_FILTER_ACT_OP 0x2 - - - -//#define DESS_MAX_FILTER 8 -#define DESS_MAX_FILTER 96 -#define DESS_RULE_FUNC_ADDR 0x0400 -#define DESS_HW_RULE_TMP_CNT (DESS_MAX_FILTER + 4) - -#define DESS_MAX_LIST_ID 255 -#define DESS_MAX_LIST_PRI 255 - -#define DESS_UDF_MAX_LENGTH 15 -#define DESS_UDF_MAX_OFFSET 31 - -#define WIN_RULE_CTL0_ADDR 0x218 -#define WIN_RULE_CTL1_ADDR 0x234 - - -#define DESS_FILTER_VLU_ADDR 0x58000 -#define DESS_FILTER_MSK_ADDR 0x59000 -#define DESS_FILTER_ACT_ADDR 0x5a000 - - -#define FIELD_SET(reg, field, val) \ - SW_REG_SET_BY_FIELD_U32(hw->vlu[reg], val, reg##_##field##_BOFFSET, \ - reg##_##field##_BLEN) - -#define FIELD_GET(reg, field, val) \ - SW_FIELD_GET_BY_REG_U32(hw->vlu[reg], val, reg##_##field##_BOFFSET, \ - reg##_##field##_BLEN) - -#define FIELD_SET_MASK(reg, field, val) \ - SW_REG_SET_BY_FIELD_U32(hw->msk[reg-5], val, reg##_##field##_BOFFSET, \ - reg##_##field##_BLEN) - -#define FIELD_GET_MASK(reg, field, val) \ - SW_FIELD_GET_BY_REG_U32(hw->msk[reg-5], val, reg##_##field##_BOFFSET, \ - reg##_##field##_BLEN) - -#define FIELD_SET_ACTION(reg, field, val) \ - SW_REG_SET_BY_FIELD_U32(hw->act[reg-10], val, reg##_##field##_BOFFSET, \ - reg##_##field##_BLEN) - -#define FIELD_GET_ACTION(reg, field, val) \ - SW_FIELD_GET_BY_REG_U32(hw->act[reg-10], val, reg##_##field##_BOFFSET, \ - reg##_##field##_BLEN) - -sw_error_t -_dess_acl_rule_sw_to_hw(a_uint32_t dev_id, fal_acl_rule_t * sw, dess_acl_rule_t * hw_filter_snap, a_uint32_t * idx); - - -sw_error_t -_dess_acl_rule_hw_to_sw(a_uint32_t dev_id, fal_acl_rule_t * sw, dess_acl_rule_t * hw_filter_snap, a_uint32_t idx, a_uint32_t ent_nr); - - diff --git a/feeds/ipq807x/qca-ssdk/src/src/hsl/dess/dess_cosmap.c b/feeds/ipq807x/qca-ssdk/src/src/hsl/dess/dess_cosmap.c deleted file mode 100755 index 593c57382..000000000 --- a/feeds/ipq807x/qca-ssdk/src/src/hsl/dess/dess_cosmap.c +++ /dev/null @@ -1,945 +0,0 @@ -/* - * Copyright (c) 2014, 2016, The Linux Foundation. All rights reserved. - * Permission to use, copy, modify, and/or distribute this software for - * any purpose with or without fee is hereby granted, provided that the - * above copyright notice and this permission notice appear in all copies. - * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES - * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR - * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES - * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN - * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT - * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. - */ - - -/** - * @defgroup dess_cosmap DESS_COSMAP - * @{ - */ -#include "sw.h" -#include "hsl.h" -#include "hsl_dev.h" -#include "hsl_port_prop.h" -#include "dess_cosmap.h" -#include "dess_reg.h" - -#define DESS_MAX_DSCP 63 -#define DESS_MAX_UP 7 -#define DESS_MAX_PRI 7 -#define DESS_MAX_DP 1 -#define DESS_MAX_QUEUE 3 -#define DESS_MAX_EH_QUEUE 5 - -#define DESS_DSCP_TO_PRI 0 -#define DESS_DSCP_TO_DP 1 -#define DESS_UP_TO_PRI 2 -#define DESS_UP_TO_DP 3 - -#define DESS_EGRESS_REAMRK_ADDR 0x5ae00 -#define DESS_EGRESS_REAMRK_NUM 16 - -static sw_error_t -_dess_cosmap_dscp_to_pri_dp_set(a_uint32_t dev_id, a_uint32_t mode, - a_uint32_t dscp, a_uint32_t val) -{ - sw_error_t rv; - a_uint32_t index, data = 0; - - if (DESS_MAX_DSCP < dscp) - { - return SW_BAD_PARAM; - } - - index = dscp >> 3; - HSL_REG_ENTRY_GET(rv, dev_id, DSCP_TO_PRI, index, (a_uint8_t *) (&data), - sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - - if (DESS_DSCP_TO_PRI == mode) - { - if (DESS_MAX_PRI < val) - { - return SW_BAD_PARAM; - } - - data &= (~(0x7 << ((dscp & 0x7) << 2))); - data |= (val << ((dscp & 0x7) << 2)); - } - else - { - if (DESS_MAX_DP < val) - { - return SW_BAD_PARAM; - } - - data &= (~(0x1 << (((dscp & 0x7) << 2) + 3))); - data |= (val << (((dscp & 0x7) << 2) + 3)); - } - - HSL_REG_ENTRY_SET(rv, dev_id, DSCP_TO_PRI, index, (a_uint8_t *) (&data), - sizeof (a_uint32_t)); - return rv; -} - -static sw_error_t -_dess_cosmap_dscp_to_pri_dp_get(a_uint32_t dev_id, a_uint32_t mode, - a_uint32_t dscp, a_uint32_t * val) -{ - sw_error_t rv; - a_uint32_t index, data = 0; - - if (DESS_MAX_DSCP < dscp) - { - return SW_BAD_PARAM; - } - - index = dscp >> 3; - HSL_REG_ENTRY_GET(rv, dev_id, DSCP_TO_PRI, index, (a_uint8_t *) (&data), - sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - - data = (data >> ((dscp & 0x7) << 2)) & 0xf; - if (DESS_DSCP_TO_PRI == mode) - { - *val = data & 0x7; - } - else - { - *val = (data & 0x8) >> 3; - } - - return SW_OK; -} - -static sw_error_t -_dess_cosmap_up_to_pri_dp_set(a_uint32_t dev_id, a_uint32_t mode, a_uint32_t up, - a_uint32_t val) -{ - sw_error_t rv; - a_uint32_t data = 0; - - if (DESS_MAX_UP < up) - { - return SW_BAD_PARAM; - } - - HSL_REG_ENTRY_GET(rv, dev_id, UP_TO_PRI, 0, (a_uint8_t *) (&data), - sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - - if (DESS_UP_TO_PRI == mode) - { - if (DESS_MAX_PRI < val) - { - return SW_BAD_PARAM; - } - - data &= (~(0x7 << (up << 2))); - data |= (val << (up << 2)); - } - else - { - if (DESS_MAX_DP < val) - { - return SW_BAD_PARAM; - } - - data &= (~(0x1 << ((up << 2) + 3))); - data |= (val << ((up << 2) + 3)); - } - - HSL_REG_ENTRY_SET(rv, dev_id, UP_TO_PRI, 0, (a_uint8_t *) (&data), - sizeof (a_uint32_t)); - return rv; -} - -static sw_error_t -_dess_cosmap_up_to_pri_dp_get(a_uint32_t dev_id, a_uint32_t mode, a_uint32_t up, - a_uint32_t * val) -{ - sw_error_t rv; - a_uint32_t data = 0; - - if (DESS_MAX_UP < up) - { - return SW_BAD_PARAM; - } - - HSL_REG_ENTRY_GET(rv, dev_id, UP_TO_PRI, 0, (a_uint8_t *) (&data), - sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - - data = (data >> (up << 2)) & 0xf; - - if (DESS_UP_TO_PRI == mode) - { - *val = (data & 0x7); - } - else - { - *val = (data & 0x8) >> 3; - } - - return SW_OK; -} - -static sw_error_t -_dess_cosmap_dscp_to_ehpri_dp_set(a_uint32_t dev_id, a_uint32_t mode, - a_uint32_t dscp, a_uint32_t val) -{ - sw_error_t rv; - a_uint32_t index, data = 0; - - if (DESS_MAX_DSCP < dscp) - { - return SW_BAD_PARAM; - } - - index = dscp >> 3; - HSL_REG_ENTRY_GET(rv, dev_id, DSCP_TO_EHPRI, index, (a_uint8_t *) (&data), - sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - - if (DESS_DSCP_TO_PRI == mode) - { - if (DESS_MAX_PRI < val) - { - return SW_BAD_PARAM; - } - - data &= (~(0x7 << ((dscp & 0x7) << 2))); - data |= (val << ((dscp & 0x7) << 2)); - } - else - { - if (DESS_MAX_DP < val) - { - return SW_BAD_PARAM; - } - - data &= (~(0x1 << (((dscp & 0x7) << 2) + 3))); - data |= (val << (((dscp & 0x7) << 2) + 3)); - } - - HSL_REG_ENTRY_SET(rv, dev_id, DSCP_TO_EHPRI, index, (a_uint8_t *) (&data), - sizeof (a_uint32_t)); - return rv; -} - -static sw_error_t -_dess_cosmap_dscp_to_ehpri_dp_get(a_uint32_t dev_id, a_uint32_t mode, - a_uint32_t dscp, a_uint32_t * val) -{ - sw_error_t rv; - a_uint32_t index, data = 0; - - if (DESS_MAX_DSCP < dscp) - { - return SW_BAD_PARAM; - } - - index = dscp >> 3; - HSL_REG_ENTRY_GET(rv, dev_id, DSCP_TO_EHPRI, index, (a_uint8_t *) (&data), - sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - - data = (data >> ((dscp & 0x7) << 2)) & 0xf; - if (DESS_DSCP_TO_PRI == mode) - { - *val = data & 0x7; - } - else - { - *val = (data & 0x8) >> 3; - } - - return SW_OK; -} - -static sw_error_t -_dess_cosmap_up_to_ehpri_dp_set(a_uint32_t dev_id, a_uint32_t mode, a_uint32_t up, - a_uint32_t val) -{ - sw_error_t rv; - a_uint32_t data = 0; - - if (DESS_MAX_UP < up) - { - return SW_BAD_PARAM; - } - - HSL_REG_ENTRY_GET(rv, dev_id, UP_TO_EHPRI, 0, (a_uint8_t *) (&data), - sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - - if (DESS_UP_TO_PRI == mode) - { - if (DESS_MAX_PRI < val) - { - return SW_BAD_PARAM; - } - - data &= (~(0x7 << (up << 2))); - data |= (val << (up << 2)); - } - else - { - if (DESS_MAX_DP < val) - { - return SW_BAD_PARAM; - } - - data &= (~(0x1 << ((up << 2) + 3))); - data |= (val << ((up << 2) + 3)); - } - - HSL_REG_ENTRY_SET(rv, dev_id, UP_TO_EHPRI, 0, (a_uint8_t *) (&data), - sizeof (a_uint32_t)); - return rv; -} - -static sw_error_t -_dess_cosmap_up_to_ehpri_dp_get(a_uint32_t dev_id, a_uint32_t mode, a_uint32_t up, - a_uint32_t * val) -{ - sw_error_t rv; - a_uint32_t data = 0; - - if (DESS_MAX_UP < up) - { - return SW_BAD_PARAM; - } - - HSL_REG_ENTRY_GET(rv, dev_id, UP_TO_EHPRI, 0, (a_uint8_t *) (&data), - sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - - data = (data >> (up << 2)) & 0xf; - - if (DESS_UP_TO_PRI == mode) - { - *val = (data & 0x7); - } - else - { - *val = (data & 0x8) >> 3; - } - - return SW_OK; -} - -static sw_error_t -_dess_cosmap_pri_to_queue_set(a_uint32_t dev_id, a_uint32_t pri, - a_uint32_t queue) -{ - sw_error_t rv; - a_uint32_t data = 0; - - if ((DESS_MAX_PRI < pri) || (DESS_MAX_QUEUE < queue)) - { - return SW_BAD_PARAM; - } - - HSL_REG_ENTRY_GET(rv, dev_id, PRI_TO_QUEUE, 0, (a_uint8_t *) (&data), - sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - - data &= (~(0x3 << (pri << 2))); - data |= (queue << (pri << 2)); - - HSL_REG_ENTRY_SET(rv, dev_id, PRI_TO_QUEUE, 0, (a_uint8_t *) (&data), - sizeof (a_uint32_t)); - return rv; -} - -static sw_error_t -_dess_cosmap_pri_to_queue_get(a_uint32_t dev_id, a_uint32_t pri, - a_uint32_t * queue) -{ - sw_error_t rv; - a_uint32_t data = 0; - - if (DESS_MAX_PRI < pri) - { - return SW_BAD_PARAM; - } - - HSL_REG_ENTRY_GET(rv, dev_id, PRI_TO_QUEUE, 0, (a_uint8_t *) (&data), - sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - - *queue = (data >> (pri << 2)) & 0x3; - return SW_OK; -} - -static sw_error_t -_dess_cosmap_pri_to_ehqueue_set(a_uint32_t dev_id, a_uint32_t pri, - a_uint32_t queue) -{ - sw_error_t rv; - a_uint32_t data = 0; - - if ((DESS_MAX_PRI < pri) || (DESS_MAX_EH_QUEUE < queue)) - { - return SW_BAD_PARAM; - } - - HSL_REG_ENTRY_GET(rv, dev_id, PRI_TO_EHQUEUE, 0, (a_uint8_t *) (&data), - sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - - data &= (~(0x7 << (pri << 2))); - data |= (queue << (pri << 2)); - - HSL_REG_ENTRY_SET(rv, dev_id, PRI_TO_EHQUEUE, 0, (a_uint8_t *) (&data), - sizeof (a_uint32_t)); - return rv; -} - -static sw_error_t -_dess_cosmap_pri_to_ehqueue_get(a_uint32_t dev_id, a_uint32_t pri, - a_uint32_t * queue) -{ - sw_error_t rv; - a_uint32_t data = 0; - - if (DESS_MAX_PRI < pri) - { - return SW_BAD_PARAM; - } - - HSL_REG_ENTRY_GET(rv, dev_id, PRI_TO_EHQUEUE, 0, (a_uint8_t *) (&data), - sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - - *queue = (data >> (pri << 2)) & 0x7; - return SW_OK; -} - -static sw_error_t -_dess_cosmap_egress_remark_set(a_uint32_t dev_id, a_uint32_t tbl_id, - fal_egress_remark_table_t * tbl) -{ - sw_error_t rv; - a_uint32_t data, addr; - - if (DESS_EGRESS_REAMRK_NUM <= tbl_id) - { - return SW_BAD_PARAM; - } - - data = (tbl->y_up & 0x7) - | ((tbl->y_dei & 0x1) << 3) - | ((tbl->g_up & 0x7) << 4) - | ((tbl->y_dscp & 0x3f) << 8) - | ((tbl->g_dei & 0x1) << 14) - | ((tbl->g_dscp & 0x3f) << 16) - | ((tbl->remark_dscp & 0x1) << 23) - | ((tbl->remark_up & 0x1) << 22) - | ((tbl->remark_dei & 0x1) << 7); - - addr = DESS_EGRESS_REAMRK_ADDR + (tbl_id << 4); - HSL_REG_ENTRY_GEN_SET(rv, dev_id, addr, sizeof (a_uint32_t), - (a_uint8_t *) (&data), sizeof (a_uint32_t)); - return rv; -} - -static sw_error_t -_dess_cosmap_egress_remark_get(a_uint32_t dev_id, a_uint32_t tbl_id, - fal_egress_remark_table_t * tbl) -{ - sw_error_t rv; - a_uint32_t data = 0, addr; - - if (DESS_EGRESS_REAMRK_NUM <= tbl_id) - { - return SW_BAD_PARAM; - } - - aos_mem_zero(tbl, sizeof (fal_egress_remark_table_t)); - - addr = DESS_EGRESS_REAMRK_ADDR + (tbl_id << 4); - HSL_REG_ENTRY_GEN_GET(rv, dev_id, addr, sizeof (a_uint32_t), - (a_uint8_t *) (&data), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - - if (data & (0x1 << 23)) - { - tbl->remark_dscp = A_TRUE; - tbl->y_dscp = (data >> 8) & 0x3f; - tbl->g_dscp = (data >> 16) & 0x3f; - } - - if (data & (0x1 << 22)) - { - tbl->remark_up = A_TRUE; - tbl->y_up = data & 0x7; - tbl->g_up = (data >> 4) & 0x7; - } - - if (data & (0x1 << 7)) - { - tbl->remark_dei = A_TRUE; - tbl->y_dei = (data >> 3) & 0x1; - tbl->g_dei = (data >> 14) & 0x1; - } - - return SW_OK; -} - -/** - * @brief Set dscp to internal priority mapping on one particular device. - * @param[in] dev_id device id - * @param[in] dscp dscp - * @param[in] pri internal priority - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -dess_cosmap_dscp_to_pri_set(a_uint32_t dev_id, a_uint32_t dscp, a_uint32_t pri) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _dess_cosmap_dscp_to_pri_dp_set(dev_id, DESS_DSCP_TO_PRI, dscp, pri); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Get dscp to internal priority mapping on one particular device. - * @param[in] dev_id device id - * @param[in] dscp dscp - * @param[out] pri internal priority - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -dess_cosmap_dscp_to_pri_get(a_uint32_t dev_id, a_uint32_t dscp, - a_uint32_t * pri) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _dess_cosmap_dscp_to_pri_dp_get(dev_id, DESS_DSCP_TO_PRI, dscp, pri); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Set dscp to internal drop precedence mapping on one particular device. - * @param[in] dev_id device id - * @param[in] dscp dscp - * @param[in] dp internal drop precedence - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -dess_cosmap_dscp_to_dp_set(a_uint32_t dev_id, a_uint32_t dscp, a_uint32_t dp) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _dess_cosmap_dscp_to_pri_dp_set(dev_id, DESS_DSCP_TO_DP, dscp, dp); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Get dscp to internal drop precedence mapping on one particular device. - * @param[in] dev_id device id - * @param[in] dscp dscp - * @param[out] dp internal drop precedence - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -dess_cosmap_dscp_to_dp_get(a_uint32_t dev_id, a_uint32_t dscp, a_uint32_t * dp) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _dess_cosmap_dscp_to_pri_dp_get(dev_id, DESS_DSCP_TO_DP, dscp, dp); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Set dot1p to internal priority mapping on one particular device. - * @param[in] dev_id device id - * @param[in] up dot1p - * @param[in] pri internal priority - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -dess_cosmap_up_to_pri_set(a_uint32_t dev_id, a_uint32_t up, a_uint32_t pri) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _dess_cosmap_up_to_pri_dp_set(dev_id, DESS_UP_TO_PRI, up, pri); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Get dot1p to internal priority mapping on one particular device. - * @param[in] dev_id device id - * @param[in] up dot1p - * @param[out] pri internal priority - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -dess_cosmap_up_to_pri_get(a_uint32_t dev_id, a_uint32_t up, a_uint32_t * pri) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _dess_cosmap_up_to_pri_dp_get(dev_id, DESS_UP_TO_PRI, up, pri); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Set dot1p to internal drop precedence mapping on one particular device. - * @param[in] dev_id device id - * @param[in] up dot1p - * @param[in] dp internal drop precedence - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -dess_cosmap_up_to_dp_set(a_uint32_t dev_id, a_uint32_t up, a_uint32_t dp) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _dess_cosmap_up_to_pri_dp_set(dev_id, DESS_UP_TO_DP, up, dp); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Get dot1p to internal drop precedence mapping on one particular device. - * @param[in] dev_id device id - * @param[in] up dot1p - * @param[in] dp internal drop precedence - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -dess_cosmap_up_to_dp_get(a_uint32_t dev_id, a_uint32_t up, a_uint32_t * dp) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _dess_cosmap_up_to_pri_dp_get(dev_id, DESS_UP_TO_DP, up, dp); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Set dscp to internal priority mapping on one particular device for WAN port. - * @param[in] dev_id device id - * @param[in] dscp dscp - * @param[in] pri internal priority - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -dess_cosmap_dscp_to_ehpri_set(a_uint32_t dev_id, a_uint32_t dscp, a_uint32_t pri) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _dess_cosmap_dscp_to_ehpri_dp_set(dev_id, DESS_DSCP_TO_PRI, dscp, pri); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Get dscp to internal priority mapping on one particular device for WAN port. - * @param[in] dev_id device id - * @param[in] dscp dscp - * @param[out] pri internal priority - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -dess_cosmap_dscp_to_ehpri_get(a_uint32_t dev_id, a_uint32_t dscp, - a_uint32_t * pri) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _dess_cosmap_dscp_to_ehpri_dp_get(dev_id, DESS_DSCP_TO_PRI, dscp, pri); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Set dscp to internal drop precedence mapping on one particular device for WAN port. - * @param[in] dev_id device id - * @param[in] dscp dscp - * @param[in] dp internal drop precedence - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -dess_cosmap_dscp_to_ehdp_set(a_uint32_t dev_id, a_uint32_t dscp, a_uint32_t dp) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _dess_cosmap_dscp_to_ehpri_dp_set(dev_id, DESS_DSCP_TO_DP, dscp, dp); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Get dscp to internal drop precedence mapping on one particular device for WAN port. - * @param[in] dev_id device id - * @param[in] dscp dscp - * @param[out] dp internal drop precedence - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -dess_cosmap_dscp_to_ehdp_get(a_uint32_t dev_id, a_uint32_t dscp, a_uint32_t * dp) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _dess_cosmap_dscp_to_ehpri_dp_get(dev_id, DESS_DSCP_TO_DP, dscp, dp); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Set dot1p to internal priority mapping on one particular device for WAN port. - * @param[in] dev_id device id - * @param[in] up dot1p - * @param[in] pri internal priority - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -dess_cosmap_up_to_ehpri_set(a_uint32_t dev_id, a_uint32_t up, a_uint32_t pri) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _dess_cosmap_up_to_ehpri_dp_set(dev_id, DESS_UP_TO_PRI, up, pri); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Get dot1p to internal priority mapping on one particular device for WAN port. - * @param[in] dev_id device id - * @param[in] up dot1p - * @param[out] pri internal priority - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -dess_cosmap_up_to_ehpri_get(a_uint32_t dev_id, a_uint32_t up, a_uint32_t * pri) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _dess_cosmap_up_to_ehpri_dp_get(dev_id, DESS_UP_TO_PRI, up, pri); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Set dot1p to internal drop precedence mapping on one particular device for WAN port. - * @param[in] dev_id device id - * @param[in] up dot1p - * @param[in] dp internal drop precedence - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -dess_cosmap_up_to_ehdp_set(a_uint32_t dev_id, a_uint32_t up, a_uint32_t dp) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _dess_cosmap_up_to_ehpri_dp_set(dev_id, DESS_UP_TO_DP, up, dp); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Get dot1p to internal drop precedence mapping on one particular device for WAN port. - * @param[in] dev_id device id - * @param[in] up dot1p - * @param[in] dp internal drop precedence - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -dess_cosmap_up_to_ehdp_get(a_uint32_t dev_id, a_uint32_t up, a_uint32_t * dp) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _dess_cosmap_up_to_ehpri_dp_get(dev_id, DESS_UP_TO_DP, up, dp); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Set internal priority to queue mapping on one particular device. - * @details Comments: - * This function is for port 1/2/3/4 which have four egress queues - * @param[in] dev_id device id - * @param[in] pri internal priority - * @param[in] queue queue id - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -dess_cosmap_pri_to_queue_set(a_uint32_t dev_id, a_uint32_t pri, - a_uint32_t queue) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _dess_cosmap_pri_to_queue_set(dev_id, pri, queue); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Get internal priority to queue mapping on one particular device. - * @details Comments: - * This function is for port 1/2/3/4 which have four egress queues - * @param[in] dev_id device id - * @param[in] pri internal priority - * @param[out] queue queue id - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -dess_cosmap_pri_to_queue_get(a_uint32_t dev_id, a_uint32_t pri, - a_uint32_t * queue) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _dess_cosmap_pri_to_queue_get(dev_id, pri, queue); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Set internal priority to queue mapping on one particular device. - * @details Comments: - * This function is for port 0/5/6 which have six egress queues - * @param[in] dev_id device id - * @param[in] pri internal priority - * @param[in] queue queue id - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -dess_cosmap_pri_to_ehqueue_set(a_uint32_t dev_id, a_uint32_t pri, - a_uint32_t queue) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _dess_cosmap_pri_to_ehqueue_set(dev_id, pri, queue); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Get internal priority to queue mapping on one particular device. - * @details Comments: - * This function is for port 0/5/6 which have six egress queues - * @param[in] dev_id device id - * @param[in] pri internal priority - * @param[in] queue queue id - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -dess_cosmap_pri_to_ehqueue_get(a_uint32_t dev_id, a_uint32_t pri, - a_uint32_t * queue) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _dess_cosmap_pri_to_ehqueue_get(dev_id, pri, queue); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Set egress queue based CoS remap table on one particular device. - * @param[in] dev_id device id - * @param[in] tbl_id CoS remap table id - * @param[in] tbl CoS remap table - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -dess_cosmap_egress_remark_set(a_uint32_t dev_id, a_uint32_t tbl_id, - fal_egress_remark_table_t * tbl) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _dess_cosmap_egress_remark_set(dev_id, tbl_id, tbl); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Get egress queue based CoS remap table on one particular device. - * @param[in] dev_id device id - * @param[in] tbl_id CoS remap table id - * @param[out] tbl CoS remap table - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -dess_cosmap_egress_remark_get(a_uint32_t dev_id, a_uint32_t tbl_id, - fal_egress_remark_table_t * tbl) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _dess_cosmap_egress_remark_get(dev_id, tbl_id, tbl); - HSL_API_UNLOCK; - return rv; -} - -sw_error_t -dess_cosmap_init(a_uint32_t dev_id) -{ - HSL_DEV_ID_CHECK(dev_id); - -#ifndef HSL_STANDALONG - { - hsl_api_t *p_api; - - SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id)); - - p_api->cosmap_dscp_to_pri_set = dess_cosmap_dscp_to_pri_set; - p_api->cosmap_dscp_to_pri_get = dess_cosmap_dscp_to_pri_get; - p_api->cosmap_dscp_to_dp_set = dess_cosmap_dscp_to_dp_set; - p_api->cosmap_dscp_to_dp_get = dess_cosmap_dscp_to_dp_get; - p_api->cosmap_up_to_pri_set = dess_cosmap_up_to_pri_set; - p_api->cosmap_up_to_pri_get = dess_cosmap_up_to_pri_get; - p_api->cosmap_up_to_dp_set = dess_cosmap_up_to_dp_set; - p_api->cosmap_up_to_dp_get = dess_cosmap_up_to_dp_get; - p_api->cosmap_dscp_to_ehpri_set = dess_cosmap_dscp_to_ehpri_set; - p_api->cosmap_dscp_to_ehpri_get = dess_cosmap_dscp_to_ehpri_get; - p_api->cosmap_dscp_to_ehdp_set = dess_cosmap_dscp_to_ehdp_set; - p_api->cosmap_dscp_to_ehdp_get = dess_cosmap_dscp_to_ehdp_get; - p_api->cosmap_up_to_ehpri_set = dess_cosmap_up_to_ehpri_set; - p_api->cosmap_up_to_ehpri_get = dess_cosmap_up_to_ehpri_get; - p_api->cosmap_up_to_ehdp_set = dess_cosmap_up_to_ehdp_set; - p_api->cosmap_up_to_ehdp_get = dess_cosmap_up_to_ehdp_get; - p_api->cosmap_pri_to_queue_set = dess_cosmap_pri_to_queue_set; - p_api->cosmap_pri_to_queue_get = dess_cosmap_pri_to_queue_get; - p_api->cosmap_pri_to_ehqueue_set = dess_cosmap_pri_to_ehqueue_set; - p_api->cosmap_pri_to_ehqueue_get = dess_cosmap_pri_to_ehqueue_get; - p_api->cosmap_egress_remark_set = dess_cosmap_egress_remark_set; - p_api->cosmap_egress_remark_get = dess_cosmap_egress_remark_get; - } -#endif - - return SW_OK; -} - -/** - * @} - */ - diff --git a/feeds/ipq807x/qca-ssdk/src/src/hsl/dess/dess_fdb.c b/feeds/ipq807x/qca-ssdk/src/src/hsl/dess/dess_fdb.c deleted file mode 100755 index c92899e71..000000000 --- a/feeds/ipq807x/qca-ssdk/src/src/hsl/dess/dess_fdb.c +++ /dev/null @@ -1,2431 +0,0 @@ -/* - * Copyright (c) 2014-2016, The Linux Foundation. All rights reserved. - * Permission to use, copy, modify, and/or distribute this software for - * any purpose with or without fee is hereby granted, provided that the - * above copyright notice and this permission notice appear in all copies. - * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES - * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR - * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES - * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN - * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT - * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. - */ - - -/** - * @defgroup dess_fdb DESS_FDB - * @{ - */ -#include "sw.h" -#include "hsl.h" -#include "hsl_dev.h" -#include "hsl_port_prop.h" -#include "dess_fdb.h" -#include "dess_reg.h" -#include "dess_fdb_prv.h" - -static aos_lock_t dess_fdb_lock; -static sw_error_t -_dess_wl_feature_check(a_uint32_t dev_id) -{ - sw_error_t rv; - a_uint32_t entry = 0; - - HSL_REG_FIELD_GET(rv, dev_id, MASK_CTL, 0, DEVICE_ID, - (a_uint8_t *) (&entry), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - - if (DESS_DEVICE_ID == entry) - { - return SW_OK; - } - else - { - return SW_NOT_SUPPORTED; - } -} - -static a_bool_t -_dess_fdb_is_zeroaddr(fal_mac_addr_t addr) -{ - a_uint32_t i; - - for (i = 0; i < 6; i++) - { - if (addr.uc[i]) - { - return A_FALSE; - } - } - - return A_TRUE; -} - -static void -_dess_fdb_fill_addr(fal_mac_addr_t addr, a_uint32_t * reg0, a_uint32_t * reg1) -{ - SW_SET_REG_BY_FIELD(ADDR_TABLE_FUNC1, AT_ADDR_BYTE0, addr.uc[0], *reg1); - SW_SET_REG_BY_FIELD(ADDR_TABLE_FUNC1, AT_ADDR_BYTE1, addr.uc[1], *reg1); - - SW_SET_REG_BY_FIELD(ADDR_TABLE_FUNC0, AT_ADDR_BYTE2, addr.uc[2], *reg0); - SW_SET_REG_BY_FIELD(ADDR_TABLE_FUNC0, AT_ADDR_BYTE3, addr.uc[3], *reg0); - SW_SET_REG_BY_FIELD(ADDR_TABLE_FUNC0, AT_ADDR_BYTE4, addr.uc[4], *reg0); - SW_SET_REG_BY_FIELD(ADDR_TABLE_FUNC0, AT_ADDR_BYTE5, addr.uc[5], *reg0); - - return; -} - -static sw_error_t -_dess_atu_sw_to_hw(a_uint32_t dev_id, const fal_fdb_entry_t * entry, - a_uint32_t reg[]) -{ - a_uint32_t port; - sw_error_t rv; - - if (A_TRUE == entry->white_list_en) - { - rv = _dess_wl_feature_check(dev_id); - SW_RTN_ON_ERROR(rv); - - SW_SET_REG_BY_FIELD(ADDR_TABLE_FUNC2, WL_EN, 1, reg[2]); - } - - if (FAL_SVL_FID == entry->fid) - { - SW_SET_REG_BY_FIELD(ADDR_TABLE_FUNC2, AT_VID, 0, reg[2]); - SW_SET_REG_BY_FIELD(ADDR_TABLE_FUNC1, AT_SVL_EN, 1, reg[1]); - } - else if (DESS_MAX_FID >= entry->fid) - { - SW_SET_REG_BY_FIELD(ADDR_TABLE_FUNC2, AT_VID, (entry->fid), reg[2]); - SW_SET_REG_BY_FIELD(ADDR_TABLE_FUNC1, AT_SVL_EN, 0, reg[1]); - } - else - { - return SW_BAD_PARAM; - } - - if (A_FALSE == entry->portmap_en) - { - if (A_TRUE != - hsl_port_prop_check(dev_id, entry->port.id, HSL_PP_INCL_CPU)) - { - return SW_BAD_PARAM; - } - - port = 0x1UL << entry->port.id; - } - else - { - if (A_FALSE == - hsl_mports_prop_check(dev_id, entry->port.map, HSL_PP_INCL_CPU)) - { - return SW_BAD_PARAM; - } - - port = entry->port.map; - } - SW_SET_REG_BY_FIELD(ADDR_TABLE_FUNC1, DES_PORT, port, reg[1]); - - if (FAL_MAC_CPY_TO_CPU == entry->dacmd) - { - SW_SET_REG_BY_FIELD(ADDR_TABLE_FUNC2, COPY_TO_CPU, 1, reg[2]); - } - else if (FAL_MAC_RDT_TO_CPU == entry->dacmd) - { - SW_SET_REG_BY_FIELD(ADDR_TABLE_FUNC2, REDRCT_TO_CPU, 1, reg[2]); - } - else if (FAL_MAC_FRWRD != entry->dacmd) - { - return SW_NOT_SUPPORTED; - } - - if (A_TRUE == entry->leaky_en) - { - SW_SET_REG_BY_FIELD(ADDR_TABLE_FUNC2, LEAKY_EN, 1, reg[2]); - } - else - { - SW_SET_REG_BY_FIELD(ADDR_TABLE_FUNC2, LEAKY_EN, 0, reg[2]); - } - - if (A_TRUE == entry->static_en) - { - SW_SET_REG_BY_FIELD(ADDR_TABLE_FUNC2, AT_STATUS, 15, reg[2]); - } - else - { - SW_SET_REG_BY_FIELD(ADDR_TABLE_FUNC2, AT_STATUS, 7, reg[2]); - } - - if (FAL_MAC_DROP == entry->sacmd) - { - SW_SET_REG_BY_FIELD(ADDR_TABLE_FUNC1, SA_DROP_EN, 1, reg[1]); - } - else if (FAL_MAC_FRWRD != entry->sacmd) - { - return SW_NOT_SUPPORTED; - } - - if (A_TRUE == entry->mirror_en) - { - SW_SET_REG_BY_FIELD(ADDR_TABLE_FUNC1, MIRROR_EN, 1, reg[1]); - } - - if (A_TRUE == entry->cross_pt_state) - { - SW_SET_REG_BY_FIELD(ADDR_TABLE_FUNC1, CROSS_PT, 1, reg[1]); - } - else - { - SW_SET_REG_BY_FIELD(ADDR_TABLE_FUNC1, CROSS_PT, 0, reg[1]); - } - - if (A_TRUE == entry->da_pri_en) - { - SW_SET_REG_BY_FIELD(ADDR_TABLE_FUNC1, AT_PRI_EN, 1, reg[1]); - SW_SET_REG_BY_FIELD(ADDR_TABLE_FUNC1, AT_PRI, (entry->da_queue & 0x7), - reg[1]); - } - else - { - SW_SET_REG_BY_FIELD(ADDR_TABLE_FUNC1, AT_PRI_EN, 0, reg[1]); - } - - if (A_TRUE == entry->load_balance_en) - { - SW_SET_REG_BY_FIELD(ADDR_TABLE_FUNC2, LOAD_BALANCE_EN, 1, reg[2]); - SW_SET_REG_BY_FIELD(ADDR_TABLE_FUNC2, LOAD_BALANCE, - (entry->load_balance & 0x3), reg[2]); - } - else - { - SW_SET_REG_BY_FIELD(ADDR_TABLE_FUNC2, LOAD_BALANCE_EN, 0, reg[2]); - } - - _dess_fdb_fill_addr(entry->addr, ®[0], ®[1]); - return SW_OK; -} - -static void -_dess_atu_hw_to_sw(const a_uint32_t reg[], fal_fdb_entry_t * entry) -{ - a_uint32_t i, data; - - aos_mem_zero(entry, sizeof (fal_fdb_entry_t)); - - SW_GET_FIELD_BY_REG(ADDR_TABLE_FUNC1, AT_SVL_EN, data, reg[1]); - if (data) - { - entry->fid = FAL_SVL_FID; - } - else - { - SW_GET_FIELD_BY_REG(ADDR_TABLE_FUNC2, AT_VID, data, reg[2]); - entry->fid = data; - } - - entry->dacmd = FAL_MAC_FRWRD; - SW_GET_FIELD_BY_REG(ADDR_TABLE_FUNC2, COPY_TO_CPU, data, reg[2]); - if (1 == data) - { - entry->dacmd = FAL_MAC_CPY_TO_CPU; - } - - SW_GET_FIELD_BY_REG(ADDR_TABLE_FUNC2, REDRCT_TO_CPU, data, reg[2]); - if (1 == data) - { - entry->dacmd = FAL_MAC_RDT_TO_CPU; - } - - entry->sacmd = FAL_MAC_FRWRD; - SW_GET_FIELD_BY_REG(ADDR_TABLE_FUNC1, SA_DROP_EN, data, reg[1]); - if (1 == data) - { - entry->sacmd = FAL_MAC_DROP; - } - - entry->leaky_en = A_FALSE; - SW_GET_FIELD_BY_REG(ADDR_TABLE_FUNC2, LEAKY_EN, data, reg[2]); - if (1 == data) - { - entry->leaky_en = A_TRUE; - } - - entry->static_en = A_FALSE; - SW_GET_FIELD_BY_REG(ADDR_TABLE_FUNC2, AT_STATUS, data, reg[2]); - if (0xf == data) - { - entry->static_en = A_TRUE; - } - - entry->mirror_en = A_FALSE; - SW_GET_FIELD_BY_REG(ADDR_TABLE_FUNC1, MIRROR_EN, data, reg[1]); - if (1 == data) - { - entry->mirror_en = A_TRUE; - } - - entry->da_pri_en = A_FALSE; - SW_GET_FIELD_BY_REG(ADDR_TABLE_FUNC1, AT_PRI_EN, data, reg[1]); - if (1 == data) - { - SW_GET_FIELD_BY_REG(ADDR_TABLE_FUNC1, AT_PRI, data, reg[1]); - entry->da_pri_en = A_TRUE; - entry->da_queue = data & 0x7; - } - - entry->cross_pt_state = A_FALSE; - SW_GET_FIELD_BY_REG(ADDR_TABLE_FUNC1, CROSS_PT, data, reg[1]); - if (1 == data) - { - entry->cross_pt_state = A_TRUE; - } - - SW_GET_FIELD_BY_REG(ADDR_TABLE_FUNC1, DES_PORT, data, reg[1]); - entry->portmap_en = A_TRUE; - entry->port.map = data; - - for (i = 2; i < 6; i++) - { - entry->addr.uc[i] = (reg[0] >> ((5 - i) << 3)) & 0xff; - } - - for (i = 0; i < 2; i++) - { - entry->addr.uc[i] = (reg[1] >> ((1 - i) << 3)) & 0xff; - } - - entry->white_list_en = A_FALSE; - SW_GET_FIELD_BY_REG(ADDR_TABLE_FUNC2, WL_EN, data, reg[2]); - if (1 == data) - { - entry->white_list_en = A_TRUE; - } - - entry->load_balance_en = A_FALSE; - entry->load_balance = 0; - SW_GET_FIELD_BY_REG(ADDR_TABLE_FUNC2, LOAD_BALANCE_EN, data, reg[2]); - if (1 == data) - { - entry->load_balance_en = A_TRUE; - SW_GET_FIELD_BY_REG(ADDR_TABLE_FUNC2, LOAD_BALANCE, data, reg[2]); - entry->load_balance = data; - } - - return; -} - -static sw_error_t -_dess_atu_down_to_hw(a_uint32_t dev_id, a_uint32_t reg[]) -{ - sw_error_t rv; - - HSL_REG_ENTRY_SET(rv, dev_id, ADDR_TABLE_FUNC0, 0, - (a_uint8_t *) (®[0]), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - - HSL_REG_ENTRY_SET(rv, dev_id, ADDR_TABLE_FUNC1, 0, - (a_uint8_t *) (®[1]), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - - HSL_REG_ENTRY_SET(rv, dev_id, ADDR_TABLE_FUNC2, 0, - (a_uint8_t *) (®[2]), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - - HSL_REG_ENTRY_SET(rv, dev_id, ADDR_TABLE_FUNC3, 0, - (a_uint8_t *) (®[3]), sizeof (a_uint32_t)); - return rv; -} - -static sw_error_t -_dess_atu_up_to_sw(a_uint32_t dev_id, a_uint32_t reg[]) -{ - sw_error_t rv; - - HSL_REG_ENTRY_GET(rv, dev_id, ADDR_TABLE_FUNC0, 0, - (a_uint8_t *) (®[0]), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - - HSL_REG_ENTRY_GET(rv, dev_id, ADDR_TABLE_FUNC1, 0, - (a_uint8_t *) (®[1]), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - - HSL_REG_ENTRY_GET(rv, dev_id, ADDR_TABLE_FUNC2, 0, - (a_uint8_t *) (®[2]), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - - HSL_REG_ENTRY_GET(rv, dev_id, ADDR_TABLE_FUNC3, 0, - (a_uint8_t *) (®[3]), sizeof (a_uint32_t)); - return rv; -} - -static sw_error_t -_dess_fdb_commit(a_uint32_t dev_id, a_uint32_t op) -{ - sw_error_t rv; - a_uint32_t busy = 1; - a_uint32_t full_vio; - a_uint32_t i = 2000; - a_uint32_t entry = 0; - a_uint32_t hwop = op; - - while (busy && --i) - { - HSL_REG_ENTRY_GET(rv, dev_id, ADDR_TABLE_FUNC3, 0, - (a_uint8_t *) (&entry), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - SW_GET_FIELD_BY_REG(ADDR_TABLE_FUNC3, AT_BUSY, busy, entry); - } - - if (0 == i) - { - return SW_BUSY; - } - - if (ARL_FIRST_ENTRY == op) - { - hwop = ARL_NEXT_ENTRY; - } - - SW_SET_REG_BY_FIELD(ADDR_TABLE_FUNC3, AT_BUSY, 1, entry); - - if (ARL_FLUSH_PORT_AND_STATIC == hwop) - { - hwop = ARL_FLUSH_PORT_UNICAST; - SW_SET_REG_BY_FIELD(ADDR_TABLE_FUNC3, FLUSH_ST_EN, 1, entry); - } - - if (ARL_FLUSH_PORT_NO_STATIC == hwop) - { - hwop = ARL_FLUSH_PORT_UNICAST; - SW_SET_REG_BY_FIELD(ADDR_TABLE_FUNC3, FLUSH_ST_EN, 0, entry); - } - - SW_SET_REG_BY_FIELD(ADDR_TABLE_FUNC3, AT_FUNC, hwop, entry); - - HSL_REG_ENTRY_SET(rv, dev_id, ADDR_TABLE_FUNC3, 0, - (a_uint8_t *) (&entry), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - - busy = 1; - i = 2000; - while (busy && --i) - { - HSL_REG_ENTRY_GET(rv, dev_id, ADDR_TABLE_FUNC3, 0, - (a_uint8_t *) (&entry), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - SW_GET_FIELD_BY_REG(ADDR_TABLE_FUNC3, AT_BUSY, busy, entry); - } - - if (0 == i) - { - return SW_FAIL; - } - - SW_GET_FIELD_BY_REG(ADDR_TABLE_FUNC3, AT_FULL_VIO, full_vio, entry); - - if (full_vio) - { - /* must clear AT_FULL_VOI bit */ - entry = 0x1000; - HSL_REG_ENTRY_SET(rv, dev_id, ADDR_TABLE_FUNC3, 0, - (a_uint8_t *) (&entry), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - - if (ARL_LOAD_ENTRY == hwop) - { - return SW_FULL; - } - else if ((ARL_PURGE_ENTRY == hwop) - || (ARL_FLUSH_PORT_UNICAST == hwop)) - { - return SW_NOT_FOUND; - } - else - { - return SW_FAIL; - } - } - - return SW_OK; -} - -static sw_error_t -_dess_fdb_get(a_uint32_t dev_id, fal_fdb_op_t * option, fal_fdb_entry_t * entry, - a_uint32_t hwop) -{ - sw_error_t rv; - a_uint32_t i, port = 0, status, reg[4] = { 0 }; - - HSL_DEV_ID_CHECK(dev_id); - - if (A_TRUE == option->port_en) - { - SW_SET_REG_BY_FIELD(ADDR_TABLE_FUNC3, AT_PORT_EN, 1, reg[3]); - if (A_FALSE == entry->portmap_en) - { - if (A_TRUE != - hsl_port_prop_check(dev_id, entry->port.id, HSL_PP_INCL_CPU)) - { - return SW_BAD_PARAM; - } - port = entry->port.id; - } - else - { - if (A_FALSE == - hsl_mports_prop_check(dev_id, entry->port.map, - HSL_PP_INCL_CPU)) - { - return SW_BAD_PARAM; - } - - status = 0; - for (i = 0; i < SW_MAX_NR_PORT; i++) - { - if ((entry->port.map) & (0x1UL << i)) - { - if (status) - { - return SW_BAD_PARAM; - } - port = i; - status = 1; - } - } - } - SW_SET_REG_BY_FIELD(ADDR_TABLE_FUNC3, AT_PORT_NUM, port, reg[3]); - } - - if (A_TRUE == option->fid_en) - { - SW_SET_REG_BY_FIELD(ADDR_TABLE_FUNC3, AT_VID_EN, 1, reg[3]); - } - - if (A_TRUE == option->multicast_en) - { - SW_SET_REG_BY_FIELD(ADDR_TABLE_FUNC3, AT_MULTI_EN, 1, reg[3]); - } - - if (FAL_SVL_FID == entry->fid) - { - SW_SET_REG_BY_FIELD(ADDR_TABLE_FUNC2, AT_VID, 0, reg[2]); - SW_SET_REG_BY_FIELD(ADDR_TABLE_FUNC1, AT_SVL_EN, 1, reg[1]); - } - else if (DESS_MAX_FID >= entry->fid) - { - SW_SET_REG_BY_FIELD(ADDR_TABLE_FUNC2, AT_VID, entry->fid, reg[2]); - SW_SET_REG_BY_FIELD(ADDR_TABLE_FUNC1, AT_SVL_EN, 0, reg[1]); - } - else - { - return SW_BAD_PARAM; - } - - if (ARL_FIRST_ENTRY != hwop) - { - SW_SET_REG_BY_FIELD(ADDR_TABLE_FUNC2, AT_STATUS, 0xf, reg[2]); - } - - _dess_fdb_fill_addr(entry->addr, ®[0], ®[1]); - - rv = _dess_atu_down_to_hw(dev_id, reg); - SW_RTN_ON_ERROR(rv); - - rv = _dess_fdb_commit(dev_id, hwop); - SW_RTN_ON_ERROR(rv); - - rv = _dess_atu_up_to_sw(dev_id, reg); - SW_RTN_ON_ERROR(rv); - - _dess_atu_hw_to_sw(reg, entry); - - SW_GET_FIELD_BY_REG(ADDR_TABLE_FUNC2, AT_STATUS, status, reg[2]); - if ((A_TRUE == _dess_fdb_is_zeroaddr(entry->addr)) - && (0 == status)) - { - if (ARL_NEXT_ENTRY == hwop) - { - return SW_NO_MORE; - } - else - { - return SW_NOT_FOUND; - } - } - else - { - return SW_OK; - } - - return SW_OK; -} - -static sw_error_t -_dess_fdb_add(a_uint32_t dev_id, const fal_fdb_entry_t * entry) -{ - sw_error_t rv; - a_uint32_t reg[4] = { 0 }; - - HSL_DEV_ID_CHECK(dev_id); - - rv = _dess_atu_sw_to_hw(dev_id, entry, reg); - SW_RTN_ON_ERROR(rv); - - rv = _dess_atu_down_to_hw(dev_id, reg); - SW_RTN_ON_ERROR(rv); - - rv = _dess_fdb_commit(dev_id, ARL_LOAD_ENTRY); - return rv; -} - -static sw_error_t -_dess_fdb_del_all(a_uint32_t dev_id, a_uint32_t flag) -{ - sw_error_t rv; - - HSL_DEV_ID_CHECK(dev_id); - - if (FAL_FDB_DEL_STATIC & flag) - { - rv = _dess_fdb_commit(dev_id, ARL_FLUSH_ALL); - } - else - { - rv = _dess_fdb_commit(dev_id, ARL_FLUSH_ALL_UNLOCK); - } - - return rv; -} - -static sw_error_t -_dess_fdb_del_by_port(a_uint32_t dev_id, fal_port_t port_id, a_uint32_t flag) -{ - sw_error_t rv; - a_uint32_t reg = 0; - - HSL_DEV_ID_CHECK(dev_id); - - if (A_FALSE == hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU)) - { - return SW_BAD_PARAM; - } - - SW_SET_REG_BY_FIELD(ADDR_TABLE_FUNC3, AT_PORT_NUM, port_id, reg); - - HSL_REG_ENTRY_SET(rv, dev_id, ADDR_TABLE_FUNC3, 0, (a_uint8_t *) (®), - sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - - if (FAL_FDB_DEL_STATIC & flag) - { - rv = _dess_fdb_commit(dev_id, ARL_FLUSH_PORT_AND_STATIC); - } - else - { - rv = _dess_fdb_commit(dev_id, ARL_FLUSH_PORT_NO_STATIC); - } - - return rv; -} - -static sw_error_t -_dess_fdb_del_by_mac(a_uint32_t dev_id, const fal_fdb_entry_t * entry) -{ - sw_error_t rv; - a_uint32_t reg0 = 0, reg1 = 0, reg2 = 0; - - HSL_DEV_ID_CHECK(dev_id); - - _dess_fdb_fill_addr(entry->addr, ®0, ®1); - - if (FAL_SVL_FID == entry->fid) - { - SW_SET_REG_BY_FIELD(ADDR_TABLE_FUNC2, AT_VID, 0, reg2); - SW_SET_REG_BY_FIELD(ADDR_TABLE_FUNC1, AT_SVL_EN, 1, reg1); - } - else if (DESS_MAX_FID >= entry->fid) - { - SW_SET_REG_BY_FIELD(ADDR_TABLE_FUNC2, AT_VID, (entry->fid), reg2); - SW_SET_REG_BY_FIELD(ADDR_TABLE_FUNC1, AT_SVL_EN, 0, reg1); - } - else - { - return SW_BAD_PARAM; - } - - HSL_REG_ENTRY_SET(rv, dev_id, ADDR_TABLE_FUNC2, 0, (a_uint8_t *) (®2), - sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - - HSL_REG_ENTRY_SET(rv, dev_id, ADDR_TABLE_FUNC1, 0, (a_uint8_t *) (®1), - sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - - HSL_REG_ENTRY_SET(rv, dev_id, ADDR_TABLE_FUNC0, 0, (a_uint8_t *) (®0), - sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - - rv = _dess_fdb_commit(dev_id, ARL_PURGE_ENTRY); - return rv; -} - -static sw_error_t -_dess_fdb_find(a_uint32_t dev_id, fal_fdb_entry_t * entry) -{ - sw_error_t rv; - fal_fdb_op_t option; - - aos_mem_zero(&option, sizeof (fal_fdb_op_t)); - rv = _dess_fdb_get(dev_id, &option, entry, ARL_FIND_ENTRY); - return rv; -} - -static sw_error_t -_dess_fdb_extend_next(a_uint32_t dev_id, fal_fdb_op_t * option, - fal_fdb_entry_t * entry) -{ - sw_error_t rv; - - rv = _dess_fdb_get(dev_id, option, entry, ARL_NEXT_ENTRY); - return rv; -} - -static sw_error_t -_dess_fdb_extend_first(a_uint32_t dev_id, fal_fdb_op_t * option, - fal_fdb_entry_t * entry) -{ - sw_error_t rv; - - rv = _dess_fdb_get(dev_id, option, entry, ARL_FIRST_ENTRY); - return rv; -} - -static sw_error_t -_dess_fdb_transfer(a_uint32_t dev_id, fal_port_t old_port, fal_port_t new_port, - a_uint32_t fid, fal_fdb_op_t * option) -{ - sw_error_t rv; - a_uint32_t reg[4] = { 0 }; - - if (A_TRUE == option->port_en) - { - return SW_NOT_SUPPORTED; - } - - if (A_TRUE == option->fid_en) - { - SW_SET_REG_BY_FIELD(ADDR_TABLE_FUNC3, AT_VID_EN, 1, reg[3]); - } - - if (A_TRUE == option->multicast_en) - { - SW_SET_REG_BY_FIELD(ADDR_TABLE_FUNC3, AT_MULTI_EN, 1, reg[3]); - } - - if (FAL_SVL_FID == fid) - { - SW_SET_REG_BY_FIELD(ADDR_TABLE_FUNC2, AT_VID, 0, reg[2]); - SW_SET_REG_BY_FIELD(ADDR_TABLE_FUNC1, AT_SVL_EN, 1, reg[1]); - } - else if (DESS_MAX_FID >= fid) - { - SW_SET_REG_BY_FIELD(ADDR_TABLE_FUNC2, AT_VID, fid, reg[2]); - SW_SET_REG_BY_FIELD(ADDR_TABLE_FUNC1, AT_SVL_EN, 0, reg[1]); - } - else - { - return SW_BAD_PARAM; - } - - SW_SET_REG_BY_FIELD(ADDR_TABLE_FUNC3, AT_PORT_NUM, old_port, reg[3]); - SW_SET_REG_BY_FIELD(ADDR_TABLE_FUNC3, NEW_PORT_NUM, new_port, reg[3]); - - rv = _dess_atu_down_to_hw(dev_id, reg); - SW_RTN_ON_ERROR(rv); - - rv = _dess_fdb_commit(dev_id, ARL_TRANSFER_ENTRY); - return rv; -} - -static sw_error_t -_dess_fdb_port_learn_set(a_uint32_t dev_id, fal_port_t port_id, a_bool_t enable) -{ - a_uint32_t data; - sw_error_t rv; - - HSL_DEV_ID_CHECK(dev_id); - - if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU)) - { - return SW_BAD_PARAM; - } - - if (A_TRUE == enable) - { - data = 1; - } - else if (A_FALSE == enable) - { - data = 0; - } - else - { - return SW_BAD_PARAM; - } - - HSL_REG_FIELD_SET(rv, dev_id, PORT_LOOKUP_CTL, port_id, LEARN_EN, - (a_uint8_t *) (&data), sizeof (a_uint32_t)); - return rv; -} - -static sw_error_t -_dess_fdb_port_learn_get(a_uint32_t dev_id, fal_port_t port_id, - a_bool_t * enable) -{ - a_uint32_t data = 0; - sw_error_t rv; - - HSL_DEV_ID_CHECK(dev_id); - - if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU)) - { - return SW_BAD_PARAM; - } - - HSL_REG_FIELD_GET(rv, dev_id, PORT_LOOKUP_CTL, port_id, LEARN_EN, - (a_uint8_t *) (&data), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - - if (1 == data) - { - *enable = A_TRUE; - } - else - { - *enable = A_FALSE; - } - - return SW_OK; -} - -static sw_error_t -_dess_fdb_age_ctrl_set(a_uint32_t dev_id, a_bool_t enable) -{ - a_uint32_t data; - sw_error_t rv; - - HSL_DEV_ID_CHECK(dev_id); - - if (A_TRUE == enable) - { - data = 1; - } - else if (A_FALSE == enable) - { - data = 0; - } - else - { - return SW_BAD_PARAM; - } - - HSL_REG_FIELD_SET(rv, dev_id, ADDR_TABLE_CTL, 0, AGE_EN, - (a_uint8_t *) (&data), sizeof (a_uint32_t)); - return rv; -} - -static sw_error_t -_dess_fdb_vlan_ivl_svl_set(a_uint32_t dev_id, fal_fdb_smode smode) -{ - a_uint32_t data; - sw_error_t rv; - - HSL_DEV_ID_CHECK(dev_id); - - data = smode; - - HSL_REG_FIELD_SET(rv, dev_id, ADDR_TABLE_CTL, 0, ARL_INI_EN, - (a_uint8_t *) (&data), sizeof (a_uint32_t)); - return rv; -} - -static sw_error_t -_dess_fdb_vlan_ivl_svl_get(a_uint32_t dev_id, fal_fdb_smode* smode) -{ - a_uint32_t data = 0; - sw_error_t rv; - - HSL_DEV_ID_CHECK(dev_id); - - HSL_REG_FIELD_GET(rv, dev_id, ADDR_TABLE_CTL, 0, ARL_INI_EN, - (a_uint8_t *) (&data), sizeof (a_uint32_t)); - - *smode = data; - - return rv; -} - - - -static sw_error_t -_dess_fdb_age_ctrl_get(a_uint32_t dev_id, a_bool_t * enable) -{ - a_uint32_t data = 0; - sw_error_t rv; - - HSL_DEV_ID_CHECK(dev_id); - - HSL_REG_FIELD_GET(rv, dev_id, ADDR_TABLE_CTL, 0, AGE_EN, - (a_uint8_t *) (&data), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - - if (1 == data) - { - *enable = A_TRUE; - } - else - { - *enable = A_FALSE; - } - - return SW_OK; -} - -static sw_error_t -_dess_fdb_age_time_set(a_uint32_t dev_id, a_uint32_t * time) -{ - a_uint32_t data; - sw_error_t rv; - - HSL_DEV_ID_CHECK(dev_id); - - if ((65535 * 7 < *time) || (7 > *time)) - { - return SW_BAD_PARAM; - } - data = *time / 7; - *time = data * 7; - HSL_REG_FIELD_SET(rv, dev_id, ADDR_TABLE_CTL, 0, AGE_TIME, - (a_uint8_t *) (&data), sizeof (a_uint32_t)); - return rv; -} - -static sw_error_t -_dess_fdb_age_time_get(a_uint32_t dev_id, a_uint32_t * time) -{ - a_uint32_t data = 0; - sw_error_t rv; - - HSL_DEV_ID_CHECK(dev_id); - - HSL_REG_FIELD_GET(rv, dev_id, ADDR_TABLE_CTL, 0, AGE_TIME, - (a_uint8_t *) (&data), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - - *time = data * 7; - return SW_OK; -} - -static sw_error_t -_dess_port_fdb_learn_limit_set(a_uint32_t dev_id, fal_port_t port_id, - a_bool_t enable, a_uint32_t cnt) -{ - sw_error_t rv; - a_uint32_t reg = 0; - - HSL_DEV_ID_CHECK(dev_id); - - if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU)) - { - return SW_BAD_PARAM; - } - - HSL_REG_ENTRY_GET(rv, dev_id, PORT_LEARN_LIMIT_CTL, port_id, - (a_uint8_t *) (®), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - - if (A_TRUE == enable) - { - if (DESS_MAX_PORT_LEARN_LIMIT_CNT < cnt) - { - return SW_BAD_PARAM; - } - SW_SET_REG_BY_FIELD(PORT_LEARN_LIMIT_CTL, SA_LEARN_LIMIT_EN, 1, reg); - SW_SET_REG_BY_FIELD(PORT_LEARN_LIMIT_CTL, SA_LEARN_CNT, cnt, reg); - } - else if (A_FALSE == enable) - { - SW_SET_REG_BY_FIELD(PORT_LEARN_LIMIT_CTL, SA_LEARN_LIMIT_EN, 0, reg); - SW_SET_REG_BY_FIELD(PORT_LEARN_LIMIT_CTL, SA_LEARN_CNT, 0, reg); - } - else - { - return SW_BAD_PARAM; - } - - HSL_REG_ENTRY_SET(rv, dev_id, PORT_LEARN_LIMIT_CTL, port_id, - (a_uint8_t *) (®), sizeof (a_uint32_t)); - return rv; -} - -static sw_error_t -_dess_port_fdb_learn_limit_get(a_uint32_t dev_id, fal_port_t port_id, - a_bool_t * enable, a_uint32_t * cnt) -{ - sw_error_t rv; - a_uint32_t data, reg = 0; - - HSL_DEV_ID_CHECK(dev_id); - - if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU)) - { - return SW_BAD_PARAM; - } - - HSL_REG_ENTRY_GET(rv, dev_id, PORT_LEARN_LIMIT_CTL, port_id, - (a_uint8_t *) (®), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - - SW_GET_FIELD_BY_REG(PORT_LEARN_LIMIT_CTL, SA_LEARN_LIMIT_EN, data, reg); - if (data) - { - SW_GET_FIELD_BY_REG(PORT_LEARN_LIMIT_CTL, SA_LEARN_CNT, data, reg); - *enable = A_TRUE; - *cnt = data; - } - else - { - *enable = A_FALSE; - *cnt = 0; - } - - return SW_OK; -} - -static sw_error_t -_dess_port_fdb_learn_exceed_cmd_set(a_uint32_t dev_id, fal_port_t port_id, - fal_fwd_cmd_t cmd) -{ - sw_error_t rv; - a_uint32_t data = 0; - - HSL_DEV_ID_CHECK(dev_id); - - if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU)) - { - return SW_BAD_PARAM; - } - - if (FAL_MAC_DROP == cmd) - { - data = 1; - } - else if (FAL_MAC_RDT_TO_CPU == cmd) - { - data = 0; - } - else - { - return SW_NOT_SUPPORTED; - } - - HSL_REG_FIELD_SET(rv, dev_id, PORT_LEARN_LIMIT_CTL, port_id, - SA_LEARN_LIMIT_DROP_EN, (a_uint8_t *) (&data), - sizeof (a_uint32_t)); - return rv; -} - -static sw_error_t -_dess_port_fdb_learn_exceed_cmd_get(a_uint32_t dev_id, fal_port_t port_id, - fal_fwd_cmd_t * cmd) -{ - sw_error_t rv; - a_uint32_t data = 0; - - HSL_DEV_ID_CHECK(dev_id); - - if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU)) - { - return SW_BAD_PARAM; - } - - HSL_REG_FIELD_GET(rv, dev_id, PORT_LEARN_LIMIT_CTL, port_id, - SA_LEARN_LIMIT_DROP_EN, (a_uint8_t *) (&data), - sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - - if (data) - { - *cmd = FAL_MAC_DROP; - } - else - { - *cmd = FAL_MAC_RDT_TO_CPU; - } - - return SW_OK; -} - -static sw_error_t -_dess_fdb_learn_limit_set(a_uint32_t dev_id, a_bool_t enable, a_uint32_t cnt) -{ - sw_error_t rv; - a_uint32_t reg = 0; - - HSL_REG_ENTRY_GET(rv, dev_id, GLOBAL_LEARN_LIMIT_CTL, 0, - (a_uint8_t *) (®), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - - if (A_TRUE == enable) - { - if (DESS_MAX_LEARN_LIMIT_CNT < cnt) - { - return SW_BAD_PARAM; - } - SW_SET_REG_BY_FIELD(GLOBAL_LEARN_LIMIT_CTL, GOL_SA_LEARN_LIMIT_EN, 1, - reg); - SW_SET_REG_BY_FIELD(GLOBAL_LEARN_LIMIT_CTL, GOL_SA_LEARN_CNT, cnt, reg); - } - else if (A_FALSE == enable) - { - SW_SET_REG_BY_FIELD(GLOBAL_LEARN_LIMIT_CTL, GOL_SA_LEARN_LIMIT_EN, 0, - reg); - SW_SET_REG_BY_FIELD(GLOBAL_LEARN_LIMIT_CTL, GOL_SA_LEARN_CNT, 0, reg); - } - else - { - return SW_BAD_PARAM; - } - - HSL_REG_ENTRY_SET(rv, dev_id, GLOBAL_LEARN_LIMIT_CTL, 0, - (a_uint8_t *) (®), sizeof (a_uint32_t)); - return rv; -} - -static sw_error_t -_dess_fdb_learn_limit_get(a_uint32_t dev_id, a_bool_t * enable, - a_uint32_t * cnt) -{ - sw_error_t rv; - a_uint32_t data, reg = 0; - - HSL_REG_ENTRY_GET(rv, dev_id, GLOBAL_LEARN_LIMIT_CTL, 0, - (a_uint8_t *) (®), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - - SW_GET_FIELD_BY_REG(GLOBAL_LEARN_LIMIT_CTL, GOL_SA_LEARN_LIMIT_EN, data, - reg); - if (data) - { - SW_GET_FIELD_BY_REG(GLOBAL_LEARN_LIMIT_CTL, GOL_SA_LEARN_CNT, data, - reg); - *enable = A_TRUE; - *cnt = data; - } - else - { - *enable = A_FALSE; - *cnt = 0; - } - - return SW_OK; -} - -static sw_error_t -_dess_fdb_learn_exceed_cmd_set(a_uint32_t dev_id, fal_fwd_cmd_t cmd) -{ - sw_error_t rv; - a_uint32_t data = 0; - - HSL_DEV_ID_CHECK(dev_id); - - if (FAL_MAC_DROP == cmd) - { - data = 1; - } - else if (FAL_MAC_RDT_TO_CPU == cmd) - { - data = 0; - } - else - { - return SW_NOT_SUPPORTED; - } - - HSL_REG_FIELD_SET(rv, dev_id, GLOBAL_LEARN_LIMIT_CTL, 0, - GOL_SA_LEARN_LIMIT_DROP_EN, (a_uint8_t *) (&data), - sizeof (a_uint32_t)); - return rv; -} - -static sw_error_t -_dess_fdb_learn_exceed_cmd_get(a_uint32_t dev_id, fal_fwd_cmd_t * cmd) -{ - sw_error_t rv; - a_uint32_t data = 0; - - HSL_DEV_ID_CHECK(dev_id); - - HSL_REG_FIELD_GET(rv, dev_id, GLOBAL_LEARN_LIMIT_CTL, 0, - GOL_SA_LEARN_LIMIT_DROP_EN, (a_uint8_t *) (&data), - sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - - if (data) - { - *cmd = FAL_MAC_DROP; - } - else - { - *cmd = FAL_MAC_RDT_TO_CPU; - } - - return SW_OK; -} - -#define DESS_RESV_ADDR_NUM 32 -#define RESV_ADDR_TBL0_ADDR 0x3c000 -#define RESV_ADDR_TBL1_ADDR 0x3c004 -#define RESV_ADDR_TBL2_ADDR 0x3c008 - -static void -_dess_resv_addr_parse(const a_uint32_t reg[], fal_mac_addr_t * addr) -{ - a_uint32_t i; - - for (i = 2; i < 6; i++) - { - addr->uc[i] = (reg[0] >> ((5 - i) << 3)) & 0xff; - } - - for (i = 0; i < 2; i++) - { - addr->uc[i] = (reg[1] >> ((1 - i) << 3)) & 0xff; - } -} - -static sw_error_t -_dess_resv_atu_sw_to_hw(a_uint32_t dev_id, fal_fdb_entry_t * entry, - a_uint32_t reg[]) -{ - a_uint32_t port; - - if (A_FALSE == entry->portmap_en) - { - if (A_TRUE != - hsl_port_prop_check(dev_id, entry->port.id, HSL_PP_INCL_CPU)) - { - return SW_BAD_PARAM; - } - port = 0x1UL << entry->port.id; - } - else - { - if (A_FALSE == - hsl_mports_prop_check(dev_id, entry->port.map, HSL_PP_INCL_CPU)) - { - return SW_BAD_PARAM; - } - port = entry->port.map; - } - SW_SET_REG_BY_FIELD(RESV_ADDR_TBL1, RESV_DES_PORT, port, reg[1]); - - if (FAL_MAC_CPY_TO_CPU == entry->dacmd) - { - SW_SET_REG_BY_FIELD(RESV_ADDR_TBL1, RESV_COPY_TO_CPU, 1, reg[1]); - } - else if (FAL_MAC_RDT_TO_CPU == entry->dacmd) - { - SW_SET_REG_BY_FIELD(RESV_ADDR_TBL1, RESV_REDRCT_TO_CPU, 1, reg[1]); - } - else if (FAL_MAC_FRWRD != entry->dacmd) - { - return SW_NOT_SUPPORTED; - } - - if (FAL_MAC_FRWRD != entry->sacmd) - { - return SW_NOT_SUPPORTED; - } - - if (A_TRUE == entry->leaky_en) - { - SW_SET_REG_BY_FIELD(RESV_ADDR_TBL1, RESV_LEAKY_EN, 1, reg[1]); - } - else - { - SW_SET_REG_BY_FIELD(RESV_ADDR_TBL1, RESV_LEAKY_EN, 0, reg[1]); - } - - if (A_TRUE != entry->static_en) - { - return SW_NOT_SUPPORTED; - } - SW_SET_REG_BY_FIELD(RESV_ADDR_TBL2, RESV_STATUS, 1, reg[2]); - - if (A_TRUE == entry->mirror_en) - { - SW_SET_REG_BY_FIELD(RESV_ADDR_TBL1, RESV_MIRROR_EN, 1, reg[1]); - } - - if (A_TRUE == entry->cross_pt_state) - { - SW_SET_REG_BY_FIELD(RESV_ADDR_TBL1, RESV_CROSS_PT, 1, reg[1]); - } - - if (A_TRUE == entry->da_pri_en) - { - SW_SET_REG_BY_FIELD(RESV_ADDR_TBL1, RESV_PRI_EN, 1, reg[1]); - SW_SET_REG_BY_FIELD(RESV_ADDR_TBL1, RESV_PRI, (entry->da_queue & 0x7), - reg[1]); - } - - _dess_fdb_fill_addr(entry->addr, ®[0], ®[1]); - return SW_OK; -} - -static void -_dess_resv_atu_hw_to_sw(const a_uint32_t reg[], fal_fdb_entry_t * entry) -{ - a_uint32_t data; - - aos_mem_zero(entry, sizeof (fal_fdb_entry_t)); - - entry->fid = FAL_SVL_FID; - - entry->dacmd = FAL_MAC_FRWRD; - SW_GET_FIELD_BY_REG(RESV_ADDR_TBL1, RESV_COPY_TO_CPU, data, reg[1]); - if (1 == data) - { - entry->dacmd = FAL_MAC_CPY_TO_CPU; - } - - SW_GET_FIELD_BY_REG(RESV_ADDR_TBL1, RESV_REDRCT_TO_CPU, data, reg[1]); - if (1 == data) - { - entry->dacmd = FAL_MAC_RDT_TO_CPU; - } - - entry->sacmd = FAL_MAC_FRWRD; - - entry->leaky_en = A_FALSE; - SW_GET_FIELD_BY_REG(RESV_ADDR_TBL1, RESV_LEAKY_EN, data, reg[1]); - if (1 == data) - { - entry->leaky_en = A_TRUE; - } - - entry->static_en = A_TRUE; - - entry->mirror_en = A_FALSE; - SW_GET_FIELD_BY_REG(RESV_ADDR_TBL1, RESV_MIRROR_EN, data, reg[1]); - if (1 == data) - { - entry->mirror_en = A_TRUE; - } - - entry->da_pri_en = A_FALSE; - SW_GET_FIELD_BY_REG(RESV_ADDR_TBL1, RESV_PRI_EN, data, reg[1]); - if (1 == data) - { - SW_GET_FIELD_BY_REG(RESV_ADDR_TBL1, RESV_PRI, data, reg[1]); - entry->da_pri_en = A_TRUE; - entry->da_queue = data & 0x7; - } - - entry->cross_pt_state = A_FALSE; - SW_GET_FIELD_BY_REG(RESV_ADDR_TBL1, RESV_CROSS_PT, data, reg[1]); - if (1 == data) - { - entry->cross_pt_state = A_TRUE; - } - - SW_GET_FIELD_BY_REG(RESV_ADDR_TBL1, RESV_DES_PORT, data, reg[1]); - entry->portmap_en = A_TRUE; - entry->port.map = data; - - _dess_resv_addr_parse(reg, &(entry->addr)); - return; -} - -static sw_error_t -_dess_fdb_resv_commit(a_uint32_t dev_id, fal_fdb_entry_t * entry, a_uint32_t op, - a_uint32_t * empty) -{ - a_uint32_t index, addr, data, tbl[3] = { 0 }; - sw_error_t rv; - fal_mac_addr_t mac_tmp; - - *empty = DESS_RESV_ADDR_NUM; - for (index = 0; index < DESS_RESV_ADDR_NUM; index++) - { - addr = RESV_ADDR_TBL2_ADDR + (index << 4); - HSL_REG_ENTRY_GEN_GET(rv, dev_id, addr, sizeof (a_uint32_t), - (a_uint8_t *) (&(tbl[2])), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - - SW_GET_FIELD_BY_REG(RESV_ADDR_TBL2, RESV_STATUS, data, tbl[2]); - if (data) - { - addr = RESV_ADDR_TBL0_ADDR + (index << 4); - HSL_REG_ENTRY_GEN_GET(rv, dev_id, addr, sizeof (a_uint32_t), - (a_uint8_t *) (&(tbl[0])), - sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - - addr = RESV_ADDR_TBL1_ADDR + (index << 4); - HSL_REG_ENTRY_GEN_GET(rv, dev_id, addr, sizeof (a_uint32_t), - (a_uint8_t *) (&(tbl[1])), - sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - - _dess_resv_addr_parse(tbl, &mac_tmp); - if (!aos_mem_cmp - ((void *) &(entry->addr), (void *) &mac_tmp, - sizeof (fal_mac_addr_t))) - { - if (ARL_PURGE_ENTRY == op) - { - addr = RESV_ADDR_TBL2_ADDR + (index << 4); - tbl[2] = 0; - HSL_REG_ENTRY_GEN_SET(rv, dev_id, addr, sizeof (a_uint32_t), - (a_uint8_t *) (&(tbl[2])), - sizeof (a_uint32_t)); - return rv; - } - else if (ARL_LOAD_ENTRY == op) - { - return SW_ALREADY_EXIST; - } - else if (ARL_FIND_ENTRY == op) - { - _dess_resv_atu_hw_to_sw(tbl, entry); - return SW_OK; - } - } - } - else - { - *empty = index; - } - } - - return SW_NOT_FOUND; -} - -static sw_error_t -_dess_fdb_resv_add(a_uint32_t dev_id, fal_fdb_entry_t * entry) -{ - sw_error_t rv; - a_uint32_t i, empty, addr, tbl[3] = { 0 }; - - rv = _dess_resv_atu_sw_to_hw(dev_id, entry, tbl); - SW_RTN_ON_ERROR(rv); - - rv = _dess_fdb_resv_commit(dev_id, entry, ARL_LOAD_ENTRY, &empty); - if (SW_ALREADY_EXIST == rv) - { - return rv; - } - - if (DESS_RESV_ADDR_NUM == empty) - { - return SW_NO_RESOURCE; - } - - for (i = 0; i < 3; i++) - { - addr = RESV_ADDR_TBL0_ADDR + (empty << 4) + (i << 2); - HSL_REG_ENTRY_GEN_SET(rv, dev_id, addr, sizeof (a_uint32_t), - (a_uint8_t *) (&(tbl[i])), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - } - - return SW_OK; -} - -static sw_error_t -_dess_fdb_resv_del(a_uint32_t dev_id, fal_fdb_entry_t * entry) -{ - sw_error_t rv; - a_uint32_t empty; - - rv = _dess_fdb_resv_commit(dev_id, entry, ARL_PURGE_ENTRY, &empty); - return rv; -} - -static sw_error_t -_dess_fdb_resv_find(a_uint32_t dev_id, fal_fdb_entry_t * entry) -{ - sw_error_t rv; - a_uint32_t empty; - - rv = _dess_fdb_resv_commit(dev_id, entry, ARL_FIND_ENTRY, &empty); - return rv; -} - -static sw_error_t -_dess_fdb_resv_iterate(a_uint32_t dev_id, a_uint32_t * iterator, - fal_fdb_entry_t * entry) -{ - a_uint32_t index, addr, data, tbl[3] = { 0 }; - sw_error_t rv; - - if ((NULL == iterator) || (NULL == entry)) - { - return SW_BAD_PTR; - } - - if (DESS_RESV_ADDR_NUM < *iterator) - { - return SW_BAD_PARAM; - } - - for (index = *iterator; index < DESS_RESV_ADDR_NUM; index++) - { - addr = RESV_ADDR_TBL2_ADDR + (index << 4); - HSL_REG_ENTRY_GEN_GET(rv, dev_id, addr, sizeof (a_uint32_t), - (a_uint8_t *) (&(tbl[2])), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - - SW_GET_FIELD_BY_REG(RESV_ADDR_TBL2, RESV_STATUS, data, tbl[2]); - if (data) - { - addr = RESV_ADDR_TBL0_ADDR + (index << 4); - HSL_REG_ENTRY_GEN_GET(rv, dev_id, addr, sizeof (a_uint32_t), - (a_uint8_t *) (&(tbl[0])), - sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - - addr = RESV_ADDR_TBL1_ADDR + (index << 4); - HSL_REG_ENTRY_GEN_GET(rv, dev_id, addr, sizeof (a_uint32_t), - (a_uint8_t *) (&(tbl[1])), - sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - - _dess_resv_atu_hw_to_sw(tbl, entry); - break; - } - } - - if (DESS_RESV_ADDR_NUM == index) - { - return SW_NO_MORE; - } - - *iterator = index + 1; - return SW_OK; -} - -static sw_error_t -_dess_fdb_port_learn_static_set(a_uint32_t dev_id, fal_port_t port_id, - a_bool_t enable) -{ - a_uint32_t data; - sw_error_t rv; - - HSL_DEV_ID_CHECK(dev_id); - - if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU)) - { - return SW_BAD_PARAM; - } - - if (A_TRUE == enable) - { - data = 0xf; - } - else if (A_FALSE == enable) - { - data = 0x7; - } - else - { - return SW_BAD_PARAM; - } - - HSL_REG_FIELD_SET(rv, dev_id, PORT_LEARN_LIMIT_CTL, port_id, - SA_LEARN_STATUS, (a_uint8_t *) (&data), - sizeof (a_uint32_t)); - return rv; -} - -static sw_error_t -_dess_fdb_port_learn_static_get(a_uint32_t dev_id, fal_port_t port_id, - a_bool_t * enable) -{ - a_uint32_t data = 0; - sw_error_t rv; - - HSL_DEV_ID_CHECK(dev_id); - - if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU)) - { - return SW_BAD_PARAM; - } - - HSL_REG_FIELD_GET(rv, dev_id, PORT_LEARN_LIMIT_CTL, port_id, - SA_LEARN_STATUS, (a_uint8_t *) (&data), - sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - - if (0xf == data) - { - *enable = A_TRUE; - } - else - { - *enable = A_FALSE; - } - - return SW_OK; -} - -static sw_error_t -_dess_fdb_port_update(a_uint32_t dev_id, a_uint32_t fid, fal_mac_addr_t * addr, fal_port_t port_id, a_uint32_t op) -{ - sw_error_t rv; - fal_fdb_entry_t entry; - fal_fdb_op_t option; - a_uint32_t reg, port; - - HSL_DEV_ID_CHECK(dev_id); - - if (FAL_SVL_FID < fid) - { - return SW_BAD_PARAM; - } - - if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU)) - { - return SW_BAD_PARAM; - } - - aos_mem_zero(&option, sizeof(fal_fdb_op_t)); - aos_mem_copy(&(entry.addr), addr, sizeof(fal_mac_addr_t)); - entry.fid = fid & 0xffff; - rv = _dess_fdb_get(dev_id, &option, &entry, ARL_FIND_ENTRY); - SW_RTN_ON_ERROR(rv); - - HSL_REG_ENTRY_GET(rv, dev_id, ADDR_TABLE_FUNC1, 0, - (a_uint8_t *) (®), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - - SW_GET_FIELD_BY_REG(ADDR_TABLE_FUNC1, DES_PORT, port, reg); - if (op) - { - port |= (0x1 << port_id); - } - else - { - port &= (~(0x1 << port_id)); - } - SW_SET_REG_BY_FIELD(ADDR_TABLE_FUNC1, DES_PORT, port, reg); - HSL_REG_ENTRY_SET(rv, dev_id, ADDR_TABLE_FUNC1, 0, - (a_uint8_t *) (®), sizeof (a_uint32_t)); - - rv = _dess_fdb_commit(dev_id, ARL_LOAD_ENTRY); - return rv; -} -#define FDB_RFS_ADD 1 -#define FDB_RFS_DEL 2 -static sw_error_t -_dess_fdb_rfs_update(const fal_fdb_rfs_t *rfs, fal_fdb_entry_t *entry, char op) -{ - _dess_fdb_del_by_mac(0, entry); - if(FDB_RFS_ADD == op) { - entry->static_en = 1; - entry->load_balance_en = 1; - entry->load_balance = rfs->load_balance; - entry->port.map = 1; - entry->portmap_en = 1; - } else { - entry->static_en = 0; - entry->load_balance_en = 0; - } - return _dess_fdb_add(0, entry); -} - - -static sw_error_t -_dess_fdb_rfs_set(a_uint32_t dev_id, const fal_fdb_rfs_t *rfs) -{ - - fal_fdb_entry_t entry; - sw_error_t ret; - - memset(&entry, 0, sizeof(entry)); - - entry.addr = rfs->addr; - entry.fid = rfs->fid; - ret = _dess_fdb_find(0, &entry); - if(!ret) { - return _dess_fdb_rfs_update(rfs, &entry, FDB_RFS_ADD); - } else { - entry.addr = rfs->addr; - entry.fid = rfs->fid; - entry.load_balance_en = 1; - entry.load_balance = rfs->load_balance; - entry.static_en = 1; - entry.port.map = 1; - entry.portmap_en = 1; - return _dess_fdb_add(0, &entry); - } -} - -static sw_error_t -_dess_fdb_rfs_del(a_uint32_t dev_id, const fal_fdb_rfs_t *rfs) -{ - - fal_fdb_entry_t entry; - sw_error_t ret; - - memset(&entry, 0, sizeof(entry)); - entry.addr = rfs->addr; - entry.fid = rfs->fid; - ret = _dess_fdb_find(0, &entry); - if(!ret) { - return _dess_fdb_rfs_update(rfs, &entry, FDB_RFS_DEL); - } else { - return ret; - } -} - - - -sw_error_t -inter_dess_fdb_flush(a_uint32_t dev_id, a_uint32_t flag) -{ - if (FAL_FDB_DEL_STATIC & flag) - { - return _dess_fdb_commit(dev_id, ARL_FLUSH_ALL); - } - else - { - return _dess_fdb_commit(dev_id, ARL_FLUSH_ALL_UNLOCK); - } -} - -/** - * @brief Add a Fdb entry - * @param[in] dev_id device id - * @param[in] entry fdb entry - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -dess_fdb_add(a_uint32_t dev_id, const fal_fdb_entry_t * entry) -{ - sw_error_t rv; - - HSL_API_LOCK; - aos_lock_bh(&dess_fdb_lock); - rv = _dess_fdb_add(dev_id, entry); - aos_unlock_bh(&dess_fdb_lock); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Delete all Fdb entries - * @details Comments: - * If set FAL_FDB_DEL_STATIC bit in flag which means delete all fdb - * entries otherwise only delete dynamic entries. - * @param[in] dev_id device id - * @param[in] flag delete operation option - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -dess_fdb_del_all(a_uint32_t dev_id, a_uint32_t flag) -{ - sw_error_t rv; - - HSL_API_LOCK; - aos_lock_bh(&dess_fdb_lock); - rv = _dess_fdb_del_all(dev_id, flag); - aos_unlock_bh(&dess_fdb_lock); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Delete Fdb entries on a particular port - * @details Comments: - * If set FAL_FDB_DEL_STATIC bit in flag which means delete all fdb - * entries otherwise only delete dynamic entries. - * @param[in] dev_id device id - * @param[in] port_id port id - * @param[in] flag delete operation option - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -dess_fdb_del_by_port(a_uint32_t dev_id, fal_port_t port_id, a_uint32_t flag) -{ - sw_error_t rv; - - HSL_API_LOCK; - aos_lock_bh(&dess_fdb_lock); - rv = _dess_fdb_del_by_port(dev_id, port_id, flag); - aos_unlock_bh(&dess_fdb_lock); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Delete a particular Fdb entry through mac address - * @details Comments: - * Only addr field in entry is meaning. For IVL learning vid or fid field - * also is meaning. - * @param[in] dev_id device id - * @param[in] entry fdb entry - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -dess_fdb_del_by_mac(a_uint32_t dev_id, const fal_fdb_entry_t * entry) -{ - sw_error_t rv; - - HSL_API_LOCK; - aos_lock_bh(&dess_fdb_lock); - rv = _dess_fdb_del_by_mac(dev_id, entry); - aos_unlock_bh(&dess_fdb_lock); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Find a particular Fdb entry from device through mac address. - * @details Comments: - For input parameter only addr field in entry is meaning. - * @param[in] dev_id device id - * @param[in] entry fdb entry - * @param[out] entry fdb entry - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -dess_fdb_find(a_uint32_t dev_id, fal_fdb_entry_t * entry) -{ - sw_error_t rv; - - HSL_API_LOCK; - aos_lock_bh(&dess_fdb_lock); - rv = _dess_fdb_find(dev_id, entry); - aos_unlock_bh(&dess_fdb_lock); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Get next Fdb entry from a particular device - * @param[in] dev_id device id - * @param[in] option next operation options - * @param[out] entry fdb entry - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -dess_fdb_extend_next(a_uint32_t dev_id, fal_fdb_op_t * option, - fal_fdb_entry_t * entry) -{ - sw_error_t rv; - - HSL_API_LOCK; - aos_lock_bh(&dess_fdb_lock); - rv = _dess_fdb_extend_next(dev_id, option, entry); - aos_unlock_bh(&dess_fdb_lock); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Get first Fdb entry from a particular device - * @param[in] dev_id device id - * @param[in] option first operation options - * @param[out] entry fdb entry - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -dess_fdb_extend_first(a_uint32_t dev_id, fal_fdb_op_t * option, - fal_fdb_entry_t * entry) -{ - sw_error_t rv; - - HSL_API_LOCK; - aos_lock_bh(&dess_fdb_lock); - rv = _dess_fdb_extend_first(dev_id, option, entry); - aos_unlock_bh(&dess_fdb_lock); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Transfer fdb entries port information on a particular device. - * @param[in] dev_id device id - * @param[in] old_port source port id - * @param[in] new_port destination port id - * @param[in] fid filter database id - * @param[in] option transfer operation options - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -dess_fdb_transfer(a_uint32_t dev_id, fal_port_t old_port, fal_port_t new_port, - a_uint32_t fid, fal_fdb_op_t * option) -{ - sw_error_t rv; - - HSL_API_LOCK; - aos_lock_bh(&dess_fdb_lock); - rv = _dess_fdb_transfer(dev_id, old_port, new_port, fid, option); - aos_unlock_bh(&dess_fdb_lock); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Set dynamic address learning status on a particular port. - * @details Comments: - * This operation will enable or disable dynamic address learning - * feature on a particular port. - * @param[in] dev_id device id - * @param[in] port_id port id - * @param[in] enable enable or disable - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -dess_fdb_port_learn_set(a_uint32_t dev_id, fal_port_t port_id, a_bool_t enable) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _dess_fdb_port_learn_set(dev_id, port_id, enable); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Get dynamic address learning status on a particular port. - * @param[in] dev_id device id - * @param[in] port_id port id - * @param[out] enable A_TRUE or A_FALSE - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -dess_fdb_port_learn_get(a_uint32_t dev_id, fal_port_t port_id, - a_bool_t * enable) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _dess_fdb_port_learn_get(dev_id, port_id, enable); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Set dynamic address aging status on particular device. - * @details Comments: - * This operation will enable or disable dynamic address aging - * feature on particular device. - * @param[in] dev_id device id - * @param[in] enable enable or disable - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -dess_fdb_age_ctrl_set(a_uint32_t dev_id, a_bool_t enable) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _dess_fdb_age_ctrl_set(dev_id, enable); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Get dynamic address aging status on particular device. - * @param[in] dev_id device id - * @param[in] enable enable or disable - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -dess_fdb_age_ctrl_get(a_uint32_t dev_id, a_bool_t * enable) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _dess_fdb_age_ctrl_get(dev_id, enable); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief set arl search mode as ivl or svl when vlan invalid. - * @param[in] dev_id device id - * @param[in] smode INVALID_VLAN_IVL or INVALID_VLAN_SVL - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -dess_fdb_vlan_ivl_svl_set(a_uint32_t dev_id, fal_fdb_smode smode) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _dess_fdb_vlan_ivl_svl_set(dev_id, smode); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief get arl search mode when vlan invalid. - * @param[in] dev_id device id - * @param[out] smode INVALID_VLAN_IVL or INVALID_VLAN_SVL - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -dess_fdb_vlan_ivl_svl_get(a_uint32_t dev_id, fal_fdb_smode* smode) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _dess_fdb_vlan_ivl_svl_get(dev_id, smode); - HSL_API_UNLOCK; - return rv; -} - - - -/** - * @brief Set dynamic address aging time on a particular device. - * @details Comments: - * This operation will set dynamic address aging time on a particular device. - * The unit of time is second. Because different device has differnet - * hardware granularity function will return actual time in hardware. - * @param[in] dev_id device id - * @param time aging time - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -dess_fdb_age_time_set(a_uint32_t dev_id, a_uint32_t * time) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _dess_fdb_age_time_set(dev_id, time); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Get dynamic address aging time on a particular device. - * @param[in] dev_id device id - * @param[out] time aging time - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -dess_fdb_age_time_get(a_uint32_t dev_id, a_uint32_t * time) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _dess_fdb_age_time_get(dev_id, time); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Set dynamic address learning count limit on a particular port. - * @param[in] dev_id device id - * @param[in] port_id port id - * @param[in] enable A_TRUE or A_FALSE - * @param[in] cnt limit count - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -dess_port_fdb_learn_limit_set(a_uint32_t dev_id, fal_port_t port_id, - a_bool_t enable, a_uint32_t cnt) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _dess_port_fdb_learn_limit_set(dev_id, port_id, enable, cnt); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Get dynamic address learning count limit on a particular port. - * @param[in] dev_id device id - * @param[in] port_id port id - * @param[out] enable A_TRUE or A_FALSE - * @param[out] cnt limit count - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -dess_port_fdb_learn_limit_get(a_uint32_t dev_id, fal_port_t port_id, - a_bool_t * enable, a_uint32_t * cnt) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _dess_port_fdb_learn_limit_get(dev_id, port_id, enable, cnt); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Set dynamic address learning count exceed command on a particular port. - * @param[in] dev_id device id - * @param[in] port_id port id - * @param[in] cmd forwarding command - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -dess_port_fdb_learn_exceed_cmd_set(a_uint32_t dev_id, fal_port_t port_id, - fal_fwd_cmd_t cmd) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _dess_port_fdb_learn_exceed_cmd_set(dev_id, port_id, cmd); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Get dynamic address learning count exceed command on a particular port. - * @param[in] dev_id device id - * @param[in] port_id port id - * @param[out] cmd forwarding command - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -dess_port_fdb_learn_exceed_cmd_get(a_uint32_t dev_id, fal_port_t port_id, - fal_fwd_cmd_t * cmd) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _dess_port_fdb_learn_exceed_cmd_get(dev_id, port_id, cmd); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Set dynamic address learning count limit on a particular device. - * @param[in] dev_id device id - * @param[in] enable A_TRUE or A_FALSE - * @param[in] cnt limit count - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -dess_fdb_learn_limit_set(a_uint32_t dev_id, a_bool_t enable, a_uint32_t cnt) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _dess_fdb_learn_limit_set(dev_id, enable, cnt); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Get dynamic address learning count limit on a particular device. - * @param[in] dev_id device id - * @param[in] enable A_TRUE or A_FALSE - * @param[in] cnt limit count - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -dess_fdb_learn_limit_get(a_uint32_t dev_id, a_bool_t * enable, a_uint32_t * cnt) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _dess_fdb_learn_limit_get(dev_id, enable, cnt); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Set dynamic address learning count exceed command on a particular device. - * @param[in] dev_id device id - * @param[in] cmd forwarding command - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -dess_fdb_learn_exceed_cmd_set(a_uint32_t dev_id, fal_fwd_cmd_t cmd) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _dess_fdb_learn_exceed_cmd_set(dev_id, cmd); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Get dynamic address learning count exceed command on a particular device. - * @param[in] dev_id device id - * @param[out] cmd forwarding command - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -dess_fdb_learn_exceed_cmd_get(a_uint32_t dev_id, fal_fwd_cmd_t * cmd) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _dess_fdb_learn_exceed_cmd_get(dev_id, cmd); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Add a particular reserve Fdb entry - * @param[in] dev_id device id - * @param[in] entry reserve fdb entry - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -dess_fdb_resv_add(a_uint32_t dev_id, fal_fdb_entry_t * entry) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _dess_fdb_resv_add(dev_id, entry); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Delete a particular reserve Fdb entry through mac address - * @param[in] dev_id device id - * @param[in] entry reserve fdb entry - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -dess_fdb_resv_del(a_uint32_t dev_id, fal_fdb_entry_t * entry) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _dess_fdb_resv_del(dev_id, entry); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Find a particular reserve Fdb entry through mac address - * @param[in] dev_id device id - * @param[in] entry reserve fdb entry - * @param[out] entry reserve fdb entry - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -dess_fdb_resv_find(a_uint32_t dev_id, fal_fdb_entry_t * entry) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _dess_fdb_resv_find(dev_id, entry); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Iterate all reserve fdb entries on a particular device. - * @param[in] dev_id device id - * @param[in] iterator reserve fdb entry index if it's zero means get the first entry - * @param[out] iterator next valid fdb entry index - * @param[out] entry reserve fdb entry - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -dess_fdb_resv_iterate(a_uint32_t dev_id, a_uint32_t * iterator, - fal_fdb_entry_t * entry) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _dess_fdb_resv_iterate(dev_id, iterator, entry); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Set the static status of fdb entries which learned by hardware on a particular port. - * @param[in] dev_id device id - * @param[in] port_id port id - * @param[in] enable A_TRUE or A_FALSE - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -dess_fdb_port_learn_static_set(a_uint32_t dev_id, fal_port_t port_id, - a_bool_t enable) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _dess_fdb_port_learn_static_set(dev_id, port_id, enable); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Get the static status of fdb entries which learned by hardware on a particular port. - * @param[in] dev_id device id - * @param[in] port_id port id - * @param[out] enable A_TRUE or A_FALSE - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -dess_fdb_port_learn_static_get(a_uint32_t dev_id, fal_port_t port_id, - a_bool_t * enable) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _dess_fdb_port_learn_static_get(dev_id, port_id, enable); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Add a port to an exsiting entry - * @param[in] dev_id device id - * @param[in] fid filtering database id - * @param[in] addr MAC address - * @param[in] port_id port id - * @return SW_OK or error code, If entry not exist will return error. - */ -HSL_LOCAL sw_error_t -dess_fdb_port_add(a_uint32_t dev_id, a_uint32_t fid, fal_mac_addr_t * addr, fal_port_t port_id) -{ - sw_error_t rv; - - HSL_API_LOCK; - aos_lock_bh(&dess_fdb_lock); - rv = _dess_fdb_port_update(dev_id, fid, addr, port_id, 1); - aos_unlock_bh(&dess_fdb_lock); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Delete a port from an exsiting entry - * @param[in] dev_id device id - * @param[in] fid filtering database id - * @param[in] addr MAC address - * @param[in] port_id port id - * @return SW_OK or error code, If entry not exist will return error. - */ -HSL_LOCAL sw_error_t -dess_fdb_port_del(a_uint32_t dev_id, a_uint32_t fid, fal_mac_addr_t * addr, fal_port_t port_id) -{ - sw_error_t rv; - - HSL_API_LOCK; - aos_lock_bh(&dess_fdb_lock); - rv = _dess_fdb_port_update(dev_id, fid, addr, port_id, 0); - aos_unlock_bh(&dess_fdb_lock); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief set a fdb rfs entry - * @param[in] dev_id device id - * @param[in] rfs entry - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -dess_fdb_rfs_set(a_uint32_t dev_id, const fal_fdb_rfs_t *rfs) -{ - sw_error_t rv; - - HSL_API_LOCK; - aos_lock_bh(&dess_fdb_lock); - rv = _dess_fdb_rfs_set(dev_id, rfs); - aos_unlock_bh(&dess_fdb_lock); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief del a fdb rfs entry - * @param[in] dev_id device id - * @param[in] rfs entry - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -dess_fdb_rfs_del(a_uint32_t dev_id, const fal_fdb_rfs_t *rfs) -{ - sw_error_t rv; - - HSL_API_LOCK; - aos_lock_bh(&dess_fdb_lock); - rv = _dess_fdb_rfs_del(dev_id, rfs); - aos_unlock_bh(&dess_fdb_lock); - HSL_API_UNLOCK; - return rv; -} - - -sw_error_t -dess_fdb_init(a_uint32_t dev_id) -{ - HSL_DEV_ID_CHECK(dev_id); - -#ifndef HSL_STANDALONG - { - hsl_api_t *p_api; - - SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id)); - - p_api->fdb_add = dess_fdb_add; - p_api->fdb_del_all = dess_fdb_del_all; - p_api->fdb_del_by_port = dess_fdb_del_by_port; - p_api->fdb_del_by_mac = dess_fdb_del_by_mac; - p_api->fdb_find = dess_fdb_find; - p_api->port_learn_set = dess_fdb_port_learn_set; - p_api->port_learn_get = dess_fdb_port_learn_get; - p_api->age_ctrl_set = dess_fdb_age_ctrl_set; - p_api->age_ctrl_get = dess_fdb_age_ctrl_get; - p_api->vlan_ivl_svl_set = dess_fdb_vlan_ivl_svl_set; - p_api->vlan_ivl_svl_get = dess_fdb_vlan_ivl_svl_get; - p_api->age_time_set = dess_fdb_age_time_set; - p_api->age_time_get = dess_fdb_age_time_get; - p_api->fdb_extend_next = dess_fdb_extend_next; - p_api->fdb_extend_first = dess_fdb_extend_first; - p_api->fdb_transfer = dess_fdb_transfer; - p_api->port_fdb_learn_limit_set = dess_port_fdb_learn_limit_set; - p_api->port_fdb_learn_limit_get = dess_port_fdb_learn_limit_get; - p_api->port_fdb_learn_exceed_cmd_set = dess_port_fdb_learn_exceed_cmd_set; - p_api->port_fdb_learn_exceed_cmd_get = dess_port_fdb_learn_exceed_cmd_get; - p_api->fdb_learn_limit_set = dess_fdb_learn_limit_set; - p_api->fdb_learn_limit_get = dess_fdb_learn_limit_get; - p_api->fdb_learn_exceed_cmd_set = dess_fdb_learn_exceed_cmd_set; - p_api->fdb_learn_exceed_cmd_get = dess_fdb_learn_exceed_cmd_get; - p_api->fdb_resv_add = dess_fdb_resv_add; - p_api->fdb_resv_del = dess_fdb_resv_del; - p_api->fdb_resv_find = dess_fdb_resv_find; - p_api->fdb_resv_iterate = dess_fdb_resv_iterate; - p_api->fdb_port_learn_static_set = dess_fdb_port_learn_static_set; - p_api->fdb_port_learn_static_get = dess_fdb_port_learn_static_get; - p_api->fdb_port_add = dess_fdb_port_add; - p_api->fdb_port_del = dess_fdb_port_del; - p_api->fdb_rfs_set = dess_fdb_rfs_set; - p_api->fdb_rfs_del = dess_fdb_rfs_del; - } -#endif - - aos_lock_init(&dess_fdb_lock); - - return SW_OK; -} - -/** - * @} - */ - diff --git a/feeds/ipq807x/qca-ssdk/src/src/hsl/dess/dess_igmp.c b/feeds/ipq807x/qca-ssdk/src/src/hsl/dess/dess_igmp.c deleted file mode 100755 index 5ca8a6fed..000000000 --- a/feeds/ipq807x/qca-ssdk/src/src/hsl/dess/dess_igmp.c +++ /dev/null @@ -1,1147 +0,0 @@ -/* - * Copyright (c) 2014, 2016, The Linux Foundation. All rights reserved. - * Permission to use, copy, modify, and/or distribute this software for - * any purpose with or without fee is hereby granted, provided that the - * above copyright notice and this permission notice appear in all copies. - * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES - * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR - * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES - * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN - * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT - * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. - */ - - -/** - * @defgroup dess_igmp DESS_IGMP - * @{ - */ -#include "sw.h" -#include "hsl.h" -#include "hsl_dev.h" -#include "hsl_port_prop.h" -#include "dess_igmp.h" -#include "dess_reg.h" - -#define LEAVE_EN_OFFSET 2 -#define JOIN_EN_OFFSET 1 -#define IGMP_MLD_EN_OFFSET 0 - -#define DESS_MAX_PORT_LEARN_LIMIT_CNT 1024 - -extern sw_error_t -dess_igmp_sg_entry_set(a_uint32_t dev_id, fal_igmp_sg_entry_t * entry); - -extern sw_error_t -dess_igmp_sg_entry_clear(a_uint32_t dev_id, fal_igmp_sg_entry_t * entry); - -extern sw_error_t -dess_igmp_sg_entry_show(a_uint32_t dev_id); - -extern sw_error_t -dess_igmp_sg_entry_query(a_uint32_t dev_id, fal_igmp_sg_info_t * info); - -static sw_error_t -_dess_port_igmp_property_set(a_uint32_t dev_id, fal_port_t port_id, - a_bool_t enable, a_uint32_t item) -{ - sw_error_t rv; - a_uint32_t reg = 0, val; - - HSL_DEV_ID_CHECK(dev_id); - - if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU)) - { - return SW_BAD_PARAM; - } - - if (A_TRUE == enable) - { - val = 1; - } - else if (A_FALSE == enable) - { - val = 0; - } - else - { - return SW_BAD_PARAM; - } - - if (3 >= port_id) - { - HSL_REG_ENTRY_GET(rv, dev_id, FRAME_ACK_CTL0, 0, - (a_uint8_t *) (®), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - - reg &= ~(0x1UL << ((port_id << 3) + item)); - reg |= (val << ((port_id << 3) + item)); - - HSL_REG_ENTRY_SET(rv, dev_id, FRAME_ACK_CTL0, 0, - (a_uint8_t *) (®), sizeof (a_uint32_t)); - } - else - { - HSL_REG_ENTRY_GET(rv, dev_id, FRAME_ACK_CTL1, 0, - (a_uint8_t *) (®), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - - reg &= ~(0x1UL << (((port_id - 4) << 3) + item)); - reg |= (val << (((port_id - 4) << 3) + item)); - - HSL_REG_ENTRY_SET(rv, dev_id, FRAME_ACK_CTL1, 0, - (a_uint8_t *) (®), sizeof (a_uint32_t)); - } - return rv; -} - -static sw_error_t -_dess_port_igmp_property_get(a_uint32_t dev_id, fal_port_t port_id, - a_bool_t * enable, a_uint32_t item) -{ - sw_error_t rv; - a_uint32_t reg = 0, val; - - HSL_DEV_ID_CHECK(dev_id); - - if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU)) - { - return SW_BAD_PARAM; - } - - if (3 >= port_id) - { - HSL_REG_ENTRY_GET(rv, dev_id, FRAME_ACK_CTL0, 0, - (a_uint8_t *) (®), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - - val = (reg >> ((port_id << 3) + item)) & 0x1UL; - } - else - { - HSL_REG_ENTRY_GET(rv, dev_id, FRAME_ACK_CTL1, 0, - (a_uint8_t *) (®), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - - val = (reg >> (((port_id - 4) << 3) + item)) & 0x1UL; - } - - if (1 == val) - { - *enable = A_TRUE; - } - else - { - *enable = A_FALSE; - } - - return SW_OK; -} - -static sw_error_t -_dess_igmp_mld_cmd_set(a_uint32_t dev_id, fal_fwd_cmd_t cmd) -{ - sw_error_t rv; - a_uint32_t val; - - HSL_DEV_ID_CHECK(dev_id); - - if (FAL_MAC_CPY_TO_CPU == cmd) - { - val = 1; - } - else if (FAL_MAC_RDT_TO_CPU == cmd) - { - val = 0; - } - else - { - return SW_NOT_SUPPORTED; - } - - HSL_REG_FIELD_SET(rv, dev_id, FORWARD_CTL0, 0, IGMP_COPY_EN, - (a_uint8_t *) (&val), sizeof (a_uint32_t)); - return rv; -} - -static sw_error_t -_dess_igmp_mld_cmd_get(a_uint32_t dev_id, fal_fwd_cmd_t * cmd) -{ - sw_error_t rv; - a_uint32_t val = 0; - - HSL_DEV_ID_CHECK(dev_id); - - HSL_REG_FIELD_GET(rv, dev_id, FORWARD_CTL0, 0, IGMP_COPY_EN, - (a_uint8_t *) (&val), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - - if (1 == val) - { - *cmd = FAL_MAC_CPY_TO_CPU; - } - else - { - *cmd = FAL_MAC_RDT_TO_CPU; - } - - return SW_OK; -} - -static sw_error_t -_dess_igmp_mld_rp_set(a_uint32_t dev_id, fal_pbmp_t pts) -{ - sw_error_t rv; - a_uint32_t val; - - HSL_DEV_ID_CHECK(dev_id); - - if (A_FALSE == hsl_mports_validity_check(dev_id, pts)) - { - return SW_BAD_PARAM; - } - val = pts; - HSL_REG_FIELD_SET(rv, dev_id, FORWARD_CTL1, 0, IGMP_DP, - (a_uint8_t *) (&val), sizeof (a_uint32_t)); - return rv; -} - -static sw_error_t -_dess_igmp_mld_rp_get(a_uint32_t dev_id, fal_pbmp_t * pts) -{ - sw_error_t rv; - a_uint32_t val = 0; - - HSL_DEV_ID_CHECK(dev_id); - - HSL_REG_FIELD_GET(rv, dev_id, FORWARD_CTL1, 0, IGMP_DP, - (a_uint8_t *) (&val), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - - *pts = val; - return SW_OK; -} - -static sw_error_t -_dess_igmp_mld_entry_creat_set(a_uint32_t dev_id, a_bool_t enable) -{ - sw_error_t rv; - a_uint32_t val; - - HSL_DEV_ID_CHECK(dev_id); - - if (A_TRUE == enable) - { - val = 1; - } - else if (A_FALSE == enable) - { - val = 0; - } - else - { - return SW_BAD_PARAM; - } - - HSL_REG_FIELD_SET(rv, dev_id, ADDR_TABLE_CTL, 0, IGMP_CREAT_EN, - (a_uint8_t *) (&val), sizeof (a_uint32_t)); - return rv; -} - -static sw_error_t -_dess_igmp_mld_entry_creat_get(a_uint32_t dev_id, a_bool_t * enable) -{ - sw_error_t rv; - a_uint32_t val = 0; - - HSL_DEV_ID_CHECK(dev_id); - - HSL_REG_FIELD_GET(rv, dev_id, ADDR_TABLE_CTL, 0, IGMP_CREAT_EN, - (a_uint8_t *) (&val), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - - if (val) - { - *enable = A_TRUE; - } - else - { - *enable = A_FALSE; - } - - return SW_OK; -} - -static sw_error_t -_dess_igmp_mld_entry_static_set(a_uint32_t dev_id, a_bool_t enable) -{ - sw_error_t rv; - a_uint32_t val; - - HSL_DEV_ID_CHECK(dev_id); - - if (A_TRUE == enable) - { - val = 0xf; - } - else if (A_FALSE == enable) - { - val = 0xe; - } - else - { - return SW_BAD_PARAM; - } - - HSL_REG_FIELD_SET(rv, dev_id, ADDR_TABLE_CTL, 0, IGMP_JOIN_STATIC, - (a_uint8_t *) (&val), sizeof (a_uint32_t)); - return rv; -} - -static sw_error_t -_dess_igmp_mld_entry_static_get(a_uint32_t dev_id, a_bool_t * enable) -{ - sw_error_t rv; - a_uint32_t val = 0; - - HSL_DEV_ID_CHECK(dev_id); - - HSL_REG_FIELD_GET(rv, dev_id, ADDR_TABLE_CTL, 0, IGMP_JOIN_STATIC, - (a_uint8_t *) (&val), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - - if (0xf == val) - { - *enable = A_TRUE; - } - else - { - *enable = A_FALSE; - } - - return SW_OK; -} - -static sw_error_t -_dess_igmp_mld_entry_leaky_set(a_uint32_t dev_id, a_bool_t enable) -{ - sw_error_t rv; - a_uint32_t val; - - HSL_DEV_ID_CHECK(dev_id); - - if (A_TRUE == enable) - { - val = 1; - } - else if (A_FALSE == enable) - { - val = 0; - } - else - { - return SW_BAD_PARAM; - } - - HSL_REG_FIELD_SET(rv, dev_id, ADDR_TABLE_CTL, 0, IGMP_JOIN_LEAKY, - (a_uint8_t *) (&val), sizeof (a_uint32_t)); - return rv; -} - -static sw_error_t -_dess_igmp_mld_entry_leaky_get(a_uint32_t dev_id, a_bool_t * enable) -{ - sw_error_t rv; - a_uint32_t val = 0; - - HSL_DEV_ID_CHECK(dev_id); - - HSL_REG_FIELD_GET(rv, dev_id, ADDR_TABLE_CTL, 0, IGMP_JOIN_LEAKY, - (a_uint8_t *) (&val), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - - if (val) - { - *enable = A_TRUE; - } - else - { - *enable = A_FALSE; - } - - return SW_OK; -} - -static sw_error_t -_dess_igmp_mld_entry_v3_set(a_uint32_t dev_id, a_bool_t enable) -{ - sw_error_t rv; - a_uint32_t val; - - HSL_DEV_ID_CHECK(dev_id); - - if (A_TRUE == enable) - { - val = 1; - } - else if (A_FALSE == enable) - { - val = 0; - } - else - { - return SW_BAD_PARAM; - } - - HSL_REG_FIELD_SET(rv, dev_id, FRAME_ACK_CTL1, 0, IGMP_V3_EN, - (a_uint8_t *) (&val), sizeof (a_uint32_t)); - return rv; -} - -static sw_error_t -_dess_igmp_mld_entry_v3_get(a_uint32_t dev_id, a_bool_t * enable) -{ - sw_error_t rv; - a_uint32_t val = 0; - - HSL_DEV_ID_CHECK(dev_id); - - HSL_REG_FIELD_GET(rv, dev_id, FRAME_ACK_CTL1, 0, IGMP_V3_EN, - (a_uint8_t *) (&val), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - - if (val) - { - *enable = A_TRUE; - } - else - { - *enable = A_FALSE; - } - - return SW_OK; -} - -static sw_error_t -_dess_igmp_mld_entry_queue_set(a_uint32_t dev_id, a_bool_t enable, - a_uint32_t queue) -{ - sw_error_t rv; - a_uint32_t entry = 0; - - HSL_DEV_ID_CHECK(dev_id); - - HSL_REG_ENTRY_GET(rv, dev_id, ADDR_TABLE_CTL, 0, - (a_uint8_t *) (&entry), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - - if (A_TRUE == enable) - { - SW_SET_REG_BY_FIELD(ADDR_TABLE_CTL, IGMP_PRI_EN, 1, entry); - SW_SET_REG_BY_FIELD(ADDR_TABLE_CTL, IGMP_PRI, queue, entry); - } - else if (A_FALSE == enable) - { - SW_SET_REG_BY_FIELD(ADDR_TABLE_CTL, IGMP_PRI_EN, 0, entry); - SW_SET_REG_BY_FIELD(ADDR_TABLE_CTL, IGMP_PRI, 0, entry); - } - else - { - return SW_BAD_PARAM; - } - - HSL_REG_ENTRY_SET(rv, dev_id, ADDR_TABLE_CTL, 0, - (a_uint8_t *) (&entry), sizeof (a_uint32_t)); - return rv; -} - -static sw_error_t -_dess_igmp_mld_entry_queue_get(a_uint32_t dev_id, a_bool_t * enable, - a_uint32_t * queue) -{ - sw_error_t rv; - a_uint32_t entry = 0, data; - - HSL_DEV_ID_CHECK(dev_id); - - HSL_REG_ENTRY_GET(rv, dev_id, ADDR_TABLE_CTL, 0, - (a_uint8_t *) (&entry), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - - SW_GET_FIELD_BY_REG(ADDR_TABLE_CTL, IGMP_PRI_EN, data, entry); - if (data) - { - *enable = A_TRUE; - SW_GET_FIELD_BY_REG(ADDR_TABLE_CTL, IGMP_PRI, data, entry); - *queue = data; - } - else - { - *enable = A_FALSE; - *queue = 0; - } - - return SW_OK; -} - -static sw_error_t -_dess_port_igmp_mld_learn_limit_set(a_uint32_t dev_id, fal_port_t port_id, - a_bool_t enable, a_uint32_t cnt) -{ - sw_error_t rv; - a_uint32_t reg = 0; - - HSL_DEV_ID_CHECK(dev_id); - - if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU)) - { - return SW_BAD_PARAM; - } - - HSL_REG_ENTRY_GET(rv, dev_id, PORT_LEARN_LIMIT_CTL, port_id, - (a_uint8_t *) (®), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - - if (A_TRUE == enable) - { - if (DESS_MAX_PORT_LEARN_LIMIT_CNT < cnt) - { - return SW_BAD_PARAM; - } - SW_SET_REG_BY_FIELD(PORT_LEARN_LIMIT_CTL, IGMP_JOIN_LIMIT_EN, 1, reg); - SW_SET_REG_BY_FIELD(PORT_LEARN_LIMIT_CTL, IGMP_JOIN_CNT, cnt, reg); - } - else if (A_FALSE == enable) - { - SW_SET_REG_BY_FIELD(PORT_LEARN_LIMIT_CTL, IGMP_JOIN_LIMIT_EN, 0, reg); - SW_SET_REG_BY_FIELD(PORT_LEARN_LIMIT_CTL, IGMP_JOIN_CNT, 0, reg); - } - else - { - return SW_BAD_PARAM; - } - - HSL_REG_ENTRY_SET(rv, dev_id, PORT_LEARN_LIMIT_CTL, port_id, - (a_uint8_t *) (®), sizeof (a_uint32_t)); - return rv; -} - -static sw_error_t -_dess_port_igmp_mld_learn_limit_get(a_uint32_t dev_id, fal_port_t port_id, - a_bool_t * enable, a_uint32_t * cnt) -{ - sw_error_t rv; - a_uint32_t data, reg = 0; - - HSL_DEV_ID_CHECK(dev_id); - - if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU)) - { - return SW_BAD_PARAM; - } - - HSL_REG_ENTRY_GET(rv, dev_id, PORT_LEARN_LIMIT_CTL, port_id, - (a_uint8_t *) (®), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - - SW_GET_FIELD_BY_REG(PORT_LEARN_LIMIT_CTL, IGMP_JOIN_LIMIT_EN, data, reg); - if (data) - { - SW_GET_FIELD_BY_REG(PORT_LEARN_LIMIT_CTL, IGMP_JOIN_CNT, data, reg); - *enable = A_TRUE; - *cnt = data; - } - else - { - *enable = A_FALSE; - *cnt = data; - } - - return SW_OK; -} - -static sw_error_t -_dess_port_igmp_mld_learn_exceed_cmd_set(a_uint32_t dev_id, fal_port_t port_id, - fal_fwd_cmd_t cmd) -{ - sw_error_t rv; - a_uint32_t data = 0; - - HSL_DEV_ID_CHECK(dev_id); - - if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU)) - { - return SW_BAD_PARAM; - } - - if (FAL_MAC_DROP == cmd) - { - data = 1; - } - else if (FAL_MAC_RDT_TO_CPU == cmd) - { - data = 0; - } - else - { - return SW_NOT_SUPPORTED; - } - - HSL_REG_FIELD_SET(rv, dev_id, PORT_LEARN_LIMIT_CTL, port_id, - IGMP_JOIN_LIMIT_DROP_EN, (a_uint8_t *) (&data), - sizeof (a_uint32_t)); - return rv; -} - -static sw_error_t -_dess_port_igmp_mld_learn_exceed_cmd_get(a_uint32_t dev_id, fal_port_t port_id, - fal_fwd_cmd_t * cmd) -{ - sw_error_t rv; - a_uint32_t data = 0; - - HSL_DEV_ID_CHECK(dev_id); - - if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU)) - { - return SW_BAD_PARAM; - } - - HSL_REG_FIELD_GET(rv, dev_id, PORT_LEARN_LIMIT_CTL, port_id, - IGMP_JOIN_LIMIT_DROP_EN, (a_uint8_t *) (&data), - sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - - if (data) - { - *cmd = FAL_MAC_DROP; - } - else - { - *cmd = FAL_MAC_RDT_TO_CPU; - } - - return SW_OK; -} - -/** - * @brief Set igmp/mld packets snooping status on a particular port. - * @details Comments: - * After enabling igmp/mld snooping feature on a particular port all kinds - * igmp/mld packets received on this port would be acknowledged by hardware. - * Particular forwarding decision could be setted by fal_igmp_mld_cmd_set. - * @param[in] dev_id device id - * @param[in] port_id port id - * @param[in] enable A_TRUE or A_FALSE - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -dess_port_igmps_status_set(a_uint32_t dev_id, fal_port_t port_id, - a_bool_t enable) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _dess_port_igmp_property_set(dev_id, port_id, enable, - IGMP_MLD_EN_OFFSET); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Get igmp/mld packets snooping status on particular port. - * @param[in] dev_id device id - * @param[in] port_id port id - * @param[out] enable A_TRUE or A_FALSE - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -dess_port_igmps_status_get(a_uint32_t dev_id, fal_port_t port_id, - a_bool_t * enable) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _dess_port_igmp_property_get(dev_id, port_id, enable, - IGMP_MLD_EN_OFFSET); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Set igmp/mld packets forwarding command on a particular device. - * @details Comments: - * Particular device may only support parts of forwarding commands. - * This operation will take effect only after enabling igmp/mld snooping - * @param[in] dev_id device id - * @param[in] cmd forwarding command - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -dess_igmp_mld_cmd_set(a_uint32_t dev_id, fal_fwd_cmd_t cmd) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _dess_igmp_mld_cmd_set(dev_id, cmd); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Get igmp/mld packets forwarding command on a particular device. - * @param[in] dev_id device id - * @param[out] cmd forwarding command - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -dess_igmp_mld_cmd_get(a_uint32_t dev_id, fal_fwd_cmd_t * cmd) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _dess_igmp_mld_cmd_get(dev_id, cmd); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Set igmp/mld join packets hardware acknowledgement status on particular port. - * @details Comments: - * After enabling igmp/mld join feature on a particular port hardware will - * dynamic learning or changing multicast entry. - * @param[in] dev_id device id - * @param[in] port_id port id - * @param[in] enable A_TRUE or A_FALSE - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -dess_port_igmp_mld_join_set(a_uint32_t dev_id, fal_port_t port_id, - a_bool_t enable) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _dess_port_igmp_property_set(dev_id, port_id, enable, JOIN_EN_OFFSET); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Get igmp/mld join packets hardware acknowledgement status on a particular port. - * @param[in] dev_id device id - * @param[in] port_id port id - * @param[out] enable A_TRUE or A_FALSE - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -dess_port_igmp_mld_join_get(a_uint32_t dev_id, fal_port_t port_id, - a_bool_t * enable) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _dess_port_igmp_property_get(dev_id, port_id, enable, JOIN_EN_OFFSET); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Set igmp/mld leave packets hardware acknowledgement status on a particular port. - * @details Comments: - * After enabling igmp leave feature on a particular port hardware will dynamic - * deleting or changing multicast entry. - * @param[in] dev_id device id - * @param[in] port_id port id - * @param[in] enable A_TRUE or A_FALSE - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -dess_port_igmp_mld_leave_set(a_uint32_t dev_id, fal_port_t port_id, - a_bool_t enable) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _dess_port_igmp_property_set(dev_id, port_id, enable, LEAVE_EN_OFFSET); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Get igmp/mld leave packets hardware acknowledgement status on a particular port. - * @param[in] dev_id device id - * @param[in] port_id port id - * @param[out] enable A_TRUE or A_FALSE - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -dess_port_igmp_mld_leave_get(a_uint32_t dev_id, fal_port_t port_id, - a_bool_t * enable) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _dess_port_igmp_property_get(dev_id, port_id, enable, LEAVE_EN_OFFSET); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Set igmp/mld router ports on a particular device. - * @details Comments: - * After enabling igmp/mld join/leave feature on a particular port igmp/mld - * join/leave packets received on this port will be forwarded to router ports. - * @param[in] dev_id device id - * @param[in] pts dedicates ports - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -dess_igmp_mld_rp_set(a_uint32_t dev_id, fal_pbmp_t pts) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _dess_igmp_mld_rp_set(dev_id, pts); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Get igmp/mld router ports on a particular device. - * @param[in] dev_id device id - * @param[out] pts dedicates ports - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -dess_igmp_mld_rp_get(a_uint32_t dev_id, fal_pbmp_t * pts) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _dess_igmp_mld_rp_get(dev_id, pts); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Set the status of creating multicast entry during igmp/mld join/leave procedure. - * @details Comments: - * After enabling igmp/mld join/leave feature on a particular port if enable - * entry creat hardware will dynamic creat and delete multicast entry, - * otherwise hardware only can change destination ports of existing muticast entry. - * @param[in] dev_id device id - * @param[in] enable A_TRUE or A_FALSE - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -dess_igmp_mld_entry_creat_set(a_uint32_t dev_id, a_bool_t enable) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _dess_igmp_mld_entry_creat_set(dev_id, enable); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Get the status of creating multicast entry during igmp/mld join/leave procedure. - * @param[in] dev_id device id - * @param[out] enable A_TRUE or A_FALSE - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -dess_igmp_mld_entry_creat_get(a_uint32_t dev_id, a_bool_t * enable) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _dess_igmp_mld_entry_creat_get(dev_id, enable); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Set the static status of multicast entry which learned by hardware. - * @details Comments: - * After enabling igmp/mld join/leave feature on a particular port if enable - * static status hardware will not age out multicast entry which leardned by hardware, - * otherwise hardware will age out multicast entry which leardned by hardware. - * @param[in] dev_id device id - * @param[in] enable A_TRUE or A_FALSE - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -dess_igmp_mld_entry_static_set(a_uint32_t dev_id, a_bool_t enable) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _dess_igmp_mld_entry_static_set(dev_id, enable); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Get the static status of multicast entry which learned by hardware. - * @param[in] dev_id device id - * @param[out] enable A_TRUE or A_FALSE - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -dess_igmp_mld_entry_static_get(a_uint32_t dev_id, a_bool_t * enable) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _dess_igmp_mld_entry_static_get(dev_id, enable); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Set the leaky status of multicast entry which learned by hardware. - * @details Comments: - * After enabling igmp/mld join/leave feature on a particular port if enable - * leaky status hardware will set leaky flag of multicast entry which leardned by hardware, - * otherwise hardware will not set leaky flag of multicast entry which leardned by hardware. - * @param[in] dev_id device id - * @param[in] enable A_TRUE or A_FALSE - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -dess_igmp_mld_entry_leaky_set(a_uint32_t dev_id, a_bool_t enable) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _dess_igmp_mld_entry_leaky_set(dev_id, enable); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Get the leaky status of multicast entry which learned by hardware. - * @param[in] dev_id device id - * @param[out] enable A_TRUE or A_FALSE - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -dess_igmp_mld_entry_leaky_get(a_uint32_t dev_id, a_bool_t * enable) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _dess_igmp_mld_entry_leaky_get(dev_id, enable); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Set igmpv3/mldv2 packets hardware acknowledgement status on a particular device. - * @details Comments: - * After enabling igmp join/leave feature on a particular port hardware will dynamic - * creating or changing multicast entry after receiving igmpv3/mldv2 packets. - * @param[in] dev_id device id - * @param[in] enable A_TRUE or A_FALSE - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -dess_igmp_mld_entry_v3_set(a_uint32_t dev_id, a_bool_t enable) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _dess_igmp_mld_entry_v3_set(dev_id, enable); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Get igmpv3/mldv2 packets hardware acknowledgement status on a particular device. - * @param[in] dev_id device id - * @param[out] enable A_TRUE or A_FALSE - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -dess_igmp_mld_entry_v3_get(a_uint32_t dev_id, a_bool_t * enable) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _dess_igmp_mld_entry_v3_get(dev_id, enable); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Set the queue status of multicast entry which learned by hardware. - * @details Comments: - * After enabling igmp/mld join/leave feature on a particular port if enable - * leaky status hardware will set queue flag of multicast entry which leardned by hardware, - * otherwise hardware will not set queue flag of multicast entry which leardned by hardware. - * @param[in] dev_id device id - * @param[in] enable A_TRUE or A_FALSE - * @param[in] queue queue id - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -dess_igmp_mld_entry_queue_set(a_uint32_t dev_id, a_bool_t enable, - a_uint32_t queue) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _dess_igmp_mld_entry_queue_set(dev_id, enable, queue); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Get the queue status of multicast entry which learned by hardware. - * @param[in] dev_id device id - * @param[out] enable A_TRUE or A_FALSE - * @param[out] queue queue id - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -dess_igmp_mld_entry_queue_get(a_uint32_t dev_id, a_bool_t * enable, - a_uint32_t * queue) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _dess_igmp_mld_entry_queue_get(dev_id, enable, queue); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Set IGMP hardware learning count limit on a particular port. - * @param[in] dev_id device id - * @param[in] port_id port id - * @param[in] enable A_TRUE or A_FALSE - * @param[in] cnt limit count - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -dess_port_igmp_mld_learn_limit_set(a_uint32_t dev_id, fal_port_t port_id, - a_bool_t enable, a_uint32_t cnt) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _dess_port_igmp_mld_learn_limit_set(dev_id, port_id, enable, cnt); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Get IGMP hardware learning count limit on a particular port. - * @param[in] dev_id device id - * @param[in] port_id port id - * @param[out] enable A_TRUE or A_FALSE - * @param[out] cnt limit count - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -dess_port_igmp_mld_learn_limit_get(a_uint32_t dev_id, fal_port_t port_id, - a_bool_t * enable, a_uint32_t * cnt) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _dess_port_igmp_mld_learn_limit_get(dev_id, port_id, enable, cnt); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Set IGMP hardware learning count exceed command on a particular port. - * @param[in] dev_id device id - * @param[in] port_id port id - * @param[in] cmd forwarding command - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -dess_port_igmp_mld_learn_exceed_cmd_set(a_uint32_t dev_id, fal_port_t port_id, - fal_fwd_cmd_t cmd) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _dess_port_igmp_mld_learn_exceed_cmd_set(dev_id, port_id, cmd); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Get IGMP hardware learning count exceed command on a particular port. - * @param[in] dev_id device id - * @param[in] port_id port id - * @param[out] cmd forwarding command - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -dess_port_igmp_mld_learn_exceed_cmd_get(a_uint32_t dev_id, fal_port_t port_id, - fal_fwd_cmd_t * cmd) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _dess_port_igmp_mld_learn_exceed_cmd_get(dev_id, port_id, cmd); - HSL_API_UNLOCK; - return rv; -} - -sw_error_t -dess_igmp_init(a_uint32_t dev_id) -{ - HSL_DEV_ID_CHECK(dev_id); - -#ifndef HSL_STANDALONG - { - hsl_api_t *p_api; - - SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id)); - - p_api->port_igmps_status_set = dess_port_igmps_status_set; - p_api->port_igmps_status_get = dess_port_igmps_status_get; - p_api->igmp_mld_cmd_set = dess_igmp_mld_cmd_set; - p_api->igmp_mld_cmd_get = dess_igmp_mld_cmd_get; - p_api->port_igmp_join_set = dess_port_igmp_mld_join_set; - p_api->port_igmp_join_get = dess_port_igmp_mld_join_get; - p_api->port_igmp_leave_set = dess_port_igmp_mld_leave_set; - p_api->port_igmp_leave_get = dess_port_igmp_mld_leave_get; - p_api->igmp_rp_set = dess_igmp_mld_rp_set; - p_api->igmp_rp_get = dess_igmp_mld_rp_get; - p_api->igmp_entry_creat_set = dess_igmp_mld_entry_creat_set; - p_api->igmp_entry_creat_get = dess_igmp_mld_entry_creat_get; - p_api->igmp_entry_static_set = dess_igmp_mld_entry_static_set; - p_api->igmp_entry_static_get = dess_igmp_mld_entry_static_get; - p_api->igmp_entry_leaky_set = dess_igmp_mld_entry_leaky_set; - p_api->igmp_entry_leaky_get = dess_igmp_mld_entry_leaky_get; - p_api->igmp_entry_v3_set = dess_igmp_mld_entry_v3_set; - p_api->igmp_entry_v3_get = dess_igmp_mld_entry_v3_get; - p_api->igmp_entry_queue_set = dess_igmp_mld_entry_queue_set; - p_api->igmp_entry_queue_get = dess_igmp_mld_entry_queue_get; - p_api->port_igmp_mld_learn_limit_set = dess_port_igmp_mld_learn_limit_set; - p_api->port_igmp_mld_learn_limit_get = dess_port_igmp_mld_learn_limit_get; - p_api->port_igmp_mld_learn_exceed_cmd_set = dess_port_igmp_mld_learn_exceed_cmd_set; - p_api->port_igmp_mld_learn_exceed_cmd_get = dess_port_igmp_mld_learn_exceed_cmd_get; - p_api->igmp_sg_entry_set = dess_igmp_sg_entry_set; - p_api->igmp_sg_entry_clear = dess_igmp_sg_entry_clear; - p_api->igmp_sg_entry_show = dess_igmp_sg_entry_show; - p_api->igmp_sg_entry_query = dess_igmp_sg_entry_query; - } -#endif - - return SW_OK; -} - -/** - * @} - */ - diff --git a/feeds/ipq807x/qca-ssdk/src/src/hsl/dess/dess_init.c b/feeds/ipq807x/qca-ssdk/src/src/hsl/dess/dess_init.c deleted file mode 100644 index 53eae17bb..000000000 --- a/feeds/ipq807x/qca-ssdk/src/src/hsl/dess/dess_init.c +++ /dev/null @@ -1,343 +0,0 @@ -/* - * Copyright (c) 2014-2017, The Linux Foundation. All rights reserved. - * Permission to use, copy, modify, and/or distribute this software for - * any purpose with or without fee is hereby granted, provided that the - * above copyright notice and this permission notice appear in all copies. - * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES - * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR - * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES - * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN - * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT - * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. - */ - - -/** - * @defgroup dess_init DESS_INIT - * @{ - */ -#include "sw.h" -#include "hsl.h" -#include "hsl_dev.h" -#include "hsl_port_prop.h" -#include "dess_mib.h" -#include "dess_port_ctrl.h" -#include "dess_portvlan.h" -#include "dess_vlan.h" -#include "dess_fdb.h" -#include "dess_qos.h" -#include "dess_mirror.h" -#include "dess_stp.h" -#include "dess_rate.h" -#include "dess_misc.h" -#include "dess_leaky.h" -#include "dess_igmp.h" -#include "dess_acl.h" -#include "dess_led.h" -#include "dess_cosmap.h" -#include "dess_ip.h" -#include "dess_nat.h" -#if defined(IN_NAT_HELPER) -#include "dess_nat_helper.h" -#endif -#include "dess_sec.h" -#include "dess_trunk.h" -#include "dess_interface_ctrl.h" -#include "dess_reg_access.h" -#include "dess_reg.h" -#include "dess_init.h" -#include - - -static ssdk_init_cfg * dess_cfg[SW_MAX_NR_DEV] = { 0 }; -a_uint32_t dess_nat_global_status = 0; - -#if !(defined(KERNEL_MODULE) && defined(USER_MODE)) -/* For isis there are five internal PHY devices and seven MAC devices. - PORT0 always connect to external DMA device. - MAC1..MAC4 connect to internal PHY0..PHY3. -*/ - - -a_uint32_t dess_pbmp_5[PORT_WRAPPER_MAX] = { - ((1<<1) | (1<<2) | (1<<3) | (1<<4) | (1<<5)), /*PORT_WRAPPER_PSGMII*/ - ((1<<1) | (1<<2) | (1<<3) | (1<<4) | (1<<5)), /*PORT_WRAPPER_PSGMII_RGMII5*/ - ((1<<1) | (1<<5)), /*PORT_WRAPPER_SGMII0_RGMII5*/ - ((1<<2) | (1<<5)), /*PORT_WRAPPER_SGMII1_RGMII5*/ - ((1<<1) | (1<<2) | (1<<3) | (1<<4) | (1<<5)), /*PORT_WRAPPER_PSGMII_RMII0*/ - ((1<<1) | (1<<2) | (1<<3) | (1<<4) | (1<<5)), /*PORT_WRAPPER_PSGMII_RMII1*/ - ((1<<1) | (1<<2) | (1<<3) | (1<<4) | (1<<5)), /*PORT_WRAPPER_PSGMII_RMII0_RMII1*/ - ((1<<1) | (1<<2) | (1<<3) | (1<<4) | (1<<5)), /*PORT_WRAPPER_SGMII_RGMII4*/ - ((1<<1) | (1<<4)), /*PORT_WRAPPER_SGMII0_RGMII4*/ - ((1<<2) | (1<<4)), /*PORT_WRAPPER_SGMII1_RGMII4*/ - ((1<<5) | (1<<4)), /*PORT_WRAPPER_SGMII4_RGMII4*/ - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - ((1<<1) | (1<<2) | (1<<3) | (1<<4) | (1<<5)), /*PORT_WRAPPER_PSGMII_FIBER*/ - }; - -a_uint32_t dess_pbmp_2[PORT_WRAPPER_MAX] = { - ((1<<4) | (1<<5)), /*PORT_WRAPPER_PSGMII*/ - 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, - ((1<<4) | (1<<5)), /*PORT_WRAPPER_PSGMII_FIBER*/ - }; - -a_uint32_t dess_get_port_phy_id(void) -{ - return dess_cfg[0]->phy_id; -} - -enum ssdk_port_wrapper_cfg dess_get_port_config(void) -{ - return dess_cfg[0]->mac_mode; -} - -a_bool_t dess_mac_port_valid_check(fal_port_t port_id) -{ - a_uint32_t bitmap = 0; - enum ssdk_port_wrapper_cfg cfg; - a_uint32_t phy_id; - - cfg = dess_get_port_config(); - phy_id = dess_get_port_phy_id(); - - if (phy_id == MALIBU_1_1_2PORT) - bitmap = dess_pbmp_2[cfg]; - else { - bitmap = dess_pbmp_5[cfg]; - } - return SW_IS_PBMP_MEMBER(bitmap, port_id); - -} - -static sw_error_t -dess_portproperty_init(a_uint32_t dev_id) -{ - hsl_port_prop_t p_type; - hsl_dev_t *pdev = NULL; - fal_port_t port_id; - enum ssdk_port_wrapper_cfg cfg; - a_uint32_t bitmap = 0; - - pdev = hsl_dev_ptr_get(dev_id); - if (pdev == NULL) - return SW_NOT_INITIALIZED; - - cfg = dess_get_port_config(); - bitmap = dess_pbmp_5[cfg]; - - /* for port property set, SSDK should not generate some limitations */ - for (port_id = 0; port_id < SW_MAX_NR_PORT; port_id++) - { - if((!SW_IS_PBMP_MEMBER(bitmap, port_id)) && (port_id != pdev->cpu_port_nr)) - continue; - - hsl_port_prop_portmap_set(dev_id, port_id); - - for (p_type = HSL_PP_PHY; p_type < HSL_PP_BUTT; p_type++) - { - - switch (p_type) - { - case HSL_PP_PHY: - /* Only port0 without PHY device */ - if (port_id != pdev->cpu_port_nr) - { - if(SW_IS_PBMP_MEMBER(bitmap, port_id)) - SW_RTN_ON_ERROR(hsl_port_prop_set(dev_id, port_id, p_type)); - } - break; - - case HSL_PP_INCL_CPU: - /* include cpu port but exclude wan port in some cases */ - /* but which port is wan port, we are no meaning */ - if (port_id == pdev->cpu_port_nr) - SW_RTN_ON_ERROR(hsl_port_prop_set(dev_id, port_id, p_type)); - if(SW_IS_PBMP_MEMBER(bitmap, port_id)) - SW_RTN_ON_ERROR(hsl_port_prop_set(dev_id, port_id, p_type)); - break; - - case HSL_PP_EXCL_CPU: - /* exclude cpu port and wan port in some cases */ - /* which port is wan port, we are no meaning but port0 is - always CPU port */ - if (port_id != pdev->cpu_port_nr) - { - if(SW_IS_PBMP_MEMBER(bitmap, port_id)) - SW_RTN_ON_ERROR(hsl_port_prop_set(dev_id, port_id, p_type)); - } - break; - - default: - break; - } - } - - if (port_id != pdev->cpu_port_nr) - { - SW_RTN_ON_ERROR(hsl_port_prop_set_phyid - (dev_id, port_id, port_id - 1)); - } - } - - return SW_OK; -} -#endif - -static sw_error_t -dess_dev_init(a_uint32_t dev_id, ssdk_init_cfg *cfg) -{ - a_uint32_t entry = 0; - sw_error_t rv; - hsl_dev_t *pdev = NULL; - - pdev = hsl_dev_ptr_get(dev_id); - if (pdev == NULL) - return SW_NOT_INITIALIZED; - - HSL_REG_FIELD_GET(rv, dev_id, MASK_CTL, 0, DEVICE_ID, - (a_uint8_t *) (&entry), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - - if (DESS_DEVICE_ID == entry) - { - a_uint32_t i = 0, port_nr = 0, tmp = 0; - tmp = cfg->port_cfg.lan_bmp | cfg->port_cfg.wan_bmp; - for(i = 0; i < SW_MAX_NR_PORT; i++) { - if(tmp & (1 << i)) { - port_nr++; - } - } - pdev->nr_phy = port_nr; - for(i = 0; i < SW_MAX_NR_PORT; i++) { - if(cfg->port_cfg.cpu_bmp & (1 << i)) { - port_nr++; - pdev->cpu_port_nr = i; - break; - } - } - if(i >= SW_MAX_NR_PORT) - return SW_BAD_VALUE; - pdev->nr_ports = port_nr; - pdev->nr_vlans = 4096; - pdev->hw_vlan_query = A_TRUE; - pdev->nr_queue = port_nr; - pdev->cpu_mode = cfg->cpu_mode; - pdev->wan_bmp = cfg->port_cfg.wan_bmp; - } - - return SW_OK; -} - -sw_error_t -dess_cleanup(a_uint32_t dev_id) -{ - sw_error_t rv; - - if (dess_cfg[dev_id]) - { -#if defined(IN_NAT_HELPER) - if(dess_nat_global_status) - DESS_NAT_HELPER_CLEANUP(rv, dev_id); -#endif - - DESS_ACL_CLEANUP(rv, dev_id); - - SW_RTN_ON_ERROR(hsl_port_prop_cleanup_by_dev(dev_id)); - - aos_mem_free(dess_cfg[dev_id]); - dess_cfg[dev_id] = NULL; - } - - return SW_OK; -} - -/** - * @brief Init hsl layer. - * @details Comments: - * This operation will init hsl layer and hsl layer - * @param[in] dev_id device id - * @param[in] cfg configuration for initialization - * @return SW_OK or error code - */ -sw_error_t -dess_init(a_uint32_t dev_id, ssdk_init_cfg *cfg) -{ - HSL_DEV_ID_CHECK(dev_id); - - if (NULL == dess_cfg[dev_id]) - { - dess_cfg[dev_id] = aos_mem_alloc(sizeof (ssdk_init_cfg)); - } - - if (NULL == dess_cfg[dev_id]) - { - return SW_OUT_OF_MEM; - } - - aos_mem_copy(dess_cfg[dev_id], cfg, sizeof (ssdk_init_cfg)); - - SW_RTN_ON_ERROR(dess_reg_access_init(dev_id, cfg->reg_mode)); - - SW_RTN_ON_ERROR(dess_dev_init(dev_id, cfg)); - -#if !(defined(KERNEL_MODULE) && defined(USER_MODE)) - { - sw_error_t rv; - - SW_RTN_ON_ERROR(hsl_port_prop_init(dev_id)); - SW_RTN_ON_ERROR(hsl_port_prop_init_by_dev(dev_id)); - SW_RTN_ON_ERROR(dess_portproperty_init(dev_id)); - - DESS_MIB_INIT(rv, dev_id); - DESS_PORT_CTRL_INIT(rv, dev_id); - DESS_PORTVLAN_INIT(rv, dev_id); - DESS_VLAN_INIT(rv, dev_id); - DESS_FDB_INIT(rv, dev_id); - DESS_QOS_INIT(rv, dev_id); - DESS_STP_INIT(rv, dev_id); - DESS_MIRR_INIT(rv, dev_id); - DESS_RATE_INIT(rv, dev_id); - DESS_MISC_INIT(rv, dev_id); - DESS_LEAKY_INIT(rv, dev_id); - DESS_IGMP_INIT(rv, dev_id); - DESS_ACL_INIT(rv, dev_id); - DESS_LED_INIT(rv, dev_id); - DESS_COSMAP_INIT(rv, dev_id); - DESS_IP_INIT(rv, dev_id); - DESS_NAT_INIT(rv, dev_id); - DESS_TRUNK_INIT(rv, dev_id); - DESS_SEC_INIT(rv, dev_id); - DESS_INTERFACE_CTRL_INIT(rv, dev_id); - - { - hsl_api_t *p_api; - - SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id)); - p_api->dev_clean = dess_cleanup; - } -#if 0 -#if defined(IN_NAT_HELPER) - if(!dess_nat_global_status) { - DESS_NAT_HELPER_INIT(rv, dev_id); - dess_nat_global_status = 1; - } -#endif -#endif - } -#endif - - return SW_OK; -} - -/** - * @} - */ - diff --git a/feeds/ipq807x/qca-ssdk/src/src/hsl/dess/dess_interface_ctrl.c b/feeds/ipq807x/qca-ssdk/src/src/hsl/dess/dess_interface_ctrl.c deleted file mode 100755 index f6396f943..000000000 --- a/feeds/ipq807x/qca-ssdk/src/src/hsl/dess/dess_interface_ctrl.c +++ /dev/null @@ -1,299 +0,0 @@ -/* - * Copyright (c) 2014, 2016, The Linux Foundation. All rights reserved. - * Permission to use, copy, modify, and/or distribute this software for - * any purpose with or without fee is hereby granted, provided that the - * above copyright notice and this permission notice appear in all copies. - * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES - * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR - * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES - * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN - * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT - * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. - */ - - -/** - * @defgroup dess_interface_ctrl DESS_INTERFACE_CONTROL - * @{ - */ -#include "sw.h" -#include "hsl.h" -#include "hsl_dev.h" -#include "hsl_port_prop.h" -#include "dess_interface_ctrl.h" -#include "dess_reg.h" - - -#define DESS_PHY_MODE_PHY_ID 4 -#define DESS_LPI_PORT1_OFFSET 4 -#define DESS_LPI_BIT_STEP 2 -#define DESS_LPI_ENABLE 3 - -#define DESS_MAC4 4 -#define DESS_MAC5 5 - -static sw_error_t -_dess_port_3az_status_set(a_uint32_t dev_id, fal_port_t port_id, a_bool_t enable) -{ - sw_error_t rv = SW_OK; - a_uint32_t reg = 0, field, offset, device_id; - - HSL_REG_ENTRY_GET(rv, dev_id, MASK_CTL, 0, - (a_uint8_t *) (®), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - - SW_GET_FIELD_BY_REG(MASK_CTL, DEVICE_ID, device_id, reg); - if (DESS_DEVICE_ID != device_id) - { - return SW_NOT_SUPPORTED; - } - - if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_PHY)) - { - return SW_BAD_PARAM; - } - - HSL_REG_ENTRY_GET(rv, dev_id, EEE_CTL, 0, - (a_uint8_t *) (®), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - - if (A_TRUE == enable) - { - field = DESS_LPI_ENABLE; - } - else if (A_FALSE == enable) - { - field = 0; - } - else - { - return SW_BAD_PARAM; - } - - offset = (port_id - 1) * DESS_LPI_BIT_STEP + DESS_LPI_PORT1_OFFSET; - reg &= (~(DESS_LPI_ENABLE << offset)); - reg |= (field << offset); - - HSL_REG_ENTRY_SET(rv, dev_id, EEE_CTL, 0, - (a_uint8_t *) (®), sizeof (a_uint32_t)); - return rv; -} - -static sw_error_t -_dess_port_3az_status_get(a_uint32_t dev_id, fal_port_t port_id, a_bool_t * enable) -{ - sw_error_t rv = SW_OK; - a_uint32_t reg = 0, field, offset, device_id; - - HSL_REG_ENTRY_GET(rv, dev_id, MASK_CTL, 0, - (a_uint8_t *) (®), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - - SW_GET_FIELD_BY_REG(MASK_CTL, DEVICE_ID, device_id, reg); - if (DESS_DEVICE_ID != device_id) - { - return SW_NOT_SUPPORTED; - } - - if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_PHY)) - { - return SW_BAD_PARAM; - } - - HSL_REG_ENTRY_GET(rv, dev_id, EEE_CTL, 0, - (a_uint8_t *) (®), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - - offset = (port_id - 1) * DESS_LPI_BIT_STEP + DESS_LPI_PORT1_OFFSET; - field = (reg >> offset) & 0x3; - - if (field == DESS_LPI_ENABLE) - { - *enable = A_TRUE; - } - else - { - *enable = A_FALSE; - } - - return SW_OK; -} - -static sw_error_t -_dess_interface_mac_mode_set(a_uint32_t dev_id, fal_port_t port_id, fal_mac_config_t * config) -{ - sw_error_t rv = SW_OK; - a_uint32_t reg = 0, field; - - HSL_DEV_ID_CHECK(dev_id); - - - if (FAL_MAC_MODE_RMII == config->mac_mode) - { - HSL_REG_ENTRY_GET(rv, dev_id, RGMII_CTRL, 0, - (a_uint8_t *) (®), sizeof (a_uint32_t)); - if (port_id == DESS_MAC4) { - SW_GET_FIELD_BY_REG(RGMII_CTRL, RMII1_MASTER_EN, field, reg); - if(field == config->config.rmii.master_mode) - return rv; - SW_SET_REG_BY_FIELD(RGMII_CTRL, RMII1_MASTER_EN, config->config.rmii.master_mode, reg); - } - else if (port_id == DESS_MAC5) { - SW_GET_FIELD_BY_REG(RGMII_CTRL, RMII0_MASTER_EN, field, reg); - if(field == config->config.rmii.master_mode) - return rv; - SW_SET_REG_BY_FIELD(RGMII_CTRL, RMII1_MASTER_EN, config->config.rmii.master_mode, reg); - } - else - { - return SW_BAD_PARAM; - } - HSL_REG_ENTRY_SET(rv, dev_id, RGMII_CTRL, 0, - (a_uint8_t *) (®), sizeof (a_uint32_t)); - } - else - { - return SW_BAD_PARAM; - } - - return rv; -} - -static sw_error_t -_dess_interface_mac_mode_get(a_uint32_t dev_id, fal_port_t port_id, fal_mac_config_t * config) -{ - sw_error_t rv = SW_OK; - a_uint32_t reg = 0, field; - - HSL_DEV_ID_CHECK(dev_id); - - - if (FAL_MAC_MODE_RMII == config->mac_mode) - { - HSL_REG_ENTRY_GET(rv, dev_id, RGMII_CTRL, 0, - (a_uint8_t *) (®), sizeof (a_uint32_t)); - if (port_id == DESS_MAC4) { - SW_GET_FIELD_BY_REG(RGMII_CTRL, RMII1_MASTER_EN, field, reg); - config->config.rmii.master_mode = field; - } - else if (port_id == DESS_MAC5) { - SW_GET_FIELD_BY_REG(RGMII_CTRL, RMII0_MASTER_EN, field, reg); - config->config.rmii.master_mode = field; - } - else - { - return SW_BAD_PARAM; - } - } - else - { - return SW_BAD_PARAM; - } - - return rv; -} - - -/** - * @brief Set 802.3az status on a particular port. - * @param[in] dev_id device id - * @param[in] port_id port id - * @param[in] enable A_TRUE or A_FALSE - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -dess_port_3az_status_set(a_uint32_t dev_id, fal_port_t port_id, a_bool_t enable) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _dess_port_3az_status_set(dev_id, port_id, enable); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Get 802.3az status on a particular port. - * @param[in] dev_id device id - * @param[in] port_id port id - * @param[out] enable A_TRUE or A_FALSE - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -dess_port_3az_status_get(a_uint32_t dev_id, fal_port_t port_id, a_bool_t * enable) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _dess_port_3az_status_get(dev_id, port_id, enable); - HSL_API_UNLOCK; - return rv; -} - - -/** - * @brief Set interface mode on RGMII/RMII. - * @param[in] dev_id device id - * @param[in] delay - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -dess_interface_mac_mode_set(a_uint32_t dev_id, fal_port_t port_id, fal_mac_config_t * config) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _dess_interface_mac_mode_set(dev_id, port_id, config); - HSL_API_UNLOCK; - return rv; -} - - -/** - * @brief Get interface mode on RGMII/RMII. - * @param[in] dev_id device id - * @param[in] mca_id MAC device ID - * @param[out] config interface configuration - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -dess_interface_mac_mode_get(a_uint32_t dev_id, fal_port_t port_id, fal_mac_config_t * config) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _dess_interface_mac_mode_get(dev_id, port_id, config); - HSL_API_UNLOCK; - return rv; -} - - - - -sw_error_t -dess_interface_ctrl_init(a_uint32_t dev_id) -{ - HSL_DEV_ID_CHECK(dev_id); - -#ifndef HSL_STANDALONG - { - hsl_api_t *p_api; - - SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id)); - - p_api->port_3az_status_set = dess_port_3az_status_set; - p_api->port_3az_status_get = dess_port_3az_status_get; - p_api->interface_mac_mode_set = dess_interface_mac_mode_set; - p_api->interface_mac_mode_get = dess_interface_mac_mode_get; - - } -#endif - - return SW_OK; -} - -/** - * @} - */ - diff --git a/feeds/ipq807x/qca-ssdk/src/src/hsl/dess/dess_ip.c b/feeds/ipq807x/qca-ssdk/src/src/hsl/dess/dess_ip.c deleted file mode 100755 index 5e636a311..000000000 --- a/feeds/ipq807x/qca-ssdk/src/src/hsl/dess/dess_ip.c +++ /dev/null @@ -1,3668 +0,0 @@ -/* - * Copyright (c) 2014-2016, The Linux Foundation. All rights reserved. - * Permission to use, copy, modify, and/or distribute this software for - * any purpose with or without fee is hereby granted, provided that the - * above copyright notice and this permission notice appear in all copies. - * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES - * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR - * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES - * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN - * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT - * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. - */ - - -/** - * @defgroup dess_ip DESS_IP - * @{ - */ - -#include "sw.h" -#include "hsl.h" -#include "hsl_dev.h" -#include "hsl_port_prop.h" -#include "dess_ip.h" -#include "dess_reg.h" - -#define DESS_HOST_ENTRY_DATA0_ADDR 0x0e80 -#define DESS_HOST_ENTRY_DATA1_ADDR 0x0e84 -#define DESS_HOST_ENTRY_DATA2_ADDR 0x0e88 -#define DESS_HOST_ENTRY_DATA3_ADDR 0x0e8c -#define DESS_HOST_ENTRY_DATA4_ADDR 0x0e90 -#define DESS_HOST_ENTRY_DATA5_ADDR 0x0e94 -#define DESS_HOST_ENTRY_DATA6_ADDR 0x0e98 -#define DESS_HOST_ENTRY_DATA7_ADDR 0x0e58 - -#define DESS_HOST_ENTRY_REG_NUM 8 - -#define DESS_HOST_ENTRY_FLUSH 1 -#define DESS_HOST_ENTRY_ADD 2 -#define DESS_HOST_ENTRY_DEL 3 -#define DESS_HOST_ENTRY_NEXT 4 -#define DESS_HOST_ENTRY_SEARCH 5 - -#define DESS_ENTRY_ARP 3 - -#define DESS_INTF_MAC_ADDR_NUM 8 -#define DESS_INTF_MAC_TBL0_ADDR 0x5a900 -#define DESS_INTF_MAC_TBL1_ADDR 0x5a904 -#define DESS_INTF_MAC_TBL2_ADDR 0x5a908 -#define DESS_INTF_MAC_EDIT0_ADDR 0x02000 -#define DESS_INTF_MAC_EDIT1_ADDR 0x02004 -#define DESS_INTF_MAC_EDIT2_ADDR 0x02008 - -#define DESS_IP6_BASE_ADDR 0x0470 - -#define DESS_HOST_ENTRY_NUM 128 - -#define DESS_IP_COUTER_ADDR 0x2b000 - -#define DESS_DEFAULT_ROUTE_NUM 8 -#define DESS_IP4_DEFAULT_ROUTE_TBL_ADDR 0x004c4 -#define DESS_IP6_DEFAULT_ROUTE_TBL_ADDR 0x004e4 -#define DESS_HOST_ROUTE_NUM 16 -#define DESS_IP4_HOST_ROUTE_TBL0_ADDR 0x5b000 -#define DESS_IP4_HOST_ROUTE_TBL1_ADDR 0x5b004 -#define DESS_IP6_HOST_ROUTE_TBL0_ADDR 0x5b100 -#define DESS_IP6_HOST_ROUTE_TBL1_ADDR 0x5b104 -#define DESS_IP6_HOST_ROUTE_TBL2_ADDR 0x5b108 -#define DESS_IP6_HOST_ROUTE_TBL3_ADDR 0x5b10c -#define DESS_IP6_HOST_ROUTE_TBL4_ADDR 0x5b110 - - -static a_uint32_t dess_mac_snap[SW_MAX_NR_DEV] = { 0 }; -static fal_intf_mac_entry_t dess_intf_snap[SW_MAX_NR_DEV][DESS_INTF_MAC_ADDR_NUM]; - -extern aos_lock_t dess_nat_lock; - - -static void -_dess_ip_pt_learn_save(a_uint32_t dev_id, a_uint32_t * status) -{ - sw_error_t rv; - a_uint32_t data = 0; - - HSL_REG_ENTRY_GET(rv, dev_id, ROUTER_PTCTRL2, 0, - (a_uint8_t *) (&data), sizeof (a_uint32_t)); - if (SW_OK != rv) - { - return; - } - - *status = (data & 0x7f7f); - - data &= 0xffff8080; - HSL_REG_ENTRY_SET(rv, dev_id, ROUTER_PTCTRL2, 0, - (a_uint8_t *) (&data), sizeof (a_uint32_t)); - return; -} - -static void -_dess_ip_pt_learn_restore(a_uint32_t dev_id, a_uint32_t status) -{ - sw_error_t rv; - a_uint32_t data = 0; - - HSL_REG_ENTRY_GET(rv, dev_id, ROUTER_PTCTRL2, 0, - (a_uint8_t *) (&data), sizeof (a_uint32_t)); - if (SW_OK != rv) - { - return; - } - - data &= 0xffff8080; - data |= (status & 0x7f7f); - - HSL_REG_ENTRY_SET(rv, dev_id, ROUTER_PTCTRL2, 0, - (a_uint8_t *) (&data), sizeof (a_uint32_t)); - return; -} - -static sw_error_t -_dess_ip_feature_check(a_uint32_t dev_id) -{ - sw_error_t rv; - a_uint32_t entry = 0; - - HSL_REG_FIELD_GET(rv, dev_id, MASK_CTL, 0, DEVICE_ID, - (a_uint8_t *) (&entry), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - - if (DESS_DEVICE_ID == entry) - { - return SW_OK; - } - else - { - return SW_NOT_SUPPORTED; - } -} - -static sw_error_t -_dess_ip_counter_get(a_uint32_t dev_id, a_uint32_t cnt_id, - a_uint32_t counter[2]) -{ - sw_error_t rv; - a_uint32_t i, addr; - - addr = DESS_IP_COUTER_ADDR + (cnt_id << 3); - for (i = 0; i < 2; i++) - { - HSL_REG_ENTRY_GEN_GET(rv, dev_id, addr, sizeof (a_uint32_t), - (a_uint8_t *) (&(counter[i])), - sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - - addr += 4; - } - - return SW_OK; -} - -static sw_error_t -_dess_host_entry_commit(a_uint32_t dev_id, a_uint32_t entry_type, a_uint32_t op) -{ - a_uint32_t busy = 1, i = 0x9000000, entry = 0, j, try_num; - a_uint32_t learn_status = 0, data = 0; - sw_error_t rv; - - while (busy && --i) - { - HSL_REG_ENTRY_GET(rv, dev_id, HOST_ENTRY7, 0, (a_uint8_t *) (&entry), - sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - //printk("IP first entry is 0x%x\r\n", entry); - SW_GET_FIELD_BY_REG(HOST_ENTRY7, TBL_BUSY, busy, entry); - } - - if (i == 0) - { - printk("host entry busy!\n"); - return SW_BUSY; - } - - - /* hardware requirements, we should disable ARP learn at first */ - /* and maybe we should try several times... */ - _dess_ip_pt_learn_save(dev_id, &learn_status); - - //printk("data0=0x%x\n", data); - if(learn_status) { - aos_mdelay(800); - HSL_REG_ENTRY_GET(rv, dev_id, ROUTER_PTCTRL2, 0, - (a_uint8_t *) (&data), sizeof (a_uint32_t)); - } - //printk("data1=0x%x\n", data); - - - SW_SET_REG_BY_FIELD(HOST_ENTRY7, TBL_BUSY, 1, entry); - SW_SET_REG_BY_FIELD(HOST_ENTRY7, TBL_SEL, entry_type, entry); - SW_SET_REG_BY_FIELD(HOST_ENTRY7, ENTRY_FUNC, op, entry); - - HSL_REG_ENTRY_SET(rv, dev_id, HOST_ENTRY7, 0, (a_uint8_t *) (&entry), - sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - - if (learn_status) - { - try_num = 300; - } - else - { - try_num = 1; - } - - for (j = 0; j < try_num; j++) - { - busy = 1; - i = 0x9000000; - while (busy && --i) - { - HSL_REG_ENTRY_GET(rv, dev_id, HOST_ENTRY7, 0, (a_uint8_t *) (&entry), - sizeof (a_uint32_t)); - //printk("IP second entry is 0x%x\r\n", entry); - if (SW_OK != rv) - { - _dess_ip_pt_learn_restore(dev_id, learn_status); - return rv; - } - SW_GET_FIELD_BY_REG(HOST_ENTRY7, TBL_BUSY, busy, entry); - } - - if (i == 0) - { - _dess_ip_pt_learn_restore(dev_id, learn_status); - return SW_BUSY; - } - - /* hardware requirement, we should read again... */ - HSL_REG_ENTRY_GET(rv, dev_id, HOST_ENTRY7, 0, (a_uint8_t *) (&entry), - sizeof (a_uint32_t)); - if (SW_OK != rv) - { - _dess_ip_pt_learn_restore(dev_id, learn_status); - return rv; - } - - /* operation success...... */ - SW_GET_FIELD_BY_REG(HOST_ENTRY7, TBL_STAUS, busy, entry); - if (busy) - { - _dess_ip_pt_learn_restore(dev_id, learn_status); - return SW_OK; - } - } - - _dess_ip_pt_learn_restore(dev_id, learn_status); - if (DESS_HOST_ENTRY_NEXT == op) - { - return SW_NO_MORE; - } - else if (DESS_HOST_ENTRY_SEARCH == op) - { - return SW_NOT_FOUND; - } - else if (DESS_HOST_ENTRY_DEL == op) - { - return SW_NOT_FOUND; - } - else - { - return SW_FAIL; - } -} - -static sw_error_t -_dess_ip_intf_sw_to_hw(a_uint32_t dev_id, fal_host_entry_t * entry, - a_uint32_t * hw_intf) -{ - sw_error_t rv; - a_uint32_t addr, lvid, hvid, tbl[3] = {0}, i; - a_uint32_t sw_intf = entry->intf_id; - a_uint32_t vid_offset; - - for (i = 0; i < DESS_INTF_MAC_ADDR_NUM; i++) - { - if (dess_mac_snap[dev_id] & (0x1 << i)) - { - addr = DESS_INTF_MAC_TBL0_ADDR + (i << 4) + 4; - HSL_REG_ENTRY_GEN_GET(rv, dev_id, addr, sizeof (a_uint32_t), - (a_uint8_t *) (&(tbl[1])), - sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - - addr = DESS_INTF_MAC_TBL0_ADDR + (i << 4) + 8; - HSL_REG_ENTRY_GEN_GET(rv, dev_id, addr, sizeof (a_uint32_t), - (a_uint8_t *) (&(tbl[2])), - sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - - SW_GET_FIELD_BY_REG(INTF_ADDR_ENTRY1, VID_HIGH0, hvid, tbl[1]); - SW_GET_FIELD_BY_REG(INTF_ADDR_ENTRY2, VID_HIGH1, lvid, tbl[2]); - hvid |= ((lvid & 0xff) << 4); - - SW_GET_FIELD_BY_REG(INTF_ADDR_ENTRY1, VID_LOW, lvid, tbl[1]); - - if ((lvid <= sw_intf) && (hvid >= sw_intf)) - { - vid_offset = entry->expect_vid ? (entry->expect_vid - lvid) : (sw_intf - lvid); - *hw_intf = (vid_offset << 3) | i; - return SW_OK; - } - } - } - - return SW_BAD_PARAM; -} - -static sw_error_t -_dess_ip_intf_hw_to_sw(a_uint32_t dev_id, a_uint32_t hw_intf, - a_uint32_t * sw_intf) -{ - sw_error_t rv; - a_uint32_t addr, lvid, tbl = 0, i; - - i = hw_intf & 0x7; - - addr = DESS_INTF_MAC_TBL0_ADDR + (i << 4) + 4; - HSL_REG_ENTRY_GEN_GET(rv, dev_id, addr, sizeof (a_uint32_t), - (a_uint8_t *) (&tbl), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - - SW_GET_FIELD_BY_REG(INTF_ADDR_ENTRY1, VID_LOW, lvid, tbl); - *sw_intf = lvid + (hw_intf >> 3); - - return SW_OK; -} - -static sw_error_t -_dess_ip_age_time_set(a_uint32_t dev_id, a_uint32_t * time) -{ - sw_error_t rv; - a_uint32_t data; - - if (255 < ((*time + 5) / 6)) - { - return SW_BAD_PARAM; - } - - data = ((*time + 5) / 6); - *time = data * 6; - - HSL_REG_FIELD_SET(rv, dev_id, ROUTER_CTRL, 0, ARP_AGE_TIME, - (a_uint8_t *) (&data), sizeof (a_uint32_t)); - return rv; -} - -static sw_error_t -_dess_ip_age_time_get(a_uint32_t dev_id, a_uint32_t * time) -{ - sw_error_t rv; - a_uint32_t data = 0; - - HSL_REG_FIELD_GET(rv, dev_id, ROUTER_CTRL, 0, ARP_AGE_TIME, - (a_uint8_t *) (&data), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - - *time = data * 6; - return SW_OK; -} - -static sw_error_t -_dess_host_sw_to_hw(a_uint32_t dev_id, fal_host_entry_t * entry, - a_uint32_t reg[]) -{ - sw_error_t rv; - a_uint32_t data; - - if (FAL_IP_IP4_ADDR & entry->flags) - { - reg[0] = entry->ip4_addr; - SW_SET_REG_BY_FIELD(HOST_ENTRY6, IP_VER, 0, reg[6]); - } - - if (FAL_IP_IP6_ADDR & entry->flags) - { - reg[0] = entry->ip6_addr.ul[3]; - reg[1] = entry->ip6_addr.ul[2]; - reg[2] = entry->ip6_addr.ul[1]; - reg[3] = entry->ip6_addr.ul[0]; - SW_SET_REG_BY_FIELD(HOST_ENTRY6, IP_VER, 1, reg[6]); - } - - SW_SET_REG_BY_FIELD(HOST_ENTRY4, MAC_ADDR2, entry->mac_addr.uc[2], reg[4]); - SW_SET_REG_BY_FIELD(HOST_ENTRY4, MAC_ADDR3, entry->mac_addr.uc[3], reg[4]); - SW_SET_REG_BY_FIELD(HOST_ENTRY4, MAC_ADDR4, entry->mac_addr.uc[4], reg[4]); - SW_SET_REG_BY_FIELD(HOST_ENTRY4, MAC_ADDR5, entry->mac_addr.uc[5], reg[4]); - SW_SET_REG_BY_FIELD(HOST_ENTRY5, MAC_ADDR0, entry->mac_addr.uc[0], reg[5]); - SW_SET_REG_BY_FIELD(HOST_ENTRY5, MAC_ADDR1, entry->mac_addr.uc[1], reg[5]); - - rv = _dess_ip_intf_sw_to_hw(dev_id, entry/*was:->intf_id*/, &data); - - SW_RTN_ON_ERROR(rv); - SW_SET_REG_BY_FIELD(HOST_ENTRY5, INTF_ID, data, reg[5]); - -#if 0 - if (A_TRUE != hsl_port_prop_check(dev_id, entry->port_id, HSL_PP_INCL_CPU)) - { - return SW_BAD_PARAM; - } -#endif - - SW_SET_REG_BY_FIELD(HOST_ENTRY5, SRC_PORT, entry->port_id, reg[5]); - - if (FAL_IP_CPU_ADDR & entry->flags) - { - SW_SET_REG_BY_FIELD(HOST_ENTRY5, CPU_ADDR, 1, reg[5]); - } - - SW_SET_REG_BY_FIELD(HOST_ENTRY6, AGE_FLAG, entry->status, reg[6]); - SW_SET_REG_BY_FIELD(HOST_ENTRY6, VRF_ID, entry->vrf_id, reg[6]); - SW_SET_REG_BY_FIELD(HOST_ENTRY6, LB_BIT, entry->lb_num, reg[6]); - - if ((A_TRUE == entry->mirror_en) && (FAL_MAC_FRWRD != entry->action)) - { - return SW_NOT_SUPPORTED; - } - - if (A_TRUE == entry->counter_en) - { - SW_SET_REG_BY_FIELD(HOST_ENTRY6, CNT_EN, 1, reg[6]); - SW_SET_REG_BY_FIELD(HOST_ENTRY6, CNT_IDX, entry->counter_id, reg[6]); - } - - if (FAL_MAC_DROP == entry->action) - { - SW_SET_REG_BY_FIELD(HOST_ENTRY5, SRC_PORT, 7, reg[5]); - SW_SET_REG_BY_FIELD(HOST_ENTRY6, ACTION, 3, reg[6]); - } - else if (FAL_MAC_RDT_TO_CPU == entry->action) - { - SW_SET_REG_BY_FIELD(HOST_ENTRY6, ACTION, 1, reg[6]); - } - else if (FAL_MAC_CPY_TO_CPU == entry->action) - { - SW_SET_REG_BY_FIELD(HOST_ENTRY6, ACTION, 2, reg[6]); - } - else - { - if (A_TRUE == entry->mirror_en) - { - SW_SET_REG_BY_FIELD(HOST_ENTRY6, ACTION, 0, reg[6]); - } - else - { - SW_SET_REG_BY_FIELD(HOST_ENTRY6, ACTION, 3, reg[6]); - } - } - - return SW_OK; -} - -static sw_error_t -_dess_host_hw_to_sw(a_uint32_t dev_id, a_uint32_t reg[], - fal_host_entry_t * entry) -{ - sw_error_t rv; - a_uint32_t data = 0, cnt[2] = {0}; - - SW_GET_FIELD_BY_REG(HOST_ENTRY6, IP_VER, data, reg[6]); - if (data) - { - entry->ip6_addr.ul[0] = reg[3]; - entry->ip6_addr.ul[1] = reg[2]; - entry->ip6_addr.ul[2] = reg[1]; - entry->ip6_addr.ul[3] = reg[0]; - entry->flags |= FAL_IP_IP6_ADDR; - } - else - { - entry->ip4_addr = reg[0]; - entry->flags |= FAL_IP_IP4_ADDR; - } - - SW_GET_FIELD_BY_REG(HOST_ENTRY4, MAC_ADDR2, entry->mac_addr.uc[2], reg[4]); - SW_GET_FIELD_BY_REG(HOST_ENTRY4, MAC_ADDR3, entry->mac_addr.uc[3], reg[4]); - SW_GET_FIELD_BY_REG(HOST_ENTRY4, MAC_ADDR4, entry->mac_addr.uc[4], reg[4]); - SW_GET_FIELD_BY_REG(HOST_ENTRY4, MAC_ADDR5, entry->mac_addr.uc[5], reg[4]); - SW_GET_FIELD_BY_REG(HOST_ENTRY5, MAC_ADDR0, entry->mac_addr.uc[0], reg[5]); - SW_GET_FIELD_BY_REG(HOST_ENTRY5, MAC_ADDR1, entry->mac_addr.uc[1], reg[5]); - - SW_GET_FIELD_BY_REG(HOST_ENTRY5, INTF_ID, data, reg[5]); - rv = _dess_ip_intf_hw_to_sw(dev_id, data, &(entry->intf_id)); - SW_RTN_ON_ERROR(rv); - - SW_GET_FIELD_BY_REG(HOST_ENTRY5, SRC_PORT, entry->port_id, reg[5]); - - SW_GET_FIELD_BY_REG(HOST_ENTRY5, CPU_ADDR, data, reg[5]); - if (data) - { - entry->flags |= FAL_IP_CPU_ADDR; - } - - SW_GET_FIELD_BY_REG(HOST_ENTRY6, AGE_FLAG, entry->status, reg[6]); - SW_GET_FIELD_BY_REG(HOST_ENTRY6, VRF_ID, entry->vrf_id, reg[6]); - SW_GET_FIELD_BY_REG(HOST_ENTRY6, LB_BIT, entry->lb_num, reg[6]); - - SW_GET_FIELD_BY_REG(HOST_ENTRY6, CNT_EN, data, reg[6]); - if (data) - { - entry->counter_en = A_TRUE; - SW_GET_FIELD_BY_REG(HOST_ENTRY6, CNT_IDX, entry->counter_id, reg[6]); - - rv = _dess_ip_counter_get(dev_id, entry->counter_id, cnt); - SW_RTN_ON_ERROR(rv); - - entry->packet = cnt[0]; - entry->byte = cnt[1]; - } - else - { - entry->counter_en = A_FALSE; - } - - SW_GET_FIELD_BY_REG(HOST_ENTRY6, PPPOE_EN, data, reg[6]); - if (data) - { - entry->pppoe_en = A_TRUE; - SW_GET_FIELD_BY_REG(HOST_ENTRY6, PPPOE_IDX, data, reg[6]); - entry->pppoe_id = data; - } - else - { - entry->pppoe_en = A_FALSE; - } - - if (7 == entry->port_id) - { - entry->port_id = 0; - entry->action = FAL_MAC_DROP; - } - else - { - SW_GET_FIELD_BY_REG(HOST_ENTRY6, ACTION, data, reg[6]); - entry->action = FAL_MAC_FRWRD; - if (0 == data) - { - entry->mirror_en = A_TRUE; - } - else if (1 == data) - { - entry->action = FAL_MAC_RDT_TO_CPU; - } - else if (2 == data) - { - entry->action = FAL_MAC_CPY_TO_CPU; - } - } - - return SW_OK; -} - -static sw_error_t -_dess_host_down_to_hw(a_uint32_t dev_id, a_uint32_t reg[]) -{ - sw_error_t rv; - a_uint32_t i, addr; - - for (i = 0; i < DESS_HOST_ENTRY_REG_NUM; i++) - { - if((DESS_HOST_ENTRY_REG_NUM - 1) == i) - { - addr = DESS_HOST_ENTRY_DATA7_ADDR; - } - else - { - addr = DESS_HOST_ENTRY_DATA0_ADDR + (i << 2); - } - - HSL_REG_ENTRY_GEN_SET(rv, dev_id, addr, sizeof (a_uint32_t), - (a_uint8_t *) (®[i]), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - } - - return SW_OK; -} - -static sw_error_t -_dess_host_up_to_sw(a_uint32_t dev_id, a_uint32_t reg[]) -{ - sw_error_t rv; - a_uint32_t i, addr; - - for (i = 0; i < DESS_HOST_ENTRY_REG_NUM; i++) - { - if((DESS_HOST_ENTRY_REG_NUM - 1) == i) - { - addr = DESS_HOST_ENTRY_DATA7_ADDR; - } - else - { - addr = DESS_HOST_ENTRY_DATA0_ADDR + (i << 2); - } - HSL_REG_ENTRY_GEN_GET(rv, dev_id, addr, sizeof (a_uint32_t), - (a_uint8_t *) (®[i]), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - } - - return SW_OK; -} - -static sw_error_t -_dess_ip_host_add(a_uint32_t dev_id, fal_host_entry_t * entry) -{ - sw_error_t rv; - a_uint32_t reg[DESS_HOST_ENTRY_REG_NUM] = { 0 }; - - HSL_DEV_ID_CHECK(dev_id); - - rv = _dess_ip_feature_check(dev_id); - SW_RTN_ON_ERROR(rv); - - rv = _dess_host_sw_to_hw(dev_id, entry, reg); - SW_RTN_ON_ERROR(rv); - - aos_lock_bh(&dess_nat_lock); - rv = _dess_host_down_to_hw(dev_id, reg); - if (rv != SW_OK) { - aos_unlock_bh(&dess_nat_lock); - return rv; - } - - rv = _dess_host_entry_commit(dev_id, DESS_ENTRY_ARP, DESS_HOST_ENTRY_ADD); - if (rv != SW_OK) { - aos_unlock_bh(&dess_nat_lock); - return rv; - } - - HSL_REG_ENTRY_GET(rv, dev_id, HOST_ENTRY7, 0, (a_uint8_t *) (®[7]), - sizeof (a_uint32_t)); - if (rv != SW_OK) { - aos_unlock_bh(&dess_nat_lock); - return rv; - } - aos_unlock_bh(&dess_nat_lock); - SW_GET_FIELD_BY_REG(HOST_ENTRY7, TBL_IDX, entry->entry_id, reg[7]); - - return SW_OK; -} - -static sw_error_t -_dess_ip_host_del(a_uint32_t dev_id, a_uint32_t del_mode, - fal_host_entry_t * entry) -{ - sw_error_t rv; - a_uint32_t data, reg[DESS_HOST_ENTRY_REG_NUM] = { 0 }, op = DESS_HOST_ENTRY_FLUSH; - - HSL_DEV_ID_CHECK(dev_id); - - rv = _dess_ip_feature_check(dev_id); - SW_RTN_ON_ERROR(rv); - - if (FAL_IP_ENTRY_ID_EN & del_mode) - { - return SW_NOT_SUPPORTED; - } - - if (FAL_IP_ENTRY_IPADDR_EN & del_mode) - { - op = DESS_HOST_ENTRY_DEL; - if (FAL_IP_IP4_ADDR & entry->flags) - { - reg[0] = entry->ip4_addr; - } - - if (FAL_IP_IP6_ADDR & entry->flags) - { - reg[0] = entry->ip6_addr.ul[3]; - reg[1] = entry->ip6_addr.ul[2]; - reg[2] = entry->ip6_addr.ul[1]; - reg[3] = entry->ip6_addr.ul[0]; - SW_SET_REG_BY_FIELD(HOST_ENTRY6, IP_VER, 1, reg[6]); - } - } - - if (FAL_IP_ENTRY_INTF_EN & del_mode) - { - rv = _dess_ip_intf_sw_to_hw(dev_id, entry/*was:->intf_id*/, &data); - SW_RTN_ON_ERROR(rv); - - SW_SET_REG_BY_FIELD(HOST_ENTRY7, SPEC_VID, 1, reg[7]); - SW_SET_REG_BY_FIELD(HOST_ENTRY5, INTF_ID, data, reg[5]); - } - - if (FAL_IP_ENTRY_PORT_EN & del_mode) - { - SW_SET_REG_BY_FIELD(HOST_ENTRY7, SPEC_SP, 1, reg[7]); - SW_SET_REG_BY_FIELD(HOST_ENTRY5, SRC_PORT, entry->port_id, reg[5]); - } - - if (FAL_IP_ENTRY_STATUS_EN & del_mode) - { - SW_SET_REG_BY_FIELD(HOST_ENTRY7, SPEC_STATUS, 1, reg[7]); - SW_SET_REG_BY_FIELD(HOST_ENTRY6, AGE_FLAG, entry->status, reg[6]); - } - aos_lock_bh(&dess_nat_lock); - rv = _dess_host_down_to_hw(dev_id, reg); - if (rv != SW_OK) { - aos_unlock_bh(&dess_nat_lock); - return rv; - } - - rv = _dess_host_entry_commit(dev_id, DESS_ENTRY_ARP, op); - aos_unlock_bh(&dess_nat_lock); - - return rv; -} - -static sw_error_t -_dess_ip_host_get(a_uint32_t dev_id, a_uint32_t get_mode, - fal_host_entry_t * entry) -{ - sw_error_t rv; - a_uint32_t reg[DESS_HOST_ENTRY_REG_NUM] = { 0 }; - - HSL_DEV_ID_CHECK(dev_id); - - rv = _dess_ip_feature_check(dev_id); - SW_RTN_ON_ERROR(rv); - - if (FAL_IP_ENTRY_IPADDR_EN != get_mode) - { - return SW_NOT_SUPPORTED; - } - - if (FAL_IP_IP4_ADDR & entry->flags) - { - reg[0] = entry->ip4_addr; - } - else - { - reg[0] = entry->ip6_addr.ul[3]; - reg[1] = entry->ip6_addr.ul[2]; - reg[2] = entry->ip6_addr.ul[1]; - reg[3] = entry->ip6_addr.ul[0]; - SW_SET_REG_BY_FIELD(HOST_ENTRY6, IP_VER, 1, reg[6]); - } - aos_lock_bh(&dess_nat_lock); - rv = _dess_host_down_to_hw(dev_id, reg); - if (rv != SW_OK) { - aos_unlock_bh(&dess_nat_lock); - return rv; - } - - rv = _dess_host_entry_commit(dev_id, DESS_ENTRY_ARP, - DESS_HOST_ENTRY_SEARCH); - if (rv != SW_OK) { - aos_unlock_bh(&dess_nat_lock); - return rv; - } - - rv = _dess_host_up_to_sw(dev_id, reg); - if (rv != SW_OK) { - aos_unlock_bh(&dess_nat_lock); - return rv; - } - - aos_mem_zero(entry, sizeof (fal_host_entry_t)); - - rv = _dess_host_hw_to_sw(dev_id, reg, entry); - if (rv != SW_OK) { - aos_unlock_bh(&dess_nat_lock); - return rv; - } - - if (!(entry->status)) - { - aos_unlock_bh(&dess_nat_lock); - return SW_NOT_FOUND; - } - - HSL_REG_ENTRY_GET(rv, dev_id, HOST_ENTRY7, 0, (a_uint8_t *) (®[7]), - sizeof (a_uint32_t)); - aos_unlock_bh(&dess_nat_lock); - SW_RTN_ON_ERROR(rv); - - SW_GET_FIELD_BY_REG(HOST_ENTRY7, TBL_IDX, entry->entry_id, reg[7]); - return SW_OK; -} - -static sw_error_t -_dess_ip_host_next(a_uint32_t dev_id, a_uint32_t next_mode, - fal_host_entry_t * entry) -{ - sw_error_t rv; - a_uint32_t idx, data, reg[DESS_HOST_ENTRY_REG_NUM] = { 0 }; - - HSL_DEV_ID_CHECK(dev_id); - - rv = _dess_ip_feature_check(dev_id); - SW_RTN_ON_ERROR(rv); - - if (FAL_NEXT_ENTRY_FIRST_ID == entry->entry_id) - { - idx = DESS_HOST_ENTRY_NUM - 1; - } - else - { - if ((DESS_HOST_ENTRY_NUM - 1) == entry->entry_id) - { - return SW_NO_MORE; - } - else - { - idx = entry->entry_id; - } - } - - SW_SET_REG_BY_FIELD(HOST_ENTRY7, TBL_IDX, idx, reg[7]); - - if (FAL_IP_ENTRY_INTF_EN & next_mode) - { - rv = _dess_ip_intf_sw_to_hw(dev_id, entry/*was:->intf_id*/, &data); - SW_RTN_ON_ERROR(rv); - - SW_SET_REG_BY_FIELD(HOST_ENTRY7, SPEC_VID, 1, reg[7]); - SW_SET_REG_BY_FIELD(HOST_ENTRY5, INTF_ID, data, reg[5]); - } - - if (FAL_IP_ENTRY_PORT_EN & next_mode) - { - SW_SET_REG_BY_FIELD(HOST_ENTRY7, SPEC_SP, 1, reg[7]); - SW_SET_REG_BY_FIELD(HOST_ENTRY5, SRC_PORT, entry->port_id, reg[5]); - } - - if (FAL_IP_ENTRY_STATUS_EN & next_mode) - { - SW_SET_REG_BY_FIELD(HOST_ENTRY7, SPEC_STATUS, 1, reg[7]); - SW_SET_REG_BY_FIELD(HOST_ENTRY6, AGE_FLAG, entry->status, reg[6]); - } - - SW_SET_REG_BY_FIELD(HOST_ENTRY6, VRF_ID, entry->vrf_id, reg[6]); - aos_lock_bh(&dess_nat_lock); - rv = _dess_host_down_to_hw(dev_id, reg); - if (rv != SW_OK) { - aos_unlock_bh(&dess_nat_lock); - return rv; - } - - rv = _dess_host_entry_commit(dev_id, DESS_ENTRY_ARP, DESS_HOST_ENTRY_NEXT); - if (rv != SW_OK) { - aos_unlock_bh(&dess_nat_lock); - return rv; - } - - rv = _dess_host_up_to_sw(dev_id, reg); - aos_unlock_bh(&dess_nat_lock); - SW_RTN_ON_ERROR(rv); - - aos_mem_zero(entry, sizeof (fal_host_entry_t)); - - rv = _dess_host_hw_to_sw(dev_id, reg, entry); - SW_RTN_ON_ERROR(rv); - - if (!(entry->status)) - { - return SW_NO_MORE; - } - - SW_GET_FIELD_BY_REG(HOST_ENTRY7, TBL_IDX, entry->entry_id, reg[7]); - return SW_OK; -} - -static sw_error_t -_dess_ip_host_counter_bind(a_uint32_t dev_id, a_uint32_t entry_id, - a_uint32_t cnt_id, a_bool_t enable) -{ - sw_error_t rv; - a_uint32_t reg[DESS_HOST_ENTRY_REG_NUM] = { 0 }, tbl[DESS_HOST_ENTRY_REG_NUM] = { 0 }, tbl_idx; - - HSL_DEV_ID_CHECK(dev_id); - - rv = _dess_ip_feature_check(dev_id); - SW_RTN_ON_ERROR(rv); - - tbl_idx = (entry_id - 1) & 0x7f; - SW_SET_REG_BY_FIELD(HOST_ENTRY7, TBL_IDX, tbl_idx, reg[7]); - - rv = _dess_host_down_to_hw(dev_id, reg); - SW_RTN_ON_ERROR(rv); - - rv = _dess_host_entry_commit(dev_id, DESS_ENTRY_ARP, DESS_HOST_ENTRY_NEXT); - if (SW_OK != rv) - { - return SW_NOT_FOUND; - } - - rv = _dess_host_up_to_sw(dev_id, reg); - SW_RTN_ON_ERROR(rv); - - SW_GET_FIELD_BY_REG(HOST_ENTRY7, TBL_IDX, tbl_idx, reg[7]); - if (entry_id != tbl_idx) - { - return SW_NOT_FOUND; - } - - tbl[0] = reg[0]; - tbl[1] = reg[1]; - tbl[2] = reg[2]; - tbl[3] = reg[3]; - tbl[6] = (reg[6] >> 15) << 15; - rv = _dess_host_down_to_hw(dev_id, tbl); - SW_RTN_ON_ERROR(rv); - - rv = _dess_host_entry_commit(dev_id, DESS_ENTRY_ARP, DESS_HOST_ENTRY_DEL); - SW_RTN_ON_ERROR(rv); - - if (A_FALSE == enable) - { - SW_SET_REG_BY_FIELD(HOST_ENTRY6, CNT_EN, 0, reg[6]); - } - else if (A_TRUE == enable) - { - SW_SET_REG_BY_FIELD(HOST_ENTRY6, CNT_EN, 1, reg[6]); - SW_SET_REG_BY_FIELD(HOST_ENTRY6, CNT_IDX, cnt_id, reg[6]); - } - else - { - return SW_BAD_PARAM; - } - - reg[7] = 0x0; - rv = _dess_host_down_to_hw(dev_id, reg); - SW_RTN_ON_ERROR(rv); - - rv = _dess_host_entry_commit(dev_id, DESS_ENTRY_ARP, DESS_HOST_ENTRY_ADD); - return rv; -} - -static sw_error_t -_dess_ip_host_pppoe_bind(a_uint32_t dev_id, a_uint32_t entry_id, - a_uint32_t pppoe_id, a_bool_t enable) -{ - sw_error_t rv; - a_uint32_t reg[DESS_HOST_ENTRY_REG_NUM] = { 0 }, tbl[DESS_HOST_ENTRY_REG_NUM] = { 0 }, tbl_idx; - - HSL_DEV_ID_CHECK(dev_id); - - rv = _dess_ip_feature_check(dev_id); - SW_RTN_ON_ERROR(rv); - - tbl_idx = (entry_id - 1) & 0x7f; - SW_SET_REG_BY_FIELD(HOST_ENTRY7, TBL_IDX, tbl_idx, reg[7]); - aos_lock_bh(&dess_nat_lock); - rv = _dess_host_down_to_hw(dev_id, reg); - if (rv != SW_OK) { - aos_unlock_bh(&dess_nat_lock); - return rv; - } - - rv = _dess_host_entry_commit(dev_id, DESS_ENTRY_ARP, DESS_HOST_ENTRY_NEXT); - if (rv != SW_OK) { - aos_unlock_bh(&dess_nat_lock); - return rv; - } - - rv = _dess_host_up_to_sw(dev_id, reg); - aos_unlock_bh(&dess_nat_lock); - if (SW_OK != rv) - { - return SW_NOT_FOUND; - } - - SW_GET_FIELD_BY_REG(HOST_ENTRY7, TBL_IDX, tbl_idx, reg[7]); - if (entry_id != tbl_idx) - { - return SW_NOT_FOUND; - } - - if (A_FALSE == enable) - { - SW_SET_REG_BY_FIELD(HOST_ENTRY6, PPPOE_EN, 0, reg[6]); - } - else if (A_TRUE == enable) - { - SW_SET_REG_BY_FIELD(HOST_ENTRY6, PPPOE_EN, 1, reg[6]); - SW_SET_REG_BY_FIELD(HOST_ENTRY6, PPPOE_IDX, pppoe_id, reg[6]); - } - else - { - return SW_BAD_PARAM; - } - - tbl[0] = reg[0]; - tbl[1] = reg[1]; - tbl[2] = reg[2]; - tbl[3] = reg[3]; - tbl[6] = (reg[6] >> 15) << 15; - aos_lock_bh(&dess_nat_lock); - rv = _dess_host_down_to_hw(dev_id, tbl); - if (rv != SW_OK) { - aos_unlock_bh(&dess_nat_lock); - return rv; - } - - rv = _dess_host_entry_commit(dev_id, DESS_ENTRY_ARP, DESS_HOST_ENTRY_DEL); - if (rv != SW_OK) { - aos_unlock_bh(&dess_nat_lock); - return rv; - } - - reg[7] = 0x0; - rv = _dess_host_down_to_hw(dev_id, reg); - if (rv != SW_OK) { - aos_unlock_bh(&dess_nat_lock); - return rv; - } - - rv = _dess_host_entry_commit(dev_id, DESS_ENTRY_ARP, DESS_HOST_ENTRY_ADD); - if (rv != SW_OK) { - aos_unlock_bh(&dess_nat_lock); - return rv; - } - - rv = _dess_host_up_to_sw(dev_id, reg); - aos_unlock_bh(&dess_nat_lock); - SW_RTN_ON_ERROR(rv); - - return SW_OK; -} - -static sw_error_t -_dess_ip_pt_arp_learn_set(a_uint32_t dev_id, fal_port_t port_id, - a_uint32_t flags) -{ - sw_error_t rv; - a_uint32_t data = 0; - - HSL_DEV_ID_CHECK(dev_id); - - rv = _dess_ip_feature_check(dev_id); - SW_RTN_ON_ERROR(rv); - - HSL_REG_ENTRY_GET(rv, dev_id, ROUTER_PTCTRL2, 0, - (a_uint8_t *) (&data), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - - if (FAL_ARP_LEARN_REQ & flags) - { - data |= (0x1 << port_id); - } - else - { - data &= (~(0x1 << port_id)); - } - - if (FAL_ARP_LEARN_ACK & flags) - { - data |= (0x1 << (ROUTER_PTCTRL2_ARP_LEARN_ACK_BOFFSET + port_id)); - } - else - { - data &= (~(0x1 << (ROUTER_PTCTRL2_ARP_LEARN_ACK_BOFFSET + port_id))); - } - - HSL_REG_ENTRY_SET(rv, dev_id, ROUTER_PTCTRL2, 0, - (a_uint8_t *) (&data), sizeof (a_uint32_t)); - return rv; -} - -static sw_error_t -_dess_ip_pt_arp_learn_get(a_uint32_t dev_id, fal_port_t port_id, - a_uint32_t * flags) -{ - sw_error_t rv; - a_uint32_t data = 0; - - HSL_DEV_ID_CHECK(dev_id); - - rv = _dess_ip_feature_check(dev_id); - SW_RTN_ON_ERROR(rv); - - *flags = 0; - - HSL_REG_ENTRY_GET(rv, dev_id, ROUTER_PTCTRL2, 0, - (a_uint8_t *) (&data), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - - if (data & (0x1 << port_id)) - { - *flags |= FAL_ARP_LEARN_REQ; - } - - if (data & (0x1 << (ROUTER_PTCTRL2_ARP_LEARN_ACK_BOFFSET + port_id))) - { - *flags |= FAL_ARP_LEARN_ACK; - } - - return SW_OK; -} - -static sw_error_t -_dess_ip_arp_learn_set(a_uint32_t dev_id, fal_arp_learn_mode_t mode) -{ - sw_error_t rv; - a_uint32_t data; - - HSL_DEV_ID_CHECK(dev_id); - - rv = _dess_ip_feature_check(dev_id); - SW_RTN_ON_ERROR(rv); - - if (FAL_ARP_LEARN_ALL == mode) - { - data = 1; - } - else if (FAL_ARP_LEARN_LOCAL == mode) - { - data = 0; - } - else - { - return SW_BAD_PARAM; - } - - HSL_REG_FIELD_SET(rv, dev_id, ROUTER_CTRL, 0, ARP_LEARN_MODE, - (a_uint8_t *) (&data), sizeof (a_uint32_t)); - return rv; -} - -static sw_error_t -_dess_ip_arp_learn_get(a_uint32_t dev_id, fal_arp_learn_mode_t * mode) -{ - sw_error_t rv; - a_uint32_t data = 0; - - HSL_DEV_ID_CHECK(dev_id); - - rv = _dess_ip_feature_check(dev_id); - SW_RTN_ON_ERROR(rv); - - HSL_REG_FIELD_GET(rv, dev_id, ROUTER_CTRL, 0, ARP_LEARN_MODE, - (a_uint8_t *) (&data), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - - if (data) - { - *mode = FAL_ARP_LEARN_ALL; - } - else - { - *mode = FAL_ARP_LEARN_LOCAL; - } - - return SW_OK; -} - -static sw_error_t -_dess_ip_source_guard_set(a_uint32_t dev_id, fal_port_t port_id, - fal_source_guard_mode_t mode) -{ - sw_error_t rv; - a_uint32_t reg = 0, data; - - HSL_DEV_ID_CHECK(dev_id); - - rv = _dess_ip_feature_check(dev_id); - SW_RTN_ON_ERROR(rv); - - HSL_REG_ENTRY_GET(rv, dev_id, ROUTER_PTCTRL1, 0, - (a_uint8_t *) (®), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - - if (FAL_NO_SOURCE_GUARD < mode) - { - return SW_BAD_PARAM; - } - - data = 0; - if (FAL_MAC_IP_GUARD == mode) - { - data = 1; - } - else if (FAL_MAC_IP_PORT_GUARD == mode) - { - data = 2; - } - else if (FAL_MAC_IP_VLAN_GUARD == mode) - { - data = 3; - } - else if (FAL_MAC_IP_PORT_VLAN_GUARD == mode) - { - data = 4; - } - reg &= (~(0x7 << (port_id * 3))); - reg |= ((data & 0x7) << (port_id * 3)); - - HSL_REG_ENTRY_SET(rv, dev_id, ROUTER_PTCTRL1, 0, - (a_uint8_t *) (®), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - - data = 1; - if (FAL_NO_SOURCE_GUARD == mode) - { - data = 0; - } - - HSL_REG_FIELD_SET(rv, dev_id, PORT_VLAN1, port_id, SP_CHECK_EN, - (a_uint8_t *) (&data), sizeof (a_uint32_t)); - return rv; -} - -static sw_error_t -_dess_ip_source_guard_get(a_uint32_t dev_id, fal_port_t port_id, - fal_source_guard_mode_t * mode) -{ - sw_error_t rv; - a_uint32_t reg = 0, data; - - HSL_DEV_ID_CHECK(dev_id); - - rv = _dess_ip_feature_check(dev_id); - SW_RTN_ON_ERROR(rv); - - HSL_REG_ENTRY_GET(rv, dev_id, ROUTER_PTCTRL1, 0, - (a_uint8_t *) (®), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - - data = (reg >> (port_id * 3)) & 0x7; - - *mode = FAL_NO_SOURCE_GUARD; - if (1 == data) - { - *mode = FAL_MAC_IP_GUARD; - } - else if (2 == data) - { - *mode = FAL_MAC_IP_PORT_GUARD; - } - else if (3 == data) - { - *mode = FAL_MAC_IP_VLAN_GUARD; - } - else if (4 == data) - { - *mode = FAL_MAC_IP_PORT_VLAN_GUARD; - } - - return SW_OK; -} - -static sw_error_t -_dess_ip_unk_source_cmd_set(a_uint32_t dev_id, fal_fwd_cmd_t cmd) -{ - sw_error_t rv; - a_uint32_t data; - - HSL_DEV_ID_CHECK(dev_id); - - rv = _dess_ip_feature_check(dev_id); - SW_RTN_ON_ERROR(rv); - - if (FAL_MAC_FRWRD == cmd) - { - data = 0; - } - else if (FAL_MAC_DROP == cmd) - { - data = 1; - } - else if (FAL_MAC_RDT_TO_CPU == cmd) - { - data = 2; - } - else - { - return SW_NOT_SUPPORTED; - } - - HSL_REG_FIELD_SET(rv, dev_id, FORWARD_CTL0, 0, IP_NOT_FOUND, - (a_uint8_t *) (&data), sizeof (a_uint32_t)); - return rv; -} - -static sw_error_t -_dess_ip_unk_source_cmd_get(a_uint32_t dev_id, fal_fwd_cmd_t * cmd) -{ - sw_error_t rv; - a_uint32_t data = 0; - - HSL_DEV_ID_CHECK(dev_id); - - rv = _dess_ip_feature_check(dev_id); - SW_RTN_ON_ERROR(rv); - - HSL_REG_FIELD_GET(rv, dev_id, FORWARD_CTL0, 0, IP_NOT_FOUND, - (a_uint8_t *) (&data), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - - if (0 == data) - { - *cmd = FAL_MAC_FRWRD; - } - else if (1 == data) - { - *cmd = FAL_MAC_DROP; - } - else - { - *cmd = FAL_MAC_RDT_TO_CPU; - } - - return SW_OK; -} - -static sw_error_t -_dess_ip_arp_guard_set(a_uint32_t dev_id, fal_port_t port_id, - fal_source_guard_mode_t mode) -{ - sw_error_t rv; - a_uint32_t reg = 0, data; - - HSL_DEV_ID_CHECK(dev_id); - - rv = _dess_ip_feature_check(dev_id); - SW_RTN_ON_ERROR(rv); - - HSL_DEV_ID_CHECK(dev_id); - - HSL_REG_ENTRY_GET(rv, dev_id, ROUTER_PTCTRL0, 0, - (a_uint8_t *) (®), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - - if (FAL_NO_SOURCE_GUARD < mode) - { - return SW_BAD_PARAM; - } - - data = 0; - if (FAL_MAC_IP_GUARD == mode) - { - data = 1; - } - else if (FAL_MAC_IP_PORT_GUARD == mode) - { - data = 2; - } - else if (FAL_MAC_IP_VLAN_GUARD == mode) - { - data = 3; - } - else if (FAL_MAC_IP_PORT_VLAN_GUARD == mode) - { - data = 4; - } - reg &= (~(0x7 << (port_id * 3))); - reg |= ((data & 0x7) << (port_id * 3)); - - HSL_REG_ENTRY_SET(rv, dev_id, ROUTER_PTCTRL0, 0, - (a_uint8_t *) (®), sizeof (a_uint32_t)); - return rv; -} - -static sw_error_t -_dess_ip_arp_guard_get(a_uint32_t dev_id, fal_port_t port_id, - fal_source_guard_mode_t * mode) -{ - sw_error_t rv; - a_uint32_t reg = 0, data; - - HSL_DEV_ID_CHECK(dev_id); - - rv = _dess_ip_feature_check(dev_id); - SW_RTN_ON_ERROR(rv); - - HSL_DEV_ID_CHECK(dev_id); - - HSL_REG_ENTRY_GET(rv, dev_id, ROUTER_PTCTRL0, 0, - (a_uint8_t *) (®), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - - data = (reg >> (port_id * 3)) & 0x7; - - *mode = FAL_NO_SOURCE_GUARD; - if (1 == data) - { - *mode = FAL_MAC_IP_GUARD; - } - else if (2 == data) - { - *mode = FAL_MAC_IP_PORT_GUARD; - } - else if (3 == data) - { - *mode = FAL_MAC_IP_VLAN_GUARD; - } - else if (4 == data) - { - *mode = FAL_MAC_IP_PORT_VLAN_GUARD; - } - - return SW_OK; -} - -static sw_error_t -_dess_arp_unk_source_cmd_set(a_uint32_t dev_id, fal_fwd_cmd_t cmd) -{ - sw_error_t rv; - a_uint32_t data; - - HSL_DEV_ID_CHECK(dev_id); - - rv = _dess_ip_feature_check(dev_id); - SW_RTN_ON_ERROR(rv); - - if (FAL_MAC_FRWRD == cmd) - { - data = 0; - } - else if (FAL_MAC_DROP == cmd) - { - data = 1; - } - else if (FAL_MAC_RDT_TO_CPU == cmd) - { - data = 2; - } - else - { - return SW_NOT_SUPPORTED; - } - - HSL_REG_FIELD_SET(rv, dev_id, FORWARD_CTL0, 0, ARP_NOT_FOUND, - (a_uint8_t *) (&data), sizeof (a_uint32_t)); - return rv; -} - -static sw_error_t -_dess_arp_unk_source_cmd_get(a_uint32_t dev_id, fal_fwd_cmd_t * cmd) -{ - sw_error_t rv; - a_uint32_t data = 0; - - HSL_DEV_ID_CHECK(dev_id); - - rv = _dess_ip_feature_check(dev_id); - SW_RTN_ON_ERROR(rv); - - HSL_REG_FIELD_GET(rv, dev_id, FORWARD_CTL0, 0, ARP_NOT_FOUND, - (a_uint8_t *) (&data), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - - if (0 == data) - { - *cmd = FAL_MAC_FRWRD; - } - else if (1 == data) - { - *cmd = FAL_MAC_DROP; - } - else - { - *cmd = FAL_MAC_RDT_TO_CPU; - } - - return SW_OK; -} - -static sw_error_t -_dess_ip_route_status_set(a_uint32_t dev_id, a_bool_t enable) -{ - sw_error_t rv; - a_uint32_t data; - - HSL_DEV_ID_CHECK(dev_id); - - rv = _dess_ip_feature_check(dev_id); - SW_RTN_ON_ERROR(rv); - - if (A_TRUE == enable) - { - data = 1; - } - else if (A_FALSE == enable) - { - data = 0; - } - else - { - return SW_BAD_PARAM; - } - - HSL_REG_FIELD_SET(rv, dev_id, ROUTER_CTRL, 0, ROUTER_EN, - (a_uint8_t *) (&data), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - - HSL_REG_FIELD_SET(rv, dev_id, MOD_ENABLE, 0, L3_EN, - (a_uint8_t *) (&data), sizeof (a_uint32_t)); - return rv; -} - -static sw_error_t -_dess_ip_route_status_get(a_uint32_t dev_id, a_bool_t * enable) -{ - sw_error_t rv; - a_uint32_t route_en = 0, l3_en = 0; - - HSL_DEV_ID_CHECK(dev_id); - - rv = _dess_ip_feature_check(dev_id); - SW_RTN_ON_ERROR(rv); - - HSL_REG_FIELD_GET(rv, dev_id, ROUTER_CTRL, 0, ROUTER_EN, - (a_uint8_t *) (&route_en), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - - HSL_REG_FIELD_GET(rv, dev_id, MOD_ENABLE, 0, L3_EN, - (a_uint8_t *) (&l3_en), sizeof (a_uint32_t)) - SW_RTN_ON_ERROR(rv); - - if (route_en && l3_en) - { - *enable = A_TRUE; - } - else - { - *enable = A_FALSE; - } - - return rv; -} - -static sw_error_t -_dess_ip_intf_entry_add(a_uint32_t dev_id, fal_intf_mac_entry_t * entry) -{ - sw_error_t rv; - a_uint32_t i, j, found = 0, addr, tbl[3] = { 0 }; - fal_intf_mac_entry_t * intf_entry = NULL; - - HSL_DEV_ID_CHECK(dev_id); - - rv = _dess_ip_feature_check(dev_id); - SW_RTN_ON_ERROR(rv); - - for (i = 0; i < DESS_INTF_MAC_ADDR_NUM; i++) - { - if (dess_mac_snap[dev_id] & (0x1 << i)) - { - intf_entry = &(dess_intf_snap[dev_id][i]); - if ((entry->vid_low == intf_entry->vid_low) - && (entry->vid_high == intf_entry->vid_high)) - { - /* all same, return OK directly */ - if (!aos_mem_cmp(intf_entry, entry, sizeof(fal_intf_mac_entry_t))) - { - return SW_OK; - } - else - { - /* update entry */ - found = 1; - break; - } - } - else - { - /* entry VID cross border, not support */ - if ((entry->vid_low >= intf_entry->vid_low) && (entry->vid_low <= intf_entry->vid_high)) - { - return SW_BAD_PARAM; - } - - /* entry VID cross border, not support */ - if ((entry->vid_high >= intf_entry->vid_low) && (entry->vid_low <= intf_entry->vid_high)) - { - return SW_BAD_PARAM; - } - } - } - } - - if (!found) - { - for (i = 0; i < DESS_INTF_MAC_ADDR_NUM; i++) - { - if (!(dess_mac_snap[dev_id] & (0x1 << i))) - { - intf_entry = &(dess_intf_snap[dev_id][i]); - break; - } - } - } - - if (DESS_INTF_MAC_ADDR_NUM == i) - { - return SW_NO_RESOURCE; - } - - if ((A_FALSE == entry->ip4_route) && (A_FALSE == entry->ip6_route)) - { - return SW_NOT_SUPPORTED; - } - - if (512 <= (entry->vid_high - entry->vid_low)) - { - return SW_BAD_PARAM; - } - - SW_SET_REG_BY_FIELD(INTF_ADDR_ENTRY0, MAC_ADDR2, entry->mac_addr.uc[2], - tbl[0]); - SW_SET_REG_BY_FIELD(INTF_ADDR_ENTRY0, MAC_ADDR3, entry->mac_addr.uc[3], - tbl[0]); - SW_SET_REG_BY_FIELD(INTF_ADDR_ENTRY0, MAC_ADDR4, entry->mac_addr.uc[4], - tbl[0]); - SW_SET_REG_BY_FIELD(INTF_ADDR_ENTRY0, MAC_ADDR5, entry->mac_addr.uc[5], - tbl[0]); - SW_SET_REG_BY_FIELD(INTF_ADDR_ENTRY1, MAC_ADDR0, entry->mac_addr.uc[0], - tbl[1]); - SW_SET_REG_BY_FIELD(INTF_ADDR_ENTRY1, MAC_ADDR1, entry->mac_addr.uc[1], - tbl[1]); - - SW_SET_REG_BY_FIELD(INTF_ADDR_ENTRY1, VID_LOW, entry->vid_low, tbl[1]); - SW_SET_REG_BY_FIELD(INTF_ADDR_ENTRY1, VID_HIGH0, (entry->vid_high & 0xf), - tbl[1]); - SW_SET_REG_BY_FIELD(INTF_ADDR_ENTRY2, VID_HIGH1, (entry->vid_high >> 4), - tbl[2]); - - if (A_TRUE == entry->ip4_route) - { - SW_SET_REG_BY_FIELD(INTF_ADDR_ENTRY2, IP4_ROUTE, 1, tbl[2]); - } - - if (A_TRUE == entry->ip6_route) - { - SW_SET_REG_BY_FIELD(INTF_ADDR_ENTRY2, IP6_ROUTE, 1, tbl[2]); - } - - SW_SET_REG_BY_FIELD(INTF_ADDR_ENTRY2, VRF_ID, entry->vrf_id, tbl[2]); - - for (j = 0; j < 2; j++) - { - addr = DESS_INTF_MAC_EDIT0_ADDR + (i << 4) + (j << 2); - HSL_REG_ENTRY_GEN_SET(rv, dev_id, addr, sizeof (a_uint32_t), - (a_uint8_t *) (&(tbl[j])), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - } - - for (j = 0; j < 3; j++) - { - addr = DESS_INTF_MAC_TBL0_ADDR + (i << 4) + (j << 2); - HSL_REG_ENTRY_GEN_SET(rv, dev_id, addr, sizeof (a_uint32_t), - (a_uint8_t *) (&(tbl[j])), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - } - - dess_mac_snap[dev_id] |= (0x1 << i); - *intf_entry = *entry; - entry->entry_id = i; - return SW_OK; -} - -static sw_error_t -_dess_ip_intf_entry_del(a_uint32_t dev_id, a_uint32_t del_mode, - fal_intf_mac_entry_t * entry) -{ - sw_error_t rv; - a_uint32_t addr, tbl[3] = { 0 }; - - HSL_DEV_ID_CHECK(dev_id); - - rv = _dess_ip_feature_check(dev_id); - SW_RTN_ON_ERROR(rv); - - if (!(FAL_IP_ENTRY_ID_EN & del_mode)) - { - return SW_NOT_SUPPORTED; - } - - if (DESS_INTF_MAC_ADDR_NUM <= entry->entry_id) - { - return SW_BAD_PARAM; - } - - /* clear valid bits */ - addr = DESS_INTF_MAC_TBL2_ADDR + (entry->entry_id << 4); - HSL_REG_ENTRY_GEN_SET(rv, dev_id, addr, sizeof (a_uint32_t), - (a_uint8_t *) (&(tbl[2])), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - - dess_mac_snap[dev_id] &= (~(0x1 << entry->entry_id)); - return SW_OK; -} - -static sw_error_t -_dess_ip_intf_entry_next(a_uint32_t dev_id, a_uint32_t next_mode, - fal_intf_mac_entry_t * entry) -{ - sw_error_t rv; - a_uint32_t i, j, idx, addr, tbl[3] = { 0 }; - - HSL_DEV_ID_CHECK(dev_id); - - rv = _dess_ip_feature_check(dev_id); - SW_RTN_ON_ERROR(rv); - - if (FAL_NEXT_ENTRY_FIRST_ID == entry->entry_id) - { - idx = 0; - } - else - { - if ((DESS_INTF_MAC_ADDR_NUM - 1) == entry->entry_id) - { - return SW_NO_MORE; - } - else - { - idx = entry->entry_id + 1; - } - } - - for (i = idx; i < DESS_INTF_MAC_ADDR_NUM; i++) - { - if (dess_mac_snap[dev_id] & (0x1 << i)) - { - break; - } - } - - if (DESS_INTF_MAC_ADDR_NUM == i) - { - return SW_NO_MORE; - } - - for (j = 0; j < 3; j++) - { - addr = DESS_INTF_MAC_TBL0_ADDR + (i << 4) + (j << 2); - HSL_REG_ENTRY_GEN_GET(rv, dev_id, addr, sizeof (a_uint32_t), - (a_uint8_t *) (&(tbl[j])), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - } - - aos_mem_zero(entry, sizeof (fal_intf_mac_entry_t)); - - SW_GET_FIELD_BY_REG(INTF_ADDR_ENTRY0, MAC_ADDR2, entry->mac_addr.uc[2], - tbl[0]); - SW_GET_FIELD_BY_REG(INTF_ADDR_ENTRY0, MAC_ADDR3, entry->mac_addr.uc[3], - tbl[0]); - SW_GET_FIELD_BY_REG(INTF_ADDR_ENTRY0, MAC_ADDR4, entry->mac_addr.uc[4], - tbl[0]); - SW_GET_FIELD_BY_REG(INTF_ADDR_ENTRY0, MAC_ADDR5, entry->mac_addr.uc[5], - tbl[0]); - SW_GET_FIELD_BY_REG(INTF_ADDR_ENTRY1, MAC_ADDR0, entry->mac_addr.uc[0], - tbl[1]); - SW_GET_FIELD_BY_REG(INTF_ADDR_ENTRY1, MAC_ADDR1, entry->mac_addr.uc[1], - tbl[1]); - - SW_GET_FIELD_BY_REG(INTF_ADDR_ENTRY1, VID_LOW, entry->vid_low, tbl[1]); - SW_GET_FIELD_BY_REG(INTF_ADDR_ENTRY1, VID_HIGH0, j, tbl[1]); - entry->vid_high = j & 0xf; - SW_GET_FIELD_BY_REG(INTF_ADDR_ENTRY2, VID_HIGH1, j, tbl[2]); - entry->vid_high |= ((j & 0xff) << 4); - - SW_GET_FIELD_BY_REG(INTF_ADDR_ENTRY2, IP4_ROUTE, j, tbl[2]); - if (j) - { - entry->ip4_route = A_TRUE; - } - - SW_GET_FIELD_BY_REG(INTF_ADDR_ENTRY2, IP6_ROUTE, j, tbl[2]); - if (j) - { - entry->ip6_route = A_TRUE; - } - SW_GET_FIELD_BY_REG(INTF_ADDR_ENTRY2, VRF_ID, entry->vrf_id, tbl[2]); - - entry->entry_id = i; - return SW_OK; -} - -#define DESS_WCMP_ENTRY_MAX_ID 3 -#define DESS_WCMP_HASH_MAX_NUM 16 -#define DESS_IP_ENTRY_MAX_ID 127 - -#define DESS_WCMP_HASH_TBL_ADDR 0x0e10 -#define DESS_WCMP_NHOP_TBL_ADDR 0x0e20 - -static sw_error_t -_dess_ip_wcmp_entry_set(a_uint32_t dev_id, a_uint32_t wcmp_id, fal_ip_wcmp_t * wcmp) -{ - sw_error_t rv; - a_uint32_t i, j, addr, data; - a_uint8_t idx, ptr[4] = { 0 }, pos[16] = { 0 }; - - HSL_DEV_ID_CHECK(dev_id); - - rv = _dess_ip_feature_check(dev_id); - SW_RTN_ON_ERROR(rv); - - if (DESS_WCMP_ENTRY_MAX_ID < wcmp_id) - { - return SW_BAD_PARAM; - } - - if (DESS_WCMP_HASH_MAX_NUM < wcmp->nh_nr) - { - return SW_BAD_PARAM; - } - - for (i = 0; i < wcmp->nh_nr; i++) - { - if (DESS_IP_ENTRY_MAX_ID < wcmp->nh_id[i]) - { - return SW_BAD_PARAM; - } - - idx = 4; - for (j = 0; j < 4; j++) - { - if (ptr[j] & 0x80) - { - if ((ptr[j] & 0x7f) == wcmp->nh_id[i]) - { - idx = j; - break; - } - } - else - { - idx = j; - } - } - - if (4 == idx) - { - return SW_BAD_PARAM; - } - else - { - ptr[idx] = (wcmp->nh_id[i] & 0x7f) | 0x80; - pos[i] = idx; - } - } - - data = 0; - for (j = 0; j < 4; j++) - { - data |= (ptr[j] << (j << 3)); - } - - addr = DESS_WCMP_NHOP_TBL_ADDR + (wcmp_id << 2); - HSL_REG_ENTRY_GEN_SET(rv, dev_id, addr, sizeof (a_uint32_t), - (a_uint8_t *) (&data), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - - data = 0; - for (j = 0; j < 16; j++) - { - data |= (pos[j] << (j << 1)); - } - - addr = DESS_WCMP_HASH_TBL_ADDR + (wcmp_id << 2); - HSL_REG_ENTRY_GEN_SET(rv, dev_id, addr, sizeof (a_uint32_t), - (a_uint8_t *) (&data), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - - return SW_OK; -} - -static sw_error_t -_dess_ip_wcmp_entry_get(a_uint32_t dev_id, a_uint32_t wcmp_id, fal_ip_wcmp_t * wcmp) -{ - sw_error_t rv; - a_uint32_t i, addr, data = 0; - a_uint8_t ptr[4] = { 0 }, pos[16] = { 0 }; - - HSL_DEV_ID_CHECK(dev_id); - - rv = _dess_ip_feature_check(dev_id); - SW_RTN_ON_ERROR(rv); - - if (DESS_WCMP_ENTRY_MAX_ID < wcmp_id) - { - return SW_BAD_PARAM; - } - - wcmp->nh_nr = DESS_WCMP_HASH_MAX_NUM; - - addr = DESS_WCMP_NHOP_TBL_ADDR + (wcmp_id << 2); - HSL_REG_ENTRY_GEN_GET(rv, dev_id, addr, sizeof (a_uint32_t), - (a_uint8_t *) (&data), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - - for (i = 0; i < 4; i++) - { - ptr[i] = (data >> (i << 3)) & 0x7f; - } - - addr = DESS_WCMP_HASH_TBL_ADDR + (wcmp_id << 2); - HSL_REG_ENTRY_GEN_GET(rv, dev_id, addr, sizeof (a_uint32_t), - (a_uint8_t *) (&data), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - - for (i = 0; i < 16; i++) - { - pos[i] = (data >> (i << 1)) & 0x3; - } - - for (i = 0; i < 16; i++) - { - wcmp->nh_id[i] = ptr[pos[i]]; - } - - return SW_OK; -} - -static sw_error_t -_dess_ip_wcmp_hash_mode_set(a_uint32_t dev_id, a_uint32_t hash_mode) -{ - sw_error_t rv; - a_uint32_t data = 0; - - HSL_REG_ENTRY_GET(rv, dev_id, ROUTER_CTRL, 0, - (a_uint8_t *) (&data), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - - if (FAL_WCMP_HASH_KEY_SIP & hash_mode) - { - SW_SET_REG_BY_FIELD(ROUTER_CTRL, WCMP_HAHS_SIP, 1, data); - } - else - { - SW_SET_REG_BY_FIELD(ROUTER_CTRL, WCMP_HAHS_SIP, 0, data); - } - - if (FAL_WCMP_HASH_KEY_DIP & hash_mode) - { - SW_SET_REG_BY_FIELD(ROUTER_CTRL, WCMP_HAHS_DIP, 1, data); - } - else - { - SW_SET_REG_BY_FIELD(ROUTER_CTRL, WCMP_HAHS_DIP, 0, data); - } - - if (FAL_WCMP_HASH_KEY_SPORT & hash_mode) - { - SW_SET_REG_BY_FIELD(ROUTER_CTRL, WCMP_HAHS_SP, 1, data); - } - else - { - SW_SET_REG_BY_FIELD(ROUTER_CTRL, WCMP_HAHS_SP, 0, data); - } - - if (FAL_WCMP_HASH_KEY_DPORT & hash_mode) - { - SW_SET_REG_BY_FIELD(ROUTER_CTRL, WCMP_HAHS_DP, 1, data); - } - else - { - SW_SET_REG_BY_FIELD(ROUTER_CTRL, WCMP_HAHS_DP, 0, data); - } - - - HSL_REG_ENTRY_SET(rv, dev_id, ROUTER_CTRL, 0, - (a_uint8_t *) (&data), sizeof (a_uint32_t)); - return rv; -} - -static sw_error_t -_dess_ip_wcmp_hash_mode_get(a_uint32_t dev_id, a_uint32_t * hash_mode) -{ - sw_error_t rv; - a_uint32_t data = 0, field; - - *hash_mode = 0; - - HSL_REG_ENTRY_GET(rv, dev_id, ROUTER_CTRL, 0, - (a_uint8_t *) (&data), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - - SW_GET_FIELD_BY_REG(ROUTER_CTRL, WCMP_HAHS_SIP, field, data); - if (field) - { - *hash_mode |= FAL_WCMP_HASH_KEY_SIP; - } - - SW_GET_FIELD_BY_REG(ROUTER_CTRL, WCMP_HAHS_DIP, field, data); - if (field) - { - *hash_mode |= FAL_WCMP_HASH_KEY_DIP; - } - - SW_GET_FIELD_BY_REG(ROUTER_CTRL, WCMP_HAHS_SP, field, data); - if (field) - { - *hash_mode |= FAL_WCMP_HASH_KEY_SPORT; - } - - SW_GET_FIELD_BY_REG(ROUTER_CTRL, WCMP_HAHS_DP, field, data); - if (field) - { - *hash_mode |= FAL_WCMP_HASH_KEY_DPORT; - } - - return SW_OK; -} - -#define DESS_VRF_ENTRY_MAX_ID 7 - -#define DESS_VRF_ENTRY_TBL_ADDR 0x0484 -#define DESS_VRF_ENTRY_MASK_ADDR 0x0488 - -static sw_error_t -_dess_ip_vrf_base_addr_set(a_uint32_t dev_id, a_uint32_t vrf_id, fal_ip4_addr_t addr) -{ - sw_error_t rv; - a_uint32_t reg_addr; - - HSL_DEV_ID_CHECK(dev_id); - - rv = _dess_ip_feature_check(dev_id); - SW_RTN_ON_ERROR(rv); - - if (DESS_VRF_ENTRY_MAX_ID < vrf_id) - { - return SW_BAD_PARAM; - } - - reg_addr = DESS_VRF_ENTRY_TBL_ADDR + (vrf_id << 3); - HSL_REG_ENTRY_GEN_SET(rv, dev_id, reg_addr, sizeof (a_uint32_t), - (a_uint8_t *) (&addr), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - - return rv; -} - -static sw_error_t -_dess_ip_vrf_base_addr_get(a_uint32_t dev_id, a_uint32_t vrf_id, fal_ip4_addr_t * addr) -{ - sw_error_t rv; - a_uint32_t reg_addr; - - HSL_DEV_ID_CHECK(dev_id); - - rv = _dess_ip_feature_check(dev_id); - SW_RTN_ON_ERROR(rv); - - if (DESS_VRF_ENTRY_MAX_ID < vrf_id) - { - return SW_BAD_PARAM; - } - - reg_addr = DESS_VRF_ENTRY_TBL_ADDR + (vrf_id << 3); - HSL_REG_ENTRY_GEN_GET(rv, dev_id, reg_addr, sizeof (a_uint32_t), - (a_uint8_t *) (addr), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - - return SW_OK; -} - -static sw_error_t -_dess_ip_vrf_base_mask_set(a_uint32_t dev_id, a_uint32_t vrf_id, fal_ip4_addr_t addr) -{ - sw_error_t rv; - a_uint32_t reg_addr; - - HSL_DEV_ID_CHECK(dev_id); - - rv = _dess_ip_feature_check(dev_id); - SW_RTN_ON_ERROR(rv); - - if (DESS_VRF_ENTRY_MAX_ID < vrf_id) - { - return SW_BAD_PARAM; - } - - reg_addr = DESS_VRF_ENTRY_MASK_ADDR + (vrf_id << 3); - HSL_REG_ENTRY_GEN_SET(rv, dev_id, reg_addr, sizeof (a_uint32_t), - (a_uint8_t *) (&addr), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - - return rv; -} - -static sw_error_t -_dess_ip_vrf_base_mask_get(a_uint32_t dev_id, a_uint32_t vrf_id, fal_ip4_addr_t * addr) -{ - sw_error_t rv; - a_uint32_t reg_addr; - - HSL_DEV_ID_CHECK(dev_id); - - rv = _dess_ip_feature_check(dev_id); - SW_RTN_ON_ERROR(rv); - - if (DESS_VRF_ENTRY_MAX_ID < vrf_id) - { - return SW_BAD_PARAM; - } - - reg_addr = DESS_VRF_ENTRY_MASK_ADDR + (vrf_id << 3); - HSL_REG_ENTRY_GEN_GET(rv, dev_id, reg_addr, sizeof (a_uint32_t), - (a_uint8_t *) (addr), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - - return SW_OK; -} - -static sw_error_t -_dess_ip_default_route_set(a_uint32_t dev_id, a_uint32_t droute_id, fal_default_route_t * entry) -{ - sw_error_t rv; - a_uint32_t data = 0; - a_uint32_t addr; - - HSL_DEV_ID_CHECK(dev_id); - - rv = _dess_ip_feature_check(dev_id); - SW_RTN_ON_ERROR(rv); - - if (entry->ip_version == FAL_ADDR_IPV4) - { - SW_SET_REG_BY_FIELD(IP4_DEFAULT_ROUTE_ENTRY, VALID, entry->valid, data); - SW_SET_REG_BY_FIELD(IP4_DEFAULT_ROUTE_ENTRY, VRF, entry->vrf_id, data); - SW_SET_REG_BY_FIELD(IP4_DEFAULT_ROUTE_ENTRY, ARP_WCMP_TYPE, entry->droute_type, data); - SW_SET_REG_BY_FIELD(IP4_DEFAULT_ROUTE_ENTRY, ARP_WCMP_INDEX, entry->index, data); - - addr = DESS_IP4_DEFAULT_ROUTE_TBL_ADDR + (droute_id << 2); - HSL_REG_ENTRY_GEN_SET(rv, dev_id, addr, sizeof (a_uint32_t), - (a_uint8_t *) (&data), sizeof (a_uint32_t)); - } - else - { - SW_SET_REG_BY_FIELD(IP6_DEFAULT_ROUTE_ENTRY, VALID, entry->valid, data); - SW_SET_REG_BY_FIELD(IP6_DEFAULT_ROUTE_ENTRY, VRF, entry->vrf_id, data); - SW_SET_REG_BY_FIELD(IP6_DEFAULT_ROUTE_ENTRY, ARP_WCMP_TYPE, entry->droute_type, data); - SW_SET_REG_BY_FIELD(IP6_DEFAULT_ROUTE_ENTRY, ARP_WCMP_INDEX, entry->index, data); - - addr = DESS_IP6_DEFAULT_ROUTE_TBL_ADDR + (droute_id << 2); - HSL_REG_ENTRY_GEN_SET(rv, dev_id, addr, sizeof (a_uint32_t), - (a_uint8_t *) (&data), sizeof (a_uint32_t)); - } - - return rv; -} - -static sw_error_t -_dess_ip_default_route_get(a_uint32_t dev_id, a_uint32_t droute_id, fal_default_route_t * entry) -{ - sw_error_t rv; - a_uint32_t data = 0; - a_uint32_t addr; - - HSL_DEV_ID_CHECK(dev_id); - - rv = _dess_ip_feature_check(dev_id); - SW_RTN_ON_ERROR(rv); - - if (entry->ip_version == FAL_ADDR_IPV4) - { - addr = DESS_IP4_DEFAULT_ROUTE_TBL_ADDR + (droute_id << 2); - HSL_REG_ENTRY_GEN_GET(rv, dev_id, addr, sizeof (a_uint32_t), - (a_uint8_t *) (&data), sizeof (a_uint32_t)); - - SW_GET_FIELD_BY_REG(IP4_DEFAULT_ROUTE_ENTRY, VALID, entry->valid, data); - SW_GET_FIELD_BY_REG(IP4_DEFAULT_ROUTE_ENTRY, VRF, entry->vrf_id, data); - SW_GET_FIELD_BY_REG(IP4_DEFAULT_ROUTE_ENTRY, ARP_WCMP_TYPE, entry->droute_type, data); - SW_GET_FIELD_BY_REG(IP4_DEFAULT_ROUTE_ENTRY, ARP_WCMP_INDEX, entry->index, data); - } - else - { - addr = DESS_IP6_DEFAULT_ROUTE_TBL_ADDR + (droute_id << 2); - HSL_REG_ENTRY_GEN_GET(rv, dev_id, addr, sizeof (a_uint32_t), - (a_uint8_t *) (&data), sizeof (a_uint32_t)); - - SW_GET_FIELD_BY_REG(IP6_DEFAULT_ROUTE_ENTRY, VALID, entry->valid, data); - SW_GET_FIELD_BY_REG(IP6_DEFAULT_ROUTE_ENTRY, VRF, entry->vrf_id, data); - SW_GET_FIELD_BY_REG(IP6_DEFAULT_ROUTE_ENTRY, ARP_WCMP_TYPE, entry->droute_type, data); - SW_GET_FIELD_BY_REG(IP6_DEFAULT_ROUTE_ENTRY, ARP_WCMP_INDEX, entry->index, data); - } - - return SW_OK; -} - -static sw_error_t -_dess_ip_host_route_set(a_uint32_t dev_id, a_uint32_t hroute_id, fal_host_route_t * entry) -{ - sw_error_t rv; - a_uint32_t j, addr, tbl[5] = { 0 }; - a_uint32_t addr0_low, addr0_high, addr1_low, addr1_high, - addr2_low, addr2_high, addr3_low, addr3_high; - - HSL_DEV_ID_CHECK(dev_id); - - rv = _dess_ip_feature_check(dev_id); - SW_RTN_ON_ERROR(rv); - - if (entry->ip_version == FAL_ADDR_IPV4) - { - addr0_low = entry->route_addr.ip4_addr & 0x7ffffff; - addr0_high = entry->route_addr.ip4_addr >> 27; - SW_SET_REG_BY_FIELD(IP4_HOST_ROUTE_ENTRY0, PREFIX_LENGTH, entry->prefix_length, - tbl[0]); - SW_SET_REG_BY_FIELD(IP4_HOST_ROUTE_ENTRY0, IP4_ADDRL, addr0_low, tbl[0]); - SW_SET_REG_BY_FIELD(IP4_HOST_ROUTE_ENTRY1, IP4_ADDRH, addr0_high, tbl[1]); - SW_SET_REG_BY_FIELD(IP4_HOST_ROUTE_ENTRY1, VALID, entry->valid, - tbl[1]); - SW_SET_REG_BY_FIELD(IP4_HOST_ROUTE_ENTRY1, VRF, entry->vrf_id, - tbl[1]); - for (j = 0; j < 2; j++) - { - addr = DESS_IP4_HOST_ROUTE_TBL0_ADDR + (hroute_id << 4) + (j << 2); - HSL_REG_ENTRY_GEN_SET(rv, dev_id, addr, sizeof (a_uint32_t), - (a_uint8_t *) (&(tbl[j])), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - } - } - else - { - addr0_low = entry->route_addr.ip6_addr.ul[3] & 0x1ffffff; - addr0_high = (entry->route_addr.ip6_addr.ul[3] >> 25) & 0x7f; - addr1_low = entry->route_addr.ip6_addr.ul[2] & 0x1ffffff; - addr1_high = (entry->route_addr.ip6_addr.ul[2] >> 25) & 0x7f; - addr2_low = entry->route_addr.ip6_addr.ul[1] & 0x1ffffff; - addr2_high = (entry->route_addr.ip6_addr.ul[1] >> 25) & 0x7f; - addr3_low = entry->route_addr.ip6_addr.ul[0] & 0x1ffffff; - addr3_high = (entry->route_addr.ip6_addr.ul[0] >> 25) & 0x7f; - - SW_SET_REG_BY_FIELD(IP6_HOST_ROUTE_ENTRY0, IP6_ADDR0L, addr0_low, tbl[0]); - SW_SET_REG_BY_FIELD(IP6_HOST_ROUTE_ENTRY0, PREFIX_LENGTH, entry->prefix_length, tbl[0]); - - SW_SET_REG_BY_FIELD(IP6_HOST_ROUTE_ENTRY1, IP6_ADDR1L, addr1_low, tbl[1]); - SW_SET_REG_BY_FIELD(IP6_HOST_ROUTE_ENTRY1, IP6_ADDR0H, addr0_high, tbl[1]); - - SW_SET_REG_BY_FIELD(IP6_HOST_ROUTE_ENTRY2, IP6_ADDR2L, addr2_low, tbl[2]); - SW_SET_REG_BY_FIELD(IP6_HOST_ROUTE_ENTRY2, IP6_ADDR1H, addr1_high, tbl[2]); - - SW_SET_REG_BY_FIELD(IP6_HOST_ROUTE_ENTRY3, IP6_ADDR3L, addr3_low, tbl[3]); - SW_SET_REG_BY_FIELD(IP6_HOST_ROUTE_ENTRY3, IP6_ADDR2H, addr2_high, tbl[3]); - - SW_SET_REG_BY_FIELD(IP6_HOST_ROUTE_ENTRY4, VALID, entry->valid, tbl[4]); - SW_SET_REG_BY_FIELD(IP6_HOST_ROUTE_ENTRY4, VRF, entry->vrf_id, tbl[4]); - SW_SET_REG_BY_FIELD(IP6_HOST_ROUTE_ENTRY4, IP6_ADDR3H, addr3_high, tbl[4]); - - for (j = 0; j < 5; j++) - { - addr = DESS_IP6_HOST_ROUTE_TBL0_ADDR + (hroute_id << 5) + (j << 2); - HSL_REG_ENTRY_GEN_SET(rv, dev_id, addr, sizeof (a_uint32_t), - (a_uint8_t *) (&(tbl[j])), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - } - } - - return SW_OK; -} - -static sw_error_t -_dess_ip_host_route_get(a_uint32_t dev_id, a_uint32_t hroute_id, fal_host_route_t * entry) -{ - sw_error_t rv; - a_uint32_t j, addr, tbl[5] = { 0 }; - a_uint32_t addr0_low, addr0_high, addr1_low, addr1_high, - addr2_low, addr2_high, addr3_low, addr3_high; - - HSL_DEV_ID_CHECK(dev_id); - - rv = _dess_ip_feature_check(dev_id); - SW_RTN_ON_ERROR(rv); - - if (entry->ip_version == FAL_ADDR_IPV4) - { - for (j = 0; j < 2; j++) - { - addr = DESS_IP4_HOST_ROUTE_TBL0_ADDR + (hroute_id << 4) + (j << 2); - HSL_REG_ENTRY_GEN_GET(rv, dev_id, addr, sizeof (a_uint32_t), - (a_uint8_t *) (&(tbl[j])), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - } - SW_GET_FIELD_BY_REG(IP4_HOST_ROUTE_ENTRY0, PREFIX_LENGTH, entry->prefix_length, - tbl[0]); - SW_GET_FIELD_BY_REG(IP4_HOST_ROUTE_ENTRY0, IP4_ADDRL, addr0_low, - tbl[0]); - SW_GET_FIELD_BY_REG(IP4_HOST_ROUTE_ENTRY1, IP4_ADDRH, addr0_high, - tbl[1]); - SW_GET_FIELD_BY_REG(IP4_HOST_ROUTE_ENTRY1, VALID, entry->valid, - tbl[1]); - SW_GET_FIELD_BY_REG(IP4_HOST_ROUTE_ENTRY1, VRF, entry->vrf_id, - tbl[1]); - entry->route_addr.ip4_addr = addr0_low | (addr0_high << 27); - } - else - { - for (j = 0; j < 5; j++) - { - addr = DESS_IP6_HOST_ROUTE_TBL0_ADDR + (hroute_id << 5) + (j << 2); - HSL_REG_ENTRY_GEN_GET(rv, dev_id, addr, sizeof (a_uint32_t), - (a_uint8_t *) (&(tbl[j])), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - } - - SW_GET_FIELD_BY_REG(IP6_HOST_ROUTE_ENTRY0, IP6_ADDR0L, addr0_low, tbl[0]); - SW_GET_FIELD_BY_REG(IP6_HOST_ROUTE_ENTRY0, PREFIX_LENGTH, entry->prefix_length, tbl[0]); - SW_GET_FIELD_BY_REG(IP6_HOST_ROUTE_ENTRY1, IP6_ADDR1L, addr1_low, tbl[1]); - SW_GET_FIELD_BY_REG(IP6_HOST_ROUTE_ENTRY1, IP6_ADDR0H, addr0_high, tbl[1]); - SW_GET_FIELD_BY_REG(IP6_HOST_ROUTE_ENTRY2, IP6_ADDR2L, addr2_low, tbl[2]); - SW_GET_FIELD_BY_REG(IP6_HOST_ROUTE_ENTRY2, IP6_ADDR1H, addr1_high, tbl[2]); - SW_GET_FIELD_BY_REG(IP6_HOST_ROUTE_ENTRY3, IP6_ADDR3L, addr3_low, tbl[3]); - SW_GET_FIELD_BY_REG(IP6_HOST_ROUTE_ENTRY3, IP6_ADDR2H, addr2_high, tbl[3]); - SW_GET_FIELD_BY_REG(IP6_HOST_ROUTE_ENTRY4, VRF, entry->vrf_id, tbl[4]); - SW_GET_FIELD_BY_REG(IP6_HOST_ROUTE_ENTRY4, IP6_ADDR3H, addr3_high, tbl[4]); - SW_GET_FIELD_BY_REG(IP6_HOST_ROUTE_ENTRY4, VALID, entry->valid, tbl[4]); - entry->route_addr.ip6_addr.ul[3] = (addr0_high << 25) | addr0_low; - entry->route_addr.ip6_addr.ul[2] = (addr1_high << 25) | addr1_low; - entry->route_addr.ip6_addr.ul[1] = (addr2_high << 25) | addr2_low; - entry->route_addr.ip6_addr.ul[0] = (addr3_high << 25) | addr3_low; - } - - return SW_OK; -} - -#define RFS_ADD_OP 1 -#define RFS_DEL_OP 2 -static sw_error_t -_dess_ip_rfs_ip4_update( - a_uint32_t dev_id, - fal_host_entry_t *entry, - fal_ip4_rfs_t * rfs, - char op) -{ - fal_host_entry_t tmp = *entry; - - _dess_ip_host_del(dev_id, FAL_IP_ENTRY_IPADDR_EN, entry); - if(RFS_ADD_OP == op) { - tmp.lb_num = rfs->load_balance | 0x4; - tmp.status = 0x7; - } - else { - tmp.lb_num = 0; - tmp.status = 0x6; - } - return _dess_ip_host_add(dev_id, &tmp); -} - -static sw_error_t -_dess_ip_rfs_ip6_update( - a_uint32_t dev_id, - fal_host_entry_t *entry, - fal_ip6_rfs_t * rfs, - char op) -{ - fal_host_entry_t tmp = *entry; - - _dess_ip_host_del(dev_id, FAL_IP_ENTRY_IPADDR_EN, entry); - if(RFS_ADD_OP == op) { - tmp.lb_num = rfs->load_balance | 0x4; - tmp.status = 0x7; - } - else { - tmp.lb_num = 0; - tmp.status = 0x6; - } - return _dess_ip_host_add(dev_id, &tmp); -} - -static sw_error_t -_dess_ip_rfs_ip4_set(a_uint32_t dev_id, fal_ip4_rfs_t * rfs) -{ - fal_host_entry_t entry; - - memset(&entry, 0, sizeof(entry)); - entry.flags = FAL_IP_IP4_ADDR; - entry.ip4_addr = rfs->ip4_addr; - if(SW_OK == _dess_ip_host_get(dev_id, 0x10, &entry)) { - return _dess_ip_rfs_ip4_update(dev_id, &entry, rfs, RFS_ADD_OP); - } - /*add a new one*/ - entry.status = 0x7; - entry.flags = FAL_IP_IP4_ADDR; - entry.ip4_addr = rfs->ip4_addr; - memcpy(&entry.mac_addr, &rfs->mac_addr, 6); - entry.intf_id = rfs->vid; - entry.port_id = 0; - entry.lb_num = rfs->load_balance | 0x4; - entry.action = FAL_MAC_RDT_TO_CPU; - return _dess_ip_host_add(dev_id, &entry); -} - -static sw_error_t -_dess_ip_rfs_ip6_set(a_uint32_t dev_id, fal_ip6_rfs_t * rfs) -{ - fal_host_entry_t entry; - - memset(&entry, 0, sizeof(entry)); - entry.flags = FAL_IP_IP6_ADDR; - entry.ip6_addr = rfs->ip6_addr; - if(SW_OK == _dess_ip_host_get(dev_id, 0x10, &entry)) { - return _dess_ip_rfs_ip6_update(dev_id, &entry, rfs, RFS_ADD_OP); - } - /*add a new one*/ - entry.status = 0x7; - entry.flags = FAL_IP_IP6_ADDR; - entry.ip6_addr = rfs->ip6_addr; - memcpy(&entry.mac_addr, &rfs->mac_addr, 6); - entry.intf_id = rfs->vid; - entry.port_id = 0; - entry.lb_num = rfs->load_balance | 0x4; - entry.action = FAL_MAC_RDT_TO_CPU; - return _dess_ip_host_add(dev_id, &entry); -} - -static sw_error_t -_dess_ip_rfs_ip4_del(a_uint32_t dev_id, fal_ip4_rfs_t * rfs) -{ - fal_host_entry_t entry; - sw_error_t ret; - - memset(&entry, 0, sizeof(entry)); - entry.flags = FAL_IP_IP4_ADDR; - entry.ip4_addr = rfs->ip4_addr; - if(SW_OK == (ret = _dess_ip_host_get(dev_id, 0x10, &entry))) { - return _dess_ip_rfs_ip4_update(dev_id, &entry, rfs, RFS_DEL_OP); - } - return ret; -} - -static sw_error_t -_dess_ip_rfs_ip6_del(a_uint32_t dev_id, fal_ip6_rfs_t * rfs) -{ - fal_host_entry_t entry; - sw_error_t ret; - - memset(&entry, 0, sizeof(entry)); - entry.flags = FAL_IP_IP6_ADDR; - entry.ip6_addr = rfs->ip6_addr; - if(SW_OK == (ret = _dess_ip_host_get(dev_id, 0x10, &entry))) { - return _dess_ip_rfs_ip6_update(dev_id, &entry, rfs, RFS_DEL_OP); - } - return ret; -} - -static sw_error_t -_dess_default_flow_cmd_set(a_uint32_t dev_id, a_uint32_t vrf_id, fal_flow_type_t type, fal_default_flow_cmd_t cmd) -{ - sw_error_t rv; - a_uint32_t data; - - HSL_DEV_ID_CHECK(dev_id); - - rv = _dess_ip_feature_check(dev_id); - SW_RTN_ON_ERROR(rv); - - if (FAL_DEFAULT_FLOW_FORWARD == cmd) - { - data = 0; - } - else if (FAL_DEFAULT_FLOW_DROP == cmd) - { - data = 1; - } - else if (FAL_DEFAULT_FLOW_RDT_TO_CPU == cmd) - { - data = 2; - } - else if (FAL_DEFAULT_FLOW_ADMIT_ALL == cmd) - { - data = 3; - } - else - { - return SW_NOT_SUPPORTED; - } - - if (FAL_FLOW_LAN_TO_LAN == type) - { - HSL_REG_FIELD_SET(rv, dev_id, FlOW_CMD_CTL, vrf_id, LAN_2_LAN_DEFAULT, - (a_uint8_t *) (&data), sizeof (a_uint32_t)); - } - else if (FAL_FLOW_WAN_TO_LAN == type) - { - HSL_REG_FIELD_SET(rv, dev_id, FlOW_CMD_CTL, vrf_id, WAN_2_LAN_DEFAULT, - (a_uint8_t *) (&data), sizeof (a_uint32_t)); - } - else if (FAL_FLOW_LAN_TO_WAN == type) - { - HSL_REG_FIELD_SET(rv, dev_id, FlOW_CMD_CTL, vrf_id, LAN_2_WAN_DEFAULT, - (a_uint8_t *) (&data), sizeof (a_uint32_t)); - } - else if (FAL_FLOW_WAN_TO_WAN == type) - { - HSL_REG_FIELD_SET(rv, dev_id, FlOW_CMD_CTL, vrf_id, WAN_2_WAN_DEFAULT, - (a_uint8_t *) (&data), sizeof (a_uint32_t)); - } - else - { - return SW_NOT_SUPPORTED; - } - - return rv; -} - -static sw_error_t -_dess_default_flow_cmd_get(a_uint32_t dev_id, a_uint32_t vrf_id, fal_flow_type_t type, fal_default_flow_cmd_t * cmd) -{ - sw_error_t rv; - a_uint32_t data = 0; - - HSL_DEV_ID_CHECK(dev_id); - - rv = _dess_ip_feature_check(dev_id); - SW_RTN_ON_ERROR(rv); - - if (FAL_FLOW_LAN_TO_LAN == type) - { - HSL_REG_FIELD_GET(rv, dev_id, FlOW_CMD_CTL, vrf_id, LAN_2_LAN_DEFAULT, - (a_uint8_t *) (&data), sizeof (a_uint32_t)); - } - else if (FAL_FLOW_WAN_TO_LAN == type) - { - HSL_REG_FIELD_GET(rv, dev_id, FlOW_CMD_CTL, vrf_id, WAN_2_LAN_DEFAULT, - (a_uint8_t *) (&data), sizeof (a_uint32_t)); - } - else if (FAL_FLOW_LAN_TO_WAN == type) - { - HSL_REG_FIELD_GET(rv, dev_id, FlOW_CMD_CTL, vrf_id, LAN_2_WAN_DEFAULT, - (a_uint8_t *) (&data), sizeof (a_uint32_t)); - } - else if (FAL_FLOW_WAN_TO_WAN == type) - { - HSL_REG_FIELD_GET(rv, dev_id, FlOW_CMD_CTL, vrf_id, WAN_2_WAN_DEFAULT, - (a_uint8_t *) (&data), sizeof (a_uint32_t)); - } - else - { - return SW_NOT_SUPPORTED; - } - SW_RTN_ON_ERROR(rv); - - if (0 == data) - { - *cmd = FAL_DEFAULT_FLOW_FORWARD; - } - else if (1 == data) - { - *cmd = FAL_DEFAULT_FLOW_DROP; - } - else if (2 == data) - { - *cmd = FAL_DEFAULT_FLOW_RDT_TO_CPU; - } - else if (3 == data) - { - *cmd = FAL_DEFAULT_FLOW_ADMIT_ALL; - } - - return SW_OK; -} - -static sw_error_t -_dess_default_rt_flow_cmd_set(a_uint32_t dev_id, a_uint32_t vrf_id, fal_flow_type_t type, fal_default_flow_cmd_t cmd) -{ - sw_error_t rv; - a_uint32_t data; - - HSL_DEV_ID_CHECK(dev_id); - - rv = _dess_ip_feature_check(dev_id); - SW_RTN_ON_ERROR(rv); - - if (FAL_DEFAULT_FLOW_FORWARD == cmd) - { - data = 0; - } - else if (FAL_DEFAULT_FLOW_DROP == cmd) - { - data = 1; - } - else if (FAL_DEFAULT_FLOW_RDT_TO_CPU == cmd) - { - data = 2; - } - else if (FAL_DEFAULT_FLOW_ADMIT_ALL == cmd) - { - data = 3; - } - else - { - return SW_NOT_SUPPORTED; - } - - if (FAL_FLOW_LAN_TO_LAN == type) - { - HSL_REG_FIELD_SET(rv, dev_id, FlOW_RT_CMD_CTL, vrf_id, LAN_2_LAN_DEFAULT, - (a_uint8_t *) (&data), sizeof (a_uint32_t)); - } - else if (FAL_FLOW_WAN_TO_LAN == type) - { - HSL_REG_FIELD_SET(rv, dev_id, FlOW_RT_CMD_CTL, vrf_id, WAN_2_LAN_DEFAULT, - (a_uint8_t *) (&data), sizeof (a_uint32_t)); - } - else if (FAL_FLOW_LAN_TO_WAN == type) - { - HSL_REG_FIELD_SET(rv, dev_id, FlOW_RT_CMD_CTL, vrf_id, LAN_2_WAN_DEFAULT, - (a_uint8_t *) (&data), sizeof (a_uint32_t)); - } - else if (FAL_FLOW_WAN_TO_WAN == type) - { - HSL_REG_FIELD_SET(rv, dev_id, FlOW_RT_CMD_CTL, vrf_id, WAN_2_WAN_DEFAULT, - (a_uint8_t *) (&data), sizeof (a_uint32_t)); - } - else - { - return SW_NOT_SUPPORTED; - } - - return rv; -} - -static sw_error_t -_dess_default_rt_flow_cmd_get(a_uint32_t dev_id, a_uint32_t vrf_id, fal_flow_type_t type, fal_default_flow_cmd_t * cmd) -{ - sw_error_t rv; - a_uint32_t data = 0; - - HSL_DEV_ID_CHECK(dev_id); - - rv = _dess_ip_feature_check(dev_id); - SW_RTN_ON_ERROR(rv); - - if (FAL_FLOW_LAN_TO_LAN == type) - { - HSL_REG_FIELD_GET(rv, dev_id, FlOW_RT_CMD_CTL, vrf_id, LAN_2_LAN_DEFAULT, - (a_uint8_t *) (&data), sizeof (a_uint32_t)); - } - else if (FAL_FLOW_WAN_TO_LAN == type) - { - HSL_REG_FIELD_GET(rv, dev_id, FlOW_RT_CMD_CTL, vrf_id, WAN_2_LAN_DEFAULT, - (a_uint8_t *) (&data), sizeof (a_uint32_t)); - } - else if (FAL_FLOW_LAN_TO_WAN == type) - { - HSL_REG_FIELD_GET(rv, dev_id, FlOW_RT_CMD_CTL, vrf_id, LAN_2_WAN_DEFAULT, - (a_uint8_t *) (&data), sizeof (a_uint32_t)); - } - else if (FAL_FLOW_WAN_TO_WAN == type) - { - HSL_REG_FIELD_GET(rv, dev_id, FlOW_RT_CMD_CTL, vrf_id, WAN_2_WAN_DEFAULT, - (a_uint8_t *) (&data), sizeof (a_uint32_t)); - } - else - { - return SW_NOT_SUPPORTED; - } - SW_RTN_ON_ERROR(rv); - - if (0 == data) - { - *cmd = FAL_DEFAULT_FLOW_FORWARD; - } - else if (1 == data) - { - *cmd = FAL_DEFAULT_FLOW_DROP; - } - else if (2 == data) - { - *cmd = FAL_DEFAULT_FLOW_RDT_TO_CPU; - } - else if (3 == data) - { - *cmd = FAL_DEFAULT_FLOW_ADMIT_ALL; - } - - return SW_OK; -} - -static sw_error_t -_dess_ip_glb_lock_time_set(a_uint32_t dev_id, fal_glb_lock_time_t lock_time) -{ - sw_error_t rv; - a_uint32_t data = lock_time; - - HSL_REG_FIELD_SET(rv, dev_id, ROUTER_CTRL, 0, GLB_LOCKTIME, - (a_uint8_t *) (&data), sizeof (a_uint32_t)); - return rv; -} - -sw_error_t -dess_ip_reset(a_uint32_t dev_id) -{ - sw_error_t rv; - a_uint32_t i, addr, data = 0; - - HSL_DEV_ID_CHECK(dev_id); - - rv = _dess_ip_feature_check(dev_id); - SW_RTN_ON_ERROR(rv); - - HSL_REG_ENTRY_SET(rv, dev_id, HOST_ENTRY7, 0, (a_uint8_t *) (&data), - sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - - rv = _dess_host_entry_commit(dev_id, DESS_ENTRY_ARP, DESS_HOST_ENTRY_FLUSH); - SW_RTN_ON_ERROR(rv); - - dess_mac_snap[dev_id] = 0; - for (i = 0; i < DESS_INTF_MAC_ADDR_NUM; i++) - { - addr = DESS_INTF_MAC_TBL2_ADDR + (i << 4); - HSL_REG_ENTRY_GEN_SET(rv, dev_id, addr, sizeof (a_uint32_t), - (a_uint8_t *) (&data), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - } - - return SW_OK; -} - -/** - * @brief Add one host entry to one particular device. - * @details Comments: - * For ISIS the intf_id parameter in host_entry means vlan id. - Before host entry added related interface entry and ip6 base address - must be set at first. - Hardware entry id will be returned. - * @param[in] dev_id device id - * @param[in] host_entry host entry parameter - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -dess_ip_host_add(a_uint32_t dev_id, fal_host_entry_t * host_entry) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _dess_ip_host_add(dev_id, host_entry); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Delete one host entry from one particular device. - * @details Comments: - * For ISIS the intf_id parameter in host_entry means vlan id. - Before host entry deleted related interface entry and ip6 base address - must be set atfirst. - For del_mode please refer IP entry operation flags. - * @param[in] dev_id device id - * @param[in] del_mode delete operation mode - * @param[in] host_entry host entry parameter - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -dess_ip_host_del(a_uint32_t dev_id, a_uint32_t del_mode, - fal_host_entry_t * host_entry) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _dess_ip_host_del(dev_id, del_mode, host_entry); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Get one host entry from one particular device. - * @details Comments: - * For ISIS the intf_id parameter in host_entry means vlan id. - Before host entry deleted related interface entry and ip6 base address - must be set atfirst. - For get_mode please refer IP entry operation flags. - * @param[in] dev_id device id - * @param[in] get_mode get operation mode - * @param[out] host_entry host entry parameter - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -dess_ip_host_get(a_uint32_t dev_id, a_uint32_t get_mode, - fal_host_entry_t * host_entry) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _dess_ip_host_get(dev_id, get_mode, host_entry); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Next one host entry from one particular device. - * @details Comments: - * For ISIS the intf_id parameter in host_entry means vlan id. - Before host entry deleted related interface entry and ip6 base address - must be set atfirst. - For next_mode please refer IP entry operation flags. - For get the first entry please set entry id as FAL_NEXT_ENTRY_FIRST_ID - * @param[in] dev_id device id - * @param[in] next_mode next operation mode - * @param[out] host_entry host entry parameter - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -dess_ip_host_next(a_uint32_t dev_id, a_uint32_t next_mode, - fal_host_entry_t * host_entry) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _dess_ip_host_next(dev_id, next_mode, host_entry); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Bind one counter entry to one host entry on one particular device. - * @param[in] dev_id device id - * @param[in] entry_id host entry id - * @param[in] cnt_id counter entry id - * @param[in] enable A_TRUE means bind, A_FALSE means unbind - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -dess_ip_host_counter_bind(a_uint32_t dev_id, a_uint32_t entry_id, - a_uint32_t cnt_id, a_bool_t enable) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _dess_ip_host_counter_bind(dev_id, entry_id, cnt_id, enable); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Bind one pppoe session entry to one host entry on one particular device. - * @param[in] dev_id device id - * @param[in] entry_id host entry id - * @param[in] pppoe_id pppoe session entry id - * @param[in] enable A_TRUE means bind, A_FALSE means unbind - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -dess_ip_host_pppoe_bind(a_uint32_t dev_id, a_uint32_t entry_id, - a_uint32_t pppoe_id, a_bool_t enable) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _dess_ip_host_pppoe_bind(dev_id, entry_id, pppoe_id, enable); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Set arp packets type to learn on one particular port. - * @param[in] dev_id device id - * @param[in] port_id port id - * @param[in] flags arp type FAL_ARP_LEARN_REQ and/or FAL_ARP_LEARN_ACK - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -dess_ip_pt_arp_learn_set(a_uint32_t dev_id, fal_port_t port_id, - a_uint32_t flags) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _dess_ip_pt_arp_learn_set(dev_id, port_id, flags); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Get arp packets type to learn on one particular port. - * @param[in] dev_id device id - * @param[in] port_id port id - * @param[out] flags arp type FAL_ARP_LEARN_REQ and/or FAL_ARP_LEARN_ACK - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -dess_ip_pt_arp_learn_get(a_uint32_t dev_id, fal_port_t port_id, - a_uint32_t * flags) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _dess_ip_pt_arp_learn_get(dev_id, port_id, flags); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Set arp packets type to learn on one particular device. - * @param[in] dev_id device id - * @param[in] mode learning mode - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -dess_ip_arp_learn_set(a_uint32_t dev_id, fal_arp_learn_mode_t mode) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _dess_ip_arp_learn_set(dev_id, mode); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Get arp packets type to learn on one particular device. - * @param[in] dev_id device id - * @param[out] mode learning mode - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -dess_ip_arp_learn_get(a_uint32_t dev_id, fal_arp_learn_mode_t * mode) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _dess_ip_arp_learn_get(dev_id, mode); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Set ip packets source guarding mode on one particular port. - * @param[in] dev_id device id - * @param[in] port_id port id - * @param[in] mode source guarding mode - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -dess_ip_source_guard_set(a_uint32_t dev_id, fal_port_t port_id, - fal_source_guard_mode_t mode) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _dess_ip_source_guard_set(dev_id, port_id, mode); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Get ip packets source guarding mode on one particular port. - * @param[in] dev_id device id - * @param[in] port_id port id - * @param[out] mode source guarding mode - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -dess_ip_source_guard_get(a_uint32_t dev_id, fal_port_t port_id, - fal_source_guard_mode_t * mode) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _dess_ip_source_guard_get(dev_id, port_id, mode); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Set unkonw source ip packets forwarding command on one particular device. - * @details Comments: - * This settin is no meaning when ip source guard not enable - * @param[in] dev_id device id - * @param[in] cmd forwarding command - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -dess_ip_unk_source_cmd_set(a_uint32_t dev_id, fal_fwd_cmd_t cmd) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _dess_ip_unk_source_cmd_set(dev_id, cmd); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Get unkonw source ip packets forwarding command on one particular device. - * @param[in] dev_id device id - * @param[out] cmd forwarding command - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -dess_ip_unk_source_cmd_get(a_uint32_t dev_id, fal_fwd_cmd_t * cmd) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _dess_ip_unk_source_cmd_get(dev_id, cmd); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Set arp packets source guarding mode on one particular port. - * @param[in] dev_id device id - * @param[in] port_id port id - * @param[in] mode source guarding mode - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -dess_ip_arp_guard_set(a_uint32_t dev_id, fal_port_t port_id, - fal_source_guard_mode_t mode) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _dess_ip_arp_guard_set(dev_id, port_id, mode); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Get arp packets source guarding mode on one particular port. - * @param[in] dev_id device id - * @param[in] port_id port id - * @param[out] mode source guarding mode - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -dess_ip_arp_guard_get(a_uint32_t dev_id, fal_port_t port_id, - fal_source_guard_mode_t * mode) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _dess_ip_arp_guard_get(dev_id, port_id, mode); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Set unkonw source arp packets forwarding command on one particular device. - * @details Comments: - * This settin is no meaning when arp source guard not enable - * @param[in] dev_id device id - * @param[in] cmd forwarding command - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -dess_arp_unk_source_cmd_set(a_uint32_t dev_id, fal_fwd_cmd_t cmd) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _dess_arp_unk_source_cmd_set(dev_id, cmd); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Get unkonw source arp packets forwarding command on one particular device. - * @param[in] dev_id device id - * @param[out] cmd forwarding command - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -dess_arp_unk_source_cmd_get(a_uint32_t dev_id, fal_fwd_cmd_t * cmd) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _dess_arp_unk_source_cmd_get(dev_id, cmd); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Set IP unicast routing status on one particular device. - * @param[in] dev_id device id - * @param[in] enable A_TRUE or A_FALSE - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -dess_ip_route_status_set(a_uint32_t dev_id, a_bool_t enable) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _dess_ip_route_status_set(dev_id, enable); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Get IP unicast routing status on one particular device. - * @param[in] dev_id device id - * @param[out] enable A_TRUE or A_FALSE - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -dess_ip_route_status_get(a_uint32_t dev_id, a_bool_t * enable) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _dess_ip_route_status_get(dev_id, enable); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Add one interface entry to one particular device. - * @param[in] dev_id device id - * @param[in] entry interface entry - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -dess_ip_intf_entry_add(a_uint32_t dev_id, fal_intf_mac_entry_t * entry) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _dess_ip_intf_entry_add(dev_id, entry); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Delete one interface entry from one particular device. - * @param[in] dev_id device id - * @param[in] del_mode delete operation mode - * @param[in] entry interface entry - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -dess_ip_intf_entry_del(a_uint32_t dev_id, a_uint32_t del_mode, - fal_intf_mac_entry_t * entry) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _dess_ip_intf_entry_del(dev_id, del_mode, entry); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Next one interface entry from one particular device. - * @param[in] dev_id device id - * @param[in] next_mode next operation mode - * @param[out] entry interface entry - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -dess_ip_intf_entry_next(a_uint32_t dev_id, a_uint32_t next_mode, - fal_intf_mac_entry_t * entry) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _dess_ip_intf_entry_next(dev_id, next_mode, entry); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Set IP host entry aging time on one particular device. - * @details Comments: - * This operation will set dynamic entry aging time on a particular device. - * The unit of time is second. Because different device has differnet - * hardware granularity function will return actual time in hardware. - * @param[in] dev_id device id - * @param[in] time aging time - * @param[out] time actual aging time - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -dess_ip_age_time_set(a_uint32_t dev_id, a_uint32_t * time) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _dess_ip_age_time_set(dev_id, time); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Get IP host entry aging time on one particular device. - * @param[in] dev_id device id - * @param[out] time aging time - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -dess_ip_age_time_get(a_uint32_t dev_id, a_uint32_t * time) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _dess_ip_age_time_get(dev_id, time); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Set IP WCMP table one particular device. - * @details Comments: - * Hardware only support 0 - 15 hash values and 4 different host tables. - * @param[in] dev_id device id - * @param[in] wcmp_id wcmp entry id - * @param[in] wcmp wcmp entry - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -dess_ip_wcmp_entry_set(a_uint32_t dev_id, a_uint32_t wcmp_id, fal_ip_wcmp_t * wcmp) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _dess_ip_wcmp_entry_set(dev_id, wcmp_id, wcmp); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Get IP WCMP table one particular device. - * @details Comments: - * Hardware only support 0 - 15 hash values and 4 different host tables. - * @param[in] dev_id device id - * @param[in] wcmp_id wcmp entry id - * @param[out] wcmp wcmp entry - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -dess_ip_wcmp_entry_get(a_uint32_t dev_id, a_uint32_t wcmp_id, fal_ip_wcmp_t * wcmp) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _dess_ip_wcmp_entry_get(dev_id, wcmp_id, wcmp); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Set IP WCMP hash key mode. - * @param[in] dev_id device id - * @param[in] hash_mode hash mode - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -dess_ip_wcmp_hash_mode_set(a_uint32_t dev_id, a_uint32_t hash_mode) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _dess_ip_wcmp_hash_mode_set(dev_id, hash_mode); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Get IP WCMP hash key mode. - * @param[in] dev_id device id - * @param[out] hash_mode hash mode - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -dess_ip_wcmp_hash_mode_get(a_uint32_t dev_id, a_uint32_t * hash_mode) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _dess_ip_wcmp_hash_mode_get(dev_id, hash_mode); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Set IP VRF base IP address. - * @param[in] dev_id device id - * @param[in] vrf_id VRF route index, from 0~7 - * @param[in] fal_ip4_addr_t IPv4 address for this VRF route - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -dess_ip_vrf_base_addr_set(a_uint32_t dev_id, a_uint32_t vrf_id, fal_ip4_addr_t addr) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _dess_ip_vrf_base_addr_set(dev_id, vrf_id, addr); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Get IP VRF base IP address. - * @param[in] dev_id device id - * @param[in] vrf_id VRF route index, from 0~7 - * @param[out] fal_ip4_addr_t IPv4 address for this VRF route - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -dess_ip_vrf_base_addr_get(a_uint32_t dev_id, a_uint32_t vrf_id, fal_ip4_addr_t * addr) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _dess_ip_vrf_base_addr_get(dev_id, vrf_id, addr); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Set IP VRF base IP address mask. - * @param[in] dev_id device id - * @param[in] vrf_id VRF route index, from 0~7 - * @param[in] fal_ip4_addr_t IPv4 address mask for this VRF route - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -dess_ip_vrf_base_mask_set(a_uint32_t dev_id, a_uint32_t vrf_id, fal_ip4_addr_t addr) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _dess_ip_vrf_base_mask_set(dev_id, vrf_id, addr); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Get IP VRF base IP address mask. - * @param[in] dev_id device id - * @param[in] vrf_id VRF route index, from 0~7 - * @param[out] fal_ip4_addr_t IPv4 address mask for this VRF route - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -dess_ip_vrf_base_mask_get(a_uint32_t dev_id, a_uint32_t vrf_id, fal_ip4_addr_t * addr) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _dess_ip_vrf_base_mask_get(dev_id, vrf_id, addr); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Set IP default route entry with special default route id. - * @param[in] dev_id device id - * @param[in] droute_id default route index, from 0~7 - * @param[in] fal_default_route_t default route entry - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -dess_ip_default_route_set(a_uint32_t dev_id, a_uint32_t droute_id, fal_default_route_t * entry) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _dess_ip_default_route_set(dev_id, droute_id, entry); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Get IP default route entry with special default route id. - * @param[in] dev_id device id - * @param[in] droute_id default route index, from 0~7 - * @param[in] fal_default_route_t default route entry - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -dess_ip_default_route_get(a_uint32_t dev_id, a_uint32_t droute_id, fal_default_route_t * entry) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _dess_ip_default_route_get(dev_id, droute_id, entry); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Set IP host route entry with special default route id. - * @param[in] dev_id device id - * @param[in] hroute_id default route index, from 0~15 - * @param[in] fal_host_route_t host route entry - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -dess_ip_host_route_set(a_uint32_t dev_id, a_uint32_t hroute_id, fal_host_route_t * entry) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _dess_ip_host_route_set(dev_id, hroute_id, entry); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Get IP host route entry with special default route id. - * @param[in] dev_id device id - * @param[in] hroute_id default route index, from 0~15 - * @param[in] fal_host_route_t host route entry - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -dess_ip_host_route_get(a_uint32_t dev_id, a_uint32_t hroute_id, fal_host_route_t * entry) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _dess_ip_host_route_get(dev_id, hroute_id, entry); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Set IP host route load balance. - * @param[in] dev_id device id - * @param[in] fal_ip4_rfs_t host route entry - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -dess_ip_rfs_ip4_set(a_uint32_t dev_id, fal_ip4_rfs_t * rfs) -{ - sw_error_t rv; - fal_intf_mac_entry_t mac_entry; - - HSL_API_LOCK; - memset(&mac_entry, 0, sizeof(mac_entry)); - mac_entry.ip4_route = A_TRUE; - mac_entry.ip6_route = A_TRUE; - mac_entry.vid_low = rfs->vid; - mac_entry.vid_high = rfs->vid; - mac_entry.mac_addr = rfs->mac_addr; - rv = _dess_ip_intf_entry_add(dev_id, &mac_entry); - if(!rv) - rv = _dess_ip_rfs_ip4_set(dev_id, rfs); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Set IP6 host route load balance. - * @param[in] dev_id device id - * @param[in] fal_ip6_rfs_t host route entry - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -dess_ip_rfs_ip6_set(a_uint32_t dev_id, fal_ip6_rfs_t * rfs) -{ - sw_error_t rv; - fal_intf_mac_entry_t mac_entry; - - HSL_API_LOCK; - memset(&mac_entry, 0, sizeof(mac_entry)); - mac_entry.ip4_route = A_TRUE; - mac_entry.ip6_route = A_TRUE; - mac_entry.vid_low = rfs->vid; - mac_entry.vid_high = rfs->vid; - mac_entry.mac_addr = rfs->mac_addr; - rv = _dess_ip_intf_entry_add(dev_id, &mac_entry); - if(!rv) - rv = _dess_ip_rfs_ip6_set(dev_id, rfs); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief del IP host route load balance. - * @param[in] dev_id device id - * @param[in] fal_ip4_rfs_t host route entry - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -dess_ip_rfs_ip4_del(a_uint32_t dev_id, fal_ip4_rfs_t * rfs) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _dess_ip_rfs_ip4_del(dev_id, rfs); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief del IP6 host route load balance. - * @param[in] dev_id device id - * @param[in] fal_ip6_rfs_t host route entry - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -dess_ip_rfs_ip6_del(a_uint32_t dev_id, fal_ip6_rfs_t * rfs) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _dess_ip_rfs_ip6_del(dev_id, rfs); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Set flow type traffic default forward command. - * @param[in] dev_id device id - * @param[in] vrf_id VRF route index, from 0~7 - * @param[in] type traffic flow type pass through switch core - * @param[in] fal_default_flow_cmd_mode_t default flow forward command when flow table mismatch - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -dess_default_flow_cmd_set(a_uint32_t dev_id, a_uint32_t vrf_id, fal_flow_type_t type, fal_default_flow_cmd_t cmd) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _dess_default_flow_cmd_set(dev_id, vrf_id, type, cmd); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Get flow type traffic default forward command. - * @param[in] dev_id device id - * @param[in] vrf_id VRF route index, from 0~7 - * @param[in] type traffic flow type pass through switch core - * @param[out] fal_default_flow_cmd_mode_t default flow forward command when flow table mismatch - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -dess_default_flow_cmd_get(a_uint32_t dev_id, a_uint32_t vrf_id, fal_flow_type_t type, fal_default_flow_cmd_t * cmd) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _dess_default_flow_cmd_get(dev_id, vrf_id, type, cmd); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Set flow&route type traffic default forward command. - * @param[in] dev_id device id - * @param[in] vrf_id VRF route index, from 0~7 - * @param[in] type traffic flow type pass through switch core - * @param[in] fal_default_flow_cmd_mode_t default flow&route forward command when route mac match but flow table mismatch - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -dess_default_rt_flow_cmd_set(a_uint32_t dev_id, a_uint32_t vrf_id, fal_flow_type_t type, fal_default_flow_cmd_t cmd) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _dess_default_rt_flow_cmd_set(dev_id, vrf_id, type, cmd); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Get flow&route type traffic default forward command. - * @param[in] dev_id device id - * @param[in] vrf_id VRF route index, from 0~7 - * @param[in] type traffic flow type pass through switch core - * @param[in] fal_default_flow_cmd_mode_t default flow&route forward command when route mac match but flow table mismatch - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -dess_default_rt_flow_cmd_get(a_uint32_t dev_id, a_uint32_t vrf_id, fal_flow_type_t type, fal_default_flow_cmd_t * cmd) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _dess_default_rt_flow_cmd_get(dev_id, vrf_id, type, cmd); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Set blobal lock time. - * @param[in] dev_id device id - * @param[in] fal_glb_lock_time_t lock time - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -dess_ip_glb_lock_time_set(a_uint32_t dev_id, fal_glb_lock_time_t lock_time) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _dess_ip_glb_lock_time_set(dev_id, lock_time); - HSL_API_UNLOCK; - return rv; -} - -sw_error_t -dess_ip_init(a_uint32_t dev_id) -{ - sw_error_t rv; - - HSL_DEV_ID_CHECK(dev_id); - - rv = dess_ip_reset(dev_id); - SW_RTN_ON_ERROR(rv); - -#ifndef HSL_STANDALONG - { - hsl_api_t *p_api; - - SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id)); - - p_api->ip_host_add = dess_ip_host_add; - p_api->ip_host_del = dess_ip_host_del; - p_api->ip_host_get = dess_ip_host_get; - p_api->ip_host_next = dess_ip_host_next; - p_api->ip_host_counter_bind = dess_ip_host_counter_bind; - p_api->ip_host_pppoe_bind = dess_ip_host_pppoe_bind; - p_api->ip_pt_arp_learn_set = dess_ip_pt_arp_learn_set; - p_api->ip_pt_arp_learn_get = dess_ip_pt_arp_learn_get; - p_api->ip_arp_learn_set = dess_ip_arp_learn_set; - p_api->ip_arp_learn_get = dess_ip_arp_learn_get; - p_api->ip_source_guard_set = dess_ip_source_guard_set; - p_api->ip_source_guard_get = dess_ip_source_guard_get; - p_api->ip_unk_source_cmd_set = dess_ip_unk_source_cmd_set; - p_api->ip_unk_source_cmd_get = dess_ip_unk_source_cmd_get; - p_api->ip_arp_guard_set = dess_ip_arp_guard_set; - p_api->ip_arp_guard_get = dess_ip_arp_guard_get; - p_api->arp_unk_source_cmd_set = dess_arp_unk_source_cmd_set; - p_api->arp_unk_source_cmd_get = dess_arp_unk_source_cmd_get; - p_api->ip_route_status_set = dess_ip_route_status_set; - p_api->ip_route_status_get = dess_ip_route_status_get; - p_api->ip_intf_entry_add = dess_ip_intf_entry_add; - p_api->ip_intf_entry_del = dess_ip_intf_entry_del; - p_api->ip_intf_entry_next = dess_ip_intf_entry_next; - p_api->ip_age_time_set = dess_ip_age_time_set; - p_api->ip_age_time_get = dess_ip_age_time_get; - p_api->ip_wcmp_hash_mode_set = dess_ip_wcmp_hash_mode_set; - p_api->ip_wcmp_hash_mode_get = dess_ip_wcmp_hash_mode_get; - p_api->ip_vrf_base_addr_set = dess_ip_vrf_base_addr_set; - p_api->ip_vrf_base_addr_get = dess_ip_vrf_base_addr_get; - p_api->ip_vrf_base_mask_set = dess_ip_vrf_base_mask_set; - p_api->ip_vrf_base_mask_get = dess_ip_vrf_base_mask_get; - p_api->ip_default_route_set = dess_ip_default_route_set; - p_api->ip_default_route_get = dess_ip_default_route_get; - p_api->ip_host_route_set = dess_ip_host_route_set; - p_api->ip_host_route_get = dess_ip_host_route_get; - p_api->ip_wcmp_entry_set = dess_ip_wcmp_entry_set; - p_api->ip_wcmp_entry_get = dess_ip_wcmp_entry_get; - p_api->ip_rfs_ip4_set = dess_ip_rfs_ip4_set; - p_api->ip_rfs_ip6_set = dess_ip_rfs_ip6_set; - p_api->ip_rfs_ip4_del = dess_ip_rfs_ip4_del; - p_api->ip_rfs_ip6_del = dess_ip_rfs_ip6_del; - p_api->ip_default_flow_cmd_set = dess_default_flow_cmd_set; - p_api->ip_default_flow_cmd_get = dess_default_flow_cmd_get; - p_api->ip_default_rt_flow_cmd_set = dess_default_rt_flow_cmd_set; - p_api->ip_default_rt_flow_cmd_get = dess_default_rt_flow_cmd_get; - p_api->ip_glb_lock_time_set = dess_ip_glb_lock_time_set; - } -#endif - - return SW_OK; -} - -/** - * @} - */ - diff --git a/feeds/ipq807x/qca-ssdk/src/src/hsl/dess/dess_leaky.c b/feeds/ipq807x/qca-ssdk/src/src/hsl/dess/dess_leaky.c deleted file mode 100755 index 6aef5d58d..000000000 --- a/feeds/ipq807x/qca-ssdk/src/src/hsl/dess/dess_leaky.c +++ /dev/null @@ -1,526 +0,0 @@ -/* - * Copyright (c) 2014, 2016, The Linux Foundation. All rights reserved. - * Permission to use, copy, modify, and/or distribute this software for - * any purpose with or without fee is hereby granted, provided that the - * above copyright notice and this permission notice appear in all copies. - * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES - * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR - * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES - * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN - * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT - * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. - */ - - -/** - * @defgroup dess_leaky DESS_LEAKY - * @{ - */ -#include "sw.h" -#include "hsl.h" -#include "hsl_dev.h" -#include "hsl_port_prop.h" -#include "dess_leaky.h" -#include "dess_reg.h" - -static sw_error_t -_dess_uc_leaky_mode_set(a_uint32_t dev_id, - fal_leaky_ctrl_mode_t ctrl_mode) -{ - a_uint32_t data; - sw_error_t rv; - - HSL_DEV_ID_CHECK(dev_id); - - if (FAL_LEAKY_PORT_CTRL == ctrl_mode) - { - data = 0; - } - else if (FAL_LEAKY_FDB_CTRL == ctrl_mode) - { - data = 1; - } - else - { - return SW_BAD_PARAM; - } - - HSL_REG_FIELD_SET(rv, dev_id, FORWARD_CTL0, 0, ARL_UNI_LEAKY, - (a_uint8_t *) (&data), sizeof (a_uint32_t)); - return rv; -} - -static sw_error_t -_dess_uc_leaky_mode_get(a_uint32_t dev_id, - fal_leaky_ctrl_mode_t *ctrl_mode) -{ - a_uint32_t data = 0; - sw_error_t rv; - - HSL_DEV_ID_CHECK(dev_id); - - HSL_REG_FIELD_GET(rv, dev_id, FORWARD_CTL0, 0, ARL_UNI_LEAKY, - (a_uint8_t *) (&data), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - - if (1 == data) - { - *ctrl_mode = FAL_LEAKY_FDB_CTRL; - } - else - { - *ctrl_mode = FAL_LEAKY_PORT_CTRL; - } - - return SW_OK; -} - -static sw_error_t -_dess_mc_leaky_mode_set(a_uint32_t dev_id, - fal_leaky_ctrl_mode_t ctrl_mode) -{ - a_uint32_t data; - sw_error_t rv; - - HSL_DEV_ID_CHECK(dev_id); - - if (FAL_LEAKY_PORT_CTRL == ctrl_mode) - { - data = 0; - } - else if (FAL_LEAKY_FDB_CTRL == ctrl_mode) - { - data = 1; - } - else - { - return SW_BAD_PARAM; - } - - HSL_REG_FIELD_SET(rv, dev_id, FORWARD_CTL0, 0, ARL_MUL_LEAKY, - (a_uint8_t *) (&data), sizeof (a_uint32_t)); - return rv; -} - -static sw_error_t -_dess_mc_leaky_mode_get(a_uint32_t dev_id, - fal_leaky_ctrl_mode_t *ctrl_mode) -{ - a_uint32_t data = 0; - sw_error_t rv; - - HSL_DEV_ID_CHECK(dev_id); - - HSL_REG_FIELD_GET(rv, dev_id, FORWARD_CTL0, 0, ARL_MUL_LEAKY, - (a_uint8_t *) (&data), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - - if (1 == data) - { - *ctrl_mode = FAL_LEAKY_FDB_CTRL; - } - else - { - *ctrl_mode = FAL_LEAKY_PORT_CTRL; - } - - return SW_OK; -} - -static sw_error_t -_dess_port_arp_leaky_set(a_uint32_t dev_id, fal_port_t port_id, - a_bool_t enable) -{ - a_uint32_t data; - sw_error_t rv; - - HSL_DEV_ID_CHECK(dev_id); - - if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU)) - { - return SW_BAD_PARAM; - } - - if (A_TRUE == enable) - { - data = 1; - } - else if (A_FALSE == enable) - { - data = 0; - } - else - { - return SW_BAD_PARAM; - } - - HSL_REG_FIELD_SET(rv, dev_id, PORT_LOOKUP_CTL, port_id, ARP_LEAKY_EN, - (a_uint8_t *) (&data), sizeof (a_uint32_t)); - return rv; -} - -static sw_error_t -_dess_port_arp_leaky_get(a_uint32_t dev_id, fal_port_t port_id, - a_bool_t *enable) -{ - a_uint32_t data = 0; - sw_error_t rv; - - HSL_DEV_ID_CHECK(dev_id); - - if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU)) - { - return SW_BAD_PARAM; - } - - HSL_REG_FIELD_GET(rv, dev_id, PORT_LOOKUP_CTL, port_id, ARP_LEAKY_EN, - (a_uint8_t *) (&data), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - - if (1 == data) - { - *enable = A_TRUE; - } - else - { - *enable = A_FALSE; - } - - return SW_OK; -} - -static sw_error_t -_dess_port_uc_leaky_set(a_uint32_t dev_id, fal_port_t port_id, - a_bool_t enable) -{ - a_uint32_t data; - sw_error_t rv; - - HSL_DEV_ID_CHECK(dev_id); - - if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU)) - { - return SW_BAD_PARAM; - } - - if (A_TRUE == enable) - { - data = 1; - } - else if (A_FALSE == enable) - { - data = 0; - } - else - { - return SW_BAD_PARAM; - } - - HSL_REG_FIELD_SET(rv, dev_id, PORT_LOOKUP_CTL, port_id, UNI_LEAKY_EN, - (a_uint8_t *) (&data), sizeof (a_uint32_t)); - return rv; -} - -static sw_error_t -_dess_port_uc_leaky_get(a_uint32_t dev_id, fal_port_t port_id, - a_bool_t *enable) -{ - a_uint32_t data = 0; - sw_error_t rv; - - HSL_DEV_ID_CHECK(dev_id); - - if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU)) - { - return SW_BAD_PARAM; - } - - HSL_REG_FIELD_GET(rv, dev_id, PORT_LOOKUP_CTL, port_id, UNI_LEAKY_EN, - (a_uint8_t *) (&data), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - - if (1 == data) - { - *enable = A_TRUE; - } - else - { - *enable = A_FALSE; - } - - return SW_OK; -} - -static sw_error_t -_dess_port_mc_leaky_set(a_uint32_t dev_id, fal_port_t port_id, - a_bool_t enable) -{ - a_uint32_t data; - sw_error_t rv; - - HSL_DEV_ID_CHECK(dev_id); - - if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU)) - { - return SW_BAD_PARAM; - } - - if (A_TRUE == enable) - { - data = 1; - } - else if (A_FALSE == enable) - { - data = 0; - } - else - { - return SW_BAD_PARAM; - } - - HSL_REG_FIELD_SET(rv, dev_id, PORT_LOOKUP_CTL, port_id, MUL_LEAKY_EN, - (a_uint8_t *) (&data), sizeof (a_uint32_t)); - return rv; -} - -static sw_error_t -_dess_port_mc_leaky_get(a_uint32_t dev_id, fal_port_t port_id, - a_bool_t *enable) -{ - a_uint32_t data = 0; - sw_error_t rv; - - HSL_DEV_ID_CHECK(dev_id); - - if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU)) - { - return SW_BAD_PARAM; - } - - HSL_REG_FIELD_GET(rv, dev_id, PORT_LOOKUP_CTL, port_id, MUL_LEAKY_EN, - (a_uint8_t *) (&data), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - - if (1 == data) - { - *enable = A_TRUE; - } - else - { - *enable = A_FALSE; - } - - return SW_OK; -} - -/** -* @brief Set unicast packets leaky control mode on a particular device. -* @param[in] dev_id device id -* @param[in] ctrl_mode leaky control mode -* @return SW_OK or error code -*/ -HSL_LOCAL sw_error_t -dess_uc_leaky_mode_set(a_uint32_t dev_id, - fal_leaky_ctrl_mode_t ctrl_mode) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _dess_uc_leaky_mode_set(dev_id, ctrl_mode); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Get unicast packets leaky control mode on a particular device. - * @param[in] dev_id device id - * @param[out] ctrl_mode leaky control mode - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -dess_uc_leaky_mode_get(a_uint32_t dev_id, - fal_leaky_ctrl_mode_t *ctrl_mode) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _dess_uc_leaky_mode_get(dev_id, ctrl_mode); - HSL_API_UNLOCK; - return rv; -} - -/** -* @brief Set multicast packets leaky control mode on a particular device. -* @param[in] dev_id device id -* @param[in] ctrl_mode leaky control mode -* @return SW_OK or error code -*/ -HSL_LOCAL sw_error_t -dess_mc_leaky_mode_set(a_uint32_t dev_id, - fal_leaky_ctrl_mode_t ctrl_mode) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _dess_mc_leaky_mode_set(dev_id, ctrl_mode); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Get multicast packets leaky control mode on a particular device. - * @param[in] dev_id device id - * @param[out] ctrl_mode leaky control mode - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -dess_mc_leaky_mode_get(a_uint32_t dev_id, - fal_leaky_ctrl_mode_t *ctrl_mode) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _dess_mc_leaky_mode_get(dev_id, ctrl_mode); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Set arp packets leaky status on a particular port. - * @param[in] dev_id device id - * @param[in] enable A_TRUE or A_FALSE - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -dess_port_arp_leaky_set(a_uint32_t dev_id, fal_port_t port_id, - a_bool_t enable) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _dess_port_arp_leaky_set(dev_id, port_id, enable); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Get arp packets leaky status on a particular port. - * @param[in] dev_id device id - * @param[out] enable A_TRUE or A_FALSE - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -dess_port_arp_leaky_get(a_uint32_t dev_id, fal_port_t port_id, - a_bool_t *enable) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _dess_port_arp_leaky_get(dev_id, port_id, enable); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Set unicast packets leaky status on a particular port. - * @param[in] dev_id device id - * @param[in] enable A_TRUE or A_FALSE - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -dess_port_uc_leaky_set(a_uint32_t dev_id, fal_port_t port_id, - a_bool_t enable) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _dess_port_uc_leaky_set(dev_id, port_id, enable); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Get unicast packets leaky status on a particular port. - * @param[in] dev_id device id - * @param[out] enable A_TRUE or A_FALSE - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -dess_port_uc_leaky_get(a_uint32_t dev_id, fal_port_t port_id, - a_bool_t *enable) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _dess_port_uc_leaky_get(dev_id, port_id, enable); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Set multicast packets leaky status on a particular port. - * @param[in] dev_id device id - * @param[in] enable A_TRUE or A_FALSE - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -dess_port_mc_leaky_set(a_uint32_t dev_id, fal_port_t port_id, - a_bool_t enable) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _dess_port_mc_leaky_set(dev_id, port_id, enable); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Get multicast packets leaky status on a particular port. - * @param[in] dev_id device id - * @param[out] enable A_TRUE or A_FALSE - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -dess_port_mc_leaky_get(a_uint32_t dev_id, fal_port_t port_id, - a_bool_t *enable) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _dess_port_mc_leaky_get(dev_id, port_id, enable); - HSL_API_UNLOCK; - return rv; -} - -sw_error_t -dess_leaky_init(a_uint32_t dev_id) -{ - HSL_DEV_ID_CHECK(dev_id); - -#ifndef HSL_STANDALONG - { - hsl_api_t *p_api; - - SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id)); - p_api->uc_leaky_mode_set = dess_uc_leaky_mode_set; - p_api->uc_leaky_mode_get = dess_uc_leaky_mode_get; - p_api->mc_leaky_mode_set = dess_mc_leaky_mode_set; - p_api->mc_leaky_mode_get = dess_mc_leaky_mode_get; - p_api->port_arp_leaky_set = dess_port_arp_leaky_set; - p_api->port_arp_leaky_get = dess_port_arp_leaky_get; - p_api->port_uc_leaky_set = dess_port_uc_leaky_set; - p_api->port_uc_leaky_get = dess_port_uc_leaky_get; - p_api->port_mc_leaky_set = dess_port_mc_leaky_set; - p_api->port_mc_leaky_get = dess_port_mc_leaky_get; - } -#endif - - return SW_OK; -} - -/** - * @} - */ - diff --git a/feeds/ipq807x/qca-ssdk/src/src/hsl/dess/dess_led.c b/feeds/ipq807x/qca-ssdk/src/src/hsl/dess/dess_led.c deleted file mode 100755 index 6f2b2ace7..000000000 --- a/feeds/ipq807x/qca-ssdk/src/src/hsl/dess/dess_led.c +++ /dev/null @@ -1,670 +0,0 @@ -/* - * Copyright (c) 2014, 2016, The Linux Foundation. All rights reserved. - * Permission to use, copy, modify, and/or distribute this software for - * any purpose with or without fee is hereby granted, provided that the - * above copyright notice and this permission notice appear in all copies. - * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES - * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR - * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES - * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN - * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT - * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. - */ - - -/** - * @defgroup dess_led DESS_LED - * @{ - */ -#include "sw.h" -#include "hsl.h" -#include "hsl_dev.h" -#include "dess_led.h" -#include "dess_reg.h" - -#define MAX_LED_PATTERN_ID 2 -#define LED_PATTERN_ADDR 0x50 - -static sw_error_t -_dess_led_ctrl_pattern_set(a_uint32_t dev_id, led_pattern_group_t group, - led_pattern_id_t id, led_ctrl_pattern_t * pattern) -{ - a_uint32_t data = 0, reg = 0, mode; - a_uint32_t addr; - sw_error_t rv; - - HSL_DEV_ID_CHECK(dev_id); - - if ((LED_WAN_PORT_GROUP != group) && (LED_LAN_PORT_GROUP != group)) - { - return SW_BAD_PARAM; - } - - if (id > MAX_LED_PATTERN_ID) - { - return SW_BAD_PARAM; - } - - addr = LED_PATTERN_ADDR + (id << 2); - - if (LED_ALWAYS_OFF == pattern->mode) - { - mode = 0; - } - else if (LED_ALWAYS_BLINK == pattern->mode) - { - mode = 1; - } - else if (LED_ALWAYS_ON == pattern->mode) - { - mode = 2; - } - else if (LED_PATTERN_MAP_EN == pattern->mode) - { - mode = 3; - } - else - { - return SW_BAD_PARAM; - } - SW_SET_REG_BY_FIELD(LED_CTRL, PATTERN_EN, mode, data); - - if (pattern->map & (1 << FULL_DUPLEX_LIGHT_EN)) - { - SW_SET_REG_BY_FIELD(LED_CTRL, FULL_LIGHT_EN, 1, data); - } - - if (pattern->map & (1 << HALF_DUPLEX_LIGHT_EN)) - { - SW_SET_REG_BY_FIELD(LED_CTRL, HALF_LIGHT_EN, 1, data); - } - - if (pattern->map & (1 << POWER_ON_LIGHT_EN)) - { - SW_SET_REG_BY_FIELD(LED_CTRL, POWERON_LIGHT_EN, 1, data); - } - - if (pattern->map & (1 << LINK_1000M_LIGHT_EN)) - { - SW_SET_REG_BY_FIELD(LED_CTRL, GE_LIGHT_EN, 1, data); - } - - if (pattern->map & (1 << LINK_100M_LIGHT_EN)) - { - SW_SET_REG_BY_FIELD(LED_CTRL, FE_LIGHT_EN, 1, data); - } - - if (pattern->map & (1 << LINK_10M_LIGHT_EN)) - { - SW_SET_REG_BY_FIELD(LED_CTRL, ETH_LIGHT_EN, 1, data); - } - - if (pattern->map & (1 << COLLISION_BLINK_EN)) - { - SW_SET_REG_BY_FIELD(LED_CTRL, COL_BLINK_EN, 1, data); - } - - if (pattern->map & (1 << RX_TRAFFIC_BLINK_EN)) - { - SW_SET_REG_BY_FIELD(LED_CTRL, RX_BLINK_EN, 1, data); - } - - if (pattern->map & (1 << TX_TRAFFIC_BLINK_EN)) - { - SW_SET_REG_BY_FIELD(LED_CTRL, TX_BLINK_EN, 1, data); - } - - if (pattern->map & (1 << LINKUP_OVERRIDE_EN)) - { - SW_SET_REG_BY_FIELD(LED_CTRL, LINKUP_OVER_EN, 1, data); - } - else - { - SW_SET_REG_BY_FIELD(LED_CTRL, LINKUP_OVER_EN, 0, data); - } - - if (LED_BLINK_2HZ == pattern->freq) - { - SW_SET_REG_BY_FIELD(LED_CTRL, BLINK_FREQ, 0, data); - } - else if (LED_BLINK_4HZ == pattern->freq) - { - SW_SET_REG_BY_FIELD(LED_CTRL, BLINK_FREQ, 1, data); - } - else if (LED_BLINK_8HZ == pattern->freq) - { - SW_SET_REG_BY_FIELD(LED_CTRL, BLINK_FREQ, 2, data); - } - else if (LED_BLINK_TXRX == pattern->freq) - { - SW_SET_REG_BY_FIELD(LED_CTRL, BLINK_FREQ, 3, data); - } - else - { - return SW_BAD_PARAM; - } - - HSL_REG_ENTRY_GEN_GET(rv, dev_id, addr, sizeof (a_uint32_t), - (a_uint8_t *) (®), - sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - - if (LED_WAN_PORT_GROUP == group) - { - reg &= 0xffff; - reg |= (data << 16); - } - else - { - reg &= 0xffff0000; - reg |= data; - } - - HSL_REG_ENTRY_GEN_SET(rv, dev_id, addr, sizeof (a_uint32_t), - (a_uint8_t *) (®), - sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - - if (LED_WAN_PORT_GROUP == group) - { - return SW_OK; - } - - HSL_REG_ENTRY_GET(rv, dev_id, LED_PATTERN, 0, - (a_uint8_t *) (&data), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - - if (LED_LAN_PORT_GROUP == group) - { - if (0 == id) - { - SW_SET_REG_BY_FIELD(LED_PATTERN, P3L0_MODE, mode, data); - SW_SET_REG_BY_FIELD(LED_PATTERN, P2L0_MODE, mode, data); - SW_SET_REG_BY_FIELD(LED_PATTERN, P1L0_MODE, mode, data); - } - else if (1 == id) - { - SW_SET_REG_BY_FIELD(LED_PATTERN, P3L1_MODE, mode, data); - SW_SET_REG_BY_FIELD(LED_PATTERN, P2L1_MODE, mode, data); - SW_SET_REG_BY_FIELD(LED_PATTERN, P1L1_MODE, mode, data); - } - else - { - SW_SET_REG_BY_FIELD(LED_PATTERN, P3L2_MODE, mode, data); - SW_SET_REG_BY_FIELD(LED_PATTERN, P2L2_MODE, mode, data); - SW_SET_REG_BY_FIELD(LED_PATTERN, P1L2_MODE, mode, data); - } - } - - HSL_REG_ENTRY_SET(rv, dev_id, LED_PATTERN, 0, - (a_uint8_t *) (&data), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - - return SW_OK; -} - -static sw_error_t -_dess_led_ctrl_pattern_get(a_uint32_t dev_id, led_pattern_group_t group, - led_pattern_id_t id, led_ctrl_pattern_t * pattern) -{ - a_uint32_t data = 0, reg = 0, tmp; - a_uint32_t addr; - sw_error_t rv; - - HSL_DEV_ID_CHECK(dev_id); - - if ((LED_WAN_PORT_GROUP != group) && (LED_LAN_PORT_GROUP != group)) - { - return SW_BAD_PARAM; - } - - if (id > MAX_LED_PATTERN_ID) - { - return SW_BAD_PARAM; - } - - aos_mem_zero(pattern, sizeof(led_ctrl_pattern_t)); - - addr = LED_PATTERN_ADDR + (id << 2); - - HSL_REG_ENTRY_GEN_GET(rv, dev_id, addr, sizeof (a_uint32_t), - (a_uint8_t *) (®), - sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - - if (LED_WAN_PORT_GROUP == group) - { - data = (reg >> 16) & 0xffff; - } - else - { - data = reg & 0xffff; - } - - SW_GET_FIELD_BY_REG(LED_CTRL, PATTERN_EN, tmp, data); - if (0 == tmp) - { - pattern->mode = LED_ALWAYS_OFF; - } - else if (1 == tmp) - { - pattern->mode = LED_ALWAYS_BLINK; - } - else if (2 == tmp) - { - pattern->mode = LED_ALWAYS_ON; - } - else - { - pattern->mode = LED_PATTERN_MAP_EN; - } - - SW_GET_FIELD_BY_REG(LED_CTRL, FULL_LIGHT_EN, tmp, data); - if (1 == tmp) - { - pattern->map |= (1 << FULL_DUPLEX_LIGHT_EN); - } - - SW_GET_FIELD_BY_REG(LED_CTRL, HALF_LIGHT_EN, tmp, data); - if (1 == tmp) - { - pattern->map |= (1 << HALF_DUPLEX_LIGHT_EN); - } - - SW_GET_FIELD_BY_REG(LED_CTRL, POWERON_LIGHT_EN, tmp, data); - if (1 == tmp) - { - pattern->map |= (1 << POWER_ON_LIGHT_EN); - } - - SW_GET_FIELD_BY_REG(LED_CTRL, GE_LIGHT_EN, tmp, data); - if (1 == tmp) - { - pattern->map |= (1 << LINK_1000M_LIGHT_EN); - } - - SW_GET_FIELD_BY_REG(LED_CTRL, FE_LIGHT_EN, tmp, data); - if (1 == tmp) - { - pattern->map |= (1 << LINK_100M_LIGHT_EN); - } - - SW_GET_FIELD_BY_REG(LED_CTRL, ETH_LIGHT_EN, tmp, data); - if (1 == tmp) - { - pattern->map |= (1 << LINK_10M_LIGHT_EN); - } - - SW_GET_FIELD_BY_REG(LED_CTRL, COL_BLINK_EN, tmp, data); - if (1 == tmp) - { - pattern->map |= (1 << COLLISION_BLINK_EN); - } - - SW_GET_FIELD_BY_REG(LED_CTRL, RX_BLINK_EN, tmp, data); - if (1 == tmp) - { - pattern->map |= (1 << RX_TRAFFIC_BLINK_EN); - } - - SW_GET_FIELD_BY_REG(LED_CTRL, TX_BLINK_EN, tmp, data); - if (1 == tmp) - { - pattern->map |= (1 << TX_TRAFFIC_BLINK_EN); - } - - SW_GET_FIELD_BY_REG(LED_CTRL, LINKUP_OVER_EN, tmp, data); - if (1 == tmp) - { - pattern->map |= (1 << LINKUP_OVERRIDE_EN); - } - - SW_GET_FIELD_BY_REG(LED_CTRL, BLINK_FREQ, tmp, data); - if (0 == tmp) - { - pattern->freq = LED_BLINK_2HZ; - } - else if (1 == tmp) - { - pattern->freq = LED_BLINK_4HZ; - } - else if (2 == tmp) - { - pattern->freq = LED_BLINK_8HZ; - } - else - { - pattern->freq = LED_BLINK_TXRX; - } - - return SW_OK; -} - -static sw_error_t -_dess_led_source_pattern_set(a_uint32_t dev_id, a_uint32_t source_id, led_ctrl_pattern_t * pattern) -{ - a_uint32_t data = 0, data1 = 0, reg = 0, mode; - sw_error_t rv; - a_uint32_t addr; - - HSL_DEV_ID_CHECK(dev_id); - - if (LED_ALWAYS_OFF == pattern->mode) - { - mode = 0; - } - else if (LED_ALWAYS_BLINK == pattern->mode) - { - mode = 1; - } - else if (LED_ALWAYS_ON == pattern->mode) - { - mode = 2; - } - else if (LED_PATTERN_MAP_EN == pattern->mode) - { - mode = 3; - } - else - { - return SW_BAD_PARAM; - } - - SW_SET_REG_BY_FIELD(LED_CTRL, PATTERN_EN, mode, data); - - if (pattern->map & (1 << FULL_DUPLEX_LIGHT_EN)) - { - SW_SET_REG_BY_FIELD(LED_CTRL, FULL_LIGHT_EN, 1, data); - } - - if (pattern->map & (1 << HALF_DUPLEX_LIGHT_EN)) - { - SW_SET_REG_BY_FIELD(LED_CTRL, HALF_LIGHT_EN, 1, data); - } - - if (pattern->map & (1 << POWER_ON_LIGHT_EN)) - { - SW_SET_REG_BY_FIELD(LED_CTRL, POWERON_LIGHT_EN, 1, data); - } - - if (pattern->map & (1 << LINK_1000M_LIGHT_EN)) - { - SW_SET_REG_BY_FIELD(LED_CTRL, GE_LIGHT_EN, 1, data); - } - - if (pattern->map & (1 << LINK_100M_LIGHT_EN)) - { - SW_SET_REG_BY_FIELD(LED_CTRL, FE_LIGHT_EN, 1, data); - } - - if (pattern->map & (1 << LINK_10M_LIGHT_EN)) - { - SW_SET_REG_BY_FIELD(LED_CTRL, ETH_LIGHT_EN, 1, data); - } - - if (pattern->map & (1 << COLLISION_BLINK_EN)) - { - SW_SET_REG_BY_FIELD(LED_CTRL, COL_BLINK_EN, 1, data); - } - - if (pattern->map & (1 << RX_TRAFFIC_BLINK_EN)) - { - SW_SET_REG_BY_FIELD(LED_CTRL, RX_BLINK_EN, 1, data); - } - - if (pattern->map & (1 << TX_TRAFFIC_BLINK_EN)) - { - SW_SET_REG_BY_FIELD(LED_CTRL, TX_BLINK_EN, 1, data); - } - - if (pattern->map & (1 << LINKUP_OVERRIDE_EN)) - { - SW_SET_REG_BY_FIELD(LED_CTRL, LINKUP_OVER_EN, 1, data); - } - else - { - SW_SET_REG_BY_FIELD(LED_CTRL, LINKUP_OVER_EN, 0, data); - } - - if (LED_BLINK_2HZ == pattern->freq) - { - SW_SET_REG_BY_FIELD(LED_CTRL, BLINK_FREQ, 0, data); - } - else if (LED_BLINK_4HZ == pattern->freq) - { - SW_SET_REG_BY_FIELD(LED_CTRL, BLINK_FREQ, 1, data); - } - else if (LED_BLINK_8HZ == pattern->freq) - { - SW_SET_REG_BY_FIELD(LED_CTRL, BLINK_FREQ, 2, data); - } - else if (LED_BLINK_TXRX == pattern->freq) - { - SW_SET_REG_BY_FIELD(LED_CTRL, BLINK_FREQ, 3, data); - } - else - { - return SW_BAD_PARAM; - } - - if (source_id == 1) - { - - addr = LED_PATTERN_ADDR; - HSL_REG_ENTRY_GEN_GET(rv, dev_id, addr, sizeof (a_uint32_t), - (a_uint8_t *) (®), - sizeof (a_uint32_t)); - reg &= 0xffff0000; - reg |= data; - HSL_REG_ENTRY_GEN_SET(rv, dev_id, addr, sizeof (a_uint32_t), - (a_uint8_t *) (®), - sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - - } - else if (source_id == 2) - { - addr = LED_PATTERN_ADDR + (1 << 2); - HSL_REG_ENTRY_GEN_GET(rv, dev_id, addr, sizeof (a_uint32_t), - (a_uint8_t *) (®), - sizeof (a_uint32_t)); - reg &= 0xffff0000; - reg |= data; - HSL_REG_ENTRY_GEN_SET(rv, dev_id, addr, sizeof (a_uint32_t), - (a_uint8_t *) (®), - sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - - } - else if (source_id == 3) - { - addr = LED_PATTERN_ADDR + (2 << 2); - HSL_REG_ENTRY_GEN_GET(rv, dev_id, addr, sizeof (a_uint32_t), - (a_uint8_t *) (®), - sizeof (a_uint32_t)); - reg &= 0xffff0000; - reg |= data; - HSL_REG_ENTRY_GEN_SET(rv, dev_id, addr, sizeof (a_uint32_t), - (a_uint8_t *) (®), - sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - - } - if (source_id == 13) - { - addr = LED_PATTERN_ADDR; - HSL_REG_ENTRY_GEN_GET(rv, dev_id, addr, sizeof (a_uint32_t), - (a_uint8_t *) (®), - sizeof (a_uint32_t)); - reg &= 0xffff; - reg |= (data << 16); - HSL_REG_ENTRY_GEN_SET(rv, dev_id, addr, sizeof (a_uint32_t), - (a_uint8_t *) (®), - sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - - } - else if (source_id == 14) - { - addr = LED_PATTERN_ADDR + (1 << 2); - HSL_REG_ENTRY_GEN_GET(rv, dev_id, addr, sizeof (a_uint32_t), - (a_uint8_t *) (®), - sizeof (a_uint32_t)); - reg &= 0xffff; - reg |= (data << 16); - HSL_REG_ENTRY_GEN_SET(rv, dev_id, addr, sizeof (a_uint32_t), - (a_uint8_t *) (®), - sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - - } - else if (source_id == 15) - { - addr = LED_PATTERN_ADDR + (2 << 2); - HSL_REG_ENTRY_GEN_GET(rv, dev_id, addr, sizeof (a_uint32_t), - (a_uint8_t *) (®), - sizeof (a_uint32_t)); - reg &= 0xffff; - reg |= (data << 16); - HSL_REG_ENTRY_GEN_SET(rv, dev_id, addr, sizeof (a_uint32_t), - (a_uint8_t *) (®), - sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - - } - else if ((source_id) >= 4 && (source_id <= 12)) - { - HSL_REG_ENTRY_GET(rv, dev_id, LED_PATTERN, 0, - (a_uint8_t *) (&data1), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - - if (source_id == 4) - { - SW_SET_REG_BY_FIELD(LED_PATTERN, P1L0_MODE, mode, data1); - } - if (source_id == 5) - { - SW_SET_REG_BY_FIELD(LED_PATTERN, P1L1_MODE, mode, data1); - } - if (source_id == 6) - { - SW_SET_REG_BY_FIELD(LED_PATTERN, P1L2_MODE, mode, data1); - } - if (source_id == 7) - { - SW_SET_REG_BY_FIELD(LED_PATTERN, P2L0_MODE, mode, data1); - } - if (source_id == 8) - { - SW_SET_REG_BY_FIELD(LED_PATTERN, P2L1_MODE, mode, data1); - } - if (source_id == 9) - { - SW_SET_REG_BY_FIELD(LED_PATTERN, P2L2_MODE, mode, data1); - } - if (source_id == 10) - { - SW_SET_REG_BY_FIELD(LED_PATTERN, P3L0_MODE, mode, data1); - } - if (source_id == 11) - { - SW_SET_REG_BY_FIELD(LED_PATTERN, P3L1_MODE, mode, data1); - } - if (source_id == 12) - { - SW_SET_REG_BY_FIELD(LED_PATTERN, P3L2_MODE, mode, data1); - } - - HSL_REG_ENTRY_SET(rv, dev_id, LED_PATTERN, 0, - (a_uint8_t *) (&data1), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - - } - - return SW_OK; - -} - -/** -* @brief Set led control pattern on a particular device. -* @param[in] dev_id device id -* @param[in] group pattern group, lan or wan -* @param[in] id pattern id -* @param[in] pattern led control pattern -* @return SW_OK or error code -*/ -HSL_LOCAL sw_error_t -dess_led_ctrl_pattern_set(a_uint32_t dev_id, led_pattern_group_t group, - led_pattern_id_t id, led_ctrl_pattern_t * pattern) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _dess_led_ctrl_pattern_set(dev_id, group, id, pattern); - HSL_API_UNLOCK; - return rv; -} - -/** -* @brief Get led control pattern on a particular device. -* @param[in] dev_id device id -* @param[in] group pattern group, lan or wan -* @param[in] id pattern id -* @param[out] pattern led control pattern -* @return SW_OK or error code -*/ -HSL_LOCAL sw_error_t -dess_led_ctrl_pattern_get(a_uint32_t dev_id, led_pattern_group_t group, - led_pattern_id_t id, led_ctrl_pattern_t * pattern) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _dess_led_ctrl_pattern_get(dev_id, group, id, pattern); - HSL_API_UNLOCK; - return rv; -} - -/** -* @brief Set led source pattern on a particular device. -* @param[in] dev_id device id -* @param[in] source id -* @param[in] id pattern id -* @param[in] pattern led control pattern -* @return SW_OK or error code -*/ -HSL_LOCAL sw_error_t -dess_led_source_pattern_set(a_uint32_t dev_id, a_uint32_t source_id, led_ctrl_pattern_t * pattern) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _dess_led_source_pattern_set(dev_id, source_id, pattern); - HSL_API_UNLOCK; - return rv; -} - -sw_error_t -dess_led_init(a_uint32_t dev_id) -{ - HSL_DEV_ID_CHECK(dev_id); - -#ifndef HSL_STANDALONG - { - hsl_api_t *p_api; - - SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id)); - p_api->led_ctrl_pattern_set = dess_led_ctrl_pattern_set; - p_api->led_ctrl_pattern_get = dess_led_ctrl_pattern_get; - p_api->led_ctrl_source_set = dess_led_source_pattern_set; - } -#endif - - return SW_OK; -} - -/** - * @} - */ - diff --git a/feeds/ipq807x/qca-ssdk/src/src/hsl/dess/dess_mib.c b/feeds/ipq807x/qca-ssdk/src/src/hsl/dess/dess_mib.c deleted file mode 100755 index 4cc6ed7b2..000000000 --- a/feeds/ipq807x/qca-ssdk/src/src/hsl/dess/dess_mib.c +++ /dev/null @@ -1,861 +0,0 @@ -/* - * Copyright (c) 2014, 2016, The Linux Foundation. All rights reserved. - * Permission to use, copy, modify, and/or distribute this software for - * any purpose with or without fee is hereby granted, provided that the - * above copyright notice and this permission notice appear in all copies. - * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES - * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR - * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES - * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN - * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT - * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. - */ - - -/** - * @defgroup dess_mib DESS_MIB - * @{ - */ -#include "sw.h" -#include "hsl.h" -#include "hsl_dev.h" -#include "hsl_port_prop.h" -#include "dess_mib.h" -#include "dess_reg.h" - - -#define MIB_FLUSH_ALL_PORTS 0x1 -#define MIB_FLUSH_ONE_PORT 0x2 -#define MIB_AUTOCAST_ALL_PORTS 0x3 - -static sw_error_t -_dess_mib_op_commit(a_uint32_t dev_id, a_uint32_t op) -{ - a_uint32_t mib_busy = 1, i = 0x1000, val; - sw_error_t rv; - - while (mib_busy && --i) - { - HSL_REG_FIELD_GET(rv, dev_id, MIB_FUNC, 0, MIB_BUSY, - (a_uint8_t *) (&mib_busy), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - aos_udelay(5); - } - - if (i == 0) - return SW_BUSY; - - HSL_REG_ENTRY_GET(rv, dev_id, MIB_FUNC, 0, - (a_uint8_t *) (&val), sizeof (a_uint32_t)); - SW_SET_REG_BY_FIELD(MIB_FUNC, MIB_FUN, op, val); - SW_SET_REG_BY_FIELD(MIB_FUNC, MIB_BUSY, 1, val); - - HSL_REG_ENTRY_SET(rv, dev_id, MIB_FUNC, 0, - (a_uint8_t *) (&val), sizeof (a_uint32_t)); - - SW_RTN_ON_ERROR(rv); - - mib_busy = 1; - i = 0x1000; - while (mib_busy && --i) - { - HSL_REG_FIELD_GET(rv, dev_id, MIB_FUNC, 0, MIB_BUSY, - (a_uint8_t *) (&mib_busy), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - aos_udelay(5); - } - - if (i == 0) - return SW_FAIL; - - return SW_OK; -} - -static sw_error_t -_dess_get_mib_info(a_uint32_t dev_id, fal_port_t port_id, - fal_mib_info_t * mib_info) -{ - a_uint32_t val = 0; - sw_error_t rv; - - HSL_DEV_ID_CHECK(dev_id); - - if (A_FALSE == hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU)) - { - return SW_OUT_OF_RANGE; - } - - HSL_REG_ENTRY_GET(rv, dev_id, MIB_RXBROAD, port_id, - (a_uint8_t *) (&val), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - mib_info->RxBroad = val; - - HSL_REG_ENTRY_GET(rv, dev_id, MIB_RXPAUSE, port_id, - (a_uint8_t *) (&val), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - mib_info->RxPause = val; - - HSL_REG_ENTRY_GET(rv, dev_id, MIB_RXMULTI, port_id, - (a_uint8_t *) (&val), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - mib_info->RxMulti = val; - - HSL_REG_ENTRY_GET(rv, dev_id, MIB_RXFCSERR, port_id, - (a_uint8_t *) (&val), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - mib_info->RxFcsErr = val; - - HSL_REG_ENTRY_GET(rv, dev_id, MIB_RXALLIGNERR, port_id, - (a_uint8_t *) (&val), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - mib_info->RxAllignErr = val; - - HSL_REG_ENTRY_GET(rv, dev_id, MIB_RXRUNT, port_id, (a_uint8_t *) (&val), - sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - mib_info->RxRunt = val; - - HSL_REG_ENTRY_GET(rv, dev_id, MIB_RXFRAGMENT, port_id, - (a_uint8_t *) (&val), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - mib_info->RxFragment = val; - - HSL_REG_ENTRY_GET(rv, dev_id, MIB_RX64BYTE, port_id, - (a_uint8_t *) (&val), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - mib_info->Rx64Byte = val; - - HSL_REG_ENTRY_GET(rv, dev_id, MIB_RX128BYTE, port_id, - (a_uint8_t *) (&val), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - mib_info->Rx128Byte = val; - - HSL_REG_ENTRY_GET(rv, dev_id, MIB_RX256BYTE, port_id, - (a_uint8_t *) (&val), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - mib_info->Rx256Byte = val; - - HSL_REG_ENTRY_GET(rv, dev_id, MIB_RX512BYTE, port_id, - (a_uint8_t *) (&val), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - mib_info->Rx512Byte = val; - - HSL_REG_ENTRY_GET(rv, dev_id, MIB_RX1024BYTE, port_id, - (a_uint8_t *) (&val), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - mib_info->Rx1024Byte = val; - - HSL_REG_ENTRY_GET(rv, dev_id, MIB_RX1518BYTE, port_id, - (a_uint8_t *) (&val), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - mib_info->Rx1518Byte = val; - - HSL_REG_ENTRY_GET(rv, dev_id, MIB_RXMAXBYTE, port_id, - (a_uint8_t *) (&val), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - mib_info->RxMaxByte = val; - - HSL_REG_ENTRY_GET(rv, dev_id, MIB_RXTOOLONG, port_id, - (a_uint8_t *) (&val), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - mib_info->RxTooLong = val; - - HSL_REG_ENTRY_GET(rv, dev_id, MIB_RXGOODBYTE_LO, port_id, - (a_uint8_t *) (&val), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - mib_info->RxGoodByte_lo = val; - - HSL_REG_ENTRY_GET(rv, dev_id, MIB_RXGOODBYTE_HI, port_id, - (a_uint8_t *) (&val), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - mib_info->RxGoodByte_hi = val; - - HSL_REG_ENTRY_GET(rv, dev_id, MIB_RXBADBYTE_LO, port_id, - (a_uint8_t *) (&val), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - mib_info->RxBadByte_lo = val; - - HSL_REG_ENTRY_GET(rv, dev_id, MIB_RXBADBYTE_HI, port_id, - (a_uint8_t *) (&val), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - mib_info->RxBadByte_hi = val; - - HSL_REG_ENTRY_GET(rv, dev_id, MIB_RXOVERFLOW, port_id, - (a_uint8_t *) (&val), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - mib_info->RxOverFlow = val; - - HSL_REG_ENTRY_GET(rv, dev_id, MIB_FILTERED, port_id, - (a_uint8_t *) (&val), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - mib_info->Filtered = val; - - HSL_REG_ENTRY_GET(rv, dev_id, MIB_TXBROAD, port_id, (a_uint8_t *) (&val), - sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - mib_info->TxBroad = val; - - HSL_REG_ENTRY_GET(rv, dev_id, MIB_TXPAUSE, port_id, (a_uint8_t *) (&val), - sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - mib_info->TxPause = val; - - HSL_REG_ENTRY_GET(rv, dev_id, MIB_TXMULTI, port_id, (a_uint8_t *) (&val), - sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - mib_info->TxMulti = val; - - HSL_REG_ENTRY_GET(rv, dev_id, MIB_TXUNDERRUN, port_id, - (a_uint8_t *) (&val), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - mib_info->TxUnderRun = val; - - HSL_REG_ENTRY_GET(rv, dev_id, MIB_TX64BYTE, port_id, - (a_uint8_t *) (&val), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - mib_info->Tx64Byte = val; - - HSL_REG_ENTRY_GET(rv, dev_id, MIB_TX128BYTE, port_id, - (a_uint8_t *) (&val), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - mib_info->Tx128Byte = val; - - HSL_REG_ENTRY_GET(rv, dev_id, MIB_TX256BYTE, port_id, - (a_uint8_t *) (&val), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - mib_info->Tx256Byte = val; - - HSL_REG_ENTRY_GET(rv, dev_id, MIB_TX512BYTE, port_id, - (a_uint8_t *) (&val), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - mib_info->Tx512Byte = val; - - HSL_REG_ENTRY_GET(rv, dev_id, MIB_TX1024BYTE, port_id, - (a_uint8_t *) (&val), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - mib_info->Tx1024Byte = val; - - HSL_REG_ENTRY_GET(rv, dev_id, MIB_TX1518BYTE, port_id, - (a_uint8_t *) (&val), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - mib_info->Tx1518Byte = val; - - HSL_REG_ENTRY_GET(rv, dev_id, MIB_TXMAXBYTE, port_id, - (a_uint8_t *) (&val), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - mib_info->TxMaxByte = val; - - HSL_REG_ENTRY_GET(rv, dev_id, MIB_TXOVERSIZE, port_id, - (a_uint8_t *) (&val), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - mib_info->TxOverSize = val; - - HSL_REG_ENTRY_GET(rv, dev_id, MIB_TXBYTE_LO, port_id, - (a_uint8_t *) (&val), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - mib_info->TxByte_lo = val; - - HSL_REG_ENTRY_GET(rv, dev_id, MIB_TXBYTE_HI, port_id, - (a_uint8_t *) (&val), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - mib_info->TxByte_hi = val; - - HSL_REG_ENTRY_GET(rv, dev_id, MIB_TXCOLLISION, port_id, - (a_uint8_t *) (&val), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - mib_info->TxCollision = val; - - HSL_REG_ENTRY_GET(rv, dev_id, MIB_TXABORTCOL, port_id, - (a_uint8_t *) (&val), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - mib_info->TxAbortCol = val; - - HSL_REG_ENTRY_GET(rv, dev_id, MIB_TXMULTICOL, port_id, - (a_uint8_t *) (&val), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - mib_info->TxMultiCol = val; - - HSL_REG_ENTRY_GET(rv, dev_id, MIB_TXSINGALCOL, port_id, - (a_uint8_t *) (&val), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - mib_info->TxSingalCol = val; - - HSL_REG_ENTRY_GET(rv, dev_id, MIB_TXEXCDEFER, port_id, - (a_uint8_t *) (&val), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - mib_info->TxExcDefer = val; - - HSL_REG_ENTRY_GET(rv, dev_id, MIB_TXDEFER, port_id, (a_uint8_t *) (&val), - sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - mib_info->TxDefer = val; - - HSL_REG_ENTRY_GET(rv, dev_id, MIB_TXLATECOL, port_id, - (a_uint8_t *) (&val), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - mib_info->TxLateCol = val; - - HSL_REG_ENTRY_GET(rv, dev_id, MIB_RXUNICAST, port_id, - (a_uint8_t *) (&val), sizeof - (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - mib_info->RxUniCast = val; - - HSL_REG_ENTRY_GET(rv, dev_id, MIB_TXUNICAST, port_id, - (a_uint8_t *) (&val), sizeof - (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - mib_info->TxUniCast = val; - - return SW_OK; -} - -static sw_error_t -_dess_get_rx_mib_info(a_uint32_t dev_id, fal_port_t port_id, - fal_mib_info_t * mib_info) -{ - a_uint32_t val = 0; - sw_error_t rv; - - HSL_DEV_ID_CHECK(dev_id); - - if (A_FALSE == hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU)) - { - return SW_OUT_OF_RANGE; - } - - HSL_REG_ENTRY_GET(rv, dev_id, MIB_RXBROAD, port_id, - (a_uint8_t *) (&val), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - mib_info->RxBroad = val; - - HSL_REG_ENTRY_GET(rv, dev_id, MIB_RXPAUSE, port_id, - (a_uint8_t *) (&val), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - mib_info->RxPause = val; - - HSL_REG_ENTRY_GET(rv, dev_id, MIB_RXMULTI, port_id, - (a_uint8_t *) (&val), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - mib_info->RxMulti = val; - - HSL_REG_ENTRY_GET(rv, dev_id, MIB_RXFCSERR, port_id, - (a_uint8_t *) (&val), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - mib_info->RxFcsErr = val; - - HSL_REG_ENTRY_GET(rv, dev_id, MIB_RXALLIGNERR, port_id, - (a_uint8_t *) (&val), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - mib_info->RxAllignErr = val; - - HSL_REG_ENTRY_GET(rv, dev_id, MIB_RXRUNT, port_id, (a_uint8_t *) (&val), - sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - mib_info->RxRunt = val; - - HSL_REG_ENTRY_GET(rv, dev_id, MIB_RXFRAGMENT, port_id, - (a_uint8_t *) (&val), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - mib_info->RxFragment = val; - - HSL_REG_ENTRY_GET(rv, dev_id, MIB_RX64BYTE, port_id, - (a_uint8_t *) (&val), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - mib_info->Rx64Byte = val; - - HSL_REG_ENTRY_GET(rv, dev_id, MIB_RX128BYTE, port_id, - (a_uint8_t *) (&val), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - mib_info->Rx128Byte = val; - - HSL_REG_ENTRY_GET(rv, dev_id, MIB_RX256BYTE, port_id, - (a_uint8_t *) (&val), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - mib_info->Rx256Byte = val; - - HSL_REG_ENTRY_GET(rv, dev_id, MIB_RX512BYTE, port_id, - (a_uint8_t *) (&val), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - mib_info->Rx512Byte = val; - - HSL_REG_ENTRY_GET(rv, dev_id, MIB_RX1024BYTE, port_id, - (a_uint8_t *) (&val), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - mib_info->Rx1024Byte = val; - - HSL_REG_ENTRY_GET(rv, dev_id, MIB_RX1518BYTE, port_id, - (a_uint8_t *) (&val), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - mib_info->Rx1518Byte = val; - - HSL_REG_ENTRY_GET(rv, dev_id, MIB_RXMAXBYTE, port_id, - (a_uint8_t *) (&val), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - mib_info->RxMaxByte = val; - - HSL_REG_ENTRY_GET(rv, dev_id, MIB_RXTOOLONG, port_id, - (a_uint8_t *) (&val), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - mib_info->RxTooLong = val; - - HSL_REG_ENTRY_GET(rv, dev_id, MIB_RXGOODBYTE_LO, port_id, - (a_uint8_t *) (&val), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - mib_info->RxGoodByte_lo = val; - - HSL_REG_ENTRY_GET(rv, dev_id, MIB_RXGOODBYTE_HI, port_id, - (a_uint8_t *) (&val), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - mib_info->RxGoodByte_hi = val; - - HSL_REG_ENTRY_GET(rv, dev_id, MIB_RXBADBYTE_LO, port_id, - (a_uint8_t *) (&val), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - mib_info->RxBadByte_lo = val; - - HSL_REG_ENTRY_GET(rv, dev_id, MIB_RXBADBYTE_HI, port_id, - (a_uint8_t *) (&val), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - mib_info->RxBadByte_hi = val; - - HSL_REG_ENTRY_GET(rv, dev_id, MIB_RXOVERFLOW, port_id, - (a_uint8_t *) (&val), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - mib_info->RxOverFlow = val; - - HSL_REG_ENTRY_GET(rv, dev_id, MIB_FILTERED, port_id, - (a_uint8_t *) (&val), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - mib_info->Filtered = val; - - HSL_REG_ENTRY_GET(rv, dev_id, MIB_RXUNICAST, port_id, - (a_uint8_t *) (&val), sizeof - (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - mib_info->RxUniCast = val; - - return SW_OK; -} - -static sw_error_t -_dess_get_tx_mib_info(a_uint32_t dev_id, fal_port_t port_id, - fal_mib_info_t * mib_info) -{ - a_uint32_t val = 0; - sw_error_t rv; - - HSL_DEV_ID_CHECK(dev_id); - - if (A_FALSE == hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU)) - { - return SW_OUT_OF_RANGE; - } - - HSL_REG_ENTRY_GET(rv, dev_id, MIB_TXBROAD, port_id, (a_uint8_t *) (&val), - sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - mib_info->TxBroad = val; - - HSL_REG_ENTRY_GET(rv, dev_id, MIB_TXPAUSE, port_id, (a_uint8_t *) (&val), - sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - mib_info->TxPause = val; - - HSL_REG_ENTRY_GET(rv, dev_id, MIB_TXMULTI, port_id, (a_uint8_t *) (&val), - sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - mib_info->TxMulti = val; - - HSL_REG_ENTRY_GET(rv, dev_id, MIB_TXUNDERRUN, port_id, - (a_uint8_t *) (&val), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - mib_info->TxUnderRun = val; - - HSL_REG_ENTRY_GET(rv, dev_id, MIB_TX64BYTE, port_id, - (a_uint8_t *) (&val), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - mib_info->Tx64Byte = val; - - HSL_REG_ENTRY_GET(rv, dev_id, MIB_TX128BYTE, port_id, - (a_uint8_t *) (&val), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - mib_info->Tx128Byte = val; - - HSL_REG_ENTRY_GET(rv, dev_id, MIB_TX256BYTE, port_id, - (a_uint8_t *) (&val), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - mib_info->Tx256Byte = val; - - HSL_REG_ENTRY_GET(rv, dev_id, MIB_TX512BYTE, port_id, - (a_uint8_t *) (&val), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - mib_info->Tx512Byte = val; - - HSL_REG_ENTRY_GET(rv, dev_id, MIB_TX1024BYTE, port_id, - (a_uint8_t *) (&val), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - mib_info->Tx1024Byte = val; - - HSL_REG_ENTRY_GET(rv, dev_id, MIB_TX1518BYTE, port_id, - (a_uint8_t *) (&val), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - mib_info->Tx1518Byte = val; - - HSL_REG_ENTRY_GET(rv, dev_id, MIB_TXMAXBYTE, port_id, - (a_uint8_t *) (&val), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - mib_info->TxMaxByte = val; - - HSL_REG_ENTRY_GET(rv, dev_id, MIB_TXOVERSIZE, port_id, - (a_uint8_t *) (&val), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - mib_info->TxOverSize = val; - - HSL_REG_ENTRY_GET(rv, dev_id, MIB_TXBYTE_LO, port_id, - (a_uint8_t *) (&val), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - mib_info->TxByte_lo = val; - - HSL_REG_ENTRY_GET(rv, dev_id, MIB_TXBYTE_HI, port_id, - (a_uint8_t *) (&val), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - mib_info->TxByte_hi = val; - - HSL_REG_ENTRY_GET(rv, dev_id, MIB_TXCOLLISION, port_id, - (a_uint8_t *) (&val), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - mib_info->TxCollision = val; - - HSL_REG_ENTRY_GET(rv, dev_id, MIB_TXABORTCOL, port_id, - (a_uint8_t *) (&val), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - mib_info->TxAbortCol = val; - - HSL_REG_ENTRY_GET(rv, dev_id, MIB_TXMULTICOL, port_id, - (a_uint8_t *) (&val), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - mib_info->TxMultiCol = val; - - HSL_REG_ENTRY_GET(rv, dev_id, MIB_TXSINGALCOL, port_id, - (a_uint8_t *) (&val), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - mib_info->TxSingalCol = val; - - HSL_REG_ENTRY_GET(rv, dev_id, MIB_TXEXCDEFER, port_id, - (a_uint8_t *) (&val), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - mib_info->TxExcDefer = val; - - HSL_REG_ENTRY_GET(rv, dev_id, MIB_TXDEFER, port_id, (a_uint8_t *) (&val), - sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - mib_info->TxDefer = val; - - HSL_REG_ENTRY_GET(rv, dev_id, MIB_TXLATECOL, port_id, - (a_uint8_t *) (&val), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - mib_info->TxLateCol = val; - - HSL_REG_ENTRY_GET(rv, dev_id, MIB_TXUNICAST, port_id, - (a_uint8_t *) (&val), sizeof - (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - mib_info->TxUniCast = val; - - return SW_OK; -} - -static sw_error_t -_dess_mib_status_set(a_uint32_t dev_id, a_bool_t enable) -{ - sw_error_t rv; - a_uint32_t val; - - HSL_DEV_ID_CHECK(dev_id); - - if (A_TRUE == enable) - { - val = 1; - } - else if (A_FALSE == enable) - { - val = 0; - } - else - { - return SW_BAD_PARAM; - } - - HSL_REG_FIELD_SET(rv, dev_id, MOD_ENABLE, 0, MIB_EN, - (a_uint8_t *) (&val), sizeof (a_uint32_t)); - return rv; -} - -static sw_error_t -_dess_mib_status_get(a_uint32_t dev_id, a_bool_t * enable) -{ - sw_error_t rv; - a_uint32_t val = 0; - - HSL_DEV_ID_CHECK(dev_id); - - HSL_REG_FIELD_GET(rv, dev_id, MOD_ENABLE, 0, MIB_EN, - (a_uint8_t *) (&val), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - - if (1 == val) - { - *enable = A_TRUE; - } - else - { - *enable = A_FALSE; - } - - return SW_OK; -} - -static sw_error_t -_dess_mib_cpukeep_set(a_uint32_t dev_id, a_bool_t enable) -{ - sw_error_t rv; - a_uint32_t val; - - HSL_DEV_ID_CHECK(dev_id); - - if (A_TRUE == enable) - { - val = 1; - } - else if (A_FALSE == enable) - { - val = 0; - } - else - { - return SW_BAD_PARAM; - } - - HSL_REG_FIELD_SET(rv, dev_id, MIB_FUNC, 0, MIB_CPU_KEEP, - (a_uint8_t *) (&val), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - - return rv; -} - -static sw_error_t -_dess_mib_cpukeep_get(a_uint32_t dev_id, a_bool_t * enable) -{ - sw_error_t rv; - a_uint32_t val = 0; - - HSL_DEV_ID_CHECK(dev_id); - - HSL_REG_FIELD_GET(rv, dev_id, MIB_FUNC, 0, MIB_CPU_KEEP, - (a_uint8_t *) (&val), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - - if (1 == val) - { - *enable = A_TRUE; - } - else - { - *enable = A_FALSE; - } - - return SW_OK; -} - -static sw_error_t -_dess_mib_port_flush_counters(a_uint32_t dev_id, fal_port_t port_id) -{ - a_uint32_t val; - sw_error_t rv; - - HSL_DEV_ID_CHECK(dev_id); - - if (A_FALSE == hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU)) - { - return SW_OUT_OF_RANGE; - } - - if (port_id>7) - return SW_BAD_PARAM; - - val = port_id; - HSL_REG_FIELD_SET(rv, dev_id, MIB_FUNC, 0, MIB_FLUSH_PORT, - (a_uint8_t *) (&val), sizeof (a_uint32_t)); - - rv = _dess_mib_op_commit( dev_id, MIB_FLUSH_ONE_PORT); - - return rv; -} - -/** - * @brief Get mib infomation on particular port. - * @param[in] dev_id device id - * @param[in] port_id port id - * @param[out] mib_info mib infomation - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -dess_get_mib_info(a_uint32_t dev_id, fal_port_t port_id, - fal_mib_info_t * mib_info) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _dess_get_mib_info(dev_id, port_id, mib_info); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Get RX mib infomation on particular port. - * @param[in] dev_id device id - * @param[in] port_id port id - * @param[out] mib_info mib infomation - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -dess_get_rx_mib_info(a_uint32_t dev_id, fal_port_t port_id, - fal_mib_info_t * mib_info) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _dess_get_rx_mib_info(dev_id, port_id, mib_info); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Get TX mib infomation on particular port. - * @param[in] dev_id device id - * @param[in] port_id port id - * @param[out] mib_info mib infomation - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -dess_get_tx_mib_info(a_uint32_t dev_id, fal_port_t port_id, - fal_mib_info_t * mib_info) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _dess_get_tx_mib_info(dev_id, port_id, mib_info); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Set mib status on a particular device. - * @param[in] dev_id device id - * @param[in] enable A_TRUE or A_FALSE - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -dess_mib_status_set(a_uint32_t dev_id, a_bool_t enable) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _dess_mib_status_set(dev_id, enable); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Get mib status on a particular device. - * @param[in] dev_id device id - * @param[out] enable A_TRUE or A_FALSE - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -dess_mib_status_get(a_uint32_t dev_id, a_bool_t * enable) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _dess_mib_status_get(dev_id, enable); - HSL_API_UNLOCK; - return rv; -} - -HSL_LOCAL sw_error_t -dess_mib_port_flush_counters(a_uint32_t dev_id, fal_port_t port_id) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _dess_mib_port_flush_counters(dev_id, port_id); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Set mib cpu keep bit on a particular device. - * @param[in] dev_id device id - * @param[in] enable A_TRUE or A_FALSE - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -dess_mib_cpukeep_set(a_uint32_t dev_id, a_bool_t enable) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _dess_mib_cpukeep_set(dev_id, enable); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Get mib keep bit on a particular device. - * @param[in] dev_id device id - * @param[out] enable A_TRUE or A_FALSE - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -dess_mib_cpukeep_get(a_uint32_t dev_id, a_bool_t * enable) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _dess_mib_cpukeep_get(dev_id, enable); - HSL_API_UNLOCK; - return rv; -} - -sw_error_t -dess_mib_init(a_uint32_t dev_id) -{ - -#ifndef HSL_STANDALONG - hsl_api_t *p_api; -#endif - HSL_DEV_ID_CHECK(dev_id); - -#ifndef HSL_STANDALONG - SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id)); - - p_api->get_mib_info = dess_get_mib_info; - p_api->get_rx_mib_info = dess_get_rx_mib_info; - p_api->get_tx_mib_info = dess_get_tx_mib_info; - p_api->mib_status_set = dess_mib_status_set; - p_api->mib_status_get = dess_mib_status_get; - p_api->mib_port_flush_counters = dess_mib_port_flush_counters; - p_api->mib_cpukeep_set = dess_mib_cpukeep_set; - p_api->mib_cpukeep_get = dess_mib_cpukeep_get; -#endif - - return SW_OK; -} - -/** - * @} - */ - diff --git a/feeds/ipq807x/qca-ssdk/src/src/hsl/dess/dess_mirror.c b/feeds/ipq807x/qca-ssdk/src/src/hsl/dess/dess_mirror.c deleted file mode 100755 index 9edb85fa4..000000000 --- a/feeds/ipq807x/qca-ssdk/src/src/hsl/dess/dess_mirror.c +++ /dev/null @@ -1,316 +0,0 @@ -/* - * Copyright (c) 2014, 2016, The Linux Foundation. All rights reserved. - * Permission to use, copy, modify, and/or distribute this software for - * any purpose with or without fee is hereby granted, provided that the - * above copyright notice and this permission notice appear in all copies. - * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES - * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR - * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES - * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN - * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT - * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. - */ - - -/** - * @defgroup dess_mirror DESS_MIRROR - * @{ - */ -#include "sw.h" -#include "hsl.h" -#include "hsl_dev.h" -#include "hsl_port_prop.h" -#include "dess_mirror.h" -#include "dess_reg.h" - -static sw_error_t -_dess_mirr_analysis_port_set(a_uint32_t dev_id, fal_port_t port_id) -{ - sw_error_t rv; - a_uint32_t val; - - HSL_DEV_ID_CHECK(dev_id); - - if (port_id != MIRROR_ANALYZER_NONE) { - if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU)) { - return SW_BAD_PARAM; - } - } - val = port_id; - HSL_REG_FIELD_SET(rv, dev_id, FORWARD_CTL0, 0, MIRROR_PORT_NUM, - (a_uint8_t *) (&val), sizeof (a_uint32_t)); - return rv; -} - -static sw_error_t -_dess_mirr_analysis_port_get(a_uint32_t dev_id, fal_port_t * port_id) -{ - sw_error_t rv; - a_uint32_t val = 0; - - HSL_DEV_ID_CHECK(dev_id); - - HSL_REG_FIELD_GET(rv, dev_id, FORWARD_CTL0, 0, MIRROR_PORT_NUM, - (a_uint8_t *) (&val), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - - *port_id = val; - return SW_OK; -} - -static sw_error_t -_dess_mirr_port_in_set(a_uint32_t dev_id, fal_port_t port_id, a_bool_t enable) -{ - sw_error_t rv; - a_uint32_t val; - - HSL_DEV_ID_CHECK(dev_id); - - if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU)) - { - return SW_BAD_PARAM; - } - - if (A_TRUE == enable) - { - val = 1; - } - else if (A_FALSE == enable) - { - val = 0; - } - else - { - return SW_BAD_PARAM; - } - - HSL_REG_FIELD_SET(rv, dev_id, PORT_LOOKUP_CTL, port_id, ING_MIRROR_EN, - (a_uint8_t *) (&val), sizeof (a_uint32_t)); - return rv; -} - -static sw_error_t -_dess_mirr_port_in_get(a_uint32_t dev_id, fal_port_t port_id, a_bool_t * enable) -{ - sw_error_t rv; - a_uint32_t val = 0; - - HSL_DEV_ID_CHECK(dev_id); - - if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU)) - { - return SW_BAD_PARAM; - } - - HSL_REG_FIELD_GET(rv, dev_id, PORT_LOOKUP_CTL, port_id, ING_MIRROR_EN, - (a_uint8_t *) (&val), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - - if (1 == val) - { - *enable = A_TRUE; - } - else - { - *enable = A_FALSE; - } - - return SW_OK; -} - -static sw_error_t -_dess_mirr_port_eg_set(a_uint32_t dev_id, fal_port_t port_id, a_bool_t enable) -{ - sw_error_t rv; - a_uint32_t val; - - HSL_DEV_ID_CHECK(dev_id); - - if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU)) - { - return SW_BAD_PARAM; - } - - if (A_TRUE == enable) - { - val = 1; - } - else if (A_FALSE == enable) - { - val = 0; - } - else - { - return SW_BAD_PARAM; - } - - HSL_REG_FIELD_SET(rv, dev_id, PORT_HOL_CTL1, port_id, EG_MIRROR_EN, - (a_uint8_t *) (&val), sizeof (a_uint32_t)); - return rv; -} - -static sw_error_t -_dess_mirr_port_eg_get(a_uint32_t dev_id, fal_port_t port_id, a_bool_t * enable) -{ - sw_error_t rv; - a_uint32_t val = 0; - - HSL_DEV_ID_CHECK(dev_id); - - if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU)) - { - return SW_BAD_PARAM; - } - - HSL_REG_FIELD_GET(rv, dev_id, PORT_HOL_CTL1, port_id, EG_MIRROR_EN, - (a_uint8_t *) (&val), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - - if (1 == val) - { - *enable = A_TRUE; - } - else - { - *enable = A_FALSE; - } - - return SW_OK; -} - -/** - * @details Comments: - * The analysis port works for both ingress and egress mirror. - * @brief Set mirror analyzer port on particular a device. - * @param[in] dev_id device id - * @param[in] port_id port id - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -dess_mirr_analysis_port_set(a_uint32_t dev_id, fal_port_t port_id) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _dess_mirr_analysis_port_set(dev_id, port_id); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Get mirror analysis port on particular a device. - * @param[in] dev_id device id - * @param[out] port_id port id - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -dess_mirr_analysis_port_get(a_uint32_t dev_id, fal_port_t * port_id) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _dess_mirr_analysis_port_get(dev_id, port_id); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Set ingress mirror status on particular a port. - * @param[in] dev_id device id - * @param[in] port_id port id - * @param[in] enable A_TRUE or A_FALSE - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -dess_mirr_port_in_set(a_uint32_t dev_id, fal_port_t port_id, a_bool_t enable) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _dess_mirr_port_in_set(dev_id, port_id, enable); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Get ingress mirror status on particular a port. - * @param[in] dev_id device id - * @param[in] port_id port id - * @param[out] enable A_TRUE or A_FALSE - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -dess_mirr_port_in_get(a_uint32_t dev_id, fal_port_t port_id, a_bool_t * enable) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _dess_mirr_port_in_get(dev_id, port_id, enable); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Set egress mirror status on a particular port. - * @param[in] dev_id device id - * @param[in] port_id port id - * @param[in] enable A_TRUE or A_FALSE - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -dess_mirr_port_eg_set(a_uint32_t dev_id, fal_port_t port_id, a_bool_t enable) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _dess_mirr_port_eg_set(dev_id, port_id, enable); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Get egress mirror status on a particular port. - * @param[in] dev_id device id - * @param[in] port_id port id - * @param[out] enable A_TRUE or A_FALSE - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -dess_mirr_port_eg_get(a_uint32_t dev_id, fal_port_t port_id, a_bool_t * enable) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _dess_mirr_port_eg_get(dev_id, port_id, enable); - HSL_API_UNLOCK; - return rv; -} - -sw_error_t -dess_mirr_init(a_uint32_t dev_id) -{ - HSL_DEV_ID_CHECK(dev_id); - -#ifndef HSL_STANDALONG - { - hsl_api_t *p_api; - - SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id)); - - p_api->mirr_analysis_port_set = dess_mirr_analysis_port_set; - p_api->mirr_analysis_port_get = dess_mirr_analysis_port_get; - p_api->mirr_port_in_set = dess_mirr_port_in_set; - p_api->mirr_port_in_get = dess_mirr_port_in_get; - p_api->mirr_port_eg_set = dess_mirr_port_eg_set; - p_api->mirr_port_eg_get = dess_mirr_port_eg_get; - } -#endif - - return SW_OK; -} - -/** - * @} - */ - diff --git a/feeds/ipq807x/qca-ssdk/src/src/hsl/dess/dess_misc.c b/feeds/ipq807x/qca-ssdk/src/src/hsl/dess/dess_misc.c deleted file mode 100755 index 9db084dcb..000000000 --- a/feeds/ipq807x/qca-ssdk/src/src/hsl/dess/dess_misc.c +++ /dev/null @@ -1,2450 +0,0 @@ -/* - * Copyright (c) 2014, 2016-2017, The Linux Foundation. All rights reserved. - * Permission to use, copy, modify, and/or distribute this software for - * any purpose with or without fee is hereby granted, provided that the - * above copyright notice and this permission notice appear in all copies. - * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES - * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR - * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES - * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN - * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT - * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. - */ - - -/** - * @defgroup dess_misc DESS_MISC - * @{ - */ -#include "sw.h" -#include "hsl.h" -#include "hsl_dev.h" -#include "hsl_port_prop.h" -#include "dess_misc.h" -#include "dess_reg.h" -#include "hsl_phy.h" - -#define DESS_MAX_FRMAE_SIZE 9216 - -#define ARP_REQ_EN_OFFSET 6 -#define ARP_ACK_EN_OFFSET 5 -#define DHCP_EN_OFFSET 4 -#define EAPOL_EN_OFFSET 3 - -#define DESS_SWITCH_INT_PHY_INT 0x8000 - - -static sw_error_t -_dess_port_misc_property_set(a_uint32_t dev_id, fal_port_t port_id, - a_bool_t enable, a_uint32_t item) -{ - sw_error_t rv; - a_uint32_t reg = 0, val; - - HSL_DEV_ID_CHECK(dev_id); - - if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU)) - { - return SW_BAD_PARAM; - } - - if (A_TRUE == enable) - { - val = 1; - } - else if (A_FALSE == enable) - { - val = 0; - } - else - { - return SW_BAD_PARAM; - } - - if (3 >= port_id) - { - HSL_REG_ENTRY_GET(rv, dev_id, FRAME_ACK_CTL0, 0, - (a_uint8_t *) (®), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - - reg &= ~(0x1UL << ((port_id << 3) + item)); - reg |= (val << ((port_id << 3) + item)); - - HSL_REG_ENTRY_SET(rv, dev_id, FRAME_ACK_CTL0, 0, - (a_uint8_t *) (®), sizeof (a_uint32_t)); - } - else - { - HSL_REG_ENTRY_GET(rv, dev_id, FRAME_ACK_CTL1, 0, - (a_uint8_t *) (®), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - - reg &= ~(0x1UL << (((port_id - 4) << 3) + item)); - reg |= (val << (((port_id - 4) << 3) + item)); - - HSL_REG_ENTRY_SET(rv, dev_id, FRAME_ACK_CTL1, 0, - (a_uint8_t *) (®), sizeof (a_uint32_t)); - } - return rv; -} - -static sw_error_t -_dess_port_misc_property_get(a_uint32_t dev_id, fal_port_t port_id, - a_bool_t * enable, a_uint32_t item) -{ - sw_error_t rv; - a_uint32_t reg = 0, val; - - HSL_DEV_ID_CHECK(dev_id); - - if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU)) - { - return SW_BAD_PARAM; - } - - if (3 >= port_id) - { - HSL_REG_ENTRY_GET(rv, dev_id, FRAME_ACK_CTL0, 0, - (a_uint8_t *) (®), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - - val = (reg >> ((port_id << 3) + item)) & 0x1UL; - } - else - { - HSL_REG_ENTRY_GET(rv, dev_id, FRAME_ACK_CTL1, 0, - (a_uint8_t *) (®), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - - val = (reg >> (((port_id - 4) << 3) + item)) & 0x1UL; - } - - if (1 == val) - { - *enable = A_TRUE; - } - else - { - *enable = A_FALSE; - } - - return SW_OK; -} - -static sw_error_t -_dess_frame_max_size_set(a_uint32_t dev_id, a_uint32_t size) -{ - a_uint32_t data; - sw_error_t rv; - - HSL_DEV_ID_CHECK(dev_id); - - if (DESS_MAX_FRMAE_SIZE < size) - { - return SW_BAD_PARAM; - } - - data = size; - HSL_REG_FIELD_SET(rv, dev_id, MAX_SIZE, 0, MAX_FRAME_SIZE, - (a_uint8_t *) (&data), sizeof (a_uint32_t)); - return rv; -} - -static sw_error_t -_dess_frame_max_size_get(a_uint32_t dev_id, a_uint32_t * size) -{ - a_uint32_t data = 0; - sw_error_t rv; - - HSL_DEV_ID_CHECK(dev_id); - - HSL_REG_FIELD_GET(rv, dev_id, MAX_SIZE, 0, MAX_FRAME_SIZE, - (a_uint8_t *) (&data), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - - *size = data; - return SW_OK; -} - -static sw_error_t -_dess_port_unk_uc_filter_set(a_uint32_t dev_id, fal_port_t port_id, - a_bool_t enable) -{ - sw_error_t rv; - a_uint32_t data = 0; - - HSL_DEV_ID_CHECK(dev_id); - - if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU)) - { - return SW_BAD_PARAM; - } - - HSL_REG_FIELD_GET(rv, dev_id, FORWARD_CTL1, 0, UNI_FLOOD_DP, - (a_uint8_t *) (&data), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - - if (A_TRUE == enable) - { - data &= (~((a_uint32_t) 0x1 << port_id)); - } - else if (A_FALSE == enable) - { - data |= (0x1 << port_id); - } - else - { - return SW_BAD_PARAM; - } - - HSL_REG_FIELD_SET(rv, dev_id, FORWARD_CTL1, 0, UNI_FLOOD_DP, - (a_uint8_t *) (&data), sizeof (a_uint32_t)); - return rv; -} - -static sw_error_t -_dess_port_unk_uc_filter_get(a_uint32_t dev_id, fal_port_t port_id, - a_bool_t * enable) -{ - sw_error_t rv; - a_uint32_t reg = 0, field; - - HSL_DEV_ID_CHECK(dev_id); - - if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU)) - { - return SW_BAD_PARAM; - } - - HSL_REG_FIELD_GET(rv, dev_id, FORWARD_CTL1, 0, UNI_FLOOD_DP, - (a_uint8_t *) (®), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - - field = reg & (0x1 << port_id); - if (field) - { - *enable = A_FALSE; - } - else - { - *enable = A_TRUE; - } - - return SW_OK; -} - -static sw_error_t -_dess_port_unk_mc_filter_set(a_uint32_t dev_id, fal_port_t port_id, - a_bool_t enable) -{ - sw_error_t rv; - a_uint32_t data = 0; - - HSL_DEV_ID_CHECK(dev_id); - - if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU)) - { - return SW_BAD_PARAM; - } - - HSL_REG_FIELD_GET(rv, dev_id, FORWARD_CTL1, 0, MUL_FLOOD_DP, - (a_uint8_t *) (&data), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - - if (A_TRUE == enable) - { - data &= (~((a_uint32_t) 0x1 << port_id)); - } - else if (A_FALSE == enable) - { - data |= (0x1 << port_id); - } - else - { - return SW_BAD_PARAM; - } - - HSL_REG_FIELD_SET(rv, dev_id, FORWARD_CTL1, 0, MUL_FLOOD_DP, - (a_uint8_t *) (&data), sizeof (a_uint32_t)); - return rv; -} - -static sw_error_t -_dess_port_unk_mc_filter_get(a_uint32_t dev_id, fal_port_t port_id, - a_bool_t * enable) -{ - sw_error_t rv; - a_uint32_t reg = 0, field; - - HSL_DEV_ID_CHECK(dev_id); - - if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU)) - { - return SW_BAD_PARAM; - } - - HSL_REG_FIELD_GET(rv, dev_id, FORWARD_CTL1, 0, MUL_FLOOD_DP, - (a_uint8_t *) (®), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - - field = reg & (0x1 << port_id); - if (field) - { - *enable = A_FALSE; - } - else - { - *enable = A_TRUE; - } - - return SW_OK; -} - -static sw_error_t -_dess_port_bc_filter_set(a_uint32_t dev_id, fal_port_t port_id, a_bool_t enable) -{ - sw_error_t rv; - a_uint32_t data = 0; - - HSL_DEV_ID_CHECK(dev_id); - - if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU)) - { - return SW_BAD_PARAM; - } - - HSL_REG_FIELD_GET(rv, dev_id, FORWARD_CTL1, 0, BC_FLOOD_DP, - (a_uint8_t *) (&data), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - - if (A_TRUE == enable) - { - data &= (~((a_uint32_t) 0x1 << port_id)); - } - else if (A_FALSE == enable) - { - data |= (0x1 << port_id); - } - else - { - return SW_BAD_PARAM; - } - - HSL_REG_FIELD_SET(rv, dev_id, FORWARD_CTL1, 0, BC_FLOOD_DP, - (a_uint8_t *) (&data), sizeof (a_uint32_t)); - return rv; -} - -static sw_error_t -_dess_port_bc_filter_get(a_uint32_t dev_id, fal_port_t port_id, - a_bool_t * enable) -{ - sw_error_t rv; - a_uint32_t reg = 0, field; - - HSL_DEV_ID_CHECK(dev_id); - - if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU)) - { - return SW_BAD_PARAM; - } - - HSL_REG_FIELD_GET(rv, dev_id, FORWARD_CTL1, 0, BC_FLOOD_DP, - (a_uint8_t *) (®), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - - field = reg & (0x1 << port_id); - if (field) - { - *enable = A_FALSE; - } - else - { - *enable = A_TRUE; - } - - return SW_OK; -} - -static sw_error_t -_dess_cpu_port_status_set(a_uint32_t dev_id, a_bool_t enable) -{ - sw_error_t rv; - a_uint32_t val; - - HSL_DEV_ID_CHECK(dev_id); - - if (A_TRUE == enable) - { - val = 1; - } - else if (A_FALSE == enable) - { - val = 0; - } - else - { - return SW_BAD_PARAM; - } - - HSL_REG_FIELD_SET(rv, dev_id, FORWARD_CTL0, 0, CPU_PORT_EN, - (a_uint8_t *) (&val), sizeof (a_uint32_t)); - return rv; -} - -static sw_error_t -_dess_cpu_port_status_get(a_uint32_t dev_id, a_bool_t * enable) -{ - sw_error_t rv; - a_uint32_t val = 0; - - HSL_DEV_ID_CHECK(dev_id); - - HSL_REG_FIELD_GET(rv, dev_id, FORWARD_CTL0, 0, CPU_PORT_EN, - (a_uint8_t *) (&val), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - - if (1 == val) - { - *enable = A_TRUE; - } - else - { - *enable = A_FALSE; - } - - return SW_OK; -} - -static sw_error_t -_dess_cpu_vid_en_set(a_uint32_t dev_id, a_bool_t enable) -{ - sw_error_t rv; - a_uint32_t val; - - HSL_DEV_ID_CHECK(dev_id); - - if (A_TRUE == enable) - { - val = 1; - } - else if (A_FALSE == enable) - { - val = 0; - } - else - { - return SW_BAD_PARAM; - } - - HSL_REG_FIELD_SET(rv, dev_id, PKT_CTRL, 0, CPU_VID_EN, - (a_uint8_t *) (&val), sizeof (a_uint32_t)); - return rv; -} - -static sw_error_t -_dess_cpu_vid_en_get(a_uint32_t dev_id, a_bool_t * enable) -{ - sw_error_t rv; - a_uint32_t val = 0; - - HSL_DEV_ID_CHECK(dev_id); - - HSL_REG_FIELD_GET(rv, dev_id, PKT_CTRL, 0, CPU_VID_EN, - (a_uint8_t *) (&val), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - - if (1 == val) - { - *enable = A_TRUE; - } - else - { - *enable = A_FALSE; - } - - return SW_OK; -} - -static sw_error_t -_dess_rtd_pppoe_en_set(a_uint32_t dev_id, a_bool_t enable) -{ - sw_error_t rv; - a_uint32_t val; - - HSL_DEV_ID_CHECK(dev_id); - - if (A_TRUE == enable) - { - val = 1; - } - else if (A_FALSE == enable) - { - val = 0; - } - else - { - return SW_BAD_PARAM; - } - - HSL_REG_FIELD_SET(rv, dev_id, PKT_CTRL, 0, RTD_PPPOE_EN, - (a_uint8_t *) (&val), sizeof (a_uint32_t)); - return rv; -} - -static sw_error_t -_dess_rtd_pppoe_en_get(a_uint32_t dev_id, a_bool_t * enable) -{ - sw_error_t rv; - a_uint32_t val = 0; - - HSL_DEV_ID_CHECK(dev_id); - - HSL_REG_FIELD_GET(rv, dev_id, PKT_CTRL, 0, RTD_PPPOE_EN, - (a_uint8_t *) (&val), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - - if (1 == val) - { - *enable = A_TRUE; - } - else - { - *enable = A_FALSE; - } - - return SW_OK; -} - - -static sw_error_t -_dess_pppoe_cmd_set(a_uint32_t dev_id, fal_fwd_cmd_t cmd) -{ - sw_error_t rv; - a_uint32_t val; - - HSL_DEV_ID_CHECK(dev_id); - - if (FAL_MAC_FRWRD == cmd) - { - val = 0; - } - else if (FAL_MAC_RDT_TO_CPU == cmd) - { - val = 1; - } - else - { - return SW_NOT_SUPPORTED; - } - - HSL_REG_FIELD_SET(rv, dev_id, FORWARD_CTL0, 0, PPPOE_RDT_EN, - (a_uint8_t *) (&val), sizeof (a_uint32_t)); - return rv; -} - -static sw_error_t -_dess_pppoe_cmd_get(a_uint32_t dev_id, fal_fwd_cmd_t * cmd) -{ - sw_error_t rv; - a_uint32_t val = 0; - - HSL_DEV_ID_CHECK(dev_id); - - HSL_REG_FIELD_GET(rv, dev_id, FORWARD_CTL0, 0, PPPOE_RDT_EN, - (a_uint8_t *) (&val), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - - if (1 == val) - { - *cmd = FAL_MAC_RDT_TO_CPU; - } - else - { - *cmd = FAL_MAC_FRWRD; - } - - return SW_OK; -} - -static sw_error_t -_dess_pppoe_status_set(a_uint32_t dev_id, a_bool_t enable) -{ - sw_error_t rv; - a_uint32_t val; - - HSL_DEV_ID_CHECK(dev_id); - - if (A_TRUE == enable) - { - val = 1; - } - else if (A_FALSE == enable) - { - val = 0; - } - else - { - return SW_BAD_PARAM; - } - - HSL_REG_FIELD_SET(rv, dev_id, FRAME_ACK_CTL1, 0, PPPOE_EN, - (a_uint8_t *) (&val), sizeof (a_uint32_t)); - return rv; -} - -static sw_error_t -_dess_pppoe_status_get(a_uint32_t dev_id, a_bool_t * enable) -{ - sw_error_t rv; - a_uint32_t val = 0; - - HSL_DEV_ID_CHECK(dev_id); - - HSL_REG_FIELD_GET(rv, dev_id, FRAME_ACK_CTL1, 0, PPPOE_EN, - (a_uint8_t *) (&val), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - - if (1 == val) - { - *enable = A_TRUE; - } - else - { - *enable = A_FALSE; - } - - return SW_OK; -} - -static sw_error_t -_dess_arp_cmd_set(a_uint32_t dev_id, fal_fwd_cmd_t cmd) -{ - sw_error_t rv; - a_uint32_t val; - - HSL_DEV_ID_CHECK(dev_id); - - if (FAL_MAC_CPY_TO_CPU == cmd) - { - val = 1; - } - else if (FAL_MAC_RDT_TO_CPU == cmd) - { - val = 0; - } - else if (FAL_MAC_FRWRD == cmd) - { - val = 2; - } - else - { - return SW_NOT_SUPPORTED; - } - - HSL_REG_FIELD_SET(rv, dev_id, FORWARD_CTL0, 0, ARP_CMD, - (a_uint8_t *) (&val), sizeof (a_uint32_t)); - return rv; -} - -static sw_error_t -_dess_arp_cmd_get(a_uint32_t dev_id, fal_fwd_cmd_t * cmd) -{ - sw_error_t rv; - a_uint32_t val = 0; - - HSL_DEV_ID_CHECK(dev_id); - - HSL_REG_FIELD_GET(rv, dev_id, FORWARD_CTL0, 0, ARP_CMD, - (a_uint8_t *) (&val), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - - if (1 == val) - { - *cmd = FAL_MAC_CPY_TO_CPU; - } - else if (0 == val) - { - *cmd = FAL_MAC_RDT_TO_CPU; - } - else - { - *cmd = FAL_MAC_FRWRD; - } - - return SW_OK; -} - -static sw_error_t -_dess_eapol_cmd_set(a_uint32_t dev_id, fal_fwd_cmd_t cmd) -{ - sw_error_t rv; - a_uint32_t val; - - HSL_DEV_ID_CHECK(dev_id); - - if (FAL_MAC_CPY_TO_CPU == cmd) - { - val = 0; - } - else if (FAL_MAC_RDT_TO_CPU == cmd) - { - val = 1; - } - else - { - return SW_NOT_SUPPORTED; - } - - HSL_REG_FIELD_SET(rv, dev_id, FORWARD_CTL0, 0, EAPOL_CMD, - (a_uint8_t *) (&val), sizeof (a_uint32_t)); - return rv; -} - -static sw_error_t -_dess_eapol_cmd_get(a_uint32_t dev_id, fal_fwd_cmd_t * cmd) -{ - sw_error_t rv; - a_uint32_t val = 0; - - HSL_DEV_ID_CHECK(dev_id); - - HSL_REG_FIELD_GET(rv, dev_id, FORWARD_CTL0, 0, EAPOL_CMD, - (a_uint8_t *) (&val), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - - if (0 == val) - { - *cmd = FAL_MAC_CPY_TO_CPU; - } - else - { - *cmd = FAL_MAC_RDT_TO_CPU; - } - - return SW_OK; -} - -#define DESS_MAX_PPPOE_SESSION 16 -#define DESS_MAX_SESSION_ID 0xffff - -static sw_error_t -_dess_pppoe_session_add(a_uint32_t dev_id, fal_pppoe_session_t * session_tbl) -{ - sw_error_t rv; - a_uint32_t reg = 0, i, valid, id, entry_idx = DESS_MAX_PPPOE_SESSION; - - HSL_DEV_ID_CHECK(dev_id); - - if (session_tbl->session_id > DESS_MAX_SESSION_ID) - { - return SW_BAD_PARAM; - } - - if ((A_FALSE == session_tbl->multi_session) - && (A_TRUE == session_tbl->uni_session)) - { - return SW_BAD_PARAM; - } - - if ((A_FALSE == session_tbl->multi_session) - && (A_FALSE == session_tbl->uni_session)) - { - return SW_BAD_PARAM; - } - - if(session_tbl->vrf_id > FAL_MAX_VRF_ID) - { - return SW_BAD_PARAM; - } - - for (i = 0; i < DESS_MAX_PPPOE_SESSION; i++) - { - HSL_REG_ENTRY_GET(rv, dev_id, PPPOE_SESSION, i, - (a_uint8_t *) (®), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - - SW_GET_FIELD_BY_REG(PPPOE_SESSION, ENTRY_VALID, valid, reg); - SW_GET_FIELD_BY_REG(PPPOE_SESSION, SEESION_ID, id, reg); - - if (!valid) - { - entry_idx = i; - } - else if (id == session_tbl->session_id) - { - return SW_ALREADY_EXIST; - } - } - - if (DESS_MAX_PPPOE_SESSION == entry_idx) - { - return SW_NO_RESOURCE; - } - - if (A_TRUE == session_tbl->uni_session) - { - SW_SET_REG_BY_FIELD(PPPOE_SESSION, ENTRY_VALID, 2, reg); - } - else - { - SW_SET_REG_BY_FIELD(PPPOE_SESSION, ENTRY_VALID, 1, reg); - } - - SW_SET_REG_BY_FIELD(PPPOE_SESSION, SEESION_ID, session_tbl->session_id, - reg); - SW_SET_REG_BY_FIELD(PPPOE_SESSION, VRF_ID, session_tbl->vrf_id, - reg); - - HSL_REG_ENTRY_SET(rv, dev_id, PPPOE_SESSION, entry_idx, - (a_uint8_t *) (®), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - - session_tbl->entry_id = entry_idx; - return SW_OK; -} - -static sw_error_t -_dess_pppoe_session_del(a_uint32_t dev_id, fal_pppoe_session_t * session_tbl) -{ - sw_error_t rv; - a_uint32_t reg = 0, i, valid, id; - - HSL_DEV_ID_CHECK(dev_id); - - if (session_tbl->session_id > DESS_MAX_SESSION_ID) - { - return SW_BAD_PARAM; - } - - for (i = 0; i < DESS_MAX_PPPOE_SESSION; i++) - { - HSL_REG_ENTRY_GET(rv, dev_id, PPPOE_SESSION, i, - (a_uint8_t *) (®), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - - SW_GET_FIELD_BY_REG(PPPOE_SESSION, ENTRY_VALID, valid, reg); - SW_GET_FIELD_BY_REG(PPPOE_SESSION, SEESION_ID, id, reg); - - if (((1 == valid) || (2 == valid)) && (id == session_tbl->session_id)) - { - SW_SET_REG_BY_FIELD(PPPOE_SESSION, ENTRY_VALID, 0, reg); - SW_SET_REG_BY_FIELD(PPPOE_SESSION, SEESION_ID, 0, reg); - SW_SET_REG_BY_FIELD(PPPOE_SESSION, VRF_ID, 0, reg); - HSL_REG_ENTRY_SET(rv, dev_id, PPPOE_SESSION, i, - (a_uint8_t *) (®), sizeof (a_uint32_t)); - return rv; - } - } - - return SW_NOT_FOUND; -} - -static sw_error_t -_dess_pppoe_session_get(a_uint32_t dev_id, fal_pppoe_session_t * session_tbl) -{ - sw_error_t rv; - a_uint32_t reg = 0, i, valid, id, vrf_id; - - HSL_DEV_ID_CHECK(dev_id); - - if (session_tbl->session_id > DESS_MAX_SESSION_ID) - { - return SW_BAD_PARAM; - } - - for (i = 0; i < DESS_MAX_PPPOE_SESSION; i++) - { - HSL_REG_ENTRY_GET(rv, dev_id, PPPOE_SESSION, i, - (a_uint8_t *) (®), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - - SW_GET_FIELD_BY_REG(PPPOE_SESSION, ENTRY_VALID, valid, reg); - SW_GET_FIELD_BY_REG(PPPOE_SESSION, SEESION_ID, id, reg); - SW_GET_FIELD_BY_REG(PPPOE_SESSION, VRF_ID, vrf_id, reg); - - if (((1 == valid) || (2 == valid)) && (id == session_tbl->session_id)) - { - if (1 == valid) - { - session_tbl->multi_session = A_TRUE; - session_tbl->uni_session = A_FALSE; - } - else - { - session_tbl->multi_session = A_TRUE; - session_tbl->uni_session = A_TRUE; - } - - session_tbl->entry_id = i; - session_tbl->vrf_id = vrf_id; - return SW_OK; - } - } - - return SW_NOT_FOUND; -} - -static sw_error_t -_dess_pppoe_session_id_set(a_uint32_t dev_id, a_uint32_t index, - a_uint32_t id) -{ - sw_error_t rv; - a_uint32_t reg; - - if (DESS_MAX_PPPOE_SESSION <= index) - { - return SW_BAD_PARAM; - } - - if (DESS_MAX_SESSION_ID < id) - { - return SW_BAD_PARAM; - } - - reg = 0; - SW_SET_REG_BY_FIELD(PPPOE_EDIT, EDIT_ID, id, reg); - HSL_REG_ENTRY_SET(rv, dev_id, PPPOE_EDIT, index, (a_uint8_t *) (®), - sizeof (a_uint32_t)); - - return rv; -} - -static sw_error_t -_dess_pppoe_session_id_get(a_uint32_t dev_id, a_uint32_t index, - a_uint32_t * id) -{ - sw_error_t rv; - a_uint32_t reg = 0, tmp; - - if (DESS_MAX_PPPOE_SESSION <= index) - { - return SW_BAD_PARAM; - } - - HSL_REG_ENTRY_GET(rv, dev_id, PPPOE_EDIT, index, (a_uint8_t *) (®), - sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - - tmp = 0; - SW_GET_FIELD_BY_REG(PPPOE_EDIT, EDIT_ID, tmp, reg); - *id = tmp; - return SW_OK; -} - -static sw_error_t -_dess_ripv1_status_set(a_uint32_t dev_id, a_bool_t enable) -{ - a_uint32_t data; - sw_error_t rv; - - HSL_DEV_ID_CHECK(dev_id); - - if (A_TRUE != hsl_port_prop_check(dev_id, 0, HSL_PP_INCL_CPU)) - { - return SW_BAD_PARAM; - } - - if (A_TRUE == enable) - { - data = 1; - } - else if (A_FALSE == enable) - { - data = 0; - } - else - { - return SW_BAD_PARAM; - } - - HSL_REG_FIELD_SET(rv, dev_id, FORWARD_CTL0, 0, RIP_CPY_EN, - (a_uint8_t *) (&data), sizeof (a_uint32_t)); - return rv; -} - -static sw_error_t -_dess_ripv1_status_get(a_uint32_t dev_id, a_bool_t * enable) -{ - a_uint32_t data = 0; - sw_error_t rv; - - HSL_DEV_ID_CHECK(dev_id); - - if (A_TRUE != hsl_port_prop_check(dev_id, 0, HSL_PP_INCL_CPU)) - { - return SW_BAD_PARAM; - } - - HSL_REG_FIELD_GET(rv, dev_id, FORWARD_CTL0, 0, RIP_CPY_EN, - (a_uint8_t *) (&data), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - - if (1 == data) - { - *enable = A_TRUE; - } - else - { - *enable = A_FALSE; - } - - return SW_OK; -} - -static sw_error_t -_dess_intr_mask_set(a_uint32_t dev_id, a_uint32_t intr_mask) -{ - sw_error_t rv; - a_uint32_t reg = 0; - - HSL_REG_ENTRY_GET(rv, dev_id, GBL_INT_MASK1, 0, (a_uint8_t *) (®), - sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - - if (intr_mask & FAL_SWITCH_INTR_LINK_STATUS) - { - reg |= DESS_SWITCH_INT_PHY_INT; - } - else - { - reg &= (~DESS_SWITCH_INT_PHY_INT); - } - - HSL_REG_ENTRY_SET(rv, dev_id, GBL_INT_MASK1, 0, (a_uint8_t *) (®), - sizeof (a_uint32_t)); - return rv; -} - -static sw_error_t -_dess_intr_mask_get(a_uint32_t dev_id, a_uint32_t * intr_mask) -{ - sw_error_t rv; - a_uint32_t reg = 0; - - *intr_mask = 0; - HSL_REG_ENTRY_GET(rv, dev_id, GBL_INT_MASK1, 0, (a_uint8_t *) (®), - sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - - if (reg & DESS_SWITCH_INT_PHY_INT) - { - *intr_mask |= FAL_SWITCH_INTR_LINK_STATUS; - } - - return SW_OK; -} - -static sw_error_t -_dess_intr_status_get(a_uint32_t dev_id, a_uint32_t * intr_status) -{ - sw_error_t rv; - a_uint32_t reg = 0; - - *intr_status = 0; - HSL_REG_ENTRY_GET(rv, dev_id, GBL_INT_STATUS1, 0, (a_uint8_t *) (®), - sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - - if (reg & DESS_SWITCH_INT_PHY_INT) - { - *intr_status |= FAL_SWITCH_INTR_LINK_STATUS; - } - - return SW_OK; -} - -static sw_error_t -_dess_intr_status_clear(a_uint32_t dev_id, a_uint32_t intr_status) -{ - sw_error_t rv; - a_uint32_t reg; - - reg = 0; - if (intr_status & FAL_SWITCH_INTR_LINK_STATUS) - { - reg |= DESS_SWITCH_INT_PHY_INT; - } - - HSL_REG_ENTRY_SET(rv, dev_id, GBL_INT_STATUS1, 0, (a_uint8_t *) (®), - sizeof (a_uint32_t)); - return rv; -} - -static sw_error_t -_dess_port_link_intr_mask_set(a_uint32_t dev_id, a_uint32_t port_id, a_uint32_t intr_mask_flag) -{ - sw_error_t rv; - a_uint32_t phy_id; - hsl_phy_ops_t *phy_drv; - - HSL_DEV_ID_CHECK(dev_id); - - if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_PHY)) - { - return SW_BAD_PARAM; - } - - SW_RTN_ON_NULL (phy_drv = hsl_phy_api_ops_get (dev_id, port_id)); - - if (NULL == phy_drv->phy_intr_mask_set) - return SW_NOT_SUPPORTED; - - rv = hsl_port_prop_get_phyid(dev_id, port_id, &phy_id); - SW_RTN_ON_ERROR(rv); - - rv = phy_drv->phy_intr_mask_set(dev_id, phy_id, intr_mask_flag); - return rv; -} - -static sw_error_t -_dess_port_link_intr_mask_get(a_uint32_t dev_id, a_uint32_t port_id, a_uint32_t * intr_mask_flag) -{ - sw_error_t rv; - a_uint32_t phy_id; - hsl_phy_ops_t *phy_drv; - - HSL_DEV_ID_CHECK(dev_id); - - if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_PHY)) - { - return SW_BAD_PARAM; - } - - SW_RTN_ON_NULL (phy_drv = hsl_phy_api_ops_get (dev_id, port_id)); - - if (NULL == phy_drv->phy_intr_mask_get) - return SW_NOT_SUPPORTED; - - rv = hsl_port_prop_get_phyid(dev_id, port_id, &phy_id); - SW_RTN_ON_ERROR(rv); - - rv = phy_drv->phy_intr_mask_get(dev_id, phy_id, intr_mask_flag); - - return rv; -} - -static sw_error_t -_dess_port_link_intr_status_get(a_uint32_t dev_id, a_uint32_t port_id, a_uint32_t * intr_mask_flag) -{ - sw_error_t rv; - a_uint32_t phy_id; - hsl_phy_ops_t *phy_drv; - - HSL_DEV_ID_CHECK(dev_id); - - if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_PHY)) - { - return SW_BAD_PARAM; - } - - SW_RTN_ON_NULL (phy_drv = hsl_phy_api_ops_get (dev_id, port_id)); - - if (NULL == phy_drv->phy_intr_status_get) - return SW_NOT_SUPPORTED; - - rv = hsl_port_prop_get_phyid(dev_id, port_id, &phy_id); - SW_RTN_ON_ERROR(rv); - - rv = phy_drv->phy_intr_status_get(dev_id, phy_id, intr_mask_flag); - return rv; -} - -static sw_error_t -_dess_intr_mask_mac_linkchg_set(a_uint32_t dev_id, a_uint32_t port_id, a_bool_t enable) -{ - sw_error_t rv; - a_uint32_t data = 0; - - HSL_DEV_ID_CHECK(dev_id); - - if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU)) - { - return SW_BAD_PARAM; - } - - HSL_REG_FIELD_GET(rv, dev_id, GBL_INT_MASK1, 0, LINK_CHG_INT_M, - (a_uint8_t *) (&data), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - - if (A_FALSE == enable) - { - data &= (~((a_uint32_t) 0x1 << port_id)); - } - else if (A_TRUE == enable) - { - data |= (0x1 << port_id); - } - else - { - return SW_BAD_PARAM; - } - - HSL_REG_FIELD_SET(rv, dev_id, GBL_INT_MASK1, 0, LINK_CHG_INT_M, - (a_uint8_t *) (&data), sizeof (a_uint32_t)); - - return rv; -} - - -static sw_error_t -_dess_intr_mask_mac_linkchg_get(a_uint32_t dev_id, a_uint32_t port_id, a_bool_t * enable) -{ - sw_error_t rv; - a_uint32_t reg = 0, field; - - HSL_DEV_ID_CHECK(dev_id); - - if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU)) - { - return SW_BAD_PARAM; - } - - HSL_REG_FIELD_GET(rv, dev_id, GBL_INT_MASK1, 0, LINK_CHG_INT_M, - (a_uint8_t *) (®), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - - field = reg & (0x1 << port_id); - if (field) - { - *enable = A_TRUE; - } - else - { - *enable = A_FALSE; - } - - return SW_OK; -} - - -static sw_error_t -_dess_intr_status_mac_linkchg_get(a_uint32_t dev_id, fal_pbmp_t* port_bitmap) -{ - sw_error_t rv; - a_uint32_t reg = 0; - - HSL_DEV_ID_CHECK(dev_id); - - HSL_REG_FIELD_GET(rv, dev_id, GBL_INT_STATUS1, 0, LINK_CHG_INT_S, - (a_uint8_t *) (®), sizeof (a_uint32_t)); - *port_bitmap = reg; - - return rv; - -} - -static sw_error_t -_dess_intr_status_mac_linkchg_clear(a_uint32_t dev_id) -{ - sw_error_t rv; - a_uint32_t reg; - - HSL_DEV_ID_CHECK(dev_id); - - HSL_REG_FIELD_GET(rv, dev_id, GBL_INT_STATUS1, 0, LINK_CHG_INT_S, - (a_uint8_t *) (®), sizeof (a_uint32_t)); - - HSL_REG_FIELD_SET(rv, dev_id, GBL_INT_STATUS1, 0, LINK_CHG_INT_S, - (a_uint8_t *) (®), sizeof (a_uint32_t)); - - return rv; - -} - -static sw_error_t -_dess_global_macaddr_set(a_uint32_t dev_id, fal_mac_addr_t * addr) -{ - sw_error_t rv; - a_uint32_t reg = 0; - - - HSL_DEV_ID_CHECK(dev_id); - - reg = (addr->uc[4] << 8) | addr->uc[5]; - HSL_REG_ENTRY_SET(rv, dev_id, GLOBAL_MAC_ADDR0, 0, (a_uint8_t *) (®), sizeof (a_uint32_t)); - reg = (addr->uc[0] << 24) | (addr->uc[1] << 16) | (addr->uc[2] << 8) | addr->uc[3]; - HSL_REG_ENTRY_SET(rv, dev_id, GLOBAL_MAC_ADDR1, 0, (a_uint8_t *) (®), sizeof (a_uint32_t)); - - return rv; -} - -static sw_error_t -_dess_global_macaddr_get(a_uint32_t dev_id, fal_mac_addr_t * addr) -{ - sw_error_t rv; - a_uint32_t reg = 0; - - - HSL_DEV_ID_CHECK(dev_id); - HSL_REG_ENTRY_GET(rv, dev_id, GLOBAL_MAC_ADDR0, 0, (a_uint8_t *) (®), sizeof (a_uint32_t)); - addr->uc[4] = (reg >> 8) & 0xff; - addr->uc[5] = reg & 0xff; - HSL_REG_ENTRY_GET(rv, dev_id, GLOBAL_MAC_ADDR1, 0, (a_uint8_t *) (®), sizeof (a_uint32_t)); - addr->uc[0] = (reg >> 24) & 0xff; - addr->uc[1] = (reg >> 16) & 0xff; - addr->uc[2] = (reg >> 8) & 0xff; - addr->uc[3] = reg; - - return rv; -} - -static sw_error_t -_dess_lldp_status_set(a_uint32_t dev_id, a_bool_t enable) -{ - sw_error_t rv; - a_uint32_t val; - - HSL_DEV_ID_CHECK(dev_id); - - if (A_TRUE == enable) - { - val = 1; - } - else if (A_FALSE == enable) - { - val = 0; - } - else - { - return SW_BAD_PARAM; - } - - HSL_REG_FIELD_SET(rv, dev_id, FRAME_ACK_CTL1, 0, LLDP_EN, - (a_uint8_t *) (&val), sizeof (a_uint32_t)); - return rv; -} - -static sw_error_t -_dess_lldp_status_get(a_uint32_t dev_id, a_bool_t * enable) -{ - sw_error_t rv; - a_uint32_t val = 0; - - HSL_DEV_ID_CHECK(dev_id); - - HSL_REG_FIELD_GET(rv, dev_id, FRAME_ACK_CTL1, 0, LLDP_EN, - (a_uint8_t *) (&val), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - - if (1 == val) - { - *enable = A_TRUE; - } - else - { - *enable = A_FALSE; - } - - return SW_OK; -} - -static sw_error_t -_dess_frame_crc_reserve_set(a_uint32_t dev_id, a_bool_t enable) -{ - sw_error_t rv; - a_uint32_t val; - - HSL_DEV_ID_CHECK(dev_id); - - if (A_TRUE == enable) - { - val = 1; - } - else if (A_FALSE == enable) - { - val = 0; - } - else - { - return SW_BAD_PARAM; - } - - HSL_REG_FIELD_SET(rv, dev_id, MAX_SIZE, 0, CRC_RESERVE, - (a_uint8_t *) (&val), sizeof (a_uint32_t)); - return rv; -} - -static sw_error_t -_dess_frame_crc_reserve_get(a_uint32_t dev_id, a_bool_t * enable) -{ - sw_error_t rv; - a_uint32_t val = 0; - - HSL_DEV_ID_CHECK(dev_id); - - HSL_REG_FIELD_GET(rv, dev_id, MAX_SIZE, 0, CRC_RESERVE, - (a_uint8_t *) (&val), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - - if (1 == val) - { - *enable = A_TRUE; - } - else - { - *enable = A_FALSE; - } - - return SW_OK; -} - - -/** - * @brief Set max frame size which device can received on a particular device. - * @details Comments: - * The granularity of packets size is byte. - * @param[in] dev_id device id - * @param[in] size packet size - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -dess_frame_max_size_set(a_uint32_t dev_id, a_uint32_t size) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _dess_frame_max_size_set(dev_id, size); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Get max frame size which device can received on a particular device. - * @details Comments: - * The unit of packets size is byte. - * @param[in] dev_id device id - * @param[out] size packet size - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -dess_frame_max_size_get(a_uint32_t dev_id, a_uint32_t * size) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _dess_frame_max_size_get(dev_id, size); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Set flooding status of unknown unicast packets on a particular port. - * @details Comments: - * If enable unknown unicast packets filter on one port then unknown - * unicast packets can't flood out from this port. - * @param[in] dev_id device id - * @param[in] port_id port id - * @param[in] enable A_TRUE or A_FALSE - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -dess_port_unk_uc_filter_set(a_uint32_t dev_id, fal_port_t port_id, - a_bool_t enable) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _dess_port_unk_uc_filter_set(dev_id, port_id, enable); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Get flooding status of unknown unicast packets on a particular port. - * @param[in] dev_id device id - * @param[in] port_id port id - * @param[out] enable A_TRUE or A_FALSE - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -dess_port_unk_uc_filter_get(a_uint32_t dev_id, fal_port_t port_id, - a_bool_t * enable) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _dess_port_unk_uc_filter_get(dev_id, port_id, enable); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Set flooding status of unknown multicast packets on a particular port. - * @details Comments: - * If enable unknown multicast packets filter on one port then unknown - * multicast packets can't flood out from this port. - * @param[in] dev_id device id - * @param[in] port_id port id - * @param[in] enable A_TRUE or A_FALSE - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -dess_port_unk_mc_filter_set(a_uint32_t dev_id, fal_port_t port_id, - a_bool_t enable) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _dess_port_unk_mc_filter_set(dev_id, port_id, enable); - HSL_API_UNLOCK; - return rv; -} - -/** @brief Get flooding status of unknown multicast packets on a particular port. - * @param[in] dev_id device id - * @param[in] port_id port id - * @param[out] enable A_TRUE or A_FALSE - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -dess_port_unk_mc_filter_get(a_uint32_t dev_id, fal_port_t port_id, - a_bool_t * enable) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _dess_port_unk_mc_filter_get(dev_id, port_id, enable); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Set flooding status of broadcast packets on a particular port. - * @details Comments: - * If enable unknown multicast packets filter on one port then unknown - * multicast packets can't flood out from this port. - * @param[in] dev_id device id - * @param[in] port_id port id - * @param[in] enable A_TRUE or A_FALSE - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -dess_port_bc_filter_set(a_uint32_t dev_id, fal_port_t port_id, a_bool_t enable) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _dess_port_bc_filter_set(dev_id, port_id, enable); - HSL_API_UNLOCK; - return rv; -} - -/** @brief Get flooding status of broadcast packets on a particular port. - * @param[in] dev_id device id - * @param[in] port_id port id - * @param[out] enable A_TRUE or A_FALSE - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -dess_port_bc_filter_get(a_uint32_t dev_id, fal_port_t port_id, - a_bool_t * enable) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _dess_port_bc_filter_get(dev_id, port_id, enable); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Set cpu port status on a particular device. - * @param[in] dev_id device id - * @param[in] enable A_TRUE or A_FALSE - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -dess_cpu_port_status_set(a_uint32_t dev_id, a_bool_t enable) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _dess_cpu_port_status_set(dev_id, enable); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Get cpu port status on a particular device. - * @param[in] dev_id device id - * @param[in] enable A_TRUE or A_FALSE - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -dess_cpu_port_status_get(a_uint32_t dev_id, a_bool_t * enable) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _dess_cpu_port_status_get(dev_id, enable); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Set pppoe packets forwarding command on a particular device. - * @details comments: - * Particular device may only support parts of forwarding commands. - * Ihis operation will take effect only after enabling pppoe packets - * hardware acknowledgement - * @param[in] dev_id device id - * @param[in] cmd forwarding command - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -dess_pppoe_cmd_set(a_uint32_t dev_id, fal_fwd_cmd_t cmd) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _dess_pppoe_cmd_set(dev_id, cmd); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Get pppoe packets forwarding command on a particular device. - * @param[in] dev_id device id - * @param[out] cmd forwarding command - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -dess_pppoe_cmd_get(a_uint32_t dev_id, fal_fwd_cmd_t * cmd) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _dess_pppoe_cmd_get(dev_id, cmd); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Set pppoe packets hardware acknowledgement status on particular device. - * @details comments: - * Particular device may only support parts of pppoe packets. - * @param[in] dev_id device id - * @param[in] enable A_TRUE or A_FALSE - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -dess_pppoe_status_set(a_uint32_t dev_id, a_bool_t enable) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _dess_pppoe_status_set(dev_id, enable); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Get pppoe packets hardware acknowledgement status on a particular device. - * @param[in] dev_id device id - * @param[out] enable A_TRUE or A_FALSE - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -dess_pppoe_status_get(a_uint32_t dev_id, a_bool_t * enable) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _dess_pppoe_status_get(dev_id, enable); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Set dhcp packets hardware acknowledgement status on a particular device. - * @param[in] dev_id device id - * @param[in] enable A_TRUE or A_FALSE - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -dess_port_dhcp_set(a_uint32_t dev_id, fal_port_t port_id, a_bool_t enable) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _dess_port_misc_property_set(dev_id, port_id, enable, DHCP_EN_OFFSET); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Get dhcp packets hardware acknowledgement status on particular device. - * @param[in] dev_id device id - * @param[out] enable A_TRUE or A_FALSE - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -dess_port_dhcp_get(a_uint32_t dev_id, fal_port_t port_id, a_bool_t * enable) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _dess_port_misc_property_get(dev_id, port_id, enable, DHCP_EN_OFFSET); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Set arp packets forwarding command on a particular device. - * @details comments: - * Particular device may only support parts of forwarding commands. - * Ihis operation will take effect only after enabling arp packets - * hardware acknowledgement - * @param[in] dev_id device id - * @param[in] cmd forwarding command - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -dess_arp_cmd_set(a_uint32_t dev_id, fal_fwd_cmd_t cmd) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _dess_arp_cmd_set(dev_id, cmd); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Get arp packets forwarding command on a particular device. - * @param[in] dev_id device id - * @param[out] cmd forwarding command - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -dess_arp_cmd_get(a_uint32_t dev_id, fal_fwd_cmd_t * cmd) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _dess_arp_cmd_get(dev_id, cmd); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Set eapol packets forwarding command on a particular device. - * @details comments: - * Particular device may only support parts of forwarding commands. - * Ihis operation will take effect only after enabling eapol packets - * hardware acknowledgement - * @param[in] dev_id device id - * @param[in] cmd forwarding command - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -dess_eapol_cmd_set(a_uint32_t dev_id, fal_fwd_cmd_t cmd) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _dess_eapol_cmd_set(dev_id, cmd); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Get eapol packets forwarding command on a particular device. - * @param[in] dev_id device id - * @param[out] cmd forwarding command - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -dess_eapol_cmd_get(a_uint32_t dev_id, fal_fwd_cmd_t * cmd) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _dess_eapol_cmd_get(dev_id, cmd); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Add a pppoe session entry to a particular device. - * The entry only for pppoe/ppp header remove. - * @param[in] dev_id device id - * @param[in] session_tbl pppoe session table - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -dess_pppoe_session_table_add(a_uint32_t dev_id, - fal_pppoe_session_t * session_tbl) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _dess_pppoe_session_add(dev_id, session_tbl); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Delete a pppoe session entry from a particular device. - * The entry only for pppoe/ppp header remove. - * @param[in] dev_id device id - * @param[in] session_tbl pppoe session table - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -dess_pppoe_session_table_del(a_uint32_t dev_id, - fal_pppoe_session_t * session_tbl) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _dess_pppoe_session_del(dev_id, session_tbl); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Get a pppoe session entry from a particular device. - * The entry only for pppoe/ppp header remove. - * @param[in] dev_id device id - * @param[out] session_tbl pppoe session table - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -dess_pppoe_session_table_get(a_uint32_t dev_id, - fal_pppoe_session_t * session_tbl) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _dess_pppoe_session_get(dev_id, session_tbl); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Set a pppoe session id entry to a particular device. - * The entry only for pppoe/ppp header add. - * @param[in] dev_id device id - * @param[in] session_tbl pppoe session table - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -dess_pppoe_session_id_set(a_uint32_t dev_id, a_uint32_t index, - a_uint32_t id) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _dess_pppoe_session_id_set(dev_id, index, id); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Get a pppoe session id entry from a particular device. - * The entry only for pppoe/ppp header add. - * @param[in] dev_id device id - * @param[out] session_tbl pppoe session table - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -dess_pppoe_session_id_get(a_uint32_t dev_id, a_uint32_t index, - a_uint32_t * id) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _dess_pppoe_session_id_get(dev_id, index, id); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Set eapol packets hardware acknowledgement status on a particular port. - * @param[in] dev_id device id - * @param[in] port_id port id - * @param[in] enable A_TRUE or A_FALSE - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -dess_eapol_status_set(a_uint32_t dev_id, a_uint32_t port_id, a_bool_t enable) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _dess_port_misc_property_set(dev_id, port_id, enable, EAPOL_EN_OFFSET); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Get eapol packets hardware acknowledgement status on a particular port. - * @param[in] dev_id device id - * @param[in] port_id port id - * @param[out] enable A_TRUE or A_FALSE - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -dess_eapol_status_get(a_uint32_t dev_id, a_uint32_t port_id, a_bool_t * enable) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _dess_port_misc_property_get(dev_id, port_id, enable, EAPOL_EN_OFFSET); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Set rip v1 packets hardware acknowledgement status on a particular port. - * @param[in] dev_id device id - * @param[in] enable A_TRUE or A_FALSE - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -dess_ripv1_status_set(a_uint32_t dev_id, a_bool_t enable) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _dess_ripv1_status_set(dev_id, enable); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Get rip v1 packets hardware acknowledgement status on a particular port. - * @param[in] dev_id device id - * @param[out] enable A_TRUE or A_FALSE - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -dess_ripv1_status_get(a_uint32_t dev_id, a_bool_t * enable) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _dess_ripv1_status_get(dev_id, enable); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Set arp req packets hardware acknowledgement status on a particular device. - * @param[in] dev_id device id - * @param[in] enable A_TRUE or A_FALSE - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -dess_port_arp_req_status_set(a_uint32_t dev_id, fal_port_t port_id, - a_bool_t enable) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _dess_port_misc_property_set(dev_id, port_id, enable, - ARP_REQ_EN_OFFSET); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Get arp req packets hardware acknowledgement status on a particular device. - * @param[in] dev_id device id - * @param[out] enable A_TRUE or A_FALSE - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -dess_port_arp_req_status_get(a_uint32_t dev_id, fal_port_t port_id, - a_bool_t * enable) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _dess_port_misc_property_get(dev_id, port_id, enable, - ARP_REQ_EN_OFFSET); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Set arp ack packets hardware acknowledgement status on a particular device. - * @param[in] dev_id device id - * @param[in] enable A_TRUE or A_FALSE - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -dess_port_arp_ack_status_set(a_uint32_t dev_id, fal_port_t port_id, - a_bool_t enable) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _dess_port_misc_property_set(dev_id, port_id, enable, - ARP_ACK_EN_OFFSET); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Get arp ack packets hardware acknowledgement status on a particular device. - * @param[in] dev_id device id - * @param[out] enable A_TRUE or A_FALSE - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -dess_port_arp_ack_status_get(a_uint32_t dev_id, fal_port_t port_id, - a_bool_t * enable) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _dess_port_misc_property_get(dev_id, port_id, enable, - ARP_ACK_EN_OFFSET); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Set switch interrupt mask on one particular device. - * @param[in] dev_id device id - * @param[in] intr_mask mask - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -dess_intr_mask_set(a_uint32_t dev_id, a_uint32_t intr_mask) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _dess_intr_mask_set(dev_id, intr_mask); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Get switch interrupt mask on one particular device. - * @param[in] dev_id device id - * @param[in] intr_mask mask - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -dess_intr_mask_get(a_uint32_t dev_id, a_uint32_t * intr_mask) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _dess_intr_mask_get(dev_id, intr_mask); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Get switch interrupt status on one particular device. - * @param[in] dev_id device id - * @param[in] intr_status status - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -dess_intr_status_get(a_uint32_t dev_id, a_uint32_t * intr_status) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _dess_intr_status_get(dev_id, intr_status); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Clear switch interrupt status on one particular device. - * @param[in] dev_id device id - * @param[in] intr_status status - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -dess_intr_status_clear(a_uint32_t dev_id, a_uint32_t intr_status) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _dess_intr_status_clear(dev_id, intr_status); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Set link interrupt mask on particular port. - * @param[in] dev_id device id - * @param[in] port_id port id - * @param[in] intr_mask_flag interrupt mask - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -dess_intr_port_link_mask_set(a_uint32_t dev_id, a_uint32_t port_id, a_uint32_t intr_mask_flag) -{ - sw_error_t rv; - HSL_API_LOCK; - rv = _dess_port_link_intr_mask_set(dev_id, port_id, intr_mask_flag); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Get link interrupt mask on particular port. - * @param[in] dev_id device id - * @param[in] port_id port id - * @param[out] intr_mask_flag interrupt mask - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -dess_intr_port_link_mask_get(a_uint32_t dev_id, a_uint32_t port_id, a_uint32_t * intr_mask_flag) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _dess_port_link_intr_mask_get(dev_id, port_id, intr_mask_flag); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Get link interrupt status on particular port. - * @param[in] dev_id device id - * @param[in] port_id port id - * @param[out] intr_mask_flag interrupt mask - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -dess_intr_port_link_status_get(a_uint32_t dev_id, a_uint32_t port_id, a_uint32_t * intr_mask_flag) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _dess_port_link_intr_status_get(dev_id, port_id, intr_mask_flag); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Set mac link change interrupt mask on particular port. - * @param[in] dev_id device id - * @param[in] port_id port id - * @param[in] enable ports intr mask enabled - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -dess_intr_mask_mac_linkchg_set(a_uint32_t dev_id, a_uint32_t port_id, a_bool_t enable) -{ - sw_error_t rv; - FAL_API_LOCK; - rv = _dess_intr_mask_mac_linkchg_set(dev_id, port_id, enable); - FAL_API_UNLOCK; - return rv; -} - -/** - * @brief Get mac link change interrupt mask on particular port. - * @param[in] dev_id device id - * @param[in] port_id port id - * @param[out] port interrupt mask or not - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -dess_intr_mask_mac_linkchg_get(a_uint32_t dev_id, a_uint32_t port_id, a_bool_t * enable) -{ - sw_error_t rv; - - FAL_API_LOCK; - rv = _dess_intr_mask_mac_linkchg_get(dev_id, port_id, enable); - FAL_API_UNLOCK; - return rv; -} - -/** - * @brief Get link change interrupt status for all ports. - * @param[in] dev_id device id - * @param[in] port_id port id - * @param[out] ports bitmap which generates interrupt - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -dess_intr_status_mac_linkchg_get(a_uint32_t dev_id, fal_pbmp_t* port_bitmap) -{ - sw_error_t rv; - - FAL_API_LOCK; - rv = _dess_intr_status_mac_linkchg_get(dev_id, port_bitmap); - FAL_API_UNLOCK; - return rv; -} - -/** - * @brief Set cpu vid enable status on a particular device. - * @param[in] dev_id device id - * @param[in] enable A_TRUE or A_FALSE - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -dess_cpu_vid_en_set(a_uint32_t dev_id, a_bool_t enable) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _dess_cpu_vid_en_set(dev_id, enable); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Get cpu vid enable status on a particular device. - * @param[in] dev_id device id - * @param[in] enable A_TRUE or A_FALSE - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -dess_cpu_vid_en_get(a_uint32_t dev_id, a_bool_t * enable) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _dess_cpu_vid_en_get(dev_id, enable); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Set RM_RTD_PPPOE_EN status on a particular device. - * @param[in] dev_id device id - * @param[in] enable A_TRUE or A_FALSE - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -dess_rtd_pppoe_en_set(a_uint32_t dev_id, a_bool_t enable) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _dess_rtd_pppoe_en_set(dev_id, enable); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Get RM_RTD_PPPOE_EN status on a particular device. - * @param[in] dev_id device id - * @param[in] enable A_TRUE or A_FALSE - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -dess_rtd_pppoe_en_get(a_uint32_t dev_id, a_bool_t * enable) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _dess_rtd_pppoe_en_get(dev_id, enable); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Clear link change interrupt status for all ports. - * @param[in] dev_id device id - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -dess_intr_status_mac_linkchg_clear(a_uint32_t dev_id) -{ - sw_error_t rv; - - FAL_API_LOCK; - rv = _dess_intr_status_mac_linkchg_clear(dev_id); - FAL_API_UNLOCK; - return rv; -} - -/** - * @brief Set global macaddr on particular device. - * @param[in] dev_id device id - * @param[in] addr addr - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -dess_global_macaddr_set(a_uint32_t dev_id, fal_mac_addr_t * addr) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _dess_global_macaddr_set(dev_id, addr); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Get global macaddr on particular device. - * @param[in] dev_id device id - * @param[out] addr addr - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -dess_global_macaddr_get(a_uint32_t dev_id, fal_mac_addr_t * addr) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _dess_global_macaddr_get(dev_id, addr); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Set lldp packets hardware acknowledgement status on particular device. - * @details comments: - * Particular device may only support parts of pppoe packets. - * @param[in] dev_id device id - * @param[in] enable A_TRUE or A_FALSE - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -dess_lldp_status_set(a_uint32_t dev_id, a_bool_t enable) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _dess_lldp_status_set(dev_id, enable); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Get lldp packets hardware acknowledgement status on a particular device. - * @param[in] dev_id device id - * @param[out] enable A_TRUE or A_FALSE - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -dess_lldp_status_get(a_uint32_t dev_id, a_bool_t * enable) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _dess_lldp_status_get(dev_id, enable); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Set frame crc reserve enable on particular device. - * @details comments: - * Particular device may only support parts of pppoe packets. - * @param[in] dev_id device id - * @param[in] enable A_TRUE or A_FALSE - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -dess_frame_crc_reserve_set(a_uint32_t dev_id, a_bool_t enable) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _dess_frame_crc_reserve_set(dev_id, enable); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Get frame crc reserve enable on particular device. - * @param[in] dev_id device id - * @param[out] enable A_TRUE or A_FALSE - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -dess_frame_crc_reserve_get(a_uint32_t dev_id, a_bool_t * enable) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _dess_frame_crc_reserve_get(dev_id, enable); - HSL_API_UNLOCK; - return rv; -} - - -sw_error_t -dess_misc_init(a_uint32_t dev_id) -{ - HSL_DEV_ID_CHECK(dev_id); - -#ifndef HSL_STANDALONG - { - hsl_api_t *p_api; - - SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id)); - - p_api->frame_max_size_set = dess_frame_max_size_set; - p_api->frame_max_size_get = dess_frame_max_size_get; - p_api->port_unk_uc_filter_set = dess_port_unk_uc_filter_set; - p_api->port_unk_uc_filter_get = dess_port_unk_uc_filter_get; - p_api->port_unk_mc_filter_set = dess_port_unk_mc_filter_set; - p_api->port_unk_mc_filter_get = dess_port_unk_mc_filter_get; - p_api->port_bc_filter_set = dess_port_bc_filter_set; - p_api->port_bc_filter_get = dess_port_bc_filter_get; - p_api->cpu_port_status_set = dess_cpu_port_status_set; - p_api->cpu_port_status_get = dess_cpu_port_status_get; - p_api->pppoe_cmd_set = dess_pppoe_cmd_set; - p_api->pppoe_cmd_get = dess_pppoe_cmd_get; - p_api->pppoe_status_set = dess_pppoe_status_set; - p_api->pppoe_status_get = dess_pppoe_status_get; - p_api->port_dhcp_set = dess_port_dhcp_set; - p_api->port_dhcp_get = dess_port_dhcp_get; - p_api->arp_cmd_set = dess_arp_cmd_set; - p_api->arp_cmd_get = dess_arp_cmd_get; - p_api->eapol_cmd_set = dess_eapol_cmd_set; - p_api->eapol_cmd_get = dess_eapol_cmd_get; - p_api->pppoe_session_table_add = dess_pppoe_session_table_add; - p_api->pppoe_session_table_del = dess_pppoe_session_table_del; - p_api->pppoe_session_table_get = dess_pppoe_session_table_get; - p_api->pppoe_session_id_set = dess_pppoe_session_id_set; - p_api->pppoe_session_id_get = dess_pppoe_session_id_get; - p_api->eapol_status_set = dess_eapol_status_set; - p_api->eapol_status_get = dess_eapol_status_get; - p_api->ripv1_status_set = dess_ripv1_status_set; - p_api->ripv1_status_get = dess_ripv1_status_get; - p_api->port_arp_req_status_set = dess_port_arp_req_status_set; - p_api->port_arp_req_status_get = dess_port_arp_req_status_get; - p_api->port_arp_ack_status_set = dess_port_arp_ack_status_set; - p_api->port_arp_ack_status_get = dess_port_arp_ack_status_get; - p_api->intr_mask_set = dess_intr_mask_set; - p_api->intr_mask_get = dess_intr_mask_get; - p_api->intr_status_get = dess_intr_status_get; - p_api->intr_status_clear = dess_intr_status_clear; - p_api->intr_port_link_mask_set = dess_intr_port_link_mask_set; - p_api->intr_port_link_mask_get = dess_intr_port_link_mask_get; - p_api->intr_port_link_status_get = dess_intr_port_link_status_get; - p_api->intr_mask_mac_linkchg_set = dess_intr_mask_mac_linkchg_set; - p_api->intr_mask_mac_linkchg_get = dess_intr_mask_mac_linkchg_get; - p_api->intr_status_mac_linkchg_get = dess_intr_status_mac_linkchg_get; - p_api->cpu_vid_en_set = dess_cpu_vid_en_set; - p_api->cpu_vid_en_get = dess_cpu_vid_en_get; - p_api->rtd_pppoe_en_set = dess_rtd_pppoe_en_set; - p_api->rtd_pppoe_en_get = dess_rtd_pppoe_en_get; - p_api->intr_status_mac_linkchg_clear = dess_intr_status_mac_linkchg_clear; - p_api->global_macaddr_set = dess_global_macaddr_set; - p_api->global_macaddr_get = dess_global_macaddr_get; - p_api->lldp_status_set = dess_lldp_status_set; - p_api->lldp_status_get = dess_lldp_status_get; - p_api->frame_crc_reserve_set = dess_frame_crc_reserve_set; - p_api->frame_crc_reserve_get = dess_frame_crc_reserve_get; - - } -#endif - - return SW_OK; -} - -/** - * @} - */ diff --git a/feeds/ipq807x/qca-ssdk/src/src/hsl/dess/dess_multicast_acl.c b/feeds/ipq807x/qca-ssdk/src/src/hsl/dess/dess_multicast_acl.c deleted file mode 100755 index 7995737fd..000000000 --- a/feeds/ipq807x/qca-ssdk/src/src/hsl/dess/dess_multicast_acl.c +++ /dev/null @@ -1,1030 +0,0 @@ -/* - * Copyright (c) 2014, 2016, The Linux Foundation. All rights reserved. - * Permission to use, copy, modify, and/or distribute this software for - * any purpose with or without fee is hereby granted, provided that the - * above copyright notice and this permission notice appear in all copies. - * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES - * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR - * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES - * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN - * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT - * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. - */ - - - -#include "fal_nat.h" -#include "fal_ip.h" -#include "hsl_api.h" -#include "sw.h" -#include "hsl.h" -#include "hsl_dev.h" -#include "hsl_port_prop.h" -#include "dess_igmp.h" -#include "dess_reg.h" -#include "dess_acl.h" -#include "fal_multi.h" -#include "sal/os/aos_lock.h" - -#if 0 -/** - * I/F prototype for complete igmpv3 & mldv2 support - */ - -/*supports 32 entries*/ -#define FAL_IGMP_SG_ENTRY_MAX 32 - -typedef enum -{ - FAL_ADDR_IPV4 = 0, - FAL_ADDR_IPV6 -} fal_addr_type_t; - -typedef struct -{ - fal_addr_type_t type; - union - { - fal_ip4_addr_t ip4_addr; - fal_ip6_addr_t ip6_addr; - } u; -} fal_igmp_sg_addr_t; - -typedef struct -{ - fal_igmp_sg_addr_t source; - fal_igmp_sg_addr_t group; - fal_pbmp_t port_map; -} fal_igmp_sg_entry_t; - -/** - * @brief set PortMap of IGMP sg entry. - * search entry according to source/group address, - * update PortMap if SG entry is found, otherwise create a new sg entry. - * @param[in] dev_id device id - * @param[in-out] entry SG entry - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -dess_igmp_sg_entry_set(a_uint32_t dev_id, fal_igmp_sg_entry_t * entry); - -/** - * @brief clear PortMap of IGMP sg entry. - * search entry according to source/group address, - * update PortMap if SG entry is found, delete the entry in case PortMap was 0. - * SW_NOT_FOUND will be returned in case search failed. - * @param[in] dev_id device id - * @param[in-out] entry SG entry - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -dess_igmp_sg_entry_clear(a_uint32_t dev_id, fal_igmp_sg_entry_t * entry); - -#define MULTI_DEBUG_ -#ifdef MULTI_DEBUG_ -#define MULTI_DEBUG(x...) aos_printk(x) -#else -#define MULTI_DEBUG(x...) -#endif - -#define FAL_ACL_LIST_MULTICAST 55 -#define FAL_MULTICAST_PRI 5 - -#define MULT_ACTION_SET 1 -#define MULT_ACTION_CLEAR 1 - -static a_uint32_t rule_nr=1; - -typedef struct -{ - a_uint8_t index; //MAX is 32 - fal_igmp_sg_entry_t entry; //Stores the specific ACL rule info -} multi_acl_info_t; -#endif - -static a_uint32_t mul_rule_nr=1; - -void -dess_multicast_init(a_uint32_t dev_id); - -HSL_LOCAL sw_error_t multi_portmap_aclreg_set(a_uint32_t pos, fal_igmp_sg_entry_t * entry); - -static multi_acl_info_t multi_acl_info[FAL_IGMP_SG_ENTRY_MAX]; -static multi_acl_info_t multi_acl_group[FAL_IGMP_SG_ENTRY_MAX]; - -static int ip6_addr_is_null(fal_ip6_addr_t *ip6) -{ - if (NULL == ip6) - { - aos_printk("Invalid ip6 address\n"); - return -1; - } - if(0 == ip6->ul[0] && 0 == ip6->ul[1] && 0 == ip6->ul[2] && 0 == ip6->ul[3]) - return 1; - else - return 0; -} -static int multi_source_is_null(fal_igmp_sg_addr_t *s) -{ - if (NULL == s) - { - aos_printk("Invalid source address\n"); - return -1; - } - if(0 == s->type && 0==s->u.ip4_addr) - return 1; - if(1 == s->type && 1 == ip6_addr_is_null(&(s->u.ip6_addr))) - return 1; - - return 0; -} - -HSL_LOCAL int iterate_multicast_acl_rule(int list_id, int start_n) -{ - a_uint32_t dev_id=0; - a_uint32_t rule_id; - sw_error_t ret; - fal_acl_rule_t rule= {0}; - - if(start_n>=FAL_IGMP_SG_ENTRY_MAX || start_n < 0) - { - return -1; - } - - for(rule_id=0; rule_id=FAL_IGMP_SG_ENTRY_MAX) - { - return -1; - } - - multi_acl_info[rule_id+start_n].index = rule_id; // consider here... index is NOT related start_n - //MULTI_DEBUG("normal query1: rule dest_ip4_val=%x, src ip4=%x, dst_ip6=%x, ports=%x\n", - //rule.dest_ip4_val, rule.src_ip4_val, rule.dest_ip6_val.ul[0], rule.ports); - - if(rule.dest_ip4_val !=0 && ip6_addr_is_null(&rule.dest_ip6_val)) //only ip4 - { - multi_acl_info[rule_id+start_n].entry.group.type = FAL_ADDR_IPV4; - multi_acl_info[rule_id+start_n].entry.source.type = FAL_ADDR_IPV4; - multi_acl_info[rule_id+start_n].entry.group.u.ip4_addr = rule.dest_ip4_val; - multi_acl_info[rule_id+start_n].entry.source.u.ip4_addr = rule.src_ip4_val; - multi_acl_info[rule_id+start_n].entry.port_map= rule.ports; - } - else if(rule.dest_ip4_val ==0 && !ip6_addr_is_null(&rule.dest_ip6_val)) //only ip6 - { - multi_acl_info[rule_id+start_n].entry.group.type = FAL_ADDR_IPV6; - multi_acl_info[rule_id+start_n].entry.source.type = FAL_ADDR_IPV6; - memcpy(&(multi_acl_info[rule_id+start_n].entry.group.u.ip6_addr), &(rule.dest_ip6_val), sizeof(rule.dest_ip6_val)); - memcpy(&(multi_acl_info[rule_id+start_n].entry.source.u.ip6_addr), &(rule.src_ip6_val), sizeof(rule.src_ip6_val)); - multi_acl_info[rule_id+start_n].entry.port_map= rule.ports; - } - if (FAL_FIELD_FLG_TST(rule.field_flg, FAL_ACL_FIELD_MAC_VID)) - { - multi_acl_info[rule_id+start_n].entry.vlan_id = rule.vid_val; - } - else - { - multi_acl_info[rule_id+start_n].entry.vlan_id = 0xffff; - } - } - - return rule_id+start_n; -} -/* -** Iterate the total 32 multicast ACL entries. - After the function completes: - 1. Stores all multicast related ACL rules in multi_acl_info[32] - 2. return the number of multicast related ACL rules -*/ -HSL_LOCAL a_uint32_t dess_multicast_acl_query(void) -{ - int start_n; - int total_n; - //a_uint32_t i; - - start_n = iterate_multicast_acl_rule(FAL_ACL_LIST_MULTICAST, 0); - if(-1 == start_n) - aos_printk("ACL rule1 is FULL\n"); - total_n = iterate_multicast_acl_rule(FAL_ACL_LIST_MULTICAST+1, start_n); - if(-1 == total_n) - aos_printk("ACL rule2 is FULL\n"); - - MULTI_DEBUG("KKK, the total ACL rule number is %d, (G,S) number=%d\n", total_n, start_n); - /* - for(i=0;i>6)&0x3) == 0x3) || (((msk_valid>>6)&0x3) == 0x2)) - { - rv = multi_portmap_aclreg_set(i, entry); - break; - } - else if ((((msk_valid>>6)&0x3)) == 0x0 || (((msk_valid>>6)&0x3) == 0x1)) - { - rv = multi_portmap_aclreg_set(i, entry); - continue; - } - else - { - aos_printk("The rule valid bit:6 7 is wrong!!!"); - break; - } - } - return rv; -} -HSL_LOCAL sw_error_t multi_portmap_aclreg_set(a_uint32_t pos, fal_igmp_sg_entry_t * entry) -{ - a_uint32_t i, base, addr; - a_uint32_t dev_id=0; - sw_error_t rv; - a_uint32_t act[3]= {0}; - fal_pbmp_t pm; - - pm = entry->port_map; - - base = DESS_FILTER_ACT_ADDR + (pos << 4); - for (i = 0; i < 3; i++) - { - addr = base + (i << 2); - HSL_REG_ENTRY_GEN_GET(rv, dev_id, addr, sizeof (a_uint32_t), - (a_uint8_t *) (&act[i]), - sizeof (a_uint32_t)); - //MULTI_DEBUG("2:Get register value 0x%x =%x\n", addr, act[i]); - SW_RTN_ON_ERROR(rv); - } - - act[1] &= ~(0x7<<29); // clear the high 3 bits - act[1] |= (pm&0x7)<<29; //the low 3 bits of pm means redirect port 0,1,2 - - /* New modification: update acl ACTION register from DENY to redirect */ - if (((act[2]>>6)&0x7) == 0x7) //DENY mode - { - if(pm) - { - act[2] &= ~(0x7<<6);//clear DENY bits - act[2] |= (0x1<<4); //DES_PORT_EN set 1, enable - } - } - else if (((act[2]>>4)&0x1) == 0x1) //redirect mode - { - if(pm==0) - { - act[2] &= ~(0x1<<4);//clear redirect bits - act[2] |= (0x7<<6); //set to DENY - } - } - - act[2] &= ~0xf; //clear the low 4 bits of port 3,4,5,6 - act[2] |= (pm>>3)&0xf; - - addr = base + (1<<2); - HSL_REG_ENTRY_GEN_SET(rv, dev_id, addr, sizeof (a_uint32_t), - (a_uint8_t *) (&act[1]), sizeof (a_uint32_t)); - addr = base + (2<<2); - HSL_REG_ENTRY_GEN_SET(rv, dev_id, addr, sizeof (a_uint32_t), - (a_uint8_t *) (&act[2]), sizeof (a_uint32_t)); - MULTI_DEBUG("pos=%d, before sync portmap, the new act=%x %x\n", pos, act[1],act[2]); - if((rv = dess_acl_rule_sync_multi_portmap(dev_id, pos, act)) < 0) - aos_printk("Sync multicast portmap error\n"); - return rv; -} - -HSL_LOCAL int multi_get_dp(void) -{ - a_uint32_t addr; - a_uint32_t dev_id=0; - sw_error_t rv; - int val=0; - - addr = 0x624;//GLOBAL_FW_CTRL1 - HSL_REG_ENTRY_GEN_GET(rv, dev_id, addr, sizeof (a_uint32_t), - (a_uint8_t *) (&val), - sizeof (a_uint32_t)); - if (rv != SW_OK) - aos_printk("Get entry value error\n"); - - val = (val>>24)&0x7f; //30:24, IGMP_JOIN_LEAVE_DP - - return val; -} -static int old_bind_p=-1; -HSL_LOCAL int multi_acl_bind(void) -{ - int bind_p; - int i; - - bind_p = multi_get_dp(); - if(bind_p == old_bind_p) - return 0; - old_bind_p = bind_p; - - for(i=0; i<7; i++) - { - dess_acl_list_unbind(0, FAL_ACL_LIST_MULTICAST, FAL_ACL_DIREC_IN, FAL_ACL_BIND_PORT, i); - dess_acl_list_unbind(0, FAL_ACL_LIST_MULTICAST+1, FAL_ACL_DIREC_IN, FAL_ACL_BIND_PORT, i); - } - - if(bind_p==0) - { - for(i=0; i<7; i++) - { - dess_acl_list_bind(0, FAL_ACL_LIST_MULTICAST, FAL_ACL_DIREC_IN, FAL_ACL_BIND_PORT, i); - dess_acl_list_bind(0, FAL_ACL_LIST_MULTICAST+1, FAL_ACL_DIREC_IN, FAL_ACL_BIND_PORT, i); - } - } - else - { - for(i=0; i<7; i++) - if((bind_p>>i) &0x1) - { - dess_acl_list_bind(0, FAL_ACL_LIST_MULTICAST, FAL_ACL_DIREC_IN, FAL_ACL_BIND_PORT, i); - dess_acl_list_bind(0, FAL_ACL_LIST_MULTICAST+1, FAL_ACL_DIREC_IN, FAL_ACL_BIND_PORT, i); - } - else - continue; - } - return 0; -} -/* -** Only update the related portmap from the privious input. -*/ -HSL_LOCAL sw_error_t dess_multicast_acl_update( int list_id, int acl_index, fal_igmp_sg_entry_t * entry, int action) -{ - a_uint32_t dev_id=0; - a_uint32_t rule_pos; - sw_error_t rv = SW_OK; - - if(acl_index<0) - { - aos_printk("Something is wrong...\n"); - return SW_FAIL; - } - - rule_pos = dess_acl_rule_get_offset(dev_id, list_id, multi_acl_group[acl_index].index); - if(MULT_ACTION_SET == action) - { - multi_acl_group[acl_index].entry.port_map |= entry->port_map; - if(entry->port_map == 0) - { - multi_acl_group[acl_index].entry.port_map = 0; - } - } - else if(MULT_ACTION_CLEAR == action) - multi_acl_group[acl_index].entry.port_map &= ~(entry->port_map); - - rv = multi_portmap_aclreg_set_all(rule_pos, &multi_acl_group[acl_index].entry); - - multi_acl_bind(); //Here need extra bind since IGMP join/leave would happen - return rv; -} - -HSL_LOCAL sw_error_t dess_multicast_acl_del(int list_id, int index) -{ - sw_error_t rv; - int rule_id; - - rule_id = multi_acl_group[index].index; - - rv = dess_acl_rule_delete(0, list_id, rule_id, 1); - multi_acl_bind(); //Here need extra bind since IGMP join/leave would happen - return rv; -} - -/* -** Add new acl rule with parameters: DIP, SIP, redirect port. -*/ -HSL_LOCAL sw_error_t dess_multicast_acl_add(int list_id, fal_igmp_sg_entry_t * entry) -{ - sw_error_t val; - a_uint32_t pos; - fal_acl_rule_t acl= {0}; - - /* IPv4 multicast */ - if( entry->group.type == FAL_ADDR_IPV4 ) - { - MULTI_DEBUG("KKK1, group[%d][%x], source[%d][%x]\n",entry->group.type, - entry->group.u.ip4_addr, entry->source.type, entry->source.u.ip4_addr); - - acl.rule_type = FAL_ACL_RULE_IP4; - - if(entry->group.u.ip4_addr!= 0) - { - acl.dest_ip4_val = entry->group.u.ip4_addr; - acl.dest_ip4_mask = 0xffffffff;//e->ip.dmsk.s_addr; - FAL_FIELD_FLG_SET(acl.field_flg, FAL_ACL_FIELD_IP4_DIP); - } - if(entry->source.u.ip4_addr!= 0) - { - acl.src_ip4_val = entry->source.u.ip4_addr; - acl.src_ip4_mask = 0xffffffff;//e->ip.smsk.s_addr; - FAL_FIELD_FLG_SET(acl.field_flg, FAL_ACL_FIELD_IP4_SIP); - } - if( entry->port_map==0 ) - FAL_ACTION_FLG_SET ( acl.action_flg, FAL_ACL_ACTION_DENY); - else - //FAL_FIELD_FLG_SET(acl.field_flg, FAL_ACL_FIELD_INVERSE_ALL); - FAL_ACTION_FLG_SET ( acl.action_flg, FAL_ACL_ACTION_PERMIT ); - - /* Be careful, _dess_acl_action_parse() will block FAL_ACL_ACTION_DENY action, So we change it. */ - if( entry->port_map ) - { - FAL_ACTION_FLG_SET(acl.action_flg, FAL_ACL_ACTION_REDPT); - acl.ports = entry->port_map; - } - } - else if( entry->group.type == FAL_ADDR_IPV6 ) - { - MULTI_DEBUG("KKK2, group[%d][%x], source[%d][%x], pm=%x\n",entry->group.type, - entry->group.u.ip6_addr.ul[0], entry->source.type, entry->source.u.ip6_addr.ul[0], entry->port_map); - - acl.rule_type = FAL_ACL_RULE_IP6; - - if(!ip6_addr_is_null(&(entry->group.u.ip6_addr))) - { - memcpy(&acl.dest_ip6_val, &(entry->group.u.ip6_addr), sizeof(entry->group.u.ip6_addr)); - acl.dest_ip6_mask.ul[0] = 0xffffffff; - acl.dest_ip6_mask.ul[1] = 0xffffffff; - acl.dest_ip6_mask.ul[2] = 0xffffffff; - acl.dest_ip6_mask.ul[3] = 0xffffffff; - FAL_FIELD_FLG_SET(acl.field_flg, FAL_ACL_FIELD_IP6_DIP); - } - if(!ip6_addr_is_null(&(entry->source.u.ip6_addr))) - { - memcpy(&acl.src_ip6_val, &(entry->source.u.ip6_addr), sizeof(entry->source.u.ip6_addr)); - acl.src_ip6_mask.ul[0] = 0xffffffff; - acl.src_ip6_mask.ul[1] = 0xffffffff; - acl.src_ip6_mask.ul[2] = 0xffffffff; - acl.src_ip6_mask.ul[3] = 0xffffffff; - FAL_FIELD_FLG_SET(acl.field_flg, FAL_ACL_FIELD_IP6_SIP); - } - - if( entry->port_map==0 ) - FAL_ACTION_FLG_SET ( acl.action_flg, FAL_ACL_ACTION_DENY); - else - //FAL_FIELD_FLG_SET(acl.field_flg, FAL_ACL_FIELD_INVERSE_ALL); - FAL_ACTION_FLG_SET ( acl.action_flg, FAL_ACL_ACTION_PERMIT ); - - /* Be careful, _dess_acl_action_parse() will block FAL_ACL_ACTION_DENY action, So we change it. */ - if( entry->port_map ) - { - FAL_ACTION_FLG_SET(acl.action_flg, FAL_ACL_ACTION_REDPT); - acl.ports = entry->port_map; - } - } - - if (entry->vlan_id < 4096) - { - FAL_FIELD_FLG_SET(acl.field_flg, FAL_ACL_FIELD_MAC_VID); - acl.vid_val = entry->vlan_id; - acl.vid_op = FAL_ACL_FIELD_MASK; - acl.vid_mask = 0xfff; - } - - pos = dess_multicast_acl_total_n(list_id); - - MULTI_DEBUG("In dess_multicast_acl_add, list_id=%d, rule_id=%d\n", list_id, pos); - val = dess_acl_rule_add(0, list_id, pos, mul_rule_nr, &acl); - - multi_acl_bind(); - - return val; -} - - -HSL_LOCAL int iterate_multicast_acl_group(a_uint32_t number, fal_igmp_sg_entry_t * entry) -{ - int count=0; - int i; - - if (number == 0) - return 0; //no any ACL rules based the query - - for(i=0; igroup.type, entry->group.u.ip6_addr.ul[0], entry->port_map);*/ - - if(0 == memcmp(&(multi_acl_info[i].entry.group), &(entry->group), sizeof(entry->group))) - { - memcpy(&multi_acl_group[count], &multi_acl_info[i], sizeof(multi_acl_info[i])); - count++;//return the real number of multi_acl_group[] - MULTI_DEBUG("in iterate_multicast_acl_group, count=%d, i=%d\n", count, i); - } - } - - return count; -} - -HSL_LOCAL int mult_acl_has_entry(fal_igmp_sg_addr_t * group, fal_igmp_sg_addr_t *source) -{ - int rule_id; - int ret = 0; -#if 0 - if(source != NULL) - { - MULTI_DEBUG("new group[%d]= %x %x %x %x, new source[%d]=%x %x %x %x\n", - group->type, group->u.ip6_addr.ul[0], group->u.ip6_addr.ul[1], group->u.ip6_addr.ul[2], group->u.ip6_addr.ul[3], - source->type, source->u.ip6_addr.ul[0], source->u.ip6_addr.ul[1], source->u.ip6_addr.ul[2], source->u.ip6_addr.ul[3]); - - MULTI_DEBUG("old group[%d]= %x %x %x %x, old source[%d]=%x %x %x %x\n", - multi_acl_group[0].entry.group.type, multi_acl_group[0].entry.group.u.ip6_addr.ul[0], - multi_acl_group[0].entry.group.u.ip6_addr.ul[1], multi_acl_group[0].entry.group.u.ip6_addr.ul[2], multi_acl_group[0].entry.group.u.ip6_addr.ul[3], - multi_acl_group[0].entry.source.type, multi_acl_group[0].entry.source.u.ip6_addr.ul[0], - multi_acl_group[0].entry.source.u.ip6_addr.ul[1], multi_acl_group[0].entry.source.u.ip6_addr.ul[2], multi_acl_group[0].entry.source.u.ip6_addr.ul[3]); - } -#endif - if(source == NULL) - { - for(rule_id=0; rule_idport_map, g_source->source.u.ip4_addr, g_source->group.u.ip4_addr, - g_star->port_map, g_star->source.u.ip4_addr,g_star->group.u.ip4_addr);*/ - - if(multi_source_is_null(&(g_star->source))) - { - if((g_source->port_map|g_star->port_map) == g_star->port_map) - { - return 0; - } - } - - return 1; -} - - -HSL_LOCAL int portmap_clear_type(int count, int index, fal_pbmp_t portmap) -{ - if(count>=0 && index0; this means there're (G,*) and (G,S) - { - //if the new clear portmap will cause (G,S)=(G,*), Delete the (G,S) - if((multi_acl_group[index].entry.port_map & (~portmap)) == multi_acl_group[count].entry.port_map) - return 1; //delete - - - //The following means there must be at least one bit clear wrong. Clear the (G,*) portmap. - if( ((multi_acl_group[index].entry.port_map & (~portmap)) & (multi_acl_group[count].entry.port_map)) - != (multi_acl_group[count].entry.port_map)) - return 0; - - return 2; //Normal update - } - return 0; -} -sw_error_t dess_igmp_sg_entry_set(a_uint32_t dev_id, fal_igmp_sg_entry_t * entry) -{ - int number, count; - int new_index=0; - sw_error_t rv; - int action = MULT_ACTION_SET; - int i=0; - - HSL_API_LOCK; - (void)dess_multicast_init(0); - aos_mem_zero(multi_acl_info, FAL_IGMP_SG_ENTRY_MAX * sizeof (multi_acl_info_t)); - aos_mem_zero(multi_acl_group, FAL_IGMP_SG_ENTRY_MAX * sizeof (multi_acl_info_t)); - MULTI_DEBUG("Before query: group=%x, source=%x, portmap=%x\n", entry->group.u.ip4_addr, entry->source.u.ip4_addr, entry->port_map); - //number is the total multicast ACL rules amount, stores in multi_acl_info[]; - number = dess_multicast_acl_query(); - - if(number > FAL_IGMP_SG_ENTRY_MAX) - return SW_FAIL; - //count the total specific multicast group ACL rules, stores in multi_acl_group[]; count <=number - count = iterate_multicast_acl_group(number, entry); - //new_index-1 is the found entry index in multi_acl_group[], the real index is [new_index-1], 0 means no entry - new_index = mult_acl_has_entry(&entry->group, &entry->source); - - MULTI_DEBUG("Start entry set: number=%d, count=%d, new_index=%d, pm=%x\n", number, count, new_index, entry->port_map); - if( 0==multi_source_is_null(&entry->source) ) // new entry is (G, S) - { - MULTI_DEBUG("the new entry is (G,S)\n"); - if(count>0 && 0 == portmap_valid(entry, &(multi_acl_group[count-1].entry))) //specfic group entry exist,(G,S) or (G,*) - { - //return SW_NO_CHANGE; // The new portmap is Not valid - MULTI_DEBUG("KKK, modified 1 !!!\n"); - } - - if(0 == new_index) //new entry, need add - { -#if 0 - /*The method: - 1. predict if the portmap should be modified. - 2. add new acl rule with new portmap value. - */ - if((tmp_index = mult_acl_has_entry(&entry->group, NULL))>0) // (G, *) entry exist - { - /*Here the update should new (G, S) OR orignal (G,*) portmap, - be careful, entry's portmap value will be modified, so I use tmp_entry. - */ - memcpy(tmp_entry, entry, sizeof(fal_igmp_sg_entry_t)); - MULTI_DEBUG("Here, (G,*) exist! tmp_index=%d\n", tmp_index); - sw_multicast_acl_update(FAL_ACL_LIST_MULTICAST+1, tmp_index-1, tmp_entry, action); - - dess_multicast_acl_add(FAL_ACL_LIST_MULTICAST, tmp_entry); - return SW_OK; - } -#endif - dess_multicast_acl_add(FAL_ACL_LIST_MULTICAST, entry); - MULTI_DEBUG("Here, need add (G, S), portmap=%x\n", entry->port_map); - return SW_OK; - } - else - { - //Here update Just: the old exist entry portmap OR the new entry portmap - dess_multicast_acl_update(FAL_ACL_LIST_MULTICAST, new_index-1, entry, action); - return SW_OK; - } - } //end of memcmp - else // new entry is (G, *) - { - if(0 == new_index) //new entry, need add - { - dess_multicast_acl_add(FAL_ACL_LIST_MULTICAST+1, entry); - rv = SW_OK; - } - else if(new_index > 0) // (G, *) entry exist? - { - //Update exist (G, *) portmap with new portmap - MULTI_DEBUG("(G,*) exist, before update, new_index=%d\n", new_index ); - dess_multicast_acl_update(FAL_ACL_LIST_MULTICAST+1, new_index-1, entry, action); - rv = SW_OK; - } - - if(new_index>0&&count>1) //(G,S*) and (G,*) exist, new entry is (G,*) - { - for(i=count-2; i>=0&&i0) //only exist (G,S*) orignally - { - for(i=count-1; i>=0&&iport_map); - dess_multicast_acl_del(FAL_ACL_LIST_MULTICAST, i); - rv = SW_NO_MORE; - } - else - { - MULTI_DEBUG("2:Start update all (G,S),i=%d, portmap=%x\n", i, entry->port_map); - //Update all (G,S) entry portmap with new(G, *) portmap - dess_multicast_acl_update(FAL_ACL_LIST_MULTICAST, i, entry, action); - rv = SW_OK; - } - } - } - } - HSL_API_UNLOCK; - return rv; -} - -sw_error_t dess_igmp_sg_entry_clear(a_uint32_t dev_id, fal_igmp_sg_entry_t * entry) -{ - a_uint32_t number, count; - int new_index=0; - sw_error_t rv = SW_OK; - int action= MULT_ACTION_CLEAR; - int i=0; - int pm_type; - - HSL_API_LOCK; - (void)dess_multicast_init(0); - aos_mem_zero(multi_acl_info, FAL_IGMP_SG_ENTRY_MAX * sizeof (multi_acl_info_t)); - aos_mem_zero(multi_acl_group, FAL_IGMP_SG_ENTRY_MAX * sizeof (multi_acl_info_t)); - //number is the total multicast ACL rules amount, stores in multi_acl_info[]; - number = dess_multicast_acl_query(); - if(number > FAL_IGMP_SG_ENTRY_MAX) - return SW_FAIL; - //count the total specific multicast group ACL rules, stores in multi_acl_group[]; count <=number - count = iterate_multicast_acl_group(number, entry); - if(count == 0) - return SW_OK; - //new_index-1 is the found entry index in multi_acl_group[] - new_index = mult_acl_has_entry(&entry->group, &entry->source); - - MULTI_DEBUG("Start entry clear: number=%d, count=%d, new_index=%d\n", number, count, new_index); - if(0 == new_index || new_index > FAL_IGMP_SG_ENTRY_MAX || count > FAL_IGMP_SG_ENTRY_MAX) //new entry, the user command is wrong - { - return SW_NO_SUCH; - } - - if( 0==multi_source_is_null(&entry->source) ) // new entry is (G, S) - { - if (portmap_null(new_index-1, entry->port_map)) - { - MULTI_DEBUG("KKK entry clear, new(G,S), with null portmap. \n"); - dess_multicast_acl_del(FAL_ACL_LIST_MULTICAST, new_index-1); - return SW_OK; - } - else - { - MULTI_DEBUG("KKK entry clear, new(G,S), with NOT null portmap. \n"); - /* If (G,*) doesn't exist, [count-1] is the last specfic group, maybe(G,*) */ - if(0 == multi_source_is_null(&(multi_acl_group[count-1].entry.source))) - { - dess_multicast_acl_update(FAL_ACL_LIST_MULTICAST, new_index-1, entry, action); - } - else //(G,*) exist - { - pm_type = portmap_clear_type(count-1, new_index-1, entry->port_map); - if(pm_type == 0) - return SW_NO_CHANGE; - else if(pm_type == 1) - { - dess_multicast_acl_del(FAL_ACL_LIST_MULTICAST, new_index-1); - return SW_OK; - } - else - { - //normal update; consider here...wangson - dess_multicast_acl_update(FAL_ACL_LIST_MULTICAST, new_index-1, entry, action); - } - } - } - return SW_OK; - } - else //clear entry is (G,*) - { - MULTI_DEBUG("Here, new_index[%d]>=0, new portmap to clear is %x\n", new_index, entry->port_map); - if (portmap_null(new_index-1, entry->port_map)) - { - dess_multicast_acl_del(FAL_ACL_LIST_MULTICAST+1, new_index-1); - rv = SW_OK; - } - else - { - MULTI_DEBUG("Update (G,*)!, new_index=%d, pm=%x\n", new_index, entry->port_map); - dess_multicast_acl_update(FAL_ACL_LIST_MULTICAST+1, new_index-1, entry, action); - } - MULTI_DEBUG("KKK, ready clear (G, S*), count=%d\n", count); -#if 0 - if(count>1) // (G, S*) entry exist, if count=1 here, only exist(G,*)entry - { - //count must >=2 - for(i=count-2; i>=0; i--) - { - if(portmap_null(i, entry->port_map)) - { - MULTI_DEBUG("portmap_null, i=%d\n", i); - dess_multicast_acl_del(FAL_ACL_LIST_MULTICAST, i); - rv = SW_NO_MORE; - } - else - { - //Update all (G,S) entry portmap with new(G, *) portmap - dess_multicast_acl_update(FAL_ACL_LIST_MULTICAST, i, entry, action); - rv = SW_OK; - } - } - } -#else - if(count>1) // (G, S*) entry exist, if count=1 here, only exist(G,*)entry - { - //count must >=2 - for(i=count-2; i>=0&&iport_map))) == - multi_acl_group[i].entry.port_map) - dess_multicast_acl_del(FAL_ACL_LIST_MULTICAST, i); - else - //Update all (G,S) entry portmap with new(G, *) portmap - dess_multicast_acl_update(FAL_ACL_LIST_MULTICAST, i, entry, action); - rv = SW_OK; - } - } -#endif - } - HSL_API_UNLOCK; - return rv; -} - -static void -print_ip4addr(char * param_name, a_uint32_t * buf, - a_uint32_t size) -{ - a_uint32_t i; - fal_ip4_addr_t ip4; - - ip4 = *((fal_ip4_addr_t *) buf); - aos_printk("%s", param_name); - for (i = 0; i < 3; i++) - { - aos_printk("%d.", (ip4 >> (24 - i * 8)) & 0xff); - } - aos_printk("%d", (ip4 & 0xff)); -} -static void -print_ip6addr(char * param_name, a_uint32_t * buf, - a_uint32_t size) -{ - a_uint32_t i; - fal_ip6_addr_t ip6; - - ip6 = *(fal_ip6_addr_t *) buf; - aos_printk("%s", param_name); - for (i = 0; i < 3; i++) - { - aos_printk("%x:%x:", (ip6.ul[i] >> 16) & 0xffff, ip6.ul[i] & 0xffff); - } - aos_printk("%x:%x", (ip6.ul[3] >> 16) & 0xffff, ip6.ul[3] & 0xffff); -} -sw_error_t dess_igmp_sg_entry_show(a_uint32_t dev_id) -{ - a_uint32_t number; - int i; - - HSL_API_LOCK; - (void)dess_multicast_init(0); - aos_mem_zero(multi_acl_info, FAL_IGMP_SG_ENTRY_MAX * sizeof (multi_acl_info_t)); - aos_mem_zero(multi_acl_group, FAL_IGMP_SG_ENTRY_MAX * sizeof (multi_acl_info_t)); - //number is the total multicast ACL rules amount, stores in multi_acl_info[]; - number = dess_multicast_acl_query(); - - for(i=0; i FAL_IGMP_SG_ENTRY_MAX) - { - HSL_API_UNLOCK; - return SW_FAIL; - } - info->cnt = number; - - for(i=0; iacl_info[i]), &(multi_acl_info[i]), sizeof(multi_acl_info_t)); - } - HSL_API_UNLOCK; - - return SW_OK; -} - diff --git a/feeds/ipq807x/qca-ssdk/src/src/hsl/dess/dess_nat.c b/feeds/ipq807x/qca-ssdk/src/src/hsl/dess/dess_nat.c deleted file mode 100755 index cbe9d5788..000000000 --- a/feeds/ipq807x/qca-ssdk/src/src/hsl/dess/dess_nat.c +++ /dev/null @@ -1,3213 +0,0 @@ -/* - * Copyright (c) 2014-2016, The Linux Foundation. All rights reserved. - * Permission to use, copy, modify, and/or distribute this software for - * any purpose with or without fee is hereby granted, provided that the - * above copyright notice and this permission notice appear in all copies. - * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES - * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR - * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES - * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN - * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT - * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. - */ - - -/** - * @defgroup dess_ip DESS_NAT - * @{ - */ - -#include "sw.h" -#include "hsl.h" -#include "hsl_dev.h" -#include "hsl_port_prop.h" -#include "dess_nat.h" -#include "dess_reg.h" -#if defined(IN_NAT_HELPER) -#include "dess_nat_helper.h" -#endif - -#define DESS_HOST_ENTRY_DATA0_ADDR 0x0e80 -#define DESS_HOST_ENTRY_DATA1_ADDR 0x0e84 -#define DESS_HOST_ENTRY_DATA2_ADDR 0x0e88 -#define DESS_HOST_ENTRY_DATA3_ADDR 0x0e8c -#define DESS_HOST_ENTRY_DATA4_ADDR 0x0e90 -#define DESS_HOST_ENTRY_DATA5_ADDR 0x0e94 -#define DESS_HOST_ENTRY_DATA6_ADDR 0x0e98 -#define DESS_HOST_ENTRY_DATA7_ADDR 0x0e58 - -#define DESS_HOST_ENTRY_REG_NUM 8 - -#define DESS_NAT_ENTRY_FLUSH 1 -#define DESS_NAT_ENTRY_ADD 2 -#define DESS_NAT_ENTRY_DEL 3 -#define DESS_NAT_ENTRY_NEXT 4 -#define DESS_NAT_ENTRY_SEARCH 5 - -#define DESS_ENTRY_NAPT 0 -#define DESS_ENTRY_FLOW 1 -#define DESS_ENTRY_NAT 2 -#define DESS_ENTRY_ARP 3 - -#define DESS_PUB_ADDR_NUM 16 -#define DESS_PUB_ADDR_TBL0_ADDR 0x5aa00 -#define DESS_PUB_ADDR_TBL1_ADDR 0x5aa04 -#define DESS_PUB_ADDR_EDIT0_ADDR 0x02100 -#define DESS_PUB_ADDR_EDIT1_ADDR 0x02104 -#define DESS_PUB_ADDR_OFFLOAD_ADDR 0x2f000 -#define DESS_PUB_ADDR_VALID_ADDR 0x2f040 - -#define DESS_NAT_ENTRY_NUM 32 -#define DESS_NAPT_ENTRY_NUM 1024 - -#define DESS_NAT_COUTER_ADDR 0x2b000 - -#define DESS_NAT_PORT_NUM 255 - -aos_lock_t dess_nat_lock; -static a_uint32_t dess_nat_snap[SW_MAX_NR_DEV] = { 0 }; -extern a_uint32_t dess_nat_global_status; - -#if defined(IN_NAT_HELPER) -extern void nat_helper_cookie_del(a_uint32_t hw_index); -#endif - -static sw_error_t -_dess_nat_feature_check(a_uint32_t dev_id) -{ - sw_error_t rv; - a_uint32_t entry = 0; - - HSL_REG_FIELD_GET(rv, dev_id, MASK_CTL, 0, DEVICE_ID, - (a_uint8_t *) (&entry), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - - if (DESS_DEVICE_ID == entry) - { - return SW_OK; - } - else - { - return SW_NOT_SUPPORTED; - } -} - -static sw_error_t -_dess_ip_prvaddr_sw_to_hw(a_uint32_t dev_id, fal_ip4_addr_t sw_addr, - a_uint32_t * hw_addr) -{ - /* - sw_error_t rv; - a_uint32_t data; - - HSL_REG_FIELD_GET(rv, dev_id, PRVIP_CTL, 0, BASEADDR_SEL, - (a_uint8_t *) (&data), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - - if (data) { - *hw_addr = (sw_addr & 0xff) | (((sw_addr >> 16) & 0xf) << 8); - } else { - *hw_addr = sw_addr & 0xfff; - } - */ - *hw_addr = sw_addr; - return SW_OK; -} - -static sw_error_t -_dess_ip_prvaddr_hw_to_sw(a_uint32_t dev_id, a_uint32_t hw_addr, - fal_ip4_addr_t * sw_addr) -{ - /* - sw_error_t rv; - a_uint32_t data, addr; - - HSL_REG_FIELD_GET(rv, dev_id, PRVIP_CTL, 0, BASEADDR_SEL, - (a_uint8_t *) (&data), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - - HSL_REG_FIELD_GET(rv, dev_id, PRVIP_CTL, 0, IP4_BASEADDR, - (a_uint8_t *) (&addr), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - - if (data) { - *sw_addr = ((addr & 0xff) << 8) | (((addr >> 8) & 0xfff) << 8) - | (hw_addr & 0xff) | (((hw_addr >> 8) & 0xf) << 16); - } else { - *sw_addr = (addr << 12) | (hw_addr & 0xfff); - } - */ - *sw_addr = hw_addr; - - return SW_OK; -} - -static sw_error_t -_dess_nat_counter_get(a_uint32_t dev_id, a_uint32_t cnt_id, - a_uint32_t counter[4]) -{ - sw_error_t rv; - a_uint32_t i, addr; - - addr = DESS_NAT_COUTER_ADDR + (cnt_id << 4); - for (i = 0; i < 4; i++) - { - HSL_REG_ENTRY_GEN_GET(rv, dev_id, addr, sizeof (a_uint32_t), - (a_uint8_t *) (&(counter[i])), - sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - - addr += 4; - } - - return SW_OK; -} - -static sw_error_t -_dess_nat_entry_commit(a_uint32_t dev_id, a_uint32_t entry_type, a_uint32_t op) -{ - a_uint32_t busy = 1, i = 0x9000000, entry = 0; - sw_error_t rv; - - - while (busy && --i) - { - HSL_REG_ENTRY_GET(rv, dev_id, HOST_ENTRY7, 0, (a_uint8_t *) (&entry), - sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - SW_GET_FIELD_BY_REG(HOST_ENTRY7, TBL_BUSY, busy, entry); - } - - if (i == 0) - { - printk("busy 1\n"); - return SW_BUSY; - } - - SW_SET_REG_BY_FIELD(HOST_ENTRY7, TBL_BUSY, 1, entry); - SW_SET_REG_BY_FIELD(HOST_ENTRY7, TBL_SEL, entry_type, entry); - SW_SET_REG_BY_FIELD(HOST_ENTRY7, ENTRY_FUNC, op, entry); - - HSL_REG_ENTRY_SET(rv, dev_id, HOST_ENTRY7, 0, (a_uint8_t *) (&entry), - sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - - busy = 1; - i = 0x90000000; - while (busy && --i) - { - HSL_REG_ENTRY_GET(rv, dev_id, HOST_ENTRY7, 0, (a_uint8_t *) (&entry), - sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - SW_GET_FIELD_BY_REG(HOST_ENTRY7, TBL_BUSY, busy, entry); -#if 1 - if(DESS_NAT_ENTRY_SEARCH == op && busy) break; -#endif - } - - if (i == 0) - { - printk("busy 2\n"); - return SW_BUSY; - } - - /* hardware requirement, we should delay... */ - if ((DESS_NAT_ENTRY_FLUSH == op) && ((DESS_ENTRY_NAPT == entry_type) || - (DESS_ENTRY_FLOW == entry_type))) - { - aos_mdelay(10); - } - - /* hardware requirement, we should read again... */ - HSL_REG_ENTRY_GET(rv, dev_id, HOST_ENTRY7, 0, (a_uint8_t *) (&entry), - sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - - SW_GET_FIELD_BY_REG(HOST_ENTRY7, TBL_STAUS, busy, entry); - if (!busy) - { - if (DESS_NAT_ENTRY_NEXT == op) - { - return SW_NO_MORE; - } - else if (DESS_NAT_ENTRY_SEARCH == op) - { - return SW_NOT_FOUND; - } - else - { - return SW_FAIL; - } - } - - return SW_OK; -} - -static sw_error_t -_dess_nat_sw_to_hw(a_uint32_t dev_id, fal_nat_entry_t * entry, a_uint32_t reg[]) -{ - sw_error_t rv; - a_uint32_t data; - - if (FAL_NAT_ENTRY_TRANS_IPADDR_INDEX & entry->flags) - { - return SW_BAD_PARAM; - } - - reg[0] = entry->trans_addr; - - if (FAL_NAT_ENTRY_PORT_CHECK & entry->flags) - { - SW_SET_REG_BY_FIELD(NAT_ENTRY3, PORT_EN, 1, reg[3]); - SW_SET_REG_BY_FIELD(NAT_ENTRY1, PORT_RANGE, entry->port_range, reg[1]); - if (DESS_NAT_PORT_NUM < entry->port_range) - { - return SW_BAD_PARAM; - } - SW_SET_REG_BY_FIELD(NAT_ENTRY1, PORT_NUM, entry->port_num, reg[1]); - } - else - { - SW_SET_REG_BY_FIELD(NAT_ENTRY3, PORT_EN, 0, reg[3]); - } - - rv = _dess_ip_prvaddr_sw_to_hw(dev_id, entry->src_addr, &data); - SW_RTN_ON_ERROR(rv); - - SW_SET_REG_BY_FIELD(NAT_ENTRY1, PRV_IPADDR0, data, reg[1]); - SW_SET_REG_BY_FIELD(NAT_ENTRY2, PRV_IPADDR1, (data >> 8), reg[2]); - - if (FAL_MAC_FRWRD == entry->action) - { - if (A_TRUE == entry->mirror_en) - { - SW_SET_REG_BY_FIELD(NAT_ENTRY2, ACTION, 0, reg[2]); - } - else - { - SW_SET_REG_BY_FIELD(NAT_ENTRY2, ACTION, 3, reg[2]); - } - } - else if (FAL_MAC_CPY_TO_CPU == entry->action) - { - SW_SET_REG_BY_FIELD(NAT_ENTRY2, ACTION, 2, reg[2]); - } - else if (FAL_MAC_RDT_TO_CPU == entry->action) - { - SW_SET_REG_BY_FIELD(NAT_ENTRY2, ACTION, 1, reg[2]); - } - else - { - return SW_NOT_SUPPORTED; - } - - if (A_TRUE == entry->counter_en) - { - SW_SET_REG_BY_FIELD(NAT_ENTRY2, CNT_EN, 1, reg[2]); - SW_SET_REG_BY_FIELD(NAT_ENTRY2, CNT_IDX, entry->counter_id, reg[2]); - } - - if (FAL_NAT_ENTRY_PROTOCOL_ANY & entry->flags) - { - data = 3; - } - else if ((FAL_NAT_ENTRY_PROTOCOL_TCP & entry->flags) - && (FAL_NAT_ENTRY_PROTOCOL_UDP & entry->flags)) - { - data = 2; - } - else if (FAL_NAT_ENTRY_PROTOCOL_TCP & entry->flags) - { - data = 0; - } - else if (FAL_NAT_ENTRY_PROTOCOL_UDP & entry->flags) - { - data = 1; - } - else - { - return SW_BAD_PARAM; - } - - SW_SET_REG_BY_FIELD(NAT_ENTRY3, PRO_TYP, data, reg[3]); - SW_SET_REG_BY_FIELD(NAT_ENTRY3, VRF_ID, entry->vrf_id, reg[3]); - - SW_SET_REG_BY_FIELD(NAT_ENTRY2, HASH_KEY, entry->slct_idx, reg[2]); - - SW_SET_REG_BY_FIELD(NAT_ENTRY3, ENTRY_VALID, 1, reg[3]); - SW_SET_REG_BY_FIELD(HOST_ENTRY7, TBL_IDX, entry->entry_id, reg[7]); - return SW_OK; -} - -static sw_error_t -_dess_nat_hw_to_sw(a_uint32_t dev_id, a_uint32_t reg[], fal_nat_entry_t * entry) -{ - sw_error_t rv; - a_uint32_t data, cnt[4] = {0}; - - entry->trans_addr = reg[0]; - - SW_GET_FIELD_BY_REG(NAT_ENTRY3, PORT_EN, data, reg[3]); - if (data) - { - entry->flags |= FAL_NAT_ENTRY_PORT_CHECK; - SW_GET_FIELD_BY_REG(NAT_ENTRY1, PORT_RANGE, data, reg[1]); - entry->port_range = data; - SW_GET_FIELD_BY_REG(NAT_ENTRY1, PORT_NUM, data, reg[1]); - entry->port_num = data; - } - - SW_GET_FIELD_BY_REG(NAT_ENTRY1, PRV_IPADDR0, data, reg[1]); - entry->src_addr = data; - SW_GET_FIELD_BY_REG(NAT_ENTRY2, PRV_IPADDR1, data, reg[2]); - data = (entry->src_addr & 0xff) | (data << 8); - - rv = _dess_ip_prvaddr_hw_to_sw(dev_id, data, &(entry->src_addr)); - SW_RTN_ON_ERROR(rv); - - SW_GET_FIELD_BY_REG(NAT_ENTRY2, ACTION, data, reg[2]); - entry->action = FAL_MAC_FRWRD; - if (0 == data) - { - entry->mirror_en = A_TRUE; - } - else if (2 == data) - { - entry->action = FAL_MAC_CPY_TO_CPU; - } - else if (1 == data) - { - entry->action = FAL_MAC_RDT_TO_CPU; - } - - SW_GET_FIELD_BY_REG(NAT_ENTRY2, CNT_EN, data, reg[2]); - if (data) - { - entry->counter_en = A_TRUE; - SW_GET_FIELD_BY_REG(NAT_ENTRY2, CNT_IDX, entry->counter_id, reg[2]); - - rv = _dess_nat_counter_get(dev_id, entry->counter_id, cnt); - SW_RTN_ON_ERROR(rv); - - entry->ingress_packet = cnt[0]; - entry->ingress_byte = cnt[1]; - entry->egress_packet = cnt[2]; - entry->egress_byte = cnt[3]; - } - else - { - entry->counter_en = A_FALSE; - } - - SW_GET_FIELD_BY_REG(NAT_ENTRY3, PRO_TYP, data, reg[3]); - - if (3 == data) - { - entry->flags |= FAL_NAT_ENTRY_PROTOCOL_ANY; - } - else if (2 == data) - { - entry->flags |= FAL_NAT_ENTRY_PROTOCOL_TCP; - entry->flags |= FAL_NAT_ENTRY_PROTOCOL_UDP; - } - else if (1 == data) - { - entry->flags |= FAL_NAT_ENTRY_PROTOCOL_UDP; - } - else if (0 == data) - { - entry->flags |= FAL_NAT_ENTRY_PROTOCOL_TCP; - } - - SW_GET_FIELD_BY_REG(NAT_ENTRY3, VRF_ID, data, reg[3]); - entry->vrf_id = data; - - SW_GET_FIELD_BY_REG(NAT_ENTRY2, HASH_KEY, data, reg[2]); - entry->slct_idx = data; - - return SW_OK; -} - -static sw_error_t -_dess_napt_sw_to_hw(a_uint32_t dev_id, fal_napt_entry_t * entry, - a_uint32_t reg[]) -{ - sw_error_t rv; - a_uint32_t data; - - reg[0] = entry->dst_addr; - - SW_SET_REG_BY_FIELD(NAPT_ENTRY1, DST_PORT, entry->dst_port, reg[1]); - SW_SET_REG_BY_FIELD(NAPT_ENTRY1, SRC_PORT, entry->src_port, reg[1]); - SW_SET_REG_BY_FIELD(NAPT_ENTRY2, TRANS_PORT, entry->trans_port, reg[2]); - - rv = _dess_ip_prvaddr_sw_to_hw(dev_id, entry->src_addr, &data); - SW_RTN_ON_ERROR(rv); - - SW_SET_REG_BY_FIELD(NAPT_ENTRY2, SRC_IPADDR0, (data & 0xfff), reg[2]); - SW_SET_REG_BY_FIELD(NAPT_ENTRY3, SRC_IPADDR1, (data >> 12), reg[3]); - - SW_SET_REG_BY_FIELD(NAPT_ENTRY2, TRANS_IPADDR, entry->trans_addr, reg[2]); - - if (FAL_MAC_FRWRD == entry->action) - { - if (A_TRUE == entry->mirror_en) - { - SW_SET_REG_BY_FIELD(NAPT_ENTRY3, ACTION, 0, reg[3]); - } - else - { - SW_SET_REG_BY_FIELD(NAPT_ENTRY3, ACTION, 3, reg[3]); - } - } - else if (FAL_MAC_CPY_TO_CPU == entry->action) - { - SW_SET_REG_BY_FIELD(NAPT_ENTRY3, ACTION, 2, reg[3]); - } - else if (FAL_MAC_RDT_TO_CPU == entry->action) - { - SW_SET_REG_BY_FIELD(NAPT_ENTRY3, ACTION, 1, reg[3]); - } - else - { - return SW_NOT_SUPPORTED; - } - - if (A_TRUE == entry->counter_en) - { - SW_SET_REG_BY_FIELD(NAPT_ENTRY3, CNT_EN, 1, reg[3]); - SW_SET_REG_BY_FIELD(NAPT_ENTRY3, CNT_IDX, entry->counter_id, reg[3]); - } - - if (A_TRUE == entry->priority_en) - { - SW_SET_REG_BY_FIELD(NAPT_ENTRY3, PRIORITY_EN, 1, reg[3]); - SW_SET_REG_BY_FIELD(NAPT_ENTRY3, PRIORITY_VAL, entry->priority_val, reg[3]); - } - - data = 2; - if (FAL_NAT_ENTRY_PROTOCOL_TCP & entry->flags) - { - data = 0; - } - else if (FAL_NAT_ENTRY_PROTOCOL_UDP & entry->flags) - { - data = 1; - } - else if (FAL_NAT_ENTRY_PROTOCOL_PPTP & entry->flags) - { - data = 3; - } - SW_SET_REG_BY_FIELD(NAPT_ENTRY3, PROT_TYP, data, reg[3]); - - SW_SET_REG_BY_FIELD(NAPT_ENTRY4, AGE_FLAG, entry->status, reg[4]); - SW_SET_REG_BY_FIELD(NAPT_ENTRY4, AGE_SYNC, entry->aging_sync, reg[4]); - SW_SET_REG_BY_FIELD(NAPT_ENTRY4, VRF_ID, entry->vrf_id, reg[4]); - SW_SET_REG_BY_FIELD(NAPT_ENTRY4, FLOW_COOKIE, entry->flow_cookie, reg[4]); - SW_SET_REG_BY_FIELD(NAPT_ENTRY4, LOAD_BALANCE, entry->load_balance, reg[4]); - return SW_OK; -} - -static sw_error_t -_dess_napt_hw_to_sw(a_uint32_t dev_id, a_uint32_t reg[], - fal_napt_entry_t * entry) -{ - sw_error_t rv; - a_uint32_t data, cnt[4] = {0}; - - entry->dst_addr = reg[0]; - - SW_GET_FIELD_BY_REG(NAPT_ENTRY1, DST_PORT, entry->dst_port, reg[1]); - SW_GET_FIELD_BY_REG(NAPT_ENTRY1, SRC_PORT, entry->src_port, reg[1]); - SW_GET_FIELD_BY_REG(NAPT_ENTRY2, TRANS_PORT, entry->trans_port, reg[2]); - - SW_GET_FIELD_BY_REG(NAPT_ENTRY2, SRC_IPADDR0, data, reg[2]); - entry->src_addr = data; - SW_GET_FIELD_BY_REG(NAPT_ENTRY3, SRC_IPADDR1, data, reg[3]); - data = (entry->src_addr & 0xfff) | (data << 12); - rv = _dess_ip_prvaddr_hw_to_sw(dev_id, data, &(entry->src_addr)); - SW_RTN_ON_ERROR(rv); - - entry->flags |= FAL_NAT_ENTRY_TRANS_IPADDR_INDEX; - SW_GET_FIELD_BY_REG(NAPT_ENTRY2, TRANS_IPADDR, entry->trans_addr, reg[2]); - - SW_GET_FIELD_BY_REG(NAPT_ENTRY3, ACTION, data, reg[3]); - entry->action = FAL_MAC_FRWRD; - if (0 == data) - { - entry->mirror_en = A_TRUE; - } - else if (2 == data) - { - entry->action = FAL_MAC_CPY_TO_CPU; - } - else if (1 == data) - { - entry->action = FAL_MAC_RDT_TO_CPU; - } - - SW_GET_FIELD_BY_REG(NAPT_ENTRY3, CNT_EN, data, reg[3]); - if (data) - { - entry->counter_en = A_TRUE; - SW_GET_FIELD_BY_REG(NAPT_ENTRY3, CNT_IDX, entry->counter_id, reg[3]); - - rv = _dess_nat_counter_get(dev_id, entry->counter_id, cnt); - SW_RTN_ON_ERROR(rv); - - entry->ingress_packet = cnt[0]; - entry->ingress_byte = cnt[1]; - entry->egress_packet = cnt[2]; - entry->egress_byte = cnt[3]; - } - else - { - entry->counter_en = A_FALSE; - } - - SW_GET_FIELD_BY_REG(NAPT_ENTRY3, PRIORITY_EN, data, reg[3]); - if (data) - { - entry->priority_en = A_TRUE; - SW_GET_FIELD_BY_REG(NAPT_ENTRY3, PRIORITY_VAL, entry->priority_val, reg[3]); - } - else - { - entry->priority_en = A_FALSE; - } - - SW_GET_FIELD_BY_REG(NAPT_ENTRY3, PROT_TYP, data, reg[3]); - if (0 == data) - { - entry->flags |= FAL_NAT_ENTRY_PROTOCOL_TCP; - } - else if (1 == data) - { - entry->flags |= FAL_NAT_ENTRY_PROTOCOL_UDP; - } - else if (3 == data) - { - entry->flags |= FAL_NAT_ENTRY_PROTOCOL_PPTP; - } - - SW_GET_FIELD_BY_REG(NAPT_ENTRY4, AGE_FLAG, entry->status, reg[4]); - SW_GET_FIELD_BY_REG(NAPT_ENTRY4, AGE_SYNC, entry->aging_sync, reg[4]); - SW_GET_FIELD_BY_REG(NAPT_ENTRY4, VRF_ID, entry->vrf_id, reg[4]); - SW_GET_FIELD_BY_REG(NAPT_ENTRY4, FLOW_COOKIE, entry->flow_cookie, reg[4]); - SW_GET_FIELD_BY_REG(NAPT_ENTRY4, LOAD_BALANCE, entry->load_balance, reg[4]); - return SW_OK; -} - -static sw_error_t -_dess_nat_down_to_hw(a_uint32_t dev_id, a_uint32_t reg[]) -{ - sw_error_t rv; - a_uint32_t i, addr; - - for (i = 0; i < DESS_HOST_ENTRY_REG_NUM; i++) - { - if((DESS_HOST_ENTRY_REG_NUM - 1) == i) - { - addr = DESS_HOST_ENTRY_DATA7_ADDR; - } - else - { - addr = DESS_HOST_ENTRY_DATA0_ADDR + (i << 2); - } - - HSL_REG_ENTRY_GEN_SET(rv, dev_id, addr, sizeof (a_uint32_t), - (a_uint8_t *) (®[i]), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - } - - return SW_OK; -} - -static sw_error_t -_dess_nat_up_to_sw(a_uint32_t dev_id, a_uint32_t reg[]) -{ - sw_error_t rv; - a_uint32_t i, addr; - - for (i = 0; i < DESS_HOST_ENTRY_REG_NUM; i++) - { - if((DESS_HOST_ENTRY_REG_NUM -1) == i) - { - addr = DESS_HOST_ENTRY_DATA7_ADDR; - } - else - { - addr = DESS_HOST_ENTRY_DATA0_ADDR + (i << 2); - } - - HSL_REG_ENTRY_GEN_GET(rv, dev_id, addr, sizeof (a_uint32_t), - (a_uint8_t *) (®[i]), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - } - - return SW_OK; -} - -static sw_error_t -_dess_nat_add(a_uint32_t dev_id, fal_nat_entry_t * entry) -{ - sw_error_t rv; - a_uint32_t i, reg[DESS_HOST_ENTRY_REG_NUM] = { 0 }; - - HSL_DEV_ID_CHECK(dev_id); - - rv = _dess_nat_feature_check(dev_id); - SW_RTN_ON_ERROR(rv); - - for (i = 0; i < DESS_NAT_ENTRY_NUM; i++) - { - if (!(dess_nat_snap[dev_id] & (0x1 << i))) - { - break; - } - } - - if (DESS_NAT_ENTRY_NUM == i) - { - return SW_NO_RESOURCE; - } - - entry->entry_id = i; - - rv = _dess_nat_sw_to_hw(dev_id, entry, reg); - SW_RTN_ON_ERROR(rv); - - rv = _dess_nat_down_to_hw(dev_id, reg); - SW_RTN_ON_ERROR(rv); - - rv = _dess_nat_entry_commit(dev_id, DESS_ENTRY_NAT, DESS_NAT_ENTRY_ADD); - SW_RTN_ON_ERROR(rv); - - dess_nat_snap[dev_id] |= (0x1 << i); - entry->entry_id = i; - return SW_OK; -} - -static sw_error_t -_dess_nat_del(a_uint32_t dev_id, a_uint32_t del_mode, fal_nat_entry_t * entry) -{ - sw_error_t rv; - a_uint32_t reg[DESS_HOST_ENTRY_REG_NUM] = { 0 }; - - HSL_DEV_ID_CHECK(dev_id); - - rv = _dess_nat_feature_check(dev_id); - SW_RTN_ON_ERROR(rv); - - if (FAL_NAT_ENTRY_ID_EN & del_mode) - { - SW_SET_REG_BY_FIELD(HOST_ENTRY7, ENTRY_FUNC, DESS_NAT_ENTRY_DEL, reg[7]); - SW_SET_REG_BY_FIELD(HOST_ENTRY7, TBL_IDX, entry->entry_id, reg[7]); - - rv = _dess_nat_down_to_hw(dev_id, reg); - SW_RTN_ON_ERROR(rv); - - rv = _dess_nat_entry_commit(dev_id, DESS_ENTRY_NAT, DESS_NAT_ENTRY_DEL); - SW_RTN_ON_ERROR(rv); - - dess_nat_snap[dev_id] &= (~(0x1 << entry->entry_id)); - } - else - { - rv = _dess_nat_down_to_hw(dev_id, reg); - SW_RTN_ON_ERROR(rv); - - rv = _dess_nat_entry_commit(dev_id, DESS_ENTRY_NAT, DESS_NAT_ENTRY_FLUSH); - SW_RTN_ON_ERROR(rv); - - dess_nat_snap[dev_id] = 0; - } - - return SW_OK; -} - -static sw_error_t -_dess_nat_get(a_uint32_t dev_id, a_uint32_t get_mode, fal_nat_entry_t * entry) -{ - sw_error_t rv; - a_uint32_t reg[DESS_HOST_ENTRY_REG_NUM] = { 0 }; - - HSL_DEV_ID_CHECK(dev_id); - - rv = _dess_nat_feature_check(dev_id); - SW_RTN_ON_ERROR(rv); - - if (FAL_NAT_ENTRY_ID_EN != get_mode) - { - return SW_NOT_SUPPORTED; - } - - if (!(dess_nat_snap[dev_id] & (0x1 << entry->entry_id))) - { - return SW_NOT_FOUND; - } - - SW_SET_REG_BY_FIELD(HOST_ENTRY7, TBL_IDX, entry->entry_id, reg[7]); - - rv = _dess_nat_down_to_hw(dev_id, reg); - SW_RTN_ON_ERROR(rv); - - rv = _dess_nat_entry_commit(dev_id, DESS_ENTRY_NAT, DESS_NAT_ENTRY_SEARCH); - SW_RTN_ON_ERROR(rv); - - rv = _dess_nat_up_to_sw(dev_id, reg); - SW_RTN_ON_ERROR(rv); - - rv = _dess_nat_hw_to_sw(dev_id, reg, entry); - return rv; -} - -static sw_error_t -_dess_nat_next(a_uint32_t dev_id, a_uint32_t next_mode, - fal_nat_entry_t * nat_entry) -{ - a_uint32_t i, idx, reg[DESS_HOST_ENTRY_REG_NUM] = { 0 }; - sw_error_t rv; - - HSL_DEV_ID_CHECK(dev_id); - - rv = _dess_nat_feature_check(dev_id); - SW_RTN_ON_ERROR(rv); - - if (FAL_NEXT_ENTRY_FIRST_ID == nat_entry->entry_id) - { - idx = 0; - } - else - { - if ((DESS_NAT_ENTRY_NUM - 1) == nat_entry->entry_id) - { - return SW_NO_MORE; - } - else - { - idx = nat_entry->entry_id + 1; - } - } - - for (i = idx; i < DESS_NAT_ENTRY_NUM; i++) - { - if (dess_nat_snap[dev_id] & (0x1 << i)) - { - break; - } - } - - if (DESS_NAT_ENTRY_NUM == i) - { - return SW_NO_MORE; - } - - SW_SET_REG_BY_FIELD(HOST_ENTRY7, TBL_IDX, i, reg[7]); - - rv = _dess_nat_down_to_hw(dev_id, reg); - SW_RTN_ON_ERROR(rv); - - rv = _dess_nat_entry_commit(dev_id, DESS_ENTRY_NAT, DESS_NAT_ENTRY_SEARCH); - SW_RTN_ON_ERROR(rv); - - rv = _dess_nat_up_to_sw(dev_id, reg); - SW_RTN_ON_ERROR(rv); - - aos_mem_zero(nat_entry, sizeof (fal_nat_entry_t)); - - rv = _dess_nat_hw_to_sw(dev_id, reg, nat_entry); - SW_RTN_ON_ERROR(rv); - - nat_entry->entry_id = i; - return SW_OK; -} - -static sw_error_t -_dess_nat_counter_bind(a_uint32_t dev_id, a_uint32_t entry_id, - a_uint32_t cnt_id, a_bool_t enable) -{ - sw_error_t rv; - a_uint32_t reg[DESS_HOST_ENTRY_REG_NUM] = { 0 }; - - HSL_DEV_ID_CHECK(dev_id); - - rv = _dess_nat_feature_check(dev_id); - SW_RTN_ON_ERROR(rv); - - if (!(dess_nat_snap[dev_id] & (0x1 << entry_id))) - { - return SW_NOT_FOUND; - } - - SW_SET_REG_BY_FIELD(HOST_ENTRY7, TBL_IDX, entry_id, reg[7]); - - rv = _dess_nat_entry_commit(dev_id, DESS_ENTRY_NAT, DESS_NAT_ENTRY_SEARCH); - SW_RTN_ON_ERROR(rv); - - rv = _dess_nat_up_to_sw(dev_id, reg); - SW_RTN_ON_ERROR(rv); - - if (A_FALSE == enable) - { - SW_SET_REG_BY_FIELD(NAT_ENTRY2, CNT_EN, 0, reg[2]); - } - else if (A_TRUE == enable) - { - SW_SET_REG_BY_FIELD(NAT_ENTRY2, CNT_EN, 1, reg[2]); - SW_SET_REG_BY_FIELD(NAT_ENTRY2, CNT_IDX, cnt_id, reg[2]); - } - else - { - return SW_BAD_PARAM; - } - - /* needn't set TBL_IDX, keep hardware register value */ - - rv = _dess_nat_entry_commit(dev_id, DESS_ENTRY_NAT, DESS_NAT_ENTRY_DEL); - SW_RTN_ON_ERROR(rv); - - rv = _dess_nat_down_to_hw(dev_id, reg); - SW_RTN_ON_ERROR(rv); - - /* needn't set TBL_IDX, keep hardware register value */ - - rv = _dess_nat_entry_commit(dev_id, DESS_ENTRY_NAT, DESS_NAT_ENTRY_ADD); - return rv; -} - -static sw_error_t -_dess_napt_add(a_uint32_t dev_id, fal_napt_entry_t * entry) -{ - sw_error_t rv; - a_uint32_t reg[DESS_HOST_ENTRY_REG_NUM] = { 0 }; - - HSL_DEV_ID_CHECK(dev_id); - - rv = _dess_nat_feature_check(dev_id); - SW_RTN_ON_ERROR(rv); - - HSL_DEV_ID_CHECK(dev_id); - - rv = _dess_napt_sw_to_hw(dev_id, entry, reg); - SW_RTN_ON_ERROR(rv); - - aos_lock_bh(&dess_nat_lock); - rv = _dess_nat_down_to_hw(dev_id, reg); - if (rv != SW_OK) { - aos_unlock_bh(&dess_nat_lock); - return rv; - } - - rv = _dess_nat_entry_commit(dev_id, DESS_ENTRY_NAPT, DESS_NAT_ENTRY_ADD); - if (rv != SW_OK) { - aos_unlock_bh(&dess_nat_lock); - return rv; - } - - rv = _dess_nat_up_to_sw(dev_id, reg); - if (rv != SW_OK) { - aos_unlock_bh(&dess_nat_lock); - return rv; - } - - SW_GET_FIELD_BY_REG(HOST_ENTRY7, TBL_IDX, entry->entry_id, reg[7]); - aos_unlock_bh(&dess_nat_lock); - return SW_OK; -} - -static sw_error_t -_dess_napt_del(a_uint32_t dev_id, a_uint32_t del_mode, fal_napt_entry_t * entry) -{ - sw_error_t rv; - a_uint32_t data, reg[DESS_HOST_ENTRY_REG_NUM] = { 0 }; - - HSL_DEV_ID_CHECK(dev_id); - - rv = _dess_nat_feature_check(dev_id); - SW_RTN_ON_ERROR(rv); - - if (FAL_NAT_ENTRY_ID_EN & del_mode) - { - return SW_NOT_SUPPORTED; - } - - if (FAL_NAT_ENTRY_KEY_EN & del_mode) - { - rv = _dess_napt_sw_to_hw(dev_id, entry, reg); - SW_RTN_ON_ERROR(rv); - - aos_lock_bh(&dess_nat_lock); - rv = _dess_nat_down_to_hw(dev_id, reg); - if (rv != SW_OK) { - aos_unlock_bh(&dess_nat_lock); - return rv; - } - - rv = _dess_nat_entry_commit(dev_id, DESS_ENTRY_NAPT, DESS_NAT_ENTRY_DEL); - if (rv != SW_OK) { - aos_unlock_bh(&dess_nat_lock); - return rv; - } - - rv = _dess_nat_up_to_sw(dev_id, reg); - if (rv != SW_OK) { - aos_unlock_bh(&dess_nat_lock); - return rv; - } - - SW_GET_FIELD_BY_REG(HOST_ENTRY7, TBL_IDX, entry->entry_id, reg[7]); - aos_unlock_bh(&dess_nat_lock); - return SW_OK; - } - else - { - if (FAL_NAT_ENTRY_PUBLIC_IP_EN & del_mode) - { - SW_SET_REG_BY_FIELD(HOST_ENTRY7, SPEC_PIP, 1, reg[7]); - SW_SET_REG_BY_FIELD(NAPT_ENTRY2, TRANS_IPADDR, entry->trans_addr, reg[2]); - } - - if (FAL_NAT_ENTRY_SOURCE_IP_EN & del_mode) - { - SW_SET_REG_BY_FIELD(HOST_ENTRY7, SPEC_SIP, 1, reg[7]); - rv = _dess_ip_prvaddr_sw_to_hw(dev_id, entry->src_addr, &data); - SW_RTN_ON_ERROR(rv); - SW_SET_REG_BY_FIELD(NAPT_ENTRY2, SRC_IPADDR0, (data & 0xfff), reg[2]); - SW_SET_REG_BY_FIELD(NAPT_ENTRY3, SRC_IPADDR1, (data >> 12), reg[3]); - } - - if (FAL_NAT_ENTRY_AGE_EN & del_mode) - { - SW_SET_REG_BY_FIELD(HOST_ENTRY7, SPEC_STATUS, 1, reg[7]); - SW_SET_REG_BY_FIELD(NAPT_ENTRY4, AGE_FLAG, entry->status, reg[4]); - } - - aos_lock_bh(&dess_nat_lock); - rv = _dess_nat_down_to_hw(dev_id, reg); - if (rv != SW_OK) { - aos_unlock_bh(&dess_nat_lock); - return rv; - } - rv = _dess_nat_entry_commit(dev_id, DESS_ENTRY_NAPT, DESS_NAT_ENTRY_FLUSH); - aos_unlock_bh(&dess_nat_lock); - return rv; - } -} - -static sw_error_t -_dess_napt_get(a_uint32_t dev_id, a_uint32_t get_mode, fal_napt_entry_t * entry) -{ - sw_error_t rv; - a_uint32_t found, age, reg[DESS_HOST_ENTRY_REG_NUM] = { 0 }; - - HSL_DEV_ID_CHECK(dev_id); - - rv = _dess_nat_feature_check(dev_id); - SW_RTN_ON_ERROR(rv); - -#if 0 - if (FAL_NAT_ENTRY_ID_EN != get_mode) - { - return SW_NOT_SUPPORTED; - } - - SW_SET_REG_BY_FIELD(HOST_ENTRY7, TBL_IDX, entry->entry_id, reg[7]); -#else - rv = _dess_napt_sw_to_hw(dev_id, entry, reg); - SW_RTN_ON_ERROR(rv); -#endif - - aos_lock_bh(&dess_nat_lock); - rv = _dess_nat_down_to_hw(dev_id, reg); - if (rv != SW_OK) { - aos_unlock_bh(&dess_nat_lock); - return rv; - } - - rv = _dess_nat_entry_commit(dev_id, DESS_ENTRY_NAPT, DESS_NAT_ENTRY_SEARCH); - if (rv != SW_OK) { - aos_unlock_bh(&dess_nat_lock); - return rv; - } - - rv = _dess_nat_up_to_sw(dev_id, reg); - if (rv != SW_OK) { - aos_unlock_bh(&dess_nat_lock); - return rv; - } - aos_unlock_bh(&dess_nat_lock); - - SW_GET_FIELD_BY_REG(HOST_ENTRY7, TBL_STAUS, found, reg[7]); - SW_GET_FIELD_BY_REG(NAPT_ENTRY4, AGE_FLAG, age, reg[4]); - if (found && age) - { - found = 1; - } - else - { - found = 0; - } - - rv = _dess_napt_hw_to_sw(dev_id, reg, entry); - SW_RTN_ON_ERROR(rv); - - if (!found) - { - return SW_NOT_FOUND; - } - - SW_GET_FIELD_BY_REG(HOST_ENTRY7, TBL_IDX, entry->entry_id, reg[7]); - return SW_OK; -} - -static sw_error_t -_dess_napt_next(a_uint32_t dev_id, a_uint32_t next_mode, - fal_napt_entry_t * napt_entry) -{ - a_uint32_t data, idx, reg[DESS_HOST_ENTRY_REG_NUM] = { 0 }; - sw_error_t rv; - - HSL_DEV_ID_CHECK(dev_id); - - rv = _dess_nat_feature_check(dev_id); - SW_RTN_ON_ERROR(rv); - - if (FAL_NEXT_ENTRY_FIRST_ID == napt_entry->entry_id) - { - idx = DESS_NAPT_ENTRY_NUM - 1; - } - else - { - if ((DESS_NAPT_ENTRY_NUM - 1) == napt_entry->entry_id) - { - return SW_NO_MORE; - } - else - { - idx = napt_entry->entry_id; - } - } - - if (FAL_NAT_ENTRY_PUBLIC_IP_EN & next_mode) - { - SW_SET_REG_BY_FIELD(HOST_ENTRY7, SPEC_PIP, 1, reg[7]); - SW_SET_REG_BY_FIELD(NAPT_ENTRY2, TRANS_IPADDR, napt_entry->trans_addr, reg[2]); - } - - if (FAL_NAT_ENTRY_SOURCE_IP_EN & next_mode) - { - SW_SET_REG_BY_FIELD(HOST_ENTRY7, SPEC_SIP, 1, reg[7]); - rv = _dess_ip_prvaddr_sw_to_hw(dev_id, napt_entry->src_addr, &data); - SW_RTN_ON_ERROR(rv); - SW_SET_REG_BY_FIELD(NAPT_ENTRY2, SRC_IPADDR0, (data & 0xfff), reg[2]); - SW_SET_REG_BY_FIELD(NAPT_ENTRY3, SRC_IPADDR1, (data >> 12), reg[3]); - } - - if (FAL_NAT_ENTRY_AGE_EN & next_mode) - { - SW_SET_REG_BY_FIELD(HOST_ENTRY7, SPEC_STATUS, 1, reg[7]); - SW_SET_REG_BY_FIELD(NAPT_ENTRY4, AGE_FLAG, napt_entry->status, reg[4]); - } - - if (FAL_NAT_ENTRY_SYNC_EN & next_mode) - { - SW_SET_REG_BY_FIELD(HOST_ENTRY7, SPEC_SYNC, 1, reg[7]); - SW_SET_REG_BY_FIELD(NAPT_ENTRY4, AGE_SYNC, napt_entry->aging_sync, reg[4]); - } - - SW_SET_REG_BY_FIELD(HOST_ENTRY7, TBL_IDX, idx, reg[7]); - - aos_lock_bh(&dess_nat_lock); - rv = _dess_nat_down_to_hw(dev_id, reg); - if (rv != SW_OK) { - aos_unlock_bh(&dess_nat_lock); - return rv; - } - - rv = _dess_nat_entry_commit(dev_id, DESS_ENTRY_NAPT, DESS_NAT_ENTRY_NEXT); - if (rv != SW_OK) { - aos_unlock_bh(&dess_nat_lock); - return rv; - } - - rv = _dess_nat_up_to_sw(dev_id, reg); - if (rv != SW_OK) { - aos_unlock_bh(&dess_nat_lock); - return rv; - } - aos_unlock_bh(&dess_nat_lock); - - aos_mem_zero(napt_entry, sizeof (fal_nat_entry_t)); - - rv = _dess_napt_hw_to_sw(dev_id, reg, napt_entry); - SW_RTN_ON_ERROR(rv); - -#if 0 - a_uint32_t temp=0, complete=0; - - HSL_REG_ENTRY_GET(rv, dev_id, HOST_ENTRY7, 0, (a_uint8_t *) (&temp), - sizeof (a_uint32_t)); - - SW_GET_FIELD_BY_REG(HOST_ENTRY7, TBL_STAUS, complete, temp); - - if (!complete) - { - return SW_NO_MORE; - } -#endif - - SW_GET_FIELD_BY_REG(HOST_ENTRY7, TBL_IDX, napt_entry->entry_id, reg[7]); - return SW_OK; -} - -static sw_error_t -_dess_napt_counter_bind(a_uint32_t dev_id, a_uint32_t entry_id, - a_uint32_t cnt_id, a_bool_t enable) -{ - sw_error_t rv; - a_uint32_t reg[DESS_HOST_ENTRY_REG_NUM] = { 0 }, tbl_idx; - - HSL_DEV_ID_CHECK(dev_id); - - rv = _dess_nat_feature_check(dev_id); - SW_RTN_ON_ERROR(rv); - - tbl_idx = (entry_id - 1) & 0x3ff; - SW_SET_REG_BY_FIELD(HOST_ENTRY7, TBL_IDX, tbl_idx, reg[7]); - - rv = _dess_nat_down_to_hw(dev_id, reg); - SW_RTN_ON_ERROR(rv); - - rv = _dess_nat_entry_commit(dev_id, DESS_ENTRY_NAPT, DESS_NAT_ENTRY_NEXT); - if (SW_OK != rv) - { - return SW_NOT_FOUND; - } - - rv = _dess_nat_up_to_sw(dev_id, reg); - SW_RTN_ON_ERROR(rv); - - SW_GET_FIELD_BY_REG(HOST_ENTRY7, TBL_IDX, tbl_idx, reg[7]); - if (entry_id != tbl_idx) - { - return SW_NOT_FOUND; - } - - if (A_FALSE == enable) - { - SW_SET_REG_BY_FIELD(NAPT_ENTRY3, CNT_EN, 0, reg[3]); - } - else if (A_TRUE == enable) - { - SW_SET_REG_BY_FIELD(NAPT_ENTRY3, CNT_EN, 1, reg[3]); - SW_SET_REG_BY_FIELD(NAPT_ENTRY3, CNT_IDX, cnt_id, reg[3]); - } - else - { - return SW_BAD_PARAM; - } - - rv = _dess_nat_entry_commit(dev_id, DESS_ENTRY_NAPT, DESS_NAT_ENTRY_DEL); - SW_RTN_ON_ERROR(rv); - - rv = _dess_nat_down_to_hw(dev_id, reg); - SW_RTN_ON_ERROR(rv); - - rv = _dess_nat_entry_commit(dev_id, DESS_ENTRY_NAPT, DESS_NAT_ENTRY_ADD); - return rv; -} - -static sw_error_t -_dess_flow_add(a_uint32_t dev_id, fal_napt_entry_t * entry) -{ - sw_error_t rv; - a_uint32_t reg[DESS_HOST_ENTRY_REG_NUM] = { 0 }; - - HSL_DEV_ID_CHECK(dev_id); - - rv = _dess_nat_feature_check(dev_id); - SW_RTN_ON_ERROR(rv); - - HSL_DEV_ID_CHECK(dev_id); - - rv = _dess_napt_sw_to_hw(dev_id, entry, reg); - SW_RTN_ON_ERROR(rv); - - aos_lock_bh(&dess_nat_lock); - rv = _dess_nat_down_to_hw(dev_id, reg); - if (rv != SW_OK) { - aos_unlock_bh(&dess_nat_lock); - return rv; - } - - rv = _dess_nat_entry_commit(dev_id, DESS_ENTRY_FLOW, DESS_NAT_ENTRY_ADD); - if (rv != SW_OK) { - aos_unlock_bh(&dess_nat_lock); - return rv; - } - - rv = _dess_nat_up_to_sw(dev_id, reg); - if (rv != SW_OK) { - aos_unlock_bh(&dess_nat_lock); - return rv; - } - - SW_GET_FIELD_BY_REG(HOST_ENTRY7, TBL_IDX, entry->entry_id, reg[7]); - aos_unlock_bh(&dess_nat_lock); - return SW_OK; -} - -static sw_error_t -_dess_flow_del(a_uint32_t dev_id, a_uint32_t del_mode, fal_napt_entry_t * entry) -{ - sw_error_t rv; - a_uint32_t data, reg[DESS_HOST_ENTRY_REG_NUM] = { 0 }; - - HSL_DEV_ID_CHECK(dev_id); - - rv = _dess_nat_feature_check(dev_id); - SW_RTN_ON_ERROR(rv); - - if (FAL_NAT_ENTRY_ID_EN & del_mode) - { - return SW_NOT_SUPPORTED; - } - - if (FAL_NAT_ENTRY_KEY_EN & del_mode) - { - rv = _dess_napt_sw_to_hw(dev_id, entry, reg); - SW_RTN_ON_ERROR(rv); - - aos_lock_bh(&dess_nat_lock); - rv = _dess_nat_down_to_hw(dev_id, reg); - if (rv != SW_OK) { - aos_unlock_bh(&dess_nat_lock); - return rv; - } - - rv = _dess_nat_entry_commit(dev_id, DESS_ENTRY_FLOW, DESS_NAT_ENTRY_DEL); - if (rv != SW_OK) { - aos_unlock_bh(&dess_nat_lock); - return rv; - } - - rv = _dess_nat_up_to_sw(dev_id, reg); - if (rv != SW_OK) { - aos_unlock_bh(&dess_nat_lock); - return rv; - } - - SW_GET_FIELD_BY_REG(HOST_ENTRY7, TBL_IDX, entry->entry_id, reg[7]); - aos_unlock_bh(&dess_nat_lock); - return SW_OK; - } - else - { - if (FAL_NAT_ENTRY_PUBLIC_IP_EN & del_mode) - { - SW_SET_REG_BY_FIELD(HOST_ENTRY7, SPEC_PIP, 1, reg[7]); - SW_SET_REG_BY_FIELD(NAPT_ENTRY2, TRANS_IPADDR, entry->trans_addr, reg[2]); - } - - if (FAL_NAT_ENTRY_SOURCE_IP_EN & del_mode) - { - SW_SET_REG_BY_FIELD(HOST_ENTRY7, SPEC_SIP, 1, reg[7]); - rv = _dess_ip_prvaddr_sw_to_hw(dev_id, entry->src_addr, &data); - SW_RTN_ON_ERROR(rv); - SW_SET_REG_BY_FIELD(NAPT_ENTRY2, SRC_IPADDR0, (data & 0xfff), reg[2]); - SW_SET_REG_BY_FIELD(NAPT_ENTRY3, SRC_IPADDR1, (data >> 12), reg[3]); - } - - if (FAL_NAT_ENTRY_AGE_EN & del_mode) - { - SW_SET_REG_BY_FIELD(HOST_ENTRY7, SPEC_STATUS, 1, reg[7]); - SW_SET_REG_BY_FIELD(NAPT_ENTRY4, AGE_FLAG, entry->status, reg[4]); - } - - aos_lock_bh(&dess_nat_lock); - rv = _dess_nat_down_to_hw(dev_id, reg); - if (rv != SW_OK) { - aos_unlock_bh(&dess_nat_lock); - return rv; - } - - rv = _dess_nat_entry_commit(dev_id, DESS_ENTRY_FLOW, DESS_NAT_ENTRY_FLUSH); - aos_unlock_bh(&dess_nat_lock); - return rv; - } -} - -static sw_error_t -_dess_flow_get(a_uint32_t dev_id, a_uint32_t get_mode, fal_napt_entry_t * entry) -{ - sw_error_t rv; - a_uint32_t found, age, reg[DESS_HOST_ENTRY_REG_NUM] = { 0 }; - - HSL_DEV_ID_CHECK(dev_id); - - rv = _dess_nat_feature_check(dev_id); - SW_RTN_ON_ERROR(rv); - -#if 0 - if (FAL_NAT_ENTRY_ID_EN != get_mode) - { - return SW_NOT_SUPPORTED; - } - - SW_SET_REG_BY_FIELD(HOST_ENTRY7, TBL_IDX, entry->entry_id, reg[7]); -#else - rv = _dess_napt_sw_to_hw(dev_id, entry, reg); - SW_RTN_ON_ERROR(rv); -#endif - - aos_lock_bh(&dess_nat_lock); - rv = _dess_nat_down_to_hw(dev_id, reg); - if (rv != SW_OK) { - aos_unlock_bh(&dess_nat_lock); - return rv; - } - - rv = _dess_nat_entry_commit(dev_id, DESS_ENTRY_FLOW, DESS_NAT_ENTRY_SEARCH); - if (rv != SW_OK) { - aos_unlock_bh(&dess_nat_lock); - return rv; - } - - rv = _dess_nat_up_to_sw(dev_id, reg); - if (rv != SW_OK) { - aos_unlock_bh(&dess_nat_lock); - return rv; - } - aos_unlock_bh(&dess_nat_lock); - - SW_GET_FIELD_BY_REG(HOST_ENTRY7, TBL_STAUS, found, reg[7]); - SW_GET_FIELD_BY_REG(NAPT_ENTRY4, AGE_FLAG, age, reg[4]); - if (found && age) - { - found = 1; - } - else - { - found = 0; - } - - rv = _dess_napt_hw_to_sw(dev_id, reg, entry); - SW_RTN_ON_ERROR(rv); - - if (!found) - { - return SW_NOT_FOUND; - } - - SW_GET_FIELD_BY_REG(HOST_ENTRY7, TBL_IDX, entry->entry_id, reg[7]); - return SW_OK; -} - -static sw_error_t -_dess_flow_next(a_uint32_t dev_id, a_uint32_t next_mode, - fal_napt_entry_t * napt_entry) -{ - a_uint32_t data, idx, reg[DESS_HOST_ENTRY_REG_NUM] = { 0 }; - sw_error_t rv; - - HSL_DEV_ID_CHECK(dev_id); - - rv = _dess_nat_feature_check(dev_id); - SW_RTN_ON_ERROR(rv); - - if (FAL_NEXT_ENTRY_FIRST_ID == napt_entry->entry_id) - { - idx = DESS_NAPT_ENTRY_NUM - 1; - } - else - { - if ((DESS_NAPT_ENTRY_NUM - 1) == napt_entry->entry_id) - { - return SW_NO_MORE; - } - else - { - idx = napt_entry->entry_id; - } - } - - if (FAL_NAT_ENTRY_PUBLIC_IP_EN & next_mode) - { - SW_SET_REG_BY_FIELD(HOST_ENTRY7, SPEC_PIP, 1, reg[7]); - SW_SET_REG_BY_FIELD(NAPT_ENTRY2, TRANS_IPADDR, napt_entry->trans_addr, reg[2]); - } - - if (FAL_NAT_ENTRY_SOURCE_IP_EN & next_mode) - { - SW_SET_REG_BY_FIELD(HOST_ENTRY7, SPEC_SIP, 1, reg[7]); - rv = _dess_ip_prvaddr_sw_to_hw(dev_id, napt_entry->src_addr, &data); - SW_RTN_ON_ERROR(rv); - SW_SET_REG_BY_FIELD(NAPT_ENTRY2, SRC_IPADDR0, (data & 0xfff), reg[2]); - SW_SET_REG_BY_FIELD(NAPT_ENTRY3, SRC_IPADDR1, (data >> 12), reg[3]); - } - - if (FAL_NAT_ENTRY_AGE_EN & next_mode) - { - SW_SET_REG_BY_FIELD(HOST_ENTRY7, SPEC_STATUS, 1, reg[7]); - SW_SET_REG_BY_FIELD(NAPT_ENTRY4, AGE_FLAG, napt_entry->status, reg[4]); - } - - if (FAL_NAT_ENTRY_SYNC_EN & next_mode) - { - SW_SET_REG_BY_FIELD(HOST_ENTRY7, SPEC_SYNC, 1, reg[7]); - SW_SET_REG_BY_FIELD(NAPT_ENTRY4, AGE_SYNC, napt_entry->status, reg[4]); - } - - SW_SET_REG_BY_FIELD(HOST_ENTRY7, TBL_IDX, idx, reg[7]); - - aos_lock_bh(&dess_nat_lock); - rv = _dess_nat_down_to_hw(dev_id, reg); - if (rv != SW_OK) { - aos_unlock_bh(&dess_nat_lock); - return rv; - } - - rv = _dess_nat_entry_commit(dev_id, DESS_ENTRY_FLOW, DESS_NAT_ENTRY_NEXT); - if (rv != SW_OK) { - aos_unlock_bh(&dess_nat_lock); - return rv; - } - - rv = _dess_nat_up_to_sw(dev_id, reg); - if (rv != SW_OK) { - aos_unlock_bh(&dess_nat_lock); - return rv; - } - aos_unlock_bh(&dess_nat_lock); - - aos_mem_zero(napt_entry, sizeof (fal_nat_entry_t)); - - rv = _dess_napt_hw_to_sw(dev_id, reg, napt_entry); - SW_RTN_ON_ERROR(rv); - -#if 0 - a_uint32_t temp=0, complete=0; - - HSL_REG_ENTRY_GET(rv, dev_id, HOST_ENTRY7, 0, (a_uint8_t *) (&temp), - sizeof (a_uint32_t)); - - SW_GET_FIELD_BY_REG(HOST_ENTRY7, TBL_STAUS, complete, temp); - - if (!complete) - { - return SW_NO_MORE; - } -#endif - - SW_GET_FIELD_BY_REG(HOST_ENTRY7, TBL_IDX, napt_entry->entry_id, reg[7]); - return SW_OK; -} - -static sw_error_t -_dess_flow_counter_bind(a_uint32_t dev_id, a_uint32_t entry_id, - a_uint32_t cnt_id, a_bool_t enable) -{ - sw_error_t rv; - a_uint32_t reg[DESS_HOST_ENTRY_REG_NUM] = { 0 }, tbl_idx; - - HSL_DEV_ID_CHECK(dev_id); - - rv = _dess_nat_feature_check(dev_id); - SW_RTN_ON_ERROR(rv); - - tbl_idx = (entry_id - 1) & 0x3ff; - SW_SET_REG_BY_FIELD(HOST_ENTRY7, TBL_IDX, tbl_idx, reg[7]); - - rv = _dess_nat_down_to_hw(dev_id, reg); - SW_RTN_ON_ERROR(rv); - - rv = _dess_nat_entry_commit(dev_id, DESS_ENTRY_FLOW, DESS_NAT_ENTRY_NEXT); - if (SW_OK != rv) - { - return SW_NOT_FOUND; - } - - rv = _dess_nat_up_to_sw(dev_id, reg); - SW_RTN_ON_ERROR(rv); - - SW_GET_FIELD_BY_REG(HOST_ENTRY7, TBL_IDX, tbl_idx, reg[7]); - if (entry_id != tbl_idx) - { - return SW_NOT_FOUND; - } - - if (A_FALSE == enable) - { - SW_SET_REG_BY_FIELD(NAPT_ENTRY3, CNT_EN, 0, reg[3]); - } - else if (A_TRUE == enable) - { - SW_SET_REG_BY_FIELD(NAPT_ENTRY3, CNT_EN, 1, reg[3]); - SW_SET_REG_BY_FIELD(NAPT_ENTRY3, CNT_IDX, cnt_id, reg[3]); - } - else - { - return SW_BAD_PARAM; - } - - rv = _dess_nat_entry_commit(dev_id, DESS_ENTRY_FLOW, DESS_NAT_ENTRY_DEL); - SW_RTN_ON_ERROR(rv); - - rv = _dess_nat_down_to_hw(dev_id, reg); - SW_RTN_ON_ERROR(rv); - - rv = _dess_nat_entry_commit(dev_id, DESS_ENTRY_FLOW, DESS_NAT_ENTRY_ADD); - return rv; -} - -static sw_error_t -_dess_nat_status_set(a_uint32_t dev_id, a_bool_t enable) -{ - sw_error_t rv; - a_uint32_t data; - - HSL_DEV_ID_CHECK(dev_id); - - rv = _dess_nat_feature_check(dev_id); - SW_RTN_ON_ERROR(rv); - - if (A_TRUE == enable) - { - data = 1; - } - else if (A_FALSE == enable) - { - data = 0; - } - else - { - return SW_BAD_PARAM; - } - - HSL_REG_FIELD_SET(rv, dev_id, NAT_CTRL, 0, NAT_EN, - (a_uint8_t *) (&data), sizeof (a_uint32_t)); - return rv; -} - -static sw_error_t -_dess_nat_status_get(a_uint32_t dev_id, a_bool_t * enable) -{ - sw_error_t rv; - a_uint32_t data = 0; - - HSL_DEV_ID_CHECK(dev_id); - - rv = _dess_nat_feature_check(dev_id); - SW_RTN_ON_ERROR(rv); - - HSL_REG_FIELD_GET(rv, dev_id, NAT_CTRL, 0, NAT_EN, - (a_uint8_t *) (&data), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - - if (data) - { - *enable = A_TRUE; - } - else - { - *enable = A_FALSE; - } - - return rv; -} - -static sw_error_t -_dess_napt_status_set(a_uint32_t dev_id, a_bool_t enable) -{ - sw_error_t rv; - a_uint32_t data; - - HSL_DEV_ID_CHECK(dev_id); - - rv = _dess_nat_feature_check(dev_id); - SW_RTN_ON_ERROR(rv); - - if (A_TRUE == enable) - { - data = 1; - } - else if (A_FALSE == enable) - { - data = 0; - } - else - { - return SW_BAD_PARAM; - } - - HSL_REG_FIELD_SET(rv, dev_id, NAT_CTRL, 0, NAPT_EN, - (a_uint8_t *) (&data), sizeof (a_uint32_t)); - return rv; -} - -static sw_error_t -_dess_napt_status_get(a_uint32_t dev_id, a_bool_t * enable) -{ - sw_error_t rv; - a_uint32_t data = 0; - - HSL_DEV_ID_CHECK(dev_id); - - rv = _dess_nat_feature_check(dev_id); - SW_RTN_ON_ERROR(rv); - - HSL_REG_FIELD_GET(rv, dev_id, NAT_CTRL, 0, NAPT_EN, - (a_uint8_t *) (&data), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - - if (data) - { - *enable = A_TRUE; - } - else - { - *enable = A_FALSE; - } - - return rv; -} - -static sw_error_t -_dess_napt_mode_set(a_uint32_t dev_id, fal_napt_mode_t mode) -{ - sw_error_t rv; - a_uint32_t data; - - HSL_DEV_ID_CHECK(dev_id); - - rv = _dess_nat_feature_check(dev_id); - SW_RTN_ON_ERROR(rv); - - if (FAL_NAPT_FULL_CONE == mode) - { - data = 0; - } - else if (FAL_NAPT_STRICT_CONE == mode) - { - data = 1; - } - else if ((FAL_NAPT_PORT_STRICT == mode) - || (FAL_NAPT_SYNMETRIC == mode)) - { - data = 2; - } - else - { - return SW_BAD_PARAM; - } - - HSL_REG_FIELD_SET(rv, dev_id, NAT_CTRL, 0, NAPT_MODE, - (a_uint8_t *) (&data), sizeof (a_uint32_t)); - return rv; -} - -static sw_error_t -_dess_napt_mode_get(a_uint32_t dev_id, fal_napt_mode_t * mode) -{ - sw_error_t rv; - a_uint32_t data = 0; - - HSL_DEV_ID_CHECK(dev_id); - - rv = _dess_nat_feature_check(dev_id); - SW_RTN_ON_ERROR(rv); - - HSL_REG_FIELD_GET(rv, dev_id, NAT_CTRL, 0, NAPT_MODE, - (a_uint8_t *) (&data), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - - if (0 == data) - { - *mode = FAL_NAPT_FULL_CONE; - } - else if (1 == data) - { - *mode = FAL_NAPT_STRICT_CONE; - } - else - { - *mode = FAL_NAPT_PORT_STRICT; - } - - return SW_OK; -} - -static sw_error_t -_dess_nat_hash_mode_set(a_uint32_t dev_id, a_uint32_t mode) -{ - sw_error_t rv; - a_uint32_t data; - - HSL_DEV_ID_CHECK(dev_id); - - rv = _dess_nat_feature_check(dev_id); - SW_RTN_ON_ERROR(rv); - - if ((FAL_NAT_HASH_KEY_PORT & mode) - && (FAL_NAT_HASH_KEY_IPADDR & mode)) - { - data = 2; - } - else if (FAL_NAT_HASH_KEY_PORT & mode) - { - data = 0; - } - else if (FAL_NAT_HASH_KEY_IPADDR & mode) - { - data = 1; - } - else - { - return SW_BAD_PARAM; - } - - HSL_REG_FIELD_SET(rv, dev_id, NAT_CTRL, 0, NAT_HASH_MODE, - (a_uint8_t *) (&data), sizeof (a_uint32_t)); - return rv; -} - -static sw_error_t -_dess_nat_hash_mode_get(a_uint32_t dev_id, a_uint32_t * mode) -{ - sw_error_t rv; - a_uint32_t data = 0; - - HSL_DEV_ID_CHECK(dev_id); - - rv = _dess_nat_feature_check(dev_id); - SW_RTN_ON_ERROR(rv); - - HSL_REG_FIELD_GET(rv, dev_id, NAT_CTRL, 0, NAT_HASH_MODE, - (a_uint8_t *) (&data), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - - *mode = 0; - if (0 == data) - { - *mode = FAL_NAT_HASH_KEY_PORT; - } - else if (1 == data) - { - *mode = FAL_NAT_HASH_KEY_IPADDR; - } - else if (2 == data) - { - *mode = FAL_NAT_HASH_KEY_PORT; - *mode |= FAL_NAT_HASH_KEY_IPADDR; - } - - return SW_OK; -} - -static sw_error_t -_dess_nat_prv_base_addr_set(a_uint32_t dev_id, fal_ip4_addr_t addr) -{ - sw_error_t rv; - a_uint32_t data; - - HSL_DEV_ID_CHECK(dev_id); - - rv = _dess_nat_feature_check(dev_id); - SW_RTN_ON_ERROR(rv); - - data = addr; - HSL_REG_FIELD_SET(rv, dev_id, PRVIP_ADDR, 0, IP4_BASEADDR, - (a_uint8_t *) (&data), sizeof (a_uint32_t)); - return rv; -} - -static sw_error_t -_dess_nat_prv_base_addr_get(a_uint32_t dev_id, fal_ip4_addr_t * addr) -{ - sw_error_t rv; - a_uint32_t data = 0; - - HSL_DEV_ID_CHECK(dev_id); - - rv = _dess_nat_feature_check(dev_id); - SW_RTN_ON_ERROR(rv); - - HSL_REG_FIELD_GET(rv, dev_id, PRVIP_ADDR, 0, IP4_BASEADDR, - (a_uint8_t *) (&data), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - *addr = data; - - return SW_OK; -} - -static sw_error_t -_dess_nat_prv_base_mask_set(a_uint32_t dev_id, fal_ip4_addr_t mask) -{ - sw_error_t rv; - a_uint32_t data; - - HSL_DEV_ID_CHECK(dev_id); - - rv = _dess_nat_feature_check(dev_id); - SW_RTN_ON_ERROR(rv); - - data = mask; - HSL_REG_FIELD_SET(rv, dev_id, PRVIP_MASK, 0, IP4_BASEMASK, - (a_uint8_t *) (&data), sizeof (a_uint32_t)); - return rv; -} - -static sw_error_t -_dess_nat_prv_base_mask_get(a_uint32_t dev_id, fal_ip4_addr_t * mask) -{ - sw_error_t rv; - a_uint32_t data = 0; - - HSL_DEV_ID_CHECK(dev_id); - - rv = _dess_nat_feature_check(dev_id); - SW_RTN_ON_ERROR(rv); - - HSL_REG_FIELD_GET(rv, dev_id, PRVIP_MASK, 0, IP4_BASEMASK, - (a_uint8_t *) (&data), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - - *mask = data; - return SW_OK; -} - -static sw_error_t -_dess_nat_pub_addr_commit(a_uint32_t dev_id, fal_nat_pub_addr_t * entry, - a_uint32_t op, a_uint32_t * empty) -{ - a_uint32_t index, addr, data, tbl[2] = { 0 }; - sw_error_t rv; - - *empty = DESS_PUB_ADDR_NUM; - for (index = 0; index < DESS_PUB_ADDR_NUM; index++) - { - addr = DESS_PUB_ADDR_TBL1_ADDR + (index << 4); - HSL_REG_ENTRY_GEN_GET(rv, dev_id, addr, sizeof (a_uint32_t), - (a_uint8_t *) (&(tbl[1])), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - - SW_GET_FIELD_BY_REG(PUB_ADDR1, ADDR_VALID, data, tbl[1]); - if (data) - { - addr = DESS_PUB_ADDR_TBL0_ADDR + (index << 4); - HSL_REG_ENTRY_GEN_GET(rv, dev_id, addr, sizeof (a_uint32_t), - (a_uint8_t *) (&(tbl[0])), - sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - - if (!aos_mem_cmp - ((void *) &(entry->pub_addr), (void *) &(tbl[0]), - sizeof (fal_ip4_addr_t))) - { - if (DESS_NAT_ENTRY_DEL == op) - { - addr = DESS_PUB_ADDR_TBL1_ADDR + (index << 4); - tbl[1] = 0; - HSL_REG_ENTRY_GEN_SET(rv, dev_id, addr, sizeof (a_uint32_t), - (a_uint8_t *) (&(tbl[1])), - sizeof (a_uint32_t)); - *empty = index; - return rv; - } - else if (DESS_NAT_ENTRY_ADD == op) - { - entry->entry_id = index; - return SW_ALREADY_EXIST; - } - } - } - else - { - *empty = index; - } - } - - return SW_NOT_FOUND; -} - -static sw_error_t -_dess_nat_pub_addr_add(a_uint32_t dev_id, fal_nat_pub_addr_t * entry) -{ - sw_error_t rv; - a_uint32_t i, empty, addr, data = 0, tbl[2] = { 0 }; - - HSL_DEV_ID_CHECK(dev_id); - - rv = _dess_nat_feature_check(dev_id); - SW_RTN_ON_ERROR(rv); - - tbl[0] = entry->pub_addr; - tbl[1] = 1; - - rv = _dess_nat_pub_addr_commit(dev_id, entry, DESS_NAT_ENTRY_ADD, &empty); - if (SW_ALREADY_EXIST == rv) - { - return rv; - } - - if (DESS_PUB_ADDR_NUM == empty) - { - return SW_NO_RESOURCE; - } - - for (i = 0; i < 1; i++) - { - addr = DESS_PUB_ADDR_EDIT0_ADDR + (empty << 4) + (i << 2); - HSL_REG_ENTRY_GEN_SET(rv, dev_id, addr, sizeof (a_uint32_t), - (a_uint8_t *) (&(tbl[i])), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - } - - addr = DESS_PUB_ADDR_OFFLOAD_ADDR + (empty << 2); - HSL_REG_ENTRY_GEN_SET(rv, dev_id, addr, sizeof (a_uint32_t), - (a_uint8_t *) (&(tbl[0])), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - - addr = DESS_PUB_ADDR_VALID_ADDR; - HSL_REG_ENTRY_GEN_GET(rv, dev_id, addr, sizeof (a_uint32_t), - (a_uint8_t *) (&data), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - - data |= (0x1 << empty); - HSL_REG_ENTRY_GEN_SET(rv, dev_id, addr, sizeof (a_uint32_t), - (a_uint8_t *) (&data), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - - for (i = 0; i < 2; i++) - { - addr = DESS_PUB_ADDR_TBL0_ADDR + (empty << 4) + (i << 2); - HSL_REG_ENTRY_GEN_SET(rv, dev_id, addr, sizeof (a_uint32_t), - (a_uint8_t *) (&(tbl[i])), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - } - - entry->entry_id = empty; - return SW_OK; -} - -static sw_error_t -_dess_nat_pub_addr_del(a_uint32_t dev_id, a_uint32_t del_mode, - fal_nat_pub_addr_t * entry) -{ - sw_error_t rv; - a_uint32_t empty, addr, data = 0; - - HSL_DEV_ID_CHECK(dev_id); - - rv = _dess_nat_feature_check(dev_id); - SW_RTN_ON_ERROR(rv); - - rv = _dess_nat_pub_addr_commit(dev_id, entry, DESS_NAT_ENTRY_DEL, &empty); - SW_RTN_ON_ERROR(rv); - - addr = DESS_PUB_ADDR_VALID_ADDR; - HSL_REG_ENTRY_GEN_GET(rv, dev_id, addr, sizeof (a_uint32_t), - (a_uint8_t *) (&data), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - - data &= (~(0x1 << empty)); - HSL_REG_ENTRY_GEN_SET(rv, dev_id, addr, sizeof (a_uint32_t), - (a_uint8_t *) (&data), sizeof (a_uint32_t)); - - return rv; -} - -static sw_error_t -_dess_nat_pub_addr_next(a_uint32_t dev_id, a_uint32_t next_mode, - fal_nat_pub_addr_t * entry) -{ - sw_error_t rv; - a_uint32_t data, addr, idx, index, tbl[2] = {0}; - - HSL_DEV_ID_CHECK(dev_id); - - rv = _dess_nat_feature_check(dev_id); - SW_RTN_ON_ERROR(rv); - - if (FAL_NEXT_ENTRY_FIRST_ID == entry->entry_id) - { - idx = 0; - } - else - { - if ((DESS_PUB_ADDR_NUM - 1) == entry->entry_id) - { - return SW_NO_MORE; - } - else - { - idx = entry->entry_id + 1; - } - } - - for (index = idx; index < DESS_PUB_ADDR_NUM; index++) - { - addr = DESS_PUB_ADDR_TBL1_ADDR + (index << 4); - HSL_REG_ENTRY_GEN_GET(rv, dev_id, addr, sizeof (a_uint32_t), - (a_uint8_t *) (&(tbl[1])), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - - SW_GET_FIELD_BY_REG(PUB_ADDR1, ADDR_VALID, data, tbl[1]); - if (data) - { - break; - } - } - - if (DESS_PUB_ADDR_NUM == index) - { - return SW_NO_MORE; - } - - addr = DESS_PUB_ADDR_TBL0_ADDR + (index << 4); - HSL_REG_ENTRY_GEN_GET(rv, dev_id, addr, sizeof (a_uint32_t), - (a_uint8_t *) (&(tbl[0])), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - - entry->entry_id = index; - entry->pub_addr = tbl[0]; - - return SW_OK; -} - -static sw_error_t -_dess_nat_unk_session_cmd_set(a_uint32_t dev_id, fal_fwd_cmd_t cmd) -{ - sw_error_t rv; - a_uint32_t data; - - HSL_DEV_ID_CHECK(dev_id); - - rv = _dess_nat_feature_check(dev_id); - SW_RTN_ON_ERROR(rv); - - if (FAL_MAC_DROP == cmd) - { - data = 1; - } - else if (FAL_MAC_RDT_TO_CPU == cmd) - { - data = 0; - } - else - { - return SW_NOT_SUPPORTED; - } - - HSL_REG_FIELD_SET(rv, dev_id, FORWARD_CTL0, 0, NAT_NOT_FOUND_DROP, - (a_uint8_t *) (&data), sizeof (a_uint32_t)); - return rv; -} - -static sw_error_t -_dess_nat_unk_session_cmd_get(a_uint32_t dev_id, fal_fwd_cmd_t * cmd) -{ - sw_error_t rv; - a_uint32_t data = 0; - - HSL_DEV_ID_CHECK(dev_id); - - rv = _dess_nat_feature_check(dev_id); - SW_RTN_ON_ERROR(rv); - - HSL_REG_FIELD_GET(rv, dev_id, FORWARD_CTL0, 0, NAT_NOT_FOUND_DROP, - (a_uint8_t *) (&data), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - - if (0 == data) - { - *cmd = FAL_MAC_RDT_TO_CPU; - } - else - { - *cmd = FAL_MAC_DROP; - } - - return SW_OK; -} - -#define DESS_NAT_VRF_ENTRY_TBL_ADDR 0x0484 -#define DESS_NAT_VRF_ENTRY_MASK_ADDR 0x0488 - -a_uint8_t _dess_snat_matched(a_uint32_t dev_id, fal_ip4_addr_t addr) -{ - a_bool_t nat_enable = 0, napt_enable = 0; - fal_ip4_addr_t mask = 0, base = 0; - a_uint32_t reg_addr; - sw_error_t rv; - - _dess_nat_status_get(dev_id, &nat_enable); - _dess_napt_status_get(dev_id, &napt_enable); - if(!(nat_enable & napt_enable)) - return 0; - - /*check for private base ip*/ - reg_addr = DESS_NAT_VRF_ENTRY_MASK_ADDR; - HSL_REG_ENTRY_GEN_GET(rv, dev_id, reg_addr, sizeof (a_uint32_t), - (a_uint8_t *) (&mask), sizeof (a_uint32_t)); - - reg_addr = DESS_NAT_VRF_ENTRY_TBL_ADDR; - HSL_REG_ENTRY_GEN_GET(rv, dev_id, reg_addr, sizeof (a_uint32_t), - (a_uint8_t *) (&base), sizeof (a_uint32_t)); - if (rv) - return 0; - if((mask&addr) == (mask&base)) { - return 1; - } - - return 0; -} - -a_uint8_t _dess_dnat_matched( - a_uint32_t dev_id, - fal_ip4_addr_t addr, - a_uint8_t *index) -{ - a_bool_t nat_enable = 0, napt_enable = 0; - fal_nat_pub_addr_t entry; - sw_error_t ret; - - _dess_nat_status_get(dev_id, &nat_enable); - _dess_napt_status_get(dev_id, &napt_enable); - if(!(nat_enable & napt_enable)) - return 0; - - /*check for public ip*/ - memset(&entry, 0, sizeof(entry)); - entry.entry_id = FAL_NEXT_ENTRY_FIRST_ID; - while(1) { - ret = _dess_nat_pub_addr_next(dev_id, 0, &entry); - if(ret) { - break; - } - if(entry.pub_addr == addr) { - *index = entry.entry_id; - return 1; - } - } - return 0; -} - - - -static sw_error_t -_dess_flow_cookie_snat_set(a_uint32_t dev_id, fal_flow_cookie_t * flow_cookie) -{ - fal_napt_entry_t entry; - sw_error_t ret; - - memset(&entry, 0, sizeof(entry)); - entry.flags = FAL_NAT_ENTRY_TRANS_IPADDR_INDEX | flow_cookie->proto; - entry.status = 0xf; - entry.src_addr = flow_cookie->src_addr; - entry.dst_addr = flow_cookie->dst_addr; - entry.src_port = flow_cookie->src_port; - entry.dst_port = flow_cookie->dst_port; - entry.trans_port = flow_cookie->src_port; - entry.action = FAL_MAC_RDT_TO_CPU; - ret = _dess_napt_get(dev_id, 0, &entry); - if(ret) { - if(flow_cookie->flow_cookie == 0) - return SW_OK; - } - if(flow_cookie->flow_cookie == 0) { - if(entry.flow_cookie == 0) { - ret = _dess_napt_del(dev_id, FAL_NAT_ENTRY_KEY_EN, &entry); - #if defined(IN_NAT_HELPER) - #if 0 - napt_cookie[entry.entry_id*2+1] = 0; - #endif - if (dess_nat_global_status) - nat_helper_cookie_del(entry.entry_id); - #endif - return ret; - } - ret = _dess_napt_del(dev_id, FAL_NAT_ENTRY_KEY_EN, &entry); - } else { - entry.flow_cookie = flow_cookie->flow_cookie; - ret = _dess_napt_add(dev_id, &entry); - } - - return ret; -} - -static sw_error_t -_dess_flow_cookie_dnat_set( - a_uint32_t dev_id, - fal_flow_cookie_t * flow_cookie, - a_uint8_t index) -{ - fal_napt_entry_t entry; - sw_error_t ret = 0; - - memset(&entry, 0, sizeof(entry)); - entry.flags = FAL_NAT_ENTRY_TRANS_IPADDR_INDEX | flow_cookie->proto; - entry.status = 0xf; - entry.trans_addr = index; - entry.trans_port = flow_cookie->dst_port; - entry.dst_addr = flow_cookie->src_addr; - entry.dst_port = flow_cookie->src_port; - entry.src_port = flow_cookie->dst_port; - entry.action = FAL_MAC_RDT_TO_CPU; - ret = _dess_napt_get(dev_id, 0, &entry); - if(ret) { - if(flow_cookie->flow_cookie == 0) { - return SW_OK; - } else { - /*add a fresh flowcookie*/ - entry.flow_cookie = flow_cookie->flow_cookie; - ret = _dess_napt_add(dev_id, &entry); - return ret; - } - } - if(flow_cookie->flow_cookie == 0) { - /*del flow cookie*/ - if(entry.flow_cookie == 0) { - ret = _dess_napt_del(dev_id, FAL_NAT_ENTRY_KEY_EN, &entry); - #if defined(IN_NAT_HELPER) - #if 0 - napt_cookie[entry.entry_id*2] = 0; - #endif - if (dess_nat_global_status) - nat_helper_cookie_del(entry.entry_id); - #endif - return ret; - } - ret = _dess_napt_del(dev_id, FAL_NAT_ENTRY_KEY_EN, &entry); - if(entry.load_balance & 4) { - /*keep rfs*/ - entry.flow_cookie = 0; - ret = _dess_napt_add(dev_id, &entry); - return ret; - } - } else { - /*add flow cookie*/ - ret = _dess_napt_del(dev_id, FAL_NAT_ENTRY_KEY_EN, &entry); - entry.flow_cookie = flow_cookie->flow_cookie; - ret = _dess_napt_add(dev_id, &entry); - return ret; - } - return ret; - -} - -static sw_error_t -_dess_flow_rfs_dnat_set( - a_uint32_t dev_id, - a_uint8_t action, - fal_flow_rfs_t * rfs, - a_uint8_t index) -{ - fal_napt_entry_t entry; - sw_error_t ret = 0; - - memset(&entry, 0, sizeof(entry)); - entry.flags = FAL_NAT_ENTRY_TRANS_IPADDR_INDEX | rfs->proto; - entry.status = 0xf; - entry.trans_addr = index; - entry.trans_port = rfs->dst_port; - entry.dst_addr = rfs->src_addr; - entry.dst_port = rfs->src_port; - entry.src_port = rfs->dst_port; - entry.action = FAL_MAC_RDT_TO_CPU; - ret = _dess_napt_get(dev_id, 0, &entry); - if(ret) { - if(action == 0) { - return SW_FAIL; - } else { - /*add a fresh rfs*/ - entry.load_balance = rfs->load_balance | 4; - ret = _dess_napt_add(dev_id, &entry); - return ret; - } - } - if(action == 0) { - /*del flow rfs*/ - ret = _dess_napt_del(dev_id, FAL_NAT_ENTRY_KEY_EN, &entry); - if(entry.flow_cookie != 0) { - /*keep cookie*/ - entry.load_balance = 0; - ret = _dess_napt_add(dev_id, &entry); - return ret; - } - } else { - /*add flow rfs*/ - ret = _dess_napt_del(dev_id, FAL_NAT_ENTRY_KEY_EN, &entry); - entry.load_balance = rfs->load_balance | 4; - ret = _dess_napt_add(dev_id, &entry); - return ret; - } - return ret; - -} - - -static sw_error_t -_dess_flow_cookie_set(a_uint32_t dev_id, fal_flow_cookie_t * flow_cookie) -{ - fal_napt_entry_t entry; - sw_error_t ret; - a_uint8_t index; - - if(_dess_dnat_matched(dev_id, flow_cookie->dst_addr, &index)) - return _dess_flow_cookie_dnat_set(dev_id, flow_cookie, index); - if(_dess_snat_matched(dev_id, flow_cookie->src_addr)) - return _dess_flow_cookie_snat_set(dev_id, flow_cookie); - - /*normal flow*/ - memset(&entry, 0, sizeof(entry)); - entry.flags = flow_cookie->proto; - entry.src_addr = flow_cookie->src_addr; - entry.dst_addr = flow_cookie->dst_addr; - entry.src_port = flow_cookie->src_port; - entry.dst_port = flow_cookie->dst_port; - ret = _dess_flow_get(0, 0, &entry); - if(SW_OK != ret && flow_cookie->flow_cookie == 0) - return ret; - if(flow_cookie->flow_cookie == 0) { - /*del*/ - _dess_flow_del(0, FAL_NAT_ENTRY_KEY_EN, &entry); - if(entry.load_balance & 4) { - entry.status = 0xf; - entry.flow_cookie = 0; - return _dess_flow_add(0, &entry); - } - } else { - /*add*/ - if(ret == SW_OK) - _dess_flow_del(0, FAL_NAT_ENTRY_KEY_EN, &entry); - entry.status = 0xf; - entry.flow_cookie = flow_cookie->flow_cookie; - return _dess_flow_add(0, &entry); - } - return SW_OK; -} - -static sw_error_t -_dess_flow_rfs_set(a_uint32_t dev_id, a_uint8_t action, fal_flow_rfs_t * rfs) -{ - fal_napt_entry_t entry; - sw_error_t ret; - a_uint8_t index; - - if(_dess_dnat_matched(dev_id, rfs->dst_addr, &index)) - return _dess_flow_rfs_dnat_set(dev_id, action, rfs, index); - - memset(&entry, 0, sizeof(entry)); - entry.flags = rfs->proto; - entry.src_addr = rfs->src_addr; - entry.dst_addr = rfs->dst_addr; - entry.src_port = rfs->src_port; - entry.dst_port = rfs->dst_port; - ret = _dess_flow_get(0, 0, &entry); - if(SW_OK != ret && action == 0) - return ret; - if(action == 0) { - /*del*/ - _dess_flow_del(0, FAL_NAT_ENTRY_KEY_EN, &entry); - if(entry.flow_cookie != 0) { - entry.load_balance = 0; - return _dess_flow_add(0, &entry); - } - } else { - /*add*/ - if(ret == SW_OK) - _dess_flow_del(0, FAL_NAT_ENTRY_KEY_EN, &entry); - entry.status = 0xf; - entry.load_balance = rfs->load_balance | 0x4; - return _dess_flow_add(0, &entry); - } - return SW_OK; -} - - - -sw_error_t -dess_nat_reset(a_uint32_t dev_id) -{ - sw_error_t rv; - a_uint32_t index, addr, data = 0; - - HSL_DEV_ID_CHECK(dev_id); - - rv = _dess_nat_feature_check(dev_id); - SW_RTN_ON_ERROR(rv); - - dess_nat_snap[dev_id] = 0; - - HSL_REG_ENTRY_SET(rv, dev_id, HOST_ENTRY7, 0, (a_uint8_t *) (&data), - sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - - rv = _dess_nat_entry_commit(dev_id, DESS_ENTRY_NAT, DESS_NAT_ENTRY_FLUSH); - SW_RTN_ON_ERROR(rv); - - HSL_REG_ENTRY_SET(rv, dev_id, HOST_ENTRY7, 0, (a_uint8_t *) (&data), - sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - - rv = _dess_nat_entry_commit(dev_id, DESS_ENTRY_NAPT, DESS_NAT_ENTRY_FLUSH); - SW_RTN_ON_ERROR(rv); - - rv = _dess_nat_entry_commit(dev_id, DESS_ENTRY_FLOW, DESS_NAT_ENTRY_FLUSH); - SW_RTN_ON_ERROR(rv); - - for (index = 0; index < DESS_PUB_ADDR_NUM; index++) - { - addr = DESS_PUB_ADDR_TBL1_ADDR + (index << 4); - HSL_REG_ENTRY_GEN_SET(rv, dev_id, addr, sizeof (a_uint32_t), - (a_uint8_t *) (&data), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - } - - return SW_OK; -} - -/** - * @brief Add one NAT entry to one particular device. - * @details Comments: - Before NAT entry added ip4 private base address must be set - at first. - In parameter nat_entry entry flags must be set - Hardware entry id will be returned. - * @param[in] dev_id device id - * @param[in] nat_entry NAT entry parameter - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -dess_nat_add(a_uint32_t dev_id, fal_nat_entry_t * nat_entry) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _dess_nat_add(dev_id, nat_entry); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Del NAT entries from one particular device. - * @param[in] dev_id device id - * @param[in] del_mode NAT entry delete operation mode - * @param[in] nat_entry NAT entry parameter - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -dess_nat_del(a_uint32_t dev_id, a_uint32_t del_mode, - fal_nat_entry_t * nat_entry) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _dess_nat_del(dev_id, del_mode, nat_entry); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Get one NAT entry from one particular device. - * @param[in] dev_id device id - * @param[in] get_mode NAT entry get operation mode - * @param[in] nat_entry NAT entry parameter - * @param[out] nat_entry NAT entry parameter - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -dess_nat_get(a_uint32_t dev_id, a_uint32_t get_mode, - fal_nat_entry_t * nat_entry) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _dess_nat_get(dev_id, get_mode, nat_entry); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Next NAT entries from one particular device. - * @param[in] dev_id device id - * @param[in] next_mode NAT entry next operation mode - * @param[in] nat_entry NAT entry parameter - * @param[out] nat_entry NAT entry parameter - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -dess_nat_next(a_uint32_t dev_id, a_uint32_t next_mode, - fal_nat_entry_t * nat_entry) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _dess_nat_next(dev_id, next_mode, nat_entry); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Bind one counter entry to one NAT entry to one particular device. - * @param[in] dev_id device id - * @param[in] entry_id NAT entry id - * @param[in] cnt_id counter entry id - * @param[in] enable A_TRUE or A_FALSE - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -dess_nat_counter_bind(a_uint32_t dev_id, a_uint32_t entry_id, a_uint32_t cnt_id, - a_bool_t enable) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _dess_nat_counter_bind(dev_id, entry_id, cnt_id, enable); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Add one NAPT entry to one particular device. - * @details Comments: - Before NAPT entry added related ip4 private base address must be set - at first. - In parameter napt_entry related entry flags must be set - Hardware entry id will be returned. - * @param[in] dev_id device id - * @param[in] napt_entry NAPT entry parameter - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -dess_napt_add(a_uint32_t dev_id, fal_napt_entry_t * napt_entry) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _dess_napt_add(dev_id, napt_entry); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Del NAPT entries from one particular device. - * @param[in] dev_id device id - * @param[in] del_mode NAPT entry delete operation mode - * @param[in] napt_entry NAPT entry parameter - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -dess_napt_del(a_uint32_t dev_id, a_uint32_t del_mode, - fal_napt_entry_t * napt_entry) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _dess_napt_del(dev_id, del_mode, napt_entry); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Get one NAPT entry from one particular device. - * @param[in] dev_id device id - * @param[in] get_mode NAPT entry get operation mode - * @param[in] nat_entry NAPT entry parameter - * @param[out] nat_entry NAPT entry parameter - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -dess_napt_get(a_uint32_t dev_id, a_uint32_t get_mode, - fal_napt_entry_t * napt_entry) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _dess_napt_get(dev_id, get_mode, napt_entry); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Next NAPT entries from one particular device. - * @param[in] dev_id device id - * @param[in] next_mode NAPT entry next operation mode - * @param[in] napt_entry NAPT entry parameter - * @param[out] napt_entry NAPT entry parameter - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -dess_napt_next(a_uint32_t dev_id, a_uint32_t next_mode, - fal_napt_entry_t * napt_entry) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _dess_napt_next(dev_id, next_mode, napt_entry); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Bind one counter entry to one NAPT entry to one particular device. - * @param[in] dev_id device id - * @param[in] entry_id NAPT entry id - * @param[in] cnt_id counter entry id - * @param[in] enable A_TRUE or A_FALSE - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -dess_napt_counter_bind(a_uint32_t dev_id, a_uint32_t entry_id, - a_uint32_t cnt_id, a_bool_t enable) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _dess_napt_counter_bind(dev_id, entry_id, cnt_id, enable); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Add one FLOW entry to one particular device. - * @details Comments: - Before FLOW entry added related ip4 private base address must be set - at first. - In parameter napt_entry related entry flags must be set - Hardware entry id will be returned. - * @param[in] dev_id device id - * @param[in] napt_entry FLOW entry parameter - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -dess_flow_add(a_uint32_t dev_id, fal_napt_entry_t * napt_entry) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _dess_flow_add(dev_id, napt_entry); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Del FLOW entries from one particular device. - * @param[in] dev_id device id - * @param[in] del_mode FLOW entry delete operation mode - * @param[in] napt_entry FLOW entry parameter - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -dess_flow_del(a_uint32_t dev_id, a_uint32_t del_mode, - fal_napt_entry_t * napt_entry) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _dess_flow_del(dev_id, del_mode, napt_entry); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Get one FLOW entry from one particular device. - * @param[in] dev_id device id - * @param[in] get_mode FLOW entry get operation mode - * @param[in] nat_entry FLOW entry parameter - * @param[out] nat_entry FLOW entry parameter - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -dess_flow_get(a_uint32_t dev_id, a_uint32_t get_mode, - fal_napt_entry_t * napt_entry) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _dess_flow_get(dev_id, get_mode, napt_entry); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Next FLOW entries from one particular device. - * @param[in] dev_id device id - * @param[in] next_mode FLOW entry next operation mode - * @param[in] napt_entry FLOW entry parameter - * @param[out] napt_entry FLOW entry parameter - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -dess_flow_next(a_uint32_t dev_id, a_uint32_t next_mode, - fal_napt_entry_t * napt_entry) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _dess_flow_next(dev_id, next_mode, napt_entry); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Bind one counter entry to one FLOW entry to one particular device. - * @param[in] dev_id device id - * @param[in] entry_id FLOW entry id - * @param[in] cnt_id counter entry id - * @param[in] enable A_TRUE or A_FALSE - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -dess_flow_counter_bind(a_uint32_t dev_id, a_uint32_t entry_id, - a_uint32_t cnt_id, a_bool_t enable) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _dess_flow_counter_bind(dev_id, entry_id, cnt_id, enable); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Set working status of NAT engine on a particular device - * @param[in] dev_id device id - * @param[in] enable A_TRUE or A_FALSE - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -dess_nat_status_set(a_uint32_t dev_id, a_bool_t enable) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _dess_nat_status_set(dev_id, enable); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Get working status of NAT engine on a particular device - * @param[in] dev_id device id - * @param[out] enable A_TRUE or A_FALSE - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -dess_nat_status_get(a_uint32_t dev_id, a_bool_t * enable) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _dess_nat_status_get(dev_id, enable); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Set NAT hash mode on a particular device - * @param[in] dev_id device id - * @param[in] mode NAT hash mode - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -dess_nat_hash_mode_set(a_uint32_t dev_id, a_uint32_t mode) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _dess_nat_hash_mode_set(dev_id, mode); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Get NAT hash mode on a particular device - * @param[in] dev_id device id - * @param[out] mode NAT hash mode - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -dess_nat_hash_mode_get(a_uint32_t dev_id, a_uint32_t * mode) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _dess_nat_hash_mode_get(dev_id, mode); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Set working status of NAPT engine on a particular device - * @param[in] dev_id device id - * @param[in] enable A_TRUE or A_FALSE - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -dess_napt_status_set(a_uint32_t dev_id, a_bool_t enable) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _dess_napt_status_set(dev_id, enable); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Get working status of NAPT engine on a particular device - * @param[in] dev_id device id - * @param[out] enable A_TRUE or A_FALSE - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -dess_napt_status_get(a_uint32_t dev_id, a_bool_t * enable) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _dess_napt_status_get(dev_id, enable); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Set working mode of NAPT engine on a particular device - * @param[in] dev_id device id - * @param[in] mode NAPT mode - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -dess_napt_mode_set(a_uint32_t dev_id, fal_napt_mode_t mode) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _dess_napt_mode_set(dev_id, mode); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Get working mode of NAPT engine on a particular device - * @param[in] dev_id device id - * @param[out] mode NAPT mode - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -dess_napt_mode_get(a_uint32_t dev_id, fal_napt_mode_t * mode) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _dess_napt_mode_get(dev_id, mode); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Set IP4 private base address on a particular device - * @details Comments: - Only 20bits is meaning which 20bits is determined by private address mode. - * @param[in] dev_id device id - * @param[in] addr private base address - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -dess_nat_prv_base_addr_set(a_uint32_t dev_id, fal_ip4_addr_t addr) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _dess_nat_prv_base_addr_set(dev_id, addr); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Get IP4 private base address on a particular device - * @param[in] dev_id device id - * @param[out] addr private base address - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -dess_nat_prv_base_addr_get(a_uint32_t dev_id, fal_ip4_addr_t * addr) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _dess_nat_prv_base_addr_get(dev_id, addr); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Set IP4 private base address on a particular device - * @param[in] dev_id device id - * @param[in] mask private base mask - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -dess_nat_prv_base_mask_set(a_uint32_t dev_id, fal_ip4_addr_t mask) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _dess_nat_prv_base_mask_set(dev_id, mask); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Get IP4 private base address on a particular device - * @param[in] dev_id device id - * @param[out] mask private base mask - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -dess_nat_prv_base_mask_get(a_uint32_t dev_id, fal_ip4_addr_t * mask) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _dess_nat_prv_base_mask_get(dev_id, mask); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Add one public address entry to one particular device. - * @details Comments: - Hardware entry id will be returned. - * @param[in] dev_id device id - * @param[in] entry public address entry parameter - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -dess_nat_pub_addr_add(a_uint32_t dev_id, fal_nat_pub_addr_t * entry) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _dess_nat_pub_addr_add(dev_id, entry); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Delete one public address entry from one particular device. - * @param[in] dev_id device id - * @param[in] del_mode delete operaton mode - * @param[in] entry public address entry parameter - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -dess_nat_pub_addr_del(a_uint32_t dev_id, a_uint32_t del_mode, - fal_nat_pub_addr_t * entry) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _dess_nat_pub_addr_del(dev_id, del_mode, entry); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Next public address entries from one particular device. - * @param[in] dev_id device id - * @param[in] next_mode next operaton mode - * @param[out] entry public address entry parameter - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -dess_nat_pub_addr_next(a_uint32_t dev_id, a_uint32_t next_mode, - fal_nat_pub_addr_t * entry) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _dess_nat_pub_addr_next(dev_id, next_mode, entry); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Set forwarding command for those packets miss NAT entries on a particular device. - * @param[in] dev_id device id - * @param[in] cmd forwarding command - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -dess_nat_unk_session_cmd_set(a_uint32_t dev_id, fal_fwd_cmd_t cmd) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _dess_nat_unk_session_cmd_set(dev_id, cmd); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Get forwarding command for those packets miss NAT entries on a particular device. - * @param[in] dev_id device id - * @param[out] cmd forwarding command - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -dess_nat_unk_session_cmd_get(a_uint32_t dev_id, fal_fwd_cmd_t * cmd) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _dess_nat_unk_session_cmd_get(dev_id, cmd); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Set working status of NAT engine on a particular device - * @param[in] dev_id device id - * @param[in] enable A_TRUE or A_FALSE - * @param[in] portbmp port bitmap - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -dess_nat_global_set(a_uint32_t dev_id, a_bool_t enable, a_uint32_t portbmp) -{ - sw_error_t rv = SW_OK; - - HSL_API_LOCK; - printk("enable:%d\n", enable); - if(enable) { - if(dess_nat_global_status == 0) { - dess_nat_global_status = 1; -#if defined(IN_NAT_HELPER) - DESS_NAT_HELPER_INIT(rv, dev_id, portbmp); -#endif - } - } else { - if(dess_nat_global_status == 1) { - dess_nat_global_status = 0; -#if defined(IN_NAT_HELPER) - DESS_NAT_HELPER_CLEANUP(rv, dev_id); -#endif - } - } - //rv = SW_OK; - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Add/del one FLOW cookie entry to one particular device. - * @details Comments: - Before FLOW entry added related ip4 private base address must be set - at first. - In parameter napt_entry related entry flags must be set - Hardware entry id will be returned. - * @param[in] dev_id device id - * @param[in] FLOW cookie entry parameter - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -dess_flow_cookie_set(a_uint32_t dev_id, fal_flow_cookie_t * flow_cookie) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _dess_flow_cookie_set(dev_id, flow_cookie); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Add/del one FLOW rfs entry to one particular device. - * @details Comments: - Before FLOW entry added related ip4 private base address must be set - at first. - In parameter napt_entry related entry flags must be set - Hardware entry id will be returned. - * @param[in] dev_id device id - * @param[in] FLOW cookie entry parameter - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -dess_flow_rfs_set(a_uint32_t dev_id, a_uint8_t action, fal_flow_rfs_t * rfs) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _dess_flow_rfs_set(dev_id, action, rfs); - HSL_API_UNLOCK; - return rv; -} - - - -sw_error_t -dess_nat_init(a_uint32_t dev_id) -{ - sw_error_t rv; - - HSL_DEV_ID_CHECK(dev_id); - aos_lock_init(&dess_nat_lock); - - rv = dess_nat_reset(dev_id); - SW_RTN_ON_ERROR(rv); - -#ifndef HSL_STANDALONG - { - hsl_api_t *p_api; - - SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id)); - - p_api->nat_add = dess_nat_add; - p_api->nat_del = dess_nat_del; - p_api->nat_get = dess_nat_get; - p_api->nat_next = dess_nat_next; - p_api->nat_counter_bind = dess_nat_counter_bind; - p_api->napt_add = dess_napt_add; - p_api->napt_del = dess_napt_del; - p_api->napt_get = dess_napt_get; - p_api->napt_next = dess_napt_next; - p_api->napt_counter_bind = dess_napt_counter_bind; - p_api->flow_add = dess_flow_add; - p_api->flow_del = dess_flow_del; - p_api->flow_get = dess_flow_get; - p_api->flow_next = dess_flow_next; - p_api->flow_counter_bind = dess_flow_counter_bind; - p_api->nat_status_set = dess_nat_status_set; - p_api->nat_status_get = dess_nat_status_get; - p_api->nat_hash_mode_set = dess_nat_hash_mode_set; - p_api->nat_hash_mode_get = dess_nat_hash_mode_get; - p_api->napt_status_set = dess_napt_status_set; - p_api->napt_status_get = dess_napt_status_get; - p_api->napt_mode_set = dess_napt_mode_set; - p_api->napt_mode_get = dess_napt_mode_get; - p_api->nat_pub_addr_add = dess_nat_pub_addr_add; - p_api->nat_pub_addr_del = dess_nat_pub_addr_del; - p_api->nat_pub_addr_next = dess_nat_pub_addr_next; - p_api->nat_unk_session_cmd_set = dess_nat_unk_session_cmd_set; - p_api->nat_unk_session_cmd_get = dess_nat_unk_session_cmd_get; - p_api->nat_prv_base_addr_set = dess_nat_prv_base_addr_set; - p_api->nat_prv_base_addr_get = dess_nat_prv_base_addr_get; - p_api->nat_prv_base_mask_set = dess_nat_prv_base_mask_set; - p_api->nat_prv_base_mask_get = dess_nat_prv_base_mask_get; - p_api->nat_global_set = dess_nat_global_set; - p_api->flow_cookie_set = dess_flow_cookie_set; - p_api->flow_rfs_set = dess_flow_rfs_set; - } -#endif - - return SW_OK; -} - -/** - * @} - */ diff --git a/feeds/ipq807x/qca-ssdk/src/src/hsl/dess/dess_port_ctrl.c b/feeds/ipq807x/qca-ssdk/src/src/hsl/dess/dess_port_ctrl.c deleted file mode 100755 index f038ee9ff..000000000 --- a/feeds/ipq807x/qca-ssdk/src/src/hsl/dess/dess_port_ctrl.c +++ /dev/null @@ -1,3983 +0,0 @@ -/* - * Copyright (c) 2014-2017, The Linux Foundation. All rights reserved. - * Permission to use, copy, modify, and/or distribute this software for - * any purpose with or without fee is hereby granted, provided that the - * above copyright notice and this permission notice appear in all copies. - * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES - * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR - * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES - * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN - * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT - * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. - */ - - -/** - * @defgroup dess_port_ctrl DESS_PORT_CONTROL - * @{ - */ -#include "sw.h" -#include "hsl.h" -#include "hsl_dev.h" -#include "hsl_port_prop.h" -#include "dess_port_ctrl.h" -#include "dess_reg.h" -#include "hsl_phy.h" - -#define DMA_MAX_VIRT_RING 8 -extern a_bool_t dess_mac_port_valid_check (fal_port_t port_id); - -/* -PORT0 egress 6 queues -PORT1~4 egress 4 queues -PORT5 egress 6 queues -*/ -static a_uint32_t port_queue[6] = { 6, 4, 4, 4, 4, 6 }; - - -static a_bool_t -_dess_port_phy_connected (a_uint32_t dev_id, fal_port_t port_id) -{ - if (0 == port_id) - { - return A_FALSE; - } - else - { - - return dess_mac_port_valid_check (port_id); - } -} - -static sw_error_t -_dess_port_duplex_set (a_uint32_t dev_id, fal_port_t port_id, - fal_port_duplex_t duplex) -{ - sw_error_t rv; - a_uint32_t phy_id; - hsl_phy_ops_t *phy_drv; - - HSL_DEV_ID_CHECK (dev_id); - - if (A_TRUE != hsl_port_prop_check (dev_id, port_id, HSL_PP_INCL_CPU)) - { - return SW_BAD_PARAM; - } - - SW_RTN_ON_NULL (phy_drv = hsl_phy_api_ops_get (dev_id, port_id)); - if (NULL == phy_drv->phy_duplex_set) - return SW_NOT_SUPPORTED; - - if (FAL_DUPLEX_BUTT <= duplex) - { - return SW_BAD_PARAM; - } - rv = hsl_port_prop_get_phyid (dev_id, port_id, &phy_id); - SW_RTN_ON_ERROR (rv); - - rv = phy_drv->phy_duplex_set (dev_id, phy_id, duplex); - SW_RTN_ON_ERROR (rv); -#if 0 - HSL_REG_ENTRY_GET (rv, dev_id, PORT_STATUS, port_id, - (a_uint8_t *) (®_val), sizeof (a_uint32_t)); - - /* for those ports without PHY device we set MAC register */ - if (A_FALSE == _dess_port_phy_connected (dev_id, port_id)) - { - SW_SET_REG_BY_FIELD (PORT_STATUS, LINK_EN, 0, reg_val); - if (FAL_HALF_DUPLEX == duplex) - { - SW_SET_REG_BY_FIELD (PORT_STATUS, DUPLEX_MODE, 0, reg_val); - } - else - { - SW_SET_REG_BY_FIELD (PORT_STATUS, DUPLEX_MODE, 1, reg_val); - } - reg_save = reg_val; - } - else - { - /* hardware requirement: set mac be config by sw and turn off RX/TX MAC */ - reg_save = reg_val; - SW_SET_REG_BY_FIELD (PORT_STATUS, LINK_EN, 0, reg_val); - SW_SET_REG_BY_FIELD (PORT_STATUS, RXMAC_EN, 0, reg_val); - SW_SET_REG_BY_FIELD (PORT_STATUS, TXMAC_EN, 0, reg_val); - - HSL_REG_ENTRY_SET (rv, dev_id, PORT_STATUS, port_id, - (a_uint8_t *) (®_val), sizeof (a_uint32_t)); - - rv = hsl_port_prop_get_phyid (dev_id, port_id, &phy_id); - SW_RTN_ON_ERROR (rv); - - rv = phy_drv->phy_duplex_set (dev_id, phy_id, duplex); - SW_RTN_ON_ERROR (rv); - - /* If MAC not in sync with PHY mode, the behavior is undefine. - You must be careful... */ - SW_GET_FIELD_BY_REG (PORT_STATUS, LINK_EN, force, reg_save); - if (!force) - { - if (FAL_HALF_DUPLEX == duplex) - { - SW_SET_REG_BY_FIELD (PORT_STATUS, DUPLEX_MODE, 0, reg_save); - } - else - { - SW_SET_REG_BY_FIELD (PORT_STATUS, DUPLEX_MODE, 1, reg_save); - } - } - } - - HSL_REG_ENTRY_SET (rv, dev_id, PORT_STATUS, port_id, - (a_uint8_t *) (®_save), sizeof (a_uint32_t)); - #endif - return rv; -} - -static sw_error_t -_dess_port_duplex_get (a_uint32_t dev_id, fal_port_t port_id, - fal_port_duplex_t * pduplex) -{ - sw_error_t rv = SW_OK; - a_uint32_t phy_id; - hsl_phy_ops_t *phy_drv; - - HSL_DEV_ID_CHECK (dev_id); - - if (A_TRUE != hsl_port_prop_check (dev_id, port_id, HSL_PP_INCL_CPU)) - { - return SW_BAD_PARAM; - } - - /* for those ports without PHY device supposed always full duplex */ - if (A_FALSE == _dess_port_phy_connected (dev_id, port_id)) - { - *pduplex = FAL_FULL_DUPLEX; - } - else - { - SW_RTN_ON_NULL (phy_drv = hsl_phy_api_ops_get (dev_id, port_id)); - if (NULL == phy_drv->phy_duplex_get) - return SW_NOT_SUPPORTED; - - rv = hsl_port_prop_get_phyid (dev_id, port_id, &phy_id); - SW_RTN_ON_ERROR (rv); - - rv = phy_drv->phy_duplex_get (dev_id, phy_id, pduplex); - SW_RTN_ON_ERROR (rv); - } -#if 0 - HSL_REG_ENTRY_GET (rv, dev_id, PORT_STATUS, port_id, - (a_uint8_t *) (®), sizeof (a_uint32_t)); - SW_GET_FIELD_BY_REG (PORT_STATUS, DUPLEX_MODE, field, reg); - if (field) - { - *pduplex = FAL_FULL_DUPLEX; - } - else - { - *pduplex = FAL_HALF_DUPLEX; - } - -#endif - - return rv; -} - -static sw_error_t -_dess_port_speed_set (a_uint32_t dev_id, fal_port_t port_id, - fal_port_speed_t speed) -{ - sw_error_t rv; - a_uint32_t phy_id; - hsl_phy_ops_t *phy_drv; - - HSL_DEV_ID_CHECK (dev_id); - - if (A_TRUE != hsl_port_prop_check (dev_id, port_id, HSL_PP_INCL_CPU)) - { - return SW_BAD_PARAM; - } - - SW_RTN_ON_NULL (phy_drv = hsl_phy_api_ops_get (dev_id, port_id)); - if (NULL == phy_drv->phy_speed_set) - return SW_NOT_SUPPORTED; - - if (FAL_SPEED_1000 < speed) - { - return SW_BAD_PARAM; - } - - rv = hsl_port_prop_get_phyid (dev_id, port_id, &phy_id); - SW_RTN_ON_ERROR (rv); - - rv = phy_drv->phy_speed_set (dev_id, phy_id, speed); - SW_RTN_ON_ERROR (rv); -#if 0 - HSL_REG_ENTRY_GET (rv, dev_id, PORT_STATUS, port_id, - (a_uint8_t *) (®_val), sizeof (a_uint32_t)); - - /* for those ports without PHY device we set MAC register */ - if (A_FALSE == _dess_port_phy_connected (dev_id, port_id)) - { - SW_SET_REG_BY_FIELD (PORT_STATUS, LINK_EN, 0, reg_val); - if (FAL_SPEED_10 == speed) - { - SW_SET_REG_BY_FIELD (PORT_STATUS, SPEED_MODE, 0, reg_val); - } - else if (FAL_SPEED_100 == speed) - { - SW_SET_REG_BY_FIELD (PORT_STATUS, SPEED_MODE, 1, reg_val); - } - else - { - SW_SET_REG_BY_FIELD (PORT_STATUS, SPEED_MODE, 2, reg_val); - } - reg_save = reg_val; - - } - else - { - /* hardware requirement: set mac be config by sw and turn off RX/TX MAC */ - reg_save = reg_val; - SW_SET_REG_BY_FIELD (PORT_STATUS, LINK_EN, 0, reg_val); - SW_SET_REG_BY_FIELD (PORT_STATUS, RXMAC_EN, 0, reg_val); - SW_SET_REG_BY_FIELD (PORT_STATUS, TXMAC_EN, 0, reg_val); - - HSL_REG_ENTRY_SET (rv, dev_id, PORT_STATUS, port_id, - (a_uint8_t *) (®_val), sizeof (a_uint32_t)); - - rv = hsl_port_prop_get_phyid (dev_id, port_id, &phy_id); - SW_RTN_ON_ERROR (rv); - - rv = phy_drv->phy_speed_set (dev_id, phy_id, speed); - SW_RTN_ON_ERROR (rv); - - /* If MAC not in sync with PHY mode, the behavior is undefine. - You must be careful... */ - SW_GET_FIELD_BY_REG (PORT_STATUS, LINK_EN, force, reg_save); - if (!force) - { - if (FAL_SPEED_10 == speed) - { - SW_SET_REG_BY_FIELD (PORT_STATUS, SPEED_MODE, 0, reg_save); - } - else if (FAL_SPEED_100 == speed) - { - SW_SET_REG_BY_FIELD (PORT_STATUS, SPEED_MODE, 1, reg_save); - } - else - { - SW_SET_REG_BY_FIELD (PORT_STATUS, SPEED_MODE, 2, reg_save); - } - } - } - - HSL_REG_ENTRY_SET (rv, dev_id, PORT_STATUS, port_id, - (a_uint8_t *) (®_save), sizeof (a_uint32_t)); - #endif - return rv; -} - -static sw_error_t -_dess_port_speed_get (a_uint32_t dev_id, fal_port_t port_id, - fal_port_speed_t * pspeed) -{ - sw_error_t rv = SW_OK; - a_uint32_t phy_id; - hsl_phy_ops_t *phy_drv; - - HSL_DEV_ID_CHECK (dev_id); - - if (A_TRUE != hsl_port_prop_check (dev_id, port_id, HSL_PP_INCL_CPU)) - { - return SW_BAD_PARAM; - } - - /* for those ports without PHY device supposed always 1000Mbps */ - if (A_FALSE == _dess_port_phy_connected (dev_id, port_id)) - { - *pspeed = FAL_SPEED_1000; - } - else - { - SW_RTN_ON_NULL (phy_drv = hsl_phy_api_ops_get (dev_id, port_id)); - if (NULL == phy_drv->phy_speed_get) - return SW_NOT_SUPPORTED; - - rv = hsl_port_prop_get_phyid (dev_id, port_id, &phy_id); - SW_RTN_ON_ERROR (rv); - rv = phy_drv->phy_speed_get (dev_id, phy_id, pspeed); - SW_RTN_ON_ERROR (rv); - } -#if 0 - HSL_REG_ENTRY_GET (rv, dev_id, PORT_STATUS, port_id, - (a_uint8_t *) (®), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR (rv); - - SW_GET_FIELD_BY_REG (PORT_STATUS, SPEED_MODE, field, reg); - if (0 == field) - { - *pspeed = FAL_SPEED_10; - } - else if (1 == field) - { - *pspeed = FAL_SPEED_100; - } - else if (2 == field) - { - *pspeed = FAL_SPEED_1000; - } - else - { - *pspeed = FAL_SPEED_BUTT; - rv = SW_READ_ERROR; - } -#endif - - return rv; -} - -static sw_error_t -_dess_port_autoneg_status_get (a_uint32_t dev_id, fal_port_t port_id, - a_bool_t * status) -{ - a_uint32_t phy_id; - sw_error_t rv; - hsl_phy_ops_t *phy_drv; - - HSL_DEV_ID_CHECK (dev_id); - - if (A_TRUE != hsl_port_prop_check (dev_id, port_id, HSL_PP_PHY)) - { - return SW_BAD_PARAM; - } - - SW_RTN_ON_NULL (phy_drv = hsl_phy_api_ops_get (dev_id, port_id)); - if (NULL == phy_drv->phy_autoneg_status_get) - return SW_NOT_SUPPORTED; - - rv = hsl_port_prop_get_phyid (dev_id, port_id, &phy_id); - SW_RTN_ON_ERROR (rv); - - *status = phy_drv->phy_autoneg_status_get (dev_id, phy_id); - - return SW_OK; -} - -static sw_error_t -_dess_port_autoneg_enable (a_uint32_t dev_id, fal_port_t port_id) -{ - sw_error_t rv; - a_uint32_t phy_id; - hsl_phy_ops_t *phy_drv; - - HSL_DEV_ID_CHECK (dev_id); - - if (A_TRUE != hsl_port_prop_check (dev_id, port_id, HSL_PP_PHY)) - { - return SW_BAD_PARAM; - } - - SW_RTN_ON_NULL (phy_drv = hsl_phy_api_ops_get (dev_id, port_id)); - if (NULL == phy_drv->phy_autoneg_enable_set) - return SW_NOT_SUPPORTED; - - rv = hsl_port_prop_get_phyid (dev_id, port_id, &phy_id); - SW_RTN_ON_ERROR (rv); - - rv = phy_drv->phy_autoneg_enable_set (dev_id, phy_id); - return rv; -} - -static sw_error_t -_dess_port_autoneg_restart (a_uint32_t dev_id, fal_port_t port_id) -{ - sw_error_t rv; - a_uint32_t phy_id; - hsl_phy_ops_t *phy_drv; - - HSL_DEV_ID_CHECK (dev_id); - - if (A_TRUE != hsl_port_prop_check (dev_id, port_id, HSL_PP_PHY)) - { - return SW_BAD_PARAM; - } - - SW_RTN_ON_NULL (phy_drv = hsl_phy_api_ops_get (dev_id, port_id)); - if (NULL == phy_drv->phy_restart_autoneg) - return SW_NOT_SUPPORTED; - - rv = hsl_port_prop_get_phyid (dev_id, port_id, &phy_id); - SW_RTN_ON_ERROR (rv); - - rv = phy_drv->phy_restart_autoneg (dev_id, phy_id); - return rv; -} - -static sw_error_t -_dess_port_autoneg_adv_set (a_uint32_t dev_id, fal_port_t port_id, - a_uint32_t autoadv) -{ - sw_error_t rv; - a_uint32_t phy_id; - hsl_phy_ops_t *phy_drv; - - HSL_DEV_ID_CHECK (dev_id); - - if (A_TRUE != hsl_port_prop_check (dev_id, port_id, HSL_PP_PHY)) - { - return SW_BAD_PARAM; - } - - SW_RTN_ON_NULL (phy_drv = hsl_phy_api_ops_get (dev_id, port_id)); - if (NULL == phy_drv->phy_autoneg_adv_set) - return SW_NOT_SUPPORTED; - - rv = hsl_port_prop_get_phyid (dev_id, port_id, &phy_id); - SW_RTN_ON_ERROR (rv); - - rv = phy_drv->phy_autoneg_adv_set (dev_id, phy_id, autoadv); - SW_RTN_ON_ERROR (rv); - - return SW_OK; -} - -static sw_error_t -_dess_port_autoneg_adv_get (a_uint32_t dev_id, fal_port_t port_id, - a_uint32_t * autoadv) -{ - sw_error_t rv; - a_uint32_t phy_id; - hsl_phy_ops_t *phy_drv; - - HSL_DEV_ID_CHECK (dev_id); - - if (A_TRUE != hsl_port_prop_check (dev_id, port_id, HSL_PP_PHY)) - { - return SW_BAD_PARAM; - } - - SW_RTN_ON_NULL (phy_drv = hsl_phy_api_ops_get (dev_id, port_id)); - if (NULL == phy_drv->phy_autoneg_adv_get) - return SW_NOT_SUPPORTED; - - rv = hsl_port_prop_get_phyid (dev_id, port_id, &phy_id); - SW_RTN_ON_ERROR (rv); - - *autoadv = 0; - rv = phy_drv->phy_autoneg_adv_get (dev_id, phy_id, autoadv); - SW_RTN_ON_ERROR (rv); - - return SW_OK; -} - -static sw_error_t -_dess_port_flowctrl_set (a_uint32_t dev_id, fal_port_t port_id, - a_bool_t enable) -{ - sw_error_t rv; - a_uint32_t val, force, reg = 0, tmp; - - if (A_TRUE != hsl_port_prop_check (dev_id, port_id, HSL_PP_INCL_CPU)) - { - return SW_BAD_PARAM; - } - - if (A_TRUE == enable) - { - val = 1; - } - else if (A_FALSE == enable) - { - val = 0; - } - else - { - return SW_BAD_PARAM; - } - - HSL_REG_ENTRY_GET (rv, dev_id, PORT_STATUS, port_id, - (a_uint8_t *) (®), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR (rv); - - SW_GET_FIELD_BY_REG (PORT_STATUS, FLOW_LINK_EN, force, reg); - if (force) - { - /* flow control isn't in force mode so can't set */ - return SW_DISABLE; - } - tmp = reg; - - SW_SET_REG_BY_FIELD (PORT_STATUS, RX_FLOW_EN, val, reg); - SW_SET_REG_BY_FIELD (PORT_STATUS, TX_FLOW_EN, val, reg); - SW_SET_REG_BY_FIELD (PORT_STATUS, TX_HALF_FLOW_EN, val, reg); - if (reg == tmp) - return SW_OK; - - HSL_REG_ENTRY_SET (rv, dev_id, PORT_STATUS, port_id, - (a_uint8_t *) (®), sizeof (a_uint32_t)); - return rv; -} - -static sw_error_t -_dess_port_flowctrl_thresh_set (a_uint32_t dev_id, fal_port_t port_id, - a_uint8_t on, a_uint8_t off) -{ - sw_error_t rv; - a_uint32_t reg = 0; - - reg = (on << 16) | off; - HSL_REG_ENTRY_SET (rv, dev_id, PORT_FLOC_CTRL_THRESH, port_id, - (a_uint8_t *) (®), sizeof (a_uint32_t)); - return rv; -} - -static sw_error_t -_dess_port_flowctrl_get (a_uint32_t dev_id, fal_port_t port_id, - a_bool_t * enable) -{ - sw_error_t rv; - a_uint32_t rx, reg = 0; - - if (A_TRUE != hsl_port_prop_check (dev_id, port_id, HSL_PP_INCL_CPU)) - { - return SW_BAD_PARAM; - } - - HSL_REG_ENTRY_GET (rv, dev_id, PORT_STATUS, port_id, - (a_uint8_t *) (®), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR (rv); - - SW_GET_FIELD_BY_REG (PORT_STATUS, RX_FLOW_EN, rx, reg); - - if (1 == rx) - { - *enable = A_TRUE; - } - else - { - *enable = A_FALSE; - } - - return SW_OK; -} - -static sw_error_t -_dess_port_flowctrl_forcemode_set (a_uint32_t dev_id, fal_port_t port_id, - a_bool_t enable) -{ - sw_error_t rv; - a_uint32_t reg = 0, tmp; - - if (A_TRUE != hsl_port_prop_check (dev_id, port_id, HSL_PP_INCL_CPU)) - { - return SW_BAD_PARAM; - } - - HSL_REG_ENTRY_GET (rv, dev_id, PORT_STATUS, port_id, - (a_uint8_t *) (®), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR (rv); - SW_GET_FIELD_BY_REG(PORT_STATUS, FLOW_LINK_EN, tmp, reg); - - if (A_TRUE == enable) - { - if (tmp== 0) - return SW_OK; - SW_SET_REG_BY_FIELD (PORT_STATUS, FLOW_LINK_EN, 0, reg); - } - else if (A_FALSE == enable) - { - /* for those ports without PHY, it can't sync flow control status */ - if (A_FALSE == _dess_port_phy_connected (dev_id, port_id)) - { - return SW_DISABLE; - } - if (tmp == 1) - return SW_OK; - SW_SET_REG_BY_FIELD (PORT_STATUS, FLOW_LINK_EN, 1, reg); - } - else - { - return SW_BAD_PARAM; - } - - HSL_REG_ENTRY_SET (rv, dev_id, PORT_STATUS, port_id, - (a_uint8_t *) (®), sizeof (a_uint32_t)); - return rv; -} - -static sw_error_t -_dess_port_flowctrl_forcemode_get (a_uint32_t dev_id, fal_port_t port_id, - a_bool_t * enable) -{ - sw_error_t rv; - a_uint32_t force, reg; - - if (A_TRUE != hsl_port_prop_check (dev_id, port_id, HSL_PP_INCL_CPU)) - { - return SW_BAD_PARAM; - } - - HSL_REG_ENTRY_GET (rv, dev_id, PORT_STATUS, port_id, - (a_uint8_t *) (®), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR (rv); - - SW_GET_FIELD_BY_REG (PORT_STATUS, FLOW_LINK_EN, force, reg); - if (0 == force) - { - *enable = A_TRUE; - } - else - { - *enable = A_FALSE; - } - - return SW_OK; -} - -static sw_error_t -_dess_port_powersave_set (a_uint32_t dev_id, fal_port_t port_id, - a_bool_t enable) -{ - sw_error_t rv; - a_uint32_t phy_id = 0; - hsl_phy_ops_t *phy_drv; - - HSL_DEV_ID_CHECK (dev_id); - - if (A_TRUE != hsl_port_prop_check (dev_id, port_id, HSL_PP_PHY)) - { - return SW_BAD_PARAM; - } - - SW_RTN_ON_NULL (phy_drv = hsl_phy_api_ops_get (dev_id, port_id)); - if (NULL == phy_drv->phy_powersave_set) - return SW_NOT_SUPPORTED; - - rv = hsl_port_prop_get_phyid (dev_id, port_id, &phy_id); - SW_RTN_ON_ERROR (rv); - - rv = phy_drv->phy_powersave_set (dev_id, phy_id, enable); - - return rv; -} - -static sw_error_t -_dess_port_powersave_get (a_uint32_t dev_id, fal_port_t port_id, - a_bool_t * enable) -{ - sw_error_t rv; - a_uint32_t phy_id = 0; - hsl_phy_ops_t *phy_drv; - - HSL_DEV_ID_CHECK (dev_id); - - if (A_TRUE != hsl_port_prop_check (dev_id, port_id, HSL_PP_PHY)) - { - return SW_BAD_PARAM; - } - - SW_RTN_ON_NULL (phy_drv = hsl_phy_api_ops_get (dev_id, port_id)); - if (NULL == phy_drv->phy_powersave_get) - return SW_NOT_SUPPORTED; - - rv = hsl_port_prop_get_phyid (dev_id, port_id, &phy_id); - SW_RTN_ON_ERROR (rv); - - rv = phy_drv->phy_powersave_get (dev_id, phy_id, enable); - - return rv; -} - -static sw_error_t -_dess_port_hibernate_set (a_uint32_t dev_id, fal_port_t port_id, - a_bool_t enable) -{ - sw_error_t rv; - a_uint32_t phy_id = 0; - hsl_phy_ops_t *phy_drv; - - HSL_DEV_ID_CHECK (dev_id); - - if (A_TRUE != hsl_port_prop_check (dev_id, port_id, HSL_PP_PHY)) - { - return SW_BAD_PARAM; - } - - SW_RTN_ON_NULL (phy_drv = hsl_phy_api_ops_get (dev_id, port_id)); - if (NULL == phy_drv->phy_hibernation_set) - return SW_NOT_SUPPORTED; - - rv = hsl_port_prop_get_phyid (dev_id, port_id, &phy_id); - SW_RTN_ON_ERROR (rv); - - rv = phy_drv->phy_hibernation_set (dev_id, phy_id, enable); - - return rv; -} - -static sw_error_t -_dess_port_hibernate_get (a_uint32_t dev_id, fal_port_t port_id, - a_bool_t * enable) -{ - sw_error_t rv; - a_uint32_t phy_id = 0; - hsl_phy_ops_t *phy_drv; - - HSL_DEV_ID_CHECK (dev_id); - - if (A_TRUE != hsl_port_prop_check (dev_id, port_id, HSL_PP_PHY)) - { - return SW_BAD_PARAM; - } - - SW_RTN_ON_NULL (phy_drv = hsl_phy_api_ops_get (dev_id, port_id)); - if (NULL == phy_drv->phy_hibernation_get) - return SW_NOT_SUPPORTED; - - rv = hsl_port_prop_get_phyid (dev_id, port_id, &phy_id); - SW_RTN_ON_ERROR (rv); - - rv = phy_drv->phy_hibernation_get (dev_id, phy_id, enable); - - return rv; -} - -static sw_error_t -_dess_port_cdt (a_uint32_t dev_id, fal_port_t port_id, a_uint32_t mdi_pair, - fal_cable_status_t * cable_status, a_uint32_t * cable_len) -{ - sw_error_t rv; - a_uint32_t phy_id = 0; - hsl_phy_ops_t *phy_drv; - - HSL_DEV_ID_CHECK (dev_id); - - if (A_TRUE != hsl_port_prop_check (dev_id, port_id, HSL_PP_PHY)) - { - return SW_BAD_PARAM; - } - - SW_RTN_ON_NULL (phy_drv = hsl_phy_api_ops_get (dev_id, port_id)); - if (NULL == phy_drv->phy_cdt) - return SW_NOT_SUPPORTED; - - rv = hsl_port_prop_get_phyid (dev_id, port_id, &phy_id); - SW_RTN_ON_ERROR (rv); - - rv = phy_drv->phy_cdt (dev_id, phy_id, mdi_pair, cable_status, cable_len); - - return rv; -} - -static sw_error_t -_dess_port_rxhdr_mode_set (a_uint32_t dev_id, fal_port_t port_id, - fal_port_header_mode_t mode) -{ - sw_error_t rv; - a_uint32_t val = 0; - - HSL_DEV_ID_CHECK (dev_id); - - if (A_TRUE != hsl_port_prop_check (dev_id, port_id, HSL_PP_INCL_CPU)) - { - return SW_BAD_PARAM; - } - - if (FAL_NO_HEADER_EN == mode) - { - val = 0; - } - else if (FAL_ONLY_MANAGE_FRAME_EN == mode && port_id != 0) - { - val = 1; - } - else if (FAL_ALL_TYPE_FRAME_EN == mode) - { - val = 2; - } - else - { - return SW_BAD_PARAM; - } - - HSL_REG_FIELD_SET (rv, dev_id, PORT_HDR_CTL, port_id, RXHDR_MODE, - (a_uint8_t *) (&val), sizeof (a_uint32_t)); - return rv; -} - -static sw_error_t -_dess_port_rxhdr_mode_get (a_uint32_t dev_id, fal_port_t port_id, - fal_port_header_mode_t * mode) -{ - sw_error_t rv; - a_uint32_t val; - - HSL_DEV_ID_CHECK (dev_id); - - if (A_TRUE != hsl_port_prop_check (dev_id, port_id, HSL_PP_INCL_CPU)) - { - return SW_BAD_PARAM; - } - - HSL_REG_FIELD_GET (rv, dev_id, PORT_HDR_CTL, port_id, RXHDR_MODE, - (a_uint8_t *) (&val), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR (rv); - - if (1 == val) - { - *mode = FAL_ONLY_MANAGE_FRAME_EN; - } - else if (2 == val) - { - *mode = FAL_ALL_TYPE_FRAME_EN; - } - else - { - *mode = FAL_NO_HEADER_EN; - } - - return SW_OK; -} - -static sw_error_t -_dess_port_txhdr_mode_set (a_uint32_t dev_id, fal_port_t port_id, - fal_port_header_mode_t mode) -{ - sw_error_t rv; - a_uint32_t val = 0; - - HSL_DEV_ID_CHECK (dev_id); - - if (A_TRUE != hsl_port_prop_check (dev_id, port_id, HSL_PP_EXCL_CPU)) - { - return SW_BAD_PARAM; - } - - if (FAL_NO_HEADER_EN == mode) - { - val = 0; - } - else if (FAL_ONLY_MANAGE_FRAME_EN == mode) - { - val = 1; - } - else if (FAL_ALL_TYPE_FRAME_EN == mode) - { - val = 2; - } - else - { - return SW_BAD_PARAM; - } - - HSL_REG_FIELD_SET (rv, dev_id, PORT_HDR_CTL, port_id, TXHDR_MODE, - (a_uint8_t *) (&val), sizeof (a_uint32_t)); - return rv; -} - -static sw_error_t -_dess_port_txhdr_mode_get (a_uint32_t dev_id, fal_port_t port_id, - fal_port_header_mode_t * mode) -{ - sw_error_t rv; - a_uint32_t val = 0; - - HSL_DEV_ID_CHECK (dev_id); - - if (A_TRUE != hsl_port_prop_check (dev_id, port_id, HSL_PP_EXCL_CPU)) - { - return SW_BAD_PARAM; - } - - HSL_REG_FIELD_GET (rv, dev_id, PORT_HDR_CTL, port_id, TXHDR_MODE, - (a_uint8_t *) (&val), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR (rv); - - if (1 == val) - { - *mode = FAL_ONLY_MANAGE_FRAME_EN; - } - else if (2 == val) - { - *mode = FAL_ALL_TYPE_FRAME_EN; - } - else - { - *mode = FAL_NO_HEADER_EN; - } - - return SW_OK; -} - -static sw_error_t -_dess_header_type_set (a_uint32_t dev_id, a_bool_t enable, a_uint32_t type) -{ - a_uint32_t reg = 0; - sw_error_t rv; - - HSL_DEV_ID_CHECK (dev_id); - - HSL_REG_ENTRY_GET (rv, dev_id, HEADER_CTL, 0, - (a_uint8_t *) (®), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR (rv); - - if (A_TRUE == enable) - { - if (0xffff < type) - { - return SW_BAD_PARAM; - } - SW_SET_REG_BY_FIELD (HEADER_CTL, TYPE_LEN, 1, reg); - SW_SET_REG_BY_FIELD (HEADER_CTL, TYPE_VAL, type, reg); - } - else if (A_FALSE == enable) - { - SW_SET_REG_BY_FIELD (HEADER_CTL, TYPE_LEN, 0, reg); - SW_SET_REG_BY_FIELD (HEADER_CTL, TYPE_VAL, 0, reg); - } - else - { - return SW_BAD_PARAM; - } - - HSL_REG_ENTRY_SET (rv, dev_id, HEADER_CTL, 0, - (a_uint8_t *) (®), sizeof (a_uint32_t)); - return rv; -} - -static sw_error_t -_dess_header_type_get (a_uint32_t dev_id, a_bool_t * enable, - a_uint32_t * type) -{ - a_uint32_t data, reg = 0; - sw_error_t rv; - - HSL_DEV_ID_CHECK (dev_id); - - HSL_REG_ENTRY_GET (rv, dev_id, HEADER_CTL, 0, - (a_uint8_t *) (®), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR (rv); - - SW_GET_FIELD_BY_REG (HEADER_CTL, TYPE_LEN, data, reg); - if (data) - { - SW_GET_FIELD_BY_REG (HEADER_CTL, TYPE_VAL, data, reg); - *enable = A_TRUE; - *type = data; - } - else - { - *enable = A_FALSE; - *type = 0; - } - - return SW_OK; -} - -static sw_error_t -_dess_port_txmac_status_set (a_uint32_t dev_id, fal_port_t port_id, - a_bool_t enable) -{ - sw_error_t rv; - a_uint32_t reg, force, val = 0, tmp; - - HSL_DEV_ID_CHECK (dev_id); - - if (A_TRUE != hsl_port_prop_check (dev_id, port_id, HSL_PP_INCL_CPU)) - { - return SW_BAD_PARAM; - } - - HSL_REG_ENTRY_GET (rv, dev_id, PORT_STATUS, port_id, - (a_uint8_t *) (®), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR (rv); - - if (A_TRUE == enable) - { - val = 1; - } - else if (A_FALSE == enable) - { - val = 0; - } - else - { - return SW_BAD_PARAM; - } - tmp = reg; - - /* for those ports without PHY device we set MAC register */ - if (A_FALSE == _dess_port_phy_connected (dev_id, port_id)) - { - SW_SET_REG_BY_FIELD (PORT_STATUS, LINK_EN, 0, reg); - SW_SET_REG_BY_FIELD (PORT_STATUS, TXMAC_EN, val, reg); - } - else - { - SW_GET_FIELD_BY_REG (PORT_STATUS, LINK_EN, force, reg); - if (force) - { - /* link isn't in force mode so can't set */ - return SW_DISABLE; - } - else - { - SW_SET_REG_BY_FIELD (PORT_STATUS, TXMAC_EN, val, reg); - } - } - if (tmp == reg) - return SW_OK; - HSL_REG_ENTRY_SET (rv, dev_id, PORT_STATUS, port_id, - (a_uint8_t *) (®), sizeof (a_uint32_t)); - return rv; -} - -static sw_error_t -_dess_port_txmac_status_get (a_uint32_t dev_id, fal_port_t port_id, - a_bool_t * enable) -{ - sw_error_t rv; - a_uint32_t val = 0; - - HSL_DEV_ID_CHECK (dev_id); - - if (A_TRUE != hsl_port_prop_check (dev_id, port_id, HSL_PP_INCL_CPU)) - { - return SW_BAD_PARAM; - } - - HSL_REG_FIELD_GET (rv, dev_id, PORT_STATUS, port_id, TXMAC_EN, - (a_uint8_t *) (&val), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR (rv); - - if (val) - { - *enable = A_TRUE; - } - else - { - *enable = A_FALSE; - } - - return SW_OK; -} - -static sw_error_t -_dess_port_rxmac_status_set (a_uint32_t dev_id, fal_port_t port_id, - a_bool_t enable) -{ - sw_error_t rv; - a_uint32_t reg = 0, force, val = 0, tmp = 0; - - HSL_DEV_ID_CHECK (dev_id); - - if (A_TRUE != hsl_port_prop_check (dev_id, port_id, HSL_PP_INCL_CPU)) - { - return SW_BAD_PARAM; - } - - HSL_REG_ENTRY_GET (rv, dev_id, PORT_STATUS, port_id, - (a_uint8_t *) (®), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR (rv); - - if (A_TRUE == enable) - { - val = 1; - } - else if (A_FALSE == enable) - { - val = 0; - } - else - { - return SW_BAD_PARAM; - } - tmp = reg; - - /* for those ports without PHY device we set MAC register */ - if (A_FALSE == _dess_port_phy_connected (dev_id, port_id)) - { - SW_SET_REG_BY_FIELD (PORT_STATUS, LINK_EN, 0, reg); - SW_SET_REG_BY_FIELD (PORT_STATUS, RXMAC_EN, val, reg); - } - else - { - SW_GET_FIELD_BY_REG (PORT_STATUS, LINK_EN, force, reg); - if (force) - { - /* link isn't in force mode so can't set */ - return SW_DISABLE; - } - else - { - SW_SET_REG_BY_FIELD (PORT_STATUS, RXMAC_EN, val, reg); - } - } - if (tmp == reg) - return SW_OK; - HSL_REG_ENTRY_SET (rv, dev_id, PORT_STATUS, port_id, - (a_uint8_t *) (®), sizeof (a_uint32_t)); - return rv; -} - -static sw_error_t -_dess_port_rxmac_status_get (a_uint32_t dev_id, fal_port_t port_id, - a_bool_t * enable) -{ - sw_error_t rv; - a_uint32_t val = 0; - - HSL_DEV_ID_CHECK (dev_id); - - if (A_TRUE != hsl_port_prop_check (dev_id, port_id, HSL_PP_INCL_CPU)) - { - return SW_BAD_PARAM; - } - - HSL_REG_FIELD_GET (rv, dev_id, PORT_STATUS, port_id, RXMAC_EN, - (a_uint8_t *) (&val), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR (rv); - - if (val) - { - *enable = A_TRUE; - } - else - { - *enable = A_FALSE; - } - - return SW_OK; -} - -static sw_error_t -_dess_port_txfc_status_set (a_uint32_t dev_id, fal_port_t port_id, - a_bool_t enable) -{ - sw_error_t rv; - a_uint32_t val = 0, reg = 0, force, tmp; - - HSL_DEV_ID_CHECK (dev_id); - - if (A_TRUE != hsl_port_prop_check (dev_id, port_id, HSL_PP_INCL_CPU)) - { - return SW_BAD_PARAM; - } - - if (A_TRUE == enable) - { - val = 1; - } - else if (A_FALSE == enable) - { - val = 0; - } - else - { - return SW_BAD_PARAM; - } - - HSL_REG_ENTRY_GET (rv, dev_id, PORT_STATUS, port_id, - (a_uint8_t *) (®), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR (rv); - tmp = reg; - - /* for those ports without PHY device we set MAC register */ - if (A_FALSE == _dess_port_phy_connected (dev_id, port_id)) - { - SW_SET_REG_BY_FIELD (PORT_STATUS, FLOW_LINK_EN, 0, reg); - SW_SET_REG_BY_FIELD (PORT_STATUS, TX_FLOW_EN, val, reg); - } - else - { - SW_GET_FIELD_BY_REG (PORT_STATUS, FLOW_LINK_EN, force, reg); - if (force) - { - /* flow control isn't in force mode so can't set */ - return SW_DISABLE; - } - else - { - SW_SET_REG_BY_FIELD (PORT_STATUS, TX_FLOW_EN, val, reg); - } - } - if (tmp == reg) - return SW_OK; - HSL_REG_ENTRY_SET (rv, dev_id, PORT_STATUS, port_id, - (a_uint8_t *) (®), sizeof (a_uint32_t)); - return rv; -} - -static sw_error_t -_dess_port_txfc_status_get (a_uint32_t dev_id, fal_port_t port_id, - a_bool_t * enable) -{ - sw_error_t rv; - a_uint32_t val; - - HSL_DEV_ID_CHECK (dev_id); - - if (A_TRUE != hsl_port_prop_check (dev_id, port_id, HSL_PP_INCL_CPU)) - { - return SW_BAD_PARAM; - } - - HSL_REG_FIELD_GET (rv, dev_id, PORT_STATUS, port_id, TX_FLOW_EN, - (a_uint8_t *) (&val), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR (rv); - - if (val) - { - *enable = A_TRUE; - } - else - { - *enable = A_FALSE; - } - - return SW_OK; -} - -static sw_error_t -_dess_port_rxfc_status_set (a_uint32_t dev_id, fal_port_t port_id, - a_bool_t enable) -{ - sw_error_t rv; - a_uint32_t val = 0, reg, force, tmp; - - HSL_DEV_ID_CHECK (dev_id); - - if (A_TRUE != hsl_port_prop_check (dev_id, port_id, HSL_PP_INCL_CPU)) - { - return SW_BAD_PARAM; - } - - if (A_TRUE == enable) - { - val = 1; - } - else if (A_FALSE == enable) - { - val = 0; - } - else - { - return SW_BAD_PARAM; - } - - HSL_REG_ENTRY_GET (rv, dev_id, PORT_STATUS, port_id, - (a_uint8_t *) (®), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR (rv); - tmp = reg; - - /* for those ports without PHY device we set MAC register */ - if (A_FALSE == _dess_port_phy_connected (dev_id, port_id)) - { - SW_SET_REG_BY_FIELD (PORT_STATUS, FLOW_LINK_EN, 0, reg); - SW_SET_REG_BY_FIELD (PORT_STATUS, RX_FLOW_EN, val, reg); - } - else - { - SW_GET_FIELD_BY_REG (PORT_STATUS, FLOW_LINK_EN, force, reg); - if (force) - { - /* flow control isn't in force mode so can't set */ - return SW_DISABLE; - } - else - { - SW_SET_REG_BY_FIELD (PORT_STATUS, RX_FLOW_EN, val, reg); - } - } - if (tmp == reg) - return SW_OK; - HSL_REG_ENTRY_SET (rv, dev_id, PORT_STATUS, port_id, - (a_uint8_t *) (®), sizeof (a_uint32_t)); - return rv; -} - -static sw_error_t -_dess_port_rxfc_status_get (a_uint32_t dev_id, fal_port_t port_id, - a_bool_t * enable) -{ - sw_error_t rv; - a_uint32_t val; - - HSL_DEV_ID_CHECK (dev_id); - - if (A_TRUE != hsl_port_prop_check (dev_id, port_id, HSL_PP_INCL_CPU)) - { - return SW_BAD_PARAM; - } - - HSL_REG_FIELD_GET (rv, dev_id, PORT_STATUS, port_id, RX_FLOW_EN, - (a_uint8_t *) (&val), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR (rv); - - if (val) - { - *enable = A_TRUE; - } - else - { - *enable = A_FALSE; - } - - return SW_OK; -} - -static sw_error_t -_dess_port_bp_status_set (a_uint32_t dev_id, fal_port_t port_id, - a_bool_t enable) -{ - sw_error_t rv; - a_uint32_t val = 0, tmp = 0; - - HSL_DEV_ID_CHECK (dev_id); - - if (A_TRUE != hsl_port_prop_check (dev_id, port_id, HSL_PP_INCL_CPU)) - { - return SW_BAD_PARAM; - } - - if (A_TRUE == enable) - { - val = 1; - } - else if (A_FALSE == enable) - { - val = 0; - } - else - { - return SW_BAD_PARAM; - } - HSL_REG_FIELD_GET (rv, dev_id, PORT_STATUS, port_id, TX_HALF_FLOW_EN, - (a_uint8_t *) (&tmp), sizeof (a_uint32_t)); - if (tmp == val) - return SW_OK; - - HSL_REG_FIELD_SET (rv, dev_id, PORT_STATUS, port_id, TX_HALF_FLOW_EN, - (a_uint8_t *) (&val), sizeof (a_uint32_t)); - return rv; -} - -static sw_error_t -_dess_port_bp_status_get (a_uint32_t dev_id, fal_port_t port_id, - a_bool_t * enable) -{ - sw_error_t rv; - a_uint32_t val = 0; - - HSL_DEV_ID_CHECK (dev_id); - - if (A_TRUE != hsl_port_prop_check (dev_id, port_id, HSL_PP_INCL_CPU)) - { - return SW_BAD_PARAM; - } - - HSL_REG_FIELD_GET (rv, dev_id, PORT_STATUS, port_id, TX_HALF_FLOW_EN, - (a_uint8_t *) (&val), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR (rv); - - if (val) - { - *enable = A_TRUE; - } - else - { - *enable = A_FALSE; - } - - return SW_OK; -} - -static sw_error_t -_dess_port_link_forcemode_set (a_uint32_t dev_id, fal_port_t port_id, - a_bool_t enable) -{ - sw_error_t rv; - a_uint32_t reg = 0, tmp = 0; - - HSL_DEV_ID_CHECK (dev_id); - - if (A_TRUE != hsl_port_prop_check (dev_id, port_id, HSL_PP_EXCL_CPU)) - { - return SW_BAD_PARAM; - } - - HSL_REG_ENTRY_GET (rv, dev_id, PORT_STATUS, port_id, - (a_uint8_t *) (®), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR (rv); - SW_GET_FIELD_BY_REG(PORT_STATUS, LINK_EN, tmp, reg); - - if (A_TRUE == enable) - { - if(tmp == 0) - return SW_OK; - SW_SET_REG_BY_FIELD (PORT_STATUS, LINK_EN, 0, reg); - } - else if (A_FALSE == enable) - { - if(tmp == 1) - return SW_OK; - /* for those ports without PHY, it can't sync link status */ - if (A_FALSE == _dess_port_phy_connected (dev_id, port_id)) - { - return SW_DISABLE; - } - SW_SET_REG_BY_FIELD (PORT_STATUS, LINK_EN, 1, reg); - } - else - { - return SW_BAD_PARAM; - } - - HSL_REG_ENTRY_SET (rv, dev_id, PORT_STATUS, port_id, - (a_uint8_t *) (®), sizeof (a_uint32_t)); - return rv; -} - -static sw_error_t -_dess_port_link_forcemode_get (a_uint32_t dev_id, fal_port_t port_id, - a_bool_t * enable) -{ - sw_error_t rv; - a_uint32_t val = 0; - - HSL_DEV_ID_CHECK (dev_id); - - if (A_TRUE != hsl_port_prop_check (dev_id, port_id, HSL_PP_EXCL_CPU)) - { - return SW_BAD_PARAM; - } - - HSL_REG_FIELD_GET (rv, dev_id, PORT_STATUS, port_id, LINK_EN, - (a_uint8_t *) (&val), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR (rv); - - if (0 == val) - { - *enable = A_TRUE; - } - else - { - *enable = A_FALSE; - } - - return SW_OK; -} - -static sw_error_t -_dess_port_link_status_get (a_uint32_t dev_id, fal_port_t port_id, - a_bool_t * status) -{ - sw_error_t rv; - a_uint32_t phy_id; - hsl_phy_ops_t *phy_drv; - - HSL_DEV_ID_CHECK (dev_id); - - if (A_TRUE != hsl_port_prop_check (dev_id, port_id, HSL_PP_INCL_CPU)) - { - return SW_BAD_PARAM; - } - - /* for those ports without PHY device supposed always link up */ - if (A_FALSE == _dess_port_phy_connected (dev_id, port_id)) - { - *status = A_TRUE; - } - else - { - SW_RTN_ON_NULL (phy_drv = hsl_phy_api_ops_get (dev_id, port_id)); - if (NULL == phy_drv->phy_link_status_get) - return SW_NOT_SUPPORTED; - - rv = hsl_port_prop_get_phyid (dev_id, port_id, &phy_id); - SW_RTN_ON_ERROR (rv); - - if (A_TRUE == phy_drv->phy_link_status_get (dev_id, phy_id)) - { - *status = A_TRUE; - } - else - { - *status = A_FALSE; - } - } - - return SW_OK; -} - -static sw_error_t -_dess_ports_link_status_get(a_uint32_t dev_id, a_uint32_t * status) -{ - sw_error_t rv; - a_uint32_t port_id; - a_uint32_t phy_id; - hsl_dev_t *pdev = NULL; - hsl_phy_ops_t *phy_drv; - a_uint32_t port_bmp[SW_MAX_NR_DEV] = {0}; - - HSL_DEV_ID_CHECK(dev_id); - - pdev = hsl_dev_ptr_get(dev_id); - if (pdev == NULL) - return SW_NOT_INITIALIZED; - - port_bmp[dev_id] = qca_ssdk_phy_type_port_bmp_get(dev_id, MALIBU_PHY_CHIP); - - *status = 0x0; - for (port_id = 0; port_id < pdev->nr_ports; port_id++) - { - if (port_id >= SW_MAX_NR_PORT) - break; - /* for those ports without PHY device supposed always link up */ - if (A_FALSE == _dess_port_phy_connected(dev_id, port_id)) - { - *status |= (0x1 << port_id); - } - else - { - if(port_bmp[dev_id] & (0x1 << port_id)) - { - SW_RTN_ON_NULL (phy_drv = hsl_phy_api_ops_get (dev_id, port_id)); - if (NULL == phy_drv->phy_link_status_get) - return SW_NOT_SUPPORTED; - rv = hsl_port_prop_get_phyid(dev_id, port_id, &phy_id); - SW_RTN_ON_ERROR(rv); - - if (A_TRUE == phy_drv->phy_link_status_get (dev_id, phy_id)) - { - *status |= (0x1 << port_id); - } - else - { - *status &= ~(0x1 << port_id); - } - } - } - } - return SW_OK; -} - -static sw_error_t -_dess_port_mac_loopback_set (a_uint32_t dev_id, fal_port_t port_id, - a_bool_t enable) -{ - sw_error_t rv = SW_OK; - a_uint32_t val = 0; - - HSL_DEV_ID_CHECK (dev_id); - - if (A_TRUE != hsl_port_prop_check (dev_id, port_id, HSL_PP_INCL_CPU)) - { - return SW_BAD_PARAM; - } - - if (A_TRUE == enable) - { - val = 1; - } - else if (A_FALSE == enable) - { - val = 0; - } - else - { - return SW_BAD_PARAM; - } - - HSL_REG_FIELD_SET (rv, dev_id, PORT_HDR_CTL, port_id, LOOPBACK_EN, - (a_uint8_t *) (&val), sizeof (a_uint32_t)); - return rv; -} - -static sw_error_t -_dess_port_mac_loopback_get (a_uint32_t dev_id, fal_port_t port_id, - a_bool_t * enable) -{ - sw_error_t rv; - a_uint32_t val = 0; - - HSL_DEV_ID_CHECK (dev_id); - - if (A_TRUE != hsl_port_prop_check (dev_id, port_id, HSL_PP_INCL_CPU)) - { - return SW_BAD_PARAM; - } - - HSL_REG_FIELD_GET (rv, dev_id, PORT_HDR_CTL, port_id, LOOPBACK_EN, - (a_uint8_t *) (&val), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR (rv); - - if (0 == val) - { - *enable = A_FALSE; - } - else - { - *enable = A_TRUE; - } - - return SW_OK; -} - - -static sw_error_t -_dess_port_congestion_drop_set (a_uint32_t dev_id, fal_port_t port_id, - a_uint32_t queue_id, a_bool_t enable) -{ - sw_error_t rv = SW_OK; - a_uint32_t val = 0, offset = 0, field = 0; - - HSL_DEV_ID_CHECK (dev_id); - - if (A_TRUE != hsl_port_prop_check (dev_id, port_id, HSL_PP_INCL_CPU)) - { - return SW_BAD_PARAM; - } - - if (queue_id >= port_queue[port_id]) - { - return SW_BAD_PARAM; - } - - if (port_id != 0) - offset = port_id * 4 + 2; - offset += queue_id; - - if (A_TRUE == enable) - { - field = 1 << offset; - } - else if (A_FALSE == enable) - { - field = ~(1 << offset); - } - else - { - return SW_BAD_PARAM; - } - - - - HSL_REG_ENTRY_GET (rv, dev_id, FLOW_CONGE_DROP_CTRL0, 0, - (a_uint8_t *) (&val), sizeof (a_uint32_t)); - if (A_TRUE == enable) - { - val = val | field; - } - else - { - val = val & field; - } - - HSL_REG_ENTRY_SET (rv, dev_id, FLOW_CONGE_DROP_CTRL0, 0, - (a_uint8_t *) (&val), sizeof (a_uint32_t)); - return rv; -} - - -static sw_error_t -_dess_port_congestion_drop_get (a_uint32_t dev_id, fal_port_t port_id, - a_uint32_t queue_id, a_bool_t * enable) -{ - sw_error_t rv = SW_OK; - a_uint32_t val, offset = 0; - - HSL_DEV_ID_CHECK (dev_id); - - if (A_TRUE != hsl_port_prop_check (dev_id, port_id, HSL_PP_INCL_CPU)) - { - return SW_BAD_PARAM; - } - - if (queue_id >= port_queue[port_id]) - { - return SW_BAD_PARAM; - } - - if (port_id != 0) - offset = port_id * 4 + 2; - offset += queue_id; - - HSL_REG_ENTRY_GET (rv, dev_id, FLOW_CONGE_DROP_CTRL0, 0, - (a_uint8_t *) (&val), sizeof (a_uint32_t)); - val = (val >> offset) & 0x1; - if (val == 0) - { - *enable = A_FALSE; - } - else if (val == 1) - { - *enable = A_TRUE; - } - return rv; -} - -static sw_error_t -_dess_ring_flow_ctrl_thres_set (a_uint32_t dev_id, a_uint32_t ring_id, - a_uint8_t on_thres, a_uint8_t off_thres) -{ - sw_error_t rv; - a_uint32_t val = 0; - - HSL_DEV_ID_CHECK (dev_id); - - if (ring_id >= DMA_MAX_VIRT_RING) - { - return SW_BAD_PARAM; - } - - if (on_thres > off_thres || on_thres == 0) - { - return SW_BAD_PARAM; - } - - SW_SET_REG_BY_FIELD (RING_FLOW_CTRL_THRES, XON, on_thres, val); - SW_SET_REG_BY_FIELD (RING_FLOW_CTRL_THRES, XOFF, off_thres, val); - HSL_REG_ENTRY_SET (rv, dev_id, RING_FLOW_CTRL_THRES, ring_id, - (a_uint8_t *) (&val), sizeof (a_uint32_t)); - - - return rv; -} - - -static sw_error_t -_dess_ring_flow_ctrl_thres_get (a_uint32_t dev_id, a_uint32_t ring_id, - a_uint8_t * on_thres, a_uint8_t * off_thres) -{ - - sw_error_t rv; - a_uint32_t val = 0; - a_uint8_t hthres, lthres; - - HSL_DEV_ID_CHECK (dev_id); - - if (ring_id >= DMA_MAX_VIRT_RING) - { - return SW_BAD_PARAM; - } - - HSL_REG_ENTRY_GET (rv, dev_id, RING_FLOW_CTRL_THRES, ring_id, - (a_uint8_t *) (&val), sizeof (a_uint32_t)); - - SW_GET_FIELD_BY_REG (RING_FLOW_CTRL_THRES, XON, hthres, val); - SW_GET_FIELD_BY_REG (RING_FLOW_CTRL_THRES, XOFF, lthres, val); - - *on_thres = hthres; - *off_thres = lthres; - - return rv; -} - -static sw_error_t -_dess_port_8023az_set (a_uint32_t dev_id, fal_port_t port_id, a_bool_t enable) -{ - sw_error_t rv; - a_uint32_t phy_id = 0; - hsl_phy_ops_t *phy_drv; - - HSL_DEV_ID_CHECK (dev_id); - if (A_TRUE != hsl_port_prop_check (dev_id, port_id, HSL_PP_PHY)) - { - return SW_BAD_PARAM; - } - - SW_RTN_ON_NULL (phy_drv = hsl_phy_api_ops_get (dev_id, port_id)); - if (NULL == phy_drv->phy_8023az_set) - return SW_NOT_SUPPORTED; - - rv = hsl_port_prop_get_phyid (dev_id, port_id, &phy_id); - SW_RTN_ON_ERROR (rv); - - rv = phy_drv->phy_8023az_set (dev_id, phy_id, enable); - - return rv; -} - -static sw_error_t -_dess_port_8023az_get (a_uint32_t dev_id, fal_port_t port_id, - a_bool_t * enable) -{ - sw_error_t rv; - a_uint32_t phy_id = 0; - hsl_phy_ops_t *phy_drv; - - HSL_DEV_ID_CHECK (dev_id); - - if (A_TRUE != hsl_port_prop_check (dev_id, port_id, HSL_PP_PHY)) - { - return SW_BAD_PARAM; - } - - SW_RTN_ON_NULL (phy_drv = hsl_phy_api_ops_get (dev_id, port_id)); - if (NULL == phy_drv->phy_8023az_get) - return SW_NOT_SUPPORTED; - - rv = hsl_port_prop_get_phyid (dev_id, port_id, &phy_id); - SW_RTN_ON_ERROR (rv); - - rv = phy_drv->phy_8023az_get (dev_id, phy_id, enable); - - return rv; -} - -static sw_error_t -_dess_port_mdix_set (a_uint32_t dev_id, fal_port_t port_id, - fal_port_mdix_mode_t mode) -{ - sw_error_t rv; - a_uint32_t phy_id = 0; - hsl_phy_ops_t *phy_drv; - - HSL_DEV_ID_CHECK (dev_id); - if (A_TRUE != hsl_port_prop_check (dev_id, port_id, HSL_PP_PHY)) - { - return SW_BAD_PARAM; - } - - SW_RTN_ON_NULL (phy_drv = hsl_phy_api_ops_get (dev_id, port_id)); - if (NULL == phy_drv->phy_mdix_set) - return SW_NOT_SUPPORTED; - - rv = hsl_port_prop_get_phyid (dev_id, port_id, &phy_id); - SW_RTN_ON_ERROR (rv); - - rv = phy_drv->phy_mdix_set (dev_id, phy_id, mode); - - return rv; -} - -static sw_error_t -_dess_port_mdix_get (a_uint32_t dev_id, fal_port_t port_id, - fal_port_mdix_mode_t * mode) -{ - sw_error_t rv; - a_uint32_t phy_id = 0; - hsl_phy_ops_t *phy_drv; - - HSL_DEV_ID_CHECK (dev_id); - - if (A_TRUE != hsl_port_prop_check (dev_id, port_id, HSL_PP_PHY)) - { - return SW_BAD_PARAM; - } - - SW_RTN_ON_NULL (phy_drv = hsl_phy_api_ops_get (dev_id, port_id)); - if (NULL == phy_drv->phy_mdix_get) - return SW_NOT_SUPPORTED; - - rv = hsl_port_prop_get_phyid (dev_id, port_id, &phy_id); - SW_RTN_ON_ERROR (rv); - - rv = phy_drv->phy_mdix_get (dev_id, phy_id, mode); - - return rv; -} - -static sw_error_t -_dess_port_mdix_status_get (a_uint32_t dev_id, fal_port_t port_id, - fal_port_mdix_status_t * mode) -{ - sw_error_t rv; - a_uint32_t phy_id = 0; - hsl_phy_ops_t *phy_drv; - - HSL_DEV_ID_CHECK (dev_id); - - if (A_TRUE != hsl_port_prop_check (dev_id, port_id, HSL_PP_PHY)) - { - return SW_BAD_PARAM; - } - - SW_RTN_ON_NULL (phy_drv = hsl_phy_api_ops_get (dev_id, port_id)); - if (NULL == phy_drv->phy_mdix_status_get) - return SW_NOT_SUPPORTED; - - rv = hsl_port_prop_get_phyid (dev_id, port_id, &phy_id); - SW_RTN_ON_ERROR (rv); - - rv = phy_drv->phy_mdix_status_get (dev_id, phy_id, mode); - - return rv; -} - -static sw_error_t -_dess_port_combo_prefer_medium_set (a_uint32_t dev_id, fal_port_t port_id, - fal_port_medium_t phy_medium) -{ - sw_error_t rv; - a_uint32_t phy_id = 0; - hsl_phy_ops_t *phy_drv; - - HSL_DEV_ID_CHECK (dev_id); - if (A_TRUE != hsl_port_prop_check (dev_id, port_id, HSL_PP_PHY)) - { - return SW_BAD_PARAM; - } - - SW_RTN_ON_NULL (phy_drv = hsl_phy_api_ops_get (dev_id, port_id)); - if (NULL == phy_drv->phy_combo_prefer_medium_set) - return SW_NOT_SUPPORTED; - - rv = hsl_port_prop_get_phyid (dev_id, port_id, &phy_id); - SW_RTN_ON_ERROR (rv); - - rv = phy_drv->phy_combo_prefer_medium_set (dev_id, phy_id, phy_medium); - - return rv; -} - -static sw_error_t -_dess_port_combo_prefer_medium_get (a_uint32_t dev_id, fal_port_t port_id, - fal_port_medium_t * phy_medium) -{ - sw_error_t rv; - a_uint32_t phy_id = 0; - hsl_phy_ops_t *phy_drv; - - HSL_DEV_ID_CHECK (dev_id); - if (A_TRUE != hsl_port_prop_check (dev_id, port_id, HSL_PP_PHY)) - { - return SW_BAD_PARAM; - } - - SW_RTN_ON_NULL (phy_drv = hsl_phy_api_ops_get (dev_id, port_id)); - if (NULL == phy_drv->phy_combo_prefer_medium_get) - return SW_NOT_SUPPORTED; - - rv = hsl_port_prop_get_phyid (dev_id, port_id, &phy_id); - SW_RTN_ON_ERROR (rv); - - rv = phy_drv->phy_combo_prefer_medium_get (dev_id, phy_id, phy_medium); - - return rv; -} - -static sw_error_t -_dess_port_combo_medium_status_get (a_uint32_t dev_id, fal_port_t port_id, - fal_port_medium_t * phy_medium) -{ - sw_error_t rv; - a_uint32_t phy_id = 0; - hsl_phy_ops_t *phy_drv; - - HSL_DEV_ID_CHECK (dev_id); - if (A_TRUE != hsl_port_prop_check (dev_id, port_id, HSL_PP_PHY)) - { - return SW_BAD_PARAM; - } - - SW_RTN_ON_NULL (phy_drv = hsl_phy_api_ops_get (dev_id, port_id)); - if (NULL == phy_drv->phy_combo_medium_status_get) - return SW_NOT_SUPPORTED; - - rv = hsl_port_prop_get_phyid (dev_id, port_id, &phy_id); - SW_RTN_ON_ERROR (rv); - - rv = phy_drv->phy_combo_medium_status_get (dev_id, phy_id, phy_medium); - - return rv; -} - -static sw_error_t -_dess_port_combo_fiber_mode_set (a_uint32_t dev_id, fal_port_t port_id, - fal_port_fiber_mode_t fiber_mode) -{ - sw_error_t rv; - a_uint32_t phy_id = 0; - hsl_phy_ops_t *phy_drv; - - HSL_DEV_ID_CHECK (dev_id); - if (A_TRUE != hsl_port_prop_check (dev_id, port_id, HSL_PP_PHY)) - { - return SW_BAD_PARAM; - } - - SW_RTN_ON_NULL (phy_drv = hsl_phy_api_ops_get (dev_id, port_id)); - if (NULL == phy_drv->phy_combo_fiber_mode_set) - return SW_NOT_SUPPORTED; - - rv = hsl_port_prop_get_phyid (dev_id, port_id, &phy_id); - SW_RTN_ON_ERROR (rv); - - rv = phy_drv->phy_combo_fiber_mode_set (dev_id, phy_id, fiber_mode); - - return rv; -} - -static sw_error_t -_dess_port_combo_fiber_mode_get (a_uint32_t dev_id, fal_port_t port_id, - fal_port_fiber_mode_t * fiber_mode) -{ - sw_error_t rv; - a_uint32_t phy_id = 0; - hsl_phy_ops_t *phy_drv; - - HSL_DEV_ID_CHECK (dev_id); - if (A_TRUE != hsl_port_prop_check (dev_id, port_id, HSL_PP_PHY)) - { - return SW_BAD_PARAM; - } - - SW_RTN_ON_NULL (phy_drv = hsl_phy_api_ops_get (dev_id, port_id)); - if (NULL == phy_drv->phy_combo_fiber_mode_get) - return SW_NOT_SUPPORTED; - - rv = hsl_port_prop_get_phyid (dev_id, port_id, &phy_id); - SW_RTN_ON_ERROR (rv); - - rv = phy_drv->phy_combo_fiber_mode_get (dev_id, phy_id, fiber_mode); - - return rv; -} - -static sw_error_t -_dess_port_local_loopback_set (a_uint32_t dev_id, fal_port_t port_id, - a_bool_t enable) -{ - sw_error_t rv; - a_uint32_t phy_id = 0; - hsl_phy_ops_t *phy_drv; - - HSL_DEV_ID_CHECK (dev_id); - if (A_TRUE != hsl_port_prop_check (dev_id, port_id, HSL_PP_PHY)) - { - return SW_BAD_PARAM; - } - - SW_RTN_ON_NULL (phy_drv = hsl_phy_api_ops_get (dev_id, port_id)); - if (NULL == phy_drv->phy_local_loopback_set) - return SW_NOT_SUPPORTED; - - rv = hsl_port_prop_get_phyid (dev_id, port_id, &phy_id); - SW_RTN_ON_ERROR (rv); - - rv = phy_drv->phy_local_loopback_set (dev_id, phy_id, enable); - - return rv; -} - -static sw_error_t -_dess_port_local_loopback_get (a_uint32_t dev_id, fal_port_t port_id, - a_bool_t * enable) -{ - sw_error_t rv; - a_uint32_t phy_id = 0; - hsl_phy_ops_t *phy_drv; - - HSL_DEV_ID_CHECK (dev_id); - - if (A_TRUE != hsl_port_prop_check (dev_id, port_id, HSL_PP_PHY)) - { - return SW_BAD_PARAM; - } - - SW_RTN_ON_NULL (phy_drv = hsl_phy_api_ops_get (dev_id, port_id)); - if (NULL == phy_drv->phy_local_loopback_get) - return SW_NOT_SUPPORTED; - - rv = hsl_port_prop_get_phyid (dev_id, port_id, &phy_id); - SW_RTN_ON_ERROR (rv); - - rv = phy_drv->phy_local_loopback_get (dev_id, phy_id, enable); - - return rv; -} - -static sw_error_t -_dess_port_remote_loopback_set (a_uint32_t dev_id, fal_port_t port_id, - a_bool_t enable) -{ - sw_error_t rv; - a_uint32_t phy_id = 0; - hsl_phy_ops_t *phy_drv; - - HSL_DEV_ID_CHECK (dev_id); - if (A_TRUE != hsl_port_prop_check (dev_id, port_id, HSL_PP_PHY)) - { - return SW_BAD_PARAM; - } - - SW_RTN_ON_NULL (phy_drv = hsl_phy_api_ops_get (dev_id, port_id)); - if (NULL == phy_drv->phy_remote_loopback_set) - return SW_NOT_SUPPORTED; - - rv = hsl_port_prop_get_phyid (dev_id, port_id, &phy_id); - SW_RTN_ON_ERROR (rv); - - rv = phy_drv->phy_remote_loopback_set (dev_id, phy_id, enable); - - return rv; -} - -static sw_error_t -_dess_port_remote_loopback_get (a_uint32_t dev_id, fal_port_t port_id, - a_bool_t * enable) -{ - sw_error_t rv; - a_uint32_t phy_id = 0; - hsl_phy_ops_t *phy_drv; - - HSL_DEV_ID_CHECK (dev_id); - - if (A_TRUE != hsl_port_prop_check (dev_id, port_id, HSL_PP_PHY)) - { - return SW_BAD_PARAM; - } - - SW_RTN_ON_NULL (phy_drv = hsl_phy_api_ops_get (dev_id, port_id)); - if (NULL == phy_drv->phy_remote_loopback_get) - return SW_NOT_SUPPORTED; - - rv = hsl_port_prop_get_phyid (dev_id, port_id, &phy_id); - SW_RTN_ON_ERROR (rv); - - rv = phy_drv->phy_remote_loopback_get (dev_id, phy_id, enable); - - return rv; -} - -static sw_error_t -_dess_port_reset (a_uint32_t dev_id, fal_port_t port_id) -{ - sw_error_t rv; - a_uint32_t phy_id = 0; - hsl_phy_ops_t *phy_drv; - - HSL_DEV_ID_CHECK (dev_id); - - if (A_TRUE != hsl_port_prop_check (dev_id, port_id, HSL_PP_PHY)) - { - return SW_BAD_PARAM; - } - - SW_RTN_ON_NULL (phy_drv = hsl_phy_api_ops_get (dev_id, port_id)); - if (NULL == phy_drv->phy_reset) - return SW_NOT_SUPPORTED; - - rv = hsl_port_prop_get_phyid (dev_id, port_id, &phy_id); - SW_RTN_ON_ERROR (rv); - - rv = phy_drv->phy_reset(dev_id, phy_id); - - return rv; -} - -static sw_error_t -_dess_port_power_off (a_uint32_t dev_id, fal_port_t port_id) -{ - sw_error_t rv; - a_uint32_t phy_id = 0; - hsl_phy_ops_t *phy_drv; - - HSL_DEV_ID_CHECK (dev_id); - - if (A_TRUE != hsl_port_prop_check (dev_id, port_id, HSL_PP_PHY)) - { - return SW_BAD_PARAM; - } - - SW_RTN_ON_NULL (phy_drv = hsl_phy_api_ops_get (dev_id, port_id)); - if (NULL == phy_drv->phy_power_off) - return SW_NOT_SUPPORTED; - - rv = hsl_port_prop_get_phyid (dev_id, port_id, &phy_id); - SW_RTN_ON_ERROR (rv); - - rv = phy_drv->phy_power_off(dev_id, phy_id); - - return rv; -} - -static sw_error_t -_dess_port_power_on (a_uint32_t dev_id, fal_port_t port_id) -{ - sw_error_t rv; - a_uint32_t phy_id = 0; - hsl_phy_ops_t *phy_drv; - - HSL_DEV_ID_CHECK (dev_id); - - if (A_TRUE != hsl_port_prop_check (dev_id, port_id, HSL_PP_PHY)) - { - return SW_BAD_PARAM; - } - - SW_RTN_ON_NULL (phy_drv = hsl_phy_api_ops_get (dev_id, port_id)); - if (NULL == phy_drv->phy_power_on) - return SW_NOT_SUPPORTED; - - rv = hsl_port_prop_get_phyid (dev_id, port_id, &phy_id); - SW_RTN_ON_ERROR (rv); - - rv = phy_drv->phy_power_on(dev_id, phy_id); - - return rv; -} - -static sw_error_t -_dess_port_wol_status_set (a_uint32_t dev_id, fal_port_t port_id, - a_bool_t enable) -{ - sw_error_t rv; - a_uint32_t phy_id = 0; - hsl_phy_ops_t *phy_drv; - - HSL_DEV_ID_CHECK (dev_id); - if (A_TRUE != hsl_port_prop_check (dev_id, port_id, HSL_PP_PHY)) - { - return SW_BAD_PARAM; - } - - SW_RTN_ON_NULL (phy_drv = hsl_phy_api_ops_get (dev_id, port_id)); - if (NULL == phy_drv->phy_wol_status_set) - return SW_NOT_SUPPORTED; - - rv = hsl_port_prop_get_phyid (dev_id, port_id, &phy_id); - SW_RTN_ON_ERROR (rv); - - rv = phy_drv->phy_wol_status_set (dev_id, phy_id, enable); - - return rv; -} - -static sw_error_t -_dess_port_wol_status_get (a_uint32_t dev_id, fal_port_t port_id, - a_bool_t * enable) -{ - sw_error_t rv; - a_uint32_t phy_id = 0; - hsl_phy_ops_t *phy_drv; - - HSL_DEV_ID_CHECK (dev_id); - - if (A_TRUE != hsl_port_prop_check (dev_id, port_id, HSL_PP_PHY)) - { - return SW_BAD_PARAM; - } - - SW_RTN_ON_NULL (phy_drv = hsl_phy_api_ops_get (dev_id, port_id)); - if (NULL == phy_drv->phy_wol_status_get) - return SW_NOT_SUPPORTED; - - rv = hsl_port_prop_get_phyid (dev_id, port_id, &phy_id); - SW_RTN_ON_ERROR (rv); - - rv = phy_drv->phy_wol_status_get (dev_id, phy_id, enable); - - return rv; -} - -static sw_error_t -_dess_port_phy_id_get (a_uint32_t dev_id, fal_port_t port_id, - a_uint16_t * org_id, a_uint16_t * rev_id) -{ - sw_error_t rv; - a_uint32_t phy_id = 0; - hsl_phy_ops_t *phy_drv; - a_uint32_t phy_data; - - HSL_DEV_ID_CHECK (dev_id); - - if (A_TRUE != hsl_port_prop_check (dev_id, port_id, HSL_PP_PHY)) - { - return SW_BAD_PARAM; - } - - SW_RTN_ON_NULL (phy_drv = hsl_phy_api_ops_get (dev_id, port_id)); - if (NULL == phy_drv->phy_id_get) - return SW_NOT_SUPPORTED; - - rv = hsl_port_prop_get_phyid (dev_id, port_id, &phy_id); - SW_RTN_ON_ERROR (rv); - - rv = phy_drv->phy_id_get (dev_id, phy_id, &phy_data); - SW_RTN_ON_ERROR (rv); - - *org_id = (phy_data >> 16) & 0xffff; - *rev_id = phy_data & 0xffff; - - return rv; -} - -static sw_error_t -_dess_port_magic_frame_mac_set (a_uint32_t dev_id, fal_port_t port_id, - fal_mac_addr_t * mac) -{ - sw_error_t rv; - a_uint32_t phy_id = 0; - hsl_phy_ops_t *phy_drv; - - HSL_DEV_ID_CHECK (dev_id); - - if (A_TRUE != hsl_port_prop_check (dev_id, port_id, HSL_PP_PHY)) - { - return SW_BAD_PARAM; - } - - SW_RTN_ON_NULL (phy_drv = hsl_phy_api_ops_get (dev_id, port_id)); - if (NULL == phy_drv->phy_magic_frame_mac_set) - return SW_NOT_SUPPORTED; - - rv = hsl_port_prop_get_phyid (dev_id, port_id, &phy_id); - SW_RTN_ON_ERROR (rv); - - rv = phy_drv->phy_magic_frame_mac_set (dev_id, phy_id,mac); - - return rv; -} - -static sw_error_t -_dess_port_magic_frame_mac_get (a_uint32_t dev_id, fal_port_t port_id, - fal_mac_addr_t * mac) -{ - sw_error_t rv; - a_uint32_t phy_id = 0; - hsl_phy_ops_t *phy_drv; - - HSL_DEV_ID_CHECK (dev_id); - - if (A_TRUE != hsl_port_prop_check (dev_id, port_id, HSL_PP_PHY)) - { - return SW_BAD_PARAM; - } - - SW_RTN_ON_NULL (phy_drv = hsl_phy_api_ops_get (dev_id, port_id)); - if (NULL == phy_drv->phy_magic_frame_mac_get) - return SW_NOT_SUPPORTED; - - rv = hsl_port_prop_get_phyid (dev_id, port_id, &phy_id); - SW_RTN_ON_ERROR (rv); - - rv = phy_drv->phy_magic_frame_mac_get (dev_id, phy_id,mac); - - return rv; -} - -static sw_error_t -_dess_port_interface_mode_set (a_uint32_t dev_id, fal_port_t port_id, - fal_port_interface_mode_t mode) -{ - sw_error_t rv; - a_uint32_t phy_id = 0; - hsl_phy_ops_t *phy_drv; - - HSL_DEV_ID_CHECK (dev_id); - - if (A_TRUE != hsl_port_prop_check (dev_id, port_id, HSL_PP_PHY)) - { - return SW_BAD_PARAM; - } - - SW_RTN_ON_NULL (phy_drv = hsl_phy_api_ops_get (dev_id, port_id)); - if (NULL == phy_drv->phy_interface_mode_set) - return SW_NOT_SUPPORTED; - - rv = hsl_port_prop_get_phyid (dev_id, port_id, &phy_id); - SW_RTN_ON_ERROR (rv); - - rv = phy_drv->phy_interface_mode_set (dev_id, phy_id,mode); - - return rv; -} - -static sw_error_t -_dess_port_interface_mode_get (a_uint32_t dev_id, fal_port_t port_id, - fal_port_interface_mode_t * mode) -{ - sw_error_t rv; - a_uint32_t phy_id = 0; - hsl_phy_ops_t *phy_drv; - - HSL_DEV_ID_CHECK (dev_id); - - if (A_TRUE != hsl_port_prop_check (dev_id, port_id, HSL_PP_PHY)) - { - return SW_BAD_PARAM; - } - - SW_RTN_ON_NULL (phy_drv = hsl_phy_api_ops_get (dev_id, port_id)); - if (NULL == phy_drv->phy_interface_mode_get) - return SW_NOT_SUPPORTED; - - rv = hsl_port_prop_get_phyid (dev_id, port_id, &phy_id); - SW_RTN_ON_ERROR (rv); - - rv = phy_drv->phy_interface_mode_get (dev_id, phy_id,mode); - - return rv; -} - -static sw_error_t -_dess_port_interface_mode_status_get (a_uint32_t dev_id, fal_port_t port_id, - fal_port_interface_mode_t * mode) -{ - sw_error_t rv; - a_uint32_t phy_id = 0; - hsl_phy_ops_t *phy_drv; - - HSL_DEV_ID_CHECK (dev_id); - - if (A_TRUE != hsl_port_prop_check (dev_id, port_id, HSL_PP_PHY)) - { - return SW_BAD_PARAM; - } - - SW_RTN_ON_NULL (phy_drv = hsl_phy_api_ops_get (dev_id, port_id)); - if (NULL == phy_drv->phy_interface_mode_status_get) - return SW_NOT_SUPPORTED; - - rv = hsl_port_prop_get_phyid (dev_id, port_id, &phy_id); - SW_RTN_ON_ERROR (rv); - - rv = phy_drv->phy_interface_mode_status_get (dev_id, phy_id,mode); - - return rv; -} - -static sw_error_t -_dess_port_counter_set (a_uint32_t dev_id, fal_port_t port_id, a_bool_t enable) -{ - sw_error_t rv; - a_uint32_t phy_id = 0; - hsl_phy_ops_t *phy_drv; - - HSL_DEV_ID_CHECK (dev_id); - if (A_TRUE != hsl_port_prop_check (dev_id, port_id, HSL_PP_PHY)) - { - return SW_BAD_PARAM; - } - - SW_RTN_ON_NULL (phy_drv = hsl_phy_api_ops_get (dev_id, port_id)); - if (NULL == phy_drv->phy_counter_set) - return SW_NOT_SUPPORTED; - - rv = hsl_port_prop_get_phyid (dev_id, port_id, &phy_id); - SW_RTN_ON_ERROR (rv); - - rv = phy_drv->phy_counter_set (dev_id, phy_id, enable); - - return rv; -} - -static sw_error_t -_dess_port_counter_get (a_uint32_t dev_id, fal_port_t port_id, - a_bool_t * enable) -{ - sw_error_t rv; - a_uint32_t phy_id = 0; - hsl_phy_ops_t *phy_drv; - - HSL_DEV_ID_CHECK (dev_id); - - if (A_TRUE != hsl_port_prop_check (dev_id, port_id, HSL_PP_PHY)) - { - return SW_BAD_PARAM; - } - - SW_RTN_ON_NULL (phy_drv = hsl_phy_api_ops_get (dev_id, port_id)); - if (NULL == phy_drv->phy_counter_get) - return SW_NOT_SUPPORTED; - - rv = hsl_port_prop_get_phyid (dev_id, port_id, &phy_id); - SW_RTN_ON_ERROR (rv); - - rv = phy_drv->phy_counter_get (dev_id, phy_id, enable); - - return rv; -} - -static sw_error_t -_dess_port_counter_show (a_uint32_t dev_id, fal_port_t port_id, - fal_port_counter_info_t * counter_info) -{ - sw_error_t rv; - a_uint32_t phy_id = 0; - hsl_phy_ops_t *phy_drv; - - HSL_DEV_ID_CHECK (dev_id); - - if (A_TRUE != hsl_port_prop_check (dev_id, port_id, HSL_PP_PHY)) - { - return SW_BAD_PARAM; - } - - SW_RTN_ON_NULL (phy_drv = hsl_phy_api_ops_get (dev_id, port_id)); - if (NULL == phy_drv->phy_counter_show) - return SW_NOT_SUPPORTED; - - rv = hsl_port_prop_get_phyid (dev_id, port_id, &phy_id); - SW_RTN_ON_ERROR (rv); - - rv = phy_drv->phy_counter_show (dev_id, phy_id,counter_info); - - return rv; -} - -/** - * @brief Set duplex mode on a particular port. - * @param[in] dev_id device id - * @param[in] port_id port id - * @param[in] duplex duplex mode - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -dess_port_duplex_set (a_uint32_t dev_id, fal_port_t port_id, - fal_port_duplex_t duplex) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _dess_port_duplex_set (dev_id, port_id, duplex); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Get duplex mode on a particular port. - * @param[in] dev_id device id - * @param[in] port_id port id - * @param[out] duplex duplex mode - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -dess_port_duplex_get (a_uint32_t dev_id, fal_port_t port_id, - fal_port_duplex_t * pduplex) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _dess_port_duplex_get (dev_id, port_id, pduplex); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Set speed on a particular port. - * @param[in] dev_id device id - * @param[in] port_id port id - * @param[in] speed port speed - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -dess_port_speed_set (a_uint32_t dev_id, fal_port_t port_id, - fal_port_speed_t speed) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _dess_port_speed_set (dev_id, port_id, speed); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Get speed on a particular port. - * @param[in] dev_id device id - * @param[in] port_id port id - * @param[out] speed port speed - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -dess_port_speed_get (a_uint32_t dev_id, fal_port_t port_id, - fal_port_speed_t * pspeed) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _dess_port_speed_get (dev_id, port_id, pspeed); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Get auto negotiation status on a particular port. - * @param[in] dev_id device id - * @param[in] port_id port id - * @param[out] status A_TRUE or A_FALSE - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -dess_port_autoneg_status_get (a_uint32_t dev_id, fal_port_t port_id, - a_bool_t * status) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _dess_port_autoneg_status_get (dev_id, port_id, status); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Enable auto negotiation status on a particular port. - * @param[in] dev_id device id - * @param[in] port_id port id - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -dess_port_autoneg_enable (a_uint32_t dev_id, fal_port_t port_id) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _dess_port_autoneg_enable (dev_id, port_id); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Restart auto negotiation procedule on a particular port. - * @param[in] dev_id device id - * @param[in] port_id port id - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -dess_port_autoneg_restart (a_uint32_t dev_id, fal_port_t port_id) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _dess_port_autoneg_restart (dev_id, port_id); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Set auto negotiation advtisement ability on a particular port. - * @details Comments: - * auto negotiation advtisement ability is defined by macro such as - * FAL_PHY_ADV_10T_HD, FAL_PHY_ADV_PAUSE... - * @param[in] dev_id device id - * @param[in] port_id port id - * @param[in] autoadv auto negotiation advtisement ability bit map - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -dess_port_autoneg_adv_set (a_uint32_t dev_id, fal_port_t port_id, - a_uint32_t autoadv) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _dess_port_autoneg_adv_set (dev_id, port_id, autoadv); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Get auto negotiation advtisement ability on a particular port. - * @param[in] dev_id device id - * @param[in] port_id port id - * @param[out] autoadv auto negotiation advtisement ability bit map - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -dess_port_autoneg_adv_get (a_uint32_t dev_id, fal_port_t port_id, - a_uint32_t * autoadv) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _dess_port_autoneg_adv_get (dev_id, port_id, autoadv); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Set flow control(rx/tx/bp) status on a particular port. - * @param[in] dev_id device id - * @param[in] port_id port id - * @param[in] enable A_TRUE or A_FALSE - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -dess_port_flowctrl_set (a_uint32_t dev_id, fal_port_t port_id, - a_bool_t enable) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _dess_port_flowctrl_set (dev_id, port_id, enable); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Set flow control(rx/tx/bp) threshold on a particular port. - * @param[in] dev_id device id - * @param[in] port_id port id - * @param[in] on on threshold - * @param[in] off off threshold - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -dess_port_flowctrl_thresh_set (a_uint32_t dev_id, fal_port_t port_id, - a_uint8_t on, a_uint8_t off) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _dess_port_flowctrl_thresh_set (dev_id, port_id, on, off); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Get flow control status on a particular port. - * @param[in] dev_id device id - * @param[in] port_id port id - * @param[out] enable A_TRUE or A_FALSE - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -dess_port_flowctrl_get (a_uint32_t dev_id, fal_port_t port_id, - a_bool_t * enable) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _dess_port_flowctrl_get (dev_id, port_id, enable); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Set flow control force mode on a particular port. - * @param[in] dev_id device id - * @param[in] port_id port id - * @param[out] enable A_TRUE or A_FALSE - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -dess_port_flowctrl_forcemode_set (a_uint32_t dev_id, fal_port_t port_id, - a_bool_t enable) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _dess_port_flowctrl_forcemode_set (dev_id, port_id, enable); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Get flow control force mode on a particular port. - * @param[in] dev_id device id - * @param[in] port_id port id - * @param[out] enable A_TRUE or A_FALSE - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -dess_port_flowctrl_forcemode_get (a_uint32_t dev_id, fal_port_t port_id, - a_bool_t * enable) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _dess_port_flowctrl_forcemode_get (dev_id, port_id, enable); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Set powersaving status on a particular port. - * @param[in] dev_id device id - * @param[in] port_id port id - * @param[out] enable A_TRUE or A_FALSE - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -dess_port_powersave_set (a_uint32_t dev_id, fal_port_t port_id, - a_bool_t enable) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _dess_port_powersave_set (dev_id, port_id, enable); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Get powersaving status on a particular port. - * @param[in] dev_id device id - * @param[in] port_id port id - * @param[out] enable A_TRUE or A_FALSE - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -dess_port_powersave_get (a_uint32_t dev_id, fal_port_t port_id, - a_bool_t * enable) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _dess_port_powersave_get (dev_id, port_id, enable); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Set hibernate status on a particular port. - * @param[in] dev_id device id - * @param[in] port_id port id - * @param[out] enable A_TRUE or A_FALSE - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -dess_port_hibernate_set (a_uint32_t dev_id, fal_port_t port_id, - a_bool_t enable) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _dess_port_hibernate_set (dev_id, port_id, enable); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Get hibernate status on a particular port. - * @param[in] dev_id device id - * @param[in] port_id port id - * @param[out] enable A_TRUE or A_FALSE - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -dess_port_hibernate_get (a_uint32_t dev_id, fal_port_t port_id, - a_bool_t * enable) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _dess_port_hibernate_get (dev_id, port_id, enable); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Run cable diagnostic test on a particular port. - * @param[in] dev_id device id - * @param[in] port_id port id - * @param[in] mdi_pair mdi pair id - * @param[out] cable_status cable status - * @param[out] cable_len cable len - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -dess_port_cdt (a_uint32_t dev_id, fal_port_t port_id, a_uint32_t mdi_pair, - fal_cable_status_t * cable_status, a_uint32_t * cable_len) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _dess_port_cdt (dev_id, port_id, mdi_pair, cable_status, cable_len); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Set status of Atheros header packets parsed on a particular port. - * @param[in] dev_id device id - * @param[in] port_id port id - * @param[in] enable A_TRUE or A_FALSE - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -dess_port_rxhdr_mode_set (a_uint32_t dev_id, fal_port_t port_id, - fal_port_header_mode_t mode) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _dess_port_rxhdr_mode_set (dev_id, port_id, mode); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Get status of Atheros header packets parsed on a particular port. - * @param[in] dev_id device id - * @param[in] port_id port id - * @param[out] enable A_TRUE or A_FALSE - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -dess_port_rxhdr_mode_get (a_uint32_t dev_id, fal_port_t port_id, - fal_port_header_mode_t * mode) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _dess_port_rxhdr_mode_get (dev_id, port_id, mode); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Set status of Atheros header packets parsed on a particular port. - * @param[in] dev_id device id - * @param[in] port_id port id - * @param[in] enable A_TRUE or A_FALSE - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -dess_port_txhdr_mode_set (a_uint32_t dev_id, fal_port_t port_id, - fal_port_header_mode_t mode) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _dess_port_txhdr_mode_set (dev_id, port_id, mode); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Get status of Atheros header packets parsed on a particular port. - * @param[in] dev_id device id - * @param[in] port_id port id - * @param[out] enable A_TRUE or A_FALSE - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -dess_port_txhdr_mode_get (a_uint32_t dev_id, fal_port_t port_id, - fal_port_header_mode_t * mode) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _dess_port_txhdr_mode_get (dev_id, port_id, mode); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Set status of Atheros header type value on a particular device. - * @param[in] dev_id device id - * @param[in] enable A_TRUE or A_FALSE - * @param[in] type header type value - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -dess_header_type_set (a_uint32_t dev_id, a_bool_t enable, a_uint32_t type) -{ - sw_error_t rv; - HSL_API_LOCK; - rv = _dess_header_type_set (dev_id, enable, type); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Get status of Atheros header type value on a particular device. - * @param[in] dev_id device id - * @param[out] enable A_TRUE or A_FALSE - * @param[out] type header type value - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -dess_header_type_get (a_uint32_t dev_id, a_bool_t * enable, a_uint32_t * type) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _dess_header_type_get (dev_id, enable, type); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Set status of txmac on a particular port. - * @param[in] dev_id device id - * @param[in] port_id port id - * @param[in] enable A_TRUE or A_FALSE - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -dess_port_txmac_status_set (a_uint32_t dev_id, fal_port_t port_id, - a_bool_t enable) -{ - sw_error_t rv; - HSL_API_LOCK; - rv = _dess_port_txmac_status_set (dev_id, port_id, enable); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Get status of txmac on a particular port. - * @param[in] dev_id device id - * @param[in] port_id port id - * @param[out] enable A_TRUE or A_FALSE - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -dess_port_txmac_status_get (a_uint32_t dev_id, fal_port_t port_id, - a_bool_t * enable) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _dess_port_txmac_status_get (dev_id, port_id, enable); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Set status of rxmac on a particular port. - * @param[in] dev_id device id - * @param[in] port_id port id - * @param[in] enable A_TRUE or A_FALSE - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -dess_port_rxmac_status_set (a_uint32_t dev_id, fal_port_t port_id, - a_bool_t enable) -{ - sw_error_t rv; - HSL_API_LOCK; - rv = _dess_port_rxmac_status_set (dev_id, port_id, enable); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Get status of rxmac on a particular port. - * @param[in] dev_id device id - * @param[in] port_id port id - * @param[out] enable A_TRUE or A_FALSE - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -dess_port_rxmac_status_get (a_uint32_t dev_id, fal_port_t port_id, - a_bool_t * enable) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _dess_port_rxmac_status_get (dev_id, port_id, enable); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Set status of tx flow control on a particular port. - * @param[in] dev_id device id - * @param[in] port_id port id - * @param[in] enable A_TRUE or A_FALSE - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -dess_port_txfc_status_set (a_uint32_t dev_id, fal_port_t port_id, - a_bool_t enable) -{ - sw_error_t rv; - HSL_API_LOCK; - rv = _dess_port_txfc_status_set (dev_id, port_id, enable); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Get status of tx flow control on a particular port. - * @param[in] dev_id device id - * @param[in] port_id port id - * @param[out] enable A_TRUE or A_FALSE - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -dess_port_txfc_status_get (a_uint32_t dev_id, fal_port_t port_id, - a_bool_t * enable) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _dess_port_txfc_status_get (dev_id, port_id, enable); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Set status of rx flow control on a particular port. - * @param[in] dev_id device id - * @param[in] port_id port id - * @param[in] enable A_TRUE or A_FALSE - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -dess_port_rxfc_status_set (a_uint32_t dev_id, fal_port_t port_id, - a_bool_t enable) -{ - sw_error_t rv; - HSL_API_LOCK; - rv = _dess_port_rxfc_status_set (dev_id, port_id, enable); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Set status of rx flow control on a particular port. - * @param[in] dev_id device id - * @param[in] port_id port id - * @param[out] enable A_TRUE or A_FALSE - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -dess_port_rxfc_status_get (a_uint32_t dev_id, fal_port_t port_id, - a_bool_t * enable) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _dess_port_rxfc_status_get (dev_id, port_id, enable); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Set status of back pressure on a particular port. - * @param[in] dev_id device id - * @param[in] port_id port id - * @param[in] enable A_TRUE or A_FALSE - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -dess_port_bp_status_set (a_uint32_t dev_id, fal_port_t port_id, - a_bool_t enable) -{ - sw_error_t rv; - HSL_API_LOCK; - rv = _dess_port_bp_status_set (dev_id, port_id, enable); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Set status of back pressure on a particular port. - * @param[in] dev_id device id - * @param[in] port_id port id - * @param[out] enable A_TRUE or A_FALSE - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -dess_port_bp_status_get (a_uint32_t dev_id, fal_port_t port_id, - a_bool_t * enable) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _dess_port_bp_status_get (dev_id, port_id, enable); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Set link force mode on a particular port. - * @param[in] dev_id device id - * @param[in] port_id port id - * @param[in] enable A_TRUE or A_FALSE - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -dess_port_link_forcemode_set (a_uint32_t dev_id, fal_port_t port_id, - a_bool_t enable) -{ - sw_error_t rv; - HSL_API_LOCK; - rv = _dess_port_link_forcemode_set (dev_id, port_id, enable); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Get link force mode on a particular port. - * @param[in] dev_id device id - * @param[in] port_id port id - * @param[out] enable A_TRUE or A_FALSE - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -dess_port_link_forcemode_get (a_uint32_t dev_id, fal_port_t port_id, - a_bool_t * enable) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _dess_port_link_forcemode_get (dev_id, port_id, enable); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Get link status on particular port. - * @param[in] dev_id device id - * @param[in] port_id port id - * @param[out] status link status up (A_TRUE) or down (A_FALSE) - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -dess_port_link_status_get (a_uint32_t dev_id, fal_port_t port_id, - a_bool_t * status) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _dess_port_link_status_get (dev_id, port_id, status); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Get link status on all ports. - * @param[in] dev_id device id - * @param[out] status link status bitmap and bit 0 for port 0, bi 1 for port 1, ..., etc. - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -dess_ports_link_status_get(a_uint32_t dev_id, a_uint32_t * status) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _dess_ports_link_status_get(dev_id, status); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Set mac loop back on a particular port. - * @param[in] dev_id device id - * @param[in] port_id port id - * @param[in] enable A_TRUE or A_FALSE - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -dess_port_mac_loopback_set (a_uint32_t dev_id, fal_port_t port_id, - a_bool_t enable) -{ - sw_error_t rv; - HSL_API_LOCK; - rv = _dess_port_mac_loopback_set (dev_id, port_id, enable); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Get mac loop back on a particular port. - * @param[in] dev_id device id - * @param[in] port_id port id - * @param[out] enable A_TRUE or A_FALSE - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -dess_port_mac_loopback_get (a_uint32_t dev_id, fal_port_t port_id, - a_bool_t * enable) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _dess_port_mac_loopback_get (dev_id, port_id, enable); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Set flow congestion drop on a particular port queue. - * @param[in] dev_id device id - * @param[in] port_id port id - * @param[in] queue_id queue id - * @param[in] enable A_TRUE or A_FALSE - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -dess_port_congestion_drop_set (a_uint32_t dev_id, fal_port_t port_id, - a_uint32_t queue_id, a_bool_t enable) -{ - sw_error_t rv; - HSL_API_LOCK; - rv = _dess_port_congestion_drop_set (dev_id, port_id, queue_id, enable); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Set flow congestion drop on a particular port. - * @param[in] dev_id device id - * @param[in] port_id port id - * @param[in] queue_id queue id - * @param[out] enable A_TRUE or A_FALSE - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -dess_port_congestion_drop_get (a_uint32_t dev_id, fal_port_t port_id, - a_uint32_t queue_id, a_bool_t * enable) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _dess_port_congestion_drop_get (dev_id, port_id, queue_id, enable); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Set flow ctrl thres on a particular DMA ring. - * @param[in] dev_id device id - * @param[in] ring_id ring id - * @param[in] on_thres on_thres - * @param[in] off_thres off_thres - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -dess_ring_flow_ctrl_thres_set (a_uint32_t dev_id, a_uint32_t ring_id, - a_uint8_t on_thres, a_uint8_t off_thres) -{ - sw_error_t rv; - HSL_API_LOCK; - rv = _dess_ring_flow_ctrl_thres_set (dev_id, ring_id, on_thres, off_thres); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Set flow ctrl thres on a particular DMA ring. - * @param[in] dev_id device id - * @param[in] ring_id ring id - * @param[out] on_thres on_thres - * @param[out] off_thres off_thres - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -dess_ring_flow_ctrl_thres_get (a_uint32_t dev_id, a_uint32_t ring_id, - a_uint8_t * on_thres, a_uint8_t * off_thres) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _dess_ring_flow_ctrl_thres_get (dev_id, ring_id, on_thres, off_thres); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Set 802.3az status on a particular port. - * @param[in] dev_id device id - * @param[in] port_id port id - * @param[out] enable A_TRUE or A_FALSE - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -dess_port_8023az_set (a_uint32_t dev_id, fal_port_t port_id, a_bool_t enable) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _dess_port_8023az_set (dev_id, port_id, enable); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Get 8023az status on a particular port. - * @param[in] dev_id device id - * @param[in] port_id port id - * @param[out] enable A_TRUE or A_FALSE - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -dess_port_8023az_get (a_uint32_t dev_id, fal_port_t port_id, - a_bool_t * enable) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _dess_port_8023az_get (dev_id, port_id, enable); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Set mdix on a particular port. - * @param[in] dev_id device id - * @param[in] port_id port id - * @param[out] mode - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -dess_port_mdix_set (a_uint32_t dev_id, a_uint32_t phy_id, - fal_port_mdix_mode_t mode) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _dess_port_mdix_set (dev_id, phy_id, mode); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Get mdix configuration on a particular port. - * @param[in] dev_id device id - * @param[in] port_id port id - * @param[out] mode - * @return SW_OK or error code - */ - -HSL_LOCAL sw_error_t -dess_port_mdix_get (a_uint32_t dev_id, fal_port_t port_id, - fal_port_mdix_mode_t * mode) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _dess_port_mdix_get (dev_id, port_id, mode); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Get mdix status on a particular port. - * @param[in] dev_id device id - * @param[in] port_id port id - * @param[out] mode - * @return SW_OK or error code - */ - -HSL_LOCAL sw_error_t -dess_port_mdix_status_get (a_uint32_t dev_id, fal_port_t port_id, - fal_port_mdix_status_t * mode) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _dess_port_mdix_status_get (dev_id, port_id, mode); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Set combo prefer medium on a particular port. - * @param[in] dev_id device id - * @param[in] port_id port id - * @param[out] phy_medium [fiber or copper] - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -dess_port_combo_prefer_medium_set (a_uint32_t dev_id, a_uint32_t phy_id, - fal_port_medium_t phy_medium) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _dess_port_combo_prefer_medium_set (dev_id, phy_id, phy_medium); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Get combo prefer medium on a particular port. - * @param[in] dev_id device id - * @param[in] port_id port id - * @param[out] phy_medium [fiber or copper] - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -dess_port_combo_prefer_medium_get (a_uint32_t dev_id, a_uint32_t phy_id, - fal_port_medium_t * phy_medium) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _dess_port_combo_prefer_medium_get (dev_id, phy_id, phy_medium); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Get current combo medium status on a particular port. - * @param[in] dev_id device id - * @param[in] port_id port id - * @param[out] phy_medium [fiber or copper] - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -dess_port_combo_medium_status_get (a_uint32_t dev_id, a_uint32_t phy_id, - fal_port_medium_t * phy_medium) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _dess_port_combo_medium_status_get (dev_id, phy_id, phy_medium); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Set fiber mode on a particular port. - * @param[in] dev_id device id - * @param[in] port_id port id - * @param[out] fiber mode [1000bx or 100fx] - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -dess_port_combo_fiber_mode_set (a_uint32_t dev_id, a_uint32_t phy_id, - fal_port_fiber_mode_t fiber_mode) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _dess_port_combo_fiber_mode_set (dev_id, phy_id, fiber_mode); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Get fiber mode on a particular port. - * @param[in] dev_id device id - * @param[in] port_id port id - * @param[out] fiber mode [1000bx or 100fx] - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -dess_port_combo_fiber_mode_get (a_uint32_t dev_id, a_uint32_t phy_id, - fal_port_fiber_mode_t * fiber_mode) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _dess_port_combo_fiber_mode_get (dev_id, phy_id, fiber_mode); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Set phy local loop back on a particular port. - * @param[in] dev_id device id - * @param[in] port_id port id - * @param[in] enable A_TRUE or A_FALSE - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -dess_port_local_loopback_set (a_uint32_t dev_id, fal_port_t port_id, - a_bool_t enable) -{ - sw_error_t rv; - HSL_API_LOCK; - rv = _dess_port_local_loopback_set (dev_id, port_id, enable); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Get phy local loop back on a particular port. - * @param[in] dev_id device id - * @param[in] port_id port id - * @param[out] enable A_TRUE or A_FALSE - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -dess_port_local_loopback_get (a_uint32_t dev_id, fal_port_t port_id, - a_bool_t * enable) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _dess_port_local_loopback_get (dev_id, port_id, enable); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Set phy remote loop back on a particular port. - * @param[in] dev_id device id - * @param[in] port_id port id - * @param[in] enable A_TRUE or A_FALSE - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -dess_port_remote_loopback_set (a_uint32_t dev_id, fal_port_t port_id, - a_bool_t enable) -{ - sw_error_t rv; - HSL_API_LOCK; - rv = _dess_port_remote_loopback_set (dev_id, port_id, enable); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Get phy remote loop back on a particular port. - * @param[in] dev_id device id - * @param[in] port_id port id - * @param[out] enable A_TRUE or A_FALSE - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -dess_port_remote_loopback_get (a_uint32_t dev_id, fal_port_t port_id, - a_bool_t * enable) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _dess_port_remote_loopback_get (dev_id, port_id, enable); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief software reset on a particular port. - * @param[in] dev_id device id - * @param[in] port_id port id - * @param[in] - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -dess_port_reset (a_uint32_t dev_id, fal_port_t port_id) -{ - sw_error_t rv; - HSL_API_LOCK; - rv = _dess_port_reset (dev_id, port_id); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief phy power off on a particular port. - * @param[in] dev_id device id - * @param[in] port_id port id - * @param[in] - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -dess_port_power_off (a_uint32_t dev_id, fal_port_t port_id) -{ - sw_error_t rv; - HSL_API_LOCK; - rv = _dess_port_power_off (dev_id, port_id); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief phy power on on a particular port. - * @param[in] dev_id device id - * @param[in] port_id port id - * @param[in] - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -dess_port_power_on (a_uint32_t dev_id, fal_port_t port_id) -{ - sw_error_t rv; - HSL_API_LOCK; - rv = _dess_port_power_on (dev_id, port_id); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Set phy wol enable on a particular port. - * @param[in] dev_id device id - * @param[in] port_id port id - * @param[in] enable A_TRUE or A_FALSE - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -dess_port_wol_status_set (a_uint32_t dev_id, fal_port_t port_id, - a_bool_t enable) -{ - sw_error_t rv; - HSL_API_LOCK; - rv = _dess_port_wol_status_set (dev_id, port_id, enable); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Get phy wol status on a particular port. - * @param[in] dev_id device id - * @param[in] port_id port id - * @param[out] enable A_TRUE or A_FALSE - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -dess_port_wol_status_get (a_uint32_t dev_id, fal_port_t port_id, - a_bool_t * enable) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _dess_port_wol_status_get (dev_id, port_id, enable); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Get phy id on a particular port. - * @param[in] dev_id device id - * @param[in] port_id port id - * @param[out] org_id and rev_id - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -dess_port_phy_id_get (a_uint32_t dev_id, fal_port_t port_id, - a_uint16_t * org_id, a_uint16_t * rev_id) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _dess_port_phy_id_get (dev_id, port_id, org_id,rev_id); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Set phy magic frame mac on a particular port. - * @param[in] dev_id device id - * @param[in] port_id port id - * @param[in] mac address - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -dess_port_magic_frame_mac_set (a_uint32_t dev_id, fal_port_t port_id, - fal_mac_addr_t * mac) -{ - sw_error_t rv; - HSL_API_LOCK; - rv = _dess_port_magic_frame_mac_set (dev_id, port_id, mac); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Get phy magic frame mac on a particular port. - * @param[in] dev_id device id - * @param[in] port_id port id - * @param[out] mac address - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -dess_port_magic_frame_mac_get (a_uint32_t dev_id, fal_port_t port_id, - fal_mac_addr_t * mac) -{ - sw_error_t rv; - HSL_API_LOCK; - rv = _dess_port_magic_frame_mac_get (dev_id, port_id, mac); - HSL_API_UNLOCK; - return rv; -} - - -/** - * @brief Set phy interface mode. - * @param[in] dev_id device id - * @param[in] port_id port id - * @param[in] interface mode.. - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -dess_port_interface_mode_set (a_uint32_t dev_id, fal_port_t port_id, - fal_port_interface_mode_t mode) -{ - sw_error_t rv; - HSL_API_LOCK; - rv = _dess_port_interface_mode_set (dev_id, port_id, mode); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Set phy interface mode. - * @param[in] dev_id device id - * @param[in] port_id port id - * @param[out] interface mode.. - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -dess_port_interface_mode_get (a_uint32_t dev_id, fal_port_t port_id, - fal_port_interface_mode_t * mode) -{ - sw_error_t rv; - HSL_API_LOCK; - rv = _dess_port_interface_mode_get (dev_id, port_id, mode); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Set phy interface mode status. - * @param[in] dev_id device id - * @param[in] port_id port id - * @param[out] interface mode.. - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -dess_port_interface_mode_status_get (a_uint32_t dev_id, fal_port_t port_id, - fal_port_interface_mode_t * mode) -{ - sw_error_t rv; - HSL_API_LOCK; - rv = _dess_port_interface_mode_status_get (dev_id, port_id, mode); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Set counter status on a particular port. - * @param[in] dev_id device id - * @param[in] port_id port id - * @param[out] enable A_TRUE or A_FALSE - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -dess_port_counter_set (a_uint32_t dev_id, fal_port_t port_id, a_bool_t enable) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _dess_port_counter_set (dev_id, port_id, enable); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Get counter status on a particular port. - * @param[in] dev_id device id - * @param[in] port_id port id - * @param[out] enable A_TRUE or A_FALSE - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -dess_port_counter_get (a_uint32_t dev_id, fal_port_t port_id, - a_bool_t * enable) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _dess_port_counter_get (dev_id, port_id, enable); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Get counter statistics on a particular port. - * @param[in] dev_id device id - * @param[in] port_id port id - * @param[out] frame counter statistics - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -dess_port_counter_show(a_uint32_t dev_id, fal_port_t port_id, - fal_port_counter_info_t * counter_info) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _dess_port_counter_show (dev_id, port_id, counter_info); - HSL_API_UNLOCK; - return rv; -} - -sw_error_t -dess_port_ctrl_init (a_uint32_t dev_id) -{ - HSL_DEV_ID_CHECK (dev_id); - -#ifndef HSL_STANDALONG - { - hsl_api_t *p_api; - - SW_RTN_ON_NULL (p_api = hsl_api_ptr_get (dev_id)); - - p_api->port_duplex_get = dess_port_duplex_get; - p_api->port_duplex_set = dess_port_duplex_set; - p_api->port_speed_get = dess_port_speed_get; - p_api->port_speed_set = dess_port_speed_set; - p_api->port_autoneg_status_get = dess_port_autoneg_status_get; - p_api->port_autoneg_enable = dess_port_autoneg_enable; - p_api->port_autoneg_restart = dess_port_autoneg_restart; - p_api->port_autoneg_adv_get = dess_port_autoneg_adv_get; - p_api->port_autoneg_adv_set = dess_port_autoneg_adv_set; - p_api->port_flowctrl_set = dess_port_flowctrl_set; - p_api->port_flowctrl_get = dess_port_flowctrl_get; - p_api->port_flowctrl_thresh_set = dess_port_flowctrl_thresh_set; - p_api->port_flowctrl_forcemode_set = dess_port_flowctrl_forcemode_set; - p_api->port_flowctrl_forcemode_get = dess_port_flowctrl_forcemode_get; - p_api->port_powersave_set = dess_port_powersave_set; - p_api->port_powersave_get = dess_port_powersave_get; - p_api->port_hibernate_set = dess_port_hibernate_set; - p_api->port_hibernate_get = dess_port_hibernate_get; - p_api->port_cdt = dess_port_cdt; - p_api->port_rxhdr_mode_set = dess_port_rxhdr_mode_set; - p_api->port_rxhdr_mode_get = dess_port_rxhdr_mode_get; - p_api->port_txhdr_mode_set = dess_port_txhdr_mode_set; - p_api->port_txhdr_mode_get = dess_port_txhdr_mode_get; - p_api->header_type_set = dess_header_type_set; - p_api->header_type_get = dess_header_type_get; - p_api->port_txmac_status_set = dess_port_txmac_status_set; - p_api->port_txmac_status_get = dess_port_txmac_status_get; - p_api->port_rxmac_status_set = dess_port_rxmac_status_set; - p_api->port_rxmac_status_get = dess_port_rxmac_status_get; - p_api->port_txfc_status_set = dess_port_txfc_status_set; - p_api->port_txfc_status_get = dess_port_txfc_status_get; - p_api->port_rxfc_status_set = dess_port_rxfc_status_set; - p_api->port_rxfc_status_get = dess_port_rxfc_status_get; - p_api->port_bp_status_set = dess_port_bp_status_set; - p_api->port_bp_status_get = dess_port_bp_status_get; - p_api->port_link_forcemode_set = dess_port_link_forcemode_set; - p_api->port_link_forcemode_get = dess_port_link_forcemode_get; - p_api->port_link_status_get = dess_port_link_status_get; - p_api->ports_link_status_get = dess_ports_link_status_get; - p_api->port_mac_loopback_set = dess_port_mac_loopback_set; - p_api->port_mac_loopback_get = dess_port_mac_loopback_get; - p_api->port_congestion_drop_set = dess_port_congestion_drop_set; - p_api->port_congestion_drop_get = dess_port_congestion_drop_get; - p_api->ring_flow_ctrl_thres_set = dess_ring_flow_ctrl_thres_set; - p_api->ring_flow_ctrl_thres_get = dess_ring_flow_ctrl_thres_get; - p_api->port_8023az_set = dess_port_8023az_set; - p_api->port_8023az_get = dess_port_8023az_get; - p_api->port_mdix_set = dess_port_mdix_set; - p_api->port_mdix_get = dess_port_mdix_get; - p_api->port_mdix_status_get = dess_port_mdix_status_get; - p_api->port_combo_prefer_medium_set = dess_port_combo_prefer_medium_set; - p_api->port_combo_prefer_medium_get = dess_port_combo_prefer_medium_get; - p_api->port_combo_medium_status_get = dess_port_combo_medium_status_get; - p_api->port_combo_fiber_mode_set = dess_port_combo_fiber_mode_set; - p_api->port_combo_fiber_mode_get = dess_port_combo_fiber_mode_get; - p_api->port_local_loopback_set = dess_port_local_loopback_set; - p_api->port_local_loopback_get = dess_port_local_loopback_get; - p_api->port_remote_loopback_set = dess_port_remote_loopback_set; - p_api->port_remote_loopback_get = dess_port_remote_loopback_get; - p_api->port_reset = dess_port_reset; - p_api->port_power_off = dess_port_power_off; - p_api->port_power_on = dess_port_power_on; - p_api->port_phy_id_get = dess_port_phy_id_get; - p_api->port_wol_status_set = dess_port_wol_status_set; - p_api->port_wol_status_get = dess_port_wol_status_get; - p_api->port_magic_frame_mac_set = dess_port_magic_frame_mac_set; - p_api->port_magic_frame_mac_get = dess_port_magic_frame_mac_get; - p_api->port_interface_mode_set = dess_port_interface_mode_set; - p_api->port_interface_mode_get = dess_port_interface_mode_get; - p_api->port_interface_mode_status_get = dess_port_interface_mode_status_get; - p_api->port_counter_set = dess_port_counter_set; - p_api->port_counter_get = dess_port_counter_get; - p_api->port_counter_show = dess_port_counter_show; - } -#endif - - return SW_OK; -} - -/** - * @} - */ diff --git a/feeds/ipq807x/qca-ssdk/src/src/hsl/dess/dess_portvlan.c b/feeds/ipq807x/qca-ssdk/src/src/hsl/dess/dess_portvlan.c deleted file mode 100755 index bab6228e8..000000000 --- a/feeds/ipq807x/qca-ssdk/src/src/hsl/dess/dess_portvlan.c +++ /dev/null @@ -1,2336 +0,0 @@ -/* - * Copyright (c) 2014, 2016, The Linux Foundation. All rights reserved. - * Permission to use, copy, modify, and/or distribute this software for - * any purpose with or without fee is hereby granted, provided that the - * above copyright notice and this permission notice appear in all copies. - * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES - * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR - * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES - * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN - * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT - * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. - */ - - -/** - * @defgroup dess_port_vlan DESS_PORT_VLAN - * @{ - */ -#include "sw.h" -#include "hsl.h" -#include "hsl_dev.h" -#include "hsl_port_prop.h" -#include "dess_portvlan.h" -#include "dess_reg.h" - -#define MAX_VLAN_ID 4095 -#define DESS_MAX_VLAN_TRANS 64 -#define DESS_VLAN_TRANS_ADDR 0x5ac00 - - -static sw_error_t -_dess_port_route_defv_set(a_uint32_t dev_id, fal_port_t port_id) -{ - sw_error_t rv; - a_uint32_t data = 0, reg = 0; - - HSL_REG_FIELD_GET(rv, dev_id, PORT_VLAN1, port_id, - COREP_EN, (a_uint8_t *) (&data), sizeof (a_uint32_t)); - - SW_RTN_ON_ERROR(rv); - - if (data) - { - HSL_REG_FIELD_GET(rv, dev_id, PORT_VLAN0, port_id, - DEF_SVID, (a_uint8_t *) (&data), sizeof (a_uint32_t)); - } - else - { - HSL_REG_FIELD_GET(rv, dev_id, PORT_VLAN0, port_id, - DEF_CVID, (a_uint8_t *) (&data), sizeof (a_uint32_t)); - } - - HSL_REG_ENTRY_GET(rv, dev_id, ROUTER_DEFV, (port_id / 2), - (a_uint8_t *) (®), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - - if (port_id % 2) - { - reg &= 0xffff; - reg |= ((data & 0xfff) << 16); - } - else - { - reg &= 0xffff0000; - reg |= (data & 0xfff); - } - - HSL_REG_ENTRY_SET(rv, dev_id, ROUTER_DEFV, (port_id / 2), - (a_uint8_t *) (®), sizeof (a_uint32_t)); - return rv; -} - -static sw_error_t -_dess_port_1qmode_set(a_uint32_t dev_id, fal_port_t port_id, - fal_pt_1qmode_t port_1qmode) -{ - sw_error_t rv; - a_uint32_t data, regval[FAL_1Q_MODE_BUTT] = { 0, 3, 2, 1 }; - - HSL_DEV_ID_CHECK(dev_id); - - if (A_FALSE == hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU)) - { - return SW_BAD_PARAM; - } - - if (FAL_1Q_MODE_BUTT <= port_1qmode) - { - return SW_BAD_PARAM; - } - - HSL_REG_FIELD_SET(rv, dev_id, PORT_LOOKUP_CTL, port_id, DOT1Q_MODE, - (a_uint8_t *) (®val[port_1qmode]), - sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - - if (FAL_1Q_DISABLE == port_1qmode) - { - data = 1; - } - else - { - data = 0; - } - - HSL_REG_FIELD_SET(rv, dev_id, PORT_VLAN1, port_id, VLAN_DIS, - (a_uint8_t *) (&data), sizeof (a_uint32_t)); - return rv; -} - -static sw_error_t -_dess_port_1qmode_get(a_uint32_t dev_id, fal_port_t port_id, - fal_pt_1qmode_t * pport_1qmode) -{ - sw_error_t rv; - a_uint32_t regval = 0; - fal_pt_1qmode_t retval[4] = { FAL_1Q_DISABLE, FAL_1Q_FALLBACK, - FAL_1Q_CHECK, FAL_1Q_SECURE - }; - - HSL_DEV_ID_CHECK(dev_id); - - if (A_FALSE == hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU)) - { - return SW_BAD_PARAM; - } - - SW_RTN_ON_NULL(pport_1qmode); - - HSL_REG_FIELD_GET(rv, dev_id, PORT_LOOKUP_CTL, port_id, DOT1Q_MODE, - (a_uint8_t *) (®val), sizeof (a_uint32_t)); - - SW_RTN_ON_ERROR(rv); - - *pport_1qmode = retval[regval & 0x3]; - - return SW_OK; -} - -static sw_error_t -_dess_port_egvlanmode_set(a_uint32_t dev_id, fal_port_t port_id, - fal_pt_1q_egmode_t port_egvlanmode) -{ - sw_error_t rv; - a_uint32_t regval[FAL_EG_MODE_BUTT] = { 0, 1, 2, 3, 3 }; - - HSL_DEV_ID_CHECK(dev_id); - - if (A_FALSE == hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU)) - { - return SW_BAD_PARAM; - } - - if ((FAL_EG_MODE_BUTT <= port_egvlanmode) - || (FAL_EG_HYBRID == port_egvlanmode)) - { - return SW_BAD_PARAM; - } - - HSL_REG_FIELD_SET(rv, dev_id, PORT_VLAN1, port_id, EG_VLAN_MODE, - (a_uint8_t *) (®val[port_egvlanmode]), - sizeof (a_uint32_t)); - - SW_RTN_ON_ERROR(rv); - - return rv; -} - -static sw_error_t -_dess_port_egvlanmode_get(a_uint32_t dev_id, fal_port_t port_id, - fal_pt_1q_egmode_t * pport_egvlanmode) -{ - sw_error_t rv; - a_uint32_t regval = 0; - fal_pt_1q_egmode_t retval[4] = { FAL_EG_UNMODIFIED, FAL_EG_UNTAGGED, - FAL_EG_TAGGED, FAL_EG_UNTOUCHED - }; - - HSL_DEV_ID_CHECK(dev_id); - - if (A_FALSE == hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU)) - { - return SW_BAD_PARAM; - } - - SW_RTN_ON_NULL(pport_egvlanmode); - - HSL_REG_FIELD_GET(rv, dev_id, PORT_VLAN1, port_id, EG_VLAN_MODE, - (a_uint8_t *) (®val), sizeof (a_uint32_t)); - - SW_RTN_ON_ERROR(rv); - - *pport_egvlanmode = retval[regval & 0x3]; - - return SW_OK; -} - -static sw_error_t -_dess_portvlan_member_add(a_uint32_t dev_id, fal_port_t port_id, - a_uint32_t mem_port_id) -{ - sw_error_t rv; - a_uint32_t regval = 0; - - HSL_DEV_ID_CHECK(dev_id); - - if (A_FALSE == hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU)) - { - return SW_BAD_PARAM; - } - - if (A_FALSE == hsl_port_prop_check(dev_id, mem_port_id, HSL_PP_INCL_CPU)) - { - return SW_BAD_PARAM; - } - - HSL_REG_FIELD_GET(rv, dev_id, PORT_LOOKUP_CTL, port_id, - PORT_VID_MEM, (a_uint8_t *) (®val), - sizeof (a_uint32_t)); - - SW_RTN_ON_ERROR(rv); - - regval |= (0x1UL << mem_port_id); - - HSL_REG_FIELD_SET(rv, dev_id, PORT_LOOKUP_CTL, port_id, - PORT_VID_MEM, (a_uint8_t *) (®val), - sizeof (a_uint32_t)); - - return rv; -} - -static sw_error_t -_dess_portvlan_member_del(a_uint32_t dev_id, fal_port_t port_id, - a_uint32_t mem_port_id) -{ - sw_error_t rv; - a_uint32_t regval = 0; - - HSL_DEV_ID_CHECK(dev_id); - - if (A_FALSE == hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU)) - { - return SW_BAD_PARAM; - } - - if (A_FALSE == hsl_port_prop_check(dev_id, mem_port_id, HSL_PP_INCL_CPU)) - { - return SW_BAD_PARAM; - } - - HSL_REG_FIELD_GET(rv, dev_id, PORT_LOOKUP_CTL, port_id, - PORT_VID_MEM, (a_uint8_t *) (®val), - sizeof (a_uint32_t)); - - SW_RTN_ON_ERROR(rv); - - regval &= (~(0x1UL << mem_port_id)); - - HSL_REG_FIELD_SET(rv, dev_id, PORT_LOOKUP_CTL, port_id, - PORT_VID_MEM, (a_uint8_t *) (®val), - sizeof (a_uint32_t)); - - return rv; -} - -static sw_error_t -_dess_portvlan_member_update(a_uint32_t dev_id, fal_port_t port_id, - fal_pbmp_t mem_port_map) -{ - sw_error_t rv; - - HSL_DEV_ID_CHECK(dev_id); - - if (A_FALSE == hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU)) - { - return SW_BAD_PARAM; - } - - if (A_FALSE == hsl_mports_prop_check(dev_id, mem_port_map, HSL_PP_INCL_CPU)) - { - return SW_BAD_PARAM; - } - - HSL_REG_FIELD_SET(rv, dev_id, PORT_LOOKUP_CTL, port_id, - PORT_VID_MEM, (a_uint8_t *) (&mem_port_map), - sizeof (a_uint32_t)); - - return rv; -} - -static sw_error_t -_dess_portvlan_member_get(a_uint32_t dev_id, fal_port_t port_id, - fal_pbmp_t * mem_port_map) -{ - sw_error_t rv; - - HSL_DEV_ID_CHECK(dev_id); - - if (A_FALSE == hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU)) - { - return SW_BAD_PARAM; - } - - *mem_port_map = 0; - HSL_REG_FIELD_GET(rv, dev_id, PORT_LOOKUP_CTL, port_id, - PORT_VID_MEM, (a_uint8_t *) mem_port_map, - sizeof (a_uint32_t)); - - SW_RTN_ON_ERROR(rv); - - return SW_OK; -} - -static sw_error_t -_dess_port_force_default_vid_set(a_uint32_t dev_id, fal_port_t port_id, - a_bool_t enable) -{ - sw_error_t rv; - a_uint32_t val; - - HSL_DEV_ID_CHECK(dev_id); - - if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU)) - { - return SW_BAD_PARAM; - } - - if (A_TRUE == enable) - { - val = 1; - } - else if (A_FALSE == enable) - { - val = 0; - } - else - { - return SW_BAD_PARAM; - } - - HSL_REG_FIELD_SET(rv, dev_id, PORT_VLAN1, port_id, - FORCE_DEF_VID, (a_uint8_t *) (&val), sizeof (a_uint32_t)); - return rv; -} - -static sw_error_t -_dess_port_force_default_vid_get(a_uint32_t dev_id, fal_port_t port_id, - a_bool_t * enable) -{ - sw_error_t rv; - a_uint32_t val = 0; - - HSL_DEV_ID_CHECK(dev_id); - - if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU)) - { - return SW_BAD_PARAM; - } - - HSL_REG_FIELD_GET(rv, dev_id, PORT_VLAN1, port_id, - FORCE_DEF_VID, (a_uint8_t *) (&val), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - - if (val) - { - *enable = A_TRUE; - } - else - { - *enable = A_FALSE; - } - - return SW_OK; -} - -static sw_error_t -_dess_port_force_portvlan_set(a_uint32_t dev_id, fal_port_t port_id, - a_bool_t enable) -{ - sw_error_t rv; - a_uint32_t val; - - HSL_DEV_ID_CHECK(dev_id); - - if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU)) - { - return SW_BAD_PARAM; - } - - if (A_TRUE == enable) - { - val = 1; - } - else if (A_FALSE == enable) - { - val = 0; - } - else - { - return SW_BAD_PARAM; - } - - HSL_REG_FIELD_SET(rv, dev_id, PORT_LOOKUP_CTL, port_id, - FORCE_PVLAN, (a_uint8_t *) (&val), sizeof (a_uint32_t)); - return rv; -} - -static sw_error_t -_dess_port_force_portvlan_get(a_uint32_t dev_id, fal_port_t port_id, - a_bool_t * enable) -{ - sw_error_t rv; - a_uint32_t val = 0; - - HSL_DEV_ID_CHECK(dev_id); - - if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU)) - { - return SW_BAD_PARAM; - } - - HSL_REG_FIELD_GET(rv, dev_id, PORT_LOOKUP_CTL, port_id, - FORCE_PVLAN, (a_uint8_t *) (&val), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - - if (val) - { - *enable = A_TRUE; - } - else - { - *enable = A_FALSE; - } - - return SW_OK; -} - -static sw_error_t -_dess_nestvlan_tpid_set(a_uint32_t dev_id, a_uint32_t tpid) -{ - sw_error_t rv; - a_uint32_t val; - - HSL_DEV_ID_CHECK(dev_id); - - val = tpid; - HSL_REG_FIELD_SET(rv, dev_id, SERVICE_TAG, 0, - TAG_VALUE, (a_uint8_t *) (&val), sizeof (a_uint32_t)); - return rv; -} - -static sw_error_t -_dess_nestvlan_tpid_get(a_uint32_t dev_id, a_uint32_t * tpid) -{ - sw_error_t rv; - a_uint32_t val = 0; - - HSL_DEV_ID_CHECK(dev_id); - - HSL_REG_FIELD_GET(rv, dev_id, SERVICE_TAG, 0, - TAG_VALUE, (a_uint8_t *) (&val), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - - *tpid = val; - return SW_OK; -} - -static sw_error_t -_dess_port_invlan_mode_set(a_uint32_t dev_id, fal_port_t port_id, - fal_pt_invlan_mode_t mode) -{ - sw_error_t rv; - a_uint32_t regval[FAL_INVLAN_MODE_BUTT] = { 0, 1, 2 }; - - HSL_DEV_ID_CHECK(dev_id); - - if (A_FALSE == hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU)) - { - return SW_BAD_PARAM; - } - - if (FAL_INVLAN_MODE_BUTT <= mode) - { - return SW_BAD_PARAM; - } - - HSL_REG_FIELD_SET(rv, dev_id, PORT_VLAN1, port_id, IN_VLAN_MODE, - (a_uint8_t *) (®val[mode]), sizeof (a_uint32_t)); - return rv; -} - -static sw_error_t -_dess_port_invlan_mode_get(a_uint32_t dev_id, fal_port_t port_id, - fal_pt_invlan_mode_t * mode) -{ - sw_error_t rv; - a_uint32_t regval = 0; - fal_pt_invlan_mode_t retval[FAL_INVLAN_MODE_BUTT] = { FAL_INVLAN_ADMIT_ALL, - FAL_INVLAN_ADMIT_TAGGED, FAL_INVLAN_ADMIT_UNTAGGED - }; - - HSL_DEV_ID_CHECK(dev_id); - - if (A_FALSE == hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU)) - { - return SW_BAD_PARAM; - } - - SW_RTN_ON_NULL(mode); - - HSL_REG_FIELD_GET(rv, dev_id, PORT_VLAN1, port_id, IN_VLAN_MODE, - (a_uint8_t *) (®val), sizeof (a_uint32_t)); - - SW_RTN_ON_ERROR(rv); - - if (regval >= 3) - { - return SW_FAIL; - } - *mode = retval[regval & 0x3]; - - return rv; -} - -static sw_error_t -_dess_port_tls_set(a_uint32_t dev_id, fal_port_t port_id, a_bool_t enable) -{ - sw_error_t rv; - a_uint32_t val; - - HSL_DEV_ID_CHECK(dev_id); - - if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU)) - { - return SW_BAD_PARAM; - } - - if (A_TRUE == enable) - { - val = 1; - } - else if (A_FALSE == enable) - { - val = 0; - } - else - { - return SW_BAD_PARAM; - } - - HSL_REG_FIELD_SET(rv, dev_id, PORT_VLAN1, port_id, - TLS_EN, (a_uint8_t *) (&val), sizeof (a_uint32_t)); - return rv; -} - -static sw_error_t -_dess_port_tls_get(a_uint32_t dev_id, fal_port_t port_id, a_bool_t * enable) -{ - sw_error_t rv; - a_uint32_t val = 0; - - HSL_DEV_ID_CHECK(dev_id); - - if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU)) - { - return SW_BAD_PARAM; - } - - HSL_REG_FIELD_GET(rv, dev_id, PORT_VLAN1, port_id, - TLS_EN, (a_uint8_t *) (&val), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - - if (1 == val) - { - *enable = A_TRUE; - } - else - { - *enable = A_FALSE; - } - - return SW_OK; -} - -static sw_error_t -_dess_port_pri_propagation_set(a_uint32_t dev_id, fal_port_t port_id, - a_bool_t enable) -{ - sw_error_t rv; - a_uint32_t val; - - HSL_DEV_ID_CHECK(dev_id); - - if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU)) - { - return SW_BAD_PARAM; - } - - if (A_TRUE == enable) - { - val = 1; - } - else if (A_FALSE == enable) - { - val = 0; - } - else - { - return SW_BAD_PARAM; - } - - HSL_REG_FIELD_SET(rv, dev_id, PORT_VLAN1, port_id, - PRI_PROPAGATION, (a_uint8_t *) (&val), - sizeof (a_uint32_t)); - return rv; -} - -static sw_error_t -_dess_port_pri_propagation_get(a_uint32_t dev_id, fal_port_t port_id, - a_bool_t * enable) -{ - sw_error_t rv; - a_uint32_t val = 0; - - HSL_DEV_ID_CHECK(dev_id); - - if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU)) - { - return SW_BAD_PARAM; - } - - HSL_REG_FIELD_GET(rv, dev_id, PORT_VLAN1, port_id, - PRI_PROPAGATION, (a_uint8_t *) (&val), - sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - - if (1 == val) - { - *enable = A_TRUE; - } - else - { - *enable = A_FALSE; - } - - return SW_OK; -} - -static sw_error_t -_dess_port_default_svid_set(a_uint32_t dev_id, fal_port_t port_id, - a_uint32_t vid) -{ - sw_error_t rv; - a_uint32_t val; - - HSL_DEV_ID_CHECK(dev_id); - - if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU)) - { - return SW_BAD_PARAM; - } - - if (vid > MAX_VLAN_ID) - { - return SW_BAD_PARAM; - } - - val = vid; - HSL_REG_FIELD_SET(rv, dev_id, PORT_VLAN0, port_id, - DEF_SVID, (a_uint8_t *) (&val), sizeof (a_uint32_t)); - - SW_RTN_ON_ERROR(rv); - - rv = _dess_port_route_defv_set(dev_id, port_id); - return rv; -} - -static sw_error_t -_dess_port_default_svid_get(a_uint32_t dev_id, fal_port_t port_id, - a_uint32_t * vid) -{ - sw_error_t rv; - a_uint32_t val = 0; - - HSL_DEV_ID_CHECK(dev_id); - - if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU)) - { - return SW_BAD_PARAM; - } - - HSL_REG_FIELD_GET(rv, dev_id, PORT_VLAN0, port_id, - DEF_SVID, (a_uint8_t *) (&val), sizeof (a_uint32_t)); - - *vid = val & 0xfff; - return rv; -} - -static sw_error_t -_dess_port_default_cvid_set(a_uint32_t dev_id, fal_port_t port_id, - a_uint32_t vid) -{ - sw_error_t rv; - a_uint32_t val; - - HSL_DEV_ID_CHECK(dev_id); - - if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU)) - { - return SW_BAD_PARAM; - } - - if (vid > MAX_VLAN_ID) - { - return SW_BAD_PARAM; - } - - val = vid; - HSL_REG_FIELD_SET(rv, dev_id, PORT_VLAN0, port_id, - DEF_CVID, (a_uint8_t *) (&val), sizeof (a_uint32_t)); - - SW_RTN_ON_ERROR(rv); - - rv = _dess_port_route_defv_set(dev_id, port_id); - return rv; -} - -static sw_error_t -_dess_port_default_cvid_get(a_uint32_t dev_id, fal_port_t port_id, - a_uint32_t * vid) -{ - sw_error_t rv; - a_uint32_t val = 0; - - HSL_DEV_ID_CHECK(dev_id); - - if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU)) - { - return SW_BAD_PARAM; - } - - HSL_REG_FIELD_GET(rv, dev_id, PORT_VLAN0, port_id, - DEF_CVID, (a_uint8_t *) (&val), sizeof (a_uint32_t)); - - *vid = val & 0xfff; - return rv; -} - -static sw_error_t -_dess_port_vlan_propagation_set(a_uint32_t dev_id, fal_port_t port_id, - fal_vlan_propagation_mode_t mode) -{ - sw_error_t rv; - a_uint32_t reg = 0, p, c; - - HSL_DEV_ID_CHECK(dev_id); - - if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU)) - { - return SW_BAD_PARAM; - } - - if (FAL_VLAN_PROPAGATION_DISABLE == mode) - { - p = 0; - c = 0; - } - else if (FAL_VLAN_PROPAGATION_CLONE == mode) - { - p = 1; - c = 1; - } - else if (FAL_VLAN_PROPAGATION_REPLACE == mode) - { - p = 1; - c = 0; - } - else - { - return SW_BAD_PARAM; - } - - HSL_REG_ENTRY_GET(rv, dev_id, PORT_VLAN1, port_id, - (a_uint8_t *) (®), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - - SW_SET_REG_BY_FIELD(PORT_VLAN1, PROPAGATION_EN, p, reg); - SW_SET_REG_BY_FIELD(PORT_VLAN1, CLONE, c, reg); - - HSL_REG_ENTRY_SET(rv, dev_id, PORT_VLAN1, port_id, - (a_uint8_t *) (®), sizeof (a_uint32_t)); - return rv; -} - -static sw_error_t -_dess_port_vlan_propagation_get(a_uint32_t dev_id, fal_port_t port_id, - fal_vlan_propagation_mode_t * mode) -{ - sw_error_t rv; - a_uint32_t reg = 0, p, c; - - HSL_DEV_ID_CHECK(dev_id); - - if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU)) - { - return SW_BAD_PARAM; - } - - HSL_REG_ENTRY_GET(rv, dev_id, PORT_VLAN1, port_id, - (a_uint8_t *) (®), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - - SW_GET_FIELD_BY_REG(PORT_VLAN1, PROPAGATION_EN, p, reg); - SW_GET_FIELD_BY_REG(PORT_VLAN1, CLONE, c, reg); - - if (p) - { - if (c) - { - *mode = FAL_VLAN_PROPAGATION_CLONE; - } - else - { - *mode = FAL_VLAN_PROPAGATION_REPLACE; - } - } - else - { - *mode = FAL_VLAN_PROPAGATION_DISABLE; - } - - return SW_OK; -} - -static sw_error_t -_dess_vlan_trans_read(a_uint32_t dev_id, a_uint32_t entry_idx, - fal_pbmp_t * pbmp, fal_vlan_trans_entry_t * entry) -{ - sw_error_t rv; - a_uint32_t i, addr, dir, table[2] = {0}; - - *pbmp = 0; - aos_mem_zero(entry, sizeof (fal_vlan_trans_entry_t)); - - addr = DESS_VLAN_TRANS_ADDR + (entry_idx << 3); - /* get vlan trans table */ - for (i = 0; i < 2; i++) - { - HSL_REG_ENTRY_GEN_GET(rv, dev_id, addr + (i << 2), sizeof (a_uint32_t), - (a_uint8_t *) (&(table[i])), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - } - - dir = 0x3 & (table[1] >> 4); - if (!dir) - { - return SW_EMPTY; - } - - entry->o_vid = table[0] & 0xfff; - *pbmp = (table[1] >> 6) & 0x7f; - - if (3 == dir) - { - entry->bi_dir = A_TRUE; - entry->forward_dir = A_TRUE; - entry->reverse_dir = A_TRUE; - } - else if (1 == dir) - { - entry->bi_dir = A_FALSE; - entry->forward_dir = A_TRUE; - entry->reverse_dir = A_FALSE; - } - else - { - entry->bi_dir = A_FALSE; - entry->forward_dir = A_FALSE; - entry->reverse_dir = A_TRUE; - } - - entry->o_vid_is_cvid = (table[1] >> 13) & 0x1UL; - entry->one_2_one_vlan = (table[1] >> 16) & 0x1UL; - entry->s_vid_enable = (table[1] >> 14) & 0x1UL; - entry->c_vid_enable = (table[1] >> 15) & 0x1UL; - - if (A_TRUE == entry->s_vid_enable) - { - entry->s_vid = (table[0] >> 12) & 0xfff; - } - - if (A_TRUE == entry->c_vid_enable) - { - entry->c_vid = ((table[0] >> 24) & 0xff) | ((table[1] & 0xf) << 8); - } - - return SW_OK; -} - -static sw_error_t -_dess_vlan_trans_write(a_uint32_t dev_id, a_uint32_t entry_idx, fal_pbmp_t pbmp, - fal_vlan_trans_entry_t entry) -{ - sw_error_t rv; - a_uint32_t i, addr, table[2] = { 0 }; - - addr = DESS_VLAN_TRANS_ADDR + (entry_idx << 3); - - if (0 != pbmp) - { - table[0] = entry.o_vid & 0xfff; - table[0] |= ((entry.s_vid & 0xfff) << 12); - table[0] |= ((entry.c_vid & 0xff) << 24); - table[1] = (entry.c_vid >> 8) & 0xf; - - if (A_TRUE == entry.bi_dir) - { - table[1] |= (0x3 << 4); - } - - if (A_TRUE == entry.forward_dir) - { - table[1] |= (0x1 << 4); - } - - if (A_TRUE == entry.reverse_dir) - { - table[1] |= (0x1 << 5); - } - - table[1] |= (pbmp << 6); - table[1] |= ((0x1UL & entry.o_vid_is_cvid) << 13); - table[1] |= ((0x1UL & entry.s_vid_enable) << 14); - table[1] |= ((0x1UL & entry.c_vid_enable) << 15); - table[1] |= ((0x1UL & entry.one_2_one_vlan) << 16); - } - - /* set vlan trans table */ - for (i = 0; i < 2; i++) - { - HSL_REG_ENTRY_GEN_SET(rv, dev_id, addr + (i << 2), sizeof (a_uint32_t), - (a_uint8_t *) (&(table[i])), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - } - - return SW_OK; -} - -static sw_error_t -_dess_port_vlan_trans_convert(fal_vlan_trans_entry_t * entry, - fal_vlan_trans_entry_t * local) -{ - aos_mem_copy(local, entry, sizeof (fal_vlan_trans_entry_t)); - - if ((A_TRUE == local->bi_dir) - || ((A_TRUE == local->forward_dir) - && (A_TRUE == local->reverse_dir))) - { - local->bi_dir = A_TRUE; - local->forward_dir = A_TRUE; - local->reverse_dir = A_TRUE; - } - - if (A_FALSE == local->s_vid_enable) - { - local->s_vid = 0; - } - - if (A_FALSE == local->c_vid_enable) - { - local->c_vid = 0; - } - - return SW_OK; -} - -static sw_error_t -_dess_port_vlan_trans_add(a_uint32_t dev_id, fal_port_t port_id, - fal_vlan_trans_entry_t * entry) -{ - sw_error_t rv; - fal_pbmp_t t_pbmp; - a_uint32_t idx, entry_idx = DESS_MAX_VLAN_TRANS; - fal_vlan_trans_entry_t temp, local; - - HSL_DEV_ID_CHECK(dev_id); - - if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU)) - { - return SW_BAD_PARAM; - } - - if (NULL == entry) - { - return SW_BAD_PTR; - } - aos_mem_zero(&local, sizeof (fal_vlan_trans_entry_t)); - rv = _dess_port_vlan_trans_convert(entry, &local); - SW_RTN_ON_ERROR(rv); - - for (idx = 0; idx < DESS_MAX_VLAN_TRANS; idx++) - { - rv = _dess_vlan_trans_read(dev_id, idx, &t_pbmp, &temp); - if (SW_EMPTY == rv) - { - entry_idx = idx; - continue; - } - SW_RTN_ON_ERROR(rv); - - if (!aos_mem_cmp(&local, &temp, sizeof (fal_vlan_trans_entry_t))) - { - if (SW_IS_PBMP_MEMBER(t_pbmp, port_id)) - { - return SW_ALREADY_EXIST; - } - entry_idx = idx; - break; - } - else - { - t_pbmp = 0; - } - } - - if (DESS_MAX_VLAN_TRANS != entry_idx) - { - t_pbmp |= (0x1 << port_id); - } - else - { - return SW_NO_RESOURCE; - } - - return _dess_vlan_trans_write(dev_id, entry_idx, t_pbmp, local); -} - -static sw_error_t -_dess_port_vlan_trans_del(a_uint32_t dev_id, fal_port_t port_id, - fal_vlan_trans_entry_t * entry) -{ - sw_error_t rv; - fal_pbmp_t t_pbmp; - a_uint32_t idx, entry_idx = DESS_MAX_VLAN_TRANS; - fal_vlan_trans_entry_t temp, local; - - HSL_DEV_ID_CHECK(dev_id); - - if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU)) - { - return SW_BAD_PARAM; - } - - if (NULL == entry) - { - return SW_BAD_PTR; - } - aos_mem_zero(&local, sizeof (fal_vlan_trans_entry_t)); - rv = _dess_port_vlan_trans_convert(entry, &local); - SW_RTN_ON_ERROR(rv); - - for (idx = 0; idx < DESS_MAX_VLAN_TRANS; idx++) - { - rv = _dess_vlan_trans_read(dev_id, idx, &t_pbmp, &temp); - if (SW_EMPTY == rv) - { - continue; - } - SW_RTN_ON_ERROR(rv); - - if (!aos_mem_cmp(&temp, &local, sizeof (fal_vlan_trans_entry_t))) - { - if (SW_IS_PBMP_MEMBER(t_pbmp, port_id)) - { - entry_idx = idx; - break; - } - } - } - - if (DESS_MAX_VLAN_TRANS != entry_idx) - { - t_pbmp &= (~(0x1 << port_id)); - } - else - { - return SW_NOT_FOUND; - } - - return _dess_vlan_trans_write(dev_id, entry_idx, t_pbmp, local); -} - -static sw_error_t -_dess_port_vlan_trans_get(a_uint32_t dev_id, fal_port_t port_id, - fal_vlan_trans_entry_t * entry) -{ - sw_error_t rv; - fal_pbmp_t t_pbmp; - a_uint32_t idx; - fal_vlan_trans_entry_t temp, local; - - HSL_DEV_ID_CHECK(dev_id); - - if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU)) - { - return SW_BAD_PARAM; - } - - if (NULL == entry) - { - return SW_BAD_PTR; - } - aos_mem_zero(&local, sizeof (fal_vlan_trans_entry_t)); - rv = _dess_port_vlan_trans_convert(entry, &local); - SW_RTN_ON_ERROR(rv); - - for (idx = 0; idx < DESS_MAX_VLAN_TRANS; idx++) - { - rv = _dess_vlan_trans_read(dev_id, idx, &t_pbmp, &temp); - if (SW_EMPTY == rv) - { - continue; - } - SW_RTN_ON_ERROR(rv); - - if (!aos_mem_cmp(&temp, &local, sizeof (fal_vlan_trans_entry_t))) - { - if (SW_IS_PBMP_MEMBER(t_pbmp, port_id)) - { - return SW_OK; - } - } - } - - return SW_NOT_FOUND; -} - -static sw_error_t -_dess_port_vlan_trans_iterate(a_uint32_t dev_id, fal_port_t port_id, - a_uint32_t * iterator, - fal_vlan_trans_entry_t * entry) -{ - a_uint32_t index; - sw_error_t rv; - fal_vlan_trans_entry_t entry_t; - fal_pbmp_t pbmp_t; - - HSL_DEV_ID_CHECK(dev_id); - - if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU)) - { - return SW_BAD_PARAM; - } - - if ((NULL == iterator) || (NULL == entry)) - { - return SW_BAD_PTR; - } - - if (DESS_MAX_VLAN_TRANS < *iterator) - { - return SW_BAD_PARAM; - } - - for (index = *iterator; index < DESS_MAX_VLAN_TRANS; index++) - { - rv = _dess_vlan_trans_read(dev_id, index, &pbmp_t, &entry_t); - if (SW_EMPTY == rv) - { - continue; - } - - if (SW_IS_PBMP_MEMBER(pbmp_t, port_id)) - { - aos_mem_copy(entry, &entry_t, sizeof (fal_vlan_trans_entry_t)); - break; - } - } - - if (DESS_MAX_VLAN_TRANS == index) - { - return SW_NO_MORE; - } - - *iterator = index + 1; - return SW_OK; -} - -static sw_error_t -_dess_qinq_mode_set(a_uint32_t dev_id, fal_qinq_mode_t mode) -{ - sw_error_t rv; - a_uint32_t stag = 0; - - HSL_DEV_ID_CHECK(dev_id); - - if (FAL_QINQ_MODE_BUTT <= mode) - { - return SW_BAD_PARAM; - } - - if (FAL_QINQ_STAG_MODE == mode) - { - stag = 1; - } - - HSL_REG_FIELD_SET(rv, dev_id, SERVICE_TAG, 0, - STAG_MODE, (a_uint8_t *) (&stag), sizeof (a_uint32_t)); - - return rv; -} - -static sw_error_t -_dess_qinq_mode_get(a_uint32_t dev_id, fal_qinq_mode_t * mode) -{ - sw_error_t rv; - a_uint32_t stag = 0; - - HSL_DEV_ID_CHECK(dev_id); - - HSL_REG_FIELD_GET(rv, dev_id, SERVICE_TAG, 0, - STAG_MODE, (a_uint8_t *) (&stag), sizeof (a_uint32_t)); - - SW_RTN_ON_ERROR(rv); - - if (stag) - { - *mode = FAL_QINQ_STAG_MODE; - } - else - { - *mode = FAL_QINQ_CTAG_MODE; - } - - return SW_OK; -} - -static sw_error_t -_dess_port_qinq_role_set(a_uint32_t dev_id, fal_port_t port_id, - fal_qinq_port_role_t role) -{ - sw_error_t rv; - a_uint32_t core = 0; - - HSL_DEV_ID_CHECK(dev_id); - - if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU)) - { - return SW_BAD_PARAM; - } - - if (FAL_QINQ_PORT_ROLE_BUTT <= role) - { - return SW_BAD_PARAM; - } - - if (FAL_QINQ_CORE_PORT == role) - { - core = 1; - } - - HSL_REG_FIELD_SET(rv, dev_id, PORT_VLAN1, port_id, - COREP_EN, (a_uint8_t *) (&core), sizeof (a_uint32_t)); - - SW_RTN_ON_ERROR(rv); - - rv = _dess_port_route_defv_set(dev_id, port_id); - return rv; -} - -static sw_error_t -_dess_port_qinq_role_get(a_uint32_t dev_id, fal_port_t port_id, - fal_qinq_port_role_t * role) -{ - sw_error_t rv; - a_uint32_t core = 0; - - HSL_DEV_ID_CHECK(dev_id); - - if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU)) - { - return SW_BAD_PARAM; - } - - HSL_REG_FIELD_GET(rv, dev_id, PORT_VLAN1, port_id, - COREP_EN, (a_uint8_t *) (&core), sizeof (a_uint32_t)); - - SW_RTN_ON_ERROR(rv); - - if (core) - { - *role = FAL_QINQ_CORE_PORT; - } - else - { - *role = FAL_QINQ_EDGE_PORT; - } - - return SW_OK; -} - -static sw_error_t -_dess_port_mac_vlan_xlt_set(a_uint32_t dev_id, fal_port_t port_id, - a_bool_t enable) -{ - sw_error_t rv; - a_uint32_t val; - - HSL_DEV_ID_CHECK(dev_id); - - if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU)) - { - return SW_BAD_PARAM; - } - - if (A_TRUE == enable) - { - val = 1; - } - else if (A_FALSE == enable) - { - val = 0; - } - else - { - return SW_BAD_PARAM; - } - - HSL_REG_FIELD_SET(rv, dev_id, PRI_CTL, port_id, - EG_MAC_BASE_VLAN_EN, (a_uint8_t *) (&val), sizeof (a_uint32_t)); - return rv; - -} - -static sw_error_t -_dess_port_mac_vlan_xlt_get(a_uint32_t dev_id, fal_port_t port_id, - a_bool_t * enable) -{ - sw_error_t rv; - a_uint32_t val = 0; - - HSL_DEV_ID_CHECK(dev_id); - - if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU)) - { - return SW_BAD_PARAM; - } - - HSL_REG_FIELD_GET(rv, dev_id, PRI_CTL, port_id, - EG_MAC_BASE_VLAN_EN, (a_uint8_t *) (&val), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - - if (1 == val) - { - *enable = A_TRUE; - } - else - { - *enable = A_FALSE; - } - - return SW_OK; -} - -static sw_error_t -_dess_netisolate_set(a_uint32_t dev_id, a_uint32_t enable) -{ - sw_error_t rv; - a_uint32_t val; - - HSL_DEV_ID_CHECK(dev_id); - - val = enable; - HSL_REG_FIELD_SET(rv, dev_id, VLAN_TRANS, 0, - NET_ISO, (a_uint8_t *) (&val), sizeof (a_uint32_t)); - return rv; -} - -static sw_error_t -_dess_netisolate_get(a_uint32_t dev_id, a_uint32_t * enable) -{ - sw_error_t rv; - a_uint32_t val = 0; - - HSL_DEV_ID_CHECK(dev_id); - - HSL_REG_FIELD_GET(rv, dev_id, VLAN_TRANS, 0, - NET_ISO, (a_uint8_t *) (&val), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - - *enable = val; - return SW_OK; -} - -static sw_error_t -_dess_eg_trans_filter_bypass_en_set(a_uint32_t dev_id, a_uint32_t enable) -{ - sw_error_t rv; - a_uint32_t val; - - HSL_DEV_ID_CHECK(dev_id); - - val = enable; - HSL_REG_FIELD_SET(rv, dev_id, VLAN_TRANS, 0, - EG_FLTR_BYPASS_EN, (a_uint8_t *) (&val), sizeof (a_uint32_t)); - return rv; -} - -static sw_error_t -_dess_eg_trans_filter_bypass_en_get(a_uint32_t dev_id, a_uint32_t * enable) -{ - sw_error_t rv; - a_uint32_t val = 0; - - HSL_DEV_ID_CHECK(dev_id); - - HSL_REG_FIELD_GET(rv, dev_id, VLAN_TRANS, 0, - EG_FLTR_BYPASS_EN, (a_uint8_t *) (&val), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - - *enable = val; - return SW_OK; -} - -static sw_error_t -_dess_port_vrf_id_set(a_uint32_t dev_id, fal_port_t port_id, - a_uint32_t vrf_id) -{ - sw_error_t rv; - - HSL_DEV_ID_CHECK(dev_id); - - if (A_FALSE == hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU)) - { - return SW_BAD_PARAM; - } - - HSL_REG_FIELD_SET(rv, dev_id, PORT_VLAN1, port_id, - VRF_ID, (a_uint8_t *) (&vrf_id), - sizeof (a_uint32_t)); - - SW_RTN_ON_ERROR(rv); - - return rv; -} - -static sw_error_t -_dess_port_vrf_id_get(a_uint32_t dev_id, fal_port_t port_id, - a_uint32_t * vrf_id) -{ - sw_error_t rv; - - HSL_DEV_ID_CHECK(dev_id); - - if (A_FALSE == hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU)) - { - return SW_BAD_PARAM; - } - - HSL_REG_FIELD_GET(rv, dev_id, PORT_VLAN1, port_id, - VRF_ID, (a_uint8_t *) (vrf_id), - sizeof (a_uint32_t)); - - SW_RTN_ON_ERROR(rv); - - return rv; -} - - -/** - * @brief Set 802.1q work mode on a particular port. - * @param[in] dev_id device id - * @param[in] port_id port id - * @param[in] port_1qmode 802.1q work mode - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -dess_port_1qmode_set(a_uint32_t dev_id, fal_port_t port_id, - fal_pt_1qmode_t port_1qmode) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _dess_port_1qmode_set(dev_id, port_id, port_1qmode); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Get 802.1q work mode on a particular port. - * @param[in] dev_id device id - * @param[in] port_id port id - * @param[out] port_1qmode 802.1q work mode - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -dess_port_1qmode_get(a_uint32_t dev_id, fal_port_t port_id, - fal_pt_1qmode_t * pport_1qmode) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _dess_port_1qmode_get(dev_id, port_id, pport_1qmode); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Set packets transmitted out vlan tagged mode on a particular port. - * @param[in] dev_id device id - * @param[in] port_id port id - * @param[in] port_egvlanmode packets transmitted out vlan tagged mode - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -dess_port_egvlanmode_set(a_uint32_t dev_id, fal_port_t port_id, - fal_pt_1q_egmode_t port_egvlanmode) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _dess_port_egvlanmode_set(dev_id, port_id, port_egvlanmode); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Get packets transmitted out vlan tagged mode on a particular port. - * @param[in] dev_id device id - * @param[in] port_id port id - * @param[out] port_egvlanmode packets transmitted out vlan tagged mode - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -dess_port_egvlanmode_get(a_uint32_t dev_id, fal_port_t port_id, - fal_pt_1q_egmode_t * pport_egvlanmode) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _dess_port_egvlanmode_get(dev_id, port_id, pport_egvlanmode); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Add member of port based vlan on a particular port. - * @param[in] dev_id device id - * @param[in] port_id port id - * @param[in] mem_port_id port member - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -dess_portvlan_member_add(a_uint32_t dev_id, fal_port_t port_id, - a_uint32_t mem_port_id) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _dess_portvlan_member_add(dev_id, port_id, mem_port_id); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Delete member of port based vlan on a particular port. - * @param[in] dev_id device id - * @param[in] port_id port id - * @param[in] mem_port_id port member - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -dess_portvlan_member_del(a_uint32_t dev_id, fal_port_t port_id, - a_uint32_t mem_port_id) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _dess_portvlan_member_del(dev_id, port_id, mem_port_id); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Update member of port based vlan on a particular port. - * @param[in] dev_id device id - * @param[in] port_id port id - * @param[in] mem_port_map port members - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -dess_portvlan_member_update(a_uint32_t dev_id, fal_port_t port_id, - fal_pbmp_t mem_port_map) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _dess_portvlan_member_update(dev_id, port_id, mem_port_map); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Get member of port based vlan on a particular port. - * @param[in] dev_id device id - * @param[in] port_id port id - * @param[out] mem_port_map port members - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -dess_portvlan_member_get(a_uint32_t dev_id, fal_port_t port_id, - fal_pbmp_t * mem_port_map) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _dess_portvlan_member_get(dev_id, port_id, mem_port_map); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Set force default vlan id status on a particular port. - * @param[in] dev_id device id - * @param[in] port_id port id - * @param[in] enable A_TRUE or A_FALSE - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -dess_port_force_default_vid_set(a_uint32_t dev_id, fal_port_t port_id, - a_bool_t enable) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _dess_port_force_default_vid_set(dev_id, port_id, enable); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Get force default vlan id status on a particular port. - * @param[in] dev_id device id - * @param[in] port_id port id - * @param[out] enable A_TRUE or A_FALSE - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -dess_port_force_default_vid_get(a_uint32_t dev_id, fal_port_t port_id, - a_bool_t * enable) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _dess_port_force_default_vid_get(dev_id, port_id, enable); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Set force port based vlan status on a particular port. - * @param[in] dev_id device id - * @param[in] port_id port id - * @param[in] enable A_TRUE or A_FALSE - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -dess_port_force_portvlan_set(a_uint32_t dev_id, fal_port_t port_id, - a_bool_t enable) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _dess_port_force_portvlan_set(dev_id, port_id, enable); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Get force port based vlan status on a particular port. - * @param[in] dev_id device id - * @param[in] port_id port id - * @param[out] enable A_TRUE or A_FALSE - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -dess_port_force_portvlan_get(a_uint32_t dev_id, fal_port_t port_id, - a_bool_t * enable) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _dess_port_force_portvlan_get(dev_id, port_id, enable); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Set nest vlan tpid on a particular device. - * @param[in] dev_id device id - * @param[in] tpid tag protocol identification - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -dess_nestvlan_tpid_set(a_uint32_t dev_id, a_uint32_t tpid) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _dess_nestvlan_tpid_set(dev_id, tpid); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Get nest vlan tpid on a particular device. - * @param[in] dev_id device id - * @param[out] tpid tag protocol identification - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -dess_nestvlan_tpid_get(a_uint32_t dev_id, a_uint32_t * tpid) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _dess_nestvlan_tpid_get(dev_id, tpid); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Set ingress vlan mode mode on a particular port. - * @param[in] dev_id device id - * @param[in] port_id port id - * @param[in] mode ingress vlan mode - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -dess_port_invlan_mode_set(a_uint32_t dev_id, fal_port_t port_id, - fal_pt_invlan_mode_t mode) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _dess_port_invlan_mode_set(dev_id, port_id, mode); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Get ingress vlan mode mode on a particular port. - * @param[in] dev_id device id - * @param[in] port_id port id - * @param[out] mode ingress vlan mode - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -dess_port_invlan_mode_get(a_uint32_t dev_id, fal_port_t port_id, - fal_pt_invlan_mode_t * mode) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _dess_port_invlan_mode_get(dev_id, port_id, mode); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Set tls status on a particular port. - * @param[in] dev_id device id - * @param[in] port_id port id - * @param[in] enable A_TRUE or A_FALSE - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -dess_port_tls_set(a_uint32_t dev_id, fal_port_t port_id, a_bool_t enable) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _dess_port_tls_set(dev_id, port_id, enable); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Get tls status on a particular port. - * @param[in] dev_id device id - * @param[in] port_id port id - * @param[out] enable A_TRUE or A_FALSE - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -dess_port_tls_get(a_uint32_t dev_id, fal_port_t port_id, a_bool_t * enable) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _dess_port_tls_get(dev_id, port_id, enable); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Set priority propagation status on a particular port. - * @param[in] dev_id device id - * @param[in] port_id port id - * @param[in] enable A_TRUE or A_FALSE - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -dess_port_pri_propagation_set(a_uint32_t dev_id, fal_port_t port_id, - a_bool_t enable) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _dess_port_pri_propagation_set(dev_id, port_id, enable); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Get priority propagation status on a particular port. - * @param[in] dev_id device id - * @param[in] port_id port id - * @param[out] enable A_TRUE or A_FALSE - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -dess_port_pri_propagation_get(a_uint32_t dev_id, fal_port_t port_id, - a_bool_t * enable) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _dess_port_pri_propagation_get(dev_id, port_id, enable); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Set default s-vid on a particular port. - * @param[in] dev_id device id - * @param[in] port_id port id - * @param[in] vid s-vid - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -dess_port_default_svid_set(a_uint32_t dev_id, fal_port_t port_id, - a_uint32_t vid) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _dess_port_default_svid_set(dev_id, port_id, vid); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Get default s-vid on a particular port. - * @param[in] dev_id device id - * @param[in] port_id port id - * @param[out] vid s-vid - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -dess_port_default_svid_get(a_uint32_t dev_id, fal_port_t port_id, - a_uint32_t * vid) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _dess_port_default_svid_get(dev_id, port_id, vid); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Set default c-vid on a particular port. - * @param[in] dev_id device id - * @param[in] port_id port id - * @param[in] vid c-vid - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -dess_port_default_cvid_set(a_uint32_t dev_id, fal_port_t port_id, - a_uint32_t vid) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _dess_port_default_cvid_set(dev_id, port_id, vid); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Get default c-vid on a particular port. - * @param[in] dev_id device id - * @param[in] port_id port id - * @param[out] vid c-vid - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -dess_port_default_cvid_get(a_uint32_t dev_id, fal_port_t port_id, - a_uint32_t * vid) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _dess_port_default_cvid_get(dev_id, port_id, vid); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Set vlan propagation status on a particular port. - * @param[in] dev_id device id - * @param[in] port_id port id - * @param[in] mode vlan propagation mode - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -dess_port_vlan_propagation_set(a_uint32_t dev_id, fal_port_t port_id, - fal_vlan_propagation_mode_t mode) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _dess_port_vlan_propagation_set(dev_id, port_id, mode); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Get vlan propagation status on a particular port. - * @param[in] dev_id device id - * @param[in] port_id port id - * @param[out] mode vlan propagation mode - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -dess_port_vlan_propagation_get(a_uint32_t dev_id, fal_port_t port_id, - fal_vlan_propagation_mode_t * mode) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _dess_port_vlan_propagation_get(dev_id, port_id, mode); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Add a vlan translation entry to a particular port. - * @param[in] dev_id device id - * @param[in] port_id port id - * @param entry vlan translation entry - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -dess_port_vlan_trans_add(a_uint32_t dev_id, fal_port_t port_id, - fal_vlan_trans_entry_t * entry) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _dess_port_vlan_trans_add(dev_id, port_id, entry); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Delete a vlan translation entry from a particular port. - * @param[in] dev_id device id - * @param[in] port_id port id - * @param entry vlan translation entry - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -dess_port_vlan_trans_del(a_uint32_t dev_id, fal_port_t port_id, - fal_vlan_trans_entry_t * entry) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _dess_port_vlan_trans_del(dev_id, port_id, entry); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Get a vlan translation entry from a particular port. - * @param[in] dev_id device id - * @param[in] port_id port id - * @param entry vlan translation entry - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -dess_port_vlan_trans_get(a_uint32_t dev_id, fal_port_t port_id, - fal_vlan_trans_entry_t * entry) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _dess_port_vlan_trans_get(dev_id, port_id, entry); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Iterate all vlan translation entries from a particular port. - * @param[in] dev_id device id - * @param[in] port_id port id - * @param[in] iterator translation entry index if it's zero means get the first entry - * @param[out] iterator next valid translation entry index - * @param[out] entry vlan translation entry - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -dess_port_vlan_trans_iterate(a_uint32_t dev_id, fal_port_t port_id, - a_uint32_t * iterator, - fal_vlan_trans_entry_t * entry) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _dess_port_vlan_trans_iterate(dev_id, port_id, iterator, entry); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Set switch qinq work mode on a particular device. - * @param[in] dev_id device id - * @param[in] mode qinq work mode - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -dess_qinq_mode_set(a_uint32_t dev_id, fal_qinq_mode_t mode) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _dess_qinq_mode_set(dev_id, mode); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Get switch qinq work mode on a particular device. - * @param[in] dev_id device id - * @param[out] mode qinq work mode - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -dess_qinq_mode_get(a_uint32_t dev_id, fal_qinq_mode_t * mode) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _dess_qinq_mode_get(dev_id, mode); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Set qinq role on a particular port. - * @param[in] dev_id device id - * @param[in] port_id port id - * @param[in] role port role - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -dess_port_qinq_role_set(a_uint32_t dev_id, fal_port_t port_id, - fal_qinq_port_role_t role) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _dess_port_qinq_role_set(dev_id, port_id, role); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Get qinq role on a particular port. - * @param[in] dev_id device id - * @param[in] port_id port id - * @param[out] role port role - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -dess_port_qinq_role_get(a_uint32_t dev_id, fal_port_t port_id, - fal_qinq_port_role_t * role) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _dess_port_qinq_role_get(dev_id, port_id, role); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Set MAC_VLAN_XLT status on a particular port. - * @param[in] dev_id device id - * @param[in] port_id port id - * @param[in] role port role - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -dess_port_mac_vlan_xlt_set(a_uint32_t dev_id, fal_port_t port_id, - a_bool_t enable) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _dess_port_mac_vlan_xlt_set(dev_id, port_id, enable); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Get MAC_VLAN_XLT status on a particular port. - * @param[in] dev_id device id - * @param[in] port_id port id - * @param[out] role port role - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -dess_port_mac_vlan_xlt_get(a_uint32_t dev_id, fal_port_t port_id, - a_bool_t * enable) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _dess_port_mac_vlan_xlt_get(dev_id, port_id, enable); - HSL_API_UNLOCK; - return rv; -} -#if 0 -HSL_LOCAL sw_error_t -dess_port_route_defv_set(a_uint32_t dev_id, fal_port_t port_id) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv =_dess_port_route_defv_set(dev_id, port_id); - HSL_API_UNLOCK; - return rv; -} -#endif -/** - * @brief Set NET_ISOLATE_EN - * @param[in] dev_id device id - * @param[in] role port role - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -dess_netisolate_set(a_uint32_t dev_id, a_bool_t enable) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _dess_netisolate_set(dev_id, enable); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Get NET_ISOLATE_EN status - * @param[in] dev_id device id - * @param[out] role port role - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -dess_netisolate_get(a_uint32_t dev_id, a_bool_t *enable) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _dess_netisolate_get(dev_id, enable); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Set egress translation filter bypass enable - * @param[in] dev_id device id - * @param[in] enable A_TRUE or A_FALSE - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -dess_eg_trans_filter_bypass_en_set(a_uint32_t dev_id, a_bool_t enable) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _dess_eg_trans_filter_bypass_en_set(dev_id, enable); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Get egress translation filter bypass enable - * @param[in] dev_id device id - * @param[in] enable A_TRUE or A_FALSE - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -dess_eg_trans_filter_bypass_en_get(a_uint32_t dev_id, a_bool_t* enable) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _dess_eg_trans_filter_bypass_en_get(dev_id, enable); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Set VRF id on a particular port. - * @param[in] dev_id device id - * @param[in] port_id port id - * @param[in] vrf_id VRF id - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -dess_port_vrf_id_set(a_uint32_t dev_id, fal_port_t port_id, - a_uint32_t vrf_id) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _dess_port_vrf_id_set(dev_id, port_id, vrf_id); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Get VRF id on a particular port. - * @param[in] dev_id device id - * @param[in] port_id port id - * @param[out] vrf_id VRF id - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -dess_port_vrf_id_get(a_uint32_t dev_id, fal_port_t port_id, - a_uint32_t * vrf_id) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _dess_port_vrf_id_get(dev_id, port_id, vrf_id); - HSL_API_UNLOCK; - return rv; -} - -sw_error_t -dess_portvlan_init(a_uint32_t dev_id) -{ - a_uint32_t i; - sw_error_t rv; - fal_vlan_trans_entry_t entry_init; - hsl_api_t *p_api; - - HSL_DEV_ID_CHECK(dev_id); - - aos_mem_set(&entry_init, 0, sizeof (fal_vlan_trans_entry_t)); - - for (i = 0; i < DESS_MAX_VLAN_TRANS; i++) - { - rv = _dess_vlan_trans_write(dev_id, i, 0, entry_init); - SW_RTN_ON_ERROR(rv); - } - -#ifndef HSL_STANDALONG - - SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id)); - - p_api->port_1qmode_get = dess_port_1qmode_get; - p_api->port_1qmode_set = dess_port_1qmode_set; - p_api->port_egvlanmode_get = dess_port_egvlanmode_get; - p_api->port_egvlanmode_set = dess_port_egvlanmode_set; - p_api->portvlan_member_add = dess_portvlan_member_add; - p_api->portvlan_member_del = dess_portvlan_member_del; - p_api->portvlan_member_update = dess_portvlan_member_update; - p_api->portvlan_member_get = dess_portvlan_member_get; - p_api->port_force_default_vid_set = dess_port_force_default_vid_set; - p_api->port_force_default_vid_get = dess_port_force_default_vid_get; - p_api->port_force_portvlan_set = dess_port_force_portvlan_set; - p_api->port_force_portvlan_get = dess_port_force_portvlan_get; - p_api->nestvlan_tpid_set = dess_nestvlan_tpid_set; - p_api->nestvlan_tpid_get = dess_nestvlan_tpid_get; - p_api->port_invlan_mode_set = dess_port_invlan_mode_set; - p_api->port_invlan_mode_get = dess_port_invlan_mode_get; - p_api->port_tls_set = dess_port_tls_set; - p_api->port_tls_get = dess_port_tls_get; - p_api->port_pri_propagation_set = dess_port_pri_propagation_set; - p_api->port_pri_propagation_get = dess_port_pri_propagation_get; - p_api->port_default_svid_set = dess_port_default_svid_set; - p_api->port_default_svid_get = dess_port_default_svid_get; - p_api->port_default_cvid_set = dess_port_default_cvid_set; - p_api->port_default_cvid_get = dess_port_default_cvid_get; - p_api->port_vlan_propagation_set = dess_port_vlan_propagation_set; - p_api->port_vlan_propagation_get = dess_port_vlan_propagation_get; - p_api->port_vlan_trans_add = dess_port_vlan_trans_add; - p_api->port_vlan_trans_del = dess_port_vlan_trans_del; - p_api->port_vlan_trans_get = dess_port_vlan_trans_get; - p_api->qinq_mode_set = dess_qinq_mode_set; - p_api->qinq_mode_get = dess_qinq_mode_get; - p_api->port_qinq_role_set = dess_port_qinq_role_set; - p_api->port_qinq_role_get = dess_port_qinq_role_get; - p_api->port_vlan_trans_iterate = dess_port_vlan_trans_iterate; - p_api->port_mac_vlan_xlt_set = dess_port_mac_vlan_xlt_set; - p_api->port_mac_vlan_xlt_get = dess_port_mac_vlan_xlt_get; - p_api->netisolate_set = dess_netisolate_set; - p_api->netisolate_get = dess_netisolate_get; - p_api->eg_trans_filter_bypass_en_set = dess_eg_trans_filter_bypass_en_set; - p_api->eg_trans_filter_bypass_en_get = dess_eg_trans_filter_bypass_en_get; - p_api->port_vrf_id_set = dess_port_vrf_id_set; - p_api->port_vrf_id_get = dess_port_vrf_id_get; -#endif - - return SW_OK; -} - -/** - * @} - */ diff --git a/feeds/ipq807x/qca-ssdk/src/src/hsl/dess/dess_psgmii.c b/feeds/ipq807x/qca-ssdk/src/src/hsl/dess/dess_psgmii.c deleted file mode 100755 index aab36d24e..000000000 --- a/feeds/ipq807x/qca-ssdk/src/src/hsl/dess/dess_psgmii.c +++ /dev/null @@ -1,722 +0,0 @@ -/* - * Copyright (c) 2015-2016, The Linux Foundation. All rights reserved. - * Permission to use, copy, modify, and/or distribute this software for - * any purpose with or without fee is hereby granted, provided that the - * above copyright notice and this permission notice appear in all copies. - * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES - * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR - * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES - * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN - * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT - * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. - */ - - - -#include "sw.h" -#include "fal_port_ctrl.h" -#include "hsl_api.h" -#include "hsl.h" -#include "sd.h" -#include "dess_psgmii.h" -#include "aos_timer.h" - -static psgmii_interface_mac_mode_t psgmii_mac_mode = {0}; -static a_uint32_t sgmii_ch_id = 0; - -sw_error_t -dess_psgmii_reg_get(a_uint32_t dev_id, a_uint32_t reg_addr, a_uint8_t value[], - a_uint32_t value_len) -{ - sw_error_t rv; - - rv = sd_reg_psgmii_get(dev_id, reg_addr, value, value_len); - return rv; -} - -sw_error_t -dess_psgmii_reg_set(a_uint32_t dev_id, a_uint32_t reg_addr, a_uint8_t value[], - a_uint32_t value_len) -{ - sw_error_t rv; - - rv = sd_reg_psgmii_set(dev_id, reg_addr, value, value_len); - return rv; -} - -sw_error_t -dess_psgmii_reg_field_get(a_uint32_t dev_id, a_uint32_t reg_addr, - a_uint32_t bit_offset, a_uint32_t field_len, - a_uint8_t value[], a_uint32_t value_len) -{ - a_uint32_t reg_val = 0; - - if ((bit_offset >= 32 || (field_len > 32)) || (field_len == 0)) - return SW_OUT_OF_RANGE; - - if (value_len != sizeof (a_uint32_t)) - return SW_BAD_LEN; - - SW_RTN_ON_ERROR(dess_psgmii_reg_get(dev_id, reg_addr, (a_uint8_t *) & reg_val, sizeof (a_uint32_t))); - - - if(32 == field_len) - { - *((a_uint32_t *) value) = reg_val; - } - else - { - *((a_uint32_t *) value) = SW_REG_2_FIELD(reg_val, bit_offset, field_len); - } - return SW_OK; -} - -sw_error_t -dess_psgmii_reg_field_set(a_uint32_t dev_id, a_uint32_t reg_addr, - a_uint32_t bit_offset, a_uint32_t field_len, - const a_uint8_t value[], a_uint32_t value_len) -{ - a_uint32_t reg_val = 0; - a_uint32_t field_val = *((a_uint32_t *) value); - - if ((bit_offset >= 32 || (field_len > 32)) || (field_len == 0)) - return SW_OUT_OF_RANGE; - - if (value_len != sizeof (a_uint32_t)) - return SW_BAD_LEN; - - SW_RTN_ON_ERROR(dess_psgmii_reg_get(dev_id, reg_addr, (a_uint8_t *) & reg_val, sizeof (a_uint32_t))); - - if(32 == field_len) - { - reg_val = field_val; - } - else - { - SW_REG_SET_BY_FIELD_U32(reg_val, field_val, bit_offset, field_len); - } - - SW_RTN_ON_ERROR(dess_psgmii_reg_set(dev_id, reg_addr, (a_uint8_t *) & reg_val, sizeof (a_uint32_t))); - - return SW_OK; -} - - -/****************************************************************************** -* -* psgmii_set_powersave - set power saving status -* -* set power saving status -*/ -sw_error_t -dess_psgmii_set_lpi(a_uint32_t dev_id, a_uint32_t phy_id, a_bool_t enable) -{ - sw_error_t rv; - a_uint32_t data = 0; - - if (phy_id == 0) - { - rv = dess_psgmii_reg_get(dev_id, PSGMIIPHY_EEE_CH0_5, - (a_uint8_t *) (&data), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - } - else - { - rv = dess_psgmii_reg_get(dev_id, PSGMIIPHY_EEE_CH1_1 + phy_id * 0xc, - (a_uint8_t *) (&data), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - } - - if (enable) - { - data &= ~(PSGMIIPHY_EEE_DIS_LPI); - data |= PSGMIIPHY_EEE_EN_LPI; - } - else - { - data |= PSGMIIPHY_EEE_DIS_LPI; - data &= ~(PSGMIIPHY_EEE_EN_LPI); - } - - if (phy_id == 0) - { - rv = dess_psgmii_reg_set(dev_id, PSGMIIPHY_EEE_CH0_5, - (a_uint8_t *) (&data), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - } - else - { - rv = dess_psgmii_reg_set(dev_id, PSGMIIPHY_EEE_CH1_1 + phy_id * 0xc, - (a_uint8_t *) (&data), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - } - - return SW_OK; -} - -/****************************************************************************** -* -*psgmii_get_powersave - get power saving status -* -* set power saving status -*/ -sw_error_t -dess_psgmii_get_lpi(a_uint32_t dev_id, a_uint32_t phy_id, a_bool_t *enable) -{ - sw_error_t rv; - a_uint32_t data = 0; - - if (phy_id == 0) - { - rv = dess_psgmii_reg_get(dev_id, PSGMIIPHY_EEE_CH0_5, - (a_uint8_t *) (&data), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - } - else - { - rv = dess_psgmii_reg_get(dev_id, PSGMIIPHY_EEE_CH1_1 + phy_id * 0xc, - (a_uint8_t *) (&data), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - } - - if (!(data & PSGMIIPHY_EEE_DIS_LPI) && (data & PSGMIIPHY_EEE_EN_LPI)) - { - *enable = A_TRUE; - } - else - { - *enable = A_FALSE; - } - - return SW_OK; -} - -/****************************************************************************** -* -*psgmii_set_hibernate - set hibernate status -* -* set hibernate status -*/ -sw_error_t -dess_psgmii_set_interface_type(a_uint32_t dev_id, a_uint32_t phy_id, - psgmii_interface_mac_mode_t mode) -{ - sw_error_t rv; - a_uint32_t data = 0; - - rv = dess_psgmii_reg_get(dev_id, PSGMIIPHY_MODE_CONTROL, - (a_uint8_t *) (&data), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - - switch(mode) - { - case PSGMII_MAC_MODE_PSGMII: - { - data |= PSGMIIPHY_MODE_CH0_PSGMII_QSGMII; - data &= (~PSGMIIPHY_MODE_CH0_QSGMII_SGMII); - data &= (~PSGMIIPHY_MODE_CH4_CH1_0_SGMII); - data &= (~PSGMIIPHY_MODE_CH1_CH0_SGMII); - break; - } - case PSGMII_MAC_MODE_QSGMII: - { - data &= (~PSGMIIPHY_MODE_CH0_PSGMII_QSGMII); - data |= PSGMIIPHY_MODE_CH0_QSGMII_SGMII; - if (phy_id == 0) - { - data &= (~PSGMIIPHY_MODE_CH4_CH1_0_SGMII); - data &= (~PSGMIIPHY_MODE_CH1_CH0_SGMII); - } - else if (phy_id == 1) - { - data &= (~PSGMIIPHY_MODE_CH4_CH1_0_SGMII); - data |= PSGMIIPHY_MODE_CH1_CH0_SGMII; - } - else if (phy_id == 4) - { - data |= PSGMIIPHY_MODE_CH4_CH1_0_SGMII; - data &= (~PSGMIIPHY_MODE_CH1_CH0_SGMII); - } - else - { - return SW_NOT_SUPPORTED; - } - - break; - } - case PSGMII_MAC_MODE_SGMII: - { - data &= (~PSGMIIPHY_MODE_CH0_PSGMII_QSGMII); - data &= (~PSGMIIPHY_MODE_CH0_QSGMII_SGMII); - if (phy_id == 0) - { - data &= (~PSGMIIPHY_MODE_CH4_CH1_0_SGMII); - data &= (~PSGMIIPHY_MODE_CH1_CH0_SGMII); - } - else if (phy_id == 1) - { - data &= (~PSGMIIPHY_MODE_CH4_CH1_0_SGMII); - data |= PSGMIIPHY_MODE_CH1_CH0_SGMII; - } - else if (phy_id == 4) - { - data |= PSGMIIPHY_MODE_CH4_CH1_0_SGMII; - data &= (~PSGMIIPHY_MODE_CH1_CH0_SGMII); - } - else - { - return SW_NOT_SUPPORTED; - } - - break; - } - default: - break; - } - - rv = dess_psgmii_reg_set(dev_id, PSGMIIPHY_MODE_CONTROL, - (a_uint8_t *) (&data), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - - psgmii_mac_mode = mode; - sgmii_ch_id = phy_id; - - return SW_OK; -} - -/****************************************************************************** -* -* psgmii_get_hibernate - get hibernate status -* -* get hibernate status -*/ -sw_error_t -dess_psgmii_get_interface_type(a_uint32_t dev_id, a_uint32_t * phy_id, - psgmii_interface_mac_mode_t * mode) -{ - *phy_id = sgmii_ch_id; - *mode = psgmii_mac_mode; - - return SW_OK; -} - -/****************************************************************************** -* -* psgmii_autoneg_done -* -*psgmii_autoneg_done -*/ -a_bool_t -dess_psgmii_autoneg_done(a_uint32_t dev_id, a_uint32_t phy_id) -{ - sw_error_t rv; - a_uint32_t data = 0; - - rv = dess_psgmii_reg_get(dev_id, PSGMIIPHY_CHANNEL_0_INPUT_OUTPUT_1 + phy_id * 0x18, - (a_uint8_t *) (&data), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - - if (data & PSGMIIPHY_CHANNEL_0_INPUT_OUTPUT_1_MR_AN_COMPLETE) - return A_TRUE; - else - return A_FALSE; - - return A_TRUE; -} - -/****************************************************************************** -* -*psgmii_reset - reset the psgmii -* -* reset the psgmii -*/ -sw_error_t -dess_psgmii_reset(a_uint32_t dev_id, a_uint32_t phy_id) -{ - sw_error_t rv; - a_uint32_t data = 0; - - rv = dess_psgmii_reg_get(dev_id, PSGMIIPHY_CHANNEL_0_INPUT_OUTPUT_4 + phy_id * 0x18, - (a_uint8_t *) (&data), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - - data |= PSGMIIPHY_CHANNEL_0_INPUT_OUTPUT_4_MR_MAIN_RESET_25M; - - rv = dess_psgmii_reg_set(dev_id, PSGMIIPHY_CHANNEL_0_INPUT_OUTPUT_4 + phy_id * 0x18, - (a_uint8_t *) (&data), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - - return SW_OK; -} - -/****************************************************************************** -* -* psgmii_off - power off the psgmii to change its speed -* -* Power off the psgmii -*/ -sw_error_t -dess_psgmii_poweroff(a_uint32_t dev_id, a_uint32_t phy_id) -{ - sw_error_t rv; - a_uint32_t data = 0; - - rv = dess_psgmii_reg_get(dev_id, PSGMIIPHY_CHANNEL_0_INPUT_OUTPUT_4 + phy_id * 0x18, - (a_uint8_t *) (&data), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - - data &= (~PSGMIIPHY_CHANNEL_0_INPUT_OUTPUT_4_POWER_ON_25M); - - rv = dess_psgmii_reg_set(dev_id, PSGMIIPHY_CHANNEL_0_INPUT_OUTPUT_4 + phy_id * 0x18, - (a_uint8_t *) (&data), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - - return SW_OK; -} - -/****************************************************************************** -* -* psgmii_on - power on the psgmii after speed changed -* -* Power on the psgmii -*/ -sw_error_t -dess_psgmii_poweron(a_uint32_t dev_id, a_uint32_t phy_id) -{ - sw_error_t rv; - a_uint32_t data = 0; - - rv = dess_psgmii_reg_get(dev_id, PSGMIIPHY_CHANNEL_0_INPUT_OUTPUT_4 + phy_id * 0x18, - (a_uint8_t *) (&data), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - - data |= PSGMIIPHY_CHANNEL_0_INPUT_OUTPUT_4_POWER_ON_25M; - - rv = dess_psgmii_reg_set(dev_id, PSGMIIPHY_CHANNEL_0_INPUT_OUTPUT_4 + phy_id * 0x18, - (a_uint8_t *) (&data), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - - return SW_OK; -} - -/****************************************************************************** -* -* psgmii_status - test to see if the specified psgmii link is alive -* -* RETURNS: -* A_TRUE --> link is alive -* A_FALSE --> link is down -*/ -a_bool_t -dess_psgmii_get_link_status(a_uint32_t dev_id, a_uint32_t phy_id) -{ - sw_error_t rv; - a_uint32_t data = 0; - - rv = dess_psgmii_reg_get(dev_id, PSGMIIPHY_CHANNEL_0_INPUT_OUTPUT_5 + phy_id * 0x18, - (a_uint8_t *) (&data), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - - if (data & PSGMIIPHY_CHANNEL_0_INPUT_OUTPUT_5_LINK_25M) - return A_TRUE; - else - return A_FALSE; - - return SW_OK; -} - -/****************************************************************************** -* -* psgmii_set_loopback - set the psgmii loopback -* -*/ -sw_error_t -dess_psgmii_set_loopback(a_uint32_t dev_id, a_uint32_t phy_id, - a_bool_t enable) -{ - sw_error_t rv; - a_uint32_t data = 0; - - rv = dess_psgmii_reg_get(dev_id, PSGMIIPHY_CHANNEL_0_INPUT_OUTPUT_4 + phy_id * 0x18, - (a_uint8_t *) (&data), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - - if (enable) - data |= PSGMIIPHY_CHANNEL_0_INPUT_OUTPUT_4_MR_MR_LOOPBACK_25M; - else - data &= (~PSGMIIPHY_CHANNEL_0_INPUT_OUTPUT_4_MR_MR_LOOPBACK_25M); - - rv = dess_psgmii_reg_set(dev_id, PSGMIIPHY_CHANNEL_0_INPUT_OUTPUT_4 + phy_id * 0x18, - (a_uint8_t *) (&data), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - - return SW_OK; -} - -/****************************************************************************** -* -* psgmii_get_loopback - get the psgmii loopback -* -*/ -sw_error_t -dess_psgmii_get_loopback(a_uint32_t dev_id, a_uint32_t phy_id, - a_bool_t * enable) -{ - sw_error_t rv; - a_uint32_t data = 0; - - rv = dess_psgmii_reg_get(dev_id, PSGMIIPHY_CHANNEL_0_INPUT_OUTPUT_4 + phy_id * 0x18, - (a_uint8_t *) (&data), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - - if (data & PSGMIIPHY_CHANNEL_0_INPUT_OUTPUT_4_MR_MR_LOOPBACK_25M) - *enable = A_TRUE; - else - *enable = A_FALSE; - - return SW_OK; -} - -/****************************************************************************** -* -* psgmii_enable_autonego - power off the psgmii to change its speed -* -* Power off the phy -*/ -a_bool_t -dess_psgmii_autoneg_status(a_uint32_t dev_id, a_uint32_t phy_id) -{ - - return A_FALSE; -} - -/****************************************************************************** -* -* psgmii_restart_autoneg - restart the psgmii autoneg -* -*/ -sw_error_t -dess_psgmii_restart_autoneg(a_uint32_t dev_id, a_uint32_t phy_id) -{ - sw_error_t rv; - a_uint32_t data = 0; - - rv = dess_psgmii_reg_get(dev_id, PSGMIIPHY_CHANNEL_0_INPUT_OUTPUT_4 + phy_id * 0x18, - (a_uint8_t *) (&data), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - - data |= PSGMIIPHY_CHANNEL_0_INPUT_OUTPUT_4_MR_RESTART_AN_25M; - - rv = dess_psgmii_reg_set(dev_id, PSGMIIPHY_CHANNEL_0_INPUT_OUTPUT_4 + phy_id * 0x18, - (a_uint8_t *) (&data), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - - return SW_OK; -} - -/****************************************************************************** -* -* psgmii_enable_autonego - power off the psgmii to change its speed -* -* Power off the phy -*/ -sw_error_t -dess_psgmii_enable_autoneg(a_uint32_t dev_id, a_uint32_t phy_id) -{ - sw_error_t rv; - a_uint32_t data = 0; - - rv = dess_psgmii_reg_get(dev_id, PSGMIIPHY_CHANNEL_0_INPUT_OUTPUT_4 + phy_id * 0x18, - (a_uint8_t *) (&data), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - - data |= PSGMIIPHY_CHANNEL_0_INPUT_OUTPUT_4_MR_AN_ENABLE_25M; - - rv = dess_psgmii_reg_set(dev_id, PSGMIIPHY_CHANNEL_0_INPUT_OUTPUT_4 + phy_id * 0x18, - (a_uint8_t *) (&data), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - - return SW_OK; -} - - -/****************************************************************************** -* -* psgmii_get_speed - Determines the speed of psgmii ports associated with the -* specified device. -*/ - -sw_error_t -dess_psgmii_get_speed(a_uint32_t dev_id, a_uint32_t phy_id, - fal_port_speed_t * speed) -{ - sw_error_t rv; - a_uint32_t data = 0; - - rv = dess_psgmii_reg_get(dev_id, PSGMIIPHY_CHANNEL_0_INPUT_OUTPUT_4 + phy_id * 0x18, - (a_uint8_t *) (&data), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - - /*Force speed mode*/ - if (data & PSGMIIPHY_CHANNEL_0_INPUT_OUTPUT_4_FORCE_SPEED_25M) - { - switch (data & PSGMIIPHY_CHANNEL_3_INPUT_OUTPUT_4_SPEED_25M_MASK) - { - case PSGMIIPHY_CHANNEL_3_INPUT_OUTPUT_4_SPEED_25M_1000M: - *speed = FAL_SPEED_1000; - break; - case PSGMIIPHY_CHANNEL_3_INPUT_OUTPUT_4_SPEED_25M_100M: - *speed = FAL_SPEED_100; - break; - case PSGMIIPHY_CHANNEL_3_INPUT_OUTPUT_4_SPEED_25M_10M: - *speed = FAL_SPEED_10; - break; - default: - return SW_READ_ERROR; - } - } - else - { - rv = dess_psgmii_reg_get(dev_id, PSGMIIPHY_CHANNEL_0_INPUT_OUTPUT_5 + phy_id * 0x18, - (a_uint8_t *) (&data), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - switch (data & PSGMIIPHY_CHANNEL_3_INPUT_OUTPUT_5_SPEED_MODE_25M) - { - case PSGMIIPHY_CHANNEL_3_INPUT_OUTPUT_5_SPEED_25M_1000M: - *speed = FAL_SPEED_1000; - break; - case PSGMIIPHY_CHANNEL_3_INPUT_OUTPUT_5_SPEED_25M_100M: - *speed = FAL_SPEED_100; - break; - case PSGMIIPHY_CHANNEL_3_INPUT_OUTPUT_5_SPEED_25M_10M: - *speed = FAL_SPEED_10; - break; - default: - return SW_READ_ERROR; - } - } - - return SW_OK; -} - -/****************************************************************************** -* -* psgmii_set_speed - Determines the speed of psgmii ports associated with the -* specified device. -*/ -sw_error_t -dess_psgmii_set_speed(a_uint32_t dev_id, a_uint32_t phy_id, - fal_port_speed_t speed) -{ - sw_error_t rv; - a_uint32_t data = 0; - - rv = dess_psgmii_reg_get(dev_id, PSGMIIPHY_CHANNEL_0_INPUT_OUTPUT_4 + phy_id * 0x18, - (a_uint8_t *) (&data), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - - data |= PSGMIIPHY_CHANNEL_0_INPUT_OUTPUT_4_FORCE_SPEED_25M; - data &= ~(PSGMIIPHY_CHANNEL_3_INPUT_OUTPUT_4_SPEED_25M_MASK); - - if (FAL_SPEED_1000 == speed) - { - data |= PSGMIIPHY_CHANNEL_3_INPUT_OUTPUT_4_SPEED_25M_1000M; - } - else if (FAL_SPEED_100 == speed) - { - data |= PSGMIIPHY_CHANNEL_3_INPUT_OUTPUT_4_SPEED_25M_100M; - } - else if (FAL_SPEED_10 == speed) - { - data |= PSGMIIPHY_CHANNEL_3_INPUT_OUTPUT_4_SPEED_25M_10M; - } - else - { - return SW_BAD_PARAM; - } - - rv = dess_psgmii_reg_set(dev_id, PSGMIIPHY_CHANNEL_0_INPUT_OUTPUT_4 + phy_id * 0x18, - (a_uint8_t *) (&data), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - - return SW_OK; - -} - -/****************************************************************************** -* -* psgmii_get_duplex - Determines the speed of psgmii ports associated with the -* specified device. -*/ -sw_error_t -dess_psgmii_get_duplex(a_uint32_t dev_id, a_uint32_t phy_id, - fal_port_duplex_t * duplex) -{ - sw_error_t rv; - a_uint32_t data = 0; - - rv = dess_psgmii_reg_get(dev_id, PSGMIIPHY_CHANNEL_0_INPUT_OUTPUT_5 + phy_id * 0x18, - (a_uint8_t *) (&data), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - - /*Force speed mode*/ - if (data & PSGMIIPHY_CHANNEL_0_INPUT_OUTPUT_5_DUPLEX_MODE_25M) - { - *duplex = FAL_FULL_DUPLEX; - } - else - { - *duplex = FAL_HALF_DUPLEX; - } - - - return SW_OK; -} - -/****************************************************************************** -* -*psgmii_set_duplex - Determines the speed of psgmii ports associated with the -* specified device. -*/ -sw_error_t -dess_psgmii_set_duplex(a_uint32_t dev_id, a_uint32_t phy_id, - fal_port_duplex_t duplex) -{ - sw_error_t rv; - a_uint32_t data = 0; - - rv = dess_psgmii_reg_get(dev_id, PSGMIIPHY_CHANNEL_0_INPUT_OUTPUT_5 + phy_id * 0x18, - (a_uint8_t *) (&data), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - - if (FAL_FULL_DUPLEX == duplex) - { - data |= PSGMIIPHY_CHANNEL_0_INPUT_OUTPUT_5_FULL_DUPLEX_25M; - data &= (~PSGMIIPHY_CHANNEL_0_INPUT_OUTPUT_5_HALF_DUPLEX_25M); - } - else - { - data |= PSGMIIPHY_CHANNEL_0_INPUT_OUTPUT_5_HALF_DUPLEX_25M; - data &= (~PSGMIIPHY_CHANNEL_0_INPUT_OUTPUT_5_FULL_DUPLEX_25M); - } - - rv = dess_psgmii_reg_set(dev_id, PSGMIIPHY_CHANNEL_0_INPUT_OUTPUT_5 + phy_id * 0x18, - (a_uint8_t *) (&data), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - - return SW_OK; -} - -/****************************************************************************** -* -* psgmii_init - -* -*/ -a_bool_t -dess_psgmii_init(a_uint32_t dev_id, a_uint32_t phy_id, - a_uint16_t org_id, a_uint16_t rev_id) -{ - - return SW_OK; -} diff --git a/feeds/ipq807x/qca-ssdk/src/src/hsl/dess/dess_qos.c b/feeds/ipq807x/qca-ssdk/src/src/hsl/dess/dess_qos.c deleted file mode 100755 index 80039f5b2..000000000 --- a/feeds/ipq807x/qca-ssdk/src/src/hsl/dess/dess_qos.c +++ /dev/null @@ -1,1562 +0,0 @@ -/* - * Copyright (c) 2014, 2016, The Linux Foundation. All rights reserved. - * Permission to use, copy, modify, and/or distribute this software for - * any purpose with or without fee is hereby granted, provided that the - * above copyright notice and this permission notice appear in all copies. - * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES - * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR - * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES - * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN - * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT - * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. - */ - - -/** - * @defgroup dess_qos DESS_QOS - * @{ - */ -#include "sw.h" -#include "hsl.h" -#include "hsl_dev.h" -#include "hsl_port_prop.h" -#include "dess_qos.h" -#include "dess_reg.h" - -#define DESS_QOS_QUEUE_TX_BUFFER_MAX 120 -#define DESS_QOS_PORT_TX_BUFFER_MAX 504 -#define DESS_QOS_PORT_RX_BUFFER_MAX 120 - -#define DESS_QOS_HOL_STEP 8 -#define DESS_QOS_HOL_MOD 3 - -//#define DESS_MIN_QOS_MODE_PRI 0 -#define DESS_MAX_QOS_MODE_PRI 3 -#define DESS_MAX_PRI 7 -#define DESS_MAX_QUEUE 3 -#define DESS_MAX_EH_QUEUE 5 - -static sw_error_t -_dess_qos_queue_tx_buf_status_set(a_uint32_t dev_id, fal_port_t port_id, - a_bool_t enable) -{ - a_uint32_t val = 0; - sw_error_t rv; - - if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU)) - { - return SW_BAD_PARAM; - } - - if (A_TRUE == enable) - { - val = 1; - } - else if (A_FALSE == enable) - { - val = 0; - } - else - { - return SW_BAD_PARAM; - } - - HSL_REG_FIELD_SET(rv, dev_id, PORT_HOL_CTL1, port_id, QUEUE_DESC_EN, - (a_uint8_t *) (&val), sizeof (a_uint32_t)); - return rv; -} - -static sw_error_t -_dess_qos_queue_tx_buf_status_get(a_uint32_t dev_id, fal_port_t port_id, - a_bool_t * enable) -{ - a_uint32_t val = 0; - sw_error_t rv; - - if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU)) - { - return SW_BAD_PARAM; - } - - HSL_REG_FIELD_GET(rv, dev_id, PORT_HOL_CTL1, port_id, QUEUE_DESC_EN, - (a_uint8_t *) (&val), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - - if (1 == val) - { - *enable = A_TRUE; - } - else - { - *enable = A_FALSE; - } - - return SW_OK; -} - -static sw_error_t -_dess_qos_port_tx_buf_status_set(a_uint32_t dev_id, fal_port_t port_id, - a_bool_t enable) -{ - a_uint32_t val = 0; - sw_error_t rv; - - if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU)) - { - return SW_BAD_PARAM; - } - - if (A_TRUE == enable) - { - val = 1; - } - else if (A_FALSE == enable) - { - val = 0; - } - else - { - return SW_BAD_PARAM; - } - - HSL_REG_FIELD_SET(rv, dev_id, PORT_HOL_CTL1, port_id, PORT_DESC_EN, - (a_uint8_t *) (&val), sizeof (a_uint32_t)); - return rv; -} - -static sw_error_t -_dess_qos_port_tx_buf_status_get(a_uint32_t dev_id, fal_port_t port_id, - a_bool_t * enable) -{ - a_uint32_t val = 0; - sw_error_t rv; - - if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU)) - { - return SW_BAD_PARAM; - } - - HSL_REG_FIELD_GET(rv, dev_id, PORT_HOL_CTL1, port_id, PORT_DESC_EN, - (a_uint8_t *) (&val), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - - if (1 == val) - { - *enable = A_TRUE; - } - else - { - *enable = A_FALSE; - } - - return SW_OK; -} - -static sw_error_t -_dess_qos_port_red_en_set(a_uint32_t dev_id, fal_port_t port_id, - a_bool_t enable) -{ - a_uint32_t val = 0; - sw_error_t rv; - - if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU)) - { - return SW_BAD_PARAM; - } - if (A_TRUE == enable) - { - val = 1; - } - else if (A_FALSE == enable) - { - val = 0; - } - else - { - return SW_BAD_PARAM; - } - - HSL_REG_FIELD_SET(rv, dev_id, PORT_HOL_CTL1, port_id, PORT_RED_EN, - (a_uint8_t *) (&val), sizeof (a_uint32_t)); - return rv; -} - - - -static sw_error_t -_dess_qos_port_red_en_get(a_uint32_t dev_id, fal_port_t port_id, - a_bool_t * enable) -{ - a_uint32_t val = 0; - sw_error_t rv; - - if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU)) - { - return SW_BAD_PARAM; - } - - HSL_REG_FIELD_GET(rv, dev_id, PORT_HOL_CTL1, port_id, PORT_RED_EN, - (a_uint8_t *) (&val), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - - if (1 == val) - { - *enable = A_TRUE; - } - else - { - *enable = A_FALSE; - } - - return SW_OK; -} - - - -static sw_error_t -_dess_qos_port_queue_check(fal_port_t port_id, fal_queue_t queue_id) -{ - if ((0 == port_id) || (5 == port_id) || (6 == port_id)) - { - if (DESS_MAX_EH_QUEUE < queue_id) - { - return SW_BAD_PARAM; - } - } - else - { - if (DESS_MAX_QUEUE < queue_id) - { - return SW_BAD_PARAM; - } - } - - return SW_OK; -} - -static sw_error_t -_dess_qos_queue_tx_buf_nr_set(a_uint32_t dev_id, fal_port_t port_id, - fal_queue_t queue_id, a_uint32_t * number) -{ - a_uint32_t data = 0, val = 0; - sw_error_t rv; - - if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU)) - { - return SW_BAD_PARAM; - } - - if (DESS_QOS_QUEUE_TX_BUFFER_MAX < *number) - { - return SW_BAD_PARAM; - } - - rv = _dess_qos_port_queue_check(port_id, queue_id); - SW_RTN_ON_ERROR(rv); - - val = *number / DESS_QOS_HOL_STEP; - *number = val << DESS_QOS_HOL_MOD; - - HSL_REG_ENTRY_GET(rv, dev_id, PORT_HOL_CTL0, port_id, (a_uint8_t *) (&data), - sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - - data &= (~(0xf << (queue_id << 2))); - data |= (val << (queue_id << 2)); - - HSL_REG_ENTRY_SET(rv, dev_id, PORT_HOL_CTL0, port_id, (a_uint8_t *) (&data), - sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - - return rv; -} - -static sw_error_t -_dess_qos_queue_tx_buf_nr_get(a_uint32_t dev_id, fal_port_t port_id, - fal_queue_t queue_id, a_uint32_t * number) -{ - a_uint32_t data = 0, val = 0; - sw_error_t rv; - - if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU)) - { - return SW_BAD_PARAM; - } - - rv = _dess_qos_port_queue_check(port_id, queue_id); - SW_RTN_ON_ERROR(rv); - - HSL_REG_ENTRY_GET(rv, dev_id, PORT_HOL_CTL0, port_id, (a_uint8_t *) (&data), - sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - - val = (data >> (queue_id << 2)) & 0xf; - *number = val << DESS_QOS_HOL_MOD; - return SW_OK; -} - -static sw_error_t -_dess_qos_port_tx_buf_nr_set(a_uint32_t dev_id, fal_port_t port_id, - a_uint32_t * number) -{ - a_uint32_t val = 0; - sw_error_t rv; - - if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU)) - { - return SW_BAD_PARAM; - } - - if (DESS_QOS_PORT_TX_BUFFER_MAX < *number) - { - return SW_BAD_PARAM; - } - - val = *number / DESS_QOS_HOL_STEP; - *number = val << DESS_QOS_HOL_MOD; - HSL_REG_FIELD_SET(rv, dev_id, PORT_HOL_CTL0, port_id, PORT_DESC_NR, - (a_uint8_t *) (&val), sizeof (a_uint32_t)); - return rv; -} - -static sw_error_t -_dess_qos_port_tx_buf_nr_get(a_uint32_t dev_id, fal_port_t port_id, - a_uint32_t * number) -{ - a_uint32_t val = 0; - sw_error_t rv; - - if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU)) - { - return SW_BAD_PARAM; - } - - HSL_REG_FIELD_GET(rv, dev_id, PORT_HOL_CTL0, port_id, PORT_DESC_NR, - (a_uint8_t *) (&val), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - - *number = val << DESS_QOS_HOL_MOD; - return SW_OK; -} - -static sw_error_t -_dess_qos_port_rx_buf_nr_set(a_uint32_t dev_id, fal_port_t port_id, - a_uint32_t * number) -{ - a_uint32_t val = 0; - sw_error_t rv; - - if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU)) - { - return SW_BAD_PARAM; - } - - if (DESS_QOS_PORT_RX_BUFFER_MAX < *number) - { - return SW_BAD_PARAM; - } - - val = *number / DESS_QOS_HOL_STEP; - *number = val << DESS_QOS_HOL_MOD; - HSL_REG_FIELD_SET(rv, dev_id, PORT_HOL_CTL1, port_id, PORT_IN_DESC_EN, - (a_uint8_t *) (&val), sizeof (a_uint32_t)); - return rv; -} - -static sw_error_t -_dess_qos_port_rx_buf_nr_get(a_uint32_t dev_id, fal_port_t port_id, - a_uint32_t * number) -{ - a_uint32_t val = 0; - sw_error_t rv; - - if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU)) - { - return SW_BAD_PARAM; - } - - HSL_REG_FIELD_GET(rv, dev_id, PORT_HOL_CTL1, port_id, PORT_IN_DESC_EN, - (a_uint8_t *) (&val), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - - *number = val << DESS_QOS_HOL_MOD; - return SW_OK; -} - -static sw_error_t -_dess_qos_port_mode_set(a_uint32_t dev_id, fal_port_t port_id, - fal_qos_mode_t mode, a_bool_t enable) -{ - sw_error_t rv; - a_uint32_t val; - - HSL_DEV_ID_CHECK(dev_id); - - if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU)) - { - return SW_BAD_PARAM; - } - - if (A_TRUE == enable) - { - val = 1; - } - else if (A_FALSE == enable) - { - val = 0; - } - else - { - return SW_BAD_PARAM; - } - - if (FAL_QOS_DA_MODE == mode) - { - HSL_REG_FIELD_SET(rv, dev_id, PRI_CTL, port_id, DA_PRI_EN, - (a_uint8_t *) (&val), sizeof (a_uint32_t)); - } - else if (FAL_QOS_UP_MODE == mode) - { - HSL_REG_FIELD_SET(rv, dev_id, PRI_CTL, port_id, VLAN_PRI_EN, - (a_uint8_t *) (&val), sizeof (a_uint32_t)); - } - else if (FAL_QOS_DSCP_MODE == mode) - { - HSL_REG_FIELD_SET(rv, dev_id, PRI_CTL, port_id, IP_PRI_EN, - (a_uint8_t *) (&val), sizeof (a_uint32_t)); - } - else if (FAL_QOS_FLOW_MODE == mode) - { - HSL_REG_FIELD_SET(rv, dev_id, PRI_CTL, port_id, FLOW_PRI_EN, - (a_uint8_t *) (&val), sizeof (a_uint32_t)); - } - else - { - return SW_BAD_PARAM; - } - - return rv; -} - -static sw_error_t -_dess_qos_port_mode_get(a_uint32_t dev_id, fal_port_t port_id, - fal_qos_mode_t mode, a_bool_t * enable) -{ - sw_error_t rv; - a_uint32_t val = 0; - - HSL_DEV_ID_CHECK(dev_id); - - if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU)) - { - return SW_BAD_PARAM; - } - - if (FAL_QOS_DA_MODE == mode) - { - HSL_REG_FIELD_GET(rv, dev_id, PRI_CTL, port_id, DA_PRI_EN, - (a_uint8_t *) (&val), sizeof (a_uint32_t)); - } - else if (FAL_QOS_UP_MODE == mode) - { - HSL_REG_FIELD_GET(rv, dev_id, PRI_CTL, port_id, VLAN_PRI_EN, - (a_uint8_t *) (&val), sizeof (a_uint32_t)); - } - else if (FAL_QOS_DSCP_MODE == mode) - { - HSL_REG_FIELD_GET(rv, dev_id, PRI_CTL, port_id, IP_PRI_EN, - (a_uint8_t *) (&val), sizeof (a_uint32_t)); - } - else if (FAL_QOS_FLOW_MODE == mode) - { - HSL_REG_FIELD_GET(rv, dev_id, PRI_CTL, port_id, FLOW_PRI_EN, - (a_uint8_t *) (&val), sizeof (a_uint32_t)); - } - else - { - return SW_BAD_PARAM; - } - SW_RTN_ON_ERROR(rv); - - if (1 == val) - { - *enable = A_TRUE; - } - else - { - *enable = A_FALSE; - } - - return SW_OK; -} - -static sw_error_t -_dess_qos_port_mode_pri_set(a_uint32_t dev_id, fal_port_t port_id, - fal_qos_mode_t mode, a_uint32_t pri) -{ - sw_error_t rv; - a_uint32_t val = 0; - - HSL_DEV_ID_CHECK(dev_id); - - if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU)) - { - return SW_BAD_PARAM; - } - - if (DESS_MAX_QOS_MODE_PRI < pri) - { - return SW_BAD_PARAM; - } - - HSL_REG_ENTRY_GET(rv, dev_id, PRI_CTL, port_id, (a_uint8_t *) (&val), - sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - - if (FAL_QOS_DA_MODE == mode) - { - SW_SET_REG_BY_FIELD(PRI_CTL, DA_PRI_SEL, pri, val); - } - else if (FAL_QOS_UP_MODE == mode) - { - SW_SET_REG_BY_FIELD(PRI_CTL, VLAN_PRI_SEL, pri, val); - } - else if (FAL_QOS_DSCP_MODE == mode) - { - SW_SET_REG_BY_FIELD(PRI_CTL, IP_PRI_SEL, pri, val); - } - else if (FAL_QOS_FLOW_MODE == mode) - { - SW_SET_REG_BY_FIELD(PRI_CTL, FLOW_PRI_SEL, pri, val); - } - else - { - return SW_NOT_SUPPORTED; - } - - HSL_REG_ENTRY_SET(rv, dev_id, PRI_CTL, port_id, (a_uint8_t *) (&val), - sizeof (a_uint32_t)); - return rv; -} - -static sw_error_t -_dess_qos_port_mode_pri_get(a_uint32_t dev_id, fal_port_t port_id, - fal_qos_mode_t mode, a_uint32_t * pri) -{ - sw_error_t rv; - a_uint32_t entry = 0, f_val; - - HSL_DEV_ID_CHECK(dev_id); - - if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU)) - { - return SW_BAD_PARAM; - } - - HSL_REG_ENTRY_GET(rv, dev_id, PRI_CTL, port_id, (a_uint8_t *) (&entry), - sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - - if (FAL_QOS_DA_MODE == mode) - { - SW_GET_FIELD_BY_REG(PRI_CTL, DA_PRI_SEL, f_val, entry); - } - else if (FAL_QOS_UP_MODE == mode) - { - SW_GET_FIELD_BY_REG(PRI_CTL, VLAN_PRI_SEL, f_val, entry); - } - else if (FAL_QOS_DSCP_MODE == mode) - { - SW_GET_FIELD_BY_REG(PRI_CTL, IP_PRI_SEL, f_val, entry); - } - else if (FAL_QOS_FLOW_MODE == mode) - { - SW_GET_FIELD_BY_REG(PRI_CTL, FLOW_PRI_SEL, f_val, entry); - } - else - { - return SW_NOT_SUPPORTED; - } - - *pri = f_val; - return SW_OK; -} - -static sw_error_t -_dess_qos_port_sch_mode_set(a_uint32_t dev_id, a_uint32_t port_id, - fal_sch_mode_t mode, const a_uint32_t weight[]) -{ - sw_error_t rv; - a_uint32_t reg = 0, val, w[6] = { 0 }; - a_int32_t i, _index; - - HSL_DEV_ID_CHECK(dev_id); - - if (FAL_SCH_SP_MODE == mode) - { - val = 0; - _index = -1; - } - else if (FAL_SCH_WRR_MODE == mode) - { - val = 3; - _index = 5; - } - else if (FAL_SCH_MIX_MODE == mode) - { - val = 1; - _index = 4; - } - else if (FAL_SCH_MIX_PLUS_MODE == mode) - { - val = 2; - _index = 3; - } - else - { - return SW_NOT_SUPPORTED; - } - - for (i = _index; i >= 0; i--) - { - if (weight[i] > 0x1f) - { - return SW_BAD_PARAM; - } - w[i] = weight[i]; - } - - HSL_REG_ENTRY_GET(rv, dev_id, WRR_CTRL, port_id, (a_uint8_t *) (®), - sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - - SW_SET_REG_BY_FIELD(WRR_CTRL, SCH_MODE, val, reg); - SW_SET_REG_BY_FIELD(WRR_CTRL, Q5_W, w[5], reg); - SW_SET_REG_BY_FIELD(WRR_CTRL, Q4_W, w[4], reg); - SW_SET_REG_BY_FIELD(WRR_CTRL, Q3_W, w[3], reg); - SW_SET_REG_BY_FIELD(WRR_CTRL, Q2_W, w[2], reg); - SW_SET_REG_BY_FIELD(WRR_CTRL, Q1_W, w[1], reg); - SW_SET_REG_BY_FIELD(WRR_CTRL, Q0_W, w[0], reg); - - HSL_REG_ENTRY_SET(rv, dev_id, WRR_CTRL, port_id, - (a_uint8_t *) (®), sizeof (a_uint32_t)); - return rv; -} - -static sw_error_t -_dess_qos_port_sch_mode_get(a_uint32_t dev_id, a_uint32_t port_id, - fal_sch_mode_t * mode, a_uint32_t weight[]) -{ - sw_error_t rv; - a_uint32_t val = 0, sch, w[6], i; - - HSL_DEV_ID_CHECK(dev_id); - - HSL_REG_ENTRY_GET(rv, dev_id, WRR_CTRL, port_id, (a_uint8_t *) (&val), - sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - - SW_GET_FIELD_BY_REG(WRR_CTRL, SCH_MODE, sch, val); - SW_GET_FIELD_BY_REG(WRR_CTRL, Q5_W, w[5], val); - SW_GET_FIELD_BY_REG(WRR_CTRL, Q4_W, w[4], val); - SW_GET_FIELD_BY_REG(WRR_CTRL, Q3_W, w[3], val); - SW_GET_FIELD_BY_REG(WRR_CTRL, Q2_W, w[2], val); - SW_GET_FIELD_BY_REG(WRR_CTRL, Q1_W, w[1], val); - SW_GET_FIELD_BY_REG(WRR_CTRL, Q0_W, w[0], val); - - if (0 == sch) - { - *mode = FAL_SCH_SP_MODE; - } - else if (1 == sch) - { - *mode = FAL_SCH_MIX_MODE; - } - else if (2 == sch) - { - *mode = FAL_SCH_MIX_PLUS_MODE; - } - else - { - *mode = FAL_SCH_WRR_MODE; - } - - for (i = 0; i < 6; i++) - { - weight[i] = w[i]; - } - - return SW_OK; -} - -static sw_error_t -_dess_qos_port_default_spri_set(a_uint32_t dev_id, fal_port_t port_id, - a_uint32_t spri) -{ - sw_error_t rv; - a_uint32_t val; - - HSL_DEV_ID_CHECK(dev_id); - - if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU)) - { - return SW_BAD_PARAM; - } - - if (DESS_MAX_PRI < spri) - { - return SW_BAD_PARAM; - } - - val = spri; - HSL_REG_FIELD_SET(rv, dev_id, PORT_VLAN0, port_id, - ING_SPRI, (a_uint8_t *) (&val), sizeof (a_uint32_t)); - - return rv; -} - -static sw_error_t -_dess_qos_port_default_spri_get(a_uint32_t dev_id, fal_port_t port_id, - a_uint32_t * spri) -{ - sw_error_t rv; - a_uint32_t val = 0; - - HSL_DEV_ID_CHECK(dev_id); - - if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU)) - { - return SW_BAD_PARAM; - } - - HSL_REG_FIELD_GET(rv, dev_id, PORT_VLAN0, port_id, - ING_SPRI, (a_uint8_t *) (&val), sizeof (a_uint32_t)); - - *spri = val & 0x7; - return rv; -} - -static sw_error_t -_dess_qos_port_default_cpri_set(a_uint32_t dev_id, fal_port_t port_id, - a_uint32_t cpri) -{ - sw_error_t rv; - a_uint32_t val; - - HSL_DEV_ID_CHECK(dev_id); - - if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU)) - { - return SW_BAD_PARAM; - } - - if (DESS_MAX_PRI < cpri) - { - return SW_BAD_PARAM; - } - - val = cpri; - HSL_REG_FIELD_SET(rv, dev_id, PORT_VLAN0, port_id, - ING_CPRI, (a_uint8_t *) (&val), sizeof (a_uint32_t)); - - return rv; -} - -HSL_LOCAL sw_error_t -_dess_qos_port_default_cpri_get(a_uint32_t dev_id, fal_port_t port_id, - a_uint32_t * cpri) -{ - sw_error_t rv; - a_uint32_t val = 0; - - HSL_DEV_ID_CHECK(dev_id); - - if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU)) - { - return SW_BAD_PARAM; - } - - HSL_REG_FIELD_GET(rv, dev_id, PORT_VLAN0, port_id, - ING_CPRI, (a_uint8_t *) (&val), sizeof (a_uint32_t)); - - *cpri = val & 0x7; - return rv; -} - -HSL_LOCAL sw_error_t -_dess_qos_port_force_spri_status_set(a_uint32_t dev_id, fal_port_t port_id, - a_bool_t enable) -{ - sw_error_t rv; - a_uint32_t val; - - HSL_DEV_ID_CHECK(dev_id); - - if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU)) - { - return SW_BAD_PARAM; - } - - if (A_TRUE == enable) - { - val = 1; - } - else if (A_FALSE == enable) - { - val = 0; - } - else - { - return SW_BAD_PARAM; - } - - HSL_REG_FIELD_SET(rv, dev_id, PORT_VLAN0, port_id, - ING_FORCE_SPRI, (a_uint8_t *) (&val), sizeof (a_uint32_t)); - return rv; -} - -HSL_LOCAL sw_error_t -_dess_qos_port_force_spri_status_get(a_uint32_t dev_id, fal_port_t port_id, - a_bool_t* enable) -{ - sw_error_t rv; - a_uint32_t val = 0; - - HSL_DEV_ID_CHECK(dev_id); - if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU)) - { - return SW_BAD_PARAM; - } - - HSL_REG_FIELD_GET(rv, dev_id, PORT_VLAN0, port_id, - ING_FORCE_SPRI, (a_uint8_t *) (&val), sizeof (a_uint32_t)); - - if (1 == val) - { - *enable = A_TRUE; - } - else - { - *enable = A_FALSE; - } - - return rv; -} - -HSL_LOCAL sw_error_t -_dess_qos_port_force_cpri_status_set(a_uint32_t dev_id, fal_port_t port_id, - a_bool_t enable) -{ - sw_error_t rv; - a_uint32_t val; - - HSL_DEV_ID_CHECK(dev_id); - - if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU)) - { - return SW_BAD_PARAM; - } - - val = enable ? 1 : 0; - - HSL_REG_FIELD_SET(rv, dev_id, PORT_VLAN0, port_id, - ING_FORCE_CPRI, (a_uint8_t *) (&val), sizeof (a_uint32_t)); - - return rv; -} - -HSL_LOCAL sw_error_t -_dess_qos_port_force_cpri_status_get(a_uint32_t dev_id, fal_port_t port_id, - a_bool_t* enable) -{ - sw_error_t rv; - a_uint32_t val = 0; - - HSL_DEV_ID_CHECK(dev_id); - - if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU)) - { - return SW_BAD_PARAM; - } - - HSL_REG_FIELD_GET(rv, dev_id, PORT_VLAN0, port_id, - ING_FORCE_CPRI, (a_uint8_t *) (&val), sizeof (a_uint32_t)); - - if (1 == val) - { - *enable = A_TRUE; - } - else - { - *enable = A_FALSE; - } - - return rv; -} - -static sw_error_t -_dess_qos_queue_remark_table_set(a_uint32_t dev_id, fal_port_t port_id, - fal_queue_t queue_id, a_uint32_t tbl_id, a_bool_t enable) -{ - sw_error_t rv; - a_uint32_t addr, data = 0; - a_uint32_t base[7] = {0x0c40, 0x0c48, 0x0c4c, 0x0c50, 0x0c54, 0x0c58, 0x0c60}; - - rv = _dess_qos_port_queue_check(port_id, queue_id); - SW_RTN_ON_ERROR(rv); - - addr = base[port_id] + ((queue_id / 4) << 2); - HSL_REG_ENTRY_GEN_GET(rv, dev_id, addr, sizeof (a_uint32_t), - (a_uint8_t *) (&data), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - - data &= (~(0xff << ((queue_id % 4) << 3))); - data |= (((enable << 7 ) | (tbl_id & 0xf)) << ((queue_id % 4) << 3)); - - HSL_REG_ENTRY_GEN_SET(rv, dev_id, addr, sizeof (a_uint32_t), - (a_uint8_t *) (&data), sizeof (a_uint32_t)); - return rv; -} - -HSL_LOCAL sw_error_t -_dess_qos_queue_remark_table_get(a_uint32_t dev_id, fal_port_t port_id, - fal_queue_t queue_id, a_uint32_t * tbl_id, a_bool_t * enable) -{ - sw_error_t rv; - a_uint32_t addr, data = 0; - a_uint32_t base[7] = {0x0c40, 0x0c48, 0x0c4c, 0x0c50, 0x0c54, 0x0c58, 0x0c60}; - - rv = _dess_qos_port_queue_check(port_id, queue_id); - SW_RTN_ON_ERROR(rv); - - addr = base[port_id] + ((queue_id / 4) << 2); - HSL_REG_ENTRY_GEN_GET(rv, dev_id, addr, sizeof (a_uint32_t), - (a_uint8_t *) (&data), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - - *tbl_id = (data >> ((queue_id % 4) << 3)) & 0xf; - *enable = ((data >> ((queue_id % 4) << 3)) & 0x80) >> 7; - return SW_OK; -} - -/** - * @brief Set buffer aggsinment status of transmitting queue on one particular port. - * @details Comments: - * If enable queue tx buffer on one port that means each queue of this port - * will have fixed number buffers when transmitting packets. Otherwise they - * share the whole buffers with other queues in device. - * @param[in] dev_id device id - * @param[in] port_id port id - * @param[in] enable A_TRUE or A_FALSE - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -dess_qos_queue_tx_buf_status_set(a_uint32_t dev_id, fal_port_t port_id, - a_bool_t enable) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _dess_qos_queue_tx_buf_status_set(dev_id, port_id, enable); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Get buffer aggsinment status of transmitting queue on particular port. - * @param[in] dev_id device id - * @param[in] port_id port id - * @param[in] enable A_TRUE or A_FALSE - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -dess_qos_queue_tx_buf_status_get(a_uint32_t dev_id, fal_port_t port_id, - a_bool_t * enable) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _dess_qos_queue_tx_buf_status_get(dev_id, port_id, enable); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Set buffer aggsinment status of transmitting port on one particular port. - * @details Comments: - If enable tx buffer on one port that means this port will have fixed - number buffers when transmitting packets. Otherwise they will - share the whole buffers with other ports in device. - * function will return actual buffer numbers in hardware. - * @param[in] dev_id device id - * @param[in] port_id port id - * @param[in] enable A_TRUE or A_FALSE - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -dess_qos_port_tx_buf_status_set(a_uint32_t dev_id, fal_port_t port_id, - a_bool_t enable) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _dess_qos_port_tx_buf_status_set(dev_id, port_id, enable); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Get buffer aggsinment status of transmitting port on one particular port. - * @param[in] dev_id device id - * @param[in] port_id port id - * @param[out] enable A_TRUE or A_FALSE - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -dess_qos_port_tx_buf_status_get(a_uint32_t dev_id, fal_port_t port_id, - a_bool_t * enable) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _dess_qos_port_tx_buf_status_get(dev_id, port_id, enable); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Set status of port red on one particular port. - * @param[in] dev_id device id - * @param[in] port_id port id - * @param[in] enable A_TRUE or A_FALSE - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -dess_qos_port_red_en_set(a_uint32_t dev_id, fal_port_t port_id, - a_bool_t enable) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _dess_qos_port_red_en_set(dev_id, port_id, enable); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Set status of port red on one particular port. - * @param[in] dev_id device id - * @param[in] port_id port id - * @param[in] enable A_TRUE or A_FALSE - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -dess_qos_port_red_en_get(a_uint32_t dev_id, fal_port_t port_id, - a_bool_t* enable) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _dess_qos_port_red_en_get(dev_id, port_id, enable); - HSL_API_UNLOCK; - return rv; -} - - -/** - * @brief Set max occupied buffer number of transmitting queue on one particular port. - * @details Comments: - The step of buffer number in Garuda is 4, function will return actual - buffer numbers in hardware. - The buffer number range for queue is 4 to 60. - * share the whole buffers with other ports in device. - * @param[in] dev_id device id - * @param[in] port_id port id - * @param[in] queue_id queue id - * @param number buffer number - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -dess_qos_queue_tx_buf_nr_set(a_uint32_t dev_id, fal_port_t port_id, - fal_queue_t queue_id, a_uint32_t * number) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _dess_qos_queue_tx_buf_nr_set(dev_id, port_id, queue_id, number); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Get max occupied buffer number of transmitting queue on one particular port. - * @param[in] dev_id device id - * @param[in] port_id port id - * @param[in] queue_id queue id - * @param[out] number buffer number - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -dess_qos_queue_tx_buf_nr_get(a_uint32_t dev_id, fal_port_t port_id, - fal_queue_t queue_id, a_uint32_t * number) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _dess_qos_queue_tx_buf_nr_get(dev_id, port_id, queue_id, number); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Set max occupied buffer number of transmitting port on one particular port. - * @details Comments: - The step of buffer number in Garuda is four, function will return actual - buffer numbers in hardware. - The buffer number range for transmitting port is 4 to 124. - * @param[in] dev_id device id - * @param[in] port_id port id - * @param number buffer number - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -dess_qos_port_tx_buf_nr_set(a_uint32_t dev_id, fal_port_t port_id, - a_uint32_t * number) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _dess_qos_port_tx_buf_nr_set(dev_id, port_id, number); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Get max occupied buffer number of transmitting port on one particular port. - * @param[in] dev_id device id - * @param[in] port_id port id - * @param[out] number buffer number - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -dess_qos_port_tx_buf_nr_get(a_uint32_t dev_id, fal_port_t port_id, - a_uint32_t * number) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _dess_qos_port_tx_buf_nr_get(dev_id, port_id, number); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Set max occupied buffer number of receiving port on one particular port. - * @details Comments: - The step of buffer number in Shiva is four, function will return actual - buffer numbers in hardware. - The buffer number range for receiving port is 4 to 60. - * @param[in] dev_id device id - * @param[in] port_id port id - * @param number buffer number - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -dess_qos_port_rx_buf_nr_set(a_uint32_t dev_id, fal_port_t port_id, - a_uint32_t * number) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _dess_qos_port_rx_buf_nr_set(dev_id, port_id, number); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Get max occupied buffer number of receiving port on one particular port. - * @param[in] dev_id device id - * @param[in] port_id port id - * @param[out] number buffer number - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -dess_qos_port_rx_buf_nr_get(a_uint32_t dev_id, fal_port_t port_id, - a_uint32_t * number) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _dess_qos_port_rx_buf_nr_get(dev_id, port_id, number); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Set port qos mode on a particular port. - * @param[in] dev_id device id - * @param[in] port_id port id - * @param[in] mode qos mode - * @param[in] enable A_TRUE of A_FALSE - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -dess_qos_port_mode_set(a_uint32_t dev_id, fal_port_t port_id, - fal_qos_mode_t mode, a_bool_t enable) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _dess_qos_port_mode_set(dev_id, port_id, mode, enable); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Get port qos mode on a particular port. - * @param[in] dev_id device id - * @param[in] port_id port id - * @param[in] mode qos mode - * @param[out] enable A_TRUE of A_FALSE - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -dess_qos_port_mode_get(a_uint32_t dev_id, fal_port_t port_id, - fal_qos_mode_t mode, a_bool_t * enable) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _dess_qos_port_mode_get(dev_id, port_id, mode, enable); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Set priority of one particular qos mode on one particular port. - * @details Comments: - If the priority of a mode is more small then the priority is more high. - Differnet mode should have differnet priority. - * @param[in] dev_id device id - * @param[in] port_id port id - * @param[in] mode qos mode - * @param[in] pri priority of one particular qos mode - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -dess_qos_port_mode_pri_set(a_uint32_t dev_id, fal_port_t port_id, - fal_qos_mode_t mode, a_uint32_t pri) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _dess_qos_port_mode_pri_set(dev_id, port_id, mode, pri); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Get priority of one particular qos mode on one particular port. - * @param[in] dev_id device id - * @param[in] port_id port id - * @param[in] mode qos mode - * @param[out] pri priority of one particular qos mode - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -dess_qos_port_mode_pri_get(a_uint32_t dev_id, fal_port_t port_id, - fal_qos_mode_t mode, a_uint32_t * pri) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _dess_qos_port_mode_pri_get(dev_id, port_id, mode, pri); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Set traffic scheduling mode on particular one port. - * @details Comments: - * When scheduling mode is sp the weight is meaningless usually it's zero - * @param[in] dev_id device id - * @param[in] port_id port id - * @param[in] fal_sch_mode_t traffic scheduling mode - * @param[in] weight[] weight value for each queue when in wrr mode, - the max value supported by ISIS is 0x1f. - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -dess_qos_port_sch_mode_set(a_uint32_t dev_id, a_uint32_t port_id, - fal_sch_mode_t mode, const a_uint32_t weight[]) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _dess_qos_port_sch_mode_set(dev_id, port_id, mode, weight); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Get traffic scheduling mode on particular port. - * @param[in] dev_id device id - * @param[in] port_id port id - * @param[out] fal_sch_mode_t traffic scheduling mode - * @param[out] weight weight value for wrr mode - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -dess_qos_port_sch_mode_get(a_uint32_t dev_id, a_uint32_t port_id, - fal_sch_mode_t * mode, a_uint32_t weight[]) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _dess_qos_port_sch_mode_get(dev_id, port_id, mode, weight); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Set default stag priority on one particular port. - * @param[in] dev_id device id - * @param[in] port_id port id - * @param[in] spri vlan priority - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -dess_qos_port_default_spri_set(a_uint32_t dev_id, fal_port_t port_id, - a_uint32_t spri) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _dess_qos_port_default_spri_set(dev_id, port_id, spri); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Get default stag priority on one particular port. - * @param[in] dev_id device id - * @param[in] port_id port id - * @param[out] spri vlan priority - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -dess_qos_port_default_spri_get(a_uint32_t dev_id, fal_port_t port_id, - a_uint32_t * spri) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _dess_qos_port_default_spri_get(dev_id, port_id, spri); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Set default ctag priority on one particular port. - * @param[in] dev_id device id - * @param[in] port_id port id - * @param[in] cpri vlan priority - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -dess_qos_port_default_cpri_set(a_uint32_t dev_id, fal_port_t port_id, - a_uint32_t cpri) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _dess_qos_port_default_cpri_set(dev_id, port_id, cpri); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Get default ctag priority on one particular port. - * @param[in] dev_id device id - * @param[in] port_id port id - * @param[out] cpri vlan priority - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -dess_qos_port_default_cpri_get(a_uint32_t dev_id, fal_port_t port_id, - a_uint32_t * cpri) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _dess_qos_port_default_cpri_get(dev_id, port_id, cpri); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Set port force stag priority enable flag one particular port. - * @param[in] dev_id device id - * @param[in] port_id port id - * @param[in] enable A_TRUE or A_FALSE - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -dess_qos_port_force_spri_status_set(a_uint32_t dev_id, fal_port_t port_id, - a_bool_t enable) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _dess_qos_port_force_spri_status_set(dev_id, port_id, enable); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Get port force stag priority enable flag one particular port. - * @param[in] dev_id device id - * @param[in] port_id port id - * @param[out] enable A_TRUE or A_FALSE - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -dess_qos_port_force_spri_status_get(a_uint32_t dev_id, fal_port_t port_id, - a_bool_t* enable) -{ - sw_error_t rv; - HSL_API_LOCK; - rv = _dess_qos_port_force_spri_status_get(dev_id, port_id, enable); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Set port force ctag priority enable flag one particular port. - * @param[in] dev_id device id - * @param[in] port_id port id - * @param[in] enable A_TRUE or A_FALSE - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -dess_qos_port_force_cpri_status_set(a_uint32_t dev_id, fal_port_t port_id, - a_bool_t enable) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _dess_qos_port_force_cpri_status_set(dev_id, port_id, enable); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Get port force ctag priority enable flag one particular port. - * @param[in] dev_id device id - * @param[in] port_id port id - * @param[out] enable A_TRUE or A_FALSE - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -dess_qos_port_force_cpri_status_get(a_uint32_t dev_id, fal_port_t port_id, - a_bool_t* enable) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _dess_qos_port_force_cpri_status_get(dev_id, port_id, enable); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Set egress queue based CoS remark on one particular port. - * @param[in] dev_id device id - * @param[in] port_id port id - * @param[in] queue_id queue id - * @param[in] tbl_id CoS remark table id - * @param[in] enable A_TRUE or A_FALSE - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -dess_qos_queue_remark_table_set(a_uint32_t dev_id, fal_port_t port_id, - fal_queue_t queue_id, a_uint32_t tbl_id, a_bool_t enable) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _dess_qos_queue_remark_table_set(dev_id, port_id, queue_id, tbl_id, enable); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Get egress queue based CoS remark on one particular port. - * @param[in] dev_id device id - * @param[in] port_id port id - * @param[in] queue_id queue id - * @param[out] tbl_id CoS remark table id - * @param[out] enable A_TRUE or A_FALSE - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -dess_qos_queue_remark_table_get(a_uint32_t dev_id, fal_port_t port_id, - fal_queue_t queue_id, a_uint32_t * tbl_id, a_bool_t * enable) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _dess_qos_queue_remark_table_get(dev_id, port_id, queue_id, tbl_id, enable); - HSL_API_UNLOCK; - return rv; -} - -sw_error_t -dess_qos_init(a_uint32_t dev_id) -{ - HSL_DEV_ID_CHECK(dev_id); - -#ifndef HSL_STANDALONG - { - hsl_api_t *p_api; - - SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id)); - - p_api->qos_queue_tx_buf_status_set = dess_qos_queue_tx_buf_status_set; - p_api->qos_queue_tx_buf_status_get = dess_qos_queue_tx_buf_status_get; - p_api->qos_port_tx_buf_status_set = dess_qos_port_tx_buf_status_set; - p_api->qos_port_tx_buf_status_get = dess_qos_port_tx_buf_status_get; - p_api->qos_port_red_en_set = dess_qos_port_red_en_set; - p_api->qos_port_red_en_get = dess_qos_port_red_en_get; - p_api->qos_queue_tx_buf_nr_set = dess_qos_queue_tx_buf_nr_set; - p_api->qos_queue_tx_buf_nr_get = dess_qos_queue_tx_buf_nr_get; - p_api->qos_port_tx_buf_nr_set = dess_qos_port_tx_buf_nr_set; - p_api->qos_port_tx_buf_nr_get = dess_qos_port_tx_buf_nr_get; - p_api->qos_port_rx_buf_nr_set = dess_qos_port_rx_buf_nr_set; - p_api->qos_port_rx_buf_nr_get = dess_qos_port_rx_buf_nr_get; - p_api->qos_port_mode_set = dess_qos_port_mode_set; - p_api->qos_port_mode_get = dess_qos_port_mode_get; - p_api->qos_port_mode_pri_set = dess_qos_port_mode_pri_set; - p_api->qos_port_mode_pri_get = dess_qos_port_mode_pri_get; - p_api->qos_port_sch_mode_set = dess_qos_port_sch_mode_set; - p_api->qos_port_sch_mode_get = dess_qos_port_sch_mode_get; - p_api->qos_port_default_spri_set = dess_qos_port_default_spri_set; - p_api->qos_port_default_spri_get = dess_qos_port_default_spri_get; - p_api->qos_port_default_cpri_set = dess_qos_port_default_cpri_set; - p_api->qos_port_default_cpri_get = dess_qos_port_default_cpri_get; - p_api->qos_port_force_spri_status_set = dess_qos_port_force_spri_status_set; - p_api->qos_port_force_spri_status_get = dess_qos_port_force_spri_status_get; - p_api->qos_port_force_cpri_status_set = dess_qos_port_force_cpri_status_set; - p_api->qos_port_force_cpri_status_get = dess_qos_port_force_cpri_status_get; - p_api->qos_queue_remark_table_set = dess_qos_queue_remark_table_set; - p_api->qos_queue_remark_table_get = dess_qos_queue_remark_table_get; - } -#endif - - return SW_OK; -} - -/** - * @} - */ diff --git a/feeds/ipq807x/qca-ssdk/src/src/hsl/dess/dess_rate.c b/feeds/ipq807x/qca-ssdk/src/src/hsl/dess/dess_rate.c deleted file mode 100755 index 44cd36a80..000000000 --- a/feeds/ipq807x/qca-ssdk/src/src/hsl/dess/dess_rate.c +++ /dev/null @@ -1,1672 +0,0 @@ -/* - * Copyright (c) 2014,2016 The Linux Foundation. All rights reserved. - * Permission to use, copy, modify, and/or distribute this software for - * any purpose with or without fee is hereby granted, provided that the - * above copyright notice and this permission notice appear in all copies. - * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES - * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR - * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES - * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN - * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT - * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. - */ - - -/** - * @defgroup dess_rate DESS_RATE - * @{ - */ -#include "sw.h" -#include "hsl.h" -#include "hsl_dev.h" -#include "hsl_port_prop.h" -#include "dess_rate.h" -#include "dess_reg.h" - -#define DESS_MAX_POLICER_ID 31 -#define DESS_MAX_QUEUE 3 -#define DESS_MAX_EH_QUEUE 5 - -#define ACL_POLICER_CNT_SEL_ADDR 0x09f0 -#define ACL_POLICER_CNT_MODE_ADDR 0x09f4 -#define ACL_POLICER_CNT_RST_ADDR 0x09f8 - -static sw_error_t -_dess_rate_port_queue_check(fal_port_t port_id, fal_queue_t queue_id) -{ - if ((0 == port_id) || (5 == port_id) || (6 == port_id)) - { - if (DESS_MAX_EH_QUEUE < queue_id) - { - return SW_BAD_PARAM; - } - } - else - { - if (DESS_MAX_QUEUE < queue_id) - { - return SW_BAD_PARAM; - } - } - - return SW_OK; -} - -static void -_dess_egress_bs_byte_sw_to_hw(a_uint32_t sw_bs, a_uint32_t * hw_bs) -{ - a_int32_t i; - a_uint32_t data[8] = - { - 0, 2 * 1024, 4 * 1024, 8 * 1024, 16 * 1024, 32 * 1024, 128 * 1024, - 512 * 1024 - }; - - for (i = 7; i >= 0; i--) - { - if (sw_bs >= data[i]) - { - *hw_bs = i; - break; - } - } -} - -static void -_dess_egress_bs_byte_hw_to_sw(a_uint32_t hw_bs, a_uint32_t * sw_bs) -{ - a_uint32_t data[8] = - { - 0, 2 * 1024, 4 * 1024, 8 * 1024, 16 * 1024, 32 * 1024, 128 * 1024, - 512 * 1024 - }; - - *sw_bs = data[hw_bs & 0x7]; -} - -static void -_dess_egress_bs_frame_sw_to_hw(a_uint32_t sw_bs, a_uint32_t * hw_bs) -{ - a_uint32_t data[8] = { 0, 2, 4, 16, 64, 256, 512, 1024 }; - a_int32_t i; - - for (i = 7; i >= 0; i--) - { - if (sw_bs >= data[i]) - { - *hw_bs = i; - break; - } - } -} - -static void -_dess_egress_bs_frame_hw_to_sw(a_uint32_t hw_bs, a_uint32_t * sw_bs) -{ - a_uint32_t data[8] = { 0, 2, 4, 16, 64, 256, 512, 1024 }; - - *sw_bs = data[hw_bs & 0x7]; -} - -static void -_dess_ingress_bs_byte_sw_to_hw(a_uint32_t sw_bs, a_uint32_t * hw_bs) -{ - a_int32_t i; - a_uint32_t data[8] = - { - 0, 4 * 1024, 32 * 1024, 128 * 1024, 512 * 1024, 2 * 1024 * 1024, - 8 * 1024 * 1024, 32 * 1024 * 1024 - }; - - for (i = 7; i >= 0; i--) - { - if (sw_bs >= data[i]) - { - *hw_bs = i; - break; - } - } -} - -static void -_dess_ingress_bs_byte_hw_to_sw(a_uint32_t hw_bs, a_uint32_t * sw_bs) -{ - a_uint32_t data[8] = - { - 0, 4 * 1024, 32 * 1024, 128 * 1024, 512 * 1024, 2 * 1024 * 1024, - 8 * 1024 * 1024, 32 * 1024 * 1024 - }; - - *sw_bs = data[hw_bs & 0x7]; -} - -static void -_dess_ingress_bs_frame_sw_to_hw(a_uint32_t sw_bs, a_uint32_t * hw_bs) -{ - a_uint32_t data[8] = { 0, 4, 16, 64, 256, 1024, 4096, 16384 }; - a_int32_t i; - - for (i = 7; i >= 0; i--) - { - if (sw_bs >= data[i]) - { - *hw_bs = i; - break; - } - } -} - -static void -_dess_ingress_bs_frame_hw_to_sw(a_uint32_t hw_bs, a_uint32_t * sw_bs) -{ - a_uint32_t data[8] = { 0, 4, 16, 64, 256, 1024, 4096, 16384 }; - - *sw_bs = data[hw_bs & 0x7]; -} - -static void -_dess_rate_flag_parse(a_uint32_t sw_flag, a_uint32_t * hw_flag) -{ - *hw_flag = 0; - - if (FAL_INGRESS_POLICING_TCP_CTRL & sw_flag) - { - *hw_flag |= (0x1 << 1); - } - - if (FAL_INGRESS_POLICING_MANAGEMENT & sw_flag) - { - *hw_flag |= (0x1 << 2); - } - - if (FAL_INGRESS_POLICING_BROAD & sw_flag) - { - *hw_flag |= (0x1 << 3); - } - - if (FAL_INGRESS_POLICING_UNK_UNI & sw_flag) - { - *hw_flag |= (0x1 << 4); - } - - if (FAL_INGRESS_POLICING_UNK_MUL & sw_flag) - { - *hw_flag |= (0x1 << 5); - } - - if (FAL_INGRESS_POLICING_UNI & sw_flag) - { - *hw_flag |= (0x1 << 6); - } - - if (FAL_INGRESS_POLICING_MUL & sw_flag) - { - *hw_flag |= (0x1 << 7); - } -} - -static void -_dess_rate_flag_reparse(a_uint32_t hw_flag, a_uint32_t * sw_flag) -{ - *sw_flag = 0; - - if (hw_flag & 0x2) - { - *sw_flag |= FAL_INGRESS_POLICING_TCP_CTRL; - } - - if (hw_flag & 0x4) - { - *sw_flag |= FAL_INGRESS_POLICING_MANAGEMENT; - } - - if (hw_flag & 0x8) - { - *sw_flag |= FAL_INGRESS_POLICING_BROAD; - } - - if (hw_flag & 0x10) - { - *sw_flag |= FAL_INGRESS_POLICING_UNK_UNI; - } - - if (hw_flag & 0x20) - { - *sw_flag |= FAL_INGRESS_POLICING_UNK_MUL; - } - - if (hw_flag & 0x40) - { - *sw_flag |= FAL_INGRESS_POLICING_UNI; - } - - if (hw_flag & 0x80) - { - *sw_flag |= FAL_INGRESS_POLICING_MUL; - } -} - -static void -_dess_rate_ts_parse(fal_rate_mt_t sw, a_uint32_t * hw) -{ - if (FAL_RATE_MI_100US == sw) - { - *hw = 0; - } - else if (FAL_RATE_MI_1MS == sw) - { - *hw = 1; - } - else if (FAL_RATE_MI_10MS == sw) - { - *hw = 2; - } - else if (FAL_RATE_MI_100MS) - { - *hw = 3; - } - else - { - *hw = 0; - } -} - -static void -_dess_rate_ts_reparse(a_uint32_t hw, fal_rate_mt_t * sw) -{ - if (0 == hw) - { - *sw = FAL_RATE_MI_100US; - } - else if (1 == hw) - { - *sw = FAL_RATE_MI_1MS; - } - else if (2 == hw) - { - *sw = FAL_RATE_MI_10MS; - } - else - { - *sw = FAL_RATE_MI_100MS; - } -} - -static sw_error_t -_dess_rate_port_policer_set(a_uint32_t dev_id, fal_port_t port_id, - fal_port_policer_t * policer) -{ - sw_error_t rv; - a_uint32_t cir = 0x7fff, eir = 0x7fff, cbs = 0, ebs = 0, tmp, data[3] = { 0 }; - - HSL_DEV_ID_CHECK(dev_id); - - if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU)) - { - return SW_BAD_PARAM; - } - - data[0] = 0x18000000; - if (FAL_BYTE_BASED == policer->meter_unit) - { - if (A_TRUE == policer->c_enable) - { - cir = policer->cir >> 5; - policer->cir = cir << 5; - _dess_ingress_bs_byte_sw_to_hw(policer->cbs, &cbs); - _dess_ingress_bs_byte_hw_to_sw(cbs, &(policer->cbs)); - } - - if (A_TRUE == policer->e_enable) - { - eir = policer->eir >> 5; - policer->eir = eir << 5; - _dess_ingress_bs_byte_sw_to_hw(policer->ebs, &ebs); - _dess_ingress_bs_byte_hw_to_sw(ebs, &(policer->ebs)); - } - - SW_SET_REG_BY_FIELD(INGRESS_POLICER1, INGRESS_UNIT, 0, data[1]); - } - else if (FAL_FRAME_BASED == policer->meter_unit) - { - if (A_TRUE == policer->c_enable) - { - cir = (policer->cir * 2) / 125; - policer->cir = cir / 2 * 125 + cir % 2 * 63; - _dess_ingress_bs_frame_sw_to_hw(policer->cbs, &cbs); - _dess_ingress_bs_frame_hw_to_sw(cbs, &(policer->cbs)); - } - - if (A_TRUE == policer->e_enable) - { - eir = (policer->eir * 2) / 125; - policer->eir = eir / 2 * 125 + eir % 2 * 63; - _dess_ingress_bs_frame_sw_to_hw(policer->ebs, &ebs); - _dess_ingress_bs_frame_hw_to_sw(ebs, &(policer->ebs)); - } - - SW_SET_REG_BY_FIELD(INGRESS_POLICER1, INGRESS_UNIT, 1, data[1]); - } - else - { - return SW_BAD_PARAM; - } - - SW_SET_REG_BY_FIELD(INGRESS_POLICER0, INGRESS_CIR, cir, data[0]); - SW_SET_REG_BY_FIELD(INGRESS_POLICER0, INGRESS_CBS, cbs, data[0]); - SW_SET_REG_BY_FIELD(INGRESS_POLICER1, INGRESS_EIR, eir, data[1]); - SW_SET_REG_BY_FIELD(INGRESS_POLICER1, INGRESS_EBS, ebs, data[1]); - - if (A_TRUE == policer->combine_mode) - { - SW_SET_REG_BY_FIELD(INGRESS_POLICER0, RATE_MODE, 1, data[0]); - } - - if (A_TRUE == policer->deficit_en) - { - SW_SET_REG_BY_FIELD(INGRESS_POLICER1, INGRESS_BORROW, 1, data[1]); - } - - if (A_TRUE == policer->color_mode) - { - SW_SET_REG_BY_FIELD(INGRESS_POLICER1, INGRESS_CM, 1, data[1]); - } - - if (A_TRUE == policer->couple_flag) - { - SW_SET_REG_BY_FIELD(INGRESS_POLICER1, INGRESS_CF, 1, data[1]); - } - - _dess_rate_ts_parse(policer->c_meter_interval, &tmp); - SW_SET_REG_BY_FIELD(INGRESS_POLICER0, C_ING_TS, tmp, data[0]); - - _dess_rate_ts_parse(policer->e_meter_interval, &tmp); - SW_SET_REG_BY_FIELD(INGRESS_POLICER1, E_ING_TS, tmp, data[1]); - - _dess_rate_flag_parse(policer->c_rate_flag, &tmp); - data[2] = (tmp << 8) & 0xff00; - - _dess_rate_flag_parse(policer->e_rate_flag, &tmp); - data[2] |= (tmp & 0xff); - - HSL_REG_ENTRY_SET(rv, dev_id, INGRESS_POLICER0, port_id, - (a_uint8_t *) (&data[0]), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - - HSL_REG_ENTRY_SET(rv, dev_id, INGRESS_POLICER1, port_id, - (a_uint8_t *) (&data[1]), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - - HSL_REG_ENTRY_SET(rv, dev_id, INGRESS_POLICER2, port_id, - (a_uint8_t *) (&data[2]), sizeof (a_uint32_t)); - return rv; -} - -static sw_error_t -_dess_rate_port_policer_get(a_uint32_t dev_id, fal_port_t port_id, - fal_port_policer_t * policer) -{ - sw_error_t rv; - a_uint32_t unit, ts, cir, eir, cbs, ebs, data[3] = {0}; - - HSL_DEV_ID_CHECK(dev_id); - - if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU)) - { - return SW_BAD_PARAM; - } - - HSL_REG_ENTRY_GET(rv, dev_id, INGRESS_POLICER0, port_id, - (a_uint8_t *) (&data[0]), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - - HSL_REG_ENTRY_GET(rv, dev_id, INGRESS_POLICER1, port_id, - (a_uint8_t *) (&data[1]), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - - HSL_REG_ENTRY_GET(rv, dev_id, INGRESS_POLICER2, port_id, - (a_uint8_t *) (&data[2]), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - - SW_GET_FIELD_BY_REG(INGRESS_POLICER0, INGRESS_CIR, cir, data[0]); - SW_GET_FIELD_BY_REG(INGRESS_POLICER0, INGRESS_CBS, cbs, data[0]); - SW_GET_FIELD_BY_REG(INGRESS_POLICER1, INGRESS_EIR, eir, data[1]); - SW_GET_FIELD_BY_REG(INGRESS_POLICER1, INGRESS_EBS, ebs, data[1]); - SW_GET_FIELD_BY_REG(INGRESS_POLICER1, INGRESS_UNIT, unit, data[1]); - - policer->c_enable = A_TRUE; - if (0x7fff == cir) - { - policer->c_enable = A_FALSE; - cir = 0; - } - - policer->e_enable = A_TRUE; - if (0x7fff == eir) - { - policer->e_enable = A_FALSE; - eir = 0; - } - - if (unit) - { - policer->meter_unit = FAL_FRAME_BASED; - policer->cir = cir / 2 * 125 + cir % 2 * 63; - policer->eir = eir / 2 * 125 + eir % 2 * 63; - _dess_ingress_bs_frame_hw_to_sw(cbs, &(policer->cbs)); - _dess_ingress_bs_frame_hw_to_sw(ebs, &(policer->ebs)); - } - else - { - policer->meter_unit = FAL_BYTE_BASED; - policer->cir = cir << 5; - policer->eir = eir << 5; - _dess_ingress_bs_byte_hw_to_sw(cbs, &(policer->cbs)); - _dess_ingress_bs_byte_hw_to_sw(ebs, &(policer->ebs)); - } - - SW_GET_FIELD_BY_REG(INGRESS_POLICER0, RATE_MODE, policer->combine_mode, - data[0]); - SW_GET_FIELD_BY_REG(INGRESS_POLICER1, INGRESS_BORROW, policer->deficit_en, - data[1]); - SW_GET_FIELD_BY_REG(INGRESS_POLICER1, INGRESS_CF, policer->couple_flag, - data[1]); - SW_GET_FIELD_BY_REG(INGRESS_POLICER1, INGRESS_CM, policer->color_mode, - data[1]); - - ts = (data[2] >> 8) & 0xff; - _dess_rate_flag_reparse(ts, &(policer->c_rate_flag)); - - ts = data[2] & 0xff; - _dess_rate_flag_reparse(ts, &(policer->e_rate_flag)); - - SW_GET_FIELD_BY_REG(INGRESS_POLICER0, C_ING_TS, ts, data[0]); - _dess_rate_ts_reparse(ts, &(policer->c_meter_interval)); - - SW_GET_FIELD_BY_REG(INGRESS_POLICER1, E_ING_TS, ts, data[1]); - _dess_rate_ts_reparse(ts, &(policer->e_meter_interval)); - - return SW_OK; -} - -static sw_error_t -_dess_rate_port_shaper_set(a_uint32_t dev_id, fal_port_t port_id, - a_bool_t enable, fal_egress_shaper_t * shaper) -{ - sw_error_t rv; - a_uint32_t data, cir, eir, cbs = 0, ebs = 0; - - HSL_DEV_ID_CHECK(dev_id); - - if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU)) - { - return SW_BAD_PARAM; - } - - if (A_FALSE == enable) - { - aos_mem_zero(shaper, sizeof (fal_egress_shaper_t)); - - cir = 0x7fff; - eir = 0x7fff; - } - else - { - if (FAL_BYTE_BASED == shaper->meter_unit) - { - cir = shaper->cir >> 5; - shaper->cir = cir << 5; - - eir = shaper->eir >> 5; - shaper->eir = eir << 5; - - _dess_egress_bs_byte_sw_to_hw(shaper->cbs, &cbs); - _dess_egress_bs_byte_hw_to_sw(cbs, &(shaper->cbs)); - - _dess_egress_bs_byte_sw_to_hw(shaper->ebs, &ebs); - _dess_egress_bs_byte_hw_to_sw(ebs, &(shaper->ebs)); - - data = 0; - } - else if (FAL_FRAME_BASED == shaper->meter_unit) - { - cir = (shaper->cir * 2) / 125; - shaper->cir = cir / 2 * 125 + cir % 2 * 63; - - eir = (shaper->eir * 2) / 125; - shaper->eir = eir / 2 * 125 + eir % 2 * 63; - - _dess_egress_bs_frame_sw_to_hw(shaper->cbs, &cbs); - _dess_egress_bs_frame_hw_to_sw(cbs, &(shaper->cbs)); - - _dess_egress_bs_frame_sw_to_hw(shaper->ebs, &ebs); - _dess_egress_bs_frame_hw_to_sw(ebs, &(shaper->ebs)); - - data = 1; - } - else - { - return SW_BAD_PARAM; - } - - HSL_REG_FIELD_SET(rv, dev_id, EG_SHAPER7, port_id, EG_Q0_UNIT, - (a_uint8_t *) (&data), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - - data = 1; - HSL_REG_FIELD_SET(rv, dev_id, EG_SHAPER7, port_id, EG_PT, - (a_uint8_t *) (&data), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - - data = 0; - HSL_REG_FIELD_SET(rv, dev_id, EG_SHAPER7, port_id, EG_TS, - (a_uint8_t *) (&data), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - } - - HSL_REG_FIELD_SET(rv, dev_id, EG_SHAPER0, port_id, EG_Q0_CIR, - (a_uint8_t *) (&cir), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - - HSL_REG_FIELD_SET(rv, dev_id, EG_SHAPER3, port_id, EG_Q0_EIR, - (a_uint8_t *) (&eir), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - - HSL_REG_FIELD_SET(rv, dev_id, EG_SHAPER6, port_id, EG_Q0_CBS, - (a_uint8_t *) (&cbs), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - - HSL_REG_FIELD_SET(rv, dev_id, EG_SHAPER6, port_id, EG_Q0_EBS, - (a_uint8_t *) (&ebs), sizeof (a_uint32_t)); - return rv; -} - -static sw_error_t -_dess_rate_port_shaper_get(a_uint32_t dev_id, fal_port_t port_id, - a_bool_t * enable, fal_egress_shaper_t * shaper) -{ - sw_error_t rv; - a_uint32_t data = 0, cir = 0, eir = 0, cbs = 0, ebs = 0; - - HSL_DEV_ID_CHECK(dev_id); - - if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU)) - { - return SW_BAD_PARAM; - } - - aos_mem_zero(shaper, sizeof (fal_egress_shaper_t)); - - HSL_REG_FIELD_GET(rv, dev_id, EG_SHAPER7, port_id, EG_PT, - (a_uint8_t *) (&data), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - - if (!data) - { - *enable = A_FALSE; - return SW_OK; - } - - HSL_REG_FIELD_GET(rv, dev_id, EG_SHAPER0, port_id, EG_Q0_CIR, - (a_uint8_t *) (&cir), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - - HSL_REG_FIELD_GET(rv, dev_id, EG_SHAPER3, port_id, EG_Q0_EIR, - (a_uint8_t *) (&eir), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - - HSL_REG_FIELD_GET(rv, dev_id, EG_SHAPER6, port_id, EG_Q0_CBS, - (a_uint8_t *) (&cbs), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - - HSL_REG_FIELD_GET(rv, dev_id, EG_SHAPER6, port_id, EG_Q0_EBS, - (a_uint8_t *) (&ebs), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - - if ((0x7fff == cir) && (0x7fff == eir)) - { - *enable = A_FALSE; - return SW_OK; - } - - *enable = A_TRUE; - HSL_REG_FIELD_GET(rv, dev_id, EG_SHAPER7, port_id, EG_Q0_UNIT, - (a_uint8_t *) (&data), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - - if (data) - { - shaper->meter_unit = FAL_FRAME_BASED; - shaper->cir = cir / 2 * 125 + cir % 2 * 63; - shaper->eir = eir / 2 * 125 + eir % 2 * 63; - _dess_egress_bs_frame_hw_to_sw(cbs, &(shaper->cbs)); - _dess_egress_bs_frame_hw_to_sw(ebs, &(shaper->ebs)); - } - else - { - shaper->meter_unit = FAL_BYTE_BASED; - shaper->cir = cir << 5; - shaper->eir = eir << 5; - _dess_egress_bs_byte_hw_to_sw(cbs, &(shaper->cbs)); - _dess_egress_bs_byte_hw_to_sw(ebs, &(shaper->ebs)); - } - - return SW_OK; -} - -static sw_error_t -_dess_rate_queue_shaper_set(a_uint32_t dev_id, fal_port_t port_id, - fal_queue_t queue_id, a_bool_t enable, - fal_egress_shaper_t * shaper) -{ - sw_error_t rv; - a_uint32_t unit = 0, data, cir, eir, cbs = 0, ebs = 0; - - HSL_DEV_ID_CHECK(dev_id); - - if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU)) - { - return SW_BAD_PARAM; - } - - rv = _dess_rate_port_queue_check(port_id, queue_id); - SW_RTN_ON_ERROR(rv); - - if (A_FALSE == enable) - { - aos_mem_zero(shaper, sizeof (fal_egress_shaper_t)); - - cir = 0x7fff; - eir = 0x7fff; - } - else - { - if (FAL_BYTE_BASED == shaper->meter_unit) - { - cir = shaper->cir >> 5; - shaper->cir = cir << 5; - - eir = shaper->eir >> 5; - shaper->eir = eir << 5; - - _dess_egress_bs_byte_sw_to_hw(shaper->cbs, &cbs); - _dess_egress_bs_byte_hw_to_sw(cbs, &(shaper->cbs)); - - _dess_egress_bs_byte_sw_to_hw(shaper->ebs, &ebs); - _dess_egress_bs_byte_hw_to_sw(ebs, &(shaper->ebs)); - - unit = 0; - } - else if (FAL_FRAME_BASED == shaper->meter_unit) - { - cir = (shaper->cir * 2) / 125; - shaper->cir = cir / 2 * 125 + cir % 2 * 63; - - eir = (shaper->eir * 2) / 125; - shaper->eir = eir / 2 * 125 + eir % 2 * 63; - - _dess_egress_bs_frame_sw_to_hw(shaper->cbs, &cbs); - _dess_egress_bs_frame_hw_to_sw(cbs, &(shaper->cbs)); - - _dess_egress_bs_frame_sw_to_hw(shaper->ebs, &ebs); - _dess_egress_bs_frame_hw_to_sw(ebs, &(shaper->ebs)); - - unit = 1; - } - - data = 0; - HSL_REG_FIELD_SET(rv, dev_id, EG_SHAPER7, port_id, EG_PT, - (a_uint8_t *) (&data), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - - data = 0; - HSL_REG_FIELD_SET(rv, dev_id, EG_SHAPER7, port_id, EG_TS, - (a_uint8_t *) (&data), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - } - - if (0 == queue_id) - { - HSL_REG_FIELD_SET(rv, dev_id, EG_SHAPER0, port_id, EG_Q0_CIR, - (a_uint8_t *) (&cir), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - - HSL_REG_FIELD_SET(rv, dev_id, EG_SHAPER3, port_id, EG_Q0_EIR, - (a_uint8_t *) (&eir), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - - HSL_REG_FIELD_SET(rv, dev_id, EG_SHAPER6, port_id, EG_Q0_CBS, - (a_uint8_t *) (&cbs), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - - HSL_REG_FIELD_SET(rv, dev_id, EG_SHAPER6, port_id, EG_Q0_EBS, - (a_uint8_t *) (&ebs), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - - HSL_REG_FIELD_SET(rv, dev_id, EG_SHAPER7, port_id, EG_Q0_UNIT, - (a_uint8_t *) (&unit), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - } - else if (1 == queue_id) - { - HSL_REG_FIELD_SET(rv, dev_id, EG_SHAPER0, port_id, EG_Q1_CIR, - (a_uint8_t *) (&cir), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - - HSL_REG_FIELD_SET(rv, dev_id, EG_SHAPER3, port_id, EG_Q1_EIR, - (a_uint8_t *) (&eir), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - - HSL_REG_FIELD_SET(rv, dev_id, EG_SHAPER6, port_id, EG_Q1_CBS, - (a_uint8_t *) (&cbs), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - - HSL_REG_FIELD_SET(rv, dev_id, EG_SHAPER6, port_id, EG_Q1_EBS, - (a_uint8_t *) (&ebs), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - - HSL_REG_FIELD_SET(rv, dev_id, EG_SHAPER7, port_id, EG_Q1_UNIT, - (a_uint8_t *) (&unit), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - } - else if (2 == queue_id) - { - HSL_REG_FIELD_SET(rv, dev_id, EG_SHAPER1, port_id, EG_Q2_CIR, - (a_uint8_t *) (&cir), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - - HSL_REG_FIELD_SET(rv, dev_id, EG_SHAPER4, port_id, EG_Q2_EIR, - (a_uint8_t *) (&eir), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - - HSL_REG_FIELD_SET(rv, dev_id, EG_SHAPER6, port_id, EG_Q2_CBS, - (a_uint8_t *) (&cbs), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - - HSL_REG_FIELD_SET(rv, dev_id, EG_SHAPER6, port_id, EG_Q2_EBS, - (a_uint8_t *) (&ebs), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - - HSL_REG_FIELD_SET(rv, dev_id, EG_SHAPER7, port_id, EG_Q2_UNIT, - (a_uint8_t *) (&unit), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - } - else if (3 == queue_id) - { - HSL_REG_FIELD_SET(rv, dev_id, EG_SHAPER1, port_id, EG_Q3_CIR, - (a_uint8_t *) (&cir), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - - HSL_REG_FIELD_SET(rv, dev_id, EG_SHAPER4, port_id, EG_Q3_EIR, - (a_uint8_t *) (&eir), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - - HSL_REG_FIELD_SET(rv, dev_id, EG_SHAPER6, port_id, EG_Q3_CBS, - (a_uint8_t *) (&cbs), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - - HSL_REG_FIELD_SET(rv, dev_id, EG_SHAPER6, port_id, EG_Q3_EBS, - (a_uint8_t *) (&ebs), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - - HSL_REG_FIELD_SET(rv, dev_id, EG_SHAPER7, port_id, EG_Q3_UNIT, - (a_uint8_t *) (&unit), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - } - else if (4 == queue_id) - { - HSL_REG_FIELD_SET(rv, dev_id, EG_SHAPER2, port_id, EG_Q4_CIR, - (a_uint8_t *) (&cir), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - - HSL_REG_FIELD_SET(rv, dev_id, EG_SHAPER5, port_id, EG_Q4_EIR, - (a_uint8_t *) (&eir), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - - HSL_REG_FIELD_SET(rv, dev_id, EG_SHAPER7, port_id, EG_Q4_CBS, - (a_uint8_t *) (&cbs), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - - HSL_REG_FIELD_SET(rv, dev_id, EG_SHAPER7, port_id, EG_Q4_EBS, - (a_uint8_t *) (&ebs), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - - HSL_REG_FIELD_SET(rv, dev_id, EG_SHAPER7, port_id, EG_Q4_UNIT, - (a_uint8_t *) (&unit), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - } - else - { - HSL_REG_FIELD_SET(rv, dev_id, EG_SHAPER2, port_id, EG_Q5_CIR, - (a_uint8_t *) (&cir), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - - HSL_REG_FIELD_SET(rv, dev_id, EG_SHAPER5, port_id, EG_Q5_EIR, - (a_uint8_t *) (&eir), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - - HSL_REG_FIELD_SET(rv, dev_id, EG_SHAPER7, port_id, EG_Q5_CBS, - (a_uint8_t *) (&cbs), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - - HSL_REG_FIELD_SET(rv, dev_id, EG_SHAPER7, port_id, EG_Q5_EBS, - (a_uint8_t *) (&ebs), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - - HSL_REG_FIELD_SET(rv, dev_id, EG_SHAPER7, port_id, EG_Q5_UNIT, - (a_uint8_t *) (&unit), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - } - - return SW_OK; -} - -static sw_error_t -_dess_rate_queue_shaper_get(a_uint32_t dev_id, fal_port_t port_id, - fal_queue_t queue_id, a_bool_t * enable, - fal_egress_shaper_t * shaper) -{ - sw_error_t rv; - a_uint32_t data = 0, cir = 0, eir = 0, cbs = 0, ebs = 0; - - HSL_DEV_ID_CHECK(dev_id); - - if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU)) - { - return SW_BAD_PARAM; - } - - rv = _dess_rate_port_queue_check(port_id, queue_id); - SW_RTN_ON_ERROR(rv); - - aos_mem_zero(shaper, sizeof (fal_egress_shaper_t)); - - HSL_REG_FIELD_GET(rv, dev_id, EG_SHAPER7, port_id, EG_PT, - (a_uint8_t *) (&data), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - - if (data) - { - *enable = A_FALSE; - return SW_OK; - } - - if (0 == queue_id) - { - HSL_REG_FIELD_GET(rv, dev_id, EG_SHAPER0, port_id, EG_Q0_CIR, - (a_uint8_t *) (&cir), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - - HSL_REG_FIELD_GET(rv, dev_id, EG_SHAPER3, port_id, EG_Q0_EIR, - (a_uint8_t *) (&eir), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - - HSL_REG_FIELD_GET(rv, dev_id, EG_SHAPER6, port_id, EG_Q0_CBS, - (a_uint8_t *) (&cbs), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - - HSL_REG_FIELD_GET(rv, dev_id, EG_SHAPER6, port_id, EG_Q0_EBS, - (a_uint8_t *) (&ebs), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - - HSL_REG_FIELD_GET(rv, dev_id, EG_SHAPER7, port_id, EG_Q0_UNIT, - (a_uint8_t *) (&data), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - } - else if (1 == queue_id) - { - HSL_REG_FIELD_GET(rv, dev_id, EG_SHAPER0, port_id, EG_Q1_CIR, - (a_uint8_t *) (&cir), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - - HSL_REG_FIELD_GET(rv, dev_id, EG_SHAPER3, port_id, EG_Q1_EIR, - (a_uint8_t *) (&eir), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - - HSL_REG_FIELD_GET(rv, dev_id, EG_SHAPER6, port_id, EG_Q1_CBS, - (a_uint8_t *) (&cbs), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - - HSL_REG_FIELD_GET(rv, dev_id, EG_SHAPER6, port_id, EG_Q1_EBS, - (a_uint8_t *) (&ebs), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - - HSL_REG_FIELD_GET(rv, dev_id, EG_SHAPER7, port_id, EG_Q1_UNIT, - (a_uint8_t *) (&data), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - } - else if (2 == queue_id) - { - HSL_REG_FIELD_GET(rv, dev_id, EG_SHAPER1, port_id, EG_Q2_CIR, - (a_uint8_t *) (&cir), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - - HSL_REG_FIELD_GET(rv, dev_id, EG_SHAPER4, port_id, EG_Q2_EIR, - (a_uint8_t *) (&eir), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - - HSL_REG_FIELD_GET(rv, dev_id, EG_SHAPER6, port_id, EG_Q2_CBS, - (a_uint8_t *) (&cbs), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - - HSL_REG_FIELD_GET(rv, dev_id, EG_SHAPER6, port_id, EG_Q2_EBS, - (a_uint8_t *) (&ebs), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - - HSL_REG_FIELD_GET(rv, dev_id, EG_SHAPER7, port_id, EG_Q2_UNIT, - (a_uint8_t *) (&data), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - } - else if (3 == queue_id) - { - HSL_REG_FIELD_GET(rv, dev_id, EG_SHAPER1, port_id, EG_Q3_CIR, - (a_uint8_t *) (&cir), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - - HSL_REG_FIELD_GET(rv, dev_id, EG_SHAPER4, port_id, EG_Q3_EIR, - (a_uint8_t *) (&eir), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - - HSL_REG_FIELD_GET(rv, dev_id, EG_SHAPER6, port_id, EG_Q3_CBS, - (a_uint8_t *) (&cbs), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - - HSL_REG_FIELD_GET(rv, dev_id, EG_SHAPER6, port_id, EG_Q3_EBS, - (a_uint8_t *) (&ebs), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - - HSL_REG_FIELD_GET(rv, dev_id, EG_SHAPER7, port_id, EG_Q3_UNIT, - (a_uint8_t *) (&data), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - } - else if (4 == queue_id) - { - HSL_REG_FIELD_GET(rv, dev_id, EG_SHAPER2, port_id, EG_Q4_CIR, - (a_uint8_t *) (&cir), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - - HSL_REG_FIELD_GET(rv, dev_id, EG_SHAPER5, port_id, EG_Q4_EIR, - (a_uint8_t *) (&eir), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - - HSL_REG_FIELD_GET(rv, dev_id, EG_SHAPER7, port_id, EG_Q4_CBS, - (a_uint8_t *) (&cbs), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - - HSL_REG_FIELD_GET(rv, dev_id, EG_SHAPER7, port_id, EG_Q4_EBS, - (a_uint8_t *) (&ebs), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - - HSL_REG_FIELD_GET(rv, dev_id, EG_SHAPER7, port_id, EG_Q4_UNIT, - (a_uint8_t *) (&data), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - } - else - { - HSL_REG_FIELD_GET(rv, dev_id, EG_SHAPER2, port_id, EG_Q5_CIR, - (a_uint8_t *) (&cir), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - - HSL_REG_FIELD_GET(rv, dev_id, EG_SHAPER5, port_id, EG_Q5_EIR, - (a_uint8_t *) (&eir), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - - HSL_REG_FIELD_GET(rv, dev_id, EG_SHAPER7, port_id, EG_Q5_CBS, - (a_uint8_t *) (&cbs), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - - HSL_REG_FIELD_GET(rv, dev_id, EG_SHAPER7, port_id, EG_Q5_EBS, - (a_uint8_t *) (&ebs), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - - HSL_REG_FIELD_GET(rv, dev_id, EG_SHAPER7, port_id, EG_Q5_UNIT, - (a_uint8_t *) (&data), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - } - - if ((0x7fff == cir) && (0x7fff == eir)) - { - *enable = A_FALSE; - return SW_OK; - } - - *enable = A_TRUE; - if (data) - { - shaper->meter_unit = FAL_FRAME_BASED; - shaper->cir = cir / 2 * 125 + cir % 2 * 63; - shaper->eir = eir / 2 * 125 + eir % 2 * 63; - _dess_egress_bs_frame_hw_to_sw(cbs, &(shaper->cbs)); - _dess_egress_bs_frame_hw_to_sw(ebs, &(shaper->ebs)); - } - else - { - shaper->meter_unit = FAL_BYTE_BASED; - shaper->cir = cir << 5; - shaper->eir = eir << 5; - _dess_egress_bs_byte_hw_to_sw(cbs, &(shaper->cbs)); - _dess_egress_bs_byte_hw_to_sw(ebs, &(shaper->ebs)); - } - - return SW_OK; -} - -static sw_error_t -_dess_rate_acl_policer_set(a_uint32_t dev_id, a_uint32_t policer_id, - fal_acl_policer_t * policer) -{ - sw_error_t rv; - a_uint32_t ts, cir, eir, cbs = 0, ebs = 0, addr, data[2] = { 0 }; - - HSL_DEV_ID_CHECK(dev_id); - - if (DESS_MAX_POLICER_ID < policer_id) - { - return SW_BAD_PARAM; - } - - if (A_TRUE == policer->counter_mode) - { - addr = ACL_POLICER_CNT_SEL_ADDR; - data[0] = 0x1; - HSL_REG_FIELD_GEN_SET(rv, dev_id, addr, 1, policer_id, - (a_uint8_t *) (&data[0]), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - - addr = ACL_POLICER_CNT_MODE_ADDR; - if (FAL_FRAME_BASED == policer->meter_unit) - { - data[0] = 0x0; - } - else - { - data[0] = 0x1; - } - HSL_REG_FIELD_GEN_SET(rv, dev_id, addr, 1, policer_id, - (a_uint8_t *) (&data[0]), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - - addr = ACL_POLICER_CNT_RST_ADDR; - data[0] = 0x1; - HSL_REG_FIELD_GEN_SET(rv, dev_id, addr, 1, policer_id, - (a_uint8_t *) (&data[0]), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - - data[0] = 0x0; - HSL_REG_FIELD_GEN_SET(rv, dev_id, addr, 1, policer_id, - (a_uint8_t *) (&data[0]), sizeof (a_uint32_t)); - return rv; - } - - addr = ACL_POLICER_CNT_SEL_ADDR; - data[0] = 0x0; - HSL_REG_FIELD_GEN_SET(rv, dev_id, addr, 1, policer_id, - (a_uint8_t *) (&data[0]), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - - if (FAL_BYTE_BASED == policer->meter_unit) - { - cir = policer->cir >> 5; - policer->cir = cir << 5; - - eir = policer->eir >> 5; - policer->eir = eir << 5; - - _dess_ingress_bs_byte_sw_to_hw(policer->cbs, &cbs); - _dess_ingress_bs_byte_hw_to_sw(cbs, &(policer->cbs)); - - _dess_ingress_bs_byte_sw_to_hw(policer->ebs, &ebs); - _dess_ingress_bs_byte_hw_to_sw(ebs, &(policer->ebs)); - - SW_SET_REG_BY_FIELD(ACL_POLICER1, ACL_UNIT, 0, data[1]); - } - else if (FAL_FRAME_BASED == policer->meter_unit) - { - cir = (policer->cir * 2) / 125; - policer->cir = cir / 2 * 125 + cir % 2 * 63; - - eir = (policer->eir * 2) / 125; - policer->eir = eir / 2 * 125 + eir % 2 * 63; - - _dess_ingress_bs_frame_sw_to_hw(policer->cbs, &cbs); - _dess_ingress_bs_frame_hw_to_sw(cbs, &(policer->cbs)); - - _dess_ingress_bs_frame_sw_to_hw(policer->ebs, &ebs); - _dess_ingress_bs_frame_hw_to_sw(ebs, &(policer->ebs)); - - SW_SET_REG_BY_FIELD(ACL_POLICER1, ACL_UNIT, 1, data[1]); - } - else - { - return SW_BAD_PARAM; - } - - SW_SET_REG_BY_FIELD(ACL_POLICER0, ACL_CIR, cir, data[0]); - SW_SET_REG_BY_FIELD(ACL_POLICER0, ACL_CBS, cbs, data[0]); - SW_SET_REG_BY_FIELD(ACL_POLICER1, ACL_EIR, eir, data[1]); - SW_SET_REG_BY_FIELD(ACL_POLICER1, ACL_EBS, ebs, data[1]); - - if (A_TRUE == policer->deficit_en) - { - SW_SET_REG_BY_FIELD(ACL_POLICER1, ACL_BORROW, 1, data[1]); - } - - if (A_TRUE == policer->color_mode) - { - SW_SET_REG_BY_FIELD(ACL_POLICER1, ACL_CM, 1, data[1]); - } - - if (A_TRUE == policer->couple_flag) - { - SW_SET_REG_BY_FIELD(ACL_POLICER1, ACL_CF, 1, data[1]); - } - - _dess_rate_ts_parse(policer->meter_interval, &ts); - SW_SET_REG_BY_FIELD(ACL_POLICER1, ACL_TS, ts, data[1]); - - HSL_REG_ENTRY_SET(rv, dev_id, ACL_POLICER0, policer_id, - (a_uint8_t *) (&data[0]), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - - HSL_REG_ENTRY_SET(rv, dev_id, ACL_POLICER1, policer_id, - (a_uint8_t *) (&data[1]), sizeof (a_uint32_t)); - - return rv; -} - -static sw_error_t -_dess_rate_acl_policer_get(a_uint32_t dev_id, a_uint32_t policer_id, - fal_acl_policer_t * policer) -{ - sw_error_t rv; - a_uint32_t unit, ts, cir, eir, cbs, ebs, addr, data[2] = {0}; - - HSL_DEV_ID_CHECK(dev_id); - - if (DESS_MAX_POLICER_ID < policer_id) - { - return SW_BAD_PARAM; - } - - aos_mem_zero(policer, sizeof (policer)); - - addr = ACL_POLICER_CNT_SEL_ADDR; - HSL_REG_FIELD_GEN_GET(rv, dev_id, addr, 1, policer_id, - (a_uint8_t *) (&data[0]), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - - if (data[0]) - { - policer->counter_mode = A_TRUE; - - addr = ACL_POLICER_CNT_MODE_ADDR; - HSL_REG_FIELD_GEN_GET(rv, dev_id, addr, 1, policer_id, - (a_uint8_t *) (&data[0]), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - - if (data[0]) - { - policer->meter_unit = FAL_BYTE_BASED; - } - else - { - policer->meter_unit = FAL_FRAME_BASED; - } - - HSL_REG_ENTRY_GET(rv, dev_id, ACL_COUNTER0, policer_id, - (a_uint8_t *) (&data[0]), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - - HSL_REG_ENTRY_GET(rv, dev_id, ACL_COUNTER1, policer_id, - (a_uint8_t *) (&data[1]), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - - policer->counter_low = data[0]; - policer->counter_high = data[1]; - - return SW_OK; - } - - HSL_REG_ENTRY_GET(rv, dev_id, ACL_POLICER0, policer_id, - (a_uint8_t *) (&data[0]), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - - HSL_REG_ENTRY_GET(rv, dev_id, ACL_POLICER1, policer_id, - (a_uint8_t *) (&data[1]), sizeof (a_uint32_t)); - - SW_GET_FIELD_BY_REG(ACL_POLICER0, ACL_CIR, cir, data[0]); - SW_GET_FIELD_BY_REG(ACL_POLICER0, ACL_CBS, cbs, data[0]); - SW_GET_FIELD_BY_REG(ACL_POLICER1, ACL_EIR, eir, data[1]); - SW_GET_FIELD_BY_REG(ACL_POLICER1, ACL_EBS, ebs, data[1]); - SW_GET_FIELD_BY_REG(ACL_POLICER1, ACL_UNIT, unit, data[1]); - if (unit) - { - policer->meter_unit = FAL_FRAME_BASED; - policer->cir = cir / 2 * 125 + cir % 2 * 63; - policer->eir = eir / 2 * 125 + eir % 2 * 63; - _dess_ingress_bs_frame_hw_to_sw(cbs, &(policer->cbs)); - _dess_ingress_bs_frame_hw_to_sw(ebs, &(policer->ebs)); - - } - else - { - policer->meter_unit = FAL_BYTE_BASED; - policer->cir = cir << 5; - policer->eir = eir << 5; - _dess_ingress_bs_byte_hw_to_sw(cbs, &(policer->cbs)); - _dess_ingress_bs_byte_hw_to_sw(ebs, &(policer->ebs)); - } - - SW_GET_FIELD_BY_REG(ACL_POLICER1, ACL_BORROW, policer->deficit_en, - data[1]); - SW_GET_FIELD_BY_REG(ACL_POLICER1, ACL_CF, policer->couple_flag, data[1]); - SW_GET_FIELD_BY_REG(ACL_POLICER1, ACL_CM, policer->color_mode, data[1]); - - SW_GET_FIELD_BY_REG(ACL_POLICER1, ACL_TS, ts, data[1]); - _dess_rate_ts_reparse(ts, &(policer->meter_interval)); - - return SW_OK; -} - -sw_error_t -_dess_rate_port_add_rate_byte_set(a_uint32_t dev_id, fal_port_t port_id, - a_uint32_t number) -{ - a_uint32_t val = number; - sw_error_t rv; - - HSL_DEV_ID_CHECK(dev_id); - - if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU)) - { - return SW_BAD_PARAM; - } - - if (val>255) - return SW_BAD_PARAM; - - HSL_REG_FIELD_SET(rv, dev_id, INGRESS_POLICER0, port_id, ADD_RATE_BYTE, - (a_uint8_t *) (&val), sizeof (a_uint32_t)); - - return rv; -} - -sw_error_t -_dess_rate_port_add_rate_byte_get(a_uint32_t dev_id, fal_port_t port_id, - a_uint32_t *number) -{ - a_uint32_t val = 0; - sw_error_t rv = SW_OK; - - HSL_DEV_ID_CHECK(dev_id); - - if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU)) - { - return SW_BAD_PARAM; - } - - - HSL_REG_FIELD_GET(rv, dev_id, INGRESS_POLICER0, port_id, ADD_RATE_BYTE, - (a_uint8_t *) (&val), sizeof (a_uint32_t)); - *number = val; - - return rv; -} - -sw_error_t -_dess_rate_port_gol_flow_en_set(a_uint32_t dev_id, fal_port_t port_id, - a_bool_t enable) -{ - a_uint32_t val = 0; - sw_error_t rv; - - HSL_DEV_ID_CHECK(dev_id); - - if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU)) - { - return SW_BAD_PARAM; - } - - HSL_REG_ENTRY_GET(rv, dev_id, QM_CTRL_REG, 0, - (a_uint8_t *) (&val), sizeof (a_uint32_t)); - - SW_RTN_ON_ERROR(rv); - - - if (A_TRUE == enable) - { - val |= (0x1<<(16+port_id)); - } - else if (A_FALSE == enable) - { - val &= ~(0x1<<(16+port_id)); - } - else - { - return SW_BAD_PARAM; - } - - HSL_REG_ENTRY_SET(rv, dev_id, QM_CTRL_REG, 0, - (a_uint8_t *) (&val), sizeof (a_uint32_t)); - - return rv; -} - -sw_error_t -_dess_rate_port_gol_flow_en_get(a_uint32_t dev_id, fal_port_t port_id, - a_bool_t* enable) -{ - a_uint32_t val = 0; - sw_error_t rv; - - HSL_DEV_ID_CHECK(dev_id); - - if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU)) - { - return SW_BAD_PARAM; - } - - HSL_REG_ENTRY_GET(rv, dev_id, QM_CTRL_REG, 0, - (a_uint8_t *) (&val), sizeof (a_uint32_t)); - - SW_RTN_ON_ERROR(rv); - - if (val&(0x1<<(16+port_id))) - { - *enable = A_TRUE; - } - else - { - *enable = A_FALSE; - } - - return rv; -} - - - -/** - * @brief Set port ingress policer parameters on one particular port. - * @details Comments: - The granularity of speed is 32kbps or 62.5fps. - Because of hardware granularity function will return actual speed in hardware. - When disable port ingress policer input parameter speed is meaningless. - * @param[in] dev_id device id - * @param[in] port_id port id - * @param[in] policer port ingress policer parameter - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -dess_rate_port_policer_set(a_uint32_t dev_id, fal_port_t port_id, - fal_port_policer_t * policer) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _dess_rate_port_policer_set(dev_id, port_id, policer); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Get port ingress policer parameters on one particular port. - * @details Comments: - The granularity of speed is 32kbps or 62.5fps. - Because of hardware granularity function will return actual speed in hardware. - When disable port ingress policer input parameter speed is meaningless. - * @param[in] dev_id device id - * @param[in] port_id port id - * @param[out] policer port ingress policer parameter - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -dess_rate_port_policer_get(a_uint32_t dev_id, fal_port_t port_id, - fal_port_policer_t * policer) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _dess_rate_port_policer_get(dev_id, port_id, policer); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Set port egress shaper parameters on one particular port. - * @details Comments: - The granularity of speed is 32kbps or 62.5fps. - Because of hardware granularity function will return actual speed in hardware. - When disable port egress shaper parameters is meaningless. - * @param[in] port_id port id - * @param[in] enable A_TRUE or A_FALSE - * @param[in] shaper port egress shaper parameter - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -dess_rate_port_shaper_set(a_uint32_t dev_id, fal_port_t port_id, - a_bool_t enable, fal_egress_shaper_t * shaper) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _dess_rate_port_shaper_set(dev_id, port_id, enable, shaper); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Get port egress shaper parameters on one particular port. - * @details Comments: - The granularity of speed is 32kbps or 62.5fps. - Because of hardware granularity function will return actual speed in hardware. - When disable port egress shaper parameters is meaningless. - * @param[in] dev_id device id - * @param[in] port_id port id - * @param[out] enable A_TRUE or A_FALSE - * @param[out] shaper port egress shaper parameter - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -dess_rate_port_shaper_get(a_uint32_t dev_id, fal_port_t port_id, - a_bool_t * enable, fal_egress_shaper_t * shaper) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _dess_rate_port_shaper_get(dev_id, port_id, enable, shaper); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Set queue egress shaper parameters on one particular port. - * @details Comments: - The granularity of speed is 32kbps or 62.5fps. - Because of hardware granularity function will return actual speed in hardware. - When disable queue egress shaper parameters is meaningless. - * @param[in] port_id port id - * @param[in] queue_id queue id - * @param[in] enable A_TRUE or A_FALSE - * @param[in] shaper port egress shaper parameter - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -dess_rate_queue_shaper_set(a_uint32_t dev_id, fal_port_t port_id, - fal_queue_t queue_id, a_bool_t enable, - fal_egress_shaper_t * shaper) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _dess_rate_queue_shaper_set(dev_id, port_id, queue_id, enable, shaper); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Get queue egress shaper parameters on one particular port. - * @details Comments: - The granularity of speed is 32kbps or 62.5fps. - Because of hardware granularity function will return actual speed in hardware. - When disable queue egress shaper parameters is meaningless. - * @param[in] port_id port id - * @param[in] queue_id queue id - * @param[out] enable A_TRUE or A_FALSE - * @param[out] shaper port egress shaper parameter - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -dess_rate_queue_shaper_get(a_uint32_t dev_id, fal_port_t port_id, - fal_queue_t queue_id, a_bool_t * enable, - fal_egress_shaper_t * shaper) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _dess_rate_queue_shaper_get(dev_id, port_id, queue_id, enable, shaper); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Set ACL ingress policer parameters. - * @details Comments: - The granularity of speed is 32kbps or 62.5fps. - Because of hardware granularity function will return actual speed in hardware. - * @param[in] dev_id device id - * @param[in] policer_id ACL policer id - * @param[in] policer ACL ingress policer parameters - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -dess_rate_acl_policer_set(a_uint32_t dev_id, a_uint32_t policer_id, - fal_acl_policer_t * policer) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _dess_rate_acl_policer_set(dev_id, policer_id, policer); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Get ACL ingress policer parameters. - * @details Comments: - The granularity of speed is 32kbps or 62.5fps. - Because of hardware granularity function will return actual speed in hardware. - * @param[in] dev_id device id - * @param[in] policer_id ACL policer id - * @param[in] policer ACL ingress policer parameters - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -dess_rate_acl_policer_get(a_uint32_t dev_id, a_uint32_t policer_id, - fal_acl_policer_t * policer) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _dess_rate_acl_policer_get(dev_id, policer_id, policer); - HSL_API_UNLOCK; - return rv; -} - -HSL_LOCAL sw_error_t -dess_rate_port_add_rate_byte_set(a_uint32_t dev_id, fal_port_t port_id, - a_uint32_t number) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _dess_rate_port_add_rate_byte_set(dev_id, port_id, number); - HSL_API_UNLOCK; - return rv; -} - -HSL_LOCAL sw_error_t -dess_rate_port_add_rate_byte_get(a_uint32_t dev_id, fal_port_t port_id, - a_uint32_t *number) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _dess_rate_port_add_rate_byte_get(dev_id, port_id, number); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Set status of port global flow control when global threshold is reached. - * @param[in] dev_id device id - * @param[in] port_id port id - * @param[in] enable A_TRUE or A_FALSE - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -dess_rate_port_gol_flow_en_set(a_uint32_t dev_id, fal_port_t port_id, - a_bool_t enable) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _dess_rate_port_gol_flow_en_set(dev_id, port_id, enable); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief get status of port global flow control when global threshold is reached. - * @param[in] dev_id device id - * @param[in] port_id port id - * @param[out] enable A_TRUE or A_FALSE - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -dess_rate_port_gol_flow_en_get(a_uint32_t dev_id, fal_port_t port_id, - a_bool_t* enable) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _dess_rate_port_gol_flow_en_get(dev_id, port_id, enable); - HSL_API_UNLOCK; - return rv; -} - - - -sw_error_t -dess_rate_init(a_uint32_t dev_id) -{ - HSL_DEV_ID_CHECK(dev_id); - -#ifndef HSL_STANDALONG - { - hsl_api_t *p_api; - - SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id)); - - p_api->rate_port_policer_set = dess_rate_port_policer_set; - p_api->rate_port_policer_get = dess_rate_port_policer_get; - p_api->rate_port_shaper_set = dess_rate_port_shaper_set; - p_api->rate_port_shaper_get = dess_rate_port_shaper_get; - p_api->rate_queue_shaper_set = dess_rate_queue_shaper_set; - p_api->rate_queue_shaper_get = dess_rate_queue_shaper_get; - p_api->rate_acl_policer_set = dess_rate_acl_policer_set; - p_api->rate_acl_policer_get = dess_rate_acl_policer_get; - p_api->rate_port_gol_flow_en_set = dess_rate_port_gol_flow_en_set; - p_api->rate_port_gol_flow_en_get = dess_rate_port_gol_flow_en_get; - p_api->rate_port_add_rate_byte_set=dess_rate_port_add_rate_byte_set; - p_api->rate_port_add_rate_byte_get=dess_rate_port_add_rate_byte_get; - } -#endif - - return SW_OK; -} - -/** - * @} - */ - diff --git a/feeds/ipq807x/qca-ssdk/src/src/hsl/dess/dess_reg_access.c b/feeds/ipq807x/qca-ssdk/src/src/hsl/dess/dess_reg_access.c deleted file mode 100755 index 734b2e73a..000000000 --- a/feeds/ipq807x/qca-ssdk/src/src/hsl/dess/dess_reg_access.c +++ /dev/null @@ -1,644 +0,0 @@ -/* - * Copyright (c) 2014, 2016-2017, The Linux Foundation. All rights reserved. - * Permission to use, copy, modify, and/or distribute this software for - * any purpose with or without fee is hereby granted, provided that the - * above copyright notice and this permission notice appear in all copies. - * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES - * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR - * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES - * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN - * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT - * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. - */ - - -#include "sw.h" -#include "hsl.h" -#include "hsl_dev.h" -#include "sd.h" -#include "dess_reg_access.h" -#include "dess_psgmii.h" - -#if 0 -#include -#include -#include -#include -#include -#endif - -static hsl_access_mode reg_mode; - -#if defined(API_LOCK) -static aos_lock_t mdio_lock; -#define MDIO_LOCKER_INIT aos_lock_init(&mdio_lock) -#define MDIO_LOCKER_LOCK aos_lock(&mdio_lock) -#define MDIO_LOCKER_UNLOCK aos_unlock(&mdio_lock) -#else -#define MDIO_LOCKER_INIT -#define MDIO_LOCKER_LOCK -#define MDIO_LOCKER_UNLOCK -#endif - -#if defined(REG_ACCESS_SPEEDUP) -static a_uint32_t mdio_base_addr = 0xffffffff; -#endif - -extern void ssdk_psgmii_self_test(a_uint32_t dev_id, a_bool_t enable, a_uint32_t times, a_uint32_t *result); -extern void clear_self_test_config(a_uint32_t dev_id); - -static sw_error_t -_dess_mdio_reg_get(a_uint32_t dev_id, a_uint32_t reg_addr, - a_uint8_t value[], a_uint32_t value_len) -{ -#if 0 - a_uint32_t reg_word_addr; - a_uint32_t phy_addr, reg_val; - a_uint16_t phy_val, tmp_val; - a_uint8_t phy_reg; - sw_error_t rv; -#else - a_uint32_t reg_val; -#endif - - if (value_len != sizeof (a_uint32_t)) - return SW_BAD_LEN; - -#if 0 - /* change reg_addr to 16-bit word address, 32-bit aligned */ - reg_word_addr = (reg_addr & 0xfffffffc) >> 1; - - /* configure register high address */ - phy_addr = 0x18; - phy_reg = 0x0; - phy_val = (a_uint16_t) ((reg_word_addr >> 8) & 0x3ff); /* bit16-8 of reg address */ - -#if defined(REG_ACCESS_SPEEDUP) - if (phy_val != mdio_base_addr) - { - rv = sd_reg_mdio_set(dev_id, phy_addr, phy_reg, phy_val); - SW_RTN_ON_ERROR(rv); - - mdio_base_addr = phy_val; - } -#else - rv = sd_reg_mdio_set(dev_id, phy_addr, phy_reg, phy_val); - SW_RTN_ON_ERROR(rv); -#endif - - /* For some registers such as MIBs, since it is read/clear, we should */ - /* read the lower 16-bit register then the higher one */ - - /* read register in lower address */ - phy_addr = 0x10 | ((reg_word_addr >> 5) & 0x7); /* bit7-5 of reg address */ - phy_reg = (a_uint8_t) (reg_word_addr & 0x1f); /* bit4-0 of reg address */ - rv = sd_reg_mdio_get(dev_id, phy_addr, phy_reg, &tmp_val); - SW_RTN_ON_ERROR(rv); - reg_val = tmp_val; - - /* read register in higher address */ - reg_word_addr++; - phy_addr = 0x10 | ((reg_word_addr >> 5) & 0x7); /* bit7-5 of reg address */ - phy_reg = (a_uint8_t) (reg_word_addr & 0x1f); /* bit4-0 of reg address */ - rv = sd_reg_mdio_get(dev_id, phy_addr, phy_reg, &tmp_val); - SW_RTN_ON_ERROR(rv); - reg_val |= (((a_uint32_t)tmp_val) << 16); -#else - reg_val = sd_reg_mii_get(dev_id, reg_addr); -#endif - aos_mem_copy(value, ®_val, sizeof (a_uint32_t)); - - return SW_OK; -} - -static sw_error_t -_dess_mdio_reg_set(a_uint32_t dev_id, a_uint32_t reg_addr, a_uint8_t value[], - a_uint32_t value_len) -{ -#if 0 - a_uint32_t reg_word_addr; - a_uint32_t phy_addr, reg_val; - a_uint16_t phy_val; - a_uint8_t phy_reg; - sw_error_t rv; -#else - a_uint32_t reg_val = 0; -#endif - - - if (value_len != sizeof (a_uint32_t)) - return SW_BAD_LEN; - - aos_mem_copy(®_val, value, sizeof (a_uint32_t)); - -#if 0 - /* change reg_addr to 16-bit word address, 32-bit aligned */ - reg_word_addr = (reg_addr & 0xfffffffc) >> 1; - - /* configure register high address */ - phy_addr = 0x18; - phy_reg = 0x0; - phy_val = (a_uint16_t) ((reg_word_addr >> 8) & 0x3ff); /* bit16-8 of reg address */ - -#if defined(REG_ACCESS_SPEEDUP) - if (phy_val != mdio_base_addr) - { - rv = sd_reg_mdio_set(dev_id, phy_addr, phy_reg, phy_val); - SW_RTN_ON_ERROR(rv); - - mdio_base_addr = phy_val; - } -#else - rv = sd_reg_mdio_set(dev_id, phy_addr, phy_reg, phy_val); - SW_RTN_ON_ERROR(rv); -#endif - - /* For some registers such as ARL and VLAN, since they include BUSY bit */ - /* in higher address, we should write the lower 16-bit register then the */ - /* higher one */ - - /* write register in lower address */ - phy_addr = 0x10 | ((reg_word_addr >> 5) & 0x7); /* bit7-5 of reg address */ - phy_reg = (a_uint8_t) (reg_word_addr & 0x1f); /* bit4-0 of reg address */ - phy_val = (a_uint16_t) (reg_val & 0xffff); - rv = sd_reg_mdio_set(dev_id, phy_addr, phy_reg, phy_val); - SW_RTN_ON_ERROR(rv); - - /* write register in higher address */ - reg_word_addr++; - phy_addr = 0x10 | ((reg_word_addr >> 5) & 0x7); /* bit7-5 of reg address */ - phy_reg = (a_uint8_t) (reg_word_addr & 0x1f); /* bit4-0 of reg address */ - phy_val = (a_uint16_t) ((reg_val >> 16) & 0xffff); - rv = sd_reg_mdio_set(dev_id, phy_addr, phy_reg, phy_val); - SW_RTN_ON_ERROR(rv); -#else - sd_reg_mii_set(dev_id, reg_addr, reg_val); -#endif - return SW_OK; -} - -sw_error_t -dess_phy_get(a_uint32_t dev_id, a_uint32_t phy_addr, - a_uint32_t reg, a_uint16_t * value) -{ - sw_error_t rv; - - MDIO_LOCKER_LOCK; - rv = sd_reg_mdio_get(dev_id, phy_addr, reg, value); - MDIO_LOCKER_UNLOCK; - return rv; -} - -sw_error_t -dess_phy_set(a_uint32_t dev_id, a_uint32_t phy_addr, - a_uint32_t reg, a_uint16_t value) -{ - sw_error_t rv; - - MDIO_LOCKER_LOCK; - rv = sd_reg_mdio_set(dev_id, phy_addr, reg, value); - MDIO_LOCKER_UNLOCK; - return rv; -} - -sw_error_t -dess_reg_get(a_uint32_t dev_id, a_uint32_t reg_addr, a_uint8_t value[], - a_uint32_t value_len) -{ - sw_error_t rv; - - MDIO_LOCKER_LOCK; - if (HSL_MDIO == reg_mode) - { - rv = _dess_mdio_reg_get(dev_id, reg_addr, value, value_len); - } - else - { - rv = sd_reg_hdr_get(dev_id, reg_addr, value, value_len); - } - MDIO_LOCKER_UNLOCK; - - return rv; -} - -sw_error_t -dess_reg_set(a_uint32_t dev_id, a_uint32_t reg_addr, a_uint8_t value[], - a_uint32_t value_len) -{ - sw_error_t rv; -#if 0 - unsigned long flags; - - struct file *filp; - // mm_segment_t fs; - a_uint32_t rt_value = 0; - a_uint32_t write_flag = 0; - char s[20]= {0}; - a_uint32_t tmp_val = *((a_uint32_t *) value); -#else - a_uint32_t rt_value = 0; -#endif - - /*get MODULE_EN reg rsv */ - SW_RTN_ON_ERROR(dess_reg_get(dev_id, 0x30,(void *)&rt_value,4)); -// write_flag = (rt_value>>15) & 0x1; - - MDIO_LOCKER_LOCK; - if (HSL_MDIO == reg_mode) - { - rv = _dess_mdio_reg_set(dev_id, reg_addr, value, value_len); - } - else - { - rv = sd_reg_hdr_set(dev_id, reg_addr, value, value_len); - } - MDIO_LOCKER_UNLOCK; - -#if 0 - if(write_flag) - { - filp = filp_open("/tmp/asic_output", O_RDWR|O_APPEND, 0644); - if(IS_ERR(filp)) - { - printk("open error...\n"); - return; - } - - fs=get_fs(); - - set_fs(KERNEL_DS); - sprintf(s,"%08x %08x\n",reg_addr,tmp_val); - filp->f_op->write(filp, s, strlen(s),&filp->f_pos); - - set_fs(fs); - - filp_close(filp,NULL); - } -#endif - - return rv; -} - -sw_error_t -dess_reg_field_get(a_uint32_t dev_id, a_uint32_t reg_addr, - a_uint32_t bit_offset, a_uint32_t field_len, - a_uint8_t value[], a_uint32_t value_len) -{ - a_uint32_t reg_val = 0; - - if ((bit_offset >= 32 || (field_len > 32)) || (field_len == 0)) - return SW_OUT_OF_RANGE; - - if (value_len != sizeof (a_uint32_t)) - return SW_BAD_LEN; - - SW_RTN_ON_ERROR(dess_reg_get(dev_id, reg_addr, (a_uint8_t *) & reg_val, sizeof (a_uint32_t))); - - - if(32 == field_len) - { - *((a_uint32_t *) value) = reg_val; - } - else - { - *((a_uint32_t *) value) = SW_REG_2_FIELD(reg_val, bit_offset, field_len); - } - return SW_OK; -} - -sw_error_t -dess_reg_field_set(a_uint32_t dev_id, a_uint32_t reg_addr, - a_uint32_t bit_offset, a_uint32_t field_len, - const a_uint8_t value[], a_uint32_t value_len) -{ - a_uint32_t reg_val = 0; - a_uint32_t field_val = *((a_uint32_t *) value); - - if ((bit_offset >= 32 || (field_len > 32)) || (field_len == 0)) - return SW_OUT_OF_RANGE; - - if (value_len != sizeof (a_uint32_t)) - return SW_BAD_LEN; - - SW_RTN_ON_ERROR(dess_reg_get(dev_id, reg_addr, (a_uint8_t *) & reg_val, sizeof (a_uint32_t))); - - if(32 == field_len) - { - reg_val = field_val; - } - else - { - SW_REG_SET_BY_FIELD_U32(reg_val, field_val, bit_offset, field_len); - } - - - SW_RTN_ON_ERROR(dess_reg_set(dev_id, reg_addr, (a_uint8_t *) & reg_val, sizeof (a_uint32_t))); - - return SW_OK; -} - -static sw_error_t -_dess_regsiter_dump(a_uint32_t dev_id,a_uint32_t register_idx, fal_reg_dump_t * reg_dump) -{ - sw_error_t rv = SW_OK; - typedef struct { - a_uint32_t reg_base; - a_uint32_t reg_end; - char name[30]; - } regdump; - - regdump reg_dumps[8] = - { - {0x0, 0xE4, "0.Global control registers"}, - {0x100, 0x168, "1.EEE control registers"}, - {0x200, 0x270, "2.Parser control registers"}, - {0x400, 0x474, "3.ACL control registers"}, - {0x600, 0x718, "4.Lookup control registers"}, - {0x800, 0xb70, "5.QM control registers"}, - {0xc00, 0xc80, "6.PKT edit control registers"}, - {0x820, 0x820, "7.QM debug registers"} - }; - - a_uint32_t dump_addr, reg_count, reg_val = 0; - switch (register_idx) - { - case 0: - case 1: - case 2: - case 3: - case 4: - case 5: - case 6: - reg_count = 0; - for (dump_addr = reg_dumps[register_idx].reg_base; dump_addr <= reg_dumps[register_idx].reg_end; reg_count++) - { - rv = dess_reg_get(dev_id, dump_addr, (a_uint8_t *) & reg_val, sizeof (a_uint32_t)); - reg_dump->reg_value[reg_count] = reg_val; - dump_addr += 4; - } - reg_dump->reg_count = reg_count; - reg_dump->reg_base = reg_dumps[register_idx].reg_base; - reg_dump->reg_end = reg_dumps[register_idx].reg_end; - snprintf((char *)reg_dump->reg_name,sizeof(reg_dump->reg_name),"%s",reg_dumps[register_idx].name); - break; - default: - return SW_BAD_PARAM; - } - - return rv; -} - -static sw_error_t -_dess_debug_regsiter_dump(a_uint32_t dev_id,fal_debug_reg_dump_t * dbg_reg_dump) -{ - sw_error_t rv = SW_OK; - a_uint32_t reg; - a_uint32_t reg_count, reg_val = 0; - - reg_count = 0; - - for(reg=0;reg<=0x1F;reg++) - { - dess_reg_set(dev_id, 0x820, (a_uint8_t *) & reg, sizeof (a_uint32_t)); - rv = dess_reg_get(dev_id, 0x824, (a_uint8_t *) & reg_val, sizeof (a_uint32_t)); - dbg_reg_dump->reg_value[reg_count] = reg_val; - dbg_reg_dump->reg_addr[reg_count] = reg; - reg_count++; - } - dbg_reg_dump->reg_count = reg_count; - - snprintf((char *)dbg_reg_dump->reg_name,sizeof(dbg_reg_dump->reg_name),"QM debug registers"); - return rv; -} -static sw_error_t -_dess_debug_psgmii_self_test(a_uint32_t dev_id, a_bool_t enable, - a_uint32_t times, a_uint32_t * result) -{ - sw_error_t rv = SW_OK; - ssdk_psgmii_self_test(dev_id, enable, times, result); - clear_self_test_config(dev_id); - - return rv; -} - -static sw_error_t -_dess_phy_dump(a_uint32_t dev_id, a_uint32_t phy_addr, - a_uint32_t idx, fal_phy_dump_t * phy_dump) -{ - sw_error_t rv = SW_OK; - typedef struct { - a_uint32_t phy_base; - a_uint32_t phy_end; - char name[30]; - } phydump; - - phydump dump[2] = - { - {0x0, 0x1f, "0.mii registers"}, - {0x0, 0x3f, "1.debug registers"}, - }; - - a_uint32_t mmd1[] = {0x0,0x5,0x8,0x1800,0x1801,0x1802,0x1803,0x1804, - 0x1805,0x1806,0x1807,0x1808,0x9000,0x9001,0x9002,0x9003, - 0x9004,0x9905,0x9006,0x9007,0x9008,0x9009,0x900a,0x900b}; - char mmd1name[30] = {"2.mmd1 register"}; - - a_uint32_t mmd3[] = {0x0,0x1,0x5,0x8,0x14,0x16,0x8001,0x8002, - 0x8003,0x8004,0x8005,0x8006,0x8007,0x8008,0x8009,0x800a, - 0x8045,0x8046,0x8047,0x8048,0x8049,0x804a,0x804b,0x804c, - 0x804d,0x804e,0x804f}; - char mmd3name[30] = {"3.mmd3 register"}; - - a_uint32_t mmd7[] = {0x0,0x1,0x5,0x16,0x17,0x18,0x19,0x1a,0x1b, - 0x3c,0x3d,0x8000,0x801a}; - char mmd7name[30] = {"4.mmd7 register"}; - - a_uint32_t reg = 0, phy_count = 0,i = 0; - a_uint16_t phy_val = 0; - switch (idx) - { - case 0: - for (reg = dump[idx].phy_base; reg <= dump[idx].phy_end; reg++) - { - rv = dess_phy_get(dev_id, phy_addr, reg, &phy_val); - phy_dump->phy_value[phy_count] = phy_val; - phy_count ++; - } - phy_dump->phy_count = phy_count; - phy_dump->phy_base = dump[idx].phy_base; - phy_dump->phy_end = dump[idx].phy_end; - snprintf((char *)phy_dump->phy_name, - sizeof(phy_dump->phy_name),"%s",dump[idx].name); - break; - case 1: - for (reg = dump[idx].phy_base; reg <= dump[idx].phy_end; reg++) - { - rv = dess_phy_set(dev_id, phy_addr, 0x1d, (a_uint16_t)reg); - rv = dess_phy_get(dev_id, phy_addr, 0x1e, &phy_val); - phy_dump->phy_value[phy_count] = phy_val; - phy_count ++; - } - phy_dump->phy_count = phy_count; - phy_dump->phy_base = dump[idx].phy_base; - phy_dump->phy_end = dump[idx].phy_end; - snprintf((char *)phy_dump->phy_name, - sizeof(phy_dump->phy_name),"%s",dump[idx].name); - break; - case 2: - phy_count = sizeof (mmd1)/sizeof(a_uint32_t); - for (i = 0; i < phy_count; i++ ) - { - rv = dess_phy_set(dev_id, phy_addr, 0xd, 1); - rv = dess_phy_set(dev_id, phy_addr, 0xe, (a_uint16_t)mmd1[i]); - rv = dess_phy_set(dev_id, phy_addr, 0xd, 0x4001); - rv = dess_phy_get(dev_id, phy_addr, 0xe, &phy_val); - phy_dump->phy_value[i] = phy_val; - } - phy_dump->phy_count = phy_count - 1; - phy_dump->phy_base = mmd1[0]; - phy_dump->phy_end = mmd1[phy_count - 1]; - snprintf((char *)phy_dump->phy_name, - sizeof(phy_dump->phy_name),"%s",mmd1name); - break; - case 3: - phy_count = sizeof (mmd3)/sizeof(a_uint32_t); - for (i = 0; i < phy_count; i++ ) - { - rv = dess_phy_set(dev_id, phy_addr, 0xd, 3); - rv = dess_phy_set(dev_id, phy_addr, 0xe, (a_uint16_t)mmd3[i]); - rv = dess_phy_set(dev_id, phy_addr, 0xd, 0x4003); - rv = dess_phy_get(dev_id, phy_addr, 0xe, &phy_val); - phy_dump->phy_value[i] = phy_val; - } - phy_dump->phy_count = phy_count - 1; - phy_dump->phy_base = mmd3[0]; - phy_dump->phy_end = mmd3[phy_count - 1]; - snprintf((char *)phy_dump->phy_name, - sizeof(phy_dump->phy_name),"%s",mmd3name); - break; - case 4: - phy_count = sizeof (mmd7)/sizeof(a_uint32_t); - for (i = 0; i < phy_count; i++ ) - { - rv = dess_phy_set(dev_id, phy_addr, 0xd, 7); - rv = dess_phy_set(dev_id, phy_addr, 0xe, (a_uint16_t)mmd7[i]); - rv = dess_phy_set(dev_id, phy_addr, 0xd, 0x4007); - rv = dess_phy_get(dev_id, phy_addr, 0xe, &phy_val); - phy_dump->phy_value[i] = phy_val; - } - phy_dump->phy_count = phy_count - 1; - phy_dump->phy_base = mmd7[0]; - phy_dump->phy_end = mmd7[phy_count - 1]; - snprintf((char *)phy_dump->phy_name, - sizeof(phy_dump->phy_name),"%s",mmd7name); - break; - default: - return SW_BAD_PARAM; - } - - return rv; -} - -/** - * @brief dump registers. - * @param[in] dev_id device id - * @param[in] register_idx register group id - * @param[out] reg_dump register dump result - * @return SW_OK or error code - */ -sw_error_t -dess_regsiter_dump(a_uint32_t dev_id,a_uint32_t register_idx, fal_reg_dump_t * reg_dump) -{ - sw_error_t rv = SW_OK; - - FAL_API_LOCK; - rv = _dess_regsiter_dump(dev_id,register_idx,reg_dump); - FAL_API_UNLOCK; - return rv; -} - -/** - * @brief dump registers. - * @param[in] dev_id device id - * @param[out] reg_dump debug register dump - * @return SW_OK or error code - */ -sw_error_t -dess_debug_regsiter_dump(a_uint32_t dev_id, fal_debug_reg_dump_t * dbg_reg_dump) -{ - sw_error_t rv = SW_OK; - - FAL_API_LOCK; - rv = _dess_debug_regsiter_dump(dev_id,dbg_reg_dump); - FAL_API_UNLOCK; - return rv; -} - - -/** - * @brief debug psgmii self test. - * @param[in] dev_id, enable, times - * @param[out] status - * @return SW_OK or error code - */ -sw_error_t -dess_debug_psgmii_self_test(a_uint32_t dev_id, a_bool_t enable, - a_uint32_t times, a_uint32_t * result) - -{ - sw_error_t rv = SW_OK; - - FAL_API_LOCK; - rv = _dess_debug_psgmii_self_test(dev_id, enable, times, result); - FAL_API_UNLOCK; - return rv; -} - -sw_error_t -dess_phy_dump(a_uint32_t dev_id, a_uint32_t phy_addr, - a_uint32_t idx, fal_phy_dump_t * phy_dump) -{ - sw_error_t rv = SW_OK; - - FAL_API_LOCK; - rv = _dess_phy_dump(dev_id, phy_addr, idx, phy_dump); - FAL_API_UNLOCK; - return rv; -} -sw_error_t -dess_reg_access_init(a_uint32_t dev_id, hsl_access_mode mode) -{ - hsl_api_t *p_api; - - MDIO_LOCKER_INIT; - reg_mode = mode; - - SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id)); - p_api->phy_get = dess_phy_get; - p_api->phy_set = dess_phy_set; - p_api->reg_get = dess_reg_get; - p_api->reg_set = dess_reg_set; - p_api->reg_field_get = dess_reg_field_get; - p_api->reg_field_set = dess_reg_field_set; - #ifdef IN_INTERFACECONTROL - p_api->psgmii_reg_get = dess_psgmii_reg_get; - p_api->psgmii_reg_set = dess_psgmii_reg_set; - #endif - p_api->register_dump = dess_regsiter_dump; - p_api->debug_register_dump = dess_debug_regsiter_dump; - p_api->debug_psgmii_self_test = dess_debug_psgmii_self_test; - p_api->phy_dump = dess_phy_dump; - - - return SW_OK; -} - -sw_error_t -dess_access_mode_set(a_uint32_t dev_id, hsl_access_mode mode) -{ - reg_mode = mode; - return SW_OK; - -} - diff --git a/feeds/ipq807x/qca-ssdk/src/src/hsl/dess/dess_sec.c b/feeds/ipq807x/qca-ssdk/src/src/hsl/dess/dess_sec.c deleted file mode 100755 index 61c7588d1..000000000 --- a/feeds/ipq807x/qca-ssdk/src/src/hsl/dess/dess_sec.c +++ /dev/null @@ -1,787 +0,0 @@ -/* - * Copyright (c) 2014, 2016, The Linux Foundation. All rights reserved. - * Permission to use, copy, modify, and/or distribute this software for - * any purpose with or without fee is hereby granted, provided that the - * above copyright notice and this permission notice appear in all copies. - * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES - * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR - * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES - * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN - * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT - * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. - */ - - -/** - * @defgroup dess_sec DESS_SEC - * @{ - */ -#include "sw.h" -#include "hsl.h" -#include "hsl_dev.h" -#include "hsl_port_prop.h" -#include "dess_sec.h" -#include "dess_reg.h" - -#define NORM_CTRL0_ADDR 0x0200 -#define NORM_CTRL1_ADDR 0x0204 -#define NORM_CTRL2_ADDR 0x0208 -#define NORM_CTRL3_ADDR 0x0c00 - -static sw_error_t -_dess_sec_norm_item_set(a_uint32_t dev_id, fal_norm_item_t item, void *value) -{ - sw_error_t rv; - fal_fwd_cmd_t cmd; - a_bool_t enable; - a_uint32_t addr, offset, len, reg = 0, val; - - HSL_DEV_ID_CHECK(dev_id); - - cmd = *((fal_fwd_cmd_t *) value); - enable = *((a_bool_t *) value); - val = *((a_uint32_t *) value); - - len = 1; - switch (item) - { - case FAL_NORM_MAC_RESV_VID_CMD: - addr = NORM_CTRL0_ADDR; - offset = 0; - goto cmd_chk; - - case FAL_NORM_MAC_INVALID_SRC_ADDR_CMD: - addr = NORM_CTRL1_ADDR; - offset = 20; - goto cmd_chk; - - case FAL_NORM_IP_INVALID_VER_CMD: - addr = NORM_CTRL0_ADDR; - offset = 1; - goto cmd_chk; - - case FAL_NROM_IP_SAME_ADDR_CMD: - addr = NORM_CTRL0_ADDR; - offset = 2; - goto cmd_chk; - break; - - case FAL_NROM_IP_TTL_CHANGE_STATUS: - addr = NORM_CTRL3_ADDR; - offset = 11; - goto sts_chk; - - case FAL_NROM_IP_TTL_VALUE: - addr = NORM_CTRL3_ADDR; - offset = 12; - len = 8; - goto set_reg; - - case FAL_NROM_IP4_INVALID_HL_CMD: - addr = NORM_CTRL0_ADDR; - offset = 3; - goto cmd_chk; - - case FAL_NROM_IP4_HDR_OPTIONS_CMD: - addr = NORM_CTRL0_ADDR; - offset = 4; - len = 2; - goto s_cmd_chk; - - case FAL_NROM_IP4_INVALID_DF_CMD: - addr = NORM_CTRL0_ADDR; - offset = 7; - goto cmd_chk; - - case FAL_NROM_IP4_FRAG_OFFSET_MIN_LEN_CMD: - addr = NORM_CTRL0_ADDR; - offset = 8; - goto cmd_chk; - - case FAL_NROM_IP4_FRAG_OFFSET_MIN_SIZE: - addr = NORM_CTRL1_ADDR; - offset = 24; - len = 8; - goto set_reg; - - case FAL_NROM_IP4_FRAG_OFFSET_MAX_LEN_CMD: - addr = NORM_CTRL0_ADDR; - offset = 9; - goto cmd_chk; - - case FAL_NROM_IP4_INVALID_FRAG_OFFSET_CMD: - addr = NORM_CTRL0_ADDR; - offset = 10; - goto cmd_chk; - - case FAL_NROM_IP4_INVALID_SIP_CMD: - addr = NORM_CTRL0_ADDR; - offset = 11; - len = 1; - goto cmd_chk; - - case FAL_NROM_IP4_INVALID_DIP_CMD: - addr = NORM_CTRL0_ADDR; - offset = 12; - goto cmd_chk; - - case FAL_NROM_IP4_INVALID_CHKSUM_CMD: - addr = NORM_CTRL0_ADDR; - offset = 13; - goto cmd_chk; - - case FAL_NROM_IP4_INVALID_PL_CMD: - addr = NORM_CTRL1_ADDR; - offset = 19; - goto cmd_chk; - - case FAL_NROM_IP4_DF_CLEAR_STATUS: - addr = NORM_CTRL3_ADDR; - offset = 9; - goto sts_chk; - - case FAL_NROM_IP4_IPID_RANDOM_STATUS: - addr = NORM_CTRL3_ADDR; - offset = 10; - goto sts_chk; - - case FAL_NROM_IP6_INVALID_DIP_CMD: - addr = NORM_CTRL1_ADDR; - offset = 16; - goto cmd_chk; - - case FAL_NROM_IP6_INVALID_SIP_CMD: - addr = NORM_CTRL1_ADDR; - offset = 17; - goto cmd_chk; - - case FAL_NROM_IP6_INVALID_PL_CMD: - addr = NORM_CTRL1_ADDR; - offset = 18; - goto cmd_chk; - - case FAL_NROM_TCP_BLAT_CMD: - addr = NORM_CTRL0_ADDR; - offset = 14; - goto cmd_chk; - - case FAL_NROM_TCP_INVALID_HL_CMD: - addr = NORM_CTRL0_ADDR; - offset = 15; - goto cmd_chk; - - case FAL_NROM_TCP_MIN_HDR_SIZE: - addr = NORM_CTRL1_ADDR; - offset = 12; - len = 4; - goto set_reg; - - case FAL_NROM_TCP_INVALID_SYN_CMD: - addr = NORM_CTRL0_ADDR; - offset = 16; - goto cmd_chk; - break; - - case FAL_NROM_TCP_SU_BLOCK_CMD: - addr = NORM_CTRL0_ADDR; - offset = 17; - goto cmd_chk; - - case FAL_NROM_TCP_SP_BLOCK_CMD: - addr = NORM_CTRL0_ADDR; - offset = 18; - goto cmd_chk; - - case FAL_NROM_TCP_SAP_BLOCK_CMD: - addr = NORM_CTRL0_ADDR; - offset = 19; - goto cmd_chk; - - case FAL_NROM_TCP_XMAS_SCAN_CMD: - addr = NORM_CTRL0_ADDR; - offset = 20; - goto cmd_chk; - - case FAL_NROM_TCP_NULL_SCAN_CMD: - addr = NORM_CTRL0_ADDR; - offset = 21; - goto cmd_chk; - - case FAL_NROM_TCP_SR_BLOCK_CMD: - addr = NORM_CTRL0_ADDR; - offset = 22; - goto cmd_chk; - - case FAL_NROM_TCP_SF_BLOCK_CMD: - addr = NORM_CTRL0_ADDR; - offset = 23; - goto cmd_chk; - - case FAL_NROM_TCP_SAR_BLOCK_CMD: - addr = NORM_CTRL0_ADDR; - offset = 24; - goto cmd_chk; - - case FAL_NROM_TCP_RST_SCAN_CMD: - addr = NORM_CTRL0_ADDR; - offset = 25; - goto cmd_chk; - - case FAL_NROM_TCP_SYN_WITH_DATA_CMD: - addr = NORM_CTRL0_ADDR; - offset = 26; - goto cmd_chk; - - case FAL_NROM_TCP_RST_WITH_DATA_CMD: - addr = NORM_CTRL0_ADDR; - offset = 27; - goto cmd_chk; - - case FAL_NROM_TCP_FA_BLOCK_CMD: - addr = NORM_CTRL0_ADDR; - offset = 28; - goto cmd_chk; - - case FAL_NROM_TCP_PA_BLOCK_CMD: - addr = NORM_CTRL0_ADDR; - offset = 29; - goto cmd_chk; - - case FAL_NROM_TCP_UA_BLOCK_CMD: - addr = NORM_CTRL1_ADDR; - offset = 0; - goto cmd_chk; - - case FAL_NROM_TCP_INVALID_CHKSUM_CMD: - addr = NORM_CTRL1_ADDR; - offset = 1; - goto cmd_chk; - - case FAL_NROM_TCP_INVALID_URGPTR_CMD: - addr = NORM_CTRL1_ADDR; - offset = 2; - goto cmd_chk; - - case FAL_NROM_TCP_INVALID_OPTIONS_CMD: - addr = NORM_CTRL1_ADDR; - offset = 3; - goto cmd_chk; - - case FAL_NROM_UDP_BLAT_CMD: - addr = NORM_CTRL1_ADDR; - offset = 4; - goto cmd_chk; - - case FAL_NROM_UDP_INVALID_LEN_CMD: - addr = NORM_CTRL1_ADDR; - offset = 5; - goto cmd_chk; - - case FAL_NROM_UDP_INVALID_CHKSUM_CMD: - addr = NORM_CTRL1_ADDR; - offset = 6; - goto cmd_chk; - - case FAL_NROM_ICMP4_PING_PL_EXCEED_CMD: - addr = NORM_CTRL1_ADDR; - offset = 7; - goto cmd_chk; - - case FAL_NROM_ICMP6_PING_PL_EXCEED_CMD: - addr = NORM_CTRL1_ADDR; - offset = 8; - goto cmd_chk; - - case FAL_NROM_ICMP4_PING_FRAG_CMD: - addr = NORM_CTRL1_ADDR; - offset = 9; - goto cmd_chk; - - case FAL_NROM_ICMP6_PING_FRAG_CMD: - addr = NORM_CTRL1_ADDR; - offset = 10; - goto cmd_chk; - - case FAL_NROM_ICMP4_PING_MAX_PL_VALUE: - addr = NORM_CTRL2_ADDR; - offset = 0; - len = 14; - goto set_reg; - - case FAL_NROM_ICMP6_PING_MAX_PL_VALUE: - addr = NORM_CTRL2_ADDR; - offset = 16; - len = 14; - goto set_reg; - - default: - return SW_BAD_PARAM; - } - -sts_chk: - if (A_TRUE == enable) - { - val = 1; - } - else if (A_FALSE == enable) - { - val = 0; - } - else - { - return SW_BAD_PARAM; - } - goto set_reg; - -s_cmd_chk: - if (FAL_MAC_FRWRD == cmd) - { - val = 0; - } - else if (FAL_MAC_DROP == cmd) - { - val = 3; - } - else if (FAL_MAC_RDT_TO_CPU == cmd) - { - val = 2; - } - else - { - return SW_BAD_PARAM; - } - goto set_reg; - -cmd_chk: - if (FAL_MAC_FRWRD == cmd) - { - val = 0; - } - else if (FAL_MAC_DROP == cmd) - { - val = 1; - } - else - { - return SW_BAD_PARAM; - } - -set_reg: - HSL_REG_ENTRY_GEN_GET(rv, dev_id, addr, sizeof (a_uint32_t), - (a_uint8_t *) (®), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - - SW_REG_SET_BY_FIELD_U32(reg, val, offset, len); - - HSL_REG_ENTRY_GEN_SET(rv, dev_id, addr, sizeof (a_uint32_t), - (a_uint8_t *) (®), sizeof (a_uint32_t)); - return rv; -} - -static sw_error_t -_dess_sec_norm_item_get(a_uint32_t dev_id, fal_norm_item_t item, void *value) -{ - sw_error_t rv; - a_uint32_t addr, offset, len, reg = 0, val; - a_uint32_t status_chk = 0, val_chk = 0, scmd_chk = 0; - - HSL_DEV_ID_CHECK(dev_id); - - len = 1; - switch (item) - { - case FAL_NORM_MAC_RESV_VID_CMD: - addr = NORM_CTRL0_ADDR; - offset = 0; - break; - - case FAL_NORM_MAC_INVALID_SRC_ADDR_CMD: - addr = NORM_CTRL1_ADDR; - offset = 20; - break; - - case FAL_NORM_IP_INVALID_VER_CMD: - addr = NORM_CTRL0_ADDR; - offset = 1; - break; - - case FAL_NROM_IP_SAME_ADDR_CMD: - addr = NORM_CTRL0_ADDR; - offset = 2; - break; - - case FAL_NROM_IP_TTL_CHANGE_STATUS: - addr = NORM_CTRL3_ADDR; - offset = 11; - status_chk = 1; - break; - - case FAL_NROM_IP_TTL_VALUE: - addr = NORM_CTRL3_ADDR; - offset = 12; - len = 8; - val_chk = 1; - break; - - case FAL_NROM_IP4_INVALID_HL_CMD: - addr = NORM_CTRL0_ADDR; - offset = 3; - break; - - case FAL_NROM_IP4_HDR_OPTIONS_CMD: - addr = NORM_CTRL0_ADDR; - offset = 4; - len = 2; - scmd_chk = 1; - break; - - case FAL_NROM_IP4_INVALID_DF_CMD: - addr = NORM_CTRL0_ADDR; - offset = 7; - break; - - case FAL_NROM_IP4_FRAG_OFFSET_MIN_LEN_CMD: - addr = NORM_CTRL0_ADDR; - offset = 8; - break; - - case FAL_NROM_IP4_FRAG_OFFSET_MIN_SIZE: - addr = NORM_CTRL1_ADDR; - offset = 24; - len = 8; - val_chk = 1; - break; - - case FAL_NROM_IP4_FRAG_OFFSET_MAX_LEN_CMD: - addr = NORM_CTRL0_ADDR; - offset = 9; - break; - - case FAL_NROM_IP4_INVALID_FRAG_OFFSET_CMD: - addr = NORM_CTRL0_ADDR; - offset = 10; - break; - - case FAL_NROM_IP4_INVALID_SIP_CMD: - addr = NORM_CTRL0_ADDR; - offset = 11; - len = 1; - break; - - case FAL_NROM_IP4_INVALID_DIP_CMD: - addr = NORM_CTRL0_ADDR; - offset = 12; - break; - - case FAL_NROM_IP4_INVALID_CHKSUM_CMD: - addr = NORM_CTRL0_ADDR; - offset = 13; - break; - - case FAL_NROM_IP4_INVALID_PL_CMD: - addr = NORM_CTRL1_ADDR; - offset = 19; - break; - - case FAL_NROM_IP4_DF_CLEAR_STATUS: - addr = NORM_CTRL3_ADDR; - offset = 9; - status_chk = 1; - break; - - case FAL_NROM_IP4_IPID_RANDOM_STATUS: - addr = NORM_CTRL3_ADDR; - offset = 10; - status_chk = 1; - break; - - case FAL_NROM_IP6_INVALID_DIP_CMD: - addr = NORM_CTRL1_ADDR; - offset = 16; - break; - - case FAL_NROM_IP6_INVALID_SIP_CMD: - addr = NORM_CTRL1_ADDR; - offset = 17; - break; - - case FAL_NROM_IP6_INVALID_PL_CMD: - addr = NORM_CTRL1_ADDR; - offset = 18; - break; - - case FAL_NROM_TCP_BLAT_CMD: - addr = NORM_CTRL0_ADDR; - offset = 14; - break; - - case FAL_NROM_TCP_INVALID_HL_CMD: - addr = NORM_CTRL0_ADDR; - offset = 15; - break; - - case FAL_NROM_TCP_MIN_HDR_SIZE: - addr = NORM_CTRL1_ADDR; - offset = 12; - len = 4; - val_chk = 1; - break; - - case FAL_NROM_TCP_INVALID_SYN_CMD: - addr = NORM_CTRL0_ADDR; - offset = 16; - break; - - case FAL_NROM_TCP_SU_BLOCK_CMD: - addr = NORM_CTRL0_ADDR; - offset = 17; - break; - - case FAL_NROM_TCP_SP_BLOCK_CMD: - addr = NORM_CTRL0_ADDR; - offset = 18; - break; - - case FAL_NROM_TCP_SAP_BLOCK_CMD: - addr = NORM_CTRL0_ADDR; - offset = 19; - break; - - case FAL_NROM_TCP_XMAS_SCAN_CMD: - addr = NORM_CTRL0_ADDR; - offset = 20; - break; - - case FAL_NROM_TCP_NULL_SCAN_CMD: - addr = NORM_CTRL0_ADDR; - offset = 21; - break; - - case FAL_NROM_TCP_SR_BLOCK_CMD: - addr = NORM_CTRL0_ADDR; - offset = 22; - break; - - case FAL_NROM_TCP_SF_BLOCK_CMD: - addr = NORM_CTRL0_ADDR; - offset = 23; - break; - - case FAL_NROM_TCP_SAR_BLOCK_CMD: - addr = NORM_CTRL0_ADDR; - offset = 24; - break; - - case FAL_NROM_TCP_RST_SCAN_CMD: - addr = NORM_CTRL0_ADDR; - offset = 25; - break; - - case FAL_NROM_TCP_SYN_WITH_DATA_CMD: - addr = NORM_CTRL0_ADDR; - offset = 26; - break; - - case FAL_NROM_TCP_RST_WITH_DATA_CMD: - addr = NORM_CTRL0_ADDR; - offset = 27; - break; - - case FAL_NROM_TCP_FA_BLOCK_CMD: - addr = NORM_CTRL0_ADDR; - offset = 28; - break; - - case FAL_NROM_TCP_PA_BLOCK_CMD: - addr = NORM_CTRL0_ADDR; - offset = 29; - break; - - case FAL_NROM_TCP_UA_BLOCK_CMD: - addr = NORM_CTRL1_ADDR; - offset = 0; - break; - - case FAL_NROM_TCP_INVALID_CHKSUM_CMD: - addr = NORM_CTRL1_ADDR; - offset = 1; - break; - - case FAL_NROM_TCP_INVALID_URGPTR_CMD: - addr = NORM_CTRL1_ADDR; - offset = 2; - break; - - case FAL_NROM_TCP_INVALID_OPTIONS_CMD: - addr = NORM_CTRL1_ADDR; - offset = 3; - break; - - case FAL_NROM_UDP_BLAT_CMD: - addr = NORM_CTRL1_ADDR; - offset = 4; - break; - - case FAL_NROM_UDP_INVALID_LEN_CMD: - addr = NORM_CTRL1_ADDR; - offset = 5; - break; - - case FAL_NROM_UDP_INVALID_CHKSUM_CMD: - addr = NORM_CTRL1_ADDR; - offset = 6; - break; - - case FAL_NROM_ICMP4_PING_PL_EXCEED_CMD: - addr = NORM_CTRL1_ADDR; - offset = 7; - break; - - case FAL_NROM_ICMP6_PING_PL_EXCEED_CMD: - addr = NORM_CTRL1_ADDR; - offset = 8; - break; - - case FAL_NROM_ICMP4_PING_FRAG_CMD: - addr = NORM_CTRL1_ADDR; - offset = 9; - break; - - case FAL_NROM_ICMP6_PING_FRAG_CMD: - addr = NORM_CTRL1_ADDR; - offset = 10; - break; - - case FAL_NROM_ICMP4_PING_MAX_PL_VALUE: - addr = NORM_CTRL2_ADDR; - offset = 0; - len = 14; - val_chk = 1; - break; - - case FAL_NROM_ICMP6_PING_MAX_PL_VALUE: - addr = NORM_CTRL2_ADDR; - offset = 16; - len = 14; - val_chk = 1; - break; - - default: - return SW_BAD_PARAM; - } - - HSL_REG_ENTRY_GEN_GET(rv, dev_id, addr, sizeof (a_uint32_t), - (a_uint8_t *) (®), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - - SW_FIELD_GET_BY_REG_U32(reg, val, offset, len); - - if (val_chk) - { - *((a_uint32_t *) value) = val; - } - else if (status_chk) - { - if (val) - { - *((a_bool_t *) value) = A_TRUE; - } - else - { - *((a_bool_t *) value) = A_FALSE; - } - } - else if (scmd_chk) - { - if (2 == val) - { - *((fal_fwd_cmd_t *) value) = FAL_MAC_RDT_TO_CPU; - } - else if (3 == val) - { - *((fal_fwd_cmd_t *) value) = FAL_MAC_DROP; - } - else - { - *((fal_fwd_cmd_t *) value) = FAL_MAC_FRWRD; - } - } - else - { - if (val) - { - *((fal_fwd_cmd_t *) value) = FAL_MAC_DROP; - } - else - { - *((fal_fwd_cmd_t *) value) = FAL_MAC_FRWRD; - } - } - - return SW_OK; -} - -/** - * @brief Set normalization particular item types value. - * @details Comments: - * This operation will set normalization item values on a particular device. - * The prototye of value based on the item type. - * @param[in] dev_id device id - * @param[in] item normalizaton item type - * @param[in] value normalizaton item value - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -dess_sec_norm_item_set(a_uint32_t dev_id, fal_norm_item_t item, void *value) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _dess_sec_norm_item_set(dev_id, item, value); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Get normalization particular item types value. - * @details Comments: - * This operation will set normalization item values on a particular device. - * The prototye of value based on the item type. - * @param[in] dev_id device id - * @param[in] item normalizaton item type - * @param[out] value normalizaton item value - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -dess_sec_norm_item_get(a_uint32_t dev_id, fal_norm_item_t item, void *value) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _dess_sec_norm_item_get(dev_id, item, value); - HSL_API_UNLOCK; - return rv; -} - -sw_error_t -dess_sec_init(a_uint32_t dev_id) -{ - HSL_DEV_ID_CHECK(dev_id); - -#ifndef HSL_STANDALONG - { - hsl_api_t *p_api; - - SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id)); - p_api->sec_norm_item_set = dess_sec_norm_item_set; - p_api->sec_norm_item_get = dess_sec_norm_item_get; - } -#endif - - return SW_OK; -} - -/** - * @} - */ diff --git a/feeds/ipq807x/qca-ssdk/src/src/hsl/dess/dess_stp.c b/feeds/ipq807x/qca-ssdk/src/src/hsl/dess/dess_stp.c deleted file mode 100755 index 6537241de..000000000 --- a/feeds/ipq807x/qca-ssdk/src/src/hsl/dess/dess_stp.c +++ /dev/null @@ -1,193 +0,0 @@ -/* - * Copyright (c) 2014, 2016, The Linux Foundation. All rights reserved. - * Permission to use, copy, modify, and/or distribute this software for - * any purpose with or without fee is hereby granted, provided that the - * above copyright notice and this permission notice appear in all copies. - * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES - * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR - * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES - * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN - * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT - * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. - */ - - -/** - * @defgroup dess_stp DESS_STP - * @{ - */ -#include "sw.h" -#include "hsl.h" -#include "hsl_dev.h" -#include "hsl_port_prop.h" -#include "dess_stp.h" -#include "dess_reg.h" - -#define DESS_PORT_DISABLED 0 -#define DESS_STP_BLOCKING 1 -#define DESS_STP_LISTENING 2 -#define DESS_STP_LEARNING 3 -#define DESS_STP_FARWARDING 4 - -static sw_error_t -_dess_stp_port_state_set(a_uint32_t dev_id, a_uint32_t st_id, - fal_port_t port_id, fal_stp_state_t state) -{ - sw_error_t rv; - a_uint32_t val; - - HSL_DEV_ID_CHECK(dev_id); - - if (FAL_SINGLE_STP_ID != st_id) - { - return SW_BAD_PARAM; - } - - if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_EXCL_CPU)) - { - return SW_BAD_PARAM; - } - - switch (state) - { - case FAL_STP_BLOKING: - val = DESS_STP_BLOCKING; - break; - case FAL_STP_LISTENING: - val = DESS_STP_LISTENING; - break; - case FAL_STP_LEARNING: - val = DESS_STP_LEARNING; - break; - case FAL_STP_FARWARDING: - val = DESS_STP_FARWARDING; - break; - case FAL_STP_DISABLED: - val = DESS_PORT_DISABLED; - break; - default: - return SW_BAD_PARAM; - } - - HSL_REG_FIELD_SET(rv, dev_id, PORT_LOOKUP_CTL, port_id, PORT_STATE, - (a_uint8_t *) (&val), sizeof (a_uint32_t)); - return rv; -} - -static sw_error_t -_dess_stp_port_state_get(a_uint32_t dev_id, a_uint32_t st_id, - fal_port_t port_id, fal_stp_state_t * state) -{ - sw_error_t rv; - a_uint32_t val = 0; - - HSL_DEV_ID_CHECK(dev_id); - - if (FAL_SINGLE_STP_ID != st_id) - { - return SW_BAD_PARAM; - } - - if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_EXCL_CPU)) - { - return SW_BAD_PARAM; - } - - HSL_REG_FIELD_GET(rv, dev_id, PORT_LOOKUP_CTL, port_id, PORT_STATE, - (a_uint8_t *) (&val), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - - switch (val) - { - case DESS_STP_BLOCKING: - *state = FAL_STP_BLOKING; - break; - case DESS_STP_LISTENING: - *state = FAL_STP_LISTENING; - break; - case DESS_STP_LEARNING: - *state = FAL_STP_LEARNING; - break; - case DESS_STP_FARWARDING: - *state = FAL_STP_FARWARDING; - break; - case DESS_PORT_DISABLED: - *state = FAL_STP_DISABLED; - break; - default: - return SW_FAIL; - } - - return SW_OK; -} - -/** - * @brief Set port stp state on a particular spanning tree and port. - * @details Comments: - Garuda only support single spanning tree so st_id should be - FAL_SINGLE_STP_ID that is zero. - * @param[in] dev_id device id - * @param[in] st_id spanning tree id - * @param[in] port_id port id - * @param[in] state port state for spanning tree - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -dess_stp_port_state_set(a_uint32_t dev_id, a_uint32_t st_id, - fal_port_t port_id, fal_stp_state_t state) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _dess_stp_port_state_set(dev_id, st_id, port_id, state); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Get port stp state on a particular spanning tree and port. - * @details Comments: - Garuda only support single spanning tree so st_id should be - FAL_SINGLE_STP_ID that is zero. - * @param[in] dev_id device id - * @param[in] st_id spanning tree id - * @param[in] port_id port id - * @param[out] state port state for spanning tree - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -dess_stp_port_state_get(a_uint32_t dev_id, a_uint32_t st_id, - fal_port_t port_id, fal_stp_state_t * state) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _dess_stp_port_state_get(dev_id, st_id, port_id, state); - HSL_API_UNLOCK; - return rv; -} - -sw_error_t -dess_stp_init(a_uint32_t dev_id) -{ - HSL_DEV_ID_CHECK(dev_id); - -#ifndef HSL_STANDALONG - { - hsl_api_t *p_api; - - SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id)); - - p_api->stp_port_state_set = dess_stp_port_state_set; - p_api->stp_port_state_get = dess_stp_port_state_get; - } -#endif - - return SW_OK; -} - -/** - * @} - */ - diff --git a/feeds/ipq807x/qca-ssdk/src/src/hsl/dess/dess_trunk.c b/feeds/ipq807x/qca-ssdk/src/src/hsl/dess/dess_trunk.c deleted file mode 100755 index e57eb0d25..000000000 --- a/feeds/ipq807x/qca-ssdk/src/src/hsl/dess/dess_trunk.c +++ /dev/null @@ -1,327 +0,0 @@ -/* - * Copyright (c) 2014, 2016, The Linux Foundation. All rights reserved. - * Permission to use, copy, modify, and/or distribute this software for - * any purpose with or without fee is hereby granted, provided that the - * above copyright notice and this permission notice appear in all copies. - * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES - * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR - * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES - * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN - * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT - * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. - */ - - - -/** - * @defgroup dess_trunk DESS_TRUNK - * @{ - */ -#include "sw.h" -#include "hsl.h" -#include "hsl_dev.h" -#include "hsl_port_prop.h" -#include "dess_trunk.h" -#include "dess_reg.h" - -#define DESS_MAX_TRUNK_ID 3 - -enum dess_trunk_reg_id -{ - DESS_TRUNK_HASH_EN = 0, /*0x270*/ - DESS_TRUNK_CTRL_0, /*0x700*/ - DESS_TRUNK_CTRL_1, /*0x704*/ - DESS_TRUNK_CTRL_2, /*0x708*/ - DESS_TRUNK_REG_MAX -}; - -static a_uint32_t dess_trunk_regs[DESS_TRUNK_REG_MAX] = -{ - 0xf, 0x0, 0x0, 0x0 -}; - -static sw_error_t -_dess_trunk_group_set(a_uint32_t dev_id, a_uint32_t trunk_id, - a_bool_t enable, fal_pbmp_t member) -{ - sw_error_t rv; - a_uint32_t i, reg = 0, cnt = 0, data0 = 0, data1 = 0; - - if (DESS_MAX_TRUNK_ID < trunk_id) - { - return SW_BAD_PARAM; - } - - if (A_FALSE == hsl_mports_prop_check(dev_id, member, HSL_PP_INCL_CPU)) - { - return SW_BAD_PARAM; - } - - if (A_TRUE == enable) - { - data0 = (0x1 << 7) | member; - - for (i = 0; i < 7; i++) - { - if (member & (0x1 << i)) - { - if (4 <= cnt) - { - return SW_BAD_PARAM; - } - - data1 |= (i << (cnt << 2)); - data1 |= (1 << (3 + (cnt << 2))); - cnt++; - } - } - } - else if (A_FALSE == enable) - { - - } - else - { - return SW_BAD_PARAM; - } - - /* set trunk port member bitmap info */ - HSL_REG_ENTRY_GET(rv, dev_id, GOL_TRUNK_CTL0, 0, - (a_uint8_t *) (®), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - - reg &= (~(0xff << (trunk_id << 3))); - reg |= (data0 << (trunk_id << 3)); - - HSL_REG_ENTRY_SET(rv, dev_id, GOL_TRUNK_CTL0, 0, - (a_uint8_t *) (®), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - - dess_trunk_regs[DESS_TRUNK_CTRL_0] = reg; - - /* set trunk port member id info */ - HSL_REG_ENTRY_GET(rv, dev_id, GOL_TRUNK_CTL1, (trunk_id >> 1), - (a_uint8_t *) (®), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - - reg &= (~(0xffff << ((trunk_id % 2) << 4))); - reg |= (data1 << ((trunk_id % 2) << 4)); - - HSL_REG_ENTRY_SET(rv, dev_id, GOL_TRUNK_CTL1, (trunk_id >> 1), - (a_uint8_t *) (®), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - - dess_trunk_regs[DESS_TRUNK_CTRL_1 + (trunk_id >> 1)] = reg; - - return SW_OK; -} - -static sw_error_t -_dess_trunk_group_get(a_uint32_t dev_id, a_uint32_t trunk_id, - a_bool_t * enable, fal_pbmp_t * member) -{ - sw_error_t rv; - a_uint32_t data, reg = 0; - - if (DESS_MAX_TRUNK_ID < trunk_id) - { - return SW_BAD_PARAM; - } - - HSL_REG_ENTRY_GET(rv, dev_id, GOL_TRUNK_CTL0, 0, - (a_uint8_t *) (®), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - - data = (reg >> (trunk_id << 3)) & 0xff; - if (0x80 & data) - { - *enable = A_TRUE; - *member = data & 0x7f; - } - else - { - *enable = A_FALSE; - *member = 0; - } - - return SW_OK; -} - -static sw_error_t -_dess_trunk_hash_mode_set(a_uint32_t dev_id, a_uint32_t hash_mode) -{ - sw_error_t rv; - a_uint32_t data = 0; - - if (FAL_TRUNK_HASH_KEY_DA & hash_mode) - { - SW_SET_REG_BY_FIELD(TRUNK_HASH_MODE, DA_EN, 1, data); - } - - if (FAL_TRUNK_HASH_KEY_SA & hash_mode) - { - SW_SET_REG_BY_FIELD(TRUNK_HASH_MODE, SA_EN, 1, data); - } - - if (FAL_TRUNK_HASH_KEY_DIP & hash_mode) - { - SW_SET_REG_BY_FIELD(TRUNK_HASH_MODE, DIP_EN, 1, data); - } - - if (FAL_TRUNK_HASH_KEY_SIP & hash_mode) - { - SW_SET_REG_BY_FIELD(TRUNK_HASH_MODE, SIP_EN, 1, data); - } - - HSL_REG_ENTRY_SET(rv, dev_id, TRUNK_HASH_MODE, 0, - (a_uint8_t *) (&data), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - - dess_trunk_regs[DESS_TRUNK_HASH_EN] = data; - - return rv; -} - -static sw_error_t -_dess_trunk_hash_mode_get(a_uint32_t dev_id, a_uint32_t * hash_mode) -{ - sw_error_t rv; - a_uint32_t reg = 0, data = 0; - - HSL_REG_ENTRY_GET(rv, dev_id, TRUNK_HASH_MODE, 0, - (a_uint8_t *) (®), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - - *hash_mode = 0; - - SW_GET_FIELD_BY_REG(TRUNK_HASH_MODE, DA_EN, data, reg); - if (data) - { - *hash_mode |= FAL_TRUNK_HASH_KEY_DA; - } - - SW_GET_FIELD_BY_REG(TRUNK_HASH_MODE, SA_EN, data, reg); - if (data) - { - *hash_mode |= FAL_TRUNK_HASH_KEY_SA; - } - - SW_GET_FIELD_BY_REG(TRUNK_HASH_MODE, DIP_EN, data, reg); - if (data) - { - *hash_mode |= FAL_TRUNK_HASH_KEY_DIP; - } - - SW_GET_FIELD_BY_REG(TRUNK_HASH_MODE, SIP_EN, data, reg); - if (data) - { - *hash_mode |= FAL_TRUNK_HASH_KEY_SIP; - } - - return SW_OK; -} - - -/** - * @brief Set particular trunk group information on particular device. - * @param[in] dev_id device id - * @param[in] trunk_id trunk group id - * @param[in] enable trunk group status, enable or disable - * @param[in] member port member information - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -dess_trunk_group_set(a_uint32_t dev_id, a_uint32_t trunk_id, - a_bool_t enable, fal_pbmp_t member) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _dess_trunk_group_set(dev_id, trunk_id, enable, member); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Get particular trunk group information on particular device. - * @param[in] dev_id device id - * @param[in] trunk_id trunk group id - * @param[out] enable trunk group status, enable or disable - * @param[out] member port member information - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -dess_trunk_group_get(a_uint32_t dev_id, a_uint32_t trunk_id, - a_bool_t * enable, fal_pbmp_t * member) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _dess_trunk_group_get(dev_id, trunk_id, enable, member); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Set trunk hash mode on particular device. - * @details Comments: - hash mode is listed below - FAL_TRUNK_HASH_KEY_DA, FAL_TRUNK_HASH_KEY_SA, FAL_TRUNK_HASH_KEY_DIP and FAL_TRUNK_HASH_KEY_SIP - * @param[in] dev_id device id - * @param[in] hash_mode trunk hash mode - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -dess_trunk_hash_mode_set(a_uint32_t dev_id, a_uint32_t hash_mode) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _dess_trunk_hash_mode_set(dev_id, hash_mode); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Get trunk hash mode on particular device. - * @param[in] dev_id device id - * @param[out] hash_mode trunk hash mode - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -dess_trunk_hash_mode_get(a_uint32_t dev_id, a_uint32_t * hash_mode) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _dess_trunk_hash_mode_get(dev_id, hash_mode); - HSL_API_UNLOCK; - return rv; -} - - -sw_error_t -dess_trunk_init(a_uint32_t dev_id) -{ - HSL_DEV_ID_CHECK(dev_id); - -#ifndef HSL_STANDALONG - { - hsl_api_t *p_api; - - SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id)); - p_api->trunk_group_set = dess_trunk_group_set; - p_api->trunk_group_get = dess_trunk_group_get; - p_api->trunk_hash_mode_set = dess_trunk_hash_mode_set; - p_api->trunk_hash_mode_get = dess_trunk_hash_mode_get; - } -#endif - - return SW_OK; -} - -/** - * @} - */ - diff --git a/feeds/ipq807x/qca-ssdk/src/src/hsl/dess/dess_vlan.c b/feeds/ipq807x/qca-ssdk/src/src/hsl/dess/dess_vlan.c deleted file mode 100755 index 2923cb34e..000000000 --- a/feeds/ipq807x/qca-ssdk/src/src/hsl/dess/dess_vlan.c +++ /dev/null @@ -1,906 +0,0 @@ -/* - * Copyright (c) 2014, The Linux Foundation. All rights reserved. - * Permission to use, copy, modify, and/or distribute this software for - * any purpose with or without fee is hereby granted, provided that the - * above copyright notice and this permission notice appear in all copies. - * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES - * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR - * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES - * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN - * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT - * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. - */ - - -/** - * @defgroup dess_vlan DESS_VLAN - * @{ - */ -#include "sw.h" -#include "hsl.h" -#include "hsl_dev.h" -#include "hsl_port_prop.h" -#include "dess_vlan.h" -#include "dess_reg.h" - -#define MAX_VLAN_ID 4095 - -#define VLAN_FLUSH 1 -#define VLAN_LOAD_ENTRY 2 -#define VLAN_PURGE_ENTRY 3 -#define VLAN_REMOVE_PORT 4 -#define VLAN_NEXT_ENTRY 5 -#define VLAN_FIND_ENTRY 6 - -static void -_dess_vlan_hw_to_sw(a_uint32_t reg[], fal_vlan_t * vlan_entry) -{ - a_uint32_t i, data, tmp; - - aos_mem_zero(vlan_entry, sizeof (fal_vlan_t)); - - SW_GET_FIELD_BY_REG(VLAN_TABLE_FUNC1, VLAN_ID, data, reg[1]); - vlan_entry->vid = data & 0xfff; - - SW_GET_FIELD_BY_REG(VLAN_TABLE_FUNC0, IVL_EN, data, reg[0]); - if (1 == data) - { - vlan_entry->fid = vlan_entry->vid; - } - else - { - vlan_entry->fid = FAL_SVL_FID; - } - - SW_GET_FIELD_BY_REG(VLAN_TABLE_FUNC0, LEARN_DIS, data, reg[0]); - if (1 == data) - { - vlan_entry->learn_dis = A_TRUE; - } - else - { - vlan_entry->learn_dis = A_FALSE; - } - - SW_GET_FIELD_BY_REG(VLAN_TABLE_FUNC0, VT_PRI_EN, data, reg[0]); - if (1 == data) - { - vlan_entry->vid_pri_en = A_TRUE; - - SW_GET_FIELD_BY_REG(VLAN_TABLE_FUNC0, VT_PRI, data, reg[0]); - vlan_entry->vid_pri = data & 0xff; - } - else - { - vlan_entry->vid_pri_en = A_FALSE; - } - - SW_GET_FIELD_BY_REG(VLAN_TABLE_FUNC0, VID_MEM, data, reg[0]); - for (i = 0; i < 7; i++) - { - tmp = (data >> (i << 1)) & 0x3UL; - if (0 == tmp) - { - vlan_entry->mem_ports |= (0x1UL << i); - vlan_entry->unmodify_ports |= (0x1UL << i); - } - else if (1 == tmp) - { - vlan_entry->mem_ports |= (0x1UL << i); - vlan_entry->untagged_ports |= (0x1UL << i); - } - else if (2 == tmp) - { - vlan_entry->mem_ports |= (0x1UL << i); - vlan_entry->tagged_ports |= (0x1UL << i); - } - } - - return; -} - -static sw_error_t -_dess_vlan_sw_to_hw(a_uint32_t dev_id, const fal_vlan_t * vlan_entry, - a_uint32_t reg[]) -{ - a_uint32_t i, tag, untag, unmodify, member = 0; - - if (vlan_entry->vid > MAX_VLAN_ID) - { - return SW_OUT_OF_RANGE; - } - - if (A_FALSE == - hsl_mports_prop_check(dev_id, vlan_entry->mem_ports, HSL_PP_INCL_CPU)) - { - return SW_BAD_PARAM; - } - - SW_SET_REG_BY_FIELD(VLAN_TABLE_FUNC0, VT_VALID, 1, reg[0]); - - if (FAL_SVL_FID == vlan_entry->fid) - { - SW_SET_REG_BY_FIELD(VLAN_TABLE_FUNC0, IVL_EN, 0, reg[0]); - } - else if (vlan_entry->vid == vlan_entry->fid) - { - SW_SET_REG_BY_FIELD(VLAN_TABLE_FUNC0, IVL_EN, 1, reg[0]); - } - else - { - return SW_BAD_VALUE; - } - - if (A_TRUE == vlan_entry->learn_dis) - { - SW_SET_REG_BY_FIELD(VLAN_TABLE_FUNC0, LEARN_DIS, 1, reg[0]); - } - else - { - SW_SET_REG_BY_FIELD(VLAN_TABLE_FUNC0, LEARN_DIS, 0, reg[0]); - } - - for (i = 0; i < 7; i++) - { - if ((vlan_entry->mem_ports >> i) & 0x1UL) - { - tag = (vlan_entry->tagged_ports >> i) & 0x1UL; - untag = (vlan_entry->untagged_ports >> i) & 0x1UL; - unmodify = (vlan_entry->unmodify_ports >> i) & 0x1UL; - - if ((0 == (tag + untag + unmodify)) - || (1 < (tag + untag + unmodify))) - { - return SW_BAD_VALUE; - } - - if (tag) - { - member |= (2 << (i << 1)); - } - else if (untag) - { - member |= (1 << (i << 1)); - } - } - else - { - member |= (3 << (i << 1)); - } - } - SW_SET_REG_BY_FIELD(VLAN_TABLE_FUNC0, VID_MEM, member, reg[0]); - - if (A_TRUE == vlan_entry->vid_pri_en) - { - SW_SET_REG_BY_FIELD(VLAN_TABLE_FUNC0, VT_PRI_EN, 1, reg[0]); - SW_SET_REG_BY_FIELD(VLAN_TABLE_FUNC0, VT_PRI, vlan_entry->vid_pri, - reg[0]); - } - else - { - SW_SET_REG_BY_FIELD(VLAN_TABLE_FUNC0, VT_PRI_EN, 0, reg[0]); - } - - SW_SET_REG_BY_FIELD(VLAN_TABLE_FUNC1, VLAN_ID, vlan_entry->vid, reg[1]); - - return SW_OK; -} - -static sw_error_t -_dess_vlan_down_to_hw(a_uint32_t dev_id, a_uint32_t reg[]) -{ - sw_error_t rv; - - HSL_REG_ENTRY_SET(rv, dev_id, VLAN_TABLE_FUNC0, 0, - (a_uint8_t *) (®[0]), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - - HSL_REG_ENTRY_SET(rv, dev_id, VLAN_TABLE_FUNC1, 0, - (a_uint8_t *) (®[1]), sizeof (a_uint32_t)); - return rv; -} - -static sw_error_t -_dess_vlan_up_to_sw(a_uint32_t dev_id, a_uint32_t reg[]) -{ - sw_error_t rv; - - HSL_REG_ENTRY_GET(rv, dev_id, VLAN_TABLE_FUNC0, 0, - (a_uint8_t *) (®[0]), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - - HSL_REG_ENTRY_GET(rv, dev_id, VLAN_TABLE_FUNC1, 0, - (a_uint8_t *) (®[1]), sizeof (a_uint32_t)); - return rv; -} - -static sw_error_t -_dess_vlan_commit(a_uint32_t dev_id, a_uint32_t op) -{ - a_uint32_t vt_busy = 1, i = 0x1000, vt_full, val; - sw_error_t rv; - - while (vt_busy && --i) - { - HSL_REG_FIELD_GET(rv, dev_id, VLAN_TABLE_FUNC1, 0, VT_BUSY, - (a_uint8_t *) (&vt_busy), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - aos_udelay(5); - } - - if (i == 0) - return SW_BUSY; - - HSL_REG_ENTRY_GET(rv, dev_id, VLAN_TABLE_FUNC1, 0, - (a_uint8_t *) (&val), sizeof (a_uint32_t)); - SW_SET_REG_BY_FIELD(VLAN_TABLE_FUNC1, VT_FUNC, op, val); - SW_SET_REG_BY_FIELD(VLAN_TABLE_FUNC1, VT_BUSY, 1, val); - - HSL_REG_ENTRY_SET(rv, dev_id, VLAN_TABLE_FUNC1, 0, - (a_uint8_t *) (&val), sizeof (a_uint32_t)); - - SW_RTN_ON_ERROR(rv); - - vt_busy = 1; - i = 0x1000; - while (vt_busy && --i) - { - HSL_REG_FIELD_GET(rv, dev_id, VLAN_TABLE_FUNC1, 0, VT_BUSY, - (a_uint8_t *) (&vt_busy), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - aos_udelay(5); - } - - if (i == 0) - return SW_FAIL; - - HSL_REG_FIELD_GET(rv, dev_id, VLAN_TABLE_FUNC1, 0, VT_FULL_VIO, - (a_uint8_t *) (&vt_full), sizeof (a_uint32_t)); - - SW_RTN_ON_ERROR(rv); - - if (vt_full) - { - val = 0x10; - HSL_REG_ENTRY_SET(rv, dev_id, VLAN_TABLE_FUNC1, 0, - (a_uint8_t *) (&val), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - if (VLAN_LOAD_ENTRY == op) - { - return SW_FULL; - } - else if (VLAN_PURGE_ENTRY == op) - { - return SW_NOT_FOUND; - } - } - - HSL_REG_FIELD_GET(rv, dev_id, VLAN_TABLE_FUNC0, 0, VT_VALID, - (a_uint8_t *) (&val), sizeof (a_uint32_t)); - - SW_RTN_ON_ERROR(rv); - - if (!val) - { - if (VLAN_FIND_ENTRY == op) - return SW_NOT_FOUND; - - if (VLAN_NEXT_ENTRY == op) - return SW_NO_MORE; - } - - return SW_OK; -} - -static sw_error_t -_dess_vlan_hwentry_get(a_uint32_t dev_id, a_uint32_t vlan_id, a_uint32_t reg[]) -{ - sw_error_t rv; - - if (vlan_id > MAX_VLAN_ID) - { - return SW_OUT_OF_RANGE; - } - - SW_SET_REG_BY_FIELD(VLAN_TABLE_FUNC1, VLAN_ID, vlan_id, reg[1]); - HSL_REG_ENTRY_SET(rv, dev_id, VLAN_TABLE_FUNC1, 0, - (a_uint8_t *) (®[1]), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - - rv = _dess_vlan_commit(dev_id, VLAN_FIND_ENTRY); - SW_RTN_ON_ERROR(rv); - - rv = _dess_vlan_up_to_sw(dev_id, reg); - return rv; -} - -static sw_error_t -_dess_vlan_entry_append(a_uint32_t dev_id, const fal_vlan_t * vlan_entry) -{ - sw_error_t rv; - a_uint32_t reg[2] = { 0 }; - - HSL_DEV_ID_CHECK(dev_id); - - rv = _dess_vlan_sw_to_hw(dev_id, vlan_entry, reg); - SW_RTN_ON_ERROR(rv); - - rv = _dess_vlan_down_to_hw(dev_id, reg); - SW_RTN_ON_ERROR(rv); - - rv = _dess_vlan_commit(dev_id, VLAN_LOAD_ENTRY); - return rv; -} - -static sw_error_t -_dess_vlan_create(a_uint32_t dev_id, a_uint32_t vlan_id) -{ - sw_error_t rv; - a_uint32_t reg[2] = { 0 }; - - HSL_DEV_ID_CHECK(dev_id); - - if (vlan_id > MAX_VLAN_ID) - { - return SW_OUT_OF_RANGE; - } - - SW_SET_REG_BY_FIELD(VLAN_TABLE_FUNC0, VT_VALID, 1, reg[0]); - SW_SET_REG_BY_FIELD(VLAN_TABLE_FUNC0, IVL_EN, 1, reg[0]); - SW_SET_REG_BY_FIELD(VLAN_TABLE_FUNC0, LEARN_DIS, 0, reg[0]); - SW_SET_REG_BY_FIELD(VLAN_TABLE_FUNC0, VID_MEM, 0x3fff, reg[0]); - SW_SET_REG_BY_FIELD(VLAN_TABLE_FUNC1, VLAN_ID, vlan_id, reg[1]); - - rv = _dess_vlan_down_to_hw(dev_id, reg); - SW_RTN_ON_ERROR(rv); - - rv = _dess_vlan_commit(dev_id, VLAN_LOAD_ENTRY); - return rv; -} - -static sw_error_t -_dess_vlan_next(a_uint32_t dev_id, a_uint32_t vlan_id, fal_vlan_t * p_vlan) -{ - sw_error_t rv; - a_uint32_t reg[2] = { 0 }; - - HSL_DEV_ID_CHECK(dev_id); - - if (FAL_NEXT_ENTRY_FIRST_ID == vlan_id) - { - rv = _dess_vlan_hwentry_get(dev_id, 0, reg); - - if (SW_OK == rv) - { - _dess_vlan_hw_to_sw(reg, p_vlan); - return SW_OK; - } - else - { - vlan_id = 0; - } - } - - if (vlan_id > MAX_VLAN_ID) - return SW_OUT_OF_RANGE; - - SW_SET_REG_BY_FIELD(VLAN_TABLE_FUNC1, VLAN_ID, vlan_id, reg[1]); - HSL_REG_ENTRY_SET(rv, dev_id, VLAN_TABLE_FUNC1, 0, - (a_uint8_t *) (®[1]), sizeof (a_uint32_t)); - - SW_RTN_ON_ERROR(rv); - - rv = _dess_vlan_commit(dev_id, VLAN_NEXT_ENTRY); - SW_RTN_ON_ERROR(rv); - - rv = _dess_vlan_up_to_sw(dev_id, reg); - SW_RTN_ON_ERROR(rv); - - _dess_vlan_hw_to_sw(reg, p_vlan); - - if (0 == p_vlan->vid) - { - return SW_NO_MORE; - } - else - { - return SW_OK; - } -} - -static sw_error_t -_dess_vlan_find(a_uint32_t dev_id, a_uint32_t vlan_id, fal_vlan_t * p_vlan) -{ - sw_error_t rv; - a_uint32_t reg[2] = { 0 }; - - HSL_DEV_ID_CHECK(dev_id); - - rv = _dess_vlan_hwentry_get(dev_id, vlan_id, reg); - SW_RTN_ON_ERROR(rv); - - _dess_vlan_hw_to_sw(reg, p_vlan); - return SW_OK; -} - -static sw_error_t -_dess_vlan_delete(a_uint32_t dev_id, a_uint32_t vlan_id) -{ - sw_error_t rv; - a_uint32_t reg; - - HSL_DEV_ID_CHECK(dev_id); - - if (vlan_id > MAX_VLAN_ID) - { - return SW_OUT_OF_RANGE; - } - - reg = (a_int32_t) vlan_id; - HSL_REG_FIELD_SET(rv, dev_id, VLAN_TABLE_FUNC1, 0, VLAN_ID, - (a_uint8_t *) (®), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - - rv = _dess_vlan_commit(dev_id, VLAN_PURGE_ENTRY); - return rv; -} - -static sw_error_t -_dess_vlan_flush(a_uint32_t dev_id) -{ - sw_error_t rv; - - HSL_DEV_ID_CHECK(dev_id); - - rv = _dess_vlan_commit(dev_id, VLAN_FLUSH); - return rv; -} - -static sw_error_t -_dess_vlan_fid_set(a_uint32_t dev_id, a_uint32_t vlan_id, a_uint32_t fid) -{ - sw_error_t rv; - a_uint32_t reg[2] = { 0 }; - - HSL_DEV_ID_CHECK(dev_id); - - if ((MAX_VLAN_ID < fid) && (FAL_SVL_FID != fid)) - { - return SW_BAD_PARAM; - } - - if ((MAX_VLAN_ID >= fid) && (vlan_id != fid)) - { - return SW_BAD_PARAM; - } - - rv = _dess_vlan_hwentry_get(dev_id, vlan_id, reg); - SW_RTN_ON_ERROR(rv); - - if (FAL_SVL_FID == fid) - { - SW_SET_REG_BY_FIELD(VLAN_TABLE_FUNC0, IVL_EN, 0, reg[0]); - } - else - { - SW_SET_REG_BY_FIELD(VLAN_TABLE_FUNC0, IVL_EN, 1, reg[0]); - } - - rv = _dess_vlan_down_to_hw(dev_id, reg); - SW_RTN_ON_ERROR(rv); - - rv = _dess_vlan_commit(dev_id, VLAN_LOAD_ENTRY); - if (SW_FULL == rv) - { - rv = SW_OK; - } - return rv; -} - -static sw_error_t -_dess_vlan_fid_get(a_uint32_t dev_id, a_uint32_t vlan_id, a_uint32_t * fid) -{ - sw_error_t rv; - a_uint32_t data, reg[2] = { 0 }; - - HSL_DEV_ID_CHECK(dev_id); - - rv = _dess_vlan_hwentry_get(dev_id, vlan_id, reg); - SW_RTN_ON_ERROR(rv); - - SW_GET_FIELD_BY_REG(VLAN_TABLE_FUNC0, IVL_EN, data, reg[0]); - if (data) - { - *fid = vlan_id; - } - else - { - *fid = FAL_SVL_FID; - } - return SW_OK; -} - -static sw_error_t -_dess_vlan_member_update(a_uint32_t dev_id, a_uint32_t vlan_id, - fal_port_t port_id, a_uint32_t port_info) -{ - sw_error_t rv; - a_uint32_t data, reg[2] = { 0 }; - - HSL_DEV_ID_CHECK(dev_id); - - if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU)) - { - return SW_BAD_PARAM; - } - - rv = _dess_vlan_hwentry_get(dev_id, vlan_id, reg); - SW_RTN_ON_ERROR(rv); - - SW_GET_FIELD_BY_REG(VLAN_TABLE_FUNC0, VID_MEM, data, reg[0]); - data &= (~(0x3 << (port_id << 1))); - data |= ((port_info & 0x3) << (port_id << 1)); - SW_SET_REG_BY_FIELD(VLAN_TABLE_FUNC0, VID_MEM, data, reg[0]); - - rv = _dess_vlan_down_to_hw(dev_id, reg); - SW_RTN_ON_ERROR(rv); - - rv = _dess_vlan_commit(dev_id, VLAN_LOAD_ENTRY); - if (SW_FULL == rv) - { - rv = SW_OK; - } - return rv; -} - -static sw_error_t -_dess_vlan_member_add(a_uint32_t dev_id, a_uint32_t vlan_id, - fal_port_t port_id, fal_pt_1q_egmode_t port_info) -{ - sw_error_t rv; - a_uint32_t info = 0; - - if (FAL_EG_UNMODIFIED == port_info) - { - info = 0; - } - else if (FAL_EG_TAGGED == port_info) - { - info = 0x2; - } - else if (FAL_EG_UNTAGGED == port_info) - { - info = 0x1; - } - else - { - return SW_BAD_PARAM; - } - - rv = _dess_vlan_member_update(dev_id, vlan_id, port_id, info); - return rv; -} - -static sw_error_t -_dess_vlan_member_del(a_uint32_t dev_id, a_uint32_t vlan_id, fal_port_t port_id) -{ - sw_error_t rv; - a_uint32_t info = 0x3; - - rv = _dess_vlan_member_update(dev_id, vlan_id, port_id, info); - return rv; -} - -static sw_error_t -_dess_vlan_learning_state_set(a_uint32_t dev_id, a_uint32_t vlan_id, - a_bool_t enable) -{ - sw_error_t rv; - a_uint32_t reg[2] = { 0 }; - - HSL_DEV_ID_CHECK(dev_id); - - rv = _dess_vlan_hwentry_get(dev_id, vlan_id, reg); - SW_RTN_ON_ERROR(rv); - - if (A_TRUE == enable) - { - SW_SET_REG_BY_FIELD(VLAN_TABLE_FUNC0, LEARN_DIS, 0, reg[0]); - } - else if (A_FALSE == enable) - { - SW_SET_REG_BY_FIELD(VLAN_TABLE_FUNC0, LEARN_DIS, 1, reg[0]); - } - else - { - return SW_BAD_PARAM; - } - - rv = _dess_vlan_down_to_hw(dev_id, reg); - SW_RTN_ON_ERROR(rv); - - rv = _dess_vlan_commit(dev_id, VLAN_LOAD_ENTRY); - if (SW_FULL == rv) - { - rv = SW_OK; - } - return rv; -} - -static sw_error_t -_dess_vlan_learning_state_get(a_uint32_t dev_id, a_uint32_t vlan_id, - a_bool_t * enable) -{ - sw_error_t rv; - a_uint32_t data, reg[2] = { 0 }; - - HSL_DEV_ID_CHECK(dev_id); - - rv = _dess_vlan_hwentry_get(dev_id, vlan_id, reg); - SW_RTN_ON_ERROR(rv); - - SW_GET_FIELD_BY_REG(VLAN_TABLE_FUNC0, LEARN_DIS, data, reg[0]); - if (data) - { - *enable = A_FALSE; - } - else - { - *enable = A_TRUE; - } - return SW_OK; -} - -/** - * @brief Append a vlan entry on paticular device. - * @param[in] dev_id device id - * @param[in] vlan_entry vlan entry - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -dess_vlan_entry_append(a_uint32_t dev_id, const fal_vlan_t * vlan_entry) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _dess_vlan_entry_append(dev_id, vlan_entry); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Creat a vlan entry through vlan id on a paticular device. - * @details Comments: - * After this operation the member ports of the created vlan entry are null. - * @param[in] dev_id device id - * @param[in] vlan_id vlan id - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -dess_vlan_create(a_uint32_t dev_id, a_uint32_t vlan_id) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _dess_vlan_create(dev_id, vlan_id); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Next a vlan entry through vlan id on a paticular device. - * @details Comments: - * If the value of vid is zero this operation will get the first entry. - * @param[in] dev_id device id - * @param[in] vlan_id vlan id - * @param[out] p_vlan vlan entry - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -dess_vlan_next(a_uint32_t dev_id, a_uint32_t vlan_id, fal_vlan_t * p_vlan) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _dess_vlan_next(dev_id, vlan_id, p_vlan); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Find a vlan entry through vlan id on paticular device. - * @param[in] dev_id device id - * @param[in] vlan_id vlan id - * @param[out] p_vlan vlan entry - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -dess_vlan_find(a_uint32_t dev_id, a_uint32_t vlan_id, fal_vlan_t * p_vlan) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _dess_vlan_find(dev_id, vlan_id, p_vlan); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Delete a vlan entry through vlan id on a paticular device. - * @param[in] dev_id device id - * @param[in] vlan_id vlan id - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -dess_vlan_delete(a_uint32_t dev_id, a_uint32_t vlan_id) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _dess_vlan_delete(dev_id, vlan_id); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Flush all vlan entries on a paticular device. - * @param[in] dev_id device id - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -dess_vlan_flush(a_uint32_t dev_id) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _dess_vlan_flush(dev_id); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Set FID of a paticular vlan entry on a paticular device. - * @param[in] dev_id device id - * @param[in] vlan_id vlan id - * @param[in] fid FDB id - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -dess_vlan_fid_set(a_uint32_t dev_id, a_uint32_t vlan_id, a_uint32_t fid) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _dess_vlan_fid_set(dev_id, vlan_id, fid); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Get FID of a paticular vlan entry on a paticular device. - * @param[in] dev_id device id - * @param[in] vlan_id vlan id - * @param[out] fid FDB id - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -dess_vlan_fid_get(a_uint32_t dev_id, a_uint32_t vlan_id, a_uint32_t * fid) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _dess_vlan_fid_get(dev_id, vlan_id, fid); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Add a port member to a paticular vlan entry on a paticular device. - * @param[in] dev_id device id - * @param[in] vlan_id vlan id - * @param[in] port_id port id - * @param[in] port_info port tag information - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -dess_vlan_member_add(a_uint32_t dev_id, a_uint32_t vlan_id, - fal_port_t port_id, fal_pt_1q_egmode_t port_info) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _dess_vlan_member_add(dev_id, vlan_id, port_id, port_info); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Del a port member from a paticular vlan entry on a paticular device. - * @param[in] dev_id device id - * @param[in] vlan_id vlan id - * @param[in] port_id port id - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -dess_vlan_member_del(a_uint32_t dev_id, a_uint32_t vlan_id, fal_port_t port_id) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _dess_vlan_member_del(dev_id, vlan_id, port_id); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Set FDB learning status of a paticular vlan entry on a paticular device. - * @param[in] dev_id device id - * @param[in] vlan_id vlan id - * @param[in] enable A_TRUE or A_FALSE - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -dess_vlan_learning_state_set(a_uint32_t dev_id, a_uint32_t vlan_id, - a_bool_t enable) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _dess_vlan_learning_state_set(dev_id, vlan_id, enable); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Get FDB learning status of a paticular vlan entry on a paticular device. - * @param[in] dev_id device id - * @param[in] vlan_id vlan id - * @param[out] enable A_TRUE or A_FALSE - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -dess_vlan_learning_state_get(a_uint32_t dev_id, a_uint32_t vlan_id, - a_bool_t * enable) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _dess_vlan_learning_state_get(dev_id, vlan_id, enable); - HSL_API_UNLOCK; - return rv; -} - -sw_error_t -dess_vlan_init(a_uint32_t dev_id) -{ - hsl_api_t *p_api; - HSL_DEV_ID_CHECK(dev_id); - -#ifndef HSL_STANDALONG - - SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id)); - - p_api->vlan_entry_append = dess_vlan_entry_append; - p_api->vlan_creat = dess_vlan_create; - p_api->vlan_delete = dess_vlan_delete; - p_api->vlan_next = dess_vlan_next; - p_api->vlan_find = dess_vlan_find; - p_api->vlan_flush = dess_vlan_flush; - p_api->vlan_fid_set = dess_vlan_fid_set; - p_api->vlan_fid_get = dess_vlan_fid_get; - p_api->vlan_member_add = dess_vlan_member_add; - p_api->vlan_member_del = dess_vlan_member_del; - p_api->vlan_learning_state_set = dess_vlan_learning_state_set; - p_api->vlan_learning_state_get = dess_vlan_learning_state_get; - - -#endif - - return SW_OK; -} - -/** - * @} - */ - diff --git a/feeds/ipq807x/qca-ssdk/src/src/hsl/garuda/Makefile b/feeds/ipq807x/qca-ssdk/src/src/hsl/garuda/Makefile deleted file mode 100755 index 67ebb1247..000000000 --- a/feeds/ipq807x/qca-ssdk/src/src/hsl/garuda/Makefile +++ /dev/null @@ -1,84 +0,0 @@ -LOC_DIR=src/hsl/garuda -LIB=HSL - -include $(PRJ_PATH)/make/config.mk - -SRC_LIST=garuda_reg_access.c garuda_init.c - -ifeq (TRUE, $(IN_ACL)) - SRC_LIST += garuda_acl.c -endif - -ifeq (TRUE, $(IN_FDB)) - SRC_LIST += garuda_fdb.c -endif - -ifeq (TRUE, $(IN_IGMP)) - SRC_LIST += garuda_igmp.c -endif - -ifeq (TRUE, $(IN_LEAKY)) - SRC_LIST += garuda_leaky.c -endif - -ifeq (TRUE, $(IN_LED)) - SRC_LIST += garuda_led.c -endif - -ifeq (TRUE, $(IN_MIB)) - SRC_LIST += garuda_mib.c -endif - -ifeq (TRUE, $(IN_MIRROR)) - SRC_LIST += garuda_mirror.c -endif - -ifeq (TRUE, $(IN_MISC)) - SRC_LIST += garuda_misc.c -endif - -ifeq (TRUE, $(IN_PORTCONTROL)) - SRC_LIST += garuda_port_ctrl.c -endif - -ifeq (TRUE, $(IN_PORTVLAN)) - SRC_LIST += garuda_portvlan.c -endif - -ifeq (TRUE, $(IN_QOS)) - SRC_LIST += garuda_qos.c -endif - -ifeq (TRUE, $(IN_RATE)) - SRC_LIST += garuda_rate.c -endif - -ifeq (TRUE, $(IN_STP)) - SRC_LIST += garuda_stp.c -endif - -ifeq (TRUE, $(IN_VLAN)) - SRC_LIST += garuda_vlan.c -endif - -ifeq (TRUE, $(IN_REDUCED_ACL)) - SRC_LIST += garuda_reduced_acl.c -endif - -ifeq (linux, $(OS)) - ifeq (KSLIB, $(MODULE_TYPE)) - ifneq (TRUE, $(KERNEL_MODE)) - SRC_LIST=garuda_reg_access.c garuda_init.c - endif - endif -endif - -ifeq (, $(findstring GARUDA, $(SUPPORT_CHIP))) - SRC_LIST= -endif - -include $(PRJ_PATH)/make/components.mk -include $(PRJ_PATH)/make/defs.mk -include $(PRJ_PATH)/make/target.mk - -all: dep obj \ No newline at end of file diff --git a/feeds/ipq807x/qca-ssdk/src/src/hsl/garuda/garuda_acl.c b/feeds/ipq807x/qca-ssdk/src/src/hsl/garuda/garuda_acl.c deleted file mode 100755 index 216468fc0..000000000 --- a/feeds/ipq807x/qca-ssdk/src/src/hsl/garuda/garuda_acl.c +++ /dev/null @@ -1,3034 +0,0 @@ -/* - * Copyright (c) 2012, The Linux Foundation. All rights reserved. - * Permission to use, copy, modify, and/or distribute this software for - * any purpose with or without fee is hereby granted, provided that the - * above copyright notice and this permission notice appear in all copies. - * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES - * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR - * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES - * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN - * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT - * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. - */ - - - -/** - * @defgroup garuda_acl GARUDA_ACL - * @{ - */ - -#include "sw.h" -#include "hsl.h" -#include "hsl_dev.h" -#include "hsl_acl.h" -#include "hsl_port_prop.h" -#include "garuda_acl.h" -#include "garuda_reg.h" - -//#define GARUDA_ACL_DEBUG -//#define GARUDA_SW_ENTRY -//#define GARUDA_ENTRY_DUMP - -typedef struct -{ - a_uint32_t list_id; - a_uint32_t list_pri; - a_uint32_t addr; - a_uint32_t size; - a_uint32_t status; - fal_pbmp_t bind_pts; -} garuda_acl_list_t; - -typedef struct -{ - a_uint32_t slct[8]; - a_uint32_t vlu[5]; - a_uint32_t msk[5]; - a_uint32_t typ; - a_uint32_t act; -} garuda_acl_hw_rule_t; - -static garuda_acl_list_t *list_ent[SW_MAX_NR_DEV]; -static garuda_acl_hw_rule_t *hw_rule_ent; - -static a_uint32_t filter[SW_MAX_NR_DEV]; -static a_uint32_t filter_snap[SW_MAX_NR_DEV]; - -#define GARUDA_MAX_LIST 32 -#define GARUDA_MAX_RULE 32 - -#define ENT_FREE 0x1 -#define ENT_USED 0x2 - -#define GARUDA_RULE_VLU_ADDR 0x58400 -#define GARUDA_RULE_MSK_ADDR 0x58c00 -#define GARUDA_RULE_TYP_ADDR 0x5881c -#define GARUDA_RULE_ACT_ADDR 0x58000 -#define GARUDA_RULE_SLCT_ADDR 0x58800 - -#define GARUDA_MAC_FILTER 1 -#define GARUDA_IP4_FILTER 2 -#define GARUDA_IP6R1_FILTER 3 -#define GARUDA_IP6R2_FILTER 4 -#define GARUDA_IP6R3_FILTER 5 - -#ifdef GARUDA_SW_ENTRY -static char *flt_vlu_mem = NULL; -static char *flt_msk_mem = NULL; -static char *flt_typ_mem = NULL; -static char *act_mem = NULL; -static char *slct_mem = NULL; -#endif - -static a_bool_t _garuda_acl_zero_addr(const fal_mac_addr_t addr); - -static a_bool_t -_garuda_acl_field_care(fal_acl_field_op_t op, a_uint32_t val, a_uint32_t mask, - a_uint32_t chkvlu); - -static sw_error_t -_garuda_acl_list_loc(a_uint32_t dev_id, a_uint32_t list_id, a_uint32_t * idx); - -static sw_error_t -_garuda_acl_filter_map_get(const garuda_acl_hw_rule_t * rule, - a_uint32_t flt_idx[], a_uint32_t * flt_nr); - -static sw_error_t -_garuda_acl_rule_mac_parse(fal_acl_rule_t * sw, fal_pbmp_t bind_pts, - garuda_acl_hw_rule_t * hw, a_bool_t * b_care, - a_uint32_t * len); - -static sw_error_t -_garuda_acl_rule_ip4_parse(fal_acl_rule_t * sw, fal_pbmp_t bind_pts, - garuda_acl_hw_rule_t * hw, a_bool_t * b_care, - a_uint32_t * len); - -static sw_error_t -_garuda_acl_rule_ip6r1_parse(fal_acl_rule_t * sw, fal_pbmp_t bind_pts, - garuda_acl_hw_rule_t * hw, a_bool_t * b_care, - a_uint32_t * len); - -static sw_error_t -_garuda_acl_rule_ip6r2_parse(fal_acl_rule_t * sw, fal_pbmp_t bind_pts, - garuda_acl_hw_rule_t * hw, a_bool_t * b_care, - a_uint32_t * len); - -static sw_error_t -_garuda_acl_rule_ip6r3_parse(fal_acl_rule_t * sw, fal_pbmp_t bind_pts, - garuda_acl_hw_rule_t * hw, a_bool_t * b_care, - a_uint32_t * len); - -static sw_error_t -_garuda_acl_action_parse(a_uint32_t dev_id, const fal_acl_rule_t * sw, - garuda_acl_hw_rule_t * hw); - -static sw_error_t -_garuda_acl_rule_mac_reparse(fal_acl_rule_t * sw, - const garuda_acl_hw_rule_t * hw); - -static sw_error_t -_garuda_acl_rule_ip4_reparse(fal_acl_rule_t * sw, - const garuda_acl_hw_rule_t * hw); - -static sw_error_t -_garuda_acl_rule_ip6r1_reparse(fal_acl_rule_t * sw, - const garuda_acl_hw_rule_t * hw); - -static sw_error_t -_garuda_acl_rule_ip6r2_reparse(fal_acl_rule_t * sw, - const garuda_acl_hw_rule_t * hw); - -static sw_error_t -_garuda_acl_rule_ip6r3_reparse(fal_acl_rule_t * sw, - const garuda_acl_hw_rule_t * hw); - -static sw_error_t -_garuda_acl_rule_action_reparse(fal_acl_rule_t * sw, - const garuda_acl_hw_rule_t * hw); - -static sw_error_t -_garuda_acl_filter_alloc(a_uint32_t dev_id, a_uint32_t * idx); - -static void -_garuda_acl_filter_free(a_uint32_t dev_id, a_uint32_t idx); - -static void -_garuda_acl_filter_snap(a_uint32_t dev_id); - -static void -_garuda_acl_filter_commit(a_uint32_t dev_id); - -static sw_error_t -_garuda_acl_slct_update(garuda_acl_hw_rule_t * hw, a_uint32_t offset, - a_uint32_t flt_idx); - -static sw_error_t -_garuda_acl_filter_write(a_uint32_t dev_id, const garuda_acl_hw_rule_t * rule, - a_uint32_t flt_idx); - -static sw_error_t -_garuda_acl_action_write(a_uint32_t dev_id, const garuda_acl_hw_rule_t * rule, - a_uint32_t act_idx); - -static sw_error_t -_garuda_acl_slct_write(a_uint32_t dev_id, const garuda_acl_hw_rule_t * rule, - a_uint32_t slct_idx); - -static sw_error_t -_garuda_acl_filter_read(a_uint32_t dev_id, garuda_acl_hw_rule_t * rule, - a_uint32_t flt_idx); - -static sw_error_t -_garuda_acl_action_read(a_uint32_t dev_id, garuda_acl_hw_rule_t * rule, - a_uint32_t act_idx); - -static sw_error_t -_garuda_acl_slct_read(a_uint32_t dev_id, garuda_acl_hw_rule_t * rule, - a_uint32_t slct_idx); - -static sw_error_t -_garuda_acl_rule_set(a_uint32_t dev_id, a_uint32_t base_addr, - const garuda_acl_hw_rule_t * hw_rule_ent, - a_uint32_t rule_nr); - -static sw_error_t -_garuda_acl_rule_get(a_uint32_t dev_id, garuda_acl_hw_rule_t * rule, - a_uint32_t * ent_idx, a_uint32_t rule_idx); - -static sw_error_t -_garuda_acl_rule_sw_to_hw(a_uint32_t dev_id, fal_acl_rule_t * sw, - fal_pbmp_t bind_pts, garuda_acl_hw_rule_t * hw, - a_uint32_t * idx, a_uint32_t * flt_len); - -static sw_error_t -_garuda_acl_rule_hw_to_sw(fal_acl_rule_t * sw, const garuda_acl_hw_rule_t * hw, - a_uint32_t ent_idx, a_uint32_t ent_nr); - -static sw_error_t -_garuda_acl_rule_copy(a_uint32_t dev_id, a_uint32_t src_slct_idx, - a_uint32_t dst_slct_idx, a_uint32_t size); - -static sw_error_t -_garuda_acl_rule_invalid(a_uint32_t dev_id, a_uint32_t rule_idx, - a_uint32_t size); - -static sw_error_t -_garuda_acl_rule_valid(a_uint32_t dev_id, a_uint32_t rule_idx, a_uint32_t size, - a_uint32_t flag); - -static sw_error_t -_garuda_acl_addr_update(a_uint32_t dev_id, a_uint32_t old_addr, - a_uint32_t new_addr, a_uint32_t list_id); - -static sw_error_t -_garuda_acl_rule_bind(a_uint32_t dev_id, a_uint32_t rule_idx, a_uint32_t ports); - -#ifdef GARUDA_ACL_DEBUG -static void -_garuda_acl_list_dump(a_uint32_t dev_id) -{ - a_uint32_t i; - - aos_printk("\ndev_id=%d list control infomation", dev_id); - for (i = 0; i < GARUDA_MAX_LIST; i++) - { - if (ENT_USED == list_ent[dev_id][i].status) - { - aos_printk("\nlist_id=%d list_pri=%d addr=%d size=%d idx=%d ", - list_ent[dev_id][i].list_id, - list_ent[dev_id][i].list_pri, - list_ent[dev_id][i].addr, list_ent[dev_id][i].size, i); - } - } - aos_printk("\n"); -} -#else -#define _garuda_acl_list_dump(dev_id) -#endif - -static a_bool_t -_garuda_acl_zero_addr(const fal_mac_addr_t addr) -{ - a_uint32_t i; - - for (i = 0; i < 6; i++) - { - if (addr.uc[i]) - { - return A_FALSE; - } - } - return A_TRUE; -} - -static a_bool_t -_garuda_acl_field_care(fal_acl_field_op_t op, a_uint32_t val, a_uint32_t mask, - a_uint32_t chkvlu) -{ - if (FAL_ACL_FIELD_MASK == op) - { - if (0 == mask) - return A_FALSE; - } - else if (FAL_ACL_FIELD_RANGE == op) - { - if ((0 == val) && (chkvlu == mask)) - return A_FALSE; - } - else if (FAL_ACL_FIELD_LE == op) - { - if (chkvlu == val) - return A_FALSE; - } - else if (FAL_ACL_FIELD_GE == op) - { - if (0 == val) - return A_FALSE; - } - else if (FAL_ACL_FIELD_NE == op) - { - return A_TRUE; - } - - return A_TRUE; -} - -static sw_error_t -_garuda_acl_list_loc(a_uint32_t dev_id, a_uint32_t list_id, a_uint32_t * idx) -{ - a_uint32_t i; - - for (i = 0; i < GARUDA_MAX_LIST; i++) - { - if ((ENT_USED == list_ent[dev_id][i].status) - && (list_id == list_ent[dev_id][i].list_id)) - { - *idx = i; - return SW_OK; - } - } - return SW_NOT_FOUND; -} - -static sw_error_t -_garuda_acl_filter_map_get(const garuda_acl_hw_rule_t * rule, - a_uint32_t flt_idx[], a_uint32_t * flt_nr) -{ - a_uint32_t flt_en, idx, i = 0; - - SW_GET_FIELD_BY_REG(RUL_SLCT0, ADDR0_EN, flt_en, (rule->slct[0])); - if (flt_en) - { - SW_GET_FIELD_BY_REG(RUL_SLCT1, ADDR0, idx, (rule->slct[1])); - flt_idx[i] = idx; - i++; - } - - SW_GET_FIELD_BY_REG(RUL_SLCT0, ADDR1_EN, flt_en, (rule->slct[0])); - if (flt_en) - { - SW_GET_FIELD_BY_REG(RUL_SLCT2, ADDR1, idx, (rule->slct[2])); - flt_idx[i] = idx; - i++; - } - - SW_GET_FIELD_BY_REG(RUL_SLCT0, ADDR2_EN, flt_en, (rule->slct[0])); - if (flt_en) - { - SW_GET_FIELD_BY_REG(RUL_SLCT3, ADDR2, idx, (rule->slct[3])); - flt_idx[i] = idx; - i++; - } - - SW_GET_FIELD_BY_REG(RUL_SLCT0, ADDR3_EN, flt_en, (rule->slct[0])); - if (flt_en) - { - SW_GET_FIELD_BY_REG(RUL_SLCT4, ADDR3, idx, (rule->slct[4])); - flt_idx[i] = idx; - i++; - } - - *flt_nr = i; - return SW_OK; -} - -static sw_error_t -_garuda_acl_rule_mac_parse(fal_acl_rule_t * sw, fal_pbmp_t bind_pts, - garuda_acl_hw_rule_t * hw, a_bool_t * b_care, - a_uint32_t * len) -{ - a_uint32_t i; - - *b_care = A_FALSE; - *len = 0; - - aos_mem_zero(&(hw->vlu[0]), sizeof (hw->vlu)); - aos_mem_zero(&(hw->msk[0]), sizeof (hw->msk)); - aos_mem_zero(&(hw->typ), sizeof (hw->typ)); - - SW_SET_REG_BY_FIELD(MAC_RUL_V4, MAC_INPT, bind_pts, hw->vlu[4]); - SW_SET_REG_BY_FIELD(RUL_TYPE, TYP, GARUDA_MAC_FILTER, hw->typ); - - if (FAL_FIELD_FLG_TST(sw->field_flg, FAL_ACL_FIELD_MAC_DA)) - { - if (A_TRUE != _garuda_acl_zero_addr(sw->dest_mac_mask)) - { - *b_care = A_TRUE; - *len = 6; - } - - for (i = 0; i < 6; i++) - { - sw->dest_mac_val.uc[i] &= sw->dest_mac_mask.uc[i]; - } - - SW_SET_REG_BY_FIELD(MAC_RUL_V0, DAV_BYTE2, sw->dest_mac_val.uc[2], - hw->vlu[0]); - SW_SET_REG_BY_FIELD(MAC_RUL_V0, DAV_BYTE3, sw->dest_mac_val.uc[3], - hw->vlu[0]); - SW_SET_REG_BY_FIELD(MAC_RUL_V0, DAV_BYTE4, sw->dest_mac_val.uc[4], - hw->vlu[0]); - SW_SET_REG_BY_FIELD(MAC_RUL_V0, DAV_BYTE5, sw->dest_mac_val.uc[5], - hw->vlu[0]); - SW_SET_REG_BY_FIELD(MAC_RUL_V1, DAV_BYTE0, sw->dest_mac_val.uc[0], - hw->vlu[1]); - SW_SET_REG_BY_FIELD(MAC_RUL_V1, DAV_BYTE1, sw->dest_mac_val.uc[1], - hw->vlu[1]); - - SW_SET_REG_BY_FIELD(MAC_RUL_M0, DAM_BYTE2, sw->dest_mac_mask.uc[2], - hw->msk[0]); - SW_SET_REG_BY_FIELD(MAC_RUL_M0, DAM_BYTE3, sw->dest_mac_mask.uc[3], - hw->msk[0]); - SW_SET_REG_BY_FIELD(MAC_RUL_M0, DAM_BYTE4, sw->dest_mac_mask.uc[4], - hw->msk[0]); - SW_SET_REG_BY_FIELD(MAC_RUL_M0, DAM_BYTE5, sw->dest_mac_mask.uc[5], - hw->msk[0]); - SW_SET_REG_BY_FIELD(MAC_RUL_M1, DAM_BYTE0, sw->dest_mac_mask.uc[0], - hw->msk[1]); - SW_SET_REG_BY_FIELD(MAC_RUL_M1, DAM_BYTE1, sw->dest_mac_mask.uc[1], - hw->msk[1]); - } - - if (FAL_FIELD_FLG_TST(sw->field_flg, FAL_ACL_FIELD_MAC_SA)) - { - if (A_TRUE != _garuda_acl_zero_addr(sw->src_mac_mask)) - { - *b_care = A_TRUE; - *len = 12; - } - - for (i = 0; i < 6; i++) - { - sw->src_mac_val.uc[i] &= sw->src_mac_mask.uc[i]; - } - - SW_SET_REG_BY_FIELD(MAC_RUL_V1, SAV_BYTE4, sw->src_mac_val.uc[4], - hw->vlu[1]); - SW_SET_REG_BY_FIELD(MAC_RUL_V1, SAV_BYTE5, sw->src_mac_val.uc[5], - hw->vlu[1]); - SW_SET_REG_BY_FIELD(MAC_RUL_V2, SAV_BYTE0, sw->src_mac_val.uc[0], - hw->vlu[2]); - SW_SET_REG_BY_FIELD(MAC_RUL_V2, SAV_BYTE1, sw->src_mac_val.uc[1], - hw->vlu[2]); - SW_SET_REG_BY_FIELD(MAC_RUL_V2, SAV_BYTE2, sw->src_mac_val.uc[2], - hw->vlu[2]); - SW_SET_REG_BY_FIELD(MAC_RUL_V2, SAV_BYTE3, sw->src_mac_val.uc[3], - hw->vlu[2]); - - SW_SET_REG_BY_FIELD(MAC_RUL_M1, SAM_BYTE4, sw->src_mac_mask.uc[4], - hw->msk[1]); - SW_SET_REG_BY_FIELD(MAC_RUL_M1, SAM_BYTE5, sw->src_mac_mask.uc[5], - hw->msk[1]); - SW_SET_REG_BY_FIELD(MAC_RUL_M2, SAM_BYTE0, sw->src_mac_mask.uc[0], - hw->msk[2]); - SW_SET_REG_BY_FIELD(MAC_RUL_M2, SAM_BYTE1, sw->src_mac_mask.uc[1], - hw->msk[2]); - SW_SET_REG_BY_FIELD(MAC_RUL_M2, SAM_BYTE2, sw->src_mac_mask.uc[2], - hw->msk[2]); - SW_SET_REG_BY_FIELD(MAC_RUL_M2, SAM_BYTE3, sw->src_mac_mask.uc[3], - hw->msk[2]); - } - - if (FAL_FIELD_FLG_TST(sw->field_flg, FAL_ACL_FIELD_MAC_ETHTYPE)) - { - if (0x0 != sw->ethtype_mask) - { - *b_care = A_TRUE; - *len = 14; - } - - sw->ethtype_val &= sw->ethtype_mask; - SW_SET_REG_BY_FIELD(MAC_RUL_V3, ETHTYPV, sw->ethtype_val, hw->vlu[3]); - SW_SET_REG_BY_FIELD(MAC_RUL_M3, ETHTYPM, sw->ethtype_mask, hw->msk[3]); - } - - if (FAL_FIELD_FLG_TST(sw->field_flg, FAL_ACL_FIELD_MAC_TAGGED)) - { - if (0x0 != sw->tagged_mask) - { - *b_care = A_TRUE; - } - - sw->tagged_val &= sw->tagged_mask; - SW_SET_REG_BY_FIELD(MAC_RUL_V4, TAGGEDV, sw->tagged_val, hw->vlu[4]); - SW_SET_REG_BY_FIELD(MAC_RUL_V4, TAGGEDM, sw->tagged_mask, hw->vlu[4]); - } - - if (FAL_FIELD_FLG_TST(sw->field_flg, FAL_ACL_FIELD_MAC_UP)) - { - if (0x0 != sw->up_mask) - { - *b_care = A_TRUE; - } - - sw->up_val &= sw->up_mask; - SW_SET_REG_BY_FIELD(MAC_RUL_V3, VLANPRIV, sw->up_val, hw->vlu[3]); - SW_SET_REG_BY_FIELD(MAC_RUL_M3, VLANPRIM, sw->up_mask, hw->msk[3]); - } - - SW_SET_REG_BY_FIELD(MAC_RUL_M3, VIDMSK, 1, hw->msk[3]); - if (FAL_FIELD_FLG_TST(sw->field_flg, FAL_ACL_FIELD_MAC_VID)) - { - if ((FAL_ACL_FIELD_MASK != sw->vid_op) - && (FAL_ACL_FIELD_RANGE != sw->vid_op) - && (FAL_ACL_FIELD_LE != sw->vid_op) - && (FAL_ACL_FIELD_GE != sw->vid_op)) - { - return SW_NOT_SUPPORTED; - } - - if (A_TRUE == - _garuda_acl_field_care(sw->vid_op, sw->vid_val, sw->vid_mask, - 0xfff)) - { - *b_care = A_TRUE; - } - - SW_SET_REG_BY_FIELD(MAC_RUL_M3, VIDMSK, 0, hw->msk[3]); - if (FAL_ACL_FIELD_MASK == sw->vid_op) - { - sw->vid_val &= sw->vid_mask; - SW_SET_REG_BY_FIELD(MAC_RUL_V3, VLANIDV, sw->vid_val, hw->vlu[3]); - SW_SET_REG_BY_FIELD(MAC_RUL_M3, VLANIDM, sw->vid_mask, hw->msk[3]); - SW_SET_REG_BY_FIELD(MAC_RUL_M3, VIDMSK, 1, hw->msk[3]); - } - else if (FAL_ACL_FIELD_RANGE == sw->vid_op) - { - SW_SET_REG_BY_FIELD(MAC_RUL_V3, VLANIDV, sw->vid_val, hw->vlu[3]); - SW_SET_REG_BY_FIELD(MAC_RUL_M3, VLANIDM, sw->vid_mask, hw->msk[3]); - } - else if (FAL_ACL_FIELD_LE == sw->vid_op) - { - SW_SET_REG_BY_FIELD(MAC_RUL_V3, VLANIDV, 0, hw->vlu[3]); - SW_SET_REG_BY_FIELD(MAC_RUL_M3, VLANIDM, sw->vid_val, hw->msk[3]); - } - else - { - SW_SET_REG_BY_FIELD(MAC_RUL_V3, VLANIDV, sw->vid_val, hw->vlu[3]); - SW_SET_REG_BY_FIELD(MAC_RUL_M3, VLANIDM, 0xfff, hw->msk[3]); - } - } - - return SW_OK; -} - -static sw_error_t -_garuda_acl_rule_ip4_parse(fal_acl_rule_t * sw, fal_pbmp_t bind_pts, - garuda_acl_hw_rule_t * hw, a_bool_t * b_care, - a_uint32_t * len) -{ - *b_care = A_FALSE; - *len = 0; - - aos_mem_zero(&(hw->vlu[0]), sizeof (hw->vlu)); - aos_mem_zero(&(hw->msk[0]), sizeof (hw->msk)); - aos_mem_zero(&(hw->typ), sizeof (hw->typ)); - - SW_SET_REG_BY_FIELD(IP4_RUL_V4, IP4_INPT, bind_pts, hw->vlu[4]); - SW_SET_REG_BY_FIELD(RUL_TYPE, TYP, GARUDA_IP4_FILTER, hw->typ); - - if (FAL_FIELD_FLG_TST(sw->field_flg, FAL_ACL_FIELD_IP_DSCP)) - { - if (0x0 != sw->ip_dscp_mask) - { - *b_care = A_TRUE; - *len = 16; - } - - sw->ip_dscp_val &= sw->ip_dscp_mask; - SW_SET_REG_BY_FIELD(IP4_RUL_V2, IP4DSCPV, sw->ip_dscp_val, hw->vlu[2]); - SW_SET_REG_BY_FIELD(IP4_RUL_M2, IP4DSCPM, sw->ip_dscp_mask, hw->msk[2]); - } - - if (FAL_FIELD_FLG_TST(sw->field_flg, FAL_ACL_FIELD_IP_PROTO)) - { - if (0x0 != sw->ip_proto_mask) - { - *b_care = A_TRUE; - *len = 24; - } - - sw->ip_proto_val &= sw->ip_proto_mask; - SW_SET_REG_BY_FIELD(IP4_RUL_V2, IP4PROTV, sw->ip_proto_val, hw->vlu[2]); - SW_SET_REG_BY_FIELD(IP4_RUL_M2, IP4PROTM, sw->ip_proto_mask, - hw->msk[2]); - } - - if (FAL_FIELD_FLG_TST(sw->field_flg, FAL_ACL_FIELD_IP4_SIP)) - { - if (0x0 != sw->src_ip4_mask) - { - *b_care = A_TRUE; - *len = 30; - } - sw->src_ip4_val &= sw->src_ip4_mask; - hw->vlu[1] = sw->src_ip4_val; - hw->msk[1] = sw->src_ip4_mask; - } - - if (FAL_FIELD_FLG_TST(sw->field_flg, FAL_ACL_FIELD_IP4_DIP)) - { - if (0x0 != sw->dest_ip4_mask) - { - *b_care = A_TRUE; - *len = 34; - } - sw->dest_ip4_val &= sw->dest_ip4_mask; - hw->vlu[0] = sw->dest_ip4_val; - hw->msk[0] = sw->dest_ip4_mask; - } - - SW_SET_REG_BY_FIELD(IP4_RUL_M3, IP4SPORTM_EN, 1, hw->msk[3]); - if (FAL_FIELD_FLG_TST(sw->field_flg, FAL_ACL_FIELD_L4_SPORT)) - { - if ((FAL_ACL_FIELD_MASK != sw->src_l4port_op) - && (FAL_ACL_FIELD_RANGE != sw->src_l4port_op) - && (FAL_ACL_FIELD_LE != sw->src_l4port_op) - && (FAL_ACL_FIELD_GE != sw->src_l4port_op)) - { - return SW_NOT_SUPPORTED; - } - - if (A_TRUE == - _garuda_acl_field_care(sw->src_l4port_op, sw->src_l4port_val, - sw->src_l4port_mask, 0xffff)) - { - *b_care = A_TRUE; - *len = 36; - } - - SW_SET_REG_BY_FIELD(IP4_RUL_M3, IP4SPORTM_EN, 0, hw->msk[3]); - if (FAL_ACL_FIELD_MASK == sw->src_l4port_op) - { - sw->src_l4port_val &= sw->src_l4port_mask; - SW_SET_REG_BY_FIELD(IP4_RUL_V3, IP4SPORTV, sw->src_l4port_val, - hw->vlu[3]); - SW_SET_REG_BY_FIELD(IP4_RUL_M3, IP4SPORTM, sw->src_l4port_mask, - hw->msk[3]); - SW_SET_REG_BY_FIELD(IP4_RUL_M3, IP4SPORTM_EN, 1, hw->msk[3]); - } - else if (FAL_ACL_FIELD_RANGE == sw->src_l4port_op) - { - SW_SET_REG_BY_FIELD(IP4_RUL_V3, IP4SPORTV, sw->src_l4port_val, - hw->vlu[3]); - SW_SET_REG_BY_FIELD(IP4_RUL_M3, IP4SPORTM, sw->src_l4port_mask, - hw->msk[3]); - } - else if (FAL_ACL_FIELD_LE == sw->src_l4port_op) - { - SW_SET_REG_BY_FIELD(IP4_RUL_V3, IP4SPORTV, 0, hw->vlu[3]); - SW_SET_REG_BY_FIELD(IP4_RUL_M3, IP4SPORTM, sw->src_l4port_val, - hw->msk[3]); - } - else - { - SW_SET_REG_BY_FIELD(IP4_RUL_V3, IP4SPORTV, sw->src_l4port_val, - hw->vlu[3]); - SW_SET_REG_BY_FIELD(IP4_RUL_M3, IP4SPORTM, 0xffff, hw->msk[3]); - } - } - - SW_SET_REG_BY_FIELD(IP4_RUL_M3, IP4DPORTM_EN, 1, hw->msk[3]); - if (FAL_FIELD_FLG_TST(sw->field_flg, FAL_ACL_FIELD_L4_DPORT)) - { - if ((FAL_ACL_FIELD_MASK != sw->dest_l4port_op) - && (FAL_ACL_FIELD_RANGE != sw->dest_l4port_op) - && (FAL_ACL_FIELD_LE != sw->dest_l4port_op) - && (FAL_ACL_FIELD_GE != sw->dest_l4port_op)) - { - return SW_NOT_SUPPORTED; - } - - if (A_TRUE == - _garuda_acl_field_care(sw->dest_l4port_op, sw->dest_l4port_val, - sw->dest_l4port_mask, 0xffff)) - { - *b_care = A_TRUE; - *len = 38; - } - - SW_SET_REG_BY_FIELD(IP4_RUL_M3, IP4DPORTM_EN, 0, hw->msk[3]); - if (FAL_ACL_FIELD_MASK == sw->dest_l4port_op) - { - sw->dest_l4port_val &= sw->dest_l4port_mask; - SW_SET_REG_BY_FIELD(IP4_RUL_V2, IP4DPORTV, sw->dest_l4port_val, - hw->vlu[2]); - SW_SET_REG_BY_FIELD(IP4_RUL_M2, IP4DPORTM, sw->dest_l4port_mask, - hw->msk[2]); - SW_SET_REG_BY_FIELD(IP4_RUL_M3, IP4DPORTM_EN, 1, hw->msk[3]); - } - else if (FAL_ACL_FIELD_RANGE == sw->dest_l4port_op) - { - SW_SET_REG_BY_FIELD(IP4_RUL_V2, IP4DPORTV, sw->dest_l4port_val, - hw->vlu[2]); - SW_SET_REG_BY_FIELD(IP4_RUL_M2, IP4DPORTM, sw->dest_l4port_mask, - hw->msk[2]); - } - else if (FAL_ACL_FIELD_LE == sw->dest_l4port_op) - { - SW_SET_REG_BY_FIELD(IP4_RUL_V2, IP4DPORTV, 0, hw->vlu[2]); - SW_SET_REG_BY_FIELD(IP4_RUL_M2, IP4DPORTM, sw->dest_l4port_val, - hw->msk[2]); - } - else - { - SW_SET_REG_BY_FIELD(IP4_RUL_V2, IP4DPORTV, sw->dest_l4port_val, - hw->vlu[2]); - SW_SET_REG_BY_FIELD(IP4_RUL_M2, IP4DPORTM, 0xffff, hw->msk[2]); - } - } - - return SW_OK; -} - -static sw_error_t -_garuda_acl_rule_ip6r1_parse(fal_acl_rule_t * sw, fal_pbmp_t bind_pts, - garuda_acl_hw_rule_t * hw, a_bool_t * b_care, - a_uint32_t * len) -{ - a_uint32_t i; - - *b_care = A_FALSE; - *len = 0; - - aos_mem_zero(&(hw->vlu[0]), sizeof (hw->vlu)); - aos_mem_zero(&(hw->msk[0]), sizeof (hw->msk)); - aos_mem_zero(&(hw->typ), sizeof (hw->typ)); - - SW_SET_REG_BY_FIELD(IP6_RUL1_V4, IP6_RUL1_INPT, bind_pts, hw->vlu[4]); - SW_SET_REG_BY_FIELD(RUL_TYPE, TYP, GARUDA_IP6R1_FILTER, hw->typ); - - if (FAL_FIELD_FLG_TST(sw->field_flg, FAL_ACL_FIELD_IP6_DIP)) - { - for (i = 0; i < 4; i++) - { - if (0x0 != sw->dest_ip6_mask.ul[i]) - { - *b_care = A_TRUE; - *len = 54; - } - - sw->dest_ip6_val.ul[3 - i] &= sw->dest_ip6_mask.ul[3 - i]; - hw->vlu[i] = sw->dest_ip6_val.ul[3 - i]; - hw->msk[i] = sw->dest_ip6_mask.ul[3 - i]; - } - } - - return SW_OK; -} - -static sw_error_t -_garuda_acl_rule_ip6r2_parse(fal_acl_rule_t * sw, fal_pbmp_t bind_pts, - garuda_acl_hw_rule_t * hw, a_bool_t * b_care, - a_uint32_t * len) -{ - a_uint32_t i; - - *b_care = A_FALSE; - *len = 0; - - aos_mem_zero(&(hw->vlu[0]), sizeof (hw->vlu)); - aos_mem_zero(&(hw->msk[0]), sizeof (hw->msk)); - aos_mem_zero(&(hw->typ), sizeof (hw->typ)); - - SW_SET_REG_BY_FIELD(IP6_RUL2_V4, IP6_RUL2_INPT, bind_pts, hw->vlu[4]); - SW_SET_REG_BY_FIELD(RUL_TYPE, TYP, GARUDA_IP6R2_FILTER, hw->typ); - - if (FAL_FIELD_FLG_TST(sw->field_flg, FAL_ACL_FIELD_IP6_SIP)) - { - for (i = 0; i < 4; i++) - { - if (0x0 != sw->src_ip6_mask.ul[i]) - { - *b_care = A_TRUE; - *len = 38; - } - - sw->src_ip6_val.ul[3 - i] &= sw->src_ip6_mask.ul[3 - i]; - hw->vlu[i] = sw->src_ip6_val.ul[3 - i]; - hw->msk[i] = sw->src_ip6_mask.ul[3 - i]; - } - } - - return SW_OK; -} - -static sw_error_t -_garuda_acl_rule_ip6r3_parse(fal_acl_rule_t * sw, fal_pbmp_t bind_pts, - garuda_acl_hw_rule_t * hw, a_bool_t * b_care, - a_uint32_t * len) -{ - *b_care = A_FALSE; - *len = 0; - - aos_mem_zero(&(hw->vlu[0]), sizeof (hw->vlu)); - aos_mem_zero(&(hw->msk[0]), sizeof (hw->msk)); - aos_mem_zero(&(hw->typ), sizeof (hw->typ)); - - SW_SET_REG_BY_FIELD(IP6_RUL3_V4, IP6_RUL3_INPT, bind_pts, hw->vlu[4]); - SW_SET_REG_BY_FIELD(RUL_TYPE, TYP, GARUDA_IP6R3_FILTER, hw->typ); - - if (FAL_FIELD_FLG_TST(sw->field_flg, FAL_ACL_FIELD_IP_DSCP)) - { - if (0x0 != sw->ip_dscp_mask) - { - *b_care = A_TRUE; - *len = 38; - } - - sw->ip_dscp_val &= sw->ip_dscp_mask; - SW_SET_REG_BY_FIELD(IP6_RUL3_V0, IP6DSCPV, sw->ip_dscp_val, hw->vlu[0]); - SW_SET_REG_BY_FIELD(IP6_RUL3_M0, IP6DSCPM, sw->ip_dscp_mask, - hw->msk[0]); - } - - if (FAL_FIELD_FLG_TST(sw->field_flg, FAL_ACL_FIELD_IP6_LABEL)) - { - if (0x0 != sw->ip6_lable_mask) - { - *b_care = A_TRUE; - *len = 18; - } - - sw->ip6_lable_val &= sw->ip6_lable_mask; - SW_SET_REG_BY_FIELD(IP6_RUL3_V1, IP6LABEL1V, sw->ip6_lable_val, - hw->vlu[1]); - SW_SET_REG_BY_FIELD(IP6_RUL3_M1, IP6LABEL1M, sw->ip6_lable_mask, - hw->msk[1]); - - SW_SET_REG_BY_FIELD(IP6_RUL3_V2, IP6LABEL2V, (sw->ip6_lable_val >> 16), - hw->vlu[2]); - SW_SET_REG_BY_FIELD(IP6_RUL3_M2, IP6LABEL2M, (sw->ip6_lable_mask >> 16), - hw->msk[2]); - } - - if (FAL_FIELD_FLG_TST(sw->field_flg, FAL_ACL_FIELD_IP_PROTO)) - { - if (0x0 != sw->ip_proto_mask) - { - *b_care = A_TRUE; - *len = 21; - } - - sw->ip_proto_val &= sw->ip_proto_mask; - SW_SET_REG_BY_FIELD(IP6_RUL3_V0, IP6PROTV, sw->ip_proto_val, - hw->vlu[0]); - SW_SET_REG_BY_FIELD(IP6_RUL3_M0, IP6PROTM, sw->ip_proto_mask, - hw->msk[0]); - } - - SW_SET_REG_BY_FIELD(IP6_RUL3_M3, IP6SPORTM_EN, 1, hw->msk[3]); - if (FAL_FIELD_FLG_TST(sw->field_flg, FAL_ACL_FIELD_L4_SPORT)) - { - if ((FAL_ACL_FIELD_MASK != sw->src_l4port_op) - && (FAL_ACL_FIELD_RANGE != sw->src_l4port_op) - && (FAL_ACL_FIELD_LE != sw->src_l4port_op) - && (FAL_ACL_FIELD_GE != sw->src_l4port_op)) - { - return SW_NOT_SUPPORTED; - } - - if (A_TRUE == - _garuda_acl_field_care(sw->src_l4port_op, sw->src_l4port_val, - sw->src_l4port_mask, 0xffff)) - { - *b_care = A_TRUE; - *len = 56; - } - - SW_SET_REG_BY_FIELD(IP6_RUL3_M3, IP6SPORTM_EN, 0, hw->msk[3]); - if (FAL_ACL_FIELD_MASK == sw->src_l4port_op) - { - sw->src_l4port_val &= sw->src_l4port_mask; - SW_SET_REG_BY_FIELD(IP6_RUL3_V1, IP6SPORTV, sw->src_l4port_val, - hw->vlu[1]); - SW_SET_REG_BY_FIELD(IP6_RUL3_M1, IP6SPORTM, sw->src_l4port_mask, - hw->msk[1]); - SW_SET_REG_BY_FIELD(IP6_RUL3_M3, IP6SPORTM_EN, 1, hw->msk[3]); - } - else if (FAL_ACL_FIELD_RANGE == sw->src_l4port_op) - { - SW_SET_REG_BY_FIELD(IP6_RUL3_V1, IP6SPORTV, sw->src_l4port_val, - hw->vlu[1]); - SW_SET_REG_BY_FIELD(IP6_RUL3_M1, IP6SPORTM, sw->src_l4port_mask, - hw->msk[1]); - } - else if (FAL_ACL_FIELD_LE == sw->src_l4port_op) - { - SW_SET_REG_BY_FIELD(IP6_RUL3_V1, IP6SPORTV, 0, hw->vlu[1]); - SW_SET_REG_BY_FIELD(IP6_RUL3_M1, IP6SPORTM, sw->src_l4port_val, - hw->msk[1]); - } - else - { - SW_SET_REG_BY_FIELD(IP6_RUL3_V1, IP6SPORTV, sw->src_l4port_val, - hw->vlu[1]); - SW_SET_REG_BY_FIELD(IP6_RUL3_M1, IP6SPORTM, 0xffff, hw->msk[1]); - } - } - - SW_SET_REG_BY_FIELD(IP6_RUL3_M3, IP6DPORTM_EN, 1, hw->msk[3]); - if (FAL_FIELD_FLG_TST(sw->field_flg, FAL_ACL_FIELD_L4_DPORT)) - { - if ((FAL_ACL_FIELD_MASK != sw->dest_l4port_op) - && (FAL_ACL_FIELD_RANGE != sw->dest_l4port_op) - && (FAL_ACL_FIELD_LE != sw->dest_l4port_op) - && (FAL_ACL_FIELD_GE != sw->dest_l4port_op)) - { - return SW_NOT_SUPPORTED; - } - - if (A_TRUE == - _garuda_acl_field_care(sw->dest_l4port_op, sw->dest_l4port_val, - sw->dest_l4port_mask, 0xffff)) - { - *b_care = A_TRUE; - *len = 58; - } - - SW_SET_REG_BY_FIELD(IP6_RUL3_M3, IP6DPORTM_EN, 0, hw->msk[3]); - if (FAL_ACL_FIELD_MASK == sw->dest_l4port_op) - { - sw->dest_l4port_val &= sw->dest_l4port_mask; - SW_SET_REG_BY_FIELD(IP6_RUL3_V0, IP6DPORTV, sw->dest_l4port_val, - hw->vlu[0]); - SW_SET_REG_BY_FIELD(IP6_RUL3_M0, IP6DPORTM, sw->dest_l4port_mask, - hw->msk[0]); - SW_SET_REG_BY_FIELD(IP6_RUL3_M3, IP6DPORTM_EN, 1, hw->msk[3]); - } - else if (FAL_ACL_FIELD_RANGE == sw->dest_l4port_op) - { - SW_SET_REG_BY_FIELD(IP6_RUL3_V0, IP6DPORTV, sw->dest_l4port_val, - hw->vlu[0]); - SW_SET_REG_BY_FIELD(IP6_RUL3_M0, IP6DPORTM, sw->dest_l4port_mask, - hw->msk[0]); - } - else if (FAL_ACL_FIELD_LE == sw->dest_l4port_op) - { - SW_SET_REG_BY_FIELD(IP6_RUL3_V0, IP6DPORTV, 0, hw->vlu[0]); - SW_SET_REG_BY_FIELD(IP6_RUL3_M0, IP6DPORTM, sw->dest_l4port_val, - hw->msk[0]); - } - else - { - SW_SET_REG_BY_FIELD(IP6_RUL3_V0, IP6DPORTV, sw->dest_l4port_val, - hw->vlu[0]); - SW_SET_REG_BY_FIELD(IP6_RUL3_M0, IP6DPORTM, 0xffff, hw->msk[0]); - } - } - - return SW_OK; -} - -static sw_error_t -_garuda_acl_action_parse(a_uint32_t dev_id, const fal_acl_rule_t * sw, - garuda_acl_hw_rule_t * hw) -{ - hw->act = 0; - if ((FAL_ACTION_FLG_TST(sw->action_flg, FAL_ACL_ACTION_MODIFY_VLAN)) - && (FAL_ACTION_FLG_TST(sw->action_flg, FAL_ACL_ACTION_NEST_VLAN))) - { - return SW_NOT_SUPPORTED; - } - - /* FAL_ACL_ACTION_PERMIT need't process */ - - /* we should ignore any other action flags when DENY bit is settd. */ - if (FAL_ACTION_FLG_TST(sw->action_flg, FAL_ACL_ACTION_DENY)) - { - SW_SET_REG_BY_FIELD(ACL_RSLT, DES_PORT_EN, 1, hw->act); - SW_SET_REG_BY_FIELD(ACL_RSLT, PORT_MEM, 0, hw->act); - return SW_OK; - } - - if (FAL_ACTION_FLG_TST(sw->action_flg, FAL_ACL_ACTION_RDTCPU)) - { - SW_SET_REG_BY_FIELD(ACL_RSLT, RDTCPU, 1, hw->act); - } - - if (FAL_ACTION_FLG_TST(sw->action_flg, FAL_ACL_ACTION_CPYCPU)) - { - SW_SET_REG_BY_FIELD(ACL_RSLT, CPYCPU, 1, hw->act); - } - - if (FAL_ACTION_FLG_TST(sw->action_flg, FAL_ACL_ACTION_MIRROR)) - { - SW_SET_REG_BY_FIELD(ACL_RSLT, MIRR_EN, 1, hw->act); - } - - if (FAL_ACTION_FLG_TST(sw->action_flg, FAL_ACL_ACTION_REDPT)) - { - SW_SET_REG_BY_FIELD(ACL_RSLT, DES_PORT_EN, 1, hw->act); - SW_SET_REG_BY_FIELD(ACL_RSLT, PORT_MEM, sw->ports, hw->act); - } - - if (FAL_ACTION_FLG_TST(sw->action_flg, FAL_ACL_ACTION_REMARK_UP)) - { - SW_SET_REG_BY_FIELD(ACL_RSLT, REMARK_DOT1P, 1, hw->act); - SW_SET_REG_BY_FIELD(ACL_RSLT, DOT1P, sw->up, hw->act); - } - - if (FAL_ACTION_FLG_TST(sw->action_flg, FAL_ACL_ACTION_REMARK_QUEUE)) - { - SW_SET_REG_BY_FIELD(ACL_RSLT, REMARK_PRI_QU, 1, hw->act); - SW_SET_REG_BY_FIELD(ACL_RSLT, PRI_QU, sw->queue, hw->act); - } - - if ((FAL_ACTION_FLG_TST(sw->action_flg, FAL_ACL_ACTION_MODIFY_VLAN)) - || (FAL_ACTION_FLG_TST(sw->action_flg, FAL_ACL_ACTION_NEST_VLAN))) - { - - SW_SET_REG_BY_FIELD(ACL_RSLT, CHG_VID_EN, 1, hw->act); - SW_SET_REG_BY_FIELD(ACL_RSLT, VID, sw->vid, hw->act); - SW_SET_REG_BY_FIELD(ACL_RSLT, STAG_CHG_EN, 1, hw->act); - if (FAL_ACTION_FLG_TST(sw->action_flg, FAL_ACL_ACTION_MODIFY_VLAN)) - { - SW_SET_REG_BY_FIELD(ACL_RSLT, STAG_CHG_EN, 0, hw->act); - - if (!FAL_ACTION_FLG_TST(sw->action_flg, FAL_ACL_ACTION_REDPT)) - { - SW_SET_REG_BY_FIELD(ACL_RSLT, VID_MEM_EN, 1, hw->act); - SW_SET_REG_BY_FIELD(ACL_RSLT, PORT_MEM, sw->ports, hw->act); - } - } - } - - return SW_OK; -} - -static sw_error_t -_garuda_acl_rule_mac_reparse(fal_acl_rule_t * sw, - const garuda_acl_hw_rule_t * hw) -{ - a_uint32_t mask_en; - - /* destnation mac address */ - SW_GET_FIELD_BY_REG(MAC_RUL_V0, DAV_BYTE2, sw->dest_mac_val.uc[2], - hw->vlu[0]); - SW_GET_FIELD_BY_REG(MAC_RUL_V0, DAV_BYTE3, sw->dest_mac_val.uc[3], - hw->vlu[0]); - SW_GET_FIELD_BY_REG(MAC_RUL_V0, DAV_BYTE4, sw->dest_mac_val.uc[4], - hw->vlu[0]); - SW_GET_FIELD_BY_REG(MAC_RUL_V0, DAV_BYTE5, sw->dest_mac_val.uc[5], - hw->vlu[0]); - SW_GET_FIELD_BY_REG(MAC_RUL_V1, DAV_BYTE0, sw->dest_mac_val.uc[0], - hw->vlu[1]); - SW_GET_FIELD_BY_REG(MAC_RUL_V1, DAV_BYTE1, sw->dest_mac_val.uc[1], - hw->vlu[1]); - - SW_GET_FIELD_BY_REG(MAC_RUL_M0, DAM_BYTE2, sw->dest_mac_mask.uc[2], - hw->msk[0]); - SW_GET_FIELD_BY_REG(MAC_RUL_M0, DAM_BYTE3, sw->dest_mac_mask.uc[3], - hw->msk[0]); - SW_GET_FIELD_BY_REG(MAC_RUL_M0, DAM_BYTE4, sw->dest_mac_mask.uc[4], - hw->msk[0]); - SW_GET_FIELD_BY_REG(MAC_RUL_M0, DAM_BYTE5, sw->dest_mac_mask.uc[5], - hw->msk[0]); - SW_GET_FIELD_BY_REG(MAC_RUL_M1, DAM_BYTE0, sw->dest_mac_mask.uc[0], - hw->msk[1]); - SW_GET_FIELD_BY_REG(MAC_RUL_M1, DAM_BYTE1, sw->dest_mac_mask.uc[1], - hw->msk[1]); - if (A_FALSE == _garuda_acl_zero_addr(sw->dest_mac_mask)) - { - FAL_FIELD_FLG_SET(sw->field_flg, FAL_ACL_FIELD_MAC_DA); - } - - /* source mac address */ - SW_GET_FIELD_BY_REG(MAC_RUL_V2, SAV_BYTE0, sw->src_mac_val.uc[0], - hw->vlu[2]); - SW_GET_FIELD_BY_REG(MAC_RUL_V2, SAV_BYTE1, sw->src_mac_val.uc[1], - hw->vlu[2]); - SW_GET_FIELD_BY_REG(MAC_RUL_V2, SAV_BYTE2, sw->src_mac_val.uc[2], - hw->vlu[2]); - SW_GET_FIELD_BY_REG(MAC_RUL_V2, SAV_BYTE3, sw->src_mac_val.uc[3], - hw->vlu[2]); - SW_GET_FIELD_BY_REG(MAC_RUL_V1, SAV_BYTE4, sw->src_mac_val.uc[4], - hw->vlu[1]); - SW_GET_FIELD_BY_REG(MAC_RUL_V1, SAV_BYTE5, sw->src_mac_val.uc[5], - hw->vlu[1]); - - SW_GET_FIELD_BY_REG(MAC_RUL_M2, SAM_BYTE0, sw->src_mac_mask.uc[0], - hw->msk[2]); - SW_GET_FIELD_BY_REG(MAC_RUL_M2, SAM_BYTE1, sw->src_mac_mask.uc[1], - hw->msk[2]); - SW_GET_FIELD_BY_REG(MAC_RUL_M2, SAM_BYTE2, sw->src_mac_mask.uc[2], - hw->msk[2]); - SW_GET_FIELD_BY_REG(MAC_RUL_M2, SAM_BYTE3, sw->src_mac_mask.uc[3], - hw->msk[2]); - SW_GET_FIELD_BY_REG(MAC_RUL_M1, SAM_BYTE4, sw->src_mac_mask.uc[4], - hw->msk[1]); - SW_GET_FIELD_BY_REG(MAC_RUL_M1, SAM_BYTE5, sw->src_mac_mask.uc[5], - hw->msk[1]); - if (A_FALSE == _garuda_acl_zero_addr(sw->src_mac_mask)) - { - FAL_FIELD_FLG_SET(sw->field_flg, FAL_ACL_FIELD_MAC_SA); - } - - /* ethernet type */ - SW_GET_FIELD_BY_REG(MAC_RUL_V3, ETHTYPV, sw->ethtype_val, hw->vlu[3]); - SW_GET_FIELD_BY_REG(MAC_RUL_M3, ETHTYPM, sw->ethtype_mask, hw->msk[3]); - if (0x0 != sw->ethtype_mask) - { - FAL_FIELD_FLG_SET(sw->field_flg, FAL_ACL_FIELD_MAC_ETHTYPE); - } - - /* packet tagged */ - SW_GET_FIELD_BY_REG(MAC_RUL_V4, TAGGEDV, sw->tagged_val, hw->vlu[4]); - SW_GET_FIELD_BY_REG(MAC_RUL_V4, TAGGEDM, sw->tagged_mask, hw->vlu[4]); - if (0x0 != sw->tagged_mask) - { - FAL_FIELD_FLG_SET(sw->field_flg, FAL_ACL_FIELD_MAC_TAGGED); - } - - /* vlan priority */ - SW_GET_FIELD_BY_REG(MAC_RUL_V3, VLANPRIV, sw->up_val, hw->vlu[3]); - SW_GET_FIELD_BY_REG(MAC_RUL_M3, VLANPRIM, sw->up_mask, hw->msk[3]); - if (0x0 != sw->up_mask) - { - FAL_FIELD_FLG_SET(sw->field_flg, FAL_ACL_FIELD_MAC_UP); - } - - /* vlanid */ - SW_GET_FIELD_BY_REG(MAC_RUL_V3, VLANIDV, sw->vid_val, hw->vlu[3]); - SW_GET_FIELD_BY_REG(MAC_RUL_M3, VLANIDM, sw->vid_mask, hw->msk[3]); - SW_GET_FIELD_BY_REG(MAC_RUL_M3, VIDMSK, mask_en, hw->msk[3]); - if (mask_en) - { - sw->vid_op = FAL_ACL_FIELD_MASK; - } - else - { - sw->vid_op = FAL_ACL_FIELD_RANGE; - } - - if (A_TRUE == - _garuda_acl_field_care(sw->vid_op, (a_uint32_t) sw->vid_val, - (a_uint32_t) sw->vid_mask, 0xfff)) - { - FAL_FIELD_FLG_SET(sw->field_flg, FAL_ACL_FIELD_MAC_VID); - } - - return SW_OK; -} - -static sw_error_t -_garuda_acl_rule_ip4_reparse(fal_acl_rule_t * sw, - const garuda_acl_hw_rule_t * hw) -{ - a_uint32_t mask_en; - - sw->dest_ip4_val = hw->vlu[0]; - sw->dest_ip4_mask = hw->msk[0]; - if (0x0 != sw->dest_ip4_mask) - { - FAL_FIELD_FLG_SET(sw->field_flg, FAL_ACL_FIELD_IP4_DIP); - } - - sw->src_ip4_val = hw->vlu[1]; - sw->src_ip4_mask = hw->msk[1]; - if (0x0 != sw->src_ip4_mask) - { - FAL_FIELD_FLG_SET(sw->field_flg, FAL_ACL_FIELD_IP4_SIP); - } - - SW_GET_FIELD_BY_REG(IP4_RUL_V2, IP4PROTV, sw->ip_proto_val, hw->vlu[2]); - SW_GET_FIELD_BY_REG(IP4_RUL_M2, IP4PROTM, sw->ip_proto_mask, hw->msk[2]); - if (0x0 != sw->ip_proto_mask) - { - FAL_FIELD_FLG_SET(sw->field_flg, FAL_ACL_FIELD_IP_PROTO); - } - - SW_GET_FIELD_BY_REG(IP4_RUL_V2, IP4DSCPV, sw->ip_dscp_val, hw->vlu[2]); - SW_GET_FIELD_BY_REG(IP4_RUL_M2, IP4DSCPM, sw->ip_dscp_mask, hw->msk[2]); - if (0x0 != sw->ip_dscp_mask) - { - FAL_FIELD_FLG_SET(sw->field_flg, FAL_ACL_FIELD_IP_DSCP); - } - - SW_GET_FIELD_BY_REG(IP4_RUL_V2, IP4DPORTV, sw->dest_l4port_val, hw->vlu[2]); - SW_GET_FIELD_BY_REG(IP4_RUL_M2, IP4DPORTM, sw->dest_l4port_mask, - hw->msk[2]); - SW_GET_FIELD_BY_REG(IP4_RUL_M3, IP4DPORTM_EN, mask_en, hw->msk[3]); - if (mask_en) - { - sw->dest_l4port_op = FAL_ACL_FIELD_MASK; - } - else - { - sw->dest_l4port_op = FAL_ACL_FIELD_RANGE; - } - - if (A_TRUE == - _garuda_acl_field_care(sw->dest_l4port_op, - (a_uint32_t) sw->dest_l4port_val, - (a_uint32_t) sw->dest_l4port_mask, 0xffff)) - { - FAL_FIELD_FLG_SET(sw->field_flg, FAL_ACL_FIELD_L4_DPORT); - } - - SW_GET_FIELD_BY_REG(IP4_RUL_V3, IP4SPORTV, sw->src_l4port_val, hw->vlu[3]); - SW_GET_FIELD_BY_REG(IP4_RUL_M3, IP4SPORTM, sw->src_l4port_mask, hw->msk[3]); - SW_GET_FIELD_BY_REG(IP4_RUL_M3, IP4SPORTM_EN, mask_en, hw->msk[3]); - if (mask_en) - { - sw->src_l4port_op = FAL_ACL_FIELD_MASK; - } - else - { - sw->src_l4port_op = FAL_ACL_FIELD_RANGE; - } - - if (A_TRUE == - _garuda_acl_field_care(sw->src_l4port_op, - (a_uint32_t) sw->src_l4port_val, - (a_uint32_t) sw->src_l4port_mask, 0xffff)) - { - FAL_FIELD_FLG_SET(sw->field_flg, FAL_ACL_FIELD_L4_SPORT); - } - - return SW_OK; -} - -static sw_error_t -_garuda_acl_rule_ip6r1_reparse(fal_acl_rule_t * sw, - const garuda_acl_hw_rule_t * hw) -{ - a_uint32_t i; - - for (i = 0; i < 4; i++) - { - sw->dest_ip6_val.ul[i] = hw->vlu[3 - i]; - sw->dest_ip6_mask.ul[i] = hw->msk[3 - i]; - if (0x0 != sw->dest_ip6_mask.ul[i]) - { - FAL_FIELD_FLG_SET(sw->field_flg, FAL_ACL_FIELD_IP6_DIP); - } - } - return SW_OK; -} - -static sw_error_t -_garuda_acl_rule_ip6r2_reparse(fal_acl_rule_t * sw, - const garuda_acl_hw_rule_t * hw) -{ - a_uint32_t i; - - for (i = 0; i < 4; i++) - { - sw->src_ip6_val.ul[i] = hw->vlu[3 - i]; - sw->src_ip6_mask.ul[i] = hw->msk[3 - i]; - if (0x0 != sw->src_ip6_mask.ul[i]) - { - FAL_FIELD_FLG_SET(sw->field_flg, FAL_ACL_FIELD_IP6_SIP); - } - } - return SW_OK; -} - -static sw_error_t -_garuda_acl_rule_ip6r3_reparse(fal_acl_rule_t * sw, - const garuda_acl_hw_rule_t * hw) -{ - a_uint32_t mask_en; - a_uint32_t tmp; - - SW_GET_FIELD_BY_REG(IP6_RUL3_V0, IP6PROTV, sw->ip_proto_val, hw->vlu[0]); - SW_GET_FIELD_BY_REG(IP6_RUL3_M0, IP6PROTM, sw->ip_proto_mask, hw->msk[0]); - if (0x0 != sw->ip_proto_mask) - { - FAL_FIELD_FLG_SET(sw->field_flg, FAL_ACL_FIELD_IP_PROTO); - } - - SW_GET_FIELD_BY_REG(IP6_RUL3_V0, IP6DSCPV, sw->ip_dscp_val, hw->vlu[0]); - SW_GET_FIELD_BY_REG(IP6_RUL3_M0, IP6DSCPM, sw->ip_dscp_mask, hw->msk[0]); - if (0x0 != sw->ip_dscp_mask) - { - FAL_FIELD_FLG_SET(sw->field_flg, FAL_ACL_FIELD_IP_DSCP); - } - - SW_GET_FIELD_BY_REG(IP6_RUL3_V0, IP6DPORTV, sw->dest_l4port_val, - hw->vlu[0]); - SW_GET_FIELD_BY_REG(IP6_RUL3_M0, IP6DPORTM, sw->dest_l4port_mask, - hw->msk[0]); - SW_GET_FIELD_BY_REG(IP6_RUL3_M3, IP6DPORTM_EN, mask_en, hw->msk[3]); - if (mask_en) - { - sw->dest_l4port_op = FAL_ACL_FIELD_MASK; - } - else - { - sw->dest_l4port_op = FAL_ACL_FIELD_RANGE; - } - - if (A_TRUE == - _garuda_acl_field_care(sw->dest_l4port_op, - (a_uint32_t) sw->dest_l4port_val, - (a_uint32_t) sw->dest_l4port_mask, 0xffff)) - { - FAL_FIELD_FLG_SET(sw->field_flg, FAL_ACL_FIELD_L4_DPORT); - } - - SW_GET_FIELD_BY_REG(IP6_RUL3_V1, IP6SPORTV, sw->src_l4port_val, hw->vlu[1]); - SW_GET_FIELD_BY_REG(IP6_RUL3_M1, IP6SPORTM, sw->src_l4port_mask, - hw->msk[1]); - SW_GET_FIELD_BY_REG(IP6_RUL3_M3, IP6SPORTM_EN, mask_en, hw->msk[3]); - if (mask_en) - { - sw->src_l4port_op = FAL_ACL_FIELD_MASK; - } - else - { - sw->src_l4port_op = FAL_ACL_FIELD_RANGE; - } - - if (A_TRUE == - _garuda_acl_field_care(sw->src_l4port_op, - (a_uint32_t) sw->src_l4port_val, - (a_uint32_t) sw->src_l4port_mask, 0xffff)) - { - FAL_FIELD_FLG_SET(sw->field_flg, FAL_ACL_FIELD_L4_SPORT); - } - - SW_GET_FIELD_BY_REG(IP6_RUL3_V1, IP6LABEL1V, sw->ip6_lable_val, hw->vlu[1]); - SW_GET_FIELD_BY_REG(IP6_RUL3_M1, IP6LABEL1M, sw->ip6_lable_mask, - hw->msk[1]); - - SW_GET_FIELD_BY_REG(IP6_RUL3_V2, IP6LABEL2V, tmp, hw->vlu[2]); - sw->ip6_lable_val |= (tmp << 16); - SW_GET_FIELD_BY_REG(IP6_RUL3_M2, IP6LABEL2M, tmp, hw->msk[2]); - sw->ip6_lable_mask |= (tmp << 16); - - if (0x0 != sw->ip6_lable_mask) - { - FAL_FIELD_FLG_SET(sw->field_flg, FAL_ACL_FIELD_IP6_LABEL); - } - - return SW_OK; -} - -static sw_error_t -_garuda_acl_rule_action_reparse(fal_acl_rule_t * sw, - const garuda_acl_hw_rule_t * hw) -{ - a_uint32_t data; - - sw->action_flg = 0; - SW_GET_FIELD_BY_REG(ACL_RSLT, DES_PORT_EN, data, (hw->act)); - if (1 == data) - { - SW_GET_FIELD_BY_REG(ACL_RSLT, PORT_MEM, data, (hw->act)); - sw->ports = data; - - FAL_ACTION_FLG_SET(sw->action_flg, FAL_ACL_ACTION_REDPT); - } - - SW_GET_FIELD_BY_REG(ACL_RSLT, RDTCPU, data, (hw->act)); - if (1 == data) - { - FAL_ACTION_FLG_SET(sw->action_flg, FAL_ACL_ACTION_RDTCPU); - } - - SW_GET_FIELD_BY_REG(ACL_RSLT, CPYCPU, data, (hw->act)); - if (1 == data) - { - FAL_ACTION_FLG_SET(sw->action_flg, FAL_ACL_ACTION_CPYCPU); - } - - SW_GET_FIELD_BY_REG(ACL_RSLT, MIRR_EN, data, (hw->act)); - if (1 == data) - { - FAL_ACTION_FLG_SET(sw->action_flg, FAL_ACL_ACTION_MIRROR); - } - - SW_GET_FIELD_BY_REG(ACL_RSLT, REMARK_DOT1P, data, (hw->act)); - if (1 == data) - { - SW_GET_FIELD_BY_REG(ACL_RSLT, DOT1P, data, (hw->act)); - sw->up = data & 0x7; - - FAL_ACTION_FLG_SET(sw->action_flg, FAL_ACL_ACTION_REMARK_UP); - } - - SW_GET_FIELD_BY_REG(ACL_RSLT, REMARK_PRI_QU, data, (hw->act)); - if (1 == data) - { - SW_GET_FIELD_BY_REG(ACL_RSLT, PRI_QU, data, (hw->act)); - sw->queue = data & 0x3; - - FAL_ACTION_FLG_SET(sw->action_flg, FAL_ACL_ACTION_REMARK_QUEUE); - } - - SW_GET_FIELD_BY_REG(ACL_RSLT, CHG_VID_EN, data, (hw->act)); - if (1 == data) - { - SW_GET_FIELD_BY_REG(ACL_RSLT, STAG_CHG_EN, data, (hw->act)); - if (1 == data) - { - FAL_ACTION_FLG_SET(sw->action_flg, FAL_ACL_ACTION_NEST_VLAN); - } - else - { - FAL_ACTION_FLG_SET(sw->action_flg, FAL_ACL_ACTION_MODIFY_VLAN); - SW_GET_FIELD_BY_REG(ACL_RSLT, PORT_MEM, data, (hw->act)); - sw->ports = data; - } - } - - SW_GET_FIELD_BY_REG(ACL_RSLT, VID, data, (hw->act)); - sw->vid = data & 0xfff; - - return SW_OK; -} - -static sw_error_t -_garuda_acl_filter_alloc(a_uint32_t dev_id, a_uint32_t * idx) -{ - a_uint32_t i; - - for (i = 0; i < GARUDA_MAX_RULE; i++) - { - if (0 == (filter_snap[dev_id] & (0x1UL << i))) - { - filter_snap[dev_id] |= (0x1UL << i); - *idx = i; - return SW_OK; - } - } - return SW_NO_RESOURCE; -} - -static void -_garuda_acl_filter_free(a_uint32_t dev_id, a_uint32_t idx) -{ - filter_snap[dev_id] &= (~(0x1UL << idx)); -} - -static void -_garuda_acl_filter_snap(a_uint32_t dev_id) -{ - filter_snap[dev_id] = filter[dev_id]; - return; -} - -static void -_garuda_acl_filter_commit(a_uint32_t dev_id) -{ - filter[dev_id] = filter_snap[dev_id]; - return; -} - -static sw_error_t -_garuda_acl_slct_update(garuda_acl_hw_rule_t * hw, a_uint32_t offset, - a_uint32_t flt_idx) -{ - switch (offset) - { - case 0: - SW_SET_REG_BY_FIELD(RUL_SLCT0, ADDR0_EN, 1, hw->slct[0]); - SW_SET_REG_BY_FIELD(RUL_SLCT1, ADDR0, flt_idx, hw->slct[1]); - break; - - case 1: - SW_SET_REG_BY_FIELD(RUL_SLCT0, ADDR1_EN, 1, hw->slct[0]); - SW_SET_REG_BY_FIELD(RUL_SLCT2, ADDR1, flt_idx, hw->slct[2]); - break; - - case 2: - SW_SET_REG_BY_FIELD(RUL_SLCT0, ADDR2_EN, 1, hw->slct[0]); - SW_SET_REG_BY_FIELD(RUL_SLCT3, ADDR2, flt_idx, hw->slct[3]); - break; - - case 3: - SW_SET_REG_BY_FIELD(RUL_SLCT0, ADDR3_EN, 1, hw->slct[0]); - SW_SET_REG_BY_FIELD(RUL_SLCT4, ADDR3, flt_idx, hw->slct[4]); - break; - - default: - return SW_FAIL; - } - return SW_OK; -} - -static sw_error_t -_garuda_acl_filter_write(a_uint32_t dev_id, const garuda_acl_hw_rule_t * rule, - a_uint32_t flt_idx) -{ -#ifdef GARUDA_SW_ENTRY - char *memaddr; - a_uint32_t i; - - memaddr = flt_vlu_mem + (flt_idx << 5); - aos_mem_copy(memaddr, (char *) &(rule->vlu[0]), 20); - - memaddr = flt_msk_mem + (flt_idx << 5); - aos_mem_copy(memaddr, (char *) &(rule->msk[0]), 20); - - memaddr = flt_typ_mem + (flt_idx << 5); - aos_mem_copy(memaddr, (char *) &(rule->typ), 4); - -#else - sw_error_t rv; - a_uint32_t i, base, addr; - - /* set filter value */ - base = GARUDA_RULE_VLU_ADDR + (flt_idx << 5); - for (i = 0; i < 5; i++) - { - addr = base + (i << 2); - HSL_REG_ENTRY_GEN_SET(rv, dev_id, addr, sizeof (a_uint32_t), - (a_uint8_t *) (&(rule->vlu[i])), - sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - } - - /* set filter mask */ - base = GARUDA_RULE_MSK_ADDR + (flt_idx << 5); - for (i = 0; i < 5; i++) - { - addr = base + (i << 2); - HSL_REG_ENTRY_GEN_SET(rv, dev_id, addr, sizeof (a_uint32_t), - (a_uint8_t *) (&(rule->msk[i])), - sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - } - - /* set filter type */ - addr = GARUDA_RULE_TYP_ADDR + (flt_idx << 5); - HSL_REG_ENTRY_GEN_SET(rv, dev_id, addr, sizeof (a_uint32_t), - (a_uint8_t *) (&(rule->typ)), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); -#endif - -#ifdef GARUDA_ENTRY_DUMP - aos_printk("\n_garuda_acl_filter_write flt_idx = %d\n", flt_idx); - for (i = 0; i < 5; i++) - { - aos_printk("%08x ", rule->vlu[i]); - } - aos_printk("\n"); - for (i = 0; i < 5; i++) - { - aos_printk("%08x ", rule->msk[i]); - } -#endif - - return SW_OK; -} - -static sw_error_t -_garuda_acl_action_write(a_uint32_t dev_id, const garuda_acl_hw_rule_t * rule, - a_uint32_t act_idx) -{ -#ifdef GARUDA_SW_ENTRY - char *memaddr; - - memaddr = act_mem + (act_idx << 5); - aos_mem_copy(memaddr, (char *) &(rule->act), 4); - -#else - sw_error_t rv; - a_uint32_t addr; - - /* set rule action */ - addr = GARUDA_RULE_ACT_ADDR + (act_idx << 5); - HSL_REG_ENTRY_GEN_SET(rv, dev_id, addr, sizeof (a_uint32_t), - (a_uint8_t *) (&(rule->act)), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); -#endif - -#ifdef GARUDA_ENTRY_DUMP - aos_printk("\n_garuda_acl_action_write act_idx = %d ", act_idx); - aos_printk("%08x ", rule->act); -#endif - - return SW_OK; -} - -static sw_error_t -_garuda_acl_slct_write(a_uint32_t dev_id, const garuda_acl_hw_rule_t * rule, - a_uint32_t slct_idx) -{ -#ifdef GARUDA_SW_ENTRY - char *memaddr; - a_uint32_t i; - - memaddr = slct_mem + (slct_idx << 5); - aos_mem_copy(memaddr, (char *) &(rule->slct[0]), 32); - -#else - sw_error_t rv; - a_uint32_t base, addr; - a_uint32_t i; - - base = GARUDA_RULE_SLCT_ADDR + (slct_idx << 5); - - /* set filter length */ - HSL_REG_ENTRY_GEN_SET(rv, dev_id, (base + 24), sizeof (a_uint32_t), - (a_uint8_t *) (&(rule->slct[6])), - sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - - /* set filter address */ - for (i = 1; i < 5; i++) - { - addr = base + (i << 2); - HSL_REG_ENTRY_GEN_SET(rv, dev_id, addr, sizeof (a_uint32_t), - (a_uint8_t *) (&(rule->slct[i])), - sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - } - - /* set filter enable */ - HSL_REG_ENTRY_GEN_SET(rv, dev_id, base, sizeof (a_uint32_t), - (a_uint8_t *) (&(rule->slct[0])), - sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); -#endif - -#ifdef GARUDA_ENTRY_DUMP - aos_printk("\n_garuda_acl_slct_write slct_idx = %d\n", slct_idx); - for (i = 0; i < 8; i++) - { - aos_printk("%08x ", rule->slct[i]); - } -#endif - - return SW_OK; -} - -static sw_error_t -_garuda_acl_filter_read(a_uint32_t dev_id, garuda_acl_hw_rule_t * rule, - a_uint32_t flt_idx) -{ -#ifdef GARUDA_SW_ENTRY - char *memaddr; - a_uint32_t i; - - memaddr = flt_vlu_mem + (flt_idx << 5); - aos_mem_copy((char *) &(rule->vlu[0]), memaddr, 20); - - memaddr = flt_msk_mem + (flt_idx << 5); - aos_mem_copy((char *) &(rule->msk[0]), memaddr, 20); - - memaddr = flt_typ_mem + (flt_idx << 5); - aos_mem_copy((char *) &(rule->typ), memaddr, 4); - -#else - sw_error_t rv; - a_uint32_t i, base, addr; - - /* get filter value */ - base = GARUDA_RULE_VLU_ADDR + (flt_idx << 5); - for (i = 0; i < 5; i++) - { - addr = base + (i << 2); - HSL_REG_ENTRY_GEN_GET(rv, dev_id, addr, sizeof (a_uint32_t), - (a_uint8_t *) (&(rule->vlu[i])), - sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - } - - /* get filter mask */ - base = GARUDA_RULE_MSK_ADDR + (flt_idx << 5); - for (i = 0; i < 5; i++) - { - addr = base + (i << 2); - HSL_REG_ENTRY_GEN_GET(rv, dev_id, addr, sizeof (a_uint32_t), - (a_uint8_t *) (&(rule->msk[i])), - sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - } - - /* get filter type */ - addr = GARUDA_RULE_TYP_ADDR + (flt_idx << 5); - HSL_REG_ENTRY_GEN_GET(rv, dev_id, addr, sizeof (a_uint32_t), - (a_uint8_t *) (&(rule->typ)), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); -#endif - -#ifdef GARUDA_ENTRY_DUMP - aos_printk("\n_garuda_acl_filter_read flt_idx = %d\n", flt_idx); - for (i = 0; i < 5; i++) - { - aos_printk("%08x ", rule->vlu[i]); - } - aos_printk("\n"); - for (i = 0; i < 5; i++) - { - aos_printk("%08x ", rule->msk[i]); - } -#endif - - return SW_OK; -} - -static sw_error_t -_garuda_acl_action_read(a_uint32_t dev_id, garuda_acl_hw_rule_t * rule, - a_uint32_t act_idx) -{ -#ifdef GARUDA_SW_ENTRY - char *memaddr; - - memaddr = act_mem + (act_idx << 5); - aos_mem_copy((char *) &(rule->act), memaddr, 4); - -#else - sw_error_t rv; - a_uint32_t addr; - - /* get rule action */ - addr = GARUDA_RULE_ACT_ADDR + (act_idx << 5); - HSL_REG_ENTRY_GEN_GET(rv, dev_id, addr, sizeof (a_uint32_t), - (a_uint8_t *) (&(rule->act)), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); -#endif - -#ifdef GARUDA_ENTRY_DUMP - aos_printk("\n_garuda_acl_action_read act_idx = %d ", act_idx); - aos_printk("%08x ", rule->act); -#endif - - return SW_OK; -} - -static sw_error_t -_garuda_acl_slct_read(a_uint32_t dev_id, garuda_acl_hw_rule_t * rule, - a_uint32_t slct_idx) -{ -#ifdef GARUDA_SW_ENTRY - char *memaddr; - a_uint32_t i; - - memaddr = slct_mem + (slct_idx << 5); - aos_mem_copy((char *) &(rule->slct[0]), memaddr, 32); - -#else - sw_error_t rv; - a_uint32_t i, base, addr; - - base = GARUDA_RULE_SLCT_ADDR + (slct_idx << 5); - - /* get filter type */ - HSL_REG_ENTRY_GEN_GET(rv, dev_id, (base + 28), sizeof (a_uint32_t), - (a_uint8_t *) (&(rule->slct[7])), - sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - - /* get filter length */ - HSL_REG_ENTRY_GEN_GET(rv, dev_id, (base + 24), sizeof (a_uint32_t), - (a_uint8_t *) (&(rule->slct[6])), - sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - - /* get filter address and enable */ - for (i = 0; i < 5; i++) - { - addr = base + (i << 2); - HSL_REG_ENTRY_GEN_GET(rv, dev_id, addr, sizeof (a_uint32_t), - (a_uint8_t *) (&(rule->slct[i])), - sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - } -#endif - -#ifdef GARUDA_ENTRY_DUMP - aos_printk("\n_garuda_acl_slct_read slct_idx = %d\n", slct_idx); - for (i = 0; i < 8; i++) - { - aos_printk("%08x ", rule->slct[i]); - } -#endif - - return SW_OK; -} - -static sw_error_t -_garuda_acl_rule_set(a_uint32_t dev_id, a_uint32_t base_addr, - const garuda_acl_hw_rule_t * rule, a_uint32_t rule_nr) -{ - sw_error_t rv; - a_uint32_t ent_idx, tmp_ent_idx; - a_uint32_t i, flt_nr, flt_idx[4]; - a_uint32_t act_idx, slct_idx; - - act_idx = base_addr; - slct_idx = base_addr; - ent_idx = 0; - for (i = 0; i < rule_nr; i++) - { - tmp_ent_idx = ent_idx; - - rv = _garuda_acl_filter_map_get(&rule[ent_idx], flt_idx, &flt_nr); - SW_RTN_ON_ERROR(rv); - - if (!flt_nr) - { - return SW_FAIL; - } - - for (i = 0; i < flt_nr; i++) - { - rv = _garuda_acl_filter_write(dev_id, &(rule[ent_idx]), flt_idx[i]); - ent_idx++; - } - - rv = _garuda_acl_action_write(dev_id, &(rule[tmp_ent_idx]), act_idx); - SW_RTN_ON_ERROR(rv); - - rv = _garuda_acl_slct_write(dev_id, &(rule[tmp_ent_idx]), slct_idx); - SW_RTN_ON_ERROR(rv); - - act_idx++; - slct_idx++; - } - return SW_OK; -} - -static sw_error_t -_garuda_acl_rule_get(a_uint32_t dev_id, garuda_acl_hw_rule_t * rule, - a_uint32_t * ent_idx, a_uint32_t rule_idx) -{ - sw_error_t rv; - a_uint32_t i, tmp_idx, flt_nr, flt_idx[4]; - - tmp_idx = *ent_idx; - - rv = _garuda_acl_slct_read(dev_id, &rule[tmp_idx], rule_idx); - SW_RTN_ON_ERROR(rv); - - rv = _garuda_acl_action_read(dev_id, &rule[tmp_idx], rule_idx); - SW_RTN_ON_ERROR(rv); - - rv = _garuda_acl_filter_map_get(&rule[tmp_idx], flt_idx, &flt_nr); - SW_RTN_ON_ERROR(rv); - - for (i = 0; i < flt_nr; i++) - { - rv = _garuda_acl_filter_read(dev_id, &rule[tmp_idx], flt_idx[i]); - SW_RTN_ON_ERROR(rv); - - tmp_idx++; - } - - *ent_idx = tmp_idx; - return SW_OK; -} - -static sw_error_t -_garuda_acl_rule_sw_to_hw(a_uint32_t dev_id, fal_acl_rule_t * sw, - fal_pbmp_t bind_pts, garuda_acl_hw_rule_t * hw, - a_uint32_t * idx, a_uint32_t * flt_len) -{ - sw_error_t rv; - a_bool_t b_care; - a_bool_t b_valid = A_FALSE; - a_uint32_t tmp_idx; - a_uint32_t len1 = 0, len2 = 0, len3 = 0, maxlen = 0; - - if (FAL_FIELD_FLG_TST(sw->field_flg, FAL_ACL_FIELD_UDF)) - { - return SW_NOT_SUPPORTED; - } - - tmp_idx = *idx; - if (FAL_ACL_RULE_MAC == sw->rule_type) - { - rv = _garuda_acl_rule_mac_parse(sw, bind_pts, &hw[tmp_idx], &b_care, - &len1); - SW_RTN_ON_ERROR(rv); - tmp_idx++; - - if (0 == len1) - { - *flt_len = 14; - } - else - { - *flt_len = len1; - } - } - else if (FAL_ACL_RULE_IP4 == sw->rule_type) - { - rv = _garuda_acl_rule_mac_parse(sw, bind_pts, &hw[tmp_idx], &b_care, - &len1); - SW_RTN_ON_ERROR(rv); - if (A_TRUE == b_care) - { - tmp_idx++; - } - - rv = _garuda_acl_rule_ip4_parse(sw, bind_pts, &hw[tmp_idx], &b_care, - &len1); - SW_RTN_ON_ERROR(rv); - tmp_idx++; - - if (0 == len1) - { - *flt_len = 34; - } - else - { - *flt_len = len1; - } - } - else if (FAL_ACL_RULE_IP6 == sw->rule_type) - { - rv = _garuda_acl_rule_mac_parse(sw, bind_pts, &hw[tmp_idx], &b_care, - &len1); - SW_RTN_ON_ERROR(rv); - if (A_TRUE == b_care) - { - tmp_idx++; - } - - rv = _garuda_acl_rule_ip6r1_parse(sw, bind_pts, &hw[tmp_idx], &b_care, - &len1); - SW_RTN_ON_ERROR(rv); - if (A_TRUE == b_care) - { - tmp_idx++; - b_valid = A_TRUE; - } - - rv = _garuda_acl_rule_ip6r2_parse(sw, bind_pts, &hw[tmp_idx], &b_care, - &len2); - SW_RTN_ON_ERROR(rv); - if (A_TRUE == b_care) - { - tmp_idx++; - b_valid = A_TRUE; - } - - rv = _garuda_acl_rule_ip6r3_parse(sw, bind_pts, &hw[tmp_idx], &b_care, - &len3); - SW_RTN_ON_ERROR(rv); - if ((A_TRUE == b_care) || (A_FALSE == b_valid)) - { - tmp_idx++; - } - - if (len1 >= len2) - { - if (len1 >= len3) - { - maxlen = len1; - } - else - { - maxlen = len3; - } - } - else - { - if (len2 >= len3) - { - maxlen = len2; - } - else - { - maxlen = len3; - } - } - - if (0 == maxlen) - { - *flt_len = 54; - } - else - { - *flt_len = maxlen; - } - } - else - { - return SW_NOT_SUPPORTED; - } - - rv = _garuda_acl_action_parse(dev_id, sw, &(hw_rule_ent[*idx])); - SW_RTN_ON_ERROR(rv); - - *idx = tmp_idx; - return SW_OK; -} - -static sw_error_t -_garuda_acl_rule_hw_to_sw(fal_acl_rule_t * sw, const garuda_acl_hw_rule_t * hw, - a_uint32_t ent_idx, a_uint32_t ent_nr) -{ - sw_error_t rv; - a_uint32_t i, flt_typ; - a_bool_t b_ip4 = A_FALSE, b_ip6 = A_FALSE; - - rv = _garuda_acl_rule_action_reparse(sw, &hw[ent_idx]); - SW_RTN_ON_ERROR(rv); - - sw->rule_type = FAL_ACL_RULE_MAC; - for (i = 0; i < ent_nr; i++) - { - SW_GET_FIELD_BY_REG(RUL_TYPE, TYP, flt_typ, hw[ent_idx + i].typ); - - if (GARUDA_MAC_FILTER == flt_typ) - { - rv = _garuda_acl_rule_mac_reparse(sw, &hw[ent_idx + i]); - SW_RTN_ON_ERROR(rv); - } - else if (GARUDA_IP4_FILTER == flt_typ) - { - rv = _garuda_acl_rule_ip4_reparse(sw, &hw[ent_idx + i]); - SW_RTN_ON_ERROR(rv); - b_ip4 = A_TRUE; - } - else if (GARUDA_IP6R1_FILTER == flt_typ) - { - rv = _garuda_acl_rule_ip6r1_reparse(sw, &hw[ent_idx + i]); - SW_RTN_ON_ERROR(rv); - b_ip6 = A_TRUE; - } - else if (GARUDA_IP6R2_FILTER == flt_typ) - { - rv = _garuda_acl_rule_ip6r2_reparse(sw, &hw[ent_idx + i]); - SW_RTN_ON_ERROR(rv); - b_ip6 = A_TRUE; - } - else if (GARUDA_IP6R3_FILTER == flt_typ) - { - rv = _garuda_acl_rule_ip6r3_reparse(sw, &hw[ent_idx + i]); - SW_RTN_ON_ERROR(rv); - b_ip6 = A_TRUE; - } - else - { - return SW_FAIL; - } - } - - if (A_TRUE == b_ip4) - { - sw->rule_type = FAL_ACL_RULE_IP4; - } - - if (A_TRUE == b_ip6) - { - sw->rule_type = FAL_ACL_RULE_IP6; - } - - return SW_OK; -} - -static sw_error_t -_garuda_acl_rule_copy(a_uint32_t dev_id, a_uint32_t src_slct_idx, - a_uint32_t dst_slct_idx, a_uint32_t size) -{ - sw_error_t rv; - a_uint32_t i; - a_int32_t step, src_idx, dst_idx; - garuda_acl_hw_rule_t rule; - - if (dst_slct_idx <= src_slct_idx) - { - src_idx = src_slct_idx & 0x7fffffff; - dst_idx = dst_slct_idx & 0x7fffffff; - step = 1; - } - else - { - src_idx = (src_slct_idx + size - 1) & 0x7fffffff; - dst_idx = (dst_slct_idx + size - 1) & 0x7fffffff; - step = -1; - } - - aos_mem_zero(&rule, sizeof (garuda_acl_hw_rule_t)); - for (i = 0; i < size; i++) - { - rv = _garuda_acl_rule_invalid(dev_id, (a_uint32_t) dst_idx, 1); - SW_RTN_ON_ERROR(rv); - - rv = _garuda_acl_action_read(dev_id, &rule, (a_uint32_t) src_idx); - SW_RTN_ON_ERROR(rv); - - rv = _garuda_acl_action_write(dev_id, &rule, (a_uint32_t) dst_idx); - SW_RTN_ON_ERROR(rv); - - rv = _garuda_acl_slct_read(dev_id, &rule, (a_uint32_t) src_idx); - SW_RTN_ON_ERROR(rv); - - rv = _garuda_acl_slct_write(dev_id, &rule, (a_uint32_t) dst_idx); - SW_RTN_ON_ERROR(rv); - - rv = _garuda_acl_rule_invalid(dev_id, (a_uint32_t) src_idx, 1); - SW_RTN_ON_ERROR(rv); - - src_idx += step; - dst_idx += step; - } - - return SW_OK; -} - -static sw_error_t -_garuda_acl_rule_invalid(a_uint32_t dev_id, a_uint32_t rule_idx, - a_uint32_t size) -{ - sw_error_t rv; - a_uint32_t base, flag, i; - - flag = 0; - for (i = 0; i < size; i++) - { - base = GARUDA_RULE_SLCT_ADDR + ((rule_idx + i) << 5); - HSL_REG_ENTRY_GEN_SET(rv, dev_id, base, sizeof (a_uint32_t), - (a_uint8_t *) (&flag), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - } - return SW_OK; -} - -static sw_error_t -_garuda_acl_rule_valid(a_uint32_t dev_id, a_uint32_t rule_idx, a_uint32_t size, - a_uint32_t flag) -{ - sw_error_t rv; - a_uint32_t base, i; - - for (i = 0; i < size; i++) - { - base = GARUDA_RULE_SLCT_ADDR + ((rule_idx + i) << 5); - HSL_REG_ENTRY_GEN_SET(rv, dev_id, base, sizeof (a_uint32_t), - (a_uint8_t *) (&flag), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - } - return SW_OK; -} - -static sw_error_t -_garuda_acl_addr_update(a_uint32_t dev_id, a_uint32_t old_addr, - a_uint32_t new_addr, a_uint32_t list_id) -{ - sw_error_t rv; - a_uint32_t idx; - - rv = _garuda_acl_list_loc(dev_id, list_id, &idx); - SW_RTN_ON_ERROR(rv); - - if (old_addr != list_ent[dev_id][idx].addr) - { - return SW_FAIL; - } - - list_ent[dev_id][idx].addr = new_addr; - return SW_OK; -} - -static sw_error_t -_garuda_acl_rule_bind(a_uint32_t dev_id, a_uint32_t rule_idx, a_uint32_t ports) -{ - sw_error_t rv; - a_uint32_t flt_idx[4], flt_nr; - a_uint32_t bind_pts = 0, addr, i, ret = 0; - garuda_acl_hw_rule_t rule; - - aos_mem_zero(&rule, sizeof (garuda_acl_hw_rule_t)); - - rv = _garuda_acl_slct_read(dev_id, &rule, rule_idx); - SW_RTN_ON_ERROR(rv); - - rv = _garuda_acl_filter_map_get(&rule, flt_idx, &flt_nr); - SW_RTN_ON_ERROR(rv); - - rv = _garuda_acl_rule_invalid(dev_id, rule_idx, 1); - SW_RTN_ON_ERROR(rv); - - for (i = 0; i < flt_nr; i++) - { - addr = GARUDA_RULE_VLU_ADDR + (flt_idx[i] << 5) + 16; - HSL_REG_ENTRY_GEN_GET(rv, dev_id, addr, sizeof (a_uint32_t), - (a_uint8_t *) (&bind_pts), sizeof (a_uint32_t)); - - /* source port field in different type rules has the same - hardware bit position */ - SW_SET_REG_BY_FIELD(MAC_RUL_V4, MAC_INPT, ports, bind_pts); - - HSL_REG_ENTRY_GEN_SET(rv, dev_id, addr, sizeof (a_uint32_t), - (a_uint8_t *) (&bind_pts), sizeof (a_uint32_t)); - ret += rv; - } - - rv = _garuda_acl_rule_valid(dev_id, rule_idx, 1, rule.slct[0]); - ret += rv; - if (0 != ret) - { - return SW_FAIL; - } - - return SW_OK; -} - -static sw_error_t -_garuda_acl_list_creat(a_uint32_t dev_id, a_uint32_t list_id, - a_uint32_t list_pri) -{ - a_uint32_t i, loc = GARUDA_MAX_LIST; - - HSL_DEV_ID_CHECK(dev_id); - - for (i = 0; i < GARUDA_MAX_LIST; i++) - { - if ((ENT_USED == list_ent[dev_id][i].status) - && (list_id == list_ent[dev_id][i].list_id)) - { - return SW_ALREADY_EXIST; - } - - if (ENT_FREE == list_ent[dev_id][i].status) - { - loc = i; - } - } - - if (GARUDA_MAX_LIST == loc) - { - return SW_NO_RESOURCE; - } - - aos_mem_zero(&(list_ent[dev_id][loc]), sizeof (garuda_acl_list_t)); - list_ent[dev_id][loc].list_id = list_id; - list_ent[dev_id][loc].list_pri = list_pri; - list_ent[dev_id][loc].status = ENT_USED; - _garuda_acl_list_dump(dev_id); - return SW_OK; -} - - -static sw_error_t -_garuda_acl_list_destroy(a_uint32_t dev_id, a_uint32_t list_id) -{ - a_uint32_t list_idx; - - HSL_DEV_ID_CHECK(dev_id); - - for (list_idx = 0; list_idx < GARUDA_MAX_LIST; list_idx++) - { - if ((ENT_USED == list_ent[dev_id][list_idx].status) - && (list_id == list_ent[dev_id][list_idx].list_id)) - { - break; - } - } - - if (list_idx >= GARUDA_MAX_LIST) - { - return SW_NOT_FOUND; - } - - if (0 != list_ent[dev_id][list_idx].bind_pts) - { - return SW_NOT_SUPPORTED; - } - - if (0 != list_ent[dev_id][list_idx].size) - { - return SW_NOT_SUPPORTED; - } - - aos_mem_zero(&(list_ent[dev_id][list_idx]), sizeof (garuda_acl_list_t)); - list_ent[dev_id][list_idx].status = ENT_FREE; - _garuda_acl_list_dump(dev_id); - return SW_OK; -} - - -static sw_error_t -_garuda_acl_rule_add(a_uint32_t dev_id, a_uint32_t list_id, - a_uint32_t rule_id, a_uint32_t rule_nr, - fal_acl_rule_t * rule) -{ - sw_error_t rv; - a_uint32_t hsl_f_rsc, list_new_size, list_addr; - a_uint32_t list_pri, list_idx, load_addr, bind_pts; - - HSL_DEV_ID_CHECK(dev_id); - - if ((0 == rule_nr) || (NULL == rule)) - { - return SW_BAD_PARAM; - } - - rv = hsl_acl_free_rsc_get(dev_id, &hsl_f_rsc); - SW_RTN_ON_ERROR(rv); - if (hsl_f_rsc < rule_nr) - { - return SW_NO_RESOURCE; - } - - rv = _garuda_acl_list_loc(dev_id, list_id, &list_idx); - SW_RTN_ON_ERROR(rv); - - if (rule_id != list_ent[dev_id][list_idx].size) - { - return SW_ALREADY_EXIST; - } - bind_pts = list_ent[dev_id][list_idx].bind_pts; - - _garuda_acl_filter_snap(dev_id); - - /* parse rule entry and alloc rule resource */ - { - a_uint32_t i, j; - a_uint32_t ent_idx, tmp_ent_idx, flt_idx, flt_len; - - aos_mem_zero(hw_rule_ent, - GARUDA_MAX_RULE * sizeof (garuda_acl_hw_rule_t)); - - ent_idx = 0; - for (i = 0; i < rule_nr; i++) - { - tmp_ent_idx = ent_idx; - rv = _garuda_acl_rule_sw_to_hw(dev_id, &rule[i], bind_pts, - &hw_rule_ent[ent_idx], &ent_idx, - &flt_len); - SW_RTN_ON_ERROR(rv); - - for (j = tmp_ent_idx; j < ent_idx; j++) - { - rv = _garuda_acl_filter_alloc(dev_id, &flt_idx); - SW_RTN_ON_ERROR(rv); - - rv = _garuda_acl_slct_update(&hw_rule_ent[tmp_ent_idx], - j - tmp_ent_idx, flt_idx); - SW_RTN_ON_ERROR(rv); - } - SW_SET_REG_BY_FIELD(RUL_SLCT6, RULE_LEN, flt_len, - hw_rule_ent[tmp_ent_idx].slct[6]); - } - } - - /* alloc hardware select entry resource */ - if (0 == list_ent[dev_id][list_idx].size) - { - list_new_size = rule_nr; - list_pri = list_ent[dev_id][list_idx].list_pri; - - rv = hsl_acl_blk_alloc(dev_id, list_pri, list_new_size, list_id, - &list_addr); - SW_RTN_ON_ERROR(rv); - - load_addr = list_addr; - } - else - { - list_new_size = list_ent[dev_id][list_idx].size + rule_nr; - list_addr = list_ent[dev_id][list_idx].addr; - - rv = hsl_acl_blk_resize(dev_id, list_addr, list_new_size); - SW_RTN_ON_ERROR(rv); - - /* must be careful resize opration maybe change list base address */ - list_addr = list_ent[dev_id][list_idx].addr; - load_addr = list_ent[dev_id][list_idx].size + list_addr; - } - - /* load acl rule to hardware */ - rv = _garuda_acl_rule_set(dev_id, load_addr, hw_rule_ent, rule_nr); - if (SW_OK != rv) - { - (void) hsl_acl_blk_resize(dev_id, list_addr, - list_ent[dev_id][list_idx].size); - return rv; - } - - /* update software list control information */ - list_ent[dev_id][list_idx].size = list_new_size; - list_ent[dev_id][list_idx].addr = list_addr; - - /* update hardware acl rule resource information */ - _garuda_acl_filter_commit(dev_id); - _garuda_acl_list_dump(dev_id); - return SW_OK; -} - - -static sw_error_t -_garuda_acl_rule_delete(a_uint32_t dev_id, a_uint32_t list_id, - a_uint32_t rule_id, a_uint32_t rule_nr) -{ - sw_error_t rv; - a_uint32_t flt_idx[4]; - a_uint32_t i, j, flt_nr; - a_uint32_t list_idx, addr, size, rule_idx, cnt; - - HSL_DEV_ID_CHECK(dev_id); - - rv = _garuda_acl_list_loc(dev_id, list_id, &list_idx); - SW_RTN_ON_ERROR(rv); - - if (0 == rule_nr) - { - return SW_BAD_PARAM; - } - - if ((rule_id + rule_nr) > list_ent[dev_id][list_idx].size) - { - return SW_NOT_FOUND; - } - - _garuda_acl_filter_snap(dev_id); - - /* free hardware filter resource */ - addr = list_ent[dev_id][list_idx].addr + rule_id; - for (i = 0; i < rule_nr; i++) - { - rv = _garuda_acl_slct_read(dev_id, &hw_rule_ent[0], i + addr); - SW_RTN_ON_ERROR(rv); - - rv = _garuda_acl_filter_map_get(&hw_rule_ent[0], flt_idx, &flt_nr); - SW_RTN_ON_ERROR(rv); - - for (j = 0; j < flt_nr; j++) - { - _garuda_acl_filter_free(dev_id, flt_idx[j]); - } - } - - cnt = list_ent[dev_id][list_idx].size - (rule_id + rule_nr); - rule_idx = list_ent[dev_id][list_idx].addr + (rule_id + rule_nr); - rv = _garuda_acl_rule_copy(dev_id, rule_idx, rule_idx - rule_nr, cnt); - SW_RTN_ON_ERROR(rv); - - addr = list_ent[dev_id][list_idx].addr; - size = list_ent[dev_id][list_idx].size; - rv = hsl_acl_blk_resize(dev_id, addr, size - rule_nr); - SW_RTN_ON_ERROR(rv); - - list_ent[dev_id][list_idx].size -= rule_nr; - _garuda_acl_filter_commit(dev_id); - _garuda_acl_list_dump(dev_id); - return SW_OK; -} - - -static sw_error_t -_garuda_acl_rule_query(a_uint32_t dev_id, a_uint32_t list_id, - a_uint32_t rule_id, fal_acl_rule_t * rule) -{ - sw_error_t rv; - a_uint32_t list_idx, ent_idx, tmp_ent_idx, rule_idx; - - HSL_DEV_ID_CHECK(dev_id); - - rv = _garuda_acl_list_loc(dev_id, list_id, &list_idx); - SW_RTN_ON_ERROR(rv); - - if (rule_id >= list_ent[dev_id][list_idx].size) - { - return SW_NOT_FOUND; - } - - aos_mem_zero(rule, sizeof (fal_acl_rule_t)); - - ent_idx = 0; - tmp_ent_idx = 0; - rule_idx = list_ent[dev_id][list_idx].addr + rule_id; - rv = _garuda_acl_rule_get(dev_id, hw_rule_ent, &tmp_ent_idx, rule_idx); - SW_RTN_ON_ERROR(rv); - - rv = _garuda_acl_rule_hw_to_sw(rule, hw_rule_ent, ent_idx, - tmp_ent_idx - ent_idx); - return rv; -} - - -static sw_error_t -_garuda_acl_list_bind(a_uint32_t dev_id, a_uint32_t list_id, - fal_acl_direc_t direc, fal_acl_bind_obj_t obj_t, - a_uint32_t obj_idx) -{ - sw_error_t rv; - a_uint32_t i, list_idx, rule_idx, base, ports; - - HSL_DEV_ID_CHECK(dev_id); - - if (FAL_ACL_DIREC_IN != direc) - { - return SW_NOT_SUPPORTED; - } - - if (FAL_ACL_BIND_PORT != obj_t) - { - return SW_NOT_SUPPORTED; - } - - rv = _garuda_acl_list_loc(dev_id, list_id, &list_idx); - SW_RTN_ON_ERROR(rv); - - if (list_ent[dev_id][list_idx].bind_pts & (0x1 << obj_idx)) - { - return SW_ALREADY_EXIST; - } - - base = list_ent[dev_id][list_idx].addr; - ports = list_ent[dev_id][list_idx].bind_pts | (0x1 << obj_idx); - for (i = 0; i < list_ent[dev_id][list_idx].size; i++) - { - rule_idx = base + i; - rv = _garuda_acl_rule_bind(dev_id, rule_idx, ports); - SW_RTN_ON_ERROR(rv); - } - - list_ent[dev_id][list_idx].bind_pts = ports; - return SW_OK; -} - - - -static sw_error_t -_garuda_acl_list_unbind(a_uint32_t dev_id, a_uint32_t list_id, - fal_acl_direc_t direc, fal_acl_bind_obj_t obj_t, - a_uint32_t obj_idx) -{ - sw_error_t rv; - a_uint32_t i, list_idx, rule_idx, base, ports; - - HSL_DEV_ID_CHECK(dev_id); - - if (FAL_ACL_DIREC_IN != direc) - { - return SW_NOT_SUPPORTED; - } - - if (FAL_ACL_BIND_PORT != obj_t) - { - return SW_NOT_SUPPORTED; - } - - rv = _garuda_acl_list_loc(dev_id, list_id, &list_idx); - SW_RTN_ON_ERROR(rv); - - if (!(list_ent[dev_id][list_idx].bind_pts & (0x1 << obj_idx))) - { - return SW_NOT_FOUND; - } - - base = list_ent[dev_id][list_idx].addr; - ports = list_ent[dev_id][list_idx].bind_pts & (~(0x1UL << obj_idx)); - for (i = 0; i < list_ent[dev_id][list_idx].size; i++) - { - rule_idx = base + i; - rv = _garuda_acl_rule_bind(dev_id, rule_idx, ports); - SW_RTN_ON_ERROR(rv); - } - - list_ent[dev_id][list_idx].bind_pts = ports; - return SW_OK; -} - - -static sw_error_t -_garuda_acl_status_set(a_uint32_t dev_id, a_bool_t enable) -{ - sw_error_t rv; - a_uint32_t val; - - HSL_DEV_ID_CHECK(dev_id); - - if (A_TRUE == enable) - { - val = 1; - } - else if (A_FALSE == enable) - { - val = 0; - } - else - { - return SW_BAD_PARAM; - } - - HSL_REG_FIELD_SET(rv, dev_id, QM_CTL, 0, ACL_EN, - (a_uint8_t *) (&val), sizeof (a_uint32_t)); - return rv; -} - - -static sw_error_t -_garuda_acl_status_get(a_uint32_t dev_id, a_bool_t * enable) -{ - sw_error_t rv; - a_uint32_t val; - - HSL_DEV_ID_CHECK(dev_id); - - HSL_REG_FIELD_GET(rv, dev_id, QM_CTL, 0, ACL_EN, - (a_uint8_t *) (&val), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - - if (val) - { - *enable = A_TRUE; - } - else - { - *enable = A_FALSE; - } - - return SW_OK; -} - -HSL_LOCAL sw_error_t -garuda_acl_list_dump(a_uint32_t dev_id) -{ - a_uint32_t idx; - - aos_printk("\ngaruda_acl_list_dump:\n"); - for (idx = 0; idx < GARUDA_MAX_LIST; idx++) - { - if (ENT_USED == list_ent[dev_id][idx].status) - { - aos_printk - ("\n[id]:%02d [pri]:%02d [size]:%02d [addr]:%02d [pts_map]:0x%02x", - list_ent[dev_id][idx].list_id, list_ent[dev_id][idx].list_pri, - list_ent[dev_id][idx].size, list_ent[dev_id][idx].addr, - list_ent[dev_id][idx].bind_pts); - } - } - aos_printk("\n"); - - return SW_OK; -} - -HSL_LOCAL sw_error_t -garuda_acl_rule_dump(a_uint32_t dev_id) -{ - a_uint32_t slt_idx, flt_nr, i, j; - a_uint32_t flt_idx[4]; - sw_error_t rv; - garuda_acl_hw_rule_t rule; - - aos_printk("\ngaruda_acl_rule_dump:\n"); - - aos_printk("\nfilter_bitmap:0x%x", filter[dev_id]); - for (slt_idx = 0; slt_idx < GARUDA_MAX_RULE; slt_idx++) - { - aos_mem_zero(&rule, sizeof (garuda_acl_hw_rule_t)); - - rv = _garuda_acl_slct_read(dev_id, &rule, slt_idx); - if (SW_OK != rv) - { - continue; - } - - rv = _garuda_acl_filter_map_get(&rule, flt_idx, &flt_nr); - if (SW_OK != rv) - { - continue; - } - - aos_printk("\nslct_idx=%d ", slt_idx); - for (i = 0; i < flt_nr; i++) - { - aos_printk("flt%d_idx=%d ", i, flt_idx[i]); - } - - aos_printk("\nslt:"); - for (i = 0; i < 8; i++) - { - aos_printk("%08x ", rule.slct[i]); - } - - if (flt_nr) - { - rv = _garuda_acl_action_read(dev_id, &rule, slt_idx); - if (SW_OK != rv) - { - continue; - } - aos_printk("\nact:%08x ", rule.act); - - for (i = 0; i < flt_nr; i++) - { - rv = _garuda_acl_filter_read(dev_id, &rule, flt_idx[i]); - if (SW_OK != rv) - { - continue; - } - - aos_printk("\ntyp:%08x ", rule.typ); - aos_printk("\nvlu:"); - for (j = 0; j < 5; j++) - { - aos_printk("%08x ", rule.vlu[j]); - } - - aos_printk("\nmsk:"); - for (j = 0; j < 5; j++) - { - aos_printk("%08x ", rule.msk[j]); - } - aos_printk("\n"); - } - } - aos_printk("\n"); - } - - return SW_OK; -} - -sw_error_t -garuda_acl_reset(a_uint32_t dev_id) -{ - sw_error_t rv; - a_uint32_t i; - - HSL_DEV_ID_CHECK(dev_id); - - aos_mem_zero(hw_rule_ent, - (GARUDA_MAX_RULE + 3) * sizeof (garuda_acl_hw_rule_t)); - - aos_mem_zero(list_ent[dev_id], - GARUDA_MAX_LIST * sizeof (garuda_acl_list_t)); - - for (i = 0; i < GARUDA_MAX_LIST; i++) - { - list_ent[dev_id][i].status = ENT_FREE; - } - - filter[dev_id] = 0; - filter_snap[dev_id] = 0; - - rv = hsl_acl_pool_destroy(dev_id); - SW_RTN_ON_ERROR(rv); - - rv = hsl_acl_pool_creat(dev_id, GARUDA_MAX_LIST, GARUDA_MAX_RULE); - SW_RTN_ON_ERROR(rv); - - return SW_OK; -} - -/** - * @brief Creat an acl list - * @details Comments: - * If the priority of a list is more small then the priority is more high, - * that means the list could be first matched. - * @param[in] dev_id device id - * @param[in] list_id acl list id - * @param[in] list_pri acl list priority - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -garuda_acl_list_creat(a_uint32_t dev_id, a_uint32_t list_id, - a_uint32_t list_pri) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _garuda_acl_list_creat(dev_id, list_id, list_pri); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Destroy an acl list - * @param[in] dev_id device id - * @param[in] list_id acl list id - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -garuda_acl_list_destroy(a_uint32_t dev_id, a_uint32_t list_id) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _garuda_acl_list_destroy(dev_id, list_id); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Add one rule or more rules to an existing acl list - * @param[in] dev_id device id - * @param[in] list_id acl list id - * @param[in] rule_id first rule id of this adding operation in list - * @param[in] rule_nr rule number of this adding operation - * @param[in] rule rules content of this adding operation - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -garuda_acl_rule_add(a_uint32_t dev_id, a_uint32_t list_id, - a_uint32_t rule_id, a_uint32_t rule_nr, - fal_acl_rule_t * rule) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _garuda_acl_rule_add(dev_id, list_id, rule_id, rule_nr, rule); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Delete one rule or more rules from an existing acl list - * @param[in] dev_id device id - * @param[in] list_id acl list id - * @param[in] rule_id first rule id of this deleteing operation in list - * @param[in] rule_nr rule number of this deleteing operation - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -garuda_acl_rule_delete(a_uint32_t dev_id, a_uint32_t list_id, - a_uint32_t rule_id, a_uint32_t rule_nr) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _garuda_acl_rule_delete(dev_id, list_id, rule_id, rule_nr); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Query one particular rule in a particular acl list - * @param[in] dev_id device id - * @param[in] list_id acl list id - * @param[in] rule_id first rule id of this deleteing operation in list - * @param[out] rule rule content of this operation - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -garuda_acl_rule_query(a_uint32_t dev_id, a_uint32_t list_id, - a_uint32_t rule_id, fal_acl_rule_t * rule) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _garuda_acl_rule_query(dev_id, list_id, rule_id, rule); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Bind an acl list to a particular object - * @details Comments: - * If obj_t equals FAL_ACL_BIND_PORT then obj_idx means port id - * @param[in] dev_id device id - * @param[in] list_id acl list id - * @param[in] direc direction of this binding operation - * @param[in] obj_t object type of this binding operation - * @param[in] obj_idx object index of this binding operation - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -garuda_acl_list_bind(a_uint32_t dev_id, a_uint32_t list_id, - fal_acl_direc_t direc, fal_acl_bind_obj_t obj_t, - a_uint32_t obj_idx) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _garuda_acl_list_bind(dev_id, list_id, direc, obj_t, obj_idx); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Unbind an acl list from a particular object - * @details Comments: - * If obj_t equals FAL_ACL_BIND_PORT then obj_idx means port id - * @param[in] dev_id device id - * @param[in] list_id acl list id - * @param[in] direc direction of this unbinding operation - * @param[in] obj_t object type of this unbinding operation - * @param[in] obj_idx object index of this unbinding operation - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -garuda_acl_list_unbind(a_uint32_t dev_id, a_uint32_t list_id, - fal_acl_direc_t direc, fal_acl_bind_obj_t obj_t, - a_uint32_t obj_idx) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _garuda_acl_list_unbind(dev_id, list_id, direc, obj_t, obj_idx); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Set working status of ACL engine on a particular device - * @param[in] dev_id device id - * @param[in] enable A_TRUE or A_FALSE - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -garuda_acl_status_set(a_uint32_t dev_id, a_bool_t enable) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _garuda_acl_status_set(dev_id, enable); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Get working status of ACL engine on a particular device - * @param[in] dev_id device id - * @param[out] enable A_TRUE or A_FALSE - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -garuda_acl_status_get(a_uint32_t dev_id, a_bool_t * enable) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _garuda_acl_status_get(dev_id, enable); - HSL_API_UNLOCK; - return rv; -} - -sw_error_t -garuda_acl_init(a_uint32_t dev_id) -{ - static a_bool_t b_hw_rule = A_FALSE; - hsl_acl_func_t *acl_func; - garuda_acl_hw_rule_t rule; - sw_error_t rv; - a_uint32_t i; - - HSL_DEV_ID_CHECK(dev_id); - - if (A_FALSE == b_hw_rule) - { - hw_rule_ent = (garuda_acl_hw_rule_t *) - aos_mem_alloc((GARUDA_MAX_RULE + - 3) * sizeof (garuda_acl_hw_rule_t)); - if (NULL == hw_rule_ent) - { - return SW_NO_RESOURCE; - } - aos_mem_zero(hw_rule_ent, - (GARUDA_MAX_RULE + 3) * sizeof (garuda_acl_hw_rule_t)); - b_hw_rule = A_TRUE; - } - - list_ent[dev_id] = (garuda_acl_list_t *) - aos_mem_alloc(GARUDA_MAX_LIST * sizeof (garuda_acl_list_t)); - if (NULL == list_ent[dev_id]) - { - return SW_NO_RESOURCE; - } - aos_mem_zero(list_ent[dev_id], - GARUDA_MAX_LIST * sizeof (garuda_acl_list_t)); - - for (i = 0; i < GARUDA_MAX_LIST; i++) - { - list_ent[dev_id][i].status = ENT_FREE; - } - - filter[dev_id] = 0; - filter_snap[dev_id] = 0; - - rv = hsl_acl_pool_creat(dev_id, GARUDA_MAX_LIST, GARUDA_MAX_RULE); - SW_RTN_ON_ERROR(rv); - - acl_func = hsl_acl_ptr_get(dev_id); - SW_RTN_ON_NULL(acl_func); - - acl_func->acl_rule_copy = _garuda_acl_rule_copy; - acl_func->acl_rule_invalid = _garuda_acl_rule_invalid; - acl_func->acl_addr_update = _garuda_acl_addr_update; - - /* zero acl hardware memory */ - aos_mem_zero(&rule, sizeof (garuda_acl_hw_rule_t)); - for (i = 0; i < GARUDA_MAX_RULE; i++) - { - rv = _garuda_acl_slct_write(dev_id, &rule, i); - SW_RTN_ON_ERROR(rv); - } - -#ifdef GARUDA_SW_ENTRY - flt_vlu_mem = aos_mem_alloc(GARUDA_MAX_RULE * 32); - if (NULL == flt_vlu_mem) - { - return SW_NO_RESOURCE; - } - aos_mem_zero(flt_vlu_mem, GARUDA_MAX_RULE * 32); - - flt_msk_mem = aos_mem_alloc(GARUDA_MAX_RULE * 32); - if (NULL == flt_msk_mem) - { - return SW_NO_RESOURCE; - } - aos_mem_zero(flt_msk_mem, GARUDA_MAX_RULE * 32); - - flt_typ_mem = aos_mem_alloc(GARUDA_MAX_RULE * 4); - if (NULL == flt_typ_mem) - { - return SW_NO_RESOURCE; - } - aos_mem_zero(flt_typ_mem, GARUDA_MAX_RULE * 4); - - act_mem = aos_mem_alloc(GARUDA_MAX_RULE * 32); - if (NULL == act_mem) - { - return SW_NO_RESOURCE; - } - aos_mem_zero(act_mem, GARUDA_MAX_RULE * 32); - - slct_mem = aos_mem_alloc(GARUDA_MAX_RULE * 32); - if (NULL == slct_mem) - { - return SW_NO_RESOURCE; - } - aos_mem_zero(slct_mem, GARUDA_MAX_RULE * 32); -#endif - -#ifndef HSL_STANDALONG - { - hsl_api_t *p_api; - - SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id)); - - p_api->acl_list_creat = garuda_acl_list_creat; - p_api->acl_list_destroy = garuda_acl_list_destroy; - p_api->acl_list_bind = garuda_acl_list_bind; - p_api->acl_list_unbind = garuda_acl_list_unbind; - p_api->acl_rule_add = garuda_acl_rule_add; - p_api->acl_rule_delete = garuda_acl_rule_delete; - p_api->acl_rule_query = garuda_acl_rule_query; - p_api->acl_status_set = garuda_acl_status_set; - p_api->acl_status_get = garuda_acl_status_get; - p_api->acl_list_dump = garuda_acl_list_dump; - p_api->acl_rule_dump = garuda_acl_rule_dump; - } -#endif - - return SW_OK; -} - -/** - * @} - */ - diff --git a/feeds/ipq807x/qca-ssdk/src/src/hsl/garuda/garuda_fdb.c b/feeds/ipq807x/qca-ssdk/src/src/hsl/garuda/garuda_fdb.c deleted file mode 100755 index 1904396dc..000000000 --- a/feeds/ipq807x/qca-ssdk/src/src/hsl/garuda/garuda_fdb.c +++ /dev/null @@ -1,1007 +0,0 @@ -/* - * Copyright (c) 2012, The Linux Foundation. All rights reserved. - * Permission to use, copy, modify, and/or distribute this software for - * any purpose with or without fee is hereby granted, provided that the - * above copyright notice and this permission notice appear in all copies. - * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES - * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR - * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES - * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN - * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT - * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. - */ - - - -/** - * @defgroup garuda_fdb GARUDA_FDB - * @{ - */ -#include "sw.h" -#include "hsl.h" -#include "hsl_dev.h" -#include "hsl_port_prop.h" -#include "garuda_fdb.h" -#include "garuda_reg.h" - -#define ARL_FLUSH_ALL 1 -#define ARL_LOAD_ENTRY 2 -#define ARL_PURGE_ENTRY 3 -#define ARL_FLUSH_ALL_UNLOCK 4 -#define ARL_FLUSH_PORT_UNICAST 5 -#define ARL_NEXT_ENTRY 6 -#define ARL_FIND_ENTRY 7 - -#define ARL_FIRST_ENTRY 1001 -#define ARL_FLUSH_PORT_NO_STATIC 1002 -#define ARL_FLUSH_PORT_AND_STATIC 1003 - -static a_bool_t -garuda_fdb_is_zeroaddr(fal_mac_addr_t addr) -{ - a_uint32_t i; - - for (i = 0; i < 6; i++) - { - if (addr.uc[i]) - { - return A_FALSE; - } - } - - return A_TRUE; -} - -static void -garuda_fdb_fill_addr(fal_mac_addr_t addr, a_uint32_t * reg0, a_uint32_t * reg1) -{ - SW_SET_REG_BY_FIELD(ADDR_TABLE_FUNC1, AT_ADDR_BYTE0, addr.uc[0], *reg1); - SW_SET_REG_BY_FIELD(ADDR_TABLE_FUNC1, AT_ADDR_BYTE1, addr.uc[1], *reg1); - SW_SET_REG_BY_FIELD(ADDR_TABLE_FUNC1, AT_ADDR_BYTE2, addr.uc[2], *reg1); - SW_SET_REG_BY_FIELD(ADDR_TABLE_FUNC1, AT_ADDR_BYTE3, addr.uc[3], *reg1); - - SW_SET_REG_BY_FIELD(ADDR_TABLE_FUNC0, AT_ADDR_BYTE4, addr.uc[4], *reg0); - SW_SET_REG_BY_FIELD(ADDR_TABLE_FUNC0, AT_ADDR_BYTE5, addr.uc[5], *reg0); - - return; -} - -static sw_error_t -garuda_atu_sw_to_hw(a_uint32_t dev_id, const fal_fdb_entry_t * entry, - a_uint32_t reg[]) -{ - a_uint32_t port; - - if (A_FALSE == entry->portmap_en) - { - if (A_TRUE != - hsl_port_prop_check(dev_id, entry->port.id, HSL_PP_INCL_CPU)) - { - return SW_BAD_PARAM; - } - - port = 0x1UL << entry->port.id; - } - else - { - if (A_FALSE == - hsl_mports_prop_check(dev_id, entry->port.map, HSL_PP_INCL_CPU)) - { - return SW_BAD_PARAM; - } - - port = entry->port.map; - } - - if (FAL_MAC_CPY_TO_CPU == entry->dacmd) - { - SW_SET_REG_BY_FIELD(ADDR_TABLE_FUNC2, COPY_TO_CPU, 1, reg[2]); - } - else if (FAL_MAC_RDT_TO_CPU == entry->dacmd) - { - SW_SET_REG_BY_FIELD(ADDR_TABLE_FUNC2, REDRCT_TO_CPU, 1, reg[2]); - } - else if (FAL_MAC_FRWRD != entry->dacmd) - { - return SW_NOT_SUPPORTED; - } - - if (FAL_MAC_DROP == entry->sacmd) - { - SW_SET_REG_BY_FIELD(ADDR_TABLE_FUNC2, SA_DROP_EN, 1, reg[2]); - } - else if (FAL_MAC_FRWRD != entry->sacmd) - { - return SW_NOT_SUPPORTED; - } - - if (A_TRUE == entry->leaky_en) - { - SW_SET_REG_BY_FIELD(ADDR_TABLE_FUNC2, LEAKY_EN, 1, reg[2]); - } - else - { - SW_SET_REG_BY_FIELD(ADDR_TABLE_FUNC2, LEAKY_EN, 0, reg[2]); - } - - if (A_TRUE == entry->static_en) - { - SW_SET_REG_BY_FIELD(ADDR_TABLE_FUNC2, AT_STATUS, 15, reg[2]); - } - else - { - SW_SET_REG_BY_FIELD(ADDR_TABLE_FUNC2, AT_STATUS, 7, reg[2]); - } - - if (A_TRUE == entry->mirror_en) - { - SW_SET_REG_BY_FIELD(ADDR_TABLE_FUNC2, MIRROR_EN, 1, reg[2]); - } - - if (A_TRUE == entry->clone_en) - { - SW_SET_REG_BY_FIELD(ADDR_TABLE_FUNC2, CLONE_EN, 1, reg[2]); - } - - if (A_TRUE == entry->da_pri_en) - { - hsl_dev_t *p_dev; - - SW_SET_REG_BY_FIELD(ADDR_TABLE_FUNC2, AT_PRI_EN, 1, reg[2]); - - SW_RTN_ON_NULL(p_dev = hsl_dev_ptr_get(dev_id)); - - if (entry->da_queue > (p_dev->nr_queue - 1)) - return SW_BAD_PARAM; - - SW_SET_REG_BY_FIELD(ADDR_TABLE_FUNC2, AT_PRI, entry->da_queue, reg[2]); - } - - if (A_TRUE == entry->cross_pt_state) - { - return SW_NOT_SUPPORTED; - } - - SW_SET_REG_BY_FIELD(ADDR_TABLE_FUNC2, DES_PORT, port, reg[2]); - garuda_fdb_fill_addr(entry->addr, ®[0], ®[1]); - - return SW_OK; -} - -static void -garuda_atu_hw_to_sw(const a_uint32_t reg[], fal_fdb_entry_t * entry) -{ - a_uint32_t i, data; - - aos_mem_zero(entry, sizeof (fal_fdb_entry_t)); - - entry->dacmd = FAL_MAC_FRWRD; - SW_GET_FIELD_BY_REG(ADDR_TABLE_FUNC2, COPY_TO_CPU, data, reg[2]); - if (1 == data) - { - entry->dacmd = FAL_MAC_CPY_TO_CPU; - } - - SW_GET_FIELD_BY_REG(ADDR_TABLE_FUNC2, REDRCT_TO_CPU, data, reg[2]); - if (1 == data) - { - entry->dacmd = FAL_MAC_RDT_TO_CPU; - } - - entry->sacmd = FAL_MAC_FRWRD; - SW_GET_FIELD_BY_REG(ADDR_TABLE_FUNC2, SA_DROP_EN, data, reg[2]); - if (1 == data) - { - entry->sacmd = FAL_MAC_DROP; - } - - entry->leaky_en = A_FALSE; - SW_GET_FIELD_BY_REG(ADDR_TABLE_FUNC2, LEAKY_EN, data, reg[2]); - if (1 == data) - { - entry->leaky_en = A_TRUE; - } - - entry->static_en = A_FALSE; - SW_GET_FIELD_BY_REG(ADDR_TABLE_FUNC2, AT_STATUS, data, reg[2]); - if (0xf == data) - { - entry->static_en = A_TRUE; - } - - entry->mirror_en = A_FALSE; - SW_GET_FIELD_BY_REG(ADDR_TABLE_FUNC2, MIRROR_EN, data, reg[2]); - if (1 == data) - { - entry->mirror_en = A_TRUE; - } - - entry->clone_en = A_FALSE; - SW_GET_FIELD_BY_REG(ADDR_TABLE_FUNC2, CLONE_EN, data, reg[2]); - if (1 == data) - { - entry->clone_en = A_TRUE; - } - - entry->da_pri_en = A_FALSE; - SW_GET_FIELD_BY_REG(ADDR_TABLE_FUNC2, AT_PRI_EN, data, reg[2]); - if (1 == data) - { - SW_GET_FIELD_BY_REG(ADDR_TABLE_FUNC2, AT_PRI, data, reg[2]); - entry->da_pri_en = A_TRUE; - entry->da_queue = data & 0x3; - } - - entry->cross_pt_state = A_FALSE; - - SW_GET_FIELD_BY_REG(ADDR_TABLE_FUNC2, DES_PORT, data, reg[2]); - - entry->portmap_en = A_TRUE; - entry->port.map = data; - - for (i = 0; i < 4; i++) - { - entry->addr.uc[i] = (reg[1] >> ((3 - i) << 3)) & 0xff; - } - - for (i = 4; i < 6; i++) - { - entry->addr.uc[i] = (reg[0] >> ((7 - i) << 3)) & 0xff; - } - - return; -} - -static sw_error_t -garuda_fdb_commit(a_uint32_t dev_id, a_uint32_t op) -{ - sw_error_t rv; - a_uint32_t busy = 1; - a_uint32_t full_vio; - a_uint32_t i = 1000; - a_uint32_t entry; - a_uint32_t hwop = op; - - while (busy && --i) - { - HSL_REG_FIELD_GET(rv, dev_id, ADDR_TABLE_FUNC0, 0, AT_BUSY, - (a_uint8_t *) (&busy), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - aos_udelay(5); - } - - if (0 == i) - { - return SW_BUSY; - } - - HSL_REG_ENTRY_GET(rv, dev_id, ADDR_TABLE_FUNC0, 0, - (a_uint8_t *) (&entry), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - - SW_SET_REG_BY_FIELD(ADDR_TABLE_FUNC0, AT_BUSY, 1, entry); - - if (ARL_FLUSH_PORT_AND_STATIC == hwop) - { - hwop = ARL_FLUSH_PORT_UNICAST; - SW_SET_REG_BY_FIELD(ADDR_TABLE_FUNC0, FLUSH_ST_EN, 1, entry); - } - - if (ARL_FLUSH_PORT_NO_STATIC == hwop) - { - hwop = ARL_FLUSH_PORT_UNICAST; - SW_SET_REG_BY_FIELD(ADDR_TABLE_FUNC0, FLUSH_ST_EN, 0, entry); - } - - SW_SET_REG_BY_FIELD(ADDR_TABLE_FUNC0, AT_FUNC, hwop, entry); - - HSL_REG_ENTRY_SET(rv, dev_id, ADDR_TABLE_FUNC0, 0, - (a_uint8_t *) (&entry), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - - busy = 1; - i = 1000; - while (busy && --i) - { - HSL_REG_FIELD_GET(rv, dev_id, ADDR_TABLE_FUNC0, 0, AT_BUSY, - (a_uint8_t *) (&busy), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - aos_udelay(5); - } - - if (0 == i) - { - return SW_FAIL; - } - - HSL_REG_FIELD_GET(rv, dev_id, ADDR_TABLE_FUNC0, 0, AT_FULL_VIO, - (a_uint8_t *) (&full_vio), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - - if (full_vio) - { - /* must clear AT_FULL_VOI bit */ - entry = 0x1000; - HSL_REG_ENTRY_SET(rv, dev_id, ADDR_TABLE_FUNC0, 0, - (a_uint8_t *) (&entry), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - - if (ARL_LOAD_ENTRY == hwop) - { - return SW_FULL; - } - else if ((ARL_PURGE_ENTRY == hwop) - || (ARL_FLUSH_PORT_UNICAST == hwop)) - { - return SW_NOT_FOUND; - } - else - { - return SW_FAIL; - } - } - - return SW_OK; -} - -static sw_error_t -garuda_atu_get(a_uint32_t dev_id, fal_fdb_entry_t * entry, a_uint32_t op) -{ - sw_error_t rv; - a_uint32_t reg[3] = { 0 }; - a_uint32_t status = 0; - a_uint32_t hwop = op; - - if ((ARL_NEXT_ENTRY == op) - || (ARL_FIND_ENTRY == op)) - { - garuda_fdb_fill_addr(entry->addr, ®[0], ®[1]); - } - - HSL_REG_ENTRY_SET(rv, dev_id, ADDR_TABLE_FUNC0, 0, - (a_uint8_t *) (®[0]), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - - HSL_REG_ENTRY_SET(rv, dev_id, ADDR_TABLE_FUNC1, 0, - (a_uint8_t *) (®[1]), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - - /* set status not zero */ - if (ARL_NEXT_ENTRY == op) - { - reg[2] = 0xf0000; - } - - if (ARL_FIRST_ENTRY == op) - { - hwop = ARL_NEXT_ENTRY; - } - - HSL_REG_ENTRY_SET(rv, dev_id, ADDR_TABLE_FUNC2, 0, - (a_uint8_t *) (®[2]), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - - rv = garuda_fdb_commit(dev_id, hwop); - SW_RTN_ON_ERROR(rv); - - /* get hardware enrety */ - HSL_REG_ENTRY_GET(rv, dev_id, ADDR_TABLE_FUNC0, 0, - (a_uint8_t *) (®[0]), sizeof (a_uint32_t)); - - SW_RTN_ON_ERROR(rv); - - HSL_REG_ENTRY_GET(rv, dev_id, ADDR_TABLE_FUNC1, 0, - (a_uint8_t *) (®[1]), sizeof (a_uint32_t)); - - SW_RTN_ON_ERROR(rv); - - HSL_REG_ENTRY_GET(rv, dev_id, ADDR_TABLE_FUNC2, 0, - (a_uint8_t *) (®[2]), sizeof (a_uint32_t)); - - SW_RTN_ON_ERROR(rv); - - SW_GET_FIELD_BY_REG(ADDR_TABLE_FUNC2, AT_STATUS, status, reg[2]); - - garuda_atu_hw_to_sw(reg, entry); - - /* If hardware return back with address and status all zero, - that means no other next valid entry in fdb table */ - if ((A_TRUE == garuda_fdb_is_zeroaddr(entry->addr)) - && (0 == status)) - { - if (ARL_NEXT_ENTRY == op) - { - return SW_NO_MORE; - } - else if ((ARL_FIND_ENTRY == op) - || (ARL_FIRST_ENTRY == op)) - { - return SW_NOT_FOUND; - } - else - { - return SW_FAIL; - } - } - else - { - return SW_OK; - } -} - -static sw_error_t -_garuda_fdb_add(a_uint32_t dev_id, const fal_fdb_entry_t * entry) -{ - sw_error_t rv; - a_uint32_t reg[3] = { 0, 0, 0 }; - - HSL_DEV_ID_CHECK(dev_id); - - rv = garuda_atu_sw_to_hw(dev_id, entry, reg); - SW_RTN_ON_ERROR(rv); - - HSL_REG_ENTRY_SET(rv, dev_id, ADDR_TABLE_FUNC2, 0, - (a_uint8_t *) (®[2]), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - - HSL_REG_ENTRY_SET(rv, dev_id, ADDR_TABLE_FUNC1, 0, (a_uint8_t *) (®[1]), - sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - - HSL_REG_ENTRY_SET(rv, dev_id, ADDR_TABLE_FUNC0, 0, (a_uint8_t *) (®[0]), - sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - - rv = garuda_fdb_commit(dev_id, ARL_LOAD_ENTRY); - - return rv; -} - - -static sw_error_t -_garuda_fdb_del_all(a_uint32_t dev_id, a_uint32_t flag) -{ - sw_error_t rv; - - HSL_DEV_ID_CHECK(dev_id); - - if (FAL_FDB_DEL_STATIC & flag) - { - rv = garuda_fdb_commit(dev_id, ARL_FLUSH_ALL); - } - else - { - rv = garuda_fdb_commit(dev_id, ARL_FLUSH_ALL_UNLOCK); - } - - return rv; -} - - -static sw_error_t -_garuda_fdb_del_by_port(a_uint32_t dev_id, fal_port_t port_id, a_uint32_t flag) -{ - sw_error_t rv; - a_uint32_t reg = 0; - - HSL_DEV_ID_CHECK(dev_id); - - if (A_FALSE == hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU)) - { - return SW_BAD_PARAM; - } - - SW_SET_REG_BY_FIELD(ADDR_TABLE_FUNC0, AT_PORT_NUM, port_id, reg); - - HSL_REG_ENTRY_SET(rv, dev_id, ADDR_TABLE_FUNC0, 0, (a_uint8_t *) (®), - sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - - if (FAL_FDB_DEL_STATIC & flag) - { - rv = garuda_fdb_commit(dev_id, ARL_FLUSH_PORT_AND_STATIC); - } - else - { - rv = garuda_fdb_commit(dev_id, ARL_FLUSH_PORT_NO_STATIC); - } - - return rv; -} - - -static sw_error_t -_garuda_fdb_del_by_mac(a_uint32_t dev_id, const fal_fdb_entry_t * entry) -{ - sw_error_t rv; - a_uint32_t reg0 = 0, reg1 = 0; - - HSL_DEV_ID_CHECK(dev_id); - - garuda_fdb_fill_addr(entry->addr, ®0, ®1); - - HSL_REG_ENTRY_SET(rv, dev_id, ADDR_TABLE_FUNC1, 0, (a_uint8_t *) (®1), - sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - - HSL_REG_ENTRY_SET(rv, dev_id, ADDR_TABLE_FUNC0, 0, (a_uint8_t *) (®0), - sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - - rv = garuda_fdb_commit(dev_id, ARL_PURGE_ENTRY); - return rv; -} - - -static sw_error_t -_garuda_fdb_next(a_uint32_t dev_id, fal_fdb_entry_t * entry) -{ - sw_error_t rv; - - HSL_DEV_ID_CHECK(dev_id); - - rv = garuda_atu_get(dev_id, entry, ARL_NEXT_ENTRY); - return rv; -} - - -static sw_error_t -_garuda_fdb_first(a_uint32_t dev_id, fal_fdb_entry_t * entry) -{ - sw_error_t rv; - - HSL_DEV_ID_CHECK(dev_id); - - rv = garuda_atu_get(dev_id, entry, ARL_FIRST_ENTRY); - return rv; -} - - -static sw_error_t -_garuda_fdb_find(a_uint32_t dev_id, fal_fdb_entry_t * entry) -{ - sw_error_t rv; - - HSL_DEV_ID_CHECK(dev_id); - - rv = garuda_atu_get(dev_id, entry, ARL_FIND_ENTRY); - return rv; -} - - -static sw_error_t -_garuda_fdb_port_learn_set(a_uint32_t dev_id, fal_port_t port_id, - a_bool_t enable) -{ - a_uint32_t data; - sw_error_t rv; - - HSL_DEV_ID_CHECK(dev_id); - - if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU)) - { - return SW_BAD_PARAM; - } - - if (A_TRUE == enable) - { - data = 1; - } - else if (A_FALSE == enable) - { - data = 0; - } - else - { - return SW_BAD_PARAM; - } - - HSL_REG_FIELD_SET(rv, dev_id, PORT_CTL, port_id, LEARN_EN, - (a_uint8_t *) (&data), sizeof (a_uint32_t)); - return rv; -} - - -static sw_error_t -_garuda_fdb_port_learn_get(a_uint32_t dev_id, fal_port_t port_id, - a_bool_t *enable) -{ - a_uint32_t data; - sw_error_t rv; - - HSL_DEV_ID_CHECK(dev_id); - - if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU)) - { - return SW_BAD_PARAM; - } - - HSL_REG_FIELD_GET(rv, dev_id, PORT_CTL, port_id, LEARN_EN, - (a_uint8_t *) (&data), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - - if (1 == data) - { - *enable = A_TRUE; - } - else - { - *enable = A_FALSE; - } - - return SW_OK; -} - -static sw_error_t -_garuda_fdb_age_ctrl_set(a_uint32_t dev_id, a_bool_t enable) -{ - a_uint32_t data; - sw_error_t rv; - - HSL_DEV_ID_CHECK(dev_id); - - if (A_TRUE == enable) - { - data = 1; - } - else if (A_FALSE == enable) - { - data = 0; - } - else - { - return SW_BAD_PARAM; - } - - HSL_REG_FIELD_SET(rv, dev_id, ADDR_TABLE_CTL, 0, AGE_EN, - (a_uint8_t *) (&data), sizeof (a_uint32_t)); - return rv; -} - - -static sw_error_t -_garuda_fdb_age_ctrl_get(a_uint32_t dev_id, a_bool_t *enable) -{ - a_uint32_t data; - sw_error_t rv; - - HSL_DEV_ID_CHECK(dev_id); - - HSL_REG_FIELD_GET(rv, dev_id, ADDR_TABLE_CTL, 0, AGE_EN, - (a_uint8_t *) (&data), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - - if (1 == data) - { - *enable = A_TRUE; - } - else - { - *enable = A_FALSE; - } - - return SW_OK; -} - - -static sw_error_t -_garuda_fdb_age_time_set(a_uint32_t dev_id, a_uint32_t * time) -{ - a_uint32_t data; - sw_error_t rv; - - HSL_DEV_ID_CHECK(dev_id); - - if ((65535 * 7 < *time) || (7 > *time)) - { - return SW_BAD_PARAM; - } - data = *time / 7; - *time = data * 7; - HSL_REG_FIELD_SET(rv, dev_id, ADDR_TABLE_CTL, 0, AGE_TIME, - (a_uint8_t *) (&data), sizeof (a_uint32_t)); - return rv; -} - - -static sw_error_t -_garuda_fdb_age_time_get(a_uint32_t dev_id, a_uint32_t *time) -{ - a_uint32_t data; - sw_error_t rv; - - HSL_DEV_ID_CHECK(dev_id); - - HSL_REG_FIELD_GET(rv, dev_id, ADDR_TABLE_CTL, 0, AGE_TIME, - (a_uint8_t *) (&data), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - - *time = data * 7; - return SW_OK; -} - -/** - * @brief Add a Fdb entry - * @param[in] dev_id device id - * @param[in] entry fdb entry - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -garuda_fdb_add(a_uint32_t dev_id, const fal_fdb_entry_t * entry) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _garuda_fdb_add(dev_id, entry); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Delete all Fdb entries - * @details Comments: - * If set FAL_FDB_DEL_STATIC bit in flag which means delete all fdb - * entries otherwise only delete dynamic entries. - * @param[in] dev_id device id - * @param[in] flag delete operation option - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -garuda_fdb_del_all(a_uint32_t dev_id, a_uint32_t flag) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _garuda_fdb_del_all(dev_id, flag); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Delete Fdb entries on a particular port - * @details Comments: - * If set FAL_FDB_DEL_STATIC bit in flag which means delete all fdb - * entries otherwise only delete dynamic entries. - * @param[in] dev_id device id - * @param[in] port_id port id - * @param[in] flag delete operation option - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -garuda_fdb_del_by_port(a_uint32_t dev_id, fal_port_t port_id, a_uint32_t flag) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _garuda_fdb_del_by_port(dev_id, port_id, flag); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Delete a particular Fdb entry through mac address - * @details Comments: - * Only addr field in entry is meaning. For IVL learning vid or fid field - * also is meaning. - * @param[in] dev_id device id - * @param[in] entry fdb entry - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -garuda_fdb_del_by_mac(a_uint32_t dev_id, const fal_fdb_entry_t * entry) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _garuda_fdb_del_by_mac(dev_id, entry); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Get next Fdb entry from particular device - * @details Comments: - * For input parameter only addr field in entry is meaning. - * @param[in] dev_id device id - * @param entry fdb entry - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -garuda_fdb_next(a_uint32_t dev_id, fal_fdb_entry_t * entry) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _garuda_fdb_next(dev_id, entry); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Get first Fdb entry from particular device - * @param[in] dev_id device id - * @param[out] entry fdb entry - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -garuda_fdb_first(a_uint32_t dev_id, fal_fdb_entry_t * entry) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _garuda_fdb_first(dev_id, entry); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Find a particular Fdb entry from device through mac address. - * @details Comments: - For input parameter only addr field in entry is meaning. - * @param[in] dev_id device id - * @param[in] entry fdb entry - * @param[out] entry fdb entry - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -garuda_fdb_find(a_uint32_t dev_id, fal_fdb_entry_t * entry) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _garuda_fdb_find(dev_id, entry); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Set dynamic address learning status on a particular port. - * @details Comments: - * This operation will enable or disable dynamic address learning - * feature on a particular port. - * @param[in] dev_id device id - * @param[in] port_id port id - * @param[in] enable enable or disable - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -garuda_fdb_port_learn_set(a_uint32_t dev_id, fal_port_t port_id, - a_bool_t enable) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _garuda_fdb_port_learn_set(dev_id, port_id, enable); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Get dynamic address learning status on a particular port. - * @param[in] dev_id device id - * @param[in] port_id port id - * @param[out] enable A_TRUE or A_FALSE - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -garuda_fdb_port_learn_get(a_uint32_t dev_id, fal_port_t port_id, - a_bool_t *enable) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _garuda_fdb_port_learn_get(dev_id, port_id, enable); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Set dynamic address aging status on particular device. - * @details Comments: - * This operation will enable or disable dynamic address aging - * feature on particular device. - * @param[in] dev_id device id - * @param[in] enable enable or disable - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -garuda_fdb_age_ctrl_set(a_uint32_t dev_id, a_bool_t enable) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _garuda_fdb_age_ctrl_set(dev_id, enable); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Get dynamic address aging status on particular device. - * @param[in] dev_id device id - * @param[in] enable enable or disable - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -garuda_fdb_age_ctrl_get(a_uint32_t dev_id, a_bool_t *enable) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _garuda_fdb_age_ctrl_get(dev_id, enable); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Set dynamic address aging time on a particular device. - * @details Comments: - * This operation will set dynamic address aging time on a particular device. - * The unit of time is second. Because different device has differnet - * hardware granularity function will return actual time in hardware. - * @param[in] dev_id device id - * @param time aging time - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -garuda_fdb_age_time_set(a_uint32_t dev_id, a_uint32_t * time) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _garuda_fdb_age_time_set(dev_id, time); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Get dynamic address aging time on a particular device. - * @param[in] dev_id device id - * @param[out] time aging time - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -garuda_fdb_age_time_get(a_uint32_t dev_id, a_uint32_t *time) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _garuda_fdb_age_time_get(dev_id, time); - HSL_API_UNLOCK; - return rv; -} - -sw_error_t -garuda_fdb_init(a_uint32_t dev_id) -{ - HSL_DEV_ID_CHECK(dev_id); - -#ifndef HSL_STANDALONG - { - hsl_api_t *p_api; - - SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id)); - - p_api->fdb_add = garuda_fdb_add; - p_api->fdb_del_all = garuda_fdb_del_all; - p_api->fdb_del_by_port = garuda_fdb_del_by_port; - p_api->fdb_del_by_mac = garuda_fdb_del_by_mac; - p_api->fdb_first = garuda_fdb_first; - p_api->fdb_next = garuda_fdb_next; - p_api->fdb_find = garuda_fdb_find; - p_api->port_learn_set = garuda_fdb_port_learn_set; - p_api->port_learn_get = garuda_fdb_port_learn_get; - p_api->age_ctrl_set = garuda_fdb_age_ctrl_set; - p_api->age_ctrl_get = garuda_fdb_age_ctrl_get; - p_api->age_time_set = garuda_fdb_age_time_set; - p_api->age_time_get = garuda_fdb_age_time_get; - } -#endif - - return SW_OK; -} - -/** - * @} - */ - diff --git a/feeds/ipq807x/qca-ssdk/src/src/hsl/garuda/garuda_igmp.c b/feeds/ipq807x/qca-ssdk/src/src/hsl/garuda/garuda_igmp.c deleted file mode 100755 index 5f95f70c8..000000000 --- a/feeds/ipq807x/qca-ssdk/src/src/hsl/garuda/garuda_igmp.c +++ /dev/null @@ -1,610 +0,0 @@ -/* - * Copyright (c) 2012, The Linux Foundation. All rights reserved. - * Permission to use, copy, modify, and/or distribute this software for - * any purpose with or without fee is hereby granted, provided that the - * above copyright notice and this permission notice appear in all copies. - * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES - * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR - * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES - * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN - * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT - * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. - */ - - -/** - * @defgroup garuda_igmp GARUDA_IGMP - * @{ - */ - -#include "sw.h" -#include "hsl.h" -#include "hsl_dev.h" -#include "hsl_port_prop.h" -#include "garuda_igmp.h" -#include "garuda_reg.h" - -static sw_error_t -_garuda_port_igmps_status_set(a_uint32_t dev_id, fal_port_t port_id, a_bool_t enable) -{ - sw_error_t rv; - a_uint32_t val; - - HSL_DEV_ID_CHECK(dev_id); - - if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_EXCL_CPU)) - { - return SW_BAD_PARAM; - } - - if (A_TRUE == enable) - { - val = 1; - } - else if (A_FALSE == enable) - { - val = 0; - } - else - { - return SW_BAD_PARAM; - } - - HSL_REG_FIELD_SET(rv, dev_id, PORT_CTL, port_id, IGMP_MLD_EN, - (a_uint8_t *) (&val), sizeof (a_uint32_t)); - return rv; -} - -static sw_error_t -_garuda_port_igmps_status_get(a_uint32_t dev_id, fal_port_t port_id, a_bool_t *enable) -{ - sw_error_t rv; - a_uint32_t val; - - HSL_DEV_ID_CHECK(dev_id); - - if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_EXCL_CPU)) - { - return SW_BAD_PARAM; - } - - HSL_REG_FIELD_GET(rv, dev_id, PORT_CTL, port_id, IGMP_MLD_EN, - (a_uint8_t *) (&val), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - - if (1 == val) - { - *enable = A_TRUE; - } - else - { - *enable = A_FALSE; - } - - return SW_OK; -} - -static sw_error_t -_garuda_igmp_mld_cmd_set(a_uint32_t dev_id, fal_fwd_cmd_t cmd) -{ - sw_error_t rv; - a_uint32_t val; - - HSL_DEV_ID_CHECK(dev_id); - - if (FAL_MAC_CPY_TO_CPU == cmd) - { - val = 1; - } - else if (FAL_MAC_RDT_TO_CPU == cmd) - { - val = 0; - } - else - { - return SW_NOT_SUPPORTED; - } - - HSL_REG_FIELD_SET(rv, dev_id, QM_CTL, 0, IGMP_COPY_EN, - (a_uint8_t *) (&val), sizeof (a_uint32_t)); - return rv; -} - -static sw_error_t -_garuda_igmp_mld_cmd_get(a_uint32_t dev_id, fal_fwd_cmd_t * cmd) -{ - sw_error_t rv; - a_uint32_t val; - - HSL_DEV_ID_CHECK(dev_id); - - HSL_REG_FIELD_GET(rv, dev_id, QM_CTL, 0, IGMP_COPY_EN, - (a_uint8_t *) (&val), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - - if (1 == val) - { - *cmd = FAL_MAC_CPY_TO_CPU; - } - else - { - *cmd = FAL_MAC_RDT_TO_CPU; - } - - return SW_OK; -} - -static sw_error_t -_garuda_port_igmp_mld_join_set(a_uint32_t dev_id, fal_port_t port_id, a_bool_t enable) -{ - sw_error_t rv; - a_uint32_t val; - - HSL_DEV_ID_CHECK(dev_id); - - if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_EXCL_CPU)) - { - return SW_BAD_PARAM; - } - - if (A_TRUE == enable) - { - val = 1; - } - else if (A_FALSE == enable) - { - val = 0; - } - else - { - return SW_BAD_PARAM; - } - - HSL_REG_FIELD_SET(rv, dev_id, PORT_CTL, port_id, JOIN_EN, - (a_uint8_t *) (&val), sizeof (a_uint32_t)); - return rv; -} - - -static sw_error_t -_garuda_port_igmp_mld_join_get(a_uint32_t dev_id, fal_port_t port_id, a_bool_t * enable) -{ - sw_error_t rv; - a_uint32_t val; - - HSL_DEV_ID_CHECK(dev_id); - - if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_EXCL_CPU)) - { - return SW_BAD_PARAM; - } - - HSL_REG_FIELD_GET(rv, dev_id, PORT_CTL, port_id, JOIN_EN, - (a_uint8_t *) (&val), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - - if (val) - { - *enable = A_TRUE; - } - else - { - *enable = A_FALSE; - } - - return SW_OK; -} - - -static sw_error_t -_garuda_port_igmp_mld_leave_set(a_uint32_t dev_id, fal_port_t port_id, a_bool_t enable) -{ - sw_error_t rv; - a_uint32_t val; - - HSL_DEV_ID_CHECK(dev_id); - - if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_EXCL_CPU)) - { - return SW_BAD_PARAM; - } - - if (A_TRUE == enable) - { - val = 1; - } - else if (A_FALSE == enable) - { - val = 0; - } - else - { - return SW_BAD_PARAM; - } - - HSL_REG_FIELD_SET(rv, dev_id, PORT_CTL, port_id, LEAVE_EN, - (a_uint8_t *) (&val), sizeof (a_uint32_t)); - return rv; -} - - -static sw_error_t -_garuda_port_igmp_mld_leave_get(a_uint32_t dev_id, fal_port_t port_id, a_bool_t * enable) -{ - sw_error_t rv; - a_uint32_t val; - - HSL_DEV_ID_CHECK(dev_id); - - if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_EXCL_CPU)) - { - return SW_BAD_PARAM; - } - - HSL_REG_FIELD_GET(rv, dev_id, PORT_CTL, port_id, LEAVE_EN, - (a_uint8_t *) (&val), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - - if (val) - { - *enable = A_TRUE; - } - else - { - *enable = A_FALSE; - } - - return SW_OK; -} - - -static sw_error_t -_garuda_igmp_mld_rp_set(a_uint32_t dev_id, fal_pbmp_t pts) -{ - sw_error_t rv; - a_uint32_t val; - - HSL_DEV_ID_CHECK(dev_id); - - if (A_FALSE == hsl_mports_validity_check(dev_id, pts)) - { - return SW_BAD_PARAM; - } - val = pts; - HSL_REG_FIELD_SET(rv, dev_id, FLOOD_MASK, 0, IGMP_DP, - (a_uint8_t *) (&val), sizeof (a_uint32_t)); - return rv; -} - - -static sw_error_t -_garuda_igmp_mld_rp_get(a_uint32_t dev_id, fal_pbmp_t * pts) -{ - sw_error_t rv; - a_uint32_t val; - - HSL_DEV_ID_CHECK(dev_id); - - HSL_REG_FIELD_GET(rv, dev_id, FLOOD_MASK, 0, IGMP_DP, - (a_uint8_t *) (&val), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - - *pts = val; - return SW_OK; -} - - -static sw_error_t -_garuda_igmp_mld_entry_creat_set(a_uint32_t dev_id, a_bool_t enable) -{ - sw_error_t rv; - a_uint32_t val; - - HSL_DEV_ID_CHECK(dev_id); - - if (A_TRUE == enable) - { - val = 1; - } - else if (A_FALSE == enable) - { - val = 0; - } - else - { - return SW_BAD_PARAM; - } - - HSL_REG_FIELD_SET(rv, dev_id, QM_CTL, 0, IGMP_CREAT_EN, - (a_uint8_t *) (&val), sizeof (a_uint32_t)); - return rv; -} - -static sw_error_t -_garuda_igmp_mld_entry_creat_get(a_uint32_t dev_id, a_bool_t * enable) -{ - sw_error_t rv; - a_uint32_t val; - - HSL_DEV_ID_CHECK(dev_id); - - HSL_REG_FIELD_GET(rv, dev_id, QM_CTL, 0, IGMP_CREAT_EN, - (a_uint8_t *) (&val), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - - if (val) - { - *enable = A_TRUE; - } - else - { - *enable = A_FALSE; - } - - return SW_OK; -} - -/** - * @brief Set igmp/mld packets snooping status on a particular port. - * @details Comments: - * After enabling igmp/mld snooping feature on a particular port all kinds - * igmp/mld packets received on this port would be acknowledged by hardware. - * Particular forwarding decision could be setted by fal_igmp_mld_cmd_set. - * @param[in] dev_id device id - * @param[in] port_id port id - * @param[in] enable A_TRUE or A_FALSE - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -garuda_port_igmps_status_set(a_uint32_t dev_id, fal_port_t port_id, a_bool_t enable) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _garuda_port_igmps_status_set(dev_id, port_id, enable); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Get igmp/mld packets snooping status on particular port. - * @param[in] dev_id device id - * @param[in] port_id port id - * @param[out] enable A_TRUE or A_FALSE - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -garuda_port_igmps_status_get(a_uint32_t dev_id, fal_port_t port_id, a_bool_t *enable) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _garuda_port_igmps_status_get(dev_id, port_id, enable); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Set igmp/mld packets forwarding command on a particular device. - * @details Comments: - * Particular device may only support parts of forwarding commands. - * This operation will take effect only after enabling igmp/mld snooping - * @param[in] dev_id device id - * @param[in] cmd forwarding command - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -garuda_igmp_mld_cmd_set(a_uint32_t dev_id, fal_fwd_cmd_t cmd) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _garuda_igmp_mld_cmd_set(dev_id, cmd); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Get igmp/mld packets forwarding command on a particular device. - * @param[in] dev_id device id - * @param[out] cmd forwarding command - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -garuda_igmp_mld_cmd_get(a_uint32_t dev_id, fal_fwd_cmd_t * cmd) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _garuda_igmp_mld_cmd_get(dev_id, cmd); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Set igmp/mld join packets hardware acknowledgement status on particular port. - * @details Comments: - * After enabling igmp/mld join feature on a particular port hardware will - * dynamic learning or changing multicast entry. - * @param[in] dev_id device id - * @param[in] port_id port id - * @param[in] enable A_TRUE or A_FALSE - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -garuda_port_igmp_mld_join_set(a_uint32_t dev_id, fal_port_t port_id, a_bool_t enable) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _garuda_port_igmp_mld_join_set(dev_id, port_id, enable); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Get igmp/mld join packets hardware acknowledgement status on a particular port. - * @param[in] dev_id device id - * @param[in] port_id port id - * @param[out] enable A_TRUE or A_FALSE - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -garuda_port_igmp_mld_join_get(a_uint32_t dev_id, fal_port_t port_id, a_bool_t * enable) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _garuda_port_igmp_mld_join_get(dev_id, port_id, enable); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Set igmp/mld leave packets hardware acknowledgement status on a particular port. - * @details Comments: - * After enabling igmp join feature on a particular port hardware will dynamic - * deleting or changing multicast entry. - * @param[in] dev_id device id - * @param[in] port_id port id - * @param[in] enable A_TRUE or A_FALSE - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -garuda_port_igmp_mld_leave_set(a_uint32_t dev_id, fal_port_t port_id, a_bool_t enable) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _garuda_port_igmp_mld_leave_set(dev_id, port_id, enable); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Get igmp/mld leave packets hardware acknowledgement status on a particular port. - * @param[in] dev_id device id - * @param[in] port_id port id - * @param[out] enable A_TRUE or A_FALSE - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -garuda_port_igmp_mld_leave_get(a_uint32_t dev_id, fal_port_t port_id, a_bool_t * enable) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _garuda_port_igmp_mld_leave_get(dev_id, port_id, enable); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Set igmp/mld router ports on a particular device. - * @details Comments: - * After enabling igmp/mld join/leave feature on a particular port igmp/mld - * join/leave packets received on this port will be forwarded to router ports. - * @param[in] dev_id device id - * @param[in] pts dedicates ports - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -garuda_igmp_mld_rp_set(a_uint32_t dev_id, fal_pbmp_t pts) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _garuda_igmp_mld_rp_set(dev_id, pts); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Get igmp/mld router ports on a particular device. - * @param[in] dev_id device id - * @param[out] pts dedicates ports - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -garuda_igmp_mld_rp_get(a_uint32_t dev_id, fal_pbmp_t * pts) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _garuda_igmp_mld_rp_get(dev_id, pts); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Set the status of creating multicast entry during igmp/mld join/leave procedure. - * @details Comments: - * After enabling igmp/mld join/leave feature on a particular port if enable - * entry creat hardware will dynamic creat and delete multicast entry, - * otherwise hardware only can change destination ports of existing muticast entry. - * @param[in] dev_id device id - * @param[in] enable A_TRUE or A_FALSE - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -garuda_igmp_mld_entry_creat_set(a_uint32_t dev_id, a_bool_t enable) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _garuda_igmp_mld_entry_creat_set(dev_id, enable); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Get the status of creating multicast entry during igmp/mld join/leave procedure. - * @param[in] dev_id device id - * @param[out] enable A_TRUE or A_FALSE - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -garuda_igmp_mld_entry_creat_get(a_uint32_t dev_id, a_bool_t * enable) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _garuda_igmp_mld_entry_creat_get(dev_id, enable); - HSL_API_UNLOCK; - return rv; -} - -sw_error_t -garuda_igmp_init(a_uint32_t dev_id) -{ - HSL_DEV_ID_CHECK(dev_id); - -#ifndef HSL_STANDALONG - { - hsl_api_t *p_api; - - SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id)); - - p_api->port_igmps_status_set = garuda_port_igmps_status_set; - p_api->port_igmps_status_get = garuda_port_igmps_status_get; - p_api->igmp_mld_cmd_set = garuda_igmp_mld_cmd_set; - p_api->igmp_mld_cmd_get = garuda_igmp_mld_cmd_get; - p_api->port_igmp_join_set = garuda_port_igmp_mld_join_set; - p_api->port_igmp_join_get = garuda_port_igmp_mld_join_get; - p_api->port_igmp_leave_set = garuda_port_igmp_mld_leave_set; - p_api->port_igmp_leave_get = garuda_port_igmp_mld_leave_get; - p_api->igmp_rp_set = garuda_igmp_mld_rp_set; - p_api->igmp_rp_get = garuda_igmp_mld_rp_get; - p_api->igmp_entry_creat_set = garuda_igmp_mld_entry_creat_set; - p_api->igmp_entry_creat_get = garuda_igmp_mld_entry_creat_get; - } -#endif - - return SW_OK; -} - -/** - * @} - */ - diff --git a/feeds/ipq807x/qca-ssdk/src/src/hsl/garuda/garuda_init.c b/feeds/ipq807x/qca-ssdk/src/src/hsl/garuda/garuda_init.c deleted file mode 100755 index eeef514c5..000000000 --- a/feeds/ipq807x/qca-ssdk/src/src/hsl/garuda/garuda_init.c +++ /dev/null @@ -1,642 +0,0 @@ -/* - * Copyright (c) 2012, 2017, The Linux Foundation. All rights reserved. - * Permission to use, copy, modify, and/or distribute this software for - * any purpose with or without fee is hereby granted, provided that the - * above copyright notice and this permission notice appear in all copies. - * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES - * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR - * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES - * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN - * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT - * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. - */ - - -/** - * @defgroup garuda_init GARUDA_INIT - * @{ - */ -#include "sw.h" -#include "hsl.h" -#include "hsl_dev.h" -#include "hsl_port_prop.h" -#include "garuda_mib.h" -#include "garuda_port_ctrl.h" -#include "garuda_portvlan.h" -#include "garuda_vlan.h" -#include "garuda_fdb.h" -#include "garuda_qos.h" -#include "garuda_mirror.h" -#include "garuda_stp.h" -#include "garuda_rate.h" -#include "garuda_misc.h" -#include "garuda_leaky.h" -#include "garuda_igmp.h" -#include "garuda_acl.h" -#include "garuda_led.h" -#include "garuda_reg_access.h" -#include "garuda_reg.h" -#include "garuda_init.h" -#include "f1_phy.h" - -static ssdk_init_cfg * garuda_cfg[SW_MAX_NR_DEV] = { 0 }; - -#if !(defined(KERNEL_MODULE) && defined(USER_MODE)) -static sw_error_t -garuda_portproperty_init(a_uint32_t dev_id, hsl_init_mode mode) -{ - hsl_port_prop_t p_type; - hsl_dev_t *pdev = NULL; - fal_port_t port_id; - - pdev = hsl_dev_ptr_get(dev_id); - if (pdev == NULL) - return SW_NOT_INITIALIZED; - - for (port_id = 0; port_id < pdev->nr_ports; port_id++) - { - hsl_port_prop_portmap_set(dev_id, port_id); - - for (p_type = HSL_PP_PHY; p_type < HSL_PP_BUTT; p_type++) - { - if (HSL_NO_CPU == mode) - { - SW_RTN_ON_ERROR(hsl_port_prop_set(dev_id, port_id, p_type)); - continue; - } - - switch (p_type) - { - case HSL_PP_PHY: - if (HSL_CPU_1 != mode) - { - if ((port_id != pdev->cpu_port_nr) - && (port_id != (pdev->nr_ports -1))) - { - SW_RTN_ON_ERROR(hsl_port_prop_set(dev_id, port_id, p_type)); - } - } - else - { - if (port_id != pdev->cpu_port_nr) - { - SW_RTN_ON_ERROR(hsl_port_prop_set(dev_id, port_id, p_type)); - } - } - break; - - case HSL_PP_INCL_CPU: - /* include cpu port but exclude wan port in some cases */ - if (!((HSL_CPU_2 == mode) && (port_id == (pdev->nr_ports - 1)))) - SW_RTN_ON_ERROR(hsl_port_prop_set(dev_id, port_id, p_type)); - - break; - - case HSL_PP_EXCL_CPU: - /* exclude cpu port and wan port in some cases */ - if ((port_id != pdev->cpu_port_nr) - && (!((HSL_CPU_2 == mode) && (port_id == (pdev->nr_ports - 1))))) - SW_RTN_ON_ERROR(hsl_port_prop_set(dev_id, port_id, p_type)); - break; - - default: - break; - } - } - - if (HSL_NO_CPU == mode) - { - SW_RTN_ON_ERROR(hsl_port_prop_set_phyid - (dev_id, port_id, port_id + 1)); - } - else - { - if (port_id != pdev->cpu_port_nr) - { - SW_RTN_ON_ERROR(hsl_port_prop_set_phyid - (dev_id, port_id, port_id - 1)); - } - } - } - - return SW_OK; -} - -static void -phy_dport_set(a_uint32_t dev_id, a_uint32_t phy_id, a_uint32_t dport_addr, a_uint16_t val_mask) -{ - a_uint16_t phy_data; - sw_error_t rv; - - HSL_PHY_SET(rv, dev_id, phy_id, F1_DEBUG_PORT_ADDRESS, dport_addr); - HSL_PHY_GET(rv, dev_id, phy_id, F1_DEBUG_PORT_DATA, &phy_data); - phy_data |= val_mask; - HSL_PHY_SET(rv, dev_id, phy_id, F1_DEBUG_PORT_DATA, phy_data); -} - -static void -phy_dport_clear(a_uint32_t dev_id, a_uint32_t phy_id, a_uint32_t dport_addr, a_uint16_t val_mask) -{ - a_uint16_t phy_data; - sw_error_t rv; - - HSL_PHY_SET(rv, dev_id, phy_id, F1_DEBUG_PORT_ADDRESS, dport_addr); - HSL_PHY_GET(rv, dev_id, phy_id, F1_DEBUG_PORT_DATA, &phy_data); - phy_data &= ~val_mask; - HSL_PHY_SET(rv, dev_id, phy_id, F1_DEBUG_PORT_DATA, phy_data); -} - -static sw_error_t -garuda_hw_init(a_uint32_t dev_id, ssdk_init_cfg *cfg) -{ - garuda_init_spec_cfg *garuda_init_cfg = NULL; - hsl_dev_t *pdev = NULL; - hsl_init_mode cpu_mode; - a_uint32_t port_id; - a_uint32_t data; - sw_error_t rv; - - pdev = hsl_dev_ptr_get(dev_id); - if (NULL == pdev) - { - return SW_NOT_INITIALIZED; - } - cpu_mode = cfg->cpu_mode; - - HSL_REG_ENTRY_GET(rv, dev_id, POSTRIP, 0, - (a_uint8_t *) (&data), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - - /* phy pll on */ - SW_SET_REG_BY_FIELD(POSTRIP, PHY_PLL_ON, 1, data); - - garuda_init_cfg = (garuda_init_spec_cfg* )(cfg->chip_spec_cfg); - if (!garuda_init_cfg) - { - return SW_BAD_PARAM; - } - - /* delay */ - if (A_TRUE == garuda_init_cfg->rx_delay_s1) - { - SW_SET_REG_BY_FIELD(POSTRIP, RXDELAY_S1, 1, data); - } - else - { - SW_SET_REG_BY_FIELD(POSTRIP, RXDELAY_S1, 0, data); - } - - if (A_TRUE == garuda_init_cfg->rx_delay_s0) - { - SW_SET_REG_BY_FIELD(POSTRIP, RXDELAY_S0, 1, data); - } - else - { - SW_SET_REG_BY_FIELD(POSTRIP, RXDELAY_S0, 0, data); - } - - if (A_TRUE == garuda_init_cfg->tx_delay_s1) - { - SW_SET_REG_BY_FIELD(POSTRIP, TXDELAY_S1, 1, data); - } - else - { - SW_SET_REG_BY_FIELD(POSTRIP, TXDELAY_S1, 0, data); - } - - if (A_TRUE == garuda_init_cfg->tx_delay_s0) - { - SW_SET_REG_BY_FIELD(POSTRIP, TXDELAY_S0, 1, data); - } - else - { - SW_SET_REG_BY_FIELD(POSTRIP, TXDELAY_S0, 0, data); - } - - /* tx/rx delay enable */ - if (A_TRUE == garuda_init_cfg->rgmii_txclk_delay) - { - SW_SET_REG_BY_FIELD(POSTRIP, RGMII_TXCLK_DELAY_EN, 1, data); - } - else - { - SW_SET_REG_BY_FIELD(POSTRIP, RGMII_TXCLK_DELAY_EN, 0, data); - } - - /* tx/rx delay enable */ - if (A_TRUE == garuda_init_cfg->rgmii_rxclk_delay) - { - SW_SET_REG_BY_FIELD(POSTRIP, RGMII_RXCLK_DELAY_EN, 1, data); - } - else - { - SW_SET_REG_BY_FIELD(POSTRIP, RGMII_RXCLK_DELAY_EN, 0, data); - } - - /* mac5 default mode */ - /*SW_SET_REG_BY_FIELD(POSTRIP, MAC5_PHY_MODE, 0, data); - SW_SET_REG_BY_FIELD(POSTRIP, MAC5_MAC_MODE, 0, data);*/ - - /* mac0 default phy mode */ - SW_SET_REG_BY_FIELD(POSTRIP, MAC0_MAC_MODE, 0, data); - - /* mac0 default rgmii mode */ - SW_SET_REG_BY_FIELD(POSTRIP, MAC0_RGMII_EN, 1, data); - SW_SET_REG_BY_FIELD(POSTRIP, MAC0_GMII_EN, 0, data); - - /* mac5 default disable mode */ - SW_SET_REG_BY_FIELD(POSTRIP, MAC5_PHY_MODE, 0, data); - SW_SET_REG_BY_FIELD(POSTRIP, MAC5_MAC_MODE, 0, data); - - /* phy default mode */ - SW_SET_REG_BY_FIELD(POSTRIP, PHY4_RGMII_EN, 0, data); - SW_SET_REG_BY_FIELD(POSTRIP, PHY4_GMII_EN, 0, data); - - /* modify default mode */ - if (A_FALSE == garuda_init_cfg->mac0_rgmii) - { - SW_SET_REG_BY_FIELD(POSTRIP, MAC0_RGMII_EN, 0, data); - SW_SET_REG_BY_FIELD(POSTRIP, MAC0_GMII_EN, 1, data); - - /*invert clock output for port0 gmii pad.*/ - a_uint32_t temp; - HSL_REG_ENTRY_GET(rv, dev_id, MASK_CTL, 0, - (a_uint8_t *) (&temp), sizeof (a_uint32_t)); - temp |= 1<mac5_rgmii) - { - - SW_SET_REG_BY_FIELD(POSTRIP, PHY4_RGMII_EN, 1, data); - SW_SET_REG_BY_FIELD(POSTRIP, PHY4_GMII_EN, 0, data); - - a_uint32_t phy_id = 4; - /* phy4 rgmii mode enable */ - phy_dport_set(dev_id, phy_id, F1_DEBUG_PORT_RGMII_MODE, F1_DEBUG_PORT_RGMII_MODE_EN); - - /* Rx delay enable */ - if (A_TRUE == garuda_init_cfg->phy4_rx_delay) - { - phy_dport_set(dev_id, phy_id, F1_DEBUG_PORT_RX_DELAY, F1_DEBUG_PORT_RX_DELAY_EN); - } - else - { - phy_dport_clear(dev_id, phy_id, F1_DEBUG_PORT_RX_DELAY, F1_DEBUG_PORT_RX_DELAY_EN); - } - - /* Tx delay enable */ - if (A_TRUE == garuda_init_cfg->phy4_tx_delay) - { - phy_dport_set(dev_id, phy_id, F1_DEBUG_PORT_TX_DELAY, F1_DEBUG_PORT_TX_DELAY_EN); - } - else - { - phy_dport_clear(dev_id, phy_id, F1_DEBUG_PORT_TX_DELAY, F1_DEBUG_PORT_TX_DELAY_EN); - } - - } - else - { - SW_SET_REG_BY_FIELD(POSTRIP, PHY4_RGMII_EN, 0, data); - SW_SET_REG_BY_FIELD(POSTRIP, PHY4_GMII_EN, 1, data); - } - } - else if (HSL_CPU_1 == cpu_mode) - { - //SW_SET_REG_BY_FIELD(POSTRIP, TXDELAY_S0, 0, data); - - } - else if (HSL_CPU_1_PLUS == cpu_mode) - { - SW_SET_REG_BY_FIELD(POSTRIP, MAC5_MAC_MODE, 1, data); - - } - else if (HSL_NO_CPU == cpu_mode) - { - - } - - HSL_REG_ENTRY_SET(rv, dev_id, POSTRIP, 0, - (a_uint8_t *) (&data), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - - for (port_id = 0; port_id < pdev->nr_ports; port_id++) - { - if (port_id == pdev->cpu_port_nr) - { - continue; - } - - HSL_REG_ENTRY_GET(rv, dev_id, PORT_STATUS, port_id, - (a_uint8_t *) (&data), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - - SW_SET_REG_BY_FIELD(PORT_STATUS, LINK_EN, 1, data); - - HSL_REG_ENTRY_SET(rv, dev_id, PORT_STATUS, port_id, - (a_uint8_t *) (&data), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - } - - return SW_OK; -} - -static sw_error_t -garuda_bist_test(a_uint32_t dev_id) -{ - a_uint32_t entry, data, i; - sw_error_t rv; - - data = 1; - i = 0x1000; - while (data && --i) - { - HSL_REG_ENTRY_GET(rv, dev_id, BIST_CTRL, 0, - (a_uint8_t *) (&entry), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - SW_GET_FIELD_BY_REG(BIST_CTRL, BIST_BUSY, data, entry); - aos_udelay(5); - } - - if (0 == i) - { - return SW_INIT_ERROR; - } - - entry = 0; - SW_SET_REG_BY_FIELD(BIST_CTRL, BIST_BUSY, 1, entry); - SW_SET_REG_BY_FIELD(BIST_CTRL, PTN_EN2, 1, entry); - SW_SET_REG_BY_FIELD(BIST_CTRL, PTN_EN1, 1, entry); - SW_SET_REG_BY_FIELD(BIST_CTRL, PTN_EN0, 1, entry); - - HSL_REG_ENTRY_SET(rv, dev_id, BIST_CTRL, 0, - (a_uint8_t *) (&entry), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - - data = 1; - i = 0x1000; - while (data && --i) - { - HSL_REG_ENTRY_GET(rv, dev_id, BIST_CTRL, 0, - (a_uint8_t *) (&entry), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - SW_GET_FIELD_BY_REG(BIST_CTRL, BIST_BUSY, data, entry); - aos_udelay(5); - } - - if (0 == i) - { - return SW_INIT_ERROR; - } - - SW_GET_FIELD_BY_REG(BIST_CTRL, ERR_CNT, data, entry); - if (data) - { - SW_GET_FIELD_BY_REG(BIST_CTRL, ONE_ERR, data, entry); - if (!data) - { - return SW_INIT_ERROR; - } - - SW_GET_FIELD_BY_REG(BIST_CTRL, ERR_ADDR, data, entry); - - entry = 0; - SW_SET_REG_BY_FIELD(BIST_RCV, RCV_EN, 1, entry); - SW_SET_REG_BY_FIELD(BIST_RCV, RCV_ADDR, data, entry); - HSL_REG_ENTRY_SET(rv, dev_id, BIST_RCV, 0, - (a_uint8_t *) (&entry), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - } - else - { - return SW_OK; - } - - entry = 0; - SW_SET_REG_BY_FIELD(BIST_CTRL, BIST_BUSY, 1, entry); - SW_SET_REG_BY_FIELD(BIST_CTRL, PTN_EN2, 1, entry); - SW_SET_REG_BY_FIELD(BIST_CTRL, PTN_EN1, 1, entry); - SW_SET_REG_BY_FIELD(BIST_CTRL, PTN_EN0, 1, entry); - - HSL_REG_ENTRY_SET(rv, dev_id, BIST_CTRL, 0, - (a_uint8_t *) (&entry), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - - data = 1; - i = 0x1000; - while (data && --i) - { - HSL_REG_ENTRY_GET(rv, dev_id, BIST_CTRL, 0, - (a_uint8_t *) (&entry), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - SW_GET_FIELD_BY_REG(BIST_CTRL, BIST_BUSY, data, entry); - aos_udelay(5); - } - - if (0 == i) - { - return SW_INIT_ERROR; - } - - SW_GET_FIELD_BY_REG(BIST_CTRL, ERR_CNT, data, entry); - if (data) - { - return SW_INIT_ERROR; - } - - return SW_OK; -} - - -#endif - -static sw_error_t -garuda_dev_init(a_uint32_t dev_id, hsl_init_mode cpu_mode) -{ - hsl_dev_t *pdev = NULL; - - pdev = hsl_dev_ptr_get(dev_id); - if (pdev == NULL) - return SW_NOT_INITIALIZED; - - pdev->nr_ports = 6; - pdev->nr_phy = 5; - pdev->cpu_port_nr = 0; - pdev->nr_vlans = 4096; - pdev->hw_vlan_query = A_TRUE; - pdev->nr_queue = 4; - pdev->cpu_mode = cpu_mode; - - return SW_OK; -} - -static sw_error_t -_garuda_reset(a_uint32_t dev_id) -{ -#if !(defined(KERNEL_MODULE) && defined(USER_MODE)) - sw_error_t rv; - a_uint32_t val; - - HSL_DEV_ID_CHECK(dev_id); - - val = 0x1; - HSL_REG_FIELD_SET(rv, dev_id, MASK_CTL, 0, SOFT_RST, - (a_uint8_t *) (&val), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - - rv = garuda_hw_init(dev_id, garuda_cfg[dev_id]); - SW_RTN_ON_ERROR(rv); - - GARUDA_ACL_RESET(rv, dev_id); -#endif - - return SW_OK; -} - -sw_error_t -garuda_cleanup(a_uint32_t dev_id) -{ - if (garuda_cfg[dev_id]) - { - aos_mem_free(garuda_cfg[dev_id]); - garuda_cfg[dev_id] = NULL; - } - - return SW_OK; -} - -/** - * @brief reset hsl layer. - * @details Comments: - * This operation will reset hsl layer - * @param[in] dev_id device id - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -garuda_reset(a_uint32_t dev_id) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _garuda_reset(dev_id); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Init hsl layer. - * @details Comments: - * This operation will init hsl layer and hsl layer - * @param[in] dev_id device id - * @param[in] cfg configuration for initialization - * @return SW_OK or error code - */ -sw_error_t -garuda_init(a_uint32_t dev_id, ssdk_init_cfg *cfg) -{ - a_uint8_t *p_mem; - - HSL_DEV_ID_CHECK(dev_id); - - p_mem = (a_uint8_t *)garuda_cfg[dev_id]; - if (NULL == p_mem) - { - p_mem = aos_mem_alloc(sizeof (ssdk_init_cfg) - + sizeof(garuda_init_spec_cfg)); - garuda_cfg[dev_id] = (ssdk_init_cfg *)p_mem; - garuda_cfg[dev_id]->chip_spec_cfg = (garuda_init_spec_cfg *) - (p_mem + sizeof (ssdk_init_cfg)); - } - - if (NULL == p_mem) - { - return SW_OUT_OF_MEM; - } - - aos_mem_copy(garuda_cfg[dev_id]->chip_spec_cfg, - cfg->chip_spec_cfg, sizeof (garuda_init_spec_cfg)); - aos_mem_copy(garuda_cfg[dev_id], cfg, sizeof (ssdk_init_cfg)); - garuda_cfg[dev_id]->chip_spec_cfg = (garuda_init_spec_cfg *) - (p_mem + sizeof (ssdk_init_cfg)); - - SW_RTN_ON_ERROR(garuda_reg_access_init(dev_id, cfg->reg_mode)); - - SW_RTN_ON_ERROR(garuda_dev_init(dev_id, cfg->cpu_mode)); - -#if !(defined(KERNEL_MODULE) && defined(USER_MODE)) - { - a_uint32_t i, entry; - sw_error_t rv; - - if(HSL_MDIO == cfg->reg_mode) - { - SW_RTN_ON_ERROR(garuda_bist_test(dev_id)); - - entry = 0x1; - HSL_REG_FIELD_SET(rv, dev_id, MASK_CTL, 0, SOFT_RST, - (a_uint8_t *) (&entry), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - - i = 0x10; - do - { - HSL_REG_FIELD_GET(rv, dev_id, MASK_CTL, 0, SOFT_RST, - (a_uint8_t *) (&entry), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - - aos_mdelay(10); - } - while (entry && --i); - - if (0 == i) - { - return SW_INIT_ERROR; - } - } - SW_RTN_ON_ERROR(hsl_port_prop_init(dev_id)); - SW_RTN_ON_ERROR(hsl_port_prop_init_by_dev(dev_id)); - SW_RTN_ON_ERROR(garuda_portproperty_init(dev_id, cfg->cpu_mode)); - - GARUDA_MIB_INIT(rv, dev_id); - GARUDA_PORT_CTRL_INIT(rv, dev_id); - GARUDA_PORTVLAN_INIT(rv, dev_id); - GARUDA_VLAN_INIT(rv, dev_id); - GARUDA_FDB_INIT(rv, dev_id); - GARUDA_QOS_INIT(rv, dev_id); - GARUDA_STP_INIT(rv, dev_id); - GARUDA_MIRR_INIT(rv, dev_id); - GARUDA_RATE_INIT(rv, dev_id); - GARUDA_MISC_INIT(rv, dev_id); - GARUDA_LEAKY_INIT(rv, dev_id); - GARUDA_IGMP_INIT(rv, dev_id); - GARUDA_ACL_INIT(rv, dev_id); - GARUDA_LED_INIT(rv, dev_id); - - { - hsl_api_t *p_api; - - SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id)); - p_api->dev_reset = garuda_reset; - p_api->dev_clean = garuda_cleanup; - } - - if(cfg->reg_mode == HSL_MDIO) - { - SW_RTN_ON_ERROR(garuda_hw_init(dev_id, cfg)); - } - } -#endif - - return SW_OK; -} - -/** - * @} - */ - diff --git a/feeds/ipq807x/qca-ssdk/src/src/hsl/garuda/garuda_leaky.c b/feeds/ipq807x/qca-ssdk/src/src/hsl/garuda/garuda_leaky.c deleted file mode 100755 index 5969fa189..000000000 --- a/feeds/ipq807x/qca-ssdk/src/src/hsl/garuda/garuda_leaky.c +++ /dev/null @@ -1,531 +0,0 @@ -/* - * Copyright (c) 2012, The Linux Foundation. All rights reserved. - * Permission to use, copy, modify, and/or distribute this software for - * any purpose with or without fee is hereby granted, provided that the - * above copyright notice and this permission notice appear in all copies. - * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES - * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR - * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES - * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN - * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT - * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. - */ - - - -/** - * @defgroup garuda_leaky GARUDA_LEAKY - * @{ - */ -#include "sw.h" -#include "hsl.h" -#include "hsl_dev.h" -#include "hsl_port_prop.h" -#include "garuda_leaky.h" -#include "garuda_reg.h" - -static sw_error_t -_garuda_uc_leaky_mode_set(a_uint32_t dev_id, - fal_leaky_ctrl_mode_t ctrl_mode) -{ - a_uint32_t data; - sw_error_t rv; - - HSL_DEV_ID_CHECK(dev_id); - - if (FAL_LEAKY_PORT_CTRL == ctrl_mode) - { - data = 0; - } - else if (FAL_LEAKY_FDB_CTRL == ctrl_mode) - { - data = 1; - } - else - { - return SW_BAD_PARAM; - } - - HSL_REG_FIELD_SET(rv, dev_id, FLOOD_MASK, 0, ARL_UNI_LEAKY, - (a_uint8_t *) (&data), sizeof (a_uint32_t)); - return rv; -} - -static sw_error_t -_garuda_uc_leaky_mode_get(a_uint32_t dev_id, - fal_leaky_ctrl_mode_t *ctrl_mode) -{ - a_uint32_t data; - sw_error_t rv; - - HSL_DEV_ID_CHECK(dev_id); - - HSL_REG_FIELD_GET(rv, dev_id, FLOOD_MASK, 0, ARL_UNI_LEAKY, - (a_uint8_t *) (&data), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - - if (1 == data) - { - *ctrl_mode = FAL_LEAKY_FDB_CTRL; - } - else - { - *ctrl_mode = FAL_LEAKY_PORT_CTRL; - } - - return SW_OK; -} - -static sw_error_t -_garuda_mc_leaky_mode_set(a_uint32_t dev_id, - fal_leaky_ctrl_mode_t ctrl_mode) -{ - a_uint32_t data; - sw_error_t rv; - - HSL_DEV_ID_CHECK(dev_id); - - if (FAL_LEAKY_PORT_CTRL == ctrl_mode) - { - data = 0; - } - else if (FAL_LEAKY_FDB_CTRL == ctrl_mode) - { - data = 1; - } - else - { - return SW_BAD_PARAM; - } - - HSL_REG_FIELD_SET(rv, dev_id, FLOOD_MASK, 0, ARL_MUL_LEAKY, - (a_uint8_t *) (&data), sizeof (a_uint32_t)); - return rv; -} - - - -static sw_error_t -_garuda_mc_leaky_mode_get(a_uint32_t dev_id, - fal_leaky_ctrl_mode_t *ctrl_mode) -{ - a_uint32_t data; - sw_error_t rv; - - HSL_DEV_ID_CHECK(dev_id); - - HSL_REG_FIELD_GET(rv, dev_id, FLOOD_MASK, 0, ARL_MUL_LEAKY, - (a_uint8_t *) (&data), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - - if (1 == data) - { - *ctrl_mode = FAL_LEAKY_FDB_CTRL; - } - else - { - *ctrl_mode = FAL_LEAKY_PORT_CTRL; - } - - return SW_OK; -} - - -static sw_error_t -_garuda_port_arp_leaky_set(a_uint32_t dev_id, fal_port_t port_id, - a_bool_t enable) -{ - a_uint32_t data; - sw_error_t rv; - - HSL_DEV_ID_CHECK(dev_id); - - if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU)) - { - return SW_BAD_PARAM; - } - - if (A_TRUE == enable) - { - data = 1; - } - else if (A_FALSE == enable) - { - data = 0; - } - else - { - return SW_BAD_PARAM; - } - - HSL_REG_FIELD_SET(rv, dev_id, PORT_BASE_VLAN, port_id, ARP_LEAKY_EN, - (a_uint8_t *) (&data), sizeof (a_uint32_t)); - return rv; -} - - -static sw_error_t -_garuda_port_arp_leaky_get(a_uint32_t dev_id, fal_port_t port_id, - a_bool_t *enable) -{ - a_uint32_t data; - sw_error_t rv; - - HSL_DEV_ID_CHECK(dev_id); - - if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU)) - { - return SW_BAD_PARAM; - } - - HSL_REG_FIELD_GET(rv, dev_id, PORT_BASE_VLAN, port_id, ARP_LEAKY_EN, - (a_uint8_t *) (&data), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - - if (1 == data) - { - *enable = A_TRUE; - } - else - { - *enable = A_FALSE; - } - - return SW_OK; -} - -static sw_error_t -_garuda_port_uc_leaky_set(a_uint32_t dev_id, fal_port_t port_id, - a_bool_t enable) -{ - a_uint32_t data; - sw_error_t rv; - - HSL_DEV_ID_CHECK(dev_id); - - if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU)) - { - return SW_BAD_PARAM; - } - - if (A_TRUE == enable) - { - data = 1; - } - else if (A_FALSE == enable) - { - data = 0; - } - else - { - return SW_BAD_PARAM; - } - - HSL_REG_FIELD_SET(rv, dev_id, PORT_BASE_VLAN, port_id, UNI_LEAKY_EN, - (a_uint8_t *) (&data), sizeof (a_uint32_t)); - return rv; -} - -static sw_error_t -_garuda_port_uc_leaky_get(a_uint32_t dev_id, fal_port_t port_id, - a_bool_t *enable) -{ - a_uint32_t data; - sw_error_t rv; - - HSL_DEV_ID_CHECK(dev_id); - - if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU)) - { - return SW_BAD_PARAM; - } - - HSL_REG_FIELD_GET(rv, dev_id, PORT_BASE_VLAN, port_id, UNI_LEAKY_EN, - (a_uint8_t *) (&data), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - - if (1 == data) - { - *enable = A_TRUE; - } - else - { - *enable = A_FALSE; - } - - return SW_OK; -} - -static sw_error_t -_garuda_port_mc_leaky_set(a_uint32_t dev_id, fal_port_t port_id, - a_bool_t enable) -{ - a_uint32_t data; - sw_error_t rv; - - HSL_DEV_ID_CHECK(dev_id); - - if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU)) - { - return SW_BAD_PARAM; - } - - if (A_TRUE == enable) - { - data = 1; - } - else if (A_FALSE == enable) - { - data = 0; - } - else - { - return SW_BAD_PARAM; - } - - HSL_REG_FIELD_SET(rv, dev_id, PORT_BASE_VLAN, port_id, MUL_LEAKY_EN, - (a_uint8_t *) (&data), sizeof (a_uint32_t)); - return rv; -} - -static sw_error_t -_garuda_port_mc_leaky_get(a_uint32_t dev_id, fal_port_t port_id, - a_bool_t *enable) -{ - a_uint32_t data; - sw_error_t rv; - - HSL_DEV_ID_CHECK(dev_id); - - if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU)) - { - return SW_BAD_PARAM; - } - - HSL_REG_FIELD_GET(rv, dev_id, PORT_BASE_VLAN, port_id, MUL_LEAKY_EN, - (a_uint8_t *) (&data), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - - if (1 == data) - { - *enable = A_TRUE; - } - else - { - *enable = A_FALSE; - } - - return SW_OK; -} - -/** -* @brief Set unicast packets leaky control mode on a particular device. -* @param[in] dev_id device id -* @param[in] ctrl_mode leaky control mode -* @return SW_OK or error code -*/ -HSL_LOCAL sw_error_t -garuda_uc_leaky_mode_set(a_uint32_t dev_id, - fal_leaky_ctrl_mode_t ctrl_mode) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _garuda_uc_leaky_mode_set(dev_id, ctrl_mode); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Get unicast packets leaky control mode on a particular device. - * @param[in] dev_id device id - * @param[out] ctrl_mode leaky control mode - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -garuda_uc_leaky_mode_get(a_uint32_t dev_id, - fal_leaky_ctrl_mode_t *ctrl_mode) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _garuda_uc_leaky_mode_get(dev_id, ctrl_mode); - HSL_API_UNLOCK; - return rv; -} - -/** -* @brief Set multicast packets leaky control mode on a particular device. -* @param[in] dev_id device id -* @param[in] ctrl_mode leaky control mode -* @return SW_OK or error code -*/ -HSL_LOCAL sw_error_t -garuda_mc_leaky_mode_set(a_uint32_t dev_id, - fal_leaky_ctrl_mode_t ctrl_mode) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _garuda_mc_leaky_mode_set(dev_id, ctrl_mode); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Get multicast packets leaky control mode on a particular device. - * @param[in] dev_id device id - * @param[out] ctrl_mode leaky control mode - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -garuda_mc_leaky_mode_get(a_uint32_t dev_id, - fal_leaky_ctrl_mode_t *ctrl_mode) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _garuda_mc_leaky_mode_get(dev_id, ctrl_mode); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Set arp packets leaky status on a particular port. - * @param[in] dev_id device id - * @param[in] enable A_TRUE or A_FALSE - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -garuda_port_arp_leaky_set(a_uint32_t dev_id, fal_port_t port_id, - a_bool_t enable) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _garuda_port_arp_leaky_set(dev_id, port_id, enable); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Get arp packets leaky status on a particular port. - * @param[in] dev_id device id - * @param[out] enable A_TRUE or A_FALSE - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -garuda_port_arp_leaky_get(a_uint32_t dev_id, fal_port_t port_id, - a_bool_t *enable) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _garuda_port_arp_leaky_get(dev_id, port_id, enable); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Set unicast packets leaky status on a particular port. - * @param[in] dev_id device id - * @param[in] enable A_TRUE or A_FALSE - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -garuda_port_uc_leaky_set(a_uint32_t dev_id, fal_port_t port_id, - a_bool_t enable) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _garuda_port_uc_leaky_set(dev_id, port_id, enable); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Get unicast packets leaky status on a particular port. - * @param[in] dev_id device id - * @param[out] enable A_TRUE or A_FALSE - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -garuda_port_uc_leaky_get(a_uint32_t dev_id, fal_port_t port_id, - a_bool_t *enable) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _garuda_port_uc_leaky_get(dev_id, port_id, enable); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Set multicast packets leaky status on a particular port. - * @param[in] dev_id device id - * @param[in] enable A_TRUE or A_FALSE - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -garuda_port_mc_leaky_set(a_uint32_t dev_id, fal_port_t port_id, - a_bool_t enable) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _garuda_port_mc_leaky_set(dev_id, port_id, enable); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Get multicast packets leaky status on a particular port. - * @param[in] dev_id device id - * @param[out] enable A_TRUE or A_FALSE - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -garuda_port_mc_leaky_get(a_uint32_t dev_id, fal_port_t port_id, - a_bool_t *enable) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _garuda_port_mc_leaky_get(dev_id, port_id, enable); - HSL_API_UNLOCK; - return rv; -} - -sw_error_t -garuda_leaky_init(a_uint32_t dev_id) -{ - HSL_DEV_ID_CHECK(dev_id); - -#ifndef HSL_STANDALONG - { - hsl_api_t *p_api; - - SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id)); - p_api->uc_leaky_mode_set = garuda_uc_leaky_mode_set; - p_api->uc_leaky_mode_get = garuda_uc_leaky_mode_get; - p_api->mc_leaky_mode_set = garuda_mc_leaky_mode_set; - p_api->mc_leaky_mode_get = garuda_mc_leaky_mode_get; - p_api->port_arp_leaky_set = garuda_port_arp_leaky_set; - p_api->port_arp_leaky_get = garuda_port_arp_leaky_get; - p_api->port_uc_leaky_set = garuda_port_uc_leaky_set; - p_api->port_uc_leaky_get = garuda_port_uc_leaky_get; - p_api->port_mc_leaky_set = garuda_port_mc_leaky_set; - p_api->port_mc_leaky_get = garuda_port_mc_leaky_get; - } -#endif - - return SW_OK; -} - -/** - * @} - */ - diff --git a/feeds/ipq807x/qca-ssdk/src/src/hsl/garuda/garuda_led.c b/feeds/ipq807x/qca-ssdk/src/src/hsl/garuda/garuda_led.c deleted file mode 100755 index f69b2a97b..000000000 --- a/feeds/ipq807x/qca-ssdk/src/src/hsl/garuda/garuda_led.c +++ /dev/null @@ -1,370 +0,0 @@ -/* - * Copyright (c) 2012, The Linux Foundation. All rights reserved. - * Permission to use, copy, modify, and/or distribute this software for - * any purpose with or without fee is hereby granted, provided that the - * above copyright notice and this permission notice appear in all copies. - * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES - * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR - * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES - * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN - * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT - * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. - */ - - - -/** - * @defgroup garuda_led GARUDA_LED - * @{ - */ - -#include "sw.h" -#include "hsl.h" -#include "hsl_dev.h" -#include "garuda_led.h" -#include "garuda_reg.h" - -#define MAX_LED_PATTERN_ID 2 -#define LED_PATTERN_ADDR 0xB0 - - -static sw_error_t -_garuda_led_ctrl_pattern_set(a_uint32_t dev_id, led_pattern_group_t group, - led_pattern_id_t id, led_ctrl_pattern_t * pattern) -{ - a_uint32_t data = 0, reg; - a_uint32_t addr; - sw_error_t rv; - - HSL_DEV_ID_CHECK(dev_id); - - if ((LED_LAN_PORT_GROUP != group) && (LED_WAN_PORT_GROUP != group)) - { - return SW_NOT_SUPPORTED; - } - - if (id > MAX_LED_PATTERN_ID) - { - return SW_BAD_PARAM; - } - - addr = LED_PATTERN_ADDR + (id << 2); - - if (LED_ALWAYS_OFF == pattern->mode) - { - SW_SET_REG_BY_FIELD(LED_CTRL, PATTERN_EN, 0, data); - } - else if (LED_ALWAYS_BLINK == pattern->mode) - { - SW_SET_REG_BY_FIELD(LED_CTRL, PATTERN_EN, 1, data); - } - else if (LED_ALWAYS_ON == pattern->mode) - { - SW_SET_REG_BY_FIELD(LED_CTRL, PATTERN_EN, 2, data); - } - else if (LED_PATTERN_MAP_EN == pattern->mode) - { - SW_SET_REG_BY_FIELD(LED_CTRL, PATTERN_EN, 3, data); - } - else - { - return SW_BAD_PARAM; - } - - if (pattern->map & (1 << FULL_DUPLEX_LIGHT_EN)) - { - SW_SET_REG_BY_FIELD(LED_CTRL, FULL_LIGHT_EN, 1, data); - } - - if (pattern->map & (1 << HALF_DUPLEX_LIGHT_EN)) - { - SW_SET_REG_BY_FIELD(LED_CTRL, HALF_LIGHT_EN, 1, data); - } - - if (pattern->map & (1 << POWER_ON_LIGHT_EN)) - { - SW_SET_REG_BY_FIELD(LED_CTRL, POWERON_LIGHT_EN, 1, data); - } - - if (pattern->map & (1 << LINK_1000M_LIGHT_EN)) - { - SW_SET_REG_BY_FIELD(LED_CTRL, GE_LIGHT_EN, 1, data); - } - - if (pattern->map & (1 << LINK_100M_LIGHT_EN)) - { - SW_SET_REG_BY_FIELD(LED_CTRL, FE_LIGHT_EN, 1, data); - } - - if (pattern->map & (1 << LINK_10M_LIGHT_EN)) - { - SW_SET_REG_BY_FIELD(LED_CTRL, ETH_LIGHT_EN, 1, data); - } - - if (pattern->map & (1 << COLLISION_BLINK_EN)) - { - SW_SET_REG_BY_FIELD(LED_CTRL, COL_BLINK_EN, 1, data); - } - - if (pattern->map & (1 << RX_TRAFFIC_BLINK_EN)) - { - SW_SET_REG_BY_FIELD(LED_CTRL, RX_BLINK_EN, 1, data); - } - - if (pattern->map & (1 << TX_TRAFFIC_BLINK_EN)) - { - SW_SET_REG_BY_FIELD(LED_CTRL, TX_BLINK_EN, 1, data); - } - - if (pattern->map & (1 << LINKUP_OVERRIDE_EN)) - { - SW_SET_REG_BY_FIELD(LED_CTRL, LINKUP_OVER_EN, 1, data); - } - else - { - SW_SET_REG_BY_FIELD(LED_CTRL, LINKUP_OVER_EN, 0, data); - } - - if (LED_BLINK_2HZ == pattern->freq) - { - SW_SET_REG_BY_FIELD(LED_CTRL, BLINK_FREQ, 0, data); - } - else if (LED_BLINK_4HZ == pattern->freq) - { - SW_SET_REG_BY_FIELD(LED_CTRL, BLINK_FREQ, 1, data); - } - else if (LED_BLINK_8HZ == pattern->freq) - { - SW_SET_REG_BY_FIELD(LED_CTRL, BLINK_FREQ, 2, data); - } - else if (LED_BLINK_TXRX == pattern->freq) - { - SW_SET_REG_BY_FIELD(LED_CTRL, BLINK_FREQ, 3, data); - } - else - { - return SW_BAD_PARAM; - } - - HSL_REG_ENTRY_GEN_GET(rv, dev_id, addr, sizeof (a_uint32_t), - (a_uint8_t *) (®), - sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - - if (LED_LAN_PORT_GROUP == group) - { - reg &= 0xffff0000; - reg |= data; - } - else - { - reg &= 0xffff; - reg |= (data << 16); - } - - HSL_REG_ENTRY_GEN_SET(rv, dev_id, addr, sizeof (a_uint32_t), - (a_uint8_t *) (®), - sizeof (a_uint32_t)); - return rv; -} - -static sw_error_t -_garuda_led_ctrl_pattern_get(a_uint32_t dev_id, led_pattern_group_t group, - led_pattern_id_t id, led_ctrl_pattern_t * pattern) -{ - a_uint32_t data = 0, reg, tmp; - a_uint32_t addr; - sw_error_t rv; - - HSL_DEV_ID_CHECK(dev_id); - - if (group >= LED_GROUP_BUTT) - { - return SW_BAD_PARAM; - } - - if (id > MAX_LED_PATTERN_ID) - { - return SW_BAD_PARAM; - } - - aos_mem_zero(pattern, sizeof(led_ctrl_pattern_t)); - - addr = LED_PATTERN_ADDR + (id << 2); - - HSL_REG_ENTRY_GEN_GET(rv, dev_id, addr, sizeof (a_uint32_t), - (a_uint8_t *) (®), - sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - - if (LED_LAN_PORT_GROUP == group) - { - data = reg & 0xffff; - } - else - { - data = (reg >> 16) & 0xffff; - } - - SW_GET_FIELD_BY_REG(LED_CTRL, PATTERN_EN, tmp, data); - if (0 == tmp) - { - pattern->mode = LED_ALWAYS_OFF; - } - else if (1 == tmp) - { - pattern->mode = LED_ALWAYS_BLINK; - } - else if (2 == tmp) - { - pattern->mode = LED_ALWAYS_ON; - } - else - { - pattern->mode = LED_PATTERN_MAP_EN; - } - - SW_GET_FIELD_BY_REG(LED_CTRL, FULL_LIGHT_EN, tmp, data); - if (1 == tmp) - { - pattern->map |= (1 << FULL_DUPLEX_LIGHT_EN); - } - - SW_GET_FIELD_BY_REG(LED_CTRL, HALF_LIGHT_EN, tmp, data); - if (1 == tmp) - { - pattern->map |= (1 << HALF_DUPLEX_LIGHT_EN); - } - - SW_GET_FIELD_BY_REG(LED_CTRL, POWERON_LIGHT_EN, tmp, data); - if (1 == tmp) - { - pattern->map |= (1 << POWER_ON_LIGHT_EN); - } - - SW_GET_FIELD_BY_REG(LED_CTRL, GE_LIGHT_EN, tmp, data); - if (1 == tmp) - { - pattern->map |= (1 << LINK_1000M_LIGHT_EN); - } - - SW_GET_FIELD_BY_REG(LED_CTRL, FE_LIGHT_EN, tmp, data); - if (1 == tmp) - { - pattern->map |= (1 << LINK_100M_LIGHT_EN); - } - - SW_GET_FIELD_BY_REG(LED_CTRL, ETH_LIGHT_EN, tmp, data); - if (1 == tmp) - { - pattern->map |= (1 << LINK_10M_LIGHT_EN); - } - - SW_GET_FIELD_BY_REG(LED_CTRL, COL_BLINK_EN, tmp, data); - if (1 == tmp) - { - pattern->map |= (1 << COLLISION_BLINK_EN); - } - - SW_GET_FIELD_BY_REG(LED_CTRL, RX_BLINK_EN, tmp, data); - if (1 == tmp) - { - pattern->map |= (1 << RX_TRAFFIC_BLINK_EN); - } - - SW_GET_FIELD_BY_REG(LED_CTRL, TX_BLINK_EN, tmp, data); - if (1 == tmp) - { - pattern->map |= (1 << TX_TRAFFIC_BLINK_EN); - } - - SW_GET_FIELD_BY_REG(LED_CTRL, LINKUP_OVER_EN, tmp, data); - if (1 == tmp) - { - pattern->map |= (1 << LINKUP_OVERRIDE_EN); - } - - SW_GET_FIELD_BY_REG(LED_CTRL, BLINK_FREQ, tmp, data); - if (0 == tmp) - { - pattern->freq = LED_BLINK_2HZ; - } - else if (1 == tmp) - { - pattern->freq = LED_BLINK_4HZ; - } - else if (2 == tmp) - { - pattern->freq = LED_BLINK_8HZ; - } - else - { - pattern->freq = LED_BLINK_TXRX; - } - - return SW_OK; -} - -/** -* @brief Set led control pattern on a particular device. -* @param[in] dev_id device id -* @param[in] group pattern group, lan or wan -* @param[in] id pattern id -* @param[in] pattern led control pattern -* @return SW_OK or error code -*/ -HSL_LOCAL sw_error_t -garuda_led_ctrl_pattern_set(a_uint32_t dev_id, led_pattern_group_t group, - led_pattern_id_t id, led_ctrl_pattern_t * pattern) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _garuda_led_ctrl_pattern_set(dev_id, group, id, pattern); - HSL_API_UNLOCK; - return rv; -} - -/** -* @brief Get led control pattern on a particular device. -* @param[in] dev_id device id -* @param[in] group pattern group, lan or wan -* @param[in] id pattern id -* @param[out] pattern led control pattern -* @return SW_OK or error code -*/ -HSL_LOCAL sw_error_t -garuda_led_ctrl_pattern_get(a_uint32_t dev_id, led_pattern_group_t group, - led_pattern_id_t id, led_ctrl_pattern_t * pattern) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _garuda_led_ctrl_pattern_get(dev_id, group, id, pattern); - HSL_API_UNLOCK; - return rv; -} - -sw_error_t -garuda_led_init(a_uint32_t dev_id) -{ - HSL_DEV_ID_CHECK(dev_id); - -#ifndef HSL_STANDALONG - { - hsl_api_t *p_api; - - SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id)); - p_api->led_ctrl_pattern_set = garuda_led_ctrl_pattern_set; - p_api->led_ctrl_pattern_get = garuda_led_ctrl_pattern_get; - } -#endif - - return SW_OK; -} - -/** - * @} - */ - diff --git a/feeds/ipq807x/qca-ssdk/src/src/hsl/garuda/garuda_mib.c b/feeds/ipq807x/qca-ssdk/src/src/hsl/garuda/garuda_mib.c deleted file mode 100755 index 9e1fe747b..000000000 --- a/feeds/ipq807x/qca-ssdk/src/src/hsl/garuda/garuda_mib.c +++ /dev/null @@ -1,378 +0,0 @@ -/* - * Copyright (c) 2012, The Linux Foundation. All rights reserved. - * Permission to use, copy, modify, and/or distribute this software for - * any purpose with or without fee is hereby granted, provided that the - * above copyright notice and this permission notice appear in all copies. - * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES - * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR - * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES - * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN - * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT - * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. - */ - - -/** - * @defgroup garuda_mib GARUDA_MIB - * @{ - */ -#include "sw.h" -#include "hsl.h" -#include "hsl_dev.h" -#include "hsl_port_prop.h" -#include "garuda_mib.h" -#include "garuda_reg.h" - -static sw_error_t -_garuda_get_mib_info(a_uint32_t dev_id, fal_port_t port_id, - fal_mib_info_t * mib_info) -{ - a_uint32_t val; - sw_error_t rv; - - HSL_DEV_ID_CHECK(dev_id); - - if (A_FALSE == hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU)) - { - return SW_OUT_OF_RANGE; - } - - HSL_REG_ENTRY_GET(rv, dev_id, MIB_RXBROAD, port_id, - (a_uint8_t *) (&val), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - mib_info->RxBroad = val; - - HSL_REG_ENTRY_GET(rv, dev_id, MIB_RXPAUSE, port_id, - (a_uint8_t *) (&val), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - mib_info->RxPause = val; - - HSL_REG_ENTRY_GET(rv, dev_id, MIB_RXMULTI, port_id, - (a_uint8_t *) (&val), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - mib_info->RxMulti = val; - - HSL_REG_ENTRY_GET(rv, dev_id, MIB_RXFCSERR, port_id, - (a_uint8_t *) (&val), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - mib_info->RxFcsErr = val; - - HSL_REG_ENTRY_GET(rv, dev_id, MIB_RXALLIGNERR, port_id, - (a_uint8_t *) (&val), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - mib_info->RxAllignErr = val; - - HSL_REG_ENTRY_GET(rv, dev_id, MIB_RXRUNT, port_id, (a_uint8_t *) (&val), - sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - mib_info->RxRunt = val; - - HSL_REG_ENTRY_GET(rv, dev_id, MIB_RXFRAGMENT, port_id, - (a_uint8_t *) (&val), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - mib_info->RxFragment = val; - - HSL_REG_ENTRY_GET(rv, dev_id, MIB_RX64BYTE, port_id, - (a_uint8_t *) (&val), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - mib_info->Rx64Byte = val; - - HSL_REG_ENTRY_GET(rv, dev_id, MIB_RX128BYTE, port_id, - (a_uint8_t *) (&val), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - mib_info->Rx128Byte = val; - - HSL_REG_ENTRY_GET(rv, dev_id, MIB_RX256BYTE, port_id, - (a_uint8_t *) (&val), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - mib_info->Rx256Byte = val; - - HSL_REG_ENTRY_GET(rv, dev_id, MIB_RX512BYTE, port_id, - (a_uint8_t *) (&val), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - mib_info->Rx512Byte = val; - - HSL_REG_ENTRY_GET(rv, dev_id, MIB_RX1024BYTE, port_id, - (a_uint8_t *) (&val), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - mib_info->Rx1024Byte = val; - - HSL_REG_ENTRY_GET(rv, dev_id, MIB_RX1518BYTE, port_id, - (a_uint8_t *) (&val), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - mib_info->Rx1518Byte = val; - - HSL_REG_ENTRY_GET(rv, dev_id, MIB_RXMAXBYTE, port_id, - (a_uint8_t *) (&val), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - mib_info->RxMaxByte = val; - - HSL_REG_ENTRY_GET(rv, dev_id, MIB_RXTOOLONG, port_id, - (a_uint8_t *) (&val), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - mib_info->RxTooLong = val; - - HSL_REG_ENTRY_GET(rv, dev_id, MIB_RXGOODBYTE_LO, port_id, - (a_uint8_t *) (&val), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - mib_info->RxGoodByte_lo = val; - - HSL_REG_ENTRY_GET(rv, dev_id, MIB_RXGOODBYTE_HI, port_id, - (a_uint8_t *) (&val), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - mib_info->RxGoodByte_hi = val; - - HSL_REG_ENTRY_GET(rv, dev_id, MIB_RXBADBYTE_LO, port_id, - (a_uint8_t *) (&val), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - mib_info->RxBadByte_lo = val; - - HSL_REG_ENTRY_GET(rv, dev_id, MIB_RXBADBYTE_HI, port_id, - (a_uint8_t *) (&val), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - mib_info->RxBadByte_hi = val; - - HSL_REG_ENTRY_GET(rv, dev_id, MIB_RXOVERFLOW, port_id, - (a_uint8_t *) (&val), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - mib_info->RxOverFlow = val; - - HSL_REG_ENTRY_GET(rv, dev_id, MIB_FILTERED, port_id, - (a_uint8_t *) (&val), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - mib_info->Filtered = val; - - HSL_REG_ENTRY_GET(rv, dev_id, MIB_TXBROAD, port_id, (a_uint8_t *) (&val), - sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - mib_info->TxBroad = val; - - HSL_REG_ENTRY_GET(rv, dev_id, MIB_TXPAUSE, port_id, (a_uint8_t *) (&val), - sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - mib_info->TxPause = val; - - HSL_REG_ENTRY_GET(rv, dev_id, MIB_TXMULTI, port_id, (a_uint8_t *) (&val), - sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - mib_info->TxMulti = val; - - HSL_REG_ENTRY_GET(rv, dev_id, MIB_TXUNDERRUN, port_id, - (a_uint8_t *) (&val), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - mib_info->TxUnderRun = val; - - HSL_REG_ENTRY_GET(rv, dev_id, MIB_TX64BYTE, port_id, - (a_uint8_t *) (&val), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - mib_info->Tx64Byte = val; - - HSL_REG_ENTRY_GET(rv, dev_id, MIB_TX128BYTE, port_id, - (a_uint8_t *) (&val), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - mib_info->Tx128Byte = val; - - HSL_REG_ENTRY_GET(rv, dev_id, MIB_TX256BYTE, port_id, - (a_uint8_t *) (&val), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - mib_info->Tx256Byte = val; - - HSL_REG_ENTRY_GET(rv, dev_id, MIB_TX512BYTE, port_id, - (a_uint8_t *) (&val), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - mib_info->Tx512Byte = val; - - HSL_REG_ENTRY_GET(rv, dev_id, MIB_TX1024BYTE, port_id, - (a_uint8_t *) (&val), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - mib_info->Tx1024Byte = val; - - HSL_REG_ENTRY_GET(rv, dev_id, MIB_TX1518BYTE, port_id, - (a_uint8_t *) (&val), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - mib_info->Tx1518Byte = val; - - HSL_REG_ENTRY_GET(rv, dev_id, MIB_TXMAXBYTE, port_id, - (a_uint8_t *) (&val), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - mib_info->TxMaxByte = val; - - HSL_REG_ENTRY_GET(rv, dev_id, MIB_TXOVERSIZE, port_id, - (a_uint8_t *) (&val), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - mib_info->TxOverSize = val; - - HSL_REG_ENTRY_GET(rv, dev_id, MIB_TXBYTE_LO, port_id, - (a_uint8_t *) (&val), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - mib_info->TxByte_lo = val; - - HSL_REG_ENTRY_GET(rv, dev_id, MIB_TXBYTE_HI, port_id, - (a_uint8_t *) (&val), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - mib_info->TxByte_hi = val; - - HSL_REG_ENTRY_GET(rv, dev_id, MIB_TXCOLLISION, port_id, - (a_uint8_t *) (&val), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - mib_info->TxCollision = val; - - HSL_REG_ENTRY_GET(rv, dev_id, MIB_TXABORTCOL, port_id, - (a_uint8_t *) (&val), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - mib_info->TxAbortCol = val; - - HSL_REG_ENTRY_GET(rv, dev_id, MIB_TXMULTICOL, port_id, - (a_uint8_t *) (&val), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - mib_info->TxMultiCol = val; - - HSL_REG_ENTRY_GET(rv, dev_id, MIB_TXSINGALCOL, port_id, - (a_uint8_t *) (&val), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - mib_info->TxSingalCol = val; - - HSL_REG_ENTRY_GET(rv, dev_id, MIB_TXEXCDEFER, port_id, - (a_uint8_t *) (&val), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - mib_info->TxExcDefer = val; - - HSL_REG_ENTRY_GET(rv, dev_id, MIB_TXDEFER, port_id, (a_uint8_t *) (&val), - sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - mib_info->TxDefer = val; - - HSL_REG_ENTRY_GET(rv, dev_id, MIB_TXLATECOL, port_id, - (a_uint8_t *) (&val), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - mib_info->TxLateCol = val; - - return SW_OK; -} - -static sw_error_t -_garuda_mib_status_set(a_uint32_t dev_id, a_bool_t enable) -{ - sw_error_t rv; - a_uint32_t val; - - HSL_DEV_ID_CHECK(dev_id); - - if (A_TRUE == enable) - { - val = 1; - } - else if (A_FALSE == enable) - { - val = 0; - } - else - { - return SW_BAD_PARAM; - } - - HSL_REG_FIELD_SET(rv, dev_id, MIB_FUNC, 0, MIB_EN, - (a_uint8_t *) (&val), sizeof (a_uint32_t)); - return rv; -} - -static sw_error_t -_garuda_mib_status_get(a_uint32_t dev_id, a_bool_t * enable) -{ - sw_error_t rv; - a_uint32_t val; - - HSL_DEV_ID_CHECK(dev_id); - - HSL_REG_FIELD_GET(rv, dev_id, MIB_FUNC, 0, MIB_EN, - (a_uint8_t *) (&val), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - - if (1 == val) - { - *enable = A_TRUE; - } - else - { - *enable = A_FALSE; - } - - return SW_OK; -} - -/** - * @brief Get mib infomation on particular port. - * @param[in] dev_id device id - * @param[in] port_id port id - * @param[out] mib_info mib infomation - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -garuda_get_mib_info(a_uint32_t dev_id, fal_port_t port_id, - fal_mib_info_t * mib_info) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _garuda_get_mib_info(dev_id, port_id, mib_info); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Set mib status on a particular device. - * @param[in] dev_id device id - * @param[in] enable A_TRUE or A_FALSE - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -garuda_mib_status_set(a_uint32_t dev_id, a_bool_t enable) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _garuda_mib_status_set(dev_id, enable); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Get mib status on a particular device. - * @param[in] dev_id device id - * @param[out] enable A_TRUE or A_FALSE - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -garuda_mib_status_get(a_uint32_t dev_id, a_bool_t * enable) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _garuda_mib_status_get(dev_id, enable); - HSL_API_UNLOCK; - return rv; -} - -sw_error_t -garuda_mib_init(a_uint32_t dev_id) -{ - HSL_DEV_ID_CHECK(dev_id); - -#ifndef HSL_STANDALONG - hsl_api_t *p_api; - - SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id)); - - p_api->get_mib_info = garuda_get_mib_info; - p_api->mib_status_set = garuda_mib_status_set; - p_api->mib_status_get = garuda_mib_status_get; -#endif - - return SW_OK; -} - -/** - * @} - */ - diff --git a/feeds/ipq807x/qca-ssdk/src/src/hsl/garuda/garuda_mirror.c b/feeds/ipq807x/qca-ssdk/src/src/hsl/garuda/garuda_mirror.c deleted file mode 100755 index 88b78f184..000000000 --- a/feeds/ipq807x/qca-ssdk/src/src/hsl/garuda/garuda_mirror.c +++ /dev/null @@ -1,318 +0,0 @@ -/* - * Copyright (c) 2012, The Linux Foundation. All rights reserved. - * Permission to use, copy, modify, and/or distribute this software for - * any purpose with or without fee is hereby granted, provided that the - * above copyright notice and this permission notice appear in all copies. - * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES - * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR - * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES - * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN - * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT - * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. - */ - - -/** - * @defgroup garuda_mirror GARUDA_MIRROR - * @{ - */ -#include "sw.h" -#include "hsl.h" -#include "hsl_dev.h" -#include "hsl_port_prop.h" -#include "garuda_mirror.h" -#include "garuda_reg.h" - -static sw_error_t -_garuda_mirr_analysis_port_set(a_uint32_t dev_id, fal_port_t port_id) -{ - sw_error_t rv; - a_uint32_t val; - - HSL_DEV_ID_CHECK(dev_id); - - if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU)) - { - return SW_BAD_PARAM; - } - - val = port_id; - HSL_REG_FIELD_SET(rv, dev_id, CPU_PORT, 0, MIRROR_PORT_NUM, - (a_uint8_t *) (&val), sizeof (a_uint32_t)); - return rv; -} - -static sw_error_t -_garuda_mirr_analysis_port_get(a_uint32_t dev_id, fal_port_t * port_id) -{ - sw_error_t rv; - a_uint32_t val; - - HSL_DEV_ID_CHECK(dev_id); - - HSL_REG_FIELD_GET(rv, dev_id, CPU_PORT, 0, MIRROR_PORT_NUM, - (a_uint8_t *) (&val), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - - *port_id = val; - return SW_OK; -} - -static sw_error_t -_garuda_mirr_port_in_set(a_uint32_t dev_id, fal_port_t port_id, a_bool_t enable) -{ - sw_error_t rv; - a_uint32_t val; - - HSL_DEV_ID_CHECK(dev_id); - - if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU)) - { - return SW_BAD_PARAM; - } - - if (A_TRUE == enable) - { - val = 1; - } - else if (A_FALSE == enable) - { - val = 0; - } - else - { - return SW_BAD_PARAM; - } - - HSL_REG_FIELD_SET(rv, dev_id, PORT_CTL, port_id, ING_MIRROR_EN, - (a_uint8_t *) (&val), sizeof (a_uint32_t)); - return rv; -} - -static sw_error_t -_garuda_mirr_port_in_get(a_uint32_t dev_id, fal_port_t port_id, - a_bool_t * enable) -{ - sw_error_t rv; - a_uint32_t val; - - HSL_DEV_ID_CHECK(dev_id); - - if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU)) - { - return SW_BAD_PARAM; - } - - HSL_REG_FIELD_GET(rv, dev_id, PORT_CTL, port_id, ING_MIRROR_EN, - (a_uint8_t *) (&val), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - - if (1 == val) - { - *enable = A_TRUE; - } - else - { - *enable = A_FALSE; - } - - return SW_OK; -} - -static sw_error_t -_garuda_mirr_port_eg_set(a_uint32_t dev_id, fal_port_t port_id, a_bool_t enable) -{ - sw_error_t rv; - a_uint32_t val; - - HSL_DEV_ID_CHECK(dev_id); - - if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU)) - { - return SW_BAD_PARAM; - } - - if (A_TRUE == enable) - { - val = 1; - } - else if (A_FALSE == enable) - { - val = 0; - } - else - { - return SW_BAD_PARAM; - } - - HSL_REG_FIELD_SET(rv, dev_id, PORT_CTL, port_id, EG_MIRROR_EN, - (a_uint8_t *) (&val), sizeof (a_uint32_t)); - return rv; -} - -static sw_error_t -_garuda_mirr_port_eg_get(a_uint32_t dev_id, fal_port_t port_id, a_bool_t * enable) -{ - sw_error_t rv; - a_uint32_t val; - - HSL_DEV_ID_CHECK(dev_id); - - if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU)) - { - return SW_BAD_PARAM; - } - - HSL_REG_FIELD_GET(rv, dev_id, PORT_CTL, port_id, EG_MIRROR_EN, - (a_uint8_t *) (&val), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - - if (1 == val) - { - *enable = A_TRUE; - } - else - { - *enable = A_FALSE; - } - - return SW_OK; -} - -/** - * @details Comments: - * The analysis port works for both ingress and egress mirror. - * @brief Set mirror analyzer port on particular a device. - * @param[in] dev_id device id - * @param[in] port_id port id - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -garuda_mirr_analysis_port_set(a_uint32_t dev_id, fal_port_t port_id) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _garuda_mirr_analysis_port_set(dev_id, port_id); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Get mirror analysis port on particular a device. - * @param[in] dev_id device id - * @param[out] port_id port id - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -garuda_mirr_analysis_port_get(a_uint32_t dev_id, fal_port_t * port_id) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _garuda_mirr_analysis_port_get(dev_id, port_id); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Set ingress mirror status on particular a port. - * @param[in] dev_id device id - * @param[in] port_id port id - * @param[in] enable A_TRUE or A_FALSE - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -garuda_mirr_port_in_set(a_uint32_t dev_id, fal_port_t port_id, a_bool_t enable) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _garuda_mirr_port_in_set(dev_id, port_id, enable); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Get ingress mirror status on particular a port. - * @param[in] dev_id device id - * @param[in] port_id port id - * @param[out] enable A_TRUE or A_FALSE - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -garuda_mirr_port_in_get(a_uint32_t dev_id, fal_port_t port_id, - a_bool_t * enable) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _garuda_mirr_port_in_get(dev_id, port_id, enable); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Set egress mirror status on a particular port. - * @param[in] dev_id device id - * @param[in] port_id port id - * @param[in] enable A_TRUE or A_FALSE - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -garuda_mirr_port_eg_set(a_uint32_t dev_id, fal_port_t port_id, a_bool_t enable) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _garuda_mirr_port_eg_set(dev_id, port_id, enable); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Get egress mirror status on a particular port. - * @param[in] dev_id device id - * @param[in] port_id port id - * @param[out] enable A_TRUE or A_FALSE - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -garuda_mirr_port_eg_get(a_uint32_t dev_id, fal_port_t port_id, a_bool_t * enable) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _garuda_mirr_port_eg_get(dev_id, port_id, enable); - HSL_API_UNLOCK; - return rv; -} - -sw_error_t -garuda_mirr_init(a_uint32_t dev_id) -{ - HSL_DEV_ID_CHECK(dev_id); - -#ifndef HSL_STANDALONG - { - hsl_api_t *p_api; - - SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id)); - - p_api->mirr_analysis_port_set = garuda_mirr_analysis_port_set; - p_api->mirr_analysis_port_get = garuda_mirr_analysis_port_get; - p_api->mirr_port_in_set = garuda_mirr_port_in_set; - p_api->mirr_port_in_get = garuda_mirr_port_in_get; - p_api->mirr_port_eg_set = garuda_mirr_port_eg_set; - p_api->mirr_port_eg_get = garuda_mirr_port_eg_get; - } -#endif - - return SW_OK; -} - -/** - * @} - */ - diff --git a/feeds/ipq807x/qca-ssdk/src/src/hsl/garuda/garuda_misc.c b/feeds/ipq807x/qca-ssdk/src/src/hsl/garuda/garuda_misc.c deleted file mode 100755 index 73ba5ef88..000000000 --- a/feeds/ipq807x/qca-ssdk/src/src/hsl/garuda/garuda_misc.c +++ /dev/null @@ -1,1009 +0,0 @@ -/* - * Copyright (c) 2012, The Linux Foundation. All rights reserved. - * Permission to use, copy, modify, and/or distribute this software for - * any purpose with or without fee is hereby granted, provided that the - * above copyright notice and this permission notice appear in all copies. - * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES - * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR - * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES - * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN - * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT - * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. - */ - - -/** - * @defgroup garuda_misc GARUDA_MISC - * @{ - */ - -#include "sw.h" -#include "hsl.h" -#include "hsl_dev.h" -#include "hsl_port_prop.h" -#include "garuda_misc.h" -#include "garuda_reg.h" - -#define GARUDA_MAX_FRMAE_SIZE 9216 - - -static sw_error_t -_garuda_arp_status_set(a_uint32_t dev_id, a_bool_t enable) -{ - a_uint32_t data; - sw_error_t rv; - - HSL_DEV_ID_CHECK(dev_id); - - if (A_TRUE == enable) - { - data = 1; - } - else if (A_FALSE == enable) - { - data = 0; - } - else - { - return SW_BAD_PARAM; - } - - HSL_REG_FIELD_SET(rv, dev_id, ADDR_TABLE_CTL, 0, ARP_EN, - (a_uint8_t *) (&data), sizeof (a_uint32_t)); - return rv; -} - - -static sw_error_t -_garuda_arp_status_get(a_uint32_t dev_id, a_bool_t *enable) -{ - a_uint32_t data; - sw_error_t rv; - - HSL_DEV_ID_CHECK(dev_id); - - HSL_REG_FIELD_GET(rv, dev_id, ADDR_TABLE_CTL, 0, ARP_EN, - (a_uint8_t *) (&data), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - - if (1 == data) - { - *enable = A_TRUE; - } - else - { - *enable = A_FALSE; - } - - return SW_OK; -} - - -static sw_error_t -_garuda_frame_max_size_set(a_uint32_t dev_id, a_uint32_t size) -{ - a_uint32_t data; - sw_error_t rv; - - HSL_DEV_ID_CHECK(dev_id); - - if (GARUDA_MAX_FRMAE_SIZE < size) - { - return SW_BAD_PARAM; - } - - data = size; - HSL_REG_FIELD_SET(rv, dev_id, GLOBAL_CTL, 0, MAX_FRAME_SIZE, - (a_uint8_t *) (&data), sizeof (a_uint32_t)); - return rv; -} - - -static sw_error_t -_garuda_frame_max_size_get(a_uint32_t dev_id, a_uint32_t *size) -{ - a_uint32_t data; - sw_error_t rv; - - HSL_DEV_ID_CHECK(dev_id); - - HSL_REG_FIELD_GET(rv, dev_id, GLOBAL_CTL, 0, MAX_FRAME_SIZE, - (a_uint8_t *) (&data), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - - *size = data; - return SW_OK; -} - -static sw_error_t -_garuda_port_unk_sa_cmd_set(a_uint32_t dev_id, fal_port_t port_id, - fal_fwd_cmd_t cmd) -{ - sw_error_t rv; - a_uint32_t data; - - HSL_DEV_ID_CHECK(dev_id); - - if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU)) - { - return SW_BAD_PARAM; - } - - HSL_REG_ENTRY_GET(rv, dev_id, PORT_CTL, port_id, (a_uint8_t *) (&data), - sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - - if (FAL_MAC_FRWRD == cmd) - { - SW_SET_REG_BY_FIELD(PORT_CTL, PORT_LOCK_EN, 0, data); - } - else if (FAL_MAC_DROP == cmd) - { - SW_SET_REG_BY_FIELD(PORT_CTL, PORT_LOCK_EN, 1, data); - SW_SET_REG_BY_FIELD(PORT_CTL, LOCK_DROP_EN, 1, data); - } - else if (FAL_MAC_RDT_TO_CPU == cmd) - { - SW_SET_REG_BY_FIELD(PORT_CTL, PORT_LOCK_EN, 1, data); - SW_SET_REG_BY_FIELD(PORT_CTL, LOCK_DROP_EN, 0, data); - } - else - { - return SW_NOT_SUPPORTED; - } - - HSL_REG_ENTRY_SET(rv, dev_id, PORT_CTL, port_id, (a_uint8_t *) (&data), - sizeof (a_uint32_t)); - return rv; -} - -static sw_error_t -_garuda_port_unk_sa_cmd_get(a_uint32_t dev_id, fal_port_t port_id, - fal_fwd_cmd_t * action) -{ - sw_error_t rv; - a_uint32_t data; - a_uint32_t port_lock_en, port_drop_en; - - HSL_DEV_ID_CHECK(dev_id); - - if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU)) - { - return SW_BAD_PARAM; - } - - HSL_REG_ENTRY_GET(rv, dev_id, PORT_CTL, port_id, (a_uint8_t *) (&data), - sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - - SW_GET_FIELD_BY_REG(PORT_CTL, PORT_LOCK_EN, port_lock_en, data); - SW_GET_FIELD_BY_REG(PORT_CTL, LOCK_DROP_EN, port_drop_en, data); - - if (1 == port_lock_en) - { - if (1 == port_drop_en) - { - *action = FAL_MAC_DROP; - } - else - { - *action = FAL_MAC_RDT_TO_CPU; - } - } - else - { - *action = FAL_MAC_FRWRD; - } - - return SW_OK; -} - -static sw_error_t -_garuda_port_unk_uc_filter_set(a_uint32_t dev_id, fal_port_t port_id, - a_bool_t enable) -{ - sw_error_t rv; - a_uint32_t data; - - HSL_DEV_ID_CHECK(dev_id); - - if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU)) - { - return SW_BAD_PARAM; - } - - HSL_REG_FIELD_GET(rv, dev_id, FLOOD_MASK, 0, UNI_FLOOD_DP, - (a_uint8_t *) (&data), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - - if (A_TRUE == enable) - { - data &= (~((a_uint32_t)0x1 << port_id)); - } - else if (A_FALSE == enable) - { - data |= (0x1 << port_id); - } - else - { - return SW_BAD_PARAM; - } - - HSL_REG_FIELD_SET(rv, dev_id, FLOOD_MASK, 0, UNI_FLOOD_DP, - (a_uint8_t *) (&data), sizeof (a_uint32_t)); - return rv; -} - -static sw_error_t -_garuda_port_unk_uc_filter_get(a_uint32_t dev_id, fal_port_t port_id, - a_bool_t * enable) -{ - sw_error_t rv; - a_uint32_t reg, field; - - HSL_DEV_ID_CHECK(dev_id); - - if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU)) - { - return SW_BAD_PARAM; - } - - HSL_REG_FIELD_GET(rv, dev_id, FLOOD_MASK, 0, UNI_FLOOD_DP, - (a_uint8_t *) (®), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - - field = reg & (0x1 << port_id); - if (field) - { - *enable = A_FALSE; - } - else - { - *enable = A_TRUE; - } - - return SW_OK; -} - -static sw_error_t -_garuda_port_unk_mc_filter_set(a_uint32_t dev_id, fal_port_t port_id, - a_bool_t enable) -{ - sw_error_t rv; - a_uint32_t data; - - HSL_DEV_ID_CHECK(dev_id); - - if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU)) - { - return SW_BAD_PARAM; - } - - HSL_REG_FIELD_GET(rv, dev_id, FLOOD_MASK, 0, MUL_FLOOD_DP, - (a_uint8_t *) (&data), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - - if (A_TRUE == enable) - { - data &= (~((a_uint32_t)0x1 << port_id)); - } - else if (A_FALSE == enable) - { - data |= (0x1 << port_id); - } - else - { - return SW_BAD_PARAM; - } - - HSL_REG_FIELD_SET(rv, dev_id, FLOOD_MASK, 0, MUL_FLOOD_DP, - (a_uint8_t *) (&data), sizeof (a_uint32_t)); - return rv; -} - -static sw_error_t -_garuda_port_unk_mc_filter_get(a_uint32_t dev_id, fal_port_t port_id, - a_bool_t * enable) -{ - sw_error_t rv; - a_uint32_t reg, field; - - HSL_DEV_ID_CHECK(dev_id); - - if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU)) - { - return SW_BAD_PARAM; - } - - HSL_REG_FIELD_GET(rv, dev_id, FLOOD_MASK, 0, MUL_FLOOD_DP, - (a_uint8_t *) (®), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - - field = reg & (0x1 << port_id); - if (field) - { - *enable = A_FALSE; - } - else - { - *enable = A_TRUE; - } - - return SW_OK; -} - -static sw_error_t -_garuda_cpu_port_status_set(a_uint32_t dev_id, a_bool_t enable) -{ - sw_error_t rv; - a_uint32_t val; - - HSL_DEV_ID_CHECK(dev_id); - - if (A_TRUE == enable) - { - val = 1; - } - else if (A_FALSE == enable) - { - val = 0; - } - else - { - return SW_BAD_PARAM; - } - - HSL_REG_FIELD_SET(rv, dev_id, CPU_PORT, 0, CPU_PORT_EN, - (a_uint8_t *) (&val), sizeof (a_uint32_t)); - return rv; -} - -static sw_error_t -_garuda_cpu_port_status_get(a_uint32_t dev_id, a_bool_t *enable) -{ - sw_error_t rv; - a_uint32_t val; - - HSL_DEV_ID_CHECK(dev_id); - - HSL_REG_FIELD_GET(rv, dev_id, CPU_PORT, 0, CPU_PORT_EN, - (a_uint8_t *) (&val), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - - if (1 == val) - { - *enable = A_TRUE; - } - else - { - *enable = A_FALSE; - } - - return SW_OK; -} - - -static sw_error_t -_garuda_bc_to_cpu_port_set(a_uint32_t dev_id, a_bool_t enable) -{ - sw_error_t rv; - a_uint32_t val; - - HSL_DEV_ID_CHECK(dev_id); - - if (A_TRUE == enable) - { - val = 1; - } - else if (A_FALSE == enable) - { - val = 0; - } - else - { - return SW_BAD_PARAM; - } - - HSL_REG_FIELD_SET(rv, dev_id, FLOOD_MASK, 0, BROAD_TO_CPU, - (a_uint8_t *) (&val), sizeof (a_uint32_t)); - return rv; -} - - -static sw_error_t -_garuda_bc_to_cpu_port_get(a_uint32_t dev_id, a_bool_t * enable) -{ - sw_error_t rv; - a_uint32_t val; - - HSL_REG_FIELD_GET(rv, dev_id, FLOOD_MASK, 0, BROAD_TO_CPU, - (a_uint8_t *) (&val), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - - if (1 == val) - { - *enable = A_TRUE; - } - else - { - *enable = A_FALSE; - } - - return SW_OK; -} - -static sw_error_t -_garuda_pppoe_cmd_set(a_uint32_t dev_id, fal_fwd_cmd_t cmd) -{ - sw_error_t rv; - a_uint32_t val; - - HSL_DEV_ID_CHECK(dev_id); - - if (FAL_MAC_FRWRD == cmd) - { - val = 0; - } - else if (FAL_MAC_RDT_TO_CPU == cmd) - { - val = 1; - } - else - { - return SW_NOT_SUPPORTED; - } - - HSL_REG_FIELD_SET(rv, dev_id, QM_CTL, 0, PPPOE_RDT_EN, - (a_uint8_t *) (&val), sizeof (a_uint32_t)); - return rv; -} - - -static sw_error_t -_garuda_pppoe_cmd_get(a_uint32_t dev_id, fal_fwd_cmd_t * cmd) -{ - sw_error_t rv; - a_uint32_t val; - - HSL_DEV_ID_CHECK(dev_id); - - HSL_REG_FIELD_GET(rv, dev_id, QM_CTL, 0, PPPOE_RDT_EN, - (a_uint8_t *) (&val), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - - if (1 == val) - { - *cmd = FAL_MAC_RDT_TO_CPU; - } - else - { - *cmd = FAL_MAC_FRWRD; - } - - return SW_OK; -} - - -static sw_error_t -_garuda_pppoe_status_set(a_uint32_t dev_id, a_bool_t enable) -{ - sw_error_t rv; - a_uint32_t val; - - HSL_DEV_ID_CHECK(dev_id); - - if (A_TRUE == enable) - { - val = 1; - } - else if (A_FALSE == enable) - { - val = 0; - } - else - { - return SW_BAD_PARAM; - } - - HSL_REG_FIELD_SET(rv, dev_id, QM_CTL, 0, PPPOE_EN, - (a_uint8_t *) (&val), sizeof (a_uint32_t)); - return rv; -} - -static sw_error_t -_garuda_pppoe_status_get(a_uint32_t dev_id, a_bool_t * enable) -{ - sw_error_t rv; - a_uint32_t val; - - HSL_DEV_ID_CHECK(dev_id); - - HSL_REG_FIELD_GET(rv, dev_id, QM_CTL, 0, PPPOE_EN, - (a_uint8_t *) (&val), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - - if (1 == val) - { - *enable = A_TRUE; - } - else - { - *enable = A_FALSE; - } - - return SW_OK; -} - - - -static sw_error_t -_garuda_port_dhcp_set(a_uint32_t dev_id, fal_port_t port_id, a_bool_t enable) -{ - sw_error_t rv; - a_uint32_t val; - - HSL_DEV_ID_CHECK(dev_id); - - if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU)) - { - return SW_BAD_PARAM; - } - - if (A_TRUE == enable) - { - val = 1; - } - else if (A_FALSE == enable) - { - val = 0; - } - else - { - return SW_BAD_PARAM; - } - - HSL_REG_FIELD_SET(rv, dev_id, PORT_CTL, port_id, DHCP_EN, - (a_uint8_t *) (&val), sizeof (a_uint32_t)); - return rv; -} - -static sw_error_t -_garuda_port_dhcp_get(a_uint32_t dev_id, fal_port_t port_id, a_bool_t * enable) -{ - sw_error_t rv; - a_uint32_t val; - - HSL_DEV_ID_CHECK(dev_id); - - if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU)) - { - return SW_BAD_PARAM; - } - - HSL_REG_FIELD_GET(rv, dev_id, PORT_CTL, port_id, DHCP_EN, - (a_uint8_t *) (&val), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - - if (1 == val) - { - *enable = A_TRUE; - } - else - { - *enable = A_FALSE; - } - - return SW_OK; -} - -/** - * @brief Set arp packets hardware acknowledgement status on a particular device. - * @param[in] dev_id device id - * @param[in] enable A_TRUE or A_FALSE - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -garuda_arp_status_set(a_uint32_t dev_id, a_bool_t enable) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _garuda_arp_status_set(dev_id, enable); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Get arp packets hardware acknowledgement status on a particular device. - * @param[in] dev_id device id - * @param[out] enable A_TRUE or A_FALSE - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -garuda_arp_status_get(a_uint32_t dev_id, a_bool_t *enable) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _garuda_arp_status_get(dev_id, enable); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Set max frame size which device can received on a particular device. - * @details Comments: - * The granularity of packets size is byte. - * @param[in] dev_id device id - * @param[in] size packet size - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -garuda_frame_max_size_set(a_uint32_t dev_id, a_uint32_t size) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _garuda_frame_max_size_set(dev_id, size); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Get max frame size which device can received on a particular device. - * @details Comments: - * The unit of packets size is byte. - * @param[in] dev_id device id - * @param[out] size packet size - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -garuda_frame_max_size_get(a_uint32_t dev_id, a_uint32_t *size) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _garuda_frame_max_size_get(dev_id, size); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Set forwarding command for packets which source address is unknown on a particular port. - * @details Comments: - * Particular device may only support parts of forwarding commands. - * @param[in] dev_id device id - * @param[in] port_id port id - * @param[in] cmd forwarding command - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -garuda_port_unk_sa_cmd_set(a_uint32_t dev_id, fal_port_t port_id, - fal_fwd_cmd_t cmd) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _garuda_port_unk_sa_cmd_set(dev_id, port_id, cmd); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Get forwarding command for packets which source address is unknown on a particular port. - * @param[in] dev_id device id - * @param[in] port_id port id - * @param[out] cmd forwarding command - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -garuda_port_unk_sa_cmd_get(a_uint32_t dev_id, fal_port_t port_id, - fal_fwd_cmd_t * action) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _garuda_port_unk_sa_cmd_get(dev_id, port_id, action); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Set flooding status of unknown unicast packets on a particular port. - * @details Comments: - * If enable unknown unicast packets filter on one port then unknown - * unicast packets can't flood out from this port. - * @param[in] dev_id device id - * @param[in] port_id port id - * @param[in] enable A_TRUE or A_FALSE - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -garuda_port_unk_uc_filter_set(a_uint32_t dev_id, fal_port_t port_id, - a_bool_t enable) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _garuda_port_unk_uc_filter_set(dev_id, port_id, enable); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Get flooding status of unknown unicast packets on a particular port. - * @param[in] dev_id device id - * @param[in] port_id port id - * @param[out] enable A_TRUE or A_FALSE - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -garuda_port_unk_uc_filter_get(a_uint32_t dev_id, fal_port_t port_id, - a_bool_t * enable) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _garuda_port_unk_uc_filter_get(dev_id, port_id, enable); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Set flooding status of unknown multicast packets on a particular port. - * @details Comments: - * If enable unknown multicast packets filter on one port then unknown - * multicast packets can't flood out from this port. - * @param[in] dev_id device id - * @param[in] port_id port id - * @param[in] enable A_TRUE or A_FALSE - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -garuda_port_unk_mc_filter_set(a_uint32_t dev_id, fal_port_t port_id, - a_bool_t enable) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _garuda_port_unk_mc_filter_set(dev_id, port_id, enable); - HSL_API_UNLOCK; - return rv; -} - -/** @brief Get flooding status of unknown multicast packets on a particular port. - * @param[in] dev_id device id - * @param[in] port_id port id - * @param[out] enable A_TRUE or A_FALSE - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -garuda_port_unk_mc_filter_get(a_uint32_t dev_id, fal_port_t port_id, - a_bool_t * enable) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _garuda_port_unk_mc_filter_get(dev_id, port_id, enable); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Set cpu port status on a particular device. - * @param[in] dev_id device id - * @param[in] enable A_TRUE or A_FALSE - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -garuda_cpu_port_status_set(a_uint32_t dev_id, a_bool_t enable) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _garuda_cpu_port_status_set(dev_id, enable); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Get cpu port status on a particular device. - * @param[in] dev_id device id - * @param[in] enable A_TRUE or A_FALSE - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -garuda_cpu_port_status_get(a_uint32_t dev_id, a_bool_t *enable) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _garuda_cpu_port_status_get(dev_id, enable); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Set status of braodcast packets broadcasting to cpu on a particular device. - * @param[in] dev_id device id - * @param[in] enable A_TRUE or A_FALSE - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -garuda_bc_to_cpu_port_set(a_uint32_t dev_id, a_bool_t enable) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _garuda_bc_to_cpu_port_set(dev_id, enable); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Get status of braodcast packets broadcasting to cpu on a particular device. - * @param[in] dev_id device id - * @param[in] enable A_TRUE or A_FALSE - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -garuda_bc_to_cpu_port_get(a_uint32_t dev_id, a_bool_t * enable) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _garuda_bc_to_cpu_port_get(dev_id, enable); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Set pppoe packets forwarding command on a particular device. - * @details comments: - * Particular device may only support parts of forwarding commands. - * Ihis operation will take effect only after enabling pppoe packets - * hardware acknowledgement - * @param[in] dev_id device id - * @param[in] cmd forwarding command - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -garuda_pppoe_cmd_set(a_uint32_t dev_id, fal_fwd_cmd_t cmd) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _garuda_pppoe_cmd_set(dev_id, cmd); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Get pppoe packets forwarding command on a particular device. - * @param[in] dev_id device id - * @param[out] cmd forwarding command - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -garuda_pppoe_cmd_get(a_uint32_t dev_id, fal_fwd_cmd_t * cmd) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _garuda_pppoe_cmd_get(dev_id, cmd); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Set pppoe packets hardware acknowledgement status on particular device. - * @details comments: - * Particular device may only support parts of pppoe packets. - * @param[in] dev_id device id - * @param[in] enable A_TRUE or A_FALSE - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -garuda_pppoe_status_set(a_uint32_t dev_id, a_bool_t enable) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _garuda_pppoe_status_set(dev_id, enable); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Get pppoe packets hardware acknowledgement status on a particular device. - * @param[in] dev_id device id - * @param[out] enable A_TRUE or A_FALSE - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -garuda_pppoe_status_get(a_uint32_t dev_id, a_bool_t * enable) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _garuda_pppoe_status_get(dev_id, enable); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Set dhcp packets hardware acknowledgement status on a particular device. - * @param[in] dev_id device id - * @param[in] enable A_TRUE or A_FALSE - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -garuda_port_dhcp_set(a_uint32_t dev_id, fal_port_t port_id, a_bool_t enable) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _garuda_port_dhcp_set(dev_id, port_id, enable); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Get dhcp packets hardware acknowledgement status on particular device. - * @param[in] dev_id device id - * @param[out] enable A_TRUE or A_FALSE - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -garuda_port_dhcp_get(a_uint32_t dev_id, fal_port_t port_id, a_bool_t * enable) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _garuda_port_dhcp_get(dev_id, port_id, enable); - HSL_API_UNLOCK; - return rv; -} - -sw_error_t -garuda_misc_init(a_uint32_t dev_id) -{ - HSL_DEV_ID_CHECK(dev_id); - -#ifndef HSL_STANDALONG - { - hsl_api_t *p_api; - - SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id)); - - p_api->arp_status_set = garuda_arp_status_set; - p_api->arp_status_get = garuda_arp_status_get; - p_api->frame_max_size_set = garuda_frame_max_size_set; - p_api->frame_max_size_get = garuda_frame_max_size_get; - p_api->port_unk_sa_cmd_set = garuda_port_unk_sa_cmd_set; - p_api->port_unk_sa_cmd_get = garuda_port_unk_sa_cmd_get; - p_api->port_unk_uc_filter_set = garuda_port_unk_uc_filter_set; - p_api->port_unk_uc_filter_get = garuda_port_unk_uc_filter_get; - p_api->port_unk_mc_filter_set = garuda_port_unk_mc_filter_set; - p_api->port_unk_mc_filter_get = garuda_port_unk_mc_filter_get; - p_api->cpu_port_status_set = garuda_cpu_port_status_set; - p_api->cpu_port_status_get = garuda_cpu_port_status_get; - p_api->bc_to_cpu_port_set = garuda_bc_to_cpu_port_set; - p_api->bc_to_cpu_port_get = garuda_bc_to_cpu_port_get; - p_api->pppoe_cmd_set = garuda_pppoe_cmd_set; - p_api->pppoe_cmd_get = garuda_pppoe_cmd_get; - p_api->pppoe_status_set = garuda_pppoe_status_set; - p_api->pppoe_status_get = garuda_pppoe_status_get; - p_api->port_dhcp_set = garuda_port_dhcp_set; - p_api->port_dhcp_get = garuda_port_dhcp_get; - } -#endif - - return SW_OK; -} - -/** - * @} - */ - diff --git a/feeds/ipq807x/qca-ssdk/src/src/hsl/garuda/garuda_port_ctrl.c b/feeds/ipq807x/qca-ssdk/src/src/hsl/garuda/garuda_port_ctrl.c deleted file mode 100755 index 839db8c0b..000000000 --- a/feeds/ipq807x/qca-ssdk/src/src/hsl/garuda/garuda_port_ctrl.c +++ /dev/null @@ -1,1069 +0,0 @@ -/* - * Copyright (c) 2012, 2015, The Linux Foundation. All rights reserved. - * Permission to use, copy, modify, and/or distribute this software for - * any purpose with or without fee is hereby granted, provided that the - * above copyright notice and this permission notice appear in all copies. - * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES - * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR - * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES - * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN - * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT - * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. - */ - - -/** - * @defgroup garuda_port_ctrl GARUDA_PORT_CONTROL - * @{ - */ -#include "sw.h" -#include "hsl.h" -#include "hsl_dev.h" -#include "hsl_port_prop.h" -#include "garuda_port_ctrl.h" -#include "garuda_reg.h" -#include "hsl_phy.h" - -static sw_error_t -_garuda_port_duplex_set(a_uint32_t dev_id, fal_port_t port_id, - fal_port_duplex_t duplex) -{ - sw_error_t rv; - a_uint32_t phy_id = 0; - a_uint32_t reg_save = 0; - a_uint32_t reg_val = 0; - hsl_phy_ops_t *phy_drv; - - HSL_DEV_ID_CHECK(dev_id); - - if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_PHY)) - { - return SW_BAD_PARAM; - } - - SW_RTN_ON_NULL (phy_drv = hsl_phy_api_ops_get (dev_id)); - if (NULL == phy_drv->phy_duplex_set) - return SW_NOT_SUPPORTED; - - if (FAL_DUPLEX_BUTT <= duplex) - { - return SW_BAD_PARAM; - } - - rv = hsl_port_prop_get_phyid(dev_id, port_id, &phy_id); - SW_RTN_ON_ERROR(rv); - - //save reg value - HSL_REG_ENTRY_GET(rv, dev_id, PORT_STATUS, port_id, - (a_uint8_t *) (®_val), sizeof (a_uint32_t)); - reg_save = reg_val; - - SW_SET_REG_BY_FIELD(PORT_STATUS, LINK_EN, 0, reg_val); - SW_SET_REG_BY_FIELD(PORT_STATUS, RXMAC_EN, 0, reg_val); - SW_SET_REG_BY_FIELD(PORT_STATUS, TXMAC_EN, 0, reg_val); - - //set mac be config by sw and turn off RX TX MAC_EN - HSL_REG_ENTRY_SET(rv, dev_id, PORT_STATUS, port_id, - (a_uint8_t *) (®_val), sizeof (a_uint32_t)); - - rv = phy_drv->phy_duplex_set(dev_id, phy_id, duplex); - - //retore reg value - HSL_REG_ENTRY_SET(rv, dev_id, PORT_STATUS, port_id, - (a_uint8_t *) (®_save), sizeof (a_uint32_t)); - - return rv; -} - - -static sw_error_t -_garuda_port_duplex_get(a_uint32_t dev_id, fal_port_t port_id, - fal_port_duplex_t * pduplex) -{ - sw_error_t rv; - a_uint32_t phy_id; - hsl_phy_ops_t *phy_drv; - - HSL_DEV_ID_CHECK(dev_id); - - if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_PHY)) - { - return SW_BAD_PARAM; - } - - SW_RTN_ON_NULL (phy_drv = hsl_phy_api_ops_get (dev_id)); - if (NULL == phy_drv->phy_duplex_get) - return SW_NOT_SUPPORTED; - - rv = hsl_port_prop_get_phyid(dev_id, port_id, &phy_id); - SW_RTN_ON_ERROR(rv); - - rv = phy_drv->phy_duplex_get(dev_id, phy_id, pduplex); - return rv; -} - -static sw_error_t -_garuda_port_speed_set(a_uint32_t dev_id, fal_port_t port_id, - fal_port_speed_t speed) -{ - sw_error_t rv; - a_uint32_t phy_id = 0; - hsl_phy_ops_t *phy_drv; - - HSL_DEV_ID_CHECK(dev_id); - - if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_PHY)) - { - return SW_BAD_PARAM; - } - - SW_RTN_ON_NULL (phy_drv = hsl_phy_api_ops_get (dev_id)); - if (NULL == phy_drv->phy_speed_set) - return SW_NOT_SUPPORTED; - - rv = hsl_port_prop_get_phyid(dev_id, port_id, &phy_id); - SW_RTN_ON_ERROR(rv); - - if (FAL_SPEED_1000 < speed) - { - return SW_BAD_PARAM; - } - - rv = phy_drv->phy_speed_set(dev_id, phy_id, speed); - - return rv; -} - - -static sw_error_t -_garuda_port_speed_get(a_uint32_t dev_id, fal_port_t port_id, - fal_port_speed_t * pspeed) -{ - sw_error_t rv; - a_uint32_t phy_id; - hsl_phy_ops_t *phy_drv; - - HSL_DEV_ID_CHECK(dev_id); - - if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_PHY)) - { - return SW_BAD_PARAM; - } - - SW_RTN_ON_NULL (phy_drv = hsl_phy_api_ops_get (dev_id)); - if (NULL == phy_drv->phy_speed_get) - return SW_NOT_SUPPORTED; - - rv = hsl_port_prop_get_phyid(dev_id, port_id, &phy_id); - SW_RTN_ON_ERROR(rv); - - rv = phy_drv->phy_speed_get(dev_id, phy_id, pspeed); - - return rv; -} - -static sw_error_t -_garuda_port_autoneg_status_get(a_uint32_t dev_id, fal_port_t port_id, - a_bool_t * status) -{ - a_uint32_t phy_id; - sw_error_t rv; - hsl_phy_ops_t *phy_drv; - - HSL_DEV_ID_CHECK(dev_id); - - if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_PHY)) - { - return SW_BAD_PARAM; - } - - SW_RTN_ON_NULL (phy_drv = hsl_phy_api_ops_get (dev_id)); - if (NULL == phy_drv->phy_autoneg_status_get) - return SW_NOT_SUPPORTED; - - rv = hsl_port_prop_get_phyid(dev_id, port_id, &phy_id); - SW_RTN_ON_ERROR(rv); - - *status = phy_drv->phy_autoneg_status_get (dev_id, phy_id); - - return SW_OK; -} - -static sw_error_t -_garuda_port_autoneg_enable(a_uint32_t dev_id, fal_port_t port_id) -{ - sw_error_t rv; - a_uint32_t phy_id; - hsl_phy_ops_t *phy_drv; - - HSL_DEV_ID_CHECK(dev_id); - - if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_PHY)) - { - return SW_BAD_PARAM; - } - - SW_RTN_ON_NULL (phy_drv = hsl_phy_api_ops_get (dev_id)); - if (NULL == phy_drv->phy_autoneg_enable_set) - return SW_NOT_SUPPORTED; - - rv = hsl_port_prop_get_phyid(dev_id, port_id, &phy_id); - SW_RTN_ON_ERROR(rv); - - rv = phy_drv->phy_autoneg_enable_set(dev_id, phy_id); - return rv; -} - -static sw_error_t -_garuda_port_autoneg_restart(a_uint32_t dev_id, fal_port_t port_id) -{ - sw_error_t rv; - a_uint32_t phy_id; - hsl_phy_ops_t *phy_drv; - - HSL_DEV_ID_CHECK(dev_id); - - if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_PHY)) - { - return SW_BAD_PARAM; - } - - SW_RTN_ON_NULL (phy_drv = hsl_phy_api_ops_get (dev_id)); - if (NULL == phy_drv->phy_restart_autoneg) - return SW_NOT_SUPPORTED; - - rv = hsl_port_prop_get_phyid(dev_id, port_id, &phy_id); - SW_RTN_ON_ERROR(rv); - - rv = phy_drv->phy_restart_autoneg(dev_id, phy_id); - return rv; -} - - -static sw_error_t -_garuda_port_autoneg_adv_set(a_uint32_t dev_id, fal_port_t port_id, - a_uint32_t autoadv) -{ - sw_error_t rv; - a_uint32_t phy_id; - hsl_phy_ops_t *phy_drv; - - HSL_DEV_ID_CHECK(dev_id); - - if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_PHY)) - { - return SW_BAD_PARAM; - } - - SW_RTN_ON_NULL (phy_drv = hsl_phy_api_ops_get (dev_id)); - if (NULL == phy_drv->phy_autoneg_adv_set) - return SW_NOT_SUPPORTED; - - rv = hsl_port_prop_get_phyid(dev_id, port_id, &phy_id); - SW_RTN_ON_ERROR(rv); - - rv = phy_drv->phy_autoneg_adv_set(dev_id, phy_id, autoadv); - SW_RTN_ON_ERROR(rv); - - return SW_OK; -} - - -static sw_error_t -_garuda_port_autoneg_adv_get(a_uint32_t dev_id, fal_port_t port_id, - a_uint32_t * autoadv) -{ - sw_error_t rv; - a_uint32_t phy_id; - hsl_phy_ops_t *phy_drv; - - HSL_DEV_ID_CHECK(dev_id); - - if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_PHY)) - { - return SW_BAD_PARAM; - } - - SW_RTN_ON_NULL (phy_drv = hsl_phy_api_ops_get (dev_id)); - if (NULL == phy_drv->phy_autoneg_adv_get) - return SW_NOT_SUPPORTED; - - rv = hsl_port_prop_get_phyid(dev_id, port_id, &phy_id); - SW_RTN_ON_ERROR(rv); - - *autoadv = 0; - rv = phy_drv->phy_autoneg_adv_get(dev_id, phy_id, autoadv); - SW_RTN_ON_ERROR(rv); - - return SW_OK; -} - -static sw_error_t -_garuda_port_hdr_status_set(a_uint32_t dev_id, fal_port_t port_id, - a_bool_t enable) -{ - sw_error_t rv; - a_uint32_t val; - - HSL_DEV_ID_CHECK(dev_id); - - if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU)) - { - return SW_BAD_PARAM; - } - - if (A_TRUE == enable) - { - val = 1; - } - else if (A_FALSE == enable) - { - val = 0; - } - else - { - return SW_BAD_PARAM; - } - - HSL_REG_FIELD_SET(rv, dev_id, PORT_CTL, port_id, HEAD_EN, - (a_uint8_t *) (&val), sizeof (a_uint32_t)); - - return rv; -} - -static sw_error_t -_garuda_port_hdr_status_get(a_uint32_t dev_id, fal_port_t port_id, - a_bool_t * enable) -{ - sw_error_t rv; - a_uint32_t val; - - HSL_DEV_ID_CHECK(dev_id); - - if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU)) - { - return SW_BAD_PARAM; - } - - HSL_REG_FIELD_GET(rv, dev_id, PORT_CTL, port_id, HEAD_EN, - (a_uint8_t *) (&val), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - - if (1 == val) - { - *enable = A_TRUE; - } - else - { - *enable = A_FALSE; - } - - return rv; -} - -static sw_error_t -_garuda_port_flowctrl_set(a_uint32_t dev_id, fal_port_t port_id, a_bool_t enable) -{ - sw_error_t rv; - a_uint32_t val, force, reg; - - if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU)) - { - return SW_BAD_PARAM; - } - - if (A_TRUE == enable) - { - val = 1; - } - else if (A_FALSE == enable) - { - val = 0; - } - else - { - return SW_BAD_PARAM; - } - - HSL_REG_ENTRY_GET(rv, dev_id, PORT_STATUS, port_id, - (a_uint8_t *) (®), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - - SW_GET_FIELD_BY_REG(PORT_STATUS, FLOW_LINK_EN, force, reg); - if (force) - { - /* flow control isn't in force mode so can't set */ - return SW_DISABLE; - } - - SW_SET_REG_BY_FIELD(PORT_STATUS, RX_FLOW_EN, val, reg); - SW_SET_REG_BY_FIELD(PORT_STATUS, TX_FLOW_EN, val, reg); - SW_SET_REG_BY_FIELD(PORT_STATUS, TX_HALF_FLOW_EN, val, reg); - - HSL_REG_ENTRY_SET(rv, dev_id, PORT_STATUS, port_id, - (a_uint8_t *) (®), sizeof (a_uint32_t)); - return rv; -} - - -static sw_error_t -_garuda_port_flowctrl_get(a_uint32_t dev_id, fal_port_t port_id, - a_bool_t * enable) -{ - sw_error_t rv; - a_uint32_t tx, rx, reg; - - if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU)) - { - return SW_BAD_PARAM; - } - - HSL_REG_ENTRY_GET(rv, dev_id, PORT_STATUS, port_id, - (a_uint8_t *) (®), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - - SW_GET_FIELD_BY_REG(PORT_STATUS, RX_FLOW_EN, rx, reg); - SW_GET_FIELD_BY_REG(PORT_STATUS, TX_FLOW_EN, tx, reg); - - if (1 == rx) - { - *enable = A_TRUE; - } - else - { - *enable = A_FALSE; - } - - return SW_OK; -} - -static sw_error_t -_garuda_port_flowctrl_forcemode_set(a_uint32_t dev_id, fal_port_t port_id, - a_bool_t enable) -{ - sw_error_t rv; - a_uint32_t force, reg; - - if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU)) - { - return SW_BAD_PARAM; - } - - HSL_REG_ENTRY_GET(rv, dev_id, PORT_STATUS, port_id, - (a_uint8_t *) (®), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - - SW_GET_FIELD_BY_REG(PORT_STATUS, FLOW_LINK_EN, force, reg); - if (force != (a_uint32_t) enable) - { - return SW_OK; - } - - if (A_TRUE == enable) - { - SW_SET_REG_BY_FIELD(PORT_STATUS, FLOW_LINK_EN, 0, reg); - SW_SET_REG_BY_FIELD(PORT_STATUS, TX_FLOW_EN, 0, reg); - SW_SET_REG_BY_FIELD(PORT_STATUS, RX_FLOW_EN, 0, reg); - } - else if (A_FALSE == enable) - { - SW_SET_REG_BY_FIELD(PORT_STATUS, FLOW_LINK_EN, 1, reg); - } - else - { - return SW_BAD_PARAM; - } - SW_SET_REG_BY_FIELD(PORT_STATUS, TX_HALF_FLOW_EN, 0, reg); - - HSL_REG_ENTRY_SET(rv, dev_id, PORT_STATUS, port_id, - (a_uint8_t *) (®), sizeof (a_uint32_t)); - return rv; -} - -static sw_error_t -_garuda_port_flowctrl_forcemode_get(a_uint32_t dev_id, fal_port_t port_id, - a_bool_t * enable) -{ - sw_error_t rv; - a_uint32_t force, reg; - - if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU)) - { - return SW_BAD_PARAM; - } - - HSL_REG_ENTRY_GET(rv, dev_id, PORT_STATUS, port_id, - (a_uint8_t *) (®), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - - SW_GET_FIELD_BY_REG(PORT_STATUS, FLOW_LINK_EN, force, reg); - if (0 == force) - { - *enable = A_TRUE; - } - else - { - *enable = A_FALSE; - } - - return SW_OK; -} - -static sw_error_t -_garuda_port_powersave_set(a_uint32_t dev_id, fal_port_t port_id, - a_bool_t enable) -{ - sw_error_t rv; - a_uint32_t phy_id = 0; - hsl_phy_ops_t *phy_drv; - - HSL_DEV_ID_CHECK(dev_id); - - if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_PHY)) - { - return SW_BAD_PARAM; - } - - SW_RTN_ON_NULL (phy_drv = hsl_phy_api_ops_get (dev_id)); - if (NULL == phy_drv->phy_powersave_set) - return SW_NOT_SUPPORTED; - - rv = hsl_port_prop_get_phyid(dev_id, port_id, &phy_id); - SW_RTN_ON_ERROR(rv); - - rv = phy_drv->phy_powersave_set(dev_id, phy_id, enable); - - return rv; -} - -static sw_error_t -_garuda_port_powersave_get(a_uint32_t dev_id, fal_port_t port_id, - a_bool_t *enable) -{ - sw_error_t rv; - a_uint32_t phy_id = 0; - hsl_phy_ops_t *phy_drv; - - HSL_DEV_ID_CHECK(dev_id); - - if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_PHY)) - { - return SW_BAD_PARAM; - } - - SW_RTN_ON_NULL (phy_drv = hsl_phy_api_ops_get (dev_id)); - if (NULL == phy_drv->phy_powersave_get) - return SW_NOT_SUPPORTED; - - rv = hsl_port_prop_get_phyid(dev_id, port_id, &phy_id); - SW_RTN_ON_ERROR(rv); - - rv = phy_drv->phy_powersave_get(dev_id, phy_id, enable); - - return rv; -} - -static sw_error_t -_garuda_port_hibernate_set(a_uint32_t dev_id, fal_port_t port_id, - a_bool_t enable) -{ - sw_error_t rv; - a_uint32_t phy_id = 0; - hsl_phy_ops_t *phy_drv; - - HSL_DEV_ID_CHECK(dev_id); - - if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_PHY)) - { - return SW_BAD_PARAM; - } - - SW_RTN_ON_NULL (phy_drv = hsl_phy_api_ops_get (dev_id)); - if (NULL == phy_drv->phy_hibernation_set) - return SW_NOT_SUPPORTED; - - rv = hsl_port_prop_get_phyid(dev_id, port_id, &phy_id); - SW_RTN_ON_ERROR(rv); - - rv = phy_drv->phy_hibernation_set(dev_id, phy_id, enable); - - return rv; -} - -static sw_error_t -_garuda_port_hibernate_get(a_uint32_t dev_id, fal_port_t port_id, - a_bool_t *enable) -{ - sw_error_t rv; - a_uint32_t phy_id = 0; - hsl_phy_ops_t *phy_drv; - - HSL_DEV_ID_CHECK(dev_id); - - if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_PHY)) - { - return SW_BAD_PARAM; - } - - SW_RTN_ON_NULL (phy_drv = hsl_phy_api_ops_get (dev_id)); - if (NULL == phy_drv->phy_hibernation_get) - return SW_NOT_SUPPORTED; - - rv = hsl_port_prop_get_phyid(dev_id, port_id, &phy_id); - SW_RTN_ON_ERROR(rv); - - rv = phy_drv->phy_hibernation_get(dev_id, phy_id, enable); - - return rv; -} - -static sw_error_t -_garuda_port_cdt(a_uint32_t dev_id, fal_port_t port_id, a_uint32_t mdi_pair, - fal_cable_status_t *cable_status, a_uint32_t *cable_len) -{ - sw_error_t rv; - a_uint32_t phy_id = 0; - hsl_phy_ops_t *phy_drv; - - HSL_DEV_ID_CHECK(dev_id); - - if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_PHY)) - { - return SW_BAD_PARAM; - } - - SW_RTN_ON_NULL (phy_drv = hsl_phy_api_ops_get (dev_id)); - if (NULL == phy_drv->phy_cdt) - return SW_NOT_SUPPORTED; - - rv = hsl_port_prop_get_phyid(dev_id, port_id, &phy_id); - SW_RTN_ON_ERROR(rv); - - rv = phy_drv->phy_cdt(dev_id, phy_id, mdi_pair, cable_status, cable_len); - - return rv; -} - -/** - * @brief Set duplex mode on a particular port. - * @param[in] dev_id device id - * @param[in] port_id port id - * @param[in] duplex duplex mode - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -garuda_port_duplex_set(a_uint32_t dev_id, fal_port_t port_id, - fal_port_duplex_t duplex) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _garuda_port_duplex_set(dev_id, port_id, duplex); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Get duplex mode on a particular port. - * @param[in] dev_id device id - * @param[in] port_id port id - * @param[out] duplex duplex mode - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -garuda_port_duplex_get(a_uint32_t dev_id, fal_port_t port_id, - fal_port_duplex_t * pduplex) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _garuda_port_duplex_get(dev_id, port_id, pduplex); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Set speed on a particular port. - * @param[in] dev_id device id - * @param[in] port_id port id - * @param[in] speed port speed - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -garuda_port_speed_set(a_uint32_t dev_id, fal_port_t port_id, - fal_port_speed_t speed) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _garuda_port_speed_set(dev_id, port_id, speed); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Get speed on a particular port. - * @param[in] dev_id device id - * @param[in] port_id port id - * @param[out] speed port speed - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -garuda_port_speed_get(a_uint32_t dev_id, fal_port_t port_id, - fal_port_speed_t * pspeed) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _garuda_port_speed_get(dev_id, port_id, pspeed); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Get auto negotiation status on a particular port. - * @param[in] dev_id device id - * @param[in] port_id port id - * @param[out] status A_TRUE or A_FALSE - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -garuda_port_autoneg_status_get(a_uint32_t dev_id, fal_port_t port_id, - a_bool_t * status) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _garuda_port_autoneg_status_get(dev_id, port_id, status); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Enable auto negotiation status on a particular port. - * @param[in] dev_id device id - * @param[in] port_id port id - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -garuda_port_autoneg_enable(a_uint32_t dev_id, fal_port_t port_id) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _garuda_port_autoneg_enable(dev_id, port_id); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Restart auto negotiation procedule on a particular port. - * @param[in] dev_id device id - * @param[in] port_id port id - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -garuda_port_autoneg_restart(a_uint32_t dev_id, fal_port_t port_id) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _garuda_port_autoneg_restart(dev_id, port_id); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Set auto negotiation advtisement ability on a particular port. - * @details Comments: - * auto negotiation advtisement ability is defined by macro such as - * FAL_PHY_ADV_10T_HD, FAL_PHY_ADV_PAUSE... - * @param[in] dev_id device id - * @param[in] port_id port id - * @param[in] autoadv auto negotiation advtisement ability bit map - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -garuda_port_autoneg_adv_set(a_uint32_t dev_id, fal_port_t port_id, - a_uint32_t autoadv) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _garuda_port_autoneg_adv_set(dev_id, port_id, autoadv); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Get auto negotiation advtisement ability on a particular port. - * @param[in] dev_id device id - * @param[in] port_id port id - * @param[out] autoadv auto negotiation advtisement ability bit map - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -garuda_port_autoneg_adv_get(a_uint32_t dev_id, fal_port_t port_id, - a_uint32_t * autoadv) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _garuda_port_autoneg_adv_get(dev_id, port_id, autoadv); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Set status of Atheros header packets parsed on a particular port. - * @param[in] dev_id device id - * @param[in] port_id port id - * @param[in] enable A_TRUE or A_FALSE - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -garuda_port_hdr_status_set(a_uint32_t dev_id, fal_port_t port_id, - a_bool_t enable) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _garuda_port_hdr_status_set(dev_id, port_id, enable); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Get status of Atheros header packets parsed on a particular port. - * @param[in] dev_id device id - * @param[in] port_id port id - * @param[out] enable A_TRUE or A_FALSE - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -garuda_port_hdr_status_get(a_uint32_t dev_id, fal_port_t port_id, - a_bool_t * enable) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _garuda_port_hdr_status_get(dev_id, port_id, enable); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Set flow control status on a particular port. - * @param[in] dev_id device id - * @param[in] port_id port id - * @param[in] enable A_TRUE or A_FALSE - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -garuda_port_flowctrl_set(a_uint32_t dev_id, fal_port_t port_id, a_bool_t enable) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _garuda_port_flowctrl_set(dev_id, port_id, enable); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Get flow control status on a particular port. - * @param[in] dev_id device id - * @param[in] port_id port id - * @param[out] enable A_TRUE or A_FALSE - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -garuda_port_flowctrl_get(a_uint32_t dev_id, fal_port_t port_id, - a_bool_t * enable) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _garuda_port_flowctrl_get(dev_id, port_id, enable); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Set flow control force mode on a particular port. - * @param[in] dev_id device id - * @param[in] port_id port id - * @param[out] enable A_TRUE or A_FALSE - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -garuda_port_flowctrl_forcemode_set(a_uint32_t dev_id, fal_port_t port_id, - a_bool_t enable) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _garuda_port_flowctrl_forcemode_set(dev_id, port_id, enable); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Get flow control force mode on a particular port. - * @param[in] dev_id device id - * @param[in] port_id port id - * @param[out] enable A_TRUE or A_FALSE - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -garuda_port_flowctrl_forcemode_get(a_uint32_t dev_id, fal_port_t port_id, - a_bool_t * enable) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _garuda_port_flowctrl_forcemode_get(dev_id, port_id, enable); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Set powersaving status on a particular port. - * @param[in] dev_id device id - * @param[in] port_id port id - * @param[out] enable A_TRUE or A_FALSE - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -garuda_port_powersave_set(a_uint32_t dev_id, fal_port_t port_id, - a_bool_t enable) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _garuda_port_powersave_set(dev_id, port_id, enable); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Get powersaving status on a particular port. - * @param[in] dev_id device id - * @param[in] port_id port id - * @param[out] enable A_TRUE or A_FALSE - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -garuda_port_powersave_get(a_uint32_t dev_id, fal_port_t port_id, - a_bool_t *enable) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _garuda_port_powersave_get(dev_id, port_id, enable); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Set hibernate status on a particular port. - * @param[in] dev_id device id - * @param[in] port_id port id - * @param[out] enable A_TRUE or A_FALSE - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -garuda_port_hibernate_set(a_uint32_t dev_id, fal_port_t port_id, - a_bool_t enable) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _garuda_port_hibernate_set(dev_id, port_id, enable); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Get hibernate status on a particular port. - * @param[in] dev_id device id - * @param[in] port_id port id - * @param[out] enable A_TRUE or A_FALSE - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -garuda_port_hibernate_get(a_uint32_t dev_id, fal_port_t port_id, - a_bool_t *enable) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _garuda_port_hibernate_get(dev_id, port_id, enable); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Run cable diagnostic test on a particular port. - * @param[in] dev_id device id - * @param[in] port_id port id - * @param[in] mdi_pair mdi pair id - * @param[out] cable_status cable status - * @param[out] cable_len cable len - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -garuda_port_cdt(a_uint32_t dev_id, fal_port_t port_id, a_uint32_t mdi_pair, - fal_cable_status_t *cable_status, a_uint32_t *cable_len) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _garuda_port_cdt(dev_id, port_id, mdi_pair, cable_status, cable_len); - HSL_API_UNLOCK; - return rv; -} - -sw_error_t -garuda_port_ctrl_init(a_uint32_t dev_id) -{ - HSL_DEV_ID_CHECK(dev_id); - -#ifndef HSL_STANDALONG - { - hsl_api_t *p_api; - - SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id)); - - p_api->port_duplex_get = garuda_port_duplex_get; - p_api->port_duplex_set = garuda_port_duplex_set; - p_api->port_speed_get = garuda_port_speed_get; - p_api->port_speed_set = garuda_port_speed_set; - p_api->port_autoneg_status_get = garuda_port_autoneg_status_get; - p_api->port_autoneg_enable = garuda_port_autoneg_enable; - p_api->port_autoneg_restart = garuda_port_autoneg_restart; - p_api->port_autoneg_adv_get = garuda_port_autoneg_adv_get; - p_api->port_autoneg_adv_set = garuda_port_autoneg_adv_set; - p_api->port_hdr_status_set = garuda_port_hdr_status_set; - p_api->port_hdr_status_get = garuda_port_hdr_status_get; - p_api->port_flowctrl_set = garuda_port_flowctrl_set; - p_api->port_flowctrl_get = garuda_port_flowctrl_get; - p_api->port_flowctrl_forcemode_set = garuda_port_flowctrl_forcemode_set; - p_api->port_flowctrl_forcemode_get = garuda_port_flowctrl_forcemode_get; - p_api->port_powersave_set = garuda_port_powersave_set; - p_api->port_powersave_get = garuda_port_powersave_get; - p_api->port_hibernate_set = garuda_port_hibernate_set; - p_api->port_hibernate_get = garuda_port_hibernate_get; - p_api->port_cdt = garuda_port_cdt; - - } -#endif - - return SW_OK; -} - -/** - * @} - */ - diff --git a/feeds/ipq807x/qca-ssdk/src/src/hsl/garuda/garuda_portvlan.c b/feeds/ipq807x/qca-ssdk/src/src/hsl/garuda/garuda_portvlan.c deleted file mode 100755 index 38986bcac..000000000 --- a/feeds/ipq807x/qca-ssdk/src/src/hsl/garuda/garuda_portvlan.c +++ /dev/null @@ -1,912 +0,0 @@ -/* - * Copyright (c) 2012, The Linux Foundation. All rights reserved. - * Permission to use, copy, modify, and/or distribute this software for - * any purpose with or without fee is hereby granted, provided that the - * above copyright notice and this permission notice appear in all copies. - * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES - * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR - * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES - * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN - * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT - * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. - */ - - - -/** - * @defgroup garuda_port_vlan GARUDA_PORT_VLAN - * @{ - */ -#include "sw.h" -#include "hsl.h" -#include "hsl_dev.h" -#include "hsl_port_prop.h" -#include "garuda_portvlan.h" -#include "garuda_reg.h" - -#define MAX_VLAN_ID 4095 - - -static sw_error_t -_garuda_port_1qmode_set(a_uint32_t dev_id, fal_port_t port_id, - fal_pt_1qmode_t port_1qmode) -{ - sw_error_t rv; - a_uint32_t regval[FAL_1Q_MODE_BUTT] = { 0, 3, 2, 1 }; - - HSL_DEV_ID_CHECK(dev_id); - - if (A_FALSE == hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU)) - { - return SW_BAD_PARAM; - } - - if (FAL_1Q_MODE_BUTT <= port_1qmode) - { - return SW_BAD_PARAM; - } - - HSL_REG_FIELD_SET(rv, dev_id, PORT_BASE_VLAN, port_id, DOT1Q_MODE, - (a_uint8_t *) (®val[port_1qmode]), - sizeof (a_uint32_t)); - - return rv; - -} - - -static sw_error_t -_garuda_port_1qmode_get(a_uint32_t dev_id, fal_port_t port_id, - fal_pt_1qmode_t * pport_1qmode) -{ - sw_error_t rv; - a_uint32_t regval = 0; - fal_pt_1qmode_t retval[4] = { FAL_1Q_DISABLE, FAL_1Q_FALLBACK, - FAL_1Q_CHECK, FAL_1Q_SECURE - }; - - HSL_DEV_ID_CHECK(dev_id); - - if (A_FALSE == hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU)) - { - return SW_BAD_PARAM; - } - - SW_RTN_ON_NULL(pport_1qmode); - - HSL_REG_FIELD_GET(rv, dev_id, PORT_BASE_VLAN, port_id, DOT1Q_MODE, - (a_uint8_t *) (®val), sizeof (a_uint32_t)); - - SW_RTN_ON_ERROR(rv); - - *pport_1qmode = retval[regval & 0x3]; - - return SW_OK; - -} - - -static sw_error_t -_garuda_port_egvlanmode_set(a_uint32_t dev_id, fal_port_t port_id, - fal_pt_1q_egmode_t port_egvlanmode) -{ - sw_error_t rv; - a_uint32_t regval[FAL_EG_MODE_BUTT] = { 0, 1, 2, 3 }; - - HSL_DEV_ID_CHECK(dev_id); - - if (A_FALSE == hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU)) - { - return SW_BAD_PARAM; - } - - if (FAL_EG_MODE_BUTT <= port_egvlanmode) - { - return SW_BAD_PARAM; - } - - if (FAL_EG_HYBRID == port_egvlanmode) - { - return SW_NOT_SUPPORTED; - } - - HSL_REG_FIELD_SET(rv, dev_id, PORT_CTL, port_id, EG_VLAN_MODE, - (a_uint8_t *) (®val[port_egvlanmode]), - sizeof (a_uint32_t)); - - return rv; - -} - - -static sw_error_t -_garuda_port_egvlanmode_get(a_uint32_t dev_id, fal_port_t port_id, - fal_pt_1q_egmode_t * pport_egvlanmode) -{ - sw_error_t rv; - a_uint32_t regval = 0; - fal_pt_1q_egmode_t retval[3] = { FAL_EG_UNMODIFIED, FAL_EG_UNTAGGED, - FAL_EG_TAGGED - }; - - HSL_DEV_ID_CHECK(dev_id); - - if (A_FALSE == hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU)) - { - return SW_BAD_PARAM; - } - - SW_RTN_ON_NULL(pport_egvlanmode); - - HSL_REG_FIELD_GET(rv, dev_id, PORT_CTL, port_id, EG_VLAN_MODE, - (a_uint8_t *) (®val), sizeof (a_uint32_t)); - - SW_RTN_ON_ERROR(rv); - - *pport_egvlanmode = retval[regval & 0x3]; - - return SW_OK; - -} - - -static sw_error_t -_garuda_portvlan_member_add(a_uint32_t dev_id, fal_port_t port_id, - a_uint32_t mem_port_id) -{ - sw_error_t rv; - a_uint32_t regval = 0; - - HSL_DEV_ID_CHECK(dev_id); - - if (A_FALSE == hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU)) - { - return SW_BAD_PARAM; - } - - if (A_FALSE == hsl_port_prop_check(dev_id, mem_port_id, HSL_PP_INCL_CPU)) - { - return SW_BAD_PARAM; - } - - HSL_REG_FIELD_GET(rv, dev_id, PORT_BASE_VLAN, port_id, - PORT_VID_MEM, (a_uint8_t *) (®val), - sizeof (a_uint32_t)); - - SW_RTN_ON_ERROR(rv); - - regval |= (0x1UL << mem_port_id); - - HSL_REG_FIELD_SET(rv, dev_id, PORT_BASE_VLAN, port_id, - PORT_VID_MEM, (a_uint8_t *) (®val), - sizeof (a_uint32_t)); - - return rv; - -} - -static sw_error_t -_garuda_portvlan_member_del(a_uint32_t dev_id, fal_port_t port_id, - a_uint32_t mem_port_id) -{ - sw_error_t rv; - a_uint32_t regval = 0; - - HSL_DEV_ID_CHECK(dev_id); - - if (A_FALSE == hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU)) - { - return SW_BAD_PARAM; - } - - if (A_FALSE == hsl_port_prop_check(dev_id, mem_port_id, HSL_PP_INCL_CPU)) - { - return SW_BAD_PARAM; - } - - HSL_REG_FIELD_GET(rv, dev_id, PORT_BASE_VLAN, port_id, - PORT_VID_MEM, (a_uint8_t *) (®val), - sizeof (a_uint32_t)); - - SW_RTN_ON_ERROR(rv); - - regval &= (~(0x1UL << mem_port_id)); - - HSL_REG_FIELD_SET(rv, dev_id, PORT_BASE_VLAN, port_id, - PORT_VID_MEM, (a_uint8_t *) (®val), - sizeof (a_uint32_t)); - - return rv; - -} - - -static sw_error_t -_garuda_portvlan_member_update(a_uint32_t dev_id, fal_port_t port_id, - fal_pbmp_t mem_port_map) -{ - sw_error_t rv; - - HSL_DEV_ID_CHECK(dev_id); - - if (A_FALSE == hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU)) - { - return SW_BAD_PARAM; - } - - if (A_FALSE == - hsl_mports_prop_check(dev_id, mem_port_map, HSL_PP_INCL_CPU)) - { - return SW_BAD_PARAM; - } - - HSL_REG_FIELD_SET(rv, dev_id, PORT_BASE_VLAN, port_id, - PORT_VID_MEM, (a_uint8_t *) (&mem_port_map), - sizeof (a_uint32_t)); - - return rv; -} - - -static sw_error_t -_garuda_portvlan_member_get(a_uint32_t dev_id, fal_port_t port_id, - fal_pbmp_t * mem_port_map) -{ - sw_error_t rv; - - HSL_DEV_ID_CHECK(dev_id); - - if (A_FALSE == hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU)) - { - return SW_BAD_PARAM; - } - - *mem_port_map = 0; - HSL_REG_FIELD_GET(rv, dev_id, PORT_BASE_VLAN, port_id, - PORT_VID_MEM, (a_uint8_t *) mem_port_map, - sizeof (a_uint32_t)); - - SW_RTN_ON_ERROR(rv); - - return SW_OK; -} - -static sw_error_t -_garuda_port_default_vid_set(a_uint32_t dev_id, fal_port_t port_id, a_uint32_t vid) -{ - sw_error_t rv; - a_uint32_t val; - - HSL_DEV_ID_CHECK(dev_id); - - if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU)) - { - return SW_BAD_PARAM; - } - - if ((0 == vid) || (vid > MAX_VLAN_ID)) - { - return SW_BAD_PARAM; - } - - val = vid; - HSL_REG_FIELD_SET(rv, dev_id, PORT_BASE_VLAN, port_id, - PORT_VID, (a_uint8_t *) (&val), - sizeof (a_uint32_t)); - - return rv; -} - - -static sw_error_t -_garuda_port_default_vid_get(a_uint32_t dev_id, fal_port_t port_id, a_uint32_t *vid) -{ - sw_error_t rv; - a_uint32_t val; - - HSL_DEV_ID_CHECK(dev_id); - - if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU)) - { - return SW_BAD_PARAM; - } - - HSL_REG_FIELD_GET(rv, dev_id, PORT_BASE_VLAN, port_id, - PORT_VID, (a_uint8_t *) (&val), - sizeof (a_uint32_t)); - - *vid = val & 0xfff; - return rv; -} - -static sw_error_t -_garuda_port_force_default_vid_set(a_uint32_t dev_id, fal_port_t port_id, a_bool_t enable) -{ - sw_error_t rv; - a_uint32_t val; - - HSL_DEV_ID_CHECK(dev_id); - - if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU)) - { - return SW_BAD_PARAM; - } - - if (A_TRUE == enable) - { - val = 1; - } - else if (A_FALSE == enable) - { - val = 0; - } - else - { - return SW_BAD_PARAM; - } - - HSL_REG_FIELD_SET(rv, dev_id, PORT_BASE_VLAN, port_id, - FORCE_DEF_VID, (a_uint8_t *) (&val), - sizeof (a_uint32_t)); - return rv; -} - -static sw_error_t -_garuda_port_force_default_vid_get(a_uint32_t dev_id, fal_port_t port_id, a_bool_t * enable) -{ - sw_error_t rv; - a_uint32_t val; - - HSL_DEV_ID_CHECK(dev_id); - - if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU)) - { - return SW_BAD_PARAM; - } - - HSL_REG_FIELD_GET(rv, dev_id, PORT_BASE_VLAN, port_id, - FORCE_DEF_VID, (a_uint8_t *) (&val), - sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - - if (val) - { - *enable = A_TRUE; - } - else - { - *enable = A_FALSE; - } - - return SW_OK; -} - - -static sw_error_t -_garuda_port_force_portvlan_set(a_uint32_t dev_id, fal_port_t port_id, a_bool_t enable) -{ - sw_error_t rv; - a_uint32_t val; - - HSL_DEV_ID_CHECK(dev_id); - - if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU)) - { - return SW_BAD_PARAM; - } - - if (A_TRUE == enable) - { - val = 1; - } - else if (A_FALSE == enable) - { - val = 0; - } - else - { - return SW_BAD_PARAM; - } - - HSL_REG_FIELD_SET(rv, dev_id, PORT_BASE_VLAN, port_id, - FORCE_PVLAN, (a_uint8_t *) (&val), - sizeof (a_uint32_t)); - return rv; -} - - -static sw_error_t -_garuda_port_force_portvlan_get(a_uint32_t dev_id, fal_port_t port_id, a_bool_t * enable) -{ - sw_error_t rv; - a_uint32_t val; - - HSL_DEV_ID_CHECK(dev_id); - - if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU)) - { - return SW_BAD_PARAM; - } - - HSL_REG_FIELD_GET(rv, dev_id, PORT_BASE_VLAN, port_id, - FORCE_PVLAN, (a_uint8_t *) (&val), - sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - - if (val) - { - *enable = A_TRUE; - } - else - { - *enable = A_FALSE; - } - - return SW_OK; -} - -static sw_error_t -_garuda_port_nestvlan_set(a_uint32_t dev_id, fal_port_t port_id, a_bool_t enable) -{ - sw_error_t rv; - a_uint32_t val; - - HSL_DEV_ID_CHECK(dev_id); - - if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_EXCL_CPU)) - { - return SW_BAD_PARAM; - } - - if (A_TRUE == enable) - { - val = 1; - } - else if (A_FALSE == enable) - { - val = 0; - } - else - { - return SW_BAD_PARAM; - } - - HSL_REG_FIELD_SET(rv, dev_id, PORT_CTL, port_id, - DTAG_EN, (a_uint8_t *) (&val), - sizeof (a_uint32_t)); - return rv; -} - - -static sw_error_t -_garuda_port_nestvlan_get(a_uint32_t dev_id, fal_port_t port_id, a_bool_t *enable) -{ - sw_error_t rv; - a_uint32_t val; - - HSL_DEV_ID_CHECK(dev_id); - - if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_EXCL_CPU)) - { - return SW_BAD_PARAM; - } - - HSL_REG_FIELD_GET(rv, dev_id, PORT_CTL, port_id, - DTAG_EN, (a_uint8_t *) (&val), - sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - - if (1 == val) - { - *enable = A_TRUE; - } - else - { - *enable = A_FALSE; - } - - return SW_OK; -} - - -static sw_error_t -_garuda_nestvlan_tpid_set(a_uint32_t dev_id, a_uint32_t tpid) -{ - sw_error_t rv; - a_uint32_t val; - - HSL_DEV_ID_CHECK(dev_id); - - val = tpid; - HSL_REG_FIELD_SET(rv, dev_id, SERVICE_TAG, 0, - TAG_VALUE, (a_uint8_t *) (&val), - sizeof (a_uint32_t)); - return rv; -} - - -static sw_error_t -_garuda_nestvlan_tpid_get(a_uint32_t dev_id, a_uint32_t *tpid) -{ - sw_error_t rv; - a_uint32_t val; - - HSL_DEV_ID_CHECK(dev_id); - - HSL_REG_FIELD_GET(rv, dev_id, SERVICE_TAG, 0, - TAG_VALUE, (a_uint8_t *) (&val), - sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - - *tpid = val; - return SW_OK; -} - -/** - * @brief Set 802.1q work mode on a particular port. - * @param[in] dev_id device id - * @param[in] port_id port id - * @param[in] port_1qmode 802.1q work mode - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -garuda_port_1qmode_set(a_uint32_t dev_id, fal_port_t port_id, - fal_pt_1qmode_t port_1qmode) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _garuda_port_1qmode_set(dev_id, port_id, port_1qmode); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Get 802.1q work mode on a particular port. - * @param[in] dev_id device id - * @param[in] port_id port id - * @param[out] port_1qmode 802.1q work mode - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -garuda_port_1qmode_get(a_uint32_t dev_id, fal_port_t port_id, - fal_pt_1qmode_t * pport_1qmode) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _garuda_port_1qmode_get(dev_id, port_id, pport_1qmode); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Set packets transmitted out vlan tagged mode on a particular port. - * @param[in] dev_id device id - * @param[in] port_id port id - * @param[in] port_egvlanmode packets transmitted out vlan tagged mode - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -garuda_port_egvlanmode_set(a_uint32_t dev_id, fal_port_t port_id, - fal_pt_1q_egmode_t port_egvlanmode) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _garuda_port_egvlanmode_set(dev_id, port_id, port_egvlanmode); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Get packets transmitted out vlan tagged mode on a particular port. - * @param[in] dev_id device id - * @param[in] port_id port id - * @param[out] port_egvlanmode packets transmitted out vlan tagged mode - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -garuda_port_egvlanmode_get(a_uint32_t dev_id, fal_port_t port_id, - fal_pt_1q_egmode_t * pport_egvlanmode) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _garuda_port_egvlanmode_get(dev_id, port_id, pport_egvlanmode); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Add member of port based vlan on a particular port. - * @param[in] dev_id device id - * @param[in] port_id port id - * @param[in] mem_port_id port member - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -garuda_portvlan_member_add(a_uint32_t dev_id, fal_port_t port_id, - a_uint32_t mem_port_id) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _garuda_portvlan_member_add(dev_id, port_id, mem_port_id); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Delete member of port based vlan on a particular port. - * @param[in] dev_id device id - * @param[in] port_id port id - * @param[in] mem_port_id port member - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -garuda_portvlan_member_del(a_uint32_t dev_id, fal_port_t port_id, - a_uint32_t mem_port_id) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _garuda_portvlan_member_del(dev_id, port_id, mem_port_id); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Update member of port based vlan on a particular port. - * @param[in] dev_id device id - * @param[in] port_id port id - * @param[in] mem_port_map port members - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -garuda_portvlan_member_update(a_uint32_t dev_id, fal_port_t port_id, - fal_pbmp_t mem_port_map) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _garuda_portvlan_member_update(dev_id, port_id, mem_port_map); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Get member of port based vlan on a particular port. - * @param[in] dev_id device id - * @param[in] port_id port id - * @param[out] mem_port_map port members - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -garuda_portvlan_member_get(a_uint32_t dev_id, fal_port_t port_id, - fal_pbmp_t * mem_port_map) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _garuda_portvlan_member_get(dev_id, port_id, mem_port_map); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Set default vlan id on a particular port. - * @param[in] dev_id device id - * @param[in] port_id port id - * @param[in] vid default vlan id - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -garuda_port_default_vid_set(a_uint32_t dev_id, fal_port_t port_id, a_uint32_t vid) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _garuda_port_default_vid_set(dev_id, port_id, vid); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Get default vlan id on a particular port. - * @param[in] dev_id device id - * @param[in] port_id port id - * @param[out] vid default vlan id - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -garuda_port_default_vid_get(a_uint32_t dev_id, fal_port_t port_id, a_uint32_t *vid) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _garuda_port_default_vid_get(dev_id, port_id, vid); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Set force default vlan id status on a particular port. - * @param[in] dev_id device id - * @param[in] port_id port id - * @param[in] enable A_TRUE or A_FALSE - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -garuda_port_force_default_vid_set(a_uint32_t dev_id, fal_port_t port_id, a_bool_t enable) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _garuda_port_force_default_vid_set(dev_id, port_id, enable); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Get force default vlan id status on a particular port. - * @param[in] dev_id device id - * @param[in] port_id port id - * @param[out] enable A_TRUE or A_FALSE - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -garuda_port_force_default_vid_get(a_uint32_t dev_id, fal_port_t port_id, a_bool_t * enable) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _garuda_port_force_default_vid_get(dev_id, port_id, enable); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Set force port based vlan status on a particular port. - * @param[in] dev_id device id - * @param[in] port_id port id - * @param[in] enable A_TRUE or A_FALSE - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -garuda_port_force_portvlan_set(a_uint32_t dev_id, fal_port_t port_id, a_bool_t enable) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _garuda_port_force_portvlan_set(dev_id, port_id, enable); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Get force port based vlan status on a particular port. - * @param[in] dev_id device id - * @param[in] port_id port id - * @param[out] enable A_TRUE or A_FALSE - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -garuda_port_force_portvlan_get(a_uint32_t dev_id, fal_port_t port_id, a_bool_t * enable) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _garuda_port_force_portvlan_get(dev_id, port_id, enable); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Set nest vlan feature status on a particular port. - * @param[in] dev_id device id - * @param[in] port_id port id - * @param[in] enable A_TRUE or A_FALSE - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -garuda_port_nestvlan_set(a_uint32_t dev_id, fal_port_t port_id, a_bool_t enable) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _garuda_port_nestvlan_set(dev_id, port_id, enable); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Get nest vlan feature status on a particular port. - * @param[in] dev_id device id - * @param[in] port_id port id - * @param[out] enable A_TRUE or A_FALSE - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -garuda_port_nestvlan_get(a_uint32_t dev_id, fal_port_t port_id, a_bool_t *enable) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _garuda_port_nestvlan_get(dev_id, port_id, enable); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Set nest vlan tpid on a particular device. - * @param[in] dev_id device id - * @param[in] tpid tag protocol identification - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -garuda_nestvlan_tpid_set(a_uint32_t dev_id, a_uint32_t tpid) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _garuda_nestvlan_tpid_set(dev_id, tpid); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Get nest vlan tpid on a particular device. - * @param[in] dev_id device id - * @param[out] tpid tag protocol identification - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -garuda_nestvlan_tpid_get(a_uint32_t dev_id, a_uint32_t *tpid) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _garuda_nestvlan_tpid_get(dev_id, tpid); - HSL_API_UNLOCK; - return rv; -} - -sw_error_t -garuda_portvlan_init(a_uint32_t dev_id) -{ - HSL_DEV_ID_CHECK(dev_id); - -#ifndef HSL_STANDALONG - hsl_api_t *p_api; - - SW_RTN_ON_NULL (p_api = hsl_api_ptr_get(dev_id)); - - p_api->port_1qmode_get = garuda_port_1qmode_get; - p_api->port_1qmode_set = garuda_port_1qmode_set; - p_api->port_egvlanmode_get = garuda_port_egvlanmode_get; - p_api->port_egvlanmode_set = garuda_port_egvlanmode_set; - p_api->portvlan_member_add = garuda_portvlan_member_add; - p_api->portvlan_member_del = garuda_portvlan_member_del; - p_api->portvlan_member_update = garuda_portvlan_member_update; - p_api->portvlan_member_get = garuda_portvlan_member_get; - p_api->port_default_vid_set = garuda_port_default_vid_set; - p_api->port_default_vid_get = garuda_port_default_vid_get; - p_api->port_force_default_vid_set = garuda_port_force_default_vid_set; - p_api->port_force_default_vid_get = garuda_port_force_default_vid_get; - p_api->port_force_portvlan_set = garuda_port_force_portvlan_set; - p_api->port_force_portvlan_get = garuda_port_force_portvlan_get; - p_api->port_nestvlan_set = garuda_port_nestvlan_set; - p_api->port_nestvlan_get = garuda_port_nestvlan_get; - p_api->nestvlan_tpid_set = garuda_nestvlan_tpid_set; - p_api->nestvlan_tpid_get = garuda_nestvlan_tpid_get; -#endif - - return SW_OK; -} - -/** - * @} - */ - diff --git a/feeds/ipq807x/qca-ssdk/src/src/hsl/garuda/garuda_qos.c b/feeds/ipq807x/qca-ssdk/src/src/hsl/garuda/garuda_qos.c deleted file mode 100755 index f1c367a14..000000000 --- a/feeds/ipq807x/qca-ssdk/src/src/hsl/garuda/garuda_qos.c +++ /dev/null @@ -1,1191 +0,0 @@ -/* - * Copyright (c) 2012, The Linux Foundation. All rights reserved. - * Permission to use, copy, modify, and/or distribute this software for - * any purpose with or without fee is hereby granted, provided that the - * above copyright notice and this permission notice appear in all copies. - * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES - * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR - * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES - * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN - * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT - * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. - */ - - -/** - * @defgroup garuda_qos GARUDA_QOS - * @{ - */ -#include "sw.h" -#include "hsl.h" -#include "hsl_dev.h" -#include "hsl_port_prop.h" -#include "garuda_qos.h" -#include "garuda_reg.h" - -#define GARUDA_QOS_QUEUE_TX_BUFFER_MAX 60 -#define GARUDA_QOS_PORT_TX_BUFFER_MAX 252 - -//#define GARUDA_MIN_QOS_MODE_PRI 0 -#define GARUDA_MAX_QOS_MODE_PRI 3 - -static sw_error_t -_garuda_qos_sch_mode_set(a_uint32_t dev_id, - fal_sch_mode_t mode, const a_uint32_t weight[]) -{ - sw_error_t rv; - a_uint32_t val, wrr, mix; - - HSL_DEV_ID_CHECK(dev_id); - - if (FAL_SCH_SP_MODE == mode) - { - wrr = 0; - mix = 0; - } - else if (FAL_SCH_WRR_MODE == mode) - { - wrr = 1; - mix = 0; - } - else if (FAL_SCH_MIX_MODE == mode) - { - wrr = 1; - mix = 1; - } - else - { - return SW_NOT_SUPPORTED; - } - - HSL_REG_ENTRY_GET(rv, dev_id, GLOBAL_CTL, 0, (a_uint32_t *) (&val), - sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - - SW_SET_REG_BY_FIELD(GLOBAL_CTL, WEIGHT_PRIORITY, wrr, val); - SW_SET_REG_BY_FIELD(GLOBAL_CTL, MIX_PRIORITY, mix, val); - - HSL_REG_ENTRY_SET(rv, dev_id, GLOBAL_CTL, 0, - (a_uint8_t *) (&val), sizeof (a_uint32_t)); - return rv; -} - -static sw_error_t -_garuda_qos_sch_mode_get(a_uint32_t dev_id, - fal_sch_mode_t * mode, a_uint32_t weight[]) -{ - sw_error_t rv; - a_uint32_t idx, val, wrr, mix; - - HSL_DEV_ID_CHECK(dev_id); - - HSL_REG_ENTRY_GET(rv, dev_id, GLOBAL_CTL, 0, (a_uint32_t *) (&val), - sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - - SW_GET_FIELD_BY_REG(GLOBAL_CTL, WEIGHT_PRIORITY, wrr, val); - SW_GET_FIELD_BY_REG(GLOBAL_CTL, MIX_PRIORITY, mix, val); - - if (0 == wrr) - { - *mode = FAL_SCH_SP_MODE; - for (idx = 0; idx < 4; idx++) - { - weight[idx] = 0; - } - } - else - { - if (0 == mix) - { - *mode = FAL_SCH_WRR_MODE; - weight[0] = 1; - for (idx = 1; idx < 4; idx++) - { - weight[idx] = weight[idx - 1] << 1; - } - } - else - { - *mode = FAL_SCH_MIX_MODE; - weight[3] = 0; - weight[2] = 4; - weight[1] = 2; - weight[0] = 1; - } - } - - return SW_OK; -} - -static sw_error_t -_garuda_qos_queue_tx_buf_status_set(a_uint32_t dev_id, fal_port_t port_id, - a_bool_t enable) -{ - a_uint32_t val = 0; - sw_error_t rv; - - if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU)) - { - return SW_BAD_PARAM; - } - - if (A_TRUE == enable) - { - val = 1; - } - else if (A_FALSE == enable) - { - val = 0; - } - else - { - return SW_BAD_PARAM; - } - - HSL_REG_FIELD_SET(rv, dev_id, QUEUE_CTL, port_id, QUEUE_DESC_EN, - (a_uint8_t *) (&val), sizeof (a_uint32_t)); - return rv; -} - - -static sw_error_t -_garuda_qos_queue_tx_buf_status_get(a_uint32_t dev_id, fal_port_t port_id, - a_bool_t * enable) -{ - a_uint32_t val = 0; - sw_error_t rv; - - if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU)) - { - return SW_BAD_PARAM; - } - - HSL_REG_FIELD_GET(rv, dev_id, QUEUE_CTL, port_id, QUEUE_DESC_EN, - (a_uint8_t *) (&val), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - - if (1 == val) - { - *enable = A_TRUE; - } - else - { - *enable = A_FALSE; - } - - return SW_OK; -} - - -static sw_error_t -_garuda_qos_port_tx_buf_status_set(a_uint32_t dev_id, fal_port_t port_id, - a_bool_t enable) -{ - a_uint32_t val = 0; - sw_error_t rv; - - if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU)) - { - return SW_BAD_PARAM; - } - - if (A_TRUE == enable) - { - val = 1; - } - else if (A_FALSE == enable) - { - val = 0; - } - else - { - return SW_BAD_PARAM; - } - - HSL_REG_FIELD_SET(rv, dev_id, QUEUE_CTL, port_id, PORT_DESC_EN, - (a_uint8_t *) (&val), sizeof (a_uint32_t)); - return rv; -} - - -static sw_error_t -_garuda_qos_port_tx_buf_status_get(a_uint32_t dev_id, fal_port_t port_id, - a_bool_t * enable) -{ - a_uint32_t val = 0; - sw_error_t rv; - - if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU)) - { - return SW_BAD_PARAM; - } - - HSL_REG_FIELD_GET(rv, dev_id, QUEUE_CTL, port_id, PORT_DESC_EN, - (a_uint8_t *) (&val), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - - if (1 == val) - { - *enable = A_TRUE; - } - else - { - *enable = A_FALSE; - } - - return SW_OK; -} - - -static sw_error_t -_garuda_qos_queue_tx_buf_nr_set(a_uint32_t dev_id, fal_port_t port_id, - fal_queue_t queue_id, a_uint32_t * number) -{ - a_uint32_t val = 0; - sw_error_t rv; - - if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU)) - { - return SW_BAD_PARAM; - } - - if (GARUDA_QOS_QUEUE_TX_BUFFER_MAX < *number) - { - return SW_BAD_PARAM; - } - - val = *number / 4; - *number = val << 2; - - if (0 == queue_id) - { - HSL_REG_FIELD_SET(rv, dev_id, QUEUE_CTL, port_id, QUEUE0_DESC_NR, - (a_uint8_t *) (&val), sizeof (a_uint32_t)); - } - else if (1 == queue_id) - { - HSL_REG_FIELD_SET(rv, dev_id, QUEUE_CTL, port_id, QUEUE1_DESC_NR, - (a_uint8_t *) (&val), sizeof (a_uint32_t)); - } - else if (2 == queue_id) - { - HSL_REG_FIELD_SET(rv, dev_id, QUEUE_CTL, port_id, QUEUE2_DESC_NR, - (a_uint8_t *) (&val), sizeof (a_uint32_t)); - } - else if (3 == queue_id) - { - HSL_REG_FIELD_SET(rv, dev_id, QUEUE_CTL, port_id, QUEUE3_DESC_NR, - (a_uint8_t *) (&val), sizeof (a_uint32_t)); - } - else - { - return SW_BAD_PARAM; - } - - return rv; -} - - -static sw_error_t -_garuda_qos_queue_tx_buf_nr_get(a_uint32_t dev_id, fal_port_t port_id, - fal_queue_t queue_id, a_uint32_t * number) -{ - a_uint32_t val = 0; - sw_error_t rv; - - if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU)) - { - return SW_BAD_PARAM; - } - - if (0 == queue_id) - { - HSL_REG_FIELD_GET(rv, dev_id, QUEUE_CTL, port_id, QUEUE0_DESC_NR, - (a_uint8_t *) (&val), sizeof (a_uint32_t)); - } - else if (1 == queue_id) - { - HSL_REG_FIELD_GET(rv, dev_id, QUEUE_CTL, port_id, QUEUE1_DESC_NR, - (a_uint8_t *) (&val), sizeof (a_uint32_t)); - } - else if (2 == queue_id) - { - HSL_REG_FIELD_GET(rv, dev_id, QUEUE_CTL, port_id, QUEUE2_DESC_NR, - (a_uint8_t *) (&val), sizeof (a_uint32_t)); - } - else if (3 == queue_id) - { - HSL_REG_FIELD_GET(rv, dev_id, QUEUE_CTL, port_id, QUEUE3_DESC_NR, - (a_uint8_t *) (&val), sizeof (a_uint32_t)); - } - else - { - return SW_BAD_PARAM; - } - SW_RTN_ON_ERROR(rv); - - *number = val << 2; - return SW_OK; -} - - -static sw_error_t -_garuda_qos_port_tx_buf_nr_set(a_uint32_t dev_id, fal_port_t port_id, - a_uint32_t * number) -{ - a_uint32_t val = 0; - sw_error_t rv; - - if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU)) - { - return SW_BAD_PARAM; - } - - if (GARUDA_QOS_PORT_TX_BUFFER_MAX < *number) - { - return SW_BAD_PARAM; - } - - val = *number / 4; - *number = val << 2; - HSL_REG_FIELD_SET(rv, dev_id, QUEUE_CTL, port_id, PORT_DESC_NR, - (a_uint8_t *) (&val), sizeof (a_uint32_t)); - return rv; -} - -static sw_error_t -_garuda_qos_port_tx_buf_nr_get(a_uint32_t dev_id, fal_port_t port_id, - a_uint32_t * number) -{ - a_uint32_t val = 0; - sw_error_t rv; - - if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU)) - { - return SW_BAD_PARAM; - } - - HSL_REG_FIELD_GET(rv, dev_id, QUEUE_CTL, port_id, PORT_DESC_NR, - (a_uint8_t *) (&val), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - - *number = val << 2; - return SW_OK; -} - -static sw_error_t -_garuda_cosmap_up_queue_set(a_uint32_t dev_id, a_uint32_t up, - fal_queue_t queue) -{ - sw_error_t rv; - a_uint32_t val; - hsl_dev_t *p_dev = NULL; - - HSL_DEV_ID_CHECK(dev_id); - - if (FAL_DOT1P_MAX < up) - { - return SW_BAD_PARAM; - } - - SW_RTN_ON_NULL(p_dev = hsl_dev_ptr_get(dev_id)); - if (p_dev->nr_queue <= queue) - { - return SW_BAD_PARAM; - } - - val = queue; - HSL_REG_FIELD_GEN_SET(rv, dev_id, TAG_PRI_MAPPING_OFFSET, 2, - (a_uint16_t) (up << 1), (a_uint8_t *) (&val), - sizeof (a_uint32_t)); - return rv; -} - - -static sw_error_t -_garuda_cosmap_up_queue_get(a_uint32_t dev_id, a_uint32_t up, - fal_queue_t * queue) -{ - sw_error_t rv; - a_uint32_t val; - - HSL_DEV_ID_CHECK(dev_id); - - if (FAL_DOT1P_MAX < up) - { - return SW_BAD_PARAM; - } - - HSL_REG_FIELD_GEN_GET(rv, dev_id, TAG_PRI_MAPPING_OFFSET, 2, - (a_uint16_t) (up << 1), (a_uint8_t *) (&val), - sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - - *queue = val; - return SW_OK; -} - -static sw_error_t -_garuda_cosmap_dscp_queue_set(a_uint32_t dev_id, a_uint32_t dscp, - fal_queue_t queue) -{ - sw_error_t rv; - a_uint32_t val; - a_uint32_t offsetaddr; - a_uint16_t fieldoffset; - hsl_dev_t *p_dev = NULL; - - HSL_DEV_ID_CHECK(dev_id); - - if (FAL_DSCP_MAX < dscp) - { - return SW_BAD_PARAM; - } - - SW_RTN_ON_NULL(p_dev = hsl_dev_ptr_get(dev_id)); - if (p_dev->nr_queue <= queue) - { - return SW_BAD_PARAM; - } - - offsetaddr = (dscp >> 4) << 2; - fieldoffset = (dscp & 0xf) << 1; - - val = queue; - HSL_REG_FIELD_GEN_SET(rv, dev_id, (IP_PRI_MAPPING_OFFSET + offsetaddr), - 2, fieldoffset, (a_uint8_t *) (&val), sizeof (a_uint32_t)); - return rv; -} - -static sw_error_t -_garuda_cosmap_dscp_queue_get(a_uint32_t dev_id, a_uint32_t dscp, - fal_queue_t * queue) -{ - sw_error_t rv; - a_uint32_t val; - a_uint32_t offsetaddr; - a_uint16_t fieldoffset; - - HSL_DEV_ID_CHECK(dev_id); - - if (FAL_DSCP_MAX < dscp) - { - return SW_BAD_PARAM; - } - - offsetaddr = (dscp / 16) << 2; - fieldoffset = (dscp & 0xf) << 1; - - HSL_REG_FIELD_GEN_GET(rv, dev_id, (IP_PRI_MAPPING_OFFSET + offsetaddr), - 2, fieldoffset, (a_uint8_t *) (&val), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - - *queue = val; - return SW_OK; -} - - -static sw_error_t -_garuda_qos_port_mode_set(a_uint32_t dev_id, fal_port_t port_id, - fal_qos_mode_t mode, a_bool_t enable) -{ - sw_error_t rv; - a_uint32_t val; - - HSL_DEV_ID_CHECK(dev_id); - - if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU)) - { - return SW_BAD_PARAM; - } - - if (A_TRUE == enable) - { - val = 1; - } - else if (A_FALSE == enable) - { - val = 0; - } - else - { - return SW_BAD_PARAM; - } - - if (FAL_QOS_DA_MODE == mode) - { - HSL_REG_FIELD_SET(rv, dev_id, PRI_CTL, port_id, DA_PRI_EN, - (a_uint8_t *) (&val), sizeof (a_uint32_t)); - } - else if (FAL_QOS_UP_MODE == mode) - { - HSL_REG_FIELD_SET(rv, dev_id, PRI_CTL, port_id, VLAN_PRI_EN, - (a_uint8_t *) (&val), sizeof (a_uint32_t)); - } - else if (FAL_QOS_DSCP_MODE == mode) - { - HSL_REG_FIELD_SET(rv, dev_id, PRI_CTL, port_id, IP_PRI_EN, - (a_uint8_t *) (&val), sizeof (a_uint32_t)); - } - else if (FAL_QOS_PORT_MODE == mode) - { - HSL_REG_FIELD_SET(rv, dev_id, PRI_CTL, port_id, PORT_PRI_EN, - (a_uint8_t *) (&val), sizeof (a_uint32_t)); - } - else - { - return SW_BAD_PARAM; - } - - return rv; -} - - -static sw_error_t -_garuda_qos_port_mode_get(a_uint32_t dev_id, fal_port_t port_id, - fal_qos_mode_t mode, a_bool_t * enable) -{ - sw_error_t rv; - a_uint32_t val; - - HSL_DEV_ID_CHECK(dev_id); - - if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU)) - { - return SW_BAD_PARAM; - } - - if (FAL_QOS_DA_MODE == mode) - { - HSL_REG_FIELD_GET(rv, dev_id, PRI_CTL, port_id, DA_PRI_EN, - (a_uint8_t *) (&val), sizeof (a_uint32_t)); - } - else if (FAL_QOS_UP_MODE == mode) - { - HSL_REG_FIELD_GET(rv, dev_id, PRI_CTL, port_id, VLAN_PRI_EN, - (a_uint8_t *) (&val), sizeof (a_uint32_t)); - } - else if (FAL_QOS_DSCP_MODE == mode) - { - HSL_REG_FIELD_GET(rv, dev_id, PRI_CTL, port_id, IP_PRI_EN, - (a_uint8_t *) (&val), sizeof (a_uint32_t)); - } - else if (FAL_QOS_PORT_MODE == mode) - { - HSL_REG_FIELD_GET(rv, dev_id, PRI_CTL, port_id, PORT_PRI_EN, - (a_uint8_t *) (&val), sizeof (a_uint32_t)); - } - else - { - return SW_BAD_PARAM; - } - SW_RTN_ON_ERROR(rv); - - if (1 == val) - { - *enable = A_TRUE; - } - else - { - *enable = A_FALSE; - } - - return SW_OK; -} - -static sw_error_t -_garuda_qos_port_mode_pri_set(a_uint32_t dev_id, fal_port_t port_id, - fal_qos_mode_t mode, a_uint32_t pri) -{ - sw_error_t rv; - a_uint32_t val; - - HSL_DEV_ID_CHECK(dev_id); - - if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU)) - { - return SW_BAD_PARAM; - } - - if (GARUDA_MAX_QOS_MODE_PRI < pri) - { - return SW_BAD_PARAM; - } - - HSL_REG_ENTRY_GET(rv, dev_id, PRI_CTL, port_id, (a_uint8_t *) (&val), - sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - - if (FAL_QOS_DA_MODE == mode) - { - SW_SET_REG_BY_FIELD(PRI_CTL, DA_PRI_SEL, pri, val); - } - else if (FAL_QOS_UP_MODE == mode) - { - SW_SET_REG_BY_FIELD(PRI_CTL, VLAN_PRI_SEL, pri, val); - } - else if (FAL_QOS_DSCP_MODE == mode) - { - SW_SET_REG_BY_FIELD(PRI_CTL, IP_PRI_SEL, pri, val); - } - else if (FAL_QOS_PORT_MODE == mode) - { - SW_SET_REG_BY_FIELD(PRI_CTL, PORT_PRI_SEL, pri, val); - } - else - { - return SW_NOT_SUPPORTED; - } - - HSL_REG_ENTRY_SET(rv, dev_id, PRI_CTL, port_id, (a_uint8_t *) (&val), - sizeof (a_uint32_t)); - return rv; -} - - -static sw_error_t -_garuda_qos_port_mode_pri_get(a_uint32_t dev_id, fal_port_t port_id, - fal_qos_mode_t mode, a_uint32_t * pri) -{ - sw_error_t rv; - a_uint32_t entry, f_val; - - HSL_DEV_ID_CHECK(dev_id); - - if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU)) - { - return SW_BAD_PARAM; - } - - HSL_REG_ENTRY_GET(rv, dev_id, PRI_CTL, port_id, (a_uint8_t *) (&entry), - sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - - if (FAL_QOS_DA_MODE == mode) - { - SW_GET_FIELD_BY_REG(PRI_CTL, DA_PRI_SEL, f_val, entry); - } - else if (FAL_QOS_UP_MODE == mode) - { - SW_GET_FIELD_BY_REG(PRI_CTL, VLAN_PRI_SEL, f_val, entry); - } - else if (FAL_QOS_DSCP_MODE == mode) - { - SW_GET_FIELD_BY_REG(PRI_CTL, IP_PRI_SEL, f_val, entry); - } - else if (FAL_QOS_PORT_MODE == mode) - { - SW_GET_FIELD_BY_REG(PRI_CTL, PORT_PRI_SEL, f_val, entry); - } - else - { - return SW_NOT_SUPPORTED; - } - - *pri = f_val; - return SW_OK; -} - - -static sw_error_t -_garuda_qos_port_default_up_set(a_uint32_t dev_id, fal_port_t port_id, - a_uint32_t up) -{ - sw_error_t rv; - a_uint32_t val; - - HSL_DEV_ID_CHECK(dev_id); - - if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU)) - { - return SW_BAD_PARAM; - } - - if (FAL_DOT1P_MAX < up) - { - return SW_BAD_PARAM; - } - - val = up; - HSL_REG_FIELD_SET(rv, dev_id, PORT_BASE_VLAN, port_id, ING_PRI, - (a_uint8_t *) (&val), sizeof (a_uint32_t)); - return rv; -} - -static sw_error_t -_garuda_qos_port_default_up_get(a_uint32_t dev_id, fal_port_t port_id, - a_uint32_t * up) -{ - sw_error_t rv; - a_uint32_t val; - - HSL_DEV_ID_CHECK(dev_id); - - if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU)) - { - return SW_BAD_PARAM; - } - - HSL_REG_FIELD_GET(rv, dev_id, PORT_BASE_VLAN, port_id, ING_PRI, - (a_uint8_t *) (&val), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - - *up = val; - return SW_OK; -} - -/** - * @brief Set traffic scheduling mode on particular one device. - * @details Comments: - * GARUDA doesn't support variable weight in wrr mode, the weight for four queues - * are 8:4:2:1. - * When scheduling mode is sp the weight is meaningless usually it's zero - * When scheduling mode is sp the weight for four queues are 0:4:2:1 - * @param[in] dev_id device id - * @param[in] fal_sch_mode_t traffic scheduling mode - * @param[in] weight[] weight value for each queue when in wrr mode - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -garuda_qos_sch_mode_set(a_uint32_t dev_id, - fal_sch_mode_t mode, const a_uint32_t weight[]) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _garuda_qos_sch_mode_set(dev_id, mode, weight); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Get traffic scheduling mode on particular device. - * @param[in] dev_id device id - * @param[in] fal_sch_mode_t traffic scheduling mode - * @param[out] weight weight value for wrr mode - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -garuda_qos_sch_mode_get(a_uint32_t dev_id, - fal_sch_mode_t * mode, a_uint32_t weight[]) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _garuda_qos_sch_mode_get(dev_id, mode, weight); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Set buffer aggsinment status of transmitting queue on one particular port. - * @details Comments: - * If enable queue tx buffer on one port that means each queue of this port - * will have fixed number buffers when transmitting packets. Otherwise they - * share the whole buffers with other queues in device. - * @param[in] dev_id device id - * @param[in] port_id port id - * @param[in] enable A_TRUE or A_FALSE - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -garuda_qos_queue_tx_buf_status_set(a_uint32_t dev_id, fal_port_t port_id, - a_bool_t enable) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _garuda_qos_queue_tx_buf_status_set(dev_id, port_id, enable); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Get buffer aggsinment status of transmitting queue on particular port. - * @param[in] dev_id device id - * @param[in] port_id port id - * @param[in] enable A_TRUE or A_FALSE - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -garuda_qos_queue_tx_buf_status_get(a_uint32_t dev_id, fal_port_t port_id, - a_bool_t * enable) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _garuda_qos_queue_tx_buf_status_get(dev_id, port_id, enable); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Set buffer aggsinment status of transmitting port on one particular port. - * @details Comments: - If enable tx buffer on one port that means this port will have fixed - number buffers when transmitting packets. Otherwise they will - share the whole buffers with other ports in device. - * function will return actual buffer numbers in hardware. - * @param[in] dev_id device id - * @param[in] port_id port id - * @param[in] enable A_TRUE or A_FALSE - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -garuda_qos_port_tx_buf_status_set(a_uint32_t dev_id, fal_port_t port_id, - a_bool_t enable) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _garuda_qos_port_tx_buf_status_set(dev_id, port_id, enable); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Get buffer aggsinment status of transmitting port on one particular port. - * @param[in] dev_id device id - * @param[in] port_id port id - * @param[out] enable A_TRUE or A_FALSE - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -garuda_qos_port_tx_buf_status_get(a_uint32_t dev_id, fal_port_t port_id, - a_bool_t * enable) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _garuda_qos_port_tx_buf_status_get(dev_id, port_id, enable); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Set max occupied buffer number of transmitting queue on one particular port. - * @details Comments: - The step of buffer number in GARUDA is 4, function will return actual - buffer numbers in hardware. - The buffer number range for queue is 4 to 60. - * share the whole buffers with other ports in device. - * @param[in] dev_id device id - * @param[in] port_id port id - * @param[in] queue_id queue id - * @param number buffer number - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -garuda_qos_queue_tx_buf_nr_set(a_uint32_t dev_id, fal_port_t port_id, - fal_queue_t queue_id, a_uint32_t * number) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _garuda_qos_queue_tx_buf_nr_set(dev_id, port_id, queue_id, number); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Get max occupied buffer number of transmitting queue on one particular port. - * @param[in] dev_id device id - * @param[in] port_id port id - * @param[in] queue_id queue id - * @param[out] number buffer number - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -garuda_qos_queue_tx_buf_nr_get(a_uint32_t dev_id, fal_port_t port_id, - fal_queue_t queue_id, a_uint32_t * number) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _garuda_qos_queue_tx_buf_nr_get(dev_id, port_id, queue_id, number); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Set max occupied buffer number of transmitting port on one particular port. - * @details Comments: - The step of buffer number in GARUDA is four, function will return actual - buffer numbers in hardware. - The buffer number range for transmitting port is 4 to 124. - * @param[in] dev_id device id - * @param[in] port_id port id - * @param number buffer number - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -garuda_qos_port_tx_buf_nr_set(a_uint32_t dev_id, fal_port_t port_id, - a_uint32_t * number) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _garuda_qos_port_tx_buf_nr_set(dev_id, port_id, number); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Get max occupied buffer number of transmitting port on one particular port. - * @param[in] dev_id device id - * @param[in] port_id port id - * @param[out] number buffer number - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -garuda_qos_port_tx_buf_nr_get(a_uint32_t dev_id, fal_port_t port_id, - a_uint32_t * number) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _garuda_qos_port_tx_buf_nr_get(dev_id, port_id, number); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Set user priority to mapping on one particular device. - * @param[in] dev_id device id - * @param[in] dot1p 802.1p - * @param[in] queue queue id - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -garuda_cosmap_up_queue_set(a_uint32_t dev_id, a_uint32_t up, - fal_queue_t queue) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _garuda_cosmap_up_queue_set(dev_id, up, queue); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Get user priority to mapping on one particular device. - * @param[in] dev_id device id - * @param[in] dot1p 802.1p - * @param[out] queue queue id - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -garuda_cosmap_up_queue_get(a_uint32_t dev_id, a_uint32_t up, - fal_queue_t * queue) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _garuda_cosmap_up_queue_get(dev_id, up, queue); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Set cos map dscp_2_queue item on one particular device. - * @param[in] dev_id device id - * @param[in] dscp dscp - * @param[in] queue queue id - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -garuda_cosmap_dscp_queue_set(a_uint32_t dev_id, a_uint32_t dscp, - fal_queue_t queue) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _garuda_cosmap_dscp_queue_set(dev_id, dscp, queue); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Get cos map dscp_2_queue item on one particular device. - * @param[in] dev_id device id - * @param[in] dscp dscp - * @param[out] queue queue id - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -garuda_cosmap_dscp_queue_get(a_uint32_t dev_id, a_uint32_t dscp, - fal_queue_t * queue) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _garuda_cosmap_dscp_queue_get(dev_id, dscp, queue); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Set port qos mode on a particular port. - * @param[in] dev_id device id - * @param[in] port_id port id - * @param[in] mode qos mode - * @param[in] enable A_TRUE of A_FALSE - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -garuda_qos_port_mode_set(a_uint32_t dev_id, fal_port_t port_id, - fal_qos_mode_t mode, a_bool_t enable) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _garuda_qos_port_mode_set(dev_id, port_id, mode, enable); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Get port qos mode on a particular port. - * @param[in] dev_id device id - * @param[in] port_id port id - * @param[in] mode qos mode - * @param[out] enable A_TRUE of A_FALSE - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -garuda_qos_port_mode_get(a_uint32_t dev_id, fal_port_t port_id, - fal_qos_mode_t mode, a_bool_t * enable) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _garuda_qos_port_mode_get(dev_id, port_id, mode, enable); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Set priority of one particular qos mode on one particular port. - * @details Comments: - If the priority of a mode is more small then the priority is more high. - Differnet mode should have differnet priority. - * @param[in] dev_id device id - * @param[in] port_id port id - * @param[in] mode qos mode - * @param[in] pri priority of one particular qos mode - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -garuda_qos_port_mode_pri_set(a_uint32_t dev_id, fal_port_t port_id, - fal_qos_mode_t mode, a_uint32_t pri) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _garuda_qos_port_mode_pri_set(dev_id, port_id, mode, pri); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Get priority of one particular qos mode on one particular port. - * @param[in] dev_id device id - * @param[in] port_id port id - * @param[in] mode qos mode - * @param[out] pri priority of one particular qos mode - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -garuda_qos_port_mode_pri_get(a_uint32_t dev_id, fal_port_t port_id, - fal_qos_mode_t mode, a_uint32_t * pri) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _garuda_qos_port_mode_pri_get(dev_id, port_id, mode, pri); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Set default user priority on one particular port. - * @param[in] dev_id device id - * @param[in] port_id port id - * @param[in] up 802.1p - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -garuda_qos_port_default_up_set(a_uint32_t dev_id, fal_port_t port_id, - a_uint32_t up) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _garuda_qos_port_default_up_set(dev_id, port_id, up); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Get default user priority on one particular port. - * @param[in] dev_id device id - * @param[in] port_id port id - * @param[out] up 802.1p - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -garuda_qos_port_default_up_get(a_uint32_t dev_id, fal_port_t port_id, - a_uint32_t * up) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _garuda_qos_port_default_up_get(dev_id, port_id, up); - HSL_API_UNLOCK; - return rv; -} - -sw_error_t -garuda_qos_init(a_uint32_t dev_id) -{ - HSL_DEV_ID_CHECK(dev_id); - -#ifndef HSL_STANDALONG - { - hsl_api_t *p_api; - - SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id)); - - p_api->qos_sch_mode_set = garuda_qos_sch_mode_set; - p_api->qos_sch_mode_get = garuda_qos_sch_mode_get; - p_api->qos_queue_tx_buf_status_set = garuda_qos_queue_tx_buf_status_set; - p_api->qos_queue_tx_buf_status_get = garuda_qos_queue_tx_buf_status_get; - p_api->qos_port_tx_buf_status_set = garuda_qos_port_tx_buf_status_set; - p_api->qos_port_tx_buf_status_get = garuda_qos_port_tx_buf_status_get; - p_api->qos_queue_tx_buf_nr_set = garuda_qos_queue_tx_buf_nr_set; - p_api->qos_queue_tx_buf_nr_get = garuda_qos_queue_tx_buf_nr_get; - p_api->qos_port_tx_buf_nr_set = garuda_qos_port_tx_buf_nr_set; - p_api->qos_port_tx_buf_nr_get = garuda_qos_port_tx_buf_nr_get; - p_api->cosmap_up_queue_set = garuda_cosmap_up_queue_set; - p_api->cosmap_up_queue_get = garuda_cosmap_up_queue_get; - p_api->cosmap_dscp_queue_set = garuda_cosmap_dscp_queue_set; - p_api->cosmap_dscp_queue_get = garuda_cosmap_dscp_queue_get; - p_api->qos_port_mode_set = garuda_qos_port_mode_set; - p_api->qos_port_mode_get = garuda_qos_port_mode_get; - p_api->qos_port_mode_pri_set = garuda_qos_port_mode_pri_set; - p_api->qos_port_mode_pri_get = garuda_qos_port_mode_pri_get; - p_api->qos_port_default_up_set = garuda_qos_port_default_up_set; - p_api->qos_port_default_up_get = garuda_qos_port_default_up_get; - } -#endif - - return SW_OK; -} - -/** - * @} - */ - diff --git a/feeds/ipq807x/qca-ssdk/src/src/hsl/garuda/garuda_rate.c b/feeds/ipq807x/qca-ssdk/src/src/hsl/garuda/garuda_rate.c deleted file mode 100755 index 8bd9cac65..000000000 --- a/feeds/ipq807x/qca-ssdk/src/src/hsl/garuda/garuda_rate.c +++ /dev/null @@ -1,851 +0,0 @@ -/* - * Copyright (c) 2012, The Linux Foundation. All rights reserved. - * Permission to use, copy, modify, and/or distribute this software for - * any purpose with or without fee is hereby granted, provided that the - * above copyright notice and this permission notice appear in all copies. - * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES - * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR - * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES - * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN - * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT - * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. - */ - - - -/** - * @defgroup garuda_rate GARUDA_RATE - * @{ - */ - -#include "sw.h" -#include "hsl.h" -#include "hsl_dev.h" -#include "hsl_port_prop.h" -#include "garuda_rate.h" -#include "garuda_reg.h" - -#define GARUDA_STORM_MIN_RATE_PPS 1000 -#define GARUDA_STORM_MAX_RATE_PPS (1024 * 1000) - -static sw_error_t -garuda_stormrate_sw_to_hw(a_uint32_t swrate, a_uint32_t * hwrate) -{ - a_uint32_t shrnr = 0; - a_uint32_t tmp = swrate / 1000; - - if ((GARUDA_STORM_MIN_RATE_PPS > swrate) - || (GARUDA_STORM_MAX_RATE_PPS < swrate)) - { - return SW_BAD_PARAM; - } - - while ((tmp != 0) && (shrnr < 12)) - { - tmp = tmp >> 1; - shrnr++; - } - - if (12 == shrnr) - { - return SW_BAD_PARAM; - } - - *hwrate = shrnr; - return SW_OK; -} - -static sw_error_t -garuda_stormrate_hw_to_sw(a_uint32_t hwrate, a_uint32_t * swrate) -{ - if (0 == hwrate) - { - hwrate = 1; - } - - if ((1 > hwrate) || (11 < hwrate)) - { - return SW_BAD_PARAM; - } - - *swrate = (1 << (hwrate - 1)) * 1000; - return SW_OK; -} - - -static sw_error_t -_garuda_rate_queue_egrl_set(a_uint32_t dev_id, fal_port_t port_id, - fal_queue_t queue_id, a_uint32_t * speed, - a_bool_t enable) -{ - sw_error_t rv; - a_uint32_t val; - a_uint32_t portrl; - - if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU)) - { - return SW_BAD_PARAM; - } - - HSL_REG_FIELD_GET(rv, dev_id, RATE_LIMIT0, port_id, EG_RATE_EN, - (a_uint8_t *) (&portrl), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - - if (A_TRUE == enable) - { - if (1 == portrl) - { - /* already enable port egress rate limit, queue and port - egress rate limit can't coexist */ - return SW_NOT_SUPPORTED; - } - - if ((0x7ffe << 5) < *speed) - { - return SW_BAD_PARAM; - } - val = *speed >> 5; - *speed = val << 5; - } - else if (A_FALSE == enable) - { - val = 0x7fff; - *speed = 0; - if (1 == portrl) - { - /* already enable port egress rate limit */ - return SW_OK; - } - } - else - { - return SW_BAD_PARAM; - } - - if (0 == queue_id) - { - HSL_REG_FIELD_SET(rv, dev_id, RATE_LIMIT1, port_id, EG_Q0_RATE, - (a_uint8_t *) (&val), sizeof (a_uint32_t)); - } - else if (1 == queue_id) - { - HSL_REG_FIELD_SET(rv, dev_id, RATE_LIMIT1, port_id, EG_Q1_RATE, - (a_uint8_t *) (&val), sizeof (a_uint32_t)); - } - else if (2 == queue_id) - { - HSL_REG_FIELD_SET(rv, dev_id, RATE_LIMIT2, port_id, EG_Q2_RATE, - (a_uint8_t *) (&val), sizeof (a_uint32_t)); - } - else if (3 == queue_id) - { - HSL_REG_FIELD_SET(rv, dev_id, RATE_LIMIT2, port_id, EG_Q3_RATE, - (a_uint8_t *) (&val), sizeof (a_uint32_t)); - } - else - { - return SW_BAD_PARAM; - } - - return rv; -} - -static sw_error_t -_garuda_rate_queue_egrl_get(a_uint32_t dev_id, fal_port_t port_id, - fal_queue_t queue_id, a_uint32_t * speed, - a_bool_t * enable) -{ - sw_error_t rv; - a_uint32_t val; - - if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU)) - { - return SW_BAD_PARAM; - } - - HSL_REG_FIELD_GET(rv, dev_id, RATE_LIMIT0, port_id, EG_RATE_EN, - (a_uint8_t *) (&val), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - - if (1 == val) - { - /* already enable port egress rate limit */ - *speed = 0; - *enable = A_FALSE; - - return SW_OK; - } - - if (0 == queue_id) - { - HSL_REG_FIELD_GET(rv, dev_id, RATE_LIMIT1, port_id, EG_Q0_RATE, - (a_uint8_t *) (&val), sizeof (a_uint32_t)); - } - else if (1 == queue_id) - { - HSL_REG_FIELD_GET(rv, dev_id, RATE_LIMIT1, port_id, EG_Q1_RATE, - (a_uint8_t *) (&val), sizeof (a_uint32_t)); - } - else if (2 == queue_id) - { - HSL_REG_FIELD_GET(rv, dev_id, RATE_LIMIT2, port_id, EG_Q2_RATE, - (a_uint8_t *) (&val), sizeof (a_uint32_t)); - } - else if (3 == queue_id) - { - HSL_REG_FIELD_GET(rv, dev_id, RATE_LIMIT2, port_id, EG_Q3_RATE, - (a_uint8_t *) (&val), sizeof (a_uint32_t)); - } - else - { - return SW_BAD_PARAM; - } - - SW_RTN_ON_ERROR(rv); - - if (0x7fff == val) - { - *enable = A_FALSE; - } - else - { - *enable = A_TRUE; - *speed = val << 5; - } - - return SW_OK; -} - - -static sw_error_t -_garuda_rate_port_egrl_set(a_uint32_t dev_id, fal_port_t port_id, - a_uint32_t * speed, a_bool_t enable) -{ - sw_error_t rv; - a_uint32_t val; - a_uint32_t portrl; - - HSL_DEV_ID_CHECK(dev_id); - - if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU)) - { - return SW_BAD_PARAM; - } - - HSL_REG_FIELD_GET(rv, dev_id, RATE_LIMIT0, port_id, EG_RATE_EN, - (a_uint8_t *) (&portrl), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - - if (A_FALSE == enable) - { - *speed = 0; - - /* if port egress rate limit current enable then disable */ - if (1 == portrl) - { - val = 0; - HSL_REG_FIELD_SET(rv, dev_id, RATE_LIMIT0, port_id, EG_RATE_EN, - (a_uint8_t *) (&val), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - - val = 0x7fff; - HSL_REG_FIELD_SET(rv, dev_id, RATE_LIMIT2, port_id, EG_Q3_RATE, - (a_uint8_t *) (&val), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - } - - rv = SW_OK; - } - else - { - if ((0x7ffe << 5) < *speed) - { - return SW_BAD_PARAM; - } - - /* not enable egress port rate limit */ - if (0 == portrl) - { - HSL_REG_FIELD_GET(rv, dev_id, RATE_LIMIT1, port_id, EG_Q0_RATE, - (a_uint8_t *) (&val), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - - if (0x7fff != val) - { - /* already enable egress queue0 rate limit, queue and port - egress rate limit can't coexist */ - return SW_NOT_SUPPORTED; - } - - HSL_REG_FIELD_GET(rv, dev_id, RATE_LIMIT1, port_id, EG_Q1_RATE, - (a_uint8_t *) (&val), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - - if (0x7fff != val) - { - /* already enable egress queue1 rate limit, queue and port - egress rate limit can't coexist */ - return SW_NOT_SUPPORTED; - } - - HSL_REG_FIELD_GET(rv, dev_id, RATE_LIMIT2, port_id, EG_Q2_RATE, - (a_uint8_t *) (&val), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - - if (0x7fff != val) - { - /* already enable egress queue2 rate limit, queue and port - egress rate limit can't coexist */ - return SW_NOT_SUPPORTED; - } - - HSL_REG_FIELD_GET(rv, dev_id, RATE_LIMIT2, port_id, EG_Q3_RATE, - (a_uint8_t *) (&val), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - - if (0x7fff != val) - { - /* already enable egress queue3 rate limit, queue and port - egress rate limit can't coexist */ - return SW_NOT_SUPPORTED; - } - - val = 1; - HSL_REG_FIELD_SET(rv, dev_id, RATE_LIMIT0, port_id, EG_RATE_EN, - (a_uint8_t *) (&val), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - } - - val = *speed >> 5; - *speed = val << 5; - HSL_REG_FIELD_SET(rv, dev_id, RATE_LIMIT2, port_id, EG_Q3_RATE, - (a_uint8_t *) (&val), sizeof (a_uint32_t)); - } - - return rv; -} - -static sw_error_t -_garuda_rate_port_egrl_get(a_uint32_t dev_id, fal_port_t port_id, - a_uint32_t * speed, a_bool_t * enable) -{ - sw_error_t rv; - a_uint32_t val; - - HSL_DEV_ID_CHECK(dev_id); - - if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU)) - { - return SW_BAD_PARAM; - } - - HSL_REG_FIELD_GET(rv, dev_id, RATE_LIMIT0, port_id, EG_RATE_EN, - (a_uint8_t *) (&val), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - - if (0 == val) - { - *speed = 0; - *enable = A_FALSE; - return SW_OK; - } - - HSL_REG_FIELD_GET(rv, dev_id, RATE_LIMIT2, port_id, EG_Q3_RATE, - (a_uint8_t *) (&val), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - *enable = A_TRUE; - *speed = val << 5; - - return SW_OK; -} - -static sw_error_t -_garuda_rate_port_inrl_set(a_uint32_t dev_id, fal_port_t port_id, - a_uint32_t * speed, a_bool_t enable) -{ - sw_error_t rv; - a_uint32_t val; - - HSL_DEV_ID_CHECK(dev_id); - - if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU)) - { - return SW_BAD_PARAM; - } - - if (A_TRUE == enable) - { - if ((0x7ffe << 5) < *speed) - { - return SW_BAD_PARAM; - } - val = *speed >> 5; - *speed = val << 5; - } - else if (A_FALSE == enable) - { - val = 0x7fff; - *speed = 0; - } - else - { - return SW_BAD_PARAM; - } - - HSL_REG_FIELD_SET(rv, dev_id, RATE_LIMIT0, port_id, ING_RATE, - (a_uint8_t *) (&val), sizeof (a_uint32_t)); - return rv; -} - -static sw_error_t -_garuda_rate_port_inrl_get(a_uint32_t dev_id, fal_port_t port_id, - a_uint32_t * speed, a_bool_t * enable) -{ - sw_error_t rv; - a_uint32_t val; - - HSL_DEV_ID_CHECK(dev_id); - - if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU)) - { - return SW_BAD_PARAM; - } - - HSL_REG_FIELD_GET(rv, dev_id, RATE_LIMIT0, port_id, ING_RATE, - (a_uint8_t *) (&val), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - - if (0x7fff == val) - { - *enable = A_FALSE; - *speed = 0; - } - else - { - *enable = A_TRUE; - *speed = val << 5; - } - - return SW_OK; -} - -static sw_error_t -_garuda_storm_ctrl_frame_set(a_uint32_t dev_id, fal_port_t port_id, - fal_storm_type_t storm_type, a_bool_t enable) -{ - a_uint32_t data; - sw_error_t rv; - - HSL_DEV_ID_CHECK(dev_id); - - if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU)) - { - return SW_BAD_PARAM; - } - - if (A_TRUE == enable) - { - data = 1; - } - else if (A_FALSE == enable) - { - data = 0; - } - else - { - return SW_BAD_PARAM; - } - - if (FAL_UNICAST_STORM == storm_type) - { - HSL_REG_FIELD_SET(rv, dev_id, STORM_CTL, port_id, UNI_EN, - (a_uint8_t *) (&data), sizeof (a_uint32_t)); - } - else if (FAL_MULTICAST_STORM == storm_type) - { - HSL_REG_FIELD_SET(rv, dev_id, STORM_CTL, port_id, MUL_EN, - (a_uint8_t *) (&data), sizeof (a_uint32_t)); - } - else if (FAL_BROADCAST_STORM == storm_type) - { - HSL_REG_FIELD_SET(rv, dev_id, STORM_CTL, port_id, BRO_EN, - (a_uint8_t *) (&data), sizeof (a_uint32_t)); - } - else - { - return SW_BAD_PARAM; - } - SW_RTN_ON_ERROR(rv); - - HSL_REG_FIELD_GET(rv, dev_id, STORM_CTL, port_id, RATE, - (a_uint8_t *) (&data), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - - if (0 == data) - { - data = 1; - HSL_REG_FIELD_SET(rv, dev_id, STORM_CTL, port_id, RATE, - (a_uint8_t *) (&data), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - } - - return SW_OK; -} - -static sw_error_t -_garuda_storm_ctrl_frame_get(a_uint32_t dev_id, fal_port_t port_id, - fal_storm_type_t storm_type, a_bool_t * enable) -{ - a_uint32_t data; - sw_error_t rv; - - HSL_DEV_ID_CHECK(dev_id); - - if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU)) - { - return SW_BAD_PARAM; - } - - if (FAL_UNICAST_STORM == storm_type) - { - HSL_REG_FIELD_GET(rv, dev_id, STORM_CTL, port_id, UNI_EN, - (a_uint8_t *) (&data), sizeof (a_uint32_t)); - } - else if (FAL_MULTICAST_STORM == storm_type) - { - HSL_REG_FIELD_GET(rv, dev_id, STORM_CTL, port_id, MUL_EN, - (a_uint8_t *) (&data), sizeof (a_uint32_t)); - } - else if (FAL_BROADCAST_STORM == storm_type) - { - HSL_REG_FIELD_GET(rv, dev_id, STORM_CTL, port_id, BRO_EN, - (a_uint8_t *) (&data), sizeof (a_uint32_t)); - } - else - { - return SW_BAD_PARAM; - } - - SW_RTN_ON_ERROR(rv); - - if (1 == data) - { - data = 1; - *enable = A_TRUE; - } - else - { - *enable = A_FALSE; - } - - return SW_OK; -} - -static sw_error_t -_garuda_storm_ctrl_rate_set(a_uint32_t dev_id, fal_port_t port_id, - a_uint32_t * rate_in_pps) -{ - a_uint32_t data; - sw_error_t rv; - - HSL_DEV_ID_CHECK(dev_id); - - if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU)) - { - return SW_BAD_PARAM; - } - - rv = garuda_stormrate_sw_to_hw(*rate_in_pps, &data); - SW_RTN_ON_ERROR(rv); - - HSL_REG_FIELD_SET(rv, dev_id, STORM_CTL, port_id, RATE, - (a_uint8_t *) (&data), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - - rv = garuda_stormrate_hw_to_sw(data, rate_in_pps); - SW_RTN_ON_ERROR(rv); - - return SW_OK; -} - -static sw_error_t -_garuda_storm_ctrl_rate_get(a_uint32_t dev_id, fal_port_t port_id, - a_uint32_t * rate_in_pps) -{ - a_uint32_t data; - sw_error_t rv; - - HSL_DEV_ID_CHECK(dev_id); - - if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU)) - { - return SW_BAD_PARAM; - } - - HSL_REG_FIELD_GET(rv, dev_id, STORM_CTL, port_id, RATE, - (a_uint8_t *) (&data), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - - rv = garuda_stormrate_hw_to_sw(data, rate_in_pps); - return rv; -} - -/** - * @brief Set queue egress rate limit status on one particular port and queue. - * @details Comments: - The granularity of speed is bps. - Because of hardware granularity function will return actual speed in hardware. - When disable queue egress rate limit input parameter speed is meaningless. - Egress queue rate limit can't coexist with port egress rate limit. - The step of speed is 32kbps. - * @param[in] dev_id device id - * @param[in] port_id port id - * @param[in] queue_id queue id - * @param speed rate limit speed - * @param[in] enable A_TRUE or A_FALSE - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -garuda_rate_queue_egrl_set(a_uint32_t dev_id, fal_port_t port_id, - fal_queue_t queue_id, a_uint32_t * speed, - a_bool_t enable) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _garuda_rate_queue_egrl_set(dev_id, port_id, queue_id, speed, enable); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Get queue egress rate limit status on one particular port and queue. - * @param[in] dev_id device id - * @param[in] port_id port id - * @param[in] queue_id queue id - * @param[out] speed rate limit speed - * @param[out] enable A_TRUE or A_FALSE - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -garuda_rate_queue_egrl_get(a_uint32_t dev_id, fal_port_t port_id, - fal_queue_t queue_id, a_uint32_t * speed, - a_bool_t * enable) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _garuda_rate_queue_egrl_get(dev_id, port_id, queue_id, speed, enable); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Set port egress rate limit status on one particular port. - * @details Comments: - The granularity of speed is bps. - Because of hardware granularity function will return actual speed in hardware. - When disable port egress rate limit input parameter speed is meaningless. - Egress port rate limit can't coexist with queue egress rate limit. - The step of speed is 32kbps. - * @param[in] dev_id device id - * @param[in] port_id port id - * @param speed rate limit speed - * @param[in] enable A_TRUE or A_FALSE - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -garuda_rate_port_egrl_set(a_uint32_t dev_id, fal_port_t port_id, - a_uint32_t * speed, a_bool_t enable) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _garuda_rate_port_egrl_set(dev_id, port_id, speed, enable); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Get port egress rate limit status on one particular port. - * @param[in] dev_id device id - * @param[in] port_id port id - * @param[out] speed rate limit speed - * @param[out] enable A_TRUE or A_FALSE - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -garuda_rate_port_egrl_get(a_uint32_t dev_id, fal_port_t port_id, - a_uint32_t * speed, a_bool_t * enable) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _garuda_rate_port_egrl_get(dev_id, port_id, speed, enable); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Set port ingress rate limit status on one particular port. - * @details Comments: - The granularity of speed is bps. - Because of hardware granularity function will return actual speed in hardware. - When disable port ingress rate limit input parameter speed is meaningless. - The step of speed is 32kbps. - * When disable port ingress rate limit input parameter speed is meaningless. - * @param[in] dev_id device id - * @param[in] port_id port id - * @param speed rate limit speed - * @param[in] enable A_TRUE or A_FALSE - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -garuda_rate_port_inrl_set(a_uint32_t dev_id, fal_port_t port_id, - a_uint32_t * speed, a_bool_t enable) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _garuda_rate_port_inrl_set(dev_id, port_id, speed, enable); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Get port ingress rate limit status on one particular port. - * @param[in] dev_id device id - * @param[in] port_id port id - * @param[out] speed rate limit speed - * @param[out] enable A_TRUE or A_FALSE - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -garuda_rate_port_inrl_get(a_uint32_t dev_id, fal_port_t port_id, - a_uint32_t * speed, a_bool_t * enable) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _garuda_rate_port_inrl_get(dev_id, port_id, speed, enable); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Set particular type storm control status on one particular port. - * @details Comments: - * When enable one particular packets type storm control this type packets - * speed will be calculated in storm control. - * @param[in] dev_id device id - * @param[in] port_id port id - * @param[in] frame_type packets type which causes storm - * @param[in] enable A_TRUE or A_FALSE - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -garuda_storm_ctrl_frame_set(a_uint32_t dev_id, fal_port_t port_id, - fal_storm_type_t storm_type, a_bool_t enable) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _garuda_storm_ctrl_frame_set(dev_id, port_id, storm_type, enable); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Get particular type storm control status on one particular port. - * @param[in] dev_id device id - * @param[in] port_id port id - * @param[in] frame_type packets type which causes storm - * @param[out] enable A_TRUE or A_FALSE - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -garuda_storm_ctrl_frame_get(a_uint32_t dev_id, fal_port_t port_id, - fal_storm_type_t storm_type, a_bool_t * enable) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _garuda_storm_ctrl_frame_get(dev_id, port_id, storm_type, enable); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Set storm control speed on one particular port. - * @details Comments: - Because of hardware granularity function will return actual speed in hardware. - The step of speed is kpps. - The speed range is from 1k to 1M - * @param[in] dev_id device id - * @param[in] port_id port id - * @param speed storm control speed - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -garuda_storm_ctrl_rate_set(a_uint32_t dev_id, fal_port_t port_id, - a_uint32_t * rate_in_pps) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _garuda_storm_ctrl_rate_set(dev_id, port_id, rate_in_pps); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Get storm control speed on one particular port. - * @param[in] dev_id device id - * @param[in] port_id port id - * @param[out] speed storm control speed - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -garuda_storm_ctrl_rate_get(a_uint32_t dev_id, fal_port_t port_id, - a_uint32_t * rate_in_pps) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _garuda_storm_ctrl_rate_get(dev_id, port_id, rate_in_pps); - HSL_API_UNLOCK; - return rv; -} - -sw_error_t -garuda_rate_init(a_uint32_t dev_id) -{ - HSL_DEV_ID_CHECK(dev_id); - -#ifndef HSL_STANDALONG - { - hsl_api_t *p_api; - - SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id)); - - p_api->rate_queue_egrl_set = garuda_rate_queue_egrl_set; - p_api->rate_queue_egrl_get = garuda_rate_queue_egrl_get; - p_api->rate_port_egrl_set = garuda_rate_port_egrl_set; - p_api->rate_port_egrl_get = garuda_rate_port_egrl_get; - p_api->rate_port_inrl_set = garuda_rate_port_inrl_set; - p_api->rate_port_inrl_get = garuda_rate_port_inrl_get; - p_api->storm_ctrl_frame_set = garuda_storm_ctrl_frame_set; - p_api->storm_ctrl_frame_get = garuda_storm_ctrl_frame_get; - p_api->storm_ctrl_rate_set = garuda_storm_ctrl_rate_set; - p_api->storm_ctrl_rate_get = garuda_storm_ctrl_rate_get; - } -#endif - - return SW_OK; -} - -/** - * @} - */ - diff --git a/feeds/ipq807x/qca-ssdk/src/src/hsl/garuda/garuda_reduced_acl.c b/feeds/ipq807x/qca-ssdk/src/src/hsl/garuda/garuda_reduced_acl.c deleted file mode 100755 index 73d2a5aa3..000000000 --- a/feeds/ipq807x/qca-ssdk/src/src/hsl/garuda/garuda_reduced_acl.c +++ /dev/null @@ -1,170 +0,0 @@ -/* - * Copyright (c) 2012, The Linux Foundation. All rights reserved. - * Permission to use, copy, modify, and/or distribute this software for - * any purpose with or without fee is hereby granted, provided that the - * above copyright notice and this permission notice appear in all copies. - * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES - * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR - * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES - * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN - * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT - * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. - */ - -#include "sw.h" -#include "garuda_reduced_acl.h" -#include "hsl.h" - -#define GARUDA_RULE_VLU_ADDR 0x58400 -#define GARUDA_RULE_MSK_ADDR 0x58c00 -#define GARUDA_RULE_ACT_ADDR 0x58000 -#define GARUDA_RULE_SLCT_ADDR 0x58800 - -sw_error_t -garuda_acl_rule_write(a_uint32_t dev_id, a_uint32_t rule_idx, a_uint32_t vlu[8], - a_uint32_t msk[8]) -{ - sw_error_t rv; - a_uint32_t i, base, addr; - - /* set rule value */ - base = GARUDA_RULE_VLU_ADDR + (rule_idx << 5); - for (i = 0; i < 5; i++) - { - addr = base + (i << 2); - HSL_REG_ENTRY_GEN_SET(rv, dev_id, addr, sizeof (a_uint32_t), - (a_uint8_t *) (&(vlu[i])), - sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - } - - /* set rule mask */ - base = GARUDA_RULE_MSK_ADDR + (rule_idx << 5); - for (i = 0; i < 5; i++) - { - addr = base + (i << 2); - HSL_REG_ENTRY_GEN_SET(rv, dev_id, addr, sizeof (a_uint32_t), - (a_uint8_t *) (&(msk[i])), - sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - } - - return SW_OK; -} - -sw_error_t -garuda_acl_action_write(a_uint32_t dev_id, a_uint32_t act_idx, - a_uint32_t act) -{ - sw_error_t rv; - a_uint32_t addr; - - /* set rule action */ - addr = GARUDA_RULE_ACT_ADDR + (act_idx << 5); - HSL_REG_ENTRY_GEN_SET(rv, dev_id, addr, sizeof (a_uint32_t), - (a_uint8_t *) (&act), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - - return SW_OK; -} - -sw_error_t -garuda_acl_slct_write(a_uint32_t dev_id, a_uint32_t slct_idx, - a_uint32_t slct[8]) -{ - sw_error_t rv; - a_uint32_t base, addr; - a_uint32_t i; - - base = GARUDA_RULE_SLCT_ADDR + (slct_idx << 5); - - /* set rule address */ - for (i = 1; i < 7; i++) - { - addr = base + (i << 2); - HSL_REG_ENTRY_GEN_SET(rv, dev_id, addr, sizeof (a_uint32_t), - (a_uint8_t *) (&(slct[i])), - sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - } - - /* set rule enable */ - HSL_REG_ENTRY_GEN_SET(rv, dev_id, base, sizeof (a_uint32_t), - (a_uint8_t *) (&(slct[0])), - sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - - return SW_OK; -} - -sw_error_t -garuda_acl_rule_read(a_uint32_t dev_id, a_uint32_t rule_idx, a_uint32_t vlu[8], - a_uint32_t msk[8]) -{ - sw_error_t rv; - a_uint32_t i, base, addr; - - /* get rule value */ - base = GARUDA_RULE_VLU_ADDR + (rule_idx << 5); - for (i = 0; i < 5; i++) - { - addr = base + (i << 2); - HSL_REG_ENTRY_GEN_GET(rv, dev_id, addr, sizeof (a_uint32_t), - (a_uint8_t *) (&(vlu[i])), - sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - } - - /* get rule mask */ - base = GARUDA_RULE_MSK_ADDR + (rule_idx << 5); - for (i = 0; i < 5; i++) - { - addr = base + (i << 2); - HSL_REG_ENTRY_GEN_GET(rv, dev_id, addr, sizeof (a_uint32_t), - (a_uint8_t *) (&(msk[i])), - sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - } - - return SW_OK; -} - -sw_error_t -garuda_acl_action_read(a_uint32_t dev_id, a_uint32_t act_idx, - a_uint32_t * act) -{ - sw_error_t rv; - a_uint32_t addr; - - /* get rule action */ - addr = GARUDA_RULE_ACT_ADDR + (act_idx << 5); - HSL_REG_ENTRY_GEN_GET(rv, dev_id, addr, sizeof (a_uint32_t), - (a_uint8_t *) act, sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - - return SW_OK; -} - -sw_error_t -garuda_acl_slct_read(a_uint32_t dev_id, a_uint32_t slct_idx, - a_uint32_t slct[8]) -{ - sw_error_t rv; - a_uint32_t i, base, addr; - - base = GARUDA_RULE_SLCT_ADDR + (slct_idx << 5); - - /* get filter address and enable */ - for (i = 0; i < 7; i++) - { - addr = base + (i << 2); - HSL_REG_ENTRY_GEN_GET(rv, dev_id, addr, sizeof (a_uint32_t), - (a_uint8_t *) (&(slct[i])), - sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - } - - return SW_OK; -} - diff --git a/feeds/ipq807x/qca-ssdk/src/src/hsl/garuda/garuda_reg_access.c b/feeds/ipq807x/qca-ssdk/src/src/hsl/garuda/garuda_reg_access.c deleted file mode 100755 index 2fb078429..000000000 --- a/feeds/ipq807x/qca-ssdk/src/src/hsl/garuda/garuda_reg_access.c +++ /dev/null @@ -1,271 +0,0 @@ -/* - * Copyright (c) 2012, The Linux Foundation. All rights reserved. - * Permission to use, copy, modify, and/or distribute this software for - * any purpose with or without fee is hereby granted, provided that the - * above copyright notice and this permission notice appear in all copies. - * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES - * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR - * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES - * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN - * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT - * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. - */ - - -#include "sw.h" -#include "hsl.h" -#include "hsl_dev.h" -#include "sd.h" -#include "garuda_reg_access.h" - -static hsl_access_mode reg_mode; - -#if defined(API_LOCK) -static aos_lock_t mdio_lock; -#define MDIO_LOCKER_INIT aos_lock_init(&mdio_lock) -#define MDIO_LOCKER_LOCK aos_lock(&mdio_lock) -#define MDIO_LOCKER_UNLOCK aos_unlock(&mdio_lock) -#else -#define MDIO_LOCKER_INIT -#define MDIO_LOCKER_LOCK -#define MDIO_LOCKER_UNLOCK -#endif - -static sw_error_t -_garuda_mdio_reg_get(a_uint32_t dev_id, a_uint32_t reg_addr, - a_uint8_t value[], a_uint32_t value_len) -{ - a_uint32_t reg_word_addr; - a_uint32_t phy_addr, reg_val; - a_uint16_t phy_val, tmp_val; - a_uint8_t phy_reg; - sw_error_t rv; - - if (value_len != sizeof (a_uint32_t)) - return SW_BAD_LEN; - - /* change reg_addr to 16-bit word address, 32-bit aligned */ - reg_word_addr = (reg_addr & 0xfffffffc) >> 1; - - /* configure register high address */ - phy_addr = 0x18; - phy_reg = 0x0; - phy_val = (a_uint16_t) ((reg_word_addr >> 8) & 0x3ff); /* bit16-8 of reg address */ - - rv = sd_reg_mdio_set(dev_id, phy_addr, phy_reg, phy_val); - SW_RTN_ON_ERROR(rv); - - /* For some registers such as MIBs, since it is read/clear, we should */ - /* read the lower 16-bit register then the higher one */ - - /* read register in lower address */ - phy_addr = 0x10 | ((reg_word_addr >> 5) & 0x7); /* bit7-5 of reg address */ - phy_reg = (a_uint8_t) (reg_word_addr & 0x1f); /* bit4-0 of reg address */ - rv = sd_reg_mdio_get(dev_id, phy_addr, phy_reg, &tmp_val); - SW_RTN_ON_ERROR(rv); - reg_val = tmp_val; - - /* read register in higher address */ - reg_word_addr++; - phy_addr = 0x10 | ((reg_word_addr >> 5) & 0x7); /* bit7-5 of reg address */ - phy_reg = (a_uint8_t) (reg_word_addr & 0x1f); /* bit4-0 of reg address */ - rv = sd_reg_mdio_get(dev_id, phy_addr, phy_reg, &tmp_val); - SW_RTN_ON_ERROR(rv); - reg_val |= (((a_uint32_t)tmp_val) << 16); - - aos_mem_copy(value, ®_val, sizeof (a_uint32_t)); - - return SW_OK; -} - -static sw_error_t -_garuda_mdio_reg_set(a_uint32_t dev_id, a_uint32_t reg_addr, a_uint8_t value[], - a_uint32_t value_len) -{ - a_uint32_t reg_word_addr; - a_uint32_t phy_addr, reg_val; - a_uint16_t phy_val; - a_uint8_t phy_reg; - sw_error_t rv; - - if (value_len != sizeof (a_uint32_t)) - return SW_BAD_LEN; - - aos_mem_copy(®_val, value, sizeof (a_uint32_t)); - - /* change reg_addr to 16-bit word address, 32-bit aligned */ - reg_word_addr = (reg_addr & 0xfffffffc) >> 1; - - /* configure register high address */ - phy_addr = 0x18; - phy_reg = 0x0; - phy_val = (a_uint16_t) ((reg_word_addr >> 8) & 0x3ff); /* bit16-8 of reg address */ - - rv = sd_reg_mdio_set(dev_id, phy_addr, phy_reg, phy_val); - SW_RTN_ON_ERROR(rv); - - /* For some registers such as ARL and VLAN, since they include BUSY bit */ - /* in lower address, we should write the higher 16-bit register then the */ - /* lower one */ - - /* write register in higher address */ - reg_word_addr++; - phy_addr = 0x10 | ((reg_word_addr >> 5) & 0x7); /* bit7-5 of reg address */ - phy_reg = (a_uint8_t) (reg_word_addr & 0x1f); /* bit4-0 of reg address */ - phy_val = (a_uint16_t) ((reg_val >> 16) & 0xffff); - rv = sd_reg_mdio_set(dev_id, phy_addr, phy_reg, phy_val); - SW_RTN_ON_ERROR(rv); - - /* write register in lower address */ - reg_word_addr--; - phy_addr = 0x10 | ((reg_word_addr >> 5) & 0x7); /* bit7-5 of reg address */ - phy_reg = (a_uint8_t) (reg_word_addr & 0x1f); /* bit4-0 of reg address */ - phy_val = (a_uint16_t) (reg_val & 0xffff); - rv = sd_reg_mdio_set(dev_id, phy_addr, phy_reg, phy_val); - SW_RTN_ON_ERROR(rv); - - return SW_OK; -} - -sw_error_t -garuda_phy_get(a_uint32_t dev_id, a_uint32_t phy_addr, - a_uint32_t reg, a_uint16_t * value) -{ - sw_error_t rv; - - MDIO_LOCKER_LOCK; - rv = sd_reg_mdio_get(dev_id, phy_addr, reg, value); - MDIO_LOCKER_UNLOCK; - - return rv; -} - -sw_error_t -garuda_phy_set(a_uint32_t dev_id, a_uint32_t phy_addr, - a_uint32_t reg, a_uint16_t value) -{ - sw_error_t rv; - - MDIO_LOCKER_LOCK; - rv = sd_reg_mdio_set(dev_id, phy_addr, reg, value); - MDIO_LOCKER_UNLOCK; - - return rv; -} - -sw_error_t -garuda_reg_get(a_uint32_t dev_id, a_uint32_t reg_addr, a_uint8_t value[], - a_uint32_t value_len) -{ - sw_error_t rv; - a_uint32_t flags; - - MDIO_LOCKER_LOCK; - if (HSL_MDIO == reg_mode) - { - aos_irq_save(flags); - rv = _garuda_mdio_reg_get(dev_id, reg_addr, value, value_len); - aos_irq_restore(flags); - } - else - { - rv = sd_reg_hdr_get(dev_id, reg_addr, value, value_len); - } - MDIO_LOCKER_UNLOCK; - - return rv; -} - -sw_error_t -garuda_reg_set(a_uint32_t dev_id, a_uint32_t reg_addr, a_uint8_t value[], - a_uint32_t value_len) -{ - sw_error_t rv; - a_uint32_t flags; - - MDIO_LOCKER_LOCK; - if (HSL_MDIO == reg_mode) - { - aos_irq_save(flags); - rv = _garuda_mdio_reg_set(dev_id, reg_addr, value, value_len); - aos_irq_restore(flags); - } - else - { - rv = sd_reg_hdr_set(dev_id, reg_addr, value, value_len); - } - MDIO_LOCKER_UNLOCK; - - return rv; -} - -sw_error_t -garuda_reg_field_get(a_uint32_t dev_id, a_uint32_t reg_addr, - a_uint32_t bit_offset, a_uint32_t field_len, - a_uint8_t value[], a_uint32_t value_len) -{ - a_uint32_t reg_val = 0; - - if ((bit_offset >= 32 || (field_len > 32)) || (field_len == 0)) - return SW_OUT_OF_RANGE; - - if (value_len != sizeof (a_uint32_t)) - return SW_BAD_LEN; - - SW_RTN_ON_ERROR(garuda_reg_get(dev_id, reg_addr, (a_uint8_t *) & reg_val, sizeof (a_uint32_t))); - - *((a_uint32_t *) value) = SW_REG_2_FIELD(reg_val, bit_offset, field_len); - return SW_OK; -} - -sw_error_t -garuda_reg_field_set(a_uint32_t dev_id, a_uint32_t reg_addr, - a_uint32_t bit_offset, a_uint32_t field_len, - const a_uint8_t value[], a_uint32_t value_len) -{ - a_uint32_t reg_val; - a_uint32_t field_val = *((a_uint32_t *) value); - - if ((bit_offset >= 32 || (field_len > 32)) || (field_len == 0)) - return SW_OUT_OF_RANGE; - - if (value_len != sizeof (a_uint32_t)) - return SW_BAD_LEN; - - SW_RTN_ON_ERROR(garuda_reg_get(dev_id, reg_addr, (a_uint8_t *) & reg_val, sizeof (a_uint32_t))); - - SW_REG_SET_BY_FIELD_U32(reg_val, field_val, bit_offset, field_len); - - SW_RTN_ON_ERROR(garuda_reg_set(dev_id, reg_addr, (a_uint8_t *) & reg_val, sizeof (a_uint32_t))); - - return SW_OK; -} - -sw_error_t -garuda_reg_access_init(a_uint32_t dev_id, hsl_access_mode mode) -{ - hsl_api_t *p_api; - - MDIO_LOCKER_INIT; - reg_mode = mode; - - SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id)); - p_api->phy_get = garuda_phy_get; - p_api->phy_set = garuda_phy_set; - p_api->reg_get = garuda_reg_get; - p_api->reg_set = garuda_reg_set; - p_api->reg_field_get = garuda_reg_field_get; - p_api->reg_field_set = garuda_reg_field_set; - p_api->dev_access_set= garuda_access_mode_set; - - return SW_OK; -} - -sw_error_t -garuda_access_mode_set(a_uint32_t dev_id, hsl_access_mode mode) -{ - reg_mode = mode; - return SW_OK; - -} diff --git a/feeds/ipq807x/qca-ssdk/src/src/hsl/garuda/garuda_stp.c b/feeds/ipq807x/qca-ssdk/src/src/hsl/garuda/garuda_stp.c deleted file mode 100755 index b05435c05..000000000 --- a/feeds/ipq807x/qca-ssdk/src/src/hsl/garuda/garuda_stp.c +++ /dev/null @@ -1,193 +0,0 @@ -/* - * Copyright (c) 2012, The Linux Foundation. All rights reserved. - * Permission to use, copy, modify, and/or distribute this software for - * any purpose with or without fee is hereby granted, provided that the - * above copyright notice and this permission notice appear in all copies. - * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES - * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR - * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES - * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN - * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT - * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. - */ - - -/** - * @defgroup garuda_stp GARUDA_STP - * @{ - */ -#include "sw.h" -#include "hsl.h" -#include "hsl_dev.h" -#include "hsl_port_prop.h" -#include "garuda_stp.h" -#include "garuda_reg.h" - -#define GARUDA_PORT_DISABLED 0 -#define GARUDA_STP_BLOCKING 1 -#define GARUDA_STP_LISTENING 2 -#define GARUDA_STP_LEARNING 3 -#define GARUDA_STP_FARWARDING 4 - -static sw_error_t -_garuda_stp_port_state_set(a_uint32_t dev_id, a_uint32_t st_id, - fal_port_t port_id, fal_stp_state_t state) -{ - sw_error_t rv; - a_uint32_t val; - - HSL_DEV_ID_CHECK(dev_id); - - if (FAL_SINGLE_STP_ID != st_id) - { - return SW_BAD_PARAM; - } - - if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_EXCL_CPU)) - { - return SW_BAD_PARAM; - } - - switch (state) - { - case FAL_STP_BLOKING: - val = GARUDA_STP_BLOCKING; - break; - case FAL_STP_LISTENING: - val = GARUDA_STP_LISTENING; - break; - case FAL_STP_LEARNING: - val = GARUDA_STP_LEARNING; - break; - case FAL_STP_FARWARDING: - val = GARUDA_STP_FARWARDING; - break; - case FAL_STP_DISABLED: - val = GARUDA_PORT_DISABLED; - break; - default: - return SW_BAD_PARAM; - } - - HSL_REG_FIELD_SET(rv, dev_id, PORT_CTL, port_id, PORT_STATE, - (a_uint8_t *) (&val), sizeof (a_uint32_t)); - return rv; -} - -static sw_error_t -_garuda_stp_port_state_get(a_uint32_t dev_id, a_uint32_t st_id, - fal_port_t port_id, fal_stp_state_t * state) -{ - sw_error_t rv; - a_uint32_t val; - - HSL_DEV_ID_CHECK(dev_id); - - if (FAL_SINGLE_STP_ID != st_id) - { - return SW_BAD_PARAM; - } - - if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_EXCL_CPU)) - { - return SW_BAD_PARAM; - } - - HSL_REG_FIELD_GET(rv, dev_id, PORT_CTL, port_id, PORT_STATE, - (a_uint8_t *) (&val), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - - switch (val) - { - case GARUDA_STP_BLOCKING: - *state = FAL_STP_BLOKING; - break; - case GARUDA_STP_LISTENING: - *state = FAL_STP_LISTENING; - break; - case GARUDA_STP_LEARNING: - *state = FAL_STP_LEARNING; - break; - case GARUDA_STP_FARWARDING: - *state = FAL_STP_FARWARDING; - break; - case GARUDA_PORT_DISABLED: - *state = FAL_STP_DISABLED; - break; - default: - return SW_FAIL; - } - - return SW_OK; -} - -/** - * @brief Set port stp state on a particular spanning tree and port. - * @details Comments: - GARUDA only support single spanning tree so st_id should be - FAL_SINGLE_STP_ID that is zero. - * @param[in] dev_id device id - * @param[in] st_id spanning tree id - * @param[in] port_id port id - * @param[in] state port state for spanning tree - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -garuda_stp_port_state_set(a_uint32_t dev_id, a_uint32_t st_id, - fal_port_t port_id, fal_stp_state_t state) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _garuda_stp_port_state_set(dev_id, st_id, port_id, state); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Get port stp state on a particular spanning tree and port. - * @details Comments: - GARUDA only support single spanning tree so st_id should be - FAL_SINGLE_STP_ID that is zero. - * @param[in] dev_id device id - * @param[in] st_id spanning tree id - * @param[in] port_id port id - * @param[out] state port state for spanning tree - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -garuda_stp_port_state_get(a_uint32_t dev_id, a_uint32_t st_id, - fal_port_t port_id, fal_stp_state_t * state) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _garuda_stp_port_state_get(dev_id, st_id, port_id, state); - HSL_API_UNLOCK; - return rv; -} - -sw_error_t -garuda_stp_init(a_uint32_t dev_id) -{ - HSL_DEV_ID_CHECK(dev_id); - -#ifndef HSL_STANDALONG - { - hsl_api_t *p_api; - - SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id)); - - p_api->stp_port_state_set = garuda_stp_port_state_set; - p_api->stp_port_state_get = garuda_stp_port_state_get; - } -#endif - - return SW_OK; -} - -/** - * @} - */ - diff --git a/feeds/ipq807x/qca-ssdk/src/src/hsl/garuda/garuda_vlan.c b/feeds/ipq807x/qca-ssdk/src/src/hsl/garuda/garuda_vlan.c deleted file mode 100755 index 5f001d5c9..000000000 --- a/feeds/ipq807x/qca-ssdk/src/src/hsl/garuda/garuda_vlan.c +++ /dev/null @@ -1,498 +0,0 @@ -/* - * Copyright (c) 2012, The Linux Foundation. All rights reserved. - * Permission to use, copy, modify, and/or distribute this software for - * any purpose with or without fee is hereby granted, provided that the - * above copyright notice and this permission notice appear in all copies. - * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES - * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR - * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES - * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN - * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT - * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. - */ - - -/** - * @defgroup garuda_vlan GARUDA_VLAN - * @{ - */ -#include "sw.h" -#include "hsl.h" -#include "hsl_dev.h" -#include "hsl_port_prop.h" -#include "garuda_vlan.h" -#include "garuda_reg.h" - -#define MAX_VLAN_ID 4095 - -#define VLAN_FLUSH 1 -#define VLAN_LOAD_ENTRY 2 -#define VLAN_PURGE_ENTRY 3 -#define VLAN_REMOVE_PORT 4 -#define VLAN_NEXT_ENTRY 5 -#define VLAN_FIND_ENTRY 6 - -static void -garuda_vlan_hw_to_sw(const a_uint32_t reg[], fal_vlan_t * vlan_entry) -{ - a_uint32_t data; - - SW_GET_FIELD_BY_REG(VLAN_TABLE_FUNC0, VT_PRI_EN, data, reg[0]); - if (1 == data) - { - vlan_entry->vid_pri_en = A_TRUE; - - SW_GET_FIELD_BY_REG(VLAN_TABLE_FUNC0, VT_PRI, data, reg[0]); - vlan_entry->vid_pri = data & 0xff; - } - else - { - vlan_entry->vid_pri_en = A_FALSE; - } - - SW_GET_FIELD_BY_REG(VLAN_TABLE_FUNC0, VLAN_ID, data, reg[0]); - vlan_entry->vid = data & 0xffff; - - SW_GET_FIELD_BY_REG(VLAN_TABLE_FUNC1, VID_MEM, data, reg[1]); - vlan_entry->mem_ports = data; - - return; -} - -static sw_error_t -garuda_vlan_sw_to_hw(const fal_vlan_t * vlan_entry, a_uint32_t reg[]) -{ - if (A_TRUE == vlan_entry->vid_pri_en) - { - SW_SET_REG_BY_FIELD(VLAN_TABLE_FUNC0, VT_PRI_EN, 1, reg[0]); - SW_SET_REG_BY_FIELD(VLAN_TABLE_FUNC0, VT_PRI, vlan_entry->vid_pri, reg[0]); - } - else - { - SW_SET_REG_BY_FIELD(VLAN_TABLE_FUNC0, VT_PRI_EN, 0, reg[0]); - } - - SW_SET_REG_BY_FIELD(VLAN_TABLE_FUNC0, VLAN_ID, vlan_entry->vid, reg[0]); - - SW_SET_REG_BY_FIELD(VLAN_TABLE_FUNC1, VT_VALID, 1, reg[1]); - SW_SET_REG_BY_FIELD(VLAN_TABLE_FUNC1, VID_MEM, vlan_entry->mem_ports, reg[1]); - - if (0 != vlan_entry->u_ports) - { - return SW_BAD_VALUE; - } - - return SW_OK; -} - -static sw_error_t -garuda_vlan_commit(a_uint32_t dev_id, a_uint32_t op) -{ - a_uint32_t vt_busy = 1, i = 0x1000, vt_full, val; - sw_error_t rv; - - while (vt_busy && --i) - { - HSL_REG_FIELD_GET(rv, dev_id, VLAN_TABLE_FUNC0, 0, VT_BUSY, - (a_uint8_t *) (&vt_busy), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - aos_udelay(5); - } - - if (i == 0) - return SW_BUSY; - - HSL_REG_ENTRY_GET(rv, dev_id, VLAN_TABLE_FUNC0, 0, - (a_uint8_t *) (&val), sizeof (a_uint32_t)); - SW_SET_REG_BY_FIELD(VLAN_TABLE_FUNC0, VT_FUNC, op, val); - SW_SET_REG_BY_FIELD(VLAN_TABLE_FUNC0, VT_BUSY, 1, val); - - HSL_REG_ENTRY_SET(rv, dev_id, VLAN_TABLE_FUNC0, 0, - (a_uint8_t *) (&val), sizeof (a_uint32_t)); - - SW_RTN_ON_ERROR(rv); - - vt_busy = 1; - i = 0x1000; - while (vt_busy && --i) - { - HSL_REG_FIELD_GET(rv, dev_id, VLAN_TABLE_FUNC0, 0, VT_BUSY, - (a_uint8_t *) (&vt_busy), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - aos_udelay(5); - } - - if (i == 0) - return SW_FAIL; - - HSL_REG_FIELD_GET(rv, dev_id, VLAN_TABLE_FUNC0, 0, VT_FULL_VIO, - (a_uint8_t *) (&vt_full), sizeof (a_uint32_t)); - - SW_RTN_ON_ERROR(rv); - - if (vt_full) - { - val = 0x10; - HSL_REG_ENTRY_SET(rv, dev_id, VLAN_TABLE_FUNC0, 0, - (a_uint8_t *) (&val), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - if (VLAN_LOAD_ENTRY == op) - { - return SW_FULL; - } - else if (VLAN_PURGE_ENTRY == op) - { - return SW_NOT_FOUND; - } - } - - HSL_REG_FIELD_GET(rv, dev_id, VLAN_TABLE_FUNC1, 0, VT_VALID, - (a_uint8_t *) (&val), sizeof (a_uint32_t)); - - SW_RTN_ON_ERROR(rv); - - if (!val) - { - if (VLAN_FIND_ENTRY == op) - return SW_NOT_FOUND; - - if (VLAN_NEXT_ENTRY == op) - return SW_NO_MORE; - } - - return SW_OK; -} - -static sw_error_t -_garuda_vlan_entry_append(a_uint32_t dev_id, const fal_vlan_t * vlan_entry) -{ - sw_error_t rv; - a_uint32_t reg[2] = { 0 }; - - HSL_DEV_ID_CHECK(dev_id); - - if ((vlan_entry->vid == 0) || (vlan_entry->vid > MAX_VLAN_ID)) - return SW_OUT_OF_RANGE; - - if (A_FALSE == hsl_mports_prop_check(dev_id, vlan_entry->mem_ports, HSL_PP_INCL_CPU)) - return SW_BAD_PARAM; - - rv = garuda_vlan_sw_to_hw(vlan_entry, reg); - SW_RTN_ON_ERROR(rv); - - HSL_REG_ENTRY_SET(rv, dev_id, VLAN_TABLE_FUNC0, 0, - (a_uint8_t *) (®[0]), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - - HSL_REG_ENTRY_SET(rv, dev_id, VLAN_TABLE_FUNC1, 0, - (a_uint8_t *) (®[1]), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - - rv = garuda_vlan_commit(dev_id, VLAN_LOAD_ENTRY); - return rv; -} - -static sw_error_t -_garuda_vlan_create(a_uint32_t dev_id, a_uint32_t vlan_id) -{ - sw_error_t rv; - a_uint32_t entry = 0; - - HSL_DEV_ID_CHECK(dev_id); - - if ((vlan_id == 0) || (vlan_id > MAX_VLAN_ID)) - return SW_OUT_OF_RANGE; - - /* set default value for VLAN_TABLE_FUNC0, all 0 except vid */ - entry = 0; - SW_SET_REG_BY_FIELD(VLAN_TABLE_FUNC0, VLAN_ID, vlan_id, entry); - HSL_REG_ENTRY_SET(rv, dev_id, VLAN_TABLE_FUNC0, 0, - (a_uint8_t *) (&entry), sizeof (a_uint32_t)); - - SW_RTN_ON_ERROR(rv); - - /* set default value for VLAN_TABLE_FUNC1, all 0 */ - entry = 0; - SW_SET_REG_BY_FIELD(VLAN_TABLE_FUNC1, VT_VALID, 1, entry); - HSL_REG_ENTRY_SET(rv, dev_id, VLAN_TABLE_FUNC1, 0, - (a_uint8_t *) (&entry), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - - rv = garuda_vlan_commit(dev_id, VLAN_LOAD_ENTRY); - return rv; -} - -static sw_error_t -_garuda_vlan_next(a_uint32_t dev_id, a_uint32_t vlan_id, fal_vlan_t * p_vlan) -{ - sw_error_t rv; - a_uint32_t reg[2] = { 0 }; - - HSL_DEV_ID_CHECK(dev_id); - - if (vlan_id > MAX_VLAN_ID) - return SW_OUT_OF_RANGE; - - aos_mem_zero(p_vlan, sizeof (fal_vlan_t)); - - SW_SET_REG_BY_FIELD(VLAN_TABLE_FUNC0, VLAN_ID, vlan_id, reg[0]); - HSL_REG_ENTRY_SET(rv, dev_id, VLAN_TABLE_FUNC0, 0, - (a_uint8_t *) (®[0]), sizeof (a_uint32_t)); - - SW_RTN_ON_ERROR(rv); - - rv = garuda_vlan_commit(dev_id, VLAN_NEXT_ENTRY); - SW_RTN_ON_ERROR(rv); - - HSL_REG_ENTRY_GET(rv, dev_id, VLAN_TABLE_FUNC0, 0, - (a_uint8_t *) (®[0]), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - - HSL_REG_ENTRY_GET(rv, dev_id, VLAN_TABLE_FUNC1, 0, - (a_uint8_t *) (®[1]), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - - garuda_vlan_hw_to_sw(reg, p_vlan); - - if (0 == p_vlan->vid) - return SW_NO_MORE; - else - return SW_OK; -} - -static sw_error_t -_garuda_vlan_find(a_uint32_t dev_id, a_uint32_t vlan_id, fal_vlan_t * p_vlan) -{ - sw_error_t rv; - a_uint32_t reg[2] = { 0 }; - - HSL_DEV_ID_CHECK(dev_id); - - if ((vlan_id == 0) || (vlan_id > MAX_VLAN_ID)) - return SW_OUT_OF_RANGE; - - aos_mem_zero(p_vlan, sizeof (fal_vlan_t)); - - SW_SET_REG_BY_FIELD(VLAN_TABLE_FUNC0, VLAN_ID, vlan_id, reg[0]); - HSL_REG_ENTRY_SET(rv, dev_id, VLAN_TABLE_FUNC0, 0, - (a_uint8_t *) (®[0]), sizeof (a_uint32_t)); - - SW_RTN_ON_ERROR(rv); - - rv = garuda_vlan_commit(dev_id, VLAN_FIND_ENTRY); - SW_RTN_ON_ERROR(rv); - - HSL_REG_ENTRY_GET(rv, dev_id, VLAN_TABLE_FUNC0, 0, - (a_uint8_t *) (®[0]), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - - HSL_REG_ENTRY_GET(rv, dev_id, VLAN_TABLE_FUNC1, 0, - (a_uint8_t *) (®[1]), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - - garuda_vlan_hw_to_sw(reg, p_vlan); - - return SW_OK; -} - -static sw_error_t -_garuda_vlan_member_update(a_uint32_t dev_id, a_uint32_t vlan_id, - fal_pbmp_t member, fal_pbmp_t u_member) -{ - sw_error_t rv; - a_uint32_t reg = 0; - - HSL_DEV_ID_CHECK(dev_id); - - if ((vlan_id == 0) || (vlan_id > MAX_VLAN_ID)) - return SW_OUT_OF_RANGE; - - if (A_FALSE == hsl_mports_prop_check(dev_id, member, HSL_PP_INCL_CPU)) - return SW_BAD_PARAM; - - if (u_member != 0) - return SW_BAD_PARAM; - - /* get vlan entry first */ - SW_SET_REG_BY_FIELD(VLAN_TABLE_FUNC0, VLAN_ID, vlan_id, reg); - HSL_REG_ENTRY_SET(rv, dev_id, VLAN_TABLE_FUNC0, 0, - (a_uint8_t *) (®), sizeof (a_uint32_t)); - - SW_RTN_ON_ERROR(rv); - - rv = garuda_vlan_commit(dev_id, VLAN_FIND_ENTRY); - SW_RTN_ON_ERROR(rv); - - /* set vlan member for VLAN_TABLE_FUNC1 */ - HSL_REG_FIELD_SET(rv, dev_id, VLAN_TABLE_FUNC1, 0, VID_MEM, - (a_uint8_t *) (&member), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - - rv = garuda_vlan_commit(dev_id, VLAN_LOAD_ENTRY); - /* when update port member through LOAD opration, hardware will - return VT_FULL_VIO, we should ignore it */ - if (SW_FULL == rv) - rv = SW_OK; - - return rv; -} - - -static sw_error_t -_garuda_vlan_delete(a_uint32_t dev_id, a_uint32_t vlan_id) -{ - sw_error_t rv; - a_uint32_t reg; - - HSL_DEV_ID_CHECK(dev_id); - - if ((vlan_id == 0) || (vlan_id > MAX_VLAN_ID)) - return SW_OUT_OF_RANGE; - - reg = (a_int32_t) vlan_id; - HSL_REG_FIELD_SET(rv, dev_id, VLAN_TABLE_FUNC0, 0, VLAN_ID, - (a_uint8_t *) (®), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - - rv = garuda_vlan_commit(dev_id, VLAN_PURGE_ENTRY); - return rv; -} - -/** - * @brief Append a vlan entry on paticular device. - * @param[in] dev_id device id - * @param[in] vlan_entry vlan entry - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -garuda_vlan_entry_append(a_uint32_t dev_id, const fal_vlan_t * vlan_entry) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _garuda_vlan_entry_append(dev_id, vlan_entry); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Creat a vlan entry through vlan id on a paticular device. - * @details Comments: - * After this operation the member ports of the created vlan entry are null. - * @param[in] dev_id device id - * @param[in] vlan_id vlan id - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -garuda_vlan_create(a_uint32_t dev_id, a_uint32_t vlan_id) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _garuda_vlan_create(dev_id, vlan_id); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Next a vlan entry through vlan id on a paticular device. - * @details Comments: - * If the value of vid is zero this operation will get the first entry. - * @param[in] dev_id device id - * @param[in] vlan_id vlan id - * @param[out] p_vlan vlan entry - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -garuda_vlan_next(a_uint32_t dev_id, a_uint32_t vlan_id, fal_vlan_t * p_vlan) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _garuda_vlan_next(dev_id, vlan_id, p_vlan); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Find a vlan entry through vlan id on paticular device. - * @param[in] dev_id device id - * @param[in] vlan_id vlan id - * @param[out] p_vlan vlan entry - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -garuda_vlan_find(a_uint32_t dev_id, a_uint32_t vlan_id, fal_vlan_t * p_vlan) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _garuda_vlan_find(dev_id, vlan_id, p_vlan); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Update a vlan entry member port through vlan id on a paticular device. - * @param[in] dev_id device id - * @param[in] vlan_id vlan id - * @param[in] member member ports - * @param[in] u_member tagged or untagged infomation for member ports - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -garuda_vlan_member_update(a_uint32_t dev_id, a_uint32_t vlan_id, - fal_pbmp_t member, fal_pbmp_t u_member) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _garuda_vlan_member_update(dev_id, vlan_id, member, u_member); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Delete a vlan entry through vlan id on a paticular device. - * @param[in] dev_id device id - * @param[in] vlan_id vlan id - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -garuda_vlan_delete(a_uint32_t dev_id, a_uint32_t vlan_id) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _garuda_vlan_delete(dev_id, vlan_id); - HSL_API_UNLOCK; - return rv; -} - -sw_error_t -garuda_vlan_init(a_uint32_t dev_id) -{ - HSL_DEV_ID_CHECK(dev_id); - -#ifndef HSL_STANDALONG - hsl_api_t *p_api; - - SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id)); - - p_api->vlan_entry_append = garuda_vlan_entry_append; - p_api->vlan_creat = garuda_vlan_create; - p_api->vlan_member_update = garuda_vlan_member_update; - p_api->vlan_delete = garuda_vlan_delete; - p_api->vlan_next = garuda_vlan_next; - p_api->vlan_find = garuda_vlan_find; - -#endif - - return SW_OK; -} - -/** - * @} - */ - diff --git a/feeds/ipq807x/qca-ssdk/src/src/hsl/horus/Makefile b/feeds/ipq807x/qca-ssdk/src/src/hsl/horus/Makefile deleted file mode 100755 index bdbd6c0b2..000000000 --- a/feeds/ipq807x/qca-ssdk/src/src/hsl/horus/Makefile +++ /dev/null @@ -1,80 +0,0 @@ -LOC_DIR=src/hsl/horus -LIB=HSL - -include $(PRJ_PATH)/make/config.mk - -SRC_LIST=horus_reg_access.c horus_init.c - -ifeq (TRUE, $(IN_FDB)) - SRC_LIST += horus_fdb.c -endif - -ifeq (TRUE, $(IN_IGMP)) - SRC_LIST += horus_igmp.c -endif - -ifeq (TRUE, $(IN_LEAKY)) - SRC_LIST += horus_leaky.c -endif - -ifeq (TRUE, $(IN_LED)) - SRC_LIST += horus_led.c -endif - -ifeq (TRUE, $(IN_MIB)) - SRC_LIST += horus_mib.c -endif - -ifeq (TRUE, $(IN_MIRROR)) - SRC_LIST += horus_mirror.c -endif - -ifeq (TRUE, $(IN_MISC)) - SRC_LIST += horus_misc.c -endif - -ifeq (TRUE, $(IN_PORTCONTROL)) - SRC_LIST += horus_port_ctrl.c -endif - -ifeq (TRUE, $(IN_PORTVLAN)) - SRC_LIST += horus_portvlan.c -endif - -ifeq (TRUE, $(IN_QOS)) - SRC_LIST += horus_qos.c -endif - -ifeq (TRUE, $(IN_RATE)) - SRC_LIST += horus_rate.c -endif - -ifeq (TRUE, $(IN_STP)) - SRC_LIST += horus_stp.c -endif - -ifeq (TRUE, $(IN_VLAN)) - SRC_LIST += horus_vlan.c -endif - -ifeq (TRUE, $(IN_REDUCED_ACL)) - SRC_LIST += horus_reduced_acl.c -endif - -ifeq (linux, $(OS)) - ifeq (KSLIB, $(MODULE_TYPE)) - ifneq (TRUE, $(KERNEL_MODE)) - SRC_LIST=horus_reg_access.c horus_init.c - endif - endif -endif - -ifeq (, $(findstring HORUS, $(SUPPORT_CHIP))) - SRC_LIST= -endif - -include $(PRJ_PATH)/make/components.mk -include $(PRJ_PATH)/make/defs.mk -include $(PRJ_PATH)/make/target.mk - -all: dep obj \ No newline at end of file diff --git a/feeds/ipq807x/qca-ssdk/src/src/hsl/horus/horus_fdb.c b/feeds/ipq807x/qca-ssdk/src/src/hsl/horus/horus_fdb.c deleted file mode 100755 index 6ca18e032..000000000 --- a/feeds/ipq807x/qca-ssdk/src/src/hsl/horus/horus_fdb.c +++ /dev/null @@ -1,999 +0,0 @@ -/* - * Copyright (c) 2012, The Linux Foundation. All rights reserved. - * Permission to use, copy, modify, and/or distribute this software for - * any purpose with or without fee is hereby granted, provided that the - * above copyright notice and this permission notice appear in all copies. - * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES - * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR - * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES - * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN - * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT - * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. - */ - - -/** - * @defgroup horus_fdb HORUS_FDB - * @{ - */ -#include "sw.h" -#include "hsl.h" -#include "hsl_dev.h" -#include "hsl_port_prop.h" -#include "horus_fdb.h" -#include "horus_reg.h" - -#define ARL_FLUSH_ALL 1 -#define ARL_LOAD_ENTRY 2 -#define ARL_PURGE_ENTRY 3 -#define ARL_FLUSH_ALL_UNLOCK 4 -#define ARL_FLUSH_PORT_UNICAST 5 -#define ARL_NEXT_ENTRY 6 -#define ARL_FIND_ENTRY 7 - -#define ARL_FIRST_ENTRY 1001 -#define ARL_FLUSH_PORT_NO_STATIC 1002 -#define ARL_FLUSH_PORT_AND_STATIC 1003 - -static a_bool_t -horus_fdb_is_zeroaddr(fal_mac_addr_t addr) -{ - a_uint32_t i; - - for (i = 0; i < 6; i++) - { - if (addr.uc[i]) - { - return A_FALSE; - } - } - - return A_TRUE; -} - -static void -horus_fdb_fill_addr(fal_mac_addr_t addr, a_uint32_t * reg0, a_uint32_t * reg1) -{ - SW_SET_REG_BY_FIELD(ADDR_TABLE_FUNC1, AT_ADDR_BYTE0, addr.uc[0], *reg1); - SW_SET_REG_BY_FIELD(ADDR_TABLE_FUNC1, AT_ADDR_BYTE1, addr.uc[1], *reg1); - SW_SET_REG_BY_FIELD(ADDR_TABLE_FUNC1, AT_ADDR_BYTE2, addr.uc[2], *reg1); - SW_SET_REG_BY_FIELD(ADDR_TABLE_FUNC1, AT_ADDR_BYTE3, addr.uc[3], *reg1); - - SW_SET_REG_BY_FIELD(ADDR_TABLE_FUNC0, AT_ADDR_BYTE4, addr.uc[4], *reg0); - SW_SET_REG_BY_FIELD(ADDR_TABLE_FUNC0, AT_ADDR_BYTE5, addr.uc[5], *reg0); - - return; -} - -static sw_error_t -horus_atu_sw_to_hw(a_uint32_t dev_id, const fal_fdb_entry_t * entry, - a_uint32_t reg[]) -{ - a_uint32_t port; - - if (A_FALSE == entry->portmap_en) - { - if (A_TRUE != - hsl_port_prop_check(dev_id, entry->port.id, HSL_PP_INCL_CPU)) - { - return SW_BAD_PARAM; - } - - port = 0x1UL << entry->port.id; - } - else - { - if (A_FALSE == - hsl_mports_prop_check(dev_id, entry->port.map, HSL_PP_INCL_CPU)) - { - return SW_BAD_PARAM; - } - - port = entry->port.map; - } - - if (FAL_MAC_CPY_TO_CPU == entry->dacmd) - { - SW_SET_REG_BY_FIELD(ADDR_TABLE_FUNC2, COPY_TO_CPU, 1, reg[2]); - } - else if (FAL_MAC_RDT_TO_CPU == entry->dacmd) - { - SW_SET_REG_BY_FIELD(ADDR_TABLE_FUNC2, REDRCT_TO_CPU, 1, reg[2]); - } - else if (FAL_MAC_FRWRD != entry->dacmd) - { - return SW_NOT_SUPPORTED; - } - - if (FAL_MAC_DROP == entry->sacmd) - { - SW_SET_REG_BY_FIELD(ADDR_TABLE_FUNC2, SA_DROP_EN, 1, reg[2]); - } - else if (FAL_MAC_FRWRD != entry->sacmd) - { - return SW_NOT_SUPPORTED; - } - - if (A_TRUE == entry->leaky_en) - { - SW_SET_REG_BY_FIELD(ADDR_TABLE_FUNC2, LEAKY_EN, 1, reg[2]); - } - else - { - SW_SET_REG_BY_FIELD(ADDR_TABLE_FUNC2, LEAKY_EN, 0, reg[2]); - } - - if (A_TRUE == entry->static_en) - { - SW_SET_REG_BY_FIELD(ADDR_TABLE_FUNC2, AT_STATUS, 15, reg[2]); - } - else - { - SW_SET_REG_BY_FIELD(ADDR_TABLE_FUNC2, AT_STATUS, 7, reg[2]); - } - - if (A_TRUE == entry->mirror_en) - { - SW_SET_REG_BY_FIELD(ADDR_TABLE_FUNC2, MIRROR_EN, 1, reg[2]); - } - - if (A_TRUE == entry->clone_en) - { - SW_SET_REG_BY_FIELD(ADDR_TABLE_FUNC2, CLONE_EN, 1, reg[2]); - } - - if (A_TRUE == entry->cross_pt_state) - { - SW_SET_REG_BY_FIELD(ADDR_TABLE_FUNC2, CROSS_PT, 1, reg[2]); - } - - if (A_TRUE == entry->da_pri_en) - { - hsl_dev_t *p_dev; - - SW_SET_REG_BY_FIELD(ADDR_TABLE_FUNC2, AT_PRI_EN, 1, reg[2]); - - SW_RTN_ON_NULL(p_dev = hsl_dev_ptr_get(dev_id)); - - if (entry->da_queue > (p_dev->nr_queue - 1)) - return SW_BAD_PARAM; - - SW_SET_REG_BY_FIELD(ADDR_TABLE_FUNC2, AT_PRI, entry->da_queue, reg[2]); - } - - SW_SET_REG_BY_FIELD(ADDR_TABLE_FUNC2, DES_PORT, port, reg[2]); - horus_fdb_fill_addr(entry->addr, ®[0], ®[1]); - - return SW_OK; -} - -static void -horus_atu_hw_to_sw(const a_uint32_t reg[], fal_fdb_entry_t * entry) -{ - a_uint32_t i, data; - - aos_mem_zero(entry, sizeof (fal_fdb_entry_t)); - - entry->dacmd = FAL_MAC_FRWRD; - SW_GET_FIELD_BY_REG(ADDR_TABLE_FUNC2, COPY_TO_CPU, data, reg[2]); - if (1 == data) - { - entry->dacmd = FAL_MAC_CPY_TO_CPU; - } - - SW_GET_FIELD_BY_REG(ADDR_TABLE_FUNC2, REDRCT_TO_CPU, data, reg[2]); - if (1 == data) - { - entry->dacmd = FAL_MAC_RDT_TO_CPU; - } - - entry->sacmd = FAL_MAC_FRWRD; - SW_GET_FIELD_BY_REG(ADDR_TABLE_FUNC2, SA_DROP_EN, data, reg[2]); - if (1 == data) - { - entry->sacmd = FAL_MAC_DROP; - } - - entry->leaky_en = A_FALSE; - SW_GET_FIELD_BY_REG(ADDR_TABLE_FUNC2, LEAKY_EN, data, reg[2]); - if (1 == data) - { - entry->leaky_en = A_TRUE; - } - - entry->static_en = A_FALSE; - SW_GET_FIELD_BY_REG(ADDR_TABLE_FUNC2, AT_STATUS, data, reg[2]); - if (0xf == data) - { - entry->static_en = A_TRUE; - } - - entry->mirror_en = A_FALSE; - SW_GET_FIELD_BY_REG(ADDR_TABLE_FUNC2, MIRROR_EN, data, reg[2]); - if (1 == data) - { - entry->mirror_en = A_TRUE; - } - - entry->clone_en = A_FALSE; - SW_GET_FIELD_BY_REG(ADDR_TABLE_FUNC2, CLONE_EN, data, reg[2]); - if (1 == data) - { - entry->clone_en = A_TRUE; - } - - entry->da_pri_en = A_FALSE; - SW_GET_FIELD_BY_REG(ADDR_TABLE_FUNC2, AT_PRI_EN, data, reg[2]); - if (1 == data) - { - SW_GET_FIELD_BY_REG(ADDR_TABLE_FUNC2, AT_PRI, data, reg[2]); - entry->da_pri_en = A_TRUE; - entry->da_queue = data & 0x3; - } - - entry->cross_pt_state = A_FALSE; - SW_GET_FIELD_BY_REG(ADDR_TABLE_FUNC2, CROSS_PT, data, reg[2]); - if (1 == data) - { - entry->cross_pt_state = A_TRUE; - } - - SW_GET_FIELD_BY_REG(ADDR_TABLE_FUNC2, DES_PORT, data, reg[2]); - - entry->portmap_en = A_TRUE; - entry->port.map = data; - - for (i = 0; i < 4; i++) - { - entry->addr.uc[i] = (reg[1] >> ((3 - i) << 3)) & 0xff; - } - - for (i = 4; i < 6; i++) - { - entry->addr.uc[i] = (reg[0] >> ((7 - i) << 3)) & 0xff; - } - - return; -} - -static sw_error_t -horus_fdb_commit(a_uint32_t dev_id, a_uint32_t op) -{ - sw_error_t rv; - a_uint32_t busy = 1; - a_uint32_t full_vio; - a_uint32_t i = 1000; - a_uint32_t entry; - a_uint32_t hwop = op; - - while (busy && --i) - { - HSL_REG_FIELD_GET(rv, dev_id, ADDR_TABLE_FUNC0, 0, AT_BUSY, - (a_uint8_t *) (&busy), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - aos_udelay(5); - } - - if (0 == i) - { - return SW_BUSY; - } - - HSL_REG_ENTRY_GET(rv, dev_id, ADDR_TABLE_FUNC0, 0, - (a_uint8_t *) (&entry), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - - SW_SET_REG_BY_FIELD(ADDR_TABLE_FUNC0, AT_BUSY, 1, entry); - - if (ARL_FLUSH_PORT_AND_STATIC == hwop) - { - hwop = ARL_FLUSH_PORT_UNICAST; - SW_SET_REG_BY_FIELD(ADDR_TABLE_FUNC0, FLUSH_ST_EN, 1, entry); - } - - if (ARL_FLUSH_PORT_NO_STATIC == hwop) - { - hwop = ARL_FLUSH_PORT_UNICAST; - SW_SET_REG_BY_FIELD(ADDR_TABLE_FUNC0, FLUSH_ST_EN, 0, entry); - } - - SW_SET_REG_BY_FIELD(ADDR_TABLE_FUNC0, AT_FUNC, hwop, entry); - - HSL_REG_ENTRY_SET(rv, dev_id, ADDR_TABLE_FUNC0, 0, - (a_uint8_t *) (&entry), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - - busy = 1; - i = 1000; - while (busy && --i) - { - HSL_REG_FIELD_GET(rv, dev_id, ADDR_TABLE_FUNC0, 0, AT_BUSY, - (a_uint8_t *) (&busy), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - aos_udelay(5); - } - - if (0 == i) - { - return SW_FAIL; - } - - HSL_REG_FIELD_GET(rv, dev_id, ADDR_TABLE_FUNC0, 0, AT_FULL_VIO, - (a_uint8_t *) (&full_vio), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - - if (full_vio) - { - /* must clear AT_FULL_VOI bit */ - entry = 0x1000; - HSL_REG_ENTRY_SET(rv, dev_id, ADDR_TABLE_FUNC0, 0, - (a_uint8_t *) (&entry), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - - if (ARL_LOAD_ENTRY == hwop) - { - return SW_FULL; - } - else if ((ARL_PURGE_ENTRY == hwop) - || (ARL_FLUSH_PORT_UNICAST == hwop)) - { - return SW_NOT_FOUND; - } - else - { - return SW_FAIL; - } - } - - return SW_OK; -} - -static sw_error_t -horus_atu_get(a_uint32_t dev_id, fal_fdb_entry_t * entry, a_uint32_t op) -{ - sw_error_t rv; - a_uint32_t reg[3] = { 0 }; - a_uint32_t status = 0; - a_uint32_t hwop = op; - - if ((ARL_NEXT_ENTRY == op) - || (ARL_FIND_ENTRY == op)) - { - horus_fdb_fill_addr(entry->addr, ®[0], ®[1]); - } - - HSL_REG_ENTRY_SET(rv, dev_id, ADDR_TABLE_FUNC0, 0, - (a_uint8_t *) (®[0]), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - - HSL_REG_ENTRY_SET(rv, dev_id, ADDR_TABLE_FUNC1, 0, - (a_uint8_t *) (®[1]), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - - /* set status not zero */ - if (ARL_NEXT_ENTRY == op) - { - reg[2] = 0xf0000; - } - - if (ARL_FIRST_ENTRY == op) - { - hwop = ARL_NEXT_ENTRY; - } - - HSL_REG_ENTRY_SET(rv, dev_id, ADDR_TABLE_FUNC2, 0, - (a_uint8_t *) (®[2]), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - - rv = horus_fdb_commit(dev_id, hwop); - SW_RTN_ON_ERROR(rv); - - /* get hardware enrety */ - HSL_REG_ENTRY_GET(rv, dev_id, ADDR_TABLE_FUNC0, 0, - (a_uint8_t *) (®[0]), sizeof (a_uint32_t)); - - SW_RTN_ON_ERROR(rv); - - HSL_REG_ENTRY_GET(rv, dev_id, ADDR_TABLE_FUNC1, 0, - (a_uint8_t *) (®[1]), sizeof (a_uint32_t)); - - SW_RTN_ON_ERROR(rv); - - HSL_REG_ENTRY_GET(rv, dev_id, ADDR_TABLE_FUNC2, 0, - (a_uint8_t *) (®[2]), sizeof (a_uint32_t)); - - SW_RTN_ON_ERROR(rv); - - SW_GET_FIELD_BY_REG(ADDR_TABLE_FUNC2, AT_STATUS, status, reg[2]); - - horus_atu_hw_to_sw(reg, entry); - - /* If hardware return back with address and status all zero, - that means no other next valid entry in fdb table */ - if ((A_TRUE == horus_fdb_is_zeroaddr(entry->addr)) - && (0 == status)) - { - if (ARL_NEXT_ENTRY == op) - { - return SW_NO_MORE; - } - else if ((ARL_FIND_ENTRY == op) - || (ARL_FIRST_ENTRY == op)) - { - return SW_NOT_FOUND; - } - else - { - return SW_FAIL; - } - } - else - { - return SW_OK; - } -} - -static sw_error_t -_horus_fdb_add(a_uint32_t dev_id, const fal_fdb_entry_t * entry) -{ - sw_error_t rv; - a_uint32_t reg[3] = { 0, 0, 0 }; - - HSL_DEV_ID_CHECK(dev_id); - - rv = horus_atu_sw_to_hw(dev_id, entry, reg); - SW_RTN_ON_ERROR(rv); - - HSL_REG_ENTRY_SET(rv, dev_id, ADDR_TABLE_FUNC2, 0, - (a_uint8_t *) (®[2]), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - - HSL_REG_ENTRY_SET(rv, dev_id, ADDR_TABLE_FUNC1, 0, (a_uint8_t *) (®[1]), - sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - - HSL_REG_ENTRY_SET(rv, dev_id, ADDR_TABLE_FUNC0, 0, (a_uint8_t *) (®[0]), - sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - - rv = horus_fdb_commit(dev_id, ARL_LOAD_ENTRY); - - return rv; -} - -static sw_error_t -_horus_fdb_del_all(a_uint32_t dev_id, a_uint32_t flag) -{ - sw_error_t rv; - - HSL_DEV_ID_CHECK(dev_id); - - if (FAL_FDB_DEL_STATIC & flag) - { - rv = horus_fdb_commit(dev_id, ARL_FLUSH_ALL); - } - else - { - rv = horus_fdb_commit(dev_id, ARL_FLUSH_ALL_UNLOCK); - } - - return rv; -} - -static sw_error_t -_horus_fdb_del_by_port(a_uint32_t dev_id, fal_port_t port_id, a_uint32_t flag) -{ - sw_error_t rv; - a_uint32_t reg = 0; - - HSL_DEV_ID_CHECK(dev_id); - - if (A_FALSE == hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU)) - { - return SW_BAD_PARAM; - } - - SW_SET_REG_BY_FIELD(ADDR_TABLE_FUNC0, AT_PORT_NUM, port_id, reg); - - HSL_REG_ENTRY_SET(rv, dev_id, ADDR_TABLE_FUNC0, 0, (a_uint8_t *) (®), - sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - - if (FAL_FDB_DEL_STATIC & flag) - { - rv = horus_fdb_commit(dev_id, ARL_FLUSH_PORT_AND_STATIC); - } - else - { - rv = horus_fdb_commit(dev_id, ARL_FLUSH_PORT_NO_STATIC); - } - - return rv; -} - -static sw_error_t -_horus_fdb_del_by_mac(a_uint32_t dev_id, const fal_fdb_entry_t * entry) -{ - sw_error_t rv; - a_uint32_t reg0 = 0, reg1 = 0; - - HSL_DEV_ID_CHECK(dev_id); - - horus_fdb_fill_addr(entry->addr, ®0, ®1); - - HSL_REG_ENTRY_SET(rv, dev_id, ADDR_TABLE_FUNC1, 0, (a_uint8_t *) (®1), - sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - - HSL_REG_ENTRY_SET(rv, dev_id, ADDR_TABLE_FUNC0, 0, (a_uint8_t *) (®0), - sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - - rv = horus_fdb_commit(dev_id, ARL_PURGE_ENTRY); - return rv; -} - -static sw_error_t -_horus_fdb_next(a_uint32_t dev_id, fal_fdb_entry_t * entry) -{ - sw_error_t rv; - - HSL_DEV_ID_CHECK(dev_id); - - rv = horus_atu_get(dev_id, entry, ARL_NEXT_ENTRY); - return rv; -} - -static sw_error_t -_horus_fdb_first(a_uint32_t dev_id, fal_fdb_entry_t * entry) -{ - sw_error_t rv; - - HSL_DEV_ID_CHECK(dev_id); - - rv = horus_atu_get(dev_id, entry, ARL_FIRST_ENTRY); - return rv; -} - -static sw_error_t -_horus_fdb_find(a_uint32_t dev_id, fal_fdb_entry_t * entry) -{ - sw_error_t rv; - - HSL_DEV_ID_CHECK(dev_id); - - rv = horus_atu_get(dev_id, entry, ARL_FIND_ENTRY); - return rv; -} - -static sw_error_t -_horus_fdb_port_learn_set(a_uint32_t dev_id, fal_port_t port_id, - a_bool_t enable) -{ - a_uint32_t data; - sw_error_t rv; - - HSL_DEV_ID_CHECK(dev_id); - - if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU)) - { - return SW_BAD_PARAM; - } - - if (A_TRUE == enable) - { - data = 1; - } - else if (A_FALSE == enable) - { - data = 0; - } - else - { - return SW_BAD_PARAM; - } - - HSL_REG_FIELD_SET(rv, dev_id, PORT_CTL, port_id, LEARN_EN, - (a_uint8_t *) (&data), sizeof (a_uint32_t)); - return rv; -} - -static sw_error_t -_horus_fdb_port_learn_get(a_uint32_t dev_id, fal_port_t port_id, - a_bool_t *enable) -{ - a_uint32_t data; - sw_error_t rv; - - HSL_DEV_ID_CHECK(dev_id); - - if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU)) - { - return SW_BAD_PARAM; - } - - HSL_REG_FIELD_GET(rv, dev_id, PORT_CTL, port_id, LEARN_EN, - (a_uint8_t *) (&data), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - - if (1 == data) - { - *enable = A_TRUE; - } - else - { - *enable = A_FALSE; - } - - return SW_OK; -} - -static sw_error_t -_horus_fdb_age_ctrl_set(a_uint32_t dev_id, a_bool_t enable) -{ - a_uint32_t data; - sw_error_t rv; - - HSL_DEV_ID_CHECK(dev_id); - - if (A_TRUE == enable) - { - data = 1; - } - else if (A_FALSE == enable) - { - data = 0; - } - else - { - return SW_BAD_PARAM; - } - - HSL_REG_FIELD_SET(rv, dev_id, ADDR_TABLE_CTL, 0, AGE_EN, - (a_uint8_t *) (&data), sizeof (a_uint32_t)); - return rv; -} - -static sw_error_t -_horus_fdb_age_ctrl_get(a_uint32_t dev_id, a_bool_t *enable) -{ - a_uint32_t data; - sw_error_t rv; - - HSL_DEV_ID_CHECK(dev_id); - - HSL_REG_FIELD_GET(rv, dev_id, ADDR_TABLE_CTL, 0, AGE_EN, - (a_uint8_t *) (&data), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - - if (1 == data) - { - *enable = A_TRUE; - } - else - { - *enable = A_FALSE; - } - - return SW_OK; -} - -static sw_error_t -_horus_fdb_age_time_set(a_uint32_t dev_id, a_uint32_t * time) -{ - a_uint32_t data; - sw_error_t rv; - - HSL_DEV_ID_CHECK(dev_id); - - if ((65535 * 7 < *time) || (7 > *time)) - { - return SW_BAD_PARAM; - } - data = *time / 7; - *time = data * 7; - HSL_REG_FIELD_SET(rv, dev_id, ADDR_TABLE_CTL, 0, AGE_TIME, - (a_uint8_t *) (&data), sizeof (a_uint32_t)); - return rv; -} - -static sw_error_t -_horus_fdb_age_time_get(a_uint32_t dev_id, a_uint32_t *time) -{ - a_uint32_t data; - sw_error_t rv; - - HSL_DEV_ID_CHECK(dev_id); - - HSL_REG_FIELD_GET(rv, dev_id, ADDR_TABLE_CTL, 0, AGE_TIME, - (a_uint8_t *) (&data), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - - *time = data * 7; - return SW_OK; -} - -/** - * @brief Add a Fdb entry - * @param[in] dev_id device id - * @param[in] entry fdb entry - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -horus_fdb_add(a_uint32_t dev_id, const fal_fdb_entry_t * entry) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _horus_fdb_add(dev_id, entry); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Delete all Fdb entries - * @details Comments: - * If set FAL_FDB_DEL_STATIC bit in flag which means delete all fdb - * entries otherwise only delete dynamic entries. - * @param[in] dev_id device id - * @param[in] flag delete operation option - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -horus_fdb_del_all(a_uint32_t dev_id, a_uint32_t flag) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _horus_fdb_del_all(dev_id, flag); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Delete Fdb entries on a particular port - * @details Comments: - * If set FAL_FDB_DEL_STATIC bit in flag which means delete all fdb - * entries otherwise only delete dynamic entries. - * @param[in] dev_id device id - * @param[in] port_id port id - * @param[in] flag delete operation option - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -horus_fdb_del_by_port(a_uint32_t dev_id, fal_port_t port_id, a_uint32_t flag) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _horus_fdb_del_by_port(dev_id, port_id, flag); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Delete a particular Fdb entry through mac address - * @details Comments: - * Only addr field in entry is meaning. For IVL learning vid or fid field - * also is meaning. - * @param[in] dev_id device id - * @param[in] entry fdb entry - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -horus_fdb_del_by_mac(a_uint32_t dev_id, const fal_fdb_entry_t * entry) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _horus_fdb_del_by_mac(dev_id, entry); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Get next Fdb entry from particular device - * @details Comments: - * For input parameter only addr field in entry is meaning. - * @param[in] dev_id device id - * @param entry fdb entry - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -horus_fdb_next(a_uint32_t dev_id, fal_fdb_entry_t * entry) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _horus_fdb_next(dev_id, entry); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Get first Fdb entry from particular device - * @param[in] dev_id device id - * @param[out] entry fdb entry - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -horus_fdb_first(a_uint32_t dev_id, fal_fdb_entry_t * entry) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _horus_fdb_first(dev_id, entry); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Find a particular Fdb entry from device through mac address. - * @details Comments: - For input parameter only addr field in entry is meaning. - * @param[in] dev_id device id - * @param[in] entry fdb entry - * @param[out] entry fdb entry - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -horus_fdb_find(a_uint32_t dev_id, fal_fdb_entry_t * entry) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _horus_fdb_find(dev_id, entry); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Set dynamic address learning status on a particular port. - * @details Comments: - * This operation will enable or disable dynamic address learning - * feature on a particular port. - * @param[in] dev_id device id - * @param[in] port_id port id - * @param[in] enable enable or disable - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -horus_fdb_port_learn_set(a_uint32_t dev_id, fal_port_t port_id, - a_bool_t enable) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _horus_fdb_port_learn_set(dev_id, port_id, enable); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Get dynamic address learning status on a particular port. - * @param[in] dev_id device id - * @param[in] port_id port id - * @param[out] enable A_TRUE or A_FALSE - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -horus_fdb_port_learn_get(a_uint32_t dev_id, fal_port_t port_id, - a_bool_t *enable) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _horus_fdb_port_learn_get(dev_id, port_id, enable); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Set dynamic address aging status on particular device. - * @details Comments: - * This operation will enable or disable dynamic address aging - * feature on particular device. - * @param[in] dev_id device id - * @param[in] enable enable or disable - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -horus_fdb_age_ctrl_set(a_uint32_t dev_id, a_bool_t enable) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _horus_fdb_age_ctrl_set(dev_id, enable); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Get dynamic address aging status on particular device. - * @param[in] dev_id device id - * @param[in] enable enable or disable - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -horus_fdb_age_ctrl_get(a_uint32_t dev_id, a_bool_t *enable) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _horus_fdb_age_ctrl_get(dev_id, enable); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Set dynamic address aging time on a particular device. - * @details Comments: - * This operation will set dynamic address aging time on a particular device. - * The unit of time is second. Because different device has differnet - * hardware granularity function will return actual time in hardware. - * @param[in] dev_id device id - * @param time aging time - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -horus_fdb_age_time_set(a_uint32_t dev_id, a_uint32_t * time) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _horus_fdb_age_time_set(dev_id, time); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Get dynamic address aging time on a particular device. - * @param[in] dev_id device id - * @param[out] time aging time - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -horus_fdb_age_time_get(a_uint32_t dev_id, a_uint32_t *time) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _horus_fdb_age_time_get(dev_id, time); - HSL_API_UNLOCK; - return rv; -} - -sw_error_t -horus_fdb_init(a_uint32_t dev_id) -{ - HSL_DEV_ID_CHECK(dev_id); - -#ifndef HSL_STANDALONG - { - hsl_api_t *p_api; - - SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id)); - - p_api->fdb_add = horus_fdb_add; - p_api->fdb_del_all = horus_fdb_del_all; - p_api->fdb_del_by_port = horus_fdb_del_by_port; - p_api->fdb_del_by_mac = horus_fdb_del_by_mac; - p_api->fdb_first = horus_fdb_first; - p_api->fdb_next = horus_fdb_next; - p_api->fdb_find = horus_fdb_find; - p_api->port_learn_set = horus_fdb_port_learn_set; - p_api->port_learn_get = horus_fdb_port_learn_get; - p_api->age_ctrl_set = horus_fdb_age_ctrl_set; - p_api->age_ctrl_get = horus_fdb_age_ctrl_get; - p_api->age_time_set = horus_fdb_age_time_set; - p_api->age_time_get = horus_fdb_age_time_get; - } -#endif - - return SW_OK; -} - -/** - * @} - */ diff --git a/feeds/ipq807x/qca-ssdk/src/src/hsl/horus/horus_igmp.c b/feeds/ipq807x/qca-ssdk/src/src/hsl/horus/horus_igmp.c deleted file mode 100755 index 4f42ed2d8..000000000 --- a/feeds/ipq807x/qca-ssdk/src/src/hsl/horus/horus_igmp.c +++ /dev/null @@ -1,979 +0,0 @@ -/* - * Copyright (c) 2012, The Linux Foundation. All rights reserved. - * Permission to use, copy, modify, and/or distribute this software for - * any purpose with or without fee is hereby granted, provided that the - * above copyright notice and this permission notice appear in all copies. - * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES - * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR - * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES - * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN - * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT - * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. - */ - - -/** - * @defgroup horus_igmp HORUS_IGMP - * @{ - */ -#include "sw.h" -#include "hsl.h" -#include "hsl_dev.h" -#include "hsl_port_prop.h" -#include "horus_igmp.h" -#include "horus_reg.h" - -static sw_error_t -_horus_port_igmps_status_set(a_uint32_t dev_id, fal_port_t port_id, a_bool_t enable) -{ - sw_error_t rv; - a_uint32_t val; - - HSL_DEV_ID_CHECK(dev_id); - - if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_EXCL_CPU)) - { - return SW_BAD_PARAM; - } - - if (A_TRUE == enable) - { - val = 1; - } - else if (A_FALSE == enable) - { - val = 0; - } - else - { - return SW_BAD_PARAM; - } - - HSL_REG_FIELD_SET(rv, dev_id, PORT_CTL, port_id, IGMP_MLD_EN, - (a_uint8_t *) (&val), sizeof (a_uint32_t)); - return rv; -} - -static sw_error_t -_horus_port_igmps_status_get(a_uint32_t dev_id, fal_port_t port_id, a_bool_t *enable) -{ - sw_error_t rv; - a_uint32_t val; - - HSL_DEV_ID_CHECK(dev_id); - - if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_EXCL_CPU)) - { - return SW_BAD_PARAM; - } - - HSL_REG_FIELD_GET(rv, dev_id, PORT_CTL, port_id, IGMP_MLD_EN, - (a_uint8_t *) (&val), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - - if (1 == val) - { - *enable = A_TRUE; - } - else - { - *enable = A_FALSE; - } - - return SW_OK; -} - -static sw_error_t -_horus_igmp_mld_cmd_set(a_uint32_t dev_id, fal_fwd_cmd_t cmd) -{ - sw_error_t rv; - a_uint32_t val; - - HSL_DEV_ID_CHECK(dev_id); - - if (FAL_MAC_CPY_TO_CPU == cmd) - { - val = 1; - } - else if (FAL_MAC_RDT_TO_CPU == cmd) - { - val = 0; - } - else - { - return SW_NOT_SUPPORTED; - } - - HSL_REG_FIELD_SET(rv, dev_id, QM_CTL, 0, IGMP_COPY_EN, - (a_uint8_t *) (&val), sizeof (a_uint32_t)); - return rv; -} - -static sw_error_t -_horus_igmp_mld_cmd_get(a_uint32_t dev_id, fal_fwd_cmd_t * cmd) -{ - sw_error_t rv; - a_uint32_t val; - - HSL_DEV_ID_CHECK(dev_id); - - HSL_REG_FIELD_GET(rv, dev_id, QM_CTL, 0, IGMP_COPY_EN, - (a_uint8_t *) (&val), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - - if (1 == val) - { - *cmd = FAL_MAC_CPY_TO_CPU; - } - else - { - *cmd = FAL_MAC_RDT_TO_CPU; - } - - return SW_OK; -} - -static sw_error_t -_horus_port_igmp_mld_join_set(a_uint32_t dev_id, fal_port_t port_id, a_bool_t enable) -{ - sw_error_t rv; - a_uint32_t val; - - HSL_DEV_ID_CHECK(dev_id); - - if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_EXCL_CPU)) - { - return SW_BAD_PARAM; - } - - if (A_TRUE == enable) - { - val = 1; - } - else if (A_FALSE == enable) - { - val = 0; - } - else - { - return SW_BAD_PARAM; - } - - HSL_REG_FIELD_SET(rv, dev_id, PORT_CTL, port_id, JOIN_EN, - (a_uint8_t *) (&val), sizeof (a_uint32_t)); - return rv; -} - -static sw_error_t -_horus_port_igmp_mld_join_get(a_uint32_t dev_id, fal_port_t port_id, a_bool_t * enable) -{ - sw_error_t rv; - a_uint32_t val; - - HSL_DEV_ID_CHECK(dev_id); - - if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_EXCL_CPU)) - { - return SW_BAD_PARAM; - } - - HSL_REG_FIELD_GET(rv, dev_id, PORT_CTL, port_id, JOIN_EN, - (a_uint8_t *) (&val), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - - if (val) - { - *enable = A_TRUE; - } - else - { - *enable = A_FALSE; - } - - return SW_OK; -} - -static sw_error_t -_horus_port_igmp_mld_leave_set(a_uint32_t dev_id, fal_port_t port_id, a_bool_t enable) -{ - sw_error_t rv; - a_uint32_t val; - - HSL_DEV_ID_CHECK(dev_id); - - if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_EXCL_CPU)) - { - return SW_BAD_PARAM; - } - - if (A_TRUE == enable) - { - val = 1; - } - else if (A_FALSE == enable) - { - val = 0; - } - else - { - return SW_BAD_PARAM; - } - - HSL_REG_FIELD_SET(rv, dev_id, PORT_CTL, port_id, LEAVE_EN, - (a_uint8_t *) (&val), sizeof (a_uint32_t)); - return rv; -} - -static sw_error_t -_horus_port_igmp_mld_leave_get(a_uint32_t dev_id, fal_port_t port_id, a_bool_t * enable) -{ - sw_error_t rv; - a_uint32_t val; - - HSL_DEV_ID_CHECK(dev_id); - - if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_EXCL_CPU)) - { - return SW_BAD_PARAM; - } - - HSL_REG_FIELD_GET(rv, dev_id, PORT_CTL, port_id, LEAVE_EN, - (a_uint8_t *) (&val), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - - if (val) - { - *enable = A_TRUE; - } - else - { - *enable = A_FALSE; - } - - return SW_OK; -} - -static sw_error_t -_horus_igmp_mld_rp_set(a_uint32_t dev_id, fal_pbmp_t pts) -{ - sw_error_t rv; - a_uint32_t val; - - HSL_DEV_ID_CHECK(dev_id); - - if (A_FALSE == hsl_mports_validity_check(dev_id, pts)) - { - return SW_BAD_PARAM; - } - val = pts; - HSL_REG_FIELD_SET(rv, dev_id, FLOOD_MASK, 0, IGMP_DP, - (a_uint8_t *) (&val), sizeof (a_uint32_t)); - return rv; -} - -static sw_error_t -_horus_igmp_mld_rp_get(a_uint32_t dev_id, fal_pbmp_t * pts) -{ - sw_error_t rv; - a_uint32_t val; - - HSL_DEV_ID_CHECK(dev_id); - - HSL_REG_FIELD_GET(rv, dev_id, FLOOD_MASK, 0, IGMP_DP, - (a_uint8_t *) (&val), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - - *pts = val; - return SW_OK; -} - -static sw_error_t -_horus_igmp_mld_entry_creat_set(a_uint32_t dev_id, a_bool_t enable) -{ - sw_error_t rv; - a_uint32_t val; - - HSL_DEV_ID_CHECK(dev_id); - - if (A_TRUE == enable) - { - val = 1; - } - else if (A_FALSE == enable) - { - val = 0; - } - else - { - return SW_BAD_PARAM; - } - - HSL_REG_FIELD_SET(rv, dev_id, QM_CTL, 0, IGMP_CREAT_EN, - (a_uint8_t *) (&val), sizeof (a_uint32_t)); - return rv; -} - -static sw_error_t -_horus_igmp_mld_entry_creat_get(a_uint32_t dev_id, a_bool_t * enable) -{ - sw_error_t rv; - a_uint32_t val; - - HSL_DEV_ID_CHECK(dev_id); - - HSL_REG_FIELD_GET(rv, dev_id, QM_CTL, 0, IGMP_CREAT_EN, - (a_uint8_t *) (&val), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - - if (val) - { - *enable = A_TRUE; - } - else - { - *enable = A_FALSE; - } - - return SW_OK; -} - -static sw_error_t -_horus_igmp_mld_entry_static_set(a_uint32_t dev_id, a_bool_t enable) -{ - sw_error_t rv; - a_uint32_t val; - - HSL_DEV_ID_CHECK(dev_id); - - if (A_TRUE == enable) - { - val = 0xf; - } - else if (A_FALSE == enable) - { - val = 0xe; - } - else - { - return SW_BAD_PARAM; - } - - HSL_REG_FIELD_SET(rv, dev_id, QM_CTL, 0, IGMP_JOIN_STATIC, - (a_uint8_t *) (&val), sizeof (a_uint32_t)); - return rv; -} - -static sw_error_t -_horus_igmp_mld_entry_static_get(a_uint32_t dev_id, a_bool_t * enable) -{ - sw_error_t rv; - a_uint32_t val; - - HSL_DEV_ID_CHECK(dev_id); - - HSL_REG_FIELD_GET(rv, dev_id, QM_CTL, 0, IGMP_JOIN_STATIC, - (a_uint8_t *) (&val), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - - if (0xf == val) - { - *enable = A_TRUE; - } - else - { - *enable = A_FALSE; - } - - return SW_OK; -} - -static sw_error_t -_horus_igmp_mld_entry_leaky_set(a_uint32_t dev_id, a_bool_t enable) -{ - sw_error_t rv; - a_uint32_t val; - - HSL_DEV_ID_CHECK(dev_id); - - if (A_TRUE == enable) - { - val = 1; - } - else if (A_FALSE == enable) - { - val = 0; - } - else - { - return SW_BAD_PARAM; - } - - HSL_REG_FIELD_SET(rv, dev_id, QM_CTL, 0, IGMP_JOIN_LEAKY, - (a_uint8_t *) (&val), sizeof (a_uint32_t)); - return rv; -} - -static sw_error_t -_horus_igmp_mld_entry_leaky_get(a_uint32_t dev_id, a_bool_t * enable) -{ - sw_error_t rv; - a_uint32_t val; - - HSL_DEV_ID_CHECK(dev_id); - - HSL_REG_FIELD_GET(rv, dev_id, QM_CTL, 0, IGMP_JOIN_LEAKY, - (a_uint8_t *) (&val), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - - if (val) - { - *enable = A_TRUE; - } - else - { - *enable = A_FALSE; - } - - return SW_OK; -} - -static sw_error_t -_horus_igmp_mld_entry_v3_set(a_uint32_t dev_id, a_bool_t enable) -{ - sw_error_t rv; - a_uint32_t val; - - HSL_DEV_ID_CHECK(dev_id); - - if (A_TRUE == enable) - { - val = 1; - } - else if (A_FALSE == enable) - { - val = 0; - } - else - { - return SW_BAD_PARAM; - } - - HSL_REG_FIELD_SET(rv, dev_id, QM_CTL, 0, IGMP_V3_EN, - (a_uint8_t *) (&val), sizeof (a_uint32_t)); - return rv; -} - -static sw_error_t -_horus_igmp_mld_entry_v3_get(a_uint32_t dev_id, a_bool_t * enable) -{ - sw_error_t rv; - a_uint32_t val; - - HSL_DEV_ID_CHECK(dev_id); - - HSL_REG_FIELD_GET(rv, dev_id, QM_CTL, 0, IGMP_V3_EN, - (a_uint8_t *) (&val), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - - if (val) - { - *enable = A_TRUE; - } - else - { - *enable = A_FALSE; - } - - return SW_OK; -} - -static sw_error_t -_horus_igmp_mld_entry_queue_set(a_uint32_t dev_id, a_bool_t enable, a_uint32_t queue) -{ - sw_error_t rv; - a_uint32_t entry; - hsl_dev_t *p_dev; - - HSL_DEV_ID_CHECK(dev_id); - - HSL_REG_ENTRY_GET(rv, dev_id, QM_CTL, 0, - (a_uint8_t *) (&entry), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - - if (A_TRUE == enable) - { - SW_SET_REG_BY_FIELD(QM_CTL, IGMP_PRI_EN, 1, entry); - SW_RTN_ON_NULL(p_dev = hsl_dev_ptr_get(dev_id)); - if (queue >= p_dev->nr_queue) - { - return SW_BAD_PARAM; - } - SW_SET_REG_BY_FIELD(QM_CTL, IGMP_PRI, queue, entry); - } - else if (A_FALSE == enable) - { - SW_SET_REG_BY_FIELD(QM_CTL, IGMP_PRI_EN, 0, entry); - SW_SET_REG_BY_FIELD(QM_CTL, IGMP_PRI, 0, entry); - } - else - { - return SW_BAD_PARAM; - } - - HSL_REG_ENTRY_SET(rv, dev_id, QM_CTL, 0, - (a_uint8_t *) (&entry), sizeof (a_uint32_t)); - return rv; -} - -static sw_error_t -_horus_igmp_mld_entry_queue_get(a_uint32_t dev_id, a_bool_t * enable, a_uint32_t * queue) -{ - sw_error_t rv; - a_uint32_t entry, data; - - HSL_DEV_ID_CHECK(dev_id); - - HSL_REG_ENTRY_GET(rv, dev_id, QM_CTL, 0, - (a_uint8_t *) (&entry), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - - SW_GET_FIELD_BY_REG(QM_CTL, IGMP_PRI_EN, data, entry); - if (data) - { - *enable = A_TRUE; - SW_GET_FIELD_BY_REG(QM_CTL, IGMP_PRI, data, entry); - *queue = data; - } - else - { - *enable = A_FALSE; - *queue = 0; - } - - return SW_OK; -} - -/** - * @brief Set igmp/mld packets snooping status on a particular port. - * @details Comments: - * After enabling igmp/mld snooping feature on a particular port all kinds - * igmp/mld packets received on this port would be acknowledged by hardware. - * Particular forwarding decision could be setted by fal_igmp_mld_cmd_set. - * @param[in] dev_id device id - * @param[in] port_id port id - * @param[in] enable A_TRUE or A_FALSE - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -horus_port_igmps_status_set(a_uint32_t dev_id, fal_port_t port_id, a_bool_t enable) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _horus_port_igmps_status_set(dev_id, port_id, enable); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Get igmp/mld packets snooping status on particular port. - * @param[in] dev_id device id - * @param[in] port_id port id - * @param[out] enable A_TRUE or A_FALSE - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -horus_port_igmps_status_get(a_uint32_t dev_id, fal_port_t port_id, a_bool_t *enable) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _horus_port_igmps_status_get(dev_id, port_id, enable); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Set igmp/mld packets forwarding command on a particular device. - * @details Comments: - * Particular device may only support parts of forwarding commands. - * This operation will take effect only after enabling igmp/mld snooping - * @param[in] dev_id device id - * @param[in] cmd forwarding command - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -horus_igmp_mld_cmd_set(a_uint32_t dev_id, fal_fwd_cmd_t cmd) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _horus_igmp_mld_cmd_set(dev_id, cmd); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Get igmp/mld packets forwarding command on a particular device. - * @param[in] dev_id device id - * @param[out] cmd forwarding command - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -horus_igmp_mld_cmd_get(a_uint32_t dev_id, fal_fwd_cmd_t * cmd) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _horus_igmp_mld_cmd_get(dev_id, cmd); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Set igmp/mld join packets hardware acknowledgement status on particular port. - * @details Comments: - * After enabling igmp/mld join feature on a particular port hardware will - * dynamic learning or changing multicast entry. - * @param[in] dev_id device id - * @param[in] port_id port id - * @param[in] enable A_TRUE or A_FALSE - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -horus_port_igmp_mld_join_set(a_uint32_t dev_id, fal_port_t port_id, a_bool_t enable) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _horus_port_igmp_mld_join_set(dev_id, port_id, enable); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Get igmp/mld join packets hardware acknowledgement status on a particular port. - * @param[in] dev_id device id - * @param[in] port_id port id - * @param[out] enable A_TRUE or A_FALSE - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -horus_port_igmp_mld_join_get(a_uint32_t dev_id, fal_port_t port_id, a_bool_t * enable) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _horus_port_igmp_mld_join_get(dev_id, port_id, enable); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Set igmp/mld leave packets hardware acknowledgement status on a particular port. - * @details Comments: - * After enabling igmp leave feature on a particular port hardware will dynamic - * deleting or changing multicast entry. - * @param[in] dev_id device id - * @param[in] port_id port id - * @param[in] enable A_TRUE or A_FALSE - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -horus_port_igmp_mld_leave_set(a_uint32_t dev_id, fal_port_t port_id, a_bool_t enable) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _horus_port_igmp_mld_leave_set(dev_id, port_id, enable); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Get igmp/mld leave packets hardware acknowledgement status on a particular port. - * @param[in] dev_id device id - * @param[in] port_id port id - * @param[out] enable A_TRUE or A_FALSE - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -horus_port_igmp_mld_leave_get(a_uint32_t dev_id, fal_port_t port_id, a_bool_t * enable) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _horus_port_igmp_mld_leave_get(dev_id, port_id, enable); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Set igmp/mld router ports on a particular device. - * @details Comments: - * After enabling igmp/mld join/leave feature on a particular port igmp/mld - * join/leave packets received on this port will be forwarded to router ports. - * @param[in] dev_id device id - * @param[in] pts dedicates ports - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -horus_igmp_mld_rp_set(a_uint32_t dev_id, fal_pbmp_t pts) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _horus_igmp_mld_rp_set(dev_id, pts); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Get igmp/mld router ports on a particular device. - * @param[in] dev_id device id - * @param[out] pts dedicates ports - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -horus_igmp_mld_rp_get(a_uint32_t dev_id, fal_pbmp_t * pts) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _horus_igmp_mld_rp_get(dev_id, pts); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Set the status of creating multicast entry during igmp/mld join/leave procedure. - * @details Comments: - * After enabling igmp/mld join/leave feature on a particular port if enable - * entry creat hardware will dynamic creat and delete multicast entry, - * otherwise hardware only can change destination ports of existing muticast entry. - * @param[in] dev_id device id - * @param[in] enable A_TRUE or A_FALSE - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -horus_igmp_mld_entry_creat_set(a_uint32_t dev_id, a_bool_t enable) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _horus_igmp_mld_entry_creat_set(dev_id, enable); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Get the status of creating multicast entry during igmp/mld join/leave procedure. - * @param[in] dev_id device id - * @param[out] enable A_TRUE or A_FALSE - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -horus_igmp_mld_entry_creat_get(a_uint32_t dev_id, a_bool_t * enable) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _horus_igmp_mld_entry_creat_get(dev_id, enable); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Set the static status of multicast entry which learned by hardware. - * @details Comments: - * After enabling igmp/mld join/leave feature on a particular port if enable - * static status hardware will not age out multicast entry which leardned by hardware, - * otherwise hardware will age out multicast entry which leardned by hardware. - * @param[in] dev_id device id - * @param[in] enable A_TRUE or A_FALSE - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -horus_igmp_mld_entry_static_set(a_uint32_t dev_id, a_bool_t enable) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _horus_igmp_mld_entry_static_set(dev_id, enable); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Get the static status of multicast entry which learned by hardware. - * @param[in] dev_id device id - * @param[out] enable A_TRUE or A_FALSE - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -horus_igmp_mld_entry_static_get(a_uint32_t dev_id, a_bool_t * enable) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _horus_igmp_mld_entry_static_get(dev_id, enable); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Set the leaky status of multicast entry which learned by hardware. - * @details Comments: - * After enabling igmp/mld join/leave feature on a particular port if enable - * leaky status hardware will set leaky flag of multicast entry which leardned by hardware, - * otherwise hardware will not set leaky flag of multicast entry which leardned by hardware. - * @param[in] dev_id device id - * @param[in] enable A_TRUE or A_FALSE - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -horus_igmp_mld_entry_leaky_set(a_uint32_t dev_id, a_bool_t enable) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _horus_igmp_mld_entry_leaky_set(dev_id, enable); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Get the leaky status of multicast entry which learned by hardware. - * @param[in] dev_id device id - * @param[out] enable A_TRUE or A_FALSE - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -horus_igmp_mld_entry_leaky_get(a_uint32_t dev_id, a_bool_t * enable) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _horus_igmp_mld_entry_leaky_get(dev_id, enable); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Set igmpv3/mldv2 packets hardware acknowledgement status on a particular device. - * @details Comments: - * After enabling igmp join/leave feature on a particular port hardware will dynamic - * creating or changing multicast entry after receiving igmpv3/mldv2 packets. - * @param[in] dev_id device id - * @param[in] enable A_TRUE or A_FALSE - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -horus_igmp_mld_entry_v3_set(a_uint32_t dev_id, a_bool_t enable) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _horus_igmp_mld_entry_v3_set(dev_id, enable); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Get igmpv3/mldv2 packets hardware acknowledgement status on a particular device. - * @param[in] dev_id device id - * @param[out] enable A_TRUE or A_FALSE - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -horus_igmp_mld_entry_v3_get(a_uint32_t dev_id, a_bool_t * enable) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _horus_igmp_mld_entry_v3_get(dev_id, enable); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Set the queue status of multicast entry which learned by hardware. - * @details Comments: - * After enabling igmp/mld join/leave feature on a particular port if enable - * leaky status hardware will set queue flag of multicast entry which leardned by hardware, - * otherwise hardware will not set queue flag of multicast entry which leardned by hardware. - * @param[in] dev_id device id - * @param[in] enable A_TRUE or A_FALSE - * @param[in] queue queue id - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -horus_igmp_mld_entry_queue_set(a_uint32_t dev_id, a_bool_t enable, a_uint32_t queue) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _horus_igmp_mld_entry_queue_set(dev_id, enable, queue); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Get the queue status of multicast entry which learned by hardware. - * @param[in] dev_id device id - * @param[out] enable A_TRUE or A_FALSE - * @param[out] queue queue id - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -horus_igmp_mld_entry_queue_get(a_uint32_t dev_id, a_bool_t * enable, a_uint32_t * queue) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _horus_igmp_mld_entry_queue_get(dev_id, enable, queue); - HSL_API_UNLOCK; - return rv; -} - -sw_error_t -horus_igmp_init(a_uint32_t dev_id) -{ - HSL_DEV_ID_CHECK(dev_id); - -#ifndef HSL_STANDALONG - { - hsl_api_t *p_api; - - SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id)); - - p_api->port_igmps_status_set = horus_port_igmps_status_set; - p_api->port_igmps_status_get = horus_port_igmps_status_get; - p_api->igmp_mld_cmd_set = horus_igmp_mld_cmd_set; - p_api->igmp_mld_cmd_get = horus_igmp_mld_cmd_get; - p_api->port_igmp_join_set = horus_port_igmp_mld_join_set; - p_api->port_igmp_join_get = horus_port_igmp_mld_join_get; - p_api->port_igmp_leave_set = horus_port_igmp_mld_leave_set; - p_api->port_igmp_leave_get = horus_port_igmp_mld_leave_get; - p_api->igmp_rp_set = horus_igmp_mld_rp_set; - p_api->igmp_rp_get = horus_igmp_mld_rp_get; - p_api->igmp_entry_creat_set = horus_igmp_mld_entry_creat_set; - p_api->igmp_entry_creat_get = horus_igmp_mld_entry_creat_get; - p_api->igmp_entry_static_set = horus_igmp_mld_entry_static_set; - p_api->igmp_entry_static_get = horus_igmp_mld_entry_static_get; - p_api->igmp_entry_leaky_set = horus_igmp_mld_entry_leaky_set; - p_api->igmp_entry_leaky_get = horus_igmp_mld_entry_leaky_get; - p_api->igmp_entry_v3_set = horus_igmp_mld_entry_v3_set; - p_api->igmp_entry_v3_get = horus_igmp_mld_entry_v3_get; - p_api->igmp_entry_queue_set = horus_igmp_mld_entry_queue_set; - p_api->igmp_entry_queue_get = horus_igmp_mld_entry_queue_get; - } -#endif - - return SW_OK; -} - -/** - * @} - */ diff --git a/feeds/ipq807x/qca-ssdk/src/src/hsl/horus/horus_init.c b/feeds/ipq807x/qca-ssdk/src/src/hsl/horus/horus_init.c deleted file mode 100755 index d22fe8667..000000000 --- a/feeds/ipq807x/qca-ssdk/src/src/hsl/horus/horus_init.c +++ /dev/null @@ -1,432 +0,0 @@ -/* - * Copyright (c) 2012, 2017, The Linux Foundation. All rights reserved. - * Permission to use, copy, modify, and/or distribute this software for - * any purpose with or without fee is hereby granted, provided that the - * above copyright notice and this permission notice appear in all copies. - * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES - * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR - * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES - * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN - * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT - * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. - */ - - -/** - * @defgroup horus_init HORUS_INIT - * @{ - */ -#include "sw.h" -#include "hsl.h" -#include "hsl_dev.h" -#include "hsl_port_prop.h" -#include "horus_mib.h" -#include "horus_port_ctrl.h" -#include "horus_portvlan.h" -#include "horus_vlan.h" -#include "horus_fdb.h" -#include "horus_qos.h" -#include "horus_mirror.h" -#include "horus_stp.h" -#include "horus_rate.h" -#include "horus_misc.h" -#include "horus_leaky.h" -#include "horus_igmp.h" -#include "horus_led.h" -#include "horus_reg_access.h" -#include "horus_reg.h" -#include "f2_phy.h" - -static ssdk_init_cfg * horus_cfg[SW_MAX_NR_DEV] = { 0 }; - -#if !(defined(KERNEL_MODULE) && defined(USER_MODE)) -static sw_error_t -horus_portproperty_init(a_uint32_t dev_id, hsl_init_mode mode) -{ - hsl_port_prop_t p_type; - hsl_dev_t *pdev = NULL; - fal_port_t port_id; - - pdev = hsl_dev_ptr_get(dev_id); - if (pdev == NULL) - return SW_NOT_INITIALIZED; - - for (port_id = 0; port_id < pdev->nr_ports; port_id++) - { - hsl_port_prop_portmap_set(dev_id, port_id); - - for (p_type = HSL_PP_PHY; p_type < HSL_PP_BUTT; p_type++) - { - if (HSL_NO_CPU == mode) - { - SW_RTN_ON_ERROR(hsl_port_prop_set(dev_id, port_id, p_type)); - continue; - } - - switch (p_type) - { - case HSL_PP_PHY: - if (HSL_CPU_1 != mode) - { - if ((port_id != pdev->cpu_port_nr) - && (port_id != (pdev->nr_ports -1))) - { - SW_RTN_ON_ERROR(hsl_port_prop_set(dev_id, port_id, p_type)); - } - } - else - { - if (port_id != pdev->cpu_port_nr) - { - SW_RTN_ON_ERROR(hsl_port_prop_set(dev_id, port_id, p_type)); - } - } - break; - - case HSL_PP_INCL_CPU: - /* include cpu port and wan port in some cases */ - if (!((HSL_CPU_2 == mode) && (port_id == (pdev->nr_ports - 1)))) - SW_RTN_ON_ERROR(hsl_port_prop_set(dev_id, port_id, p_type)); - - break; - - case HSL_PP_EXCL_CPU: - /* exclude cpu port and wan port in some cases */ - if ((port_id != pdev->cpu_port_nr) - && (!((HSL_CPU_2 == mode) && (port_id == (pdev->nr_ports - 1))))) - SW_RTN_ON_ERROR(hsl_port_prop_set(dev_id, port_id, p_type)); - break; - - default: - break; - } - } - - if (HSL_NO_CPU == mode) - { - SW_RTN_ON_ERROR(hsl_port_prop_set_phyid - (dev_id, port_id, port_id + 1)); - } - else - { - if (port_id != pdev->cpu_port_nr) - { - SW_RTN_ON_ERROR(hsl_port_prop_set_phyid - (dev_id, port_id, port_id - 1)); - } - } - } - - return SW_OK; -} - -static sw_error_t -horus_hw_init(a_uint32_t dev_id, ssdk_init_cfg *cfg) -{ - hsl_dev_t *pdev = NULL; - a_uint32_t port_id; - a_uint32_t data; - sw_error_t rv; - - pdev = hsl_dev_ptr_get(dev_id); - if (NULL == pdev) - { - return SW_NOT_INITIALIZED; - } - - for (port_id = 0; port_id < pdev->nr_ports; port_id++) - { - if (port_id == pdev->cpu_port_nr) - { - continue; - } - - HSL_REG_ENTRY_GET(rv, dev_id, PORT_STATUS, port_id, - (a_uint8_t *) (&data), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - - SW_SET_REG_BY_FIELD(PORT_STATUS, LINK_EN, 1, data); - - HSL_REG_ENTRY_SET(rv, dev_id, PORT_STATUS, port_id, - (a_uint8_t *) (&data), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - } - - return SW_OK; -} - -static sw_error_t -horus_bist_test(a_uint32_t dev_id) -{ - a_uint32_t entry, data, i; - sw_error_t rv; - - data = 1; - i = 0x1000; - while (data && --i) - { - HSL_REG_ENTRY_GET(rv, dev_id, BIST_CTRL, 0, - (a_uint8_t *) (&entry), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - SW_GET_FIELD_BY_REG(BIST_CTRL, BIST_BUSY, data, entry); - aos_udelay(5); - } - - if (0 == i) - { - return SW_INIT_ERROR; - } - - entry = 0; - SW_SET_REG_BY_FIELD(BIST_CTRL, BIST_BUSY, 1, entry); - SW_SET_REG_BY_FIELD(BIST_CTRL, PTN_EN2, 1, entry); - SW_SET_REG_BY_FIELD(BIST_CTRL, PTN_EN1, 1, entry); - SW_SET_REG_BY_FIELD(BIST_CTRL, PTN_EN0, 1, entry); - - HSL_REG_ENTRY_SET(rv, dev_id, BIST_CTRL, 0, - (a_uint8_t *) (&entry), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - - data = 1; - i = 0x1000; - while (data && --i) - { - HSL_REG_ENTRY_GET(rv, dev_id, BIST_CTRL, 0, - (a_uint8_t *) (&entry), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - SW_GET_FIELD_BY_REG(BIST_CTRL, BIST_BUSY, data, entry); - aos_udelay(5); - } - - if (0 == i) - { - return SW_INIT_ERROR; - } - - SW_GET_FIELD_BY_REG(BIST_CTRL, ERR_CNT, data, entry); - if (data) - { - SW_GET_FIELD_BY_REG(BIST_CTRL, ONE_ERR, data, entry); - if (!data) - { - return SW_INIT_ERROR; - } - - SW_GET_FIELD_BY_REG(BIST_CTRL, ERR_ADDR, data, entry); - - entry = 0; - SW_SET_REG_BY_FIELD(BIST_RCV, RCV_EN, 1, entry); - SW_SET_REG_BY_FIELD(BIST_RCV, RCV_ADDR, data, entry); - HSL_REG_ENTRY_SET(rv, dev_id, BIST_RCV, 0, - (a_uint8_t *) (&entry), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - } - else - { - return SW_OK; - } - - entry = 0; - SW_SET_REG_BY_FIELD(BIST_CTRL, BIST_BUSY, 1, entry); - SW_SET_REG_BY_FIELD(BIST_CTRL, PTN_EN2, 1, entry); - SW_SET_REG_BY_FIELD(BIST_CTRL, PTN_EN1, 1, entry); - SW_SET_REG_BY_FIELD(BIST_CTRL, PTN_EN0, 1, entry); - - HSL_REG_ENTRY_SET(rv, dev_id, BIST_CTRL, 0, - (a_uint8_t *) (&entry), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - - data = 1; - i = 0x1000; - while (data && --i) - { - HSL_REG_ENTRY_GET(rv, dev_id, BIST_CTRL, 0, - (a_uint8_t *) (&entry), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - SW_GET_FIELD_BY_REG(BIST_CTRL, BIST_BUSY, data, entry); - aos_udelay(5); - } - - if (0 == i) - { - return SW_INIT_ERROR; - } - - SW_GET_FIELD_BY_REG(BIST_CTRL, ERR_CNT, data, entry); - if (data) - { - return SW_INIT_ERROR; - } - - return SW_OK; -} -#endif - -static sw_error_t -horus_dev_init(a_uint32_t dev_id, hsl_init_mode cpu_mode) -{ - hsl_dev_t *pdev = NULL; - - pdev = hsl_dev_ptr_get(dev_id); - if (pdev == NULL) - return SW_NOT_INITIALIZED; - - pdev->nr_ports = 6; - pdev->nr_phy = 5; - pdev->cpu_port_nr = 0; - pdev->nr_vlans = 16; - pdev->hw_vlan_query = A_TRUE; - pdev->nr_queue = 4; - pdev->cpu_mode = cpu_mode; - - return SW_OK; -} - -static sw_error_t -_horus_reset(a_uint32_t dev_id) -{ -#if !(defined(KERNEL_MODULE) && defined(USER_MODE)) - sw_error_t rv; - a_uint32_t val; - - HSL_DEV_ID_CHECK(dev_id); - - val = 0x1; - HSL_REG_FIELD_SET(rv, dev_id, MASK_CTL, 0, SOFT_RST, - (a_uint8_t *) (&val), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - - rv = horus_hw_init(dev_id, horus_cfg[dev_id]); - SW_RTN_ON_ERROR(rv); -#endif - - return SW_OK; -} - - -sw_error_t -horus_cleanup(a_uint32_t dev_id) -{ - - if (horus_cfg[dev_id]) - { - aos_mem_free(horus_cfg[dev_id]); - horus_cfg[dev_id] = NULL; - } - - return SW_OK; -} - -/** - * @brief reset hsl layer. - * @details Comments: - * This operation will reset hsl layer - * @param[in] dev_id device id - * @return SW_OK or error code - */ -sw_error_t -horus_reset(a_uint32_t dev_id) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _horus_reset(dev_id); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Init hsl layer. - * @details Comments: - * This operation will init hsl layer and hsl layer - * @param[in] dev_id device id - * @param[in] cfg configuration for initialization - * @return SW_OK or error code - */ -sw_error_t -horus_init(a_uint32_t dev_id, ssdk_init_cfg *cfg) -{ - HSL_DEV_ID_CHECK(dev_id); - - if (NULL == horus_cfg[dev_id]) - { - horus_cfg[dev_id] = aos_mem_alloc(sizeof (ssdk_init_cfg)); - } - - if (NULL == horus_cfg[dev_id]) - { - return SW_OUT_OF_MEM; - } - - aos_mem_copy(horus_cfg[dev_id], cfg, sizeof (ssdk_init_cfg)); - - SW_RTN_ON_ERROR(horus_reg_access_init(dev_id, cfg->reg_mode)); - - SW_RTN_ON_ERROR(horus_dev_init(dev_id, cfg->cpu_mode)); - -#if !(defined(KERNEL_MODULE) && defined(USER_MODE)) - { - a_uint32_t i, entry; - sw_error_t rv; - - SW_RTN_ON_ERROR(horus_bist_test(dev_id)); - - entry = 0x1; - HSL_REG_FIELD_SET(rv, dev_id, MASK_CTL, 0, SOFT_RST, - (a_uint8_t *) (&entry), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - - i = 0x10; - do - { - HSL_REG_FIELD_GET(rv, dev_id, MASK_CTL, 0, SOFT_RST, - (a_uint8_t *) (&entry), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - - aos_mdelay(10); - } - while (entry && --i); - - if (0 == i) - { - return SW_INIT_ERROR; - } - - SW_RTN_ON_ERROR(hsl_port_prop_init(dev_id)); - SW_RTN_ON_ERROR(hsl_port_prop_init_by_dev(dev_id)); - SW_RTN_ON_ERROR(horus_portproperty_init(dev_id, cfg->cpu_mode)); - - HORUS_MIB_INIT(rv, dev_id); - HORUS_PORT_CTRL_INIT(rv, dev_id); - HORUS_PORTVLAN_INIT(rv, dev_id); - HORUS_VLAN_INIT(rv, dev_id); - HORUS_FDB_INIT(rv, dev_id); - HORUS_QOS_INIT(rv, dev_id); - HORUS_STP_INIT(rv, dev_id); - HORUS_MIRR_INIT(rv, dev_id); - HORUS_RATE_INIT(rv, dev_id); - HORUS_MISC_INIT(rv, dev_id); - HORUS_LEAKY_INIT(rv, dev_id); - HORUS_IGMP_INIT(rv, dev_id); - HORUS_LED_INIT(rv, dev_id); - - { - hsl_api_t *p_api; - - SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id)); - p_api->dev_reset = horus_reset; - p_api->dev_clean = horus_cleanup; - } - - SW_RTN_ON_ERROR(horus_hw_init(dev_id, cfg)); - } -#endif - - return SW_OK; -} - - -/** - * @} - */ diff --git a/feeds/ipq807x/qca-ssdk/src/src/hsl/horus/horus_leaky.c b/feeds/ipq807x/qca-ssdk/src/src/hsl/horus/horus_leaky.c deleted file mode 100755 index d3973be1f..000000000 --- a/feeds/ipq807x/qca-ssdk/src/src/hsl/horus/horus_leaky.c +++ /dev/null @@ -1,525 +0,0 @@ -/* - * Copyright (c) 2012, The Linux Foundation. All rights reserved. - * Permission to use, copy, modify, and/or distribute this software for - * any purpose with or without fee is hereby granted, provided that the - * above copyright notice and this permission notice appear in all copies. - * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES - * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR - * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES - * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN - * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT - * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. - */ - - -/** - * @defgroup horus_leaky HORUS_LEAKY - * @{ - */ -#include "sw.h" -#include "hsl.h" -#include "hsl_dev.h" -#include "hsl_port_prop.h" -#include "horus_leaky.h" -#include "horus_reg.h" - -static sw_error_t -_horus_uc_leaky_mode_set(a_uint32_t dev_id, - fal_leaky_ctrl_mode_t ctrl_mode) -{ - a_uint32_t data; - sw_error_t rv; - - HSL_DEV_ID_CHECK(dev_id); - - if (FAL_LEAKY_PORT_CTRL == ctrl_mode) - { - data = 0; - } - else if (FAL_LEAKY_FDB_CTRL == ctrl_mode) - { - data = 1; - } - else - { - return SW_BAD_PARAM; - } - - HSL_REG_FIELD_SET(rv, dev_id, FLOOD_MASK, 0, ARL_UNI_LEAKY, - (a_uint8_t *) (&data), sizeof (a_uint32_t)); - return rv; -} - -static sw_error_t -_horus_uc_leaky_mode_get(a_uint32_t dev_id, - fal_leaky_ctrl_mode_t *ctrl_mode) -{ - a_uint32_t data; - sw_error_t rv; - - HSL_DEV_ID_CHECK(dev_id); - - HSL_REG_FIELD_GET(rv, dev_id, FLOOD_MASK, 0, ARL_UNI_LEAKY, - (a_uint8_t *) (&data), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - - if (1 == data) - { - *ctrl_mode = FAL_LEAKY_FDB_CTRL; - } - else - { - *ctrl_mode = FAL_LEAKY_PORT_CTRL; - } - - return SW_OK; -} - -static sw_error_t -_horus_mc_leaky_mode_set(a_uint32_t dev_id, - fal_leaky_ctrl_mode_t ctrl_mode) -{ - a_uint32_t data; - sw_error_t rv; - - HSL_DEV_ID_CHECK(dev_id); - - if (FAL_LEAKY_PORT_CTRL == ctrl_mode) - { - data = 0; - } - else if (FAL_LEAKY_FDB_CTRL == ctrl_mode) - { - data = 1; - } - else - { - return SW_BAD_PARAM; - } - - HSL_REG_FIELD_SET(rv, dev_id, FLOOD_MASK, 0, ARL_MUL_LEAKY, - (a_uint8_t *) (&data), sizeof (a_uint32_t)); - return rv; -} - -static sw_error_t -_horus_mc_leaky_mode_get(a_uint32_t dev_id, - fal_leaky_ctrl_mode_t *ctrl_mode) -{ - a_uint32_t data; - sw_error_t rv; - - HSL_DEV_ID_CHECK(dev_id); - - HSL_REG_FIELD_GET(rv, dev_id, FLOOD_MASK, 0, ARL_MUL_LEAKY, - (a_uint8_t *) (&data), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - - if (1 == data) - { - *ctrl_mode = FAL_LEAKY_FDB_CTRL; - } - else - { - *ctrl_mode = FAL_LEAKY_PORT_CTRL; - } - - return SW_OK; -} - -static sw_error_t -_horus_port_arp_leaky_set(a_uint32_t dev_id, fal_port_t port_id, - a_bool_t enable) -{ - a_uint32_t data; - sw_error_t rv; - - HSL_DEV_ID_CHECK(dev_id); - - if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU)) - { - return SW_BAD_PARAM; - } - - if (A_TRUE == enable) - { - data = 1; - } - else if (A_FALSE == enable) - { - data = 0; - } - else - { - return SW_BAD_PARAM; - } - - HSL_REG_FIELD_SET(rv, dev_id, PORT_CTL, port_id, ARP_LEAKY_EN, - (a_uint8_t *) (&data), sizeof (a_uint32_t)); - return rv; -} - -static sw_error_t -_horus_port_arp_leaky_get(a_uint32_t dev_id, fal_port_t port_id, - a_bool_t *enable) -{ - a_uint32_t data; - sw_error_t rv; - - HSL_DEV_ID_CHECK(dev_id); - - if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU)) - { - return SW_BAD_PARAM; - } - - HSL_REG_FIELD_GET(rv, dev_id, PORT_CTL, port_id, ARP_LEAKY_EN, - (a_uint8_t *) (&data), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - - if (1 == data) - { - *enable = A_TRUE; - } - else - { - *enable = A_FALSE; - } - - return SW_OK; -} - -static sw_error_t -_horus_port_uc_leaky_set(a_uint32_t dev_id, fal_port_t port_id, - a_bool_t enable) -{ - a_uint32_t data; - sw_error_t rv; - - HSL_DEV_ID_CHECK(dev_id); - - if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU)) - { - return SW_BAD_PARAM; - } - - if (A_TRUE == enable) - { - data = 1; - } - else if (A_FALSE == enable) - { - data = 0; - } - else - { - return SW_BAD_PARAM; - } - - HSL_REG_FIELD_SET(rv, dev_id, PORT_BASE_VLAN, port_id, UNI_LEAKY_EN, - (a_uint8_t *) (&data), sizeof (a_uint32_t)); - return rv; -} - -static sw_error_t -_horus_port_uc_leaky_get(a_uint32_t dev_id, fal_port_t port_id, - a_bool_t *enable) -{ - a_uint32_t data; - sw_error_t rv; - - HSL_DEV_ID_CHECK(dev_id); - - if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU)) - { - return SW_BAD_PARAM; - } - - HSL_REG_FIELD_GET(rv, dev_id, PORT_BASE_VLAN, port_id, UNI_LEAKY_EN, - (a_uint8_t *) (&data), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - - if (1 == data) - { - *enable = A_TRUE; - } - else - { - *enable = A_FALSE; - } - - return SW_OK; -} - -static sw_error_t -_horus_port_mc_leaky_set(a_uint32_t dev_id, fal_port_t port_id, - a_bool_t enable) -{ - a_uint32_t data; - sw_error_t rv; - - HSL_DEV_ID_CHECK(dev_id); - - if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU)) - { - return SW_BAD_PARAM; - } - - if (A_TRUE == enable) - { - data = 1; - } - else if (A_FALSE == enable) - { - data = 0; - } - else - { - return SW_BAD_PARAM; - } - - HSL_REG_FIELD_SET(rv, dev_id, PORT_BASE_VLAN, port_id, MUL_LEAKY_EN, - (a_uint8_t *) (&data), sizeof (a_uint32_t)); - return rv; -} - -static sw_error_t -_horus_port_mc_leaky_get(a_uint32_t dev_id, fal_port_t port_id, - a_bool_t *enable) -{ - a_uint32_t data; - sw_error_t rv; - - HSL_DEV_ID_CHECK(dev_id); - - if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU)) - { - return SW_BAD_PARAM; - } - - HSL_REG_FIELD_GET(rv, dev_id, PORT_BASE_VLAN, port_id, MUL_LEAKY_EN, - (a_uint8_t *) (&data), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - - if (1 == data) - { - *enable = A_TRUE; - } - else - { - *enable = A_FALSE; - } - - return SW_OK; -} - -/** -* @brief Set unicast packets leaky control mode on a particular device. -* @param[in] dev_id device id -* @param[in] ctrl_mode leaky control mode -* @return SW_OK or error code -*/ -HSL_LOCAL sw_error_t -horus_uc_leaky_mode_set(a_uint32_t dev_id, - fal_leaky_ctrl_mode_t ctrl_mode) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _horus_uc_leaky_mode_set(dev_id, ctrl_mode); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Get unicast packets leaky control mode on a particular device. - * @param[in] dev_id device id - * @param[out] ctrl_mode leaky control mode - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -horus_uc_leaky_mode_get(a_uint32_t dev_id, - fal_leaky_ctrl_mode_t *ctrl_mode) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _horus_uc_leaky_mode_get(dev_id, ctrl_mode); - HSL_API_UNLOCK; - return rv; -} - -/** -* @brief Set multicast packets leaky control mode on a particular device. -* @param[in] dev_id device id -* @param[in] ctrl_mode leaky control mode -* @return SW_OK or error code -*/ -HSL_LOCAL sw_error_t -horus_mc_leaky_mode_set(a_uint32_t dev_id, - fal_leaky_ctrl_mode_t ctrl_mode) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _horus_mc_leaky_mode_set(dev_id, ctrl_mode); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Get multicast packets leaky control mode on a particular device. - * @param[in] dev_id device id - * @param[out] ctrl_mode leaky control mode - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -horus_mc_leaky_mode_get(a_uint32_t dev_id, - fal_leaky_ctrl_mode_t *ctrl_mode) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _horus_mc_leaky_mode_get(dev_id, ctrl_mode); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Set arp packets leaky status on a particular port. - * @param[in] dev_id device id - * @param[in] enable A_TRUE or A_FALSE - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -horus_port_arp_leaky_set(a_uint32_t dev_id, fal_port_t port_id, - a_bool_t enable) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _horus_port_arp_leaky_set(dev_id, port_id, enable); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Get arp packets leaky status on a particular port. - * @param[in] dev_id device id - * @param[out] enable A_TRUE or A_FALSE - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -horus_port_arp_leaky_get(a_uint32_t dev_id, fal_port_t port_id, - a_bool_t *enable) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _horus_port_arp_leaky_get(dev_id, port_id, enable); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Set unicast packets leaky status on a particular port. - * @param[in] dev_id device id - * @param[in] enable A_TRUE or A_FALSE - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -horus_port_uc_leaky_set(a_uint32_t dev_id, fal_port_t port_id, - a_bool_t enable) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _horus_port_uc_leaky_set(dev_id, port_id, enable); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Get unicast packets leaky status on a particular port. - * @param[in] dev_id device id - * @param[out] enable A_TRUE or A_FALSE - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -horus_port_uc_leaky_get(a_uint32_t dev_id, fal_port_t port_id, - a_bool_t *enable) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _horus_port_uc_leaky_get(dev_id, port_id, enable); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Set multicast packets leaky status on a particular port. - * @param[in] dev_id device id - * @param[in] enable A_TRUE or A_FALSE - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -horus_port_mc_leaky_set(a_uint32_t dev_id, fal_port_t port_id, - a_bool_t enable) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _horus_port_mc_leaky_set(dev_id, port_id, enable); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Get multicast packets leaky status on a particular port. - * @param[in] dev_id device id - * @param[out] enable A_TRUE or A_FALSE - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -horus_port_mc_leaky_get(a_uint32_t dev_id, fal_port_t port_id, - a_bool_t *enable) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _horus_port_mc_leaky_get(dev_id, port_id, enable); - HSL_API_UNLOCK; - return rv; -} - -sw_error_t -horus_leaky_init(a_uint32_t dev_id) -{ - HSL_DEV_ID_CHECK(dev_id); - -#ifndef HSL_STANDALONG - { - hsl_api_t *p_api; - - SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id)); - p_api->uc_leaky_mode_set = horus_uc_leaky_mode_set; - p_api->uc_leaky_mode_get = horus_uc_leaky_mode_get; - p_api->mc_leaky_mode_set = horus_mc_leaky_mode_set; - p_api->mc_leaky_mode_get = horus_mc_leaky_mode_get; - p_api->port_arp_leaky_set = horus_port_arp_leaky_set; - p_api->port_arp_leaky_get = horus_port_arp_leaky_get; - p_api->port_uc_leaky_set = horus_port_uc_leaky_set; - p_api->port_uc_leaky_get = horus_port_uc_leaky_get; - p_api->port_mc_leaky_set = horus_port_mc_leaky_set; - p_api->port_mc_leaky_get = horus_port_mc_leaky_get; - } -#endif - - return SW_OK; -} - -/** - * @} - */ diff --git a/feeds/ipq807x/qca-ssdk/src/src/hsl/horus/horus_led.c b/feeds/ipq807x/qca-ssdk/src/src/hsl/horus/horus_led.c deleted file mode 100755 index db2765dbf..000000000 --- a/feeds/ipq807x/qca-ssdk/src/src/hsl/horus/horus_led.c +++ /dev/null @@ -1,427 +0,0 @@ -/* - * Copyright (c) 2012, The Linux Foundation. All rights reserved. - * Permission to use, copy, modify, and/or distribute this software for - * any purpose with or without fee is hereby granted, provided that the - * above copyright notice and this permission notice appear in all copies. - * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES - * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR - * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES - * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN - * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT - * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. - */ - - -/** - * @defgroup horus_led HORUS_LED - * @{ - */ -#include "sw.h" -#include "hsl.h" -#include "hsl_dev.h" -#include "hsl_port_prop.h" -#include "horus_led.h" -#include "horus_reg.h" - -#define MAX_LED_PATTERN_ID 1 -#define LED_PATTERN_ADDR 0xB0 - -static sw_error_t -_horus_led_ctrl_pattern_set(a_uint32_t dev_id, led_pattern_group_t group, - led_pattern_id_t id, led_ctrl_pattern_t * pattern) -{ - a_uint32_t data = 0, reg, mode; - a_uint32_t addr; - sw_error_t rv; - - HSL_DEV_ID_CHECK(dev_id); - - if (group >= LED_GROUP_BUTT) - { - return SW_BAD_PARAM; - } - - if (id > MAX_LED_PATTERN_ID) - { - return SW_BAD_PARAM; - } - - if ((LED_MAC_PORT_GROUP == group) && (0 != id)) - { - return SW_BAD_PARAM; - } - - if (LED_MAC_PORT_GROUP == group) - { - addr = LED_PATTERN_ADDR + 8; - } - else - { - addr = LED_PATTERN_ADDR + (id << 2); - } - - if (LED_ALWAYS_OFF == pattern->mode) - { - mode = 0; - } - else if (LED_ALWAYS_BLINK == pattern->mode) - { - mode = 1; - } - else if (LED_ALWAYS_ON == pattern->mode) - { - mode = 2; - } - else if (LED_PATTERN_MAP_EN == pattern->mode) - { - mode = 3; - } - else - { - return SW_BAD_PARAM; - } - SW_SET_REG_BY_FIELD(LED_CTRL, PATTERN_EN, mode, data); - - if (pattern->map & (1 << FULL_DUPLEX_LIGHT_EN)) - { - SW_SET_REG_BY_FIELD(LED_CTRL, FULL_LIGHT_EN, 1, data); - } - - if (pattern->map & (1 << HALF_DUPLEX_LIGHT_EN)) - { - SW_SET_REG_BY_FIELD(LED_CTRL, HALF_LIGHT_EN, 1, data); - } - - if (pattern->map & (1 << POWER_ON_LIGHT_EN)) - { - SW_SET_REG_BY_FIELD(LED_CTRL, POWERON_LIGHT_EN, 1, data); - } - - if (pattern->map & (1 << LINK_1000M_LIGHT_EN)) - { - SW_SET_REG_BY_FIELD(LED_CTRL, GE_LIGHT_EN, 1, data); - } - - if (pattern->map & (1 << LINK_100M_LIGHT_EN)) - { - SW_SET_REG_BY_FIELD(LED_CTRL, FE_LIGHT_EN, 1, data); - } - - if (pattern->map & (1 << LINK_10M_LIGHT_EN)) - { - SW_SET_REG_BY_FIELD(LED_CTRL, ETH_LIGHT_EN, 1, data); - } - - if (pattern->map & (1 << COLLISION_BLINK_EN)) - { - SW_SET_REG_BY_FIELD(LED_CTRL, COL_BLINK_EN, 1, data); - } - - if (pattern->map & (1 << RX_TRAFFIC_BLINK_EN)) - { - SW_SET_REG_BY_FIELD(LED_CTRL, RX_BLINK_EN, 1, data); - } - - if (pattern->map & (1 << TX_TRAFFIC_BLINK_EN)) - { - SW_SET_REG_BY_FIELD(LED_CTRL, TX_BLINK_EN, 1, data); - } - - if (pattern->map & (1 << LINKUP_OVERRIDE_EN)) - { - SW_SET_REG_BY_FIELD(LED_CTRL, LINKUP_OVER_EN, 1, data); - } - else - { - SW_SET_REG_BY_FIELD(LED_CTRL, LINKUP_OVER_EN, 0, data); - } - - if (LED_BLINK_2HZ == pattern->freq) - { - SW_SET_REG_BY_FIELD(LED_CTRL, BLINK_FREQ, 0, data); - } - else if (LED_BLINK_4HZ == pattern->freq) - { - SW_SET_REG_BY_FIELD(LED_CTRL, BLINK_FREQ, 1, data); - } - else if (LED_BLINK_8HZ == pattern->freq) - { - SW_SET_REG_BY_FIELD(LED_CTRL, BLINK_FREQ, 2, data); - } - else if (LED_BLINK_TXRX == pattern->freq) - { - SW_SET_REG_BY_FIELD(LED_CTRL, BLINK_FREQ, 3, data); - } - else - { - return SW_BAD_PARAM; - } - - HSL_REG_ENTRY_GEN_GET(rv, dev_id, addr, sizeof (a_uint32_t), - (a_uint8_t *) (®), - sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - - if (LED_WAN_PORT_GROUP == group) - { - reg &= 0xffff; - reg |= (data << 16); - } - else - { - reg &= 0xffff0000; - reg |= data; - } - - HSL_REG_ENTRY_GEN_SET(rv, dev_id, addr, sizeof (a_uint32_t), - (a_uint8_t *) (®), - sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - - if (LED_WAN_PORT_GROUP == group) - { - return SW_OK; - } - - HSL_REG_ENTRY_GET(rv, dev_id, LED_PATTERN, 0, - (a_uint8_t *) (&data), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - - if (LED_LAN_PORT_GROUP == group) - { - if (id) - { - SW_SET_REG_BY_FIELD(LED_PATTERN, P3L1_MODE, mode, data); - SW_SET_REG_BY_FIELD(LED_PATTERN, P2L1_MODE, mode, data); - SW_SET_REG_BY_FIELD(LED_PATTERN, P1L1_MODE, mode, data); - } - else - { - SW_SET_REG_BY_FIELD(LED_PATTERN, P3L0_MODE, mode, data); - SW_SET_REG_BY_FIELD(LED_PATTERN, P2L0_MODE, mode, data); - SW_SET_REG_BY_FIELD(LED_PATTERN, P1L0_MODE, mode, data); - } - } - else - { - SW_SET_REG_BY_FIELD(LED_PATTERN, M5_MODE, mode, data); - } - - HSL_REG_ENTRY_SET(rv, dev_id, LED_PATTERN, 0, - (a_uint8_t *) (&data), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - - return SW_OK; -} - -static sw_error_t -_horus_led_ctrl_pattern_get(a_uint32_t dev_id, led_pattern_group_t group, - led_pattern_id_t id, led_ctrl_pattern_t * pattern) -{ - a_uint32_t data = 0, reg, tmp; - a_uint32_t addr; - sw_error_t rv; - - HSL_DEV_ID_CHECK(dev_id); - - if (group >= LED_GROUP_BUTT) - { - return SW_BAD_PARAM; - } - - if (id > MAX_LED_PATTERN_ID) - { - return SW_BAD_PARAM; - } - - if ((LED_MAC_PORT_GROUP == group) && (0 != id)) - { - return SW_BAD_PARAM; - } - - aos_mem_zero(pattern, sizeof(led_ctrl_pattern_t)); - - if (LED_MAC_PORT_GROUP == group) - { - addr = LED_PATTERN_ADDR + 8; - } - else - { - addr = LED_PATTERN_ADDR + (id << 2); - } - - HSL_REG_ENTRY_GEN_GET(rv, dev_id, addr, sizeof (a_uint32_t), - (a_uint8_t *) (®), - sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - - if (LED_WAN_PORT_GROUP == group) - { - data = (reg >> 16) & 0xffff; - } - else - { - data = reg & 0xffff; - } - - SW_GET_FIELD_BY_REG(LED_CTRL, PATTERN_EN, tmp, data); - if (0 == tmp) - { - pattern->mode = LED_ALWAYS_OFF; - } - else if (1 == tmp) - { - pattern->mode = LED_ALWAYS_BLINK; - } - else if (2 == tmp) - { - pattern->mode = LED_ALWAYS_ON; - } - else - { - pattern->mode = LED_PATTERN_MAP_EN; - } - - SW_GET_FIELD_BY_REG(LED_CTRL, FULL_LIGHT_EN, tmp, data); - if (1 == tmp) - { - pattern->map |= (1 << FULL_DUPLEX_LIGHT_EN); - } - - SW_GET_FIELD_BY_REG(LED_CTRL, HALF_LIGHT_EN, tmp, data); - if (1 == tmp) - { - pattern->map |= (1 << HALF_DUPLEX_LIGHT_EN); - } - - SW_GET_FIELD_BY_REG(LED_CTRL, POWERON_LIGHT_EN, tmp, data); - if (1 == tmp) - { - pattern->map |= (1 << POWER_ON_LIGHT_EN); - } - - SW_GET_FIELD_BY_REG(LED_CTRL, GE_LIGHT_EN, tmp, data); - if (1 == tmp) - { - pattern->map |= (1 << LINK_1000M_LIGHT_EN); - } - - SW_GET_FIELD_BY_REG(LED_CTRL, FE_LIGHT_EN, tmp, data); - if (1 == tmp) - { - pattern->map |= (1 << LINK_100M_LIGHT_EN); - } - - SW_GET_FIELD_BY_REG(LED_CTRL, ETH_LIGHT_EN, tmp, data); - if (1 == tmp) - { - pattern->map |= (1 << LINK_10M_LIGHT_EN); - } - - SW_GET_FIELD_BY_REG(LED_CTRL, COL_BLINK_EN, tmp, data); - if (1 == tmp) - { - pattern->map |= (1 << COLLISION_BLINK_EN); - } - - SW_GET_FIELD_BY_REG(LED_CTRL, RX_BLINK_EN, tmp, data); - if (1 == tmp) - { - pattern->map |= (1 << RX_TRAFFIC_BLINK_EN); - } - - SW_GET_FIELD_BY_REG(LED_CTRL, TX_BLINK_EN, tmp, data); - if (1 == tmp) - { - pattern->map |= (1 << TX_TRAFFIC_BLINK_EN); - } - - SW_GET_FIELD_BY_REG(LED_CTRL, LINKUP_OVER_EN, tmp, data); - if (1 == tmp) - { - pattern->map |= (1 << LINKUP_OVERRIDE_EN); - } - - SW_GET_FIELD_BY_REG(LED_CTRL, BLINK_FREQ, tmp, data); - if (0 == tmp) - { - pattern->freq = LED_BLINK_2HZ; - } - else if (1 == tmp) - { - pattern->freq = LED_BLINK_4HZ; - } - else if (2 == tmp) - { - pattern->freq = LED_BLINK_8HZ; - } - else - { - pattern->freq = LED_BLINK_TXRX; - } - - return SW_OK; -} - -/** -* @brief Set led control pattern on a particular device. -* @param[in] dev_id device id -* @param[in] group pattern group, lan or wan -* @param[in] id pattern id -* @param[in] pattern led control pattern -* @return SW_OK or error code -*/ -HSL_LOCAL sw_error_t -horus_led_ctrl_pattern_set(a_uint32_t dev_id, led_pattern_group_t group, - led_pattern_id_t id, led_ctrl_pattern_t * pattern) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _horus_led_ctrl_pattern_set(dev_id, group, id, pattern); - HSL_API_UNLOCK; - return rv; -} - -/** -* @brief Get led control pattern on a particular device. -* @param[in] dev_id device id -* @param[in] group pattern group, lan or wan -* @param[in] id pattern id -* @param[out] pattern led control pattern -* @return SW_OK or error code -*/ -HSL_LOCAL sw_error_t -horus_led_ctrl_pattern_get(a_uint32_t dev_id, led_pattern_group_t group, - led_pattern_id_t id, led_ctrl_pattern_t * pattern) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _horus_led_ctrl_pattern_get(dev_id, group, id, pattern); - HSL_API_UNLOCK; - return rv; -} - -sw_error_t -horus_led_init(a_uint32_t dev_id) -{ - HSL_DEV_ID_CHECK(dev_id); - -#ifndef HSL_STANDALONG - { - hsl_api_t *p_api; - - SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id)); - p_api->led_ctrl_pattern_set = horus_led_ctrl_pattern_set; - p_api->led_ctrl_pattern_get = horus_led_ctrl_pattern_get; - } -#endif - - return SW_OK; -} - -/** - * @} - */ diff --git a/feeds/ipq807x/qca-ssdk/src/src/hsl/horus/horus_mib.c b/feeds/ipq807x/qca-ssdk/src/src/hsl/horus/horus_mib.c deleted file mode 100755 index 4c800011b..000000000 --- a/feeds/ipq807x/qca-ssdk/src/src/hsl/horus/horus_mib.c +++ /dev/null @@ -1,377 +0,0 @@ -/* - * Copyright (c) 2012, The Linux Foundation. All rights reserved. - * Permission to use, copy, modify, and/or distribute this software for - * any purpose with or without fee is hereby granted, provided that the - * above copyright notice and this permission notice appear in all copies. - * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES - * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR - * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES - * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN - * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT - * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. - */ - - -/** - * @defgroup horus_mib HORUS_MIB - * @{ - */ -#include "sw.h" -#include "hsl.h" -#include "hsl_dev.h" -#include "hsl_port_prop.h" -#include "horus_mib.h" -#include "horus_reg.h" - -static sw_error_t -_horus_get_mib_info(a_uint32_t dev_id, fal_port_t port_id, - fal_mib_info_t * mib_info) -{ - a_uint32_t val; - sw_error_t rv; - - HSL_DEV_ID_CHECK(dev_id); - - if (A_FALSE == hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU)) - { - return SW_OUT_OF_RANGE; - } - - HSL_REG_ENTRY_GET(rv, dev_id, MIB_RXBROAD, port_id, - (a_uint8_t *) (&val), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - mib_info->RxBroad = val; - - HSL_REG_ENTRY_GET(rv, dev_id, MIB_RXPAUSE, port_id, - (a_uint8_t *) (&val), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - mib_info->RxPause = val; - - HSL_REG_ENTRY_GET(rv, dev_id, MIB_RXMULTI, port_id, - (a_uint8_t *) (&val), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - mib_info->RxMulti = val; - - HSL_REG_ENTRY_GET(rv, dev_id, MIB_RXFCSERR, port_id, - (a_uint8_t *) (&val), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - mib_info->RxFcsErr = val; - - HSL_REG_ENTRY_GET(rv, dev_id, MIB_RXALLIGNERR, port_id, - (a_uint8_t *) (&val), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - mib_info->RxAllignErr = val; - - HSL_REG_ENTRY_GET(rv, dev_id, MIB_RXRUNT, port_id, (a_uint8_t *) (&val), - sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - mib_info->RxRunt = val; - - HSL_REG_ENTRY_GET(rv, dev_id, MIB_RXFRAGMENT, port_id, - (a_uint8_t *) (&val), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - mib_info->RxFragment = val; - - HSL_REG_ENTRY_GET(rv, dev_id, MIB_RX64BYTE, port_id, - (a_uint8_t *) (&val), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - mib_info->Rx64Byte = val; - - HSL_REG_ENTRY_GET(rv, dev_id, MIB_RX128BYTE, port_id, - (a_uint8_t *) (&val), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - mib_info->Rx128Byte = val; - - HSL_REG_ENTRY_GET(rv, dev_id, MIB_RX256BYTE, port_id, - (a_uint8_t *) (&val), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - mib_info->Rx256Byte = val; - - HSL_REG_ENTRY_GET(rv, dev_id, MIB_RX512BYTE, port_id, - (a_uint8_t *) (&val), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - mib_info->Rx512Byte = val; - - HSL_REG_ENTRY_GET(rv, dev_id, MIB_RX1024BYTE, port_id, - (a_uint8_t *) (&val), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - mib_info->Rx1024Byte = val; - - HSL_REG_ENTRY_GET(rv, dev_id, MIB_RX1518BYTE, port_id, - (a_uint8_t *) (&val), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - mib_info->Rx1518Byte = val; - - HSL_REG_ENTRY_GET(rv, dev_id, MIB_RXMAXBYTE, port_id, - (a_uint8_t *) (&val), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - mib_info->RxMaxByte = val; - - HSL_REG_ENTRY_GET(rv, dev_id, MIB_RXTOOLONG, port_id, - (a_uint8_t *) (&val), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - mib_info->RxTooLong = val; - - HSL_REG_ENTRY_GET(rv, dev_id, MIB_RXGOODBYTE_LO, port_id, - (a_uint8_t *) (&val), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - mib_info->RxGoodByte_lo = val; - - HSL_REG_ENTRY_GET(rv, dev_id, MIB_RXGOODBYTE_HI, port_id, - (a_uint8_t *) (&val), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - mib_info->RxGoodByte_hi = val; - - HSL_REG_ENTRY_GET(rv, dev_id, MIB_RXBADBYTE_LO, port_id, - (a_uint8_t *) (&val), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - mib_info->RxBadByte_lo = val; - - HSL_REG_ENTRY_GET(rv, dev_id, MIB_RXBADBYTE_HI, port_id, - (a_uint8_t *) (&val), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - mib_info->RxBadByte_hi = val; - - HSL_REG_ENTRY_GET(rv, dev_id, MIB_RXOVERFLOW, port_id, - (a_uint8_t *) (&val), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - mib_info->RxOverFlow = val; - - HSL_REG_ENTRY_GET(rv, dev_id, MIB_FILTERED, port_id, - (a_uint8_t *) (&val), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - mib_info->Filtered = val; - - HSL_REG_ENTRY_GET(rv, dev_id, MIB_TXBROAD, port_id, (a_uint8_t *) (&val), - sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - mib_info->TxBroad = val; - - HSL_REG_ENTRY_GET(rv, dev_id, MIB_TXPAUSE, port_id, (a_uint8_t *) (&val), - sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - mib_info->TxPause = val; - - HSL_REG_ENTRY_GET(rv, dev_id, MIB_TXMULTI, port_id, (a_uint8_t *) (&val), - sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - mib_info->TxMulti = val; - - HSL_REG_ENTRY_GET(rv, dev_id, MIB_TXUNDERRUN, port_id, - (a_uint8_t *) (&val), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - mib_info->TxUnderRun = val; - - HSL_REG_ENTRY_GET(rv, dev_id, MIB_TX64BYTE, port_id, - (a_uint8_t *) (&val), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - mib_info->Tx64Byte = val; - - HSL_REG_ENTRY_GET(rv, dev_id, MIB_TX128BYTE, port_id, - (a_uint8_t *) (&val), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - mib_info->Tx128Byte = val; - - HSL_REG_ENTRY_GET(rv, dev_id, MIB_TX256BYTE, port_id, - (a_uint8_t *) (&val), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - mib_info->Tx256Byte = val; - - HSL_REG_ENTRY_GET(rv, dev_id, MIB_TX512BYTE, port_id, - (a_uint8_t *) (&val), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - mib_info->Tx512Byte = val; - - HSL_REG_ENTRY_GET(rv, dev_id, MIB_TX1024BYTE, port_id, - (a_uint8_t *) (&val), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - mib_info->Tx1024Byte = val; - - HSL_REG_ENTRY_GET(rv, dev_id, MIB_TX1518BYTE, port_id, - (a_uint8_t *) (&val), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - mib_info->Tx1518Byte = val; - - HSL_REG_ENTRY_GET(rv, dev_id, MIB_TXMAXBYTE, port_id, - (a_uint8_t *) (&val), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - mib_info->TxMaxByte = val; - - HSL_REG_ENTRY_GET(rv, dev_id, MIB_TXOVERSIZE, port_id, - (a_uint8_t *) (&val), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - mib_info->TxOverSize = val; - - HSL_REG_ENTRY_GET(rv, dev_id, MIB_TXBYTE_LO, port_id, - (a_uint8_t *) (&val), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - mib_info->TxByte_lo = val; - - HSL_REG_ENTRY_GET(rv, dev_id, MIB_TXBYTE_HI, port_id, - (a_uint8_t *) (&val), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - mib_info->TxByte_hi = val; - - HSL_REG_ENTRY_GET(rv, dev_id, MIB_TXCOLLISION, port_id, - (a_uint8_t *) (&val), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - mib_info->TxCollision = val; - - HSL_REG_ENTRY_GET(rv, dev_id, MIB_TXABORTCOL, port_id, - (a_uint8_t *) (&val), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - mib_info->TxAbortCol = val; - - HSL_REG_ENTRY_GET(rv, dev_id, MIB_TXMULTICOL, port_id, - (a_uint8_t *) (&val), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - mib_info->TxMultiCol = val; - - HSL_REG_ENTRY_GET(rv, dev_id, MIB_TXSINGALCOL, port_id, - (a_uint8_t *) (&val), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - mib_info->TxSingalCol = val; - - HSL_REG_ENTRY_GET(rv, dev_id, MIB_TXEXCDEFER, port_id, - (a_uint8_t *) (&val), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - mib_info->TxExcDefer = val; - - HSL_REG_ENTRY_GET(rv, dev_id, MIB_TXDEFER, port_id, (a_uint8_t *) (&val), - sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - mib_info->TxDefer = val; - - HSL_REG_ENTRY_GET(rv, dev_id, MIB_TXLATECOL, port_id, - (a_uint8_t *) (&val), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - mib_info->TxLateCol = val; - - return SW_OK; -} - -static sw_error_t -_horus_mib_status_set(a_uint32_t dev_id, a_bool_t enable) -{ - sw_error_t rv; - a_uint32_t val; - - HSL_DEV_ID_CHECK(dev_id); - - if (A_TRUE == enable) - { - val = 1; - } - else if (A_FALSE == enable) - { - val = 0; - } - else - { - return SW_BAD_PARAM; - } - - HSL_REG_FIELD_SET(rv, dev_id, MIB_FUNC, 0, MIB_EN, - (a_uint8_t *) (&val), sizeof (a_uint32_t)); - return rv; -} - -static sw_error_t -_horus_mib_status_get(a_uint32_t dev_id, a_bool_t * enable) -{ - sw_error_t rv; - a_uint32_t val; - - HSL_DEV_ID_CHECK(dev_id); - - HSL_REG_FIELD_GET(rv, dev_id, MIB_FUNC, 0, MIB_EN, - (a_uint8_t *) (&val), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - - if (1 == val) - { - *enable = A_TRUE; - } - else - { - *enable = A_FALSE; - } - - return SW_OK; -} - -/** - * @brief Get mib infomation on particular port. - * @param[in] dev_id device id - * @param[in] port_id port id - * @param[out] mib_info mib infomation - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -horus_get_mib_info(a_uint32_t dev_id, fal_port_t port_id, - fal_mib_info_t * mib_info) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _horus_get_mib_info(dev_id, port_id, mib_info); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Set mib status on a particular device. - * @param[in] dev_id device id - * @param[in] enable A_TRUE or A_FALSE - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -horus_mib_status_set(a_uint32_t dev_id, a_bool_t enable) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _horus_mib_status_set(dev_id, enable); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Get mib status on a particular device. - * @param[in] dev_id device id - * @param[out] enable A_TRUE or A_FALSE - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -horus_mib_status_get(a_uint32_t dev_id, a_bool_t * enable) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _horus_mib_status_get(dev_id, enable); - HSL_API_UNLOCK; - return rv; -} - -sw_error_t -horus_mib_init(a_uint32_t dev_id) -{ - HSL_DEV_ID_CHECK(dev_id); - -#ifndef HSL_STANDALONG - hsl_api_t *p_api; - - SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id)); - - p_api->get_mib_info = horus_get_mib_info; - p_api->mib_status_set = horus_mib_status_set; - p_api->mib_status_get = horus_mib_status_get; -#endif - - return SW_OK; -} - -/** - * @} - */ diff --git a/feeds/ipq807x/qca-ssdk/src/src/hsl/horus/horus_mirror.c b/feeds/ipq807x/qca-ssdk/src/src/hsl/horus/horus_mirror.c deleted file mode 100755 index bc929808a..000000000 --- a/feeds/ipq807x/qca-ssdk/src/src/hsl/horus/horus_mirror.c +++ /dev/null @@ -1,317 +0,0 @@ -/* - * Copyright (c) 2012, The Linux Foundation. All rights reserved. - * Permission to use, copy, modify, and/or distribute this software for - * any purpose with or without fee is hereby granted, provided that the - * above copyright notice and this permission notice appear in all copies. - * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES - * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR - * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES - * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN - * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT - * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. - */ - - -/** - * @defgroup horus_mirror HORUS_MIRROR - * @{ - */ -#include "sw.h" -#include "hsl.h" -#include "hsl_dev.h" -#include "hsl_port_prop.h" -#include "horus_mirror.h" -#include "horus_reg.h" - -static sw_error_t -_horus_mirr_analysis_port_set(a_uint32_t dev_id, fal_port_t port_id) -{ - sw_error_t rv; - a_uint32_t val; - - HSL_DEV_ID_CHECK(dev_id); - - if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU)) - { - return SW_BAD_PARAM; - } - - val = port_id; - HSL_REG_FIELD_SET(rv, dev_id, CPU_PORT, 0, MIRROR_PORT_NUM, - (a_uint8_t *) (&val), sizeof (a_uint32_t)); - return rv; -} - -static sw_error_t -_horus_mirr_analysis_port_get(a_uint32_t dev_id, fal_port_t * port_id) -{ - sw_error_t rv; - a_uint32_t val; - - HSL_DEV_ID_CHECK(dev_id); - - HSL_REG_FIELD_GET(rv, dev_id, CPU_PORT, 0, MIRROR_PORT_NUM, - (a_uint8_t *) (&val), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - - *port_id = val; - return SW_OK; -} - -static sw_error_t -_horus_mirr_port_in_set(a_uint32_t dev_id, fal_port_t port_id, a_bool_t enable) -{ - sw_error_t rv; - a_uint32_t val; - - HSL_DEV_ID_CHECK(dev_id); - - if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU)) - { - return SW_BAD_PARAM; - } - - if (A_TRUE == enable) - { - val = 1; - } - else if (A_FALSE == enable) - { - val = 0; - } - else - { - return SW_BAD_PARAM; - } - - HSL_REG_FIELD_SET(rv, dev_id, PORT_CTL, port_id, ING_MIRROR_EN, - (a_uint8_t *) (&val), sizeof (a_uint32_t)); - return rv; -} - -static sw_error_t -_horus_mirr_port_in_get(a_uint32_t dev_id, fal_port_t port_id, - a_bool_t * enable) -{ - sw_error_t rv; - a_uint32_t val; - - HSL_DEV_ID_CHECK(dev_id); - - if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU)) - { - return SW_BAD_PARAM; - } - - HSL_REG_FIELD_GET(rv, dev_id, PORT_CTL, port_id, ING_MIRROR_EN, - (a_uint8_t *) (&val), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - - if (1 == val) - { - *enable = A_TRUE; - } - else - { - *enable = A_FALSE; - } - - return SW_OK; -} - -static sw_error_t -_horus_mirr_port_eg_set(a_uint32_t dev_id, fal_port_t port_id, a_bool_t enable) -{ - sw_error_t rv; - a_uint32_t val; - - HSL_DEV_ID_CHECK(dev_id); - - if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU)) - { - return SW_BAD_PARAM; - } - - if (A_TRUE == enable) - { - val = 1; - } - else if (A_FALSE == enable) - { - val = 0; - } - else - { - return SW_BAD_PARAM; - } - - HSL_REG_FIELD_SET(rv, dev_id, PORT_CTL, port_id, EG_MIRROR_EN, - (a_uint8_t *) (&val), sizeof (a_uint32_t)); - return rv; -} - -static sw_error_t -_horus_mirr_port_eg_get(a_uint32_t dev_id, fal_port_t port_id, a_bool_t * enable) -{ - sw_error_t rv; - a_uint32_t val; - - HSL_DEV_ID_CHECK(dev_id); - - if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU)) - { - return SW_BAD_PARAM; - } - - HSL_REG_FIELD_GET(rv, dev_id, PORT_CTL, port_id, EG_MIRROR_EN, - (a_uint8_t *) (&val), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - - if (1 == val) - { - *enable = A_TRUE; - } - else - { - *enable = A_FALSE; - } - - return SW_OK; -} - -/** - * @details Comments: - * The analysis port works for both ingress and egress mirror. - * @brief Set mirror analyzer port on particular a device. - * @param[in] dev_id device id - * @param[in] port_id port id - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -horus_mirr_analysis_port_set(a_uint32_t dev_id, fal_port_t port_id) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _horus_mirr_analysis_port_set(dev_id, port_id); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Get mirror analysis port on particular a device. - * @param[in] dev_id device id - * @param[out] port_id port id - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -horus_mirr_analysis_port_get(a_uint32_t dev_id, fal_port_t * port_id) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _horus_mirr_analysis_port_get(dev_id, port_id); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Set ingress mirror status on particular a port. - * @param[in] dev_id device id - * @param[in] port_id port id - * @param[in] enable A_TRUE or A_FALSE - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -horus_mirr_port_in_set(a_uint32_t dev_id, fal_port_t port_id, a_bool_t enable) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _horus_mirr_port_in_set(dev_id, port_id, enable); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Get ingress mirror status on particular a port. - * @param[in] dev_id device id - * @param[in] port_id port id - * @param[out] enable A_TRUE or A_FALSE - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -horus_mirr_port_in_get(a_uint32_t dev_id, fal_port_t port_id, - a_bool_t * enable) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _horus_mirr_port_in_get(dev_id, port_id, enable); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Set egress mirror status on a particular port. - * @param[in] dev_id device id - * @param[in] port_id port id - * @param[in] enable A_TRUE or A_FALSE - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -horus_mirr_port_eg_set(a_uint32_t dev_id, fal_port_t port_id, a_bool_t enable) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _horus_mirr_port_eg_set(dev_id, port_id, enable); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Get egress mirror status on a particular port. - * @param[in] dev_id device id - * @param[in] port_id port id - * @param[out] enable A_TRUE or A_FALSE - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -horus_mirr_port_eg_get(a_uint32_t dev_id, fal_port_t port_id, a_bool_t * enable) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _horus_mirr_port_eg_get(dev_id, port_id, enable); - HSL_API_UNLOCK; - return rv; -} - -sw_error_t -horus_mirr_init(a_uint32_t dev_id) -{ - HSL_DEV_ID_CHECK(dev_id); - -#ifndef HSL_STANDALONG - { - hsl_api_t *p_api; - - SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id)); - - p_api->mirr_analysis_port_set = horus_mirr_analysis_port_set; - p_api->mirr_analysis_port_get = horus_mirr_analysis_port_get; - p_api->mirr_port_in_set = horus_mirr_port_in_set; - p_api->mirr_port_in_get = horus_mirr_port_in_get; - p_api->mirr_port_eg_set = horus_mirr_port_eg_set; - p_api->mirr_port_eg_get = horus_mirr_port_eg_get; - } -#endif - - return SW_OK; -} - -/** - * @} - */ diff --git a/feeds/ipq807x/qca-ssdk/src/src/hsl/horus/horus_misc.c b/feeds/ipq807x/qca-ssdk/src/src/hsl/horus/horus_misc.c deleted file mode 100755 index 1c13ff704..000000000 --- a/feeds/ipq807x/qca-ssdk/src/src/hsl/horus/horus_misc.c +++ /dev/null @@ -1,1396 +0,0 @@ -/* - * Copyright (c) 2012, The Linux Foundation. All rights reserved. - * Permission to use, copy, modify, and/or distribute this software for - * any purpose with or without fee is hereby granted, provided that the - * above copyright notice and this permission notice appear in all copies. - * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES - * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR - * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES - * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN - * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT - * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. - */ - - -/** - * @defgroup horus_misc HORUS_MISC - * @{ - */ -#include "sw.h" -#include "hsl.h" -#include "hsl_dev.h" -#include "hsl_port_prop.h" -#include "horus_misc.h" -#include "horus_reg.h" - -#define HORUS_MAX_FRMAE_SIZE 9216 - -static sw_error_t -_horus_arp_status_set(a_uint32_t dev_id, a_bool_t enable) -{ - a_uint32_t data; - sw_error_t rv; - - HSL_DEV_ID_CHECK(dev_id); - - if (A_TRUE == enable) - { - data = 1; - } - else if (A_FALSE == enable) - { - data = 0; - } - else - { - return SW_BAD_PARAM; - } - - HSL_REG_FIELD_SET(rv, dev_id, QM_CTL, 0, ARP_EN, - (a_uint8_t *) (&data), sizeof (a_uint32_t)); - return rv; -} - -static sw_error_t -_horus_arp_status_get(a_uint32_t dev_id, a_bool_t *enable) -{ - a_uint32_t data; - sw_error_t rv; - - HSL_DEV_ID_CHECK(dev_id); - - HSL_REG_FIELD_GET(rv, dev_id, QM_CTL, 0, ARP_EN, - (a_uint8_t *) (&data), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - - if (1 == data) - { - *enable = A_TRUE; - } - else - { - *enable = A_FALSE; - } - - return SW_OK; -} - -static sw_error_t -_horus_frame_max_size_set(a_uint32_t dev_id, a_uint32_t size) -{ - a_uint32_t data; - sw_error_t rv; - - HSL_DEV_ID_CHECK(dev_id); - - if (HORUS_MAX_FRMAE_SIZE < size) - { - return SW_BAD_PARAM; - } - - data = size; - HSL_REG_FIELD_SET(rv, dev_id, GLOBAL_CTL, 0, MAX_FRAME_SIZE, - (a_uint8_t *) (&data), sizeof (a_uint32_t)); - return rv; -} - -static sw_error_t -_horus_frame_max_size_get(a_uint32_t dev_id, a_uint32_t *size) -{ - a_uint32_t data; - sw_error_t rv; - - HSL_DEV_ID_CHECK(dev_id); - - HSL_REG_FIELD_GET(rv, dev_id, GLOBAL_CTL, 0, MAX_FRAME_SIZE, - (a_uint8_t *) (&data), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - - *size = data; - return SW_OK; -} - -static sw_error_t -_horus_port_unk_sa_cmd_set(a_uint32_t dev_id, fal_port_t port_id, - fal_fwd_cmd_t cmd) -{ - sw_error_t rv; - a_uint32_t data; - - HSL_DEV_ID_CHECK(dev_id); - - if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU)) - { - return SW_BAD_PARAM; - } - - HSL_REG_ENTRY_GET(rv, dev_id, PORT_CTL, port_id, (a_uint8_t *) (&data), - sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - - if (FAL_MAC_FRWRD == cmd) - { - SW_SET_REG_BY_FIELD(PORT_CTL, PORT_LOCK_EN, 0, data); - } - else if (FAL_MAC_DROP == cmd) - { - SW_SET_REG_BY_FIELD(PORT_CTL, PORT_LOCK_EN, 1, data); - SW_SET_REG_BY_FIELD(PORT_CTL, LOCK_DROP_EN, 1, data); - } - else if (FAL_MAC_RDT_TO_CPU == cmd) - { - SW_SET_REG_BY_FIELD(PORT_CTL, PORT_LOCK_EN, 1, data); - SW_SET_REG_BY_FIELD(PORT_CTL, LOCK_DROP_EN, 0, data); - } - else - { - return SW_NOT_SUPPORTED; - } - - HSL_REG_ENTRY_SET(rv, dev_id, PORT_CTL, port_id, (a_uint8_t *) (&data), - sizeof (a_uint32_t)); - return rv; -} - -static sw_error_t -_horus_port_unk_sa_cmd_get(a_uint32_t dev_id, fal_port_t port_id, - fal_fwd_cmd_t * action) -{ - sw_error_t rv; - a_uint32_t data; - a_uint32_t port_lock_en, port_drop_en; - - HSL_DEV_ID_CHECK(dev_id); - - if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU)) - { - return SW_BAD_PARAM; - } - - HSL_REG_ENTRY_GET(rv, dev_id, PORT_CTL, port_id, (a_uint8_t *) (&data), - sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - - SW_GET_FIELD_BY_REG(PORT_CTL, PORT_LOCK_EN, port_lock_en, data); - SW_GET_FIELD_BY_REG(PORT_CTL, LOCK_DROP_EN, port_drop_en, data); - - if (1 == port_lock_en) - { - if (1 == port_drop_en) - { - *action = FAL_MAC_DROP; - } - else - { - *action = FAL_MAC_RDT_TO_CPU; - } - } - else - { - *action = FAL_MAC_FRWRD; - } - - return SW_OK; -} - -static sw_error_t -_horus_port_unk_uc_filter_set(a_uint32_t dev_id, fal_port_t port_id, - a_bool_t enable) -{ - sw_error_t rv; - a_uint32_t data; - - HSL_DEV_ID_CHECK(dev_id); - - if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU)) - { - return SW_BAD_PARAM; - } - - HSL_REG_FIELD_GET(rv, dev_id, FLOOD_MASK, 0, UNI_FLOOD_DP, - (a_uint8_t *) (&data), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - - if (A_TRUE == enable) - { - data &= (~((a_uint32_t)0x1 << port_id)); - } - else if (A_FALSE == enable) - { - data |= (0x1 << port_id); - } - else - { - return SW_BAD_PARAM; - } - - HSL_REG_FIELD_SET(rv, dev_id, FLOOD_MASK, 0, UNI_FLOOD_DP, - (a_uint8_t *) (&data), sizeof (a_uint32_t)); - return rv; -} - -static sw_error_t -_horus_port_unk_uc_filter_get(a_uint32_t dev_id, fal_port_t port_id, - a_bool_t * enable) -{ - sw_error_t rv; - a_uint32_t reg, field; - - HSL_DEV_ID_CHECK(dev_id); - - if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU)) - { - return SW_BAD_PARAM; - } - - HSL_REG_FIELD_GET(rv, dev_id, FLOOD_MASK, 0, UNI_FLOOD_DP, - (a_uint8_t *) (®), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - - field = reg & (0x1 << port_id); - if (field) - { - *enable = A_FALSE; - } - else - { - *enable = A_TRUE; - } - - return SW_OK; -} - -static sw_error_t -_horus_port_unk_mc_filter_set(a_uint32_t dev_id, fal_port_t port_id, - a_bool_t enable) -{ - sw_error_t rv; - a_uint32_t data; - - HSL_DEV_ID_CHECK(dev_id); - - if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU)) - { - return SW_BAD_PARAM; - } - - HSL_REG_FIELD_GET(rv, dev_id, FLOOD_MASK, 0, MUL_FLOOD_DP, - (a_uint8_t *) (&data), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - - if (A_TRUE == enable) - { - data &= (~((a_uint32_t)0x1 << port_id)); - } - else if (A_FALSE == enable) - { - data |= (0x1 << port_id); - } - else - { - return SW_BAD_PARAM; - } - - HSL_REG_FIELD_SET(rv, dev_id, FLOOD_MASK, 0, MUL_FLOOD_DP, - (a_uint8_t *) (&data), sizeof (a_uint32_t)); - return rv; -} - -static sw_error_t -_horus_port_unk_mc_filter_get(a_uint32_t dev_id, fal_port_t port_id, - a_bool_t * enable) -{ - sw_error_t rv; - a_uint32_t reg, field; - - HSL_DEV_ID_CHECK(dev_id); - - if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU)) - { - return SW_BAD_PARAM; - } - - HSL_REG_FIELD_GET(rv, dev_id, FLOOD_MASK, 0, MUL_FLOOD_DP, - (a_uint8_t *) (®), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - - field = reg & (0x1 << port_id); - if (field) - { - *enable = A_FALSE; - } - else - { - *enable = A_TRUE; - } - - return SW_OK; -} - -static sw_error_t -_horus_port_bc_filter_set(a_uint32_t dev_id, fal_port_t port_id, - a_bool_t enable) -{ - sw_error_t rv; - a_uint32_t data; - - HSL_DEV_ID_CHECK(dev_id); - - if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU)) - { - return SW_BAD_PARAM; - } - - HSL_REG_FIELD_GET(rv, dev_id, FLOOD_MASK, 0, BC_FLOOD_DP, - (a_uint8_t *) (&data), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - - if (A_TRUE == enable) - { - data &= (~((a_uint32_t)0x1 << port_id)); - } - else if (A_FALSE == enable) - { - data |= (0x1 << port_id); - } - else - { - return SW_BAD_PARAM; - } - - HSL_REG_FIELD_SET(rv, dev_id, FLOOD_MASK, 0, BC_FLOOD_DP, - (a_uint8_t *) (&data), sizeof (a_uint32_t)); - return rv; -} - -static sw_error_t -_horus_port_bc_filter_get(a_uint32_t dev_id, fal_port_t port_id, - a_bool_t * enable) -{ - sw_error_t rv; - a_uint32_t reg, field; - - HSL_DEV_ID_CHECK(dev_id); - - if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU)) - { - return SW_BAD_PARAM; - } - - HSL_REG_FIELD_GET(rv, dev_id, FLOOD_MASK, 0, BC_FLOOD_DP, - (a_uint8_t *) (®), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - - field = reg & (0x1 << port_id); - if (field) - { - *enable = A_FALSE; - } - else - { - *enable = A_TRUE; - } - - return SW_OK; -} - -static sw_error_t -_horus_cpu_port_status_set(a_uint32_t dev_id, a_bool_t enable) -{ - sw_error_t rv; - a_uint32_t val; - - HSL_DEV_ID_CHECK(dev_id); - - if (A_TRUE == enable) - { - val = 1; - } - else if (A_FALSE == enable) - { - val = 0; - } - else - { - return SW_BAD_PARAM; - } - - HSL_REG_FIELD_SET(rv, dev_id, CPU_PORT, 0, CPU_PORT_EN, - (a_uint8_t *) (&val), sizeof (a_uint32_t)); - return rv; -} - -static sw_error_t -_horus_cpu_port_status_get(a_uint32_t dev_id, a_bool_t *enable) -{ - sw_error_t rv; - a_uint32_t val; - - HSL_DEV_ID_CHECK(dev_id); - - HSL_REG_FIELD_GET(rv, dev_id, CPU_PORT, 0, CPU_PORT_EN, - (a_uint8_t *) (&val), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - - if (1 == val) - { - *enable = A_TRUE; - } - else - { - *enable = A_FALSE; - } - - return SW_OK; -} - -static sw_error_t -_horus_pppoe_cmd_set(a_uint32_t dev_id, fal_fwd_cmd_t cmd) -{ - sw_error_t rv; - a_uint32_t val; - - HSL_DEV_ID_CHECK(dev_id); - - if (FAL_MAC_FRWRD == cmd) - { - val = 0; - } - else if (FAL_MAC_RDT_TO_CPU == cmd) - { - val = 1; - } - else - { - return SW_NOT_SUPPORTED; - } - - HSL_REG_FIELD_SET(rv, dev_id, QM_CTL, 0, PPPOE_RDT_EN, - (a_uint8_t *) (&val), sizeof (a_uint32_t)); - return rv; -} - -static sw_error_t -_horus_pppoe_cmd_get(a_uint32_t dev_id, fal_fwd_cmd_t * cmd) -{ - sw_error_t rv; - a_uint32_t val; - - HSL_DEV_ID_CHECK(dev_id); - - HSL_REG_FIELD_GET(rv, dev_id, QM_CTL, 0, PPPOE_RDT_EN, - (a_uint8_t *) (&val), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - - if (1 == val) - { - *cmd = FAL_MAC_RDT_TO_CPU; - } - else - { - *cmd = FAL_MAC_FRWRD; - } - - return SW_OK; -} - -static sw_error_t -_horus_pppoe_status_set(a_uint32_t dev_id, a_bool_t enable) -{ - sw_error_t rv; - a_uint32_t val; - - HSL_DEV_ID_CHECK(dev_id); - - if (A_TRUE == enable) - { - val = 1; - } - else if (A_FALSE == enable) - { - val = 0; - } - else - { - return SW_BAD_PARAM; - } - - HSL_REG_FIELD_SET(rv, dev_id, QM_CTL, 0, PPPOE_EN, - (a_uint8_t *) (&val), sizeof (a_uint32_t)); - return rv; -} - -static sw_error_t -_horus_pppoe_status_get(a_uint32_t dev_id, a_bool_t * enable) -{ - sw_error_t rv; - a_uint32_t val; - - HSL_DEV_ID_CHECK(dev_id); - - HSL_REG_FIELD_GET(rv, dev_id, QM_CTL, 0, PPPOE_EN, - (a_uint8_t *) (&val), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - - if (1 == val) - { - *enable = A_TRUE; - } - else - { - *enable = A_FALSE; - } - - return SW_OK; -} - -static sw_error_t -_horus_port_dhcp_set(a_uint32_t dev_id, fal_port_t port_id, a_bool_t enable) -{ - sw_error_t rv; - a_uint32_t val; - - HSL_DEV_ID_CHECK(dev_id); - - if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU)) - { - return SW_BAD_PARAM; - } - - if (A_TRUE == enable) - { - val = 1; - } - else if (A_FALSE == enable) - { - val = 0; - } - else - { - return SW_BAD_PARAM; - } - - HSL_REG_FIELD_SET(rv, dev_id, PORT_CTL, port_id, DHCP_EN, - (a_uint8_t *) (&val), sizeof (a_uint32_t)); - return rv; -} - -static sw_error_t -_horus_port_dhcp_get(a_uint32_t dev_id, fal_port_t port_id, a_bool_t * enable) -{ - sw_error_t rv; - a_uint32_t val; - - HSL_DEV_ID_CHECK(dev_id); - - if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU)) - { - return SW_BAD_PARAM; - } - - HSL_REG_FIELD_GET(rv, dev_id, PORT_CTL, port_id, DHCP_EN, - (a_uint8_t *) (&val), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - - if (1 == val) - { - *enable = A_TRUE; - } - else - { - *enable = A_FALSE; - } - - return SW_OK; -} - -static sw_error_t -_horus_arp_cmd_set(a_uint32_t dev_id, fal_fwd_cmd_t cmd) -{ - sw_error_t rv; - a_uint32_t val; - - HSL_DEV_ID_CHECK(dev_id); - - if (FAL_MAC_CPY_TO_CPU == cmd) - { - val = 0; - } - else if (FAL_MAC_RDT_TO_CPU == cmd) - { - val = 1; - } - else - { - return SW_NOT_SUPPORTED; - } - - HSL_REG_FIELD_SET(rv, dev_id, QM_CTL, 0, ARP_CMD, - (a_uint8_t *) (&val), sizeof (a_uint32_t)); - return rv; -} - -static sw_error_t -_horus_arp_cmd_get(a_uint32_t dev_id, fal_fwd_cmd_t * cmd) -{ - sw_error_t rv; - a_uint32_t val; - - HSL_DEV_ID_CHECK(dev_id); - - HSL_REG_FIELD_GET(rv, dev_id, QM_CTL, 0, ARP_CMD, - (a_uint8_t *) (&val), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - - if (0 == val) - { - *cmd = FAL_MAC_CPY_TO_CPU; - } - else - { - *cmd = FAL_MAC_RDT_TO_CPU; - } - - return SW_OK; -} - -static sw_error_t -_horus_eapol_cmd_set(a_uint32_t dev_id, fal_fwd_cmd_t cmd) -{ - sw_error_t rv; - a_uint32_t val; - - HSL_DEV_ID_CHECK(dev_id); - - if (FAL_MAC_CPY_TO_CPU == cmd) - { - val = 0; - } - else if (FAL_MAC_RDT_TO_CPU == cmd) - { - val = 1; - } - else - { - return SW_NOT_SUPPORTED; - } - - HSL_REG_FIELD_SET(rv, dev_id, QM_CTL, 0, EAPOL_CMD, - (a_uint8_t *) (&val), sizeof (a_uint32_t)); - return rv; -} - -static sw_error_t -_horus_eapol_cmd_get(a_uint32_t dev_id, fal_fwd_cmd_t * cmd) -{ - sw_error_t rv; - a_uint32_t val; - - HSL_DEV_ID_CHECK(dev_id); - - HSL_REG_FIELD_GET(rv, dev_id, QM_CTL, 0, EAPOL_CMD, - (a_uint8_t *) (&val), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - - if (0 == val) - { - *cmd = FAL_MAC_CPY_TO_CPU; - } - else - { - *cmd = FAL_MAC_RDT_TO_CPU; - } - - return SW_OK; -} - -static sw_error_t -_horus_eapol_status_set(a_uint32_t dev_id, a_uint32_t port_id, a_bool_t enable) -{ - a_uint32_t data; - sw_error_t rv; - - HSL_DEV_ID_CHECK(dev_id); - - if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU)) - { - return SW_BAD_PARAM; - } - - if (A_TRUE == enable) - { - data = 1; - } - else if (A_FALSE == enable) - { - data = 0; - } - else - { - return SW_BAD_PARAM; - } - - HSL_REG_FIELD_SET(rv, dev_id, PORT_CTL, port_id, EAPOL_EN, - (a_uint8_t *) (&data), sizeof (a_uint32_t)); - return rv; -} - -static sw_error_t -_horus_eapol_status_get(a_uint32_t dev_id, a_uint32_t port_id, a_bool_t *enable) -{ - a_uint32_t data; - sw_error_t rv; - - HSL_DEV_ID_CHECK(dev_id); - - if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU)) - { - return SW_BAD_PARAM; - } - - HSL_REG_FIELD_GET(rv, dev_id, PORT_CTL, port_id, EAPOL_EN, - (a_uint8_t *) (&data), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - - if (1 == data) - { - *enable = A_TRUE; - } - else - { - *enable = A_FALSE; - } - - return SW_OK; -} - -static sw_error_t -_horus_ripv1_status_set(a_uint32_t dev_id, a_bool_t enable) -{ - a_uint32_t data; - sw_error_t rv; - - HSL_DEV_ID_CHECK(dev_id); - - if (A_TRUE != hsl_port_prop_check(dev_id, 0, HSL_PP_INCL_CPU)) - { - return SW_BAD_PARAM; - } - - if (A_TRUE == enable) - { - data = 1; - } - else if (A_FALSE == enable) - { - data = 0; - } - else - { - return SW_BAD_PARAM; - } - - HSL_REG_FIELD_SET(rv, dev_id, QM_CTL, 0, RIP_CPY_EN, - (a_uint8_t *) (&data), sizeof (a_uint32_t)); - return rv; -} - -static sw_error_t -_horus_ripv1_status_get(a_uint32_t dev_id, a_bool_t *enable) -{ - a_uint32_t data; - sw_error_t rv; - - HSL_DEV_ID_CHECK(dev_id); - - if (A_TRUE != hsl_port_prop_check(dev_id, 0, HSL_PP_INCL_CPU)) - { - return SW_BAD_PARAM; - } - - HSL_REG_FIELD_GET(rv, dev_id, QM_CTL, 0, RIP_CPY_EN, - (a_uint8_t *) (&data), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - - if (1 == data) - { - *enable = A_TRUE; - } - else - { - *enable = A_FALSE; - } - - return SW_OK; -} - -/** - * @brief Set arp packets hardware acknowledgement status on a particular device. - * @param[in] dev_id device id - * @param[in] enable A_TRUE or A_FALSE - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -horus_arp_status_set(a_uint32_t dev_id, a_bool_t enable) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _horus_arp_status_set(dev_id, enable); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Get arp packets hardware acknowledgement status on a particular device. - * @param[in] dev_id device id - * @param[out] enable A_TRUE or A_FALSE - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -horus_arp_status_get(a_uint32_t dev_id, a_bool_t *enable) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _horus_arp_status_get(dev_id, enable); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Set max frame size which device can received on a particular device. - * @details Comments: - * The granularity of packets size is byte. - * @param[in] dev_id device id - * @param[in] size packet size - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -horus_frame_max_size_set(a_uint32_t dev_id, a_uint32_t size) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _horus_frame_max_size_set(dev_id, size); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Get max frame size which device can received on a particular device. - * @details Comments: - * The unit of packets size is byte. - * @param[in] dev_id device id - * @param[out] size packet size - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -horus_frame_max_size_get(a_uint32_t dev_id, a_uint32_t *size) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _horus_frame_max_size_get(dev_id, size); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Set forwarding command for packets which source address is unknown on a particular port. - * @details Comments: - * Particular device may only support parts of forwarding commands. - * @param[in] dev_id device id - * @param[in] port_id port id - * @param[in] cmd forwarding command - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -horus_port_unk_sa_cmd_set(a_uint32_t dev_id, fal_port_t port_id, - fal_fwd_cmd_t cmd) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _horus_port_unk_sa_cmd_set(dev_id, port_id, cmd); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Get forwarding command for packets which source address is unknown on a particular port. - * @param[in] dev_id device id - * @param[in] port_id port id - * @param[out] cmd forwarding command - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -horus_port_unk_sa_cmd_get(a_uint32_t dev_id, fal_port_t port_id, - fal_fwd_cmd_t * action) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _horus_port_unk_sa_cmd_get(dev_id, port_id, action); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Set flooding status of unknown unicast packets on a particular port. - * @details Comments: - * If enable unknown unicast packets filter on one port then unknown - * unicast packets can't flood out from this port. - * @param[in] dev_id device id - * @param[in] port_id port id - * @param[in] enable A_TRUE or A_FALSE - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -horus_port_unk_uc_filter_set(a_uint32_t dev_id, fal_port_t port_id, - a_bool_t enable) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _horus_port_unk_uc_filter_set(dev_id, port_id, enable); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Get flooding status of unknown unicast packets on a particular port. - * @param[in] dev_id device id - * @param[in] port_id port id - * @param[out] enable A_TRUE or A_FALSE - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -horus_port_unk_uc_filter_get(a_uint32_t dev_id, fal_port_t port_id, - a_bool_t * enable) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _horus_port_unk_uc_filter_get(dev_id, port_id, enable); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Set flooding status of unknown multicast packets on a particular port. - * @details Comments: - * If enable unknown multicast packets filter on one port then unknown - * multicast packets can't flood out from this port. - * @param[in] dev_id device id - * @param[in] port_id port id - * @param[in] enable A_TRUE or A_FALSE - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -horus_port_unk_mc_filter_set(a_uint32_t dev_id, fal_port_t port_id, - a_bool_t enable) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _horus_port_unk_mc_filter_set(dev_id, port_id, enable); - HSL_API_UNLOCK; - return rv; -} - -/** @brief Get flooding status of unknown multicast packets on a particular port. - * @param[in] dev_id device id - * @param[in] port_id port id - * @param[out] enable A_TRUE or A_FALSE - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -horus_port_unk_mc_filter_get(a_uint32_t dev_id, fal_port_t port_id, - a_bool_t * enable) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _horus_port_unk_mc_filter_get(dev_id, port_id, enable); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Set flooding status of broadcast packets on a particular port. - * @details Comments: - * If enable unknown multicast packets filter on one port then unknown - * multicast packets can't flood out from this port. - * @param[in] dev_id device id - * @param[in] port_id port id - * @param[in] enable A_TRUE or A_FALSE - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -horus_port_bc_filter_set(a_uint32_t dev_id, fal_port_t port_id, - a_bool_t enable) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _horus_port_bc_filter_set(dev_id, port_id, enable); - HSL_API_UNLOCK; - return rv; -} - -/** @brief Get flooding status of broadcast packets on a particular port. - * @param[in] dev_id device id - * @param[in] port_id port id - * @param[out] enable A_TRUE or A_FALSE - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -horus_port_bc_filter_get(a_uint32_t dev_id, fal_port_t port_id, - a_bool_t * enable) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _horus_port_bc_filter_get(dev_id, port_id, enable); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Set cpu port status on a particular device. - * @param[in] dev_id device id - * @param[in] enable A_TRUE or A_FALSE - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -horus_cpu_port_status_set(a_uint32_t dev_id, a_bool_t enable) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _horus_cpu_port_status_set(dev_id, enable); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Get cpu port status on a particular device. - * @param[in] dev_id device id - * @param[in] enable A_TRUE or A_FALSE - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -horus_cpu_port_status_get(a_uint32_t dev_id, a_bool_t *enable) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _horus_cpu_port_status_get(dev_id, enable); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Set pppoe packets forwarding command on a particular device. - * @details comments: - * Particular device may only support parts of forwarding commands. - * Ihis operation will take effect only after enabling pppoe packets - * hardware acknowledgement - * @param[in] dev_id device id - * @param[in] cmd forwarding command - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -horus_pppoe_cmd_set(a_uint32_t dev_id, fal_fwd_cmd_t cmd) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _horus_pppoe_cmd_set(dev_id, cmd); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Get pppoe packets forwarding command on a particular device. - * @param[in] dev_id device id - * @param[out] cmd forwarding command - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -horus_pppoe_cmd_get(a_uint32_t dev_id, fal_fwd_cmd_t * cmd) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _horus_pppoe_cmd_get(dev_id, cmd); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Set pppoe packets hardware acknowledgement status on particular device. - * @details comments: - * Particular device may only support parts of pppoe packets. - * @param[in] dev_id device id - * @param[in] enable A_TRUE or A_FALSE - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -horus_pppoe_status_set(a_uint32_t dev_id, a_bool_t enable) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _horus_pppoe_status_set(dev_id, enable); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Get pppoe packets hardware acknowledgement status on a particular device. - * @param[in] dev_id device id - * @param[out] enable A_TRUE or A_FALSE - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -horus_pppoe_status_get(a_uint32_t dev_id, a_bool_t * enable) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _horus_pppoe_status_get(dev_id, enable); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Set dhcp packets hardware acknowledgement status on a particular device. - * @param[in] dev_id device id - * @param[in] enable A_TRUE or A_FALSE - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -horus_port_dhcp_set(a_uint32_t dev_id, fal_port_t port_id, a_bool_t enable) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _horus_port_dhcp_set(dev_id, port_id, enable); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Get dhcp packets hardware acknowledgement status on particular device. - * @param[in] dev_id device id - * @param[out] enable A_TRUE or A_FALSE - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -horus_port_dhcp_get(a_uint32_t dev_id, fal_port_t port_id, a_bool_t * enable) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _horus_port_dhcp_get(dev_id, port_id, enable); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Set arp packets forwarding command on a particular device. - * @details comments: - * Particular device may only support parts of forwarding commands. - * Ihis operation will take effect only after enabling arp packets - * hardware acknowledgement - * @param[in] dev_id device id - * @param[in] cmd forwarding command - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -horus_arp_cmd_set(a_uint32_t dev_id, fal_fwd_cmd_t cmd) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _horus_arp_cmd_set(dev_id, cmd); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Get arp packets forwarding command on a particular device. - * @param[in] dev_id device id - * @param[out] cmd forwarding command - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -horus_arp_cmd_get(a_uint32_t dev_id, fal_fwd_cmd_t * cmd) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _horus_arp_cmd_get(dev_id, cmd); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Set eapol packets forwarding command on a particular device. - * @details comments: - * Particular device may only support parts of forwarding commands. - * Ihis operation will take effect only after enabling eapol packets - * hardware acknowledgement - * @param[in] dev_id device id - * @param[in] cmd forwarding command - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -horus_eapol_cmd_set(a_uint32_t dev_id, fal_fwd_cmd_t cmd) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _horus_eapol_cmd_set(dev_id, cmd); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Get eapol packets forwarding command on a particular device. - * @param[in] dev_id device id - * @param[out] cmd forwarding command - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -horus_eapol_cmd_get(a_uint32_t dev_id, fal_fwd_cmd_t * cmd) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _horus_eapol_cmd_get(dev_id, cmd); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Set eapol packets hardware acknowledgement status on a particular port. - * @param[in] dev_id device id - * @param[in] port_id port id - * @param[in] enable A_TRUE or A_FALSE - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -horus_eapol_status_set(a_uint32_t dev_id, a_uint32_t port_id, a_bool_t enable) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _horus_eapol_status_set(dev_id, port_id, enable); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Get eapol packets hardware acknowledgement status on a particular port. - * @param[in] dev_id device id - * @param[in] port_id port id - * @param[out] enable A_TRUE or A_FALSE - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -horus_eapol_status_get(a_uint32_t dev_id, a_uint32_t port_id, a_bool_t *enable) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _horus_eapol_status_get(dev_id, port_id, enable); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Set rip v1 packets hardware acknowledgement status on a particular port. - * @param[in] dev_id device id - * @param[in] enable A_TRUE or A_FALSE - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -horus_ripv1_status_set(a_uint32_t dev_id, a_bool_t enable) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _horus_ripv1_status_set(dev_id, enable); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Get rip v1 packets hardware acknowledgement status on a particular port. - * @param[in] dev_id device id - * @param[out] enable A_TRUE or A_FALSE - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -horus_ripv1_status_get(a_uint32_t dev_id, a_bool_t *enable) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _horus_ripv1_status_get(dev_id, enable); - HSL_API_UNLOCK; - return rv; -} - -sw_error_t -horus_misc_init(a_uint32_t dev_id) -{ - HSL_DEV_ID_CHECK(dev_id); - -#ifndef HSL_STANDALONG - { - hsl_api_t *p_api; - - SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id)); - - p_api->arp_status_set = horus_arp_status_set; - p_api->arp_status_get = horus_arp_status_get; - p_api->frame_max_size_set = horus_frame_max_size_set; - p_api->frame_max_size_get = horus_frame_max_size_get; - p_api->port_unk_sa_cmd_set = horus_port_unk_sa_cmd_set; - p_api->port_unk_sa_cmd_get = horus_port_unk_sa_cmd_get; - p_api->port_unk_uc_filter_set = horus_port_unk_uc_filter_set; - p_api->port_unk_uc_filter_get = horus_port_unk_uc_filter_get; - p_api->port_unk_mc_filter_set = horus_port_unk_mc_filter_set; - p_api->port_unk_mc_filter_get = horus_port_unk_mc_filter_get; - p_api->port_bc_filter_set = horus_port_bc_filter_set; - p_api->port_bc_filter_get = horus_port_bc_filter_get; - p_api->cpu_port_status_set = horus_cpu_port_status_set; - p_api->cpu_port_status_get = horus_cpu_port_status_get; - p_api->pppoe_cmd_set = horus_pppoe_cmd_set; - p_api->pppoe_cmd_get = horus_pppoe_cmd_get; - p_api->pppoe_status_set = horus_pppoe_status_set; - p_api->pppoe_status_get = horus_pppoe_status_get; - p_api->port_dhcp_set = horus_port_dhcp_set; - p_api->port_dhcp_get = horus_port_dhcp_get; - p_api->arp_cmd_set = horus_arp_cmd_set; - p_api->arp_cmd_get = horus_arp_cmd_get; - p_api->eapol_cmd_set = horus_eapol_cmd_set; - p_api->eapol_cmd_get = horus_eapol_cmd_get; - p_api->eapol_status_set = horus_eapol_status_set; - p_api->eapol_status_get = horus_eapol_status_get; - p_api->ripv1_status_set = horus_ripv1_status_set; - p_api->ripv1_status_get = horus_ripv1_status_get; - } -#endif - - return SW_OK; -} - -/** - * @} - */ diff --git a/feeds/ipq807x/qca-ssdk/src/src/hsl/horus/horus_port_ctrl.c b/feeds/ipq807x/qca-ssdk/src/src/hsl/horus/horus_port_ctrl.c deleted file mode 100755 index 75fcee817..000000000 --- a/feeds/ipq807x/qca-ssdk/src/src/hsl/horus/horus_port_ctrl.c +++ /dev/null @@ -1,1061 +0,0 @@ -/* - * Copyright (c) 2012, 2015,The Linux Foundation. All rights reserved. - * Permission to use, copy, modify, and/or distribute this software for - * any purpose with or without fee is hereby granted, provided that the - * above copyright notice and this permission notice appear in all copies. - * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES - * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR - * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES - * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN - * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT - * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. - */ - - -/** - * @defgroup horus_port_ctrl HORUS_PORT_CONTROL - * @{ - */ -#include "sw.h" -#include "hsl.h" -#include "hsl_dev.h" -#include "hsl_port_prop.h" -#include "horus_port_ctrl.h" -#include "horus_reg.h" -#include "hsl_phy.h" - -static sw_error_t -_horus_port_duplex_set(a_uint32_t dev_id, fal_port_t port_id, - fal_port_duplex_t duplex) -{ - sw_error_t rv; - a_uint32_t phy_id = 0; - a_uint32_t reg_save = 0; - a_uint32_t reg_val = 0; - hsl_phy_ops_t *phy_drv; - - HSL_DEV_ID_CHECK(dev_id); - - if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_PHY)) - { - return SW_BAD_PARAM; - } - - SW_RTN_ON_NULL (phy_drv = hsl_phy_api_ops_get (dev_id)); - if (NULL == phy_drv->phy_duplex_set) - return SW_NOT_SUPPORTED; - - if (FAL_DUPLEX_BUTT <= duplex) - { - return SW_BAD_PARAM; - } - - rv = hsl_port_prop_get_phyid(dev_id, port_id, &phy_id); - SW_RTN_ON_ERROR(rv); - - //save reg value - HSL_REG_ENTRY_GET(rv, dev_id, PORT_STATUS, port_id, - (a_uint8_t *) (®_val), sizeof (a_uint32_t)); - reg_save = reg_val; - - SW_SET_REG_BY_FIELD(PORT_STATUS, LINK_EN, 0, reg_val); - SW_SET_REG_BY_FIELD(PORT_STATUS, RXMAC_EN, 0, reg_val); - SW_SET_REG_BY_FIELD(PORT_STATUS, TXMAC_EN, 0, reg_val); - - //set mac be config by sw and turn off RX TX MAC_EN - HSL_REG_ENTRY_SET(rv, dev_id, PORT_STATUS, port_id, - (a_uint8_t *) (®_val), sizeof (a_uint32_t)); - - rv = phy_drv->phy_duplex_set(dev_id, phy_id, duplex); - - //retore reg value - HSL_REG_ENTRY_SET(rv, dev_id, PORT_STATUS, port_id, - (a_uint8_t *) (®_save), sizeof (a_uint32_t)); - - return rv; -} - -static sw_error_t -_horus_port_duplex_get(a_uint32_t dev_id, fal_port_t port_id, - fal_port_duplex_t * pduplex) -{ - sw_error_t rv; - a_uint32_t phy_id; - hsl_phy_ops_t *phy_drv; - - HSL_DEV_ID_CHECK(dev_id); - - if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_PHY)) - { - return SW_BAD_PARAM; - } - - SW_RTN_ON_NULL (phy_drv = hsl_phy_api_ops_get (dev_id)); - if (NULL == phy_drv->phy_duplex_get) - return SW_NOT_SUPPORTED; - - rv = hsl_port_prop_get_phyid(dev_id, port_id, &phy_id); - SW_RTN_ON_ERROR(rv); - - rv = phy_drv->phy_duplex_get(dev_id, phy_id, pduplex); - return rv; -} - -static sw_error_t -_horus_port_speed_set(a_uint32_t dev_id, fal_port_t port_id, - fal_port_speed_t speed) -{ - sw_error_t rv; - a_uint32_t phy_id = 0; - hsl_phy_ops_t *phy_drv; - - HSL_DEV_ID_CHECK(dev_id); - - if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_PHY)) - { - return SW_BAD_PARAM; - } - - SW_RTN_ON_NULL (phy_drv = hsl_phy_api_ops_get (dev_id)); - if (NULL == phy_drv->phy_speed_set) - return SW_NOT_SUPPORTED; - - rv = hsl_port_prop_get_phyid(dev_id, port_id, &phy_id); - SW_RTN_ON_ERROR(rv); - - if (FAL_SPEED_100 < speed) - { - return SW_BAD_PARAM; - } - - rv = phy_drv->phy_speed_set(dev_id, phy_id, speed); - - return rv; -} - -static sw_error_t -_horus_port_speed_get(a_uint32_t dev_id, fal_port_t port_id, - fal_port_speed_t * pspeed) -{ - sw_error_t rv; - a_uint32_t phy_id; - hsl_phy_ops_t *phy_drv; - - HSL_DEV_ID_CHECK(dev_id); - - if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_PHY)) - { - return SW_BAD_PARAM; - } - - SW_RTN_ON_NULL (phy_drv = hsl_phy_api_ops_get (dev_id)); - if (NULL == phy_drv->phy_speed_get) - return SW_NOT_SUPPORTED; - - rv = hsl_port_prop_get_phyid(dev_id, port_id, &phy_id); - SW_RTN_ON_ERROR(rv); - - rv = phy_drv->phy_speed_get(dev_id, phy_id, pspeed); - - return rv; -} - -static sw_error_t -_horus_port_autoneg_status_get(a_uint32_t dev_id, fal_port_t port_id, - a_bool_t * status) -{ - a_uint32_t phy_id; - sw_error_t rv; - hsl_phy_ops_t *phy_drv; - - HSL_DEV_ID_CHECK(dev_id); - - if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_PHY)) - { - return SW_BAD_PARAM; - } - - SW_RTN_ON_NULL (phy_drv = hsl_phy_api_ops_get (dev_id)); - if (NULL == phy_drv->phy_autoneg_status_get) - return SW_NOT_SUPPORTED; - - rv = hsl_port_prop_get_phyid(dev_id, port_id, &phy_id); - SW_RTN_ON_ERROR(rv); - - *status = phy_drv->phy_autoneg_status_get(dev_id, phy_id); - - return SW_OK; -} - -static sw_error_t -_horus_port_autoneg_enable(a_uint32_t dev_id, fal_port_t port_id) -{ - sw_error_t rv; - a_uint32_t phy_id; - hsl_phy_ops_t *phy_drv; - - HSL_DEV_ID_CHECK(dev_id); - - if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_PHY)) - { - return SW_BAD_PARAM; - } - - SW_RTN_ON_NULL (phy_drv = hsl_phy_api_ops_get (dev_id)); - if (NULL == phy_drv->phy_autoneg_enable_set) - return SW_NOT_SUPPORTED; - - rv = hsl_port_prop_get_phyid(dev_id, port_id, &phy_id); - SW_RTN_ON_ERROR(rv); - - rv = phy_drv->phy_autoneg_enable_set(dev_id, phy_id); - return rv; -} - -static sw_error_t -_horus_port_autoneg_restart(a_uint32_t dev_id, fal_port_t port_id) -{ - sw_error_t rv; - a_uint32_t phy_id; - hsl_phy_ops_t *phy_drv; - - HSL_DEV_ID_CHECK(dev_id); - - if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_PHY)) - { - return SW_BAD_PARAM; - } - - SW_RTN_ON_NULL (phy_drv = hsl_phy_api_ops_get (dev_id)); - if (NULL == phy_drv->phy_restart_autoneg) - return SW_NOT_SUPPORTED; - - rv = hsl_port_prop_get_phyid(dev_id, port_id, &phy_id); - SW_RTN_ON_ERROR(rv); - - rv = phy_drv->phy_restart_autoneg(dev_id, phy_id); - return rv; -} - -static sw_error_t -_horus_port_autoneg_adv_set(a_uint32_t dev_id, fal_port_t port_id, - a_uint32_t autoadv) -{ - sw_error_t rv; - a_uint32_t phy_id; - hsl_phy_ops_t *phy_drv; - - HSL_DEV_ID_CHECK(dev_id); - - if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_PHY)) - { - return SW_BAD_PARAM; - } - - SW_RTN_ON_NULL (phy_drv = hsl_phy_api_ops_get (dev_id)); - if (NULL == phy_drv->phy_autoneg_adv_set) - return SW_NOT_SUPPORTED; - - rv = hsl_port_prop_get_phyid(dev_id, port_id, &phy_id); - SW_RTN_ON_ERROR(rv); - - rv = phy_drv->phy_autoneg_adv_set(dev_id, phy_id, autoadv); - SW_RTN_ON_ERROR(rv); - - return SW_OK; -} - -static sw_error_t -_horus_port_autoneg_adv_get(a_uint32_t dev_id, fal_port_t port_id, - a_uint32_t * autoadv) -{ - sw_error_t rv; - a_uint32_t phy_id; - hsl_phy_ops_t *phy_drv; - - HSL_DEV_ID_CHECK(dev_id); - - if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_PHY)) - { - return SW_BAD_PARAM; - } - - SW_RTN_ON_NULL (phy_drv = hsl_phy_api_ops_get (dev_id)); - if (NULL == phy_drv->phy_autoneg_adv_get) - return SW_NOT_SUPPORTED; - - rv = hsl_port_prop_get_phyid(dev_id, port_id, &phy_id); - SW_RTN_ON_ERROR(rv); - - *autoadv = 0; - rv = phy_drv->phy_autoneg_adv_get(dev_id, phy_id, autoadv); - SW_RTN_ON_ERROR(rv); - - return SW_OK; -} - -static sw_error_t -_horus_port_hdr_status_set(a_uint32_t dev_id, fal_port_t port_id, - a_bool_t enable) -{ - sw_error_t rv; - a_uint32_t val; - - HSL_DEV_ID_CHECK(dev_id); - - if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU)) - { - return SW_BAD_PARAM; - } - - if (A_TRUE == enable) - { - val = 1; - } - else if (A_FALSE == enable) - { - val = 0; - } - else - { - return SW_BAD_PARAM; - } - - HSL_REG_FIELD_SET(rv, dev_id, PORT_CTL, port_id, HEAD_EN, - (a_uint8_t *) (&val), sizeof (a_uint32_t)); - - return rv; -} - -static sw_error_t -_horus_port_hdr_status_get(a_uint32_t dev_id, fal_port_t port_id, - a_bool_t * enable) -{ - sw_error_t rv; - a_uint32_t val; - - HSL_DEV_ID_CHECK(dev_id); - - if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU)) - { - return SW_BAD_PARAM; - } - - HSL_REG_FIELD_GET(rv, dev_id, PORT_CTL, port_id, HEAD_EN, - (a_uint8_t *) (&val), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - - if (1 == val) - { - *enable = A_TRUE; - } - else - { - *enable = A_FALSE; - } - - return rv; -} - -static sw_error_t -_horus_port_flowctrl_set(a_uint32_t dev_id, fal_port_t port_id, a_bool_t enable) -{ - sw_error_t rv; - a_uint32_t val, force, reg; - - if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU)) - { - return SW_BAD_PARAM; - } - - if (A_TRUE == enable) - { - val = 1; - } - else if (A_FALSE == enable) - { - val = 0; - } - else - { - return SW_BAD_PARAM; - } - - HSL_REG_ENTRY_GET(rv, dev_id, PORT_STATUS, port_id, - (a_uint8_t *) (®), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - - SW_GET_FIELD_BY_REG(PORT_STATUS, FLOW_LINK_EN, force, reg); - if (force) - { - /* flow control isn't in force mode so can't set */ - return SW_DISABLE; - } - - SW_SET_REG_BY_FIELD(PORT_STATUS, RX_FLOW_EN, val, reg); - SW_SET_REG_BY_FIELD(PORT_STATUS, TX_FLOW_EN, val, reg); - SW_SET_REG_BY_FIELD(PORT_STATUS, TX_HALF_FLOW_EN, val, reg); - - HSL_REG_ENTRY_SET(rv, dev_id, PORT_STATUS, port_id, - (a_uint8_t *) (®), sizeof (a_uint32_t)); - return rv; -} - -static sw_error_t -_horus_port_flowctrl_get(a_uint32_t dev_id, fal_port_t port_id, - a_bool_t * enable) -{ - sw_error_t rv; - a_uint32_t tx, rx, reg; - - if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU)) - { - return SW_BAD_PARAM; - } - - HSL_REG_ENTRY_GET(rv, dev_id, PORT_STATUS, port_id, - (a_uint8_t *) (®), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - - SW_GET_FIELD_BY_REG(PORT_STATUS, RX_FLOW_EN, rx, reg); - SW_GET_FIELD_BY_REG(PORT_STATUS, TX_FLOW_EN, tx, reg); - - if (1 == rx) - { - *enable = A_TRUE; - } - else - { - *enable = A_FALSE; - } - - return SW_OK; -} - -static sw_error_t -_horus_port_flowctrl_forcemode_set(a_uint32_t dev_id, fal_port_t port_id, - a_bool_t enable) -{ - sw_error_t rv; - a_uint32_t force, reg; - - if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU)) - { - return SW_BAD_PARAM; - } - - HSL_REG_ENTRY_GET(rv, dev_id, PORT_STATUS, port_id, - (a_uint8_t *) (®), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - - SW_GET_FIELD_BY_REG(PORT_STATUS, FLOW_LINK_EN, force, reg); - if (force != (a_uint32_t) enable) - { - return SW_OK; - } - - if (A_TRUE == enable) - { - SW_SET_REG_BY_FIELD(PORT_STATUS, FLOW_LINK_EN, 0, reg); - SW_SET_REG_BY_FIELD(PORT_STATUS, TX_FLOW_EN, 0, reg); - } - else if (A_FALSE == enable) - { - SW_SET_REG_BY_FIELD(PORT_STATUS, FLOW_LINK_EN, 1, reg); - } - else - { - return SW_BAD_PARAM; - } - SW_SET_REG_BY_FIELD(PORT_STATUS, TX_HALF_FLOW_EN, 0, reg); - - HSL_REG_ENTRY_SET(rv, dev_id, PORT_STATUS, port_id, - (a_uint8_t *) (®), sizeof (a_uint32_t)); - return rv; -} - -static sw_error_t -_horus_port_flowctrl_forcemode_get(a_uint32_t dev_id, fal_port_t port_id, - a_bool_t * enable) -{ - sw_error_t rv; - a_uint32_t force, reg; - - if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU)) - { - return SW_BAD_PARAM; - } - - HSL_REG_ENTRY_GET(rv, dev_id, PORT_STATUS, port_id, - (a_uint8_t *) (®), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - - SW_GET_FIELD_BY_REG(PORT_STATUS, FLOW_LINK_EN, force, reg); - if (0 == force) - { - *enable = A_TRUE; - } - else - { - *enable = A_FALSE; - } - - return SW_OK; -} - -static sw_error_t -_horus_port_powersave_set(a_uint32_t dev_id, fal_port_t port_id, - a_bool_t enable) -{ - sw_error_t rv; - a_uint32_t phy_id = 0; - hsl_phy_ops_t *phy_drv; - - HSL_DEV_ID_CHECK(dev_id); - - if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_PHY)) - { - return SW_BAD_PARAM; - } - - SW_RTN_ON_NULL (phy_drv = hsl_phy_api_ops_get (dev_id)); - if (NULL == phy_drv->phy_powersave_set) - return SW_NOT_SUPPORTED; - - rv = hsl_port_prop_get_phyid(dev_id, port_id, &phy_id); - SW_RTN_ON_ERROR(rv); - - rv = phy_drv->phy_powersave_set(dev_id, phy_id, enable); - - return rv; -} - -static sw_error_t -_horus_port_powersave_get(a_uint32_t dev_id, fal_port_t port_id, - a_bool_t *enable) -{ - sw_error_t rv; - a_uint32_t phy_id = 0; - hsl_phy_ops_t *phy_drv; - - HSL_DEV_ID_CHECK(dev_id); - - if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_PHY)) - { - return SW_BAD_PARAM; - } - - SW_RTN_ON_NULL (phy_drv = hsl_phy_api_ops_get (dev_id)); - if (NULL == phy_drv->phy_powersave_get) - return SW_NOT_SUPPORTED; - - rv = hsl_port_prop_get_phyid(dev_id, port_id, &phy_id); - SW_RTN_ON_ERROR(rv); - - rv = phy_drv->phy_powersave_get(dev_id, phy_id, enable); - - return rv; -} - -static sw_error_t -_horus_port_hibernate_set(a_uint32_t dev_id, fal_port_t port_id, - a_bool_t enable) -{ - sw_error_t rv; - a_uint32_t phy_id = 0; - hsl_phy_ops_t *phy_drv; - - HSL_DEV_ID_CHECK(dev_id); - - if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_PHY)) - { - return SW_BAD_PARAM; - } - - SW_RTN_ON_NULL (phy_drv = hsl_phy_api_ops_get (dev_id)); - if (NULL == phy_drv->phy_hibernation_set) - return SW_NOT_SUPPORTED; - - rv = hsl_port_prop_get_phyid(dev_id, port_id, &phy_id); - SW_RTN_ON_ERROR(rv); - - rv = phy_drv->phy_hibernation_set(dev_id, phy_id, enable); - - return rv; -} - -static sw_error_t -_horus_port_hibernate_get(a_uint32_t dev_id, fal_port_t port_id, - a_bool_t *enable) -{ - sw_error_t rv; - a_uint32_t phy_id = 0; - hsl_phy_ops_t *phy_drv; - - HSL_DEV_ID_CHECK(dev_id); - - if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_PHY)) - { - return SW_BAD_PARAM; - } - - SW_RTN_ON_NULL (phy_drv = hsl_phy_api_ops_get (dev_id)); - if (NULL == phy_drv->phy_hibernation_get) - return SW_NOT_SUPPORTED; - - rv = hsl_port_prop_get_phyid(dev_id, port_id, &phy_id); - SW_RTN_ON_ERROR(rv); - - rv = phy_drv->phy_hibernation_get(dev_id, phy_id, enable); - - return rv; -} - -static sw_error_t -_horus_port_cdt(a_uint32_t dev_id, fal_port_t port_id, a_uint32_t mdi_pair, - fal_cable_status_t *cable_status, a_uint32_t *cable_len) -{ - sw_error_t rv; - a_uint32_t phy_id = 0; - hsl_phy_ops_t *phy_drv; - - HSL_DEV_ID_CHECK(dev_id); - - if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_PHY)) - { - return SW_BAD_PARAM; - } - - SW_RTN_ON_NULL (phy_drv = hsl_phy_api_ops_get (dev_id)); - if (NULL == phy_drv->phy_cdt) - return SW_NOT_SUPPORTED; - - rv = hsl_port_prop_get_phyid(dev_id, port_id, &phy_id); - SW_RTN_ON_ERROR(rv); - - rv = phy_drv->phy_cdt(dev_id, phy_id, mdi_pair, cable_status, cable_len); - - return rv; -} - -/** - * @brief Set duplex mode on a particular port. - * @param[in] dev_id device id - * @param[in] port_id port id - * @param[in] duplex duplex mode - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -horus_port_duplex_set(a_uint32_t dev_id, fal_port_t port_id, - fal_port_duplex_t duplex) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _horus_port_duplex_set(dev_id, port_id, duplex); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Get duplex mode on a particular port. - * @param[in] dev_id device id - * @param[in] port_id port id - * @param[out] duplex duplex mode - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -horus_port_duplex_get(a_uint32_t dev_id, fal_port_t port_id, - fal_port_duplex_t * pduplex) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _horus_port_duplex_get(dev_id, port_id, pduplex); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Set speed on a particular port. - * @param[in] dev_id device id - * @param[in] port_id port id - * @param[in] speed port speed - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -horus_port_speed_set(a_uint32_t dev_id, fal_port_t port_id, - fal_port_speed_t speed) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _horus_port_speed_set(dev_id, port_id, speed); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Get speed on a particular port. - * @param[in] dev_id device id - * @param[in] port_id port id - * @param[out] speed port speed - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -horus_port_speed_get(a_uint32_t dev_id, fal_port_t port_id, - fal_port_speed_t * pspeed) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _horus_port_speed_get(dev_id, port_id, pspeed); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Get auto negotiation status on a particular port. - * @param[in] dev_id device id - * @param[in] port_id port id - * @param[out] status A_TRUE or A_FALSE - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -horus_port_autoneg_status_get(a_uint32_t dev_id, fal_port_t port_id, - a_bool_t * status) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _horus_port_autoneg_status_get(dev_id, port_id, status); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Enable auto negotiation status on a particular port. - * @param[in] dev_id device id - * @param[in] port_id port id - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -horus_port_autoneg_enable(a_uint32_t dev_id, fal_port_t port_id) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _horus_port_autoneg_enable(dev_id, port_id); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Restart auto negotiation procedule on a particular port. - * @param[in] dev_id device id - * @param[in] port_id port id - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -horus_port_autoneg_restart(a_uint32_t dev_id, fal_port_t port_id) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _horus_port_autoneg_restart(dev_id, port_id); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Set auto negotiation advtisement ability on a particular port. - * @details Comments: - * auto negotiation advtisement ability is defined by macro such as - * FAL_PHY_ADV_10T_HD, FAL_PHY_ADV_PAUSE... - * @param[in] dev_id device id - * @param[in] port_id port id - * @param[in] autoadv auto negotiation advtisement ability bit map - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -horus_port_autoneg_adv_set(a_uint32_t dev_id, fal_port_t port_id, - a_uint32_t autoadv) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _horus_port_autoneg_adv_set(dev_id, port_id, autoadv); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Get auto negotiation advtisement ability on a particular port. - * @param[in] dev_id device id - * @param[in] port_id port id - * @param[out] autoadv auto negotiation advtisement ability bit map - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -horus_port_autoneg_adv_get(a_uint32_t dev_id, fal_port_t port_id, - a_uint32_t * autoadv) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _horus_port_autoneg_adv_get(dev_id, port_id, autoadv); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Set status of Atheros header packets parsed on a particular port. - * @param[in] dev_id device id - * @param[in] port_id port id - * @param[in] enable A_TRUE or A_FALSE - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -horus_port_hdr_status_set(a_uint32_t dev_id, fal_port_t port_id, - a_bool_t enable) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _horus_port_hdr_status_set(dev_id, port_id, enable); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Get status of Atheros header packets parsed on a particular port. - * @param[in] dev_id device id - * @param[in] port_id port id - * @param[out] enable A_TRUE or A_FALSE - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -horus_port_hdr_status_get(a_uint32_t dev_id, fal_port_t port_id, - a_bool_t * enable) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _horus_port_hdr_status_get(dev_id, port_id, enable); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Set flow control status on a particular port. - * @param[in] dev_id device id - * @param[in] port_id port id - * @param[in] enable A_TRUE or A_FALSE - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -horus_port_flowctrl_set(a_uint32_t dev_id, fal_port_t port_id, a_bool_t enable) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _horus_port_flowctrl_set(dev_id, port_id, enable); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Get flow control status on a particular port. - * @param[in] dev_id device id - * @param[in] port_id port id - * @param[out] enable A_TRUE or A_FALSE - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -horus_port_flowctrl_get(a_uint32_t dev_id, fal_port_t port_id, - a_bool_t * enable) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _horus_port_flowctrl_get(dev_id, port_id, enable); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Set flow control force mode on a particular port. - * @param[in] dev_id device id - * @param[in] port_id port id - * @param[out] enable A_TRUE or A_FALSE - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -horus_port_flowctrl_forcemode_set(a_uint32_t dev_id, fal_port_t port_id, - a_bool_t enable) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _horus_port_flowctrl_forcemode_set(dev_id, port_id, enable); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Get flow control force mode on a particular port. - * @param[in] dev_id device id - * @param[in] port_id port id - * @param[out] enable A_TRUE or A_FALSE - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -horus_port_flowctrl_forcemode_get(a_uint32_t dev_id, fal_port_t port_id, - a_bool_t * enable) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _horus_port_flowctrl_forcemode_get(dev_id, port_id, enable); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Set powersaving status on a particular port. - * @param[in] dev_id device id - * @param[in] port_id port id - * @param[out] enable A_TRUE or A_FALSE - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -horus_port_powersave_set(a_uint32_t dev_id, fal_port_t port_id, - a_bool_t enable) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _horus_port_powersave_set(dev_id, port_id, enable); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Get powersaving status on a particular port. - * @param[in] dev_id device id - * @param[in] port_id port id - * @param[out] enable A_TRUE or A_FALSE - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -horus_port_powersave_get(a_uint32_t dev_id, fal_port_t port_id, - a_bool_t *enable) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _horus_port_powersave_get(dev_id, port_id, enable); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Set hibernate status on a particular port. - * @param[in] dev_id device id - * @param[in] port_id port id - * @param[out] enable A_TRUE or A_FALSE - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -horus_port_hibernate_set(a_uint32_t dev_id, fal_port_t port_id, - a_bool_t enable) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _horus_port_hibernate_set(dev_id, port_id, enable); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Get hibernate status on a particular port. - * @param[in] dev_id device id - * @param[in] port_id port id - * @param[out] enable A_TRUE or A_FALSE - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -horus_port_hibernate_get(a_uint32_t dev_id, fal_port_t port_id, - a_bool_t *enable) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _horus_port_hibernate_get(dev_id, port_id, enable); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Run cable diagnostic test on a particular port. - * @param[in] dev_id device id - * @param[in] port_id port id - * @param[in] mdi_pair mdi pair id - * @param[out] cable_status cable status - * @param[out] cable_len cable len - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -horus_port_cdt(a_uint32_t dev_id, fal_port_t port_id, a_uint32_t mdi_pair, - fal_cable_status_t *cable_status, a_uint32_t *cable_len) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _horus_port_cdt(dev_id, port_id, mdi_pair, cable_status, cable_len); - HSL_API_UNLOCK; - return rv; -} - -sw_error_t -horus_port_ctrl_init(a_uint32_t dev_id) -{ - HSL_DEV_ID_CHECK(dev_id); - -#ifndef HSL_STANDALONG - { - hsl_api_t *p_api; - - SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id)); - - p_api->port_duplex_get = horus_port_duplex_get; - p_api->port_duplex_set = horus_port_duplex_set; - p_api->port_speed_get = horus_port_speed_get; - p_api->port_speed_set = horus_port_speed_set; - p_api->port_autoneg_status_get = horus_port_autoneg_status_get; - p_api->port_autoneg_enable = horus_port_autoneg_enable; - p_api->port_autoneg_restart = horus_port_autoneg_restart; - p_api->port_autoneg_adv_get = horus_port_autoneg_adv_get; - p_api->port_autoneg_adv_set = horus_port_autoneg_adv_set; - p_api->port_hdr_status_set = horus_port_hdr_status_set; - p_api->port_hdr_status_get = horus_port_hdr_status_get; - p_api->port_flowctrl_set = horus_port_flowctrl_set; - p_api->port_flowctrl_get = horus_port_flowctrl_get; - p_api->port_flowctrl_forcemode_set = horus_port_flowctrl_forcemode_set; - p_api->port_flowctrl_forcemode_get = horus_port_flowctrl_forcemode_get; - p_api->port_powersave_set = horus_port_powersave_set; - p_api->port_powersave_get = horus_port_powersave_get; - p_api->port_hibernate_set = horus_port_hibernate_set; - p_api->port_hibernate_get = horus_port_hibernate_get; - p_api->port_cdt = horus_port_cdt; - } -#endif - - return SW_OK; -} - -/** - * @} - */ diff --git a/feeds/ipq807x/qca-ssdk/src/src/hsl/horus/horus_portvlan.c b/feeds/ipq807x/qca-ssdk/src/src/hsl/horus/horus_portvlan.c deleted file mode 100755 index 1bf9f9822..000000000 --- a/feeds/ipq807x/qca-ssdk/src/src/hsl/horus/horus_portvlan.c +++ /dev/null @@ -1,1184 +0,0 @@ -/* - * Copyright (c) 2012, The Linux Foundation. All rights reserved. - * Permission to use, copy, modify, and/or distribute this software for - * any purpose with or without fee is hereby granted, provided that the - * above copyright notice and this permission notice appear in all copies. - * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES - * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR - * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES - * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN - * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT - * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. - */ - - -/** - * @defgroup horus_port_vlan HORUS_PORT_VLAN - * @{ - */ -#include "sw.h" -#include "hsl.h" -#include "hsl_dev.h" -#include "hsl_port_prop.h" -#include "horus_portvlan.h" -#include "horus_reg.h" - -#define MAX_VLAN_ID 4095 - -static sw_error_t -_horus_port_1qmode_set(a_uint32_t dev_id, fal_port_t port_id, - fal_pt_1qmode_t port_1qmode) -{ - sw_error_t rv; - a_uint32_t regval[FAL_1Q_MODE_BUTT] = { 0, 3, 2, 1 }; - - HSL_DEV_ID_CHECK(dev_id); - - if (A_FALSE == hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU)) - { - return SW_BAD_PARAM; - } - - if (FAL_1Q_MODE_BUTT <= port_1qmode) - { - return SW_BAD_PARAM; - } - - HSL_REG_FIELD_SET(rv, dev_id, PORT_BASE_VLAN, port_id, DOT1Q_MODE, - (a_uint8_t *) (®val[port_1qmode]), - sizeof (a_uint32_t)); - - return rv; - -} - -static sw_error_t -_horus_port_1qmode_get(a_uint32_t dev_id, fal_port_t port_id, - fal_pt_1qmode_t * pport_1qmode) -{ - sw_error_t rv; - a_uint32_t regval = 0; - fal_pt_1qmode_t retval[4] = { FAL_1Q_DISABLE, FAL_1Q_FALLBACK, - FAL_1Q_CHECK, FAL_1Q_SECURE - }; - - HSL_DEV_ID_CHECK(dev_id); - - if (A_FALSE == hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU)) - { - return SW_BAD_PARAM; - } - - SW_RTN_ON_NULL(pport_1qmode); - - HSL_REG_FIELD_GET(rv, dev_id, PORT_BASE_VLAN, port_id, DOT1Q_MODE, - (a_uint8_t *) (®val), sizeof (a_uint32_t)); - - SW_RTN_ON_ERROR(rv); - - *pport_1qmode = retval[regval & 0x3]; - - return SW_OK; - -} - -static sw_error_t -_horus_port_egvlanmode_set(a_uint32_t dev_id, fal_port_t port_id, - fal_pt_1q_egmode_t port_egvlanmode) -{ - sw_error_t rv; - a_uint32_t regval[FAL_EG_MODE_BUTT] = { 0, 1, 2, 3}; - - HSL_DEV_ID_CHECK(dev_id); - - if (A_FALSE == hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU)) - { - return SW_BAD_PARAM; - } - - if (FAL_EG_MODE_BUTT <= port_egvlanmode) - { - return SW_BAD_PARAM; - } - - HSL_REG_FIELD_SET(rv, dev_id, PORT_CTL, port_id, EG_VLAN_MODE, - (a_uint8_t *) (®val[port_egvlanmode]), - sizeof (a_uint32_t)); - - return rv; - -} - -static sw_error_t -_horus_port_egvlanmode_get(a_uint32_t dev_id, fal_port_t port_id, - fal_pt_1q_egmode_t * pport_egvlanmode) -{ - sw_error_t rv; - a_uint32_t regval = 0; - fal_pt_1q_egmode_t retval[4] = { FAL_EG_UNMODIFIED, FAL_EG_UNTAGGED, - FAL_EG_TAGGED, FAL_EG_HYBRID - }; - - HSL_DEV_ID_CHECK(dev_id); - - if (A_FALSE == hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU)) - { - return SW_BAD_PARAM; - } - - SW_RTN_ON_NULL(pport_egvlanmode); - - HSL_REG_FIELD_GET(rv, dev_id, PORT_CTL, port_id, EG_VLAN_MODE, - (a_uint8_t *) (®val), sizeof (a_uint32_t)); - - SW_RTN_ON_ERROR(rv); - - *pport_egvlanmode = retval[regval & 0x3]; - - return SW_OK; - -} - -static sw_error_t -_horus_portvlan_member_add(a_uint32_t dev_id, fal_port_t port_id, - a_uint32_t mem_port_id) -{ - sw_error_t rv; - a_uint32_t regval = 0; - - HSL_DEV_ID_CHECK(dev_id); - - if (A_FALSE == hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU)) - { - return SW_BAD_PARAM; - } - - if (A_FALSE == hsl_port_prop_check(dev_id, mem_port_id, HSL_PP_INCL_CPU)) - { - return SW_BAD_PARAM; - } - - HSL_REG_FIELD_GET(rv, dev_id, PORT_BASE_VLAN, port_id, - PORT_VID_MEM, (a_uint8_t *) (®val), - sizeof (a_uint32_t)); - - SW_RTN_ON_ERROR(rv); - - regval |= (0x1UL << mem_port_id); - - HSL_REG_FIELD_SET(rv, dev_id, PORT_BASE_VLAN, port_id, - PORT_VID_MEM, (a_uint8_t *) (®val), - sizeof (a_uint32_t)); - - return rv; - -} - -static sw_error_t -_horus_portvlan_member_del(a_uint32_t dev_id, fal_port_t port_id, - a_uint32_t mem_port_id) -{ - sw_error_t rv; - a_uint32_t regval = 0; - - HSL_DEV_ID_CHECK(dev_id); - - if (A_FALSE == hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU)) - { - return SW_BAD_PARAM; - } - - if (A_FALSE == hsl_port_prop_check(dev_id, mem_port_id, HSL_PP_INCL_CPU)) - { - return SW_BAD_PARAM; - } - - HSL_REG_FIELD_GET(rv, dev_id, PORT_BASE_VLAN, port_id, - PORT_VID_MEM, (a_uint8_t *) (®val), - sizeof (a_uint32_t)); - - SW_RTN_ON_ERROR(rv); - - regval &= (~(0x1UL << mem_port_id)); - - HSL_REG_FIELD_SET(rv, dev_id, PORT_BASE_VLAN, port_id, - PORT_VID_MEM, (a_uint8_t *) (®val), - sizeof (a_uint32_t)); - - return rv; - -} - -static sw_error_t -_horus_portvlan_member_update(a_uint32_t dev_id, fal_port_t port_id, - fal_pbmp_t mem_port_map) -{ - sw_error_t rv; - - HSL_DEV_ID_CHECK(dev_id); - - if (A_FALSE == hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU)) - { - return SW_BAD_PARAM; - } - - if (A_FALSE == - hsl_mports_prop_check(dev_id, mem_port_map, HSL_PP_INCL_CPU)) - { - return SW_BAD_PARAM; - } - - HSL_REG_FIELD_SET(rv, dev_id, PORT_BASE_VLAN, port_id, - PORT_VID_MEM, (a_uint8_t *) (&mem_port_map), - sizeof (a_uint32_t)); - - return rv; -} - -static sw_error_t -_horus_portvlan_member_get(a_uint32_t dev_id, fal_port_t port_id, - fal_pbmp_t * mem_port_map) -{ - sw_error_t rv; - - HSL_DEV_ID_CHECK(dev_id); - - if (A_FALSE == hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU)) - { - return SW_BAD_PARAM; - } - - *mem_port_map = 0; - HSL_REG_FIELD_GET(rv, dev_id, PORT_BASE_VLAN, port_id, - PORT_VID_MEM, (a_uint8_t *) mem_port_map, - sizeof (a_uint32_t)); - - SW_RTN_ON_ERROR(rv); - - return SW_OK; -} - -static sw_error_t -_horus_port_default_vid_set(a_uint32_t dev_id, fal_port_t port_id, a_uint32_t vid) -{ - sw_error_t rv; - a_uint32_t val; - - HSL_DEV_ID_CHECK(dev_id); - - if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU)) - { - return SW_BAD_PARAM; - } - - if ((0 == vid) || (vid > MAX_VLAN_ID)) - { - return SW_BAD_PARAM; - } - - val = vid; - HSL_REG_FIELD_SET(rv, dev_id, PORT_DOT1Q, port_id, - DEF_VID, (a_uint8_t *) (&val), - sizeof (a_uint32_t)); - - return rv; -} - - -static sw_error_t -_horus_port_default_vid_get(a_uint32_t dev_id, fal_port_t port_id, a_uint32_t *vid) -{ - sw_error_t rv; - a_uint32_t val; - - HSL_DEV_ID_CHECK(dev_id); - - if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU)) - { - return SW_BAD_PARAM; - } - - HSL_REG_FIELD_GET(rv, dev_id, PORT_DOT1Q, port_id, - DEF_VID, (a_uint8_t *) (&val), - sizeof (a_uint32_t)); - - *vid = val & 0xfff; - return rv; -} - - -static sw_error_t -_horus_port_force_default_vid_set(a_uint32_t dev_id, fal_port_t port_id, a_bool_t enable) -{ - sw_error_t rv; - a_uint32_t val; - - HSL_DEV_ID_CHECK(dev_id); - - if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU)) - { - return SW_BAD_PARAM; - } - - if (A_TRUE == enable) - { - val = 1; - } - else if (A_FALSE == enable) - { - val = 0; - } - else - { - return SW_BAD_PARAM; - } - - HSL_REG_FIELD_SET(rv, dev_id, PORT_DOT1Q, port_id, - FORCE_DEF_VID, (a_uint8_t *) (&val), - sizeof (a_uint32_t)); - return rv; -} - -static sw_error_t -_horus_port_force_default_vid_get(a_uint32_t dev_id, fal_port_t port_id, a_bool_t * enable) -{ - sw_error_t rv; - a_uint32_t val; - - HSL_DEV_ID_CHECK(dev_id); - - if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU)) - { - return SW_BAD_PARAM; - } - - HSL_REG_FIELD_GET(rv, dev_id, PORT_DOT1Q, port_id, - FORCE_DEF_VID, (a_uint8_t *) (&val), - sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - - if (val) - { - *enable = A_TRUE; - } - else - { - *enable = A_FALSE; - } - - return SW_OK; -} - -static sw_error_t -_horus_port_force_portvlan_set(a_uint32_t dev_id, fal_port_t port_id, a_bool_t enable) -{ - sw_error_t rv; - a_uint32_t val; - - HSL_DEV_ID_CHECK(dev_id); - - if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU)) - { - return SW_BAD_PARAM; - } - - if (A_TRUE == enable) - { - val = 1; - } - else if (A_FALSE == enable) - { - val = 0; - } - else - { - return SW_BAD_PARAM; - } - - HSL_REG_FIELD_SET(rv, dev_id, PORT_DOT1Q, port_id, - FORCE_PVLAN, (a_uint8_t *) (&val), - sizeof (a_uint32_t)); - return rv; -} - -static sw_error_t -_horus_port_force_portvlan_get(a_uint32_t dev_id, fal_port_t port_id, a_bool_t * enable) -{ - sw_error_t rv; - a_uint32_t val; - - HSL_DEV_ID_CHECK(dev_id); - - if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU)) - { - return SW_BAD_PARAM; - } - - HSL_REG_FIELD_GET(rv, dev_id, PORT_DOT1Q, port_id, - FORCE_PVLAN, (a_uint8_t *) (&val), - sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - - if (val) - { - *enable = A_TRUE; - } - else - { - *enable = A_FALSE; - } - - return SW_OK; -} - -static sw_error_t -_horus_nestvlan_tpid_set(a_uint32_t dev_id, a_uint32_t tpid) -{ - sw_error_t rv; - a_uint32_t val; - - HSL_DEV_ID_CHECK(dev_id); - - val = tpid; - HSL_REG_FIELD_SET(rv, dev_id, SERVICE_TAG, 0, - TAG_VALUE, (a_uint8_t *) (&val), - sizeof (a_uint32_t)); - return rv; -} - -static sw_error_t -_horus_nestvlan_tpid_get(a_uint32_t dev_id, a_uint32_t *tpid) -{ - sw_error_t rv; - a_uint32_t val; - - HSL_DEV_ID_CHECK(dev_id); - - HSL_REG_FIELD_GET(rv, dev_id, SERVICE_TAG, 0, - TAG_VALUE, (a_uint8_t *) (&val), - sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - - *tpid = val; - return SW_OK; -} - -static sw_error_t -_horus_port_invlan_mode_set(a_uint32_t dev_id, fal_port_t port_id, - fal_pt_invlan_mode_t mode) -{ - sw_error_t rv; - a_uint32_t regval[FAL_INVLAN_MODE_BUTT] = { 0, 1, 2}; - - HSL_DEV_ID_CHECK(dev_id); - - if (A_FALSE == hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU)) - { - return SW_BAD_PARAM; - } - - if (FAL_INVLAN_MODE_BUTT <= mode) - { - return SW_BAD_PARAM; - } - - HSL_REG_FIELD_SET(rv, dev_id, PORT_BASE_VLAN, port_id, IN_VLAN_MODE, - (a_uint8_t *) (®val[mode]), - sizeof (a_uint32_t)); - - return rv; -} - -static sw_error_t -_horus_port_invlan_mode_get(a_uint32_t dev_id, fal_port_t port_id, - fal_pt_invlan_mode_t * mode) -{ - sw_error_t rv; - a_uint32_t regval = 0; - fal_pt_invlan_mode_t retval[FAL_INVLAN_MODE_BUTT] = { FAL_INVLAN_ADMIT_ALL, - FAL_INVLAN_ADMIT_TAGGED, FAL_INVLAN_ADMIT_UNTAGGED - }; - - HSL_DEV_ID_CHECK(dev_id); - - if (A_FALSE == hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU)) - { - return SW_BAD_PARAM; - } - - SW_RTN_ON_NULL(mode); - - HSL_REG_FIELD_GET(rv, dev_id, PORT_BASE_VLAN, port_id, IN_VLAN_MODE, - (a_uint8_t *) (®val), - sizeof (a_uint32_t)); - - SW_RTN_ON_ERROR(rv); - - if (regval >= 3) - { - return SW_FAIL; - } - *mode = retval[regval & 0x3]; - - return rv; -} - -static sw_error_t -_horus_port_pri_propagation_set(a_uint32_t dev_id, fal_port_t port_id, - a_bool_t enable) -{ - sw_error_t rv; - a_uint32_t val; - - HSL_DEV_ID_CHECK(dev_id); - - if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU)) - { - return SW_BAD_PARAM; - } - - if (A_TRUE == enable) - { - val = 1; - } - else if (A_FALSE == enable) - { - val = 0; - } - else - { - return SW_BAD_PARAM; - } - - HSL_REG_FIELD_SET(rv, dev_id, PORT_BASE_VLAN, port_id, - PRI_PROPAGATION, (a_uint8_t *) (&val), - sizeof (a_uint32_t)); - return rv; -} - -static sw_error_t -_horus_port_pri_propagation_get(a_uint32_t dev_id, fal_port_t port_id, - a_bool_t * enable) -{ - sw_error_t rv; - a_uint32_t val; - - HSL_DEV_ID_CHECK(dev_id); - - if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU)) - { - return SW_BAD_PARAM; - } - - HSL_REG_FIELD_GET(rv, dev_id, PORT_BASE_VLAN, port_id, - PRI_PROPAGATION, (a_uint8_t *) (&val), - sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - - if (1 == val) - { - *enable = A_TRUE; - } - else - { - *enable = A_FALSE; - } - - return SW_OK; -} - -static sw_error_t -_horus_qinq_mode_set(a_uint32_t dev_id, fal_qinq_mode_t mode) -{ - sw_error_t rv; - a_uint32_t stag = 0; - - HSL_DEV_ID_CHECK(dev_id); - - if (FAL_QINQ_MODE_BUTT <= mode) - { - return SW_BAD_PARAM; - } - - if (FAL_QINQ_STAG_MODE == mode) - { - stag = 1; - } - - HSL_REG_FIELD_SET(rv, dev_id, ADDR_TABLE_CTL, 0, - STAG_MODE, (a_uint8_t *) (&stag), - sizeof (a_uint32_t)); - - return rv; -} - -static sw_error_t -_horus_qinq_mode_get(a_uint32_t dev_id, fal_qinq_mode_t * mode) -{ - sw_error_t rv; - a_uint32_t stag = 0; - - HSL_DEV_ID_CHECK(dev_id); - - HSL_REG_FIELD_GET(rv, dev_id, ADDR_TABLE_CTL, 0, - STAG_MODE, (a_uint8_t *) (&stag), - sizeof (a_uint32_t)); - - SW_RTN_ON_ERROR(rv); - - if (stag) - { - *mode = FAL_QINQ_STAG_MODE; - } - else - { - *mode = FAL_QINQ_CTAG_MODE; - } - - return SW_OK; -} - -static sw_error_t -_horus_port_qinq_role_set(a_uint32_t dev_id, fal_port_t port_id, fal_qinq_port_role_t role) -{ - sw_error_t rv; - a_uint32_t core = 0; - - HSL_DEV_ID_CHECK(dev_id); - - if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU)) - { - return SW_BAD_PARAM; - } - - if (FAL_QINQ_PORT_ROLE_BUTT <= role) - { - return SW_BAD_PARAM; - } - - if (FAL_QINQ_CORE_PORT == role) - { - core = 1; - } - - HSL_REG_FIELD_SET(rv, dev_id, PORT_BASE_VLAN, port_id, - COREP_EN, (a_uint8_t *) (&core), - sizeof (a_uint32_t)); - - return rv; -} - -static sw_error_t -_horus_port_qinq_role_get(a_uint32_t dev_id, fal_port_t port_id, fal_qinq_port_role_t * role) -{ - sw_error_t rv; - a_uint32_t core = 0; - - HSL_DEV_ID_CHECK(dev_id); - - if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU)) - { - return SW_BAD_PARAM; - } - - HSL_REG_FIELD_GET(rv, dev_id, PORT_BASE_VLAN, port_id, - COREP_EN, (a_uint8_t *) (&core), - sizeof (a_uint32_t)); - - SW_RTN_ON_ERROR(rv); - - if (core) - { - *role = FAL_QINQ_CORE_PORT; - } - else - { - *role = FAL_QINQ_EDGE_PORT; - } - - return SW_OK; -} - -/** - * @brief Set 802.1q work mode on a particular port. - * @param[in] dev_id device id - * @param[in] port_id port id - * @param[in] port_1qmode 802.1q work mode - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -horus_port_1qmode_set(a_uint32_t dev_id, fal_port_t port_id, - fal_pt_1qmode_t port_1qmode) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _horus_port_1qmode_set(dev_id, port_id, port_1qmode); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Get 802.1q work mode on a particular port. - * @param[in] dev_id device id - * @param[in] port_id port id - * @param[out] port_1qmode 802.1q work mode - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -horus_port_1qmode_get(a_uint32_t dev_id, fal_port_t port_id, - fal_pt_1qmode_t * pport_1qmode) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _horus_port_1qmode_get(dev_id, port_id, pport_1qmode); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Set packets transmitted out vlan tagged mode on a particular port. - * @param[in] dev_id device id - * @param[in] port_id port id - * @param[in] port_egvlanmode packets transmitted out vlan tagged mode - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -horus_port_egvlanmode_set(a_uint32_t dev_id, fal_port_t port_id, - fal_pt_1q_egmode_t port_egvlanmode) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _horus_port_egvlanmode_set(dev_id, port_id, port_egvlanmode); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Get packets transmitted out vlan tagged mode on a particular port. - * @param[in] dev_id device id - * @param[in] port_id port id - * @param[out] port_egvlanmode packets transmitted out vlan tagged mode - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -horus_port_egvlanmode_get(a_uint32_t dev_id, fal_port_t port_id, - fal_pt_1q_egmode_t * pport_egvlanmode) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _horus_port_egvlanmode_get(dev_id, port_id, pport_egvlanmode); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Add member of port based vlan on a particular port. - * @param[in] dev_id device id - * @param[in] port_id port id - * @param[in] mem_port_id port member - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -horus_portvlan_member_add(a_uint32_t dev_id, fal_port_t port_id, - a_uint32_t mem_port_id) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _horus_portvlan_member_add(dev_id, port_id, mem_port_id); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Delete member of port based vlan on a particular port. - * @param[in] dev_id device id - * @param[in] port_id port id - * @param[in] mem_port_id port member - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -horus_portvlan_member_del(a_uint32_t dev_id, fal_port_t port_id, - a_uint32_t mem_port_id) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _horus_portvlan_member_del(dev_id, port_id, mem_port_id); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Update member of port based vlan on a particular port. - * @param[in] dev_id device id - * @param[in] port_id port id - * @param[in] mem_port_map port members - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -horus_portvlan_member_update(a_uint32_t dev_id, fal_port_t port_id, - fal_pbmp_t mem_port_map) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _horus_portvlan_member_update(dev_id, port_id, mem_port_map); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Get member of port based vlan on a particular port. - * @param[in] dev_id device id - * @param[in] port_id port id - * @param[out] mem_port_map port members - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -horus_portvlan_member_get(a_uint32_t dev_id, fal_port_t port_id, - fal_pbmp_t * mem_port_map) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _horus_portvlan_member_get(dev_id, port_id, mem_port_map); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Set default vlan id on a particular port. - * @param[in] dev_id device id - * @param[in] port_id port id - * @param[in] vid default vlan id - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -horus_port_default_vid_set(a_uint32_t dev_id, fal_port_t port_id, a_uint32_t vid) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _horus_port_default_vid_set(dev_id, port_id, vid); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Get default vlan id on a particular port. - * @param[in] dev_id device id - * @param[in] port_id port id - * @param[out] vid default vlan id - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -horus_port_default_vid_get(a_uint32_t dev_id, fal_port_t port_id, a_uint32_t *vid) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _horus_port_default_vid_get(dev_id, port_id, vid); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Set force default vlan id status on a particular port. - * @param[in] dev_id device id - * @param[in] port_id port id - * @param[in] enable A_TRUE or A_FALSE - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -horus_port_force_default_vid_set(a_uint32_t dev_id, fal_port_t port_id, a_bool_t enable) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _horus_port_force_default_vid_set(dev_id, port_id, enable); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Get force default vlan id status on a particular port. - * @param[in] dev_id device id - * @param[in] port_id port id - * @param[out] enable A_TRUE or A_FALSE - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -horus_port_force_default_vid_get(a_uint32_t dev_id, fal_port_t port_id, a_bool_t * enable) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _horus_port_force_default_vid_get(dev_id, port_id, enable); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Set force port based vlan status on a particular port. - * @param[in] dev_id device id - * @param[in] port_id port id - * @param[in] enable A_TRUE or A_FALSE - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -horus_port_force_portvlan_set(a_uint32_t dev_id, fal_port_t port_id, a_bool_t enable) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _horus_port_force_portvlan_set(dev_id, port_id, enable); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Get force port based vlan status on a particular port. - * @param[in] dev_id device id - * @param[in] port_id port id - * @param[out] enable A_TRUE or A_FALSE - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -horus_port_force_portvlan_get(a_uint32_t dev_id, fal_port_t port_id, a_bool_t * enable) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _horus_port_force_portvlan_get(dev_id, port_id, enable); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Set nest vlan tpid on a particular device. - * @param[in] dev_id device id - * @param[in] tpid tag protocol identification - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -horus_nestvlan_tpid_set(a_uint32_t dev_id, a_uint32_t tpid) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _horus_nestvlan_tpid_set(dev_id, tpid); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Get nest vlan tpid on a particular device. - * @param[in] dev_id device id - * @param[out] tpid tag protocol identification - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -horus_nestvlan_tpid_get(a_uint32_t dev_id, a_uint32_t *tpid) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _horus_nestvlan_tpid_get(dev_id, tpid); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Set ingress vlan mode mode on a particular port. - * @param[in] dev_id device id - * @param[in] port_id port id - * @param[in] mode ingress vlan mode - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -horus_port_invlan_mode_set(a_uint32_t dev_id, fal_port_t port_id, - fal_pt_invlan_mode_t mode) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _horus_port_invlan_mode_set(dev_id, port_id, mode); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Get ingress vlan mode mode on a particular port. - * @param[in] dev_id device id - * @param[in] port_id port id - * @param[out] mode ingress vlan mode - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -horus_port_invlan_mode_get(a_uint32_t dev_id, fal_port_t port_id, - fal_pt_invlan_mode_t * mode) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _horus_port_invlan_mode_get(dev_id, port_id, mode); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Set priority propagation status on a particular port. - * @param[in] dev_id device id - * @param[in] port_id port id - * @param[in] enable A_TRUE or A_FALSE - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -horus_port_pri_propagation_set(a_uint32_t dev_id, fal_port_t port_id, - a_bool_t enable) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _horus_port_pri_propagation_set(dev_id, port_id, enable); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Get priority propagation status on a particular port. - * @param[in] dev_id device id - * @param[in] port_id port id - * @param[out] enable A_TRUE or A_FALSE - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -horus_port_pri_propagation_get(a_uint32_t dev_id, fal_port_t port_id, - a_bool_t * enable) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _horus_port_pri_propagation_get(dev_id, port_id, enable); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Set switch qinq work mode on a particular device. - * @param[in] dev_id device id - * @param[in] mode qinq work mode - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -horus_qinq_mode_set(a_uint32_t dev_id, fal_qinq_mode_t mode) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _horus_qinq_mode_set(dev_id, mode); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Get switch qinq work mode on a particular device. - * @param[in] dev_id device id - * @param[out] mode qinq work mode - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -horus_qinq_mode_get(a_uint32_t dev_id, fal_qinq_mode_t * mode) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _horus_qinq_mode_get(dev_id, mode); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Set qinq role on a particular port. - * @param[in] dev_id device id - * @param[in] port_id port id - * @param[in] role port role - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -horus_port_qinq_role_set(a_uint32_t dev_id, fal_port_t port_id, fal_qinq_port_role_t role) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _horus_port_qinq_role_set(dev_id, port_id, role); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Get qinq role on a particular port. - * @param[in] dev_id device id - * @param[in] port_id port id - * @param[out] role port role - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -horus_port_qinq_role_get(a_uint32_t dev_id, fal_port_t port_id, fal_qinq_port_role_t * role) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _horus_port_qinq_role_get(dev_id, port_id, role); - HSL_API_UNLOCK; - return rv; -} - -sw_error_t -horus_portvlan_init(a_uint32_t dev_id) -{ - HSL_DEV_ID_CHECK(dev_id); - -#ifndef HSL_STANDALONG - hsl_api_t *p_api; - - SW_RTN_ON_NULL (p_api = hsl_api_ptr_get(dev_id)); - - p_api->port_1qmode_get = horus_port_1qmode_get; - p_api->port_1qmode_set = horus_port_1qmode_set; - p_api->port_egvlanmode_get = horus_port_egvlanmode_get; - p_api->port_egvlanmode_set = horus_port_egvlanmode_set; - p_api->portvlan_member_add = horus_portvlan_member_add; - p_api->portvlan_member_del = horus_portvlan_member_del; - p_api->portvlan_member_update = horus_portvlan_member_update; - p_api->portvlan_member_get = horus_portvlan_member_get; - p_api->port_default_vid_set = horus_port_default_vid_set; - p_api->port_default_vid_get = horus_port_default_vid_get; - p_api->port_force_default_vid_set = horus_port_force_default_vid_set; - p_api->port_force_default_vid_get = horus_port_force_default_vid_get; - p_api->port_force_portvlan_set = horus_port_force_portvlan_set; - p_api->port_force_portvlan_get = horus_port_force_portvlan_get; - p_api->nestvlan_tpid_set = horus_nestvlan_tpid_set; - p_api->nestvlan_tpid_get = horus_nestvlan_tpid_get; - p_api->port_invlan_mode_set = horus_port_invlan_mode_set; - p_api->port_invlan_mode_get = horus_port_invlan_mode_get; - p_api->port_pri_propagation_set = horus_port_pri_propagation_set; - p_api->port_pri_propagation_get = horus_port_pri_propagation_get; - p_api->qinq_mode_set = horus_qinq_mode_set; - p_api->qinq_mode_get = horus_qinq_mode_get; - p_api->port_qinq_role_set = horus_port_qinq_role_set; - p_api->port_qinq_role_get = horus_port_qinq_role_get; -#endif - - return SW_OK; -} - -/** - * @} - */ diff --git a/feeds/ipq807x/qca-ssdk/src/src/hsl/horus/horus_qos.c b/feeds/ipq807x/qca-ssdk/src/src/hsl/horus/horus_qos.c deleted file mode 100755 index b2c6398e5..000000000 --- a/feeds/ipq807x/qca-ssdk/src/src/hsl/horus/horus_qos.c +++ /dev/null @@ -1,1260 +0,0 @@ -/* - * Copyright (c) 2012, The Linux Foundation. All rights reserved. - * Permission to use, copy, modify, and/or distribute this software for - * any purpose with or without fee is hereby granted, provided that the - * above copyright notice and this permission notice appear in all copies. - * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES - * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR - * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES - * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN - * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT - * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. - */ - - -/** - * @defgroup horus_qos HORUS_QOS - * @{ - */ -#include "sw.h" -#include "hsl.h" -#include "hsl_dev.h" -#include "hsl_port_prop.h" -#include "horus_qos.h" -#include "horus_reg.h" - -#define HORUS_QOS_QUEUE_TX_BUFFER_MAX 60 -#define HORUS_QOS_PORT_TX_BUFFER_MAX 252 -#define HORUS_QOS_PORT_RX_BUFFER_MAX 60 - -//#define HORUS_MIN_QOS_MODE_PRI 0 -#define HORUS_MAX_QOS_MODE_PRI 3 - -static sw_error_t -_horus_qos_queue_tx_buf_status_set(a_uint32_t dev_id, fal_port_t port_id, - a_bool_t enable) -{ - a_uint32_t val = 0; - sw_error_t rv; - - if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU)) - { - return SW_BAD_PARAM; - } - - if (A_TRUE == enable) - { - val = 1; - } - else if (A_FALSE == enable) - { - val = 0; - } - else - { - return SW_BAD_PARAM; - } - - HSL_REG_FIELD_SET(rv, dev_id, QUEUE_CTL, port_id, QUEUE_DESC_EN, - (a_uint8_t *) (&val), sizeof (a_uint32_t)); - return rv; -} - -static sw_error_t -_horus_qos_queue_tx_buf_status_get(a_uint32_t dev_id, fal_port_t port_id, - a_bool_t * enable) -{ - a_uint32_t val = 0; - sw_error_t rv; - - if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU)) - { - return SW_BAD_PARAM; - } - - HSL_REG_FIELD_GET(rv, dev_id, QUEUE_CTL, port_id, QUEUE_DESC_EN, - (a_uint8_t *) (&val), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - - if (1 == val) - { - *enable = A_TRUE; - } - else - { - *enable = A_FALSE; - } - - return SW_OK; -} - -static sw_error_t -_horus_qos_port_tx_buf_status_set(a_uint32_t dev_id, fal_port_t port_id, - a_bool_t enable) -{ - a_uint32_t val = 0; - sw_error_t rv; - - if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU)) - { - return SW_BAD_PARAM; - } - - if (A_TRUE == enable) - { - val = 1; - } - else if (A_FALSE == enable) - { - val = 0; - } - else - { - return SW_BAD_PARAM; - } - - HSL_REG_FIELD_SET(rv, dev_id, QUEUE_CTL, port_id, PORT_DESC_EN, - (a_uint8_t *) (&val), sizeof (a_uint32_t)); - return rv; -} - -static sw_error_t -_horus_qos_port_tx_buf_status_get(a_uint32_t dev_id, fal_port_t port_id, - a_bool_t * enable) -{ - a_uint32_t val = 0; - sw_error_t rv; - - if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU)) - { - return SW_BAD_PARAM; - } - - HSL_REG_FIELD_GET(rv, dev_id, QUEUE_CTL, port_id, PORT_DESC_EN, - (a_uint8_t *) (&val), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - - if (1 == val) - { - *enable = A_TRUE; - } - else - { - *enable = A_FALSE; - } - - return SW_OK; -} - -static sw_error_t -_horus_qos_queue_tx_buf_nr_set(a_uint32_t dev_id, fal_port_t port_id, - fal_queue_t queue_id, a_uint32_t * number) -{ - a_uint32_t val = 0; - sw_error_t rv; - - if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU)) - { - return SW_BAD_PARAM; - } - - if (HORUS_QOS_QUEUE_TX_BUFFER_MAX < *number) - { - return SW_BAD_PARAM; - } - - val = *number / 4; - *number = val << 2; - - if (0 == queue_id) - { - HSL_REG_FIELD_SET(rv, dev_id, QUEUE_CTL, port_id, QUEUE0_DESC_NR, - (a_uint8_t *) (&val), sizeof (a_uint32_t)); - } - else if (1 == queue_id) - { - HSL_REG_FIELD_SET(rv, dev_id, QUEUE_CTL, port_id, QUEUE1_DESC_NR, - (a_uint8_t *) (&val), sizeof (a_uint32_t)); - } - else if (2 == queue_id) - { - HSL_REG_FIELD_SET(rv, dev_id, QUEUE_CTL, port_id, QUEUE2_DESC_NR, - (a_uint8_t *) (&val), sizeof (a_uint32_t)); - } - else if (3 == queue_id) - { - HSL_REG_FIELD_SET(rv, dev_id, QUEUE_CTL, port_id, QUEUE3_DESC_NR, - (a_uint8_t *) (&val), sizeof (a_uint32_t)); - } - else - { - return SW_BAD_PARAM; - } - - return rv; -} - -static sw_error_t -_horus_qos_queue_tx_buf_nr_get(a_uint32_t dev_id, fal_port_t port_id, - fal_queue_t queue_id, a_uint32_t * number) -{ - a_uint32_t val = 0; - sw_error_t rv; - - if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU)) - { - return SW_BAD_PARAM; - } - - if (0 == queue_id) - { - HSL_REG_FIELD_GET(rv, dev_id, QUEUE_CTL, port_id, QUEUE0_DESC_NR, - (a_uint8_t *) (&val), sizeof (a_uint32_t)); - } - else if (1 == queue_id) - { - HSL_REG_FIELD_GET(rv, dev_id, QUEUE_CTL, port_id, QUEUE1_DESC_NR, - (a_uint8_t *) (&val), sizeof (a_uint32_t)); - } - else if (2 == queue_id) - { - HSL_REG_FIELD_GET(rv, dev_id, QUEUE_CTL, port_id, QUEUE2_DESC_NR, - (a_uint8_t *) (&val), sizeof (a_uint32_t)); - } - else if (3 == queue_id) - { - HSL_REG_FIELD_GET(rv, dev_id, QUEUE_CTL, port_id, QUEUE3_DESC_NR, - (a_uint8_t *) (&val), sizeof (a_uint32_t)); - } - else - { - return SW_BAD_PARAM; - } - SW_RTN_ON_ERROR(rv); - - *number = val << 2; - return SW_OK; -} - -static sw_error_t -_horus_qos_port_tx_buf_nr_set(a_uint32_t dev_id, fal_port_t port_id, - a_uint32_t * number) -{ - a_uint32_t val = 0; - sw_error_t rv; - - if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU)) - { - return SW_BAD_PARAM; - } - - if (HORUS_QOS_PORT_TX_BUFFER_MAX < *number) - { - return SW_BAD_PARAM; - } - - val = *number / 4; - *number = val << 2; - HSL_REG_FIELD_SET(rv, dev_id, QUEUE_CTL, port_id, PORT_DESC_NR, - (a_uint8_t *) (&val), sizeof (a_uint32_t)); - return rv; -} - -static sw_error_t -_horus_qos_port_tx_buf_nr_get(a_uint32_t dev_id, fal_port_t port_id, - a_uint32_t * number) -{ - a_uint32_t val = 0; - sw_error_t rv; - - if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU)) - { - return SW_BAD_PARAM; - } - - HSL_REG_FIELD_GET(rv, dev_id, QUEUE_CTL, port_id, PORT_DESC_NR, - (a_uint8_t *) (&val), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - - *number = val << 2; - return SW_OK; -} - -static sw_error_t -_horus_qos_port_rx_buf_nr_set(a_uint32_t dev_id, fal_port_t port_id, - a_uint32_t * number) -{ - a_uint32_t val = 0; - sw_error_t rv; - - if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU)) - { - return SW_BAD_PARAM; - } - - if (HORUS_QOS_PORT_RX_BUFFER_MAX < *number) - { - return SW_BAD_PARAM; - } - - val = *number / 4; - *number = val << 2; - HSL_REG_FIELD_SET(rv, dev_id, QUEUE_CTL, port_id, PORT_IN_DESC_EN, - (a_uint8_t *) (&val), sizeof (a_uint32_t)); - return rv; -} - -static sw_error_t -_horus_qos_port_rx_buf_nr_get(a_uint32_t dev_id, fal_port_t port_id, - a_uint32_t * number) -{ - a_uint32_t val = 0; - sw_error_t rv; - - if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU)) - { - return SW_BAD_PARAM; - } - - HSL_REG_FIELD_GET(rv, dev_id, QUEUE_CTL, port_id, PORT_IN_DESC_EN, - (a_uint8_t *) (&val), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - - *number = val << 2; - return SW_OK; -} - -static sw_error_t -_horus_cosmap_up_queue_set(a_uint32_t dev_id, a_uint32_t up, - fal_queue_t queue) -{ - sw_error_t rv; - a_uint32_t val; - hsl_dev_t *p_dev = NULL; - - HSL_DEV_ID_CHECK(dev_id); - - if (FAL_DOT1P_MAX < up) - { - return SW_BAD_PARAM; - } - - SW_RTN_ON_NULL(p_dev = hsl_dev_ptr_get(dev_id)); - if (p_dev->nr_queue <= queue) - { - return SW_BAD_PARAM; - } - - val = queue; - HSL_REG_FIELD_GEN_SET(rv, dev_id, TAG_PRI_MAPPING_OFFSET, 2, - (a_uint16_t) (up << 1), (a_uint8_t *) (&val), - sizeof (a_uint32_t)); - return rv; -} - -static sw_error_t -_horus_cosmap_up_queue_get(a_uint32_t dev_id, a_uint32_t up, - fal_queue_t * queue) -{ - sw_error_t rv; - a_uint32_t val; - - HSL_DEV_ID_CHECK(dev_id); - - if (FAL_DOT1P_MAX < up) - { - return SW_BAD_PARAM; - } - - HSL_REG_FIELD_GEN_GET(rv, dev_id, TAG_PRI_MAPPING_OFFSET, 2, - (a_uint16_t) (up << 1), (a_uint8_t *) (&val), - sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - - *queue = val; - return SW_OK; -} - -static sw_error_t -_horus_cosmap_dscp_queue_set(a_uint32_t dev_id, a_uint32_t dscp, - fal_queue_t queue) -{ - sw_error_t rv; - a_uint32_t val; - a_uint32_t offsetaddr; - a_uint16_t fieldoffset; - hsl_dev_t *p_dev = NULL; - - HSL_DEV_ID_CHECK(dev_id); - - if (FAL_DSCP_MAX < dscp) - { - return SW_BAD_PARAM; - } - - SW_RTN_ON_NULL(p_dev = hsl_dev_ptr_get(dev_id)); - if (p_dev->nr_queue <= queue) - { - return SW_BAD_PARAM; - } - - offsetaddr = (dscp >> 4) << 2; - fieldoffset = (dscp & 0xf) << 1; - - val = queue; - HSL_REG_FIELD_GEN_SET(rv, dev_id, (IP_PRI_MAPPING_OFFSET + offsetaddr), - 2, fieldoffset, (a_uint8_t *) (&val), sizeof (a_uint32_t)); - return rv; -} - -static sw_error_t -_horus_cosmap_dscp_queue_get(a_uint32_t dev_id, a_uint32_t dscp, - fal_queue_t * queue) -{ - sw_error_t rv; - a_uint32_t val; - a_uint32_t offsetaddr; - a_uint16_t fieldoffset; - - HSL_DEV_ID_CHECK(dev_id); - - if (FAL_DSCP_MAX < dscp) - { - return SW_BAD_PARAM; - } - - offsetaddr = (dscp / 16) << 2; - fieldoffset = (dscp & 0xf) << 1; - - HSL_REG_FIELD_GEN_GET(rv, dev_id, (IP_PRI_MAPPING_OFFSET + offsetaddr), - 2, fieldoffset, (a_uint8_t *) (&val), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - - *queue = val; - return SW_OK; -} - -static sw_error_t -_horus_qos_port_mode_set(a_uint32_t dev_id, fal_port_t port_id, - fal_qos_mode_t mode, a_bool_t enable) -{ - sw_error_t rv; - a_uint32_t val; - - HSL_DEV_ID_CHECK(dev_id); - - if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU)) - { - return SW_BAD_PARAM; - } - - if (A_TRUE == enable) - { - val = 1; - } - else if (A_FALSE == enable) - { - val = 0; - } - else - { - return SW_BAD_PARAM; - } - - if (FAL_QOS_DA_MODE == mode) - { - HSL_REG_FIELD_SET(rv, dev_id, PRI_CTL, port_id, DA_PRI_EN, - (a_uint8_t *) (&val), sizeof (a_uint32_t)); - } - else if (FAL_QOS_UP_MODE == mode) - { - HSL_REG_FIELD_SET(rv, dev_id, PRI_CTL, port_id, VLAN_PRI_EN, - (a_uint8_t *) (&val), sizeof (a_uint32_t)); - } - else if (FAL_QOS_DSCP_MODE == mode) - { - HSL_REG_FIELD_SET(rv, dev_id, PRI_CTL, port_id, IP_PRI_EN, - (a_uint8_t *) (&val), sizeof (a_uint32_t)); - } - else if (FAL_QOS_PORT_MODE == mode) - { - HSL_REG_FIELD_SET(rv, dev_id, PRI_CTL, port_id, PORT_PRI_EN, - (a_uint8_t *) (&val), sizeof (a_uint32_t)); - } - else - { - return SW_BAD_PARAM; - } - - return rv; -} - -static sw_error_t -_horus_qos_port_mode_get(a_uint32_t dev_id, fal_port_t port_id, - fal_qos_mode_t mode, a_bool_t * enable) -{ - sw_error_t rv; - a_uint32_t val; - - HSL_DEV_ID_CHECK(dev_id); - - if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU)) - { - return SW_BAD_PARAM; - } - - if (FAL_QOS_DA_MODE == mode) - { - HSL_REG_FIELD_GET(rv, dev_id, PRI_CTL, port_id, DA_PRI_EN, - (a_uint8_t *) (&val), sizeof (a_uint32_t)); - } - else if (FAL_QOS_UP_MODE == mode) - { - HSL_REG_FIELD_GET(rv, dev_id, PRI_CTL, port_id, VLAN_PRI_EN, - (a_uint8_t *) (&val), sizeof (a_uint32_t)); - } - else if (FAL_QOS_DSCP_MODE == mode) - { - HSL_REG_FIELD_GET(rv, dev_id, PRI_CTL, port_id, IP_PRI_EN, - (a_uint8_t *) (&val), sizeof (a_uint32_t)); - } - else if (FAL_QOS_PORT_MODE == mode) - { - HSL_REG_FIELD_GET(rv, dev_id, PRI_CTL, port_id, PORT_PRI_EN, - (a_uint8_t *) (&val), sizeof (a_uint32_t)); - } - else - { - return SW_BAD_PARAM; - } - SW_RTN_ON_ERROR(rv); - - if (1 == val) - { - *enable = A_TRUE; - } - else - { - *enable = A_FALSE; - } - - return SW_OK; -} - -static sw_error_t -_horus_qos_port_mode_pri_set(a_uint32_t dev_id, fal_port_t port_id, - fal_qos_mode_t mode, a_uint32_t pri) -{ - sw_error_t rv; - a_uint32_t val; - - HSL_DEV_ID_CHECK(dev_id); - - if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU)) - { - return SW_BAD_PARAM; - } - - if (HORUS_MAX_QOS_MODE_PRI < pri) - { - return SW_BAD_PARAM; - } - - HSL_REG_ENTRY_GET(rv, dev_id, PRI_CTL, port_id, (a_uint8_t *) (&val), - sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - - if (FAL_QOS_DA_MODE == mode) - { - SW_SET_REG_BY_FIELD(PRI_CTL, DA_PRI_SEL, pri, val); - } - else if (FAL_QOS_UP_MODE == mode) - { - SW_SET_REG_BY_FIELD(PRI_CTL, VLAN_PRI_SEL, pri, val); - } - else if (FAL_QOS_DSCP_MODE == mode) - { - SW_SET_REG_BY_FIELD(PRI_CTL, IP_PRI_SEL, pri, val); - } - else if (FAL_QOS_PORT_MODE == mode) - { - SW_SET_REG_BY_FIELD(PRI_CTL, PORT_PRI_SEL, pri, val); - } - else - { - return SW_NOT_SUPPORTED; - } - - HSL_REG_ENTRY_SET(rv, dev_id, PRI_CTL, port_id, (a_uint8_t *) (&val), - sizeof (a_uint32_t)); - return rv; -} - -static sw_error_t -_horus_qos_port_mode_pri_get(a_uint32_t dev_id, fal_port_t port_id, - fal_qos_mode_t mode, a_uint32_t * pri) -{ - sw_error_t rv; - a_uint32_t entry, f_val; - - HSL_DEV_ID_CHECK(dev_id); - - if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU)) - { - return SW_BAD_PARAM; - } - - HSL_REG_ENTRY_GET(rv, dev_id, PRI_CTL, port_id, (a_uint8_t *) (&entry), - sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - - if (FAL_QOS_DA_MODE == mode) - { - SW_GET_FIELD_BY_REG(PRI_CTL, DA_PRI_SEL, f_val, entry); - } - else if (FAL_QOS_UP_MODE == mode) - { - SW_GET_FIELD_BY_REG(PRI_CTL, VLAN_PRI_SEL, f_val, entry); - } - else if (FAL_QOS_DSCP_MODE == mode) - { - SW_GET_FIELD_BY_REG(PRI_CTL, IP_PRI_SEL, f_val, entry); - } - else if (FAL_QOS_PORT_MODE == mode) - { - SW_GET_FIELD_BY_REG(PRI_CTL, PORT_PRI_SEL, f_val, entry); - } - else - { - return SW_NOT_SUPPORTED; - } - - *pri = f_val; - return SW_OK; -} - -static sw_error_t -_horus_qos_port_default_up_set(a_uint32_t dev_id, fal_port_t port_id, - a_uint32_t up) -{ - sw_error_t rv; - a_uint32_t val; - - HSL_DEV_ID_CHECK(dev_id); - - if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU)) - { - return SW_BAD_PARAM; - } - - if (FAL_DOT1P_MAX < up) - { - return SW_BAD_PARAM; - } - - val = up; - HSL_REG_FIELD_SET(rv, dev_id, PORT_DOT1Q, port_id, ING_PRI, - (a_uint8_t *) (&val), sizeof (a_uint32_t)); - return rv; -} - -static sw_error_t -_horus_qos_port_default_up_get(a_uint32_t dev_id, fal_port_t port_id, - a_uint32_t * up) -{ - sw_error_t rv; - a_uint32_t val; - - HSL_DEV_ID_CHECK(dev_id); - - if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU)) - { - return SW_BAD_PARAM; - } - - HSL_REG_FIELD_GET(rv, dev_id, PORT_DOT1Q, port_id, ING_PRI, - (a_uint8_t *) (&val), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - - *up = val; - return SW_OK; -} - -static sw_error_t -_horus_qos_port_sch_mode_set(a_uint32_t dev_id, a_uint32_t port_id, - fal_sch_mode_t mode, const a_uint32_t weight[]) -{ - sw_error_t rv; - a_uint32_t val; - - HSL_DEV_ID_CHECK(dev_id); - - if (FAL_SCH_SP_MODE == mode) - { - val = 0; - } - else if (FAL_SCH_WRR_MODE == mode) - { - val = 3; - } - else if (FAL_SCH_MIX_MODE == mode) - { - val = 1; - } - else if (FAL_SCH_MIX_PLUS_MODE == mode) - { - val = 2; - } - else - { - return SW_NOT_SUPPORTED; - } - - HSL_REG_FIELD_SET(rv, dev_id, WRR_CTRL, port_id, SCH_MODE, - (a_uint8_t *) (&val), sizeof (a_uint32_t)); - return rv; -} - -static sw_error_t -_horus_qos_port_sch_mode_get(a_uint32_t dev_id, a_uint32_t port_id, - fal_sch_mode_t * mode, a_uint32_t weight[]) -{ - sw_error_t rv; - a_uint32_t sch, i; - a_uint32_t w[4] = {1, 2, 4, 8}; - - HSL_DEV_ID_CHECK(dev_id); - - HSL_REG_FIELD_GET(rv, dev_id, WRR_CTRL, port_id, SCH_MODE, - (a_uint8_t *) (&sch), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - - if (0 == sch) - { - *mode = FAL_SCH_SP_MODE; - for (i = 0; i < 4; i++) - { - w[i] = 0; - } - } - else if (1 == sch) - { - *mode = FAL_SCH_MIX_MODE; - w[3] = 0; - } - else if (2 == sch) - { - *mode = FAL_SCH_MIX_PLUS_MODE; - w[3] = 0; - w[2] = 0; - } - else - { - *mode = FAL_SCH_WRR_MODE; - } - - for (i = 0; i < 4; i++) - { - weight[i] = w[i]; - } - - return SW_OK; -} - -/** - * @brief Set buffer aggsinment status of transmitting queue on one particular port. - * @details Comments: - * If enable queue tx buffer on one port that means each queue of this port - * will have fixed number buffers when transmitting packets. Otherwise they - * share the whole buffers with other queues in device. - * @param[in] dev_id device id - * @param[in] port_id port id - * @param[in] enable A_TRUE or A_FALSE - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -horus_qos_queue_tx_buf_status_set(a_uint32_t dev_id, fal_port_t port_id, - a_bool_t enable) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _horus_qos_queue_tx_buf_status_set(dev_id, port_id, enable); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Get buffer aggsinment status of transmitting queue on particular port. - * @param[in] dev_id device id - * @param[in] port_id port id - * @param[in] enable A_TRUE or A_FALSE - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -horus_qos_queue_tx_buf_status_get(a_uint32_t dev_id, fal_port_t port_id, - a_bool_t * enable) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _horus_qos_queue_tx_buf_status_get(dev_id, port_id, enable); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Set buffer aggsinment status of transmitting port on one particular port. - * @details Comments: - If enable tx buffer on one port that means this port will have fixed - number buffers when transmitting packets. Otherwise they will - share the whole buffers with other ports in device. - * function will return actual buffer numbers in hardware. - * @param[in] dev_id device id - * @param[in] port_id port id - * @param[in] enable A_TRUE or A_FALSE - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -horus_qos_port_tx_buf_status_set(a_uint32_t dev_id, fal_port_t port_id, - a_bool_t enable) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _horus_qos_port_tx_buf_status_set(dev_id, port_id, enable); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Get buffer aggsinment status of transmitting port on one particular port. - * @param[in] dev_id device id - * @param[in] port_id port id - * @param[out] enable A_TRUE or A_FALSE - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -horus_qos_port_tx_buf_status_get(a_uint32_t dev_id, fal_port_t port_id, - a_bool_t * enable) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _horus_qos_port_tx_buf_status_get(dev_id, port_id, enable); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Set max occupied buffer number of transmitting queue on one particular port. - * @details Comments: - The step of buffer number in Garuda is 4, function will return actual - buffer numbers in hardware. - The buffer number range for queue is 4 to 60. - * share the whole buffers with other ports in device. - * @param[in] dev_id device id - * @param[in] port_id port id - * @param[in] queue_id queue id - * @param number buffer number - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -horus_qos_queue_tx_buf_nr_set(a_uint32_t dev_id, fal_port_t port_id, - fal_queue_t queue_id, a_uint32_t * number) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _horus_qos_queue_tx_buf_nr_set(dev_id, port_id, queue_id, number); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Get max occupied buffer number of transmitting queue on one particular port. - * @param[in] dev_id device id - * @param[in] port_id port id - * @param[in] queue_id queue id - * @param[out] number buffer number - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -horus_qos_queue_tx_buf_nr_get(a_uint32_t dev_id, fal_port_t port_id, - fal_queue_t queue_id, a_uint32_t * number) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _horus_qos_queue_tx_buf_nr_get(dev_id, port_id, queue_id, number); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Set max occupied buffer number of transmitting port on one particular port. - * @details Comments: - The step of buffer number in Garuda is four, function will return actual - buffer numbers in hardware. - The buffer number range for transmitting port is 4 to 124. - * @param[in] dev_id device id - * @param[in] port_id port id - * @param number buffer number - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -horus_qos_port_tx_buf_nr_set(a_uint32_t dev_id, fal_port_t port_id, - a_uint32_t * number) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _horus_qos_port_tx_buf_nr_set(dev_id, port_id, number); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Get max occupied buffer number of transmitting port on one particular port. - * @param[in] dev_id device id - * @param[in] port_id port id - * @param[out] number buffer number - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -horus_qos_port_tx_buf_nr_get(a_uint32_t dev_id, fal_port_t port_id, - a_uint32_t * number) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _horus_qos_port_tx_buf_nr_get(dev_id, port_id, number); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Set max occupied buffer number of receiving port on one particular port. - * @details Comments: - The step of buffer number in Horus is four, function will return actual - buffer numbers in hardware. - The buffer number range for receiving port is 4 to 60. - * @param[in] dev_id device id - * @param[in] port_id port id - * @param number buffer number - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -horus_qos_port_rx_buf_nr_set(a_uint32_t dev_id, fal_port_t port_id, - a_uint32_t * number) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _horus_qos_port_rx_buf_nr_set(dev_id, port_id, number); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Get max occupied buffer number of receiving port on one particular port. - * @param[in] dev_id device id - * @param[in] port_id port id - * @param[out] number buffer number - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -horus_qos_port_rx_buf_nr_get(a_uint32_t dev_id, fal_port_t port_id, - a_uint32_t * number) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _horus_qos_port_rx_buf_nr_get(dev_id, port_id, number); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Set user priority to mapping on one particular device. - * @param[in] dev_id device id - * @param[in] dot1p 802.1p - * @param[in] queue queue id - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -horus_cosmap_up_queue_set(a_uint32_t dev_id, a_uint32_t up, - fal_queue_t queue) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _horus_cosmap_up_queue_set(dev_id, up, queue); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Get user priority to mapping on one particular device. - * @param[in] dev_id device id - * @param[in] dot1p 802.1p - * @param[out] queue queue id - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -horus_cosmap_up_queue_get(a_uint32_t dev_id, a_uint32_t up, - fal_queue_t * queue) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _horus_cosmap_up_queue_get(dev_id, up, queue); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Set cos map dscp_2_queue item on one particular device. - * @param[in] dev_id device id - * @param[in] dscp dscp - * @param[in] queue queue id - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -horus_cosmap_dscp_queue_set(a_uint32_t dev_id, a_uint32_t dscp, - fal_queue_t queue) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _horus_cosmap_dscp_queue_set(dev_id, dscp, queue); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Get cos map dscp_2_queue item on one particular device. - * @param[in] dev_id device id - * @param[in] dscp dscp - * @param[out] queue queue id - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -horus_cosmap_dscp_queue_get(a_uint32_t dev_id, a_uint32_t dscp, - fal_queue_t * queue) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _horus_cosmap_dscp_queue_get(dev_id, dscp, queue); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Set port qos mode on a particular port. - * @param[in] dev_id device id - * @param[in] port_id port id - * @param[in] mode qos mode - * @param[in] enable A_TRUE of A_FALSE - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -horus_qos_port_mode_set(a_uint32_t dev_id, fal_port_t port_id, - fal_qos_mode_t mode, a_bool_t enable) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _horus_qos_port_mode_set(dev_id, port_id, mode, enable); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Get port qos mode on a particular port. - * @param[in] dev_id device id - * @param[in] port_id port id - * @param[in] mode qos mode - * @param[out] enable A_TRUE of A_FALSE - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -horus_qos_port_mode_get(a_uint32_t dev_id, fal_port_t port_id, - fal_qos_mode_t mode, a_bool_t * enable) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _horus_qos_port_mode_get(dev_id, port_id, mode, enable); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Set priority of one particular qos mode on one particular port. - * @details Comments: - If the priority of a mode is more small then the priority is more high. - Differnet mode should have differnet priority. - * @param[in] dev_id device id - * @param[in] port_id port id - * @param[in] mode qos mode - * @param[in] pri priority of one particular qos mode - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -horus_qos_port_mode_pri_set(a_uint32_t dev_id, fal_port_t port_id, - fal_qos_mode_t mode, a_uint32_t pri) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _horus_qos_port_mode_pri_set(dev_id, port_id, mode, pri); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Get priority of one particular qos mode on one particular port. - * @param[in] dev_id device id - * @param[in] port_id port id - * @param[in] mode qos mode - * @param[out] pri priority of one particular qos mode - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -horus_qos_port_mode_pri_get(a_uint32_t dev_id, fal_port_t port_id, - fal_qos_mode_t mode, a_uint32_t * pri) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _horus_qos_port_mode_pri_get(dev_id, port_id, mode, pri); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Set default user priority on one particular port. - * @param[in] dev_id device id - * @param[in] port_id port id - * @param[in] up 802.1p - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -horus_qos_port_default_up_set(a_uint32_t dev_id, fal_port_t port_id, - a_uint32_t up) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _horus_qos_port_default_up_set(dev_id, port_id, up); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Get default user priority on one particular port. - * @param[in] dev_id device id - * @param[in] port_id port id - * @param[out] up 802.1p - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -horus_qos_port_default_up_get(a_uint32_t dev_id, fal_port_t port_id, - a_uint32_t * up) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _horus_qos_port_default_up_get(dev_id, port_id, up); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Set traffic scheduling mode on particular one port. - * @details Comments: - * When scheduling mode is sp the weight is meaningless usually it's zero - * @param[in] dev_id device id - * @param[in] port_id port id - * @param[in] fal_sch_mode_t traffic scheduling mode - * @param[in] weight[] weight value for each queue when in wrr mode, - Horus only support fixed weight 1:2:4:8 for four queues. - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -horus_qos_port_sch_mode_set(a_uint32_t dev_id, a_uint32_t port_id, - fal_sch_mode_t mode, const a_uint32_t weight[]) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _horus_qos_port_sch_mode_set(dev_id, port_id, mode, weight); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Get traffic scheduling mode on particular port. - * @param[in] dev_id device id - * @param[in] port_id port id - * @param[out] fal_sch_mode_t traffic scheduling mode - * @param[out] weight weight value for wrr mode - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -horus_qos_port_sch_mode_get(a_uint32_t dev_id, a_uint32_t port_id, - fal_sch_mode_t * mode, a_uint32_t weight[]) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _horus_qos_port_sch_mode_get(dev_id, port_id, mode, weight); - HSL_API_UNLOCK; - return rv; -} - -sw_error_t -horus_qos_init(a_uint32_t dev_id) -{ - HSL_DEV_ID_CHECK(dev_id); - -#ifndef HSL_STANDALONG - { - hsl_api_t *p_api; - - SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id)); - - p_api->qos_queue_tx_buf_status_set = horus_qos_queue_tx_buf_status_set; - p_api->qos_queue_tx_buf_status_get = horus_qos_queue_tx_buf_status_get; - p_api->qos_port_tx_buf_status_set = horus_qos_port_tx_buf_status_set; - p_api->qos_port_tx_buf_status_get = horus_qos_port_tx_buf_status_get; - p_api->qos_queue_tx_buf_nr_set = horus_qos_queue_tx_buf_nr_set; - p_api->qos_queue_tx_buf_nr_get = horus_qos_queue_tx_buf_nr_get; - p_api->qos_port_tx_buf_nr_set = horus_qos_port_tx_buf_nr_set; - p_api->qos_port_tx_buf_nr_get = horus_qos_port_tx_buf_nr_get; - p_api->qos_port_rx_buf_nr_set = horus_qos_port_rx_buf_nr_set; - p_api->qos_port_rx_buf_nr_get = horus_qos_port_rx_buf_nr_get; - p_api->cosmap_up_queue_set = horus_cosmap_up_queue_set; - p_api->cosmap_up_queue_get = horus_cosmap_up_queue_get; - p_api->cosmap_dscp_queue_set = horus_cosmap_dscp_queue_set; - p_api->cosmap_dscp_queue_get = horus_cosmap_dscp_queue_get; - p_api->qos_port_mode_set = horus_qos_port_mode_set; - p_api->qos_port_mode_get = horus_qos_port_mode_get; - p_api->qos_port_mode_pri_set = horus_qos_port_mode_pri_set; - p_api->qos_port_mode_pri_get = horus_qos_port_mode_pri_get; - p_api->qos_port_default_up_set = horus_qos_port_default_up_set; - p_api->qos_port_default_up_get = horus_qos_port_default_up_get; - p_api->qos_port_sch_mode_set = horus_qos_port_sch_mode_set; - p_api->qos_port_sch_mode_get = horus_qos_port_sch_mode_get; - } -#endif - - return SW_OK; -} - -/** - * @} - */ diff --git a/feeds/ipq807x/qca-ssdk/src/src/hsl/horus/horus_rate.c b/feeds/ipq807x/qca-ssdk/src/src/hsl/horus/horus_rate.c deleted file mode 100755 index acb1fb0c1..000000000 --- a/feeds/ipq807x/qca-ssdk/src/src/hsl/horus/horus_rate.c +++ /dev/null @@ -1,578 +0,0 @@ -/* - * Copyright (c) 2012, The Linux Foundation. All rights reserved. - * Permission to use, copy, modify, and/or distribute this software for - * any purpose with or without fee is hereby granted, provided that the - * above copyright notice and this permission notice appear in all copies. - * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES - * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR - * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES - * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN - * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT - * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. - */ - - -/** - * @defgroup horus_rate HORUS_RATE - * @{ - */ -#include "sw.h" -#include "hsl.h" -#include "hsl_dev.h" -#include "hsl_port_prop.h" -#include "horus_rate.h" -#include "horus_reg.h" - -#define HORUS_STORM_MIN_RATE_PPS 1000 -#define HORUS_STORM_MAX_RATE_PPS (1024 * 1000) - -static sw_error_t -horus_stormrate_sw_to_hw(a_uint32_t swrate, a_uint32_t * hwrate) -{ - a_uint32_t shrnr = 0; - a_uint32_t tmp = swrate / 1000; - - if ((HORUS_STORM_MIN_RATE_PPS > swrate) - || (HORUS_STORM_MAX_RATE_PPS < swrate)) - { - return SW_BAD_PARAM; - } - - while ((tmp != 0) && (shrnr < 12)) - { - tmp = tmp >> 1; - shrnr++; - } - - if (12 == shrnr) - { - return SW_BAD_PARAM; - } - - *hwrate = shrnr; - return SW_OK; -} - -static sw_error_t -horus_stormrate_hw_to_sw(a_uint32_t hwrate, a_uint32_t * swrate) -{ - if (0 == hwrate) - { - hwrate = 1; - } - - if ((1 > hwrate) || (11 < hwrate)) - { - return SW_BAD_PARAM; - } - - *swrate = (1 << (hwrate - 1)) * 1000; - return SW_OK; -} - -static sw_error_t -_horus_rate_port_egrl_set(a_uint32_t dev_id, fal_port_t port_id, - a_uint32_t * speed, a_bool_t enable) -{ - sw_error_t rv; - a_uint32_t val; - - HSL_DEV_ID_CHECK(dev_id); - - if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU)) - { - return SW_BAD_PARAM; - } - - if (A_FALSE == enable) - { - *speed = 0; - - val = 0x1fff; - HSL_REG_FIELD_SET(rv, dev_id, RATE_LIMIT1, port_id, EG_RATE, - (a_uint8_t *) (&val), sizeof (a_uint32_t)); - } - else - { - if ((0x1ffe << 5) < *speed) - { - return SW_BAD_PARAM; - } - - val = *speed >> 5; - *speed = val << 5; - HSL_REG_FIELD_SET(rv, dev_id, RATE_LIMIT1, port_id, EG_RATE, - (a_uint8_t *) (&val), sizeof (a_uint32_t)); - } - - return rv; -} - -static sw_error_t -_horus_rate_port_egrl_get(a_uint32_t dev_id, fal_port_t port_id, - a_uint32_t * speed, a_bool_t * enable) -{ - sw_error_t rv; - a_uint32_t val; - - HSL_DEV_ID_CHECK(dev_id); - - if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU)) - { - return SW_BAD_PARAM; - } - - HSL_REG_FIELD_GET(rv, dev_id, RATE_LIMIT1, port_id, EG_RATE, - (a_uint8_t *) (&val), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - - if (0x1fff == val) - { - *speed = 0; - *enable = A_FALSE; - } - else - { - *enable = A_TRUE; - *speed = val << 5; - } - - return SW_OK; -} - -static sw_error_t -_horus_rate_port_inrl_set(a_uint32_t dev_id, fal_port_t port_id, - a_uint32_t * speed, a_bool_t enable) -{ - sw_error_t rv; - a_uint32_t val; - - HSL_DEV_ID_CHECK(dev_id); - - if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU)) - { - return SW_BAD_PARAM; - } - - if (A_TRUE == enable) - { - if ((0x7ffe << 5) < *speed) - { - return SW_BAD_PARAM; - } - val = *speed >> 5; - *speed = val << 5; - } - else if (A_FALSE == enable) - { - val = 0x7fff; - *speed = 0; - } - else - { - return SW_BAD_PARAM; - } - - HSL_REG_FIELD_SET(rv, dev_id, RATE_LIMIT0, port_id, ING_RATE, - (a_uint8_t *) (&val), sizeof (a_uint32_t)); - return rv; -} - -static sw_error_t -_horus_rate_port_inrl_get(a_uint32_t dev_id, fal_port_t port_id, - a_uint32_t * speed, a_bool_t * enable) -{ - sw_error_t rv; - a_uint32_t val; - - HSL_DEV_ID_CHECK(dev_id); - - if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU)) - { - return SW_BAD_PARAM; - } - - HSL_REG_FIELD_GET(rv, dev_id, RATE_LIMIT0, port_id, ING_RATE, - (a_uint8_t *) (&val), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - - if (0x7fff == val) - { - *enable = A_FALSE; - *speed = 0; - } - else - { - *enable = A_TRUE; - *speed = val << 5; - } - - return SW_OK; -} - -static sw_error_t -_horus_storm_ctrl_frame_set(a_uint32_t dev_id, fal_port_t port_id, - fal_storm_type_t storm_type, a_bool_t enable) -{ - a_uint32_t data; - sw_error_t rv; - - HSL_DEV_ID_CHECK(dev_id); - - if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU)) - { - return SW_BAD_PARAM; - } - - if (A_TRUE == enable) - { - data = 1; - } - else if (A_FALSE == enable) - { - data = 0; - } - else - { - return SW_BAD_PARAM; - } - - if (FAL_UNICAST_STORM == storm_type) - { - HSL_REG_FIELD_SET(rv, dev_id, STORM_CTL, port_id, UNI_EN, - (a_uint8_t *) (&data), sizeof (a_uint32_t)); - } - else if (FAL_MULTICAST_STORM == storm_type) - { - HSL_REG_FIELD_SET(rv, dev_id, STORM_CTL, port_id, MUL_EN, - (a_uint8_t *) (&data), sizeof (a_uint32_t)); - } - else if (FAL_BROADCAST_STORM == storm_type) - { - HSL_REG_FIELD_SET(rv, dev_id, STORM_CTL, port_id, BRO_EN, - (a_uint8_t *) (&data), sizeof (a_uint32_t)); - } - else - { - return SW_BAD_PARAM; - } - SW_RTN_ON_ERROR(rv); - - HSL_REG_FIELD_GET(rv, dev_id, STORM_CTL, port_id, RATE, - (a_uint8_t *) (&data), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - - if (0 == data) - { - data = 1; - HSL_REG_FIELD_SET(rv, dev_id, STORM_CTL, port_id, RATE, - (a_uint8_t *) (&data), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - } - - return SW_OK; -} - -static sw_error_t -_horus_storm_ctrl_frame_get(a_uint32_t dev_id, fal_port_t port_id, - fal_storm_type_t storm_type, a_bool_t * enable) -{ - a_uint32_t data; - sw_error_t rv; - - HSL_DEV_ID_CHECK(dev_id); - - if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU)) - { - return SW_BAD_PARAM; - } - - if (FAL_UNICAST_STORM == storm_type) - { - HSL_REG_FIELD_GET(rv, dev_id, STORM_CTL, port_id, UNI_EN, - (a_uint8_t *) (&data), sizeof (a_uint32_t)); - } - else if (FAL_MULTICAST_STORM == storm_type) - { - HSL_REG_FIELD_GET(rv, dev_id, STORM_CTL, port_id, MUL_EN, - (a_uint8_t *) (&data), sizeof (a_uint32_t)); - } - else if (FAL_BROADCAST_STORM == storm_type) - { - HSL_REG_FIELD_GET(rv, dev_id, STORM_CTL, port_id, BRO_EN, - (a_uint8_t *) (&data), sizeof (a_uint32_t)); - } - else - { - return SW_BAD_PARAM; - } - - SW_RTN_ON_ERROR(rv); - - if (1 == data) - { - data = 1; - *enable = A_TRUE; - } - else - { - *enable = A_FALSE; - } - - return SW_OK; -} - -static sw_error_t -_horus_storm_ctrl_rate_set(a_uint32_t dev_id, fal_port_t port_id, - a_uint32_t * rate_in_pps) -{ - a_uint32_t data; - sw_error_t rv; - - HSL_DEV_ID_CHECK(dev_id); - - if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU)) - { - return SW_BAD_PARAM; - } - - rv = horus_stormrate_sw_to_hw(*rate_in_pps, &data); - SW_RTN_ON_ERROR(rv); - - HSL_REG_FIELD_SET(rv, dev_id, STORM_CTL, port_id, RATE, - (a_uint8_t *) (&data), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - - rv = horus_stormrate_hw_to_sw(data, rate_in_pps); - SW_RTN_ON_ERROR(rv); - - return SW_OK; -} - -static sw_error_t -_horus_storm_ctrl_rate_get(a_uint32_t dev_id, fal_port_t port_id, - a_uint32_t * rate_in_pps) -{ - a_uint32_t data; - sw_error_t rv; - - HSL_DEV_ID_CHECK(dev_id); - - if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU)) - { - return SW_BAD_PARAM; - } - - HSL_REG_FIELD_GET(rv, dev_id, STORM_CTL, port_id, RATE, - (a_uint8_t *) (&data), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - - rv = horus_stormrate_hw_to_sw(data, rate_in_pps); - return rv; -} - -/** - * @brief Set port egress rate limit status on one particular port. - * @details Comments: - The granularity of speed is bps. - Because of hardware granularity function will return actual speed in hardware. - When disable port egress rate limit input parameter speed is meaningless. - The step of speed is 32kbps. - * @param[in] dev_id device id - * @param[in] port_id port id - * @param speed rate limit speed - * @param[in] enable A_TRUE or A_FALSE - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -horus_rate_port_egrl_set(a_uint32_t dev_id, fal_port_t port_id, - a_uint32_t * speed, a_bool_t enable) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _horus_rate_port_egrl_set(dev_id, port_id, speed, enable); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Get port egress rate limit status on one particular port. - * @param[in] dev_id device id - * @param[in] port_id port id - * @param[out] speed rate limit speed - * @param[out] enable A_TRUE or A_FALSE - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -horus_rate_port_egrl_get(a_uint32_t dev_id, fal_port_t port_id, - a_uint32_t * speed, a_bool_t * enable) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _horus_rate_port_egrl_get(dev_id, port_id, speed, enable); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Set port ingress rate limit status on one particular port. - * @details Comments: - The granularity of speed is bps. - Because of hardware granularity function will return actual speed in hardware. - When disable port ingress rate limit input parameter speed is meaningless. - The step of speed is 32kbps. - * When disable port ingress rate limit input parameter speed is meaningless. - * @param[in] dev_id device id - * @param[in] port_id port id - * @param speed rate limit speed - * @param[in] enable A_TRUE or A_FALSE - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -horus_rate_port_inrl_set(a_uint32_t dev_id, fal_port_t port_id, - a_uint32_t * speed, a_bool_t enable) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _horus_rate_port_inrl_set(dev_id, port_id, speed, enable); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Get port ingress rate limit status on one particular port. - * @param[in] dev_id device id - * @param[in] port_id port id - * @param[out] speed rate limit speed - * @param[out] enable A_TRUE or A_FALSE - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -horus_rate_port_inrl_get(a_uint32_t dev_id, fal_port_t port_id, - a_uint32_t * speed, a_bool_t * enable) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _horus_rate_port_inrl_get(dev_id, port_id, speed, enable); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Set particular type storm control status on one particular port. - * @details Comments: - * When enable one particular packets type storm control this type packets - * speed will be calculated in storm control. - * @param[in] dev_id device id - * @param[in] port_id port id - * @param[in] frame_type packets type which causes storm - * @param[in] enable A_TRUE or A_FALSE - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -horus_storm_ctrl_frame_set(a_uint32_t dev_id, fal_port_t port_id, - fal_storm_type_t storm_type, a_bool_t enable) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _horus_storm_ctrl_frame_set(dev_id, port_id, storm_type, enable); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Get particular type storm control status on one particular port. - * @param[in] dev_id device id - * @param[in] port_id port id - * @param[in] frame_type packets type which causes storm - * @param[out] enable A_TRUE or A_FALSE - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -horus_storm_ctrl_frame_get(a_uint32_t dev_id, fal_port_t port_id, - fal_storm_type_t storm_type, a_bool_t * enable) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _horus_storm_ctrl_frame_get(dev_id, port_id, storm_type, enable); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Set storm control speed on one particular port. - * @details Comments: - Because of hardware granularity function will return actual speed in hardware. - The step of speed is kpps. - The speed range is from 1k to 1M - * @param[in] dev_id device id - * @param[in] port_id port id - * @param speed storm control speed - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -horus_storm_ctrl_rate_set(a_uint32_t dev_id, fal_port_t port_id, - a_uint32_t * rate_in_pps) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _horus_storm_ctrl_rate_set(dev_id, port_id, rate_in_pps); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Get storm control speed on one particular port. - * @param[in] dev_id device id - * @param[in] port_id port id - * @param[out] speed storm control speed - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -horus_storm_ctrl_rate_get(a_uint32_t dev_id, fal_port_t port_id, - a_uint32_t * rate_in_pps) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _horus_storm_ctrl_rate_get(dev_id, port_id, rate_in_pps); - HSL_API_UNLOCK; - return rv; -} - -sw_error_t -horus_rate_init(a_uint32_t dev_id) -{ - HSL_DEV_ID_CHECK(dev_id); - -#ifndef HSL_STANDALONG - { - hsl_api_t *p_api; - - SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id)); - - p_api->rate_port_egrl_set = horus_rate_port_egrl_set; - p_api->rate_port_egrl_get = horus_rate_port_egrl_get; - p_api->rate_port_inrl_set = horus_rate_port_inrl_set; - p_api->rate_port_inrl_get = horus_rate_port_inrl_get; - p_api->storm_ctrl_frame_set = horus_storm_ctrl_frame_set; - p_api->storm_ctrl_frame_get = horus_storm_ctrl_frame_get; - p_api->storm_ctrl_rate_set = horus_storm_ctrl_rate_set; - p_api->storm_ctrl_rate_get = horus_storm_ctrl_rate_get; - } -#endif - - return SW_OK; -} - -/** - * @} - */ diff --git a/feeds/ipq807x/qca-ssdk/src/src/hsl/horus/horus_reg_access.c b/feeds/ipq807x/qca-ssdk/src/src/hsl/horus/horus_reg_access.c deleted file mode 100755 index f8d4fae20..000000000 --- a/feeds/ipq807x/qca-ssdk/src/src/hsl/horus/horus_reg_access.c +++ /dev/null @@ -1,273 +0,0 @@ -/* - * Copyright (c) 2012, The Linux Foundation. All rights reserved. - * Permission to use, copy, modify, and/or distribute this software for - * any purpose with or without fee is hereby granted, provided that the - * above copyright notice and this permission notice appear in all copies. - * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES - * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR - * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES - * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN - * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT - * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. - */ - - -#include "sw.h" -#include "hsl.h" -#include "hsl_dev.h" -#include "sd.h" -#include "horus_reg_access.h" - -static hsl_access_mode reg_mode; - -#if defined(API_LOCK) -static aos_lock_t mdio_lock; -#define MDIO_LOCKER_INIT aos_lock_init(&mdio_lock) -#define MDIO_LOCKER_LOCK aos_lock(&mdio_lock) -#define MDIO_LOCKER_UNLOCK aos_unlock(&mdio_lock) -#else -#define MDIO_LOCKER_INIT -#define MDIO_LOCKER_LOCK -#define MDIO_LOCKER_UNLOCK -#endif - -static sw_error_t -_horus_mdio_reg_get(a_uint32_t dev_id, a_uint32_t reg_addr, - a_uint8_t value[], a_uint32_t value_len) -{ - a_uint32_t reg_word_addr; - a_uint32_t phy_addr, reg_val; - a_uint16_t phy_val, tmp_val; - a_uint8_t phy_reg; - sw_error_t rv; - - if (value_len != sizeof (a_uint32_t)) - return SW_BAD_LEN; - - /* change reg_addr to 16-bit word address, 32-bit aligned */ - reg_word_addr = (reg_addr & 0xfffffffc) >> 1; - - /* configure register high address */ - phy_addr = 0x18; - phy_reg = 0x0; - phy_val = (a_uint16_t) ((reg_word_addr >> 8) & 0x3ff); /* bit16-8 of reg address */ - - rv = sd_reg_mdio_set(dev_id, phy_addr, phy_reg, phy_val); - SW_RTN_ON_ERROR(rv); - - /* For some registers such as MIBs, since it is read/clear, we should */ - /* read the lower 16-bit register then the higher one */ - - /* read register in lower address */ - phy_addr = 0x10 | ((reg_word_addr >> 5) & 0x7); /* bit7-5 of reg address */ - phy_reg = (a_uint8_t) (reg_word_addr & 0x1f); /* bit4-0 of reg address */ - rv = sd_reg_mdio_get(dev_id, phy_addr, phy_reg, &tmp_val); - SW_RTN_ON_ERROR(rv); - reg_val = tmp_val; - - /* read register in higher address */ - reg_word_addr++; - phy_addr = 0x10 | ((reg_word_addr >> 5) & 0x7); /* bit7-5 of reg address */ - phy_reg = (a_uint8_t) (reg_word_addr & 0x1f); /* bit4-0 of reg address */ - rv = sd_reg_mdio_get(dev_id, phy_addr, phy_reg, &tmp_val); - SW_RTN_ON_ERROR(rv); - reg_val |= (((a_uint32_t)tmp_val) << 16); - - aos_mem_copy(value, ®_val, sizeof (a_uint32_t)); - - return SW_OK; -} - -static sw_error_t -_horus_mdio_reg_set(a_uint32_t dev_id, a_uint32_t reg_addr, a_uint8_t value[], - a_uint32_t value_len) -{ - a_uint32_t reg_word_addr; - a_uint32_t phy_addr, reg_val; - a_uint16_t phy_val; - a_uint8_t phy_reg; - sw_error_t rv; - - if (value_len != sizeof (a_uint32_t)) - return SW_BAD_LEN; - - aos_mem_copy(®_val, value, sizeof (a_uint32_t)); - - /* change reg_addr to 16-bit word address, 32-bit aligned */ - reg_word_addr = (reg_addr & 0xfffffffc) >> 1; - - /* configure register high address */ - phy_addr = 0x18; - phy_reg = 0x0; - phy_val = (a_uint16_t) ((reg_word_addr >> 8) & 0x3ff); /* bit16-8 of reg address */ - - rv = sd_reg_mdio_set(dev_id, phy_addr, phy_reg, phy_val); - SW_RTN_ON_ERROR(rv); - - /* For some registers such as ARL and VLAN, since they include BUSY bit */ - /* in lower address, we should write the higher 16-bit register then the */ - /* lower one */ - - /* write register in higher address */ - reg_word_addr++; - phy_addr = 0x10 | ((reg_word_addr >> 5) & 0x7); /* bit7-5 of reg address */ - phy_reg = (a_uint8_t) (reg_word_addr & 0x1f); /* bit4-0 of reg address */ - phy_val = (a_uint16_t) ((reg_val >> 16) & 0xffff); - rv = sd_reg_mdio_set(dev_id, phy_addr, phy_reg, phy_val); - SW_RTN_ON_ERROR(rv); - - /* write register in lower address */ - reg_word_addr--; - phy_addr = 0x10 | ((reg_word_addr >> 5) & 0x7); /* bit7-5 of reg address */ - phy_reg = (a_uint8_t) (reg_word_addr & 0x1f); /* bit4-0 of reg address */ - phy_val = (a_uint16_t) (reg_val & 0xffff); - rv = sd_reg_mdio_set(dev_id, phy_addr, phy_reg, phy_val); - SW_RTN_ON_ERROR(rv); - - return SW_OK; -} - -sw_error_t -horus_phy_get(a_uint32_t dev_id, a_uint32_t phy_addr, - a_uint32_t reg, a_uint16_t * value) -{ - sw_error_t rv; - - MDIO_LOCKER_LOCK; - rv = sd_reg_mdio_get(dev_id, phy_addr, reg, value); - MDIO_LOCKER_UNLOCK; - - return rv; -} - -sw_error_t -horus_phy_set(a_uint32_t dev_id, a_uint32_t phy_addr, - a_uint32_t reg, a_uint16_t value) -{ - sw_error_t rv; - - MDIO_LOCKER_LOCK; - rv = sd_reg_mdio_set(dev_id, phy_addr, reg, value); - MDIO_LOCKER_UNLOCK; - - return rv; -} - -sw_error_t -horus_reg_get(a_uint32_t dev_id, a_uint32_t reg_addr, a_uint8_t value[], - a_uint32_t value_len) -{ - sw_error_t rv; - a_uint32_t flags; - - MDIO_LOCKER_LOCK; - if (HSL_MDIO == reg_mode) - { - aos_irq_save(flags); - rv = _horus_mdio_reg_get(dev_id, reg_addr, value, value_len); - aos_irq_restore(flags); - } - else - { - rv = sd_reg_hdr_get(dev_id, reg_addr, value, value_len); - } - MDIO_LOCKER_UNLOCK; - - return rv; -} - -sw_error_t -horus_reg_set(a_uint32_t dev_id, a_uint32_t reg_addr, a_uint8_t value[], - a_uint32_t value_len) -{ - sw_error_t rv; - a_uint32_t flags; - - MDIO_LOCKER_LOCK; - if (HSL_MDIO == reg_mode) - { - aos_irq_save(flags); - rv = _horus_mdio_reg_set(dev_id, reg_addr, value, value_len); - aos_irq_restore(flags); - } - else - { - rv = sd_reg_hdr_set(dev_id, reg_addr, value, value_len); - } - MDIO_LOCKER_UNLOCK; - - return rv; -} - -sw_error_t -horus_reg_field_get(a_uint32_t dev_id, a_uint32_t reg_addr, - a_uint32_t bit_offset, a_uint32_t field_len, - a_uint8_t value[], a_uint32_t value_len) -{ - a_uint32_t reg_val = 0; - - if ((bit_offset >= 32 || (field_len > 32)) || (field_len == 0)) - return SW_OUT_OF_RANGE; - - if (value_len != sizeof (a_uint32_t)) - return SW_BAD_LEN; - - SW_RTN_ON_ERROR(horus_reg_get(dev_id, reg_addr, (a_uint8_t *) & reg_val, sizeof (a_uint32_t))); - - *((a_uint32_t *) value) = SW_REG_2_FIELD(reg_val, bit_offset, field_len); - return SW_OK; -} - -sw_error_t -horus_reg_field_set(a_uint32_t dev_id, a_uint32_t reg_addr, - a_uint32_t bit_offset, a_uint32_t field_len, - const a_uint8_t value[], a_uint32_t value_len) -{ - a_uint32_t reg_val; - a_uint32_t field_val = *((a_uint32_t *) value); - - if ((bit_offset >= 32 || (field_len > 32)) || (field_len == 0)) - return SW_OUT_OF_RANGE; - - if (value_len != sizeof (a_uint32_t)) - return SW_BAD_LEN; - - SW_RTN_ON_ERROR(horus_reg_get(dev_id, reg_addr, (a_uint8_t *) & reg_val, sizeof (a_uint32_t))); - - SW_REG_SET_BY_FIELD_U32(reg_val, field_val, bit_offset, field_len); - - SW_RTN_ON_ERROR(horus_reg_set(dev_id, reg_addr, (a_uint8_t *) & reg_val, sizeof (a_uint32_t))); - - return SW_OK; -} - -sw_error_t -horus_reg_access_init(a_uint32_t dev_id, hsl_access_mode mode) -{ - hsl_api_t *p_api; - - MDIO_LOCKER_INIT; - reg_mode = mode; - - SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id)); - - p_api->phy_get = horus_phy_get; - p_api->phy_set = horus_phy_set; - p_api->reg_get = horus_reg_get; - p_api->reg_set = horus_reg_set; - p_api->reg_field_get = horus_reg_field_get; - p_api->reg_field_set = horus_reg_field_set; - p_api->dev_access_set= horus_access_mode_set; - - return SW_OK; -} - -sw_error_t -horus_access_mode_set(a_uint32_t dev_id, hsl_access_mode mode) -{ - reg_mode = mode; - return SW_OK; - -} - diff --git a/feeds/ipq807x/qca-ssdk/src/src/hsl/horus/horus_stp.c b/feeds/ipq807x/qca-ssdk/src/src/hsl/horus/horus_stp.c deleted file mode 100755 index 0f4a97367..000000000 --- a/feeds/ipq807x/qca-ssdk/src/src/hsl/horus/horus_stp.c +++ /dev/null @@ -1,192 +0,0 @@ -/* - * Copyright (c) 2012, The Linux Foundation. All rights reserved. - * Permission to use, copy, modify, and/or distribute this software for - * any purpose with or without fee is hereby granted, provided that the - * above copyright notice and this permission notice appear in all copies. - * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES - * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR - * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES - * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN - * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT - * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. - */ - - -/** - * @defgroup horus_stp HORUS_STP - * @{ - */ -#include "sw.h" -#include "hsl.h" -#include "hsl_dev.h" -#include "hsl_port_prop.h" -#include "horus_stp.h" -#include "horus_reg.h" - -#define HORUS_PORT_DISABLED 0 -#define HORUS_STP_BLOCKING 1 -#define HORUS_STP_LISTENING 2 -#define HORUS_STP_LEARNING 3 -#define HORUS_STP_FARWARDING 4 - -static sw_error_t -_horus_stp_port_state_set(a_uint32_t dev_id, a_uint32_t st_id, - fal_port_t port_id, fal_stp_state_t state) -{ - sw_error_t rv; - a_uint32_t val; - - HSL_DEV_ID_CHECK(dev_id); - - if (FAL_SINGLE_STP_ID != st_id) - { - return SW_BAD_PARAM; - } - - if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_EXCL_CPU)) - { - return SW_BAD_PARAM; - } - - switch (state) - { - case FAL_STP_BLOKING: - val = HORUS_STP_BLOCKING; - break; - case FAL_STP_LISTENING: - val = HORUS_STP_LISTENING; - break; - case FAL_STP_LEARNING: - val = HORUS_STP_LEARNING; - break; - case FAL_STP_FARWARDING: - val = HORUS_STP_FARWARDING; - break; - case FAL_STP_DISABLED: - val = HORUS_PORT_DISABLED; - break; - default: - return SW_BAD_PARAM; - } - - HSL_REG_FIELD_SET(rv, dev_id, PORT_CTL, port_id, PORT_STATE, - (a_uint8_t *) (&val), sizeof (a_uint32_t)); - return rv; -} - -static sw_error_t -_horus_stp_port_state_get(a_uint32_t dev_id, a_uint32_t st_id, - fal_port_t port_id, fal_stp_state_t * state) -{ - sw_error_t rv; - a_uint32_t val; - - HSL_DEV_ID_CHECK(dev_id); - - if (FAL_SINGLE_STP_ID != st_id) - { - return SW_BAD_PARAM; - } - - if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_EXCL_CPU)) - { - return SW_BAD_PARAM; - } - - HSL_REG_FIELD_GET(rv, dev_id, PORT_CTL, port_id, PORT_STATE, - (a_uint8_t *) (&val), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - - switch (val) - { - case HORUS_STP_BLOCKING: - *state = FAL_STP_BLOKING; - break; - case HORUS_STP_LISTENING: - *state = FAL_STP_LISTENING; - break; - case HORUS_STP_LEARNING: - *state = FAL_STP_LEARNING; - break; - case HORUS_STP_FARWARDING: - *state = FAL_STP_FARWARDING; - break; - case HORUS_PORT_DISABLED: - *state = FAL_STP_DISABLED; - break; - default: - return SW_FAIL; - } - - return SW_OK; -} - -/** - * @brief Set port stp state on a particular spanning tree and port. - * @details Comments: - Garuda only support single spanning tree so st_id should be - FAL_SINGLE_STP_ID that is zero. - * @param[in] dev_id device id - * @param[in] st_id spanning tree id - * @param[in] port_id port id - * @param[in] state port state for spanning tree - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -horus_stp_port_state_set(a_uint32_t dev_id, a_uint32_t st_id, - fal_port_t port_id, fal_stp_state_t state) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _horus_stp_port_state_set(dev_id, st_id, port_id, state); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Get port stp state on a particular spanning tree and port. - * @details Comments: - Garuda only support single spanning tree so st_id should be - FAL_SINGLE_STP_ID that is zero. - * @param[in] dev_id device id - * @param[in] st_id spanning tree id - * @param[in] port_id port id - * @param[out] state port state for spanning tree - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -horus_stp_port_state_get(a_uint32_t dev_id, a_uint32_t st_id, - fal_port_t port_id, fal_stp_state_t * state) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _horus_stp_port_state_get(dev_id, st_id, port_id, state); - HSL_API_UNLOCK; - return rv; -} - -sw_error_t -horus_stp_init(a_uint32_t dev_id) -{ - HSL_DEV_ID_CHECK(dev_id); - -#ifndef HSL_STANDALONG - { - hsl_api_t *p_api; - - SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id)); - - p_api->stp_port_state_set = horus_stp_port_state_set; - p_api->stp_port_state_get = horus_stp_port_state_get; - } -#endif - - return SW_OK; -} - -/** - * @} - */ diff --git a/feeds/ipq807x/qca-ssdk/src/src/hsl/horus/horus_vlan.c b/feeds/ipq807x/qca-ssdk/src/src/hsl/horus/horus_vlan.c deleted file mode 100755 index 754194ffa..000000000 --- a/feeds/ipq807x/qca-ssdk/src/src/hsl/horus/horus_vlan.c +++ /dev/null @@ -1,518 +0,0 @@ -/* - * Copyright (c) 2012, The Linux Foundation. All rights reserved. - * Permission to use, copy, modify, and/or distribute this software for - * any purpose with or without fee is hereby granted, provided that the - * above copyright notice and this permission notice appear in all copies. - * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES - * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR - * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES - * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN - * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT - * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. - */ - - -/** - * @defgroup horus_vlan HORUS_VLAN - * @{ - */ -#include "sw.h" -#include "hsl.h" -#include "hsl_dev.h" -#include "hsl_port_prop.h" -#include "horus_vlan.h" -#include "horus_reg.h" - -#define MAX_VLAN_ID 4095 - -#define VLAN_FLUSH 1 -#define VLAN_LOAD_ENTRY 2 -#define VLAN_PURGE_ENTRY 3 -#define VLAN_REMOVE_PORT 4 -#define VLAN_NEXT_ENTRY 5 -#define VLAN_FIND_ENTRY 6 - -static void -horus_vlan_hw_to_sw(const a_uint32_t reg[], fal_vlan_t * vlan_entry) -{ - a_uint32_t data; - - SW_GET_FIELD_BY_REG(VLAN_TABLE_FUNC0, VT_PRI_EN, data, reg[0]); - if (1 == data) - { - vlan_entry->vid_pri_en = A_TRUE; - - SW_GET_FIELD_BY_REG(VLAN_TABLE_FUNC0, VT_PRI, data, reg[0]); - vlan_entry->vid_pri = data & 0xff; - } - else - { - vlan_entry->vid_pri_en = A_FALSE; - } - - SW_GET_FIELD_BY_REG(VLAN_TABLE_FUNC0, VLAN_ID, data, reg[0]); - vlan_entry->vid = data & 0xffff; - - SW_GET_FIELD_BY_REG(VLAN_TABLE_FUNC1, VID_MEM, data, reg[1]); - vlan_entry->mem_ports = data; - - SW_GET_FIELD_BY_REG(VLAN_TABLE_FUNC1, LEARN_DIS, data, reg[1]); - if (1 == data) - { - vlan_entry->learn_dis = A_TRUE; - } - else - { - vlan_entry->learn_dis = A_FALSE; - } - - return; -} - -static sw_error_t -horus_vlan_sw_to_hw(const fal_vlan_t * vlan_entry, a_uint32_t reg[]) -{ - if (A_TRUE == vlan_entry->vid_pri_en) - { - SW_SET_REG_BY_FIELD(VLAN_TABLE_FUNC0, VT_PRI_EN, 1, reg[0]); - SW_SET_REG_BY_FIELD(VLAN_TABLE_FUNC0, VT_PRI, vlan_entry->vid_pri, reg[0]); - } - else - { - SW_SET_REG_BY_FIELD(VLAN_TABLE_FUNC0, VT_PRI_EN, 0, reg[0]); - } - - SW_SET_REG_BY_FIELD(VLAN_TABLE_FUNC0, VLAN_ID, vlan_entry->vid, reg[0]); - - SW_SET_REG_BY_FIELD(VLAN_TABLE_FUNC1, VT_VALID, 1, reg[1]); - SW_SET_REG_BY_FIELD(VLAN_TABLE_FUNC1, VID_MEM, vlan_entry->mem_ports, reg[1]); - - if (A_TRUE == vlan_entry->learn_dis) - { - SW_SET_REG_BY_FIELD(VLAN_TABLE_FUNC1, LEARN_DIS, 1, reg[1]); - } - else - { - SW_SET_REG_BY_FIELD(VLAN_TABLE_FUNC1, LEARN_DIS, 0, reg[1]); - } - - if (0 != vlan_entry->u_ports) - { - return SW_BAD_VALUE; - } - - return SW_OK; -} - -static sw_error_t -horus_vlan_commit(a_uint32_t dev_id, a_uint32_t op) -{ - a_uint32_t vt_busy = 1, i = 0x1000, vt_full, val; - sw_error_t rv; - - while (vt_busy && --i) - { - HSL_REG_FIELD_GET(rv, dev_id, VLAN_TABLE_FUNC0, 0, VT_BUSY, - (a_uint8_t *) (&vt_busy), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - aos_udelay(5); - } - - if (i == 0) - return SW_BUSY; - - HSL_REG_ENTRY_GET(rv, dev_id, VLAN_TABLE_FUNC0, 0, - (a_uint8_t *) (&val), sizeof (a_uint32_t)); - SW_SET_REG_BY_FIELD(VLAN_TABLE_FUNC0, VT_FUNC, op, val); - SW_SET_REG_BY_FIELD(VLAN_TABLE_FUNC0, VT_BUSY, 1, val); - - HSL_REG_ENTRY_SET(rv, dev_id, VLAN_TABLE_FUNC0, 0, - (a_uint8_t *) (&val), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - - vt_busy = 1; - i = 0x1000; - while (vt_busy && --i) - { - HSL_REG_FIELD_GET(rv, dev_id, VLAN_TABLE_FUNC0, 0, VT_BUSY, - (a_uint8_t *) (&vt_busy), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - aos_udelay(5); - } - - if (i == 0) - return SW_FAIL; - - HSL_REG_FIELD_GET(rv, dev_id, VLAN_TABLE_FUNC0, 0, VT_FULL_VIO, - (a_uint8_t *) (&vt_full), sizeof (a_uint32_t)); - - SW_RTN_ON_ERROR(rv); - - if (vt_full) - { - val = 0x10; - HSL_REG_ENTRY_SET(rv, dev_id, VLAN_TABLE_FUNC0, 0, - (a_uint8_t *) (&val), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - if (VLAN_LOAD_ENTRY == op) - { - return SW_FULL; - } - else if (VLAN_PURGE_ENTRY == op) - { - return SW_NOT_FOUND; - } - } - - HSL_REG_FIELD_GET(rv, dev_id, VLAN_TABLE_FUNC1, 0, VT_VALID, - (a_uint8_t *) (&val), sizeof (a_uint32_t)); - - SW_RTN_ON_ERROR(rv); - - if (!val) - { - if (VLAN_FIND_ENTRY == op) - return SW_NOT_FOUND; - - if (VLAN_NEXT_ENTRY == op) - return SW_NO_MORE; - } - - return SW_OK; -} - -static sw_error_t -_horus_vlan_entry_append(a_uint32_t dev_id, const fal_vlan_t * vlan_entry) -{ - sw_error_t rv; - a_uint32_t reg[2] = { 0 }; - - HSL_DEV_ID_CHECK(dev_id); - - if ((vlan_entry->vid == 0) || (vlan_entry->vid > MAX_VLAN_ID)) - return SW_OUT_OF_RANGE; - - if (A_FALSE == hsl_mports_prop_check(dev_id, vlan_entry->mem_ports, HSL_PP_INCL_CPU)) - return SW_BAD_PARAM; - - rv = horus_vlan_sw_to_hw(vlan_entry, reg); - SW_RTN_ON_ERROR(rv); - - HSL_REG_ENTRY_SET(rv, dev_id, VLAN_TABLE_FUNC0, 0, - (a_uint8_t *) (®[0]), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - - HSL_REG_ENTRY_SET(rv, dev_id, VLAN_TABLE_FUNC1, 0, - (a_uint8_t *) (®[1]), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - - rv = horus_vlan_commit(dev_id, VLAN_LOAD_ENTRY); - return rv; -} - -static sw_error_t -_horus_vlan_create(a_uint32_t dev_id, a_uint16_t vlan_id) -{ - sw_error_t rv; - a_uint32_t entry = 0; - - HSL_DEV_ID_CHECK(dev_id); - - if ((vlan_id == 0) || (vlan_id > MAX_VLAN_ID)) - return SW_OUT_OF_RANGE; - - /* set default value for VLAN_TABLE_FUNC0, all 0 except vid */ - entry = 0; - SW_SET_REG_BY_FIELD(VLAN_TABLE_FUNC0, VLAN_ID, vlan_id, entry); - HSL_REG_ENTRY_SET(rv, dev_id, VLAN_TABLE_FUNC0, 0, - (a_uint8_t *) (&entry), sizeof (a_uint32_t)); - - SW_RTN_ON_ERROR(rv); - - /* set default value for VLAN_TABLE_FUNC1, all 0 */ - entry = 0; - SW_SET_REG_BY_FIELD(VLAN_TABLE_FUNC1, VT_VALID, 1, entry); - HSL_REG_ENTRY_SET(rv, dev_id, VLAN_TABLE_FUNC1, 0, - (a_uint8_t *) (&entry), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - - rv = horus_vlan_commit(dev_id, VLAN_LOAD_ENTRY); - return rv; -} - -static sw_error_t -_horus_vlan_next(a_uint32_t dev_id, a_uint16_t vlan_id, fal_vlan_t * p_vlan) -{ - sw_error_t rv; - a_uint32_t reg[2] = { 0 }; - - HSL_DEV_ID_CHECK(dev_id); - - if (vlan_id > MAX_VLAN_ID) - return SW_OUT_OF_RANGE; - - aos_mem_zero(p_vlan, sizeof (fal_vlan_t)); - - SW_SET_REG_BY_FIELD(VLAN_TABLE_FUNC0, VLAN_ID, vlan_id, reg[0]); - HSL_REG_ENTRY_SET(rv, dev_id, VLAN_TABLE_FUNC0, 0, - (a_uint8_t *) (®[0]), sizeof (a_uint32_t)); - - SW_RTN_ON_ERROR(rv); - - HSL_REG_ENTRY_SET(rv, dev_id, VLAN_TABLE_FUNC1, 0, - (a_uint8_t *) (®[1]), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - - rv = horus_vlan_commit(dev_id, VLAN_NEXT_ENTRY); - SW_RTN_ON_ERROR(rv); - - HSL_REG_ENTRY_GET(rv, dev_id, VLAN_TABLE_FUNC0, 0, - (a_uint8_t *) (®[0]), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - - HSL_REG_ENTRY_GET(rv, dev_id, VLAN_TABLE_FUNC1, 0, - (a_uint8_t *) (®[1]), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - - horus_vlan_hw_to_sw(reg, p_vlan); - - if (0 == p_vlan->vid) - return SW_NO_MORE; - else - return SW_OK; -} - -static sw_error_t -_horus_vlan_find(a_uint32_t dev_id, a_uint16_t vlan_id, fal_vlan_t * p_vlan) -{ - sw_error_t rv; - a_uint32_t reg[2] = { 0 }; - - HSL_DEV_ID_CHECK(dev_id); - - if ((vlan_id == 0) || (vlan_id > MAX_VLAN_ID)) - return SW_OUT_OF_RANGE; - - aos_mem_zero(p_vlan, sizeof (fal_vlan_t)); - - SW_SET_REG_BY_FIELD(VLAN_TABLE_FUNC0, VLAN_ID, vlan_id, reg[0]); - HSL_REG_ENTRY_SET(rv, dev_id, VLAN_TABLE_FUNC0, 0, - (a_uint8_t *) (®[0]), sizeof (a_uint32_t)); - - SW_RTN_ON_ERROR(rv); - - rv = horus_vlan_commit(dev_id, VLAN_FIND_ENTRY); - SW_RTN_ON_ERROR(rv); - - HSL_REG_ENTRY_GET(rv, dev_id, VLAN_TABLE_FUNC0, 0, - (a_uint8_t *) (®[0]), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - - HSL_REG_ENTRY_GET(rv, dev_id, VLAN_TABLE_FUNC1, 0, - (a_uint8_t *) (®[1]), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - - horus_vlan_hw_to_sw(reg, p_vlan); - - return SW_OK; -} - -static sw_error_t -_horus_vlan_member_update(a_uint32_t dev_id, a_uint16_t vlan_id, - fal_pbmp_t member, fal_pbmp_t u_member) -{ - sw_error_t rv; - a_uint32_t reg = 0; - - HSL_DEV_ID_CHECK(dev_id); - - if ((vlan_id == 0) || (vlan_id > MAX_VLAN_ID)) - return SW_OUT_OF_RANGE; - - if (A_FALSE == hsl_mports_prop_check(dev_id, member, HSL_PP_INCL_CPU)) - return SW_BAD_PARAM; - - if (u_member != 0) - return SW_BAD_PARAM; - - /* get vlan entry first */ - SW_SET_REG_BY_FIELD(VLAN_TABLE_FUNC0, VLAN_ID, vlan_id, reg); - HSL_REG_ENTRY_SET(rv, dev_id, VLAN_TABLE_FUNC0, 0, - (a_uint8_t *) (®), sizeof (a_uint32_t)); - - SW_RTN_ON_ERROR(rv); - - rv = horus_vlan_commit(dev_id, VLAN_FIND_ENTRY); - SW_RTN_ON_ERROR(rv); - - /* set vlan member for VLAN_TABLE_FUNC1 */ - HSL_REG_FIELD_SET(rv, dev_id, VLAN_TABLE_FUNC1, 0, VID_MEM, - (a_uint8_t *) (&member), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - - rv = horus_vlan_commit(dev_id, VLAN_LOAD_ENTRY); - /* when update port member through LOAD opration, hardware will - return VT_FULL_VIO, we should ignore it */ - if (SW_FULL == rv) - rv = SW_OK; - - return rv; -} - -static sw_error_t -_horus_vlan_delete(a_uint32_t dev_id, a_uint16_t vlan_id) -{ - sw_error_t rv; - a_uint32_t reg; - - HSL_DEV_ID_CHECK(dev_id); - - if ((vlan_id == 0) || (vlan_id > MAX_VLAN_ID)) - return SW_OUT_OF_RANGE; - - reg = (a_int32_t) vlan_id; - HSL_REG_FIELD_SET(rv, dev_id, VLAN_TABLE_FUNC0, 0, VLAN_ID, - (a_uint8_t *) (®), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - - rv = horus_vlan_commit(dev_id, VLAN_PURGE_ENTRY); - return rv; -} - -/** - * @brief Append a vlan entry on paticular device. - * @param[in] dev_id device id - * @param[in] vlan_entry vlan entry - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -horus_vlan_entry_append(a_uint32_t dev_id, const fal_vlan_t * vlan_entry) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _horus_vlan_entry_append(dev_id, vlan_entry); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Creat a vlan entry through vlan id on a paticular device. - * @details Comments: - * After this operation the member ports of the created vlan entry are null. - * @param[in] dev_id device id - * @param[in] vlan_id vlan id - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -horus_vlan_create(a_uint32_t dev_id, a_uint32_t vlan_id) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _horus_vlan_create(dev_id, vlan_id); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Next a vlan entry through vlan id on a paticular device. - * @details Comments: - * If the value of vid is zero this operation will get the first entry. - * @param[in] dev_id device id - * @param[in] vlan_id vlan id - * @param[out] p_vlan vlan entry - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -horus_vlan_next(a_uint32_t dev_id, a_uint32_t vlan_id, fal_vlan_t * p_vlan) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _horus_vlan_next(dev_id, vlan_id, p_vlan); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Find a vlan entry through vlan id on paticular device. - * @param[in] dev_id device id - * @param[in] vlan_id vlan id - * @param[out] p_vlan vlan entry - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -horus_vlan_find(a_uint32_t dev_id, a_uint32_t vlan_id, fal_vlan_t * p_vlan) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _horus_vlan_find(dev_id, vlan_id, p_vlan); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Update a vlan entry member port through vlan id on a paticular device. - * @param[in] dev_id device id - * @param[in] vlan_id vlan id - * @param[in] member member ports - * @param[in] u_member tagged or untagged infomation for member ports - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -horus_vlan_member_update(a_uint32_t dev_id, a_uint32_t vlan_id, - fal_pbmp_t member, fal_pbmp_t u_member) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _horus_vlan_member_update(dev_id, vlan_id, member, u_member); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Delete a vlan entry through vlan id on a paticular device. - * @param[in] dev_id device id - * @param[in] vlan_id vlan id - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -horus_vlan_delete(a_uint32_t dev_id, a_uint32_t vlan_id) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _horus_vlan_delete(dev_id, vlan_id); - HSL_API_UNLOCK; - return rv; -} - -sw_error_t -horus_vlan_init(a_uint32_t dev_id) -{ - HSL_DEV_ID_CHECK(dev_id); - -#ifndef HSL_STANDALONG - hsl_api_t *p_api; - - SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id)); - - p_api->vlan_entry_append = horus_vlan_entry_append; - p_api->vlan_creat = horus_vlan_create; - p_api->vlan_member_update = horus_vlan_member_update; - p_api->vlan_delete = horus_vlan_delete; - p_api->vlan_next = horus_vlan_next; - p_api->vlan_find = horus_vlan_find; - -#endif - - return SW_OK; -} - -/** - * @} - */ diff --git a/feeds/ipq807x/qca-ssdk/src/src/hsl/hppe/Makefile b/feeds/ipq807x/qca-ssdk/src/src/hsl/hppe/Makefile deleted file mode 100755 index 453b55dcd..000000000 --- a/feeds/ipq807x/qca-ssdk/src/src/hsl/hppe/Makefile +++ /dev/null @@ -1,110 +0,0 @@ -LOC_DIR=src/hsl/hppe -LIB=HSL - -include $(PRJ_PATH)/make/config.mk - -SRC_LIST=hppe_init.c hppe_reg_access.c hppe_global.c - -ifeq (TRUE, $(IN_FLOW)) - SRC_LIST+=hppe_flow.c -endif - -ifeq (TRUE, $(IN_IP)) - SRC_LIST+=hppe_ip.c -endif - -ifeq (TRUE, $(IN_QOS)) - SRC_LIST+=hppe_qos.c -endif - -ifeq (TRUE, $(IN_FDB)) - SRC_LIST+=hppe_fdb.c -endif - -ifeq (TRUE, $(IN_PORTVLAN)) - SRC_LIST+=hppe_portvlan.c -endif - -ifeq (TRUE, $(IN_STP)) - SRC_LIST+=hppe_stp.c -endif - -ifeq (TRUE, $(IN_QM)) - SRC_LIST+=hppe_qm.c -endif - -ifeq (TRUE, $(IN_VSI)) - SRC_LIST+=hppe_vsi.c -endif - -ifeq (TRUE, $(IN_SEC)) - SRC_LIST+=hppe_sec.c -endif - -ifeq (TRUE, $(IN_BM)) - SRC_LIST+=hppe_bm.c -endif - -ifeq (TRUE, $(IN_MIB)) - SRC_LIST+=hppe_mib.c hppe_xgmacmib.c -endif - -ifeq (TRUE, $(IN_SERVCODE)) - SRC_LIST+=hppe_servcode.c -endif - -ifeq (TRUE, $(IN_CTRLPKT)) - SRC_LIST+=hppe_ctrlpkt.c -endif - -ifeq (TRUE, $(IN_RSS_HASH)) - SRC_LIST+=hppe_rss.c -endif - -ifeq (TRUE, $(IN_PPPOE)) - SRC_LIST+=hppe_pppoe.c -endif - -ifeq (TRUE, $(IN_PORTCONTROL)) - SRC_LIST+=hppe_portctrl.c hppe_xgportctrl.c -endif - -ifeq (TRUE, $(IN_MIRROR)) - SRC_LIST+=hppe_mirror.c -endif - -ifeq (TRUE, $(IN_TRUNK)) - SRC_LIST+=hppe_trunk.c -endif - -ifeq (TRUE, $(IN_ACL)) - SRC_LIST+=hppe_acl.c -endif - -ifeq (TRUE, $(IN_POLICER)) - SRC_LIST+=hppe_policer.c -endif - -ifeq (TRUE, $(IN_SHAPER)) - SRC_LIST+=hppe_shaper.c -endif - -ifeq (TRUE, $(IN_UNIPHY)) - SRC_LIST+=hppe_uniphy.c -endif - -ifeq (, $(findstring HPPE, $(SUPPORT_CHIP))) - SRC_LIST= -ifneq (, $(filter MP, $(SUPPORT_CHIP))) - SRC_LIST=hppe_reg_access.c -ifeq (TRUE, $(IN_UNIPHY)) - SRC_LIST+=hppe_uniphy.c -endif -endif -endif - -include $(PRJ_PATH)/make/components.mk -include $(PRJ_PATH)/make/defs.mk -include $(PRJ_PATH)/make/target.mk - -all: dep obj diff --git a/feeds/ipq807x/qca-ssdk/src/src/hsl/hppe/hppe_acl.c b/feeds/ipq807x/qca-ssdk/src/src/hsl/hppe/hppe_acl.c deleted file mode 100755 index 6df9253c9..000000000 --- a/feeds/ipq807x/qca-ssdk/src/src/hsl/hppe/hppe_acl.c +++ /dev/null @@ -1,3164 +0,0 @@ -/* - * Copyright (c) 2016-2017, The Linux Foundation. All rights reserved. - * Permission to use, copy, modify, and/or distribute this software for - * any purpose with or without fee is hereby granted, provided that the - * above copyright notice and this permission notice appear in all copies. - * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES - * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR - * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES - * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN - * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT - * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. - */ - - -/** - * @defgroup - * @{ - */ -#include "sw.h" -#include "hsl.h" -#include "hppe_reg_access.h" -#include "hppe_acl_reg.h" -#include "hppe_acl.h" - -sw_error_t -hppe_non_ip_udf0_ctrl_reg_get( - a_uint32_t dev_id, - union udf_ctrl_reg_u *value) -{ - return hppe_reg_get( - dev_id, - IPR_CSR_BASE_ADDR + NON_IP_UDF0_CTRL_REG_ADDRESS, - &value->val); -} - -sw_error_t -hppe_non_ip_udf0_ctrl_reg_set( - a_uint32_t dev_id, - union udf_ctrl_reg_u *value) -{ - return hppe_reg_set( - dev_id, - IPR_CSR_BASE_ADDR + NON_IP_UDF0_CTRL_REG_ADDRESS, - value->val); -} - -sw_error_t -hppe_non_ip_udf1_ctrl_reg_get( - a_uint32_t dev_id, - union udf_ctrl_reg_u *value) -{ - return hppe_reg_get( - dev_id, - IPR_CSR_BASE_ADDR + NON_IP_UDF1_CTRL_REG_ADDRESS, - &value->val); -} - -sw_error_t -hppe_non_ip_udf1_ctrl_reg_set( - a_uint32_t dev_id, - union udf_ctrl_reg_u *value) -{ - return hppe_reg_set( - dev_id, - IPR_CSR_BASE_ADDR + NON_IP_UDF1_CTRL_REG_ADDRESS, - value->val); -} - -sw_error_t -hppe_non_ip_udf2_ctrl_reg_get( - a_uint32_t dev_id, - union udf_ctrl_reg_u *value) -{ - return hppe_reg_get( - dev_id, - IPR_CSR_BASE_ADDR + NON_IP_UDF2_CTRL_REG_ADDRESS, - &value->val); -} - -sw_error_t -hppe_non_ip_udf2_ctrl_reg_set( - a_uint32_t dev_id, - union udf_ctrl_reg_u *value) -{ - return hppe_reg_set( - dev_id, - IPR_CSR_BASE_ADDR + NON_IP_UDF2_CTRL_REG_ADDRESS, - value->val); -} - -sw_error_t -hppe_non_ip_udf3_ctrl_reg_get( - a_uint32_t dev_id, - union udf_ctrl_reg_u *value) -{ - return hppe_reg_get( - dev_id, - IPR_CSR_BASE_ADDR + NON_IP_UDF3_CTRL_REG_ADDRESS, - &value->val); -} - -sw_error_t -hppe_non_ip_udf3_ctrl_reg_set( - a_uint32_t dev_id, - union udf_ctrl_reg_u *value) -{ - return hppe_reg_set( - dev_id, - IPR_CSR_BASE_ADDR + NON_IP_UDF3_CTRL_REG_ADDRESS, - value->val); -} - -sw_error_t -hppe_ipv4_udf0_ctrl_reg_get( - a_uint32_t dev_id, - union udf_ctrl_reg_u *value) -{ - return hppe_reg_get( - dev_id, - IPR_CSR_BASE_ADDR + IPV4_UDF0_CTRL_REG_ADDRESS, - &value->val); -} - -sw_error_t -hppe_ipv4_udf0_ctrl_reg_set( - a_uint32_t dev_id, - union udf_ctrl_reg_u *value) -{ - return hppe_reg_set( - dev_id, - IPR_CSR_BASE_ADDR + IPV4_UDF0_CTRL_REG_ADDRESS, - value->val); -} - -sw_error_t -hppe_ipv4_udf1_ctrl_reg_get( - a_uint32_t dev_id, - union udf_ctrl_reg_u *value) -{ - return hppe_reg_get( - dev_id, - IPR_CSR_BASE_ADDR + IPV4_UDF1_CTRL_REG_ADDRESS, - &value->val); -} - -sw_error_t -hppe_ipv4_udf1_ctrl_reg_set( - a_uint32_t dev_id, - union udf_ctrl_reg_u *value) -{ - return hppe_reg_set( - dev_id, - IPR_CSR_BASE_ADDR + IPV4_UDF1_CTRL_REG_ADDRESS, - value->val); -} - -sw_error_t -hppe_ipv4_udf2_ctrl_reg_get( - a_uint32_t dev_id, - union udf_ctrl_reg_u *value) -{ - return hppe_reg_get( - dev_id, - IPR_CSR_BASE_ADDR + IPV4_UDF2_CTRL_REG_ADDRESS, - &value->val); -} - -sw_error_t -hppe_ipv4_udf2_ctrl_reg_set( - a_uint32_t dev_id, - union udf_ctrl_reg_u *value) -{ - return hppe_reg_set( - dev_id, - IPR_CSR_BASE_ADDR + IPV4_UDF2_CTRL_REG_ADDRESS, - value->val); -} - -sw_error_t -hppe_ipv4_udf3_ctrl_reg_get( - a_uint32_t dev_id, - union udf_ctrl_reg_u *value) -{ - return hppe_reg_get( - dev_id, - IPR_CSR_BASE_ADDR + IPV4_UDF3_CTRL_REG_ADDRESS, - &value->val); -} - -sw_error_t -hppe_ipv4_udf3_ctrl_reg_set( - a_uint32_t dev_id, - union udf_ctrl_reg_u *value) -{ - return hppe_reg_set( - dev_id, - IPR_CSR_BASE_ADDR + IPV4_UDF3_CTRL_REG_ADDRESS, - value->val); -} - -sw_error_t -hppe_ipv6_udf0_ctrl_reg_get( - a_uint32_t dev_id, - union udf_ctrl_reg_u *value) -{ - return hppe_reg_get( - dev_id, - IPR_CSR_BASE_ADDR + IPV6_UDF0_CTRL_REG_ADDRESS, - &value->val); -} - -sw_error_t -hppe_ipv6_udf0_ctrl_reg_set( - a_uint32_t dev_id, - union udf_ctrl_reg_u *value) -{ - return hppe_reg_set( - dev_id, - IPR_CSR_BASE_ADDR + IPV6_UDF0_CTRL_REG_ADDRESS, - value->val); -} - -sw_error_t -hppe_ipv6_udf1_ctrl_reg_get( - a_uint32_t dev_id, - union udf_ctrl_reg_u *value) -{ - return hppe_reg_get( - dev_id, - IPR_CSR_BASE_ADDR + IPV6_UDF1_CTRL_REG_ADDRESS, - &value->val); -} - -sw_error_t -hppe_ipv6_udf1_ctrl_reg_set( - a_uint32_t dev_id, - union udf_ctrl_reg_u *value) -{ - return hppe_reg_set( - dev_id, - IPR_CSR_BASE_ADDR + IPV6_UDF1_CTRL_REG_ADDRESS, - value->val); -} - -sw_error_t -hppe_ipv6_udf2_ctrl_reg_get( - a_uint32_t dev_id, - union udf_ctrl_reg_u *value) -{ - return hppe_reg_get( - dev_id, - IPR_CSR_BASE_ADDR + IPV6_UDF2_CTRL_REG_ADDRESS, - &value->val); -} - -sw_error_t -hppe_ipv6_udf2_ctrl_reg_set( - a_uint32_t dev_id, - union udf_ctrl_reg_u *value) -{ - return hppe_reg_set( - dev_id, - IPR_CSR_BASE_ADDR + IPV6_UDF2_CTRL_REG_ADDRESS, - value->val); -} - -sw_error_t -hppe_ipv6_udf3_ctrl_reg_get( - a_uint32_t dev_id, - union udf_ctrl_reg_u *value) -{ - return hppe_reg_get( - dev_id, - IPR_CSR_BASE_ADDR + IPV6_UDF3_CTRL_REG_ADDRESS, - &value->val); -} - -sw_error_t -hppe_ipv6_udf3_ctrl_reg_set( - a_uint32_t dev_id, - union udf_ctrl_reg_u *value) -{ - return hppe_reg_set( - dev_id, - IPR_CSR_BASE_ADDR + IPV6_UDF3_CTRL_REG_ADDRESS, - value->val); -} - -sw_error_t -hppe_non_ip_udf0_ctrl_reg_udf0_base_get( - a_uint32_t dev_id, - a_uint32_t *value) -{ - union udf_ctrl_reg_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_non_ip_udf0_ctrl_reg_get(dev_id, ®_val); - *value = reg_val.bf.udf_base; - return ret; -} - -sw_error_t -hppe_non_ip_udf0_ctrl_reg_udf0_base_set( - a_uint32_t dev_id, - a_uint32_t value) -{ - union udf_ctrl_reg_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_non_ip_udf0_ctrl_reg_get(dev_id, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.udf_base = value; - ret = hppe_non_ip_udf0_ctrl_reg_set(dev_id, ®_val); - return ret; -} - -sw_error_t -hppe_non_ip_udf0_ctrl_reg_udf0_offset_get( - a_uint32_t dev_id, - a_uint32_t *value) -{ - union udf_ctrl_reg_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_non_ip_udf0_ctrl_reg_get(dev_id, ®_val); - *value = reg_val.bf.udf_offset; - return ret; -} - -sw_error_t -hppe_non_ip_udf0_ctrl_reg_udf0_offset_set( - a_uint32_t dev_id, - a_uint32_t value) -{ - union udf_ctrl_reg_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_non_ip_udf0_ctrl_reg_get(dev_id, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.udf_offset = value; - ret = hppe_non_ip_udf0_ctrl_reg_set(dev_id, ®_val); - return ret; -} - -sw_error_t -hppe_non_ip_udf1_ctrl_reg_udf1_base_get( - a_uint32_t dev_id, - a_uint32_t *value) -{ - union udf_ctrl_reg_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_non_ip_udf1_ctrl_reg_get(dev_id, ®_val); - *value = reg_val.bf.udf_base; - return ret; -} - -sw_error_t -hppe_non_ip_udf1_ctrl_reg_udf1_base_set( - a_uint32_t dev_id, - a_uint32_t value) -{ - union udf_ctrl_reg_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_non_ip_udf1_ctrl_reg_get(dev_id, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.udf_base = value; - ret = hppe_non_ip_udf1_ctrl_reg_set(dev_id, ®_val); - return ret; -} - -sw_error_t -hppe_non_ip_udf1_ctrl_reg_udf1_offset_get( - a_uint32_t dev_id, - a_uint32_t *value) -{ - union udf_ctrl_reg_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_non_ip_udf1_ctrl_reg_get(dev_id, ®_val); - *value = reg_val.bf.udf_offset; - return ret; -} - -sw_error_t -hppe_non_ip_udf1_ctrl_reg_udf1_offset_set( - a_uint32_t dev_id, - a_uint32_t value) -{ - union udf_ctrl_reg_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_non_ip_udf1_ctrl_reg_get(dev_id, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.udf_offset = value; - ret = hppe_non_ip_udf1_ctrl_reg_set(dev_id, ®_val); - return ret; -} - -sw_error_t -hppe_non_ip_udf2_ctrl_reg_udf2_offset_get( - a_uint32_t dev_id, - a_uint32_t *value) -{ - union udf_ctrl_reg_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_non_ip_udf2_ctrl_reg_get(dev_id, ®_val); - *value = reg_val.bf.udf_offset; - return ret; -} - -sw_error_t -hppe_non_ip_udf2_ctrl_reg_udf2_offset_set( - a_uint32_t dev_id, - a_uint32_t value) -{ - union udf_ctrl_reg_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_non_ip_udf2_ctrl_reg_get(dev_id, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.udf_offset = value; - ret = hppe_non_ip_udf2_ctrl_reg_set(dev_id, ®_val); - return ret; -} - -sw_error_t -hppe_non_ip_udf2_ctrl_reg_udf2_base_get( - a_uint32_t dev_id, - a_uint32_t *value) -{ - union udf_ctrl_reg_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_non_ip_udf2_ctrl_reg_get(dev_id, ®_val); - *value = reg_val.bf.udf_base; - return ret; -} - -sw_error_t -hppe_non_ip_udf2_ctrl_reg_udf2_base_set( - a_uint32_t dev_id, - a_uint32_t value) -{ - union udf_ctrl_reg_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_non_ip_udf2_ctrl_reg_get(dev_id, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.udf_base = value; - ret = hppe_non_ip_udf2_ctrl_reg_set(dev_id, ®_val); - return ret; -} - -sw_error_t -hppe_non_ip_udf3_ctrl_reg_udf3_base_get( - a_uint32_t dev_id, - a_uint32_t *value) -{ - union udf_ctrl_reg_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_non_ip_udf3_ctrl_reg_get(dev_id, ®_val); - *value = reg_val.bf.udf_base; - return ret; -} - -sw_error_t -hppe_non_ip_udf3_ctrl_reg_udf3_base_set( - a_uint32_t dev_id, - a_uint32_t value) -{ - union udf_ctrl_reg_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_non_ip_udf3_ctrl_reg_get(dev_id, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.udf_base = value; - ret = hppe_non_ip_udf3_ctrl_reg_set(dev_id, ®_val); - return ret; -} - -sw_error_t -hppe_non_ip_udf3_ctrl_reg_udf3_offset_get( - a_uint32_t dev_id, - a_uint32_t *value) -{ - union udf_ctrl_reg_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_non_ip_udf3_ctrl_reg_get(dev_id, ®_val); - *value = reg_val.bf.udf_offset; - return ret; -} - -sw_error_t -hppe_non_ip_udf3_ctrl_reg_udf3_offset_set( - a_uint32_t dev_id, - a_uint32_t value) -{ - union udf_ctrl_reg_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_non_ip_udf3_ctrl_reg_get(dev_id, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.udf_offset = value; - ret = hppe_non_ip_udf3_ctrl_reg_set(dev_id, ®_val); - return ret; -} - -sw_error_t -hppe_ipv4_udf0_ctrl_reg_udf0_base_get( - a_uint32_t dev_id, - a_uint32_t *value) -{ - union udf_ctrl_reg_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_ipv4_udf0_ctrl_reg_get(dev_id, ®_val); - *value = reg_val.bf.udf_base; - return ret; -} - -sw_error_t -hppe_ipv4_udf0_ctrl_reg_udf0_base_set( - a_uint32_t dev_id, - a_uint32_t value) -{ - union udf_ctrl_reg_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_ipv4_udf0_ctrl_reg_get(dev_id, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.udf_base = value; - ret = hppe_ipv4_udf0_ctrl_reg_set(dev_id, ®_val); - return ret; -} - -sw_error_t -hppe_ipv4_udf0_ctrl_reg_udf0_offset_get( - a_uint32_t dev_id, - a_uint32_t *value) -{ - union udf_ctrl_reg_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_ipv4_udf0_ctrl_reg_get(dev_id, ®_val); - *value = reg_val.bf.udf_offset; - return ret; -} - -sw_error_t -hppe_ipv4_udf0_ctrl_reg_udf0_offset_set( - a_uint32_t dev_id, - a_uint32_t value) -{ - union udf_ctrl_reg_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_ipv4_udf0_ctrl_reg_get(dev_id, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.udf_offset = value; - ret = hppe_ipv4_udf0_ctrl_reg_set(dev_id, ®_val); - return ret; -} - -sw_error_t -hppe_ipv4_udf1_ctrl_reg_udf1_base_get( - a_uint32_t dev_id, - a_uint32_t *value) -{ - union udf_ctrl_reg_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_ipv4_udf1_ctrl_reg_get(dev_id, ®_val); - *value = reg_val.bf.udf_base; - return ret; -} - -sw_error_t -hppe_ipv4_udf1_ctrl_reg_udf1_base_set( - a_uint32_t dev_id, - a_uint32_t value) -{ - union udf_ctrl_reg_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_ipv4_udf1_ctrl_reg_get(dev_id, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.udf_base = value; - ret = hppe_ipv4_udf1_ctrl_reg_set(dev_id, ®_val); - return ret; -} - -sw_error_t -hppe_ipv4_udf1_ctrl_reg_udf1_offset_get( - a_uint32_t dev_id, - a_uint32_t *value) -{ - union udf_ctrl_reg_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_ipv4_udf1_ctrl_reg_get(dev_id, ®_val); - *value = reg_val.bf.udf_offset; - return ret; -} - -sw_error_t -hppe_ipv4_udf1_ctrl_reg_udf1_offset_set( - a_uint32_t dev_id, - a_uint32_t value) -{ - union udf_ctrl_reg_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_ipv4_udf1_ctrl_reg_get(dev_id, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.udf_offset = value; - ret = hppe_ipv4_udf1_ctrl_reg_set(dev_id, ®_val); - return ret; -} - -sw_error_t -hppe_ipv4_udf2_ctrl_reg_udf2_offset_get( - a_uint32_t dev_id, - a_uint32_t *value) -{ - union udf_ctrl_reg_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_ipv4_udf2_ctrl_reg_get(dev_id, ®_val); - *value = reg_val.bf.udf_offset; - return ret; -} - -sw_error_t -hppe_ipv4_udf2_ctrl_reg_udf2_offset_set( - a_uint32_t dev_id, - a_uint32_t value) -{ - union udf_ctrl_reg_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_ipv4_udf2_ctrl_reg_get(dev_id, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.udf_offset = value; - ret = hppe_ipv4_udf2_ctrl_reg_set(dev_id, ®_val); - return ret; -} - -sw_error_t -hppe_ipv4_udf2_ctrl_reg_udf2_base_get( - a_uint32_t dev_id, - a_uint32_t *value) -{ - union udf_ctrl_reg_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_ipv4_udf2_ctrl_reg_get(dev_id, ®_val); - *value = reg_val.bf.udf_base; - return ret; -} - -sw_error_t -hppe_ipv4_udf2_ctrl_reg_udf2_base_set( - a_uint32_t dev_id, - a_uint32_t value) -{ - union udf_ctrl_reg_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_ipv4_udf2_ctrl_reg_get(dev_id, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.udf_base = value; - ret = hppe_ipv4_udf2_ctrl_reg_set(dev_id, ®_val); - return ret; -} - -sw_error_t -hppe_ipv4_udf3_ctrl_reg_udf3_base_get( - a_uint32_t dev_id, - a_uint32_t *value) -{ - union udf_ctrl_reg_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_ipv4_udf3_ctrl_reg_get(dev_id, ®_val); - *value = reg_val.bf.udf_base; - return ret; -} - -sw_error_t -hppe_ipv4_udf3_ctrl_reg_udf3_base_set( - a_uint32_t dev_id, - a_uint32_t value) -{ - union udf_ctrl_reg_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_ipv4_udf3_ctrl_reg_get(dev_id, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.udf_base = value; - ret = hppe_ipv4_udf3_ctrl_reg_set(dev_id, ®_val); - return ret; -} - -sw_error_t -hppe_ipv4_udf3_ctrl_reg_udf3_offset_get( - a_uint32_t dev_id, - a_uint32_t *value) -{ - union udf_ctrl_reg_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_ipv4_udf3_ctrl_reg_get(dev_id, ®_val); - *value = reg_val.bf.udf_offset; - return ret; -} - -sw_error_t -hppe_ipv4_udf3_ctrl_reg_udf3_offset_set( - a_uint32_t dev_id, - a_uint32_t value) -{ - union udf_ctrl_reg_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_ipv4_udf3_ctrl_reg_get(dev_id, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.udf_offset = value; - ret = hppe_ipv4_udf3_ctrl_reg_set(dev_id, ®_val); - return ret; -} - -sw_error_t -hppe_ipv6_udf0_ctrl_reg_udf0_base_get( - a_uint32_t dev_id, - a_uint32_t *value) -{ - union udf_ctrl_reg_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_ipv6_udf0_ctrl_reg_get(dev_id, ®_val); - *value = reg_val.bf.udf_base; - return ret; -} - -sw_error_t -hppe_ipv6_udf0_ctrl_reg_udf0_base_set( - a_uint32_t dev_id, - a_uint32_t value) -{ - union udf_ctrl_reg_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_ipv6_udf0_ctrl_reg_get(dev_id, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.udf_base = value; - ret = hppe_ipv6_udf0_ctrl_reg_set(dev_id, ®_val); - return ret; -} - -sw_error_t -hppe_ipv6_udf0_ctrl_reg_udf0_offset_get( - a_uint32_t dev_id, - a_uint32_t *value) -{ - union udf_ctrl_reg_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_ipv6_udf0_ctrl_reg_get(dev_id, ®_val); - *value = reg_val.bf.udf_offset; - return ret; -} - -sw_error_t -hppe_ipv6_udf0_ctrl_reg_udf0_offset_set( - a_uint32_t dev_id, - a_uint32_t value) -{ - union udf_ctrl_reg_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_ipv6_udf0_ctrl_reg_get(dev_id, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.udf_offset = value; - ret = hppe_ipv6_udf0_ctrl_reg_set(dev_id, ®_val); - return ret; -} - -sw_error_t -hppe_ipv6_udf1_ctrl_reg_udf1_base_get( - a_uint32_t dev_id, - a_uint32_t *value) -{ - union udf_ctrl_reg_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_ipv6_udf1_ctrl_reg_get(dev_id, ®_val); - *value = reg_val.bf.udf_base; - return ret; -} - -sw_error_t -hppe_ipv6_udf1_ctrl_reg_udf1_base_set( - a_uint32_t dev_id, - a_uint32_t value) -{ - union udf_ctrl_reg_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_ipv6_udf1_ctrl_reg_get(dev_id, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.udf_base = value; - ret = hppe_ipv6_udf1_ctrl_reg_set(dev_id, ®_val); - return ret; -} - -sw_error_t -hppe_ipv6_udf1_ctrl_reg_udf1_offset_get( - a_uint32_t dev_id, - a_uint32_t *value) -{ - union udf_ctrl_reg_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_ipv6_udf1_ctrl_reg_get(dev_id, ®_val); - *value = reg_val.bf.udf_offset; - return ret; -} - -sw_error_t -hppe_ipv6_udf1_ctrl_reg_udf1_offset_set( - a_uint32_t dev_id, - a_uint32_t value) -{ - union udf_ctrl_reg_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_ipv6_udf1_ctrl_reg_get(dev_id, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.udf_offset = value; - ret = hppe_ipv6_udf1_ctrl_reg_set(dev_id, ®_val); - return ret; -} - -sw_error_t -hppe_ipv6_udf2_ctrl_reg_udf2_offset_get( - a_uint32_t dev_id, - a_uint32_t *value) -{ - union udf_ctrl_reg_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_ipv6_udf2_ctrl_reg_get(dev_id, ®_val); - *value = reg_val.bf.udf_offset; - return ret; -} - -sw_error_t -hppe_ipv6_udf2_ctrl_reg_udf2_offset_set( - a_uint32_t dev_id, - a_uint32_t value) -{ - union udf_ctrl_reg_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_ipv6_udf2_ctrl_reg_get(dev_id, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.udf_offset = value; - ret = hppe_ipv6_udf2_ctrl_reg_set(dev_id, ®_val); - return ret; -} - -sw_error_t -hppe_ipv6_udf2_ctrl_reg_udf2_base_get( - a_uint32_t dev_id, - a_uint32_t *value) -{ - union udf_ctrl_reg_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_ipv6_udf2_ctrl_reg_get(dev_id, ®_val); - *value = reg_val.bf.udf_base; - return ret; -} - -sw_error_t -hppe_ipv6_udf2_ctrl_reg_udf2_base_set( - a_uint32_t dev_id, - a_uint32_t value) -{ - union udf_ctrl_reg_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_ipv6_udf2_ctrl_reg_get(dev_id, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.udf_base = value; - ret = hppe_ipv6_udf2_ctrl_reg_set(dev_id, ®_val); - return ret; -} - -sw_error_t -hppe_ipv6_udf3_ctrl_reg_udf3_base_get( - a_uint32_t dev_id, - a_uint32_t *value) -{ - union udf_ctrl_reg_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_ipv6_udf3_ctrl_reg_get(dev_id, ®_val); - *value = reg_val.bf.udf_base; - return ret; -} - -sw_error_t -hppe_ipv6_udf3_ctrl_reg_udf3_base_set( - a_uint32_t dev_id, - a_uint32_t value) -{ - union udf_ctrl_reg_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_ipv6_udf3_ctrl_reg_get(dev_id, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.udf_base = value; - ret = hppe_ipv6_udf3_ctrl_reg_set(dev_id, ®_val); - return ret; -} - -sw_error_t -hppe_ipv6_udf3_ctrl_reg_udf3_offset_get( - a_uint32_t dev_id, - a_uint32_t *value) -{ - union udf_ctrl_reg_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_ipv6_udf3_ctrl_reg_get(dev_id, ®_val); - *value = reg_val.bf.udf_offset; - return ret; -} - -sw_error_t -hppe_ipv6_udf3_ctrl_reg_udf3_offset_set( - a_uint32_t dev_id, - a_uint32_t value) -{ - union udf_ctrl_reg_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_ipv6_udf3_ctrl_reg_get(dev_id, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.udf_offset = value; - ret = hppe_ipv6_udf3_ctrl_reg_set(dev_id, ®_val); - return ret; -} - -sw_error_t -hppe_ipo_rule_reg_get( - a_uint32_t dev_id, - a_uint32_t index, - union ipo_rule_reg_u *value) -{ - return hppe_reg_tbl_get( - dev_id, - IPO_CSR_BASE_ADDR + IPO_RULE_REG_ADDRESS + \ - index * IPO_RULE_REG_INC, - value->val, - 3); -} - -sw_error_t -hppe_ipo_rule_reg_set( - a_uint32_t dev_id, - a_uint32_t index, - union ipo_rule_reg_u *value) -{ - return hppe_reg_tbl_set( - dev_id, - IPO_CSR_BASE_ADDR + IPO_RULE_REG_ADDRESS + \ - index * IPO_RULE_REG_INC, - value->val, - 3); -} - -sw_error_t -hppe_ipo_mask_reg_get( - a_uint32_t dev_id, - a_uint32_t index, - union ipo_mask_reg_u *value) -{ - return hppe_reg_tbl_get( - dev_id, - IPO_CSR_BASE_ADDR + IPO_MASK_REG_ADDRESS + \ - index * IPO_MASK_REG_INC, - value->val, - 2); -} - -sw_error_t -hppe_ipo_mask_reg_set( - a_uint32_t dev_id, - a_uint32_t index, - union ipo_mask_reg_u *value) -{ - return hppe_reg_tbl_set( - dev_id, - IPO_CSR_BASE_ADDR + IPO_MASK_REG_ADDRESS + \ - index * IPO_MASK_REG_INC, - value->val, - 2); -} - -sw_error_t -hppe_rule_ext_1_reg_get( - a_uint32_t dev_id, - a_uint32_t index, - union rule_ext_1_reg_u *value) -{ - if (index >= RULE_EXT_1_REG_MAX_ENTRY) - return SW_OUT_OF_RANGE; - return hppe_reg_get( - dev_id, - IPO_CSR_BASE_ADDR + RULE_EXT_1_REG_ADDRESS + \ - index * RULE_EXT_1_REG_INC, - &value->val); -} - -sw_error_t -hppe_rule_ext_1_reg_set( - a_uint32_t dev_id, - a_uint32_t index, - union rule_ext_1_reg_u *value) -{ - return hppe_reg_set( - dev_id, - IPO_CSR_BASE_ADDR + RULE_EXT_1_REG_ADDRESS + \ - index * RULE_EXT_1_REG_INC, - value->val); -} - -sw_error_t -hppe_rule_ext_2_reg_get( - a_uint32_t dev_id, - a_uint32_t index, - union rule_ext_2_reg_u *value) -{ - if (index >= RULE_EXT_2_REG_MAX_ENTRY) - return SW_OUT_OF_RANGE; - return hppe_reg_get( - dev_id, - IPO_CSR_BASE_ADDR + RULE_EXT_2_REG_ADDRESS + \ - index * RULE_EXT_2_REG_INC, - &value->val); -} - -sw_error_t -hppe_rule_ext_2_reg_set( - a_uint32_t dev_id, - a_uint32_t index, - union rule_ext_2_reg_u *value) -{ - return hppe_reg_set( - dev_id, - IPO_CSR_BASE_ADDR + RULE_EXT_2_REG_ADDRESS + \ - index * RULE_EXT_2_REG_INC, - value->val); -} - -sw_error_t -hppe_rule_ext_4_reg_get( - a_uint32_t dev_id, - a_uint32_t index, - union rule_ext_4_reg_u *value) -{ - if (index >= RULE_EXT_4_REG_MAX_ENTRY) - return SW_OUT_OF_RANGE; - return hppe_reg_get( - dev_id, - IPO_CSR_BASE_ADDR + RULE_EXT_4_REG_ADDRESS + \ - index * RULE_EXT_4_REG_INC, - &value->val); -} - -sw_error_t -hppe_rule_ext_4_reg_set( - a_uint32_t dev_id, - a_uint32_t index, - union rule_ext_4_reg_u *value) -{ - return hppe_reg_set( - dev_id, - IPO_CSR_BASE_ADDR + RULE_EXT_4_REG_ADDRESS + \ - index * RULE_EXT_4_REG_INC, - value->val); -} - -sw_error_t -hppe_ipo_dbg_addr_reg_get( - a_uint32_t dev_id, - union ipo_dbg_addr_reg_u *value) -{ - return hppe_reg_get( - dev_id, - IPO_CSR_BASE_ADDR + IPO_DBG_ADDR_REG_ADDRESS, - &value->val); -} - -sw_error_t -hppe_ipo_dbg_addr_reg_set( - a_uint32_t dev_id, - union ipo_dbg_addr_reg_u *value) -{ - return hppe_reg_set( - dev_id, - IPO_CSR_BASE_ADDR + IPO_DBG_ADDR_REG_ADDRESS, - value->val); -} - -sw_error_t -hppe_ipo_dbg_data_reg_get( - a_uint32_t dev_id, - union ipo_dbg_data_reg_u *value) -{ - return hppe_reg_get( - dev_id, - IPO_CSR_BASE_ADDR + IPO_DBG_DATA_REG_ADDRESS, - &value->val); -} - -sw_error_t -hppe_ipo_dbg_data_reg_set( - a_uint32_t dev_id, - union ipo_dbg_data_reg_u *value) -{ - return SW_NOT_SUPPORTED; -} - -sw_error_t -hppe_ipo_spare_reg_reg_get( - a_uint32_t dev_id, - union ipo_spare_reg_reg_u *value) -{ - return hppe_reg_get( - dev_id, - IPO_CSR_BASE_ADDR + IPO_SPARE_REG_REG_ADDRESS, - &value->val); -} - -sw_error_t -hppe_ipo_spare_reg_reg_set( - a_uint32_t dev_id, - union ipo_spare_reg_reg_u *value) -{ - return hppe_reg_set( - dev_id, - IPO_CSR_BASE_ADDR + IPO_SPARE_REG_REG_ADDRESS, - value->val); -} - -sw_error_t -hppe_ipo_glb_hit_counter_reg_get( - a_uint32_t dev_id, - union ipo_glb_hit_counter_reg_u *value) -{ - return hppe_reg_get( - dev_id, - IPO_CSR_BASE_ADDR + IPO_GLB_HIT_COUNTER_REG_ADDRESS, - &value->val); -} - -sw_error_t -hppe_ipo_glb_hit_counter_reg_set( - a_uint32_t dev_id, - union ipo_glb_hit_counter_reg_u *value) -{ - return SW_NOT_SUPPORTED; -} - -sw_error_t -hppe_ipo_glb_miss_counter_reg_get( - a_uint32_t dev_id, - union ipo_glb_miss_counter_reg_u *value) -{ - return hppe_reg_get( - dev_id, - IPO_CSR_BASE_ADDR + IPO_GLB_MISS_COUNTER_REG_ADDRESS, - &value->val); -} - -sw_error_t -hppe_ipo_glb_miss_counter_reg_set( - a_uint32_t dev_id, - union ipo_glb_miss_counter_reg_u *value) -{ - return SW_NOT_SUPPORTED; -} - -sw_error_t -hppe_ipo_glb_bypass_counter_reg_get( - a_uint32_t dev_id, - union ipo_glb_bypass_counter_reg_u *value) -{ - return hppe_reg_get( - dev_id, - IPO_CSR_BASE_ADDR + IPO_GLB_BYPASS_COUNTER_REG_ADDRESS, - &value->val); -} - -sw_error_t -hppe_ipo_glb_bypass_counter_reg_set( - a_uint32_t dev_id, - union ipo_glb_bypass_counter_reg_u *value) -{ - return SW_NOT_SUPPORTED; -} - -sw_error_t -hppe_ipo_rule_reg_src_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union ipo_rule_reg_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_ipo_rule_reg_get(dev_id, index, ®_val); - *value = reg_val.bf.src_1 << 3 | \ - reg_val.bf.src_0; - return ret; -} - -sw_error_t -hppe_ipo_rule_reg_src_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - union ipo_rule_reg_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_ipo_rule_reg_get(dev_id, index, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.src_1 = value >> 3; - reg_val.bf.src_0 = value & (((a_uint64_t)1<<3)-1); - ret = hppe_ipo_rule_reg_set(dev_id, index, ®_val); - return ret; -} - -sw_error_t -hppe_ipo_rule_reg_inverse_en_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union ipo_rule_reg_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_ipo_rule_reg_get(dev_id, index, ®_val); - *value = reg_val.bf.inverse_en; - return ret; -} - -sw_error_t -hppe_ipo_rule_reg_inverse_en_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - union ipo_rule_reg_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_ipo_rule_reg_get(dev_id, index, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.inverse_en = value; - ret = hppe_ipo_rule_reg_set(dev_id, index, ®_val); - return ret; -} - -sw_error_t -hppe_ipo_rule_reg_rule_type_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union ipo_rule_reg_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_ipo_rule_reg_get(dev_id, index, ®_val); - *value = reg_val.bf.rule_type; - return ret; -} - -sw_error_t -hppe_ipo_rule_reg_rule_type_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - union ipo_rule_reg_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_ipo_rule_reg_get(dev_id, index, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.rule_type = value; - ret = hppe_ipo_rule_reg_set(dev_id, index, ®_val); - return ret; -} - -sw_error_t -hppe_ipo_rule_reg_src_type_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union ipo_rule_reg_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_ipo_rule_reg_get(dev_id, index, ®_val); - *value = reg_val.bf.src_type; - return ret; -} - -sw_error_t -hppe_ipo_rule_reg_src_type_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - union ipo_rule_reg_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_ipo_rule_reg_get(dev_id, index, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.src_type = value; - ret = hppe_ipo_rule_reg_set(dev_id, index, ®_val); - return ret; -} - -sw_error_t -hppe_ipo_rule_reg_range_en_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union ipo_rule_reg_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_ipo_rule_reg_get(dev_id, index, ®_val); - *value = reg_val.bf.range_en; - return ret; -} - -sw_error_t -hppe_ipo_rule_reg_range_en_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - union ipo_rule_reg_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_ipo_rule_reg_get(dev_id, index, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.range_en = value; - ret = hppe_ipo_rule_reg_set(dev_id, index, ®_val); - return ret; -} - -sw_error_t -hppe_ipo_rule_reg_post_routing_en_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union ipo_rule_reg_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_ipo_rule_reg_get(dev_id, index, ®_val); - *value = reg_val.bf.post_routing_en; - return ret; -} - -sw_error_t -hppe_ipo_rule_reg_post_routing_en_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - union ipo_rule_reg_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_ipo_rule_reg_get(dev_id, index, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.post_routing_en = value; - ret = hppe_ipo_rule_reg_set(dev_id, index, ®_val); - return ret; -} - -sw_error_t -hppe_ipo_rule_reg_fake_mac_header_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union ipo_rule_reg_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_ipo_rule_reg_get(dev_id, index, ®_val); - *value = reg_val.bf.fake_mac_header; - return ret; -} - -sw_error_t -hppe_ipo_rule_reg_fake_mac_header_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - union ipo_rule_reg_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_ipo_rule_reg_get(dev_id, index, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.fake_mac_header = value; - ret = hppe_ipo_rule_reg_set(dev_id, index, ®_val); - return ret; -} - -sw_error_t -hppe_ipo_rule_reg_res_chain_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union ipo_rule_reg_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_ipo_rule_reg_get(dev_id, index, ®_val); - *value = reg_val.bf.res_chain; - return ret; -} - -sw_error_t -hppe_ipo_rule_reg_res_chain_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - union ipo_rule_reg_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_ipo_rule_reg_get(dev_id, index, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.res_chain = value; - ret = hppe_ipo_rule_reg_set(dev_id, index, ®_val); - return ret; -} - -sw_error_t -hppe_ipo_rule_reg_pri_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union ipo_rule_reg_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_ipo_rule_reg_get(dev_id, index, ®_val); - *value = reg_val.bf.pri; - return ret; -} - -sw_error_t -hppe_ipo_rule_reg_pri_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - union ipo_rule_reg_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_ipo_rule_reg_get(dev_id, index, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.pri = value; - ret = hppe_ipo_rule_reg_set(dev_id, index, ®_val); - return ret; -} - -sw_error_t -hppe_ipo_rule_reg_rule_field_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint64_t *value) -{ - union ipo_rule_reg_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_ipo_rule_reg_get(dev_id, index, ®_val); - *value = (a_uint64_t)reg_val.bf.rule_field_1 << 32 | \ - reg_val.bf.rule_field_0; - return ret; -} - -sw_error_t -hppe_ipo_rule_reg_rule_field_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint64_t value) -{ - union ipo_rule_reg_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_ipo_rule_reg_get(dev_id, index, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.rule_field_1 = value >> 32; - reg_val.bf.rule_field_0 = value & (((a_uint64_t)1<<32)-1); - ret = hppe_ipo_rule_reg_set(dev_id, index, ®_val); - return ret; -} - -sw_error_t -hppe_ipo_mask_reg_maskfield_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint64_t *value) -{ - union ipo_mask_reg_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_ipo_mask_reg_get(dev_id, index, ®_val); - *value = (a_uint64_t)reg_val.bf.maskfield_1 << 32 | \ - reg_val.bf.maskfield_0; - return ret; -} - -sw_error_t -hppe_ipo_mask_reg_maskfield_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint64_t value) -{ - union ipo_mask_reg_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_ipo_mask_reg_get(dev_id, index, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.maskfield_1 = value >> 32; - reg_val.bf.maskfield_0 = value & (((a_uint64_t)1<<32)-1); - ret = hppe_ipo_mask_reg_set(dev_id, index, ®_val); - return ret; -} - -sw_error_t -hppe_rule_ext_1_reg_ext2_2_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union rule_ext_1_reg_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_rule_ext_1_reg_get(dev_id, index, ®_val); - *value = reg_val.bf.ext2_2; - return ret; -} - -sw_error_t -hppe_rule_ext_1_reg_ext2_2_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - union rule_ext_1_reg_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_rule_ext_1_reg_get(dev_id, index, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.ext2_2 = value; - ret = hppe_rule_ext_1_reg_set(dev_id, index, ®_val); - return ret; -} - -sw_error_t -hppe_rule_ext_1_reg_ext2_0_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union rule_ext_1_reg_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_rule_ext_1_reg_get(dev_id, index, ®_val); - *value = reg_val.bf.ext2_0; - return ret; -} - -sw_error_t -hppe_rule_ext_1_reg_ext2_0_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - union rule_ext_1_reg_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_rule_ext_1_reg_get(dev_id, index, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.ext2_0 = value; - ret = hppe_rule_ext_1_reg_set(dev_id, index, ®_val); - return ret; -} - -sw_error_t -hppe_rule_ext_1_reg_ext2_3_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union rule_ext_1_reg_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_rule_ext_1_reg_get(dev_id, index, ®_val); - *value = reg_val.bf.ext2_3; - return ret; -} - -sw_error_t -hppe_rule_ext_1_reg_ext2_3_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - union rule_ext_1_reg_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_rule_ext_1_reg_get(dev_id, index, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.ext2_3 = value; - ret = hppe_rule_ext_1_reg_set(dev_id, index, ®_val); - return ret; -} - -sw_error_t -hppe_rule_ext_1_reg_ext2_1_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union rule_ext_1_reg_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_rule_ext_1_reg_get(dev_id, index, ®_val); - *value = reg_val.bf.ext2_1; - return ret; -} - -sw_error_t -hppe_rule_ext_1_reg_ext2_1_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - union rule_ext_1_reg_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_rule_ext_1_reg_get(dev_id, index, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.ext2_1 = value; - ret = hppe_rule_ext_1_reg_set(dev_id, index, ®_val); - return ret; -} - -sw_error_t -hppe_rule_ext_2_reg_ext4_0_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union rule_ext_2_reg_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_rule_ext_2_reg_get(dev_id, index, ®_val); - *value = reg_val.bf.ext4_0; - return ret; -} - -sw_error_t -hppe_rule_ext_2_reg_ext4_0_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - union rule_ext_2_reg_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_rule_ext_2_reg_get(dev_id, index, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.ext4_0 = value; - ret = hppe_rule_ext_2_reg_set(dev_id, index, ®_val); - return ret; -} - -sw_error_t -hppe_rule_ext_2_reg_ext4_1_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union rule_ext_2_reg_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_rule_ext_2_reg_get(dev_id, index, ®_val); - *value = reg_val.bf.ext4_1; - return ret; -} - -sw_error_t -hppe_rule_ext_2_reg_ext4_1_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - union rule_ext_2_reg_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_rule_ext_2_reg_get(dev_id, index, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.ext4_1 = value; - ret = hppe_rule_ext_2_reg_set(dev_id, index, ®_val); - return ret; -} - -sw_error_t -hppe_rule_ext_4_reg_ext8_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union rule_ext_4_reg_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_rule_ext_4_reg_get(dev_id, index, ®_val); - *value = reg_val.bf.ext8; - return ret; -} - -sw_error_t -hppe_rule_ext_4_reg_ext8_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - union rule_ext_4_reg_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_rule_ext_4_reg_get(dev_id, index, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.ext8 = value; - ret = hppe_rule_ext_4_reg_set(dev_id, index, ®_val); - return ret; -} - -sw_error_t -hppe_ipo_dbg_addr_reg_ipo_dbg_addr_get( - a_uint32_t dev_id, - a_uint32_t *value) -{ - union ipo_dbg_addr_reg_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_ipo_dbg_addr_reg_get(dev_id, ®_val); - *value = reg_val.bf.ipo_dbg_addr; - return ret; -} - -sw_error_t -hppe_ipo_dbg_addr_reg_ipo_dbg_addr_set( - a_uint32_t dev_id, - a_uint32_t value) -{ - union ipo_dbg_addr_reg_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_ipo_dbg_addr_reg_get(dev_id, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.ipo_dbg_addr = value; - ret = hppe_ipo_dbg_addr_reg_set(dev_id, ®_val); - return ret; -} - -sw_error_t -hppe_ipo_dbg_data_reg_ipo_dbg_data_get( - a_uint32_t dev_id, - a_uint32_t *value) -{ - union ipo_dbg_data_reg_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_ipo_dbg_data_reg_get(dev_id, ®_val); - *value = reg_val.bf.ipo_dbg_data; - return ret; -} - -sw_error_t -hppe_ipo_dbg_data_reg_ipo_dbg_data_set( - a_uint32_t dev_id, - a_uint32_t value) -{ - return SW_NOT_SUPPORTED; -} - -sw_error_t -hppe_ipo_spare_reg_reg_spare_reg_get( - a_uint32_t dev_id, - a_uint32_t *value) -{ - union ipo_spare_reg_reg_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_ipo_spare_reg_reg_get(dev_id, ®_val); - *value = reg_val.bf.spare_reg; - return ret; -} - -sw_error_t -hppe_ipo_spare_reg_reg_spare_reg_set( - a_uint32_t dev_id, - a_uint32_t value) -{ - union ipo_spare_reg_reg_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_ipo_spare_reg_reg_get(dev_id, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.spare_reg = value; - ret = hppe_ipo_spare_reg_reg_set(dev_id, ®_val); - return ret; -} - -sw_error_t -hppe_ipo_glb_hit_counter_reg_hit_count_get( - a_uint32_t dev_id, - a_uint32_t *value) -{ - union ipo_glb_hit_counter_reg_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_ipo_glb_hit_counter_reg_get(dev_id, ®_val); - *value = reg_val.bf.hit_count; - return ret; -} - -sw_error_t -hppe_ipo_glb_hit_counter_reg_hit_count_set( - a_uint32_t dev_id, - a_uint32_t value) -{ - return SW_NOT_SUPPORTED; -} - -sw_error_t -hppe_ipo_glb_miss_counter_reg_miss_count_get( - a_uint32_t dev_id, - a_uint32_t *value) -{ - union ipo_glb_miss_counter_reg_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_ipo_glb_miss_counter_reg_get(dev_id, ®_val); - *value = reg_val.bf.miss_count; - return ret; -} - -sw_error_t -hppe_ipo_glb_miss_counter_reg_miss_count_set( - a_uint32_t dev_id, - a_uint32_t value) -{ - return SW_NOT_SUPPORTED; -} - -sw_error_t -hppe_ipo_glb_bypass_counter_reg_bypass_count_get( - a_uint32_t dev_id, - a_uint32_t *value) -{ - union ipo_glb_bypass_counter_reg_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_ipo_glb_bypass_counter_reg_get(dev_id, ®_val); - *value = reg_val.bf.bypass_count; - return ret; -} - -sw_error_t -hppe_ipo_glb_bypass_counter_reg_bypass_count_set( - a_uint32_t dev_id, - a_uint32_t value) -{ - return SW_NOT_SUPPORTED; -} - - -sw_error_t -hppe_ipo_cnt_tbl_get( - a_uint32_t dev_id, - a_uint32_t index, - union ipo_cnt_tbl_u *value) -{ - return hppe_reg_tbl_get( - dev_id, - INGRESS_POLICER_BASE_ADDR + IPO_CNT_TBL_ADDRESS + \ - index * IPO_CNT_TBL_INC, - value->val, - 3); -} - -sw_error_t -hppe_ipo_cnt_tbl_set( - a_uint32_t dev_id, - a_uint32_t index, - union ipo_cnt_tbl_u *value) -{ - return hppe_reg_tbl_set( - dev_id, - INGRESS_POLICER_BASE_ADDR + IPO_CNT_TBL_ADDRESS + \ - index * IPO_CNT_TBL_INC, - value->val, - 3); -} - -sw_error_t -hppe_ipo_cnt_tbl_hit_byte_cnt_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint64_t *value) -{ - union ipo_cnt_tbl_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_ipo_cnt_tbl_get(dev_id, index, ®_val); - *value = (a_uint64_t)reg_val.bf.hit_byte_cnt_1 << 32 | \ - reg_val.bf.hit_byte_cnt_0; - return ret; -} - -sw_error_t -hppe_ipo_cnt_tbl_hit_byte_cnt_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint64_t value) -{ - union ipo_cnt_tbl_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_ipo_cnt_tbl_get(dev_id, index, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.hit_byte_cnt_1 = value >> 32; - reg_val.bf.hit_byte_cnt_0 = value & (((a_uint64_t)1<<32)-1); - ret = hppe_ipo_cnt_tbl_set(dev_id, index, ®_val); - return ret; -} - -sw_error_t -hppe_ipo_cnt_tbl_hit_pkt_cnt_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union ipo_cnt_tbl_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_ipo_cnt_tbl_get(dev_id, index, ®_val); - *value = reg_val.bf.hit_pkt_cnt; - return ret; -} - -sw_error_t -hppe_ipo_cnt_tbl_hit_pkt_cnt_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - union ipo_cnt_tbl_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_ipo_cnt_tbl_get(dev_id, index, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.hit_pkt_cnt = value; - ret = hppe_ipo_cnt_tbl_set(dev_id, index, ®_val); - return ret; -} - - -sw_error_t -hppe_ipo_action_get( - a_uint32_t dev_id, - a_uint32_t index, - union ipo_action_u *value) -{ - return hppe_reg_tbl_get( - dev_id, - IPE_L2_BASE_ADDR + IPO_ACTION_ADDRESS + \ - index * IPO_ACTION_INC, - value->val, - 5); -} - -sw_error_t -hppe_ipo_action_set( - a_uint32_t dev_id, - a_uint32_t index, - union ipo_action_u *value) -{ - return hppe_reg_tbl_set( - dev_id, - IPE_L2_BASE_ADDR + IPO_ACTION_ADDRESS + \ - index * IPO_ACTION_INC, - value->val, - 5); -} - -sw_error_t -hppe_ipo_action_mirror_en_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union ipo_action_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_ipo_action_get(dev_id, index, ®_val); - *value = reg_val.bf.mirror_en; - return ret; -} - -sw_error_t -hppe_ipo_action_mirror_en_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - union ipo_action_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_ipo_action_get(dev_id, index, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.mirror_en = value; - ret = hppe_ipo_action_set(dev_id, index, ®_val); - return ret; -} - -sw_error_t -hppe_ipo_action_ctag_pcp_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union ipo_action_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_ipo_action_get(dev_id, index, ®_val); - *value = reg_val.bf.ctag_pcp_1 << 2 | \ - reg_val.bf.ctag_pcp_0; - return ret; -} - -sw_error_t -hppe_ipo_action_ctag_pcp_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - union ipo_action_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_ipo_action_get(dev_id, index, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.ctag_pcp_1 = value >> 2; - reg_val.bf.ctag_pcp_0 = value & (((a_uint64_t)1<<2)-1); - ret = hppe_ipo_action_set(dev_id, index, ®_val); - return ret; -} - -sw_error_t -hppe_ipo_action_int_dp_change_en_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union ipo_action_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_ipo_action_get(dev_id, index, ®_val); - *value = reg_val.bf.int_dp_change_en; - return ret; -} - -sw_error_t -hppe_ipo_action_int_dp_change_en_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - union ipo_action_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_ipo_action_get(dev_id, index, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.int_dp_change_en = value; - ret = hppe_ipo_action_set(dev_id, index, ®_val); - return ret; -} - -sw_error_t -hppe_ipo_action_enqueue_pri_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union ipo_action_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_ipo_action_get(dev_id, index, ®_val); - *value = reg_val.bf.enqueue_pri; - return ret; -} - -sw_error_t -hppe_ipo_action_enqueue_pri_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - union ipo_action_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_ipo_action_get(dev_id, index, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.enqueue_pri = value; - ret = hppe_ipo_action_set(dev_id, index, ®_val); - return ret; -} - -sw_error_t -hppe_ipo_action_stag_pcp_change_en_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union ipo_action_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_ipo_action_get(dev_id, index, ®_val); - *value = reg_val.bf.stag_pcp_change_en; - return ret; -} - -sw_error_t -hppe_ipo_action_stag_pcp_change_en_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - union ipo_action_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_ipo_action_get(dev_id, index, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.stag_pcp_change_en = value; - ret = hppe_ipo_action_set(dev_id, index, ®_val); - return ret; -} - -sw_error_t -hppe_ipo_action_dscp_tc_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union ipo_action_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_ipo_action_get(dev_id, index, ®_val); - *value = reg_val.bf.dscp_tc; - return ret; -} - -sw_error_t -hppe_ipo_action_dscp_tc_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - union ipo_action_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_ipo_action_get(dev_id, index, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.dscp_tc = value; - ret = hppe_ipo_action_set(dev_id, index, ®_val); - return ret; -} - -sw_error_t -hppe_ipo_action_cpu_code_en_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union ipo_action_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_ipo_action_get(dev_id, index, ®_val); - *value = reg_val.bf.cpu_code_en; - return ret; -} - -sw_error_t -hppe_ipo_action_cpu_code_en_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - union ipo_action_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_ipo_action_get(dev_id, index, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.cpu_code_en = value; - ret = hppe_ipo_action_set(dev_id, index, ®_val); - return ret; -} - -sw_error_t -hppe_ipo_action_stag_dei_change_en_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union ipo_action_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_ipo_action_get(dev_id, index, ®_val); - *value = reg_val.bf.stag_dei_change_en; - return ret; -} - -sw_error_t -hppe_ipo_action_stag_dei_change_en_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - union ipo_action_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_ipo_action_get(dev_id, index, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.stag_dei_change_en = value; - ret = hppe_ipo_action_set(dev_id, index, ®_val); - return ret; -} - -sw_error_t -hppe_ipo_action_ctag_fmt_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union ipo_action_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_ipo_action_get(dev_id, index, ®_val); - *value = reg_val.bf.ctag_fmt; - return ret; -} - -sw_error_t -hppe_ipo_action_ctag_fmt_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - union ipo_action_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_ipo_action_get(dev_id, index, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.ctag_fmt = value; - ret = hppe_ipo_action_set(dev_id, index, ®_val); - return ret; -} - -sw_error_t -hppe_ipo_action_dest_info_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union ipo_action_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_ipo_action_get(dev_id, index, ®_val); - *value = reg_val.bf.dest_info; - return ret; -} - -sw_error_t -hppe_ipo_action_dest_info_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - union ipo_action_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_ipo_action_get(dev_id, index, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.dest_info = value; - ret = hppe_ipo_action_set(dev_id, index, ®_val); - return ret; -} - -sw_error_t -hppe_ipo_action_svid_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union ipo_action_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_ipo_action_get(dev_id, index, ®_val); - *value = reg_val.bf.svid; - return ret; -} - -sw_error_t -hppe_ipo_action_svid_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - union ipo_action_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_ipo_action_get(dev_id, index, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.svid = value; - ret = hppe_ipo_action_set(dev_id, index, ®_val); - return ret; -} - -sw_error_t -hppe_ipo_action_dest_info_change_en_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union ipo_action_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_ipo_action_get(dev_id, index, ®_val); - *value = reg_val.bf.dest_info_change_en; - return ret; -} - -sw_error_t -hppe_ipo_action_dest_info_change_en_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - union ipo_action_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_ipo_action_get(dev_id, index, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.dest_info_change_en = value; - ret = hppe_ipo_action_set(dev_id, index, ®_val); - return ret; -} - -sw_error_t -hppe_ipo_action_policer_en_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union ipo_action_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_ipo_action_get(dev_id, index, ®_val); - *value = reg_val.bf.policer_en; - return ret; -} - -sw_error_t -hppe_ipo_action_policer_en_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - union ipo_action_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_ipo_action_get(dev_id, index, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.policer_en = value; - ret = hppe_ipo_action_set(dev_id, index, ®_val); - return ret; -} - -sw_error_t -hppe_ipo_action_int_dp_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union ipo_action_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_ipo_action_get(dev_id, index, ®_val); - *value = reg_val.bf.int_dp; - return ret; -} - -sw_error_t -hppe_ipo_action_int_dp_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - union ipo_action_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_ipo_action_get(dev_id, index, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.int_dp = value; - ret = hppe_ipo_action_set(dev_id, index, ®_val); - return ret; -} - -sw_error_t -hppe_ipo_action_ctag_pcp_change_en_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union ipo_action_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_ipo_action_get(dev_id, index, ®_val); - *value = reg_val.bf.ctag_pcp_change_en; - return ret; -} - -sw_error_t -hppe_ipo_action_ctag_pcp_change_en_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - union ipo_action_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_ipo_action_get(dev_id, index, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.ctag_pcp_change_en = value; - ret = hppe_ipo_action_set(dev_id, index, ®_val); - return ret; -} - -sw_error_t -hppe_ipo_action_metadata_en_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union ipo_action_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_ipo_action_get(dev_id, index, ®_val); - *value = reg_val.bf.metadata_en; - return ret; -} - -sw_error_t -hppe_ipo_action_metadata_en_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - union ipo_action_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_ipo_action_get(dev_id, index, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.metadata_en = value; - ret = hppe_ipo_action_set(dev_id, index, ®_val); - return ret; -} - -sw_error_t -hppe_ipo_action_enqueue_pri_change_en_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union ipo_action_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_ipo_action_get(dev_id, index, ®_val); - *value = reg_val.bf.enqueue_pri_change_en; - return ret; -} - -sw_error_t -hppe_ipo_action_enqueue_pri_change_en_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - union ipo_action_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_ipo_action_get(dev_id, index, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.enqueue_pri_change_en = value; - ret = hppe_ipo_action_set(dev_id, index, ®_val); - return ret; -} - -sw_error_t -hppe_ipo_action_stag_dei_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union ipo_action_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_ipo_action_get(dev_id, index, ®_val); - *value = reg_val.bf.stag_dei; - return ret; -} - -sw_error_t -hppe_ipo_action_stag_dei_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - union ipo_action_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_ipo_action_get(dev_id, index, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.stag_dei = value; - ret = hppe_ipo_action_set(dev_id, index, ®_val); - return ret; -} - -sw_error_t -hppe_ipo_action_fwd_cmd_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union ipo_action_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_ipo_action_get(dev_id, index, ®_val); - *value = reg_val.bf.fwd_cmd; - return ret; -} - -sw_error_t -hppe_ipo_action_fwd_cmd_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - union ipo_action_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_ipo_action_get(dev_id, index, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.fwd_cmd = value; - ret = hppe_ipo_action_set(dev_id, index, ®_val); - return ret; -} - -sw_error_t -hppe_ipo_action_bypass_bitmap_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union ipo_action_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_ipo_action_get(dev_id, index, ®_val); - *value = reg_val.bf.bypass_bitmap_1 << 14 | \ - reg_val.bf.bypass_bitmap_0; - return ret; -} - -sw_error_t -hppe_ipo_action_bypass_bitmap_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - union ipo_action_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_ipo_action_get(dev_id, index, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.bypass_bitmap_1 = value >> 14; - reg_val.bf.bypass_bitmap_0 = value & (((a_uint64_t)1<<14)-1); - ret = hppe_ipo_action_set(dev_id, index, ®_val); - return ret; -} - -sw_error_t -hppe_ipo_action_ctag_dei_change_en_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union ipo_action_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_ipo_action_get(dev_id, index, ®_val); - *value = reg_val.bf.ctag_dei_change_en; - return ret; -} - -sw_error_t -hppe_ipo_action_ctag_dei_change_en_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - union ipo_action_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_ipo_action_get(dev_id, index, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.ctag_dei_change_en = value; - ret = hppe_ipo_action_set(dev_id, index, ®_val); - return ret; -} - -sw_error_t -hppe_ipo_action_policer_index_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union ipo_action_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_ipo_action_get(dev_id, index, ®_val); - *value = reg_val.bf.policer_index; - return ret; -} - -sw_error_t -hppe_ipo_action_policer_index_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - union ipo_action_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_ipo_action_get(dev_id, index, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.policer_index = value; - ret = hppe_ipo_action_set(dev_id, index, ®_val); - return ret; -} - -sw_error_t -hppe_ipo_action_ctag_dei_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union ipo_action_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_ipo_action_get(dev_id, index, ®_val); - *value = reg_val.bf.ctag_dei; - return ret; -} - -sw_error_t -hppe_ipo_action_ctag_dei_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - union ipo_action_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_ipo_action_get(dev_id, index, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.ctag_dei = value; - ret = hppe_ipo_action_set(dev_id, index, ®_val); - return ret; -} - -sw_error_t -hppe_ipo_action_stag_pcp_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union ipo_action_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_ipo_action_get(dev_id, index, ®_val); - *value = reg_val.bf.stag_pcp; - return ret; -} - -sw_error_t -hppe_ipo_action_stag_pcp_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - union ipo_action_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_ipo_action_get(dev_id, index, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.stag_pcp = value; - ret = hppe_ipo_action_set(dev_id, index, ®_val); - return ret; -} - -sw_error_t -hppe_ipo_action_syn_toggle_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union ipo_action_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_ipo_action_get(dev_id, index, ®_val); - *value = reg_val.bf.syn_toggle; - return ret; -} - -sw_error_t -hppe_ipo_action_syn_toggle_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - union ipo_action_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_ipo_action_get(dev_id, index, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.syn_toggle = value; - ret = hppe_ipo_action_set(dev_id, index, ®_val); - return ret; -} - -sw_error_t -hppe_ipo_action_service_code_en_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union ipo_action_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_ipo_action_get(dev_id, index, ®_val); - *value = reg_val.bf.service_code_en; - return ret; -} - -sw_error_t -hppe_ipo_action_service_code_en_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - union ipo_action_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_ipo_action_get(dev_id, index, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.service_code_en = value; - ret = hppe_ipo_action_set(dev_id, index, ®_val); - return ret; -} - -sw_error_t -hppe_ipo_action_qid_en_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union ipo_action_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_ipo_action_get(dev_id, index, ®_val); - *value = reg_val.bf.qid_en; - return ret; -} - -sw_error_t -hppe_ipo_action_qid_en_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - union ipo_action_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_ipo_action_get(dev_id, index, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.qid_en = value; - ret = hppe_ipo_action_set(dev_id, index, ®_val); - return ret; -} - -sw_error_t -hppe_ipo_action_service_code_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union ipo_action_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_ipo_action_get(dev_id, index, ®_val); - *value = reg_val.bf.service_code_1 << 1 | \ - reg_val.bf.service_code_0; - return ret; -} - -sw_error_t -hppe_ipo_action_service_code_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - union ipo_action_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_ipo_action_get(dev_id, index, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.service_code_1 = value >> 1; - reg_val.bf.service_code_0 = value & (((a_uint64_t)1<<1)-1); - ret = hppe_ipo_action_set(dev_id, index, ®_val); - return ret; -} - -sw_error_t -hppe_ipo_action_cvid_change_en_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union ipo_action_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_ipo_action_get(dev_id, index, ®_val); - *value = reg_val.bf.cvid_change_en; - return ret; -} - -sw_error_t -hppe_ipo_action_cvid_change_en_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - union ipo_action_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_ipo_action_get(dev_id, index, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.cvid_change_en = value; - ret = hppe_ipo_action_set(dev_id, index, ®_val); - return ret; -} - -sw_error_t -hppe_ipo_action_cvid_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union ipo_action_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_ipo_action_get(dev_id, index, ®_val); - *value = reg_val.bf.cvid; - return ret; -} - -sw_error_t -hppe_ipo_action_cvid_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - union ipo_action_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_ipo_action_get(dev_id, index, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.cvid = value; - ret = hppe_ipo_action_set(dev_id, index, ®_val); - return ret; -} - -sw_error_t -hppe_ipo_action_svid_change_en_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union ipo_action_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_ipo_action_get(dev_id, index, ®_val); - *value = reg_val.bf.svid_change_en; - return ret; -} - -sw_error_t -hppe_ipo_action_svid_change_en_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - union ipo_action_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_ipo_action_get(dev_id, index, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.svid_change_en = value; - ret = hppe_ipo_action_set(dev_id, index, ®_val); - return ret; -} - -sw_error_t -hppe_ipo_action_cpu_code_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union ipo_action_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_ipo_action_get(dev_id, index, ®_val); - *value = reg_val.bf.cpu_code; - return ret; -} - -sw_error_t -hppe_ipo_action_cpu_code_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - union ipo_action_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_ipo_action_get(dev_id, index, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.cpu_code = value; - ret = hppe_ipo_action_set(dev_id, index, ®_val); - return ret; -} - -sw_error_t -hppe_ipo_action_dscp_tc_change_en_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union ipo_action_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_ipo_action_get(dev_id, index, ®_val); - *value = reg_val.bf.dscp_tc_change_en; - return ret; -} - -sw_error_t -hppe_ipo_action_dscp_tc_change_en_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - union ipo_action_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_ipo_action_get(dev_id, index, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.dscp_tc_change_en = value; - ret = hppe_ipo_action_set(dev_id, index, ®_val); - return ret; -} - -sw_error_t -hppe_ipo_action_qid_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union ipo_action_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_ipo_action_get(dev_id, index, ®_val); - *value = reg_val.bf.qid; - return ret; -} - -sw_error_t -hppe_ipo_action_qid_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - union ipo_action_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_ipo_action_get(dev_id, index, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.qid = value; - ret = hppe_ipo_action_set(dev_id, index, ®_val); - return ret; -} - -sw_error_t -hppe_ipo_action_stag_fmt_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union ipo_action_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_ipo_action_get(dev_id, index, ®_val); - *value = reg_val.bf.stag_fmt; - return ret; -} - -sw_error_t -hppe_ipo_action_stag_fmt_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - union ipo_action_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_ipo_action_get(dev_id, index, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.stag_fmt = value; - ret = hppe_ipo_action_set(dev_id, index, ®_val); - return ret; -} - diff --git a/feeds/ipq807x/qca-ssdk/src/src/hsl/hppe/hppe_bm.c b/feeds/ipq807x/qca-ssdk/src/src/hsl/hppe/hppe_bm.c deleted file mode 100755 index 989275f77..000000000 --- a/feeds/ipq807x/qca-ssdk/src/src/hsl/hppe/hppe_bm.c +++ /dev/null @@ -1,3027 +0,0 @@ -/* - * Copyright (c) 2016-2017, The Linux Foundation. All rights reserved. - * Permission to use, copy, modify, and/or distribute this software for - * any purpose with or without fee is hereby granted, provided that the - * above copyright notice and this permission notice appear in all copies. - * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES - * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR - * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES - * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN - * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT - * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. - */ - - -/** - * @defgroup - * @{ - */ -#include "sw.h" -#include "hsl.h" -#include "hppe_reg_access.h" -#include "hppe_bm_reg.h" -#include "hppe_bm.h" - -#ifndef IN_BM_MINI -sw_error_t -hppe_fb_fifo_cfg_get( - a_uint32_t dev_id, - union fb_fifo_cfg_u *value) -{ - return hppe_reg_get( - dev_id, - NSS_BM_CSR_BASE_ADDR + FB_FIFO_CFG_ADDRESS, - &value->val); -} - -sw_error_t -hppe_fb_fifo_cfg_set( - a_uint32_t dev_id, - union fb_fifo_cfg_u *value) -{ - return hppe_reg_set( - dev_id, - NSS_BM_CSR_BASE_ADDR + FB_FIFO_CFG_ADDRESS, - value->val); -} - -sw_error_t -hppe_fp_fifo_cfg_get( - a_uint32_t dev_id, - union fp_fifo_cfg_u *value) -{ - return hppe_reg_get( - dev_id, - NSS_BM_CSR_BASE_ADDR + FP_FIFO_CFG_ADDRESS, - &value->val); -} - -sw_error_t -hppe_fp_fifo_cfg_set( - a_uint32_t dev_id, - union fp_fifo_cfg_u *value) -{ - return hppe_reg_set( - dev_id, - NSS_BM_CSR_BASE_ADDR + FP_FIFO_CFG_ADDRESS, - value->val); -} - -sw_error_t -hppe_deq_fifo_cfg_get( - a_uint32_t dev_id, - a_uint32_t index, - union deq_fifo_cfg_u *value) -{ - if (index >= DEQ_FIFO_CFG_MAX_ENTRY) - return SW_OUT_OF_RANGE; - return hppe_reg_get( - dev_id, - NSS_BM_CSR_BASE_ADDR + DEQ_FIFO_CFG_ADDRESS + \ - index * DEQ_FIFO_CFG_INC, - &value->val); -} - -sw_error_t -hppe_deq_fifo_cfg_set( - a_uint32_t dev_id, - a_uint32_t index, - union deq_fifo_cfg_u *value) -{ - return hppe_reg_set( - dev_id, - NSS_BM_CSR_BASE_ADDR + DEQ_FIFO_CFG_ADDRESS + \ - index * DEQ_FIFO_CFG_INC, - value->val); -} - -sw_error_t -hppe_tick_dly_cfg_get( - a_uint32_t dev_id, - union tick_dly_cfg_u *value) -{ - return hppe_reg_get( - dev_id, - NSS_BM_CSR_BASE_ADDR + TICK_DLY_CFG_ADDRESS, - &value->val); -} - -sw_error_t -hppe_tick_dly_cfg_set( - a_uint32_t dev_id, - union tick_dly_cfg_u *value) -{ - return hppe_reg_set( - dev_id, - NSS_BM_CSR_BASE_ADDR + TICK_DLY_CFG_ADDRESS, - value->val); -} - -sw_error_t -hppe_bm_rsv_0_get( - a_uint32_t dev_id, - union bm_rsv_0_u *value) -{ - return hppe_reg_get( - dev_id, - NSS_BM_CSR_BASE_ADDR + BM_RSV_0_ADDRESS, - &value->val); -} - -sw_error_t -hppe_bm_rsv_0_set( - a_uint32_t dev_id, - union bm_rsv_0_u *value) -{ - return hppe_reg_set( - dev_id, - NSS_BM_CSR_BASE_ADDR + BM_RSV_0_ADDRESS, - value->val); -} - -sw_error_t -hppe_bm_rsv_1_get( - a_uint32_t dev_id, - union bm_rsv_1_u *value) -{ - return hppe_reg_get( - dev_id, - NSS_BM_CSR_BASE_ADDR + BM_RSV_1_ADDRESS, - &value->val); -} - -sw_error_t -hppe_bm_rsv_1_set( - a_uint32_t dev_id, - union bm_rsv_1_u *value) -{ - return hppe_reg_set( - dev_id, - NSS_BM_CSR_BASE_ADDR + BM_RSV_1_ADDRESS, - value->val); -} - -sw_error_t -hppe_bm_dbg_addr_get( - a_uint32_t dev_id, - union bm_dbg_addr_u *value) -{ - return hppe_reg_get( - dev_id, - NSS_BM_CSR_BASE_ADDR + BM_DBG_ADDR_ADDRESS, - &value->val); -} - -sw_error_t -hppe_bm_dbg_addr_set( - a_uint32_t dev_id, - union bm_dbg_addr_u *value) -{ - return hppe_reg_set( - dev_id, - NSS_BM_CSR_BASE_ADDR + BM_DBG_ADDR_ADDRESS, - value->val); -} - -sw_error_t -hppe_bm_dbg_data_get( - a_uint32_t dev_id, - union bm_dbg_data_u *value) -{ - return hppe_reg_get( - dev_id, - NSS_BM_CSR_BASE_ADDR + BM_DBG_DATA_ADDRESS, - &value->val); -} - -sw_error_t -hppe_bm_dbg_data_set( - a_uint32_t dev_id, - union bm_dbg_data_u *value) -{ - return SW_NOT_SUPPORTED; -} - -sw_error_t -hppe_port_fc_mode_get( - a_uint32_t dev_id, - a_uint32_t index, - union port_fc_mode_u *value) -{ - if (index >= PORT_FC_MODE_MAX_ENTRY) - return SW_OUT_OF_RANGE; - return hppe_reg_get( - dev_id, - NSS_BM_CSR_BASE_ADDR + PORT_FC_MODE_ADDRESS + \ - index * PORT_FC_MODE_INC, - &value->val); -} -#endif - -sw_error_t -hppe_port_fc_mode_set( - a_uint32_t dev_id, - a_uint32_t index, - union port_fc_mode_u *value) -{ - return hppe_reg_set( - dev_id, - NSS_BM_CSR_BASE_ADDR + PORT_FC_MODE_ADDRESS + \ - index * PORT_FC_MODE_INC, - value->val); -} - -#ifndef IN_BM_MINI -sw_error_t -hppe_port_fc_status_get( - a_uint32_t dev_id, - a_uint32_t index, - union port_fc_status_u *value) -{ - if (index >= PORT_FC_STATUS_MAX_ENTRY) - return SW_OUT_OF_RANGE; - return hppe_reg_get( - dev_id, - NSS_BM_CSR_BASE_ADDR + PORT_FC_STATUS_ADDRESS + \ - index * PORT_FC_STATUS_INC, - &value->val); -} - -sw_error_t -hppe_port_fc_status_set( - a_uint32_t dev_id, - a_uint32_t index, - union port_fc_status_u *value) -{ - return SW_NOT_SUPPORTED; -} - -sw_error_t -hppe_port_group_id_get( - a_uint32_t dev_id, - a_uint32_t index, - union port_group_id_u *value) -{ - if (index >= PORT_GROUP_ID_MAX_ENTRY) - return SW_OUT_OF_RANGE; - return hppe_reg_get( - dev_id, - NSS_BM_CSR_BASE_ADDR + PORT_GROUP_ID_ADDRESS + \ - index * PORT_GROUP_ID_INC, - &value->val); -} -#endif - -sw_error_t -hppe_port_group_id_set( - a_uint32_t dev_id, - a_uint32_t index, - union port_group_id_u *value) -{ - return hppe_reg_set( - dev_id, - NSS_BM_CSR_BASE_ADDR + PORT_GROUP_ID_ADDRESS + \ - index * PORT_GROUP_ID_INC, - value->val); -} - -#ifndef IN_BM_MINI -sw_error_t -hppe_port_cnt_get( - a_uint32_t dev_id, - a_uint32_t index, - union port_cnt_u *value) -{ - if (index >= PORT_CNT_MAX_ENTRY) - return SW_OUT_OF_RANGE; - return hppe_reg_get( - dev_id, - NSS_BM_CSR_BASE_ADDR + PORT_CNT_ADDRESS + \ - index * PORT_CNT_INC, - &value->val); -} - -sw_error_t -hppe_port_cnt_set( - a_uint32_t dev_id, - a_uint32_t index, - union port_cnt_u *value) -{ - return SW_NOT_SUPPORTED; -} - -sw_error_t -hppe_port_reacted_cnt_get( - a_uint32_t dev_id, - a_uint32_t index, - union port_reacted_cnt_u *value) -{ - if (index >= PORT_REACTED_CNT_MAX_ENTRY) - return SW_OUT_OF_RANGE; - return hppe_reg_get( - dev_id, - NSS_BM_CSR_BASE_ADDR + PORT_REACTED_CNT_ADDRESS + \ - index * PORT_REACTED_CNT_INC, - &value->val); -} - -sw_error_t -hppe_port_reacted_cnt_set( - a_uint32_t dev_id, - a_uint32_t index, - union port_reacted_cnt_u *value) -{ - return SW_NOT_SUPPORTED; -} - -sw_error_t -hppe_shared_group_cnt_get( - a_uint32_t dev_id, - a_uint32_t index, - union shared_group_cnt_u *value) -{ - if (index >= SHARED_GROUP_CNT_MAX_ENTRY) - return SW_OUT_OF_RANGE; - return hppe_reg_get( - dev_id, - NSS_BM_CSR_BASE_ADDR + SHARED_GROUP_CNT_ADDRESS + \ - index * SHARED_GROUP_CNT_INC, - &value->val); -} - -sw_error_t -hppe_shared_group_cnt_set( - a_uint32_t dev_id, - a_uint32_t index, - union shared_group_cnt_u *value) -{ - return SW_NOT_SUPPORTED; -} - -sw_error_t -hppe_shared_group_cfg_get( - a_uint32_t dev_id, - a_uint32_t index, - union shared_group_cfg_u *value) -{ - if (index >= SHARED_GROUP_CFG_MAX_ENTRY) - return SW_OUT_OF_RANGE; - return hppe_reg_get( - dev_id, - NSS_BM_CSR_BASE_ADDR + SHARED_GROUP_CFG_ADDRESS + \ - index * SHARED_GROUP_CFG_INC, - &value->val); -} -#endif - -sw_error_t -hppe_shared_group_cfg_set( - a_uint32_t dev_id, - a_uint32_t index, - union shared_group_cfg_u *value) -{ - return hppe_reg_set( - dev_id, - NSS_BM_CSR_BASE_ADDR + SHARED_GROUP_CFG_ADDRESS + \ - index * SHARED_GROUP_CFG_INC, - value->val); -} - -#ifndef IN_BM_MINI -sw_error_t -hppe_port_profile_cnt_en_get( - a_uint32_t dev_id, - union port_profile_cnt_en_u *value) -{ - return hppe_reg_get( - dev_id, - NSS_BM_CSR_BASE_ADDR + PORT_PROFILE_CNT_EN_ADDRESS, - &value->val); -} - -sw_error_t -hppe_port_profile_cnt_en_set( - a_uint32_t dev_id, - union port_profile_cnt_en_u *value) -{ - return hppe_reg_set( - dev_id, - NSS_BM_CSR_BASE_ADDR + PORT_PROFILE_CNT_EN_ADDRESS, - value->val); -} - -sw_error_t -hppe_grp_profile_cnt_en_get( - a_uint32_t dev_id, - union grp_profile_cnt_en_u *value) -{ - return hppe_reg_get( - dev_id, - NSS_BM_CSR_BASE_ADDR + GRP_PROFILE_CNT_EN_ADDRESS, - &value->val); -} - -sw_error_t -hppe_grp_profile_cnt_en_set( - a_uint32_t dev_id, - union grp_profile_cnt_en_u *value) -{ - return hppe_reg_set( - dev_id, - NSS_BM_CSR_BASE_ADDR + GRP_PROFILE_CNT_EN_ADDRESS, - value->val); -} - -sw_error_t -hppe_port_profile_th_cfg_get( - a_uint32_t dev_id, - a_uint32_t index, - union port_profile_th_cfg_u *value) -{ - if (index >= PORT_PROFILE_TH_CFG_MAX_ENTRY) - return SW_OUT_OF_RANGE; - return hppe_reg_get( - dev_id, - NSS_BM_CSR_BASE_ADDR + PORT_PROFILE_TH_CFG_ADDRESS + \ - index * PORT_PROFILE_TH_CFG_INC, - &value->val); -} - -sw_error_t -hppe_port_profile_th_cfg_set( - a_uint32_t dev_id, - a_uint32_t index, - union port_profile_th_cfg_u *value) -{ - return hppe_reg_set( - dev_id, - NSS_BM_CSR_BASE_ADDR + PORT_PROFILE_TH_CFG_ADDRESS + \ - index * PORT_PROFILE_TH_CFG_INC, - value->val); -} - -sw_error_t -hppe_react_profile_th_cfg_get( - a_uint32_t dev_id, - a_uint32_t index, - union react_profile_th_cfg_u *value) -{ - if (index >= REACT_PROFILE_TH_CFG_MAX_ENTRY) - return SW_OUT_OF_RANGE; - return hppe_reg_get( - dev_id, - NSS_BM_CSR_BASE_ADDR + REACT_PROFILE_TH_CFG_ADDRESS + \ - index * REACT_PROFILE_TH_CFG_INC, - &value->val); -} - -sw_error_t -hppe_react_profile_th_cfg_set( - a_uint32_t dev_id, - a_uint32_t index, - union react_profile_th_cfg_u *value) -{ - return hppe_reg_set( - dev_id, - NSS_BM_CSR_BASE_ADDR + REACT_PROFILE_TH_CFG_ADDRESS + \ - index * REACT_PROFILE_TH_CFG_INC, - value->val); -} - -sw_error_t -hppe_grp_profile_th_cfg_get( - a_uint32_t dev_id, - a_uint32_t index, - union grp_profile_th_cfg_u *value) -{ - if (index >= GRP_PROFILE_TH_CFG_MAX_ENTRY) - return SW_OUT_OF_RANGE; - return hppe_reg_get( - dev_id, - NSS_BM_CSR_BASE_ADDR + GRP_PROFILE_TH_CFG_ADDRESS + \ - index * GRP_PROFILE_TH_CFG_INC, - &value->val); -} - -sw_error_t -hppe_grp_profile_th_cfg_set( - a_uint32_t dev_id, - a_uint32_t index, - union grp_profile_th_cfg_u *value) -{ - return hppe_reg_set( - dev_id, - NSS_BM_CSR_BASE_ADDR + GRP_PROFILE_TH_CFG_ADDRESS + \ - index * GRP_PROFILE_TH_CFG_INC, - value->val); -} - -sw_error_t -hppe_tot_react_profile_th_cfg_get( - a_uint32_t dev_id, - union tot_react_profile_th_cfg_u *value) -{ - return hppe_reg_get( - dev_id, - NSS_BM_CSR_BASE_ADDR + TOT_REACT_PROFILE_TH_CFG_ADDRESS, - &value->val); -} - -sw_error_t -hppe_tot_react_profile_th_cfg_set( - a_uint32_t dev_id, - union tot_react_profile_th_cfg_u *value) -{ - return hppe_reg_set( - dev_id, - NSS_BM_CSR_BASE_ADDR + TOT_REACT_PROFILE_TH_CFG_ADDRESS, - value->val); -} - -sw_error_t -hppe_port_out_profile_cnt_get( - a_uint32_t dev_id, - a_uint32_t index, - union port_out_profile_cnt_u *value) -{ - if (index >= PORT_OUT_PROFILE_CNT_MAX_ENTRY) - return SW_OUT_OF_RANGE; - return hppe_reg_get( - dev_id, - NSS_BM_CSR_BASE_ADDR + PORT_OUT_PROFILE_CNT_ADDRESS + \ - index * PORT_OUT_PROFILE_CNT_INC, - &value->val); -} - -sw_error_t -hppe_port_out_profile_cnt_set( - a_uint32_t dev_id, - a_uint32_t index, - union port_out_profile_cnt_u *value) -{ - return hppe_reg_set( - dev_id, - NSS_BM_CSR_BASE_ADDR + PORT_OUT_PROFILE_CNT_ADDRESS + \ - index * PORT_OUT_PROFILE_CNT_INC, - value->val); -} - -sw_error_t -hppe_port_in_profile_cnt_get( - a_uint32_t dev_id, - a_uint32_t index, - union port_in_profile_cnt_u *value) -{ - if (index >= PORT_IN_PROFILE_CNT_MAX_ENTRY) - return SW_OUT_OF_RANGE; - return hppe_reg_get( - dev_id, - NSS_BM_CSR_BASE_ADDR + PORT_IN_PROFILE_CNT_ADDRESS + \ - index * PORT_IN_PROFILE_CNT_INC, - &value->val); -} - -sw_error_t -hppe_port_in_profile_cnt_set( - a_uint32_t dev_id, - a_uint32_t index, - union port_in_profile_cnt_u *value) -{ - return hppe_reg_set( - dev_id, - NSS_BM_CSR_BASE_ADDR + PORT_IN_PROFILE_CNT_ADDRESS + \ - index * PORT_IN_PROFILE_CNT_INC, - value->val); -} - -sw_error_t -hppe_react_out_profile_cnt_get( - a_uint32_t dev_id, - a_uint32_t index, - union react_out_profile_cnt_u *value) -{ - if (index >= REACT_OUT_PROFILE_CNT_MAX_ENTRY) - return SW_OUT_OF_RANGE; - return hppe_reg_get( - dev_id, - NSS_BM_CSR_BASE_ADDR + REACT_OUT_PROFILE_CNT_ADDRESS + \ - index * REACT_OUT_PROFILE_CNT_INC, - &value->val); -} - -sw_error_t -hppe_react_out_profile_cnt_set( - a_uint32_t dev_id, - a_uint32_t index, - union react_out_profile_cnt_u *value) -{ - return hppe_reg_set( - dev_id, - NSS_BM_CSR_BASE_ADDR + REACT_OUT_PROFILE_CNT_ADDRESS + \ - index * REACT_OUT_PROFILE_CNT_INC, - value->val); -} - -sw_error_t -hppe_react_in_profile_cnt_get( - a_uint32_t dev_id, - a_uint32_t index, - union react_in_profile_cnt_u *value) -{ - if (index >= REACT_IN_PROFILE_CNT_MAX_ENTRY) - return SW_OUT_OF_RANGE; - return hppe_reg_get( - dev_id, - NSS_BM_CSR_BASE_ADDR + REACT_IN_PROFILE_CNT_ADDRESS + \ - index * REACT_IN_PROFILE_CNT_INC, - &value->val); -} - -sw_error_t -hppe_react_in_profile_cnt_set( - a_uint32_t dev_id, - a_uint32_t index, - union react_in_profile_cnt_u *value) -{ - return hppe_reg_set( - dev_id, - NSS_BM_CSR_BASE_ADDR + REACT_IN_PROFILE_CNT_ADDRESS + \ - index * REACT_IN_PROFILE_CNT_INC, - value->val); -} - -sw_error_t -hppe_grp_out_profile_cnt_get( - a_uint32_t dev_id, - a_uint32_t index, - union grp_out_profile_cnt_u *value) -{ - if (index >= GRP_OUT_PROFILE_CNT_MAX_ENTRY) - return SW_OUT_OF_RANGE; - return hppe_reg_get( - dev_id, - NSS_BM_CSR_BASE_ADDR + GRP_OUT_PROFILE_CNT_ADDRESS + \ - index * GRP_OUT_PROFILE_CNT_INC, - &value->val); -} - -sw_error_t -hppe_grp_out_profile_cnt_set( - a_uint32_t dev_id, - a_uint32_t index, - union grp_out_profile_cnt_u *value) -{ - return hppe_reg_set( - dev_id, - NSS_BM_CSR_BASE_ADDR + GRP_OUT_PROFILE_CNT_ADDRESS + \ - index * GRP_OUT_PROFILE_CNT_INC, - value->val); -} - -sw_error_t -hppe_grp_in_profile_cnt_get( - a_uint32_t dev_id, - a_uint32_t index, - union grp_in_profile_cnt_u *value) -{ - if (index >= GRP_IN_PROFILE_CNT_MAX_ENTRY) - return SW_OUT_OF_RANGE; - return hppe_reg_get( - dev_id, - NSS_BM_CSR_BASE_ADDR + GRP_IN_PROFILE_CNT_ADDRESS + \ - index * GRP_IN_PROFILE_CNT_INC, - &value->val); -} - -sw_error_t -hppe_grp_in_profile_cnt_set( - a_uint32_t dev_id, - a_uint32_t index, - union grp_in_profile_cnt_u *value) -{ - return hppe_reg_set( - dev_id, - NSS_BM_CSR_BASE_ADDR + GRP_IN_PROFILE_CNT_ADDRESS + \ - index * GRP_IN_PROFILE_CNT_INC, - value->val); -} - -sw_error_t -hppe_tot_react_out_profile_cnt_get( - a_uint32_t dev_id, - union tot_react_out_profile_cnt_u *value) -{ - return hppe_reg_get( - dev_id, - NSS_BM_CSR_BASE_ADDR + TOT_REACT_OUT_PROFILE_CNT_ADDRESS, - &value->val); -} - -sw_error_t -hppe_tot_react_out_profile_cnt_set( - a_uint32_t dev_id, - union tot_react_out_profile_cnt_u *value) -{ - return hppe_reg_set( - dev_id, - NSS_BM_CSR_BASE_ADDR + TOT_REACT_OUT_PROFILE_CNT_ADDRESS, - value->val); -} - -sw_error_t -hppe_tot_react_in_profile_cnt_get( - a_uint32_t dev_id, - union tot_react_in_profile_cnt_u *value) -{ - return hppe_reg_get( - dev_id, - NSS_BM_CSR_BASE_ADDR + TOT_REACT_IN_PROFILE_CNT_ADDRESS, - &value->val); -} - -sw_error_t -hppe_tot_react_in_profile_cnt_set( - a_uint32_t dev_id, - union tot_react_in_profile_cnt_u *value) -{ - return hppe_reg_set( - dev_id, - NSS_BM_CSR_BASE_ADDR + TOT_REACT_IN_PROFILE_CNT_ADDRESS, - value->val); -} -#endif - -sw_error_t -hppe_port_fc_cfg_get( - a_uint32_t dev_id, - a_uint32_t index, - union port_fc_cfg_u *value) -{ - return hppe_reg_tbl_get( - dev_id, - NSS_BM_CSR_BASE_ADDR + PORT_FC_CFG_ADDRESS + \ - index * PORT_FC_CFG_INC, - value->val, - 2); -} - -sw_error_t -hppe_port_fc_cfg_set( - a_uint32_t dev_id, - a_uint32_t index, - union port_fc_cfg_u *value) -{ - return hppe_reg_tbl_set( - dev_id, - NSS_BM_CSR_BASE_ADDR + PORT_FC_CFG_ADDRESS + \ - index * PORT_FC_CFG_INC, - value->val, - 2); -} - -#ifndef IN_BM_MINI -sw_error_t -hppe_llm_get( - a_uint32_t dev_id, - a_uint32_t index, - union llm_u *value) -{ - if (index >= LLM_MAX_ENTRY) - return SW_OUT_OF_RANGE; - return hppe_reg_get( - dev_id, - NSS_BM_CSR_BASE_ADDR + LLM_ADDRESS + \ - index * LLM_INC, - &value->val); -} - -sw_error_t -hppe_llm_set( - a_uint32_t dev_id, - a_uint32_t index, - union llm_u *value) -{ - return hppe_reg_set( - dev_id, - NSS_BM_CSR_BASE_ADDR + LLM_ADDRESS + \ - index * LLM_INC, - value->val); -} - -sw_error_t -hppe_rcm_get( - a_uint32_t dev_id, - a_uint32_t index, - union rcm_u *value) -{ - if (index >= RCM_MAX_ENTRY) - return SW_OUT_OF_RANGE; - return hppe_reg_get( - dev_id, - NSS_BM_CSR_BASE_ADDR + RCM_ADDRESS + \ - index * RCM_INC, - &value->val); -} - -sw_error_t -hppe_rcm_set( - a_uint32_t dev_id, - a_uint32_t index, - union rcm_u *value) -{ - return hppe_reg_set( - dev_id, - NSS_BM_CSR_BASE_ADDR + RCM_ADDRESS + \ - index * RCM_INC, - value->val); -} - -sw_error_t -hppe_dm_get( - a_uint32_t dev_id, - a_uint32_t index, - union dm_u *value) -{ - return hppe_reg_tbl_get( - dev_id, - NSS_BM_CSR_BASE_ADDR + DM_ADDRESS + \ - index * DM_INC, - value->val, - 16); -} - -sw_error_t -hppe_dm_set( - a_uint32_t dev_id, - a_uint32_t index, - union dm_u *value) -{ - return hppe_reg_tbl_set( - dev_id, - NSS_BM_CSR_BASE_ADDR + DM_ADDRESS + \ - index * DM_INC, - value->val, - 16); -} - -sw_error_t -hppe_fb_fifo_cfg_fb_fifo_thres_get( - a_uint32_t dev_id, - a_uint32_t *value) -{ - union fb_fifo_cfg_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_fb_fifo_cfg_get(dev_id, ®_val); - *value = reg_val.bf.fb_fifo_thres; - return ret; -} - -sw_error_t -hppe_fb_fifo_cfg_fb_fifo_thres_set( - a_uint32_t dev_id, - a_uint32_t value) -{ - union fb_fifo_cfg_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_fb_fifo_cfg_get(dev_id, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.fb_fifo_thres = value; - ret = hppe_fb_fifo_cfg_set(dev_id, ®_val); - return ret; -} - -sw_error_t -hppe_fp_fifo_cfg_fp_fifo_thres_get( - a_uint32_t dev_id, - a_uint32_t *value) -{ - union fp_fifo_cfg_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_fp_fifo_cfg_get(dev_id, ®_val); - *value = reg_val.bf.fp_fifo_thres; - return ret; -} - -sw_error_t -hppe_fp_fifo_cfg_fp_fifo_thres_set( - a_uint32_t dev_id, - a_uint32_t value) -{ - union fp_fifo_cfg_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_fp_fifo_cfg_get(dev_id, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.fp_fifo_thres = value; - ret = hppe_fp_fifo_cfg_set(dev_id, ®_val); - return ret; -} - -sw_error_t -hppe_deq_fifo_cfg_deq_fifo_thres_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union deq_fifo_cfg_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_deq_fifo_cfg_get(dev_id, index, ®_val); - *value = reg_val.bf.deq_fifo_thres; - return ret; -} - -sw_error_t -hppe_deq_fifo_cfg_deq_fifo_thres_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - union deq_fifo_cfg_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_deq_fifo_cfg_get(dev_id, index, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.deq_fifo_thres = value; - ret = hppe_deq_fifo_cfg_set(dev_id, index, ®_val); - return ret; -} - -sw_error_t -hppe_tick_dly_cfg_tick_dly_get( - a_uint32_t dev_id, - a_uint32_t *value) -{ - union tick_dly_cfg_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_tick_dly_cfg_get(dev_id, ®_val); - *value = reg_val.bf.tick_dly; - return ret; -} - -sw_error_t -hppe_tick_dly_cfg_tick_dly_set( - a_uint32_t dev_id, - a_uint32_t value) -{ - union tick_dly_cfg_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_tick_dly_cfg_get(dev_id, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.tick_dly = value; - ret = hppe_tick_dly_cfg_set(dev_id, ®_val); - return ret; -} - -sw_error_t -hppe_bm_rsv_0_rsv_0_get( - a_uint32_t dev_id, - a_uint32_t *value) -{ - union bm_rsv_0_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_bm_rsv_0_get(dev_id, ®_val); - *value = reg_val.bf.rsv_0; - return ret; -} - -sw_error_t -hppe_bm_rsv_0_rsv_0_set( - a_uint32_t dev_id, - a_uint32_t value) -{ - union bm_rsv_0_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_bm_rsv_0_get(dev_id, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.rsv_0 = value; - ret = hppe_bm_rsv_0_set(dev_id, ®_val); - return ret; -} - -sw_error_t -hppe_bm_rsv_1_rsv_1_get( - a_uint32_t dev_id, - a_uint32_t *value) -{ - union bm_rsv_1_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_bm_rsv_1_get(dev_id, ®_val); - *value = reg_val.bf.rsv_1; - return ret; -} - -sw_error_t -hppe_bm_rsv_1_rsv_1_set( - a_uint32_t dev_id, - a_uint32_t value) -{ - union bm_rsv_1_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_bm_rsv_1_get(dev_id, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.rsv_1 = value; - ret = hppe_bm_rsv_1_set(dev_id, ®_val); - return ret; -} - -sw_error_t -hppe_bm_dbg_addr_dbg_addr_get( - a_uint32_t dev_id, - a_uint32_t *value) -{ - union bm_dbg_addr_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_bm_dbg_addr_get(dev_id, ®_val); - *value = reg_val.bf.dbg_addr; - return ret; -} - -sw_error_t -hppe_bm_dbg_addr_dbg_addr_set( - a_uint32_t dev_id, - a_uint32_t value) -{ - union bm_dbg_addr_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_bm_dbg_addr_get(dev_id, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.dbg_addr = value; - ret = hppe_bm_dbg_addr_set(dev_id, ®_val); - return ret; -} - -sw_error_t -hppe_bm_dbg_data_dbg_data_get( - a_uint32_t dev_id, - a_uint32_t *value) -{ - union bm_dbg_data_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_bm_dbg_data_get(dev_id, ®_val); - *value = reg_val.bf.dbg_data; - return ret; -} - -sw_error_t -hppe_bm_dbg_data_dbg_data_set( - a_uint32_t dev_id, - a_uint32_t value) -{ - return SW_NOT_SUPPORTED; -} - -sw_error_t -hppe_port_fc_mode_fc_en_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union port_fc_mode_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_port_fc_mode_get(dev_id, index, ®_val); - *value = reg_val.bf.fc_en; - return ret; -} - -sw_error_t -hppe_port_fc_mode_fc_en_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - union port_fc_mode_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_port_fc_mode_get(dev_id, index, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.fc_en = value; - ret = hppe_port_fc_mode_set(dev_id, index, ®_val); - return ret; -} - -sw_error_t -hppe_port_fc_status_port_fc_status_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union port_fc_status_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_port_fc_status_get(dev_id, index, ®_val); - *value = reg_val.bf.port_fc_status; - return ret; -} - -sw_error_t -hppe_port_fc_status_port_fc_status_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - return SW_NOT_SUPPORTED; -} - -sw_error_t -hppe_port_fc_status_port_xon_th_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union port_fc_status_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_port_fc_status_get(dev_id, index, ®_val); - *value = reg_val.bf.port_xon_th; - return ret; -} - -sw_error_t -hppe_port_fc_status_port_xon_th_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - return SW_NOT_SUPPORTED; -} - -sw_error_t -hppe_port_group_id_port_shared_group_id_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union port_group_id_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_port_group_id_get(dev_id, index, ®_val); - *value = reg_val.bf.port_shared_group_id; - return ret; -} - -sw_error_t -hppe_port_group_id_port_shared_group_id_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - union port_group_id_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_port_group_id_get(dev_id, index, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.port_shared_group_id = value; - ret = hppe_port_group_id_set(dev_id, index, ®_val); - return ret; -} - -sw_error_t -hppe_port_cnt_port_cnt_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union port_cnt_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_port_cnt_get(dev_id, index, ®_val); - *value = reg_val.bf.port_cnt; - return ret; -} - -sw_error_t -hppe_port_cnt_port_cnt_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - return SW_NOT_SUPPORTED; -} - -sw_error_t -hppe_port_reacted_cnt_port_reacted_cnt_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union port_reacted_cnt_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_port_reacted_cnt_get(dev_id, index, ®_val); - *value = reg_val.bf.port_reacted_cnt; - return ret; -} - -sw_error_t -hppe_port_reacted_cnt_port_reacted_cnt_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - return SW_NOT_SUPPORTED; -} - -sw_error_t -hppe_shared_group_cnt_shared_group_cnt_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union shared_group_cnt_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_shared_group_cnt_get(dev_id, index, ®_val); - *value = reg_val.bf.shared_group_cnt; - return ret; -} - -sw_error_t -hppe_shared_group_cnt_shared_group_cnt_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - return SW_NOT_SUPPORTED; -} - -sw_error_t -hppe_shared_group_cfg_shared_group_limit_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union shared_group_cfg_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_shared_group_cfg_get(dev_id, index, ®_val); - *value = reg_val.bf.shared_group_limit; - return ret; -} - -sw_error_t -hppe_shared_group_cfg_shared_group_limit_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - union shared_group_cfg_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_shared_group_cfg_get(dev_id, index, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.shared_group_limit = value; - ret = hppe_shared_group_cfg_set(dev_id, index, ®_val); - return ret; -} - -sw_error_t -hppe_port_profile_cnt_en_react_cnt_en_8_get( - a_uint32_t dev_id, - a_uint32_t *value) -{ - union port_profile_cnt_en_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_port_profile_cnt_en_get(dev_id, ®_val); - *value = reg_val.bf.react_cnt_en_8; - return ret; -} - -sw_error_t -hppe_port_profile_cnt_en_react_cnt_en_8_set( - a_uint32_t dev_id, - a_uint32_t value) -{ - union port_profile_cnt_en_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_port_profile_cnt_en_get(dev_id, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.react_cnt_en_8 = value; - ret = hppe_port_profile_cnt_en_set(dev_id, ®_val); - return ret; -} - -sw_error_t -hppe_port_profile_cnt_en_react_cnt_en_7_get( - a_uint32_t dev_id, - a_uint32_t *value) -{ - union port_profile_cnt_en_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_port_profile_cnt_en_get(dev_id, ®_val); - *value = reg_val.bf.react_cnt_en_7; - return ret; -} - -sw_error_t -hppe_port_profile_cnt_en_react_cnt_en_7_set( - a_uint32_t dev_id, - a_uint32_t value) -{ - union port_profile_cnt_en_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_port_profile_cnt_en_get(dev_id, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.react_cnt_en_7 = value; - ret = hppe_port_profile_cnt_en_set(dev_id, ®_val); - return ret; -} - -sw_error_t -hppe_port_profile_cnt_en_port_cnt_en_6_get( - a_uint32_t dev_id, - a_uint32_t *value) -{ - union port_profile_cnt_en_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_port_profile_cnt_en_get(dev_id, ®_val); - *value = reg_val.bf.port_cnt_en_6; - return ret; -} - -sw_error_t -hppe_port_profile_cnt_en_port_cnt_en_6_set( - a_uint32_t dev_id, - a_uint32_t value) -{ - union port_profile_cnt_en_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_port_profile_cnt_en_get(dev_id, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.port_cnt_en_6 = value; - ret = hppe_port_profile_cnt_en_set(dev_id, ®_val); - return ret; -} - -sw_error_t -hppe_port_profile_cnt_en_react_cnt_en_2_get( - a_uint32_t dev_id, - a_uint32_t *value) -{ - union port_profile_cnt_en_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_port_profile_cnt_en_get(dev_id, ®_val); - *value = reg_val.bf.react_cnt_en_2; - return ret; -} - -sw_error_t -hppe_port_profile_cnt_en_react_cnt_en_2_set( - a_uint32_t dev_id, - a_uint32_t value) -{ - union port_profile_cnt_en_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_port_profile_cnt_en_get(dev_id, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.react_cnt_en_2 = value; - ret = hppe_port_profile_cnt_en_set(dev_id, ®_val); - return ret; -} - -sw_error_t -hppe_port_profile_cnt_en_port_cnt_en_8_get( - a_uint32_t dev_id, - a_uint32_t *value) -{ - union port_profile_cnt_en_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_port_profile_cnt_en_get(dev_id, ®_val); - *value = reg_val.bf.port_cnt_en_8; - return ret; -} - -sw_error_t -hppe_port_profile_cnt_en_port_cnt_en_8_set( - a_uint32_t dev_id, - a_uint32_t value) -{ - union port_profile_cnt_en_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_port_profile_cnt_en_get(dev_id, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.port_cnt_en_8 = value; - ret = hppe_port_profile_cnt_en_set(dev_id, ®_val); - return ret; -} - -sw_error_t -hppe_port_profile_cnt_en_port_cnt_en_5_get( - a_uint32_t dev_id, - a_uint32_t *value) -{ - union port_profile_cnt_en_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_port_profile_cnt_en_get(dev_id, ®_val); - *value = reg_val.bf.port_cnt_en_5; - return ret; -} - -sw_error_t -hppe_port_profile_cnt_en_port_cnt_en_5_set( - a_uint32_t dev_id, - a_uint32_t value) -{ - union port_profile_cnt_en_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_port_profile_cnt_en_get(dev_id, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.port_cnt_en_5 = value; - ret = hppe_port_profile_cnt_en_set(dev_id, ®_val); - return ret; -} - -sw_error_t -hppe_port_profile_cnt_en_port_cnt_en_12_get( - a_uint32_t dev_id, - a_uint32_t *value) -{ - union port_profile_cnt_en_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_port_profile_cnt_en_get(dev_id, ®_val); - *value = reg_val.bf.port_cnt_en_12; - return ret; -} - -sw_error_t -hppe_port_profile_cnt_en_port_cnt_en_12_set( - a_uint32_t dev_id, - a_uint32_t value) -{ - union port_profile_cnt_en_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_port_profile_cnt_en_get(dev_id, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.port_cnt_en_12 = value; - ret = hppe_port_profile_cnt_en_set(dev_id, ®_val); - return ret; -} - -sw_error_t -hppe_port_profile_cnt_en_react_cnt_en_4_get( - a_uint32_t dev_id, - a_uint32_t *value) -{ - union port_profile_cnt_en_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_port_profile_cnt_en_get(dev_id, ®_val); - *value = reg_val.bf.react_cnt_en_4; - return ret; -} - -sw_error_t -hppe_port_profile_cnt_en_react_cnt_en_4_set( - a_uint32_t dev_id, - a_uint32_t value) -{ - union port_profile_cnt_en_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_port_profile_cnt_en_get(dev_id, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.react_cnt_en_4 = value; - ret = hppe_port_profile_cnt_en_set(dev_id, ®_val); - return ret; -} - -sw_error_t -hppe_port_profile_cnt_en_port_cnt_en_3_get( - a_uint32_t dev_id, - a_uint32_t *value) -{ - union port_profile_cnt_en_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_port_profile_cnt_en_get(dev_id, ®_val); - *value = reg_val.bf.port_cnt_en_3; - return ret; -} - -sw_error_t -hppe_port_profile_cnt_en_port_cnt_en_3_set( - a_uint32_t dev_id, - a_uint32_t value) -{ - union port_profile_cnt_en_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_port_profile_cnt_en_get(dev_id, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.port_cnt_en_3 = value; - ret = hppe_port_profile_cnt_en_set(dev_id, ®_val); - return ret; -} - -sw_error_t -hppe_port_profile_cnt_en_port_cnt_en_10_get( - a_uint32_t dev_id, - a_uint32_t *value) -{ - union port_profile_cnt_en_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_port_profile_cnt_en_get(dev_id, ®_val); - *value = reg_val.bf.port_cnt_en_10; - return ret; -} - -sw_error_t -hppe_port_profile_cnt_en_port_cnt_en_10_set( - a_uint32_t dev_id, - a_uint32_t value) -{ - union port_profile_cnt_en_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_port_profile_cnt_en_get(dev_id, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.port_cnt_en_10 = value; - ret = hppe_port_profile_cnt_en_set(dev_id, ®_val); - return ret; -} - -sw_error_t -hppe_port_profile_cnt_en_port_cnt_en_4_get( - a_uint32_t dev_id, - a_uint32_t *value) -{ - union port_profile_cnt_en_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_port_profile_cnt_en_get(dev_id, ®_val); - *value = reg_val.bf.port_cnt_en_4; - return ret; -} - -sw_error_t -hppe_port_profile_cnt_en_port_cnt_en_4_set( - a_uint32_t dev_id, - a_uint32_t value) -{ - union port_profile_cnt_en_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_port_profile_cnt_en_get(dev_id, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.port_cnt_en_4 = value; - ret = hppe_port_profile_cnt_en_set(dev_id, ®_val); - return ret; -} - -sw_error_t -hppe_port_profile_cnt_en_react_cnt_en_5_get( - a_uint32_t dev_id, - a_uint32_t *value) -{ - union port_profile_cnt_en_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_port_profile_cnt_en_get(dev_id, ®_val); - *value = reg_val.bf.react_cnt_en_5; - return ret; -} - -sw_error_t -hppe_port_profile_cnt_en_react_cnt_en_5_set( - a_uint32_t dev_id, - a_uint32_t value) -{ - union port_profile_cnt_en_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_port_profile_cnt_en_get(dev_id, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.react_cnt_en_5 = value; - ret = hppe_port_profile_cnt_en_set(dev_id, ®_val); - return ret; -} - -sw_error_t -hppe_port_profile_cnt_en_port_cnt_en_14_get( - a_uint32_t dev_id, - a_uint32_t *value) -{ - union port_profile_cnt_en_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_port_profile_cnt_en_get(dev_id, ®_val); - *value = reg_val.bf.port_cnt_en_14; - return ret; -} - -sw_error_t -hppe_port_profile_cnt_en_port_cnt_en_14_set( - a_uint32_t dev_id, - a_uint32_t value) -{ - union port_profile_cnt_en_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_port_profile_cnt_en_get(dev_id, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.port_cnt_en_14 = value; - ret = hppe_port_profile_cnt_en_set(dev_id, ®_val); - return ret; -} - -sw_error_t -hppe_port_profile_cnt_en_react_cnt_en_14_get( - a_uint32_t dev_id, - a_uint32_t *value) -{ - union port_profile_cnt_en_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_port_profile_cnt_en_get(dev_id, ®_val); - *value = reg_val.bf.react_cnt_en_14; - return ret; -} - -sw_error_t -hppe_port_profile_cnt_en_react_cnt_en_14_set( - a_uint32_t dev_id, - a_uint32_t value) -{ - union port_profile_cnt_en_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_port_profile_cnt_en_get(dev_id, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.react_cnt_en_14 = value; - ret = hppe_port_profile_cnt_en_set(dev_id, ®_val); - return ret; -} - -sw_error_t -hppe_port_profile_cnt_en_react_cnt_en_3_get( - a_uint32_t dev_id, - a_uint32_t *value) -{ - union port_profile_cnt_en_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_port_profile_cnt_en_get(dev_id, ®_val); - *value = reg_val.bf.react_cnt_en_3; - return ret; -} - -sw_error_t -hppe_port_profile_cnt_en_react_cnt_en_3_set( - a_uint32_t dev_id, - a_uint32_t value) -{ - union port_profile_cnt_en_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_port_profile_cnt_en_get(dev_id, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.react_cnt_en_3 = value; - ret = hppe_port_profile_cnt_en_set(dev_id, ®_val); - return ret; -} - -sw_error_t -hppe_port_profile_cnt_en_port_cnt_en_1_get( - a_uint32_t dev_id, - a_uint32_t *value) -{ - union port_profile_cnt_en_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_port_profile_cnt_en_get(dev_id, ®_val); - *value = reg_val.bf.port_cnt_en_1; - return ret; -} - -sw_error_t -hppe_port_profile_cnt_en_port_cnt_en_1_set( - a_uint32_t dev_id, - a_uint32_t value) -{ - union port_profile_cnt_en_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_port_profile_cnt_en_get(dev_id, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.port_cnt_en_1 = value; - ret = hppe_port_profile_cnt_en_set(dev_id, ®_val); - return ret; -} - -sw_error_t -hppe_port_profile_cnt_en_port_cnt_en_0_get( - a_uint32_t dev_id, - a_uint32_t *value) -{ - union port_profile_cnt_en_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_port_profile_cnt_en_get(dev_id, ®_val); - *value = reg_val.bf.port_cnt_en_0; - return ret; -} - -sw_error_t -hppe_port_profile_cnt_en_port_cnt_en_0_set( - a_uint32_t dev_id, - a_uint32_t value) -{ - union port_profile_cnt_en_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_port_profile_cnt_en_get(dev_id, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.port_cnt_en_0 = value; - ret = hppe_port_profile_cnt_en_set(dev_id, ®_val); - return ret; -} - -sw_error_t -hppe_port_profile_cnt_en_port_cnt_en_7_get( - a_uint32_t dev_id, - a_uint32_t *value) -{ - union port_profile_cnt_en_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_port_profile_cnt_en_get(dev_id, ®_val); - *value = reg_val.bf.port_cnt_en_7; - return ret; -} - -sw_error_t -hppe_port_profile_cnt_en_port_cnt_en_7_set( - a_uint32_t dev_id, - a_uint32_t value) -{ - union port_profile_cnt_en_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_port_profile_cnt_en_get(dev_id, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.port_cnt_en_7 = value; - ret = hppe_port_profile_cnt_en_set(dev_id, ®_val); - return ret; -} - -sw_error_t -hppe_port_profile_cnt_en_port_cnt_en_13_get( - a_uint32_t dev_id, - a_uint32_t *value) -{ - union port_profile_cnt_en_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_port_profile_cnt_en_get(dev_id, ®_val); - *value = reg_val.bf.port_cnt_en_13; - return ret; -} - -sw_error_t -hppe_port_profile_cnt_en_port_cnt_en_13_set( - a_uint32_t dev_id, - a_uint32_t value) -{ - union port_profile_cnt_en_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_port_profile_cnt_en_get(dev_id, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.port_cnt_en_13 = value; - ret = hppe_port_profile_cnt_en_set(dev_id, ®_val); - return ret; -} - -sw_error_t -hppe_port_profile_cnt_en_react_cnt_en_6_get( - a_uint32_t dev_id, - a_uint32_t *value) -{ - union port_profile_cnt_en_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_port_profile_cnt_en_get(dev_id, ®_val); - *value = reg_val.bf.react_cnt_en_6; - return ret; -} - -sw_error_t -hppe_port_profile_cnt_en_react_cnt_en_6_set( - a_uint32_t dev_id, - a_uint32_t value) -{ - union port_profile_cnt_en_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_port_profile_cnt_en_get(dev_id, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.react_cnt_en_6 = value; - ret = hppe_port_profile_cnt_en_set(dev_id, ®_val); - return ret; -} - -sw_error_t -hppe_port_profile_cnt_en_react_cnt_en_0_get( - a_uint32_t dev_id, - a_uint32_t *value) -{ - union port_profile_cnt_en_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_port_profile_cnt_en_get(dev_id, ®_val); - *value = reg_val.bf.react_cnt_en_0; - return ret; -} - -sw_error_t -hppe_port_profile_cnt_en_react_cnt_en_0_set( - a_uint32_t dev_id, - a_uint32_t value) -{ - union port_profile_cnt_en_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_port_profile_cnt_en_get(dev_id, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.react_cnt_en_0 = value; - ret = hppe_port_profile_cnt_en_set(dev_id, ®_val); - return ret; -} - -sw_error_t -hppe_port_profile_cnt_en_react_cnt_en_13_get( - a_uint32_t dev_id, - a_uint32_t *value) -{ - union port_profile_cnt_en_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_port_profile_cnt_en_get(dev_id, ®_val); - *value = reg_val.bf.react_cnt_en_13; - return ret; -} - -sw_error_t -hppe_port_profile_cnt_en_react_cnt_en_13_set( - a_uint32_t dev_id, - a_uint32_t value) -{ - union port_profile_cnt_en_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_port_profile_cnt_en_get(dev_id, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.react_cnt_en_13 = value; - ret = hppe_port_profile_cnt_en_set(dev_id, ®_val); - return ret; -} - -sw_error_t -hppe_port_profile_cnt_en_port_cnt_en_11_get( - a_uint32_t dev_id, - a_uint32_t *value) -{ - union port_profile_cnt_en_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_port_profile_cnt_en_get(dev_id, ®_val); - *value = reg_val.bf.port_cnt_en_11; - return ret; -} - -sw_error_t -hppe_port_profile_cnt_en_port_cnt_en_11_set( - a_uint32_t dev_id, - a_uint32_t value) -{ - union port_profile_cnt_en_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_port_profile_cnt_en_get(dev_id, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.port_cnt_en_11 = value; - ret = hppe_port_profile_cnt_en_set(dev_id, ®_val); - return ret; -} - -sw_error_t -hppe_port_profile_cnt_en_react_cnt_en_1_get( - a_uint32_t dev_id, - a_uint32_t *value) -{ - union port_profile_cnt_en_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_port_profile_cnt_en_get(dev_id, ®_val); - *value = reg_val.bf.react_cnt_en_1; - return ret; -} - -sw_error_t -hppe_port_profile_cnt_en_react_cnt_en_1_set( - a_uint32_t dev_id, - a_uint32_t value) -{ - union port_profile_cnt_en_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_port_profile_cnt_en_get(dev_id, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.react_cnt_en_1 = value; - ret = hppe_port_profile_cnt_en_set(dev_id, ®_val); - return ret; -} - -sw_error_t -hppe_port_profile_cnt_en_react_cnt_en_12_get( - a_uint32_t dev_id, - a_uint32_t *value) -{ - union port_profile_cnt_en_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_port_profile_cnt_en_get(dev_id, ®_val); - *value = reg_val.bf.react_cnt_en_12; - return ret; -} - -sw_error_t -hppe_port_profile_cnt_en_react_cnt_en_12_set( - a_uint32_t dev_id, - a_uint32_t value) -{ - union port_profile_cnt_en_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_port_profile_cnt_en_get(dev_id, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.react_cnt_en_12 = value; - ret = hppe_port_profile_cnt_en_set(dev_id, ®_val); - return ret; -} - -sw_error_t -hppe_port_profile_cnt_en_react_cnt_en_11_get( - a_uint32_t dev_id, - a_uint32_t *value) -{ - union port_profile_cnt_en_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_port_profile_cnt_en_get(dev_id, ®_val); - *value = reg_val.bf.react_cnt_en_11; - return ret; -} - -sw_error_t -hppe_port_profile_cnt_en_react_cnt_en_11_set( - a_uint32_t dev_id, - a_uint32_t value) -{ - union port_profile_cnt_en_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_port_profile_cnt_en_get(dev_id, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.react_cnt_en_11 = value; - ret = hppe_port_profile_cnt_en_set(dev_id, ®_val); - return ret; -} - -sw_error_t -hppe_port_profile_cnt_en_react_cnt_en_10_get( - a_uint32_t dev_id, - a_uint32_t *value) -{ - union port_profile_cnt_en_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_port_profile_cnt_en_get(dev_id, ®_val); - *value = reg_val.bf.react_cnt_en_10; - return ret; -} - -sw_error_t -hppe_port_profile_cnt_en_react_cnt_en_10_set( - a_uint32_t dev_id, - a_uint32_t value) -{ - union port_profile_cnt_en_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_port_profile_cnt_en_get(dev_id, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.react_cnt_en_10 = value; - ret = hppe_port_profile_cnt_en_set(dev_id, ®_val); - return ret; -} - -sw_error_t -hppe_port_profile_cnt_en_port_cnt_en_9_get( - a_uint32_t dev_id, - a_uint32_t *value) -{ - union port_profile_cnt_en_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_port_profile_cnt_en_get(dev_id, ®_val); - *value = reg_val.bf.port_cnt_en_9; - return ret; -} - -sw_error_t -hppe_port_profile_cnt_en_port_cnt_en_9_set( - a_uint32_t dev_id, - a_uint32_t value) -{ - union port_profile_cnt_en_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_port_profile_cnt_en_get(dev_id, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.port_cnt_en_9 = value; - ret = hppe_port_profile_cnt_en_set(dev_id, ®_val); - return ret; -} - -sw_error_t -hppe_port_profile_cnt_en_port_cnt_en_2_get( - a_uint32_t dev_id, - a_uint32_t *value) -{ - union port_profile_cnt_en_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_port_profile_cnt_en_get(dev_id, ®_val); - *value = reg_val.bf.port_cnt_en_2; - return ret; -} - -sw_error_t -hppe_port_profile_cnt_en_port_cnt_en_2_set( - a_uint32_t dev_id, - a_uint32_t value) -{ - union port_profile_cnt_en_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_port_profile_cnt_en_get(dev_id, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.port_cnt_en_2 = value; - ret = hppe_port_profile_cnt_en_set(dev_id, ®_val); - return ret; -} - -sw_error_t -hppe_port_profile_cnt_en_react_cnt_en_9_get( - a_uint32_t dev_id, - a_uint32_t *value) -{ - union port_profile_cnt_en_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_port_profile_cnt_en_get(dev_id, ®_val); - *value = reg_val.bf.react_cnt_en_9; - return ret; -} - -sw_error_t -hppe_port_profile_cnt_en_react_cnt_en_9_set( - a_uint32_t dev_id, - a_uint32_t value) -{ - union port_profile_cnt_en_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_port_profile_cnt_en_get(dev_id, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.react_cnt_en_9 = value; - ret = hppe_port_profile_cnt_en_set(dev_id, ®_val); - return ret; -} - -sw_error_t -hppe_grp_profile_cnt_en_grp_cnt_en_3_get( - a_uint32_t dev_id, - a_uint32_t *value) -{ - union grp_profile_cnt_en_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_grp_profile_cnt_en_get(dev_id, ®_val); - *value = reg_val.bf.grp_cnt_en_3; - return ret; -} - -sw_error_t -hppe_grp_profile_cnt_en_grp_cnt_en_3_set( - a_uint32_t dev_id, - a_uint32_t value) -{ - union grp_profile_cnt_en_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_grp_profile_cnt_en_get(dev_id, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.grp_cnt_en_3 = value; - ret = hppe_grp_profile_cnt_en_set(dev_id, ®_val); - return ret; -} - -sw_error_t -hppe_grp_profile_cnt_en_tot_rect_cnt_en_get( - a_uint32_t dev_id, - a_uint32_t *value) -{ - union grp_profile_cnt_en_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_grp_profile_cnt_en_get(dev_id, ®_val); - *value = reg_val.bf.tot_rect_cnt_en; - return ret; -} - -sw_error_t -hppe_grp_profile_cnt_en_tot_rect_cnt_en_set( - a_uint32_t dev_id, - a_uint32_t value) -{ - union grp_profile_cnt_en_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_grp_profile_cnt_en_get(dev_id, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.tot_rect_cnt_en = value; - ret = hppe_grp_profile_cnt_en_set(dev_id, ®_val); - return ret; -} - -sw_error_t -hppe_grp_profile_cnt_en_grp_cnt_en_1_get( - a_uint32_t dev_id, - a_uint32_t *value) -{ - union grp_profile_cnt_en_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_grp_profile_cnt_en_get(dev_id, ®_val); - *value = reg_val.bf.grp_cnt_en_1; - return ret; -} - -sw_error_t -hppe_grp_profile_cnt_en_grp_cnt_en_1_set( - a_uint32_t dev_id, - a_uint32_t value) -{ - union grp_profile_cnt_en_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_grp_profile_cnt_en_get(dev_id, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.grp_cnt_en_1 = value; - ret = hppe_grp_profile_cnt_en_set(dev_id, ®_val); - return ret; -} - -sw_error_t -hppe_grp_profile_cnt_en_grp_cnt_en_0_get( - a_uint32_t dev_id, - a_uint32_t *value) -{ - union grp_profile_cnt_en_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_grp_profile_cnt_en_get(dev_id, ®_val); - *value = reg_val.bf.grp_cnt_en_0; - return ret; -} - -sw_error_t -hppe_grp_profile_cnt_en_grp_cnt_en_0_set( - a_uint32_t dev_id, - a_uint32_t value) -{ - union grp_profile_cnt_en_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_grp_profile_cnt_en_get(dev_id, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.grp_cnt_en_0 = value; - ret = hppe_grp_profile_cnt_en_set(dev_id, ®_val); - return ret; -} - -sw_error_t -hppe_grp_profile_cnt_en_grp_cnt_en_2_get( - a_uint32_t dev_id, - a_uint32_t *value) -{ - union grp_profile_cnt_en_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_grp_profile_cnt_en_get(dev_id, ®_val); - *value = reg_val.bf.grp_cnt_en_2; - return ret; -} - -sw_error_t -hppe_grp_profile_cnt_en_grp_cnt_en_2_set( - a_uint32_t dev_id, - a_uint32_t value) -{ - union grp_profile_cnt_en_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_grp_profile_cnt_en_get(dev_id, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.grp_cnt_en_2 = value; - ret = hppe_grp_profile_cnt_en_set(dev_id, ®_val); - return ret; -} - -sw_error_t -hppe_port_profile_th_cfg_port_profile_th_cfg_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union port_profile_th_cfg_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_port_profile_th_cfg_get(dev_id, index, ®_val); - *value = reg_val.bf.port_profile_th_cfg; - return ret; -} - -sw_error_t -hppe_port_profile_th_cfg_port_profile_th_cfg_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - union port_profile_th_cfg_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_port_profile_th_cfg_get(dev_id, index, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.port_profile_th_cfg = value; - ret = hppe_port_profile_th_cfg_set(dev_id, index, ®_val); - return ret; -} - -sw_error_t -hppe_react_profile_th_cfg_react_profile_th_cfg_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union react_profile_th_cfg_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_react_profile_th_cfg_get(dev_id, index, ®_val); - *value = reg_val.bf.react_profile_th_cfg; - return ret; -} - -sw_error_t -hppe_react_profile_th_cfg_react_profile_th_cfg_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - union react_profile_th_cfg_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_react_profile_th_cfg_get(dev_id, index, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.react_profile_th_cfg = value; - ret = hppe_react_profile_th_cfg_set(dev_id, index, ®_val); - return ret; -} - -sw_error_t -hppe_grp_profile_th_cfg_grp_profile_th_cfg_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union grp_profile_th_cfg_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_grp_profile_th_cfg_get(dev_id, index, ®_val); - *value = reg_val.bf.grp_profile_th_cfg; - return ret; -} - -sw_error_t -hppe_grp_profile_th_cfg_grp_profile_th_cfg_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - union grp_profile_th_cfg_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_grp_profile_th_cfg_get(dev_id, index, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.grp_profile_th_cfg = value; - ret = hppe_grp_profile_th_cfg_set(dev_id, index, ®_val); - return ret; -} - -sw_error_t -hppe_tot_react_profile_th_cfg_tot_react_profile_th_cfg_get( - a_uint32_t dev_id, - a_uint32_t *value) -{ - union tot_react_profile_th_cfg_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_tot_react_profile_th_cfg_get(dev_id, ®_val); - *value = reg_val.bf.tot_react_profile_th_cfg; - return ret; -} - -sw_error_t -hppe_tot_react_profile_th_cfg_tot_react_profile_th_cfg_set( - a_uint32_t dev_id, - a_uint32_t value) -{ - union tot_react_profile_th_cfg_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_tot_react_profile_th_cfg_get(dev_id, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.tot_react_profile_th_cfg = value; - ret = hppe_tot_react_profile_th_cfg_set(dev_id, ®_val); - return ret; -} - -sw_error_t -hppe_port_out_profile_cnt_port_out_profile_cnt_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union port_out_profile_cnt_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_port_out_profile_cnt_get(dev_id, index, ®_val); - *value = reg_val.bf.port_out_profile_cnt; - return ret; -} - -sw_error_t -hppe_port_out_profile_cnt_port_out_profile_cnt_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - union port_out_profile_cnt_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_port_out_profile_cnt_get(dev_id, index, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.port_out_profile_cnt = value; - ret = hppe_port_out_profile_cnt_set(dev_id, index, ®_val); - return ret; -} - -sw_error_t -hppe_port_in_profile_cnt_port_in_profile_cnt_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union port_in_profile_cnt_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_port_in_profile_cnt_get(dev_id, index, ®_val); - *value = reg_val.bf.port_in_profile_cnt; - return ret; -} - -sw_error_t -hppe_port_in_profile_cnt_port_in_profile_cnt_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - union port_in_profile_cnt_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_port_in_profile_cnt_get(dev_id, index, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.port_in_profile_cnt = value; - ret = hppe_port_in_profile_cnt_set(dev_id, index, ®_val); - return ret; -} - -sw_error_t -hppe_react_out_profile_cnt_react_out_profile_cnt_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union react_out_profile_cnt_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_react_out_profile_cnt_get(dev_id, index, ®_val); - *value = reg_val.bf.react_out_profile_cnt; - return ret; -} - -sw_error_t -hppe_react_out_profile_cnt_react_out_profile_cnt_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - union react_out_profile_cnt_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_react_out_profile_cnt_get(dev_id, index, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.react_out_profile_cnt = value; - ret = hppe_react_out_profile_cnt_set(dev_id, index, ®_val); - return ret; -} - -sw_error_t -hppe_react_in_profile_cnt_react_in_profile_cnt_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union react_in_profile_cnt_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_react_in_profile_cnt_get(dev_id, index, ®_val); - *value = reg_val.bf.react_in_profile_cnt; - return ret; -} - -sw_error_t -hppe_react_in_profile_cnt_react_in_profile_cnt_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - union react_in_profile_cnt_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_react_in_profile_cnt_get(dev_id, index, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.react_in_profile_cnt = value; - ret = hppe_react_in_profile_cnt_set(dev_id, index, ®_val); - return ret; -} - -sw_error_t -hppe_grp_out_profile_cnt_grp_out_profile_cnt_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union grp_out_profile_cnt_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_grp_out_profile_cnt_get(dev_id, index, ®_val); - *value = reg_val.bf.grp_out_profile_cnt; - return ret; -} - -sw_error_t -hppe_grp_out_profile_cnt_grp_out_profile_cnt_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - union grp_out_profile_cnt_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_grp_out_profile_cnt_get(dev_id, index, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.grp_out_profile_cnt = value; - ret = hppe_grp_out_profile_cnt_set(dev_id, index, ®_val); - return ret; -} - -sw_error_t -hppe_grp_in_profile_cnt_grp_in_profile_cnt_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union grp_in_profile_cnt_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_grp_in_profile_cnt_get(dev_id, index, ®_val); - *value = reg_val.bf.grp_in_profile_cnt; - return ret; -} - -sw_error_t -hppe_grp_in_profile_cnt_grp_in_profile_cnt_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - union grp_in_profile_cnt_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_grp_in_profile_cnt_get(dev_id, index, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.grp_in_profile_cnt = value; - ret = hppe_grp_in_profile_cnt_set(dev_id, index, ®_val); - return ret; -} - -sw_error_t -hppe_tot_react_out_profile_cnt_tot_react_out_profile_cnt_get( - a_uint32_t dev_id, - a_uint32_t *value) -{ - union tot_react_out_profile_cnt_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_tot_react_out_profile_cnt_get(dev_id, ®_val); - *value = reg_val.bf.tot_react_out_profile_cnt; - return ret; -} - -sw_error_t -hppe_tot_react_out_profile_cnt_tot_react_out_profile_cnt_set( - a_uint32_t dev_id, - a_uint32_t value) -{ - union tot_react_out_profile_cnt_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_tot_react_out_profile_cnt_get(dev_id, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.tot_react_out_profile_cnt = value; - ret = hppe_tot_react_out_profile_cnt_set(dev_id, ®_val); - return ret; -} - -sw_error_t -hppe_tot_react_in_profile_cnt_tot_react_in_profile_cnt_get( - a_uint32_t dev_id, - a_uint32_t *value) -{ - union tot_react_in_profile_cnt_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_tot_react_in_profile_cnt_get(dev_id, ®_val); - *value = reg_val.bf.tot_react_in_profile_cnt; - return ret; -} - -sw_error_t -hppe_tot_react_in_profile_cnt_tot_react_in_profile_cnt_set( - a_uint32_t dev_id, - a_uint32_t value) -{ - union tot_react_in_profile_cnt_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_tot_react_in_profile_cnt_get(dev_id, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.tot_react_in_profile_cnt = value; - ret = hppe_tot_react_in_profile_cnt_set(dev_id, ®_val); - return ret; -} - -sw_error_t -hppe_port_fc_cfg_port_pre_alloc_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union port_fc_cfg_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_port_fc_cfg_get(dev_id, index, ®_val); - *value = reg_val.bf.port_pre_alloc; - return ret; -} - -sw_error_t -hppe_port_fc_cfg_port_pre_alloc_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - union port_fc_cfg_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_port_fc_cfg_get(dev_id, index, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.port_pre_alloc = value; - ret = hppe_port_fc_cfg_set(dev_id, index, ®_val); - return ret; -} - -sw_error_t -hppe_port_fc_cfg_port_resume_offset_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union port_fc_cfg_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_port_fc_cfg_get(dev_id, index, ®_val); - *value = reg_val.bf.port_resume_offset; - return ret; -} - -sw_error_t -hppe_port_fc_cfg_port_resume_offset_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - union port_fc_cfg_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_port_fc_cfg_get(dev_id, index, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.port_resume_offset = value; - ret = hppe_port_fc_cfg_set(dev_id, index, ®_val); - return ret; -} - -sw_error_t -hppe_port_fc_cfg_port_shared_dynamic_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union port_fc_cfg_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_port_fc_cfg_get(dev_id, index, ®_val); - *value = reg_val.bf.port_shared_dynamic; - return ret; -} - -sw_error_t -hppe_port_fc_cfg_port_shared_dynamic_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - union port_fc_cfg_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_port_fc_cfg_get(dev_id, index, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.port_shared_dynamic = value; - ret = hppe_port_fc_cfg_set(dev_id, index, ®_val); - return ret; -} - -sw_error_t -hppe_port_fc_cfg_port_shared_weight_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union port_fc_cfg_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_port_fc_cfg_get(dev_id, index, ®_val); - *value = reg_val.bf.port_shared_weight; - return ret; -} - -sw_error_t -hppe_port_fc_cfg_port_shared_weight_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - union port_fc_cfg_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_port_fc_cfg_get(dev_id, index, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.port_shared_weight = value; - ret = hppe_port_fc_cfg_set(dev_id, index, ®_val); - return ret; -} - -sw_error_t -hppe_port_fc_cfg_port_resume_floor_th_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union port_fc_cfg_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_port_fc_cfg_get(dev_id, index, ®_val); - *value = reg_val.bf.port_resume_floor_th; - return ret; -} - -sw_error_t -hppe_port_fc_cfg_port_resume_floor_th_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - union port_fc_cfg_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_port_fc_cfg_get(dev_id, index, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.port_resume_floor_th = value; - ret = hppe_port_fc_cfg_set(dev_id, index, ®_val); - return ret; -} - -sw_error_t -hppe_port_fc_cfg_port_react_limit_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union port_fc_cfg_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_port_fc_cfg_get(dev_id, index, ®_val); - *value = reg_val.bf.port_react_limit; - return ret; -} - -sw_error_t -hppe_port_fc_cfg_port_react_limit_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - union port_fc_cfg_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_port_fc_cfg_get(dev_id, index, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.port_react_limit = value; - ret = hppe_port_fc_cfg_set(dev_id, index, ®_val); - return ret; -} - -sw_error_t -hppe_port_fc_cfg_port_shared_ceiling_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union port_fc_cfg_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_port_fc_cfg_get(dev_id, index, ®_val); - *value = reg_val.bf.port_shared_ceiling_1 << 3 | \ - reg_val.bf.port_shared_ceiling_0; - return ret; -} - -sw_error_t -hppe_port_fc_cfg_port_shared_ceiling_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - union port_fc_cfg_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_port_fc_cfg_get(dev_id, index, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.port_shared_ceiling_1 = value >> 3; - reg_val.bf.port_shared_ceiling_0 = value & (((a_uint64_t)1<<3)-1); - ret = hppe_port_fc_cfg_set(dev_id, index, ®_val); - return ret; -} - -sw_error_t -hppe_llm_eop_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union llm_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_llm_get(dev_id, index, ®_val); - *value = reg_val.bf.eop; - return ret; -} - -sw_error_t -hppe_llm_eop_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - union llm_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_llm_get(dev_id, index, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.eop = value; - ret = hppe_llm_set(dev_id, index, ®_val); - return ret; -} - -sw_error_t -hppe_llm_nxt_ptr_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union llm_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_llm_get(dev_id, index, ®_val); - *value = reg_val.bf.nxt_ptr; - return ret; -} - -sw_error_t -hppe_llm_nxt_ptr_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - union llm_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_llm_get(dev_id, index, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.nxt_ptr = value; - ret = hppe_llm_set(dev_id, index, ®_val); - return ret; -} - -sw_error_t -hppe_rcm_ref_cnt_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union rcm_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_rcm_get(dev_id, index, ®_val); - *value = reg_val.bf.ref_cnt; - return ret; -} - -sw_error_t -hppe_rcm_ref_cnt_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - union rcm_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_rcm_get(dev_id, index, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.ref_cnt = value; - ret = hppe_rcm_set(dev_id, index, ®_val); - return ret; -} - -sw_error_t -hppe_dm_pkt_data_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint64_t *value) -{ - union dm_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_dm_get(dev_id, index, ®_val); - *value = (a_uint64_t)reg_val.bf.pkt_data_1 << 32 | \ - reg_val.bf.pkt_data_0; - return ret; -} - -sw_error_t -hppe_dm_pkt_data_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint64_t value) -{ - union dm_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_dm_get(dev_id, index, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.pkt_data_1 = value >> 32; - reg_val.bf.pkt_data_0 = value & (((a_uint64_t)1<<32)-1); - ret = hppe_dm_set(dev_id, index, ®_val); - return ret; -} -#endif diff --git a/feeds/ipq807x/qca-ssdk/src/src/hsl/hppe/hppe_ctrlpkt.c b/feeds/ipq807x/qca-ssdk/src/src/hsl/hppe/hppe_ctrlpkt.c deleted file mode 100755 index a3ff31440..000000000 --- a/feeds/ipq807x/qca-ssdk/src/src/hsl/hppe/hppe_ctrlpkt.c +++ /dev/null @@ -1,581 +0,0 @@ -/* - * Copyright (c) 2016-2017, The Linux Foundation. All rights reserved. - * Permission to use, copy, modify, and/or distribute this software for - * any purpose with or without fee is hereby granted, provided that the - * above copyright notice and this permission notice appear in all copies. - * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES - * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR - * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES - * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN - * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT - * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. - */ - - -/** - * @defgroup - * @{ - */ -#include "sw.h" -#include "hsl.h" -#include "hppe_reg_access.h" -#include "hppe_ctrlpkt_reg.h" -#include "hppe_ctrlpkt.h" - -sw_error_t -hppe_ethertype_ctrl_get( - a_uint32_t dev_id, - a_uint32_t index, - union ethertype_ctrl_u *value) -{ - if (index >= ETHERTYPE_CTRL_MAX_ENTRY) - return SW_OUT_OF_RANGE; - return hppe_reg_get( - dev_id, - IPE_L2_BASE_ADDR + ETHERTYPE_CTRL_ADDRESS + \ - index * ETHERTYPE_CTRL_INC, - &value->val); -} - -sw_error_t -hppe_ethertype_ctrl_set( - a_uint32_t dev_id, - a_uint32_t index, - union ethertype_ctrl_u *value) -{ - return hppe_reg_set( - dev_id, - IPE_L2_BASE_ADDR + ETHERTYPE_CTRL_ADDRESS + \ - index * ETHERTYPE_CTRL_INC, - value->val); -} - -sw_error_t -hppe_app_ctrl_get( - a_uint32_t dev_id, - a_uint32_t index, - union app_ctrl_u *value) -{ - return hppe_reg_tbl_get( - dev_id, - IPE_L2_BASE_ADDR + APP_CTRL_ADDRESS + \ - index * APP_CTRL_INC, - value->val, - 3); -} - -sw_error_t -hppe_app_ctrl_set( - a_uint32_t dev_id, - a_uint32_t index, - union app_ctrl_u *value) -{ - return hppe_reg_tbl_set( - dev_id, - IPE_L2_BASE_ADDR + APP_CTRL_ADDRESS + \ - index * APP_CTRL_INC, - value->val, - 3); -} - -sw_error_t -hppe_ethertype_ctrl_ethertype_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union ethertype_ctrl_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_ethertype_ctrl_get(dev_id, index, ®_val); - *value = reg_val.bf.ethertype; - return ret; -} - -sw_error_t -hppe_ethertype_ctrl_ethertype_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - union ethertype_ctrl_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_ethertype_ctrl_get(dev_id, index, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.ethertype = value; - ret = hppe_ethertype_ctrl_set(dev_id, index, ®_val); - return ret; -} - -sw_error_t -hppe_ethertype_ctrl_ethertype_en_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union ethertype_ctrl_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_ethertype_ctrl_get(dev_id, index, ®_val); - *value = reg_val.bf.ethertype_en; - return ret; -} - -sw_error_t -hppe_ethertype_ctrl_ethertype_en_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - union ethertype_ctrl_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_ethertype_ctrl_get(dev_id, index, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.ethertype_en = value; - ret = hppe_ethertype_ctrl_set(dev_id, index, ®_val); - return ret; -} - -sw_error_t -hppe_app_ctrl_portbitmap_include_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union app_ctrl_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_app_ctrl_get(dev_id, index, ®_val); - *value = reg_val.bf.portbitmap_include; - return ret; -} - -sw_error_t -hppe_app_ctrl_portbitmap_include_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - union app_ctrl_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_app_ctrl_get(dev_id, index, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.portbitmap_include = value; - ret = hppe_app_ctrl_set(dev_id, index, ®_val); - return ret; -} - -sw_error_t -hppe_app_ctrl_cmd_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union app_ctrl_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_app_ctrl_get(dev_id, index, ®_val); - *value = reg_val.bf.cmd; - return ret; -} - -sw_error_t -hppe_app_ctrl_cmd_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - union app_ctrl_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_app_ctrl_get(dev_id, index, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.cmd = value; - ret = hppe_app_ctrl_set(dev_id, index, ®_val); - return ret; -} - -sw_error_t -hppe_app_ctrl_portbitmap_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union app_ctrl_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_app_ctrl_get(dev_id, index, ®_val); - *value = reg_val.bf.portbitmap; - return ret; -} - -sw_error_t -hppe_app_ctrl_portbitmap_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - union app_ctrl_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_app_ctrl_get(dev_id, index, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.portbitmap = value; - ret = hppe_app_ctrl_set(dev_id, index, ®_val); - return ret; -} - -sw_error_t -hppe_app_ctrl_rfdb_index_bitmap_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union app_ctrl_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_app_ctrl_get(dev_id, index, ®_val); - *value = reg_val.bf.rfdb_index_bitmap_1 << 30 | \ - reg_val.bf.rfdb_index_bitmap_0; - return ret; -} - -sw_error_t -hppe_app_ctrl_rfdb_index_bitmap_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - union app_ctrl_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_app_ctrl_get(dev_id, index, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.rfdb_index_bitmap_1 = value >> 30; - reg_val.bf.rfdb_index_bitmap_0 = value & (((a_uint64_t)1<<30)-1); - ret = hppe_app_ctrl_set(dev_id, index, ®_val); - return ret; -} - -sw_error_t -hppe_app_ctrl_protocol_bitmap_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union app_ctrl_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_app_ctrl_get(dev_id, index, ®_val); - *value = reg_val.bf.protocol_bitmap; - return ret; -} - -sw_error_t -hppe_app_ctrl_protocol_bitmap_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - union app_ctrl_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_app_ctrl_get(dev_id, index, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.protocol_bitmap = value; - ret = hppe_app_ctrl_set(dev_id, index, ®_val); - return ret; -} - -sw_error_t -hppe_app_ctrl_in_stg_byp_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union app_ctrl_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_app_ctrl_get(dev_id, index, ®_val); - *value = reg_val.bf.in_stg_byp; - return ret; -} - -sw_error_t -hppe_app_ctrl_in_stg_byp_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - union app_ctrl_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_app_ctrl_get(dev_id, index, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.in_stg_byp = value; - ret = hppe_app_ctrl_set(dev_id, index, ®_val); - return ret; -} - -sw_error_t -hppe_app_ctrl_valid_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union app_ctrl_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_app_ctrl_get(dev_id, index, ®_val); - *value = reg_val.bf.valid; - return ret; -} - -sw_error_t -hppe_app_ctrl_valid_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - union app_ctrl_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_app_ctrl_get(dev_id, index, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.valid = value; - ret = hppe_app_ctrl_set(dev_id, index, ®_val); - return ret; -} - -sw_error_t -hppe_app_ctrl_l2_sec_byp_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union app_ctrl_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_app_ctrl_get(dev_id, index, ®_val); - *value = reg_val.bf.l2_sec_byp; - return ret; -} - -sw_error_t -hppe_app_ctrl_l2_sec_byp_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - union app_ctrl_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_app_ctrl_get(dev_id, index, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.l2_sec_byp = value; - ret = hppe_app_ctrl_set(dev_id, index, ®_val); - return ret; -} - -sw_error_t -hppe_app_ctrl_protocol_include_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union app_ctrl_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_app_ctrl_get(dev_id, index, ®_val); - *value = reg_val.bf.protocol_include; - return ret; -} - -sw_error_t -hppe_app_ctrl_protocol_include_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - union app_ctrl_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_app_ctrl_get(dev_id, index, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.protocol_include = value; - ret = hppe_app_ctrl_set(dev_id, index, ®_val); - return ret; -} - -sw_error_t -hppe_app_ctrl_ethertype_include_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union app_ctrl_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_app_ctrl_get(dev_id, index, ®_val); - *value = reg_val.bf.ethertype_include; - return ret; -} - -sw_error_t -hppe_app_ctrl_ethertype_include_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - union app_ctrl_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_app_ctrl_get(dev_id, index, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.ethertype_include = value; - ret = hppe_app_ctrl_set(dev_id, index, ®_val); - return ret; -} - -sw_error_t -hppe_app_ctrl_sg_byp_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union app_ctrl_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_app_ctrl_get(dev_id, index, ®_val); - *value = reg_val.bf.sg_byp; - return ret; -} - -sw_error_t -hppe_app_ctrl_sg_byp_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - union app_ctrl_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_app_ctrl_get(dev_id, index, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.sg_byp = value; - ret = hppe_app_ctrl_set(dev_id, index, ®_val); - return ret; -} - -sw_error_t -hppe_app_ctrl_rfdb_include_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union app_ctrl_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_app_ctrl_get(dev_id, index, ®_val); - *value = reg_val.bf.rfdb_include; - return ret; -} - -sw_error_t -hppe_app_ctrl_rfdb_include_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - union app_ctrl_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_app_ctrl_get(dev_id, index, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.rfdb_include = value; - ret = hppe_app_ctrl_set(dev_id, index, ®_val); - return ret; -} - -sw_error_t -hppe_app_ctrl_ethertype_index_bitmap_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union app_ctrl_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_app_ctrl_get(dev_id, index, ®_val); - *value = reg_val.bf.ethertype_index_bitmap_1 << 2 | \ - reg_val.bf.ethertype_index_bitmap_0; - return ret; -} - -sw_error_t -hppe_app_ctrl_ethertype_index_bitmap_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - union app_ctrl_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_app_ctrl_get(dev_id, index, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.ethertype_index_bitmap_1 = value >> 2; - reg_val.bf.ethertype_index_bitmap_0 = value & (((a_uint64_t)1<<2)-1); - ret = hppe_app_ctrl_set(dev_id, index, ®_val); - return ret; -} - -sw_error_t -hppe_app_ctrl_in_vlan_fltr_byp_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union app_ctrl_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_app_ctrl_get(dev_id, index, ®_val); - *value = reg_val.bf.in_vlan_fltr_byp; - return ret; -} - -sw_error_t -hppe_app_ctrl_in_vlan_fltr_byp_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - union app_ctrl_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_app_ctrl_get(dev_id, index, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.in_vlan_fltr_byp = value; - ret = hppe_app_ctrl_set(dev_id, index, ®_val); - return ret; -} - diff --git a/feeds/ipq807x/qca-ssdk/src/src/hsl/hppe/hppe_fdb.c b/feeds/ipq807x/qca-ssdk/src/src/hsl/hppe/hppe_fdb.c deleted file mode 100755 index 43481d071..000000000 --- a/feeds/ipq807x/qca-ssdk/src/src/hsl/hppe/hppe_fdb.c +++ /dev/null @@ -1,2178 +0,0 @@ -/* - * Copyright (c) 2016-2017, The Linux Foundation. All rights reserved. - * Permission to use, copy, modify, and/or distribute this software for - * any purpose with or without fee is hereby granted, provided that the - * above copyright notice and this permission notice appear in all copies. - * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES - * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR - * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES - * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN - * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT - * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. - */ - - -/** - * @defgroup - * @{ - */ -#include "sw.h" -#include "hsl.h" -#include "hppe_reg_access.h" -#include "hppe_fdb_reg.h" -#include "hppe_fdb.h" -#ifndef IN_FDB_MINI -sw_error_t -hppe_l2_dbg_addr_get( - a_uint32_t dev_id, - union l2_dbg_addr_u *value) -{ - return hppe_reg_get( - dev_id, - IPE_L2_BASE_ADDR + L2_DBG_ADDR_ADDRESS, - &value->val); -} - -sw_error_t -hppe_l2_dbg_addr_set( - a_uint32_t dev_id, - union l2_dbg_addr_u *value) -{ - return hppe_reg_set( - dev_id, - IPE_L2_BASE_ADDR + L2_DBG_ADDR_ADDRESS, - value->val); -} - -sw_error_t -hppe_l2_dbg_data_get( - a_uint32_t dev_id, - union l2_dbg_data_u *value) -{ - return hppe_reg_get( - dev_id, - IPE_L2_BASE_ADDR + L2_DBG_DATA_ADDRESS, - &value->val); -} - -sw_error_t -hppe_l2_dbg_data_set( - a_uint32_t dev_id, - union l2_dbg_data_u *value) -{ - return SW_NOT_SUPPORTED; -} - -sw_error_t -hppe_fdb_tbl_op_get( - a_uint32_t dev_id, - union fdb_tbl_op_u *value) -{ - return hppe_reg_get( - dev_id, - IPE_L2_BASE_ADDR + FDB_TBL_OP_ADDRESS, - &value->val); -} -#endif -sw_error_t -hppe_fdb_tbl_op_set( - a_uint32_t dev_id, - union fdb_tbl_op_u *value) -{ - return hppe_reg_set( - dev_id, - IPE_L2_BASE_ADDR + FDB_TBL_OP_ADDRESS, - value->val); -} -#ifndef IN_FDB_MINI -sw_error_t -hppe_fdb_tbl_rd_op_get( - a_uint32_t dev_id, - union fdb_tbl_rd_op_u *value) -{ - return hppe_reg_get( - dev_id, - IPE_L2_BASE_ADDR + FDB_TBL_RD_OP_ADDRESS, - &value->val); -} -#endif -sw_error_t -hppe_fdb_tbl_rd_op_set( - a_uint32_t dev_id, - union fdb_tbl_rd_op_u *value) -{ - return hppe_reg_set( - dev_id, - IPE_L2_BASE_ADDR + FDB_TBL_RD_OP_ADDRESS, - value->val); -} - -sw_error_t -hppe_fdb_tbl_op_rslt_get( - a_uint32_t dev_id, - union fdb_tbl_op_rslt_u *value) -{ - return hppe_reg_get( - dev_id, - IPE_L2_BASE_ADDR + FDB_TBL_OP_RSLT_ADDRESS, - &value->val); -} -#ifndef IN_FDB_MINI -sw_error_t -hppe_fdb_tbl_op_rslt_set( - a_uint32_t dev_id, - union fdb_tbl_op_rslt_u *value) -{ - return SW_NOT_SUPPORTED; -} -#endif -sw_error_t -hppe_fdb_tbl_rd_op_rslt_get( - a_uint32_t dev_id, - union fdb_tbl_rd_op_rslt_u *value) -{ - return hppe_reg_get( - dev_id, - IPE_L2_BASE_ADDR + FDB_TBL_RD_OP_RSLT_ADDRESS, - &value->val); -} -#ifndef IN_FDB_MINI -sw_error_t -hppe_fdb_tbl_rd_op_rslt_set( - a_uint32_t dev_id, - union fdb_tbl_rd_op_rslt_u *value) -{ - return SW_NOT_SUPPORTED; -} - -sw_error_t -hppe_age_timer_get( - a_uint32_t dev_id, - union age_timer_u *value) -{ - return hppe_reg_get( - dev_id, - IPE_L2_BASE_ADDR + AGE_TIMER_ADDRESS, - &value->val); -} - -sw_error_t -hppe_age_timer_set( - a_uint32_t dev_id, - union age_timer_u *value) -{ - return hppe_reg_set( - dev_id, - IPE_L2_BASE_ADDR + AGE_TIMER_ADDRESS, - value->val); -} -#endif -sw_error_t -hppe_l2_global_conf_get( - a_uint32_t dev_id, - union l2_global_conf_u *value) -{ - return hppe_reg_get( - dev_id, - IPE_L2_BASE_ADDR + L2_GLOBAL_CONF_ADDRESS, - &value->val); -} - -sw_error_t -hppe_l2_global_conf_set( - a_uint32_t dev_id, - union l2_global_conf_u *value) -{ - return hppe_reg_set( - dev_id, - IPE_L2_BASE_ADDR + L2_GLOBAL_CONF_ADDRESS, - value->val); -} -#ifndef IN_FDB_MINI -sw_error_t -hppe_l2_dbgcnt_cmd_get( - a_uint32_t dev_id, - union l2_dbgcnt_cmd_u *value) -{ - return hppe_reg_get( - dev_id, - IPE_L2_BASE_ADDR + L2_DBGCNT_CMD_ADDRESS, - &value->val); -} - -sw_error_t -hppe_l2_dbgcnt_cmd_set( - a_uint32_t dev_id, - union l2_dbgcnt_cmd_u *value) -{ - return hppe_reg_set( - dev_id, - IPE_L2_BASE_ADDR + L2_DBGCNT_CMD_ADDRESS, - value->val); -} - -sw_error_t -hppe_l2_dbgcnt_rdata_get( - a_uint32_t dev_id, - union l2_dbgcnt_rdata_u *value) -{ - return hppe_reg_get( - dev_id, - IPE_L2_BASE_ADDR + L2_DBGCNT_RDATA_ADDRESS, - &value->val); -} - -sw_error_t -hppe_l2_dbgcnt_rdata_set( - a_uint32_t dev_id, - union l2_dbgcnt_rdata_u *value) -{ - return SW_NOT_SUPPORTED; -} - -sw_error_t -hppe_l2_dbgcnt_wdata_get( - a_uint32_t dev_id, - union l2_dbgcnt_wdata_u *value) -{ - return hppe_reg_get( - dev_id, - IPE_L2_BASE_ADDR + L2_DBGCNT_WDATA_ADDRESS, - &value->val); -} - -sw_error_t -hppe_l2_dbgcnt_wdata_set( - a_uint32_t dev_id, - union l2_dbgcnt_wdata_u *value) -{ - return hppe_reg_set( - dev_id, - IPE_L2_BASE_ADDR + L2_DBGCNT_WDATA_ADDRESS, - value->val); -} -#endif -sw_error_t -hppe_fdb_tbl_rd_op_rslt_data0_get( - a_uint32_t dev_id, - union fdb_tbl_rd_op_rslt_data0_u *value) -{ - return hppe_reg_get( - dev_id, - IPE_L2_BASE_ADDR + FDB_TBL_RD_OP_RSLT_DATA0_ADDRESS, - &value->val); -} - -sw_error_t -hppe_fdb_tbl_rd_op_rslt_data0_set( - a_uint32_t dev_id, - union fdb_tbl_rd_op_rslt_data0_u *value) -{ - return SW_NOT_SUPPORTED; -} - -sw_error_t -hppe_fdb_tbl_rd_op_rslt_data1_get( - a_uint32_t dev_id, - union fdb_tbl_rd_op_rslt_data1_u *value) -{ - return hppe_reg_get( - dev_id, - IPE_L2_BASE_ADDR + FDB_TBL_RD_OP_RSLT_DATA1_ADDRESS, - &value->val); -} -#ifndef IN_FDB_MINI -sw_error_t -hppe_fdb_tbl_rd_op_rslt_data1_set( - a_uint32_t dev_id, - union fdb_tbl_rd_op_rslt_data1_u *value) -{ - return SW_NOT_SUPPORTED; -} -#endif -sw_error_t -hppe_fdb_tbl_rd_op_rslt_data2_get( - a_uint32_t dev_id, - union fdb_tbl_rd_op_rslt_data2_u *value) -{ - return hppe_reg_get( - dev_id, - IPE_L2_BASE_ADDR + FDB_TBL_RD_OP_RSLT_DATA2_ADDRESS, - &value->val); -} -#ifndef IN_FDB_MINI -sw_error_t -hppe_fdb_tbl_rd_op_rslt_data2_set( - a_uint32_t dev_id, - union fdb_tbl_rd_op_rslt_data2_u *value) -{ - return SW_NOT_SUPPORTED; -} -#endif -sw_error_t -hppe_fdb_tbl_op_data0_get( - a_uint32_t dev_id, - union fdb_tbl_op_data0_u *value) -{ - return hppe_reg_get( - dev_id, - IPE_L2_BASE_ADDR + FDB_TBL_OP_DATA0_ADDRESS, - &value->val); -} - -sw_error_t -hppe_fdb_tbl_op_data0_set( - a_uint32_t dev_id, - union fdb_tbl_op_data0_u *value) -{ - return hppe_reg_set( - dev_id, - IPE_L2_BASE_ADDR + FDB_TBL_OP_DATA0_ADDRESS, - value->val); -} - -sw_error_t -hppe_fdb_tbl_op_data1_get( - a_uint32_t dev_id, - union fdb_tbl_op_data1_u *value) -{ - return hppe_reg_get( - dev_id, - IPE_L2_BASE_ADDR + FDB_TBL_OP_DATA1_ADDRESS, - &value->val); -} - -sw_error_t -hppe_fdb_tbl_op_data1_set( - a_uint32_t dev_id, - union fdb_tbl_op_data1_u *value) -{ - return hppe_reg_set( - dev_id, - IPE_L2_BASE_ADDR + FDB_TBL_OP_DATA1_ADDRESS, - value->val); -} - -sw_error_t -hppe_fdb_tbl_op_data2_get( - a_uint32_t dev_id, - union fdb_tbl_op_data2_u *value) -{ - return hppe_reg_get( - dev_id, - IPE_L2_BASE_ADDR + FDB_TBL_OP_DATA2_ADDRESS, - &value->val); -} - -sw_error_t -hppe_fdb_tbl_op_data2_set( - a_uint32_t dev_id, - union fdb_tbl_op_data2_u *value) -{ - return hppe_reg_set( - dev_id, - IPE_L2_BASE_ADDR + FDB_TBL_OP_DATA2_ADDRESS, - value->val); -} - -sw_error_t -hppe_fdb_tbl_rd_op_data0_get( - a_uint32_t dev_id, - union fdb_tbl_rd_op_data0_u *value) -{ - return hppe_reg_get( - dev_id, - IPE_L2_BASE_ADDR + FDB_TBL_RD_OP_DATA0_ADDRESS, - &value->val); -} - -sw_error_t -hppe_fdb_tbl_rd_op_data0_set( - a_uint32_t dev_id, - union fdb_tbl_rd_op_data0_u *value) -{ - return hppe_reg_set( - dev_id, - IPE_L2_BASE_ADDR + FDB_TBL_RD_OP_DATA0_ADDRESS, - value->val); -} - -sw_error_t -hppe_fdb_tbl_rd_op_data1_get( - a_uint32_t dev_id, - union fdb_tbl_rd_op_data1_u *value) -{ - return hppe_reg_get( - dev_id, - IPE_L2_BASE_ADDR + FDB_TBL_RD_OP_DATA1_ADDRESS, - &value->val); -} - -sw_error_t -hppe_fdb_tbl_rd_op_data1_set( - a_uint32_t dev_id, - union fdb_tbl_rd_op_data1_u *value) -{ - return hppe_reg_set( - dev_id, - IPE_L2_BASE_ADDR + FDB_TBL_RD_OP_DATA1_ADDRESS, - value->val); -} - -sw_error_t -hppe_fdb_tbl_rd_op_data2_get( - a_uint32_t dev_id, - union fdb_tbl_rd_op_data2_u *value) -{ - return hppe_reg_get( - dev_id, - IPE_L2_BASE_ADDR + FDB_TBL_RD_OP_DATA2_ADDRESS, - &value->val); -} - -sw_error_t -hppe_fdb_tbl_rd_op_data2_set( - a_uint32_t dev_id, - union fdb_tbl_rd_op_data2_u *value) -{ - return hppe_reg_set( - dev_id, - IPE_L2_BASE_ADDR + FDB_TBL_RD_OP_DATA2_ADDRESS, - value->val); -} - -sw_error_t -hppe_port_bridge_ctrl_get( - a_uint32_t dev_id, - a_uint32_t index, - union port_bridge_ctrl_u *value) -{ - if (index >= PORT_BRIDGE_CTRL_MAX_ENTRY) - return SW_OUT_OF_RANGE; - return hppe_reg_get( - dev_id, - IPE_L2_BASE_ADDR + PORT_BRIDGE_CTRL_ADDRESS + \ - index * PORT_BRIDGE_CTRL_INC, - &value->val); -} - -sw_error_t -hppe_port_bridge_ctrl_set( - a_uint32_t dev_id, - a_uint32_t index, - union port_bridge_ctrl_u *value) -{ - return hppe_reg_set( - dev_id, - IPE_L2_BASE_ADDR + PORT_BRIDGE_CTRL_ADDRESS + \ - index * PORT_BRIDGE_CTRL_INC, - value->val); -} -#ifndef IN_FDB_MINI -sw_error_t -hppe_port_lrn_limit_ctrl_get( - a_uint32_t dev_id, - a_uint32_t index, - union port_lrn_limit_ctrl_u *value) -{ - if (index >= PORT_LRN_LIMIT_CTRL_MAX_ENTRY) - return SW_OUT_OF_RANGE; - return hppe_reg_get( - dev_id, - IPE_L2_BASE_ADDR + PORT_LRN_LIMIT_CTRL_ADDRESS + \ - index * PORT_LRN_LIMIT_CTRL_INC, - &value->val); -} - -sw_error_t -hppe_port_lrn_limit_ctrl_set( - a_uint32_t dev_id, - a_uint32_t index, - union port_lrn_limit_ctrl_u *value) -{ - return hppe_reg_set( - dev_id, - IPE_L2_BASE_ADDR + PORT_LRN_LIMIT_CTRL_ADDRESS + \ - index * PORT_LRN_LIMIT_CTRL_INC, - value->val); -} - -sw_error_t -hppe_port_lrn_limit_counter_get( - a_uint32_t dev_id, - a_uint32_t index, - union port_lrn_limit_counter_u *value) -{ - if (index >= PORT_LRN_LIMIT_COUNTER_MAX_ENTRY) - return SW_OUT_OF_RANGE; - return hppe_reg_get( - dev_id, - IPE_L2_BASE_ADDR + PORT_LRN_LIMIT_COUNTER_ADDRESS + \ - index * PORT_LRN_LIMIT_COUNTER_INC, - &value->val); -} - -sw_error_t -hppe_port_lrn_limit_counter_set( - a_uint32_t dev_id, - a_uint32_t index, - union port_lrn_limit_counter_u *value) -{ - return SW_NOT_SUPPORTED; -} -#endif -sw_error_t -hppe_rfdb_tbl_get( - a_uint32_t dev_id, - a_uint32_t index, - union rfdb_tbl_u *value) -{ - return hppe_reg_tbl_get( - dev_id, - IPE_L2_BASE_ADDR + RFDB_TBL_ADDRESS + \ - index * RFDB_TBL_INC, - value->val, - 2); -} - -sw_error_t -hppe_rfdb_tbl_set( - a_uint32_t dev_id, - a_uint32_t index, - union rfdb_tbl_u *value) -{ - return hppe_reg_tbl_set( - dev_id, - IPE_L2_BASE_ADDR + RFDB_TBL_ADDRESS + \ - index * RFDB_TBL_INC, - value->val, - 2); -} -#ifndef IN_FDB_MINI -sw_error_t -hppe_fdb_tbl_get( - a_uint32_t dev_id, - a_uint32_t index, - union fdb_tbl_u *value) -{ - return hppe_reg_tbl_get( - dev_id, - IPE_L2_BASE_ADDR + FDB_TBL_ADDRESS + \ - index * FDB_TBL_INC, - value->val, - 3); -} - -sw_error_t -hppe_fdb_tbl_set( - a_uint32_t dev_id, - a_uint32_t index, - union fdb_tbl_u *value) -{ - return hppe_reg_tbl_set( - dev_id, - IPE_L2_BASE_ADDR + FDB_TBL_ADDRESS + \ - index * FDB_TBL_INC, - value->val, - 3); -} - -sw_error_t -hppe_l2_dbg_addr_l2_dbg_addr_get( - a_uint32_t dev_id, - a_uint32_t *value) -{ - union l2_dbg_addr_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_l2_dbg_addr_get(dev_id, ®_val); - *value = reg_val.bf.l2_dbg_addr; - return ret; -} - -sw_error_t -hppe_l2_dbg_addr_l2_dbg_addr_set( - a_uint32_t dev_id, - a_uint32_t value) -{ - union l2_dbg_addr_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_l2_dbg_addr_get(dev_id, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.l2_dbg_addr = value; - ret = hppe_l2_dbg_addr_set(dev_id, ®_val); - return ret; -} - -sw_error_t -hppe_l2_dbg_data_l2_dbg_data_get( - a_uint32_t dev_id, - a_uint32_t *value) -{ - union l2_dbg_data_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_l2_dbg_data_get(dev_id, ®_val); - *value = reg_val.bf.l2_dbg_data; - return ret; -} - -sw_error_t -hppe_l2_dbg_data_l2_dbg_data_set( - a_uint32_t dev_id, - a_uint32_t value) -{ - return SW_NOT_SUPPORTED; -} - -sw_error_t -hppe_fdb_tbl_op_op_mode_get( - a_uint32_t dev_id, - a_uint32_t *value) -{ - union fdb_tbl_op_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_fdb_tbl_op_get(dev_id, ®_val); - *value = reg_val.bf.op_mode; - return ret; -} - -sw_error_t -hppe_fdb_tbl_op_op_mode_set( - a_uint32_t dev_id, - a_uint32_t value) -{ - union fdb_tbl_op_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_fdb_tbl_op_get(dev_id, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.op_mode = value; - ret = hppe_fdb_tbl_op_set(dev_id, ®_val); - return ret; -} - -sw_error_t -hppe_fdb_tbl_op_op_type_get( - a_uint32_t dev_id, - a_uint32_t *value) -{ - union fdb_tbl_op_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_fdb_tbl_op_get(dev_id, ®_val); - *value = reg_val.bf.op_type; - return ret; -} - -sw_error_t -hppe_fdb_tbl_op_op_type_set( - a_uint32_t dev_id, - a_uint32_t value) -{ - union fdb_tbl_op_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_fdb_tbl_op_get(dev_id, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.op_type = value; - ret = hppe_fdb_tbl_op_set(dev_id, ®_val); - return ret; -} - -sw_error_t -hppe_fdb_tbl_op_entry_index_get( - a_uint32_t dev_id, - a_uint32_t *value) -{ - union fdb_tbl_op_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_fdb_tbl_op_get(dev_id, ®_val); - *value = reg_val.bf.entry_index; - return ret; -} - -sw_error_t -hppe_fdb_tbl_op_entry_index_set( - a_uint32_t dev_id, - a_uint32_t value) -{ - union fdb_tbl_op_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_fdb_tbl_op_get(dev_id, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.entry_index = value; - ret = hppe_fdb_tbl_op_set(dev_id, ®_val); - return ret; -} - -sw_error_t -hppe_fdb_tbl_op_cmd_id_get( - a_uint32_t dev_id, - a_uint32_t *value) -{ - union fdb_tbl_op_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_fdb_tbl_op_get(dev_id, ®_val); - *value = reg_val.bf.cmd_id; - return ret; -} - -sw_error_t -hppe_fdb_tbl_op_cmd_id_set( - a_uint32_t dev_id, - a_uint32_t value) -{ - union fdb_tbl_op_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_fdb_tbl_op_get(dev_id, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.cmd_id = value; - ret = hppe_fdb_tbl_op_set(dev_id, ®_val); - return ret; -} - -sw_error_t -hppe_fdb_tbl_op_hash_block_bitmap_get( - a_uint32_t dev_id, - a_uint32_t *value) -{ - union fdb_tbl_op_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_fdb_tbl_op_get(dev_id, ®_val); - *value = reg_val.bf.hash_block_bitmap; - return ret; -} - -sw_error_t -hppe_fdb_tbl_op_hash_block_bitmap_set( - a_uint32_t dev_id, - a_uint32_t value) -{ - union fdb_tbl_op_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_fdb_tbl_op_get(dev_id, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.hash_block_bitmap = value; - ret = hppe_fdb_tbl_op_set(dev_id, ®_val); - return ret; -} - -sw_error_t -hppe_fdb_tbl_op_byp_rslt_en_get( - a_uint32_t dev_id, - a_uint32_t *value) -{ - union fdb_tbl_op_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_fdb_tbl_op_get(dev_id, ®_val); - *value = reg_val.bf.byp_rslt_en; - return ret; -} - -sw_error_t -hppe_fdb_tbl_op_byp_rslt_en_set( - a_uint32_t dev_id, - a_uint32_t value) -{ - union fdb_tbl_op_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_fdb_tbl_op_get(dev_id, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.byp_rslt_en = value; - ret = hppe_fdb_tbl_op_set(dev_id, ®_val); - return ret; -} - -sw_error_t -hppe_fdb_tbl_rd_op_op_mode_get( - a_uint32_t dev_id, - a_uint32_t *value) -{ - union fdb_tbl_rd_op_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_fdb_tbl_rd_op_get(dev_id, ®_val); - *value = reg_val.bf.op_mode; - return ret; -} - -sw_error_t -hppe_fdb_tbl_rd_op_op_mode_set( - a_uint32_t dev_id, - a_uint32_t value) -{ - union fdb_tbl_rd_op_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_fdb_tbl_rd_op_get(dev_id, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.op_mode = value; - ret = hppe_fdb_tbl_rd_op_set(dev_id, ®_val); - return ret; -} - -sw_error_t -hppe_fdb_tbl_rd_op_op_type_get( - a_uint32_t dev_id, - a_uint32_t *value) -{ - union fdb_tbl_rd_op_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_fdb_tbl_rd_op_get(dev_id, ®_val); - *value = reg_val.bf.op_type; - return ret; -} - -sw_error_t -hppe_fdb_tbl_rd_op_op_type_set( - a_uint32_t dev_id, - a_uint32_t value) -{ - union fdb_tbl_rd_op_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_fdb_tbl_rd_op_get(dev_id, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.op_type = value; - ret = hppe_fdb_tbl_rd_op_set(dev_id, ®_val); - return ret; -} - -sw_error_t -hppe_fdb_tbl_rd_op_entry_index_get( - a_uint32_t dev_id, - a_uint32_t *value) -{ - union fdb_tbl_rd_op_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_fdb_tbl_rd_op_get(dev_id, ®_val); - *value = reg_val.bf.entry_index; - return ret; -} - -sw_error_t -hppe_fdb_tbl_rd_op_entry_index_set( - a_uint32_t dev_id, - a_uint32_t value) -{ - union fdb_tbl_rd_op_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_fdb_tbl_rd_op_get(dev_id, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.entry_index = value; - ret = hppe_fdb_tbl_rd_op_set(dev_id, ®_val); - return ret; -} - -sw_error_t -hppe_fdb_tbl_rd_op_cmd_id_get( - a_uint32_t dev_id, - a_uint32_t *value) -{ - union fdb_tbl_rd_op_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_fdb_tbl_rd_op_get(dev_id, ®_val); - *value = reg_val.bf.cmd_id; - return ret; -} - -sw_error_t -hppe_fdb_tbl_rd_op_cmd_id_set( - a_uint32_t dev_id, - a_uint32_t value) -{ - union fdb_tbl_rd_op_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_fdb_tbl_rd_op_get(dev_id, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.cmd_id = value; - ret = hppe_fdb_tbl_rd_op_set(dev_id, ®_val); - return ret; -} - -sw_error_t -hppe_fdb_tbl_rd_op_hash_block_bitmap_get( - a_uint32_t dev_id, - a_uint32_t *value) -{ - union fdb_tbl_rd_op_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_fdb_tbl_rd_op_get(dev_id, ®_val); - *value = reg_val.bf.hash_block_bitmap; - return ret; -} - -sw_error_t -hppe_fdb_tbl_rd_op_hash_block_bitmap_set( - a_uint32_t dev_id, - a_uint32_t value) -{ - union fdb_tbl_rd_op_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_fdb_tbl_rd_op_get(dev_id, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.hash_block_bitmap = value; - ret = hppe_fdb_tbl_rd_op_set(dev_id, ®_val); - return ret; -} - -sw_error_t -hppe_fdb_tbl_rd_op_byp_rslt_en_get( - a_uint32_t dev_id, - a_uint32_t *value) -{ - union fdb_tbl_rd_op_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_fdb_tbl_rd_op_get(dev_id, ®_val); - *value = reg_val.bf.byp_rslt_en; - return ret; -} - -sw_error_t -hppe_fdb_tbl_rd_op_byp_rslt_en_set( - a_uint32_t dev_id, - a_uint32_t value) -{ - union fdb_tbl_rd_op_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_fdb_tbl_rd_op_get(dev_id, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.byp_rslt_en = value; - ret = hppe_fdb_tbl_rd_op_set(dev_id, ®_val); - return ret; -} - -sw_error_t -hppe_fdb_tbl_op_rslt_op_rslt_get( - a_uint32_t dev_id, - a_uint32_t *value) -{ - union fdb_tbl_op_rslt_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_fdb_tbl_op_rslt_get(dev_id, ®_val); - *value = reg_val.bf.op_rslt; - return ret; -} - -sw_error_t -hppe_fdb_tbl_op_rslt_op_rslt_set( - a_uint32_t dev_id, - a_uint32_t value) -{ - return SW_NOT_SUPPORTED; -} - -sw_error_t -hppe_fdb_tbl_op_rslt_valid_cnt_get( - a_uint32_t dev_id, - a_uint32_t *value) -{ - union fdb_tbl_op_rslt_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_fdb_tbl_op_rslt_get(dev_id, ®_val); - *value = reg_val.bf.valid_cnt; - return ret; -} - -sw_error_t -hppe_fdb_tbl_op_rslt_valid_cnt_set( - a_uint32_t dev_id, - a_uint32_t value) -{ - return SW_NOT_SUPPORTED; -} - -sw_error_t -hppe_fdb_tbl_op_rslt_entry_index_get( - a_uint32_t dev_id, - a_uint32_t *value) -{ - union fdb_tbl_op_rslt_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_fdb_tbl_op_rslt_get(dev_id, ®_val); - *value = reg_val.bf.entry_index; - return ret; -} - -sw_error_t -hppe_fdb_tbl_op_rslt_entry_index_set( - a_uint32_t dev_id, - a_uint32_t value) -{ - return SW_NOT_SUPPORTED; -} - -sw_error_t -hppe_fdb_tbl_op_rslt_cmd_id_get( - a_uint32_t dev_id, - a_uint32_t *value) -{ - union fdb_tbl_op_rslt_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_fdb_tbl_op_rslt_get(dev_id, ®_val); - *value = reg_val.bf.cmd_id; - return ret; -} - -sw_error_t -hppe_fdb_tbl_op_rslt_cmd_id_set( - a_uint32_t dev_id, - a_uint32_t value) -{ - return SW_NOT_SUPPORTED; -} - -sw_error_t -hppe_fdb_tbl_rd_op_rslt_op_rslt_get( - a_uint32_t dev_id, - a_uint32_t *value) -{ - union fdb_tbl_rd_op_rslt_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_fdb_tbl_rd_op_rslt_get(dev_id, ®_val); - *value = reg_val.bf.op_rslt; - return ret; -} - -sw_error_t -hppe_fdb_tbl_rd_op_rslt_op_rslt_set( - a_uint32_t dev_id, - a_uint32_t value) -{ - return SW_NOT_SUPPORTED; -} - -sw_error_t -hppe_fdb_tbl_rd_op_rslt_valid_cnt_get( - a_uint32_t dev_id, - a_uint32_t *value) -{ - union fdb_tbl_rd_op_rslt_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_fdb_tbl_rd_op_rslt_get(dev_id, ®_val); - *value = reg_val.bf.valid_cnt; - return ret; -} - -sw_error_t -hppe_fdb_tbl_rd_op_rslt_valid_cnt_set( - a_uint32_t dev_id, - a_uint32_t value) -{ - return SW_NOT_SUPPORTED; -} - -sw_error_t -hppe_fdb_tbl_rd_op_rslt_entry_index_get( - a_uint32_t dev_id, - a_uint32_t *value) -{ - union fdb_tbl_rd_op_rslt_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_fdb_tbl_rd_op_rslt_get(dev_id, ®_val); - *value = reg_val.bf.entry_index; - return ret; -} - -sw_error_t -hppe_fdb_tbl_rd_op_rslt_entry_index_set( - a_uint32_t dev_id, - a_uint32_t value) -{ - return SW_NOT_SUPPORTED; -} - -sw_error_t -hppe_fdb_tbl_rd_op_rslt_cmd_id_get( - a_uint32_t dev_id, - a_uint32_t *value) -{ - union fdb_tbl_rd_op_rslt_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_fdb_tbl_rd_op_rslt_get(dev_id, ®_val); - *value = reg_val.bf.cmd_id; - return ret; -} - -sw_error_t -hppe_fdb_tbl_rd_op_rslt_cmd_id_set( - a_uint32_t dev_id, - a_uint32_t value) -{ - return SW_NOT_SUPPORTED; -} - -sw_error_t -hppe_age_timer_age_val_get( - a_uint32_t dev_id, - a_uint32_t *value) -{ - union age_timer_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_age_timer_get(dev_id, ®_val); - *value = reg_val.bf.age_val; - return ret; -} - -sw_error_t -hppe_age_timer_age_val_set( - a_uint32_t dev_id, - a_uint32_t value) -{ - union age_timer_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_age_timer_get(dev_id, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.age_val = value; - ret = hppe_age_timer_set(dev_id, ®_val); - return ret; -} - -sw_error_t -hppe_l2_global_conf_fdb_hash_full_fwd_cmd_get( - a_uint32_t dev_id, - a_uint32_t *value) -{ - union l2_global_conf_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_l2_global_conf_get(dev_id, ®_val); - *value = reg_val.bf.fdb_hash_full_fwd_cmd; - return ret; -} - -sw_error_t -hppe_l2_global_conf_fdb_hash_full_fwd_cmd_set( - a_uint32_t dev_id, - a_uint32_t value) -{ - union l2_global_conf_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_l2_global_conf_get(dev_id, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.fdb_hash_full_fwd_cmd = value; - ret = hppe_l2_global_conf_set(dev_id, ®_val); - return ret; -} - -sw_error_t -hppe_l2_global_conf_failover_en_get( - a_uint32_t dev_id, - a_uint32_t *value) -{ - union l2_global_conf_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_l2_global_conf_get(dev_id, ®_val); - *value = reg_val.bf.failover_en; - return ret; -} - -sw_error_t -hppe_l2_global_conf_failover_en_set( - a_uint32_t dev_id, - a_uint32_t value) -{ - union l2_global_conf_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_l2_global_conf_get(dev_id, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.failover_en = value; - ret = hppe_l2_global_conf_set(dev_id, ®_val); - return ret; -} - -sw_error_t -hppe_l2_global_conf_lrn_ctrl_mode_get( - a_uint32_t dev_id, - a_uint32_t *value) -{ - union l2_global_conf_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_l2_global_conf_get(dev_id, ®_val); - *value = reg_val.bf.lrn_ctrl_mode; - return ret; -} - -sw_error_t -hppe_l2_global_conf_lrn_ctrl_mode_set( - a_uint32_t dev_id, - a_uint32_t value) -{ - union l2_global_conf_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_l2_global_conf_get(dev_id, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.lrn_ctrl_mode = value; - ret = hppe_l2_global_conf_set(dev_id, ®_val); - return ret; -} - -sw_error_t -hppe_l2_global_conf_age_en_get( - a_uint32_t dev_id, - a_uint32_t *value) -{ - union l2_global_conf_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_l2_global_conf_get(dev_id, ®_val); - *value = reg_val.bf.age_en; - return ret; -} - -sw_error_t -hppe_l2_global_conf_age_en_set( - a_uint32_t dev_id, - a_uint32_t value) -{ - union l2_global_conf_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_l2_global_conf_get(dev_id, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.age_en = value; - ret = hppe_l2_global_conf_set(dev_id, ®_val); - return ret; -} - -sw_error_t -hppe_l2_global_conf_fdb_hash_mode_1_get( - a_uint32_t dev_id, - a_uint32_t *value) -{ - union l2_global_conf_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_l2_global_conf_get(dev_id, ®_val); - *value = reg_val.bf.fdb_hash_mode_1; - return ret; -} - -sw_error_t -hppe_l2_global_conf_fdb_hash_mode_1_set( - a_uint32_t dev_id, - a_uint32_t value) -{ - union l2_global_conf_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_l2_global_conf_get(dev_id, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.fdb_hash_mode_1 = value; - ret = hppe_l2_global_conf_set(dev_id, ®_val); - return ret; -} - -sw_error_t -hppe_l2_global_conf_lrn_en_get( - a_uint32_t dev_id, - a_uint32_t *value) -{ - union l2_global_conf_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_l2_global_conf_get(dev_id, ®_val); - *value = reg_val.bf.lrn_en; - return ret; -} - -sw_error_t -hppe_l2_global_conf_lrn_en_set( - a_uint32_t dev_id, - a_uint32_t value) -{ - union l2_global_conf_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_l2_global_conf_get(dev_id, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.lrn_en = value; - ret = hppe_l2_global_conf_set(dev_id, ®_val); - return ret; -} - -sw_error_t -hppe_l2_global_conf_fdb_hash_mode_0_get( - a_uint32_t dev_id, - a_uint32_t *value) -{ - union l2_global_conf_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_l2_global_conf_get(dev_id, ®_val); - *value = reg_val.bf.fdb_hash_mode_0; - return ret; -} - -sw_error_t -hppe_l2_global_conf_fdb_hash_mode_0_set( - a_uint32_t dev_id, - a_uint32_t value) -{ - union l2_global_conf_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_l2_global_conf_get(dev_id, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.fdb_hash_mode_0 = value; - ret = hppe_l2_global_conf_set(dev_id, ®_val); - return ret; -} - -sw_error_t -hppe_l2_global_conf_age_ctrl_mode_get( - a_uint32_t dev_id, - a_uint32_t *value) -{ - union l2_global_conf_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_l2_global_conf_get(dev_id, ®_val); - *value = reg_val.bf.age_ctrl_mode; - return ret; -} - -sw_error_t -hppe_l2_global_conf_age_ctrl_mode_set( - a_uint32_t dev_id, - a_uint32_t value) -{ - union l2_global_conf_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_l2_global_conf_get(dev_id, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.age_ctrl_mode = value; - ret = hppe_l2_global_conf_set(dev_id, ®_val); - return ret; -} - -sw_error_t -hppe_l2_global_conf_service_code_loop_get( - a_uint32_t dev_id, - a_uint32_t *value) -{ - union l2_global_conf_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_l2_global_conf_get(dev_id, ®_val); - *value = reg_val.bf.service_code_loop; - return ret; -} - -sw_error_t -hppe_l2_global_conf_service_code_loop_set( - a_uint32_t dev_id, - a_uint32_t value) -{ - union l2_global_conf_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_l2_global_conf_get(dev_id, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.service_code_loop = value; - ret = hppe_l2_global_conf_set(dev_id, ®_val); - return ret; -} - -sw_error_t -hppe_l2_dbgcnt_cmd_type_get( - a_uint32_t dev_id, - a_uint32_t *value) -{ - union l2_dbgcnt_cmd_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_l2_dbgcnt_cmd_get(dev_id, ®_val); - *value = reg_val.bf.type; - return ret; -} - -sw_error_t -hppe_l2_dbgcnt_cmd_type_set( - a_uint32_t dev_id, - a_uint32_t value) -{ - union l2_dbgcnt_cmd_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_l2_dbgcnt_cmd_get(dev_id, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.type = value; - ret = hppe_l2_dbgcnt_cmd_set(dev_id, ®_val); - return ret; -} - -sw_error_t -hppe_l2_dbgcnt_cmd_addr_get( - a_uint32_t dev_id, - a_uint32_t *value) -{ - union l2_dbgcnt_cmd_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_l2_dbgcnt_cmd_get(dev_id, ®_val); - *value = reg_val.bf.addr; - return ret; -} - -sw_error_t -hppe_l2_dbgcnt_cmd_addr_set( - a_uint32_t dev_id, - a_uint32_t value) -{ - union l2_dbgcnt_cmd_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_l2_dbgcnt_cmd_get(dev_id, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.addr = value; - ret = hppe_l2_dbgcnt_cmd_set(dev_id, ®_val); - return ret; -} - -sw_error_t -hppe_l2_dbgcnt_rdata_data_get( - a_uint32_t dev_id, - a_uint32_t *value) -{ - union l2_dbgcnt_rdata_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_l2_dbgcnt_rdata_get(dev_id, ®_val); - *value = reg_val.bf.data; - return ret; -} - -sw_error_t -hppe_l2_dbgcnt_rdata_data_set( - a_uint32_t dev_id, - a_uint32_t value) -{ - return SW_NOT_SUPPORTED; -} - -sw_error_t -hppe_l2_dbgcnt_wdata_data_get( - a_uint32_t dev_id, - a_uint32_t *value) -{ - union l2_dbgcnt_wdata_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_l2_dbgcnt_wdata_get(dev_id, ®_val); - *value = reg_val.bf.data; - return ret; -} - -sw_error_t -hppe_l2_dbgcnt_wdata_data_set( - a_uint32_t dev_id, - a_uint32_t value) -{ - union l2_dbgcnt_wdata_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_l2_dbgcnt_wdata_get(dev_id, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.data = value; - ret = hppe_l2_dbgcnt_wdata_set(dev_id, ®_val); - return ret; -} -#endif -sw_error_t -hppe_fdb_tbl_rd_op_rslt_data0_data_get( - a_uint32_t dev_id, - a_uint32_t *value) -{ - union fdb_tbl_rd_op_rslt_data0_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_fdb_tbl_rd_op_rslt_data0_get(dev_id, ®_val); - *value = reg_val.bf.data; - return ret; -} -#ifndef IN_FDB_MINI -sw_error_t -hppe_fdb_tbl_rd_op_rslt_data0_data_set( - a_uint32_t dev_id, - a_uint32_t value) -{ - return SW_NOT_SUPPORTED; -} -#endif -sw_error_t -hppe_fdb_tbl_rd_op_rslt_data1_data_get( - a_uint32_t dev_id, - a_uint32_t *value) -{ - union fdb_tbl_rd_op_rslt_data1_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_fdb_tbl_rd_op_rslt_data1_get(dev_id, ®_val); - *value = reg_val.bf.data; - return ret; -} -#ifndef IN_FDB_MINI -sw_error_t -hppe_fdb_tbl_rd_op_rslt_data1_data_set( - a_uint32_t dev_id, - a_uint32_t value) -{ - return SW_NOT_SUPPORTED; -} -#endif -sw_error_t -hppe_fdb_tbl_rd_op_rslt_data2_data_get( - a_uint32_t dev_id, - a_uint32_t *value) -{ - union fdb_tbl_rd_op_rslt_data2_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_fdb_tbl_rd_op_rslt_data2_get(dev_id, ®_val); - *value = reg_val.bf.data; - return ret; -} -#ifndef IN_FDB_MINI -sw_error_t -hppe_fdb_tbl_rd_op_rslt_data2_data_set( - a_uint32_t dev_id, - a_uint32_t value) -{ - return SW_NOT_SUPPORTED; -} - -sw_error_t -hppe_fdb_tbl_op_data0_data_get( - a_uint32_t dev_id, - a_uint32_t *value) -{ - union fdb_tbl_op_data0_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_fdb_tbl_op_data0_get(dev_id, ®_val); - *value = reg_val.bf.data; - return ret; -} -#endif -sw_error_t -hppe_fdb_tbl_op_data0_data_set( - a_uint32_t dev_id, - a_uint32_t value) -{ - union fdb_tbl_op_data0_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_fdb_tbl_op_data0_get(dev_id, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.data = value; - ret = hppe_fdb_tbl_op_data0_set(dev_id, ®_val); - return ret; -} -#ifndef IN_FDB_MINI -sw_error_t -hppe_fdb_tbl_op_data1_data_get( - a_uint32_t dev_id, - a_uint32_t *value) -{ - union fdb_tbl_op_data1_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_fdb_tbl_op_data1_get(dev_id, ®_val); - *value = reg_val.bf.data; - return ret; -} -#endif -sw_error_t -hppe_fdb_tbl_op_data1_data_set( - a_uint32_t dev_id, - a_uint32_t value) -{ - union fdb_tbl_op_data1_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_fdb_tbl_op_data1_get(dev_id, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.data = value; - ret = hppe_fdb_tbl_op_data1_set(dev_id, ®_val); - return ret; -} -#ifndef IN_FDB_MINI -sw_error_t -hppe_fdb_tbl_op_data2_data_get( - a_uint32_t dev_id, - a_uint32_t *value) -{ - union fdb_tbl_op_data2_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_fdb_tbl_op_data2_get(dev_id, ®_val); - *value = reg_val.bf.data; - return ret; -} -#endif -sw_error_t -hppe_fdb_tbl_op_data2_data_set( - a_uint32_t dev_id, - a_uint32_t value) -{ - union fdb_tbl_op_data2_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_fdb_tbl_op_data2_get(dev_id, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.data = value; - ret = hppe_fdb_tbl_op_data2_set(dev_id, ®_val); - return ret; -} -#ifndef IN_FDB_MINI -sw_error_t -hppe_fdb_tbl_rd_op_data0_data_get( - a_uint32_t dev_id, - a_uint32_t *value) -{ - union fdb_tbl_rd_op_data0_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_fdb_tbl_rd_op_data0_get(dev_id, ®_val); - *value = reg_val.bf.data; - return ret; -} -#endif -sw_error_t -hppe_fdb_tbl_rd_op_data0_data_set( - a_uint32_t dev_id, - a_uint32_t value) -{ - union fdb_tbl_rd_op_data0_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_fdb_tbl_rd_op_data0_get(dev_id, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.data = value; - ret = hppe_fdb_tbl_rd_op_data0_set(dev_id, ®_val); - return ret; -} -#ifndef IN_FDB_MINI -sw_error_t -hppe_fdb_tbl_rd_op_data1_data_get( - a_uint32_t dev_id, - a_uint32_t *value) -{ - union fdb_tbl_rd_op_data1_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_fdb_tbl_rd_op_data1_get(dev_id, ®_val); - *value = reg_val.bf.data; - return ret; -} -#endif -sw_error_t -hppe_fdb_tbl_rd_op_data1_data_set( - a_uint32_t dev_id, - a_uint32_t value) -{ - union fdb_tbl_rd_op_data1_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_fdb_tbl_rd_op_data1_get(dev_id, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.data = value; - ret = hppe_fdb_tbl_rd_op_data1_set(dev_id, ®_val); - return ret; -} -#ifndef IN_FDB_MINI -sw_error_t -hppe_fdb_tbl_rd_op_data2_data_get( - a_uint32_t dev_id, - a_uint32_t *value) -{ - union fdb_tbl_rd_op_data2_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_fdb_tbl_rd_op_data2_get(dev_id, ®_val); - *value = reg_val.bf.data; - return ret; -} -#endif -sw_error_t -hppe_fdb_tbl_rd_op_data2_data_set( - a_uint32_t dev_id, - a_uint32_t value) -{ - union fdb_tbl_rd_op_data2_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_fdb_tbl_rd_op_data2_get(dev_id, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.data = value; - ret = hppe_fdb_tbl_rd_op_data2_set(dev_id, ®_val); - return ret; -} -#ifndef IN_FDB_MINI -sw_error_t -hppe_port_bridge_ctrl_txmac_en_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union port_bridge_ctrl_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_port_bridge_ctrl_get(dev_id, index, ®_val); - *value = reg_val.bf.txmac_en; - return ret; -} - -sw_error_t -hppe_port_bridge_ctrl_txmac_en_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - union port_bridge_ctrl_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_port_bridge_ctrl_get(dev_id, index, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.txmac_en = value; - ret = hppe_port_bridge_ctrl_set(dev_id, index, ®_val); - return ret; -} - -sw_error_t -hppe_port_bridge_ctrl_port_isolation_bitmap_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union port_bridge_ctrl_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_port_bridge_ctrl_get(dev_id, index, ®_val); - *value = reg_val.bf.port_isolation_bitmap; - return ret; -} - -sw_error_t -hppe_port_bridge_ctrl_port_isolation_bitmap_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - union port_bridge_ctrl_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_port_bridge_ctrl_get(dev_id, index, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.port_isolation_bitmap = value; - ret = hppe_port_bridge_ctrl_set(dev_id, index, ®_val); - return ret; -} - -sw_error_t -hppe_port_bridge_ctrl_station_move_lrn_en_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union port_bridge_ctrl_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_port_bridge_ctrl_get(dev_id, index, ®_val); - *value = reg_val.bf.station_move_lrn_en; - return ret; -} - -sw_error_t -hppe_port_bridge_ctrl_station_move_lrn_en_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - union port_bridge_ctrl_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_port_bridge_ctrl_get(dev_id, index, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.station_move_lrn_en = value; - ret = hppe_port_bridge_ctrl_set(dev_id, index, ®_val); - return ret; -} - -sw_error_t -hppe_port_bridge_ctrl_new_addr_fwd_cmd_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union port_bridge_ctrl_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_port_bridge_ctrl_get(dev_id, index, ®_val); - *value = reg_val.bf.new_addr_fwd_cmd; - return ret; -} - -sw_error_t -hppe_port_bridge_ctrl_new_addr_fwd_cmd_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - union port_bridge_ctrl_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_port_bridge_ctrl_get(dev_id, index, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.new_addr_fwd_cmd = value; - ret = hppe_port_bridge_ctrl_set(dev_id, index, ®_val); - return ret; -} - -sw_error_t -hppe_port_bridge_ctrl_promisc_en_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union port_bridge_ctrl_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_port_bridge_ctrl_get(dev_id, index, ®_val); - *value = reg_val.bf.promisc_en; - return ret; -} - -sw_error_t -hppe_port_bridge_ctrl_promisc_en_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - union port_bridge_ctrl_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_port_bridge_ctrl_get(dev_id, index, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.promisc_en = value; - ret = hppe_port_bridge_ctrl_set(dev_id, index, ®_val); - return ret; -} - -sw_error_t -hppe_port_bridge_ctrl_new_addr_lrn_en_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union port_bridge_ctrl_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_port_bridge_ctrl_get(dev_id, index, ®_val); - *value = reg_val.bf.new_addr_lrn_en; - return ret; -} - -sw_error_t -hppe_port_bridge_ctrl_new_addr_lrn_en_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - union port_bridge_ctrl_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_port_bridge_ctrl_get(dev_id, index, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.new_addr_lrn_en = value; - ret = hppe_port_bridge_ctrl_set(dev_id, index, ®_val); - return ret; -} - -sw_error_t -hppe_port_bridge_ctrl_station_move_fwd_cmd_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union port_bridge_ctrl_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_port_bridge_ctrl_get(dev_id, index, ®_val); - *value = reg_val.bf.station_move_fwd_cmd; - return ret; -} - -sw_error_t -hppe_port_bridge_ctrl_station_move_fwd_cmd_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - union port_bridge_ctrl_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_port_bridge_ctrl_get(dev_id, index, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.station_move_fwd_cmd = value; - ret = hppe_port_bridge_ctrl_set(dev_id, index, ®_val); - return ret; -} - -sw_error_t -hppe_port_lrn_limit_ctrl_lrn_lmt_en_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union port_lrn_limit_ctrl_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_port_lrn_limit_ctrl_get(dev_id, index, ®_val); - *value = reg_val.bf.lrn_lmt_en; - return ret; -} - -sw_error_t -hppe_port_lrn_limit_ctrl_lrn_lmt_en_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - union port_lrn_limit_ctrl_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_port_lrn_limit_ctrl_get(dev_id, index, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.lrn_lmt_en = value; - ret = hppe_port_lrn_limit_ctrl_set(dev_id, index, ®_val); - return ret; -} - -sw_error_t -hppe_port_lrn_limit_ctrl_lrn_lmt_cnt_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union port_lrn_limit_ctrl_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_port_lrn_limit_ctrl_get(dev_id, index, ®_val); - *value = reg_val.bf.lrn_lmt_cnt; - return ret; -} - -sw_error_t -hppe_port_lrn_limit_ctrl_lrn_lmt_cnt_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - union port_lrn_limit_ctrl_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_port_lrn_limit_ctrl_get(dev_id, index, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.lrn_lmt_cnt = value; - ret = hppe_port_lrn_limit_ctrl_set(dev_id, index, ®_val); - return ret; -} - -sw_error_t -hppe_port_lrn_limit_ctrl_lrn_lmt_exceed_fwd_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union port_lrn_limit_ctrl_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_port_lrn_limit_ctrl_get(dev_id, index, ®_val); - *value = reg_val.bf.lrn_lmt_exceed_fwd; - return ret; -} - -sw_error_t -hppe_port_lrn_limit_ctrl_lrn_lmt_exceed_fwd_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - union port_lrn_limit_ctrl_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_port_lrn_limit_ctrl_get(dev_id, index, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.lrn_lmt_exceed_fwd = value; - ret = hppe_port_lrn_limit_ctrl_set(dev_id, index, ®_val); - return ret; -} - -sw_error_t -hppe_port_lrn_limit_counter_lrn_cnt_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union port_lrn_limit_counter_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_port_lrn_limit_counter_get(dev_id, index, ®_val); - *value = reg_val.bf.lrn_cnt; - return ret; -} - -sw_error_t -hppe_port_lrn_limit_counter_lrn_cnt_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - return SW_NOT_SUPPORTED; -} -#endif -sw_error_t -hppe_rfdb_tbl_mac_addr_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint64_t *value) -{ - union rfdb_tbl_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_rfdb_tbl_get(dev_id, index, ®_val); - *value = (a_uint64_t)reg_val.bf.mac_addr_1 << 32 | \ - reg_val.bf.mac_addr_0; - return ret; -} - -sw_error_t -hppe_rfdb_tbl_mac_addr_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint64_t value) -{ - union rfdb_tbl_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_rfdb_tbl_get(dev_id, index, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.mac_addr_1 = value >> 32; - reg_val.bf.mac_addr_0 = value & (((a_uint64_t)1<<32)-1); - ret = hppe_rfdb_tbl_set(dev_id, index, ®_val); - return ret; -} -#ifndef IN_FDB_MINI -sw_error_t -hppe_rfdb_tbl_valid_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union rfdb_tbl_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_rfdb_tbl_get(dev_id, index, ®_val); - *value = reg_val.bf.valid; - return ret; -} -#endif -sw_error_t -hppe_rfdb_tbl_valid_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - union rfdb_tbl_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_rfdb_tbl_get(dev_id, index, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.valid = value; - ret = hppe_rfdb_tbl_set(dev_id, index, ®_val); - return ret; -} - diff --git a/feeds/ipq807x/qca-ssdk/src/src/hsl/hppe/hppe_flow.c b/feeds/ipq807x/qca-ssdk/src/src/hsl/hppe/hppe_flow.c deleted file mode 100755 index f2fabba02..000000000 --- a/feeds/ipq807x/qca-ssdk/src/src/hsl/hppe/hppe_flow.c +++ /dev/null @@ -1,5814 +0,0 @@ -/* - * Copyright (c) 2016-2017, The Linux Foundation. All rights reserved. - * Permission to use, copy, modify, and/or distribute this software for - * any purpose with or without fee is hereby granted, provided that the - * above copyright notice and this permission notice appear in all copies. - * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES - * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR - * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES - * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN - * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT - * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. - */ - - -/** - * @defgroup - * @{ - */ -#include "sw.h" -#include "hsl.h" -#include "hppe_reg_access.h" -#include "hppe_flow_reg.h" -#include "hppe_flow.h" -#include "hppe_ip_reg.h" -#include "hppe_ip.h" - -#ifndef IN_FLOW_MINI -static a_uint32_t flow_cmd_id = 0; -static a_uint32_t flow_host_cmd_id = 0; - -sw_error_t -hppe_in_flow_cnt_tbl_get( - a_uint32_t dev_id, - a_uint32_t index, - union in_flow_cnt_tbl_u *value) -{ - return hppe_reg_tbl_get( - dev_id, - INGRESS_POLICER_BASE_ADDR + IN_FLOW_CNT_TBL_ADDRESS + \ - index * IN_FLOW_CNT_TBL_INC, - value->val, - 3); -} - -sw_error_t -hppe_in_flow_cnt_tbl_set( - a_uint32_t dev_id, - a_uint32_t index, - union in_flow_cnt_tbl_u *value) -{ - return hppe_reg_tbl_set( - dev_id, - INGRESS_POLICER_BASE_ADDR + IN_FLOW_CNT_TBL_ADDRESS + \ - index * IN_FLOW_CNT_TBL_INC, - value->val, - 3); -} - -sw_error_t -hppe_flow_ctrl0_get( - a_uint32_t dev_id, - union flow_ctrl0_u *value) -{ - return hppe_reg_get( - dev_id, - IPE_L3_BASE_ADDR + FLOW_CTRL0_ADDRESS, - &value->val); -} - -sw_error_t -hppe_flow_ctrl0_set( - a_uint32_t dev_id, - union flow_ctrl0_u *value) -{ - return hppe_reg_set( - dev_id, - IPE_L3_BASE_ADDR + FLOW_CTRL0_ADDRESS, - value->val); -} -#endif - -sw_error_t -hppe_flow_ctrl1_get( - a_uint32_t dev_id, - a_uint32_t index, - union flow_ctrl1_u *value) -{ - if (index >= FLOW_CTRL1_MAX_ENTRY) - return SW_OUT_OF_RANGE; - return hppe_reg_get( - dev_id, - IPE_L3_BASE_ADDR + FLOW_CTRL1_ADDRESS + \ - index * FLOW_CTRL1_INC, - &value->val); -} - -sw_error_t -hppe_flow_ctrl1_set( - a_uint32_t dev_id, - a_uint32_t index, - union flow_ctrl1_u *value) -{ - return hppe_reg_set( - dev_id, - IPE_L3_BASE_ADDR + FLOW_CTRL1_ADDRESS + \ - index * FLOW_CTRL1_INC, - value->val); -} - -#ifndef IN_FLOW_MINI -sw_error_t -hppe_in_flow_tbl_op_get( - a_uint32_t dev_id, - union in_flow_tbl_op_u *value) -{ - return hppe_reg_get( - dev_id, - IPE_L3_BASE_ADDR + IN_FLOW_TBL_OP_ADDRESS, - &value->val); -} - -sw_error_t -hppe_in_flow_tbl_op_set( - a_uint32_t dev_id, - union in_flow_tbl_op_u *value) -{ - return hppe_reg_set( - dev_id, - IPE_L3_BASE_ADDR + IN_FLOW_TBL_OP_ADDRESS, - value->val); -} - -sw_error_t -hppe_in_flow_host_tbl_op_get( - a_uint32_t dev_id, - union in_flow_host_tbl_op_u *value) -{ - return hppe_reg_get( - dev_id, - IPE_L3_BASE_ADDR + IN_FLOW_HOST_TBL_OP_ADDRESS, - &value->val); -} - -sw_error_t -hppe_in_flow_host_tbl_op_set( - a_uint32_t dev_id, - union in_flow_host_tbl_op_u *value) -{ - return hppe_reg_set( - dev_id, - IPE_L3_BASE_ADDR + IN_FLOW_HOST_TBL_OP_ADDRESS, - value->val); -} - -sw_error_t -hppe_in_flow_tbl_op_data0_get( - a_uint32_t dev_id, - union in_flow_tbl_op_data0_u *value) -{ - return hppe_reg_get( - dev_id, - IPE_L3_BASE_ADDR + IN_FLOW_TBL_OP_DATA0_ADDRESS, - &value->val); -} - -sw_error_t -hppe_in_flow_tbl_op_data0_set( - a_uint32_t dev_id, - union in_flow_tbl_op_data0_u *value) -{ - return hppe_reg_set( - dev_id, - IPE_L3_BASE_ADDR + IN_FLOW_TBL_OP_DATA0_ADDRESS, - value->val); -} - -sw_error_t -hppe_in_flow_tbl_op_data1_get( - a_uint32_t dev_id, - union in_flow_tbl_op_data1_u *value) -{ - return hppe_reg_get( - dev_id, - IPE_L3_BASE_ADDR + IN_FLOW_TBL_OP_DATA1_ADDRESS, - &value->val); -} - -sw_error_t -hppe_in_flow_tbl_op_data1_set( - a_uint32_t dev_id, - union in_flow_tbl_op_data1_u *value) -{ - return hppe_reg_set( - dev_id, - IPE_L3_BASE_ADDR + IN_FLOW_TBL_OP_DATA1_ADDRESS, - value->val); -} - -sw_error_t -hppe_in_flow_tbl_op_data2_get( - a_uint32_t dev_id, - union in_flow_tbl_op_data2_u *value) -{ - return hppe_reg_get( - dev_id, - IPE_L3_BASE_ADDR + IN_FLOW_TBL_OP_DATA2_ADDRESS, - &value->val); -} - -sw_error_t -hppe_in_flow_tbl_op_data2_set( - a_uint32_t dev_id, - union in_flow_tbl_op_data2_u *value) -{ - return hppe_reg_set( - dev_id, - IPE_L3_BASE_ADDR + IN_FLOW_TBL_OP_DATA2_ADDRESS, - value->val); -} - -sw_error_t -hppe_in_flow_tbl_op_data3_get( - a_uint32_t dev_id, - union in_flow_tbl_op_data3_u *value) -{ - return hppe_reg_get( - dev_id, - IPE_L3_BASE_ADDR + IN_FLOW_TBL_OP_DATA3_ADDRESS, - &value->val); -} - -sw_error_t -hppe_in_flow_tbl_op_data3_set( - a_uint32_t dev_id, - union in_flow_tbl_op_data3_u *value) -{ - return hppe_reg_set( - dev_id, - IPE_L3_BASE_ADDR + IN_FLOW_TBL_OP_DATA3_ADDRESS, - value->val); -} - -sw_error_t -hppe_in_flow_tbl_op_data4_get( - a_uint32_t dev_id, - union in_flow_tbl_op_data4_u *value) -{ - return hppe_reg_get( - dev_id, - IPE_L3_BASE_ADDR + IN_FLOW_TBL_OP_DATA4_ADDRESS, - &value->val); -} - -sw_error_t -hppe_in_flow_tbl_op_data4_set( - a_uint32_t dev_id, - union in_flow_tbl_op_data4_u *value) -{ - return hppe_reg_set( - dev_id, - IPE_L3_BASE_ADDR + IN_FLOW_TBL_OP_DATA4_ADDRESS, - value->val); -} - -sw_error_t -hppe_in_flow_tbl_op_data5_get( - a_uint32_t dev_id, - union in_flow_tbl_op_data5_u *value) -{ - return hppe_reg_get( - dev_id, - IPE_L3_BASE_ADDR + IN_FLOW_TBL_OP_DATA5_ADDRESS, - &value->val); -} - -sw_error_t -hppe_in_flow_tbl_op_data5_set( - a_uint32_t dev_id, - union in_flow_tbl_op_data5_u *value) -{ - return hppe_reg_set( - dev_id, - IPE_L3_BASE_ADDR + IN_FLOW_TBL_OP_DATA5_ADDRESS, - value->val); -} - -sw_error_t -hppe_in_flow_tbl_op_data6_get( - a_uint32_t dev_id, - union in_flow_tbl_op_data6_u *value) -{ - return hppe_reg_get( - dev_id, - IPE_L3_BASE_ADDR + IN_FLOW_TBL_OP_DATA6_ADDRESS, - &value->val); -} - -sw_error_t -hppe_in_flow_tbl_op_data6_set( - a_uint32_t dev_id, - union in_flow_tbl_op_data6_u *value) -{ - return hppe_reg_set( - dev_id, - IPE_L3_BASE_ADDR + IN_FLOW_TBL_OP_DATA6_ADDRESS, - value->val); -} - -sw_error_t -hppe_in_flow_tbl_op_data7_get( - a_uint32_t dev_id, - union in_flow_tbl_op_data7_u *value) -{ - return hppe_reg_get( - dev_id, - IPE_L3_BASE_ADDR + IN_FLOW_TBL_OP_DATA7_ADDRESS, - &value->val); -} - -sw_error_t -hppe_in_flow_tbl_op_data7_set( - a_uint32_t dev_id, - union in_flow_tbl_op_data7_u *value) -{ - return hppe_reg_set( - dev_id, - IPE_L3_BASE_ADDR + IN_FLOW_TBL_OP_DATA7_ADDRESS, - value->val); -} - -sw_error_t -hppe_in_flow_tbl_op_data8_get( - a_uint32_t dev_id, - union in_flow_tbl_op_data8_u *value) -{ - return hppe_reg_get( - dev_id, - IPE_L3_BASE_ADDR + IN_FLOW_TBL_OP_DATA8_ADDRESS, - &value->val); -} - -sw_error_t -hppe_in_flow_tbl_op_data8_set( - a_uint32_t dev_id, - union in_flow_tbl_op_data8_u *value) -{ - return hppe_reg_set( - dev_id, - IPE_L3_BASE_ADDR + IN_FLOW_TBL_OP_DATA8_ADDRESS, - value->val); -} - -sw_error_t -hppe_flow_host_tbl_op_data0_get( - a_uint32_t dev_id, - union flow_host_tbl_op_data0_u *value) -{ - return hppe_reg_get( - dev_id, - IPE_L3_BASE_ADDR + FLOW_HOST_TBL_OP_DATA0_ADDRESS, - &value->val); -} - -sw_error_t -hppe_flow_host_tbl_op_data0_set( - a_uint32_t dev_id, - union flow_host_tbl_op_data0_u *value) -{ - return hppe_reg_set( - dev_id, - IPE_L3_BASE_ADDR + FLOW_HOST_TBL_OP_DATA0_ADDRESS, - value->val); -} - -sw_error_t -hppe_flow_host_tbl_op_data1_get( - a_uint32_t dev_id, - union flow_host_tbl_op_data1_u *value) -{ - return hppe_reg_get( - dev_id, - IPE_L3_BASE_ADDR + FLOW_HOST_TBL_OP_DATA1_ADDRESS, - &value->val); -} - -sw_error_t -hppe_flow_host_tbl_op_data1_set( - a_uint32_t dev_id, - union flow_host_tbl_op_data1_u *value) -{ - return hppe_reg_set( - dev_id, - IPE_L3_BASE_ADDR + FLOW_HOST_TBL_OP_DATA1_ADDRESS, - value->val); -} - -sw_error_t -hppe_flow_host_tbl_op_data2_get( - a_uint32_t dev_id, - union flow_host_tbl_op_data2_u *value) -{ - return hppe_reg_get( - dev_id, - IPE_L3_BASE_ADDR + FLOW_HOST_TBL_OP_DATA2_ADDRESS, - &value->val); -} - -sw_error_t -hppe_flow_host_tbl_op_data2_set( - a_uint32_t dev_id, - union flow_host_tbl_op_data2_u *value) -{ - return hppe_reg_set( - dev_id, - IPE_L3_BASE_ADDR + FLOW_HOST_TBL_OP_DATA2_ADDRESS, - value->val); -} - -sw_error_t -hppe_flow_host_tbl_op_data3_get( - a_uint32_t dev_id, - union flow_host_tbl_op_data3_u *value) -{ - return hppe_reg_get( - dev_id, - IPE_L3_BASE_ADDR + FLOW_HOST_TBL_OP_DATA3_ADDRESS, - &value->val); -} - -sw_error_t -hppe_flow_host_tbl_op_data3_set( - a_uint32_t dev_id, - union flow_host_tbl_op_data3_u *value) -{ - return hppe_reg_set( - dev_id, - IPE_L3_BASE_ADDR + FLOW_HOST_TBL_OP_DATA3_ADDRESS, - value->val); -} - -sw_error_t -hppe_flow_host_tbl_op_data4_get( - a_uint32_t dev_id, - union flow_host_tbl_op_data4_u *value) -{ - return hppe_reg_get( - dev_id, - IPE_L3_BASE_ADDR + FLOW_HOST_TBL_OP_DATA4_ADDRESS, - &value->val); -} - -sw_error_t -hppe_flow_host_tbl_op_data4_set( - a_uint32_t dev_id, - union flow_host_tbl_op_data4_u *value) -{ - return hppe_reg_set( - dev_id, - IPE_L3_BASE_ADDR + FLOW_HOST_TBL_OP_DATA4_ADDRESS, - value->val); -} - -sw_error_t -hppe_flow_host_tbl_op_data5_get( - a_uint32_t dev_id, - union flow_host_tbl_op_data5_u *value) -{ - return hppe_reg_get( - dev_id, - IPE_L3_BASE_ADDR + FLOW_HOST_TBL_OP_DATA5_ADDRESS, - &value->val); -} - -sw_error_t -hppe_flow_host_tbl_op_data5_set( - a_uint32_t dev_id, - union flow_host_tbl_op_data5_u *value) -{ - return hppe_reg_set( - dev_id, - IPE_L3_BASE_ADDR + FLOW_HOST_TBL_OP_DATA5_ADDRESS, - value->val); -} - -sw_error_t -hppe_flow_host_tbl_op_data6_get( - a_uint32_t dev_id, - union flow_host_tbl_op_data6_u *value) -{ - return hppe_reg_get( - dev_id, - IPE_L3_BASE_ADDR + FLOW_HOST_TBL_OP_DATA6_ADDRESS, - &value->val); -} - -sw_error_t -hppe_flow_host_tbl_op_data6_set( - a_uint32_t dev_id, - union flow_host_tbl_op_data6_u *value) -{ - return hppe_reg_set( - dev_id, - IPE_L3_BASE_ADDR + FLOW_HOST_TBL_OP_DATA6_ADDRESS, - value->val); -} - -sw_error_t -hppe_flow_host_tbl_op_data7_get( - a_uint32_t dev_id, - union flow_host_tbl_op_data7_u *value) -{ - return hppe_reg_get( - dev_id, - IPE_L3_BASE_ADDR + FLOW_HOST_TBL_OP_DATA7_ADDRESS, - &value->val); -} - -sw_error_t -hppe_flow_host_tbl_op_data7_set( - a_uint32_t dev_id, - union flow_host_tbl_op_data7_u *value) -{ - return hppe_reg_set( - dev_id, - IPE_L3_BASE_ADDR + FLOW_HOST_TBL_OP_DATA7_ADDRESS, - value->val); -} - -sw_error_t -hppe_flow_host_tbl_op_data8_get( - a_uint32_t dev_id, - union flow_host_tbl_op_data8_u *value) -{ - return hppe_reg_get( - dev_id, - IPE_L3_BASE_ADDR + FLOW_HOST_TBL_OP_DATA8_ADDRESS, - &value->val); -} - -sw_error_t -hppe_flow_host_tbl_op_data8_set( - a_uint32_t dev_id, - union flow_host_tbl_op_data8_u *value) -{ - return hppe_reg_set( - dev_id, - IPE_L3_BASE_ADDR + FLOW_HOST_TBL_OP_DATA8_ADDRESS, - value->val); -} - -sw_error_t -hppe_flow_host_tbl_op_data9_get( - a_uint32_t dev_id, - union flow_host_tbl_op_data9_u *value) -{ - return hppe_reg_get( - dev_id, - IPE_L3_BASE_ADDR + FLOW_HOST_TBL_OP_DATA9_ADDRESS, - &value->val); -} - -sw_error_t -hppe_flow_host_tbl_op_data9_set( - a_uint32_t dev_id, - union flow_host_tbl_op_data9_u *value) -{ - return hppe_reg_set( - dev_id, - IPE_L3_BASE_ADDR + FLOW_HOST_TBL_OP_DATA9_ADDRESS, - value->val); -} - -sw_error_t -hppe_in_flow_tbl_op_rslt_get( - a_uint32_t dev_id, - union in_flow_tbl_op_rslt_u *value) -{ - return hppe_reg_get( - dev_id, - IPE_L3_BASE_ADDR + IN_FLOW_TBL_OP_RSLT_ADDRESS, - &value->val); -} - -sw_error_t -hppe_in_flow_tbl_op_rslt_set( - a_uint32_t dev_id, - union in_flow_tbl_op_rslt_u *value) -{ - return SW_NOT_SUPPORTED; -} - -sw_error_t -hppe_flow_host_tbl_op_rslt_get( - a_uint32_t dev_id, - union flow_host_tbl_op_rslt_u *value) -{ - return hppe_reg_get( - dev_id, - IPE_L3_BASE_ADDR + FLOW_HOST_TBL_OP_RSLT_ADDRESS, - &value->val); -} - -sw_error_t -hppe_flow_host_tbl_op_rslt_set( - a_uint32_t dev_id, - union flow_host_tbl_op_rslt_u *value) -{ - return SW_NOT_SUPPORTED; -} - -sw_error_t -hppe_in_flow_tbl_rd_op_get( - a_uint32_t dev_id, - union in_flow_tbl_rd_op_u *value) -{ - return hppe_reg_get( - dev_id, - IPE_L3_BASE_ADDR + IN_FLOW_TBL_RD_OP_ADDRESS, - &value->val); -} - -sw_error_t -hppe_in_flow_tbl_rd_op_set( - a_uint32_t dev_id, - union in_flow_tbl_rd_op_u *value) -{ - return hppe_reg_set( - dev_id, - IPE_L3_BASE_ADDR + IN_FLOW_TBL_RD_OP_ADDRESS, - value->val); -} - -sw_error_t -hppe_in_flow_host_tbl_rd_op_get( - a_uint32_t dev_id, - union in_flow_host_tbl_rd_op_u *value) -{ - return hppe_reg_get( - dev_id, - IPE_L3_BASE_ADDR + IN_FLOW_HOST_TBL_RD_OP_ADDRESS, - &value->val); -} - -sw_error_t -hppe_in_flow_host_tbl_rd_op_set( - a_uint32_t dev_id, - union in_flow_host_tbl_rd_op_u *value) -{ - return hppe_reg_set( - dev_id, - IPE_L3_BASE_ADDR + IN_FLOW_HOST_TBL_RD_OP_ADDRESS, - value->val); -} - -sw_error_t -hppe_in_flow_tbl_rd_op_data0_get( - a_uint32_t dev_id, - union in_flow_tbl_rd_op_data0_u *value) -{ - return hppe_reg_get( - dev_id, - IPE_L3_BASE_ADDR + IN_FLOW_TBL_RD_OP_DATA0_ADDRESS, - &value->val); -} - -sw_error_t -hppe_in_flow_tbl_rd_op_data0_set( - a_uint32_t dev_id, - union in_flow_tbl_rd_op_data0_u *value) -{ - return hppe_reg_set( - dev_id, - IPE_L3_BASE_ADDR + IN_FLOW_TBL_RD_OP_DATA0_ADDRESS, - value->val); -} - -sw_error_t -hppe_in_flow_tbl_rd_op_data1_get( - a_uint32_t dev_id, - union in_flow_tbl_rd_op_data1_u *value) -{ - return hppe_reg_get( - dev_id, - IPE_L3_BASE_ADDR + IN_FLOW_TBL_RD_OP_DATA1_ADDRESS, - &value->val); -} - -sw_error_t -hppe_in_flow_tbl_rd_op_data1_set( - a_uint32_t dev_id, - union in_flow_tbl_rd_op_data1_u *value) -{ - return hppe_reg_set( - dev_id, - IPE_L3_BASE_ADDR + IN_FLOW_TBL_RD_OP_DATA1_ADDRESS, - value->val); -} - -sw_error_t -hppe_in_flow_tbl_rd_op_data2_get( - a_uint32_t dev_id, - union in_flow_tbl_rd_op_data2_u *value) -{ - return hppe_reg_get( - dev_id, - IPE_L3_BASE_ADDR + IN_FLOW_TBL_RD_OP_DATA2_ADDRESS, - &value->val); -} - -sw_error_t -hppe_in_flow_tbl_rd_op_data2_set( - a_uint32_t dev_id, - union in_flow_tbl_rd_op_data2_u *value) -{ - return hppe_reg_set( - dev_id, - IPE_L3_BASE_ADDR + IN_FLOW_TBL_RD_OP_DATA2_ADDRESS, - value->val); -} - -sw_error_t -hppe_in_flow_tbl_rd_op_data3_get( - a_uint32_t dev_id, - union in_flow_tbl_rd_op_data3_u *value) -{ - return hppe_reg_get( - dev_id, - IPE_L3_BASE_ADDR + IN_FLOW_TBL_RD_OP_DATA3_ADDRESS, - &value->val); -} - -sw_error_t -hppe_in_flow_tbl_rd_op_data3_set( - a_uint32_t dev_id, - union in_flow_tbl_rd_op_data3_u *value) -{ - return hppe_reg_set( - dev_id, - IPE_L3_BASE_ADDR + IN_FLOW_TBL_RD_OP_DATA3_ADDRESS, - value->val); -} - -sw_error_t -hppe_in_flow_tbl_rd_op_data4_get( - a_uint32_t dev_id, - union in_flow_tbl_rd_op_data4_u *value) -{ - return hppe_reg_get( - dev_id, - IPE_L3_BASE_ADDR + IN_FLOW_TBL_RD_OP_DATA4_ADDRESS, - &value->val); -} - -sw_error_t -hppe_in_flow_tbl_rd_op_data4_set( - a_uint32_t dev_id, - union in_flow_tbl_rd_op_data4_u *value) -{ - return hppe_reg_set( - dev_id, - IPE_L3_BASE_ADDR + IN_FLOW_TBL_RD_OP_DATA4_ADDRESS, - value->val); -} - -sw_error_t -hppe_in_flow_tbl_rd_op_data5_get( - a_uint32_t dev_id, - union in_flow_tbl_rd_op_data5_u *value) -{ - return hppe_reg_get( - dev_id, - IPE_L3_BASE_ADDR + IN_FLOW_TBL_RD_OP_DATA5_ADDRESS, - &value->val); -} - -sw_error_t -hppe_in_flow_tbl_rd_op_data5_set( - a_uint32_t dev_id, - union in_flow_tbl_rd_op_data5_u *value) -{ - return hppe_reg_set( - dev_id, - IPE_L3_BASE_ADDR + IN_FLOW_TBL_RD_OP_DATA5_ADDRESS, - value->val); -} - -sw_error_t -hppe_in_flow_tbl_rd_op_data6_get( - a_uint32_t dev_id, - union in_flow_tbl_rd_op_data6_u *value) -{ - return hppe_reg_get( - dev_id, - IPE_L3_BASE_ADDR + IN_FLOW_TBL_RD_OP_DATA6_ADDRESS, - &value->val); -} - -sw_error_t -hppe_in_flow_tbl_rd_op_data6_set( - a_uint32_t dev_id, - union in_flow_tbl_rd_op_data6_u *value) -{ - return hppe_reg_set( - dev_id, - IPE_L3_BASE_ADDR + IN_FLOW_TBL_RD_OP_DATA6_ADDRESS, - value->val); -} - -sw_error_t -hppe_in_flow_tbl_rd_op_data7_get( - a_uint32_t dev_id, - union in_flow_tbl_rd_op_data7_u *value) -{ - return hppe_reg_get( - dev_id, - IPE_L3_BASE_ADDR + IN_FLOW_TBL_RD_OP_DATA7_ADDRESS, - &value->val); -} - -sw_error_t -hppe_in_flow_tbl_rd_op_data7_set( - a_uint32_t dev_id, - union in_flow_tbl_rd_op_data7_u *value) -{ - return hppe_reg_set( - dev_id, - IPE_L3_BASE_ADDR + IN_FLOW_TBL_RD_OP_DATA7_ADDRESS, - value->val); -} - -sw_error_t -hppe_in_flow_tbl_rd_op_data8_get( - a_uint32_t dev_id, - union in_flow_tbl_rd_op_data8_u *value) -{ - return hppe_reg_get( - dev_id, - IPE_L3_BASE_ADDR + IN_FLOW_TBL_RD_OP_DATA8_ADDRESS, - &value->val); -} - -sw_error_t -hppe_in_flow_tbl_rd_op_data8_set( - a_uint32_t dev_id, - union in_flow_tbl_rd_op_data8_u *value) -{ - return hppe_reg_set( - dev_id, - IPE_L3_BASE_ADDR + IN_FLOW_TBL_RD_OP_DATA8_ADDRESS, - value->val); -} - -sw_error_t -hppe_flow_host_tbl_rd_op_data0_get( - a_uint32_t dev_id, - union flow_host_tbl_rd_op_data0_u *value) -{ - return hppe_reg_get( - dev_id, - IPE_L3_BASE_ADDR + FLOW_HOST_TBL_RD_OP_DATA0_ADDRESS, - &value->val); -} - -sw_error_t -hppe_flow_host_tbl_rd_op_data0_set( - a_uint32_t dev_id, - union flow_host_tbl_rd_op_data0_u *value) -{ - return hppe_reg_set( - dev_id, - IPE_L3_BASE_ADDR + FLOW_HOST_TBL_RD_OP_DATA0_ADDRESS, - value->val); -} - -sw_error_t -hppe_flow_host_tbl_rd_op_data1_get( - a_uint32_t dev_id, - union flow_host_tbl_rd_op_data1_u *value) -{ - return hppe_reg_get( - dev_id, - IPE_L3_BASE_ADDR + FLOW_HOST_TBL_RD_OP_DATA1_ADDRESS, - &value->val); -} - -sw_error_t -hppe_flow_host_tbl_rd_op_data1_set( - a_uint32_t dev_id, - union flow_host_tbl_rd_op_data1_u *value) -{ - return hppe_reg_set( - dev_id, - IPE_L3_BASE_ADDR + FLOW_HOST_TBL_RD_OP_DATA1_ADDRESS, - value->val); -} - -sw_error_t -hppe_flow_host_tbl_rd_op_data2_get( - a_uint32_t dev_id, - union flow_host_tbl_rd_op_data2_u *value) -{ - return hppe_reg_get( - dev_id, - IPE_L3_BASE_ADDR + FLOW_HOST_TBL_RD_OP_DATA2_ADDRESS, - &value->val); -} - -sw_error_t -hppe_flow_host_tbl_rd_op_data2_set( - a_uint32_t dev_id, - union flow_host_tbl_rd_op_data2_u *value) -{ - return hppe_reg_set( - dev_id, - IPE_L3_BASE_ADDR + FLOW_HOST_TBL_RD_OP_DATA2_ADDRESS, - value->val); -} - -sw_error_t -hppe_flow_host_tbl_rd_op_data3_get( - a_uint32_t dev_id, - union flow_host_tbl_rd_op_data3_u *value) -{ - return hppe_reg_get( - dev_id, - IPE_L3_BASE_ADDR + FLOW_HOST_TBL_RD_OP_DATA3_ADDRESS, - &value->val); -} - -sw_error_t -hppe_flow_host_tbl_rd_op_data3_set( - a_uint32_t dev_id, - union flow_host_tbl_rd_op_data3_u *value) -{ - return hppe_reg_set( - dev_id, - IPE_L3_BASE_ADDR + FLOW_HOST_TBL_RD_OP_DATA3_ADDRESS, - value->val); -} - -sw_error_t -hppe_flow_host_tbl_rd_op_data4_get( - a_uint32_t dev_id, - union flow_host_tbl_rd_op_data4_u *value) -{ - return hppe_reg_get( - dev_id, - IPE_L3_BASE_ADDR + FLOW_HOST_TBL_RD_OP_DATA4_ADDRESS, - &value->val); -} - -sw_error_t -hppe_flow_host_tbl_rd_op_data4_set( - a_uint32_t dev_id, - union flow_host_tbl_rd_op_data4_u *value) -{ - return hppe_reg_set( - dev_id, - IPE_L3_BASE_ADDR + FLOW_HOST_TBL_RD_OP_DATA4_ADDRESS, - value->val); -} - -sw_error_t -hppe_flow_host_tbl_rd_op_data5_get( - a_uint32_t dev_id, - union flow_host_tbl_rd_op_data5_u *value) -{ - return hppe_reg_get( - dev_id, - IPE_L3_BASE_ADDR + FLOW_HOST_TBL_RD_OP_DATA5_ADDRESS, - &value->val); -} - -sw_error_t -hppe_flow_host_tbl_rd_op_data5_set( - a_uint32_t dev_id, - union flow_host_tbl_rd_op_data5_u *value) -{ - return hppe_reg_set( - dev_id, - IPE_L3_BASE_ADDR + FLOW_HOST_TBL_RD_OP_DATA5_ADDRESS, - value->val); -} - -sw_error_t -hppe_flow_host_tbl_rd_op_data6_get( - a_uint32_t dev_id, - union flow_host_tbl_rd_op_data6_u *value) -{ - return hppe_reg_get( - dev_id, - IPE_L3_BASE_ADDR + FLOW_HOST_TBL_RD_OP_DATA6_ADDRESS, - &value->val); -} - -sw_error_t -hppe_flow_host_tbl_rd_op_data6_set( - a_uint32_t dev_id, - union flow_host_tbl_rd_op_data6_u *value) -{ - return hppe_reg_set( - dev_id, - IPE_L3_BASE_ADDR + FLOW_HOST_TBL_RD_OP_DATA6_ADDRESS, - value->val); -} - -sw_error_t -hppe_flow_host_tbl_rd_op_data7_get( - a_uint32_t dev_id, - union flow_host_tbl_rd_op_data7_u *value) -{ - return hppe_reg_get( - dev_id, - IPE_L3_BASE_ADDR + FLOW_HOST_TBL_RD_OP_DATA7_ADDRESS, - &value->val); -} - -sw_error_t -hppe_flow_host_tbl_rd_op_data7_set( - a_uint32_t dev_id, - union flow_host_tbl_rd_op_data7_u *value) -{ - return hppe_reg_set( - dev_id, - IPE_L3_BASE_ADDR + FLOW_HOST_TBL_RD_OP_DATA7_ADDRESS, - value->val); -} - -sw_error_t -hppe_flow_host_tbl_rd_op_data8_get( - a_uint32_t dev_id, - union flow_host_tbl_rd_op_data8_u *value) -{ - return hppe_reg_get( - dev_id, - IPE_L3_BASE_ADDR + FLOW_HOST_TBL_RD_OP_DATA8_ADDRESS, - &value->val); -} - -sw_error_t -hppe_flow_host_tbl_rd_op_data8_set( - a_uint32_t dev_id, - union flow_host_tbl_rd_op_data8_u *value) -{ - return hppe_reg_set( - dev_id, - IPE_L3_BASE_ADDR + FLOW_HOST_TBL_RD_OP_DATA8_ADDRESS, - value->val); -} - -sw_error_t -hppe_flow_host_tbl_rd_op_data9_get( - a_uint32_t dev_id, - union flow_host_tbl_rd_op_data9_u *value) -{ - return hppe_reg_get( - dev_id, - IPE_L3_BASE_ADDR + FLOW_HOST_TBL_RD_OP_DATA9_ADDRESS, - &value->val); -} - -sw_error_t -hppe_flow_host_tbl_rd_op_data9_set( - a_uint32_t dev_id, - union flow_host_tbl_rd_op_data9_u *value) -{ - return hppe_reg_set( - dev_id, - IPE_L3_BASE_ADDR + FLOW_HOST_TBL_RD_OP_DATA9_ADDRESS, - value->val); -} - -sw_error_t -hppe_in_flow_tbl_rd_op_rslt_get( - a_uint32_t dev_id, - union in_flow_tbl_rd_op_rslt_u *value) -{ - return hppe_reg_get( - dev_id, - IPE_L3_BASE_ADDR + IN_FLOW_TBL_RD_OP_RSLT_ADDRESS, - &value->val); -} - -sw_error_t -hppe_in_flow_tbl_rd_op_rslt_set( - a_uint32_t dev_id, - union in_flow_tbl_rd_op_rslt_u *value) -{ - return SW_NOT_SUPPORTED; -} - -sw_error_t -hppe_flow_host_tbl_rd_op_rslt_get( - a_uint32_t dev_id, - union flow_host_tbl_rd_op_rslt_u *value) -{ - return hppe_reg_get( - dev_id, - IPE_L3_BASE_ADDR + FLOW_HOST_TBL_RD_OP_RSLT_ADDRESS, - &value->val); -} - -sw_error_t -hppe_flow_host_tbl_rd_op_rslt_set( - a_uint32_t dev_id, - union flow_host_tbl_rd_op_rslt_u *value) -{ - return SW_NOT_SUPPORTED; -} - -sw_error_t -hppe_in_flow_tbl_rd_rslt_data0_get( - a_uint32_t dev_id, - union in_flow_tbl_rd_rslt_data0_u *value) -{ - return hppe_reg_get( - dev_id, - IPE_L3_BASE_ADDR + IN_FLOW_TBL_RD_RSLT_DATA0_ADDRESS, - &value->val); -} - -sw_error_t -hppe_in_flow_tbl_rd_rslt_data0_set( - a_uint32_t dev_id, - union in_flow_tbl_rd_rslt_data0_u *value) -{ - return SW_NOT_SUPPORTED; -} - -sw_error_t -hppe_in_flow_tbl_rd_rslt_data1_get( - a_uint32_t dev_id, - union in_flow_tbl_rd_rslt_data1_u *value) -{ - return hppe_reg_get( - dev_id, - IPE_L3_BASE_ADDR + IN_FLOW_TBL_RD_RSLT_DATA1_ADDRESS, - &value->val); -} - -sw_error_t -hppe_in_flow_tbl_rd_rslt_data1_set( - a_uint32_t dev_id, - union in_flow_tbl_rd_rslt_data1_u *value) -{ - return SW_NOT_SUPPORTED; -} - -sw_error_t -hppe_in_flow_tbl_rd_rslt_data2_get( - a_uint32_t dev_id, - union in_flow_tbl_rd_rslt_data2_u *value) -{ - return hppe_reg_get( - dev_id, - IPE_L3_BASE_ADDR + IN_FLOW_TBL_RD_RSLT_DATA2_ADDRESS, - &value->val); -} - -sw_error_t -hppe_in_flow_tbl_rd_rslt_data2_set( - a_uint32_t dev_id, - union in_flow_tbl_rd_rslt_data2_u *value) -{ - return SW_NOT_SUPPORTED; -} - -sw_error_t -hppe_in_flow_tbl_rd_rslt_data3_get( - a_uint32_t dev_id, - union in_flow_tbl_rd_rslt_data3_u *value) -{ - return hppe_reg_get( - dev_id, - IPE_L3_BASE_ADDR + IN_FLOW_TBL_RD_RSLT_DATA3_ADDRESS, - &value->val); -} - -sw_error_t -hppe_in_flow_tbl_rd_rslt_data3_set( - a_uint32_t dev_id, - union in_flow_tbl_rd_rslt_data3_u *value) -{ - return SW_NOT_SUPPORTED; -} - -sw_error_t -hppe_in_flow_tbl_rd_rslt_data4_get( - a_uint32_t dev_id, - union in_flow_tbl_rd_rslt_data4_u *value) -{ - return hppe_reg_get( - dev_id, - IPE_L3_BASE_ADDR + IN_FLOW_TBL_RD_RSLT_DATA4_ADDRESS, - &value->val); -} - -sw_error_t -hppe_in_flow_tbl_rd_rslt_data4_set( - a_uint32_t dev_id, - union in_flow_tbl_rd_rslt_data4_u *value) -{ - return SW_NOT_SUPPORTED; -} - -sw_error_t -hppe_in_flow_tbl_rd_rslt_data5_get( - a_uint32_t dev_id, - union in_flow_tbl_rd_rslt_data5_u *value) -{ - return hppe_reg_get( - dev_id, - IPE_L3_BASE_ADDR + IN_FLOW_TBL_RD_RSLT_DATA5_ADDRESS, - &value->val); -} - -sw_error_t -hppe_in_flow_tbl_rd_rslt_data5_set( - a_uint32_t dev_id, - union in_flow_tbl_rd_rslt_data5_u *value) -{ - return SW_NOT_SUPPORTED; -} - -sw_error_t -hppe_in_flow_tbl_rd_rslt_data6_get( - a_uint32_t dev_id, - union in_flow_tbl_rd_rslt_data6_u *value) -{ - return hppe_reg_get( - dev_id, - IPE_L3_BASE_ADDR + IN_FLOW_TBL_RD_RSLT_DATA6_ADDRESS, - &value->val); -} - -sw_error_t -hppe_in_flow_tbl_rd_rslt_data6_set( - a_uint32_t dev_id, - union in_flow_tbl_rd_rslt_data6_u *value) -{ - return SW_NOT_SUPPORTED; -} - -sw_error_t -hppe_in_flow_tbl_rd_rslt_data7_get( - a_uint32_t dev_id, - union in_flow_tbl_rd_rslt_data7_u *value) -{ - return hppe_reg_get( - dev_id, - IPE_L3_BASE_ADDR + IN_FLOW_TBL_RD_RSLT_DATA7_ADDRESS, - &value->val); -} - -sw_error_t -hppe_in_flow_tbl_rd_rslt_data7_set( - a_uint32_t dev_id, - union in_flow_tbl_rd_rslt_data7_u *value) -{ - return SW_NOT_SUPPORTED; -} - -sw_error_t -hppe_in_flow_tbl_rd_rslt_data8_get( - a_uint32_t dev_id, - union in_flow_tbl_rd_rslt_data8_u *value) -{ - return hppe_reg_get( - dev_id, - IPE_L3_BASE_ADDR + IN_FLOW_TBL_RD_RSLT_DATA8_ADDRESS, - &value->val); -} - -sw_error_t -hppe_in_flow_tbl_rd_rslt_data8_set( - a_uint32_t dev_id, - union in_flow_tbl_rd_rslt_data8_u *value) -{ - return SW_NOT_SUPPORTED; -} - -sw_error_t -hppe_flow_host_tbl_rd_rslt_data0_get( - a_uint32_t dev_id, - union flow_host_tbl_rd_rslt_data0_u *value) -{ - return hppe_reg_get( - dev_id, - IPE_L3_BASE_ADDR + FLOW_HOST_TBL_RD_RSLT_DATA0_ADDRESS, - &value->val); -} - -sw_error_t -hppe_flow_host_tbl_rd_rslt_data0_set( - a_uint32_t dev_id, - union flow_host_tbl_rd_rslt_data0_u *value) -{ - return SW_NOT_SUPPORTED; -} - -sw_error_t -hppe_flow_host_tbl_rd_rslt_data1_get( - a_uint32_t dev_id, - union flow_host_tbl_rd_rslt_data1_u *value) -{ - return hppe_reg_get( - dev_id, - IPE_L3_BASE_ADDR + FLOW_HOST_TBL_RD_RSLT_DATA1_ADDRESS, - &value->val); -} - -sw_error_t -hppe_flow_host_tbl_rd_rslt_data1_set( - a_uint32_t dev_id, - union flow_host_tbl_rd_rslt_data1_u *value) -{ - return SW_NOT_SUPPORTED; -} - -sw_error_t -hppe_flow_host_tbl_rd_rslt_data2_get( - a_uint32_t dev_id, - union flow_host_tbl_rd_rslt_data2_u *value) -{ - return hppe_reg_get( - dev_id, - IPE_L3_BASE_ADDR + FLOW_HOST_TBL_RD_RSLT_DATA2_ADDRESS, - &value->val); -} - -sw_error_t -hppe_flow_host_tbl_rd_rslt_data2_set( - a_uint32_t dev_id, - union flow_host_tbl_rd_rslt_data2_u *value) -{ - return SW_NOT_SUPPORTED; -} - -sw_error_t -hppe_flow_host_tbl_rd_rslt_data3_get( - a_uint32_t dev_id, - union flow_host_tbl_rd_rslt_data3_u *value) -{ - return hppe_reg_get( - dev_id, - IPE_L3_BASE_ADDR + FLOW_HOST_TBL_RD_RSLT_DATA3_ADDRESS, - &value->val); -} - -sw_error_t -hppe_flow_host_tbl_rd_rslt_data3_set( - a_uint32_t dev_id, - union flow_host_tbl_rd_rslt_data3_u *value) -{ - return SW_NOT_SUPPORTED; -} - -sw_error_t -hppe_flow_host_tbl_rd_rslt_data4_get( - a_uint32_t dev_id, - union flow_host_tbl_rd_rslt_data4_u *value) -{ - return hppe_reg_get( - dev_id, - IPE_L3_BASE_ADDR + FLOW_HOST_TBL_RD_RSLT_DATA4_ADDRESS, - &value->val); -} - -sw_error_t -hppe_flow_host_tbl_rd_rslt_data4_set( - a_uint32_t dev_id, - union flow_host_tbl_rd_rslt_data4_u *value) -{ - return SW_NOT_SUPPORTED; -} - -sw_error_t -hppe_flow_host_tbl_rd_rslt_data5_get( - a_uint32_t dev_id, - union flow_host_tbl_rd_rslt_data5_u *value) -{ - return hppe_reg_get( - dev_id, - IPE_L3_BASE_ADDR + FLOW_HOST_TBL_RD_RSLT_DATA5_ADDRESS, - &value->val); -} - -sw_error_t -hppe_flow_host_tbl_rd_rslt_data5_set( - a_uint32_t dev_id, - union flow_host_tbl_rd_rslt_data5_u *value) -{ - return SW_NOT_SUPPORTED; -} - -sw_error_t -hppe_flow_host_tbl_rd_rslt_data6_get( - a_uint32_t dev_id, - union flow_host_tbl_rd_rslt_data6_u *value) -{ - return hppe_reg_get( - dev_id, - IPE_L3_BASE_ADDR + FLOW_HOST_TBL_RD_RSLT_DATA6_ADDRESS, - &value->val); -} - -sw_error_t -hppe_flow_host_tbl_rd_rslt_data6_set( - a_uint32_t dev_id, - union flow_host_tbl_rd_rslt_data6_u *value) -{ - return SW_NOT_SUPPORTED; -} - -sw_error_t -hppe_flow_host_tbl_rd_rslt_data7_get( - a_uint32_t dev_id, - union flow_host_tbl_rd_rslt_data7_u *value) -{ - return hppe_reg_get( - dev_id, - IPE_L3_BASE_ADDR + FLOW_HOST_TBL_RD_RSLT_DATA7_ADDRESS, - &value->val); -} - -sw_error_t -hppe_flow_host_tbl_rd_rslt_data7_set( - a_uint32_t dev_id, - union flow_host_tbl_rd_rslt_data7_u *value) -{ - return SW_NOT_SUPPORTED; -} - -sw_error_t -hppe_flow_host_tbl_rd_rslt_data8_get( - a_uint32_t dev_id, - union flow_host_tbl_rd_rslt_data8_u *value) -{ - return hppe_reg_get( - dev_id, - IPE_L3_BASE_ADDR + FLOW_HOST_TBL_RD_RSLT_DATA8_ADDRESS, - &value->val); -} - -sw_error_t -hppe_flow_host_tbl_rd_rslt_data8_set( - a_uint32_t dev_id, - union flow_host_tbl_rd_rslt_data8_u *value) -{ - return SW_NOT_SUPPORTED; -} - -sw_error_t -hppe_flow_host_tbl_rd_rslt_data9_get( - a_uint32_t dev_id, - union flow_host_tbl_rd_rslt_data9_u *value) -{ - return hppe_reg_get( - dev_id, - IPE_L3_BASE_ADDR + FLOW_HOST_TBL_RD_RSLT_DATA9_ADDRESS, - &value->val); -} - -sw_error_t -hppe_flow_host_tbl_rd_rslt_data9_set( - a_uint32_t dev_id, - union flow_host_tbl_rd_rslt_data9_u *value) -{ - return SW_NOT_SUPPORTED; -} - -sw_error_t -hppe_in_flow_3tuple_tbl_get( - a_uint32_t dev_id, - a_uint32_t index, - union in_flow_3tuple_tbl_u *value) -{ - return hppe_reg_tbl_get( - dev_id, - IPE_L3_BASE_ADDR + IN_FLOW_3TUPLE_TBL_ADDRESS + \ - index * IN_FLOW_3TUPLE_TBL_INC, - value->val, - 4); -} - -sw_error_t -hppe_in_flow_3tuple_tbl_set( - a_uint32_t dev_id, - a_uint32_t index, - union in_flow_3tuple_tbl_u *value) -{ - return hppe_reg_tbl_set( - dev_id, - IPE_L3_BASE_ADDR + IN_FLOW_3TUPLE_TBL_ADDRESS + \ - index * IN_FLOW_3TUPLE_TBL_INC, - value->val, - 4); -} - -sw_error_t -hppe_in_flow_ipv6_3tuple_tbl_get( - a_uint32_t dev_id, - a_uint32_t index, - union in_flow_ipv6_3tuple_tbl_u *value) -{ - return hppe_reg_tbl_get( - dev_id, - IPE_L3_BASE_ADDR + IN_FLOW_IPV6_3TUPLE_TBL_ADDRESS + \ - index * IN_FLOW_IPV6_3TUPLE_TBL_INC, - value->val, - 9); -} - -sw_error_t -hppe_in_flow_ipv6_3tuple_tbl_set( - a_uint32_t dev_id, - a_uint32_t index, - union in_flow_ipv6_3tuple_tbl_u *value) -{ - return hppe_reg_tbl_set( - dev_id, - IPE_L3_BASE_ADDR + IN_FLOW_IPV6_3TUPLE_TBL_ADDRESS + \ - index * IN_FLOW_IPV6_3TUPLE_TBL_INC, - value->val, - 9); -} - -sw_error_t -hppe_in_flow_ipv6_5tuple_tbl_get( - a_uint32_t dev_id, - a_uint32_t index, - union in_flow_ipv6_5tuple_tbl_u *value) -{ - return hppe_reg_tbl_get( - dev_id, - IPE_L3_BASE_ADDR + IN_FLOW_IPV6_5TUPLE_TBL_ADDRESS + \ - index * IN_FLOW_IPV6_5TUPLE_TBL_INC, - value->val, - 9); -} - -sw_error_t -hppe_in_flow_ipv6_5tuple_tbl_set( - a_uint32_t dev_id, - a_uint32_t index, - union in_flow_ipv6_5tuple_tbl_u *value) -{ - return hppe_reg_tbl_set( - dev_id, - IPE_L3_BASE_ADDR + IN_FLOW_IPV6_5TUPLE_TBL_ADDRESS + \ - index * IN_FLOW_IPV6_5TUPLE_TBL_INC, - value->val, - 9); -} - -sw_error_t -hppe_in_flow_tbl_get( - a_uint32_t dev_id, - a_uint32_t index, - union in_flow_tbl_u *value) -{ - return hppe_reg_tbl_get( - dev_id, - IPE_L3_BASE_ADDR + IN_FLOW_TBL_ADDRESS + \ - index * IN_FLOW_TBL_INC, - value->val, - 5); -} - -sw_error_t -hppe_in_flow_tbl_set( - a_uint32_t dev_id, - a_uint32_t index, - union in_flow_tbl_u *value) -{ - return hppe_reg_tbl_set( - dev_id, - IPE_L3_BASE_ADDR + IN_FLOW_TBL_ADDRESS + \ - index * IN_FLOW_TBL_INC, - value->val, - 5); -} - -sw_error_t -hppe_eg_flow_tree_map_tbl_get( - a_uint32_t dev_id, - a_uint32_t index, - union eg_flow_tree_map_tbl_u *value) -{ - if (index >= EG_FLOW_TREE_MAP_TBL_MAX_ENTRY) - return SW_OUT_OF_RANGE; - return hppe_reg_get( - dev_id, - NSS_PTX_CSR_BASE_ADDR + EG_FLOW_TREE_MAP_TBL_ADDRESS + \ - index * EG_FLOW_TREE_MAP_TBL_INC, - &value->val); -} - -sw_error_t -hppe_eg_flow_tree_map_tbl_set( - a_uint32_t dev_id, - a_uint32_t index, - union eg_flow_tree_map_tbl_u *value) -{ - return hppe_reg_set( - dev_id, - NSS_PTX_CSR_BASE_ADDR + EG_FLOW_TREE_MAP_TBL_ADDRESS + \ - index * EG_FLOW_TREE_MAP_TBL_INC, - value->val); -} - -sw_error_t -hppe_flow_ctrl0_flow_hash_mode_0_get( - a_uint32_t dev_id, - a_uint32_t *value) -{ - union flow_ctrl0_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_flow_ctrl0_get(dev_id, ®_val); - *value = reg_val.bf.flow_hash_mode_0; - return ret; -} - -sw_error_t -hppe_flow_ctrl0_flow_hash_mode_0_set( - a_uint32_t dev_id, - a_uint32_t value) -{ - union flow_ctrl0_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_flow_ctrl0_get(dev_id, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.flow_hash_mode_0 = value; - ret = hppe_flow_ctrl0_set(dev_id, ®_val); - return ret; -} - -sw_error_t -hppe_flow_ctrl0_flow_age_timer_unit_get( - a_uint32_t dev_id, - a_uint32_t *value) -{ - union flow_ctrl0_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_flow_ctrl0_get(dev_id, ®_val); - *value = reg_val.bf.flow_age_timer_unit; - return ret; -} - -sw_error_t -hppe_flow_ctrl0_flow_age_timer_unit_set( - a_uint32_t dev_id, - a_uint32_t value) -{ - union flow_ctrl0_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_flow_ctrl0_get(dev_id, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.flow_age_timer_unit = value; - ret = hppe_flow_ctrl0_set(dev_id, ®_val); - return ret; -} - -sw_error_t -hppe_flow_ctrl0_flow_hash_mode_1_get( - a_uint32_t dev_id, - a_uint32_t *value) -{ - union flow_ctrl0_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_flow_ctrl0_get(dev_id, ®_val); - *value = reg_val.bf.flow_hash_mode_1; - return ret; -} - -sw_error_t -hppe_flow_ctrl0_flow_hash_mode_1_set( - a_uint32_t dev_id, - a_uint32_t value) -{ - union flow_ctrl0_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_flow_ctrl0_get(dev_id, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.flow_hash_mode_1 = value; - ret = hppe_flow_ctrl0_set(dev_id, ®_val); - return ret; -} - -sw_error_t -hppe_flow_ctrl0_flow_age_timer_get( - a_uint32_t dev_id, - a_uint32_t *value) -{ - union flow_ctrl0_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_flow_ctrl0_get(dev_id, ®_val); - *value = reg_val.bf.flow_age_timer; - return ret; -} - -sw_error_t -hppe_flow_ctrl0_flow_age_timer_set( - a_uint32_t dev_id, - a_uint32_t value) -{ - union flow_ctrl0_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_flow_ctrl0_get(dev_id, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.flow_age_timer = value; - ret = hppe_flow_ctrl0_set(dev_id, ®_val); - return ret; -} - -sw_error_t -hppe_flow_ctrl0_flow_en_get( - a_uint32_t dev_id, - a_uint32_t *value) -{ - union flow_ctrl0_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_flow_ctrl0_get(dev_id, ®_val); - *value = reg_val.bf.flow_en; - return ret; -} - -sw_error_t -hppe_flow_ctrl0_flow_en_set( - a_uint32_t dev_id, - a_uint32_t value) -{ - union flow_ctrl0_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_flow_ctrl0_get(dev_id, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.flow_en = value; - ret = hppe_flow_ctrl0_set(dev_id, ®_val); - return ret; -} - -sw_error_t -hppe_flow_ctrl1_flow_ctl1_frag_bypass_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union flow_ctrl1_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_flow_ctrl1_get(dev_id, index, ®_val); - *value = reg_val.bf.flow_ctl1_frag_bypass; - return ret; -} - -sw_error_t -hppe_flow_ctrl1_flow_ctl1_frag_bypass_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - union flow_ctrl1_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_flow_ctrl1_get(dev_id, index, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.flow_ctl1_frag_bypass = value; - ret = hppe_flow_ctrl1_set(dev_id, index, ®_val); - return ret; -} - -sw_error_t -hppe_flow_ctrl1_flow_ctl4_key_sel_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union flow_ctrl1_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_flow_ctrl1_get(dev_id, index, ®_val); - *value = reg_val.bf.flow_ctl4_key_sel; - return ret; -} - -sw_error_t -hppe_flow_ctrl1_flow_ctl4_key_sel_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - union flow_ctrl1_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_flow_ctrl1_get(dev_id, index, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.flow_ctl4_key_sel = value; - ret = hppe_flow_ctrl1_set(dev_id, index, ®_val); - return ret; -} - -sw_error_t -hppe_flow_ctrl1_flow_ctl1_key_sel_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union flow_ctrl1_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_flow_ctrl1_get(dev_id, index, ®_val); - *value = reg_val.bf.flow_ctl1_key_sel; - return ret; -} - -sw_error_t -hppe_flow_ctrl1_flow_ctl1_key_sel_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - union flow_ctrl1_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_flow_ctrl1_get(dev_id, index, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.flow_ctl1_key_sel = value; - ret = hppe_flow_ctrl1_set(dev_id, index, ®_val); - return ret; -} - -sw_error_t -hppe_flow_ctrl1_flow_ctl0_frag_bypass_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union flow_ctrl1_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_flow_ctrl1_get(dev_id, index, ®_val); - *value = reg_val.bf.flow_ctl0_frag_bypass; - return ret; -} - -sw_error_t -hppe_flow_ctrl1_flow_ctl0_frag_bypass_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - union flow_ctrl1_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_flow_ctrl1_get(dev_id, index, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.flow_ctl0_frag_bypass = value; - ret = hppe_flow_ctrl1_set(dev_id, index, ®_val); - return ret; -} - -sw_error_t -hppe_flow_ctrl1_flow_ctl0_miss_action_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union flow_ctrl1_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_flow_ctrl1_get(dev_id, index, ®_val); - *value = reg_val.bf.flow_ctl0_miss_action; - return ret; -} - -sw_error_t -hppe_flow_ctrl1_flow_ctl0_miss_action_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - union flow_ctrl1_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_flow_ctrl1_get(dev_id, index, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.flow_ctl0_miss_action = value; - ret = hppe_flow_ctrl1_set(dev_id, index, ®_val); - return ret; -} - -sw_error_t -hppe_flow_ctrl1_flow_ctl0_key_sel_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union flow_ctrl1_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_flow_ctrl1_get(dev_id, index, ®_val); - *value = reg_val.bf.flow_ctl0_key_sel; - return ret; -} - -sw_error_t -hppe_flow_ctrl1_flow_ctl0_key_sel_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - union flow_ctrl1_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_flow_ctrl1_get(dev_id, index, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.flow_ctl0_key_sel = value; - ret = hppe_flow_ctrl1_set(dev_id, index, ®_val); - return ret; -} - -sw_error_t -hppe_flow_ctrl1_flow_ctl1_bypass_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union flow_ctrl1_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_flow_ctrl1_get(dev_id, index, ®_val); - *value = reg_val.bf.flow_ctl1_bypass; - return ret; -} - -sw_error_t -hppe_flow_ctrl1_flow_ctl1_bypass_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - union flow_ctrl1_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_flow_ctrl1_get(dev_id, index, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.flow_ctl1_bypass = value; - ret = hppe_flow_ctrl1_set(dev_id, index, ®_val); - return ret; -} - -sw_error_t -hppe_flow_ctrl1_flow_ctl0_bypass_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union flow_ctrl1_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_flow_ctrl1_get(dev_id, index, ®_val); - *value = reg_val.bf.flow_ctl0_bypass; - return ret; -} - -sw_error_t -hppe_flow_ctrl1_flow_ctl0_bypass_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - union flow_ctrl1_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_flow_ctrl1_get(dev_id, index, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.flow_ctl0_bypass = value; - ret = hppe_flow_ctrl1_set(dev_id, index, ®_val); - return ret; -} - -sw_error_t -hppe_flow_ctrl1_flow_ctl2_tcp_special_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union flow_ctrl1_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_flow_ctrl1_get(dev_id, index, ®_val); - *value = reg_val.bf.flow_ctl2_tcp_special; - return ret; -} - -sw_error_t -hppe_flow_ctrl1_flow_ctl2_tcp_special_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - union flow_ctrl1_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_flow_ctrl1_get(dev_id, index, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.flow_ctl2_tcp_special = value; - ret = hppe_flow_ctrl1_set(dev_id, index, ®_val); - return ret; -} - -sw_error_t -hppe_flow_ctrl1_flow_ctl4_tcp_special_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union flow_ctrl1_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_flow_ctrl1_get(dev_id, index, ®_val); - *value = reg_val.bf.flow_ctl4_tcp_special; - return ret; -} - -sw_error_t -hppe_flow_ctrl1_flow_ctl4_tcp_special_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - union flow_ctrl1_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_flow_ctrl1_get(dev_id, index, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.flow_ctl4_tcp_special = value; - ret = hppe_flow_ctrl1_set(dev_id, index, ®_val); - return ret; -} - -sw_error_t -hppe_flow_ctrl1_flow_ctl3_frag_bypass_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union flow_ctrl1_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_flow_ctrl1_get(dev_id, index, ®_val); - *value = reg_val.bf.flow_ctl3_frag_bypass; - return ret; -} - -sw_error_t -hppe_flow_ctrl1_flow_ctl3_frag_bypass_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - union flow_ctrl1_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_flow_ctrl1_get(dev_id, index, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.flow_ctl3_frag_bypass = value; - ret = hppe_flow_ctrl1_set(dev_id, index, ®_val); - return ret; -} - -sw_error_t -hppe_flow_ctrl1_flow_ctl3_bypass_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union flow_ctrl1_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_flow_ctrl1_get(dev_id, index, ®_val); - *value = reg_val.bf.flow_ctl3_bypass; - return ret; -} - -sw_error_t -hppe_flow_ctrl1_flow_ctl3_bypass_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - union flow_ctrl1_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_flow_ctrl1_get(dev_id, index, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.flow_ctl3_bypass = value; - ret = hppe_flow_ctrl1_set(dev_id, index, ®_val); - return ret; -} - -sw_error_t -hppe_flow_ctrl1_flow_ctl3_tcp_special_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union flow_ctrl1_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_flow_ctrl1_get(dev_id, index, ®_val); - *value = reg_val.bf.flow_ctl3_tcp_special; - return ret; -} - -sw_error_t -hppe_flow_ctrl1_flow_ctl3_tcp_special_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - union flow_ctrl1_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_flow_ctrl1_get(dev_id, index, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.flow_ctl3_tcp_special = value; - ret = hppe_flow_ctrl1_set(dev_id, index, ®_val); - return ret; -} - -sw_error_t -hppe_flow_ctrl1_flow_ctl1_miss_action_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union flow_ctrl1_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_flow_ctrl1_get(dev_id, index, ®_val); - *value = reg_val.bf.flow_ctl1_miss_action; - return ret; -} - -sw_error_t -hppe_flow_ctrl1_flow_ctl1_miss_action_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - union flow_ctrl1_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_flow_ctrl1_get(dev_id, index, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.flow_ctl1_miss_action = value; - ret = hppe_flow_ctrl1_set(dev_id, index, ®_val); - return ret; -} - -sw_error_t -hppe_flow_ctrl1_flow_ctl4_frag_bypass_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union flow_ctrl1_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_flow_ctrl1_get(dev_id, index, ®_val); - *value = reg_val.bf.flow_ctl4_frag_bypass; - return ret; -} - -sw_error_t -hppe_flow_ctrl1_flow_ctl4_frag_bypass_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - union flow_ctrl1_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_flow_ctrl1_get(dev_id, index, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.flow_ctl4_frag_bypass = value; - ret = hppe_flow_ctrl1_set(dev_id, index, ®_val); - return ret; -} - -sw_error_t -hppe_flow_ctrl1_flow_ctl1_tcp_special_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union flow_ctrl1_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_flow_ctrl1_get(dev_id, index, ®_val); - *value = reg_val.bf.flow_ctl1_tcp_special; - return ret; -} - -sw_error_t -hppe_flow_ctrl1_flow_ctl1_tcp_special_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - union flow_ctrl1_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_flow_ctrl1_get(dev_id, index, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.flow_ctl1_tcp_special = value; - ret = hppe_flow_ctrl1_set(dev_id, index, ®_val); - return ret; -} - -sw_error_t -hppe_flow_ctrl1_flow_ctl2_key_sel_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union flow_ctrl1_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_flow_ctrl1_get(dev_id, index, ®_val); - *value = reg_val.bf.flow_ctl2_key_sel; - return ret; -} - -sw_error_t -hppe_flow_ctrl1_flow_ctl2_key_sel_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - union flow_ctrl1_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_flow_ctrl1_get(dev_id, index, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.flow_ctl2_key_sel = value; - ret = hppe_flow_ctrl1_set(dev_id, index, ®_val); - return ret; -} - -sw_error_t -hppe_flow_ctrl1_flow_ctl2_miss_action_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union flow_ctrl1_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_flow_ctrl1_get(dev_id, index, ®_val); - *value = reg_val.bf.flow_ctl2_miss_action; - return ret; -} - -sw_error_t -hppe_flow_ctrl1_flow_ctl2_miss_action_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - union flow_ctrl1_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_flow_ctrl1_get(dev_id, index, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.flow_ctl2_miss_action = value; - ret = hppe_flow_ctrl1_set(dev_id, index, ®_val); - return ret; -} - -sw_error_t -hppe_flow_ctrl1_flow_ctl2_bypass_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union flow_ctrl1_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_flow_ctrl1_get(dev_id, index, ®_val); - *value = reg_val.bf.flow_ctl2_bypass; - return ret; -} - -sw_error_t -hppe_flow_ctrl1_flow_ctl2_bypass_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - union flow_ctrl1_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_flow_ctrl1_get(dev_id, index, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.flow_ctl2_bypass = value; - ret = hppe_flow_ctrl1_set(dev_id, index, ®_val); - return ret; -} - -sw_error_t -hppe_flow_ctrl1_flow_ctl4_bypass_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union flow_ctrl1_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_flow_ctrl1_get(dev_id, index, ®_val); - *value = reg_val.bf.flow_ctl4_bypass; - return ret; -} - -sw_error_t -hppe_flow_ctrl1_flow_ctl4_bypass_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - union flow_ctrl1_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_flow_ctrl1_get(dev_id, index, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.flow_ctl4_bypass = value; - ret = hppe_flow_ctrl1_set(dev_id, index, ®_val); - return ret; -} - -sw_error_t -hppe_flow_ctrl1_flow_ctl3_key_sel_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union flow_ctrl1_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_flow_ctrl1_get(dev_id, index, ®_val); - *value = reg_val.bf.flow_ctl3_key_sel; - return ret; -} - -sw_error_t -hppe_flow_ctrl1_flow_ctl3_key_sel_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - union flow_ctrl1_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_flow_ctrl1_get(dev_id, index, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.flow_ctl3_key_sel = value; - ret = hppe_flow_ctrl1_set(dev_id, index, ®_val); - return ret; -} - -sw_error_t -hppe_flow_ctrl1_flow_ctl0_tcp_special_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union flow_ctrl1_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_flow_ctrl1_get(dev_id, index, ®_val); - *value = reg_val.bf.flow_ctl0_tcp_special; - return ret; -} - -sw_error_t -hppe_flow_ctrl1_flow_ctl0_tcp_special_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - union flow_ctrl1_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_flow_ctrl1_get(dev_id, index, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.flow_ctl0_tcp_special = value; - ret = hppe_flow_ctrl1_set(dev_id, index, ®_val); - return ret; -} - -sw_error_t -hppe_flow_ctrl1_flow_ctl2_frag_bypass_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union flow_ctrl1_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_flow_ctrl1_get(dev_id, index, ®_val); - *value = reg_val.bf.flow_ctl2_frag_bypass; - return ret; -} - -sw_error_t -hppe_flow_ctrl1_flow_ctl2_frag_bypass_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - union flow_ctrl1_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_flow_ctrl1_get(dev_id, index, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.flow_ctl2_frag_bypass = value; - ret = hppe_flow_ctrl1_set(dev_id, index, ®_val); - return ret; -} - -sw_error_t -hppe_flow_ctrl1_flow_ctl3_miss_action_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union flow_ctrl1_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_flow_ctrl1_get(dev_id, index, ®_val); - *value = reg_val.bf.flow_ctl3_miss_action; - return ret; -} - -sw_error_t -hppe_flow_ctrl1_flow_ctl3_miss_action_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - union flow_ctrl1_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_flow_ctrl1_get(dev_id, index, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.flow_ctl3_miss_action = value; - ret = hppe_flow_ctrl1_set(dev_id, index, ®_val); - return ret; -} - -sw_error_t -hppe_flow_ctrl1_flow_ctl4_miss_action_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union flow_ctrl1_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_flow_ctrl1_get(dev_id, index, ®_val); - *value = reg_val.bf.flow_ctl4_miss_action; - return ret; -} - -sw_error_t -hppe_flow_ctrl1_flow_ctl4_miss_action_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - union flow_ctrl1_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_flow_ctrl1_get(dev_id, index, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.flow_ctl4_miss_action = value; - ret = hppe_flow_ctrl1_set(dev_id, index, ®_val); - return ret; -} - -sw_error_t -hppe_in_flow_tbl_op_entry_index_get( - a_uint32_t dev_id, - a_uint32_t *value) -{ - union in_flow_tbl_op_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_in_flow_tbl_op_get(dev_id, ®_val); - *value = reg_val.bf.entry_index; - return ret; -} - -sw_error_t -hppe_in_flow_tbl_op_entry_index_set( - a_uint32_t dev_id, - a_uint32_t value) -{ - union in_flow_tbl_op_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_in_flow_tbl_op_get(dev_id, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.entry_index = value; - ret = hppe_in_flow_tbl_op_set(dev_id, ®_val); - return ret; -} - -sw_error_t -hppe_in_flow_tbl_op_cmd_id_get( - a_uint32_t dev_id, - a_uint32_t *value) -{ - union in_flow_tbl_op_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_in_flow_tbl_op_get(dev_id, ®_val); - *value = reg_val.bf.cmd_id; - return ret; -} - -sw_error_t -hppe_in_flow_tbl_op_cmd_id_set( - a_uint32_t dev_id, - a_uint32_t value) -{ - union in_flow_tbl_op_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_in_flow_tbl_op_get(dev_id, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.cmd_id = value; - ret = hppe_in_flow_tbl_op_set(dev_id, ®_val); - return ret; -} - -sw_error_t -hppe_in_flow_tbl_op_byp_rslt_en_get( - a_uint32_t dev_id, - a_uint32_t *value) -{ - union in_flow_tbl_op_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_in_flow_tbl_op_get(dev_id, ®_val); - *value = reg_val.bf.byp_rslt_en; - return ret; -} - -sw_error_t -hppe_in_flow_tbl_op_byp_rslt_en_set( - a_uint32_t dev_id, - a_uint32_t value) -{ - union in_flow_tbl_op_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_in_flow_tbl_op_get(dev_id, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.byp_rslt_en = value; - ret = hppe_in_flow_tbl_op_set(dev_id, ®_val); - return ret; -} - -sw_error_t -hppe_in_flow_tbl_op_op_mode_get( - a_uint32_t dev_id, - a_uint32_t *value) -{ - union in_flow_tbl_op_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_in_flow_tbl_op_get(dev_id, ®_val); - *value = reg_val.bf.op_mode; - return ret; -} - -sw_error_t -hppe_in_flow_tbl_op_op_mode_set( - a_uint32_t dev_id, - a_uint32_t value) -{ - union in_flow_tbl_op_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_in_flow_tbl_op_get(dev_id, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.op_mode = value; - ret = hppe_in_flow_tbl_op_set(dev_id, ®_val); - return ret; -} - -sw_error_t -hppe_in_flow_tbl_op_op_type_get( - a_uint32_t dev_id, - a_uint32_t *value) -{ - union in_flow_tbl_op_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_in_flow_tbl_op_get(dev_id, ®_val); - *value = reg_val.bf.op_type; - return ret; -} - -sw_error_t -hppe_in_flow_tbl_op_op_type_set( - a_uint32_t dev_id, - a_uint32_t value) -{ - union in_flow_tbl_op_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_in_flow_tbl_op_get(dev_id, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.op_type = value; - ret = hppe_in_flow_tbl_op_set(dev_id, ®_val); - return ret; -} - -sw_error_t -hppe_in_flow_tbl_op_op_host_en_get( - a_uint32_t dev_id, - a_uint32_t *value) -{ - union in_flow_tbl_op_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_in_flow_tbl_op_get(dev_id, ®_val); - *value = reg_val.bf.op_host_en; - return ret; -} - -sw_error_t -hppe_in_flow_tbl_op_op_host_en_set( - a_uint32_t dev_id, - a_uint32_t value) -{ - union in_flow_tbl_op_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_in_flow_tbl_op_get(dev_id, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.op_host_en = value; - ret = hppe_in_flow_tbl_op_set(dev_id, ®_val); - return ret; -} - -sw_error_t -hppe_in_flow_tbl_op_op_result_get( - a_uint32_t dev_id, - a_uint32_t *value) -{ - union in_flow_tbl_op_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_in_flow_tbl_op_get(dev_id, ®_val); - *value = reg_val.bf.op_result; - return ret; -} - -sw_error_t -hppe_in_flow_tbl_op_op_result_set( - a_uint32_t dev_id, - a_uint32_t value) -{ - union in_flow_tbl_op_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_in_flow_tbl_op_get(dev_id, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.op_result = value; - ret = hppe_in_flow_tbl_op_set(dev_id, ®_val); - return ret; -} - -sw_error_t -hppe_in_flow_tbl_op_busy_get( - a_uint32_t dev_id, - a_uint32_t *value) -{ - union in_flow_tbl_op_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_in_flow_tbl_op_get(dev_id, ®_val); - *value = reg_val.bf.busy; - return ret; -} - -sw_error_t -hppe_in_flow_tbl_op_busy_set( - a_uint32_t dev_id, - a_uint32_t value) -{ - union in_flow_tbl_op_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_in_flow_tbl_op_get(dev_id, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.busy = value; - ret = hppe_in_flow_tbl_op_set(dev_id, ®_val); - return ret; -} - -sw_error_t -hppe_in_flow_tbl_op_hash_block_bitmap_get( - a_uint32_t dev_id, - a_uint32_t *value) -{ - union in_flow_tbl_op_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_in_flow_tbl_op_get(dev_id, ®_val); - *value = reg_val.bf.hash_block_bitmap; - return ret; -} - -sw_error_t -hppe_in_flow_tbl_op_hash_block_bitmap_set( - a_uint32_t dev_id, - a_uint32_t value) -{ - union in_flow_tbl_op_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_in_flow_tbl_op_get(dev_id, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.hash_block_bitmap = value; - ret = hppe_in_flow_tbl_op_set(dev_id, ®_val); - return ret; -} - -sw_error_t -hppe_in_flow_host_tbl_op_host_entry_index_get( - a_uint32_t dev_id, - a_uint32_t *value) -{ - union in_flow_host_tbl_op_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_in_flow_host_tbl_op_get(dev_id, ®_val); - *value = reg_val.bf.host_entry_index; - return ret; -} - -sw_error_t -hppe_in_flow_host_tbl_op_host_entry_index_set( - a_uint32_t dev_id, - a_uint32_t value) -{ - union in_flow_host_tbl_op_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_in_flow_host_tbl_op_get(dev_id, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.host_entry_index = value; - ret = hppe_in_flow_host_tbl_op_set(dev_id, ®_val); - return ret; -} - -sw_error_t -hppe_in_flow_host_tbl_op_hash_block_bitmap_get( - a_uint32_t dev_id, - a_uint32_t *value) -{ - union in_flow_host_tbl_op_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_in_flow_host_tbl_op_get(dev_id, ®_val); - *value = reg_val.bf.hash_block_bitmap; - return ret; -} - -sw_error_t -hppe_in_flow_host_tbl_op_hash_block_bitmap_set( - a_uint32_t dev_id, - a_uint32_t value) -{ - union in_flow_host_tbl_op_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_in_flow_host_tbl_op_get(dev_id, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.hash_block_bitmap = value; - ret = hppe_in_flow_host_tbl_op_set(dev_id, ®_val); - return ret; -} - -sw_error_t -hppe_in_flow_tbl_op_data0_data_get( - a_uint32_t dev_id, - a_uint32_t *value) -{ - union in_flow_tbl_op_data0_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_in_flow_tbl_op_data0_get(dev_id, ®_val); - *value = reg_val.bf.data; - return ret; -} - -sw_error_t -hppe_in_flow_tbl_op_data0_data_set( - a_uint32_t dev_id, - a_uint32_t value) -{ - union in_flow_tbl_op_data0_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_in_flow_tbl_op_data0_get(dev_id, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.data = value; - ret = hppe_in_flow_tbl_op_data0_set(dev_id, ®_val); - return ret; -} - -sw_error_t -hppe_in_flow_tbl_op_data1_data_get( - a_uint32_t dev_id, - a_uint32_t *value) -{ - union in_flow_tbl_op_data1_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_in_flow_tbl_op_data1_get(dev_id, ®_val); - *value = reg_val.bf.data; - return ret; -} - -sw_error_t -hppe_in_flow_tbl_op_data1_data_set( - a_uint32_t dev_id, - a_uint32_t value) -{ - union in_flow_tbl_op_data1_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_in_flow_tbl_op_data1_get(dev_id, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.data = value; - ret = hppe_in_flow_tbl_op_data1_set(dev_id, ®_val); - return ret; -} - -sw_error_t -hppe_in_flow_tbl_op_data2_data_get( - a_uint32_t dev_id, - a_uint32_t *value) -{ - union in_flow_tbl_op_data2_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_in_flow_tbl_op_data2_get(dev_id, ®_val); - *value = reg_val.bf.data; - return ret; -} - -sw_error_t -hppe_in_flow_tbl_op_data2_data_set( - a_uint32_t dev_id, - a_uint32_t value) -{ - union in_flow_tbl_op_data2_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_in_flow_tbl_op_data2_get(dev_id, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.data = value; - ret = hppe_in_flow_tbl_op_data2_set(dev_id, ®_val); - return ret; -} - -sw_error_t -hppe_in_flow_tbl_op_data3_data_get( - a_uint32_t dev_id, - a_uint32_t *value) -{ - union in_flow_tbl_op_data3_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_in_flow_tbl_op_data3_get(dev_id, ®_val); - *value = reg_val.bf.data; - return ret; -} - -sw_error_t -hppe_in_flow_tbl_op_data3_data_set( - a_uint32_t dev_id, - a_uint32_t value) -{ - union in_flow_tbl_op_data3_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_in_flow_tbl_op_data3_get(dev_id, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.data = value; - ret = hppe_in_flow_tbl_op_data3_set(dev_id, ®_val); - return ret; -} - -sw_error_t -hppe_in_flow_tbl_op_data4_data_get( - a_uint32_t dev_id, - a_uint32_t *value) -{ - union in_flow_tbl_op_data4_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_in_flow_tbl_op_data4_get(dev_id, ®_val); - *value = reg_val.bf.data; - return ret; -} - -sw_error_t -hppe_in_flow_tbl_op_data4_data_set( - a_uint32_t dev_id, - a_uint32_t value) -{ - union in_flow_tbl_op_data4_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_in_flow_tbl_op_data4_get(dev_id, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.data = value; - ret = hppe_in_flow_tbl_op_data4_set(dev_id, ®_val); - return ret; -} - -sw_error_t -hppe_in_flow_tbl_op_data5_data_get( - a_uint32_t dev_id, - a_uint32_t *value) -{ - union in_flow_tbl_op_data5_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_in_flow_tbl_op_data5_get(dev_id, ®_val); - *value = reg_val.bf.data; - return ret; -} - -sw_error_t -hppe_in_flow_tbl_op_data5_data_set( - a_uint32_t dev_id, - a_uint32_t value) -{ - union in_flow_tbl_op_data5_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_in_flow_tbl_op_data5_get(dev_id, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.data = value; - ret = hppe_in_flow_tbl_op_data5_set(dev_id, ®_val); - return ret; -} - -sw_error_t -hppe_in_flow_tbl_op_data6_data_get( - a_uint32_t dev_id, - a_uint32_t *value) -{ - union in_flow_tbl_op_data6_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_in_flow_tbl_op_data6_get(dev_id, ®_val); - *value = reg_val.bf.data; - return ret; -} - -sw_error_t -hppe_in_flow_tbl_op_data6_data_set( - a_uint32_t dev_id, - a_uint32_t value) -{ - union in_flow_tbl_op_data6_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_in_flow_tbl_op_data6_get(dev_id, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.data = value; - ret = hppe_in_flow_tbl_op_data6_set(dev_id, ®_val); - return ret; -} - -sw_error_t -hppe_in_flow_tbl_op_data7_data_get( - a_uint32_t dev_id, - a_uint32_t *value) -{ - union in_flow_tbl_op_data7_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_in_flow_tbl_op_data7_get(dev_id, ®_val); - *value = reg_val.bf.data; - return ret; -} - -sw_error_t -hppe_in_flow_tbl_op_data7_data_set( - a_uint32_t dev_id, - a_uint32_t value) -{ - union in_flow_tbl_op_data7_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_in_flow_tbl_op_data7_get(dev_id, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.data = value; - ret = hppe_in_flow_tbl_op_data7_set(dev_id, ®_val); - return ret; -} - -sw_error_t -hppe_in_flow_tbl_op_data8_data_get( - a_uint32_t dev_id, - a_uint32_t *value) -{ - union in_flow_tbl_op_data8_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_in_flow_tbl_op_data8_get(dev_id, ®_val); - *value = reg_val.bf.data; - return ret; -} - -sw_error_t -hppe_in_flow_tbl_op_data8_data_set( - a_uint32_t dev_id, - a_uint32_t value) -{ - union in_flow_tbl_op_data8_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_in_flow_tbl_op_data8_get(dev_id, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.data = value; - ret = hppe_in_flow_tbl_op_data8_set(dev_id, ®_val); - return ret; -} - -sw_error_t -hppe_flow_host_tbl_op_data0_data_get( - a_uint32_t dev_id, - a_uint32_t *value) -{ - union flow_host_tbl_op_data0_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_flow_host_tbl_op_data0_get(dev_id, ®_val); - *value = reg_val.bf.data; - return ret; -} - -sw_error_t -hppe_flow_host_tbl_op_data0_data_set( - a_uint32_t dev_id, - a_uint32_t value) -{ - union flow_host_tbl_op_data0_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_flow_host_tbl_op_data0_get(dev_id, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.data = value; - ret = hppe_flow_host_tbl_op_data0_set(dev_id, ®_val); - return ret; -} - -sw_error_t -hppe_flow_host_tbl_op_data1_data_get( - a_uint32_t dev_id, - a_uint32_t *value) -{ - union flow_host_tbl_op_data1_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_flow_host_tbl_op_data1_get(dev_id, ®_val); - *value = reg_val.bf.data; - return ret; -} - -sw_error_t -hppe_flow_host_tbl_op_data1_data_set( - a_uint32_t dev_id, - a_uint32_t value) -{ - union flow_host_tbl_op_data1_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_flow_host_tbl_op_data1_get(dev_id, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.data = value; - ret = hppe_flow_host_tbl_op_data1_set(dev_id, ®_val); - return ret; -} - -sw_error_t -hppe_flow_host_tbl_op_data2_data_get( - a_uint32_t dev_id, - a_uint32_t *value) -{ - union flow_host_tbl_op_data2_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_flow_host_tbl_op_data2_get(dev_id, ®_val); - *value = reg_val.bf.data; - return ret; -} - -sw_error_t -hppe_flow_host_tbl_op_data2_data_set( - a_uint32_t dev_id, - a_uint32_t value) -{ - union flow_host_tbl_op_data2_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_flow_host_tbl_op_data2_get(dev_id, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.data = value; - ret = hppe_flow_host_tbl_op_data2_set(dev_id, ®_val); - return ret; -} - -sw_error_t -hppe_flow_host_tbl_op_data3_data_get( - a_uint32_t dev_id, - a_uint32_t *value) -{ - union flow_host_tbl_op_data3_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_flow_host_tbl_op_data3_get(dev_id, ®_val); - *value = reg_val.bf.data; - return ret; -} - -sw_error_t -hppe_flow_host_tbl_op_data3_data_set( - a_uint32_t dev_id, - a_uint32_t value) -{ - union flow_host_tbl_op_data3_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_flow_host_tbl_op_data3_get(dev_id, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.data = value; - ret = hppe_flow_host_tbl_op_data3_set(dev_id, ®_val); - return ret; -} - -sw_error_t -hppe_flow_host_tbl_op_data4_data_get( - a_uint32_t dev_id, - a_uint32_t *value) -{ - union flow_host_tbl_op_data4_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_flow_host_tbl_op_data4_get(dev_id, ®_val); - *value = reg_val.bf.data; - return ret; -} - -sw_error_t -hppe_flow_host_tbl_op_data4_data_set( - a_uint32_t dev_id, - a_uint32_t value) -{ - union flow_host_tbl_op_data4_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_flow_host_tbl_op_data4_get(dev_id, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.data = value; - ret = hppe_flow_host_tbl_op_data4_set(dev_id, ®_val); - return ret; -} - -sw_error_t -hppe_flow_host_tbl_op_data5_data_get( - a_uint32_t dev_id, - a_uint32_t *value) -{ - union flow_host_tbl_op_data5_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_flow_host_tbl_op_data5_get(dev_id, ®_val); - *value = reg_val.bf.data; - return ret; -} - -sw_error_t -hppe_flow_host_tbl_op_data5_data_set( - a_uint32_t dev_id, - a_uint32_t value) -{ - union flow_host_tbl_op_data5_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_flow_host_tbl_op_data5_get(dev_id, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.data = value; - ret = hppe_flow_host_tbl_op_data5_set(dev_id, ®_val); - return ret; -} - -sw_error_t -hppe_flow_host_tbl_op_data6_data_get( - a_uint32_t dev_id, - a_uint32_t *value) -{ - union flow_host_tbl_op_data6_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_flow_host_tbl_op_data6_get(dev_id, ®_val); - *value = reg_val.bf.data; - return ret; -} - -sw_error_t -hppe_flow_host_tbl_op_data6_data_set( - a_uint32_t dev_id, - a_uint32_t value) -{ - union flow_host_tbl_op_data6_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_flow_host_tbl_op_data6_get(dev_id, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.data = value; - ret = hppe_flow_host_tbl_op_data6_set(dev_id, ®_val); - return ret; -} - -sw_error_t -hppe_flow_host_tbl_op_data7_data_get( - a_uint32_t dev_id, - a_uint32_t *value) -{ - union flow_host_tbl_op_data7_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_flow_host_tbl_op_data7_get(dev_id, ®_val); - *value = reg_val.bf.data; - return ret; -} - -sw_error_t -hppe_flow_host_tbl_op_data7_data_set( - a_uint32_t dev_id, - a_uint32_t value) -{ - union flow_host_tbl_op_data7_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_flow_host_tbl_op_data7_get(dev_id, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.data = value; - ret = hppe_flow_host_tbl_op_data7_set(dev_id, ®_val); - return ret; -} - -sw_error_t -hppe_flow_host_tbl_op_data8_data_get( - a_uint32_t dev_id, - a_uint32_t *value) -{ - union flow_host_tbl_op_data8_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_flow_host_tbl_op_data8_get(dev_id, ®_val); - *value = reg_val.bf.data; - return ret; -} - -sw_error_t -hppe_flow_host_tbl_op_data8_data_set( - a_uint32_t dev_id, - a_uint32_t value) -{ - union flow_host_tbl_op_data8_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_flow_host_tbl_op_data8_get(dev_id, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.data = value; - ret = hppe_flow_host_tbl_op_data8_set(dev_id, ®_val); - return ret; -} - -sw_error_t -hppe_flow_host_tbl_op_data9_data_get( - a_uint32_t dev_id, - a_uint32_t *value) -{ - union flow_host_tbl_op_data9_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_flow_host_tbl_op_data9_get(dev_id, ®_val); - *value = reg_val.bf.data; - return ret; -} - -sw_error_t -hppe_flow_host_tbl_op_data9_data_set( - a_uint32_t dev_id, - a_uint32_t value) -{ - union flow_host_tbl_op_data9_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_flow_host_tbl_op_data9_get(dev_id, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.data = value; - ret = hppe_flow_host_tbl_op_data9_set(dev_id, ®_val); - return ret; -} - -sw_error_t -hppe_in_flow_tbl_op_rslt_op_rslt_get( - a_uint32_t dev_id, - a_uint32_t *value) -{ - union in_flow_tbl_op_rslt_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_in_flow_tbl_op_rslt_get(dev_id, ®_val); - *value = reg_val.bf.op_rslt; - return ret; -} - -sw_error_t -hppe_in_flow_tbl_op_rslt_op_rslt_set( - a_uint32_t dev_id, - a_uint32_t value) -{ - return SW_NOT_SUPPORTED; -} - -sw_error_t -hppe_in_flow_tbl_op_rslt_valid_cnt_get( - a_uint32_t dev_id, - a_uint32_t *value) -{ - union in_flow_tbl_op_rslt_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_in_flow_tbl_op_rslt_get(dev_id, ®_val); - *value = reg_val.bf.valid_cnt; - return ret; -} - -sw_error_t -hppe_in_flow_tbl_op_rslt_valid_cnt_set( - a_uint32_t dev_id, - a_uint32_t value) -{ - return SW_NOT_SUPPORTED; -} - -sw_error_t -hppe_in_flow_tbl_op_rslt_flow_entry_index_get( - a_uint32_t dev_id, - a_uint32_t *value) -{ - union in_flow_tbl_op_rslt_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_in_flow_tbl_op_rslt_get(dev_id, ®_val); - *value = reg_val.bf.flow_entry_index; - return ret; -} - -sw_error_t -hppe_in_flow_tbl_op_rslt_flow_entry_index_set( - a_uint32_t dev_id, - a_uint32_t value) -{ - return SW_NOT_SUPPORTED; -} - -sw_error_t -hppe_in_flow_tbl_op_rslt_cmd_id_get( - a_uint32_t dev_id, - a_uint32_t *value) -{ - union in_flow_tbl_op_rslt_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_in_flow_tbl_op_rslt_get(dev_id, ®_val); - *value = reg_val.bf.cmd_id; - return ret; -} - -sw_error_t -hppe_in_flow_tbl_op_rslt_cmd_id_set( - a_uint32_t dev_id, - a_uint32_t value) -{ - return SW_NOT_SUPPORTED; -} - -sw_error_t -hppe_flow_host_tbl_op_rslt_host_entry_index_get( - a_uint32_t dev_id, - a_uint32_t *value) -{ - union flow_host_tbl_op_rslt_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_flow_host_tbl_op_rslt_get(dev_id, ®_val); - *value = reg_val.bf.host_entry_index; - return ret; -} - -sw_error_t -hppe_flow_host_tbl_op_rslt_host_entry_index_set( - a_uint32_t dev_id, - a_uint32_t value) -{ - return SW_NOT_SUPPORTED; -} - -sw_error_t -hppe_in_flow_tbl_rd_op_entry_index_get( - a_uint32_t dev_id, - a_uint32_t *value) -{ - union in_flow_tbl_rd_op_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_in_flow_tbl_rd_op_get(dev_id, ®_val); - *value = reg_val.bf.entry_index; - return ret; -} - -sw_error_t -hppe_in_flow_tbl_rd_op_entry_index_set( - a_uint32_t dev_id, - a_uint32_t value) -{ - union in_flow_tbl_rd_op_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_in_flow_tbl_rd_op_get(dev_id, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.entry_index = value; - ret = hppe_in_flow_tbl_rd_op_set(dev_id, ®_val); - return ret; -} - -sw_error_t -hppe_in_flow_tbl_rd_op_cmd_id_get( - a_uint32_t dev_id, - a_uint32_t *value) -{ - union in_flow_tbl_rd_op_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_in_flow_tbl_rd_op_get(dev_id, ®_val); - *value = reg_val.bf.cmd_id; - return ret; -} - -sw_error_t -hppe_in_flow_tbl_rd_op_cmd_id_set( - a_uint32_t dev_id, - a_uint32_t value) -{ - union in_flow_tbl_rd_op_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_in_flow_tbl_rd_op_get(dev_id, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.cmd_id = value; - ret = hppe_in_flow_tbl_rd_op_set(dev_id, ®_val); - return ret; -} - -sw_error_t -hppe_in_flow_tbl_rd_op_byp_rslt_en_get( - a_uint32_t dev_id, - a_uint32_t *value) -{ - union in_flow_tbl_rd_op_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_in_flow_tbl_rd_op_get(dev_id, ®_val); - *value = reg_val.bf.byp_rslt_en; - return ret; -} - -sw_error_t -hppe_in_flow_tbl_rd_op_byp_rslt_en_set( - a_uint32_t dev_id, - a_uint32_t value) -{ - union in_flow_tbl_rd_op_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_in_flow_tbl_rd_op_get(dev_id, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.byp_rslt_en = value; - ret = hppe_in_flow_tbl_rd_op_set(dev_id, ®_val); - return ret; -} - -sw_error_t -hppe_in_flow_tbl_rd_op_op_mode_get( - a_uint32_t dev_id, - a_uint32_t *value) -{ - union in_flow_tbl_rd_op_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_in_flow_tbl_rd_op_get(dev_id, ®_val); - *value = reg_val.bf.op_mode; - return ret; -} - -sw_error_t -hppe_in_flow_tbl_rd_op_op_mode_set( - a_uint32_t dev_id, - a_uint32_t value) -{ - union in_flow_tbl_rd_op_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_in_flow_tbl_rd_op_get(dev_id, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.op_mode = value; - ret = hppe_in_flow_tbl_rd_op_set(dev_id, ®_val); - return ret; -} - -sw_error_t -hppe_in_flow_tbl_rd_op_op_type_get( - a_uint32_t dev_id, - a_uint32_t *value) -{ - union in_flow_tbl_rd_op_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_in_flow_tbl_rd_op_get(dev_id, ®_val); - *value = reg_val.bf.op_type; - return ret; -} - -sw_error_t -hppe_in_flow_tbl_rd_op_op_type_set( - a_uint32_t dev_id, - a_uint32_t value) -{ - union in_flow_tbl_rd_op_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_in_flow_tbl_rd_op_get(dev_id, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.op_type = value; - ret = hppe_in_flow_tbl_rd_op_set(dev_id, ®_val); - return ret; -} - -sw_error_t -hppe_in_flow_tbl_rd_op_op_host_en_get( - a_uint32_t dev_id, - a_uint32_t *value) -{ - union in_flow_tbl_rd_op_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_in_flow_tbl_rd_op_get(dev_id, ®_val); - *value = reg_val.bf.op_host_en; - return ret; -} - -sw_error_t -hppe_in_flow_tbl_rd_op_op_host_en_set( - a_uint32_t dev_id, - a_uint32_t value) -{ - union in_flow_tbl_rd_op_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_in_flow_tbl_rd_op_get(dev_id, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.op_host_en = value; - ret = hppe_in_flow_tbl_rd_op_set(dev_id, ®_val); - return ret; -} - -sw_error_t -hppe_in_flow_tbl_rd_op_op_result_get( - a_uint32_t dev_id, - a_uint32_t *value) -{ - union in_flow_tbl_rd_op_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_in_flow_tbl_rd_op_get(dev_id, ®_val); - *value = reg_val.bf.op_result; - return ret; -} - -sw_error_t -hppe_in_flow_tbl_rd_op_op_result_set( - a_uint32_t dev_id, - a_uint32_t value) -{ - union in_flow_tbl_rd_op_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_in_flow_tbl_rd_op_get(dev_id, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.op_result = value; - ret = hppe_in_flow_tbl_rd_op_set(dev_id, ®_val); - return ret; -} - -sw_error_t -hppe_in_flow_tbl_rd_op_busy_get( - a_uint32_t dev_id, - a_uint32_t *value) -{ - union in_flow_tbl_rd_op_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_in_flow_tbl_rd_op_get(dev_id, ®_val); - *value = reg_val.bf.busy; - return ret; -} - -sw_error_t -hppe_in_flow_tbl_rd_op_busy_set( - a_uint32_t dev_id, - a_uint32_t value) -{ - union in_flow_tbl_rd_op_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_in_flow_tbl_rd_op_get(dev_id, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.busy = value; - ret = hppe_in_flow_tbl_rd_op_set(dev_id, ®_val); - return ret; -} - -sw_error_t -hppe_in_flow_tbl_rd_op_hash_block_bitmap_get( - a_uint32_t dev_id, - a_uint32_t *value) -{ - union in_flow_tbl_rd_op_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_in_flow_tbl_rd_op_get(dev_id, ®_val); - *value = reg_val.bf.hash_block_bitmap; - return ret; -} - -sw_error_t -hppe_in_flow_tbl_rd_op_hash_block_bitmap_set( - a_uint32_t dev_id, - a_uint32_t value) -{ - union in_flow_tbl_rd_op_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_in_flow_tbl_rd_op_get(dev_id, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.hash_block_bitmap = value; - ret = hppe_in_flow_tbl_rd_op_set(dev_id, ®_val); - return ret; -} - -sw_error_t -hppe_in_flow_host_tbl_rd_op_host_entry_index_get( - a_uint32_t dev_id, - a_uint32_t *value) -{ - union in_flow_host_tbl_rd_op_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_in_flow_host_tbl_rd_op_get(dev_id, ®_val); - *value = reg_val.bf.host_entry_index; - return ret; -} - -sw_error_t -hppe_in_flow_host_tbl_rd_op_host_entry_index_set( - a_uint32_t dev_id, - a_uint32_t value) -{ - union in_flow_host_tbl_rd_op_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_in_flow_host_tbl_rd_op_get(dev_id, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.host_entry_index = value; - ret = hppe_in_flow_host_tbl_rd_op_set(dev_id, ®_val); - return ret; -} - -sw_error_t -hppe_in_flow_host_tbl_rd_op_hash_block_bitmap_get( - a_uint32_t dev_id, - a_uint32_t *value) -{ - union in_flow_host_tbl_rd_op_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_in_flow_host_tbl_rd_op_get(dev_id, ®_val); - *value = reg_val.bf.hash_block_bitmap; - return ret; -} - -sw_error_t -hppe_in_flow_host_tbl_rd_op_hash_block_bitmap_set( - a_uint32_t dev_id, - a_uint32_t value) -{ - union in_flow_host_tbl_rd_op_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_in_flow_host_tbl_rd_op_get(dev_id, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.hash_block_bitmap = value; - ret = hppe_in_flow_host_tbl_rd_op_set(dev_id, ®_val); - return ret; -} - -sw_error_t -hppe_in_flow_tbl_rd_op_data0_data_get( - a_uint32_t dev_id, - a_uint32_t *value) -{ - union in_flow_tbl_rd_op_data0_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_in_flow_tbl_rd_op_data0_get(dev_id, ®_val); - *value = reg_val.bf.data; - return ret; -} - -sw_error_t -hppe_in_flow_tbl_rd_op_data0_data_set( - a_uint32_t dev_id, - a_uint32_t value) -{ - union in_flow_tbl_rd_op_data0_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_in_flow_tbl_rd_op_data0_get(dev_id, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.data = value; - ret = hppe_in_flow_tbl_rd_op_data0_set(dev_id, ®_val); - return ret; -} - -sw_error_t -hppe_in_flow_tbl_rd_op_data1_data_get( - a_uint32_t dev_id, - a_uint32_t *value) -{ - union in_flow_tbl_rd_op_data1_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_in_flow_tbl_rd_op_data1_get(dev_id, ®_val); - *value = reg_val.bf.data; - return ret; -} - -sw_error_t -hppe_in_flow_tbl_rd_op_data1_data_set( - a_uint32_t dev_id, - a_uint32_t value) -{ - union in_flow_tbl_rd_op_data1_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_in_flow_tbl_rd_op_data1_get(dev_id, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.data = value; - ret = hppe_in_flow_tbl_rd_op_data1_set(dev_id, ®_val); - return ret; -} - -sw_error_t -hppe_in_flow_tbl_rd_op_data2_data_get( - a_uint32_t dev_id, - a_uint32_t *value) -{ - union in_flow_tbl_rd_op_data2_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_in_flow_tbl_rd_op_data2_get(dev_id, ®_val); - *value = reg_val.bf.data; - return ret; -} - -sw_error_t -hppe_in_flow_tbl_rd_op_data2_data_set( - a_uint32_t dev_id, - a_uint32_t value) -{ - union in_flow_tbl_rd_op_data2_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_in_flow_tbl_rd_op_data2_get(dev_id, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.data = value; - ret = hppe_in_flow_tbl_rd_op_data2_set(dev_id, ®_val); - return ret; -} - -sw_error_t -hppe_in_flow_tbl_rd_op_data3_data_get( - a_uint32_t dev_id, - a_uint32_t *value) -{ - union in_flow_tbl_rd_op_data3_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_in_flow_tbl_rd_op_data3_get(dev_id, ®_val); - *value = reg_val.bf.data; - return ret; -} - -sw_error_t -hppe_in_flow_tbl_rd_op_data3_data_set( - a_uint32_t dev_id, - a_uint32_t value) -{ - union in_flow_tbl_rd_op_data3_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_in_flow_tbl_rd_op_data3_get(dev_id, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.data = value; - ret = hppe_in_flow_tbl_rd_op_data3_set(dev_id, ®_val); - return ret; -} - -sw_error_t -hppe_in_flow_tbl_rd_op_data4_data_get( - a_uint32_t dev_id, - a_uint32_t *value) -{ - union in_flow_tbl_rd_op_data4_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_in_flow_tbl_rd_op_data4_get(dev_id, ®_val); - *value = reg_val.bf.data; - return ret; -} - -sw_error_t -hppe_in_flow_tbl_rd_op_data4_data_set( - a_uint32_t dev_id, - a_uint32_t value) -{ - union in_flow_tbl_rd_op_data4_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_in_flow_tbl_rd_op_data4_get(dev_id, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.data = value; - ret = hppe_in_flow_tbl_rd_op_data4_set(dev_id, ®_val); - return ret; -} - -sw_error_t -hppe_in_flow_tbl_rd_op_data5_data_get( - a_uint32_t dev_id, - a_uint32_t *value) -{ - union in_flow_tbl_rd_op_data5_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_in_flow_tbl_rd_op_data5_get(dev_id, ®_val); - *value = reg_val.bf.data; - return ret; -} - -sw_error_t -hppe_in_flow_tbl_rd_op_data5_data_set( - a_uint32_t dev_id, - a_uint32_t value) -{ - union in_flow_tbl_rd_op_data5_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_in_flow_tbl_rd_op_data5_get(dev_id, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.data = value; - ret = hppe_in_flow_tbl_rd_op_data5_set(dev_id, ®_val); - return ret; -} - -sw_error_t -hppe_in_flow_tbl_rd_op_data6_data_get( - a_uint32_t dev_id, - a_uint32_t *value) -{ - union in_flow_tbl_rd_op_data6_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_in_flow_tbl_rd_op_data6_get(dev_id, ®_val); - *value = reg_val.bf.data; - return ret; -} - -sw_error_t -hppe_in_flow_tbl_rd_op_data6_data_set( - a_uint32_t dev_id, - a_uint32_t value) -{ - union in_flow_tbl_rd_op_data6_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_in_flow_tbl_rd_op_data6_get(dev_id, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.data = value; - ret = hppe_in_flow_tbl_rd_op_data6_set(dev_id, ®_val); - return ret; -} - -sw_error_t -hppe_in_flow_tbl_rd_op_data7_data_get( - a_uint32_t dev_id, - a_uint32_t *value) -{ - union in_flow_tbl_rd_op_data7_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_in_flow_tbl_rd_op_data7_get(dev_id, ®_val); - *value = reg_val.bf.data; - return ret; -} - -sw_error_t -hppe_in_flow_tbl_rd_op_data7_data_set( - a_uint32_t dev_id, - a_uint32_t value) -{ - union in_flow_tbl_rd_op_data7_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_in_flow_tbl_rd_op_data7_get(dev_id, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.data = value; - ret = hppe_in_flow_tbl_rd_op_data7_set(dev_id, ®_val); - return ret; -} - -sw_error_t -hppe_in_flow_tbl_rd_op_data8_data_get( - a_uint32_t dev_id, - a_uint32_t *value) -{ - union in_flow_tbl_rd_op_data8_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_in_flow_tbl_rd_op_data8_get(dev_id, ®_val); - *value = reg_val.bf.data; - return ret; -} - -sw_error_t -hppe_in_flow_tbl_rd_op_data8_data_set( - a_uint32_t dev_id, - a_uint32_t value) -{ - union in_flow_tbl_rd_op_data8_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_in_flow_tbl_rd_op_data8_get(dev_id, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.data = value; - ret = hppe_in_flow_tbl_rd_op_data8_set(dev_id, ®_val); - return ret; -} - -sw_error_t -hppe_flow_host_tbl_rd_op_data0_data_get( - a_uint32_t dev_id, - a_uint32_t *value) -{ - union flow_host_tbl_rd_op_data0_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_flow_host_tbl_rd_op_data0_get(dev_id, ®_val); - *value = reg_val.bf.data; - return ret; -} - -sw_error_t -hppe_flow_host_tbl_rd_op_data0_data_set( - a_uint32_t dev_id, - a_uint32_t value) -{ - union flow_host_tbl_rd_op_data0_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_flow_host_tbl_rd_op_data0_get(dev_id, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.data = value; - ret = hppe_flow_host_tbl_rd_op_data0_set(dev_id, ®_val); - return ret; -} - -sw_error_t -hppe_flow_host_tbl_rd_op_data1_data_get( - a_uint32_t dev_id, - a_uint32_t *value) -{ - union flow_host_tbl_rd_op_data1_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_flow_host_tbl_rd_op_data1_get(dev_id, ®_val); - *value = reg_val.bf.data; - return ret; -} - -sw_error_t -hppe_flow_host_tbl_rd_op_data1_data_set( - a_uint32_t dev_id, - a_uint32_t value) -{ - union flow_host_tbl_rd_op_data1_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_flow_host_tbl_rd_op_data1_get(dev_id, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.data = value; - ret = hppe_flow_host_tbl_rd_op_data1_set(dev_id, ®_val); - return ret; -} - -sw_error_t -hppe_flow_host_tbl_rd_op_data2_data_get( - a_uint32_t dev_id, - a_uint32_t *value) -{ - union flow_host_tbl_rd_op_data2_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_flow_host_tbl_rd_op_data2_get(dev_id, ®_val); - *value = reg_val.bf.data; - return ret; -} - -sw_error_t -hppe_flow_host_tbl_rd_op_data2_data_set( - a_uint32_t dev_id, - a_uint32_t value) -{ - union flow_host_tbl_rd_op_data2_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_flow_host_tbl_rd_op_data2_get(dev_id, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.data = value; - ret = hppe_flow_host_tbl_rd_op_data2_set(dev_id, ®_val); - return ret; -} - -sw_error_t -hppe_flow_host_tbl_rd_op_data3_data_get( - a_uint32_t dev_id, - a_uint32_t *value) -{ - union flow_host_tbl_rd_op_data3_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_flow_host_tbl_rd_op_data3_get(dev_id, ®_val); - *value = reg_val.bf.data; - return ret; -} - -sw_error_t -hppe_flow_host_tbl_rd_op_data3_data_set( - a_uint32_t dev_id, - a_uint32_t value) -{ - union flow_host_tbl_rd_op_data3_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_flow_host_tbl_rd_op_data3_get(dev_id, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.data = value; - ret = hppe_flow_host_tbl_rd_op_data3_set(dev_id, ®_val); - return ret; -} - -sw_error_t -hppe_flow_host_tbl_rd_op_data4_data_get( - a_uint32_t dev_id, - a_uint32_t *value) -{ - union flow_host_tbl_rd_op_data4_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_flow_host_tbl_rd_op_data4_get(dev_id, ®_val); - *value = reg_val.bf.data; - return ret; -} - -sw_error_t -hppe_flow_host_tbl_rd_op_data4_data_set( - a_uint32_t dev_id, - a_uint32_t value) -{ - union flow_host_tbl_rd_op_data4_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_flow_host_tbl_rd_op_data4_get(dev_id, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.data = value; - ret = hppe_flow_host_tbl_rd_op_data4_set(dev_id, ®_val); - return ret; -} - -sw_error_t -hppe_flow_host_tbl_rd_op_data5_data_get( - a_uint32_t dev_id, - a_uint32_t *value) -{ - union flow_host_tbl_rd_op_data5_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_flow_host_tbl_rd_op_data5_get(dev_id, ®_val); - *value = reg_val.bf.data; - return ret; -} - -sw_error_t -hppe_flow_host_tbl_rd_op_data5_data_set( - a_uint32_t dev_id, - a_uint32_t value) -{ - union flow_host_tbl_rd_op_data5_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_flow_host_tbl_rd_op_data5_get(dev_id, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.data = value; - ret = hppe_flow_host_tbl_rd_op_data5_set(dev_id, ®_val); - return ret; -} - -sw_error_t -hppe_flow_host_tbl_rd_op_data6_data_get( - a_uint32_t dev_id, - a_uint32_t *value) -{ - union flow_host_tbl_rd_op_data6_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_flow_host_tbl_rd_op_data6_get(dev_id, ®_val); - *value = reg_val.bf.data; - return ret; -} - -sw_error_t -hppe_flow_host_tbl_rd_op_data6_data_set( - a_uint32_t dev_id, - a_uint32_t value) -{ - union flow_host_tbl_rd_op_data6_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_flow_host_tbl_rd_op_data6_get(dev_id, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.data = value; - ret = hppe_flow_host_tbl_rd_op_data6_set(dev_id, ®_val); - return ret; -} - -sw_error_t -hppe_flow_host_tbl_rd_op_data7_data_get( - a_uint32_t dev_id, - a_uint32_t *value) -{ - union flow_host_tbl_rd_op_data7_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_flow_host_tbl_rd_op_data7_get(dev_id, ®_val); - *value = reg_val.bf.data; - return ret; -} - -sw_error_t -hppe_flow_host_tbl_rd_op_data7_data_set( - a_uint32_t dev_id, - a_uint32_t value) -{ - union flow_host_tbl_rd_op_data7_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_flow_host_tbl_rd_op_data7_get(dev_id, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.data = value; - ret = hppe_flow_host_tbl_rd_op_data7_set(dev_id, ®_val); - return ret; -} - -sw_error_t -hppe_flow_host_tbl_rd_op_data8_data_get( - a_uint32_t dev_id, - a_uint32_t *value) -{ - union flow_host_tbl_rd_op_data8_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_flow_host_tbl_rd_op_data8_get(dev_id, ®_val); - *value = reg_val.bf.data; - return ret; -} - -sw_error_t -hppe_flow_host_tbl_rd_op_data8_data_set( - a_uint32_t dev_id, - a_uint32_t value) -{ - union flow_host_tbl_rd_op_data8_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_flow_host_tbl_rd_op_data8_get(dev_id, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.data = value; - ret = hppe_flow_host_tbl_rd_op_data8_set(dev_id, ®_val); - return ret; -} - -sw_error_t -hppe_flow_host_tbl_rd_op_data9_data_get( - a_uint32_t dev_id, - a_uint32_t *value) -{ - union flow_host_tbl_rd_op_data9_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_flow_host_tbl_rd_op_data9_get(dev_id, ®_val); - *value = reg_val.bf.data; - return ret; -} - -sw_error_t -hppe_flow_host_tbl_rd_op_data9_data_set( - a_uint32_t dev_id, - a_uint32_t value) -{ - union flow_host_tbl_rd_op_data9_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_flow_host_tbl_rd_op_data9_get(dev_id, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.data = value; - ret = hppe_flow_host_tbl_rd_op_data9_set(dev_id, ®_val); - return ret; -} - -sw_error_t -hppe_in_flow_tbl_rd_op_rslt_op_rslt_get( - a_uint32_t dev_id, - a_uint32_t *value) -{ - union in_flow_tbl_rd_op_rslt_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_in_flow_tbl_rd_op_rslt_get(dev_id, ®_val); - *value = reg_val.bf.op_rslt; - return ret; -} - -sw_error_t -hppe_in_flow_tbl_rd_op_rslt_op_rslt_set( - a_uint32_t dev_id, - a_uint32_t value) -{ - return SW_NOT_SUPPORTED; -} - -sw_error_t -hppe_in_flow_tbl_rd_op_rslt_valid_cnt_get( - a_uint32_t dev_id, - a_uint32_t *value) -{ - union in_flow_tbl_rd_op_rslt_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_in_flow_tbl_rd_op_rslt_get(dev_id, ®_val); - *value = reg_val.bf.valid_cnt; - return ret; -} - -sw_error_t -hppe_in_flow_tbl_rd_op_rslt_valid_cnt_set( - a_uint32_t dev_id, - a_uint32_t value) -{ - return SW_NOT_SUPPORTED; -} - -sw_error_t -hppe_in_flow_tbl_rd_op_rslt_flow_entry_index_get( - a_uint32_t dev_id, - a_uint32_t *value) -{ - union in_flow_tbl_rd_op_rslt_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_in_flow_tbl_rd_op_rslt_get(dev_id, ®_val); - *value = reg_val.bf.flow_entry_index; - return ret; -} - -sw_error_t -hppe_in_flow_tbl_rd_op_rslt_flow_entry_index_set( - a_uint32_t dev_id, - a_uint32_t value) -{ - return SW_NOT_SUPPORTED; -} - -sw_error_t -hppe_in_flow_tbl_rd_op_rslt_cmd_id_get( - a_uint32_t dev_id, - a_uint32_t *value) -{ - union in_flow_tbl_rd_op_rslt_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_in_flow_tbl_rd_op_rslt_get(dev_id, ®_val); - *value = reg_val.bf.cmd_id; - return ret; -} - -sw_error_t -hppe_in_flow_tbl_rd_op_rslt_cmd_id_set( - a_uint32_t dev_id, - a_uint32_t value) -{ - return SW_NOT_SUPPORTED; -} - -sw_error_t -hppe_flow_host_tbl_rd_op_rslt_host_entry_index_get( - a_uint32_t dev_id, - a_uint32_t *value) -{ - union flow_host_tbl_rd_op_rslt_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_flow_host_tbl_rd_op_rslt_get(dev_id, ®_val); - *value = reg_val.bf.host_entry_index; - return ret; -} - -sw_error_t -hppe_flow_host_tbl_rd_op_rslt_host_entry_index_set( - a_uint32_t dev_id, - a_uint32_t value) -{ - return SW_NOT_SUPPORTED; -} - -sw_error_t -hppe_in_flow_tbl_rd_rslt_data0_data_get( - a_uint32_t dev_id, - a_uint32_t *value) -{ - union in_flow_tbl_rd_rslt_data0_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_in_flow_tbl_rd_rslt_data0_get(dev_id, ®_val); - *value = reg_val.bf.data; - return ret; -} - -sw_error_t -hppe_in_flow_tbl_rd_rslt_data0_data_set( - a_uint32_t dev_id, - a_uint32_t value) -{ - return SW_NOT_SUPPORTED; -} - -sw_error_t -hppe_in_flow_tbl_rd_rslt_data1_data_get( - a_uint32_t dev_id, - a_uint32_t *value) -{ - union in_flow_tbl_rd_rslt_data1_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_in_flow_tbl_rd_rslt_data1_get(dev_id, ®_val); - *value = reg_val.bf.data; - return ret; -} - -sw_error_t -hppe_in_flow_tbl_rd_rslt_data1_data_set( - a_uint32_t dev_id, - a_uint32_t value) -{ - return SW_NOT_SUPPORTED; -} - -sw_error_t -hppe_in_flow_tbl_rd_rslt_data2_data_get( - a_uint32_t dev_id, - a_uint32_t *value) -{ - union in_flow_tbl_rd_rslt_data2_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_in_flow_tbl_rd_rslt_data2_get(dev_id, ®_val); - *value = reg_val.bf.data; - return ret; -} - -sw_error_t -hppe_in_flow_tbl_rd_rslt_data2_data_set( - a_uint32_t dev_id, - a_uint32_t value) -{ - return SW_NOT_SUPPORTED; -} - -sw_error_t -hppe_in_flow_tbl_rd_rslt_data3_data_get( - a_uint32_t dev_id, - a_uint32_t *value) -{ - union in_flow_tbl_rd_rslt_data3_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_in_flow_tbl_rd_rslt_data3_get(dev_id, ®_val); - *value = reg_val.bf.data; - return ret; -} - -sw_error_t -hppe_in_flow_tbl_rd_rslt_data3_data_set( - a_uint32_t dev_id, - a_uint32_t value) -{ - return SW_NOT_SUPPORTED; -} - -sw_error_t -hppe_in_flow_tbl_rd_rslt_data4_data_get( - a_uint32_t dev_id, - a_uint32_t *value) -{ - union in_flow_tbl_rd_rslt_data4_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_in_flow_tbl_rd_rslt_data4_get(dev_id, ®_val); - *value = reg_val.bf.data; - return ret; -} - -sw_error_t -hppe_in_flow_tbl_rd_rslt_data4_data_set( - a_uint32_t dev_id, - a_uint32_t value) -{ - return SW_NOT_SUPPORTED; -} - -sw_error_t -hppe_in_flow_tbl_rd_rslt_data5_data_get( - a_uint32_t dev_id, - a_uint32_t *value) -{ - union in_flow_tbl_rd_rslt_data5_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_in_flow_tbl_rd_rslt_data5_get(dev_id, ®_val); - *value = reg_val.bf.data; - return ret; -} - -sw_error_t -hppe_in_flow_tbl_rd_rslt_data5_data_set( - a_uint32_t dev_id, - a_uint32_t value) -{ - return SW_NOT_SUPPORTED; -} - -sw_error_t -hppe_in_flow_tbl_rd_rslt_data6_data_get( - a_uint32_t dev_id, - a_uint32_t *value) -{ - union in_flow_tbl_rd_rslt_data6_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_in_flow_tbl_rd_rslt_data6_get(dev_id, ®_val); - *value = reg_val.bf.data; - return ret; -} - -sw_error_t -hppe_in_flow_tbl_rd_rslt_data6_data_set( - a_uint32_t dev_id, - a_uint32_t value) -{ - return SW_NOT_SUPPORTED; -} - -sw_error_t -hppe_in_flow_tbl_rd_rslt_data7_data_get( - a_uint32_t dev_id, - a_uint32_t *value) -{ - union in_flow_tbl_rd_rslt_data7_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_in_flow_tbl_rd_rslt_data7_get(dev_id, ®_val); - *value = reg_val.bf.data; - return ret; -} - -sw_error_t -hppe_in_flow_tbl_rd_rslt_data7_data_set( - a_uint32_t dev_id, - a_uint32_t value) -{ - return SW_NOT_SUPPORTED; -} - -sw_error_t -hppe_in_flow_tbl_rd_rslt_data8_data_get( - a_uint32_t dev_id, - a_uint32_t *value) -{ - union in_flow_tbl_rd_rslt_data8_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_in_flow_tbl_rd_rslt_data8_get(dev_id, ®_val); - *value = reg_val.bf.data; - return ret; -} - -sw_error_t -hppe_in_flow_tbl_rd_rslt_data8_data_set( - a_uint32_t dev_id, - a_uint32_t value) -{ - return SW_NOT_SUPPORTED; -} - -sw_error_t -hppe_flow_host_tbl_rd_rslt_data0_data_get( - a_uint32_t dev_id, - a_uint32_t *value) -{ - union flow_host_tbl_rd_rslt_data0_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_flow_host_tbl_rd_rslt_data0_get(dev_id, ®_val); - *value = reg_val.bf.data; - return ret; -} - -sw_error_t -hppe_flow_host_tbl_rd_rslt_data0_data_set( - a_uint32_t dev_id, - a_uint32_t value) -{ - return SW_NOT_SUPPORTED; -} - -sw_error_t -hppe_flow_host_tbl_rd_rslt_data1_data_get( - a_uint32_t dev_id, - a_uint32_t *value) -{ - union flow_host_tbl_rd_rslt_data1_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_flow_host_tbl_rd_rslt_data1_get(dev_id, ®_val); - *value = reg_val.bf.data; - return ret; -} - -sw_error_t -hppe_flow_host_tbl_rd_rslt_data1_data_set( - a_uint32_t dev_id, - a_uint32_t value) -{ - return SW_NOT_SUPPORTED; -} - -sw_error_t -hppe_flow_host_tbl_rd_rslt_data2_data_get( - a_uint32_t dev_id, - a_uint32_t *value) -{ - union flow_host_tbl_rd_rslt_data2_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_flow_host_tbl_rd_rslt_data2_get(dev_id, ®_val); - *value = reg_val.bf.data; - return ret; -} - -sw_error_t -hppe_flow_host_tbl_rd_rslt_data2_data_set( - a_uint32_t dev_id, - a_uint32_t value) -{ - return SW_NOT_SUPPORTED; -} - -sw_error_t -hppe_flow_host_tbl_rd_rslt_data3_data_get( - a_uint32_t dev_id, - a_uint32_t *value) -{ - union flow_host_tbl_rd_rslt_data3_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_flow_host_tbl_rd_rslt_data3_get(dev_id, ®_val); - *value = reg_val.bf.data; - return ret; -} - -sw_error_t -hppe_flow_host_tbl_rd_rslt_data3_data_set( - a_uint32_t dev_id, - a_uint32_t value) -{ - return SW_NOT_SUPPORTED; -} - -sw_error_t -hppe_flow_host_tbl_rd_rslt_data4_data_get( - a_uint32_t dev_id, - a_uint32_t *value) -{ - union flow_host_tbl_rd_rslt_data4_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_flow_host_tbl_rd_rslt_data4_get(dev_id, ®_val); - *value = reg_val.bf.data; - return ret; -} - -sw_error_t -hppe_flow_host_tbl_rd_rslt_data4_data_set( - a_uint32_t dev_id, - a_uint32_t value) -{ - return SW_NOT_SUPPORTED; -} - -sw_error_t -hppe_flow_host_tbl_rd_rslt_data5_data_get( - a_uint32_t dev_id, - a_uint32_t *value) -{ - union flow_host_tbl_rd_rslt_data5_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_flow_host_tbl_rd_rslt_data5_get(dev_id, ®_val); - *value = reg_val.bf.data; - return ret; -} - -sw_error_t -hppe_flow_host_tbl_rd_rslt_data5_data_set( - a_uint32_t dev_id, - a_uint32_t value) -{ - return SW_NOT_SUPPORTED; -} - -sw_error_t -hppe_flow_host_tbl_rd_rslt_data6_data_get( - a_uint32_t dev_id, - a_uint32_t *value) -{ - union flow_host_tbl_rd_rslt_data6_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_flow_host_tbl_rd_rslt_data6_get(dev_id, ®_val); - *value = reg_val.bf.data; - return ret; -} - -sw_error_t -hppe_flow_host_tbl_rd_rslt_data6_data_set( - a_uint32_t dev_id, - a_uint32_t value) -{ - return SW_NOT_SUPPORTED; -} - -sw_error_t -hppe_flow_host_tbl_rd_rslt_data7_data_get( - a_uint32_t dev_id, - a_uint32_t *value) -{ - union flow_host_tbl_rd_rslt_data7_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_flow_host_tbl_rd_rslt_data7_get(dev_id, ®_val); - *value = reg_val.bf.data; - return ret; -} - -sw_error_t -hppe_flow_host_tbl_rd_rslt_data7_data_set( - a_uint32_t dev_id, - a_uint32_t value) -{ - return SW_NOT_SUPPORTED; -} - -sw_error_t -hppe_flow_host_tbl_rd_rslt_data8_data_get( - a_uint32_t dev_id, - a_uint32_t *value) -{ - union flow_host_tbl_rd_rslt_data8_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_flow_host_tbl_rd_rslt_data8_get(dev_id, ®_val); - *value = reg_val.bf.data; - return ret; -} - -sw_error_t -hppe_flow_host_tbl_rd_rslt_data8_data_set( - a_uint32_t dev_id, - a_uint32_t value) -{ - return SW_NOT_SUPPORTED; -} - -sw_error_t -hppe_flow_host_tbl_rd_rslt_data9_data_get( - a_uint32_t dev_id, - a_uint32_t *value) -{ - union flow_host_tbl_rd_rslt_data9_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_flow_host_tbl_rd_rslt_data9_get(dev_id, ®_val); - *value = reg_val.bf.data; - return ret; -} - -sw_error_t -hppe_flow_host_tbl_rd_rslt_data9_data_set( - a_uint32_t dev_id, - a_uint32_t value) -{ - return SW_NOT_SUPPORTED; -} - -sw_error_t -hppe_eg_flow_tree_map_tbl_tree_id_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union eg_flow_tree_map_tbl_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_eg_flow_tree_map_tbl_get(dev_id, index, ®_val); - *value = reg_val.bf.tree_id; - return ret; -} - -sw_error_t -hppe_eg_flow_tree_map_tbl_tree_id_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - union eg_flow_tree_map_tbl_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_eg_flow_tree_map_tbl_get(dev_id, index, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.tree_id = value; - ret = hppe_eg_flow_tree_map_tbl_set(dev_id, index, ®_val); - return ret; -} - -sw_error_t -hppe_in_flow_cnt_tbl_hit_byte_counter_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint64_t *value) -{ - union in_flow_cnt_tbl_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_in_flow_cnt_tbl_get(dev_id, index, ®_val); - *value = (a_uint64_t)reg_val.bf.hit_byte_counter_1 << 32 | \ - reg_val.bf.hit_byte_counter_0; - return ret; -} - -sw_error_t -hppe_in_flow_cnt_tbl_hit_byte_counter_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint64_t value) -{ - union in_flow_cnt_tbl_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_in_flow_cnt_tbl_get(dev_id, index, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.hit_byte_counter_1 = value >> 32; - reg_val.bf.hit_byte_counter_0 = value & (((a_uint64_t)1<<32)-1); - ret = hppe_in_flow_cnt_tbl_set(dev_id, index, ®_val); - return ret; -} - -sw_error_t -hppe_in_flow_cnt_tbl_hit_pkt_counter_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union in_flow_cnt_tbl_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_in_flow_cnt_tbl_get(dev_id, index, ®_val); - *value = reg_val.bf.hit_pkt_counter; - return ret; -} - -sw_error_t -hppe_in_flow_cnt_tbl_hit_pkt_counter_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - union in_flow_cnt_tbl_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_in_flow_cnt_tbl_get(dev_id, index, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.hit_pkt_counter = value; - ret = hppe_in_flow_cnt_tbl_set(dev_id, index, ®_val); - return ret; -} - - -sw_error_t -hppe_flow_get_common( - a_uint32_t dev_id, - a_uint32_t op_mode, - a_uint32_t *index, - a_uint32_t *data, - a_uint32_t num) -{ - union in_flow_tbl_rd_op_u op; - union in_flow_tbl_rd_op_rslt_u result; - a_uint32_t i = 0x100; - sw_error_t rv; - - op.bf.cmd_id = flow_cmd_id; - flow_cmd_id++; - op.bf.byp_rslt_en = 0; - op.bf.op_type = 2; - op.bf.hash_block_bitmap = 3; - op.bf.op_mode = op_mode; - op.bf.entry_index = *index; - op.bf.op_host_en = 0; - - rv = hppe_in_flow_tbl_rd_op_set(dev_id, &op); - if (SW_OK != rv) - return rv; - rv = hppe_in_flow_tbl_rd_op_rslt_get(dev_id, &result); - if (SW_OK != rv) - return rv; - while (!result.bf.valid_cnt && --i) { - hppe_in_flow_tbl_rd_op_rslt_get(dev_id, &result); - } - if (i == 0) - return SW_BUSY; - if (result.bf.op_rslt == 0) { - hppe_reg_tbl_get( - dev_id, - IPE_L3_BASE_ADDR + IN_FLOW_TBL_RD_RSLT_DATA0_ADDRESS, - data, num); - *index = result.bf.flow_entry_index; - return SW_OK; - } - else - return SW_FAIL; - -} - - -sw_error_t -hppe_flow_flush_common(a_uint32_t dev_id) -{ - union in_flow_tbl_op_u op; - union in_flow_tbl_op_rslt_u result; - a_uint32_t i = 0x100 * 50; - sw_error_t rv; - - op.bf.cmd_id = flow_cmd_id; - flow_cmd_id++; - op.bf.byp_rslt_en = 0; - op.bf.op_type = 3; - op.bf.hash_block_bitmap = 3; - op.bf.op_mode = 0; - op.bf.op_host_en = 0; - - rv = hppe_in_flow_tbl_op_set(dev_id, &op); - if (SW_OK != rv) - return rv; - rv = hppe_in_flow_tbl_op_rslt_get(dev_id, &result); - if (SW_OK != rv) - return rv; - while (!result.bf.valid_cnt && --i) { - hppe_in_flow_tbl_op_rslt_get(dev_id, &result); - } - if (i == 0) - return SW_BUSY; - if (result.bf.op_rslt == 0) - return SW_OK; - else - return SW_FAIL; - - -} - -sw_error_t -hppe_flow_op_common( - a_uint32_t dev_id, - a_uint32_t op_type, - a_uint32_t op_mode, - a_uint32_t *index) -{ - union in_flow_tbl_op_u op; - union in_flow_tbl_op_rslt_u result; - a_uint32_t i = 0x100; - sw_error_t rv; - - op.bf.cmd_id = flow_cmd_id; - flow_cmd_id++; - op.bf.byp_rslt_en = 0; - op.bf.op_type = op_type; - op.bf.hash_block_bitmap = 3; - op.bf.op_mode = op_mode; - op.bf.entry_index = *index; - op.bf.op_host_en = 0; - - rv = hppe_in_flow_tbl_op_set(dev_id, &op); - if (SW_OK != rv) - return rv; - rv = hppe_in_flow_tbl_op_rslt_get(dev_id, &result); - if (SW_OK != rv) - return rv; - while (!result.bf.valid_cnt && --i) { - hppe_in_flow_tbl_op_rslt_get(dev_id, &result); - } - if (i == 0) - return SW_BUSY; - if (result.bf.op_rslt == 0) { - *index = result.bf.flow_entry_index; - return SW_OK; - } - else - return SW_FAIL; - -} - -#include "hppe_ip_reg.h" - -sw_error_t -hppe_flow_host_get_common( - a_uint32_t dev_id, - a_uint32_t op_mode, - a_uint32_t *index, - a_uint32_t *data, - a_uint32_t num) -{ - union in_flow_tbl_rd_op_u op; - union in_flow_tbl_rd_op_rslt_u result; - a_uint32_t i = 0x100; - sw_error_t rv; - - op.bf.cmd_id = flow_host_cmd_id; - flow_host_cmd_id++; - op.bf.byp_rslt_en = 0; - op.bf.op_type = 2; - op.bf.hash_block_bitmap = 3; - op.bf.op_mode = op_mode; - op.bf.entry_index = *index; - op.bf.op_host_en = 1; - - rv = hppe_in_flow_tbl_rd_op_set(dev_id, &op); - if (SW_OK != rv) - return rv; - rv = hppe_in_flow_tbl_rd_op_rslt_get(dev_id, &result); - if (SW_OK != rv) - return rv; - while (!result.bf.valid_cnt && --i) { - hppe_in_flow_tbl_rd_op_rslt_get(dev_id, &result); - } - if (i == 0) - return SW_BUSY; - - if (result.bf.op_rslt == 0) { - hppe_reg_tbl_get( - dev_id, - IPE_L3_BASE_ADDR + IN_FLOW_TBL_RD_RSLT_DATA0_ADDRESS, - data, num); - *index = result.bf.flow_entry_index; - return SW_OK; - } - else - return SW_FAIL; -} - -sw_error_t -hppe_flow_host_flush_common(a_uint32_t dev_id) -{ - union in_flow_tbl_op_u op; - union in_flow_tbl_op_rslt_u result; - a_uint32_t i = 0x100 * 50; - sw_error_t rv; - - op.bf.cmd_id = flow_host_cmd_id; - flow_host_cmd_id++; - op.bf.byp_rslt_en = 0; - op.bf.op_type = 3; - op.bf.hash_block_bitmap = 3; - op.bf.op_mode = 0; - op.bf.op_host_en = 1; - - rv = hppe_in_flow_tbl_op_set(dev_id, &op); - if (SW_OK != rv) - return rv; - rv = hppe_in_flow_tbl_op_rslt_get(dev_id, &result); - if (SW_OK != rv) - return rv; - while (!result.bf.valid_cnt && --i) { - hppe_in_flow_tbl_op_rslt_get(dev_id, &result); - } - if (i == 0) - return SW_BUSY; - if (result.bf.op_rslt == 0) - return SW_OK; - else - return SW_FAIL; -} - -sw_error_t -hppe_flow_host_op_both_common( - a_uint32_t dev_id, - a_uint32_t op_type, - a_uint32_t op_mode, - a_uint32_t *index) -{ - union in_flow_tbl_op_u op; - union in_flow_tbl_op_rslt_u result; - a_uint32_t i = 0x100; - sw_error_t rv; - - op.bf.cmd_id = flow_host_cmd_id; - flow_host_cmd_id++; - op.bf.byp_rslt_en = 0; - op.bf.op_type = op_type; - op.bf.hash_block_bitmap = 3; - op.bf.op_mode = op_mode; - op.bf.entry_index = *index; - op.bf.op_host_en = 1; - - rv = hppe_in_flow_tbl_op_set(dev_id, &op); - if (SW_OK != rv) - return rv; - rv = hppe_in_flow_tbl_op_rslt_get(dev_id, &result); - if (SW_OK != rv) - return rv; - while (!result.bf.valid_cnt && --i) { - hppe_in_flow_tbl_op_rslt_get(dev_id, &result); - } - if (i == 0) - return SW_BUSY; - if (result.bf.op_rslt == 0) { - *index = result.bf.flow_entry_index; - return SW_OK; - } - else - return SW_FAIL; -} - -sw_error_t -hppe_flow_entry_host_op_ipv4_5tuple_add( - a_uint32_t dev_id, a_uint32_t op_mode, - a_uint32_t *index, union in_flow_tbl_u *entry) -{ - hppe_in_flow_tbl_op_data0_set(dev_id, (union in_flow_tbl_op_data0_u *)(&entry->val[0])); - hppe_in_flow_tbl_op_data1_set(dev_id, (union in_flow_tbl_op_data1_u *)(&entry->val[1])); - hppe_in_flow_tbl_op_data2_set(dev_id, (union in_flow_tbl_op_data2_u *)(&entry->val[2])); - hppe_in_flow_tbl_op_data3_set(dev_id, (union in_flow_tbl_op_data3_u *)(&entry->val[3])); - hppe_in_flow_tbl_op_data4_set(dev_id, (union in_flow_tbl_op_data4_u *)(&entry->val[4])); - return hppe_flow_host_op_both_common(dev_id, 0, op_mode, index); -} - -sw_error_t -hppe_flow_entry_host_op_ipv4_3tuple_add( - a_uint32_t dev_id, a_uint32_t op_mode, - a_uint32_t *index, union in_flow_3tuple_tbl_u *entry) -{ - hppe_in_flow_tbl_op_data0_set(dev_id, (union in_flow_tbl_op_data0_u *)(&entry->val[0])); - hppe_in_flow_tbl_op_data1_set(dev_id, (union in_flow_tbl_op_data1_u *)(&entry->val[1])); - hppe_in_flow_tbl_op_data2_set(dev_id, (union in_flow_tbl_op_data2_u *)(&entry->val[2])); - hppe_in_flow_tbl_op_data3_set(dev_id, (union in_flow_tbl_op_data3_u *)(&entry->val[3])); - hppe_in_flow_tbl_op_data4_set(dev_id, (union in_flow_tbl_op_data4_u *)(&entry->val[4])); - return hppe_flow_host_op_both_common(dev_id, 0, op_mode, index); -} - -sw_error_t -hppe_flow_entry_host_op_ipv6_5tuple_add( - a_uint32_t dev_id, a_uint32_t op_mode, - a_uint32_t *index, union in_flow_ipv6_5tuple_tbl_u *entry) -{ - hppe_in_flow_tbl_op_data0_set(dev_id, (union in_flow_tbl_op_data0_u *)(&entry->val[0])); - hppe_in_flow_tbl_op_data1_set(dev_id, (union in_flow_tbl_op_data1_u *)(&entry->val[1])); - hppe_in_flow_tbl_op_data2_set(dev_id, (union in_flow_tbl_op_data2_u *)(&entry->val[2])); - hppe_in_flow_tbl_op_data3_set(dev_id, (union in_flow_tbl_op_data3_u *)(&entry->val[3])); - hppe_in_flow_tbl_op_data4_set(dev_id, (union in_flow_tbl_op_data4_u *)(&entry->val[4])); - hppe_in_flow_tbl_op_data5_set(dev_id, (union in_flow_tbl_op_data5_u *)(&entry->val[5])); - hppe_in_flow_tbl_op_data6_set(dev_id, (union in_flow_tbl_op_data6_u *)(&entry->val[6])); - hppe_in_flow_tbl_op_data7_set(dev_id, (union in_flow_tbl_op_data7_u *)(&entry->val[7])); - hppe_in_flow_tbl_op_data8_set(dev_id, (union in_flow_tbl_op_data8_u *)(&entry->val[8])); - return hppe_flow_host_op_both_common(dev_id, 0, op_mode, index); -} - -sw_error_t -hppe_flow_entry_host_op_ipv6_3tuple_add( - a_uint32_t dev_id, a_uint32_t op_mode, - a_uint32_t *index, union in_flow_ipv6_3tuple_tbl_u *entry) -{ - hppe_in_flow_tbl_op_data0_set(dev_id, (union in_flow_tbl_op_data0_u *)(&entry->val[0])); - hppe_in_flow_tbl_op_data1_set(dev_id, (union in_flow_tbl_op_data1_u *)(&entry->val[1])); - hppe_in_flow_tbl_op_data2_set(dev_id, (union in_flow_tbl_op_data2_u *)(&entry->val[2])); - hppe_in_flow_tbl_op_data3_set(dev_id, (union in_flow_tbl_op_data3_u *)(&entry->val[3])); - hppe_in_flow_tbl_op_data4_set(dev_id, (union in_flow_tbl_op_data4_u *)(&entry->val[4])); - hppe_in_flow_tbl_op_data5_set(dev_id, (union in_flow_tbl_op_data5_u *)(&entry->val[5])); - hppe_in_flow_tbl_op_data6_set(dev_id, (union in_flow_tbl_op_data6_u *)(&entry->val[6])); - hppe_in_flow_tbl_op_data7_set(dev_id, (union in_flow_tbl_op_data7_u *)(&entry->val[7])); - hppe_in_flow_tbl_op_data8_set(dev_id, (union in_flow_tbl_op_data8_u *)(&entry->val[8])); - return hppe_flow_host_op_both_common(dev_id, 0, op_mode, index); -} - -sw_error_t -hppe_flow_entry_host_op_ipv4_5tuple_del( - a_uint32_t dev_id, a_uint32_t op_mode, - a_uint32_t *index, union in_flow_tbl_u *entry) -{ - if (op_mode == 0) { - hppe_in_flow_tbl_op_data0_set(dev_id, (union in_flow_tbl_op_data0_u *)(&entry->val[0])); - hppe_in_flow_tbl_op_data1_set(dev_id, (union in_flow_tbl_op_data1_u *)(&entry->val[1])); - hppe_in_flow_tbl_op_data2_set(dev_id, (union in_flow_tbl_op_data2_u *)(&entry->val[2])); - hppe_in_flow_tbl_op_data3_set(dev_id, (union in_flow_tbl_op_data3_u *)(&entry->val[3])); - hppe_in_flow_tbl_op_data4_set(dev_id, (union in_flow_tbl_op_data4_u *)(&entry->val[4])); - } - return hppe_flow_host_op_both_common(dev_id, 1, op_mode, index); -} - -sw_error_t -hppe_flow_entry_host_op_ipv4_3tuple_del( - a_uint32_t dev_id, a_uint32_t op_mode, - a_uint32_t *index, union in_flow_3tuple_tbl_u *entry) -{ - if (op_mode == 0) { - hppe_in_flow_tbl_op_data0_set(dev_id, (union in_flow_tbl_op_data0_u *)(&entry->val[0])); - hppe_in_flow_tbl_op_data1_set(dev_id, (union in_flow_tbl_op_data1_u *)(&entry->val[1])); - hppe_in_flow_tbl_op_data2_set(dev_id, (union in_flow_tbl_op_data2_u *)(&entry->val[2])); - hppe_in_flow_tbl_op_data3_set(dev_id, (union in_flow_tbl_op_data3_u *)(&entry->val[3])); - hppe_in_flow_tbl_op_data4_set(dev_id, (union in_flow_tbl_op_data4_u *)(&entry->val[4])); - } - return hppe_flow_host_op_both_common(dev_id, 1, op_mode, index); -} - -sw_error_t -hppe_flow_entry_host_op_ipv6_5tuple_del( - a_uint32_t dev_id, a_uint32_t op_mode, - a_uint32_t *index, union in_flow_ipv6_5tuple_tbl_u *entry) -{ - if (op_mode == 0) { - hppe_in_flow_tbl_op_data0_set(dev_id, (union in_flow_tbl_op_data0_u *)(&entry->val[0])); - hppe_in_flow_tbl_op_data1_set(dev_id, (union in_flow_tbl_op_data1_u *)(&entry->val[1])); - hppe_in_flow_tbl_op_data2_set(dev_id, (union in_flow_tbl_op_data2_u *)(&entry->val[2])); - hppe_in_flow_tbl_op_data3_set(dev_id, (union in_flow_tbl_op_data3_u *)(&entry->val[3])); - hppe_in_flow_tbl_op_data4_set(dev_id, (union in_flow_tbl_op_data4_u *)(&entry->val[4])); - hppe_in_flow_tbl_op_data5_set(dev_id, (union in_flow_tbl_op_data5_u *)(&entry->val[5])); - hppe_in_flow_tbl_op_data6_set(dev_id, (union in_flow_tbl_op_data6_u *)(&entry->val[6])); - hppe_in_flow_tbl_op_data7_set(dev_id, (union in_flow_tbl_op_data7_u *)(&entry->val[7])); - hppe_in_flow_tbl_op_data8_set(dev_id, (union in_flow_tbl_op_data8_u *)(&entry->val[8])); - } - return hppe_flow_host_op_both_common(dev_id, 1, op_mode, index); -} - -sw_error_t -hppe_flow_entry_host_op_ipv6_3tuple_del( - a_uint32_t dev_id, a_uint32_t op_mode, - a_uint32_t *index, union in_flow_ipv6_3tuple_tbl_u *entry) -{ - if (op_mode == 0) { - hppe_in_flow_tbl_op_data0_set(dev_id, (union in_flow_tbl_op_data0_u *)(&entry->val[0])); - hppe_in_flow_tbl_op_data1_set(dev_id, (union in_flow_tbl_op_data1_u *)(&entry->val[1])); - hppe_in_flow_tbl_op_data2_set(dev_id, (union in_flow_tbl_op_data2_u *)(&entry->val[2])); - hppe_in_flow_tbl_op_data3_set(dev_id, (union in_flow_tbl_op_data3_u *)(&entry->val[3])); - hppe_in_flow_tbl_op_data4_set(dev_id, (union in_flow_tbl_op_data4_u *)(&entry->val[4])); - hppe_in_flow_tbl_op_data5_set(dev_id, (union in_flow_tbl_op_data5_u *)(&entry->val[5])); - hppe_in_flow_tbl_op_data6_set(dev_id, (union in_flow_tbl_op_data6_u *)(&entry->val[6])); - hppe_in_flow_tbl_op_data7_set(dev_id, (union in_flow_tbl_op_data7_u *)(&entry->val[7])); - hppe_in_flow_tbl_op_data8_set(dev_id, (union in_flow_tbl_op_data8_u *)(&entry->val[8])); - } - return hppe_flow_host_op_both_common(dev_id, 1, op_mode, index); -} - -sw_error_t -hppe_flow_entry_host_op_ipv4_5tuple_get( - a_uint32_t dev_id, a_uint32_t op_mode, - a_uint32_t *index, union in_flow_tbl_u *entry) -{ - if (op_mode == 0) { - hppe_in_flow_tbl_rd_op_data0_set(dev_id, (union in_flow_tbl_rd_op_data0_u *)(&entry->val[0])); - hppe_in_flow_tbl_rd_op_data1_set(dev_id, (union in_flow_tbl_rd_op_data1_u *)(&entry->val[1])); - hppe_in_flow_tbl_rd_op_data2_set(dev_id, (union in_flow_tbl_rd_op_data2_u *)(&entry->val[2])); - hppe_in_flow_tbl_rd_op_data3_set(dev_id, (union in_flow_tbl_rd_op_data3_u *)(&entry->val[3])); - hppe_in_flow_tbl_rd_op_data4_set(dev_id, (union in_flow_tbl_rd_op_data4_u *)(&entry->val[4])); - } - return hppe_flow_host_get_common(dev_id, op_mode, index, (a_uint32_t *)entry, 5); -} - -sw_error_t -hppe_flow_entry_host_op_ipv4_3tuple_get( - a_uint32_t dev_id, a_uint32_t op_mode, - a_uint32_t *index, union in_flow_3tuple_tbl_u *entry) -{ - if (op_mode == 0) { - hppe_in_flow_tbl_rd_op_data0_set(dev_id, (union in_flow_tbl_rd_op_data0_u *)(&entry->val[0])); - hppe_in_flow_tbl_rd_op_data1_set(dev_id, (union in_flow_tbl_rd_op_data1_u *)(&entry->val[1])); - hppe_in_flow_tbl_rd_op_data2_set(dev_id, (union in_flow_tbl_rd_op_data2_u *)(&entry->val[2])); - hppe_in_flow_tbl_rd_op_data3_set(dev_id, (union in_flow_tbl_rd_op_data3_u *)(&entry->val[3])); - hppe_in_flow_tbl_rd_op_data4_set(dev_id, (union in_flow_tbl_rd_op_data4_u *)(&entry->val[4])); - } - return hppe_flow_host_get_common(dev_id, op_mode, index, (a_uint32_t *)entry, 5); -} - -sw_error_t -hppe_flow_entry_host_op_ipv6_5tuple_get( - a_uint32_t dev_id, a_uint32_t op_mode, - a_uint32_t *index, union in_flow_ipv6_5tuple_tbl_u *entry) -{ - if (op_mode == 0) { - hppe_in_flow_tbl_rd_op_data0_set(dev_id, (union in_flow_tbl_rd_op_data0_u *)(&entry->val[0])); - hppe_in_flow_tbl_rd_op_data1_set(dev_id, (union in_flow_tbl_rd_op_data1_u *)(&entry->val[1])); - hppe_in_flow_tbl_rd_op_data2_set(dev_id, (union in_flow_tbl_rd_op_data2_u *)(&entry->val[2])); - hppe_in_flow_tbl_rd_op_data3_set(dev_id, (union in_flow_tbl_rd_op_data3_u *)(&entry->val[3])); - hppe_in_flow_tbl_rd_op_data4_set(dev_id, (union in_flow_tbl_rd_op_data4_u *)(&entry->val[4])); - hppe_in_flow_tbl_rd_op_data5_set(dev_id, (union in_flow_tbl_rd_op_data5_u *)(&entry->val[5])); - hppe_in_flow_tbl_rd_op_data6_set(dev_id, (union in_flow_tbl_rd_op_data6_u *)(&entry->val[6])); - hppe_in_flow_tbl_rd_op_data7_set(dev_id, (union in_flow_tbl_rd_op_data7_u *)(&entry->val[7])); - hppe_in_flow_tbl_rd_op_data8_set(dev_id, (union in_flow_tbl_rd_op_data8_u *)(&entry->val[8])); - } - return hppe_flow_host_get_common(dev_id, op_mode, index, (a_uint32_t *)entry, 9); -} - -sw_error_t -hppe_flow_entry_host_op_ipv6_3tuple_get( - a_uint32_t dev_id, a_uint32_t op_mode, - a_uint32_t *index, union in_flow_ipv6_3tuple_tbl_u *entry) -{ - if (op_mode == 0) { - hppe_in_flow_tbl_rd_op_data0_set(dev_id, (union in_flow_tbl_rd_op_data0_u *)(&entry->val[0])); - hppe_in_flow_tbl_rd_op_data1_set(dev_id, (union in_flow_tbl_rd_op_data1_u *)(&entry->val[1])); - hppe_in_flow_tbl_rd_op_data2_set(dev_id, (union in_flow_tbl_rd_op_data2_u *)(&entry->val[2])); - hppe_in_flow_tbl_rd_op_data3_set(dev_id, (union in_flow_tbl_rd_op_data3_u *)(&entry->val[3])); - hppe_in_flow_tbl_rd_op_data4_set(dev_id, (union in_flow_tbl_rd_op_data4_u *)(&entry->val[4])); - hppe_in_flow_tbl_rd_op_data5_set(dev_id, (union in_flow_tbl_rd_op_data5_u *)(&entry->val[5])); - hppe_in_flow_tbl_rd_op_data6_set(dev_id, (union in_flow_tbl_rd_op_data6_u *)(&entry->val[6])); - hppe_in_flow_tbl_rd_op_data7_set(dev_id, (union in_flow_tbl_rd_op_data7_u *)(&entry->val[7])); - hppe_in_flow_tbl_rd_op_data8_set(dev_id, (union in_flow_tbl_rd_op_data8_u *)(&entry->val[8])); - } - return hppe_flow_host_get_common(dev_id, op_mode, index, (a_uint32_t *)entry, 9); -} - -sw_error_t -hppe_flow_host_data_op_common( - a_uint32_t dev_id, - a_uint32_t op_type, - a_uint32_t op_mode, - a_uint32_t *index) -{ - union in_flow_host_tbl_op_u op; - sw_error_t rv; - - op.bf.hash_block_bitmap = 3; - op.bf.host_entry_index = *index; - - rv = hppe_in_flow_host_tbl_op_set(dev_id, &op); - if (SW_OK != rv) - return rv; - - return SW_OK; -} - -sw_error_t -hppe_flow_host_data_rd_op_common( - a_uint32_t dev_id, - a_uint32_t op_type, - a_uint32_t op_mode, - a_uint32_t *index) -{ - union in_flow_host_tbl_rd_op_u op; - sw_error_t rv; - - op.bf.hash_block_bitmap = 3; - op.bf.host_entry_index = *index; - - rv = hppe_in_flow_host_tbl_rd_op_set(dev_id, &op); - if (SW_OK != rv) - return rv; - - return SW_OK; -} -sw_error_t -hppe_flow_host_ipv4_data_add( - a_uint32_t dev_id, a_uint32_t op_mode, - a_uint32_t *index, union host_tbl_u *entry) -{ - hppe_flow_host_tbl_op_data0_set(dev_id, (union flow_host_tbl_op_data0_u *)(&entry->val[0])); - hppe_flow_host_tbl_op_data1_set(dev_id, (union flow_host_tbl_op_data1_u *)(&entry->val[1])); - hppe_flow_host_tbl_op_data2_set(dev_id, (union flow_host_tbl_op_data2_u *)(&entry->val[2])); - return hppe_flow_host_data_op_common(dev_id, 0, op_mode, index); -} - -sw_error_t -hppe_flow_host_ipv6_data_add( - a_uint32_t dev_id, a_uint32_t op_mode, - a_uint32_t *index, union host_ipv6_tbl_u *entry) -{ - hppe_flow_host_tbl_op_data0_set(dev_id, (union flow_host_tbl_op_data0_u *)(&entry->val[0])); - hppe_flow_host_tbl_op_data1_set(dev_id, (union flow_host_tbl_op_data1_u *)(&entry->val[1])); - hppe_flow_host_tbl_op_data2_set(dev_id, (union flow_host_tbl_op_data2_u *)(&entry->val[2])); - hppe_flow_host_tbl_op_data3_set(dev_id, (union flow_host_tbl_op_data3_u *)(&entry->val[3])); - hppe_flow_host_tbl_op_data4_set(dev_id, (union flow_host_tbl_op_data4_u *)(&entry->val[4])); - return hppe_flow_host_data_op_common(dev_id, 0, op_mode, index); -} - -sw_error_t -hppe_flow_host_ipv4_data_rd_add( - a_uint32_t dev_id, a_uint32_t op_mode, - a_uint32_t *index, union host_tbl_u *entry) -{ - hppe_flow_host_tbl_rd_op_data0_set(dev_id, (union flow_host_tbl_rd_op_data0_u *)(&entry->val[0])); - hppe_flow_host_tbl_rd_op_data1_set(dev_id, (union flow_host_tbl_rd_op_data1_u *)(&entry->val[1])); - hppe_flow_host_tbl_rd_op_data2_set(dev_id, (union flow_host_tbl_rd_op_data2_u*)(&entry->val[2])); - return hppe_flow_host_data_rd_op_common(dev_id, 0, op_mode, index); -} - -sw_error_t -hppe_flow_host_ipv6_data_rd_add( - a_uint32_t dev_id, a_uint32_t op_mode, - a_uint32_t *index, union host_ipv6_tbl_u *entry) -{ - hppe_flow_host_tbl_rd_op_data0_set(dev_id, (union flow_host_tbl_rd_op_data0_u *)(&entry->val[0])); - hppe_flow_host_tbl_rd_op_data1_set(dev_id, (union flow_host_tbl_rd_op_data1_u *)(&entry->val[1])); - hppe_flow_host_tbl_rd_op_data2_set(dev_id, (union flow_host_tbl_rd_op_data2_u *)(&entry->val[2])); - hppe_flow_host_tbl_rd_op_data3_set(dev_id, (union flow_host_tbl_rd_op_data3_u *)(&entry->val[3])); - hppe_flow_host_tbl_rd_op_data4_set(dev_id, (union flow_host_tbl_rd_op_data4_u *)(&entry->val[4])); - return hppe_flow_host_data_rd_op_common(dev_id, 0, op_mode, index); -} - -sw_error_t -hppe_flow_host_ipv4_data_get( - a_uint32_t dev_id, a_uint32_t op_mode, - a_uint32_t *index, union host_tbl_u *entry) -{ - if (1){//op_mode == 0) { - hppe_host_tbl_rd_op_data0_get(dev_id, (union host_tbl_rd_op_data0_u *)(&entry->val[0])); - hppe_host_tbl_rd_op_data1_get(dev_id, (union host_tbl_rd_op_data1_u *)(&entry->val[1])); - hppe_host_tbl_rd_op_data2_set(dev_id, (union host_tbl_rd_op_data2_u *)(&entry->val[2])); - } - return SW_OK; -} - -sw_error_t -hppe_flow_host_ipv6_data_get( - a_uint32_t dev_id, a_uint32_t op_mode, - a_uint32_t *index, union host_ipv6_tbl_u *entry) -{ - if (1){//op_mode == 0) { - hppe_host_tbl_rd_op_data0_get(dev_id, (union host_tbl_rd_op_data0_u *)(&entry->val[0])); - hppe_host_tbl_rd_op_data1_get(dev_id, (union host_tbl_rd_op_data1_u *)(&entry->val[1])); - hppe_host_tbl_rd_op_data2_get(dev_id, (union host_tbl_rd_op_data2_u *)(&entry->val[2])); - hppe_host_tbl_rd_op_data3_get(dev_id, (union host_tbl_rd_op_data3_u *)(&entry->val[3])); - hppe_host_tbl_rd_op_data4_get(dev_id, (union host_tbl_rd_op_data4_u *)(&entry->val[4])); - } - return SW_OK; -} - -sw_error_t -hppe_flow_host_ipv4_data_del( - a_uint32_t dev_id, a_uint32_t op_mode, - a_uint32_t *index, union host_tbl_u *entry) -{ - if (op_mode == 0) { - hppe_host_tbl_op_data0_set(dev_id, (union host_tbl_op_data0_u *)(&entry->val[0])); - hppe_host_tbl_op_data1_set(dev_id, (union host_tbl_op_data1_u *)(&entry->val[1])); - hppe_host_tbl_op_data2_set(dev_id, (union host_tbl_op_data2_u *)(&entry->val[2])); - } - return hppe_flow_host_data_op_common(dev_id, 1, op_mode, index); - -} - -sw_error_t -hppe_flow_host_ipv6_data_del( - a_uint32_t dev_id, a_uint32_t op_mode, - a_uint32_t *index, union host_ipv6_tbl_u *entry) -{ - if (op_mode == 0) { - hppe_host_tbl_op_data0_set(dev_id, (union host_tbl_op_data0_u *)(&entry->val[0])); - hppe_host_tbl_op_data1_set(dev_id, (union host_tbl_op_data1_u *)(&entry->val[1])); - hppe_host_tbl_op_data2_set(dev_id, (union host_tbl_op_data2_u *)(&entry->val[2])); - hppe_host_tbl_op_data3_set(dev_id, (union host_tbl_op_data3_u *)(&entry->val[3])); - hppe_host_tbl_op_data4_set(dev_id, (union host_tbl_op_data4_u *)(&entry->val[4])); - } - return hppe_flow_host_data_op_common(dev_id, 1, op_mode, index); -} - - -sw_error_t -hppe_flow_ipv4_5tuple_add( - a_uint32_t dev_id, a_uint32_t op_mode, - a_uint32_t *index, union in_flow_tbl_u *entry) -{ - hppe_in_flow_tbl_op_data0_set(dev_id, (union in_flow_tbl_op_data0_u *)(&entry->val[0])); - hppe_in_flow_tbl_op_data1_set(dev_id, (union in_flow_tbl_op_data1_u *)(&entry->val[1])); - hppe_in_flow_tbl_op_data2_set(dev_id, (union in_flow_tbl_op_data2_u *)(&entry->val[2])); - hppe_in_flow_tbl_op_data3_set(dev_id, (union in_flow_tbl_op_data3_u *)(&entry->val[3])); - hppe_in_flow_tbl_op_data4_set(dev_id, (union in_flow_tbl_op_data4_u *)(&entry->val[4])); - return hppe_flow_op_common(dev_id, 0, op_mode, index); -} - -sw_error_t -hppe_flow_ipv4_3tuple_add( - a_uint32_t dev_id, a_uint32_t op_mode, - a_uint32_t *index, union in_flow_3tuple_tbl_u *entry) -{ - hppe_in_flow_tbl_op_data0_set(dev_id, (union in_flow_tbl_op_data0_u *)(&entry->val[0])); - hppe_in_flow_tbl_op_data1_set(dev_id, (union in_flow_tbl_op_data1_u *)(&entry->val[1])); - hppe_in_flow_tbl_op_data2_set(dev_id, (union in_flow_tbl_op_data2_u *)(&entry->val[2])); - hppe_in_flow_tbl_op_data3_set(dev_id, (union in_flow_tbl_op_data3_u *)(&entry->val[3])); - hppe_in_flow_tbl_op_data4_set(dev_id, (union in_flow_tbl_op_data4_u *)(&entry->val[4])); - return hppe_flow_op_common(dev_id, 0, op_mode, index); -} - -sw_error_t -hppe_flow_ipv6_5tuple_add( - a_uint32_t dev_id, a_uint32_t op_mode, - a_uint32_t *index, union in_flow_ipv6_5tuple_tbl_u *entry) -{ - hppe_in_flow_tbl_op_data0_set(dev_id, (union in_flow_tbl_op_data0_u *)(&entry->val[0])); - hppe_in_flow_tbl_op_data1_set(dev_id, (union in_flow_tbl_op_data1_u *)(&entry->val[1])); - hppe_in_flow_tbl_op_data2_set(dev_id, (union in_flow_tbl_op_data2_u *)(&entry->val[2])); - hppe_in_flow_tbl_op_data3_set(dev_id, (union in_flow_tbl_op_data3_u *)(&entry->val[3])); - hppe_in_flow_tbl_op_data4_set(dev_id, (union in_flow_tbl_op_data4_u *)(&entry->val[4])); - hppe_in_flow_tbl_op_data5_set(dev_id, (union in_flow_tbl_op_data5_u *)(&entry->val[5])); - hppe_in_flow_tbl_op_data6_set(dev_id, (union in_flow_tbl_op_data6_u *)(&entry->val[6])); - hppe_in_flow_tbl_op_data7_set(dev_id, (union in_flow_tbl_op_data7_u *)(&entry->val[7])); - hppe_in_flow_tbl_op_data8_set(dev_id, (union in_flow_tbl_op_data8_u *)(&entry->val[8])); - return hppe_flow_op_common(dev_id, 0, op_mode, index); -} - -sw_error_t -hppe_flow_ipv6_3tuple_add( - a_uint32_t dev_id, a_uint32_t op_mode, - a_uint32_t *index, union in_flow_ipv6_3tuple_tbl_u *entry) -{ - hppe_in_flow_tbl_op_data0_set(dev_id, (union in_flow_tbl_op_data0_u *)(&entry->val[0])); - hppe_in_flow_tbl_op_data1_set(dev_id, (union in_flow_tbl_op_data1_u *)(&entry->val[1])); - hppe_in_flow_tbl_op_data2_set(dev_id, (union in_flow_tbl_op_data2_u *)(&entry->val[2])); - hppe_in_flow_tbl_op_data3_set(dev_id, (union in_flow_tbl_op_data3_u *)(&entry->val[3])); - hppe_in_flow_tbl_op_data4_set(dev_id, (union in_flow_tbl_op_data4_u *)(&entry->val[4])); - hppe_in_flow_tbl_op_data5_set(dev_id, (union in_flow_tbl_op_data5_u *)(&entry->val[5])); - hppe_in_flow_tbl_op_data6_set(dev_id, (union in_flow_tbl_op_data6_u *)(&entry->val[6])); - hppe_in_flow_tbl_op_data7_set(dev_id, (union in_flow_tbl_op_data7_u *)(&entry->val[7])); - hppe_in_flow_tbl_op_data8_set(dev_id, (union in_flow_tbl_op_data8_u *)(&entry->val[8])); - return hppe_flow_op_common(dev_id, 0, op_mode, index); -} - -sw_error_t -hppe_flow_ipv4_5tuple_del( - a_uint32_t dev_id, a_uint32_t op_mode, - a_uint32_t *index, union in_flow_tbl_u *entry) -{ - if (op_mode == 0) { - hppe_in_flow_tbl_op_data0_set(dev_id, - (union in_flow_tbl_op_data0_u *)(&entry->val[0])); - hppe_in_flow_tbl_op_data1_set(dev_id, - (union in_flow_tbl_op_data1_u *)(&entry->val[1])); - hppe_in_flow_tbl_op_data2_set(dev_id, - (union in_flow_tbl_op_data2_u *)(&entry->val[2])); - hppe_in_flow_tbl_op_data3_set(dev_id, - (union in_flow_tbl_op_data3_u *)(&entry->val[3])); - hppe_in_flow_tbl_op_data4_set(dev_id, - (union in_flow_tbl_op_data4_u *)(&entry->val[4])); - } - return hppe_flow_op_common(dev_id, 1, op_mode, index); -} - -sw_error_t -hppe_flow_ipv4_3tuple_del( - a_uint32_t dev_id, a_uint32_t op_mode, - a_uint32_t *index, union in_flow_3tuple_tbl_u *entry) -{ - if (op_mode == 0) { - hppe_in_flow_tbl_op_data0_set(dev_id, - (union in_flow_tbl_op_data0_u *)(&entry->val[0])); - hppe_in_flow_tbl_op_data1_set(dev_id, - (union in_flow_tbl_op_data1_u *)(&entry->val[1])); - hppe_in_flow_tbl_op_data2_set(dev_id, - (union in_flow_tbl_op_data2_u *)(&entry->val[2])); - hppe_in_flow_tbl_op_data3_set(dev_id, - (union in_flow_tbl_op_data3_u *)(&entry->val[3])); - hppe_in_flow_tbl_op_data4_set(dev_id, - (union in_flow_tbl_op_data4_u *)(&entry->val[4])); - } - return hppe_flow_op_common(dev_id, 1, op_mode, index); -} - -sw_error_t -hppe_flow_ipv6_5tuple_del( - a_uint32_t dev_id, a_uint32_t op_mode, - a_uint32_t *index, union in_flow_ipv6_5tuple_tbl_u *entry) -{ - if (op_mode == 0) { - hppe_in_flow_tbl_op_data0_set(dev_id, - (union in_flow_tbl_op_data0_u *)(&entry->val[0])); - hppe_in_flow_tbl_op_data1_set(dev_id, - (union in_flow_tbl_op_data1_u *)(&entry->val[1])); - hppe_in_flow_tbl_op_data2_set(dev_id, - (union in_flow_tbl_op_data2_u *)(&entry->val[2])); - hppe_in_flow_tbl_op_data3_set(dev_id, - (union in_flow_tbl_op_data3_u *)(&entry->val[3])); - hppe_in_flow_tbl_op_data4_set(dev_id, - (union in_flow_tbl_op_data4_u *)(&entry->val[4])); - hppe_in_flow_tbl_op_data5_set(dev_id, - (union in_flow_tbl_op_data5_u *)(&entry->val[5])); - hppe_in_flow_tbl_op_data6_set(dev_id, - (union in_flow_tbl_op_data6_u *)(&entry->val[6])); - hppe_in_flow_tbl_op_data7_set(dev_id, - (union in_flow_tbl_op_data7_u *)(&entry->val[7])); - hppe_in_flow_tbl_op_data8_set(dev_id, - (union in_flow_tbl_op_data8_u *)(&entry->val[8])); - } - return hppe_flow_op_common(dev_id, 1, op_mode, index); -} - -sw_error_t -hppe_flow_ipv6_3tuple_del( - a_uint32_t dev_id, a_uint32_t op_mode, - a_uint32_t *index, union in_flow_ipv6_3tuple_tbl_u *entry) -{ - if (op_mode == 0) { - hppe_in_flow_tbl_op_data0_set(dev_id, - (union in_flow_tbl_op_data0_u *)(&entry->val[0])); - hppe_in_flow_tbl_op_data1_set(dev_id, - (union in_flow_tbl_op_data1_u *)(&entry->val[1])); - hppe_in_flow_tbl_op_data2_set(dev_id, - (union in_flow_tbl_op_data2_u *)(&entry->val[2])); - hppe_in_flow_tbl_op_data3_set(dev_id, - (union in_flow_tbl_op_data3_u *)(&entry->val[3])); - hppe_in_flow_tbl_op_data4_set(dev_id, - (union in_flow_tbl_op_data4_u *)(&entry->val[4])); - hppe_in_flow_tbl_op_data5_set(dev_id, - (union in_flow_tbl_op_data5_u *)(&entry->val[5])); - hppe_in_flow_tbl_op_data6_set(dev_id, - (union in_flow_tbl_op_data6_u *)(&entry->val[6])); - hppe_in_flow_tbl_op_data7_set(dev_id, - (union in_flow_tbl_op_data7_u *)(&entry->val[7])); - hppe_in_flow_tbl_op_data8_set(dev_id, - (union in_flow_tbl_op_data8_u *)(&entry->val[8])); - } - return hppe_flow_op_common(dev_id, 1, op_mode, index); -} - -sw_error_t -hppe_flow_ipv4_5tuple_get( - a_uint32_t dev_id, a_uint32_t op_mode, - a_uint32_t *index, union in_flow_tbl_u *entry) -{ - if (op_mode == 0) { - hppe_in_flow_tbl_rd_op_data0_set(dev_id, - (union in_flow_tbl_rd_op_data0_u *)(&entry->val[0])); - hppe_in_flow_tbl_rd_op_data1_set(dev_id, - (union in_flow_tbl_rd_op_data1_u *)(&entry->val[1])); - hppe_in_flow_tbl_rd_op_data2_set(dev_id, - (union in_flow_tbl_rd_op_data2_u *)(&entry->val[2])); - hppe_in_flow_tbl_rd_op_data3_set(dev_id, - (union in_flow_tbl_rd_op_data3_u *)(&entry->val[3])); - hppe_in_flow_tbl_rd_op_data4_set(dev_id, - (union in_flow_tbl_rd_op_data4_u *)(&entry->val[4])); - } - return hppe_flow_get_common(dev_id, op_mode, index, (a_uint32_t *)entry, 5); -} - -sw_error_t -hppe_flow_ipv4_3tuple_get( - a_uint32_t dev_id, a_uint32_t op_mode, - a_uint32_t *index, union in_flow_3tuple_tbl_u *entry) -{ - if (op_mode == 0) { - hppe_in_flow_tbl_rd_op_data0_set(dev_id, - (union in_flow_tbl_rd_op_data0_u *)(&entry->val[0])); - hppe_in_flow_tbl_rd_op_data1_set(dev_id, - (union in_flow_tbl_rd_op_data1_u *)(&entry->val[1])); - hppe_in_flow_tbl_rd_op_data2_set(dev_id, - (union in_flow_tbl_rd_op_data2_u *)(&entry->val[2])); - hppe_in_flow_tbl_rd_op_data3_set(dev_id, - (union in_flow_tbl_rd_op_data3_u *)(&entry->val[3])); - hppe_in_flow_tbl_rd_op_data4_set(dev_id, - (union in_flow_tbl_rd_op_data4_u *)(&entry->val[4])); - } - return hppe_flow_get_common(dev_id, op_mode, index, (a_uint32_t *)entry, 5); -} - -sw_error_t -hppe_flow_ipv6_5tuple_get( - a_uint32_t dev_id, a_uint32_t op_mode, - a_uint32_t *index, union in_flow_ipv6_5tuple_tbl_u *entry) -{ - if (op_mode == 0) { - hppe_in_flow_tbl_rd_op_data0_set(dev_id, - (union in_flow_tbl_rd_op_data0_u *)(&entry->val[0])); - hppe_in_flow_tbl_rd_op_data1_set(dev_id, - (union in_flow_tbl_rd_op_data1_u *)(&entry->val[1])); - hppe_in_flow_tbl_rd_op_data2_set(dev_id, - (union in_flow_tbl_rd_op_data2_u *)(&entry->val[2])); - hppe_in_flow_tbl_rd_op_data3_set(dev_id, - (union in_flow_tbl_rd_op_data3_u *)(&entry->val[3])); - hppe_in_flow_tbl_rd_op_data4_set(dev_id, - (union in_flow_tbl_rd_op_data4_u *)(&entry->val[4])); - hppe_in_flow_tbl_rd_op_data5_set(dev_id, - (union in_flow_tbl_rd_op_data5_u *)(&entry->val[5])); - hppe_in_flow_tbl_rd_op_data6_set(dev_id, - (union in_flow_tbl_rd_op_data6_u *)(&entry->val[6])); - hppe_in_flow_tbl_rd_op_data7_set(dev_id, - (union in_flow_tbl_rd_op_data7_u *)(&entry->val[7])); - hppe_in_flow_tbl_rd_op_data8_set(dev_id, - (union in_flow_tbl_rd_op_data8_u *)(&entry->val[8])); - } - return hppe_flow_get_common(dev_id, op_mode, index, (a_uint32_t *)entry, 9); -} - -sw_error_t -hppe_flow_ipv6_3tuple_get( - a_uint32_t dev_id, a_uint32_t op_mode, - a_uint32_t *index, union in_flow_ipv6_3tuple_tbl_u *entry) -{ - if (op_mode == 0) { - hppe_in_flow_tbl_rd_op_data0_set(dev_id, - (union in_flow_tbl_rd_op_data0_u *)(&entry->val[0])); - hppe_in_flow_tbl_rd_op_data1_set(dev_id, - (union in_flow_tbl_rd_op_data1_u *)(&entry->val[1])); - hppe_in_flow_tbl_rd_op_data2_set(dev_id, - (union in_flow_tbl_rd_op_data2_u *)(&entry->val[2])); - hppe_in_flow_tbl_rd_op_data3_set(dev_id, - (union in_flow_tbl_rd_op_data3_u *)(&entry->val[3])); - hppe_in_flow_tbl_rd_op_data4_set(dev_id, - (union in_flow_tbl_rd_op_data4_u *)(&entry->val[4])); - hppe_in_flow_tbl_rd_op_data5_set(dev_id, - (union in_flow_tbl_rd_op_data5_u *)(&entry->val[5])); - hppe_in_flow_tbl_rd_op_data6_set(dev_id, - (union in_flow_tbl_rd_op_data6_u *)(&entry->val[6])); - hppe_in_flow_tbl_rd_op_data7_set(dev_id, - (union in_flow_tbl_rd_op_data7_u *)(&entry->val[7])); - hppe_in_flow_tbl_rd_op_data8_set(dev_id, - (union in_flow_tbl_rd_op_data8_u *)(&entry->val[8])); - } - return hppe_flow_get_common(dev_id, op_mode, index, (a_uint32_t *)entry, 9); -} -#endif diff --git a/feeds/ipq807x/qca-ssdk/src/src/hsl/hppe/hppe_global.c b/feeds/ipq807x/qca-ssdk/src/src/hsl/hppe/hppe_global.c deleted file mode 100755 index 85fbaaf53..000000000 --- a/feeds/ipq807x/qca-ssdk/src/src/hsl/hppe/hppe_global.c +++ /dev/null @@ -1,3117 +0,0 @@ -/* - * Copyright (c) 2016-2017, The Linux Foundation. All rights reserved. - * Permission to use, copy, modify, and/or distribute this software for - * any purpose with or without fee is hereby granted, provided that the - * above copyright notice and this permission notice appear in all copies. - * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES - * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR - * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES - * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN - * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT - * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. - */ - - -/** - * @defgroup - * @{ - */ -#include "sw.h" -#include "hsl.h" -#include "hppe_reg_access.h" -#include "hppe_global_reg.h" -#include "hppe_global.h" - -sw_error_t -hppe_switch_id_get( - a_uint32_t dev_id, - union switch_id_u *value) -{ - return hppe_reg_get( - dev_id, - NSS_GLOBAL_BASE_ADDR + SWITCH_ID_ADDRESS, - &value->val); -} - -sw_error_t -hppe_switch_id_set( - a_uint32_t dev_id, - union switch_id_u *value) -{ - return hppe_reg_set( - dev_id, - NSS_GLOBAL_BASE_ADDR + SWITCH_ID_ADDRESS, - value->val); -} - -sw_error_t -hppe_rgmii_ctrl_get( - a_uint32_t dev_id, - union rgmii_ctrl_u *value) -{ - return hppe_reg_get( - dev_id, - NSS_GLOBAL_BASE_ADDR + RGMII_CTRL_ADDRESS, - &value->val); -} - -sw_error_t -hppe_rgmii_ctrl_set( - a_uint32_t dev_id, - union rgmii_ctrl_u *value) -{ - return hppe_reg_set( - dev_id, - NSS_GLOBAL_BASE_ADDR + RGMII_CTRL_ADDRESS, - value->val); -} - -sw_error_t -hppe_clk_gating_ctrl_get( - a_uint32_t dev_id, - union clk_gating_ctrl_u *value) -{ - return hppe_reg_get( - dev_id, - NSS_GLOBAL_BASE_ADDR + CLK_GATING_CTRL_ADDRESS, - &value->val); -} - -sw_error_t -hppe_clk_gating_ctrl_set( - a_uint32_t dev_id, - union clk_gating_ctrl_u *value) -{ - return hppe_reg_set( - dev_id, - NSS_GLOBAL_BASE_ADDR + CLK_GATING_CTRL_ADDRESS, - value->val); -} - -sw_error_t -hppe_port_mux_ctrl_get( - a_uint32_t dev_id, - union port_mux_ctrl_u *value) -{ - return hppe_reg_get( - dev_id, - NSS_GLOBAL_BASE_ADDR + PORT_MUX_CTRL_ADDRESS, - &value->val); -} - -sw_error_t -hppe_port_mux_ctrl_set( - a_uint32_t dev_id, - union port_mux_ctrl_u *value) -{ - return hppe_reg_set( - dev_id, - NSS_GLOBAL_BASE_ADDR + PORT_MUX_CTRL_ADDRESS, - value->val); -} - -sw_error_t -cppe_port_mux_ctrl_get( - a_uint32_t dev_id, - union cppe_port_mux_ctrl_u *value) -{ - return hppe_reg_get( - dev_id, - NSS_GLOBAL_BASE_ADDR + PORT_MUX_CTRL_ADDRESS, - &value->val); -} -sw_error_t -cppe_port_mux_ctrl_set( - a_uint32_t dev_id, - union cppe_port_mux_ctrl_u *value) -{ - return hppe_reg_set( - dev_id, - NSS_GLOBAL_BASE_ADDR + PORT_MUX_CTRL_ADDRESS, - value->val); -} -sw_error_t -hppe_module_ini_done_int_get( - a_uint32_t dev_id, - union module_ini_done_int_u *value) -{ - return hppe_reg_get( - dev_id, - NSS_GLOBAL_BASE_ADDR + MODULE_INI_DONE_INT_ADDRESS, - &value->val); -} - -sw_error_t -hppe_module_ini_done_int_set( - a_uint32_t dev_id, - union module_ini_done_int_u *value) -{ - return hppe_reg_set( - dev_id, - NSS_GLOBAL_BASE_ADDR + MODULE_INI_DONE_INT_ADDRESS, - value->val); -} - -sw_error_t -hppe_module_cpu_done_int_get( - a_uint32_t dev_id, - union module_cpu_done_int_u *value) -{ - return hppe_reg_get( - dev_id, - NSS_GLOBAL_BASE_ADDR + MODULE_CPU_DONE_INT_ADDRESS, - &value->val); -} - -sw_error_t -hppe_module_cpu_done_int_set( - a_uint32_t dev_id, - union module_cpu_done_int_u *value) -{ - return hppe_reg_set( - dev_id, - NSS_GLOBAL_BASE_ADDR + MODULE_CPU_DONE_INT_ADDRESS, - value->val); -} - -sw_error_t -hppe_port_link_int_get( - a_uint32_t dev_id, - union port_link_int_u *value) -{ - return hppe_reg_get( - dev_id, - NSS_GLOBAL_BASE_ADDR + PORT_LINK_INT_ADDRESS, - &value->val); -} - -sw_error_t -hppe_port_link_int_set( - a_uint32_t dev_id, - union port_link_int_u *value) -{ - return hppe_reg_set( - dev_id, - NSS_GLOBAL_BASE_ADDR + PORT_LINK_INT_ADDRESS, - value->val); -} - -sw_error_t -hppe_module_ini_done_int_mask_get( - a_uint32_t dev_id, - union module_ini_done_int_mask_u *value) -{ - return hppe_reg_get( - dev_id, - NSS_GLOBAL_BASE_ADDR + MODULE_INI_DONE_INT_MASK_ADDRESS, - &value->val); -} - -sw_error_t -hppe_module_ini_done_int_mask_set( - a_uint32_t dev_id, - union module_ini_done_int_mask_u *value) -{ - return hppe_reg_set( - dev_id, - NSS_GLOBAL_BASE_ADDR + MODULE_INI_DONE_INT_MASK_ADDRESS, - value->val); -} - -sw_error_t -hppe_module_cpu_done_int_mask_get( - a_uint32_t dev_id, - union module_cpu_done_int_mask_u *value) -{ - return hppe_reg_get( - dev_id, - NSS_GLOBAL_BASE_ADDR + MODULE_CPU_DONE_INT_MASK_ADDRESS, - &value->val); -} - -sw_error_t -hppe_module_cpu_done_int_mask_set( - a_uint32_t dev_id, - union module_cpu_done_int_mask_u *value) -{ - return hppe_reg_set( - dev_id, - NSS_GLOBAL_BASE_ADDR + MODULE_CPU_DONE_INT_MASK_ADDRESS, - value->val); -} - -sw_error_t -hppe_port_link_int_mask_get( - a_uint32_t dev_id, - union port_link_int_mask_u *value) -{ - return hppe_reg_get( - dev_id, - NSS_GLOBAL_BASE_ADDR + PORT_LINK_INT_MASK_ADDRESS, - &value->val); -} - -sw_error_t -hppe_port_link_int_mask_set( - a_uint32_t dev_id, - union port_link_int_mask_u *value) -{ - return hppe_reg_set( - dev_id, - NSS_GLOBAL_BASE_ADDR + PORT_LINK_INT_MASK_ADDRESS, - value->val); -} - -sw_error_t -hppe_port_phy_status_0_get( - a_uint32_t dev_id, - union port_phy_status_0_u *value) -{ - return hppe_reg_get( - dev_id, - NSS_GLOBAL_BASE_ADDR + PORT_PHY_STATUS_0_ADDRESS, - &value->val); -} - -sw_error_t -hppe_port_phy_status_0_set( - a_uint32_t dev_id, - union port_phy_status_0_u *value) -{ - return SW_NOT_SUPPORTED; -} - -sw_error_t -hppe_port_phy_status_1_get( - a_uint32_t dev_id, - union port_phy_status_1_u *value) -{ - return hppe_reg_get( - dev_id, - NSS_GLOBAL_BASE_ADDR + PORT_PHY_STATUS_1_ADDRESS, - &value->val); -} - -sw_error_t -hppe_port_phy_status_1_set( - a_uint32_t dev_id, - union port_phy_status_1_u *value) -{ - return SW_NOT_SUPPORTED; -} - -sw_error_t -hppe_port1_status_get( - a_uint32_t dev_id, - union port1_status_u *value) -{ - return hppe_reg_get( - dev_id, - NSS_GLOBAL_BASE_ADDR + PORT1_STATUS_ADDRESS, - &value->val); -} - -sw_error_t -hppe_port1_status_set( - a_uint32_t dev_id, - union port1_status_u *value) -{ - return SW_NOT_SUPPORTED; -} - -sw_error_t -hppe_port2_status_get( - a_uint32_t dev_id, - union port2_status_u *value) -{ - return hppe_reg_get( - dev_id, - NSS_GLOBAL_BASE_ADDR + PORT2_STATUS_ADDRESS, - &value->val); -} - -sw_error_t -hppe_port2_status_set( - a_uint32_t dev_id, - union port2_status_u *value) -{ - return SW_NOT_SUPPORTED; -} - -sw_error_t -hppe_port3_status_get( - a_uint32_t dev_id, - union port3_status_u *value) -{ - return hppe_reg_get( - dev_id, - NSS_GLOBAL_BASE_ADDR + PORT3_STATUS_ADDRESS, - &value->val); -} - -sw_error_t -hppe_port3_status_set( - a_uint32_t dev_id, - union port3_status_u *value) -{ - return SW_NOT_SUPPORTED; -} - -sw_error_t -hppe_port4_status_get( - a_uint32_t dev_id, - union port4_status_u *value) -{ - return hppe_reg_get( - dev_id, - NSS_GLOBAL_BASE_ADDR + PORT4_STATUS_ADDRESS, - &value->val); -} - -sw_error_t -hppe_port4_status_set( - a_uint32_t dev_id, - union port4_status_u *value) -{ - return SW_NOT_SUPPORTED; -} - -sw_error_t -hppe_port5_status_get( - a_uint32_t dev_id, - union port5_status_u *value) -{ - return hppe_reg_get( - dev_id, - NSS_GLOBAL_BASE_ADDR + PORT5_STATUS_ADDRESS, - &value->val); -} - -sw_error_t -hppe_port5_status_set( - a_uint32_t dev_id, - union port5_status_u *value) -{ - return SW_NOT_SUPPORTED; -} - -sw_error_t -hppe_port6_status_get( - a_uint32_t dev_id, - union port6_status_u *value) -{ - return hppe_reg_get( - dev_id, - NSS_GLOBAL_BASE_ADDR + PORT6_STATUS_ADDRESS, - &value->val); -} - -sw_error_t -hppe_port6_status_set( - a_uint32_t dev_id, - union port6_status_u *value) -{ - return SW_NOT_SUPPORTED; -} - -sw_error_t -hppe_reserved_regs_0_get( - a_uint32_t dev_id, - union reserved_regs_0_u *value) -{ - return hppe_reg_get( - dev_id, - NSS_GLOBAL_BASE_ADDR + RESERVED_REGS_0_ADDRESS, - &value->val); -} - -sw_error_t -hppe_reserved_regs_0_set( - a_uint32_t dev_id, - union reserved_regs_0_u *value) -{ - return hppe_reg_set( - dev_id, - NSS_GLOBAL_BASE_ADDR + RESERVED_REGS_0_ADDRESS, - value->val); -} - -sw_error_t -hppe_reserved_regs_1_get( - a_uint32_t dev_id, - union reserved_regs_1_u *value) -{ - return hppe_reg_get( - dev_id, - NSS_GLOBAL_BASE_ADDR + RESERVED_REGS_1_ADDRESS, - &value->val); -} - -sw_error_t -hppe_reserved_regs_1_set( - a_uint32_t dev_id, - union reserved_regs_1_u *value) -{ - return hppe_reg_set( - dev_id, - NSS_GLOBAL_BASE_ADDR + RESERVED_REGS_1_ADDRESS, - value->val); -} - -sw_error_t -hppe_reserved_regs_2_get( - a_uint32_t dev_id, - union reserved_regs_2_u *value) -{ - return hppe_reg_get( - dev_id, - NSS_GLOBAL_BASE_ADDR + RESERVED_REGS_2_ADDRESS, - &value->val); -} - -sw_error_t -hppe_reserved_regs_2_set( - a_uint32_t dev_id, - union reserved_regs_2_u *value) -{ - return hppe_reg_set( - dev_id, - NSS_GLOBAL_BASE_ADDR + RESERVED_REGS_2_ADDRESS, - value->val); -} - -sw_error_t -hppe_reserved_regs_3_get( - a_uint32_t dev_id, - union reserved_regs_3_u *value) -{ - return hppe_reg_get( - dev_id, - NSS_GLOBAL_BASE_ADDR + RESERVED_REGS_3_ADDRESS, - &value->val); -} - -sw_error_t -hppe_reserved_regs_3_set( - a_uint32_t dev_id, - union reserved_regs_3_u *value) -{ - return hppe_reg_set( - dev_id, - NSS_GLOBAL_BASE_ADDR + RESERVED_REGS_3_ADDRESS, - value->val); -} - -sw_error_t -hppe_dbg_data_sel_get( - a_uint32_t dev_id, - union dbg_data_sel_u *value) -{ - return hppe_reg_get( - dev_id, - NSS_GLOBAL_BASE_ADDR + DBG_DATA_SEL_ADDRESS, - &value->val); -} - -sw_error_t -hppe_dbg_data_sel_set( - a_uint32_t dev_id, - union dbg_data_sel_u *value) -{ - return hppe_reg_set( - dev_id, - NSS_GLOBAL_BASE_ADDR + DBG_DATA_SEL_ADDRESS, - value->val); -} - -sw_error_t -hppe_switch_id_dev_id_get( - a_uint32_t dev_id, - a_uint32_t *value) -{ - union switch_id_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_switch_id_get(dev_id, ®_val); - *value = reg_val.bf.dev_id; - return ret; -} - -sw_error_t -hppe_switch_id_dev_id_set( - a_uint32_t dev_id, - a_uint32_t value) -{ - union switch_id_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_switch_id_get(dev_id, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.dev_id = value; - ret = hppe_switch_id_set(dev_id, ®_val); - return ret; -} - -sw_error_t -hppe_switch_id_rev_id_get( - a_uint32_t dev_id, - a_uint32_t *value) -{ - union switch_id_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_switch_id_get(dev_id, ®_val); - *value = reg_val.bf.rev_id; - return ret; -} - -sw_error_t -hppe_switch_id_rev_id_set( - a_uint32_t dev_id, - a_uint32_t value) -{ - union switch_id_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_switch_id_get(dev_id, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.rev_id = value; - ret = hppe_switch_id_set(dev_id, ®_val); - return ret; -} - -sw_error_t -hppe_rgmii_ctrl_rgmii_ctrl_get( - a_uint32_t dev_id, - a_uint32_t *value) -{ - union rgmii_ctrl_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_rgmii_ctrl_get(dev_id, ®_val); - *value = reg_val.bf.rgmii_ctrl; - return ret; -} - -sw_error_t -hppe_rgmii_ctrl_rgmii_ctrl_set( - a_uint32_t dev_id, - a_uint32_t value) -{ - union rgmii_ctrl_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_rgmii_ctrl_get(dev_id, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.rgmii_ctrl = value; - ret = hppe_rgmii_ctrl_set(dev_id, ®_val); - return ret; -} - -sw_error_t -hppe_clk_gating_ctrl_clk_gating_ctrl_get( - a_uint32_t dev_id, - a_uint32_t *value) -{ - union clk_gating_ctrl_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_clk_gating_ctrl_get(dev_id, ®_val); - *value = reg_val.bf.clk_gating_ctrl; - return ret; -} - -sw_error_t -hppe_clk_gating_ctrl_clk_gating_ctrl_set( - a_uint32_t dev_id, - a_uint32_t value) -{ - union clk_gating_ctrl_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_clk_gating_ctrl_get(dev_id, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.clk_gating_ctrl = value; - ret = hppe_clk_gating_ctrl_set(dev_id, ®_val); - return ret; -} - -sw_error_t -hppe_port_mux_ctrl_port6_pcs_sel_get( - a_uint32_t dev_id, - a_uint32_t *value) -{ - union port_mux_ctrl_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_port_mux_ctrl_get(dev_id, ®_val); - *value = reg_val.bf.port6_pcs_sel; - return ret; -} - -sw_error_t -hppe_port_mux_ctrl_port6_pcs_sel_set( - a_uint32_t dev_id, - a_uint32_t value) -{ - union port_mux_ctrl_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_port_mux_ctrl_get(dev_id, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.port6_pcs_sel = value; - ret = hppe_port_mux_ctrl_set(dev_id, ®_val); - return ret; -} - -sw_error_t -hppe_port_mux_ctrl_port5_gmac_sel_get( - a_uint32_t dev_id, - a_uint32_t *value) -{ - union port_mux_ctrl_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_port_mux_ctrl_get(dev_id, ®_val); - *value = reg_val.bf.port5_gmac_sel; - return ret; -} - -sw_error_t -hppe_port_mux_ctrl_port5_gmac_sel_set( - a_uint32_t dev_id, - a_uint32_t value) -{ - union port_mux_ctrl_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_port_mux_ctrl_get(dev_id, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.port5_gmac_sel = value; - ret = hppe_port_mux_ctrl_set(dev_id, ®_val); - return ret; -} - -sw_error_t -hppe_port_mux_ctrl_port5_pcs_sel_get( - a_uint32_t dev_id, - a_uint32_t *value) -{ - union port_mux_ctrl_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_port_mux_ctrl_get(dev_id, ®_val); - *value = reg_val.bf.port5_pcs_sel; - return ret; -} - -sw_error_t -hppe_port_mux_ctrl_port5_pcs_sel_set( - a_uint32_t dev_id, - a_uint32_t value) -{ - union port_mux_ctrl_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_port_mux_ctrl_get(dev_id, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.port5_pcs_sel = value; - ret = hppe_port_mux_ctrl_set(dev_id, ®_val); - return ret; -} - -sw_error_t -hppe_port_mux_ctrl_port4_pcs_sel_get( - a_uint32_t dev_id, - a_uint32_t *value) -{ - union port_mux_ctrl_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_port_mux_ctrl_get(dev_id, ®_val); - *value = reg_val.bf.port4_pcs_sel; - return ret; -} - -sw_error_t -hppe_port_mux_ctrl_port4_pcs_sel_set( - a_uint32_t dev_id, - a_uint32_t value) -{ - union port_mux_ctrl_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_port_mux_ctrl_get(dev_id, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.port4_pcs_sel = value; - ret = hppe_port_mux_ctrl_set(dev_id, ®_val); - return ret; -} - -sw_error_t -hppe_port_mux_ctrl_port6_gmac_sel_get( - a_uint32_t dev_id, - a_uint32_t *value) -{ - union port_mux_ctrl_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_port_mux_ctrl_get(dev_id, ®_val); - *value = reg_val.bf.port6_gmac_sel; - return ret; -} - -sw_error_t -hppe_port_mux_ctrl_port6_gmac_sel_set( - a_uint32_t dev_id, - a_uint32_t value) -{ - union port_mux_ctrl_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_port_mux_ctrl_get(dev_id, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.port6_gmac_sel = value; - ret = hppe_port_mux_ctrl_set(dev_id, ®_val); - return ret; -} - -sw_error_t -hppe_module_ini_done_int_iv_ini_done_int_get( - a_uint32_t dev_id, - a_uint32_t *value) -{ - union module_ini_done_int_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_module_ini_done_int_get(dev_id, ®_val); - *value = reg_val.bf.iv_ini_done_int; - return ret; -} - -sw_error_t -hppe_module_ini_done_int_iv_ini_done_int_set( - a_uint32_t dev_id, - a_uint32_t value) -{ - union module_ini_done_int_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_module_ini_done_int_get(dev_id, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.iv_ini_done_int = value; - ret = hppe_module_ini_done_int_set(dev_id, ®_val); - return ret; -} - -sw_error_t -hppe_module_ini_done_int_qm_ini_done_int_get( - a_uint32_t dev_id, - a_uint32_t *value) -{ - union module_ini_done_int_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_module_ini_done_int_get(dev_id, ®_val); - *value = reg_val.bf.qm_ini_done_int; - return ret; -} - -sw_error_t -hppe_module_ini_done_int_qm_ini_done_int_set( - a_uint32_t dev_id, - a_uint32_t value) -{ - union module_ini_done_int_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_module_ini_done_int_get(dev_id, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.qm_ini_done_int = value; - ret = hppe_module_ini_done_int_set(dev_id, ®_val); - return ret; -} - -sw_error_t -hppe_module_ini_done_int_l3_ini_done_int_get( - a_uint32_t dev_id, - a_uint32_t *value) -{ - union module_ini_done_int_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_module_ini_done_int_get(dev_id, ®_val); - *value = reg_val.bf.l3_ini_done_int; - return ret; -} - -sw_error_t -hppe_module_ini_done_int_l3_ini_done_int_set( - a_uint32_t dev_id, - a_uint32_t value) -{ - union module_ini_done_int_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_module_ini_done_int_get(dev_id, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.l3_ini_done_int = value; - ret = hppe_module_ini_done_int_set(dev_id, ®_val); - return ret; -} - -sw_error_t -hppe_module_ini_done_int_bm_ini_done_int_get( - a_uint32_t dev_id, - a_uint32_t *value) -{ - union module_ini_done_int_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_module_ini_done_int_get(dev_id, ®_val); - *value = reg_val.bf.bm_ini_done_int; - return ret; -} - -sw_error_t -hppe_module_ini_done_int_bm_ini_done_int_set( - a_uint32_t dev_id, - a_uint32_t value) -{ - union module_ini_done_int_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_module_ini_done_int_get(dev_id, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.bm_ini_done_int = value; - ret = hppe_module_ini_done_int_set(dev_id, ®_val); - return ret; -} - -sw_error_t -hppe_module_ini_done_int_ptx_ini_done_int_get( - a_uint32_t dev_id, - a_uint32_t *value) -{ - union module_ini_done_int_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_module_ini_done_int_get(dev_id, ®_val); - *value = reg_val.bf.ptx_ini_done_int; - return ret; -} - -sw_error_t -hppe_module_ini_done_int_ptx_ini_done_int_set( - a_uint32_t dev_id, - a_uint32_t value) -{ - union module_ini_done_int_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_module_ini_done_int_get(dev_id, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.ptx_ini_done_int = value; - ret = hppe_module_ini_done_int_set(dev_id, ®_val); - return ret; -} - -sw_error_t -hppe_module_ini_done_int_tm_ini_done_int_get( - a_uint32_t dev_id, - a_uint32_t *value) -{ - union module_ini_done_int_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_module_ini_done_int_get(dev_id, ®_val); - *value = reg_val.bf.tm_ini_done_int; - return ret; -} - -sw_error_t -hppe_module_ini_done_int_tm_ini_done_int_set( - a_uint32_t dev_id, - a_uint32_t value) -{ - union module_ini_done_int_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_module_ini_done_int_get(dev_id, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.tm_ini_done_int = value; - ret = hppe_module_ini_done_int_set(dev_id, ®_val); - return ret; -} - -sw_error_t -hppe_module_ini_done_int_l2_ini_done_int_get( - a_uint32_t dev_id, - a_uint32_t *value) -{ - union module_ini_done_int_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_module_ini_done_int_get(dev_id, ®_val); - *value = reg_val.bf.l2_ini_done_int; - return ret; -} - -sw_error_t -hppe_module_ini_done_int_l2_ini_done_int_set( - a_uint32_t dev_id, - a_uint32_t value) -{ - union module_ini_done_int_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_module_ini_done_int_get(dev_id, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.l2_ini_done_int = value; - ret = hppe_module_ini_done_int_set(dev_id, ®_val); - return ret; -} - -sw_error_t -hppe_module_ini_done_int_acl_ini_done_int_get( - a_uint32_t dev_id, - a_uint32_t *value) -{ - union module_ini_done_int_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_module_ini_done_int_get(dev_id, ®_val); - *value = reg_val.bf.acl_ini_done_int; - return ret; -} - -sw_error_t -hppe_module_ini_done_int_acl_ini_done_int_set( - a_uint32_t dev_id, - a_uint32_t value) -{ - union module_ini_done_int_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_module_ini_done_int_get(dev_id, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.acl_ini_done_int = value; - ret = hppe_module_ini_done_int_set(dev_id, ®_val); - return ret; -} - -sw_error_t -hppe_module_ini_done_int_ing_rate_ini_done_int_get( - a_uint32_t dev_id, - a_uint32_t *value) -{ - union module_ini_done_int_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_module_ini_done_int_get(dev_id, ®_val); - *value = reg_val.bf.ing_rate_ini_done_int; - return ret; -} - -sw_error_t -hppe_module_ini_done_int_ing_rate_ini_done_int_set( - a_uint32_t dev_id, - a_uint32_t value) -{ - union module_ini_done_int_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_module_ini_done_int_get(dev_id, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.ing_rate_ini_done_int = value; - ret = hppe_module_ini_done_int_set(dev_id, ®_val); - return ret; -} - -sw_error_t -hppe_module_cpu_done_int_l3_flow_wr_cmd_overflow_int_get( - a_uint32_t dev_id, - a_uint32_t *value) -{ - union module_cpu_done_int_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_module_cpu_done_int_get(dev_id, ®_val); - *value = reg_val.bf.l3_flow_wr_cmd_overflow_int; - return ret; -} - -sw_error_t -hppe_module_cpu_done_int_l3_flow_wr_cmd_overflow_int_set( - a_uint32_t dev_id, - a_uint32_t value) -{ - union module_cpu_done_int_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_module_cpu_done_int_get(dev_id, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.l3_flow_wr_cmd_overflow_int = value; - ret = hppe_module_cpu_done_int_set(dev_id, ®_val); - return ret; -} - -sw_error_t -hppe_module_cpu_done_int_l2_fdb_rd_cmd_overflow_int_get( - a_uint32_t dev_id, - a_uint32_t *value) -{ - union module_cpu_done_int_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_module_cpu_done_int_get(dev_id, ®_val); - *value = reg_val.bf.l2_fdb_rd_cmd_overflow_int; - return ret; -} - -sw_error_t -hppe_module_cpu_done_int_l2_fdb_rd_cmd_overflow_int_set( - a_uint32_t dev_id, - a_uint32_t value) -{ - union module_cpu_done_int_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_module_cpu_done_int_get(dev_id, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.l2_fdb_rd_cmd_overflow_int = value; - ret = hppe_module_cpu_done_int_set(dev_id, ®_val); - return ret; -} - -sw_error_t -hppe_module_cpu_done_int_qm_cpu_op_done_int_get( - a_uint32_t dev_id, - a_uint32_t *value) -{ - union module_cpu_done_int_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_module_cpu_done_int_get(dev_id, ®_val); - *value = reg_val.bf.qm_cpu_op_done_int; - return ret; -} - -sw_error_t -hppe_module_cpu_done_int_qm_cpu_op_done_int_set( - a_uint32_t dev_id, - a_uint32_t value) -{ - union module_cpu_done_int_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_module_cpu_done_int_get(dev_id, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.qm_cpu_op_done_int = value; - ret = hppe_module_cpu_done_int_set(dev_id, ®_val); - return ret; -} - -sw_error_t -hppe_module_cpu_done_int_l3_flow_rd_cmd_overflow_int_get( - a_uint32_t dev_id, - a_uint32_t *value) -{ - union module_cpu_done_int_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_module_cpu_done_int_get(dev_id, ®_val); - *value = reg_val.bf.l3_flow_rd_cmd_overflow_int; - return ret; -} - -sw_error_t -hppe_module_cpu_done_int_l3_flow_rd_cmd_overflow_int_set( - a_uint32_t dev_id, - a_uint32_t value) -{ - union module_cpu_done_int_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_module_cpu_done_int_get(dev_id, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.l3_flow_rd_cmd_overflow_int = value; - ret = hppe_module_cpu_done_int_set(dev_id, ®_val); - return ret; -} - -sw_error_t -hppe_module_cpu_done_int_l2_fdb_wr_result_vld_int_get( - a_uint32_t dev_id, - a_uint32_t *value) -{ - union module_cpu_done_int_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_module_cpu_done_int_get(dev_id, ®_val); - *value = reg_val.bf.l2_fdb_wr_result_vld_int; - return ret; -} - -sw_error_t -hppe_module_cpu_done_int_l2_fdb_wr_result_vld_int_set( - a_uint32_t dev_id, - a_uint32_t value) -{ - union module_cpu_done_int_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_module_cpu_done_int_get(dev_id, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.l2_fdb_wr_result_vld_int = value; - ret = hppe_module_cpu_done_int_set(dev_id, ®_val); - return ret; -} - -sw_error_t -hppe_module_cpu_done_int_l2_fdb_rd_result_vld_int_get( - a_uint32_t dev_id, - a_uint32_t *value) -{ - union module_cpu_done_int_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_module_cpu_done_int_get(dev_id, ®_val); - *value = reg_val.bf.l2_fdb_rd_result_vld_int; - return ret; -} - -sw_error_t -hppe_module_cpu_done_int_l2_fdb_rd_result_vld_int_set( - a_uint32_t dev_id, - a_uint32_t value) -{ - union module_cpu_done_int_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_module_cpu_done_int_get(dev_id, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.l2_fdb_rd_result_vld_int = value; - ret = hppe_module_cpu_done_int_set(dev_id, ®_val); - return ret; -} - -sw_error_t -hppe_module_cpu_done_int_l2_fdb_wr_cmd_overflow_int_get( - a_uint32_t dev_id, - a_uint32_t *value) -{ - union module_cpu_done_int_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_module_cpu_done_int_get(dev_id, ®_val); - *value = reg_val.bf.l2_fdb_wr_cmd_overflow_int; - return ret; -} - -sw_error_t -hppe_module_cpu_done_int_l2_fdb_wr_cmd_overflow_int_set( - a_uint32_t dev_id, - a_uint32_t value) -{ - union module_cpu_done_int_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_module_cpu_done_int_get(dev_id, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.l2_fdb_wr_cmd_overflow_int = value; - ret = hppe_module_cpu_done_int_set(dev_id, ®_val); - return ret; -} - -sw_error_t -hppe_module_cpu_done_int_l3_flow_rd_result_vld_int_get( - a_uint32_t dev_id, - a_uint32_t *value) -{ - union module_cpu_done_int_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_module_cpu_done_int_get(dev_id, ®_val); - *value = reg_val.bf.l3_flow_rd_result_vld_int; - return ret; -} - -sw_error_t -hppe_module_cpu_done_int_l3_flow_rd_result_vld_int_set( - a_uint32_t dev_id, - a_uint32_t value) -{ - union module_cpu_done_int_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_module_cpu_done_int_get(dev_id, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.l3_flow_rd_result_vld_int = value; - ret = hppe_module_cpu_done_int_set(dev_id, ®_val); - return ret; -} - -sw_error_t -hppe_module_cpu_done_int_l3_host_wr_cmd_overflow_int_get( - a_uint32_t dev_id, - a_uint32_t *value) -{ - union module_cpu_done_int_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_module_cpu_done_int_get(dev_id, ®_val); - *value = reg_val.bf.l3_host_wr_cmd_overflow_int; - return ret; -} - -sw_error_t -hppe_module_cpu_done_int_l3_host_wr_cmd_overflow_int_set( - a_uint32_t dev_id, - a_uint32_t value) -{ - union module_cpu_done_int_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_module_cpu_done_int_get(dev_id, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.l3_host_wr_cmd_overflow_int = value; - ret = hppe_module_cpu_done_int_set(dev_id, ®_val); - return ret; -} - -sw_error_t -hppe_module_cpu_done_int_l3_host_rd_cmd_overflow_int_get( - a_uint32_t dev_id, - a_uint32_t *value) -{ - union module_cpu_done_int_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_module_cpu_done_int_get(dev_id, ®_val); - *value = reg_val.bf.l3_host_rd_cmd_overflow_int; - return ret; -} - -sw_error_t -hppe_module_cpu_done_int_l3_host_rd_cmd_overflow_int_set( - a_uint32_t dev_id, - a_uint32_t value) -{ - union module_cpu_done_int_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_module_cpu_done_int_get(dev_id, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.l3_host_rd_cmd_overflow_int = value; - ret = hppe_module_cpu_done_int_set(dev_id, ®_val); - return ret; -} - -sw_error_t -hppe_module_cpu_done_int_l3_host_rd_result_vld_int_get( - a_uint32_t dev_id, - a_uint32_t *value) -{ - union module_cpu_done_int_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_module_cpu_done_int_get(dev_id, ®_val); - *value = reg_val.bf.l3_host_rd_result_vld_int; - return ret; -} - -sw_error_t -hppe_module_cpu_done_int_l3_host_rd_result_vld_int_set( - a_uint32_t dev_id, - a_uint32_t value) -{ - union module_cpu_done_int_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_module_cpu_done_int_get(dev_id, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.l3_host_rd_result_vld_int = value; - ret = hppe_module_cpu_done_int_set(dev_id, ®_val); - return ret; -} - -sw_error_t -hppe_module_cpu_done_int_l3_host_wr_result_vld_int_get( - a_uint32_t dev_id, - a_uint32_t *value) -{ - union module_cpu_done_int_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_module_cpu_done_int_get(dev_id, ®_val); - *value = reg_val.bf.l3_host_wr_result_vld_int; - return ret; -} - -sw_error_t -hppe_module_cpu_done_int_l3_host_wr_result_vld_int_set( - a_uint32_t dev_id, - a_uint32_t value) -{ - union module_cpu_done_int_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_module_cpu_done_int_get(dev_id, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.l3_host_wr_result_vld_int = value; - ret = hppe_module_cpu_done_int_set(dev_id, ®_val); - return ret; -} - -sw_error_t -hppe_module_cpu_done_int_l3_flow_wr_result_vld_int_get( - a_uint32_t dev_id, - a_uint32_t *value) -{ - union module_cpu_done_int_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_module_cpu_done_int_get(dev_id, ®_val); - *value = reg_val.bf.l3_flow_wr_result_vld_int; - return ret; -} - -sw_error_t -hppe_module_cpu_done_int_l3_flow_wr_result_vld_int_set( - a_uint32_t dev_id, - a_uint32_t value) -{ - union module_cpu_done_int_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_module_cpu_done_int_get(dev_id, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.l3_flow_wr_result_vld_int = value; - ret = hppe_module_cpu_done_int_set(dev_id, ®_val); - return ret; -} - -sw_error_t -hppe_port_link_int_port6_link_chg_int_get( - a_uint32_t dev_id, - a_uint32_t *value) -{ - union port_link_int_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_port_link_int_get(dev_id, ®_val); - *value = reg_val.bf.port6_link_chg_int; - return ret; -} - -sw_error_t -hppe_port_link_int_port6_link_chg_int_set( - a_uint32_t dev_id, - a_uint32_t value) -{ - union port_link_int_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_port_link_int_get(dev_id, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.port6_link_chg_int = value; - ret = hppe_port_link_int_set(dev_id, ®_val); - return ret; -} - -sw_error_t -hppe_port_link_int_xgmac0_an_done_int_get( - a_uint32_t dev_id, - a_uint32_t *value) -{ - union port_link_int_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_port_link_int_get(dev_id, ®_val); - *value = reg_val.bf.xgmac0_an_done_int; - return ret; -} - -sw_error_t -hppe_port_link_int_xgmac0_an_done_int_set( - a_uint32_t dev_id, - a_uint32_t value) -{ - union port_link_int_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_port_link_int_get(dev_id, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.xgmac0_an_done_int = value; - ret = hppe_port_link_int_set(dev_id, ®_val); - return ret; -} - -sw_error_t -hppe_port_link_int_port5_1_link_chg_int_get( - a_uint32_t dev_id, - a_uint32_t *value) -{ - union port_link_int_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_port_link_int_get(dev_id, ®_val); - *value = reg_val.bf.port5_1_link_chg_int; - return ret; -} - -sw_error_t -hppe_port_link_int_port5_1_link_chg_int_set( - a_uint32_t dev_id, - a_uint32_t value) -{ - union port_link_int_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_port_link_int_get(dev_id, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.port5_1_link_chg_int = value; - ret = hppe_port_link_int_set(dev_id, ®_val); - return ret; -} - -sw_error_t -hppe_port_link_int_port5_0_link_chg_int_get( - a_uint32_t dev_id, - a_uint32_t *value) -{ - union port_link_int_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_port_link_int_get(dev_id, ®_val); - *value = reg_val.bf.port5_0_link_chg_int; - return ret; -} - -sw_error_t -hppe_port_link_int_port5_0_link_chg_int_set( - a_uint32_t dev_id, - a_uint32_t value) -{ - union port_link_int_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_port_link_int_get(dev_id, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.port5_0_link_chg_int = value; - ret = hppe_port_link_int_set(dev_id, ®_val); - return ret; -} - -sw_error_t -hppe_port_link_int_port4_link_chg_int_get( - a_uint32_t dev_id, - a_uint32_t *value) -{ - union port_link_int_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_port_link_int_get(dev_id, ®_val); - *value = reg_val.bf.port4_link_chg_int; - return ret; -} - -sw_error_t -hppe_port_link_int_port4_link_chg_int_set( - a_uint32_t dev_id, - a_uint32_t value) -{ - union port_link_int_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_port_link_int_get(dev_id, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.port4_link_chg_int = value; - ret = hppe_port_link_int_set(dev_id, ®_val); - return ret; -} - -sw_error_t -hppe_port_link_int_port3_link_chg_int_get( - a_uint32_t dev_id, - a_uint32_t *value) -{ - union port_link_int_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_port_link_int_get(dev_id, ®_val); - *value = reg_val.bf.port3_link_chg_int; - return ret; -} - -sw_error_t -hppe_port_link_int_port3_link_chg_int_set( - a_uint32_t dev_id, - a_uint32_t value) -{ - union port_link_int_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_port_link_int_get(dev_id, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.port3_link_chg_int = value; - ret = hppe_port_link_int_set(dev_id, ®_val); - return ret; -} - -sw_error_t -hppe_port_link_int_port2_link_chg_int_get( - a_uint32_t dev_id, - a_uint32_t *value) -{ - union port_link_int_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_port_link_int_get(dev_id, ®_val); - *value = reg_val.bf.port2_link_chg_int; - return ret; -} - -sw_error_t -hppe_port_link_int_port2_link_chg_int_set( - a_uint32_t dev_id, - a_uint32_t value) -{ - union port_link_int_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_port_link_int_get(dev_id, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.port2_link_chg_int = value; - ret = hppe_port_link_int_set(dev_id, ®_val); - return ret; -} - -sw_error_t -hppe_port_link_int_xgmac1_an_done_int_get( - a_uint32_t dev_id, - a_uint32_t *value) -{ - union port_link_int_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_port_link_int_get(dev_id, ®_val); - *value = reg_val.bf.xgmac1_an_done_int; - return ret; -} - -sw_error_t -hppe_port_link_int_xgmac1_an_done_int_set( - a_uint32_t dev_id, - a_uint32_t value) -{ - union port_link_int_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_port_link_int_get(dev_id, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.xgmac1_an_done_int = value; - ret = hppe_port_link_int_set(dev_id, ®_val); - return ret; -} - -sw_error_t -hppe_port_link_int_port1_link_chg_int_get( - a_uint32_t dev_id, - a_uint32_t *value) -{ - union port_link_int_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_port_link_int_get(dev_id, ®_val); - *value = reg_val.bf.port1_link_chg_int; - return ret; -} - -sw_error_t -hppe_port_link_int_port1_link_chg_int_set( - a_uint32_t dev_id, - a_uint32_t value) -{ - union port_link_int_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_port_link_int_get(dev_id, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.port1_link_chg_int = value; - ret = hppe_port_link_int_set(dev_id, ®_val); - return ret; -} - -sw_error_t -hppe_module_ini_done_int_mask_tm_ini_done_int_mask_get( - a_uint32_t dev_id, - a_uint32_t *value) -{ - union module_ini_done_int_mask_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_module_ini_done_int_mask_get(dev_id, ®_val); - *value = reg_val.bf.tm_ini_done_int_mask; - return ret; -} - -sw_error_t -hppe_module_ini_done_int_mask_tm_ini_done_int_mask_set( - a_uint32_t dev_id, - a_uint32_t value) -{ - union module_ini_done_int_mask_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_module_ini_done_int_mask_get(dev_id, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.tm_ini_done_int_mask = value; - ret = hppe_module_ini_done_int_mask_set(dev_id, ®_val); - return ret; -} - -sw_error_t -hppe_module_ini_done_int_mask_bm_ini_done_int_mask_get( - a_uint32_t dev_id, - a_uint32_t *value) -{ - union module_ini_done_int_mask_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_module_ini_done_int_mask_get(dev_id, ®_val); - *value = reg_val.bf.bm_ini_done_int_mask; - return ret; -} - -sw_error_t -hppe_module_ini_done_int_mask_bm_ini_done_int_mask_set( - a_uint32_t dev_id, - a_uint32_t value) -{ - union module_ini_done_int_mask_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_module_ini_done_int_mask_get(dev_id, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.bm_ini_done_int_mask = value; - ret = hppe_module_ini_done_int_mask_set(dev_id, ®_val); - return ret; -} - -sw_error_t -hppe_module_ini_done_int_mask_iv_ini_done_int_mask_get( - a_uint32_t dev_id, - a_uint32_t *value) -{ - union module_ini_done_int_mask_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_module_ini_done_int_mask_get(dev_id, ®_val); - *value = reg_val.bf.iv_ini_done_int_mask; - return ret; -} - -sw_error_t -hppe_module_ini_done_int_mask_iv_ini_done_int_mask_set( - a_uint32_t dev_id, - a_uint32_t value) -{ - union module_ini_done_int_mask_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_module_ini_done_int_mask_get(dev_id, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.iv_ini_done_int_mask = value; - ret = hppe_module_ini_done_int_mask_set(dev_id, ®_val); - return ret; -} - -sw_error_t -hppe_module_ini_done_int_mask_acl_ini_done_int_mask_get( - a_uint32_t dev_id, - a_uint32_t *value) -{ - union module_ini_done_int_mask_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_module_ini_done_int_mask_get(dev_id, ®_val); - *value = reg_val.bf.acl_ini_done_int_mask; - return ret; -} - -sw_error_t -hppe_module_ini_done_int_mask_acl_ini_done_int_mask_set( - a_uint32_t dev_id, - a_uint32_t value) -{ - union module_ini_done_int_mask_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_module_ini_done_int_mask_get(dev_id, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.acl_ini_done_int_mask = value; - ret = hppe_module_ini_done_int_mask_set(dev_id, ®_val); - return ret; -} - -sw_error_t -hppe_module_ini_done_int_mask_qm_ini_done_int_mask_get( - a_uint32_t dev_id, - a_uint32_t *value) -{ - union module_ini_done_int_mask_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_module_ini_done_int_mask_get(dev_id, ®_val); - *value = reg_val.bf.qm_ini_done_int_mask; - return ret; -} - -sw_error_t -hppe_module_ini_done_int_mask_qm_ini_done_int_mask_set( - a_uint32_t dev_id, - a_uint32_t value) -{ - union module_ini_done_int_mask_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_module_ini_done_int_mask_get(dev_id, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.qm_ini_done_int_mask = value; - ret = hppe_module_ini_done_int_mask_set(dev_id, ®_val); - return ret; -} - -sw_error_t -hppe_module_ini_done_int_mask_l2_ini_done_int_mask_get( - a_uint32_t dev_id, - a_uint32_t *value) -{ - union module_ini_done_int_mask_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_module_ini_done_int_mask_get(dev_id, ®_val); - *value = reg_val.bf.l2_ini_done_int_mask; - return ret; -} - -sw_error_t -hppe_module_ini_done_int_mask_l2_ini_done_int_mask_set( - a_uint32_t dev_id, - a_uint32_t value) -{ - union module_ini_done_int_mask_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_module_ini_done_int_mask_get(dev_id, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.l2_ini_done_int_mask = value; - ret = hppe_module_ini_done_int_mask_set(dev_id, ®_val); - return ret; -} - -sw_error_t -hppe_module_ini_done_int_mask_ptx_ini_done_int_mask_get( - a_uint32_t dev_id, - a_uint32_t *value) -{ - union module_ini_done_int_mask_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_module_ini_done_int_mask_get(dev_id, ®_val); - *value = reg_val.bf.ptx_ini_done_int_mask; - return ret; -} - -sw_error_t -hppe_module_ini_done_int_mask_ptx_ini_done_int_mask_set( - a_uint32_t dev_id, - a_uint32_t value) -{ - union module_ini_done_int_mask_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_module_ini_done_int_mask_get(dev_id, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.ptx_ini_done_int_mask = value; - ret = hppe_module_ini_done_int_mask_set(dev_id, ®_val); - return ret; -} - -sw_error_t -hppe_module_ini_done_int_mask_ing_rate_ini_done_int_mask_get( - a_uint32_t dev_id, - a_uint32_t *value) -{ - union module_ini_done_int_mask_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_module_ini_done_int_mask_get(dev_id, ®_val); - *value = reg_val.bf.ing_rate_ini_done_int_mask; - return ret; -} - -sw_error_t -hppe_module_ini_done_int_mask_ing_rate_ini_done_int_mask_set( - a_uint32_t dev_id, - a_uint32_t value) -{ - union module_ini_done_int_mask_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_module_ini_done_int_mask_get(dev_id, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.ing_rate_ini_done_int_mask = value; - ret = hppe_module_ini_done_int_mask_set(dev_id, ®_val); - return ret; -} - -sw_error_t -hppe_module_ini_done_int_mask_l3_ini_done_int_mask_get( - a_uint32_t dev_id, - a_uint32_t *value) -{ - union module_ini_done_int_mask_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_module_ini_done_int_mask_get(dev_id, ®_val); - *value = reg_val.bf.l3_ini_done_int_mask; - return ret; -} - -sw_error_t -hppe_module_ini_done_int_mask_l3_ini_done_int_mask_set( - a_uint32_t dev_id, - a_uint32_t value) -{ - union module_ini_done_int_mask_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_module_ini_done_int_mask_get(dev_id, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.l3_ini_done_int_mask = value; - ret = hppe_module_ini_done_int_mask_set(dev_id, ®_val); - return ret; -} - -sw_error_t -hppe_module_cpu_done_int_mask_l3_host_wr_result_vld_int_mask_get( - a_uint32_t dev_id, - a_uint32_t *value) -{ - union module_cpu_done_int_mask_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_module_cpu_done_int_mask_get(dev_id, ®_val); - *value = reg_val.bf.l3_host_wr_result_vld_int_mask; - return ret; -} - -sw_error_t -hppe_module_cpu_done_int_mask_l3_host_wr_result_vld_int_mask_set( - a_uint32_t dev_id, - a_uint32_t value) -{ - union module_cpu_done_int_mask_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_module_cpu_done_int_mask_get(dev_id, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.l3_host_wr_result_vld_int_mask = value; - ret = hppe_module_cpu_done_int_mask_set(dev_id, ®_val); - return ret; -} - -sw_error_t -hppe_module_cpu_done_int_mask_l3_flow_wr_result_vld_int_mask_get( - a_uint32_t dev_id, - a_uint32_t *value) -{ - union module_cpu_done_int_mask_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_module_cpu_done_int_mask_get(dev_id, ®_val); - *value = reg_val.bf.l3_flow_wr_result_vld_int_mask; - return ret; -} - -sw_error_t -hppe_module_cpu_done_int_mask_l3_flow_wr_result_vld_int_mask_set( - a_uint32_t dev_id, - a_uint32_t value) -{ - union module_cpu_done_int_mask_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_module_cpu_done_int_mask_get(dev_id, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.l3_flow_wr_result_vld_int_mask = value; - ret = hppe_module_cpu_done_int_mask_set(dev_id, ®_val); - return ret; -} - -sw_error_t -hppe_module_cpu_done_int_mask_l3_host_rd_cmd_overflow_int_mask_get( - a_uint32_t dev_id, - a_uint32_t *value) -{ - union module_cpu_done_int_mask_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_module_cpu_done_int_mask_get(dev_id, ®_val); - *value = reg_val.bf.l3_host_rd_cmd_overflow_int_mask; - return ret; -} - -sw_error_t -hppe_module_cpu_done_int_mask_l3_host_rd_cmd_overflow_int_mask_set( - a_uint32_t dev_id, - a_uint32_t value) -{ - union module_cpu_done_int_mask_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_module_cpu_done_int_mask_get(dev_id, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.l3_host_rd_cmd_overflow_int_mask = value; - ret = hppe_module_cpu_done_int_mask_set(dev_id, ®_val); - return ret; -} - -sw_error_t -hppe_module_cpu_done_int_mask_l3_flow_wr_cmd_overflow_int_mask_get( - a_uint32_t dev_id, - a_uint32_t *value) -{ - union module_cpu_done_int_mask_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_module_cpu_done_int_mask_get(dev_id, ®_val); - *value = reg_val.bf.l3_flow_wr_cmd_overflow_int_mask; - return ret; -} - -sw_error_t -hppe_module_cpu_done_int_mask_l3_flow_wr_cmd_overflow_int_mask_set( - a_uint32_t dev_id, - a_uint32_t value) -{ - union module_cpu_done_int_mask_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_module_cpu_done_int_mask_get(dev_id, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.l3_flow_wr_cmd_overflow_int_mask = value; - ret = hppe_module_cpu_done_int_mask_set(dev_id, ®_val); - return ret; -} - -sw_error_t -hppe_module_cpu_done_int_mask_l3_host_rd_result_vld_int_mask_get( - a_uint32_t dev_id, - a_uint32_t *value) -{ - union module_cpu_done_int_mask_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_module_cpu_done_int_mask_get(dev_id, ®_val); - *value = reg_val.bf.l3_host_rd_result_vld_int_mask; - return ret; -} - -sw_error_t -hppe_module_cpu_done_int_mask_l3_host_rd_result_vld_int_mask_set( - a_uint32_t dev_id, - a_uint32_t value) -{ - union module_cpu_done_int_mask_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_module_cpu_done_int_mask_get(dev_id, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.l3_host_rd_result_vld_int_mask = value; - ret = hppe_module_cpu_done_int_mask_set(dev_id, ®_val); - return ret; -} - -sw_error_t -hppe_module_cpu_done_int_mask_l2_fdb_rd_cmd_overflow_int_mask_get( - a_uint32_t dev_id, - a_uint32_t *value) -{ - union module_cpu_done_int_mask_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_module_cpu_done_int_mask_get(dev_id, ®_val); - *value = reg_val.bf.l2_fdb_rd_cmd_overflow_int_mask; - return ret; -} - -sw_error_t -hppe_module_cpu_done_int_mask_l2_fdb_rd_cmd_overflow_int_mask_set( - a_uint32_t dev_id, - a_uint32_t value) -{ - union module_cpu_done_int_mask_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_module_cpu_done_int_mask_get(dev_id, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.l2_fdb_rd_cmd_overflow_int_mask = value; - ret = hppe_module_cpu_done_int_mask_set(dev_id, ®_val); - return ret; -} - -sw_error_t -hppe_module_cpu_done_int_mask_l2_fdb_wr_cmd_overflow_int_mask_get( - a_uint32_t dev_id, - a_uint32_t *value) -{ - union module_cpu_done_int_mask_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_module_cpu_done_int_mask_get(dev_id, ®_val); - *value = reg_val.bf.l2_fdb_wr_cmd_overflow_int_mask; - return ret; -} - -sw_error_t -hppe_module_cpu_done_int_mask_l2_fdb_wr_cmd_overflow_int_mask_set( - a_uint32_t dev_id, - a_uint32_t value) -{ - union module_cpu_done_int_mask_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_module_cpu_done_int_mask_get(dev_id, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.l2_fdb_wr_cmd_overflow_int_mask = value; - ret = hppe_module_cpu_done_int_mask_set(dev_id, ®_val); - return ret; -} - -sw_error_t -hppe_module_cpu_done_int_mask_l3_host_wr_cmd_overflow_int_mask_get( - a_uint32_t dev_id, - a_uint32_t *value) -{ - union module_cpu_done_int_mask_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_module_cpu_done_int_mask_get(dev_id, ®_val); - *value = reg_val.bf.l3_host_wr_cmd_overflow_int_mask; - return ret; -} - -sw_error_t -hppe_module_cpu_done_int_mask_l3_host_wr_cmd_overflow_int_mask_set( - a_uint32_t dev_id, - a_uint32_t value) -{ - union module_cpu_done_int_mask_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_module_cpu_done_int_mask_get(dev_id, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.l3_host_wr_cmd_overflow_int_mask = value; - ret = hppe_module_cpu_done_int_mask_set(dev_id, ®_val); - return ret; -} - -sw_error_t -hppe_module_cpu_done_int_mask_l2_fdb_rd_result_vld_int_mask_get( - a_uint32_t dev_id, - a_uint32_t *value) -{ - union module_cpu_done_int_mask_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_module_cpu_done_int_mask_get(dev_id, ®_val); - *value = reg_val.bf.l2_fdb_rd_result_vld_int_mask; - return ret; -} - -sw_error_t -hppe_module_cpu_done_int_mask_l2_fdb_rd_result_vld_int_mask_set( - a_uint32_t dev_id, - a_uint32_t value) -{ - union module_cpu_done_int_mask_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_module_cpu_done_int_mask_get(dev_id, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.l2_fdb_rd_result_vld_int_mask = value; - ret = hppe_module_cpu_done_int_mask_set(dev_id, ®_val); - return ret; -} - -sw_error_t -hppe_module_cpu_done_int_mask_l2_fdb_wr_result_vld_int_mask_get( - a_uint32_t dev_id, - a_uint32_t *value) -{ - union module_cpu_done_int_mask_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_module_cpu_done_int_mask_get(dev_id, ®_val); - *value = reg_val.bf.l2_fdb_wr_result_vld_int_mask; - return ret; -} - -sw_error_t -hppe_module_cpu_done_int_mask_l2_fdb_wr_result_vld_int_mask_set( - a_uint32_t dev_id, - a_uint32_t value) -{ - union module_cpu_done_int_mask_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_module_cpu_done_int_mask_get(dev_id, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.l2_fdb_wr_result_vld_int_mask = value; - ret = hppe_module_cpu_done_int_mask_set(dev_id, ®_val); - return ret; -} - -sw_error_t -hppe_module_cpu_done_int_mask_qm_cpu_op_done_int_mask_get( - a_uint32_t dev_id, - a_uint32_t *value) -{ - union module_cpu_done_int_mask_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_module_cpu_done_int_mask_get(dev_id, ®_val); - *value = reg_val.bf.qm_cpu_op_done_int_mask; - return ret; -} - -sw_error_t -hppe_module_cpu_done_int_mask_qm_cpu_op_done_int_mask_set( - a_uint32_t dev_id, - a_uint32_t value) -{ - union module_cpu_done_int_mask_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_module_cpu_done_int_mask_get(dev_id, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.qm_cpu_op_done_int_mask = value; - ret = hppe_module_cpu_done_int_mask_set(dev_id, ®_val); - return ret; -} - -sw_error_t -hppe_module_cpu_done_int_mask_l3_flow_rd_result_vld_int_mask_get( - a_uint32_t dev_id, - a_uint32_t *value) -{ - union module_cpu_done_int_mask_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_module_cpu_done_int_mask_get(dev_id, ®_val); - *value = reg_val.bf.l3_flow_rd_result_vld_int_mask; - return ret; -} - -sw_error_t -hppe_module_cpu_done_int_mask_l3_flow_rd_result_vld_int_mask_set( - a_uint32_t dev_id, - a_uint32_t value) -{ - union module_cpu_done_int_mask_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_module_cpu_done_int_mask_get(dev_id, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.l3_flow_rd_result_vld_int_mask = value; - ret = hppe_module_cpu_done_int_mask_set(dev_id, ®_val); - return ret; -} - -sw_error_t -hppe_module_cpu_done_int_mask_l3_flow_rd_cmd_overflow_int_mask_get( - a_uint32_t dev_id, - a_uint32_t *value) -{ - union module_cpu_done_int_mask_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_module_cpu_done_int_mask_get(dev_id, ®_val); - *value = reg_val.bf.l3_flow_rd_cmd_overflow_int_mask; - return ret; -} - -sw_error_t -hppe_module_cpu_done_int_mask_l3_flow_rd_cmd_overflow_int_mask_set( - a_uint32_t dev_id, - a_uint32_t value) -{ - union module_cpu_done_int_mask_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_module_cpu_done_int_mask_get(dev_id, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.l3_flow_rd_cmd_overflow_int_mask = value; - ret = hppe_module_cpu_done_int_mask_set(dev_id, ®_val); - return ret; -} - -sw_error_t -hppe_port_link_int_mask_xgmac0_an_done_int_mask_get( - a_uint32_t dev_id, - a_uint32_t *value) -{ - union port_link_int_mask_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_port_link_int_mask_get(dev_id, ®_val); - *value = reg_val.bf.xgmac0_an_done_int_mask; - return ret; -} - -sw_error_t -hppe_port_link_int_mask_xgmac0_an_done_int_mask_set( - a_uint32_t dev_id, - a_uint32_t value) -{ - union port_link_int_mask_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_port_link_int_mask_get(dev_id, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.xgmac0_an_done_int_mask = value; - ret = hppe_port_link_int_mask_set(dev_id, ®_val); - return ret; -} - -sw_error_t -hppe_port_link_int_mask_port2_link_chg_int_mask_get( - a_uint32_t dev_id, - a_uint32_t *value) -{ - union port_link_int_mask_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_port_link_int_mask_get(dev_id, ®_val); - *value = reg_val.bf.port2_link_chg_int_mask; - return ret; -} - -sw_error_t -hppe_port_link_int_mask_port2_link_chg_int_mask_set( - a_uint32_t dev_id, - a_uint32_t value) -{ - union port_link_int_mask_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_port_link_int_mask_get(dev_id, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.port2_link_chg_int_mask = value; - ret = hppe_port_link_int_mask_set(dev_id, ®_val); - return ret; -} - -sw_error_t -hppe_port_link_int_mask_port4_link_chg_int_mask_get( - a_uint32_t dev_id, - a_uint32_t *value) -{ - union port_link_int_mask_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_port_link_int_mask_get(dev_id, ®_val); - *value = reg_val.bf.port4_link_chg_int_mask; - return ret; -} - -sw_error_t -hppe_port_link_int_mask_port4_link_chg_int_mask_set( - a_uint32_t dev_id, - a_uint32_t value) -{ - union port_link_int_mask_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_port_link_int_mask_get(dev_id, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.port4_link_chg_int_mask = value; - ret = hppe_port_link_int_mask_set(dev_id, ®_val); - return ret; -} - -sw_error_t -hppe_port_link_int_mask_port3_link_chg_int_mask_get( - a_uint32_t dev_id, - a_uint32_t *value) -{ - union port_link_int_mask_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_port_link_int_mask_get(dev_id, ®_val); - *value = reg_val.bf.port3_link_chg_int_mask; - return ret; -} - -sw_error_t -hppe_port_link_int_mask_port3_link_chg_int_mask_set( - a_uint32_t dev_id, - a_uint32_t value) -{ - union port_link_int_mask_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_port_link_int_mask_get(dev_id, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.port3_link_chg_int_mask = value; - ret = hppe_port_link_int_mask_set(dev_id, ®_val); - return ret; -} - -sw_error_t -hppe_port_link_int_mask_port5_1_link_chg_int_mask_get( - a_uint32_t dev_id, - a_uint32_t *value) -{ - union port_link_int_mask_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_port_link_int_mask_get(dev_id, ®_val); - *value = reg_val.bf.port5_1_link_chg_int_mask; - return ret; -} - -sw_error_t -hppe_port_link_int_mask_port5_1_link_chg_int_mask_set( - a_uint32_t dev_id, - a_uint32_t value) -{ - union port_link_int_mask_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_port_link_int_mask_get(dev_id, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.port5_1_link_chg_int_mask = value; - ret = hppe_port_link_int_mask_set(dev_id, ®_val); - return ret; -} - -sw_error_t -hppe_port_link_int_mask_xgmac1_an_done_int_mask_get( - a_uint32_t dev_id, - a_uint32_t *value) -{ - union port_link_int_mask_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_port_link_int_mask_get(dev_id, ®_val); - *value = reg_val.bf.xgmac1_an_done_int_mask; - return ret; -} - -sw_error_t -hppe_port_link_int_mask_xgmac1_an_done_int_mask_set( - a_uint32_t dev_id, - a_uint32_t value) -{ - union port_link_int_mask_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_port_link_int_mask_get(dev_id, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.xgmac1_an_done_int_mask = value; - ret = hppe_port_link_int_mask_set(dev_id, ®_val); - return ret; -} - -sw_error_t -hppe_port_link_int_mask_port1_link_chg_int_mask_get( - a_uint32_t dev_id, - a_uint32_t *value) -{ - union port_link_int_mask_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_port_link_int_mask_get(dev_id, ®_val); - *value = reg_val.bf.port1_link_chg_int_mask; - return ret; -} - -sw_error_t -hppe_port_link_int_mask_port1_link_chg_int_mask_set( - a_uint32_t dev_id, - a_uint32_t value) -{ - union port_link_int_mask_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_port_link_int_mask_get(dev_id, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.port1_link_chg_int_mask = value; - ret = hppe_port_link_int_mask_set(dev_id, ®_val); - return ret; -} - -sw_error_t -hppe_port_link_int_mask_port5_0_link_chg_int_mask_get( - a_uint32_t dev_id, - a_uint32_t *value) -{ - union port_link_int_mask_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_port_link_int_mask_get(dev_id, ®_val); - *value = reg_val.bf.port5_0_link_chg_int_mask; - return ret; -} - -sw_error_t -hppe_port_link_int_mask_port5_0_link_chg_int_mask_set( - a_uint32_t dev_id, - a_uint32_t value) -{ - union port_link_int_mask_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_port_link_int_mask_get(dev_id, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.port5_0_link_chg_int_mask = value; - ret = hppe_port_link_int_mask_set(dev_id, ®_val); - return ret; -} - -sw_error_t -hppe_port_link_int_mask_port6_link_chg_int_mask_get( - a_uint32_t dev_id, - a_uint32_t *value) -{ - union port_link_int_mask_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_port_link_int_mask_get(dev_id, ®_val); - *value = reg_val.bf.port6_link_chg_int_mask; - return ret; -} - -sw_error_t -hppe_port_link_int_mask_port6_link_chg_int_mask_set( - a_uint32_t dev_id, - a_uint32_t value) -{ - union port_link_int_mask_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_port_link_int_mask_get(dev_id, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.port6_link_chg_int_mask = value; - ret = hppe_port_link_int_mask_set(dev_id, ®_val); - return ret; -} - -sw_error_t -hppe_port_phy_status_0_port3_phy_status_get( - a_uint32_t dev_id, - a_uint32_t *value) -{ - union port_phy_status_0_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_port_phy_status_0_get(dev_id, ®_val); - *value = reg_val.bf.port3_phy_status; - return ret; -} - -sw_error_t -hppe_port_phy_status_0_port3_phy_status_set( - a_uint32_t dev_id, - a_uint32_t value) -{ - return SW_NOT_SUPPORTED; -} - -sw_error_t -hppe_port_phy_status_0_port4_phy_status_get( - a_uint32_t dev_id, - a_uint32_t *value) -{ - union port_phy_status_0_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_port_phy_status_0_get(dev_id, ®_val); - *value = reg_val.bf.port4_phy_status; - return ret; -} - -sw_error_t -hppe_port_phy_status_0_port4_phy_status_set( - a_uint32_t dev_id, - a_uint32_t value) -{ - return SW_NOT_SUPPORTED; -} - -sw_error_t -hppe_port_phy_status_0_port2_phy_status_get( - a_uint32_t dev_id, - a_uint32_t *value) -{ - union port_phy_status_0_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_port_phy_status_0_get(dev_id, ®_val); - *value = reg_val.bf.port2_phy_status; - return ret; -} - -sw_error_t -hppe_port_phy_status_0_port2_phy_status_set( - a_uint32_t dev_id, - a_uint32_t value) -{ - return SW_NOT_SUPPORTED; -} - -sw_error_t -hppe_port_phy_status_0_port1_phy_status_get( - a_uint32_t dev_id, - a_uint32_t *value) -{ - union port_phy_status_0_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_port_phy_status_0_get(dev_id, ®_val); - *value = reg_val.bf.port1_phy_status; - return ret; -} - -sw_error_t -hppe_port_phy_status_0_port1_phy_status_set( - a_uint32_t dev_id, - a_uint32_t value) -{ - return SW_NOT_SUPPORTED; -} - -sw_error_t -hppe_port_phy_status_1_port6_phy_status_get( - a_uint32_t dev_id, - a_uint32_t *value) -{ - union port_phy_status_1_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_port_phy_status_1_get(dev_id, ®_val); - *value = reg_val.bf.port6_phy_status; - return ret; -} - -sw_error_t -hppe_port_phy_status_1_port6_phy_status_set( - a_uint32_t dev_id, - a_uint32_t value) -{ - return SW_NOT_SUPPORTED; -} - -sw_error_t -hppe_port_phy_status_1_port5_0_phy_status_get( - a_uint32_t dev_id, - a_uint32_t *value) -{ - union port_phy_status_1_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_port_phy_status_1_get(dev_id, ®_val); - *value = reg_val.bf.port5_0_phy_status; - return ret; -} - -sw_error_t -hppe_port_phy_status_1_port5_0_phy_status_set( - a_uint32_t dev_id, - a_uint32_t value) -{ - return SW_NOT_SUPPORTED; -} - -sw_error_t -hppe_port_phy_status_1_port5_1_phy_status_get( - a_uint32_t dev_id, - a_uint32_t *value) -{ - union port_phy_status_1_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_port_phy_status_1_get(dev_id, ®_val); - *value = reg_val.bf.port5_1_phy_status; - return ret; -} - -sw_error_t -hppe_port_phy_status_1_port5_1_phy_status_set( - a_uint32_t dev_id, - a_uint32_t value) -{ - return SW_NOT_SUPPORTED; -} - -sw_error_t -hppe_port1_status_port1_status_get( - a_uint32_t dev_id, - a_uint32_t *value) -{ - union port1_status_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_port1_status_get(dev_id, ®_val); - *value = reg_val.bf.port1_status; - return ret; -} - -sw_error_t -hppe_port1_status_port1_status_set( - a_uint32_t dev_id, - a_uint32_t value) -{ - return SW_NOT_SUPPORTED; -} - -sw_error_t -hppe_port2_status_port2_status_get( - a_uint32_t dev_id, - a_uint32_t *value) -{ - union port2_status_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_port2_status_get(dev_id, ®_val); - *value = reg_val.bf.port2_status; - return ret; -} - -sw_error_t -hppe_port2_status_port2_status_set( - a_uint32_t dev_id, - a_uint32_t value) -{ - return SW_NOT_SUPPORTED; -} - -sw_error_t -hppe_port3_status_port3_status_get( - a_uint32_t dev_id, - a_uint32_t *value) -{ - union port3_status_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_port3_status_get(dev_id, ®_val); - *value = reg_val.bf.port3_status; - return ret; -} - -sw_error_t -hppe_port3_status_port3_status_set( - a_uint32_t dev_id, - a_uint32_t value) -{ - return SW_NOT_SUPPORTED; -} - -sw_error_t -hppe_port4_status_port4_status_get( - a_uint32_t dev_id, - a_uint32_t *value) -{ - union port4_status_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_port4_status_get(dev_id, ®_val); - *value = reg_val.bf.port4_status; - return ret; -} - -sw_error_t -hppe_port4_status_port4_status_set( - a_uint32_t dev_id, - a_uint32_t value) -{ - return SW_NOT_SUPPORTED; -} - -sw_error_t -hppe_port5_status_port3_mac_speed_get( - a_uint32_t dev_id, - a_uint32_t *value) -{ - union port5_status_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_port5_status_get(dev_id, ®_val); - *value = reg_val.bf.port3_mac_speed; - return ret; -} - -sw_error_t -hppe_port5_status_port3_mac_speed_set( - a_uint32_t dev_id, - a_uint32_t value) -{ - return SW_NOT_SUPPORTED; -} - -sw_error_t -hppe_port5_status_port2_mac_speed_get( - a_uint32_t dev_id, - a_uint32_t *value) -{ - union port5_status_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_port5_status_get(dev_id, ®_val); - *value = reg_val.bf.port2_mac_speed; - return ret; -} - -sw_error_t -hppe_port5_status_port2_mac_speed_set( - a_uint32_t dev_id, - a_uint32_t value) -{ - return SW_NOT_SUPPORTED; -} - -sw_error_t -hppe_port5_status_port1_mac_speed_get( - a_uint32_t dev_id, - a_uint32_t *value) -{ - union port5_status_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_port5_status_get(dev_id, ®_val); - *value = reg_val.bf.port1_mac_speed; - return ret; -} - -sw_error_t -hppe_port5_status_port1_mac_speed_set( - a_uint32_t dev_id, - a_uint32_t value) -{ - return SW_NOT_SUPPORTED; -} - -sw_error_t -hppe_port5_status_port5_status_get( - a_uint32_t dev_id, - a_uint32_t *value) -{ - union port5_status_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_port5_status_get(dev_id, ®_val); - *value = reg_val.bf.port5_status; - return ret; -} - -sw_error_t -hppe_port5_status_port5_status_set( - a_uint32_t dev_id, - a_uint32_t value) -{ - return SW_NOT_SUPPORTED; -} - -sw_error_t -hppe_port5_status_port4_mac_speed_get( - a_uint32_t dev_id, - a_uint32_t *value) -{ - union port5_status_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_port5_status_get(dev_id, ®_val); - *value = reg_val.bf.port4_mac_speed; - return ret; -} - -sw_error_t -hppe_port5_status_port4_mac_speed_set( - a_uint32_t dev_id, - a_uint32_t value) -{ - return SW_NOT_SUPPORTED; -} - -sw_error_t -hppe_port6_status_port6_status_get( - a_uint32_t dev_id, - a_uint32_t *value) -{ - union port6_status_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_port6_status_get(dev_id, ®_val); - *value = reg_val.bf.port6_status; - return ret; -} - -sw_error_t -hppe_port6_status_port6_status_set( - a_uint32_t dev_id, - a_uint32_t value) -{ - return SW_NOT_SUPPORTED; -} - -sw_error_t -hppe_reserved_regs_0_spare_regs_0_get( - a_uint32_t dev_id, - a_uint32_t *value) -{ - union reserved_regs_0_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_reserved_regs_0_get(dev_id, ®_val); - *value = reg_val.bf.spare_regs_0; - return ret; -} - -sw_error_t -hppe_reserved_regs_0_spare_regs_0_set( - a_uint32_t dev_id, - a_uint32_t value) -{ - union reserved_regs_0_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_reserved_regs_0_get(dev_id, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.spare_regs_0 = value; - ret = hppe_reserved_regs_0_set(dev_id, ®_val); - return ret; -} - -sw_error_t -hppe_reserved_regs_1_spare_regs_1_get( - a_uint32_t dev_id, - a_uint32_t *value) -{ - union reserved_regs_1_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_reserved_regs_1_get(dev_id, ®_val); - *value = reg_val.bf.spare_regs_1; - return ret; -} - -sw_error_t -hppe_reserved_regs_1_spare_regs_1_set( - a_uint32_t dev_id, - a_uint32_t value) -{ - union reserved_regs_1_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_reserved_regs_1_get(dev_id, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.spare_regs_1 = value; - ret = hppe_reserved_regs_1_set(dev_id, ®_val); - return ret; -} - -sw_error_t -hppe_reserved_regs_2_spare_regs_2_get( - a_uint32_t dev_id, - a_uint32_t *value) -{ - union reserved_regs_2_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_reserved_regs_2_get(dev_id, ®_val); - *value = reg_val.bf.spare_regs_2; - return ret; -} - -sw_error_t -hppe_reserved_regs_2_spare_regs_2_set( - a_uint32_t dev_id, - a_uint32_t value) -{ - union reserved_regs_2_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_reserved_regs_2_get(dev_id, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.spare_regs_2 = value; - ret = hppe_reserved_regs_2_set(dev_id, ®_val); - return ret; -} - -sw_error_t -hppe_reserved_regs_3_spare_regs_3_get( - a_uint32_t dev_id, - a_uint32_t *value) -{ - union reserved_regs_3_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_reserved_regs_3_get(dev_id, ®_val); - *value = reg_val.bf.spare_regs_3; - return ret; -} - -sw_error_t -hppe_reserved_regs_3_spare_regs_3_set( - a_uint32_t dev_id, - a_uint32_t value) -{ - union reserved_regs_3_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_reserved_regs_3_get(dev_id, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.spare_regs_3 = value; - ret = hppe_reserved_regs_3_set(dev_id, ®_val); - return ret; -} - -sw_error_t -hppe_dbg_data_sel_dbg_data_sel_desp_get( - a_uint32_t dev_id, - a_uint32_t *value) -{ - union dbg_data_sel_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_dbg_data_sel_get(dev_id, ®_val); - *value = reg_val.bf.dbg_data_sel_desp; - return ret; -} - -sw_error_t -hppe_dbg_data_sel_dbg_data_sel_desp_set( - a_uint32_t dev_id, - a_uint32_t value) -{ - union dbg_data_sel_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_dbg_data_sel_get(dev_id, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.dbg_data_sel_desp = value; - ret = hppe_dbg_data_sel_set(dev_id, ®_val); - return ret; -} - -sw_error_t -hppe_dbg_data_sel_dbg_data_sel_switch_get( - a_uint32_t dev_id, - a_uint32_t *value) -{ - union dbg_data_sel_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_dbg_data_sel_get(dev_id, ®_val); - *value = reg_val.bf.dbg_data_sel_switch; - return ret; -} - -sw_error_t -hppe_dbg_data_sel_dbg_data_sel_switch_set( - a_uint32_t dev_id, - a_uint32_t value) -{ - union dbg_data_sel_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_dbg_data_sel_get(dev_id, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.dbg_data_sel_switch = value; - ret = hppe_dbg_data_sel_set(dev_id, ®_val); - return ret; -} - diff --git a/feeds/ipq807x/qca-ssdk/src/src/hsl/hppe/hppe_init.c b/feeds/ipq807x/qca-ssdk/src/src/hsl/hppe/hppe_init.c deleted file mode 100755 index 1297d9c17..000000000 --- a/feeds/ipq807x/qca-ssdk/src/src/hsl/hppe/hppe_init.c +++ /dev/null @@ -1,234 +0,0 @@ -/* - * Copyright (c) 2016-2017, 2019, The Linux Foundation. All rights reserved. - * Permission to use, copy, modify, and/or distribute this software for - * any purpose with or without fee is hereby granted, provided that the - * above copyright notice and this permission notice appear in all copies. - * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES - * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR - * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES - * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN - * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT - * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. - */ - - -/** - * @defgroup dess_init HPPE_INIT - * @{ - */ -#include "sw.h" -#include "hsl.h" -#include "hsl_dev.h" -#include "hsl_port_prop.h" -#include "sd.h" -#include "hsl_phy.h" - - -static ssdk_init_cfg * hppe_cfg[SW_MAX_NR_DEV] = { 0 }; - -a_bool_t hppe_xgmac_port_check(fal_port_t port_id) -{ - return ((port_id == 5) ||( port_id == 6)); -} -a_bool_t hppe_mac_port_valid_check(a_uint32_t dev_id, fal_port_t port_id) -{ - a_uint32_t bitmap = 0; - - bitmap = qca_ssdk_port_bmp_get(dev_id); - - return SW_IS_PBMP_MEMBER(bitmap, port_id); - -} - -static sw_error_t -hppe_portproperty_init(a_uint32_t dev_id) -{ - hsl_port_prop_t p_type; - hsl_dev_t *pdev = NULL; - fal_port_t port_id; - a_uint32_t bitmap = 0; - a_uint32_t inner_pbmp = 0; - - pdev = hsl_dev_ptr_get(dev_id); - if (pdev == NULL) - return SW_NOT_INITIALIZED; - - bitmap = qca_ssdk_port_bmp_get(dev_id); - inner_pbmp = hsl_dev_inner_ports_get(dev_id); - - /* for port property set, SSDK should not generate some limitations */ - for (port_id = 0; port_id < SW_MAX_NR_PORT; port_id++) - { - if ((port_id == pdev->cpu_port_nr) || - (bitmap & (0x1 << port_id)) || - (inner_pbmp & (0x1 << port_id))) - { - hsl_port_prop_portmap_set(dev_id, port_id); - - for (p_type = HSL_PP_PHY; p_type < HSL_PP_BUTT; p_type++) - { - switch (p_type) - { - case HSL_PP_PHY:/*front ports*/ - if (SW_IS_PBMP_MEMBER(bitmap, port_id)) - { - SW_RTN_ON_ERROR - (hsl_port_prop_set(dev_id, port_id,p_type)); - } - break; - - case HSL_PP_INNER:/*inner ports*/ - if (SW_IS_PBMP_MEMBER(inner_pbmp, port_id)) - { - SW_RTN_ON_ERROR - (hsl_port_prop_set(dev_id, port_id,p_type)); - } - break; - - case HSL_PP_INCL_CPU: - /*the ports include cpu port*/ - SW_RTN_ON_ERROR - (hsl_port_prop_set(dev_id, port_id, p_type)); - break; - - case HSL_PP_EXCL_CPU: - /*the ports exclude cpu port*/ - if (port_id != pdev->cpu_port_nr) - { - SW_RTN_ON_ERROR - (hsl_port_prop_set(dev_id, port_id,p_type)); - } - break; - - case HSL_PP_CPU:/*cpu port*/ - if (port_id == pdev->cpu_port_nr) - { - SW_RTN_ON_ERROR - (hsl_port_prop_set(dev_id, port_id,p_type)); - } - break; - - default: - break; - } - } - } - } - return SW_OK; -} - -static sw_error_t -hppe_dev_init(a_uint32_t dev_id, ssdk_init_cfg *cfg) -{ - hsl_dev_t *pdev = NULL; - a_uint32_t i = 0, port_nr = 0, tmp = 0; - - pdev = hsl_dev_ptr_get(dev_id); - if (pdev == NULL) - return SW_NOT_INITIALIZED; - - tmp = cfg->port_cfg.lan_bmp | cfg->port_cfg.wan_bmp; - for(i = 0; i < SW_MAX_NR_PORT; i++) { - if(tmp & (1 << i)) { - port_nr++; - } - } - pdev->nr_phy = port_nr; - - for(i = 0; i < SW_MAX_NR_PORT; i++) { - if(cfg->port_cfg.inner_bmp & (1 << i)) { - port_nr++; - } - } - - for(i = 0; i < SW_MAX_NR_PORT; i++) { - if(cfg->port_cfg.cpu_bmp & (1 << i)) { - port_nr++; - pdev->cpu_port_nr = i; - break; - } - } - if(i >= SW_MAX_NR_PORT) - return SW_BAD_VALUE; - pdev->nr_ports = port_nr; - pdev->nr_vlans = 4096; - pdev->hw_vlan_query = A_TRUE; - pdev->nr_queue = port_nr; - pdev->cpu_mode = cfg->cpu_mode; - pdev->wan_bmp = cfg->port_cfg.wan_bmp; - - return SW_OK; -} - -sw_error_t -hppe_cleanup(a_uint32_t dev_id) -{ - - if (hppe_cfg[dev_id]) - { - SW_RTN_ON_ERROR(hsl_port_prop_cleanup_by_dev(dev_id)); - - aos_mem_free(hppe_cfg[dev_id]); - hppe_cfg[dev_id] = NULL; - } - - return SW_OK; -} - -/** - * @brief Init hsl layer. - * @details Comments: - * This operation will init hsl layer and hsl layer - * @param[in] dev_id device id - * @param[in] cfg configuration for initialization - * @return SW_OK or error code - */ -sw_error_t hppe_init(a_uint32_t dev_id, ssdk_init_cfg *cfg) -{ - HSL_DEV_ID_CHECK(dev_id); - - printk("HPPE initializing...\n"); - if (NULL == hppe_cfg[dev_id]) - { - hppe_cfg[dev_id] = aos_mem_alloc(sizeof (ssdk_init_cfg)); - } - - if (NULL == hppe_cfg[dev_id]) - { - return SW_OUT_OF_MEM; - } - - aos_mem_copy(hppe_cfg[dev_id], cfg, sizeof (ssdk_init_cfg)); - - SW_RTN_ON_ERROR(hppe_dev_init(dev_id, cfg)); - -#if !(defined(KERNEL_MODULE) && defined(USER_MODE)) - { - hsl_api_t *p_api; - - SW_RTN_ON_ERROR(hsl_port_prop_init(dev_id)); - SW_RTN_ON_ERROR(hsl_port_prop_init_by_dev(dev_id)); - SW_RTN_ON_ERROR(hppe_portproperty_init(dev_id)); - - SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id)); - p_api->dev_clean = hppe_cleanup; - p_api->reg_get = sd_reg_hdr_get; - p_api->reg_set = sd_reg_hdr_set; - p_api->phy_get = sd_reg_mdio_get; - p_api->phy_set = sd_reg_mdio_set; - p_api->phy_i2c_get = sd_reg_i2c_get; - p_api->phy_i2c_set = sd_reg_i2c_set; - p_api->uniphy_reg_get = sd_reg_uniphy_get; - p_api->uniphy_reg_set = sd_reg_uniphy_set; - - } -#endif - - return SW_OK; -} - -/** - * @} - */ - diff --git a/feeds/ipq807x/qca-ssdk/src/src/hsl/hppe/hppe_ip.c b/feeds/ipq807x/qca-ssdk/src/src/hsl/hppe/hppe_ip.c deleted file mode 100755 index 81af477cb..000000000 --- a/feeds/ipq807x/qca-ssdk/src/src/hsl/hppe/hppe_ip.c +++ /dev/null @@ -1,6892 +0,0 @@ -/* - * Copyright (c) 2016-2017, The Linux Foundation. All rights reserved. - * Permission to use, copy, modify, and/or distribute this software for - * any purpose with or without fee is hereby granted, provided that the - * above copyright notice and this permission notice appear in all copies. - * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES - * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR - * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES - * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN - * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT - * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. - */ - - -/** - * @defgroup - * @{ - */ -#include "sw.h" -#include "hsl.h" -#include "hppe_reg_access.h" -#include "hppe_ip_reg.h" -#include "hppe_ip.h" - -#ifndef IN_IP_MINI -static a_uint32_t host_cmd_id = 0; -sw_error_t -hppe_rt_interface_cnt_tbl_get( - a_uint32_t dev_id, - a_uint32_t index, - union rt_interface_cnt_tbl_u *value) -{ - return hppe_reg_tbl_get( - dev_id, - INGRESS_POLICER_BASE_ADDR + RT_INTERFACE_CNT_TBL_ADDRESS + \ - index * RT_INTERFACE_CNT_TBL_INC, - value->val, - 5); -} - -sw_error_t -hppe_rt_interface_cnt_tbl_set( - a_uint32_t dev_id, - a_uint32_t index, - union rt_interface_cnt_tbl_u *value) -{ - return hppe_reg_tbl_set( - dev_id, - INGRESS_POLICER_BASE_ADDR + RT_INTERFACE_CNT_TBL_ADDRESS + \ - index * RT_INTERFACE_CNT_TBL_INC, - value->val, - 5); -} - -sw_error_t -hppe_my_mac_tbl_get( - a_uint32_t dev_id, - a_uint32_t index, - union my_mac_tbl_u *value) -{ - return hppe_reg_tbl_get( - dev_id, - IPE_L3_BASE_ADDR + MY_MAC_TBL_ADDRESS + \ - index * MY_MAC_TBL_INC, - value->val, - 2); -} - -sw_error_t -hppe_my_mac_tbl_set( - a_uint32_t dev_id, - a_uint32_t index, - union my_mac_tbl_u *value) -{ - return hppe_reg_tbl_set( - dev_id, - IPE_L3_BASE_ADDR + MY_MAC_TBL_ADDRESS + \ - index * MY_MAC_TBL_INC, - value->val, - 2); -} - -sw_error_t -hppe_l3_vsi_get( - a_uint32_t dev_id, - a_uint32_t index, - union l3_vsi_u *value) -{ - if (index >= L3_VSI_MAX_ENTRY) - return SW_OUT_OF_RANGE; - return hppe_reg_get( - dev_id, - IPE_L3_BASE_ADDR + L3_VSI_ADDRESS + \ - index * L3_VSI_INC, - &value->val); -} - -sw_error_t -hppe_l3_vsi_set( - a_uint32_t dev_id, - a_uint32_t index, - union l3_vsi_u *value) -{ - return hppe_reg_set( - dev_id, - IPE_L3_BASE_ADDR + L3_VSI_ADDRESS + \ - index * L3_VSI_INC, - value->val); -} - -sw_error_t -hppe_l3_vsi_ext_get( - a_uint32_t dev_id, - a_uint32_t index, - union l3_vsi_ext_u *value) -{ - if (index >= L3_VSI_EXT_MAX_ENTRY) - return SW_OUT_OF_RANGE; - return hppe_reg_get( - dev_id, - IPE_L3_BASE_ADDR + L3_VSI_EXT_ADDRESS + \ - index * L3_VSI_EXT_INC, - &value->val); -} - -sw_error_t -hppe_l3_vsi_ext_set( - a_uint32_t dev_id, - a_uint32_t index, - union l3_vsi_ext_u *value) -{ - return hppe_reg_set( - dev_id, - IPE_L3_BASE_ADDR + L3_VSI_EXT_ADDRESS + \ - index * L3_VSI_EXT_INC, - value->val); -} - -sw_error_t -hppe_network_route_ip_get( - a_uint32_t dev_id, - a_uint32_t index, - union network_route_ip_u *value) -{ - return hppe_reg_tbl_get( - dev_id, - IPE_L3_BASE_ADDR + NETWORK_ROUTE_IP_ADDRESS + \ - index * NETWORK_ROUTE_IP_INC, - value->val, - 2); -} - -sw_error_t -hppe_in_pub_ip_addr_tbl_set( - a_uint32_t dev_id, - a_uint32_t index, - union in_pub_ip_addr_tbl_u *value) -{ - return hppe_reg_set( - dev_id, - IPE_L3_BASE_ADDR + IN_PUB_IP_ADDR_TBL_ADDRESS + \ - index * IN_PUB_IP_ADDR_TBL_INC, - value->val); -} - - -sw_error_t -hppe_in_pub_ip_addr_tbl_get( - a_uint32_t dev_id, - a_uint32_t index, - union in_pub_ip_addr_tbl_u *value) -{ - if (index >= IN_PUB_IP_ADDR_TBL_MAX_ENTRY) - return SW_OUT_OF_RANGE; - return hppe_reg_get( - dev_id, - IPE_L3_BASE_ADDR + IN_PUB_IP_ADDR_TBL_ADDRESS + \ - index * IN_PUB_IP_ADDR_TBL_INC, - &value->val); -} - -sw_error_t -hppe_network_route_ip_set( - a_uint32_t dev_id, - a_uint32_t index, - union network_route_ip_u *value) -{ - return hppe_reg_tbl_set( - dev_id, - IPE_L3_BASE_ADDR + NETWORK_ROUTE_IP_ADDRESS + \ - index * NETWORK_ROUTE_IP_INC, - value->val, - 2); -} - -sw_error_t -hppe_network_route_ip_ext_get( - a_uint32_t dev_id, - a_uint32_t index, - union network_route_ip_ext_u *value) -{ - if (index >= NETWORK_ROUTE_IP_EXT_MAX_ENTRY) - return SW_OUT_OF_RANGE; - return hppe_reg_get( - dev_id, - IPE_L3_BASE_ADDR + NETWORK_ROUTE_IP_EXT_ADDRESS + \ - index * NETWORK_ROUTE_IP_EXT_INC, - &value->val); -} - -sw_error_t -hppe_network_route_ip_ext_set( - a_uint32_t dev_id, - a_uint32_t index, - union network_route_ip_ext_u *value) -{ - return hppe_reg_set( - dev_id, - IPE_L3_BASE_ADDR + NETWORK_ROUTE_IP_EXT_ADDRESS + \ - index * NETWORK_ROUTE_IP_EXT_INC, - value->val); -} - -sw_error_t -hppe_network_route_action_get( - a_uint32_t dev_id, - a_uint32_t index, - union network_route_action_u *value) -{ - if (index >= NETWORK_ROUTE_ACTION_MAX_ENTRY) - return SW_OUT_OF_RANGE; - return hppe_reg_get( - dev_id, - IPE_L3_BASE_ADDR + NETWORK_ROUTE_ACTION_ADDRESS + \ - index * NETWORK_ROUTE_ACTION_INC, - &value->val); -} - -sw_error_t -hppe_network_route_action_set( - a_uint32_t dev_id, - a_uint32_t index, - union network_route_action_u *value) -{ - return hppe_reg_set( - dev_id, - IPE_L3_BASE_ADDR + NETWORK_ROUTE_ACTION_ADDRESS + \ - index * NETWORK_ROUTE_ACTION_INC, - value->val); -} -#endif -#if ((!defined IN_IP_MINI) || (!defined IN_FLOW_MINI)) -sw_error_t -hppe_l3_route_ctrl_get( - a_uint32_t dev_id, - union l3_route_ctrl_u *value) -{ - return hppe_reg_get( - dev_id, - IPE_L3_BASE_ADDR + L3_ROUTE_CTRL_ADDRESS, - &value->val); -} - -sw_error_t -hppe_l3_route_ctrl_set( - a_uint32_t dev_id, - union l3_route_ctrl_u *value) -{ - return hppe_reg_set( - dev_id, - IPE_L3_BASE_ADDR + L3_ROUTE_CTRL_ADDRESS, - value->val); -} - -sw_error_t -hppe_l3_route_ctrl_ext_get( - a_uint32_t dev_id, - union l3_route_ctrl_ext_u *value) -{ - return hppe_reg_get( - dev_id, - IPE_L3_BASE_ADDR + L3_ROUTE_CTRL_EXT_ADDRESS, - &value->val); -} - -sw_error_t -hppe_l3_route_ctrl_ext_set( - a_uint32_t dev_id, - union l3_route_ctrl_ext_u *value) -{ - return hppe_reg_set( - dev_id, - IPE_L3_BASE_ADDR + L3_ROUTE_CTRL_EXT_ADDRESS, - value->val); -} -#endif -#ifndef IN_IP_MINI -sw_error_t -hppe_host_tbl_op_get( - a_uint32_t dev_id, - union host_tbl_op_u *value) -{ - return hppe_reg_get( - dev_id, - IPE_L3_BASE_ADDR + HOST_TBL_OP_ADDRESS, - &value->val); -} - -sw_error_t -hppe_host_tbl_op_set( - a_uint32_t dev_id, - union host_tbl_op_u *value) -{ - return hppe_reg_set( - dev_id, - IPE_L3_BASE_ADDR + HOST_TBL_OP_ADDRESS, - value->val); -} -#endif -#if ((!defined IN_IP_MINI) || (!defined IN_FLOW_MINI)) -sw_error_t -hppe_host_tbl_op_data0_get( - a_uint32_t dev_id, - union host_tbl_op_data0_u *value) -{ - return hppe_reg_get( - dev_id, - IPE_L3_BASE_ADDR + HOST_TBL_OP_DATA0_ADDRESS, - &value->val); -} - -sw_error_t -hppe_host_tbl_op_data0_set( - a_uint32_t dev_id, - union host_tbl_op_data0_u *value) -{ - return hppe_reg_set( - dev_id, - IPE_L3_BASE_ADDR + HOST_TBL_OP_DATA0_ADDRESS, - value->val); -} - -sw_error_t -hppe_host_tbl_op_data1_get( - a_uint32_t dev_id, - union host_tbl_op_data1_u *value) -{ - return hppe_reg_get( - dev_id, - IPE_L3_BASE_ADDR + HOST_TBL_OP_DATA1_ADDRESS, - &value->val); -} - -sw_error_t -hppe_host_tbl_op_data1_set( - a_uint32_t dev_id, - union host_tbl_op_data1_u *value) -{ - return hppe_reg_set( - dev_id, - IPE_L3_BASE_ADDR + HOST_TBL_OP_DATA1_ADDRESS, - value->val); -} - -sw_error_t -hppe_host_tbl_op_data2_get( - a_uint32_t dev_id, - union host_tbl_op_data2_u *value) -{ - return hppe_reg_get( - dev_id, - IPE_L3_BASE_ADDR + HOST_TBL_OP_DATA2_ADDRESS, - &value->val); -} - -sw_error_t -hppe_host_tbl_op_data2_set( - a_uint32_t dev_id, - union host_tbl_op_data2_u *value) -{ - return hppe_reg_set( - dev_id, - IPE_L3_BASE_ADDR + HOST_TBL_OP_DATA2_ADDRESS, - value->val); -} - -sw_error_t -hppe_host_tbl_op_data3_get( - a_uint32_t dev_id, - union host_tbl_op_data3_u *value) -{ - return hppe_reg_get( - dev_id, - IPE_L3_BASE_ADDR + HOST_TBL_OP_DATA3_ADDRESS, - &value->val); -} - -sw_error_t -hppe_host_tbl_op_data3_set( - a_uint32_t dev_id, - union host_tbl_op_data3_u *value) -{ - return hppe_reg_set( - dev_id, - IPE_L3_BASE_ADDR + HOST_TBL_OP_DATA3_ADDRESS, - value->val); -} - -sw_error_t -hppe_host_tbl_op_data4_get( - a_uint32_t dev_id, - union host_tbl_op_data4_u *value) -{ - return hppe_reg_get( - dev_id, - IPE_L3_BASE_ADDR + HOST_TBL_OP_DATA4_ADDRESS, - &value->val); -} - -sw_error_t -hppe_host_tbl_op_data4_set( - a_uint32_t dev_id, - union host_tbl_op_data4_u *value) -{ - return hppe_reg_set( - dev_id, - IPE_L3_BASE_ADDR + HOST_TBL_OP_DATA4_ADDRESS, - value->val); -} -#endif -#ifndef IN_IP_MINI -sw_error_t -hppe_host_tbl_op_data5_get( - a_uint32_t dev_id, - union host_tbl_op_data5_u *value) -{ - return hppe_reg_get( - dev_id, - IPE_L3_BASE_ADDR + HOST_TBL_OP_DATA5_ADDRESS, - &value->val); -} - -sw_error_t -hppe_host_tbl_op_data5_set( - a_uint32_t dev_id, - union host_tbl_op_data5_u *value) -{ - return hppe_reg_set( - dev_id, - IPE_L3_BASE_ADDR + HOST_TBL_OP_DATA5_ADDRESS, - value->val); -} - -sw_error_t -hppe_host_tbl_op_data6_get( - a_uint32_t dev_id, - union host_tbl_op_data6_u *value) -{ - return hppe_reg_get( - dev_id, - IPE_L3_BASE_ADDR + HOST_TBL_OP_DATA6_ADDRESS, - &value->val); -} - -sw_error_t -hppe_host_tbl_op_data6_set( - a_uint32_t dev_id, - union host_tbl_op_data6_u *value) -{ - return hppe_reg_set( - dev_id, - IPE_L3_BASE_ADDR + HOST_TBL_OP_DATA6_ADDRESS, - value->val); -} - -sw_error_t -hppe_host_tbl_op_data7_get( - a_uint32_t dev_id, - union host_tbl_op_data7_u *value) -{ - return hppe_reg_get( - dev_id, - IPE_L3_BASE_ADDR + HOST_TBL_OP_DATA7_ADDRESS, - &value->val); -} - -sw_error_t -hppe_host_tbl_op_data7_set( - a_uint32_t dev_id, - union host_tbl_op_data7_u *value) -{ - return hppe_reg_set( - dev_id, - IPE_L3_BASE_ADDR + HOST_TBL_OP_DATA7_ADDRESS, - value->val); -} - -sw_error_t -hppe_host_tbl_op_data8_get( - a_uint32_t dev_id, - union host_tbl_op_data8_u *value) -{ - return hppe_reg_get( - dev_id, - IPE_L3_BASE_ADDR + HOST_TBL_OP_DATA8_ADDRESS, - &value->val); -} - -sw_error_t -hppe_host_tbl_op_data8_set( - a_uint32_t dev_id, - union host_tbl_op_data8_u *value) -{ - return hppe_reg_set( - dev_id, - IPE_L3_BASE_ADDR + HOST_TBL_OP_DATA8_ADDRESS, - value->val); -} - -sw_error_t -hppe_host_tbl_op_data9_get( - a_uint32_t dev_id, - union host_tbl_op_data9_u *value) -{ - return hppe_reg_get( - dev_id, - IPE_L3_BASE_ADDR + HOST_TBL_OP_DATA9_ADDRESS, - &value->val); -} - -sw_error_t -hppe_host_tbl_op_data9_set( - a_uint32_t dev_id, - union host_tbl_op_data9_u *value) -{ - return hppe_reg_set( - dev_id, - IPE_L3_BASE_ADDR + HOST_TBL_OP_DATA9_ADDRESS, - value->val); -} - -sw_error_t -hppe_host_tbl_op_rslt_get( - a_uint32_t dev_id, - union host_tbl_op_rslt_u *value) -{ - return hppe_reg_get( - dev_id, - IPE_L3_BASE_ADDR + HOST_TBL_OP_RSLT_ADDRESS, - &value->val); -} - -sw_error_t -hppe_host_tbl_op_rslt_set( - a_uint32_t dev_id, - union host_tbl_op_rslt_u *value) -{ - return SW_NOT_SUPPORTED; -} - -sw_error_t -hppe_host_tbl_rd_op_get( - a_uint32_t dev_id, - union host_tbl_rd_op_u *value) -{ - return hppe_reg_get( - dev_id, - IPE_L3_BASE_ADDR + HOST_TBL_RD_OP_ADDRESS, - &value->val); -} - -sw_error_t -hppe_host_tbl_rd_op_set( - a_uint32_t dev_id, - union host_tbl_rd_op_u *value) -{ - return hppe_reg_set( - dev_id, - IPE_L3_BASE_ADDR + HOST_TBL_RD_OP_ADDRESS, - value->val); -} -#endif -#if ((!defined IN_IP_MINI) || (!defined IN_FLOW_MINI)) -sw_error_t -hppe_host_tbl_rd_op_data0_get( - a_uint32_t dev_id, - union host_tbl_rd_op_data0_u *value) -{ - return hppe_reg_get( - dev_id, - IPE_L3_BASE_ADDR + HOST_TBL_RD_OP_DATA0_ADDRESS, - &value->val); -} - -sw_error_t -hppe_host_tbl_rd_op_data0_set( - a_uint32_t dev_id, - union host_tbl_rd_op_data0_u *value) -{ - return hppe_reg_set( - dev_id, - IPE_L3_BASE_ADDR + HOST_TBL_RD_OP_DATA0_ADDRESS, - value->val); -} - -sw_error_t -hppe_host_tbl_rd_op_data1_get( - a_uint32_t dev_id, - union host_tbl_rd_op_data1_u *value) -{ - return hppe_reg_get( - dev_id, - IPE_L3_BASE_ADDR + HOST_TBL_RD_OP_DATA1_ADDRESS, - &value->val); -} - -sw_error_t -hppe_host_tbl_rd_op_data1_set( - a_uint32_t dev_id, - union host_tbl_rd_op_data1_u *value) -{ - return hppe_reg_set( - dev_id, - IPE_L3_BASE_ADDR + HOST_TBL_RD_OP_DATA1_ADDRESS, - value->val); -} - -sw_error_t -hppe_host_tbl_rd_op_data2_get( - a_uint32_t dev_id, - union host_tbl_rd_op_data2_u *value) -{ - return hppe_reg_get( - dev_id, - IPE_L3_BASE_ADDR + HOST_TBL_RD_OP_DATA2_ADDRESS, - &value->val); -} - -sw_error_t -hppe_host_tbl_rd_op_data2_set( - a_uint32_t dev_id, - union host_tbl_rd_op_data2_u *value) -{ - return hppe_reg_set( - dev_id, - IPE_L3_BASE_ADDR + HOST_TBL_RD_OP_DATA2_ADDRESS, - value->val); -} - -sw_error_t -hppe_host_tbl_rd_op_data3_get( - a_uint32_t dev_id, - union host_tbl_rd_op_data3_u *value) -{ - return hppe_reg_get( - dev_id, - IPE_L3_BASE_ADDR + HOST_TBL_RD_OP_DATA3_ADDRESS, - &value->val); -} - -sw_error_t -hppe_host_tbl_rd_op_data3_set( - a_uint32_t dev_id, - union host_tbl_rd_op_data3_u *value) -{ - return hppe_reg_set( - dev_id, - IPE_L3_BASE_ADDR + HOST_TBL_RD_OP_DATA3_ADDRESS, - value->val); -} - -sw_error_t -hppe_host_tbl_rd_op_data4_get( - a_uint32_t dev_id, - union host_tbl_rd_op_data4_u *value) -{ - return hppe_reg_get( - dev_id, - IPE_L3_BASE_ADDR + HOST_TBL_RD_OP_DATA4_ADDRESS, - &value->val); -} - -sw_error_t -hppe_host_tbl_rd_op_data4_set( - a_uint32_t dev_id, - union host_tbl_rd_op_data4_u *value) -{ - return hppe_reg_set( - dev_id, - IPE_L3_BASE_ADDR + HOST_TBL_RD_OP_DATA4_ADDRESS, - value->val); -} -#endif -#ifndef IN_IP_MINI -sw_error_t -hppe_host_tbl_rd_op_data5_get( - a_uint32_t dev_id, - union host_tbl_rd_op_data5_u *value) -{ - return hppe_reg_get( - dev_id, - IPE_L3_BASE_ADDR + HOST_TBL_RD_OP_DATA5_ADDRESS, - &value->val); -} - -sw_error_t -hppe_host_tbl_rd_op_data5_set( - a_uint32_t dev_id, - union host_tbl_rd_op_data5_u *value) -{ - return hppe_reg_set( - dev_id, - IPE_L3_BASE_ADDR + HOST_TBL_RD_OP_DATA5_ADDRESS, - value->val); -} - -sw_error_t -hppe_host_tbl_rd_op_data6_get( - a_uint32_t dev_id, - union host_tbl_rd_op_data6_u *value) -{ - return hppe_reg_get( - dev_id, - IPE_L3_BASE_ADDR + HOST_TBL_RD_OP_DATA6_ADDRESS, - &value->val); -} - -sw_error_t -hppe_host_tbl_rd_op_data6_set( - a_uint32_t dev_id, - union host_tbl_rd_op_data6_u *value) -{ - return hppe_reg_set( - dev_id, - IPE_L3_BASE_ADDR + HOST_TBL_RD_OP_DATA6_ADDRESS, - value->val); -} - -sw_error_t -hppe_host_tbl_rd_op_data7_get( - a_uint32_t dev_id, - union host_tbl_rd_op_data7_u *value) -{ - return hppe_reg_get( - dev_id, - IPE_L3_BASE_ADDR + HOST_TBL_RD_OP_DATA7_ADDRESS, - &value->val); -} - -sw_error_t -hppe_host_tbl_rd_op_data7_set( - a_uint32_t dev_id, - union host_tbl_rd_op_data7_u *value) -{ - return hppe_reg_set( - dev_id, - IPE_L3_BASE_ADDR + HOST_TBL_RD_OP_DATA7_ADDRESS, - value->val); -} - -sw_error_t -hppe_host_tbl_rd_op_data8_get( - a_uint32_t dev_id, - union host_tbl_rd_op_data8_u *value) -{ - return hppe_reg_get( - dev_id, - IPE_L3_BASE_ADDR + HOST_TBL_RD_OP_DATA8_ADDRESS, - &value->val); -} - -sw_error_t -hppe_host_tbl_rd_op_data8_set( - a_uint32_t dev_id, - union host_tbl_rd_op_data8_u *value) -{ - return hppe_reg_set( - dev_id, - IPE_L3_BASE_ADDR + HOST_TBL_RD_OP_DATA8_ADDRESS, - value->val); -} - -sw_error_t -hppe_host_tbl_rd_op_data9_get( - a_uint32_t dev_id, - union host_tbl_rd_op_data9_u *value) -{ - return hppe_reg_get( - dev_id, - IPE_L3_BASE_ADDR + HOST_TBL_RD_OP_DATA9_ADDRESS, - &value->val); -} - -sw_error_t -hppe_host_tbl_rd_op_data9_set( - a_uint32_t dev_id, - union host_tbl_rd_op_data9_u *value) -{ - return hppe_reg_set( - dev_id, - IPE_L3_BASE_ADDR + HOST_TBL_RD_OP_DATA9_ADDRESS, - value->val); -} - -sw_error_t -hppe_host_tbl_rd_op_rslt_get( - a_uint32_t dev_id, - union host_tbl_rd_op_rslt_u *value) -{ - return hppe_reg_get( - dev_id, - IPE_L3_BASE_ADDR + HOST_TBL_RD_OP_RSLT_ADDRESS, - &value->val); -} - -sw_error_t -hppe_host_tbl_rd_op_rslt_set( - a_uint32_t dev_id, - union host_tbl_rd_op_rslt_u *value) -{ - return SW_NOT_SUPPORTED; -} - -sw_error_t -hppe_host_tbl_rd_rslt_data0_get( - a_uint32_t dev_id, - union host_tbl_rd_rslt_data0_u *value) -{ - return hppe_reg_get( - dev_id, - IPE_L3_BASE_ADDR + HOST_TBL_RD_RSLT_DATA0_ADDRESS, - &value->val); -} - -sw_error_t -hppe_host_tbl_rd_rslt_data0_set( - a_uint32_t dev_id, - union host_tbl_rd_rslt_data0_u *value) -{ - return SW_NOT_SUPPORTED; -} - -sw_error_t -hppe_host_tbl_rd_rslt_data1_get( - a_uint32_t dev_id, - union host_tbl_rd_rslt_data1_u *value) -{ - return hppe_reg_get( - dev_id, - IPE_L3_BASE_ADDR + HOST_TBL_RD_RSLT_DATA1_ADDRESS, - &value->val); -} - -sw_error_t -hppe_host_tbl_rd_rslt_data1_set( - a_uint32_t dev_id, - union host_tbl_rd_rslt_data1_u *value) -{ - return SW_NOT_SUPPORTED; -} - -sw_error_t -hppe_host_tbl_rd_rslt_data2_get( - a_uint32_t dev_id, - union host_tbl_rd_rslt_data2_u *value) -{ - return hppe_reg_get( - dev_id, - IPE_L3_BASE_ADDR + HOST_TBL_RD_RSLT_DATA2_ADDRESS, - &value->val); -} - -sw_error_t -hppe_host_tbl_rd_rslt_data2_set( - a_uint32_t dev_id, - union host_tbl_rd_rslt_data2_u *value) -{ - return SW_NOT_SUPPORTED; -} - -sw_error_t -hppe_host_tbl_rd_rslt_data3_get( - a_uint32_t dev_id, - union host_tbl_rd_rslt_data3_u *value) -{ - return hppe_reg_get( - dev_id, - IPE_L3_BASE_ADDR + HOST_TBL_RD_RSLT_DATA3_ADDRESS, - &value->val); -} - -sw_error_t -hppe_host_tbl_rd_rslt_data3_set( - a_uint32_t dev_id, - union host_tbl_rd_rslt_data3_u *value) -{ - return SW_NOT_SUPPORTED; -} - -sw_error_t -hppe_host_tbl_rd_rslt_data4_get( - a_uint32_t dev_id, - union host_tbl_rd_rslt_data4_u *value) -{ - return hppe_reg_get( - dev_id, - IPE_L3_BASE_ADDR + HOST_TBL_RD_RSLT_DATA4_ADDRESS, - &value->val); -} - -sw_error_t -hppe_host_tbl_rd_rslt_data4_set( - a_uint32_t dev_id, - union host_tbl_rd_rslt_data4_u *value) -{ - return SW_NOT_SUPPORTED; -} - -sw_error_t -hppe_host_tbl_rd_rslt_data5_get( - a_uint32_t dev_id, - union host_tbl_rd_rslt_data5_u *value) -{ - return hppe_reg_get( - dev_id, - IPE_L3_BASE_ADDR + HOST_TBL_RD_RSLT_DATA5_ADDRESS, - &value->val); -} - -sw_error_t -hppe_host_tbl_rd_rslt_data5_set( - a_uint32_t dev_id, - union host_tbl_rd_rslt_data5_u *value) -{ - return SW_NOT_SUPPORTED; -} - -sw_error_t -hppe_host_tbl_rd_rslt_data6_get( - a_uint32_t dev_id, - union host_tbl_rd_rslt_data6_u *value) -{ - return hppe_reg_get( - dev_id, - IPE_L3_BASE_ADDR + HOST_TBL_RD_RSLT_DATA6_ADDRESS, - &value->val); -} - -sw_error_t -hppe_host_tbl_rd_rslt_data6_set( - a_uint32_t dev_id, - union host_tbl_rd_rslt_data6_u *value) -{ - return SW_NOT_SUPPORTED; -} - -sw_error_t -hppe_host_tbl_rd_rslt_data7_get( - a_uint32_t dev_id, - union host_tbl_rd_rslt_data7_u *value) -{ - return hppe_reg_get( - dev_id, - IPE_L3_BASE_ADDR + HOST_TBL_RD_RSLT_DATA7_ADDRESS, - &value->val); -} - -sw_error_t -hppe_host_tbl_rd_rslt_data7_set( - a_uint32_t dev_id, - union host_tbl_rd_rslt_data7_u *value) -{ - return SW_NOT_SUPPORTED; -} - -sw_error_t -hppe_host_tbl_rd_rslt_data8_get( - a_uint32_t dev_id, - union host_tbl_rd_rslt_data8_u *value) -{ - return hppe_reg_get( - dev_id, - IPE_L3_BASE_ADDR + HOST_TBL_RD_RSLT_DATA8_ADDRESS, - &value->val); -} - -sw_error_t -hppe_host_tbl_rd_rslt_data8_set( - a_uint32_t dev_id, - union host_tbl_rd_rslt_data8_u *value) -{ - return SW_NOT_SUPPORTED; -} - -sw_error_t -hppe_host_tbl_rd_rslt_data9_get( - a_uint32_t dev_id, - union host_tbl_rd_rslt_data9_u *value) -{ - return hppe_reg_get( - dev_id, - IPE_L3_BASE_ADDR + HOST_TBL_RD_RSLT_DATA9_ADDRESS, - &value->val); -} - -sw_error_t -hppe_host_tbl_rd_rslt_data9_set( - a_uint32_t dev_id, - union host_tbl_rd_rslt_data9_u *value) -{ - return SW_NOT_SUPPORTED; -} - -sw_error_t -hppe_l3_dbg_cmd_get( - a_uint32_t dev_id, - union l3_dbg_cmd_u *value) -{ - return hppe_reg_get( - dev_id, - IPE_L3_BASE_ADDR + L3_DBG_CMD_ADDRESS, - &value->val); -} - -sw_error_t -hppe_l3_dbg_cmd_set( - a_uint32_t dev_id, - union l3_dbg_cmd_u *value) -{ - return hppe_reg_set( - dev_id, - IPE_L3_BASE_ADDR + L3_DBG_CMD_ADDRESS, - value->val); -} - -sw_error_t -hppe_l3_dbg_wr_data_get( - a_uint32_t dev_id, - union l3_dbg_wr_data_u *value) -{ - return hppe_reg_get( - dev_id, - IPE_L3_BASE_ADDR + L3_DBG_WR_DATA_ADDRESS, - &value->val); -} - -sw_error_t -hppe_l3_dbg_wr_data_set( - a_uint32_t dev_id, - union l3_dbg_wr_data_u *value) -{ - return hppe_reg_set( - dev_id, - IPE_L3_BASE_ADDR + L3_DBG_WR_DATA_ADDRESS, - value->val); -} - -sw_error_t -hppe_l3_dbg_rd_data_get( - a_uint32_t dev_id, - union l3_dbg_rd_data_u *value) -{ - return hppe_reg_get( - dev_id, - IPE_L3_BASE_ADDR + L3_DBG_RD_DATA_ADDRESS, - &value->val); -} - -sw_error_t -hppe_l3_dbg_rd_data_set( - a_uint32_t dev_id, - union l3_dbg_rd_data_u *value) -{ - return SW_NOT_SUPPORTED; -} -#endif -sw_error_t -hppe_l3_vp_port_tbl_get( - a_uint32_t dev_id, - a_uint32_t index, - union l3_vp_port_tbl_u *value) -{ - return hppe_reg_tbl_get( - dev_id, - IPE_L3_BASE_ADDR + L3_VP_PORT_TBL_ADDRESS + \ - index * L3_VP_PORT_TBL_INC, - value->val, - 3); -} - -sw_error_t -hppe_l3_vp_port_tbl_set( - a_uint32_t dev_id, - a_uint32_t index, - union l3_vp_port_tbl_u *value) -{ - return hppe_reg_tbl_set( - dev_id, - IPE_L3_BASE_ADDR + L3_VP_PORT_TBL_ADDRESS + \ - index * L3_VP_PORT_TBL_INC, - value->val, - 3); -} -#if ((!defined IN_IP_MINI) || (defined IN_PPPOE)) -sw_error_t -hppe_in_l3_if_tbl_get( - a_uint32_t dev_id, - a_uint32_t index, - union in_l3_if_tbl_u *value) -{ - return hppe_reg_tbl_get( - dev_id, - IPE_L3_BASE_ADDR + IN_L3_IF_TBL_ADDRESS + \ - index * IN_L3_IF_TBL_INC, - value->val, - 2); -} - -sw_error_t -hppe_in_l3_if_tbl_set( - a_uint32_t dev_id, - a_uint32_t index, - union in_l3_if_tbl_u *value) -{ - return hppe_reg_tbl_set( - dev_id, - IPE_L3_BASE_ADDR + IN_L3_IF_TBL_ADDRESS + \ - index * IN_L3_IF_TBL_INC, - value->val, - 2); -} -#endif -#ifndef IN_IP_MINI -sw_error_t -hppe_host_ipv6_mcast_tbl_get( - a_uint32_t dev_id, - a_uint32_t index, - union host_ipv6_mcast_tbl_u *value) -{ - return hppe_reg_tbl_get( - dev_id, - IPE_L3_BASE_ADDR + HOST_IPV6_MCAST_TBL_ADDRESS + \ - index * HOST_IPV6_MCAST_TBL_INC, - value->val, - 10); -} - -sw_error_t -hppe_host_ipv6_mcast_tbl_set( - a_uint32_t dev_id, - a_uint32_t index, - union host_ipv6_mcast_tbl_u *value) -{ - return hppe_reg_tbl_set( - dev_id, - IPE_L3_BASE_ADDR + HOST_IPV6_MCAST_TBL_ADDRESS + \ - index * HOST_IPV6_MCAST_TBL_INC, - value->val, - 10); -} - -sw_error_t -hppe_host_ipv4_mcast_tbl_get( - a_uint32_t dev_id, - a_uint32_t index, - union host_ipv4_mcast_tbl_u *value) -{ - return hppe_reg_tbl_get( - dev_id, - IPE_L3_BASE_ADDR + HOST_IPV4_MCAST_TBL_ADDRESS + \ - index * HOST_IPV4_MCAST_TBL_INC, - value->val, - 5); -} - -sw_error_t -hppe_host_ipv4_mcast_tbl_set( - a_uint32_t dev_id, - a_uint32_t index, - union host_ipv4_mcast_tbl_u *value) -{ - return hppe_reg_tbl_set( - dev_id, - IPE_L3_BASE_ADDR + HOST_IPV4_MCAST_TBL_ADDRESS + \ - index * HOST_IPV4_MCAST_TBL_INC, - value->val, - 5); -} - -sw_error_t -hppe_host_tbl_get( - a_uint32_t dev_id, - a_uint32_t index, - union host_tbl_u *value) -{ - return hppe_reg_tbl_get( - dev_id, - IPE_L3_BASE_ADDR + HOST_TBL_ADDRESS + \ - index * HOST_TBL_INC, - value->val, - 2); -} - -sw_error_t -hppe_host_tbl_set( - a_uint32_t dev_id, - a_uint32_t index, - union host_tbl_u *value) -{ - return hppe_reg_tbl_set( - dev_id, - IPE_L3_BASE_ADDR + HOST_TBL_ADDRESS + \ - index * HOST_TBL_INC, - value->val, - 2); -} - -sw_error_t -hppe_host_ipv6_tbl_get( - a_uint32_t dev_id, - a_uint32_t index, - union host_ipv6_tbl_u *value) -{ - return hppe_reg_tbl_get( - dev_id, - IPE_L3_BASE_ADDR + HOST_IPV6_TBL_ADDRESS + \ - index * HOST_IPV6_TBL_INC, - value->val, - 5); -} - -sw_error_t -hppe_host_ipv6_tbl_set( - a_uint32_t dev_id, - a_uint32_t index, - union host_ipv6_tbl_u *value) -{ - return hppe_reg_tbl_set( - dev_id, - IPE_L3_BASE_ADDR + HOST_IPV6_TBL_ADDRESS + \ - index * HOST_IPV6_TBL_INC, - value->val, - 5); -} - -sw_error_t -hppe_in_nexthop_tbl_get( - a_uint32_t dev_id, - a_uint32_t index, - union in_nexthop_tbl_u *value) -{ - return hppe_reg_tbl_get( - dev_id, - IPE_L3_BASE_ADDR + IN_NEXTHOP_TBL_ADDRESS + \ - index * IN_NEXTHOP_TBL_INC, - value->val, - 4); -} - -sw_error_t -hppe_in_nexthop_tbl_set( - a_uint32_t dev_id, - a_uint32_t index, - union in_nexthop_tbl_u *value) -{ - return hppe_reg_tbl_set( - dev_id, - IPE_L3_BASE_ADDR + IN_NEXTHOP_TBL_ADDRESS + \ - index * IN_NEXTHOP_TBL_INC, - value->val, - 4); -} -#endif -#if ((!defined IN_IP_MINI) || (defined IN_PPPOE)) -sw_error_t -hppe_eg_l3_if_tbl_get( - a_uint32_t dev_id, - a_uint32_t index, - union eg_l3_if_tbl_u *value) -{ - return hppe_reg_tbl_get( - dev_id, - NSS_PTX_CSR_BASE_ADDR + EG_L3_IF_TBL_ADDRESS + \ - index * EG_L3_IF_TBL_INC, - value->val, - 3); -} - -sw_error_t -hppe_eg_l3_if_tbl_set( - a_uint32_t dev_id, - a_uint32_t index, - union eg_l3_if_tbl_u *value) -{ - return hppe_reg_tbl_set( - dev_id, - NSS_PTX_CSR_BASE_ADDR + EG_L3_IF_TBL_ADDRESS + \ - index * EG_L3_IF_TBL_INC, - value->val, - 3); -} -#endif -#ifndef IN_IP_MINI -sw_error_t -hppe_my_mac_tbl_mac_da_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint64_t *value) -{ - union my_mac_tbl_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_my_mac_tbl_get(dev_id, index, ®_val); - *value = (a_uint64_t)reg_val.bf.mac_da_1 << 32 | \ - reg_val.bf.mac_da_0; - return ret; -} - -sw_error_t -hppe_my_mac_tbl_mac_da_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint64_t value) -{ - union my_mac_tbl_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_my_mac_tbl_get(dev_id, index, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.mac_da_1 = value >> 32; - reg_val.bf.mac_da_0 = value & (((a_uint64_t)1<<32)-1); - ret = hppe_my_mac_tbl_set(dev_id, index, ®_val); - return ret; -} - -sw_error_t -hppe_my_mac_tbl_valid_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union my_mac_tbl_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_my_mac_tbl_get(dev_id, index, ®_val); - *value = reg_val.bf.valid; - return ret; -} - -sw_error_t -hppe_my_mac_tbl_valid_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - union my_mac_tbl_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_my_mac_tbl_get(dev_id, index, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.valid = value; - ret = hppe_my_mac_tbl_set(dev_id, index, ®_val); - return ret; -} - -sw_error_t -hppe_l3_vsi_l3_if_index_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union l3_vsi_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_l3_vsi_get(dev_id, index, ®_val); - *value = reg_val.bf.l3_if_index; - return ret; -} - -sw_error_t -hppe_l3_vsi_l3_if_index_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - union l3_vsi_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_l3_vsi_get(dev_id, index, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.l3_if_index = value; - ret = hppe_l3_vsi_set(dev_id, index, ®_val); - return ret; -} - -sw_error_t -hppe_l3_vsi_l2_ipv6_mc_mode_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union l3_vsi_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_l3_vsi_get(dev_id, index, ®_val); - *value = reg_val.bf.l2_ipv6_mc_mode; - return ret; -} - -sw_error_t -hppe_l3_vsi_l2_ipv6_mc_mode_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - union l3_vsi_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_l3_vsi_get(dev_id, index, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.l2_ipv6_mc_mode = value; - ret = hppe_l3_vsi_set(dev_id, index, ®_val); - return ret; -} - -sw_error_t -hppe_l3_vsi_l3_if_valid_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union l3_vsi_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_l3_vsi_get(dev_id, index, ®_val); - *value = reg_val.bf.l3_if_valid; - return ret; -} - -sw_error_t -hppe_l3_vsi_l3_if_valid_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - union l3_vsi_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_l3_vsi_get(dev_id, index, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.l3_if_valid = value; - ret = hppe_l3_vsi_set(dev_id, index, ®_val); - return ret; -} - -sw_error_t -hppe_l3_vsi_l2_ipv6_mc_en_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union l3_vsi_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_l3_vsi_get(dev_id, index, ®_val); - *value = reg_val.bf.l2_ipv6_mc_en; - return ret; -} - -sw_error_t -hppe_l3_vsi_l2_ipv6_mc_en_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - union l3_vsi_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_l3_vsi_get(dev_id, index, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.l2_ipv6_mc_en = value; - ret = hppe_l3_vsi_set(dev_id, index, ®_val); - return ret; -} - -sw_error_t -hppe_l3_vsi_l2_ipv4_mc_en_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union l3_vsi_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_l3_vsi_get(dev_id, index, ®_val); - *value = reg_val.bf.l2_ipv4_mc_en; - return ret; -} - -sw_error_t -hppe_l3_vsi_l2_ipv4_mc_en_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - union l3_vsi_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_l3_vsi_get(dev_id, index, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.l2_ipv4_mc_en = value; - ret = hppe_l3_vsi_set(dev_id, index, ®_val); - return ret; -} - -sw_error_t -hppe_l3_vsi_l2_ipv4_mc_mode_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union l3_vsi_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_l3_vsi_get(dev_id, index, ®_val); - *value = reg_val.bf.l2_ipv4_mc_mode; - return ret; -} - -sw_error_t -hppe_l3_vsi_l2_ipv4_mc_mode_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - union l3_vsi_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_l3_vsi_get(dev_id, index, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.l2_ipv4_mc_mode = value; - ret = hppe_l3_vsi_set(dev_id, index, ®_val); - return ret; -} - -sw_error_t -hppe_l3_vsi_ext_ip_arp_sg_en_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union l3_vsi_ext_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_l3_vsi_ext_get(dev_id, index, ®_val); - *value = reg_val.bf.ip_arp_sg_en; - return ret; -} - -sw_error_t -hppe_l3_vsi_ext_ip_arp_sg_en_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - union l3_vsi_ext_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_l3_vsi_ext_get(dev_id, index, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.ip_arp_sg_en = value; - ret = hppe_l3_vsi_ext_set(dev_id, index, ®_val); - return ret; -} - -sw_error_t -hppe_l3_vsi_ext_ipv6_sg_svlan_en_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union l3_vsi_ext_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_l3_vsi_ext_get(dev_id, index, ®_val); - *value = reg_val.bf.ipv6_sg_svlan_en; - return ret; -} - -sw_error_t -hppe_l3_vsi_ext_ipv6_sg_svlan_en_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - union l3_vsi_ext_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_l3_vsi_ext_get(dev_id, index, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.ipv6_sg_svlan_en = value; - ret = hppe_l3_vsi_ext_set(dev_id, index, ®_val); - return ret; -} - -sw_error_t -hppe_l3_vsi_ext_ip_nd_sg_cvlan_en_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union l3_vsi_ext_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_l3_vsi_ext_get(dev_id, index, ®_val); - *value = reg_val.bf.ip_nd_sg_cvlan_en; - return ret; -} - -sw_error_t -hppe_l3_vsi_ext_ip_nd_sg_cvlan_en_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - union l3_vsi_ext_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_l3_vsi_ext_get(dev_id, index, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.ip_nd_sg_cvlan_en = value; - ret = hppe_l3_vsi_ext_set(dev_id, index, ®_val); - return ret; -} - -sw_error_t -hppe_l3_vsi_ext_ip_nd_sg_vio_cmd_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union l3_vsi_ext_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_l3_vsi_ext_get(dev_id, index, ®_val); - *value = reg_val.bf.ip_nd_sg_vio_cmd; - return ret; -} - -sw_error_t -hppe_l3_vsi_ext_ip_nd_sg_vio_cmd_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - union l3_vsi_ext_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_l3_vsi_ext_get(dev_id, index, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.ip_nd_sg_vio_cmd = value; - ret = hppe_l3_vsi_ext_set(dev_id, index, ®_val); - return ret; -} - -sw_error_t -hppe_l3_vsi_ext_ipv4_sg_port_en_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union l3_vsi_ext_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_l3_vsi_ext_get(dev_id, index, ®_val); - *value = reg_val.bf.ipv4_sg_port_en; - return ret; -} - -sw_error_t -hppe_l3_vsi_ext_ipv4_sg_port_en_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - union l3_vsi_ext_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_l3_vsi_ext_get(dev_id, index, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.ipv4_sg_port_en = value; - ret = hppe_l3_vsi_ext_set(dev_id, index, ®_val); - return ret; -} - -sw_error_t -hppe_l3_vsi_ext_ip_nd_sg_en_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union l3_vsi_ext_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_l3_vsi_ext_get(dev_id, index, ®_val); - *value = reg_val.bf.ip_nd_sg_en; - return ret; -} - -sw_error_t -hppe_l3_vsi_ext_ip_nd_sg_en_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - union l3_vsi_ext_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_l3_vsi_ext_get(dev_id, index, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.ip_nd_sg_en = value; - ret = hppe_l3_vsi_ext_set(dev_id, index, ®_val); - return ret; -} - -sw_error_t -hppe_l3_vsi_ext_ipv4_sg_svlan_en_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union l3_vsi_ext_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_l3_vsi_ext_get(dev_id, index, ®_val); - *value = reg_val.bf.ipv4_sg_svlan_en; - return ret; -} - -sw_error_t -hppe_l3_vsi_ext_ipv4_sg_svlan_en_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - union l3_vsi_ext_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_l3_vsi_ext_get(dev_id, index, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.ipv4_sg_svlan_en = value; - ret = hppe_l3_vsi_ext_set(dev_id, index, ®_val); - return ret; -} - -sw_error_t -hppe_l3_vsi_ext_ipv4_sg_cvlan_en_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union l3_vsi_ext_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_l3_vsi_ext_get(dev_id, index, ®_val); - *value = reg_val.bf.ipv4_sg_cvlan_en; - return ret; -} - -sw_error_t -hppe_l3_vsi_ext_ipv4_sg_cvlan_en_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - union l3_vsi_ext_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_l3_vsi_ext_get(dev_id, index, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.ipv4_sg_cvlan_en = value; - ret = hppe_l3_vsi_ext_set(dev_id, index, ®_val); - return ret; -} - -sw_error_t -hppe_l3_vsi_ext_ip_arp_sg_svlan_en_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union l3_vsi_ext_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_l3_vsi_ext_get(dev_id, index, ®_val); - *value = reg_val.bf.ip_arp_sg_svlan_en; - return ret; -} - -sw_error_t -hppe_l3_vsi_ext_ip_arp_sg_svlan_en_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - union l3_vsi_ext_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_l3_vsi_ext_get(dev_id, index, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.ip_arp_sg_svlan_en = value; - ret = hppe_l3_vsi_ext_set(dev_id, index, ®_val); - return ret; -} - -sw_error_t -hppe_l3_vsi_ext_ip_nd_sg_svlan_en_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union l3_vsi_ext_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_l3_vsi_ext_get(dev_id, index, ®_val); - *value = reg_val.bf.ip_nd_sg_svlan_en; - return ret; -} - -sw_error_t -hppe_l3_vsi_ext_ip_nd_sg_svlan_en_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - union l3_vsi_ext_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_l3_vsi_ext_get(dev_id, index, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.ip_nd_sg_svlan_en = value; - ret = hppe_l3_vsi_ext_set(dev_id, index, ®_val); - return ret; -} - -sw_error_t -hppe_l3_vsi_ext_ipv6_sg_vio_cmd_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union l3_vsi_ext_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_l3_vsi_ext_get(dev_id, index, ®_val); - *value = reg_val.bf.ipv6_sg_vio_cmd; - return ret; -} - -sw_error_t -hppe_l3_vsi_ext_ipv6_sg_vio_cmd_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - union l3_vsi_ext_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_l3_vsi_ext_get(dev_id, index, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.ipv6_sg_vio_cmd = value; - ret = hppe_l3_vsi_ext_set(dev_id, index, ®_val); - return ret; -} - -sw_error_t -hppe_l3_vsi_ext_ip_nd_sg_port_en_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union l3_vsi_ext_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_l3_vsi_ext_get(dev_id, index, ®_val); - *value = reg_val.bf.ip_nd_sg_port_en; - return ret; -} - -sw_error_t -hppe_l3_vsi_ext_ip_nd_sg_port_en_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - union l3_vsi_ext_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_l3_vsi_ext_get(dev_id, index, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.ip_nd_sg_port_en = value; - ret = hppe_l3_vsi_ext_set(dev_id, index, ®_val); - return ret; -} - -sw_error_t -hppe_l3_vsi_ext_ip_arp_src_unk_cmd_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union l3_vsi_ext_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_l3_vsi_ext_get(dev_id, index, ®_val); - *value = reg_val.bf.ip_arp_src_unk_cmd; - return ret; -} - -sw_error_t -hppe_l3_vsi_ext_ip_arp_src_unk_cmd_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - union l3_vsi_ext_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_l3_vsi_ext_get(dev_id, index, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.ip_arp_src_unk_cmd = value; - ret = hppe_l3_vsi_ext_set(dev_id, index, ®_val); - return ret; -} - -sw_error_t -hppe_l3_vsi_ext_ipv6_sg_port_en_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union l3_vsi_ext_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_l3_vsi_ext_get(dev_id, index, ®_val); - *value = reg_val.bf.ipv6_sg_port_en; - return ret; -} - -sw_error_t -hppe_l3_vsi_ext_ipv6_sg_port_en_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - union l3_vsi_ext_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_l3_vsi_ext_get(dev_id, index, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.ipv6_sg_port_en = value; - ret = hppe_l3_vsi_ext_set(dev_id, index, ®_val); - return ret; -} - -sw_error_t -hppe_l3_vsi_ext_ipv4_src_unk_cmd_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union l3_vsi_ext_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_l3_vsi_ext_get(dev_id, index, ®_val); - *value = reg_val.bf.ipv4_src_unk_cmd; - return ret; -} - -sw_error_t -hppe_l3_vsi_ext_ipv4_src_unk_cmd_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - union l3_vsi_ext_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_l3_vsi_ext_get(dev_id, index, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.ipv4_src_unk_cmd = value; - ret = hppe_l3_vsi_ext_set(dev_id, index, ®_val); - return ret; -} - -sw_error_t -hppe_l3_vsi_ext_ip_arp_sg_vio_cmd_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union l3_vsi_ext_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_l3_vsi_ext_get(dev_id, index, ®_val); - *value = reg_val.bf.ip_arp_sg_vio_cmd; - return ret; -} - -sw_error_t -hppe_l3_vsi_ext_ip_arp_sg_vio_cmd_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - union l3_vsi_ext_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_l3_vsi_ext_get(dev_id, index, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.ip_arp_sg_vio_cmd = value; - ret = hppe_l3_vsi_ext_set(dev_id, index, ®_val); - return ret; -} - -sw_error_t -hppe_l3_vsi_ext_ip_arp_sg_port_en_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union l3_vsi_ext_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_l3_vsi_ext_get(dev_id, index, ®_val); - *value = reg_val.bf.ip_arp_sg_port_en; - return ret; -} - -sw_error_t -hppe_l3_vsi_ext_ip_arp_sg_port_en_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - union l3_vsi_ext_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_l3_vsi_ext_get(dev_id, index, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.ip_arp_sg_port_en = value; - ret = hppe_l3_vsi_ext_set(dev_id, index, ®_val); - return ret; -} - -sw_error_t -hppe_l3_vsi_ext_ipv4_sg_vio_cmd_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union l3_vsi_ext_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_l3_vsi_ext_get(dev_id, index, ®_val); - *value = reg_val.bf.ipv4_sg_vio_cmd; - return ret; -} - -sw_error_t -hppe_l3_vsi_ext_ipv4_sg_vio_cmd_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - union l3_vsi_ext_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_l3_vsi_ext_get(dev_id, index, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.ipv4_sg_vio_cmd = value; - ret = hppe_l3_vsi_ext_set(dev_id, index, ®_val); - return ret; -} - -sw_error_t -hppe_l3_vsi_ext_ipv6_src_unk_cmd_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union l3_vsi_ext_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_l3_vsi_ext_get(dev_id, index, ®_val); - *value = reg_val.bf.ipv6_src_unk_cmd; - return ret; -} - -sw_error_t -hppe_l3_vsi_ext_ipv6_src_unk_cmd_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - union l3_vsi_ext_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_l3_vsi_ext_get(dev_id, index, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.ipv6_src_unk_cmd = value; - ret = hppe_l3_vsi_ext_set(dev_id, index, ®_val); - return ret; -} - -sw_error_t -hppe_l3_vsi_ext_ipv6_sg_en_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union l3_vsi_ext_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_l3_vsi_ext_get(dev_id, index, ®_val); - *value = reg_val.bf.ipv6_sg_en; - return ret; -} - -sw_error_t -hppe_l3_vsi_ext_ipv6_sg_en_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - union l3_vsi_ext_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_l3_vsi_ext_get(dev_id, index, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.ipv6_sg_en = value; - ret = hppe_l3_vsi_ext_set(dev_id, index, ®_val); - return ret; -} - -sw_error_t -hppe_l3_vsi_ext_ip_arp_sg_cvlan_en_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union l3_vsi_ext_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_l3_vsi_ext_get(dev_id, index, ®_val); - *value = reg_val.bf.ip_arp_sg_cvlan_en; - return ret; -} - -sw_error_t -hppe_l3_vsi_ext_ip_arp_sg_cvlan_en_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - union l3_vsi_ext_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_l3_vsi_ext_get(dev_id, index, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.ip_arp_sg_cvlan_en = value; - ret = hppe_l3_vsi_ext_set(dev_id, index, ®_val); - return ret; -} - -sw_error_t -hppe_l3_vsi_ext_ip_nd_src_unk_cmd_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union l3_vsi_ext_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_l3_vsi_ext_get(dev_id, index, ®_val); - *value = reg_val.bf.ip_nd_src_unk_cmd; - return ret; -} - -sw_error_t -hppe_l3_vsi_ext_ip_nd_src_unk_cmd_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - union l3_vsi_ext_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_l3_vsi_ext_get(dev_id, index, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.ip_nd_src_unk_cmd = value; - ret = hppe_l3_vsi_ext_set(dev_id, index, ®_val); - return ret; -} - -sw_error_t -hppe_l3_vsi_ext_ipv4_sg_en_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union l3_vsi_ext_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_l3_vsi_ext_get(dev_id, index, ®_val); - *value = reg_val.bf.ipv4_sg_en; - return ret; -} - -sw_error_t -hppe_l3_vsi_ext_ipv4_sg_en_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - union l3_vsi_ext_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_l3_vsi_ext_get(dev_id, index, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.ipv4_sg_en = value; - ret = hppe_l3_vsi_ext_set(dev_id, index, ®_val); - return ret; -} - -sw_error_t -hppe_l3_vsi_ext_ipv6_sg_cvlan_en_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union l3_vsi_ext_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_l3_vsi_ext_get(dev_id, index, ®_val); - *value = reg_val.bf.ipv6_sg_cvlan_en; - return ret; -} - -sw_error_t -hppe_l3_vsi_ext_ipv6_sg_cvlan_en_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - union l3_vsi_ext_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_l3_vsi_ext_get(dev_id, index, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.ipv6_sg_cvlan_en = value; - ret = hppe_l3_vsi_ext_set(dev_id, index, ®_val); - return ret; -} - -sw_error_t -hppe_network_route_ip_ip_addr_mask_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union network_route_ip_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_network_route_ip_get(dev_id, index, ®_val); - *value = reg_val.bf.ip_addr_mask; - return ret; -} - -sw_error_t -hppe_network_route_ip_ip_addr_mask_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - union network_route_ip_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_network_route_ip_get(dev_id, index, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.ip_addr_mask = value; - ret = hppe_network_route_ip_set(dev_id, index, ®_val); - return ret; -} - -sw_error_t -hppe_network_route_ip_ip_addr_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union network_route_ip_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_network_route_ip_get(dev_id, index, ®_val); - *value = reg_val.bf.ip_addr; - return ret; -} - -sw_error_t -hppe_network_route_ip_ip_addr_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - union network_route_ip_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_network_route_ip_get(dev_id, index, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.ip_addr = value; - ret = hppe_network_route_ip_set(dev_id, index, ®_val); - return ret; -} - -sw_error_t -hppe_network_route_ip_ext_entry_type_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union network_route_ip_ext_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_network_route_ip_ext_get(dev_id, index, ®_val); - *value = reg_val.bf.entry_type; - return ret; -} - -sw_error_t -hppe_network_route_ip_ext_entry_type_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - union network_route_ip_ext_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_network_route_ip_ext_get(dev_id, index, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.entry_type = value; - ret = hppe_network_route_ip_ext_set(dev_id, index, ®_val); - return ret; -} - -sw_error_t -hppe_network_route_ip_ext_valid_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union network_route_ip_ext_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_network_route_ip_ext_get(dev_id, index, ®_val); - *value = reg_val.bf.valid; - return ret; -} - -sw_error_t -hppe_network_route_ip_ext_valid_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - union network_route_ip_ext_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_network_route_ip_ext_get(dev_id, index, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.valid = value; - ret = hppe_network_route_ip_ext_set(dev_id, index, ®_val); - return ret; -} - -sw_error_t -hppe_network_route_action_lan_wan_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union network_route_action_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_network_route_action_get(dev_id, index, ®_val); - *value = reg_val.bf.lan_wan; - return ret; -} - -sw_error_t -hppe_network_route_action_lan_wan_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - union network_route_action_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_network_route_action_get(dev_id, index, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.lan_wan = value; - ret = hppe_network_route_action_set(dev_id, index, ®_val); - return ret; -} - -sw_error_t -hppe_network_route_action_fwd_cmd_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union network_route_action_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_network_route_action_get(dev_id, index, ®_val); - *value = reg_val.bf.fwd_cmd; - return ret; -} - -sw_error_t -hppe_network_route_action_fwd_cmd_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - union network_route_action_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_network_route_action_get(dev_id, index, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.fwd_cmd = value; - ret = hppe_network_route_action_set(dev_id, index, ®_val); - return ret; -} - -sw_error_t -hppe_network_route_action_dst_info_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union network_route_action_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_network_route_action_get(dev_id, index, ®_val); - *value = reg_val.bf.dst_info; - return ret; -} - -sw_error_t -hppe_network_route_action_dst_info_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - union network_route_action_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_network_route_action_get(dev_id, index, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.dst_info = value; - ret = hppe_network_route_action_set(dev_id, index, ®_val); - return ret; -} - -sw_error_t -hppe_l3_route_ctrl_flow_src_if_check_de_acce_get( - a_uint32_t dev_id, - a_uint32_t *value) -{ - union l3_route_ctrl_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_l3_route_ctrl_get(dev_id, ®_val); - *value = reg_val.bf.flow_src_if_check_de_acce; - return ret; -} - -sw_error_t -hppe_l3_route_ctrl_flow_src_if_check_de_acce_set( - a_uint32_t dev_id, - a_uint32_t value) -{ - union l3_route_ctrl_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_l3_route_ctrl_get(dev_id, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.flow_src_if_check_de_acce = value; - ret = hppe_l3_route_ctrl_set(dev_id, ®_val); - return ret; -} - -sw_error_t -hppe_l3_route_ctrl_pppoe_multicast_cmd_get( - a_uint32_t dev_id, - a_uint32_t *value) -{ - union l3_route_ctrl_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_l3_route_ctrl_get(dev_id, ®_val); - *value = reg_val.bf.pppoe_multicast_cmd; - return ret; -} - -sw_error_t -hppe_l3_route_ctrl_pppoe_multicast_cmd_set( - a_uint32_t dev_id, - a_uint32_t value) -{ - union l3_route_ctrl_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_l3_route_ctrl_get(dev_id, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.pppoe_multicast_cmd = value; - ret = hppe_l3_route_ctrl_set(dev_id, ®_val); - return ret; -} - -sw_error_t -hppe_l3_route_ctrl_ip_mtu_fail_get( - a_uint32_t dev_id, - a_uint32_t *value) -{ - union l3_route_ctrl_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_l3_route_ctrl_get(dev_id, ®_val); - *value = reg_val.bf.ip_mtu_fail; - return ret; -} - -sw_error_t -hppe_l3_route_ctrl_ip_mtu_fail_set( - a_uint32_t dev_id, - a_uint32_t value) -{ - union l3_route_ctrl_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_l3_route_ctrl_get(dev_id, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.ip_mtu_fail = value; - ret = hppe_l3_route_ctrl_set(dev_id, ®_val); - return ret; -} - -sw_error_t -hppe_l3_route_ctrl_flow_src_if_check_cmd_get( - a_uint32_t dev_id, - a_uint32_t *value) -{ - union l3_route_ctrl_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_l3_route_ctrl_get(dev_id, ®_val); - *value = reg_val.bf.flow_src_if_check_cmd; - return ret; -} - -sw_error_t -hppe_l3_route_ctrl_flow_src_if_check_cmd_set( - a_uint32_t dev_id, - a_uint32_t value) -{ - union l3_route_ctrl_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_l3_route_ctrl_get(dev_id, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.flow_src_if_check_cmd = value; - ret = hppe_l3_route_ctrl_set(dev_id, ®_val); - return ret; -} - -sw_error_t -hppe_l3_route_ctrl_icmp_rdt_de_acce_get( - a_uint32_t dev_id, - a_uint32_t *value) -{ - union l3_route_ctrl_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_l3_route_ctrl_get(dev_id, ®_val); - *value = reg_val.bf.icmp_rdt_de_acce; - return ret; -} - -sw_error_t -hppe_l3_route_ctrl_icmp_rdt_de_acce_set( - a_uint32_t dev_id, - a_uint32_t value) -{ - union l3_route_ctrl_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_l3_route_ctrl_get(dev_id, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.icmp_rdt_de_acce = value; - ret = hppe_l3_route_ctrl_set(dev_id, ®_val); - return ret; -} - -sw_error_t -hppe_l3_route_ctrl_flow_de_acce_cmd_get( - a_uint32_t dev_id, - a_uint32_t *value) -{ - union l3_route_ctrl_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_l3_route_ctrl_get(dev_id, ®_val); - *value = reg_val.bf.flow_de_acce_cmd; - return ret; -} - -sw_error_t -hppe_l3_route_ctrl_flow_de_acce_cmd_set( - a_uint32_t dev_id, - a_uint32_t value) -{ - union l3_route_ctrl_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_l3_route_ctrl_get(dev_id, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.flow_de_acce_cmd = value; - ret = hppe_l3_route_ctrl_set(dev_id, ®_val); - return ret; -} - -sw_error_t -hppe_l3_route_ctrl_ip_mtu_fail_de_acce_get( - a_uint32_t dev_id, - a_uint32_t *value) -{ - union l3_route_ctrl_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_l3_route_ctrl_get(dev_id, ®_val); - *value = reg_val.bf.ip_mtu_fail_de_acce; - return ret; -} - -sw_error_t -hppe_l3_route_ctrl_ip_mtu_fail_de_acce_set( - a_uint32_t dev_id, - a_uint32_t value) -{ - union l3_route_ctrl_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_l3_route_ctrl_get(dev_id, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.ip_mtu_fail_de_acce = value; - ret = hppe_l3_route_ctrl_set(dev_id, ®_val); - return ret; -} - -sw_error_t -hppe_l3_route_ctrl_flow_sync_mismatch_cmd_get( - a_uint32_t dev_id, - a_uint32_t *value) -{ - union l3_route_ctrl_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_l3_route_ctrl_get(dev_id, ®_val); - *value = reg_val.bf.flow_sync_mismatch_cmd; - return ret; -} - -sw_error_t -hppe_l3_route_ctrl_flow_sync_mismatch_cmd_set( - a_uint32_t dev_id, - a_uint32_t value) -{ - union l3_route_ctrl_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_l3_route_ctrl_get(dev_id, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.flow_sync_mismatch_cmd = value; - ret = hppe_l3_route_ctrl_set(dev_id, ®_val); - return ret; -} - -sw_error_t -hppe_l3_route_ctrl_flow_service_code_loop_de_acce_get( - a_uint32_t dev_id, - a_uint32_t *value) -{ - union l3_route_ctrl_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_l3_route_ctrl_get(dev_id, ®_val); - *value = reg_val.bf.flow_service_code_loop_de_acce; - return ret; -} - -sw_error_t -hppe_l3_route_ctrl_flow_service_code_loop_de_acce_set( - a_uint32_t dev_id, - a_uint32_t value) -{ - union l3_route_ctrl_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_l3_route_ctrl_get(dev_id, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.flow_service_code_loop_de_acce = value; - ret = hppe_l3_route_ctrl_set(dev_id, ®_val); - return ret; -} - -sw_error_t -hppe_l3_route_ctrl_flow_sync_mismatch_de_acce_get( - a_uint32_t dev_id, - a_uint32_t *value) -{ - union l3_route_ctrl_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_l3_route_ctrl_get(dev_id, ®_val); - *value = reg_val.bf.flow_sync_mismatch_de_acce; - return ret; -} - -sw_error_t -hppe_l3_route_ctrl_flow_sync_mismatch_de_acce_set( - a_uint32_t dev_id, - a_uint32_t value) -{ - union l3_route_ctrl_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_l3_route_ctrl_get(dev_id, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.flow_sync_mismatch_de_acce = value; - ret = hppe_l3_route_ctrl_set(dev_id, ®_val); - return ret; -} - -sw_error_t -hppe_l3_route_ctrl_ip_mtu_df_fail_get( - a_uint32_t dev_id, - a_uint32_t *value) -{ - union l3_route_ctrl_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_l3_route_ctrl_get(dev_id, ®_val); - *value = reg_val.bf.ip_mtu_df_fail; - return ret; -} - -sw_error_t -hppe_l3_route_ctrl_ip_mtu_df_fail_set( - a_uint32_t dev_id, - a_uint32_t value) -{ - union l3_route_ctrl_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_l3_route_ctrl_get(dev_id, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.ip_mtu_df_fail = value; - ret = hppe_l3_route_ctrl_set(dev_id, ®_val); - return ret; -} - -sw_error_t -hppe_l3_route_ctrl_flow_service_code_loop_get( - a_uint32_t dev_id, - a_uint32_t *value) -{ - union l3_route_ctrl_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_l3_route_ctrl_get(dev_id, ®_val); - *value = reg_val.bf.flow_service_code_loop; - return ret; -} - -sw_error_t -hppe_l3_route_ctrl_flow_service_code_loop_set( - a_uint32_t dev_id, - a_uint32_t value) -{ - union l3_route_ctrl_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_l3_route_ctrl_get(dev_id, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.flow_service_code_loop = value; - ret = hppe_l3_route_ctrl_set(dev_id, ®_val); - return ret; -} - -sw_error_t -hppe_l3_route_ctrl_ip_mru_check_fail_de_acce_get( - a_uint32_t dev_id, - a_uint32_t *value) -{ - union l3_route_ctrl_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_l3_route_ctrl_get(dev_id, ®_val); - *value = reg_val.bf.ip_mru_check_fail_de_acce; - return ret; -} - -sw_error_t -hppe_l3_route_ctrl_ip_mru_check_fail_de_acce_set( - a_uint32_t dev_id, - a_uint32_t value) -{ - union l3_route_ctrl_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_l3_route_ctrl_get(dev_id, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.ip_mru_check_fail_de_acce = value; - ret = hppe_l3_route_ctrl_set(dev_id, ®_val); - return ret; -} - -sw_error_t -hppe_l3_route_ctrl_ip_prefix_bc_cmd_get( - a_uint32_t dev_id, - a_uint32_t *value) -{ - union l3_route_ctrl_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_l3_route_ctrl_get(dev_id, ®_val); - *value = reg_val.bf.ip_prefix_bc_cmd; - return ret; -} - -sw_error_t -hppe_l3_route_ctrl_ip_prefix_bc_cmd_set( - a_uint32_t dev_id, - a_uint32_t value) -{ - union l3_route_ctrl_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_l3_route_ctrl_get(dev_id, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.ip_prefix_bc_cmd = value; - ret = hppe_l3_route_ctrl_set(dev_id, ®_val); - return ret; -} - -sw_error_t -hppe_l3_route_ctrl_ip_mtu_df_fail_de_acce_get( - a_uint32_t dev_id, - a_uint32_t *value) -{ - union l3_route_ctrl_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_l3_route_ctrl_get(dev_id, ®_val); - *value = reg_val.bf.ip_mtu_df_fail_de_acce; - return ret; -} - -sw_error_t -hppe_l3_route_ctrl_ip_mtu_df_fail_de_acce_set( - a_uint32_t dev_id, - a_uint32_t value) -{ - union l3_route_ctrl_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_l3_route_ctrl_get(dev_id, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.ip_mtu_df_fail_de_acce = value; - ret = hppe_l3_route_ctrl_set(dev_id, ®_val); - return ret; -} - -sw_error_t -hppe_l3_route_ctrl_pppoe_multicast_de_acce_get( - a_uint32_t dev_id, - a_uint32_t *value) -{ - union l3_route_ctrl_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_l3_route_ctrl_get(dev_id, ®_val); - *value = reg_val.bf.pppoe_multicast_de_acce; - return ret; -} - -sw_error_t -hppe_l3_route_ctrl_pppoe_multicast_de_acce_set( - a_uint32_t dev_id, - a_uint32_t value) -{ - union l3_route_ctrl_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_l3_route_ctrl_get(dev_id, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.pppoe_multicast_de_acce = value; - ret = hppe_l3_route_ctrl_set(dev_id, ®_val); - return ret; -} - -sw_error_t -hppe_l3_route_ctrl_ip_mru_check_fail_get( - a_uint32_t dev_id, - a_uint32_t *value) -{ - union l3_route_ctrl_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_l3_route_ctrl_get(dev_id, ®_val); - *value = reg_val.bf.ip_mru_check_fail; - return ret; -} - -sw_error_t -hppe_l3_route_ctrl_ip_mru_check_fail_set( - a_uint32_t dev_id, - a_uint32_t value) -{ - union l3_route_ctrl_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_l3_route_ctrl_get(dev_id, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.ip_mru_check_fail = value; - ret = hppe_l3_route_ctrl_set(dev_id, ®_val); - return ret; -} - -sw_error_t -hppe_l3_route_ctrl_icmp_rdt_cmd_get( - a_uint32_t dev_id, - a_uint32_t *value) -{ - union l3_route_ctrl_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_l3_route_ctrl_get(dev_id, ®_val); - *value = reg_val.bf.icmp_rdt_cmd; - return ret; -} - -sw_error_t -hppe_l3_route_ctrl_icmp_rdt_cmd_set( - a_uint32_t dev_id, - a_uint32_t value) -{ - union l3_route_ctrl_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_l3_route_ctrl_get(dev_id, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.icmp_rdt_cmd = value; - ret = hppe_l3_route_ctrl_set(dev_id, ®_val); - return ret; -} - -sw_error_t -hppe_l3_route_ctrl_ip_prefix_bc_de_acce_get( - a_uint32_t dev_id, - a_uint32_t *value) -{ - union l3_route_ctrl_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_l3_route_ctrl_get(dev_id, ®_val); - *value = reg_val.bf.ip_prefix_bc_de_acce; - return ret; -} - -sw_error_t -hppe_l3_route_ctrl_ip_prefix_bc_de_acce_set( - a_uint32_t dev_id, - a_uint32_t value) -{ - union l3_route_ctrl_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_l3_route_ctrl_get(dev_id, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.ip_prefix_bc_de_acce = value; - ret = hppe_l3_route_ctrl_set(dev_id, ®_val); - return ret; -} - -sw_error_t -hppe_l3_route_ctrl_ext_flow_service_code_loop_en_get( - a_uint32_t dev_id, - a_uint32_t *value) -{ - union l3_route_ctrl_ext_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_l3_route_ctrl_ext_get(dev_id, ®_val); - *value = reg_val.bf.flow_service_code_loop_en; - return ret; -} - -sw_error_t -hppe_l3_route_ctrl_ext_flow_service_code_loop_en_set( - a_uint32_t dev_id, - a_uint32_t value) -{ - union l3_route_ctrl_ext_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_l3_route_ctrl_ext_get(dev_id, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.flow_service_code_loop_en = value; - ret = hppe_l3_route_ctrl_ext_set(dev_id, ®_val); - return ret; -} - -sw_error_t -hppe_l3_route_ctrl_ext_host_hash_mode_0_get( - a_uint32_t dev_id, - a_uint32_t *value) -{ - union l3_route_ctrl_ext_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_l3_route_ctrl_ext_get(dev_id, ®_val); - *value = reg_val.bf.host_hash_mode_0; - return ret; -} - -sw_error_t -hppe_l3_route_ctrl_ext_host_hash_mode_0_set( - a_uint32_t dev_id, - a_uint32_t value) -{ - union l3_route_ctrl_ext_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_l3_route_ctrl_ext_get(dev_id, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.host_hash_mode_0 = value; - ret = hppe_l3_route_ctrl_ext_set(dev_id, ®_val); - return ret; -} - -sw_error_t -hppe_l3_route_ctrl_ext_host_hash_mode_1_get( - a_uint32_t dev_id, - a_uint32_t *value) -{ - union l3_route_ctrl_ext_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_l3_route_ctrl_ext_get(dev_id, ®_val); - *value = reg_val.bf.host_hash_mode_1; - return ret; -} - -sw_error_t -hppe_l3_route_ctrl_ext_host_hash_mode_1_set( - a_uint32_t dev_id, - a_uint32_t value) -{ - union l3_route_ctrl_ext_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_l3_route_ctrl_ext_get(dev_id, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.host_hash_mode_1 = value; - ret = hppe_l3_route_ctrl_ext_set(dev_id, ®_val); - return ret; -} - -sw_error_t -hppe_l3_route_ctrl_ext_ip_route_mismatch_get( - a_uint32_t dev_id, - a_uint32_t *value) -{ - union l3_route_ctrl_ext_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_l3_route_ctrl_ext_get(dev_id, ®_val); - *value = reg_val.bf.ip_route_mismatch; - return ret; -} - -sw_error_t -hppe_l3_route_ctrl_ext_ip_route_mismatch_set( - a_uint32_t dev_id, - a_uint32_t value) -{ - union l3_route_ctrl_ext_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_l3_route_ctrl_ext_get(dev_id, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.ip_route_mismatch = value; - ret = hppe_l3_route_ctrl_ext_set(dev_id, ®_val); - return ret; -} - -sw_error_t -hppe_host_tbl_op_entry_index_get( - a_uint32_t dev_id, - a_uint32_t *value) -{ - union host_tbl_op_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_host_tbl_op_get(dev_id, ®_val); - *value = reg_val.bf.entry_index; - return ret; -} - -sw_error_t -hppe_host_tbl_op_entry_index_set( - a_uint32_t dev_id, - a_uint32_t value) -{ - union host_tbl_op_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_host_tbl_op_get(dev_id, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.entry_index = value; - ret = hppe_host_tbl_op_set(dev_id, ®_val); - return ret; -} - -sw_error_t -hppe_host_tbl_op_cmd_id_get( - a_uint32_t dev_id, - a_uint32_t *value) -{ - union host_tbl_op_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_host_tbl_op_get(dev_id, ®_val); - *value = reg_val.bf.cmd_id; - return ret; -} - -sw_error_t -hppe_host_tbl_op_cmd_id_set( - a_uint32_t dev_id, - a_uint32_t value) -{ - union host_tbl_op_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_host_tbl_op_get(dev_id, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.cmd_id = value; - ret = hppe_host_tbl_op_set(dev_id, ®_val); - return ret; -} - -sw_error_t -hppe_host_tbl_op_byp_rslt_en_get( - a_uint32_t dev_id, - a_uint32_t *value) -{ - union host_tbl_op_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_host_tbl_op_get(dev_id, ®_val); - *value = reg_val.bf.byp_rslt_en; - return ret; -} - -sw_error_t -hppe_host_tbl_op_byp_rslt_en_set( - a_uint32_t dev_id, - a_uint32_t value) -{ - union host_tbl_op_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_host_tbl_op_get(dev_id, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.byp_rslt_en = value; - ret = hppe_host_tbl_op_set(dev_id, ®_val); - return ret; -} - -sw_error_t -hppe_host_tbl_op_op_mode_get( - a_uint32_t dev_id, - a_uint32_t *value) -{ - union host_tbl_op_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_host_tbl_op_get(dev_id, ®_val); - *value = reg_val.bf.op_mode; - return ret; -} - -sw_error_t -hppe_host_tbl_op_op_mode_set( - a_uint32_t dev_id, - a_uint32_t value) -{ - union host_tbl_op_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_host_tbl_op_get(dev_id, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.op_mode = value; - ret = hppe_host_tbl_op_set(dev_id, ®_val); - return ret; -} - -sw_error_t -hppe_host_tbl_op_op_type_get( - a_uint32_t dev_id, - a_uint32_t *value) -{ - union host_tbl_op_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_host_tbl_op_get(dev_id, ®_val); - *value = reg_val.bf.op_type; - return ret; -} - -sw_error_t -hppe_host_tbl_op_op_type_set( - a_uint32_t dev_id, - a_uint32_t value) -{ - union host_tbl_op_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_host_tbl_op_get(dev_id, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.op_type = value; - ret = hppe_host_tbl_op_set(dev_id, ®_val); - return ret; -} - -sw_error_t -hppe_host_tbl_op_op_result_get( - a_uint32_t dev_id, - a_uint32_t *value) -{ - union host_tbl_op_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_host_tbl_op_get(dev_id, ®_val); - *value = reg_val.bf.op_result; - return ret; -} - -sw_error_t -hppe_host_tbl_op_op_result_set( - a_uint32_t dev_id, - a_uint32_t value) -{ - union host_tbl_op_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_host_tbl_op_get(dev_id, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.op_result = value; - ret = hppe_host_tbl_op_set(dev_id, ®_val); - return ret; -} - -sw_error_t -hppe_host_tbl_op_busy_get( - a_uint32_t dev_id, - a_uint32_t *value) -{ - union host_tbl_op_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_host_tbl_op_get(dev_id, ®_val); - *value = reg_val.bf.busy; - return ret; -} - -sw_error_t -hppe_host_tbl_op_busy_set( - a_uint32_t dev_id, - a_uint32_t value) -{ - union host_tbl_op_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_host_tbl_op_get(dev_id, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.busy = value; - ret = hppe_host_tbl_op_set(dev_id, ®_val); - return ret; -} - -sw_error_t -hppe_host_tbl_op_hash_block_bitmap_get( - a_uint32_t dev_id, - a_uint32_t *value) -{ - union host_tbl_op_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_host_tbl_op_get(dev_id, ®_val); - *value = reg_val.bf.hash_block_bitmap; - return ret; -} - -sw_error_t -hppe_host_tbl_op_hash_block_bitmap_set( - a_uint32_t dev_id, - a_uint32_t value) -{ - union host_tbl_op_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_host_tbl_op_get(dev_id, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.hash_block_bitmap = value; - ret = hppe_host_tbl_op_set(dev_id, ®_val); - return ret; -} - -sw_error_t -hppe_host_tbl_op_data0_data_get( - a_uint32_t dev_id, - a_uint32_t *value) -{ - union host_tbl_op_data0_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_host_tbl_op_data0_get(dev_id, ®_val); - *value = reg_val.bf.data; - return ret; -} - -sw_error_t -hppe_host_tbl_op_data0_data_set( - a_uint32_t dev_id, - a_uint32_t value) -{ - union host_tbl_op_data0_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_host_tbl_op_data0_get(dev_id, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.data = value; - ret = hppe_host_tbl_op_data0_set(dev_id, ®_val); - return ret; -} - -sw_error_t -hppe_host_tbl_op_data1_data_get( - a_uint32_t dev_id, - a_uint32_t *value) -{ - union host_tbl_op_data1_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_host_tbl_op_data1_get(dev_id, ®_val); - *value = reg_val.bf.data; - return ret; -} - -sw_error_t -hppe_host_tbl_op_data1_data_set( - a_uint32_t dev_id, - a_uint32_t value) -{ - union host_tbl_op_data1_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_host_tbl_op_data1_get(dev_id, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.data = value; - ret = hppe_host_tbl_op_data1_set(dev_id, ®_val); - return ret; -} - -sw_error_t -hppe_host_tbl_op_data2_data_get( - a_uint32_t dev_id, - a_uint32_t *value) -{ - union host_tbl_op_data2_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_host_tbl_op_data2_get(dev_id, ®_val); - *value = reg_val.bf.data; - return ret; -} - -sw_error_t -hppe_host_tbl_op_data2_data_set( - a_uint32_t dev_id, - a_uint32_t value) -{ - union host_tbl_op_data2_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_host_tbl_op_data2_get(dev_id, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.data = value; - ret = hppe_host_tbl_op_data2_set(dev_id, ®_val); - return ret; -} - -sw_error_t -hppe_host_tbl_op_data3_data_get( - a_uint32_t dev_id, - a_uint32_t *value) -{ - union host_tbl_op_data3_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_host_tbl_op_data3_get(dev_id, ®_val); - *value = reg_val.bf.data; - return ret; -} - -sw_error_t -hppe_host_tbl_op_data3_data_set( - a_uint32_t dev_id, - a_uint32_t value) -{ - union host_tbl_op_data3_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_host_tbl_op_data3_get(dev_id, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.data = value; - ret = hppe_host_tbl_op_data3_set(dev_id, ®_val); - return ret; -} - -sw_error_t -hppe_host_tbl_op_data4_data_get( - a_uint32_t dev_id, - a_uint32_t *value) -{ - union host_tbl_op_data4_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_host_tbl_op_data4_get(dev_id, ®_val); - *value = reg_val.bf.data; - return ret; -} - -sw_error_t -hppe_host_tbl_op_data4_data_set( - a_uint32_t dev_id, - a_uint32_t value) -{ - union host_tbl_op_data4_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_host_tbl_op_data4_get(dev_id, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.data = value; - ret = hppe_host_tbl_op_data4_set(dev_id, ®_val); - return ret; -} - -sw_error_t -hppe_host_tbl_op_data5_data_get( - a_uint32_t dev_id, - a_uint32_t *value) -{ - union host_tbl_op_data5_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_host_tbl_op_data5_get(dev_id, ®_val); - *value = reg_val.bf.data; - return ret; -} - -sw_error_t -hppe_host_tbl_op_data5_data_set( - a_uint32_t dev_id, - a_uint32_t value) -{ - union host_tbl_op_data5_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_host_tbl_op_data5_get(dev_id, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.data = value; - ret = hppe_host_tbl_op_data5_set(dev_id, ®_val); - return ret; -} - -sw_error_t -hppe_host_tbl_op_data6_data_get( - a_uint32_t dev_id, - a_uint32_t *value) -{ - union host_tbl_op_data6_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_host_tbl_op_data6_get(dev_id, ®_val); - *value = reg_val.bf.data; - return ret; -} - -sw_error_t -hppe_host_tbl_op_data6_data_set( - a_uint32_t dev_id, - a_uint32_t value) -{ - union host_tbl_op_data6_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_host_tbl_op_data6_get(dev_id, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.data = value; - ret = hppe_host_tbl_op_data6_set(dev_id, ®_val); - return ret; -} - -sw_error_t -hppe_host_tbl_op_data7_data_get( - a_uint32_t dev_id, - a_uint32_t *value) -{ - union host_tbl_op_data7_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_host_tbl_op_data7_get(dev_id, ®_val); - *value = reg_val.bf.data; - return ret; -} - -sw_error_t -hppe_host_tbl_op_data7_data_set( - a_uint32_t dev_id, - a_uint32_t value) -{ - union host_tbl_op_data7_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_host_tbl_op_data7_get(dev_id, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.data = value; - ret = hppe_host_tbl_op_data7_set(dev_id, ®_val); - return ret; -} - -sw_error_t -hppe_host_tbl_op_data8_data_get( - a_uint32_t dev_id, - a_uint32_t *value) -{ - union host_tbl_op_data8_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_host_tbl_op_data8_get(dev_id, ®_val); - *value = reg_val.bf.data; - return ret; -} - -sw_error_t -hppe_host_tbl_op_data8_data_set( - a_uint32_t dev_id, - a_uint32_t value) -{ - union host_tbl_op_data8_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_host_tbl_op_data8_get(dev_id, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.data = value; - ret = hppe_host_tbl_op_data8_set(dev_id, ®_val); - return ret; -} - -sw_error_t -hppe_host_tbl_op_data9_data_get( - a_uint32_t dev_id, - a_uint32_t *value) -{ - union host_tbl_op_data9_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_host_tbl_op_data9_get(dev_id, ®_val); - *value = reg_val.bf.data; - return ret; -} - -sw_error_t -hppe_host_tbl_op_data9_data_set( - a_uint32_t dev_id, - a_uint32_t value) -{ - union host_tbl_op_data9_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_host_tbl_op_data9_get(dev_id, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.data = value; - ret = hppe_host_tbl_op_data9_set(dev_id, ®_val); - return ret; -} - -sw_error_t -hppe_host_tbl_op_rslt_op_rslt_get( - a_uint32_t dev_id, - a_uint32_t *value) -{ - union host_tbl_op_rslt_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_host_tbl_op_rslt_get(dev_id, ®_val); - *value = reg_val.bf.op_rslt; - return ret; -} - -sw_error_t -hppe_host_tbl_op_rslt_op_rslt_set( - a_uint32_t dev_id, - a_uint32_t value) -{ - return SW_NOT_SUPPORTED; -} - -sw_error_t -hppe_host_tbl_op_rslt_valid_cnt_get( - a_uint32_t dev_id, - a_uint32_t *value) -{ - union host_tbl_op_rslt_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_host_tbl_op_rslt_get(dev_id, ®_val); - *value = reg_val.bf.valid_cnt; - return ret; -} - -sw_error_t -hppe_host_tbl_op_rslt_valid_cnt_set( - a_uint32_t dev_id, - a_uint32_t value) -{ - return SW_NOT_SUPPORTED; -} - -sw_error_t -hppe_host_tbl_op_rslt_entry_index_get( - a_uint32_t dev_id, - a_uint32_t *value) -{ - union host_tbl_op_rslt_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_host_tbl_op_rslt_get(dev_id, ®_val); - *value = reg_val.bf.entry_index; - return ret; -} - -sw_error_t -hppe_host_tbl_op_rslt_entry_index_set( - a_uint32_t dev_id, - a_uint32_t value) -{ - return SW_NOT_SUPPORTED; -} - -sw_error_t -hppe_host_tbl_op_rslt_cmd_id_get( - a_uint32_t dev_id, - a_uint32_t *value) -{ - union host_tbl_op_rslt_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_host_tbl_op_rslt_get(dev_id, ®_val); - *value = reg_val.bf.cmd_id; - return ret; -} - -sw_error_t -hppe_host_tbl_op_rslt_cmd_id_set( - a_uint32_t dev_id, - a_uint32_t value) -{ - return SW_NOT_SUPPORTED; -} - -sw_error_t -hppe_host_tbl_rd_op_entry_index_get( - a_uint32_t dev_id, - a_uint32_t *value) -{ - union host_tbl_rd_op_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_host_tbl_rd_op_get(dev_id, ®_val); - *value = reg_val.bf.entry_index; - return ret; -} - -sw_error_t -hppe_host_tbl_rd_op_entry_index_set( - a_uint32_t dev_id, - a_uint32_t value) -{ - union host_tbl_rd_op_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_host_tbl_rd_op_get(dev_id, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.entry_index = value; - ret = hppe_host_tbl_rd_op_set(dev_id, ®_val); - return ret; -} - -sw_error_t -hppe_host_tbl_rd_op_cmd_id_get( - a_uint32_t dev_id, - a_uint32_t *value) -{ - union host_tbl_rd_op_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_host_tbl_rd_op_get(dev_id, ®_val); - *value = reg_val.bf.cmd_id; - return ret; -} - -sw_error_t -hppe_host_tbl_rd_op_cmd_id_set( - a_uint32_t dev_id, - a_uint32_t value) -{ - union host_tbl_rd_op_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_host_tbl_rd_op_get(dev_id, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.cmd_id = value; - ret = hppe_host_tbl_rd_op_set(dev_id, ®_val); - return ret; -} - -sw_error_t -hppe_host_tbl_rd_op_byp_rslt_en_get( - a_uint32_t dev_id, - a_uint32_t *value) -{ - union host_tbl_rd_op_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_host_tbl_rd_op_get(dev_id, ®_val); - *value = reg_val.bf.byp_rslt_en; - return ret; -} - -sw_error_t -hppe_host_tbl_rd_op_byp_rslt_en_set( - a_uint32_t dev_id, - a_uint32_t value) -{ - union host_tbl_rd_op_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_host_tbl_rd_op_get(dev_id, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.byp_rslt_en = value; - ret = hppe_host_tbl_rd_op_set(dev_id, ®_val); - return ret; -} - -sw_error_t -hppe_host_tbl_rd_op_op_mode_get( - a_uint32_t dev_id, - a_uint32_t *value) -{ - union host_tbl_rd_op_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_host_tbl_rd_op_get(dev_id, ®_val); - *value = reg_val.bf.op_mode; - return ret; -} - -sw_error_t -hppe_host_tbl_rd_op_op_mode_set( - a_uint32_t dev_id, - a_uint32_t value) -{ - union host_tbl_rd_op_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_host_tbl_rd_op_get(dev_id, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.op_mode = value; - ret = hppe_host_tbl_rd_op_set(dev_id, ®_val); - return ret; -} - -sw_error_t -hppe_host_tbl_rd_op_op_type_get( - a_uint32_t dev_id, - a_uint32_t *value) -{ - union host_tbl_rd_op_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_host_tbl_rd_op_get(dev_id, ®_val); - *value = reg_val.bf.op_type; - return ret; -} - -sw_error_t -hppe_host_tbl_rd_op_op_type_set( - a_uint32_t dev_id, - a_uint32_t value) -{ - union host_tbl_rd_op_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_host_tbl_rd_op_get(dev_id, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.op_type = value; - ret = hppe_host_tbl_rd_op_set(dev_id, ®_val); - return ret; -} - -sw_error_t -hppe_host_tbl_rd_op_op_result_get( - a_uint32_t dev_id, - a_uint32_t *value) -{ - union host_tbl_rd_op_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_host_tbl_rd_op_get(dev_id, ®_val); - *value = reg_val.bf.op_result; - return ret; -} - -sw_error_t -hppe_host_tbl_rd_op_op_result_set( - a_uint32_t dev_id, - a_uint32_t value) -{ - union host_tbl_rd_op_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_host_tbl_rd_op_get(dev_id, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.op_result = value; - ret = hppe_host_tbl_rd_op_set(dev_id, ®_val); - return ret; -} - -sw_error_t -hppe_host_tbl_rd_op_busy_get( - a_uint32_t dev_id, - a_uint32_t *value) -{ - union host_tbl_rd_op_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_host_tbl_rd_op_get(dev_id, ®_val); - *value = reg_val.bf.busy; - return ret; -} - -sw_error_t -hppe_host_tbl_rd_op_busy_set( - a_uint32_t dev_id, - a_uint32_t value) -{ - union host_tbl_rd_op_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_host_tbl_rd_op_get(dev_id, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.busy = value; - ret = hppe_host_tbl_rd_op_set(dev_id, ®_val); - return ret; -} - -sw_error_t -hppe_host_tbl_rd_op_hash_block_bitmap_get( - a_uint32_t dev_id, - a_uint32_t *value) -{ - union host_tbl_rd_op_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_host_tbl_rd_op_get(dev_id, ®_val); - *value = reg_val.bf.hash_block_bitmap; - return ret; -} - -sw_error_t -hppe_host_tbl_rd_op_hash_block_bitmap_set( - a_uint32_t dev_id, - a_uint32_t value) -{ - union host_tbl_rd_op_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_host_tbl_rd_op_get(dev_id, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.hash_block_bitmap = value; - ret = hppe_host_tbl_rd_op_set(dev_id, ®_val); - return ret; -} - -sw_error_t -hppe_host_tbl_rd_op_data0_data_get( - a_uint32_t dev_id, - a_uint32_t *value) -{ - union host_tbl_rd_op_data0_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_host_tbl_rd_op_data0_get(dev_id, ®_val); - *value = reg_val.bf.data; - return ret; -} - -sw_error_t -hppe_host_tbl_rd_op_data0_data_set( - a_uint32_t dev_id, - a_uint32_t value) -{ - union host_tbl_rd_op_data0_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_host_tbl_rd_op_data0_get(dev_id, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.data = value; - ret = hppe_host_tbl_rd_op_data0_set(dev_id, ®_val); - return ret; -} - -sw_error_t -hppe_host_tbl_rd_op_data1_data_get( - a_uint32_t dev_id, - a_uint32_t *value) -{ - union host_tbl_rd_op_data1_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_host_tbl_rd_op_data1_get(dev_id, ®_val); - *value = reg_val.bf.data; - return ret; -} - -sw_error_t -hppe_host_tbl_rd_op_data1_data_set( - a_uint32_t dev_id, - a_uint32_t value) -{ - union host_tbl_rd_op_data1_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_host_tbl_rd_op_data1_get(dev_id, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.data = value; - ret = hppe_host_tbl_rd_op_data1_set(dev_id, ®_val); - return ret; -} - -sw_error_t -hppe_host_tbl_rd_op_data2_data_get( - a_uint32_t dev_id, - a_uint32_t *value) -{ - union host_tbl_rd_op_data2_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_host_tbl_rd_op_data2_get(dev_id, ®_val); - *value = reg_val.bf.data; - return ret; -} - -sw_error_t -hppe_host_tbl_rd_op_data2_data_set( - a_uint32_t dev_id, - a_uint32_t value) -{ - union host_tbl_rd_op_data2_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_host_tbl_rd_op_data2_get(dev_id, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.data = value; - ret = hppe_host_tbl_rd_op_data2_set(dev_id, ®_val); - return ret; -} - -sw_error_t -hppe_host_tbl_rd_op_data3_data_get( - a_uint32_t dev_id, - a_uint32_t *value) -{ - union host_tbl_rd_op_data3_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_host_tbl_rd_op_data3_get(dev_id, ®_val); - *value = reg_val.bf.data; - return ret; -} - -sw_error_t -hppe_host_tbl_rd_op_data3_data_set( - a_uint32_t dev_id, - a_uint32_t value) -{ - union host_tbl_rd_op_data3_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_host_tbl_rd_op_data3_get(dev_id, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.data = value; - ret = hppe_host_tbl_rd_op_data3_set(dev_id, ®_val); - return ret; -} - -sw_error_t -hppe_host_tbl_rd_op_data4_data_get( - a_uint32_t dev_id, - a_uint32_t *value) -{ - union host_tbl_rd_op_data4_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_host_tbl_rd_op_data4_get(dev_id, ®_val); - *value = reg_val.bf.data; - return ret; -} - -sw_error_t -hppe_host_tbl_rd_op_data4_data_set( - a_uint32_t dev_id, - a_uint32_t value) -{ - union host_tbl_rd_op_data4_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_host_tbl_rd_op_data4_get(dev_id, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.data = value; - ret = hppe_host_tbl_rd_op_data4_set(dev_id, ®_val); - return ret; -} - -sw_error_t -hppe_host_tbl_rd_op_data5_data_get( - a_uint32_t dev_id, - a_uint32_t *value) -{ - union host_tbl_rd_op_data5_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_host_tbl_rd_op_data5_get(dev_id, ®_val); - *value = reg_val.bf.data; - return ret; -} - -sw_error_t -hppe_host_tbl_rd_op_data5_data_set( - a_uint32_t dev_id, - a_uint32_t value) -{ - union host_tbl_rd_op_data5_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_host_tbl_rd_op_data5_get(dev_id, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.data = value; - ret = hppe_host_tbl_rd_op_data5_set(dev_id, ®_val); - return ret; -} - -sw_error_t -hppe_host_tbl_rd_op_data6_data_get( - a_uint32_t dev_id, - a_uint32_t *value) -{ - union host_tbl_rd_op_data6_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_host_tbl_rd_op_data6_get(dev_id, ®_val); - *value = reg_val.bf.data; - return ret; -} - -sw_error_t -hppe_host_tbl_rd_op_data6_data_set( - a_uint32_t dev_id, - a_uint32_t value) -{ - union host_tbl_rd_op_data6_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_host_tbl_rd_op_data6_get(dev_id, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.data = value; - ret = hppe_host_tbl_rd_op_data6_set(dev_id, ®_val); - return ret; -} - -sw_error_t -hppe_host_tbl_rd_op_data7_data_get( - a_uint32_t dev_id, - a_uint32_t *value) -{ - union host_tbl_rd_op_data7_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_host_tbl_rd_op_data7_get(dev_id, ®_val); - *value = reg_val.bf.data; - return ret; -} - -sw_error_t -hppe_host_tbl_rd_op_data7_data_set( - a_uint32_t dev_id, - a_uint32_t value) -{ - union host_tbl_rd_op_data7_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_host_tbl_rd_op_data7_get(dev_id, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.data = value; - ret = hppe_host_tbl_rd_op_data7_set(dev_id, ®_val); - return ret; -} - -sw_error_t -hppe_host_tbl_rd_op_data8_data_get( - a_uint32_t dev_id, - a_uint32_t *value) -{ - union host_tbl_rd_op_data8_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_host_tbl_rd_op_data8_get(dev_id, ®_val); - *value = reg_val.bf.data; - return ret; -} - -sw_error_t -hppe_host_tbl_rd_op_data8_data_set( - a_uint32_t dev_id, - a_uint32_t value) -{ - union host_tbl_rd_op_data8_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_host_tbl_rd_op_data8_get(dev_id, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.data = value; - ret = hppe_host_tbl_rd_op_data8_set(dev_id, ®_val); - return ret; -} - -sw_error_t -hppe_host_tbl_rd_op_data9_data_get( - a_uint32_t dev_id, - a_uint32_t *value) -{ - union host_tbl_rd_op_data9_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_host_tbl_rd_op_data9_get(dev_id, ®_val); - *value = reg_val.bf.data; - return ret; -} - -sw_error_t -hppe_host_tbl_rd_op_data9_data_set( - a_uint32_t dev_id, - a_uint32_t value) -{ - union host_tbl_rd_op_data9_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_host_tbl_rd_op_data9_get(dev_id, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.data = value; - ret = hppe_host_tbl_rd_op_data9_set(dev_id, ®_val); - return ret; -} - -sw_error_t -hppe_host_tbl_rd_op_rslt_op_rslt_get( - a_uint32_t dev_id, - a_uint32_t *value) -{ - union host_tbl_rd_op_rslt_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_host_tbl_rd_op_rslt_get(dev_id, ®_val); - *value = reg_val.bf.op_rslt; - return ret; -} - -sw_error_t -hppe_host_tbl_rd_op_rslt_op_rslt_set( - a_uint32_t dev_id, - a_uint32_t value) -{ - return SW_NOT_SUPPORTED; -} - -sw_error_t -hppe_host_tbl_rd_op_rslt_valid_cnt_get( - a_uint32_t dev_id, - a_uint32_t *value) -{ - union host_tbl_rd_op_rslt_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_host_tbl_rd_op_rslt_get(dev_id, ®_val); - *value = reg_val.bf.valid_cnt; - return ret; -} - -sw_error_t -hppe_host_tbl_rd_op_rslt_valid_cnt_set( - a_uint32_t dev_id, - a_uint32_t value) -{ - return SW_NOT_SUPPORTED; -} - -sw_error_t -hppe_host_tbl_rd_op_rslt_entry_index_get( - a_uint32_t dev_id, - a_uint32_t *value) -{ - union host_tbl_rd_op_rslt_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_host_tbl_rd_op_rslt_get(dev_id, ®_val); - *value = reg_val.bf.entry_index; - return ret; -} - -sw_error_t -hppe_host_tbl_rd_op_rslt_entry_index_set( - a_uint32_t dev_id, - a_uint32_t value) -{ - return SW_NOT_SUPPORTED; -} - -sw_error_t -hppe_host_tbl_rd_op_rslt_cmd_id_get( - a_uint32_t dev_id, - a_uint32_t *value) -{ - union host_tbl_rd_op_rslt_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_host_tbl_rd_op_rslt_get(dev_id, ®_val); - *value = reg_val.bf.cmd_id; - return ret; -} - -sw_error_t -hppe_host_tbl_rd_op_rslt_cmd_id_set( - a_uint32_t dev_id, - a_uint32_t value) -{ - return SW_NOT_SUPPORTED; -} - -sw_error_t -hppe_host_tbl_rd_rslt_data0_data_get( - a_uint32_t dev_id, - a_uint32_t *value) -{ - union host_tbl_rd_rslt_data0_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_host_tbl_rd_rslt_data0_get(dev_id, ®_val); - *value = reg_val.bf.data; - return ret; -} - -sw_error_t -hppe_host_tbl_rd_rslt_data0_data_set( - a_uint32_t dev_id, - a_uint32_t value) -{ - return SW_NOT_SUPPORTED; -} - -sw_error_t -hppe_host_tbl_rd_rslt_data1_data_get( - a_uint32_t dev_id, - a_uint32_t *value) -{ - union host_tbl_rd_rslt_data1_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_host_tbl_rd_rslt_data1_get(dev_id, ®_val); - *value = reg_val.bf.data; - return ret; -} - -sw_error_t -hppe_host_tbl_rd_rslt_data1_data_set( - a_uint32_t dev_id, - a_uint32_t value) -{ - return SW_NOT_SUPPORTED; -} - -sw_error_t -hppe_host_tbl_rd_rslt_data2_data_get( - a_uint32_t dev_id, - a_uint32_t *value) -{ - union host_tbl_rd_rslt_data2_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_host_tbl_rd_rslt_data2_get(dev_id, ®_val); - *value = reg_val.bf.data; - return ret; -} - -sw_error_t -hppe_host_tbl_rd_rslt_data2_data_set( - a_uint32_t dev_id, - a_uint32_t value) -{ - return SW_NOT_SUPPORTED; -} - -sw_error_t -hppe_host_tbl_rd_rslt_data3_data_get( - a_uint32_t dev_id, - a_uint32_t *value) -{ - union host_tbl_rd_rslt_data3_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_host_tbl_rd_rslt_data3_get(dev_id, ®_val); - *value = reg_val.bf.data; - return ret; -} - -sw_error_t -hppe_host_tbl_rd_rslt_data3_data_set( - a_uint32_t dev_id, - a_uint32_t value) -{ - return SW_NOT_SUPPORTED; -} - -sw_error_t -hppe_host_tbl_rd_rslt_data4_data_get( - a_uint32_t dev_id, - a_uint32_t *value) -{ - union host_tbl_rd_rslt_data4_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_host_tbl_rd_rslt_data4_get(dev_id, ®_val); - *value = reg_val.bf.data; - return ret; -} - -sw_error_t -hppe_host_tbl_rd_rslt_data4_data_set( - a_uint32_t dev_id, - a_uint32_t value) -{ - return SW_NOT_SUPPORTED; -} - -sw_error_t -hppe_host_tbl_rd_rslt_data5_data_get( - a_uint32_t dev_id, - a_uint32_t *value) -{ - union host_tbl_rd_rslt_data5_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_host_tbl_rd_rslt_data5_get(dev_id, ®_val); - *value = reg_val.bf.data; - return ret; -} - -sw_error_t -hppe_host_tbl_rd_rslt_data5_data_set( - a_uint32_t dev_id, - a_uint32_t value) -{ - return SW_NOT_SUPPORTED; -} - -sw_error_t -hppe_host_tbl_rd_rslt_data6_data_get( - a_uint32_t dev_id, - a_uint32_t *value) -{ - union host_tbl_rd_rslt_data6_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_host_tbl_rd_rslt_data6_get(dev_id, ®_val); - *value = reg_val.bf.data; - return ret; -} - -sw_error_t -hppe_host_tbl_rd_rslt_data6_data_set( - a_uint32_t dev_id, - a_uint32_t value) -{ - return SW_NOT_SUPPORTED; -} - -sw_error_t -hppe_host_tbl_rd_rslt_data7_data_get( - a_uint32_t dev_id, - a_uint32_t *value) -{ - union host_tbl_rd_rslt_data7_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_host_tbl_rd_rslt_data7_get(dev_id, ®_val); - *value = reg_val.bf.data; - return ret; -} - -sw_error_t -hppe_host_tbl_rd_rslt_data7_data_set( - a_uint32_t dev_id, - a_uint32_t value) -{ - return SW_NOT_SUPPORTED; -} - -sw_error_t -hppe_host_tbl_rd_rslt_data8_data_get( - a_uint32_t dev_id, - a_uint32_t *value) -{ - union host_tbl_rd_rslt_data8_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_host_tbl_rd_rslt_data8_get(dev_id, ®_val); - *value = reg_val.bf.data; - return ret; -} - -sw_error_t -hppe_host_tbl_rd_rslt_data8_data_set( - a_uint32_t dev_id, - a_uint32_t value) -{ - return SW_NOT_SUPPORTED; -} - -sw_error_t -hppe_host_tbl_rd_rslt_data9_data_get( - a_uint32_t dev_id, - a_uint32_t *value) -{ - union host_tbl_rd_rslt_data9_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_host_tbl_rd_rslt_data9_get(dev_id, ®_val); - *value = reg_val.bf.data; - return ret; -} - -sw_error_t -hppe_host_tbl_rd_rslt_data9_data_set( - a_uint32_t dev_id, - a_uint32_t value) -{ - return SW_NOT_SUPPORTED; -} - -sw_error_t -hppe_l3_dbg_cmd_type_get( - a_uint32_t dev_id, - a_uint32_t *value) -{ - union l3_dbg_cmd_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_l3_dbg_cmd_get(dev_id, ®_val); - *value = reg_val.bf.type; - return ret; -} - -sw_error_t -hppe_l3_dbg_cmd_type_set( - a_uint32_t dev_id, - a_uint32_t value) -{ - union l3_dbg_cmd_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_l3_dbg_cmd_get(dev_id, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.type = value; - ret = hppe_l3_dbg_cmd_set(dev_id, ®_val); - return ret; -} - -sw_error_t -hppe_l3_dbg_cmd_addr_get( - a_uint32_t dev_id, - a_uint32_t *value) -{ - union l3_dbg_cmd_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_l3_dbg_cmd_get(dev_id, ®_val); - *value = reg_val.bf.addr; - return ret; -} - -sw_error_t -hppe_l3_dbg_cmd_addr_set( - a_uint32_t dev_id, - a_uint32_t value) -{ - union l3_dbg_cmd_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_l3_dbg_cmd_get(dev_id, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.addr = value; - ret = hppe_l3_dbg_cmd_set(dev_id, ®_val); - return ret; -} - -sw_error_t -hppe_l3_dbg_wr_data_data_get( - a_uint32_t dev_id, - a_uint32_t *value) -{ - union l3_dbg_wr_data_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_l3_dbg_wr_data_get(dev_id, ®_val); - *value = reg_val.bf.data; - return ret; -} - -sw_error_t -hppe_l3_dbg_wr_data_data_set( - a_uint32_t dev_id, - a_uint32_t value) -{ - union l3_dbg_wr_data_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_l3_dbg_wr_data_get(dev_id, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.data = value; - ret = hppe_l3_dbg_wr_data_set(dev_id, ®_val); - return ret; -} - -sw_error_t -hppe_l3_dbg_rd_data_data_get( - a_uint32_t dev_id, - a_uint32_t *value) -{ - union l3_dbg_rd_data_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_l3_dbg_rd_data_get(dev_id, ®_val); - *value = reg_val.bf.data; - return ret; -} - -sw_error_t -hppe_l3_dbg_rd_data_data_set( - a_uint32_t dev_id, - a_uint32_t value) -{ - return SW_NOT_SUPPORTED; -} - -sw_error_t -hppe_l3_vp_port_tbl_ip_arp_sg_en_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union l3_vp_port_tbl_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_l3_vp_port_tbl_get(dev_id, index, ®_val); - *value = reg_val.bf.ip_arp_sg_en; - return ret; -} - -sw_error_t -hppe_l3_vp_port_tbl_ip_arp_sg_en_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - union l3_vp_port_tbl_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_l3_vp_port_tbl_get(dev_id, index, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.ip_arp_sg_en = value; - ret = hppe_l3_vp_port_tbl_set(dev_id, index, ®_val); - return ret; -} - -sw_error_t -hppe_l3_vp_port_tbl_ipv6_sg_svlan_en_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union l3_vp_port_tbl_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_l3_vp_port_tbl_get(dev_id, index, ®_val); - *value = reg_val.bf.ipv6_sg_svlan_en; - return ret; -} - -sw_error_t -hppe_l3_vp_port_tbl_ipv6_sg_svlan_en_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - union l3_vp_port_tbl_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_l3_vp_port_tbl_get(dev_id, index, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.ipv6_sg_svlan_en = value; - ret = hppe_l3_vp_port_tbl_set(dev_id, index, ®_val); - return ret; -} - -sw_error_t -hppe_l3_vp_port_tbl_ip_nd_sg_cvlan_en_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union l3_vp_port_tbl_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_l3_vp_port_tbl_get(dev_id, index, ®_val); - *value = reg_val.bf.ip_nd_sg_cvlan_en; - return ret; -} - -sw_error_t -hppe_l3_vp_port_tbl_ip_nd_sg_cvlan_en_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - union l3_vp_port_tbl_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_l3_vp_port_tbl_get(dev_id, index, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.ip_nd_sg_cvlan_en = value; - ret = hppe_l3_vp_port_tbl_set(dev_id, index, ®_val); - return ret; -} - -sw_error_t -hppe_l3_vp_port_tbl_l3_if_valid_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union l3_vp_port_tbl_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_l3_vp_port_tbl_get(dev_id, index, ®_val); - *value = reg_val.bf.l3_if_valid; - return ret; -} - -sw_error_t -hppe_l3_vp_port_tbl_l3_if_valid_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - union l3_vp_port_tbl_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_l3_vp_port_tbl_get(dev_id, index, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.l3_if_valid = value; - ret = hppe_l3_vp_port_tbl_set(dev_id, index, ®_val); - return ret; -} - -sw_error_t -hppe_l3_vp_port_tbl_ip_nd_sg_vio_cmd_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union l3_vp_port_tbl_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_l3_vp_port_tbl_get(dev_id, index, ®_val); - *value = reg_val.bf.ip_nd_sg_vio_cmd; - return ret; -} - -sw_error_t -hppe_l3_vp_port_tbl_ip_nd_sg_vio_cmd_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - union l3_vp_port_tbl_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_l3_vp_port_tbl_get(dev_id, index, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.ip_nd_sg_vio_cmd = value; - ret = hppe_l3_vp_port_tbl_set(dev_id, index, ®_val); - return ret; -} - -sw_error_t -hppe_l3_vp_port_tbl_ipv4_sg_port_en_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union l3_vp_port_tbl_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_l3_vp_port_tbl_get(dev_id, index, ®_val); - *value = reg_val.bf.ipv4_sg_port_en; - return ret; -} - -sw_error_t -hppe_l3_vp_port_tbl_ipv4_sg_port_en_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - union l3_vp_port_tbl_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_l3_vp_port_tbl_get(dev_id, index, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.ipv4_sg_port_en = value; - ret = hppe_l3_vp_port_tbl_set(dev_id, index, ®_val); - return ret; -} - -sw_error_t -hppe_l3_vp_port_tbl_ip_nd_sg_en_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union l3_vp_port_tbl_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_l3_vp_port_tbl_get(dev_id, index, ®_val); - *value = reg_val.bf.ip_nd_sg_en; - return ret; -} - -sw_error_t -hppe_l3_vp_port_tbl_ip_nd_sg_en_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - union l3_vp_port_tbl_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_l3_vp_port_tbl_get(dev_id, index, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.ip_nd_sg_en = value; - ret = hppe_l3_vp_port_tbl_set(dev_id, index, ®_val); - return ret; -} - -sw_error_t -hppe_l3_vp_port_tbl_l3_if_index_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union l3_vp_port_tbl_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_l3_vp_port_tbl_get(dev_id, index, ®_val); - *value = reg_val.bf.l3_if_index; - return ret; -} - -sw_error_t -hppe_l3_vp_port_tbl_l3_if_index_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - union l3_vp_port_tbl_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_l3_vp_port_tbl_get(dev_id, index, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.l3_if_index = value; - ret = hppe_l3_vp_port_tbl_set(dev_id, index, ®_val); - return ret; -} - -sw_error_t -hppe_l3_vp_port_tbl_ipv4_sg_svlan_en_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union l3_vp_port_tbl_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_l3_vp_port_tbl_get(dev_id, index, ®_val); - *value = reg_val.bf.ipv4_sg_svlan_en; - return ret; -} - -sw_error_t -hppe_l3_vp_port_tbl_ipv4_sg_svlan_en_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - union l3_vp_port_tbl_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_l3_vp_port_tbl_get(dev_id, index, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.ipv4_sg_svlan_en = value; - ret = hppe_l3_vp_port_tbl_set(dev_id, index, ®_val); - return ret; -} - -sw_error_t -hppe_l3_vp_port_tbl_ipv4_sg_cvlan_en_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union l3_vp_port_tbl_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_l3_vp_port_tbl_get(dev_id, index, ®_val); - *value = reg_val.bf.ipv4_sg_cvlan_en; - return ret; -} - -sw_error_t -hppe_l3_vp_port_tbl_ipv4_sg_cvlan_en_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - union l3_vp_port_tbl_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_l3_vp_port_tbl_get(dev_id, index, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.ipv4_sg_cvlan_en = value; - ret = hppe_l3_vp_port_tbl_set(dev_id, index, ®_val); - return ret; -} - -sw_error_t -hppe_l3_vp_port_tbl_ip_arp_sg_svlan_en_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union l3_vp_port_tbl_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_l3_vp_port_tbl_get(dev_id, index, ®_val); - *value = reg_val.bf.ip_arp_sg_svlan_en; - return ret; -} - -sw_error_t -hppe_l3_vp_port_tbl_ip_arp_sg_svlan_en_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - union l3_vp_port_tbl_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_l3_vp_port_tbl_get(dev_id, index, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.ip_arp_sg_svlan_en = value; - ret = hppe_l3_vp_port_tbl_set(dev_id, index, ®_val); - return ret; -} - -sw_error_t -hppe_l3_vp_port_tbl_mac_valid_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union l3_vp_port_tbl_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_l3_vp_port_tbl_get(dev_id, index, ®_val); - *value = reg_val.bf.mac_valid; - return ret; -} - -sw_error_t -hppe_l3_vp_port_tbl_mac_valid_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - union l3_vp_port_tbl_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_l3_vp_port_tbl_get(dev_id, index, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.mac_valid = value; - ret = hppe_l3_vp_port_tbl_set(dev_id, index, ®_val); - return ret; -} - -sw_error_t -hppe_l3_vp_port_tbl_ip_nd_sg_svlan_en_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union l3_vp_port_tbl_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_l3_vp_port_tbl_get(dev_id, index, ®_val); - *value = reg_val.bf.ip_nd_sg_svlan_en; - return ret; -} - -sw_error_t -hppe_l3_vp_port_tbl_ip_nd_sg_svlan_en_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - union l3_vp_port_tbl_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_l3_vp_port_tbl_get(dev_id, index, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.ip_nd_sg_svlan_en = value; - ret = hppe_l3_vp_port_tbl_set(dev_id, index, ®_val); - return ret; -} - -sw_error_t -hppe_l3_vp_port_tbl_vsi_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union l3_vp_port_tbl_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_l3_vp_port_tbl_get(dev_id, index, ®_val); - *value = reg_val.bf.vsi; - return ret; -} - -sw_error_t -hppe_l3_vp_port_tbl_vsi_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - union l3_vp_port_tbl_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_l3_vp_port_tbl_get(dev_id, index, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.vsi = value; - ret = hppe_l3_vp_port_tbl_set(dev_id, index, ®_val); - return ret; -} - -sw_error_t -hppe_l3_vp_port_tbl_mac_da_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint64_t *value) -{ - union l3_vp_port_tbl_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_l3_vp_port_tbl_get(dev_id, index, ®_val); - *value = (a_uint64_t)reg_val.bf.mac_da_1 << 16 | \ - reg_val.bf.mac_da_0; - return ret; -} - -sw_error_t -hppe_l3_vp_port_tbl_mac_da_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint64_t value) -{ - union l3_vp_port_tbl_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_l3_vp_port_tbl_get(dev_id, index, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.mac_da_1 = value >> 16; - reg_val.bf.mac_da_0 = value & (((a_uint64_t)1<<16)-1); - ret = hppe_l3_vp_port_tbl_set(dev_id, index, ®_val); - return ret; -} - -sw_error_t -hppe_l3_vp_port_tbl_ipv6_sg_vio_cmd_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union l3_vp_port_tbl_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_l3_vp_port_tbl_get(dev_id, index, ®_val); - *value = reg_val.bf.ipv6_sg_vio_cmd; - return ret; -} - -sw_error_t -hppe_l3_vp_port_tbl_ipv6_sg_vio_cmd_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - union l3_vp_port_tbl_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_l3_vp_port_tbl_get(dev_id, index, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.ipv6_sg_vio_cmd = value; - ret = hppe_l3_vp_port_tbl_set(dev_id, index, ®_val); - return ret; -} - -sw_error_t -hppe_l3_vp_port_tbl_ip_nd_sg_port_en_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union l3_vp_port_tbl_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_l3_vp_port_tbl_get(dev_id, index, ®_val); - *value = reg_val.bf.ip_nd_sg_port_en; - return ret; -} - -sw_error_t -hppe_l3_vp_port_tbl_ip_nd_sg_port_en_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - union l3_vp_port_tbl_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_l3_vp_port_tbl_get(dev_id, index, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.ip_nd_sg_port_en = value; - ret = hppe_l3_vp_port_tbl_set(dev_id, index, ®_val); - return ret; -} - -sw_error_t -hppe_l3_vp_port_tbl_ip_arp_src_unk_cmd_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union l3_vp_port_tbl_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_l3_vp_port_tbl_get(dev_id, index, ®_val); - *value = reg_val.bf.ip_arp_src_unk_cmd; - return ret; -} - -sw_error_t -hppe_l3_vp_port_tbl_ip_arp_src_unk_cmd_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - union l3_vp_port_tbl_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_l3_vp_port_tbl_get(dev_id, index, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.ip_arp_src_unk_cmd = value; - ret = hppe_l3_vp_port_tbl_set(dev_id, index, ®_val); - return ret; -} - -sw_error_t -hppe_l3_vp_port_tbl_ipv6_sg_port_en_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union l3_vp_port_tbl_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_l3_vp_port_tbl_get(dev_id, index, ®_val); - *value = reg_val.bf.ipv6_sg_port_en; - return ret; -} - -sw_error_t -hppe_l3_vp_port_tbl_ipv6_sg_port_en_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - union l3_vp_port_tbl_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_l3_vp_port_tbl_get(dev_id, index, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.ipv6_sg_port_en = value; - ret = hppe_l3_vp_port_tbl_set(dev_id, index, ®_val); - return ret; -} - -sw_error_t -hppe_l3_vp_port_tbl_ipv4_src_unk_cmd_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union l3_vp_port_tbl_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_l3_vp_port_tbl_get(dev_id, index, ®_val); - *value = reg_val.bf.ipv4_src_unk_cmd; - return ret; -} - -sw_error_t -hppe_l3_vp_port_tbl_ipv4_src_unk_cmd_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - union l3_vp_port_tbl_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_l3_vp_port_tbl_get(dev_id, index, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.ipv4_src_unk_cmd = value; - ret = hppe_l3_vp_port_tbl_set(dev_id, index, ®_val); - return ret; -} - -sw_error_t -hppe_l3_vp_port_tbl_ip_arp_sg_port_en_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union l3_vp_port_tbl_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_l3_vp_port_tbl_get(dev_id, index, ®_val); - *value = reg_val.bf.ip_arp_sg_port_en; - return ret; -} - -sw_error_t -hppe_l3_vp_port_tbl_ip_arp_sg_port_en_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - union l3_vp_port_tbl_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_l3_vp_port_tbl_get(dev_id, index, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.ip_arp_sg_port_en = value; - ret = hppe_l3_vp_port_tbl_set(dev_id, index, ®_val); - return ret; -} - -sw_error_t -hppe_l3_vp_port_tbl_ip_arp_sg_vio_cmd_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union l3_vp_port_tbl_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_l3_vp_port_tbl_get(dev_id, index, ®_val); - *value = reg_val.bf.ip_arp_sg_vio_cmd; - return ret; -} - -sw_error_t -hppe_l3_vp_port_tbl_ip_arp_sg_vio_cmd_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - union l3_vp_port_tbl_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_l3_vp_port_tbl_get(dev_id, index, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.ip_arp_sg_vio_cmd = value; - ret = hppe_l3_vp_port_tbl_set(dev_id, index, ®_val); - return ret; -} - -sw_error_t -hppe_l3_vp_port_tbl_ipv4_sg_vio_cmd_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union l3_vp_port_tbl_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_l3_vp_port_tbl_get(dev_id, index, ®_val); - *value = reg_val.bf.ipv4_sg_vio_cmd; - return ret; -} - -sw_error_t -hppe_l3_vp_port_tbl_ipv4_sg_vio_cmd_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - union l3_vp_port_tbl_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_l3_vp_port_tbl_get(dev_id, index, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.ipv4_sg_vio_cmd = value; - ret = hppe_l3_vp_port_tbl_set(dev_id, index, ®_val); - return ret; -} - -sw_error_t -hppe_l3_vp_port_tbl_ipv6_src_unk_cmd_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union l3_vp_port_tbl_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_l3_vp_port_tbl_get(dev_id, index, ®_val); - *value = reg_val.bf.ipv6_src_unk_cmd; - return ret; -} - -sw_error_t -hppe_l3_vp_port_tbl_ipv6_src_unk_cmd_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - union l3_vp_port_tbl_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_l3_vp_port_tbl_get(dev_id, index, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.ipv6_src_unk_cmd = value; - ret = hppe_l3_vp_port_tbl_set(dev_id, index, ®_val); - return ret; -} - -sw_error_t -hppe_l3_vp_port_tbl_ip_arp_sg_cvlan_en_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union l3_vp_port_tbl_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_l3_vp_port_tbl_get(dev_id, index, ®_val); - *value = reg_val.bf.ip_arp_sg_cvlan_en; - return ret; -} - -sw_error_t -hppe_l3_vp_port_tbl_ip_arp_sg_cvlan_en_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - union l3_vp_port_tbl_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_l3_vp_port_tbl_get(dev_id, index, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.ip_arp_sg_cvlan_en = value; - ret = hppe_l3_vp_port_tbl_set(dev_id, index, ®_val); - return ret; -} - -sw_error_t -hppe_l3_vp_port_tbl_ipv6_sg_en_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union l3_vp_port_tbl_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_l3_vp_port_tbl_get(dev_id, index, ®_val); - *value = reg_val.bf.ipv6_sg_en; - return ret; -} - -sw_error_t -hppe_l3_vp_port_tbl_ipv6_sg_en_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - union l3_vp_port_tbl_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_l3_vp_port_tbl_get(dev_id, index, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.ipv6_sg_en = value; - ret = hppe_l3_vp_port_tbl_set(dev_id, index, ®_val); - return ret; -} - -sw_error_t -hppe_l3_vp_port_tbl_vsi_valid_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union l3_vp_port_tbl_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_l3_vp_port_tbl_get(dev_id, index, ®_val); - *value = reg_val.bf.vsi_valid; - return ret; -} - -sw_error_t -hppe_l3_vp_port_tbl_vsi_valid_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - union l3_vp_port_tbl_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_l3_vp_port_tbl_get(dev_id, index, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.vsi_valid = value; - ret = hppe_l3_vp_port_tbl_set(dev_id, index, ®_val); - return ret; -} - -sw_error_t -hppe_l3_vp_port_tbl_ip_nd_src_unk_cmd_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union l3_vp_port_tbl_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_l3_vp_port_tbl_get(dev_id, index, ®_val); - *value = reg_val.bf.ip_nd_src_unk_cmd; - return ret; -} - -sw_error_t -hppe_l3_vp_port_tbl_ip_nd_src_unk_cmd_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - union l3_vp_port_tbl_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_l3_vp_port_tbl_get(dev_id, index, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.ip_nd_src_unk_cmd = value; - ret = hppe_l3_vp_port_tbl_set(dev_id, index, ®_val); - return ret; -} - -sw_error_t -hppe_l3_vp_port_tbl_ipv4_sg_en_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union l3_vp_port_tbl_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_l3_vp_port_tbl_get(dev_id, index, ®_val); - *value = reg_val.bf.ipv4_sg_en; - return ret; -} - -sw_error_t -hppe_l3_vp_port_tbl_ipv4_sg_en_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - union l3_vp_port_tbl_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_l3_vp_port_tbl_get(dev_id, index, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.ipv4_sg_en = value; - ret = hppe_l3_vp_port_tbl_set(dev_id, index, ®_val); - return ret; -} - -sw_error_t -hppe_l3_vp_port_tbl_ipv6_sg_cvlan_en_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union l3_vp_port_tbl_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_l3_vp_port_tbl_get(dev_id, index, ®_val); - *value = reg_val.bf.ipv6_sg_cvlan_en; - return ret; -} - -sw_error_t -hppe_l3_vp_port_tbl_ipv6_sg_cvlan_en_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - union l3_vp_port_tbl_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_l3_vp_port_tbl_get(dev_id, index, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.ipv6_sg_cvlan_en = value; - ret = hppe_l3_vp_port_tbl_set(dev_id, index, ®_val); - return ret; -} - -sw_error_t -hppe_in_l3_if_tbl_ttl_dec_bypass_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union in_l3_if_tbl_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_in_l3_if_tbl_get(dev_id, index, ®_val); - *value = reg_val.bf.ttl_dec_bypass; - return ret; -} - -sw_error_t -hppe_in_l3_if_tbl_ttl_dec_bypass_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - union in_l3_if_tbl_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_in_l3_if_tbl_get(dev_id, index, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.ttl_dec_bypass = value; - ret = hppe_in_l3_if_tbl_set(dev_id, index, ®_val); - return ret; -} - -sw_error_t -hppe_in_l3_if_tbl_ttl_exceed_cmd_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union in_l3_if_tbl_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_in_l3_if_tbl_get(dev_id, index, ®_val); - *value = reg_val.bf.ttl_exceed_cmd; - return ret; -} - -sw_error_t -hppe_in_l3_if_tbl_ttl_exceed_cmd_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - union in_l3_if_tbl_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_in_l3_if_tbl_get(dev_id, index, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.ttl_exceed_cmd = value; - ret = hppe_in_l3_if_tbl_set(dev_id, index, ®_val); - return ret; -} - -sw_error_t -hppe_in_l3_if_tbl_mru_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union in_l3_if_tbl_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_in_l3_if_tbl_get(dev_id, index, ®_val); - *value = reg_val.bf.mru; - return ret; -} - -sw_error_t -hppe_in_l3_if_tbl_mru_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - union in_l3_if_tbl_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_in_l3_if_tbl_get(dev_id, index, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.mru = value; - ret = hppe_in_l3_if_tbl_set(dev_id, index, ®_val); - return ret; -} - -sw_error_t -hppe_in_l3_if_tbl_ipv4_uc_route_en_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union in_l3_if_tbl_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_in_l3_if_tbl_get(dev_id, index, ®_val); - *value = reg_val.bf.ipv4_uc_route_en; - return ret; -} - -sw_error_t -hppe_in_l3_if_tbl_ipv4_uc_route_en_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - union in_l3_if_tbl_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_in_l3_if_tbl_get(dev_id, index, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.ipv4_uc_route_en = value; - ret = hppe_in_l3_if_tbl_set(dev_id, index, ®_val); - return ret; -} - -sw_error_t -hppe_in_l3_if_tbl_ipv6_uc_route_en_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union in_l3_if_tbl_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_in_l3_if_tbl_get(dev_id, index, ®_val); - *value = reg_val.bf.ipv6_uc_route_en; - return ret; -} - -sw_error_t -hppe_in_l3_if_tbl_ipv6_uc_route_en_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - union in_l3_if_tbl_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_in_l3_if_tbl_get(dev_id, index, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.ipv6_uc_route_en = value; - ret = hppe_in_l3_if_tbl_set(dev_id, index, ®_val); - return ret; -} - -sw_error_t -hppe_in_l3_if_tbl_ttl_exceed_de_acce_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union in_l3_if_tbl_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_in_l3_if_tbl_get(dev_id, index, ®_val); - *value = reg_val.bf.ttl_exceed_de_acce; - return ret; -} - -sw_error_t -hppe_in_l3_if_tbl_ttl_exceed_de_acce_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - union in_l3_if_tbl_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_in_l3_if_tbl_get(dev_id, index, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.ttl_exceed_de_acce = value; - ret = hppe_in_l3_if_tbl_set(dev_id, index, ®_val); - return ret; -} - -sw_error_t -hppe_in_l3_if_tbl_icmp_trigger_en_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union in_l3_if_tbl_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_in_l3_if_tbl_get(dev_id, index, ®_val); - *value = reg_val.bf.icmp_trigger_en; - return ret; -} - -sw_error_t -hppe_in_l3_if_tbl_icmp_trigger_en_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - union in_l3_if_tbl_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_in_l3_if_tbl_get(dev_id, index, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.icmp_trigger_en = value; - ret = hppe_in_l3_if_tbl_set(dev_id, index, ®_val); - return ret; -} - -sw_error_t -hppe_in_l3_if_tbl_mac_bitmap_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union in_l3_if_tbl_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_in_l3_if_tbl_get(dev_id, index, ®_val); - *value = reg_val.bf.mac_bitmap; - return ret; -} - -sw_error_t -hppe_in_l3_if_tbl_mac_bitmap_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - union in_l3_if_tbl_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_in_l3_if_tbl_get(dev_id, index, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.mac_bitmap = value; - ret = hppe_in_l3_if_tbl_set(dev_id, index, ®_val); - return ret; -} - -sw_error_t -hppe_in_l3_if_tbl_pppoe_en_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union in_l3_if_tbl_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_in_l3_if_tbl_get(dev_id, index, ®_val); - *value = reg_val.bf.pppoe_en; - return ret; -} - -sw_error_t -hppe_in_l3_if_tbl_pppoe_en_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - union in_l3_if_tbl_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_in_l3_if_tbl_get(dev_id, index, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.pppoe_en = value; - ret = hppe_in_l3_if_tbl_set(dev_id, index, ®_val); - return ret; -} - -sw_error_t -hppe_in_l3_if_tbl_mtu_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union in_l3_if_tbl_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_in_l3_if_tbl_get(dev_id, index, ®_val); - *value = reg_val.bf.mtu; - return ret; -} - -sw_error_t -hppe_in_l3_if_tbl_mtu_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - union in_l3_if_tbl_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_in_l3_if_tbl_get(dev_id, index, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.mtu = value; - ret = hppe_in_l3_if_tbl_set(dev_id, index, ®_val); - return ret; -} - -sw_error_t -hppe_in_nexthop_tbl_ip_pub_addr_index_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union in_nexthop_tbl_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_in_nexthop_tbl_get(dev_id, index, ®_val); - *value = reg_val.bf1.ip_pub_addr_index; - return ret; -} - -sw_error_t -hppe_in_nexthop_tbl_ip_pub_addr_index_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - union in_nexthop_tbl_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_in_nexthop_tbl_get(dev_id, index, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf1.ip_pub_addr_index = value; - ret = hppe_in_nexthop_tbl_set(dev_id, index, ®_val); - return ret; -} - -sw_error_t -hppe_in_nexthop_tbl_cvid_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union in_nexthop_tbl_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_in_nexthop_tbl_get(dev_id, index, ®_val); - *value = reg_val.bf1.cvid; - return ret; -} - -sw_error_t -hppe_in_nexthop_tbl_cvid_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - union in_nexthop_tbl_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_in_nexthop_tbl_get(dev_id, index, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf1.cvid = value; - ret = hppe_in_nexthop_tbl_set(dev_id, index, ®_val); - return ret; -} - -sw_error_t -hppe_in_nexthop_tbl_post_l3_if_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union in_nexthop_tbl_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_in_nexthop_tbl_get(dev_id, index, ®_val); - *value = reg_val.bf1.post_l3_if; - return ret; -} - -sw_error_t -hppe_in_nexthop_tbl_post_l3_if_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - union in_nexthop_tbl_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_in_nexthop_tbl_get(dev_id, index, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf1.post_l3_if = value; - ret = hppe_in_nexthop_tbl_set(dev_id, index, ®_val); - return ret; -} - -sw_error_t -hppe_in_nexthop_tbl_mac_addr_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint64_t *value) -{ - union in_nexthop_tbl_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_in_nexthop_tbl_get(dev_id, index, ®_val); - *value = (a_uint64_t)reg_val.bf1.mac_addr_1 << 16 | \ - reg_val.bf1.mac_addr_0; - return ret; -} - -sw_error_t -hppe_in_nexthop_tbl_mac_addr_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint64_t value) -{ - union in_nexthop_tbl_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_in_nexthop_tbl_get(dev_id, index, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf1.mac_addr_1 = value >> 16; - reg_val.bf1.mac_addr_0 = value & (((a_uint64_t)1<<16)-1); - ret = hppe_in_nexthop_tbl_set(dev_id, index, ®_val); - return ret; -} - -sw_error_t -hppe_in_nexthop_tbl_port_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union in_nexthop_tbl_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_in_nexthop_tbl_get(dev_id, index, ®_val); - *value = reg_val.bf0.port; - return ret; -} - -sw_error_t -hppe_in_nexthop_tbl_port_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - union in_nexthop_tbl_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_in_nexthop_tbl_get(dev_id, index, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf0.port = value; - ret = hppe_in_nexthop_tbl_set(dev_id, index, ®_val); - return ret; -} - -sw_error_t -hppe_in_nexthop_tbl_ip_to_me_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union in_nexthop_tbl_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_in_nexthop_tbl_get(dev_id, index, ®_val); - *value = reg_val.bf1.ip_to_me; - return ret; -} - -sw_error_t -hppe_in_nexthop_tbl_ip_to_me_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - union in_nexthop_tbl_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_in_nexthop_tbl_get(dev_id, index, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf1.ip_to_me = value; - ret = hppe_in_nexthop_tbl_set(dev_id, index, ®_val); - return ret; -} - -sw_error_t -hppe_in_nexthop_tbl_ip_addr_dnat_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union in_nexthop_tbl_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_in_nexthop_tbl_get(dev_id, index, ®_val); - *value = reg_val.bf1.ip_addr_dnat; - return ret; -} - -sw_error_t -hppe_in_nexthop_tbl_ip_addr_dnat_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - union in_nexthop_tbl_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_in_nexthop_tbl_get(dev_id, index, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf1.ip_addr_dnat = value; - ret = hppe_in_nexthop_tbl_set(dev_id, index, ®_val); - return ret; -} - -sw_error_t -hppe_in_nexthop_tbl_type_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union in_nexthop_tbl_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_in_nexthop_tbl_get(dev_id, index, ®_val); - *value = reg_val.bf1.type; - return ret; -} - -sw_error_t -hppe_in_nexthop_tbl_type_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - union in_nexthop_tbl_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_in_nexthop_tbl_get(dev_id, index, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf1.type = value; - ret = hppe_in_nexthop_tbl_set(dev_id, index, ®_val); - return ret; -} - -sw_error_t -hppe_in_nexthop_tbl_stag_fmt_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union in_nexthop_tbl_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_in_nexthop_tbl_get(dev_id, index, ®_val); - *value = reg_val.bf1.stag_fmt; - return ret; -} - -sw_error_t -hppe_in_nexthop_tbl_stag_fmt_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - union in_nexthop_tbl_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_in_nexthop_tbl_get(dev_id, index, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf1.stag_fmt = value; - ret = hppe_in_nexthop_tbl_set(dev_id, index, ®_val); - return ret; -} - -sw_error_t -hppe_in_nexthop_tbl_vsi_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union in_nexthop_tbl_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_in_nexthop_tbl_get(dev_id, index, ®_val); - *value = reg_val.bf1.vsi; - return ret; -} - -sw_error_t -hppe_in_nexthop_tbl_vsi_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - union in_nexthop_tbl_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_in_nexthop_tbl_get(dev_id, index, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf1.vsi = value; - ret = hppe_in_nexthop_tbl_set(dev_id, index, ®_val); - return ret; -} - -sw_error_t -hppe_in_nexthop_tbl_svid_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union in_nexthop_tbl_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_in_nexthop_tbl_get(dev_id, index, ®_val); - *value = reg_val.bf1.svid; - return ret; -} - -sw_error_t -hppe_in_nexthop_tbl_svid_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - union in_nexthop_tbl_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_in_nexthop_tbl_get(dev_id, index, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf1.svid = value; - ret = hppe_in_nexthop_tbl_set(dev_id, index, ®_val); - return ret; -} - -sw_error_t -hppe_in_nexthop_tbl_ctag_fmt_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union in_nexthop_tbl_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_in_nexthop_tbl_get(dev_id, index, ®_val); - *value = reg_val.bf1.ctag_fmt; - return ret; -} - -sw_error_t -hppe_in_nexthop_tbl_ctag_fmt_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - union in_nexthop_tbl_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_in_nexthop_tbl_get(dev_id, index, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf1.ctag_fmt = value; - ret = hppe_in_nexthop_tbl_set(dev_id, index, ®_val); - return ret; -} - -sw_error_t -hppe_eg_l3_if_tbl_session_id_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union eg_l3_if_tbl_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_eg_l3_if_tbl_get(dev_id, index, ®_val); - *value = reg_val.bf.session_id; - return ret; -} - -sw_error_t -hppe_eg_l3_if_tbl_session_id_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - union eg_l3_if_tbl_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_eg_l3_if_tbl_get(dev_id, index, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.session_id = value; - ret = hppe_eg_l3_if_tbl_set(dev_id, index, ®_val); - return ret; -} - -sw_error_t -hppe_eg_l3_if_tbl_mac_addr_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint64_t *value) -{ - union eg_l3_if_tbl_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_eg_l3_if_tbl_get(dev_id, index, ®_val); - *value = (a_uint64_t)reg_val.bf.mac_addr_1 << 32 | \ - reg_val.bf.mac_addr_0; - return ret; -} - -sw_error_t -hppe_eg_l3_if_tbl_mac_addr_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint64_t value) -{ - union eg_l3_if_tbl_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_eg_l3_if_tbl_get(dev_id, index, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.mac_addr_1 = value >> 32; - reg_val.bf.mac_addr_0 = value & (((a_uint64_t)1<<32)-1); - ret = hppe_eg_l3_if_tbl_set(dev_id, index, ®_val); - return ret; -} - -sw_error_t -hppe_eg_l3_if_tbl_pppoe_en_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union eg_l3_if_tbl_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_eg_l3_if_tbl_get(dev_id, index, ®_val); - *value = reg_val.bf.pppoe_en; - return ret; -} - -sw_error_t -hppe_eg_l3_if_tbl_pppoe_en_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - union eg_l3_if_tbl_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_eg_l3_if_tbl_get(dev_id, index, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.pppoe_en = value; - ret = hppe_eg_l3_if_tbl_set(dev_id, index, ®_val); - return ret; -} - -sw_error_t -hppe_in_pub_ip_addr_tbl_ip_addr_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union in_pub_ip_addr_tbl_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_in_pub_ip_addr_tbl_get(dev_id, index, ®_val); - *value = reg_val.bf.ip_addr; - return ret; -} - -sw_error_t -hppe_in_pub_ip_addr_tbl_ip_addr_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - union in_pub_ip_addr_tbl_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_in_pub_ip_addr_tbl_get(dev_id, index, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.ip_addr = value; - ret = hppe_in_pub_ip_addr_tbl_set(dev_id, index, ®_val); - return ret; -} - -sw_error_t -hppe_rt_interface_cnt_tbl_byte_cnt_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint64_t *value) -{ - union rt_interface_cnt_tbl_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_rt_interface_cnt_tbl_get(dev_id, index, ®_val); - *value = (a_uint64_t)reg_val.bf.byte_cnt_1 << 32 | \ - reg_val.bf.byte_cnt_0; - return ret; -} - -sw_error_t -hppe_rt_interface_cnt_tbl_byte_cnt_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint64_t value) -{ - union rt_interface_cnt_tbl_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_rt_interface_cnt_tbl_get(dev_id, index, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.byte_cnt_1 = value >> 32; - reg_val.bf.byte_cnt_0 = value & (((a_uint64_t)1<<32)-1); - ret = hppe_rt_interface_cnt_tbl_set(dev_id, index, ®_val); - return ret; -} - -sw_error_t -hppe_rt_interface_cnt_tbl_pkt_cnt_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union rt_interface_cnt_tbl_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_rt_interface_cnt_tbl_get(dev_id, index, ®_val); - *value = reg_val.bf.pkt_cnt; - return ret; -} - -sw_error_t -hppe_rt_interface_cnt_tbl_pkt_cnt_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - union rt_interface_cnt_tbl_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_rt_interface_cnt_tbl_get(dev_id, index, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.pkt_cnt = value; - ret = hppe_rt_interface_cnt_tbl_set(dev_id, index, ®_val); - return ret; -} - -sw_error_t -hppe_rt_interface_cnt_tbl_drop_byte_cnt_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint64_t *value) -{ - union rt_interface_cnt_tbl_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_rt_interface_cnt_tbl_get(dev_id, index, ®_val); - *value = (a_uint64_t)reg_val.bf.drop_byte_cnt_1 << 24 | \ - reg_val.bf.drop_byte_cnt_0; - return ret; -} - -sw_error_t -hppe_rt_interface_cnt_tbl_drop_byte_cnt_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint64_t value) -{ - union rt_interface_cnt_tbl_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_rt_interface_cnt_tbl_get(dev_id, index, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.drop_byte_cnt_1 = value >> 24; - reg_val.bf.drop_byte_cnt_0 = value & (((a_uint64_t)1<<24)-1); - ret = hppe_rt_interface_cnt_tbl_set(dev_id, index, ®_val); - return ret; -} - -sw_error_t -hppe_rt_interface_cnt_tbl_drop_pkt_cnt_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union rt_interface_cnt_tbl_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_rt_interface_cnt_tbl_get(dev_id, index, ®_val); - *value = reg_val.bf.drop_pkt_cnt_1 << 24 | \ - reg_val.bf.drop_pkt_cnt_0; - return ret; -} - -sw_error_t -hppe_rt_interface_cnt_tbl_drop_pkt_cnt_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - union rt_interface_cnt_tbl_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_rt_interface_cnt_tbl_get(dev_id, index, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.drop_pkt_cnt_1 = value >> 24; - reg_val.bf.drop_pkt_cnt_0 = value & (((a_uint64_t)1<<24)-1); - ret = hppe_rt_interface_cnt_tbl_set(dev_id, index, ®_val); - return ret; -} - - -sw_error_t -hppe_host_op_common( - a_uint32_t dev_id, - a_uint32_t op_type, - a_uint32_t op_mode, - a_uint32_t *index) -{ - union host_tbl_op_u op; - union host_tbl_op_rslt_u result; - a_uint32_t i = 0x100; - sw_error_t rv; - - op.bf.cmd_id = host_cmd_id; - host_cmd_id++; - op.bf.byp_rslt_en = 0; - op.bf.op_type = op_type; - op.bf.hash_block_bitmap = 3; - op.bf.op_mode = op_mode; - op.bf.entry_index = *index; - - rv = hppe_host_tbl_op_set(dev_id, &op); - if (SW_OK != rv) - return rv; - rv = hppe_host_tbl_op_rslt_get(dev_id, &result); - if (SW_OK != rv) - return rv; - while (!result.bf.valid_cnt && --i) { - hppe_host_tbl_op_rslt_get(dev_id, &result); - } - if (i == 0) - return SW_BUSY; - if (result.bf.op_rslt == 0) { - *index = result.bf.entry_index; - return SW_OK; - } - else - return SW_FAIL; - -} - -sw_error_t -hppe_host_ipv4_add( - a_uint32_t dev_id, a_uint32_t op_mode, - a_uint32_t *index, union host_tbl_u *entry) -{ - hppe_host_tbl_op_data0_set(dev_id, (union host_tbl_op_data0_u *)(&entry->val[0])); - hppe_host_tbl_op_data1_set(dev_id, (union host_tbl_op_data1_u *)(&entry->val[1])); - hppe_host_tbl_op_data2_set(dev_id, (union host_tbl_op_data2_u *)(&entry->val[2])); - return hppe_host_op_common(dev_id, 0, op_mode, index); -} - -sw_error_t -hppe_host_ipv6_add( - a_uint32_t dev_id, a_uint32_t op_mode, - a_uint32_t *index, union host_ipv6_tbl_u *entry) -{ - hppe_host_tbl_op_data0_set(dev_id, (union host_tbl_op_data0_u *)(&entry->val[0])); - hppe_host_tbl_op_data1_set(dev_id, (union host_tbl_op_data1_u *)(&entry->val[1])); - hppe_host_tbl_op_data2_set(dev_id, (union host_tbl_op_data2_u *)(&entry->val[2])); - hppe_host_tbl_op_data3_set(dev_id, (union host_tbl_op_data3_u *)(&entry->val[3])); - hppe_host_tbl_op_data4_set(dev_id, (union host_tbl_op_data4_u *)(&entry->val[4])); - return hppe_host_op_common(dev_id, 0, op_mode, index); -} - -sw_error_t -hppe_host_ipv4_mcast_add( - a_uint32_t dev_id, a_uint32_t op_mode, - a_uint32_t *index, union host_ipv4_mcast_tbl_u *entry) -{ - hppe_host_tbl_op_data0_set(dev_id, (union host_tbl_op_data0_u *)(&entry->val[0])); - hppe_host_tbl_op_data1_set(dev_id, (union host_tbl_op_data1_u *)(&entry->val[1])); - hppe_host_tbl_op_data2_set(dev_id, (union host_tbl_op_data2_u *)(&entry->val[2])); - hppe_host_tbl_op_data3_set(dev_id, (union host_tbl_op_data3_u *)(&entry->val[3])); - hppe_host_tbl_op_data4_set(dev_id, (union host_tbl_op_data4_u *)(&entry->val[4])); - return hppe_host_op_common(dev_id, 0, op_mode, index); -} - -sw_error_t -hppe_host_ipv6_mcast_add( - a_uint32_t dev_id, a_uint32_t op_mode, - a_uint32_t *index, union host_ipv6_mcast_tbl_u *entry) -{ - hppe_host_tbl_op_data0_set(dev_id, (union host_tbl_op_data0_u *)(&entry->val[0])); - hppe_host_tbl_op_data1_set(dev_id, (union host_tbl_op_data1_u *)(&entry->val[1])); - hppe_host_tbl_op_data2_set(dev_id, (union host_tbl_op_data2_u *)(&entry->val[2])); - hppe_host_tbl_op_data3_set(dev_id, (union host_tbl_op_data3_u *)(&entry->val[3])); - hppe_host_tbl_op_data4_set(dev_id, (union host_tbl_op_data4_u *)(&entry->val[4])); - hppe_host_tbl_op_data5_set(dev_id, (union host_tbl_op_data5_u *)(&entry->val[5])); - hppe_host_tbl_op_data6_set(dev_id, (union host_tbl_op_data6_u *)(&entry->val[6])); - hppe_host_tbl_op_data7_set(dev_id, (union host_tbl_op_data7_u *)(&entry->val[7])); - hppe_host_tbl_op_data8_set(dev_id, (union host_tbl_op_data8_u *)(&entry->val[8])); - hppe_host_tbl_op_data9_set(dev_id, (union host_tbl_op_data9_u *)(&entry->val[9])); - return hppe_host_op_common(dev_id, 0, op_mode, index); -} - -sw_error_t -hppe_host_ipv4_del( - a_uint32_t dev_id, a_uint32_t op_mode, - a_uint32_t *index, union host_tbl_u *entry) -{ - if (op_mode == 0) { - hppe_host_tbl_op_data0_set(dev_id, (union host_tbl_op_data0_u *)(&entry->val[0])); - hppe_host_tbl_op_data1_set(dev_id, (union host_tbl_op_data1_u *)(&entry->val[1])); - hppe_host_tbl_op_data2_set(dev_id, (union host_tbl_op_data2_u *)(&entry->val[2])); - } - return hppe_host_op_common(dev_id, 1, op_mode, index); - -} - -sw_error_t -hppe_host_ipv6_del( - a_uint32_t dev_id, a_uint32_t op_mode, - a_uint32_t *index, union host_ipv6_tbl_u *entry) -{ - if (op_mode == 0) { - hppe_host_tbl_op_data0_set(dev_id, (union host_tbl_op_data0_u *)(&entry->val[0])); - hppe_host_tbl_op_data1_set(dev_id, (union host_tbl_op_data1_u *)(&entry->val[1])); - hppe_host_tbl_op_data2_set(dev_id, (union host_tbl_op_data2_u *)(&entry->val[2])); - hppe_host_tbl_op_data3_set(dev_id, (union host_tbl_op_data3_u *)(&entry->val[3])); - hppe_host_tbl_op_data4_set(dev_id, (union host_tbl_op_data4_u *)(&entry->val[4])); - } - return hppe_host_op_common(dev_id, 1, op_mode, index); -} - -sw_error_t -hppe_host_ipv4_mcast_del( - a_uint32_t dev_id, a_uint32_t op_mode, - a_uint32_t *index, union host_ipv4_mcast_tbl_u *entry) -{ - if (op_mode == 0) { - hppe_host_tbl_op_data0_set(dev_id, (union host_tbl_op_data0_u *)(&entry->val[0])); - hppe_host_tbl_op_data1_set(dev_id, (union host_tbl_op_data1_u *)(&entry->val[1])); - hppe_host_tbl_op_data2_set(dev_id, (union host_tbl_op_data2_u *)(&entry->val[2])); - hppe_host_tbl_op_data3_set(dev_id, (union host_tbl_op_data3_u *)(&entry->val[3])); - hppe_host_tbl_op_data4_set(dev_id, (union host_tbl_op_data4_u *)(&entry->val[4])); - } - return hppe_host_op_common(dev_id, 1, op_mode, index); -} - -sw_error_t -hppe_host_ipv6_mcast_del( - a_uint32_t dev_id, a_uint32_t op_mode, - a_uint32_t *index, union host_ipv6_mcast_tbl_u *entry) -{ - if (op_mode == 0) { - hppe_host_tbl_op_data0_set(dev_id, (union host_tbl_op_data0_u *)(&entry->val[0])); - hppe_host_tbl_op_data1_set(dev_id, (union host_tbl_op_data1_u *)(&entry->val[1])); - hppe_host_tbl_op_data2_set(dev_id, (union host_tbl_op_data2_u *)(&entry->val[2])); - hppe_host_tbl_op_data3_set(dev_id, (union host_tbl_op_data3_u *)(&entry->val[3])); - hppe_host_tbl_op_data4_set(dev_id, (union host_tbl_op_data4_u *)(&entry->val[4])); - hppe_host_tbl_op_data5_set(dev_id, (union host_tbl_op_data5_u *)(&entry->val[5])); - hppe_host_tbl_op_data6_set(dev_id, (union host_tbl_op_data6_u *)(&entry->val[6])); - hppe_host_tbl_op_data7_set(dev_id, (union host_tbl_op_data7_u *)(&entry->val[7])); - hppe_host_tbl_op_data8_set(dev_id, (union host_tbl_op_data8_u *)(&entry->val[8])); - hppe_host_tbl_op_data9_set(dev_id, (union host_tbl_op_data9_u *)(&entry->val[9])); - } - return hppe_host_op_common(dev_id, 1, op_mode, index); -} - -sw_error_t -hppe_host_get_common( - a_uint32_t dev_id, - a_uint32_t op_mode, - a_uint32_t *index, - a_uint32_t *data, - a_uint32_t num) -{ - union host_tbl_rd_op_u op; - union host_tbl_rd_op_rslt_u result; - a_uint32_t i = 0x100; - sw_error_t rv; - - op.bf.cmd_id = host_cmd_id; - host_cmd_id++; - op.bf.byp_rslt_en = 0; - op.bf.op_type = 2; - op.bf.hash_block_bitmap = 3; - op.bf.op_mode = op_mode; - op.bf.entry_index = *index; - - rv = hppe_host_tbl_rd_op_set(dev_id, &op); - if (SW_OK != rv) - return rv; - rv = hppe_host_tbl_rd_op_rslt_get(dev_id, &result); - if (SW_OK != rv) - return rv; - while (!result.bf.valid_cnt && --i) { - hppe_host_tbl_rd_op_rslt_get(dev_id, &result); - } - if (i == 0) - return SW_BUSY; - if (result.bf.op_rslt == 0) { - hppe_reg_tbl_get( - dev_id, - IPE_L3_BASE_ADDR + HOST_TBL_RD_RSLT_DATA0_ADDRESS, - data, num); - *index = result.bf.entry_index; - return SW_OK; - } - else - return SW_FAIL; - -} - - -sw_error_t -hppe_host_ipv4_get( - a_uint32_t dev_id, a_uint32_t op_mode, - a_uint32_t *index, union host_tbl_u *entry) -{ - if (op_mode == 0) { - hppe_host_tbl_rd_op_data0_set(dev_id, (union host_tbl_rd_op_data0_u *)(&entry->val[0])); - hppe_host_tbl_rd_op_data1_set(dev_id, (union host_tbl_rd_op_data1_u *)(&entry->val[1])); - hppe_host_tbl_rd_op_data2_set(dev_id, (union host_tbl_rd_op_data2_u *)(&entry->val[2])); - } - return hppe_host_get_common(dev_id, op_mode, index, - (a_uint32_t *)entry, 3); - -} - -sw_error_t -hppe_host_ipv6_get( - a_uint32_t dev_id, a_uint32_t op_mode, - a_uint32_t *index, union host_ipv6_tbl_u *entry) -{ - if (op_mode == 0) { - hppe_host_tbl_rd_op_data0_set(dev_id, (union host_tbl_rd_op_data0_u *)(&entry->val[0])); - hppe_host_tbl_rd_op_data1_set(dev_id, (union host_tbl_rd_op_data1_u *)(&entry->val[1])); - hppe_host_tbl_rd_op_data2_set(dev_id, (union host_tbl_rd_op_data2_u *)(&entry->val[2])); - hppe_host_tbl_rd_op_data3_set(dev_id, (union host_tbl_rd_op_data3_u *)(&entry->val[3])); - hppe_host_tbl_rd_op_data4_set(dev_id, (union host_tbl_rd_op_data4_u *)(&entry->val[4])); - } - return hppe_host_get_common(dev_id, op_mode, index, - (a_uint32_t *)entry, 5); -} - -sw_error_t -hppe_host_ipv4_mcast_get( - a_uint32_t dev_id, a_uint32_t op_mode, - a_uint32_t *index, union host_ipv4_mcast_tbl_u *entry) -{ - if (op_mode == 0) { - hppe_host_tbl_rd_op_data0_set(dev_id, (union host_tbl_rd_op_data0_u *)(&entry->val[0])); - hppe_host_tbl_rd_op_data1_set(dev_id, (union host_tbl_rd_op_data1_u *)(&entry->val[1])); - hppe_host_tbl_rd_op_data2_set(dev_id, (union host_tbl_rd_op_data2_u *)(&entry->val[2])); - hppe_host_tbl_rd_op_data3_set(dev_id, (union host_tbl_rd_op_data3_u *)(&entry->val[3])); - hppe_host_tbl_rd_op_data4_set(dev_id, (union host_tbl_rd_op_data4_u *)(&entry->val[4])); - } - return hppe_host_get_common(dev_id, op_mode, index, - (a_uint32_t *)entry, 5); -} - -sw_error_t -hppe_host_ipv6_mcast_get( - a_uint32_t dev_id, a_uint32_t op_mode, - a_uint32_t *index, union host_ipv6_mcast_tbl_u *entry) -{ - if (op_mode == 0) { - hppe_host_tbl_rd_op_data0_set(dev_id, (union host_tbl_rd_op_data0_u *)(&entry->val[0])); - hppe_host_tbl_rd_op_data1_set(dev_id, (union host_tbl_rd_op_data1_u *)(&entry->val[1])); - hppe_host_tbl_rd_op_data2_set(dev_id, (union host_tbl_rd_op_data2_u *)(&entry->val[2])); - hppe_host_tbl_rd_op_data3_set(dev_id, (union host_tbl_rd_op_data3_u *)(&entry->val[3])); - hppe_host_tbl_rd_op_data4_set(dev_id, (union host_tbl_rd_op_data4_u *)(&entry->val[4])); - hppe_host_tbl_rd_op_data5_set(dev_id, (union host_tbl_rd_op_data5_u *)(&entry->val[5])); - hppe_host_tbl_rd_op_data6_set(dev_id, (union host_tbl_rd_op_data6_u *)(&entry->val[6])); - hppe_host_tbl_rd_op_data7_set(dev_id, (union host_tbl_rd_op_data7_u *)(&entry->val[7])); - hppe_host_tbl_rd_op_data8_set(dev_id, (union host_tbl_rd_op_data8_u *)(&entry->val[8])); - hppe_host_tbl_rd_op_data9_set(dev_id, (union host_tbl_rd_op_data9_u *)(&entry->val[9])); - } - return hppe_host_get_common(dev_id, op_mode, index, - (a_uint32_t *)entry, 10); -} - -sw_error_t -hppe_host_flush_common(a_uint32_t dev_id) -{ - union host_tbl_op_u op; - union host_tbl_op_rslt_u result; - a_uint32_t i = 0x100 * 50; - sw_error_t rv; - - op.bf.cmd_id = host_cmd_id; - host_cmd_id++; - op.bf.byp_rslt_en = 0; - op.bf.op_type = 3; - op.bf.hash_block_bitmap = 3; - op.bf.op_mode = 0; - - rv = hppe_host_tbl_op_set(dev_id, &op); - if (SW_OK != rv) - return rv; - rv = hppe_host_tbl_op_rslt_get(dev_id, &result); - if (SW_OK != rv) - return rv; - while (!result.bf.valid_cnt && --i) { - hppe_host_tbl_op_rslt_get(dev_id, &result); - } - if (i == 0) - return SW_BUSY; - if (result.bf.op_rslt == 0) - return SW_OK; - else - return SW_FAIL; - - -} -#endif diff --git a/feeds/ipq807x/qca-ssdk/src/src/hsl/hppe/hppe_mib.c b/feeds/ipq807x/qca-ssdk/src/src/hsl/hppe/hppe_mib.c deleted file mode 100755 index 34c66db6d..000000000 --- a/feeds/ipq807x/qca-ssdk/src/src/hsl/hppe/hppe_mib.c +++ /dev/null @@ -1,2167 +0,0 @@ -/* - * Copyright (c) 2016-2017, The Linux Foundation. All rights reserved. - * Permission to use, copy, modify, and/or distribute this software for - * any purpose with or without fee is hereby granted, provided that the - * above copyright notice and this permission notice appear in all copies. - * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES - * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR - * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES - * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN - * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT - * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. - */ - - -/** - * @defgroup - * @{ - */ -#include "sw.h" -#include "hsl.h" -#include "hppe_reg_access.h" -#include "hppe_mib_reg.h" -#include "hppe_mib.h" - -sw_error_t -hppe_mac_mib_ctrl_get( - a_uint32_t dev_id, - a_uint32_t index, - union mac_mib_ctrl_u *value) -{ - if (index >= MAC_MIB_CTRL_MAX_ENTRY) - return SW_OUT_OF_RANGE; - return hppe_reg_get( - dev_id, - NSS_MAC_CSR_BASE_ADDR + MAC_MIB_CTRL_ADDRESS + \ - index * MAC_MIB_CTRL_INC, - &value->val); -} - -sw_error_t -hppe_mac_mib_ctrl_set( - a_uint32_t dev_id, - a_uint32_t index, - union mac_mib_ctrl_u *value) -{ - return hppe_reg_set( - dev_id, - NSS_MAC_CSR_BASE_ADDR + MAC_MIB_CTRL_ADDRESS + \ - index * MAC_MIB_CTRL_INC, - value->val); -} - -sw_error_t -hppe_rxbroad_get( - a_uint32_t dev_id, - a_uint32_t index, - union rxbroad_u *value) -{ - if (index >= RXBROAD_MAX_ENTRY) - return SW_OUT_OF_RANGE; - return hppe_reg_get( - dev_id, - NSS_MAC_CSR_BASE_ADDR + RXBROAD_ADDRESS + \ - index * RXBROAD_INC, - &value->val); -} - -sw_error_t -hppe_rxbroad_set( - a_uint32_t dev_id, - a_uint32_t index, - union rxbroad_u *value) -{ - return SW_NOT_SUPPORTED; -} - -sw_error_t -hppe_rxpause_get( - a_uint32_t dev_id, - a_uint32_t index, - union rxpause_u *value) -{ - if (index >= RXPAUSE_MAX_ENTRY) - return SW_OUT_OF_RANGE; - return hppe_reg_get( - dev_id, - NSS_MAC_CSR_BASE_ADDR + RXPAUSE_ADDRESS + \ - index * RXPAUSE_INC, - &value->val); -} - -sw_error_t -hppe_rxpause_set( - a_uint32_t dev_id, - a_uint32_t index, - union rxpause_u *value) -{ - return SW_NOT_SUPPORTED; -} - -sw_error_t -hppe_rxmulti_get( - a_uint32_t dev_id, - a_uint32_t index, - union rxmulti_u *value) -{ - if (index >= RXMULTI_MAX_ENTRY) - return SW_OUT_OF_RANGE; - return hppe_reg_get( - dev_id, - NSS_MAC_CSR_BASE_ADDR + RXMULTI_ADDRESS + \ - index * RXMULTI_INC, - &value->val); -} - -sw_error_t -hppe_rxmulti_set( - a_uint32_t dev_id, - a_uint32_t index, - union rxmulti_u *value) -{ - return SW_NOT_SUPPORTED; -} - -sw_error_t -hppe_rxfcserr_get( - a_uint32_t dev_id, - a_uint32_t index, - union rxfcserr_u *value) -{ - if (index >= RXFCSERR_MAX_ENTRY) - return SW_OUT_OF_RANGE; - return hppe_reg_get( - dev_id, - NSS_MAC_CSR_BASE_ADDR + RXFCSERR_ADDRESS + \ - index * RXFCSERR_INC, - &value->val); -} - -sw_error_t -hppe_rxfcserr_set( - a_uint32_t dev_id, - a_uint32_t index, - union rxfcserr_u *value) -{ - return SW_NOT_SUPPORTED; -} - -sw_error_t -hppe_rxalignerr_get( - a_uint32_t dev_id, - a_uint32_t index, - union rxalignerr_u *value) -{ - if (index >= RXALIGNERR_MAX_ENTRY) - return SW_OUT_OF_RANGE; - return hppe_reg_get( - dev_id, - NSS_MAC_CSR_BASE_ADDR + RXALIGNERR_ADDRESS + \ - index * RXALIGNERR_INC, - &value->val); -} - -sw_error_t -hppe_rxalignerr_set( - a_uint32_t dev_id, - a_uint32_t index, - union rxalignerr_u *value) -{ - return SW_NOT_SUPPORTED; -} - -sw_error_t -hppe_rxrunt_get( - a_uint32_t dev_id, - a_uint32_t index, - union rxrunt_u *value) -{ - if (index >= RXRUNT_MAX_ENTRY) - return SW_OUT_OF_RANGE; - return hppe_reg_get( - dev_id, - NSS_MAC_CSR_BASE_ADDR + RXRUNT_ADDRESS + \ - index * RXRUNT_INC, - &value->val); -} - -sw_error_t -hppe_rxrunt_set( - a_uint32_t dev_id, - a_uint32_t index, - union rxrunt_u *value) -{ - return SW_NOT_SUPPORTED; -} - -sw_error_t -hppe_rxfrag_get( - a_uint32_t dev_id, - a_uint32_t index, - union rxfrag_u *value) -{ - if (index >= RXFRAG_MAX_ENTRY) - return SW_OUT_OF_RANGE; - return hppe_reg_get( - dev_id, - NSS_MAC_CSR_BASE_ADDR + RXFRAG_ADDRESS + \ - index * RXFRAG_INC, - &value->val); -} - -sw_error_t -hppe_rxfrag_set( - a_uint32_t dev_id, - a_uint32_t index, - union rxfrag_u *value) -{ - return SW_NOT_SUPPORTED; -} - -sw_error_t -hppe_rxjumbofcserr_get( - a_uint32_t dev_id, - a_uint32_t index, - union rxjumbofcserr_u *value) -{ - if (index >= RXJUMBOFCSERR_MAX_ENTRY) - return SW_OUT_OF_RANGE; - return hppe_reg_get( - dev_id, - NSS_MAC_CSR_BASE_ADDR + RXJUMBOFCSERR_ADDRESS + \ - index * RXJUMBOFCSERR_INC, - &value->val); -} - -sw_error_t -hppe_rxjumbofcserr_set( - a_uint32_t dev_id, - a_uint32_t index, - union rxjumbofcserr_u *value) -{ - return SW_NOT_SUPPORTED; -} - -sw_error_t -hppe_rxjumboalignerr_get( - a_uint32_t dev_id, - a_uint32_t index, - union rxjumboalignerr_u *value) -{ - if (index >= RXJUMBOALIGNERR_MAX_ENTRY) - return SW_OUT_OF_RANGE; - return hppe_reg_get( - dev_id, - NSS_MAC_CSR_BASE_ADDR + RXJUMBOALIGNERR_ADDRESS + \ - index * RXJUMBOALIGNERR_INC, - &value->val); -} - -sw_error_t -hppe_rxjumboalignerr_set( - a_uint32_t dev_id, - a_uint32_t index, - union rxjumboalignerr_u *value) -{ - return SW_NOT_SUPPORTED; -} - -sw_error_t -hppe_rxpkt64_get( - a_uint32_t dev_id, - a_uint32_t index, - union rxpkt64_u *value) -{ - if (index >= RXPKT64_MAX_ENTRY) - return SW_OUT_OF_RANGE; - return hppe_reg_get( - dev_id, - NSS_MAC_CSR_BASE_ADDR + RXPKT64_ADDRESS + \ - index * RXPKT64_INC, - &value->val); -} - -sw_error_t -hppe_rxpkt64_set( - a_uint32_t dev_id, - a_uint32_t index, - union rxpkt64_u *value) -{ - return SW_NOT_SUPPORTED; -} - -sw_error_t -hppe_rxpkt65to127_get( - a_uint32_t dev_id, - a_uint32_t index, - union rxpkt65to127_u *value) -{ - if (index >= RXPKT65TO127_MAX_ENTRY) - return SW_OUT_OF_RANGE; - return hppe_reg_get( - dev_id, - NSS_MAC_CSR_BASE_ADDR + RXPKT65TO127_ADDRESS + \ - index * RXPKT65TO127_INC, - &value->val); -} - -sw_error_t -hppe_rxpkt65to127_set( - a_uint32_t dev_id, - a_uint32_t index, - union rxpkt65to127_u *value) -{ - return SW_NOT_SUPPORTED; -} - -sw_error_t -hppe_rxpkt128to255_get( - a_uint32_t dev_id, - a_uint32_t index, - union rxpkt128to255_u *value) -{ - if (index >= RXPKT128TO255_MAX_ENTRY) - return SW_OUT_OF_RANGE; - return hppe_reg_get( - dev_id, - NSS_MAC_CSR_BASE_ADDR + RXPKT128TO255_ADDRESS + \ - index * RXPKT128TO255_INC, - &value->val); -} - -sw_error_t -hppe_rxpkt128to255_set( - a_uint32_t dev_id, - a_uint32_t index, - union rxpkt128to255_u *value) -{ - return SW_NOT_SUPPORTED; -} - -sw_error_t -hppe_rxpkt256to511_get( - a_uint32_t dev_id, - a_uint32_t index, - union rxpkt256to511_u *value) -{ - if (index >= RXPKT256TO511_MAX_ENTRY) - return SW_OUT_OF_RANGE; - return hppe_reg_get( - dev_id, - NSS_MAC_CSR_BASE_ADDR + RXPKT256TO511_ADDRESS + \ - index * RXPKT256TO511_INC, - &value->val); -} - -sw_error_t -hppe_rxpkt256to511_set( - a_uint32_t dev_id, - a_uint32_t index, - union rxpkt256to511_u *value) -{ - return SW_NOT_SUPPORTED; -} - -sw_error_t -hppe_rxpkt512to1023_get( - a_uint32_t dev_id, - a_uint32_t index, - union rxpkt512to1023_u *value) -{ - if (index >= RXPKT512TO1023_MAX_ENTRY) - return SW_OUT_OF_RANGE; - return hppe_reg_get( - dev_id, - NSS_MAC_CSR_BASE_ADDR + RXPKT512TO1023_ADDRESS + \ - index * RXPKT512TO1023_INC, - &value->val); -} - -sw_error_t -hppe_rxpkt512to1023_set( - a_uint32_t dev_id, - a_uint32_t index, - union rxpkt512to1023_u *value) -{ - return SW_NOT_SUPPORTED; -} - -sw_error_t -hppe_rxpkt1024to1518_get( - a_uint32_t dev_id, - a_uint32_t index, - union rxpkt1024to1518_u *value) -{ - if (index >= RXPKT1024TO1518_MAX_ENTRY) - return SW_OUT_OF_RANGE; - return hppe_reg_get( - dev_id, - NSS_MAC_CSR_BASE_ADDR + RXPKT1024TO1518_ADDRESS + \ - index * RXPKT1024TO1518_INC, - &value->val); -} - -sw_error_t -hppe_rxpkt1024to1518_set( - a_uint32_t dev_id, - a_uint32_t index, - union rxpkt1024to1518_u *value) -{ - return SW_NOT_SUPPORTED; -} - -sw_error_t -hppe_rxpkt1519tox_get( - a_uint32_t dev_id, - a_uint32_t index, - union rxpkt1519tox_u *value) -{ - if (index >= RXPKT1519TOX_MAX_ENTRY) - return SW_OUT_OF_RANGE; - return hppe_reg_get( - dev_id, - NSS_MAC_CSR_BASE_ADDR + RXPKT1519TOX_ADDRESS + \ - index * RXPKT1519TOX_INC, - &value->val); -} - -sw_error_t -hppe_rxpkt1519tox_set( - a_uint32_t dev_id, - a_uint32_t index, - union rxpkt1519tox_u *value) -{ - return SW_NOT_SUPPORTED; -} - -sw_error_t -hppe_rxtoolong_get( - a_uint32_t dev_id, - a_uint32_t index, - union rxtoolong_u *value) -{ - if (index >= RXTOOLONG_MAX_ENTRY) - return SW_OUT_OF_RANGE; - return hppe_reg_get( - dev_id, - NSS_MAC_CSR_BASE_ADDR + RXTOOLONG_ADDRESS + \ - index * RXTOOLONG_INC, - &value->val); -} - -sw_error_t -hppe_rxtoolong_set( - a_uint32_t dev_id, - a_uint32_t index, - union rxtoolong_u *value) -{ - return SW_NOT_SUPPORTED; -} - -sw_error_t -hppe_rxgoodbyte_l_get( - a_uint32_t dev_id, - a_uint32_t index, - union rxgoodbyte_l_u *value) -{ - if (index >= RXGOODBYTE_L_MAX_ENTRY) - return SW_OUT_OF_RANGE; - return hppe_reg_get( - dev_id, - NSS_MAC_CSR_BASE_ADDR + RXGOODBYTE_L_ADDRESS + \ - index * RXGOODBYTE_L_INC, - &value->val); -} - -sw_error_t -hppe_rxgoodbyte_l_set( - a_uint32_t dev_id, - a_uint32_t index, - union rxgoodbyte_l_u *value) -{ - return SW_NOT_SUPPORTED; -} - -sw_error_t -hppe_rxgoodbyte_h_get( - a_uint32_t dev_id, - a_uint32_t index, - union rxgoodbyte_h_u *value) -{ - if (index >= RXGOODBYTE_H_MAX_ENTRY) - return SW_OUT_OF_RANGE; - return hppe_reg_get( - dev_id, - NSS_MAC_CSR_BASE_ADDR + RXGOODBYTE_H_ADDRESS + \ - index * RXGOODBYTE_H_INC, - &value->val); -} - -sw_error_t -hppe_rxgoodbyte_h_set( - a_uint32_t dev_id, - a_uint32_t index, - union rxgoodbyte_h_u *value) -{ - return SW_NOT_SUPPORTED; -} - -sw_error_t -hppe_rxbadbyte_l_get( - a_uint32_t dev_id, - a_uint32_t index, - union rxbadbyte_l_u *value) -{ - if (index >= RXBADBYTE_L_MAX_ENTRY) - return SW_OUT_OF_RANGE; - return hppe_reg_get( - dev_id, - NSS_MAC_CSR_BASE_ADDR + RXBADBYTE_L_ADDRESS + \ - index * RXBADBYTE_L_INC, - &value->val); -} - -sw_error_t -hppe_rxbadbyte_l_set( - a_uint32_t dev_id, - a_uint32_t index, - union rxbadbyte_l_u *value) -{ - return SW_NOT_SUPPORTED; -} - -sw_error_t -hppe_rxbadbyte_h_get( - a_uint32_t dev_id, - a_uint32_t index, - union rxbadbyte_h_u *value) -{ - if (index >= RXBADBYTE_H_MAX_ENTRY) - return SW_OUT_OF_RANGE; - return hppe_reg_get( - dev_id, - NSS_MAC_CSR_BASE_ADDR + RXBADBYTE_H_ADDRESS + \ - index * RXBADBYTE_H_INC, - &value->val); -} - -sw_error_t -hppe_rxbadbyte_h_set( - a_uint32_t dev_id, - a_uint32_t index, - union rxbadbyte_h_u *value) -{ - return SW_NOT_SUPPORTED; -} - -sw_error_t -hppe_rxuni_get( - a_uint32_t dev_id, - a_uint32_t index, - union rxuni_u *value) -{ - if (index >= RXUNI_MAX_ENTRY) - return SW_OUT_OF_RANGE; - return hppe_reg_get( - dev_id, - NSS_MAC_CSR_BASE_ADDR + RXUNI_ADDRESS + \ - index * RXUNI_INC, - &value->val); -} - -sw_error_t -hppe_rxuni_set( - a_uint32_t dev_id, - a_uint32_t index, - union rxuni_u *value) -{ - return SW_NOT_SUPPORTED; -} - -sw_error_t -hppe_txbroad_get( - a_uint32_t dev_id, - a_uint32_t index, - union txbroad_u *value) -{ - if (index >= TXBROAD_MAX_ENTRY) - return SW_OUT_OF_RANGE; - return hppe_reg_get( - dev_id, - NSS_MAC_CSR_BASE_ADDR + TXBROAD_ADDRESS + \ - index * TXBROAD_INC, - &value->val); -} - -sw_error_t -hppe_txbroad_set( - a_uint32_t dev_id, - a_uint32_t index, - union txbroad_u *value) -{ - return SW_NOT_SUPPORTED; -} - -sw_error_t -hppe_txpause_get( - a_uint32_t dev_id, - a_uint32_t index, - union txpause_u *value) -{ - if (index >= TXPAUSE_MAX_ENTRY) - return SW_OUT_OF_RANGE; - return hppe_reg_get( - dev_id, - NSS_MAC_CSR_BASE_ADDR + TXPAUSE_ADDRESS + \ - index * TXPAUSE_INC, - &value->val); -} - -sw_error_t -hppe_txpause_set( - a_uint32_t dev_id, - a_uint32_t index, - union txpause_u *value) -{ - return SW_NOT_SUPPORTED; -} - -sw_error_t -hppe_txmulti_get( - a_uint32_t dev_id, - a_uint32_t index, - union txmulti_u *value) -{ - if (index >= TXMULTI_MAX_ENTRY) - return SW_OUT_OF_RANGE; - return hppe_reg_get( - dev_id, - NSS_MAC_CSR_BASE_ADDR + TXMULTI_ADDRESS + \ - index * TXMULTI_INC, - &value->val); -} - -sw_error_t -hppe_txmulti_set( - a_uint32_t dev_id, - a_uint32_t index, - union txmulti_u *value) -{ - return SW_NOT_SUPPORTED; -} - -sw_error_t -hppe_txunderrun_get( - a_uint32_t dev_id, - a_uint32_t index, - union txunderrun_u *value) -{ - if (index >= TXUNDERRUN_MAX_ENTRY) - return SW_OUT_OF_RANGE; - return hppe_reg_get( - dev_id, - NSS_MAC_CSR_BASE_ADDR + TXUNDERRUN_ADDRESS + \ - index * TXUNDERRUN_INC, - &value->val); -} - -sw_error_t -hppe_txunderrun_set( - a_uint32_t dev_id, - a_uint32_t index, - union txunderrun_u *value) -{ - return SW_NOT_SUPPORTED; -} - -sw_error_t -hppe_txpkt64_get( - a_uint32_t dev_id, - a_uint32_t index, - union txpkt64_u *value) -{ - if (index >= TXPKT64_MAX_ENTRY) - return SW_OUT_OF_RANGE; - return hppe_reg_get( - dev_id, - NSS_MAC_CSR_BASE_ADDR + TXPKT64_ADDRESS + \ - index * TXPKT64_INC, - &value->val); -} - -sw_error_t -hppe_txpkt64_set( - a_uint32_t dev_id, - a_uint32_t index, - union txpkt64_u *value) -{ - return SW_NOT_SUPPORTED; -} - -sw_error_t -hppe_txpkt65to127_get( - a_uint32_t dev_id, - a_uint32_t index, - union txpkt65to127_u *value) -{ - if (index >= TXPKT65TO127_MAX_ENTRY) - return SW_OUT_OF_RANGE; - return hppe_reg_get( - dev_id, - NSS_MAC_CSR_BASE_ADDR + TXPKT65TO127_ADDRESS + \ - index * TXPKT65TO127_INC, - &value->val); -} - -sw_error_t -hppe_txpkt65to127_set( - a_uint32_t dev_id, - a_uint32_t index, - union txpkt65to127_u *value) -{ - return SW_NOT_SUPPORTED; -} - -sw_error_t -hppe_txpkt128to255_get( - a_uint32_t dev_id, - a_uint32_t index, - union txpkt128to255_u *value) -{ - if (index >= TXPKT128TO255_MAX_ENTRY) - return SW_OUT_OF_RANGE; - return hppe_reg_get( - dev_id, - NSS_MAC_CSR_BASE_ADDR + TXPKT128TO255_ADDRESS + \ - index * TXPKT128TO255_INC, - &value->val); -} - -sw_error_t -hppe_txpkt128to255_set( - a_uint32_t dev_id, - a_uint32_t index, - union txpkt128to255_u *value) -{ - return SW_NOT_SUPPORTED; -} - -sw_error_t -hppe_txpkt256to511_get( - a_uint32_t dev_id, - a_uint32_t index, - union txpkt256to511_u *value) -{ - if (index >= TXPKT256TO511_MAX_ENTRY) - return SW_OUT_OF_RANGE; - return hppe_reg_get( - dev_id, - NSS_MAC_CSR_BASE_ADDR + TXPKT256TO511_ADDRESS + \ - index * TXPKT256TO511_INC, - &value->val); -} - -sw_error_t -hppe_txpkt256to511_set( - a_uint32_t dev_id, - a_uint32_t index, - union txpkt256to511_u *value) -{ - return SW_NOT_SUPPORTED; -} - -sw_error_t -hppe_txpkt512to1023_get( - a_uint32_t dev_id, - a_uint32_t index, - union txpkt512to1023_u *value) -{ - if (index >= TXPKT512TO1023_MAX_ENTRY) - return SW_OUT_OF_RANGE; - return hppe_reg_get( - dev_id, - NSS_MAC_CSR_BASE_ADDR + TXPKT512TO1023_ADDRESS + \ - index * TXPKT512TO1023_INC, - &value->val); -} - -sw_error_t -hppe_txpkt512to1023_set( - a_uint32_t dev_id, - a_uint32_t index, - union txpkt512to1023_u *value) -{ - return SW_NOT_SUPPORTED; -} - -sw_error_t -hppe_txpkt1024to1518_get( - a_uint32_t dev_id, - a_uint32_t index, - union txpkt1024to1518_u *value) -{ - if (index >= TXPKT1024TO1518_MAX_ENTRY) - return SW_OUT_OF_RANGE; - return hppe_reg_get( - dev_id, - NSS_MAC_CSR_BASE_ADDR + TXPKT1024TO1518_ADDRESS + \ - index * TXPKT1024TO1518_INC, - &value->val); -} - -sw_error_t -hppe_txpkt1024to1518_set( - a_uint32_t dev_id, - a_uint32_t index, - union txpkt1024to1518_u *value) -{ - return SW_NOT_SUPPORTED; -} - -sw_error_t -hppe_txpkt1519tox_get( - a_uint32_t dev_id, - a_uint32_t index, - union txpkt1519tox_u *value) -{ - if (index >= TXPKT1519TOX_MAX_ENTRY) - return SW_OUT_OF_RANGE; - return hppe_reg_get( - dev_id, - NSS_MAC_CSR_BASE_ADDR + TXPKT1519TOX_ADDRESS + \ - index * TXPKT1519TOX_INC, - &value->val); -} - -sw_error_t -hppe_txpkt1519tox_set( - a_uint32_t dev_id, - a_uint32_t index, - union txpkt1519tox_u *value) -{ - return SW_NOT_SUPPORTED; -} - -sw_error_t -hppe_txbyte_l_get( - a_uint32_t dev_id, - a_uint32_t index, - union txbyte_l_u *value) -{ - if (index >= TXBYTE_L_MAX_ENTRY) - return SW_OUT_OF_RANGE; - return hppe_reg_get( - dev_id, - NSS_MAC_CSR_BASE_ADDR + TXBYTE_L_ADDRESS + \ - index * TXBYTE_L_INC, - &value->val); -} - -sw_error_t -hppe_txbyte_l_set( - a_uint32_t dev_id, - a_uint32_t index, - union txbyte_l_u *value) -{ - return SW_NOT_SUPPORTED; -} - -sw_error_t -hppe_txbyte_h_get( - a_uint32_t dev_id, - a_uint32_t index, - union txbyte_h_u *value) -{ - if (index >= TXBYTE_H_MAX_ENTRY) - return SW_OUT_OF_RANGE; - return hppe_reg_get( - dev_id, - NSS_MAC_CSR_BASE_ADDR + TXBYTE_H_ADDRESS + \ - index * TXBYTE_H_INC, - &value->val); -} - -sw_error_t -hppe_txbyte_h_set( - a_uint32_t dev_id, - a_uint32_t index, - union txbyte_h_u *value) -{ - return SW_NOT_SUPPORTED; -} - -sw_error_t -hppe_txcollisions_get( - a_uint32_t dev_id, - a_uint32_t index, - union txcollisions_u *value) -{ - if (index >= TXCOLLISIONS_MAX_ENTRY) - return SW_OUT_OF_RANGE; - return hppe_reg_get( - dev_id, - NSS_MAC_CSR_BASE_ADDR + TXCOLLISIONS_ADDRESS + \ - index * TXCOLLISIONS_INC, - &value->val); -} - -sw_error_t -hppe_txcollisions_set( - a_uint32_t dev_id, - a_uint32_t index, - union txcollisions_u *value) -{ - return SW_NOT_SUPPORTED; -} - -sw_error_t -hppe_txabortcol_get( - a_uint32_t dev_id, - a_uint32_t index, - union txabortcol_u *value) -{ - if (index >= TXABORTCOL_MAX_ENTRY) - return SW_OUT_OF_RANGE; - return hppe_reg_get( - dev_id, - NSS_MAC_CSR_BASE_ADDR + TXABORTCOL_ADDRESS + \ - index * TXABORTCOL_INC, - &value->val); -} - -sw_error_t -hppe_txabortcol_set( - a_uint32_t dev_id, - a_uint32_t index, - union txabortcol_u *value) -{ - return SW_NOT_SUPPORTED; -} - -sw_error_t -hppe_txmulticol_get( - a_uint32_t dev_id, - a_uint32_t index, - union txmulticol_u *value) -{ - if (index >= TXMULTICOL_MAX_ENTRY) - return SW_OUT_OF_RANGE; - return hppe_reg_get( - dev_id, - NSS_MAC_CSR_BASE_ADDR + TXMULTICOL_ADDRESS + \ - index * TXMULTICOL_INC, - &value->val); -} - -sw_error_t -hppe_txmulticol_set( - a_uint32_t dev_id, - a_uint32_t index, - union txmulticol_u *value) -{ - return SW_NOT_SUPPORTED; -} - -sw_error_t -hppe_txsinglecol_get( - a_uint32_t dev_id, - a_uint32_t index, - union txsinglecol_u *value) -{ - if (index >= TXSINGLECOL_MAX_ENTRY) - return SW_OUT_OF_RANGE; - return hppe_reg_get( - dev_id, - NSS_MAC_CSR_BASE_ADDR + TXSINGLECOL_ADDRESS + \ - index * TXSINGLECOL_INC, - &value->val); -} - -sw_error_t -hppe_txsinglecol_set( - a_uint32_t dev_id, - a_uint32_t index, - union txsinglecol_u *value) -{ - return SW_NOT_SUPPORTED; -} - -sw_error_t -hppe_txexcessivedefer_get( - a_uint32_t dev_id, - a_uint32_t index, - union txexcessivedefer_u *value) -{ - if (index >= TXEXCESSIVEDEFER_MAX_ENTRY) - return SW_OUT_OF_RANGE; - return hppe_reg_get( - dev_id, - NSS_MAC_CSR_BASE_ADDR + TXEXCESSIVEDEFER_ADDRESS + \ - index * TXEXCESSIVEDEFER_INC, - &value->val); -} - -sw_error_t -hppe_txexcessivedefer_set( - a_uint32_t dev_id, - a_uint32_t index, - union txexcessivedefer_u *value) -{ - return SW_NOT_SUPPORTED; -} - -sw_error_t -hppe_txdefer_get( - a_uint32_t dev_id, - a_uint32_t index, - union txdefer_u *value) -{ - if (index >= TXDEFER_MAX_ENTRY) - return SW_OUT_OF_RANGE; - return hppe_reg_get( - dev_id, - NSS_MAC_CSR_BASE_ADDR + TXDEFER_ADDRESS + \ - index * TXDEFER_INC, - &value->val); -} - -sw_error_t -hppe_txdefer_set( - a_uint32_t dev_id, - a_uint32_t index, - union txdefer_u *value) -{ - return SW_NOT_SUPPORTED; -} - -sw_error_t -hppe_txlatecol_get( - a_uint32_t dev_id, - a_uint32_t index, - union txlatecol_u *value) -{ - if (index >= TXLATECOL_MAX_ENTRY) - return SW_OUT_OF_RANGE; - return hppe_reg_get( - dev_id, - NSS_MAC_CSR_BASE_ADDR + TXLATECOL_ADDRESS + \ - index * TXLATECOL_INC, - &value->val); -} - -sw_error_t -hppe_txlatecol_set( - a_uint32_t dev_id, - a_uint32_t index, - union txlatecol_u *value) -{ - return SW_NOT_SUPPORTED; -} - -sw_error_t -hppe_txuni_get( - a_uint32_t dev_id, - a_uint32_t index, - union txuni_u *value) -{ - if (index >= TXUNI_MAX_ENTRY) - return SW_OUT_OF_RANGE; - return hppe_reg_get( - dev_id, - NSS_MAC_CSR_BASE_ADDR + TXUNI_ADDRESS + \ - index * TXUNI_INC, - &value->val); -} - -sw_error_t -hppe_txuni_set( - a_uint32_t dev_id, - a_uint32_t index, - union txuni_u *value) -{ - return SW_NOT_SUPPORTED; -} - -sw_error_t -hppe_mac_mib_ctrl_mib_reset_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union mac_mib_ctrl_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_mac_mib_ctrl_get(dev_id, index, ®_val); - *value = reg_val.bf.mib_reset; - return ret; -} - -sw_error_t -hppe_mac_mib_ctrl_mib_reset_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - union mac_mib_ctrl_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_mac_mib_ctrl_get(dev_id, index, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.mib_reset = value; - ret = hppe_mac_mib_ctrl_set(dev_id, index, ®_val); - return ret; -} - -sw_error_t -hppe_mac_mib_ctrl_mib_en_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union mac_mib_ctrl_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_mac_mib_ctrl_get(dev_id, index, ®_val); - *value = reg_val.bf.mib_en; - return ret; -} - -sw_error_t -hppe_mac_mib_ctrl_mib_en_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - union mac_mib_ctrl_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_mac_mib_ctrl_get(dev_id, index, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.mib_en = value; - ret = hppe_mac_mib_ctrl_set(dev_id, index, ®_val); - return ret; -} - -sw_error_t -hppe_mac_mib_ctrl_mib_rd_clr_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union mac_mib_ctrl_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_mac_mib_ctrl_get(dev_id, index, ®_val); - *value = reg_val.bf.mib_rd_clr; - return ret; -} - -sw_error_t -hppe_mac_mib_ctrl_mib_rd_clr_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - union mac_mib_ctrl_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_mac_mib_ctrl_get(dev_id, index, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.mib_rd_clr = value; - ret = hppe_mac_mib_ctrl_set(dev_id, index, ®_val); - return ret; -} - -sw_error_t -hppe_rxbroad_rxbroad_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union rxbroad_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_rxbroad_get(dev_id, index, ®_val); - *value = reg_val.bf.rxbroad; - return ret; -} - -sw_error_t -hppe_rxbroad_rxbroad_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - return SW_NOT_SUPPORTED; -} - -sw_error_t -hppe_rxpause_rxpause_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union rxpause_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_rxpause_get(dev_id, index, ®_val); - *value = reg_val.bf.rxpause; - return ret; -} - -sw_error_t -hppe_rxpause_rxpause_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - return SW_NOT_SUPPORTED; -} - -sw_error_t -hppe_rxmulti_rxmulti_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union rxmulti_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_rxmulti_get(dev_id, index, ®_val); - *value = reg_val.bf.rxmulti; - return ret; -} - -sw_error_t -hppe_rxmulti_rxmulti_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - return SW_NOT_SUPPORTED; -} - -sw_error_t -hppe_rxfcserr_rxfcserr_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union rxfcserr_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_rxfcserr_get(dev_id, index, ®_val); - *value = reg_val.bf.rxfcserr; - return ret; -} - -sw_error_t -hppe_rxfcserr_rxfcserr_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - return SW_NOT_SUPPORTED; -} - -sw_error_t -hppe_rxalignerr_rxalignerr_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union rxalignerr_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_rxalignerr_get(dev_id, index, ®_val); - *value = reg_val.bf.rxalignerr; - return ret; -} - -sw_error_t -hppe_rxalignerr_rxalignerr_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - return SW_NOT_SUPPORTED; -} - -sw_error_t -hppe_rxrunt_rxrunt_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union rxrunt_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_rxrunt_get(dev_id, index, ®_val); - *value = reg_val.bf.rxrunt; - return ret; -} - -sw_error_t -hppe_rxrunt_rxrunt_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - return SW_NOT_SUPPORTED; -} - -sw_error_t -hppe_rxfrag_rxfrag_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union rxfrag_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_rxfrag_get(dev_id, index, ®_val); - *value = reg_val.bf.rxfrag; - return ret; -} - -sw_error_t -hppe_rxfrag_rxfrag_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - return SW_NOT_SUPPORTED; -} - -sw_error_t -hppe_rxjumbofcserr_rxjumbofcserr_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union rxjumbofcserr_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_rxjumbofcserr_get(dev_id, index, ®_val); - *value = reg_val.bf.rxjumbofcserr; - return ret; -} - -sw_error_t -hppe_rxjumbofcserr_rxjumbofcserr_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - return SW_NOT_SUPPORTED; -} - -sw_error_t -hppe_rxjumboalignerr_rxjumboalignerr_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union rxjumboalignerr_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_rxjumboalignerr_get(dev_id, index, ®_val); - *value = reg_val.bf.rxjumboalignerr; - return ret; -} - -sw_error_t -hppe_rxjumboalignerr_rxjumboalignerr_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - return SW_NOT_SUPPORTED; -} - -sw_error_t -hppe_rxpkt64_rxpkt64_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union rxpkt64_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_rxpkt64_get(dev_id, index, ®_val); - *value = reg_val.bf.rxpkt64; - return ret; -} - -sw_error_t -hppe_rxpkt64_rxpkt64_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - return SW_NOT_SUPPORTED; -} - -sw_error_t -hppe_rxpkt65to127_rxpkt65to127_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union rxpkt65to127_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_rxpkt65to127_get(dev_id, index, ®_val); - *value = reg_val.bf.rxpkt65to127; - return ret; -} - -sw_error_t -hppe_rxpkt65to127_rxpkt65to127_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - return SW_NOT_SUPPORTED; -} - -sw_error_t -hppe_rxpkt128to255_rxpkt128to255_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union rxpkt128to255_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_rxpkt128to255_get(dev_id, index, ®_val); - *value = reg_val.bf.rxpkt128to255; - return ret; -} - -sw_error_t -hppe_rxpkt128to255_rxpkt128to255_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - return SW_NOT_SUPPORTED; -} - -sw_error_t -hppe_rxpkt256to511_rxpkt256to511_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union rxpkt256to511_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_rxpkt256to511_get(dev_id, index, ®_val); - *value = reg_val.bf.rxpkt256to511; - return ret; -} - -sw_error_t -hppe_rxpkt256to511_rxpkt256to511_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - return SW_NOT_SUPPORTED; -} - -sw_error_t -hppe_rxpkt512to1023_rxpkt512to1023_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union rxpkt512to1023_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_rxpkt512to1023_get(dev_id, index, ®_val); - *value = reg_val.bf.rxpkt512to1023; - return ret; -} - -sw_error_t -hppe_rxpkt512to1023_rxpkt512to1023_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - return SW_NOT_SUPPORTED; -} - -sw_error_t -hppe_rxpkt1024to1518_rxpkt1024to1518_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union rxpkt1024to1518_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_rxpkt1024to1518_get(dev_id, index, ®_val); - *value = reg_val.bf.rxpkt1024to1518; - return ret; -} - -sw_error_t -hppe_rxpkt1024to1518_rxpkt1024to1518_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - return SW_NOT_SUPPORTED; -} - -sw_error_t -hppe_rxpkt1519tox_rxpkt1519tox_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union rxpkt1519tox_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_rxpkt1519tox_get(dev_id, index, ®_val); - *value = reg_val.bf.rxpkt1519tox; - return ret; -} - -sw_error_t -hppe_rxpkt1519tox_rxpkt1519tox_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - return SW_NOT_SUPPORTED; -} - -sw_error_t -hppe_rxtoolong_rxtoolong_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union rxtoolong_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_rxtoolong_get(dev_id, index, ®_val); - *value = reg_val.bf.rxtoolong; - return ret; -} - -sw_error_t -hppe_rxtoolong_rxtoolong_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - return SW_NOT_SUPPORTED; -} - -sw_error_t -hppe_rxgoodbyte_l_rxgoodbyte_l_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union rxgoodbyte_l_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_rxgoodbyte_l_get(dev_id, index, ®_val); - *value = reg_val.bf.rxgoodbyte_l; - return ret; -} - -sw_error_t -hppe_rxgoodbyte_l_rxgoodbyte_l_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - return SW_NOT_SUPPORTED; -} - -sw_error_t -hppe_rxgoodbyte_h_rxgoodbyte_h_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union rxgoodbyte_h_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_rxgoodbyte_h_get(dev_id, index, ®_val); - *value = reg_val.bf.rxgoodbyte_h; - return ret; -} - -sw_error_t -hppe_rxgoodbyte_h_rxgoodbyte_h_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - return SW_NOT_SUPPORTED; -} - -sw_error_t -hppe_rxbadbyte_l_rxbadbyte_l_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union rxbadbyte_l_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_rxbadbyte_l_get(dev_id, index, ®_val); - *value = reg_val.bf.rxbadbyte_l; - return ret; -} - -sw_error_t -hppe_rxbadbyte_l_rxbadbyte_l_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - return SW_NOT_SUPPORTED; -} - -sw_error_t -hppe_rxbadbyte_h_rxbadbyte_h_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union rxbadbyte_h_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_rxbadbyte_h_get(dev_id, index, ®_val); - *value = reg_val.bf.rxbadbyte_h; - return ret; -} - -sw_error_t -hppe_rxbadbyte_h_rxbadbyte_h_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - return SW_NOT_SUPPORTED; -} - -sw_error_t -hppe_rxuni_rxuni_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union rxuni_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_rxuni_get(dev_id, index, ®_val); - *value = reg_val.bf.rxuni; - return ret; -} - -sw_error_t -hppe_rxuni_rxuni_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - return SW_NOT_SUPPORTED; -} - -sw_error_t -hppe_txbroad_txbroad_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union txbroad_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_txbroad_get(dev_id, index, ®_val); - *value = reg_val.bf.txbroad; - return ret; -} - -sw_error_t -hppe_txbroad_txbroad_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - return SW_NOT_SUPPORTED; -} - -sw_error_t -hppe_txpause_txpause_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union txpause_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_txpause_get(dev_id, index, ®_val); - *value = reg_val.bf.txpause; - return ret; -} - -sw_error_t -hppe_txpause_txpause_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - return SW_NOT_SUPPORTED; -} - -sw_error_t -hppe_txmulti_txmulti_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union txmulti_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_txmulti_get(dev_id, index, ®_val); - *value = reg_val.bf.txmulti; - return ret; -} - -sw_error_t -hppe_txmulti_txmulti_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - return SW_NOT_SUPPORTED; -} - -sw_error_t -hppe_txunderrun_txunderrun_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union txunderrun_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_txunderrun_get(dev_id, index, ®_val); - *value = reg_val.bf.txunderrun; - return ret; -} - -sw_error_t -hppe_txunderrun_txunderrun_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - return SW_NOT_SUPPORTED; -} - -sw_error_t -hppe_txpkt64_txpkt64_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union txpkt64_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_txpkt64_get(dev_id, index, ®_val); - *value = reg_val.bf.txpkt64; - return ret; -} - -sw_error_t -hppe_txpkt64_txpkt64_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - return SW_NOT_SUPPORTED; -} - -sw_error_t -hppe_txpkt65to127_txpkt65to127_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union txpkt65to127_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_txpkt65to127_get(dev_id, index, ®_val); - *value = reg_val.bf.txpkt65to127; - return ret; -} - -sw_error_t -hppe_txpkt65to127_txpkt65to127_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - return SW_NOT_SUPPORTED; -} - -sw_error_t -hppe_txpkt128to255_txpkt128to255_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union txpkt128to255_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_txpkt128to255_get(dev_id, index, ®_val); - *value = reg_val.bf.txpkt128to255; - return ret; -} - -sw_error_t -hppe_txpkt128to255_txpkt128to255_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - return SW_NOT_SUPPORTED; -} - -sw_error_t -hppe_txpkt256to511_txpkt256to511_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union txpkt256to511_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_txpkt256to511_get(dev_id, index, ®_val); - *value = reg_val.bf.txpkt256to511; - return ret; -} - -sw_error_t -hppe_txpkt256to511_txpkt256to511_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - return SW_NOT_SUPPORTED; -} - -sw_error_t -hppe_txpkt512to1023_txpkt512to1023_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union txpkt512to1023_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_txpkt512to1023_get(dev_id, index, ®_val); - *value = reg_val.bf.txpkt512to1023; - return ret; -} - -sw_error_t -hppe_txpkt512to1023_txpkt512to1023_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - return SW_NOT_SUPPORTED; -} - -sw_error_t -hppe_txpkt1024to1518_txpkt1024to1518_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union txpkt1024to1518_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_txpkt1024to1518_get(dev_id, index, ®_val); - *value = reg_val.bf.txpkt1024to1518; - return ret; -} - -sw_error_t -hppe_txpkt1024to1518_txpkt1024to1518_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - return SW_NOT_SUPPORTED; -} - -sw_error_t -hppe_txpkt1519tox_txpkt1519tox_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union txpkt1519tox_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_txpkt1519tox_get(dev_id, index, ®_val); - *value = reg_val.bf.txpkt1519tox; - return ret; -} - -sw_error_t -hppe_txpkt1519tox_txpkt1519tox_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - return SW_NOT_SUPPORTED; -} - -sw_error_t -hppe_txbyte_l_txbyte_l_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union txbyte_l_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_txbyte_l_get(dev_id, index, ®_val); - *value = reg_val.bf.txbyte_l; - return ret; -} - -sw_error_t -hppe_txbyte_l_txbyte_l_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - return SW_NOT_SUPPORTED; -} - -sw_error_t -hppe_txbyte_h_txbyte_h_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union txbyte_h_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_txbyte_h_get(dev_id, index, ®_val); - *value = reg_val.bf.txbyte_h; - return ret; -} - -sw_error_t -hppe_txbyte_h_txbyte_h_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - return SW_NOT_SUPPORTED; -} - -sw_error_t -hppe_txcollisions_txcollisions_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union txcollisions_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_txcollisions_get(dev_id, index, ®_val); - *value = reg_val.bf.txcollisions; - return ret; -} - -sw_error_t -hppe_txcollisions_txcollisions_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - return SW_NOT_SUPPORTED; -} - -sw_error_t -hppe_txabortcol_txabortcol_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union txabortcol_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_txabortcol_get(dev_id, index, ®_val); - *value = reg_val.bf.txabortcol; - return ret; -} - -sw_error_t -hppe_txabortcol_txabortcol_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - return SW_NOT_SUPPORTED; -} - -sw_error_t -hppe_txmulticol_txmulticol_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union txmulticol_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_txmulticol_get(dev_id, index, ®_val); - *value = reg_val.bf.txmulticol; - return ret; -} - -sw_error_t -hppe_txmulticol_txmulticol_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - return SW_NOT_SUPPORTED; -} - -sw_error_t -hppe_txsinglecol_txsinglecol_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union txsinglecol_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_txsinglecol_get(dev_id, index, ®_val); - *value = reg_val.bf.txsinglecol; - return ret; -} - -sw_error_t -hppe_txsinglecol_txsinglecol_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - return SW_NOT_SUPPORTED; -} - -sw_error_t -hppe_txexcessivedefer_txexcessivedefer_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union txexcessivedefer_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_txexcessivedefer_get(dev_id, index, ®_val); - *value = reg_val.bf.txexcessivedefer; - return ret; -} - -sw_error_t -hppe_txexcessivedefer_txexcessivedefer_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - return SW_NOT_SUPPORTED; -} - -sw_error_t -hppe_txdefer_txdefer_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union txdefer_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_txdefer_get(dev_id, index, ®_val); - *value = reg_val.bf.txdefer; - return ret; -} - -sw_error_t -hppe_txdefer_txdefer_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - return SW_NOT_SUPPORTED; -} - -sw_error_t -hppe_txlatecol_txlatecol_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union txlatecol_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_txlatecol_get(dev_id, index, ®_val); - *value = reg_val.bf.txlatecol; - return ret; -} - -sw_error_t -hppe_txlatecol_txlatecol_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - return SW_NOT_SUPPORTED; -} - -sw_error_t -hppe_txuni_txuni_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union txuni_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_txuni_get(dev_id, index, ®_val); - *value = reg_val.bf.txuni; - return ret; -} - -sw_error_t -hppe_txuni_txuni_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - return SW_NOT_SUPPORTED; -} - diff --git a/feeds/ipq807x/qca-ssdk/src/src/hsl/hppe/hppe_mirror.c b/feeds/ipq807x/qca-ssdk/src/src/hsl/hppe/hppe_mirror.c deleted file mode 100755 index 531460a7f..000000000 --- a/feeds/ipq807x/qca-ssdk/src/src/hsl/hppe/hppe_mirror.c +++ /dev/null @@ -1,194 +0,0 @@ -/* - * Copyright (c) 2016-2017, The Linux Foundation. All rights reserved. - * Permission to use, copy, modify, and/or distribute this software for - * any purpose with or without fee is hereby granted, provided that the - * above copyright notice and this permission notice appear in all copies. - * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES - * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR - * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES - * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN - * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT - * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. - */ - - -/** - * @defgroup - * @{ - */ -#include "sw.h" -#include "hsl.h" -#include "hppe_reg_access.h" -#include "hppe_mirror_reg.h" -#include "hppe_mirror.h" - -sw_error_t -hppe_mirror_analyzer_get( - a_uint32_t dev_id, - union mirror_analyzer_u *value) -{ - return hppe_reg_get( - dev_id, - IPE_L2_BASE_ADDR + MIRROR_ANALYZER_ADDRESS, - &value->val); -} - -sw_error_t -hppe_mirror_analyzer_set( - a_uint32_t dev_id, - union mirror_analyzer_u *value) -{ - return hppe_reg_set( - dev_id, - IPE_L2_BASE_ADDR + MIRROR_ANALYZER_ADDRESS, - value->val); -} - -sw_error_t -hppe_port_mirror_get( - a_uint32_t dev_id, - a_uint32_t index, - union port_mirror_u *value) -{ - if (index >= PORT_MIRROR_MAX_ENTRY) - return SW_OUT_OF_RANGE; - return hppe_reg_get( - dev_id, - IPE_L2_BASE_ADDR + PORT_MIRROR_ADDRESS + \ - index * PORT_MIRROR_INC, - &value->val); -} - -sw_error_t -hppe_port_mirror_set( - a_uint32_t dev_id, - a_uint32_t index, - union port_mirror_u *value) -{ - return hppe_reg_set( - dev_id, - IPE_L2_BASE_ADDR + PORT_MIRROR_ADDRESS + \ - index * PORT_MIRROR_INC, - value->val); -} - -sw_error_t -hppe_mirror_analyzer_in_analyzer_port_get( - a_uint32_t dev_id, - a_uint32_t *value) -{ - union mirror_analyzer_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_mirror_analyzer_get(dev_id, ®_val); - *value = reg_val.bf.in_analyzer_port; - return ret; -} - -sw_error_t -hppe_mirror_analyzer_in_analyzer_port_set( - a_uint32_t dev_id, - a_uint32_t value) -{ - union mirror_analyzer_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_mirror_analyzer_get(dev_id, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.in_analyzer_port = value; - ret = hppe_mirror_analyzer_set(dev_id, ®_val); - return ret; -} - -sw_error_t -hppe_mirror_analyzer_eg_analyzer_port_get( - a_uint32_t dev_id, - a_uint32_t *value) -{ - union mirror_analyzer_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_mirror_analyzer_get(dev_id, ®_val); - *value = reg_val.bf.eg_analyzer_port; - return ret; -} - -sw_error_t -hppe_mirror_analyzer_eg_analyzer_port_set( - a_uint32_t dev_id, - a_uint32_t value) -{ - union mirror_analyzer_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_mirror_analyzer_get(dev_id, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.eg_analyzer_port = value; - ret = hppe_mirror_analyzer_set(dev_id, ®_val); - return ret; -} - -sw_error_t -hppe_port_mirror_in_mirr_en_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union port_mirror_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_port_mirror_get(dev_id, index, ®_val); - *value = reg_val.bf.in_mirr_en; - return ret; -} - -sw_error_t -hppe_port_mirror_in_mirr_en_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - union port_mirror_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_port_mirror_get(dev_id, index, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.in_mirr_en = value; - ret = hppe_port_mirror_set(dev_id, index, ®_val); - return ret; -} - -sw_error_t -hppe_port_mirror_eg_mirr_en_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union port_mirror_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_port_mirror_get(dev_id, index, ®_val); - *value = reg_val.bf.eg_mirr_en; - return ret; -} - -sw_error_t -hppe_port_mirror_eg_mirr_en_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - union port_mirror_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_port_mirror_get(dev_id, index, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.eg_mirr_en = value; - ret = hppe_port_mirror_set(dev_id, index, ®_val); - return ret; -} diff --git a/feeds/ipq807x/qca-ssdk/src/src/hsl/hppe/hppe_policer.c b/feeds/ipq807x/qca-ssdk/src/src/hsl/hppe/hppe_policer.c deleted file mode 100755 index 45e8f3489..000000000 --- a/feeds/ipq807x/qca-ssdk/src/src/hsl/hppe/hppe_policer.c +++ /dev/null @@ -1,2928 +0,0 @@ -/* - * Copyright (c) 2016-2017, 2021, The Linux Foundation. All rights reserved. - * Permission to use, copy, modify, and/or distribute this software for - * any purpose with or without fee is hereby granted, provided that the - * above copyright notice and this permission notice appear in all copies. - * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES - * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR - * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES - * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN - * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT - * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. - */ - - -/** - * @defgroup - * @{ - */ -#include "sw.h" -#include "hsl.h" -#include "hppe_reg_access.h" -#include "hppe_policer_reg.h" -#include "hppe_policer.h" - -sw_error_t -hppe_meter_cmpst_length_reg_get( - a_uint32_t dev_id, - a_uint32_t index, - union meter_cmpst_length_reg_u *value) -{ - if (index >= METER_CMPST_LENGTH_REG_MAX_ENTRY) - return SW_OUT_OF_RANGE; - return hppe_reg_get( - dev_id, - INGRESS_POLICER_BASE_ADDR + METER_CMPST_LENGTH_REG_ADDRESS + \ - index * METER_CMPST_LENGTH_REG_INC, - &value->val); -} - -sw_error_t -hppe_meter_cmpst_length_reg_set( - a_uint32_t dev_id, - a_uint32_t index, - union meter_cmpst_length_reg_u *value) -{ - return hppe_reg_set( - dev_id, - INGRESS_POLICER_BASE_ADDR + METER_CMPST_LENGTH_REG_ADDRESS + \ - index * METER_CMPST_LENGTH_REG_INC, - value->val); -} - -sw_error_t -hppe_pc_drop_bypass_reg_set( - a_uint32_t dev_id, - union pc_drop_bypass_reg_u *value) -{ - return hppe_reg_set( - dev_id, - INGRESS_POLICER_BASE_ADDR + PC_DROP_BYPASS_REG_ADDRESS, - value->val); -} - -#ifndef IN_POLICER_MINI -sw_error_t -hppe_pc_drop_bypass_reg_get( - a_uint32_t dev_id, - union pc_drop_bypass_reg_u *value) -{ - return hppe_reg_get( - dev_id, - INGRESS_POLICER_BASE_ADDR + PC_DROP_BYPASS_REG_ADDRESS, - &value->val); -} - -sw_error_t -hppe_pc_spare_reg_get( - a_uint32_t dev_id, - union pc_spare_reg_u *value) -{ - return hppe_reg_get( - dev_id, - INGRESS_POLICER_BASE_ADDR + PC_SPARE_REG_ADDRESS, - &value->val); -} - -sw_error_t -hppe_pc_spare_reg_set( - a_uint32_t dev_id, - union pc_spare_reg_u *value) -{ - return hppe_reg_set( - dev_id, - INGRESS_POLICER_BASE_ADDR + PC_SPARE_REG_ADDRESS, - value->val); -} - -sw_error_t -hppe_time_slot_reg_get( - a_uint32_t dev_id, - union time_slot_reg_u *value) -{ - return hppe_reg_get( - dev_id, - INGRESS_POLICER_BASE_ADDR + TIME_SLOT_REG_ADDRESS, - &value->val); -} -#endif - -sw_error_t -hppe_time_slot_reg_set( - a_uint32_t dev_id, - union time_slot_reg_u *value) -{ - return hppe_reg_set( - dev_id, - INGRESS_POLICER_BASE_ADDR + TIME_SLOT_REG_ADDRESS, - value->val); -} - -#ifndef IN_POLICER_MINI -sw_error_t -hppe_pc_dbg_addr_reg_get( - a_uint32_t dev_id, - union pc_dbg_addr_reg_u *value) -{ - return hppe_reg_get( - dev_id, - INGRESS_POLICER_BASE_ADDR + PC_DBG_ADDR_REG_ADDRESS, - &value->val); -} - -sw_error_t -hppe_pc_dbg_addr_reg_set( - a_uint32_t dev_id, - union pc_dbg_addr_reg_u *value) -{ - return hppe_reg_set( - dev_id, - INGRESS_POLICER_BASE_ADDR + PC_DBG_ADDR_REG_ADDRESS, - value->val); -} - -sw_error_t -hppe_pc_dbg_data_reg_get( - a_uint32_t dev_id, - union pc_dbg_data_reg_u *value) -{ - return hppe_reg_get( - dev_id, - INGRESS_POLICER_BASE_ADDR + PC_DBG_DATA_REG_ADDRESS, - &value->val); -} - -sw_error_t -hppe_pc_dbg_data_reg_set( - a_uint32_t dev_id, - union pc_dbg_data_reg_u *value) -{ - return SW_NOT_SUPPORTED; -} - -sw_error_t -hppe_in_acl_meter_cfg_tbl_get( - a_uint32_t dev_id, - a_uint32_t index, - union in_acl_meter_cfg_tbl_u *value) -{ - return hppe_reg_tbl_get( - dev_id, - INGRESS_POLICER_BASE_ADDR + IN_ACL_METER_CFG_TBL_ADDRESS + \ - index * IN_ACL_METER_CFG_TBL_INC, - value->val, - 4); -} - -sw_error_t -hppe_in_acl_meter_cfg_tbl_set( - a_uint32_t dev_id, - a_uint32_t index, - union in_acl_meter_cfg_tbl_u *value) -{ - return hppe_reg_tbl_set( - dev_id, - INGRESS_POLICER_BASE_ADDR + IN_ACL_METER_CFG_TBL_ADDRESS + \ - index * IN_ACL_METER_CFG_TBL_INC, - value->val, - 4); -} - -sw_error_t -hppe_in_acl_meter_crdt_tbl_get( - a_uint32_t dev_id, - a_uint32_t index, - union in_acl_meter_crdt_tbl_u *value) -{ - return hppe_reg_tbl_get( - dev_id, - INGRESS_POLICER_BASE_ADDR + IN_ACL_METER_CRDT_TBL_ADDRESS + \ - index * IN_ACL_METER_CRDT_TBL_INC, - value->val, - 2); -} - -sw_error_t -hppe_in_acl_meter_crdt_tbl_set( - a_uint32_t dev_id, - a_uint32_t index, - union in_acl_meter_crdt_tbl_u *value) -{ - return hppe_reg_tbl_set( - dev_id, - INGRESS_POLICER_BASE_ADDR + IN_ACL_METER_CRDT_TBL_ADDRESS + \ - index * IN_ACL_METER_CRDT_TBL_INC, - value->val, - 2); -} - -sw_error_t -hppe_in_port_meter_cfg_tbl_get( - a_uint32_t dev_id, - a_uint32_t index, - union in_port_meter_cfg_tbl_u *value) -{ - return hppe_reg_tbl_get( - dev_id, - INGRESS_POLICER_BASE_ADDR + IN_PORT_METER_CFG_TBL_ADDRESS + \ - index * IN_PORT_METER_CFG_TBL_INC, - value->val, - 4); -} - -sw_error_t -hppe_in_port_meter_cfg_tbl_set( - a_uint32_t dev_id, - a_uint32_t index, - union in_port_meter_cfg_tbl_u *value) -{ - return hppe_reg_tbl_set( - dev_id, - INGRESS_POLICER_BASE_ADDR + IN_PORT_METER_CFG_TBL_ADDRESS + \ - index * IN_PORT_METER_CFG_TBL_INC, - value->val, - 4); -} - -sw_error_t -hppe_in_port_meter_crdt_tbl_get( - a_uint32_t dev_id, - a_uint32_t index, - union in_port_meter_crdt_tbl_u *value) -{ - return hppe_reg_tbl_get( - dev_id, - INGRESS_POLICER_BASE_ADDR + IN_PORT_METER_CRDT_TBL_ADDRESS + \ - index * IN_PORT_METER_CRDT_TBL_INC, - value->val, - 2); -} - -sw_error_t -hppe_in_port_meter_crdt_tbl_set( - a_uint32_t dev_id, - a_uint32_t index, - union in_port_meter_crdt_tbl_u *value) -{ - return hppe_reg_tbl_set( - dev_id, - INGRESS_POLICER_BASE_ADDR + IN_PORT_METER_CRDT_TBL_ADDRESS + \ - index * IN_PORT_METER_CRDT_TBL_INC, - value->val, - 2); -} - -sw_error_t -hppe_in_port_meter_cnt_tbl_get( - a_uint32_t dev_id, - a_uint32_t index, - union in_port_meter_cnt_tbl_u *value) -{ - return hppe_reg_tbl_get( - dev_id, - INGRESS_POLICER_BASE_ADDR + IN_PORT_METER_CNT_TBL_ADDRESS + \ - index * IN_PORT_METER_CNT_TBL_INC, - value->val, - 3); -} - -sw_error_t -hppe_in_port_meter_cnt_tbl_set( - a_uint32_t dev_id, - a_uint32_t index, - union in_port_meter_cnt_tbl_u *value) -{ - return hppe_reg_tbl_set( - dev_id, - INGRESS_POLICER_BASE_ADDR + IN_PORT_METER_CNT_TBL_ADDRESS + \ - index * IN_PORT_METER_CNT_TBL_INC, - value->val, - 3); -} - -sw_error_t -hppe_in_acl_meter_cnt_tbl_get( - a_uint32_t dev_id, - a_uint32_t index, - union in_acl_meter_cnt_tbl_u *value) -{ - return hppe_reg_tbl_get( - dev_id, - INGRESS_POLICER_BASE_ADDR + IN_ACL_METER_CNT_TBL_ADDRESS + \ - index * IN_ACL_METER_CNT_TBL_INC, - value->val, - 3); -} - -sw_error_t -hppe_in_acl_meter_cnt_tbl_set( - a_uint32_t dev_id, - a_uint32_t index, - union in_acl_meter_cnt_tbl_u *value) -{ - return hppe_reg_tbl_set( - dev_id, - INGRESS_POLICER_BASE_ADDR + IN_ACL_METER_CNT_TBL_ADDRESS + \ - index * IN_ACL_METER_CNT_TBL_INC, - value->val, - 3); -} - -sw_error_t -hppe_pc_global_cnt_tbl_get( - a_uint32_t dev_id, - a_uint32_t index, - union pc_global_cnt_tbl_u *value) -{ - return hppe_reg_tbl_get( - dev_id, - INGRESS_POLICER_BASE_ADDR + PC_GLOBAL_CNT_TBL_ADDRESS + \ - index * PC_GLOBAL_CNT_TBL_INC, - value->val, - 3); -} - -sw_error_t -hppe_pc_global_cnt_tbl_set( - a_uint32_t dev_id, - a_uint32_t index, - union pc_global_cnt_tbl_u *value) -{ - return hppe_reg_tbl_set( - dev_id, - INGRESS_POLICER_BASE_ADDR + PC_GLOBAL_CNT_TBL_ADDRESS + \ - index * PC_GLOBAL_CNT_TBL_INC, - value->val, - 3); -} -#endif - -sw_error_t -hppe_drop_cpu_cnt_tbl_get( - a_uint32_t dev_id, - a_uint32_t index, - union drop_cpu_cnt_tbl_u *value) -{ - return hppe_reg_tbl_get( - dev_id, - INGRESS_POLICER_BASE_ADDR + DROP_CPU_CNT_TBL_ADDRESS + \ - index * DROP_CPU_CNT_TBL_INC, - value->val, - 3); -} - -sw_error_t -hppe_drop_cpu_cnt_tbl_set( - a_uint32_t dev_id, - a_uint32_t index, - union drop_cpu_cnt_tbl_u *value) -{ - return hppe_reg_tbl_set( - dev_id, - INGRESS_POLICER_BASE_ADDR + DROP_CPU_CNT_TBL_ADDRESS + \ - index * DROP_CPU_CNT_TBL_INC, - value->val, - 3); -} - -sw_error_t -hppe_port_tx_drop_cnt_tbl_get( - a_uint32_t dev_id, - a_uint32_t index, - union port_tx_drop_cnt_tbl_u *value) -{ - return hppe_reg_tbl_get( - dev_id, - INGRESS_POLICER_BASE_ADDR + PORT_TX_DROP_CNT_TBL_ADDRESS + \ - index * PORT_TX_DROP_CNT_TBL_INC, - value->val, - 3); -} - -sw_error_t -hppe_port_tx_drop_cnt_tbl_set( - a_uint32_t dev_id, - a_uint32_t index, - union port_tx_drop_cnt_tbl_u *value) -{ - return hppe_reg_tbl_set( - dev_id, - INGRESS_POLICER_BASE_ADDR + PORT_TX_DROP_CNT_TBL_ADDRESS + \ - index * PORT_TX_DROP_CNT_TBL_INC, - value->val, - 3); -} - -sw_error_t -hppe_vp_tx_drop_cnt_tbl_get( - a_uint32_t dev_id, - a_uint32_t index, - union vp_tx_drop_cnt_tbl_u *value) -{ - return hppe_reg_tbl_get( - dev_id, - INGRESS_POLICER_BASE_ADDR + VP_TX_DROP_CNT_TBL_ADDRESS + \ - index * VP_TX_DROP_CNT_TBL_INC, - value->val, - 3); -} - -sw_error_t -hppe_vp_tx_drop_cnt_tbl_set( - a_uint32_t dev_id, - a_uint32_t index, - union vp_tx_drop_cnt_tbl_u *value) -{ - return hppe_reg_tbl_set( - dev_id, - INGRESS_POLICER_BASE_ADDR + VP_TX_DROP_CNT_TBL_ADDRESS + \ - index * VP_TX_DROP_CNT_TBL_INC, - value->val, - 3); -} - -sw_error_t -hppe_vlan_dev_cnt_tbl_get( - a_uint32_t dev_id, - a_uint32_t index, - union vlan_dev_cnt_tbl_u *value) -{ - return hppe_reg_tbl_get( - dev_id, - INGRESS_POLICER_BASE_ADDR + VLAN_DEV_CNT_TBL_ADDRESS + \ - index * VLAN_DEV_CNT_TBL_INC, - value->val, - 3); -} - -sw_error_t -hppe_vlan_dev_cnt_tbl_set( - a_uint32_t dev_id, - a_uint32_t index, - union vlan_dev_cnt_tbl_u *value) -{ - return hppe_reg_tbl_set( - dev_id, - INGRESS_POLICER_BASE_ADDR + VLAN_DEV_CNT_TBL_ADDRESS + \ - index * VLAN_DEV_CNT_TBL_INC, - value->val, - 3); -} - -#ifndef IN_POLICER_MINI -sw_error_t -hppe_meter_cmpst_length_reg_cmpst_length_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union meter_cmpst_length_reg_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_meter_cmpst_length_reg_get(dev_id, index, ®_val); - *value = reg_val.bf.cmpst_length; - return ret; -} - -sw_error_t -hppe_meter_cmpst_length_reg_cmpst_length_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - union meter_cmpst_length_reg_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_meter_cmpst_length_reg_get(dev_id, index, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.cmpst_length = value; - ret = hppe_meter_cmpst_length_reg_set(dev_id, index, ®_val); - return ret; -} - -sw_error_t -hppe_pc_drop_bypass_reg_drop_bypass_en_get( - a_uint32_t dev_id, - a_uint32_t *value) -{ - union pc_drop_bypass_reg_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_pc_drop_bypass_reg_get(dev_id, ®_val); - *value = reg_val.bf.drop_bypass_en; - return ret; -} - -sw_error_t -hppe_pc_drop_bypass_reg_drop_bypass_en_set( - a_uint32_t dev_id, - a_uint32_t value) -{ - union pc_drop_bypass_reg_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_pc_drop_bypass_reg_get(dev_id, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.drop_bypass_en = value; - ret = hppe_pc_drop_bypass_reg_set(dev_id, ®_val); - return ret; -} - -sw_error_t -hppe_pc_spare_reg_spare_reg_get( - a_uint32_t dev_id, - a_uint32_t *value) -{ - union pc_spare_reg_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_pc_spare_reg_get(dev_id, ®_val); - *value = reg_val.bf.spare_reg; - return ret; -} - -sw_error_t -hppe_pc_spare_reg_spare_reg_set( - a_uint32_t dev_id, - a_uint32_t value) -{ - union pc_spare_reg_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_pc_spare_reg_get(dev_id, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.spare_reg = value; - ret = hppe_pc_spare_reg_set(dev_id, ®_val); - return ret; -} - -sw_error_t -hppe_time_slot_reg_time_slot_get( - a_uint32_t dev_id, - a_uint32_t *value) -{ - union time_slot_reg_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_time_slot_reg_get(dev_id, ®_val); - *value = reg_val.bf.time_slot; - return ret; -} - -sw_error_t -hppe_time_slot_reg_time_slot_set( - a_uint32_t dev_id, - a_uint32_t value) -{ - union time_slot_reg_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_time_slot_reg_get(dev_id, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.time_slot = value; - ret = hppe_time_slot_reg_set(dev_id, ®_val); - return ret; -} - -sw_error_t -hppe_pc_dbg_addr_reg_dbg_addr_get( - a_uint32_t dev_id, - a_uint32_t *value) -{ - union pc_dbg_addr_reg_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_pc_dbg_addr_reg_get(dev_id, ®_val); - *value = reg_val.bf.dbg_addr; - return ret; -} - -sw_error_t -hppe_pc_dbg_addr_reg_dbg_addr_set( - a_uint32_t dev_id, - a_uint32_t value) -{ - union pc_dbg_addr_reg_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_pc_dbg_addr_reg_get(dev_id, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.dbg_addr = value; - ret = hppe_pc_dbg_addr_reg_set(dev_id, ®_val); - return ret; -} - -sw_error_t -hppe_pc_dbg_data_reg_dbg_data_get( - a_uint32_t dev_id, - a_uint32_t *value) -{ - union pc_dbg_data_reg_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_pc_dbg_data_reg_get(dev_id, ®_val); - *value = reg_val.bf.dbg_data; - return ret; -} - -sw_error_t -hppe_pc_dbg_data_reg_dbg_data_set( - a_uint32_t dev_id, - a_uint32_t value) -{ - return SW_NOT_SUPPORTED; -} - -sw_error_t -hppe_in_acl_meter_cfg_tbl_meter_mode_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union in_acl_meter_cfg_tbl_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_in_acl_meter_cfg_tbl_get(dev_id, index, ®_val); - *value = reg_val.bf.meter_mode; - return ret; -} - -sw_error_t -hppe_in_acl_meter_cfg_tbl_meter_mode_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - union in_acl_meter_cfg_tbl_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_in_acl_meter_cfg_tbl_get(dev_id, index, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.meter_mode = value; - ret = hppe_in_acl_meter_cfg_tbl_set(dev_id, index, ®_val); - return ret; -} - -sw_error_t -hppe_in_acl_meter_cfg_tbl_color_mode_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union in_acl_meter_cfg_tbl_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_in_acl_meter_cfg_tbl_get(dev_id, index, ®_val); - *value = reg_val.bf.color_mode; - return ret; -} - -sw_error_t -hppe_in_acl_meter_cfg_tbl_color_mode_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - union in_acl_meter_cfg_tbl_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_in_acl_meter_cfg_tbl_get(dev_id, index, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.color_mode = value; - ret = hppe_in_acl_meter_cfg_tbl_set(dev_id, index, ®_val); - return ret; -} - -sw_error_t -hppe_in_acl_meter_cfg_tbl_exceed_chg_pcp_cmd_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union in_acl_meter_cfg_tbl_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_in_acl_meter_cfg_tbl_get(dev_id, index, ®_val); - *value = reg_val.bf.exceed_chg_pcp_cmd; - return ret; -} - -sw_error_t -hppe_in_acl_meter_cfg_tbl_exceed_chg_pcp_cmd_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - union in_acl_meter_cfg_tbl_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_in_acl_meter_cfg_tbl_get(dev_id, index, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.exceed_chg_pcp_cmd = value; - ret = hppe_in_acl_meter_cfg_tbl_set(dev_id, index, ®_val); - return ret; -} - -sw_error_t -hppe_in_acl_meter_cfg_tbl_exceed_pri_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union in_acl_meter_cfg_tbl_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_in_acl_meter_cfg_tbl_get(dev_id, index, ®_val); - *value = reg_val.bf.exceed_pri; - return ret; -} - -sw_error_t -hppe_in_acl_meter_cfg_tbl_exceed_pri_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - union in_acl_meter_cfg_tbl_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_in_acl_meter_cfg_tbl_get(dev_id, index, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.exceed_pri = value; - ret = hppe_in_acl_meter_cfg_tbl_set(dev_id, index, ®_val); - return ret; -} - -sw_error_t -hppe_in_acl_meter_cfg_tbl_exceed_chg_pri_cmd_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union in_acl_meter_cfg_tbl_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_in_acl_meter_cfg_tbl_get(dev_id, index, ®_val); - *value = reg_val.bf.exceed_chg_pri_cmd; - return ret; -} - -sw_error_t -hppe_in_acl_meter_cfg_tbl_exceed_chg_pri_cmd_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - union in_acl_meter_cfg_tbl_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_in_acl_meter_cfg_tbl_get(dev_id, index, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.exceed_chg_pri_cmd = value; - ret = hppe_in_acl_meter_cfg_tbl_set(dev_id, index, ®_val); - return ret; -} - -sw_error_t -hppe_in_acl_meter_cfg_tbl_exceed_dp_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union in_acl_meter_cfg_tbl_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_in_acl_meter_cfg_tbl_get(dev_id, index, ®_val); - *value = reg_val.bf.exceed_dp; - return ret; -} - -sw_error_t -hppe_in_acl_meter_cfg_tbl_exceed_dp_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - union in_acl_meter_cfg_tbl_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_in_acl_meter_cfg_tbl_get(dev_id, index, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.exceed_dp = value; - ret = hppe_in_acl_meter_cfg_tbl_set(dev_id, index, ®_val); - return ret; -} - -sw_error_t -hppe_in_acl_meter_cfg_tbl_violate_dp_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union in_acl_meter_cfg_tbl_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_in_acl_meter_cfg_tbl_get(dev_id, index, ®_val); - *value = reg_val.bf.violate_dp; - return ret; -} - -sw_error_t -hppe_in_acl_meter_cfg_tbl_violate_dp_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - union in_acl_meter_cfg_tbl_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_in_acl_meter_cfg_tbl_get(dev_id, index, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.violate_dp = value; - ret = hppe_in_acl_meter_cfg_tbl_set(dev_id, index, ®_val); - return ret; -} - -sw_error_t -hppe_in_acl_meter_cfg_tbl_exceed_dei_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union in_acl_meter_cfg_tbl_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_in_acl_meter_cfg_tbl_get(dev_id, index, ®_val); - *value = reg_val.bf.exceed_dei; - return ret; -} - -sw_error_t -hppe_in_acl_meter_cfg_tbl_exceed_dei_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - union in_acl_meter_cfg_tbl_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_in_acl_meter_cfg_tbl_get(dev_id, index, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.exceed_dei = value; - ret = hppe_in_acl_meter_cfg_tbl_set(dev_id, index, ®_val); - return ret; -} - -sw_error_t -hppe_in_acl_meter_cfg_tbl_violate_pri_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union in_acl_meter_cfg_tbl_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_in_acl_meter_cfg_tbl_get(dev_id, index, ®_val); - *value = reg_val.bf.violate_pri_1 << 1 | \ - reg_val.bf.violate_pri_0; - return ret; -} - -sw_error_t -hppe_in_acl_meter_cfg_tbl_violate_pri_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - union in_acl_meter_cfg_tbl_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_in_acl_meter_cfg_tbl_get(dev_id, index, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.violate_pri_1 = value >> 1; - reg_val.bf.violate_pri_0 = value & (((a_uint64_t)1<<1)-1); - ret = hppe_in_acl_meter_cfg_tbl_set(dev_id, index, ®_val); - return ret; -} - -sw_error_t -hppe_in_acl_meter_cfg_tbl_cbs_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union in_acl_meter_cfg_tbl_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_in_acl_meter_cfg_tbl_get(dev_id, index, ®_val); - *value = reg_val.bf.cbs; - return ret; -} - -sw_error_t -hppe_in_acl_meter_cfg_tbl_cbs_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - union in_acl_meter_cfg_tbl_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_in_acl_meter_cfg_tbl_get(dev_id, index, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.cbs = value; - ret = hppe_in_acl_meter_cfg_tbl_set(dev_id, index, ®_val); - return ret; -} - -sw_error_t -hppe_in_acl_meter_cfg_tbl_violate_chg_dei_cmd_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union in_acl_meter_cfg_tbl_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_in_acl_meter_cfg_tbl_get(dev_id, index, ®_val); - *value = reg_val.bf.violate_chg_dei_cmd; - return ret; -} - -sw_error_t -hppe_in_acl_meter_cfg_tbl_violate_chg_dei_cmd_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - union in_acl_meter_cfg_tbl_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_in_acl_meter_cfg_tbl_get(dev_id, index, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.violate_chg_dei_cmd = value; - ret = hppe_in_acl_meter_cfg_tbl_set(dev_id, index, ®_val); - return ret; -} - -sw_error_t -hppe_in_acl_meter_cfg_tbl_violate_chg_pcp_cmd_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union in_acl_meter_cfg_tbl_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_in_acl_meter_cfg_tbl_get(dev_id, index, ®_val); - *value = reg_val.bf.violate_chg_pcp_cmd; - return ret; -} - -sw_error_t -hppe_in_acl_meter_cfg_tbl_violate_chg_pcp_cmd_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - union in_acl_meter_cfg_tbl_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_in_acl_meter_cfg_tbl_get(dev_id, index, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.violate_chg_pcp_cmd = value; - ret = hppe_in_acl_meter_cfg_tbl_set(dev_id, index, ®_val); - return ret; -} - -sw_error_t -hppe_in_acl_meter_cfg_tbl_cir_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union in_acl_meter_cfg_tbl_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_in_acl_meter_cfg_tbl_get(dev_id, index, ®_val); - *value = reg_val.bf.cir_1 << 8 | \ - reg_val.bf.cir_0; - return ret; -} - -sw_error_t -hppe_in_acl_meter_cfg_tbl_cir_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - union in_acl_meter_cfg_tbl_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_in_acl_meter_cfg_tbl_get(dev_id, index, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.cir_1 = value >> 8; - reg_val.bf.cir_0 = value & (((a_uint64_t)1<<8)-1); - ret = hppe_in_acl_meter_cfg_tbl_set(dev_id, index, ®_val); - return ret; -} - -sw_error_t -hppe_in_acl_meter_cfg_tbl_violate_dei_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union in_acl_meter_cfg_tbl_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_in_acl_meter_cfg_tbl_get(dev_id, index, ®_val); - *value = reg_val.bf.violate_dei; - return ret; -} - -sw_error_t -hppe_in_acl_meter_cfg_tbl_violate_dei_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - union in_acl_meter_cfg_tbl_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_in_acl_meter_cfg_tbl_get(dev_id, index, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.violate_dei = value; - ret = hppe_in_acl_meter_cfg_tbl_set(dev_id, index, ®_val); - return ret; -} - -sw_error_t -hppe_in_acl_meter_cfg_tbl_violate_chg_pri_cmd_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union in_acl_meter_cfg_tbl_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_in_acl_meter_cfg_tbl_get(dev_id, index, ®_val); - *value = reg_val.bf.violate_chg_pri_cmd; - return ret; -} - -sw_error_t -hppe_in_acl_meter_cfg_tbl_violate_chg_pri_cmd_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - union in_acl_meter_cfg_tbl_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_in_acl_meter_cfg_tbl_get(dev_id, index, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.violate_chg_pri_cmd = value; - ret = hppe_in_acl_meter_cfg_tbl_set(dev_id, index, ®_val); - return ret; -} - -sw_error_t -hppe_in_acl_meter_cfg_tbl_meter_unit_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union in_acl_meter_cfg_tbl_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_in_acl_meter_cfg_tbl_get(dev_id, index, ®_val); - *value = reg_val.bf.meter_unit; - return ret; -} - -sw_error_t -hppe_in_acl_meter_cfg_tbl_meter_unit_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - union in_acl_meter_cfg_tbl_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_in_acl_meter_cfg_tbl_get(dev_id, index, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.meter_unit = value; - ret = hppe_in_acl_meter_cfg_tbl_set(dev_id, index, ®_val); - return ret; -} - -sw_error_t -hppe_in_acl_meter_cfg_tbl_meter_en_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union in_acl_meter_cfg_tbl_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_in_acl_meter_cfg_tbl_get(dev_id, index, ®_val); - *value = reg_val.bf.meter_en; - return ret; -} - -sw_error_t -hppe_in_acl_meter_cfg_tbl_meter_en_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - union in_acl_meter_cfg_tbl_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_in_acl_meter_cfg_tbl_get(dev_id, index, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.meter_en = value; - ret = hppe_in_acl_meter_cfg_tbl_set(dev_id, index, ®_val); - return ret; -} - -sw_error_t -hppe_in_acl_meter_cfg_tbl_violate_cmd_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union in_acl_meter_cfg_tbl_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_in_acl_meter_cfg_tbl_get(dev_id, index, ®_val); - *value = reg_val.bf.violate_cmd; - return ret; -} - -sw_error_t -hppe_in_acl_meter_cfg_tbl_violate_cmd_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - union in_acl_meter_cfg_tbl_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_in_acl_meter_cfg_tbl_get(dev_id, index, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.violate_cmd = value; - ret = hppe_in_acl_meter_cfg_tbl_set(dev_id, index, ®_val); - return ret; -} - -sw_error_t -hppe_in_acl_meter_cfg_tbl_violate_chg_dp_cmd_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union in_acl_meter_cfg_tbl_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_in_acl_meter_cfg_tbl_get(dev_id, index, ®_val); - *value = reg_val.bf.violate_chg_dp_cmd; - return ret; -} - -sw_error_t -hppe_in_acl_meter_cfg_tbl_violate_chg_dp_cmd_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - union in_acl_meter_cfg_tbl_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_in_acl_meter_cfg_tbl_get(dev_id, index, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.violate_chg_dp_cmd = value; - ret = hppe_in_acl_meter_cfg_tbl_set(dev_id, index, ®_val); - return ret; -} - -sw_error_t -hppe_in_acl_meter_cfg_tbl_eir_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union in_acl_meter_cfg_tbl_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_in_acl_meter_cfg_tbl_get(dev_id, index, ®_val); - *value = reg_val.bf.eir_1 << 6 | \ - reg_val.bf.eir_0; - return ret; -} - -sw_error_t -hppe_in_acl_meter_cfg_tbl_eir_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - union in_acl_meter_cfg_tbl_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_in_acl_meter_cfg_tbl_get(dev_id, index, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.eir_1 = value >> 6; - reg_val.bf.eir_0 = value & (((a_uint64_t)1<<6)-1); - ret = hppe_in_acl_meter_cfg_tbl_set(dev_id, index, ®_val); - return ret; -} - -sw_error_t -hppe_in_acl_meter_cfg_tbl_exceed_chg_dp_cmd_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union in_acl_meter_cfg_tbl_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_in_acl_meter_cfg_tbl_get(dev_id, index, ®_val); - *value = reg_val.bf.exceed_chg_dp_cmd; - return ret; -} - -sw_error_t -hppe_in_acl_meter_cfg_tbl_exceed_chg_dp_cmd_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - union in_acl_meter_cfg_tbl_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_in_acl_meter_cfg_tbl_get(dev_id, index, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.exceed_chg_dp_cmd = value; - ret = hppe_in_acl_meter_cfg_tbl_set(dev_id, index, ®_val); - return ret; -} - -sw_error_t -hppe_in_acl_meter_cfg_tbl_exceed_chg_dei_cmd_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union in_acl_meter_cfg_tbl_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_in_acl_meter_cfg_tbl_get(dev_id, index, ®_val); - *value = reg_val.bf.exceed_chg_dei_cmd; - return ret; -} - -sw_error_t -hppe_in_acl_meter_cfg_tbl_exceed_chg_dei_cmd_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - union in_acl_meter_cfg_tbl_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_in_acl_meter_cfg_tbl_get(dev_id, index, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.exceed_chg_dei_cmd = value; - ret = hppe_in_acl_meter_cfg_tbl_set(dev_id, index, ®_val); - return ret; -} - -sw_error_t -hppe_in_acl_meter_cfg_tbl_exceed_pcp_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union in_acl_meter_cfg_tbl_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_in_acl_meter_cfg_tbl_get(dev_id, index, ®_val); - *value = reg_val.bf.exceed_pcp; - return ret; -} - -sw_error_t -hppe_in_acl_meter_cfg_tbl_exceed_pcp_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - union in_acl_meter_cfg_tbl_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_in_acl_meter_cfg_tbl_get(dev_id, index, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.exceed_pcp = value; - ret = hppe_in_acl_meter_cfg_tbl_set(dev_id, index, ®_val); - return ret; -} - -sw_error_t -hppe_in_acl_meter_cfg_tbl_violate_pcp_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union in_acl_meter_cfg_tbl_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_in_acl_meter_cfg_tbl_get(dev_id, index, ®_val); - *value = reg_val.bf.violate_pcp; - return ret; -} - -sw_error_t -hppe_in_acl_meter_cfg_tbl_violate_pcp_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - union in_acl_meter_cfg_tbl_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_in_acl_meter_cfg_tbl_get(dev_id, index, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.violate_pcp = value; - ret = hppe_in_acl_meter_cfg_tbl_set(dev_id, index, ®_val); - return ret; -} - -sw_error_t -hppe_in_acl_meter_cfg_tbl_token_unit_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union in_acl_meter_cfg_tbl_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_in_acl_meter_cfg_tbl_get(dev_id, index, ®_val); - *value = reg_val.bf.token_unit; - return ret; -} - -sw_error_t -hppe_in_acl_meter_cfg_tbl_token_unit_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - union in_acl_meter_cfg_tbl_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_in_acl_meter_cfg_tbl_get(dev_id, index, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.token_unit = value; - ret = hppe_in_acl_meter_cfg_tbl_set(dev_id, index, ®_val); - return ret; -} - -sw_error_t -hppe_in_acl_meter_cfg_tbl_coupling_flag_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union in_acl_meter_cfg_tbl_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_in_acl_meter_cfg_tbl_get(dev_id, index, ®_val); - *value = reg_val.bf.coupling_flag; - return ret; -} - -sw_error_t -hppe_in_acl_meter_cfg_tbl_coupling_flag_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - union in_acl_meter_cfg_tbl_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_in_acl_meter_cfg_tbl_get(dev_id, index, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.coupling_flag = value; - ret = hppe_in_acl_meter_cfg_tbl_set(dev_id, index, ®_val); - return ret; -} - -sw_error_t -hppe_in_acl_meter_cfg_tbl_ebs_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union in_acl_meter_cfg_tbl_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_in_acl_meter_cfg_tbl_get(dev_id, index, ®_val); - *value = reg_val.bf.ebs; - return ret; -} - -sw_error_t -hppe_in_acl_meter_cfg_tbl_ebs_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - union in_acl_meter_cfg_tbl_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_in_acl_meter_cfg_tbl_get(dev_id, index, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.ebs = value; - ret = hppe_in_acl_meter_cfg_tbl_set(dev_id, index, ®_val); - return ret; -} - -sw_error_t -hppe_in_acl_meter_crdt_tbl_c_crdt_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union in_acl_meter_crdt_tbl_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_in_acl_meter_crdt_tbl_get(dev_id, index, ®_val); - *value = reg_val.bf.c_crdt; - return ret; -} - -sw_error_t -hppe_in_acl_meter_crdt_tbl_c_crdt_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - union in_acl_meter_crdt_tbl_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_in_acl_meter_crdt_tbl_get(dev_id, index, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.c_crdt = value; - ret = hppe_in_acl_meter_crdt_tbl_set(dev_id, index, ®_val); - return ret; -} - -sw_error_t -hppe_in_acl_meter_crdt_tbl_e_crdt_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union in_acl_meter_crdt_tbl_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_in_acl_meter_crdt_tbl_get(dev_id, index, ®_val); - *value = reg_val.bf.e_crdt; - return ret; -} - -sw_error_t -hppe_in_acl_meter_crdt_tbl_e_crdt_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - union in_acl_meter_crdt_tbl_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_in_acl_meter_crdt_tbl_get(dev_id, index, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.e_crdt = value; - ret = hppe_in_acl_meter_crdt_tbl_set(dev_id, index, ®_val); - return ret; -} - -sw_error_t -hppe_in_port_meter_cfg_tbl_meter_mode_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union in_port_meter_cfg_tbl_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_in_port_meter_cfg_tbl_get(dev_id, index, ®_val); - *value = reg_val.bf.meter_mode; - return ret; -} - -sw_error_t -hppe_in_port_meter_cfg_tbl_meter_mode_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - union in_port_meter_cfg_tbl_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_in_port_meter_cfg_tbl_get(dev_id, index, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.meter_mode = value; - ret = hppe_in_port_meter_cfg_tbl_set(dev_id, index, ®_val); - return ret; -} - -sw_error_t -hppe_in_port_meter_cfg_tbl_color_mode_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union in_port_meter_cfg_tbl_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_in_port_meter_cfg_tbl_get(dev_id, index, ®_val); - *value = reg_val.bf.color_mode; - return ret; -} - -sw_error_t -hppe_in_port_meter_cfg_tbl_color_mode_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - union in_port_meter_cfg_tbl_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_in_port_meter_cfg_tbl_get(dev_id, index, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.color_mode = value; - ret = hppe_in_port_meter_cfg_tbl_set(dev_id, index, ®_val); - return ret; -} - -sw_error_t -hppe_in_port_meter_cfg_tbl_exceed_chg_pcp_cmd_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union in_port_meter_cfg_tbl_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_in_port_meter_cfg_tbl_get(dev_id, index, ®_val); - *value = reg_val.bf.exceed_chg_pcp_cmd; - return ret; -} - -sw_error_t -hppe_in_port_meter_cfg_tbl_exceed_chg_pcp_cmd_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - union in_port_meter_cfg_tbl_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_in_port_meter_cfg_tbl_get(dev_id, index, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.exceed_chg_pcp_cmd = value; - ret = hppe_in_port_meter_cfg_tbl_set(dev_id, index, ®_val); - return ret; -} - -sw_error_t -hppe_in_port_meter_cfg_tbl_exceed_pri_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union in_port_meter_cfg_tbl_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_in_port_meter_cfg_tbl_get(dev_id, index, ®_val); - *value = reg_val.bf.exceed_pri; - return ret; -} - -sw_error_t -hppe_in_port_meter_cfg_tbl_exceed_pri_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - union in_port_meter_cfg_tbl_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_in_port_meter_cfg_tbl_get(dev_id, index, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.exceed_pri = value; - ret = hppe_in_port_meter_cfg_tbl_set(dev_id, index, ®_val); - return ret; -} - -sw_error_t -hppe_in_port_meter_cfg_tbl_exceed_chg_pri_cmd_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union in_port_meter_cfg_tbl_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_in_port_meter_cfg_tbl_get(dev_id, index, ®_val); - *value = reg_val.bf.exceed_chg_pri_cmd; - return ret; -} - -sw_error_t -hppe_in_port_meter_cfg_tbl_exceed_chg_pri_cmd_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - union in_port_meter_cfg_tbl_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_in_port_meter_cfg_tbl_get(dev_id, index, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.exceed_chg_pri_cmd = value; - ret = hppe_in_port_meter_cfg_tbl_set(dev_id, index, ®_val); - return ret; -} - -sw_error_t -hppe_in_port_meter_cfg_tbl_exceed_dp_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union in_port_meter_cfg_tbl_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_in_port_meter_cfg_tbl_get(dev_id, index, ®_val); - *value = reg_val.bf.exceed_dp; - return ret; -} - -sw_error_t -hppe_in_port_meter_cfg_tbl_exceed_dp_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - union in_port_meter_cfg_tbl_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_in_port_meter_cfg_tbl_get(dev_id, index, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.exceed_dp = value; - ret = hppe_in_port_meter_cfg_tbl_set(dev_id, index, ®_val); - return ret; -} - -sw_error_t -hppe_in_port_meter_cfg_tbl_violate_dp_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union in_port_meter_cfg_tbl_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_in_port_meter_cfg_tbl_get(dev_id, index, ®_val); - *value = reg_val.bf.violate_dp; - return ret; -} - -sw_error_t -hppe_in_port_meter_cfg_tbl_violate_dp_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - union in_port_meter_cfg_tbl_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_in_port_meter_cfg_tbl_get(dev_id, index, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.violate_dp = value; - ret = hppe_in_port_meter_cfg_tbl_set(dev_id, index, ®_val); - return ret; -} - -sw_error_t -hppe_in_port_meter_cfg_tbl_exceed_dei_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union in_port_meter_cfg_tbl_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_in_port_meter_cfg_tbl_get(dev_id, index, ®_val); - *value = reg_val.bf.exceed_dei; - return ret; -} - -sw_error_t -hppe_in_port_meter_cfg_tbl_exceed_dei_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - union in_port_meter_cfg_tbl_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_in_port_meter_cfg_tbl_get(dev_id, index, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.exceed_dei = value; - ret = hppe_in_port_meter_cfg_tbl_set(dev_id, index, ®_val); - return ret; -} - -sw_error_t -hppe_in_port_meter_cfg_tbl_violate_pri_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union in_port_meter_cfg_tbl_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_in_port_meter_cfg_tbl_get(dev_id, index, ®_val); - *value = reg_val.bf.violate_pri; - return ret; -} - -sw_error_t -hppe_in_port_meter_cfg_tbl_violate_pri_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - union in_port_meter_cfg_tbl_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_in_port_meter_cfg_tbl_get(dev_id, index, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.violate_pri = value; - ret = hppe_in_port_meter_cfg_tbl_set(dev_id, index, ®_val); - return ret; -} - -sw_error_t -hppe_in_port_meter_cfg_tbl_cbs_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union in_port_meter_cfg_tbl_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_in_port_meter_cfg_tbl_get(dev_id, index, ®_val); - *value = reg_val.bf.cbs; - return ret; -} - -sw_error_t -hppe_in_port_meter_cfg_tbl_cbs_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - union in_port_meter_cfg_tbl_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_in_port_meter_cfg_tbl_get(dev_id, index, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.cbs = value; - ret = hppe_in_port_meter_cfg_tbl_set(dev_id, index, ®_val); - return ret; -} - -sw_error_t -hppe_in_port_meter_cfg_tbl_violate_chg_dei_cmd_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union in_port_meter_cfg_tbl_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_in_port_meter_cfg_tbl_get(dev_id, index, ®_val); - *value = reg_val.bf.violate_chg_dei_cmd; - return ret; -} - -sw_error_t -hppe_in_port_meter_cfg_tbl_violate_chg_dei_cmd_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - union in_port_meter_cfg_tbl_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_in_port_meter_cfg_tbl_get(dev_id, index, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.violate_chg_dei_cmd = value; - ret = hppe_in_port_meter_cfg_tbl_set(dev_id, index, ®_val); - return ret; -} - -sw_error_t -hppe_in_port_meter_cfg_tbl_violate_chg_pcp_cmd_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union in_port_meter_cfg_tbl_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_in_port_meter_cfg_tbl_get(dev_id, index, ®_val); - *value = reg_val.bf.violate_chg_pcp_cmd; - return ret; -} - -sw_error_t -hppe_in_port_meter_cfg_tbl_violate_chg_pcp_cmd_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - union in_port_meter_cfg_tbl_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_in_port_meter_cfg_tbl_get(dev_id, index, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.violate_chg_pcp_cmd = value; - ret = hppe_in_port_meter_cfg_tbl_set(dev_id, index, ®_val); - return ret; -} - -sw_error_t -hppe_in_port_meter_cfg_tbl_cir_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union in_port_meter_cfg_tbl_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_in_port_meter_cfg_tbl_get(dev_id, index, ®_val); - *value = reg_val.bf.cir_1 << 3 | \ - reg_val.bf.cir_0; - return ret; -} - -sw_error_t -hppe_in_port_meter_cfg_tbl_cir_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - union in_port_meter_cfg_tbl_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_in_port_meter_cfg_tbl_get(dev_id, index, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.cir_1 = value >> 3; - reg_val.bf.cir_0 = value & (((a_uint64_t)1<<3)-1); - ret = hppe_in_port_meter_cfg_tbl_set(dev_id, index, ®_val); - return ret; -} - -sw_error_t -hppe_in_port_meter_cfg_tbl_violate_dei_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union in_port_meter_cfg_tbl_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_in_port_meter_cfg_tbl_get(dev_id, index, ®_val); - *value = reg_val.bf.violate_dei; - return ret; -} - -sw_error_t -hppe_in_port_meter_cfg_tbl_violate_dei_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - union in_port_meter_cfg_tbl_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_in_port_meter_cfg_tbl_get(dev_id, index, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.violate_dei = value; - ret = hppe_in_port_meter_cfg_tbl_set(dev_id, index, ®_val); - return ret; -} - -sw_error_t -hppe_in_port_meter_cfg_tbl_violate_chg_pri_cmd_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union in_port_meter_cfg_tbl_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_in_port_meter_cfg_tbl_get(dev_id, index, ®_val); - *value = reg_val.bf.violate_chg_pri_cmd; - return ret; -} - -sw_error_t -hppe_in_port_meter_cfg_tbl_violate_chg_pri_cmd_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - union in_port_meter_cfg_tbl_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_in_port_meter_cfg_tbl_get(dev_id, index, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.violate_chg_pri_cmd = value; - ret = hppe_in_port_meter_cfg_tbl_set(dev_id, index, ®_val); - return ret; -} - -sw_error_t -hppe_in_port_meter_cfg_tbl_meter_unit_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union in_port_meter_cfg_tbl_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_in_port_meter_cfg_tbl_get(dev_id, index, ®_val); - *value = reg_val.bf.meter_unit; - return ret; -} - -sw_error_t -hppe_in_port_meter_cfg_tbl_meter_unit_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - union in_port_meter_cfg_tbl_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_in_port_meter_cfg_tbl_get(dev_id, index, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.meter_unit = value; - ret = hppe_in_port_meter_cfg_tbl_set(dev_id, index, ®_val); - return ret; -} - -sw_error_t -hppe_in_port_meter_cfg_tbl_meter_en_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union in_port_meter_cfg_tbl_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_in_port_meter_cfg_tbl_get(dev_id, index, ®_val); - *value = reg_val.bf.meter_en; - return ret; -} - -sw_error_t -hppe_in_port_meter_cfg_tbl_meter_en_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - union in_port_meter_cfg_tbl_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_in_port_meter_cfg_tbl_get(dev_id, index, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.meter_en = value; - ret = hppe_in_port_meter_cfg_tbl_set(dev_id, index, ®_val); - return ret; -} - -sw_error_t -hppe_in_port_meter_cfg_tbl_violate_cmd_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union in_port_meter_cfg_tbl_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_in_port_meter_cfg_tbl_get(dev_id, index, ®_val); - *value = reg_val.bf.violate_cmd; - return ret; -} - -sw_error_t -hppe_in_port_meter_cfg_tbl_violate_cmd_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - union in_port_meter_cfg_tbl_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_in_port_meter_cfg_tbl_get(dev_id, index, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.violate_cmd = value; - ret = hppe_in_port_meter_cfg_tbl_set(dev_id, index, ®_val); - return ret; -} - -sw_error_t -hppe_in_port_meter_cfg_tbl_violate_chg_dp_cmd_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union in_port_meter_cfg_tbl_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_in_port_meter_cfg_tbl_get(dev_id, index, ®_val); - *value = reg_val.bf.violate_chg_dp_cmd; - return ret; -} - -sw_error_t -hppe_in_port_meter_cfg_tbl_violate_chg_dp_cmd_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - union in_port_meter_cfg_tbl_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_in_port_meter_cfg_tbl_get(dev_id, index, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.violate_chg_dp_cmd = value; - ret = hppe_in_port_meter_cfg_tbl_set(dev_id, index, ®_val); - return ret; -} - -sw_error_t -hppe_in_port_meter_cfg_tbl_eir_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union in_port_meter_cfg_tbl_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_in_port_meter_cfg_tbl_get(dev_id, index, ®_val); - *value = reg_val.bf.eir_1 << 1 | \ - reg_val.bf.eir_0; - return ret; -} - -sw_error_t -hppe_in_port_meter_cfg_tbl_eir_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - union in_port_meter_cfg_tbl_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_in_port_meter_cfg_tbl_get(dev_id, index, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.eir_1 = value >> 1; - reg_val.bf.eir_0 = value & (((a_uint64_t)1<<1)-1); - ret = hppe_in_port_meter_cfg_tbl_set(dev_id, index, ®_val); - return ret; -} - -sw_error_t -hppe_in_port_meter_cfg_tbl_exceed_chg_dp_cmd_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union in_port_meter_cfg_tbl_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_in_port_meter_cfg_tbl_get(dev_id, index, ®_val); - *value = reg_val.bf.exceed_chg_dp_cmd; - return ret; -} - -sw_error_t -hppe_in_port_meter_cfg_tbl_exceed_chg_dp_cmd_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - union in_port_meter_cfg_tbl_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_in_port_meter_cfg_tbl_get(dev_id, index, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.exceed_chg_dp_cmd = value; - ret = hppe_in_port_meter_cfg_tbl_set(dev_id, index, ®_val); - return ret; -} - -sw_error_t -hppe_in_port_meter_cfg_tbl_exceed_chg_dei_cmd_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union in_port_meter_cfg_tbl_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_in_port_meter_cfg_tbl_get(dev_id, index, ®_val); - *value = reg_val.bf.exceed_chg_dei_cmd; - return ret; -} - -sw_error_t -hppe_in_port_meter_cfg_tbl_exceed_chg_dei_cmd_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - union in_port_meter_cfg_tbl_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_in_port_meter_cfg_tbl_get(dev_id, index, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.exceed_chg_dei_cmd = value; - ret = hppe_in_port_meter_cfg_tbl_set(dev_id, index, ®_val); - return ret; -} - -sw_error_t -hppe_in_port_meter_cfg_tbl_exceed_pcp_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union in_port_meter_cfg_tbl_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_in_port_meter_cfg_tbl_get(dev_id, index, ®_val); - *value = reg_val.bf.exceed_pcp; - return ret; -} - -sw_error_t -hppe_in_port_meter_cfg_tbl_exceed_pcp_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - union in_port_meter_cfg_tbl_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_in_port_meter_cfg_tbl_get(dev_id, index, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.exceed_pcp = value; - ret = hppe_in_port_meter_cfg_tbl_set(dev_id, index, ®_val); - return ret; -} - -sw_error_t -hppe_in_port_meter_cfg_tbl_violate_pcp_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union in_port_meter_cfg_tbl_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_in_port_meter_cfg_tbl_get(dev_id, index, ®_val); - *value = reg_val.bf.violate_pcp; - return ret; -} - -sw_error_t -hppe_in_port_meter_cfg_tbl_violate_pcp_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - union in_port_meter_cfg_tbl_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_in_port_meter_cfg_tbl_get(dev_id, index, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.violate_pcp = value; - ret = hppe_in_port_meter_cfg_tbl_set(dev_id, index, ®_val); - return ret; -} - -sw_error_t -hppe_in_port_meter_cfg_tbl_token_unit_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union in_port_meter_cfg_tbl_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_in_port_meter_cfg_tbl_get(dev_id, index, ®_val); - *value = reg_val.bf.token_unit; - return ret; -} - -sw_error_t -hppe_in_port_meter_cfg_tbl_token_unit_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - union in_port_meter_cfg_tbl_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_in_port_meter_cfg_tbl_get(dev_id, index, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.token_unit = value; - ret = hppe_in_port_meter_cfg_tbl_set(dev_id, index, ®_val); - return ret; -} - -sw_error_t -hppe_in_port_meter_cfg_tbl_coupling_flag_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union in_port_meter_cfg_tbl_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_in_port_meter_cfg_tbl_get(dev_id, index, ®_val); - *value = reg_val.bf.coupling_flag; - return ret; -} - -sw_error_t -hppe_in_port_meter_cfg_tbl_coupling_flag_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - union in_port_meter_cfg_tbl_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_in_port_meter_cfg_tbl_get(dev_id, index, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.coupling_flag = value; - ret = hppe_in_port_meter_cfg_tbl_set(dev_id, index, ®_val); - return ret; -} - -sw_error_t -hppe_in_port_meter_cfg_tbl_meter_flag_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union in_port_meter_cfg_tbl_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_in_port_meter_cfg_tbl_get(dev_id, index, ®_val); - *value = reg_val.bf.meter_flag; - return ret; -} - -sw_error_t -hppe_in_port_meter_cfg_tbl_meter_flag_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - union in_port_meter_cfg_tbl_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_in_port_meter_cfg_tbl_get(dev_id, index, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.meter_flag = value; - ret = hppe_in_port_meter_cfg_tbl_set(dev_id, index, ®_val); - return ret; -} - -sw_error_t -hppe_in_port_meter_cfg_tbl_ebs_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union in_port_meter_cfg_tbl_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_in_port_meter_cfg_tbl_get(dev_id, index, ®_val); - *value = reg_val.bf.ebs; - return ret; -} - -sw_error_t -hppe_in_port_meter_cfg_tbl_ebs_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - union in_port_meter_cfg_tbl_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_in_port_meter_cfg_tbl_get(dev_id, index, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.ebs = value; - ret = hppe_in_port_meter_cfg_tbl_set(dev_id, index, ®_val); - return ret; -} - -sw_error_t -hppe_in_port_meter_crdt_tbl_c_crdt_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union in_port_meter_crdt_tbl_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_in_port_meter_crdt_tbl_get(dev_id, index, ®_val); - *value = reg_val.bf.c_crdt; - return ret; -} - -sw_error_t -hppe_in_port_meter_crdt_tbl_c_crdt_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - union in_port_meter_crdt_tbl_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_in_port_meter_crdt_tbl_get(dev_id, index, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.c_crdt = value; - ret = hppe_in_port_meter_crdt_tbl_set(dev_id, index, ®_val); - return ret; -} - -sw_error_t -hppe_in_port_meter_crdt_tbl_e_crdt_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union in_port_meter_crdt_tbl_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_in_port_meter_crdt_tbl_get(dev_id, index, ®_val); - *value = reg_val.bf.e_crdt; - return ret; -} - -sw_error_t -hppe_in_port_meter_crdt_tbl_e_crdt_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - union in_port_meter_crdt_tbl_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_in_port_meter_crdt_tbl_get(dev_id, index, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.e_crdt = value; - ret = hppe_in_port_meter_crdt_tbl_set(dev_id, index, ®_val); - return ret; -} - -sw_error_t -hppe_in_port_meter_cnt_tbl_byte_cnt_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint64_t *value) -{ - union in_port_meter_cnt_tbl_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_in_port_meter_cnt_tbl_get(dev_id, index, ®_val); - *value = (a_uint64_t)reg_val.bf.byte_cnt_1 << 32 | \ - reg_val.bf.byte_cnt_0; - return ret; -} - -sw_error_t -hppe_in_port_meter_cnt_tbl_byte_cnt_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint64_t value) -{ - union in_port_meter_cnt_tbl_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_in_port_meter_cnt_tbl_get(dev_id, index, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.byte_cnt_1 = value >> 32; - reg_val.bf.byte_cnt_0 = value & (((a_uint64_t)1<<32)-1); - ret = hppe_in_port_meter_cnt_tbl_set(dev_id, index, ®_val); - return ret; -} - -sw_error_t -hppe_in_port_meter_cnt_tbl_pkt_cnt_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union in_port_meter_cnt_tbl_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_in_port_meter_cnt_tbl_get(dev_id, index, ®_val); - *value = reg_val.bf.pkt_cnt; - return ret; -} - -sw_error_t -hppe_in_port_meter_cnt_tbl_pkt_cnt_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - union in_port_meter_cnt_tbl_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_in_port_meter_cnt_tbl_get(dev_id, index, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.pkt_cnt = value; - ret = hppe_in_port_meter_cnt_tbl_set(dev_id, index, ®_val); - return ret; -} - -sw_error_t -hppe_in_acl_meter_cnt_tbl_byte_cnt_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint64_t *value) -{ - union in_acl_meter_cnt_tbl_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_in_acl_meter_cnt_tbl_get(dev_id, index, ®_val); - *value = (a_uint64_t)reg_val.bf.byte_cnt_1 << 32 | \ - reg_val.bf.byte_cnt_0; - return ret; -} - -sw_error_t -hppe_in_acl_meter_cnt_tbl_byte_cnt_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint64_t value) -{ - union in_acl_meter_cnt_tbl_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_in_acl_meter_cnt_tbl_get(dev_id, index, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.byte_cnt_1 = value >> 32; - reg_val.bf.byte_cnt_0 = value & (((a_uint64_t)1<<32)-1); - ret = hppe_in_acl_meter_cnt_tbl_set(dev_id, index, ®_val); - return ret; -} - -sw_error_t -hppe_in_acl_meter_cnt_tbl_pkt_cnt_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union in_acl_meter_cnt_tbl_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_in_acl_meter_cnt_tbl_get(dev_id, index, ®_val); - *value = reg_val.bf.pkt_cnt; - return ret; -} - -sw_error_t -hppe_in_acl_meter_cnt_tbl_pkt_cnt_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - union in_acl_meter_cnt_tbl_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_in_acl_meter_cnt_tbl_get(dev_id, index, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.pkt_cnt = value; - ret = hppe_in_acl_meter_cnt_tbl_set(dev_id, index, ®_val); - return ret; -} - -sw_error_t -hppe_pc_global_cnt_tbl_byte_cnt_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint64_t *value) -{ - union pc_global_cnt_tbl_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_pc_global_cnt_tbl_get(dev_id, index, ®_val); - *value = (a_uint64_t)reg_val.bf.byte_cnt_1 << 32 | \ - reg_val.bf.byte_cnt_0; - return ret; -} - -sw_error_t -hppe_pc_global_cnt_tbl_byte_cnt_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint64_t value) -{ - union pc_global_cnt_tbl_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_pc_global_cnt_tbl_get(dev_id, index, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.byte_cnt_1 = value >> 32; - reg_val.bf.byte_cnt_0 = value & (((a_uint64_t)1<<32)-1); - ret = hppe_pc_global_cnt_tbl_set(dev_id, index, ®_val); - return ret; -} - -sw_error_t -hppe_pc_global_cnt_tbl_pkt_cnt_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union pc_global_cnt_tbl_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_pc_global_cnt_tbl_get(dev_id, index, ®_val); - *value = reg_val.bf.pkt_cnt; - return ret; -} - -sw_error_t -hppe_pc_global_cnt_tbl_pkt_cnt_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - union pc_global_cnt_tbl_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_pc_global_cnt_tbl_get(dev_id, index, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.pkt_cnt = value; - ret = hppe_pc_global_cnt_tbl_set(dev_id, index, ®_val); - return ret; -} - -sw_error_t -hppe_drop_cpu_cnt_tbl_byte_cnt_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint64_t *value) -{ - union drop_cpu_cnt_tbl_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_drop_cpu_cnt_tbl_get(dev_id, index, ®_val); - *value = (a_uint64_t)reg_val.bf.byte_cnt_1 << 32 | \ - reg_val.bf.byte_cnt_0; - return ret; -} - -sw_error_t -hppe_drop_cpu_cnt_tbl_byte_cnt_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint64_t value) -{ - union drop_cpu_cnt_tbl_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_drop_cpu_cnt_tbl_get(dev_id, index, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.byte_cnt_1 = value >> 32; - reg_val.bf.byte_cnt_0 = value & (((a_uint64_t)1<<32)-1); - ret = hppe_drop_cpu_cnt_tbl_set(dev_id, index, ®_val); - return ret; -} - -sw_error_t -hppe_drop_cpu_cnt_tbl_pkt_cnt_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union drop_cpu_cnt_tbl_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_drop_cpu_cnt_tbl_get(dev_id, index, ®_val); - *value = reg_val.bf.pkt_cnt; - return ret; -} - -sw_error_t -hppe_drop_cpu_cnt_tbl_pkt_cnt_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - union drop_cpu_cnt_tbl_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_drop_cpu_cnt_tbl_get(dev_id, index, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.pkt_cnt = value; - ret = hppe_drop_cpu_cnt_tbl_set(dev_id, index, ®_val); - return ret; -} - -sw_error_t -hppe_port_tx_drop_cnt_tbl_tx_drop_byte_cnt_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint64_t *value) -{ - union port_tx_drop_cnt_tbl_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_port_tx_drop_cnt_tbl_get(dev_id, index, ®_val); - *value = (a_uint64_t)reg_val.bf.tx_drop_byte_cnt_1 << 32 | \ - reg_val.bf.tx_drop_byte_cnt_0; - return ret; -} - -sw_error_t -hppe_port_tx_drop_cnt_tbl_tx_drop_byte_cnt_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint64_t value) -{ - union port_tx_drop_cnt_tbl_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_port_tx_drop_cnt_tbl_get(dev_id, index, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.tx_drop_byte_cnt_1 = value >> 32; - reg_val.bf.tx_drop_byte_cnt_0 = value & (((a_uint64_t)1<<32)-1); - ret = hppe_port_tx_drop_cnt_tbl_set(dev_id, index, ®_val); - return ret; -} - -sw_error_t -hppe_port_tx_drop_cnt_tbl_tx_drop_pkt_cnt_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union port_tx_drop_cnt_tbl_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_port_tx_drop_cnt_tbl_get(dev_id, index, ®_val); - *value = reg_val.bf.tx_drop_pkt_cnt; - return ret; -} - -sw_error_t -hppe_port_tx_drop_cnt_tbl_tx_drop_pkt_cnt_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - union port_tx_drop_cnt_tbl_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_port_tx_drop_cnt_tbl_get(dev_id, index, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.tx_drop_pkt_cnt = value; - ret = hppe_port_tx_drop_cnt_tbl_set(dev_id, index, ®_val); - return ret; -} - -sw_error_t -hppe_vp_tx_drop_cnt_tbl_tx_drop_byte_cnt_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint64_t *value) -{ - union vp_tx_drop_cnt_tbl_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_vp_tx_drop_cnt_tbl_get(dev_id, index, ®_val); - *value = (a_uint64_t)reg_val.bf.tx_drop_byte_cnt_1 << 32 | \ - reg_val.bf.tx_drop_byte_cnt_0; - return ret; -} - -sw_error_t -hppe_vp_tx_drop_cnt_tbl_tx_drop_byte_cnt_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint64_t value) -{ - union vp_tx_drop_cnt_tbl_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_vp_tx_drop_cnt_tbl_get(dev_id, index, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.tx_drop_byte_cnt_1 = value >> 32; - reg_val.bf.tx_drop_byte_cnt_0 = value & (((a_uint64_t)1<<32)-1); - ret = hppe_vp_tx_drop_cnt_tbl_set(dev_id, index, ®_val); - return ret; -} - -sw_error_t -hppe_vp_tx_drop_cnt_tbl_tx_drop_pkt_cnt_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union vp_tx_drop_cnt_tbl_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_vp_tx_drop_cnt_tbl_get(dev_id, index, ®_val); - *value = reg_val.bf.tx_drop_pkt_cnt; - return ret; -} - -sw_error_t -hppe_vp_tx_drop_cnt_tbl_tx_drop_pkt_cnt_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - union vp_tx_drop_cnt_tbl_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_vp_tx_drop_cnt_tbl_get(dev_id, index, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.tx_drop_pkt_cnt = value; - ret = hppe_vp_tx_drop_cnt_tbl_set(dev_id, index, ®_val); - return ret; -} - -sw_error_t -hppe_vlan_dev_cnt_tbl_rx_byte_cnt_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint64_t *value) -{ - union vlan_dev_cnt_tbl_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_vlan_dev_cnt_tbl_get(dev_id, index, ®_val); - *value = (a_uint64_t)reg_val.bf.rx_byte_cnt_1 << 32 | \ - reg_val.bf.rx_byte_cnt_0; - return ret; -} - -sw_error_t -hppe_vlan_dev_cnt_tbl_rx_byte_cnt_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint64_t value) -{ - union vlan_dev_cnt_tbl_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_vlan_dev_cnt_tbl_get(dev_id, index, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.rx_byte_cnt_1 = value >> 32; - reg_val.bf.rx_byte_cnt_0 = value & (((a_uint64_t)1<<32)-1); - ret = hppe_vlan_dev_cnt_tbl_set(dev_id, index, ®_val); - return ret; -} - -sw_error_t -hppe_vlan_dev_cnt_tbl_rx_pkt_cnt_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union vlan_dev_cnt_tbl_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_vlan_dev_cnt_tbl_get(dev_id, index, ®_val); - *value = reg_val.bf.rx_pkt_cnt; - return ret; -} - -sw_error_t -hppe_vlan_dev_cnt_tbl_rx_pkt_cnt_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - union vlan_dev_cnt_tbl_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_vlan_dev_cnt_tbl_get(dev_id, index, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.rx_pkt_cnt = value; - ret = hppe_vlan_dev_cnt_tbl_set(dev_id, index, ®_val); - return ret; -} -#endif diff --git a/feeds/ipq807x/qca-ssdk/src/src/hsl/hppe/hppe_portctrl.c b/feeds/ipq807x/qca-ssdk/src/src/hsl/hppe/hppe_portctrl.c deleted file mode 100755 index 3771da908..000000000 --- a/feeds/ipq807x/qca-ssdk/src/src/hsl/hppe/hppe_portctrl.c +++ /dev/null @@ -1,3441 +0,0 @@ -/* - * Copyright (c) 2016-2017, The Linux Foundation. All rights reserved. - * Permission to use, copy, modify, and/or distribute this software for - * any purpose with or without fee is hereby granted, provided that the - * above copyright notice and this permission notice appear in all copies. - * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES - * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR - * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES - * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN - * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT - * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. - */ - - -/** - * @defgroup - * @{ - */ -#include "sw.h" -#include "hsl.h" -#include "hppe_reg_access.h" -#include "hppe_portctrl_reg.h" -#include "hppe_portctrl.h" - -sw_error_t -hppe_mac_enable_get( - a_uint32_t dev_id, - a_uint32_t index, - union mac_enable_u *value) -{ - if (index >= MAC_ENABLE_MAX_ENTRY) - return SW_OUT_OF_RANGE; - return hppe_reg_get( - dev_id, - NSS_MAC_CSR_BASE_ADDR + MAC_ENABLE_ADDRESS + \ - index * MAC_ENABLE_INC, - &value->val); -} - -sw_error_t -hppe_mac_enable_set( - a_uint32_t dev_id, - a_uint32_t index, - union mac_enable_u *value) -{ - return hppe_reg_set( - dev_id, - NSS_MAC_CSR_BASE_ADDR + MAC_ENABLE_ADDRESS + \ - index * MAC_ENABLE_INC, - value->val); -} - -sw_error_t -hppe_mac_speed_get( - a_uint32_t dev_id, - a_uint32_t index, - union mac_speed_u *value) -{ - if (index >= MAC_SPEED_MAX_ENTRY) - return SW_OUT_OF_RANGE; - return hppe_reg_get( - dev_id, - NSS_MAC_CSR_BASE_ADDR + MAC_SPEED_ADDRESS + \ - index * MAC_SPEED_INC, - &value->val); -} - -sw_error_t -hppe_mac_speed_set( - a_uint32_t dev_id, - a_uint32_t index, - union mac_speed_u *value) -{ - return hppe_reg_set( - dev_id, - NSS_MAC_CSR_BASE_ADDR + MAC_SPEED_ADDRESS + \ - index * MAC_SPEED_INC, - value->val); -} -#ifndef IN_PORTCONTROL_MINI -sw_error_t -hppe_gol_mac_addr0_get( - a_uint32_t dev_id, - a_uint32_t index, - union gol_mac_addr0_u *value) -{ - if (index >= GOL_MAC_ADDR0_MAX_ENTRY) - return SW_OUT_OF_RANGE; - return hppe_reg_get( - dev_id, - NSS_MAC_CSR_BASE_ADDR + GOL_MAC_ADDR0_ADDRESS + \ - index * GOL_MAC_ADDR0_INC, - &value->val); -} - -sw_error_t -hppe_gol_mac_addr0_set( - a_uint32_t dev_id, - a_uint32_t index, - union gol_mac_addr0_u *value) -{ - return hppe_reg_set( - dev_id, - NSS_MAC_CSR_BASE_ADDR + GOL_MAC_ADDR0_ADDRESS + \ - index * GOL_MAC_ADDR0_INC, - value->val); -} - -sw_error_t -hppe_gol_mac_addr1_get( - a_uint32_t dev_id, - a_uint32_t index, - union gol_mac_addr1_u *value) -{ - if (index >= GOL_MAC_ADDR1_MAX_ENTRY) - return SW_OUT_OF_RANGE; - return hppe_reg_get( - dev_id, - NSS_MAC_CSR_BASE_ADDR + GOL_MAC_ADDR1_ADDRESS + \ - index * GOL_MAC_ADDR1_INC, - &value->val); -} - -sw_error_t -hppe_gol_mac_addr1_set( - a_uint32_t dev_id, - a_uint32_t index, - union gol_mac_addr1_u *value) -{ - return hppe_reg_set( - dev_id, - NSS_MAC_CSR_BASE_ADDR + GOL_MAC_ADDR1_ADDRESS + \ - index * GOL_MAC_ADDR1_INC, - value->val); -} - -sw_error_t -hppe_mac_ctrl0_get( - a_uint32_t dev_id, - a_uint32_t index, - union mac_ctrl0_u *value) -{ - if (index >= MAC_CTRL0_MAX_ENTRY) - return SW_OUT_OF_RANGE; - return hppe_reg_get( - dev_id, - NSS_MAC_CSR_BASE_ADDR + MAC_CTRL0_ADDRESS + \ - index * MAC_CTRL0_INC, - &value->val); -} - -sw_error_t -hppe_mac_ctrl0_set( - a_uint32_t dev_id, - a_uint32_t index, - union mac_ctrl0_u *value) -{ - return hppe_reg_set( - dev_id, - NSS_MAC_CSR_BASE_ADDR + MAC_CTRL0_ADDRESS + \ - index * MAC_CTRL0_INC, - value->val); -} - -sw_error_t -hppe_mac_ctrl1_get( - a_uint32_t dev_id, - a_uint32_t index, - union mac_ctrl1_u *value) -{ - if (index >= MAC_CTRL1_MAX_ENTRY) - return SW_OUT_OF_RANGE; - return hppe_reg_get( - dev_id, - NSS_MAC_CSR_BASE_ADDR + MAC_CTRL1_ADDRESS + \ - index * MAC_CTRL1_INC, - &value->val); -} - -sw_error_t -hppe_mac_ctrl1_set( - a_uint32_t dev_id, - a_uint32_t index, - union mac_ctrl1_u *value) -{ - return hppe_reg_set( - dev_id, - NSS_MAC_CSR_BASE_ADDR + MAC_CTRL1_ADDRESS + \ - index * MAC_CTRL1_INC, - value->val); -} -#endif -sw_error_t -hppe_mac_ctrl2_get( - a_uint32_t dev_id, - a_uint32_t index, - union mac_ctrl2_u *value) -{ - if (index >= MAC_CTRL2_MAX_ENTRY) - return SW_OUT_OF_RANGE; - return hppe_reg_get( - dev_id, - NSS_MAC_CSR_BASE_ADDR + MAC_CTRL2_ADDRESS + \ - index * MAC_CTRL2_INC, - &value->val); -} - -sw_error_t -hppe_mac_ctrl2_set( - a_uint32_t dev_id, - a_uint32_t index, - union mac_ctrl2_u *value) -{ - return hppe_reg_set( - dev_id, - NSS_MAC_CSR_BASE_ADDR + MAC_CTRL2_ADDRESS + \ - index * MAC_CTRL2_INC, - value->val); -} - -sw_error_t -hppe_mac_dbg_ctrl_get( - a_uint32_t dev_id, - a_uint32_t index, - union mac_dbg_ctrl_u *value) -{ - if (index >= MAC_DBG_CTRL_MAX_ENTRY) - return SW_OUT_OF_RANGE; - return hppe_reg_get( - dev_id, - NSS_MAC_CSR_BASE_ADDR + MAC_DBG_CTRL_ADDRESS + \ - index * MAC_DBG_CTRL_INC, - &value->val); -} - -sw_error_t -hppe_mac_dbg_ctrl_set( - a_uint32_t dev_id, - a_uint32_t index, - union mac_dbg_ctrl_u *value) -{ - return hppe_reg_set( - dev_id, - NSS_MAC_CSR_BASE_ADDR + MAC_DBG_CTRL_ADDRESS + \ - index * MAC_DBG_CTRL_INC, - value->val); -} -#ifndef IN_PORTCONTROL_MINI -sw_error_t -hppe_mac_dbg_addr_get( - a_uint32_t dev_id, - a_uint32_t index, - union mac_dbg_addr_u *value) -{ - if (index >= MAC_DBG_ADDR_MAX_ENTRY) - return SW_OUT_OF_RANGE; - return hppe_reg_get( - dev_id, - NSS_MAC_CSR_BASE_ADDR + MAC_DBG_ADDR_ADDRESS + \ - index * MAC_DBG_ADDR_INC, - &value->val); -} - -sw_error_t -hppe_mac_dbg_addr_set( - a_uint32_t dev_id, - a_uint32_t index, - union mac_dbg_addr_u *value) -{ - return hppe_reg_set( - dev_id, - NSS_MAC_CSR_BASE_ADDR + MAC_DBG_ADDR_ADDRESS + \ - index * MAC_DBG_ADDR_INC, - value->val); -} - -sw_error_t -hppe_mac_dbg_data_get( - a_uint32_t dev_id, - a_uint32_t index, - union mac_dbg_data_u *value) -{ - if (index >= MAC_DBG_DATA_MAX_ENTRY) - return SW_OUT_OF_RANGE; - return hppe_reg_get( - dev_id, - NSS_MAC_CSR_BASE_ADDR + MAC_DBG_DATA_ADDRESS + \ - index * MAC_DBG_DATA_INC, - &value->val); -} - -sw_error_t -hppe_mac_dbg_data_set( - a_uint32_t dev_id, - a_uint32_t index, - union mac_dbg_data_u *value) -{ - return SW_NOT_SUPPORTED; -} -#endif - -sw_error_t -hppe_mac_jumbo_size_get( - a_uint32_t dev_id, - a_uint32_t index, - union mac_jumbo_size_u *value) -{ - if (index >= MAC_JUMBO_SIZE_MAX_ENTRY) - return SW_OUT_OF_RANGE; - return hppe_reg_get( - dev_id, - NSS_MAC_CSR_BASE_ADDR + MAC_JUMBO_SIZE_ADDRESS + \ - index * MAC_JUMBO_SIZE_INC, - &value->val); -} - -sw_error_t -hppe_mac_jumbo_size_set( - a_uint32_t dev_id, - a_uint32_t index, - union mac_jumbo_size_u *value) -{ - return hppe_reg_set( - dev_id, - NSS_MAC_CSR_BASE_ADDR + MAC_JUMBO_SIZE_ADDRESS + \ - index * MAC_JUMBO_SIZE_INC, - value->val); -} - -sw_error_t -hppe_mru_mtu_ctrl_tbl_get( - a_uint32_t dev_id, - a_uint32_t index, - union mru_mtu_ctrl_tbl_u *value) -{ - return hppe_reg_tbl_get( - dev_id, - IPE_L2_BASE_ADDR + MRU_MTU_CTRL_TBL_ADDRESS + \ - index * MRU_MTU_CTRL_TBL_INC, - value->val, - 2); -} - -sw_error_t -hppe_mru_mtu_ctrl_tbl_set( - a_uint32_t dev_id, - a_uint32_t index, - union mru_mtu_ctrl_tbl_u *value) -{ - return hppe_reg_tbl_set( - dev_id, - IPE_L2_BASE_ADDR + MRU_MTU_CTRL_TBL_ADDRESS + \ - index * MRU_MTU_CTRL_TBL_INC, - value->val, - 2); -} - -#if ((!defined(IN_PORTCONTROL_MINI)) || (!defined(IN_MISC_MINI))) -sw_error_t -hppe_mc_mtu_ctrl_tbl_get( - a_uint32_t dev_id, - a_uint32_t index, - union mc_mtu_ctrl_tbl_u *value) -{ - if (index >= MC_MTU_CTRL_TBL_MAX_ENTRY) - return SW_OUT_OF_RANGE; - return hppe_reg_get( - dev_id, - IPE_L2_BASE_ADDR + MC_MTU_CTRL_TBL_ADDRESS + \ - index * MC_MTU_CTRL_TBL_INC, - &value->val); -} - -sw_error_t -hppe_mc_mtu_ctrl_tbl_set( - a_uint32_t dev_id, - a_uint32_t index, - union mc_mtu_ctrl_tbl_u *value) -{ - return hppe_reg_set( - dev_id, - IPE_L2_BASE_ADDR + MC_MTU_CTRL_TBL_ADDRESS + \ - index * MC_MTU_CTRL_TBL_INC, - value->val); -} -#endif - -sw_error_t -hppe_tdm_ctrl_get( - a_uint32_t dev_id, - union tdm_ctrl_u *value) -{ - return hppe_reg_get( - dev_id, - NSS_PRX_CSR_BASE_ADDR + TDM_CTRL_ADDRESS, - &value->val); -} - -sw_error_t -hppe_tdm_ctrl_set( - a_uint32_t dev_id, - union tdm_ctrl_u *value) -{ - return hppe_reg_set( - dev_id, - NSS_PRX_CSR_BASE_ADDR + TDM_CTRL_ADDRESS, - value->val); -} -#ifndef IN_PORTCONTROL_MINI -sw_error_t -hppe_rx_fifo_cfg_get( - a_uint32_t dev_id, - a_uint32_t index, - union rx_fifo_cfg_u *value) -{ - if (index >= RX_FIFO_CFG_MAX_ENTRY) - return SW_OUT_OF_RANGE; - return hppe_reg_get( - dev_id, - NSS_PRX_CSR_BASE_ADDR + RX_FIFO_CFG_ADDRESS + \ - index * RX_FIFO_CFG_INC, - &value->val); -} - -sw_error_t -hppe_rx_fifo_cfg_set( - a_uint32_t dev_id, - a_uint32_t index, - union rx_fifo_cfg_u *value) -{ - return hppe_reg_set( - dev_id, - NSS_PRX_CSR_BASE_ADDR + RX_FIFO_CFG_ADDRESS + \ - index * RX_FIFO_CFG_INC, - value->val); -} - -sw_error_t -hppe_tdm_cfg_get( - a_uint32_t dev_id, - a_uint32_t index, - union tdm_cfg_u *value) -{ - if (index >= TDM_CFG_MAX_ENTRY) - return SW_OUT_OF_RANGE; - return hppe_reg_get( - dev_id, - NSS_PRX_CSR_BASE_ADDR + TDM_CFG_ADDRESS + \ - index * TDM_CFG_INC, - &value->val); -} -#endif - -sw_error_t -hppe_tdm_cfg_set( - a_uint32_t dev_id, - a_uint32_t index, - union tdm_cfg_u *value) -{ - return hppe_reg_set( - dev_id, - NSS_PRX_CSR_BASE_ADDR + TDM_CFG_ADDRESS + \ - index * TDM_CFG_INC, - value->val); -} - -sw_error_t -hppe_drop_stat_get( - a_uint32_t dev_id, - a_uint32_t index, - union drop_stat_u *value) -{ - return hppe_reg_tbl_get( - dev_id, - NSS_PRX_CSR_BASE_ADDR + DROP_STAT_ADDRESS + \ - index * DROP_STAT_INC, - value->val, - 3); -} - -#ifndef IN_MISC_MINI -sw_error_t -hppe_drop_stat_set( - a_uint32_t dev_id, - a_uint32_t index, - union drop_stat_u *value) -{ - return hppe_reg_tbl_set( - dev_id, - NSS_PRX_CSR_BASE_ADDR + DROP_STAT_ADDRESS + \ - index * DROP_STAT_INC, - value->val, - 3); -} -#endif - -#ifndef IN_PORTCONTROL_MINI -sw_error_t -hppe_mac_enable_txmac_en_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union mac_enable_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_mac_enable_get(dev_id, index, ®_val); - *value = reg_val.bf.txmac_en; - return ret; -} - -sw_error_t -hppe_mac_enable_txmac_en_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - union mac_enable_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_mac_enable_get(dev_id, index, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.txmac_en = value; - ret = hppe_mac_enable_set(dev_id, index, ®_val); - return ret; -} - -sw_error_t -hppe_mac_enable_rxmac_en_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union mac_enable_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_mac_enable_get(dev_id, index, ®_val); - *value = reg_val.bf.rxmac_en; - return ret; -} - -sw_error_t -hppe_mac_enable_rxmac_en_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - union mac_enable_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_mac_enable_get(dev_id, index, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.rxmac_en = value; - ret = hppe_mac_enable_set(dev_id, index, ®_val); - return ret; -} - -sw_error_t -hppe_mac_enable_tx_flow_en_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union mac_enable_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_mac_enable_get(dev_id, index, ®_val); - *value = reg_val.bf.tx_flow_en; - return ret; -} - -sw_error_t -hppe_mac_enable_tx_flow_en_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - union mac_enable_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_mac_enable_get(dev_id, index, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.tx_flow_en = value; - ret = hppe_mac_enable_set(dev_id, index, ®_val); - return ret; -} - -sw_error_t -hppe_mac_enable_rx_flow_en_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union mac_enable_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_mac_enable_get(dev_id, index, ®_val); - *value = reg_val.bf.rx_flow_en; - return ret; -} - -sw_error_t -hppe_mac_enable_rx_flow_en_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - union mac_enable_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_mac_enable_get(dev_id, index, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.rx_flow_en = value; - ret = hppe_mac_enable_set(dev_id, index, ®_val); - return ret; -} - -sw_error_t -hppe_mac_enable_duplex_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union mac_enable_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_mac_enable_get(dev_id, index, ®_val); - *value = reg_val.bf.duplex; - return ret; -} - -sw_error_t -hppe_mac_enable_duplex_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - union mac_enable_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_mac_enable_get(dev_id, index, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.duplex = value; - ret = hppe_mac_enable_set(dev_id, index, ®_val); - return ret; -} - -sw_error_t -hppe_mac_speed_mac_speed_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union mac_speed_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_mac_speed_get(dev_id, index, ®_val); - *value = reg_val.bf.mac_speed; - return ret; -} - -sw_error_t -hppe_mac_speed_mac_speed_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - union mac_speed_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_mac_speed_get(dev_id, index, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.mac_speed = value; - ret = hppe_mac_speed_set(dev_id, index, ®_val); - return ret; -} - -sw_error_t -hppe_gol_mac_addr0_mac_addr_byte4_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union gol_mac_addr0_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_gol_mac_addr0_get(dev_id, index, ®_val); - *value = reg_val.bf.mac_addr_byte4; - return ret; -} - -sw_error_t -hppe_gol_mac_addr0_mac_addr_byte4_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - union gol_mac_addr0_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_gol_mac_addr0_get(dev_id, index, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.mac_addr_byte4 = value; - ret = hppe_gol_mac_addr0_set(dev_id, index, ®_val); - return ret; -} - -sw_error_t -hppe_gol_mac_addr0_mac_addr_byte5_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union gol_mac_addr0_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_gol_mac_addr0_get(dev_id, index, ®_val); - *value = reg_val.bf.mac_addr_byte5; - return ret; -} - -sw_error_t -hppe_gol_mac_addr0_mac_addr_byte5_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - union gol_mac_addr0_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_gol_mac_addr0_get(dev_id, index, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.mac_addr_byte5 = value; - ret = hppe_gol_mac_addr0_set(dev_id, index, ®_val); - return ret; -} - -sw_error_t -hppe_gol_mac_addr1_mac_addr_byte1_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union gol_mac_addr1_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_gol_mac_addr1_get(dev_id, index, ®_val); - *value = reg_val.bf.mac_addr_byte1; - return ret; -} - -sw_error_t -hppe_gol_mac_addr1_mac_addr_byte1_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - union gol_mac_addr1_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_gol_mac_addr1_get(dev_id, index, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.mac_addr_byte1 = value; - ret = hppe_gol_mac_addr1_set(dev_id, index, ®_val); - return ret; -} - -sw_error_t -hppe_gol_mac_addr1_mac_addr_byte2_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union gol_mac_addr1_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_gol_mac_addr1_get(dev_id, index, ®_val); - *value = reg_val.bf.mac_addr_byte2; - return ret; -} - -sw_error_t -hppe_gol_mac_addr1_mac_addr_byte2_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - union gol_mac_addr1_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_gol_mac_addr1_get(dev_id, index, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.mac_addr_byte2 = value; - ret = hppe_gol_mac_addr1_set(dev_id, index, ®_val); - return ret; -} - -sw_error_t -hppe_gol_mac_addr1_mac_addr_byte0_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union gol_mac_addr1_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_gol_mac_addr1_get(dev_id, index, ®_val); - *value = reg_val.bf.mac_addr_byte0; - return ret; -} - -sw_error_t -hppe_gol_mac_addr1_mac_addr_byte0_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - union gol_mac_addr1_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_gol_mac_addr1_get(dev_id, index, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.mac_addr_byte0 = value; - ret = hppe_gol_mac_addr1_set(dev_id, index, ®_val); - return ret; -} - -sw_error_t -hppe_gol_mac_addr1_mac_addr_byte3_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union gol_mac_addr1_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_gol_mac_addr1_get(dev_id, index, ®_val); - *value = reg_val.bf.mac_addr_byte3; - return ret; -} - -sw_error_t -hppe_gol_mac_addr1_mac_addr_byte3_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - union gol_mac_addr1_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_gol_mac_addr1_get(dev_id, index, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.mac_addr_byte3 = value; - ret = hppe_gol_mac_addr1_set(dev_id, index, ®_val); - return ret; -} - -sw_error_t -hppe_mac_ctrl0_amaxc_en_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union mac_ctrl0_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_mac_ctrl0_get(dev_id, index, ®_val); - *value = reg_val.bf.amaxc_en; - return ret; -} - -sw_error_t -hppe_mac_ctrl0_amaxc_en_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - union mac_ctrl0_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_mac_ctrl0_get(dev_id, index, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.amaxc_en = value; - ret = hppe_mac_ctrl0_set(dev_id, index, ®_val); - return ret; -} - -sw_error_t -hppe_mac_ctrl0_ipgt_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union mac_ctrl0_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_mac_ctrl0_get(dev_id, index, ®_val); - *value = reg_val.bf.ipgt; - return ret; -} - -sw_error_t -hppe_mac_ctrl0_ipgt_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - union mac_ctrl0_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_mac_ctrl0_get(dev_id, index, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.ipgt = value; - ret = hppe_mac_ctrl0_set(dev_id, index, ®_val); - return ret; -} - -sw_error_t -hppe_mac_ctrl0_nobo_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union mac_ctrl0_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_mac_ctrl0_get(dev_id, index, ®_val); - *value = reg_val.bf.nobo; - return ret; -} - -sw_error_t -hppe_mac_ctrl0_nobo_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - union mac_ctrl0_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_mac_ctrl0_get(dev_id, index, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.nobo = value; - ret = hppe_mac_ctrl0_set(dev_id, index, ®_val); - return ret; -} - -sw_error_t -hppe_mac_ctrl0_half_thdf_ctrl_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union mac_ctrl0_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_mac_ctrl0_get(dev_id, index, ®_val); - *value = reg_val.bf.half_thdf_ctrl; - return ret; -} - -sw_error_t -hppe_mac_ctrl0_half_thdf_ctrl_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - union mac_ctrl0_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_mac_ctrl0_get(dev_id, index, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.half_thdf_ctrl = value; - ret = hppe_mac_ctrl0_set(dev_id, index, ®_val); - return ret; -} - -sw_error_t -hppe_mac_ctrl0_hugen_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union mac_ctrl0_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_mac_ctrl0_get(dev_id, index, ®_val); - *value = reg_val.bf.hugen; - return ret; -} - -sw_error_t -hppe_mac_ctrl0_hugen_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - union mac_ctrl0_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_mac_ctrl0_get(dev_id, index, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.hugen = value; - ret = hppe_mac_ctrl0_set(dev_id, index, ®_val); - return ret; -} - -sw_error_t -hppe_mac_ctrl0_bpnb_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union mac_ctrl0_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_mac_ctrl0_get(dev_id, index, ®_val); - *value = reg_val.bf.bpnb; - return ret; -} - -sw_error_t -hppe_mac_ctrl0_bpnb_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - union mac_ctrl0_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_mac_ctrl0_get(dev_id, index, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.bpnb = value; - ret = hppe_mac_ctrl0_set(dev_id, index, ®_val); - return ret; -} - -sw_error_t -hppe_mac_ctrl0_flchk_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union mac_ctrl0_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_mac_ctrl0_get(dev_id, index, ®_val); - *value = reg_val.bf.flchk; - return ret; -} - -sw_error_t -hppe_mac_ctrl0_flchk_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - union mac_ctrl0_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_mac_ctrl0_get(dev_id, index, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.flchk = value; - ret = hppe_mac_ctrl0_set(dev_id, index, ®_val); - return ret; -} - -sw_error_t -hppe_mac_ctrl0_ipgr2_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union mac_ctrl0_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_mac_ctrl0_get(dev_id, index, ®_val); - *value = reg_val.bf.ipgr2; - return ret; -} - -sw_error_t -hppe_mac_ctrl0_ipgr2_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - union mac_ctrl0_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_mac_ctrl0_get(dev_id, index, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.ipgr2 = value; - ret = hppe_mac_ctrl0_set(dev_id, index, ®_val); - return ret; -} - -sw_error_t -hppe_mac_ctrl0_drbnib_rxok_en_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union mac_ctrl0_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_mac_ctrl0_get(dev_id, index, ®_val); - *value = reg_val.bf.drbnib_rxok_en; - return ret; -} - -sw_error_t -hppe_mac_ctrl0_drbnib_rxok_en_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - union mac_ctrl0_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_mac_ctrl0_get(dev_id, index, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.drbnib_rxok_en = value; - ret = hppe_mac_ctrl0_set(dev_id, index, ®_val); - return ret; -} - -sw_error_t -hppe_mac_ctrl0_huge_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union mac_ctrl0_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_mac_ctrl0_get(dev_id, index, ®_val); - *value = reg_val.bf.huge; - return ret; -} - -sw_error_t -hppe_mac_ctrl0_huge_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - union mac_ctrl0_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_mac_ctrl0_get(dev_id, index, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.huge = value; - ret = hppe_mac_ctrl0_set(dev_id, index, ®_val); - return ret; -} - -sw_error_t -hppe_mac_ctrl0_abebe_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union mac_ctrl0_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_mac_ctrl0_get(dev_id, index, ®_val); - *value = reg_val.bf.abebe; - return ret; -} - -sw_error_t -hppe_mac_ctrl0_abebe_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - union mac_ctrl0_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_mac_ctrl0_get(dev_id, index, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.abebe = value; - ret = hppe_mac_ctrl0_set(dev_id, index, ®_val); - return ret; -} - -sw_error_t -hppe_mac_ctrl1_povr_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union mac_ctrl1_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_mac_ctrl1_get(dev_id, index, ®_val); - *value = reg_val.bf.povr; - return ret; -} - -sw_error_t -hppe_mac_ctrl1_povr_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - union mac_ctrl1_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_mac_ctrl1_get(dev_id, index, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.povr = value; - ret = hppe_mac_ctrl1_set(dev_id, index, ®_val); - return ret; -} - -sw_error_t -hppe_mac_ctrl1_simr_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union mac_ctrl1_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_mac_ctrl1_get(dev_id, index, ®_val); - *value = reg_val.bf.simr; - return ret; -} - -sw_error_t -hppe_mac_ctrl1_simr_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - union mac_ctrl1_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_mac_ctrl1_get(dev_id, index, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.simr = value; - ret = hppe_mac_ctrl1_set(dev_id, index, ®_val); - return ret; -} - -sw_error_t -hppe_mac_ctrl1_jam_ipg_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union mac_ctrl1_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_mac_ctrl1_get(dev_id, index, ®_val); - *value = reg_val.bf.jam_ipg; - return ret; -} - -sw_error_t -hppe_mac_ctrl1_jam_ipg_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - union mac_ctrl1_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_mac_ctrl1_get(dev_id, index, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.jam_ipg = value; - ret = hppe_mac_ctrl1_set(dev_id, index, ®_val); - return ret; -} - -sw_error_t -hppe_mac_ctrl1_lcol_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union mac_ctrl1_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_mac_ctrl1_get(dev_id, index, ®_val); - *value = reg_val.bf.lcol; - return ret; -} - -sw_error_t -hppe_mac_ctrl1_lcol_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - union mac_ctrl1_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_mac_ctrl1_get(dev_id, index, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.lcol = value; - ret = hppe_mac_ctrl1_set(dev_id, index, ®_val); - return ret; -} - -sw_error_t -hppe_mac_ctrl1_tctl_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union mac_ctrl1_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_mac_ctrl1_get(dev_id, index, ®_val); - *value = reg_val.bf.tctl; - return ret; -} - -sw_error_t -hppe_mac_ctrl1_tctl_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - union mac_ctrl1_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_mac_ctrl1_get(dev_id, index, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.tctl = value; - ret = hppe_mac_ctrl1_set(dev_id, index, ®_val); - return ret; -} - -sw_error_t -hppe_mac_ctrl1_retry_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union mac_ctrl1_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_mac_ctrl1_get(dev_id, index, ®_val); - *value = reg_val.bf.retry; - return ret; -} - -sw_error_t -hppe_mac_ctrl1_retry_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - union mac_ctrl1_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_mac_ctrl1_get(dev_id, index, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.retry = value; - ret = hppe_mac_ctrl1_set(dev_id, index, ®_val); - return ret; -} - -sw_error_t -hppe_mac_ctrl1_prlen_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union mac_ctrl1_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_mac_ctrl1_get(dev_id, index, ®_val); - *value = reg_val.bf.prlen; - return ret; -} - -sw_error_t -hppe_mac_ctrl1_prlen_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - union mac_ctrl1_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_mac_ctrl1_get(dev_id, index, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.prlen = value; - ret = hppe_mac_ctrl1_set(dev_id, index, ®_val); - return ret; -} - -sw_error_t -hppe_mac_ctrl1_ppad_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union mac_ctrl1_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_mac_ctrl1_get(dev_id, index, ®_val); - *value = reg_val.bf.ppad; - return ret; -} - -sw_error_t -hppe_mac_ctrl1_ppad_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - union mac_ctrl1_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_mac_ctrl1_get(dev_id, index, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.ppad = value; - ret = hppe_mac_ctrl1_set(dev_id, index, ®_val); - return ret; -} - -sw_error_t -hppe_mac_ctrl1_long_jam_en_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union mac_ctrl1_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_mac_ctrl1_get(dev_id, index, ®_val); - *value = reg_val.bf.long_jam_en; - return ret; -} - -sw_error_t -hppe_mac_ctrl1_long_jam_en_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - union mac_ctrl1_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_mac_ctrl1_get(dev_id, index, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.long_jam_en = value; - ret = hppe_mac_ctrl1_set(dev_id, index, ®_val); - return ret; -} - -sw_error_t -hppe_mac_ctrl1_phug_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union mac_ctrl1_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_mac_ctrl1_get(dev_id, index, ®_val); - *value = reg_val.bf.phug; - return ret; -} - -sw_error_t -hppe_mac_ctrl1_phug_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - union mac_ctrl1_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_mac_ctrl1_get(dev_id, index, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.phug = value; - ret = hppe_mac_ctrl1_set(dev_id, index, ®_val); - return ret; -} - -sw_error_t -hppe_mac_ctrl1_sstct_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union mac_ctrl1_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_mac_ctrl1_get(dev_id, index, ®_val); - *value = reg_val.bf.sstct; - return ret; -} - -sw_error_t -hppe_mac_ctrl1_sstct_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - union mac_ctrl1_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_mac_ctrl1_get(dev_id, index, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.sstct = value; - ret = hppe_mac_ctrl1_set(dev_id, index, ®_val); - return ret; -} - -sw_error_t -hppe_mac_ctrl1_mbof_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union mac_ctrl1_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_mac_ctrl1_get(dev_id, index, ®_val); - *value = reg_val.bf.mbof; - return ret; -} - -sw_error_t -hppe_mac_ctrl1_mbof_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - union mac_ctrl1_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_mac_ctrl1_get(dev_id, index, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.mbof = value; - ret = hppe_mac_ctrl1_set(dev_id, index, ®_val); - return ret; -} - -sw_error_t -hppe_mac_ctrl1_tpause_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union mac_ctrl1_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_mac_ctrl1_get(dev_id, index, ®_val); - *value = reg_val.bf.tpause; - return ret; -} - -sw_error_t -hppe_mac_ctrl1_tpause_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - union mac_ctrl1_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_mac_ctrl1_get(dev_id, index, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.tpause = value; - ret = hppe_mac_ctrl1_set(dev_id, index, ®_val); - return ret; -} - -sw_error_t -hppe_mac_ctrl2_ipg_dec_en_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union mac_ctrl2_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_mac_ctrl2_get(dev_id, index, ®_val); - *value = reg_val.bf.ipg_dec_en; - return ret; -} - -sw_error_t -hppe_mac_ctrl2_ipg_dec_en_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - union mac_ctrl2_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_mac_ctrl2_get(dev_id, index, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.ipg_dec_en = value; - ret = hppe_mac_ctrl2_set(dev_id, index, ®_val); - return ret; -} - -sw_error_t -hppe_mac_ctrl2_mac_rsv_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union mac_ctrl2_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_mac_ctrl2_get(dev_id, index, ®_val); - *value = reg_val.bf.mac_rsv; - return ret; -} - -sw_error_t -hppe_mac_ctrl2_mac_rsv_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - union mac_ctrl2_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_mac_ctrl2_get(dev_id, index, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.mac_rsv = value; - ret = hppe_mac_ctrl2_set(dev_id, index, ®_val); - return ret; -} - -sw_error_t -hppe_mac_ctrl2_mac_tx_thd_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union mac_ctrl2_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_mac_ctrl2_get(dev_id, index, ®_val); - *value = reg_val.bf.mac_tx_thd; - return ret; -} -#endif -sw_error_t -hppe_mac_ctrl2_mac_tx_thd_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - union mac_ctrl2_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_mac_ctrl2_get(dev_id, index, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.mac_tx_thd = value; - ret = hppe_mac_ctrl2_set(dev_id, index, ®_val); - return ret; -} -#ifndef IN_PORTCONTROL_MINI -sw_error_t -hppe_mac_ctrl2_crc_rsv_en_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union mac_ctrl2_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_mac_ctrl2_get(dev_id, index, ®_val); - *value = reg_val.bf.crc_rsv_en; - return ret; -} - -sw_error_t -hppe_mac_ctrl2_crc_rsv_en_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - union mac_ctrl2_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_mac_ctrl2_get(dev_id, index, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.crc_rsv_en = value; - ret = hppe_mac_ctrl2_set(dev_id, index, ®_val); - return ret; -} - -sw_error_t -hppe_mac_ctrl2_crs_sel_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union mac_ctrl2_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_mac_ctrl2_get(dev_id, index, ®_val); - *value = reg_val.bf.crs_sel; - return ret; -} -#endif -sw_error_t -hppe_mac_ctrl2_crs_sel_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - union mac_ctrl2_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_mac_ctrl2_get(dev_id, index, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.crs_sel = value; - ret = hppe_mac_ctrl2_set(dev_id, index, ®_val); - return ret; -} -#ifndef IN_PORTCONTROL_MINI -sw_error_t -hppe_mac_ctrl2_ipg_dec_len_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union mac_ctrl2_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_mac_ctrl2_get(dev_id, index, ®_val); - *value = reg_val.bf.ipg_dec_len; - return ret; -} - -sw_error_t -hppe_mac_ctrl2_ipg_dec_len_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - union mac_ctrl2_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_mac_ctrl2_get(dev_id, index, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.ipg_dec_len = value; - ret = hppe_mac_ctrl2_set(dev_id, index, ®_val); - return ret; -} - -sw_error_t -hppe_mac_ctrl2_maxfr_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union mac_ctrl2_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_mac_ctrl2_get(dev_id, index, ®_val); - *value = reg_val.bf.maxfr; - return ret; -} -#endif -sw_error_t -hppe_mac_ctrl2_maxfr_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - union mac_ctrl2_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_mac_ctrl2_get(dev_id, index, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.maxfr = value; - ret = hppe_mac_ctrl2_set(dev_id, index, ®_val); - return ret; -} -#ifndef IN_PORTCONTROL_MINI - -sw_error_t -hppe_mac_ctrl2_mac_lpi_tx_idle_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union mac_ctrl2_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_mac_ctrl2_get(dev_id, index, ®_val); - *value = reg_val.bf.mac_lpi_tx_idle; - return ret; -} - -sw_error_t -hppe_mac_ctrl2_mac_lpi_tx_idle_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - union mac_ctrl2_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_mac_ctrl2_get(dev_id, index, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.mac_lpi_tx_idle = value; - ret = hppe_mac_ctrl2_set(dev_id, index, ®_val); - return ret; -} - -sw_error_t -hppe_mac_ctrl2_mac_loop_back_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union mac_ctrl2_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_mac_ctrl2_get(dev_id, index, ®_val); - *value = reg_val.bf.mac_loop_back; - return ret; -} - -sw_error_t -hppe_mac_ctrl2_mac_loop_back_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - union mac_ctrl2_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_mac_ctrl2_get(dev_id, index, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.mac_loop_back = value; - ret = hppe_mac_ctrl2_set(dev_id, index, ®_val); - return ret; -} - -sw_error_t -hppe_mac_ctrl2_test_pause_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union mac_ctrl2_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_mac_ctrl2_get(dev_id, index, ®_val); - *value = reg_val.bf.test_pause; - return ret; -} - -sw_error_t -hppe_mac_ctrl2_test_pause_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - union mac_ctrl2_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_mac_ctrl2_get(dev_id, index, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.test_pause = value; - ret = hppe_mac_ctrl2_set(dev_id, index, ®_val); - return ret; -} - -sw_error_t -hppe_mac_dbg_ctrl_edxsdfr_transmit_en_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union mac_dbg_ctrl_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_mac_dbg_ctrl_get(dev_id, index, ®_val); - *value = reg_val.bf.edxsdfr_transmit_en; - return ret; -} - -sw_error_t -hppe_mac_dbg_ctrl_edxsdfr_transmit_en_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - union mac_dbg_ctrl_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_mac_dbg_ctrl_get(dev_id, index, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.edxsdfr_transmit_en = value; - ret = hppe_mac_dbg_ctrl_set(dev_id, index, ®_val); - return ret; -} - -sw_error_t -hppe_mac_dbg_ctrl_hihg_ipg_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union mac_dbg_ctrl_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_mac_dbg_ctrl_get(dev_id, index, ®_val); - *value = reg_val.bf.hihg_ipg; - return ret; -} -#endif -sw_error_t -hppe_mac_dbg_ctrl_hihg_ipg_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - union mac_dbg_ctrl_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_mac_dbg_ctrl_get(dev_id, index, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.hihg_ipg = value; - ret = hppe_mac_dbg_ctrl_set(dev_id, index, ®_val); - return ret; -} -#ifndef IN_PORTCONTROL_MINI -sw_error_t -hppe_mac_dbg_ctrl_mac_ipg_ctrl_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union mac_dbg_ctrl_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_mac_dbg_ctrl_get(dev_id, index, ®_val); - *value = reg_val.bf.mac_ipg_ctrl; - return ret; -} - -sw_error_t -hppe_mac_dbg_ctrl_mac_ipg_ctrl_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - union mac_dbg_ctrl_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_mac_dbg_ctrl_get(dev_id, index, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.mac_ipg_ctrl = value; - ret = hppe_mac_dbg_ctrl_set(dev_id, index, ®_val); - return ret; -} - -sw_error_t -hppe_mac_dbg_ctrl_mac_len_ctrl_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union mac_dbg_ctrl_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_mac_dbg_ctrl_get(dev_id, index, ®_val); - *value = reg_val.bf.mac_len_ctrl; - return ret; -} - -sw_error_t -hppe_mac_dbg_ctrl_mac_len_ctrl_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - union mac_dbg_ctrl_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_mac_dbg_ctrl_get(dev_id, index, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.mac_len_ctrl = value; - ret = hppe_mac_dbg_ctrl_set(dev_id, index, ®_val); - return ret; -} - -sw_error_t -hppe_mac_dbg_ctrl_ipgr1_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union mac_dbg_ctrl_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_mac_dbg_ctrl_get(dev_id, index, ®_val); - *value = reg_val.bf.ipgr1; - return ret; -} - -sw_error_t -hppe_mac_dbg_ctrl_ipgr1_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - union mac_dbg_ctrl_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_mac_dbg_ctrl_get(dev_id, index, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.ipgr1 = value; - ret = hppe_mac_dbg_ctrl_set(dev_id, index, ®_val); - return ret; -} - -sw_error_t -hppe_mac_dbg_addr_mac_debug_addr_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union mac_dbg_addr_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_mac_dbg_addr_get(dev_id, index, ®_val); - *value = reg_val.bf.mac_debug_addr; - return ret; -} - -sw_error_t -hppe_mac_dbg_addr_mac_debug_addr_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - union mac_dbg_addr_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_mac_dbg_addr_get(dev_id, index, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.mac_debug_addr = value; - ret = hppe_mac_dbg_addr_set(dev_id, index, ®_val); - return ret; -} - -sw_error_t -hppe_mac_dbg_data_mac_debug_data_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union mac_dbg_data_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_mac_dbg_data_get(dev_id, index, ®_val); - *value = reg_val.bf.mac_debug_data; - return ret; -} - -sw_error_t -hppe_mac_dbg_data_mac_debug_data_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - return SW_NOT_SUPPORTED; -} -#endif -sw_error_t -hppe_mac_jumbo_size_mac_jumbo_size_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union mac_jumbo_size_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_mac_jumbo_size_get(dev_id, index, ®_val); - *value = reg_val.bf.mac_jumbo_size; - return ret; -} - -sw_error_t -hppe_mac_jumbo_size_mac_jumbo_size_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - union mac_jumbo_size_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_mac_jumbo_size_get(dev_id, index, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.mac_jumbo_size = value; - ret = hppe_mac_jumbo_size_set(dev_id, index, ®_val); - return ret; -} -#ifndef IN_PORTCONTROL_MINI -sw_error_t -hppe_mru_mtu_ctrl_tbl_mtu_cmd_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union mru_mtu_ctrl_tbl_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_mru_mtu_ctrl_tbl_get(dev_id, index, ®_val); - *value = reg_val.bf.mtu_cmd; - return ret; -} - -sw_error_t -hppe_mru_mtu_ctrl_tbl_mtu_cmd_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - union mru_mtu_ctrl_tbl_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_mru_mtu_ctrl_tbl_get(dev_id, index, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.mtu_cmd = value; - ret = hppe_mru_mtu_ctrl_tbl_set(dev_id, index, ®_val); - return ret; -} - -sw_error_t -hppe_mru_mtu_ctrl_tbl_rx_cnt_en_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union mru_mtu_ctrl_tbl_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_mru_mtu_ctrl_tbl_get(dev_id, index, ®_val); - *value = reg_val.bf.rx_cnt_en; - return ret; -} - -sw_error_t -hppe_mru_mtu_ctrl_tbl_rx_cnt_en_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - union mru_mtu_ctrl_tbl_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_mru_mtu_ctrl_tbl_get(dev_id, index, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.rx_cnt_en = value; - ret = hppe_mru_mtu_ctrl_tbl_set(dev_id, index, ®_val); - return ret; -} - -sw_error_t -hppe_mru_mtu_ctrl_tbl_tx_cnt_en_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union mru_mtu_ctrl_tbl_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_mru_mtu_ctrl_tbl_get(dev_id, index, ®_val); - *value = reg_val.bf.tx_cnt_en; - return ret; -} - -sw_error_t -hppe_mru_mtu_ctrl_tbl_tx_cnt_en_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - union mru_mtu_ctrl_tbl_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_mru_mtu_ctrl_tbl_get(dev_id, index, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.tx_cnt_en = value; - ret = hppe_mru_mtu_ctrl_tbl_set(dev_id, index, ®_val); - return ret; -} - -sw_error_t -hppe_mru_mtu_ctrl_tbl_mru_cmd_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union mru_mtu_ctrl_tbl_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_mru_mtu_ctrl_tbl_get(dev_id, index, ®_val); - *value = reg_val.bf.mru_cmd; - return ret; -} - -sw_error_t -hppe_mru_mtu_ctrl_tbl_mru_cmd_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - union mru_mtu_ctrl_tbl_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_mru_mtu_ctrl_tbl_get(dev_id, index, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.mru_cmd = value; - ret = hppe_mru_mtu_ctrl_tbl_set(dev_id, index, ®_val); - return ret; -} - -sw_error_t -hppe_mru_mtu_ctrl_tbl_mru_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union mru_mtu_ctrl_tbl_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_mru_mtu_ctrl_tbl_get(dev_id, index, ®_val); - *value = reg_val.bf.mru; - return ret; -} - -sw_error_t -hppe_mru_mtu_ctrl_tbl_mru_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - union mru_mtu_ctrl_tbl_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_mru_mtu_ctrl_tbl_get(dev_id, index, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.mru = value; - ret = hppe_mru_mtu_ctrl_tbl_set(dev_id, index, ®_val); - return ret; -} -#endif - -sw_error_t -hppe_mru_mtu_ctrl_tbl_src_profile_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union mru_mtu_ctrl_tbl_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_mru_mtu_ctrl_tbl_get(dev_id, index, ®_val); - *value = reg_val.bf.src_profile; - return ret; -} - -sw_error_t -hppe_mru_mtu_ctrl_tbl_src_profile_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - union mru_mtu_ctrl_tbl_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_mru_mtu_ctrl_tbl_get(dev_id, index, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.src_profile = value; - ret = hppe_mru_mtu_ctrl_tbl_set(dev_id, index, ®_val); - return ret; -} - -#ifndef IN_PORTCONTROL_MINI -sw_error_t -hppe_mc_mtu_ctrl_tbl_mtu_cmd_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union mc_mtu_ctrl_tbl_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_mc_mtu_ctrl_tbl_get(dev_id, index, ®_val); - *value = reg_val.bf.mtu_cmd; - return ret; -} - -sw_error_t -hppe_mc_mtu_ctrl_tbl_mtu_cmd_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - union mc_mtu_ctrl_tbl_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_mc_mtu_ctrl_tbl_get(dev_id, index, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.mtu_cmd = value; - ret = hppe_mc_mtu_ctrl_tbl_set(dev_id, index, ®_val); - return ret; -} - -sw_error_t -hppe_mc_mtu_ctrl_tbl_tx_cnt_en_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union mc_mtu_ctrl_tbl_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_mc_mtu_ctrl_tbl_get(dev_id, index, ®_val); - *value = reg_val.bf.tx_cnt_en; - return ret; -} - -sw_error_t -hppe_mc_mtu_ctrl_tbl_tx_cnt_en_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - union mc_mtu_ctrl_tbl_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_mc_mtu_ctrl_tbl_get(dev_id, index, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.tx_cnt_en = value; - ret = hppe_mc_mtu_ctrl_tbl_set(dev_id, index, ®_val); - return ret; -} - -sw_error_t -hppe_mc_mtu_ctrl_tbl_mtu_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union mc_mtu_ctrl_tbl_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_mc_mtu_ctrl_tbl_get(dev_id, index, ®_val); - *value = reg_val.bf.mtu; - return ret; -} - -sw_error_t -hppe_mc_mtu_ctrl_tbl_mtu_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - union mc_mtu_ctrl_tbl_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_mc_mtu_ctrl_tbl_get(dev_id, index, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.mtu = value; - ret = hppe_mc_mtu_ctrl_tbl_set(dev_id, index, ®_val); - return ret; -} - -sw_error_t -hppe_tdm_ctrl_tdm_en_get( - a_uint32_t dev_id, - a_uint32_t *value) -{ - union tdm_ctrl_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_tdm_ctrl_get(dev_id, ®_val); - *value = reg_val.bf.tdm_en; - return ret; -} - -sw_error_t -hppe_tdm_ctrl_tdm_en_set( - a_uint32_t dev_id, - a_uint32_t value) -{ - union tdm_ctrl_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_tdm_ctrl_get(dev_id, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.tdm_en = value; - ret = hppe_tdm_ctrl_set(dev_id, ®_val); - return ret; -} - -sw_error_t -hppe_tdm_ctrl_tdm_offset_get( - a_uint32_t dev_id, - a_uint32_t *value) -{ - union tdm_ctrl_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_tdm_ctrl_get(dev_id, ®_val); - *value = reg_val.bf.tdm_offset; - return ret; -} - -sw_error_t -hppe_tdm_ctrl_tdm_offset_set( - a_uint32_t dev_id, - a_uint32_t value) -{ - union tdm_ctrl_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_tdm_ctrl_get(dev_id, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.tdm_offset = value; - ret = hppe_tdm_ctrl_set(dev_id, ®_val); - return ret; -} - -sw_error_t -hppe_tdm_ctrl_tdm_depth_get( - a_uint32_t dev_id, - a_uint32_t *value) -{ - union tdm_ctrl_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_tdm_ctrl_get(dev_id, ®_val); - *value = reg_val.bf.tdm_depth; - return ret; -} - -sw_error_t -hppe_tdm_ctrl_tdm_depth_set( - a_uint32_t dev_id, - a_uint32_t value) -{ - union tdm_ctrl_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_tdm_ctrl_get(dev_id, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.tdm_depth = value; - ret = hppe_tdm_ctrl_set(dev_id, ®_val); - return ret; -} - -sw_error_t -hppe_rx_fifo_cfg_rx_fifo_thres_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union rx_fifo_cfg_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_rx_fifo_cfg_get(dev_id, index, ®_val); - *value = reg_val.bf.rx_fifo_thres; - return ret; -} - -sw_error_t -hppe_rx_fifo_cfg_rx_fifo_thres_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - union rx_fifo_cfg_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_rx_fifo_cfg_get(dev_id, index, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.rx_fifo_thres = value; - ret = hppe_rx_fifo_cfg_set(dev_id, index, ®_val); - return ret; -} - -sw_error_t -hppe_tdm_cfg_port_num_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union tdm_cfg_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_tdm_cfg_get(dev_id, index, ®_val); - *value = reg_val.bf.port_num; - return ret; -} - -sw_error_t -hppe_tdm_cfg_port_num_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - union tdm_cfg_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_tdm_cfg_get(dev_id, index, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.port_num = value; - ret = hppe_tdm_cfg_set(dev_id, index, ®_val); - return ret; -} - -sw_error_t -hppe_tdm_cfg_valid_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union tdm_cfg_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_tdm_cfg_get(dev_id, index, ®_val); - *value = reg_val.bf.valid; - return ret; -} - -sw_error_t -hppe_tdm_cfg_valid_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - union tdm_cfg_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_tdm_cfg_get(dev_id, index, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.valid = value; - ret = hppe_tdm_cfg_set(dev_id, index, ®_val); - return ret; -} - -sw_error_t -hppe_tdm_cfg_dir_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union tdm_cfg_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_tdm_cfg_get(dev_id, index, ®_val); - *value = reg_val.bf.dir; - return ret; -} - -sw_error_t -hppe_tdm_cfg_dir_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - union tdm_cfg_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_tdm_cfg_get(dev_id, index, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.dir = value; - ret = hppe_tdm_cfg_set(dev_id, index, ®_val); - return ret; -} -#endif -sw_error_t -hppe_port_in_forward_get( - a_uint32_t dev_id, - a_uint32_t index, - union port_in_forward_u *value) -{ - if (index >= PORT_IN_FORWARD_MAX_ENTRY) - return SW_OUT_OF_RANGE; - return hppe_reg_get( - dev_id, - IPE_L2_BASE_ADDR + PORT_IN_FORWARD_ADDRESS + \ - index * PORT_IN_FORWARD_INC, - &value->val); -} - -sw_error_t -hppe_port_in_forward_set( - a_uint32_t dev_id, - a_uint32_t index, - union port_in_forward_u *value) -{ - return hppe_reg_set( - dev_id, - IPE_L2_BASE_ADDR + PORT_IN_FORWARD_ADDRESS + \ - index * PORT_IN_FORWARD_INC, - value->val); -} -#ifndef IN_PORTCONTROL_MINI -sw_error_t -hppe_port_in_forward_source_filtering_bypass_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union port_in_forward_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_port_in_forward_get(dev_id, index, ®_val); - *value = reg_val.bf.source_filtering_bypass; - return ret; -} - -sw_error_t -hppe_port_in_forward_source_filtering_bypass_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - union port_in_forward_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_port_in_forward_get(dev_id, index, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.source_filtering_bypass = value; - ret = hppe_port_in_forward_set(dev_id, index, ®_val); - return ret; -} -#endif - -#ifndef IN_MISC_MINI -sw_error_t -hppe_drop_stat_bytes_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint64_t *value) -{ - union drop_stat_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_drop_stat_get(dev_id, index, ®_val); - *value = (a_uint64_t)reg_val.bf.bytes_1 << 32 | \ - reg_val.bf.bytes_0; - return ret; -} - -sw_error_t -hppe_drop_stat_bytes_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint64_t value) -{ - union drop_stat_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_drop_stat_get(dev_id, index, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.bytes_1 = value >> 32; - reg_val.bf.bytes_0 = value & (((a_uint64_t)1<<32)-1); - ret = hppe_drop_stat_set(dev_id, index, ®_val); - return ret; -} - -sw_error_t -hppe_drop_stat_pkts_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union drop_stat_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_drop_stat_get(dev_id, index, ®_val); - *value = reg_val.bf.pkts; - return ret; -} - -sw_error_t -hppe_drop_stat_pkts_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - union drop_stat_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_drop_stat_get(dev_id, index, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.pkts = value; - ret = hppe_drop_stat_set(dev_id, index, ®_val); - return ret; -} -#endif - -#if ((!defined(IN_PORTCONTROL_MINI)) || (!defined(IN_MISC_MINI))) -sw_error_t -hppe_port_tx_counter_tbl_reg_get( - a_uint32_t dev_id, - a_uint32_t index, - union port_tx_counter_tbl_reg_u *value) -{ - return hppe_reg_tbl_get( - dev_id, - NSS_PTX_CSR_BASE_ADDR + PORT_TX_COUNTER_TBL_REG_ADDRESS + \ - index * PORT_TX_COUNTER_TBL_REG_INC, - value->val, - 3); -} - -sw_error_t -hppe_port_tx_counter_tbl_reg_set( - a_uint32_t dev_id, - a_uint32_t index, - union port_tx_counter_tbl_reg_u *value) -{ - return hppe_reg_tbl_set( - dev_id, - NSS_PTX_CSR_BASE_ADDR + PORT_TX_COUNTER_TBL_REG_ADDRESS + \ - index * PORT_TX_COUNTER_TBL_REG_INC, - value->val, - 3); -} - -sw_error_t -hppe_vp_tx_counter_tbl_reg_get( - a_uint32_t dev_id, - a_uint32_t index, - union vp_tx_counter_tbl_reg_u *value) -{ - return hppe_reg_tbl_get( - dev_id, - NSS_PTX_CSR_BASE_ADDR + VP_TX_COUNTER_TBL_REG_ADDRESS + \ - index * VP_TX_COUNTER_TBL_REG_INC, - value->val, - 3); -} - -sw_error_t -hppe_vp_tx_counter_tbl_reg_set( - a_uint32_t dev_id, - a_uint32_t index, - union vp_tx_counter_tbl_reg_u *value) -{ - return hppe_reg_tbl_set( - dev_id, - NSS_PTX_CSR_BASE_ADDR + VP_TX_COUNTER_TBL_REG_ADDRESS + \ - index * VP_TX_COUNTER_TBL_REG_INC, - value->val, - 3); -} - -sw_error_t -hppe_epe_dbg_in_cnt_reg_get( - a_uint32_t dev_id, - union epe_dbg_in_cnt_reg_u *value) -{ - return hppe_reg_get( - dev_id, - NSS_PTX_CSR_BASE_ADDR + EPE_DBG_IN_CNT_REG_ADDRESS, - &value->val); -} - -sw_error_t -hppe_epe_dbg_in_cnt_reg_set( - a_uint32_t dev_id, - union epe_dbg_in_cnt_reg_u *value) -{ - return hppe_reg_set( - dev_id, - NSS_PTX_CSR_BASE_ADDR + EPE_DBG_IN_CNT_REG_ADDRESS, - value->val); -} - -sw_error_t -hppe_epe_dbg_out_cnt_reg_set( - a_uint32_t dev_id, - union epe_dbg_out_cnt_reg_u *value) -{ - return hppe_reg_set( - dev_id, - NSS_PTX_CSR_BASE_ADDR + EPE_DBG_OUT_CNT_REG_ADDRESS, - value->val); -} -#endif - -#ifndef IN_PORTCONTROL_MINI -sw_error_t -hppe_epe_dbg_out_cnt_reg_get( - a_uint32_t dev_id, - union epe_dbg_out_cnt_reg_u *value) -{ - return hppe_reg_get( - dev_id, - NSS_PTX_CSR_BASE_ADDR + EPE_DBG_OUT_CNT_REG_ADDRESS, - &value->val); -} - -sw_error_t -hppe_port_tx_counter_tbl_reg_tx_bytes_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint64_t *value) -{ - union port_tx_counter_tbl_reg_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_port_tx_counter_tbl_reg_get(dev_id, index, ®_val); - *value = (a_uint64_t)reg_val.bf.tx_bytes_1 << 32 | \ - reg_val.bf.tx_bytes_0; - return ret; -} - -sw_error_t -hppe_port_tx_counter_tbl_reg_tx_bytes_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint64_t value) -{ - union port_tx_counter_tbl_reg_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_port_tx_counter_tbl_reg_get(dev_id, index, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.tx_bytes_1 = value >> 32; - reg_val.bf.tx_bytes_0 = value & (((a_uint64_t)1<<32)-1); - ret = hppe_port_tx_counter_tbl_reg_set(dev_id, index, ®_val); - return ret; -} - -sw_error_t -hppe_port_tx_counter_tbl_reg_tx_packets_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union port_tx_counter_tbl_reg_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_port_tx_counter_tbl_reg_get(dev_id, index, ®_val); - *value = reg_val.bf.tx_packets; - return ret; -} - -sw_error_t -hppe_port_tx_counter_tbl_reg_tx_packets_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - union port_tx_counter_tbl_reg_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_port_tx_counter_tbl_reg_get(dev_id, index, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.tx_packets = value; - ret = hppe_port_tx_counter_tbl_reg_set(dev_id, index, ®_val); - return ret; -} - -sw_error_t -hppe_vp_tx_counter_tbl_reg_tx_bytes_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint64_t *value) -{ - union vp_tx_counter_tbl_reg_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_vp_tx_counter_tbl_reg_get(dev_id, index, ®_val); - *value = (a_uint64_t)reg_val.bf.tx_bytes_1 << 32 | \ - reg_val.bf.tx_bytes_0; - return ret; -} - -sw_error_t -hppe_vp_tx_counter_tbl_reg_tx_bytes_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint64_t value) -{ - union vp_tx_counter_tbl_reg_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_vp_tx_counter_tbl_reg_get(dev_id, index, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.tx_bytes_1 = value >> 32; - reg_val.bf.tx_bytes_0 = value & (((a_uint64_t)1<<32)-1); - ret = hppe_vp_tx_counter_tbl_reg_set(dev_id, index, ®_val); - return ret; -} - -sw_error_t -hppe_vp_tx_counter_tbl_reg_tx_packets_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union vp_tx_counter_tbl_reg_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_vp_tx_counter_tbl_reg_get(dev_id, index, ®_val); - *value = reg_val.bf.tx_packets; - return ret; -} - -sw_error_t -hppe_vp_tx_counter_tbl_reg_tx_packets_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - union vp_tx_counter_tbl_reg_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_vp_tx_counter_tbl_reg_get(dev_id, index, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.tx_packets = value; - ret = hppe_vp_tx_counter_tbl_reg_set(dev_id, index, ®_val); - return ret; -} - -sw_error_t -hppe_epe_dbg_in_cnt_reg_counter_get( - a_uint32_t dev_id, - a_uint32_t *value) -{ - union epe_dbg_in_cnt_reg_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_epe_dbg_in_cnt_reg_get(dev_id, ®_val); - *value = reg_val.bf.counter; - return ret; -} - -sw_error_t -hppe_epe_dbg_in_cnt_reg_counter_set( - a_uint32_t dev_id, - a_uint32_t value) -{ - union epe_dbg_in_cnt_reg_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_epe_dbg_in_cnt_reg_get(dev_id, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.counter = value; - ret = hppe_epe_dbg_in_cnt_reg_set(dev_id, ®_val); - return ret; -} - -sw_error_t -hppe_epe_dbg_out_cnt_reg_counter_get( - a_uint32_t dev_id, - a_uint32_t *value) -{ - union epe_dbg_out_cnt_reg_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_epe_dbg_out_cnt_reg_get(dev_id, ®_val); - *value = reg_val.bf.counter; - return ret; -} - -sw_error_t -hppe_epe_dbg_out_cnt_reg_counter_set( - a_uint32_t dev_id, - a_uint32_t value) -{ - union epe_dbg_out_cnt_reg_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_epe_dbg_out_cnt_reg_get(dev_id, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.counter = value; - ret = hppe_epe_dbg_out_cnt_reg_set(dev_id, ®_val); - return ret; -} -#endif - -sw_error_t -hppe_lpi_enable_get( - a_uint32_t dev_id, - a_uint32_t index, - union lpi_enable_u *value) -{ - return hppe_reg_get( - dev_id, - NSS_LPI_BASE_ADDR + LPI_ENABLE_ADDRESS + \ - index * LPI_ENABLE_INC, - &value->val); -} - -sw_error_t -hppe_lpi_enable_set( - a_uint32_t dev_id, - a_uint32_t index, - union lpi_enable_u *value) -{ - return hppe_reg_set( - dev_id, - NSS_LPI_BASE_ADDR + LPI_ENABLE_ADDRESS + \ - index * LPI_ENABLE_INC, - value->val); -} - -sw_error_t -hppe_lpi_timer_get( - a_uint32_t dev_id, - a_uint32_t index, - union lpi_port_timer_u *value) -{ - return hppe_reg_get( - dev_id, - NSS_LPI_BASE_ADDR + LPI_PORT_TIMER_ADDRESS + \ - index * LPI_PORT_TIMER_INC, - &value->val); -} - -sw_error_t -hppe_lpi_timer_set( - a_uint32_t dev_id, - a_uint32_t index, - union lpi_port_timer_u *value) -{ - return hppe_reg_set( - dev_id, - NSS_LPI_BASE_ADDR + LPI_PORT_TIMER_ADDRESS + \ - index * LPI_PORT_TIMER_INC, - value->val); -} -#ifndef IN_PORTCONTROL_MINI -sw_error_t -hppe_lpi_dbg_addr_get( - a_uint32_t dev_id, - a_uint32_t index, - union lpi_dbg_addr_u *value) -{ - return hppe_reg_get( - dev_id, - NSS_LPI_BASE_ADDR + LPI_DBG_ADDR_ADDRESS + \ - index * LPI_DBG_ADDR_INC, - &value->val); -} - -sw_error_t -hppe_lpi_dbg_addr_set( - a_uint32_t dev_id, - a_uint32_t index, - union lpi_dbg_addr_u *value) -{ - return hppe_reg_set( - dev_id, - NSS_LPI_BASE_ADDR + LPI_DBG_ADDR_ADDRESS + \ - index * LPI_DBG_ADDR_INC, - value->val); -} - -sw_error_t -hppe_lpi_dbg_data_get( - a_uint32_t dev_id, - a_uint32_t index, - union lpi_dbg_data_u *value) -{ - return hppe_reg_get( - dev_id, - NSS_LPI_BASE_ADDR + LPI_DBG_DATA_ADDRESS + \ - index * LPI_DBG_DATA_INC, - &value->val); -} - -sw_error_t -hppe_lpi_dbg_data_set( - a_uint32_t dev_id, - a_uint32_t index, - union lpi_dbg_addr_u *value) -{ - return hppe_reg_set( - dev_id, - NSS_LPI_BASE_ADDR + LPI_DBG_DATA_ADDRESS + \ - index * LPI_DBG_DATA_INC, - value->val); -} -sw_error_t -hppe_lpi_cnt_get( - a_uint32_t dev_id, - a_uint32_t index, - union lpi_cnt_u *value) -{ - return hppe_reg_get( - dev_id, - NSS_LPI_BASE_ADDR + LPI_CNT_ADDRESS + \ - index * LPI_CNT_INC, - &value->val); -} - -sw_error_t -hppe_lpi_cnt_set( - a_uint32_t dev_id, - a_uint32_t index, - union lpi_cnt_u *value) -{ - return hppe_reg_set( - dev_id, - NSS_LPI_BASE_ADDR + LPI_CNT_ADDRESS + \ - index * LPI_CNT_INC, - value->val); -} -#endif - -#ifndef IN_MISC_MINI -sw_error_t -hppe_drop_cnt_get( - a_uint32_t dev_id, - a_uint32_t index, - union drop_cnt_u *value) -{ - if (index >= DROP_CNT_MAX_ENTRY) - return SW_OUT_OF_RANGE; - return hppe_reg_get( - dev_id, - NSS_PRX_CSR_BASE_ADDR + DROP_CNT_ADDRESS + \ - index * DROP_CNT_INC, - &value->val); -} - -sw_error_t -hppe_drop_cnt_set( - a_uint32_t dev_id, - a_uint32_t index, - union drop_cnt_u *value) -{ - return hppe_reg_set( - dev_id, - NSS_PRX_CSR_BASE_ADDR + DROP_CNT_ADDRESS + \ - index * DROP_CNT_INC, - value->val); -} - -sw_error_t -hppe_drop_cnt_drop_cnt_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union drop_cnt_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_drop_cnt_get(dev_id, index, ®_val); - *value = reg_val.bf.drop_cnt; - return ret; -} - -sw_error_t -hppe_drop_cnt_drop_cnt_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - union drop_cnt_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_drop_cnt_get(dev_id, index, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.drop_cnt = value; - ret = hppe_drop_cnt_set(dev_id, index, ®_val); - return ret; -} - -sw_error_t -hppe_ipr_pkt_num_tbl_reg_get( - a_uint32_t dev_id, - a_uint32_t index, - union ipr_pkt_num_tbl_reg_u *value) -{ - if (index >= IPR_PKT_NUM_TBL_REG_MAX_ENTRY) - return SW_OUT_OF_RANGE; - return hppe_reg_get( - dev_id, - IPR_CSR_BASE_ADDR + IPR_PKT_NUM_TBL_REG_ADDRESS + \ - index * IPR_PKT_NUM_TBL_REG_INC, - &value->val); -} - -sw_error_t -hppe_ipr_pkt_num_tbl_reg_set( - a_uint32_t dev_id, - a_uint32_t index, - union ipr_pkt_num_tbl_reg_u *value) -{ - return hppe_reg_set( - dev_id, - IPR_CSR_BASE_ADDR + IPR_PKT_NUM_TBL_REG_ADDRESS + \ - index * IPR_PKT_NUM_TBL_REG_INC, - value->val); -} - -sw_error_t -hppe_ipr_byte_low_reg_reg_get( - a_uint32_t dev_id, - a_uint32_t index, - union ipr_byte_low_reg_reg_u *value) -{ - if (index >= IPR_BYTE_LOW_REG_REG_MAX_ENTRY) - return SW_OUT_OF_RANGE; - return hppe_reg_get( - dev_id, - IPR_CSR_BASE_ADDR + IPR_BYTE_LOW_REG_REG_ADDRESS + \ - index * IPR_BYTE_LOW_REG_REG_INC, - &value->val); -} - -sw_error_t -hppe_ipr_byte_low_reg_reg_set( - a_uint32_t dev_id, - a_uint32_t index, - union ipr_byte_low_reg_reg_u *value) -{ - return hppe_reg_set( - dev_id, - IPR_CSR_BASE_ADDR + IPR_BYTE_LOW_REG_REG_ADDRESS + \ - index * IPR_BYTE_LOW_REG_REG_INC, - value->val); -} - -sw_error_t -hppe_ipr_byte_high_reg_get( - a_uint32_t dev_id, - a_uint32_t index, - union ipr_byte_high_reg_u *value) -{ - if (index >= IPR_BYTE_HIGH_REG_MAX_ENTRY) - return SW_OUT_OF_RANGE; - return hppe_reg_get( - dev_id, - IPR_CSR_BASE_ADDR + IPR_BYTE_HIGH_REG_ADDRESS + \ - index * IPR_BYTE_HIGH_REG_INC, - &value->val); -} - -sw_error_t -hppe_ipr_byte_high_reg_set( - a_uint32_t dev_id, - a_uint32_t index, - union ipr_byte_high_reg_u *value) -{ - return hppe_reg_set( - dev_id, - IPR_CSR_BASE_ADDR + IPR_BYTE_HIGH_REG_ADDRESS + \ - index * IPR_BYTE_HIGH_REG_INC, - value->val); -} - -sw_error_t -hppe_ipr_pkt_num_tbl_reg_packets_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union ipr_pkt_num_tbl_reg_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_ipr_pkt_num_tbl_reg_get(dev_id, index, ®_val); - *value = reg_val.bf.packets; - return ret; -} - -sw_error_t -hppe_ipr_pkt_num_tbl_reg_packets_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - union ipr_pkt_num_tbl_reg_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_ipr_pkt_num_tbl_reg_get(dev_id, index, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.packets = value; - ret = hppe_ipr_pkt_num_tbl_reg_set(dev_id, index, ®_val); - return ret; -} - -sw_error_t -hppe_ipr_byte_low_reg_reg_bytes_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union ipr_byte_low_reg_reg_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_ipr_byte_low_reg_reg_get(dev_id, index, ®_val); - *value = reg_val.bf.bytes; - return ret; -} - -sw_error_t -hppe_ipr_byte_low_reg_reg_bytes_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - union ipr_byte_low_reg_reg_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_ipr_byte_low_reg_reg_get(dev_id, index, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.bytes = value; - ret = hppe_ipr_byte_low_reg_reg_set(dev_id, index, ®_val); - return ret; -} - -sw_error_t -hppe_ipr_byte_high_reg_bytes_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union ipr_byte_high_reg_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_ipr_byte_high_reg_get(dev_id, index, ®_val); - *value = reg_val.bf.bytes; - return ret; -} - -sw_error_t -hppe_ipr_byte_high_reg_bytes_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - union ipr_byte_high_reg_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_ipr_byte_high_reg_get(dev_id, index, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.bytes = value; - ret = hppe_ipr_byte_high_reg_set(dev_id, index, ®_val); - return ret; -} -#endif - diff --git a/feeds/ipq807x/qca-ssdk/src/src/hsl/hppe/hppe_portvlan.c b/feeds/ipq807x/qca-ssdk/src/src/hsl/hppe/hppe_portvlan.c deleted file mode 100755 index d38b7820b..000000000 --- a/feeds/ipq807x/qca-ssdk/src/src/hsl/hppe/hppe_portvlan.c +++ /dev/null @@ -1,4108 +0,0 @@ -/* - * Copyright (c) 2016-2017, The Linux Foundation. All rights reserved. - * Permission to use, copy, modify, and/or distribute this software for - * any purpose with or without fee is hereby granted, provided that the - * above copyright notice and this permission notice appear in all copies. - * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES - * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR - * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES - * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN - * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT - * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. - */ - - -/** - * @defgroup - * @{ - */ -#include "sw.h" -#include "hsl.h" -#include "hppe_reg_access.h" -#include "hppe_portvlan_reg.h" -#include "hppe_portvlan.h" - -sw_error_t -hppe_port_parsing_reg_get( - a_uint32_t dev_id, - a_uint32_t index, - union port_parsing_reg_u *value) -{ - if (index >= PORT_PARSING_REG_MAX_ENTRY) - return SW_OUT_OF_RANGE; - return hppe_reg_get( - dev_id, - IPR_CSR_BASE_ADDR + PORT_PARSING_REG_ADDRESS + \ - index * PORT_PARSING_REG_INC, - &value->val); -} - -sw_error_t -hppe_port_parsing_reg_set( - a_uint32_t dev_id, - a_uint32_t index, - union port_parsing_reg_u *value) -{ - return hppe_reg_set( - dev_id, - IPR_CSR_BASE_ADDR + PORT_PARSING_REG_ADDRESS + \ - index * PORT_PARSING_REG_INC, - value->val); -} - -sw_error_t -hppe_edma_vlan_tpid_reg_get( - a_uint32_t dev_id, - union edma_vlan_tpid_reg_u *value) -{ - return hppe_reg_get( - dev_id, - EDMA_CSR_BASE_ADDR + EDMA_VLAN_TPID_REG_ADDRESS, - &value->val); -} - -sw_error_t -hppe_edma_vlan_tpid_reg_set( - a_uint32_t dev_id, - union edma_vlan_tpid_reg_u *value) -{ - return hppe_reg_set( - dev_id, - EDMA_CSR_BASE_ADDR + EDMA_VLAN_TPID_REG_ADDRESS, - value->val); -} - -sw_error_t -hppe_vlan_tpid_reg_get( - a_uint32_t dev_id, - union vlan_tpid_reg_u *value) -{ - return hppe_reg_get( - dev_id, - IPR_CSR_BASE_ADDR + VLAN_TPID_REG_ADDRESS, - &value->val); -} - -sw_error_t -hppe_vlan_tpid_reg_set( - a_uint32_t dev_id, - union vlan_tpid_reg_u *value) -{ - return hppe_reg_set( - dev_id, - IPR_CSR_BASE_ADDR + VLAN_TPID_REG_ADDRESS, - value->val); -} - -sw_error_t -hppe_port_parsing_reg_port_role_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union port_parsing_reg_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_port_parsing_reg_get(dev_id, index, ®_val); - *value = reg_val.bf.port_role; - return ret; -} - -sw_error_t -hppe_port_parsing_reg_port_role_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - union port_parsing_reg_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_port_parsing_reg_get(dev_id, index, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.port_role = value; - ret = hppe_port_parsing_reg_set(dev_id, index, ®_val); - return ret; -} - -sw_error_t -hppe_vlan_tpid_reg_stag_tpid_get( - a_uint32_t dev_id, - a_uint32_t *value) -{ - union vlan_tpid_reg_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_vlan_tpid_reg_get(dev_id, ®_val); - *value = reg_val.bf.stag_tpid; - return ret; -} - -sw_error_t -hppe_vlan_tpid_reg_stag_tpid_set( - a_uint32_t dev_id, - a_uint32_t value) -{ - union vlan_tpid_reg_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_vlan_tpid_reg_get(dev_id, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.stag_tpid = value; - ret = hppe_vlan_tpid_reg_set(dev_id, ®_val); - return ret; -} - -sw_error_t -hppe_vlan_tpid_reg_ctag_tpid_get( - a_uint32_t dev_id, - a_uint32_t *value) -{ - union vlan_tpid_reg_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_vlan_tpid_reg_get(dev_id, ®_val); - *value = reg_val.bf.ctag_tpid; - return ret; -} - -sw_error_t -hppe_vlan_tpid_reg_ctag_tpid_set( - a_uint32_t dev_id, - a_uint32_t value) -{ - union vlan_tpid_reg_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_vlan_tpid_reg_get(dev_id, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.ctag_tpid = value; - ret = hppe_vlan_tpid_reg_set(dev_id, ®_val); - return ret; -} - -sw_error_t -hppe_bridge_config_get( - a_uint32_t dev_id, - union bridge_config_u *value) -{ - return hppe_reg_get( - dev_id, - INGRESS_VLAN_BASE_ADDR + BRIDGE_CONFIG_ADDRESS, - &value->val); -} - -sw_error_t -hppe_bridge_config_set( - a_uint32_t dev_id, - union bridge_config_u *value) -{ - return hppe_reg_set( - dev_id, - INGRESS_VLAN_BASE_ADDR + BRIDGE_CONFIG_ADDRESS, - value->val); -} - -sw_error_t -hppe_port_def_vid_get( - a_uint32_t dev_id, - a_uint32_t port_id, - union port_def_vid_u *value) -{ - return hppe_reg_get( - dev_id, - INGRESS_VLAN_BASE_ADDR + PORT_DEF_VID_ADDRESS + - port_id * PORT_DEF_VID_INC, - &value->val); -} - -sw_error_t -hppe_port_def_vid_set( - a_uint32_t dev_id, - a_uint32_t port_id, - union port_def_vid_u *value) -{ - return hppe_reg_set( - dev_id, - INGRESS_VLAN_BASE_ADDR + PORT_DEF_VID_ADDRESS + - port_id * PORT_DEF_VID_INC, - value->val); -} - -sw_error_t -hppe_port_def_pcp_get( - a_uint32_t dev_id, - a_uint32_t port_id, - union port_def_pcp_u *value) -{ - return hppe_reg_get( - dev_id, - INGRESS_VLAN_BASE_ADDR + PORT_DEF_PCP_ADDRESS + - port_id * PORT_DEF_PCP_INC, - &value->val); -} - -sw_error_t -hppe_port_def_pcp_set( - a_uint32_t dev_id, - a_uint32_t port_id, - union port_def_pcp_u *value) -{ - return hppe_reg_set( - dev_id, - INGRESS_VLAN_BASE_ADDR + PORT_DEF_PCP_ADDRESS + - port_id * PORT_DEF_PCP_INC, - value->val); -} - -sw_error_t -hppe_port_vlan_config_get( - a_uint32_t dev_id, - a_uint32_t port_id, - union port_vlan_config_u *value) -{ - return hppe_reg_get( - dev_id, - INGRESS_VLAN_BASE_ADDR + PORT_VLAN_CONFIG_ADDRESS + - port_id * PORT_VLAN_CONFIG_INC, - &value->val); -} - -sw_error_t -hppe_port_vlan_config_set( - a_uint32_t dev_id, - a_uint32_t port_id, - union port_vlan_config_u *value) -{ - return hppe_reg_set( - dev_id, - INGRESS_VLAN_BASE_ADDR + PORT_VLAN_CONFIG_ADDRESS + - port_id * PORT_VLAN_CONFIG_INC, - value->val); -} - -#ifndef IN_PORTVLAN_MINI -sw_error_t -hppe_iv_dbg_addr_get( - a_uint32_t dev_id, - union iv_dbg_addr_u *value) -{ - return hppe_reg_get( - dev_id, - INGRESS_VLAN_BASE_ADDR + IV_DBG_ADDR_ADDRESS, - &value->val); -} - -sw_error_t -hppe_iv_dbg_addr_set( - a_uint32_t dev_id, - union iv_dbg_addr_u *value) -{ - return hppe_reg_set( - dev_id, - INGRESS_VLAN_BASE_ADDR + IV_DBG_ADDR_ADDRESS, - value->val); -} - -sw_error_t -hppe_iv_dbg_data_get( - a_uint32_t dev_id, - union iv_dbg_data_u *value) -{ - return hppe_reg_get( - dev_id, - INGRESS_VLAN_BASE_ADDR + IV_DBG_DATA_ADDRESS, - &value->val); -} - -sw_error_t -hppe_iv_dbg_data_set( - a_uint32_t dev_id, - union iv_dbg_data_u *value) -{ - return SW_NOT_SUPPORTED; -} - -sw_error_t -hppe_eco_reserve_get( - a_uint32_t dev_id, - union eco_reserve_u *value) -{ - return hppe_reg_get( - dev_id, - INGRESS_VLAN_BASE_ADDR + ECO_RESERVE_ADDRESS, - &value->val); -} - -sw_error_t -hppe_eco_reserve_set( - a_uint32_t dev_id, - union eco_reserve_u *value) -{ - return hppe_reg_set( - dev_id, - INGRESS_VLAN_BASE_ADDR + ECO_RESERVE_ADDRESS, - value->val); -} -#endif - -sw_error_t -hppe_xlt_rule_tbl_get( - a_uint32_t dev_id, - a_uint32_t index, - union xlt_rule_tbl_u *value) -{ - return hppe_reg_tbl_get( - dev_id, - INGRESS_VLAN_BASE_ADDR + XLT_RULE_TBL_ADDRESS + \ - index * XLT_RULE_TBL_INC, - value->val, - 3); -} - -sw_error_t -hppe_xlt_rule_tbl_set( - a_uint32_t dev_id, - a_uint32_t index, - union xlt_rule_tbl_u *value) -{ - return hppe_reg_tbl_set( - dev_id, - INGRESS_VLAN_BASE_ADDR + XLT_RULE_TBL_ADDRESS + \ - index * XLT_RULE_TBL_INC, - value->val, - 3); -} - -sw_error_t -hppe_xlt_action_tbl_get( - a_uint32_t dev_id, - a_uint32_t index, - union xlt_action_tbl_u *value) -{ - return hppe_reg_tbl_get( - dev_id, - INGRESS_VLAN_BASE_ADDR + XLT_ACTION_TBL_ADDRESS + \ - index * XLT_ACTION_TBL_INC, - value->val, - 2); -} - -sw_error_t -hppe_xlt_action_tbl_set( - a_uint32_t dev_id, - a_uint32_t index, - union xlt_action_tbl_u *value) -{ - return hppe_reg_tbl_set( - dev_id, - INGRESS_VLAN_BASE_ADDR + XLT_ACTION_TBL_ADDRESS + \ - index * XLT_ACTION_TBL_INC, - value->val, - 2); -} - -sw_error_t -hppe_bridge_config_bridge_type_get( - a_uint32_t dev_id, - a_uint32_t *value) -{ - union bridge_config_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_bridge_config_get(dev_id, ®_val); - *value = reg_val.bf.bridge_type; - return ret; -} - -sw_error_t -hppe_bridge_config_bridge_type_set( - a_uint32_t dev_id, - a_uint32_t value) -{ - union bridge_config_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_bridge_config_get(dev_id, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.bridge_type = value; - ret = hppe_bridge_config_set(dev_id, ®_val); - return ret; -} - -sw_error_t -hppe_port_def_vid_port_def_cvid_en_get( - a_uint32_t dev_id, - a_uint32_t port_id, - a_uint32_t *value) -{ - union port_def_vid_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_port_def_vid_get(dev_id, port_id, ®_val); - *value = reg_val.bf.port_def_cvid_en; - return ret; -} - -sw_error_t -hppe_port_def_vid_port_def_cvid_en_set( - a_uint32_t dev_id, - a_uint32_t port_id, - a_uint32_t value) -{ - union port_def_vid_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_port_def_vid_get(dev_id, port_id, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.port_def_cvid_en = value; - ret = hppe_port_def_vid_set(dev_id, port_id, ®_val); - return ret; -} - -sw_error_t -hppe_port_def_vid_port_def_svid_en_get( - a_uint32_t dev_id, - a_uint32_t port_id, - a_uint32_t *value) -{ - union port_def_vid_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_port_def_vid_get(dev_id, port_id, ®_val); - *value = reg_val.bf.port_def_svid_en; - return ret; -} - -sw_error_t -hppe_port_def_vid_port_def_svid_en_set( - a_uint32_t dev_id, - a_uint32_t port_id, - a_uint32_t value) -{ - union port_def_vid_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_port_def_vid_get(dev_id, port_id, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.port_def_svid_en = value; - ret = hppe_port_def_vid_set(dev_id, port_id, ®_val); - return ret; -} - -sw_error_t -hppe_port_def_vid_port_def_cvid_get( - a_uint32_t dev_id, - a_uint32_t port_id, - a_uint32_t *value) -{ - union port_def_vid_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_port_def_vid_get(dev_id, port_id, ®_val); - *value = reg_val.bf.port_def_cvid; - return ret; -} - -sw_error_t -hppe_port_def_vid_port_def_cvid_set( - a_uint32_t dev_id, - a_uint32_t port_id, - a_uint32_t value) -{ - union port_def_vid_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_port_def_vid_get(dev_id, port_id, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.port_def_cvid = value; - ret = hppe_port_def_vid_set(dev_id, port_id, ®_val); - return ret; -} - -sw_error_t -hppe_port_def_vid_port_def_svid_get( - a_uint32_t dev_id, - a_uint32_t port_id, - a_uint32_t *value) -{ - union port_def_vid_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_port_def_vid_get(dev_id, port_id, ®_val); - *value = reg_val.bf.port_def_svid; - return ret; -} - -sw_error_t -hppe_port_def_vid_port_def_svid_set( - a_uint32_t dev_id, - a_uint32_t port_id, - a_uint32_t value) -{ - union port_def_vid_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_port_def_vid_get(dev_id, port_id, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.port_def_svid = value; - ret = hppe_port_def_vid_set(dev_id, port_id, ®_val); - return ret; -} - -sw_error_t -hppe_port_def_pcp_port_def_sdei_get( - a_uint32_t dev_id, - a_uint32_t port_id, - a_uint32_t *value) -{ - union port_def_pcp_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_port_def_pcp_get(dev_id, port_id, ®_val); - *value = reg_val.bf.port_def_sdei; - return ret; -} - -sw_error_t -hppe_port_def_pcp_port_def_sdei_set( - a_uint32_t dev_id, - a_uint32_t port_id, - a_uint32_t value) -{ - union port_def_pcp_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_port_def_pcp_get(dev_id, port_id, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.port_def_sdei = value; - ret = hppe_port_def_pcp_set(dev_id, port_id, ®_val); - return ret; -} - -sw_error_t -hppe_port_def_pcp_port_def_spcp_get( - a_uint32_t dev_id, - a_uint32_t port_id, - a_uint32_t *value) -{ - union port_def_pcp_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_port_def_pcp_get(dev_id, port_id, ®_val); - *value = reg_val.bf.port_def_spcp; - return ret; -} - -sw_error_t -hppe_port_def_pcp_port_def_spcp_set( - a_uint32_t dev_id, - a_uint32_t port_id, - a_uint32_t value) -{ - union port_def_pcp_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_port_def_pcp_get(dev_id, port_id, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.port_def_spcp = value; - ret = hppe_port_def_pcp_set(dev_id, port_id, ®_val); - return ret; -} - -sw_error_t -hppe_port_def_pcp_port_def_cdei_get( - a_uint32_t dev_id, - a_uint32_t port_id, - a_uint32_t *value) -{ - union port_def_pcp_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_port_def_pcp_get(dev_id, port_id, ®_val); - *value = reg_val.bf.port_def_cdei; - return ret; -} - -sw_error_t -hppe_port_def_pcp_port_def_cdei_set( - a_uint32_t dev_id, - a_uint32_t port_id, - a_uint32_t value) -{ - union port_def_pcp_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_port_def_pcp_get(dev_id, port_id, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.port_def_cdei = value; - ret = hppe_port_def_pcp_set(dev_id, port_id, ®_val); - return ret; -} - -sw_error_t -hppe_port_def_pcp_port_def_cpcp_get( - a_uint32_t dev_id, - a_uint32_t port_id, - a_uint32_t *value) -{ - union port_def_pcp_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_port_def_pcp_get(dev_id, port_id, ®_val); - *value = reg_val.bf.port_def_cpcp; - return ret; -} - -sw_error_t -hppe_port_def_pcp_port_def_cpcp_set( - a_uint32_t dev_id, - a_uint32_t port_id, - a_uint32_t value) -{ - union port_def_pcp_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_port_def_pcp_get(dev_id, port_id, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.port_def_cpcp = value; - ret = hppe_port_def_pcp_set(dev_id, port_id, ®_val); - return ret; -} - -sw_error_t -hppe_port_vlan_config_port_in_dei_prop_cmd_get( - a_uint32_t dev_id, - a_uint32_t port_id, - a_uint32_t *value) -{ - union port_vlan_config_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_port_vlan_config_get(dev_id, port_id, ®_val); - *value = reg_val.bf.port_in_dei_prop_cmd; - return ret; -} - -sw_error_t -hppe_port_vlan_config_port_in_dei_prop_cmd_set( - a_uint32_t dev_id, - a_uint32_t port_id, - a_uint32_t value) -{ - union port_vlan_config_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_port_vlan_config_get(dev_id, port_id, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.port_in_dei_prop_cmd = value; - ret = hppe_port_vlan_config_set(dev_id, port_id, ®_val); - return ret; -} - -sw_error_t -hppe_port_vlan_config_port_in_pcp_prop_cmd_get( - a_uint32_t dev_id, - a_uint32_t port_id, - a_uint32_t *value) -{ - union port_vlan_config_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_port_vlan_config_get(dev_id, port_id, ®_val); - *value = reg_val.bf.port_in_pcp_prop_cmd; - return ret; -} - -sw_error_t -hppe_port_vlan_config_port_in_pcp_prop_cmd_set( - a_uint32_t dev_id, - a_uint32_t port_id, - a_uint32_t value) -{ - union port_vlan_config_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_port_vlan_config_get(dev_id, port_id, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.port_in_pcp_prop_cmd = value; - ret = hppe_port_vlan_config_set(dev_id, port_id, ®_val); - return ret; -} - -sw_error_t -hppe_port_vlan_config_port_untag_fltr_cmd_get( - a_uint32_t dev_id, - a_uint32_t port_id, - a_uint32_t *value) -{ - union port_vlan_config_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_port_vlan_config_get(dev_id, port_id, ®_val); - *value = reg_val.bf.port_untag_fltr_cmd; - return ret; -} - -sw_error_t -hppe_port_vlan_config_port_untag_fltr_cmd_set( - a_uint32_t dev_id, - a_uint32_t port_id, - a_uint32_t value) -{ - union port_vlan_config_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_port_vlan_config_get(dev_id, port_id, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.port_untag_fltr_cmd = value; - ret = hppe_port_vlan_config_set(dev_id, port_id, ®_val); - return ret; -} - -sw_error_t -hppe_port_vlan_config_port_in_vlan_fltr_cmd_get( - a_uint32_t dev_id, - a_uint32_t port_id, - a_uint32_t *value) -{ - union port_vlan_config_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_port_vlan_config_get(dev_id, port_id, ®_val); - *value = reg_val.bf.port_in_vlan_fltr_cmd; - return ret; -} - -sw_error_t -hppe_port_vlan_config_port_in_vlan_fltr_cmd_set( - a_uint32_t dev_id, - a_uint32_t port_id, - a_uint32_t value) -{ - union port_vlan_config_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_port_vlan_config_get(dev_id, port_id, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.port_in_vlan_fltr_cmd = value; - ret = hppe_port_vlan_config_set(dev_id, port_id, ®_val); - return ret; -} - -sw_error_t -hppe_port_vlan_config_port_pri_tag_fltr_cmd_get( - a_uint32_t dev_id, - a_uint32_t port_id, - a_uint32_t *value) -{ - union port_vlan_config_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_port_vlan_config_get(dev_id, port_id, ®_val); - *value = reg_val.bf.port_pri_tag_fltr_cmd; - return ret; -} - -sw_error_t -hppe_port_vlan_config_port_pri_tag_fltr_cmd_set( - a_uint32_t dev_id, - a_uint32_t port_id, - a_uint32_t value) -{ - union port_vlan_config_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_port_vlan_config_get(dev_id, port_id, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.port_pri_tag_fltr_cmd = value; - ret = hppe_port_vlan_config_set(dev_id, port_id, ®_val); - return ret; -} - -sw_error_t -hppe_port_vlan_config_port_vlan_xlt_miss_fwd_cmd_get( - a_uint32_t dev_id, - a_uint32_t port_id, - a_uint32_t *value) -{ - union port_vlan_config_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_port_vlan_config_get(dev_id, port_id, ®_val); - *value = reg_val.bf.port_vlan_xlt_miss_fwd_cmd; - return ret; -} - -sw_error_t -hppe_port_vlan_config_port_vlan_xlt_miss_fwd_cmd_set( - a_uint32_t dev_id, - a_uint32_t port_id, - a_uint32_t value) -{ - union port_vlan_config_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_port_vlan_config_get(dev_id, port_id, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.port_vlan_xlt_miss_fwd_cmd = value; - ret = hppe_port_vlan_config_set(dev_id, port_id, ®_val); - return ret; -} - -sw_error_t -hppe_port_vlan_config_port_tag_fltr_cmd_get( - a_uint32_t dev_id, - a_uint32_t port_id, - a_uint32_t *value) -{ - union port_vlan_config_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_port_vlan_config_get(dev_id, port_id, ®_val); - *value = reg_val.bf.port_tag_fltr_cmd; - return ret; -} - -sw_error_t -hppe_port_vlan_config_port_tag_fltr_cmd_set( - a_uint32_t dev_id, - a_uint32_t port_id, - a_uint32_t value) -{ - union port_vlan_config_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_port_vlan_config_get(dev_id, port_id, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.port_tag_fltr_cmd = value; - ret = hppe_port_vlan_config_set(dev_id, port_id, ®_val); - return ret; -} - -#ifndef IN_PORTVLAN_MINI -sw_error_t -hppe_iv_dbg_addr_dbg_addr_get( - a_uint32_t dev_id, - a_uint32_t *value) -{ - union iv_dbg_addr_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_iv_dbg_addr_get(dev_id, ®_val); - *value = reg_val.bf.dbg_addr; - return ret; -} - -sw_error_t -hppe_iv_dbg_addr_dbg_addr_set( - a_uint32_t dev_id, - a_uint32_t value) -{ - union iv_dbg_addr_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_iv_dbg_addr_get(dev_id, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.dbg_addr = value; - ret = hppe_iv_dbg_addr_set(dev_id, ®_val); - return ret; -} - -sw_error_t -hppe_iv_dbg_data_dbg_data_get( - a_uint32_t dev_id, - a_uint32_t *value) -{ - union iv_dbg_data_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_iv_dbg_data_get(dev_id, ®_val); - *value = reg_val.bf.dbg_data; - return ret; -} - -sw_error_t -hppe_iv_dbg_data_dbg_data_set( - a_uint32_t dev_id, - a_uint32_t value) -{ - return SW_NOT_SUPPORTED; -} - -sw_error_t -hppe_eco_reserve_eco_res_get( - a_uint32_t dev_id, - a_uint32_t *value) -{ - union eco_reserve_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_eco_reserve_get(dev_id, ®_val); - *value = reg_val.bf.eco_res; - return ret; -} - -sw_error_t -hppe_eco_reserve_eco_res_set( - a_uint32_t dev_id, - a_uint32_t value) -{ - union eco_reserve_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_eco_reserve_get(dev_id, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.eco_res = value; - ret = hppe_eco_reserve_set(dev_id, ®_val); - return ret; -} -#endif - -sw_error_t -hppe_xlt_rule_tbl_ckey_vid_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union xlt_rule_tbl_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_xlt_rule_tbl_get(dev_id, index, ®_val); - *value = reg_val.bf.ckey_vid; - return ret; -} - -sw_error_t -hppe_xlt_rule_tbl_ckey_vid_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - union xlt_rule_tbl_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_xlt_rule_tbl_get(dev_id, index, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.ckey_vid = value; - ret = hppe_xlt_rule_tbl_set(dev_id, index, ®_val); - return ret; -} - -sw_error_t -hppe_xlt_rule_tbl_frm_type_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union xlt_rule_tbl_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_xlt_rule_tbl_get(dev_id, index, ®_val); - *value = reg_val.bf.frm_type; - return ret; -} - -sw_error_t -hppe_xlt_rule_tbl_frm_type_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - union xlt_rule_tbl_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_xlt_rule_tbl_get(dev_id, index, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.frm_type = value; - ret = hppe_xlt_rule_tbl_set(dev_id, index, ®_val); - return ret; -} - -sw_error_t -hppe_xlt_rule_tbl_prot_value_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union xlt_rule_tbl_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_xlt_rule_tbl_get(dev_id, index, ®_val); - *value = reg_val.bf.prot_value_1 << 7 | \ - reg_val.bf.prot_value_0; - return ret; -} - -sw_error_t -hppe_xlt_rule_tbl_prot_value_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - union xlt_rule_tbl_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_xlt_rule_tbl_get(dev_id, index, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.prot_value_1 = value >> 7; - reg_val.bf.prot_value_0 = value & (((a_uint64_t)1<<7)-1); - ret = hppe_xlt_rule_tbl_set(dev_id, index, ®_val); - return ret; -} - -sw_error_t -hppe_xlt_rule_tbl_valid_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union xlt_rule_tbl_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_xlt_rule_tbl_get(dev_id, index, ®_val); - *value = reg_val.bf.valid; - return ret; -} - -sw_error_t -hppe_xlt_rule_tbl_valid_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - union xlt_rule_tbl_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_xlt_rule_tbl_get(dev_id, index, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.valid = value; - ret = hppe_xlt_rule_tbl_set(dev_id, index, ®_val); - return ret; -} - -sw_error_t -hppe_xlt_rule_tbl_frm_type_incl_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union xlt_rule_tbl_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_xlt_rule_tbl_get(dev_id, index, ®_val); - *value = reg_val.bf.frm_type_incl; - return ret; -} - -sw_error_t -hppe_xlt_rule_tbl_frm_type_incl_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - union xlt_rule_tbl_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_xlt_rule_tbl_get(dev_id, index, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.frm_type_incl = value; - ret = hppe_xlt_rule_tbl_set(dev_id, index, ®_val); - return ret; -} - -sw_error_t -hppe_xlt_rule_tbl_ckey_dei_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union xlt_rule_tbl_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_xlt_rule_tbl_get(dev_id, index, ®_val); - *value = reg_val.bf.ckey_dei; - return ret; -} - -sw_error_t -hppe_xlt_rule_tbl_ckey_dei_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - union xlt_rule_tbl_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_xlt_rule_tbl_get(dev_id, index, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.ckey_dei = value; - ret = hppe_xlt_rule_tbl_set(dev_id, index, ®_val); - return ret; -} - -sw_error_t -hppe_xlt_rule_tbl_skey_dei_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union xlt_rule_tbl_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_xlt_rule_tbl_get(dev_id, index, ®_val); - *value = reg_val.bf.skey_dei; - return ret; -} - -sw_error_t -hppe_xlt_rule_tbl_skey_dei_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - union xlt_rule_tbl_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_xlt_rule_tbl_get(dev_id, index, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.skey_dei = value; - ret = hppe_xlt_rule_tbl_set(dev_id, index, ®_val); - return ret; -} - -sw_error_t -hppe_xlt_rule_tbl_skey_pcp_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union xlt_rule_tbl_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_xlt_rule_tbl_get(dev_id, index, ®_val); - *value = reg_val.bf.skey_pcp; - return ret; -} - -sw_error_t -hppe_xlt_rule_tbl_skey_pcp_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - union xlt_rule_tbl_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_xlt_rule_tbl_get(dev_id, index, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.skey_pcp = value; - ret = hppe_xlt_rule_tbl_set(dev_id, index, ®_val); - return ret; -} - -sw_error_t -hppe_xlt_rule_tbl_ckey_pcp_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union xlt_rule_tbl_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_xlt_rule_tbl_get(dev_id, index, ®_val); - *value = reg_val.bf.ckey_pcp; - return ret; -} - -sw_error_t -hppe_xlt_rule_tbl_ckey_pcp_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - union xlt_rule_tbl_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_xlt_rule_tbl_get(dev_id, index, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.ckey_pcp = value; - ret = hppe_xlt_rule_tbl_set(dev_id, index, ®_val); - return ret; -} - -sw_error_t -hppe_xlt_rule_tbl_ckey_vid_incl_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union xlt_rule_tbl_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_xlt_rule_tbl_get(dev_id, index, ®_val); - *value = reg_val.bf.ckey_vid_incl; - return ret; -} - -sw_error_t -hppe_xlt_rule_tbl_ckey_vid_incl_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - union xlt_rule_tbl_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_xlt_rule_tbl_get(dev_id, index, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.ckey_vid_incl = value; - ret = hppe_xlt_rule_tbl_set(dev_id, index, ®_val); - return ret; -} - -sw_error_t -hppe_xlt_rule_tbl_ckey_dei_incl_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union xlt_rule_tbl_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_xlt_rule_tbl_get(dev_id, index, ®_val); - *value = reg_val.bf.ckey_dei_incl; - return ret; -} - -sw_error_t -hppe_xlt_rule_tbl_ckey_dei_incl_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - union xlt_rule_tbl_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_xlt_rule_tbl_get(dev_id, index, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.ckey_dei_incl = value; - ret = hppe_xlt_rule_tbl_set(dev_id, index, ®_val); - return ret; -} - -sw_error_t -hppe_xlt_rule_tbl_port_bitmap_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union xlt_rule_tbl_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_xlt_rule_tbl_get(dev_id, index, ®_val); - *value = reg_val.bf.port_bitmap; - return ret; -} - -sw_error_t -hppe_xlt_rule_tbl_port_bitmap_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - union xlt_rule_tbl_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_xlt_rule_tbl_get(dev_id, index, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.port_bitmap = value; - ret = hppe_xlt_rule_tbl_set(dev_id, index, ®_val); - return ret; -} - -sw_error_t -hppe_xlt_rule_tbl_prot_incl_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union xlt_rule_tbl_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_xlt_rule_tbl_get(dev_id, index, ®_val); - *value = reg_val.bf.prot_incl; - return ret; -} - -sw_error_t -hppe_xlt_rule_tbl_prot_incl_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - union xlt_rule_tbl_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_xlt_rule_tbl_get(dev_id, index, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.prot_incl = value; - ret = hppe_xlt_rule_tbl_set(dev_id, index, ®_val); - return ret; -} - -sw_error_t -hppe_xlt_rule_tbl_skey_pcp_incl_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union xlt_rule_tbl_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_xlt_rule_tbl_get(dev_id, index, ®_val); - *value = reg_val.bf.skey_pcp_incl; - return ret; -} - -sw_error_t -hppe_xlt_rule_tbl_skey_pcp_incl_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - union xlt_rule_tbl_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_xlt_rule_tbl_get(dev_id, index, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.skey_pcp_incl = value; - ret = hppe_xlt_rule_tbl_set(dev_id, index, ®_val); - return ret; -} - -sw_error_t -hppe_xlt_rule_tbl_ckey_fmt_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union xlt_rule_tbl_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_xlt_rule_tbl_get(dev_id, index, ®_val); - *value = reg_val.bf.ckey_fmt_1 << 1 | \ - reg_val.bf.ckey_fmt_0; - return ret; -} - -sw_error_t -hppe_xlt_rule_tbl_ckey_fmt_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - union xlt_rule_tbl_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_xlt_rule_tbl_get(dev_id, index, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.ckey_fmt_1 = value >> 1; - reg_val.bf.ckey_fmt_0 = value & (((a_uint64_t)1<<1)-1); - ret = hppe_xlt_rule_tbl_set(dev_id, index, ®_val); - return ret; -} - -sw_error_t -hppe_xlt_rule_tbl_skey_vid_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union xlt_rule_tbl_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_xlt_rule_tbl_get(dev_id, index, ®_val); - *value = reg_val.bf.skey_vid; - return ret; -} - -sw_error_t -hppe_xlt_rule_tbl_skey_vid_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - union xlt_rule_tbl_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_xlt_rule_tbl_get(dev_id, index, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.skey_vid = value; - ret = hppe_xlt_rule_tbl_set(dev_id, index, ®_val); - return ret; -} - -sw_error_t -hppe_xlt_rule_tbl_skey_fmt_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union xlt_rule_tbl_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_xlt_rule_tbl_get(dev_id, index, ®_val); - *value = reg_val.bf.skey_fmt; - return ret; -} - -sw_error_t -hppe_xlt_rule_tbl_skey_fmt_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - union xlt_rule_tbl_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_xlt_rule_tbl_get(dev_id, index, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.skey_fmt = value; - ret = hppe_xlt_rule_tbl_set(dev_id, index, ®_val); - return ret; -} - -sw_error_t -hppe_xlt_rule_tbl_ckey_pcp_incl_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union xlt_rule_tbl_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_xlt_rule_tbl_get(dev_id, index, ®_val); - *value = reg_val.bf.ckey_pcp_incl; - return ret; -} - -sw_error_t -hppe_xlt_rule_tbl_ckey_pcp_incl_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - union xlt_rule_tbl_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_xlt_rule_tbl_get(dev_id, index, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.ckey_pcp_incl = value; - ret = hppe_xlt_rule_tbl_set(dev_id, index, ®_val); - return ret; -} - -sw_error_t -hppe_xlt_rule_tbl_skey_dei_incl_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union xlt_rule_tbl_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_xlt_rule_tbl_get(dev_id, index, ®_val); - *value = reg_val.bf.skey_dei_incl; - return ret; -} - -sw_error_t -hppe_xlt_rule_tbl_skey_dei_incl_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - union xlt_rule_tbl_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_xlt_rule_tbl_get(dev_id, index, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.skey_dei_incl = value; - ret = hppe_xlt_rule_tbl_set(dev_id, index, ®_val); - return ret; -} - -sw_error_t -hppe_xlt_rule_tbl_skey_vid_incl_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union xlt_rule_tbl_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_xlt_rule_tbl_get(dev_id, index, ®_val); - *value = reg_val.bf.skey_vid_incl; - return ret; -} - -sw_error_t -hppe_xlt_rule_tbl_skey_vid_incl_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - union xlt_rule_tbl_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_xlt_rule_tbl_get(dev_id, index, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.skey_vid_incl = value; - ret = hppe_xlt_rule_tbl_set(dev_id, index, ®_val); - return ret; -} - -sw_error_t -hppe_xlt_action_tbl_dei_swap_cmd_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union xlt_action_tbl_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_xlt_action_tbl_get(dev_id, index, ®_val); - *value = reg_val.bf.dei_swap_cmd; - return ret; -} - -sw_error_t -hppe_xlt_action_tbl_dei_swap_cmd_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - union xlt_action_tbl_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_xlt_action_tbl_get(dev_id, index, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.dei_swap_cmd = value; - ret = hppe_xlt_action_tbl_set(dev_id, index, ®_val); - return ret; -} - -sw_error_t -hppe_xlt_action_tbl_xlt_cvid_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union xlt_action_tbl_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_xlt_action_tbl_get(dev_id, index, ®_val); - *value = reg_val.bf.xlt_cvid; - return ret; -} - -sw_error_t -hppe_xlt_action_tbl_xlt_cvid_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - union xlt_action_tbl_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_xlt_action_tbl_get(dev_id, index, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.xlt_cvid = value; - ret = hppe_xlt_action_tbl_set(dev_id, index, ®_val); - return ret; -} - -sw_error_t -hppe_xlt_action_tbl_xlt_cpcp_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union xlt_action_tbl_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_xlt_action_tbl_get(dev_id, index, ®_val); - *value = reg_val.bf.xlt_cpcp; - return ret; -} - -sw_error_t -hppe_xlt_action_tbl_xlt_cpcp_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - union xlt_action_tbl_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_xlt_action_tbl_get(dev_id, index, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.xlt_cpcp = value; - ret = hppe_xlt_action_tbl_set(dev_id, index, ®_val); - return ret; -} - -sw_error_t -hppe_xlt_action_tbl_xlt_spcp_cmd_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union xlt_action_tbl_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_xlt_action_tbl_get(dev_id, index, ®_val); - *value = reg_val.bf.xlt_spcp_cmd; - return ret; -} - -sw_error_t -hppe_xlt_action_tbl_xlt_spcp_cmd_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - union xlt_action_tbl_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_xlt_action_tbl_get(dev_id, index, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.xlt_spcp_cmd = value; - ret = hppe_xlt_action_tbl_set(dev_id, index, ®_val); - return ret; -} - -sw_error_t -hppe_xlt_action_tbl_xlt_sdei_cmd_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union xlt_action_tbl_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_xlt_action_tbl_get(dev_id, index, ®_val); - *value = reg_val.bf.xlt_sdei_cmd; - return ret; -} - -sw_error_t -hppe_xlt_action_tbl_xlt_sdei_cmd_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - union xlt_action_tbl_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_xlt_action_tbl_get(dev_id, index, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.xlt_sdei_cmd = value; - ret = hppe_xlt_action_tbl_set(dev_id, index, ®_val); - return ret; -} - -sw_error_t -hppe_xlt_action_tbl_xlt_cvid_cmd_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union xlt_action_tbl_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_xlt_action_tbl_get(dev_id, index, ®_val); - *value = reg_val.bf.xlt_cvid_cmd; - return ret; -} - -sw_error_t -hppe_xlt_action_tbl_xlt_cvid_cmd_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - union xlt_action_tbl_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_xlt_action_tbl_get(dev_id, index, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.xlt_cvid_cmd = value; - ret = hppe_xlt_action_tbl_set(dev_id, index, ®_val); - return ret; -} - -sw_error_t -hppe_xlt_action_tbl_vsi_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union xlt_action_tbl_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_xlt_action_tbl_get(dev_id, index, ®_val); - *value = reg_val.bf.vsi; - return ret; -} - -sw_error_t -hppe_xlt_action_tbl_vsi_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - union xlt_action_tbl_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_xlt_action_tbl_get(dev_id, index, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.vsi = value; - ret = hppe_xlt_action_tbl_set(dev_id, index, ®_val); - return ret; -} - -sw_error_t -hppe_xlt_action_tbl_xlt_spcp_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union xlt_action_tbl_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_xlt_action_tbl_get(dev_id, index, ®_val); - *value = reg_val.bf.xlt_spcp_1 << 1 | \ - reg_val.bf.xlt_spcp_0; - return ret; -} - -sw_error_t -hppe_xlt_action_tbl_xlt_spcp_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - union xlt_action_tbl_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_xlt_action_tbl_get(dev_id, index, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.xlt_spcp_1 = value >> 1; - reg_val.bf.xlt_spcp_0 = value & (((a_uint64_t)1<<1)-1); - ret = hppe_xlt_action_tbl_set(dev_id, index, ®_val); - return ret; -} - -sw_error_t -hppe_xlt_action_tbl_counter_id_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union xlt_action_tbl_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_xlt_action_tbl_get(dev_id, index, ®_val); - *value = reg_val.bf.counter_id; - return ret; -} - -sw_error_t -hppe_xlt_action_tbl_counter_id_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - union xlt_action_tbl_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_xlt_action_tbl_get(dev_id, index, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.counter_id = value; - ret = hppe_xlt_action_tbl_set(dev_id, index, ®_val); - return ret; -} - -sw_error_t -hppe_xlt_action_tbl_vid_swap_cmd_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union xlt_action_tbl_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_xlt_action_tbl_get(dev_id, index, ®_val); - *value = reg_val.bf.vid_swap_cmd; - return ret; -} - -sw_error_t -hppe_xlt_action_tbl_vid_swap_cmd_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - union xlt_action_tbl_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_xlt_action_tbl_get(dev_id, index, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.vid_swap_cmd = value; - ret = hppe_xlt_action_tbl_set(dev_id, index, ®_val); - return ret; -} - -sw_error_t -hppe_xlt_action_tbl_xlt_sdei_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union xlt_action_tbl_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_xlt_action_tbl_get(dev_id, index, ®_val); - *value = reg_val.bf.xlt_sdei; - return ret; -} - -sw_error_t -hppe_xlt_action_tbl_xlt_sdei_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - union xlt_action_tbl_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_xlt_action_tbl_get(dev_id, index, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.xlt_sdei = value; - ret = hppe_xlt_action_tbl_set(dev_id, index, ®_val); - return ret; -} - -sw_error_t -hppe_xlt_action_tbl_counter_en_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union xlt_action_tbl_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_xlt_action_tbl_get(dev_id, index, ®_val); - *value = reg_val.bf.counter_en; - return ret; -} - -sw_error_t -hppe_xlt_action_tbl_counter_en_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - union xlt_action_tbl_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_xlt_action_tbl_get(dev_id, index, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.counter_en = value; - ret = hppe_xlt_action_tbl_set(dev_id, index, ®_val); - return ret; -} - -sw_error_t -hppe_xlt_action_tbl_xlt_svid_cmd_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union xlt_action_tbl_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_xlt_action_tbl_get(dev_id, index, ®_val); - *value = reg_val.bf.xlt_svid_cmd; - return ret; -} - -sw_error_t -hppe_xlt_action_tbl_xlt_svid_cmd_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - union xlt_action_tbl_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_xlt_action_tbl_get(dev_id, index, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.xlt_svid_cmd = value; - ret = hppe_xlt_action_tbl_set(dev_id, index, ®_val); - return ret; -} - -sw_error_t -hppe_xlt_action_tbl_xlt_svid_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union xlt_action_tbl_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_xlt_action_tbl_get(dev_id, index, ®_val); - *value = reg_val.bf.xlt_svid; - return ret; -} - -sw_error_t -hppe_xlt_action_tbl_xlt_svid_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - union xlt_action_tbl_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_xlt_action_tbl_get(dev_id, index, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.xlt_svid = value; - ret = hppe_xlt_action_tbl_set(dev_id, index, ®_val); - return ret; -} - -sw_error_t -hppe_xlt_action_tbl_vsi_cmd_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union xlt_action_tbl_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_xlt_action_tbl_get(dev_id, index, ®_val); - *value = reg_val.bf.vsi_cmd; - return ret; -} - -sw_error_t -hppe_xlt_action_tbl_vsi_cmd_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - union xlt_action_tbl_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_xlt_action_tbl_get(dev_id, index, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.vsi_cmd = value; - ret = hppe_xlt_action_tbl_set(dev_id, index, ®_val); - return ret; -} - -sw_error_t -hppe_xlt_action_tbl_xlt_cpcp_cmd_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union xlt_action_tbl_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_xlt_action_tbl_get(dev_id, index, ®_val); - *value = reg_val.bf.xlt_cpcp_cmd; - return ret; -} - -sw_error_t -hppe_xlt_action_tbl_xlt_cpcp_cmd_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - union xlt_action_tbl_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_xlt_action_tbl_get(dev_id, index, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.xlt_cpcp_cmd = value; - ret = hppe_xlt_action_tbl_set(dev_id, index, ®_val); - return ret; -} - -sw_error_t -hppe_xlt_action_tbl_xlt_cdei_cmd_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union xlt_action_tbl_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_xlt_action_tbl_get(dev_id, index, ®_val); - *value = reg_val.bf.xlt_cdei_cmd; - return ret; -} - -sw_error_t -hppe_xlt_action_tbl_xlt_cdei_cmd_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - union xlt_action_tbl_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_xlt_action_tbl_get(dev_id, index, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.xlt_cdei_cmd = value; - ret = hppe_xlt_action_tbl_set(dev_id, index, ®_val); - return ret; -} - -sw_error_t -hppe_xlt_action_tbl_pcp_swap_cmd_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union xlt_action_tbl_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_xlt_action_tbl_get(dev_id, index, ®_val); - *value = reg_val.bf.pcp_swap_cmd; - return ret; -} - -sw_error_t -hppe_xlt_action_tbl_pcp_swap_cmd_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - union xlt_action_tbl_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_xlt_action_tbl_get(dev_id, index, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.pcp_swap_cmd = value; - ret = hppe_xlt_action_tbl_set(dev_id, index, ®_val); - return ret; -} - -sw_error_t -hppe_xlt_action_tbl_xlt_cdei_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union xlt_action_tbl_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_xlt_action_tbl_get(dev_id, index, ®_val); - *value = reg_val.bf.xlt_cdei; - return ret; -} - -sw_error_t -hppe_xlt_action_tbl_xlt_cdei_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - union xlt_action_tbl_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_xlt_action_tbl_get(dev_id, index, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.xlt_cdei = value; - ret = hppe_xlt_action_tbl_set(dev_id, index, ®_val); - return ret; -} - -sw_error_t -hppe_eg_vlan_xlt_rule_get( - a_uint32_t dev_id, - a_uint32_t index, - union eg_vlan_xlt_rule_u *value) -{ - return hppe_reg_tbl_get( - dev_id, - NSS_PTX_CSR_BASE_ADDR + EG_VLAN_XLT_RULE_ADDRESS + \ - index * EG_VLAN_XLT_RULE_INC, - value->val, - 2); -} - -sw_error_t -hppe_eg_vlan_xlt_rule_set( - a_uint32_t dev_id, - a_uint32_t index, - union eg_vlan_xlt_rule_u *value) -{ - return hppe_reg_tbl_set( - dev_id, - NSS_PTX_CSR_BASE_ADDR + EG_VLAN_XLT_RULE_ADDRESS + \ - index * EG_VLAN_XLT_RULE_INC, - value->val, - 2); -} - -sw_error_t -hppe_eg_vsi_tag_get( - a_uint32_t dev_id, - a_uint32_t index, - union eg_vsi_tag_u *value) -{ - if (index >= EG_VSI_TAG_NUM) - return SW_OUT_OF_RANGE; - return hppe_reg_get( - dev_id, - NSS_PTX_CSR_BASE_ADDR + EG_VSI_TAG_ADDRESS + \ - index * EG_VSI_TAG_INC, - &value->val); -} - -sw_error_t -hppe_eg_vsi_tag_set( - a_uint32_t dev_id, - a_uint32_t index, - union eg_vsi_tag_u *value) -{ - return hppe_reg_set( - dev_id, - NSS_PTX_CSR_BASE_ADDR + EG_VSI_TAG_ADDRESS + \ - index * EG_VSI_TAG_INC, - value->val); -} - -sw_error_t -hppe_port_eg_def_vid_get( - a_uint32_t dev_id, - a_uint32_t index, - union port_eg_def_vid_u *value) -{ - if (index >= PORT_EG_DEF_VID_MAX_ENTRY) - return SW_OUT_OF_RANGE; - return hppe_reg_get( - dev_id, - NSS_PTX_CSR_BASE_ADDR + PORT_EG_DEF_VID_ADDRESS + \ - index * PORT_EG_DEF_VID_INC, - &value->val); -} - -sw_error_t -hppe_port_eg_def_vid_set( - a_uint32_t dev_id, - a_uint32_t index, - union port_eg_def_vid_u *value) -{ - return hppe_reg_set( - dev_id, - NSS_PTX_CSR_BASE_ADDR + PORT_EG_DEF_VID_ADDRESS + \ - index * PORT_EG_DEF_VID_INC, - value->val); -} - -sw_error_t -hppe_port_eg_vlan_get( - a_uint32_t dev_id, - a_uint32_t index, - union port_eg_vlan_u *value) -{ - if (index >= PORT_EG_VLAN_MAX_ENTRY) - return SW_OUT_OF_RANGE; - return hppe_reg_get( - dev_id, - NSS_PTX_CSR_BASE_ADDR + PORT_EG_VLAN_ADDRESS + \ - index * PORT_EG_VLAN_INC, - &value->val); -} - -sw_error_t -hppe_port_eg_vlan_set( - a_uint32_t dev_id, - a_uint32_t index, - union port_eg_vlan_u *value) -{ - return hppe_reg_set( - dev_id, - NSS_PTX_CSR_BASE_ADDR + PORT_EG_VLAN_ADDRESS + \ - index * PORT_EG_VLAN_INC, - value->val); -} - -sw_error_t -hppe_eg_vlan_tpid_get( - a_uint32_t dev_id, - union eg_vlan_tpid_u *value) -{ - return hppe_reg_get( - dev_id, - NSS_PTX_CSR_BASE_ADDR + EG_VLAN_TPID_ADDRESS, - &value->val); -} - -sw_error_t -hppe_eg_vlan_tpid_set( - a_uint32_t dev_id, - union eg_vlan_tpid_u *value) -{ - return hppe_reg_set( - dev_id, - NSS_PTX_CSR_BASE_ADDR + EG_VLAN_TPID_ADDRESS, - value->val); -} - -sw_error_t -hppe_eg_bridge_config_get( - a_uint32_t dev_id, - union eg_bridge_config_u *value) -{ - return hppe_reg_get( - dev_id, - NSS_PTX_CSR_BASE_ADDR + EG_BRIDGE_CONFIG_ADDRESS, - &value->val); -} - -sw_error_t -hppe_eg_bridge_config_set( - a_uint32_t dev_id, - union eg_bridge_config_u *value) -{ - return hppe_reg_set( - dev_id, - NSS_PTX_CSR_BASE_ADDR + EG_BRIDGE_CONFIG_ADDRESS, - value->val); -} - -sw_error_t -hppe_eg_vlan_xlt_action_get( - a_uint32_t dev_id, - a_uint32_t index, - union eg_vlan_xlt_action_u *value) -{ - return hppe_reg_tbl_get( - dev_id, - NSS_PTX_CSR_BASE_ADDR + EG_VLAN_XLT_ACTION_ADDRESS + \ - index * EG_VLAN_XLT_ACTION_INC, - value->val, - 2); -} - -sw_error_t -hppe_eg_vlan_xlt_action_set( - a_uint32_t dev_id, - a_uint32_t index, - union eg_vlan_xlt_action_u *value) -{ - return hppe_reg_tbl_set( - dev_id, - NSS_PTX_CSR_BASE_ADDR + EG_VLAN_XLT_ACTION_ADDRESS + \ - index * EG_VLAN_XLT_ACTION_INC, - value->val, - 2); -} - -sw_error_t -hppe_eg_vlan_xlt_rule_ckey_vid_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union eg_vlan_xlt_rule_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_eg_vlan_xlt_rule_get(dev_id, index, ®_val); - *value = reg_val.bf.ckey_vid; - return ret; -} - -sw_error_t -hppe_eg_vlan_xlt_rule_ckey_vid_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - union eg_vlan_xlt_rule_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_eg_vlan_xlt_rule_get(dev_id, index, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.ckey_vid = value; - ret = hppe_eg_vlan_xlt_rule_set(dev_id, index, ®_val); - return ret; -} - -sw_error_t -hppe_eg_vlan_xlt_rule_valid_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union eg_vlan_xlt_rule_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_eg_vlan_xlt_rule_get(dev_id, index, ®_val); - *value = reg_val.bf.valid; - return ret; -} - -sw_error_t -hppe_eg_vlan_xlt_rule_valid_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - union eg_vlan_xlt_rule_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_eg_vlan_xlt_rule_get(dev_id, index, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.valid = value; - ret = hppe_eg_vlan_xlt_rule_set(dev_id, index, ®_val); - return ret; -} - -sw_error_t -hppe_eg_vlan_xlt_rule_ckey_dei_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union eg_vlan_xlt_rule_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_eg_vlan_xlt_rule_get(dev_id, index, ®_val); - *value = reg_val.bf.ckey_dei; - return ret; -} - -sw_error_t -hppe_eg_vlan_xlt_rule_ckey_dei_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - union eg_vlan_xlt_rule_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_eg_vlan_xlt_rule_get(dev_id, index, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.ckey_dei = value; - ret = hppe_eg_vlan_xlt_rule_set(dev_id, index, ®_val); - return ret; -} - -sw_error_t -hppe_eg_vlan_xlt_rule_skey_dei_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union eg_vlan_xlt_rule_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_eg_vlan_xlt_rule_get(dev_id, index, ®_val); - *value = reg_val.bf.skey_dei; - return ret; -} - -sw_error_t -hppe_eg_vlan_xlt_rule_skey_dei_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - union eg_vlan_xlt_rule_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_eg_vlan_xlt_rule_get(dev_id, index, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.skey_dei = value; - ret = hppe_eg_vlan_xlt_rule_set(dev_id, index, ®_val); - return ret; -} - -sw_error_t -hppe_eg_vlan_xlt_rule_skey_pcp_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union eg_vlan_xlt_rule_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_eg_vlan_xlt_rule_get(dev_id, index, ®_val); - *value = reg_val.bf.skey_pcp; - return ret; -} - -sw_error_t -hppe_eg_vlan_xlt_rule_skey_pcp_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - union eg_vlan_xlt_rule_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_eg_vlan_xlt_rule_get(dev_id, index, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.skey_pcp = value; - ret = hppe_eg_vlan_xlt_rule_set(dev_id, index, ®_val); - return ret; -} - -sw_error_t -hppe_eg_vlan_xlt_rule_ckey_pcp_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union eg_vlan_xlt_rule_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_eg_vlan_xlt_rule_get(dev_id, index, ®_val); - *value = reg_val.bf.ckey_pcp; - return ret; -} - -sw_error_t -hppe_eg_vlan_xlt_rule_ckey_pcp_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - union eg_vlan_xlt_rule_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_eg_vlan_xlt_rule_get(dev_id, index, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.ckey_pcp = value; - ret = hppe_eg_vlan_xlt_rule_set(dev_id, index, ®_val); - return ret; -} - -sw_error_t -hppe_eg_vlan_xlt_rule_vsi_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union eg_vlan_xlt_rule_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_eg_vlan_xlt_rule_get(dev_id, index, ®_val); - *value = reg_val.bf.vsi; - return ret; -} - -sw_error_t -hppe_eg_vlan_xlt_rule_vsi_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - union eg_vlan_xlt_rule_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_eg_vlan_xlt_rule_get(dev_id, index, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.vsi = value; - ret = hppe_eg_vlan_xlt_rule_set(dev_id, index, ®_val); - return ret; -} - -sw_error_t -hppe_eg_vlan_xlt_rule_ckey_vid_incl_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union eg_vlan_xlt_rule_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_eg_vlan_xlt_rule_get(dev_id, index, ®_val); - *value = reg_val.bf.ckey_vid_incl; - return ret; -} - -sw_error_t -hppe_eg_vlan_xlt_rule_ckey_vid_incl_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - union eg_vlan_xlt_rule_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_eg_vlan_xlt_rule_get(dev_id, index, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.ckey_vid_incl = value; - ret = hppe_eg_vlan_xlt_rule_set(dev_id, index, ®_val); - return ret; -} - -sw_error_t -hppe_eg_vlan_xlt_rule_ckey_dei_incl_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union eg_vlan_xlt_rule_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_eg_vlan_xlt_rule_get(dev_id, index, ®_val); - *value = reg_val.bf.ckey_dei_incl; - return ret; -} - -sw_error_t -hppe_eg_vlan_xlt_rule_ckey_dei_incl_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - union eg_vlan_xlt_rule_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_eg_vlan_xlt_rule_get(dev_id, index, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.ckey_dei_incl = value; - ret = hppe_eg_vlan_xlt_rule_set(dev_id, index, ®_val); - return ret; -} - -sw_error_t -hppe_eg_vlan_xlt_rule_vsi_incl_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union eg_vlan_xlt_rule_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_eg_vlan_xlt_rule_get(dev_id, index, ®_val); - *value = reg_val.bf.vsi_incl; - return ret; -} - -sw_error_t -hppe_eg_vlan_xlt_rule_vsi_incl_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - union eg_vlan_xlt_rule_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_eg_vlan_xlt_rule_get(dev_id, index, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.vsi_incl = value; - ret = hppe_eg_vlan_xlt_rule_set(dev_id, index, ®_val); - return ret; -} - -sw_error_t -hppe_eg_vlan_xlt_rule_port_bitmap_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union eg_vlan_xlt_rule_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_eg_vlan_xlt_rule_get(dev_id, index, ®_val); - *value = reg_val.bf.port_bitmap; - return ret; -} - -sw_error_t -hppe_eg_vlan_xlt_rule_port_bitmap_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - union eg_vlan_xlt_rule_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_eg_vlan_xlt_rule_get(dev_id, index, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.port_bitmap = value; - ret = hppe_eg_vlan_xlt_rule_set(dev_id, index, ®_val); - return ret; -} - -sw_error_t -hppe_eg_vlan_xlt_rule_skey_pcp_incl_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union eg_vlan_xlt_rule_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_eg_vlan_xlt_rule_get(dev_id, index, ®_val); - *value = reg_val.bf.skey_pcp_incl; - return ret; -} - -sw_error_t -hppe_eg_vlan_xlt_rule_skey_pcp_incl_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - union eg_vlan_xlt_rule_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_eg_vlan_xlt_rule_get(dev_id, index, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.skey_pcp_incl = value; - ret = hppe_eg_vlan_xlt_rule_set(dev_id, index, ®_val); - return ret; -} - -sw_error_t -hppe_eg_vlan_xlt_rule_ckey_fmt_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union eg_vlan_xlt_rule_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_eg_vlan_xlt_rule_get(dev_id, index, ®_val); - *value = reg_val.bf.ckey_fmt; - return ret; -} - -sw_error_t -hppe_eg_vlan_xlt_rule_ckey_fmt_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - union eg_vlan_xlt_rule_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_eg_vlan_xlt_rule_get(dev_id, index, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.ckey_fmt = value; - ret = hppe_eg_vlan_xlt_rule_set(dev_id, index, ®_val); - return ret; -} - -sw_error_t -hppe_eg_vlan_xlt_rule_skey_vid_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union eg_vlan_xlt_rule_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_eg_vlan_xlt_rule_get(dev_id, index, ®_val); - *value = reg_val.bf.skey_vid; - return ret; -} - -sw_error_t -hppe_eg_vlan_xlt_rule_skey_vid_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - union eg_vlan_xlt_rule_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_eg_vlan_xlt_rule_get(dev_id, index, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.skey_vid = value; - ret = hppe_eg_vlan_xlt_rule_set(dev_id, index, ®_val); - return ret; -} - -sw_error_t -hppe_eg_vlan_xlt_rule_skey_fmt_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union eg_vlan_xlt_rule_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_eg_vlan_xlt_rule_get(dev_id, index, ®_val); - *value = reg_val.bf.skey_fmt; - return ret; -} - -sw_error_t -hppe_eg_vlan_xlt_rule_skey_fmt_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - union eg_vlan_xlt_rule_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_eg_vlan_xlt_rule_get(dev_id, index, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.skey_fmt = value; - ret = hppe_eg_vlan_xlt_rule_set(dev_id, index, ®_val); - return ret; -} - -sw_error_t -hppe_eg_vlan_xlt_rule_ckey_pcp_incl_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union eg_vlan_xlt_rule_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_eg_vlan_xlt_rule_get(dev_id, index, ®_val); - *value = reg_val.bf.ckey_pcp_incl; - return ret; -} - -sw_error_t -hppe_eg_vlan_xlt_rule_ckey_pcp_incl_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - union eg_vlan_xlt_rule_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_eg_vlan_xlt_rule_get(dev_id, index, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.ckey_pcp_incl = value; - ret = hppe_eg_vlan_xlt_rule_set(dev_id, index, ®_val); - return ret; -} - -sw_error_t -hppe_eg_vlan_xlt_rule_skey_vid_incl_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union eg_vlan_xlt_rule_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_eg_vlan_xlt_rule_get(dev_id, index, ®_val); - *value = reg_val.bf.skey_vid_incl; - return ret; -} - -sw_error_t -hppe_eg_vlan_xlt_rule_skey_vid_incl_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - union eg_vlan_xlt_rule_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_eg_vlan_xlt_rule_get(dev_id, index, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.skey_vid_incl = value; - ret = hppe_eg_vlan_xlt_rule_set(dev_id, index, ®_val); - return ret; -} - -sw_error_t -hppe_eg_vlan_xlt_rule_skey_dei_incl_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union eg_vlan_xlt_rule_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_eg_vlan_xlt_rule_get(dev_id, index, ®_val); - *value = reg_val.bf.skey_dei_incl; - return ret; -} - -sw_error_t -hppe_eg_vlan_xlt_rule_skey_dei_incl_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - union eg_vlan_xlt_rule_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_eg_vlan_xlt_rule_get(dev_id, index, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.skey_dei_incl = value; - ret = hppe_eg_vlan_xlt_rule_set(dev_id, index, ®_val); - return ret; -} - -sw_error_t -hppe_eg_vlan_xlt_rule_vsi_valid_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union eg_vlan_xlt_rule_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_eg_vlan_xlt_rule_get(dev_id, index, ®_val); - *value = reg_val.bf.vsi_valid; - return ret; -} - -sw_error_t -hppe_eg_vlan_xlt_rule_vsi_valid_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - union eg_vlan_xlt_rule_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_eg_vlan_xlt_rule_get(dev_id, index, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.vsi_valid = value; - ret = hppe_eg_vlan_xlt_rule_set(dev_id, index, ®_val); - return ret; -} - -sw_error_t -hppe_eg_vsi_tag_tagged_mode_port_bitmap_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union eg_vsi_tag_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_eg_vsi_tag_get(dev_id, index, ®_val); - *value = reg_val.bf.tagged_mode_port_bitmap; - return ret; -} - -sw_error_t -hppe_eg_vsi_tag_tagged_mode_port_bitmap_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - union eg_vsi_tag_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_eg_vsi_tag_get(dev_id, index, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.tagged_mode_port_bitmap = value; - ret = hppe_eg_vsi_tag_set(dev_id, index, ®_val); - return ret; -} - -sw_error_t -hppe_port_eg_def_vid_port_def_svid_en_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union port_eg_def_vid_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_port_eg_def_vid_get(dev_id, index, ®_val); - *value = reg_val.bf.port_def_svid_en; - return ret; -} - -sw_error_t -hppe_port_eg_def_vid_port_def_svid_en_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - union port_eg_def_vid_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_port_eg_def_vid_get(dev_id, index, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.port_def_svid_en = value; - ret = hppe_port_eg_def_vid_set(dev_id, index, ®_val); - return ret; -} - -sw_error_t -hppe_port_eg_def_vid_port_def_svid_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union port_eg_def_vid_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_port_eg_def_vid_get(dev_id, index, ®_val); - *value = reg_val.bf.port_def_svid; - return ret; -} - -sw_error_t -hppe_port_eg_def_vid_port_def_svid_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - union port_eg_def_vid_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_port_eg_def_vid_get(dev_id, index, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.port_def_svid = value; - ret = hppe_port_eg_def_vid_set(dev_id, index, ®_val); - return ret; -} - -sw_error_t -hppe_port_eg_def_vid_port_def_cvid_en_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union port_eg_def_vid_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_port_eg_def_vid_get(dev_id, index, ®_val); - *value = reg_val.bf.port_def_cvid_en; - return ret; -} - -sw_error_t -hppe_port_eg_def_vid_port_def_cvid_en_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - union port_eg_def_vid_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_port_eg_def_vid_get(dev_id, index, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.port_def_cvid_en = value; - ret = hppe_port_eg_def_vid_set(dev_id, index, ®_val); - return ret; -} - -sw_error_t -hppe_port_eg_def_vid_port_def_cvid_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union port_eg_def_vid_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_port_eg_def_vid_get(dev_id, index, ®_val); - *value = reg_val.bf.port_def_cvid; - return ret; -} - -sw_error_t -hppe_port_eg_def_vid_port_def_cvid_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - union port_eg_def_vid_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_port_eg_def_vid_get(dev_id, index, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.port_def_cvid = value; - ret = hppe_port_eg_def_vid_set(dev_id, index, ®_val); - return ret; -} - -sw_error_t -hppe_port_eg_vlan_tx_counting_en_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union port_eg_vlan_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_port_eg_vlan_get(dev_id, index, ®_val); - *value = reg_val.bf.tx_counting_en; - return ret; -} - -sw_error_t -hppe_port_eg_vlan_tx_counting_en_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - union port_eg_vlan_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_port_eg_vlan_get(dev_id, index, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.tx_counting_en = value; - ret = hppe_port_eg_vlan_set(dev_id, index, ®_val); - return ret; -} - -sw_error_t -hppe_port_eg_vlan_port_eg_vlan_ctag_mode_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union port_eg_vlan_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_port_eg_vlan_get(dev_id, index, ®_val); - *value = reg_val.bf.port_eg_vlan_ctag_mode; - return ret; -} - -sw_error_t -hppe_port_eg_vlan_port_eg_vlan_ctag_mode_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - union port_eg_vlan_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_port_eg_vlan_get(dev_id, index, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.port_eg_vlan_ctag_mode = value; - ret = hppe_port_eg_vlan_set(dev_id, index, ®_val); - return ret; -} - -sw_error_t -hppe_port_eg_vlan_port_eg_pcp_prop_cmd_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union port_eg_vlan_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_port_eg_vlan_get(dev_id, index, ®_val); - *value = reg_val.bf.port_eg_pcp_prop_cmd; - return ret; -} - -sw_error_t -hppe_port_eg_vlan_port_eg_pcp_prop_cmd_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - union port_eg_vlan_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_port_eg_vlan_get(dev_id, index, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.port_eg_pcp_prop_cmd = value; - ret = hppe_port_eg_vlan_set(dev_id, index, ®_val); - return ret; -} - -sw_error_t -hppe_port_eg_vlan_vsi_tag_mode_en_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union port_eg_vlan_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_port_eg_vlan_get(dev_id, index, ®_val); - *value = reg_val.bf.vsi_tag_mode_en; - return ret; -} - -sw_error_t -hppe_port_eg_vlan_vsi_tag_mode_en_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - union port_eg_vlan_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_port_eg_vlan_get(dev_id, index, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.vsi_tag_mode_en = value; - ret = hppe_port_eg_vlan_set(dev_id, index, ®_val); - return ret; -} - -sw_error_t -hppe_port_eg_vlan_port_eg_vlan_stag_mode_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union port_eg_vlan_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_port_eg_vlan_get(dev_id, index, ®_val); - *value = reg_val.bf.port_eg_vlan_stag_mode; - return ret; -} - -sw_error_t -hppe_port_eg_vlan_port_eg_vlan_stag_mode_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - union port_eg_vlan_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_port_eg_vlan_get(dev_id, index, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.port_eg_vlan_stag_mode = value; - ret = hppe_port_eg_vlan_set(dev_id, index, ®_val); - return ret; -} - -sw_error_t -hppe_port_eg_vlan_port_eg_dei_prop_cmd_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union port_eg_vlan_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_port_eg_vlan_get(dev_id, index, ®_val); - *value = reg_val.bf.port_eg_dei_prop_cmd; - return ret; -} - -sw_error_t -hppe_port_eg_vlan_port_eg_dei_prop_cmd_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - union port_eg_vlan_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_port_eg_vlan_get(dev_id, index, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.port_eg_dei_prop_cmd = value; - ret = hppe_port_eg_vlan_set(dev_id, index, ®_val); - return ret; -} - -sw_error_t -hppe_port_eg_vlan_port_vlan_type_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union port_eg_vlan_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_port_eg_vlan_get(dev_id, index, ®_val); - *value = reg_val.bf.port_vlan_type; - return ret; -} - -sw_error_t -hppe_port_eg_vlan_port_vlan_type_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - union port_eg_vlan_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_port_eg_vlan_get(dev_id, index, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.port_vlan_type = value; - ret = hppe_port_eg_vlan_set(dev_id, index, ®_val); - return ret; -} - -sw_error_t -hppe_eg_vlan_tpid_ctpid_get( - a_uint32_t dev_id, - a_uint32_t *value) -{ - union eg_vlan_tpid_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_eg_vlan_tpid_get(dev_id, ®_val); - *value = reg_val.bf.ctpid; - return ret; -} - -sw_error_t -hppe_eg_vlan_tpid_ctpid_set( - a_uint32_t dev_id, - a_uint32_t value) -{ - union eg_vlan_tpid_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_eg_vlan_tpid_get(dev_id, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.ctpid = value; - ret = hppe_eg_vlan_tpid_set(dev_id, ®_val); - return ret; -} - -sw_error_t -hppe_eg_vlan_tpid_stpid_get( - a_uint32_t dev_id, - a_uint32_t *value) -{ - union eg_vlan_tpid_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_eg_vlan_tpid_get(dev_id, ®_val); - *value = reg_val.bf.stpid; - return ret; -} - -sw_error_t -hppe_eg_vlan_tpid_stpid_set( - a_uint32_t dev_id, - a_uint32_t value) -{ - union eg_vlan_tpid_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_eg_vlan_tpid_get(dev_id, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.stpid = value; - ret = hppe_eg_vlan_tpid_set(dev_id, ®_val); - return ret; -} - -sw_error_t -hppe_eg_bridge_config_bridge_type_get( - a_uint32_t dev_id, - a_uint32_t *value) -{ - union eg_bridge_config_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_eg_bridge_config_get(dev_id, ®_val); - *value = reg_val.bf.bridge_type; - return ret; -} - -sw_error_t -hppe_eg_bridge_config_bridge_type_set( - a_uint32_t dev_id, - a_uint32_t value) -{ - union eg_bridge_config_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_eg_bridge_config_get(dev_id, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.bridge_type = value; - ret = hppe_eg_bridge_config_set(dev_id, ®_val); - return ret; -} - -sw_error_t -hppe_eg_bridge_config_pkt_l2_edit_en_get( - a_uint32_t dev_id, - a_uint32_t *value) -{ - union eg_bridge_config_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_eg_bridge_config_get(dev_id, ®_val); - *value = reg_val.bf.pkt_l2_edit_en; - return ret; -} - -sw_error_t -hppe_eg_bridge_config_pkt_l2_edit_en_set( - a_uint32_t dev_id, - a_uint32_t value) -{ - union eg_bridge_config_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_eg_bridge_config_get(dev_id, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.pkt_l2_edit_en = value; - ret = hppe_eg_bridge_config_set(dev_id, ®_val); - return ret; -} - -sw_error_t -hppe_eg_bridge_config_queue_cnt_en_get( - a_uint32_t dev_id, - a_uint32_t *value) -{ - union eg_bridge_config_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_eg_bridge_config_get(dev_id, ®_val); - *value = reg_val.bf.queue_cnt_en; - return ret; -} - -sw_error_t -hppe_eg_bridge_config_queue_cnt_en_set( - a_uint32_t dev_id, - a_uint32_t value) -{ - union eg_bridge_config_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_eg_bridge_config_get(dev_id, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.queue_cnt_en = value; - ret = hppe_eg_bridge_config_set(dev_id, ®_val); - return ret; -} - -sw_error_t -hppe_eg_vlan_xlt_action_dei_swap_cmd_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union eg_vlan_xlt_action_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_eg_vlan_xlt_action_get(dev_id, index, ®_val); - *value = reg_val.bf.dei_swap_cmd; - return ret; -} - -sw_error_t -hppe_eg_vlan_xlt_action_dei_swap_cmd_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - union eg_vlan_xlt_action_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_eg_vlan_xlt_action_get(dev_id, index, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.dei_swap_cmd = value; - ret = hppe_eg_vlan_xlt_action_set(dev_id, index, ®_val); - return ret; -} - -sw_error_t -hppe_eg_vlan_xlt_action_xlt_cvid_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union eg_vlan_xlt_action_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_eg_vlan_xlt_action_get(dev_id, index, ®_val); - *value = reg_val.bf.xlt_cvid; - return ret; -} - -sw_error_t -hppe_eg_vlan_xlt_action_xlt_cvid_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - union eg_vlan_xlt_action_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_eg_vlan_xlt_action_get(dev_id, index, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.xlt_cvid = value; - ret = hppe_eg_vlan_xlt_action_set(dev_id, index, ®_val); - return ret; -} - -sw_error_t -hppe_eg_vlan_xlt_action_xlt_cpcp_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union eg_vlan_xlt_action_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_eg_vlan_xlt_action_get(dev_id, index, ®_val); - *value = reg_val.bf.xlt_cpcp; - return ret; -} - -sw_error_t -hppe_eg_vlan_xlt_action_xlt_cpcp_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - union eg_vlan_xlt_action_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_eg_vlan_xlt_action_get(dev_id, index, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.xlt_cpcp = value; - ret = hppe_eg_vlan_xlt_action_set(dev_id, index, ®_val); - return ret; -} - -sw_error_t -hppe_eg_vlan_xlt_action_xlt_spcp_cmd_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union eg_vlan_xlt_action_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_eg_vlan_xlt_action_get(dev_id, index, ®_val); - *value = reg_val.bf.xlt_spcp_cmd; - return ret; -} - -sw_error_t -hppe_eg_vlan_xlt_action_xlt_spcp_cmd_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - union eg_vlan_xlt_action_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_eg_vlan_xlt_action_get(dev_id, index, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.xlt_spcp_cmd = value; - ret = hppe_eg_vlan_xlt_action_set(dev_id, index, ®_val); - return ret; -} - -sw_error_t -hppe_eg_vlan_xlt_action_xlt_sdei_cmd_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union eg_vlan_xlt_action_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_eg_vlan_xlt_action_get(dev_id, index, ®_val); - *value = reg_val.bf.xlt_sdei_cmd; - return ret; -} - -sw_error_t -hppe_eg_vlan_xlt_action_xlt_sdei_cmd_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - union eg_vlan_xlt_action_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_eg_vlan_xlt_action_get(dev_id, index, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.xlt_sdei_cmd = value; - ret = hppe_eg_vlan_xlt_action_set(dev_id, index, ®_val); - return ret; -} - -sw_error_t -hppe_eg_vlan_xlt_action_xlt_cvid_cmd_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union eg_vlan_xlt_action_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_eg_vlan_xlt_action_get(dev_id, index, ®_val); - *value = reg_val.bf.xlt_cvid_cmd; - return ret; -} - -sw_error_t -hppe_eg_vlan_xlt_action_xlt_cvid_cmd_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - union eg_vlan_xlt_action_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_eg_vlan_xlt_action_get(dev_id, index, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.xlt_cvid_cmd = value; - ret = hppe_eg_vlan_xlt_action_set(dev_id, index, ®_val); - return ret; -} - -sw_error_t -hppe_eg_vlan_xlt_action_xlt_spcp_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union eg_vlan_xlt_action_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_eg_vlan_xlt_action_get(dev_id, index, ®_val); - *value = reg_val.bf.xlt_spcp_1 << 1 | \ - reg_val.bf.xlt_spcp_0; - return ret; -} - -sw_error_t -hppe_eg_vlan_xlt_action_xlt_spcp_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - union eg_vlan_xlt_action_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_eg_vlan_xlt_action_get(dev_id, index, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.xlt_spcp_1 = value >> 1; - reg_val.bf.xlt_spcp_0 = value & (((a_uint64_t)1<<1)-1); - ret = hppe_eg_vlan_xlt_action_set(dev_id, index, ®_val); - return ret; -} - -sw_error_t -hppe_eg_vlan_xlt_action_counter_id_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union eg_vlan_xlt_action_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_eg_vlan_xlt_action_get(dev_id, index, ®_val); - *value = reg_val.bf.counter_id; - return ret; -} - -sw_error_t -hppe_eg_vlan_xlt_action_counter_id_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - union eg_vlan_xlt_action_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_eg_vlan_xlt_action_get(dev_id, index, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.counter_id = value; - ret = hppe_eg_vlan_xlt_action_set(dev_id, index, ®_val); - return ret; -} - -sw_error_t -hppe_eg_vlan_xlt_action_vid_swap_cmd_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union eg_vlan_xlt_action_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_eg_vlan_xlt_action_get(dev_id, index, ®_val); - *value = reg_val.bf.vid_swap_cmd; - return ret; -} - -sw_error_t -hppe_eg_vlan_xlt_action_vid_swap_cmd_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - union eg_vlan_xlt_action_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_eg_vlan_xlt_action_get(dev_id, index, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.vid_swap_cmd = value; - ret = hppe_eg_vlan_xlt_action_set(dev_id, index, ®_val); - return ret; -} - -sw_error_t -hppe_eg_vlan_xlt_action_xlt_sdei_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union eg_vlan_xlt_action_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_eg_vlan_xlt_action_get(dev_id, index, ®_val); - *value = reg_val.bf.xlt_sdei; - return ret; -} - -sw_error_t -hppe_eg_vlan_xlt_action_xlt_sdei_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - union eg_vlan_xlt_action_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_eg_vlan_xlt_action_get(dev_id, index, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.xlt_sdei = value; - ret = hppe_eg_vlan_xlt_action_set(dev_id, index, ®_val); - return ret; -} - -sw_error_t -hppe_eg_vlan_xlt_action_counter_en_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union eg_vlan_xlt_action_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_eg_vlan_xlt_action_get(dev_id, index, ®_val); - *value = reg_val.bf.counter_en; - return ret; -} - -sw_error_t -hppe_eg_vlan_xlt_action_counter_en_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - union eg_vlan_xlt_action_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_eg_vlan_xlt_action_get(dev_id, index, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.counter_en = value; - ret = hppe_eg_vlan_xlt_action_set(dev_id, index, ®_val); - return ret; -} - -sw_error_t -hppe_eg_vlan_xlt_action_xlt_svid_cmd_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union eg_vlan_xlt_action_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_eg_vlan_xlt_action_get(dev_id, index, ®_val); - *value = reg_val.bf.xlt_svid_cmd; - return ret; -} - -sw_error_t -hppe_eg_vlan_xlt_action_xlt_svid_cmd_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - union eg_vlan_xlt_action_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_eg_vlan_xlt_action_get(dev_id, index, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.xlt_svid_cmd = value; - ret = hppe_eg_vlan_xlt_action_set(dev_id, index, ®_val); - return ret; -} - -sw_error_t -hppe_eg_vlan_xlt_action_xlt_svid_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union eg_vlan_xlt_action_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_eg_vlan_xlt_action_get(dev_id, index, ®_val); - *value = reg_val.bf.xlt_svid; - return ret; -} - -sw_error_t -hppe_eg_vlan_xlt_action_xlt_svid_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - union eg_vlan_xlt_action_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_eg_vlan_xlt_action_get(dev_id, index, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.xlt_svid = value; - ret = hppe_eg_vlan_xlt_action_set(dev_id, index, ®_val); - return ret; -} - -sw_error_t -hppe_eg_vlan_xlt_action_xlt_cpcp_cmd_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union eg_vlan_xlt_action_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_eg_vlan_xlt_action_get(dev_id, index, ®_val); - *value = reg_val.bf.xlt_cpcp_cmd; - return ret; -} - -sw_error_t -hppe_eg_vlan_xlt_action_xlt_cpcp_cmd_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - union eg_vlan_xlt_action_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_eg_vlan_xlt_action_get(dev_id, index, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.xlt_cpcp_cmd = value; - ret = hppe_eg_vlan_xlt_action_set(dev_id, index, ®_val); - return ret; -} - -sw_error_t -hppe_eg_vlan_xlt_action_xlt_cdei_cmd_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union eg_vlan_xlt_action_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_eg_vlan_xlt_action_get(dev_id, index, ®_val); - *value = reg_val.bf.xlt_cdei_cmd; - return ret; -} - -sw_error_t -hppe_eg_vlan_xlt_action_xlt_cdei_cmd_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - union eg_vlan_xlt_action_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_eg_vlan_xlt_action_get(dev_id, index, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.xlt_cdei_cmd = value; - ret = hppe_eg_vlan_xlt_action_set(dev_id, index, ®_val); - return ret; -} - -sw_error_t -hppe_eg_vlan_xlt_action_pcp_swap_cmd_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union eg_vlan_xlt_action_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_eg_vlan_xlt_action_get(dev_id, index, ®_val); - *value = reg_val.bf.pcp_swap_cmd; - return ret; -} - -sw_error_t -hppe_eg_vlan_xlt_action_pcp_swap_cmd_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - union eg_vlan_xlt_action_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_eg_vlan_xlt_action_get(dev_id, index, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.pcp_swap_cmd = value; - ret = hppe_eg_vlan_xlt_action_set(dev_id, index, ®_val); - return ret; -} - -sw_error_t -hppe_eg_vlan_xlt_action_xlt_cdei_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union eg_vlan_xlt_action_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_eg_vlan_xlt_action_get(dev_id, index, ®_val); - *value = reg_val.bf.xlt_cdei; - return ret; -} - -sw_error_t -hppe_eg_vlan_xlt_action_xlt_cdei_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - union eg_vlan_xlt_action_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_eg_vlan_xlt_action_get(dev_id, index, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.xlt_cdei = value; - ret = hppe_eg_vlan_xlt_action_set(dev_id, index, ®_val); - return ret; -} - -sw_error_t -hppe_vlan_dev_tx_counter_tbl_get( - a_uint32_t dev_id, - a_uint32_t index, - union vlan_dev_tx_counter_tbl_u *value) -{ - return hppe_reg_tbl_get( - dev_id, - NSS_PTX_CSR_BASE_ADDR + VLAN_DEV_TX_COUNTER_TBL_ADDRESS + \ - index * VLAN_DEV_TX_COUNTER_TBL_INC, - value->val, - 3); -} - -sw_error_t -hppe_vlan_dev_tx_counter_tbl_set( - a_uint32_t dev_id, - a_uint32_t index, - union vlan_dev_tx_counter_tbl_u *value) -{ - return hppe_reg_tbl_set( - dev_id, - NSS_PTX_CSR_BASE_ADDR + VLAN_DEV_TX_COUNTER_TBL_ADDRESS + \ - index * VLAN_DEV_TX_COUNTER_TBL_INC, - value->val, - 3); -} - -sw_error_t -hppe_vlan_dev_tx_counter_tbl_tx_byte_cnt_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint64_t *value) -{ - union vlan_dev_tx_counter_tbl_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_vlan_dev_tx_counter_tbl_get(dev_id, index, ®_val); - *value = (a_uint64_t)reg_val.bf.tx_byte_cnt_1 << 32 | \ - reg_val.bf.tx_byte_cnt_0; - return ret; -} - -sw_error_t -hppe_vlan_dev_tx_counter_tbl_tx_byte_cnt_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint64_t value) -{ - union vlan_dev_tx_counter_tbl_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_vlan_dev_tx_counter_tbl_get(dev_id, index, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.tx_byte_cnt_1 = value >> 32; - reg_val.bf.tx_byte_cnt_0 = value & (((a_uint64_t)1<<32)-1); - ret = hppe_vlan_dev_tx_counter_tbl_set(dev_id, index, ®_val); - return ret; -} - -sw_error_t -hppe_vlan_dev_tx_counter_tbl_tx_pkt_cnt_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union vlan_dev_tx_counter_tbl_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_vlan_dev_tx_counter_tbl_get(dev_id, index, ®_val); - *value = reg_val.bf.tx_pkt_cnt; - return ret; -} - -sw_error_t -hppe_vlan_dev_tx_counter_tbl_tx_pkt_cnt_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - union vlan_dev_tx_counter_tbl_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_vlan_dev_tx_counter_tbl_get(dev_id, index, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.tx_pkt_cnt = value; - ret = hppe_vlan_dev_tx_counter_tbl_set(dev_id, index, ®_val); - return ret; -} - diff --git a/feeds/ipq807x/qca-ssdk/src/src/hsl/hppe/hppe_pppoe.c b/feeds/ipq807x/qca-ssdk/src/src/hsl/hppe/hppe_pppoe.c deleted file mode 100755 index 481de4748..000000000 --- a/feeds/ipq807x/qca-ssdk/src/src/hsl/hppe/hppe_pppoe.c +++ /dev/null @@ -1,388 +0,0 @@ -/* - * Copyright (c) 2016-2017, The Linux Foundation. All rights reserved. - * Permission to use, copy, modify, and/or distribute this software for - * any purpose with or without fee is hereby granted, provided that the - * above copyright notice and this permission notice appear in all copies. - * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES - * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR - * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES - * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN - * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT - * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. - */ - - -/** - * @defgroup - * @{ - */ -#include "sw.h" -#include "hsl.h" -#include "hppe_reg_access.h" -#include "hppe_pppoe_reg.h" -#include "hppe_pppoe.h" - -sw_error_t -hppe_pppoe_session_get( - a_uint32_t dev_id, - a_uint32_t index, - union pppoe_session_u *value) -{ - if (index >= PPPOE_SESSION_MAX_ENTRY) - return SW_OUT_OF_RANGE; - return hppe_reg_get( - dev_id, - IPE_L3_BASE_ADDR + PPPOE_SESSION_ADDRESS + \ - index * PPPOE_SESSION_INC, - &value->val); -} - -sw_error_t -hppe_pppoe_session_set( - a_uint32_t dev_id, - a_uint32_t index, - union pppoe_session_u *value) -{ - return hppe_reg_set( - dev_id, - IPE_L3_BASE_ADDR + PPPOE_SESSION_ADDRESS + \ - index * PPPOE_SESSION_INC, - value->val); -} - -sw_error_t -hppe_pppoe_session_ext_get( - a_uint32_t dev_id, - a_uint32_t index, - union pppoe_session_ext_u *value) -{ - if (index >= PPPOE_SESSION_EXT_MAX_ENTRY) - return SW_OUT_OF_RANGE; - return hppe_reg_get( - dev_id, - IPE_L3_BASE_ADDR + PPPOE_SESSION_EXT_ADDRESS + \ - index * PPPOE_SESSION_EXT_INC, - &value->val); -} - -sw_error_t -hppe_pppoe_session_ext_set( - a_uint32_t dev_id, - a_uint32_t index, - union pppoe_session_ext_u *value) -{ - return hppe_reg_set( - dev_id, - IPE_L3_BASE_ADDR + PPPOE_SESSION_EXT_ADDRESS + \ - index * PPPOE_SESSION_EXT_INC, - value->val); -} - -sw_error_t -hppe_pppoe_session_ext1_get( - a_uint32_t dev_id, - a_uint32_t index, - union pppoe_session_ext1_u *value) -{ - if (index >= PPPOE_SESSION_EXT1_MAX_ENTRY) - return SW_OUT_OF_RANGE; - return hppe_reg_get( - dev_id, - IPE_L3_BASE_ADDR + PPPOE_SESSION_EXT1_ADDRESS + \ - index * PPPOE_SESSION_EXT1_INC, - &value->val); -} - -sw_error_t -hppe_pppoe_session_ext1_set( - a_uint32_t dev_id, - a_uint32_t index, - union pppoe_session_ext1_u *value) -{ - return hppe_reg_set( - dev_id, - IPE_L3_BASE_ADDR + PPPOE_SESSION_EXT1_ADDRESS + \ - index * PPPOE_SESSION_EXT1_INC, - value->val); -} - -sw_error_t -hppe_pppoe_session_session_id_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union pppoe_session_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_pppoe_session_get(dev_id, index, ®_val); - *value = reg_val.bf.session_id; - return ret; -} - -sw_error_t -hppe_pppoe_session_session_id_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - union pppoe_session_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_pppoe_session_get(dev_id, index, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.session_id = value; - ret = hppe_pppoe_session_set(dev_id, index, ®_val); - return ret; -} - -sw_error_t -hppe_pppoe_session_l3_if_index_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union pppoe_session_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_pppoe_session_get(dev_id, index, ®_val); - *value = reg_val.bf.l3_if_index; - return ret; -} - -sw_error_t -hppe_pppoe_session_l3_if_index_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - union pppoe_session_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_pppoe_session_get(dev_id, index, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.l3_if_index = value; - ret = hppe_pppoe_session_set(dev_id, index, ®_val); - return ret; -} - -sw_error_t -hppe_pppoe_session_port_bitmap_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union pppoe_session_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_pppoe_session_get(dev_id, index, ®_val); - *value = reg_val.bf.port_bitmap; - return ret; -} - -sw_error_t -hppe_pppoe_session_port_bitmap_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - union pppoe_session_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_pppoe_session_get(dev_id, index, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.port_bitmap = value; - ret = hppe_pppoe_session_set(dev_id, index, ®_val); - return ret; -} - -sw_error_t -hppe_pppoe_session_ext_uc_valid_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union pppoe_session_ext_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_pppoe_session_ext_get(dev_id, index, ®_val); - *value = reg_val.bf.uc_valid; - return ret; -} - -sw_error_t -hppe_pppoe_session_ext_uc_valid_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - union pppoe_session_ext_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_pppoe_session_ext_get(dev_id, index, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.uc_valid = value; - ret = hppe_pppoe_session_ext_set(dev_id, index, ®_val); - return ret; -} - -sw_error_t -hppe_pppoe_session_ext_mc_valid_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union pppoe_session_ext_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_pppoe_session_ext_get(dev_id, index, ®_val); - *value = reg_val.bf.mc_valid; - return ret; -} - -sw_error_t -hppe_pppoe_session_ext_mc_valid_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - union pppoe_session_ext_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_pppoe_session_ext_get(dev_id, index, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.mc_valid = value; - ret = hppe_pppoe_session_ext_set(dev_id, index, ®_val); - return ret; -} - -sw_error_t -hppe_pppoe_session_ext_smac_valid_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union pppoe_session_ext_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_pppoe_session_ext_get(dev_id, index, ®_val); - *value = reg_val.bf.smac_valid; - return ret; -} - -sw_error_t -hppe_pppoe_session_ext_smac_valid_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - union pppoe_session_ext_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_pppoe_session_ext_get(dev_id, index, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.smac_valid = value; - ret = hppe_pppoe_session_ext_set(dev_id, index, ®_val); - return ret; -} - -sw_error_t -hppe_pppoe_session_ext_l3_if_valid_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union pppoe_session_ext_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_pppoe_session_ext_get(dev_id, index, ®_val); - *value = reg_val.bf.l3_if_valid; - return ret; -} - -sw_error_t -hppe_pppoe_session_ext_l3_if_valid_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - union pppoe_session_ext_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_pppoe_session_ext_get(dev_id, index, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.l3_if_valid = value; - ret = hppe_pppoe_session_ext_set(dev_id, index, ®_val); - return ret; -} - -sw_error_t -hppe_pppoe_session_ext_smac_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union pppoe_session_ext_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_pppoe_session_ext_get(dev_id, index, ®_val); - *value = reg_val.bf.smac; - return ret; -} - -sw_error_t -hppe_pppoe_session_ext_smac_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - union pppoe_session_ext_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_pppoe_session_ext_get(dev_id, index, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.smac = value; - ret = hppe_pppoe_session_ext_set(dev_id, index, ®_val); - return ret; -} - -sw_error_t -hppe_pppoe_session_ext1_smac_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union pppoe_session_ext1_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_pppoe_session_ext1_get(dev_id, index, ®_val); - *value = reg_val.bf.smac; - return ret; -} - -sw_error_t -hppe_pppoe_session_ext1_smac_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - union pppoe_session_ext1_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_pppoe_session_ext1_get(dev_id, index, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.smac = value; - ret = hppe_pppoe_session_ext1_set(dev_id, index, ®_val); - return ret; -} - diff --git a/feeds/ipq807x/qca-ssdk/src/src/hsl/hppe/hppe_qm.c b/feeds/ipq807x/qca-ssdk/src/src/hsl/hppe/hppe_qm.c deleted file mode 100755 index 16e3cebdc..000000000 --- a/feeds/ipq807x/qca-ssdk/src/src/hsl/hppe/hppe_qm.c +++ /dev/null @@ -1,9622 +0,0 @@ -/* - * Copyright (c) 2016-2017, The Linux Foundation. All rights reserved. - * Permission to use, copy, modify, and/or distribute this software for - * any purpose with or without fee is hereby granted, provided that the - * above copyright notice and this permission notice appear in all copies. - * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES - * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR - * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES - * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN - * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT - * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. - */ - - -/** - * @defgroup - * @{ - */ -#include "sw.h" -#include "hsl.h" -#include "hppe_reg_access.h" -#include "hppe_qm_reg.h" -#include "hppe_qm.h" - -sw_error_t -hppe_queue_tx_counter_tbl_get( - a_uint32_t dev_id, - a_uint32_t index, - union queue_tx_counter_tbl_u *value) -{ - return hppe_reg_tbl_get( - dev_id, - NSS_PTX_CSR_BASE_ADDR + QUEUE_TX_COUNTER_TBL_ADDRESS + \ - index * QUEUE_TX_COUNTER_TBL_INC, - value->val, - 3); -} - -sw_error_t -hppe_queue_tx_counter_tbl_set( - a_uint32_t dev_id, - a_uint32_t index, - union queue_tx_counter_tbl_u *value) -{ - return hppe_reg_tbl_set( - dev_id, - NSS_PTX_CSR_BASE_ADDR + QUEUE_TX_COUNTER_TBL_ADDRESS + \ - index * QUEUE_TX_COUNTER_TBL_INC, - value->val, - 3); -} - -sw_error_t -hppe_flush_cfg_get( - a_uint32_t dev_id, - union flush_cfg_u *value) -{ - return hppe_reg_get( - dev_id, - QUEUE_MANAGER_BASE_ADDR + FLUSH_CFG_ADDRESS, - &value->val); -} - -sw_error_t -hppe_flush_cfg_set( - a_uint32_t dev_id, - union flush_cfg_u *value) -{ - return hppe_reg_set( - dev_id, - QUEUE_MANAGER_BASE_ADDR + FLUSH_CFG_ADDRESS, - value->val); -} - -sw_error_t -hppe_in_mirror_priority_ctrl_get( - a_uint32_t dev_id, - union in_mirror_priority_ctrl_u *value) -{ - return hppe_reg_get( - dev_id, - QUEUE_MANAGER_BASE_ADDR + IN_MIRROR_PRIORITY_CTRL_ADDRESS, - &value->val); -} - -sw_error_t -hppe_in_mirror_priority_ctrl_set( - a_uint32_t dev_id, - union in_mirror_priority_ctrl_u *value) -{ - return hppe_reg_set( - dev_id, - QUEUE_MANAGER_BASE_ADDR + IN_MIRROR_PRIORITY_CTRL_ADDRESS, - value->val); -} - -sw_error_t -hppe_eg_mirror_priority_ctrl_get( - a_uint32_t dev_id, - union eg_mirror_priority_ctrl_u *value) -{ - return hppe_reg_get( - dev_id, - QUEUE_MANAGER_BASE_ADDR + EG_MIRROR_PRIORITY_CTRL_ADDRESS, - &value->val); -} - -sw_error_t -hppe_eg_mirror_priority_ctrl_set( - a_uint32_t dev_id, - union eg_mirror_priority_ctrl_u *value) -{ - return hppe_reg_set( - dev_id, - QUEUE_MANAGER_BASE_ADDR + EG_MIRROR_PRIORITY_CTRL_ADDRESS, - value->val); -} - -#ifndef IN_QM_MINI -sw_error_t -hppe_ucast_default_hash_get( - a_uint32_t dev_id, - union ucast_default_hash_u *value) -{ - return hppe_reg_get( - dev_id, - QUEUE_MANAGER_BASE_ADDR + UCAST_DEFAULT_HASH_ADDRESS, - &value->val); -} - -sw_error_t -hppe_ucast_default_hash_set( - a_uint32_t dev_id, - union ucast_default_hash_u *value) -{ - return hppe_reg_set( - dev_id, - QUEUE_MANAGER_BASE_ADDR + UCAST_DEFAULT_HASH_ADDRESS, - value->val); -} - -sw_error_t -hppe_spare_reg0_get( - a_uint32_t dev_id, - union spare_reg0_u *value) -{ - return hppe_reg_get( - dev_id, - QUEUE_MANAGER_BASE_ADDR + SPARE_REG0_ADDRESS, - &value->val); -} - -sw_error_t -hppe_spare_reg0_set( - a_uint32_t dev_id, - union spare_reg0_u *value) -{ - return hppe_reg_set( - dev_id, - QUEUE_MANAGER_BASE_ADDR + SPARE_REG0_ADDRESS, - value->val); -} - -sw_error_t -hppe_spare_reg1_get( - a_uint32_t dev_id, - union spare_reg1_u *value) -{ - return hppe_reg_get( - dev_id, - QUEUE_MANAGER_BASE_ADDR + SPARE_REG1_ADDRESS, - &value->val); -} - -sw_error_t -hppe_spare_reg1_set( - a_uint32_t dev_id, - union spare_reg1_u *value) -{ - return hppe_reg_set( - dev_id, - QUEUE_MANAGER_BASE_ADDR + SPARE_REG1_ADDRESS, - value->val); -} - -sw_error_t -hppe_qm_dbg_addr_get( - a_uint32_t dev_id, - union qm_dbg_addr_u *value) -{ - return hppe_reg_get( - dev_id, - QUEUE_MANAGER_BASE_ADDR + QM_DBG_ADDR_ADDRESS, - &value->val); -} - -sw_error_t -hppe_qm_dbg_addr_set( - a_uint32_t dev_id, - union qm_dbg_addr_u *value) -{ - return hppe_reg_set( - dev_id, - QUEUE_MANAGER_BASE_ADDR + QM_DBG_ADDR_ADDRESS, - value->val); -} - -sw_error_t -hppe_qm_dbg_data_get( - a_uint32_t dev_id, - union qm_dbg_data_u *value) -{ - return hppe_reg_get( - dev_id, - QUEUE_MANAGER_BASE_ADDR + QM_DBG_DATA_ADDRESS, - &value->val); -} - -sw_error_t -hppe_qm_dbg_data_set( - a_uint32_t dev_id, - union qm_dbg_data_u *value) -{ - return SW_NOT_SUPPORTED; -} - -sw_error_t -hppe_mcast_priority_map0_get( - a_uint32_t dev_id, - a_uint32_t index, - union mcast_priority_map0_u *value) -{ - if (index >= MCAST_PRIORITY_MAP0_MAX_ENTRY) - return SW_OUT_OF_RANGE; - return hppe_reg_get( - dev_id, - QUEUE_MANAGER_BASE_ADDR + MCAST_PRIORITY_MAP0_ADDRESS + \ - index * MCAST_PRIORITY_MAP0_INC, - &value->val); -} - -sw_error_t -hppe_mcast_priority_map0_set( - a_uint32_t dev_id, - a_uint32_t index, - union mcast_priority_map0_u *value) -{ - return hppe_reg_set( - dev_id, - QUEUE_MANAGER_BASE_ADDR + MCAST_PRIORITY_MAP0_ADDRESS + \ - index * MCAST_PRIORITY_MAP0_INC, - value->val); -} - -sw_error_t -hppe_mcast_priority_map1_get( - a_uint32_t dev_id, - a_uint32_t index, - union mcast_priority_map1_u *value) -{ - if (index >= MCAST_PRIORITY_MAP1_MAX_ENTRY) - return SW_OUT_OF_RANGE; - return hppe_reg_get( - dev_id, - QUEUE_MANAGER_BASE_ADDR + MCAST_PRIORITY_MAP1_ADDRESS + \ - index * MCAST_PRIORITY_MAP1_INC, - &value->val); -} - -sw_error_t -hppe_mcast_priority_map1_set( - a_uint32_t dev_id, - a_uint32_t index, - union mcast_priority_map1_u *value) -{ - return hppe_reg_set( - dev_id, - QUEUE_MANAGER_BASE_ADDR + MCAST_PRIORITY_MAP1_ADDRESS + \ - index * MCAST_PRIORITY_MAP1_INC, - value->val); -} - -sw_error_t -hppe_mcast_priority_map2_get( - a_uint32_t dev_id, - a_uint32_t index, - union mcast_priority_map2_u *value) -{ - if (index >= MCAST_PRIORITY_MAP2_MAX_ENTRY) - return SW_OUT_OF_RANGE; - return hppe_reg_get( - dev_id, - QUEUE_MANAGER_BASE_ADDR + MCAST_PRIORITY_MAP2_ADDRESS + \ - index * MCAST_PRIORITY_MAP2_INC, - &value->val); -} - -sw_error_t -hppe_mcast_priority_map2_set( - a_uint32_t dev_id, - a_uint32_t index, - union mcast_priority_map2_u *value) -{ - return hppe_reg_set( - dev_id, - QUEUE_MANAGER_BASE_ADDR + MCAST_PRIORITY_MAP2_ADDRESS + \ - index * MCAST_PRIORITY_MAP2_INC, - value->val); -} - -sw_error_t -hppe_mcast_priority_map3_get( - a_uint32_t dev_id, - a_uint32_t index, - union mcast_priority_map3_u *value) -{ - if (index >= MCAST_PRIORITY_MAP3_MAX_ENTRY) - return SW_OUT_OF_RANGE; - return hppe_reg_get( - dev_id, - QUEUE_MANAGER_BASE_ADDR + MCAST_PRIORITY_MAP3_ADDRESS + \ - index * MCAST_PRIORITY_MAP3_INC, - &value->val); -} - -sw_error_t -hppe_mcast_priority_map3_set( - a_uint32_t dev_id, - a_uint32_t index, - union mcast_priority_map3_u *value) -{ - return hppe_reg_set( - dev_id, - QUEUE_MANAGER_BASE_ADDR + MCAST_PRIORITY_MAP3_ADDRESS + \ - index * MCAST_PRIORITY_MAP3_INC, - value->val); -} - -sw_error_t -hppe_mcast_priority_map4_get( - a_uint32_t dev_id, - a_uint32_t index, - union mcast_priority_map4_u *value) -{ - if (index >= MCAST_PRIORITY_MAP4_MAX_ENTRY) - return SW_OUT_OF_RANGE; - return hppe_reg_get( - dev_id, - QUEUE_MANAGER_BASE_ADDR + MCAST_PRIORITY_MAP4_ADDRESS + \ - index * MCAST_PRIORITY_MAP4_INC, - &value->val); -} - -sw_error_t -hppe_mcast_priority_map4_set( - a_uint32_t dev_id, - a_uint32_t index, - union mcast_priority_map4_u *value) -{ - return hppe_reg_set( - dev_id, - QUEUE_MANAGER_BASE_ADDR + MCAST_PRIORITY_MAP4_ADDRESS + \ - index * MCAST_PRIORITY_MAP4_INC, - value->val); -} - -sw_error_t -hppe_mcast_priority_map5_get( - a_uint32_t dev_id, - a_uint32_t index, - union mcast_priority_map5_u *value) -{ - if (index >= MCAST_PRIORITY_MAP5_MAX_ENTRY) - return SW_OUT_OF_RANGE; - return hppe_reg_get( - dev_id, - QUEUE_MANAGER_BASE_ADDR + MCAST_PRIORITY_MAP5_ADDRESS + \ - index * MCAST_PRIORITY_MAP5_INC, - &value->val); -} - -sw_error_t -hppe_mcast_priority_map5_set( - a_uint32_t dev_id, - a_uint32_t index, - union mcast_priority_map5_u *value) -{ - return hppe_reg_set( - dev_id, - QUEUE_MANAGER_BASE_ADDR + MCAST_PRIORITY_MAP5_ADDRESS + \ - index * MCAST_PRIORITY_MAP5_INC, - value->val); -} - -sw_error_t -hppe_mcast_priority_map6_get( - a_uint32_t dev_id, - a_uint32_t index, - union mcast_priority_map6_u *value) -{ - if (index >= MCAST_PRIORITY_MAP6_MAX_ENTRY) - return SW_OUT_OF_RANGE; - return hppe_reg_get( - dev_id, - QUEUE_MANAGER_BASE_ADDR + MCAST_PRIORITY_MAP6_ADDRESS + \ - index * MCAST_PRIORITY_MAP6_INC, - &value->val); -} - -sw_error_t -hppe_mcast_priority_map6_set( - a_uint32_t dev_id, - a_uint32_t index, - union mcast_priority_map6_u *value) -{ - return hppe_reg_set( - dev_id, - QUEUE_MANAGER_BASE_ADDR + MCAST_PRIORITY_MAP6_ADDRESS + \ - index * MCAST_PRIORITY_MAP6_INC, - value->val); -} - -sw_error_t -hppe_mcast_priority_map7_get( - a_uint32_t dev_id, - a_uint32_t index, - union mcast_priority_map7_u *value) -{ - if (index >= MCAST_PRIORITY_MAP7_MAX_ENTRY) - return SW_OUT_OF_RANGE; - return hppe_reg_get( - dev_id, - QUEUE_MANAGER_BASE_ADDR + MCAST_PRIORITY_MAP7_ADDRESS + \ - index * MCAST_PRIORITY_MAP7_INC, - &value->val); -} - -sw_error_t -hppe_mcast_priority_map7_set( - a_uint32_t dev_id, - a_uint32_t index, - union mcast_priority_map7_u *value) -{ - return hppe_reg_set( - dev_id, - QUEUE_MANAGER_BASE_ADDR + MCAST_PRIORITY_MAP7_ADDRESS + \ - index * MCAST_PRIORITY_MAP7_INC, - value->val); -} - -sw_error_t -hppe_agg_profile_cnt_en_get( - a_uint32_t dev_id, - union agg_profile_cnt_en_u *value) -{ - return hppe_reg_get( - dev_id, - QUEUE_MANAGER_BASE_ADDR + AGG_PROFILE_CNT_EN_ADDRESS, - &value->val); -} - -sw_error_t -hppe_agg_profile_cnt_en_set( - a_uint32_t dev_id, - union agg_profile_cnt_en_u *value) -{ - return hppe_reg_set( - dev_id, - QUEUE_MANAGER_BASE_ADDR + AGG_PROFILE_CNT_EN_ADDRESS, - value->val); -} - -sw_error_t -hppe_uq_agg_profile_cfg_get( - a_uint32_t dev_id, - a_uint32_t index, - union uq_agg_profile_cfg_u *value) -{ - if (index >= UQ_AGG_PROFILE_CFG_MAX_ENTRY) - return SW_OUT_OF_RANGE; - return hppe_reg_get( - dev_id, - QUEUE_MANAGER_BASE_ADDR + UQ_AGG_PROFILE_CFG_ADDRESS + \ - index * UQ_AGG_PROFILE_CFG_INC, - &value->val); -} - -sw_error_t -hppe_uq_agg_profile_cfg_set( - a_uint32_t dev_id, - a_uint32_t index, - union uq_agg_profile_cfg_u *value) -{ - return hppe_reg_set( - dev_id, - QUEUE_MANAGER_BASE_ADDR + UQ_AGG_PROFILE_CFG_ADDRESS + \ - index * UQ_AGG_PROFILE_CFG_INC, - value->val); -} - -sw_error_t -hppe_mq_agg_profile_cfg_get( - a_uint32_t dev_id, - a_uint32_t index, - union mq_agg_profile_cfg_u *value) -{ - if (index >= MQ_AGG_PROFILE_CFG_MAX_ENTRY) - return SW_OUT_OF_RANGE; - return hppe_reg_get( - dev_id, - QUEUE_MANAGER_BASE_ADDR + MQ_AGG_PROFILE_CFG_ADDRESS + \ - index * MQ_AGG_PROFILE_CFG_INC, - &value->val); -} - -sw_error_t -hppe_mq_agg_profile_cfg_set( - a_uint32_t dev_id, - a_uint32_t index, - union mq_agg_profile_cfg_u *value) -{ - return hppe_reg_set( - dev_id, - QUEUE_MANAGER_BASE_ADDR + MQ_AGG_PROFILE_CFG_ADDRESS + \ - index * MQ_AGG_PROFILE_CFG_INC, - value->val); -} - -sw_error_t -hppe_grp_agg_profile_cfg_get( - a_uint32_t dev_id, - a_uint32_t index, - union grp_agg_profile_cfg_u *value) -{ - if (index >= GRP_AGG_PROFILE_CFG_MAX_ENTRY) - return SW_OUT_OF_RANGE; - return hppe_reg_get( - dev_id, - QUEUE_MANAGER_BASE_ADDR + GRP_AGG_PROFILE_CFG_ADDRESS + \ - index * GRP_AGG_PROFILE_CFG_INC, - &value->val); -} - -sw_error_t -hppe_grp_agg_profile_cfg_set( - a_uint32_t dev_id, - a_uint32_t index, - union grp_agg_profile_cfg_u *value) -{ - return hppe_reg_set( - dev_id, - QUEUE_MANAGER_BASE_ADDR + GRP_AGG_PROFILE_CFG_ADDRESS + \ - index * GRP_AGG_PROFILE_CFG_INC, - value->val); -} - -sw_error_t -hppe_uq_agg_in_profile_cnt_get( - a_uint32_t dev_id, - a_uint32_t index, - union uq_agg_in_profile_cnt_u *value) -{ - if (index >= UQ_AGG_IN_PROFILE_CNT_MAX_ENTRY) - return SW_OUT_OF_RANGE; - return hppe_reg_get( - dev_id, - QUEUE_MANAGER_BASE_ADDR + UQ_AGG_IN_PROFILE_CNT_ADDRESS + \ - index * UQ_AGG_IN_PROFILE_CNT_INC, - &value->val); -} - -sw_error_t -hppe_uq_agg_in_profile_cnt_set( - a_uint32_t dev_id, - a_uint32_t index, - union uq_agg_in_profile_cnt_u *value) -{ - return hppe_reg_set( - dev_id, - QUEUE_MANAGER_BASE_ADDR + UQ_AGG_IN_PROFILE_CNT_ADDRESS + \ - index * UQ_AGG_IN_PROFILE_CNT_INC, - value->val); -} - -sw_error_t -hppe_uq_agg_out_profile_cnt_get( - a_uint32_t dev_id, - a_uint32_t index, - union uq_agg_out_profile_cnt_u *value) -{ - if (index >= UQ_AGG_OUT_PROFILE_CNT_MAX_ENTRY) - return SW_OUT_OF_RANGE; - return hppe_reg_get( - dev_id, - QUEUE_MANAGER_BASE_ADDR + UQ_AGG_OUT_PROFILE_CNT_ADDRESS + \ - index * UQ_AGG_OUT_PROFILE_CNT_INC, - &value->val); -} - -sw_error_t -hppe_uq_agg_out_profile_cnt_set( - a_uint32_t dev_id, - a_uint32_t index, - union uq_agg_out_profile_cnt_u *value) -{ - return hppe_reg_set( - dev_id, - QUEUE_MANAGER_BASE_ADDR + UQ_AGG_OUT_PROFILE_CNT_ADDRESS + \ - index * UQ_AGG_OUT_PROFILE_CNT_INC, - value->val); -} - -sw_error_t -hppe_mq_agg_in_profile_cnt_get( - a_uint32_t dev_id, - a_uint32_t index, - union mq_agg_in_profile_cnt_u *value) -{ - if (index >= MQ_AGG_IN_PROFILE_CNT_MAX_ENTRY) - return SW_OUT_OF_RANGE; - return hppe_reg_get( - dev_id, - QUEUE_MANAGER_BASE_ADDR + MQ_AGG_IN_PROFILE_CNT_ADDRESS + \ - index * MQ_AGG_IN_PROFILE_CNT_INC, - &value->val); -} - -sw_error_t -hppe_mq_agg_in_profile_cnt_set( - a_uint32_t dev_id, - a_uint32_t index, - union mq_agg_in_profile_cnt_u *value) -{ - return hppe_reg_set( - dev_id, - QUEUE_MANAGER_BASE_ADDR + MQ_AGG_IN_PROFILE_CNT_ADDRESS + \ - index * MQ_AGG_IN_PROFILE_CNT_INC, - value->val); -} - -sw_error_t -hppe_mq_agg_out_profile_cnt_get( - a_uint32_t dev_id, - a_uint32_t index, - union mq_agg_out_profile_cnt_u *value) -{ - if (index >= MQ_AGG_OUT_PROFILE_CNT_MAX_ENTRY) - return SW_OUT_OF_RANGE; - return hppe_reg_get( - dev_id, - QUEUE_MANAGER_BASE_ADDR + MQ_AGG_OUT_PROFILE_CNT_ADDRESS + \ - index * MQ_AGG_OUT_PROFILE_CNT_INC, - &value->val); -} - -sw_error_t -hppe_mq_agg_out_profile_cnt_set( - a_uint32_t dev_id, - a_uint32_t index, - union mq_agg_out_profile_cnt_u *value) -{ - return hppe_reg_set( - dev_id, - QUEUE_MANAGER_BASE_ADDR + MQ_AGG_OUT_PROFILE_CNT_ADDRESS + \ - index * MQ_AGG_OUT_PROFILE_CNT_INC, - value->val); -} - -sw_error_t -hppe_grp_agg_in_profile_cnt_get( - a_uint32_t dev_id, - a_uint32_t index, - union grp_agg_in_profile_cnt_u *value) -{ - if (index >= GRP_AGG_IN_PROFILE_CNT_MAX_ENTRY) - return SW_OUT_OF_RANGE; - return hppe_reg_get( - dev_id, - QUEUE_MANAGER_BASE_ADDR + GRP_AGG_IN_PROFILE_CNT_ADDRESS + \ - index * GRP_AGG_IN_PROFILE_CNT_INC, - &value->val); -} - -sw_error_t -hppe_grp_agg_in_profile_cnt_set( - a_uint32_t dev_id, - a_uint32_t index, - union grp_agg_in_profile_cnt_u *value) -{ - return hppe_reg_set( - dev_id, - QUEUE_MANAGER_BASE_ADDR + GRP_AGG_IN_PROFILE_CNT_ADDRESS + \ - index * GRP_AGG_IN_PROFILE_CNT_INC, - value->val); -} - -sw_error_t -hppe_grp_agg_out_profile_cnt_get( - a_uint32_t dev_id, - a_uint32_t index, - union grp_agg_out_profile_cnt_u *value) -{ - if (index >= GRP_AGG_OUT_PROFILE_CNT_MAX_ENTRY) - return SW_OUT_OF_RANGE; - return hppe_reg_get( - dev_id, - QUEUE_MANAGER_BASE_ADDR + GRP_AGG_OUT_PROFILE_CNT_ADDRESS + \ - index * GRP_AGG_OUT_PROFILE_CNT_INC, - &value->val); -} - -sw_error_t -hppe_grp_agg_out_profile_cnt_set( - a_uint32_t dev_id, - a_uint32_t index, - union grp_agg_out_profile_cnt_u *value) -{ - return hppe_reg_set( - dev_id, - QUEUE_MANAGER_BASE_ADDR + GRP_AGG_OUT_PROFILE_CNT_ADDRESS + \ - index * GRP_AGG_OUT_PROFILE_CNT_INC, - value->val); -} - -sw_error_t -hppe_ucast_queue_map_tbl_get( - a_uint32_t dev_id, - a_uint32_t index, - union ucast_queue_map_tbl_u *value) -{ - if (index >= UCAST_QUEUE_MAP_TBL_MAX_ENTRY) - return SW_OUT_OF_RANGE; - return hppe_reg_get( - dev_id, - QUEUE_MANAGER_BASE_ADDR + UCAST_QUEUE_MAP_TBL_ADDRESS + \ - index * UCAST_QUEUE_MAP_TBL_INC, - &value->val); -} -#endif - -sw_error_t -hppe_ucast_queue_map_tbl_set( - a_uint32_t dev_id, - a_uint32_t index, - union ucast_queue_map_tbl_u *value) -{ - return hppe_reg_set( - dev_id, - QUEUE_MANAGER_BASE_ADDR + UCAST_QUEUE_MAP_TBL_ADDRESS + \ - index * UCAST_QUEUE_MAP_TBL_INC, - value->val); -} - -#ifndef IN_QM_MINI -sw_error_t -hppe_ucast_hash_map_tbl_get( - a_uint32_t dev_id, - a_uint32_t index, - union ucast_hash_map_tbl_u *value) -{ - if (index >= UCAST_HASH_MAP_TBL_MAX_ENTRY) - return SW_OUT_OF_RANGE; - return hppe_reg_get( - dev_id, - QUEUE_MANAGER_BASE_ADDR + UCAST_HASH_MAP_TBL_ADDRESS + \ - index * UCAST_HASH_MAP_TBL_INC, - &value->val); -} - -sw_error_t -hppe_ucast_hash_map_tbl_set( - a_uint32_t dev_id, - a_uint32_t index, - union ucast_hash_map_tbl_u *value) -{ - return hppe_reg_set( - dev_id, - QUEUE_MANAGER_BASE_ADDR + UCAST_HASH_MAP_TBL_ADDRESS + \ - index * UCAST_HASH_MAP_TBL_INC, - value->val); -} - -sw_error_t -hppe_ucast_priority_map_tbl_get( - a_uint32_t dev_id, - a_uint32_t index, - union ucast_priority_map_tbl_u *value) -{ - if (index >= UCAST_PRIORITY_MAP_TBL_MAX_ENTRY) - return SW_OUT_OF_RANGE; - return hppe_reg_get( - dev_id, - QUEUE_MANAGER_BASE_ADDR + UCAST_PRIORITY_MAP_TBL_ADDRESS + \ - index * UCAST_PRIORITY_MAP_TBL_INC, - &value->val); -} - -sw_error_t -hppe_ucast_priority_map_tbl_set( - a_uint32_t dev_id, - a_uint32_t index, - union ucast_priority_map_tbl_u *value) -{ - return hppe_reg_set( - dev_id, - QUEUE_MANAGER_BASE_ADDR + UCAST_PRIORITY_MAP_TBL_ADDRESS + \ - index * UCAST_PRIORITY_MAP_TBL_INC, - value->val); -} - -sw_error_t -hppe_mcast_queue_map_tbl_get( - a_uint32_t dev_id, - a_uint32_t index, - union mcast_queue_map_tbl_u *value) -{ - if (index >= MCAST_QUEUE_MAP_TBL_MAX_ENTRY) - return SW_OUT_OF_RANGE; - return hppe_reg_get( - dev_id, - QUEUE_MANAGER_BASE_ADDR + MCAST_QUEUE_MAP_TBL_ADDRESS + \ - index * MCAST_QUEUE_MAP_TBL_INC, - &value->val); -} - -sw_error_t -hppe_mcast_queue_map_tbl_set( - a_uint32_t dev_id, - a_uint32_t index, - union mcast_queue_map_tbl_u *value) -{ - return hppe_reg_set( - dev_id, - QUEUE_MANAGER_BASE_ADDR + MCAST_QUEUE_MAP_TBL_ADDRESS + \ - index * MCAST_QUEUE_MAP_TBL_INC, - value->val); -} - -sw_error_t -hppe_ac_mseq_tbl_get( - a_uint32_t dev_id, - a_uint32_t index, - union ac_mseq_tbl_u *value) -{ - if (index >= AC_MSEQ_TBL_MAX_ENTRY) - return SW_OUT_OF_RANGE; - return hppe_reg_get( - dev_id, - QUEUE_MANAGER_BASE_ADDR + AC_MSEQ_TBL_ADDRESS + \ - index * AC_MSEQ_TBL_INC, - &value->val); -} - -sw_error_t -hppe_ac_mseq_tbl_set( - a_uint32_t dev_id, - a_uint32_t index, - union ac_mseq_tbl_u *value) -{ - return hppe_reg_set( - dev_id, - QUEUE_MANAGER_BASE_ADDR + AC_MSEQ_TBL_ADDRESS + \ - index * AC_MSEQ_TBL_INC, - value->val); -} -#endif - -sw_error_t -hppe_ac_uni_queue_cfg_tbl_get( - a_uint32_t dev_id, - a_uint32_t index, - union ac_uni_queue_cfg_tbl_u *value) -{ - return hppe_reg_tbl_get( - dev_id, - QUEUE_MANAGER_BASE_ADDR + AC_UNI_QUEUE_CFG_TBL_ADDRESS + \ - index * AC_UNI_QUEUE_CFG_TBL_INC, - value->val, - 4); -} - -sw_error_t -hppe_ac_uni_queue_cfg_tbl_set( - a_uint32_t dev_id, - a_uint32_t index, - union ac_uni_queue_cfg_tbl_u *value) -{ - return hppe_reg_tbl_set( - dev_id, - QUEUE_MANAGER_BASE_ADDR + AC_UNI_QUEUE_CFG_TBL_ADDRESS + \ - index * AC_UNI_QUEUE_CFG_TBL_INC, - value->val, - 4); -} - -sw_error_t -hppe_ac_mul_queue_cfg_tbl_get( - a_uint32_t dev_id, - a_uint32_t index, - union ac_mul_queue_cfg_tbl_u *value) -{ - return hppe_reg_tbl_get( - dev_id, - QUEUE_MANAGER_BASE_ADDR + AC_MUL_QUEUE_CFG_TBL_ADDRESS + \ - index * AC_MUL_QUEUE_CFG_TBL_INC, - value->val, - 3); -} - -sw_error_t -hppe_ac_mul_queue_cfg_tbl_set( - a_uint32_t dev_id, - a_uint32_t index, - union ac_mul_queue_cfg_tbl_u *value) -{ - return hppe_reg_tbl_set( - dev_id, - QUEUE_MANAGER_BASE_ADDR + AC_MUL_QUEUE_CFG_TBL_ADDRESS + \ - index * AC_MUL_QUEUE_CFG_TBL_INC, - value->val, - 3); -} - -sw_error_t -hppe_ac_grp_cfg_tbl_get( - a_uint32_t dev_id, - a_uint32_t index, - union ac_grp_cfg_tbl_u *value) -{ - return hppe_reg_tbl_get( - dev_id, - QUEUE_MANAGER_BASE_ADDR + AC_GRP_CFG_TBL_ADDRESS + \ - index * AC_GRP_CFG_TBL_INC, - value->val, - 3); -} - -sw_error_t -hppe_ac_grp_cfg_tbl_set( - a_uint32_t dev_id, - a_uint32_t index, - union ac_grp_cfg_tbl_u *value) -{ - return hppe_reg_tbl_set( - dev_id, - QUEUE_MANAGER_BASE_ADDR + AC_GRP_CFG_TBL_ADDRESS + \ - index * AC_GRP_CFG_TBL_INC, - value->val, - 3); -} - -#ifndef IN_QM_MINI -sw_error_t -hppe_ac_uni_queue_cnt_tbl_get( - a_uint32_t dev_id, - a_uint32_t index, - union ac_uni_queue_cnt_tbl_u *value) -{ - if (index >= AC_UNI_QUEUE_CNT_TBL_MAX_ENTRY) - return SW_OUT_OF_RANGE; - return hppe_reg_get( - dev_id, - QUEUE_MANAGER_BASE_ADDR + AC_UNI_QUEUE_CNT_TBL_ADDRESS + \ - index * AC_UNI_QUEUE_CNT_TBL_INC, - &value->val); -} - -sw_error_t -hppe_ac_uni_queue_cnt_tbl_set( - a_uint32_t dev_id, - a_uint32_t index, - union ac_uni_queue_cnt_tbl_u *value) -{ - return hppe_reg_set( - dev_id, - QUEUE_MANAGER_BASE_ADDR + AC_UNI_QUEUE_CNT_TBL_ADDRESS + \ - index * AC_UNI_QUEUE_CNT_TBL_INC, - value->val); -} - -sw_error_t -hppe_ac_mul_queue_cnt_tbl_get( - a_uint32_t dev_id, - a_uint32_t index, - union ac_mul_queue_cnt_tbl_u *value) -{ - if (index >= AC_MUL_QUEUE_CNT_TBL_MAX_ENTRY) - return SW_OUT_OF_RANGE; - return hppe_reg_get( - dev_id, - QUEUE_MANAGER_BASE_ADDR + AC_MUL_QUEUE_CNT_TBL_ADDRESS + \ - index * AC_MUL_QUEUE_CNT_TBL_INC, - &value->val); -} - -sw_error_t -hppe_ac_mul_queue_cnt_tbl_set( - a_uint32_t dev_id, - a_uint32_t index, - union ac_mul_queue_cnt_tbl_u *value) -{ - return hppe_reg_set( - dev_id, - QUEUE_MANAGER_BASE_ADDR + AC_MUL_QUEUE_CNT_TBL_ADDRESS + \ - index * AC_MUL_QUEUE_CNT_TBL_INC, - value->val); -} - -sw_error_t -hppe_ac_grp_cnt_tbl_get( - a_uint32_t dev_id, - a_uint32_t index, - union ac_grp_cnt_tbl_u *value) -{ - if (index >= AC_GRP_CNT_TBL_MAX_ENTRY) - return SW_OUT_OF_RANGE; - return hppe_reg_get( - dev_id, - QUEUE_MANAGER_BASE_ADDR + AC_GRP_CNT_TBL_ADDRESS + \ - index * AC_GRP_CNT_TBL_INC, - &value->val); -} - -sw_error_t -hppe_ac_grp_cnt_tbl_set( - a_uint32_t dev_id, - a_uint32_t index, - union ac_grp_cnt_tbl_u *value) -{ - return hppe_reg_set( - dev_id, - QUEUE_MANAGER_BASE_ADDR + AC_GRP_CNT_TBL_ADDRESS + \ - index * AC_GRP_CNT_TBL_INC, - value->val); -} - -sw_error_t -hppe_ac_uni_queue_drop_state_tbl_get( - a_uint32_t dev_id, - a_uint32_t index, - union ac_uni_queue_drop_state_tbl_u *value) -{ - return hppe_reg_tbl_get( - dev_id, - QUEUE_MANAGER_BASE_ADDR + AC_UNI_QUEUE_DROP_STATE_TBL_ADDRESS + \ - index * AC_UNI_QUEUE_DROP_STATE_TBL_INC, - value->val, - 2); -} - -sw_error_t -hppe_ac_uni_queue_drop_state_tbl_set( - a_uint32_t dev_id, - a_uint32_t index, - union ac_uni_queue_drop_state_tbl_u *value) -{ - return hppe_reg_tbl_set( - dev_id, - QUEUE_MANAGER_BASE_ADDR + AC_UNI_QUEUE_DROP_STATE_TBL_ADDRESS + \ - index * AC_UNI_QUEUE_DROP_STATE_TBL_INC, - value->val, - 2); -} - -sw_error_t -hppe_ac_mul_queue_drop_state_tbl_get( - a_uint32_t dev_id, - a_uint32_t index, - union ac_mul_queue_drop_state_tbl_u *value) -{ - return hppe_reg_tbl_get( - dev_id, - QUEUE_MANAGER_BASE_ADDR + AC_MUL_QUEUE_DROP_STATE_TBL_ADDRESS + \ - index * AC_MUL_QUEUE_DROP_STATE_TBL_INC, - value->val, - 2); -} - -sw_error_t -hppe_ac_mul_queue_drop_state_tbl_set( - a_uint32_t dev_id, - a_uint32_t index, - union ac_mul_queue_drop_state_tbl_u *value) -{ - return hppe_reg_tbl_set( - dev_id, - QUEUE_MANAGER_BASE_ADDR + AC_MUL_QUEUE_DROP_STATE_TBL_ADDRESS + \ - index * AC_MUL_QUEUE_DROP_STATE_TBL_INC, - value->val, - 2); -} - -sw_error_t -hppe_ac_grp_drop_state_tbl_get( - a_uint32_t dev_id, - a_uint32_t index, - union ac_grp_drop_state_tbl_u *value) -{ - return hppe_reg_tbl_get( - dev_id, - QUEUE_MANAGER_BASE_ADDR + AC_GRP_DROP_STATE_TBL_ADDRESS + \ - index * AC_GRP_DROP_STATE_TBL_INC, - value->val, - 2); -} - -sw_error_t -hppe_ac_grp_drop_state_tbl_set( - a_uint32_t dev_id, - a_uint32_t index, - union ac_grp_drop_state_tbl_u *value) -{ - return hppe_reg_tbl_set( - dev_id, - QUEUE_MANAGER_BASE_ADDR + AC_GRP_DROP_STATE_TBL_ADDRESS + \ - index * AC_GRP_DROP_STATE_TBL_INC, - value->val, - 2); -} - -sw_error_t -hppe_oq_enq_opr_tbl_get( - a_uint32_t dev_id, - a_uint32_t index, - union oq_enq_opr_tbl_u *value) -{ - if (index >= OQ_ENQ_OPR_TBL_MAX_ENTRY) - return SW_OUT_OF_RANGE; - return hppe_reg_get( - dev_id, - QUEUE_MANAGER_BASE_ADDR + OQ_ENQ_OPR_TBL_ADDRESS + \ - index * OQ_ENQ_OPR_TBL_INC, - &value->val); -} -#endif - -sw_error_t -hppe_oq_enq_opr_tbl_set( - a_uint32_t dev_id, - a_uint32_t index, - union oq_enq_opr_tbl_u *value) -{ - return hppe_reg_set( - dev_id, - QUEUE_MANAGER_BASE_ADDR + OQ_ENQ_OPR_TBL_ADDRESS + \ - index * OQ_ENQ_OPR_TBL_INC, - value->val); -} - -#ifndef IN_QM_MINI -sw_error_t -hppe_oq_deq_opr_tbl_get( - a_uint32_t dev_id, - a_uint32_t index, - union oq_deq_opr_tbl_u *value) -{ - if (index >= OQ_DEQ_OPR_TBL_MAX_ENTRY) - return SW_OUT_OF_RANGE; - return hppe_reg_get( - dev_id, - QUEUE_MANAGER_BASE_ADDR + OQ_DEQ_OPR_TBL_ADDRESS + \ - index * OQ_DEQ_OPR_TBL_INC, - &value->val); -} - -sw_error_t -hppe_oq_deq_opr_tbl_set( - a_uint32_t dev_id, - a_uint32_t index, - union oq_deq_opr_tbl_u *value) -{ - return hppe_reg_set( - dev_id, - QUEUE_MANAGER_BASE_ADDR + OQ_DEQ_OPR_TBL_ADDRESS + \ - index * OQ_DEQ_OPR_TBL_INC, - value->val); -} - -sw_error_t -hppe_oq_head_uni_tbl_get( - a_uint32_t dev_id, - a_uint32_t index, - union oq_head_uni_tbl_u *value) -{ - if (index >= OQ_HEAD_UNI_TBL_MAX_ENTRY) - return SW_OUT_OF_RANGE; - return hppe_reg_get( - dev_id, - QUEUE_MANAGER_BASE_ADDR + OQ_HEAD_UNI_TBL_ADDRESS + \ - index * OQ_HEAD_UNI_TBL_INC, - &value->val); -} - -sw_error_t -hppe_oq_head_uni_tbl_set( - a_uint32_t dev_id, - a_uint32_t index, - union oq_head_uni_tbl_u *value) -{ - return hppe_reg_set( - dev_id, - QUEUE_MANAGER_BASE_ADDR + OQ_HEAD_UNI_TBL_ADDRESS + \ - index * OQ_HEAD_UNI_TBL_INC, - value->val); -} - -sw_error_t -hppe_oq_head_mul_tbl_get( - a_uint32_t dev_id, - a_uint32_t index, - union oq_head_mul_tbl_u *value) -{ - if (index >= OQ_HEAD_MUL_TBL_MAX_ENTRY) - return SW_OUT_OF_RANGE; - return hppe_reg_get( - dev_id, - QUEUE_MANAGER_BASE_ADDR + OQ_HEAD_MUL_TBL_ADDRESS + \ - index * OQ_HEAD_MUL_TBL_INC, - &value->val); -} - -sw_error_t -hppe_oq_head_mul_tbl_set( - a_uint32_t dev_id, - a_uint32_t index, - union oq_head_mul_tbl_u *value) -{ - return hppe_reg_set( - dev_id, - QUEUE_MANAGER_BASE_ADDR + OQ_HEAD_MUL_TBL_ADDRESS + \ - index * OQ_HEAD_MUL_TBL_INC, - value->val); -} - -sw_error_t -hppe_oq_ll_uni_tbl_get( - a_uint32_t dev_id, - a_uint32_t index, - union oq_ll_uni_tbl_u *value) -{ - if (index >= OQ_LL_UNI_TBL_MAX_ENTRY) - return SW_OUT_OF_RANGE; - return hppe_reg_get( - dev_id, - QUEUE_MANAGER_BASE_ADDR + OQ_LL_UNI_TBL_ADDRESS + \ - index * OQ_LL_UNI_TBL_INC, - &value->val); -} - -sw_error_t -hppe_oq_ll_uni_tbl_set( - a_uint32_t dev_id, - a_uint32_t index, - union oq_ll_uni_tbl_u *value) -{ - return hppe_reg_set( - dev_id, - QUEUE_MANAGER_BASE_ADDR + OQ_LL_UNI_TBL_ADDRESS + \ - index * OQ_LL_UNI_TBL_INC, - value->val); -} - -sw_error_t -hppe_oq_ll_mul_p0_tbl_get( - a_uint32_t dev_id, - a_uint32_t index, - union oq_ll_mul_p0_tbl_u *value) -{ - if (index >= OQ_LL_MUL_P0_TBL_MAX_ENTRY) - return SW_OUT_OF_RANGE; - return hppe_reg_get( - dev_id, - QUEUE_MANAGER_BASE_ADDR + OQ_LL_MUL_P0_TBL_ADDRESS + \ - index * OQ_LL_MUL_P0_TBL_INC, - &value->val); -} - -sw_error_t -hppe_oq_ll_mul_p0_tbl_set( - a_uint32_t dev_id, - a_uint32_t index, - union oq_ll_mul_p0_tbl_u *value) -{ - return hppe_reg_set( - dev_id, - QUEUE_MANAGER_BASE_ADDR + OQ_LL_MUL_P0_TBL_ADDRESS + \ - index * OQ_LL_MUL_P0_TBL_INC, - value->val); -} - -sw_error_t -hppe_oq_ll_mul_p1_tbl_get( - a_uint32_t dev_id, - a_uint32_t index, - union oq_ll_mul_p1_tbl_u *value) -{ - if (index >= OQ_LL_MUL_P1_TBL_MAX_ENTRY) - return SW_OUT_OF_RANGE; - return hppe_reg_get( - dev_id, - QUEUE_MANAGER_BASE_ADDR + OQ_LL_MUL_P1_TBL_ADDRESS + \ - index * OQ_LL_MUL_P1_TBL_INC, - &value->val); -} - -sw_error_t -hppe_oq_ll_mul_p1_tbl_set( - a_uint32_t dev_id, - a_uint32_t index, - union oq_ll_mul_p1_tbl_u *value) -{ - return hppe_reg_set( - dev_id, - QUEUE_MANAGER_BASE_ADDR + OQ_LL_MUL_P1_TBL_ADDRESS + \ - index * OQ_LL_MUL_P1_TBL_INC, - value->val); -} - -sw_error_t -hppe_oq_ll_mul_p2_tbl_get( - a_uint32_t dev_id, - a_uint32_t index, - union oq_ll_mul_p2_tbl_u *value) -{ - if (index >= OQ_LL_MUL_P2_TBL_MAX_ENTRY) - return SW_OUT_OF_RANGE; - return hppe_reg_get( - dev_id, - QUEUE_MANAGER_BASE_ADDR + OQ_LL_MUL_P2_TBL_ADDRESS + \ - index * OQ_LL_MUL_P2_TBL_INC, - &value->val); -} - -sw_error_t -hppe_oq_ll_mul_p2_tbl_set( - a_uint32_t dev_id, - a_uint32_t index, - union oq_ll_mul_p2_tbl_u *value) -{ - return hppe_reg_set( - dev_id, - QUEUE_MANAGER_BASE_ADDR + OQ_LL_MUL_P2_TBL_ADDRESS + \ - index * OQ_LL_MUL_P2_TBL_INC, - value->val); -} - -sw_error_t -hppe_oq_ll_mul_p3_tbl_get( - a_uint32_t dev_id, - a_uint32_t index, - union oq_ll_mul_p3_tbl_u *value) -{ - if (index >= OQ_LL_MUL_P3_TBL_MAX_ENTRY) - return SW_OUT_OF_RANGE; - return hppe_reg_get( - dev_id, - QUEUE_MANAGER_BASE_ADDR + OQ_LL_MUL_P3_TBL_ADDRESS + \ - index * OQ_LL_MUL_P3_TBL_INC, - &value->val); -} - -sw_error_t -hppe_oq_ll_mul_p3_tbl_set( - a_uint32_t dev_id, - a_uint32_t index, - union oq_ll_mul_p3_tbl_u *value) -{ - return hppe_reg_set( - dev_id, - QUEUE_MANAGER_BASE_ADDR + OQ_LL_MUL_P3_TBL_ADDRESS + \ - index * OQ_LL_MUL_P3_TBL_INC, - value->val); -} - -sw_error_t -hppe_oq_ll_mul_p4_tbl_get( - a_uint32_t dev_id, - a_uint32_t index, - union oq_ll_mul_p4_tbl_u *value) -{ - if (index >= OQ_LL_MUL_P4_TBL_MAX_ENTRY) - return SW_OUT_OF_RANGE; - return hppe_reg_get( - dev_id, - QUEUE_MANAGER_BASE_ADDR + OQ_LL_MUL_P4_TBL_ADDRESS + \ - index * OQ_LL_MUL_P4_TBL_INC, - &value->val); -} - -sw_error_t -hppe_oq_ll_mul_p4_tbl_set( - a_uint32_t dev_id, - a_uint32_t index, - union oq_ll_mul_p4_tbl_u *value) -{ - return hppe_reg_set( - dev_id, - QUEUE_MANAGER_BASE_ADDR + OQ_LL_MUL_P4_TBL_ADDRESS + \ - index * OQ_LL_MUL_P4_TBL_INC, - value->val); -} - -sw_error_t -hppe_oq_ll_mul_p5_tbl_get( - a_uint32_t dev_id, - a_uint32_t index, - union oq_ll_mul_p5_tbl_u *value) -{ - if (index >= OQ_LL_MUL_P5_TBL_MAX_ENTRY) - return SW_OUT_OF_RANGE; - return hppe_reg_get( - dev_id, - QUEUE_MANAGER_BASE_ADDR + OQ_LL_MUL_P5_TBL_ADDRESS + \ - index * OQ_LL_MUL_P5_TBL_INC, - &value->val); -} - -sw_error_t -hppe_oq_ll_mul_p5_tbl_set( - a_uint32_t dev_id, - a_uint32_t index, - union oq_ll_mul_p5_tbl_u *value) -{ - return hppe_reg_set( - dev_id, - QUEUE_MANAGER_BASE_ADDR + OQ_LL_MUL_P5_TBL_ADDRESS + \ - index * OQ_LL_MUL_P5_TBL_INC, - value->val); -} - -sw_error_t -hppe_oq_ll_mul_p6_tbl_get( - a_uint32_t dev_id, - a_uint32_t index, - union oq_ll_mul_p6_tbl_u *value) -{ - if (index >= OQ_LL_MUL_P6_TBL_MAX_ENTRY) - return SW_OUT_OF_RANGE; - return hppe_reg_get( - dev_id, - QUEUE_MANAGER_BASE_ADDR + OQ_LL_MUL_P6_TBL_ADDRESS + \ - index * OQ_LL_MUL_P6_TBL_INC, - &value->val); -} - -sw_error_t -hppe_oq_ll_mul_p6_tbl_set( - a_uint32_t dev_id, - a_uint32_t index, - union oq_ll_mul_p6_tbl_u *value) -{ - return hppe_reg_set( - dev_id, - QUEUE_MANAGER_BASE_ADDR + OQ_LL_MUL_P6_TBL_ADDRESS + \ - index * OQ_LL_MUL_P6_TBL_INC, - value->val); -} - -sw_error_t -hppe_oq_ll_mul_p7_tbl_get( - a_uint32_t dev_id, - a_uint32_t index, - union oq_ll_mul_p7_tbl_u *value) -{ - if (index >= OQ_LL_MUL_P7_TBL_MAX_ENTRY) - return SW_OUT_OF_RANGE; - return hppe_reg_get( - dev_id, - QUEUE_MANAGER_BASE_ADDR + OQ_LL_MUL_P7_TBL_ADDRESS + \ - index * OQ_LL_MUL_P7_TBL_INC, - &value->val); -} - -sw_error_t -hppe_oq_ll_mul_p7_tbl_set( - a_uint32_t dev_id, - a_uint32_t index, - union oq_ll_mul_p7_tbl_u *value) -{ - return hppe_reg_set( - dev_id, - QUEUE_MANAGER_BASE_ADDR + OQ_LL_MUL_P7_TBL_ADDRESS + \ - index * OQ_LL_MUL_P7_TBL_INC, - value->val); -} - -sw_error_t -hppe_pkt_desp_tbl_get( - a_uint32_t dev_id, - a_uint32_t index, - union pkt_desp_tbl_u *value) -{ - return hppe_reg_tbl_get( - dev_id, - QUEUE_MANAGER_BASE_ADDR + PKT_DESP_TBL_ADDRESS + \ - index * PKT_DESP_TBL_INC, - value->val, - 13); -} - -sw_error_t -hppe_pkt_desp_tbl_set( - a_uint32_t dev_id, - a_uint32_t index, - union pkt_desp_tbl_u *value) -{ - return hppe_reg_tbl_set( - dev_id, - QUEUE_MANAGER_BASE_ADDR + PKT_DESP_TBL_ADDRESS + \ - index * PKT_DESP_TBL_INC, - value->val, - 13); -} - -sw_error_t -hppe_uni_drop_cnt_tbl_get( - a_uint32_t dev_id, - a_uint32_t index, - union uni_drop_cnt_tbl_u *value) -{ - return hppe_reg_tbl_get( - dev_id, - QUEUE_MANAGER_BASE_ADDR + UNI_DROP_CNT_TBL_ADDRESS + \ - index * UNI_DROP_CNT_TBL_INC, - value->val, - 3); -} - -sw_error_t -hppe_uni_drop_cnt_tbl_set( - a_uint32_t dev_id, - a_uint32_t index, - union uni_drop_cnt_tbl_u *value) -{ - return hppe_reg_tbl_set( - dev_id, - QUEUE_MANAGER_BASE_ADDR + UNI_DROP_CNT_TBL_ADDRESS + \ - index * UNI_DROP_CNT_TBL_INC, - value->val, - 3); -} - -sw_error_t -hppe_mul_p0_drop_cnt_tbl_get( - a_uint32_t dev_id, - a_uint32_t index, - union mul_p0_drop_cnt_tbl_u *value) -{ - return hppe_reg_tbl_get( - dev_id, - QUEUE_MANAGER_BASE_ADDR + MUL_P0_DROP_CNT_TBL_ADDRESS + \ - index * MUL_P0_DROP_CNT_TBL_INC, - value->val, - 3); -} - -sw_error_t -hppe_mul_p0_drop_cnt_tbl_set( - a_uint32_t dev_id, - a_uint32_t index, - union mul_p0_drop_cnt_tbl_u *value) -{ - return hppe_reg_tbl_set( - dev_id, - QUEUE_MANAGER_BASE_ADDR + MUL_P0_DROP_CNT_TBL_ADDRESS + \ - index * MUL_P0_DROP_CNT_TBL_INC, - value->val, - 3); -} - -sw_error_t -hppe_mul_p1_drop_cnt_tbl_get( - a_uint32_t dev_id, - a_uint32_t index, - union mul_p1_drop_cnt_tbl_u *value) -{ - return hppe_reg_tbl_get( - dev_id, - QUEUE_MANAGER_BASE_ADDR + MUL_P1_DROP_CNT_TBL_ADDRESS + \ - index * MUL_P1_DROP_CNT_TBL_INC, - value->val, - 3); -} - -sw_error_t -hppe_mul_p1_drop_cnt_tbl_set( - a_uint32_t dev_id, - a_uint32_t index, - union mul_p1_drop_cnt_tbl_u *value) -{ - return hppe_reg_tbl_set( - dev_id, - QUEUE_MANAGER_BASE_ADDR + MUL_P1_DROP_CNT_TBL_ADDRESS + \ - index * MUL_P1_DROP_CNT_TBL_INC, - value->val, - 3); -} - -sw_error_t -hppe_mul_p2_drop_cnt_tbl_get( - a_uint32_t dev_id, - a_uint32_t index, - union mul_p2_drop_cnt_tbl_u *value) -{ - return hppe_reg_tbl_get( - dev_id, - QUEUE_MANAGER_BASE_ADDR + MUL_P2_DROP_CNT_TBL_ADDRESS + \ - index * MUL_P2_DROP_CNT_TBL_INC, - value->val, - 3); -} - -sw_error_t -hppe_mul_p2_drop_cnt_tbl_set( - a_uint32_t dev_id, - a_uint32_t index, - union mul_p2_drop_cnt_tbl_u *value) -{ - return hppe_reg_tbl_set( - dev_id, - QUEUE_MANAGER_BASE_ADDR + MUL_P2_DROP_CNT_TBL_ADDRESS + \ - index * MUL_P2_DROP_CNT_TBL_INC, - value->val, - 3); -} - -sw_error_t -hppe_mul_p3_drop_cnt_tbl_get( - a_uint32_t dev_id, - a_uint32_t index, - union mul_p3_drop_cnt_tbl_u *value) -{ - return hppe_reg_tbl_get( - dev_id, - QUEUE_MANAGER_BASE_ADDR + MUL_P3_DROP_CNT_TBL_ADDRESS + \ - index * MUL_P3_DROP_CNT_TBL_INC, - value->val, - 3); -} - -sw_error_t -hppe_mul_p3_drop_cnt_tbl_set( - a_uint32_t dev_id, - a_uint32_t index, - union mul_p3_drop_cnt_tbl_u *value) -{ - return hppe_reg_tbl_set( - dev_id, - QUEUE_MANAGER_BASE_ADDR + MUL_P3_DROP_CNT_TBL_ADDRESS + \ - index * MUL_P3_DROP_CNT_TBL_INC, - value->val, - 3); -} - -sw_error_t -hppe_mul_p4_drop_cnt_tbl_get( - a_uint32_t dev_id, - a_uint32_t index, - union mul_p4_drop_cnt_tbl_u *value) -{ - return hppe_reg_tbl_get( - dev_id, - QUEUE_MANAGER_BASE_ADDR + MUL_P4_DROP_CNT_TBL_ADDRESS + \ - index * MUL_P4_DROP_CNT_TBL_INC, - value->val, - 3); -} - -sw_error_t -hppe_mul_p4_drop_cnt_tbl_set( - a_uint32_t dev_id, - a_uint32_t index, - union mul_p4_drop_cnt_tbl_u *value) -{ - return hppe_reg_tbl_set( - dev_id, - QUEUE_MANAGER_BASE_ADDR + MUL_P4_DROP_CNT_TBL_ADDRESS + \ - index * MUL_P4_DROP_CNT_TBL_INC, - value->val, - 3); -} - -sw_error_t -hppe_mul_p5_drop_cnt_tbl_get( - a_uint32_t dev_id, - a_uint32_t index, - union mul_p5_drop_cnt_tbl_u *value) -{ - return hppe_reg_tbl_get( - dev_id, - QUEUE_MANAGER_BASE_ADDR + MUL_P5_DROP_CNT_TBL_ADDRESS + \ - index * MUL_P5_DROP_CNT_TBL_INC, - value->val, - 3); -} - -sw_error_t -hppe_mul_p5_drop_cnt_tbl_set( - a_uint32_t dev_id, - a_uint32_t index, - union mul_p5_drop_cnt_tbl_u *value) -{ - return hppe_reg_tbl_set( - dev_id, - QUEUE_MANAGER_BASE_ADDR + MUL_P5_DROP_CNT_TBL_ADDRESS + \ - index * MUL_P5_DROP_CNT_TBL_INC, - value->val, - 3); -} - -sw_error_t -hppe_mul_p6_drop_cnt_tbl_get( - a_uint32_t dev_id, - a_uint32_t index, - union mul_p6_drop_cnt_tbl_u *value) -{ - return hppe_reg_tbl_get( - dev_id, - QUEUE_MANAGER_BASE_ADDR + MUL_P6_DROP_CNT_TBL_ADDRESS + \ - index * MUL_P6_DROP_CNT_TBL_INC, - value->val, - 3); -} - -sw_error_t -hppe_mul_p6_drop_cnt_tbl_set( - a_uint32_t dev_id, - a_uint32_t index, - union mul_p6_drop_cnt_tbl_u *value) -{ - return hppe_reg_tbl_set( - dev_id, - QUEUE_MANAGER_BASE_ADDR + MUL_P6_DROP_CNT_TBL_ADDRESS + \ - index * MUL_P6_DROP_CNT_TBL_INC, - value->val, - 3); -} - -sw_error_t -hppe_mul_p7_drop_cnt_tbl_get( - a_uint32_t dev_id, - a_uint32_t index, - union mul_p7_drop_cnt_tbl_u *value) -{ - return hppe_reg_tbl_get( - dev_id, - QUEUE_MANAGER_BASE_ADDR + MUL_P7_DROP_CNT_TBL_ADDRESS + \ - index * MUL_P7_DROP_CNT_TBL_INC, - value->val, - 3); -} - -sw_error_t -hppe_mul_p7_drop_cnt_tbl_set( - a_uint32_t dev_id, - a_uint32_t index, - union mul_p7_drop_cnt_tbl_u *value) -{ - return hppe_reg_tbl_set( - dev_id, - QUEUE_MANAGER_BASE_ADDR + MUL_P7_DROP_CNT_TBL_ADDRESS + \ - index * MUL_P7_DROP_CNT_TBL_INC, - value->val, - 3); -} - -sw_error_t -hppe_uq_agg_profile_map_get( - a_uint32_t dev_id, - a_uint32_t index, - union uq_agg_profile_map_u *value) -{ - if (index >= UQ_AGG_PROFILE_MAP_MAX_ENTRY) - return SW_OUT_OF_RANGE; - return hppe_reg_get( - dev_id, - QUEUE_MANAGER_BASE_ADDR + UQ_AGG_PROFILE_MAP_ADDRESS + \ - index * UQ_AGG_PROFILE_MAP_INC, - &value->val); -} - -sw_error_t -hppe_uq_agg_profile_map_set( - a_uint32_t dev_id, - a_uint32_t index, - union uq_agg_profile_map_u *value) -{ - return hppe_reg_set( - dev_id, - QUEUE_MANAGER_BASE_ADDR + UQ_AGG_PROFILE_MAP_ADDRESS + \ - index * UQ_AGG_PROFILE_MAP_INC, - value->val); -} - -sw_error_t -hppe_flush_cfg_flush_busy_get( - a_uint32_t dev_id, - a_uint32_t *value) -{ - union flush_cfg_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_flush_cfg_get(dev_id, ®_val); - *value = reg_val.bf.flush_busy; - return ret; -} - -sw_error_t -hppe_flush_cfg_flush_busy_set( - a_uint32_t dev_id, - a_uint32_t value) -{ - union flush_cfg_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_flush_cfg_get(dev_id, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.flush_busy = value; - ret = hppe_flush_cfg_set(dev_id, ®_val); - return ret; -} - -sw_error_t -hppe_flush_cfg_flush_qid_get( - a_uint32_t dev_id, - a_uint32_t *value) -{ - union flush_cfg_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_flush_cfg_get(dev_id, ®_val); - *value = reg_val.bf.flush_qid; - return ret; -} - -sw_error_t -hppe_flush_cfg_flush_qid_set( - a_uint32_t dev_id, - a_uint32_t value) -{ - union flush_cfg_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_flush_cfg_get(dev_id, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.flush_qid = value; - ret = hppe_flush_cfg_set(dev_id, ®_val); - return ret; -} - -sw_error_t -hppe_flush_cfg_flush_dst_port_get( - a_uint32_t dev_id, - a_uint32_t *value) -{ - union flush_cfg_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_flush_cfg_get(dev_id, ®_val); - *value = reg_val.bf.flush_dst_port; - return ret; -} - -sw_error_t -hppe_flush_cfg_flush_dst_port_set( - a_uint32_t dev_id, - a_uint32_t value) -{ - union flush_cfg_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_flush_cfg_get(dev_id, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.flush_dst_port = value; - ret = hppe_flush_cfg_set(dev_id, ®_val); - return ret; -} - -sw_error_t -hppe_flush_cfg_flush_all_queues_get( - a_uint32_t dev_id, - a_uint32_t *value) -{ - union flush_cfg_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_flush_cfg_get(dev_id, ®_val); - *value = reg_val.bf.flush_all_queues; - return ret; -} - -sw_error_t -hppe_flush_cfg_flush_all_queues_set( - a_uint32_t dev_id, - a_uint32_t value) -{ - union flush_cfg_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_flush_cfg_get(dev_id, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.flush_all_queues = value; - ret = hppe_flush_cfg_set(dev_id, ®_val); - return ret; -} - -sw_error_t -hppe_flush_cfg_flush_wt_time_get( - a_uint32_t dev_id, - a_uint32_t *value) -{ - union flush_cfg_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_flush_cfg_get(dev_id, ®_val); - *value = reg_val.bf.flush_wt_time; - return ret; -} - -sw_error_t -hppe_flush_cfg_flush_wt_time_set( - a_uint32_t dev_id, - a_uint32_t value) -{ - union flush_cfg_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_flush_cfg_get(dev_id, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.flush_wt_time = value; - ret = hppe_flush_cfg_set(dev_id, ®_val); - return ret; -} - -sw_error_t -hppe_flush_cfg_flush_status_get( - a_uint32_t dev_id, - a_uint32_t *value) -{ - union flush_cfg_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_flush_cfg_get(dev_id, ®_val); - *value = reg_val.bf.flush_status; - return ret; -} - -sw_error_t -hppe_flush_cfg_flush_status_set( - a_uint32_t dev_id, - a_uint32_t value) -{ - union flush_cfg_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_flush_cfg_get(dev_id, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.flush_status = value; - ret = hppe_flush_cfg_set(dev_id, ®_val); - return ret; -} - -sw_error_t -hppe_in_mirror_priority_ctrl_priority_get( - a_uint32_t dev_id, - a_uint32_t *value) -{ - union in_mirror_priority_ctrl_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_in_mirror_priority_ctrl_get(dev_id, ®_val); - *value = reg_val.bf.priority; - return ret; -} - -sw_error_t -hppe_in_mirror_priority_ctrl_priority_set( - a_uint32_t dev_id, - a_uint32_t value) -{ - union in_mirror_priority_ctrl_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_in_mirror_priority_ctrl_get(dev_id, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.priority = value; - ret = hppe_in_mirror_priority_ctrl_set(dev_id, ®_val); - return ret; -} - -sw_error_t -hppe_eg_mirror_priority_ctrl_priority_get( - a_uint32_t dev_id, - a_uint32_t *value) -{ - union eg_mirror_priority_ctrl_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_eg_mirror_priority_ctrl_get(dev_id, ®_val); - *value = reg_val.bf.priority; - return ret; -} - -sw_error_t -hppe_eg_mirror_priority_ctrl_priority_set( - a_uint32_t dev_id, - a_uint32_t value) -{ - union eg_mirror_priority_ctrl_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_eg_mirror_priority_ctrl_get(dev_id, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.priority = value; - ret = hppe_eg_mirror_priority_ctrl_set(dev_id, ®_val); - return ret; -} - -sw_error_t -hppe_ucast_default_hash_hash_get( - a_uint32_t dev_id, - a_uint32_t *value) -{ - union ucast_default_hash_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_ucast_default_hash_get(dev_id, ®_val); - *value = reg_val.bf.hash; - return ret; -} - -sw_error_t -hppe_ucast_default_hash_hash_set( - a_uint32_t dev_id, - a_uint32_t value) -{ - union ucast_default_hash_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_ucast_default_hash_get(dev_id, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.hash = value; - ret = hppe_ucast_default_hash_set(dev_id, ®_val); - return ret; -} - -sw_error_t -hppe_spare_reg0_spare_reg0_get( - a_uint32_t dev_id, - a_uint32_t *value) -{ - union spare_reg0_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_spare_reg0_get(dev_id, ®_val); - *value = reg_val.bf.spare_reg0; - return ret; -} - -sw_error_t -hppe_spare_reg0_spare_reg0_set( - a_uint32_t dev_id, - a_uint32_t value) -{ - union spare_reg0_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_spare_reg0_get(dev_id, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.spare_reg0 = value; - ret = hppe_spare_reg0_set(dev_id, ®_val); - return ret; -} - -sw_error_t -hppe_spare_reg1_spare_reg1_get( - a_uint32_t dev_id, - a_uint32_t *value) -{ - union spare_reg1_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_spare_reg1_get(dev_id, ®_val); - *value = reg_val.bf.spare_reg1; - return ret; -} - -sw_error_t -hppe_spare_reg1_spare_reg1_set( - a_uint32_t dev_id, - a_uint32_t value) -{ - union spare_reg1_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_spare_reg1_get(dev_id, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.spare_reg1 = value; - ret = hppe_spare_reg1_set(dev_id, ®_val); - return ret; -} - -sw_error_t -hppe_qm_dbg_addr_dbg_addr_get( - a_uint32_t dev_id, - a_uint32_t *value) -{ - union qm_dbg_addr_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_qm_dbg_addr_get(dev_id, ®_val); - *value = reg_val.bf.dbg_addr; - return ret; -} - -sw_error_t -hppe_qm_dbg_addr_dbg_addr_set( - a_uint32_t dev_id, - a_uint32_t value) -{ - union qm_dbg_addr_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_qm_dbg_addr_get(dev_id, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.dbg_addr = value; - ret = hppe_qm_dbg_addr_set(dev_id, ®_val); - return ret; -} - -sw_error_t -hppe_qm_dbg_data_dbg_data_get( - a_uint32_t dev_id, - a_uint32_t *value) -{ - union qm_dbg_data_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_qm_dbg_data_get(dev_id, ®_val); - *value = reg_val.bf.dbg_data; - return ret; -} - -sw_error_t -hppe_qm_dbg_data_dbg_data_set( - a_uint32_t dev_id, - a_uint32_t value) -{ - return SW_NOT_SUPPORTED; -} - -sw_error_t -hppe_mcast_priority_map0_class_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union mcast_priority_map0_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_mcast_priority_map0_get(dev_id, index, ®_val); - *value = reg_val.bf.class; - return ret; -} - -sw_error_t -hppe_mcast_priority_map0_class_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - union mcast_priority_map0_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_mcast_priority_map0_get(dev_id, index, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.class = value; - ret = hppe_mcast_priority_map0_set(dev_id, index, ®_val); - return ret; -} - -sw_error_t -hppe_mcast_priority_map1_class_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union mcast_priority_map1_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_mcast_priority_map1_get(dev_id, index, ®_val); - *value = reg_val.bf.class; - return ret; -} - -sw_error_t -hppe_mcast_priority_map1_class_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - union mcast_priority_map1_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_mcast_priority_map1_get(dev_id, index, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.class = value; - ret = hppe_mcast_priority_map1_set(dev_id, index, ®_val); - return ret; -} - -sw_error_t -hppe_mcast_priority_map2_class_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union mcast_priority_map2_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_mcast_priority_map2_get(dev_id, index, ®_val); - *value = reg_val.bf.class; - return ret; -} - -sw_error_t -hppe_mcast_priority_map2_class_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - union mcast_priority_map2_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_mcast_priority_map2_get(dev_id, index, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.class = value; - ret = hppe_mcast_priority_map2_set(dev_id, index, ®_val); - return ret; -} - -sw_error_t -hppe_mcast_priority_map3_class_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union mcast_priority_map3_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_mcast_priority_map3_get(dev_id, index, ®_val); - *value = reg_val.bf.class; - return ret; -} - -sw_error_t -hppe_mcast_priority_map3_class_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - union mcast_priority_map3_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_mcast_priority_map3_get(dev_id, index, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.class = value; - ret = hppe_mcast_priority_map3_set(dev_id, index, ®_val); - return ret; -} - -sw_error_t -hppe_mcast_priority_map4_class_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union mcast_priority_map4_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_mcast_priority_map4_get(dev_id, index, ®_val); - *value = reg_val.bf.class; - return ret; -} - -sw_error_t -hppe_mcast_priority_map4_class_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - union mcast_priority_map4_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_mcast_priority_map4_get(dev_id, index, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.class = value; - ret = hppe_mcast_priority_map4_set(dev_id, index, ®_val); - return ret; -} - -sw_error_t -hppe_mcast_priority_map5_class_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union mcast_priority_map5_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_mcast_priority_map5_get(dev_id, index, ®_val); - *value = reg_val.bf.class; - return ret; -} - -sw_error_t -hppe_mcast_priority_map5_class_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - union mcast_priority_map5_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_mcast_priority_map5_get(dev_id, index, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.class = value; - ret = hppe_mcast_priority_map5_set(dev_id, index, ®_val); - return ret; -} - -sw_error_t -hppe_mcast_priority_map6_class_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union mcast_priority_map6_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_mcast_priority_map6_get(dev_id, index, ®_val); - *value = reg_val.bf.class; - return ret; -} - -sw_error_t -hppe_mcast_priority_map6_class_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - union mcast_priority_map6_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_mcast_priority_map6_get(dev_id, index, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.class = value; - ret = hppe_mcast_priority_map6_set(dev_id, index, ®_val); - return ret; -} - -sw_error_t -hppe_mcast_priority_map7_class_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union mcast_priority_map7_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_mcast_priority_map7_get(dev_id, index, ®_val); - *value = reg_val.bf.class; - return ret; -} - -sw_error_t -hppe_mcast_priority_map7_class_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - union mcast_priority_map7_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_mcast_priority_map7_get(dev_id, index, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.class = value; - ret = hppe_mcast_priority_map7_set(dev_id, index, ®_val); - return ret; -} - -sw_error_t -hppe_agg_profile_cnt_en_mq_p2_en_get( - a_uint32_t dev_id, - a_uint32_t *value) -{ - union agg_profile_cnt_en_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_agg_profile_cnt_en_get(dev_id, ®_val); - *value = reg_val.bf.mq_p2_en; - return ret; -} - -sw_error_t -hppe_agg_profile_cnt_en_mq_p2_en_set( - a_uint32_t dev_id, - a_uint32_t value) -{ - union agg_profile_cnt_en_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_agg_profile_cnt_en_get(dev_id, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.mq_p2_en = value; - ret = hppe_agg_profile_cnt_en_set(dev_id, ®_val); - return ret; -} - -sw_error_t -hppe_agg_profile_cnt_en_uq_en_1_get( - a_uint32_t dev_id, - a_uint32_t *value) -{ - union agg_profile_cnt_en_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_agg_profile_cnt_en_get(dev_id, ®_val); - *value = reg_val.bf.uq_en_1; - return ret; -} - -sw_error_t -hppe_agg_profile_cnt_en_uq_en_1_set( - a_uint32_t dev_id, - a_uint32_t value) -{ - union agg_profile_cnt_en_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_agg_profile_cnt_en_get(dev_id, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.uq_en_1 = value; - ret = hppe_agg_profile_cnt_en_set(dev_id, ®_val); - return ret; -} - -sw_error_t -hppe_agg_profile_cnt_en_mq_p0_en_get( - a_uint32_t dev_id, - a_uint32_t *value) -{ - union agg_profile_cnt_en_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_agg_profile_cnt_en_get(dev_id, ®_val); - *value = reg_val.bf.mq_p0_en; - return ret; -} - -sw_error_t -hppe_agg_profile_cnt_en_mq_p0_en_set( - a_uint32_t dev_id, - a_uint32_t value) -{ - union agg_profile_cnt_en_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_agg_profile_cnt_en_get(dev_id, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.mq_p0_en = value; - ret = hppe_agg_profile_cnt_en_set(dev_id, ®_val); - return ret; -} - -sw_error_t -hppe_agg_profile_cnt_en_grp_1_en_get( - a_uint32_t dev_id, - a_uint32_t *value) -{ - union agg_profile_cnt_en_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_agg_profile_cnt_en_get(dev_id, ®_val); - *value = reg_val.bf.grp_1_en; - return ret; -} - -sw_error_t -hppe_agg_profile_cnt_en_grp_1_en_set( - a_uint32_t dev_id, - a_uint32_t value) -{ - union agg_profile_cnt_en_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_agg_profile_cnt_en_get(dev_id, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.grp_1_en = value; - ret = hppe_agg_profile_cnt_en_set(dev_id, ®_val); - return ret; -} - -sw_error_t -hppe_agg_profile_cnt_en_grp_0_en_get( - a_uint32_t dev_id, - a_uint32_t *value) -{ - union agg_profile_cnt_en_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_agg_profile_cnt_en_get(dev_id, ®_val); - *value = reg_val.bf.grp_0_en; - return ret; -} - -sw_error_t -hppe_agg_profile_cnt_en_grp_0_en_set( - a_uint32_t dev_id, - a_uint32_t value) -{ - union agg_profile_cnt_en_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_agg_profile_cnt_en_get(dev_id, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.grp_0_en = value; - ret = hppe_agg_profile_cnt_en_set(dev_id, ®_val); - return ret; -} - -sw_error_t -hppe_agg_profile_cnt_en_mq_p6_en_get( - a_uint32_t dev_id, - a_uint32_t *value) -{ - union agg_profile_cnt_en_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_agg_profile_cnt_en_get(dev_id, ®_val); - *value = reg_val.bf.mq_p6_en; - return ret; -} - -sw_error_t -hppe_agg_profile_cnt_en_mq_p6_en_set( - a_uint32_t dev_id, - a_uint32_t value) -{ - union agg_profile_cnt_en_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_agg_profile_cnt_en_get(dev_id, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.mq_p6_en = value; - ret = hppe_agg_profile_cnt_en_set(dev_id, ®_val); - return ret; -} - -sw_error_t -hppe_agg_profile_cnt_en_uq_en_3_get( - a_uint32_t dev_id, - a_uint32_t *value) -{ - union agg_profile_cnt_en_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_agg_profile_cnt_en_get(dev_id, ®_val); - *value = reg_val.bf.uq_en_3; - return ret; -} - -sw_error_t -hppe_agg_profile_cnt_en_uq_en_3_set( - a_uint32_t dev_id, - a_uint32_t value) -{ - union agg_profile_cnt_en_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_agg_profile_cnt_en_get(dev_id, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.uq_en_3 = value; - ret = hppe_agg_profile_cnt_en_set(dev_id, ®_val); - return ret; -} - -sw_error_t -hppe_agg_profile_cnt_en_mq_p4_en_get( - a_uint32_t dev_id, - a_uint32_t *value) -{ - union agg_profile_cnt_en_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_agg_profile_cnt_en_get(dev_id, ®_val); - *value = reg_val.bf.mq_p4_en; - return ret; -} - -sw_error_t -hppe_agg_profile_cnt_en_mq_p4_en_set( - a_uint32_t dev_id, - a_uint32_t value) -{ - union agg_profile_cnt_en_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_agg_profile_cnt_en_get(dev_id, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.mq_p4_en = value; - ret = hppe_agg_profile_cnt_en_set(dev_id, ®_val); - return ret; -} - -sw_error_t -hppe_agg_profile_cnt_en_uq_en_2_get( - a_uint32_t dev_id, - a_uint32_t *value) -{ - union agg_profile_cnt_en_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_agg_profile_cnt_en_get(dev_id, ®_val); - *value = reg_val.bf.uq_en_2; - return ret; -} - -sw_error_t -hppe_agg_profile_cnt_en_uq_en_2_set( - a_uint32_t dev_id, - a_uint32_t value) -{ - union agg_profile_cnt_en_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_agg_profile_cnt_en_get(dev_id, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.uq_en_2 = value; - ret = hppe_agg_profile_cnt_en_set(dev_id, ®_val); - return ret; -} - -sw_error_t -hppe_agg_profile_cnt_en_uq_en_5_get( - a_uint32_t dev_id, - a_uint32_t *value) -{ - union agg_profile_cnt_en_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_agg_profile_cnt_en_get(dev_id, ®_val); - *value = reg_val.bf.uq_en_5; - return ret; -} - -sw_error_t -hppe_agg_profile_cnt_en_uq_en_5_set( - a_uint32_t dev_id, - a_uint32_t value) -{ - union agg_profile_cnt_en_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_agg_profile_cnt_en_get(dev_id, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.uq_en_5 = value; - ret = hppe_agg_profile_cnt_en_set(dev_id, ®_val); - return ret; -} - -sw_error_t -hppe_agg_profile_cnt_en_uq_en_6_get( - a_uint32_t dev_id, - a_uint32_t *value) -{ - union agg_profile_cnt_en_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_agg_profile_cnt_en_get(dev_id, ®_val); - *value = reg_val.bf.uq_en_6; - return ret; -} - -sw_error_t -hppe_agg_profile_cnt_en_uq_en_6_set( - a_uint32_t dev_id, - a_uint32_t value) -{ - union agg_profile_cnt_en_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_agg_profile_cnt_en_get(dev_id, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.uq_en_6 = value; - ret = hppe_agg_profile_cnt_en_set(dev_id, ®_val); - return ret; -} - -sw_error_t -hppe_agg_profile_cnt_en_grp_3_en_get( - a_uint32_t dev_id, - a_uint32_t *value) -{ - union agg_profile_cnt_en_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_agg_profile_cnt_en_get(dev_id, ®_val); - *value = reg_val.bf.grp_3_en; - return ret; -} - -sw_error_t -hppe_agg_profile_cnt_en_grp_3_en_set( - a_uint32_t dev_id, - a_uint32_t value) -{ - union agg_profile_cnt_en_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_agg_profile_cnt_en_get(dev_id, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.grp_3_en = value; - ret = hppe_agg_profile_cnt_en_set(dev_id, ®_val); - return ret; -} - -sw_error_t -hppe_agg_profile_cnt_en_grp_2_en_get( - a_uint32_t dev_id, - a_uint32_t *value) -{ - union agg_profile_cnt_en_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_agg_profile_cnt_en_get(dev_id, ®_val); - *value = reg_val.bf.grp_2_en; - return ret; -} - -sw_error_t -hppe_agg_profile_cnt_en_grp_2_en_set( - a_uint32_t dev_id, - a_uint32_t value) -{ - union agg_profile_cnt_en_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_agg_profile_cnt_en_get(dev_id, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.grp_2_en = value; - ret = hppe_agg_profile_cnt_en_set(dev_id, ®_val); - return ret; -} - -sw_error_t -hppe_agg_profile_cnt_en_uq_en_4_get( - a_uint32_t dev_id, - a_uint32_t *value) -{ - union agg_profile_cnt_en_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_agg_profile_cnt_en_get(dev_id, ®_val); - *value = reg_val.bf.uq_en_4; - return ret; -} - -sw_error_t -hppe_agg_profile_cnt_en_uq_en_4_set( - a_uint32_t dev_id, - a_uint32_t value) -{ - union agg_profile_cnt_en_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_agg_profile_cnt_en_get(dev_id, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.uq_en_4 = value; - ret = hppe_agg_profile_cnt_en_set(dev_id, ®_val); - return ret; -} - -sw_error_t -hppe_agg_profile_cnt_en_mq_p7_en_get( - a_uint32_t dev_id, - a_uint32_t *value) -{ - union agg_profile_cnt_en_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_agg_profile_cnt_en_get(dev_id, ®_val); - *value = reg_val.bf.mq_p7_en; - return ret; -} - -sw_error_t -hppe_agg_profile_cnt_en_mq_p7_en_set( - a_uint32_t dev_id, - a_uint32_t value) -{ - union agg_profile_cnt_en_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_agg_profile_cnt_en_get(dev_id, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.mq_p7_en = value; - ret = hppe_agg_profile_cnt_en_set(dev_id, ®_val); - return ret; -} - -sw_error_t -hppe_agg_profile_cnt_en_uq_en_7_get( - a_uint32_t dev_id, - a_uint32_t *value) -{ - union agg_profile_cnt_en_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_agg_profile_cnt_en_get(dev_id, ®_val); - *value = reg_val.bf.uq_en_7; - return ret; -} - -sw_error_t -hppe_agg_profile_cnt_en_uq_en_7_set( - a_uint32_t dev_id, - a_uint32_t value) -{ - union agg_profile_cnt_en_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_agg_profile_cnt_en_get(dev_id, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.uq_en_7 = value; - ret = hppe_agg_profile_cnt_en_set(dev_id, ®_val); - return ret; -} - -sw_error_t -hppe_agg_profile_cnt_en_global_en_get( - a_uint32_t dev_id, - a_uint32_t *value) -{ - union agg_profile_cnt_en_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_agg_profile_cnt_en_get(dev_id, ®_val); - *value = reg_val.bf.global_en; - return ret; -} - -sw_error_t -hppe_agg_profile_cnt_en_global_en_set( - a_uint32_t dev_id, - a_uint32_t value) -{ - union agg_profile_cnt_en_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_agg_profile_cnt_en_get(dev_id, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.global_en = value; - ret = hppe_agg_profile_cnt_en_set(dev_id, ®_val); - return ret; -} - -sw_error_t -hppe_agg_profile_cnt_en_mq_p5_en_get( - a_uint32_t dev_id, - a_uint32_t *value) -{ - union agg_profile_cnt_en_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_agg_profile_cnt_en_get(dev_id, ®_val); - *value = reg_val.bf.mq_p5_en; - return ret; -} - -sw_error_t -hppe_agg_profile_cnt_en_mq_p5_en_set( - a_uint32_t dev_id, - a_uint32_t value) -{ - union agg_profile_cnt_en_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_agg_profile_cnt_en_get(dev_id, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.mq_p5_en = value; - ret = hppe_agg_profile_cnt_en_set(dev_id, ®_val); - return ret; -} - -sw_error_t -hppe_agg_profile_cnt_en_mq_p1_en_get( - a_uint32_t dev_id, - a_uint32_t *value) -{ - union agg_profile_cnt_en_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_agg_profile_cnt_en_get(dev_id, ®_val); - *value = reg_val.bf.mq_p1_en; - return ret; -} - -sw_error_t -hppe_agg_profile_cnt_en_mq_p1_en_set( - a_uint32_t dev_id, - a_uint32_t value) -{ - union agg_profile_cnt_en_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_agg_profile_cnt_en_get(dev_id, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.mq_p1_en = value; - ret = hppe_agg_profile_cnt_en_set(dev_id, ®_val); - return ret; -} - -sw_error_t -hppe_agg_profile_cnt_en_uq_en_0_get( - a_uint32_t dev_id, - a_uint32_t *value) -{ - union agg_profile_cnt_en_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_agg_profile_cnt_en_get(dev_id, ®_val); - *value = reg_val.bf.uq_en_0; - return ret; -} - -sw_error_t -hppe_agg_profile_cnt_en_uq_en_0_set( - a_uint32_t dev_id, - a_uint32_t value) -{ - union agg_profile_cnt_en_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_agg_profile_cnt_en_get(dev_id, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.uq_en_0 = value; - ret = hppe_agg_profile_cnt_en_set(dev_id, ®_val); - return ret; -} - -sw_error_t -hppe_agg_profile_cnt_en_mq_p3_en_get( - a_uint32_t dev_id, - a_uint32_t *value) -{ - union agg_profile_cnt_en_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_agg_profile_cnt_en_get(dev_id, ®_val); - *value = reg_val.bf.mq_p3_en; - return ret; -} - -sw_error_t -hppe_agg_profile_cnt_en_mq_p3_en_set( - a_uint32_t dev_id, - a_uint32_t value) -{ - union agg_profile_cnt_en_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_agg_profile_cnt_en_get(dev_id, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.mq_p3_en = value; - ret = hppe_agg_profile_cnt_en_set(dev_id, ®_val); - return ret; -} - -sw_error_t -hppe_uq_agg_profile_cfg_th_cfg_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union uq_agg_profile_cfg_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_uq_agg_profile_cfg_get(dev_id, index, ®_val); - *value = reg_val.bf.th_cfg; - return ret; -} - -sw_error_t -hppe_uq_agg_profile_cfg_th_cfg_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - union uq_agg_profile_cfg_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_uq_agg_profile_cfg_get(dev_id, index, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.th_cfg = value; - ret = hppe_uq_agg_profile_cfg_set(dev_id, index, ®_val); - return ret; -} - -sw_error_t -hppe_mq_agg_profile_cfg_th_cfg_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union mq_agg_profile_cfg_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_mq_agg_profile_cfg_get(dev_id, index, ®_val); - *value = reg_val.bf.th_cfg; - return ret; -} - -sw_error_t -hppe_mq_agg_profile_cfg_th_cfg_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - union mq_agg_profile_cfg_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_mq_agg_profile_cfg_get(dev_id, index, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.th_cfg = value; - ret = hppe_mq_agg_profile_cfg_set(dev_id, index, ®_val); - return ret; -} - -sw_error_t -hppe_grp_agg_profile_cfg_th_cfg_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union grp_agg_profile_cfg_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_grp_agg_profile_cfg_get(dev_id, index, ®_val); - *value = reg_val.bf.th_cfg; - return ret; -} - -sw_error_t -hppe_grp_agg_profile_cfg_th_cfg_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - union grp_agg_profile_cfg_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_grp_agg_profile_cfg_get(dev_id, index, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.th_cfg = value; - ret = hppe_grp_agg_profile_cfg_set(dev_id, index, ®_val); - return ret; -} - -sw_error_t -hppe_uq_agg_in_profile_cnt_cnt_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union uq_agg_in_profile_cnt_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_uq_agg_in_profile_cnt_get(dev_id, index, ®_val); - *value = reg_val.bf.cnt; - return ret; -} - -sw_error_t -hppe_uq_agg_in_profile_cnt_cnt_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - union uq_agg_in_profile_cnt_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_uq_agg_in_profile_cnt_get(dev_id, index, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.cnt = value; - ret = hppe_uq_agg_in_profile_cnt_set(dev_id, index, ®_val); - return ret; -} - -sw_error_t -hppe_uq_agg_out_profile_cnt_cnt_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union uq_agg_out_profile_cnt_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_uq_agg_out_profile_cnt_get(dev_id, index, ®_val); - *value = reg_val.bf.cnt; - return ret; -} - -sw_error_t -hppe_uq_agg_out_profile_cnt_cnt_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - union uq_agg_out_profile_cnt_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_uq_agg_out_profile_cnt_get(dev_id, index, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.cnt = value; - ret = hppe_uq_agg_out_profile_cnt_set(dev_id, index, ®_val); - return ret; -} - -sw_error_t -hppe_mq_agg_in_profile_cnt_cnt_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union mq_agg_in_profile_cnt_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_mq_agg_in_profile_cnt_get(dev_id, index, ®_val); - *value = reg_val.bf.cnt; - return ret; -} - -sw_error_t -hppe_mq_agg_in_profile_cnt_cnt_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - union mq_agg_in_profile_cnt_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_mq_agg_in_profile_cnt_get(dev_id, index, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.cnt = value; - ret = hppe_mq_agg_in_profile_cnt_set(dev_id, index, ®_val); - return ret; -} - -sw_error_t -hppe_mq_agg_out_profile_cnt_cnt_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union mq_agg_out_profile_cnt_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_mq_agg_out_profile_cnt_get(dev_id, index, ®_val); - *value = reg_val.bf.cnt; - return ret; -} - -sw_error_t -hppe_mq_agg_out_profile_cnt_cnt_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - union mq_agg_out_profile_cnt_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_mq_agg_out_profile_cnt_get(dev_id, index, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.cnt = value; - ret = hppe_mq_agg_out_profile_cnt_set(dev_id, index, ®_val); - return ret; -} - -sw_error_t -hppe_grp_agg_in_profile_cnt_cnt_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union grp_agg_in_profile_cnt_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_grp_agg_in_profile_cnt_get(dev_id, index, ®_val); - *value = reg_val.bf.cnt; - return ret; -} - -sw_error_t -hppe_grp_agg_in_profile_cnt_cnt_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - union grp_agg_in_profile_cnt_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_grp_agg_in_profile_cnt_get(dev_id, index, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.cnt = value; - ret = hppe_grp_agg_in_profile_cnt_set(dev_id, index, ®_val); - return ret; -} - -sw_error_t -hppe_grp_agg_out_profile_cnt_cnt_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union grp_agg_out_profile_cnt_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_grp_agg_out_profile_cnt_get(dev_id, index, ®_val); - *value = reg_val.bf.cnt; - return ret; -} - -sw_error_t -hppe_grp_agg_out_profile_cnt_cnt_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - union grp_agg_out_profile_cnt_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_grp_agg_out_profile_cnt_get(dev_id, index, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.cnt = value; - ret = hppe_grp_agg_out_profile_cnt_set(dev_id, index, ®_val); - return ret; -} - -sw_error_t -hppe_ucast_queue_map_tbl_profile_id_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union ucast_queue_map_tbl_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_ucast_queue_map_tbl_get(dev_id, index, ®_val); - *value = reg_val.bf.profile_id; - return ret; -} - -sw_error_t -hppe_ucast_queue_map_tbl_profile_id_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - union ucast_queue_map_tbl_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_ucast_queue_map_tbl_get(dev_id, index, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.profile_id = value; - ret = hppe_ucast_queue_map_tbl_set(dev_id, index, ®_val); - return ret; -} - -sw_error_t -hppe_ucast_queue_map_tbl_queue_id_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union ucast_queue_map_tbl_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_ucast_queue_map_tbl_get(dev_id, index, ®_val); - *value = reg_val.bf.queue_id; - return ret; -} - -sw_error_t -hppe_ucast_queue_map_tbl_queue_id_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - union ucast_queue_map_tbl_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_ucast_queue_map_tbl_get(dev_id, index, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.queue_id = value; - ret = hppe_ucast_queue_map_tbl_set(dev_id, index, ®_val); - return ret; -} - -sw_error_t -hppe_ucast_hash_map_tbl_hash_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union ucast_hash_map_tbl_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_ucast_hash_map_tbl_get(dev_id, index, ®_val); - *value = reg_val.bf.hash; - return ret; -} - -sw_error_t -hppe_ucast_hash_map_tbl_hash_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - union ucast_hash_map_tbl_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_ucast_hash_map_tbl_get(dev_id, index, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.hash = value; - ret = hppe_ucast_hash_map_tbl_set(dev_id, index, ®_val); - return ret; -} - -sw_error_t -hppe_ucast_priority_map_tbl_class_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union ucast_priority_map_tbl_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_ucast_priority_map_tbl_get(dev_id, index, ®_val); - *value = reg_val.bf.class; - return ret; -} - -sw_error_t -hppe_ucast_priority_map_tbl_class_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - union ucast_priority_map_tbl_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_ucast_priority_map_tbl_get(dev_id, index, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.class = value; - ret = hppe_ucast_priority_map_tbl_set(dev_id, index, ®_val); - return ret; -} - -sw_error_t -hppe_mcast_queue_map_tbl_class_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union mcast_queue_map_tbl_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_mcast_queue_map_tbl_get(dev_id, index, ®_val); - *value = reg_val.bf.class; - return ret; -} - -sw_error_t -hppe_mcast_queue_map_tbl_class_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - union mcast_queue_map_tbl_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_mcast_queue_map_tbl_get(dev_id, index, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.class = value; - ret = hppe_mcast_queue_map_tbl_set(dev_id, index, ®_val); - return ret; -} - -sw_error_t -hppe_ac_mseq_tbl_ac_mseq_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union ac_mseq_tbl_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_ac_mseq_tbl_get(dev_id, index, ®_val); - *value = reg_val.bf.ac_mseq; - return ret; -} - -sw_error_t -hppe_ac_mseq_tbl_ac_mseq_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - union ac_mseq_tbl_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_ac_mseq_tbl_get(dev_id, index, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.ac_mseq = value; - ret = hppe_ac_mseq_tbl_set(dev_id, index, ®_val); - return ret; -} - -sw_error_t -hppe_ac_uni_queue_cfg_tbl_ac_cfg_gap_grn_yel_max_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union ac_uni_queue_cfg_tbl_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_ac_uni_queue_cfg_tbl_get(dev_id, index, ®_val); - *value = reg_val.bf.ac_cfg_gap_grn_yel_max; - return ret; -} - -sw_error_t -hppe_ac_uni_queue_cfg_tbl_ac_cfg_gap_grn_yel_max_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - union ac_uni_queue_cfg_tbl_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_ac_uni_queue_cfg_tbl_get(dev_id, index, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.ac_cfg_gap_grn_yel_max = value; - ret = hppe_ac_uni_queue_cfg_tbl_set(dev_id, index, ®_val); - return ret; -} - -sw_error_t -hppe_ac_uni_queue_cfg_tbl_ac_cfg_wred_en_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union ac_uni_queue_cfg_tbl_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_ac_uni_queue_cfg_tbl_get(dev_id, index, ®_val); - *value = reg_val.bf.ac_cfg_wred_en; - return ret; -} - -sw_error_t -hppe_ac_uni_queue_cfg_tbl_ac_cfg_wred_en_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - union ac_uni_queue_cfg_tbl_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_ac_uni_queue_cfg_tbl_get(dev_id, index, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.ac_cfg_wred_en = value; - ret = hppe_ac_uni_queue_cfg_tbl_set(dev_id, index, ®_val); - return ret; -} - -sw_error_t -hppe_ac_uni_queue_cfg_tbl_ac_cfg_ac_en_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union ac_uni_queue_cfg_tbl_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_ac_uni_queue_cfg_tbl_get(dev_id, index, ®_val); - *value = reg_val.bf.ac_cfg_ac_en; - return ret; -} - -sw_error_t -hppe_ac_uni_queue_cfg_tbl_ac_cfg_ac_en_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - union ac_uni_queue_cfg_tbl_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_ac_uni_queue_cfg_tbl_get(dev_id, index, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.ac_cfg_ac_en = value; - ret = hppe_ac_uni_queue_cfg_tbl_set(dev_id, index, ®_val); - return ret; -} - -sw_error_t -hppe_ac_uni_queue_cfg_tbl_ac_cfg_red_resume_offset_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union ac_uni_queue_cfg_tbl_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_ac_uni_queue_cfg_tbl_get(dev_id, index, ®_val); - *value = reg_val.bf.ac_cfg_red_resume_offset_1 << 9 | \ - reg_val.bf.ac_cfg_red_resume_offset_0; - return ret; -} - -sw_error_t -hppe_ac_uni_queue_cfg_tbl_ac_cfg_red_resume_offset_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - union ac_uni_queue_cfg_tbl_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_ac_uni_queue_cfg_tbl_get(dev_id, index, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.ac_cfg_red_resume_offset_1 = value >> 9; - reg_val.bf.ac_cfg_red_resume_offset_0 = value & (((a_uint64_t)1<<9)-1); - ret = hppe_ac_uni_queue_cfg_tbl_set(dev_id, index, ®_val); - return ret; -} - -sw_error_t -hppe_ac_uni_queue_cfg_tbl_ac_cfg_grp_id_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union ac_uni_queue_cfg_tbl_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_ac_uni_queue_cfg_tbl_get(dev_id, index, ®_val); - *value = reg_val.bf.ac_cfg_grp_id; - return ret; -} - -sw_error_t -hppe_ac_uni_queue_cfg_tbl_ac_cfg_grp_id_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - union ac_uni_queue_cfg_tbl_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_ac_uni_queue_cfg_tbl_get(dev_id, index, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.ac_cfg_grp_id = value; - ret = hppe_ac_uni_queue_cfg_tbl_set(dev_id, index, ®_val); - return ret; -} - -sw_error_t -hppe_ac_uni_queue_cfg_tbl_ac_cfg_color_aware_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union ac_uni_queue_cfg_tbl_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_ac_uni_queue_cfg_tbl_get(dev_id, index, ®_val); - *value = reg_val.bf.ac_cfg_color_aware; - return ret; -} - -sw_error_t -hppe_ac_uni_queue_cfg_tbl_ac_cfg_color_aware_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - union ac_uni_queue_cfg_tbl_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_ac_uni_queue_cfg_tbl_get(dev_id, index, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.ac_cfg_color_aware = value; - ret = hppe_ac_uni_queue_cfg_tbl_set(dev_id, index, ®_val); - return ret; -} - -sw_error_t -hppe_ac_uni_queue_cfg_tbl_ac_cfg_yel_resume_offset_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union ac_uni_queue_cfg_tbl_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_ac_uni_queue_cfg_tbl_get(dev_id, index, ®_val); - *value = reg_val.bf.ac_cfg_yel_resume_offset; - return ret; -} - -sw_error_t -hppe_ac_uni_queue_cfg_tbl_ac_cfg_yel_resume_offset_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - union ac_uni_queue_cfg_tbl_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_ac_uni_queue_cfg_tbl_get(dev_id, index, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.ac_cfg_yel_resume_offset = value; - ret = hppe_ac_uni_queue_cfg_tbl_set(dev_id, index, ®_val); - return ret; -} - -sw_error_t -hppe_ac_uni_queue_cfg_tbl_ac_cfg_gap_grn_yel_min_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union ac_uni_queue_cfg_tbl_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_ac_uni_queue_cfg_tbl_get(dev_id, index, ®_val); - *value = reg_val.bf.ac_cfg_gap_grn_yel_min_1 << 10 | \ - reg_val.bf.ac_cfg_gap_grn_yel_min_0; - return ret; -} - -sw_error_t -hppe_ac_uni_queue_cfg_tbl_ac_cfg_gap_grn_yel_min_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - union ac_uni_queue_cfg_tbl_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_ac_uni_queue_cfg_tbl_get(dev_id, index, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.ac_cfg_gap_grn_yel_min_1 = value >> 10; - reg_val.bf.ac_cfg_gap_grn_yel_min_0 = value & (((a_uint64_t)1<<10)-1); - ret = hppe_ac_uni_queue_cfg_tbl_set(dev_id, index, ®_val); - return ret; -} - -sw_error_t -hppe_ac_uni_queue_cfg_tbl_ac_cfg_shared_weight_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union ac_uni_queue_cfg_tbl_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_ac_uni_queue_cfg_tbl_get(dev_id, index, ®_val); - *value = reg_val.bf.ac_cfg_shared_weight; - return ret; -} - -sw_error_t -hppe_ac_uni_queue_cfg_tbl_ac_cfg_shared_weight_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - union ac_uni_queue_cfg_tbl_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_ac_uni_queue_cfg_tbl_get(dev_id, index, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.ac_cfg_shared_weight = value; - ret = hppe_ac_uni_queue_cfg_tbl_set(dev_id, index, ®_val); - return ret; -} - -sw_error_t -hppe_ac_uni_queue_cfg_tbl_ac_cfg_shared_dynamic_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union ac_uni_queue_cfg_tbl_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_ac_uni_queue_cfg_tbl_get(dev_id, index, ®_val); - *value = reg_val.bf.ac_cfg_shared_dynamic; - return ret; -} - -sw_error_t -hppe_ac_uni_queue_cfg_tbl_ac_cfg_shared_dynamic_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - union ac_uni_queue_cfg_tbl_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_ac_uni_queue_cfg_tbl_get(dev_id, index, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.ac_cfg_shared_dynamic = value; - ret = hppe_ac_uni_queue_cfg_tbl_set(dev_id, index, ®_val); - return ret; -} - -sw_error_t -hppe_ac_uni_queue_cfg_tbl_ac_cfg_gap_grn_red_max_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union ac_uni_queue_cfg_tbl_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_ac_uni_queue_cfg_tbl_get(dev_id, index, ®_val); - *value = reg_val.bf.ac_cfg_gap_grn_red_max; - return ret; -} - -sw_error_t -hppe_ac_uni_queue_cfg_tbl_ac_cfg_gap_grn_red_max_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - union ac_uni_queue_cfg_tbl_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_ac_uni_queue_cfg_tbl_get(dev_id, index, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.ac_cfg_gap_grn_red_max = value; - ret = hppe_ac_uni_queue_cfg_tbl_set(dev_id, index, ®_val); - return ret; -} - -sw_error_t -hppe_ac_uni_queue_cfg_tbl_ac_cfg_pre_alloc_limit_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union ac_uni_queue_cfg_tbl_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_ac_uni_queue_cfg_tbl_get(dev_id, index, ®_val); - *value = reg_val.bf.ac_cfg_pre_alloc_limit; - return ret; -} - -sw_error_t -hppe_ac_uni_queue_cfg_tbl_ac_cfg_pre_alloc_limit_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - union ac_uni_queue_cfg_tbl_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_ac_uni_queue_cfg_tbl_get(dev_id, index, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.ac_cfg_pre_alloc_limit = value; - ret = hppe_ac_uni_queue_cfg_tbl_set(dev_id, index, ®_val); - return ret; -} - -sw_error_t -hppe_ac_uni_queue_cfg_tbl_ac_cfg_force_ac_en_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union ac_uni_queue_cfg_tbl_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_ac_uni_queue_cfg_tbl_get(dev_id, index, ®_val); - *value = reg_val.bf.ac_cfg_force_ac_en; - return ret; -} - -sw_error_t -hppe_ac_uni_queue_cfg_tbl_ac_cfg_force_ac_en_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - union ac_uni_queue_cfg_tbl_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_ac_uni_queue_cfg_tbl_get(dev_id, index, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.ac_cfg_force_ac_en = value; - ret = hppe_ac_uni_queue_cfg_tbl_set(dev_id, index, ®_val); - return ret; -} - -sw_error_t -hppe_ac_uni_queue_cfg_tbl_ac_cfg_gap_grn_red_min_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union ac_uni_queue_cfg_tbl_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_ac_uni_queue_cfg_tbl_get(dev_id, index, ®_val); - *value = reg_val.bf.ac_cfg_gap_grn_red_min; - return ret; -} - -sw_error_t -hppe_ac_uni_queue_cfg_tbl_ac_cfg_gap_grn_red_min_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - union ac_uni_queue_cfg_tbl_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_ac_uni_queue_cfg_tbl_get(dev_id, index, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.ac_cfg_gap_grn_red_min = value; - ret = hppe_ac_uni_queue_cfg_tbl_set(dev_id, index, ®_val); - return ret; -} - -sw_error_t -hppe_ac_uni_queue_cfg_tbl_ac_cfg_gap_grn_grn_min_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union ac_uni_queue_cfg_tbl_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_ac_uni_queue_cfg_tbl_get(dev_id, index, ®_val); - *value = reg_val.bf.ac_cfg_gap_grn_grn_min; - return ret; -} - -sw_error_t -hppe_ac_uni_queue_cfg_tbl_ac_cfg_gap_grn_grn_min_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - union ac_uni_queue_cfg_tbl_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_ac_uni_queue_cfg_tbl_get(dev_id, index, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.ac_cfg_gap_grn_grn_min = value; - ret = hppe_ac_uni_queue_cfg_tbl_set(dev_id, index, ®_val); - return ret; -} - -sw_error_t -hppe_ac_uni_queue_cfg_tbl_ac_cfg_shared_ceiling_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union ac_uni_queue_cfg_tbl_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_ac_uni_queue_cfg_tbl_get(dev_id, index, ®_val); - *value = reg_val.bf.ac_cfg_shared_ceiling; - return ret; -} - -sw_error_t -hppe_ac_uni_queue_cfg_tbl_ac_cfg_shared_ceiling_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - union ac_uni_queue_cfg_tbl_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_ac_uni_queue_cfg_tbl_get(dev_id, index, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.ac_cfg_shared_ceiling = value; - ret = hppe_ac_uni_queue_cfg_tbl_set(dev_id, index, ®_val); - return ret; -} - -sw_error_t -hppe_ac_uni_queue_cfg_tbl_ac_cfg_grn_resume_offset_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union ac_uni_queue_cfg_tbl_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_ac_uni_queue_cfg_tbl_get(dev_id, index, ®_val); - *value = reg_val.bf.ac_cfg_grn_resume_offset; - return ret; -} - -sw_error_t -hppe_ac_uni_queue_cfg_tbl_ac_cfg_grn_resume_offset_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - union ac_uni_queue_cfg_tbl_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_ac_uni_queue_cfg_tbl_get(dev_id, index, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.ac_cfg_grn_resume_offset = value; - ret = hppe_ac_uni_queue_cfg_tbl_set(dev_id, index, ®_val); - return ret; -} - -sw_error_t -hppe_ac_mul_queue_cfg_tbl_ac_cfg_ac_en_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union ac_mul_queue_cfg_tbl_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_ac_mul_queue_cfg_tbl_get(dev_id, index, ®_val); - *value = reg_val.bf.ac_cfg_ac_en; - return ret; -} - -sw_error_t -hppe_ac_mul_queue_cfg_tbl_ac_cfg_ac_en_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - union ac_mul_queue_cfg_tbl_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_ac_mul_queue_cfg_tbl_get(dev_id, index, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.ac_cfg_ac_en = value; - ret = hppe_ac_mul_queue_cfg_tbl_set(dev_id, index, ®_val); - return ret; -} - -sw_error_t -hppe_ac_mul_queue_cfg_tbl_ac_cfg_red_resume_offset_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union ac_mul_queue_cfg_tbl_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_ac_mul_queue_cfg_tbl_get(dev_id, index, ®_val); - *value = reg_val.bf.ac_cfg_red_resume_offset; - return ret; -} - -sw_error_t -hppe_ac_mul_queue_cfg_tbl_ac_cfg_red_resume_offset_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - union ac_mul_queue_cfg_tbl_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_ac_mul_queue_cfg_tbl_get(dev_id, index, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.ac_cfg_red_resume_offset = value; - ret = hppe_ac_mul_queue_cfg_tbl_set(dev_id, index, ®_val); - return ret; -} - -sw_error_t -hppe_ac_mul_queue_cfg_tbl_ac_cfg_grp_id_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union ac_mul_queue_cfg_tbl_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_ac_mul_queue_cfg_tbl_get(dev_id, index, ®_val); - *value = reg_val.bf.ac_cfg_grp_id; - return ret; -} - -sw_error_t -hppe_ac_mul_queue_cfg_tbl_ac_cfg_grp_id_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - union ac_mul_queue_cfg_tbl_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_ac_mul_queue_cfg_tbl_get(dev_id, index, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.ac_cfg_grp_id = value; - ret = hppe_ac_mul_queue_cfg_tbl_set(dev_id, index, ®_val); - return ret; -} - -sw_error_t -hppe_ac_mul_queue_cfg_tbl_ac_cfg_color_aware_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union ac_mul_queue_cfg_tbl_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_ac_mul_queue_cfg_tbl_get(dev_id, index, ®_val); - *value = reg_val.bf.ac_cfg_color_aware; - return ret; -} - -sw_error_t -hppe_ac_mul_queue_cfg_tbl_ac_cfg_color_aware_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - union ac_mul_queue_cfg_tbl_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_ac_mul_queue_cfg_tbl_get(dev_id, index, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.ac_cfg_color_aware = value; - ret = hppe_ac_mul_queue_cfg_tbl_set(dev_id, index, ®_val); - return ret; -} - -sw_error_t -hppe_ac_mul_queue_cfg_tbl_ac_cfg_yel_resume_offset_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union ac_mul_queue_cfg_tbl_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_ac_mul_queue_cfg_tbl_get(dev_id, index, ®_val); - *value = reg_val.bf.ac_cfg_yel_resume_offset_1 << 4 | \ - reg_val.bf.ac_cfg_yel_resume_offset_0; - return ret; -} - -sw_error_t -hppe_ac_mul_queue_cfg_tbl_ac_cfg_yel_resume_offset_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - union ac_mul_queue_cfg_tbl_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_ac_mul_queue_cfg_tbl_get(dev_id, index, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.ac_cfg_yel_resume_offset_1 = value >> 4; - reg_val.bf.ac_cfg_yel_resume_offset_0 = value & (((a_uint64_t)1<<4)-1); - ret = hppe_ac_mul_queue_cfg_tbl_set(dev_id, index, ®_val); - return ret; -} - -sw_error_t -hppe_ac_mul_queue_cfg_tbl_ac_cfg_pre_alloc_limit_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union ac_mul_queue_cfg_tbl_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_ac_mul_queue_cfg_tbl_get(dev_id, index, ®_val); - *value = reg_val.bf.ac_cfg_pre_alloc_limit; - return ret; -} - -sw_error_t -hppe_ac_mul_queue_cfg_tbl_ac_cfg_pre_alloc_limit_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - union ac_mul_queue_cfg_tbl_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_ac_mul_queue_cfg_tbl_get(dev_id, index, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.ac_cfg_pre_alloc_limit = value; - ret = hppe_ac_mul_queue_cfg_tbl_set(dev_id, index, ®_val); - return ret; -} - -sw_error_t -hppe_ac_mul_queue_cfg_tbl_ac_cfg_force_ac_en_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union ac_mul_queue_cfg_tbl_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_ac_mul_queue_cfg_tbl_get(dev_id, index, ®_val); - *value = reg_val.bf.ac_cfg_force_ac_en; - return ret; -} - -sw_error_t -hppe_ac_mul_queue_cfg_tbl_ac_cfg_force_ac_en_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - union ac_mul_queue_cfg_tbl_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_ac_mul_queue_cfg_tbl_get(dev_id, index, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.ac_cfg_force_ac_en = value; - ret = hppe_ac_mul_queue_cfg_tbl_set(dev_id, index, ®_val); - return ret; -} - -sw_error_t -hppe_ac_mul_queue_cfg_tbl_ac_cfg_shared_ceiling_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union ac_mul_queue_cfg_tbl_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_ac_mul_queue_cfg_tbl_get(dev_id, index, ®_val); - *value = reg_val.bf.ac_cfg_shared_ceiling; - return ret; -} - -sw_error_t -hppe_ac_mul_queue_cfg_tbl_ac_cfg_shared_ceiling_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - union ac_mul_queue_cfg_tbl_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_ac_mul_queue_cfg_tbl_get(dev_id, index, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.ac_cfg_shared_ceiling = value; - ret = hppe_ac_mul_queue_cfg_tbl_set(dev_id, index, ®_val); - return ret; -} - -sw_error_t -hppe_ac_mul_queue_cfg_tbl_ac_cfg_grn_resume_offset_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union ac_mul_queue_cfg_tbl_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_ac_mul_queue_cfg_tbl_get(dev_id, index, ®_val); - *value = reg_val.bf.ac_cfg_grn_resume_offset; - return ret; -} - -sw_error_t -hppe_ac_mul_queue_cfg_tbl_ac_cfg_grn_resume_offset_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - union ac_mul_queue_cfg_tbl_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_ac_mul_queue_cfg_tbl_get(dev_id, index, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.ac_cfg_grn_resume_offset = value; - ret = hppe_ac_mul_queue_cfg_tbl_set(dev_id, index, ®_val); - return ret; -} - -sw_error_t -hppe_ac_mul_queue_cfg_tbl_ac_cfg_gap_grn_yel_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union ac_mul_queue_cfg_tbl_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_ac_mul_queue_cfg_tbl_get(dev_id, index, ®_val); - *value = reg_val.bf.ac_cfg_gap_grn_yel_1 << 5 | \ - reg_val.bf.ac_cfg_gap_grn_yel_0; - return ret; -} - -sw_error_t -hppe_ac_mul_queue_cfg_tbl_ac_cfg_gap_grn_yel_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - union ac_mul_queue_cfg_tbl_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_ac_mul_queue_cfg_tbl_get(dev_id, index, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.ac_cfg_gap_grn_yel_1 = value >> 5; - reg_val.bf.ac_cfg_gap_grn_yel_0 = value & (((a_uint64_t)1<<5)-1); - ret = hppe_ac_mul_queue_cfg_tbl_set(dev_id, index, ®_val); - return ret; -} - -sw_error_t -hppe_ac_mul_queue_cfg_tbl_ac_cfg_gap_grn_red_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union ac_mul_queue_cfg_tbl_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_ac_mul_queue_cfg_tbl_get(dev_id, index, ®_val); - *value = reg_val.bf.ac_cfg_gap_grn_red; - return ret; -} - -sw_error_t -hppe_ac_mul_queue_cfg_tbl_ac_cfg_gap_grn_red_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - union ac_mul_queue_cfg_tbl_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_ac_mul_queue_cfg_tbl_get(dev_id, index, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.ac_cfg_gap_grn_red = value; - ret = hppe_ac_mul_queue_cfg_tbl_set(dev_id, index, ®_val); - return ret; -} - -sw_error_t -hppe_ac_grp_cfg_tbl_ac_grp_grn_resume_offset_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union ac_grp_cfg_tbl_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_ac_grp_cfg_tbl_get(dev_id, index, ®_val); - *value = reg_val.bf.ac_grp_grn_resume_offset; - return ret; -} - -sw_error_t -hppe_ac_grp_cfg_tbl_ac_grp_grn_resume_offset_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - union ac_grp_cfg_tbl_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_ac_grp_cfg_tbl_get(dev_id, index, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.ac_grp_grn_resume_offset = value; - ret = hppe_ac_grp_cfg_tbl_set(dev_id, index, ®_val); - return ret; -} - -sw_error_t -hppe_ac_grp_cfg_tbl_ac_grp_dp_thrd_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union ac_grp_cfg_tbl_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_ac_grp_cfg_tbl_get(dev_id, index, ®_val); - *value = reg_val.bf.ac_grp_dp_thrd_1 << 7 | \ - reg_val.bf.ac_grp_dp_thrd_0; - return ret; -} - -sw_error_t -hppe_ac_grp_cfg_tbl_ac_grp_dp_thrd_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - union ac_grp_cfg_tbl_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_ac_grp_cfg_tbl_get(dev_id, index, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.ac_grp_dp_thrd_1 = value >> 7; - reg_val.bf.ac_grp_dp_thrd_0 = value & (((a_uint64_t)1<<7)-1); - ret = hppe_ac_grp_cfg_tbl_set(dev_id, index, ®_val); - return ret; -} - -sw_error_t -hppe_ac_grp_cfg_tbl_ac_cfg_ac_en_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union ac_grp_cfg_tbl_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_ac_grp_cfg_tbl_get(dev_id, index, ®_val); - *value = reg_val.bf.ac_cfg_ac_en; - return ret; -} - -sw_error_t -hppe_ac_grp_cfg_tbl_ac_cfg_ac_en_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - union ac_grp_cfg_tbl_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_ac_grp_cfg_tbl_get(dev_id, index, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.ac_cfg_ac_en = value; - ret = hppe_ac_grp_cfg_tbl_set(dev_id, index, ®_val); - return ret; -} - -sw_error_t -hppe_ac_grp_cfg_tbl_ac_grp_palloc_limit_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union ac_grp_cfg_tbl_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_ac_grp_cfg_tbl_get(dev_id, index, ®_val); - *value = reg_val.bf.ac_grp_palloc_limit; - return ret; -} - -sw_error_t -hppe_ac_grp_cfg_tbl_ac_grp_palloc_limit_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - union ac_grp_cfg_tbl_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_ac_grp_cfg_tbl_get(dev_id, index, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.ac_grp_palloc_limit = value; - ret = hppe_ac_grp_cfg_tbl_set(dev_id, index, ®_val); - return ret; -} - -sw_error_t -hppe_ac_grp_cfg_tbl_ac_cfg_color_aware_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union ac_grp_cfg_tbl_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_ac_grp_cfg_tbl_get(dev_id, index, ®_val); - *value = reg_val.bf.ac_cfg_color_aware; - return ret; -} - -sw_error_t -hppe_ac_grp_cfg_tbl_ac_cfg_color_aware_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - union ac_grp_cfg_tbl_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_ac_grp_cfg_tbl_get(dev_id, index, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.ac_cfg_color_aware = value; - ret = hppe_ac_grp_cfg_tbl_set(dev_id, index, ®_val); - return ret; -} - -sw_error_t -hppe_ac_grp_cfg_tbl_ac_grp_red_resume_offset_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union ac_grp_cfg_tbl_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_ac_grp_cfg_tbl_get(dev_id, index, ®_val); - *value = reg_val.bf.ac_grp_red_resume_offset; - return ret; -} - -sw_error_t -hppe_ac_grp_cfg_tbl_ac_grp_red_resume_offset_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - union ac_grp_cfg_tbl_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_ac_grp_cfg_tbl_get(dev_id, index, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.ac_grp_red_resume_offset = value; - ret = hppe_ac_grp_cfg_tbl_set(dev_id, index, ®_val); - return ret; -} - -sw_error_t -hppe_ac_grp_cfg_tbl_ac_grp_gap_grn_yel_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union ac_grp_cfg_tbl_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_ac_grp_cfg_tbl_get(dev_id, index, ®_val); - *value = reg_val.bf.ac_grp_gap_grn_yel; - return ret; -} - -sw_error_t -hppe_ac_grp_cfg_tbl_ac_grp_gap_grn_yel_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - union ac_grp_cfg_tbl_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_ac_grp_cfg_tbl_get(dev_id, index, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.ac_grp_gap_grn_yel = value; - ret = hppe_ac_grp_cfg_tbl_set(dev_id, index, ®_val); - return ret; -} - -sw_error_t -hppe_ac_grp_cfg_tbl_ac_cfg_force_ac_en_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union ac_grp_cfg_tbl_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_ac_grp_cfg_tbl_get(dev_id, index, ®_val); - *value = reg_val.bf.ac_cfg_force_ac_en; - return ret; -} - -sw_error_t -hppe_ac_grp_cfg_tbl_ac_cfg_force_ac_en_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - union ac_grp_cfg_tbl_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_ac_grp_cfg_tbl_get(dev_id, index, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.ac_cfg_force_ac_en = value; - ret = hppe_ac_grp_cfg_tbl_set(dev_id, index, ®_val); - return ret; -} - -sw_error_t -hppe_ac_grp_cfg_tbl_ac_grp_yel_resume_offset_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union ac_grp_cfg_tbl_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_ac_grp_cfg_tbl_get(dev_id, index, ®_val); - *value = reg_val.bf.ac_grp_yel_resume_offset_1 << 6 | \ - reg_val.bf.ac_grp_yel_resume_offset_0; - return ret; -} - -sw_error_t -hppe_ac_grp_cfg_tbl_ac_grp_yel_resume_offset_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - union ac_grp_cfg_tbl_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_ac_grp_cfg_tbl_get(dev_id, index, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.ac_grp_yel_resume_offset_1 = value >> 6; - reg_val.bf.ac_grp_yel_resume_offset_0 = value & (((a_uint64_t)1<<6)-1); - ret = hppe_ac_grp_cfg_tbl_set(dev_id, index, ®_val); - return ret; -} - -sw_error_t -hppe_ac_grp_cfg_tbl_ac_grp_gap_grn_red_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union ac_grp_cfg_tbl_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_ac_grp_cfg_tbl_get(dev_id, index, ®_val); - *value = reg_val.bf.ac_grp_gap_grn_red; - return ret; -} - -sw_error_t -hppe_ac_grp_cfg_tbl_ac_grp_gap_grn_red_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - union ac_grp_cfg_tbl_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_ac_grp_cfg_tbl_get(dev_id, index, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.ac_grp_gap_grn_red = value; - ret = hppe_ac_grp_cfg_tbl_set(dev_id, index, ®_val); - return ret; -} - -sw_error_t -hppe_ac_grp_cfg_tbl_ac_grp_limit_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union ac_grp_cfg_tbl_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_ac_grp_cfg_tbl_get(dev_id, index, ®_val); - *value = reg_val.bf.ac_grp_limit; - return ret; -} - -sw_error_t -hppe_ac_grp_cfg_tbl_ac_grp_limit_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - union ac_grp_cfg_tbl_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_ac_grp_cfg_tbl_get(dev_id, index, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.ac_grp_limit = value; - ret = hppe_ac_grp_cfg_tbl_set(dev_id, index, ®_val); - return ret; -} - -sw_error_t -hppe_ac_uni_queue_cnt_tbl_ac_uni_queue_cnt_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union ac_uni_queue_cnt_tbl_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_ac_uni_queue_cnt_tbl_get(dev_id, index, ®_val); - *value = reg_val.bf.ac_uni_queue_cnt; - return ret; -} - -sw_error_t -hppe_ac_uni_queue_cnt_tbl_ac_uni_queue_cnt_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - union ac_uni_queue_cnt_tbl_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_ac_uni_queue_cnt_tbl_get(dev_id, index, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.ac_uni_queue_cnt = value; - ret = hppe_ac_uni_queue_cnt_tbl_set(dev_id, index, ®_val); - return ret; -} - -sw_error_t -hppe_ac_mul_queue_cnt_tbl_ac_mul_queue_cnt_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union ac_mul_queue_cnt_tbl_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_ac_mul_queue_cnt_tbl_get(dev_id, index, ®_val); - *value = reg_val.bf.ac_mul_queue_cnt; - return ret; -} - -sw_error_t -hppe_ac_mul_queue_cnt_tbl_ac_mul_queue_cnt_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - union ac_mul_queue_cnt_tbl_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_ac_mul_queue_cnt_tbl_get(dev_id, index, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.ac_mul_queue_cnt = value; - ret = hppe_ac_mul_queue_cnt_tbl_set(dev_id, index, ®_val); - return ret; -} - -sw_error_t -hppe_ac_grp_cnt_tbl_ac_grp_alloc_used_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union ac_grp_cnt_tbl_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_ac_grp_cnt_tbl_get(dev_id, index, ®_val); - *value = reg_val.bf.ac_grp_alloc_used; - return ret; -} - -sw_error_t -hppe_ac_grp_cnt_tbl_ac_grp_alloc_used_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - union ac_grp_cnt_tbl_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_ac_grp_cnt_tbl_get(dev_id, index, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.ac_grp_alloc_used = value; - ret = hppe_ac_grp_cnt_tbl_set(dev_id, index, ®_val); - return ret; -} - -sw_error_t -hppe_ac_grp_cnt_tbl_ac_grp_cnt_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union ac_grp_cnt_tbl_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_ac_grp_cnt_tbl_get(dev_id, index, ®_val); - *value = reg_val.bf.ac_grp_cnt; - return ret; -} - -sw_error_t -hppe_ac_grp_cnt_tbl_ac_grp_cnt_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - union ac_grp_cnt_tbl_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_ac_grp_cnt_tbl_get(dev_id, index, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.ac_grp_cnt = value; - ret = hppe_ac_grp_cnt_tbl_set(dev_id, index, ®_val); - return ret; -} - -sw_error_t -hppe_ac_uni_queue_drop_state_tbl_red_resume_thrd_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union ac_uni_queue_drop_state_tbl_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_ac_uni_queue_drop_state_tbl_get(dev_id, index, ®_val); - *value = reg_val.bf.red_resume_thrd; - return ret; -} - -sw_error_t -hppe_ac_uni_queue_drop_state_tbl_red_resume_thrd_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - union ac_uni_queue_drop_state_tbl_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_ac_uni_queue_drop_state_tbl_get(dev_id, index, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.red_resume_thrd = value; - ret = hppe_ac_uni_queue_drop_state_tbl_set(dev_id, index, ®_val); - return ret; -} - -sw_error_t -hppe_ac_uni_queue_drop_state_tbl_red_drop_state_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union ac_uni_queue_drop_state_tbl_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_ac_uni_queue_drop_state_tbl_get(dev_id, index, ®_val); - *value = reg_val.bf.red_drop_state; - return ret; -} - -sw_error_t -hppe_ac_uni_queue_drop_state_tbl_red_drop_state_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - union ac_uni_queue_drop_state_tbl_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_ac_uni_queue_drop_state_tbl_get(dev_id, index, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.red_drop_state = value; - ret = hppe_ac_uni_queue_drop_state_tbl_set(dev_id, index, ®_val); - return ret; -} - -sw_error_t -hppe_ac_uni_queue_drop_state_tbl_yel_resume_thrd_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union ac_uni_queue_drop_state_tbl_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_ac_uni_queue_drop_state_tbl_get(dev_id, index, ®_val); - *value = reg_val.bf.yel_resume_thrd; - return ret; -} - -sw_error_t -hppe_ac_uni_queue_drop_state_tbl_yel_resume_thrd_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - union ac_uni_queue_drop_state_tbl_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_ac_uni_queue_drop_state_tbl_get(dev_id, index, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.yel_resume_thrd = value; - ret = hppe_ac_uni_queue_drop_state_tbl_set(dev_id, index, ®_val); - return ret; -} - -sw_error_t -hppe_ac_uni_queue_drop_state_tbl_grn_drop_state_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union ac_uni_queue_drop_state_tbl_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_ac_uni_queue_drop_state_tbl_get(dev_id, index, ®_val); - *value = reg_val.bf.grn_drop_state; - return ret; -} - -sw_error_t -hppe_ac_uni_queue_drop_state_tbl_grn_drop_state_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - union ac_uni_queue_drop_state_tbl_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_ac_uni_queue_drop_state_tbl_get(dev_id, index, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.grn_drop_state = value; - ret = hppe_ac_uni_queue_drop_state_tbl_set(dev_id, index, ®_val); - return ret; -} - -sw_error_t -hppe_ac_uni_queue_drop_state_tbl_yel_drop_state_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union ac_uni_queue_drop_state_tbl_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_ac_uni_queue_drop_state_tbl_get(dev_id, index, ®_val); - *value = reg_val.bf.yel_drop_state; - return ret; -} - -sw_error_t -hppe_ac_uni_queue_drop_state_tbl_yel_drop_state_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - union ac_uni_queue_drop_state_tbl_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_ac_uni_queue_drop_state_tbl_get(dev_id, index, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.yel_drop_state = value; - ret = hppe_ac_uni_queue_drop_state_tbl_set(dev_id, index, ®_val); - return ret; -} - -sw_error_t -hppe_ac_uni_queue_drop_state_tbl_grn_resume_thrd_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union ac_uni_queue_drop_state_tbl_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_ac_uni_queue_drop_state_tbl_get(dev_id, index, ®_val); - *value = reg_val.bf.grn_resume_thrd_1 << 10 | \ - reg_val.bf.grn_resume_thrd_0; - return ret; -} - -sw_error_t -hppe_ac_uni_queue_drop_state_tbl_grn_resume_thrd_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - union ac_uni_queue_drop_state_tbl_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_ac_uni_queue_drop_state_tbl_get(dev_id, index, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.grn_resume_thrd_1 = value >> 10; - reg_val.bf.grn_resume_thrd_0 = value & (((a_uint64_t)1<<10)-1); - ret = hppe_ac_uni_queue_drop_state_tbl_set(dev_id, index, ®_val); - return ret; -} - -sw_error_t -hppe_ac_mul_queue_drop_state_tbl_red_resume_thrd_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union ac_mul_queue_drop_state_tbl_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_ac_mul_queue_drop_state_tbl_get(dev_id, index, ®_val); - *value = reg_val.bf.red_resume_thrd; - return ret; -} - -sw_error_t -hppe_ac_mul_queue_drop_state_tbl_red_resume_thrd_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - union ac_mul_queue_drop_state_tbl_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_ac_mul_queue_drop_state_tbl_get(dev_id, index, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.red_resume_thrd = value; - ret = hppe_ac_mul_queue_drop_state_tbl_set(dev_id, index, ®_val); - return ret; -} - -sw_error_t -hppe_ac_mul_queue_drop_state_tbl_red_drop_state_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union ac_mul_queue_drop_state_tbl_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_ac_mul_queue_drop_state_tbl_get(dev_id, index, ®_val); - *value = reg_val.bf.red_drop_state; - return ret; -} - -sw_error_t -hppe_ac_mul_queue_drop_state_tbl_red_drop_state_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - union ac_mul_queue_drop_state_tbl_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_ac_mul_queue_drop_state_tbl_get(dev_id, index, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.red_drop_state = value; - ret = hppe_ac_mul_queue_drop_state_tbl_set(dev_id, index, ®_val); - return ret; -} - -sw_error_t -hppe_ac_mul_queue_drop_state_tbl_yel_resume_thrd_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union ac_mul_queue_drop_state_tbl_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_ac_mul_queue_drop_state_tbl_get(dev_id, index, ®_val); - *value = reg_val.bf.yel_resume_thrd; - return ret; -} - -sw_error_t -hppe_ac_mul_queue_drop_state_tbl_yel_resume_thrd_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - union ac_mul_queue_drop_state_tbl_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_ac_mul_queue_drop_state_tbl_get(dev_id, index, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.yel_resume_thrd = value; - ret = hppe_ac_mul_queue_drop_state_tbl_set(dev_id, index, ®_val); - return ret; -} - -sw_error_t -hppe_ac_mul_queue_drop_state_tbl_grn_drop_state_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union ac_mul_queue_drop_state_tbl_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_ac_mul_queue_drop_state_tbl_get(dev_id, index, ®_val); - *value = reg_val.bf.grn_drop_state; - return ret; -} - -sw_error_t -hppe_ac_mul_queue_drop_state_tbl_grn_drop_state_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - union ac_mul_queue_drop_state_tbl_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_ac_mul_queue_drop_state_tbl_get(dev_id, index, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.grn_drop_state = value; - ret = hppe_ac_mul_queue_drop_state_tbl_set(dev_id, index, ®_val); - return ret; -} - -sw_error_t -hppe_ac_mul_queue_drop_state_tbl_yel_drop_state_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union ac_mul_queue_drop_state_tbl_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_ac_mul_queue_drop_state_tbl_get(dev_id, index, ®_val); - *value = reg_val.bf.yel_drop_state; - return ret; -} - -sw_error_t -hppe_ac_mul_queue_drop_state_tbl_yel_drop_state_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - union ac_mul_queue_drop_state_tbl_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_ac_mul_queue_drop_state_tbl_get(dev_id, index, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.yel_drop_state = value; - ret = hppe_ac_mul_queue_drop_state_tbl_set(dev_id, index, ®_val); - return ret; -} - -sw_error_t -hppe_ac_mul_queue_drop_state_tbl_grn_resume_thrd_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union ac_mul_queue_drop_state_tbl_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_ac_mul_queue_drop_state_tbl_get(dev_id, index, ®_val); - *value = reg_val.bf.grn_resume_thrd_1 << 10 | \ - reg_val.bf.grn_resume_thrd_0; - return ret; -} - -sw_error_t -hppe_ac_mul_queue_drop_state_tbl_grn_resume_thrd_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - union ac_mul_queue_drop_state_tbl_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_ac_mul_queue_drop_state_tbl_get(dev_id, index, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.grn_resume_thrd_1 = value >> 10; - reg_val.bf.grn_resume_thrd_0 = value & (((a_uint64_t)1<<10)-1); - ret = hppe_ac_mul_queue_drop_state_tbl_set(dev_id, index, ®_val); - return ret; -} - -sw_error_t -hppe_ac_grp_drop_state_tbl_red_resume_thrd_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union ac_grp_drop_state_tbl_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_ac_grp_drop_state_tbl_get(dev_id, index, ®_val); - *value = reg_val.bf.red_resume_thrd; - return ret; -} - -sw_error_t -hppe_ac_grp_drop_state_tbl_red_resume_thrd_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - union ac_grp_drop_state_tbl_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_ac_grp_drop_state_tbl_get(dev_id, index, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.red_resume_thrd = value; - ret = hppe_ac_grp_drop_state_tbl_set(dev_id, index, ®_val); - return ret; -} - -sw_error_t -hppe_ac_grp_drop_state_tbl_red_drop_state_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union ac_grp_drop_state_tbl_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_ac_grp_drop_state_tbl_get(dev_id, index, ®_val); - *value = reg_val.bf.red_drop_state; - return ret; -} - -sw_error_t -hppe_ac_grp_drop_state_tbl_red_drop_state_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - union ac_grp_drop_state_tbl_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_ac_grp_drop_state_tbl_get(dev_id, index, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.red_drop_state = value; - ret = hppe_ac_grp_drop_state_tbl_set(dev_id, index, ®_val); - return ret; -} - -sw_error_t -hppe_ac_grp_drop_state_tbl_yel_resume_thrd_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union ac_grp_drop_state_tbl_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_ac_grp_drop_state_tbl_get(dev_id, index, ®_val); - *value = reg_val.bf.yel_resume_thrd; - return ret; -} - -sw_error_t -hppe_ac_grp_drop_state_tbl_yel_resume_thrd_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - union ac_grp_drop_state_tbl_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_ac_grp_drop_state_tbl_get(dev_id, index, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.yel_resume_thrd = value; - ret = hppe_ac_grp_drop_state_tbl_set(dev_id, index, ®_val); - return ret; -} - -sw_error_t -hppe_ac_grp_drop_state_tbl_grn_drop_state_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union ac_grp_drop_state_tbl_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_ac_grp_drop_state_tbl_get(dev_id, index, ®_val); - *value = reg_val.bf.grn_drop_state; - return ret; -} - -sw_error_t -hppe_ac_grp_drop_state_tbl_grn_drop_state_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - union ac_grp_drop_state_tbl_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_ac_grp_drop_state_tbl_get(dev_id, index, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.grn_drop_state = value; - ret = hppe_ac_grp_drop_state_tbl_set(dev_id, index, ®_val); - return ret; -} - -sw_error_t -hppe_ac_grp_drop_state_tbl_yel_drop_state_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union ac_grp_drop_state_tbl_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_ac_grp_drop_state_tbl_get(dev_id, index, ®_val); - *value = reg_val.bf.yel_drop_state; - return ret; -} - -sw_error_t -hppe_ac_grp_drop_state_tbl_yel_drop_state_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - union ac_grp_drop_state_tbl_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_ac_grp_drop_state_tbl_get(dev_id, index, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.yel_drop_state = value; - ret = hppe_ac_grp_drop_state_tbl_set(dev_id, index, ®_val); - return ret; -} - -sw_error_t -hppe_ac_grp_drop_state_tbl_grn_resume_thrd_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union ac_grp_drop_state_tbl_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_ac_grp_drop_state_tbl_get(dev_id, index, ®_val); - *value = reg_val.bf.grn_resume_thrd_1 << 10 | \ - reg_val.bf.grn_resume_thrd_0; - return ret; -} - -sw_error_t -hppe_ac_grp_drop_state_tbl_grn_resume_thrd_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - union ac_grp_drop_state_tbl_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_ac_grp_drop_state_tbl_get(dev_id, index, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.grn_resume_thrd_1 = value >> 10; - reg_val.bf.grn_resume_thrd_0 = value & (((a_uint64_t)1<<10)-1); - ret = hppe_ac_grp_drop_state_tbl_set(dev_id, index, ®_val); - return ret; -} - -sw_error_t -hppe_oq_enq_opr_tbl_enq_disable_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union oq_enq_opr_tbl_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_oq_enq_opr_tbl_get(dev_id, index, ®_val); - *value = reg_val.bf.enq_disable; - return ret; -} - -sw_error_t -hppe_oq_enq_opr_tbl_enq_disable_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - union oq_enq_opr_tbl_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_oq_enq_opr_tbl_get(dev_id, index, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.enq_disable = value; - ret = hppe_oq_enq_opr_tbl_set(dev_id, index, ®_val); - return ret; -} - -sw_error_t -hppe_oq_deq_opr_tbl_deq_drop_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union oq_deq_opr_tbl_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_oq_deq_opr_tbl_get(dev_id, index, ®_val); - *value = reg_val.bf.deq_drop; - return ret; -} - -sw_error_t -hppe_oq_deq_opr_tbl_deq_drop_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - union oq_deq_opr_tbl_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_oq_deq_opr_tbl_get(dev_id, index, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.deq_drop = value; - ret = hppe_oq_deq_opr_tbl_set(dev_id, index, ®_val); - return ret; -} - -sw_error_t -hppe_oq_head_uni_tbl_head_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union oq_head_uni_tbl_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_oq_head_uni_tbl_get(dev_id, index, ®_val); - *value = reg_val.bf.head; - return ret; -} - -sw_error_t -hppe_oq_head_uni_tbl_head_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - union oq_head_uni_tbl_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_oq_head_uni_tbl_get(dev_id, index, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.head = value; - ret = hppe_oq_head_uni_tbl_set(dev_id, index, ®_val); - return ret; -} - -sw_error_t -hppe_oq_head_uni_tbl_tail_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union oq_head_uni_tbl_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_oq_head_uni_tbl_get(dev_id, index, ®_val); - *value = reg_val.bf.tail; - return ret; -} - -sw_error_t -hppe_oq_head_uni_tbl_tail_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - union oq_head_uni_tbl_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_oq_head_uni_tbl_get(dev_id, index, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.tail = value; - ret = hppe_oq_head_uni_tbl_set(dev_id, index, ®_val); - return ret; -} - -sw_error_t -hppe_oq_head_uni_tbl_empty_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union oq_head_uni_tbl_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_oq_head_uni_tbl_get(dev_id, index, ®_val); - *value = reg_val.bf.empty; - return ret; -} - -sw_error_t -hppe_oq_head_uni_tbl_empty_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - union oq_head_uni_tbl_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_oq_head_uni_tbl_get(dev_id, index, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.empty = value; - ret = hppe_oq_head_uni_tbl_set(dev_id, index, ®_val); - return ret; -} - -sw_error_t -hppe_oq_head_mul_tbl_head_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union oq_head_mul_tbl_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_oq_head_mul_tbl_get(dev_id, index, ®_val); - *value = reg_val.bf.head; - return ret; -} - -sw_error_t -hppe_oq_head_mul_tbl_head_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - union oq_head_mul_tbl_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_oq_head_mul_tbl_get(dev_id, index, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.head = value; - ret = hppe_oq_head_mul_tbl_set(dev_id, index, ®_val); - return ret; -} - -sw_error_t -hppe_oq_head_mul_tbl_tail_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union oq_head_mul_tbl_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_oq_head_mul_tbl_get(dev_id, index, ®_val); - *value = reg_val.bf.tail; - return ret; -} - -sw_error_t -hppe_oq_head_mul_tbl_tail_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - union oq_head_mul_tbl_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_oq_head_mul_tbl_get(dev_id, index, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.tail = value; - ret = hppe_oq_head_mul_tbl_set(dev_id, index, ®_val); - return ret; -} - -sw_error_t -hppe_oq_head_mul_tbl_ingress_mirr_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union oq_head_mul_tbl_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_oq_head_mul_tbl_get(dev_id, index, ®_val); - *value = reg_val.bf.ingress_mirr; - return ret; -} - -sw_error_t -hppe_oq_head_mul_tbl_ingress_mirr_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - union oq_head_mul_tbl_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_oq_head_mul_tbl_get(dev_id, index, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.ingress_mirr = value; - ret = hppe_oq_head_mul_tbl_set(dev_id, index, ®_val); - return ret; -} - -sw_error_t -hppe_oq_head_mul_tbl_empty_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union oq_head_mul_tbl_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_oq_head_mul_tbl_get(dev_id, index, ®_val); - *value = reg_val.bf.empty; - return ret; -} - -sw_error_t -hppe_oq_head_mul_tbl_empty_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - union oq_head_mul_tbl_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_oq_head_mul_tbl_get(dev_id, index, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.empty = value; - ret = hppe_oq_head_mul_tbl_set(dev_id, index, ®_val); - return ret; -} - -sw_error_t -hppe_oq_head_mul_tbl_egress_mirr_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union oq_head_mul_tbl_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_oq_head_mul_tbl_get(dev_id, index, ®_val); - *value = reg_val.bf.egress_mirr; - return ret; -} - -sw_error_t -hppe_oq_head_mul_tbl_egress_mirr_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - union oq_head_mul_tbl_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_oq_head_mul_tbl_get(dev_id, index, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.egress_mirr = value; - ret = hppe_oq_head_mul_tbl_set(dev_id, index, ®_val); - return ret; -} - -sw_error_t -hppe_oq_head_mul_tbl_normal_fwd_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union oq_head_mul_tbl_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_oq_head_mul_tbl_get(dev_id, index, ®_val); - *value = reg_val.bf.normal_fwd; - return ret; -} - -sw_error_t -hppe_oq_head_mul_tbl_normal_fwd_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - union oq_head_mul_tbl_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_oq_head_mul_tbl_get(dev_id, index, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.normal_fwd = value; - ret = hppe_oq_head_mul_tbl_set(dev_id, index, ®_val); - return ret; -} - -sw_error_t -hppe_oq_ll_uni_tbl_next_pointer_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union oq_ll_uni_tbl_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_oq_ll_uni_tbl_get(dev_id, index, ®_val); - *value = reg_val.bf.next_pointer; - return ret; -} - -sw_error_t -hppe_oq_ll_uni_tbl_next_pointer_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - union oq_ll_uni_tbl_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_oq_ll_uni_tbl_get(dev_id, index, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.next_pointer = value; - ret = hppe_oq_ll_uni_tbl_set(dev_id, index, ®_val); - return ret; -} - -sw_error_t -hppe_oq_ll_mul_p0_tbl_next_pointer_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union oq_ll_mul_p0_tbl_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_oq_ll_mul_p0_tbl_get(dev_id, index, ®_val); - *value = reg_val.bf.next_pointer; - return ret; -} - -sw_error_t -hppe_oq_ll_mul_p0_tbl_next_pointer_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - union oq_ll_mul_p0_tbl_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_oq_ll_mul_p0_tbl_get(dev_id, index, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.next_pointer = value; - ret = hppe_oq_ll_mul_p0_tbl_set(dev_id, index, ®_val); - return ret; -} - -sw_error_t -hppe_oq_ll_mul_p0_tbl_ingress_mirr_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union oq_ll_mul_p0_tbl_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_oq_ll_mul_p0_tbl_get(dev_id, index, ®_val); - *value = reg_val.bf.ingress_mirr; - return ret; -} - -sw_error_t -hppe_oq_ll_mul_p0_tbl_ingress_mirr_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - union oq_ll_mul_p0_tbl_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_oq_ll_mul_p0_tbl_get(dev_id, index, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.ingress_mirr = value; - ret = hppe_oq_ll_mul_p0_tbl_set(dev_id, index, ®_val); - return ret; -} - -sw_error_t -hppe_oq_ll_mul_p0_tbl_egress_mirr_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union oq_ll_mul_p0_tbl_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_oq_ll_mul_p0_tbl_get(dev_id, index, ®_val); - *value = reg_val.bf.egress_mirr; - return ret; -} - -sw_error_t -hppe_oq_ll_mul_p0_tbl_egress_mirr_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - union oq_ll_mul_p0_tbl_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_oq_ll_mul_p0_tbl_get(dev_id, index, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.egress_mirr = value; - ret = hppe_oq_ll_mul_p0_tbl_set(dev_id, index, ®_val); - return ret; -} - -sw_error_t -hppe_oq_ll_mul_p0_tbl_normal_fwd_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union oq_ll_mul_p0_tbl_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_oq_ll_mul_p0_tbl_get(dev_id, index, ®_val); - *value = reg_val.bf.normal_fwd; - return ret; -} - -sw_error_t -hppe_oq_ll_mul_p0_tbl_normal_fwd_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - union oq_ll_mul_p0_tbl_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_oq_ll_mul_p0_tbl_get(dev_id, index, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.normal_fwd = value; - ret = hppe_oq_ll_mul_p0_tbl_set(dev_id, index, ®_val); - return ret; -} - -sw_error_t -hppe_oq_ll_mul_p1_tbl_next_pointer_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union oq_ll_mul_p1_tbl_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_oq_ll_mul_p1_tbl_get(dev_id, index, ®_val); - *value = reg_val.bf.next_pointer; - return ret; -} - -sw_error_t -hppe_oq_ll_mul_p1_tbl_next_pointer_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - union oq_ll_mul_p1_tbl_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_oq_ll_mul_p1_tbl_get(dev_id, index, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.next_pointer = value; - ret = hppe_oq_ll_mul_p1_tbl_set(dev_id, index, ®_val); - return ret; -} - -sw_error_t -hppe_oq_ll_mul_p1_tbl_ingress_mirr_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union oq_ll_mul_p1_tbl_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_oq_ll_mul_p1_tbl_get(dev_id, index, ®_val); - *value = reg_val.bf.ingress_mirr; - return ret; -} - -sw_error_t -hppe_oq_ll_mul_p1_tbl_ingress_mirr_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - union oq_ll_mul_p1_tbl_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_oq_ll_mul_p1_tbl_get(dev_id, index, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.ingress_mirr = value; - ret = hppe_oq_ll_mul_p1_tbl_set(dev_id, index, ®_val); - return ret; -} - -sw_error_t -hppe_oq_ll_mul_p1_tbl_egress_mirr_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union oq_ll_mul_p1_tbl_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_oq_ll_mul_p1_tbl_get(dev_id, index, ®_val); - *value = reg_val.bf.egress_mirr; - return ret; -} - -sw_error_t -hppe_oq_ll_mul_p1_tbl_egress_mirr_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - union oq_ll_mul_p1_tbl_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_oq_ll_mul_p1_tbl_get(dev_id, index, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.egress_mirr = value; - ret = hppe_oq_ll_mul_p1_tbl_set(dev_id, index, ®_val); - return ret; -} - -sw_error_t -hppe_oq_ll_mul_p1_tbl_normal_fwd_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union oq_ll_mul_p1_tbl_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_oq_ll_mul_p1_tbl_get(dev_id, index, ®_val); - *value = reg_val.bf.normal_fwd; - return ret; -} - -sw_error_t -hppe_oq_ll_mul_p1_tbl_normal_fwd_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - union oq_ll_mul_p1_tbl_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_oq_ll_mul_p1_tbl_get(dev_id, index, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.normal_fwd = value; - ret = hppe_oq_ll_mul_p1_tbl_set(dev_id, index, ®_val); - return ret; -} - -sw_error_t -hppe_oq_ll_mul_p2_tbl_next_pointer_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union oq_ll_mul_p2_tbl_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_oq_ll_mul_p2_tbl_get(dev_id, index, ®_val); - *value = reg_val.bf.next_pointer; - return ret; -} - -sw_error_t -hppe_oq_ll_mul_p2_tbl_next_pointer_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - union oq_ll_mul_p2_tbl_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_oq_ll_mul_p2_tbl_get(dev_id, index, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.next_pointer = value; - ret = hppe_oq_ll_mul_p2_tbl_set(dev_id, index, ®_val); - return ret; -} - -sw_error_t -hppe_oq_ll_mul_p2_tbl_ingress_mirr_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union oq_ll_mul_p2_tbl_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_oq_ll_mul_p2_tbl_get(dev_id, index, ®_val); - *value = reg_val.bf.ingress_mirr; - return ret; -} - -sw_error_t -hppe_oq_ll_mul_p2_tbl_ingress_mirr_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - union oq_ll_mul_p2_tbl_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_oq_ll_mul_p2_tbl_get(dev_id, index, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.ingress_mirr = value; - ret = hppe_oq_ll_mul_p2_tbl_set(dev_id, index, ®_val); - return ret; -} - -sw_error_t -hppe_oq_ll_mul_p2_tbl_egress_mirr_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union oq_ll_mul_p2_tbl_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_oq_ll_mul_p2_tbl_get(dev_id, index, ®_val); - *value = reg_val.bf.egress_mirr; - return ret; -} - -sw_error_t -hppe_oq_ll_mul_p2_tbl_egress_mirr_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - union oq_ll_mul_p2_tbl_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_oq_ll_mul_p2_tbl_get(dev_id, index, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.egress_mirr = value; - ret = hppe_oq_ll_mul_p2_tbl_set(dev_id, index, ®_val); - return ret; -} - -sw_error_t -hppe_oq_ll_mul_p2_tbl_normal_fwd_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union oq_ll_mul_p2_tbl_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_oq_ll_mul_p2_tbl_get(dev_id, index, ®_val); - *value = reg_val.bf.normal_fwd; - return ret; -} - -sw_error_t -hppe_oq_ll_mul_p2_tbl_normal_fwd_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - union oq_ll_mul_p2_tbl_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_oq_ll_mul_p2_tbl_get(dev_id, index, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.normal_fwd = value; - ret = hppe_oq_ll_mul_p2_tbl_set(dev_id, index, ®_val); - return ret; -} - -sw_error_t -hppe_oq_ll_mul_p3_tbl_next_pointer_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union oq_ll_mul_p3_tbl_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_oq_ll_mul_p3_tbl_get(dev_id, index, ®_val); - *value = reg_val.bf.next_pointer; - return ret; -} - -sw_error_t -hppe_oq_ll_mul_p3_tbl_next_pointer_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - union oq_ll_mul_p3_tbl_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_oq_ll_mul_p3_tbl_get(dev_id, index, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.next_pointer = value; - ret = hppe_oq_ll_mul_p3_tbl_set(dev_id, index, ®_val); - return ret; -} - -sw_error_t -hppe_oq_ll_mul_p3_tbl_ingress_mirr_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union oq_ll_mul_p3_tbl_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_oq_ll_mul_p3_tbl_get(dev_id, index, ®_val); - *value = reg_val.bf.ingress_mirr; - return ret; -} - -sw_error_t -hppe_oq_ll_mul_p3_tbl_ingress_mirr_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - union oq_ll_mul_p3_tbl_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_oq_ll_mul_p3_tbl_get(dev_id, index, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.ingress_mirr = value; - ret = hppe_oq_ll_mul_p3_tbl_set(dev_id, index, ®_val); - return ret; -} - -sw_error_t -hppe_oq_ll_mul_p3_tbl_egress_mirr_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union oq_ll_mul_p3_tbl_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_oq_ll_mul_p3_tbl_get(dev_id, index, ®_val); - *value = reg_val.bf.egress_mirr; - return ret; -} - -sw_error_t -hppe_oq_ll_mul_p3_tbl_egress_mirr_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - union oq_ll_mul_p3_tbl_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_oq_ll_mul_p3_tbl_get(dev_id, index, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.egress_mirr = value; - ret = hppe_oq_ll_mul_p3_tbl_set(dev_id, index, ®_val); - return ret; -} - -sw_error_t -hppe_oq_ll_mul_p3_tbl_normal_fwd_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union oq_ll_mul_p3_tbl_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_oq_ll_mul_p3_tbl_get(dev_id, index, ®_val); - *value = reg_val.bf.normal_fwd; - return ret; -} - -sw_error_t -hppe_oq_ll_mul_p3_tbl_normal_fwd_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - union oq_ll_mul_p3_tbl_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_oq_ll_mul_p3_tbl_get(dev_id, index, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.normal_fwd = value; - ret = hppe_oq_ll_mul_p3_tbl_set(dev_id, index, ®_val); - return ret; -} - -sw_error_t -hppe_oq_ll_mul_p4_tbl_next_pointer_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union oq_ll_mul_p4_tbl_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_oq_ll_mul_p4_tbl_get(dev_id, index, ®_val); - *value = reg_val.bf.next_pointer; - return ret; -} - -sw_error_t -hppe_oq_ll_mul_p4_tbl_next_pointer_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - union oq_ll_mul_p4_tbl_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_oq_ll_mul_p4_tbl_get(dev_id, index, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.next_pointer = value; - ret = hppe_oq_ll_mul_p4_tbl_set(dev_id, index, ®_val); - return ret; -} - -sw_error_t -hppe_oq_ll_mul_p4_tbl_ingress_mirr_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union oq_ll_mul_p4_tbl_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_oq_ll_mul_p4_tbl_get(dev_id, index, ®_val); - *value = reg_val.bf.ingress_mirr; - return ret; -} - -sw_error_t -hppe_oq_ll_mul_p4_tbl_ingress_mirr_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - union oq_ll_mul_p4_tbl_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_oq_ll_mul_p4_tbl_get(dev_id, index, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.ingress_mirr = value; - ret = hppe_oq_ll_mul_p4_tbl_set(dev_id, index, ®_val); - return ret; -} - -sw_error_t -hppe_oq_ll_mul_p4_tbl_egress_mirr_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union oq_ll_mul_p4_tbl_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_oq_ll_mul_p4_tbl_get(dev_id, index, ®_val); - *value = reg_val.bf.egress_mirr; - return ret; -} - -sw_error_t -hppe_oq_ll_mul_p4_tbl_egress_mirr_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - union oq_ll_mul_p4_tbl_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_oq_ll_mul_p4_tbl_get(dev_id, index, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.egress_mirr = value; - ret = hppe_oq_ll_mul_p4_tbl_set(dev_id, index, ®_val); - return ret; -} - -sw_error_t -hppe_oq_ll_mul_p4_tbl_normal_fwd_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union oq_ll_mul_p4_tbl_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_oq_ll_mul_p4_tbl_get(dev_id, index, ®_val); - *value = reg_val.bf.normal_fwd; - return ret; -} - -sw_error_t -hppe_oq_ll_mul_p4_tbl_normal_fwd_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - union oq_ll_mul_p4_tbl_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_oq_ll_mul_p4_tbl_get(dev_id, index, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.normal_fwd = value; - ret = hppe_oq_ll_mul_p4_tbl_set(dev_id, index, ®_val); - return ret; -} - -sw_error_t -hppe_oq_ll_mul_p5_tbl_next_pointer_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union oq_ll_mul_p5_tbl_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_oq_ll_mul_p5_tbl_get(dev_id, index, ®_val); - *value = reg_val.bf.next_pointer; - return ret; -} - -sw_error_t -hppe_oq_ll_mul_p5_tbl_next_pointer_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - union oq_ll_mul_p5_tbl_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_oq_ll_mul_p5_tbl_get(dev_id, index, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.next_pointer = value; - ret = hppe_oq_ll_mul_p5_tbl_set(dev_id, index, ®_val); - return ret; -} - -sw_error_t -hppe_oq_ll_mul_p5_tbl_ingress_mirr_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union oq_ll_mul_p5_tbl_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_oq_ll_mul_p5_tbl_get(dev_id, index, ®_val); - *value = reg_val.bf.ingress_mirr; - return ret; -} - -sw_error_t -hppe_oq_ll_mul_p5_tbl_ingress_mirr_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - union oq_ll_mul_p5_tbl_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_oq_ll_mul_p5_tbl_get(dev_id, index, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.ingress_mirr = value; - ret = hppe_oq_ll_mul_p5_tbl_set(dev_id, index, ®_val); - return ret; -} - -sw_error_t -hppe_oq_ll_mul_p5_tbl_egress_mirr_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union oq_ll_mul_p5_tbl_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_oq_ll_mul_p5_tbl_get(dev_id, index, ®_val); - *value = reg_val.bf.egress_mirr; - return ret; -} - -sw_error_t -hppe_oq_ll_mul_p5_tbl_egress_mirr_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - union oq_ll_mul_p5_tbl_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_oq_ll_mul_p5_tbl_get(dev_id, index, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.egress_mirr = value; - ret = hppe_oq_ll_mul_p5_tbl_set(dev_id, index, ®_val); - return ret; -} - -sw_error_t -hppe_oq_ll_mul_p5_tbl_normal_fwd_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union oq_ll_mul_p5_tbl_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_oq_ll_mul_p5_tbl_get(dev_id, index, ®_val); - *value = reg_val.bf.normal_fwd; - return ret; -} - -sw_error_t -hppe_oq_ll_mul_p5_tbl_normal_fwd_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - union oq_ll_mul_p5_tbl_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_oq_ll_mul_p5_tbl_get(dev_id, index, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.normal_fwd = value; - ret = hppe_oq_ll_mul_p5_tbl_set(dev_id, index, ®_val); - return ret; -} - -sw_error_t -hppe_oq_ll_mul_p6_tbl_next_pointer_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union oq_ll_mul_p6_tbl_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_oq_ll_mul_p6_tbl_get(dev_id, index, ®_val); - *value = reg_val.bf.next_pointer; - return ret; -} - -sw_error_t -hppe_oq_ll_mul_p6_tbl_next_pointer_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - union oq_ll_mul_p6_tbl_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_oq_ll_mul_p6_tbl_get(dev_id, index, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.next_pointer = value; - ret = hppe_oq_ll_mul_p6_tbl_set(dev_id, index, ®_val); - return ret; -} - -sw_error_t -hppe_oq_ll_mul_p6_tbl_ingress_mirr_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union oq_ll_mul_p6_tbl_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_oq_ll_mul_p6_tbl_get(dev_id, index, ®_val); - *value = reg_val.bf.ingress_mirr; - return ret; -} - -sw_error_t -hppe_oq_ll_mul_p6_tbl_ingress_mirr_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - union oq_ll_mul_p6_tbl_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_oq_ll_mul_p6_tbl_get(dev_id, index, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.ingress_mirr = value; - ret = hppe_oq_ll_mul_p6_tbl_set(dev_id, index, ®_val); - return ret; -} - -sw_error_t -hppe_oq_ll_mul_p6_tbl_egress_mirr_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union oq_ll_mul_p6_tbl_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_oq_ll_mul_p6_tbl_get(dev_id, index, ®_val); - *value = reg_val.bf.egress_mirr; - return ret; -} - -sw_error_t -hppe_oq_ll_mul_p6_tbl_egress_mirr_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - union oq_ll_mul_p6_tbl_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_oq_ll_mul_p6_tbl_get(dev_id, index, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.egress_mirr = value; - ret = hppe_oq_ll_mul_p6_tbl_set(dev_id, index, ®_val); - return ret; -} - -sw_error_t -hppe_oq_ll_mul_p6_tbl_normal_fwd_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union oq_ll_mul_p6_tbl_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_oq_ll_mul_p6_tbl_get(dev_id, index, ®_val); - *value = reg_val.bf.normal_fwd; - return ret; -} - -sw_error_t -hppe_oq_ll_mul_p6_tbl_normal_fwd_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - union oq_ll_mul_p6_tbl_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_oq_ll_mul_p6_tbl_get(dev_id, index, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.normal_fwd = value; - ret = hppe_oq_ll_mul_p6_tbl_set(dev_id, index, ®_val); - return ret; -} - -sw_error_t -hppe_oq_ll_mul_p7_tbl_next_pointer_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union oq_ll_mul_p7_tbl_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_oq_ll_mul_p7_tbl_get(dev_id, index, ®_val); - *value = reg_val.bf.next_pointer; - return ret; -} - -sw_error_t -hppe_oq_ll_mul_p7_tbl_next_pointer_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - union oq_ll_mul_p7_tbl_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_oq_ll_mul_p7_tbl_get(dev_id, index, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.next_pointer = value; - ret = hppe_oq_ll_mul_p7_tbl_set(dev_id, index, ®_val); - return ret; -} - -sw_error_t -hppe_oq_ll_mul_p7_tbl_ingress_mirr_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union oq_ll_mul_p7_tbl_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_oq_ll_mul_p7_tbl_get(dev_id, index, ®_val); - *value = reg_val.bf.ingress_mirr; - return ret; -} - -sw_error_t -hppe_oq_ll_mul_p7_tbl_ingress_mirr_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - union oq_ll_mul_p7_tbl_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_oq_ll_mul_p7_tbl_get(dev_id, index, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.ingress_mirr = value; - ret = hppe_oq_ll_mul_p7_tbl_set(dev_id, index, ®_val); - return ret; -} - -sw_error_t -hppe_oq_ll_mul_p7_tbl_egress_mirr_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union oq_ll_mul_p7_tbl_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_oq_ll_mul_p7_tbl_get(dev_id, index, ®_val); - *value = reg_val.bf.egress_mirr; - return ret; -} - -sw_error_t -hppe_oq_ll_mul_p7_tbl_egress_mirr_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - union oq_ll_mul_p7_tbl_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_oq_ll_mul_p7_tbl_get(dev_id, index, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.egress_mirr = value; - ret = hppe_oq_ll_mul_p7_tbl_set(dev_id, index, ®_val); - return ret; -} - -sw_error_t -hppe_oq_ll_mul_p7_tbl_normal_fwd_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union oq_ll_mul_p7_tbl_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_oq_ll_mul_p7_tbl_get(dev_id, index, ®_val); - *value = reg_val.bf.normal_fwd; - return ret; -} - -sw_error_t -hppe_oq_ll_mul_p7_tbl_normal_fwd_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - union oq_ll_mul_p7_tbl_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_oq_ll_mul_p7_tbl_get(dev_id, index, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.normal_fwd = value; - ret = hppe_oq_ll_mul_p7_tbl_set(dev_id, index, ®_val); - return ret; -} - -sw_error_t -hppe_pkt_desp_tbl_ip_addr_index_valid_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union pkt_desp_tbl_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_pkt_desp_tbl_get(dev_id, index, ®_val); - *value = reg_val.bf1.ip_addr_index_valid; - return ret; -} - -sw_error_t -hppe_pkt_desp_tbl_ip_addr_index_valid_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - union pkt_desp_tbl_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_pkt_desp_tbl_get(dev_id, index, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf1.ip_addr_index_valid = value; - ret = hppe_pkt_desp_tbl_set(dev_id, index, ®_val); - return ret; -} - -sw_error_t -hppe_pkt_desp_tbl_route_flag_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union pkt_desp_tbl_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_pkt_desp_tbl_get(dev_id, index, ®_val); - *value = reg_val.bf1.route_flag; - return ret; -} - -sw_error_t -hppe_pkt_desp_tbl_route_flag_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - union pkt_desp_tbl_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_pkt_desp_tbl_get(dev_id, index, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf1.route_flag = value; - ret = hppe_pkt_desp_tbl_set(dev_id, index, ®_val); - return ret; -} - -sw_error_t -hppe_pkt_desp_tbl_int_cpcp_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union pkt_desp_tbl_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_pkt_desp_tbl_get(dev_id, index, ®_val); - *value = reg_val.bf1.int_cpcp; - return ret; -} - -sw_error_t -hppe_pkt_desp_tbl_int_cpcp_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - union pkt_desp_tbl_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_pkt_desp_tbl_get(dev_id, index, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf1.int_cpcp = value; - ret = hppe_pkt_desp_tbl_set(dev_id, index, ®_val); - return ret; -} - -sw_error_t -hppe_pkt_desp_tbl_pkt_l3_edit_bypass_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union pkt_desp_tbl_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_pkt_desp_tbl_get(dev_id, index, ®_val); - *value = reg_val.bf1.pkt_l3_edit_bypass; - return ret; -} - -sw_error_t -hppe_pkt_desp_tbl_pkt_l3_edit_bypass_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - union pkt_desp_tbl_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_pkt_desp_tbl_get(dev_id, index, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf1.pkt_l3_edit_bypass = value; - ret = hppe_pkt_desp_tbl_set(dev_id, index, ®_val); - return ret; -} - -sw_error_t -hppe_pkt_desp_tbl_int_ctag_fmt_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union pkt_desp_tbl_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_pkt_desp_tbl_get(dev_id, index, ®_val); - *value = reg_val.bf1.int_ctag_fmt; - return ret; -} - -sw_error_t -hppe_pkt_desp_tbl_int_ctag_fmt_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - union pkt_desp_tbl_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_pkt_desp_tbl_get(dev_id, index, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf1.int_ctag_fmt = value; - ret = hppe_pkt_desp_tbl_set(dev_id, index, ®_val); - return ret; -} - -sw_error_t -hppe_pkt_desp_tbl_fake_mac_header_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union pkt_desp_tbl_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_pkt_desp_tbl_get(dev_id, index, ®_val); - *value = reg_val.bf1.fake_mac_header; - return ret; -} - -sw_error_t -hppe_pkt_desp_tbl_fake_mac_header_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - union pkt_desp_tbl_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_pkt_desp_tbl_get(dev_id, index, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf1.fake_mac_header = value; - ret = hppe_pkt_desp_tbl_set(dev_id, index, ®_val); - return ret; -} - -sw_error_t -hppe_pkt_desp_tbl_acl_index_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union pkt_desp_tbl_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_pkt_desp_tbl_get(dev_id, index, ®_val); - *value = reg_val.bf1.acl_index; - return ret; -} - -sw_error_t -hppe_pkt_desp_tbl_acl_index_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - union pkt_desp_tbl_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_pkt_desp_tbl_get(dev_id, index, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf1.acl_index = value; - ret = hppe_pkt_desp_tbl_set(dev_id, index, ®_val); - return ret; -} - -sw_error_t -hppe_pkt_desp_tbl_l4_type_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union pkt_desp_tbl_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_pkt_desp_tbl_get(dev_id, index, ®_val); - *value = reg_val.bf1.l4_type; - return ret; -} - -sw_error_t -hppe_pkt_desp_tbl_l4_type_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - union pkt_desp_tbl_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_pkt_desp_tbl_get(dev_id, index, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf1.l4_type = value; - ret = hppe_pkt_desp_tbl_set(dev_id, index, ®_val); - return ret; -} - -sw_error_t -hppe_pkt_desp_tbl_int_svid_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union pkt_desp_tbl_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_pkt_desp_tbl_get(dev_id, index, ®_val); - *value = reg_val.bf1.int_svid; - return ret; -} - -sw_error_t -hppe_pkt_desp_tbl_int_svid_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - union pkt_desp_tbl_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_pkt_desp_tbl_get(dev_id, index, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf1.int_svid = value; - ret = hppe_pkt_desp_tbl_set(dev_id, index, ®_val); - return ret; -} - -sw_error_t -hppe_pkt_desp_tbl_int_sdei_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union pkt_desp_tbl_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_pkt_desp_tbl_get(dev_id, index, ®_val); - *value = reg_val.bf1.int_sdei; - return ret; -} - -sw_error_t -hppe_pkt_desp_tbl_int_sdei_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - union pkt_desp_tbl_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_pkt_desp_tbl_get(dev_id, index, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf1.int_sdei = value; - ret = hppe_pkt_desp_tbl_set(dev_id, index, ®_val); - return ret; -} - -sw_error_t -hppe_pkt_desp_tbl_fc_en_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union pkt_desp_tbl_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_pkt_desp_tbl_get(dev_id, index, ®_val); - *value = reg_val.bf1.fc_en; - return ret; -} - -sw_error_t -hppe_pkt_desp_tbl_fc_en_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - union pkt_desp_tbl_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_pkt_desp_tbl_get(dev_id, index, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf1.fc_en = value; - ret = hppe_pkt_desp_tbl_set(dev_id, index, ®_val); - return ret; -} - -sw_error_t -hppe_pkt_desp_tbl_packet_length_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union pkt_desp_tbl_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_pkt_desp_tbl_get(dev_id, index, ®_val); - *value = reg_val.bf1.packet_length_1 << 8 | \ - reg_val.bf1.packet_length_0; - return ret; -} - -sw_error_t -hppe_pkt_desp_tbl_packet_length_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - union pkt_desp_tbl_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_pkt_desp_tbl_get(dev_id, index, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf1.packet_length_1 = value >> 8; - reg_val.bf1.packet_length_0 = value & (((a_uint64_t)1<<8)-1); - ret = hppe_pkt_desp_tbl_set(dev_id, index, ®_val); - return ret; -} - -sw_error_t -hppe_pkt_desp_tbl_rx_ts_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint64_t *value) -{ - union pkt_desp_tbl_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_pkt_desp_tbl_get(dev_id, index, ®_val); - *value = (a_uint64_t)reg_val.bf1.rx_ts_1 << 24 | \ - reg_val.bf1.rx_ts_0; - return ret; -} - -sw_error_t -hppe_pkt_desp_tbl_rx_ts_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint64_t value) -{ - union pkt_desp_tbl_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_pkt_desp_tbl_get(dev_id, index, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf1.rx_ts_1 = value >> 24; - reg_val.bf1.rx_ts_0 = value & (((a_uint64_t)1<<24)-1); - ret = hppe_pkt_desp_tbl_set(dev_id, index, ®_val); - return ret; -} - -sw_error_t -hppe_pkt_desp_tbl_ts_dir_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union pkt_desp_tbl_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_pkt_desp_tbl_get(dev_id, index, ®_val); - *value = reg_val.bf1.ts_dir; - return ret; -} - -sw_error_t -hppe_pkt_desp_tbl_ts_dir_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - union pkt_desp_tbl_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_pkt_desp_tbl_get(dev_id, index, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf1.ts_dir = value; - ret = hppe_pkt_desp_tbl_set(dev_id, index, ®_val); - return ret; -} - -sw_error_t -hppe_pkt_desp_tbl_chg_port_vp_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union pkt_desp_tbl_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_pkt_desp_tbl_get(dev_id, index, ®_val); - *value = reg_val.bf1.chg_port_vp; - return ret; -} - -sw_error_t -hppe_pkt_desp_tbl_chg_port_vp_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - union pkt_desp_tbl_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_pkt_desp_tbl_get(dev_id, index, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf1.chg_port_vp = value; - ret = hppe_pkt_desp_tbl_set(dev_id, index, ®_val); - return ret; -} - -sw_error_t -hppe_pkt_desp_tbl_int_pri_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union pkt_desp_tbl_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_pkt_desp_tbl_get(dev_id, index, ®_val); - *value = reg_val.bf1.int_pri; - return ret; -} - -sw_error_t -hppe_pkt_desp_tbl_int_pri_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - union pkt_desp_tbl_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_pkt_desp_tbl_get(dev_id, index, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf1.int_pri = value; - ret = hppe_pkt_desp_tbl_set(dev_id, index, ®_val); - return ret; -} - -sw_error_t -hppe_pkt_desp_tbl_one_enq_flag_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union pkt_desp_tbl_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_pkt_desp_tbl_get(dev_id, index, ®_val); - *value = reg_val.bf1.one_enq_flag; - return ret; -} - -sw_error_t -hppe_pkt_desp_tbl_one_enq_flag_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - union pkt_desp_tbl_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_pkt_desp_tbl_get(dev_id, index, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf1.one_enq_flag = value; - ret = hppe_pkt_desp_tbl_set(dev_id, index, ®_val); - return ret; -} - -sw_error_t -hppe_pkt_desp_tbl_fc_grp_id_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union pkt_desp_tbl_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_pkt_desp_tbl_get(dev_id, index, ®_val); - *value = reg_val.bf1.fc_grp_id; - return ret; -} - -sw_error_t -hppe_pkt_desp_tbl_fc_grp_id_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - union pkt_desp_tbl_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_pkt_desp_tbl_get(dev_id, index, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf1.fc_grp_id = value; - ret = hppe_pkt_desp_tbl_set(dev_id, index, ®_val); - return ret; -} - -sw_error_t -hppe_pkt_desp_tbl_fake_l2_prot_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union pkt_desp_tbl_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_pkt_desp_tbl_get(dev_id, index, ®_val); - *value = reg_val.bf1.fake_l2_prot; - return ret; -} - -sw_error_t -hppe_pkt_desp_tbl_fake_l2_prot_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - union pkt_desp_tbl_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_pkt_desp_tbl_get(dev_id, index, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf1.fake_l2_prot = value; - ret = hppe_pkt_desp_tbl_set(dev_id, index, ®_val); - return ret; -} - -sw_error_t -hppe_pkt_desp_tbl_org_src_port_vp_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union pkt_desp_tbl_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_pkt_desp_tbl_get(dev_id, index, ®_val); - *value = reg_val.bf1.org_src_port_vp; - return ret; -} - -sw_error_t -hppe_pkt_desp_tbl_org_src_port_vp_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - union pkt_desp_tbl_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_pkt_desp_tbl_get(dev_id, index, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf1.org_src_port_vp = value; - ret = hppe_pkt_desp_tbl_set(dev_id, index, ®_val); - return ret; -} - -sw_error_t -hppe_pkt_desp_tbl_hash_flag_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union pkt_desp_tbl_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_pkt_desp_tbl_get(dev_id, index, ®_val); - *value = reg_val.bf1.hash_flag; - return ret; -} - -sw_error_t -hppe_pkt_desp_tbl_hash_flag_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - union pkt_desp_tbl_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_pkt_desp_tbl_get(dev_id, index, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf1.hash_flag = value; - ret = hppe_pkt_desp_tbl_set(dev_id, index, ®_val); - return ret; -} - -sw_error_t -hppe_pkt_desp_tbl_int_stag_fmt_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union pkt_desp_tbl_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_pkt_desp_tbl_get(dev_id, index, ®_val); - *value = reg_val.bf1.int_stag_fmt; - return ret; -} - -sw_error_t -hppe_pkt_desp_tbl_int_stag_fmt_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - union pkt_desp_tbl_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_pkt_desp_tbl_get(dev_id, index, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf1.int_stag_fmt = value; - ret = hppe_pkt_desp_tbl_set(dev_id, index, ®_val); - return ret; -} - -sw_error_t -hppe_pkt_desp_tbl_service_code_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union pkt_desp_tbl_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_pkt_desp_tbl_get(dev_id, index, ®_val); - *value = reg_val.bf1.service_code_1 << 2 | \ - reg_val.bf1.service_code_0; - return ret; -} - -sw_error_t -hppe_pkt_desp_tbl_service_code_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - union pkt_desp_tbl_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_pkt_desp_tbl_get(dev_id, index, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf1.service_code_1 = value >> 2; - reg_val.bf1.service_code_0 = value & (((a_uint64_t)1<<2)-1); - ret = hppe_pkt_desp_tbl_set(dev_id, index, ®_val); - return ret; -} - -sw_error_t -hppe_pkt_desp_tbl_rx_ptp_type_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union pkt_desp_tbl_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_pkt_desp_tbl_get(dev_id, index, ®_val); - *value = reg_val.bf1.rx_ptp_type; - return ret; -} - -sw_error_t -hppe_pkt_desp_tbl_rx_ptp_type_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - union pkt_desp_tbl_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_pkt_desp_tbl_get(dev_id, index, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf1.rx_ptp_type = value; - ret = hppe_pkt_desp_tbl_set(dev_id, index, ®_val); - return ret; -} - -sw_error_t -hppe_pkt_desp_tbl_mac_da_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint64_t *value) -{ - union pkt_desp_tbl_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_pkt_desp_tbl_get(dev_id, index, ®_val); - *value = (a_uint64_t)reg_val.bf1.mac_da_1 << 18 | \ - reg_val.bf1.mac_da_0; - return ret; -} - -sw_error_t -hppe_pkt_desp_tbl_mac_da_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint64_t value) -{ - union pkt_desp_tbl_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_pkt_desp_tbl_get(dev_id, index, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf1.mac_da_1 = value >> 18; - reg_val.bf1.mac_da_0 = value & (((a_uint64_t)1<<18)-1); - ret = hppe_pkt_desp_tbl_set(dev_id, index, ®_val); - return ret; -} - -sw_error_t -hppe_pkt_desp_tbl_cpu_code_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union pkt_desp_tbl_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_pkt_desp_tbl_get(dev_id, index, ®_val); - *value = reg_val.bf1.cpu_code; - return ret; -} - -sw_error_t -hppe_pkt_desp_tbl_cpu_code_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - union pkt_desp_tbl_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_pkt_desp_tbl_get(dev_id, index, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf1.cpu_code = value; - ret = hppe_pkt_desp_tbl_set(dev_id, index, ®_val); - return ret; -} - -sw_error_t -hppe_pkt_desp_tbl_eg_vlan_tag_fmt_bypass_en_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union pkt_desp_tbl_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_pkt_desp_tbl_get(dev_id, index, ®_val); - *value = reg_val.bf1.eg_vlan_tag_fmt_bypass_en; - return ret; -} - -sw_error_t -hppe_pkt_desp_tbl_eg_vlan_tag_fmt_bypass_en_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - union pkt_desp_tbl_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_pkt_desp_tbl_get(dev_id, index, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf1.eg_vlan_tag_fmt_bypass_en = value; - ret = hppe_pkt_desp_tbl_set(dev_id, index, ®_val); - return ret; -} - -sw_error_t -hppe_pkt_desp_tbl_ip_addr_index_type_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union pkt_desp_tbl_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_pkt_desp_tbl_get(dev_id, index, ®_val); - *value = reg_val.bf1.ip_addr_index_type; - return ret; -} - -sw_error_t -hppe_pkt_desp_tbl_ip_addr_index_type_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - union pkt_desp_tbl_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_pkt_desp_tbl_get(dev_id, index, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf1.ip_addr_index_type = value; - ret = hppe_pkt_desp_tbl_set(dev_id, index, ®_val); - return ret; -} - -sw_error_t -hppe_pkt_desp_tbl_int_cvid_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union pkt_desp_tbl_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_pkt_desp_tbl_get(dev_id, index, ®_val); - *value = reg_val.bf1.int_cvid_1 << 9 | \ - reg_val.bf1.int_cvid_0; - return ret; -} - -sw_error_t -hppe_pkt_desp_tbl_int_cvid_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - union pkt_desp_tbl_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_pkt_desp_tbl_get(dev_id, index, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf1.int_cvid_1 = value >> 9; - reg_val.bf1.int_cvid_0 = value & (((a_uint64_t)1<<9)-1); - ret = hppe_pkt_desp_tbl_set(dev_id, index, ®_val); - return ret; -} - -sw_error_t -hppe_pkt_desp_tbl_eg_vlan_xlt_bypass_en_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union pkt_desp_tbl_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_pkt_desp_tbl_get(dev_id, index, ®_val); - *value = reg_val.bf1.eg_vlan_xlt_bypass_en; - return ret; -} - -sw_error_t -hppe_pkt_desp_tbl_eg_vlan_xlt_bypass_en_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - union pkt_desp_tbl_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_pkt_desp_tbl_get(dev_id, index, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf1.eg_vlan_xlt_bypass_en = value; - ret = hppe_pkt_desp_tbl_set(dev_id, index, ®_val); - return ret; -} - -sw_error_t -hppe_pkt_desp_tbl_hash_value_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union pkt_desp_tbl_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_pkt_desp_tbl_get(dev_id, index, ®_val); - *value = reg_val.bf1.hash_value_1 << 5 | \ - reg_val.bf1.hash_value_0; - return ret; -} - -sw_error_t -hppe_pkt_desp_tbl_hash_value_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - union pkt_desp_tbl_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_pkt_desp_tbl_get(dev_id, index, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf1.hash_value_1 = value >> 5; - reg_val.bf1.hash_value_0 = value & (((a_uint64_t)1<<5)-1); - ret = hppe_pkt_desp_tbl_set(dev_id, index, ®_val); - return ret; -} - -sw_error_t -hppe_pkt_desp_tbl_stag_flag_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union pkt_desp_tbl_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_pkt_desp_tbl_get(dev_id, index, ®_val); - *value = reg_val.bf1.stag_flag; - return ret; -} - -sw_error_t -hppe_pkt_desp_tbl_stag_flag_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - union pkt_desp_tbl_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_pkt_desp_tbl_get(dev_id, index, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf1.stag_flag = value; - ret = hppe_pkt_desp_tbl_set(dev_id, index, ®_val); - return ret; -} - -sw_error_t -hppe_pkt_desp_tbl_dst_l3_if_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union pkt_desp_tbl_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_pkt_desp_tbl_get(dev_id, index, ®_val); - *value = reg_val.bf1.dst_l3_if; - return ret; -} - -sw_error_t -hppe_pkt_desp_tbl_dst_l3_if_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - union pkt_desp_tbl_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_pkt_desp_tbl_get(dev_id, index, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf1.dst_l3_if = value; - ret = hppe_pkt_desp_tbl_set(dev_id, index, ®_val); - return ret; -} - -sw_error_t -hppe_pkt_desp_tbl_int_cdei_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union pkt_desp_tbl_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_pkt_desp_tbl_get(dev_id, index, ®_val); - *value = reg_val.bf1.int_cdei; - return ret; -} - -sw_error_t -hppe_pkt_desp_tbl_int_cdei_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - union pkt_desp_tbl_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_pkt_desp_tbl_get(dev_id, index, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf1.int_cdei = value; - ret = hppe_pkt_desp_tbl_set(dev_id, index, ®_val); - return ret; -} - -sw_error_t -hppe_pkt_desp_tbl_edma_vp_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union pkt_desp_tbl_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_pkt_desp_tbl_get(dev_id, index, ®_val); - *value = reg_val.bf1.edma_vp; - return ret; -} - -sw_error_t -hppe_pkt_desp_tbl_edma_vp_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - union pkt_desp_tbl_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_pkt_desp_tbl_get(dev_id, index, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf1.edma_vp = value; - ret = hppe_pkt_desp_tbl_set(dev_id, index, ®_val); - return ret; -} - -sw_error_t -hppe_pkt_desp_tbl_ac_group_bitmap_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union pkt_desp_tbl_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_pkt_desp_tbl_get(dev_id, index, ®_val); - *value = reg_val.bf1.ac_group_bitmap; - return ret; -} - -sw_error_t -hppe_pkt_desp_tbl_ac_group_bitmap_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - union pkt_desp_tbl_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_pkt_desp_tbl_get(dev_id, index, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf1.ac_group_bitmap = value; - ret = hppe_pkt_desp_tbl_set(dev_id, index, ®_val); - return ret; -} - -sw_error_t -hppe_pkt_desp_tbl_vp_tx_cnt_en_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union pkt_desp_tbl_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_pkt_desp_tbl_get(dev_id, index, ®_val); - *value = reg_val.bf1.vp_tx_cnt_en; - return ret; -} - -sw_error_t -hppe_pkt_desp_tbl_vp_tx_cnt_en_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - union pkt_desp_tbl_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_pkt_desp_tbl_get(dev_id, index, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf1.vp_tx_cnt_en = value; - ret = hppe_pkt_desp_tbl_set(dev_id, index, ®_val); - return ret; -} - -sw_error_t -hppe_pkt_desp_tbl_src_port_vp_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union pkt_desp_tbl_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_pkt_desp_tbl_get(dev_id, index, ®_val); - *value = reg_val.bf1.src_port_vp; - return ret; -} - -sw_error_t -hppe_pkt_desp_tbl_src_port_vp_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - union pkt_desp_tbl_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_pkt_desp_tbl_get(dev_id, index, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf1.src_port_vp = value; - ret = hppe_pkt_desp_tbl_set(dev_id, index, ®_val); - return ret; -} - -sw_error_t -hppe_pkt_desp_tbl_nat_action_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union pkt_desp_tbl_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_pkt_desp_tbl_get(dev_id, index, ®_val); - *value = reg_val.bf1.nat_action; - return ret; -} - -sw_error_t -hppe_pkt_desp_tbl_nat_action_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - union pkt_desp_tbl_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_pkt_desp_tbl_get(dev_id, index, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf1.nat_action = value; - ret = hppe_pkt_desp_tbl_set(dev_id, index, ®_val); - return ret; -} - -sw_error_t -hppe_pkt_desp_tbl_dscp_update_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union pkt_desp_tbl_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_pkt_desp_tbl_get(dev_id, index, ®_val); - *value = reg_val.bf1.dscp_update; - return ret; -} - -sw_error_t -hppe_pkt_desp_tbl_dscp_update_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - union pkt_desp_tbl_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_pkt_desp_tbl_get(dev_id, index, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf1.dscp_update = value; - ret = hppe_pkt_desp_tbl_set(dev_id, index, ®_val); - return ret; -} - -sw_error_t -hppe_pkt_desp_tbl_pppoe_strip_flag_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union pkt_desp_tbl_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_pkt_desp_tbl_get(dev_id, index, ®_val); - *value = reg_val.bf1.pppoe_strip_flag; - return ret; -} - -sw_error_t -hppe_pkt_desp_tbl_pppoe_strip_flag_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - union pkt_desp_tbl_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_pkt_desp_tbl_get(dev_id, index, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf1.pppoe_strip_flag = value; - ret = hppe_pkt_desp_tbl_set(dev_id, index, ®_val); - return ret; -} - -sw_error_t -hppe_pkt_desp_tbl_snap_flag_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union pkt_desp_tbl_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_pkt_desp_tbl_get(dev_id, index, ®_val); - *value = reg_val.bf1.snap_flag; - return ret; -} - -sw_error_t -hppe_pkt_desp_tbl_snap_flag_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - union pkt_desp_tbl_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_pkt_desp_tbl_get(dev_id, index, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf1.snap_flag = value; - ret = hppe_pkt_desp_tbl_set(dev_id, index, ®_val); - return ret; -} - -sw_error_t -hppe_pkt_desp_tbl_vsi_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union pkt_desp_tbl_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_pkt_desp_tbl_get(dev_id, index, ®_val); - *value = reg_val.bf1.vsi; - return ret; -} - -sw_error_t -hppe_pkt_desp_tbl_vsi_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - union pkt_desp_tbl_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_pkt_desp_tbl_get(dev_id, index, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf1.vsi = value; - ret = hppe_pkt_desp_tbl_set(dev_id, index, ®_val); - return ret; -} - -sw_error_t -hppe_pkt_desp_tbl_pkt_l2_edit_bypass_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union pkt_desp_tbl_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_pkt_desp_tbl_get(dev_id, index, ®_val); - *value = reg_val.bf1.pkt_l2_edit_bypass; - return ret; -} - -sw_error_t -hppe_pkt_desp_tbl_pkt_l2_edit_bypass_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - union pkt_desp_tbl_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_pkt_desp_tbl_get(dev_id, index, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf1.pkt_l2_edit_bypass = value; - ret = hppe_pkt_desp_tbl_set(dev_id, index, ®_val); - return ret; -} - -sw_error_t -hppe_pkt_desp_tbl_tx_ptp_tag_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union pkt_desp_tbl_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_pkt_desp_tbl_get(dev_id, index, ®_val); - *value = reg_val.bf0.tx_ptp_tag; - return ret; -} - -sw_error_t -hppe_pkt_desp_tbl_tx_ptp_tag_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - union pkt_desp_tbl_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_pkt_desp_tbl_get(dev_id, index, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf0.tx_ptp_tag = value; - ret = hppe_pkt_desp_tbl_set(dev_id, index, ®_val); - return ret; -} - -sw_error_t -hppe_pkt_desp_tbl_ip_addr_index_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union pkt_desp_tbl_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_pkt_desp_tbl_get(dev_id, index, ®_val); - *value = reg_val.bf1.ip_addr_index_1 << 1 | \ - reg_val.bf1.ip_addr_index_0; - return ret; -} - -sw_error_t -hppe_pkt_desp_tbl_ip_addr_index_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - union pkt_desp_tbl_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_pkt_desp_tbl_get(dev_id, index, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf1.ip_addr_index_1 = value >> 1; - reg_val.bf1.ip_addr_index_0 = value & (((a_uint64_t)1<<1)-1); - ret = hppe_pkt_desp_tbl_set(dev_id, index, ®_val); - return ret; -} - -sw_error_t -hppe_pkt_desp_tbl_int_dp_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union pkt_desp_tbl_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_pkt_desp_tbl_get(dev_id, index, ®_val); - *value = reg_val.bf1.int_dp; - return ret; -} - -sw_error_t -hppe_pkt_desp_tbl_int_dp_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - union pkt_desp_tbl_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_pkt_desp_tbl_get(dev_id, index, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf1.int_dp = value; - ret = hppe_pkt_desp_tbl_set(dev_id, index, ®_val); - return ret; -} - -sw_error_t -hppe_pkt_desp_tbl_src_pn_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union pkt_desp_tbl_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_pkt_desp_tbl_get(dev_id, index, ®_val); - *value = reg_val.bf1.src_pn; - return ret; -} - -sw_error_t -hppe_pkt_desp_tbl_src_pn_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - union pkt_desp_tbl_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_pkt_desp_tbl_get(dev_id, index, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf1.src_pn = value; - ret = hppe_pkt_desp_tbl_set(dev_id, index, ®_val); - return ret; -} - -sw_error_t -hppe_pkt_desp_tbl_tx_ts_en_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union pkt_desp_tbl_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_pkt_desp_tbl_get(dev_id, index, ®_val); - *value = reg_val.bf0.tx_ts_en; - return ret; -} - -sw_error_t -hppe_pkt_desp_tbl_tx_ts_en_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - union pkt_desp_tbl_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_pkt_desp_tbl_get(dev_id, index, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf0.tx_ts_en = value; - ret = hppe_pkt_desp_tbl_set(dev_id, index, ®_val); - return ret; -} - -sw_error_t -hppe_pkt_desp_tbl_l4_offset_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union pkt_desp_tbl_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_pkt_desp_tbl_get(dev_id, index, ®_val); - *value = reg_val.bf1.l4_offset_1 << 6 | \ - reg_val.bf1.l4_offset_0; - return ret; -} - -sw_error_t -hppe_pkt_desp_tbl_l4_offset_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - union pkt_desp_tbl_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_pkt_desp_tbl_get(dev_id, index, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf1.l4_offset_1 = value >> 6; - reg_val.bf1.l4_offset_0 = value & (((a_uint64_t)1<<6)-1); - ret = hppe_pkt_desp_tbl_set(dev_id, index, ®_val); - return ret; -} - -sw_error_t -hppe_pkt_desp_tbl_ttl_update_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union pkt_desp_tbl_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_pkt_desp_tbl_get(dev_id, index, ®_val); - *value = reg_val.bf1.ttl_update; - return ret; -} - -sw_error_t -hppe_pkt_desp_tbl_ttl_update_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - union pkt_desp_tbl_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_pkt_desp_tbl_get(dev_id, index, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf1.ttl_update = value; - ret = hppe_pkt_desp_tbl_set(dev_id, index, ®_val); - return ret; -} - -sw_error_t -hppe_pkt_desp_tbl_napt_port_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union pkt_desp_tbl_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_pkt_desp_tbl_get(dev_id, index, ®_val); - *value = reg_val.bf1.napt_port; - return ret; -} - -sw_error_t -hppe_pkt_desp_tbl_napt_port_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - union pkt_desp_tbl_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_pkt_desp_tbl_get(dev_id, index, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf1.napt_port = value; - ret = hppe_pkt_desp_tbl_set(dev_id, index, ®_val); - return ret; -} - -sw_error_t -hppe_pkt_desp_tbl_napt_addr_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union pkt_desp_tbl_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_pkt_desp_tbl_get(dev_id, index, ®_val); - *value = reg_val.bf1.napt_addr_1 << 13 | \ - reg_val.bf1.napt_addr_0; - return ret; -} - -sw_error_t -hppe_pkt_desp_tbl_napt_addr_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - union pkt_desp_tbl_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_pkt_desp_tbl_get(dev_id, index, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf1.napt_addr_1 = value >> 13; - reg_val.bf1.napt_addr_0 = value & (((a_uint64_t)1<<13)-1); - ret = hppe_pkt_desp_tbl_set(dev_id, index, ®_val); - return ret; -} - -sw_error_t -hppe_pkt_desp_tbl_copy_cpu_flag_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union pkt_desp_tbl_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_pkt_desp_tbl_get(dev_id, index, ®_val); - *value = reg_val.bf1.copy_cpu_flag; - return ret; -} - -sw_error_t -hppe_pkt_desp_tbl_copy_cpu_flag_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - union pkt_desp_tbl_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_pkt_desp_tbl_get(dev_id, index, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf1.copy_cpu_flag = value; - ret = hppe_pkt_desp_tbl_set(dev_id, index, ®_val); - return ret; -} - -sw_error_t -hppe_pkt_desp_tbl_ttl_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union pkt_desp_tbl_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_pkt_desp_tbl_get(dev_id, index, ®_val); - *value = reg_val.bf1.ttl_1 << 3 | \ - reg_val.bf1.ttl_0; - return ret; -} - -sw_error_t -hppe_pkt_desp_tbl_ttl_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - union pkt_desp_tbl_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_pkt_desp_tbl_get(dev_id, index, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf1.ttl_1 = value >> 3; - reg_val.bf1.ttl_0 = value & (((a_uint64_t)1<<3)-1); - ret = hppe_pkt_desp_tbl_set(dev_id, index, ®_val); - return ret; -} - -sw_error_t -hppe_pkt_desp_tbl_l3_offset_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union pkt_desp_tbl_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_pkt_desp_tbl_get(dev_id, index, ®_val); - *value = reg_val.bf1.l3_offset; - return ret; -} - -sw_error_t -hppe_pkt_desp_tbl_l3_offset_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - union pkt_desp_tbl_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_pkt_desp_tbl_get(dev_id, index, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf1.l3_offset = value; - ret = hppe_pkt_desp_tbl_set(dev_id, index, ®_val); - return ret; -} - -sw_error_t -hppe_pkt_desp_tbl_rsv0_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union pkt_desp_tbl_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_pkt_desp_tbl_get(dev_id, index, ®_val); - *value = reg_val.bf1.rsv0_1 << 3 | \ - reg_val.bf1.rsv0_0; - return ret; -} - -sw_error_t -hppe_pkt_desp_tbl_rsv0_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - union pkt_desp_tbl_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_pkt_desp_tbl_get(dev_id, index, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf1.rsv0_1 = value >> 3; - reg_val.bf1.rsv0_0 = value & (((a_uint64_t)1<<3)-1); - ret = hppe_pkt_desp_tbl_set(dev_id, index, ®_val); - return ret; -} - -sw_error_t -hppe_pkt_desp_tbl_next_header_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union pkt_desp_tbl_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_pkt_desp_tbl_get(dev_id, index, ®_val); - *value = reg_val.bf1.next_header; - return ret; -} - -sw_error_t -hppe_pkt_desp_tbl_next_header_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - union pkt_desp_tbl_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_pkt_desp_tbl_get(dev_id, index, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf1.next_header = value; - ret = hppe_pkt_desp_tbl_set(dev_id, index, ®_val); - return ret; -} - -sw_error_t -hppe_pkt_desp_tbl_acl_index_valid_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union pkt_desp_tbl_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_pkt_desp_tbl_get(dev_id, index, ®_val); - *value = reg_val.bf1.acl_index_valid; - return ret; -} - -sw_error_t -hppe_pkt_desp_tbl_acl_index_valid_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - union pkt_desp_tbl_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_pkt_desp_tbl_get(dev_id, index, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf1.acl_index_valid = value; - ret = hppe_pkt_desp_tbl_set(dev_id, index, ®_val); - return ret; -} - -sw_error_t -hppe_pkt_desp_tbl_rx_ts_valid_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union pkt_desp_tbl_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_pkt_desp_tbl_get(dev_id, index, ®_val); - *value = reg_val.bf1.rx_ts_valid; - return ret; -} - -sw_error_t -hppe_pkt_desp_tbl_rx_ts_valid_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - union pkt_desp_tbl_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_pkt_desp_tbl_get(dev_id, index, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf1.rx_ts_valid = value; - ret = hppe_pkt_desp_tbl_set(dev_id, index, ®_val); - return ret; -} - -sw_error_t -hppe_pkt_desp_tbl_dscp_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union pkt_desp_tbl_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_pkt_desp_tbl_get(dev_id, index, ®_val); - *value = reg_val.bf1.dscp; - return ret; -} - -sw_error_t -hppe_pkt_desp_tbl_dscp_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - union pkt_desp_tbl_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_pkt_desp_tbl_get(dev_id, index, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf1.dscp = value; - ret = hppe_pkt_desp_tbl_set(dev_id, index, ®_val); - return ret; -} - -sw_error_t -hppe_pkt_desp_tbl_acl_index_toggle_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union pkt_desp_tbl_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_pkt_desp_tbl_get(dev_id, index, ®_val); - *value = reg_val.bf1.acl_index_toggle; - return ret; -} - -sw_error_t -hppe_pkt_desp_tbl_acl_index_toggle_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - union pkt_desp_tbl_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_pkt_desp_tbl_get(dev_id, index, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf1.acl_index_toggle = value; - ret = hppe_pkt_desp_tbl_set(dev_id, index, ®_val); - return ret; -} - -sw_error_t -hppe_pkt_desp_tbl_ctag_flag_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union pkt_desp_tbl_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_pkt_desp_tbl_get(dev_id, index, ®_val); - *value = reg_val.bf1.ctag_flag; - return ret; -} - -sw_error_t -hppe_pkt_desp_tbl_ctag_flag_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - union pkt_desp_tbl_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_pkt_desp_tbl_get(dev_id, index, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf1.ctag_flag = value; - ret = hppe_pkt_desp_tbl_set(dev_id, index, ®_val); - return ret; -} - -sw_error_t -hppe_pkt_desp_tbl_ip_addr_index_toggle_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union pkt_desp_tbl_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_pkt_desp_tbl_get(dev_id, index, ®_val); - *value = reg_val.bf1.ip_addr_index_toggle; - return ret; -} - -sw_error_t -hppe_pkt_desp_tbl_ip_addr_index_toggle_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - union pkt_desp_tbl_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_pkt_desp_tbl_get(dev_id, index, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf1.ip_addr_index_toggle = value; - ret = hppe_pkt_desp_tbl_set(dev_id, index, ®_val); - return ret; -} - -sw_error_t -hppe_pkt_desp_tbl_tx_os_correction_en_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union pkt_desp_tbl_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_pkt_desp_tbl_get(dev_id, index, ®_val); - *value = reg_val.bf0.tx_os_correction_en; - return ret; -} - -sw_error_t -hppe_pkt_desp_tbl_tx_os_correction_en_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - union pkt_desp_tbl_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_pkt_desp_tbl_get(dev_id, index, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf0.tx_os_correction_en = value; - ret = hppe_pkt_desp_tbl_set(dev_id, index, ®_val); - return ret; -} - -sw_error_t -hppe_pkt_desp_tbl_int_spcp_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union pkt_desp_tbl_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_pkt_desp_tbl_get(dev_id, index, ®_val); - *value = reg_val.bf1.int_spcp; - return ret; -} - -sw_error_t -hppe_pkt_desp_tbl_int_spcp_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - union pkt_desp_tbl_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_pkt_desp_tbl_get(dev_id, index, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf1.int_spcp = value; - ret = hppe_pkt_desp_tbl_set(dev_id, index, ®_val); - return ret; -} - -sw_error_t -hppe_pkt_desp_tbl_pppoe_flag_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union pkt_desp_tbl_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_pkt_desp_tbl_get(dev_id, index, ®_val); - *value = reg_val.bf1.pppoe_flag; - return ret; -} - -sw_error_t -hppe_pkt_desp_tbl_pppoe_flag_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - union pkt_desp_tbl_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_pkt_desp_tbl_get(dev_id, index, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf1.pppoe_flag = value; - ret = hppe_pkt_desp_tbl_set(dev_id, index, ®_val); - return ret; -} - -sw_error_t -hppe_pkt_desp_tbl_l3_type_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union pkt_desp_tbl_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_pkt_desp_tbl_get(dev_id, index, ®_val); - *value = reg_val.bf1.l3_type; - return ret; -} - -sw_error_t -hppe_pkt_desp_tbl_l3_type_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - union pkt_desp_tbl_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_pkt_desp_tbl_get(dev_id, index, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf1.l3_type = value; - ret = hppe_pkt_desp_tbl_set(dev_id, index, ®_val); - return ret; -} - -sw_error_t -hppe_pkt_desp_tbl_vsi_valid_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union pkt_desp_tbl_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_pkt_desp_tbl_get(dev_id, index, ®_val); - *value = reg_val.bf1.vsi_valid; - return ret; -} - -sw_error_t -hppe_pkt_desp_tbl_vsi_valid_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - union pkt_desp_tbl_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_pkt_desp_tbl_get(dev_id, index, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf1.vsi_valid = value; - ret = hppe_pkt_desp_tbl_set(dev_id, index, ®_val); - return ret; -} - -sw_error_t -hppe_uni_drop_cnt_tbl_uni_drop_byte_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint64_t *value) -{ - union uni_drop_cnt_tbl_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_uni_drop_cnt_tbl_get(dev_id, index, ®_val); - *value = (a_uint64_t)reg_val.bf.uni_drop_byte_1 << 32 | \ - reg_val.bf.uni_drop_byte_0; - return ret; -} - -sw_error_t -hppe_uni_drop_cnt_tbl_uni_drop_byte_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint64_t value) -{ - union uni_drop_cnt_tbl_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_uni_drop_cnt_tbl_get(dev_id, index, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.uni_drop_byte_1 = value >> 32; - reg_val.bf.uni_drop_byte_0 = value & (((a_uint64_t)1<<32)-1); - ret = hppe_uni_drop_cnt_tbl_set(dev_id, index, ®_val); - return ret; -} - -sw_error_t -hppe_uni_drop_cnt_tbl_uni_drop_pkt_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union uni_drop_cnt_tbl_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_uni_drop_cnt_tbl_get(dev_id, index, ®_val); - *value = reg_val.bf.uni_drop_pkt; - return ret; -} - -sw_error_t -hppe_uni_drop_cnt_tbl_uni_drop_pkt_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - union uni_drop_cnt_tbl_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_uni_drop_cnt_tbl_get(dev_id, index, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.uni_drop_pkt = value; - ret = hppe_uni_drop_cnt_tbl_set(dev_id, index, ®_val); - return ret; -} - -sw_error_t -hppe_mul_p0_drop_cnt_tbl_mul_p0_drop_pkt_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union mul_p0_drop_cnt_tbl_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_mul_p0_drop_cnt_tbl_get(dev_id, index, ®_val); - *value = reg_val.bf.mul_p0_drop_pkt; - return ret; -} - -sw_error_t -hppe_mul_p0_drop_cnt_tbl_mul_p0_drop_pkt_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - union mul_p0_drop_cnt_tbl_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_mul_p0_drop_cnt_tbl_get(dev_id, index, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.mul_p0_drop_pkt = value; - ret = hppe_mul_p0_drop_cnt_tbl_set(dev_id, index, ®_val); - return ret; -} - -sw_error_t -hppe_mul_p0_drop_cnt_tbl_mul_p0_drop_byte_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint64_t *value) -{ - union mul_p0_drop_cnt_tbl_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_mul_p0_drop_cnt_tbl_get(dev_id, index, ®_val); - *value = (a_uint64_t)reg_val.bf.mul_p0_drop_byte_1 << 32 | \ - reg_val.bf.mul_p0_drop_byte_0; - return ret; -} - -sw_error_t -hppe_mul_p0_drop_cnt_tbl_mul_p0_drop_byte_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint64_t value) -{ - union mul_p0_drop_cnt_tbl_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_mul_p0_drop_cnt_tbl_get(dev_id, index, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.mul_p0_drop_byte_1 = value >> 32; - reg_val.bf.mul_p0_drop_byte_0 = value & (((a_uint64_t)1<<32)-1); - ret = hppe_mul_p0_drop_cnt_tbl_set(dev_id, index, ®_val); - return ret; -} - -sw_error_t -hppe_mul_p1_drop_cnt_tbl_mul_p1_drop_byte_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint64_t *value) -{ - union mul_p1_drop_cnt_tbl_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_mul_p1_drop_cnt_tbl_get(dev_id, index, ®_val); - *value = (a_uint64_t)reg_val.bf.mul_p1_drop_byte_1 << 32 | \ - reg_val.bf.mul_p1_drop_byte_0; - return ret; -} - -sw_error_t -hppe_mul_p1_drop_cnt_tbl_mul_p1_drop_byte_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint64_t value) -{ - union mul_p1_drop_cnt_tbl_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_mul_p1_drop_cnt_tbl_get(dev_id, index, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.mul_p1_drop_byte_1 = value >> 32; - reg_val.bf.mul_p1_drop_byte_0 = value & (((a_uint64_t)1<<32)-1); - ret = hppe_mul_p1_drop_cnt_tbl_set(dev_id, index, ®_val); - return ret; -} - -sw_error_t -hppe_mul_p1_drop_cnt_tbl_mul_p1_drop_pkt_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union mul_p1_drop_cnt_tbl_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_mul_p1_drop_cnt_tbl_get(dev_id, index, ®_val); - *value = reg_val.bf.mul_p1_drop_pkt; - return ret; -} - -sw_error_t -hppe_mul_p1_drop_cnt_tbl_mul_p1_drop_pkt_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - union mul_p1_drop_cnt_tbl_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_mul_p1_drop_cnt_tbl_get(dev_id, index, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.mul_p1_drop_pkt = value; - ret = hppe_mul_p1_drop_cnt_tbl_set(dev_id, index, ®_val); - return ret; -} - -sw_error_t -hppe_mul_p2_drop_cnt_tbl_mul_p2_drop_pkt_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union mul_p2_drop_cnt_tbl_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_mul_p2_drop_cnt_tbl_get(dev_id, index, ®_val); - *value = reg_val.bf.mul_p2_drop_pkt; - return ret; -} - -sw_error_t -hppe_mul_p2_drop_cnt_tbl_mul_p2_drop_pkt_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - union mul_p2_drop_cnt_tbl_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_mul_p2_drop_cnt_tbl_get(dev_id, index, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.mul_p2_drop_pkt = value; - ret = hppe_mul_p2_drop_cnt_tbl_set(dev_id, index, ®_val); - return ret; -} - -sw_error_t -hppe_mul_p2_drop_cnt_tbl_mul_p2_drop_byte_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint64_t *value) -{ - union mul_p2_drop_cnt_tbl_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_mul_p2_drop_cnt_tbl_get(dev_id, index, ®_val); - *value = (a_uint64_t)reg_val.bf.mul_p2_drop_byte_1 << 32 | \ - reg_val.bf.mul_p2_drop_byte_0; - return ret; -} - -sw_error_t -hppe_mul_p2_drop_cnt_tbl_mul_p2_drop_byte_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint64_t value) -{ - union mul_p2_drop_cnt_tbl_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_mul_p2_drop_cnt_tbl_get(dev_id, index, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.mul_p2_drop_byte_1 = value >> 32; - reg_val.bf.mul_p2_drop_byte_0 = value & (((a_uint64_t)1<<32)-1); - ret = hppe_mul_p2_drop_cnt_tbl_set(dev_id, index, ®_val); - return ret; -} - -sw_error_t -hppe_mul_p3_drop_cnt_tbl_mul_p3_drop_pkt_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union mul_p3_drop_cnt_tbl_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_mul_p3_drop_cnt_tbl_get(dev_id, index, ®_val); - *value = reg_val.bf.mul_p3_drop_pkt; - return ret; -} - -sw_error_t -hppe_mul_p3_drop_cnt_tbl_mul_p3_drop_pkt_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - union mul_p3_drop_cnt_tbl_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_mul_p3_drop_cnt_tbl_get(dev_id, index, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.mul_p3_drop_pkt = value; - ret = hppe_mul_p3_drop_cnt_tbl_set(dev_id, index, ®_val); - return ret; -} - -sw_error_t -hppe_mul_p3_drop_cnt_tbl_mul_p3_drop_byte_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint64_t *value) -{ - union mul_p3_drop_cnt_tbl_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_mul_p3_drop_cnt_tbl_get(dev_id, index, ®_val); - *value = (a_uint64_t)reg_val.bf.mul_p3_drop_byte_1 << 32 | \ - reg_val.bf.mul_p3_drop_byte_0; - return ret; -} - -sw_error_t -hppe_mul_p3_drop_cnt_tbl_mul_p3_drop_byte_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint64_t value) -{ - union mul_p3_drop_cnt_tbl_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_mul_p3_drop_cnt_tbl_get(dev_id, index, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.mul_p3_drop_byte_1 = value >> 32; - reg_val.bf.mul_p3_drop_byte_0 = value & (((a_uint64_t)1<<32)-1); - ret = hppe_mul_p3_drop_cnt_tbl_set(dev_id, index, ®_val); - return ret; -} - -sw_error_t -hppe_mul_p4_drop_cnt_tbl_mul_p4_drop_pkt_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union mul_p4_drop_cnt_tbl_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_mul_p4_drop_cnt_tbl_get(dev_id, index, ®_val); - *value = reg_val.bf.mul_p4_drop_pkt; - return ret; -} - -sw_error_t -hppe_mul_p4_drop_cnt_tbl_mul_p4_drop_pkt_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - union mul_p4_drop_cnt_tbl_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_mul_p4_drop_cnt_tbl_get(dev_id, index, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.mul_p4_drop_pkt = value; - ret = hppe_mul_p4_drop_cnt_tbl_set(dev_id, index, ®_val); - return ret; -} - -sw_error_t -hppe_mul_p4_drop_cnt_tbl_mul_p4_drop_byte_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint64_t *value) -{ - union mul_p4_drop_cnt_tbl_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_mul_p4_drop_cnt_tbl_get(dev_id, index, ®_val); - *value = (a_uint64_t)reg_val.bf.mul_p4_drop_byte_1 << 32 | \ - reg_val.bf.mul_p4_drop_byte_0; - return ret; -} - -sw_error_t -hppe_mul_p4_drop_cnt_tbl_mul_p4_drop_byte_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint64_t value) -{ - union mul_p4_drop_cnt_tbl_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_mul_p4_drop_cnt_tbl_get(dev_id, index, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.mul_p4_drop_byte_1 = value >> 32; - reg_val.bf.mul_p4_drop_byte_0 = value & (((a_uint64_t)1<<32)-1); - ret = hppe_mul_p4_drop_cnt_tbl_set(dev_id, index, ®_val); - return ret; -} - -sw_error_t -hppe_mul_p5_drop_cnt_tbl_mul_p5_drop_byte_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint64_t *value) -{ - union mul_p5_drop_cnt_tbl_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_mul_p5_drop_cnt_tbl_get(dev_id, index, ®_val); - *value = (a_uint64_t)reg_val.bf.mul_p5_drop_byte_1 << 32 | \ - reg_val.bf.mul_p5_drop_byte_0; - return ret; -} - -sw_error_t -hppe_mul_p5_drop_cnt_tbl_mul_p5_drop_byte_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint64_t value) -{ - union mul_p5_drop_cnt_tbl_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_mul_p5_drop_cnt_tbl_get(dev_id, index, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.mul_p5_drop_byte_1 = value >> 32; - reg_val.bf.mul_p5_drop_byte_0 = value & (((a_uint64_t)1<<32)-1); - ret = hppe_mul_p5_drop_cnt_tbl_set(dev_id, index, ®_val); - return ret; -} - -sw_error_t -hppe_mul_p5_drop_cnt_tbl_mul_p5_drop_pkt_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union mul_p5_drop_cnt_tbl_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_mul_p5_drop_cnt_tbl_get(dev_id, index, ®_val); - *value = reg_val.bf.mul_p5_drop_pkt; - return ret; -} - -sw_error_t -hppe_mul_p5_drop_cnt_tbl_mul_p5_drop_pkt_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - union mul_p5_drop_cnt_tbl_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_mul_p5_drop_cnt_tbl_get(dev_id, index, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.mul_p5_drop_pkt = value; - ret = hppe_mul_p5_drop_cnt_tbl_set(dev_id, index, ®_val); - return ret; -} - -sw_error_t -hppe_mul_p6_drop_cnt_tbl_mul_p6_drop_byte_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint64_t *value) -{ - union mul_p6_drop_cnt_tbl_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_mul_p6_drop_cnt_tbl_get(dev_id, index, ®_val); - *value = (a_uint64_t)reg_val.bf.mul_p6_drop_byte_1 << 32 | \ - reg_val.bf.mul_p6_drop_byte_0; - return ret; -} - -sw_error_t -hppe_mul_p6_drop_cnt_tbl_mul_p6_drop_byte_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint64_t value) -{ - union mul_p6_drop_cnt_tbl_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_mul_p6_drop_cnt_tbl_get(dev_id, index, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.mul_p6_drop_byte_1 = value >> 32; - reg_val.bf.mul_p6_drop_byte_0 = value & (((a_uint64_t)1<<32)-1); - ret = hppe_mul_p6_drop_cnt_tbl_set(dev_id, index, ®_val); - return ret; -} - -sw_error_t -hppe_mul_p6_drop_cnt_tbl_mul_p6_drop_pkt_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union mul_p6_drop_cnt_tbl_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_mul_p6_drop_cnt_tbl_get(dev_id, index, ®_val); - *value = reg_val.bf.mul_p6_drop_pkt; - return ret; -} - -sw_error_t -hppe_mul_p6_drop_cnt_tbl_mul_p6_drop_pkt_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - union mul_p6_drop_cnt_tbl_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_mul_p6_drop_cnt_tbl_get(dev_id, index, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.mul_p6_drop_pkt = value; - ret = hppe_mul_p6_drop_cnt_tbl_set(dev_id, index, ®_val); - return ret; -} - -sw_error_t -hppe_mul_p7_drop_cnt_tbl_mul_p7_drop_pkt_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union mul_p7_drop_cnt_tbl_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_mul_p7_drop_cnt_tbl_get(dev_id, index, ®_val); - *value = reg_val.bf.mul_p7_drop_pkt; - return ret; -} - -sw_error_t -hppe_mul_p7_drop_cnt_tbl_mul_p7_drop_pkt_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - union mul_p7_drop_cnt_tbl_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_mul_p7_drop_cnt_tbl_get(dev_id, index, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.mul_p7_drop_pkt = value; - ret = hppe_mul_p7_drop_cnt_tbl_set(dev_id, index, ®_val); - return ret; -} - -sw_error_t -hppe_mul_p7_drop_cnt_tbl_mul_p7_drop_byte_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint64_t *value) -{ - union mul_p7_drop_cnt_tbl_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_mul_p7_drop_cnt_tbl_get(dev_id, index, ®_val); - *value = (a_uint64_t)reg_val.bf.mul_p7_drop_byte_1 << 32 | \ - reg_val.bf.mul_p7_drop_byte_0; - return ret; -} - -sw_error_t -hppe_mul_p7_drop_cnt_tbl_mul_p7_drop_byte_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint64_t value) -{ - union mul_p7_drop_cnt_tbl_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_mul_p7_drop_cnt_tbl_get(dev_id, index, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.mul_p7_drop_byte_1 = value >> 32; - reg_val.bf.mul_p7_drop_byte_0 = value & (((a_uint64_t)1<<32)-1); - ret = hppe_mul_p7_drop_cnt_tbl_set(dev_id, index, ®_val); - return ret; -} - -sw_error_t -hppe_uq_agg_profile_map_qid_2_agg_id_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union uq_agg_profile_map_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_uq_agg_profile_map_get(dev_id, index, ®_val); - *value = reg_val.bf.qid_2_agg_id; - return ret; -} - -sw_error_t -hppe_uq_agg_profile_map_qid_2_agg_id_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - union uq_agg_profile_map_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_uq_agg_profile_map_get(dev_id, index, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.qid_2_agg_id = value; - ret = hppe_uq_agg_profile_map_set(dev_id, index, ®_val); - return ret; -} - -sw_error_t -hppe_uq_agg_profile_map_enable_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union uq_agg_profile_map_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_uq_agg_profile_map_get(dev_id, index, ®_val); - *value = reg_val.bf.enable; - return ret; -} - -sw_error_t -hppe_uq_agg_profile_map_enable_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - union uq_agg_profile_map_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_uq_agg_profile_map_get(dev_id, index, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.enable = value; - ret = hppe_uq_agg_profile_map_set(dev_id, index, ®_val); - return ret; -} - -sw_error_t -hppe_queue_tx_counter_tbl_tx_bytes_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint64_t *value) -{ - union queue_tx_counter_tbl_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_queue_tx_counter_tbl_get(dev_id, index, ®_val); - *value = (a_uint64_t)reg_val.bf.tx_bytes_1 << 32 | \ - reg_val.bf.tx_bytes_0; - return ret; -} - -sw_error_t -hppe_queue_tx_counter_tbl_tx_bytes_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint64_t value) -{ - union queue_tx_counter_tbl_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_queue_tx_counter_tbl_get(dev_id, index, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.tx_bytes_1 = value >> 32; - reg_val.bf.tx_bytes_0 = value & (((a_uint64_t)1<<32)-1); - ret = hppe_queue_tx_counter_tbl_set(dev_id, index, ®_val); - return ret; -} - -sw_error_t -hppe_queue_tx_counter_tbl_tx_packets_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union queue_tx_counter_tbl_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_queue_tx_counter_tbl_get(dev_id, index, ®_val); - *value = reg_val.bf.tx_packets; - return ret; -} - -sw_error_t -hppe_queue_tx_counter_tbl_tx_packets_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - union queue_tx_counter_tbl_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_queue_tx_counter_tbl_get(dev_id, index, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.tx_packets = value; - ret = hppe_queue_tx_counter_tbl_set(dev_id, index, ®_val); - return ret; -} -#endif diff --git a/feeds/ipq807x/qca-ssdk/src/src/hsl/hppe/hppe_qos.c b/feeds/ipq807x/qca-ssdk/src/src/hsl/hppe/hppe_qos.c deleted file mode 100755 index f617917f3..000000000 --- a/feeds/ipq807x/qca-ssdk/src/src/hsl/hppe/hppe_qos.c +++ /dev/null @@ -1,4548 +0,0 @@ -/* - * Copyright (c) 2016-2017, The Linux Foundation. All rights reserved. - * Permission to use, copy, modify, and/or distribute this software for - * any purpose with or without fee is hereby granted, provided that the - * above copyright notice and this permission notice appear in all copies. - * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES - * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR - * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES - * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN - * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT - * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. - */ - - -/** - * @defgroup - * @{ - */ -#include "sw.h" -#include "hsl.h" -#include "hppe_reg_access.h" -#include "hppe_qos_reg.h" -#include "hppe_qos.h" - -sw_error_t -hppe_dscp_qos_group_0_get( - a_uint32_t dev_id, - a_uint32_t index, - union dscp_qos_group_0_u *value) -{ - if (index >= DSCP_QOS_GROUP_0_MAX_ENTRY) - return SW_OUT_OF_RANGE; - return hppe_reg_get( - dev_id, - IPE_L2_BASE_ADDR + DSCP_QOS_GROUP_0_ADDRESS + \ - index * DSCP_QOS_GROUP_0_INC, - &value->val); -} - -sw_error_t -hppe_dscp_qos_group_0_set( - a_uint32_t dev_id, - a_uint32_t index, - union dscp_qos_group_0_u *value) -{ - return hppe_reg_set( - dev_id, - IPE_L2_BASE_ADDR + DSCP_QOS_GROUP_0_ADDRESS + \ - index * DSCP_QOS_GROUP_0_INC, - value->val); -} - -sw_error_t -hppe_dscp_qos_group_1_get( - a_uint32_t dev_id, - a_uint32_t index, - union dscp_qos_group_1_u *value) -{ - if (index >= DSCP_QOS_GROUP_1_MAX_ENTRY) - return SW_OUT_OF_RANGE; - return hppe_reg_get( - dev_id, - IPE_L2_BASE_ADDR + DSCP_QOS_GROUP_1_ADDRESS + \ - index * DSCP_QOS_GROUP_1_INC, - &value->val); -} - -sw_error_t -hppe_dscp_qos_group_1_set( - a_uint32_t dev_id, - a_uint32_t index, - union dscp_qos_group_1_u *value) -{ - return hppe_reg_set( - dev_id, - IPE_L2_BASE_ADDR + DSCP_QOS_GROUP_1_ADDRESS + \ - index * DSCP_QOS_GROUP_1_INC, - value->val); -} - -sw_error_t -hppe_pcp_qos_group_0_get( - a_uint32_t dev_id, - a_uint32_t index, - union pcp_qos_group_0_u *value) -{ - if (index >= PCP_QOS_GROUP_0_MAX_ENTRY) - return SW_OUT_OF_RANGE; - return hppe_reg_get( - dev_id, - IPE_L2_BASE_ADDR + PCP_QOS_GROUP_0_ADDRESS + \ - index * PCP_QOS_GROUP_0_INC, - &value->val); -} - -sw_error_t -hppe_pcp_qos_group_0_set( - a_uint32_t dev_id, - a_uint32_t index, - union pcp_qos_group_0_u *value) -{ - return hppe_reg_set( - dev_id, - IPE_L2_BASE_ADDR + PCP_QOS_GROUP_0_ADDRESS + \ - index * PCP_QOS_GROUP_0_INC, - value->val); -} - -sw_error_t -hppe_pcp_qos_group_1_get( - a_uint32_t dev_id, - a_uint32_t index, - union pcp_qos_group_1_u *value) -{ - if (index >= PCP_QOS_GROUP_1_MAX_ENTRY) - return SW_OUT_OF_RANGE; - return hppe_reg_get( - dev_id, - IPE_L2_BASE_ADDR + PCP_QOS_GROUP_1_ADDRESS + \ - index * PCP_QOS_GROUP_1_INC, - &value->val); -} - -sw_error_t -hppe_pcp_qos_group_1_set( - a_uint32_t dev_id, - a_uint32_t index, - union pcp_qos_group_1_u *value) -{ - return hppe_reg_set( - dev_id, - IPE_L2_BASE_ADDR + PCP_QOS_GROUP_1_ADDRESS + \ - index * PCP_QOS_GROUP_1_INC, - value->val); -} - -sw_error_t -hppe_flow_qos_group_0_get( - a_uint32_t dev_id, - a_uint32_t index, - union flow_qos_group_0_u *value) -{ - if (index >= FLOW_QOS_GROUP_0_MAX_ENTRY) - return SW_OUT_OF_RANGE; - return hppe_reg_get( - dev_id, - IPE_L2_BASE_ADDR + FLOW_QOS_GROUP_0_ADDRESS + \ - index * FLOW_QOS_GROUP_0_INC, - &value->val); -} - -sw_error_t -hppe_flow_qos_group_0_set( - a_uint32_t dev_id, - a_uint32_t index, - union flow_qos_group_0_u *value) -{ - return hppe_reg_set( - dev_id, - IPE_L2_BASE_ADDR + FLOW_QOS_GROUP_0_ADDRESS + \ - index * FLOW_QOS_GROUP_0_INC, - value->val); -} - -sw_error_t -hppe_flow_qos_group_1_get( - a_uint32_t dev_id, - a_uint32_t index, - union flow_qos_group_1_u *value) -{ - if (index >= FLOW_QOS_GROUP_1_MAX_ENTRY) - return SW_OUT_OF_RANGE; - return hppe_reg_get( - dev_id, - IPE_L2_BASE_ADDR + FLOW_QOS_GROUP_1_ADDRESS + \ - index * FLOW_QOS_GROUP_1_INC, - &value->val); -} - -sw_error_t -hppe_flow_qos_group_1_set( - a_uint32_t dev_id, - a_uint32_t index, - union flow_qos_group_1_u *value) -{ - return hppe_reg_set( - dev_id, - IPE_L2_BASE_ADDR + FLOW_QOS_GROUP_1_ADDRESS + \ - index * FLOW_QOS_GROUP_1_INC, - value->val); -} - -sw_error_t -hppe_port_qos_ctrl_get( - a_uint32_t dev_id, - a_uint32_t index, - union port_qos_ctrl_u *value) -{ - if (index >= PORT_QOS_CTRL_MAX_ENTRY) - return SW_OUT_OF_RANGE; - return hppe_reg_get( - dev_id, - IPE_L2_BASE_ADDR + PORT_QOS_CTRL_ADDRESS + \ - index * PORT_QOS_CTRL_INC, - &value->val); -} - -sw_error_t -hppe_port_qos_ctrl_set( - a_uint32_t dev_id, - a_uint32_t index, - union port_qos_ctrl_u *value) -{ - return hppe_reg_set( - dev_id, - IPE_L2_BASE_ADDR + PORT_QOS_CTRL_ADDRESS + \ - index * PORT_QOS_CTRL_INC, - value->val); -} -#ifndef IN_QOS_MINI -sw_error_t -hppe_tdm_depth_cfg_get( - a_uint32_t dev_id, - union tdm_depth_cfg_u *value) -{ - return hppe_reg_get( - dev_id, - TRAFFIC_MANAGER_BASE_ADDR + TDM_DEPTH_CFG_ADDRESS, - &value->val); -} -#endif -sw_error_t -hppe_tdm_depth_cfg_set( - a_uint32_t dev_id, - union tdm_depth_cfg_u *value) -{ - return hppe_reg_set( - dev_id, - TRAFFIC_MANAGER_BASE_ADDR + TDM_DEPTH_CFG_ADDRESS, - value->val); -} -#ifndef IN_QOS_MINI -sw_error_t -hppe_min_max_mode_cfg_get( - a_uint32_t dev_id, - union min_max_mode_cfg_u *value) -{ - return hppe_reg_get( - dev_id, - TRAFFIC_MANAGER_BASE_ADDR + MIN_MAX_MODE_CFG_ADDRESS, - &value->val); -} - -sw_error_t -hppe_min_max_mode_cfg_set( - a_uint32_t dev_id, - union min_max_mode_cfg_u *value) -{ - return hppe_reg_set( - dev_id, - TRAFFIC_MANAGER_BASE_ADDR + MIN_MAX_MODE_CFG_ADDRESS, - value->val); -} - -sw_error_t -hppe_tm_dbg_addr_get( - a_uint32_t dev_id, - union tm_dbg_addr_u *value) -{ - return hppe_reg_get( - dev_id, - TRAFFIC_MANAGER_BASE_ADDR + TM_DBG_ADDR_ADDRESS, - &value->val); -} - -sw_error_t -hppe_tm_dbg_addr_set( - a_uint32_t dev_id, - union tm_dbg_addr_u *value) -{ - return hppe_reg_set( - dev_id, - TRAFFIC_MANAGER_BASE_ADDR + TM_DBG_ADDR_ADDRESS, - value->val); -} - -sw_error_t -hppe_tm_dbg_data_get( - a_uint32_t dev_id, - union tm_dbg_data_u *value) -{ - return hppe_reg_get( - dev_id, - TRAFFIC_MANAGER_BASE_ADDR + TM_DBG_DATA_ADDRESS, - &value->val); -} - -sw_error_t -hppe_tm_dbg_data_set( - a_uint32_t dev_id, - union tm_dbg_data_u *value) -{ - return SW_NOT_SUPPORTED; -} - -sw_error_t -hppe_eco_reserve_0_get( - a_uint32_t dev_id, - union eco_reserve_0_u *value) -{ - return hppe_reg_get( - dev_id, - TRAFFIC_MANAGER_BASE_ADDR + ECO_RESERVE_0_ADDRESS, - &value->val); -} - -sw_error_t -hppe_eco_reserve_0_set( - a_uint32_t dev_id, - union eco_reserve_0_u *value) -{ - return hppe_reg_set( - dev_id, - TRAFFIC_MANAGER_BASE_ADDR + ECO_RESERVE_0_ADDRESS, - value->val); -} - -sw_error_t -hppe_eco_reserve_1_get( - a_uint32_t dev_id, - union eco_reserve_1_u *value) -{ - return hppe_reg_get( - dev_id, - TRAFFIC_MANAGER_BASE_ADDR + ECO_RESERVE_1_ADDRESS, - &value->val); -} - -sw_error_t -hppe_eco_reserve_1_set( - a_uint32_t dev_id, - union eco_reserve_1_u *value) -{ - return hppe_reg_set( - dev_id, - TRAFFIC_MANAGER_BASE_ADDR + ECO_RESERVE_1_ADDRESS, - value->val); -} -#endif -sw_error_t -hppe_l0_flow_map_tbl_get( - a_uint32_t dev_id, - a_uint32_t index, - union l0_flow_map_tbl_u *value) -{ - if (index >= L0_FLOW_MAP_TBL_MAX_ENTRY) - return SW_OUT_OF_RANGE; - return hppe_reg_get( - dev_id, - TRAFFIC_MANAGER_BASE_ADDR + L0_FLOW_MAP_TBL_ADDRESS + \ - index * L0_FLOW_MAP_TBL_INC, - &value->val); -} - -sw_error_t -hppe_l0_flow_map_tbl_set( - a_uint32_t dev_id, - a_uint32_t index, - union l0_flow_map_tbl_u *value) -{ - return hppe_reg_set( - dev_id, - TRAFFIC_MANAGER_BASE_ADDR + L0_FLOW_MAP_TBL_ADDRESS + \ - index * L0_FLOW_MAP_TBL_INC, - value->val); -} - -sw_error_t -hppe_l0_c_sp_cfg_tbl_get( - a_uint32_t dev_id, - a_uint32_t index, - union l0_c_sp_cfg_tbl_u *value) -{ - if (index >= L0_C_SP_CFG_TBL_MAX_ENTRY) - return SW_OUT_OF_RANGE; - return hppe_reg_get( - dev_id, - TRAFFIC_MANAGER_BASE_ADDR + L0_C_SP_CFG_TBL_ADDRESS + \ - index * L0_C_SP_CFG_TBL_INC, - &value->val); -} - -sw_error_t -hppe_l0_c_sp_cfg_tbl_set( - a_uint32_t dev_id, - a_uint32_t index, - union l0_c_sp_cfg_tbl_u *value) -{ - return hppe_reg_set( - dev_id, - TRAFFIC_MANAGER_BASE_ADDR + L0_C_SP_CFG_TBL_ADDRESS + \ - index * L0_C_SP_CFG_TBL_INC, - value->val); -} - -sw_error_t -hppe_l0_e_sp_cfg_tbl_get( - a_uint32_t dev_id, - a_uint32_t index, - union l0_e_sp_cfg_tbl_u *value) -{ - if (index >= L0_E_SP_CFG_TBL_MAX_ENTRY) - return SW_OUT_OF_RANGE; - return hppe_reg_get( - dev_id, - TRAFFIC_MANAGER_BASE_ADDR + L0_E_SP_CFG_TBL_ADDRESS + \ - index * L0_E_SP_CFG_TBL_INC, - &value->val); -} - -sw_error_t -hppe_l0_e_sp_cfg_tbl_set( - a_uint32_t dev_id, - a_uint32_t index, - union l0_e_sp_cfg_tbl_u *value) -{ - return hppe_reg_set( - dev_id, - TRAFFIC_MANAGER_BASE_ADDR + L0_E_SP_CFG_TBL_ADDRESS + \ - index * L0_E_SP_CFG_TBL_INC, - value->val); -} - -sw_error_t -hppe_l0_flow_port_map_tbl_get( - a_uint32_t dev_id, - a_uint32_t index, - union l0_flow_port_map_tbl_u *value) -{ - if (index >= L0_FLOW_PORT_MAP_TBL_MAX_ENTRY) - return SW_OUT_OF_RANGE; - return hppe_reg_get( - dev_id, - TRAFFIC_MANAGER_BASE_ADDR + L0_FLOW_PORT_MAP_TBL_ADDRESS + \ - index * L0_FLOW_PORT_MAP_TBL_INC, - &value->val); -} - -sw_error_t -hppe_l0_flow_port_map_tbl_set( - a_uint32_t dev_id, - a_uint32_t index, - union l0_flow_port_map_tbl_u *value) -{ - return hppe_reg_set( - dev_id, - TRAFFIC_MANAGER_BASE_ADDR + L0_FLOW_PORT_MAP_TBL_ADDRESS + \ - index * L0_FLOW_PORT_MAP_TBL_INC, - value->val); -} -#ifndef IN_QOS_MINI -sw_error_t -hppe_l0_c_drr_head_tbl_get( - a_uint32_t dev_id, - a_uint32_t index, - union l0_c_drr_head_tbl_u *value) -{ - return hppe_reg_tbl_get( - dev_id, - TRAFFIC_MANAGER_BASE_ADDR + L0_C_DRR_HEAD_TBL_ADDRESS + \ - index * L0_C_DRR_HEAD_TBL_INC, - value->val, - 2); -} - -sw_error_t -hppe_l0_c_drr_head_tbl_set( - a_uint32_t dev_id, - a_uint32_t index, - union l0_c_drr_head_tbl_u *value) -{ - return SW_NOT_SUPPORTED; -} - -sw_error_t -hppe_l0_e_drr_head_tbl_get( - a_uint32_t dev_id, - a_uint32_t index, - union l0_e_drr_head_tbl_u *value) -{ - return hppe_reg_tbl_get( - dev_id, - TRAFFIC_MANAGER_BASE_ADDR + L0_E_DRR_HEAD_TBL_ADDRESS + \ - index * L0_E_DRR_HEAD_TBL_INC, - value->val, - 2); -} - -sw_error_t -hppe_l0_e_drr_head_tbl_set( - a_uint32_t dev_id, - a_uint32_t index, - union l0_e_drr_head_tbl_u *value) -{ - return SW_NOT_SUPPORTED; -} - -sw_error_t -hppe_l0_drr_credit_tbl_get( - a_uint32_t dev_id, - a_uint32_t index, - union l0_drr_credit_tbl_u *value) -{ - return hppe_reg_tbl_get( - dev_id, - TRAFFIC_MANAGER_BASE_ADDR + L0_DRR_CREDIT_TBL_ADDRESS + \ - index * L0_DRR_CREDIT_TBL_INC, - value->val, - 2); -} - -sw_error_t -hppe_l0_drr_credit_tbl_set( - a_uint32_t dev_id, - a_uint32_t index, - union l0_drr_credit_tbl_u *value) -{ - return SW_NOT_SUPPORTED; -} - -sw_error_t -hppe_l0_c_drr_ll_tbl_get( - a_uint32_t dev_id, - a_uint32_t index, - union l0_c_drr_ll_tbl_u *value) -{ - if (index >= L0_C_DRR_LL_TBL_MAX_ENTRY) - return SW_OUT_OF_RANGE; - return hppe_reg_get( - dev_id, - TRAFFIC_MANAGER_BASE_ADDR + L0_C_DRR_LL_TBL_ADDRESS + \ - index * L0_C_DRR_LL_TBL_INC, - &value->val); -} - -sw_error_t -hppe_l0_c_drr_ll_tbl_set( - a_uint32_t dev_id, - a_uint32_t index, - union l0_c_drr_ll_tbl_u *value) -{ - return SW_NOT_SUPPORTED; -} - -sw_error_t -hppe_l0_c_drr_reverse_ll_tbl_get( - a_uint32_t dev_id, - a_uint32_t index, - union l0_c_drr_reverse_ll_tbl_u *value) -{ - if (index >= L0_C_DRR_REVERSE_LL_TBL_MAX_ENTRY) - return SW_OUT_OF_RANGE; - return hppe_reg_get( - dev_id, - TRAFFIC_MANAGER_BASE_ADDR + L0_C_DRR_REVERSE_LL_TBL_ADDRESS + \ - index * L0_C_DRR_REVERSE_LL_TBL_INC, - &value->val); -} - -sw_error_t -hppe_l0_c_drr_reverse_ll_tbl_set( - a_uint32_t dev_id, - a_uint32_t index, - union l0_c_drr_reverse_ll_tbl_u *value) -{ - return SW_NOT_SUPPORTED; -} - -sw_error_t -hppe_l0_e_drr_ll_tbl_get( - a_uint32_t dev_id, - a_uint32_t index, - union l0_e_drr_ll_tbl_u *value) -{ - if (index >= L0_E_DRR_LL_TBL_MAX_ENTRY) - return SW_OUT_OF_RANGE; - return hppe_reg_get( - dev_id, - TRAFFIC_MANAGER_BASE_ADDR + L0_E_DRR_LL_TBL_ADDRESS + \ - index * L0_E_DRR_LL_TBL_INC, - &value->val); -} - -sw_error_t -hppe_l0_e_drr_ll_tbl_set( - a_uint32_t dev_id, - a_uint32_t index, - union l0_e_drr_ll_tbl_u *value) -{ - return SW_NOT_SUPPORTED; -} - -sw_error_t -hppe_l0_e_drr_reverse_ll_tbl_get( - a_uint32_t dev_id, - a_uint32_t index, - union l0_e_drr_reverse_ll_tbl_u *value) -{ - if (index >= L0_E_DRR_REVERSE_LL_TBL_MAX_ENTRY) - return SW_OUT_OF_RANGE; - return hppe_reg_get( - dev_id, - TRAFFIC_MANAGER_BASE_ADDR + L0_E_DRR_REVERSE_LL_TBL_ADDRESS + \ - index * L0_E_DRR_REVERSE_LL_TBL_INC, - &value->val); -} - -sw_error_t -hppe_l0_e_drr_reverse_ll_tbl_set( - a_uint32_t dev_id, - a_uint32_t index, - union l0_e_drr_reverse_ll_tbl_u *value) -{ - return SW_NOT_SUPPORTED; -} - -sw_error_t -hppe_l0_sp_entry_tbl_get( - a_uint32_t dev_id, - a_uint32_t index, - union l0_sp_entry_tbl_u *value) -{ - return hppe_reg_tbl_get( - dev_id, - TRAFFIC_MANAGER_BASE_ADDR + L0_SP_ENTRY_TBL_ADDRESS + \ - index * L0_SP_ENTRY_TBL_INC, - value->val, - 5); -} - -sw_error_t -hppe_l0_sp_entry_tbl_set( - a_uint32_t dev_id, - a_uint32_t index, - union l0_sp_entry_tbl_u *value) -{ - return SW_NOT_SUPPORTED; -} - -sw_error_t -hppe_l0_ens_q_ll_tbl_get( - a_uint32_t dev_id, - a_uint32_t index, - union l0_ens_q_ll_tbl_u *value) -{ - if (index >= L0_ENS_Q_LL_TBL_MAX_ENTRY) - return SW_OUT_OF_RANGE; - return hppe_reg_get( - dev_id, - TRAFFIC_MANAGER_BASE_ADDR + L0_ENS_Q_LL_TBL_ADDRESS + \ - index * L0_ENS_Q_LL_TBL_INC, - &value->val); -} - -sw_error_t -hppe_l0_ens_q_ll_tbl_set( - a_uint32_t dev_id, - a_uint32_t index, - union l0_ens_q_ll_tbl_u *value) -{ - return SW_NOT_SUPPORTED; -} - -sw_error_t -hppe_l0_ens_q_head_tbl_get( - a_uint32_t dev_id, - a_uint32_t index, - union l0_ens_q_head_tbl_u *value) -{ - if (index >= L0_ENS_Q_HEAD_TBL_MAX_ENTRY) - return SW_OUT_OF_RANGE; - return hppe_reg_get( - dev_id, - TRAFFIC_MANAGER_BASE_ADDR + L0_ENS_Q_HEAD_TBL_ADDRESS + \ - index * L0_ENS_Q_HEAD_TBL_INC, - &value->val); -} - -sw_error_t -hppe_l0_ens_q_head_tbl_set( - a_uint32_t dev_id, - a_uint32_t index, - union l0_ens_q_head_tbl_u *value) -{ - return SW_NOT_SUPPORTED; -} - -sw_error_t -hppe_l0_ens_q_entry_tbl_get( - a_uint32_t dev_id, - a_uint32_t index, - union l0_ens_q_entry_tbl_u *value) -{ - if (index >= L0_ENS_Q_ENTRY_TBL_MAX_ENTRY) - return SW_OUT_OF_RANGE; - return hppe_reg_get( - dev_id, - TRAFFIC_MANAGER_BASE_ADDR + L0_ENS_Q_ENTRY_TBL_ADDRESS + \ - index * L0_ENS_Q_ENTRY_TBL_INC, - &value->val); -} - -sw_error_t -hppe_l0_ens_q_entry_tbl_set( - a_uint32_t dev_id, - a_uint32_t index, - union l0_ens_q_entry_tbl_u *value) -{ - return SW_NOT_SUPPORTED; -} - -sw_error_t -hppe_l0_flow_status_tbl_get( - a_uint32_t dev_id, - a_uint32_t index, - union l0_flow_status_tbl_u *value) -{ - if (index >= L0_FLOW_STATUS_TBL_MAX_ENTRY) - return SW_OUT_OF_RANGE; - return hppe_reg_get( - dev_id, - TRAFFIC_MANAGER_BASE_ADDR + L0_FLOW_STATUS_TBL_ADDRESS + \ - index * L0_FLOW_STATUS_TBL_INC, - &value->val); -} - -sw_error_t -hppe_l0_flow_status_tbl_set( - a_uint32_t dev_id, - a_uint32_t index, - union l0_flow_status_tbl_u *value) -{ - return SW_NOT_SUPPORTED; -} -#endif -sw_error_t -hppe_ring_q_map_tbl_get( - a_uint32_t dev_id, - a_uint32_t index, - union ring_q_map_tbl_u *value) -{ - return hppe_reg_tbl_get( - dev_id, - TRAFFIC_MANAGER_BASE_ADDR + RING_Q_MAP_TBL_ADDRESS + \ - index * RING_Q_MAP_TBL_INC, - value->val, - 10); -} - -sw_error_t -hppe_ring_q_map_tbl_set( - a_uint32_t dev_id, - a_uint32_t index, - union ring_q_map_tbl_u *value) -{ - return hppe_reg_tbl_set( - dev_id, - TRAFFIC_MANAGER_BASE_ADDR + RING_Q_MAP_TBL_ADDRESS + \ - index * RING_Q_MAP_TBL_INC, - value->val, - 10); -} -#ifndef IN_QOS_MINI -sw_error_t -hppe_rfc_block_tbl_get( - a_uint32_t dev_id, - a_uint32_t index, - union rfc_block_tbl_u *value) -{ - if (index >= RFC_BLOCK_TBL_MAX_ENTRY) - return SW_OUT_OF_RANGE; - return hppe_reg_get( - dev_id, - TRAFFIC_MANAGER_BASE_ADDR + RFC_BLOCK_TBL_ADDRESS + \ - index * RFC_BLOCK_TBL_INC, - &value->val); -} - -sw_error_t -hppe_rfc_block_tbl_set( - a_uint32_t dev_id, - a_uint32_t index, - union rfc_block_tbl_u *value) -{ - return SW_NOT_SUPPORTED; -} - -sw_error_t -hppe_rfc_status_tbl_get( - a_uint32_t dev_id, - a_uint32_t index, - union rfc_status_tbl_u *value) -{ - if (index >= RFC_STATUS_TBL_MAX_ENTRY) - return SW_OUT_OF_RANGE; - return hppe_reg_get( - dev_id, - TRAFFIC_MANAGER_BASE_ADDR + RFC_STATUS_TBL_ADDRESS + \ - index * RFC_STATUS_TBL_INC, - &value->val); -} - -sw_error_t -hppe_rfc_status_tbl_set( - a_uint32_t dev_id, - a_uint32_t index, - union rfc_status_tbl_u *value) -{ - return SW_NOT_SUPPORTED; -} -#endif -sw_error_t -hppe_deq_dis_tbl_get( - a_uint32_t dev_id, - a_uint32_t index, - union deq_dis_tbl_u *value) -{ - if (index >= DEQ_DIS_TBL_MAX_ENTRY) - return SW_OUT_OF_RANGE; - return hppe_reg_get( - dev_id, - TRAFFIC_MANAGER_BASE_ADDR + DEQ_DIS_TBL_ADDRESS + \ - index * DEQ_DIS_TBL_INC, - &value->val); -} - -sw_error_t -hppe_deq_dis_tbl_set( - a_uint32_t dev_id, - a_uint32_t index, - union deq_dis_tbl_u *value) -{ - return hppe_reg_set( - dev_id, - TRAFFIC_MANAGER_BASE_ADDR + DEQ_DIS_TBL_ADDRESS + \ - index * DEQ_DIS_TBL_INC, - value->val); -} - -sw_error_t -hppe_l1_flow_map_tbl_get( - a_uint32_t dev_id, - a_uint32_t index, - union l1_flow_map_tbl_u *value) -{ - if (index >= L1_FLOW_MAP_TBL_MAX_ENTRY) - return SW_OUT_OF_RANGE; - return hppe_reg_get( - dev_id, - TRAFFIC_MANAGER_BASE_ADDR + L1_FLOW_MAP_TBL_ADDRESS + \ - index * L1_FLOW_MAP_TBL_INC, - &value->val); -} - -sw_error_t -hppe_l1_flow_map_tbl_set( - a_uint32_t dev_id, - a_uint32_t index, - union l1_flow_map_tbl_u *value) -{ - return hppe_reg_set( - dev_id, - TRAFFIC_MANAGER_BASE_ADDR + L1_FLOW_MAP_TBL_ADDRESS + \ - index * L1_FLOW_MAP_TBL_INC, - value->val); -} - -sw_error_t -hppe_l1_c_sp_cfg_tbl_get( - a_uint32_t dev_id, - a_uint32_t index, - union l1_c_sp_cfg_tbl_u *value) -{ - if (index >= L1_C_SP_CFG_TBL_MAX_ENTRY) - return SW_OUT_OF_RANGE; - return hppe_reg_get( - dev_id, - TRAFFIC_MANAGER_BASE_ADDR + L1_C_SP_CFG_TBL_ADDRESS + \ - index * L1_C_SP_CFG_TBL_INC, - &value->val); -} - -sw_error_t -hppe_l1_c_sp_cfg_tbl_set( - a_uint32_t dev_id, - a_uint32_t index, - union l1_c_sp_cfg_tbl_u *value) -{ - return hppe_reg_set( - dev_id, - TRAFFIC_MANAGER_BASE_ADDR + L1_C_SP_CFG_TBL_ADDRESS + \ - index * L1_C_SP_CFG_TBL_INC, - value->val); -} - -sw_error_t -hppe_l1_e_sp_cfg_tbl_get( - a_uint32_t dev_id, - a_uint32_t index, - union l1_e_sp_cfg_tbl_u *value) -{ - if (index >= L1_E_SP_CFG_TBL_MAX_ENTRY) - return SW_OUT_OF_RANGE; - return hppe_reg_get( - dev_id, - TRAFFIC_MANAGER_BASE_ADDR + L1_E_SP_CFG_TBL_ADDRESS + \ - index * L1_E_SP_CFG_TBL_INC, - &value->val); -} - -sw_error_t -hppe_l1_e_sp_cfg_tbl_set( - a_uint32_t dev_id, - a_uint32_t index, - union l1_e_sp_cfg_tbl_u *value) -{ - return hppe_reg_set( - dev_id, - TRAFFIC_MANAGER_BASE_ADDR + L1_E_SP_CFG_TBL_ADDRESS + \ - index * L1_E_SP_CFG_TBL_INC, - value->val); -} - -sw_error_t -hppe_l1_flow_port_map_tbl_get( - a_uint32_t dev_id, - a_uint32_t index, - union l1_flow_port_map_tbl_u *value) -{ - if (index >= L1_FLOW_PORT_MAP_TBL_MAX_ENTRY) - return SW_OUT_OF_RANGE; - return hppe_reg_get( - dev_id, - TRAFFIC_MANAGER_BASE_ADDR + L1_FLOW_PORT_MAP_TBL_ADDRESS + \ - index * L1_FLOW_PORT_MAP_TBL_INC, - &value->val); -} - -sw_error_t -hppe_l1_flow_port_map_tbl_set( - a_uint32_t dev_id, - a_uint32_t index, - union l1_flow_port_map_tbl_u *value) -{ - return hppe_reg_set( - dev_id, - TRAFFIC_MANAGER_BASE_ADDR + L1_FLOW_PORT_MAP_TBL_ADDRESS + \ - index * L1_FLOW_PORT_MAP_TBL_INC, - value->val); -} - -sw_error_t -hppe_l1_c_drr_head_tbl_get( - a_uint32_t dev_id, - a_uint32_t index, - union l1_c_drr_head_tbl_u *value) -{ - return hppe_reg_tbl_get( - dev_id, - TRAFFIC_MANAGER_BASE_ADDR + L1_C_DRR_HEAD_TBL_ADDRESS + \ - index * L1_C_DRR_HEAD_TBL_INC, - value->val, - 2); -} -#ifndef IN_QOS_MINI -sw_error_t -hppe_l1_c_drr_head_tbl_set( - a_uint32_t dev_id, - a_uint32_t index, - union l1_c_drr_head_tbl_u *value) -{ - return SW_NOT_SUPPORTED; -} - -sw_error_t -hppe_l1_e_drr_head_tbl_get( - a_uint32_t dev_id, - a_uint32_t index, - union l1_e_drr_head_tbl_u *value) -{ - return hppe_reg_tbl_get( - dev_id, - TRAFFIC_MANAGER_BASE_ADDR + L1_E_DRR_HEAD_TBL_ADDRESS + \ - index * L1_E_DRR_HEAD_TBL_INC, - value->val, - 2); -} - -sw_error_t -hppe_l1_e_drr_head_tbl_set( - a_uint32_t dev_id, - a_uint32_t index, - union l1_e_drr_head_tbl_u *value) -{ - return SW_NOT_SUPPORTED; -} - -sw_error_t -hppe_l1_drr_credit_tbl_get( - a_uint32_t dev_id, - a_uint32_t index, - union l1_drr_credit_tbl_u *value) -{ - return hppe_reg_tbl_get( - dev_id, - TRAFFIC_MANAGER_BASE_ADDR + L1_DRR_CREDIT_TBL_ADDRESS + \ - index * L1_DRR_CREDIT_TBL_INC, - value->val, - 2); -} - -sw_error_t -hppe_l1_drr_credit_tbl_set( - a_uint32_t dev_id, - a_uint32_t index, - union l1_drr_credit_tbl_u *value) -{ - return SW_NOT_SUPPORTED; -} - -sw_error_t -hppe_l1_c_drr_ll_tbl_get( - a_uint32_t dev_id, - a_uint32_t index, - union l1_c_drr_ll_tbl_u *value) -{ - if (index >= L1_C_DRR_LL_TBL_MAX_ENTRY) - return SW_OUT_OF_RANGE; - return hppe_reg_get( - dev_id, - TRAFFIC_MANAGER_BASE_ADDR + L1_C_DRR_LL_TBL_ADDRESS + \ - index * L1_C_DRR_LL_TBL_INC, - &value->val); -} - -sw_error_t -hppe_l1_c_drr_ll_tbl_set( - a_uint32_t dev_id, - a_uint32_t index, - union l1_c_drr_ll_tbl_u *value) -{ - return SW_NOT_SUPPORTED; -} - -sw_error_t -hppe_l1_c_drr_reverse_ll_tbl_get( - a_uint32_t dev_id, - a_uint32_t index, - union l1_c_drr_reverse_ll_tbl_u *value) -{ - if (index >= L1_C_DRR_REVERSE_LL_TBL_MAX_ENTRY) - return SW_OUT_OF_RANGE; - return hppe_reg_get( - dev_id, - TRAFFIC_MANAGER_BASE_ADDR + L1_C_DRR_REVERSE_LL_TBL_ADDRESS + \ - index * L1_C_DRR_REVERSE_LL_TBL_INC, - &value->val); -} - -sw_error_t -hppe_l1_c_drr_reverse_ll_tbl_set( - a_uint32_t dev_id, - a_uint32_t index, - union l1_c_drr_reverse_ll_tbl_u *value) -{ - return SW_NOT_SUPPORTED; -} - -sw_error_t -hppe_l1_e_drr_ll_tbl_get( - a_uint32_t dev_id, - a_uint32_t index, - union l1_e_drr_ll_tbl_u *value) -{ - if (index >= L1_E_DRR_LL_TBL_MAX_ENTRY) - return SW_OUT_OF_RANGE; - return hppe_reg_get( - dev_id, - TRAFFIC_MANAGER_BASE_ADDR + L1_E_DRR_LL_TBL_ADDRESS + \ - index * L1_E_DRR_LL_TBL_INC, - &value->val); -} - -sw_error_t -hppe_l1_e_drr_ll_tbl_set( - a_uint32_t dev_id, - a_uint32_t index, - union l1_e_drr_ll_tbl_u *value) -{ - return SW_NOT_SUPPORTED; -} - -sw_error_t -hppe_l1_e_drr_reverse_ll_tbl_get( - a_uint32_t dev_id, - a_uint32_t index, - union l1_e_drr_reverse_ll_tbl_u *value) -{ - if (index >= L1_E_DRR_REVERSE_LL_TBL_MAX_ENTRY) - return SW_OUT_OF_RANGE; - return hppe_reg_get( - dev_id, - TRAFFIC_MANAGER_BASE_ADDR + L1_E_DRR_REVERSE_LL_TBL_ADDRESS + \ - index * L1_E_DRR_REVERSE_LL_TBL_INC, - &value->val); -} - -sw_error_t -hppe_l1_e_drr_reverse_ll_tbl_set( - a_uint32_t dev_id, - a_uint32_t index, - union l1_e_drr_reverse_ll_tbl_u *value) -{ - return SW_NOT_SUPPORTED; -} - -sw_error_t -hppe_l1_a_flow_entry_tbl_get( - a_uint32_t dev_id, - a_uint32_t index, - union l1_a_flow_entry_tbl_u *value) -{ - if (index >= L1_A_FLOW_ENTRY_TBL_MAX_ENTRY) - return SW_OUT_OF_RANGE; - return hppe_reg_get( - dev_id, - TRAFFIC_MANAGER_BASE_ADDR + L1_A_FLOW_ENTRY_TBL_ADDRESS + \ - index * L1_A_FLOW_ENTRY_TBL_INC, - &value->val); -} - -sw_error_t -hppe_l1_a_flow_entry_tbl_set( - a_uint32_t dev_id, - a_uint32_t index, - union l1_a_flow_entry_tbl_u *value) -{ - return SW_NOT_SUPPORTED; -} - -sw_error_t -hppe_l1_b_flow_entry_tbl_get( - a_uint32_t dev_id, - a_uint32_t index, - union l1_b_flow_entry_tbl_u *value) -{ - if (index >= L1_B_FLOW_ENTRY_TBL_MAX_ENTRY) - return SW_OUT_OF_RANGE; - return hppe_reg_get( - dev_id, - TRAFFIC_MANAGER_BASE_ADDR + L1_B_FLOW_ENTRY_TBL_ADDRESS + \ - index * L1_B_FLOW_ENTRY_TBL_INC, - &value->val); -} - -sw_error_t -hppe_l1_b_flow_entry_tbl_set( - a_uint32_t dev_id, - a_uint32_t index, - union l1_b_flow_entry_tbl_u *value) -{ - return SW_NOT_SUPPORTED; -} - -sw_error_t -hppe_l1_sp_entry_tbl_get( - a_uint32_t dev_id, - a_uint32_t index, - union l1_sp_entry_tbl_u *value) -{ - return hppe_reg_tbl_get( - dev_id, - TRAFFIC_MANAGER_BASE_ADDR + L1_SP_ENTRY_TBL_ADDRESS + \ - index * L1_SP_ENTRY_TBL_INC, - value->val, - 9); -} - -sw_error_t -hppe_l1_sp_entry_tbl_set( - a_uint32_t dev_id, - a_uint32_t index, - union l1_sp_entry_tbl_u *value) -{ - return SW_NOT_SUPPORTED; -} - -sw_error_t -hppe_l1_ens_q_ll_tbl_get( - a_uint32_t dev_id, - a_uint32_t index, - union l1_ens_q_ll_tbl_u *value) -{ - if (index >= L1_ENS_Q_LL_TBL_MAX_ENTRY) - return SW_OUT_OF_RANGE; - return hppe_reg_get( - dev_id, - TRAFFIC_MANAGER_BASE_ADDR + L1_ENS_Q_LL_TBL_ADDRESS + \ - index * L1_ENS_Q_LL_TBL_INC, - &value->val); -} - -sw_error_t -hppe_l1_ens_q_ll_tbl_set( - a_uint32_t dev_id, - a_uint32_t index, - union l1_ens_q_ll_tbl_u *value) -{ - return SW_NOT_SUPPORTED; -} - -sw_error_t -hppe_l1_ens_q_head_tbl_get( - a_uint32_t dev_id, - a_uint32_t index, - union l1_ens_q_head_tbl_u *value) -{ - if (index >= L1_ENS_Q_HEAD_TBL_MAX_ENTRY) - return SW_OUT_OF_RANGE; - return hppe_reg_get( - dev_id, - TRAFFIC_MANAGER_BASE_ADDR + L1_ENS_Q_HEAD_TBL_ADDRESS + \ - index * L1_ENS_Q_HEAD_TBL_INC, - &value->val); -} - -sw_error_t -hppe_l1_ens_q_head_tbl_set( - a_uint32_t dev_id, - a_uint32_t index, - union l1_ens_q_head_tbl_u *value) -{ - return SW_NOT_SUPPORTED; -} - -sw_error_t -hppe_l1_ens_q_entry_tbl_get( - a_uint32_t dev_id, - a_uint32_t index, - union l1_ens_q_entry_tbl_u *value) -{ - if (index >= L1_ENS_Q_ENTRY_TBL_MAX_ENTRY) - return SW_OUT_OF_RANGE; - return hppe_reg_get( - dev_id, - TRAFFIC_MANAGER_BASE_ADDR + L1_ENS_Q_ENTRY_TBL_ADDRESS + \ - index * L1_ENS_Q_ENTRY_TBL_INC, - &value->val); -} - -sw_error_t -hppe_l1_ens_q_entry_tbl_set( - a_uint32_t dev_id, - a_uint32_t index, - union l1_ens_q_entry_tbl_u *value) -{ - return SW_NOT_SUPPORTED; -} - -sw_error_t -hppe_l1_flow_status_tbl_get( - a_uint32_t dev_id, - a_uint32_t index, - union l1_flow_status_tbl_u *value) -{ - if (index >= L1_FLOW_STATUS_TBL_MAX_ENTRY) - return SW_OUT_OF_RANGE; - return hppe_reg_get( - dev_id, - TRAFFIC_MANAGER_BASE_ADDR + L1_FLOW_STATUS_TBL_ADDRESS + \ - index * L1_FLOW_STATUS_TBL_INC, - &value->val); -} - -sw_error_t -hppe_l1_flow_status_tbl_set( - a_uint32_t dev_id, - a_uint32_t index, - union l1_flow_status_tbl_u *value) -{ - return SW_NOT_SUPPORTED; -} - -sw_error_t -hppe_psch_tdm_cfg_tbl_get( - a_uint32_t dev_id, - a_uint32_t index, - union psch_tdm_cfg_tbl_u *value) -{ - if (index >= PSCH_TDM_CFG_TBL_MAX_ENTRY) - return SW_OUT_OF_RANGE; - return hppe_reg_get( - dev_id, - TRAFFIC_MANAGER_BASE_ADDR + PSCH_TDM_CFG_TBL_ADDRESS + \ - index * PSCH_TDM_CFG_TBL_INC, - &value->val); -} -#endif -sw_error_t -hppe_psch_tdm_cfg_tbl_set( - a_uint32_t dev_id, - a_uint32_t index, - union psch_tdm_cfg_tbl_u *value) -{ - return hppe_reg_set( - dev_id, - TRAFFIC_MANAGER_BASE_ADDR + PSCH_TDM_CFG_TBL_ADDRESS + \ - index * PSCH_TDM_CFG_TBL_INC, - value->val); -} -#ifndef IN_QOS_MINI -sw_error_t -hppe_tdm_depth_cfg_tdm_depth_get( - a_uint32_t dev_id, - a_uint32_t *value) -{ - union tdm_depth_cfg_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_tdm_depth_cfg_get(dev_id, ®_val); - *value = reg_val.bf.tdm_depth; - return ret; -} - -sw_error_t -hppe_tdm_depth_cfg_tdm_depth_set( - a_uint32_t dev_id, - a_uint32_t value) -{ - union tdm_depth_cfg_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_tdm_depth_cfg_get(dev_id, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.tdm_depth = value; - ret = hppe_tdm_depth_cfg_set(dev_id, ®_val); - return ret; -} - -sw_error_t -hppe_min_max_mode_cfg_min_max_mode_get( - a_uint32_t dev_id, - a_uint32_t *value) -{ - union min_max_mode_cfg_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_min_max_mode_cfg_get(dev_id, ®_val); - *value = reg_val.bf.min_max_mode; - return ret; -} - -sw_error_t -hppe_min_max_mode_cfg_min_max_mode_set( - a_uint32_t dev_id, - a_uint32_t value) -{ - union min_max_mode_cfg_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_min_max_mode_cfg_get(dev_id, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.min_max_mode = value; - ret = hppe_min_max_mode_cfg_set(dev_id, ®_val); - return ret; -} - -sw_error_t -hppe_tm_dbg_addr_dbg_addr_get( - a_uint32_t dev_id, - a_uint32_t *value) -{ - union tm_dbg_addr_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_tm_dbg_addr_get(dev_id, ®_val); - *value = reg_val.bf.dbg_addr; - return ret; -} - -sw_error_t -hppe_tm_dbg_addr_dbg_addr_set( - a_uint32_t dev_id, - a_uint32_t value) -{ - union tm_dbg_addr_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_tm_dbg_addr_get(dev_id, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.dbg_addr = value; - ret = hppe_tm_dbg_addr_set(dev_id, ®_val); - return ret; -} - -sw_error_t -hppe_tm_dbg_data_dbg_data_get( - a_uint32_t dev_id, - a_uint32_t *value) -{ - union tm_dbg_data_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_tm_dbg_data_get(dev_id, ®_val); - *value = reg_val.bf.dbg_data; - return ret; -} - -sw_error_t -hppe_tm_dbg_data_dbg_data_set( - a_uint32_t dev_id, - a_uint32_t value) -{ - return SW_NOT_SUPPORTED; -} - -sw_error_t -hppe_eco_reserve_0_eco_res_0_get( - a_uint32_t dev_id, - a_uint32_t *value) -{ - union eco_reserve_0_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_eco_reserve_0_get(dev_id, ®_val); - *value = reg_val.bf.eco_res_0; - return ret; -} - -sw_error_t -hppe_eco_reserve_0_eco_res_0_set( - a_uint32_t dev_id, - a_uint32_t value) -{ - union eco_reserve_0_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_eco_reserve_0_get(dev_id, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.eco_res_0 = value; - ret = hppe_eco_reserve_0_set(dev_id, ®_val); - return ret; -} - -sw_error_t -hppe_eco_reserve_1_eco_res_1_get( - a_uint32_t dev_id, - a_uint32_t *value) -{ - union eco_reserve_1_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_eco_reserve_1_get(dev_id, ®_val); - *value = reg_val.bf.eco_res_1; - return ret; -} - -sw_error_t -hppe_eco_reserve_1_eco_res_1_set( - a_uint32_t dev_id, - a_uint32_t value) -{ - union eco_reserve_1_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_eco_reserve_1_get(dev_id, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.eco_res_1 = value; - ret = hppe_eco_reserve_1_set(dev_id, ®_val); - return ret; -} - -sw_error_t -hppe_l0_flow_map_tbl_e_pri_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union l0_flow_map_tbl_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_l0_flow_map_tbl_get(dev_id, index, ®_val); - *value = reg_val.bf.e_pri; - return ret; -} - -sw_error_t -hppe_l0_flow_map_tbl_e_pri_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - union l0_flow_map_tbl_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_l0_flow_map_tbl_get(dev_id, index, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.e_pri = value; - ret = hppe_l0_flow_map_tbl_set(dev_id, index, ®_val); - return ret; -} - -sw_error_t -hppe_l0_flow_map_tbl_c_pri_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union l0_flow_map_tbl_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_l0_flow_map_tbl_get(dev_id, index, ®_val); - *value = reg_val.bf.c_pri; - return ret; -} - -sw_error_t -hppe_l0_flow_map_tbl_c_pri_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - union l0_flow_map_tbl_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_l0_flow_map_tbl_get(dev_id, index, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.c_pri = value; - ret = hppe_l0_flow_map_tbl_set(dev_id, index, ®_val); - return ret; -} - -sw_error_t -hppe_l0_flow_map_tbl_e_drr_wt_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union l0_flow_map_tbl_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_l0_flow_map_tbl_get(dev_id, index, ®_val); - *value = reg_val.bf.e_drr_wt; - return ret; -} - -sw_error_t -hppe_l0_flow_map_tbl_e_drr_wt_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - union l0_flow_map_tbl_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_l0_flow_map_tbl_get(dev_id, index, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.e_drr_wt = value; - ret = hppe_l0_flow_map_tbl_set(dev_id, index, ®_val); - return ret; -} - -sw_error_t -hppe_l0_flow_map_tbl_c_drr_wt_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union l0_flow_map_tbl_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_l0_flow_map_tbl_get(dev_id, index, ®_val); - *value = reg_val.bf.c_drr_wt; - return ret; -} - -sw_error_t -hppe_l0_flow_map_tbl_c_drr_wt_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - union l0_flow_map_tbl_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_l0_flow_map_tbl_get(dev_id, index, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.c_drr_wt = value; - ret = hppe_l0_flow_map_tbl_set(dev_id, index, ®_val); - return ret; -} - -sw_error_t -hppe_l0_flow_map_tbl_sp_id_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union l0_flow_map_tbl_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_l0_flow_map_tbl_get(dev_id, index, ®_val); - *value = reg_val.bf.sp_id; - return ret; -} - -sw_error_t -hppe_l0_flow_map_tbl_sp_id_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - union l0_flow_map_tbl_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_l0_flow_map_tbl_get(dev_id, index, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.sp_id = value; - ret = hppe_l0_flow_map_tbl_set(dev_id, index, ®_val); - return ret; -} - -sw_error_t -hppe_l0_c_sp_cfg_tbl_drr_credit_unit_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union l0_c_sp_cfg_tbl_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_l0_c_sp_cfg_tbl_get(dev_id, index, ®_val); - *value = reg_val.bf.drr_credit_unit; - return ret; -} - -sw_error_t -hppe_l0_c_sp_cfg_tbl_drr_credit_unit_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - union l0_c_sp_cfg_tbl_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_l0_c_sp_cfg_tbl_get(dev_id, index, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.drr_credit_unit = value; - ret = hppe_l0_c_sp_cfg_tbl_set(dev_id, index, ®_val); - return ret; -} - -sw_error_t -hppe_l0_c_sp_cfg_tbl_drr_id_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union l0_c_sp_cfg_tbl_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_l0_c_sp_cfg_tbl_get(dev_id, index, ®_val); - *value = reg_val.bf.drr_id; - return ret; -} - -sw_error_t -hppe_l0_c_sp_cfg_tbl_drr_id_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - union l0_c_sp_cfg_tbl_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_l0_c_sp_cfg_tbl_get(dev_id, index, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.drr_id = value; - ret = hppe_l0_c_sp_cfg_tbl_set(dev_id, index, ®_val); - return ret; -} - -sw_error_t -hppe_l0_e_sp_cfg_tbl_drr_credit_unit_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union l0_e_sp_cfg_tbl_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_l0_e_sp_cfg_tbl_get(dev_id, index, ®_val); - *value = reg_val.bf.drr_credit_unit; - return ret; -} - -sw_error_t -hppe_l0_e_sp_cfg_tbl_drr_credit_unit_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - union l0_e_sp_cfg_tbl_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_l0_e_sp_cfg_tbl_get(dev_id, index, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.drr_credit_unit = value; - ret = hppe_l0_e_sp_cfg_tbl_set(dev_id, index, ®_val); - return ret; -} - -sw_error_t -hppe_l0_e_sp_cfg_tbl_drr_id_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union l0_e_sp_cfg_tbl_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_l0_e_sp_cfg_tbl_get(dev_id, index, ®_val); - *value = reg_val.bf.drr_id; - return ret; -} - -sw_error_t -hppe_l0_e_sp_cfg_tbl_drr_id_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - union l0_e_sp_cfg_tbl_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_l0_e_sp_cfg_tbl_get(dev_id, index, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.drr_id = value; - ret = hppe_l0_e_sp_cfg_tbl_set(dev_id, index, ®_val); - return ret; -} - -sw_error_t -hppe_l0_flow_port_map_tbl_port_num_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union l0_flow_port_map_tbl_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_l0_flow_port_map_tbl_get(dev_id, index, ®_val); - *value = reg_val.bf.port_num; - return ret; -} - -sw_error_t -hppe_l0_flow_port_map_tbl_port_num_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - union l0_flow_port_map_tbl_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_l0_flow_port_map_tbl_get(dev_id, index, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.port_num = value; - ret = hppe_l0_flow_port_map_tbl_set(dev_id, index, ®_val); - return ret; -} - -sw_error_t -hppe_l0_c_drr_head_tbl_backup_head_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union l0_c_drr_head_tbl_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_l0_c_drr_head_tbl_get(dev_id, index, ®_val); - *value = reg_val.bf.backup_head; - return ret; -} - -sw_error_t -hppe_l0_c_drr_head_tbl_backup_head_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - return SW_NOT_SUPPORTED; -} - -sw_error_t -hppe_l0_c_drr_head_tbl_active_vld_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union l0_c_drr_head_tbl_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_l0_c_drr_head_tbl_get(dev_id, index, ®_val); - *value = reg_val.bf.active_vld; - return ret; -} - -sw_error_t -hppe_l0_c_drr_head_tbl_active_vld_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - return SW_NOT_SUPPORTED; -} - -sw_error_t -hppe_l0_c_drr_head_tbl_backup_max_n_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union l0_c_drr_head_tbl_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_l0_c_drr_head_tbl_get(dev_id, index, ®_val); - *value = reg_val.bf.backup_max_n; - return ret; -} - -sw_error_t -hppe_l0_c_drr_head_tbl_backup_max_n_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - return SW_NOT_SUPPORTED; -} - -sw_error_t -hppe_l0_c_drr_head_tbl_active_tail_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union l0_c_drr_head_tbl_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_l0_c_drr_head_tbl_get(dev_id, index, ®_val); - *value = reg_val.bf.active_tail_1 << 8 | \ - reg_val.bf.active_tail_0; - return ret; -} - -sw_error_t -hppe_l0_c_drr_head_tbl_active_tail_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - return SW_NOT_SUPPORTED; -} - -sw_error_t -hppe_l0_c_drr_head_tbl_active_head_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union l0_c_drr_head_tbl_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_l0_c_drr_head_tbl_get(dev_id, index, ®_val); - *value = reg_val.bf.active_head; - return ret; -} - -sw_error_t -hppe_l0_c_drr_head_tbl_active_head_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - return SW_NOT_SUPPORTED; -} - -sw_error_t -hppe_l0_c_drr_head_tbl_backup_vld_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union l0_c_drr_head_tbl_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_l0_c_drr_head_tbl_get(dev_id, index, ®_val); - *value = reg_val.bf.backup_vld; - return ret; -} - -sw_error_t -hppe_l0_c_drr_head_tbl_backup_vld_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - return SW_NOT_SUPPORTED; -} - -sw_error_t -hppe_l0_c_drr_head_tbl_active_max_n_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union l0_c_drr_head_tbl_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_l0_c_drr_head_tbl_get(dev_id, index, ®_val); - *value = reg_val.bf.active_max_n; - return ret; -} - -sw_error_t -hppe_l0_c_drr_head_tbl_active_max_n_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - return SW_NOT_SUPPORTED; -} - -sw_error_t -hppe_l0_c_drr_head_tbl_backup_tail_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union l0_c_drr_head_tbl_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_l0_c_drr_head_tbl_get(dev_id, index, ®_val); - *value = reg_val.bf.backup_tail; - return ret; -} - -sw_error_t -hppe_l0_c_drr_head_tbl_backup_tail_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - return SW_NOT_SUPPORTED; -} - -sw_error_t -hppe_l0_e_drr_head_tbl_backup_head_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union l0_e_drr_head_tbl_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_l0_e_drr_head_tbl_get(dev_id, index, ®_val); - *value = reg_val.bf.backup_head; - return ret; -} - -sw_error_t -hppe_l0_e_drr_head_tbl_backup_head_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - return SW_NOT_SUPPORTED; -} - -sw_error_t -hppe_l0_e_drr_head_tbl_active_vld_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union l0_e_drr_head_tbl_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_l0_e_drr_head_tbl_get(dev_id, index, ®_val); - *value = reg_val.bf.active_vld; - return ret; -} - -sw_error_t -hppe_l0_e_drr_head_tbl_active_vld_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - return SW_NOT_SUPPORTED; -} - -sw_error_t -hppe_l0_e_drr_head_tbl_backup_max_n_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union l0_e_drr_head_tbl_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_l0_e_drr_head_tbl_get(dev_id, index, ®_val); - *value = reg_val.bf.backup_max_n; - return ret; -} - -sw_error_t -hppe_l0_e_drr_head_tbl_backup_max_n_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - return SW_NOT_SUPPORTED; -} - -sw_error_t -hppe_l0_e_drr_head_tbl_active_tail_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union l0_e_drr_head_tbl_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_l0_e_drr_head_tbl_get(dev_id, index, ®_val); - *value = reg_val.bf.active_tail_1 << 8 | \ - reg_val.bf.active_tail_0; - return ret; -} - -sw_error_t -hppe_l0_e_drr_head_tbl_active_tail_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - return SW_NOT_SUPPORTED; -} - -sw_error_t -hppe_l0_e_drr_head_tbl_active_head_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union l0_e_drr_head_tbl_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_l0_e_drr_head_tbl_get(dev_id, index, ®_val); - *value = reg_val.bf.active_head; - return ret; -} - -sw_error_t -hppe_l0_e_drr_head_tbl_active_head_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - return SW_NOT_SUPPORTED; -} - -sw_error_t -hppe_l0_e_drr_head_tbl_backup_vld_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union l0_e_drr_head_tbl_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_l0_e_drr_head_tbl_get(dev_id, index, ®_val); - *value = reg_val.bf.backup_vld; - return ret; -} - -sw_error_t -hppe_l0_e_drr_head_tbl_backup_vld_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - return SW_NOT_SUPPORTED; -} - -sw_error_t -hppe_l0_e_drr_head_tbl_active_max_n_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union l0_e_drr_head_tbl_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_l0_e_drr_head_tbl_get(dev_id, index, ®_val); - *value = reg_val.bf.active_max_n; - return ret; -} - -sw_error_t -hppe_l0_e_drr_head_tbl_active_max_n_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - return SW_NOT_SUPPORTED; -} - -sw_error_t -hppe_l0_e_drr_head_tbl_backup_tail_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union l0_e_drr_head_tbl_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_l0_e_drr_head_tbl_get(dev_id, index, ®_val); - *value = reg_val.bf.backup_tail; - return ret; -} - -sw_error_t -hppe_l0_e_drr_head_tbl_backup_tail_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - return SW_NOT_SUPPORTED; -} - -sw_error_t -hppe_l0_drr_credit_tbl_e_drr_credit_neg_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union l0_drr_credit_tbl_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_l0_drr_credit_tbl_get(dev_id, index, ®_val); - *value = reg_val.bf.e_drr_credit_neg; - return ret; -} - -sw_error_t -hppe_l0_drr_credit_tbl_e_drr_credit_neg_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - return SW_NOT_SUPPORTED; -} - -sw_error_t -hppe_l0_drr_credit_tbl_c_drr_credit_neg_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union l0_drr_credit_tbl_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_l0_drr_credit_tbl_get(dev_id, index, ®_val); - *value = reg_val.bf.c_drr_credit_neg; - return ret; -} - -sw_error_t -hppe_l0_drr_credit_tbl_c_drr_credit_neg_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - return SW_NOT_SUPPORTED; -} - -sw_error_t -hppe_l0_drr_credit_tbl_c_drr_credit_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union l0_drr_credit_tbl_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_l0_drr_credit_tbl_get(dev_id, index, ®_val); - *value = reg_val.bf.c_drr_credit; - return ret; -} - -sw_error_t -hppe_l0_drr_credit_tbl_c_drr_credit_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - return SW_NOT_SUPPORTED; -} - -sw_error_t -hppe_l0_drr_credit_tbl_e_drr_credit_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union l0_drr_credit_tbl_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_l0_drr_credit_tbl_get(dev_id, index, ®_val); - *value = reg_val.bf.e_drr_credit_1 << 7 | \ - reg_val.bf.e_drr_credit_0; - return ret; -} - -sw_error_t -hppe_l0_drr_credit_tbl_e_drr_credit_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - return SW_NOT_SUPPORTED; -} - -sw_error_t -hppe_l0_c_drr_ll_tbl_next_ptr_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union l0_c_drr_ll_tbl_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_l0_c_drr_ll_tbl_get(dev_id, index, ®_val); - *value = reg_val.bf.next_ptr; - return ret; -} - -sw_error_t -hppe_l0_c_drr_ll_tbl_next_ptr_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - return SW_NOT_SUPPORTED; -} - -sw_error_t -hppe_l0_c_drr_reverse_ll_tbl_pre_ptr_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union l0_c_drr_reverse_ll_tbl_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_l0_c_drr_reverse_ll_tbl_get(dev_id, index, ®_val); - *value = reg_val.bf.pre_ptr; - return ret; -} - -sw_error_t -hppe_l0_c_drr_reverse_ll_tbl_pre_ptr_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - return SW_NOT_SUPPORTED; -} - -sw_error_t -hppe_l0_e_drr_ll_tbl_next_ptr_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union l0_e_drr_ll_tbl_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_l0_e_drr_ll_tbl_get(dev_id, index, ®_val); - *value = reg_val.bf.next_ptr; - return ret; -} - -sw_error_t -hppe_l0_e_drr_ll_tbl_next_ptr_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - return SW_NOT_SUPPORTED; -} - -sw_error_t -hppe_l0_e_drr_reverse_ll_tbl_pre_ptr_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union l0_e_drr_reverse_ll_tbl_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_l0_e_drr_reverse_ll_tbl_get(dev_id, index, ®_val); - *value = reg_val.bf.pre_ptr; - return ret; -} - -sw_error_t -hppe_l0_e_drr_reverse_ll_tbl_pre_ptr_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - return SW_NOT_SUPPORTED; -} - -sw_error_t -hppe_l0_sp_entry_tbl_entry_vld_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union l0_sp_entry_tbl_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_l0_sp_entry_tbl_get(dev_id, index, ®_val); - *value = reg_val.bf.entry_vld; - return ret; -} - -sw_error_t -hppe_l0_sp_entry_tbl_entry_vld_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - return SW_NOT_SUPPORTED; -} - -sw_error_t -hppe_l0_sp_entry_tbl_entry_path_id_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint64_t *value) -{ - union l0_sp_entry_tbl_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_l0_sp_entry_tbl_get(dev_id, index, ®_val); - *value = (a_uint64_t)reg_val.bf.entry_path_id_1 << 32 | \ - reg_val.bf.entry_path_id_0; - return ret; -} - -sw_error_t -hppe_l0_sp_entry_tbl_entry_path_id_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint64_t value) -{ - return SW_NOT_SUPPORTED; -} - -sw_error_t -hppe_l0_ens_q_ll_tbl_next_ptr_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union l0_ens_q_ll_tbl_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_l0_ens_q_ll_tbl_get(dev_id, index, ®_val); - *value = reg_val.bf.next_ptr; - return ret; -} - -sw_error_t -hppe_l0_ens_q_ll_tbl_next_ptr_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - return SW_NOT_SUPPORTED; -} - -sw_error_t -hppe_l0_ens_q_head_tbl_vld_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union l0_ens_q_head_tbl_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_l0_ens_q_head_tbl_get(dev_id, index, ®_val); - *value = reg_val.bf.vld; - return ret; -} - -sw_error_t -hppe_l0_ens_q_head_tbl_vld_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - return SW_NOT_SUPPORTED; -} - -sw_error_t -hppe_l0_ens_q_head_tbl_head_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union l0_ens_q_head_tbl_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_l0_ens_q_head_tbl_get(dev_id, index, ®_val); - *value = reg_val.bf.head; - return ret; -} - -sw_error_t -hppe_l0_ens_q_head_tbl_head_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - return SW_NOT_SUPPORTED; -} - -sw_error_t -hppe_l0_ens_q_head_tbl_tail_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union l0_ens_q_head_tbl_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_l0_ens_q_head_tbl_get(dev_id, index, ®_val); - *value = reg_val.bf.tail; - return ret; -} - -sw_error_t -hppe_l0_ens_q_head_tbl_tail_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - return SW_NOT_SUPPORTED; -} - -sw_error_t -hppe_l0_ens_q_entry_tbl_entry_ens_in_q_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union l0_ens_q_entry_tbl_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_l0_ens_q_entry_tbl_get(dev_id, index, ®_val); - *value = reg_val.bf.entry_ens_in_q; - return ret; -} - -sw_error_t -hppe_l0_ens_q_entry_tbl_entry_ens_in_q_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - return SW_NOT_SUPPORTED; -} - -sw_error_t -hppe_l0_ens_q_entry_tbl_entry_ens_vld_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union l0_ens_q_entry_tbl_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_l0_ens_q_entry_tbl_get(dev_id, index, ®_val); - *value = reg_val.bf.entry_ens_vld; - return ret; -} - -sw_error_t -hppe_l0_ens_q_entry_tbl_entry_ens_vld_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - return SW_NOT_SUPPORTED; -} - -sw_error_t -hppe_l0_ens_q_entry_tbl_entry_ens_type_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union l0_ens_q_entry_tbl_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_l0_ens_q_entry_tbl_get(dev_id, index, ®_val); - *value = reg_val.bf.entry_ens_type; - return ret; -} - -sw_error_t -hppe_l0_ens_q_entry_tbl_entry_ens_type_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - return SW_NOT_SUPPORTED; -} - -sw_error_t -hppe_l0_flow_status_tbl_en_cdrr_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union l0_flow_status_tbl_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_l0_flow_status_tbl_get(dev_id, index, ®_val); - *value = reg_val.bf.en_cdrr; - return ret; -} - -sw_error_t -hppe_l0_flow_status_tbl_en_cdrr_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - return SW_NOT_SUPPORTED; -} - -sw_error_t -hppe_l0_flow_status_tbl_en_edrr_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union l0_flow_status_tbl_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_l0_flow_status_tbl_get(dev_id, index, ®_val); - *value = reg_val.bf.en_edrr; - return ret; -} - -sw_error_t -hppe_l0_flow_status_tbl_en_edrr_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - return SW_NOT_SUPPORTED; -} - -sw_error_t -hppe_l0_flow_status_tbl_en_level_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union l0_flow_status_tbl_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_l0_flow_status_tbl_get(dev_id, index, ®_val); - *value = reg_val.bf.en_level; - return ret; -} - -sw_error_t -hppe_l0_flow_status_tbl_en_level_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - return SW_NOT_SUPPORTED; -} - -sw_error_t -hppe_ring_q_map_tbl_queue_bitmap_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint64_t *value) -{ - union ring_q_map_tbl_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_ring_q_map_tbl_get(dev_id, index, ®_val); - *value = (a_uint64_t)reg_val.bf.queue_bitmap_1 << 32 | \ - reg_val.bf.queue_bitmap_0; - return ret; -} - -sw_error_t -hppe_ring_q_map_tbl_queue_bitmap_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint64_t value) -{ - union ring_q_map_tbl_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_ring_q_map_tbl_get(dev_id, index, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.queue_bitmap_1 = value >> 32; - reg_val.bf.queue_bitmap_0 = value & (((a_uint64_t)1<<32)-1); - ret = hppe_ring_q_map_tbl_set(dev_id, index, ®_val); - return ret; -} - -sw_error_t -hppe_rfc_block_tbl_rfc_block_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union rfc_block_tbl_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_rfc_block_tbl_get(dev_id, index, ®_val); - *value = reg_val.bf.rfc_block; - return ret; -} - -sw_error_t -hppe_rfc_block_tbl_rfc_block_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - return SW_NOT_SUPPORTED; -} - -sw_error_t -hppe_rfc_status_tbl_rfc_status_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union rfc_status_tbl_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_rfc_status_tbl_get(dev_id, index, ®_val); - *value = reg_val.bf.rfc_status; - return ret; -} - -sw_error_t -hppe_rfc_status_tbl_rfc_status_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - return SW_NOT_SUPPORTED; -} - -sw_error_t -hppe_deq_dis_tbl_deq_dis_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union deq_dis_tbl_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_deq_dis_tbl_get(dev_id, index, ®_val); - *value = reg_val.bf.deq_dis; - return ret; -} - -sw_error_t -hppe_deq_dis_tbl_deq_dis_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - union deq_dis_tbl_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_deq_dis_tbl_get(dev_id, index, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.deq_dis = value; - ret = hppe_deq_dis_tbl_set(dev_id, index, ®_val); - return ret; -} - -sw_error_t -hppe_l1_flow_map_tbl_e_pri_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union l1_flow_map_tbl_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_l1_flow_map_tbl_get(dev_id, index, ®_val); - *value = reg_val.bf.e_pri; - return ret; -} - -sw_error_t -hppe_l1_flow_map_tbl_e_pri_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - union l1_flow_map_tbl_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_l1_flow_map_tbl_get(dev_id, index, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.e_pri = value; - ret = hppe_l1_flow_map_tbl_set(dev_id, index, ®_val); - return ret; -} - -sw_error_t -hppe_l1_flow_map_tbl_c_pri_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union l1_flow_map_tbl_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_l1_flow_map_tbl_get(dev_id, index, ®_val); - *value = reg_val.bf.c_pri; - return ret; -} - -sw_error_t -hppe_l1_flow_map_tbl_c_pri_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - union l1_flow_map_tbl_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_l1_flow_map_tbl_get(dev_id, index, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.c_pri = value; - ret = hppe_l1_flow_map_tbl_set(dev_id, index, ®_val); - return ret; -} - -sw_error_t -hppe_l1_flow_map_tbl_e_drr_wt_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union l1_flow_map_tbl_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_l1_flow_map_tbl_get(dev_id, index, ®_val); - *value = reg_val.bf.e_drr_wt; - return ret; -} - -sw_error_t -hppe_l1_flow_map_tbl_e_drr_wt_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - union l1_flow_map_tbl_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_l1_flow_map_tbl_get(dev_id, index, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.e_drr_wt = value; - ret = hppe_l1_flow_map_tbl_set(dev_id, index, ®_val); - return ret; -} - -sw_error_t -hppe_l1_flow_map_tbl_c_drr_wt_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union l1_flow_map_tbl_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_l1_flow_map_tbl_get(dev_id, index, ®_val); - *value = reg_val.bf.c_drr_wt; - return ret; -} - -sw_error_t -hppe_l1_flow_map_tbl_c_drr_wt_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - union l1_flow_map_tbl_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_l1_flow_map_tbl_get(dev_id, index, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.c_drr_wt = value; - ret = hppe_l1_flow_map_tbl_set(dev_id, index, ®_val); - return ret; -} - -sw_error_t -hppe_l1_flow_map_tbl_sp_id_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union l1_flow_map_tbl_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_l1_flow_map_tbl_get(dev_id, index, ®_val); - *value = reg_val.bf.sp_id; - return ret; -} - -sw_error_t -hppe_l1_flow_map_tbl_sp_id_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - union l1_flow_map_tbl_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_l1_flow_map_tbl_get(dev_id, index, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.sp_id = value; - ret = hppe_l1_flow_map_tbl_set(dev_id, index, ®_val); - return ret; -} - -sw_error_t -hppe_l1_c_sp_cfg_tbl_drr_credit_unit_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union l1_c_sp_cfg_tbl_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_l1_c_sp_cfg_tbl_get(dev_id, index, ®_val); - *value = reg_val.bf.drr_credit_unit; - return ret; -} - -sw_error_t -hppe_l1_c_sp_cfg_tbl_drr_credit_unit_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - union l1_c_sp_cfg_tbl_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_l1_c_sp_cfg_tbl_get(dev_id, index, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.drr_credit_unit = value; - ret = hppe_l1_c_sp_cfg_tbl_set(dev_id, index, ®_val); - return ret; -} - -sw_error_t -hppe_l1_c_sp_cfg_tbl_drr_id_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union l1_c_sp_cfg_tbl_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_l1_c_sp_cfg_tbl_get(dev_id, index, ®_val); - *value = reg_val.bf.drr_id; - return ret; -} - -sw_error_t -hppe_l1_c_sp_cfg_tbl_drr_id_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - union l1_c_sp_cfg_tbl_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_l1_c_sp_cfg_tbl_get(dev_id, index, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.drr_id = value; - ret = hppe_l1_c_sp_cfg_tbl_set(dev_id, index, ®_val); - return ret; -} - -sw_error_t -hppe_l1_e_sp_cfg_tbl_drr_credit_unit_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union l1_e_sp_cfg_tbl_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_l1_e_sp_cfg_tbl_get(dev_id, index, ®_val); - *value = reg_val.bf.drr_credit_unit; - return ret; -} - -sw_error_t -hppe_l1_e_sp_cfg_tbl_drr_credit_unit_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - union l1_e_sp_cfg_tbl_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_l1_e_sp_cfg_tbl_get(dev_id, index, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.drr_credit_unit = value; - ret = hppe_l1_e_sp_cfg_tbl_set(dev_id, index, ®_val); - return ret; -} - -sw_error_t -hppe_l1_e_sp_cfg_tbl_drr_id_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union l1_e_sp_cfg_tbl_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_l1_e_sp_cfg_tbl_get(dev_id, index, ®_val); - *value = reg_val.bf.drr_id; - return ret; -} - -sw_error_t -hppe_l1_e_sp_cfg_tbl_drr_id_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - union l1_e_sp_cfg_tbl_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_l1_e_sp_cfg_tbl_get(dev_id, index, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.drr_id = value; - ret = hppe_l1_e_sp_cfg_tbl_set(dev_id, index, ®_val); - return ret; -} - -sw_error_t -hppe_l1_flow_port_map_tbl_port_num_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union l1_flow_port_map_tbl_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_l1_flow_port_map_tbl_get(dev_id, index, ®_val); - *value = reg_val.bf.port_num; - return ret; -} - -sw_error_t -hppe_l1_flow_port_map_tbl_port_num_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - union l1_flow_port_map_tbl_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_l1_flow_port_map_tbl_get(dev_id, index, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.port_num = value; - ret = hppe_l1_flow_port_map_tbl_set(dev_id, index, ®_val); - return ret; -} - -sw_error_t -hppe_l1_c_drr_head_tbl_backup_head_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union l1_c_drr_head_tbl_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_l1_c_drr_head_tbl_get(dev_id, index, ®_val); - *value = reg_val.bf.backup_head; - return ret; -} - -sw_error_t -hppe_l1_c_drr_head_tbl_backup_head_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - return SW_NOT_SUPPORTED; -} - -sw_error_t -hppe_l1_c_drr_head_tbl_active_vld_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union l1_c_drr_head_tbl_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_l1_c_drr_head_tbl_get(dev_id, index, ®_val); - *value = reg_val.bf.active_vld; - return ret; -} - -sw_error_t -hppe_l1_c_drr_head_tbl_active_vld_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - return SW_NOT_SUPPORTED; -} - -sw_error_t -hppe_l1_c_drr_head_tbl_backup_max_n_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union l1_c_drr_head_tbl_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_l1_c_drr_head_tbl_get(dev_id, index, ®_val); - *value = reg_val.bf.backup_max_n; - return ret; -} - -sw_error_t -hppe_l1_c_drr_head_tbl_backup_max_n_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - return SW_NOT_SUPPORTED; -} - -sw_error_t -hppe_l1_c_drr_head_tbl_active_tail_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union l1_c_drr_head_tbl_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_l1_c_drr_head_tbl_get(dev_id, index, ®_val); - *value = reg_val.bf.active_tail; - return ret; -} - -sw_error_t -hppe_l1_c_drr_head_tbl_active_tail_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - return SW_NOT_SUPPORTED; -} - -sw_error_t -hppe_l1_c_drr_head_tbl_active_head_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union l1_c_drr_head_tbl_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_l1_c_drr_head_tbl_get(dev_id, index, ®_val); - *value = reg_val.bf.active_head; - return ret; -} - -sw_error_t -hppe_l1_c_drr_head_tbl_active_head_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - return SW_NOT_SUPPORTED; -} - -sw_error_t -hppe_l1_c_drr_head_tbl_backup_vld_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union l1_c_drr_head_tbl_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_l1_c_drr_head_tbl_get(dev_id, index, ®_val); - *value = reg_val.bf.backup_vld; - return ret; -} - -sw_error_t -hppe_l1_c_drr_head_tbl_backup_vld_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - return SW_NOT_SUPPORTED; -} - -sw_error_t -hppe_l1_c_drr_head_tbl_active_max_n_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union l1_c_drr_head_tbl_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_l1_c_drr_head_tbl_get(dev_id, index, ®_val); - *value = reg_val.bf.active_max_n_1 << 1 | \ - reg_val.bf.active_max_n_0; - return ret; -} - -sw_error_t -hppe_l1_c_drr_head_tbl_active_max_n_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - return SW_NOT_SUPPORTED; -} - -sw_error_t -hppe_l1_c_drr_head_tbl_backup_tail_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union l1_c_drr_head_tbl_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_l1_c_drr_head_tbl_get(dev_id, index, ®_val); - *value = reg_val.bf.backup_tail; - return ret; -} - -sw_error_t -hppe_l1_c_drr_head_tbl_backup_tail_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - return SW_NOT_SUPPORTED; -} - -sw_error_t -hppe_l1_e_drr_head_tbl_backup_head_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union l1_e_drr_head_tbl_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_l1_e_drr_head_tbl_get(dev_id, index, ®_val); - *value = reg_val.bf.backup_head; - return ret; -} - -sw_error_t -hppe_l1_e_drr_head_tbl_backup_head_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - return SW_NOT_SUPPORTED; -} - -sw_error_t -hppe_l1_e_drr_head_tbl_active_vld_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union l1_e_drr_head_tbl_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_l1_e_drr_head_tbl_get(dev_id, index, ®_val); - *value = reg_val.bf.active_vld; - return ret; -} - -sw_error_t -hppe_l1_e_drr_head_tbl_active_vld_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - return SW_NOT_SUPPORTED; -} - -sw_error_t -hppe_l1_e_drr_head_tbl_backup_max_n_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union l1_e_drr_head_tbl_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_l1_e_drr_head_tbl_get(dev_id, index, ®_val); - *value = reg_val.bf.backup_max_n; - return ret; -} - -sw_error_t -hppe_l1_e_drr_head_tbl_backup_max_n_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - return SW_NOT_SUPPORTED; -} - -sw_error_t -hppe_l1_e_drr_head_tbl_active_tail_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union l1_e_drr_head_tbl_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_l1_e_drr_head_tbl_get(dev_id, index, ®_val); - *value = reg_val.bf.active_tail; - return ret; -} - -sw_error_t -hppe_l1_e_drr_head_tbl_active_tail_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - return SW_NOT_SUPPORTED; -} - -sw_error_t -hppe_l1_e_drr_head_tbl_active_head_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union l1_e_drr_head_tbl_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_l1_e_drr_head_tbl_get(dev_id, index, ®_val); - *value = reg_val.bf.active_head; - return ret; -} - -sw_error_t -hppe_l1_e_drr_head_tbl_active_head_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - return SW_NOT_SUPPORTED; -} - -sw_error_t -hppe_l1_e_drr_head_tbl_backup_vld_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union l1_e_drr_head_tbl_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_l1_e_drr_head_tbl_get(dev_id, index, ®_val); - *value = reg_val.bf.backup_vld; - return ret; -} - -sw_error_t -hppe_l1_e_drr_head_tbl_backup_vld_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - return SW_NOT_SUPPORTED; -} - -sw_error_t -hppe_l1_e_drr_head_tbl_active_max_n_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union l1_e_drr_head_tbl_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_l1_e_drr_head_tbl_get(dev_id, index, ®_val); - *value = reg_val.bf.active_max_n_1 << 1 | \ - reg_val.bf.active_max_n_0; - return ret; -} - -sw_error_t -hppe_l1_e_drr_head_tbl_active_max_n_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - return SW_NOT_SUPPORTED; -} - -sw_error_t -hppe_l1_e_drr_head_tbl_backup_tail_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union l1_e_drr_head_tbl_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_l1_e_drr_head_tbl_get(dev_id, index, ®_val); - *value = reg_val.bf.backup_tail; - return ret; -} - -sw_error_t -hppe_l1_e_drr_head_tbl_backup_tail_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - return SW_NOT_SUPPORTED; -} - -sw_error_t -hppe_l1_drr_credit_tbl_e_drr_credit_neg_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union l1_drr_credit_tbl_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_l1_drr_credit_tbl_get(dev_id, index, ®_val); - *value = reg_val.bf.e_drr_credit_neg; - return ret; -} - -sw_error_t -hppe_l1_drr_credit_tbl_e_drr_credit_neg_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - return SW_NOT_SUPPORTED; -} - -sw_error_t -hppe_l1_drr_credit_tbl_c_drr_credit_neg_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union l1_drr_credit_tbl_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_l1_drr_credit_tbl_get(dev_id, index, ®_val); - *value = reg_val.bf.c_drr_credit_neg; - return ret; -} - -sw_error_t -hppe_l1_drr_credit_tbl_c_drr_credit_neg_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - return SW_NOT_SUPPORTED; -} - -sw_error_t -hppe_l1_drr_credit_tbl_c_drr_credit_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union l1_drr_credit_tbl_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_l1_drr_credit_tbl_get(dev_id, index, ®_val); - *value = reg_val.bf.c_drr_credit; - return ret; -} - -sw_error_t -hppe_l1_drr_credit_tbl_c_drr_credit_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - return SW_NOT_SUPPORTED; -} - -sw_error_t -hppe_l1_drr_credit_tbl_e_drr_credit_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union l1_drr_credit_tbl_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_l1_drr_credit_tbl_get(dev_id, index, ®_val); - *value = reg_val.bf.e_drr_credit_1 << 7 | \ - reg_val.bf.e_drr_credit_0; - return ret; -} - -sw_error_t -hppe_l1_drr_credit_tbl_e_drr_credit_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - return SW_NOT_SUPPORTED; -} - -sw_error_t -hppe_l1_c_drr_ll_tbl_next_ptr_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union l1_c_drr_ll_tbl_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_l1_c_drr_ll_tbl_get(dev_id, index, ®_val); - *value = reg_val.bf.next_ptr; - return ret; -} - -sw_error_t -hppe_l1_c_drr_ll_tbl_next_ptr_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - return SW_NOT_SUPPORTED; -} - -sw_error_t -hppe_l1_c_drr_reverse_ll_tbl_pre_ptr_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union l1_c_drr_reverse_ll_tbl_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_l1_c_drr_reverse_ll_tbl_get(dev_id, index, ®_val); - *value = reg_val.bf.pre_ptr; - return ret; -} - -sw_error_t -hppe_l1_c_drr_reverse_ll_tbl_pre_ptr_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - return SW_NOT_SUPPORTED; -} - -sw_error_t -hppe_l1_e_drr_ll_tbl_next_ptr_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union l1_e_drr_ll_tbl_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_l1_e_drr_ll_tbl_get(dev_id, index, ®_val); - *value = reg_val.bf.next_ptr; - return ret; -} - -sw_error_t -hppe_l1_e_drr_ll_tbl_next_ptr_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - return SW_NOT_SUPPORTED; -} - -sw_error_t -hppe_l1_e_drr_reverse_ll_tbl_pre_ptr_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union l1_e_drr_reverse_ll_tbl_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_l1_e_drr_reverse_ll_tbl_get(dev_id, index, ®_val); - *value = reg_val.bf.pre_ptr; - return ret; -} - -sw_error_t -hppe_l1_e_drr_reverse_ll_tbl_pre_ptr_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - return SW_NOT_SUPPORTED; -} - -sw_error_t -hppe_l1_a_flow_entry_tbl_entry_path_id_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union l1_a_flow_entry_tbl_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_l1_a_flow_entry_tbl_get(dev_id, index, ®_val); - *value = reg_val.bf.entry_path_id; - return ret; -} - -sw_error_t -hppe_l1_a_flow_entry_tbl_entry_path_id_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - return SW_NOT_SUPPORTED; -} - -sw_error_t -hppe_l1_b_flow_entry_tbl_entry_path_id_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union l1_b_flow_entry_tbl_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_l1_b_flow_entry_tbl_get(dev_id, index, ®_val); - *value = reg_val.bf.entry_path_id; - return ret; -} - -sw_error_t -hppe_l1_b_flow_entry_tbl_entry_path_id_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - return SW_NOT_SUPPORTED; -} - -sw_error_t -hppe_l1_sp_entry_tbl_entry_vld_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union l1_sp_entry_tbl_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_l1_sp_entry_tbl_get(dev_id, index, ®_val); - *value = reg_val.bf.entry_vld; - return ret; -} - -sw_error_t -hppe_l1_sp_entry_tbl_entry_vld_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - return SW_NOT_SUPPORTED; -} - -sw_error_t -hppe_l1_sp_entry_tbl_entry_path_id_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint64_t *value) -{ - union l1_sp_entry_tbl_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_l1_sp_entry_tbl_get(dev_id, index, ®_val); - *value = (a_uint64_t)reg_val.bf.entry_path_id_1 << 32 | \ - reg_val.bf.entry_path_id_0; - return ret; -} - -sw_error_t -hppe_l1_sp_entry_tbl_entry_path_id_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint64_t value) -{ - return SW_NOT_SUPPORTED; -} - -sw_error_t -hppe_l1_ens_q_ll_tbl_next_ptr_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union l1_ens_q_ll_tbl_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_l1_ens_q_ll_tbl_get(dev_id, index, ®_val); - *value = reg_val.bf.next_ptr; - return ret; -} - -sw_error_t -hppe_l1_ens_q_ll_tbl_next_ptr_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - return SW_NOT_SUPPORTED; -} - -sw_error_t -hppe_l1_ens_q_head_tbl_vld_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union l1_ens_q_head_tbl_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_l1_ens_q_head_tbl_get(dev_id, index, ®_val); - *value = reg_val.bf.vld; - return ret; -} - -sw_error_t -hppe_l1_ens_q_head_tbl_vld_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - return SW_NOT_SUPPORTED; -} - -sw_error_t -hppe_l1_ens_q_head_tbl_head_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union l1_ens_q_head_tbl_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_l1_ens_q_head_tbl_get(dev_id, index, ®_val); - *value = reg_val.bf.head; - return ret; -} - -sw_error_t -hppe_l1_ens_q_head_tbl_head_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - return SW_NOT_SUPPORTED; -} - -sw_error_t -hppe_l1_ens_q_head_tbl_tail_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union l1_ens_q_head_tbl_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_l1_ens_q_head_tbl_get(dev_id, index, ®_val); - *value = reg_val.bf.tail; - return ret; -} - -sw_error_t -hppe_l1_ens_q_head_tbl_tail_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - return SW_NOT_SUPPORTED; -} - -sw_error_t -hppe_l1_ens_q_entry_tbl_entry_ens_in_q_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union l1_ens_q_entry_tbl_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_l1_ens_q_entry_tbl_get(dev_id, index, ®_val); - *value = reg_val.bf.entry_ens_in_q; - return ret; -} - -sw_error_t -hppe_l1_ens_q_entry_tbl_entry_ens_in_q_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - return SW_NOT_SUPPORTED; -} - -sw_error_t -hppe_l1_ens_q_entry_tbl_entry_ens_vld_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union l1_ens_q_entry_tbl_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_l1_ens_q_entry_tbl_get(dev_id, index, ®_val); - *value = reg_val.bf.entry_ens_vld; - return ret; -} - -sw_error_t -hppe_l1_ens_q_entry_tbl_entry_ens_vld_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - return SW_NOT_SUPPORTED; -} - -sw_error_t -hppe_l1_ens_q_entry_tbl_entry_ens_type_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union l1_ens_q_entry_tbl_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_l1_ens_q_entry_tbl_get(dev_id, index, ®_val); - *value = reg_val.bf.entry_ens_type; - return ret; -} - -sw_error_t -hppe_l1_ens_q_entry_tbl_entry_ens_type_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - return SW_NOT_SUPPORTED; -} - -sw_error_t -hppe_l1_flow_status_tbl_en_cdrr_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union l1_flow_status_tbl_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_l1_flow_status_tbl_get(dev_id, index, ®_val); - *value = reg_val.bf.en_cdrr; - return ret; -} - -sw_error_t -hppe_l1_flow_status_tbl_en_cdrr_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - return SW_NOT_SUPPORTED; -} - -sw_error_t -hppe_l1_flow_status_tbl_en_edrr_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union l1_flow_status_tbl_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_l1_flow_status_tbl_get(dev_id, index, ®_val); - *value = reg_val.bf.en_edrr; - return ret; -} - -sw_error_t -hppe_l1_flow_status_tbl_en_edrr_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - return SW_NOT_SUPPORTED; -} - -sw_error_t -hppe_l1_flow_status_tbl_en_level_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union l1_flow_status_tbl_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_l1_flow_status_tbl_get(dev_id, index, ®_val); - *value = reg_val.bf.en_level; - return ret; -} - -sw_error_t -hppe_l1_flow_status_tbl_en_level_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - return SW_NOT_SUPPORTED; -} - -sw_error_t -hppe_psch_tdm_cfg_tbl_ens_port_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union psch_tdm_cfg_tbl_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_psch_tdm_cfg_tbl_get(dev_id, index, ®_val); - *value = reg_val.bf.ens_port; - return ret; -} - -sw_error_t -hppe_psch_tdm_cfg_tbl_ens_port_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - union psch_tdm_cfg_tbl_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_psch_tdm_cfg_tbl_get(dev_id, index, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.ens_port = value; - ret = hppe_psch_tdm_cfg_tbl_set(dev_id, index, ®_val); - return ret; -} - -sw_error_t -hppe_psch_tdm_cfg_tbl_des_port_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union psch_tdm_cfg_tbl_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_psch_tdm_cfg_tbl_get(dev_id, index, ®_val); - *value = reg_val.bf.des_port; - return ret; -} - -sw_error_t -hppe_psch_tdm_cfg_tbl_des_port_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - union psch_tdm_cfg_tbl_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_psch_tdm_cfg_tbl_get(dev_id, index, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.des_port = value; - ret = hppe_psch_tdm_cfg_tbl_set(dev_id, index, ®_val); - return ret; -} - -sw_error_t -hppe_psch_tdm_cfg_tbl_ens_port_bitmap_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union psch_tdm_cfg_tbl_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_psch_tdm_cfg_tbl_get(dev_id, index, ®_val); - *value = reg_val.bf.ens_port_bitmap; - return ret; -} - -sw_error_t -hppe_psch_tdm_cfg_tbl_ens_port_bitmap_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - union psch_tdm_cfg_tbl_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_psch_tdm_cfg_tbl_get(dev_id, index, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.ens_port_bitmap = value; - ret = hppe_psch_tdm_cfg_tbl_set(dev_id, index, ®_val); - return ret; -} - -sw_error_t -hppe_port_qos_ctrl_port_flow_qos_pri_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union port_qos_ctrl_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_port_qos_ctrl_get(dev_id, index, ®_val); - *value = reg_val.bf.port_flow_qos_pri; - return ret; -} - -sw_error_t -hppe_port_qos_ctrl_port_flow_qos_pri_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - union port_qos_ctrl_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_port_qos_ctrl_get(dev_id, index, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.port_flow_qos_pri = value; - ret = hppe_port_qos_ctrl_set(dev_id, index, ®_val); - return ret; -} - -sw_error_t -hppe_port_qos_ctrl_port_dscp_qos_pri_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union port_qos_ctrl_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_port_qos_ctrl_get(dev_id, index, ®_val); - *value = reg_val.bf.port_dscp_qos_pri; - return ret; -} - -sw_error_t -hppe_port_qos_ctrl_port_dscp_qos_pri_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - union port_qos_ctrl_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_port_qos_ctrl_get(dev_id, index, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.port_dscp_qos_pri = value; - ret = hppe_port_qos_ctrl_set(dev_id, index, ®_val); - return ret; -} - -sw_error_t -hppe_port_qos_ctrl_port_dscp_change_en_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union port_qos_ctrl_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_port_qos_ctrl_get(dev_id, index, ®_val); - *value = reg_val.bf.port_dscp_change_en; - return ret; -} - -sw_error_t -hppe_port_qos_ctrl_port_dscp_change_en_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - union port_qos_ctrl_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_port_qos_ctrl_get(dev_id, index, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.port_dscp_change_en = value; - ret = hppe_port_qos_ctrl_set(dev_id, index, ®_val); - return ret; -} - -sw_error_t -hppe_port_qos_ctrl_port_pcp_change_en_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union port_qos_ctrl_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_port_qos_ctrl_get(dev_id, index, ®_val); - *value = reg_val.bf.port_pcp_change_en; - return ret; -} - -sw_error_t -hppe_port_qos_ctrl_port_pcp_change_en_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - union port_qos_ctrl_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_port_qos_ctrl_get(dev_id, index, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.port_pcp_change_en = value; - ret = hppe_port_qos_ctrl_set(dev_id, index, ®_val); - return ret; -} - -sw_error_t -hppe_port_qos_ctrl_port_acl_qos_pri_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union port_qos_ctrl_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_port_qos_ctrl_get(dev_id, index, ®_val); - *value = reg_val.bf.port_acl_qos_pri; - return ret; -} - -sw_error_t -hppe_port_qos_ctrl_port_acl_qos_pri_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - union port_qos_ctrl_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_port_qos_ctrl_get(dev_id, index, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.port_acl_qos_pri = value; - ret = hppe_port_qos_ctrl_set(dev_id, index, ®_val); - return ret; -} - -sw_error_t -hppe_port_qos_ctrl_flow_qos_group_id_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union port_qos_ctrl_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_port_qos_ctrl_get(dev_id, index, ®_val); - *value = reg_val.bf.flow_qos_group_id; - return ret; -} - -sw_error_t -hppe_port_qos_ctrl_flow_qos_group_id_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - union port_qos_ctrl_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_port_qos_ctrl_get(dev_id, index, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.flow_qos_group_id = value; - ret = hppe_port_qos_ctrl_set(dev_id, index, ®_val); - return ret; -} - -sw_error_t -hppe_port_qos_ctrl_port_preheader_qos_pri_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union port_qos_ctrl_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_port_qos_ctrl_get(dev_id, index, ®_val); - *value = reg_val.bf.port_preheader_qos_pri; - return ret; -} - -sw_error_t -hppe_port_qos_ctrl_port_preheader_qos_pri_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - union port_qos_ctrl_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_port_qos_ctrl_get(dev_id, index, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.port_preheader_qos_pri = value; - ret = hppe_port_qos_ctrl_set(dev_id, index, ®_val); - return ret; -} - -sw_error_t -hppe_port_qos_ctrl_pcp_qos_group_id_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union port_qos_ctrl_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_port_qos_ctrl_get(dev_id, index, ®_val); - *value = reg_val.bf.pcp_qos_group_id; - return ret; -} - -sw_error_t -hppe_port_qos_ctrl_pcp_qos_group_id_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - union port_qos_ctrl_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_port_qos_ctrl_get(dev_id, index, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.pcp_qos_group_id = value; - ret = hppe_port_qos_ctrl_set(dev_id, index, ®_val); - return ret; -} - -sw_error_t -hppe_port_qos_ctrl_dscp_qos_group_id_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union port_qos_ctrl_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_port_qos_ctrl_get(dev_id, index, ®_val); - *value = reg_val.bf.dscp_qos_group_id; - return ret; -} - -sw_error_t -hppe_port_qos_ctrl_dscp_qos_group_id_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - union port_qos_ctrl_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_port_qos_ctrl_get(dev_id, index, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.dscp_qos_group_id = value; - ret = hppe_port_qos_ctrl_set(dev_id, index, ®_val); - return ret; -} - -sw_error_t -hppe_port_qos_ctrl_port_pcp_qos_pri_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union port_qos_ctrl_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_port_qos_ctrl_get(dev_id, index, ®_val); - *value = reg_val.bf.port_pcp_qos_pri; - return ret; -} - -sw_error_t -hppe_port_qos_ctrl_port_pcp_qos_pri_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - union port_qos_ctrl_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_port_qos_ctrl_get(dev_id, index, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.port_pcp_qos_pri = value; - ret = hppe_port_qos_ctrl_set(dev_id, index, ®_val); - return ret; -} - -sw_error_t -hppe_port_qos_ctrl_port_dei_change_en_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union port_qos_ctrl_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_port_qos_ctrl_get(dev_id, index, ®_val); - *value = reg_val.bf.port_dei_change_en; - return ret; -} - -sw_error_t -hppe_port_qos_ctrl_port_dei_change_en_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - union port_qos_ctrl_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_port_qos_ctrl_get(dev_id, index, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.port_dei_change_en = value; - ret = hppe_port_qos_ctrl_set(dev_id, index, ®_val); - return ret; -} - -sw_error_t -hppe_pcp_qos_group_0_qos_info_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union pcp_qos_group_0_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_pcp_qos_group_0_get(dev_id, index, ®_val); - *value = reg_val.bf.qos_info; - return ret; -} - -sw_error_t -hppe_pcp_qos_group_0_qos_info_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - union pcp_qos_group_0_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_pcp_qos_group_0_get(dev_id, index, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.qos_info = value; - ret = hppe_pcp_qos_group_0_set(dev_id, index, ®_val); - return ret; -} - -sw_error_t -hppe_pcp_qos_group_1_qos_info_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union pcp_qos_group_1_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_pcp_qos_group_1_get(dev_id, index, ®_val); - *value = reg_val.bf.qos_info; - return ret; -} - -sw_error_t -hppe_pcp_qos_group_1_qos_info_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - union pcp_qos_group_1_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_pcp_qos_group_1_get(dev_id, index, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.qos_info = value; - ret = hppe_pcp_qos_group_1_set(dev_id, index, ®_val); - return ret; -} - -sw_error_t -hppe_flow_qos_group_0_qos_info_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union flow_qos_group_0_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_flow_qos_group_0_get(dev_id, index, ®_val); - *value = reg_val.bf.qos_info; - return ret; -} - -sw_error_t -hppe_flow_qos_group_0_qos_info_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - union flow_qos_group_0_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_flow_qos_group_0_get(dev_id, index, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.qos_info = value; - ret = hppe_flow_qos_group_0_set(dev_id, index, ®_val); - return ret; -} - -sw_error_t -hppe_flow_qos_group_1_qos_info_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union flow_qos_group_1_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_flow_qos_group_1_get(dev_id, index, ®_val); - *value = reg_val.bf.qos_info; - return ret; -} - -sw_error_t -hppe_flow_qos_group_1_qos_info_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - union flow_qos_group_1_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_flow_qos_group_1_get(dev_id, index, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.qos_info = value; - ret = hppe_flow_qos_group_1_set(dev_id, index, ®_val); - return ret; -} - -sw_error_t -hppe_dscp_qos_group_0_qos_info_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union dscp_qos_group_0_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_dscp_qos_group_0_get(dev_id, index, ®_val); - *value = reg_val.bf.qos_info; - return ret; -} - -sw_error_t -hppe_dscp_qos_group_0_qos_info_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - union dscp_qos_group_0_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_dscp_qos_group_0_get(dev_id, index, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.qos_info = value; - ret = hppe_dscp_qos_group_0_set(dev_id, index, ®_val); - return ret; -} - -sw_error_t -hppe_dscp_qos_group_1_qos_info_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union dscp_qos_group_1_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_dscp_qos_group_1_get(dev_id, index, ®_val); - *value = reg_val.bf.qos_info; - return ret; -} - -sw_error_t -hppe_dscp_qos_group_1_qos_info_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - union dscp_qos_group_1_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_dscp_qos_group_1_get(dev_id, index, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.qos_info = value; - ret = hppe_dscp_qos_group_1_set(dev_id, index, ®_val); - return ret; -} -#endif \ No newline at end of file diff --git a/feeds/ipq807x/qca-ssdk/src/src/hsl/hppe/hppe_reg_access.c b/feeds/ipq807x/qca-ssdk/src/src/hsl/hppe/hppe_reg_access.c deleted file mode 100755 index a7eeeda5f..000000000 --- a/feeds/ipq807x/qca-ssdk/src/src/hsl/hppe/hppe_reg_access.c +++ /dev/null @@ -1,77 +0,0 @@ -/* - * Copyright (c) 2016-2017, The Linux Foundation. All rights reserved. - * Permission to use, copy, modify, and/or distribute this software for - * any purpose with or without fee is hereby granted, provided that the - * above copyright notice and this permission notice appear in all copies. - * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES - * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR - * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES - * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN - * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT - * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. - */ - - -/** - * @defgroup - * @{ - */ -#include "sw.h" -#include "ssdk_init.h" -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include "ssdk_plat.h" -#include - -sw_error_t hppe_reg_get(a_uint32_t dev_id, a_uint32_t reg_addr, a_uint32_t *val) -{ - qca_switch_reg_read(dev_id, reg_addr, (a_uint8_t *)val, 4); - return SW_OK; -} - -sw_error_t hppe_reg_set(a_uint32_t dev_id, a_uint32_t reg_addr, a_uint32_t val) -{ - qca_switch_reg_write(dev_id, reg_addr, (a_uint8_t *)&val, 4); - return SW_OK; -} - -sw_error_t hppe_reg_tbl_get(a_uint32_t dev_id, a_uint32_t reg_addr, a_uint32_t *val, a_uint32_t num) -{ - a_uint32_t i = 0; - for(i = 0; i < num; i++) { - hppe_reg_get(dev_id, (reg_addr + i *4), &val[i]); - } - return SW_OK; -} - -sw_error_t hppe_reg_tbl_set(a_uint32_t dev_id, a_uint32_t reg_addr, a_uint32_t *val, a_uint32_t num) -{ - a_uint32_t i = 0; - for(i = 0; i < num; i++) { - hppe_reg_set(dev_id, (reg_addr + i *4), val[i]); - } - return SW_OK; -} - -sw_error_t hppe_uniphy_reg_get(a_uint32_t dev_id, a_uint32_t reg_addr, a_uint32_t index, a_uint32_t *val) -{ - qca_uniphy_reg_read(dev_id, index, reg_addr, (a_uint8_t *)val, 4); - return SW_OK; -} - -sw_error_t hppe_uniphy_reg_set(a_uint32_t dev_id, a_uint32_t reg_addr, a_uint32_t index, a_uint32_t val) -{ - qca_uniphy_reg_write(dev_id, index, reg_addr, (a_uint8_t *)&val, 4); - return SW_OK; -} - diff --git a/feeds/ipq807x/qca-ssdk/src/src/hsl/hppe/hppe_rss.c b/feeds/ipq807x/qca-ssdk/src/src/hsl/hppe/hppe_rss.c deleted file mode 100755 index d1ec5c3da..000000000 --- a/feeds/ipq807x/qca-ssdk/src/src/hsl/hppe/hppe_rss.c +++ /dev/null @@ -1,585 +0,0 @@ -/* - * Copyright (c) 2016-2017, The Linux Foundation. All rights reserved. - * Permission to use, copy, modify, and/or distribute this software for - * any purpose with or without fee is hereby granted, provided that the - * above copyright notice and this permission notice appear in all copies. - * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES - * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR - * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES - * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN - * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT - * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. - */ - - -/** - * @defgroup - * @{ - */ -#include "sw.h" -#include "hsl.h" -#include "hppe_reg_access.h" -#include "hppe_rss_reg.h" -#include "hppe_rss.h" - -sw_error_t -hppe_rss_hash_mask_reg_get( - a_uint32_t dev_id, - union rss_hash_mask_reg_u *value) -{ - return hppe_reg_get( - dev_id, - IPO_CSR_BASE_ADDR + RSS_HASH_MASK_REG_ADDRESS, - &value->val); -} - -sw_error_t -hppe_rss_hash_mask_reg_set( - a_uint32_t dev_id, - union rss_hash_mask_reg_u *value) -{ - return hppe_reg_set( - dev_id, - IPO_CSR_BASE_ADDR + RSS_HASH_MASK_REG_ADDRESS, - value->val); -} - -sw_error_t -hppe_rss_hash_seed_reg_get( - a_uint32_t dev_id, - union rss_hash_seed_reg_u *value) -{ - return hppe_reg_get( - dev_id, - IPO_CSR_BASE_ADDR + RSS_HASH_SEED_REG_ADDRESS, - &value->val); -} - -sw_error_t -hppe_rss_hash_seed_reg_set( - a_uint32_t dev_id, - union rss_hash_seed_reg_u *value) -{ - return hppe_reg_set( - dev_id, - IPO_CSR_BASE_ADDR + RSS_HASH_SEED_REG_ADDRESS, - value->val); -} - -sw_error_t -hppe_rss_hash_mix_reg_get( - a_uint32_t dev_id, - a_uint32_t index, - union rss_hash_mix_reg_u *value) -{ - if (index >= RSS_HASH_MIX_REG_MAX_ENTRY) - return SW_OUT_OF_RANGE; - return hppe_reg_get( - dev_id, - IPO_CSR_BASE_ADDR + RSS_HASH_MIX_REG_ADDRESS + \ - index * RSS_HASH_MIX_REG_INC, - &value->val); -} - -sw_error_t -hppe_rss_hash_mix_reg_set( - a_uint32_t dev_id, - a_uint32_t index, - union rss_hash_mix_reg_u *value) -{ - return hppe_reg_set( - dev_id, - IPO_CSR_BASE_ADDR + RSS_HASH_MIX_REG_ADDRESS + \ - index * RSS_HASH_MIX_REG_INC, - value->val); -} - -sw_error_t -hppe_rss_hash_fin_reg_get( - a_uint32_t dev_id, - a_uint32_t index, - union rss_hash_fin_reg_u *value) -{ - if (index >= RSS_HASH_FIN_REG_MAX_ENTRY) - return SW_OUT_OF_RANGE; - return hppe_reg_get( - dev_id, - IPO_CSR_BASE_ADDR + RSS_HASH_FIN_REG_ADDRESS + \ - index * RSS_HASH_FIN_REG_INC, - &value->val); -} - -sw_error_t -hppe_rss_hash_fin_reg_set( - a_uint32_t dev_id, - a_uint32_t index, - union rss_hash_fin_reg_u *value) -{ - return hppe_reg_set( - dev_id, - IPO_CSR_BASE_ADDR + RSS_HASH_FIN_REG_ADDRESS + \ - index * RSS_HASH_FIN_REG_INC, - value->val); -} - -sw_error_t -hppe_rss_hash_mask_ipv4_reg_get( - a_uint32_t dev_id, - union rss_hash_mask_ipv4_reg_u *value) -{ - return hppe_reg_get( - dev_id, - IPO_CSR_BASE_ADDR + RSS_HASH_MASK_IPV4_REG_ADDRESS, - &value->val); -} - -sw_error_t -hppe_rss_hash_mask_ipv4_reg_set( - a_uint32_t dev_id, - union rss_hash_mask_ipv4_reg_u *value) -{ - return hppe_reg_set( - dev_id, - IPO_CSR_BASE_ADDR + RSS_HASH_MASK_IPV4_REG_ADDRESS, - value->val); -} - -sw_error_t -hppe_rss_hash_seed_ipv4_reg_get( - a_uint32_t dev_id, - union rss_hash_seed_ipv4_reg_u *value) -{ - return hppe_reg_get( - dev_id, - IPO_CSR_BASE_ADDR + RSS_HASH_SEED_IPV4_REG_ADDRESS, - &value->val); -} - -sw_error_t -hppe_rss_hash_seed_ipv4_reg_set( - a_uint32_t dev_id, - union rss_hash_seed_ipv4_reg_u *value) -{ - return hppe_reg_set( - dev_id, - IPO_CSR_BASE_ADDR + RSS_HASH_SEED_IPV4_REG_ADDRESS, - value->val); -} - -sw_error_t -hppe_rss_hash_mix_ipv4_reg_get( - a_uint32_t dev_id, - a_uint32_t index, - union rss_hash_mix_ipv4_reg_u *value) -{ - if (index >= RSS_HASH_MIX_IPV4_REG_MAX_ENTRY) - return SW_OUT_OF_RANGE; - return hppe_reg_get( - dev_id, - IPO_CSR_BASE_ADDR + RSS_HASH_MIX_IPV4_REG_ADDRESS + \ - index * RSS_HASH_MIX_IPV4_REG_INC, - &value->val); -} - -sw_error_t -hppe_rss_hash_mix_ipv4_reg_set( - a_uint32_t dev_id, - a_uint32_t index, - union rss_hash_mix_ipv4_reg_u *value) -{ - return hppe_reg_set( - dev_id, - IPO_CSR_BASE_ADDR + RSS_HASH_MIX_IPV4_REG_ADDRESS + \ - index * RSS_HASH_MIX_IPV4_REG_INC, - value->val); -} - -sw_error_t -hppe_rss_hash_fin_ipv4_reg_get( - a_uint32_t dev_id, - a_uint32_t index, - union rss_hash_fin_ipv4_reg_u *value) -{ - if (index >= RSS_HASH_FIN_IPV4_REG_MAX_ENTRY) - return SW_OUT_OF_RANGE; - return hppe_reg_get( - dev_id, - IPO_CSR_BASE_ADDR + RSS_HASH_FIN_IPV4_REG_ADDRESS + \ - index * RSS_HASH_FIN_IPV4_REG_INC, - &value->val); -} - -sw_error_t -hppe_rss_hash_fin_ipv4_reg_set( - a_uint32_t dev_id, - a_uint32_t index, - union rss_hash_fin_ipv4_reg_u *value) -{ - return hppe_reg_set( - dev_id, - IPO_CSR_BASE_ADDR + RSS_HASH_FIN_IPV4_REG_ADDRESS + \ - index * RSS_HASH_FIN_IPV4_REG_INC, - value->val); -} - -sw_error_t -hppe_rss_hash_mask_reg_fragment_get( - a_uint32_t dev_id, - a_uint32_t *value) -{ - union rss_hash_mask_reg_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_rss_hash_mask_reg_get(dev_id, ®_val); - *value = reg_val.bf.fragment; - return ret; -} - -sw_error_t -hppe_rss_hash_mask_reg_fragment_set( - a_uint32_t dev_id, - a_uint32_t value) -{ - union rss_hash_mask_reg_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_rss_hash_mask_reg_get(dev_id, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.fragment = value; - ret = hppe_rss_hash_mask_reg_set(dev_id, ®_val); - return ret; -} - -sw_error_t -hppe_rss_hash_mask_reg_mask_get( - a_uint32_t dev_id, - a_uint32_t *value) -{ - union rss_hash_mask_reg_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_rss_hash_mask_reg_get(dev_id, ®_val); - *value = reg_val.bf.mask; - return ret; -} - -sw_error_t -hppe_rss_hash_mask_reg_mask_set( - a_uint32_t dev_id, - a_uint32_t value) -{ - union rss_hash_mask_reg_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_rss_hash_mask_reg_get(dev_id, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.mask = value; - ret = hppe_rss_hash_mask_reg_set(dev_id, ®_val); - return ret; -} - -sw_error_t -hppe_rss_hash_seed_reg_seed_get( - a_uint32_t dev_id, - a_uint32_t *value) -{ - union rss_hash_seed_reg_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_rss_hash_seed_reg_get(dev_id, ®_val); - *value = reg_val.bf.seed; - return ret; -} - -sw_error_t -hppe_rss_hash_seed_reg_seed_set( - a_uint32_t dev_id, - a_uint32_t value) -{ - union rss_hash_seed_reg_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_rss_hash_seed_reg_get(dev_id, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.seed = value; - ret = hppe_rss_hash_seed_reg_set(dev_id, ®_val); - return ret; -} - -sw_error_t -hppe_rss_hash_mix_reg_hash_mix_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union rss_hash_mix_reg_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_rss_hash_mix_reg_get(dev_id, index, ®_val); - *value = reg_val.bf.hash_mix; - return ret; -} - -sw_error_t -hppe_rss_hash_mix_reg_hash_mix_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - union rss_hash_mix_reg_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_rss_hash_mix_reg_get(dev_id, index, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.hash_mix = value; - ret = hppe_rss_hash_mix_reg_set(dev_id, index, ®_val); - return ret; -} - -sw_error_t -hppe_rss_hash_fin_reg_fin_outer_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union rss_hash_fin_reg_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_rss_hash_fin_reg_get(dev_id, index, ®_val); - *value = reg_val.bf.fin_outer; - return ret; -} - -sw_error_t -hppe_rss_hash_fin_reg_fin_outer_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - union rss_hash_fin_reg_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_rss_hash_fin_reg_get(dev_id, index, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.fin_outer = value; - ret = hppe_rss_hash_fin_reg_set(dev_id, index, ®_val); - return ret; -} - -sw_error_t -hppe_rss_hash_fin_reg_fin_inner_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union rss_hash_fin_reg_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_rss_hash_fin_reg_get(dev_id, index, ®_val); - *value = reg_val.bf.fin_inner; - return ret; -} - -sw_error_t -hppe_rss_hash_fin_reg_fin_inner_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - union rss_hash_fin_reg_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_rss_hash_fin_reg_get(dev_id, index, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.fin_inner = value; - ret = hppe_rss_hash_fin_reg_set(dev_id, index, ®_val); - return ret; -} - -sw_error_t -hppe_rss_hash_mask_ipv4_reg_fragment_get( - a_uint32_t dev_id, - a_uint32_t *value) -{ - union rss_hash_mask_ipv4_reg_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_rss_hash_mask_ipv4_reg_get(dev_id, ®_val); - *value = reg_val.bf.fragment; - return ret; -} - -sw_error_t -hppe_rss_hash_mask_ipv4_reg_fragment_set( - a_uint32_t dev_id, - a_uint32_t value) -{ - union rss_hash_mask_ipv4_reg_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_rss_hash_mask_ipv4_reg_get(dev_id, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.fragment = value; - ret = hppe_rss_hash_mask_ipv4_reg_set(dev_id, ®_val); - return ret; -} - -sw_error_t -hppe_rss_hash_mask_ipv4_reg_mask_get( - a_uint32_t dev_id, - a_uint32_t *value) -{ - union rss_hash_mask_ipv4_reg_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_rss_hash_mask_ipv4_reg_get(dev_id, ®_val); - *value = reg_val.bf.mask; - return ret; -} - -sw_error_t -hppe_rss_hash_mask_ipv4_reg_mask_set( - a_uint32_t dev_id, - a_uint32_t value) -{ - union rss_hash_mask_ipv4_reg_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_rss_hash_mask_ipv4_reg_get(dev_id, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.mask = value; - ret = hppe_rss_hash_mask_ipv4_reg_set(dev_id, ®_val); - return ret; -} - -sw_error_t -hppe_rss_hash_seed_ipv4_reg_seed_get( - a_uint32_t dev_id, - a_uint32_t *value) -{ - union rss_hash_seed_ipv4_reg_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_rss_hash_seed_ipv4_reg_get(dev_id, ®_val); - *value = reg_val.bf.seed; - return ret; -} - -sw_error_t -hppe_rss_hash_seed_ipv4_reg_seed_set( - a_uint32_t dev_id, - a_uint32_t value) -{ - union rss_hash_seed_ipv4_reg_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_rss_hash_seed_ipv4_reg_get(dev_id, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.seed = value; - ret = hppe_rss_hash_seed_ipv4_reg_set(dev_id, ®_val); - return ret; -} - -sw_error_t -hppe_rss_hash_mix_ipv4_reg_hash_mix_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union rss_hash_mix_ipv4_reg_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_rss_hash_mix_ipv4_reg_get(dev_id, index, ®_val); - *value = reg_val.bf.hash_mix; - return ret; -} - -sw_error_t -hppe_rss_hash_mix_ipv4_reg_hash_mix_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - union rss_hash_mix_ipv4_reg_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_rss_hash_mix_ipv4_reg_get(dev_id, index, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.hash_mix = value; - ret = hppe_rss_hash_mix_ipv4_reg_set(dev_id, index, ®_val); - return ret; -} - -sw_error_t -hppe_rss_hash_fin_ipv4_reg_fin_outer_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union rss_hash_fin_ipv4_reg_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_rss_hash_fin_ipv4_reg_get(dev_id, index, ®_val); - *value = reg_val.bf.fin_outer; - return ret; -} - -sw_error_t -hppe_rss_hash_fin_ipv4_reg_fin_outer_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - union rss_hash_fin_ipv4_reg_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_rss_hash_fin_ipv4_reg_get(dev_id, index, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.fin_outer = value; - ret = hppe_rss_hash_fin_ipv4_reg_set(dev_id, index, ®_val); - return ret; -} - -sw_error_t -hppe_rss_hash_fin_ipv4_reg_fin_inner_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union rss_hash_fin_ipv4_reg_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_rss_hash_fin_ipv4_reg_get(dev_id, index, ®_val); - *value = reg_val.bf.fin_inner; - return ret; -} - -sw_error_t -hppe_rss_hash_fin_ipv4_reg_fin_inner_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - union rss_hash_fin_ipv4_reg_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_rss_hash_fin_ipv4_reg_get(dev_id, index, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.fin_inner = value; - ret = hppe_rss_hash_fin_ipv4_reg_set(dev_id, index, ®_val); - return ret; -} - diff --git a/feeds/ipq807x/qca-ssdk/src/src/hsl/hppe/hppe_sec.c b/feeds/ipq807x/qca-ssdk/src/src/hsl/hppe/hppe_sec.c deleted file mode 100755 index 992f47c16..000000000 --- a/feeds/ipq807x/qca-ssdk/src/src/hsl/hppe/hppe_sec.c +++ /dev/null @@ -1,1041 +0,0 @@ -/* - * Copyright (c) 2016-2017, The Linux Foundation. All rights reserved. - * Permission to use, copy, modify, and/or distribute this software for - * any purpose with or without fee is hereby granted, provided that the - * above copyright notice and this permission notice appear in all copies. - * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES - * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR - * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES - * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN - * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT - * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. - */ - - -/** - * @defgroup - * @{ - */ -#include "sw.h" -#include "hsl.h" -#include "hppe_reg_access.h" -#include "hppe_sec_reg.h" -#include "hppe_sec.h" - -sw_error_t -hppe_l3_exception_cmd_get( - a_uint32_t dev_id, - a_uint32_t index, - union l3_exception_cmd_u *value) -{ - if (index >= L3_EXCEPTION_CMD_MAX_ENTRY) - return SW_OUT_OF_RANGE; - return hppe_reg_get( - dev_id, - IPE_L3_BASE_ADDR + L3_EXCEPTION_CMD_ADDRESS + \ - index * L3_EXCEPTION_CMD_INC, - &value->val); -} - -sw_error_t -hppe_l3_exception_cmd_set( - a_uint32_t dev_id, - a_uint32_t index, - union l3_exception_cmd_u *value) -{ - return hppe_reg_set( - dev_id, - IPE_L3_BASE_ADDR + L3_EXCEPTION_CMD_ADDRESS + \ - index * L3_EXCEPTION_CMD_INC, - value->val); -} - -sw_error_t -hppe_l3_exp_l3_only_ctrl_get( - a_uint32_t dev_id, - a_uint32_t index, - union l3_exp_l3_only_ctrl_u *value) -{ - if (index >= L3_EXP_L3_ONLY_CTRL_MAX_ENTRY) - return SW_OUT_OF_RANGE; - return hppe_reg_get( - dev_id, - IPE_L3_BASE_ADDR + L3_EXP_L3_ONLY_CTRL_ADDRESS + \ - index * L3_EXP_L3_ONLY_CTRL_INC, - &value->val); -} - -sw_error_t -hppe_l3_exp_l3_only_ctrl_set( - a_uint32_t dev_id, - a_uint32_t index, - union l3_exp_l3_only_ctrl_u *value) -{ - return hppe_reg_set( - dev_id, - IPE_L3_BASE_ADDR + L3_EXP_L3_ONLY_CTRL_ADDRESS + \ - index * L3_EXP_L3_ONLY_CTRL_INC, - value->val); -} - -sw_error_t -hppe_l3_exp_l2_only_ctrl_get( - a_uint32_t dev_id, - a_uint32_t index, - union l3_exp_l2_only_ctrl_u *value) -{ - if (index >= L3_EXP_L2_ONLY_CTRL_MAX_ENTRY) - return SW_OUT_OF_RANGE; - return hppe_reg_get( - dev_id, - IPE_L3_BASE_ADDR + L3_EXP_L2_ONLY_CTRL_ADDRESS + \ - index * L3_EXP_L2_ONLY_CTRL_INC, - &value->val); -} - -sw_error_t -hppe_l3_exp_l2_only_ctrl_set( - a_uint32_t dev_id, - a_uint32_t index, - union l3_exp_l2_only_ctrl_u *value) -{ - return hppe_reg_set( - dev_id, - IPE_L3_BASE_ADDR + L3_EXP_L2_ONLY_CTRL_ADDRESS + \ - index * L3_EXP_L2_ONLY_CTRL_INC, - value->val); -} - -sw_error_t -hppe_l3_exp_l2_flow_ctrl_get( - a_uint32_t dev_id, - a_uint32_t index, - union l3_exp_l2_flow_ctrl_u *value) -{ - if (index >= L3_EXP_L2_FLOW_CTRL_MAX_ENTRY) - return SW_OUT_OF_RANGE; - return hppe_reg_get( - dev_id, - IPE_L3_BASE_ADDR + L3_EXP_L2_FLOW_CTRL_ADDRESS + \ - index * L3_EXP_L2_FLOW_CTRL_INC, - &value->val); -} - -sw_error_t -hppe_l3_exp_l2_flow_ctrl_set( - a_uint32_t dev_id, - a_uint32_t index, - union l3_exp_l2_flow_ctrl_u *value) -{ - return hppe_reg_set( - dev_id, - IPE_L3_BASE_ADDR + L3_EXP_L2_FLOW_CTRL_ADDRESS + \ - index * L3_EXP_L2_FLOW_CTRL_INC, - value->val); -} - -sw_error_t -hppe_l3_exp_l3_flow_ctrl_get( - a_uint32_t dev_id, - a_uint32_t index, - union l3_exp_l3_flow_ctrl_u *value) -{ - if (index >= L3_EXP_L3_FLOW_CTRL_MAX_ENTRY) - return SW_OUT_OF_RANGE; - return hppe_reg_get( - dev_id, - IPE_L3_BASE_ADDR + L3_EXP_L3_FLOW_CTRL_ADDRESS + \ - index * L3_EXP_L3_FLOW_CTRL_INC, - &value->val); -} - -sw_error_t -hppe_l3_exp_l3_flow_ctrl_set( - a_uint32_t dev_id, - a_uint32_t index, - union l3_exp_l3_flow_ctrl_u *value) -{ - return hppe_reg_set( - dev_id, - IPE_L3_BASE_ADDR + L3_EXP_L3_FLOW_CTRL_ADDRESS + \ - index * L3_EXP_L3_FLOW_CTRL_INC, - value->val); -} - -sw_error_t -hppe_l3_exp_multicast_ctrl_get( - a_uint32_t dev_id, - a_uint32_t index, - union l3_exp_multicast_ctrl_u *value) -{ - if (index >= L3_EXP_MULTICAST_CTRL_MAX_ENTRY) - return SW_OUT_OF_RANGE; - return hppe_reg_get( - dev_id, - IPE_L3_BASE_ADDR + L3_EXP_MULTICAST_CTRL_ADDRESS + \ - index * L3_EXP_MULTICAST_CTRL_INC, - &value->val); -} - -sw_error_t -hppe_l3_exp_multicast_ctrl_set( - a_uint32_t dev_id, - a_uint32_t index, - union l3_exp_multicast_ctrl_u *value) -{ - return hppe_reg_set( - dev_id, - IPE_L3_BASE_ADDR + L3_EXP_MULTICAST_CTRL_ADDRESS + \ - index * L3_EXP_MULTICAST_CTRL_INC, - value->val); -} - -sw_error_t -hppe_l3_exception_cmd_l3_excep_cmd_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union l3_exception_cmd_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_l3_exception_cmd_get(dev_id, index, ®_val); - *value = reg_val.bf.l3_excep_cmd; - return ret; -} - -sw_error_t -hppe_l3_exception_cmd_l3_excep_cmd_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - union l3_exception_cmd_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_l3_exception_cmd_get(dev_id, index, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.l3_excep_cmd = value; - ret = hppe_l3_exception_cmd_set(dev_id, index, ®_val); - return ret; -} - -sw_error_t -hppe_l3_exception_cmd_de_acce_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union l3_exception_cmd_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_l3_exception_cmd_get(dev_id, index, ®_val); - *value = reg_val.bf.de_acce; - return ret; -} - -sw_error_t -hppe_l3_exception_cmd_de_acce_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - union l3_exception_cmd_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_l3_exception_cmd_get(dev_id, index, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.de_acce = value; - ret = hppe_l3_exception_cmd_set(dev_id, index, ®_val); - return ret; -} - -sw_error_t -hppe_l3_exp_l3_only_ctrl_excep_en_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union l3_exp_l3_only_ctrl_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_l3_exp_l3_only_ctrl_get(dev_id, index, ®_val); - *value = reg_val.bf.excep_en; - return ret; -} - -sw_error_t -hppe_l3_exp_l3_only_ctrl_excep_en_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - union l3_exp_l3_only_ctrl_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_l3_exp_l3_only_ctrl_get(dev_id, index, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.excep_en = value; - ret = hppe_l3_exp_l3_only_ctrl_set(dev_id, index, ®_val); - return ret; -} - -sw_error_t -hppe_l3_exp_l2_only_ctrl_excep_en_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union l3_exp_l2_only_ctrl_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_l3_exp_l2_only_ctrl_get(dev_id, index, ®_val); - *value = reg_val.bf.excep_en; - return ret; -} - -sw_error_t -hppe_l3_exp_l2_only_ctrl_excep_en_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - union l3_exp_l2_only_ctrl_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_l3_exp_l2_only_ctrl_get(dev_id, index, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.excep_en = value; - ret = hppe_l3_exp_l2_only_ctrl_set(dev_id, index, ®_val); - return ret; -} - -sw_error_t -hppe_l3_exp_l2_flow_ctrl_excep_en_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union l3_exp_l2_flow_ctrl_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_l3_exp_l2_flow_ctrl_get(dev_id, index, ®_val); - *value = reg_val.bf.excep_en; - return ret; -} - -sw_error_t -hppe_l3_exp_l2_flow_ctrl_excep_en_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - union l3_exp_l2_flow_ctrl_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_l3_exp_l2_flow_ctrl_get(dev_id, index, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.excep_en = value; - ret = hppe_l3_exp_l2_flow_ctrl_set(dev_id, index, ®_val); - return ret; -} - -sw_error_t -hppe_l3_exp_l3_flow_ctrl_excep_en_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union l3_exp_l3_flow_ctrl_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_l3_exp_l3_flow_ctrl_get(dev_id, index, ®_val); - *value = reg_val.bf.excep_en; - return ret; -} - -sw_error_t -hppe_l3_exp_l3_flow_ctrl_excep_en_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - union l3_exp_l3_flow_ctrl_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_l3_exp_l3_flow_ctrl_get(dev_id, index, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.excep_en = value; - ret = hppe_l3_exp_l3_flow_ctrl_set(dev_id, index, ®_val); - return ret; -} - -sw_error_t -hppe_l3_exp_multicast_ctrl_excep_en_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union l3_exp_multicast_ctrl_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_l3_exp_multicast_ctrl_get(dev_id, index, ®_val); - *value = reg_val.bf.excep_en; - return ret; -} - -sw_error_t -hppe_l3_exp_multicast_ctrl_excep_en_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - union l3_exp_multicast_ctrl_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_l3_exp_multicast_ctrl_get(dev_id, index, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.excep_en = value; - ret = hppe_l3_exp_multicast_ctrl_set(dev_id, index, ®_val); - return ret; -} - -sw_error_t -hppe_l3_exception_parsing_ctrl_reg_get( - a_uint32_t dev_id, - union l3_exception_parsing_ctrl_reg_u *value) -{ - return hppe_reg_get( - dev_id, - IPR_CSR_BASE_ADDR + L3_EXCEPTION_PARSING_CTRL_REG_ADDRESS, - &value->val); -} - -sw_error_t -hppe_l3_exception_parsing_ctrl_reg_set( - a_uint32_t dev_id, - union l3_exception_parsing_ctrl_reg_u *value) -{ - return hppe_reg_set( - dev_id, - IPR_CSR_BASE_ADDR + L3_EXCEPTION_PARSING_CTRL_REG_ADDRESS, - value->val); -} - -sw_error_t -hppe_l4_exception_parsing_ctrl_0_reg_get( - a_uint32_t dev_id, - union l4_exception_parsing_ctrl_0_reg_u *value) -{ - return hppe_reg_get( - dev_id, - IPR_CSR_BASE_ADDR + L4_EXCEPTION_PARSING_CTRL_0_REG_ADDRESS, - &value->val); -} - -sw_error_t -hppe_l4_exception_parsing_ctrl_0_reg_set( - a_uint32_t dev_id, - union l4_exception_parsing_ctrl_0_reg_u *value) -{ - return hppe_reg_set( - dev_id, - IPR_CSR_BASE_ADDR + L4_EXCEPTION_PARSING_CTRL_0_REG_ADDRESS, - value->val); -} - -sw_error_t -hppe_l4_exception_parsing_ctrl_1_reg_get( - a_uint32_t dev_id, - union l4_exception_parsing_ctrl_1_reg_u *value) -{ - return hppe_reg_get( - dev_id, - IPR_CSR_BASE_ADDR + L4_EXCEPTION_PARSING_CTRL_1_REG_ADDRESS, - &value->val); -} - -sw_error_t -hppe_l4_exception_parsing_ctrl_1_reg_set( - a_uint32_t dev_id, - union l4_exception_parsing_ctrl_1_reg_u *value) -{ - return hppe_reg_set( - dev_id, - IPR_CSR_BASE_ADDR + L4_EXCEPTION_PARSING_CTRL_1_REG_ADDRESS, - value->val); -} - -sw_error_t -hppe_l4_exception_parsing_ctrl_2_reg_get( - a_uint32_t dev_id, - union l4_exception_parsing_ctrl_2_reg_u *value) -{ - return hppe_reg_get( - dev_id, - IPR_CSR_BASE_ADDR + L4_EXCEPTION_PARSING_CTRL_2_REG_ADDRESS, - &value->val); -} - -sw_error_t -hppe_l4_exception_parsing_ctrl_2_reg_set( - a_uint32_t dev_id, - union l4_exception_parsing_ctrl_2_reg_u *value) -{ - return hppe_reg_set( - dev_id, - IPR_CSR_BASE_ADDR + L4_EXCEPTION_PARSING_CTRL_2_REG_ADDRESS, - value->val); -} - -sw_error_t -hppe_l4_exception_parsing_ctrl_3_reg_get( - a_uint32_t dev_id, - union l4_exception_parsing_ctrl_3_reg_u *value) -{ - return hppe_reg_get( - dev_id, - IPR_CSR_BASE_ADDR + L4_EXCEPTION_PARSING_CTRL_3_REG_ADDRESS, - &value->val); -} - -sw_error_t -hppe_l4_exception_parsing_ctrl_3_reg_set( - a_uint32_t dev_id, - union l4_exception_parsing_ctrl_3_reg_u *value) -{ - return hppe_reg_set( - dev_id, - IPR_CSR_BASE_ADDR + L4_EXCEPTION_PARSING_CTRL_3_REG_ADDRESS, - value->val); -} - -sw_error_t -hppe_l3_exception_parsing_ctrl_reg_small_hop_limit_get( - a_uint32_t dev_id, - a_uint32_t *value) -{ - union l3_exception_parsing_ctrl_reg_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_l3_exception_parsing_ctrl_reg_get(dev_id, ®_val); - *value = reg_val.bf.small_hop_limit; - return ret; -} - -sw_error_t -hppe_l3_exception_parsing_ctrl_reg_small_hop_limit_set( - a_uint32_t dev_id, - a_uint32_t value) -{ - union l3_exception_parsing_ctrl_reg_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_l3_exception_parsing_ctrl_reg_get(dev_id, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.small_hop_limit = value; - ret = hppe_l3_exception_parsing_ctrl_reg_set(dev_id, ®_val); - return ret; -} - -sw_error_t -hppe_l3_exception_parsing_ctrl_reg_small_ttl_get( - a_uint32_t dev_id, - a_uint32_t *value) -{ - union l3_exception_parsing_ctrl_reg_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_l3_exception_parsing_ctrl_reg_get(dev_id, ®_val); - *value = reg_val.bf.small_ttl; - return ret; -} - -sw_error_t -hppe_l3_exception_parsing_ctrl_reg_small_ttl_set( - a_uint32_t dev_id, - a_uint32_t value) -{ - union l3_exception_parsing_ctrl_reg_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_l3_exception_parsing_ctrl_reg_get(dev_id, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.small_ttl = value; - ret = hppe_l3_exception_parsing_ctrl_reg_set(dev_id, ®_val); - return ret; -} - -sw_error_t -hppe_l4_exception_parsing_ctrl_0_reg_tcp_flags0_get( - a_uint32_t dev_id, - a_uint32_t *value) -{ - union l4_exception_parsing_ctrl_0_reg_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_l4_exception_parsing_ctrl_0_reg_get(dev_id, ®_val); - *value = reg_val.bf.tcp_flags0; - return ret; -} - -sw_error_t -hppe_l4_exception_parsing_ctrl_0_reg_tcp_flags0_set( - a_uint32_t dev_id, - a_uint32_t value) -{ - union l4_exception_parsing_ctrl_0_reg_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_l4_exception_parsing_ctrl_0_reg_get(dev_id, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.tcp_flags0 = value; - ret = hppe_l4_exception_parsing_ctrl_0_reg_set(dev_id, ®_val); - return ret; -} -sw_error_t -hppe_l4_exception_parsing_ctrl_0_reg_tcp_flags0_mask_get( - a_uint32_t dev_id, - a_uint32_t *value) -{ - union l4_exception_parsing_ctrl_0_reg_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_l4_exception_parsing_ctrl_0_reg_get(dev_id, ®_val); - *value = reg_val.bf.tcp_flags0_mask; - return ret; -} - -sw_error_t -hppe_l4_exception_parsing_ctrl_0_reg_tcp_flags0_mask_set( - a_uint32_t dev_id, - a_uint32_t value) -{ - union l4_exception_parsing_ctrl_0_reg_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_l4_exception_parsing_ctrl_0_reg_get(dev_id, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.tcp_flags0_mask = value; - ret = hppe_l4_exception_parsing_ctrl_0_reg_set(dev_id, ®_val); - return ret; -} - -sw_error_t -hppe_l4_exception_parsing_ctrl_0_reg_tcp_flags1_get( - a_uint32_t dev_id, - a_uint32_t *value) -{ - union l4_exception_parsing_ctrl_0_reg_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_l4_exception_parsing_ctrl_0_reg_get(dev_id, ®_val); - *value = reg_val.bf.tcp_flags1; - return ret; -} - -sw_error_t -hppe_l4_exception_parsing_ctrl_0_reg_tcp_flags1_set( - a_uint32_t dev_id, - a_uint32_t value) -{ - union l4_exception_parsing_ctrl_0_reg_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_l4_exception_parsing_ctrl_0_reg_get(dev_id, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.tcp_flags1 = value; - ret = hppe_l4_exception_parsing_ctrl_0_reg_set(dev_id, ®_val); - return ret; -} - -sw_error_t -hppe_l4_exception_parsing_ctrl_0_reg_tcp_flags1_mask_get( - a_uint32_t dev_id, - a_uint32_t *value) -{ - union l4_exception_parsing_ctrl_0_reg_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_l4_exception_parsing_ctrl_0_reg_get(dev_id, ®_val); - *value = reg_val.bf.tcp_flags1_mask; - return ret; -} - -sw_error_t -hppe_l4_exception_parsing_ctrl_0_reg_tcp_flags1_mask_set( - a_uint32_t dev_id, - a_uint32_t value) -{ - union l4_exception_parsing_ctrl_0_reg_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_l4_exception_parsing_ctrl_0_reg_get(dev_id, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.tcp_flags1_mask = value; - ret = hppe_l4_exception_parsing_ctrl_0_reg_set(dev_id, ®_val); - return ret; -} - -sw_error_t -hppe_l4_exception_parsing_ctrl_1_reg_tcp_flags2_get( - a_uint32_t dev_id, - a_uint32_t *value) -{ - union l4_exception_parsing_ctrl_1_reg_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_l4_exception_parsing_ctrl_1_reg_get(dev_id, ®_val); - *value = reg_val.bf.tcp_flags2; - return ret; -} - -sw_error_t -hppe_l4_exception_parsing_ctrl_1_reg_tcp_flags2_set( - a_uint32_t dev_id, - a_uint32_t value) -{ - union l4_exception_parsing_ctrl_1_reg_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_l4_exception_parsing_ctrl_1_reg_get(dev_id, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.tcp_flags2 = value; - ret = hppe_l4_exception_parsing_ctrl_1_reg_set(dev_id, ®_val); - return ret; -} - -sw_error_t -hppe_l4_exception_parsing_ctrl_1_reg_tcp_flags2_mask_get( - a_uint32_t dev_id, - a_uint32_t *value) -{ - union l4_exception_parsing_ctrl_1_reg_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_l4_exception_parsing_ctrl_1_reg_get(dev_id, ®_val); - *value = reg_val.bf.tcp_flags2_mask; - return ret; -} - -sw_error_t -hppe_l4_exception_parsing_ctrl_1_reg_tcp_flags2_mask_set( - a_uint32_t dev_id, - a_uint32_t value) -{ - union l4_exception_parsing_ctrl_1_reg_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_l4_exception_parsing_ctrl_1_reg_get(dev_id, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.tcp_flags2_mask = value; - ret = hppe_l4_exception_parsing_ctrl_1_reg_set(dev_id, ®_val); - return ret; -} - -sw_error_t -hppe_l4_exception_parsing_ctrl_1_reg_tcp_flags3_get( - a_uint32_t dev_id, - a_uint32_t *value) -{ - union l4_exception_parsing_ctrl_1_reg_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_l4_exception_parsing_ctrl_1_reg_get(dev_id, ®_val); - *value = reg_val.bf.tcp_flags3; - return ret; -} - -sw_error_t -hppe_l4_exception_parsing_ctrl_1_reg_tcp_flags3_set( - a_uint32_t dev_id, - a_uint32_t value) -{ - union l4_exception_parsing_ctrl_1_reg_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_l4_exception_parsing_ctrl_1_reg_get(dev_id, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.tcp_flags3 = value; - ret = hppe_l4_exception_parsing_ctrl_1_reg_set(dev_id, ®_val); - return ret; -} - -sw_error_t -hppe_l4_exception_parsing_ctrl_1_reg_tcp_flags3_mask_get( - a_uint32_t dev_id, - a_uint32_t *value) -{ - union l4_exception_parsing_ctrl_1_reg_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_l4_exception_parsing_ctrl_1_reg_get(dev_id, ®_val); - *value = reg_val.bf.tcp_flags3_mask; - return ret; -} - -sw_error_t -hppe_l4_exception_parsing_ctrl_1_reg_tcp_flags3_mask_set( - a_uint32_t dev_id, - a_uint32_t value) -{ - union l4_exception_parsing_ctrl_1_reg_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_l4_exception_parsing_ctrl_1_reg_get(dev_id, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.tcp_flags3_mask = value; - ret = hppe_l4_exception_parsing_ctrl_1_reg_set(dev_id, ®_val); - return ret; -} - -sw_error_t -hppe_l4_exception_parsing_ctrl_2_reg_tcp_flags4_get( - a_uint32_t dev_id, - a_uint32_t *value) -{ - union l4_exception_parsing_ctrl_2_reg_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_l4_exception_parsing_ctrl_2_reg_get(dev_id, ®_val); - *value = reg_val.bf.tcp_flags4; - return ret; -} - -sw_error_t -hppe_l4_exception_parsing_ctrl_2_reg_tcp_flags4_set( - a_uint32_t dev_id, - a_uint32_t value) -{ - union l4_exception_parsing_ctrl_2_reg_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_l4_exception_parsing_ctrl_2_reg_get(dev_id, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.tcp_flags4 = value; - ret = hppe_l4_exception_parsing_ctrl_2_reg_set(dev_id, ®_val); - return ret; -} - -sw_error_t -hppe_l4_exception_parsing_ctrl_2_reg_tcp_flags4_mask_get( - a_uint32_t dev_id, - a_uint32_t *value) -{ - union l4_exception_parsing_ctrl_2_reg_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_l4_exception_parsing_ctrl_2_reg_get(dev_id, ®_val); - *value = reg_val.bf.tcp_flags4_mask; - return ret; -} - -sw_error_t -hppe_l4_exception_parsing_ctrl_2_reg_tcp_flags4_mask_set( - a_uint32_t dev_id, - a_uint32_t value) -{ - union l4_exception_parsing_ctrl_2_reg_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_l4_exception_parsing_ctrl_2_reg_get(dev_id, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.tcp_flags4_mask = value; - ret = hppe_l4_exception_parsing_ctrl_2_reg_set(dev_id, ®_val); - return ret; -} - -sw_error_t -hppe_l4_exception_parsing_ctrl_2_reg_tcp_flags5_get( - a_uint32_t dev_id, - a_uint32_t *value) -{ - union l4_exception_parsing_ctrl_2_reg_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_l4_exception_parsing_ctrl_2_reg_get(dev_id, ®_val); - *value = reg_val.bf.tcp_flags5; - return ret; -} - -sw_error_t -hppe_l4_exception_parsing_ctrl_2_reg_tcp_flags5_set( - a_uint32_t dev_id, - a_uint32_t value) -{ - union l4_exception_parsing_ctrl_2_reg_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_l4_exception_parsing_ctrl_2_reg_get(dev_id, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.tcp_flags5 = value; - ret = hppe_l4_exception_parsing_ctrl_2_reg_set(dev_id, ®_val); - return ret; -} - -sw_error_t -hppe_l4_exception_parsing_ctrl_2_reg_tcp_flags5_mask_get( - a_uint32_t dev_id, - a_uint32_t *value) -{ - union l4_exception_parsing_ctrl_2_reg_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_l4_exception_parsing_ctrl_2_reg_get(dev_id, ®_val); - *value = reg_val.bf.tcp_flags5_mask; - return ret; -} - -sw_error_t -hppe_l4_exception_parsing_ctrl_2_reg_tcp_flags5_mask_set( - a_uint32_t dev_id, - a_uint32_t value) -{ - union l4_exception_parsing_ctrl_2_reg_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_l4_exception_parsing_ctrl_2_reg_get(dev_id, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.tcp_flags5_mask = value; - ret = hppe_l4_exception_parsing_ctrl_2_reg_set(dev_id, ®_val); - return ret; -} - -sw_error_t -hppe_l4_exception_parsing_ctrl_3_reg_tcp_flags6_get( - a_uint32_t dev_id, - a_uint32_t *value) -{ - union l4_exception_parsing_ctrl_3_reg_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_l4_exception_parsing_ctrl_3_reg_get(dev_id, ®_val); - *value = reg_val.bf.tcp_flags6; - return ret; -} - -sw_error_t -hppe_l4_exception_parsing_ctrl_3_reg_tcp_flags6_set( - a_uint32_t dev_id, - a_uint32_t value) -{ - union l4_exception_parsing_ctrl_3_reg_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_l4_exception_parsing_ctrl_3_reg_get(dev_id, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.tcp_flags6 = value; - ret = hppe_l4_exception_parsing_ctrl_3_reg_set(dev_id, ®_val); - return ret; -} - -sw_error_t -hppe_l4_exception_parsing_ctrl_3_reg_tcp_flags6_mask_get( - a_uint32_t dev_id, - a_uint32_t *value) -{ - union l4_exception_parsing_ctrl_3_reg_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_l4_exception_parsing_ctrl_3_reg_get(dev_id, ®_val); - *value = reg_val.bf.tcp_flags6_mask; - return ret; -} - -sw_error_t -hppe_l4_exception_parsing_ctrl_3_reg_tcp_flags6_mask_set( - a_uint32_t dev_id, - a_uint32_t value) -{ - union l4_exception_parsing_ctrl_3_reg_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_l4_exception_parsing_ctrl_3_reg_get(dev_id, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.tcp_flags6_mask = value; - ret = hppe_l4_exception_parsing_ctrl_3_reg_set(dev_id, ®_val); - return ret; -} - -sw_error_t -hppe_l4_exception_parsing_ctrl_3_reg_tcp_flags7_get( - a_uint32_t dev_id, - a_uint32_t *value) -{ - union l4_exception_parsing_ctrl_3_reg_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_l4_exception_parsing_ctrl_3_reg_get(dev_id, ®_val); - *value = reg_val.bf.tcp_flags7; - return ret; -} - -sw_error_t -hppe_l4_exception_parsing_ctrl_3_reg_tcp_flags7_set( - a_uint32_t dev_id, - a_uint32_t value) -{ - union l4_exception_parsing_ctrl_3_reg_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_l4_exception_parsing_ctrl_3_reg_get(dev_id, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.tcp_flags7 = value; - ret = hppe_l4_exception_parsing_ctrl_3_reg_set(dev_id, ®_val); - return ret; -} - -sw_error_t -hppe_l4_exception_parsing_ctrl_3_reg_tcp_flags7_mask_get( - a_uint32_t dev_id, - a_uint32_t *value) -{ - union l4_exception_parsing_ctrl_3_reg_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_l4_exception_parsing_ctrl_3_reg_get(dev_id, ®_val); - *value = reg_val.bf.tcp_flags7_mask; - return ret; -} - -sw_error_t -hppe_l4_exception_parsing_ctrl_3_reg_tcp_flags7_mask_set( - a_uint32_t dev_id, - a_uint32_t value) -{ - union l4_exception_parsing_ctrl_3_reg_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_l4_exception_parsing_ctrl_3_reg_get(dev_id, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.tcp_flags7_mask = value; - ret = hppe_l4_exception_parsing_ctrl_3_reg_set(dev_id, ®_val); - return ret; -} - diff --git a/feeds/ipq807x/qca-ssdk/src/src/hsl/hppe/hppe_servcode.c b/feeds/ipq807x/qca-ssdk/src/src/hsl/hppe/hppe_servcode.c deleted file mode 100755 index 0f5246a8c..000000000 --- a/feeds/ipq807x/qca-ssdk/src/src/hsl/hppe/hppe_servcode.c +++ /dev/null @@ -1,511 +0,0 @@ -/* - * Copyright (c) 2016-2017, The Linux Foundation. All rights reserved. - * Permission to use, copy, modify, and/or distribute this software for - * any purpose with or without fee is hereby granted, provided that the - * above copyright notice and this permission notice appear in all copies. - * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES - * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR - * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES - * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN - * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT - * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. - */ - - -/** - * @defgroup - * @{ - */ -#include "sw.h" -#include "hsl.h" -#include "hppe_reg_access.h" -#include "hppe_servcode_reg.h" -#include "hppe_servcode.h" - -sw_error_t -hppe_service_tbl_get( - a_uint32_t dev_id, - a_uint32_t index, - union service_tbl_u *value) -{ - return hppe_reg_tbl_get( - dev_id, - INGRESS_VLAN_BASE_ADDR + SERVICE_TBL_ADDRESS + \ - index * SERVICE_TBL_INC, - value->val, - 2); -} - -sw_error_t -hppe_service_tbl_set( - a_uint32_t dev_id, - a_uint32_t index, - union service_tbl_u *value) -{ - return hppe_reg_tbl_set( - dev_id, - INGRESS_VLAN_BASE_ADDR + SERVICE_TBL_ADDRESS + \ - index * SERVICE_TBL_INC, - value->val, - 2); -} - -sw_error_t -hppe_service_tbl_rx_counting_en_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union service_tbl_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_service_tbl_get(dev_id, index, ®_val); - *value = reg_val.bf.rx_counting_en; - return ret; -} - -sw_error_t -hppe_service_tbl_rx_counting_en_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - union service_tbl_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_service_tbl_get(dev_id, index, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.rx_counting_en = value; - ret = hppe_service_tbl_set(dev_id, index, ®_val); - return ret; -} - -sw_error_t -hppe_service_tbl_bypass_bitmap_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union service_tbl_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_service_tbl_get(dev_id, index, ®_val); - *value = reg_val.bf.bypass_bitmap; - return ret; -} - -sw_error_t -hppe_service_tbl_bypass_bitmap_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - union service_tbl_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_service_tbl_get(dev_id, index, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.bypass_bitmap = value; - ret = hppe_service_tbl_set(dev_id, index, ®_val); - return ret; -} - -sw_error_t -hppe_in_l2_service_tbl_get( - a_uint32_t dev_id, - a_uint32_t index, - union in_l2_service_tbl_u *value) -{ - if (index >= IN_L2_SERVICE_TBL_MAX_ENTRY) - return SW_OUT_OF_RANGE; - return hppe_reg_get( - dev_id, - IPE_L2_BASE_ADDR + IN_L2_SERVICE_TBL_ADDRESS + \ - index * IN_L2_SERVICE_TBL_INC, - &value->val); -} - -sw_error_t -hppe_in_l2_service_tbl_set( - a_uint32_t dev_id, - a_uint32_t index, - union in_l2_service_tbl_u *value) -{ - return hppe_reg_set( - dev_id, - IPE_L2_BASE_ADDR + IN_L2_SERVICE_TBL_ADDRESS + \ - index * IN_L2_SERVICE_TBL_INC, - value->val); -} - -sw_error_t -hppe_in_l2_service_tbl_direction_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union in_l2_service_tbl_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_in_l2_service_tbl_get(dev_id, index, ®_val); - *value = reg_val.bf.direction; - return ret; -} - -sw_error_t -hppe_in_l2_service_tbl_direction_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - union in_l2_service_tbl_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_in_l2_service_tbl_get(dev_id, index, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.direction = value; - ret = hppe_in_l2_service_tbl_set(dev_id, index, ®_val); - return ret; -} - -sw_error_t -hppe_in_l2_service_tbl_rx_cnt_en_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union in_l2_service_tbl_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_in_l2_service_tbl_get(dev_id, index, ®_val); - *value = reg_val.bf.rx_cnt_en; - return ret; -} - -sw_error_t -hppe_in_l2_service_tbl_rx_cnt_en_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - union in_l2_service_tbl_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_in_l2_service_tbl_get(dev_id, index, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.rx_cnt_en = value; - ret = hppe_in_l2_service_tbl_set(dev_id, index, ®_val); - return ret; -} - -sw_error_t -hppe_in_l2_service_tbl_tx_cnt_en_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union in_l2_service_tbl_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_in_l2_service_tbl_get(dev_id, index, ®_val); - *value = reg_val.bf.tx_cnt_en; - return ret; -} - -sw_error_t -hppe_in_l2_service_tbl_tx_cnt_en_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - union in_l2_service_tbl_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_in_l2_service_tbl_get(dev_id, index, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.tx_cnt_en = value; - ret = hppe_in_l2_service_tbl_set(dev_id, index, ®_val); - return ret; -} - -sw_error_t -hppe_in_l2_service_tbl_bypass_bitmap_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union in_l2_service_tbl_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_in_l2_service_tbl_get(dev_id, index, ®_val); - *value = reg_val.bf.bypass_bitmap; - return ret; -} - -sw_error_t -hppe_in_l2_service_tbl_bypass_bitmap_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - union in_l2_service_tbl_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_in_l2_service_tbl_get(dev_id, index, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.bypass_bitmap = value; - ret = hppe_in_l2_service_tbl_set(dev_id, index, ®_val); - return ret; -} - -sw_error_t -hppe_in_l2_service_tbl_dst_port_id_valid_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union in_l2_service_tbl_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_in_l2_service_tbl_get(dev_id, index, ®_val); - *value = reg_val.bf.dst_port_id_valid; - return ret; -} - -sw_error_t -hppe_in_l2_service_tbl_dst_port_id_valid_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - union in_l2_service_tbl_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_in_l2_service_tbl_get(dev_id, index, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.dst_port_id_valid = value; - ret = hppe_in_l2_service_tbl_set(dev_id, index, ®_val); - return ret; -} - -sw_error_t -hppe_in_l2_service_tbl_dst_port_id_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union in_l2_service_tbl_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_in_l2_service_tbl_get(dev_id, index, ®_val); - *value = reg_val.bf.dst_port_id; - return ret; -} - -sw_error_t -hppe_in_l2_service_tbl_dst_port_id_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - union in_l2_service_tbl_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_in_l2_service_tbl_get(dev_id, index, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.dst_port_id = value; - ret = hppe_in_l2_service_tbl_set(dev_id, index, ®_val); - return ret; -} - -sw_error_t -hppe_eg_service_tbl_get( - a_uint32_t dev_id, - a_uint32_t index, - union eg_service_tbl_u *value) -{ - return hppe_reg_tbl_get( - dev_id, - NSS_PTX_CSR_BASE_ADDR + EG_SERVICE_TBL_ADDRESS + \ - index * EG_SERVICE_TBL_INC, - value->val, - 2); -} - -sw_error_t -hppe_eg_service_tbl_set( - a_uint32_t dev_id, - a_uint32_t index, - union eg_service_tbl_u *value) -{ - return hppe_reg_tbl_set( - dev_id, - NSS_PTX_CSR_BASE_ADDR + EG_SERVICE_TBL_ADDRESS + \ - index * EG_SERVICE_TBL_INC, - value->val, - 2); -} - -sw_error_t -hppe_eg_service_tbl_next_service_code_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union eg_service_tbl_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_eg_service_tbl_get(dev_id, index, ®_val); - *value = reg_val.bf.next_service_code; - return ret; -} - -sw_error_t -hppe_eg_service_tbl_next_service_code_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - union eg_service_tbl_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_eg_service_tbl_get(dev_id, index, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.next_service_code = value; - ret = hppe_eg_service_tbl_set(dev_id, index, ®_val); - return ret; -} - -sw_error_t -hppe_eg_service_tbl_tx_counting_en_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union eg_service_tbl_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_eg_service_tbl_get(dev_id, index, ®_val); - *value = reg_val.bf.tx_counting_en; - return ret; -} - -sw_error_t -hppe_eg_service_tbl_tx_counting_en_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - union eg_service_tbl_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_eg_service_tbl_get(dev_id, index, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.tx_counting_en = value; - ret = hppe_eg_service_tbl_set(dev_id, index, ®_val); - return ret; -} - -sw_error_t -hppe_eg_service_tbl_field_update_action_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union eg_service_tbl_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_eg_service_tbl_get(dev_id, index, ®_val); - *value = reg_val.bf.field_update_action; - return ret; -} - -sw_error_t -hppe_eg_service_tbl_field_update_action_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - union eg_service_tbl_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_eg_service_tbl_get(dev_id, index, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.field_update_action = value; - ret = hppe_eg_service_tbl_set(dev_id, index, ®_val); - return ret; -} - -sw_error_t -hppe_eg_service_tbl_offset_sel_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union eg_service_tbl_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_eg_service_tbl_get(dev_id, index, ®_val); - *value = reg_val.bf.offset_sel; - return ret; -} - -sw_error_t -hppe_eg_service_tbl_offset_sel_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - union eg_service_tbl_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_eg_service_tbl_get(dev_id, index, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.offset_sel = value; - ret = hppe_eg_service_tbl_set(dev_id, index, ®_val); - return ret; -} - -sw_error_t -hppe_eg_service_tbl_hw_services_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union eg_service_tbl_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_eg_service_tbl_get(dev_id, index, ®_val); - *value = reg_val.bf.hw_services; - return ret; -} - -sw_error_t -hppe_eg_service_tbl_hw_services_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - union eg_service_tbl_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_eg_service_tbl_get(dev_id, index, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.hw_services = value; - ret = hppe_eg_service_tbl_set(dev_id, index, ®_val); - return ret; -} \ No newline at end of file diff --git a/feeds/ipq807x/qca-ssdk/src/src/hsl/hppe/hppe_shaper.c b/feeds/ipq807x/qca-ssdk/src/src/hsl/hppe/hppe_shaper.c deleted file mode 100755 index 339d3573b..000000000 --- a/feeds/ipq807x/qca-ssdk/src/src/hsl/hppe/hppe_shaper.c +++ /dev/null @@ -1,2396 +0,0 @@ -/* - * Copyright (c) 2016-2017, The Linux Foundation. All rights reserved. - * Permission to use, copy, modify, and/or distribute this software for - * any purpose with or without fee is hereby granted, provided that the - * above copyright notice and this permission notice appear in all copies. - * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES - * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR - * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES - * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN - * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT - * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. - */ - - -/** - * @defgroup - * @{ - */ -#include "sw.h" -#include "hsl.h" -#include "hppe_reg_access.h" -#include "hppe_shaper_reg.h" -#include "hppe_shaper.h" - -sw_error_t -hppe_shp_slot_cfg_l0_get( - a_uint32_t dev_id, - union shp_slot_cfg_l0_u *value) -{ - return hppe_reg_get( - dev_id, - TRAFFIC_MANAGER_BASE_ADDR + SHP_SLOT_CFG_L0_ADDRESS, - &value->val); -} - -sw_error_t -hppe_shp_slot_cfg_l0_set( - a_uint32_t dev_id, - union shp_slot_cfg_l0_u *value) -{ - return hppe_reg_set( - dev_id, - TRAFFIC_MANAGER_BASE_ADDR + SHP_SLOT_CFG_L0_ADDRESS, - value->val); -} - -sw_error_t -hppe_shp_slot_cfg_l1_get( - a_uint32_t dev_id, - union shp_slot_cfg_l1_u *value) -{ - return hppe_reg_get( - dev_id, - TRAFFIC_MANAGER_BASE_ADDR + SHP_SLOT_CFG_L1_ADDRESS, - &value->val); -} - -sw_error_t -hppe_shp_slot_cfg_l1_set( - a_uint32_t dev_id, - union shp_slot_cfg_l1_u *value) -{ - return hppe_reg_set( - dev_id, - TRAFFIC_MANAGER_BASE_ADDR + SHP_SLOT_CFG_L1_ADDRESS, - value->val); -} - -sw_error_t -hppe_shp_slot_cfg_port_get( - a_uint32_t dev_id, - union shp_slot_cfg_port_u *value) -{ - return hppe_reg_get( - dev_id, - TRAFFIC_MANAGER_BASE_ADDR + SHP_SLOT_CFG_PORT_ADDRESS, - &value->val); -} - -sw_error_t -hppe_shp_slot_cfg_port_set( - a_uint32_t dev_id, - union shp_slot_cfg_port_u *value) -{ - return hppe_reg_set( - dev_id, - TRAFFIC_MANAGER_BASE_ADDR + SHP_SLOT_CFG_PORT_ADDRESS, - value->val); -} - -sw_error_t -hppe_l0_shp_credit_tbl_get( - a_uint32_t dev_id, - a_uint32_t index, - union l0_shp_credit_tbl_u *value) -{ - return hppe_reg_tbl_get( - dev_id, - TRAFFIC_MANAGER_BASE_ADDR + L0_SHP_CREDIT_TBL_ADDRESS + \ - index * L0_SHP_CREDIT_TBL_INC, - value->val, - 2); -} - -sw_error_t -hppe_l0_shp_credit_tbl_set( - a_uint32_t dev_id, - a_uint32_t index, - union l0_shp_credit_tbl_u *value) -{ - return hppe_reg_tbl_set( - dev_id, - TRAFFIC_MANAGER_BASE_ADDR + L0_SHP_CREDIT_TBL_ADDRESS + \ - index * L0_SHP_CREDIT_TBL_INC, - value->val, - 2); -} - -sw_error_t -hppe_l0_shp_cfg_tbl_get( - a_uint32_t dev_id, - a_uint32_t index, - union l0_shp_cfg_tbl_u *value) -{ - return hppe_reg_tbl_get( - dev_id, - TRAFFIC_MANAGER_BASE_ADDR + L0_SHP_CFG_TBL_ADDRESS + \ - index * L0_SHP_CFG_TBL_INC, - value->val, - 3); -} - -sw_error_t -hppe_l0_shp_cfg_tbl_set( - a_uint32_t dev_id, - a_uint32_t index, - union l0_shp_cfg_tbl_u *value) -{ - return hppe_reg_tbl_set( - dev_id, - TRAFFIC_MANAGER_BASE_ADDR + L0_SHP_CFG_TBL_ADDRESS + \ - index * L0_SHP_CFG_TBL_INC, - value->val, - 3); -} - -#ifndef IN_SHAPER_MINI -sw_error_t -hppe_l0_comp_tbl_get( - a_uint32_t dev_id, - a_uint32_t index, - union l0_comp_tbl_u *value) -{ - return hppe_reg_tbl_get( - dev_id, - TRAFFIC_MANAGER_BASE_ADDR + L0_COMP_TBL_ADDRESS + \ - index * L0_COMP_TBL_INC, - value->val, - 3); -} - -sw_error_t -hppe_l0_comp_tbl_set( - a_uint32_t dev_id, - a_uint32_t index, - union l0_comp_tbl_u *value) -{ - return SW_NOT_SUPPORTED; -} -#endif - -sw_error_t -hppe_l0_comp_cfg_tbl_get( - a_uint32_t dev_id, - a_uint32_t index, - union l0_comp_cfg_tbl_u *value) -{ - if (index >= L0_COMP_CFG_TBL_MAX_ENTRY) - return SW_OUT_OF_RANGE; - return hppe_reg_get( - dev_id, - TRAFFIC_MANAGER_BASE_ADDR + L0_COMP_CFG_TBL_ADDRESS + \ - index * L0_COMP_CFG_TBL_INC, - &value->val); -} - -sw_error_t -hppe_l0_comp_cfg_tbl_set( - a_uint32_t dev_id, - a_uint32_t index, - union l0_comp_cfg_tbl_u *value) -{ - return hppe_reg_set( - dev_id, - TRAFFIC_MANAGER_BASE_ADDR + L0_COMP_CFG_TBL_ADDRESS + \ - index * L0_COMP_CFG_TBL_INC, - value->val); -} - - -sw_error_t -hppe_l1_shp_credit_tbl_get( - a_uint32_t dev_id, - a_uint32_t index, - union l1_shp_credit_tbl_u *value) -{ - return hppe_reg_tbl_get( - dev_id, - TRAFFIC_MANAGER_BASE_ADDR + L1_SHP_CREDIT_TBL_ADDRESS + \ - index * L1_SHP_CREDIT_TBL_INC, - value->val, - 2); -} - -sw_error_t -hppe_l1_shp_credit_tbl_set( - a_uint32_t dev_id, - a_uint32_t index, - union l1_shp_credit_tbl_u *value) -{ - return hppe_reg_tbl_set( - dev_id, - TRAFFIC_MANAGER_BASE_ADDR + L1_SHP_CREDIT_TBL_ADDRESS + \ - index * L1_SHP_CREDIT_TBL_INC, - value->val, - 2); -} - -#ifndef IN_SHAPER_MINI -sw_error_t -hppe_l1_shp_cfg_tbl_get( - a_uint32_t dev_id, - a_uint32_t index, - union l1_shp_cfg_tbl_u *value) -{ - return hppe_reg_tbl_get( - dev_id, - TRAFFIC_MANAGER_BASE_ADDR + L1_SHP_CFG_TBL_ADDRESS + \ - index * L1_SHP_CFG_TBL_INC, - value->val, - 3); -} -#endif - -sw_error_t -hppe_l1_shp_cfg_tbl_set( - a_uint32_t dev_id, - a_uint32_t index, - union l1_shp_cfg_tbl_u *value) -{ - return hppe_reg_tbl_set( - dev_id, - TRAFFIC_MANAGER_BASE_ADDR + L1_SHP_CFG_TBL_ADDRESS + \ - index * L1_SHP_CFG_TBL_INC, - value->val, - 3); -} - - -#ifndef IN_SHAPER_MINI -sw_error_t -hppe_l1_comp_tbl_get( - a_uint32_t dev_id, - a_uint32_t index, - union l1_comp_tbl_u *value) -{ - return hppe_reg_tbl_get( - dev_id, - TRAFFIC_MANAGER_BASE_ADDR + L1_COMP_TBL_ADDRESS + \ - index * L1_COMP_TBL_INC, - value->val, - 3); -} - -sw_error_t -hppe_l1_comp_tbl_set( - a_uint32_t dev_id, - a_uint32_t index, - union l1_comp_tbl_u *value) -{ - return SW_NOT_SUPPORTED; -} -#endif - -sw_error_t -hppe_l1_comp_cfg_tbl_get( - a_uint32_t dev_id, - a_uint32_t index, - union l1_comp_cfg_tbl_u *value) -{ - if (index >= L1_COMP_CFG_TBL_MAX_ENTRY) - return SW_OUT_OF_RANGE; - return hppe_reg_get( - dev_id, - TRAFFIC_MANAGER_BASE_ADDR + L1_COMP_CFG_TBL_ADDRESS + \ - index * L1_COMP_CFG_TBL_INC, - &value->val); -} - -sw_error_t -hppe_l1_comp_cfg_tbl_set( - a_uint32_t dev_id, - a_uint32_t index, - union l1_comp_cfg_tbl_u *value) -{ - return hppe_reg_set( - dev_id, - TRAFFIC_MANAGER_BASE_ADDR + L1_COMP_CFG_TBL_ADDRESS + \ - index * L1_COMP_CFG_TBL_INC, - value->val); -} - -sw_error_t -hppe_psch_shp_sign_tbl_get( - a_uint32_t dev_id, - a_uint32_t index, - union psch_shp_sign_tbl_u *value) -{ - if (index >= PSCH_SHP_SIGN_TBL_MAX_ENTRY) - return SW_OUT_OF_RANGE; - return hppe_reg_get( - dev_id, - TRAFFIC_MANAGER_BASE_ADDR + PSCH_SHP_SIGN_TBL_ADDRESS + \ - index * PSCH_SHP_SIGN_TBL_INC, - &value->val); -} - -sw_error_t -hppe_psch_shp_sign_tbl_set( - a_uint32_t dev_id, - a_uint32_t index, - union psch_shp_sign_tbl_u *value) -{ - return hppe_reg_set( - dev_id, - TRAFFIC_MANAGER_BASE_ADDR + PSCH_SHP_SIGN_TBL_ADDRESS + \ - index * PSCH_SHP_SIGN_TBL_INC, - value->val); -} - -sw_error_t -hppe_psch_shp_credit_tbl_get( - a_uint32_t dev_id, - a_uint32_t index, - union psch_shp_credit_tbl_u *value) -{ - if (index >= PSCH_SHP_CREDIT_TBL_MAX_ENTRY) - return SW_OUT_OF_RANGE; - return hppe_reg_get( - dev_id, - TRAFFIC_MANAGER_BASE_ADDR + PSCH_SHP_CREDIT_TBL_ADDRESS + \ - index * PSCH_SHP_CREDIT_TBL_INC, - &value->val); -} - -sw_error_t -hppe_psch_shp_credit_tbl_set( - a_uint32_t dev_id, - a_uint32_t index, - union psch_shp_credit_tbl_u *value) -{ - return hppe_reg_set( - dev_id, - TRAFFIC_MANAGER_BASE_ADDR + PSCH_SHP_CREDIT_TBL_ADDRESS + \ - index * PSCH_SHP_CREDIT_TBL_INC, - value->val); -} - -sw_error_t -hppe_psch_shp_cfg_tbl_get( - a_uint32_t dev_id, - a_uint32_t index, - union psch_shp_cfg_tbl_u *value) -{ - return hppe_reg_tbl_get( - dev_id, - TRAFFIC_MANAGER_BASE_ADDR + PSCH_SHP_CFG_TBL_ADDRESS + \ - index * PSCH_SHP_CFG_TBL_INC, - value->val, - 2); -} - -sw_error_t -hppe_psch_shp_cfg_tbl_set( - a_uint32_t dev_id, - a_uint32_t index, - union psch_shp_cfg_tbl_u *value) -{ - return hppe_reg_tbl_set( - dev_id, - TRAFFIC_MANAGER_BASE_ADDR + PSCH_SHP_CFG_TBL_ADDRESS + \ - index * PSCH_SHP_CFG_TBL_INC, - value->val, - 2); -} - -#ifndef IN_SHAPER_MINI -sw_error_t -hppe_psch_comp_tbl_get( - a_uint32_t dev_id, - a_uint32_t index, - union psch_comp_tbl_u *value) -{ - if (index >= PSCH_COMP_TBL_MAX_ENTRY) - return SW_OUT_OF_RANGE; - return hppe_reg_get( - dev_id, - TRAFFIC_MANAGER_BASE_ADDR + PSCH_COMP_TBL_ADDRESS + \ - index * PSCH_COMP_TBL_INC, - &value->val); -} - -sw_error_t -hppe_psch_comp_tbl_set( - a_uint32_t dev_id, - a_uint32_t index, - union psch_comp_tbl_u *value) -{ - return SW_NOT_SUPPORTED; -} -#endif - -sw_error_t -hppe_psch_comp_cfg_tbl_get( - a_uint32_t dev_id, - a_uint32_t index, - union psch_comp_cfg_tbl_u *value) -{ - if (index >= PSCH_COMP_CFG_TBL_MAX_ENTRY) - return SW_OUT_OF_RANGE; - return hppe_reg_get( - dev_id, - TRAFFIC_MANAGER_BASE_ADDR + PSCH_COMP_CFG_TBL_ADDRESS + \ - index * PSCH_COMP_CFG_TBL_INC, - &value->val); -} - -sw_error_t -hppe_psch_comp_cfg_tbl_set( - a_uint32_t dev_id, - a_uint32_t index, - union psch_comp_cfg_tbl_u *value) -{ - return hppe_reg_set( - dev_id, - TRAFFIC_MANAGER_BASE_ADDR + PSCH_COMP_CFG_TBL_ADDRESS + \ - index * PSCH_COMP_CFG_TBL_INC, - value->val); -} - -sw_error_t -hppe_ipg_pre_len_cfg_get( - a_uint32_t dev_id, - union ipg_pre_len_cfg_u *value) -{ - return hppe_reg_get( - dev_id, - TRAFFIC_MANAGER_BASE_ADDR + IPG_PRE_LEN_CFG_ADDRESS, - &value->val); -} - -sw_error_t -hppe_ipg_pre_len_cfg_set( - a_uint32_t dev_id, - union ipg_pre_len_cfg_u *value) -{ - return hppe_reg_set( - dev_id, - TRAFFIC_MANAGER_BASE_ADDR + IPG_PRE_LEN_CFG_ADDRESS, - value->val); -} - -#ifndef IN_SHAPER_MINI -sw_error_t -hppe_ipg_pre_len_cfg_ipg_pre_len_get( - a_uint32_t dev_id, - a_uint32_t *value) -{ - union ipg_pre_len_cfg_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_ipg_pre_len_cfg_get(dev_id, ®_val); - *value = reg_val.bf.ipg_pre_len; - return ret; -} - -sw_error_t -hppe_ipg_pre_len_cfg_ipg_pre_len_set( - a_uint32_t dev_id, - a_uint32_t value) -{ - union ipg_pre_len_cfg_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_ipg_pre_len_cfg_get(dev_id, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.ipg_pre_len = value; - ret = hppe_ipg_pre_len_cfg_set(dev_id, ®_val); - return ret; -} - - -sw_error_t -hppe_shp_slot_cfg_l0_l0_shp_slot_time_get( - a_uint32_t dev_id, - a_uint32_t *value) -{ - union shp_slot_cfg_l0_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_shp_slot_cfg_l0_get(dev_id, ®_val); - *value = reg_val.bf.l0_shp_slot_time; - return ret; -} - -sw_error_t -hppe_shp_slot_cfg_l0_l0_shp_slot_time_set( - a_uint32_t dev_id, - a_uint32_t value) -{ - union shp_slot_cfg_l0_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_shp_slot_cfg_l0_get(dev_id, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.l0_shp_slot_time = value; - ret = hppe_shp_slot_cfg_l0_set(dev_id, ®_val); - return ret; -} - -sw_error_t -hppe_shp_slot_cfg_l1_l1_shp_slot_time_get( - a_uint32_t dev_id, - a_uint32_t *value) -{ - union shp_slot_cfg_l1_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_shp_slot_cfg_l1_get(dev_id, ®_val); - *value = reg_val.bf.l1_shp_slot_time; - return ret; -} - -sw_error_t -hppe_shp_slot_cfg_l1_l1_shp_slot_time_set( - a_uint32_t dev_id, - a_uint32_t value) -{ - union shp_slot_cfg_l1_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_shp_slot_cfg_l1_get(dev_id, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.l1_shp_slot_time = value; - ret = hppe_shp_slot_cfg_l1_set(dev_id, ®_val); - return ret; -} - -sw_error_t -hppe_shp_slot_cfg_port_port_shp_slot_time_get( - a_uint32_t dev_id, - a_uint32_t *value) -{ - union shp_slot_cfg_port_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_shp_slot_cfg_port_get(dev_id, ®_val); - *value = reg_val.bf.port_shp_slot_time; - return ret; -} - -sw_error_t -hppe_shp_slot_cfg_port_port_shp_slot_time_set( - a_uint32_t dev_id, - a_uint32_t value) -{ - union shp_slot_cfg_port_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_shp_slot_cfg_port_get(dev_id, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.port_shp_slot_time = value; - ret = hppe_shp_slot_cfg_port_set(dev_id, ®_val); - return ret; -} - -sw_error_t -hppe_l0_shp_credit_tbl_e_shaper_credit_neg_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union l0_shp_credit_tbl_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_l0_shp_credit_tbl_get(dev_id, index, ®_val); - *value = reg_val.bf.e_shaper_credit_neg; - return ret; -} - -sw_error_t -hppe_l0_shp_credit_tbl_e_shaper_credit_neg_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - union l0_shp_credit_tbl_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_l0_shp_credit_tbl_get(dev_id, index, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.e_shaper_credit_neg = value; - ret = hppe_l0_shp_credit_tbl_set(dev_id, index, ®_val); - return ret; -} - -sw_error_t -hppe_l0_shp_credit_tbl_e_shaper_credit_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union l0_shp_credit_tbl_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_l0_shp_credit_tbl_get(dev_id, index, ®_val); - *value = reg_val.bf.e_shaper_credit_1 << 1 | \ - reg_val.bf.e_shaper_credit_0; - return ret; -} - -sw_error_t -hppe_l0_shp_credit_tbl_e_shaper_credit_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - union l0_shp_credit_tbl_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_l0_shp_credit_tbl_get(dev_id, index, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.e_shaper_credit_1 = value >> 1; - reg_val.bf.e_shaper_credit_0 = value & (((a_uint64_t)1<<1)-1); - ret = hppe_l0_shp_credit_tbl_set(dev_id, index, ®_val); - return ret; -} - -sw_error_t -hppe_l0_shp_credit_tbl_c_shaper_credit_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union l0_shp_credit_tbl_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_l0_shp_credit_tbl_get(dev_id, index, ®_val); - *value = reg_val.bf.c_shaper_credit; - return ret; -} - -sw_error_t -hppe_l0_shp_credit_tbl_c_shaper_credit_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - union l0_shp_credit_tbl_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_l0_shp_credit_tbl_get(dev_id, index, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.c_shaper_credit = value; - ret = hppe_l0_shp_credit_tbl_set(dev_id, index, ®_val); - return ret; -} - -sw_error_t -hppe_l0_shp_credit_tbl_c_shaper_credit_neg_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union l0_shp_credit_tbl_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_l0_shp_credit_tbl_get(dev_id, index, ®_val); - *value = reg_val.bf.c_shaper_credit_neg; - return ret; -} - -sw_error_t -hppe_l0_shp_credit_tbl_c_shaper_credit_neg_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - union l0_shp_credit_tbl_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_l0_shp_credit_tbl_get(dev_id, index, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.c_shaper_credit_neg = value; - ret = hppe_l0_shp_credit_tbl_set(dev_id, index, ®_val); - return ret; -} - -sw_error_t -hppe_l0_shp_cfg_tbl_cir_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union l0_shp_cfg_tbl_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_l0_shp_cfg_tbl_get(dev_id, index, ®_val); - *value = reg_val.bf.cir; - return ret; -} - -sw_error_t -hppe_l0_shp_cfg_tbl_cir_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - union l0_shp_cfg_tbl_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_l0_shp_cfg_tbl_get(dev_id, index, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.cir = value; - ret = hppe_l0_shp_cfg_tbl_set(dev_id, index, ®_val); - return ret; -} - -sw_error_t -hppe_l0_shp_cfg_tbl_cf_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union l0_shp_cfg_tbl_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_l0_shp_cfg_tbl_get(dev_id, index, ®_val); - *value = reg_val.bf.cf; - return ret; -} - -sw_error_t -hppe_l0_shp_cfg_tbl_cf_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - union l0_shp_cfg_tbl_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_l0_shp_cfg_tbl_get(dev_id, index, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.cf = value; - ret = hppe_l0_shp_cfg_tbl_set(dev_id, index, ®_val); - return ret; -} - -sw_error_t -hppe_l0_shp_cfg_tbl_meter_unit_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union l0_shp_cfg_tbl_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_l0_shp_cfg_tbl_get(dev_id, index, ®_val); - *value = reg_val.bf.meter_unit; - return ret; -} - -sw_error_t -hppe_l0_shp_cfg_tbl_meter_unit_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - union l0_shp_cfg_tbl_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_l0_shp_cfg_tbl_get(dev_id, index, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.meter_unit = value; - ret = hppe_l0_shp_cfg_tbl_set(dev_id, index, ®_val); - return ret; -} - -sw_error_t -hppe_l0_shp_cfg_tbl_e_shaper_enable_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union l0_shp_cfg_tbl_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_l0_shp_cfg_tbl_get(dev_id, index, ®_val); - *value = reg_val.bf.e_shaper_enable; - return ret; -} - -sw_error_t -hppe_l0_shp_cfg_tbl_e_shaper_enable_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - union l0_shp_cfg_tbl_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_l0_shp_cfg_tbl_get(dev_id, index, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.e_shaper_enable = value; - ret = hppe_l0_shp_cfg_tbl_set(dev_id, index, ®_val); - return ret; -} - -sw_error_t -hppe_l0_shp_cfg_tbl_c_shaper_enable_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union l0_shp_cfg_tbl_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_l0_shp_cfg_tbl_get(dev_id, index, ®_val); - *value = reg_val.bf.c_shaper_enable; - return ret; -} - -sw_error_t -hppe_l0_shp_cfg_tbl_c_shaper_enable_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - union l0_shp_cfg_tbl_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_l0_shp_cfg_tbl_get(dev_id, index, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.c_shaper_enable = value; - ret = hppe_l0_shp_cfg_tbl_set(dev_id, index, ®_val); - return ret; -} - -sw_error_t -hppe_l0_shp_cfg_tbl_eir_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union l0_shp_cfg_tbl_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_l0_shp_cfg_tbl_get(dev_id, index, ®_val); - *value = reg_val.bf.eir; - return ret; -} - -sw_error_t -hppe_l0_shp_cfg_tbl_eir_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - union l0_shp_cfg_tbl_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_l0_shp_cfg_tbl_get(dev_id, index, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.eir = value; - ret = hppe_l0_shp_cfg_tbl_set(dev_id, index, ®_val); - return ret; -} - -sw_error_t -hppe_l0_shp_cfg_tbl_token_unit_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union l0_shp_cfg_tbl_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_l0_shp_cfg_tbl_get(dev_id, index, ®_val); - *value = reg_val.bf.token_unit; - return ret; -} - -sw_error_t -hppe_l0_shp_cfg_tbl_token_unit_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - union l0_shp_cfg_tbl_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_l0_shp_cfg_tbl_get(dev_id, index, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.token_unit = value; - ret = hppe_l0_shp_cfg_tbl_set(dev_id, index, ®_val); - return ret; -} - -sw_error_t -hppe_l0_shp_cfg_tbl_cbs_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union l0_shp_cfg_tbl_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_l0_shp_cfg_tbl_get(dev_id, index, ®_val); - *value = reg_val.bf.cbs; - return ret; -} - -sw_error_t -hppe_l0_shp_cfg_tbl_cbs_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - union l0_shp_cfg_tbl_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_l0_shp_cfg_tbl_get(dev_id, index, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.cbs = value; - ret = hppe_l0_shp_cfg_tbl_set(dev_id, index, ®_val); - return ret; -} - -sw_error_t -hppe_l0_shp_cfg_tbl_ebs_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union l0_shp_cfg_tbl_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_l0_shp_cfg_tbl_get(dev_id, index, ®_val); - *value = reg_val.bf.ebs; - return ret; -} - -sw_error_t -hppe_l0_shp_cfg_tbl_ebs_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - union l0_shp_cfg_tbl_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_l0_shp_cfg_tbl_get(dev_id, index, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.ebs = value; - ret = hppe_l0_shp_cfg_tbl_set(dev_id, index, ®_val); - return ret; -} - -sw_error_t -hppe_l0_comp_tbl_c_drr_compensate_byte_cnt_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union l0_comp_tbl_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_l0_comp_tbl_get(dev_id, index, ®_val); - *value = reg_val.bf.c_drr_compensate_byte_cnt_1 << 9 | \ - reg_val.bf.c_drr_compensate_byte_cnt_0; - return ret; -} - -sw_error_t -hppe_l0_comp_tbl_c_drr_compensate_byte_cnt_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - return SW_NOT_SUPPORTED; -} - -sw_error_t -hppe_l0_comp_tbl_e_drr_compensate_byte_cnt_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union l0_comp_tbl_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_l0_comp_tbl_get(dev_id, index, ®_val); - *value = reg_val.bf.e_drr_compensate_byte_cnt; - return ret; -} - -sw_error_t -hppe_l0_comp_tbl_e_drr_compensate_byte_cnt_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - return SW_NOT_SUPPORTED; -} - -sw_error_t -hppe_l0_comp_tbl_c_shaper_compensate_byte_neg_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union l0_comp_tbl_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_l0_comp_tbl_get(dev_id, index, ®_val); - *value = reg_val.bf.c_shaper_compensate_byte_neg; - return ret; -} - -sw_error_t -hppe_l0_comp_tbl_c_shaper_compensate_byte_neg_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - return SW_NOT_SUPPORTED; -} - -sw_error_t -hppe_l0_comp_tbl_c_shaper_compensate_pkt_cnt_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union l0_comp_tbl_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_l0_comp_tbl_get(dev_id, index, ®_val); - *value = reg_val.bf.c_shaper_compensate_pkt_cnt; - return ret; -} - -sw_error_t -hppe_l0_comp_tbl_c_shaper_compensate_pkt_cnt_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - return SW_NOT_SUPPORTED; -} - -sw_error_t -hppe_l0_comp_tbl_c_shaper_compensate_byte_cnt_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union l0_comp_tbl_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_l0_comp_tbl_get(dev_id, index, ®_val); - *value = reg_val.bf.c_shaper_compensate_byte_cnt; - return ret; -} - -sw_error_t -hppe_l0_comp_tbl_c_shaper_compensate_byte_cnt_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - return SW_NOT_SUPPORTED; -} - -sw_error_t -hppe_l0_comp_tbl_e_shaper_compensate_pkt_cnt_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union l0_comp_tbl_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_l0_comp_tbl_get(dev_id, index, ®_val); - *value = reg_val.bf.e_shaper_compensate_pkt_cnt; - return ret; -} - -sw_error_t -hppe_l0_comp_tbl_e_shaper_compensate_pkt_cnt_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - return SW_NOT_SUPPORTED; -} - -sw_error_t -hppe_l0_comp_tbl_e_drr_compensate_pkt_cnt_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union l0_comp_tbl_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_l0_comp_tbl_get(dev_id, index, ®_val); - *value = reg_val.bf.e_drr_compensate_pkt_cnt; - return ret; -} - -sw_error_t -hppe_l0_comp_tbl_e_drr_compensate_pkt_cnt_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - return SW_NOT_SUPPORTED; -} - -sw_error_t -hppe_l0_comp_tbl_e_drr_compensate_byte_neg_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union l0_comp_tbl_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_l0_comp_tbl_get(dev_id, index, ®_val); - *value = reg_val.bf.e_drr_compensate_byte_neg; - return ret; -} - -sw_error_t -hppe_l0_comp_tbl_e_drr_compensate_byte_neg_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - return SW_NOT_SUPPORTED; -} - -sw_error_t -hppe_l0_comp_tbl_c_drr_compensate_pkt_cnt_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union l0_comp_tbl_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_l0_comp_tbl_get(dev_id, index, ®_val); - *value = reg_val.bf.c_drr_compensate_pkt_cnt; - return ret; -} - -sw_error_t -hppe_l0_comp_tbl_c_drr_compensate_pkt_cnt_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - return SW_NOT_SUPPORTED; -} - -sw_error_t -hppe_l0_comp_tbl_c_drr_compensate_byte_neg_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union l0_comp_tbl_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_l0_comp_tbl_get(dev_id, index, ®_val); - *value = reg_val.bf.c_drr_compensate_byte_neg; - return ret; -} - -sw_error_t -hppe_l0_comp_tbl_c_drr_compensate_byte_neg_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - return SW_NOT_SUPPORTED; -} - -sw_error_t -hppe_l0_comp_tbl_e_shaper_compensate_byte_cnt_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union l0_comp_tbl_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_l0_comp_tbl_get(dev_id, index, ®_val); - *value = reg_val.bf.e_shaper_compensate_byte_cnt; - return ret; -} - -sw_error_t -hppe_l0_comp_tbl_e_shaper_compensate_byte_cnt_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - return SW_NOT_SUPPORTED; -} - -sw_error_t -hppe_l0_comp_tbl_e_shaper_compensate_byte_neg_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union l0_comp_tbl_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_l0_comp_tbl_get(dev_id, index, ®_val); - *value = reg_val.bf.e_shaper_compensate_byte_neg; - return ret; -} - -sw_error_t -hppe_l0_comp_tbl_e_shaper_compensate_byte_neg_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - return SW_NOT_SUPPORTED; -} - -sw_error_t -hppe_l0_comp_cfg_tbl_drr_meter_len_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union l0_comp_cfg_tbl_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_l0_comp_cfg_tbl_get(dev_id, index, ®_val); - *value = reg_val.bf.drr_meter_len; - return ret; -} - -sw_error_t -hppe_l0_comp_cfg_tbl_drr_meter_len_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - union l0_comp_cfg_tbl_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_l0_comp_cfg_tbl_get(dev_id, index, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.drr_meter_len = value; - ret = hppe_l0_comp_cfg_tbl_set(dev_id, index, ®_val); - return ret; -} - -sw_error_t -hppe_l0_comp_cfg_tbl_shaper_meter_len_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union l0_comp_cfg_tbl_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_l0_comp_cfg_tbl_get(dev_id, index, ®_val); - *value = reg_val.bf.shaper_meter_len; - return ret; -} - -sw_error_t -hppe_l0_comp_cfg_tbl_shaper_meter_len_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - union l0_comp_cfg_tbl_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_l0_comp_cfg_tbl_get(dev_id, index, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.shaper_meter_len = value; - ret = hppe_l0_comp_cfg_tbl_set(dev_id, index, ®_val); - return ret; -} - -sw_error_t -hppe_l1_shp_credit_tbl_e_shaper_credit_neg_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union l1_shp_credit_tbl_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_l1_shp_credit_tbl_get(dev_id, index, ®_val); - *value = reg_val.bf.e_shaper_credit_neg; - return ret; -} - -sw_error_t -hppe_l1_shp_credit_tbl_e_shaper_credit_neg_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - union l1_shp_credit_tbl_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_l1_shp_credit_tbl_get(dev_id, index, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.e_shaper_credit_neg = value; - ret = hppe_l1_shp_credit_tbl_set(dev_id, index, ®_val); - return ret; -} - -sw_error_t -hppe_l1_shp_credit_tbl_e_shaper_credit_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union l1_shp_credit_tbl_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_l1_shp_credit_tbl_get(dev_id, index, ®_val); - *value = reg_val.bf.e_shaper_credit_1 << 1 | \ - reg_val.bf.e_shaper_credit_0; - return ret; -} - -sw_error_t -hppe_l1_shp_credit_tbl_e_shaper_credit_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - union l1_shp_credit_tbl_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_l1_shp_credit_tbl_get(dev_id, index, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.e_shaper_credit_1 = value >> 1; - reg_val.bf.e_shaper_credit_0 = value & (((a_uint64_t)1<<1)-1); - ret = hppe_l1_shp_credit_tbl_set(dev_id, index, ®_val); - return ret; -} - -sw_error_t -hppe_l1_shp_credit_tbl_c_shaper_credit_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union l1_shp_credit_tbl_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_l1_shp_credit_tbl_get(dev_id, index, ®_val); - *value = reg_val.bf.c_shaper_credit; - return ret; -} - -sw_error_t -hppe_l1_shp_credit_tbl_c_shaper_credit_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - union l1_shp_credit_tbl_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_l1_shp_credit_tbl_get(dev_id, index, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.c_shaper_credit = value; - ret = hppe_l1_shp_credit_tbl_set(dev_id, index, ®_val); - return ret; -} - -sw_error_t -hppe_l1_shp_credit_tbl_c_shaper_credit_neg_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union l1_shp_credit_tbl_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_l1_shp_credit_tbl_get(dev_id, index, ®_val); - *value = reg_val.bf.c_shaper_credit_neg; - return ret; -} - -sw_error_t -hppe_l1_shp_credit_tbl_c_shaper_credit_neg_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - union l1_shp_credit_tbl_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_l1_shp_credit_tbl_get(dev_id, index, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.c_shaper_credit_neg = value; - ret = hppe_l1_shp_credit_tbl_set(dev_id, index, ®_val); - return ret; -} - -sw_error_t -hppe_l1_shp_cfg_tbl_cir_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union l1_shp_cfg_tbl_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_l1_shp_cfg_tbl_get(dev_id, index, ®_val); - *value = reg_val.bf.cir; - return ret; -} - -sw_error_t -hppe_l1_shp_cfg_tbl_cir_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - union l1_shp_cfg_tbl_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_l1_shp_cfg_tbl_get(dev_id, index, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.cir = value; - ret = hppe_l1_shp_cfg_tbl_set(dev_id, index, ®_val); - return ret; -} - -sw_error_t -hppe_l1_shp_cfg_tbl_cf_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union l1_shp_cfg_tbl_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_l1_shp_cfg_tbl_get(dev_id, index, ®_val); - *value = reg_val.bf.cf; - return ret; -} - -sw_error_t -hppe_l1_shp_cfg_tbl_cf_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - union l1_shp_cfg_tbl_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_l1_shp_cfg_tbl_get(dev_id, index, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.cf = value; - ret = hppe_l1_shp_cfg_tbl_set(dev_id, index, ®_val); - return ret; -} - -sw_error_t -hppe_l1_shp_cfg_tbl_meter_unit_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union l1_shp_cfg_tbl_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_l1_shp_cfg_tbl_get(dev_id, index, ®_val); - *value = reg_val.bf.meter_unit; - return ret; -} - -sw_error_t -hppe_l1_shp_cfg_tbl_meter_unit_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - union l1_shp_cfg_tbl_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_l1_shp_cfg_tbl_get(dev_id, index, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.meter_unit = value; - ret = hppe_l1_shp_cfg_tbl_set(dev_id, index, ®_val); - return ret; -} - -sw_error_t -hppe_l1_shp_cfg_tbl_e_shaper_enable_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union l1_shp_cfg_tbl_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_l1_shp_cfg_tbl_get(dev_id, index, ®_val); - *value = reg_val.bf.e_shaper_enable; - return ret; -} - -sw_error_t -hppe_l1_shp_cfg_tbl_e_shaper_enable_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - union l1_shp_cfg_tbl_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_l1_shp_cfg_tbl_get(dev_id, index, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.e_shaper_enable = value; - ret = hppe_l1_shp_cfg_tbl_set(dev_id, index, ®_val); - return ret; -} - -sw_error_t -hppe_l1_shp_cfg_tbl_c_shaper_enable_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union l1_shp_cfg_tbl_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_l1_shp_cfg_tbl_get(dev_id, index, ®_val); - *value = reg_val.bf.c_shaper_enable; - return ret; -} - -sw_error_t -hppe_l1_shp_cfg_tbl_c_shaper_enable_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - union l1_shp_cfg_tbl_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_l1_shp_cfg_tbl_get(dev_id, index, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.c_shaper_enable = value; - ret = hppe_l1_shp_cfg_tbl_set(dev_id, index, ®_val); - return ret; -} - -sw_error_t -hppe_l1_shp_cfg_tbl_eir_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union l1_shp_cfg_tbl_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_l1_shp_cfg_tbl_get(dev_id, index, ®_val); - *value = reg_val.bf.eir; - return ret; -} - -sw_error_t -hppe_l1_shp_cfg_tbl_eir_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - union l1_shp_cfg_tbl_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_l1_shp_cfg_tbl_get(dev_id, index, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.eir = value; - ret = hppe_l1_shp_cfg_tbl_set(dev_id, index, ®_val); - return ret; -} - -sw_error_t -hppe_l1_shp_cfg_tbl_token_unit_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union l1_shp_cfg_tbl_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_l1_shp_cfg_tbl_get(dev_id, index, ®_val); - *value = reg_val.bf.token_unit; - return ret; -} - -sw_error_t -hppe_l1_shp_cfg_tbl_token_unit_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - union l1_shp_cfg_tbl_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_l1_shp_cfg_tbl_get(dev_id, index, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.token_unit = value; - ret = hppe_l1_shp_cfg_tbl_set(dev_id, index, ®_val); - return ret; -} - -sw_error_t -hppe_l1_shp_cfg_tbl_cbs_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union l1_shp_cfg_tbl_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_l1_shp_cfg_tbl_get(dev_id, index, ®_val); - *value = reg_val.bf.cbs; - return ret; -} - -sw_error_t -hppe_l1_shp_cfg_tbl_cbs_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - union l1_shp_cfg_tbl_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_l1_shp_cfg_tbl_get(dev_id, index, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.cbs = value; - ret = hppe_l1_shp_cfg_tbl_set(dev_id, index, ®_val); - return ret; -} - -sw_error_t -hppe_l1_shp_cfg_tbl_ebs_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union l1_shp_cfg_tbl_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_l1_shp_cfg_tbl_get(dev_id, index, ®_val); - *value = reg_val.bf.ebs; - return ret; -} - -sw_error_t -hppe_l1_shp_cfg_tbl_ebs_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - union l1_shp_cfg_tbl_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_l1_shp_cfg_tbl_get(dev_id, index, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.ebs = value; - ret = hppe_l1_shp_cfg_tbl_set(dev_id, index, ®_val); - return ret; -} - -sw_error_t -hppe_l1_comp_tbl_c_drr_compensate_byte_cnt_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union l1_comp_tbl_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_l1_comp_tbl_get(dev_id, index, ®_val); - *value = reg_val.bf.c_drr_compensate_byte_cnt_1 << 9 | \ - reg_val.bf.c_drr_compensate_byte_cnt_0; - return ret; -} - -sw_error_t -hppe_l1_comp_tbl_c_drr_compensate_byte_cnt_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - return SW_NOT_SUPPORTED; -} - -sw_error_t -hppe_l1_comp_tbl_e_drr_compensate_byte_cnt_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union l1_comp_tbl_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_l1_comp_tbl_get(dev_id, index, ®_val); - *value = reg_val.bf.e_drr_compensate_byte_cnt; - return ret; -} - -sw_error_t -hppe_l1_comp_tbl_e_drr_compensate_byte_cnt_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - return SW_NOT_SUPPORTED; -} - -sw_error_t -hppe_l1_comp_tbl_c_shaper_compensate_byte_neg_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union l1_comp_tbl_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_l1_comp_tbl_get(dev_id, index, ®_val); - *value = reg_val.bf.c_shaper_compensate_byte_neg; - return ret; -} - -sw_error_t -hppe_l1_comp_tbl_c_shaper_compensate_byte_neg_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - return SW_NOT_SUPPORTED; -} - -sw_error_t -hppe_l1_comp_tbl_c_shaper_compensate_pkt_cnt_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union l1_comp_tbl_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_l1_comp_tbl_get(dev_id, index, ®_val); - *value = reg_val.bf.c_shaper_compensate_pkt_cnt; - return ret; -} - -sw_error_t -hppe_l1_comp_tbl_c_shaper_compensate_pkt_cnt_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - return SW_NOT_SUPPORTED; -} - -sw_error_t -hppe_l1_comp_tbl_c_shaper_compensate_byte_cnt_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union l1_comp_tbl_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_l1_comp_tbl_get(dev_id, index, ®_val); - *value = reg_val.bf.c_shaper_compensate_byte_cnt; - return ret; -} - -sw_error_t -hppe_l1_comp_tbl_c_shaper_compensate_byte_cnt_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - return SW_NOT_SUPPORTED; -} - -sw_error_t -hppe_l1_comp_tbl_e_shaper_compensate_pkt_cnt_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union l1_comp_tbl_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_l1_comp_tbl_get(dev_id, index, ®_val); - *value = reg_val.bf.e_shaper_compensate_pkt_cnt; - return ret; -} - -sw_error_t -hppe_l1_comp_tbl_e_shaper_compensate_pkt_cnt_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - return SW_NOT_SUPPORTED; -} - -sw_error_t -hppe_l1_comp_tbl_e_drr_compensate_pkt_cnt_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union l1_comp_tbl_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_l1_comp_tbl_get(dev_id, index, ®_val); - *value = reg_val.bf.e_drr_compensate_pkt_cnt; - return ret; -} - -sw_error_t -hppe_l1_comp_tbl_e_drr_compensate_pkt_cnt_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - return SW_NOT_SUPPORTED; -} - -sw_error_t -hppe_l1_comp_tbl_e_drr_compensate_byte_neg_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union l1_comp_tbl_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_l1_comp_tbl_get(dev_id, index, ®_val); - *value = reg_val.bf.e_drr_compensate_byte_neg; - return ret; -} - -sw_error_t -hppe_l1_comp_tbl_e_drr_compensate_byte_neg_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - return SW_NOT_SUPPORTED; -} - -sw_error_t -hppe_l1_comp_tbl_c_drr_compensate_pkt_cnt_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union l1_comp_tbl_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_l1_comp_tbl_get(dev_id, index, ®_val); - *value = reg_val.bf.c_drr_compensate_pkt_cnt; - return ret; -} - -sw_error_t -hppe_l1_comp_tbl_c_drr_compensate_pkt_cnt_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - return SW_NOT_SUPPORTED; -} - -sw_error_t -hppe_l1_comp_tbl_c_drr_compensate_byte_neg_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union l1_comp_tbl_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_l1_comp_tbl_get(dev_id, index, ®_val); - *value = reg_val.bf.c_drr_compensate_byte_neg; - return ret; -} - -sw_error_t -hppe_l1_comp_tbl_c_drr_compensate_byte_neg_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - return SW_NOT_SUPPORTED; -} - -sw_error_t -hppe_l1_comp_tbl_e_shaper_compensate_byte_cnt_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union l1_comp_tbl_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_l1_comp_tbl_get(dev_id, index, ®_val); - *value = reg_val.bf.e_shaper_compensate_byte_cnt; - return ret; -} - -sw_error_t -hppe_l1_comp_tbl_e_shaper_compensate_byte_cnt_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - return SW_NOT_SUPPORTED; -} - -sw_error_t -hppe_l1_comp_tbl_e_shaper_compensate_byte_neg_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union l1_comp_tbl_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_l1_comp_tbl_get(dev_id, index, ®_val); - *value = reg_val.bf.e_shaper_compensate_byte_neg; - return ret; -} - -sw_error_t -hppe_l1_comp_tbl_e_shaper_compensate_byte_neg_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - return SW_NOT_SUPPORTED; -} - -sw_error_t -hppe_l1_comp_cfg_tbl_drr_meter_len_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union l1_comp_cfg_tbl_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_l1_comp_cfg_tbl_get(dev_id, index, ®_val); - *value = reg_val.bf.drr_meter_len; - return ret; -} - -sw_error_t -hppe_l1_comp_cfg_tbl_drr_meter_len_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - union l1_comp_cfg_tbl_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_l1_comp_cfg_tbl_get(dev_id, index, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.drr_meter_len = value; - ret = hppe_l1_comp_cfg_tbl_set(dev_id, index, ®_val); - return ret; -} - -sw_error_t -hppe_l1_comp_cfg_tbl_shaper_meter_len_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union l1_comp_cfg_tbl_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_l1_comp_cfg_tbl_get(dev_id, index, ®_val); - *value = reg_val.bf.shaper_meter_len; - return ret; -} - -sw_error_t -hppe_l1_comp_cfg_tbl_shaper_meter_len_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - union l1_comp_cfg_tbl_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_l1_comp_cfg_tbl_get(dev_id, index, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.shaper_meter_len = value; - ret = hppe_l1_comp_cfg_tbl_set(dev_id, index, ®_val); - return ret; -} - -sw_error_t -hppe_psch_shp_sign_tbl_shaper_credit_neg_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union psch_shp_sign_tbl_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_psch_shp_sign_tbl_get(dev_id, index, ®_val); - *value = reg_val.bf.shaper_credit_neg; - return ret; -} - -sw_error_t -hppe_psch_shp_sign_tbl_shaper_credit_neg_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - union psch_shp_sign_tbl_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_psch_shp_sign_tbl_get(dev_id, index, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.shaper_credit_neg = value; - ret = hppe_psch_shp_sign_tbl_set(dev_id, index, ®_val); - return ret; -} - -sw_error_t -hppe_psch_shp_credit_tbl_shaper_credit_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union psch_shp_credit_tbl_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_psch_shp_credit_tbl_get(dev_id, index, ®_val); - *value = reg_val.bf.shaper_credit; - return ret; -} - -sw_error_t -hppe_psch_shp_credit_tbl_shaper_credit_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - union psch_shp_credit_tbl_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_psch_shp_credit_tbl_get(dev_id, index, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.shaper_credit = value; - ret = hppe_psch_shp_credit_tbl_set(dev_id, index, ®_val); - return ret; -} - -sw_error_t -hppe_psch_shp_cfg_tbl_cir_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union psch_shp_cfg_tbl_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_psch_shp_cfg_tbl_get(dev_id, index, ®_val); - *value = reg_val.bf.cir; - return ret; -} - -sw_error_t -hppe_psch_shp_cfg_tbl_cir_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - union psch_shp_cfg_tbl_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_psch_shp_cfg_tbl_get(dev_id, index, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.cir = value; - ret = hppe_psch_shp_cfg_tbl_set(dev_id, index, ®_val); - return ret; -} - -sw_error_t -hppe_psch_shp_cfg_tbl_meter_unit_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union psch_shp_cfg_tbl_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_psch_shp_cfg_tbl_get(dev_id, index, ®_val); - *value = reg_val.bf.meter_unit; - return ret; -} - -sw_error_t -hppe_psch_shp_cfg_tbl_meter_unit_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - union psch_shp_cfg_tbl_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_psch_shp_cfg_tbl_get(dev_id, index, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.meter_unit = value; - ret = hppe_psch_shp_cfg_tbl_set(dev_id, index, ®_val); - return ret; -} - -sw_error_t -hppe_psch_shp_cfg_tbl_token_unit_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union psch_shp_cfg_tbl_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_psch_shp_cfg_tbl_get(dev_id, index, ®_val); - *value = reg_val.bf.token_unit; - return ret; -} - -sw_error_t -hppe_psch_shp_cfg_tbl_token_unit_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - union psch_shp_cfg_tbl_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_psch_shp_cfg_tbl_get(dev_id, index, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.token_unit = value; - ret = hppe_psch_shp_cfg_tbl_set(dev_id, index, ®_val); - return ret; -} - -sw_error_t -hppe_psch_shp_cfg_tbl_cbs_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union psch_shp_cfg_tbl_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_psch_shp_cfg_tbl_get(dev_id, index, ®_val); - *value = reg_val.bf.cbs; - return ret; -} - -sw_error_t -hppe_psch_shp_cfg_tbl_cbs_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - union psch_shp_cfg_tbl_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_psch_shp_cfg_tbl_get(dev_id, index, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.cbs = value; - ret = hppe_psch_shp_cfg_tbl_set(dev_id, index, ®_val); - return ret; -} - -sw_error_t -hppe_psch_shp_cfg_tbl_shaper_enable_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union psch_shp_cfg_tbl_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_psch_shp_cfg_tbl_get(dev_id, index, ®_val); - *value = reg_val.bf.shaper_enable; - return ret; -} - -sw_error_t -hppe_psch_shp_cfg_tbl_shaper_enable_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - union psch_shp_cfg_tbl_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_psch_shp_cfg_tbl_get(dev_id, index, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.shaper_enable = value; - ret = hppe_psch_shp_cfg_tbl_set(dev_id, index, ®_val); - return ret; -} - -sw_error_t -hppe_psch_comp_tbl_shaper_compensate_byte_neg_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union psch_comp_tbl_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_psch_comp_tbl_get(dev_id, index, ®_val); - *value = reg_val.bf.shaper_compensate_byte_neg; - return ret; -} - -sw_error_t -hppe_psch_comp_tbl_shaper_compensate_byte_neg_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - return SW_NOT_SUPPORTED; -} - -sw_error_t -hppe_psch_comp_tbl_shaper_compensate_pkt_cnt_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union psch_comp_tbl_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_psch_comp_tbl_get(dev_id, index, ®_val); - *value = reg_val.bf.shaper_compensate_pkt_cnt; - return ret; -} - -sw_error_t -hppe_psch_comp_tbl_shaper_compensate_pkt_cnt_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - return SW_NOT_SUPPORTED; -} - -sw_error_t -hppe_psch_comp_tbl_shaper_compensate_byte_cnt_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union psch_comp_tbl_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_psch_comp_tbl_get(dev_id, index, ®_val); - *value = reg_val.bf.shaper_compensate_byte_cnt; - return ret; -} - -sw_error_t -hppe_psch_comp_tbl_shaper_compensate_byte_cnt_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - return SW_NOT_SUPPORTED; -} - -sw_error_t -hppe_psch_comp_cfg_tbl_shaper_meter_len_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union psch_comp_cfg_tbl_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_psch_comp_cfg_tbl_get(dev_id, index, ®_val); - *value = reg_val.bf.shaper_meter_len; - return ret; -} - -sw_error_t -hppe_psch_comp_cfg_tbl_shaper_meter_len_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - union psch_comp_cfg_tbl_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_psch_comp_cfg_tbl_get(dev_id, index, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.shaper_meter_len = value; - ret = hppe_psch_comp_cfg_tbl_set(dev_id, index, ®_val); - return ret; -} -#endif diff --git a/feeds/ipq807x/qca-ssdk/src/src/hsl/hppe/hppe_stp.c b/feeds/ipq807x/qca-ssdk/src/src/hsl/hppe/hppe_stp.c deleted file mode 100755 index a6b4b82fb..000000000 --- a/feeds/ipq807x/qca-ssdk/src/src/hsl/hppe/hppe_stp.c +++ /dev/null @@ -1,85 +0,0 @@ -/* - * Copyright (c) 2016-2017, The Linux Foundation. All rights reserved. - * Permission to use, copy, modify, and/or distribute this software for - * any purpose with or without fee is hereby granted, provided that the - * above copyright notice and this permission notice appear in all copies. - * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES - * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR - * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES - * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN - * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT - * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. - */ - - -/** - * @defgroup - * @{ - */ -#include "sw.h" -#include "hsl.h" -#include "hppe_reg_access.h" -#include "hppe_stp_reg.h" -#include "hppe_stp.h" - -sw_error_t -hppe_cst_state_get( - a_uint32_t dev_id, - a_uint32_t index, - union cst_state_u *value) -{ - if (index >= CST_STATE_MAX_ENTRY) - return SW_OUT_OF_RANGE; - return hppe_reg_get( - dev_id, - IPE_L2_BASE_ADDR + CST_STATE_ADDRESS + \ - index * CST_STATE_INC, - &value->val); -} - -sw_error_t -hppe_cst_state_set( - a_uint32_t dev_id, - a_uint32_t index, - union cst_state_u *value) -{ - return hppe_reg_set( - dev_id, - IPE_L2_BASE_ADDR + CST_STATE_ADDRESS + \ - index * CST_STATE_INC, - value->val); -} - -sw_error_t -hppe_cst_state_port_state_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union cst_state_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_cst_state_get(dev_id, index, ®_val); - *value = reg_val.bf.port_state; - return ret; -} - -sw_error_t -hppe_cst_state_port_state_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - union cst_state_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_cst_state_get(dev_id, index, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.port_state = value; - ret = hppe_cst_state_set(dev_id, index, ®_val); - return ret; -} - - diff --git a/feeds/ipq807x/qca-ssdk/src/src/hsl/hppe/hppe_trunk.c b/feeds/ipq807x/qca-ssdk/src/src/hsl/hppe/hppe_trunk.c deleted file mode 100755 index d9db536b8..000000000 --- a/feeds/ipq807x/qca-ssdk/src/src/hsl/hppe/hppe_trunk.c +++ /dev/null @@ -1,790 +0,0 @@ -/* - * Copyright (c) 2016-2017, The Linux Foundation. All rights reserved. - * Permission to use, copy, modify, and/or distribute this software for - * any purpose with or without fee is hereby granted, provided that the - * above copyright notice and this permission notice appear in all copies. - * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES - * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR - * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES - * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN - * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT - * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. - */ - - -/** - * @defgroup - * @{ - */ -#include "sw.h" -#include "hsl.h" -#include "hppe_reg_access.h" -#include "hppe_trunk_reg.h" -#include "hppe_trunk.h" - -sw_error_t -hppe_trunk_hash_field_reg_get( - a_uint32_t dev_id, - union trunk_hash_field_reg_u *value) -{ - return hppe_reg_get( - dev_id, - IPR_CSR_BASE_ADDR + TRUNK_HASH_FIELD_REG_ADDRESS, - &value->val); -} - -sw_error_t -hppe_trunk_hash_field_reg_set( - a_uint32_t dev_id, - union trunk_hash_field_reg_u *value) -{ - return hppe_reg_set( - dev_id, - IPR_CSR_BASE_ADDR + TRUNK_HASH_FIELD_REG_ADDRESS, - value->val); -} - -sw_error_t -hppe_trunk_filter_get( - a_uint32_t dev_id, - a_uint32_t index, - union trunk_filter_u *value) -{ - if (index >= TRUNK_FILTER_MAX_ENTRY) - return SW_OUT_OF_RANGE; - return hppe_reg_get( - dev_id, - IPE_L2_BASE_ADDR + TRUNK_FILTER_ADDRESS + \ - index * TRUNK_FILTER_INC, - &value->val); -} - -sw_error_t -hppe_trunk_filter_set( - a_uint32_t dev_id, - a_uint32_t index, - union trunk_filter_u *value) -{ - return hppe_reg_set( - dev_id, - IPE_L2_BASE_ADDR + TRUNK_FILTER_ADDRESS + \ - index * TRUNK_FILTER_INC, - value->val); -} - -sw_error_t -hppe_trunk_member_get( - a_uint32_t dev_id, - a_uint32_t index, - union trunk_member_u *value) -{ - if (index >= TRUNK_MEMBER_MAX_ENTRY) - return SW_OUT_OF_RANGE; - return hppe_reg_get( - dev_id, - IPE_L2_BASE_ADDR + TRUNK_MEMBER_ADDRESS + \ - index * TRUNK_MEMBER_INC, - &value->val); -} - -sw_error_t -hppe_trunk_member_set( - a_uint32_t dev_id, - a_uint32_t index, - union trunk_member_u *value) -{ - return hppe_reg_set( - dev_id, - IPE_L2_BASE_ADDR + TRUNK_MEMBER_ADDRESS + \ - index * TRUNK_MEMBER_INC, - value->val); -} -sw_error_t -hppe_port_trunk_id_get( - a_uint32_t dev_id, - a_uint32_t index, - union port_trunk_id_u *value) -{ - if (index >= PORT_TRUNK_ID_MAX_ENTRY) - return SW_OUT_OF_RANGE; - return hppe_reg_get( - dev_id, - IPE_L2_BASE_ADDR + PORT_TRUNK_ID_ADDRESS + \ - index * PORT_TRUNK_ID_INC, - &value->val); -} - -sw_error_t -hppe_port_trunk_id_set( - a_uint32_t dev_id, - a_uint32_t index, - union port_trunk_id_u *value) -{ - return hppe_reg_set( - dev_id, - IPE_L2_BASE_ADDR + PORT_TRUNK_ID_ADDRESS + \ - index * PORT_TRUNK_ID_INC, - value->val); -} - -sw_error_t -hppe_trunk_hash_field_reg_udf2_incl_get( - a_uint32_t dev_id, - a_uint32_t *value) -{ - union trunk_hash_field_reg_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_trunk_hash_field_reg_get(dev_id, ®_val); - *value = reg_val.bf.udf2_incl; - return ret; -} - -sw_error_t -hppe_trunk_hash_field_reg_udf2_incl_set( - a_uint32_t dev_id, - a_uint32_t value) -{ - union trunk_hash_field_reg_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_trunk_hash_field_reg_get(dev_id, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.udf2_incl = value; - ret = hppe_trunk_hash_field_reg_set(dev_id, ®_val); - return ret; -} - -sw_error_t -hppe_trunk_hash_field_reg_mac_da_incl_get( - a_uint32_t dev_id, - a_uint32_t *value) -{ - union trunk_hash_field_reg_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_trunk_hash_field_reg_get(dev_id, ®_val); - *value = reg_val.bf.mac_da_incl; - return ret; -} - -sw_error_t -hppe_trunk_hash_field_reg_mac_da_incl_set( - a_uint32_t dev_id, - a_uint32_t value) -{ - union trunk_hash_field_reg_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_trunk_hash_field_reg_get(dev_id, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.mac_da_incl = value; - ret = hppe_trunk_hash_field_reg_set(dev_id, ®_val); - return ret; -} - -sw_error_t -hppe_trunk_hash_field_reg_src_port_incl_get( - a_uint32_t dev_id, - a_uint32_t *value) -{ - union trunk_hash_field_reg_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_trunk_hash_field_reg_get(dev_id, ®_val); - *value = reg_val.bf.src_port_incl; - return ret; -} - -sw_error_t -hppe_trunk_hash_field_reg_src_port_incl_set( - a_uint32_t dev_id, - a_uint32_t value) -{ - union trunk_hash_field_reg_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_trunk_hash_field_reg_get(dev_id, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.src_port_incl = value; - ret = hppe_trunk_hash_field_reg_set(dev_id, ®_val); - return ret; -} - -sw_error_t -hppe_trunk_hash_field_reg_udf3_incl_get( - a_uint32_t dev_id, - a_uint32_t *value) -{ - union trunk_hash_field_reg_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_trunk_hash_field_reg_get(dev_id, ®_val); - *value = reg_val.bf.udf3_incl; - return ret; -} - -sw_error_t -hppe_trunk_hash_field_reg_udf3_incl_set( - a_uint32_t dev_id, - a_uint32_t value) -{ - union trunk_hash_field_reg_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_trunk_hash_field_reg_get(dev_id, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.udf3_incl = value; - ret = hppe_trunk_hash_field_reg_set(dev_id, ®_val); - return ret; -} - -sw_error_t -hppe_trunk_hash_field_reg_l4_dst_port_incl_get( - a_uint32_t dev_id, - a_uint32_t *value) -{ - union trunk_hash_field_reg_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_trunk_hash_field_reg_get(dev_id, ®_val); - *value = reg_val.bf.l4_dst_port_incl; - return ret; -} - -sw_error_t -hppe_trunk_hash_field_reg_l4_dst_port_incl_set( - a_uint32_t dev_id, - a_uint32_t value) -{ - union trunk_hash_field_reg_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_trunk_hash_field_reg_get(dev_id, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.l4_dst_port_incl = value; - ret = hppe_trunk_hash_field_reg_set(dev_id, ®_val); - return ret; -} - -sw_error_t -hppe_trunk_hash_field_reg_udf0_incl_get( - a_uint32_t dev_id, - a_uint32_t *value) -{ - union trunk_hash_field_reg_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_trunk_hash_field_reg_get(dev_id, ®_val); - *value = reg_val.bf.udf0_incl; - return ret; -} - -sw_error_t -hppe_trunk_hash_field_reg_udf0_incl_set( - a_uint32_t dev_id, - a_uint32_t value) -{ - union trunk_hash_field_reg_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_trunk_hash_field_reg_get(dev_id, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.udf0_incl = value; - ret = hppe_trunk_hash_field_reg_set(dev_id, ®_val); - return ret; -} - -sw_error_t -hppe_trunk_hash_field_reg_dst_ip_incl_get( - a_uint32_t dev_id, - a_uint32_t *value) -{ - union trunk_hash_field_reg_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_trunk_hash_field_reg_get(dev_id, ®_val); - *value = reg_val.bf.dst_ip_incl; - return ret; -} - -sw_error_t -hppe_trunk_hash_field_reg_dst_ip_incl_set( - a_uint32_t dev_id, - a_uint32_t value) -{ - union trunk_hash_field_reg_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_trunk_hash_field_reg_get(dev_id, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.dst_ip_incl = value; - ret = hppe_trunk_hash_field_reg_set(dev_id, ®_val); - return ret; -} - -sw_error_t -hppe_trunk_hash_field_reg_l4_src_port_incl_get( - a_uint32_t dev_id, - a_uint32_t *value) -{ - union trunk_hash_field_reg_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_trunk_hash_field_reg_get(dev_id, ®_val); - *value = reg_val.bf.l4_src_port_incl; - return ret; -} - -sw_error_t -hppe_trunk_hash_field_reg_l4_src_port_incl_set( - a_uint32_t dev_id, - a_uint32_t value) -{ - union trunk_hash_field_reg_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_trunk_hash_field_reg_get(dev_id, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.l4_src_port_incl = value; - ret = hppe_trunk_hash_field_reg_set(dev_id, ®_val); - return ret; -} - -sw_error_t -hppe_trunk_hash_field_reg_src_ip_incl_get( - a_uint32_t dev_id, - a_uint32_t *value) -{ - union trunk_hash_field_reg_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_trunk_hash_field_reg_get(dev_id, ®_val); - *value = reg_val.bf.src_ip_incl; - return ret; -} - -sw_error_t -hppe_trunk_hash_field_reg_src_ip_incl_set( - a_uint32_t dev_id, - a_uint32_t value) -{ - union trunk_hash_field_reg_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_trunk_hash_field_reg_get(dev_id, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.src_ip_incl = value; - ret = hppe_trunk_hash_field_reg_set(dev_id, ®_val); - return ret; -} - -sw_error_t -hppe_trunk_hash_field_reg_udf1_incl_get( - a_uint32_t dev_id, - a_uint32_t *value) -{ - union trunk_hash_field_reg_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_trunk_hash_field_reg_get(dev_id, ®_val); - *value = reg_val.bf.udf1_incl; - return ret; -} - -sw_error_t -hppe_trunk_hash_field_reg_udf1_incl_set( - a_uint32_t dev_id, - a_uint32_t value) -{ - union trunk_hash_field_reg_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_trunk_hash_field_reg_get(dev_id, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.udf1_incl = value; - ret = hppe_trunk_hash_field_reg_set(dev_id, ®_val); - return ret; -} - -sw_error_t -hppe_trunk_hash_field_reg_mac_sa_incl_get( - a_uint32_t dev_id, - a_uint32_t *value) -{ - union trunk_hash_field_reg_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_trunk_hash_field_reg_get(dev_id, ®_val); - *value = reg_val.bf.mac_sa_incl; - return ret; -} - -sw_error_t -hppe_trunk_hash_field_reg_mac_sa_incl_set( - a_uint32_t dev_id, - a_uint32_t value) -{ - union trunk_hash_field_reg_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_trunk_hash_field_reg_get(dev_id, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.mac_sa_incl = value; - ret = hppe_trunk_hash_field_reg_set(dev_id, ®_val); - return ret; -} - -sw_error_t -hppe_trunk_filter_mem_bitmap_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union trunk_filter_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_trunk_filter_get(dev_id, index, ®_val); - *value = reg_val.bf.mem_bitmap; - return ret; -} - -sw_error_t -hppe_trunk_filter_mem_bitmap_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - union trunk_filter_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_trunk_filter_get(dev_id, index, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.mem_bitmap = value; - ret = hppe_trunk_filter_set(dev_id, index, ®_val); - return ret; -} - -sw_error_t -hppe_trunk_member_member_2_port_id_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union trunk_member_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_trunk_member_get(dev_id, index, ®_val); - *value = reg_val.bf.member_2_port_id; - return ret; -} - -sw_error_t -hppe_trunk_member_member_2_port_id_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - union trunk_member_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_trunk_member_get(dev_id, index, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.member_2_port_id = value; - ret = hppe_trunk_member_set(dev_id, index, ®_val); - return ret; -} - -sw_error_t -hppe_trunk_member_member_0_port_id_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union trunk_member_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_trunk_member_get(dev_id, index, ®_val); - *value = reg_val.bf.member_0_port_id; - return ret; -} - -sw_error_t -hppe_trunk_member_member_0_port_id_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - union trunk_member_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_trunk_member_get(dev_id, index, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.member_0_port_id = value; - ret = hppe_trunk_member_set(dev_id, index, ®_val); - return ret; -} - -sw_error_t -hppe_trunk_member_member_1_port_id_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union trunk_member_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_trunk_member_get(dev_id, index, ®_val); - *value = reg_val.bf.member_1_port_id; - return ret; -} - -sw_error_t -hppe_trunk_member_member_1_port_id_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - union trunk_member_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_trunk_member_get(dev_id, index, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.member_1_port_id = value; - ret = hppe_trunk_member_set(dev_id, index, ®_val); - return ret; -} - -sw_error_t -hppe_trunk_member_member_6_port_id_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union trunk_member_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_trunk_member_get(dev_id, index, ®_val); - *value = reg_val.bf.member_6_port_id; - return ret; -} - -sw_error_t -hppe_trunk_member_member_6_port_id_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - union trunk_member_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_trunk_member_get(dev_id, index, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.member_6_port_id = value; - ret = hppe_trunk_member_set(dev_id, index, ®_val); - return ret; -} - -sw_error_t -hppe_trunk_member_member_4_port_id_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union trunk_member_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_trunk_member_get(dev_id, index, ®_val); - *value = reg_val.bf.member_4_port_id; - return ret; -} - -sw_error_t -hppe_trunk_member_member_4_port_id_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - union trunk_member_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_trunk_member_get(dev_id, index, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.member_4_port_id = value; - ret = hppe_trunk_member_set(dev_id, index, ®_val); - return ret; -} - -sw_error_t -hppe_trunk_member_member_3_port_id_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union trunk_member_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_trunk_member_get(dev_id, index, ®_val); - *value = reg_val.bf.member_3_port_id; - return ret; -} - -sw_error_t -hppe_trunk_member_member_3_port_id_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - union trunk_member_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_trunk_member_get(dev_id, index, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.member_3_port_id = value; - ret = hppe_trunk_member_set(dev_id, index, ®_val); - return ret; -} - -sw_error_t -hppe_trunk_member_member_5_port_id_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union trunk_member_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_trunk_member_get(dev_id, index, ®_val); - *value = reg_val.bf.member_5_port_id; - return ret; -} - -sw_error_t -hppe_trunk_member_member_5_port_id_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - union trunk_member_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_trunk_member_get(dev_id, index, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.member_5_port_id = value; - ret = hppe_trunk_member_set(dev_id, index, ®_val); - return ret; -} - -sw_error_t -hppe_trunk_member_member_7_port_id_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union trunk_member_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_trunk_member_get(dev_id, index, ®_val); - *value = reg_val.bf.member_7_port_id; - return ret; -} - -sw_error_t -hppe_trunk_member_member_7_port_id_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - union trunk_member_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_trunk_member_get(dev_id, index, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.member_7_port_id = value; - ret = hppe_trunk_member_set(dev_id, index, ®_val); - return ret; -} - -sw_error_t -hppe_port_trunk_id_trunk_id_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union port_trunk_id_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_port_trunk_id_get(dev_id, index, ®_val); - *value = reg_val.bf.trunk_id; - return ret; -} - -sw_error_t -hppe_port_trunk_id_trunk_id_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - union port_trunk_id_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_port_trunk_id_get(dev_id, index, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.trunk_id = value; - ret = hppe_port_trunk_id_set(dev_id, index, ®_val); - return ret; -} - -sw_error_t -hppe_port_trunk_id_trunk_en_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union port_trunk_id_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_port_trunk_id_get(dev_id, index, ®_val); - *value = reg_val.bf.trunk_en; - return ret; -} - -sw_error_t -hppe_port_trunk_id_trunk_en_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - union port_trunk_id_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_port_trunk_id_get(dev_id, index, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.trunk_en = value; - ret = hppe_port_trunk_id_set(dev_id, index, ®_val); - return ret; -} - diff --git a/feeds/ipq807x/qca-ssdk/src/src/hsl/hppe/hppe_uniphy.c b/feeds/ipq807x/qca-ssdk/src/src/hsl/hppe/hppe_uniphy.c deleted file mode 100755 index 9588e67dc..000000000 --- a/feeds/ipq807x/qca-ssdk/src/src/hsl/hppe/hppe_uniphy.c +++ /dev/null @@ -1,6120 +0,0 @@ -/* - * Copyright (c) 2017, 2019-2020, The Linux Foundation. All rights reserved. - * Permission to use, copy, modify, and/or distribute this software for - * any purpose with or without fee is hereby granted, provided that the - * above copyright notice and this permission notice appear in all copies. - * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES - * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR - * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES - * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN - * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT - * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. - */ - - -/** - * @defgroup - * @{ - */ -#include "sw.h" -#include "hsl.h" -#include "hppe_reg_access.h" -#include "hppe_uniphy_reg.h" -#include "hppe_uniphy.h" - -sw_error_t -hppe_uniphy_offset_calib_4_get( - a_uint32_t dev_id, - a_uint32_t index, - union uniphy_offset_calib_4_u *value) -{ - if (index >= UNIPHY_OFFSET_CALIB_4_MAX_ENTRY) - return SW_OUT_OF_RANGE; - return hppe_uniphy_reg_get( - dev_id, - NSS_UNIPHY_BASE_ADDR + UNIPHY_OFFSET_CALIB_4_ADDRESS, - index * UNIPHY_OFFSET_CALIB_4_INC, - &value->val); -} -#ifndef IN_UNIPHY_MINI -sw_error_t -hppe_uniphy_offset_calib_4_set( - a_uint32_t dev_id, - a_uint32_t index, - union uniphy_offset_calib_4_u *value) -{ - return hppe_uniphy_reg_set( - dev_id, - NSS_UNIPHY_BASE_ADDR + UNIPHY_OFFSET_CALIB_4_ADDRESS, - index * UNIPHY_OFFSET_CALIB_4_INC, - value->val); -} -#endif -sw_error_t -hppe_uniphy_mode_ctrl_get( - a_uint32_t dev_id, - a_uint32_t index, - union uniphy_mode_ctrl_u *value) -{ - if (index >= UNIPHY_MODE_CTRL_MAX_ENTRY) - return SW_OUT_OF_RANGE; - return hppe_uniphy_reg_get( - dev_id, - NSS_UNIPHY_BASE_ADDR + UNIPHY_MODE_CTRL_ADDRESS, - index * UNIPHY_MODE_CTRL_INC, - &value->val); -} - -sw_error_t -hppe_uniphy_mode_ctrl_set( - a_uint32_t dev_id, - a_uint32_t index, - union uniphy_mode_ctrl_u *value) -{ - return hppe_uniphy_reg_set( - dev_id, - NSS_UNIPHY_BASE_ADDR + UNIPHY_MODE_CTRL_ADDRESS, - index * UNIPHY_MODE_CTRL_INC, - value->val); -} - -sw_error_t -hppe_uniphy_channel0_input_output_4_get( - a_uint32_t dev_id, - a_uint32_t index, - union uniphy_channel0_input_output_4_u *value) -{ - if (index >= UNIPHY_CHANNEL0_INPUT_OUTPUT_4_MAX_ENTRY) - return SW_OUT_OF_RANGE; - return hppe_uniphy_reg_get( - dev_id, - NSS_UNIPHY_BASE_ADDR + UNIPHY_CHANNEL0_INPUT_OUTPUT_4_ADDRESS, - index * UNIPHY_CHANNEL0_INPUT_OUTPUT_4_INC, - &value->val); -} - -sw_error_t -hppe_uniphy_channel0_input_output_4_set( - a_uint32_t dev_id, - a_uint32_t index, - union uniphy_channel0_input_output_4_u *value) -{ - return hppe_uniphy_reg_set( - dev_id, - NSS_UNIPHY_BASE_ADDR + UNIPHY_CHANNEL0_INPUT_OUTPUT_4_ADDRESS, - index * UNIPHY_CHANNEL0_INPUT_OUTPUT_4_INC, - value->val); -} - -sw_error_t -hppe_uniphy_channel1_input_output_4_get( - a_uint32_t dev_id, - a_uint32_t index, - union uniphy_channel1_input_output_4_u *value) -{ - if (index >= UNIPHY_CHANNEL1_INPUT_OUTPUT_4_MAX_ENTRY) - return SW_OUT_OF_RANGE; - return hppe_uniphy_reg_get( - dev_id, - NSS_UNIPHY_BASE_ADDR + UNIPHY_CHANNEL1_INPUT_OUTPUT_4_ADDRESS, - index * UNIPHY_CHANNEL1_INPUT_OUTPUT_4_INC, - &value->val); -} - -sw_error_t -hppe_uniphy_channel1_input_output_4_set( - a_uint32_t dev_id, - a_uint32_t index, - union uniphy_channel1_input_output_4_u *value) -{ - return hppe_uniphy_reg_set( - dev_id, - NSS_UNIPHY_BASE_ADDR + UNIPHY_CHANNEL1_INPUT_OUTPUT_4_ADDRESS, - index * UNIPHY_CHANNEL1_INPUT_OUTPUT_4_INC, - value->val); -} - -sw_error_t -hppe_uniphy_channel2_input_output_4_get( - a_uint32_t dev_id, - a_uint32_t index, - union uniphy_channel2_input_output_4_u *value) -{ - if (index >= UNIPHY_CHANNEL2_INPUT_OUTPUT_4_MAX_ENTRY) - return SW_OUT_OF_RANGE; - return hppe_uniphy_reg_get( - dev_id, - NSS_UNIPHY_BASE_ADDR + UNIPHY_CHANNEL2_INPUT_OUTPUT_4_ADDRESS, - index * UNIPHY_CHANNEL2_INPUT_OUTPUT_4_INC, - &value->val); -} - -sw_error_t -hppe_uniphy_channel2_input_output_4_set( - a_uint32_t dev_id, - a_uint32_t index, - union uniphy_channel2_input_output_4_u *value) -{ - return hppe_uniphy_reg_set( - dev_id, - NSS_UNIPHY_BASE_ADDR + UNIPHY_CHANNEL2_INPUT_OUTPUT_4_ADDRESS, - index * UNIPHY_CHANNEL2_INPUT_OUTPUT_4_INC, - value->val); -} - -sw_error_t -hppe_uniphy_channel3_input_output_4_get( - a_uint32_t dev_id, - a_uint32_t index, - union uniphy_channel3_input_output_4_u *value) -{ - if (index >= UNIPHY_CHANNEL3_INPUT_OUTPUT_4_MAX_ENTRY) - return SW_OUT_OF_RANGE; - return hppe_uniphy_reg_get( - dev_id, - NSS_UNIPHY_BASE_ADDR + UNIPHY_CHANNEL3_INPUT_OUTPUT_4_ADDRESS, - index * UNIPHY_CHANNEL3_INPUT_OUTPUT_4_INC, - &value->val); -} - -sw_error_t -hppe_uniphy_channel3_input_output_4_set( - a_uint32_t dev_id, - a_uint32_t index, - union uniphy_channel3_input_output_4_u *value) -{ - return hppe_uniphy_reg_set( - dev_id, - NSS_UNIPHY_BASE_ADDR + UNIPHY_CHANNEL3_INPUT_OUTPUT_4_ADDRESS, - index * UNIPHY_CHANNEL3_INPUT_OUTPUT_4_INC, - value->val); -} - -sw_error_t -hppe_uniphy_channel4_input_output_4_get( - a_uint32_t dev_id, - a_uint32_t index, - union uniphy_channel4_input_output_4_u *value) -{ - if (index >= UNIPHY_CHANNEL4_INPUT_OUTPUT_4_MAX_ENTRY) - return SW_OUT_OF_RANGE; - return hppe_uniphy_reg_get( - dev_id, - NSS_UNIPHY_BASE_ADDR + UNIPHY_CHANNEL4_INPUT_OUTPUT_4_ADDRESS, - index * UNIPHY_CHANNEL4_INPUT_OUTPUT_4_INC, - &value->val); -} - -sw_error_t -hppe_uniphy_channel4_input_output_4_set( - a_uint32_t dev_id, - a_uint32_t index, - union uniphy_channel4_input_output_4_u *value) -{ - return hppe_uniphy_reg_set( - dev_id, - NSS_UNIPHY_BASE_ADDR + UNIPHY_CHANNEL4_INPUT_OUTPUT_4_ADDRESS, - index * UNIPHY_CHANNEL4_INPUT_OUTPUT_4_INC, - value->val); -} - -sw_error_t -hppe_uniphy_instance_link_detect_get( - a_uint32_t dev_id, - a_uint32_t index, - union uniphy_instance_link_detect_u *value) -{ - return hppe_uniphy_reg_get( - dev_id, - NSS_UNIPHY_BASE_ADDR + UNIPHY_INSTANCE_LINK_DETECT_ADDRESS, - index * UNIPHY_INSTANCE_LINK_DETECT_INC, - &value->val); -} - - -sw_error_t -hppe_uniphy_instance_link_detect_set( - a_uint32_t dev_id, - a_uint32_t index, - union uniphy_instance_link_detect_u *value) -{ - return hppe_uniphy_reg_set( - dev_id, - NSS_UNIPHY_BASE_ADDR + UNIPHY_INSTANCE_LINK_DETECT_ADDRESS, - index * UNIPHY_INSTANCE_LINK_DETECT_INC, - value->val); -} - -sw_error_t -hppe_sr_xs_pcs_kr_sts1_get( - a_uint32_t dev_id, - a_uint32_t index, - union sr_xs_pcs_kr_sts1_u *value) -{ - if (index >= SR_XS_PCS_KR_STS1_MAX_ENTRY) - return SW_OUT_OF_RANGE; - return hppe_uniphy_reg_get( - dev_id, - NSS_UNIPHY_BASE_ADDR + SR_XS_PCS_KR_STS1_ADDRESS, - index * SR_XS_PCS_KR_STS1_INC, - &value->val); -} -#ifndef IN_UNIPHY_MINI -sw_error_t -hppe_sr_xs_pcs_kr_sts1_set( - a_uint32_t dev_id, - a_uint32_t index, - union sr_xs_pcs_kr_sts1_u *value) -{ - return hppe_uniphy_reg_set( - dev_id, - NSS_UNIPHY_BASE_ADDR + SR_XS_PCS_KR_STS1_ADDRESS, - index * SR_XS_PCS_KR_STS1_INC, - value->val); -} -#endif -sw_error_t -hppe_vr_xs_pcs_dig_ctrl1_get( - a_uint32_t dev_id, - a_uint32_t index, - union vr_xs_pcs_dig_ctrl1_u *value) -{ - if (index >= VR_XS_PCS_DIG_CTRL1_MAX_ENTRY) - return SW_OUT_OF_RANGE; - return hppe_uniphy_reg_get( - dev_id, - NSS_UNIPHY_BASE_ADDR + VR_XS_PCS_DIG_CTRL1_ADDRESS, - index * VR_XS_PCS_DIG_CTRL1_INC, - &value->val); -} - -sw_error_t -hppe_vr_xs_pcs_dig_ctrl1_set( - a_uint32_t dev_id, - a_uint32_t index, - union vr_xs_pcs_dig_ctrl1_u *value) -{ - return hppe_uniphy_reg_set( - dev_id, - NSS_UNIPHY_BASE_ADDR + VR_XS_PCS_DIG_CTRL1_ADDRESS, - index * VR_XS_PCS_DIG_CTRL1_INC, - value->val); -} - -sw_error_t -hppe_sr_mii_ctrl_get( - a_uint32_t dev_id, - a_uint32_t index, - union sr_mii_ctrl_u *value) -{ - if (index >= SR_MII_CTRL_MAX_ENTRY) - return SW_OUT_OF_RANGE; - return hppe_uniphy_reg_get( - dev_id, - NSS_UNIPHY_BASE_ADDR + SR_MII_CTRL_ADDRESS, - index * SR_MII_CTRL_INC, - &value->val); -} - -sw_error_t -hppe_sr_mii_ctrl_set( - a_uint32_t dev_id, - a_uint32_t index, - union sr_mii_ctrl_u *value) -{ - return hppe_uniphy_reg_set( - dev_id, - NSS_UNIPHY_BASE_ADDR + SR_MII_CTRL_ADDRESS, - index * SR_MII_CTRL_INC, - value->val); -} - -sw_error_t -hppe_vr_mii_an_ctrl_get( - a_uint32_t dev_id, - a_uint32_t index, - union vr_mii_an_ctrl_u *value) -{ - if (index >= VR_MII_AN_CTRL_MAX_ENTRY) - return SW_OUT_OF_RANGE; - return hppe_uniphy_reg_get( - dev_id, - NSS_UNIPHY_BASE_ADDR + VR_MII_AN_CTRL_ADDRESS, - index * VR_MII_AN_CTRL_INC, - &value->val); -} - -sw_error_t -hppe_vr_mii_an_ctrl_set( - a_uint32_t dev_id, - a_uint32_t index, - union vr_mii_an_ctrl_u *value) -{ - return hppe_uniphy_reg_set( - dev_id, - NSS_UNIPHY_BASE_ADDR + VR_MII_AN_CTRL_ADDRESS, - index * VR_MII_AN_CTRL_INC, - value->val); -} - -sw_error_t -hppe_vr_mii_an_intr_sts_get( - a_uint32_t dev_id, - a_uint32_t index, - union vr_mii_an_intr_sts_u *value) -{ - if (index >= VR_MII_AN_INTR_STS_MAX_ENTRY) - return SW_OUT_OF_RANGE; - return hppe_uniphy_reg_get( - dev_id, - NSS_UNIPHY_BASE_ADDR + VR_MII_AN_INTR_STS_ADDRESS, - index * VR_MII_AN_INTR_STS_INC, - &value->val); -} - -sw_error_t -hppe_vr_mii_an_intr_sts_set( - a_uint32_t dev_id, - a_uint32_t index, - union vr_mii_an_intr_sts_u *value) -{ - return hppe_uniphy_reg_set( - dev_id, - NSS_UNIPHY_BASE_ADDR + VR_MII_AN_INTR_STS_ADDRESS, - index * VR_MII_AN_INTR_STS_INC, - value->val); -} - -sw_error_t -hppe_uniphy_offset_calib_4_mmd1_reg_cal_rep_time_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union uniphy_offset_calib_4_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_uniphy_offset_calib_4_get(dev_id, index, ®_val); - *value = reg_val.bf.mmd1_reg_cal_rep_time; - return ret; -} -#ifndef IN_UNIPHY_MINI -sw_error_t -hppe_uniphy_offset_calib_4_mmd1_reg_cal_rep_time_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - union uniphy_offset_calib_4_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_uniphy_offset_calib_4_get(dev_id, index, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.mmd1_reg_cal_rep_time = value; - ret = hppe_uniphy_offset_calib_4_set(dev_id, index, ®_val); - return ret; -} - -sw_error_t -hppe_uniphy_offset_calib_4_mmd1_reg_pll_locked_reg_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union uniphy_offset_calib_4_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_uniphy_offset_calib_4_get(dev_id, index, ®_val); - *value = reg_val.bf.mmd1_reg_pll_locked_reg; - return ret; -} - -sw_error_t -hppe_uniphy_offset_calib_4_mmd1_reg_pll_locked_reg_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - union uniphy_offset_calib_4_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_uniphy_offset_calib_4_get(dev_id, index, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.mmd1_reg_pll_locked_reg = value; - ret = hppe_uniphy_offset_calib_4_set(dev_id, index, ®_val); - return ret; -} - -sw_error_t -hppe_uniphy_offset_calib_4_mmd1_reg_clr_sampler_calib_timeout_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union uniphy_offset_calib_4_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_uniphy_offset_calib_4_get(dev_id, index, ®_val); - *value = reg_val.bf.mmd1_reg_clr_sampler_calib_timeout; - return ret; -} - -sw_error_t -hppe_uniphy_offset_calib_4_mmd1_reg_clr_sampler_calib_timeout_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - union uniphy_offset_calib_4_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_uniphy_offset_calib_4_get(dev_id, index, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.mmd1_reg_clr_sampler_calib_timeout = value; - ret = hppe_uniphy_offset_calib_4_set(dev_id, index, ®_val); - return ret; -} - -sw_error_t -hppe_uniphy_offset_calib_4_mmd1_reg_lockdet_lckdt_reg_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union uniphy_offset_calib_4_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_uniphy_offset_calib_4_get(dev_id, index, ®_val); - *value = reg_val.bf.mmd1_reg_lockdet_lckdt_reg; - return ret; -} - -sw_error_t -hppe_uniphy_offset_calib_4_mmd1_reg_lockdet_lckdt_reg_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - union uniphy_offset_calib_4_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_uniphy_offset_calib_4_get(dev_id, index, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.mmd1_reg_lockdet_lckdt_reg = value; - ret = hppe_uniphy_offset_calib_4_set(dev_id, index, ®_val); - return ret; -} - -sw_error_t -hppe_uniphy_offset_calib_4_mmd1_reg_cal_detect_time_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union uniphy_offset_calib_4_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_uniphy_offset_calib_4_get(dev_id, index, ®_val); - *value = reg_val.bf.mmd1_reg_cal_detect_time; - return ret; -} - -sw_error_t -hppe_uniphy_offset_calib_4_mmd1_reg_cal_detect_time_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - union uniphy_offset_calib_4_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_uniphy_offset_calib_4_get(dev_id, index, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.mmd1_reg_cal_detect_time = value; - ret = hppe_uniphy_offset_calib_4_set(dev_id, index, ®_val); - return ret; -} - -sw_error_t -hppe_uniphy_offset_calib_4_mmd1_reg_calibration_done_reg_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union uniphy_offset_calib_4_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_uniphy_offset_calib_4_get(dev_id, index, ®_val); - *value = reg_val.bf.mmd1_reg_calibration_done_reg; - return ret; -} - -sw_error_t -hppe_uniphy_offset_calib_4_mmd1_reg_calibration_done_reg_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - union uniphy_offset_calib_4_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_uniphy_offset_calib_4_get(dev_id, index, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.mmd1_reg_calibration_done_reg = value; - ret = hppe_uniphy_offset_calib_4_set(dev_id, index, ®_val); - return ret; -} - -sw_error_t -hppe_uniphy_offset_calib_4_mmd1_reg_smpl_cal_ready_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union uniphy_offset_calib_4_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_uniphy_offset_calib_4_get(dev_id, index, ®_val); - *value = reg_val.bf.mmd1_reg_smpl_cal_ready; - return ret; -} - -sw_error_t -hppe_uniphy_offset_calib_4_mmd1_reg_smpl_cal_ready_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - union uniphy_offset_calib_4_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_uniphy_offset_calib_4_get(dev_id, index, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.mmd1_reg_smpl_cal_ready = value; - ret = hppe_uniphy_offset_calib_4_set(dev_id, index, ®_val); - return ret; -} - -sw_error_t -hppe_uniphy_mode_ctrl_newaddedfromhere_ch1_ch0_sgmii_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union uniphy_mode_ctrl_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_uniphy_mode_ctrl_get(dev_id, index, ®_val); - *value = reg_val.bf.newaddedfromhere_ch1_ch0_sgmii; - return ret; -} - -sw_error_t -hppe_uniphy_mode_ctrl_newaddedfromhere_ch1_ch0_sgmii_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - union uniphy_mode_ctrl_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_uniphy_mode_ctrl_get(dev_id, index, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.newaddedfromhere_ch1_ch0_sgmii = value; - ret = hppe_uniphy_mode_ctrl_set(dev_id, index, ®_val); - return ret; -} - -sw_error_t -hppe_uniphy_mode_ctrl_newaddedfromhere_usxg_en_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union uniphy_mode_ctrl_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_uniphy_mode_ctrl_get(dev_id, index, ®_val); - *value = reg_val.bf.newaddedfromhere_usxg_en; - return ret; -} - -sw_error_t -hppe_uniphy_mode_ctrl_newaddedfromhere_usxg_en_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - union uniphy_mode_ctrl_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_uniphy_mode_ctrl_get(dev_id, index, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.newaddedfromhere_usxg_en = value; - ret = hppe_uniphy_mode_ctrl_set(dev_id, index, ®_val); - return ret; -} - -sw_error_t -hppe_uniphy_mode_ctrl_newaddedfromhere_ch4_ch1_0_sgmii_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union uniphy_mode_ctrl_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_uniphy_mode_ctrl_get(dev_id, index, ®_val); - *value = reg_val.bf.newaddedfromhere_ch4_ch1_0_sgmii; - return ret; -} - -sw_error_t -hppe_uniphy_mode_ctrl_newaddedfromhere_ch4_ch1_0_sgmii_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - union uniphy_mode_ctrl_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_uniphy_mode_ctrl_get(dev_id, index, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.newaddedfromhere_ch4_ch1_0_sgmii = value; - ret = hppe_uniphy_mode_ctrl_set(dev_id, index, ®_val); - return ret; -} - -sw_error_t -hppe_uniphy_mode_ctrl_newaddedfromhere_sgplus_mode_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union uniphy_mode_ctrl_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_uniphy_mode_ctrl_get(dev_id, index, ®_val); - *value = reg_val.bf.newaddedfromhere_sgplus_mode; - return ret; -} - -sw_error_t -hppe_uniphy_mode_ctrl_newaddedfromhere_sgplus_mode_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - union uniphy_mode_ctrl_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_uniphy_mode_ctrl_get(dev_id, index, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.newaddedfromhere_sgplus_mode = value; - ret = hppe_uniphy_mode_ctrl_set(dev_id, index, ®_val); - return ret; -} - -sw_error_t -hppe_uniphy_mode_ctrl_newaddedfromhere_xpcs_mode_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union uniphy_mode_ctrl_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_uniphy_mode_ctrl_get(dev_id, index, ®_val); - *value = reg_val.bf.newaddedfromhere_xpcs_mode; - return ret; -} - -sw_error_t -hppe_uniphy_mode_ctrl_newaddedfromhere_xpcs_mode_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - union uniphy_mode_ctrl_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_uniphy_mode_ctrl_get(dev_id, index, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.newaddedfromhere_xpcs_mode = value; - ret = hppe_uniphy_mode_ctrl_set(dev_id, index, ®_val); - return ret; -} - -sw_error_t -hppe_uniphy_mode_ctrl_newaddedfromhere_ch0_psgmii_qsgmii_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union uniphy_mode_ctrl_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_uniphy_mode_ctrl_get(dev_id, index, ®_val); - *value = reg_val.bf.newaddedfromhere_ch0_psgmii_qsgmii; - return ret; -} - -sw_error_t -hppe_uniphy_mode_ctrl_newaddedfromhere_ch0_psgmii_qsgmii_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - union uniphy_mode_ctrl_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_uniphy_mode_ctrl_get(dev_id, index, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.newaddedfromhere_ch0_psgmii_qsgmii = value; - ret = hppe_uniphy_mode_ctrl_set(dev_id, index, ®_val); - return ret; -} - -sw_error_t -hppe_uniphy_mode_ctrl_newaddedfromhere_ch0_autoneg_mode_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union uniphy_mode_ctrl_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_uniphy_mode_ctrl_get(dev_id, index, ®_val); - *value = reg_val.bf.newaddedfromhere_ch0_autoneg_mode; - return ret; -} - -sw_error_t -hppe_uniphy_mode_ctrl_newaddedfromhere_ch0_autoneg_mode_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - union uniphy_mode_ctrl_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_uniphy_mode_ctrl_get(dev_id, index, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.newaddedfromhere_ch0_autoneg_mode = value; - ret = hppe_uniphy_mode_ctrl_set(dev_id, index, ®_val); - return ret; -} - -sw_error_t -hppe_uniphy_mode_ctrl_newaddedfromhere_sw_v17_v18_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union uniphy_mode_ctrl_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_uniphy_mode_ctrl_get(dev_id, index, ®_val); - *value = reg_val.bf.newaddedfromhere_sw_v17_v18; - return ret; -} - -sw_error_t -hppe_uniphy_mode_ctrl_newaddedfromhere_sw_v17_v18_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - union uniphy_mode_ctrl_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_uniphy_mode_ctrl_get(dev_id, index, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.newaddedfromhere_sw_v17_v18 = value; - ret = hppe_uniphy_mode_ctrl_set(dev_id, index, ®_val); - return ret; -} - -sw_error_t -hppe_uniphy_mode_ctrl_newaddedfromhere_ch0_mode_ctrl_25m_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union uniphy_mode_ctrl_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_uniphy_mode_ctrl_get(dev_id, index, ®_val); - *value = reg_val.bf.newaddedfromhere_ch0_mode_ctrl_25m; - return ret; -} - -sw_error_t -hppe_uniphy_mode_ctrl_newaddedfromhere_ch0_mode_ctrl_25m_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - union uniphy_mode_ctrl_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_uniphy_mode_ctrl_get(dev_id, index, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.newaddedfromhere_ch0_mode_ctrl_25m = value; - ret = hppe_uniphy_mode_ctrl_set(dev_id, index, ®_val); - return ret; -} - -sw_error_t -hppe_uniphy_mode_ctrl_newaddedfromhere_sgmii_even_low_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union uniphy_mode_ctrl_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_uniphy_mode_ctrl_get(dev_id, index, ®_val); - *value = reg_val.bf.newaddedfromhere_sgmii_even_low; - return ret; -} - -sw_error_t -hppe_uniphy_mode_ctrl_newaddedfromhere_sgmii_even_low_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - union uniphy_mode_ctrl_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_uniphy_mode_ctrl_get(dev_id, index, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.newaddedfromhere_sgmii_even_low = value; - ret = hppe_uniphy_mode_ctrl_set(dev_id, index, ®_val); - return ret; -} - -sw_error_t -hppe_uniphy_mode_ctrl_newaddedfromhere_ch0_qsgmii_sgmii_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union uniphy_mode_ctrl_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_uniphy_mode_ctrl_get(dev_id, index, ®_val); - *value = reg_val.bf.newaddedfromhere_ch0_qsgmii_sgmii; - return ret; -} - -sw_error_t -hppe_uniphy_mode_ctrl_newaddedfromhere_ch0_qsgmii_sgmii_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - union uniphy_mode_ctrl_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_uniphy_mode_ctrl_get(dev_id, index, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.newaddedfromhere_ch0_qsgmii_sgmii = value; - ret = hppe_uniphy_mode_ctrl_set(dev_id, index, ®_val); - return ret; -} - -sw_error_t -hppe_uniphy_mode_ctrl_newaddedfromhere_sg_mode_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union uniphy_mode_ctrl_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_uniphy_mode_ctrl_get(dev_id, index, ®_val); - *value = reg_val.bf.newaddedfromhere_sg_mode; - return ret; -} - -sw_error_t -hppe_uniphy_mode_ctrl_newaddedfromhere_sg_mode_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - union uniphy_mode_ctrl_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_uniphy_mode_ctrl_get(dev_id, index, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.newaddedfromhere_sg_mode = value; - ret = hppe_uniphy_mode_ctrl_set(dev_id, index, ®_val); - return ret; -} - -sw_error_t -hppe_uniphy_channel0_input_output_4_newaddedfromhere_ch0_mr_restart_an_25m_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union uniphy_channel0_input_output_4_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_uniphy_channel0_input_output_4_get(dev_id, index, ®_val); - *value = reg_val.bf.newaddedfromhere_ch0_mr_restart_an_25m; - return ret; -} - -sw_error_t -hppe_uniphy_channel0_input_output_4_newaddedfromhere_ch0_mr_restart_an_25m_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - union uniphy_channel0_input_output_4_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_uniphy_channel0_input_output_4_get(dev_id, index, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.newaddedfromhere_ch0_mr_restart_an_25m = value; - ret = hppe_uniphy_channel0_input_output_4_set(dev_id, index, ®_val); - return ret; -} - -sw_error_t -hppe_uniphy_channel0_input_output_4_newaddedfromhere_ch0_rem_phy_lpbk_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union uniphy_channel0_input_output_4_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_uniphy_channel0_input_output_4_get(dev_id, index, ®_val); - *value = reg_val.bf.newaddedfromhere_ch0_rem_phy_lpbk; - return ret; -} - -sw_error_t -hppe_uniphy_channel0_input_output_4_newaddedfromhere_ch0_rem_phy_lpbk_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - union uniphy_channel0_input_output_4_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_uniphy_channel0_input_output_4_get(dev_id, index, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.newaddedfromhere_ch0_rem_phy_lpbk = value; - ret = hppe_uniphy_channel0_input_output_4_set(dev_id, index, ®_val); - return ret; -} - -sw_error_t -hppe_uniphy_channel0_input_output_4_newaddedfromhere_ch0_mr_reg4_ch_25m_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union uniphy_channel0_input_output_4_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_uniphy_channel0_input_output_4_get(dev_id, index, ®_val); - *value = reg_val.bf.newaddedfromhere_ch0_mr_reg4_ch_25m; - return ret; -} - -sw_error_t -hppe_uniphy_channel0_input_output_4_newaddedfromhere_ch0_mr_reg4_ch_25m_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - union uniphy_channel0_input_output_4_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_uniphy_channel0_input_output_4_get(dev_id, index, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.newaddedfromhere_ch0_mr_reg4_ch_25m = value; - ret = hppe_uniphy_channel0_input_output_4_set(dev_id, index, ®_val); - return ret; -} - -sw_error_t -hppe_uniphy_channel0_input_output_4_newaddedfromhere_ch0_power_on_25m_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union uniphy_channel0_input_output_4_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_uniphy_channel0_input_output_4_get(dev_id, index, ®_val); - *value = reg_val.bf.newaddedfromhere_ch0_power_on_25m; - return ret; -} - -sw_error_t -hppe_uniphy_channel0_input_output_4_newaddedfromhere_ch0_power_on_25m_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - union uniphy_channel0_input_output_4_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_uniphy_channel0_input_output_4_get(dev_id, index, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.newaddedfromhere_ch0_power_on_25m = value; - ret = hppe_uniphy_channel0_input_output_4_set(dev_id, index, ®_val); - return ret; -} - -sw_error_t -hppe_uniphy_channel0_input_output_4_newaddedfromhere_ch0_mr_main_reset_25m_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union uniphy_channel0_input_output_4_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_uniphy_channel0_input_output_4_get(dev_id, index, ®_val); - *value = reg_val.bf.newaddedfromhere_ch0_mr_main_reset_25m; - return ret; -} - -sw_error_t -hppe_uniphy_channel0_input_output_4_newaddedfromhere_ch0_mr_main_reset_25m_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - union uniphy_channel0_input_output_4_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_uniphy_channel0_input_output_4_get(dev_id, index, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.newaddedfromhere_ch0_mr_main_reset_25m = value; - ret = hppe_uniphy_channel0_input_output_4_set(dev_id, index, ®_val); - return ret; -} - -sw_error_t -hppe_uniphy_channel0_force_speed_mode_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union uniphy_channel0_input_output_4_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_uniphy_channel0_input_output_4_get(dev_id, index, ®_val); - *value = reg_val.bf.newaddedfromhere_ch0_force_speed_25m; - return ret; -} -#endif -sw_error_t -hppe_uniphy_channel0_force_speed_mode_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - union uniphy_channel0_input_output_4_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_uniphy_channel0_input_output_4_get(dev_id, index, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.newaddedfromhere_ch0_force_speed_25m = value; - ret = hppe_uniphy_channel0_input_output_4_set(dev_id, index, ®_val); - return ret; -} -#ifndef IN_UNIPHY_MINI -sw_error_t -hppe_uniphy_channel0_input_output_4_newaddedfromhere_ch0_adp_sw_rstn_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union uniphy_channel0_input_output_4_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_uniphy_channel0_input_output_4_get(dev_id, index, ®_val); - *value = reg_val.bf.newaddedfromhere_ch0_adp_sw_rstn; - return ret; -} - -sw_error_t -hppe_uniphy_channel0_input_output_4_newaddedfromhere_ch0_adp_sw_rstn_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - union uniphy_channel0_input_output_4_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_uniphy_channel0_input_output_4_get(dev_id, index, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.newaddedfromhere_ch0_adp_sw_rstn = value; - ret = hppe_uniphy_channel0_input_output_4_set(dev_id, index, ®_val); - return ret; -} - -sw_error_t -hppe_uniphy_channel0_input_output_4_newaddedfromhere_ch0_speed_25m_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union uniphy_channel0_input_output_4_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_uniphy_channel0_input_output_4_get(dev_id, index, ®_val); - *value = reg_val.bf.newaddedfromhere_ch0_speed_25m; - return ret; -} - -sw_error_t -hppe_uniphy_channel0_input_output_4_newaddedfromhere_ch0_speed_25m_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - union uniphy_channel0_input_output_4_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_uniphy_channel0_input_output_4_get(dev_id, index, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.newaddedfromhere_ch0_speed_25m = value; - ret = hppe_uniphy_channel0_input_output_4_set(dev_id, index, ®_val); - return ret; -} - -sw_error_t -hppe_uniphy_channel0_input_output_4_newaddedfromhere_ch0_mr_an_enable_25m_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union uniphy_channel0_input_output_4_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_uniphy_channel0_input_output_4_get(dev_id, index, ®_val); - *value = reg_val.bf.newaddedfromhere_ch0_mr_an_enable_25m; - return ret; -} - -sw_error_t -hppe_uniphy_channel0_input_output_4_newaddedfromhere_ch0_mr_an_enable_25m_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - union uniphy_channel0_input_output_4_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_uniphy_channel0_input_output_4_get(dev_id, index, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.newaddedfromhere_ch0_mr_an_enable_25m = value; - ret = hppe_uniphy_channel0_input_output_4_set(dev_id, index, ®_val); - return ret; -} - -sw_error_t -hppe_uniphy_channel0_input_output_4_newaddedfromhere_ch0_mr_np_loaded_25m_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union uniphy_channel0_input_output_4_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_uniphy_channel0_input_output_4_get(dev_id, index, ®_val); - *value = reg_val.bf.newaddedfromhere_ch0_mr_np_loaded_25m; - return ret; -} - -sw_error_t -hppe_uniphy_channel0_input_output_4_newaddedfromhere_ch0_mr_np_loaded_25m_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - union uniphy_channel0_input_output_4_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_uniphy_channel0_input_output_4_get(dev_id, index, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.newaddedfromhere_ch0_mr_np_loaded_25m = value; - ret = hppe_uniphy_channel0_input_output_4_set(dev_id, index, ®_val); - return ret; -} - -sw_error_t -hppe_uniphy_channel0_input_output_4_newaddedfromhere_ch0_mr_loopback_25m_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union uniphy_channel0_input_output_4_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_uniphy_channel0_input_output_4_get(dev_id, index, ®_val); - *value = reg_val.bf.newaddedfromhere_ch0_mr_loopback_25m; - return ret; -} - -sw_error_t -hppe_uniphy_channel0_input_output_4_newaddedfromhere_ch0_mr_loopback_25m_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - union uniphy_channel0_input_output_4_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_uniphy_channel0_input_output_4_get(dev_id, index, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.newaddedfromhere_ch0_mr_loopback_25m = value; - ret = hppe_uniphy_channel0_input_output_4_set(dev_id, index, ®_val); - return ret; -} - -sw_error_t -hppe_uniphy_channel1_input_output_4_newaddedfromhere_ch1_adp_sw_rstn_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union uniphy_channel1_input_output_4_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_uniphy_channel1_input_output_4_get(dev_id, index, ®_val); - *value = reg_val.bf.newaddedfromhere_ch1_adp_sw_rstn; - return ret; -} - -sw_error_t -hppe_uniphy_channel1_input_output_4_newaddedfromhere_ch1_adp_sw_rstn_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - union uniphy_channel1_input_output_4_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_uniphy_channel1_input_output_4_get(dev_id, index, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.newaddedfromhere_ch1_adp_sw_rstn = value; - ret = hppe_uniphy_channel1_input_output_4_set(dev_id, index, ®_val); - return ret; -} - -sw_error_t -hppe_uniphy_channel1_input_output_4_newaddedfromhere_ch1_power_on_25m_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union uniphy_channel1_input_output_4_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_uniphy_channel1_input_output_4_get(dev_id, index, ®_val); - *value = reg_val.bf.newaddedfromhere_ch1_power_on_25m; - return ret; -} - -sw_error_t -hppe_uniphy_channel1_input_output_4_newaddedfromhere_ch1_power_on_25m_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - union uniphy_channel1_input_output_4_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_uniphy_channel1_input_output_4_get(dev_id, index, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.newaddedfromhere_ch1_power_on_25m = value; - ret = hppe_uniphy_channel1_input_output_4_set(dev_id, index, ®_val); - return ret; -} - -sw_error_t -hppe_uniphy_channel1_input_output_4_newaddedfromhere_ch1_mr_main_reset_25m_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union uniphy_channel1_input_output_4_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_uniphy_channel1_input_output_4_get(dev_id, index, ®_val); - *value = reg_val.bf.newaddedfromhere_ch1_mr_main_reset_25m; - return ret; -} - -sw_error_t -hppe_uniphy_channel1_input_output_4_newaddedfromhere_ch1_mr_main_reset_25m_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - union uniphy_channel1_input_output_4_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_uniphy_channel1_input_output_4_get(dev_id, index, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.newaddedfromhere_ch1_mr_main_reset_25m = value; - ret = hppe_uniphy_channel1_input_output_4_set(dev_id, index, ®_val); - return ret; -} - -sw_error_t -hppe_uniphy_channel1_input_output_4_newaddedfromhere_ch1_mr_an_enable_25m_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union uniphy_channel1_input_output_4_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_uniphy_channel1_input_output_4_get(dev_id, index, ®_val); - *value = reg_val.bf.newaddedfromhere_ch1_mr_an_enable_25m; - return ret; -} - -sw_error_t -hppe_uniphy_channel1_input_output_4_newaddedfromhere_ch1_mr_an_enable_25m_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - union uniphy_channel1_input_output_4_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_uniphy_channel1_input_output_4_get(dev_id, index, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.newaddedfromhere_ch1_mr_an_enable_25m = value; - ret = hppe_uniphy_channel1_input_output_4_set(dev_id, index, ®_val); - return ret; -} - -sw_error_t -hppe_uniphy_channel1_input_output_4_newaddedfromhere_ch1_speed_25m_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union uniphy_channel1_input_output_4_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_uniphy_channel1_input_output_4_get(dev_id, index, ®_val); - *value = reg_val.bf.newaddedfromhere_ch1_speed_25m; - return ret; -} - -sw_error_t -hppe_uniphy_channel1_input_output_4_newaddedfromhere_ch1_speed_25m_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - union uniphy_channel1_input_output_4_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_uniphy_channel1_input_output_4_get(dev_id, index, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.newaddedfromhere_ch1_speed_25m = value; - ret = hppe_uniphy_channel1_input_output_4_set(dev_id, index, ®_val); - return ret; -} - -sw_error_t -hppe_uniphy_channel1_input_output_4_newaddedfromhere_ch1_rem_phy_lpbk_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union uniphy_channel1_input_output_4_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_uniphy_channel1_input_output_4_get(dev_id, index, ®_val); - *value = reg_val.bf.newaddedfromhere_ch1_rem_phy_lpbk; - return ret; -} - -sw_error_t -hppe_uniphy_channel1_input_output_4_newaddedfromhere_ch1_rem_phy_lpbk_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - union uniphy_channel1_input_output_4_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_uniphy_channel1_input_output_4_get(dev_id, index, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.newaddedfromhere_ch1_rem_phy_lpbk = value; - ret = hppe_uniphy_channel1_input_output_4_set(dev_id, index, ®_val); - return ret; -} - -sw_error_t -hppe_uniphy_channel1_input_output_4_newaddedfromhere_ch1_mr_reg4_ch_25m_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union uniphy_channel1_input_output_4_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_uniphy_channel1_input_output_4_get(dev_id, index, ®_val); - *value = reg_val.bf.newaddedfromhere_ch1_mr_reg4_ch_25m; - return ret; -} - -sw_error_t -hppe_uniphy_channel1_input_output_4_newaddedfromhere_ch1_mr_reg4_ch_25m_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - union uniphy_channel1_input_output_4_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_uniphy_channel1_input_output_4_get(dev_id, index, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.newaddedfromhere_ch1_mr_reg4_ch_25m = value; - ret = hppe_uniphy_channel1_input_output_4_set(dev_id, index, ®_val); - return ret; -} - -sw_error_t -hppe_uniphy_channel1_input_output_4_newaddedfromhere_ch1_mr_np_loaded_25m_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union uniphy_channel1_input_output_4_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_uniphy_channel1_input_output_4_get(dev_id, index, ®_val); - *value = reg_val.bf.newaddedfromhere_ch1_mr_np_loaded_25m; - return ret; -} - -sw_error_t -hppe_uniphy_channel1_input_output_4_newaddedfromhere_ch1_mr_np_loaded_25m_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - union uniphy_channel1_input_output_4_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_uniphy_channel1_input_output_4_get(dev_id, index, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.newaddedfromhere_ch1_mr_np_loaded_25m = value; - ret = hppe_uniphy_channel1_input_output_4_set(dev_id, index, ®_val); - return ret; -} - -sw_error_t -hppe_uniphy_channel1_input_output_4_newaddedfromhere_ch1_force_speed_25m_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union uniphy_channel1_input_output_4_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_uniphy_channel1_input_output_4_get(dev_id, index, ®_val); - *value = reg_val.bf.newaddedfromhere_ch1_force_speed_25m; - return ret; -} - -sw_error_t -hppe_uniphy_channel1_input_output_4_newaddedfromhere_ch1_force_speed_25m_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - union uniphy_channel1_input_output_4_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_uniphy_channel1_input_output_4_get(dev_id, index, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.newaddedfromhere_ch1_force_speed_25m = value; - ret = hppe_uniphy_channel1_input_output_4_set(dev_id, index, ®_val); - return ret; -} - -sw_error_t -hppe_uniphy_channel1_input_output_4_newaddedfromhere_ch1_mr_restart_an_25m_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union uniphy_channel1_input_output_4_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_uniphy_channel1_input_output_4_get(dev_id, index, ®_val); - *value = reg_val.bf.newaddedfromhere_ch1_mr_restart_an_25m; - return ret; -} - -sw_error_t -hppe_uniphy_channel1_input_output_4_newaddedfromhere_ch1_mr_restart_an_25m_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - union uniphy_channel1_input_output_4_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_uniphy_channel1_input_output_4_get(dev_id, index, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.newaddedfromhere_ch1_mr_restart_an_25m = value; - ret = hppe_uniphy_channel1_input_output_4_set(dev_id, index, ®_val); - return ret; -} - -sw_error_t -hppe_uniphy_channel1_input_output_4_newaddedfromhere_ch1_mr_loopback_25m_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union uniphy_channel1_input_output_4_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_uniphy_channel1_input_output_4_get(dev_id, index, ®_val); - *value = reg_val.bf.newaddedfromhere_ch1_mr_loopback_25m; - return ret; -} - -sw_error_t -hppe_uniphy_channel1_input_output_4_newaddedfromhere_ch1_mr_loopback_25m_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - union uniphy_channel1_input_output_4_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_uniphy_channel1_input_output_4_get(dev_id, index, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.newaddedfromhere_ch1_mr_loopback_25m = value; - ret = hppe_uniphy_channel1_input_output_4_set(dev_id, index, ®_val); - return ret; -} - -sw_error_t -hppe_uniphy_channel2_input_output_4_newaddedfromhere_ch2_rem_phy_lpbk_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union uniphy_channel2_input_output_4_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_uniphy_channel2_input_output_4_get(dev_id, index, ®_val); - *value = reg_val.bf.newaddedfromhere_ch2_rem_phy_lpbk; - return ret; -} - -sw_error_t -hppe_uniphy_channel2_input_output_4_newaddedfromhere_ch2_rem_phy_lpbk_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - union uniphy_channel2_input_output_4_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_uniphy_channel2_input_output_4_get(dev_id, index, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.newaddedfromhere_ch2_rem_phy_lpbk = value; - ret = hppe_uniphy_channel2_input_output_4_set(dev_id, index, ®_val); - return ret; -} - -sw_error_t -hppe_uniphy_channel2_input_output_4_newaddedfromhere_ch2_adp_sw_rstn_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union uniphy_channel2_input_output_4_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_uniphy_channel2_input_output_4_get(dev_id, index, ®_val); - *value = reg_val.bf.newaddedfromhere_ch2_adp_sw_rstn; - return ret; -} - -sw_error_t -hppe_uniphy_channel2_input_output_4_newaddedfromhere_ch2_adp_sw_rstn_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - union uniphy_channel2_input_output_4_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_uniphy_channel2_input_output_4_get(dev_id, index, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.newaddedfromhere_ch2_adp_sw_rstn = value; - ret = hppe_uniphy_channel2_input_output_4_set(dev_id, index, ®_val); - return ret; -} - -sw_error_t -hppe_uniphy_channel2_input_output_4_newaddedfromhere_ch2_mr_main_reset_25m_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union uniphy_channel2_input_output_4_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_uniphy_channel2_input_output_4_get(dev_id, index, ®_val); - *value = reg_val.bf.newaddedfromhere_ch2_mr_main_reset_25m; - return ret; -} - -sw_error_t -hppe_uniphy_channel2_input_output_4_newaddedfromhere_ch2_mr_main_reset_25m_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - union uniphy_channel2_input_output_4_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_uniphy_channel2_input_output_4_get(dev_id, index, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.newaddedfromhere_ch2_mr_main_reset_25m = value; - ret = hppe_uniphy_channel2_input_output_4_set(dev_id, index, ®_val); - return ret; -} - -sw_error_t -hppe_uniphy_channel2_input_output_4_newaddedfromhere_ch2_mr_loopback_25m_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union uniphy_channel2_input_output_4_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_uniphy_channel2_input_output_4_get(dev_id, index, ®_val); - *value = reg_val.bf.newaddedfromhere_ch2_mr_loopback_25m; - return ret; -} - -sw_error_t -hppe_uniphy_channel2_input_output_4_newaddedfromhere_ch2_mr_loopback_25m_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - union uniphy_channel2_input_output_4_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_uniphy_channel2_input_output_4_get(dev_id, index, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.newaddedfromhere_ch2_mr_loopback_25m = value; - ret = hppe_uniphy_channel2_input_output_4_set(dev_id, index, ®_val); - return ret; -} - -sw_error_t -hppe_uniphy_channel2_input_output_4_newaddedfromhere_ch2_mr_restart_an_25m_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union uniphy_channel2_input_output_4_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_uniphy_channel2_input_output_4_get(dev_id, index, ®_val); - *value = reg_val.bf.newaddedfromhere_ch2_mr_restart_an_25m; - return ret; -} - -sw_error_t -hppe_uniphy_channel2_input_output_4_newaddedfromhere_ch2_mr_restart_an_25m_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - union uniphy_channel2_input_output_4_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_uniphy_channel2_input_output_4_get(dev_id, index, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.newaddedfromhere_ch2_mr_restart_an_25m = value; - ret = hppe_uniphy_channel2_input_output_4_set(dev_id, index, ®_val); - return ret; -} - -sw_error_t -hppe_uniphy_channel2_input_output_4_newaddedfromhere_ch2_speed_25m_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union uniphy_channel2_input_output_4_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_uniphy_channel2_input_output_4_get(dev_id, index, ®_val); - *value = reg_val.bf.newaddedfromhere_ch2_speed_25m; - return ret; -} - -sw_error_t -hppe_uniphy_channel2_input_output_4_newaddedfromhere_ch2_speed_25m_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - union uniphy_channel2_input_output_4_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_uniphy_channel2_input_output_4_get(dev_id, index, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.newaddedfromhere_ch2_speed_25m = value; - ret = hppe_uniphy_channel2_input_output_4_set(dev_id, index, ®_val); - return ret; -} - -sw_error_t -hppe_uniphy_channel2_input_output_4_newaddedfromhere_ch2_mr_np_loaded_25m_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union uniphy_channel2_input_output_4_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_uniphy_channel2_input_output_4_get(dev_id, index, ®_val); - *value = reg_val.bf.newaddedfromhere_ch2_mr_np_loaded_25m; - return ret; -} - -sw_error_t -hppe_uniphy_channel2_input_output_4_newaddedfromhere_ch2_mr_np_loaded_25m_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - union uniphy_channel2_input_output_4_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_uniphy_channel2_input_output_4_get(dev_id, index, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.newaddedfromhere_ch2_mr_np_loaded_25m = value; - ret = hppe_uniphy_channel2_input_output_4_set(dev_id, index, ®_val); - return ret; -} - -sw_error_t -hppe_uniphy_channel2_input_output_4_newaddedfromhere_ch2_force_speed_25m_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union uniphy_channel2_input_output_4_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_uniphy_channel2_input_output_4_get(dev_id, index, ®_val); - *value = reg_val.bf.newaddedfromhere_ch2_force_speed_25m; - return ret; -} - -sw_error_t -hppe_uniphy_channel2_input_output_4_newaddedfromhere_ch2_force_speed_25m_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - union uniphy_channel2_input_output_4_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_uniphy_channel2_input_output_4_get(dev_id, index, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.newaddedfromhere_ch2_force_speed_25m = value; - ret = hppe_uniphy_channel2_input_output_4_set(dev_id, index, ®_val); - return ret; -} - -sw_error_t -hppe_uniphy_channel2_input_output_4_newaddedfromhere_ch2_mr_an_enable_25m_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union uniphy_channel2_input_output_4_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_uniphy_channel2_input_output_4_get(dev_id, index, ®_val); - *value = reg_val.bf.newaddedfromhere_ch2_mr_an_enable_25m; - return ret; -} - -sw_error_t -hppe_uniphy_channel2_input_output_4_newaddedfromhere_ch2_mr_an_enable_25m_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - union uniphy_channel2_input_output_4_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_uniphy_channel2_input_output_4_get(dev_id, index, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.newaddedfromhere_ch2_mr_an_enable_25m = value; - ret = hppe_uniphy_channel2_input_output_4_set(dev_id, index, ®_val); - return ret; -} - -sw_error_t -hppe_uniphy_channel2_input_output_4_newaddedfromhere_ch2_power_on_25m_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union uniphy_channel2_input_output_4_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_uniphy_channel2_input_output_4_get(dev_id, index, ®_val); - *value = reg_val.bf.newaddedfromhere_ch2_power_on_25m; - return ret; -} - -sw_error_t -hppe_uniphy_channel2_input_output_4_newaddedfromhere_ch2_power_on_25m_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - union uniphy_channel2_input_output_4_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_uniphy_channel2_input_output_4_get(dev_id, index, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.newaddedfromhere_ch2_power_on_25m = value; - ret = hppe_uniphy_channel2_input_output_4_set(dev_id, index, ®_val); - return ret; -} - -sw_error_t -hppe_uniphy_channel2_input_output_4_newaddedfromhere_ch2_mr_reg4_ch_25m_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union uniphy_channel2_input_output_4_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_uniphy_channel2_input_output_4_get(dev_id, index, ®_val); - *value = reg_val.bf.newaddedfromhere_ch2_mr_reg4_ch_25m; - return ret; -} - -sw_error_t -hppe_uniphy_channel2_input_output_4_newaddedfromhere_ch2_mr_reg4_ch_25m_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - union uniphy_channel2_input_output_4_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_uniphy_channel2_input_output_4_get(dev_id, index, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.newaddedfromhere_ch2_mr_reg4_ch_25m = value; - ret = hppe_uniphy_channel2_input_output_4_set(dev_id, index, ®_val); - return ret; -} - -sw_error_t -hppe_uniphy_channel3_input_output_4_newaddedfromhere_ch3_mr_main_reset_25m_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union uniphy_channel3_input_output_4_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_uniphy_channel3_input_output_4_get(dev_id, index, ®_val); - *value = reg_val.bf.newaddedfromhere_ch3_mr_main_reset_25m; - return ret; -} - -sw_error_t -hppe_uniphy_channel3_input_output_4_newaddedfromhere_ch3_mr_main_reset_25m_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - union uniphy_channel3_input_output_4_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_uniphy_channel3_input_output_4_get(dev_id, index, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.newaddedfromhere_ch3_mr_main_reset_25m = value; - ret = hppe_uniphy_channel3_input_output_4_set(dev_id, index, ®_val); - return ret; -} - -sw_error_t -hppe_uniphy_channel3_input_output_4_newaddedfromhere_ch3_speed_25m_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union uniphy_channel3_input_output_4_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_uniphy_channel3_input_output_4_get(dev_id, index, ®_val); - *value = reg_val.bf.newaddedfromhere_ch3_speed_25m; - return ret; -} - -sw_error_t -hppe_uniphy_channel3_input_output_4_newaddedfromhere_ch3_speed_25m_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - union uniphy_channel3_input_output_4_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_uniphy_channel3_input_output_4_get(dev_id, index, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.newaddedfromhere_ch3_speed_25m = value; - ret = hppe_uniphy_channel3_input_output_4_set(dev_id, index, ®_val); - return ret; -} - -sw_error_t -hppe_uniphy_channel3_input_output_4_newaddedfromhere_ch3_mr_np_loaded_25m_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union uniphy_channel3_input_output_4_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_uniphy_channel3_input_output_4_get(dev_id, index, ®_val); - *value = reg_val.bf.newaddedfromhere_ch3_mr_np_loaded_25m; - return ret; -} - -sw_error_t -hppe_uniphy_channel3_input_output_4_newaddedfromhere_ch3_mr_np_loaded_25m_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - union uniphy_channel3_input_output_4_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_uniphy_channel3_input_output_4_get(dev_id, index, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.newaddedfromhere_ch3_mr_np_loaded_25m = value; - ret = hppe_uniphy_channel3_input_output_4_set(dev_id, index, ®_val); - return ret; -} - -sw_error_t -hppe_uniphy_channel3_input_output_4_newaddedfromhere_ch3_adp_sw_rstn_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union uniphy_channel3_input_output_4_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_uniphy_channel3_input_output_4_get(dev_id, index, ®_val); - *value = reg_val.bf.newaddedfromhere_ch3_adp_sw_rstn; - return ret; -} - -sw_error_t -hppe_uniphy_channel3_input_output_4_newaddedfromhere_ch3_adp_sw_rstn_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - union uniphy_channel3_input_output_4_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_uniphy_channel3_input_output_4_get(dev_id, index, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.newaddedfromhere_ch3_adp_sw_rstn = value; - ret = hppe_uniphy_channel3_input_output_4_set(dev_id, index, ®_val); - return ret; -} - -sw_error_t -hppe_uniphy_channel3_input_output_4_newaddedfromhere_ch3_power_on_25m_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union uniphy_channel3_input_output_4_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_uniphy_channel3_input_output_4_get(dev_id, index, ®_val); - *value = reg_val.bf.newaddedfromhere_ch3_power_on_25m; - return ret; -} - -sw_error_t -hppe_uniphy_channel3_input_output_4_newaddedfromhere_ch3_power_on_25m_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - union uniphy_channel3_input_output_4_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_uniphy_channel3_input_output_4_get(dev_id, index, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.newaddedfromhere_ch3_power_on_25m = value; - ret = hppe_uniphy_channel3_input_output_4_set(dev_id, index, ®_val); - return ret; -} - -sw_error_t -hppe_uniphy_channel3_input_output_4_newaddedfromhere_ch3_mr_an_enable_25m_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union uniphy_channel3_input_output_4_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_uniphy_channel3_input_output_4_get(dev_id, index, ®_val); - *value = reg_val.bf.newaddedfromhere_ch3_mr_an_enable_25m; - return ret; -} - -sw_error_t -hppe_uniphy_channel3_input_output_4_newaddedfromhere_ch3_mr_an_enable_25m_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - union uniphy_channel3_input_output_4_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_uniphy_channel3_input_output_4_get(dev_id, index, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.newaddedfromhere_ch3_mr_an_enable_25m = value; - ret = hppe_uniphy_channel3_input_output_4_set(dev_id, index, ®_val); - return ret; -} - -sw_error_t -hppe_uniphy_channel3_input_output_4_newaddedfromhere_ch3_mr_reg4_ch_25m_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union uniphy_channel3_input_output_4_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_uniphy_channel3_input_output_4_get(dev_id, index, ®_val); - *value = reg_val.bf.newaddedfromhere_ch3_mr_reg4_ch_25m; - return ret; -} - -sw_error_t -hppe_uniphy_channel3_input_output_4_newaddedfromhere_ch3_mr_reg4_ch_25m_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - union uniphy_channel3_input_output_4_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_uniphy_channel3_input_output_4_get(dev_id, index, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.newaddedfromhere_ch3_mr_reg4_ch_25m = value; - ret = hppe_uniphy_channel3_input_output_4_set(dev_id, index, ®_val); - return ret; -} - -sw_error_t -hppe_uniphy_channel3_input_output_4_newaddedfromhere_ch3_mr_restart_an_25m_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union uniphy_channel3_input_output_4_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_uniphy_channel3_input_output_4_get(dev_id, index, ®_val); - *value = reg_val.bf.newaddedfromhere_ch3_mr_restart_an_25m; - return ret; -} - -sw_error_t -hppe_uniphy_channel3_input_output_4_newaddedfromhere_ch3_mr_restart_an_25m_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - union uniphy_channel3_input_output_4_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_uniphy_channel3_input_output_4_get(dev_id, index, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.newaddedfromhere_ch3_mr_restart_an_25m = value; - ret = hppe_uniphy_channel3_input_output_4_set(dev_id, index, ®_val); - return ret; -} - -sw_error_t -hppe_uniphy_channel3_input_output_4_newaddedfromhere_ch3_rem_phy_lpbk_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union uniphy_channel3_input_output_4_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_uniphy_channel3_input_output_4_get(dev_id, index, ®_val); - *value = reg_val.bf.newaddedfromhere_ch3_rem_phy_lpbk; - return ret; -} - -sw_error_t -hppe_uniphy_channel3_input_output_4_newaddedfromhere_ch3_rem_phy_lpbk_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - union uniphy_channel3_input_output_4_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_uniphy_channel3_input_output_4_get(dev_id, index, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.newaddedfromhere_ch3_rem_phy_lpbk = value; - ret = hppe_uniphy_channel3_input_output_4_set(dev_id, index, ®_val); - return ret; -} - -sw_error_t -hppe_uniphy_channel3_input_output_4_newaddedfromhere_ch3_force_speed_25m_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union uniphy_channel3_input_output_4_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_uniphy_channel3_input_output_4_get(dev_id, index, ®_val); - *value = reg_val.bf.newaddedfromhere_ch3_force_speed_25m; - return ret; -} - -sw_error_t -hppe_uniphy_channel3_input_output_4_newaddedfromhere_ch3_force_speed_25m_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - union uniphy_channel3_input_output_4_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_uniphy_channel3_input_output_4_get(dev_id, index, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.newaddedfromhere_ch3_force_speed_25m = value; - ret = hppe_uniphy_channel3_input_output_4_set(dev_id, index, ®_val); - return ret; -} - -sw_error_t -hppe_uniphy_channel3_input_output_4_newaddedfromhere_ch3_mr_loopback_25m_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union uniphy_channel3_input_output_4_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_uniphy_channel3_input_output_4_get(dev_id, index, ®_val); - *value = reg_val.bf.newaddedfromhere_ch3_mr_loopback_25m; - return ret; -} - -sw_error_t -hppe_uniphy_channel3_input_output_4_newaddedfromhere_ch3_mr_loopback_25m_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - union uniphy_channel3_input_output_4_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_uniphy_channel3_input_output_4_get(dev_id, index, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.newaddedfromhere_ch3_mr_loopback_25m = value; - ret = hppe_uniphy_channel3_input_output_4_set(dev_id, index, ®_val); - return ret; -} - -sw_error_t -hppe_uniphy_channel4_input_output_4_newaddedfromhere_ch4_mr_loopback_25m_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union uniphy_channel4_input_output_4_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_uniphy_channel4_input_output_4_get(dev_id, index, ®_val); - *value = reg_val.bf.newaddedfromhere_ch4_mr_loopback_25m; - return ret; -} - -sw_error_t -hppe_uniphy_channel4_input_output_4_newaddedfromhere_ch4_mr_loopback_25m_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - union uniphy_channel4_input_output_4_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_uniphy_channel4_input_output_4_get(dev_id, index, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.newaddedfromhere_ch4_mr_loopback_25m = value; - ret = hppe_uniphy_channel4_input_output_4_set(dev_id, index, ®_val); - return ret; -} - -sw_error_t -hppe_uniphy_channel4_input_output_4_newaddedfromhere_ch4_mr_reg4_ch_25m_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union uniphy_channel4_input_output_4_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_uniphy_channel4_input_output_4_get(dev_id, index, ®_val); - *value = reg_val.bf.newaddedfromhere_ch4_mr_reg4_ch_25m; - return ret; -} - -sw_error_t -hppe_uniphy_channel4_input_output_4_newaddedfromhere_ch4_mr_reg4_ch_25m_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - union uniphy_channel4_input_output_4_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_uniphy_channel4_input_output_4_get(dev_id, index, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.newaddedfromhere_ch4_mr_reg4_ch_25m = value; - ret = hppe_uniphy_channel4_input_output_4_set(dev_id, index, ®_val); - return ret; -} - -sw_error_t -hppe_uniphy_channel4_input_output_4_newaddedfromhere_ch4_mr_restart_an_25m_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union uniphy_channel4_input_output_4_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_uniphy_channel4_input_output_4_get(dev_id, index, ®_val); - *value = reg_val.bf.newaddedfromhere_ch4_mr_restart_an_25m; - return ret; -} - -sw_error_t -hppe_uniphy_channel4_input_output_4_newaddedfromhere_ch4_mr_restart_an_25m_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - union uniphy_channel4_input_output_4_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_uniphy_channel4_input_output_4_get(dev_id, index, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.newaddedfromhere_ch4_mr_restart_an_25m = value; - ret = hppe_uniphy_channel4_input_output_4_set(dev_id, index, ®_val); - return ret; -} - -sw_error_t -hppe_uniphy_channel4_input_output_4_newaddedfromhere_ch4_mr_an_enable_25m_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union uniphy_channel4_input_output_4_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_uniphy_channel4_input_output_4_get(dev_id, index, ®_val); - *value = reg_val.bf.newaddedfromhere_ch4_mr_an_enable_25m; - return ret; -} - -sw_error_t -hppe_uniphy_channel4_input_output_4_newaddedfromhere_ch4_mr_an_enable_25m_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - union uniphy_channel4_input_output_4_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_uniphy_channel4_input_output_4_get(dev_id, index, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.newaddedfromhere_ch4_mr_an_enable_25m = value; - ret = hppe_uniphy_channel4_input_output_4_set(dev_id, index, ®_val); - return ret; -} - -sw_error_t -hppe_uniphy_channel4_input_output_4_newaddedfromhere_ch4_force_speed_25m_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union uniphy_channel4_input_output_4_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_uniphy_channel4_input_output_4_get(dev_id, index, ®_val); - *value = reg_val.bf.newaddedfromhere_ch4_force_speed_25m; - return ret; -} - -sw_error_t -hppe_uniphy_channel4_input_output_4_newaddedfromhere_ch4_force_speed_25m_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - union uniphy_channel4_input_output_4_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_uniphy_channel4_input_output_4_get(dev_id, index, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.newaddedfromhere_ch4_force_speed_25m = value; - ret = hppe_uniphy_channel4_input_output_4_set(dev_id, index, ®_val); - return ret; -} - -sw_error_t -hppe_uniphy_channel4_input_output_4_newaddedfromhere_ch4_mr_main_reset_25m_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union uniphy_channel4_input_output_4_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_uniphy_channel4_input_output_4_get(dev_id, index, ®_val); - *value = reg_val.bf.newaddedfromhere_ch4_mr_main_reset_25m; - return ret; -} - -sw_error_t -hppe_uniphy_channel4_input_output_4_newaddedfromhere_ch4_mr_main_reset_25m_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - union uniphy_channel4_input_output_4_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_uniphy_channel4_input_output_4_get(dev_id, index, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.newaddedfromhere_ch4_mr_main_reset_25m = value; - ret = hppe_uniphy_channel4_input_output_4_set(dev_id, index, ®_val); - return ret; -} - -sw_error_t -hppe_uniphy_channel4_input_output_4_newaddedfromhere_ch4_power_on_25m_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union uniphy_channel4_input_output_4_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_uniphy_channel4_input_output_4_get(dev_id, index, ®_val); - *value = reg_val.bf.newaddedfromhere_ch4_power_on_25m; - return ret; -} - -sw_error_t -hppe_uniphy_channel4_input_output_4_newaddedfromhere_ch4_power_on_25m_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - union uniphy_channel4_input_output_4_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_uniphy_channel4_input_output_4_get(dev_id, index, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.newaddedfromhere_ch4_power_on_25m = value; - ret = hppe_uniphy_channel4_input_output_4_set(dev_id, index, ®_val); - return ret; -} - -sw_error_t -hppe_uniphy_channel4_input_output_4_newaddedfromhere_ch4_speed_25m_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union uniphy_channel4_input_output_4_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_uniphy_channel4_input_output_4_get(dev_id, index, ®_val); - *value = reg_val.bf.newaddedfromhere_ch4_speed_25m; - return ret; -} - -sw_error_t -hppe_uniphy_channel4_input_output_4_newaddedfromhere_ch4_speed_25m_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - union uniphy_channel4_input_output_4_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_uniphy_channel4_input_output_4_get(dev_id, index, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.newaddedfromhere_ch4_speed_25m = value; - ret = hppe_uniphy_channel4_input_output_4_set(dev_id, index, ®_val); - return ret; -} - -sw_error_t -hppe_uniphy_channel4_input_output_4_newaddedfromhere_ch4_rem_phy_lpbk_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union uniphy_channel4_input_output_4_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_uniphy_channel4_input_output_4_get(dev_id, index, ®_val); - *value = reg_val.bf.newaddedfromhere_ch4_rem_phy_lpbk; - return ret; -} - -sw_error_t -hppe_uniphy_channel4_input_output_4_newaddedfromhere_ch4_rem_phy_lpbk_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - union uniphy_channel4_input_output_4_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_uniphy_channel4_input_output_4_get(dev_id, index, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.newaddedfromhere_ch4_rem_phy_lpbk = value; - ret = hppe_uniphy_channel4_input_output_4_set(dev_id, index, ®_val); - return ret; -} - -sw_error_t -hppe_uniphy_channel4_input_output_4_newaddedfromhere_ch4_mr_np_loaded_25m_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union uniphy_channel4_input_output_4_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_uniphy_channel4_input_output_4_get(dev_id, index, ®_val); - *value = reg_val.bf.newaddedfromhere_ch4_mr_np_loaded_25m; - return ret; -} - -sw_error_t -hppe_uniphy_channel4_input_output_4_newaddedfromhere_ch4_mr_np_loaded_25m_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - union uniphy_channel4_input_output_4_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_uniphy_channel4_input_output_4_get(dev_id, index, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.newaddedfromhere_ch4_mr_np_loaded_25m = value; - ret = hppe_uniphy_channel4_input_output_4_set(dev_id, index, ®_val); - return ret; -} - -sw_error_t -hppe_uniphy_channel4_input_output_4_newaddedfromhere_ch4_adp_sw_rstn_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union uniphy_channel4_input_output_4_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_uniphy_channel4_input_output_4_get(dev_id, index, ®_val); - *value = reg_val.bf.newaddedfromhere_ch4_adp_sw_rstn; - return ret; -} - -sw_error_t -hppe_uniphy_channel4_input_output_4_newaddedfromhere_ch4_adp_sw_rstn_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - union uniphy_channel4_input_output_4_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_uniphy_channel4_input_output_4_get(dev_id, index, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.newaddedfromhere_ch4_adp_sw_rstn = value; - ret = hppe_uniphy_channel4_input_output_4_set(dev_id, index, ®_val); - return ret; -} - -sw_error_t -hppe_sr_xs_pcs_kr_sts1_plu_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union sr_xs_pcs_kr_sts1_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_sr_xs_pcs_kr_sts1_get(dev_id, index, ®_val); - *value = reg_val.bf.plu; - return ret; -} - -sw_error_t -hppe_sr_xs_pcs_kr_sts1_plu_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - union sr_xs_pcs_kr_sts1_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_sr_xs_pcs_kr_sts1_get(dev_id, index, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.plu = value; - ret = hppe_sr_xs_pcs_kr_sts1_set(dev_id, index, ®_val); - return ret; -} - -sw_error_t -hppe_sr_xs_pcs_kr_sts1_prbs31abl_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union sr_xs_pcs_kr_sts1_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_sr_xs_pcs_kr_sts1_get(dev_id, index, ®_val); - *value = reg_val.bf.prbs31abl; - return ret; -} - -sw_error_t -hppe_sr_xs_pcs_kr_sts1_prbs31abl_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - union sr_xs_pcs_kr_sts1_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_sr_xs_pcs_kr_sts1_get(dev_id, index, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.prbs31abl = value; - ret = hppe_sr_xs_pcs_kr_sts1_set(dev_id, index, ®_val); - return ret; -} - -sw_error_t -hppe_sr_xs_pcs_kr_sts1_rpcs_bklk_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union sr_xs_pcs_kr_sts1_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_sr_xs_pcs_kr_sts1_get(dev_id, index, ®_val); - *value = reg_val.bf.rpcs_bklk; - return ret; -} - -sw_error_t -hppe_sr_xs_pcs_kr_sts1_rpcs_bklk_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - union sr_xs_pcs_kr_sts1_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_sr_xs_pcs_kr_sts1_get(dev_id, index, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.rpcs_bklk = value; - ret = hppe_sr_xs_pcs_kr_sts1_set(dev_id, index, ®_val); - return ret; -} - -sw_error_t -hppe_sr_xs_pcs_kr_sts1_prcs_hiber_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union sr_xs_pcs_kr_sts1_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_sr_xs_pcs_kr_sts1_get(dev_id, index, ®_val); - *value = reg_val.bf.prcs_hiber; - return ret; -} - -sw_error_t -hppe_sr_xs_pcs_kr_sts1_prcs_hiber_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - union sr_xs_pcs_kr_sts1_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_sr_xs_pcs_kr_sts1_get(dev_id, index, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.prcs_hiber = value; - ret = hppe_sr_xs_pcs_kr_sts1_set(dev_id, index, ®_val); - return ret; -} - -sw_error_t -hppe_sr_xs_pcs_kr_sts1_prbs9abl_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union sr_xs_pcs_kr_sts1_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_sr_xs_pcs_kr_sts1_get(dev_id, index, ®_val); - *value = reg_val.bf.prbs9abl; - return ret; -} - -sw_error_t -hppe_sr_xs_pcs_kr_sts1_prbs9abl_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - union sr_xs_pcs_kr_sts1_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_sr_xs_pcs_kr_sts1_get(dev_id, index, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.prbs9abl = value; - ret = hppe_sr_xs_pcs_kr_sts1_set(dev_id, index, ®_val); - return ret; -} - -sw_error_t -hppe_vr_xs_pcs_dig_ctrl1_vr_rst_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union vr_xs_pcs_dig_ctrl1_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_vr_xs_pcs_dig_ctrl1_get(dev_id, index, ®_val); - *value = reg_val.bf.vr_rst; - return ret; -} - -sw_error_t -hppe_vr_xs_pcs_dig_ctrl1_vr_rst_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - union vr_xs_pcs_dig_ctrl1_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_vr_xs_pcs_dig_ctrl1_get(dev_id, index, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.vr_rst = value; - ret = hppe_vr_xs_pcs_dig_ctrl1_set(dev_id, index, ®_val); - return ret; -} - -sw_error_t -hppe_vr_xs_pcs_dig_ctrl1_usra_rst_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union vr_xs_pcs_dig_ctrl1_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_vr_xs_pcs_dig_ctrl1_get(dev_id, index, ®_val); - *value = reg_val.bf.usra_rst; - return ret; -} - -sw_error_t -hppe_vr_xs_pcs_dig_ctrl1_usra_rst_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - union vr_xs_pcs_dig_ctrl1_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_vr_xs_pcs_dig_ctrl1_get(dev_id, index, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.usra_rst = value; - ret = hppe_vr_xs_pcs_dig_ctrl1_set(dev_id, index, ®_val); - return ret; -} - -sw_error_t -hppe_vr_xs_pcs_dig_ctrl1_en_2_5g_mode_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union vr_xs_pcs_dig_ctrl1_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_vr_xs_pcs_dig_ctrl1_get(dev_id, index, ®_val); - *value = reg_val.bf.en_2_5g_mode; - return ret; -} - -sw_error_t -hppe_vr_xs_pcs_dig_ctrl1_en_2_5g_mode_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - union vr_xs_pcs_dig_ctrl1_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_vr_xs_pcs_dig_ctrl1_get(dev_id, index, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.en_2_5g_mode = value; - ret = hppe_vr_xs_pcs_dig_ctrl1_set(dev_id, index, ®_val); - return ret; -} - -sw_error_t -hppe_vr_xs_pcs_dig_ctrl1_dskbyp_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union vr_xs_pcs_dig_ctrl1_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_vr_xs_pcs_dig_ctrl1_get(dev_id, index, ®_val); - *value = reg_val.bf.dskbyp; - return ret; -} - -sw_error_t -hppe_vr_xs_pcs_dig_ctrl1_dskbyp_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - union vr_xs_pcs_dig_ctrl1_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_vr_xs_pcs_dig_ctrl1_get(dev_id, index, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.dskbyp = value; - ret = hppe_vr_xs_pcs_dig_ctrl1_set(dev_id, index, ®_val); - return ret; -} - -sw_error_t -hppe_vr_xs_pcs_dig_ctrl1_en_vsmmd1_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union vr_xs_pcs_dig_ctrl1_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_vr_xs_pcs_dig_ctrl1_get(dev_id, index, ®_val); - *value = reg_val.bf.en_vsmmd1; - return ret; -} - -sw_error_t -hppe_vr_xs_pcs_dig_ctrl1_en_vsmmd1_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - union vr_xs_pcs_dig_ctrl1_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_vr_xs_pcs_dig_ctrl1_get(dev_id, index, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.en_vsmmd1 = value; - ret = hppe_vr_xs_pcs_dig_ctrl1_set(dev_id, index, ®_val); - return ret; -} - -sw_error_t -hppe_vr_xs_pcs_dig_ctrl1_init_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union vr_xs_pcs_dig_ctrl1_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_vr_xs_pcs_dig_ctrl1_get(dev_id, index, ®_val); - *value = reg_val.bf.init; - return ret; -} - -sw_error_t -hppe_vr_xs_pcs_dig_ctrl1_init_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - union vr_xs_pcs_dig_ctrl1_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_vr_xs_pcs_dig_ctrl1_get(dev_id, index, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.init = value; - ret = hppe_vr_xs_pcs_dig_ctrl1_set(dev_id, index, ®_val); - return ret; -} - -sw_error_t -hppe_vr_xs_pcs_dig_ctrl1_cl37_bp_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union vr_xs_pcs_dig_ctrl1_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_vr_xs_pcs_dig_ctrl1_get(dev_id, index, ®_val); - *value = reg_val.bf.cl37_bp; - return ret; -} - -sw_error_t -hppe_vr_xs_pcs_dig_ctrl1_cl37_bp_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - union vr_xs_pcs_dig_ctrl1_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_vr_xs_pcs_dig_ctrl1_get(dev_id, index, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.cl37_bp = value; - ret = hppe_vr_xs_pcs_dig_ctrl1_set(dev_id, index, ®_val); - return ret; -} - -sw_error_t -hppe_vr_xs_pcs_dig_ctrl1_pwrsv_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union vr_xs_pcs_dig_ctrl1_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_vr_xs_pcs_dig_ctrl1_get(dev_id, index, ®_val); - *value = reg_val.bf.pwrsv; - return ret; -} - -sw_error_t -hppe_vr_xs_pcs_dig_ctrl1_pwrsv_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - union vr_xs_pcs_dig_ctrl1_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_vr_xs_pcs_dig_ctrl1_get(dev_id, index, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.pwrsv = value; - ret = hppe_vr_xs_pcs_dig_ctrl1_set(dev_id, index, ®_val); - return ret; -} - -sw_error_t -hppe_vr_xs_pcs_dig_ctrl1_dtxlaned_3_1_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union vr_xs_pcs_dig_ctrl1_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_vr_xs_pcs_dig_ctrl1_get(dev_id, index, ®_val); - *value = reg_val.bf.dtxlaned_3_1; - return ret; -} - -sw_error_t -hppe_vr_xs_pcs_dig_ctrl1_dtxlaned_3_1_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - union vr_xs_pcs_dig_ctrl1_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_vr_xs_pcs_dig_ctrl1_get(dev_id, index, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.dtxlaned_3_1 = value; - ret = hppe_vr_xs_pcs_dig_ctrl1_set(dev_id, index, ®_val); - return ret; -} - -sw_error_t -hppe_vr_xs_pcs_dig_ctrl1_usxg_en_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union vr_xs_pcs_dig_ctrl1_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_vr_xs_pcs_dig_ctrl1_get(dev_id, index, ®_val); - *value = reg_val.bf.usxg_en; - return ret; -} - -sw_error_t -hppe_vr_xs_pcs_dig_ctrl1_usxg_en_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - union vr_xs_pcs_dig_ctrl1_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_vr_xs_pcs_dig_ctrl1_get(dev_id, index, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.usxg_en = value; - ret = hppe_vr_xs_pcs_dig_ctrl1_set(dev_id, index, ®_val); - return ret; -} - -sw_error_t -hppe_vr_xs_pcs_dig_ctrl1_r2tlbe_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union vr_xs_pcs_dig_ctrl1_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_vr_xs_pcs_dig_ctrl1_get(dev_id, index, ®_val); - *value = reg_val.bf.r2tlbe; - return ret; -} - -sw_error_t -hppe_vr_xs_pcs_dig_ctrl1_r2tlbe_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - union vr_xs_pcs_dig_ctrl1_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_vr_xs_pcs_dig_ctrl1_get(dev_id, index, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.r2tlbe = value; - ret = hppe_vr_xs_pcs_dig_ctrl1_set(dev_id, index, ®_val); - return ret; -} - -sw_error_t -hppe_vr_xs_pcs_dig_ctrl1_cr_cjn_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union vr_xs_pcs_dig_ctrl1_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_vr_xs_pcs_dig_ctrl1_get(dev_id, index, ®_val); - *value = reg_val.bf.cr_cjn; - return ret; -} - -sw_error_t -hppe_vr_xs_pcs_dig_ctrl1_cr_cjn_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - union vr_xs_pcs_dig_ctrl1_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_vr_xs_pcs_dig_ctrl1_get(dev_id, index, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.cr_cjn = value; - ret = hppe_vr_xs_pcs_dig_ctrl1_set(dev_id, index, ®_val); - return ret; -} - -sw_error_t -hppe_vr_xs_pcs_dig_ctrl1_dtxlaned_0_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union vr_xs_pcs_dig_ctrl1_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_vr_xs_pcs_dig_ctrl1_get(dev_id, index, ®_val); - *value = reg_val.bf.dtxlaned_0; - return ret; -} - -sw_error_t -hppe_vr_xs_pcs_dig_ctrl1_dtxlaned_0_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - union vr_xs_pcs_dig_ctrl1_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_vr_xs_pcs_dig_ctrl1_get(dev_id, index, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.dtxlaned_0 = value; - ret = hppe_vr_xs_pcs_dig_ctrl1_set(dev_id, index, ®_val); - return ret; -} - -sw_error_t -hppe_vr_xs_pcs_dig_ctrl1_byp_pwrup_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union vr_xs_pcs_dig_ctrl1_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_vr_xs_pcs_dig_ctrl1_get(dev_id, index, ®_val); - *value = reg_val.bf.byp_pwrup; - return ret; -} - -sw_error_t -hppe_vr_xs_pcs_dig_ctrl1_byp_pwrup_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - union vr_xs_pcs_dig_ctrl1_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_vr_xs_pcs_dig_ctrl1_get(dev_id, index, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.byp_pwrup = value; - ret = hppe_vr_xs_pcs_dig_ctrl1_set(dev_id, index, ®_val); - return ret; -} - -sw_error_t -hppe_sr_mii_ctrl_lpm_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union sr_mii_ctrl_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_sr_mii_ctrl_get(dev_id, index, ®_val); - *value = reg_val.bf.lpm; - return ret; -} - -sw_error_t -hppe_sr_mii_ctrl_lpm_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - union sr_mii_ctrl_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_sr_mii_ctrl_get(dev_id, index, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.lpm = value; - ret = hppe_sr_mii_ctrl_set(dev_id, index, ®_val); - return ret; -} - -sw_error_t -hppe_sr_mii_ctrl_duplex_mode_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union sr_mii_ctrl_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_sr_mii_ctrl_get(dev_id, index, ®_val); - *value = reg_val.bf.duplex_mode; - return ret; -} - -sw_error_t -hppe_sr_mii_ctrl_duplex_mode_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - union sr_mii_ctrl_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_sr_mii_ctrl_get(dev_id, index, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.duplex_mode = value; - ret = hppe_sr_mii_ctrl_set(dev_id, index, ®_val); - return ret; -} - -sw_error_t -hppe_sr_mii_ctrl_ss6_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union sr_mii_ctrl_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_sr_mii_ctrl_get(dev_id, index, ®_val); - *value = reg_val.bf.ss6; - return ret; -} - -sw_error_t -hppe_sr_mii_ctrl_ss6_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - union sr_mii_ctrl_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_sr_mii_ctrl_get(dev_id, index, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.ss6 = value; - ret = hppe_sr_mii_ctrl_set(dev_id, index, ®_val); - return ret; -} - -sw_error_t -hppe_sr_mii_ctrl_ss5_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union sr_mii_ctrl_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_sr_mii_ctrl_get(dev_id, index, ®_val); - *value = reg_val.bf.ss5; - return ret; -} - -sw_error_t -hppe_sr_mii_ctrl_ss5_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - union sr_mii_ctrl_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_sr_mii_ctrl_get(dev_id, index, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.ss5 = value; - ret = hppe_sr_mii_ctrl_set(dev_id, index, ®_val); - return ret; -} - -sw_error_t -hppe_sr_mii_ctrl_ss13_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union sr_mii_ctrl_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_sr_mii_ctrl_get(dev_id, index, ®_val); - *value = reg_val.bf.ss13; - return ret; -} - -sw_error_t -hppe_sr_mii_ctrl_ss13_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - union sr_mii_ctrl_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_sr_mii_ctrl_get(dev_id, index, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.ss13 = value; - ret = hppe_sr_mii_ctrl_set(dev_id, index, ®_val); - return ret; -} - -sw_error_t -hppe_sr_mii_ctrl_an_enable_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union sr_mii_ctrl_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_sr_mii_ctrl_get(dev_id, index, ®_val); - *value = reg_val.bf.an_enable; - return ret; -} - -sw_error_t -hppe_sr_mii_ctrl_an_enable_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - union sr_mii_ctrl_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_sr_mii_ctrl_get(dev_id, index, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.an_enable = value; - ret = hppe_sr_mii_ctrl_set(dev_id, index, ®_val); - return ret; -} - -sw_error_t -hppe_sr_mii_ctrl_restart_an_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union sr_mii_ctrl_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_sr_mii_ctrl_get(dev_id, index, ®_val); - *value = reg_val.bf.restart_an; - return ret; -} - -sw_error_t -hppe_sr_mii_ctrl_restart_an_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - union sr_mii_ctrl_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_sr_mii_ctrl_get(dev_id, index, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.restart_an = value; - ret = hppe_sr_mii_ctrl_set(dev_id, index, ®_val); - return ret; -} - -sw_error_t -hppe_sr_mii_ctrl_rst_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union sr_mii_ctrl_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_sr_mii_ctrl_get(dev_id, index, ®_val); - *value = reg_val.bf.rst; - return ret; -} - -sw_error_t -hppe_sr_mii_ctrl_rst_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - union sr_mii_ctrl_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_sr_mii_ctrl_get(dev_id, index, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.rst = value; - ret = hppe_sr_mii_ctrl_set(dev_id, index, ®_val); - return ret; -} - -sw_error_t -hppe_sr_mii_ctrl_lbe_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union sr_mii_ctrl_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_sr_mii_ctrl_get(dev_id, index, ®_val); - *value = reg_val.bf.lbe; - return ret; -} - -sw_error_t -hppe_sr_mii_ctrl_lbe_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - union sr_mii_ctrl_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_sr_mii_ctrl_get(dev_id, index, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.lbe = value; - ret = hppe_sr_mii_ctrl_set(dev_id, index, ®_val); - return ret; -} - -sw_error_t -hppe_vr_mii_an_ctrl_pcs_mode_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union vr_mii_an_ctrl_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_vr_mii_an_ctrl_get(dev_id, index, ®_val); - *value = reg_val.bf.pcs_mode; - return ret; -} - -sw_error_t -hppe_vr_mii_an_ctrl_pcs_mode_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - union vr_mii_an_ctrl_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_vr_mii_an_ctrl_get(dev_id, index, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.pcs_mode = value; - ret = hppe_vr_mii_an_ctrl_set(dev_id, index, ®_val); - return ret; -} - -sw_error_t -hppe_vr_mii_an_ctrl_mii_an_intr_en_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union vr_mii_an_ctrl_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_vr_mii_an_ctrl_get(dev_id, index, ®_val); - *value = reg_val.bf.mii_an_intr_en; - return ret; -} - -sw_error_t -hppe_vr_mii_an_ctrl_mii_an_intr_en_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - union vr_mii_an_ctrl_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_vr_mii_an_ctrl_get(dev_id, index, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.mii_an_intr_en = value; - ret = hppe_vr_mii_an_ctrl_set(dev_id, index, ®_val); - return ret; -} - -sw_error_t -hppe_vr_mii_an_ctrl_sgmii_link_sts_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union vr_mii_an_ctrl_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_vr_mii_an_ctrl_get(dev_id, index, ®_val); - *value = reg_val.bf.sgmii_link_sts; - return ret; -} - -sw_error_t -hppe_vr_mii_an_ctrl_sgmii_link_sts_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - union vr_mii_an_ctrl_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_vr_mii_an_ctrl_get(dev_id, index, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.sgmii_link_sts = value; - ret = hppe_vr_mii_an_ctrl_set(dev_id, index, ®_val); - return ret; -} - -sw_error_t -hppe_vr_mii_an_ctrl_tx_config_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union vr_mii_an_ctrl_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_vr_mii_an_ctrl_get(dev_id, index, ®_val); - *value = reg_val.bf.tx_config; - return ret; -} - -sw_error_t -hppe_vr_mii_an_ctrl_tx_config_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - union vr_mii_an_ctrl_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_vr_mii_an_ctrl_get(dev_id, index, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.tx_config = value; - ret = hppe_vr_mii_an_ctrl_set(dev_id, index, ®_val); - return ret; -} - -sw_error_t -hppe_vr_mii_an_ctrl_mii_ctrl_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union vr_mii_an_ctrl_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_vr_mii_an_ctrl_get(dev_id, index, ®_val); - *value = reg_val.bf.mii_ctrl; - return ret; -} - -sw_error_t -hppe_vr_mii_an_ctrl_mii_ctrl_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - union vr_mii_an_ctrl_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_vr_mii_an_ctrl_get(dev_id, index, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.mii_ctrl = value; - ret = hppe_vr_mii_an_ctrl_set(dev_id, index, ®_val); - return ret; -} - -sw_error_t -hppe_vr_mii_an_intr_sts_usxg_an_sts_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union vr_mii_an_intr_sts_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_vr_mii_an_intr_sts_get(dev_id, index, ®_val); - *value = reg_val.bf.usxg_an_sts; - return ret; -} - -sw_error_t -hppe_vr_mii_an_intr_sts_usxg_an_sts_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - union vr_mii_an_intr_sts_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_vr_mii_an_intr_sts_get(dev_id, index, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.usxg_an_sts = value; - ret = hppe_vr_mii_an_intr_sts_set(dev_id, index, ®_val); - return ret; -} - -sw_error_t -hppe_vr_mii_an_intr_sts_cl37_ansgm_sts_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union vr_mii_an_intr_sts_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_vr_mii_an_intr_sts_get(dev_id, index, ®_val); - *value = reg_val.bf.cl37_ansgm_sts; - return ret; -} - -sw_error_t -hppe_vr_mii_an_intr_sts_cl37_ansgm_sts_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - union vr_mii_an_intr_sts_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_vr_mii_an_intr_sts_get(dev_id, index, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.cl37_ansgm_sts = value; - ret = hppe_vr_mii_an_intr_sts_set(dev_id, index, ®_val); - return ret; -} - -sw_error_t -hppe_vr_mii_an_intr_sts_cl37_ancmplt_intr_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union vr_mii_an_intr_sts_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_vr_mii_an_intr_sts_get(dev_id, index, ®_val); - *value = reg_val.bf.cl37_ancmplt_intr; - return ret; -} - -sw_error_t -hppe_vr_mii_an_intr_sts_cl37_ancmplt_intr_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - union vr_mii_an_intr_sts_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_vr_mii_an_intr_sts_get(dev_id, index, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.cl37_ancmplt_intr = value; - ret = hppe_vr_mii_an_intr_sts_set(dev_id, index, ®_val); - return ret; -} - -sw_error_t -hppe_uniphy_pll_control_vco_related_selection_get( - a_uint32_t dev_id, - a_uint32_t index, - union uniphy_pll_control_vco_related_selection_u *value) -{ - if (index >= UNIPHY_PLL_CONTROL_VCO_RELATED_SELECTION_MAX_ENTRY) - return SW_OUT_OF_RANGE; - return hppe_uniphy_reg_get( - dev_id, - NSS_UNIPHY_BASE_ADDR + UNIPHY_PLL_CONTROL_VCO_RELATED_SELECTION_ADDRESS, - index * UNIPHY_PLL_CONTROL_VCO_RELATED_SELECTION_INC, - &value->val); -} - -sw_error_t -hppe_uniphy_pll_control_vco_related_selection_set( - a_uint32_t dev_id, - a_uint32_t index, - union uniphy_pll_control_vco_related_selection_u *value) -{ - return hppe_uniphy_reg_set( - dev_id, - NSS_UNIPHY_BASE_ADDR + UNIPHY_PLL_CONTROL_VCO_RELATED_SELECTION_ADDRESS, - index * UNIPHY_PLL_CONTROL_VCO_RELATED_SELECTION_INC, - value->val); -} - -sw_error_t -hppe_uniphy_tx_ac_jtag_mux_driver_selection_get( - a_uint32_t dev_id, - a_uint32_t index, - union uniphy_tx_ac_jtag_mux_driver_selection_u *value) -{ - if (index >= UNIPHY_TX_AC_JTAG_MUX_DRIVER_SELECTION_MAX_ENTRY) - return SW_OUT_OF_RANGE; - return hppe_uniphy_reg_get( - dev_id, - NSS_UNIPHY_BASE_ADDR + UNIPHY_TX_AC_JTAG_MUX_DRIVER_SELECTION_ADDRESS, - index * UNIPHY_TX_AC_JTAG_MUX_DRIVER_SELECTION_INC, - &value->val); -} - -sw_error_t -hppe_uniphy_tx_ac_jtag_mux_driver_selection_set( - a_uint32_t dev_id, - a_uint32_t index, - union uniphy_tx_ac_jtag_mux_driver_selection_u *value) -{ - return hppe_uniphy_reg_set( - dev_id, - NSS_UNIPHY_BASE_ADDR + UNIPHY_TX_AC_JTAG_MUX_DRIVER_SELECTION_ADDRESS, - index * UNIPHY_TX_AC_JTAG_MUX_DRIVER_SELECTION_INC, - value->val); -} - -sw_error_t -hppe_uniphy_resistor_calibration_1_get( - a_uint32_t dev_id, - a_uint32_t index, - union uniphy_resistor_calibration_1_u *value) -{ - if (index >= UNIPHY_RESISTOR_CALIBRATION_1_MAX_ENTRY) - return SW_OUT_OF_RANGE; - return hppe_uniphy_reg_get( - dev_id, - NSS_UNIPHY_BASE_ADDR + UNIPHY_RESISTOR_CALIBRATION_1_ADDRESS, - index * UNIPHY_RESISTOR_CALIBRATION_1_INC, - &value->val); -} - -sw_error_t -hppe_uniphy_resistor_calibration_1_set( - a_uint32_t dev_id, - a_uint32_t index, - union uniphy_resistor_calibration_1_u *value) -{ - return hppe_uniphy_reg_set( - dev_id, - NSS_UNIPHY_BASE_ADDR + UNIPHY_RESISTOR_CALIBRATION_1_ADDRESS, - index * UNIPHY_RESISTOR_CALIBRATION_1_INC, - value->val); -} - -sw_error_t -hppe_uniphy_pll_vco_related_control_1_get( - a_uint32_t dev_id, - a_uint32_t index, - union uniphy_pll_vco_related_control_1_u *value) -{ - if (index >= UNIPHY_PLL_VCO_RELATED_CONTROL_1_MAX_ENTRY) - return SW_OUT_OF_RANGE; - return hppe_uniphy_reg_get( - dev_id, - NSS_UNIPHY_BASE_ADDR + UNIPHY_PLL_VCO_RELATED_CONTROL_1_ADDRESS, - index * UNIPHY_PLL_VCO_RELATED_CONTROL_1_INC, - &value->val); -} - -sw_error_t -hppe_uniphy_pll_vco_related_control_1_set( - a_uint32_t dev_id, - a_uint32_t index, - union uniphy_pll_vco_related_control_1_u *value) -{ - return hppe_uniphy_reg_set( - dev_id, - NSS_UNIPHY_BASE_ADDR + UNIPHY_PLL_VCO_RELATED_CONTROL_1_ADDRESS, - index * UNIPHY_PLL_VCO_RELATED_CONTROL_1_INC, - value->val); -} - -sw_error_t -hppe_uniphy_rx_afe_2_get( - a_uint32_t dev_id, - a_uint32_t index, - union uniphy_rx_afe_2_u *value) -{ - if (index >= UNIPHY_RX_AFE_2_MAX_ENTRY) - return SW_OUT_OF_RANGE; - return hppe_uniphy_reg_get( - dev_id, - NSS_UNIPHY_BASE_ADDR + UNIPHY_RX_AFE_2_ADDRESS, - index * UNIPHY_RX_AFE_2_INC, - &value->val); -} - -sw_error_t -hppe_uniphy_rx_afe_2_set( - a_uint32_t dev_id, - a_uint32_t index, - union uniphy_rx_afe_2_u *value) -{ - return hppe_uniphy_reg_set( - dev_id, - NSS_UNIPHY_BASE_ADDR + UNIPHY_RX_AFE_2_ADDRESS, - index * UNIPHY_RX_AFE_2_INC, - value->val); -} - -sw_error_t -hppe_bandgap_ip_mbias_2_get( - a_uint32_t dev_id, - a_uint32_t index, - union bandgap_ip_mbias_2_u *value) -{ - if (index >= BANDGAP_IP_MBIAS_2_MAX_ENTRY) - return SW_OUT_OF_RANGE; - return hppe_uniphy_reg_get( - dev_id, - NSS_UNIPHY_BASE_ADDR + BANDGAP_IP_MBIAS_2_ADDRESS, - index * BANDGAP_IP_MBIAS_2_INC, - &value->val); -} - -sw_error_t -hppe_bandgap_ip_mbias_2_set( - a_uint32_t dev_id, - a_uint32_t index, - union bandgap_ip_mbias_2_u *value) -{ - return hppe_uniphy_reg_set( - dev_id, - NSS_UNIPHY_BASE_ADDR + BANDGAP_IP_MBIAS_2_ADDRESS, - index * BANDGAP_IP_MBIAS_2_INC, - value->val); -} - -sw_error_t -hppe_ldo_0p9v_related_1_get( - a_uint32_t dev_id, - a_uint32_t index, - union ldo_0p9v_related_1_u *value) -{ - if (index >= LDO_0P9V_RELATED_1_MAX_ENTRY) - return SW_OUT_OF_RANGE; - return hppe_uniphy_reg_get( - dev_id, - NSS_UNIPHY_BASE_ADDR + LDO_0P9V_RELATED_1_ADDRESS, - index * LDO_0P9V_RELATED_1_INC, - &value->val); -} - -sw_error_t -hppe_ldo_0p9v_related_1_set( - a_uint32_t dev_id, - a_uint32_t index, - union ldo_0p9v_related_1_u *value) -{ - return hppe_uniphy_reg_set( - dev_id, - NSS_UNIPHY_BASE_ADDR + LDO_0P9V_RELATED_1_ADDRESS, - index * LDO_0P9V_RELATED_1_INC, - value->val); -} - -sw_error_t -hppe_otp_vtt_ldo_related_get( - a_uint32_t dev_id, - a_uint32_t index, - union otp_vtt_ldo_related_u *value) -{ - if (index >= OTP_VTT_LDO_RELATED_MAX_ENTRY) - return SW_OUT_OF_RANGE; - return hppe_uniphy_reg_get( - dev_id, - NSS_UNIPHY_BASE_ADDR + OTP_VTT_LDO_RELATED_ADDRESS, - index * OTP_VTT_LDO_RELATED_INC, - &value->val); -} - -sw_error_t -hppe_otp_vtt_ldo_related_set( - a_uint32_t dev_id, - a_uint32_t index, - union otp_vtt_ldo_related_u *value) -{ - return hppe_uniphy_reg_set( - dev_id, - NSS_UNIPHY_BASE_ADDR + OTP_VTT_LDO_RELATED_ADDRESS, - index * OTP_VTT_LDO_RELATED_INC, - value->val); -} - -sw_error_t -hppe_otp_temperature_compensate_1_get( - a_uint32_t dev_id, - a_uint32_t index, - union otp_temperature_compensate_1_u *value) -{ - if (index >= OTP_TEMPERATURE_COMPENSATE_1_MAX_ENTRY) - return SW_OUT_OF_RANGE; - return hppe_uniphy_reg_get( - dev_id, - NSS_UNIPHY_BASE_ADDR + OTP_TEMPERATURE_COMPENSATE_1_ADDRESS, - index * OTP_TEMPERATURE_COMPENSATE_1_INC, - &value->val); -} - -sw_error_t -hppe_otp_temperature_compensate_1_set( - a_uint32_t dev_id, - a_uint32_t index, - union otp_temperature_compensate_1_u *value) -{ - return hppe_uniphy_reg_set( - dev_id, - NSS_UNIPHY_BASE_ADDR + OTP_TEMPERATURE_COMPENSATE_1_ADDRESS, - index * OTP_TEMPERATURE_COMPENSATE_1_INC, - value->val); -} - -sw_error_t -hppe_pll_vco_related_control_1_get( - a_uint32_t dev_id, - a_uint32_t index, - union pll_vco_related_control_1_u *value) -{ - if (index >= PLL_VCO_RELATED_CONTROL_1_MAX_ENTRY) - return SW_OUT_OF_RANGE; - return hppe_uniphy_reg_get( - dev_id, - NSS_UNIPHY_BASE_ADDR + PLL_VCO_RELATED_CONTROL_1_ADDRESS, - index * PLL_VCO_RELATED_CONTROL_1_INC, - &value->val); -} - -sw_error_t -hppe_pll_vco_related_control_1_set( - a_uint32_t dev_id, - a_uint32_t index, - union pll_vco_related_control_1_u *value) -{ - return hppe_uniphy_reg_set( - dev_id, - NSS_UNIPHY_BASE_ADDR + PLL_VCO_RELATED_CONTROL_1_ADDRESS, - index * PLL_VCO_RELATED_CONTROL_1_INC, - value->val); -} - -sw_error_t -hppe_pll_control_vco_related_selection_2_get( - a_uint32_t dev_id, - a_uint32_t index, - union pll_control_vco_related_selection_2_u *value) -{ - if (index >= PLL_CONTROL_VCO_RELATED_SELECTION_2_MAX_ENTRY) - return SW_OUT_OF_RANGE; - return hppe_uniphy_reg_get( - dev_id, - NSS_UNIPHY_BASE_ADDR + PLL_CONTROL_VCO_RELATED_SELECTION_2_ADDRESS, - index * PLL_CONTROL_VCO_RELATED_SELECTION_2_INC, - &value->val); -} - -sw_error_t -hppe_pll_control_vco_related_selection_2_set( - a_uint32_t dev_id, - a_uint32_t index, - union pll_control_vco_related_selection_2_u *value) -{ - return hppe_uniphy_reg_set( - dev_id, - NSS_UNIPHY_BASE_ADDR + PLL_CONTROL_VCO_RELATED_SELECTION_2_ADDRESS, - index * PLL_CONTROL_VCO_RELATED_SELECTION_2_INC, - value->val); -} - -sw_error_t -hppe_uniphy_pll_control_vco_related_selection_mmd1_reg_src_uphy_pll_vco_gain_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union uniphy_pll_control_vco_related_selection_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_uniphy_pll_control_vco_related_selection_get(dev_id, index, ®_val); - *value = reg_val.bf.mmd1_reg_src_uphy_pll_vco_gain; - return ret; -} - -sw_error_t -hppe_uniphy_pll_control_vco_related_selection_mmd1_reg_src_uphy_pll_vco_gain_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - union uniphy_pll_control_vco_related_selection_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_uniphy_pll_control_vco_related_selection_get(dev_id, index, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.mmd1_reg_src_uphy_pll_vco_gain = value; - ret = hppe_uniphy_pll_control_vco_related_selection_set(dev_id, index, ®_val); - return ret; -} - -sw_error_t -hppe_uniphy_pll_control_vco_related_selection_mmd1_reg_src_uphy_pll_vco_temp_cmp_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union uniphy_pll_control_vco_related_selection_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_uniphy_pll_control_vco_related_selection_get(dev_id, index, ®_val); - *value = reg_val.bf.mmd1_reg_src_uphy_pll_vco_temp_cmp; - return ret; -} - -sw_error_t -hppe_uniphy_pll_control_vco_related_selection_mmd1_reg_src_uphy_pll_vco_temp_cmp_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - union uniphy_pll_control_vco_related_selection_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_uniphy_pll_control_vco_related_selection_get(dev_id, index, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.mmd1_reg_src_uphy_pll_vco_temp_cmp = value; - ret = hppe_uniphy_pll_control_vco_related_selection_set(dev_id, index, ®_val); - return ret; -} - -sw_error_t -hppe_uniphy_pll_control_vco_related_selection_mmd1_reg_src_uphy_pll_lpf_c2_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union uniphy_pll_control_vco_related_selection_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_uniphy_pll_control_vco_related_selection_get(dev_id, index, ®_val); - *value = reg_val.bf.mmd1_reg_src_uphy_pll_lpf_c2; - return ret; -} - -sw_error_t -hppe_uniphy_pll_control_vco_related_selection_mmd1_reg_src_uphy_pll_lpf_c2_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - union uniphy_pll_control_vco_related_selection_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_uniphy_pll_control_vco_related_selection_get(dev_id, index, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.mmd1_reg_src_uphy_pll_lpf_c2 = value; - ret = hppe_uniphy_pll_control_vco_related_selection_set(dev_id, index, ®_val); - return ret; -} - -sw_error_t -hppe_uniphy_pll_control_vco_related_selection_mmd1_reg_src_uphy_pll_vco_amp_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union uniphy_pll_control_vco_related_selection_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_uniphy_pll_control_vco_related_selection_get(dev_id, index, ®_val); - *value = reg_val.bf.mmd1_reg_src_uphy_pll_vco_amp; - return ret; -} - -sw_error_t -hppe_uniphy_pll_control_vco_related_selection_mmd1_reg_src_uphy_pll_vco_amp_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - union uniphy_pll_control_vco_related_selection_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_uniphy_pll_control_vco_related_selection_get(dev_id, index, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.mmd1_reg_src_uphy_pll_vco_amp = value; - ret = hppe_uniphy_pll_control_vco_related_selection_set(dev_id, index, ®_val); - return ret; -} - -sw_error_t -hppe_uniphy_pll_control_vco_related_selection_mmd1_reg_src_uphy_pll_lpf_dc_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union uniphy_pll_control_vco_related_selection_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_uniphy_pll_control_vco_related_selection_get(dev_id, index, ®_val); - *value = reg_val.bf.mmd1_reg_src_uphy_pll_lpf_dc; - return ret; -} - -sw_error_t -hppe_uniphy_pll_control_vco_related_selection_mmd1_reg_src_uphy_pll_lpf_dc_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - union uniphy_pll_control_vco_related_selection_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_uniphy_pll_control_vco_related_selection_get(dev_id, index, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.mmd1_reg_src_uphy_pll_lpf_dc = value; - ret = hppe_uniphy_pll_control_vco_related_selection_set(dev_id, index, ®_val); - return ret; -} - -sw_error_t -hppe_uniphy_pll_control_vco_related_selection_mmd1_reg_src_uphy_pll_cp_sel_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union uniphy_pll_control_vco_related_selection_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_uniphy_pll_control_vco_related_selection_get(dev_id, index, ®_val); - *value = reg_val.bf.mmd1_reg_src_uphy_pll_cp_sel; - return ret; -} - -sw_error_t -hppe_uniphy_pll_control_vco_related_selection_mmd1_reg_src_uphy_pll_cp_sel_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - union uniphy_pll_control_vco_related_selection_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_uniphy_pll_control_vco_related_selection_get(dev_id, index, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.mmd1_reg_src_uphy_pll_cp_sel = value; - ret = hppe_uniphy_pll_control_vco_related_selection_set(dev_id, index, ®_val); - return ret; -} - -sw_error_t -hppe_uniphy_pll_control_vco_related_selection_mmd1_reg_src_uphy_pll_lpf_res_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union uniphy_pll_control_vco_related_selection_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_uniphy_pll_control_vco_related_selection_get(dev_id, index, ®_val); - *value = reg_val.bf.mmd1_reg_src_uphy_pll_lpf_res; - return ret; -} - -sw_error_t -hppe_uniphy_pll_control_vco_related_selection_mmd1_reg_src_uphy_pll_lpf_res_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - union uniphy_pll_control_vco_related_selection_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_uniphy_pll_control_vco_related_selection_get(dev_id, index, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.mmd1_reg_src_uphy_pll_lpf_res = value; - ret = hppe_uniphy_pll_control_vco_related_selection_set(dev_id, index, ®_val); - return ret; -} - -sw_error_t -hppe_uniphy_tx_ac_jtag_mux_driver_selection_mmd1_reg_src_uphy_tx_vcm_delta_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union uniphy_tx_ac_jtag_mux_driver_selection_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_uniphy_tx_ac_jtag_mux_driver_selection_get(dev_id, index, ®_val); - *value = reg_val.bf.mmd1_reg_src_uphy_tx_vcm_delta; - return ret; -} - -sw_error_t -hppe_uniphy_tx_ac_jtag_mux_driver_selection_mmd1_reg_src_uphy_tx_vcm_delta_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - union uniphy_tx_ac_jtag_mux_driver_selection_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_uniphy_tx_ac_jtag_mux_driver_selection_get(dev_id, index, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.mmd1_reg_src_uphy_tx_vcm_delta = value; - ret = hppe_uniphy_tx_ac_jtag_mux_driver_selection_set(dev_id, index, ®_val); - return ret; -} - -sw_error_t -hppe_uniphy_tx_ac_jtag_mux_driver_selection_mmd1_reg_src_uphy_tx_emp_lsb_en_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union uniphy_tx_ac_jtag_mux_driver_selection_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_uniphy_tx_ac_jtag_mux_driver_selection_get(dev_id, index, ®_val); - *value = reg_val.bf.mmd1_reg_src_uphy_tx_emp_lsb_en; - return ret; -} - -sw_error_t -hppe_uniphy_tx_ac_jtag_mux_driver_selection_mmd1_reg_src_uphy_tx_emp_lsb_en_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - union uniphy_tx_ac_jtag_mux_driver_selection_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_uniphy_tx_ac_jtag_mux_driver_selection_get(dev_id, index, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.mmd1_reg_src_uphy_tx_emp_lsb_en = value; - ret = hppe_uniphy_tx_ac_jtag_mux_driver_selection_set(dev_id, index, ®_val); - return ret; -} - -sw_error_t -hppe_uniphy_tx_ac_jtag_mux_driver_selection_mmd1_reg_src_uphy_tx_emp_lvl_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union uniphy_tx_ac_jtag_mux_driver_selection_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_uniphy_tx_ac_jtag_mux_driver_selection_get(dev_id, index, ®_val); - *value = reg_val.bf.mmd1_reg_src_uphy_tx_emp_lvl; - return ret; -} - -sw_error_t -hppe_uniphy_tx_ac_jtag_mux_driver_selection_mmd1_reg_src_uphy_tx_emp_lvl_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - union uniphy_tx_ac_jtag_mux_driver_selection_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_uniphy_tx_ac_jtag_mux_driver_selection_get(dev_id, index, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.mmd1_reg_src_uphy_tx_emp_lvl = value; - ret = hppe_uniphy_tx_ac_jtag_mux_driver_selection_set(dev_id, index, ®_val); - return ret; -} - -sw_error_t -hppe_uniphy_tx_ac_jtag_mux_driver_selection_mmd1_reg_src_uphy_tx_acjtag_beacon_en_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union uniphy_tx_ac_jtag_mux_driver_selection_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_uniphy_tx_ac_jtag_mux_driver_selection_get(dev_id, index, ®_val); - *value = reg_val.bf.mmd1_reg_src_uphy_tx_acjtag_beacon_en; - return ret; -} - -sw_error_t -hppe_uniphy_tx_ac_jtag_mux_driver_selection_mmd1_reg_src_uphy_tx_acjtag_beacon_en_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - union uniphy_tx_ac_jtag_mux_driver_selection_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_uniphy_tx_ac_jtag_mux_driver_selection_get(dev_id, index, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.mmd1_reg_src_uphy_tx_acjtag_beacon_en = value; - ret = hppe_uniphy_tx_ac_jtag_mux_driver_selection_set(dev_id, index, ®_val); - return ret; -} - -sw_error_t -hppe_uniphy_tx_ac_jtag_mux_driver_selection_mmd1_reg_src_uphy_tx_en_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union uniphy_tx_ac_jtag_mux_driver_selection_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_uniphy_tx_ac_jtag_mux_driver_selection_get(dev_id, index, ®_val); - *value = reg_val.bf.mmd1_reg_src_uphy_tx_en; - return ret; -} - -sw_error_t -hppe_uniphy_tx_ac_jtag_mux_driver_selection_mmd1_reg_src_uphy_tx_en_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - union uniphy_tx_ac_jtag_mux_driver_selection_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_uniphy_tx_ac_jtag_mux_driver_selection_get(dev_id, index, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.mmd1_reg_src_uphy_tx_en = value; - ret = hppe_uniphy_tx_ac_jtag_mux_driver_selection_set(dev_id, index, ®_val); - return ret; -} - -sw_error_t -hppe_uniphy_tx_ac_jtag_mux_driver_selection_mmd1_reg_src_uphy_txd_bit_width_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union uniphy_tx_ac_jtag_mux_driver_selection_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_uniphy_tx_ac_jtag_mux_driver_selection_get(dev_id, index, ®_val); - *value = reg_val.bf.mmd1_reg_src_uphy_txd_bit_width; - return ret; -} - -sw_error_t -hppe_uniphy_tx_ac_jtag_mux_driver_selection_mmd1_reg_src_uphy_txd_bit_width_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - union uniphy_tx_ac_jtag_mux_driver_selection_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_uniphy_tx_ac_jtag_mux_driver_selection_get(dev_id, index, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.mmd1_reg_src_uphy_txd_bit_width = value; - ret = hppe_uniphy_tx_ac_jtag_mux_driver_selection_set(dev_id, index, ®_val); - return ret; -} - -sw_error_t -hppe_uniphy_tx_ac_jtag_mux_driver_selection_mmd1_reg_src_uphy_tx_rescal_code_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union uniphy_tx_ac_jtag_mux_driver_selection_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_uniphy_tx_ac_jtag_mux_driver_selection_get(dev_id, index, ®_val); - *value = reg_val.bf.mmd1_reg_src_uphy_tx_rescal_code; - return ret; -} - -sw_error_t -hppe_uniphy_tx_ac_jtag_mux_driver_selection_mmd1_reg_src_uphy_tx_rescal_code_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - union uniphy_tx_ac_jtag_mux_driver_selection_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_uniphy_tx_ac_jtag_mux_driver_selection_get(dev_id, index, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.mmd1_reg_src_uphy_tx_rescal_code = value; - ret = hppe_uniphy_tx_ac_jtag_mux_driver_selection_set(dev_id, index, ®_val); - return ret; -} - -sw_error_t -hppe_uniphy_tx_ac_jtag_mux_driver_selection_mmd1_reg_src_uphy_tx_amp_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union uniphy_tx_ac_jtag_mux_driver_selection_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_uniphy_tx_ac_jtag_mux_driver_selection_get(dev_id, index, ®_val); - *value = reg_val.bf.mmd1_reg_src_uphy_tx_amp; - return ret; -} - -sw_error_t -hppe_uniphy_tx_ac_jtag_mux_driver_selection_mmd1_reg_src_uphy_tx_amp_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - union uniphy_tx_ac_jtag_mux_driver_selection_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_uniphy_tx_ac_jtag_mux_driver_selection_get(dev_id, index, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.mmd1_reg_src_uphy_tx_amp = value; - ret = hppe_uniphy_tx_ac_jtag_mux_driver_selection_set(dev_id, index, ®_val); - return ret; -} - -sw_error_t -hppe_uniphy_resistor_calibration_1_mmd1_reg_disable_load_res_txrx_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union uniphy_resistor_calibration_1_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_uniphy_resistor_calibration_1_get(dev_id, index, ®_val); - *value = reg_val.bf.mmd1_reg_disable_load_res_txrx; - return ret; -} - -sw_error_t -hppe_uniphy_resistor_calibration_1_mmd1_reg_disable_load_res_txrx_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - union uniphy_resistor_calibration_1_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_uniphy_resistor_calibration_1_get(dev_id, index, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.mmd1_reg_disable_load_res_txrx = value; - ret = hppe_uniphy_resistor_calibration_1_set(dev_id, index, ®_val); - return ret; -} - -sw_error_t -hppe_uniphy_resistor_calibration_1_mmd1_reg_calib_tx_reg_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union uniphy_resistor_calibration_1_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_uniphy_resistor_calibration_1_get(dev_id, index, ®_val); - *value = reg_val.bf.mmd1_reg_calib_tx_reg; - return ret; -} - -sw_error_t -hppe_uniphy_resistor_calibration_1_mmd1_reg_calib_tx_reg_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - union uniphy_resistor_calibration_1_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_uniphy_resistor_calibration_1_get(dev_id, index, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.mmd1_reg_calib_tx_reg = value; - ret = hppe_uniphy_resistor_calibration_1_set(dev_id, index, ®_val); - return ret; -} - -sw_error_t -hppe_uniphy_resistor_calibration_1_mmd1_reg_calib_rx_reg_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union uniphy_resistor_calibration_1_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_uniphy_resistor_calibration_1_get(dev_id, index, ®_val); - *value = reg_val.bf.mmd1_reg_calib_rx_reg; - return ret; -} - -sw_error_t -hppe_uniphy_resistor_calibration_1_mmd1_reg_calib_rx_reg_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - union uniphy_resistor_calibration_1_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_uniphy_resistor_calibration_1_get(dev_id, index, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.mmd1_reg_calib_rx_reg = value; - ret = hppe_uniphy_resistor_calibration_1_set(dev_id, index, ®_val); - return ret; -} - -sw_error_t -hppe_uniphy_resistor_calibration_1_mmd1_reg_vref_lvl_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union uniphy_resistor_calibration_1_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_uniphy_resistor_calibration_1_get(dev_id, index, ®_val); - *value = reg_val.bf.mmd1_reg_vref_lvl; - return ret; -} - -sw_error_t -hppe_uniphy_resistor_calibration_1_mmd1_reg_vref_lvl_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - union uniphy_resistor_calibration_1_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_uniphy_resistor_calibration_1_get(dev_id, index, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.mmd1_reg_vref_lvl = value; - ret = hppe_uniphy_resistor_calibration_1_set(dev_id, index, ®_val); - return ret; -} - -sw_error_t -hppe_uniphy_pll_vco_related_control_1_miireg_uphy_pll_lckdt_en_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union uniphy_pll_vco_related_control_1_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_uniphy_pll_vco_related_control_1_get(dev_id, index, ®_val); - *value = reg_val.bf.miireg_uphy_pll_lckdt_en; - return ret; -} - -sw_error_t -hppe_uniphy_pll_vco_related_control_1_miireg_uphy_pll_lckdt_en_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - union uniphy_pll_vco_related_control_1_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_uniphy_pll_vco_related_control_1_get(dev_id, index, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.miireg_uphy_pll_lckdt_en = value; - ret = hppe_uniphy_pll_vco_related_control_1_set(dev_id, index, ®_val); - return ret; -} - -sw_error_t -hppe_uniphy_pll_vco_related_control_1_miireg_autoload_sel_pll_vco_calib_ready_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union uniphy_pll_vco_related_control_1_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_uniphy_pll_vco_related_control_1_get(dev_id, index, ®_val); - *value = reg_val.bf.miireg_autoload_sel_pll_vco_calib_ready; - return ret; -} - -sw_error_t -hppe_uniphy_pll_vco_related_control_1_miireg_autoload_sel_pll_vco_calib_ready_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - union uniphy_pll_vco_related_control_1_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_uniphy_pll_vco_related_control_1_get(dev_id, index, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.miireg_autoload_sel_pll_vco_calib_ready = value; - ret = hppe_uniphy_pll_vco_related_control_1_set(dev_id, index, ®_val); - return ret; -} - -sw_error_t -hppe_uniphy_pll_vco_related_control_1_miireg_reg_uphy_pll_vco_calib_ready_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union uniphy_pll_vco_related_control_1_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_uniphy_pll_vco_related_control_1_get(dev_id, index, ®_val); - *value = reg_val.bf.miireg_reg_uphy_pll_vco_calib_ready; - return ret; -} - -sw_error_t -hppe_uniphy_pll_vco_related_control_1_miireg_reg_uphy_pll_vco_calib_ready_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - union uniphy_pll_vco_related_control_1_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_uniphy_pll_vco_related_control_1_get(dev_id, index, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.miireg_reg_uphy_pll_vco_calib_ready = value; - ret = hppe_uniphy_pll_vco_related_control_1_set(dev_id, index, ®_val); - return ret; -} - -sw_error_t -hppe_uniphy_pll_vco_related_control_1_miireg_reg_uphy_pll_vco_temp_cmp_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union uniphy_pll_vco_related_control_1_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_uniphy_pll_vco_related_control_1_get(dev_id, index, ®_val); - *value = reg_val.bf.miireg_reg_uphy_pll_vco_temp_cmp; - return ret; -} - -sw_error_t -hppe_uniphy_pll_vco_related_control_1_miireg_reg_uphy_pll_vco_temp_cmp_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - union uniphy_pll_vco_related_control_1_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_uniphy_pll_vco_related_control_1_get(dev_id, index, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.miireg_reg_uphy_pll_vco_temp_cmp = value; - ret = hppe_uniphy_pll_vco_related_control_1_set(dev_id, index, ®_val); - return ret; -} - -sw_error_t -hppe_uniphy_pll_vco_related_control_1_miireg_reg_uphy_pll_vco_amp_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union uniphy_pll_vco_related_control_1_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_uniphy_pll_vco_related_control_1_get(dev_id, index, ®_val); - *value = reg_val.bf.miireg_reg_uphy_pll_vco_amp; - return ret; -} - -sw_error_t -hppe_uniphy_pll_vco_related_control_1_miireg_reg_uphy_pll_vco_amp_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - union uniphy_pll_vco_related_control_1_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_uniphy_pll_vco_related_control_1_get(dev_id, index, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.miireg_reg_uphy_pll_vco_amp = value; - ret = hppe_uniphy_pll_vco_related_control_1_set(dev_id, index, ®_val); - return ret; -} - -sw_error_t -hppe_uniphy_pll_vco_related_control_1_miireg_reg_uphy_pll_vco_gain_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union uniphy_pll_vco_related_control_1_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_uniphy_pll_vco_related_control_1_get(dev_id, index, ®_val); - *value = reg_val.bf.miireg_reg_uphy_pll_vco_gain; - return ret; -} - -sw_error_t -hppe_uniphy_pll_vco_related_control_1_miireg_reg_uphy_pll_vco_gain_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - union uniphy_pll_vco_related_control_1_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_uniphy_pll_vco_related_control_1_get(dev_id, index, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.miireg_reg_uphy_pll_vco_gain = value; - ret = hppe_uniphy_pll_vco_related_control_1_set(dev_id, index, ®_val); - return ret; -} - -sw_error_t -hppe_uniphy_rx_afe_2_miireg_reg_uphy_rx_afe_res1_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union uniphy_rx_afe_2_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_uniphy_rx_afe_2_get(dev_id, index, ®_val); - *value = reg_val.bf.miireg_reg_uphy_rx_afe_res1; - return ret; -} - -sw_error_t -hppe_uniphy_rx_afe_2_miireg_reg_uphy_rx_afe_res1_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - union uniphy_rx_afe_2_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_uniphy_rx_afe_2_get(dev_id, index, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.miireg_reg_uphy_rx_afe_res1 = value; - ret = hppe_uniphy_rx_afe_2_set(dev_id, index, ®_val); - return ret; -} - -sw_error_t -hppe_uniphy_rx_afe_2_miireg_reg_uphy_rx_afe_cap1_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union uniphy_rx_afe_2_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_uniphy_rx_afe_2_get(dev_id, index, ®_val); - *value = reg_val.bf.miireg_reg_uphy_rx_afe_cap1; - return ret; -} - -sw_error_t -hppe_uniphy_rx_afe_2_miireg_reg_uphy_rx_afe_cap1_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - union uniphy_rx_afe_2_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_uniphy_rx_afe_2_get(dev_id, index, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.miireg_reg_uphy_rx_afe_cap1 = value; - ret = hppe_uniphy_rx_afe_2_set(dev_id, index, ®_val); - return ret; -} - -sw_error_t -hppe_uniphy_rx_afe_2_miireg_reg_uphy_rx_rescal_code_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union uniphy_rx_afe_2_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_uniphy_rx_afe_2_get(dev_id, index, ®_val); - *value = reg_val.bf.miireg_reg_uphy_rx_rescal_code; - return ret; -} - -sw_error_t -hppe_uniphy_rx_afe_2_miireg_reg_uphy_rx_rescal_code_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - union uniphy_rx_afe_2_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_uniphy_rx_afe_2_get(dev_id, index, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.miireg_reg_uphy_rx_rescal_code = value; - ret = hppe_uniphy_rx_afe_2_set(dev_id, index, ®_val); - return ret; -} - -sw_error_t -hppe_bandgap_ip_mbias_2_cmn_mmd1_reg_mbias_en_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union bandgap_ip_mbias_2_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_bandgap_ip_mbias_2_get(dev_id, index, ®_val); - *value = reg_val.bf.cmn_mmd1_reg_mbias_en; - return ret; -} - -sw_error_t -hppe_bandgap_ip_mbias_2_cmn_mmd1_reg_mbias_en_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - union bandgap_ip_mbias_2_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_bandgap_ip_mbias_2_get(dev_id, index, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.cmn_mmd1_reg_mbias_en = value; - ret = hppe_bandgap_ip_mbias_2_set(dev_id, index, ®_val); - return ret; -} - -sw_error_t -hppe_bandgap_ip_mbias_2_cmn_mmd1_reg_cmn_icc_rescode_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union bandgap_ip_mbias_2_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_bandgap_ip_mbias_2_get(dev_id, index, ®_val); - *value = reg_val.bf.cmn_mmd1_reg_cmn_icc_rescode; - return ret; -} - -sw_error_t -hppe_bandgap_ip_mbias_2_cmn_mmd1_reg_cmn_icc_rescode_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - union bandgap_ip_mbias_2_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_bandgap_ip_mbias_2_get(dev_id, index, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.cmn_mmd1_reg_cmn_icc_rescode = value; - ret = hppe_bandgap_ip_mbias_2_set(dev_id, index, ®_val); - return ret; -} - -sw_error_t -hppe_bandgap_ip_mbias_2_cmn_mmd1_reg_cmn_bg_rsv_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union bandgap_ip_mbias_2_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_bandgap_ip_mbias_2_get(dev_id, index, ®_val); - *value = reg_val.bf.cmn_mmd1_reg_cmn_bg_rsv; - return ret; -} - -sw_error_t -hppe_bandgap_ip_mbias_2_cmn_mmd1_reg_cmn_bg_rsv_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - union bandgap_ip_mbias_2_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_bandgap_ip_mbias_2_get(dev_id, index, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.cmn_mmd1_reg_cmn_bg_rsv = value; - ret = hppe_bandgap_ip_mbias_2_set(dev_id, index, ®_val); - return ret; -} - -sw_error_t -hppe_ldo_0p9v_related_1_cmn_mmd1_reg_cmn_ldo_ocp_en_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union ldo_0p9v_related_1_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_ldo_0p9v_related_1_get(dev_id, index, ®_val); - *value = reg_val.bf.cmn_mmd1_reg_cmn_ldo_ocp_en; - return ret; -} - -sw_error_t -hppe_ldo_0p9v_related_1_cmn_mmd1_reg_cmn_ldo_ocp_en_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - union ldo_0p9v_related_1_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_ldo_0p9v_related_1_get(dev_id, index, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.cmn_mmd1_reg_cmn_ldo_ocp_en = value; - ret = hppe_ldo_0p9v_related_1_set(dev_id, index, ®_val); - return ret; -} - -sw_error_t -hppe_ldo_0p9v_related_1_cmn_mmd1_reg_cmn_ldo_int_load_en_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union ldo_0p9v_related_1_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_ldo_0p9v_related_1_get(dev_id, index, ®_val); - *value = reg_val.bf.cmn_mmd1_reg_cmn_ldo_int_load_en; - return ret; -} - -sw_error_t -hppe_ldo_0p9v_related_1_cmn_mmd1_reg_cmn_ldo_int_load_en_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - union ldo_0p9v_related_1_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_ldo_0p9v_related_1_get(dev_id, index, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.cmn_mmd1_reg_cmn_ldo_int_load_en = value; - ret = hppe_ldo_0p9v_related_1_set(dev_id, index, ®_val); - return ret; -} - -sw_error_t -hppe_ldo_0p9v_related_1_cmn_mmd1_reg_cmn_ldo_int_res_ctrl_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union ldo_0p9v_related_1_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_ldo_0p9v_related_1_get(dev_id, index, ®_val); - *value = reg_val.bf.cmn_mmd1_reg_cmn_ldo_int_res_ctrl; - return ret; -} - -sw_error_t -hppe_ldo_0p9v_related_1_cmn_mmd1_reg_cmn_ldo_int_res_ctrl_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - union ldo_0p9v_related_1_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_ldo_0p9v_related_1_get(dev_id, index, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.cmn_mmd1_reg_cmn_ldo_int_res_ctrl = value; - ret = hppe_ldo_0p9v_related_1_set(dev_id, index, ®_val); - return ret; -} - -sw_error_t -hppe_ldo_0p9v_related_1_cmn_mmd1_reg_cmn_ldo_vout_ctrl_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union ldo_0p9v_related_1_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_ldo_0p9v_related_1_get(dev_id, index, ®_val); - *value = reg_val.bf.cmn_mmd1_reg_cmn_ldo_vout_ctrl; - return ret; -} - -sw_error_t -hppe_ldo_0p9v_related_1_cmn_mmd1_reg_cmn_ldo_vout_ctrl_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - union ldo_0p9v_related_1_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_ldo_0p9v_related_1_get(dev_id, index, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.cmn_mmd1_reg_cmn_ldo_vout_ctrl = value; - ret = hppe_ldo_0p9v_related_1_set(dev_id, index, ®_val); - return ret; -} - -sw_error_t -hppe_ldo_0p9v_related_1_cmn_mmd1_reg_cmn_ldo_ocp_current_sel_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union ldo_0p9v_related_1_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_ldo_0p9v_related_1_get(dev_id, index, ®_val); - *value = reg_val.bf.cmn_mmd1_reg_cmn_ldo_ocp_current_sel; - return ret; -} - -sw_error_t -hppe_ldo_0p9v_related_1_cmn_mmd1_reg_cmn_ldo_ocp_current_sel_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - union ldo_0p9v_related_1_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_ldo_0p9v_related_1_get(dev_id, index, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.cmn_mmd1_reg_cmn_ldo_ocp_current_sel = value; - ret = hppe_ldo_0p9v_related_1_set(dev_id, index, ®_val); - return ret; -} - -sw_error_t -hppe_ldo_0p9v_related_1_cmn_mmd1_reg_cmn_vtt_ldo_biasgen_sel_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union ldo_0p9v_related_1_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_ldo_0p9v_related_1_get(dev_id, index, ®_val); - *value = reg_val.bf.cmn_mmd1_reg_cmn_vtt_ldo_biasgen_sel; - return ret; -} - -sw_error_t -hppe_ldo_0p9v_related_1_cmn_mmd1_reg_cmn_vtt_ldo_biasgen_sel_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - union ldo_0p9v_related_1_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_ldo_0p9v_related_1_get(dev_id, index, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.cmn_mmd1_reg_cmn_vtt_ldo_biasgen_sel = value; - ret = hppe_ldo_0p9v_related_1_set(dev_id, index, ®_val); - return ret; -} - -sw_error_t -hppe_ldo_0p9v_related_1_cmn_mmd1_reg_cmn_ldo_en_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union ldo_0p9v_related_1_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_ldo_0p9v_related_1_get(dev_id, index, ®_val); - *value = reg_val.bf.cmn_mmd1_reg_cmn_ldo_en; - return ret; -} - -sw_error_t -hppe_ldo_0p9v_related_1_cmn_mmd1_reg_cmn_ldo_en_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - union ldo_0p9v_related_1_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_ldo_0p9v_related_1_get(dev_id, index, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.cmn_mmd1_reg_cmn_ldo_en = value; - ret = hppe_ldo_0p9v_related_1_set(dev_id, index, ®_val); - return ret; -} - -sw_error_t -hppe_ldo_0p9v_related_1_cmn_mmd1_reg_cmn_ldo_comp_current_en_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union ldo_0p9v_related_1_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_ldo_0p9v_related_1_get(dev_id, index, ®_val); - *value = reg_val.bf.cmn_mmd1_reg_cmn_ldo_comp_current_en; - return ret; -} - -sw_error_t -hppe_ldo_0p9v_related_1_cmn_mmd1_reg_cmn_ldo_comp_current_en_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - union ldo_0p9v_related_1_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_ldo_0p9v_related_1_get(dev_id, index, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.cmn_mmd1_reg_cmn_ldo_comp_current_en = value; - ret = hppe_ldo_0p9v_related_1_set(dev_id, index, ®_val); - return ret; -} - -sw_error_t -hppe_ldo_0p9v_related_1_cmn_mmd1_reg_cmn_ldo_bias_ctrl_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union ldo_0p9v_related_1_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_ldo_0p9v_related_1_get(dev_id, index, ®_val); - *value = reg_val.bf.cmn_mmd1_reg_cmn_ldo_bias_ctrl; - return ret; -} - -sw_error_t -hppe_ldo_0p9v_related_1_cmn_mmd1_reg_cmn_ldo_bias_ctrl_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - union ldo_0p9v_related_1_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_ldo_0p9v_related_1_get(dev_id, index, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.cmn_mmd1_reg_cmn_ldo_bias_ctrl = value; - ret = hppe_ldo_0p9v_related_1_set(dev_id, index, ®_val); - return ret; -} - -sw_error_t -hppe_otp_vtt_ldo_related_cmn_mmd1_reg_cmn_ana_isolation_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union otp_vtt_ldo_related_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_otp_vtt_ldo_related_get(dev_id, index, ®_val); - *value = reg_val.bf.cmn_mmd1_reg_cmn_ana_isolation; - return ret; -} - -sw_error_t -hppe_otp_vtt_ldo_related_cmn_mmd1_reg_cmn_ana_isolation_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - union otp_vtt_ldo_related_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_otp_vtt_ldo_related_get(dev_id, index, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.cmn_mmd1_reg_cmn_ana_isolation = value; - ret = hppe_otp_vtt_ldo_related_set(dev_id, index, ®_val); - return ret; -} - -sw_error_t -hppe_otp_vtt_ldo_related_cmn_mmd1_reg_cmn_vtt_ldo_ocp_en_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union otp_vtt_ldo_related_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_otp_vtt_ldo_related_get(dev_id, index, ®_val); - *value = reg_val.bf.cmn_mmd1_reg_cmn_vtt_ldo_ocp_en; - return ret; -} - -sw_error_t -hppe_otp_vtt_ldo_related_cmn_mmd1_reg_cmn_vtt_ldo_ocp_en_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - union otp_vtt_ldo_related_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_otp_vtt_ldo_related_get(dev_id, index, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.cmn_mmd1_reg_cmn_vtt_ldo_ocp_en = value; - ret = hppe_otp_vtt_ldo_related_set(dev_id, index, ®_val); - return ret; -} - -sw_error_t -hppe_otp_vtt_ldo_related_cmn_mmd1_reg_cmn_vtt_ldo_en_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union otp_vtt_ldo_related_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_otp_vtt_ldo_related_get(dev_id, index, ®_val); - *value = reg_val.bf.cmn_mmd1_reg_cmn_vtt_ldo_en; - return ret; -} - -sw_error_t -hppe_otp_vtt_ldo_related_cmn_mmd1_reg_cmn_vtt_ldo_en_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - union otp_vtt_ldo_related_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_otp_vtt_ldo_related_get(dev_id, index, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.cmn_mmd1_reg_cmn_vtt_ldo_en = value; - ret = hppe_otp_vtt_ldo_related_set(dev_id, index, ®_val); - return ret; -} - -sw_error_t -hppe_otp_vtt_ldo_related_cmn_mmd1_reg_cmn_vtt_ldo_bias_ctrl_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union otp_vtt_ldo_related_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_otp_vtt_ldo_related_get(dev_id, index, ®_val); - *value = reg_val.bf.cmn_mmd1_reg_cmn_vtt_ldo_bias_ctrl; - return ret; -} - -sw_error_t -hppe_otp_vtt_ldo_related_cmn_mmd1_reg_cmn_vtt_ldo_bias_ctrl_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - union otp_vtt_ldo_related_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_otp_vtt_ldo_related_get(dev_id, index, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.cmn_mmd1_reg_cmn_vtt_ldo_bias_ctrl = value; - ret = hppe_otp_vtt_ldo_related_set(dev_id, index, ®_val); - return ret; -} - -sw_error_t -hppe_otp_vtt_ldo_related_cmn_mmd1_reg_cmn_vtt_ldo_rsv_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union otp_vtt_ldo_related_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_otp_vtt_ldo_related_get(dev_id, index, ®_val); - *value = reg_val.bf.cmn_mmd1_reg_cmn_vtt_ldo_rsv; - return ret; -} - -sw_error_t -hppe_otp_vtt_ldo_related_cmn_mmd1_reg_cmn_vtt_ldo_rsv_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - union otp_vtt_ldo_related_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_otp_vtt_ldo_related_get(dev_id, index, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.cmn_mmd1_reg_cmn_vtt_ldo_rsv = value; - ret = hppe_otp_vtt_ldo_related_set(dev_id, index, ®_val); - return ret; -} - -sw_error_t -hppe_otp_vtt_ldo_related_cmn_mmd1_reg_cmn_vtt_ldo_ocp_current_sel_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union otp_vtt_ldo_related_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_otp_vtt_ldo_related_get(dev_id, index, ®_val); - *value = reg_val.bf.cmn_mmd1_reg_cmn_vtt_ldo_ocp_current_sel; - return ret; -} - -sw_error_t -hppe_otp_vtt_ldo_related_cmn_mmd1_reg_cmn_vtt_ldo_ocp_current_sel_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - union otp_vtt_ldo_related_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_otp_vtt_ldo_related_get(dev_id, index, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.cmn_mmd1_reg_cmn_vtt_ldo_ocp_current_sel = value; - ret = hppe_otp_vtt_ldo_related_set(dev_id, index, ®_val); - return ret; -} - -sw_error_t -hppe_otp_vtt_ldo_related_cmn_mmd1_reg_cmn_vtt_ldo_int_load_ctrl_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union otp_vtt_ldo_related_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_otp_vtt_ldo_related_get(dev_id, index, ®_val); - *value = reg_val.bf.cmn_mmd1_reg_cmn_vtt_ldo_int_load_ctrl; - return ret; -} - -sw_error_t -hppe_otp_vtt_ldo_related_cmn_mmd1_reg_cmn_vtt_ldo_int_load_ctrl_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - union otp_vtt_ldo_related_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_otp_vtt_ldo_related_get(dev_id, index, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.cmn_mmd1_reg_cmn_vtt_ldo_int_load_ctrl = value; - ret = hppe_otp_vtt_ldo_related_set(dev_id, index, ®_val); - return ret; -} - -sw_error_t -hppe_otp_temperature_compensate_1_cmn_mmd1_reg_uphy_ictat100u_en_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union otp_temperature_compensate_1_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_otp_temperature_compensate_1_get(dev_id, index, ®_val); - *value = reg_val.bf.cmn_mmd1_reg_uphy_ictat100u_en; - return ret; -} - -sw_error_t -hppe_otp_temperature_compensate_1_cmn_mmd1_reg_uphy_ictat100u_en_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - union otp_temperature_compensate_1_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_otp_temperature_compensate_1_get(dev_id, index, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.cmn_mmd1_reg_uphy_ictat100u_en = value; - ret = hppe_otp_temperature_compensate_1_set(dev_id, index, ®_val); - return ret; -} - -sw_error_t -hppe_otp_temperature_compensate_1_cmn_mmd1_reg_cmn_pll_ictat100u_en_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union otp_temperature_compensate_1_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_otp_temperature_compensate_1_get(dev_id, index, ®_val); - *value = reg_val.bf.cmn_mmd1_reg_cmn_pll_ictat100u_en; - return ret; -} - -sw_error_t -hppe_otp_temperature_compensate_1_cmn_mmd1_reg_cmn_pll_ictat100u_en_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - union otp_temperature_compensate_1_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_otp_temperature_compensate_1_get(dev_id, index, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.cmn_mmd1_reg_cmn_pll_ictat100u_en = value; - ret = hppe_otp_temperature_compensate_1_set(dev_id, index, ®_val); - return ret; -} - -sw_error_t -hppe_otp_temperature_compensate_1_cmn_mmd1_reg_uphy_ictat100u_ctrl1_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union otp_temperature_compensate_1_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_otp_temperature_compensate_1_get(dev_id, index, ®_val); - *value = reg_val.bf.cmn_mmd1_reg_uphy_ictat100u_ctrl1; - return ret; -} - -sw_error_t -hppe_otp_temperature_compensate_1_cmn_mmd1_reg_uphy_ictat100u_ctrl1_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - union otp_temperature_compensate_1_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_otp_temperature_compensate_1_get(dev_id, index, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.cmn_mmd1_reg_uphy_ictat100u_ctrl1 = value; - ret = hppe_otp_temperature_compensate_1_set(dev_id, index, ®_val); - return ret; -} - -sw_error_t -hppe_otp_temperature_compensate_1_cmn_mmd1_reg_uphy_ictat100u_ctrl2_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union otp_temperature_compensate_1_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_otp_temperature_compensate_1_get(dev_id, index, ®_val); - *value = reg_val.bf.cmn_mmd1_reg_uphy_ictat100u_ctrl2; - return ret; -} - -sw_error_t -hppe_otp_temperature_compensate_1_cmn_mmd1_reg_uphy_ictat100u_ctrl2_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - union otp_temperature_compensate_1_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_otp_temperature_compensate_1_get(dev_id, index, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.cmn_mmd1_reg_uphy_ictat100u_ctrl2 = value; - ret = hppe_otp_temperature_compensate_1_set(dev_id, index, ®_val); - return ret; -} - -sw_error_t -hppe_otp_temperature_compensate_1_cmn_mmd1_reg_uphy_ictat100u_ctrl0_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union otp_temperature_compensate_1_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_otp_temperature_compensate_1_get(dev_id, index, ®_val); - *value = reg_val.bf.cmn_mmd1_reg_uphy_ictat100u_ctrl0; - return ret; -} - -sw_error_t -hppe_otp_temperature_compensate_1_cmn_mmd1_reg_uphy_ictat100u_ctrl0_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - union otp_temperature_compensate_1_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_otp_temperature_compensate_1_get(dev_id, index, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.cmn_mmd1_reg_uphy_ictat100u_ctrl0 = value; - ret = hppe_otp_temperature_compensate_1_set(dev_id, index, ®_val); - return ret; -} - -sw_error_t -hppe_pll_vco_related_control_1_cmn_mii_reg_reg_cmn_pll_vco_calib_ready_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union pll_vco_related_control_1_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_pll_vco_related_control_1_get(dev_id, index, ®_val); - *value = reg_val.bf.cmn_mii_reg_reg_cmn_pll_vco_calib_ready; - return ret; -} - -sw_error_t -hppe_pll_vco_related_control_1_cmn_mii_reg_reg_cmn_pll_vco_calib_ready_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - union pll_vco_related_control_1_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_pll_vco_related_control_1_get(dev_id, index, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.cmn_mii_reg_reg_cmn_pll_vco_calib_ready = value; - ret = hppe_pll_vco_related_control_1_set(dev_id, index, ®_val); - return ret; -} - -sw_error_t -hppe_pll_vco_related_control_1_cmn_mii_reg_reg_cmn_pll_vco_temp_cmp_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union pll_vco_related_control_1_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_pll_vco_related_control_1_get(dev_id, index, ®_val); - *value = reg_val.bf.cmn_mii_reg_reg_cmn_pll_vco_temp_cmp; - return ret; -} - -sw_error_t -hppe_pll_vco_related_control_1_cmn_mii_reg_reg_cmn_pll_vco_temp_cmp_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - union pll_vco_related_control_1_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_pll_vco_related_control_1_get(dev_id, index, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.cmn_mii_reg_reg_cmn_pll_vco_temp_cmp = value; - ret = hppe_pll_vco_related_control_1_set(dev_id, index, ®_val); - return ret; -} - -sw_error_t -hppe_pll_vco_related_control_1_cmn_mii_reg_cmn_pll_lckdt_en_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union pll_vco_related_control_1_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_pll_vco_related_control_1_get(dev_id, index, ®_val); - *value = reg_val.bf.cmn_mii_reg_cmn_pll_lckdt_en; - return ret; -} - -sw_error_t -hppe_pll_vco_related_control_1_cmn_mii_reg_cmn_pll_lckdt_en_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - union pll_vco_related_control_1_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_pll_vco_related_control_1_get(dev_id, index, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.cmn_mii_reg_cmn_pll_lckdt_en = value; - ret = hppe_pll_vco_related_control_1_set(dev_id, index, ®_val); - return ret; -} - -sw_error_t -hppe_pll_vco_related_control_1_cmn_mii_reg_reg_cmn_pll_vco_amp_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union pll_vco_related_control_1_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_pll_vco_related_control_1_get(dev_id, index, ®_val); - *value = reg_val.bf.cmn_mii_reg_reg_cmn_pll_vco_amp; - return ret; -} - -sw_error_t -hppe_pll_vco_related_control_1_cmn_mii_reg_reg_cmn_pll_vco_amp_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - union pll_vco_related_control_1_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_pll_vco_related_control_1_get(dev_id, index, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.cmn_mii_reg_reg_cmn_pll_vco_amp = value; - ret = hppe_pll_vco_related_control_1_set(dev_id, index, ®_val); - return ret; -} - -sw_error_t -hppe_pll_vco_related_control_1_cmn_mii_reg_autoload_sel_pll_vco_calib_ready_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union pll_vco_related_control_1_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_pll_vco_related_control_1_get(dev_id, index, ®_val); - *value = reg_val.bf.cmn_mii_reg_autoload_sel_pll_vco_calib_ready; - return ret; -} - -sw_error_t -hppe_pll_vco_related_control_1_cmn_mii_reg_autoload_sel_pll_vco_calib_ready_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - union pll_vco_related_control_1_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_pll_vco_related_control_1_get(dev_id, index, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.cmn_mii_reg_autoload_sel_pll_vco_calib_ready = value; - ret = hppe_pll_vco_related_control_1_set(dev_id, index, ®_val); - return ret; -} - -sw_error_t -hppe_pll_control_vco_related_selection_2_cmn_mmd1_reg_src_cmn_pll_vco_calib_ready_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union pll_control_vco_related_selection_2_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_pll_control_vco_related_selection_2_get(dev_id, index, ®_val); - *value = reg_val.bf.cmn_mmd1_reg_src_cmn_pll_vco_calib_ready; - return ret; -} - -sw_error_t -hppe_pll_control_vco_related_selection_2_cmn_mmd1_reg_src_cmn_pll_vco_calib_ready_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - union pll_control_vco_related_selection_2_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_pll_control_vco_related_selection_2_get(dev_id, index, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.cmn_mmd1_reg_src_cmn_pll_vco_calib_ready = value; - ret = hppe_pll_control_vco_related_selection_2_set(dev_id, index, ®_val); - return ret; -} - -sw_error_t -hppe_pll_control_vco_related_selection_2_cmn_mmd1_reg_src_cmn_pll_vco_temp_cmp_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union pll_control_vco_related_selection_2_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_pll_control_vco_related_selection_2_get(dev_id, index, ®_val); - *value = reg_val.bf.cmn_mmd1_reg_src_cmn_pll_vco_temp_cmp; - return ret; -} - -sw_error_t -hppe_pll_control_vco_related_selection_2_cmn_mmd1_reg_src_cmn_pll_vco_temp_cmp_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - union pll_control_vco_related_selection_2_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_pll_control_vco_related_selection_2_get(dev_id, index, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.cmn_mmd1_reg_src_cmn_pll_vco_temp_cmp = value; - ret = hppe_pll_control_vco_related_selection_2_set(dev_id, index, ®_val); - return ret; -} - -sw_error_t -hppe_pll_control_vco_related_selection_2_cmn_mmd1_reg_src_cmn_pll_vco_amp_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union pll_control_vco_related_selection_2_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_pll_control_vco_related_selection_2_get(dev_id, index, ®_val); - *value = reg_val.bf.cmn_mmd1_reg_src_cmn_pll_vco_amp; - return ret; -} - -sw_error_t -hppe_pll_control_vco_related_selection_2_cmn_mmd1_reg_src_cmn_pll_vco_amp_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - union pll_control_vco_related_selection_2_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_pll_control_vco_related_selection_2_get(dev_id, index, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.cmn_mmd1_reg_src_cmn_pll_vco_amp = value; - ret = hppe_pll_control_vco_related_selection_2_set(dev_id, index, ®_val); - return ret; -} - -sw_error_t -hppe_pll_control_vco_related_selection_2_cmn_mmd1_reg_src_cmn_pll_vco_calib_start_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union pll_control_vco_related_selection_2_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_pll_control_vco_related_selection_2_get(dev_id, index, ®_val); - *value = reg_val.bf.cmn_mmd1_reg_src_cmn_pll_vco_calib_start; - return ret; -} - -sw_error_t -hppe_pll_control_vco_related_selection_2_cmn_mmd1_reg_src_cmn_pll_vco_calib_start_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - union pll_control_vco_related_selection_2_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_pll_control_vco_related_selection_2_get(dev_id, index, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.cmn_mmd1_reg_src_cmn_pll_vco_calib_start = value; - ret = hppe_pll_control_vco_related_selection_2_set(dev_id, index, ®_val); - return ret; -} - -sw_error_t -hppe_pll_control_vco_related_selection_2_cmn_mmd1_reg_src_cmn_pll_vco_calib_code_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union pll_control_vco_related_selection_2_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_pll_control_vco_related_selection_2_get(dev_id, index, ®_val); - *value = reg_val.bf.cmn_mmd1_reg_src_cmn_pll_vco_calib_code; - return ret; -} - -sw_error_t -hppe_pll_control_vco_related_selection_2_cmn_mmd1_reg_src_cmn_pll_vco_calib_code_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - union pll_control_vco_related_selection_2_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_pll_control_vco_related_selection_2_get(dev_id, index, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.cmn_mmd1_reg_src_cmn_pll_vco_calib_code = value; - ret = hppe_pll_control_vco_related_selection_2_set(dev_id, index, ®_val); - return ret; -} - -sw_error_t -hppe_pll_control_vco_related_selection_2_cmn_mmd1_reg_src_cmn_pll_fbclk_div_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union pll_control_vco_related_selection_2_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_pll_control_vco_related_selection_2_get(dev_id, index, ®_val); - *value = reg_val.bf.cmn_mmd1_reg_src_cmn_pll_fbclk_div; - return ret; -} - -sw_error_t -hppe_pll_control_vco_related_selection_2_cmn_mmd1_reg_src_cmn_pll_fbclk_div_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - union pll_control_vco_related_selection_2_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_pll_control_vco_related_selection_2_get(dev_id, index, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.cmn_mmd1_reg_src_cmn_pll_fbclk_div = value; - ret = hppe_pll_control_vco_related_selection_2_set(dev_id, index, ®_val); - return ret; -} -#endif - -sw_error_t -hppe_uniphy_phy_mode_ctrl_get( - a_uint32_t dev_id, - a_uint32_t index, - union uniphy_misc2_phy_mode_u *value) -{ - if (index >= UNIPHY_MISC2_PHY_MODE_MAX_ENTRY) - return SW_OUT_OF_RANGE; - return hppe_uniphy_reg_get( - dev_id, - NSS_UNIPHY_BASE_ADDR + UNIPHY_MISC2_PHY_MODE_ADDRESS, - index * UNIPHY_MISC2_PHY_MODE_INC, - &value->val); -} - -sw_error_t -hppe_uniphy_phy_mode_ctrl_set( - a_uint32_t dev_id, - a_uint32_t index, - union uniphy_misc2_phy_mode_u *value) -{ - if (index >= UNIPHY_MISC2_PHY_MODE_MAX_ENTRY) - return SW_OUT_OF_RANGE; - return hppe_uniphy_reg_set( - dev_id, - NSS_UNIPHY_BASE_ADDR + UNIPHY_MISC2_PHY_MODE_ADDRESS, - index * UNIPHY_MISC2_PHY_MODE_INC, - value->val); -} - -sw_error_t -hppe_uniphy_pll_reset_ctrl_get( - a_uint32_t dev_id, - a_uint32_t index, - union pll_power_on_and_reset_u *value) -{ - if (index >= UNIPHY_PLL_POWER_ON_AND_RESET_INC_MAX_ENTRY) - return SW_OUT_OF_RANGE; - return hppe_uniphy_reg_get( - dev_id, - NSS_UNIPHY_BASE_ADDR + PLL_POWER_ON_AND_RESET_ADDRESS, - index * PLL_POWER_ON_AND_RESET_INC, - &value->val); -} - -sw_error_t -hppe_uniphy_pll_reset_ctrl_set( - a_uint32_t dev_id, - a_uint32_t index, - union pll_power_on_and_reset_u *value) -{ - if (index >= UNIPHY_PLL_POWER_ON_AND_RESET_INC_MAX_ENTRY) - return SW_OUT_OF_RANGE; - return hppe_uniphy_reg_set( - dev_id, - NSS_UNIPHY_BASE_ADDR + PLL_POWER_ON_AND_RESET_ADDRESS, - index * PLL_POWER_ON_AND_RESET_INC, - value->val); -} - diff --git a/feeds/ipq807x/qca-ssdk/src/src/hsl/hppe/hppe_vsi.c b/feeds/ipq807x/qca-ssdk/src/src/hsl/hppe/hppe_vsi.c deleted file mode 100755 index 25d1d908b..000000000 --- a/feeds/ipq807x/qca-ssdk/src/src/hsl/hppe/hppe_vsi.c +++ /dev/null @@ -1,650 +0,0 @@ -/* - * Copyright (c) 2016-2017, The Linux Foundation. All rights reserved. - * Permission to use, copy, modify, and/or distribute this software for - * any purpose with or without fee is hereby granted, provided that the - * above copyright notice and this permission notice appear in all copies. - * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES - * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR - * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES - * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN - * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT - * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. - */ - - -/** - * @defgroup - * @{ - */ -#include "sw.h" -#include "hsl.h" -#include "hppe_reg_access.h" -#include "hppe_vsi_reg.h" -#include "hppe_vsi.h" - -sw_error_t -hppe_vsi_tbl_get( - a_uint32_t dev_id, - a_uint32_t index, - union vsi_tbl_u *value) -{ - return hppe_reg_tbl_get( - dev_id, - IPE_L2_BASE_ADDR + VSI_TBL_ADDRESS + \ - index * VSI_TBL_INC, - value->val, - 2); -} - -sw_error_t -hppe_vsi_tbl_set( - a_uint32_t dev_id, - a_uint32_t index, - union vsi_tbl_u *value) -{ - return hppe_reg_tbl_set( - dev_id, - IPE_L2_BASE_ADDR + VSI_TBL_ADDRESS + \ - index * VSI_TBL_INC, - value->val, - 2); -} - -#ifndef IN_VSI_MINI -sw_error_t -hppe_vsi_tbl_umc_bitmap_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union vsi_tbl_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_vsi_tbl_get(dev_id, index, ®_val); - *value = reg_val.bf.umc_bitmap; - return ret; -} - -sw_error_t -hppe_vsi_tbl_umc_bitmap_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - union vsi_tbl_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_vsi_tbl_get(dev_id, index, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.umc_bitmap = value; - ret = hppe_vsi_tbl_set(dev_id, index, ®_val); - return ret; -} - -sw_error_t -hppe_vsi_tbl_station_move_lrn_en_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union vsi_tbl_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_vsi_tbl_get(dev_id, index, ®_val); - *value = reg_val.bf.station_move_lrn_en; - return ret; -} - -sw_error_t -hppe_vsi_tbl_station_move_lrn_en_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - union vsi_tbl_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_vsi_tbl_get(dev_id, index, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.station_move_lrn_en = value; - ret = hppe_vsi_tbl_set(dev_id, index, ®_val); - return ret; -} - -sw_error_t -hppe_vsi_tbl_new_addr_fwd_cmd_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union vsi_tbl_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_vsi_tbl_get(dev_id, index, ®_val); - *value = reg_val.bf.new_addr_fwd_cmd; - return ret; -} - -sw_error_t -hppe_vsi_tbl_new_addr_fwd_cmd_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - union vsi_tbl_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_vsi_tbl_get(dev_id, index, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.new_addr_fwd_cmd = value; - ret = hppe_vsi_tbl_set(dev_id, index, ®_val); - return ret; -} - -sw_error_t -hppe_vsi_tbl_uuc_bitmap_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union vsi_tbl_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_vsi_tbl_get(dev_id, index, ®_val); - *value = reg_val.bf.uuc_bitmap; - return ret; -} - -sw_error_t -hppe_vsi_tbl_uuc_bitmap_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - union vsi_tbl_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_vsi_tbl_get(dev_id, index, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.uuc_bitmap = value; - ret = hppe_vsi_tbl_set(dev_id, index, ®_val); - return ret; -} - -sw_error_t -hppe_vsi_tbl_member_port_bitmap_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union vsi_tbl_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_vsi_tbl_get(dev_id, index, ®_val); - *value = reg_val.bf.member_port_bitmap; - return ret; -} - -sw_error_t -hppe_vsi_tbl_member_port_bitmap_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - union vsi_tbl_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_vsi_tbl_get(dev_id, index, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.member_port_bitmap = value; - ret = hppe_vsi_tbl_set(dev_id, index, ®_val); - return ret; -} - -sw_error_t -hppe_vsi_tbl_new_addr_lrn_en_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union vsi_tbl_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_vsi_tbl_get(dev_id, index, ®_val); - *value = reg_val.bf.new_addr_lrn_en; - return ret; -} - -sw_error_t -hppe_vsi_tbl_new_addr_lrn_en_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - union vsi_tbl_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_vsi_tbl_get(dev_id, index, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.new_addr_lrn_en = value; - ret = hppe_vsi_tbl_set(dev_id, index, ®_val); - return ret; -} - -sw_error_t -hppe_vsi_tbl_bc_bitmap_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union vsi_tbl_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_vsi_tbl_get(dev_id, index, ®_val); - *value = reg_val.bf.bc_bitmap; - return ret; -} - -sw_error_t -hppe_vsi_tbl_bc_bitmap_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - union vsi_tbl_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_vsi_tbl_get(dev_id, index, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.bc_bitmap = value; - ret = hppe_vsi_tbl_set(dev_id, index, ®_val); - return ret; -} - -sw_error_t -hppe_vsi_tbl_station_move_fwd_cmd_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union vsi_tbl_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_vsi_tbl_get(dev_id, index, ®_val); - *value = reg_val.bf.station_move_fwd_cmd; - return ret; -} - -sw_error_t -hppe_vsi_tbl_station_move_fwd_cmd_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - union vsi_tbl_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_vsi_tbl_get(dev_id, index, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.station_move_fwd_cmd = value; - ret = hppe_vsi_tbl_set(dev_id, index, ®_val); - return ret; -} -#endif - -sw_error_t -hppe_vlan_cnt_tbl_get( - a_uint32_t dev_id, - a_uint32_t index, - union vlan_cnt_tbl_u *value) -{ - return hppe_reg_tbl_get( - dev_id, - INGRESS_POLICER_BASE_ADDR + VLAN_CNT_TBL_ADDRESS + \ - index * VLAN_CNT_TBL_INC, - value->val, - 3); -} - -sw_error_t -hppe_vlan_cnt_tbl_set( - a_uint32_t dev_id, - a_uint32_t index, - union vlan_cnt_tbl_u *value) -{ - return hppe_reg_tbl_set( - dev_id, - INGRESS_POLICER_BASE_ADDR + VLAN_CNT_TBL_ADDRESS + \ - index * VLAN_CNT_TBL_INC, - value->val, - 3); -} - -#ifndef IN_VSI_MINI -sw_error_t -hppe_vlan_cnt_tbl_rx_byte_cnt_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint64_t *value) -{ - union vlan_cnt_tbl_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_vlan_cnt_tbl_get(dev_id, index, ®_val); - *value = (a_uint64_t)reg_val.bf.rx_byte_cnt_1 << 32 | \ - reg_val.bf.rx_byte_cnt_0; - return ret; -} - -sw_error_t -hppe_vlan_cnt_tbl_rx_byte_cnt_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint64_t value) -{ - union vlan_cnt_tbl_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_vlan_cnt_tbl_get(dev_id, index, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.rx_byte_cnt_1 = value >> 32; - reg_val.bf.rx_byte_cnt_0 = value & (((a_uint64_t)1<<32)-1); - ret = hppe_vlan_cnt_tbl_set(dev_id, index, ®_val); - return ret; -} - -sw_error_t -hppe_vlan_cnt_tbl_rx_pkt_cnt_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union vlan_cnt_tbl_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_vlan_cnt_tbl_get(dev_id, index, ®_val); - *value = reg_val.bf.rx_pkt_cnt; - return ret; -} - -sw_error_t -hppe_vlan_cnt_tbl_rx_pkt_cnt_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - union vlan_cnt_tbl_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_vlan_cnt_tbl_get(dev_id, index, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.rx_pkt_cnt = value; - ret = hppe_vlan_cnt_tbl_set(dev_id, index, ®_val); - return ret; -} -#endif - - -sw_error_t -hppe_eg_vsi_counter_tbl_get( - a_uint32_t dev_id, - a_uint32_t index, - union eg_vsi_counter_tbl_u *value) -{ - return hppe_reg_tbl_get( - dev_id, - NSS_PTX_CSR_BASE_ADDR + EG_VSI_COUNTER_TBL_ADDRESS + \ - index * EG_VSI_COUNTER_TBL_INC, - value->val, - 3); -} - -sw_error_t -hppe_eg_vsi_counter_tbl_set( - a_uint32_t dev_id, - a_uint32_t index, - union eg_vsi_counter_tbl_u *value) -{ - return hppe_reg_tbl_set( - dev_id, - NSS_PTX_CSR_BASE_ADDR + EG_VSI_COUNTER_TBL_ADDRESS + \ - index * EG_VSI_COUNTER_TBL_INC, - value->val, - 3); -} - -#ifndef IN_VSI_MINI -sw_error_t -hppe_eg_vsi_counter_tbl_tx_bytes_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint64_t *value) -{ - union eg_vsi_counter_tbl_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_eg_vsi_counter_tbl_get(dev_id, index, ®_val); - *value = (a_uint64_t)reg_val.bf.tx_bytes_1 << 32 | \ - reg_val.bf.tx_bytes_0; - return ret; -} - -sw_error_t -hppe_eg_vsi_counter_tbl_tx_bytes_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint64_t value) -{ - union eg_vsi_counter_tbl_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_eg_vsi_counter_tbl_get(dev_id, index, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.tx_bytes_1 = value >> 32; - reg_val.bf.tx_bytes_0 = value & (((a_uint64_t)1<<32)-1); - ret = hppe_eg_vsi_counter_tbl_set(dev_id, index, ®_val); - return ret; -} - -sw_error_t -hppe_eg_vsi_counter_tbl_tx_packets_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union eg_vsi_counter_tbl_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_eg_vsi_counter_tbl_get(dev_id, index, ®_val); - *value = reg_val.bf.tx_packets; - return ret; -} - -sw_error_t -hppe_eg_vsi_counter_tbl_tx_packets_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - union eg_vsi_counter_tbl_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_eg_vsi_counter_tbl_get(dev_id, index, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.tx_packets = value; - ret = hppe_eg_vsi_counter_tbl_set(dev_id, index, ®_val); - return ret; -} -#endif - -sw_error_t -hppe_pre_l2_cnt_tbl_get( - a_uint32_t dev_id, - a_uint32_t index, - union pre_l2_cnt_tbl_u *value) -{ - return hppe_reg_tbl_get( - dev_id, - INGRESS_POLICER_BASE_ADDR + PRE_L2_CNT_TBL_ADDRESS + \ - index * PRE_L2_CNT_TBL_INC, - value->val, - 5); -} - -sw_error_t -hppe_pre_l2_cnt_tbl_set( - a_uint32_t dev_id, - a_uint32_t index, - union pre_l2_cnt_tbl_u *value) -{ - return hppe_reg_tbl_set( - dev_id, - INGRESS_POLICER_BASE_ADDR + PRE_L2_CNT_TBL_ADDRESS + \ - index * PRE_L2_CNT_TBL_INC, - value->val, - 5); -} -#ifndef IN_VSI_MINI -sw_error_t -hppe_pre_l2_cnt_tbl_rx_drop_byte_cnt_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint64_t *value) -{ - union pre_l2_cnt_tbl_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_pre_l2_cnt_tbl_get(dev_id, index, ®_val); - *value = (a_uint64_t)reg_val.bf.rx_drop_byte_cnt_1 << 24 | \ - reg_val.bf.rx_drop_byte_cnt_0; - return ret; -} - -sw_error_t -hppe_pre_l2_cnt_tbl_rx_drop_byte_cnt_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint64_t value) -{ - union pre_l2_cnt_tbl_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_pre_l2_cnt_tbl_get(dev_id, index, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.rx_drop_byte_cnt_1 = value >> 24; - reg_val.bf.rx_drop_byte_cnt_0 = value & (((a_uint64_t)1<<24)-1); - ret = hppe_pre_l2_cnt_tbl_set(dev_id, index, ®_val); - return ret; -} - -sw_error_t -hppe_pre_l2_cnt_tbl_rx_byte_cnt_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint64_t *value) -{ - union pre_l2_cnt_tbl_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_pre_l2_cnt_tbl_get(dev_id, index, ®_val); - *value = (a_uint64_t)reg_val.bf.rx_byte_cnt_1 << 32 | \ - reg_val.bf.rx_byte_cnt_0; - return ret; -} - -sw_error_t -hppe_pre_l2_cnt_tbl_rx_byte_cnt_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint64_t value) -{ - union pre_l2_cnt_tbl_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_pre_l2_cnt_tbl_get(dev_id, index, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.rx_byte_cnt_1 = value >> 32; - reg_val.bf.rx_byte_cnt_0 = value & (((a_uint64_t)1<<32)-1); - ret = hppe_pre_l2_cnt_tbl_set(dev_id, index, ®_val); - return ret; -} - -sw_error_t -hppe_pre_l2_cnt_tbl_rx_pkt_cnt_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union pre_l2_cnt_tbl_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_pre_l2_cnt_tbl_get(dev_id, index, ®_val); - *value = reg_val.bf.rx_pkt_cnt; - return ret; -} - -sw_error_t -hppe_pre_l2_cnt_tbl_rx_pkt_cnt_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - union pre_l2_cnt_tbl_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_pre_l2_cnt_tbl_get(dev_id, index, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.rx_pkt_cnt = value; - ret = hppe_pre_l2_cnt_tbl_set(dev_id, index, ®_val); - return ret; -} - -sw_error_t -hppe_pre_l2_cnt_tbl_rx_drop_pkt_cnt_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union pre_l2_cnt_tbl_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_pre_l2_cnt_tbl_get(dev_id, index, ®_val); - *value = reg_val.bf.rx_drop_pkt_cnt_1 << 24 | \ - reg_val.bf.rx_drop_pkt_cnt_0; - return ret; -} - -sw_error_t -hppe_pre_l2_cnt_tbl_rx_drop_pkt_cnt_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - union pre_l2_cnt_tbl_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_pre_l2_cnt_tbl_get(dev_id, index, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.rx_drop_pkt_cnt_1 = value >> 24; - reg_val.bf.rx_drop_pkt_cnt_0 = value & (((a_uint64_t)1<<24)-1); - ret = hppe_pre_l2_cnt_tbl_set(dev_id, index, ®_val); - return ret; -} -#endif diff --git a/feeds/ipq807x/qca-ssdk/src/src/hsl/hppe/hppe_xgmacmib.c b/feeds/ipq807x/qca-ssdk/src/src/hsl/hppe/hppe_xgmacmib.c deleted file mode 100755 index aee2f49fd..000000000 --- a/feeds/ipq807x/qca-ssdk/src/src/hsl/hppe/hppe_xgmacmib.c +++ /dev/null @@ -1,4210 +0,0 @@ -/* - * Copyright (c) 2016-2017, The Linux Foundation. All rights reserved. - * Permission to use, copy, modify, and/or distribute this software for - * any purpose with or without fee is hereby granted, provided that the - * above copyright notice and this permission notice appear in all copies. - * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES - * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR - * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES - * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN - * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT - * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. - */ - - -/** - * @defgroup - * @{ - */ -#include "sw.h" -#include "hsl.h" -#include "hppe_reg_access.h" -#include "hppe_xgmacmib_reg.h" -#include "hppe_xgmacmib.h" - - -sw_error_t -hppe_mmc_control_get( - a_uint32_t dev_id, - a_uint32_t index, - union mmc_control_u *value) -{ - if (index >= MMC_CONTROL_MAX_ENTRY) - return SW_OUT_OF_RANGE; - return hppe_reg_get( - dev_id, - NSS_XGMAC_CSR_BASE_ADDR + MMC_CONTROL_ADDRESS + \ - index * MMC_CONTROL_INC, - &value->val); -} - -sw_error_t -hppe_mmc_control_set( - a_uint32_t dev_id, - a_uint32_t index, - union mmc_control_u *value) -{ - return hppe_reg_set( - dev_id, - NSS_XGMAC_CSR_BASE_ADDR + MMC_CONTROL_ADDRESS + \ - index * MMC_CONTROL_INC, - value->val); -} - -sw_error_t -hppe_tx_octet_count_good_bad_low_get( - a_uint32_t dev_id, - a_uint32_t index, - union tx_octet_count_good_bad_low_u *value) -{ - if (index >= TX_OCTET_COUNT_GOOD_BAD_LOW_MAX_ENTRY) - return SW_OUT_OF_RANGE; - return hppe_reg_get( - dev_id, - NSS_XGMAC_CSR_BASE_ADDR + TX_OCTET_COUNT_GOOD_BAD_LOW_ADDRESS + \ - index * TX_OCTET_COUNT_GOOD_BAD_LOW_INC, - &value->val); -} - -sw_error_t -hppe_tx_octet_count_good_bad_low_set( - a_uint32_t dev_id, - a_uint32_t index, - union tx_octet_count_good_bad_low_u *value) -{ - return SW_NOT_SUPPORTED; -} - -sw_error_t -hppe_tx_octet_count_good_bad_high_get( - a_uint32_t dev_id, - a_uint32_t index, - union tx_octet_count_good_bad_high_u *value) -{ - if (index >= TX_OCTET_COUNT_GOOD_BAD_HIGH_MAX_ENTRY) - return SW_OUT_OF_RANGE; - return hppe_reg_get( - dev_id, - NSS_XGMAC_CSR_BASE_ADDR + TX_OCTET_COUNT_GOOD_BAD_HIGH_ADDRESS + \ - index * TX_OCTET_COUNT_GOOD_BAD_HIGH_INC, - &value->val); -} - -sw_error_t -hppe_tx_octet_count_good_bad_high_set( - a_uint32_t dev_id, - a_uint32_t index, - union tx_octet_count_good_bad_high_u *value) -{ - return SW_NOT_SUPPORTED; -} - -sw_error_t -hppe_tx_frame_count_good_bad_low_get( - a_uint32_t dev_id, - a_uint32_t index, - union tx_frame_count_good_bad_low_u *value) -{ - if (index >= TX_FRAME_COUNT_GOOD_BAD_LOW_MAX_ENTRY) - return SW_OUT_OF_RANGE; - return hppe_reg_get( - dev_id, - NSS_XGMAC_CSR_BASE_ADDR + TX_FRAME_COUNT_GOOD_BAD_LOW_ADDRESS + \ - index * TX_FRAME_COUNT_GOOD_BAD_LOW_INC, - &value->val); -} - -sw_error_t -hppe_tx_frame_count_good_bad_low_set( - a_uint32_t dev_id, - a_uint32_t index, - union tx_frame_count_good_bad_low_u *value) -{ - return SW_NOT_SUPPORTED; -} - -sw_error_t -hppe_tx_frame_count_good_bad_high_get( - a_uint32_t dev_id, - a_uint32_t index, - union tx_frame_count_good_bad_high_u *value) -{ - if (index >= TX_FRAME_COUNT_GOOD_BAD_HIGH_MAX_ENTRY) - return SW_OUT_OF_RANGE; - return hppe_reg_get( - dev_id, - NSS_XGMAC_CSR_BASE_ADDR + TX_FRAME_COUNT_GOOD_BAD_HIGH_ADDRESS + \ - index * TX_FRAME_COUNT_GOOD_BAD_HIGH_INC, - &value->val); -} - -sw_error_t -hppe_tx_frame_count_good_bad_high_set( - a_uint32_t dev_id, - a_uint32_t index, - union tx_frame_count_good_bad_high_u *value) -{ - return SW_NOT_SUPPORTED; -} - -sw_error_t -hppe_tx_broadcast_frames_good_low_get( - a_uint32_t dev_id, - a_uint32_t index, - union tx_broadcast_frames_good_low_u *value) -{ - if (index >= TX_BROADCAST_FRAMES_GOOD_LOW_MAX_ENTRY) - return SW_OUT_OF_RANGE; - return hppe_reg_get( - dev_id, - NSS_XGMAC_CSR_BASE_ADDR + TX_BROADCAST_FRAMES_GOOD_LOW_ADDRESS + \ - index * TX_BROADCAST_FRAMES_GOOD_LOW_INC, - &value->val); -} - -sw_error_t -hppe_tx_broadcast_frames_good_low_set( - a_uint32_t dev_id, - a_uint32_t index, - union tx_broadcast_frames_good_low_u *value) -{ - return SW_NOT_SUPPORTED; -} - -sw_error_t -hppe_tx_broadcast_frames_good_high_get( - a_uint32_t dev_id, - a_uint32_t index, - union tx_broadcast_frames_good_high_u *value) -{ - if (index >= TX_BROADCAST_FRAMES_GOOD_HIGH_MAX_ENTRY) - return SW_OUT_OF_RANGE; - return hppe_reg_get( - dev_id, - NSS_XGMAC_CSR_BASE_ADDR + TX_BROADCAST_FRAMES_GOOD_HIGH_ADDRESS + \ - index * TX_BROADCAST_FRAMES_GOOD_HIGH_INC, - &value->val); -} - -sw_error_t -hppe_tx_broadcast_frames_good_high_set( - a_uint32_t dev_id, - a_uint32_t index, - union tx_broadcast_frames_good_high_u *value) -{ - return SW_NOT_SUPPORTED; -} - -sw_error_t -hppe_tx_multicast_frames_good_low_get( - a_uint32_t dev_id, - a_uint32_t index, - union tx_multicast_frames_good_low_u *value) -{ - if (index >= TX_MULTICAST_FRAMES_GOOD_LOW_MAX_ENTRY) - return SW_OUT_OF_RANGE; - return hppe_reg_get( - dev_id, - NSS_XGMAC_CSR_BASE_ADDR + TX_MULTICAST_FRAMES_GOOD_LOW_ADDRESS + \ - index * TX_MULTICAST_FRAMES_GOOD_LOW_INC, - &value->val); -} - -sw_error_t -hppe_tx_multicast_frames_good_low_set( - a_uint32_t dev_id, - a_uint32_t index, - union tx_multicast_frames_good_low_u *value) -{ - return SW_NOT_SUPPORTED; -} - -sw_error_t -hppe_tx_multicast_frames_good_high_get( - a_uint32_t dev_id, - a_uint32_t index, - union tx_multicast_frames_good_high_u *value) -{ - if (index >= TX_MULTICAST_FRAMES_GOOD_HIGH_MAX_ENTRY) - return SW_OUT_OF_RANGE; - return hppe_reg_get( - dev_id, - NSS_XGMAC_CSR_BASE_ADDR + TX_MULTICAST_FRAMES_GOOD_HIGH_ADDRESS + \ - index * TX_MULTICAST_FRAMES_GOOD_HIGH_INC, - &value->val); -} - -sw_error_t -hppe_tx_multicast_frames_good_high_set( - a_uint32_t dev_id, - a_uint32_t index, - union tx_multicast_frames_good_high_u *value) -{ - return SW_NOT_SUPPORTED; -} - -sw_error_t -hppe_tx_64octets_frames_good_bad_low_get( - a_uint32_t dev_id, - a_uint32_t index, - union tx_64octets_frames_good_bad_low_u *value) -{ - if (index >= TX_64OCTETS_FRAMES_GOOD_BAD_LOW_MAX_ENTRY) - return SW_OUT_OF_RANGE; - return hppe_reg_get( - dev_id, - NSS_XGMAC_CSR_BASE_ADDR + TX_64OCTETS_FRAMES_GOOD_BAD_LOW_ADDRESS + \ - index * TX_64OCTETS_FRAMES_GOOD_BAD_LOW_INC, - &value->val); -} - -sw_error_t -hppe_tx_64octets_frames_good_bad_low_set( - a_uint32_t dev_id, - a_uint32_t index, - union tx_64octets_frames_good_bad_low_u *value) -{ - return SW_NOT_SUPPORTED; -} - -sw_error_t -hppe_tx_64octets_frames_good_bad_high_get( - a_uint32_t dev_id, - a_uint32_t index, - union tx_64octets_frames_good_bad_high_u *value) -{ - if (index >= TX_64OCTETS_FRAMES_GOOD_BAD_HIGH_MAX_ENTRY) - return SW_OUT_OF_RANGE; - return hppe_reg_get( - dev_id, - NSS_XGMAC_CSR_BASE_ADDR + TX_64OCTETS_FRAMES_GOOD_BAD_HIGH_ADDRESS + \ - index * TX_64OCTETS_FRAMES_GOOD_BAD_HIGH_INC, - &value->val); -} - -sw_error_t -hppe_tx_64octets_frames_good_bad_high_set( - a_uint32_t dev_id, - a_uint32_t index, - union tx_64octets_frames_good_bad_high_u *value) -{ - return SW_NOT_SUPPORTED; -} - -sw_error_t -hppe_tx_65to127octets_frames_good_bad_low_get( - a_uint32_t dev_id, - a_uint32_t index, - union tx_65to127octets_frames_good_bad_low_u *value) -{ - if (index >= TX_65TO127OCTETS_FRAMES_GOOD_BAD_LOW_MAX_ENTRY) - return SW_OUT_OF_RANGE; - return hppe_reg_get( - dev_id, - NSS_XGMAC_CSR_BASE_ADDR + TX_65TO127OCTETS_FRAMES_GOOD_BAD_LOW_ADDRESS + \ - index * TX_65TO127OCTETS_FRAMES_GOOD_BAD_LOW_INC, - &value->val); -} - -sw_error_t -hppe_tx_65to127octets_frames_good_bad_low_set( - a_uint32_t dev_id, - a_uint32_t index, - union tx_65to127octets_frames_good_bad_low_u *value) -{ - return SW_NOT_SUPPORTED; -} - -sw_error_t -hppe_tx_65to127octets_frames_good_bad_high_get( - a_uint32_t dev_id, - a_uint32_t index, - union tx_65to127octets_frames_good_bad_high_u *value) -{ - if (index >= TX_65TO127OCTETS_FRAMES_GOOD_BAD_HIGH_MAX_ENTRY) - return SW_OUT_OF_RANGE; - return hppe_reg_get( - dev_id, - NSS_XGMAC_CSR_BASE_ADDR + TX_65TO127OCTETS_FRAMES_GOOD_BAD_HIGH_ADDRESS + \ - index * TX_65TO127OCTETS_FRAMES_GOOD_BAD_HIGH_INC, - &value->val); -} - -sw_error_t -hppe_tx_65to127octets_frames_good_bad_high_set( - a_uint32_t dev_id, - a_uint32_t index, - union tx_65to127octets_frames_good_bad_high_u *value) -{ - return SW_NOT_SUPPORTED; -} - -sw_error_t -hppe_tx_128to255octets_frames_good_bad_low_get( - a_uint32_t dev_id, - a_uint32_t index, - union tx_128to255octets_frames_good_bad_low_u *value) -{ - if (index >= TX_128TO255OCTETS_FRAMES_GOOD_BAD_LOW_MAX_ENTRY) - return SW_OUT_OF_RANGE; - return hppe_reg_get( - dev_id, - NSS_XGMAC_CSR_BASE_ADDR + TX_128TO255OCTETS_FRAMES_GOOD_BAD_LOW_ADDRESS + \ - index * TX_128TO255OCTETS_FRAMES_GOOD_BAD_LOW_INC, - &value->val); -} - -sw_error_t -hppe_tx_128to255octets_frames_good_bad_low_set( - a_uint32_t dev_id, - a_uint32_t index, - union tx_128to255octets_frames_good_bad_low_u *value) -{ - return SW_NOT_SUPPORTED; -} - -sw_error_t -hppe_tx_128to255octets_frames_good_bad_high_get( - a_uint32_t dev_id, - a_uint32_t index, - union tx_128to255octets_frames_good_bad_high_u *value) -{ - if (index >= TX_128TO255OCTETS_FRAMES_GOOD_BAD_HIGH_MAX_ENTRY) - return SW_OUT_OF_RANGE; - return hppe_reg_get( - dev_id, - NSS_XGMAC_CSR_BASE_ADDR + TX_128TO255OCTETS_FRAMES_GOOD_BAD_HIGH_ADDRESS + \ - index * TX_128TO255OCTETS_FRAMES_GOOD_BAD_HIGH_INC, - &value->val); -} - -sw_error_t -hppe_tx_128to255octets_frames_good_bad_high_set( - a_uint32_t dev_id, - a_uint32_t index, - union tx_128to255octets_frames_good_bad_high_u *value) -{ - return SW_NOT_SUPPORTED; -} - -sw_error_t -hppe_tx_256to511octets_frames_good_bad_low_get( - a_uint32_t dev_id, - a_uint32_t index, - union tx_256to511octets_frames_good_bad_low_u *value) -{ - if (index >= TX_256TO511OCTETS_FRAMES_GOOD_BAD_LOW_MAX_ENTRY) - return SW_OUT_OF_RANGE; - return hppe_reg_get( - dev_id, - NSS_XGMAC_CSR_BASE_ADDR + TX_256TO511OCTETS_FRAMES_GOOD_BAD_LOW_ADDRESS + \ - index * TX_256TO511OCTETS_FRAMES_GOOD_BAD_LOW_INC, - &value->val); -} - -sw_error_t -hppe_tx_256to511octets_frames_good_bad_low_set( - a_uint32_t dev_id, - a_uint32_t index, - union tx_256to511octets_frames_good_bad_low_u *value) -{ - return SW_NOT_SUPPORTED; -} - -sw_error_t -hppe_tx_256to511octets_frames_good_bad_high_get( - a_uint32_t dev_id, - a_uint32_t index, - union tx_256to511octets_frames_good_bad_high_u *value) -{ - if (index >= TX_256TO511OCTETS_FRAMES_GOOD_BAD_HIGH_MAX_ENTRY) - return SW_OUT_OF_RANGE; - return hppe_reg_get( - dev_id, - NSS_XGMAC_CSR_BASE_ADDR + TX_256TO511OCTETS_FRAMES_GOOD_BAD_HIGH_ADDRESS + \ - index * TX_256TO511OCTETS_FRAMES_GOOD_BAD_HIGH_INC, - &value->val); -} - -sw_error_t -hppe_tx_256to511octets_frames_good_bad_high_set( - a_uint32_t dev_id, - a_uint32_t index, - union tx_256to511octets_frames_good_bad_high_u *value) -{ - return SW_NOT_SUPPORTED; -} - -sw_error_t -hppe_tx_512to1023octets_frames_good_bad_low_get( - a_uint32_t dev_id, - a_uint32_t index, - union tx_512to1023octets_frames_good_bad_low_u *value) -{ - if (index >= TX_512TO1023OCTETS_FRAMES_GOOD_BAD_LOW_MAX_ENTRY) - return SW_OUT_OF_RANGE; - return hppe_reg_get( - dev_id, - NSS_XGMAC_CSR_BASE_ADDR + TX_512TO1023OCTETS_FRAMES_GOOD_BAD_LOW_ADDRESS + \ - index * TX_512TO1023OCTETS_FRAMES_GOOD_BAD_LOW_INC, - &value->val); -} - -sw_error_t -hppe_tx_512to1023octets_frames_good_bad_low_set( - a_uint32_t dev_id, - a_uint32_t index, - union tx_512to1023octets_frames_good_bad_low_u *value) -{ - return SW_NOT_SUPPORTED; -} - -sw_error_t -hppe_tx_512to1023octets_frames_good_bad_high_get( - a_uint32_t dev_id, - a_uint32_t index, - union tx_512to1023octets_frames_good_bad_high_u *value) -{ - if (index >= TX_512TO1023OCTETS_FRAMES_GOOD_BAD_HIGH_MAX_ENTRY) - return SW_OUT_OF_RANGE; - return hppe_reg_get( - dev_id, - NSS_XGMAC_CSR_BASE_ADDR + TX_512TO1023OCTETS_FRAMES_GOOD_BAD_HIGH_ADDRESS + \ - index * TX_512TO1023OCTETS_FRAMES_GOOD_BAD_HIGH_INC, - &value->val); -} - -sw_error_t -hppe_tx_512to1023octets_frames_good_bad_high_set( - a_uint32_t dev_id, - a_uint32_t index, - union tx_512to1023octets_frames_good_bad_high_u *value) -{ - return SW_NOT_SUPPORTED; -} - -sw_error_t -hppe_tx_1024tomaxoctets_frames_good_bad_low_get( - a_uint32_t dev_id, - a_uint32_t index, - union tx_1024tomaxoctets_frames_good_bad_low_u *value) -{ - if (index >= TX_1024TOMAXOCTETS_FRAMES_GOOD_BAD_LOW_MAX_ENTRY) - return SW_OUT_OF_RANGE; - return hppe_reg_get( - dev_id, - NSS_XGMAC_CSR_BASE_ADDR + TX_1024TOMAXOCTETS_FRAMES_GOOD_BAD_LOW_ADDRESS + \ - index * TX_1024TOMAXOCTETS_FRAMES_GOOD_BAD_LOW_INC, - &value->val); -} - -sw_error_t -hppe_tx_1024tomaxoctets_frames_good_bad_low_set( - a_uint32_t dev_id, - a_uint32_t index, - union tx_1024tomaxoctets_frames_good_bad_low_u *value) -{ - return SW_NOT_SUPPORTED; -} - -sw_error_t -hppe_tx_1024tomaxoctets_frames_good_bad_high_get( - a_uint32_t dev_id, - a_uint32_t index, - union tx_1024tomaxoctets_frames_good_bad_high_u *value) -{ - if (index >= TX_1024TOMAXOCTETS_FRAMES_GOOD_BAD_HIGH_MAX_ENTRY) - return SW_OUT_OF_RANGE; - return hppe_reg_get( - dev_id, - NSS_XGMAC_CSR_BASE_ADDR + TX_1024TOMAXOCTETS_FRAMES_GOOD_BAD_HIGH_ADDRESS + \ - index * TX_1024TOMAXOCTETS_FRAMES_GOOD_BAD_HIGH_INC, - &value->val); -} - -sw_error_t -hppe_tx_1024tomaxoctets_frames_good_bad_high_set( - a_uint32_t dev_id, - a_uint32_t index, - union tx_1024tomaxoctets_frames_good_bad_high_u *value) -{ - return SW_NOT_SUPPORTED; -} - -sw_error_t -hppe_tx_unicast_frames_good_bad_low_get( - a_uint32_t dev_id, - a_uint32_t index, - union tx_unicast_frames_good_bad_low_u *value) -{ - if (index >= TX_UNICAST_FRAMES_GOOD_BAD_LOW_MAX_ENTRY) - return SW_OUT_OF_RANGE; - return hppe_reg_get( - dev_id, - NSS_XGMAC_CSR_BASE_ADDR + TX_UNICAST_FRAMES_GOOD_BAD_LOW_ADDRESS + \ - index * TX_UNICAST_FRAMES_GOOD_BAD_LOW_INC, - &value->val); -} - -sw_error_t -hppe_tx_unicast_frames_good_bad_low_set( - a_uint32_t dev_id, - a_uint32_t index, - union tx_unicast_frames_good_bad_low_u *value) -{ - return SW_NOT_SUPPORTED; -} - -sw_error_t -hppe_tx_unicast_frames_good_bad_high_get( - a_uint32_t dev_id, - a_uint32_t index, - union tx_unicast_frames_good_bad_high_u *value) -{ - if (index >= TX_UNICAST_FRAMES_GOOD_BAD_HIGH_MAX_ENTRY) - return SW_OUT_OF_RANGE; - return hppe_reg_get( - dev_id, - NSS_XGMAC_CSR_BASE_ADDR + TX_UNICAST_FRAMES_GOOD_BAD_HIGH_ADDRESS + \ - index * TX_UNICAST_FRAMES_GOOD_BAD_HIGH_INC, - &value->val); -} - -sw_error_t -hppe_tx_unicast_frames_good_bad_high_set( - a_uint32_t dev_id, - a_uint32_t index, - union tx_unicast_frames_good_bad_high_u *value) -{ - return SW_NOT_SUPPORTED; -} - -sw_error_t -hppe_tx_multicast_frames_good_bad_low_get( - a_uint32_t dev_id, - a_uint32_t index, - union tx_multicast_frames_good_bad_low_u *value) -{ - if (index >= TX_MULTICAST_FRAMES_GOOD_BAD_LOW_MAX_ENTRY) - return SW_OUT_OF_RANGE; - return hppe_reg_get( - dev_id, - NSS_XGMAC_CSR_BASE_ADDR + TX_MULTICAST_FRAMES_GOOD_BAD_LOW_ADDRESS + \ - index * TX_MULTICAST_FRAMES_GOOD_BAD_LOW_INC, - &value->val); -} - -sw_error_t -hppe_tx_multicast_frames_good_bad_low_set( - a_uint32_t dev_id, - a_uint32_t index, - union tx_multicast_frames_good_bad_low_u *value) -{ - return SW_NOT_SUPPORTED; -} - -sw_error_t -hppe_tx_multicast_frames_good_bad_high_get( - a_uint32_t dev_id, - a_uint32_t index, - union tx_multicast_frames_good_bad_high_u *value) -{ - if (index >= TX_MULTICAST_FRAMES_GOOD_BAD_HIGH_MAX_ENTRY) - return SW_OUT_OF_RANGE; - return hppe_reg_get( - dev_id, - NSS_XGMAC_CSR_BASE_ADDR + TX_MULTICAST_FRAMES_GOOD_BAD_HIGH_ADDRESS + \ - index * TX_MULTICAST_FRAMES_GOOD_BAD_HIGH_INC, - &value->val); -} - -sw_error_t -hppe_tx_multicast_frames_good_bad_high_set( - a_uint32_t dev_id, - a_uint32_t index, - union tx_multicast_frames_good_bad_high_u *value) -{ - return SW_NOT_SUPPORTED; -} - -sw_error_t -hppe_tx_broadcast_frames_good_bad_low_get( - a_uint32_t dev_id, - a_uint32_t index, - union tx_broadcast_frames_good_bad_low_u *value) -{ - if (index >= TX_BROADCAST_FRAMES_GOOD_BAD_LOW_MAX_ENTRY) - return SW_OUT_OF_RANGE; - return hppe_reg_get( - dev_id, - NSS_XGMAC_CSR_BASE_ADDR + TX_BROADCAST_FRAMES_GOOD_BAD_LOW_ADDRESS + \ - index * TX_BROADCAST_FRAMES_GOOD_BAD_LOW_INC, - &value->val); -} - -sw_error_t -hppe_tx_broadcast_frames_good_bad_low_set( - a_uint32_t dev_id, - a_uint32_t index, - union tx_broadcast_frames_good_bad_low_u *value) -{ - return SW_NOT_SUPPORTED; -} - -sw_error_t -hppe_tx_broadcast_frames_good_bad_high_get( - a_uint32_t dev_id, - a_uint32_t index, - union tx_broadcast_frames_good_bad_high_u *value) -{ - if (index >= TX_BROADCAST_FRAMES_GOOD_BAD_HIGH_MAX_ENTRY) - return SW_OUT_OF_RANGE; - return hppe_reg_get( - dev_id, - NSS_XGMAC_CSR_BASE_ADDR + TX_BROADCAST_FRAMES_GOOD_BAD_HIGH_ADDRESS + \ - index * TX_BROADCAST_FRAMES_GOOD_BAD_HIGH_INC, - &value->val); -} - -sw_error_t -hppe_tx_broadcast_frames_good_bad_high_set( - a_uint32_t dev_id, - a_uint32_t index, - union tx_broadcast_frames_good_bad_high_u *value) -{ - return SW_NOT_SUPPORTED; -} - -sw_error_t -hppe_tx_underflow_error_frames_low_get( - a_uint32_t dev_id, - a_uint32_t index, - union tx_underflow_error_frames_low_u *value) -{ - if (index >= TX_UNDERFLOW_ERROR_FRAMES_LOW_MAX_ENTRY) - return SW_OUT_OF_RANGE; - return hppe_reg_get( - dev_id, - NSS_XGMAC_CSR_BASE_ADDR + TX_UNDERFLOW_ERROR_FRAMES_LOW_ADDRESS + \ - index * TX_UNDERFLOW_ERROR_FRAMES_LOW_INC, - &value->val); -} - -sw_error_t -hppe_tx_underflow_error_frames_low_set( - a_uint32_t dev_id, - a_uint32_t index, - union tx_underflow_error_frames_low_u *value) -{ - return SW_NOT_SUPPORTED; -} - -sw_error_t -hppe_tx_underflow_error_frames_high_get( - a_uint32_t dev_id, - a_uint32_t index, - union tx_underflow_error_frames_high_u *value) -{ - if (index >= TX_UNDERFLOW_ERROR_FRAMES_HIGH_MAX_ENTRY) - return SW_OUT_OF_RANGE; - return hppe_reg_get( - dev_id, - NSS_XGMAC_CSR_BASE_ADDR + TX_UNDERFLOW_ERROR_FRAMES_HIGH_ADDRESS + \ - index * TX_UNDERFLOW_ERROR_FRAMES_HIGH_INC, - &value->val); -} - -sw_error_t -hppe_tx_underflow_error_frames_high_set( - a_uint32_t dev_id, - a_uint32_t index, - union tx_underflow_error_frames_high_u *value) -{ - return SW_NOT_SUPPORTED; -} - -sw_error_t -hppe_tx_octet_count_good_low_get( - a_uint32_t dev_id, - a_uint32_t index, - union tx_octet_count_good_low_u *value) -{ - if (index >= TX_OCTET_COUNT_GOOD_LOW_MAX_ENTRY) - return SW_OUT_OF_RANGE; - return hppe_reg_get( - dev_id, - NSS_XGMAC_CSR_BASE_ADDR + TX_OCTET_COUNT_GOOD_LOW_ADDRESS + \ - index * TX_OCTET_COUNT_GOOD_LOW_INC, - &value->val); -} - -sw_error_t -hppe_tx_octet_count_good_low_set( - a_uint32_t dev_id, - a_uint32_t index, - union tx_octet_count_good_low_u *value) -{ - return SW_NOT_SUPPORTED; -} - -sw_error_t -hppe_tx_octet_count_good_high_get( - a_uint32_t dev_id, - a_uint32_t index, - union tx_octet_count_good_high_u *value) -{ - if (index >= TX_OCTET_COUNT_GOOD_HIGH_MAX_ENTRY) - return SW_OUT_OF_RANGE; - return hppe_reg_get( - dev_id, - NSS_XGMAC_CSR_BASE_ADDR + TX_OCTET_COUNT_GOOD_HIGH_ADDRESS + \ - index * TX_OCTET_COUNT_GOOD_HIGH_INC, - &value->val); -} - -sw_error_t -hppe_tx_octet_count_good_high_set( - a_uint32_t dev_id, - a_uint32_t index, - union tx_octet_count_good_high_u *value) -{ - return SW_NOT_SUPPORTED; -} - -sw_error_t -hppe_tx_frame_count_good_low_get( - a_uint32_t dev_id, - a_uint32_t index, - union tx_frame_count_good_low_u *value) -{ - if (index >= TX_FRAME_COUNT_GOOD_LOW_MAX_ENTRY) - return SW_OUT_OF_RANGE; - return hppe_reg_get( - dev_id, - NSS_XGMAC_CSR_BASE_ADDR + TX_FRAME_COUNT_GOOD_LOW_ADDRESS + \ - index * TX_FRAME_COUNT_GOOD_LOW_INC, - &value->val); -} - -sw_error_t -hppe_tx_frame_count_good_low_set( - a_uint32_t dev_id, - a_uint32_t index, - union tx_frame_count_good_low_u *value) -{ - return SW_NOT_SUPPORTED; -} - -sw_error_t -hppe_tx_frame_count_good_high_get( - a_uint32_t dev_id, - a_uint32_t index, - union tx_frame_count_good_high_u *value) -{ - if (index >= TX_FRAME_COUNT_GOOD_HIGH_MAX_ENTRY) - return SW_OUT_OF_RANGE; - return hppe_reg_get( - dev_id, - NSS_XGMAC_CSR_BASE_ADDR + TX_FRAME_COUNT_GOOD_HIGH_ADDRESS + \ - index * TX_FRAME_COUNT_GOOD_HIGH_INC, - &value->val); -} - -sw_error_t -hppe_tx_frame_count_good_high_set( - a_uint32_t dev_id, - a_uint32_t index, - union tx_frame_count_good_high_u *value) -{ - return SW_NOT_SUPPORTED; -} - -sw_error_t -hppe_tx_pause_frames_low_get( - a_uint32_t dev_id, - a_uint32_t index, - union tx_pause_frames_low_u *value) -{ - if (index >= TX_PAUSE_FRAMES_LOW_MAX_ENTRY) - return SW_OUT_OF_RANGE; - return hppe_reg_get( - dev_id, - NSS_XGMAC_CSR_BASE_ADDR + TX_PAUSE_FRAMES_LOW_ADDRESS + \ - index * TX_PAUSE_FRAMES_LOW_INC, - &value->val); -} - -sw_error_t -hppe_tx_pause_frames_low_set( - a_uint32_t dev_id, - a_uint32_t index, - union tx_pause_frames_low_u *value) -{ - return SW_NOT_SUPPORTED; -} - -sw_error_t -hppe_tx_pause_frames_high_get( - a_uint32_t dev_id, - a_uint32_t index, - union tx_pause_frames_high_u *value) -{ - if (index >= TX_PAUSE_FRAMES_HIGH_MAX_ENTRY) - return SW_OUT_OF_RANGE; - return hppe_reg_get( - dev_id, - NSS_XGMAC_CSR_BASE_ADDR + TX_PAUSE_FRAMES_HIGH_ADDRESS + \ - index * TX_PAUSE_FRAMES_HIGH_INC, - &value->val); -} - -sw_error_t -hppe_tx_pause_frames_high_set( - a_uint32_t dev_id, - a_uint32_t index, - union tx_pause_frames_high_u *value) -{ - return SW_NOT_SUPPORTED; -} - -sw_error_t -hppe_tx_vlan_frames_good_low_get( - a_uint32_t dev_id, - a_uint32_t index, - union tx_vlan_frames_good_low_u *value) -{ - if (index >= TX_VLAN_FRAMES_GOOD_LOW_MAX_ENTRY) - return SW_OUT_OF_RANGE; - return hppe_reg_get( - dev_id, - NSS_XGMAC_CSR_BASE_ADDR + TX_VLAN_FRAMES_GOOD_LOW_ADDRESS + \ - index * TX_VLAN_FRAMES_GOOD_LOW_INC, - &value->val); -} - -sw_error_t -hppe_tx_vlan_frames_good_low_set( - a_uint32_t dev_id, - a_uint32_t index, - union tx_vlan_frames_good_low_u *value) -{ - return SW_NOT_SUPPORTED; -} - -sw_error_t -hppe_tx_vlan_frames_good_high_get( - a_uint32_t dev_id, - a_uint32_t index, - union tx_vlan_frames_good_high_u *value) -{ - if (index >= TX_VLAN_FRAMES_GOOD_HIGH_MAX_ENTRY) - return SW_OUT_OF_RANGE; - return hppe_reg_get( - dev_id, - NSS_XGMAC_CSR_BASE_ADDR + TX_VLAN_FRAMES_GOOD_HIGH_ADDRESS + \ - index * TX_VLAN_FRAMES_GOOD_HIGH_INC, - &value->val); -} - -sw_error_t -hppe_tx_vlan_frames_good_high_set( - a_uint32_t dev_id, - a_uint32_t index, - union tx_vlan_frames_good_high_u *value) -{ - return SW_NOT_SUPPORTED; -} - -sw_error_t -hppe_tx_lpi_usec_cntr_get( - a_uint32_t dev_id, - a_uint32_t index, - union tx_lpi_usec_cntr_u *value) -{ - if (index >= TX_LPI_USEC_CNTR_MAX_ENTRY) - return SW_OUT_OF_RANGE; - return hppe_reg_get( - dev_id, - NSS_XGMAC_CSR_BASE_ADDR + TX_LPI_USEC_CNTR_ADDRESS + \ - index * TX_LPI_USEC_CNTR_INC, - &value->val); -} - -sw_error_t -hppe_tx_lpi_usec_cntr_set( - a_uint32_t dev_id, - a_uint32_t index, - union tx_lpi_usec_cntr_u *value) -{ - return SW_NOT_SUPPORTED; -} - -sw_error_t -hppe_tx_lpi_tran_cntr_get( - a_uint32_t dev_id, - a_uint32_t index, - union tx_lpi_tran_cntr_u *value) -{ - if (index >= TX_LPI_TRAN_CNTR_MAX_ENTRY) - return SW_OUT_OF_RANGE; - return hppe_reg_get( - dev_id, - NSS_XGMAC_CSR_BASE_ADDR + TX_LPI_TRAN_CNTR_ADDRESS + \ - index * TX_LPI_TRAN_CNTR_INC, - &value->val); -} - -sw_error_t -hppe_tx_lpi_tran_cntr_set( - a_uint32_t dev_id, - a_uint32_t index, - union tx_lpi_tran_cntr_u *value) -{ - return SW_NOT_SUPPORTED; -} - -sw_error_t -hppe_rx_frame_count_good_bad_low_get( - a_uint32_t dev_id, - a_uint32_t index, - union rx_frame_count_good_bad_low_u *value) -{ - if (index >= RX_FRAME_COUNT_GOOD_BAD_LOW_MAX_ENTRY) - return SW_OUT_OF_RANGE; - return hppe_reg_get( - dev_id, - NSS_XGMAC_CSR_BASE_ADDR + RX_FRAME_COUNT_GOOD_BAD_LOW_ADDRESS + \ - index * RX_FRAME_COUNT_GOOD_BAD_LOW_INC, - &value->val); -} - -sw_error_t -hppe_rx_frame_count_good_bad_low_set( - a_uint32_t dev_id, - a_uint32_t index, - union rx_frame_count_good_bad_low_u *value) -{ - return SW_NOT_SUPPORTED; -} - -sw_error_t -hppe_rx_frame_count_good_bad_high_get( - a_uint32_t dev_id, - a_uint32_t index, - union rx_frame_count_good_bad_high_u *value) -{ - if (index >= RX_FRAME_COUNT_GOOD_BAD_HIGH_MAX_ENTRY) - return SW_OUT_OF_RANGE; - return hppe_reg_get( - dev_id, - NSS_XGMAC_CSR_BASE_ADDR + RX_FRAME_COUNT_GOOD_BAD_HIGH_ADDRESS + \ - index * RX_FRAME_COUNT_GOOD_BAD_HIGH_INC, - &value->val); -} - -sw_error_t -hppe_rx_frame_count_good_bad_high_set( - a_uint32_t dev_id, - a_uint32_t index, - union rx_frame_count_good_bad_high_u *value) -{ - return SW_NOT_SUPPORTED; -} - -sw_error_t -hppe_rx_octet_count_good_bad_low_get( - a_uint32_t dev_id, - a_uint32_t index, - union rx_octet_count_good_bad_low_u *value) -{ - if (index >= RX_OCTET_COUNT_GOOD_BAD_LOW_MAX_ENTRY) - return SW_OUT_OF_RANGE; - return hppe_reg_get( - dev_id, - NSS_XGMAC_CSR_BASE_ADDR + RX_OCTET_COUNT_GOOD_BAD_LOW_ADDRESS + \ - index * RX_OCTET_COUNT_GOOD_BAD_LOW_INC, - &value->val); -} - -sw_error_t -hppe_rx_octet_count_good_bad_low_set( - a_uint32_t dev_id, - a_uint32_t index, - union rx_octet_count_good_bad_low_u *value) -{ - return SW_NOT_SUPPORTED; -} - -sw_error_t -hppe_rx_octet_count_good_bad_high_get( - a_uint32_t dev_id, - a_uint32_t index, - union rx_octet_count_good_bad_high_u *value) -{ - if (index >= RX_OCTET_COUNT_GOOD_BAD_HIGH_MAX_ENTRY) - return SW_OUT_OF_RANGE; - return hppe_reg_get( - dev_id, - NSS_XGMAC_CSR_BASE_ADDR + RX_OCTET_COUNT_GOOD_BAD_HIGH_ADDRESS + \ - index * RX_OCTET_COUNT_GOOD_BAD_HIGH_INC, - &value->val); -} - -sw_error_t -hppe_rx_octet_count_good_bad_high_set( - a_uint32_t dev_id, - a_uint32_t index, - union rx_octet_count_good_bad_high_u *value) -{ - return SW_NOT_SUPPORTED; -} - -sw_error_t -hppe_rx_octet_count_good_low_get( - a_uint32_t dev_id, - a_uint32_t index, - union rx_octet_count_good_low_u *value) -{ - if (index >= RX_OCTET_COUNT_GOOD_LOW_MAX_ENTRY) - return SW_OUT_OF_RANGE; - return hppe_reg_get( - dev_id, - NSS_XGMAC_CSR_BASE_ADDR + RX_OCTET_COUNT_GOOD_LOW_ADDRESS + \ - index * RX_OCTET_COUNT_GOOD_LOW_INC, - &value->val); -} - -sw_error_t -hppe_rx_octet_count_good_low_set( - a_uint32_t dev_id, - a_uint32_t index, - union rx_octet_count_good_low_u *value) -{ - return SW_NOT_SUPPORTED; -} - -sw_error_t -hppe_rx_octet_count_good_high_get( - a_uint32_t dev_id, - a_uint32_t index, - union rx_octet_count_good_high_u *value) -{ - if (index >= RX_OCTET_COUNT_GOOD_HIGH_MAX_ENTRY) - return SW_OUT_OF_RANGE; - return hppe_reg_get( - dev_id, - NSS_XGMAC_CSR_BASE_ADDR + RX_OCTET_COUNT_GOOD_HIGH_ADDRESS + \ - index * RX_OCTET_COUNT_GOOD_HIGH_INC, - &value->val); -} - -sw_error_t -hppe_rx_octet_count_good_high_set( - a_uint32_t dev_id, - a_uint32_t index, - union rx_octet_count_good_high_u *value) -{ - return SW_NOT_SUPPORTED; -} - -sw_error_t -hppe_rx_broadcast_frames_good_low_get( - a_uint32_t dev_id, - a_uint32_t index, - union rx_broadcast_frames_good_low_u *value) -{ - if (index >= RX_BROADCAST_FRAMES_GOOD_LOW_MAX_ENTRY) - return SW_OUT_OF_RANGE; - return hppe_reg_get( - dev_id, - NSS_XGMAC_CSR_BASE_ADDR + RX_BROADCAST_FRAMES_GOOD_LOW_ADDRESS + \ - index * RX_BROADCAST_FRAMES_GOOD_LOW_INC, - &value->val); -} - -sw_error_t -hppe_rx_broadcast_frames_good_low_set( - a_uint32_t dev_id, - a_uint32_t index, - union rx_broadcast_frames_good_low_u *value) -{ - return SW_NOT_SUPPORTED; -} - -sw_error_t -hppe_rx_broadcast_frames_good_high_get( - a_uint32_t dev_id, - a_uint32_t index, - union rx_broadcast_frames_good_high_u *value) -{ - if (index >= RX_BROADCAST_FRAMES_GOOD_HIGH_MAX_ENTRY) - return SW_OUT_OF_RANGE; - return hppe_reg_get( - dev_id, - NSS_XGMAC_CSR_BASE_ADDR + RX_BROADCAST_FRAMES_GOOD_HIGH_ADDRESS + \ - index * RX_BROADCAST_FRAMES_GOOD_HIGH_INC, - &value->val); -} - -sw_error_t -hppe_rx_broadcast_frames_good_high_set( - a_uint32_t dev_id, - a_uint32_t index, - union rx_broadcast_frames_good_high_u *value) -{ - return SW_NOT_SUPPORTED; -} - -sw_error_t -hppe_rx_multicast_frames_good_low_get( - a_uint32_t dev_id, - a_uint32_t index, - union rx_multicast_frames_good_low_u *value) -{ - if (index >= RX_MULTICAST_FRAMES_GOOD_LOW_MAX_ENTRY) - return SW_OUT_OF_RANGE; - return hppe_reg_get( - dev_id, - NSS_XGMAC_CSR_BASE_ADDR + RX_MULTICAST_FRAMES_GOOD_LOW_ADDRESS + \ - index * RX_MULTICAST_FRAMES_GOOD_LOW_INC, - &value->val); -} - -sw_error_t -hppe_rx_multicast_frames_good_low_set( - a_uint32_t dev_id, - a_uint32_t index, - union rx_multicast_frames_good_low_u *value) -{ - return SW_NOT_SUPPORTED; -} - -sw_error_t -hppe_rx_multicast_frames_good_high_get( - a_uint32_t dev_id, - a_uint32_t index, - union rx_multicast_frames_good_high_u *value) -{ - if (index >= RX_MULTICAST_FRAMES_GOOD_HIGH_MAX_ENTRY) - return SW_OUT_OF_RANGE; - return hppe_reg_get( - dev_id, - NSS_XGMAC_CSR_BASE_ADDR + RX_MULTICAST_FRAMES_GOOD_HIGH_ADDRESS + \ - index * RX_MULTICAST_FRAMES_GOOD_HIGH_INC, - &value->val); -} - -sw_error_t -hppe_rx_multicast_frames_good_high_set( - a_uint32_t dev_id, - a_uint32_t index, - union rx_multicast_frames_good_high_u *value) -{ - return SW_NOT_SUPPORTED; -} - -sw_error_t -hppe_rx_crc_error_frames_low_get( - a_uint32_t dev_id, - a_uint32_t index, - union rx_crc_error_frames_low_u *value) -{ - if (index >= RX_CRC_ERROR_FRAMES_LOW_MAX_ENTRY) - return SW_OUT_OF_RANGE; - return hppe_reg_get( - dev_id, - NSS_XGMAC_CSR_BASE_ADDR + RX_CRC_ERROR_FRAMES_LOW_ADDRESS + \ - index * RX_CRC_ERROR_FRAMES_LOW_INC, - &value->val); -} - -sw_error_t -hppe_rx_crc_error_frames_low_set( - a_uint32_t dev_id, - a_uint32_t index, - union rx_crc_error_frames_low_u *value) -{ - return SW_NOT_SUPPORTED; -} - -sw_error_t -hppe_rx_crc_error_frames_high_get( - a_uint32_t dev_id, - a_uint32_t index, - union rx_crc_error_frames_high_u *value) -{ - if (index >= RX_CRC_ERROR_FRAMES_HIGH_MAX_ENTRY) - return SW_OUT_OF_RANGE; - return hppe_reg_get( - dev_id, - NSS_XGMAC_CSR_BASE_ADDR + RX_CRC_ERROR_FRAMES_HIGH_ADDRESS + \ - index * RX_CRC_ERROR_FRAMES_HIGH_INC, - &value->val); -} - -sw_error_t -hppe_rx_crc_error_frames_high_set( - a_uint32_t dev_id, - a_uint32_t index, - union rx_crc_error_frames_high_u *value) -{ - return SW_NOT_SUPPORTED; -} - -sw_error_t -hppe_rx_runt_error_frames_get( - a_uint32_t dev_id, - a_uint32_t index, - union rx_runt_error_frames_u *value) -{ - if (index >= RX_RUNT_ERROR_FRAMES_MAX_ENTRY) - return SW_OUT_OF_RANGE; - return hppe_reg_get( - dev_id, - NSS_XGMAC_CSR_BASE_ADDR + RX_RUNT_ERROR_FRAMES_ADDRESS + \ - index * RX_RUNT_ERROR_FRAMES_INC, - &value->val); -} - -sw_error_t -hppe_rx_runt_error_frames_set( - a_uint32_t dev_id, - a_uint32_t index, - union rx_runt_error_frames_u *value) -{ - return SW_NOT_SUPPORTED; -} - -sw_error_t -hppe_rx_jabber_error_frames_get( - a_uint32_t dev_id, - a_uint32_t index, - union rx_jabber_error_frames_u *value) -{ - if (index >= RX_JABBER_ERROR_FRAMES_MAX_ENTRY) - return SW_OUT_OF_RANGE; - return hppe_reg_get( - dev_id, - NSS_XGMAC_CSR_BASE_ADDR + RX_JABBER_ERROR_FRAMES_ADDRESS + \ - index * RX_JABBER_ERROR_FRAMES_INC, - &value->val); -} - -sw_error_t -hppe_rx_jabber_error_frames_set( - a_uint32_t dev_id, - a_uint32_t index, - union rx_jabber_error_frames_u *value) -{ - return SW_NOT_SUPPORTED; -} - -sw_error_t -hppe_rx_undersize_frames_good_get( - a_uint32_t dev_id, - a_uint32_t index, - union rx_undersize_frames_good_u *value) -{ - if (index >= RX_UNDERSIZE_FRAMES_GOOD_MAX_ENTRY) - return SW_OUT_OF_RANGE; - return hppe_reg_get( - dev_id, - NSS_XGMAC_CSR_BASE_ADDR + RX_UNDERSIZE_FRAMES_GOOD_ADDRESS + \ - index * RX_UNDERSIZE_FRAMES_GOOD_INC, - &value->val); -} - -sw_error_t -hppe_rx_undersize_frames_good_set( - a_uint32_t dev_id, - a_uint32_t index, - union rx_undersize_frames_good_u *value) -{ - return SW_NOT_SUPPORTED; -} - -sw_error_t -hppe_rx_oversize_frames_good_get( - a_uint32_t dev_id, - a_uint32_t index, - union rx_oversize_frames_good_u *value) -{ - if (index >= RX_OVERSIZE_FRAMES_GOOD_MAX_ENTRY) - return SW_OUT_OF_RANGE; - return hppe_reg_get( - dev_id, - NSS_XGMAC_CSR_BASE_ADDR + RX_OVERSIZE_FRAMES_GOOD_ADDRESS + \ - index * RX_OVERSIZE_FRAMES_GOOD_INC, - &value->val); -} - -sw_error_t -hppe_rx_oversize_frames_good_set( - a_uint32_t dev_id, - a_uint32_t index, - union rx_oversize_frames_good_u *value) -{ - return SW_NOT_SUPPORTED; -} - -sw_error_t -hppe_rx_64octets_frames_good_bad_low_get( - a_uint32_t dev_id, - a_uint32_t index, - union rx_64octets_frames_good_bad_low_u *value) -{ - if (index >= RX_64OCTETS_FRAMES_GOOD_BAD_LOW_MAX_ENTRY) - return SW_OUT_OF_RANGE; - return hppe_reg_get( - dev_id, - NSS_XGMAC_CSR_BASE_ADDR + RX_64OCTETS_FRAMES_GOOD_BAD_LOW_ADDRESS + \ - index * RX_64OCTETS_FRAMES_GOOD_BAD_LOW_INC, - &value->val); -} - -sw_error_t -hppe_rx_64octets_frames_good_bad_low_set( - a_uint32_t dev_id, - a_uint32_t index, - union rx_64octets_frames_good_bad_low_u *value) -{ - return SW_NOT_SUPPORTED; -} - -sw_error_t -hppe_rx_64octets_frames_good_bad_high_get( - a_uint32_t dev_id, - a_uint32_t index, - union rx_64octets_frames_good_bad_high_u *value) -{ - if (index >= RX_64OCTETS_FRAMES_GOOD_BAD_HIGH_MAX_ENTRY) - return SW_OUT_OF_RANGE; - return hppe_reg_get( - dev_id, - NSS_XGMAC_CSR_BASE_ADDR + RX_64OCTETS_FRAMES_GOOD_BAD_HIGH_ADDRESS + \ - index * RX_64OCTETS_FRAMES_GOOD_BAD_HIGH_INC, - &value->val); -} - -sw_error_t -hppe_rx_64octets_frames_good_bad_high_set( - a_uint32_t dev_id, - a_uint32_t index, - union rx_64octets_frames_good_bad_high_u *value) -{ - return SW_NOT_SUPPORTED; -} - -sw_error_t -hppe_rx_65to127octets_frames_good_bad_low_get( - a_uint32_t dev_id, - a_uint32_t index, - union rx_65to127octets_frames_good_bad_low_u *value) -{ - if (index >= RX_65TO127OCTETS_FRAMES_GOOD_BAD_LOW_MAX_ENTRY) - return SW_OUT_OF_RANGE; - return hppe_reg_get( - dev_id, - NSS_XGMAC_CSR_BASE_ADDR + RX_65TO127OCTETS_FRAMES_GOOD_BAD_LOW_ADDRESS + \ - index * RX_65TO127OCTETS_FRAMES_GOOD_BAD_LOW_INC, - &value->val); -} - -sw_error_t -hppe_rx_65to127octets_frames_good_bad_low_set( - a_uint32_t dev_id, - a_uint32_t index, - union rx_65to127octets_frames_good_bad_low_u *value) -{ - return SW_NOT_SUPPORTED; -} - -sw_error_t -hppe_rx_65to127octets_frames_good_bad_high_get( - a_uint32_t dev_id, - a_uint32_t index, - union rx_65to127octets_frames_good_bad_high_u *value) -{ - if (index >= RX_65TO127OCTETS_FRAMES_GOOD_BAD_HIGH_MAX_ENTRY) - return SW_OUT_OF_RANGE; - return hppe_reg_get( - dev_id, - NSS_XGMAC_CSR_BASE_ADDR + RX_65TO127OCTETS_FRAMES_GOOD_BAD_HIGH_ADDRESS + \ - index * RX_65TO127OCTETS_FRAMES_GOOD_BAD_HIGH_INC, - &value->val); -} - -sw_error_t -hppe_rx_65to127octets_frames_good_bad_high_set( - a_uint32_t dev_id, - a_uint32_t index, - union rx_65to127octets_frames_good_bad_high_u *value) -{ - return SW_NOT_SUPPORTED; -} - -sw_error_t -hppe_rx_128to255octets_frames_good_bad_low_get( - a_uint32_t dev_id, - a_uint32_t index, - union rx_128to255octets_frames_good_bad_low_u *value) -{ - if (index >= RX_128TO255OCTETS_FRAMES_GOOD_BAD_LOW_MAX_ENTRY) - return SW_OUT_OF_RANGE; - return hppe_reg_get( - dev_id, - NSS_XGMAC_CSR_BASE_ADDR + RX_128TO255OCTETS_FRAMES_GOOD_BAD_LOW_ADDRESS + \ - index * RX_128TO255OCTETS_FRAMES_GOOD_BAD_LOW_INC, - &value->val); -} - -sw_error_t -hppe_rx_128to255octets_frames_good_bad_low_set( - a_uint32_t dev_id, - a_uint32_t index, - union rx_128to255octets_frames_good_bad_low_u *value) -{ - return SW_NOT_SUPPORTED; -} - -sw_error_t -hppe_rx_128to255octets_frames_good_bad_high_get( - a_uint32_t dev_id, - a_uint32_t index, - union rx_128to255octets_frames_good_bad_high_u *value) -{ - if (index >= RX_128TO255OCTETS_FRAMES_GOOD_BAD_HIGH_MAX_ENTRY) - return SW_OUT_OF_RANGE; - return hppe_reg_get( - dev_id, - NSS_XGMAC_CSR_BASE_ADDR + RX_128TO255OCTETS_FRAMES_GOOD_BAD_HIGH_ADDRESS + \ - index * RX_128TO255OCTETS_FRAMES_GOOD_BAD_HIGH_INC, - &value->val); -} - -sw_error_t -hppe_rx_128to255octets_frames_good_bad_high_set( - a_uint32_t dev_id, - a_uint32_t index, - union rx_128to255octets_frames_good_bad_high_u *value) -{ - return SW_NOT_SUPPORTED; -} - -sw_error_t -hppe_rx_256to511octets_frames_good_bad_low_get( - a_uint32_t dev_id, - a_uint32_t index, - union rx_256to511octets_frames_good_bad_low_u *value) -{ - if (index >= RX_256TO511OCTETS_FRAMES_GOOD_BAD_LOW_MAX_ENTRY) - return SW_OUT_OF_RANGE; - return hppe_reg_get( - dev_id, - NSS_XGMAC_CSR_BASE_ADDR + RX_256TO511OCTETS_FRAMES_GOOD_BAD_LOW_ADDRESS + \ - index * RX_256TO511OCTETS_FRAMES_GOOD_BAD_LOW_INC, - &value->val); -} - -sw_error_t -hppe_rx_256to511octets_frames_good_bad_low_set( - a_uint32_t dev_id, - a_uint32_t index, - union rx_256to511octets_frames_good_bad_low_u *value) -{ - return SW_NOT_SUPPORTED; -} - -sw_error_t -hppe_rx_256to511octets_frames_good_bad_high_get( - a_uint32_t dev_id, - a_uint32_t index, - union rx_256to511octets_frames_good_bad_high_u *value) -{ - if (index >= RX_256TO511OCTETS_FRAMES_GOOD_BAD_HIGH_MAX_ENTRY) - return SW_OUT_OF_RANGE; - return hppe_reg_get( - dev_id, - NSS_XGMAC_CSR_BASE_ADDR + RX_256TO511OCTETS_FRAMES_GOOD_BAD_HIGH_ADDRESS + \ - index * RX_256TO511OCTETS_FRAMES_GOOD_BAD_HIGH_INC, - &value->val); -} - -sw_error_t -hppe_rx_256to511octets_frames_good_bad_high_set( - a_uint32_t dev_id, - a_uint32_t index, - union rx_256to511octets_frames_good_bad_high_u *value) -{ - return SW_NOT_SUPPORTED; -} - -sw_error_t -hppe_rx_512to1023octets_frames_good_bad_low_get( - a_uint32_t dev_id, - a_uint32_t index, - union rx_512to1023octets_frames_good_bad_low_u *value) -{ - if (index >= RX_512TO1023OCTETS_FRAMES_GOOD_BAD_LOW_MAX_ENTRY) - return SW_OUT_OF_RANGE; - return hppe_reg_get( - dev_id, - NSS_XGMAC_CSR_BASE_ADDR + RX_512TO1023OCTETS_FRAMES_GOOD_BAD_LOW_ADDRESS + \ - index * RX_512TO1023OCTETS_FRAMES_GOOD_BAD_LOW_INC, - &value->val); -} - -sw_error_t -hppe_rx_512to1023octets_frames_good_bad_low_set( - a_uint32_t dev_id, - a_uint32_t index, - union rx_512to1023octets_frames_good_bad_low_u *value) -{ - return SW_NOT_SUPPORTED; -} - -sw_error_t -hppe_rx_512to1023octets_frames_good_bad_high_get( - a_uint32_t dev_id, - a_uint32_t index, - union rx_512to1023octets_frames_good_bad_high_u *value) -{ - if (index >= RX_512TO1023OCTETS_FRAMES_GOOD_BAD_HIGH_MAX_ENTRY) - return SW_OUT_OF_RANGE; - return hppe_reg_get( - dev_id, - NSS_XGMAC_CSR_BASE_ADDR + RX_512TO1023OCTETS_FRAMES_GOOD_BAD_HIGH_ADDRESS + \ - index * RX_512TO1023OCTETS_FRAMES_GOOD_BAD_HIGH_INC, - &value->val); -} - -sw_error_t -hppe_rx_512to1023octets_frames_good_bad_high_set( - a_uint32_t dev_id, - a_uint32_t index, - union rx_512to1023octets_frames_good_bad_high_u *value) -{ - return SW_NOT_SUPPORTED; -} - -sw_error_t -hppe_rx_1024tomaxoctets_frames_good_bad_low_get( - a_uint32_t dev_id, - a_uint32_t index, - union rx_1024tomaxoctets_frames_good_bad_low_u *value) -{ - if (index >= RX_1024TOMAXOCTETS_FRAMES_GOOD_BAD_LOW_MAX_ENTRY) - return SW_OUT_OF_RANGE; - return hppe_reg_get( - dev_id, - NSS_XGMAC_CSR_BASE_ADDR + RX_1024TOMAXOCTETS_FRAMES_GOOD_BAD_LOW_ADDRESS + \ - index * RX_1024TOMAXOCTETS_FRAMES_GOOD_BAD_LOW_INC, - &value->val); -} - -sw_error_t -hppe_rx_1024tomaxoctets_frames_good_bad_low_set( - a_uint32_t dev_id, - a_uint32_t index, - union rx_1024tomaxoctets_frames_good_bad_low_u *value) -{ - return SW_NOT_SUPPORTED; -} - -sw_error_t -hppe_rx_1024tomaxoctets_frames_good_bad_high_get( - a_uint32_t dev_id, - a_uint32_t index, - union rx_1024tomaxoctets_frames_good_bad_high_u *value) -{ - if (index >= RX_1024TOMAXOCTETS_FRAMES_GOOD_BAD_HIGH_MAX_ENTRY) - return SW_OUT_OF_RANGE; - return hppe_reg_get( - dev_id, - NSS_XGMAC_CSR_BASE_ADDR + RX_1024TOMAXOCTETS_FRAMES_GOOD_BAD_HIGH_ADDRESS + \ - index * RX_1024TOMAXOCTETS_FRAMES_GOOD_BAD_HIGH_INC, - &value->val); -} - -sw_error_t -hppe_rx_1024tomaxoctets_frames_good_bad_high_set( - a_uint32_t dev_id, - a_uint32_t index, - union rx_1024tomaxoctets_frames_good_bad_high_u *value) -{ - return SW_NOT_SUPPORTED; -} - -sw_error_t -hppe_rx_unicast_frames_good_low_get( - a_uint32_t dev_id, - a_uint32_t index, - union rx_unicast_frames_good_low_u *value) -{ - if (index >= RX_UNICAST_FRAMES_GOOD_LOW_MAX_ENTRY) - return SW_OUT_OF_RANGE; - return hppe_reg_get( - dev_id, - NSS_XGMAC_CSR_BASE_ADDR + RX_UNICAST_FRAMES_GOOD_LOW_ADDRESS + \ - index * RX_UNICAST_FRAMES_GOOD_LOW_INC, - &value->val); -} - -sw_error_t -hppe_rx_unicast_frames_good_low_set( - a_uint32_t dev_id, - a_uint32_t index, - union rx_unicast_frames_good_low_u *value) -{ - return SW_NOT_SUPPORTED; -} - -sw_error_t -hppe_rx_unicast_frames_good_high_get( - a_uint32_t dev_id, - a_uint32_t index, - union rx_unicast_frames_good_high_u *value) -{ - if (index >= RX_UNICAST_FRAMES_GOOD_HIGH_MAX_ENTRY) - return SW_OUT_OF_RANGE; - return hppe_reg_get( - dev_id, - NSS_XGMAC_CSR_BASE_ADDR + RX_UNICAST_FRAMES_GOOD_HIGH_ADDRESS + \ - index * RX_UNICAST_FRAMES_GOOD_HIGH_INC, - &value->val); -} - -sw_error_t -hppe_rx_unicast_frames_good_high_set( - a_uint32_t dev_id, - a_uint32_t index, - union rx_unicast_frames_good_high_u *value) -{ - return SW_NOT_SUPPORTED; -} - -sw_error_t -hppe_rx_length_error_frames_low_get( - a_uint32_t dev_id, - a_uint32_t index, - union rx_length_error_frames_low_u *value) -{ - if (index >= RX_LENGTH_ERROR_FRAMES_LOW_MAX_ENTRY) - return SW_OUT_OF_RANGE; - return hppe_reg_get( - dev_id, - NSS_XGMAC_CSR_BASE_ADDR + RX_LENGTH_ERROR_FRAMES_LOW_ADDRESS + \ - index * RX_LENGTH_ERROR_FRAMES_LOW_INC, - &value->val); -} - -sw_error_t -hppe_rx_length_error_frames_low_set( - a_uint32_t dev_id, - a_uint32_t index, - union rx_length_error_frames_low_u *value) -{ - return SW_NOT_SUPPORTED; -} - -sw_error_t -hppe_rx_length_error_frames_high_get( - a_uint32_t dev_id, - a_uint32_t index, - union rx_length_error_frames_high_u *value) -{ - if (index >= RX_LENGTH_ERROR_FRAMES_HIGH_MAX_ENTRY) - return SW_OUT_OF_RANGE; - return hppe_reg_get( - dev_id, - NSS_XGMAC_CSR_BASE_ADDR + RX_LENGTH_ERROR_FRAMES_HIGH_ADDRESS + \ - index * RX_LENGTH_ERROR_FRAMES_HIGH_INC, - &value->val); -} - -sw_error_t -hppe_rx_length_error_frames_high_set( - a_uint32_t dev_id, - a_uint32_t index, - union rx_length_error_frames_high_u *value) -{ - return SW_NOT_SUPPORTED; -} - -sw_error_t -hppe_rx_outofrange_frames_low_get( - a_uint32_t dev_id, - a_uint32_t index, - union rx_outofrange_frames_low_u *value) -{ - if (index >= RX_OUTOFRANGE_FRAMES_LOW_MAX_ENTRY) - return SW_OUT_OF_RANGE; - return hppe_reg_get( - dev_id, - NSS_XGMAC_CSR_BASE_ADDR + RX_OUTOFRANGE_FRAMES_LOW_ADDRESS + \ - index * RX_OUTOFRANGE_FRAMES_LOW_INC, - &value->val); -} - -sw_error_t -hppe_rx_outofrange_frames_low_set( - a_uint32_t dev_id, - a_uint32_t index, - union rx_outofrange_frames_low_u *value) -{ - return SW_NOT_SUPPORTED; -} - -sw_error_t -hppe_rx_outofrange_frames_high_get( - a_uint32_t dev_id, - a_uint32_t index, - union rx_outofrange_frames_high_u *value) -{ - if (index >= RX_OUTOFRANGE_FRAMES_HIGH_MAX_ENTRY) - return SW_OUT_OF_RANGE; - return hppe_reg_get( - dev_id, - NSS_XGMAC_CSR_BASE_ADDR + RX_OUTOFRANGE_FRAMES_HIGH_ADDRESS + \ - index * RX_OUTOFRANGE_FRAMES_HIGH_INC, - &value->val); -} - -sw_error_t -hppe_rx_outofrange_frames_high_set( - a_uint32_t dev_id, - a_uint32_t index, - union rx_outofrange_frames_high_u *value) -{ - return SW_NOT_SUPPORTED; -} - -sw_error_t -hppe_rx_pause_frames_low_get( - a_uint32_t dev_id, - a_uint32_t index, - union rx_pause_frames_low_u *value) -{ - if (index >= RX_PAUSE_FRAMES_LOW_MAX_ENTRY) - return SW_OUT_OF_RANGE; - return hppe_reg_get( - dev_id, - NSS_XGMAC_CSR_BASE_ADDR + RX_PAUSE_FRAMES_LOW_ADDRESS + \ - index * RX_PAUSE_FRAMES_LOW_INC, - &value->val); -} - -sw_error_t -hppe_rx_pause_frames_low_set( - a_uint32_t dev_id, - a_uint32_t index, - union rx_pause_frames_low_u *value) -{ - return SW_NOT_SUPPORTED; -} - -sw_error_t -hppe_rx_pause_frames_high_get( - a_uint32_t dev_id, - a_uint32_t index, - union rx_pause_frames_high_u *value) -{ - if (index >= RX_PAUSE_FRAMES_HIGH_MAX_ENTRY) - return SW_OUT_OF_RANGE; - return hppe_reg_get( - dev_id, - NSS_XGMAC_CSR_BASE_ADDR + RX_PAUSE_FRAMES_HIGH_ADDRESS + \ - index * RX_PAUSE_FRAMES_HIGH_INC, - &value->val); -} - -sw_error_t -hppe_rx_pause_frames_high_set( - a_uint32_t dev_id, - a_uint32_t index, - union rx_pause_frames_high_u *value) -{ - return SW_NOT_SUPPORTED; -} - -sw_error_t -hppe_rx_fifooverflow_frames_low_get( - a_uint32_t dev_id, - a_uint32_t index, - union rx_fifooverflow_frames_low_u *value) -{ - if (index >= RX_FIFOOVERFLOW_FRAMES_LOW_MAX_ENTRY) - return SW_OUT_OF_RANGE; - return hppe_reg_get( - dev_id, - NSS_XGMAC_CSR_BASE_ADDR + RX_FIFOOVERFLOW_FRAMES_LOW_ADDRESS + \ - index * RX_FIFOOVERFLOW_FRAMES_LOW_INC, - &value->val); -} - -sw_error_t -hppe_rx_fifooverflow_frames_low_set( - a_uint32_t dev_id, - a_uint32_t index, - union rx_fifooverflow_frames_low_u *value) -{ - return SW_NOT_SUPPORTED; -} - -sw_error_t -hppe_rx_fifooverflow_frames_high_get( - a_uint32_t dev_id, - a_uint32_t index, - union rx_fifooverflow_frames_high_u *value) -{ - if (index >= RX_FIFOOVERFLOW_FRAMES_HIGH_MAX_ENTRY) - return SW_OUT_OF_RANGE; - return hppe_reg_get( - dev_id, - NSS_XGMAC_CSR_BASE_ADDR + RX_FIFOOVERFLOW_FRAMES_HIGH_ADDRESS + \ - index * RX_FIFOOVERFLOW_FRAMES_HIGH_INC, - &value->val); -} - -sw_error_t -hppe_rx_fifooverflow_frames_high_set( - a_uint32_t dev_id, - a_uint32_t index, - union rx_fifooverflow_frames_high_u *value) -{ - return SW_NOT_SUPPORTED; -} - -sw_error_t -hppe_rx_vlan_frames_good_bad_low_get( - a_uint32_t dev_id, - a_uint32_t index, - union rx_vlan_frames_good_bad_low_u *value) -{ - if (index >= RX_VLAN_FRAMES_GOOD_BAD_LOW_MAX_ENTRY) - return SW_OUT_OF_RANGE; - return hppe_reg_get( - dev_id, - NSS_XGMAC_CSR_BASE_ADDR + RX_VLAN_FRAMES_GOOD_BAD_LOW_ADDRESS + \ - index * RX_VLAN_FRAMES_GOOD_BAD_LOW_INC, - &value->val); -} - -sw_error_t -hppe_rx_vlan_frames_good_bad_low_set( - a_uint32_t dev_id, - a_uint32_t index, - union rx_vlan_frames_good_bad_low_u *value) -{ - return SW_NOT_SUPPORTED; -} - -sw_error_t -hppe_rx_vlan_frames_good_bad_high_get( - a_uint32_t dev_id, - a_uint32_t index, - union rx_vlan_frames_good_bad_high_u *value) -{ - if (index >= RX_VLAN_FRAMES_GOOD_BAD_HIGH_MAX_ENTRY) - return SW_OUT_OF_RANGE; - return hppe_reg_get( - dev_id, - NSS_XGMAC_CSR_BASE_ADDR + RX_VLAN_FRAMES_GOOD_BAD_HIGH_ADDRESS + \ - index * RX_VLAN_FRAMES_GOOD_BAD_HIGH_INC, - &value->val); -} - -sw_error_t -hppe_rx_vlan_frames_good_bad_high_set( - a_uint32_t dev_id, - a_uint32_t index, - union rx_vlan_frames_good_bad_high_u *value) -{ - return SW_NOT_SUPPORTED; -} - -sw_error_t -hppe_rx_watchdog_error_frames_get( - a_uint32_t dev_id, - a_uint32_t index, - union rx_watchdog_error_frames_u *value) -{ - if (index >= RX_WATCHDOG_ERROR_FRAMES_MAX_ENTRY) - return SW_OUT_OF_RANGE; - return hppe_reg_get( - dev_id, - NSS_XGMAC_CSR_BASE_ADDR + RX_WATCHDOG_ERROR_FRAMES_ADDRESS + \ - index * RX_WATCHDOG_ERROR_FRAMES_INC, - &value->val); -} - -sw_error_t -hppe_rx_watchdog_error_frames_set( - a_uint32_t dev_id, - a_uint32_t index, - union rx_watchdog_error_frames_u *value) -{ - return SW_NOT_SUPPORTED; -} - -sw_error_t -hppe_rx_lpi_usec_cntr_get( - a_uint32_t dev_id, - a_uint32_t index, - union rx_lpi_usec_cntr_u *value) -{ - if (index >= RX_LPI_USEC_CNTR_MAX_ENTRY) - return SW_OUT_OF_RANGE; - return hppe_reg_get( - dev_id, - NSS_XGMAC_CSR_BASE_ADDR + RX_LPI_USEC_CNTR_ADDRESS + \ - index * RX_LPI_USEC_CNTR_INC, - &value->val); -} - -sw_error_t -hppe_rx_lpi_usec_cntr_set( - a_uint32_t dev_id, - a_uint32_t index, - union rx_lpi_usec_cntr_u *value) -{ - return SW_NOT_SUPPORTED; -} - -sw_error_t -hppe_rx_lpi_tran_cntr_get( - a_uint32_t dev_id, - a_uint32_t index, - union rx_lpi_tran_cntr_u *value) -{ - if (index >= RX_LPI_TRAN_CNTR_MAX_ENTRY) - return SW_OUT_OF_RANGE; - return hppe_reg_get( - dev_id, - NSS_XGMAC_CSR_BASE_ADDR + RX_LPI_TRAN_CNTR_ADDRESS + \ - index * RX_LPI_TRAN_CNTR_INC, - &value->val); -} - -sw_error_t -hppe_rx_lpi_tran_cntr_set( - a_uint32_t dev_id, - a_uint32_t index, - union rx_lpi_tran_cntr_u *value) -{ - return SW_NOT_SUPPORTED; -} - -sw_error_t -hppe_rx_discard_frame_count_good_bad_low_get( - a_uint32_t dev_id, - a_uint32_t index, - union rx_discard_frame_count_good_bad_low_u *value) -{ - if (index >= RX_DISCARD_FRAME_COUNT_GOOD_BAD_LOW_MAX_ENTRY) - return SW_OUT_OF_RANGE; - return hppe_reg_get( - dev_id, - NSS_XGMAC_CSR_BASE_ADDR + RX_DISCARD_FRAME_COUNT_GOOD_BAD_LOW_ADDRESS + \ - index * RX_DISCARD_FRAME_COUNT_GOOD_BAD_LOW_INC, - &value->val); -} - -sw_error_t -hppe_rx_discard_frame_count_good_bad_low_set( - a_uint32_t dev_id, - a_uint32_t index, - union rx_discard_frame_count_good_bad_low_u *value) -{ - return SW_NOT_SUPPORTED; -} - -sw_error_t -hppe_rx_discard_frame_count_good_bad_high_get( - a_uint32_t dev_id, - a_uint32_t index, - union rx_discard_frame_count_good_bad_high_u *value) -{ - if (index >= RX_DISCARD_FRAME_COUNT_GOOD_BAD_HIGH_MAX_ENTRY) - return SW_OUT_OF_RANGE; - return hppe_reg_get( - dev_id, - NSS_XGMAC_CSR_BASE_ADDR + RX_DISCARD_FRAME_COUNT_GOOD_BAD_HIGH_ADDRESS + \ - index * RX_DISCARD_FRAME_COUNT_GOOD_BAD_HIGH_INC, - &value->val); -} - -sw_error_t -hppe_rx_discard_frame_count_good_bad_high_set( - a_uint32_t dev_id, - a_uint32_t index, - union rx_discard_frame_count_good_bad_high_u *value) -{ - return SW_NOT_SUPPORTED; -} - -sw_error_t -hppe_rx_discard_octet_count_good_bad_low_get( - a_uint32_t dev_id, - a_uint32_t index, - union rx_discard_octet_count_good_bad_low_u *value) -{ - if (index >= RX_DISCARD_OCTET_COUNT_GOOD_BAD_LOW_MAX_ENTRY) - return SW_OUT_OF_RANGE; - return hppe_reg_get( - dev_id, - NSS_XGMAC_CSR_BASE_ADDR + RX_DISCARD_OCTET_COUNT_GOOD_BAD_LOW_ADDRESS + \ - index * RX_DISCARD_OCTET_COUNT_GOOD_BAD_LOW_INC, - &value->val); -} - -sw_error_t -hppe_rx_discard_octet_count_good_bad_low_set( - a_uint32_t dev_id, - a_uint32_t index, - union rx_discard_octet_count_good_bad_low_u *value) -{ - return SW_NOT_SUPPORTED; -} - -sw_error_t -hppe_rx_discard_octet_count_good_bad_high_get( - a_uint32_t dev_id, - a_uint32_t index, - union rx_discard_octet_count_good_bad_high_u *value) -{ - if (index >= RX_DISCARD_OCTET_COUNT_GOOD_BAD_HIGH_MAX_ENTRY) - return SW_OUT_OF_RANGE; - return hppe_reg_get( - dev_id, - NSS_XGMAC_CSR_BASE_ADDR + RX_DISCARD_OCTET_COUNT_GOOD_BAD_HIGH_ADDRESS + \ - index * RX_DISCARD_OCTET_COUNT_GOOD_BAD_HIGH_INC, - &value->val); -} - -sw_error_t -hppe_rx_discard_octet_count_good_bad_high_set( - a_uint32_t dev_id, - a_uint32_t index, - union rx_discard_octet_count_good_bad_high_u *value) -{ - return SW_NOT_SUPPORTED; -} - -sw_error_t -hppe_mmc_control_cntrst_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union mmc_control_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_mmc_control_get(dev_id, index, ®_val); - *value = reg_val.bf.cntrst; - return ret; -} - -sw_error_t -hppe_mmc_control_cntrst_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - return SW_NOT_SUPPORTED; -} - -sw_error_t -hppe_mmc_control_rstonrd_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union mmc_control_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_mmc_control_get(dev_id, index, ®_val); - *value = reg_val.bf.rstonrd; - return ret; -} - -sw_error_t -hppe_mmc_control_rstonrd_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - return SW_NOT_SUPPORTED; -} - -sw_error_t -hppe_mmc_control_cntstopro_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union mmc_control_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_mmc_control_get(dev_id, index, ®_val); - *value = reg_val.bf.cntstopro; - return ret; -} - -sw_error_t -hppe_mmc_control_cntstopro_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - return SW_NOT_SUPPORTED; -} - -sw_error_t -hppe_mmc_control_mct_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union mmc_control_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_mmc_control_get(dev_id, index, ®_val); - *value = reg_val.bf.mct; - return ret; -} - -sw_error_t -hppe_mmc_control_mct_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - return SW_NOT_SUPPORTED; -} - -sw_error_t -hppe_mmc_control_pr_mmc_sel_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union mmc_control_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_mmc_control_get(dev_id, index, ®_val); - *value = reg_val.bf.pr_mmc_sel; - return ret; -} - -sw_error_t -hppe_mmc_control_pr_mmc_sel_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - return SW_NOT_SUPPORTED; -} - -sw_error_t -hppe_mmc_control_cntprst_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union mmc_control_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_mmc_control_get(dev_id, index, ®_val); - *value = reg_val.bf.cntprst; - return ret; -} - -sw_error_t -hppe_mmc_control_cntprst_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - return SW_NOT_SUPPORTED; -} - -sw_error_t -hppe_mmc_control_mcf_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union mmc_control_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_mmc_control_get(dev_id, index, ®_val); - *value = reg_val.bf.mcf; - return ret; -} - -sw_error_t -hppe_mmc_control_mcf_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - return SW_NOT_SUPPORTED; -} - -sw_error_t -hppe_tx_octet_count_good_bad_low_txoctgblo_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union tx_octet_count_good_bad_low_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_tx_octet_count_good_bad_low_get(dev_id, index, ®_val); - *value = reg_val.bf.txoctgblo; - return ret; -} - -sw_error_t -hppe_tx_octet_count_good_bad_low_txoctgblo_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - return SW_NOT_SUPPORTED; -} - -sw_error_t -hppe_tx_octet_count_good_bad_high_txoctgbhi_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union tx_octet_count_good_bad_high_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_tx_octet_count_good_bad_high_get(dev_id, index, ®_val); - *value = reg_val.bf.txoctgbhi; - return ret; -} - -sw_error_t -hppe_tx_octet_count_good_bad_high_txoctgbhi_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - return SW_NOT_SUPPORTED; -} - -sw_error_t -hppe_tx_frame_count_good_bad_low_txfrmgblo_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union tx_frame_count_good_bad_low_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_tx_frame_count_good_bad_low_get(dev_id, index, ®_val); - *value = reg_val.bf.txfrmgblo; - return ret; -} - -sw_error_t -hppe_tx_frame_count_good_bad_low_txfrmgblo_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - return SW_NOT_SUPPORTED; -} - -sw_error_t -hppe_tx_frame_count_good_bad_high_txfrmgbhi_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union tx_frame_count_good_bad_high_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_tx_frame_count_good_bad_high_get(dev_id, index, ®_val); - *value = reg_val.bf.txfrmgbhi; - return ret; -} - -sw_error_t -hppe_tx_frame_count_good_bad_high_txfrmgbhi_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - return SW_NOT_SUPPORTED; -} - -sw_error_t -hppe_tx_broadcast_frames_good_low_txbcastglo_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union tx_broadcast_frames_good_low_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_tx_broadcast_frames_good_low_get(dev_id, index, ®_val); - *value = reg_val.bf.txbcastglo; - return ret; -} - -sw_error_t -hppe_tx_broadcast_frames_good_low_txbcastglo_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - return SW_NOT_SUPPORTED; -} - -sw_error_t -hppe_tx_broadcast_frames_good_high_txbcastghi_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union tx_broadcast_frames_good_high_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_tx_broadcast_frames_good_high_get(dev_id, index, ®_val); - *value = reg_val.bf.txbcastghi; - return ret; -} - -sw_error_t -hppe_tx_broadcast_frames_good_high_txbcastghi_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - return SW_NOT_SUPPORTED; -} - -sw_error_t -hppe_tx_multicast_frames_good_low_txmcastglo_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union tx_multicast_frames_good_low_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_tx_multicast_frames_good_low_get(dev_id, index, ®_val); - *value = reg_val.bf.txmcastglo; - return ret; -} - -sw_error_t -hppe_tx_multicast_frames_good_low_txmcastglo_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - return SW_NOT_SUPPORTED; -} - -sw_error_t -hppe_tx_multicast_frames_good_high_txmcastghi_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union tx_multicast_frames_good_high_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_tx_multicast_frames_good_high_get(dev_id, index, ®_val); - *value = reg_val.bf.txmcastghi; - return ret; -} - -sw_error_t -hppe_tx_multicast_frames_good_high_txmcastghi_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - return SW_NOT_SUPPORTED; -} - -sw_error_t -hppe_tx_64octets_frames_good_bad_low_tx64octgblo_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union tx_64octets_frames_good_bad_low_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_tx_64octets_frames_good_bad_low_get(dev_id, index, ®_val); - *value = reg_val.bf.tx64octgblo; - return ret; -} - -sw_error_t -hppe_tx_64octets_frames_good_bad_low_tx64octgblo_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - return SW_NOT_SUPPORTED; -} - -sw_error_t -hppe_tx_64octets_frames_good_bad_high_tx64octgbhi_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union tx_64octets_frames_good_bad_high_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_tx_64octets_frames_good_bad_high_get(dev_id, index, ®_val); - *value = reg_val.bf.tx64octgbhi; - return ret; -} - -sw_error_t -hppe_tx_64octets_frames_good_bad_high_tx64octgbhi_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - return SW_NOT_SUPPORTED; -} - -sw_error_t -hppe_tx_65to127octets_frames_good_bad_low_tx65_127octgblo_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union tx_65to127octets_frames_good_bad_low_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_tx_65to127octets_frames_good_bad_low_get(dev_id, index, ®_val); - *value = reg_val.bf.tx65_127octgblo; - return ret; -} - -sw_error_t -hppe_tx_65to127octets_frames_good_bad_low_tx65_127octgblo_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - return SW_NOT_SUPPORTED; -} - -sw_error_t -hppe_tx_65to127octets_frames_good_bad_high_tx65_127octgbhi_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union tx_65to127octets_frames_good_bad_high_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_tx_65to127octets_frames_good_bad_high_get(dev_id, index, ®_val); - *value = reg_val.bf.tx65_127octgbhi; - return ret; -} - -sw_error_t -hppe_tx_65to127octets_frames_good_bad_high_tx65_127octgbhi_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - return SW_NOT_SUPPORTED; -} - -sw_error_t -hppe_tx_128to255octets_frames_good_bad_low_tx128_255octgblo_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union tx_128to255octets_frames_good_bad_low_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_tx_128to255octets_frames_good_bad_low_get(dev_id, index, ®_val); - *value = reg_val.bf.tx128_255octgblo; - return ret; -} - -sw_error_t -hppe_tx_128to255octets_frames_good_bad_low_tx128_255octgblo_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - return SW_NOT_SUPPORTED; -} - -sw_error_t -hppe_tx_128to255octets_frames_good_bad_high_tx128_255octgbhi_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union tx_128to255octets_frames_good_bad_high_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_tx_128to255octets_frames_good_bad_high_get(dev_id, index, ®_val); - *value = reg_val.bf.tx128_255octgbhi; - return ret; -} - -sw_error_t -hppe_tx_128to255octets_frames_good_bad_high_tx128_255octgbhi_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - return SW_NOT_SUPPORTED; -} - -sw_error_t -hppe_tx_256to511octets_frames_good_bad_low_tx256_511octgblo_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union tx_256to511octets_frames_good_bad_low_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_tx_256to511octets_frames_good_bad_low_get(dev_id, index, ®_val); - *value = reg_val.bf.tx256_511octgblo; - return ret; -} - -sw_error_t -hppe_tx_256to511octets_frames_good_bad_low_tx256_511octgblo_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - return SW_NOT_SUPPORTED; -} - -sw_error_t -hppe_tx_256to511octets_frames_good_bad_high_tx256_511octgbhi_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union tx_256to511octets_frames_good_bad_high_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_tx_256to511octets_frames_good_bad_high_get(dev_id, index, ®_val); - *value = reg_val.bf.tx256_511octgbhi; - return ret; -} - -sw_error_t -hppe_tx_256to511octets_frames_good_bad_high_tx256_511octgbhi_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - return SW_NOT_SUPPORTED; -} - -sw_error_t -hppe_tx_512to1023octets_frames_good_bad_low_tx512_1023octgblo_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union tx_512to1023octets_frames_good_bad_low_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_tx_512to1023octets_frames_good_bad_low_get(dev_id, index, ®_val); - *value = reg_val.bf.tx512_1023octgblo; - return ret; -} - -sw_error_t -hppe_tx_512to1023octets_frames_good_bad_low_tx512_1023octgblo_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - return SW_NOT_SUPPORTED; -} - -sw_error_t -hppe_tx_512to1023octets_frames_good_bad_high_tx512_1023octgbhi_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union tx_512to1023octets_frames_good_bad_high_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_tx_512to1023octets_frames_good_bad_high_get(dev_id, index, ®_val); - *value = reg_val.bf.tx512_1023octgbhi; - return ret; -} - -sw_error_t -hppe_tx_512to1023octets_frames_good_bad_high_tx512_1023octgbhi_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - return SW_NOT_SUPPORTED; -} - -sw_error_t -hppe_tx_1024tomaxoctets_frames_good_bad_low_tx1024_maxoctgblo_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union tx_1024tomaxoctets_frames_good_bad_low_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_tx_1024tomaxoctets_frames_good_bad_low_get(dev_id, index, ®_val); - *value = reg_val.bf.tx1024_maxoctgblo; - return ret; -} - -sw_error_t -hppe_tx_1024tomaxoctets_frames_good_bad_low_tx1024_maxoctgblo_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - return SW_NOT_SUPPORTED; -} - -sw_error_t -hppe_tx_1024tomaxoctets_frames_good_bad_high_tx1024_maxoctgbhi_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union tx_1024tomaxoctets_frames_good_bad_high_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_tx_1024tomaxoctets_frames_good_bad_high_get(dev_id, index, ®_val); - *value = reg_val.bf.tx1024_maxoctgbhi; - return ret; -} - -sw_error_t -hppe_tx_1024tomaxoctets_frames_good_bad_high_tx1024_maxoctgbhi_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - return SW_NOT_SUPPORTED; -} - -sw_error_t -hppe_tx_unicast_frames_good_bad_low_txucastgblo_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union tx_unicast_frames_good_bad_low_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_tx_unicast_frames_good_bad_low_get(dev_id, index, ®_val); - *value = reg_val.bf.txucastgblo; - return ret; -} - -sw_error_t -hppe_tx_unicast_frames_good_bad_low_txucastgblo_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - return SW_NOT_SUPPORTED; -} - -sw_error_t -hppe_tx_unicast_frames_good_bad_high_txucastgbhi_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union tx_unicast_frames_good_bad_high_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_tx_unicast_frames_good_bad_high_get(dev_id, index, ®_val); - *value = reg_val.bf.txucastgbhi; - return ret; -} - -sw_error_t -hppe_tx_unicast_frames_good_bad_high_txucastgbhi_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - return SW_NOT_SUPPORTED; -} - -sw_error_t -hppe_tx_multicast_frames_good_bad_low_txmcastgblo_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union tx_multicast_frames_good_bad_low_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_tx_multicast_frames_good_bad_low_get(dev_id, index, ®_val); - *value = reg_val.bf.txmcastgblo; - return ret; -} - -sw_error_t -hppe_tx_multicast_frames_good_bad_low_txmcastgblo_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - return SW_NOT_SUPPORTED; -} - -sw_error_t -hppe_tx_multicast_frames_good_bad_high_txmcastgbhi_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union tx_multicast_frames_good_bad_high_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_tx_multicast_frames_good_bad_high_get(dev_id, index, ®_val); - *value = reg_val.bf.txmcastgbhi; - return ret; -} - -sw_error_t -hppe_tx_multicast_frames_good_bad_high_txmcastgbhi_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - return SW_NOT_SUPPORTED; -} - -sw_error_t -hppe_tx_broadcast_frames_good_bad_low_txbcastgblo_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union tx_broadcast_frames_good_bad_low_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_tx_broadcast_frames_good_bad_low_get(dev_id, index, ®_val); - *value = reg_val.bf.txbcastgblo; - return ret; -} - -sw_error_t -hppe_tx_broadcast_frames_good_bad_low_txbcastgblo_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - return SW_NOT_SUPPORTED; -} - -sw_error_t -hppe_tx_broadcast_frames_good_bad_high_txbcastgbhi_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union tx_broadcast_frames_good_bad_high_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_tx_broadcast_frames_good_bad_high_get(dev_id, index, ®_val); - *value = reg_val.bf.txbcastgbhi; - return ret; -} - -sw_error_t -hppe_tx_broadcast_frames_good_bad_high_txbcastgbhi_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - return SW_NOT_SUPPORTED; -} - -sw_error_t -hppe_tx_underflow_error_frames_low_txundrflwlo_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union tx_underflow_error_frames_low_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_tx_underflow_error_frames_low_get(dev_id, index, ®_val); - *value = reg_val.bf.txundrflwlo; - return ret; -} - -sw_error_t -hppe_tx_underflow_error_frames_low_txundrflwlo_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - return SW_NOT_SUPPORTED; -} - -sw_error_t -hppe_tx_underflow_error_frames_high_txundrflwhi_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union tx_underflow_error_frames_high_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_tx_underflow_error_frames_high_get(dev_id, index, ®_val); - *value = reg_val.bf.txundrflwhi; - return ret; -} - -sw_error_t -hppe_tx_underflow_error_frames_high_txundrflwhi_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - return SW_NOT_SUPPORTED; -} - -sw_error_t -hppe_tx_octet_count_good_low_txoctglo_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union tx_octet_count_good_low_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_tx_octet_count_good_low_get(dev_id, index, ®_val); - *value = reg_val.bf.txoctglo; - return ret; -} - -sw_error_t -hppe_tx_octet_count_good_low_txoctglo_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - return SW_NOT_SUPPORTED; -} - -sw_error_t -hppe_tx_octet_count_good_high_txoctghi_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union tx_octet_count_good_high_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_tx_octet_count_good_high_get(dev_id, index, ®_val); - *value = reg_val.bf.txoctghi; - return ret; -} - -sw_error_t -hppe_tx_octet_count_good_high_txoctghi_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - return SW_NOT_SUPPORTED; -} - -sw_error_t -hppe_tx_frame_count_good_low_txfrmglo_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union tx_frame_count_good_low_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_tx_frame_count_good_low_get(dev_id, index, ®_val); - *value = reg_val.bf.txfrmglo; - return ret; -} - -sw_error_t -hppe_tx_frame_count_good_low_txfrmglo_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - return SW_NOT_SUPPORTED; -} - -sw_error_t -hppe_tx_frame_count_good_high_txfrmghi_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union tx_frame_count_good_high_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_tx_frame_count_good_high_get(dev_id, index, ®_val); - *value = reg_val.bf.txfrmghi; - return ret; -} - -sw_error_t -hppe_tx_frame_count_good_high_txfrmghi_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - return SW_NOT_SUPPORTED; -} - -sw_error_t -hppe_tx_pause_frames_low_txpauseglo_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union tx_pause_frames_low_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_tx_pause_frames_low_get(dev_id, index, ®_val); - *value = reg_val.bf.txpauseglo; - return ret; -} - -sw_error_t -hppe_tx_pause_frames_low_txpauseglo_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - return SW_NOT_SUPPORTED; -} - -sw_error_t -hppe_tx_pause_frames_high_txpauseghi_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union tx_pause_frames_high_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_tx_pause_frames_high_get(dev_id, index, ®_val); - *value = reg_val.bf.txpauseghi; - return ret; -} - -sw_error_t -hppe_tx_pause_frames_high_txpauseghi_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - return SW_NOT_SUPPORTED; -} - -sw_error_t -hppe_tx_vlan_frames_good_low_txvlanglo_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union tx_vlan_frames_good_low_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_tx_vlan_frames_good_low_get(dev_id, index, ®_val); - *value = reg_val.bf.txvlanglo; - return ret; -} - -sw_error_t -hppe_tx_vlan_frames_good_low_txvlanglo_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - return SW_NOT_SUPPORTED; -} - -sw_error_t -hppe_tx_vlan_frames_good_high_txvlanghi_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union tx_vlan_frames_good_high_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_tx_vlan_frames_good_high_get(dev_id, index, ®_val); - *value = reg_val.bf.txvlanghi; - return ret; -} - -sw_error_t -hppe_tx_vlan_frames_good_high_txvlanghi_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - return SW_NOT_SUPPORTED; -} - -sw_error_t -hppe_tx_lpi_usec_cntr_txlpiusc_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union tx_lpi_usec_cntr_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_tx_lpi_usec_cntr_get(dev_id, index, ®_val); - *value = reg_val.bf.txlpiusc; - return ret; -} - -sw_error_t -hppe_tx_lpi_usec_cntr_txlpiusc_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - return SW_NOT_SUPPORTED; -} - -sw_error_t -hppe_tx_lpi_tran_cntr_txlpitrc_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union tx_lpi_tran_cntr_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_tx_lpi_tran_cntr_get(dev_id, index, ®_val); - *value = reg_val.bf.txlpitrc; - return ret; -} - -sw_error_t -hppe_tx_lpi_tran_cntr_txlpitrc_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - return SW_NOT_SUPPORTED; -} - -sw_error_t -hppe_rx_frame_count_good_bad_low_rxfrmgblo_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union rx_frame_count_good_bad_low_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_rx_frame_count_good_bad_low_get(dev_id, index, ®_val); - *value = reg_val.bf.rxfrmgblo; - return ret; -} - -sw_error_t -hppe_rx_frame_count_good_bad_low_rxfrmgblo_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - return SW_NOT_SUPPORTED; -} - -sw_error_t -hppe_rx_frame_count_good_bad_high_rxfrmgbhi_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union rx_frame_count_good_bad_high_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_rx_frame_count_good_bad_high_get(dev_id, index, ®_val); - *value = reg_val.bf.rxfrmgbhi; - return ret; -} - -sw_error_t -hppe_rx_frame_count_good_bad_high_rxfrmgbhi_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - return SW_NOT_SUPPORTED; -} - -sw_error_t -hppe_rx_octet_count_good_bad_low_rxoctgblo_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union rx_octet_count_good_bad_low_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_rx_octet_count_good_bad_low_get(dev_id, index, ®_val); - *value = reg_val.bf.rxoctgblo; - return ret; -} - -sw_error_t -hppe_rx_octet_count_good_bad_low_rxoctgblo_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - return SW_NOT_SUPPORTED; -} - -sw_error_t -hppe_rx_octet_count_good_bad_high_rxoctgbhi_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union rx_octet_count_good_bad_high_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_rx_octet_count_good_bad_high_get(dev_id, index, ®_val); - *value = reg_val.bf.rxoctgbhi; - return ret; -} - -sw_error_t -hppe_rx_octet_count_good_bad_high_rxoctgbhi_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - return SW_NOT_SUPPORTED; -} - -sw_error_t -hppe_rx_octet_count_good_low_rxoctglo_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union rx_octet_count_good_low_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_rx_octet_count_good_low_get(dev_id, index, ®_val); - *value = reg_val.bf.rxoctglo; - return ret; -} - -sw_error_t -hppe_rx_octet_count_good_low_rxoctglo_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - return SW_NOT_SUPPORTED; -} - -sw_error_t -hppe_rx_octet_count_good_high_rxoctghi_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union rx_octet_count_good_high_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_rx_octet_count_good_high_get(dev_id, index, ®_val); - *value = reg_val.bf.rxoctghi; - return ret; -} - -sw_error_t -hppe_rx_octet_count_good_high_rxoctghi_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - return SW_NOT_SUPPORTED; -} - -sw_error_t -hppe_rx_broadcast_frames_good_low_rxbcastglo_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union rx_broadcast_frames_good_low_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_rx_broadcast_frames_good_low_get(dev_id, index, ®_val); - *value = reg_val.bf.rxbcastglo; - return ret; -} - -sw_error_t -hppe_rx_broadcast_frames_good_low_rxbcastglo_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - return SW_NOT_SUPPORTED; -} - -sw_error_t -hppe_rx_broadcast_frames_good_high_rxbcastghi_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union rx_broadcast_frames_good_high_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_rx_broadcast_frames_good_high_get(dev_id, index, ®_val); - *value = reg_val.bf.rxbcastghi; - return ret; -} - -sw_error_t -hppe_rx_broadcast_frames_good_high_rxbcastghi_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - return SW_NOT_SUPPORTED; -} - -sw_error_t -hppe_rx_multicast_frames_good_low_rxmcastglo_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union rx_multicast_frames_good_low_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_rx_multicast_frames_good_low_get(dev_id, index, ®_val); - *value = reg_val.bf.rxmcastglo; - return ret; -} - -sw_error_t -hppe_rx_multicast_frames_good_low_rxmcastglo_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - return SW_NOT_SUPPORTED; -} - -sw_error_t -hppe_rx_multicast_frames_good_high_rxmcastghi_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union rx_multicast_frames_good_high_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_rx_multicast_frames_good_high_get(dev_id, index, ®_val); - *value = reg_val.bf.rxmcastghi; - return ret; -} - -sw_error_t -hppe_rx_multicast_frames_good_high_rxmcastghi_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - return SW_NOT_SUPPORTED; -} - -sw_error_t -hppe_rx_crc_error_frames_low_rxcrcerlo_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union rx_crc_error_frames_low_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_rx_crc_error_frames_low_get(dev_id, index, ®_val); - *value = reg_val.bf.rxcrcerlo; - return ret; -} - -sw_error_t -hppe_rx_crc_error_frames_low_rxcrcerlo_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - return SW_NOT_SUPPORTED; -} - -sw_error_t -hppe_rx_crc_error_frames_high_rxcrcerhi_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union rx_crc_error_frames_high_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_rx_crc_error_frames_high_get(dev_id, index, ®_val); - *value = reg_val.bf.rxcrcerhi; - return ret; -} - -sw_error_t -hppe_rx_crc_error_frames_high_rxcrcerhi_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - return SW_NOT_SUPPORTED; -} - -sw_error_t -hppe_rx_runt_error_frames_rxrunter_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union rx_runt_error_frames_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_rx_runt_error_frames_get(dev_id, index, ®_val); - *value = reg_val.bf.rxrunter; - return ret; -} - -sw_error_t -hppe_rx_runt_error_frames_rxrunter_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - return SW_NOT_SUPPORTED; -} - -sw_error_t -hppe_rx_jabber_error_frames_rxjaberer_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union rx_jabber_error_frames_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_rx_jabber_error_frames_get(dev_id, index, ®_val); - *value = reg_val.bf.rxjaberer; - return ret; -} - -sw_error_t -hppe_rx_jabber_error_frames_rxjaberer_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - return SW_NOT_SUPPORTED; -} - -sw_error_t -hppe_rx_undersize_frames_good_rxusizeg_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union rx_undersize_frames_good_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_rx_undersize_frames_good_get(dev_id, index, ®_val); - *value = reg_val.bf.rxusizeg; - return ret; -} - -sw_error_t -hppe_rx_undersize_frames_good_rxusizeg_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - return SW_NOT_SUPPORTED; -} - -sw_error_t -hppe_rx_oversize_frames_good_rxosizeg_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union rx_oversize_frames_good_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_rx_oversize_frames_good_get(dev_id, index, ®_val); - *value = reg_val.bf.rxosizeg; - return ret; -} - -sw_error_t -hppe_rx_oversize_frames_good_rxosizeg_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - return SW_NOT_SUPPORTED; -} - -sw_error_t -hppe_rx_64octets_frames_good_bad_low_rx64octgblo_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union rx_64octets_frames_good_bad_low_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_rx_64octets_frames_good_bad_low_get(dev_id, index, ®_val); - *value = reg_val.bf.rx64octgblo; - return ret; -} - -sw_error_t -hppe_rx_64octets_frames_good_bad_low_rx64octgblo_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - return SW_NOT_SUPPORTED; -} - -sw_error_t -hppe_rx_64octets_frames_good_bad_high_rx64octgbhi_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union rx_64octets_frames_good_bad_high_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_rx_64octets_frames_good_bad_high_get(dev_id, index, ®_val); - *value = reg_val.bf.rx64octgbhi; - return ret; -} - -sw_error_t -hppe_rx_64octets_frames_good_bad_high_rx64octgbhi_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - return SW_NOT_SUPPORTED; -} - -sw_error_t -hppe_rx_65to127octets_frames_good_bad_low_rx65_127octgblo_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union rx_65to127octets_frames_good_bad_low_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_rx_65to127octets_frames_good_bad_low_get(dev_id, index, ®_val); - *value = reg_val.bf.rx65_127octgblo; - return ret; -} - -sw_error_t -hppe_rx_65to127octets_frames_good_bad_low_rx65_127octgblo_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - return SW_NOT_SUPPORTED; -} - -sw_error_t -hppe_rx_65to127octets_frames_good_bad_high_rx65_127octgbhi_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union rx_65to127octets_frames_good_bad_high_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_rx_65to127octets_frames_good_bad_high_get(dev_id, index, ®_val); - *value = reg_val.bf.rx65_127octgbhi; - return ret; -} - -sw_error_t -hppe_rx_65to127octets_frames_good_bad_high_rx65_127octgbhi_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - return SW_NOT_SUPPORTED; -} - -sw_error_t -hppe_rx_128to255octets_frames_good_bad_low_rx128_255octgblo_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union rx_128to255octets_frames_good_bad_low_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_rx_128to255octets_frames_good_bad_low_get(dev_id, index, ®_val); - *value = reg_val.bf.rx128_255octgblo; - return ret; -} - -sw_error_t -hppe_rx_128to255octets_frames_good_bad_low_rx128_255octgblo_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - return SW_NOT_SUPPORTED; -} - -sw_error_t -hppe_rx_128to255octets_frames_good_bad_high_rx128_255octgbhi_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union rx_128to255octets_frames_good_bad_high_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_rx_128to255octets_frames_good_bad_high_get(dev_id, index, ®_val); - *value = reg_val.bf.rx128_255octgbhi; - return ret; -} - -sw_error_t -hppe_rx_128to255octets_frames_good_bad_high_rx128_255octgbhi_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - return SW_NOT_SUPPORTED; -} - -sw_error_t -hppe_rx_256to511octets_frames_good_bad_low_rx256_511octgblo_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union rx_256to511octets_frames_good_bad_low_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_rx_256to511octets_frames_good_bad_low_get(dev_id, index, ®_val); - *value = reg_val.bf.rx256_511octgblo; - return ret; -} - -sw_error_t -hppe_rx_256to511octets_frames_good_bad_low_rx256_511octgblo_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - return SW_NOT_SUPPORTED; -} - -sw_error_t -hppe_rx_256to511octets_frames_good_bad_high_rx256_511octgbhi_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union rx_256to511octets_frames_good_bad_high_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_rx_256to511octets_frames_good_bad_high_get(dev_id, index, ®_val); - *value = reg_val.bf.rx256_511octgbhi; - return ret; -} - -sw_error_t -hppe_rx_256to511octets_frames_good_bad_high_rx256_511octgbhi_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - return SW_NOT_SUPPORTED; -} - -sw_error_t -hppe_rx_512to1023octets_frames_good_bad_low_rx512_1023octgblo_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union rx_512to1023octets_frames_good_bad_low_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_rx_512to1023octets_frames_good_bad_low_get(dev_id, index, ®_val); - *value = reg_val.bf.rx512_1023octgblo; - return ret; -} - -sw_error_t -hppe_rx_512to1023octets_frames_good_bad_low_rx512_1023octgblo_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - return SW_NOT_SUPPORTED; -} - -sw_error_t -hppe_rx_512to1023octets_frames_good_bad_high_rx512_1023octgbhi_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union rx_512to1023octets_frames_good_bad_high_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_rx_512to1023octets_frames_good_bad_high_get(dev_id, index, ®_val); - *value = reg_val.bf.rx512_1023octgbhi; - return ret; -} - -sw_error_t -hppe_rx_512to1023octets_frames_good_bad_high_rx512_1023octgbhi_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - return SW_NOT_SUPPORTED; -} - -sw_error_t -hppe_rx_1024tomaxoctets_frames_good_bad_low_rx1024_maxgboctlo_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union rx_1024tomaxoctets_frames_good_bad_low_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_rx_1024tomaxoctets_frames_good_bad_low_get(dev_id, index, ®_val); - *value = reg_val.bf.rx1024_maxgboctlo; - return ret; -} - -sw_error_t -hppe_rx_1024tomaxoctets_frames_good_bad_low_rx1024_maxgboctlo_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - return SW_NOT_SUPPORTED; -} - -sw_error_t -hppe_rx_1024tomaxoctets_frames_good_bad_high_rx1024_maxgbocthi_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union rx_1024tomaxoctets_frames_good_bad_high_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_rx_1024tomaxoctets_frames_good_bad_high_get(dev_id, index, ®_val); - *value = reg_val.bf.rx1024_maxgbocthi; - return ret; -} - -sw_error_t -hppe_rx_1024tomaxoctets_frames_good_bad_high_rx1024_maxgbocthi_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - return SW_NOT_SUPPORTED; -} - -sw_error_t -hppe_rx_unicast_frames_good_low_rxucastglo_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union rx_unicast_frames_good_low_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_rx_unicast_frames_good_low_get(dev_id, index, ®_val); - *value = reg_val.bf.rxucastglo; - return ret; -} - -sw_error_t -hppe_rx_unicast_frames_good_low_rxucastglo_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - return SW_NOT_SUPPORTED; -} - -sw_error_t -hppe_rx_unicast_frames_good_high_rxucastghi_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union rx_unicast_frames_good_high_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_rx_unicast_frames_good_high_get(dev_id, index, ®_val); - *value = reg_val.bf.rxucastghi; - return ret; -} - -sw_error_t -hppe_rx_unicast_frames_good_high_rxucastghi_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - return SW_NOT_SUPPORTED; -} - -sw_error_t -hppe_rx_length_error_frames_low_rxlenerrlo_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union rx_length_error_frames_low_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_rx_length_error_frames_low_get(dev_id, index, ®_val); - *value = reg_val.bf.rxlenerrlo; - return ret; -} - -sw_error_t -hppe_rx_length_error_frames_low_rxlenerrlo_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - return SW_NOT_SUPPORTED; -} - -sw_error_t -hppe_rx_length_error_frames_high_rxlenerrhi_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union rx_length_error_frames_high_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_rx_length_error_frames_high_get(dev_id, index, ®_val); - *value = reg_val.bf.rxlenerrhi; - return ret; -} - -sw_error_t -hppe_rx_length_error_frames_high_rxlenerrhi_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - return SW_NOT_SUPPORTED; -} - -sw_error_t -hppe_rx_outofrange_frames_low_rxorangelo_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union rx_outofrange_frames_low_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_rx_outofrange_frames_low_get(dev_id, index, ®_val); - *value = reg_val.bf.rxorangelo; - return ret; -} - -sw_error_t -hppe_rx_outofrange_frames_low_rxorangelo_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - return SW_NOT_SUPPORTED; -} - -sw_error_t -hppe_rx_outofrange_frames_high_rxorangehi_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union rx_outofrange_frames_high_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_rx_outofrange_frames_high_get(dev_id, index, ®_val); - *value = reg_val.bf.rxorangehi; - return ret; -} - -sw_error_t -hppe_rx_outofrange_frames_high_rxorangehi_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - return SW_NOT_SUPPORTED; -} - -sw_error_t -hppe_rx_pause_frames_low_rxpauselo_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union rx_pause_frames_low_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_rx_pause_frames_low_get(dev_id, index, ®_val); - *value = reg_val.bf.rxpauselo; - return ret; -} - -sw_error_t -hppe_rx_pause_frames_low_rxpauselo_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - return SW_NOT_SUPPORTED; -} - -sw_error_t -hppe_rx_pause_frames_high_rxpausehi_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union rx_pause_frames_high_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_rx_pause_frames_high_get(dev_id, index, ®_val); - *value = reg_val.bf.rxpausehi; - return ret; -} - -sw_error_t -hppe_rx_pause_frames_high_rxpausehi_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - return SW_NOT_SUPPORTED; -} - -sw_error_t -hppe_rx_fifooverflow_frames_low_rxfovflo_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union rx_fifooverflow_frames_low_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_rx_fifooverflow_frames_low_get(dev_id, index, ®_val); - *value = reg_val.bf.rxfovflo; - return ret; -} - -sw_error_t -hppe_rx_fifooverflow_frames_low_rxfovflo_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - return SW_NOT_SUPPORTED; -} - -sw_error_t -hppe_rx_fifooverflow_frames_high_rxfovfhi_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union rx_fifooverflow_frames_high_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_rx_fifooverflow_frames_high_get(dev_id, index, ®_val); - *value = reg_val.bf.rxfovfhi; - return ret; -} - -sw_error_t -hppe_rx_fifooverflow_frames_high_rxfovfhi_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - return SW_NOT_SUPPORTED; -} - -sw_error_t -hppe_rx_vlan_frames_good_bad_low_rxvlangblo_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union rx_vlan_frames_good_bad_low_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_rx_vlan_frames_good_bad_low_get(dev_id, index, ®_val); - *value = reg_val.bf.rxvlangblo; - return ret; -} - -sw_error_t -hppe_rx_vlan_frames_good_bad_low_rxvlangblo_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - return SW_NOT_SUPPORTED; -} - -sw_error_t -hppe_rx_vlan_frames_good_bad_high_rxvlangbhi_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union rx_vlan_frames_good_bad_high_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_rx_vlan_frames_good_bad_high_get(dev_id, index, ®_val); - *value = reg_val.bf.rxvlangbhi; - return ret; -} - -sw_error_t -hppe_rx_vlan_frames_good_bad_high_rxvlangbhi_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - return SW_NOT_SUPPORTED; -} - -sw_error_t -hppe_rx_watchdog_error_frames_rxwdogerr_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union rx_watchdog_error_frames_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_rx_watchdog_error_frames_get(dev_id, index, ®_val); - *value = reg_val.bf.rxwdogerr; - return ret; -} - -sw_error_t -hppe_rx_watchdog_error_frames_rxwdogerr_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - return SW_NOT_SUPPORTED; -} - -sw_error_t -hppe_rx_lpi_usec_cntr_rxlpiusc_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union rx_lpi_usec_cntr_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_rx_lpi_usec_cntr_get(dev_id, index, ®_val); - *value = reg_val.bf.rxlpiusc; - return ret; -} - -sw_error_t -hppe_rx_lpi_usec_cntr_rxlpiusc_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - return SW_NOT_SUPPORTED; -} - -sw_error_t -hppe_rx_lpi_tran_cntr_rxlpitrc_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union rx_lpi_tran_cntr_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_rx_lpi_tran_cntr_get(dev_id, index, ®_val); - *value = reg_val.bf.rxlpitrc; - return ret; -} - -sw_error_t -hppe_rx_lpi_tran_cntr_rxlpitrc_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - return SW_NOT_SUPPORTED; -} - -sw_error_t -hppe_rx_discard_frame_count_good_bad_low_rxdfcntgblo_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union rx_discard_frame_count_good_bad_low_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_rx_discard_frame_count_good_bad_low_get(dev_id, index, ®_val); - *value = reg_val.bf.rxdfcntgblo; - return ret; -} - -sw_error_t -hppe_rx_discard_frame_count_good_bad_low_rxdfcntgblo_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - return SW_NOT_SUPPORTED; -} - -sw_error_t -hppe_rx_discard_frame_count_good_bad_high_rxdfcntgbhi_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union rx_discard_frame_count_good_bad_high_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_rx_discard_frame_count_good_bad_high_get(dev_id, index, ®_val); - *value = reg_val.bf.rxdfcntgbhi; - return ret; -} - -sw_error_t -hppe_rx_discard_frame_count_good_bad_high_rxdfcntgbhi_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - return SW_NOT_SUPPORTED; -} - -sw_error_t -hppe_rx_discard_octet_count_good_bad_low_rxdocntgblo_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union rx_discard_octet_count_good_bad_low_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_rx_discard_octet_count_good_bad_low_get(dev_id, index, ®_val); - *value = reg_val.bf.rxdocntgblo; - return ret; -} - -sw_error_t -hppe_rx_discard_octet_count_good_bad_low_rxdocntgblo_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - return SW_NOT_SUPPORTED; -} - -sw_error_t -hppe_rx_discard_octet_count_good_bad_high_rxdocntgbhi_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union rx_discard_octet_count_good_bad_high_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_rx_discard_octet_count_good_bad_high_get(dev_id, index, ®_val); - *value = reg_val.bf.rxdocntgbhi; - return ret; -} - -sw_error_t -hppe_rx_discard_octet_count_good_bad_high_rxdocntgbhi_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - return SW_NOT_SUPPORTED; -} - diff --git a/feeds/ipq807x/qca-ssdk/src/src/hsl/hppe/hppe_xgportctrl.c b/feeds/ipq807x/qca-ssdk/src/src/hsl/hppe/hppe_xgportctrl.c deleted file mode 100755 index 2caddc717..000000000 --- a/feeds/ipq807x/qca-ssdk/src/src/hsl/hppe/hppe_xgportctrl.c +++ /dev/null @@ -1,6074 +0,0 @@ -/* - * Copyright (c) 2016-2017, The Linux Foundation. All rights reserved. - * Permission to use, copy, modify, and/or distribute this software for - * any purpose with or without fee is hereby granted, provided that the - * above copyright notice and this permission notice appear in all copies. - * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES - * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR - * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES - * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN - * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT - * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. - */ - - -/** - * @defgroup - * @{ - */ -#include "sw.h" -#include "hsl.h" -#include "hppe_reg_access.h" -#include "hppe_xgportctrl_reg.h" -#include "hppe_xgportctrl.h" - -sw_error_t -hppe_mac_tx_configuration_get( - a_uint32_t dev_id, - a_uint32_t index, - union mac_tx_configuration_u *value) -{ - if (index >= MAC_TX_CONFIGURATION_MAX_ENTRY) - return SW_OUT_OF_RANGE; - return hppe_reg_get( - dev_id, - NSS_XGMAC_CSR_BASE_ADDR + MAC_TX_CONFIGURATION_ADDRESS + \ - index * MAC_TX_CONFIGURATION_INC, - &value->val); -} - -sw_error_t -hppe_mac_tx_configuration_set( - a_uint32_t dev_id, - a_uint32_t index, - union mac_tx_configuration_u *value) -{ - return hppe_reg_set( - dev_id, - NSS_XGMAC_CSR_BASE_ADDR + MAC_TX_CONFIGURATION_ADDRESS + \ - index * MAC_TX_CONFIGURATION_INC, - value->val); -} - -sw_error_t -hppe_mac_rx_configuration_get( - a_uint32_t dev_id, - a_uint32_t index, - union mac_rx_configuration_u *value) -{ - if (index >= MAC_RX_CONFIGURATION_MAX_ENTRY) - return SW_OUT_OF_RANGE; - return hppe_reg_get( - dev_id, - NSS_XGMAC_CSR_BASE_ADDR + MAC_RX_CONFIGURATION_ADDRESS + \ - index * MAC_RX_CONFIGURATION_INC, - &value->val); -} - -sw_error_t -hppe_mac_rx_configuration_set( - a_uint32_t dev_id, - a_uint32_t index, - union mac_rx_configuration_u *value) -{ - return hppe_reg_set( - dev_id, - NSS_XGMAC_CSR_BASE_ADDR + MAC_RX_CONFIGURATION_ADDRESS + \ - index * MAC_RX_CONFIGURATION_INC, - value->val); -} - -sw_error_t -hppe_mac_packet_filter_get( - a_uint32_t dev_id, - a_uint32_t index, - union mac_packet_filter_u *value) -{ - if (index >= MAC_PACKET_FILTER_MAX_ENTRY) - return SW_OUT_OF_RANGE; - return hppe_reg_get( - dev_id, - NSS_XGMAC_CSR_BASE_ADDR + MAC_PACKET_FILTER_ADDRESS + \ - index * MAC_PACKET_FILTER_INC, - &value->val); -} - -sw_error_t -hppe_mac_packet_filter_set( - a_uint32_t dev_id, - a_uint32_t index, - union mac_packet_filter_u *value) -{ - return hppe_reg_set( - dev_id, - NSS_XGMAC_CSR_BASE_ADDR + MAC_PACKET_FILTER_ADDRESS + \ - index * MAC_PACKET_FILTER_INC, - value->val); -} -#ifndef IN_PORTCONTROL_MINI - -sw_error_t -hppe_mac_watchdog_timeout_get( - a_uint32_t dev_id, - a_uint32_t index, - union mac_watchdog_timeout_u *value) -{ - if (index >= MAC_WATCHDOG_TIMEOUT_MAX_ENTRY) - return SW_OUT_OF_RANGE; - return hppe_reg_get( - dev_id, - NSS_XGMAC_CSR_BASE_ADDR + MAC_WATCHDOG_TIMEOUT_ADDRESS + \ - index * MAC_WATCHDOG_TIMEOUT_INC, - &value->val); -} - -sw_error_t -hppe_mac_watchdog_timeout_set( - a_uint32_t dev_id, - a_uint32_t index, - union mac_watchdog_timeout_u *value) -{ - return hppe_reg_set( - dev_id, - NSS_XGMAC_CSR_BASE_ADDR + MAC_WATCHDOG_TIMEOUT_ADDRESS + \ - index * MAC_WATCHDOG_TIMEOUT_INC, - value->val); -} - -sw_error_t -hppe_mac_vlan_tag_get( - a_uint32_t dev_id, - a_uint32_t index, - union mac_vlan_tag_u *value) -{ - if (index >= MAC_VLAN_TAG_MAX_ENTRY) - return SW_OUT_OF_RANGE; - return hppe_reg_get( - dev_id, - NSS_XGMAC_CSR_BASE_ADDR + MAC_VLAN_TAG_ADDRESS + \ - index * MAC_VLAN_TAG_INC, - &value->val); -} - -sw_error_t -hppe_mac_vlan_tag_set( - a_uint32_t dev_id, - a_uint32_t index, - union mac_vlan_tag_u *value) -{ - return hppe_reg_set( - dev_id, - NSS_XGMAC_CSR_BASE_ADDR + MAC_VLAN_TAG_ADDRESS + \ - index * MAC_VLAN_TAG_INC, - value->val); -} - -sw_error_t -hppe_mac_rx_eth_type_match_get( - a_uint32_t dev_id, - a_uint32_t index, - union mac_rx_eth_type_match_u *value) -{ - if (index >= MAC_RX_ETH_TYPE_MATCH_MAX_ENTRY) - return SW_OUT_OF_RANGE; - return hppe_reg_get( - dev_id, - NSS_XGMAC_CSR_BASE_ADDR + MAC_RX_ETH_TYPE_MATCH_ADDRESS + \ - index * MAC_RX_ETH_TYPE_MATCH_INC, - &value->val); -} - -sw_error_t -hppe_mac_rx_eth_type_match_set( - a_uint32_t dev_id, - a_uint32_t index, - union mac_rx_eth_type_match_u *value) -{ - return hppe_reg_set( - dev_id, - NSS_XGMAC_CSR_BASE_ADDR + MAC_RX_ETH_TYPE_MATCH_ADDRESS + \ - index * MAC_RX_ETH_TYPE_MATCH_INC, - value->val); -} -#endif -sw_error_t -hppe_mac_q0_tx_flow_ctrl_get( - a_uint32_t dev_id, - a_uint32_t index, - union mac_q0_tx_flow_ctrl_u *value) -{ - if (index >= MAC_Q0_TX_FLOW_CTRL_MAX_ENTRY) - return SW_OUT_OF_RANGE; - return hppe_reg_get( - dev_id, - NSS_XGMAC_CSR_BASE_ADDR + MAC_Q0_TX_FLOW_CTRL_ADDRESS + \ - index * MAC_Q0_TX_FLOW_CTRL_INC, - &value->val); -} - -sw_error_t -hppe_mac_q0_tx_flow_ctrl_set( - a_uint32_t dev_id, - a_uint32_t index, - union mac_q0_tx_flow_ctrl_u *value) -{ - return hppe_reg_set( - dev_id, - NSS_XGMAC_CSR_BASE_ADDR + MAC_Q0_TX_FLOW_CTRL_ADDRESS + \ - index * MAC_Q0_TX_FLOW_CTRL_INC, - value->val); -} - -sw_error_t -hppe_mac_rx_flow_ctrl_get( - a_uint32_t dev_id, - a_uint32_t index, - union mac_rx_flow_ctrl_u *value) -{ - if (index >= MAC_RX_FLOW_CTRL_MAX_ENTRY) - return SW_OUT_OF_RANGE; - return hppe_reg_get( - dev_id, - NSS_XGMAC_CSR_BASE_ADDR + MAC_RX_FLOW_CTRL_ADDRESS + \ - index * MAC_RX_FLOW_CTRL_INC, - &value->val); -} - -sw_error_t -hppe_mac_rx_flow_ctrl_set( - a_uint32_t dev_id, - a_uint32_t index, - union mac_rx_flow_ctrl_u *value) -{ - return hppe_reg_set( - dev_id, - NSS_XGMAC_CSR_BASE_ADDR + MAC_RX_FLOW_CTRL_ADDRESS + \ - index * MAC_RX_FLOW_CTRL_INC, - value->val); -} -#ifndef IN_PORTCONTROL_MINI - -sw_error_t -hppe_mac_interrupt_status_get( - a_uint32_t dev_id, - a_uint32_t index, - union mac_interrupt_status_u *value) -{ - if (index >= MAC_INTERRUPT_STATUS_MAX_ENTRY) - return SW_OUT_OF_RANGE; - return hppe_reg_get( - dev_id, - NSS_XGMAC_CSR_BASE_ADDR + MAC_INTERRUPT_STATUS_ADDRESS + \ - index * MAC_INTERRUPT_STATUS_INC, - &value->val); -} - -sw_error_t -hppe_mac_interrupt_status_set( - a_uint32_t dev_id, - a_uint32_t index, - union mac_interrupt_status_u *value) -{ - return SW_NOT_SUPPORTED; - -} - -sw_error_t -hppe_mac_interrupt_enable_get( - a_uint32_t dev_id, - a_uint32_t index, - union mac_interrupt_enable_u *value) -{ - if (index >= MAC_INTERRUPT_ENABLE_MAX_ENTRY) - return SW_OUT_OF_RANGE; - return hppe_reg_get( - dev_id, - NSS_XGMAC_CSR_BASE_ADDR + MAC_INTERRUPT_ENABLE_ADDRESS + \ - index * MAC_INTERRUPT_ENABLE_INC, - &value->val); -} - -sw_error_t -hppe_mac_interrupt_enable_set( - a_uint32_t dev_id, - a_uint32_t index, - union mac_interrupt_enable_u *value) -{ - return hppe_reg_set( - dev_id, - NSS_XGMAC_CSR_BASE_ADDR + MAC_INTERRUPT_ENABLE_ADDRESS + \ - index * MAC_INTERRUPT_ENABLE_INC, - value->val); -} - -sw_error_t -hppe_mac_rx_tx_status_get( - a_uint32_t dev_id, - a_uint32_t index, - union mac_rx_tx_status_u *value) -{ - if (index >= MAC_RX_TX_STATUS_MAX_ENTRY) - return SW_OUT_OF_RANGE; - return hppe_reg_get( - dev_id, - NSS_XGMAC_CSR_BASE_ADDR + MAC_RX_TX_STATUS_ADDRESS + \ - index * MAC_RX_TX_STATUS_INC, - &value->val); -} - -sw_error_t -hppe_mac_rx_tx_status_set( - a_uint32_t dev_id, - a_uint32_t index, - union mac_rx_tx_status_u *value) -{ - return SW_NOT_SUPPORTED; - -} - -sw_error_t -hppe_mac_lpi_control_status_get( - a_uint32_t dev_id, - a_uint32_t index, - union mac_lpi_control_status_u *value) -{ - if (index >= MAC_LPI_CONTROL_STATUS_MAX_ENTRY) - return SW_OUT_OF_RANGE; - return hppe_reg_get( - dev_id, - NSS_XGMAC_CSR_BASE_ADDR + MAC_LPI_CONTROL_STATUS_ADDRESS + \ - index * MAC_LPI_CONTROL_STATUS_INC, - &value->val); -} - -sw_error_t -hppe_mac_lpi_control_status_set( - a_uint32_t dev_id, - a_uint32_t index, - union mac_lpi_control_status_u *value) -{ - return hppe_reg_set( - dev_id, - NSS_XGMAC_CSR_BASE_ADDR + MAC_LPI_CONTROL_STATUS_ADDRESS + \ - index * MAC_LPI_CONTROL_STATUS_INC, - value->val); -} - -sw_error_t -hppe_mac_lpi_timers_control_get( - a_uint32_t dev_id, - a_uint32_t index, - union mac_lpi_timers_control_u *value) -{ - if (index >= MAC_LPI_TIMERS_CONTROL_MAX_ENTRY) - return SW_OUT_OF_RANGE; - return hppe_reg_get( - dev_id, - NSS_XGMAC_CSR_BASE_ADDR + MAC_LPI_TIMERS_CONTROL_ADDRESS + \ - index * MAC_LPI_TIMERS_CONTROL_INC, - &value->val); -} - -sw_error_t -hppe_mac_lpi_timers_control_set( - a_uint32_t dev_id, - a_uint32_t index, - union mac_lpi_timers_control_u *value) -{ - return hppe_reg_set( - dev_id, - NSS_XGMAC_CSR_BASE_ADDR + MAC_LPI_TIMERS_CONTROL_ADDRESS + \ - index * MAC_LPI_TIMERS_CONTROL_INC, - value->val); -} - -sw_error_t -hppe_mac_lpi_auto_entry_timer_get( - a_uint32_t dev_id, - a_uint32_t index, - union mac_lpi_auto_entry_timer_u *value) -{ - if (index >= MAC_LPI_AUTO_ENTRY_TIMER_MAX_ENTRY) - return SW_OUT_OF_RANGE; - return hppe_reg_get( - dev_id, - NSS_XGMAC_CSR_BASE_ADDR + MAC_LPI_AUTO_ENTRY_TIMER_ADDRESS + \ - index * MAC_LPI_AUTO_ENTRY_TIMER_INC, - &value->val); -} - -sw_error_t -hppe_mac_lpi_auto_entry_timer_set( - a_uint32_t dev_id, - a_uint32_t index, - union mac_lpi_auto_entry_timer_u *value) -{ - return hppe_reg_set( - dev_id, - NSS_XGMAC_CSR_BASE_ADDR + MAC_LPI_AUTO_ENTRY_TIMER_ADDRESS + \ - index * MAC_LPI_AUTO_ENTRY_TIMER_INC, - value->val); -} - -sw_error_t -hppe_mac_1us_tic_counter_get( - a_uint32_t dev_id, - a_uint32_t index, - union mac_1us_tic_counter_u *value) -{ - if (index >= MAC_1US_TIC_COUNTER_MAX_ENTRY) - return SW_OUT_OF_RANGE; - return hppe_reg_get( - dev_id, - NSS_XGMAC_CSR_BASE_ADDR + MAC_1US_TIC_COUNTER_ADDRESS + \ - index * MAC_1US_TIC_COUNTER_INC, - &value->val); -} - -sw_error_t -hppe_mac_1us_tic_counter_set( - a_uint32_t dev_id, - a_uint32_t index, - union mac_1us_tic_counter_u *value) -{ - return hppe_reg_set( - dev_id, - NSS_XGMAC_CSR_BASE_ADDR + MAC_1US_TIC_COUNTER_ADDRESS + \ - index * MAC_1US_TIC_COUNTER_INC, - value->val); -} - -sw_error_t -hppe_mac_address0_high_get( - a_uint32_t dev_id, - a_uint32_t index, - union mac_address0_high_u *value) -{ - if (index >= MAC_ADDRESS0_HIGH_MAX_ENTRY) - return SW_OUT_OF_RANGE; - return hppe_reg_get( - dev_id, - NSS_XGMAC_CSR_BASE_ADDR + MAC_ADDRESS0_HIGH_ADDRESS + \ - index * MAC_ADDRESS0_HIGH_INC, - &value->val); -} - -sw_error_t -hppe_mac_address0_high_set( - a_uint32_t dev_id, - a_uint32_t index, - union mac_address0_high_u *value) -{ - return hppe_reg_set( - dev_id, - NSS_XGMAC_CSR_BASE_ADDR + MAC_ADDRESS0_HIGH_ADDRESS + \ - index * MAC_ADDRESS0_HIGH_INC, - value->val); -} - -sw_error_t -hppe_mac_address0_low_get( - a_uint32_t dev_id, - a_uint32_t index, - union mac_address0_low_u *value) -{ - if (index >= MAC_ADDRESS0_LOW_MAX_ENTRY) - return SW_OUT_OF_RANGE; - return hppe_reg_get( - dev_id, - NSS_XGMAC_CSR_BASE_ADDR + MAC_ADDRESS0_LOW_ADDRESS + \ - index * MAC_ADDRESS0_LOW_INC, - &value->val); -} - -sw_error_t -hppe_mac_address0_low_set( - a_uint32_t dev_id, - a_uint32_t index, - union mac_address0_low_u *value) -{ - return hppe_reg_set( - dev_id, - NSS_XGMAC_CSR_BASE_ADDR + MAC_ADDRESS0_LOW_ADDRESS + \ - index * MAC_ADDRESS0_LOW_INC, - value->val); -} - -sw_error_t -hppe_mmc_receive_interrupt_get( - a_uint32_t dev_id, - a_uint32_t index, - union mmc_receive_interrupt_u *value) -{ - if (index >= MMC_RECEIVE_INTERRUPT_MAX_ENTRY) - return SW_OUT_OF_RANGE; - return hppe_reg_get( - dev_id, - NSS_XGMAC_CSR_BASE_ADDR + MMC_RECEIVE_INTERRUPT_ADDRESS + \ - index * MMC_RECEIVE_INTERRUPT_INC, - &value->val); -} - -sw_error_t -hppe_mmc_receive_interrupt_set( - a_uint32_t dev_id, - a_uint32_t index, - union mmc_receive_interrupt_u *value) -{ - return SW_NOT_SUPPORTED; -} - -sw_error_t -hppe_mmc_transmit_interrupt_get( - a_uint32_t dev_id, - a_uint32_t index, - union mmc_transmit_interrupt_u *value) -{ - if (index >= MMC_TRANSMIT_INTERRUPT_MAX_ENTRY) - return SW_OUT_OF_RANGE; - return hppe_reg_get( - dev_id, - NSS_XGMAC_CSR_BASE_ADDR + MMC_TRANSMIT_INTERRUPT_ADDRESS + \ - index * MMC_TRANSMIT_INTERRUPT_INC, - &value->val); -} - -sw_error_t -hppe_mmc_transmit_interrupt_set( - a_uint32_t dev_id, - a_uint32_t index, - union mmc_transmit_interrupt_u *value) -{ - return SW_NOT_SUPPORTED; -} - -sw_error_t -hppe_mmc_receive_interrupt_enable_get( - a_uint32_t dev_id, - a_uint32_t index, - union mmc_receive_interrupt_enable_u *value) -{ - if (index >= MMC_RECEIVE_INTERRUPT_ENABLE_MAX_ENTRY) - return SW_OUT_OF_RANGE; - return hppe_reg_get( - dev_id, - NSS_XGMAC_CSR_BASE_ADDR + MMC_RECEIVE_INTERRUPT_ENABLE_ADDRESS + \ - index * MMC_RECEIVE_INTERRUPT_ENABLE_INC, - &value->val); -} - -sw_error_t -hppe_mmc_receive_interrupt_enable_set( - a_uint32_t dev_id, - a_uint32_t index, - union mmc_receive_interrupt_enable_u *value) -{ - return hppe_reg_set( - dev_id, - NSS_XGMAC_CSR_BASE_ADDR + MMC_RECEIVE_INTERRUPT_ENABLE_ADDRESS + \ - index * MMC_RECEIVE_INTERRUPT_ENABLE_INC, - value->val); -} - -sw_error_t -hppe_mmc_transmit_interrupt_enable_get( - a_uint32_t dev_id, - a_uint32_t index, - union mmc_transmit_interrupt_enable_u *value) -{ - if (index >= MMC_TRANSMIT_INTERRUPT_ENABLE_MAX_ENTRY) - return SW_OUT_OF_RANGE; - return hppe_reg_get( - dev_id, - NSS_XGMAC_CSR_BASE_ADDR + MMC_TRANSMIT_INTERRUPT_ENABLE_ADDRESS + \ - index * MMC_TRANSMIT_INTERRUPT_ENABLE_INC, - &value->val); -} - -sw_error_t -hppe_mmc_transmit_interrupt_enable_set( - a_uint32_t dev_id, - a_uint32_t index, - union mmc_transmit_interrupt_enable_u *value) -{ - return hppe_reg_set( - dev_id, - NSS_XGMAC_CSR_BASE_ADDR + MMC_TRANSMIT_INTERRUPT_ENABLE_ADDRESS + \ - index * MMC_TRANSMIT_INTERRUPT_ENABLE_INC, - value->val); -} - -sw_error_t -hppe_mac_tx_configuration_vne_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union mac_tx_configuration_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_mac_tx_configuration_get(dev_id, index, ®_val); - *value = reg_val.bf.vne; - return ret; -} - -sw_error_t -hppe_mac_tx_configuration_vne_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - union mac_tx_configuration_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_mac_tx_configuration_get(dev_id, index, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.vne = value; - ret = hppe_mac_tx_configuration_set(dev_id, index, ®_val); - return ret; -} - -sw_error_t -hppe_mac_tx_configuration_ddic_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union mac_tx_configuration_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_mac_tx_configuration_get(dev_id, index, ®_val); - *value = reg_val.bf.ddic; - return ret; -} - -sw_error_t -hppe_mac_tx_configuration_ddic_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - union mac_tx_configuration_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_mac_tx_configuration_get(dev_id, index, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.ddic = value; - ret = hppe_mac_tx_configuration_set(dev_id, index, ®_val); - return ret; -} - -sw_error_t -hppe_mac_tx_configuration_te_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union mac_tx_configuration_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_mac_tx_configuration_get(dev_id, index, ®_val); - *value = reg_val.bf.te; - return ret; -} - -sw_error_t -hppe_mac_tx_configuration_te_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - union mac_tx_configuration_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_mac_tx_configuration_get(dev_id, index, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.te = value; - ret = hppe_mac_tx_configuration_set(dev_id, index, ®_val); - return ret; -} - -sw_error_t -hppe_mac_tx_configuration_ipg_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union mac_tx_configuration_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_mac_tx_configuration_get(dev_id, index, ®_val); - *value = reg_val.bf.ipg; - return ret; -} - -sw_error_t -hppe_mac_tx_configuration_ipg_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - union mac_tx_configuration_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_mac_tx_configuration_get(dev_id, index, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.ipg = value; - ret = hppe_mac_tx_configuration_set(dev_id, index, ®_val); - return ret; -} - -sw_error_t -hppe_mac_tx_configuration_ism_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union mac_tx_configuration_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_mac_tx_configuration_get(dev_id, index, ®_val); - *value = reg_val.bf.ism; - return ret; -} - -sw_error_t -hppe_mac_tx_configuration_ism_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - union mac_tx_configuration_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_mac_tx_configuration_get(dev_id, index, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.ism = value; - ret = hppe_mac_tx_configuration_set(dev_id, index, ®_val); - return ret; -} - -sw_error_t -hppe_mac_tx_configuration_ifp_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union mac_tx_configuration_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_mac_tx_configuration_get(dev_id, index, ®_val); - *value = reg_val.bf.ifp; - return ret; -} - -sw_error_t -hppe_mac_tx_configuration_ifp_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - union mac_tx_configuration_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_mac_tx_configuration_get(dev_id, index, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.ifp = value; - ret = hppe_mac_tx_configuration_set(dev_id, index, ®_val); - return ret; -} - -sw_error_t -hppe_mac_tx_configuration_sarc_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union mac_tx_configuration_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_mac_tx_configuration_get(dev_id, index, ®_val); - *value = reg_val.bf.sarc; - return ret; -} - -sw_error_t -hppe_mac_tx_configuration_sarc_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - union mac_tx_configuration_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_mac_tx_configuration_get(dev_id, index, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.sarc = value; - ret = hppe_mac_tx_configuration_set(dev_id, index, ®_val); - return ret; -} - -sw_error_t -hppe_mac_tx_configuration_isr_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union mac_tx_configuration_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_mac_tx_configuration_get(dev_id, index, ®_val); - *value = reg_val.bf.isr; - return ret; -} - -sw_error_t -hppe_mac_tx_configuration_isr_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - union mac_tx_configuration_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_mac_tx_configuration_get(dev_id, index, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.isr = value; - ret = hppe_mac_tx_configuration_set(dev_id, index, ®_val); - return ret; -} - -sw_error_t -hppe_mac_tx_configuration_ss_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union mac_tx_configuration_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_mac_tx_configuration_get(dev_id, index, ®_val); - *value = reg_val.bf.ss; - return ret; -} - -sw_error_t -hppe_mac_tx_configuration_ss_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - union mac_tx_configuration_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_mac_tx_configuration_get(dev_id, index, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.ss = value; - ret = hppe_mac_tx_configuration_set(dev_id, index, ®_val); - return ret; -} - -sw_error_t -hppe_mac_tx_configuration_g9991en_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union mac_tx_configuration_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_mac_tx_configuration_get(dev_id, index, ®_val); - *value = reg_val.bf.g9991en; - return ret; -} - -sw_error_t -hppe_mac_tx_configuration_g9991en_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - union mac_tx_configuration_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_mac_tx_configuration_get(dev_id, index, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.g9991en = value; - ret = hppe_mac_tx_configuration_set(dev_id, index, ®_val); - return ret; -} - -sw_error_t -hppe_mac_tx_configuration_uss_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union mac_tx_configuration_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_mac_tx_configuration_get(dev_id, index, ®_val); - *value = reg_val.bf.uss; - return ret; -} - -sw_error_t -hppe_mac_tx_configuration_uss_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - union mac_tx_configuration_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_mac_tx_configuration_get(dev_id, index, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.uss = value; - ret = hppe_mac_tx_configuration_set(dev_id, index, ®_val); - return ret; -} - -sw_error_t -hppe_mac_tx_configuration_vnm_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union mac_tx_configuration_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_mac_tx_configuration_get(dev_id, index, ®_val); - *value = reg_val.bf.vnm; - return ret; -} - -sw_error_t -hppe_mac_tx_configuration_vnm_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - union mac_tx_configuration_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_mac_tx_configuration_get(dev_id, index, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.vnm = value; - ret = hppe_mac_tx_configuration_set(dev_id, index, ®_val); - return ret; -} - -sw_error_t -hppe_mac_tx_configuration_jd_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union mac_tx_configuration_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_mac_tx_configuration_get(dev_id, index, ®_val); - *value = reg_val.bf.jd; - return ret; -} -#endif -sw_error_t -hppe_mac_tx_configuration_jd_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - union mac_tx_configuration_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_mac_tx_configuration_get(dev_id, index, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.jd = value; - ret = hppe_mac_tx_configuration_set(dev_id, index, ®_val); - return ret; -} -#ifndef IN_PORTCONTROL_MINI - -sw_error_t -hppe_mac_rx_configuration_lm_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union mac_rx_configuration_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_mac_rx_configuration_get(dev_id, index, ®_val); - *value = reg_val.bf.lm; - return ret; -} - -sw_error_t -hppe_mac_rx_configuration_lm_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - union mac_rx_configuration_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_mac_rx_configuration_get(dev_id, index, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.lm = value; - ret = hppe_mac_rx_configuration_set(dev_id, index, ®_val); - return ret; -} - -sw_error_t -hppe_mac_rx_configuration_je_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union mac_rx_configuration_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_mac_rx_configuration_get(dev_id, index, ®_val); - *value = reg_val.bf.je; - return ret; -} - -sw_error_t -hppe_mac_rx_configuration_je_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - union mac_rx_configuration_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_mac_rx_configuration_get(dev_id, index, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.je = value; - ret = hppe_mac_rx_configuration_set(dev_id, index, ®_val); - return ret; -} - -sw_error_t -hppe_mac_rx_configuration_arpen_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union mac_rx_configuration_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_mac_rx_configuration_get(dev_id, index, ®_val); - *value = reg_val.bf.arpen; - return ret; -} - -sw_error_t -hppe_mac_rx_configuration_arpen_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - union mac_rx_configuration_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_mac_rx_configuration_get(dev_id, index, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.arpen = value; - ret = hppe_mac_rx_configuration_set(dev_id, index, ®_val); - return ret; -} - -sw_error_t -hppe_mac_rx_configuration_elen_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union mac_rx_configuration_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_mac_rx_configuration_get(dev_id, index, ®_val); - *value = reg_val.bf.elen; - return ret; -} - -sw_error_t -hppe_mac_rx_configuration_elen_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - union mac_rx_configuration_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_mac_rx_configuration_get(dev_id, index, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.elen = value; - ret = hppe_mac_rx_configuration_set(dev_id, index, ®_val); - return ret; -} - -sw_error_t -hppe_mac_rx_configuration_gmpslce_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union mac_rx_configuration_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_mac_rx_configuration_get(dev_id, index, ®_val); - *value = reg_val.bf.gmpslce; - return ret; -} -#endif -sw_error_t -hppe_mac_rx_configuration_gmpslce_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - union mac_rx_configuration_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_mac_rx_configuration_get(dev_id, index, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.gmpslce = value; - ret = hppe_mac_rx_configuration_set(dev_id, index, ®_val); - return ret; -} -#ifndef IN_PORTCONTROL_MINI - -sw_error_t -hppe_mac_rx_configuration_hdsms_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union mac_rx_configuration_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_mac_rx_configuration_get(dev_id, index, ®_val); - *value = reg_val.bf.hdsms; - return ret; -} - -sw_error_t -hppe_mac_rx_configuration_hdsms_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - union mac_rx_configuration_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_mac_rx_configuration_get(dev_id, index, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.hdsms = value; - ret = hppe_mac_rx_configuration_set(dev_id, index, ®_val); - return ret; -} - -sw_error_t -hppe_mac_rx_configuration_spen_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union mac_rx_configuration_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_mac_rx_configuration_get(dev_id, index, ®_val); - *value = reg_val.bf.spen; - return ret; -} - -sw_error_t -hppe_mac_rx_configuration_spen_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - union mac_rx_configuration_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_mac_rx_configuration_get(dev_id, index, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.spen = value; - ret = hppe_mac_rx_configuration_set(dev_id, index, ®_val); - return ret; -} - -sw_error_t -hppe_mac_rx_configuration_usp_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union mac_rx_configuration_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_mac_rx_configuration_get(dev_id, index, ®_val); - *value = reg_val.bf.usp; - return ret; -} - -sw_error_t -hppe_mac_rx_configuration_usp_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - union mac_rx_configuration_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_mac_rx_configuration_get(dev_id, index, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.usp = value; - ret = hppe_mac_rx_configuration_set(dev_id, index, ®_val); - return ret; -} - -sw_error_t -hppe_mac_rx_configuration_ipc_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union mac_rx_configuration_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_mac_rx_configuration_get(dev_id, index, ®_val); - *value = reg_val.bf.ipc; - return ret; -} - -sw_error_t -hppe_mac_rx_configuration_ipc_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - union mac_rx_configuration_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_mac_rx_configuration_get(dev_id, index, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.ipc = value; - ret = hppe_mac_rx_configuration_set(dev_id, index, ®_val); - return ret; -} -#endif -sw_error_t -hppe_mac_rx_configuration_gpsl_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union mac_rx_configuration_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_mac_rx_configuration_get(dev_id, index, ®_val); - *value = reg_val.bf.gpsl; - return ret; -} - -sw_error_t -hppe_mac_rx_configuration_gpsl_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - union mac_rx_configuration_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_mac_rx_configuration_get(dev_id, index, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.gpsl = value; - ret = hppe_mac_rx_configuration_set(dev_id, index, ®_val); - return ret; -} -#ifndef IN_PORTCONTROL_MINI - -sw_error_t -hppe_mac_rx_configuration_re_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union mac_rx_configuration_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_mac_rx_configuration_get(dev_id, index, ®_val); - *value = reg_val.bf.re; - return ret; -} - -sw_error_t -hppe_mac_rx_configuration_re_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - union mac_rx_configuration_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_mac_rx_configuration_get(dev_id, index, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.re = value; - ret = hppe_mac_rx_configuration_set(dev_id, index, ®_val); - return ret; -} - -sw_error_t -hppe_mac_rx_configuration_cst_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union mac_rx_configuration_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_mac_rx_configuration_get(dev_id, index, ®_val); - *value = reg_val.bf.cst; - return ret; -} - -sw_error_t -hppe_mac_rx_configuration_cst_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - union mac_rx_configuration_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_mac_rx_configuration_get(dev_id, index, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.cst = value; - ret = hppe_mac_rx_configuration_set(dev_id, index, ®_val); - return ret; -} - -sw_error_t -hppe_mac_rx_configuration_dcrcc_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union mac_rx_configuration_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_mac_rx_configuration_get(dev_id, index, ®_val); - *value = reg_val.bf.dcrcc; - return ret; -} - -sw_error_t -hppe_mac_rx_configuration_dcrcc_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - union mac_rx_configuration_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_mac_rx_configuration_get(dev_id, index, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.dcrcc = value; - ret = hppe_mac_rx_configuration_set(dev_id, index, ®_val); - return ret; -} - -sw_error_t -hppe_mac_rx_configuration_wd_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union mac_rx_configuration_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_mac_rx_configuration_get(dev_id, index, ®_val); - *value = reg_val.bf.wd; - return ret; -} -#endif -sw_error_t -hppe_mac_rx_configuration_wd_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - union mac_rx_configuration_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_mac_rx_configuration_get(dev_id, index, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.wd = value; - ret = hppe_mac_rx_configuration_set(dev_id, index, ®_val); - return ret; -} -#ifndef IN_PORTCONTROL_MINI - -sw_error_t -hppe_mac_rx_configuration_acs_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union mac_rx_configuration_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_mac_rx_configuration_get(dev_id, index, ®_val); - *value = reg_val.bf.acs; - return ret; -} - -sw_error_t -hppe_mac_rx_configuration_acs_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - union mac_rx_configuration_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_mac_rx_configuration_get(dev_id, index, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.acs = value; - ret = hppe_mac_rx_configuration_set(dev_id, index, ®_val); - return ret; -} - -sw_error_t -hppe_mac_rx_configuration_s2kp_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union mac_rx_configuration_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_mac_rx_configuration_get(dev_id, index, ®_val); - *value = reg_val.bf.s2kp; - return ret; -} - -sw_error_t -hppe_mac_rx_configuration_s2kp_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - union mac_rx_configuration_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_mac_rx_configuration_get(dev_id, index, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.s2kp = value; - ret = hppe_mac_rx_configuration_set(dev_id, index, ®_val); - return ret; -} - -sw_error_t -hppe_mac_packet_filter_pcf_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union mac_packet_filter_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_mac_packet_filter_get(dev_id, index, ®_val); - *value = reg_val.bf.pcf; - return ret; -} -#endif -sw_error_t -hppe_mac_packet_filter_pcf_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - union mac_packet_filter_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_mac_packet_filter_get(dev_id, index, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.pcf = value; - ret = hppe_mac_packet_filter_set(dev_id, index, ®_val); - return ret; -} -#ifndef IN_PORTCONTROL_MINI - -sw_error_t -hppe_mac_packet_filter_hmc_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union mac_packet_filter_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_mac_packet_filter_get(dev_id, index, ®_val); - *value = reg_val.bf.hmc; - return ret; -} - -sw_error_t -hppe_mac_packet_filter_hmc_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - union mac_packet_filter_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_mac_packet_filter_get(dev_id, index, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.hmc = value; - ret = hppe_mac_packet_filter_set(dev_id, index, ®_val); - return ret; -} - -sw_error_t -hppe_mac_packet_filter_dntu_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union mac_packet_filter_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_mac_packet_filter_get(dev_id, index, ®_val); - *value = reg_val.bf.dntu; - return ret; -} - -sw_error_t -hppe_mac_packet_filter_dntu_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - union mac_packet_filter_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_mac_packet_filter_get(dev_id, index, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.dntu = value; - ret = hppe_mac_packet_filter_set(dev_id, index, ®_val); - return ret; -} - -sw_error_t -hppe_mac_packet_filter_saf_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union mac_packet_filter_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_mac_packet_filter_get(dev_id, index, ®_val); - *value = reg_val.bf.saf; - return ret; -} - -sw_error_t -hppe_mac_packet_filter_saf_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - union mac_packet_filter_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_mac_packet_filter_get(dev_id, index, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.saf = value; - ret = hppe_mac_packet_filter_set(dev_id, index, ®_val); - return ret; -} - -sw_error_t -hppe_mac_packet_filter_dbf_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union mac_packet_filter_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_mac_packet_filter_get(dev_id, index, ®_val); - *value = reg_val.bf.dbf; - return ret; -} - -sw_error_t -hppe_mac_packet_filter_dbf_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - union mac_packet_filter_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_mac_packet_filter_get(dev_id, index, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.dbf = value; - ret = hppe_mac_packet_filter_set(dev_id, index, ®_val); - return ret; -} - -sw_error_t -hppe_mac_packet_filter_huc_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union mac_packet_filter_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_mac_packet_filter_get(dev_id, index, ®_val); - *value = reg_val.bf.huc; - return ret; -} - -sw_error_t -hppe_mac_packet_filter_huc_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - union mac_packet_filter_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_mac_packet_filter_get(dev_id, index, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.huc = value; - ret = hppe_mac_packet_filter_set(dev_id, index, ®_val); - return ret; -} - -sw_error_t -hppe_mac_packet_filter_vtfe_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union mac_packet_filter_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_mac_packet_filter_get(dev_id, index, ®_val); - *value = reg_val.bf.vtfe; - return ret; -} - -sw_error_t -hppe_mac_packet_filter_vtfe_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - union mac_packet_filter_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_mac_packet_filter_get(dev_id, index, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.vtfe = value; - ret = hppe_mac_packet_filter_set(dev_id, index, ®_val); - return ret; -} - -sw_error_t -hppe_mac_packet_filter_daif_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union mac_packet_filter_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_mac_packet_filter_get(dev_id, index, ®_val); - *value = reg_val.bf.daif; - return ret; -} - -sw_error_t -hppe_mac_packet_filter_daif_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - union mac_packet_filter_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_mac_packet_filter_get(dev_id, index, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.daif = value; - ret = hppe_mac_packet_filter_set(dev_id, index, ®_val); - return ret; -} - -sw_error_t -hppe_mac_packet_filter_ra_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union mac_packet_filter_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_mac_packet_filter_get(dev_id, index, ®_val); - *value = reg_val.bf.ra; - return ret; -} - -sw_error_t -hppe_mac_packet_filter_ra_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - union mac_packet_filter_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_mac_packet_filter_get(dev_id, index, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.ra = value; - ret = hppe_mac_packet_filter_set(dev_id, index, ®_val); - return ret; -} - -sw_error_t -hppe_mac_packet_filter_hpf_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union mac_packet_filter_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_mac_packet_filter_get(dev_id, index, ®_val); - *value = reg_val.bf.hpf; - return ret; -} - -sw_error_t -hppe_mac_packet_filter_hpf_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - union mac_packet_filter_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_mac_packet_filter_get(dev_id, index, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.hpf = value; - ret = hppe_mac_packet_filter_set(dev_id, index, ®_val); - return ret; -} - -sw_error_t -hppe_mac_packet_filter_pm_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union mac_packet_filter_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_mac_packet_filter_get(dev_id, index, ®_val); - *value = reg_val.bf.pm; - return ret; -} - -sw_error_t -hppe_mac_packet_filter_pm_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - union mac_packet_filter_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_mac_packet_filter_get(dev_id, index, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.pm = value; - ret = hppe_mac_packet_filter_set(dev_id, index, ®_val); - return ret; -} - -sw_error_t -hppe_mac_packet_filter_vucc_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union mac_packet_filter_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_mac_packet_filter_get(dev_id, index, ®_val); - *value = reg_val.bf.vucc; - return ret; -} - -sw_error_t -hppe_mac_packet_filter_vucc_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - union mac_packet_filter_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_mac_packet_filter_get(dev_id, index, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.vucc = value; - ret = hppe_mac_packet_filter_set(dev_id, index, ®_val); - return ret; -} - -sw_error_t -hppe_mac_packet_filter_pr_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union mac_packet_filter_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_mac_packet_filter_get(dev_id, index, ®_val); - *value = reg_val.bf.pr; - return ret; -} -#endif -sw_error_t -hppe_mac_packet_filter_pr_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - union mac_packet_filter_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_mac_packet_filter_get(dev_id, index, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.pr = value; - ret = hppe_mac_packet_filter_set(dev_id, index, ®_val); - return ret; -} -#ifndef IN_PORTCONTROL_MINI - -sw_error_t -hppe_mac_packet_filter_ipfe_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union mac_packet_filter_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_mac_packet_filter_get(dev_id, index, ®_val); - *value = reg_val.bf.ipfe; - return ret; -} - -sw_error_t -hppe_mac_packet_filter_ipfe_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - union mac_packet_filter_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_mac_packet_filter_get(dev_id, index, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.ipfe = value; - ret = hppe_mac_packet_filter_set(dev_id, index, ®_val); - return ret; -} - -sw_error_t -hppe_mac_packet_filter_saif_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union mac_packet_filter_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_mac_packet_filter_get(dev_id, index, ®_val); - *value = reg_val.bf.saif; - return ret; -} - -sw_error_t -hppe_mac_packet_filter_saif_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - union mac_packet_filter_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_mac_packet_filter_get(dev_id, index, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.saif = value; - ret = hppe_mac_packet_filter_set(dev_id, index, ®_val); - return ret; -} - -sw_error_t -hppe_mac_watchdog_timeout_pwe_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union mac_watchdog_timeout_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_mac_watchdog_timeout_get(dev_id, index, ®_val); - *value = reg_val.bf.pwe; - return ret; -} - -sw_error_t -hppe_mac_watchdog_timeout_pwe_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - union mac_watchdog_timeout_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_mac_watchdog_timeout_get(dev_id, index, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.pwe = value; - ret = hppe_mac_watchdog_timeout_set(dev_id, index, ®_val); - return ret; -} - -sw_error_t -hppe_mac_watchdog_timeout_wto_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union mac_watchdog_timeout_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_mac_watchdog_timeout_get(dev_id, index, ®_val); - *value = reg_val.bf.wto; - return ret; -} - -sw_error_t -hppe_mac_watchdog_timeout_wto_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - union mac_watchdog_timeout_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_mac_watchdog_timeout_get(dev_id, index, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.wto = value; - ret = hppe_mac_watchdog_timeout_set(dev_id, index, ®_val); - return ret; -} - -sw_error_t -hppe_mac_vlan_tag_eivls_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union mac_vlan_tag_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_mac_vlan_tag_get(dev_id, index, ®_val); - *value = reg_val.bf.eivls; - return ret; -} - -sw_error_t -hppe_mac_vlan_tag_eivls_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - union mac_vlan_tag_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_mac_vlan_tag_get(dev_id, index, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.eivls = value; - ret = hppe_mac_vlan_tag_set(dev_id, index, ®_val); - return ret; -} - -sw_error_t -hppe_mac_vlan_tag_vthm_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union mac_vlan_tag_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_mac_vlan_tag_get(dev_id, index, ®_val); - *value = reg_val.bf.vthm; - return ret; -} - -sw_error_t -hppe_mac_vlan_tag_vthm_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - union mac_vlan_tag_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_mac_vlan_tag_get(dev_id, index, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.vthm = value; - ret = hppe_mac_vlan_tag_set(dev_id, index, ®_val); - return ret; -} - -sw_error_t -hppe_mac_vlan_tag_vl_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union mac_vlan_tag_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_mac_vlan_tag_get(dev_id, index, ®_val); - *value = reg_val.bf.vl; - return ret; -} - -sw_error_t -hppe_mac_vlan_tag_vl_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - union mac_vlan_tag_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_mac_vlan_tag_get(dev_id, index, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.vl = value; - ret = hppe_mac_vlan_tag_set(dev_id, index, ®_val); - return ret; -} - -sw_error_t -hppe_mac_vlan_tag_dovltc_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union mac_vlan_tag_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_mac_vlan_tag_get(dev_id, index, ®_val); - *value = reg_val.bf.dovltc; - return ret; -} - -sw_error_t -hppe_mac_vlan_tag_dovltc_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - union mac_vlan_tag_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_mac_vlan_tag_get(dev_id, index, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.dovltc = value; - ret = hppe_mac_vlan_tag_set(dev_id, index, ®_val); - return ret; -} - -sw_error_t -hppe_mac_vlan_tag_etv_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union mac_vlan_tag_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_mac_vlan_tag_get(dev_id, index, ®_val); - *value = reg_val.bf.etv; - return ret; -} - -sw_error_t -hppe_mac_vlan_tag_etv_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - union mac_vlan_tag_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_mac_vlan_tag_get(dev_id, index, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.etv = value; - ret = hppe_mac_vlan_tag_set(dev_id, index, ®_val); - return ret; -} - -sw_error_t -hppe_mac_vlan_tag_erivlt_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union mac_vlan_tag_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_mac_vlan_tag_get(dev_id, index, ®_val); - *value = reg_val.bf.erivlt; - return ret; -} - -sw_error_t -hppe_mac_vlan_tag_erivlt_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - union mac_vlan_tag_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_mac_vlan_tag_get(dev_id, index, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.erivlt = value; - ret = hppe_mac_vlan_tag_set(dev_id, index, ®_val); - return ret; -} - -sw_error_t -hppe_mac_vlan_tag_eivlrxs_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union mac_vlan_tag_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_mac_vlan_tag_get(dev_id, index, ®_val); - *value = reg_val.bf.eivlrxs; - return ret; -} - -sw_error_t -hppe_mac_vlan_tag_eivlrxs_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - union mac_vlan_tag_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_mac_vlan_tag_get(dev_id, index, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.eivlrxs = value; - ret = hppe_mac_vlan_tag_set(dev_id, index, ®_val); - return ret; -} - -sw_error_t -hppe_mac_vlan_tag_vtim_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union mac_vlan_tag_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_mac_vlan_tag_get(dev_id, index, ®_val); - *value = reg_val.bf.vtim; - return ret; -} - -sw_error_t -hppe_mac_vlan_tag_vtim_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - union mac_vlan_tag_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_mac_vlan_tag_get(dev_id, index, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.vtim = value; - ret = hppe_mac_vlan_tag_set(dev_id, index, ®_val); - return ret; -} - -sw_error_t -hppe_mac_vlan_tag_edvlp_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union mac_vlan_tag_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_mac_vlan_tag_get(dev_id, index, ®_val); - *value = reg_val.bf.edvlp; - return ret; -} - -sw_error_t -hppe_mac_vlan_tag_edvlp_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - union mac_vlan_tag_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_mac_vlan_tag_get(dev_id, index, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.edvlp = value; - ret = hppe_mac_vlan_tag_set(dev_id, index, ®_val); - return ret; -} - -sw_error_t -hppe_mac_vlan_tag_evlrxs_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union mac_vlan_tag_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_mac_vlan_tag_get(dev_id, index, ®_val); - *value = reg_val.bf.evlrxs; - return ret; -} - -sw_error_t -hppe_mac_vlan_tag_evlrxs_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - union mac_vlan_tag_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_mac_vlan_tag_get(dev_id, index, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.evlrxs = value; - ret = hppe_mac_vlan_tag_set(dev_id, index, ®_val); - return ret; -} - -sw_error_t -hppe_mac_vlan_tag_evls_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union mac_vlan_tag_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_mac_vlan_tag_get(dev_id, index, ®_val); - *value = reg_val.bf.evls; - return ret; -} - -sw_error_t -hppe_mac_vlan_tag_evls_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - union mac_vlan_tag_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_mac_vlan_tag_get(dev_id, index, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.evls = value; - ret = hppe_mac_vlan_tag_set(dev_id, index, ®_val); - return ret; -} - -sw_error_t -hppe_mac_vlan_tag_esvl_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union mac_vlan_tag_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_mac_vlan_tag_get(dev_id, index, ®_val); - *value = reg_val.bf.esvl; - return ret; -} - -sw_error_t -hppe_mac_vlan_tag_esvl_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - union mac_vlan_tag_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_mac_vlan_tag_get(dev_id, index, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.esvl = value; - ret = hppe_mac_vlan_tag_set(dev_id, index, ®_val); - return ret; -} - -sw_error_t -hppe_mac_vlan_tag_ersvlm_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union mac_vlan_tag_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_mac_vlan_tag_get(dev_id, index, ®_val); - *value = reg_val.bf.ersvlm; - return ret; -} - -sw_error_t -hppe_mac_vlan_tag_ersvlm_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - union mac_vlan_tag_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_mac_vlan_tag_get(dev_id, index, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.ersvlm = value; - ret = hppe_mac_vlan_tag_set(dev_id, index, ®_val); - return ret; -} - -sw_error_t -hppe_mac_rx_eth_type_match_et_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union mac_rx_eth_type_match_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_mac_rx_eth_type_match_get(dev_id, index, ®_val); - *value = reg_val.bf.et; - return ret; -} - -sw_error_t -hppe_mac_rx_eth_type_match_et_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - union mac_rx_eth_type_match_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_mac_rx_eth_type_match_get(dev_id, index, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.et = value; - ret = hppe_mac_rx_eth_type_match_set(dev_id, index, ®_val); - return ret; -} - -sw_error_t -hppe_mac_q0_tx_flow_ctrl_pt_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union mac_q0_tx_flow_ctrl_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_mac_q0_tx_flow_ctrl_get(dev_id, index, ®_val); - *value = reg_val.bf.pt; - return ret; -} - -sw_error_t -hppe_mac_q0_tx_flow_ctrl_pt_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - union mac_q0_tx_flow_ctrl_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_mac_q0_tx_flow_ctrl_get(dev_id, index, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.pt = value; - ret = hppe_mac_q0_tx_flow_ctrl_set(dev_id, index, ®_val); - return ret; -} - -sw_error_t -hppe_mac_q0_tx_flow_ctrl_plt_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union mac_q0_tx_flow_ctrl_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_mac_q0_tx_flow_ctrl_get(dev_id, index, ®_val); - *value = reg_val.bf.plt; - return ret; -} - -sw_error_t -hppe_mac_q0_tx_flow_ctrl_plt_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - union mac_q0_tx_flow_ctrl_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_mac_q0_tx_flow_ctrl_get(dev_id, index, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.plt = value; - ret = hppe_mac_q0_tx_flow_ctrl_set(dev_id, index, ®_val); - return ret; -} - -sw_error_t -hppe_mac_q0_tx_flow_ctrl_tfe_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union mac_q0_tx_flow_ctrl_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_mac_q0_tx_flow_ctrl_get(dev_id, index, ®_val); - *value = reg_val.bf.tfe; - return ret; -} - -sw_error_t -hppe_mac_q0_tx_flow_ctrl_tfe_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - union mac_q0_tx_flow_ctrl_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_mac_q0_tx_flow_ctrl_get(dev_id, index, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.tfe = value; - ret = hppe_mac_q0_tx_flow_ctrl_set(dev_id, index, ®_val); - return ret; -} - -sw_error_t -hppe_mac_q0_tx_flow_ctrl_fcb_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union mac_q0_tx_flow_ctrl_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_mac_q0_tx_flow_ctrl_get(dev_id, index, ®_val); - *value = reg_val.bf.fcb; - return ret; -} - -sw_error_t -hppe_mac_q0_tx_flow_ctrl_fcb_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - union mac_q0_tx_flow_ctrl_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_mac_q0_tx_flow_ctrl_get(dev_id, index, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.fcb = value; - ret = hppe_mac_q0_tx_flow_ctrl_set(dev_id, index, ®_val); - return ret; -} - -sw_error_t -hppe_mac_q0_tx_flow_ctrl_dapq_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union mac_q0_tx_flow_ctrl_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_mac_q0_tx_flow_ctrl_get(dev_id, index, ®_val); - *value = reg_val.bf.dapq; - return ret; -} - -sw_error_t -hppe_mac_q0_tx_flow_ctrl_dapq_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - union mac_q0_tx_flow_ctrl_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_mac_q0_tx_flow_ctrl_get(dev_id, index, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.dapq = value; - ret = hppe_mac_q0_tx_flow_ctrl_set(dev_id, index, ®_val); - return ret; -} - -sw_error_t -hppe_mac_rx_flow_ctrl_pfce_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union mac_rx_flow_ctrl_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_mac_rx_flow_ctrl_get(dev_id, index, ®_val); - *value = reg_val.bf.pfce; - return ret; -} - -sw_error_t -hppe_mac_rx_flow_ctrl_pfce_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - union mac_rx_flow_ctrl_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_mac_rx_flow_ctrl_get(dev_id, index, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.pfce = value; - ret = hppe_mac_rx_flow_ctrl_set(dev_id, index, ®_val); - return ret; -} - -sw_error_t -hppe_mac_rx_flow_ctrl_up_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union mac_rx_flow_ctrl_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_mac_rx_flow_ctrl_get(dev_id, index, ®_val); - *value = reg_val.bf.up; - return ret; -} - -sw_error_t -hppe_mac_rx_flow_ctrl_up_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - union mac_rx_flow_ctrl_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_mac_rx_flow_ctrl_get(dev_id, index, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.up = value; - ret = hppe_mac_rx_flow_ctrl_set(dev_id, index, ®_val); - return ret; -} - -sw_error_t -hppe_mac_rx_flow_ctrl_rfe_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union mac_rx_flow_ctrl_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_mac_rx_flow_ctrl_get(dev_id, index, ®_val); - *value = reg_val.bf.rfe; - return ret; -} - -sw_error_t -hppe_mac_rx_flow_ctrl_rfe_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - union mac_rx_flow_ctrl_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_mac_rx_flow_ctrl_get(dev_id, index, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.rfe = value; - ret = hppe_mac_rx_flow_ctrl_set(dev_id, index, ®_val); - return ret; -} - -sw_error_t -hppe_mac_interrupt_status_txesis_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union mac_interrupt_status_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_mac_interrupt_status_get(dev_id, index, ®_val); - *value = reg_val.bf.txesis; - return ret; -} - -sw_error_t -hppe_mac_interrupt_status_txesis_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - union mac_interrupt_status_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_mac_interrupt_status_get(dev_id, index, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.txesis = value; - ret = hppe_mac_interrupt_status_set(dev_id, index, ®_val); - return ret; -} - -sw_error_t -hppe_mac_interrupt_status_gpiis_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union mac_interrupt_status_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_mac_interrupt_status_get(dev_id, index, ®_val); - *value = reg_val.bf.gpiis; - return ret; -} - -sw_error_t -hppe_mac_interrupt_status_gpiis_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - union mac_interrupt_status_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_mac_interrupt_status_get(dev_id, index, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.gpiis = value; - ret = hppe_mac_interrupt_status_set(dev_id, index, ®_val); - return ret; -} - -sw_error_t -hppe_mac_interrupt_status_tsis_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union mac_interrupt_status_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_mac_interrupt_status_get(dev_id, index, ®_val); - *value = reg_val.bf.tsis; - return ret; -} - -sw_error_t -hppe_mac_interrupt_status_tsis_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - union mac_interrupt_status_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_mac_interrupt_status_get(dev_id, index, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.tsis = value; - ret = hppe_mac_interrupt_status_set(dev_id, index, ®_val); - return ret; -} - -sw_error_t -hppe_mac_interrupt_status_mmctxis_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union mac_interrupt_status_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_mac_interrupt_status_get(dev_id, index, ®_val); - *value = reg_val.bf.mmctxis; - return ret; -} - -sw_error_t -hppe_mac_interrupt_status_mmctxis_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - union mac_interrupt_status_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_mac_interrupt_status_get(dev_id, index, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.mmctxis = value; - ret = hppe_mac_interrupt_status_set(dev_id, index, ®_val); - return ret; -} - -sw_error_t -hppe_mac_interrupt_status_ls_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union mac_interrupt_status_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_mac_interrupt_status_get(dev_id, index, ®_val); - *value = reg_val.bf.ls; - return ret; -} - -sw_error_t -hppe_mac_interrupt_status_ls_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - union mac_interrupt_status_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_mac_interrupt_status_get(dev_id, index, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.ls = value; - ret = hppe_mac_interrupt_status_set(dev_id, index, ®_val); - return ret; -} - -sw_error_t -hppe_mac_interrupt_status_mmcrxis_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union mac_interrupt_status_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_mac_interrupt_status_get(dev_id, index, ®_val); - *value = reg_val.bf.mmcrxis; - return ret; -} - -sw_error_t -hppe_mac_interrupt_status_mmcrxis_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - union mac_interrupt_status_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_mac_interrupt_status_get(dev_id, index, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.mmcrxis = value; - ret = hppe_mac_interrupt_status_set(dev_id, index, ®_val); - return ret; -} - -sw_error_t -hppe_mac_interrupt_status_smi_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union mac_interrupt_status_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_mac_interrupt_status_get(dev_id, index, ®_val); - *value = reg_val.bf.smi; - return ret; -} - -sw_error_t -hppe_mac_interrupt_status_smi_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - union mac_interrupt_status_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_mac_interrupt_status_get(dev_id, index, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.smi = value; - ret = hppe_mac_interrupt_status_set(dev_id, index, ®_val); - return ret; -} - -sw_error_t -hppe_mac_interrupt_status_pmtis_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union mac_interrupt_status_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_mac_interrupt_status_get(dev_id, index, ®_val); - *value = reg_val.bf.pmtis; - return ret; -} - -sw_error_t -hppe_mac_interrupt_status_pmtis_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - union mac_interrupt_status_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_mac_interrupt_status_get(dev_id, index, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.pmtis = value; - ret = hppe_mac_interrupt_status_set(dev_id, index, ®_val); - return ret; -} - -sw_error_t -hppe_mac_interrupt_status_rxesis_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union mac_interrupt_status_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_mac_interrupt_status_get(dev_id, index, ®_val); - *value = reg_val.bf.rxesis; - return ret; -} - -sw_error_t -hppe_mac_interrupt_status_rxesis_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - union mac_interrupt_status_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_mac_interrupt_status_get(dev_id, index, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.rxesis = value; - ret = hppe_mac_interrupt_status_set(dev_id, index, ®_val); - return ret; -} - -sw_error_t -hppe_mac_interrupt_status_lpiis_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union mac_interrupt_status_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_mac_interrupt_status_get(dev_id, index, ®_val); - *value = reg_val.bf.lpiis; - return ret; -} - -sw_error_t -hppe_mac_interrupt_status_lpiis_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - union mac_interrupt_status_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_mac_interrupt_status_get(dev_id, index, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.lpiis = value; - ret = hppe_mac_interrupt_status_set(dev_id, index, ®_val); - return ret; -} - -sw_error_t -hppe_mac_interrupt_enable_tsie_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union mac_interrupt_enable_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_mac_interrupt_enable_get(dev_id, index, ®_val); - *value = reg_val.bf.tsie; - return ret; -} - -sw_error_t -hppe_mac_interrupt_enable_tsie_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - return SW_NOT_SUPPORTED; -} - -sw_error_t -hppe_mac_interrupt_enable_lpiie_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union mac_interrupt_enable_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_mac_interrupt_enable_get(dev_id, index, ®_val); - *value = reg_val.bf.lpiie; - return ret; -} - -sw_error_t -hppe_mac_interrupt_enable_lpiie_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - return SW_NOT_SUPPORTED; -} - -sw_error_t -hppe_mac_interrupt_enable_txesie_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union mac_interrupt_enable_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_mac_interrupt_enable_get(dev_id, index, ®_val); - *value = reg_val.bf.txesie; - return ret; -} - -sw_error_t -hppe_mac_interrupt_enable_txesie_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - return SW_NOT_SUPPORTED; -} - -sw_error_t -hppe_mac_interrupt_enable_pmtie_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union mac_interrupt_enable_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_mac_interrupt_enable_get(dev_id, index, ®_val); - *value = reg_val.bf.pmtie; - return ret; -} - -sw_error_t -hppe_mac_interrupt_enable_pmtie_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - return SW_NOT_SUPPORTED; -} - -sw_error_t -hppe_mac_interrupt_enable_rxesie_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union mac_interrupt_enable_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_mac_interrupt_enable_get(dev_id, index, ®_val); - *value = reg_val.bf.rxesie; - return ret; -} - -sw_error_t -hppe_mac_interrupt_enable_rxesie_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - return SW_NOT_SUPPORTED; -} - -sw_error_t -hppe_mac_rx_tx_status_tjt_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union mac_rx_tx_status_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_mac_rx_tx_status_get(dev_id, index, ®_val); - *value = reg_val.bf.tjt; - return ret; -} - -sw_error_t -hppe_mac_rx_tx_status_tjt_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - union mac_rx_tx_status_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_mac_rx_tx_status_get(dev_id, index, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.tjt = value; - ret = hppe_mac_rx_tx_status_set(dev_id, index, ®_val); - return ret; -} - -sw_error_t -hppe_mac_rx_tx_status_rwt_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union mac_rx_tx_status_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_mac_rx_tx_status_get(dev_id, index, ®_val); - *value = reg_val.bf.rwt; - return ret; -} - -sw_error_t -hppe_mac_rx_tx_status_rwt_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - union mac_rx_tx_status_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_mac_rx_tx_status_get(dev_id, index, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.rwt = value; - ret = hppe_mac_rx_tx_status_set(dev_id, index, ®_val); - return ret; -} - -sw_error_t -hppe_mac_lpi_control_status_tlpien_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union mac_lpi_control_status_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_mac_lpi_control_status_get(dev_id, index, ®_val); - *value = reg_val.bf.tlpien; - return ret; -} - -sw_error_t -hppe_mac_lpi_control_status_tlpien_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - union mac_lpi_control_status_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_mac_lpi_control_status_get(dev_id, index, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.tlpien = value; - ret = hppe_mac_lpi_control_status_set(dev_id, index, ®_val); - return ret; -} - -sw_error_t -hppe_mac_lpi_control_status_lpitcse_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union mac_lpi_control_status_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_mac_lpi_control_status_get(dev_id, index, ®_val); - *value = reg_val.bf.lpitcse; - return ret; -} - -sw_error_t -hppe_mac_lpi_control_status_lpitcse_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - union mac_lpi_control_status_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_mac_lpi_control_status_get(dev_id, index, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.lpitcse = value; - ret = hppe_mac_lpi_control_status_set(dev_id, index, ®_val); - return ret; -} - -sw_error_t -hppe_mac_lpi_control_status_rxrstp_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union mac_lpi_control_status_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_mac_lpi_control_status_get(dev_id, index, ®_val); - *value = reg_val.bf.rxrstp; - return ret; -} - -sw_error_t -hppe_mac_lpi_control_status_rxrstp_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - union mac_lpi_control_status_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_mac_lpi_control_status_get(dev_id, index, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.rxrstp = value; - ret = hppe_mac_lpi_control_status_set(dev_id, index, ®_val); - return ret; -} - -sw_error_t -hppe_mac_lpi_control_status_lpite_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union mac_lpi_control_status_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_mac_lpi_control_status_get(dev_id, index, ®_val); - *value = reg_val.bf.lpite; - return ret; -} - -sw_error_t -hppe_mac_lpi_control_status_lpite_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - union mac_lpi_control_status_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_mac_lpi_control_status_get(dev_id, index, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.lpite = value; - ret = hppe_mac_lpi_control_status_set(dev_id, index, ®_val); - return ret; -} - -sw_error_t -hppe_mac_lpi_control_status_pls_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union mac_lpi_control_status_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_mac_lpi_control_status_get(dev_id, index, ®_val); - *value = reg_val.bf.pls; - return ret; -} - -sw_error_t -hppe_mac_lpi_control_status_pls_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - union mac_lpi_control_status_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_mac_lpi_control_status_get(dev_id, index, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.pls = value; - ret = hppe_mac_lpi_control_status_set(dev_id, index, ®_val); - return ret; -} - -sw_error_t -hppe_mac_lpi_control_status_rlpiex_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union mac_lpi_control_status_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_mac_lpi_control_status_get(dev_id, index, ®_val); - *value = reg_val.bf.rlpiex; - return ret; -} - -sw_error_t -hppe_mac_lpi_control_status_rlpiex_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - union mac_lpi_control_status_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_mac_lpi_control_status_get(dev_id, index, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.rlpiex = value; - ret = hppe_mac_lpi_control_status_set(dev_id, index, ®_val); - return ret; -} - -sw_error_t -hppe_mac_lpi_control_status_rlpien_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union mac_lpi_control_status_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_mac_lpi_control_status_get(dev_id, index, ®_val); - *value = reg_val.bf.rlpien; - return ret; -} - -sw_error_t -hppe_mac_lpi_control_status_rlpien_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - union mac_lpi_control_status_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_mac_lpi_control_status_get(dev_id, index, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.rlpien = value; - ret = hppe_mac_lpi_control_status_set(dev_id, index, ®_val); - return ret; -} - -sw_error_t -hppe_mac_lpi_control_status_rlpist_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union mac_lpi_control_status_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_mac_lpi_control_status_get(dev_id, index, ®_val); - *value = reg_val.bf.rlpist; - return ret; -} - -sw_error_t -hppe_mac_lpi_control_status_rlpist_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - union mac_lpi_control_status_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_mac_lpi_control_status_get(dev_id, index, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.rlpist = value; - ret = hppe_mac_lpi_control_status_set(dev_id, index, ®_val); - return ret; -} - -sw_error_t -hppe_mac_lpi_control_status_tlpist_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union mac_lpi_control_status_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_mac_lpi_control_status_get(dev_id, index, ®_val); - *value = reg_val.bf.tlpist; - return ret; -} - -sw_error_t -hppe_mac_lpi_control_status_tlpist_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - union mac_lpi_control_status_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_mac_lpi_control_status_get(dev_id, index, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.tlpist = value; - ret = hppe_mac_lpi_control_status_set(dev_id, index, ®_val); - return ret; -} - -sw_error_t -hppe_mac_lpi_control_status_txrstp_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union mac_lpi_control_status_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_mac_lpi_control_status_get(dev_id, index, ®_val); - *value = reg_val.bf.txrstp; - return ret; -} - -sw_error_t -hppe_mac_lpi_control_status_txrstp_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - union mac_lpi_control_status_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_mac_lpi_control_status_get(dev_id, index, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.txrstp = value; - ret = hppe_mac_lpi_control_status_set(dev_id, index, ®_val); - return ret; -} - -sw_error_t -hppe_mac_lpi_control_status_plsdis_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union mac_lpi_control_status_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_mac_lpi_control_status_get(dev_id, index, ®_val); - *value = reg_val.bf.plsdis; - return ret; -} - -sw_error_t -hppe_mac_lpi_control_status_plsdis_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - union mac_lpi_control_status_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_mac_lpi_control_status_get(dev_id, index, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.plsdis = value; - ret = hppe_mac_lpi_control_status_set(dev_id, index, ®_val); - return ret; -} - -sw_error_t -hppe_mac_lpi_control_status_lpitxa_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union mac_lpi_control_status_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_mac_lpi_control_status_get(dev_id, index, ®_val); - *value = reg_val.bf.lpitxa; - return ret; -} - -sw_error_t -hppe_mac_lpi_control_status_lpitxa_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - union mac_lpi_control_status_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_mac_lpi_control_status_get(dev_id, index, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.lpitxa = value; - ret = hppe_mac_lpi_control_status_set(dev_id, index, ®_val); - return ret; -} - -sw_error_t -hppe_mac_lpi_control_status_tlpiex_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union mac_lpi_control_status_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_mac_lpi_control_status_get(dev_id, index, ®_val); - *value = reg_val.bf.tlpiex; - return ret; -} - -sw_error_t -hppe_mac_lpi_control_status_tlpiex_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - union mac_lpi_control_status_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_mac_lpi_control_status_get(dev_id, index, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.tlpiex = value; - ret = hppe_mac_lpi_control_status_set(dev_id, index, ®_val); - return ret; -} - -sw_error_t -hppe_mac_lpi_control_status_lpitxen_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union mac_lpi_control_status_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_mac_lpi_control_status_get(dev_id, index, ®_val); - *value = reg_val.bf.lpitxen; - return ret; -} - -sw_error_t -hppe_mac_lpi_control_status_lpitxen_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - union mac_lpi_control_status_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_mac_lpi_control_status_get(dev_id, index, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.lpitxen = value; - ret = hppe_mac_lpi_control_status_set(dev_id, index, ®_val); - return ret; -} - -sw_error_t -hppe_mac_lpi_timers_control_lst_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union mac_lpi_timers_control_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_mac_lpi_timers_control_get(dev_id, index, ®_val); - *value = reg_val.bf.lst; - return ret; -} - -sw_error_t -hppe_mac_lpi_timers_control_lst_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - return SW_NOT_SUPPORTED; -} - -sw_error_t -hppe_mac_lpi_timers_control_twt_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union mac_lpi_timers_control_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_mac_lpi_timers_control_get(dev_id, index, ®_val); - *value = reg_val.bf.twt; - return ret; -} - -sw_error_t -hppe_mac_lpi_timers_control_twt_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - return SW_NOT_SUPPORTED; -} - -sw_error_t -hppe_mac_lpi_auto_entry_timer_lpiet_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union mac_lpi_auto_entry_timer_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_mac_lpi_auto_entry_timer_get(dev_id, index, ®_val); - *value = reg_val.bf.lpiet; - return ret; -} - -sw_error_t -hppe_mac_lpi_auto_entry_timer_lpiet_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - return SW_NOT_SUPPORTED; -} - -sw_error_t -hppe_mac_1us_tic_counter_tic_1us_cntr_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union mac_1us_tic_counter_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_mac_1us_tic_counter_get(dev_id, index, ®_val); - *value = reg_val.bf.tic_1us_cntr; - return ret; -} - -sw_error_t -hppe_mac_1us_tic_counter_tic_1us_cntr_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - return SW_NOT_SUPPORTED; -} - -sw_error_t -hppe_mac_address0_high_addrhi_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union mac_address0_high_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_mac_address0_high_get(dev_id, index, ®_val); - *value = reg_val.bf.addrhi; - return ret; -} - -sw_error_t -hppe_mac_address0_high_addrhi_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - return SW_NOT_SUPPORTED; -} - -sw_error_t -hppe_mac_address0_high_ae_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union mac_address0_high_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_mac_address0_high_get(dev_id, index, ®_val); - *value = reg_val.bf.ae; - return ret; -} - -sw_error_t -hppe_mac_address0_high_ae_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - return SW_NOT_SUPPORTED; -} - -sw_error_t -hppe_mac_address0_high_dcs_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union mac_address0_high_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_mac_address0_high_get(dev_id, index, ®_val); - *value = reg_val.bf.dcs; - return ret; -} - -sw_error_t -hppe_mac_address0_high_dcs_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - return SW_NOT_SUPPORTED; -} - -sw_error_t -hppe_mac_address0_low_addrlo_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union mac_address0_low_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_mac_address0_low_get(dev_id, index, ®_val); - *value = reg_val.bf.addrlo; - return ret; -} - -sw_error_t -hppe_mac_address0_low_addrlo_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - return SW_NOT_SUPPORTED; -} - -sw_error_t -hppe_mmc_receive_interrupt_rxorangefis_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union mmc_receive_interrupt_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_mmc_receive_interrupt_get(dev_id, index, ®_val); - *value = reg_val.bf.rxorangefis; - return ret; -} - -sw_error_t -hppe_mmc_receive_interrupt_rxorangefis_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - return SW_NOT_SUPPORTED; -} - -sw_error_t -hppe_mmc_receive_interrupt_rxlenerfis_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union mmc_receive_interrupt_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_mmc_receive_interrupt_get(dev_id, index, ®_val); - *value = reg_val.bf.rxlenerfis; - return ret; -} - -sw_error_t -hppe_mmc_receive_interrupt_rxlenerfis_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - return SW_NOT_SUPPORTED; -} - -sw_error_t -hppe_mmc_receive_interrupt_rx65t127octgbfis_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union mmc_receive_interrupt_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_mmc_receive_interrupt_get(dev_id, index, ®_val); - *value = reg_val.bf.rx65t127octgbfis; - return ret; -} - -sw_error_t -hppe_mmc_receive_interrupt_rx65t127octgbfis_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - return SW_NOT_SUPPORTED; -} - -sw_error_t -hppe_mmc_receive_interrupt_rxprmmcis_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union mmc_receive_interrupt_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_mmc_receive_interrupt_get(dev_id, index, ®_val); - *value = reg_val.bf.rxprmmcis; - return ret; -} - -sw_error_t -hppe_mmc_receive_interrupt_rxprmmcis_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - return SW_NOT_SUPPORTED; -} - -sw_error_t -hppe_mmc_receive_interrupt_rx512t1023octgbfis_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union mmc_receive_interrupt_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_mmc_receive_interrupt_get(dev_id, index, ®_val); - *value = reg_val.bf.rx512t1023octgbfis; - return ret; -} - -sw_error_t -hppe_mmc_receive_interrupt_rx512t1023octgbfis_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - return SW_NOT_SUPPORTED; -} - -sw_error_t -hppe_mmc_receive_interrupt_rxgboctis_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union mmc_receive_interrupt_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_mmc_receive_interrupt_get(dev_id, index, ®_val); - *value = reg_val.bf.rxgboctis; - return ret; -} - -sw_error_t -hppe_mmc_receive_interrupt_rxgboctis_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - return SW_NOT_SUPPORTED; -} - -sw_error_t -hppe_mmc_receive_interrupt_rxlpiuscis_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union mmc_receive_interrupt_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_mmc_receive_interrupt_get(dev_id, index, ®_val); - *value = reg_val.bf.rxlpiuscis; - return ret; -} - -sw_error_t -hppe_mmc_receive_interrupt_rxlpiuscis_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - return SW_NOT_SUPPORTED; -} - -sw_error_t -hppe_mmc_receive_interrupt_rxjaberfis_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union mmc_receive_interrupt_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_mmc_receive_interrupt_get(dev_id, index, ®_val); - *value = reg_val.bf.rxjaberfis; - return ret; -} - -sw_error_t -hppe_mmc_receive_interrupt_rxjaberfis_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - return SW_NOT_SUPPORTED; -} - -sw_error_t -hppe_mmc_receive_interrupt_rxvlangbfis_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union mmc_receive_interrupt_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_mmc_receive_interrupt_get(dev_id, index, ®_val); - *value = reg_val.bf.rxvlangbfis; - return ret; -} - -sw_error_t -hppe_mmc_receive_interrupt_rxvlangbfis_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - return SW_NOT_SUPPORTED; -} - -sw_error_t -hppe_mmc_receive_interrupt_rxpausfis_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union mmc_receive_interrupt_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_mmc_receive_interrupt_get(dev_id, index, ®_val); - *value = reg_val.bf.rxpausfis; - return ret; -} - -sw_error_t -hppe_mmc_receive_interrupt_rxpausfis_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - return SW_NOT_SUPPORTED; -} - -sw_error_t -hppe_mmc_receive_interrupt_rxcrcerfis_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union mmc_receive_interrupt_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_mmc_receive_interrupt_get(dev_id, index, ®_val); - *value = reg_val.bf.rxcrcerfis; - return ret; -} - -sw_error_t -hppe_mmc_receive_interrupt_rxcrcerfis_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - return SW_NOT_SUPPORTED; -} - -sw_error_t -hppe_mmc_receive_interrupt_rxdisocgbis_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union mmc_receive_interrupt_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_mmc_receive_interrupt_get(dev_id, index, ®_val); - *value = reg_val.bf.rxdisocgbis; - return ret; -} - -sw_error_t -hppe_mmc_receive_interrupt_rxdisocgbis_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - return SW_NOT_SUPPORTED; -} - -sw_error_t -hppe_mmc_receive_interrupt_rxwdogfis_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union mmc_receive_interrupt_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_mmc_receive_interrupt_get(dev_id, index, ®_val); - *value = reg_val.bf.rxwdogfis; - return ret; -} - -sw_error_t -hppe_mmc_receive_interrupt_rxwdogfis_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - return SW_NOT_SUPPORTED; -} - -sw_error_t -hppe_mmc_receive_interrupt_rx128t255octgbfis_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union mmc_receive_interrupt_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_mmc_receive_interrupt_get(dev_id, index, ®_val); - *value = reg_val.bf.rx128t255octgbfis; - return ret; -} - -sw_error_t -hppe_mmc_receive_interrupt_rx128t255octgbfis_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - return SW_NOT_SUPPORTED; -} - -sw_error_t -hppe_mmc_receive_interrupt_rxdisfcgbis_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union mmc_receive_interrupt_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_mmc_receive_interrupt_get(dev_id, index, ®_val); - *value = reg_val.bf.rxdisfcgbis; - return ret; -} - -sw_error_t -hppe_mmc_receive_interrupt_rxdisfcgbis_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - return SW_NOT_SUPPORTED; -} - -sw_error_t -hppe_mmc_receive_interrupt_rxosizegfis_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union mmc_receive_interrupt_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_mmc_receive_interrupt_get(dev_id, index, ®_val); - *value = reg_val.bf.rxosizegfis; - return ret; -} - -sw_error_t -hppe_mmc_receive_interrupt_rxosizegfis_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - return SW_NOT_SUPPORTED; -} - -sw_error_t -hppe_mmc_receive_interrupt_rx1024tmaxoctgbfis_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union mmc_receive_interrupt_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_mmc_receive_interrupt_get(dev_id, index, ®_val); - *value = reg_val.bf.rx1024tmaxoctgbfis; - return ret; -} - -sw_error_t -hppe_mmc_receive_interrupt_rx1024tmaxoctgbfis_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - return SW_NOT_SUPPORTED; -} - -sw_error_t -hppe_mmc_receive_interrupt_rxruntfis_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union mmc_receive_interrupt_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_mmc_receive_interrupt_get(dev_id, index, ®_val); - *value = reg_val.bf.rxruntfis; - return ret; -} - -sw_error_t -hppe_mmc_receive_interrupt_rxruntfis_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - return SW_NOT_SUPPORTED; -} - -sw_error_t -hppe_mmc_receive_interrupt_rxmcgfis_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union mmc_receive_interrupt_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_mmc_receive_interrupt_get(dev_id, index, ®_val); - *value = reg_val.bf.rxmcgfis; - return ret; -} - -sw_error_t -hppe_mmc_receive_interrupt_rxmcgfis_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - return SW_NOT_SUPPORTED; -} - -sw_error_t -hppe_mmc_receive_interrupt_rx256t511octgbfis_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union mmc_receive_interrupt_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_mmc_receive_interrupt_get(dev_id, index, ®_val); - *value = reg_val.bf.rx256t511octgbfis; - return ret; -} - -sw_error_t -hppe_mmc_receive_interrupt_rx256t511octgbfis_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - return SW_NOT_SUPPORTED; -} - -sw_error_t -hppe_mmc_receive_interrupt_rx64octgbfis_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union mmc_receive_interrupt_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_mmc_receive_interrupt_get(dev_id, index, ®_val); - *value = reg_val.bf.rx64octgbfis; - return ret; -} - -sw_error_t -hppe_mmc_receive_interrupt_rx64octgbfis_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - return SW_NOT_SUPPORTED; -} - -sw_error_t -hppe_mmc_receive_interrupt_rxfovfis_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union mmc_receive_interrupt_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_mmc_receive_interrupt_get(dev_id, index, ®_val); - *value = reg_val.bf.rxfovfis; - return ret; -} - -sw_error_t -hppe_mmc_receive_interrupt_rxfovfis_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - return SW_NOT_SUPPORTED; -} - -sw_error_t -hppe_mmc_receive_interrupt_rxgoctis_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union mmc_receive_interrupt_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_mmc_receive_interrupt_get(dev_id, index, ®_val); - *value = reg_val.bf.rxgoctis; - return ret; -} - -sw_error_t -hppe_mmc_receive_interrupt_rxgoctis_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - return SW_NOT_SUPPORTED; -} - -sw_error_t -hppe_mmc_receive_interrupt_rxgbfrmis_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union mmc_receive_interrupt_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_mmc_receive_interrupt_get(dev_id, index, ®_val); - *value = reg_val.bf.rxgbfrmis; - return ret; -} - -sw_error_t -hppe_mmc_receive_interrupt_rxgbfrmis_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - return SW_NOT_SUPPORTED; -} - -sw_error_t -hppe_mmc_receive_interrupt_rxlpitrcis_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union mmc_receive_interrupt_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_mmc_receive_interrupt_get(dev_id, index, ®_val); - *value = reg_val.bf.rxlpitrcis; - return ret; -} - -sw_error_t -hppe_mmc_receive_interrupt_rxlpitrcis_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - return SW_NOT_SUPPORTED; -} - -sw_error_t -hppe_mmc_receive_interrupt_rxbcgfis_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union mmc_receive_interrupt_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_mmc_receive_interrupt_get(dev_id, index, ®_val); - *value = reg_val.bf.rxbcgfis; - return ret; -} - -sw_error_t -hppe_mmc_receive_interrupt_rxbcgfis_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - return SW_NOT_SUPPORTED; -} - -sw_error_t -hppe_mmc_receive_interrupt_rxusizegfis_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union mmc_receive_interrupt_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_mmc_receive_interrupt_get(dev_id, index, ®_val); - *value = reg_val.bf.rxusizegfis; - return ret; -} - -sw_error_t -hppe_mmc_receive_interrupt_rxusizegfis_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - return SW_NOT_SUPPORTED; -} - -sw_error_t -hppe_mmc_receive_interrupt_rxucgfis_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union mmc_receive_interrupt_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_mmc_receive_interrupt_get(dev_id, index, ®_val); - *value = reg_val.bf.rxucgfis; - return ret; -} - -sw_error_t -hppe_mmc_receive_interrupt_rxucgfis_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - return SW_NOT_SUPPORTED; -} - -sw_error_t -hppe_mmc_transmit_interrupt_txgbfrmis_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union mmc_transmit_interrupt_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_mmc_transmit_interrupt_get(dev_id, index, ®_val); - *value = reg_val.bf.txgbfrmis; - return ret; -} - -sw_error_t -hppe_mmc_transmit_interrupt_txgbfrmis_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - return SW_NOT_SUPPORTED; -} - -sw_error_t -hppe_mmc_transmit_interrupt_txprmmcis_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union mmc_transmit_interrupt_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_mmc_transmit_interrupt_get(dev_id, index, ®_val); - *value = reg_val.bf.txprmmcis; - return ret; -} - -sw_error_t -hppe_mmc_transmit_interrupt_txprmmcis_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - return SW_NOT_SUPPORTED; -} - -sw_error_t -hppe_mmc_transmit_interrupt_tx1024tmaxoctgbfis_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union mmc_transmit_interrupt_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_mmc_transmit_interrupt_get(dev_id, index, ®_val); - *value = reg_val.bf.tx1024tmaxoctgbfis; - return ret; -} - -sw_error_t -hppe_mmc_transmit_interrupt_tx1024tmaxoctgbfis_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - return SW_NOT_SUPPORTED; -} - -sw_error_t -hppe_mmc_transmit_interrupt_tx256t511octgbfis_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union mmc_transmit_interrupt_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_mmc_transmit_interrupt_get(dev_id, index, ®_val); - *value = reg_val.bf.tx256t511octgbfis; - return ret; -} - -sw_error_t -hppe_mmc_transmit_interrupt_tx256t511octgbfis_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - return SW_NOT_SUPPORTED; -} - -sw_error_t -hppe_mmc_transmit_interrupt_txlpitrcis_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union mmc_transmit_interrupt_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_mmc_transmit_interrupt_get(dev_id, index, ®_val); - *value = reg_val.bf.txlpitrcis; - return ret; -} - -sw_error_t -hppe_mmc_transmit_interrupt_txlpitrcis_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - return SW_NOT_SUPPORTED; -} - -sw_error_t -hppe_mmc_transmit_interrupt_txbcgfis_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union mmc_transmit_interrupt_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_mmc_transmit_interrupt_get(dev_id, index, ®_val); - *value = reg_val.bf.txbcgfis; - return ret; -} - -sw_error_t -hppe_mmc_transmit_interrupt_txbcgfis_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - return SW_NOT_SUPPORTED; -} - -sw_error_t -hppe_mmc_transmit_interrupt_tx64octgbfis_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union mmc_transmit_interrupt_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_mmc_transmit_interrupt_get(dev_id, index, ®_val); - *value = reg_val.bf.tx64octgbfis; - return ret; -} - -sw_error_t -hppe_mmc_transmit_interrupt_tx64octgbfis_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - return SW_NOT_SUPPORTED; -} - -sw_error_t -hppe_mmc_transmit_interrupt_txlpiuscis_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union mmc_transmit_interrupt_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_mmc_transmit_interrupt_get(dev_id, index, ®_val); - *value = reg_val.bf.txlpiuscis; - return ret; -} - -sw_error_t -hppe_mmc_transmit_interrupt_txlpiuscis_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - return SW_NOT_SUPPORTED; -} - -sw_error_t -hppe_mmc_transmit_interrupt_txuflowerfis_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union mmc_transmit_interrupt_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_mmc_transmit_interrupt_get(dev_id, index, ®_val); - *value = reg_val.bf.txuflowerfis; - return ret; -} - -sw_error_t -hppe_mmc_transmit_interrupt_txuflowerfis_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - return SW_NOT_SUPPORTED; -} - -sw_error_t -hppe_mmc_transmit_interrupt_txbcgbfis_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union mmc_transmit_interrupt_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_mmc_transmit_interrupt_get(dev_id, index, ®_val); - *value = reg_val.bf.txbcgbfis; - return ret; -} - -sw_error_t -hppe_mmc_transmit_interrupt_txbcgbfis_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - return SW_NOT_SUPPORTED; -} - -sw_error_t -hppe_mmc_transmit_interrupt_txpausfis_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union mmc_transmit_interrupt_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_mmc_transmit_interrupt_get(dev_id, index, ®_val); - *value = reg_val.bf.txpausfis; - return ret; -} - -sw_error_t -hppe_mmc_transmit_interrupt_txpausfis_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - return SW_NOT_SUPPORTED; -} - -sw_error_t -hppe_mmc_transmit_interrupt_txvlangfis_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union mmc_transmit_interrupt_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_mmc_transmit_interrupt_get(dev_id, index, ®_val); - *value = reg_val.bf.txvlangfis; - return ret; -} - -sw_error_t -hppe_mmc_transmit_interrupt_txvlangfis_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - return SW_NOT_SUPPORTED; -} - -sw_error_t -hppe_mmc_transmit_interrupt_txgboctis_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union mmc_transmit_interrupt_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_mmc_transmit_interrupt_get(dev_id, index, ®_val); - *value = reg_val.bf.txgboctis; - return ret; -} - -sw_error_t -hppe_mmc_transmit_interrupt_txgboctis_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - return SW_NOT_SUPPORTED; -} - -sw_error_t -hppe_mmc_transmit_interrupt_txgfrmis_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union mmc_transmit_interrupt_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_mmc_transmit_interrupt_get(dev_id, index, ®_val); - *value = reg_val.bf.txgfrmis; - return ret; -} - -sw_error_t -hppe_mmc_transmit_interrupt_txgfrmis_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - return SW_NOT_SUPPORTED; -} - -sw_error_t -hppe_mmc_transmit_interrupt_tx512t1023octgbfis_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union mmc_transmit_interrupt_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_mmc_transmit_interrupt_get(dev_id, index, ®_val); - *value = reg_val.bf.tx512t1023octgbfis; - return ret; -} - -sw_error_t -hppe_mmc_transmit_interrupt_tx512t1023octgbfis_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - return SW_NOT_SUPPORTED; -} - -sw_error_t -hppe_mmc_transmit_interrupt_txmcgfis_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union mmc_transmit_interrupt_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_mmc_transmit_interrupt_get(dev_id, index, ®_val); - *value = reg_val.bf.txmcgfis; - return ret; -} - -sw_error_t -hppe_mmc_transmit_interrupt_txmcgfis_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - return SW_NOT_SUPPORTED; -} - -sw_error_t -hppe_mmc_transmit_interrupt_txucgbfis_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union mmc_transmit_interrupt_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_mmc_transmit_interrupt_get(dev_id, index, ®_val); - *value = reg_val.bf.txucgbfis; - return ret; -} - -sw_error_t -hppe_mmc_transmit_interrupt_txucgbfis_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - return SW_NOT_SUPPORTED; -} - -sw_error_t -hppe_mmc_transmit_interrupt_tx65t127octgbfis_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union mmc_transmit_interrupt_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_mmc_transmit_interrupt_get(dev_id, index, ®_val); - *value = reg_val.bf.tx65t127octgbfis; - return ret; -} - -sw_error_t -hppe_mmc_transmit_interrupt_tx65t127octgbfis_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - return SW_NOT_SUPPORTED; -} - -sw_error_t -hppe_mmc_transmit_interrupt_txmcgbfis_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union mmc_transmit_interrupt_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_mmc_transmit_interrupt_get(dev_id, index, ®_val); - *value = reg_val.bf.txmcgbfis; - return ret; -} - -sw_error_t -hppe_mmc_transmit_interrupt_txmcgbfis_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - return SW_NOT_SUPPORTED; -} - -sw_error_t -hppe_mmc_transmit_interrupt_tx128t255octgbfis_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union mmc_transmit_interrupt_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_mmc_transmit_interrupt_get(dev_id, index, ®_val); - *value = reg_val.bf.tx128t255octgbfis; - return ret; -} - -sw_error_t -hppe_mmc_transmit_interrupt_tx128t255octgbfis_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - return SW_NOT_SUPPORTED; -} - -sw_error_t -hppe_mmc_transmit_interrupt_txgoctis_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union mmc_transmit_interrupt_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_mmc_transmit_interrupt_get(dev_id, index, ®_val); - *value = reg_val.bf.txgoctis; - return ret; -} - -sw_error_t -hppe_mmc_transmit_interrupt_txgoctis_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - return SW_NOT_SUPPORTED; -} - -sw_error_t -hppe_mmc_receive_interrupt_enable_rxprmmcise_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union mmc_receive_interrupt_enable_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_mmc_receive_interrupt_enable_get(dev_id, index, ®_val); - *value = reg_val.bf.rxprmmcise; - return ret; -} - -sw_error_t -hppe_mmc_receive_interrupt_enable_rxprmmcise_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - return SW_NOT_SUPPORTED; -} - -sw_error_t -hppe_mmc_receive_interrupt_enable_rx65t127octgbfie_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union mmc_receive_interrupt_enable_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_mmc_receive_interrupt_enable_get(dev_id, index, ®_val); - *value = reg_val.bf.rx65t127octgbfie; - return ret; -} - -sw_error_t -hppe_mmc_receive_interrupt_enable_rx65t127octgbfie_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - return SW_NOT_SUPPORTED; -} - -sw_error_t -hppe_mmc_receive_interrupt_enable_rxruntfie_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union mmc_receive_interrupt_enable_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_mmc_receive_interrupt_enable_get(dev_id, index, ®_val); - *value = reg_val.bf.rxruntfie; - return ret; -} - -sw_error_t -hppe_mmc_receive_interrupt_enable_rxruntfie_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - return SW_NOT_SUPPORTED; -} - -sw_error_t -hppe_mmc_receive_interrupt_enable_rxcrcerfie_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union mmc_receive_interrupt_enable_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_mmc_receive_interrupt_enable_get(dev_id, index, ®_val); - *value = reg_val.bf.rxcrcerfie; - return ret; -} - -sw_error_t -hppe_mmc_receive_interrupt_enable_rxcrcerfie_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - return SW_NOT_SUPPORTED; -} - -sw_error_t -hppe_mmc_receive_interrupt_enable_rx256t511octgbfie_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union mmc_receive_interrupt_enable_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_mmc_receive_interrupt_enable_get(dev_id, index, ®_val); - *value = reg_val.bf.rx256t511octgbfie; - return ret; -} - -sw_error_t -hppe_mmc_receive_interrupt_enable_rx256t511octgbfie_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - return SW_NOT_SUPPORTED; -} - -sw_error_t -hppe_mmc_receive_interrupt_enable_rxlenerfie_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union mmc_receive_interrupt_enable_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_mmc_receive_interrupt_enable_get(dev_id, index, ®_val); - *value = reg_val.bf.rxlenerfie; - return ret; -} - -sw_error_t -hppe_mmc_receive_interrupt_enable_rxlenerfie_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - return SW_NOT_SUPPORTED; -} - -sw_error_t -hppe_mmc_receive_interrupt_enable_rxusizegfie_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union mmc_receive_interrupt_enable_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_mmc_receive_interrupt_enable_get(dev_id, index, ®_val); - *value = reg_val.bf.rxusizegfie; - return ret; -} - -sw_error_t -hppe_mmc_receive_interrupt_enable_rxusizegfie_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - return SW_NOT_SUPPORTED; -} - -sw_error_t -hppe_mmc_receive_interrupt_enable_rxosizegfie_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union mmc_receive_interrupt_enable_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_mmc_receive_interrupt_enable_get(dev_id, index, ®_val); - *value = reg_val.bf.rxosizegfie; - return ret; -} - -sw_error_t -hppe_mmc_receive_interrupt_enable_rxosizegfie_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - return SW_NOT_SUPPORTED; -} - -sw_error_t -hppe_mmc_receive_interrupt_enable_rxfovfie_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union mmc_receive_interrupt_enable_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_mmc_receive_interrupt_enable_get(dev_id, index, ®_val); - *value = reg_val.bf.rxfovfie; - return ret; -} - -sw_error_t -hppe_mmc_receive_interrupt_enable_rxfovfie_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - return SW_NOT_SUPPORTED; -} - -sw_error_t -hppe_mmc_receive_interrupt_enable_rxmcgfie_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union mmc_receive_interrupt_enable_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_mmc_receive_interrupt_enable_get(dev_id, index, ®_val); - *value = reg_val.bf.rxmcgfie; - return ret; -} - -sw_error_t -hppe_mmc_receive_interrupt_enable_rxmcgfie_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - return SW_NOT_SUPPORTED; -} - -sw_error_t -hppe_mmc_receive_interrupt_enable_rxvlangbfie_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union mmc_receive_interrupt_enable_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_mmc_receive_interrupt_enable_get(dev_id, index, ®_val); - *value = reg_val.bf.rxvlangbfie; - return ret; -} - -sw_error_t -hppe_mmc_receive_interrupt_enable_rxvlangbfie_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - return SW_NOT_SUPPORTED; -} - -sw_error_t -hppe_mmc_receive_interrupt_enable_rxwdogfie_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union mmc_receive_interrupt_enable_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_mmc_receive_interrupt_enable_get(dev_id, index, ®_val); - *value = reg_val.bf.rxwdogfie; - return ret; -} - -sw_error_t -hppe_mmc_receive_interrupt_enable_rxwdogfie_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - return SW_NOT_SUPPORTED; -} - -sw_error_t -hppe_mmc_receive_interrupt_enable_rxdisocie_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union mmc_receive_interrupt_enable_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_mmc_receive_interrupt_enable_get(dev_id, index, ®_val); - *value = reg_val.bf.rxdisocie; - return ret; -} - -sw_error_t -hppe_mmc_receive_interrupt_enable_rxdisocie_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - return SW_NOT_SUPPORTED; -} - -sw_error_t -hppe_mmc_receive_interrupt_enable_rxgbfrmie_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union mmc_receive_interrupt_enable_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_mmc_receive_interrupt_enable_get(dev_id, index, ®_val); - *value = reg_val.bf.rxgbfrmie; - return ret; -} - -sw_error_t -hppe_mmc_receive_interrupt_enable_rxgbfrmie_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - return SW_NOT_SUPPORTED; -} - -sw_error_t -hppe_mmc_receive_interrupt_enable_rxjaberfie_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union mmc_receive_interrupt_enable_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_mmc_receive_interrupt_enable_get(dev_id, index, ®_val); - *value = reg_val.bf.rxjaberfie; - return ret; -} - -sw_error_t -hppe_mmc_receive_interrupt_enable_rxjaberfie_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - return SW_NOT_SUPPORTED; -} - -sw_error_t -hppe_mmc_receive_interrupt_enable_rxlpiuscie_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union mmc_receive_interrupt_enable_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_mmc_receive_interrupt_enable_get(dev_id, index, ®_val); - *value = reg_val.bf.rxlpiuscie; - return ret; -} - -sw_error_t -hppe_mmc_receive_interrupt_enable_rxlpiuscie_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - return SW_NOT_SUPPORTED; -} - -sw_error_t -hppe_mmc_receive_interrupt_enable_rxucgfie_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union mmc_receive_interrupt_enable_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_mmc_receive_interrupt_enable_get(dev_id, index, ®_val); - *value = reg_val.bf.rxucgfie; - return ret; -} - -sw_error_t -hppe_mmc_receive_interrupt_enable_rxucgfie_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - return SW_NOT_SUPPORTED; -} - -sw_error_t -hppe_mmc_receive_interrupt_enable_rx1024tmaxoctgbfie_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union mmc_receive_interrupt_enable_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_mmc_receive_interrupt_enable_get(dev_id, index, ®_val); - *value = reg_val.bf.rx1024tmaxoctgbfie; - return ret; -} - -sw_error_t -hppe_mmc_receive_interrupt_enable_rx1024tmaxoctgbfie_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - return SW_NOT_SUPPORTED; -} - -sw_error_t -hppe_mmc_receive_interrupt_enable_rxpausfie_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union mmc_receive_interrupt_enable_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_mmc_receive_interrupt_enable_get(dev_id, index, ®_val); - *value = reg_val.bf.rxpausfie; - return ret; -} - -sw_error_t -hppe_mmc_receive_interrupt_enable_rxpausfie_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - return SW_NOT_SUPPORTED; -} - -sw_error_t -hppe_mmc_receive_interrupt_enable_rxdisfcie_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union mmc_receive_interrupt_enable_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_mmc_receive_interrupt_enable_get(dev_id, index, ®_val); - *value = reg_val.bf.rxdisfcie; - return ret; -} - -sw_error_t -hppe_mmc_receive_interrupt_enable_rxdisfcie_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - return SW_NOT_SUPPORTED; -} - -sw_error_t -hppe_mmc_receive_interrupt_enable_rxgoctie_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union mmc_receive_interrupt_enable_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_mmc_receive_interrupt_enable_get(dev_id, index, ®_val); - *value = reg_val.bf.rxgoctie; - return ret; -} - -sw_error_t -hppe_mmc_receive_interrupt_enable_rxgoctie_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - return SW_NOT_SUPPORTED; -} - -sw_error_t -hppe_mmc_receive_interrupt_enable_rxgboctie_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union mmc_receive_interrupt_enable_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_mmc_receive_interrupt_enable_get(dev_id, index, ®_val); - *value = reg_val.bf.rxgboctie; - return ret; -} - -sw_error_t -hppe_mmc_receive_interrupt_enable_rxgboctie_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - return SW_NOT_SUPPORTED; -} - -sw_error_t -hppe_mmc_receive_interrupt_enable_rx128t255octgbfie_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union mmc_receive_interrupt_enable_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_mmc_receive_interrupt_enable_get(dev_id, index, ®_val); - *value = reg_val.bf.rx128t255octgbfie; - return ret; -} - -sw_error_t -hppe_mmc_receive_interrupt_enable_rx128t255octgbfie_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - return SW_NOT_SUPPORTED; -} - -sw_error_t -hppe_mmc_receive_interrupt_enable_rxlpitrcie_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union mmc_receive_interrupt_enable_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_mmc_receive_interrupt_enable_get(dev_id, index, ®_val); - *value = reg_val.bf.rxlpitrcie; - return ret; -} - -sw_error_t -hppe_mmc_receive_interrupt_enable_rxlpitrcie_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - return SW_NOT_SUPPORTED; -} - -sw_error_t -hppe_mmc_receive_interrupt_enable_rxbcgfie_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union mmc_receive_interrupt_enable_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_mmc_receive_interrupt_enable_get(dev_id, index, ®_val); - *value = reg_val.bf.rxbcgfie; - return ret; -} - -sw_error_t -hppe_mmc_receive_interrupt_enable_rxbcgfie_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - return SW_NOT_SUPPORTED; -} - -sw_error_t -hppe_mmc_receive_interrupt_enable_rx64octgbfie_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union mmc_receive_interrupt_enable_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_mmc_receive_interrupt_enable_get(dev_id, index, ®_val); - *value = reg_val.bf.rx64octgbfie; - return ret; -} - -sw_error_t -hppe_mmc_receive_interrupt_enable_rx64octgbfie_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - return SW_NOT_SUPPORTED; -} - -sw_error_t -hppe_mmc_receive_interrupt_enable_rxorangefie_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union mmc_receive_interrupt_enable_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_mmc_receive_interrupt_enable_get(dev_id, index, ®_val); - *value = reg_val.bf.rxorangefie; - return ret; -} - -sw_error_t -hppe_mmc_receive_interrupt_enable_rxorangefie_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - return SW_NOT_SUPPORTED; -} - -sw_error_t -hppe_mmc_receive_interrupt_enable_rx512t1023octgbfie_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union mmc_receive_interrupt_enable_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_mmc_receive_interrupt_enable_get(dev_id, index, ®_val); - *value = reg_val.bf.rx512t1023octgbfie; - return ret; -} - -sw_error_t -hppe_mmc_receive_interrupt_enable_rx512t1023octgbfie_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - return SW_NOT_SUPPORTED; -} - -sw_error_t -hppe_mmc_transmit_interrupt_enable_txucgbfie_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union mmc_transmit_interrupt_enable_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_mmc_transmit_interrupt_enable_get(dev_id, index, ®_val); - *value = reg_val.bf.txucgbfie; - return ret; -} - -sw_error_t -hppe_mmc_transmit_interrupt_enable_txucgbfie_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - return SW_NOT_SUPPORTED; -} - -sw_error_t -hppe_mmc_transmit_interrupt_enable_tx64octgbfie_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union mmc_transmit_interrupt_enable_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_mmc_transmit_interrupt_enable_get(dev_id, index, ®_val); - *value = reg_val.bf.tx64octgbfie; - return ret; -} - -sw_error_t -hppe_mmc_transmit_interrupt_enable_tx64octgbfie_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - return SW_NOT_SUPPORTED; -} - -sw_error_t -hppe_mmc_transmit_interrupt_enable_txbcgfie_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union mmc_transmit_interrupt_enable_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_mmc_transmit_interrupt_enable_get(dev_id, index, ®_val); - *value = reg_val.bf.txbcgfie; - return ret; -} - -sw_error_t -hppe_mmc_transmit_interrupt_enable_txbcgfie_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - return SW_NOT_SUPPORTED; -} - -sw_error_t -hppe_mmc_transmit_interrupt_enable_txgbfrmie_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union mmc_transmit_interrupt_enable_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_mmc_transmit_interrupt_enable_get(dev_id, index, ®_val); - *value = reg_val.bf.txgbfrmie; - return ret; -} - -sw_error_t -hppe_mmc_transmit_interrupt_enable_txgbfrmie_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - return SW_NOT_SUPPORTED; -} - -sw_error_t -hppe_mmc_transmit_interrupt_enable_txgfrmie_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union mmc_transmit_interrupt_enable_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_mmc_transmit_interrupt_enable_get(dev_id, index, ®_val); - *value = reg_val.bf.txgfrmie; - return ret; -} - -sw_error_t -hppe_mmc_transmit_interrupt_enable_txgfrmie_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - return SW_NOT_SUPPORTED; -} - -sw_error_t -hppe_mmc_transmit_interrupt_enable_txgoctie_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union mmc_transmit_interrupt_enable_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_mmc_transmit_interrupt_enable_get(dev_id, index, ®_val); - *value = reg_val.bf.txgoctie; - return ret; -} - -sw_error_t -hppe_mmc_transmit_interrupt_enable_txgoctie_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - return SW_NOT_SUPPORTED; -} - -sw_error_t -hppe_mmc_transmit_interrupt_enable_txbcgbfie_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union mmc_transmit_interrupt_enable_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_mmc_transmit_interrupt_enable_get(dev_id, index, ®_val); - *value = reg_val.bf.txbcgbfie; - return ret; -} - -sw_error_t -hppe_mmc_transmit_interrupt_enable_txbcgbfie_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - return SW_NOT_SUPPORTED; -} - -sw_error_t -hppe_mmc_transmit_interrupt_enable_txlpitrcie_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union mmc_transmit_interrupt_enable_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_mmc_transmit_interrupt_enable_get(dev_id, index, ®_val); - *value = reg_val.bf.txlpitrcie; - return ret; -} - -sw_error_t -hppe_mmc_transmit_interrupt_enable_txlpitrcie_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - return SW_NOT_SUPPORTED; -} - -sw_error_t -hppe_mmc_transmit_interrupt_enable_txvlangfie_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union mmc_transmit_interrupt_enable_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_mmc_transmit_interrupt_enable_get(dev_id, index, ®_val); - *value = reg_val.bf.txvlangfie; - return ret; -} - -sw_error_t -hppe_mmc_transmit_interrupt_enable_txvlangfie_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - return SW_NOT_SUPPORTED; -} - -sw_error_t -hppe_mmc_transmit_interrupt_enable_txpausfie_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union mmc_transmit_interrupt_enable_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_mmc_transmit_interrupt_enable_get(dev_id, index, ®_val); - *value = reg_val.bf.txpausfie; - return ret; -} - -sw_error_t -hppe_mmc_transmit_interrupt_enable_txpausfie_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - return SW_NOT_SUPPORTED; -} - -sw_error_t -hppe_mmc_transmit_interrupt_enable_txgboctie_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union mmc_transmit_interrupt_enable_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_mmc_transmit_interrupt_enable_get(dev_id, index, ®_val); - *value = reg_val.bf.txgboctie; - return ret; -} - -sw_error_t -hppe_mmc_transmit_interrupt_enable_txgboctie_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - return SW_NOT_SUPPORTED; -} - -sw_error_t -hppe_mmc_transmit_interrupt_enable_txmcgfie_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union mmc_transmit_interrupt_enable_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_mmc_transmit_interrupt_enable_get(dev_id, index, ®_val); - *value = reg_val.bf.txmcgfie; - return ret; -} - -sw_error_t -hppe_mmc_transmit_interrupt_enable_txmcgfie_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - return SW_NOT_SUPPORTED; -} - -sw_error_t -hppe_mmc_transmit_interrupt_enable_txuflowerfie_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union mmc_transmit_interrupt_enable_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_mmc_transmit_interrupt_enable_get(dev_id, index, ®_val); - *value = reg_val.bf.txuflowerfie; - return ret; -} - -sw_error_t -hppe_mmc_transmit_interrupt_enable_txuflowerfie_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - return SW_NOT_SUPPORTED; -} - -sw_error_t -hppe_mmc_transmit_interrupt_enable_txlpiuscie_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union mmc_transmit_interrupt_enable_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_mmc_transmit_interrupt_enable_get(dev_id, index, ®_val); - *value = reg_val.bf.txlpiuscie; - return ret; -} - -sw_error_t -hppe_mmc_transmit_interrupt_enable_txlpiuscie_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - return SW_NOT_SUPPORTED; -} - -sw_error_t -hppe_mmc_transmit_interrupt_enable_tx256t511octgbfie_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union mmc_transmit_interrupt_enable_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_mmc_transmit_interrupt_enable_get(dev_id, index, ®_val); - *value = reg_val.bf.tx256t511octgbfie; - return ret; -} - -sw_error_t -hppe_mmc_transmit_interrupt_enable_tx256t511octgbfie_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - return SW_NOT_SUPPORTED; -} - -sw_error_t -hppe_mmc_transmit_interrupt_enable_tx65t127octgbfie_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union mmc_transmit_interrupt_enable_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_mmc_transmit_interrupt_enable_get(dev_id, index, ®_val); - *value = reg_val.bf.tx65t127octgbfie; - return ret; -} - -sw_error_t -hppe_mmc_transmit_interrupt_enable_tx65t127octgbfie_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - return SW_NOT_SUPPORTED; -} - -sw_error_t -hppe_mmc_transmit_interrupt_enable_tx128t255octgbfie_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union mmc_transmit_interrupt_enable_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_mmc_transmit_interrupt_enable_get(dev_id, index, ®_val); - *value = reg_val.bf.tx128t255octgbfie; - return ret; -} - -sw_error_t -hppe_mmc_transmit_interrupt_enable_tx128t255octgbfie_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - return SW_NOT_SUPPORTED; -} - -sw_error_t -hppe_mmc_transmit_interrupt_enable_tx512t1023octgbfie_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union mmc_transmit_interrupt_enable_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_mmc_transmit_interrupt_enable_get(dev_id, index, ®_val); - *value = reg_val.bf.tx512t1023octgbfie; - return ret; -} - -sw_error_t -hppe_mmc_transmit_interrupt_enable_tx512t1023octgbfie_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - return SW_NOT_SUPPORTED; -} - -sw_error_t -hppe_mmc_transmit_interrupt_enable_tx1024tmaxoctgbfie_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union mmc_transmit_interrupt_enable_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_mmc_transmit_interrupt_enable_get(dev_id, index, ®_val); - *value = reg_val.bf.tx1024tmaxoctgbfie; - return ret; -} - -sw_error_t -hppe_mmc_transmit_interrupt_enable_tx1024tmaxoctgbfie_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - return SW_NOT_SUPPORTED; -} - -sw_error_t -hppe_mmc_transmit_interrupt_enable_txprmmcise_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union mmc_transmit_interrupt_enable_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_mmc_transmit_interrupt_enable_get(dev_id, index, ®_val); - *value = reg_val.bf.txprmmcise; - return ret; -} - -sw_error_t -hppe_mmc_transmit_interrupt_enable_txprmmcise_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - return SW_NOT_SUPPORTED; -} - -sw_error_t -hppe_mmc_transmit_interrupt_enable_txmcgbfie_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union mmc_transmit_interrupt_enable_u reg_val; - sw_error_t ret = SW_OK; - - ret = hppe_mmc_transmit_interrupt_enable_get(dev_id, index, ®_val); - *value = reg_val.bf.txmcgbfie; - return ret; -} - -sw_error_t -hppe_mmc_transmit_interrupt_enable_txmcgbfie_set( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t value) -{ - return SW_NOT_SUPPORTED; -} -#endif diff --git a/feeds/ipq807x/qca-ssdk/src/src/hsl/hsl_acl.c b/feeds/ipq807x/qca-ssdk/src/src/hsl/hsl_acl.c deleted file mode 100755 index 2361fae49..000000000 --- a/feeds/ipq807x/qca-ssdk/src/src/hsl/hsl_acl.c +++ /dev/null @@ -1,972 +0,0 @@ -/* - * Copyright (c) 2012, 2016, The Linux Foundation. All rights reserved. - * Permission to use, copy, modify, and/or distribute this software for - * any purpose with or without fee is hereby granted, provided that the - * above copyright notice and this permission notice appear in all copies. - * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES - * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR - * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES - * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN - * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT - * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. - */ - - -#include "sw_config.h" -#include "aos_head.h" -#include "sw_error.h" -#include "shared_func.h" -#include "hsl.h" -#include "hsl_dev.h" -#include "hsl_acl.h" - -typedef struct -{ - a_uint32_t pri; - a_uint32_t addr; - a_uint32_t size; - a_uint32_t status; - a_uint32_t info; -} hsl_acl_blk_t; - -typedef struct -{ - a_uint32_t used_blk; - a_uint32_t total_blk; - a_uint32_t free_rsc; - hsl_acl_blk_t *blk_ent; -} hsl_acl_pool_t; - -#define MEM_FREE 1 -#define MEM_USED 2 - -static hsl_acl_pool_t acl_pool[SW_MAX_NR_DEV]; - -static sw_error_t -_hsl_acl_blk_loc(a_uint32_t dev_id, a_uint32_t addr, a_uint32_t * idx); - -static sw_error_t -_hsl_acl_blk_comb(a_uint32_t dev_id, a_uint32_t idx, a_uint32_t nr); - -static sw_error_t _hsl_acl_free_blk_comb(a_uint32_t dev_id, a_uint32_t idx); - -static sw_error_t -_hsl_acl_blk_ent_left_mv(a_uint32_t dev_id, a_uint32_t idx, a_uint32_t offset); - -static sw_error_t -_hsl_acl_blk_ent_right_mv(a_uint32_t dev_id, a_uint32_t idx, a_uint32_t offset); - -static sw_error_t -_hsl_acl_blk_left_defrag(a_uint32_t dev_id, a_uint32_t p_idx, a_uint32_t t_size, - a_bool_t b_must, a_uint32_t * f_idx, a_uint32_t * f_nr, - a_uint32_t * f_size); - -static sw_error_t -_hsl_acl_blk_right_defrag(a_uint32_t dev_id, a_uint32_t p_idx, - a_uint32_t t_size, a_bool_t b_must, - a_uint32_t * f_idx, a_uint32_t * f_nr, - a_uint32_t * f_size); - -static sw_error_t -_hsl_acl_blk_alloc(a_uint32_t dev_id, a_uint32_t free_idx, a_uint32_t pri, - a_uint32_t size, a_uint32_t info, a_uint32_t * addr); - -static sw_error_t -_hsl_acl_blk_reduce(a_uint32_t dev_id, a_uint32_t idx, a_uint32_t new_size); - -static sw_error_t -_hsl_acl_blk_left_enlarge(a_uint32_t dev_id, a_uint32_t idx, - a_uint32_t new_size); - -static sw_error_t -_hsl_acl_blk_right_enlarge(a_uint32_t dev_id, a_uint32_t idx, - a_uint32_t new_size); - -static sw_error_t -_hsl_acl_rule_copy(a_uint32_t dev_id, a_uint32_t src_addr, a_uint32_t dest_addr, - a_uint32_t size); - -static sw_error_t -_hsl_acl_rule_invalid(a_uint32_t dev_id, a_uint32_t addr, a_uint32_t size); - -static sw_error_t -_hsl_acl_addr_update(a_uint32_t dev_id, a_uint32_t old_addr, - a_uint32_t new_addr, a_uint32_t info); - -//#define ACL_POOL_DEBUG -#ifdef ACL_POOL_DEBUG -static void -_hsl_acl_blk_dump(a_uint32_t dev_id, const char *info) -{ - a_uint32_t i; - - aos_printk("\n%s dev_id=%d free_rsc=%d total_blk=%d used_blk=%d", - info, dev_id, acl_pool[dev_id].free_rsc, - acl_pool[dev_id].total_blk, acl_pool[dev_id].used_blk); - - for (i = 0; i < acl_pool[dev_id].used_blk; i++) - { - aos_printk("\naddr=%d status = %d size=%d list_id=%d list_pri=%d", - acl_pool[dev_id].blk_ent[i].addr, - acl_pool[dev_id].blk_ent[i].status, - acl_pool[dev_id].blk_ent[i].size, - acl_pool[dev_id].blk_ent[i].info, - acl_pool[dev_id].blk_ent[i].pri); - } - aos_printk("\n"); -} -#else -#define _hsl_acl_blk_dump(dev_id, info) -#endif - -static sw_error_t -_hsl_acl_blk_loc(a_uint32_t dev_id, a_uint32_t addr, a_uint32_t * idx) -{ - a_uint32_t i; - - for (i = 0; i < acl_pool[dev_id].used_blk; i++) - { - if (addr == acl_pool[dev_id].blk_ent[i].addr) - { - *idx = i; - return SW_OK; - } - } - return SW_NOT_FOUND; -} - -static sw_error_t -_hsl_acl_blk_comb(a_uint32_t dev_id, a_uint32_t idx, a_uint32_t nr) -{ - sw_error_t rv; - a_uint32_t i, size; - - _hsl_acl_blk_dump(dev_id, "_hsl_acl_blk_comb before combine"); - - if ((idx + nr) > acl_pool[dev_id].used_blk) - { - return SW_BAD_PARAM; - } - - if (nr < 2) - { - _hsl_acl_blk_dump(dev_id, "_hsl_acl_blk_comb after combine"); - return SW_OK; - } - - size = 0; - for (i = 0; i < nr; i++) - { - size += acl_pool[dev_id].blk_ent[idx + i].size; - } - acl_pool[dev_id].blk_ent[idx].size = size; - - rv = _hsl_acl_blk_ent_left_mv(dev_id, idx + nr, nr - 1); - _hsl_acl_blk_dump(dev_id, "_hsl_acl_blk_comb after combine"); - return rv; -} - -static sw_error_t -_hsl_acl_free_blk_comb(a_uint32_t dev_id, a_uint32_t idx) -{ - sw_error_t rv; - a_uint32_t first, num; - - _hsl_acl_blk_dump(dev_id, "_hsl_acl_free_blk_comb before combine"); - - first = idx; - num = 1; - if (0 != idx) - { - if (MEM_FREE == acl_pool[dev_id].blk_ent[idx - 1].status) - { - num++; - first = idx - 1; - } - } - - if ((acl_pool[dev_id].used_blk - 1) != idx) - { - if (MEM_FREE == acl_pool[dev_id].blk_ent[idx + 1].status) - { - num++; - } - } - - rv = _hsl_acl_blk_comb(dev_id, first, num); - _hsl_acl_blk_dump(dev_id, "_hsl_acl_free_blk_comb after combine"); - return rv; -} - -static sw_error_t -_hsl_acl_blk_ent_left_mv(a_uint32_t dev_id, a_uint32_t idx, a_uint32_t offset) -{ - a_uint32_t i; - - _hsl_acl_blk_dump(dev_id, "_hsl_acl_blk_ent_left_mv before move"); - - if (offset > idx) - { - return SW_BAD_PARAM; - } - - for (i = idx; i < acl_pool[dev_id].used_blk; i++) - { - acl_pool[dev_id].blk_ent[i - offset] = acl_pool[dev_id].blk_ent[i]; - } - - acl_pool[dev_id].used_blk -= offset; - _hsl_acl_blk_dump(dev_id, "_hsl_acl_blk_ent_left_mv after move"); - return SW_OK; -} - -static sw_error_t -_hsl_acl_blk_ent_right_mv(a_uint32_t dev_id, a_uint32_t idx, a_uint32_t offset) -{ - a_uint32_t i, cnt, tmp; - - _hsl_acl_blk_dump(dev_id, "_hsl_acl_blk_ent_right_mv before move"); - - if (acl_pool[dev_id].total_blk < (acl_pool[dev_id].used_blk + offset)) - { - return SW_BAD_PARAM; - } - - /* we support to increase used block number without block moving */ - if (idx > acl_pool[dev_id].used_blk) - { - return SW_BAD_PARAM; - } - - cnt = acl_pool[dev_id].used_blk - idx; - tmp = acl_pool[dev_id].used_blk - 1; - for (i = 0; i < cnt; i++) - { - acl_pool[dev_id].blk_ent[tmp + offset - i] - = acl_pool[dev_id].blk_ent[tmp - i]; - } - - acl_pool[dev_id].used_blk += offset; - _hsl_acl_blk_dump(dev_id, "_hsl_acl_blk_ent_right_mv after move"); - return SW_OK; -} - -static sw_error_t -_hsl_acl_blk_left_defrag(a_uint32_t dev_id, a_uint32_t p_idx, a_uint32_t t_size, - a_bool_t b_must, a_uint32_t * f_idx, a_uint32_t * f_nr, - a_uint32_t * f_size) -{ - sw_error_t rv; - a_int32_t idx; - a_uint32_t i, f_rsc, f_blk, dest_addr; - - _hsl_acl_blk_dump(dev_id, "_hsl_acl_left_defrag before defrag"); - - f_rsc = 0; - for (idx = p_idx - 1; idx >= 0; idx--) - { - if (MEM_FREE == acl_pool[dev_id].blk_ent[idx].status) - { - f_rsc += acl_pool[dev_id].blk_ent[idx].size; - } - - if (t_size <= f_rsc) - { - break; - } - } - - if ((f_rsc < t_size) && (A_TRUE == b_must)) - { - return SW_NO_RESOURCE; - } - - if (0 == f_rsc) - { - *f_idx = p_idx; - *f_nr = 0; - *f_size = 0; - _hsl_acl_blk_dump(dev_id, "_hsl_acl_left_defrag after defrag"); - return SW_OK; - } - - if (idx < 0) - { - idx = 0; - } - - f_blk = 0; - f_rsc = 0; - dest_addr = acl_pool[dev_id].blk_ent[idx].addr; - for (i = idx; i < p_idx; i++) - { - if (MEM_FREE == acl_pool[dev_id].blk_ent[i].status) - { - f_blk += 1; - f_rsc += acl_pool[dev_id].blk_ent[i].size; - } - - if (MEM_USED == acl_pool[dev_id].blk_ent[i].status) - { - if (dest_addr != acl_pool[dev_id].blk_ent[i].addr) - { - /* update acl rules hardware position */ - rv = _hsl_acl_rule_copy(dev_id, - acl_pool[dev_id].blk_ent[i].addr, - dest_addr, - acl_pool[dev_id].blk_ent[i].size); - SW_RTN_ON_ERROR(rv); - - rv = _hsl_acl_addr_update(dev_id, - acl_pool[dev_id].blk_ent[i].addr, - dest_addr, - acl_pool[dev_id].blk_ent[i].info); - SW_RTN_ON_ERROR(rv); - - /* update acl memory block control infomation */ - acl_pool[dev_id].blk_ent[i - f_blk] = - acl_pool[dev_id].blk_ent[i]; - acl_pool[dev_id].blk_ent[i - f_blk].addr -= f_rsc; - } - dest_addr += acl_pool[dev_id].blk_ent[i].size; - } - } - - for (i = p_idx - f_blk; i < p_idx; i++) - { - acl_pool[dev_id].blk_ent[i].status = MEM_FREE; - acl_pool[dev_id].blk_ent[i].addr = dest_addr; - acl_pool[dev_id].blk_ent[i].size = 0; - acl_pool[dev_id].blk_ent[i].info = 0; - acl_pool[dev_id].blk_ent[i].pri = 0; - } - acl_pool[dev_id].blk_ent[p_idx - f_blk].size = f_rsc; - - *f_idx = p_idx - f_blk; - *f_nr = f_blk; - *f_size = f_rsc; - rv = _hsl_acl_rule_invalid(dev_id, acl_pool[dev_id].blk_ent[*f_idx].addr, - f_rsc); - _hsl_acl_blk_dump(dev_id, "_hsl_acl_left_defrag after defrag"); - return rv; -} - -static sw_error_t -_hsl_acl_blk_right_defrag(a_uint32_t dev_id, a_uint32_t p_idx, - a_uint32_t t_size, a_bool_t b_must, - a_uint32_t * f_idx, a_uint32_t * f_nr, - a_uint32_t * f_size) -{ - sw_error_t rv; - a_uint32_t i, cnt; - a_uint32_t idx, f_rsc, f_blk, dest_addr; - - _hsl_acl_blk_dump(dev_id, "_hsl_acl_right_defrag before defrag"); - - f_rsc = 0; - for (idx = p_idx; idx < acl_pool[dev_id].used_blk; idx++) - { - if (MEM_FREE == acl_pool[dev_id].blk_ent[idx].status) - { - f_rsc += acl_pool[dev_id].blk_ent[idx].size; - } - - if (t_size <= f_rsc) - { - break; - } - } - - if ((f_rsc < t_size) && (A_TRUE == b_must)) - { - return SW_NO_RESOURCE; - } - - if (0 == f_rsc) - { - *f_idx = p_idx; - *f_nr = 0; - *f_size = 0; - _hsl_acl_blk_dump(dev_id, "_hsl_acl_right_defrag after defrag"); - return SW_OK; - } - - if (idx >= acl_pool[dev_id].used_blk) - { - idx = acl_pool[dev_id].used_blk - 1; - } - - f_blk = 0; - f_rsc = 0; - dest_addr = acl_pool[dev_id].blk_ent[idx].addr - + acl_pool[dev_id].blk_ent[idx].size; - for (cnt = 0; cnt <= (idx -p_idx); cnt++) - { - i = idx - cnt; - if (MEM_FREE == acl_pool[dev_id].blk_ent[i].status) - { - f_blk += 1; - f_rsc += acl_pool[dev_id].blk_ent[i].size; - } - - if (MEM_USED == acl_pool[dev_id].blk_ent[i].status) - { - dest_addr -= acl_pool[dev_id].blk_ent[i].size; - - if (dest_addr != acl_pool[dev_id].blk_ent[i].addr) - { - /* update acl rules hardware position */ - rv = _hsl_acl_rule_copy(dev_id, - acl_pool[dev_id].blk_ent[i].addr, - dest_addr, - acl_pool[dev_id].blk_ent[i].size); - SW_RTN_ON_ERROR(rv); - - rv = _hsl_acl_addr_update(dev_id, - acl_pool[dev_id].blk_ent[i].addr, - dest_addr, - acl_pool[dev_id].blk_ent[i].info); - SW_RTN_ON_ERROR(rv); - - /* update acl memory block control infomation */ - acl_pool[dev_id].blk_ent[i + f_blk] = - acl_pool[dev_id].blk_ent[i]; - acl_pool[dev_id].blk_ent[i + f_blk].addr += f_rsc; - } - } - } - - for (i = p_idx; i < (p_idx + f_blk); i++) - { - acl_pool[dev_id].blk_ent[i].status = MEM_FREE; - acl_pool[dev_id].blk_ent[i].size = 0; - acl_pool[dev_id].blk_ent[i].addr = dest_addr - f_rsc; - } - acl_pool[dev_id].blk_ent[p_idx].size = f_rsc; - - *f_idx = p_idx; - *f_nr = f_blk; - *f_size = f_rsc; - rv = _hsl_acl_rule_invalid(dev_id, acl_pool[dev_id].blk_ent[*f_idx].addr, - f_rsc); - _hsl_acl_blk_dump(dev_id, "_hsl_acl_right_defrag after defrag"); - return rv; -} - -static sw_error_t -_hsl_acl_blk_alloc(a_uint32_t dev_id, a_uint32_t free_idx, a_uint32_t pri, - a_uint32_t size, a_uint32_t info, a_uint32_t * addr) -{ - sw_error_t rv; - a_uint32_t i; - a_bool_t b_comb = A_FALSE; - - _hsl_acl_blk_dump(dev_id, "_hsl_acl_blk_alloc before alloc"); - - if (MEM_FREE != acl_pool[dev_id].blk_ent[free_idx].status) - { - return SW_BAD_PARAM; - } - - if (size > acl_pool[dev_id].blk_ent[free_idx].size) - { - return SW_NO_RESOURCE; - } - - if (size != acl_pool[dev_id].blk_ent[free_idx].size) - { - b_comb = A_TRUE; - i = free_idx + 1; - rv = _hsl_acl_blk_ent_right_mv(dev_id, i, 1); - SW_RTN_ON_ERROR(rv); - - acl_pool[dev_id].blk_ent[i].addr = - acl_pool[dev_id].blk_ent[free_idx].addr + size; - acl_pool[dev_id].blk_ent[i].size = - acl_pool[dev_id].blk_ent[free_idx].size - size; - acl_pool[dev_id].blk_ent[i].status = MEM_FREE; - acl_pool[dev_id].blk_ent[i].pri = 0; - acl_pool[dev_id].blk_ent[i].info = 0; - } - - acl_pool[dev_id].blk_ent[free_idx].status = MEM_USED; - acl_pool[dev_id].blk_ent[free_idx].size = size; - acl_pool[dev_id].blk_ent[free_idx].pri = pri; - acl_pool[dev_id].blk_ent[free_idx].info = info; - acl_pool[dev_id].free_rsc -= size; - - if (A_TRUE == b_comb) - { - /* try to combine neighbor free memory blocks */ - rv = _hsl_acl_free_blk_comb(dev_id, free_idx + 1); - SW_RTN_ON_ERROR(rv); - } - - *addr = acl_pool[dev_id].blk_ent[free_idx].addr; - _hsl_acl_blk_dump(dev_id, "_hsl_acl_blk_alloc after alloc"); - return SW_OK; -} - -static sw_error_t -_hsl_acl_blk_reduce(a_uint32_t dev_id, a_uint32_t idx, a_uint32_t new_size) -{ - sw_error_t rv; - a_uint32_t addr, old_size; - - _hsl_acl_blk_dump(dev_id, "_hsl_acl_blk_reduce before reduce"); - - addr = acl_pool[dev_id].blk_ent[idx].addr; - old_size = acl_pool[dev_id].blk_ent[idx].size; - - rv = _hsl_acl_blk_ent_right_mv(dev_id, idx + 1, 1); - SW_RTN_ON_ERROR(rv); - - acl_pool[dev_id].blk_ent[idx].size = new_size; - acl_pool[dev_id].blk_ent[idx + 1].status = MEM_FREE; - acl_pool[dev_id].blk_ent[idx + 1].addr = addr + new_size; - acl_pool[dev_id].blk_ent[idx + 1].size = old_size - new_size; - acl_pool[dev_id].blk_ent[idx + 1].pri = 0; - acl_pool[dev_id].blk_ent[idx + 1].info = 0; - acl_pool[dev_id].free_rsc += (old_size - new_size); - - /* try to combine neighbor free blocks */ - rv = _hsl_acl_free_blk_comb(dev_id, idx + 1); - SW_RTN_ON_ERROR(rv); - - rv = _hsl_acl_rule_invalid(dev_id, addr + new_size, old_size - new_size); - _hsl_acl_blk_dump(dev_id, "_hsl_acl_blk_reduce after reduce"); - return rv; -} - -static sw_error_t -_hsl_acl_blk_left_enlarge(a_uint32_t dev_id, a_uint32_t idx, - a_uint32_t new_size) -{ - sw_error_t rv; - a_uint32_t old_size, old_addr, new_addr; - - _hsl_acl_blk_dump(dev_id, "_hsl_acl_blk_left_enlarge before enlarge"); - - if (0 == idx) - { - return SW_BAD_PARAM; - } - - if (MEM_FREE != acl_pool[dev_id].blk_ent[idx - 1].status) - { - return SW_BAD_PARAM; - } - - old_size = acl_pool[dev_id].blk_ent[idx].size; - if ((new_size - old_size) > acl_pool[dev_id].blk_ent[idx - 1].size) - { - return SW_BAD_PARAM; - } - - old_addr = acl_pool[dev_id].blk_ent[idx].addr; - new_addr = old_addr - (new_size - old_size); - rv = _hsl_acl_rule_copy(dev_id, old_addr, new_addr, old_size); - SW_RTN_ON_ERROR(rv); - - rv = _hsl_acl_rule_invalid(dev_id, new_addr + old_size, new_size - old_size); - SW_RTN_ON_ERROR(rv); - - acl_pool[dev_id].blk_ent[idx].size = new_size; - acl_pool[dev_id].blk_ent[idx].addr = new_addr; - acl_pool[dev_id].free_rsc -= (new_size - old_size); - rv = _hsl_acl_addr_update(dev_id, old_addr, new_addr, - acl_pool[dev_id].blk_ent[idx].info); - SW_RTN_ON_ERROR(rv); - - rv = SW_OK; - if ((new_size - old_size) == acl_pool[dev_id].blk_ent[idx - 1].size) - { - rv = _hsl_acl_blk_ent_left_mv(dev_id, idx, 1); - } - else - { - acl_pool[dev_id].blk_ent[idx - 1].size -= (new_size - old_size); - } - - _hsl_acl_blk_dump(dev_id, "_hsl_acl_blk_left_enlarge after enlarge"); - return rv; -} - -static sw_error_t -_hsl_acl_blk_right_enlarge(a_uint32_t dev_id, a_uint32_t idx, - a_uint32_t new_size) -{ - sw_error_t rv; - a_uint32_t old_size; - - _hsl_acl_blk_dump(dev_id, "_hsl_acl_blk_right_enlarge before enlarge"); - - if ((idx + 1) >= acl_pool[dev_id].used_blk) - { - return SW_BAD_PARAM; - } - - if (MEM_FREE != acl_pool[dev_id].blk_ent[idx + 1].status) - { - return SW_BAD_PARAM; - } - - old_size = acl_pool[dev_id].blk_ent[idx].size; - if ((new_size - old_size) > acl_pool[dev_id].blk_ent[idx + 1].size) - { - return SW_BAD_PARAM; - } - - acl_pool[dev_id].blk_ent[idx].size = new_size; - acl_pool[dev_id].free_rsc -= (new_size - old_size); - rv = SW_OK; - if ((new_size - old_size) < acl_pool[dev_id].blk_ent[idx + 1].size) - { - acl_pool[dev_id].blk_ent[idx + 1].size -= (new_size - old_size); - acl_pool[dev_id].blk_ent[idx + 1].addr += (new_size - old_size); - } - else - { - if ((idx + 2) < acl_pool[dev_id].used_blk) - { - rv = _hsl_acl_blk_ent_left_mv(dev_id, idx + 2, 1); - } - } - - _hsl_acl_blk_dump(dev_id, "_hsl_acl_blk_right_enlarge after enlarge"); - return rv; -} - -static sw_error_t -_hsl_acl_rule_copy(a_uint32_t dev_id, a_uint32_t src_addr, a_uint32_t dest_addr, - a_uint32_t size) -{ - hsl_acl_func_t * p_api; - sw_error_t rv; - - p_api = hsl_acl_ptr_get(dev_id); - SW_RTN_ON_NULL(p_api); - - if (NULL == p_api->acl_rule_copy) - return SW_NOT_SUPPORTED; - - rv = p_api->acl_rule_copy(dev_id, src_addr, dest_addr, size); - return rv; -} - -static sw_error_t -_hsl_acl_rule_invalid(a_uint32_t dev_id, a_uint32_t addr, a_uint32_t size) -{ - hsl_acl_func_t * p_api; - sw_error_t rv; - - p_api = hsl_acl_ptr_get(dev_id); - SW_RTN_ON_NULL(p_api); - - if (NULL == p_api->acl_rule_invalid) - return SW_NOT_SUPPORTED; - - rv = p_api->acl_rule_invalid(dev_id, addr, size); - return rv; -} - -static sw_error_t -_hsl_acl_addr_update(a_uint32_t dev_id, a_uint32_t old_addr, - a_uint32_t new_addr, a_uint32_t info) -{ - hsl_acl_func_t * p_api; - sw_error_t rv; - - p_api = hsl_acl_ptr_get(dev_id); - SW_RTN_ON_NULL(p_api); - - if (NULL == p_api->acl_addr_update) - return SW_NOT_SUPPORTED; - - rv = p_api->acl_addr_update(dev_id, old_addr, new_addr, info); - return rv; -} - -sw_error_t -hsl_acl_pool_creat(a_uint32_t dev_id, a_uint32_t blk_nr, a_uint32_t rsc_nr) -{ - HSL_DEV_ID_CHECK(dev_id); - - acl_pool[dev_id].blk_ent = aos_mem_alloc(blk_nr * (sizeof (hsl_acl_blk_t))); - if (NULL == acl_pool[dev_id].blk_ent) - { - return SW_NO_RESOURCE; - } - aos_mem_zero(acl_pool[dev_id].blk_ent, blk_nr * (sizeof (hsl_acl_blk_t))); - - acl_pool[dev_id].used_blk = 1; - acl_pool[dev_id].total_blk = blk_nr; - acl_pool[dev_id].free_rsc = rsc_nr; - - acl_pool[dev_id].blk_ent[0].addr = 0; - acl_pool[dev_id].blk_ent[0].size = rsc_nr; - acl_pool[dev_id].blk_ent[0].status = MEM_FREE; - - _hsl_acl_blk_dump(dev_id, "hsl_acl_pool_creat after creat"); - return SW_OK; -} - -sw_error_t -hsl_acl_pool_destroy(a_uint32_t dev_id) -{ - HSL_DEV_ID_CHECK(dev_id); - - if (NULL == acl_pool[dev_id].blk_ent) - { - return SW_FAIL; - } - - aos_mem_free(acl_pool[dev_id].blk_ent); - aos_mem_zero(&acl_pool[dev_id], sizeof(acl_pool[dev_id])); - return SW_OK; -} - -sw_error_t -hsl_acl_blk_alloc(a_uint32_t dev_id, a_uint32_t pri, a_uint32_t size, - a_uint32_t info, a_uint32_t * addr) -{ - sw_error_t rv; - a_uint32_t i; - a_uint32_t blk_nr; - a_uint32_t p_idx, largest_idx, prev_f_s, largest_f_s; - a_uint32_t l_idx, l_nr, l_size, r_idx, r_nr, r_size; - - HSL_DEV_ID_CHECK(dev_id); - - _hsl_acl_blk_dump(dev_id, "hsl_acl_blk_alloc before alloc"); - - if (0 == size) - { - return SW_BAD_PARAM; - } - - if (size > acl_pool[dev_id].free_rsc) - { - return SW_NO_RESOURCE; - } - - blk_nr = acl_pool[dev_id].used_blk; - - p_idx = 0; - prev_f_s = 0; - largest_f_s = 0; - largest_idx = 0; - - for (i = 0; i < blk_nr; i++) - { - if (MEM_FREE == acl_pool[dev_id].blk_ent[i].status) - { - prev_f_s += acl_pool[dev_id].blk_ent[i].size; - continue; - } - - p_idx = i; - if (pri <= acl_pool[dev_id].blk_ent[i].pri) - { - break; - } - } - - if (i == blk_nr) - { - p_idx = blk_nr; - } - - for (i = p_idx; i < blk_nr; i++) - { - if (MEM_FREE == acl_pool[dev_id].blk_ent[i].status) - { - if (largest_f_s < acl_pool[dev_id].blk_ent[i].size) - { - largest_idx = i; - largest_f_s = acl_pool[dev_id].blk_ent[i].size; - } - continue; - } - - if (pri != acl_pool[dev_id].blk_ent[i].pri) - { - break; - } - } - - if (largest_f_s >= size) - { - rv = _hsl_acl_blk_alloc(dev_id, largest_idx, pri, size, info, - addr); - - } - else if (prev_f_s >= size) - { - rv = _hsl_acl_blk_left_defrag(dev_id, p_idx, size, A_TRUE, &l_idx, - &l_nr, &l_size); - SW_RTN_ON_ERROR(rv); - - rv = _hsl_acl_blk_comb(dev_id, l_idx, l_nr); - SW_RTN_ON_ERROR(rv); - - rv = _hsl_acl_blk_alloc(dev_id, l_idx, pri, size, info, addr); - } - else if ((acl_pool[dev_id].free_rsc - prev_f_s) >= size) - { - rv = _hsl_acl_blk_right_defrag(dev_id, p_idx, size, A_TRUE, &r_idx, - &r_nr, &r_size); - SW_RTN_ON_ERROR(rv); - - rv = _hsl_acl_blk_comb(dev_id, r_idx, r_nr); - SW_RTN_ON_ERROR(rv); - - rv = _hsl_acl_blk_alloc(dev_id, r_idx, pri, size, info, addr); - } - else - { - rv = _hsl_acl_blk_left_defrag(dev_id, p_idx, size, A_FALSE, &l_idx, - &l_nr, &l_size); - SW_RTN_ON_ERROR(rv); - - rv = _hsl_acl_blk_right_defrag(dev_id, p_idx, size, A_FALSE, &r_idx, - &r_nr, &r_size); - SW_RTN_ON_ERROR(rv); - - rv = _hsl_acl_blk_comb(dev_id, l_idx, (l_nr + r_nr)); - SW_RTN_ON_ERROR(rv); - - rv = _hsl_acl_blk_alloc(dev_id, l_idx, pri, size, info, addr); - } - - _hsl_acl_blk_dump(dev_id, "hsl_acl_blk_alloc after alloc"); - return rv; -} - -sw_error_t -hsl_acl_blk_free(a_uint32_t dev_id, a_uint32_t addr) -{ - sw_error_t rv; - a_uint32_t idx; - - HSL_DEV_ID_CHECK(dev_id); - - _hsl_acl_blk_dump(dev_id, "hsl_acl_blk_free before free"); - - rv = _hsl_acl_blk_loc(dev_id, addr, &idx); - SW_RTN_ON_ERROR(rv); - - acl_pool[dev_id].blk_ent[idx].status = MEM_FREE; - acl_pool[dev_id].blk_ent[idx].pri = 0; - acl_pool[dev_id].blk_ent[idx].info = 0; - acl_pool[dev_id].free_rsc += acl_pool[dev_id].blk_ent[idx].size; - - rv = _hsl_acl_rule_invalid(dev_id, addr, acl_pool[dev_id].blk_ent[idx].size); - SW_RTN_ON_ERROR(rv); - - rv = _hsl_acl_free_blk_comb(dev_id, idx); - SW_RTN_ON_ERROR(rv); - - _hsl_acl_blk_dump(dev_id, "hsl_acl_blk_free after free"); - return SW_OK; -} - -sw_error_t -hsl_acl_blk_resize(a_uint32_t dev_id, a_uint32_t addr, a_uint32_t new_size) -{ - sw_error_t rv; - a_uint32_t idx, l_idx, l_nr, l_size, r_idx, r_nr, r_size, old_size; - - HSL_DEV_ID_CHECK(dev_id); - - _hsl_acl_blk_dump(dev_id, "hsl_acl_blk_resize before resize"); - - rv = _hsl_acl_blk_loc(dev_id, addr, &idx); - SW_RTN_ON_ERROR(rv); - - if (MEM_USED != acl_pool[dev_id].blk_ent[idx].status) - { - return SW_BAD_PARAM; - } - - old_size = acl_pool[dev_id].blk_ent[idx].size; - if (new_size == old_size) - { - return SW_OK; - } - - if (0 == new_size) - { - rv = hsl_acl_blk_free(dev_id, addr); - return rv; - } - - /* reduce acl memory block size */ - if (new_size < old_size) - { - rv = _hsl_acl_blk_reduce(dev_id, idx, new_size); - _hsl_acl_blk_dump(dev_id, "hsl_acl_blk_resize after resize"); - return rv; - } - - /* enlarge acl memory block size */ - if (acl_pool[dev_id].free_rsc < (new_size - old_size)) - { - return SW_NO_RESOURCE; - } - - rv = _hsl_acl_blk_left_defrag(dev_id, idx, new_size - old_size, - A_FALSE, &l_idx, &l_nr, &l_size); - SW_RTN_ON_ERROR(rv); - - rv = _hsl_acl_blk_comb(dev_id, l_idx, l_nr); - SW_RTN_ON_ERROR(rv); - - rv = _hsl_acl_blk_loc(dev_id, addr, &idx); - SW_RTN_ON_ERROR(rv); - - if (l_size >= (new_size - old_size)) - { - rv = _hsl_acl_blk_left_enlarge(dev_id, idx, new_size); - _hsl_acl_blk_dump(dev_id, "hsl_acl_blk_resize after resize"); - return rv; - } - - if (idx >= (acl_pool[dev_id].used_blk - 1)) - { - return SW_NO_RESOURCE; - } - rv = _hsl_acl_blk_right_defrag(dev_id, idx + 1, new_size - old_size, - A_FALSE, &r_idx, &r_nr, &r_size); - SW_RTN_ON_ERROR(rv); - - rv = _hsl_acl_blk_comb(dev_id, r_idx, r_nr); - SW_RTN_ON_ERROR(rv); - - rv = _hsl_acl_blk_loc(dev_id, addr, &idx); - SW_RTN_ON_ERROR(rv); - - if (r_size >= (new_size - old_size)) - { - rv = _hsl_acl_blk_right_enlarge(dev_id, idx, new_size); - _hsl_acl_blk_dump(dev_id, "hsl_acl_blk_resize after resize"); - return rv; - } - - rv = _hsl_acl_blk_right_enlarge(dev_id, idx, old_size + r_size); - SW_RTN_ON_ERROR(rv); - - rv = _hsl_acl_blk_left_enlarge(dev_id, idx, new_size); - _hsl_acl_blk_dump(dev_id, "hsl_acl_blk_resize after resize"); - return rv; -} - -sw_error_t -hsl_acl_free_rsc_get(a_uint32_t dev_id, a_uint32_t * free_rsc) -{ - HSL_DEV_ID_CHECK(dev_id); - - * free_rsc = acl_pool[dev_id].free_rsc; - return SW_OK; -} diff --git a/feeds/ipq807x/qca-ssdk/src/src/hsl/hsl_api.c b/feeds/ipq807x/qca-ssdk/src/src/hsl/hsl_api.c deleted file mode 100755 index aeb3d36e8..000000000 --- a/feeds/ipq807x/qca-ssdk/src/src/hsl/hsl_api.c +++ /dev/null @@ -1,42 +0,0 @@ -/* - * Copyright (c) 2012, The Linux Foundation. All rights reserved. - * Permission to use, copy, modify, and/or distribute this software for - * any purpose with or without fee is hereby granted, provided that the - * above copyright notice and this permission notice appear in all copies. - * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES - * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR - * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES - * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN - * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT - * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. - */ - - - -#include "sw.h" -#include "hsl_api.h" - -static hsl_api_t hsl_api_table[SW_MAX_NR_DEV]; - -hsl_api_t * -hsl_api_ptr_get(a_uint32_t dev_id) -{ - if (dev_id >= SW_MAX_NR_DEV) - return NULL; - - return &(hsl_api_table[dev_id]); -} - -sw_error_t -hsl_api_init(a_uint32_t dev_id) -{ - if (SW_MAX_NR_DEV <= dev_id) - { - return SW_BAD_PARAM; - } - - aos_mem_set(&hsl_api_table[dev_id], 0, sizeof (hsl_api_t)); - return SW_OK; -} - diff --git a/feeds/ipq807x/qca-ssdk/src/src/hsl/hsl_dev.c b/feeds/ipq807x/qca-ssdk/src/src/hsl/hsl_dev.c deleted file mode 100755 index ae9b98aca..000000000 --- a/feeds/ipq807x/qca-ssdk/src/src/hsl/hsl_dev.c +++ /dev/null @@ -1,705 +0,0 @@ -/* - * Copyright (c) 2012, 2017-2019, The Linux Foundation. All rights reserved. - * Permission to use, copy, modify, and/or distribute this software for - * any purpose with or without fee is hereby granted, provided that the - * above copyright notice and this permission notice appear in all copies. - * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES - * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR - * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES - * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN - * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT - * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. - */ - - -/*qca808x_start*/ -#include "sw.h" -#include "hsl.h" -#include "hsl_dev.h" -#include "hsl_lock.h" -#include "sd.h" -/*qca808x_end*/ -#if defined ATHENA -#include "athena_init.h" -#endif -#if defined GARUDA -#include "garuda_init.h" -#endif -#if defined SHIVA -#include "shiva_init.h" -#endif -#if defined HORUS -#include "horus_init.h" -#endif -#if defined ISIS -#include "isis_init.h" -#endif -#if defined ISISC -#include "isisc_init.h" -#endif -#if defined DESS -#include "dess_init.h" -#endif -#if defined HPPE -#include "hppe_init.h" -#endif -#if defined SCOMPHY -/*qca808x_start*/ -#include "scomphy_init.h" -/*qca808x_end*/ -#endif -/*qca808x_start*/ -#include "sw_api.h" -/*qca808x_end*/ -#ifdef KERNEL_MODULE -/*qca808x_start*/ -#include "sw_api_ks.h" -/*qca808x_end*/ -#else -#include "sw_api_us.h" -#endif -#include "ssdk_plat.h" -#ifdef MP -#include "hsl_phy.h" -#endif -/*qca808x_start*/ -static hsl_dev_t dev_table[SW_MAX_NR_DEV]; -static ssdk_init_cfg *dev_ssdk_cfg[SW_MAX_NR_DEV] = { 0 }; -ssdk_chip_type SSDK_CURRENT_CHIP_TYPE = CHIP_UNSPECIFIED; - -static sw_error_t hsl_set_current_chip_type(ssdk_chip_type chip_type) -{ - sw_error_t rv = SW_OK; - - SSDK_CURRENT_CHIP_TYPE = chip_type; - - if (SSDK_CURRENT_CHIP_TYPE == CHIP_UNSPECIFIED) - { -/*qca808x_end*/ -#if defined ATHENA - SSDK_CURRENT_CHIP_TYPE = CHIP_ATHENA; -#elif defined GARUDA - SSDK_CURRENT_CHIP_TYPE = CHIP_GARUDA; -#elif defined SHIVA - SSDK_CURRENT_CHIP_TYPE = CHIP_SHIVA; -#elif defined HORUS - SSDK_CURRENT_CHIP_TYPE = CHIP_HORUS; -#elif defined ISIS - SSDK_CURRENT_CHIP_TYPE = CHIP_ISIS; -#elif defined ISISC - SSDK_CURRENT_CHIP_TYPE = CHIP_ISISC; -#elif defined DESS - SSDK_CURRENT_CHIP_TYPE = CHIP_DESS; -#elif defined HPPE - SSDK_CURRENT_CHIP_TYPE = CHIP_HPPE; -#elif defined SCOMPHY -/*qca808x_start*/ - SSDK_CURRENT_CHIP_TYPE = CHIP_SCOMPHY; -/*qca808x_end*/ -#else - rv = SW_FAIL; -#endif -/*qca808x_start*/ - } - return rv; -} - -hsl_dev_t * -hsl_dev_ptr_get(a_uint32_t dev_id) -{ - if (dev_id >= SW_MAX_NR_DEV) - return NULL; - - return &dev_table[dev_id]; -} -/*qca808x_end*/ -hsl_acl_func_t * -hsl_acl_ptr_get(a_uint32_t dev_id) -{ - if (dev_id >= SW_MAX_NR_DEV) - return NULL; - - return &(dev_table[dev_id].acl_func); -} - -a_uint32_t hsl_dev_wan_port_get(a_uint32_t dev_id) -{ - if(dev_ssdk_cfg[dev_id]) { - return dev_ssdk_cfg[dev_id]->port_cfg.wan_bmp; - } - return 0; -} - -a_uint32_t hsl_dev_inner_ports_get(a_uint32_t dev_id) -{ - if(dev_ssdk_cfg[dev_id]) { - return dev_ssdk_cfg[dev_id]->port_cfg.inner_bmp; - } - return 0; -} - -/*qca808x_start*/ -sw_error_t -hsl_dev_init(a_uint32_t dev_id, ssdk_init_cfg *cfg) -{ - sw_error_t rv = SW_OK; - static int dev_init = 0; - - if (SW_MAX_NR_DEV <= dev_id) - { - return SW_BAD_PARAM; - } - - aos_mem_set(&dev_table[dev_id], 0, sizeof (hsl_dev_t)); - - if (!dev_init) { - SW_RTN_ON_ERROR(sd_init(dev_id,cfg)); - -#ifdef UK_IF - SW_RTN_ON_ERROR(sw_uk_init(cfg->nl_prot)); -#endif - -#if defined API_LOCK - SW_RTN_ON_ERROR(hsl_api_lock_init()); -#endif - dev_init = 1; - } - rv = hsl_set_current_chip_type(cfg->chip_type); - SW_RTN_ON_ERROR(rv); - - if (NULL == dev_ssdk_cfg[dev_id]) - { - dev_ssdk_cfg[dev_id] = aos_mem_alloc(sizeof (ssdk_init_cfg)); - } - - if (NULL == dev_ssdk_cfg[dev_id]) - { - return SW_OUT_OF_MEM; - } - - aos_mem_copy(dev_ssdk_cfg[dev_id], cfg, sizeof (ssdk_init_cfg)); -#if defined UK_MINOR_DEV - dev_ssdk_cfg[dev_id]->nl_prot = UK_MINOR_DEV; -#endif - - rv = SW_INIT_ERROR; - switch (cfg->chip_type) - { -/*qca808x_end*/ - case CHIP_ATHENA: -#if defined ATHENA - rv = athena_init(dev_id, cfg); -#endif - break; - - case CHIP_GARUDA: -#if defined GARUDA - rv = garuda_init(dev_id, cfg); -#endif - break; - - case CHIP_SHIVA: -#if defined SHIVA - rv = shiva_init(dev_id, cfg); -#endif - break; - - case CHIP_HORUS: -#if defined HORUS - rv = horus_init(dev_id, cfg); -#endif - break; - - case CHIP_ISIS: -#if defined ISIS - rv = isis_init(dev_id, cfg); -#endif - break; - case CHIP_ISISC: -#if defined ISISC - rv = isisc_init(dev_id, cfg); -#endif - break; - case CHIP_DESS: -#if defined DESS - rv = dess_init(dev_id, cfg); -#endif - break; - case CHIP_HPPE: -#if defined HPPE - rv = hppe_init(dev_id, cfg); -#endif - break; -/*qca808x_start*/ - case CHIP_SCOMPHY: -/*qca808x_end*/ -#if defined SCOMPHY -/*qca808x_start*/ - rv = scomphy_init(dev_id, cfg); -/*qca808x_end*/ -#endif -/*qca808x_start*/ - break; -/*qca808x_end*/ - case CHIP_UNSPECIFIED: -#if defined ATHENA - rv = athena_init(dev_id, cfg); -#elif defined GARUDA - rv = garuda_init(dev_id, cfg); -#elif defined SHIVA - rv = shiva_init(dev_id, cfg); -#elif defined HORUS - rv = horus_init(dev_id, cfg); -#elif defined ISIS - rv = isis_init(dev_id, cfg); -#elif defined ISISC - rv = isisc_init(dev_id, cfg); -#endif - break; -/*qca808x_start*/ - default: - return SW_BAD_PARAM; - } - - return rv; -} -/*qca808x_end*/ -sw_error_t -hsl_ssdk_cfg(a_uint32_t dev_id, ssdk_cfg_t *ssdk_cfg) -{ - if(!dev_ssdk_cfg[dev_id]) - { - SSDK_ERROR("the dev%d wasn't initialized\n", dev_id); - return SW_BAD_VALUE; - } - aos_mem_set(&(ssdk_cfg->init_cfg), 0, sizeof(ssdk_init_cfg)); - - aos_mem_copy(&(ssdk_cfg->init_cfg), dev_ssdk_cfg[dev_id], sizeof(ssdk_init_cfg)); - -#ifdef VERSION - aos_mem_copy(ssdk_cfg->build_ver, VERSION, sizeof(VERSION)); -#endif - -#ifdef BUILD_DATE - aos_mem_copy(ssdk_cfg->build_date, BUILD_DATE, sizeof(BUILD_DATE)); -#endif - - switch (dev_ssdk_cfg[dev_id]->chip_type) - { - case CHIP_ATHENA: - aos_mem_copy(ssdk_cfg->chip_type, "athena", sizeof("athena")); - break; - - case CHIP_GARUDA: - aos_mem_copy(ssdk_cfg->chip_type, "garuda", sizeof("garuda")); - break; - - case CHIP_SHIVA: - aos_mem_copy(ssdk_cfg->chip_type, "shiva", sizeof("shiva")); - break; - - case CHIP_HORUS: - aos_mem_copy(ssdk_cfg->chip_type, "horus", sizeof("horus")); - break; - - case CHIP_ISIS: - aos_mem_copy(ssdk_cfg->chip_type, "isis", sizeof("isis")); - break; - - case CHIP_ISISC: - aos_mem_copy(ssdk_cfg->chip_type, "isisc", sizeof("isisc")); - break; - - case CHIP_DESS: - aos_mem_copy(ssdk_cfg->chip_type, "dess", sizeof("dess")); - break; - - case CHIP_HPPE: - aos_mem_copy(ssdk_cfg->chip_type, "hppe", sizeof("hppe")); - break; - - case CHIP_SCOMPHY: -#ifdef MP - if(dev_ssdk_cfg[dev_id]->chip_revision == MP_GEPHY) - { - aos_mem_copy(ssdk_cfg->chip_type, "mp", sizeof("mp")); - } -#endif - break; - - case CHIP_UNSPECIFIED: -#if defined ATHENA - aos_mem_copy(ssdk_cfg->chip_type, "athena", sizeof("athena")); -#elif defined GARUDA - aos_mem_copy(ssdk_cfg->chip_type, "garuda", sizeof("garuda")); -#elif defined SHIVA - aos_mem_copy(ssdk_cfg->chip_type, "shiva", sizeof("shiva")); -#elif defined HORUS - aos_mem_copy(ssdk_cfg->chip_type, "horus", sizeof("horus")); -#elif defined ISIS - aos_mem_copy(ssdk_cfg->chip_type, "isis", sizeof("isis")); -#elif defined ISISC - aos_mem_copy(ssdk_cfg->chip_type, "isisc", sizeof("isisc")); -#endif - break; - - default: - return SW_BAD_PARAM; - } - -#ifdef CPU - aos_mem_copy(ssdk_cfg->cpu_type, CPU, sizeof(CPU)); -#endif - -#ifdef OS - aos_mem_copy(ssdk_cfg->os_info, OS, sizeof(OS)); -#if defined KVER26 - aos_mem_copy(ssdk_cfg->os_info+sizeof(OS)-1, " version 2.6", sizeof(" version 2.6")); -#elif defined KVER24 - aos_mem_copy(ssdk_cfg->os_info+sizeof(OS)-1, " version 2.4", sizeof(" version 2.4")); -#else - aos_mem_copy(ssdk_cfg->os_info+sizeof(OS)-1, " unknown", sizeof(" unknown")); -#endif -#endif - -#ifdef HSL_STANDALONG - ssdk_cfg->fal_mod = A_FALSE; -#else - ssdk_cfg->fal_mod = A_TRUE; -#endif - -#ifdef USER_MODE - ssdk_cfg->kernel_mode = A_FALSE; -#else - ssdk_cfg->kernel_mode = A_TRUE; -#endif - -#ifdef UK_IF - ssdk_cfg->uk_if = A_TRUE; -#else - ssdk_cfg->uk_if = A_FALSE; -#endif - -#ifdef IN_ACL - ssdk_cfg->features.in_acl = A_TRUE; -#endif -#ifdef IN_FDB - ssdk_cfg->features.in_fdb = A_TRUE; -#endif -#ifdef IN_IGMP - ssdk_cfg->features.in_igmp = A_TRUE; -#endif -#ifdef IN_LEAKY - ssdk_cfg->features.in_leaky = A_TRUE; -#endif -#ifdef IN_LED - ssdk_cfg->features.in_led = A_TRUE; -#endif -#ifdef IN_MIB - ssdk_cfg->features.in_mib = A_TRUE; -#endif -#ifdef IN_MIRROR - ssdk_cfg->features.in_mirror = A_TRUE; -#endif -#ifdef IN_MISC - ssdk_cfg->features.in_misc = A_TRUE; -#endif -#ifdef IN_PORTCONTROL - ssdk_cfg->features.in_portcontrol = A_TRUE; -#endif -#ifdef IN_PORTVLAN - ssdk_cfg->features.in_portvlan = A_TRUE; -#endif -#ifdef IN_QOS - ssdk_cfg->features.in_qos = A_TRUE; -#endif -#ifdef IN_RATE - ssdk_cfg->features.in_rate = A_TRUE; -#endif -#ifdef IN_STP - ssdk_cfg->features.in_stp = A_TRUE; -#endif -#ifdef IN_VLAN - ssdk_cfg->features.in_vlan = A_TRUE; -#endif -#ifdef IN_REDUCED_ACL - ssdk_cfg->features.in_reduced_acl = A_TRUE; -#endif -#ifdef IN_IP - ssdk_cfg->features.in_ip = A_TRUE; -#endif -#ifdef IN_NAT - ssdk_cfg->features.in_nat = A_TRUE; -#endif -#ifdef IN_COSMAP - ssdk_cfg->features.in_cosmap = A_TRUE; -#endif -#ifdef IN_SEC - ssdk_cfg->features.in_sec = A_TRUE; -#endif -#ifdef IN_TRUNK - ssdk_cfg->features.in_trunk = A_TRUE; -#endif -#ifdef IN_NAT_HELPER - ssdk_cfg->features.in_nathelper= A_TRUE; -#endif -#ifdef IN_INTERFACECONTROL - ssdk_cfg->features.in_interfacectrl= A_TRUE; -#endif - - return SW_OK; -} -/*qca808x_start*/ -sw_error_t -hsl_dev_cleanup(void) -{ - sw_error_t rv = SW_OK; - a_uint32_t dev_id; - - for (dev_id = 0; dev_id < SW_MAX_NR_DEV; dev_id++) - { - if (dev_ssdk_cfg[dev_id]) - { - hsl_api_t *p_api; - - SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id)); - if (p_api->dev_clean) - { - rv = p_api->dev_clean(dev_id); - SW_RTN_ON_ERROR(rv); - } - - aos_mem_free(dev_ssdk_cfg[dev_id]); - dev_ssdk_cfg[dev_id] = NULL; - } - } - -#ifdef UK_IF - SW_RTN_ON_ERROR(sw_uk_cleanup()); -#endif - - return SW_OK; -} -/*qca808x_end*/ -sw_error_t -hsl_access_mode_set(a_uint32_t dev_id, hsl_access_mode reg_mode) -{ - sw_error_t rv; - hsl_api_t *p_api; - - SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id)); - if (p_api->dev_access_set) - { - rv = p_api->dev_access_set(dev_id, reg_mode); - } - else - { - return SW_BAD_PARAM; - } - - return rv; -} - -sw_error_t reduce_hsl_reg_entry_get(a_uint32_t dev,a_uint32_t reg,a_uint8_t* value,a_uint8_t val_len) -{ - sw_error_t rv; - - hsl_api_t *p_api = hsl_api_ptr_get(dev); - if (p_api) { - rv = p_api->reg_get(dev, reg, (a_uint8_t*)value, (a_uint8_t)val_len); - } else { - rv = SW_NOT_INITIALIZED; - } - - return rv; -} - -sw_error_t reduce_hsl_reg_entry_set(a_uint32_t dev,a_uint32_t reg,a_uint8_t* value,a_uint8_t val_len) -{ - sw_error_t rv; - - hsl_api_t *p_api = hsl_api_ptr_get(dev); - if (p_api) { - rv = p_api->reg_set (dev, reg, - (a_uint8_t*)value, (a_uint8_t)val_len); - } else { - rv = SW_NOT_INITIALIZED; - } - - return rv; - -} - -sw_error_t reduce_hsl_reg_field_get(a_uint32_t dev,a_uint32_t reg,a_uint32_t reg_offset, - a_uint32_t reg_offset_len,a_uint8_t* value,a_uint8_t val_len) -{ - sw_error_t rv; - - hsl_api_t *p_api = hsl_api_ptr_get(dev); - if (p_api) { - rv = p_api->reg_field_get(dev, reg, reg_offset, reg_offset_len, (a_uint8_t*)value, val_len); - } else { - rv = SW_NOT_INITIALIZED; - } - return rv; -} - -sw_error_t reduce_hsl_reg_field_set(a_uint32_t dev,a_uint32_t reg,a_uint32_t reg_offset, - a_uint32_t reg_offset_len,a_uint8_t* value,a_uint8_t val_len) -{ - sw_error_t rv; - - hsl_api_t *p_api = hsl_api_ptr_get(dev); - if (p_api) { - rv = p_api->reg_field_set(dev, reg, - reg_offset, - reg_offset_len, (a_uint8_t*)value, val_len); - } else { - rv = SW_NOT_INITIALIZED; - } - return rv; -} - -sw_error_t reduce_hsl_reg_entry_gen_get(a_uint32_t dev,a_uint32_t addr,a_uint8_t* value,a_uint8_t val_len) -{ - sw_error_t rv; - - hsl_api_t *p_api = hsl_api_ptr_get(dev); - if (p_api) { - rv = p_api->reg_get(dev, addr, (a_uint8_t*)value, val_len); - } else { - rv = SW_NOT_INITIALIZED; - } - - return rv; -} - - -sw_error_t reduce_hsl_reg_entry_gen_set(a_uint32_t dev,a_uint32_t addr,a_uint8_t* value,a_uint8_t val_len) -{ - sw_error_t rv; - - hsl_api_t *p_api = hsl_api_ptr_get(dev); - if (p_api) { - rv = p_api->reg_set(dev, addr, (a_uint8_t*)value, val_len); - } else { - rv = SW_NOT_INITIALIZED; - } - - return rv; -} - -sw_error_t reduce_hsl_reg_field_gen_get(a_uint32_t dev,a_uint32_t reg_addr,a_uint32_t bitoffset, - a_uint32_t field_len,a_uint8_t* value,a_uint8_t val_len) -{ - sw_error_t rv; - - hsl_api_t *p_api = hsl_api_ptr_get(dev); - if (p_api) { - rv = p_api->reg_field_get(dev, reg_addr, - bitoffset, - field_len, (a_uint8_t*)value, val_len); - } else { - rv = SW_NOT_INITIALIZED; - } - return rv; -} - - -sw_error_t reduce_hsl_reg_field_gen_set(a_uint32_t dev,a_uint32_t regaddr,a_uint32_t bitoffset, - a_uint32_t bitlength,a_uint8_t* value,a_uint8_t val_len) -{ - sw_error_t rv; - - hsl_api_t *p_api = hsl_api_ptr_get(dev); - if (p_api) { - rv = p_api->reg_field_set(dev, regaddr, - bitoffset, - bitlength, (a_uint8_t*)value, val_len); - } else { - rv = SW_NOT_INITIALIZED; - } - return rv; -} - -/*qca808x_start*/ -sw_error_t reduce_hsl_phy_set(a_uint32_t dev,a_uint32_t phy_addr,a_uint32_t reg,a_uint16_t value) -{ - sw_error_t rv; - - hsl_api_t *p_api = hsl_api_ptr_get(dev); - if (p_api) { - rv = p_api->phy_set(dev, phy_addr, reg, value); - } else { - rv = SW_NOT_INITIALIZED; - } - - return rv; -} - -sw_error_t reduce_hsl_phy_get(a_uint32_t dev,a_uint32_t phy_addr,a_uint32_t reg,a_uint16_t* value) -{ - sw_error_t rv; - - hsl_api_t *p_api = hsl_api_ptr_get(dev); - if (p_api) { - rv = p_api->phy_get(dev, phy_addr, reg, value); - } else { - rv = SW_NOT_INITIALIZED; - } - - return rv; -} - -sw_error_t hsl_phy_i2c_set(a_uint32_t dev,a_uint32_t phy_addr,a_uint32_t reg,a_uint16_t value) -{ - sw_error_t rv; - - hsl_api_t *p_api = hsl_api_ptr_get(dev); - if (p_api) { - rv = p_api->phy_i2c_set(dev, phy_addr, reg, value); - } else { - rv = SW_NOT_INITIALIZED; - } - - return rv; -} - -sw_error_t hsl_phy_i2c_get(a_uint32_t dev,a_uint32_t phy_addr,a_uint32_t reg,a_uint16_t* value) -{ - sw_error_t rv; - - hsl_api_t *p_api = hsl_api_ptr_get(dev); - if (p_api) { - rv = p_api->phy_i2c_get(dev, phy_addr, reg, value); - } else { - rv = SW_NOT_INITIALIZED; - } - - return rv; -} - -#if 0 -void reduce_sw_set_reg_by_field_u32(unsigned int reg_value,unsigned int field_value, - unsigned int reg_offset,unsigned int reg_len) -{ - do { - (reg_value) = (((reg_value) & SW_FIELD_MASK_NOT_U32((reg_offset),(reg_offset))) - | (((field_value) & SW_BIT_MASK_U32(reg_len)) << (reg_offset))); - } while (0); - -} - - -void reduce_sw_field_get_by_reg_u32(unsigned int reg_value,unsigned int field_value, - unsigned int reg_offset,unsigned int reg_len) -{ - do { - (field_value) = (((reg_value) >> (reg_offset)) & SW_BIT_MASK_U32(reg_len)); - } while (0); - -} -#endif -/*qca808x_end*/ - diff --git a/feeds/ipq807x/qca-ssdk/src/src/hsl/hsl_lock.c b/feeds/ipq807x/qca-ssdk/src/src/hsl/hsl_lock.c deleted file mode 100755 index e9d454052..000000000 --- a/feeds/ipq807x/qca-ssdk/src/src/hsl/hsl_lock.c +++ /dev/null @@ -1,30 +0,0 @@ -/* - * Copyright (c) 2012, The Linux Foundation. All rights reserved. - * Permission to use, copy, modify, and/or distribute this software for - * any purpose with or without fee is hereby granted, provided that the - * above copyright notice and this permission notice appear in all copies. - * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES - * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR - * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES - * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN - * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT - * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. - */ - - - -#include "sw.h" - -#ifdef KVER32 -aos_lock_t sw_hsl_api_lock; -#else -aos_lock_t sw_hsl_api_lock = aos_default_unlock; -#endif - -sw_error_t -hsl_api_lock_init(void) -{ - aos_lock_init(&sw_hsl_api_lock); - return SW_OK; -} diff --git a/feeds/ipq807x/qca-ssdk/src/src/hsl/hsl_port_prop.c b/feeds/ipq807x/qca-ssdk/src/src/hsl/hsl_port_prop.c deleted file mode 100755 index b450fe40a..000000000 --- a/feeds/ipq807x/qca-ssdk/src/src/hsl/hsl_port_prop.c +++ /dev/null @@ -1,226 +0,0 @@ -/* - * Copyright (c) 2012, 2017, The Linux Foundation. All rights reserved. - * Permission to use, copy, modify, and/or distribute this software for - * any purpose with or without fee is hereby granted, provided that the - * above copyright notice and this permission notice appear in all copies. - * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES - * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR - * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES - * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN - * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT - * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. - */ - - - -#include "sw_config.h" -#include "aos_head.h" -#include "sw_error.h" -#include "shared_func.h" -#include "fal_type.h" -#include "hsl.h" -#include "hsl_dev.h" -#include "hsl_port_prop.h" -#include "hsl_phy.h" - - -typedef struct -{ - a_uint32_t phy_id[SW_MAX_NR_PORT]; - fal_pbmp_t dev_portmap; - fal_pbmp_t property[HSL_PP_BUTT]; -} port_info_t; - -static port_info_t *p_port_info[SW_MAX_NR_DEV] = { 0 }; - -a_bool_t -hsl_port_prop_check(a_uint32_t dev_id, fal_port_t port_id, - hsl_port_prop_t p_type) -{ - fal_pbmp_t pbitmap; - - if (dev_id >= SW_MAX_NR_DEV) - return A_FALSE; - - if (HSL_PP_BUTT <= p_type) - { - return A_FALSE; - } - - pbitmap = p_port_info[dev_id]->property[p_type]; - - return SW_IS_PBMP_MEMBER(pbitmap, port_id); -} - -a_bool_t -hsl_mports_prop_check(a_uint32_t dev_id, fal_pbmp_t port_bitmap, - hsl_port_prop_t p_type) -{ - fal_pbmp_t pbitmap; - - if (dev_id >= SW_MAX_NR_DEV) - return A_FALSE; - - if (HSL_PP_BUTT <= p_type) - { - return A_FALSE; - } - - pbitmap = p_port_info[dev_id]->property[p_type]; - - return (SW_IS_PBMP_INCLUDE(pbitmap, port_bitmap)); -} - -a_bool_t -hsl_port_validity_check(a_uint32_t dev_id, fal_port_t port_id) -{ - fal_pbmp_t pbitmap; - - if (dev_id >= SW_MAX_NR_DEV) - return A_FALSE; - - pbitmap = p_port_info[dev_id]->dev_portmap; - - return SW_IS_PBMP_MEMBER(pbitmap, port_id); -} - -a_bool_t -hsl_mports_validity_check(a_uint32_t dev_id, fal_pbmp_t port_bitmap) -{ - fal_pbmp_t pbitmap; - - if (dev_id >= SW_MAX_NR_DEV) - return A_FALSE; - - pbitmap = p_port_info[dev_id]->dev_portmap; - - return (SW_IS_PBMP_INCLUDE(pbitmap, port_bitmap)); -} - -sw_error_t -hsl_port_prop_set(a_uint32_t dev_id, fal_port_t port_id, hsl_port_prop_t p_type) -{ - HSL_DEV_ID_CHECK(dev_id); - - if (A_FALSE == hsl_port_validity_check(dev_id, port_id)) - { - return SW_OUT_OF_RANGE; - } - - if (HSL_PP_BUTT <= p_type) - { - return SW_BAD_PARAM; - } - - SW_PBMP_ADD_PORT(p_port_info[dev_id]->property[p_type], port_id); - - return SW_OK; -} - -sw_error_t -hsl_port_prop_clr(a_uint32_t dev_id, fal_port_t port_id, hsl_port_prop_t p_type) -{ - HSL_DEV_ID_CHECK(dev_id);; - - if (A_FALSE == hsl_port_validity_check(dev_id, port_id)) - { - return SW_OUT_OF_RANGE; - } - - if (HSL_PP_BUTT <= p_type) - { - return SW_BAD_PARAM; - } - - SW_PBMP_DEL_PORT(p_port_info[dev_id]->property[p_type], port_id); - - return SW_OK; -} - -sw_error_t -hsl_port_prop_get_phyid(a_uint32_t dev_id, fal_port_t port_id, - a_uint32_t * phy_id) -{ - HSL_DEV_ID_CHECK(dev_id); - HSL_PORT_ID_CHECK(port_id); - - if (A_FALSE == hsl_port_validity_check(dev_id, port_id)) - { - return SW_BAD_PARAM; - } - - *phy_id = qca_ssdk_port_to_phy_addr(dev_id, port_id); - - return SW_OK; -} - -sw_error_t -hsl_port_prop_set_phyid(a_uint32_t dev_id, fal_port_t port_id, a_uint32_t phy_id) -{ - HSL_DEV_ID_CHECK(dev_id); - HSL_PORT_ID_CHECK(port_id); - - if (A_FALSE == hsl_port_validity_check(dev_id, port_id)) - { - return SW_BAD_PARAM; - } - - p_port_info[dev_id]->phy_id[port_id] = phy_id; - return SW_OK; -} - -sw_error_t -hsl_port_prop_portmap_set(a_uint32_t dev_id, fal_port_t port_id) -{ - HSL_DEV_ID_CHECK(dev_id); - - if (port_id > SW_MAX_NR_PORT) - return SW_OUT_OF_RANGE; - - SW_PBMP_ADD_PORT(p_port_info[dev_id]->dev_portmap, port_id); - - return SW_OK; -} - -sw_error_t -hsl_port_prop_init_by_dev(a_uint32_t dev_id) -{ - port_info_t *p_mem; - - HSL_DEV_ID_CHECK(dev_id); - - p_mem = aos_mem_alloc(sizeof (port_info_t)); - if (p_mem == NULL) - return SW_OUT_OF_MEM; - - aos_mem_zero(p_mem, sizeof (port_info_t)); - p_port_info[dev_id] = p_mem; - - return SW_OK; -} - -sw_error_t -hsl_port_prop_cleanup_by_dev(a_uint32_t dev_id) -{ - HSL_DEV_ID_CHECK(dev_id); - - if (p_port_info[dev_id] != NULL) - aos_mem_free((void *)p_port_info[dev_id]); - - p_port_info[dev_id] = NULL; - - return SW_OK; -} - - -sw_error_t -hsl_port_prop_init(a_uint32_t dev_id) -{ - if (dev_id >= SW_MAX_NR_DEV) - return SW_BAD_VALUE; - - p_port_info[dev_id] = NULL; - - return SW_OK; -} diff --git a/feeds/ipq807x/qca-ssdk/src/src/hsl/isis/Makefile b/feeds/ipq807x/qca-ssdk/src/src/hsl/isis/Makefile deleted file mode 100755 index 2fa5d4bc3..000000000 --- a/feeds/ipq807x/qca-ssdk/src/src/hsl/isis/Makefile +++ /dev/null @@ -1,124 +0,0 @@ -LOC_DIR=src/hsl/isis -LIB=HSL - -include $(PRJ_PATH)/make/config.mk - -SRC_LIST=isis_reg_access.c isis_init.c - -ifeq (TRUE, $(IN_ACL)) - SRC_LIST += isis_acl.c isis_acl_parse.c isis_multicast_acl.c -endif - -ifeq (TRUE, $(IN_FDB)) - SRC_LIST += isis_fdb.c -endif - -ifeq (TRUE, $(IN_IGMP)) - SRC_LIST += isis_igmp.c -endif - -ifeq (TRUE, $(IN_LEAKY)) - SRC_LIST += isis_leaky.c -endif - -ifeq (TRUE, $(IN_LED)) - SRC_LIST += isis_led.c -endif - -ifeq (TRUE, $(IN_MIB)) - SRC_LIST += isis_mib.c -endif - -ifeq (TRUE, $(IN_MIRROR)) - SRC_LIST += isis_mirror.c -endif - -ifeq (TRUE, $(IN_MISC)) - SRC_LIST += isis_misc.c -endif - -ifeq (TRUE, $(IN_PORTCONTROL)) - SRC_LIST += isis_port_ctrl.c -endif - -ifeq (TRUE, $(IN_PORTVLAN)) - SRC_LIST += isis_portvlan.c -endif - -ifeq (TRUE, $(IN_QOS)) - SRC_LIST += isis_qos.c -endif - -ifeq (TRUE, $(IN_RATE)) - SRC_LIST += isis_rate.c -endif - -ifeq (TRUE, $(IN_STP)) - SRC_LIST += isis_stp.c -endif - -ifeq (TRUE, $(IN_VLAN)) - SRC_LIST += isis_vlan.c -endif - -ifeq (TRUE, $(IN_REDUCED_ACL)) - SRC_LIST += isis_reduced_acl.c -endif - -ifeq (TRUE, $(IN_COSMAP)) - SRC_LIST += isis_cosmap.c -endif - -ifeq (TRUE, $(IN_IP)) - SRC_LIST += isis_ip.c -endif - -ifeq (TRUE, $(IN_NAT)) - SRC_LIST += isis_nat.c -endif - -ifeq (TRUE, $(IN_NAT_HELPER)) - SRC_LIST += nat_helper_dt.c - SRC_LIST += nat_helper_hsl.c - SRC_LIST += nat_ipt_helper.c - SRC_LIST += napt_helper.c - SRC_LIST += host_helper.c - SRC_LIST += nat_helper.c - SRC_LIST += napt_acl.c - SRC_LIST += napt_procfs.c -endif - -ifeq (TRUE, $(IN_TRUNK)) - SRC_LIST += isis_trunk.c -endif - -ifeq (TRUE, $(IN_SEC)) - SRC_LIST += isis_sec.c -endif - -ifeq (TRUE, $(IN_INTERFACECONTROL)) - SRC_LIST += isis_interface_ctrl.c -endif - -ifeq (TRUE, $(IN_MACBLOCK)) - SRC_LIST += isis_mac_block.c -endif - - -ifeq (linux, $(OS)) - ifeq (KSLIB, $(MODULE_TYPE)) - ifneq (TRUE, $(KERNEL_MODE)) - SRC_LIST=isis_reg_access.c isis_init.c - endif - endif -endif - -ifeq (, $(filter ISIS, $(SUPPORT_CHIP))) - SRC_LIST= -endif - -include $(PRJ_PATH)/make/components.mk -include $(PRJ_PATH)/make/defs.mk -include $(PRJ_PATH)/make/target.mk - -all: dep obj diff --git a/feeds/ipq807x/qca-ssdk/src/src/hsl/isis/isis_acl.c b/feeds/ipq807x/qca-ssdk/src/src/hsl/isis/isis_acl.c deleted file mode 100755 index edca76acf..000000000 --- a/feeds/ipq807x/qca-ssdk/src/src/hsl/isis/isis_acl.c +++ /dev/null @@ -1,1904 +0,0 @@ -/* - * Copyright (c) 2012, 2016, 2018, The Linux Foundation. All rights reserved. - * Permission to use, copy, modify, and/or distribute this software for - * any purpose with or without fee is hereby granted, provided that the - * above copyright notice and this permission notice appear in all copies. - * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES - * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR - * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES - * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN - * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT - * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. - */ - - -/** - * @defgroup isis_acl ISIS_ACL - * @{ - */ -#include "sw.h" -#include "hsl.h" -#include "hsl_dev.h" -#include "hsl_acl.h" -#include "isis_acl.h" -#include "isis_reg.h" -#include "isis_acl_prv.h" - -//#define ISIS_ACL_DEBUG -//#define ISIS_SW_ENTRY -#define ISIS_HW_ENTRY - -static isis_acl_list_t *sw_list_ent[SW_MAX_NR_DEV]; -static isis_acl_rule_t *sw_rule_ent[SW_MAX_NR_DEV]; - -static isis_acl_rule_t *sw_rule_tmp[SW_MAX_NR_DEV]; -static isis_acl_rule_t *hw_rule_tmp[SW_MAX_NR_DEV]; -#ifdef ISIS_SW_ENTRY -static a_uint8_t *sw_filter_mem = NULL; -#endif - -static sw_error_t -_isis_filter_valid_set(a_uint32_t dev_id, a_uint32_t flt_idx, a_uint32_t flag); - -static sw_error_t -_isis_filter_ports_bind(a_uint32_t dev_id, a_uint32_t flt_idx, - a_uint32_t ports); - -#ifdef ISIS_SW_ENTRY -static sw_error_t -_isis_filter_write(a_uint32_t dev_id, a_uint32_t reg[], a_uint32_t flt_idx, - a_uint32_t op); - -static sw_error_t -_isis_filter_read(a_uint32_t dev_id, a_uint32_t reg[], a_uint32_t flt_idx, - a_uint32_t op); -#endif - -static sw_error_t -_isis_filter_down_to_hw(a_uint32_t dev_id, hw_filter_t * filter, - a_uint32_t flt_idx); - -static sw_error_t -_isis_filter_up_to_sw(a_uint32_t dev_id, hw_filter_t * filter, - a_uint32_t flt_idx); - -static void -_isis_acl_list_dump(a_uint32_t dev_id) -{ - a_uint32_t i; - isis_acl_list_t *sw_list; - - aos_printk("\ndev_id=%d list control infomation:", dev_id); - for (i = 0; i < ISIS_MAX_FILTER; i++) - { - sw_list = &(sw_list_ent[dev_id][i]); - if (ENT_USED & sw_list->status) - { - aos_printk - ("\nlist_id=%02d list_pri=%02d rule_nr=%02d [pts_map]:0x%02x idx=%02d ", - sw_list->list_id, sw_list->list_pri, sw_list->rule_nr, - sw_list->bind_pts, i); - } - } - aos_printk("\n"); -} - -static void -_isis_acl_sw_rule_dump(char *info, isis_acl_rule_t * sw_rule) -{ -#ifdef ISIS_ACL_DEBUG - a_uint32_t flt_idx, i; - - aos_printk("\n%s", info); - for (flt_idx = 0; flt_idx < ISIS_MAX_FILTER; flt_idx++) - { - aos_printk("\n%d software filter:", flt_idx); - aos_printk("\nact:"); - for (i = 0; i < 3; i++) - { - aos_printk("%08x ", sw_rule[flt_idx].filter.act[i]); - } - - aos_printk("\nvlu:"); - for (i = 0; i < 5; i++) - { - aos_printk("%08x ", sw_rule[flt_idx].filter.vlu[i]); - } - - aos_printk("\nmsk:"); - for (i = 0; i < 5; i++) - { - aos_printk("%08x ", sw_rule[flt_idx].filter.msk[i]); - } - - aos_printk("\nctl:status[%02d] list_id[%02d] rule_id[%02d]", - sw_rule[flt_idx].status, - sw_rule[flt_idx].list_id, sw_rule[flt_idx].rule_id); - - aos_printk("\n\n"); - } -#else - return; -#endif -} - -static isis_acl_list_t * -_isis_acl_list_loc(a_uint32_t dev_id, a_uint32_t list_id) -{ - a_uint32_t i; - - for (i = 0; i < ISIS_MAX_FILTER; i++) - { - if ((ENT_USED & sw_list_ent[dev_id][i].status) - && (list_id == sw_list_ent[dev_id][i].list_id)) - { - return &(sw_list_ent[dev_id][i]); - } - } - return NULL; -} - -static sw_error_t -_isis_filter_valid_set(a_uint32_t dev_id, a_uint32_t flt_idx, a_uint32_t flag) -{ -#ifdef ISIS_SW_ENTRY - hw_filter_t filter; - - _isis_filter_up_to_sw(dev_id, &filter, flt_idx); - - filter.msk[4] &= 0xfffffff8; - filter.msk[4] |= (flag & 0x7); - - _isis_filter_down_to_hw(dev_id, &filter, flt_idx); - - return SW_OK; -#else -#ifdef ISIS_HW_ENTRY - hw_filter_t filter; - - filter = sw_rule_ent[dev_id][flt_idx].filter; - - filter.msk[4] &= 0xfffffff8; - filter.msk[4] |= (flag & 0x7); - - _isis_filter_down_to_hw(dev_id, &filter, flt_idx); - return SW_OK; -#else - sw_error_t rv; - a_uint32_t addr, data = 0; - - /* read filter mask at first */ - addr = ISIS_RULE_FUNC_ADDR; - data = (flt_idx & 0x7f) | (0x1 << 8) | (0x1 << 10) | (0x1 << 31); - HSL_REG_ENTRY_GEN_SET(rv, dev_id, addr, sizeof (a_uint32_t), - (a_uint8_t *) (&data), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - - /* get filter mask and modify it */ - addr = ISIS_RULE_FUNC_ADDR + 20; - HSL_REG_ENTRY_GEN_GET(rv, dev_id, addr, sizeof (a_uint32_t), - (a_uint8_t *) (&data), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - - data &= 0xfffffff8; - data |= (flag & 0x7); - HSL_REG_ENTRY_GEN_SET(rv, dev_id, addr, sizeof (a_uint32_t), - (a_uint8_t *) (&data), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - - /* write back filter mask */ - addr = ISIS_RULE_FUNC_ADDR; - data = (flt_idx & 0x7f) | (0x1 << 8) | (0x1 << 31); - HSL_REG_ENTRY_GEN_SET(rv, dev_id, addr, sizeof (a_uint32_t), - (a_uint8_t *) (&data), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - - return SW_OK; -#endif -#endif -} - -static sw_error_t -_isis_filter_ports_bind(a_uint32_t dev_id, a_uint32_t flt_idx, a_uint32_t ports) -{ -#ifdef ISIS_SW_ENTRY - hw_filter_t filter; - - _isis_filter_up_to_sw(dev_id, &filter, flt_idx); - - filter.vlu[4] &= 0xffffff80; - filter.vlu[4] |= (ports & 0x7f); - - _isis_filter_down_to_hw(dev_id, &filter, flt_idx); - - return SW_OK; -#else -#ifdef ISIS_HW_ENTRY - hw_filter_t filter; - - filter = sw_rule_ent[dev_id][flt_idx].filter; - - filter.vlu[4] &= 0xffffff80; - filter.vlu[4] |= (ports & 0x7f); - - _isis_filter_down_to_hw(dev_id, &filter, flt_idx); - - return SW_OK; -#else - sw_error_t rv; - a_uint32_t addr, data; - - /* read filter value at first */ - addr = ISIS_RULE_FUNC_ADDR; - data = (flt_idx & 0x7f) | (0x1 << 10) | (0x1 << 31); - HSL_REG_ENTRY_GEN_SET(rv, dev_id, addr, sizeof (a_uint32_t), - (a_uint8_t *) (&data), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - - /* get filter value and modify it */ - addr = ISIS_RULE_FUNC_ADDR + 20; - HSL_REG_ENTRY_GEN_GET(rv, dev_id, addr, sizeof (a_uint32_t), - (a_uint8_t *) (&data), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - - data &= 0xffffff80; - data |= (ports & 0x7f); - HSL_REG_ENTRY_GEN_SET(rv, dev_id, addr, sizeof (a_uint32_t), - (a_uint8_t *) (&data), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - - /* write back filter value */ - addr = ISIS_RULE_FUNC_ADDR; - data = (flt_idx & 0x7f) | (0x1 << 31); - HSL_REG_ENTRY_GEN_SET(rv, dev_id, addr, sizeof (a_uint32_t), - (a_uint8_t *) (&data), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - - return SW_OK; -#endif -#endif -} - -#ifdef ISIS_SW_ENTRY -static sw_error_t -_isis_filter_write(a_uint32_t dev_id, a_uint32_t reg[], a_uint32_t flt_idx, - a_uint32_t op) -{ - a_uint32_t i, addr, data, idx = 6; - sw_error_t rv; - - if (ISIS_FILTER_ACT_OP == op) - { - idx = 4; - } - - for (i = 1; i < idx; i++) - { - addr = ISIS_RULE_FUNC_ADDR + (i << 2); - HSL_REG_ENTRY_GEN_SET(rv, dev_id, addr, sizeof (a_uint32_t), - (a_uint8_t *) (&(reg[i - 1])), - sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - } - - addr = ISIS_RULE_FUNC_ADDR; - data = (flt_idx & 0x7f) | (op << 8) | (0x1 << 31); - HSL_REG_ENTRY_GEN_SET(rv, dev_id, addr, sizeof (a_uint32_t), - (a_uint8_t *) (&data), sizeof (a_uint32_t)); - - return rv; -} - -static sw_error_t -_isis_filter_read(a_uint32_t dev_id, a_uint32_t reg[], a_uint32_t flt_idx, - a_uint32_t op) -{ - a_uint32_t i, addr, data, idx = 6; - sw_error_t rv; - - addr = ISIS_RULE_FUNC_ADDR; - data = (flt_idx & 0x7f) | (op << 8) | (0x1 << 10) | (0x1 << 31); - HSL_REG_ENTRY_GEN_SET(rv, dev_id, addr, sizeof (a_uint32_t), - (a_uint8_t *) (&data), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - - if (ISIS_FILTER_ACT_OP == op) - { - idx = 4; - } - - for (i = 1; i < idx; i++) - { - addr = ISIS_RULE_FUNC_ADDR + (i << 2); - HSL_REG_ENTRY_GEN_GET(rv, dev_id, addr, sizeof (a_uint32_t), - (a_uint8_t *) (&(reg[i - 1])), - sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - } - - return SW_OK; -} -#endif - -static sw_error_t -_isis_filter_down_to_hw(a_uint32_t dev_id, hw_filter_t * filter, - a_uint32_t flt_idx) -{ -#ifdef ISIS_SW_ENTRY - a_uint8_t *tbl = sw_filter_mem + sizeof (hw_filter_t) * flt_idx; - - aos_mem_copy(tbl, filter, sizeof (hw_filter_t)); -#else -#ifdef ISIS_HW_ENTRY - sw_error_t rv; - a_uint32_t i, base, addr; - - base = ISIS_FILTER_ACT_ADDR + (flt_idx << 4); - for (i = 0; i < 3; i++) - { - addr = base + (i << 2); - HSL_REG_ENTRY_GEN_SET(rv, dev_id, addr, sizeof (a_uint32_t), - (a_uint8_t *) (&(filter->act[i])), - sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - } - - base = ISIS_FILTER_VLU_ADDR + (flt_idx << 5); - for (i = 0; i < 5; i++) - { - addr = base + (i << 2); - HSL_REG_ENTRY_GEN_SET(rv, dev_id, addr, sizeof (a_uint32_t), - (a_uint8_t *) (&(filter->vlu[i])), - sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - } - - base = ISIS_FILTER_MSK_ADDR + (flt_idx << 5); - for (i = 0; i < 5; i++) - { - addr = base + (i << 2); - HSL_REG_ENTRY_GEN_SET(rv, dev_id, addr, sizeof (a_uint32_t), - (a_uint8_t *) (&(filter->msk[i])), - sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - } -#else - sw_error_t rv; - - rv = _isis_filter_write(dev_id, &(filter->act[0]), flt_idx, - ISIS_FILTER_ACT_OP); - SW_RTN_ON_ERROR(rv); - - rv = _isis_filter_write(dev_id, &(filter->vlu[0]), flt_idx, - ISIS_FILTER_VLU_OP); - SW_RTN_ON_ERROR(rv); - - rv = _isis_filter_write(dev_id, &(filter->msk[0]), flt_idx, - ISIS_FILTER_MSK_OP); - SW_RTN_ON_ERROR(rv); -#endif -#endif - - return SW_OK; -} - -static sw_error_t -_isis_filter_up_to_sw(a_uint32_t dev_id, hw_filter_t * filter, - a_uint32_t flt_idx) -{ -#ifdef ISIS_SW_ENTRY - a_uint8_t *tbl = sw_filter_mem + sizeof (hw_filter_t) * flt_idx; - - aos_mem_copy(filter, tbl, sizeof (hw_filter_t)); -#else -#ifdef ISIS_HW_ENTRY - sw_error_t rv; - a_uint32_t i, base, addr; - - base = ISIS_FILTER_VLU_ADDR + (flt_idx << 5); - for (i = 0; i < 5; i++) - { - addr = base + (i << 2); - HSL_REG_ENTRY_GEN_GET(rv, dev_id, addr, sizeof (a_uint32_t), - (a_uint8_t *) (&(filter->vlu[i])), - sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - } - - base = ISIS_FILTER_MSK_ADDR + (flt_idx << 5); - for (i = 0; i < 5; i++) - { - addr = base + (i << 2); - HSL_REG_ENTRY_GEN_GET(rv, dev_id, addr, sizeof (a_uint32_t), - (a_uint8_t *) (&(filter->msk[i])), - sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - } - - base = ISIS_FILTER_ACT_ADDR + (flt_idx << 4); - for (i = 0; i < 3; i++) - { - addr = base + (i << 2); - HSL_REG_ENTRY_GEN_GET(rv, dev_id, addr, sizeof (a_uint32_t), - (a_uint8_t *) (&(filter->act[i])), - sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - } -#else - sw_error_t rv; - - rv = _isis_filter_read(dev_id, &(filter->vlu[0]), flt_idx, - ISIS_FILTER_VLU_OP); - SW_RTN_ON_ERROR(rv); - - rv = _isis_filter_read(dev_id, &(filter->msk[0]), flt_idx, - ISIS_FILTER_MSK_OP); - SW_RTN_ON_ERROR(rv); - - rv = _isis_filter_read(dev_id, &(filter->act[0]), flt_idx, - ISIS_FILTER_ACT_OP); - SW_RTN_ON_ERROR(rv); -#endif -#endif - - return SW_OK; -} - -static sw_error_t -_isis_acl_list_insert(a_uint32_t dev_id, a_uint32_t * src_idx, - a_uint32_t * dst_idx, isis_acl_rule_t * src_rule, - isis_acl_rule_t * dst_rule) -{ - a_uint32_t i, data, rule_id, list_id, list_pri; - - rule_id = 0; - list_id = src_rule[*src_idx].list_id; - list_pri = src_rule[*src_idx].list_pri; - - for (i = *src_idx; i < ISIS_MAX_FILTER; i++) - { - if (!(ENT_USED & src_rule[i].status)) - { - continue; // was: break; - } - - if (src_rule[i].list_id != list_id) - { - break; - } - - SW_GET_FIELD_BY_REG(MAC_RUL_M4, RULE_TYP, data, - src_rule[i].filter.msk[4]); - if (!data) - { - continue; - } - - if (ISIS_MAX_FILTER <= *dst_idx) - { - return SW_NO_RESOURCE; - } - - if (ENT_USED & dst_rule[*dst_idx].status) - { - return SW_NO_RESOURCE; - } - - SW_GET_FIELD_BY_REG(MAC_RUL_M4, RULE_VALID, data, - src_rule[i].filter.msk[4]); - if ((FLT_START == data) && (*dst_idx % 2)) - { - if (*src_idx != i) - { - dst_rule[*dst_idx].list_id = list_id; - dst_rule[*dst_idx].list_pri = list_pri; - dst_rule[*dst_idx].rule_id = rule_id - 1; - dst_rule[*dst_idx].status |= ENT_USED; - } - - (*dst_idx)++; - if (ISIS_MAX_FILTER <= *dst_idx) - { - return SW_NO_RESOURCE; - } - - if (ENT_USED & dst_rule[*dst_idx].status) - { - return SW_NO_RESOURCE; - } - } - - aos_mem_copy(&(dst_rule[*dst_idx].filter), &(src_rule[i].filter), - sizeof (hw_filter_t)); - dst_rule[*dst_idx].list_id = list_id; - dst_rule[*dst_idx].list_pri = list_pri; - dst_rule[*dst_idx].rule_id = rule_id; - dst_rule[*dst_idx].status |= ENT_USED; - if (ENT_DEACTIVE & src_rule[i].status) - { - dst_rule[*dst_idx].status |= ENT_DEACTIVE; - } - (*dst_idx)++; - - if ((FLT_END == data) && (*dst_idx % 2)) - { - if (ISIS_MAX_FILTER > *dst_idx) - { - dst_rule[*dst_idx].list_id = list_id; - dst_rule[*dst_idx].list_pri = list_pri; - dst_rule[*dst_idx].rule_id = rule_id; - dst_rule[*dst_idx].status |= ENT_USED; - (*dst_idx)++; - } - } - - if ((FLT_END == data) || (FLT_STARTEND == data)) - { - rule_id++; - } - } - - *src_idx = i; - return SW_OK; -} - -static sw_error_t -_isis_acl_rule_alloc(a_uint32_t dev_id, isis_acl_list_t * sw_list, - a_uint32_t filter_nr) -{ - a_uint32_t free_flt_nr, load_idx, begin_idx, start_idx, end_idx, i; - a_uint32_t largest_nr, largest_idx; - sw_error_t rv; - - /* calculate the proper location, [start_idx, end_idx) */ - start_idx = 0; - end_idx = ISIS_MAX_FILTER; - for (i = 0; i < ISIS_MAX_FILTER; i++) - { - if (ENT_USED & sw_rule_ent[dev_id][i].status) - { - if (sw_rule_ent[dev_id][i].list_pri < sw_list->list_pri) - { - start_idx = i + 1; - } - else if (sw_rule_ent[dev_id][i].list_pri > sw_list->list_pri) - { - end_idx = i; - break; - } - } - } - - /* find the larget free filters block */ - largest_nr = 0; - largest_idx = 0; - free_flt_nr = 0; - begin_idx = start_idx; - for (i = start_idx; i < end_idx; i++) - { - if (!(ENT_USED & sw_rule_ent[dev_id][i].status)) - { - free_flt_nr++; - } - else - { - if (free_flt_nr > largest_nr) - { - largest_nr = free_flt_nr; - largest_idx = begin_idx; - } - free_flt_nr = 0; - begin_idx = i + 1; - } - } - - if (free_flt_nr > largest_nr) - { - largest_nr = free_flt_nr; - largest_idx = begin_idx; - } - - if ((!largest_nr) || ((largest_nr + 1) < filter_nr)) - { - return SW_NO_RESOURCE; - } - - for (i = 0; i < ISIS_MAX_FILTER; i++) - { - if (ENT_USED & sw_rule_ent[dev_id][i].status) - { - aos_mem_copy(&(sw_rule_tmp[dev_id][i]), &(sw_rule_ent[dev_id][i]), - sizeof (isis_acl_rule_t)); - } - } - - begin_idx = 0; - load_idx = largest_idx; - rv = _isis_acl_list_insert(dev_id, &begin_idx, &load_idx, - hw_rule_tmp[dev_id], sw_rule_tmp[dev_id]); - return rv; -} - -static sw_error_t -_isis_acl_rule_reorder(a_uint32_t dev_id, isis_acl_list_t * sw_list) -{ - a_uint32_t i, src_idx, dst_idx; - sw_error_t rv; - - dst_idx = 0; - for (i = 0; i < ISIS_MAX_FILTER;) - { - if (ENT_USED & sw_rule_ent[dev_id][i].status) - { - if (sw_rule_ent[dev_id][i].list_pri <= sw_list->list_pri) - { - rv = _isis_acl_list_insert(dev_id, &i, &dst_idx, - sw_rule_ent[dev_id], - sw_rule_tmp[dev_id]); - SW_RTN_ON_ERROR(rv); - } - else - { - break; - } - } - else - { - i++; - } - } - - src_idx = 0; - rv = _isis_acl_list_insert(dev_id, &src_idx, &dst_idx, hw_rule_tmp[dev_id], - sw_rule_tmp[dev_id]); - SW_RTN_ON_ERROR(rv); - - for (; i < ISIS_MAX_FILTER;) - { - if (ENT_USED & sw_rule_ent[dev_id][i].status) - { - rv = _isis_acl_list_insert(dev_id, &i, &dst_idx, - sw_rule_ent[dev_id], - sw_rule_tmp[dev_id]); - SW_RTN_ON_ERROR(rv); - } - else - { - i++; - } - } - - return SW_OK; -} - -static void -_isis_acl_rule_sync(a_uint32_t dev_id, a_uint32_t flt_idx, a_uint32_t flt_nr) -{ - a_uint32_t i, data; - - for (i = flt_idx; i < (flt_idx + flt_nr); i++) - { - if (aos_mem_cmp - (&(sw_rule_ent[dev_id][i]), &(sw_rule_tmp[dev_id][i]), - sizeof (isis_acl_rule_t))) - { - SW_GET_FIELD_BY_REG(MAC_RUL_M4, RULE_TYP, data, - sw_rule_tmp[dev_id][i].filter.msk[4]); - if (data) - { - _isis_filter_down_to_hw(dev_id, - &(sw_rule_tmp[dev_id][i].filter), i); - } - else - { - _isis_filter_valid_set(dev_id, i, 0); - } - - aos_mem_copy(&(sw_rule_ent[dev_id][i]), &(sw_rule_tmp[dev_id][i]), - sizeof (isis_acl_rule_t)); - } - } -} - -static sw_error_t -_isis_acl_list_creat(a_uint32_t dev_id, a_uint32_t list_id, a_uint32_t list_pri) -{ - a_uint32_t i, loc = ISIS_MAX_FILTER; - isis_acl_list_t *sw_list; - - HSL_DEV_ID_CHECK(dev_id); - - if ((ISIS_MAX_LIST_ID < list_id) || (ISIS_MAX_LIST_PRI < list_pri)) - { - return SW_NOT_SUPPORTED; - } - - for (i = 0; i < ISIS_MAX_FILTER; i++) - { - sw_list = &(sw_list_ent[dev_id][i]); - if (ENT_USED & sw_list->status) - { - if (list_id == sw_list->list_id) - { - return SW_ALREADY_EXIST; - } - } - else - { - loc = i; - } - } - - if (ISIS_MAX_FILTER == loc) - { - return SW_NO_RESOURCE; - } - - sw_list = &(sw_list_ent[dev_id][loc]); - aos_mem_zero(sw_list, sizeof (isis_acl_list_t)); - sw_list->list_id = list_id; - sw_list->list_pri = list_pri; - sw_list->status |= ENT_USED; - return SW_OK; -} - -static sw_error_t -_isis_acl_list_destroy(a_uint32_t dev_id, a_uint32_t list_id) -{ - isis_acl_list_t *sw_list; - - HSL_DEV_ID_CHECK(dev_id); - - if (ISIS_MAX_LIST_ID < list_id) - { - return SW_NOT_SUPPORTED; - } - - sw_list = _isis_acl_list_loc(dev_id, list_id); - if (NULL == sw_list) - { - return SW_NOT_FOUND; - } - - if (0 != sw_list->bind_pts) - { - return SW_NOT_SUPPORTED; - } - - if (0 != sw_list->rule_nr) - { - return SW_NOT_SUPPORTED; - } - - aos_mem_zero(sw_list, sizeof (isis_acl_list_t)); - return SW_OK; -} - -static sw_error_t -_isis_acl_rule_add(a_uint32_t dev_id, a_uint32_t list_id, - a_uint32_t rule_id, a_uint32_t rule_nr, - fal_acl_rule_t * rule) -{ - sw_error_t rv; - isis_acl_list_t *sw_list; - isis_acl_rule_t *sw_rule; - a_uint32_t i, free_flt_nr, old_flt_nr, old_flt_idx, new_flt_nr, bind_pts; - - HSL_DEV_ID_CHECK(dev_id); - - if (ISIS_MAX_LIST_ID < list_id) - { - return SW_NOT_SUPPORTED; - } - - if ((0 == rule_nr) || (NULL == rule)) - { - return SW_BAD_PARAM; - } - - sw_list = _isis_acl_list_loc(dev_id, list_id); - if (NULL == sw_list) - { - return SW_NOT_FOUND; - } - - if (rule_id != sw_list->rule_nr) - { - return SW_BAD_PARAM; - } - - old_flt_idx = 0; - old_flt_nr = 0; - free_flt_nr = 0; - aos_mem_zero(hw_rule_tmp[dev_id], - ISIS_HW_RULE_TMP_CNT * sizeof (isis_acl_rule_t)); - aos_mem_zero(sw_rule_tmp[dev_id], - ISIS_MAX_FILTER * sizeof (isis_acl_rule_t)); - for (i = 0; i < ISIS_MAX_FILTER; i++) - { - sw_rule = &(sw_rule_ent[dev_id][i]); - if (ENT_USED & sw_rule->status) - { - if (sw_rule->list_id == sw_list->list_id) - { - aos_mem_copy(&(hw_rule_tmp[dev_id][old_flt_nr]), sw_rule, - sizeof (isis_acl_rule_t)); - if (!old_flt_nr) - { - old_flt_idx = i; - } - old_flt_nr++; - } - } - else - { - free_flt_nr++; - } - } - - if (!free_flt_nr) - { - return SW_NO_RESOURCE; - } - - /* parse rule entry and alloc rule resource */ - new_flt_nr = old_flt_nr; - for (i = 0; i < rule_nr; i++) - { - rv = _isis_acl_rule_sw_to_hw(dev_id, &rule[i], hw_rule_tmp[dev_id], - &new_flt_nr); - SW_RTN_ON_ERROR(rv); - } - - if (free_flt_nr < (new_flt_nr - old_flt_nr)) - { - return SW_NO_RESOURCE; - } - - for (i = old_flt_nr; i < new_flt_nr; i++) - { - hw_rule_tmp[dev_id][i].status |= ENT_USED; - hw_rule_tmp[dev_id][i].list_id = sw_list->list_id; - hw_rule_tmp[dev_id][i].list_pri = sw_list->list_pri; - bind_pts = sw_list->bind_pts; - SW_SET_REG_BY_FIELD(MAC_RUL_V4, SRC_PT, bind_pts, - (hw_rule_tmp[dev_id][i].filter.vlu[4])); - } - - for (i = 0; i < old_flt_nr; i++) - { - sw_rule = &(sw_rule_ent[dev_id][old_flt_idx + i]); - sw_rule->status &= (~ENT_USED); - sw_rule->status |= (ENT_TMP); - } - - rv = _isis_acl_rule_alloc(dev_id, sw_list, new_flt_nr); - if (SW_OK != rv) - { - aos_mem_zero(sw_rule_tmp[dev_id], - ISIS_MAX_FILTER * sizeof (isis_acl_rule_t)); - rv = _isis_acl_rule_reorder(dev_id, sw_list); - } - - for (i = 0; i < old_flt_nr; i++) - { - sw_rule = &(sw_rule_ent[dev_id][i + old_flt_idx]); - sw_rule->status |= (ENT_USED); - sw_rule->status &= (~ENT_TMP); - } - SW_RTN_ON_ERROR(rv); - - _isis_acl_rule_sync(dev_id, 0, ISIS_MAX_FILTER); - sw_list->rule_nr += rule_nr; - - _isis_acl_sw_rule_dump("sw rule after add", sw_rule_ent[dev_id]); - return SW_OK; -} - -static sw_error_t -_isis_acl_rule_delete(a_uint32_t dev_id, a_uint32_t list_id, - a_uint32_t rule_id, a_uint32_t rule_nr) -{ - isis_acl_rule_t *sw_rule; - isis_acl_list_t *sw_list; - a_uint32_t i, flt_idx = 0, src_idx, dst_idx, del_nr = 0, flt_nr = 0; - sw_error_t rv; - - HSL_DEV_ID_CHECK(dev_id); - - if (ISIS_MAX_LIST_ID < list_id) - { - return SW_NOT_SUPPORTED; - } - - sw_list = _isis_acl_list_loc(dev_id, list_id); - if (NULL == sw_list) - { - return SW_NOT_FOUND; - } - - if (sw_list->rule_nr < (rule_id + rule_nr)) - { - return SW_BAD_PARAM; - } - - aos_mem_zero(hw_rule_tmp[dev_id], - ISIS_HW_RULE_TMP_CNT * sizeof (isis_acl_rule_t)); - aos_mem_zero(sw_rule_tmp[dev_id], - ISIS_MAX_FILTER * sizeof (isis_acl_rule_t)); - - for (i = 0; i < ISIS_MAX_FILTER; i++) - { - sw_rule = &(sw_rule_ent[dev_id][i]); - if ((ENT_USED & sw_rule->status) && (sw_rule->list_id == list_id)) - { - if (!flt_nr) - { - flt_idx = i; - } - - if ((sw_rule->rule_id >= rule_id) - && (sw_rule->rule_id < (rule_id + rule_nr))) - { - del_nr++; - } - else - { - aos_mem_copy(&(hw_rule_tmp[dev_id][flt_idx + flt_nr]), sw_rule, - sizeof (isis_acl_rule_t)); - } - flt_nr++; - } - } - - if (!del_nr) - { - return SW_NOT_FOUND; - } - - _isis_acl_sw_rule_dump("hw rule before del", hw_rule_tmp[dev_id]); - - for (i = 0; i < flt_nr; i++) - { - sw_rule = &(hw_rule_tmp[dev_id][flt_idx + i]); - if (ENT_USED & sw_rule->status) - { - break; - } - } - - if (i != flt_nr) - { - src_idx = flt_idx + i; - dst_idx = flt_idx; - rv = _isis_acl_list_insert(dev_id, &src_idx, &dst_idx, - hw_rule_tmp[dev_id], sw_rule_tmp[dev_id]); - SW_RTN_ON_ERROR(rv); - } - - _isis_acl_rule_sync(dev_id, flt_idx, flt_nr); - sw_list->rule_nr -= rule_nr; - - _isis_acl_sw_rule_dump("sw rule after del", sw_rule_ent[dev_id]); - return SW_OK; -} - -static sw_error_t -_isis_acl_rule_query(a_uint32_t dev_id, a_uint32_t list_id, - a_uint32_t rule_id, fal_acl_rule_t * rule) -{ - sw_error_t rv; - isis_acl_rule_t *sw_rule; - a_uint32_t flt_nr = 0, i; - - HSL_DEV_ID_CHECK(dev_id); - - if (ISIS_MAX_LIST_ID < list_id) - { - return SW_NOT_SUPPORTED; - } - - aos_mem_zero(hw_rule_tmp[dev_id], - ISIS_HW_RULE_TMP_CNT * sizeof (isis_acl_rule_t)); - for (i = 0; i < ISIS_MAX_FILTER; i++) - { - sw_rule = &(sw_rule_ent[dev_id][i]); - if (ENT_USED & sw_rule->status) - { - if ((sw_rule->list_id == list_id) && (sw_rule->rule_id == rule_id)) - { - aos_mem_copy(&(hw_rule_tmp[dev_id][flt_nr]), sw_rule, - sizeof (isis_acl_rule_t)); - flt_nr++; - } - } - } - - if (!flt_nr) - { - return SW_NOT_FOUND; - } - - aos_mem_zero(rule, sizeof (fal_acl_rule_t)); - rv = _isis_acl_rule_hw_to_sw(dev_id, rule, hw_rule_tmp[dev_id], 0, flt_nr); - return rv; -} - -static sw_error_t -_isis_acl_rule_bind(a_uint32_t dev_id, a_uint32_t list_id, a_uint32_t ports) -{ - sw_error_t rv; - a_uint32_t i; - isis_acl_rule_t *sw_rule; - - for (i = 0; i < ISIS_MAX_FILTER; i++) - { - sw_rule = &(sw_rule_ent[dev_id][i]); - - if ((ENT_USED & sw_rule->status) - && (list_id == sw_rule->list_id) - && (!(ENT_DEACTIVE & sw_rule->status))) - { - rv = _isis_filter_ports_bind(dev_id, i, ports); - SW_RTN_ON_ERROR(rv); - - SW_SET_REG_BY_FIELD(MAC_RUL_V4, SRC_PT, ports, - (sw_rule->filter.vlu[4])); - } - } - - return SW_OK; -} - -static sw_error_t -_isis_acl_list_bind(a_uint32_t dev_id, a_uint32_t list_id, - fal_acl_direc_t direc, fal_acl_bind_obj_t obj_t, - a_uint32_t obj_idx) -{ - sw_error_t rv; - a_uint32_t ports; - isis_acl_list_t *sw_list; - - HSL_DEV_ID_CHECK(dev_id); - - if (ISIS_MAX_LIST_ID < list_id) - { - return SW_NOT_SUPPORTED; - } - - if (FAL_ACL_DIREC_IN != direc) - { - return SW_NOT_SUPPORTED; - } - - sw_list = _isis_acl_list_loc(dev_id, list_id); - if (NULL == sw_list) - { - return SW_NOT_FOUND; - } - - if (FAL_ACL_BIND_PORT == obj_t) - { - ports = (sw_list->bind_pts) | (0x1 << obj_idx); - } - else if (FAL_ACL_BIND_PORTBITMAP == obj_t) - { - ports = (sw_list->bind_pts) | obj_idx; - } - else - { - return SW_NOT_SUPPORTED; - } - - rv = _isis_acl_rule_bind(dev_id, list_id, ports); - SW_RTN_ON_ERROR(rv); - - sw_list->bind_pts = ports; - return SW_OK; -} - -static sw_error_t -_isis_acl_list_unbind(a_uint32_t dev_id, a_uint32_t list_id, - fal_acl_direc_t direc, fal_acl_bind_obj_t obj_t, - a_uint32_t obj_idx) -{ - sw_error_t rv; - a_uint32_t ports; - isis_acl_list_t *sw_list; - - HSL_DEV_ID_CHECK(dev_id); - - if (ISIS_MAX_LIST_ID < list_id) - { - return SW_NOT_SUPPORTED; - } - - if (FAL_ACL_DIREC_IN != direc) - { - return SW_NOT_SUPPORTED; - } - - sw_list = _isis_acl_list_loc(dev_id, list_id); - if (NULL == sw_list) - { - return SW_NOT_FOUND; - } - - if (FAL_ACL_BIND_PORT == obj_t) - { - ports = (sw_list->bind_pts) & (~(0x1UL << obj_idx)); - } - else if (FAL_ACL_BIND_PORTBITMAP == obj_t) - { - ports = (sw_list->bind_pts) & (~obj_idx); - } - else - { - return SW_NOT_SUPPORTED; - } - - rv = _isis_acl_rule_bind(dev_id, list_id, ports); - SW_RTN_ON_ERROR(rv); - - sw_list->bind_pts = ports; - return SW_OK; -} - -static sw_error_t -_isis_acl_status_set(a_uint32_t dev_id, a_bool_t enable) -{ - sw_error_t rv; - a_uint32_t val; - - HSL_DEV_ID_CHECK(dev_id); - - if (A_TRUE == enable) - { - val = 1; - } - else if (A_FALSE == enable) - { - val = 0; - } - else - { - return SW_BAD_PARAM; - } - - HSL_REG_FIELD_SET(rv, dev_id, MOD_ENABLE, 0, ACL_EN, (a_uint8_t *) (&val), - sizeof (a_uint32_t)); - return rv; -} - -static sw_error_t -_isis_acl_status_get(a_uint32_t dev_id, a_bool_t * enable) -{ - sw_error_t rv; - a_uint32_t val = 0; - - HSL_DEV_ID_CHECK(dev_id); - - HSL_REG_FIELD_GET(rv, dev_id, MOD_ENABLE, 0, ACL_EN, (a_uint8_t *) (&val), - sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - - if (val) - { - *enable = A_TRUE; - } - else - { - *enable = A_FALSE; - } - - return SW_OK; -} - -static sw_error_t -_isis_acl_port_udf_profile_set(a_uint32_t dev_id, fal_port_t port_id, - fal_acl_udf_type_t udf_type, a_uint32_t offset, - a_uint32_t length) -{ - sw_error_t rv; - a_uint32_t reg = 0; - - HSL_DEV_ID_CHECK(dev_id); - - if (ISIS_UDF_MAX_OFFSET < offset) - { - return SW_BAD_PARAM; - } - - if (ISIS_UDF_MAX_OFFSET < length) - { - return SW_BAD_PARAM; - } - - if ((FAL_ACL_UDF_TYPE_L2_SNAP == udf_type) - || (FAL_ACL_UDF_TYPE_L3_PLUS == udf_type)) - { - HSL_REG_ENTRY_GET(rv, dev_id, WIN_RULE_CTL1, port_id, - (a_uint8_t *) (®), sizeof (a_uint32_t)); - } - else - { - HSL_REG_ENTRY_GET(rv, dev_id, WIN_RULE_CTL0, port_id, - (a_uint8_t *) (®), sizeof (a_uint32_t)); - } - SW_RTN_ON_ERROR(rv); - - switch (udf_type) - { - case FAL_ACL_UDF_TYPE_L2: - SW_SET_REG_BY_FIELD(WIN_RULE_CTL0, L2_OFFSET, offset, reg); - SW_SET_REG_BY_FIELD(WIN_RULE_CTL0, L2_LENGTH, length, reg); - break; - case FAL_ACL_UDF_TYPE_L3: - SW_SET_REG_BY_FIELD(WIN_RULE_CTL0, L3_OFFSET, offset, reg); - SW_SET_REG_BY_FIELD(WIN_RULE_CTL0, L3_LENGTH, length, reg); - break; - case FAL_ACL_UDF_TYPE_L4: - SW_SET_REG_BY_FIELD(WIN_RULE_CTL0, L4_OFFSET, offset, reg); - SW_SET_REG_BY_FIELD(WIN_RULE_CTL0, L4_LENGTH, length, reg); - break; - case FAL_ACL_UDF_TYPE_L2_SNAP: - SW_SET_REG_BY_FIELD(WIN_RULE_CTL1, L2S_OFFSET, offset, reg); - SW_SET_REG_BY_FIELD(WIN_RULE_CTL1, L2S_LENGTH, length, reg); - break; - case FAL_ACL_UDF_TYPE_L3_PLUS: - SW_SET_REG_BY_FIELD(WIN_RULE_CTL1, L3P_OFFSET, offset, reg); - SW_SET_REG_BY_FIELD(WIN_RULE_CTL1, L3P_LENGTH, length, reg); - break; - default: - return SW_BAD_PARAM; - } - - if ((FAL_ACL_UDF_TYPE_L2_SNAP == udf_type) - || (FAL_ACL_UDF_TYPE_L3_PLUS == udf_type)) - { - HSL_REG_ENTRY_SET(rv, dev_id, WIN_RULE_CTL1, port_id, - (a_uint8_t *) (®), sizeof (a_uint32_t)); - } - else - { - HSL_REG_ENTRY_SET(rv, dev_id, WIN_RULE_CTL0, port_id, - (a_uint8_t *) (®), sizeof (a_uint32_t)); - } - - return rv; -} - -static sw_error_t -_isis_acl_port_udf_profile_get(a_uint32_t dev_id, fal_port_t port_id, - fal_acl_udf_type_t udf_type, a_uint32_t * offset, - a_uint32_t * length) -{ - sw_error_t rv; - a_uint32_t reg = 0; - - HSL_DEV_ID_CHECK(dev_id); - - if ((FAL_ACL_UDF_TYPE_L2_SNAP == udf_type) - || (FAL_ACL_UDF_TYPE_L3_PLUS == udf_type)) - { - HSL_REG_ENTRY_GET(rv, dev_id, WIN_RULE_CTL1, port_id, - (a_uint8_t *) (®), sizeof (a_uint32_t)); - } - else - { - HSL_REG_ENTRY_GET(rv, dev_id, WIN_RULE_CTL0, port_id, - (a_uint8_t *) (®), sizeof (a_uint32_t)); - } - SW_RTN_ON_ERROR(rv); - - switch (udf_type) - { - case FAL_ACL_UDF_TYPE_L2: - SW_GET_FIELD_BY_REG(WIN_RULE_CTL0, L2_OFFSET, (*offset), reg); - SW_GET_FIELD_BY_REG(WIN_RULE_CTL0, L2_LENGTH, (*length), reg); - break; - case FAL_ACL_UDF_TYPE_L3: - SW_GET_FIELD_BY_REG(WIN_RULE_CTL0, L3_OFFSET, (*offset), reg); - SW_GET_FIELD_BY_REG(WIN_RULE_CTL0, L3_LENGTH, (*length), reg); - break; - case FAL_ACL_UDF_TYPE_L4: - SW_GET_FIELD_BY_REG(WIN_RULE_CTL0, L4_OFFSET, (*offset), reg); - SW_GET_FIELD_BY_REG(WIN_RULE_CTL0, L4_LENGTH, (*length), reg); - break; - case FAL_ACL_UDF_TYPE_L2_SNAP: - SW_GET_FIELD_BY_REG(WIN_RULE_CTL1, L2S_OFFSET, (*offset), reg); - SW_GET_FIELD_BY_REG(WIN_RULE_CTL1, L2S_LENGTH, (*length), reg); - break; - case FAL_ACL_UDF_TYPE_L3_PLUS: - SW_GET_FIELD_BY_REG(WIN_RULE_CTL1, L3P_OFFSET, (*offset), reg); - SW_GET_FIELD_BY_REG(WIN_RULE_CTL1, L3P_LENGTH, (*length), reg); - break; - default: - return SW_BAD_PARAM; - } - - return SW_OK; -} - -static sw_error_t -_isis_acl_rule_active(a_uint32_t dev_id, a_uint32_t list_id, - a_uint32_t rule_id, a_uint32_t rule_nr, a_bool_t active) -{ - sw_error_t rv; - a_uint32_t i, ports; - isis_acl_list_t *sw_list; - isis_acl_rule_t *sw_rule; - - HSL_DEV_ID_CHECK(dev_id); - - sw_list = _isis_acl_list_loc(dev_id, list_id); - if (NULL == sw_list) - { - return SW_NOT_FOUND; - } - - if (sw_list->rule_nr < (rule_id + rule_nr)) - { - return SW_BAD_PARAM; - } - - if (A_TRUE == active) - { - ports = (sw_list->bind_pts); - } - else - { - ports = 0; - } - - for (i = 0; i < ISIS_MAX_FILTER; i++) - { - sw_rule = &(sw_rule_ent[dev_id][i]); - - if ((ENT_USED & sw_rule->status) - && (list_id == sw_rule->list_id) - && (rule_id <= sw_rule->rule_id) - && ((rule_id + rule_nr) > sw_rule->rule_id)) - { - rv = _isis_filter_ports_bind(dev_id, i, ports); - SW_RTN_ON_ERROR(rv); - - SW_SET_REG_BY_FIELD(MAC_RUL_V4, SRC_PT, ports, - (sw_rule->filter.vlu[4])); - - if (A_TRUE == active) - { - sw_rule->status &= (~ENT_DEACTIVE); - } - else - { - sw_rule->status |= (ENT_DEACTIVE); - } - } - } - - return SW_OK; -} - -HSL_LOCAL sw_error_t -isis_acl_list_dump(a_uint32_t dev_id) -{ - _isis_acl_list_dump(dev_id); - return SW_OK; -} - -HSL_LOCAL sw_error_t -isis_acl_rule_dump(a_uint32_t dev_id) -{ - a_uint32_t flt_idx, i; - sw_error_t rv; - hw_filter_t filter; - - aos_printk("\nisis_acl_rule_dump:\n"); - - for (flt_idx = 0; flt_idx < ISIS_MAX_FILTER; flt_idx++) - { - aos_mem_zero(&filter, sizeof (hw_filter_t)); - - rv = _isis_filter_up_to_sw(dev_id, &filter, flt_idx); - if (SW_OK != rv) - { - continue; - } - - aos_printk("\n%d filter dump:", flt_idx); - - aos_printk("\nhardware content:"); - aos_printk("\nact:"); - for (i = 0; i < (sizeof (filter.act) / sizeof (a_uint32_t)); i++) - { - aos_printk("%08x ", filter.act[i]); - } - - aos_printk("\nvlu:"); - for (i = 0; i < (sizeof (filter.vlu) / sizeof (a_uint32_t)); i++) - { - aos_printk("%08x ", filter.vlu[i]); - } - - aos_printk("\nmsk:"); - for (i = 0; i < (sizeof (filter.msk) / sizeof (a_uint32_t)); i++) - { - aos_printk("%08x ", filter.msk[i]); - } - - aos_printk("\nsoftware content:"); - aos_printk("\nact:"); - for (i = 0; i < (sizeof (filter.act) / sizeof (a_uint32_t)); i++) - { - aos_printk("%08x ", sw_rule_ent[dev_id][flt_idx].filter.act[i]); - } - - aos_printk("\nvlu:"); - for (i = 0; i < (sizeof (filter.vlu) / sizeof (a_uint32_t)); i++) - { - aos_printk("%08x ", sw_rule_ent[dev_id][flt_idx].filter.vlu[i]); - } - - aos_printk("\nmsk:"); - for (i = 0; i < (sizeof (filter.msk) / sizeof (a_uint32_t)); i++) - { - aos_printk("%08x ", sw_rule_ent[dev_id][flt_idx].filter.msk[i]); - } - - aos_printk("\nctl:status[%02d] list_id[%02d] rule_id[%02d]", - sw_rule_ent[dev_id][flt_idx].status, - sw_rule_ent[dev_id][flt_idx].list_id, - sw_rule_ent[dev_id][flt_idx].rule_id); - - aos_printk("\n\n"); - } - - return SW_OK; -} - -sw_error_t -isis_acl_reset(a_uint32_t dev_id) -{ - HSL_DEV_ID_CHECK(dev_id); - - aos_mem_zero(sw_list_ent[dev_id], - ISIS_MAX_FILTER * sizeof (isis_acl_list_t)); - - aos_mem_zero(sw_rule_ent[dev_id], - ISIS_MAX_FILTER * sizeof (isis_acl_rule_t)); - - return SW_OK; -} - -/** - * @brief Creat an acl list - * @details Comments: - * If the value of list_pri is more small then the priority is more high, - * that means the list could be first matched. - * @param[in] dev_id device id - * @param[in] list_id acl list id - * @param[in] list_pri acl list priority - * @return SW_OK or error code - */ -sw_error_t -isis_acl_list_creat(a_uint32_t dev_id, a_uint32_t list_id, a_uint32_t list_pri) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _isis_acl_list_creat(dev_id, list_id, list_pri); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Destroy an acl list - * @param[in] dev_id device id - * @param[in] list_id acl list id - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -isis_acl_list_destroy(a_uint32_t dev_id, a_uint32_t list_id) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _isis_acl_list_destroy(dev_id, list_id); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Add one rule or more rules to an existing acl list - * @param[in] dev_id device id - * @param[in] list_id acl list id - * @param[in] rule_id first rule id of this adding operation in list - * @param[in] rule_nr rule number of this adding operation - * @param[in] rule rules content of this adding operation - * @return SW_OK or error code - */ -sw_error_t -isis_acl_rule_add(a_uint32_t dev_id, a_uint32_t list_id, - a_uint32_t rule_id, a_uint32_t rule_nr, fal_acl_rule_t * rule) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _isis_acl_rule_add(dev_id, list_id, rule_id, rule_nr, rule); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Delete one rule or more rules from an existing acl list - * @param[in] dev_id device id - * @param[in] list_id acl list id - * @param[in] rule_id first rule id of this deleteing operation in list - * @param[in] rule_nr rule number of this deleteing operation - * @return SW_OK or error code - */ -sw_error_t -isis_acl_rule_delete(a_uint32_t dev_id, a_uint32_t list_id, - a_uint32_t rule_id, a_uint32_t rule_nr) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _isis_acl_rule_delete(dev_id, list_id, rule_id, rule_nr); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Query one particular rule in a particular acl list - * @param[in] dev_id device id - * @param[in] list_id acl list id - * @param[in] rule_id first rule id of this deleteing operation in list - * @param[out] rule rule content of this operation - * @return SW_OK or error code - */ -sw_error_t -isis_acl_rule_query(a_uint32_t dev_id, a_uint32_t list_id, - a_uint32_t rule_id, fal_acl_rule_t * rule) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _isis_acl_rule_query(dev_id, list_id, rule_id, rule); - HSL_API_UNLOCK; - return rv; -} - -a_uint32_t -isis_acl_rule_get_offset(a_uint32_t dev_id, a_uint32_t list_id, a_uint32_t rule_id) -{ - a_uint32_t i, pos=0; - isis_acl_rule_t *sw_rule; - - for (i = 0; i < ISIS_MAX_FILTER; i++) - { - sw_rule = &(sw_rule_ent[0][i]); - - if ((ENT_USED & sw_rule->status) - && (list_id == sw_rule->list_id) && (sw_rule->rule_id == rule_id) - && (!(ENT_DEACTIVE & sw_rule->status))) - { - pos = i; - break; - - } - } - - return pos; -} - - -sw_error_t -isis_acl_rule_sync_multi_portmap(a_uint32_t dev_id, a_uint32_t pos, a_uint32_t *act) -{ - - HSL_DEV_ID_CHECK(dev_id); - - if (ISIS_MAX_LIST_ID < pos) - { - return SW_NOT_SUPPORTED; - } - - sw_rule_ent[dev_id][pos].filter.act[1] = act[1]; - sw_rule_ent[dev_id][pos].filter.act[2] = act[2]; - - sw_rule_tmp[dev_id][pos].filter.act[1] = act[1]; - sw_rule_tmp[dev_id][pos].filter.act[2] = act[2]; - - hw_rule_tmp[dev_id][pos].filter.act[1] = act[1]; - hw_rule_tmp[dev_id][pos].filter.act[2] = act[2]; - - - return SW_OK; -} - -/** - * @brief Bind an acl list to a particular object - * @details Comments: - * If obj_t equals FAL_ACL_BIND_PORT then obj_idx means port id - * @param[in] dev_id device id - * @param[in] list_id acl list id - * @param[in] direc direction of this binding operation - * @param[in] obj_t object type of this binding operation - * @param[in] obj_idx object index of this binding operation - * @return SW_OK or error code - */ -sw_error_t -isis_acl_list_bind(a_uint32_t dev_id, a_uint32_t list_id, - fal_acl_direc_t direc, fal_acl_bind_obj_t obj_t, - a_uint32_t obj_idx) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _isis_acl_list_bind(dev_id, list_id, direc, obj_t, obj_idx); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Unbind an acl list from a particular object - * @details Comments: - * If obj_t equals FAL_ACL_BIND_PORT then obj_idx means port id - * @param[in] dev_id device id - * @param[in] list_id acl list id - * @param[in] direc direction of this unbinding operation - * @param[in] obj_t object type of this unbinding operation - * @param[in] obj_idx object index of this unbinding operation - * @return SW_OK or error code - */ -sw_error_t -isis_acl_list_unbind(a_uint32_t dev_id, a_uint32_t list_id, - fal_acl_direc_t direc, fal_acl_bind_obj_t obj_t, - a_uint32_t obj_idx) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _isis_acl_list_unbind(dev_id, list_id, direc, obj_t, obj_idx); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Set working status of ACL engine on a particular device - * @param[in] dev_id device id - * @param[in] enable A_TRUE or A_FALSE - * @return SW_OK or error code - */ -sw_error_t -isis_acl_status_set(a_uint32_t dev_id, a_bool_t enable) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _isis_acl_status_set(dev_id, enable); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Get working status of ACL engine on a particular device - * @param[in] dev_id device id - * @param[out] enable A_TRUE or A_FALSE - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -isis_acl_status_get(a_uint32_t dev_id, a_bool_t * enable) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _isis_acl_status_get(dev_id, enable); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Set user define fields profile on a particular port - * @param[in] dev_id device id - * @param[in] port_id port id - * @param[in] udf_type udf type - * @param[in] offset udf offset - * @param[in] length udf length - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -isis_acl_port_udf_profile_set(a_uint32_t dev_id, fal_port_t port_id, - fal_acl_udf_type_t udf_type, a_uint32_t offset, - a_uint32_t length) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _isis_acl_port_udf_profile_set(dev_id, port_id, udf_type, offset, - length); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Get user define fields profile on a particular port - * @param[in] dev_id device id - * @param[in] port_id port id - * @param[in] udf_type udf type - * @param[out] offset udf offset - * @param[out] length udf length - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -isis_acl_port_udf_profile_get(a_uint32_t dev_id, fal_port_t port_id, - fal_acl_udf_type_t udf_type, a_uint32_t * offset, - a_uint32_t * length) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _isis_acl_port_udf_profile_get(dev_id, port_id, udf_type, offset, - length); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Active one or more rules in an existing acl list - * @param[in] dev_id device id - * @param[in] list_id acl list id - * @param[in] rule_id first rule id of this deactive operation in list - * @param[in] rule_nr rule number of this deactive operation - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -isis_acl_rule_active(a_uint32_t dev_id, a_uint32_t list_id, - a_uint32_t rule_id, a_uint32_t rule_nr) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _isis_acl_rule_active(dev_id, list_id, rule_id, rule_nr, A_TRUE); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Deactive one or more rules in an existing acl list - * @param[in] dev_id device id - * @param[in] list_id acl list id - * @param[in] rule_id first rule id of this deactive operation in list - * @param[in] rule_nr rule number of this deactive operation - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -isis_acl_rule_deactive(a_uint32_t dev_id, a_uint32_t list_id, - a_uint32_t rule_id, a_uint32_t rule_nr) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _isis_acl_rule_active(dev_id, list_id, rule_id, rule_nr, A_FALSE); - HSL_API_UNLOCK; - return rv; -} - -sw_error_t -isis_acl_init(a_uint32_t dev_id) -{ - HSL_DEV_ID_CHECK(dev_id); - - sw_list_ent[dev_id] = - (isis_acl_list_t *) aos_mem_alloc(ISIS_MAX_FILTER * - sizeof (isis_acl_list_t)); - if (NULL == sw_list_ent[dev_id]) - { - return SW_NO_RESOURCE; - } - aos_mem_zero(sw_list_ent[dev_id], - ISIS_MAX_FILTER * sizeof (isis_acl_list_t)); - - sw_rule_ent[dev_id] = - (isis_acl_rule_t *) aos_mem_alloc(ISIS_MAX_FILTER * - sizeof (isis_acl_rule_t)); - if (NULL == sw_rule_ent[dev_id]) - { - return SW_NO_RESOURCE; - } - aos_mem_zero(sw_rule_ent[dev_id], - ISIS_MAX_FILTER * sizeof (isis_acl_rule_t)); - - hw_rule_tmp[dev_id] = - (isis_acl_rule_t *) aos_mem_alloc(ISIS_HW_RULE_TMP_CNT * - sizeof (isis_acl_rule_t)); - if (NULL == hw_rule_tmp[dev_id]) - { - return SW_NO_RESOURCE; - } - - sw_rule_tmp[dev_id] = - (isis_acl_rule_t *) aos_mem_alloc(ISIS_MAX_FILTER * - sizeof (isis_acl_rule_t)); - if (NULL == sw_rule_tmp[dev_id]) - { - return SW_NO_RESOURCE; - } -#ifdef ISIS_SW_ENTRY - sw_filter_mem = aos_mem_alloc(ISIS_MAX_FILTER * sizeof (hw_filter_t)); - if (NULL == sw_filter_mem) - { - return SW_NO_RESOURCE; - } - aos_mem_zero(sw_filter_mem, ISIS_MAX_FILTER * sizeof (hw_filter_t)); -#endif - -#ifndef HSL_STANDALONG - { - hsl_api_t *p_api; - - SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id)); - - p_api->acl_list_creat = isis_acl_list_creat; - p_api->acl_list_destroy = isis_acl_list_destroy; - p_api->acl_list_bind = isis_acl_list_bind; - p_api->acl_list_unbind = isis_acl_list_unbind; - p_api->acl_rule_add = isis_acl_rule_add; - p_api->acl_rule_delete = isis_acl_rule_delete; - p_api->acl_rule_query = isis_acl_rule_query; - p_api->acl_status_set = isis_acl_status_set; - p_api->acl_status_get = isis_acl_status_get; - p_api->acl_list_dump = isis_acl_list_dump; - p_api->acl_rule_dump = isis_acl_rule_dump; - p_api->acl_port_udf_profile_set = isis_acl_port_udf_profile_set; - p_api->acl_port_udf_profile_get = isis_acl_port_udf_profile_get; - p_api->acl_rule_active = isis_acl_rule_active; - p_api->acl_rule_deactive = isis_acl_rule_deactive; - p_api->acl_rule_get_offset = isis_acl_rule_get_offset; - p_api->acl_rule_sync_multi_portmap = isis_acl_rule_sync_multi_portmap; - } -#endif - - return SW_OK; -} - -sw_error_t -isis_acl_cleanup(a_uint32_t dev_id) -{ - HSL_DEV_ID_CHECK(dev_id); - - if (NULL != sw_list_ent[dev_id]) - { - aos_mem_free(sw_list_ent[dev_id]); - } - - if (NULL != sw_rule_ent[dev_id]) - { - aos_mem_free(sw_rule_ent[dev_id]); - } - - if (NULL != hw_rule_tmp[dev_id]) - { - aos_mem_free(hw_rule_tmp[dev_id]); - } - - if (NULL != sw_rule_tmp[dev_id]) - { - aos_mem_free(sw_rule_tmp[dev_id]); - } -#ifdef DESS_SW_ENTRY - if (NULL != sw_filter_mem) - { - aos_mem_free(sw_filter_mem); - } -#endif - - return SW_OK; -} -/** - * @} - */ - diff --git a/feeds/ipq807x/qca-ssdk/src/src/hsl/isis/isis_acl_parse.c b/feeds/ipq807x/qca-ssdk/src/src/hsl/isis/isis_acl_parse.c deleted file mode 100755 index 4c52671ef..000000000 --- a/feeds/ipq807x/qca-ssdk/src/src/hsl/isis/isis_acl_parse.c +++ /dev/null @@ -1,2452 +0,0 @@ -/* - * Copyright (c) 2012, The Linux Foundation. All rights reserved. - * Permission to use, copy, modify, and/or distribute this software for - * any purpose with or without fee is hereby granted, provided that the - * above copyright notice and this permission notice appear in all copies. - * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES - * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR - * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES - * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN - * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT - * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. - */ - - - -#include "sw.h" -#include "hsl.h" -#include "hsl_dev.h" -#include "hsl_acl.h" -#include "isis_acl.h" -#include "isis_reg.h" -#include "isis_acl_prv.h" - -#define DAH 0x1 -#define SAH 0x2 -#define TAG 0x4 -#define STAG 0x8 -#define CTAG 0x10 - -typedef sw_error_t(*parse_func_t) (fal_acl_rule_t * sw, - hw_filter_t * hw_filter_snap, - a_bool_t * b_care); - -static a_bool_t -_isis_acl_zero_addr(const fal_mac_addr_t addr) -{ - a_uint32_t i; - - for (i = 0; i < 6; i++) - { - if (addr.uc[i]) - { - return A_FALSE; - } - } - return A_TRUE; -} - -static a_bool_t -_isis_acl_field_care(fal_acl_field_op_t op, a_uint32_t val, a_uint32_t mask, - a_uint32_t chkvlu) -{ - if (FAL_ACL_FIELD_MASK == op) - { - if (0 == mask) - return A_FALSE; - } - else if (FAL_ACL_FIELD_RANGE == op) - { - if ((0 == val) && (chkvlu == mask)) - return A_FALSE; - } - else if (FAL_ACL_FIELD_LE == op) - { - if (chkvlu == val) - return A_FALSE; - } - else if (FAL_ACL_FIELD_GE == op) - { - if (0 == val) - return A_FALSE; - } - else if (FAL_ACL_FIELD_NE == op) - { - return A_TRUE; - } - - return A_TRUE; -} - -static sw_error_t -_isis_acl_rule_bmac_parse(fal_acl_rule_t * sw, - hw_filter_t * hw, a_bool_t * b_care) -{ - a_uint32_t i; - - *b_care = A_FALSE; - aos_mem_zero(&(hw->vlu[0]), sizeof (hw->vlu)); - aos_mem_zero(&(hw->msk[0]), sizeof (hw->msk)); - - FIELD_SET_MASK(MAC_RUL_M4, RULE_TYP, ISIS_MAC_FILTER); - - if (FAL_FIELD_FLG_TST(sw->field_flg, FAL_ACL_FIELD_MAC_DA)) - { - if (A_TRUE != _isis_acl_zero_addr(sw->dest_mac_mask)) - { - *b_care = A_TRUE; - } - - for (i = 0; i < 6; i++) - { - sw->dest_mac_val.uc[i] &= sw->dest_mac_mask.uc[i]; - } - - FIELD_SET(MAC_RUL_V0, DAV_BYTE2, sw->dest_mac_val.uc[2]); - FIELD_SET(MAC_RUL_V0, DAV_BYTE3, sw->dest_mac_val.uc[3]); - FIELD_SET(MAC_RUL_V0, DAV_BYTE4, sw->dest_mac_val.uc[4]); - FIELD_SET(MAC_RUL_V0, DAV_BYTE5, sw->dest_mac_val.uc[5]); - FIELD_SET(MAC_RUL_V1, DAV_BYTE0, sw->dest_mac_val.uc[0]); - FIELD_SET(MAC_RUL_V1, DAV_BYTE1, sw->dest_mac_val.uc[1]); - - FIELD_SET_MASK(MAC_RUL_M0, DAM_BYTE2, sw->dest_mac_mask.uc[2]); - FIELD_SET_MASK(MAC_RUL_M0, DAM_BYTE3, sw->dest_mac_mask.uc[3]); - FIELD_SET_MASK(MAC_RUL_M0, DAM_BYTE4, sw->dest_mac_mask.uc[4]); - FIELD_SET_MASK(MAC_RUL_M0, DAM_BYTE5, sw->dest_mac_mask.uc[5]); - FIELD_SET_MASK(MAC_RUL_M1, DAM_BYTE0, sw->dest_mac_mask.uc[0]); - FIELD_SET_MASK(MAC_RUL_M1, DAM_BYTE1, sw->dest_mac_mask.uc[1]); - } - - if (FAL_FIELD_FLG_TST(sw->field_flg, FAL_ACL_FIELD_MAC_SA)) - { - if (A_TRUE != _isis_acl_zero_addr(sw->src_mac_mask)) - { - *b_care = A_TRUE; - } - - for (i = 0; i < 6; i++) - { - sw->src_mac_val.uc[i] &= sw->src_mac_mask.uc[i]; - } - - FIELD_SET(MAC_RUL_V1, SAV_BYTE4, sw->src_mac_val.uc[4]); - FIELD_SET(MAC_RUL_V1, SAV_BYTE5, sw->src_mac_val.uc[5]); - FIELD_SET(MAC_RUL_V2, SAV_BYTE0, sw->src_mac_val.uc[0]); - FIELD_SET(MAC_RUL_V2, SAV_BYTE1, sw->src_mac_val.uc[1]); - FIELD_SET(MAC_RUL_V2, SAV_BYTE2, sw->src_mac_val.uc[2]); - FIELD_SET(MAC_RUL_V2, SAV_BYTE3, sw->src_mac_val.uc[3]); - - FIELD_SET_MASK(MAC_RUL_M1, SAM_BYTE4, sw->src_mac_mask.uc[4]); - FIELD_SET_MASK(MAC_RUL_M1, SAM_BYTE5, sw->src_mac_mask.uc[5]); - FIELD_SET_MASK(MAC_RUL_M2, SAM_BYTE0, sw->src_mac_mask.uc[0]); - FIELD_SET_MASK(MAC_RUL_M2, SAM_BYTE1, sw->src_mac_mask.uc[1]); - FIELD_SET_MASK(MAC_RUL_M2, SAM_BYTE2, sw->src_mac_mask.uc[2]); - FIELD_SET_MASK(MAC_RUL_M2, SAM_BYTE3, sw->src_mac_mask.uc[3]); - } - - if (FAL_FIELD_FLG_TST(sw->field_flg, FAL_ACL_FIELD_MAC_ETHTYPE)) - { - if (0x0 != sw->ethtype_mask) - { - *b_care = A_TRUE; - } - - sw->ethtype_val &= sw->ethtype_mask; - FIELD_SET(MAC_RUL_V3, ETHTYPV, sw->ethtype_val); - FIELD_SET_MASK(MAC_RUL_M3, ETHTYPM, sw->ethtype_mask); - } - - if (FAL_FIELD_FLG_TST(sw->field_flg, FAL_ACL_FIELD_MAC_TAGGED)) - { - if (0x0 != sw->tagged_mask) - { - *b_care = A_TRUE; - } - - sw->tagged_val &= sw->tagged_mask; - FIELD_SET_MASK(MAC_RUL_M4, TAGGEDV, sw->tagged_val); - FIELD_SET_MASK(MAC_RUL_M4, TAGGEDM, sw->tagged_mask); - } - - if (FAL_FIELD_FLG_TST(sw->field_flg, FAL_ACL_FIELD_MAC_UP)) - { - if (0x0 != sw->up_mask) - { - *b_care = A_TRUE; - } - - sw->up_val &= sw->up_mask; - FIELD_SET(MAC_RUL_V3, VLANPRIV, sw->up_val); - FIELD_SET_MASK(MAC_RUL_M3, VLANPRIM, sw->up_mask); - } - - FIELD_SET_MASK(MAC_RUL_M4, VIDMSK, 1); - if (FAL_FIELD_FLG_TST(sw->field_flg, FAL_ACL_FIELD_MAC_VID)) - { - if ((FAL_ACL_FIELD_MASK != sw->vid_op) - && (FAL_ACL_FIELD_RANGE != sw->vid_op) - && (FAL_ACL_FIELD_LE != sw->vid_op) - && (FAL_ACL_FIELD_GE != sw->vid_op)) - { - return SW_NOT_SUPPORTED; - } - - if (A_TRUE == - _isis_acl_field_care(sw->vid_op, sw->vid_val, sw->vid_mask, - 0xfff)) - { - *b_care = A_TRUE; - } - - FIELD_SET_MASK(MAC_RUL_M4, VIDMSK, 0); - if (FAL_ACL_FIELD_MASK == sw->vid_op) - { - sw->vid_val &= sw->vid_mask; - FIELD_SET(MAC_RUL_V3, VLANIDV, sw->vid_val); - FIELD_SET_MASK(MAC_RUL_M3, VLANIDM, sw->vid_mask); - FIELD_SET_MASK(MAC_RUL_M4, VIDMSK, 1); - } - else if (FAL_ACL_FIELD_RANGE == sw->vid_op) - { - FIELD_SET(MAC_RUL_V3, VLANIDV, sw->vid_val); - FIELD_SET_MASK(MAC_RUL_M3, VLANIDM, sw->vid_mask); - } - else if (FAL_ACL_FIELD_LE == sw->vid_op) - { - FIELD_SET(MAC_RUL_V3, VLANIDV, 0); - FIELD_SET_MASK(MAC_RUL_M3, VLANIDM, sw->vid_val); - } - else - { - FIELD_SET(MAC_RUL_V3, VLANIDV, sw->vid_val); - FIELD_SET_MASK(MAC_RUL_M3, VLANIDM, 0xfff); - } - } - - if (FAL_FIELD_FLG_TST(sw->field_flg, FAL_ACL_FIELD_MAC_CFI)) - { - if (0x0 != sw->cfi_mask) - { - *b_care = A_TRUE; - } - - sw->cfi_val &= sw->cfi_mask; - FIELD_SET(MAC_RUL_V3, VLANCFIV, sw->cfi_val); - FIELD_SET_MASK(MAC_RUL_M3, VLANCFIM, sw->cfi_mask); - } - - if (FAL_FIELD_FLG_TST(sw->field_flg, FAL_ACL_FIELD_INVERSE_ALL)) - { - FIELD_SET(MAC_RUL_V4, RULE_INV, 1); - } - - return SW_OK; -} - -static sw_error_t -_isis_acl_rule_ehmac_parse(fal_acl_rule_t * sw, - hw_filter_t * hw, a_bool_t * b_care) -{ - a_uint32_t i; - a_bool_t da_h = A_FALSE, sa_h = A_FALSE; - - *b_care = A_FALSE; - aos_mem_zero(&(hw->vlu[0]), sizeof (hw->vlu)); - aos_mem_zero(&(hw->msk[0]), sizeof (hw->msk)); - - FIELD_SET_MASK(MAC_RUL_M4, RULE_TYP, ISIS_EHMAC_FILTER); - - if (FAL_FIELD_FLG_TST(sw->field_flg, FAL_ACL_FIELD_MAC_DA)) - { - for (i = 0; i < 3; i++) - { - if (sw->dest_mac_mask.uc[i]) - { - da_h = A_TRUE; - break; - } - } - } - - if (FAL_FIELD_FLG_TST(sw->field_flg, FAL_ACL_FIELD_MAC_SA)) - { - for (i = 0; i < 3; i++) - { - if (sw->src_mac_mask.uc[i]) - { - sa_h = A_TRUE; - break; - } - } - } - - /* if sa_h and da_h both are true need't process mac address fileds */ - if ((A_TRUE == da_h) && ((A_TRUE == sa_h))) - { - da_h = A_FALSE; - sa_h = A_FALSE; - } - - if (A_TRUE == da_h) - { - FIELD_SET(EHMAC_RUL_V3, DA_EN, 1); - - if (A_TRUE != _isis_acl_zero_addr(sw->dest_mac_mask)) - { - *b_care = A_TRUE; - } - - for (i = 0; i < 6; i++) - { - sw->dest_mac_val.uc[i] &= sw->dest_mac_mask.uc[i]; - } - - FIELD_SET(EHMAC_RUL_V0, DAV_BYTE2, sw->dest_mac_val.uc[2]); - FIELD_SET(EHMAC_RUL_V0, DAV_BYTE3, sw->dest_mac_val.uc[3]); - FIELD_SET(EHMAC_RUL_V0, DAV_BYTE4, sw->dest_mac_val.uc[4]); - FIELD_SET(EHMAC_RUL_V0, DAV_BYTE5, sw->dest_mac_val.uc[5]); - FIELD_SET(EHMAC_RUL_V1, DAV_BYTE0, sw->dest_mac_val.uc[0]); - FIELD_SET(EHMAC_RUL_V1, DAV_BYTE1, sw->dest_mac_val.uc[1]); - - FIELD_SET_MASK(EHMAC_RUL_M0, DAM_BYTE2, sw->dest_mac_mask.uc[2]); - FIELD_SET_MASK(EHMAC_RUL_M0, DAM_BYTE3, sw->dest_mac_mask.uc[3]); - FIELD_SET_MASK(EHMAC_RUL_M0, DAM_BYTE4, sw->dest_mac_mask.uc[4]); - FIELD_SET_MASK(EHMAC_RUL_M0, DAM_BYTE5, sw->dest_mac_mask.uc[5]); - FIELD_SET_MASK(EHMAC_RUL_M1, DAM_BYTE0, sw->dest_mac_mask.uc[0]); - FIELD_SET_MASK(EHMAC_RUL_M1, DAM_BYTE1, sw->dest_mac_mask.uc[1]); - - if (FAL_FIELD_FLG_TST(sw->field_flg, FAL_ACL_FIELD_MAC_SA)) - { - if (A_TRUE != _isis_acl_zero_addr(sw->src_mac_mask)) - { - *b_care = A_TRUE; - } - - for (i = 0; i < 6; i++) - { - sw->src_mac_val.uc[i] &= sw->src_mac_mask.uc[i]; - } - - FIELD_SET(EHMAC_RUL_V2, SAV_BYTE3, sw->src_mac_val.uc[3]); - FIELD_SET(EHMAC_RUL_V1, SAV_BYTE4, sw->src_mac_val.uc[4]); - FIELD_SET(EHMAC_RUL_V1, SAV_BYTE5, sw->src_mac_val.uc[5]); - - FIELD_SET_MASK(EHMAC_RUL_M2, SAM_BYTE3, sw->src_mac_mask.uc[3]); - FIELD_SET_MASK(EHMAC_RUL_M1, SAM_BYTE4, sw->src_mac_mask.uc[4]); - FIELD_SET_MASK(EHMAC_RUL_M1, SAM_BYTE5, sw->src_mac_mask.uc[5]); - } - } - - if (A_TRUE == sa_h) - { - if (A_TRUE != _isis_acl_zero_addr(sw->src_mac_mask)) - { - *b_care = A_TRUE; - } - - for (i = 0; i < 6; i++) - { - sw->src_mac_val.uc[i] &= sw->src_mac_mask.uc[i]; - } - - FIELD_SET(EHMAC_RUL_V0, DAV_BYTE2, sw->src_mac_val.uc[2]); - FIELD_SET(EHMAC_RUL_V0, DAV_BYTE3, sw->src_mac_val.uc[3]); - FIELD_SET(EHMAC_RUL_V0, DAV_BYTE4, sw->src_mac_val.uc[4]); - FIELD_SET(EHMAC_RUL_V0, DAV_BYTE5, sw->src_mac_val.uc[5]); - FIELD_SET(EHMAC_RUL_V1, DAV_BYTE0, sw->src_mac_val.uc[0]); - FIELD_SET(EHMAC_RUL_V1, DAV_BYTE1, sw->src_mac_val.uc[1]); - - FIELD_SET_MASK(EHMAC_RUL_M0, DAM_BYTE2, sw->src_mac_mask.uc[2]); - FIELD_SET_MASK(EHMAC_RUL_M0, DAM_BYTE3, sw->src_mac_mask.uc[3]); - FIELD_SET_MASK(EHMAC_RUL_M0, DAM_BYTE4, sw->src_mac_mask.uc[4]); - FIELD_SET_MASK(EHMAC_RUL_M0, DAM_BYTE5, sw->src_mac_mask.uc[5]); - FIELD_SET_MASK(EHMAC_RUL_M1, DAM_BYTE0, sw->src_mac_mask.uc[0]); - FIELD_SET_MASK(EHMAC_RUL_M1, DAM_BYTE1, sw->src_mac_mask.uc[1]); - - if (FAL_FIELD_FLG_TST(sw->field_flg, FAL_ACL_FIELD_MAC_DA)) - { - if (A_TRUE != _isis_acl_zero_addr(sw->dest_mac_mask)) - { - *b_care = A_TRUE; - } - - for (i = 0; i < 6; i++) - { - sw->dest_mac_val.uc[i] &= sw->dest_mac_mask.uc[i]; - } - - FIELD_SET(EHMAC_RUL_V2, SAV_BYTE3, sw->dest_mac_val.uc[3]); - FIELD_SET(EHMAC_RUL_V1, SAV_BYTE4, sw->dest_mac_val.uc[4]); - FIELD_SET(EHMAC_RUL_V1, SAV_BYTE5, sw->dest_mac_val.uc[5]); - - FIELD_SET_MASK(EHMAC_RUL_M2, SAM_BYTE3, sw->dest_mac_mask.uc[3]); - FIELD_SET_MASK(EHMAC_RUL_M1, SAM_BYTE4, sw->dest_mac_mask.uc[4]); - FIELD_SET_MASK(EHMAC_RUL_M1, SAM_BYTE5, sw->dest_mac_mask.uc[5]); - } - } - - if (FAL_FIELD_FLG_TST(sw->field_flg, FAL_ACL_FIELD_MAC_ETHTYPE)) - { - if (0x0 != sw->ethtype_mask) - { - *b_care = A_TRUE; - } - - sw->ethtype_val &= sw->ethtype_mask; - FIELD_SET(EHMAC_RUL_V3, ETHTYPV, sw->ethtype_val); - FIELD_SET_MASK(EHMAC_RUL_M3, ETHTYPM, sw->ethtype_mask); - } - - /* Process Stag Fields */ - if (FAL_FIELD_FLG_TST(sw->field_flg, FAL_ACL_FIELD_MAC_STAGGED)) - { - if (0x0 != sw->stagged_mask) - { - *b_care = A_TRUE; - } - - sw->stagged_val &= sw->stagged_mask; - FIELD_SET(EHMAC_RUL_V3, STAGGEDV, sw->stagged_val); - FIELD_SET(EHMAC_RUL_V3, STAGGEDM, sw->stagged_mask); - } - - FIELD_SET(EHMAC_RUL_V3, SVIDMSK, 1); - if (FAL_FIELD_FLG_TST(sw->field_flg, FAL_ACL_FIELD_MAC_STAG_VID)) - { - if ((FAL_ACL_FIELD_MASK != sw->stag_vid_op) - && (FAL_ACL_FIELD_RANGE != sw->stag_vid_op) - && (FAL_ACL_FIELD_LE != sw->stag_vid_op) - && (FAL_ACL_FIELD_GE != sw->stag_vid_op)) - { - return SW_NOT_SUPPORTED; - } - - if (A_TRUE == - _isis_acl_field_care(sw->stag_vid_op, sw->stag_vid_val, - sw->stag_vid_mask, 0xfff)) - { - *b_care = A_TRUE; - } - - FIELD_SET(EHMAC_RUL_V3, SVIDMSK, 0); - if (FAL_ACL_FIELD_MASK == sw->stag_vid_op) - { - sw->stag_vid_val &= sw->stag_vid_mask; - FIELD_SET(EHMAC_RUL_V2, STAG_VIDV, sw->stag_vid_val); - FIELD_SET_MASK(EHMAC_RUL_M2, STAG_VIDM, sw->stag_vid_mask); - FIELD_SET(EHMAC_RUL_V3, SVIDMSK, 1); - - } - else if (FAL_ACL_FIELD_RANGE == sw->stag_vid_op) - { - FIELD_SET(EHMAC_RUL_V2, STAG_VIDV, sw->stag_vid_val); - FIELD_SET_MASK(EHMAC_RUL_M2, STAG_VIDM, sw->stag_vid_mask); - - } - else if (FAL_ACL_FIELD_LE == sw->stag_vid_op) - { - FIELD_SET(EHMAC_RUL_V2, STAG_VIDV, 0); - FIELD_SET_MASK(EHMAC_RUL_M2, STAG_VIDM, sw->stag_vid_val); - - } - else - { - FIELD_SET(EHMAC_RUL_V2, STAG_VIDV, sw->stag_vid_val); - FIELD_SET_MASK(EHMAC_RUL_M2, STAG_VIDM, 0xfff); - } - } - - if (FAL_FIELD_FLG_TST(sw->field_flg, FAL_ACL_FIELD_MAC_STAG_PRI)) - { - if (0x0 != sw->stag_pri_mask) - { - *b_care = A_TRUE; - } - - sw->stag_pri_val &= sw->stag_pri_mask; - FIELD_SET(EHMAC_RUL_V2, STAG_PRIV, sw->stag_pri_val); - FIELD_SET_MASK(EHMAC_RUL_M2, STAG_PRIM, sw->stag_pri_mask); - } - - if (FAL_FIELD_FLG_TST(sw->field_flg, FAL_ACL_FIELD_MAC_STAG_DEI)) - { - if (0x0 != sw->stag_dei_mask) - { - *b_care = A_TRUE; - } - - sw->stag_dei_val &= sw->stag_dei_mask; - FIELD_SET(EHMAC_RUL_V2, STAG_DEIV, sw->stag_dei_val); - FIELD_SET_MASK(EHMAC_RUL_M2, STAG_DEIM, sw->stag_dei_mask); - } - - /* Process Ctag Fields */ - if (FAL_FIELD_FLG_TST(sw->field_flg, FAL_ACL_FIELD_MAC_CTAGGED)) - { - if (0x0 != sw->ctagged_mask) - { - *b_care = A_TRUE; - } - - sw->ctagged_val &= sw->ctagged_mask; - FIELD_SET_MASK(EHMAC_RUL_M4, CTAGGEDV, sw->ctagged_val); - FIELD_SET_MASK(EHMAC_RUL_M4, CTAGGEDM, sw->ctagged_mask); - } - - FIELD_SET_MASK(EHMAC_RUL_M4, CVIDMSK, 1); - if (FAL_FIELD_FLG_TST(sw->field_flg, FAL_ACL_FIELD_MAC_CTAG_VID)) - { - if ((FAL_ACL_FIELD_MASK != sw->ctag_vid_op) - && (FAL_ACL_FIELD_RANGE != sw->ctag_vid_op) - && (FAL_ACL_FIELD_LE != sw->ctag_vid_op) - && (FAL_ACL_FIELD_GE != sw->ctag_vid_op)) - { - return SW_NOT_SUPPORTED; - } - - if (A_TRUE == - _isis_acl_field_care(sw->ctag_vid_op, sw->ctag_vid_val, - sw->ctag_vid_mask, 0xfff)) - { - *b_care = A_TRUE; - } - - FIELD_SET_MASK(EHMAC_RUL_M4, CVIDMSK, 0); - if (FAL_ACL_FIELD_MASK == sw->ctag_vid_op) - { - sw->ctag_vid_val &= sw->ctag_vid_mask; - FIELD_SET(EHMAC_RUL_V2, CTAG_VIDLV, sw->ctag_vid_val); - FIELD_SET(EHMAC_RUL_V3, CTAG_VIDHV, (sw->ctag_vid_val >> 8)); - FIELD_SET_MASK(EHMAC_RUL_M2, CTAG_VIDLM, sw->ctag_vid_mask); - FIELD_SET_MASK(EHMAC_RUL_M3, CTAG_VIDHM, (sw->ctag_vid_mask >> 8)); - FIELD_SET_MASK(EHMAC_RUL_M4, CVIDMSK, 1); - - } - else if (FAL_ACL_FIELD_RANGE == sw->ctag_vid_op) - { - FIELD_SET(EHMAC_RUL_V2, CTAG_VIDLV, sw->ctag_vid_val); - FIELD_SET(EHMAC_RUL_V3, CTAG_VIDHV, (sw->ctag_vid_val >> 8)); - FIELD_SET_MASK(EHMAC_RUL_M2, CTAG_VIDLM, sw->ctag_vid_mask); - FIELD_SET_MASK(EHMAC_RUL_M3, CTAG_VIDHM, (sw->ctag_vid_mask >> 8)); - - } - else if (FAL_ACL_FIELD_LE == sw->ctag_vid_op) - { - FIELD_SET(EHMAC_RUL_V2, CTAG_VIDLV, 0); - FIELD_SET(EHMAC_RUL_V3, CTAG_VIDHV, 0); - FIELD_SET_MASK(EHMAC_RUL_M2, CTAG_VIDLM, sw->ctag_vid_val); - FIELD_SET_MASK(EHMAC_RUL_M3, CTAG_VIDHM, (sw->ctag_vid_val >> 8)); - - } - else - { - FIELD_SET(EHMAC_RUL_V2, CTAG_VIDLV, sw->ctag_vid_val); - FIELD_SET(EHMAC_RUL_V3, CTAG_VIDHV, (sw->ctag_vid_val >> 8)); - FIELD_SET_MASK(EHMAC_RUL_M2, CTAG_VIDLM, 0xff); - FIELD_SET_MASK(EHMAC_RUL_M3, CTAG_VIDHM, 0xf); - } - } - - if (FAL_FIELD_FLG_TST(sw->field_flg, FAL_ACL_FIELD_MAC_CTAG_PRI)) - { - if (0x0 != sw->ctag_pri_mask) - { - *b_care = A_TRUE; - } - - sw->ctag_pri_val &= sw->ctag_pri_mask; - FIELD_SET(EHMAC_RUL_V3, CTAG_PRIV, sw->ctag_pri_val); - FIELD_SET_MASK(EHMAC_RUL_M3, CTAG_PRIM, sw->ctag_pri_mask); - } - - if (FAL_FIELD_FLG_TST(sw->field_flg, FAL_ACL_FIELD_MAC_CTAG_CFI)) - { - if (0x0 != sw->ctag_cfi_mask) - { - *b_care = A_TRUE; - } - - sw->ctag_cfi_val &= sw->ctag_cfi_mask; - FIELD_SET(EHMAC_RUL_V3, CTAG_CFIV, sw->ctag_cfi_val); - FIELD_SET_MASK(EHMAC_RUL_M3, CTAG_CFIM, sw->ctag_cfi_mask); - } - - if (FAL_FIELD_FLG_TST(sw->field_flg, FAL_ACL_FIELD_INVERSE_ALL)) - { - FIELD_SET(MAC_RUL_V4, RULE_INV, 1); - } - - return SW_OK; -} - -static void -_isis_acl_rule_mac_preparse(fal_acl_rule_t * sw, a_bool_t * b_mac, - a_bool_t * eh_mac) -{ - a_uint32_t bm = 0, i, tmp; - - *b_mac = A_FALSE; - *eh_mac = A_FALSE; - if (FAL_FIELD_FLG_TST(sw->field_flg, FAL_ACL_FIELD_MAC_DA)) - { - for (i = 0; i < 3; i++) - { - if (sw->dest_mac_mask.uc[i]) - { - bm |= DAH; - break; - } - } - } - - if (FAL_FIELD_FLG_TST(sw->field_flg, FAL_ACL_FIELD_MAC_SA)) - { - for (i = 0; i < 3; i++) - { - if (sw->src_mac_mask.uc[i]) - { - bm |= SAH; - break; - } - } - } - - tmp = 0; - if (FAL_FIELD_FLG_TST(sw->field_flg, FAL_ACL_FIELD_MAC_TAGGED)) - { - tmp |= ((sw->tagged_mask & 0x1) << 16); - } - if (FAL_FIELD_FLG_TST(sw->field_flg, FAL_ACL_FIELD_MAC_UP)) - { - tmp |= ((sw->up_mask & 0x7) << 13); - } - if (FAL_FIELD_FLG_TST(sw->field_flg, FAL_ACL_FIELD_MAC_CFI)) - { - tmp |= ((sw->cfi_mask & 0x1) << 12); - } - if (FAL_FIELD_FLG_TST(sw->field_flg, FAL_ACL_FIELD_MAC_VID)) - { - if (A_TRUE == - _isis_acl_field_care(sw->vid_op, sw->vid_val, sw->vid_mask, - 0xfff)) - { - tmp |= 0xfff; - } - } - if (tmp) - { - bm |= TAG; - } - - tmp = 0; - if (FAL_FIELD_FLG_TST(sw->field_flg, FAL_ACL_FIELD_MAC_STAGGED)) - { - tmp |= ((sw->stagged_mask & 0x1) << 16); - } - if (FAL_FIELD_FLG_TST(sw->field_flg, FAL_ACL_FIELD_MAC_STAG_PRI)) - { - tmp |= ((sw->stag_pri_mask & 0x7) << 13); - } - if (FAL_FIELD_FLG_TST(sw->field_flg, FAL_ACL_FIELD_MAC_STAG_DEI)) - { - tmp |= ((sw->stag_dei_mask & 0x1) << 12); - } - if (FAL_FIELD_FLG_TST(sw->field_flg, FAL_ACL_FIELD_MAC_STAG_VID)) - { - if (A_TRUE == - _isis_acl_field_care(sw->stag_vid_op, sw->stag_vid_val, - sw->stag_vid_mask, 0xfff)) - { - tmp |= 0xfff; - } - } - if (tmp) - { - bm |= STAG; - } - - tmp = 0; - if (FAL_FIELD_FLG_TST(sw->field_flg, FAL_ACL_FIELD_MAC_CTAGGED)) - { - tmp |= ((sw->ctagged_mask & 0x1) << 16); - } - if (FAL_FIELD_FLG_TST(sw->field_flg, FAL_ACL_FIELD_MAC_CTAG_PRI)) - { - tmp |= ((sw->ctag_pri_mask & 0x7) << 13); - } - if (FAL_FIELD_FLG_TST(sw->field_flg, FAL_ACL_FIELD_MAC_CTAG_CFI)) - { - tmp |= ((sw->ctag_cfi_mask & 0x1) << 12); - } - if (FAL_FIELD_FLG_TST(sw->field_flg, FAL_ACL_FIELD_MAC_CTAG_VID)) - { - if (A_TRUE == - _isis_acl_field_care(sw->ctag_vid_op, sw->ctag_vid_val, - sw->ctag_vid_mask, 0xfff)) - { - tmp |= 0xfff; - } - } - if (tmp) - { - bm |= CTAG; - } - - if ((bm & CTAG) || (bm & STAG)) - { - *eh_mac = A_TRUE; - } - - if ((bm & TAG) || ((bm & DAH) && (bm & SAH))) - { - *b_mac = A_TRUE; - } -} - -static sw_error_t -_isis_acl_rule_ip4_parse(fal_acl_rule_t * sw, - hw_filter_t * hw, a_bool_t * b_care) -{ - *b_care = A_FALSE; - aos_mem_zero(&(hw->vlu[0]), sizeof (hw->vlu)); - aos_mem_zero(&(hw->msk[0]), sizeof (hw->msk)); - - FIELD_SET_MASK(MAC_RUL_M4, RULE_TYP, ISIS_IP4_FILTER); - - if (FAL_FIELD_FLG_TST(sw->field_flg, FAL_ACL_FIELD_IP_DSCP)) - { - if (0x0 != sw->ip_dscp_mask) - { - *b_care = A_TRUE; - } - - sw->ip_dscp_val &= sw->ip_dscp_mask; - FIELD_SET(IP4_RUL_V2, IP4DSCPV, sw->ip_dscp_val); - FIELD_SET_MASK(IP4_RUL_M2, IP4DSCPM, sw->ip_dscp_mask); - } - - if (FAL_FIELD_FLG_TST(sw->field_flg, FAL_ACL_FIELD_IP_PROTO)) - { - if (0x0 != sw->ip_proto_mask) - { - *b_care = A_TRUE; - } - - sw->ip_proto_val &= sw->ip_proto_mask; - FIELD_SET(IP4_RUL_V2, IP4PROTV, sw->ip_proto_val); - FIELD_SET_MASK(IP4_RUL_M2, IP4PROTM, sw->ip_proto_mask); - } - - if (FAL_FIELD_FLG_TST(sw->field_flg, FAL_ACL_FIELD_IP4_SIP)) - { - if (0x0 != sw->src_ip4_mask) - { - *b_care = A_TRUE; - } - sw->src_ip4_val &= sw->src_ip4_mask; - hw->vlu[1] = sw->src_ip4_val; - hw->msk[1] = sw->src_ip4_mask; - } - - if (FAL_FIELD_FLG_TST(sw->field_flg, FAL_ACL_FIELD_IP4_DIP)) - { - if (0x0 != sw->dest_ip4_mask) - { - *b_care = A_TRUE; - } - sw->dest_ip4_val &= sw->dest_ip4_mask; - hw->vlu[0] = sw->dest_ip4_val; - hw->msk[0] = sw->dest_ip4_mask; - } - - if ((FAL_FIELD_FLG_TST(sw->field_flg, FAL_ACL_FIELD_L4_SPORT)) - && ((FAL_FIELD_FLG_TST(sw->field_flg, FAL_ACL_FIELD_ICMP_TYPE)) - || (FAL_FIELD_FLG_TST(sw->field_flg, FAL_ACL_FIELD_ICMP_CODE)))) - { - return SW_BAD_PARAM; - } - - FIELD_SET_MASK(IP4_RUL_M3, IP4SPORTM_EN, 1); - if (FAL_FIELD_FLG_TST(sw->field_flg, FAL_ACL_FIELD_L4_SPORT)) - { - if ((FAL_ACL_FIELD_MASK != sw->src_l4port_op) - && (FAL_ACL_FIELD_RANGE != sw->src_l4port_op) - && (FAL_ACL_FIELD_LE != sw->src_l4port_op) - && (FAL_ACL_FIELD_GE != sw->src_l4port_op)) - { - return SW_NOT_SUPPORTED; - } - - if (A_FALSE == - _isis_acl_field_care(sw->src_l4port_op, sw->src_l4port_val, - sw->src_l4port_mask, 0xffff)) - { - if (FAL_ACL_FIELD_MASK == sw->src_l4port_op) - { - sw->src_l4port_op = FAL_ACL_FIELD_RANGE; - sw->src_l4port_val = 0; - sw->src_l4port_mask = 0xffff; - } - } - *b_care = A_TRUE; - - FIELD_SET_MASK(IP4_RUL_M3, IP4SPORTM_EN, 0); - if (FAL_ACL_FIELD_MASK == sw->src_l4port_op) - { - sw->src_l4port_val &= sw->src_l4port_mask; - FIELD_SET(IP4_RUL_V3, IP4SPORTV, sw->src_l4port_val); - FIELD_SET_MASK(IP4_RUL_M3, IP4SPORTM, sw->src_l4port_mask); - FIELD_SET_MASK(IP4_RUL_M3, IP4SPORTM_EN, 1); - } - else if (FAL_ACL_FIELD_RANGE == sw->src_l4port_op) - { - FIELD_SET(IP4_RUL_V3, IP4SPORTV, sw->src_l4port_val); - FIELD_SET_MASK(IP4_RUL_M3, IP4SPORTM, sw->src_l4port_mask); - } - else if (FAL_ACL_FIELD_LE == sw->src_l4port_op) - { - FIELD_SET(IP4_RUL_V3, IP4SPORTV, 0); - FIELD_SET_MASK(IP4_RUL_M3, IP4SPORTM, sw->src_l4port_val); - } - else - { - FIELD_SET(IP4_RUL_V3, IP4SPORTV, sw->src_l4port_val); - FIELD_SET_MASK(IP4_RUL_M3, IP4SPORTM, 0xffff); - } - } - - FIELD_SET_MASK(IP4_RUL_M3, IP4DPORTM_EN, 1); - if (FAL_FIELD_FLG_TST(sw->field_flg, FAL_ACL_FIELD_L4_DPORT)) - { - if ((FAL_ACL_FIELD_MASK != sw->dest_l4port_op) - && (FAL_ACL_FIELD_RANGE != sw->dest_l4port_op) - && (FAL_ACL_FIELD_LE != sw->dest_l4port_op) - && (FAL_ACL_FIELD_GE != sw->dest_l4port_op)) - { - return SW_NOT_SUPPORTED; - } - - if (A_FALSE == - _isis_acl_field_care(sw->dest_l4port_op, sw->dest_l4port_val, - sw->dest_l4port_mask, 0xffff)) - { - if (FAL_ACL_FIELD_MASK == sw->dest_l4port_op) - { - sw->dest_l4port_op = FAL_ACL_FIELD_RANGE; - sw->dest_l4port_val = 0; - sw->dest_l4port_mask = 0xffff; - } - } - *b_care = A_TRUE; - - FIELD_SET_MASK(IP4_RUL_M3, IP4DPORTM_EN, 0); - if (FAL_ACL_FIELD_MASK == sw->dest_l4port_op) - { - sw->dest_l4port_val &= sw->dest_l4port_mask; - FIELD_SET(IP4_RUL_V2, IP4DPORTV, sw->dest_l4port_val); - FIELD_SET_MASK(IP4_RUL_M2, IP4DPORTM, sw->dest_l4port_mask); - FIELD_SET_MASK(IP4_RUL_M3, IP4DPORTM_EN, 1); - } - else if (FAL_ACL_FIELD_RANGE == sw->dest_l4port_op) - { - FIELD_SET(IP4_RUL_V2, IP4DPORTV, sw->dest_l4port_val); - FIELD_SET_MASK(IP4_RUL_M2, IP4DPORTM, sw->dest_l4port_mask); - } - else if (FAL_ACL_FIELD_LE == sw->dest_l4port_op) - { - FIELD_SET(IP4_RUL_V2, IP4DPORTV, 0); - FIELD_SET_MASK(IP4_RUL_M2, IP4DPORTM, sw->dest_l4port_val); - } - else - { - FIELD_SET(IP4_RUL_V2, IP4DPORTV, sw->dest_l4port_val); - FIELD_SET_MASK(IP4_RUL_M2, IP4DPORTM, 0xffff); - } - } - - if (FAL_FIELD_FLG_TST(sw->field_flg, FAL_ACL_FIELD_ICMP_TYPE)) - { - if (0x0 != sw->icmp_type_mask) - { - *b_care = A_TRUE; - } - FIELD_SET(IP4_RUL_V3, ICMP_EN, 1); - - sw->icmp_type_val &= sw->icmp_type_mask; - FIELD_SET(IP4_RUL_V3, IP4ICMPTYPV, sw->icmp_type_val); - FIELD_SET_MASK(IP4_RUL_M3, IP4ICMPTYPM, sw->icmp_type_mask); - } - - if (FAL_FIELD_FLG_TST(sw->field_flg, FAL_ACL_FIELD_ICMP_CODE)) - { - if (0x0 != sw->icmp_code_mask) - { - *b_care = A_TRUE; - } - FIELD_SET(IP4_RUL_V3, ICMP_EN, 1); - - sw->icmp_code_val &= sw->icmp_code_mask; - FIELD_SET(IP4_RUL_V3, IP4ICMPCODEV, sw->icmp_code_val); - FIELD_SET_MASK(IP4_RUL_M3, IP4ICMPCODEM, sw->icmp_code_mask); - } - - if (FAL_FIELD_FLG_TST(sw->field_flg, FAL_ACL_FIELD_TCP_FLAG)) - { - if (0x0 != sw->tcp_flag_mask) - { - *b_care = A_TRUE; - } - - sw->tcp_flag_val &= sw->tcp_flag_mask; - FIELD_SET(IP4_RUL_V3, IP4TCPFLAGV, sw->tcp_flag_val); - FIELD_SET_MASK(IP4_RUL_M3, IP4TCPFLAGM, sw->tcp_flag_mask); - } - - if (FAL_FIELD_FLG_TST(sw->field_flg, FAL_ACL_FIELD_RIPV1)) - { - if (0x0 != sw->ripv1_mask) - { - *b_care = A_TRUE; - } - - sw->ripv1_val &= sw->ripv1_mask; - FIELD_SET(IP4_RUL_V3, IP4RIPV, sw->ripv1_val); - FIELD_SET_MASK(IP4_RUL_M3, IP4RIPM, sw->ripv1_mask); - } - - if (FAL_FIELD_FLG_TST(sw->field_flg, FAL_ACL_FIELD_DHCPV4)) - { - if (0x0 != sw->dhcpv4_mask) - { - *b_care = A_TRUE; - } - - sw->dhcpv4_val &= sw->dhcpv4_mask; - FIELD_SET(IP4_RUL_V3, IP4DHCPV, sw->dhcpv4_val); - FIELD_SET_MASK(IP4_RUL_M3, IP4DHCPM, sw->dhcpv4_mask); - } - - if (FAL_FIELD_FLG_TST(sw->field_flg, FAL_ACL_FIELD_INVERSE_ALL)) - { - FIELD_SET(MAC_RUL_V4, RULE_INV, 1); - } - - return SW_OK; -} - -static sw_error_t -_isis_acl_rule_ip6r1_parse(fal_acl_rule_t * sw, - hw_filter_t * hw, a_bool_t * b_care) -{ - a_uint32_t i; - - *b_care = A_FALSE; - aos_mem_zero(&(hw->vlu[0]), sizeof (hw->vlu)); - aos_mem_zero(&(hw->msk[0]), sizeof (hw->msk)); - - FIELD_SET_MASK(MAC_RUL_M4, RULE_TYP, ISIS_IP6R1_FILTER); - - if (FAL_FIELD_FLG_TST(sw->field_flg, FAL_ACL_FIELD_IP6_DIP)) - { - for (i = 0; i < 4; i++) - { - if (0x0 != sw->dest_ip6_mask.ul[i]) - { - *b_care = A_TRUE; - } - - sw->dest_ip6_val.ul[3 - i] &= sw->dest_ip6_mask.ul[3 - i]; - hw->vlu[i] = sw->dest_ip6_val.ul[3 - i]; - hw->msk[i] = sw->dest_ip6_mask.ul[3 - i]; - } - } - - if (FAL_FIELD_FLG_TST(sw->field_flg, FAL_ACL_FIELD_INVERSE_ALL)) - { - FIELD_SET(MAC_RUL_V4, RULE_INV, 1); - } - - return SW_OK; -} - -static sw_error_t -_isis_acl_rule_ip6r2_parse(fal_acl_rule_t * sw, - hw_filter_t * hw, a_bool_t * b_care) -{ - a_uint32_t i; - - *b_care = A_FALSE; - aos_mem_zero(&(hw->vlu[0]), sizeof (hw->vlu)); - aos_mem_zero(&(hw->msk[0]), sizeof (hw->msk)); - - FIELD_SET_MASK(MAC_RUL_M4, RULE_TYP, ISIS_IP6R2_FILTER); - - if (FAL_FIELD_FLG_TST(sw->field_flg, FAL_ACL_FIELD_IP6_SIP)) - { - for (i = 0; i < 4; i++) - { - if (0x0 != sw->src_ip6_mask.ul[i]) - { - *b_care = A_TRUE; - } - - sw->src_ip6_val.ul[3 - i] &= sw->src_ip6_mask.ul[3 - i]; - hw->vlu[i] = sw->src_ip6_val.ul[3 - i]; - hw->msk[i] = sw->src_ip6_mask.ul[3 - i]; - } - } - - if (FAL_FIELD_FLG_TST(sw->field_flg, FAL_ACL_FIELD_INVERSE_ALL)) - { - FIELD_SET(MAC_RUL_V4, RULE_INV, 1); - } - - return SW_OK; -} - -static sw_error_t -_isis_acl_rule_ip6r3_parse(fal_acl_rule_t * sw, - hw_filter_t * hw, a_bool_t * b_care) -{ - *b_care = A_FALSE; - aos_mem_zero(&(hw->vlu[0]), sizeof (hw->vlu)); - aos_mem_zero(&(hw->msk[0]), sizeof (hw->msk)); - - FIELD_SET_MASK(MAC_RUL_M4, RULE_TYP, ISIS_IP6R3_FILTER); - - if (FAL_FIELD_FLG_TST(sw->field_flg, FAL_ACL_FIELD_IP6_LABEL)) - { - if (0x0 != sw->ip6_lable_mask) - { - *b_care = A_TRUE; - } - - sw->ip6_lable_val &= sw->ip6_lable_mask; - FIELD_SET(IP6_RUL3_V1, IP6LABEL1V, sw->ip6_lable_val); - FIELD_SET_MASK(IP6_RUL3_M1, IP6LABEL1M, sw->ip6_lable_mask); - - FIELD_SET(IP6_RUL3_V2, IP6LABEL2V, (sw->ip6_lable_val >> 16)); - FIELD_SET_MASK(IP6_RUL3_M2, IP6LABEL2M, (sw->ip6_lable_mask >> 16)); - } - - if (FAL_FIELD_FLG_TST(sw->field_flg, FAL_ACL_FIELD_IP_PROTO)) - { - if (0x0 != sw->ip_proto_mask) - { - *b_care = A_TRUE; - } - - sw->ip_proto_val &= sw->ip_proto_mask; - FIELD_SET(IP6_RUL3_V0, IP6PROTV, sw->ip_proto_val); - FIELD_SET_MASK(IP6_RUL3_M0, IP6PROTM, sw->ip_proto_mask); - } - - if (FAL_FIELD_FLG_TST(sw->field_flg, FAL_ACL_FIELD_IP_DSCP)) - { - if (0x0 != sw->ip_dscp_mask) - { - *b_care = A_TRUE; - } - - sw->ip_dscp_val &= sw->ip_dscp_mask; - FIELD_SET(IP6_RUL3_V0, IP6DSCPV, sw->ip_dscp_val); - FIELD_SET_MASK(IP6_RUL3_M0, IP6DSCPM, sw->ip_dscp_mask); - } - - if ((FAL_FIELD_FLG_TST(sw->field_flg, FAL_ACL_FIELD_L4_SPORT)) - && ((FAL_FIELD_FLG_TST(sw->field_flg, FAL_ACL_FIELD_ICMP_TYPE)) - || (FAL_FIELD_FLG_TST(sw->field_flg, FAL_ACL_FIELD_ICMP_CODE)))) - { - return SW_BAD_PARAM; - } - - FIELD_SET_MASK(IP6_RUL3_M3, IP6SPORTM_EN, 1); - if (FAL_FIELD_FLG_TST(sw->field_flg, FAL_ACL_FIELD_L4_SPORT)) - { - if ((FAL_ACL_FIELD_MASK != sw->src_l4port_op) - && (FAL_ACL_FIELD_RANGE != sw->src_l4port_op) - && (FAL_ACL_FIELD_LE != sw->src_l4port_op) - && (FAL_ACL_FIELD_GE != sw->src_l4port_op)) - { - return SW_NOT_SUPPORTED; - } - - if (A_FALSE == - _isis_acl_field_care(sw->src_l4port_op, sw->src_l4port_val, - sw->src_l4port_mask, 0xffff)) - { - if (FAL_ACL_FIELD_MASK == sw->src_l4port_op) - { - sw->src_l4port_op = FAL_ACL_FIELD_RANGE; - sw->src_l4port_val = 0; - sw->src_l4port_mask = 0xffff; - } - } - *b_care = A_TRUE; - - FIELD_SET_MASK(IP6_RUL3_M3, IP6SPORTM_EN, 0); - if (FAL_ACL_FIELD_MASK == sw->src_l4port_op) - { - sw->src_l4port_val &= sw->src_l4port_mask; - FIELD_SET(IP6_RUL3_V3, IP6SPORTV, sw->src_l4port_val); - FIELD_SET_MASK(IP6_RUL3_M3, IP6SPORTM, sw->src_l4port_mask); - FIELD_SET_MASK(IP6_RUL3_M3, IP6SPORTM_EN, 1); - - } - else if (FAL_ACL_FIELD_RANGE == sw->src_l4port_op) - { - FIELD_SET(IP6_RUL3_V3, IP6SPORTV, sw->src_l4port_val); - FIELD_SET_MASK(IP6_RUL3_M3, IP6SPORTM, sw->src_l4port_mask); - - } - else if (FAL_ACL_FIELD_LE == sw->src_l4port_op) - { - FIELD_SET(IP6_RUL3_V3, IP6SPORTV, 0); - FIELD_SET_MASK(IP6_RUL3_M3, IP6SPORTM, sw->src_l4port_val); - - } - else - { - FIELD_SET(IP6_RUL3_V3, IP6SPORTV, sw->src_l4port_val); - FIELD_SET_MASK(IP6_RUL3_M3, IP6SPORTM, 0xffff); - } - } - - FIELD_SET_MASK(IP6_RUL3_M3, IP6DPORTM_EN, 1); - if (FAL_FIELD_FLG_TST(sw->field_flg, FAL_ACL_FIELD_L4_DPORT)) - { - if ((FAL_ACL_FIELD_MASK != sw->dest_l4port_op) - && (FAL_ACL_FIELD_RANGE != sw->dest_l4port_op) - && (FAL_ACL_FIELD_LE != sw->dest_l4port_op) - && (FAL_ACL_FIELD_GE != sw->dest_l4port_op)) - { - return SW_NOT_SUPPORTED; - } - - if (A_FALSE == - _isis_acl_field_care(sw->dest_l4port_op, sw->dest_l4port_val, - sw->dest_l4port_mask, 0xffff)) - { - if (FAL_ACL_FIELD_MASK == sw->dest_l4port_op) - { - sw->dest_l4port_op = FAL_ACL_FIELD_RANGE; - sw->dest_l4port_val = 0; - sw->dest_l4port_mask = 0xffff; - } - } - *b_care = A_TRUE; - - FIELD_SET_MASK(IP6_RUL3_M3, IP6DPORTM_EN, 0); - if (FAL_ACL_FIELD_MASK == sw->dest_l4port_op) - { - sw->dest_l4port_val &= sw->dest_l4port_mask; - FIELD_SET(IP6_RUL3_V2, IP6DPORTV, sw->dest_l4port_val); - FIELD_SET_MASK(IP6_RUL3_M2, IP6DPORTM, sw->dest_l4port_mask); - FIELD_SET_MASK(IP6_RUL3_M3, IP6DPORTM_EN, 1); - } - else if (FAL_ACL_FIELD_RANGE == sw->dest_l4port_op) - { - FIELD_SET(IP6_RUL3_V2, IP6DPORTV, sw->dest_l4port_val); - FIELD_SET_MASK(IP6_RUL3_M2, IP6DPORTM, sw->dest_l4port_mask); - } - else if (FAL_ACL_FIELD_LE == sw->dest_l4port_op) - { - FIELD_SET(IP6_RUL3_V2, IP6DPORTV, 0); - FIELD_SET_MASK(IP6_RUL3_M2, IP6DPORTM, sw->dest_l4port_val); - } - else - { - FIELD_SET(IP6_RUL3_V2, IP6DPORTV, sw->dest_l4port_val); - FIELD_SET_MASK(IP6_RUL3_M2, IP6DPORTM, 0xffff); - } - } - - if (FAL_FIELD_FLG_TST(sw->field_flg, FAL_ACL_FIELD_ICMP_TYPE)) - { - if (0x0 != sw->icmp_type_mask) - { - *b_care = A_TRUE; - } - FIELD_SET(IP6_RUL3_V3, ICMP6_EN, 1); - - sw->icmp_type_val &= sw->icmp_type_mask; - FIELD_SET(IP6_RUL3_V3, IP6ICMPTYPV, sw->icmp_type_val); - FIELD_SET_MASK(IP6_RUL3_M3, IP6ICMPTYPM, sw->icmp_type_mask); - } - - if (FAL_FIELD_FLG_TST(sw->field_flg, FAL_ACL_FIELD_ICMP_CODE)) - { - if (0x0 != sw->icmp_code_mask) - { - *b_care = A_TRUE; - } - FIELD_SET(IP6_RUL3_V3, ICMP6_EN, 1); - - sw->icmp_code_val &= sw->icmp_code_mask; - FIELD_SET(IP6_RUL3_V3, IP6ICMPCODEV, sw->icmp_code_val); - FIELD_SET_MASK(IP6_RUL3_M3, IP6ICMPCODEM, sw->icmp_code_mask); - } - - if (FAL_FIELD_FLG_TST(sw->field_flg, FAL_ACL_FIELD_TCP_FLAG)) - { - if (0x0 != sw->tcp_flag_mask) - { - *b_care = A_TRUE; - } - - sw->tcp_flag_val &= sw->tcp_flag_mask; - FIELD_SET(IP6_RUL3_V3, IP6TCPFLAGV, sw->tcp_flag_val); - FIELD_SET_MASK(IP6_RUL3_M3, IP6TCPFLAGM, sw->tcp_flag_mask); - } - - if (FAL_FIELD_FLG_TST(sw->field_flg, FAL_ACL_FIELD_DHCPV6)) - { - if (0x0 != sw->dhcpv6_mask) - { - *b_care = A_TRUE; - } - - sw->dhcpv6_val &= sw->dhcpv6_mask; - FIELD_SET(IP6_RUL3_V3, IP6DHCPV, sw->dhcpv6_val); - FIELD_SET_MASK(IP6_RUL3_M3, IP6DHCPM, sw->dhcpv6_mask); - } - - if (FAL_FIELD_FLG_TST(sw->field_flg, FAL_ACL_FIELD_INVERSE_ALL)) - { - FIELD_SET(MAC_RUL_V4, RULE_INV, 1); - } - - return SW_OK; -} - -static sw_error_t -_isis_acl_rule_udf_parse(fal_acl_rule_t * sw, - hw_filter_t * hw, a_bool_t * b_care) -{ - a_uint32_t i; - - *b_care = A_FALSE; - aos_mem_zero(&(hw->vlu[0]), sizeof (hw->vlu)); - aos_mem_zero(&(hw->msk[0]), sizeof (hw->msk)); - - FIELD_SET_MASK(MAC_RUL_M4, RULE_TYP, ISIS_UDF_FILTER); - - if (!FAL_FIELD_FLG_TST(sw->field_flg, FAL_ACL_FIELD_UDF)) - { - if (FAL_ACL_RULE_UDF == sw->rule_type) - { - if (FAL_FIELD_FLG_TST(sw->field_flg, FAL_ACL_FIELD_INVERSE_ALL)) - { - FIELD_SET(MAC_RUL_V4, RULE_INV, 1); - } - *b_care = A_TRUE; - } - return SW_OK; - } - - if (ISIS_MAX_UDF_LENGTH < sw->udf_len) - { - return SW_NOT_SUPPORTED; - } - - *b_care = A_TRUE; - for (i = 0; i < sw->udf_len; i++) - { - hw->vlu[3 - i / 4] |= - ((sw->udf_mask[i] & sw->udf_val[i]) << (24 - 8 * (i % 4))); - hw->msk[3 - i / 4] |= ((sw->udf_mask[i]) << (24 - 8 * i)); - } - - if (FAL_FIELD_FLG_TST(sw->field_flg, FAL_ACL_FIELD_INVERSE_ALL)) - { - FIELD_SET(MAC_RUL_V4, RULE_INV, 1); - } - - return SW_OK; -} - -static sw_error_t -_isis_acl_action_parse(a_uint32_t dev_id, const fal_acl_rule_t * sw, - hw_filter_t * hw) -{ - fal_pbmp_t des_pts; - - aos_mem_zero(&(hw->act[0]), sizeof (hw->act)); - - if (FAL_ACTION_FLG_TST(sw->action_flg, FAL_ACL_ACTION_MATCH_TRIGGER_INTR)) - { - FIELD_SET_ACTION(ACL_RSLT2, TRIGGER_INTR, 1); - } - - /* FAL_ACL_ACTION_PERMIT need't process */ - - if ((FAL_ACTION_FLG_TST(sw->action_flg, FAL_ACL_ACTION_RDTCPU)) - && (FAL_ACTION_FLG_TST(sw->action_flg, FAL_ACL_ACTION_CPYCPU))) - { - return SW_BAD_PARAM; - } - - if (FAL_ACTION_FLG_TST(sw->action_flg, FAL_ACL_ACTION_RDTCPU)) - { - FIELD_SET_ACTION(ACL_RSLT2, FWD_CMD, 0x3); - } - - if (FAL_ACTION_FLG_TST(sw->action_flg, FAL_ACL_ACTION_CPYCPU)) - { - FIELD_SET_ACTION(ACL_RSLT2, FWD_CMD, 0x1); - } - - if (FAL_ACTION_FLG_TST(sw->action_flg, FAL_ACL_ACTION_DENY)) - { - FIELD_SET_ACTION(ACL_RSLT2, FWD_CMD, 0x7); - } - - if (FAL_ACTION_FLG_TST(sw->action_flg, FAL_ACL_ACTION_MIRROR)) - { - FIELD_SET_ACTION(ACL_RSLT2, MIRR_EN, 1); - } - - if (FAL_ACTION_FLG_TST(sw->action_flg, FAL_ACL_ACTION_REDPT)) - { - FIELD_SET_ACTION(ACL_RSLT2, DES_PORT_EN, 1); - - des_pts = (sw->ports >> 3) & 0xf; - FIELD_SET_ACTION(ACL_RSLT2, DES_PORT1, des_pts); - - des_pts = sw->ports & 0x7; - FIELD_SET_ACTION(ACL_RSLT1, DES_PORT0, des_pts); - } - - if (FAL_ACTION_FLG_TST(sw->action_flg, FAL_ACL_ACTION_REMARK_UP)) - { - return SW_NOT_SUPPORTED; - } - - if (FAL_ACTION_FLG_TST(sw->action_flg, FAL_ACL_ACTION_REMARK_QUEUE)) - { - FIELD_SET_ACTION(ACL_RSLT1, PRI_QU_EN, 1); - FIELD_SET_ACTION(ACL_RSLT1, PRI_QU, sw->queue); - } - - if ((FAL_ACTION_FLG_TST(sw->action_flg, FAL_ACL_ACTION_MODIFY_VLAN)) - || (FAL_ACTION_FLG_TST(sw->action_flg, FAL_ACL_ACTION_NEST_VLAN))) - { - return SW_NOT_SUPPORTED; - } - - if (FAL_ACTION_FLG_TST(sw->action_flg, FAL_ACL_ACTION_REMARK_DSCP)) - { - FIELD_SET_ACTION(ACL_RSLT1, DSCPV, sw->dscp); - FIELD_SET_ACTION(ACL_RSLT1, DSCP_REMAP, 1); - } - - FIELD_SET_ACTION(ACL_RSLT0, STAGVID, sw->stag_vid); - if (FAL_ACTION_FLG_TST(sw->action_flg, FAL_ACL_ACTION_REMARK_STAG_VID)) - { - FIELD_SET_ACTION(ACL_RSLT1, TRANS_SVID_CHG, 1); - } - - if (FAL_ACTION_FLG_TST(sw->action_flg, FAL_ACL_ACTION_REMARK_STAG_PRI)) - { - FIELD_SET_ACTION(ACL_RSLT0, STAGPRI, sw->stag_pri); - FIELD_SET_ACTION(ACL_RSLT1, STAG_PRI_REMAP, 1); - } - - if (FAL_ACTION_FLG_TST(sw->action_flg, FAL_ACL_ACTION_REMARK_STAG_DEI)) - { - FIELD_SET_ACTION(ACL_RSLT0, STAGDEI, sw->stag_dei); - FIELD_SET_ACTION(ACL_RSLT1, STAG_DEI_CHG, 1); - } - - FIELD_SET_ACTION(ACL_RSLT0, CTAGVID, sw->ctag_vid); - if (FAL_ACTION_FLG_TST(sw->action_flg, FAL_ACL_ACTION_REMARK_CTAG_VID)) - { - FIELD_SET_ACTION(ACL_RSLT1, TRANS_CVID_CHG, 1); - } - - if (FAL_ACTION_FLG_TST(sw->action_flg, FAL_ACL_ACTION_REMARK_CTAG_PRI)) - { - FIELD_SET_ACTION(ACL_RSLT0, CTAGPRI, sw->ctag_pri); - FIELD_SET_ACTION(ACL_RSLT1, CTAG_PRI_REMAP, 1); - } - - if (FAL_ACTION_FLG_TST(sw->action_flg, FAL_ACL_ACTION_REMARK_CTAG_CFI)) - { - FIELD_SET_ACTION(ACL_RSLT0, CTAGCFI, sw->ctag_cfi); - FIELD_SET_ACTION(ACL_RSLT1, CTAG_CFI_CHG, 1); - } - - if (FAL_ACTION_FLG_TST(sw->action_flg, FAL_ACL_ACTION_REMARK_LOOKUP_VID)) - { - FIELD_SET_ACTION(ACL_RSLT1, LOOK_VID_CHG, 1); - } - - if (FAL_ACTION_FLG_TST(sw->action_flg, FAL_ACL_ACTION_POLICER_EN)) - { - FIELD_SET_ACTION(ACL_RSLT2, POLICER_PTR, sw->policer_ptr); - FIELD_SET_ACTION(ACL_RSLT2, POLICER_EN, 1); - } - - if ((FAL_ACTION_FLG_TST(sw->action_flg, FAL_ACL_ACTION_ARP_EN)) - && (FAL_ACTION_FLG_TST(sw->action_flg, FAL_ACL_ACTION_WCMP_EN))) - { - return SW_NOT_SUPPORTED; - } - - if (FAL_ACTION_FLG_TST(sw->action_flg, FAL_ACL_ACTION_ARP_EN)) - { - FIELD_SET_ACTION(ACL_RSLT1, ARP_PTR, sw->arp_ptr); - FIELD_SET_ACTION(ACL_RSLT1, ARP_PTR_EN, 1); - } - - if (FAL_ACTION_FLG_TST(sw->action_flg, FAL_ACL_ACTION_WCMP_EN)) - { - FIELD_SET_ACTION(ACL_RSLT1, ARP_PTR, sw->wcmp_ptr); - FIELD_SET_ACTION(ACL_RSLT1, WCMP_EN, 1); - FIELD_SET_ACTION(ACL_RSLT1, ARP_PTR_EN, 1); - } - - FIELD_SET_ACTION(ACL_RSLT1, FORCE_L3_MODE, 0x0); - if (FAL_ACTION_FLG_TST(sw->action_flg, FAL_ACL_ACTION_POLICY_FORWARD_EN)) - { - if (FAL_ACL_POLICY_ROUTE == sw->policy_fwd) - { - return SW_NOT_SUPPORTED; - } - else if (FAL_ACL_POLICY_SNAT == sw->policy_fwd) - { - FIELD_SET_ACTION(ACL_RSLT1, FORCE_L3_MODE, 0x1); - } - else if (FAL_ACL_POLICY_DNAT == sw->policy_fwd) - { - FIELD_SET_ACTION(ACL_RSLT1, FORCE_L3_MODE, 0x2); - } - else if (FAL_ACL_POLICY_RESERVE == sw->policy_fwd) - { - FIELD_SET_ACTION(ACL_RSLT1, FORCE_L3_MODE, 0x3); - } - else - { - return SW_BAD_PARAM; - } - } - - if (FAL_ACTION_FLG_TST(sw->action_flg, FAL_ACL_ACTION_BYPASS_EGRESS_TRANS)) - { - FIELD_SET_ACTION(ACL_RSLT2, EG_BYPASS, 1); - } - - if (FAL_ACTION_FLG_TST(sw->action_flg, FAL_ACL_ACTION_MATCH_TRIGGER_INTR)) - { - FIELD_SET_ACTION(ACL_RSLT2, TRIGGER_INTR, 1); - } - - return SW_OK; -} - -static sw_error_t -_isis_acl_rule_bmac_reparse(fal_acl_rule_t * sw, const hw_filter_t * hw) -{ - a_uint32_t mask_en; - - /* destnation mac address */ - FIELD_GET(MAC_RUL_V0, DAV_BYTE2, sw->dest_mac_val.uc[2]); - FIELD_GET(MAC_RUL_V0, DAV_BYTE3, sw->dest_mac_val.uc[3]); - FIELD_GET(MAC_RUL_V0, DAV_BYTE4, sw->dest_mac_val.uc[4]); - FIELD_GET(MAC_RUL_V0, DAV_BYTE5, sw->dest_mac_val.uc[5]); - FIELD_GET(MAC_RUL_V1, DAV_BYTE0, sw->dest_mac_val.uc[0]); - FIELD_GET(MAC_RUL_V1, DAV_BYTE1, sw->dest_mac_val.uc[1]); - - FIELD_GET_MASK(MAC_RUL_M0, DAM_BYTE2, sw->dest_mac_mask.uc[2]); - FIELD_GET_MASK(MAC_RUL_M0, DAM_BYTE3, sw->dest_mac_mask.uc[3]); - FIELD_GET_MASK(MAC_RUL_M0, DAM_BYTE4, sw->dest_mac_mask.uc[4]); - FIELD_GET_MASK(MAC_RUL_M0, DAM_BYTE5, sw->dest_mac_mask.uc[5]); - FIELD_GET_MASK(MAC_RUL_M1, DAM_BYTE0, sw->dest_mac_mask.uc[0]); - FIELD_GET_MASK(MAC_RUL_M1, DAM_BYTE1, sw->dest_mac_mask.uc[1]); - if (A_FALSE == _isis_acl_zero_addr(sw->dest_mac_mask)) - { - FAL_FIELD_FLG_SET(sw->field_flg, FAL_ACL_FIELD_MAC_DA); - } - - /* source mac address */ - FIELD_GET(MAC_RUL_V2, SAV_BYTE0, sw->src_mac_val.uc[0]); - FIELD_GET(MAC_RUL_V2, SAV_BYTE1, sw->src_mac_val.uc[1]); - FIELD_GET(MAC_RUL_V2, SAV_BYTE2, sw->src_mac_val.uc[2]); - FIELD_GET(MAC_RUL_V2, SAV_BYTE3, sw->src_mac_val.uc[3]); - FIELD_GET(MAC_RUL_V1, SAV_BYTE4, sw->src_mac_val.uc[4]); - FIELD_GET(MAC_RUL_V1, SAV_BYTE5, sw->src_mac_val.uc[5]); - - FIELD_GET_MASK(MAC_RUL_M2, SAM_BYTE0, sw->src_mac_mask.uc[0]); - FIELD_GET_MASK(MAC_RUL_M2, SAM_BYTE1, sw->src_mac_mask.uc[1]); - FIELD_GET_MASK(MAC_RUL_M2, SAM_BYTE2, sw->src_mac_mask.uc[2]); - FIELD_GET_MASK(MAC_RUL_M2, SAM_BYTE3, sw->src_mac_mask.uc[3]); - FIELD_GET_MASK(MAC_RUL_M1, SAM_BYTE4, sw->src_mac_mask.uc[4]); - FIELD_GET_MASK(MAC_RUL_M1, SAM_BYTE5, sw->src_mac_mask.uc[5]); - if (A_FALSE == _isis_acl_zero_addr(sw->src_mac_mask)) - { - FAL_FIELD_FLG_SET(sw->field_flg, FAL_ACL_FIELD_MAC_SA); - } - - /* ethernet type */ - FIELD_GET(MAC_RUL_V3, ETHTYPV, sw->ethtype_val); - FIELD_GET_MASK(MAC_RUL_M3, ETHTYPM, sw->ethtype_mask); - if (0x0 != sw->ethtype_mask) - { - FAL_FIELD_FLG_SET(sw->field_flg, FAL_ACL_FIELD_MAC_ETHTYPE); - } - - /* packet tagged */ - FIELD_GET_MASK(MAC_RUL_M4, TAGGEDV, sw->tagged_val); - FIELD_GET_MASK(MAC_RUL_M4, TAGGEDM, sw->tagged_mask); - if (0x0 != sw->tagged_mask) - { - FAL_FIELD_FLG_SET(sw->field_flg, FAL_ACL_FIELD_MAC_TAGGED); - } - - /* vlan priority */ - FIELD_GET(MAC_RUL_V3, VLANPRIV, sw->up_val); - FIELD_GET_MASK(MAC_RUL_M3, VLANPRIM, sw->up_mask); - if (0x0 != sw->up_mask) - { - FAL_FIELD_FLG_SET(sw->field_flg, FAL_ACL_FIELD_MAC_UP); - } - - /* vlanid */ - FIELD_GET(MAC_RUL_V3, VLANIDV, sw->vid_val); - FIELD_GET_MASK(MAC_RUL_M3, VLANIDM, sw->vid_mask); - FIELD_GET_MASK(MAC_RUL_M4, VIDMSK, mask_en); - if (mask_en) - { - sw->vid_op = FAL_ACL_FIELD_MASK; - } - else - { - sw->vid_op = FAL_ACL_FIELD_RANGE; - } - - if (A_TRUE == - _isis_acl_field_care(sw->vid_op, (a_uint32_t) sw->vid_val, - (a_uint32_t) sw->vid_mask, 0xfff)) - { - FAL_FIELD_FLG_SET(sw->field_flg, FAL_ACL_FIELD_MAC_VID); - } - - /* vlan cfi */ - FIELD_GET(MAC_RUL_V3, VLANCFIV, sw->cfi_val); - FIELD_GET_MASK(MAC_RUL_M3, VLANCFIM, sw->cfi_mask); - if (0x0 != sw->cfi_mask) - { - FAL_FIELD_FLG_SET(sw->field_flg, FAL_ACL_FIELD_MAC_CFI); - } - - FIELD_GET(MAC_RUL_V4, RULE_INV, mask_en); - if (mask_en) - { - FAL_FIELD_FLG_SET(sw->field_flg, FAL_ACL_FIELD_INVERSE_ALL); - } - - return SW_OK; -} - -static sw_error_t -_isis_acl_rule_ehmac_reparse(fal_acl_rule_t * sw, const hw_filter_t * hw) -{ - a_uint32_t i, mask_en, data; - - FIELD_GET(EHMAC_RUL_V3, DA_EN, data); - if (data) - { - for (i = 2; i < 6; i++) - { - sw->dest_mac_val.uc[i] = ((hw->vlu[0]) >> ((5 - i) << 3)) & 0xff; - sw->dest_mac_mask.uc[i] = ((hw->msk[0]) >> ((5 - i) << 3)) & 0xff; - } - - for (i = 0; i < 2; i++) - { - sw->dest_mac_val.uc[i] = ((hw->vlu[1]) >> ((1 - i) << 3)) & 0xff; - sw->dest_mac_mask.uc[i] = ((hw->msk[1]) >> ((1 - i) << 3)) & 0xff; - } - - if (A_FALSE == _isis_acl_zero_addr(sw->dest_mac_mask)) - { - FAL_FIELD_FLG_SET(sw->field_flg, FAL_ACL_FIELD_MAC_DA); - } - - FIELD_GET(EHMAC_RUL_V2, SAV_BYTE3, sw->src_mac_val.uc[3]); - FIELD_GET(EHMAC_RUL_V1, SAV_BYTE4, sw->src_mac_val.uc[4]); - FIELD_GET(EHMAC_RUL_V1, SAV_BYTE5, sw->src_mac_val.uc[5]); - - FIELD_GET_MASK(EHMAC_RUL_M2, SAM_BYTE3, sw->src_mac_mask.uc[3]); - FIELD_GET_MASK(EHMAC_RUL_M1, SAM_BYTE4, sw->src_mac_mask.uc[4]); - FIELD_GET_MASK(EHMAC_RUL_M1, SAM_BYTE5, sw->src_mac_mask.uc[5]); - - if (A_FALSE == _isis_acl_zero_addr(sw->src_mac_mask)) - { - FAL_FIELD_FLG_SET(sw->field_flg, FAL_ACL_FIELD_MAC_SA); - } - } - else - { - for (i = 2; i < 6; i++) - { - sw->src_mac_val.uc[i] = ((hw->vlu[0]) >> ((5 - i) << 3)) & 0xff; - sw->src_mac_mask.uc[i] = ((hw->msk[0]) >> ((5 - i) << 3)) & 0xff; - } - - for (i = 0; i < 2; i++) - { - sw->src_mac_val.uc[i] = ((hw->vlu[1]) >> ((1 - i) << 3)) & 0xff; - sw->src_mac_mask.uc[i] = ((hw->msk[1]) >> ((1 - i) << 3)) & 0xff; - } - - if (A_FALSE == _isis_acl_zero_addr(sw->src_mac_mask)) - { - FAL_FIELD_FLG_SET(sw->field_flg, FAL_ACL_FIELD_MAC_SA); - } - - FIELD_GET(EHMAC_RUL_V2, SAV_BYTE3, sw->dest_mac_val.uc[3]); - FIELD_GET(EHMAC_RUL_V1, SAV_BYTE4, sw->dest_mac_val.uc[4]); - FIELD_GET(EHMAC_RUL_V1, SAV_BYTE5, sw->dest_mac_val.uc[5]); - - FIELD_GET_MASK(EHMAC_RUL_M2, SAM_BYTE3, sw->dest_mac_mask.uc[3]); - FIELD_GET_MASK(EHMAC_RUL_M1, SAM_BYTE4, sw->dest_mac_mask.uc[4]); - FIELD_GET_MASK(EHMAC_RUL_M1, SAM_BYTE5, sw->dest_mac_mask.uc[5]); - if (A_FALSE == _isis_acl_zero_addr(sw->dest_mac_mask)) - { - FAL_FIELD_FLG_SET(sw->field_flg, FAL_ACL_FIELD_MAC_DA); - } - } - - /* ethernet type */ - FIELD_GET(EHMAC_RUL_V3, ETHTYPV, sw->ethtype_val); - FIELD_GET_MASK(EHMAC_RUL_M3, ETHTYPM, sw->ethtype_mask); - if (0x0 != sw->ethtype_mask) - { - FAL_FIELD_FLG_SET(sw->field_flg, FAL_ACL_FIELD_MAC_ETHTYPE); - } - - /* packet stagged */ - FIELD_GET(EHMAC_RUL_V3, STAGGEDV, sw->stagged_val); - FIELD_GET(EHMAC_RUL_V3, STAGGEDM, sw->stagged_mask); - if (0x0 != sw->stagged_mask) - { - FAL_FIELD_FLG_SET(sw->field_flg, FAL_ACL_FIELD_MAC_STAGGED); - } - - /* stag vid */ - FIELD_GET(EHMAC_RUL_V2, STAG_VIDV, sw->stag_vid_val); - FIELD_GET_MASK(EHMAC_RUL_M2, STAG_VIDM, sw->stag_vid_mask); - FIELD_GET(EHMAC_RUL_V3, SVIDMSK, mask_en); - if (mask_en) - { - sw->stag_vid_op = FAL_ACL_FIELD_MASK; - } - else - { - sw->stag_vid_op = FAL_ACL_FIELD_RANGE; - } - - if (A_TRUE == - _isis_acl_field_care(sw->stag_vid_op, (a_uint32_t) sw->stag_vid_val, - (a_uint32_t) sw->stag_vid_mask, 0xfff)) - { - FAL_FIELD_FLG_SET(sw->field_flg, FAL_ACL_FIELD_MAC_STAG_VID); - } - - /* stag priority */ - FIELD_GET(EHMAC_RUL_V2, STAG_PRIV, sw->stag_pri_val); - FIELD_GET_MASK(EHMAC_RUL_M2, STAG_PRIM, sw->stag_pri_mask); - if (0x0 != sw->stag_pri_mask) - { - FAL_FIELD_FLG_SET(sw->field_flg, FAL_ACL_FIELD_MAC_STAG_PRI); - } - - /* stag dei */ - FIELD_GET(EHMAC_RUL_V2, STAG_DEIV, sw->stag_dei_val); - FIELD_GET_MASK(EHMAC_RUL_M2, STAG_DEIM, sw->stag_dei_mask); - if (0x0 != sw->stag_dei_mask) - { - FAL_FIELD_FLG_SET(sw->field_flg, FAL_ACL_FIELD_MAC_STAG_DEI); - } - - /* packet ctagged */ - FIELD_GET_MASK(EHMAC_RUL_M4, CTAGGEDV, sw->ctagged_val); - FIELD_GET_MASK(EHMAC_RUL_M4, CTAGGEDM, sw->ctagged_mask); - if (0x0 != sw->ctagged_mask) - { - FAL_FIELD_FLG_SET(sw->field_flg, FAL_ACL_FIELD_MAC_CTAGGED); - } - - /* ctag vid */ - FIELD_GET(EHMAC_RUL_V2, CTAG_VIDLV, sw->ctag_vid_val); - FIELD_GET(EHMAC_RUL_V3, CTAG_VIDHV, data); - sw->ctag_vid_val |= (data << 8); - FIELD_GET_MASK(EHMAC_RUL_M2, CTAG_VIDLM, sw->ctag_vid_mask); - FIELD_GET_MASK(EHMAC_RUL_M3, CTAG_VIDHM, data); - sw->ctag_vid_mask |= (data << 8); - - FIELD_GET_MASK(EHMAC_RUL_M4, CVIDMSK, mask_en); - if (mask_en) - { - sw->ctag_vid_op = FAL_ACL_FIELD_MASK; - } - else - { - sw->ctag_vid_op = FAL_ACL_FIELD_RANGE; - } - - if (A_TRUE == - _isis_acl_field_care(sw->ctag_vid_op, (a_uint32_t) sw->ctag_vid_val, - (a_uint32_t) sw->ctag_vid_mask, 0xfff)) - { - FAL_FIELD_FLG_SET(sw->field_flg, FAL_ACL_FIELD_MAC_CTAG_VID); - } - - /* ctag priority */ - FIELD_GET(EHMAC_RUL_V3, CTAG_PRIV, sw->ctag_pri_val); - FIELD_GET_MASK(EHMAC_RUL_M3, CTAG_PRIM, sw->ctag_pri_mask); - if (0x0 != sw->ctag_pri_mask) - { - FAL_FIELD_FLG_SET(sw->field_flg, FAL_ACL_FIELD_MAC_CTAG_PRI); - } - - /* ctag dei */ - FIELD_GET(EHMAC_RUL_V3, CTAG_CFIV, sw->ctag_cfi_val); - FIELD_GET_MASK(EHMAC_RUL_M3, CTAG_CFIM, sw->ctag_cfi_mask); - if (0x0 != sw->ctag_cfi_mask) - { - FAL_FIELD_FLG_SET(sw->field_flg, FAL_ACL_FIELD_MAC_CTAG_CFI); - } - - FIELD_GET(MAC_RUL_V4, RULE_INV, mask_en); - if (mask_en) - { - FAL_FIELD_FLG_SET(sw->field_flg, FAL_ACL_FIELD_INVERSE_ALL); - } - - return SW_OK; -} - -static sw_error_t -_isis_acl_rule_ip4_reparse(fal_acl_rule_t * sw, const hw_filter_t * hw) -{ - a_uint32_t mask_en, icmp_en; - - sw->dest_ip4_val = hw->vlu[0]; - sw->dest_ip4_mask = hw->msk[0]; - if (0x0 != sw->dest_ip4_mask) - { - FAL_FIELD_FLG_SET(sw->field_flg, FAL_ACL_FIELD_IP4_DIP); - } - - sw->src_ip4_val = hw->vlu[1]; - sw->src_ip4_mask = hw->msk[1]; - if (0x0 != sw->src_ip4_mask) - { - FAL_FIELD_FLG_SET(sw->field_flg, FAL_ACL_FIELD_IP4_SIP); - } - - FIELD_GET(IP4_RUL_V2, IP4PROTV, sw->ip_proto_val); - FIELD_GET_MASK(IP4_RUL_M2, IP4PROTM, sw->ip_proto_mask); - if (0x0 != sw->ip_proto_mask) - { - FAL_FIELD_FLG_SET(sw->field_flg, FAL_ACL_FIELD_IP_PROTO); - } - - FIELD_GET(IP4_RUL_V2, IP4DSCPV, sw->ip_dscp_val); - FIELD_GET_MASK(IP4_RUL_M2, IP4DSCPM, sw->ip_dscp_mask); - if (0x0 != sw->ip_dscp_mask) - { - FAL_FIELD_FLG_SET(sw->field_flg, FAL_ACL_FIELD_IP_DSCP); - } - - FIELD_GET(IP4_RUL_V2, IP4DPORTV, sw->dest_l4port_val); - FIELD_GET_MASK(IP4_RUL_M2, IP4DPORTM, sw->dest_l4port_mask); - FIELD_GET_MASK(IP4_RUL_M3, IP4DPORTM_EN, mask_en); - if (mask_en) - { - sw->dest_l4port_op = FAL_ACL_FIELD_MASK; - } - else - { - sw->dest_l4port_op = FAL_ACL_FIELD_RANGE; - } - - if (A_TRUE == - _isis_acl_field_care(sw->dest_l4port_op, - (a_uint32_t) sw->dest_l4port_val, - (a_uint32_t) sw->dest_l4port_mask, 0xffff)) - { - FAL_FIELD_FLG_SET(sw->field_flg, FAL_ACL_FIELD_L4_DPORT); - } - else if (FAL_ACL_FIELD_RANGE == sw->dest_l4port_op) - { - FAL_FIELD_FLG_SET(sw->field_flg, FAL_ACL_FIELD_L4_DPORT); - } - - FIELD_GET(IP4_RUL_V3, ICMP_EN, icmp_en); - if (icmp_en) - { - FIELD_GET(IP4_RUL_V3, IP4ICMPTYPV, sw->icmp_type_val); - FIELD_GET_MASK(IP4_RUL_M3, IP4ICMPTYPM, sw->icmp_type_mask); - if (0x0 != sw->icmp_type_mask) - { - FAL_FIELD_FLG_SET(sw->field_flg, FAL_ACL_FIELD_ICMP_TYPE); - } - - FIELD_GET(IP4_RUL_V3, IP4ICMPCODEV, sw->icmp_code_val); - FIELD_GET_MASK(IP4_RUL_M3, IP4ICMPCODEM, sw->icmp_code_mask); - if (0x0 != sw->icmp_code_mask) - { - FAL_FIELD_FLG_SET(sw->field_flg, FAL_ACL_FIELD_ICMP_CODE); - } - } - else - { - FIELD_GET(IP4_RUL_V3, IP4SPORTV, sw->src_l4port_val); - FIELD_GET_MASK(IP4_RUL_M3, IP4SPORTM, sw->src_l4port_mask); - FIELD_GET_MASK(IP4_RUL_M3, IP4SPORTM_EN, mask_en); - if (mask_en) - { - sw->src_l4port_op = FAL_ACL_FIELD_MASK; - } - else - { - sw->src_l4port_op = FAL_ACL_FIELD_RANGE; - } - - if (A_TRUE == - _isis_acl_field_care(sw->src_l4port_op, - (a_uint32_t) sw->src_l4port_val, - (a_uint32_t) sw->src_l4port_mask, 0xffff)) - { - FAL_FIELD_FLG_SET(sw->field_flg, FAL_ACL_FIELD_L4_SPORT); - } - else if (FAL_ACL_FIELD_RANGE == sw->src_l4port_op) - { - FAL_FIELD_FLG_SET(sw->field_flg, FAL_ACL_FIELD_L4_SPORT); - } - } - - FIELD_GET(IP4_RUL_V3, IP4TCPFLAGV, sw->tcp_flag_val); - FIELD_GET_MASK(IP4_RUL_M3, IP4TCPFLAGM, sw->tcp_flag_mask); - if (0x0 != sw->tcp_flag_mask) - { - FAL_FIELD_FLG_SET(sw->field_flg, FAL_ACL_FIELD_TCP_FLAG); - } - - FIELD_GET(IP4_RUL_V3, IP4RIPV, sw->ripv1_val); - FIELD_GET_MASK(IP4_RUL_M3, IP4RIPM, sw->ripv1_mask); - if (0x0 != sw->ripv1_mask) - { - FAL_FIELD_FLG_SET(sw->field_flg, FAL_ACL_FIELD_RIPV1); - } - - FIELD_GET(IP4_RUL_V3, IP4DHCPV, sw->dhcpv4_val); - FIELD_GET_MASK(IP4_RUL_M3, IP4DHCPM, sw->dhcpv4_mask); - if (0x0 != sw->dhcpv4_mask) - { - FAL_FIELD_FLG_SET(sw->field_flg, FAL_ACL_FIELD_DHCPV4); - } - - FIELD_GET(MAC_RUL_V4, RULE_INV, mask_en); - if (mask_en) - { - FAL_FIELD_FLG_SET(sw->field_flg, FAL_ACL_FIELD_INVERSE_ALL); - } - - return SW_OK; -} - -static sw_error_t -_isis_acl_rule_ip6r1_reparse(fal_acl_rule_t * sw, const hw_filter_t * hw) -{ - a_uint32_t i; - - for (i = 0; i < 4; i++) - { - sw->dest_ip6_val.ul[i] = hw->vlu[3 - i]; - sw->dest_ip6_mask.ul[i] = hw->msk[3 - i]; - if (0x0 != sw->dest_ip6_mask.ul[i]) - { - FAL_FIELD_FLG_SET(sw->field_flg, FAL_ACL_FIELD_IP6_DIP); - } - } - - FIELD_GET(MAC_RUL_V4, RULE_INV, i); - if (i) - { - FAL_FIELD_FLG_SET(sw->field_flg, FAL_ACL_FIELD_INVERSE_ALL); - } - - return SW_OK; -} - -static sw_error_t -_isis_acl_rule_ip6r2_reparse(fal_acl_rule_t * sw, const hw_filter_t * hw) -{ - a_uint32_t i; - - for (i = 0; i < 4; i++) - { - sw->src_ip6_val.ul[i] = hw->vlu[3 - i]; - sw->src_ip6_mask.ul[i] = hw->msk[3 - i]; - if (0x0 != sw->src_ip6_mask.ul[i]) - { - FAL_FIELD_FLG_SET(sw->field_flg, FAL_ACL_FIELD_IP6_SIP); - } - } - - FIELD_GET(MAC_RUL_V4, RULE_INV, i); - if (i) - { - FAL_FIELD_FLG_SET(sw->field_flg, FAL_ACL_FIELD_INVERSE_ALL); - } - - return SW_OK; -} - -static sw_error_t -_isis_acl_rule_ip6r3_reparse(fal_acl_rule_t * sw, const hw_filter_t * hw) -{ - a_uint32_t mask_en, icmp6_en, tmp; - - FIELD_GET(IP6_RUL3_V0, IP6PROTV, sw->ip_proto_val); - FIELD_GET_MASK(IP6_RUL3_M0, IP6PROTM, sw->ip_proto_mask); - if (0x0 != sw->ip_proto_mask) - { - FAL_FIELD_FLG_SET(sw->field_flg, FAL_ACL_FIELD_IP_PROTO); - } - - FIELD_GET(IP6_RUL3_V0, IP6DSCPV, sw->ip_dscp_val); - FIELD_GET_MASK(IP6_RUL3_M0, IP6DSCPM, sw->ip_dscp_mask); - if (0x0 != sw->ip_dscp_mask) - { - FAL_FIELD_FLG_SET(sw->field_flg, FAL_ACL_FIELD_IP_DSCP); - } - - FIELD_GET(IP6_RUL3_V2, IP6DPORTV, sw->dest_l4port_val); - FIELD_GET_MASK(IP6_RUL3_M2, IP6DPORTM, sw->dest_l4port_mask); - FIELD_GET_MASK(IP6_RUL3_M3, IP6DPORTM_EN, mask_en); - if (mask_en) - { - sw->dest_l4port_op = FAL_ACL_FIELD_MASK; - } - else - { - sw->dest_l4port_op = FAL_ACL_FIELD_RANGE; - } - - if (A_TRUE == - _isis_acl_field_care(sw->dest_l4port_op, - (a_uint32_t) sw->dest_l4port_val, - (a_uint32_t) sw->dest_l4port_mask, 0xffff)) - { - FAL_FIELD_FLG_SET(sw->field_flg, FAL_ACL_FIELD_L4_DPORT); - } - else if (FAL_ACL_FIELD_RANGE == sw->dest_l4port_op) - { - FAL_FIELD_FLG_SET(sw->field_flg, FAL_ACL_FIELD_L4_DPORT); - } - - FIELD_GET(IP6_RUL3_V3, ICMP6_EN, icmp6_en); - if (icmp6_en) - { - FIELD_GET(IP6_RUL3_V3, IP6ICMPTYPV, sw->icmp_type_val); - FIELD_GET_MASK(IP6_RUL3_M3, IP6ICMPTYPM, sw->icmp_type_mask); - if (0x0 != sw->icmp_type_mask) - { - FAL_FIELD_FLG_SET(sw->field_flg, FAL_ACL_FIELD_ICMP_TYPE); - } - - FIELD_GET(IP6_RUL3_V3, IP6ICMPCODEV, sw->icmp_code_val); - FIELD_GET_MASK(IP6_RUL3_M3, IP6ICMPCODEM, sw->icmp_code_mask); - if (0x0 != sw->icmp_code_mask) - { - FAL_FIELD_FLG_SET(sw->field_flg, FAL_ACL_FIELD_ICMP_CODE); - } - } - else - { - FIELD_GET(IP6_RUL3_V3, IP6SPORTV, sw->src_l4port_val); - FIELD_GET_MASK(IP6_RUL3_M3, IP6SPORTM, sw->src_l4port_mask); - FIELD_GET_MASK(IP6_RUL3_M3, IP6SPORTM_EN, mask_en); - if (mask_en) - { - sw->src_l4port_op = FAL_ACL_FIELD_MASK; - } - else - { - sw->src_l4port_op = FAL_ACL_FIELD_RANGE; - } - - if (A_TRUE == - _isis_acl_field_care(sw->src_l4port_op, - (a_uint32_t) sw->src_l4port_val, - (a_uint32_t) sw->src_l4port_mask, 0xffff)) - { - FAL_FIELD_FLG_SET(sw->field_flg, FAL_ACL_FIELD_L4_SPORT); - } - else if (FAL_ACL_FIELD_RANGE == sw->src_l4port_op) - { - FAL_FIELD_FLG_SET(sw->field_flg, FAL_ACL_FIELD_L4_SPORT); - } - } - - FIELD_GET(IP6_RUL3_V1, IP6LABEL1V, sw->ip6_lable_val); - FIELD_GET_MASK(IP6_RUL3_M1, IP6LABEL1M, sw->ip6_lable_mask); - - FIELD_GET(IP6_RUL3_V2, IP6LABEL2V, tmp); - sw->ip6_lable_val |= (tmp << 16); - FIELD_GET_MASK(IP6_RUL3_M2, IP6LABEL2M, tmp); - sw->ip6_lable_mask |= (tmp << 16); - - if (0x0 != sw->ip6_lable_mask) - { - FAL_FIELD_FLG_SET(sw->field_flg, FAL_ACL_FIELD_IP6_LABEL); - } - - FIELD_GET(IP6_RUL3_V3, IP6TCPFLAGV, sw->tcp_flag_val); - FIELD_GET_MASK(IP6_RUL3_M3, IP6TCPFLAGM, sw->tcp_flag_mask); - if (0x0 != sw->tcp_flag_mask) - { - FAL_FIELD_FLG_SET(sw->field_flg, FAL_ACL_FIELD_TCP_FLAG); - } - - FIELD_GET(IP6_RUL3_V3, IP6DHCPV, sw->dhcpv6_val); - FIELD_GET_MASK(IP6_RUL3_M3, IP6DHCPM, sw->dhcpv6_mask); - if (0x0 != sw->dhcpv6_mask) - { - FAL_FIELD_FLG_SET(sw->field_flg, FAL_ACL_FIELD_DHCPV6); - } - - FIELD_GET(MAC_RUL_V4, RULE_INV, mask_en); - if (mask_en) - { - FAL_FIELD_FLG_SET(sw->field_flg, FAL_ACL_FIELD_INVERSE_ALL); - } - - return SW_OK; -} - -static sw_error_t -_isis_acl_rule_udf_reparse(fal_acl_rule_t * sw, const hw_filter_t * hw) -{ - a_uint32_t i; - - FAL_FIELD_FLG_SET(sw->field_flg, FAL_ACL_FIELD_UDF); - - /* for ISIS UDF type, length and offset no meanging in rules, just set default value */ - sw->udf_type = FAL_ACL_UDF_TYPE_L2; - sw->udf_len = 16; - sw->udf_offset = 0; - - for (i = 0; i < ISIS_MAX_UDF_LENGTH; i++) - { - sw->udf_val[i] = ((hw->vlu[3 - i / 4]) >> (24 - 8 * (i % 4))) & 0xff; - sw->udf_mask[i] = ((hw->msk[3 - i / 4]) >> (24 - 8 * (i % 4))) & 0xff; - } - - FIELD_GET(MAC_RUL_V4, RULE_INV, i); - if (i) - { - FAL_FIELD_FLG_SET(sw->field_flg, FAL_ACL_FIELD_INVERSE_ALL); - } - - return SW_OK; -} - -static sw_error_t -_isis_acl_rule_action_reparse(fal_acl_rule_t * sw, const hw_filter_t * hw) -{ - a_uint32_t data; - - sw->action_flg = 0; - - FIELD_GET_ACTION(ACL_RSLT2, DES_PORT_EN, data); - if (1 == data) - { - FAL_ACTION_FLG_SET(sw->action_flg, FAL_ACL_ACTION_REDPT); - FIELD_GET_ACTION(ACL_RSLT1, DES_PORT0, sw->ports); - FIELD_GET_ACTION(ACL_RSLT2, DES_PORT1, data); - sw->ports |= (data << 3); - } - - FIELD_GET_ACTION(ACL_RSLT2, FWD_CMD, data); - if (0x7 == data) - { - FAL_ACTION_FLG_SET(sw->action_flg, FAL_ACL_ACTION_DENY); - } - else if (0x3 == data) - { - FAL_ACTION_FLG_SET(sw->action_flg, FAL_ACL_ACTION_RDTCPU); - } - else if (0x1 == data) - { - FAL_ACTION_FLG_SET(sw->action_flg, FAL_ACL_ACTION_CPYCPU); - } - else - { - /* need't set permit action */ - } - - FIELD_GET_ACTION(ACL_RSLT2, MIRR_EN, data); - if (1 == data) - { - FAL_ACTION_FLG_SET(sw->action_flg, FAL_ACL_ACTION_MIRROR); - } - - FIELD_GET_ACTION(ACL_RSLT1, PRI_QU_EN, data); - if (1 == data) - { - FAL_ACTION_FLG_SET(sw->action_flg, FAL_ACL_ACTION_REMARK_QUEUE); - FIELD_GET_ACTION(ACL_RSLT1, PRI_QU, sw->queue); - } - - FIELD_GET_ACTION(ACL_RSLT1, DSCP_REMAP, data); - if (data) - { - FAL_ACTION_FLG_SET(sw->action_flg, FAL_ACL_ACTION_REMARK_DSCP); - FIELD_GET_ACTION(ACL_RSLT1, DSCPV, sw->dscp); - } - - FIELD_GET_ACTION(ACL_RSLT0, STAGVID, sw->stag_vid); - - FIELD_GET_ACTION(ACL_RSLT1, TRANS_SVID_CHG, data); - if (data) - { - FAL_ACTION_FLG_SET(sw->action_flg, FAL_ACL_ACTION_REMARK_STAG_VID); - } - - FIELD_GET_ACTION(ACL_RSLT1, STAG_PRI_REMAP, data); - if (data) - { - FAL_ACTION_FLG_SET(sw->action_flg, FAL_ACL_ACTION_REMARK_STAG_PRI); - FIELD_GET_ACTION(ACL_RSLT0, STAGPRI, sw->stag_pri); - } - - FIELD_GET_ACTION(ACL_RSLT1, STAG_DEI_CHG, data); - if (data) - { - FAL_ACTION_FLG_SET(sw->action_flg, FAL_ACL_ACTION_REMARK_STAG_DEI); - FIELD_GET_ACTION(ACL_RSLT0, STAGDEI, sw->stag_dei); - } - - FIELD_GET_ACTION(ACL_RSLT0, CTAGVID, sw->ctag_vid); - - FIELD_GET_ACTION(ACL_RSLT1, TRANS_CVID_CHG, data); - if (data) - { - FAL_ACTION_FLG_SET(sw->action_flg, FAL_ACL_ACTION_REMARK_CTAG_VID); - } - - FIELD_GET_ACTION(ACL_RSLT1, CTAG_PRI_REMAP, data); - if (data) - { - FAL_ACTION_FLG_SET(sw->action_flg, FAL_ACL_ACTION_REMARK_CTAG_PRI); - FIELD_GET_ACTION(ACL_RSLT0, CTAGPRI, sw->ctag_pri); - } - - FIELD_GET_ACTION(ACL_RSLT1, CTAG_CFI_CHG, data); - if (data) - { - FAL_ACTION_FLG_SET(sw->action_flg, FAL_ACL_ACTION_REMARK_CTAG_CFI); - FIELD_GET_ACTION(ACL_RSLT0, CTAGCFI, sw->ctag_cfi); - } - - FIELD_GET_ACTION(ACL_RSLT1, LOOK_VID_CHG, data); - if (data) - { - FAL_ACTION_FLG_SET(sw->action_flg, FAL_ACL_ACTION_REMARK_LOOKUP_VID); - } - - FIELD_GET_ACTION(ACL_RSLT2, POLICER_EN, data); - if (data) - { - FAL_ACTION_FLG_SET(sw->action_flg, FAL_ACL_ACTION_POLICER_EN); - FIELD_GET_ACTION(ACL_RSLT2, POLICER_PTR, sw->policer_ptr); - } - - FIELD_GET_ACTION(ACL_RSLT1, ARP_PTR_EN, data); - if (data) - { - FIELD_GET_ACTION(ACL_RSLT1, WCMP_EN, data); - if (data) - { - FAL_ACTION_FLG_SET(sw->action_flg, FAL_ACL_ACTION_WCMP_EN); - FIELD_GET_ACTION(ACL_RSLT1, ARP_PTR, sw->wcmp_ptr); - } - else - { - FAL_ACTION_FLG_SET(sw->action_flg, FAL_ACL_ACTION_ARP_EN); - FIELD_GET_ACTION(ACL_RSLT1, ARP_PTR, sw->arp_ptr); - } - } - - FIELD_GET_ACTION(ACL_RSLT1, FORCE_L3_MODE, data); - if ((0 != data) && (3 != data)) - { - FAL_ACTION_FLG_SET(sw->action_flg, FAL_ACL_ACTION_POLICY_FORWARD_EN); - if (0x1 == data) - { - sw->policy_fwd = FAL_ACL_POLICY_SNAT; - } - else - { - sw->policy_fwd = FAL_ACL_POLICY_DNAT; - } - } - - FIELD_GET_ACTION(ACL_RSLT2, EG_BYPASS, data); - if (data) - { - FAL_ACTION_FLG_SET(sw->action_flg, FAL_ACL_ACTION_BYPASS_EGRESS_TRANS); - } - - FIELD_GET_ACTION(ACL_RSLT2, TRIGGER_INTR, data); - if (data) - { - FAL_ACTION_FLG_SET(sw->action_flg, FAL_ACL_ACTION_MATCH_TRIGGER_INTR); - } - - return SW_OK; -} - -sw_error_t -_isis_acl_rule_sw_to_hw(a_uint32_t dev_id, fal_acl_rule_t * sw, - isis_acl_rule_t * hw_rule_snap, a_uint32_t * idx) -{ - sw_error_t rv; - a_uint32_t tmp_idx, i, b_rule[7] = { 0 }; - parse_func_t ptr[7] = { NULL }; - a_bool_t b_care, b_mac, eh_mac; - - rv = _isis_acl_action_parse(dev_id, sw, &(hw_rule_snap[*idx].filter)); - SW_RTN_ON_ERROR(rv); - - ptr[0] = _isis_acl_rule_udf_parse; - _isis_acl_rule_mac_preparse(sw, &b_mac, &eh_mac); - - /* ehmac rule must be parsed bofore mac rule. - it's important for reparse process */ - if (A_TRUE == eh_mac) - { - ptr[1] = _isis_acl_rule_ehmac_parse; - } - - if (A_TRUE == b_mac) - { - ptr[2] = _isis_acl_rule_bmac_parse; - } - - if ((A_FALSE == b_mac) && (A_FALSE == eh_mac)) - { - ptr[2] = _isis_acl_rule_bmac_parse; - } - - if (FAL_ACL_RULE_MAC == sw->rule_type) - { - } - else if (FAL_ACL_RULE_IP4 == sw->rule_type) - { - ptr[3] = _isis_acl_rule_ip4_parse; - } - else if (FAL_ACL_RULE_IP6 == sw->rule_type) - { - ptr[4] = _isis_acl_rule_ip6r1_parse; - ptr[5] = _isis_acl_rule_ip6r2_parse; - ptr[6] = _isis_acl_rule_ip6r3_parse; - } - else if (FAL_ACL_RULE_UDF == sw->rule_type) - { - ptr[1] = NULL; - ptr[2] = NULL; - } - else - { - return SW_NOT_SUPPORTED; - } - - tmp_idx = *idx; - for (i = 0; i < 7; i++) - { - if (ptr[i]) - { - if (ISIS_HW_RULE_TMP_CNT <= tmp_idx) - { - return SW_NO_RESOURCE; - } - - rv = ptr[i] (sw, &(hw_rule_snap[tmp_idx].filter), &b_care); - SW_RTN_ON_ERROR(rv); - if (A_TRUE == b_care) - { - tmp_idx++; - b_rule[i] = 1; - } - } - } - - if (FAL_ACL_RULE_IP6 == sw->rule_type) - { - if ((!b_rule[4]) && (!b_rule[5]) && (!b_rule[6])) - { - tmp_idx++; - } - } - - if (FAL_ACL_RULE_IP4 == sw->rule_type) - { - if (!b_rule[3]) - { - tmp_idx++; - } - } - - if (tmp_idx == *idx) - { - /* set type start & end */ - SW_SET_REG_BY_FIELD(MAC_RUL_M4, RULE_VALID, FLT_STARTEND, - (hw_rule_snap[*idx].filter.msk[4])); - (*idx)++; - } - else - { - if (1 == (tmp_idx - *idx)) - { - if (FAL_ACL_COMBINED_START == sw->combined) - { - SW_SET_REG_BY_FIELD(MAC_RUL_M4, RULE_VALID, FLT_START, - (hw_rule_snap[*idx].filter.msk[4])); - } - else if (FAL_ACL_COMBINED_CONTINUE == sw->combined) - { - SW_SET_REG_BY_FIELD(MAC_RUL_M4, RULE_VALID, FLT_CONTINUE, - (hw_rule_snap[*idx].filter.msk[4])); - } - else if (FAL_ACL_COMBINED_END == sw->combined) - { - SW_SET_REG_BY_FIELD(MAC_RUL_M4, RULE_VALID, FLT_END, - (hw_rule_snap[*idx].filter.msk[4])); - } - else - { - SW_SET_REG_BY_FIELD(MAC_RUL_M4, RULE_VALID, FLT_STARTEND, - (hw_rule_snap[*idx].filter.msk[4])); - } - } - else - { - for (i = *idx; i < tmp_idx; i++) - { - if (i == *idx) - { - SW_SET_REG_BY_FIELD(MAC_RUL_M4, RULE_VALID, FLT_START, - (hw_rule_snap[i].filter.msk[4])); - } - else if (i == (tmp_idx - 1)) - { - SW_SET_REG_BY_FIELD(MAC_RUL_M4, RULE_VALID, FLT_END, - (hw_rule_snap[i].filter.msk[4])); - } - else - { - SW_SET_REG_BY_FIELD(MAC_RUL_M4, RULE_VALID, FLT_CONTINUE, - (hw_rule_snap[i].filter.msk[4])); - } - aos_mem_copy(&(hw_rule_snap[i].filter.act[0]), - &(hw_rule_snap[*idx].filter.act[0]), - sizeof (hw_rule_snap[*idx].filter.act)); - } - } - *idx = tmp_idx; - } - - return SW_OK; -} - -sw_error_t -_isis_acl_rule_hw_to_sw(a_uint32_t dev_id, fal_acl_rule_t * sw, - isis_acl_rule_t * hw_rule_snap, a_uint32_t idx, - a_uint32_t ent_nr) -{ - a_bool_t b_mac = A_FALSE, b_ip4 = A_FALSE, b_ip6 = A_FALSE; - sw_error_t rv; - a_uint32_t i, flt_typ; - hw_filter_t *hw; - - rv = _isis_acl_rule_action_reparse(sw, &(hw_rule_snap[idx].filter)); - SW_RTN_ON_ERROR(rv); - - sw->rule_type = FAL_ACL_RULE_UDF; - for (i = 0; i < ent_nr; i++) - { - hw = &(hw_rule_snap[idx + i].filter); - FIELD_GET_MASK(MAC_RUL_M4, RULE_TYP, flt_typ); - - if (ISIS_UDF_FILTER == flt_typ) - { - rv = _isis_acl_rule_udf_reparse(sw, hw); - SW_RTN_ON_ERROR(rv); - } - else if (ISIS_MAC_FILTER == flt_typ) - { - rv = _isis_acl_rule_bmac_reparse(sw, hw); - SW_RTN_ON_ERROR(rv); - b_mac = A_TRUE; - } - else if (ISIS_EHMAC_FILTER == flt_typ) - { - rv = _isis_acl_rule_ehmac_reparse(sw, hw); - SW_RTN_ON_ERROR(rv); - b_mac = A_TRUE; - } - else if (ISIS_IP4_FILTER == flt_typ) - { - rv = _isis_acl_rule_ip4_reparse(sw, hw); - SW_RTN_ON_ERROR(rv); - b_ip4 = A_TRUE; - } - else if (ISIS_IP6R1_FILTER == flt_typ) - { - rv = _isis_acl_rule_ip6r1_reparse(sw, hw); - SW_RTN_ON_ERROR(rv); - b_ip6 = A_TRUE; - } - else if (ISIS_IP6R2_FILTER == flt_typ) - { - rv = _isis_acl_rule_ip6r2_reparse(sw, hw); - SW_RTN_ON_ERROR(rv); - b_ip6 = A_TRUE; - } - else if (ISIS_IP6R3_FILTER == flt_typ) - { - rv = _isis_acl_rule_ip6r3_reparse(sw, hw); - SW_RTN_ON_ERROR(rv); - b_ip6 = A_TRUE; - } - else - { - /* ignore fill gap filters */ - } - } - - if (A_TRUE == b_mac) - { - sw->rule_type = FAL_ACL_RULE_MAC; - } - - if (A_TRUE == b_ip4) - { - sw->rule_type = FAL_ACL_RULE_IP4; - } - - if (A_TRUE == b_ip6) - { - sw->rule_type = FAL_ACL_RULE_IP6; - } - - return SW_OK; -} diff --git a/feeds/ipq807x/qca-ssdk/src/src/hsl/isis/isis_acl_prv.h b/feeds/ipq807x/qca-ssdk/src/src/hsl/isis/isis_acl_prv.h deleted file mode 100755 index f6b9c7fc1..000000000 --- a/feeds/ipq807x/qca-ssdk/src/src/hsl/isis/isis_acl_prv.h +++ /dev/null @@ -1,125 +0,0 @@ -/* - * Copyright (c) 2012, The Linux Foundation. All rights reserved. - * Permission to use, copy, modify, and/or distribute this software for - * any purpose with or without fee is hereby granted, provided that the - * above copyright notice and this permission notice appear in all copies. - * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES - * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR - * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES - * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN - * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT - * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. - */ - - - -typedef struct -{ - a_uint8_t status; - a_uint8_t list_id; - a_uint8_t list_pri; - a_uint8_t rule_nr; - fal_pbmp_t bind_pts; -} isis_acl_list_t; - - -typedef struct -{ - a_uint32_t vlu[5]; - a_uint32_t msk[5]; - a_uint32_t act[3]; -} hw_filter_t; - - -typedef struct -{ - a_uint8_t status; - a_uint8_t list_id; - a_uint8_t list_pri; - a_uint8_t rule_id; - hw_filter_t filter; -} isis_acl_rule_t; - - -#define ENT_USED 0x1 -#define ENT_TMP 0x2 -#define ENT_DEACTIVE 0x4 - -#define FLT_START 0x0 -#define FLT_CONTINUE 0x1 -#define FLT_END 0x2 -#define FLT_STARTEND 0x3 - - -#define ISIS_MAC_FILTER 1 -#define ISIS_IP4_FILTER 2 -#define ISIS_IP6R1_FILTER 3 -#define ISIS_IP6R2_FILTER 4 -#define ISIS_IP6R3_FILTER 5 -#define ISIS_UDF_FILTER 6 -#define ISIS_EHMAC_FILTER 7 - - -#define ISIS_MAX_UDF_OFFSET 31 -#define ISIS_MAX_UDF_LENGTH 16 - - -#define ISIS_FILTER_VLU_OP 0x0 -#define ISIS_FILTER_MSK_OP 0x1 -#define ISIS_FILTER_ACT_OP 0x2 - - - -//#define ISIS_MAX_FILTER 8 -#define ISIS_MAX_FILTER 96 -#define ISIS_RULE_FUNC_ADDR 0x0400 -#define ISIS_HW_RULE_TMP_CNT (ISIS_MAX_FILTER + 4) - -#define ISIS_MAX_LIST_ID 255 -#define ISIS_MAX_LIST_PRI 255 - -#define ISIS_UDF_MAX_LENGTH 15 -#define ISIS_UDF_MAX_OFFSET 31 - -#define WIN_RULE_CTL0_ADDR 0x218 -#define WIN_RULE_CTL1_ADDR 0x234 - - -#define ISIS_FILTER_VLU_ADDR 0x58000 -#define ISIS_FILTER_MSK_ADDR 0x59000 -#define ISIS_FILTER_ACT_ADDR 0x5a000 - - -#define FIELD_SET(reg, field, val) \ - SW_REG_SET_BY_FIELD_U32(hw->vlu[reg], val, reg##_##field##_BOFFSET, \ - reg##_##field##_BLEN) - -#define FIELD_GET(reg, field, val) \ - SW_FIELD_GET_BY_REG_U32(hw->vlu[reg], val, reg##_##field##_BOFFSET, \ - reg##_##field##_BLEN) - -#define FIELD_SET_MASK(reg, field, val) \ - SW_REG_SET_BY_FIELD_U32(hw->msk[reg-5], val, reg##_##field##_BOFFSET, \ - reg##_##field##_BLEN) - -#define FIELD_GET_MASK(reg, field, val) \ - SW_FIELD_GET_BY_REG_U32(hw->msk[reg-5], val, reg##_##field##_BOFFSET, \ - reg##_##field##_BLEN) - -#define FIELD_SET_ACTION(reg, field, val) \ - SW_REG_SET_BY_FIELD_U32(hw->act[reg-10], val, reg##_##field##_BOFFSET, \ - reg##_##field##_BLEN) - -#define FIELD_GET_ACTION(reg, field, val) \ - SW_FIELD_GET_BY_REG_U32(hw->act[reg-10], val, reg##_##field##_BOFFSET, \ - reg##_##field##_BLEN) - -sw_error_t -_isis_acl_rule_sw_to_hw(a_uint32_t dev_id, fal_acl_rule_t * sw, isis_acl_rule_t * hw_filter_snap, a_uint32_t * idx); - - -sw_error_t -_isis_acl_rule_hw_to_sw(a_uint32_t dev_id, fal_acl_rule_t * sw, isis_acl_rule_t * hw_filter_snap, a_uint32_t idx, a_uint32_t ent_nr); - - diff --git a/feeds/ipq807x/qca-ssdk/src/src/hsl/isis/isis_cosmap.c b/feeds/ipq807x/qca-ssdk/src/src/hsl/isis/isis_cosmap.c deleted file mode 100755 index 4cecb0268..000000000 --- a/feeds/ipq807x/qca-ssdk/src/src/hsl/isis/isis_cosmap.c +++ /dev/null @@ -1,637 +0,0 @@ -/* - * Copyright (c) 2012, 2016, The Linux Foundation. All rights reserved. - * Permission to use, copy, modify, and/or distribute this software for - * any purpose with or without fee is hereby granted, provided that the - * above copyright notice and this permission notice appear in all copies. - * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES - * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR - * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES - * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN - * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT - * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. - */ - - -/** - * @defgroup isis_cosmap ISIS_COSMAP - * @{ - */ -#include "sw.h" -#include "hsl.h" -#include "hsl_dev.h" -#include "hsl_port_prop.h" -#include "isis_cosmap.h" -#include "isis_reg.h" - -#define ISIS_MAX_DSCP 63 -#define ISIS_MAX_UP 7 -#define ISIS_MAX_PRI 7 -#define ISIS_MAX_DP 1 -#define ISIS_MAX_QUEUE 3 -#define ISIS_MAX_EH_QUEUE 5 - -#define ISIS_DSCP_TO_PRI 0 -#define ISIS_DSCP_TO_DP 1 -#define ISIS_UP_TO_PRI 2 -#define ISIS_UP_TO_DP 3 - -#define ISIS_EGRESS_REAMRK_ADDR 0x5ae00 -#define ISIS_EGRESS_REAMRK_NUM 16 - -static sw_error_t -_isis_cosmap_dscp_to_pri_dp_set(a_uint32_t dev_id, a_uint32_t mode, - a_uint32_t dscp, a_uint32_t val) -{ - sw_error_t rv; - a_uint32_t index, data = 0; - - if (ISIS_MAX_DSCP < dscp) - { - return SW_BAD_PARAM; - } - - index = dscp >> 3; - HSL_REG_ENTRY_GET(rv, dev_id, DSCP_TO_PRI, index, (a_uint8_t *) (&data), - sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - - if (ISIS_DSCP_TO_PRI == mode) - { - if (ISIS_MAX_PRI < val) - { - return SW_BAD_PARAM; - } - - data &= (~(0x7 << ((dscp & 0x7) << 2))); - data |= (val << ((dscp & 0x7) << 2)); - } - else - { - if (ISIS_MAX_DP < val) - { - return SW_BAD_PARAM; - } - - data &= (~(0x1 << (((dscp & 0x7) << 2) + 3))); - data |= (val << (((dscp & 0x7) << 2) + 3)); - } - - HSL_REG_ENTRY_SET(rv, dev_id, DSCP_TO_PRI, index, (a_uint8_t *) (&data), - sizeof (a_uint32_t)); - return rv; -} - -static sw_error_t -_isis_cosmap_dscp_to_pri_dp_get(a_uint32_t dev_id, a_uint32_t mode, - a_uint32_t dscp, a_uint32_t * val) -{ - sw_error_t rv; - a_uint32_t index, data = 0; - - if (ISIS_MAX_DSCP < dscp) - { - return SW_BAD_PARAM; - } - - index = dscp >> 3; - HSL_REG_ENTRY_GET(rv, dev_id, DSCP_TO_PRI, index, (a_uint8_t *) (&data), - sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - - data = (data >> ((dscp & 0x7) << 2)) & 0xf; - if (ISIS_DSCP_TO_PRI == mode) - { - *val = data & 0x7; - } - else - { - *val = (data & 0x8) >> 3; - } - - return SW_OK; -} - -static sw_error_t -_isis_cosmap_up_to_pri_dp_set(a_uint32_t dev_id, a_uint32_t mode, a_uint32_t up, - a_uint32_t val) -{ - sw_error_t rv; - a_uint32_t data = 0; - - if (ISIS_MAX_UP < up) - { - return SW_BAD_PARAM; - } - - HSL_REG_ENTRY_GET(rv, dev_id, UP_TO_PRI, 0, (a_uint8_t *) (&data), - sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - - if (ISIS_UP_TO_PRI == mode) - { - if (ISIS_MAX_PRI < val) - { - return SW_BAD_PARAM; - } - - data &= (~(0x7 << (up << 2))); - data |= (val << (up << 2)); - } - else - { - if (ISIS_MAX_DP < val) - { - return SW_BAD_PARAM; - } - - data &= (~(0x1 << ((up << 2) + 3))); - data |= (val << ((up << 2) + 3)); - } - - HSL_REG_ENTRY_SET(rv, dev_id, UP_TO_PRI, 0, (a_uint8_t *) (&data), - sizeof (a_uint32_t)); - return rv; -} - -static sw_error_t -_isis_cosmap_up_to_pri_dp_get(a_uint32_t dev_id, a_uint32_t mode, a_uint32_t up, - a_uint32_t * val) -{ - sw_error_t rv; - a_uint32_t data = 0; - - if (ISIS_MAX_UP < up) - { - return SW_BAD_PARAM; - } - - HSL_REG_ENTRY_GET(rv, dev_id, UP_TO_PRI, 0, (a_uint8_t *) (&data), - sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - - data = (data >> (up << 2)) & 0xf; - - if (ISIS_UP_TO_PRI == mode) - { - *val = (data & 0x7); - } - else - { - *val = (data & 0x8) >> 3; - } - - return SW_OK; -} - -static sw_error_t -_isis_cosmap_pri_to_queue_set(a_uint32_t dev_id, a_uint32_t pri, - a_uint32_t queue) -{ - sw_error_t rv; - a_uint32_t data = 0; - - if ((ISIS_MAX_PRI < pri) || (ISIS_MAX_QUEUE < queue)) - { - return SW_BAD_PARAM; - } - - HSL_REG_ENTRY_GET(rv, dev_id, PRI_TO_QUEUE, 0, (a_uint8_t *) (&data), - sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - - data &= (~(0x3 << (pri << 2))); - data |= (queue << (pri << 2)); - - HSL_REG_ENTRY_SET(rv, dev_id, PRI_TO_QUEUE, 0, (a_uint8_t *) (&data), - sizeof (a_uint32_t)); - return rv; -} - -static sw_error_t -_isis_cosmap_pri_to_queue_get(a_uint32_t dev_id, a_uint32_t pri, - a_uint32_t * queue) -{ - sw_error_t rv; - a_uint32_t data = 0; - - if (ISIS_MAX_PRI < pri) - { - return SW_BAD_PARAM; - } - - HSL_REG_ENTRY_GET(rv, dev_id, PRI_TO_QUEUE, 0, (a_uint8_t *) (&data), - sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - - *queue = (data >> (pri << 2)) & 0x3; - return SW_OK; -} - -static sw_error_t -_isis_cosmap_pri_to_ehqueue_set(a_uint32_t dev_id, a_uint32_t pri, - a_uint32_t queue) -{ - sw_error_t rv; - a_uint32_t data = 0; - - if ((ISIS_MAX_PRI < pri) || (ISIS_MAX_EH_QUEUE < queue)) - { - return SW_BAD_PARAM; - } - - HSL_REG_ENTRY_GET(rv, dev_id, PRI_TO_EHQUEUE, 0, (a_uint8_t *) (&data), - sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - - data &= (~(0x7 << (pri << 2))); - data |= (queue << (pri << 2)); - - HSL_REG_ENTRY_SET(rv, dev_id, PRI_TO_EHQUEUE, 0, (a_uint8_t *) (&data), - sizeof (a_uint32_t)); - return rv; -} - -static sw_error_t -_isis_cosmap_pri_to_ehqueue_get(a_uint32_t dev_id, a_uint32_t pri, - a_uint32_t * queue) -{ - sw_error_t rv; - a_uint32_t data= 0; - - if (ISIS_MAX_PRI < pri) - { - return SW_BAD_PARAM; - } - - HSL_REG_ENTRY_GET(rv, dev_id, PRI_TO_EHQUEUE, 0, (a_uint8_t *) (&data), - sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - - *queue = (data >> (pri << 2)) & 0x7; - return SW_OK; -} - -static sw_error_t -_isis_cosmap_egress_remark_set(a_uint32_t dev_id, a_uint32_t tbl_id, - fal_egress_remark_table_t * tbl) -{ - sw_error_t rv; - a_uint32_t data, addr; - - if (ISIS_EGRESS_REAMRK_NUM <= tbl_id) - { - return SW_BAD_PARAM; - } - - data = (tbl->y_up & 0x7) - | ((tbl->g_up & 0x7) << 4) - | ((tbl->y_dscp & 0x3f) << 8) - | ((tbl->g_dscp & 0x3f) << 16) - | ((tbl->remark_dscp & 0x1) << 23) - | ((tbl->remark_up & 0x1) << 22); - - addr = ISIS_EGRESS_REAMRK_ADDR + (tbl_id << 2); - HSL_REG_ENTRY_GEN_SET(rv, dev_id, addr, sizeof (a_uint32_t), - (a_uint8_t *) (&data), sizeof (a_uint32_t)); - return rv; -} - -static sw_error_t -_isis_cosmap_egress_remark_get(a_uint32_t dev_id, a_uint32_t tbl_id, - fal_egress_remark_table_t * tbl) -{ - sw_error_t rv; - a_uint32_t data = 0, addr; - - if (ISIS_EGRESS_REAMRK_NUM <= tbl_id) - { - return SW_BAD_PARAM; - } - - aos_mem_zero(tbl, sizeof (fal_egress_remark_table_t)); - - addr = ISIS_EGRESS_REAMRK_ADDR + (tbl_id << 2); - HSL_REG_ENTRY_GEN_GET(rv, dev_id, addr, sizeof (a_uint32_t), - (a_uint8_t *) (&data), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - - if (data & (0x1 << 23)) - { - tbl->remark_dscp = A_TRUE; - tbl->y_dscp = (data >> 8) & 0x3f; - tbl->g_dscp = (data >> 16) & 0x3f; - } - - if (data & (0x1 << 22)) - { - tbl->remark_up = A_TRUE; - tbl->y_up = data & 0x7; - tbl->g_up = (data >> 4) & 0x7; - } - - return SW_OK; -} - -/** - * @brief Set dscp to internal priority mapping on one particular device. - * @param[in] dev_id device id - * @param[in] dscp dscp - * @param[in] pri internal priority - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -isis_cosmap_dscp_to_pri_set(a_uint32_t dev_id, a_uint32_t dscp, a_uint32_t pri) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _isis_cosmap_dscp_to_pri_dp_set(dev_id, ISIS_DSCP_TO_PRI, dscp, pri); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Get dscp to internal priority mapping on one particular device. - * @param[in] dev_id device id - * @param[in] dscp dscp - * @param[out] pri internal priority - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -isis_cosmap_dscp_to_pri_get(a_uint32_t dev_id, a_uint32_t dscp, - a_uint32_t * pri) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _isis_cosmap_dscp_to_pri_dp_get(dev_id, ISIS_DSCP_TO_PRI, dscp, pri); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Set dscp to internal drop precedence mapping on one particular device. - * @param[in] dev_id device id - * @param[in] dscp dscp - * @param[in] dp internal drop precedence - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -isis_cosmap_dscp_to_dp_set(a_uint32_t dev_id, a_uint32_t dscp, a_uint32_t dp) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _isis_cosmap_dscp_to_pri_dp_set(dev_id, ISIS_DSCP_TO_DP, dscp, dp); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Get dscp to internal drop precedence mapping on one particular device. - * @param[in] dev_id device id - * @param[in] dscp dscp - * @param[out] dp internal drop precedence - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -isis_cosmap_dscp_to_dp_get(a_uint32_t dev_id, a_uint32_t dscp, a_uint32_t * dp) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _isis_cosmap_dscp_to_pri_dp_get(dev_id, ISIS_DSCP_TO_DP, dscp, dp); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Set dot1p to internal priority mapping on one particular device. - * @param[in] dev_id device id - * @param[in] up dot1p - * @param[in] pri internal priority - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -isis_cosmap_up_to_pri_set(a_uint32_t dev_id, a_uint32_t up, a_uint32_t pri) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _isis_cosmap_up_to_pri_dp_set(dev_id, ISIS_UP_TO_PRI, up, pri); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Get dot1p to internal priority mapping on one particular device. - * @param[in] dev_id device id - * @param[in] up dot1p - * @param[out] pri internal priority - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -isis_cosmap_up_to_pri_get(a_uint32_t dev_id, a_uint32_t up, a_uint32_t * pri) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _isis_cosmap_up_to_pri_dp_get(dev_id, ISIS_UP_TO_PRI, up, pri); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Set dot1p to internal drop precedence mapping on one particular device. - * @param[in] dev_id device id - * @param[in] up dot1p - * @param[in] dp internal drop precedence - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -isis_cosmap_up_to_dp_set(a_uint32_t dev_id, a_uint32_t up, a_uint32_t dp) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _isis_cosmap_up_to_pri_dp_set(dev_id, ISIS_UP_TO_DP, up, dp); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Get dot1p to internal drop precedence mapping on one particular device. - * @param[in] dev_id device id - * @param[in] up dot1p - * @param[in] dp internal drop precedence - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -isis_cosmap_up_to_dp_get(a_uint32_t dev_id, a_uint32_t up, a_uint32_t * dp) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _isis_cosmap_up_to_pri_dp_get(dev_id, ISIS_UP_TO_DP, up, dp); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Set internal priority to queue mapping on one particular device. - * @details Comments: - * This function is for port 1/2/3/4 which have four egress queues - * @param[in] dev_id device id - * @param[in] pri internal priority - * @param[in] queue queue id - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -isis_cosmap_pri_to_queue_set(a_uint32_t dev_id, a_uint32_t pri, - a_uint32_t queue) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _isis_cosmap_pri_to_queue_set(dev_id, pri, queue); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Get internal priority to queue mapping on one particular device. - * @details Comments: - * This function is for port 1/2/3/4 which have four egress queues - * @param[in] dev_id device id - * @param[in] pri internal priority - * @param[out] queue queue id - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -isis_cosmap_pri_to_queue_get(a_uint32_t dev_id, a_uint32_t pri, - a_uint32_t * queue) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _isis_cosmap_pri_to_queue_get(dev_id, pri, queue); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Set internal priority to queue mapping on one particular device. - * @details Comments: - * This function is for port 0/5/6 which have six egress queues - * @param[in] dev_id device id - * @param[in] pri internal priority - * @param[in] queue queue id - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -isis_cosmap_pri_to_ehqueue_set(a_uint32_t dev_id, a_uint32_t pri, - a_uint32_t queue) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _isis_cosmap_pri_to_ehqueue_set(dev_id, pri, queue); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Get internal priority to queue mapping on one particular device. - * @details Comments: - * This function is for port 0/5/6 which have six egress queues - * @param[in] dev_id device id - * @param[in] pri internal priority - * @param[in] queue queue id - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -isis_cosmap_pri_to_ehqueue_get(a_uint32_t dev_id, a_uint32_t pri, - a_uint32_t * queue) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _isis_cosmap_pri_to_ehqueue_get(dev_id, pri, queue); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Set egress queue based CoS remap table on one particular device. - * @param[in] dev_id device id - * @param[in] tbl_id CoS remap table id - * @param[in] tbl CoS remap table - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -isis_cosmap_egress_remark_set(a_uint32_t dev_id, a_uint32_t tbl_id, - fal_egress_remark_table_t * tbl) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _isis_cosmap_egress_remark_set(dev_id, tbl_id, tbl); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Get egress queue based CoS remap table on one particular device. - * @param[in] dev_id device id - * @param[in] tbl_id CoS remap table id - * @param[out] tbl CoS remap table - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -isis_cosmap_egress_remark_get(a_uint32_t dev_id, a_uint32_t tbl_id, - fal_egress_remark_table_t * tbl) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _isis_cosmap_egress_remark_get(dev_id, tbl_id, tbl); - HSL_API_UNLOCK; - return rv; -} - -sw_error_t -isis_cosmap_init(a_uint32_t dev_id) -{ - HSL_DEV_ID_CHECK(dev_id); - -#ifndef HSL_STANDALONG - { - hsl_api_t *p_api; - - SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id)); - - p_api->cosmap_dscp_to_pri_set = isis_cosmap_dscp_to_pri_set; - p_api->cosmap_dscp_to_pri_get = isis_cosmap_dscp_to_pri_get; - p_api->cosmap_dscp_to_dp_set = isis_cosmap_dscp_to_dp_set; - p_api->cosmap_dscp_to_dp_get = isis_cosmap_dscp_to_dp_get; - p_api->cosmap_up_to_pri_set = isis_cosmap_up_to_pri_set; - p_api->cosmap_up_to_pri_get = isis_cosmap_up_to_pri_get; - p_api->cosmap_up_to_dp_set = isis_cosmap_up_to_dp_set; - p_api->cosmap_up_to_dp_get = isis_cosmap_up_to_dp_get; - p_api->cosmap_pri_to_queue_set = isis_cosmap_pri_to_queue_set; - p_api->cosmap_pri_to_queue_get = isis_cosmap_pri_to_queue_get; - p_api->cosmap_pri_to_ehqueue_set = isis_cosmap_pri_to_ehqueue_set; - p_api->cosmap_pri_to_ehqueue_get = isis_cosmap_pri_to_ehqueue_get; - p_api->cosmap_egress_remark_set = isis_cosmap_egress_remark_set; - p_api->cosmap_egress_remark_get = isis_cosmap_egress_remark_get; - } -#endif - - return SW_OK; -} - -/** - * @} - */ - diff --git a/feeds/ipq807x/qca-ssdk/src/src/hsl/isis/isis_fdb.c b/feeds/ipq807x/qca-ssdk/src/src/hsl/isis/isis_fdb.c deleted file mode 100755 index da21f2276..000000000 --- a/feeds/ipq807x/qca-ssdk/src/src/hsl/isis/isis_fdb.c +++ /dev/null @@ -1,2217 +0,0 @@ -/* - * Copyright (c) 2012, 2016, The Linux Foundation. All rights reserved. - * Permission to use, copy, modify, and/or distribute this software for - * any purpose with or without fee is hereby granted, provided that the - * above copyright notice and this permission notice appear in all copies. - * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES - * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR - * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES - * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN - * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT - * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. - */ - - -/** - * @defgroup isis_fdb ISIS_FDB - * @{ - */ -#include "sw.h" -#include "hsl.h" -#include "hsl_dev.h" -#include "hsl_port_prop.h" -#include "isis_fdb.h" -#include "isis_reg.h" - -#define ARL_FLUSH_ALL 1 -#define ARL_LOAD_ENTRY 2 -#define ARL_PURGE_ENTRY 3 -#define ARL_FLUSH_ALL_UNLOCK 4 -#define ARL_FLUSH_PORT_UNICAST 5 -#define ARL_NEXT_ENTRY 6 -#define ARL_FIND_ENTRY 7 -#define ARL_TRANSFER_ENTRY 8 - -#define ARL_FIRST_ENTRY 1001 -#define ARL_FLUSH_PORT_NO_STATIC 1002 -#define ARL_FLUSH_PORT_AND_STATIC 1003 - -#define ISIS_MAX_FID 4095 -#define ISIS_MAX_LEARN_LIMIT_CNT 2047 -#define ISIS_MAX_PORT_LEARN_LIMIT_CNT 1023 - -static sw_error_t -_isis_wl_feature_check(a_uint32_t dev_id) -{ - sw_error_t rv; - a_uint32_t entry = 0; - - HSL_REG_FIELD_GET(rv, dev_id, MASK_CTL, 0, DEVICE_ID, - (a_uint8_t *) (&entry), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - - if (S17_DEVICE_ID == entry) - { - return SW_OK; - } - else - { - return SW_NOT_SUPPORTED; - } -} - -static a_bool_t -_isis_fdb_is_zeroaddr(fal_mac_addr_t addr) -{ - a_uint32_t i; - - for (i = 0; i < 6; i++) - { - if (addr.uc[i]) - { - return A_FALSE; - } - } - - return A_TRUE; -} - -static void -_isis_fdb_fill_addr(fal_mac_addr_t addr, a_uint32_t * reg0, a_uint32_t * reg1) -{ - SW_SET_REG_BY_FIELD(ADDR_TABLE_FUNC1, AT_ADDR_BYTE0, addr.uc[0], *reg1); - SW_SET_REG_BY_FIELD(ADDR_TABLE_FUNC1, AT_ADDR_BYTE1, addr.uc[1], *reg1); - - SW_SET_REG_BY_FIELD(ADDR_TABLE_FUNC0, AT_ADDR_BYTE2, addr.uc[2], *reg0); - SW_SET_REG_BY_FIELD(ADDR_TABLE_FUNC0, AT_ADDR_BYTE3, addr.uc[3], *reg0); - SW_SET_REG_BY_FIELD(ADDR_TABLE_FUNC0, AT_ADDR_BYTE4, addr.uc[4], *reg0); - SW_SET_REG_BY_FIELD(ADDR_TABLE_FUNC0, AT_ADDR_BYTE5, addr.uc[5], *reg0); - - return; -} - -static sw_error_t -_isis_atu_sw_to_hw(a_uint32_t dev_id, const fal_fdb_entry_t * entry, - a_uint32_t reg[]) -{ - a_uint32_t port; - sw_error_t rv; - - if (A_TRUE == entry->white_list_en) - { - rv = _isis_wl_feature_check(dev_id); - SW_RTN_ON_ERROR(rv); - - SW_SET_REG_BY_FIELD(ADDR_TABLE_FUNC2, WL_EN, 1, reg[2]); - } - - if (FAL_SVL_FID == entry->fid) - { - SW_SET_REG_BY_FIELD(ADDR_TABLE_FUNC2, AT_VID, 0, reg[2]); - SW_SET_REG_BY_FIELD(ADDR_TABLE_FUNC1, AT_SVL_EN, 1, reg[1]); - } - else if (ISIS_MAX_FID >= entry->fid) - { - SW_SET_REG_BY_FIELD(ADDR_TABLE_FUNC2, AT_VID, (entry->fid), reg[2]); - SW_SET_REG_BY_FIELD(ADDR_TABLE_FUNC1, AT_SVL_EN, 0, reg[1]); - } - else - { - return SW_BAD_PARAM; - } - - if (A_FALSE == entry->portmap_en) - { - if (A_TRUE != - hsl_port_prop_check(dev_id, entry->port.id, HSL_PP_INCL_CPU)) - { - return SW_BAD_PARAM; - } - - port = 0x1UL << entry->port.id; - } - else - { - if (A_FALSE == - hsl_mports_prop_check(dev_id, entry->port.map, HSL_PP_INCL_CPU)) - { - return SW_BAD_PARAM; - } - - port = entry->port.map; - } - SW_SET_REG_BY_FIELD(ADDR_TABLE_FUNC1, DES_PORT, port, reg[1]); - - if (FAL_MAC_CPY_TO_CPU == entry->dacmd) - { - SW_SET_REG_BY_FIELD(ADDR_TABLE_FUNC2, COPY_TO_CPU, 1, reg[2]); - } - else if (FAL_MAC_RDT_TO_CPU == entry->dacmd) - { - SW_SET_REG_BY_FIELD(ADDR_TABLE_FUNC2, REDRCT_TO_CPU, 1, reg[2]); - } - else if (FAL_MAC_FRWRD != entry->dacmd) - { - return SW_NOT_SUPPORTED; - } - - if (A_TRUE == entry->leaky_en) - { - SW_SET_REG_BY_FIELD(ADDR_TABLE_FUNC2, LEAKY_EN, 1, reg[2]); - } - else - { - SW_SET_REG_BY_FIELD(ADDR_TABLE_FUNC2, LEAKY_EN, 0, reg[2]); - } - - if (A_TRUE == entry->static_en) - { - SW_SET_REG_BY_FIELD(ADDR_TABLE_FUNC2, AT_STATUS, 15, reg[2]); - } - else - { - SW_SET_REG_BY_FIELD(ADDR_TABLE_FUNC2, AT_STATUS, 7, reg[2]); - } - - if (FAL_MAC_DROP == entry->sacmd) - { - SW_SET_REG_BY_FIELD(ADDR_TABLE_FUNC1, SA_DROP_EN, 1, reg[1]); - } - else if (FAL_MAC_FRWRD != entry->sacmd) - { - return SW_NOT_SUPPORTED; - } - - if (A_TRUE == entry->mirror_en) - { - SW_SET_REG_BY_FIELD(ADDR_TABLE_FUNC1, MIRROR_EN, 1, reg[1]); - } - - if (A_TRUE == entry->cross_pt_state) - { - SW_SET_REG_BY_FIELD(ADDR_TABLE_FUNC1, CROSS_PT, 1, reg[1]); - } - else - { - SW_SET_REG_BY_FIELD(ADDR_TABLE_FUNC1, CROSS_PT, 0, reg[1]); - } - - if (A_TRUE == entry->da_pri_en) - { - SW_SET_REG_BY_FIELD(ADDR_TABLE_FUNC1, AT_PRI_EN, 1, reg[1]); - SW_SET_REG_BY_FIELD(ADDR_TABLE_FUNC1, AT_PRI, (entry->da_queue & 0x7), - reg[1]); - } - else - { - SW_SET_REG_BY_FIELD(ADDR_TABLE_FUNC1, AT_PRI_EN, 0, reg[1]); - } - - _isis_fdb_fill_addr(entry->addr, ®[0], ®[1]); - return SW_OK; -} - -static void -_isis_atu_hw_to_sw(const a_uint32_t reg[], fal_fdb_entry_t * entry) -{ - a_uint32_t i, data; - - aos_mem_zero(entry, sizeof (fal_fdb_entry_t)); - - SW_GET_FIELD_BY_REG(ADDR_TABLE_FUNC1, AT_SVL_EN, data, reg[1]); - if (data) - { - entry->fid = FAL_SVL_FID; - } - else - { - SW_GET_FIELD_BY_REG(ADDR_TABLE_FUNC2, AT_VID, data, reg[2]); - entry->fid = data; - } - - entry->dacmd = FAL_MAC_FRWRD; - SW_GET_FIELD_BY_REG(ADDR_TABLE_FUNC2, COPY_TO_CPU, data, reg[2]); - if (1 == data) - { - entry->dacmd = FAL_MAC_CPY_TO_CPU; - } - - SW_GET_FIELD_BY_REG(ADDR_TABLE_FUNC2, REDRCT_TO_CPU, data, reg[2]); - if (1 == data) - { - entry->dacmd = FAL_MAC_RDT_TO_CPU; - } - - entry->sacmd = FAL_MAC_FRWRD; - SW_GET_FIELD_BY_REG(ADDR_TABLE_FUNC1, SA_DROP_EN, data, reg[1]); - if (1 == data) - { - entry->sacmd = FAL_MAC_DROP; - } - - entry->leaky_en = A_FALSE; - SW_GET_FIELD_BY_REG(ADDR_TABLE_FUNC2, LEAKY_EN, data, reg[2]); - if (1 == data) - { - entry->leaky_en = A_TRUE; - } - - entry->static_en = A_FALSE; - SW_GET_FIELD_BY_REG(ADDR_TABLE_FUNC2, AT_STATUS, data, reg[2]); - if (0xf == data) - { - entry->static_en = A_TRUE; - } - - entry->mirror_en = A_FALSE; - SW_GET_FIELD_BY_REG(ADDR_TABLE_FUNC1, MIRROR_EN, data, reg[1]); - if (1 == data) - { - entry->mirror_en = A_TRUE; - } - - entry->da_pri_en = A_FALSE; - SW_GET_FIELD_BY_REG(ADDR_TABLE_FUNC1, AT_PRI_EN, data, reg[1]); - if (1 == data) - { - SW_GET_FIELD_BY_REG(ADDR_TABLE_FUNC1, AT_PRI, data, reg[1]); - entry->da_pri_en = A_TRUE; - entry->da_queue = data & 0x7; - } - - entry->cross_pt_state = A_FALSE; - SW_GET_FIELD_BY_REG(ADDR_TABLE_FUNC1, CROSS_PT, data, reg[1]); - if (1 == data) - { - entry->cross_pt_state = A_TRUE; - } - - SW_GET_FIELD_BY_REG(ADDR_TABLE_FUNC1, DES_PORT, data, reg[1]); - entry->portmap_en = A_TRUE; - entry->port.map = data; - - for (i = 2; i < 6; i++) - { - entry->addr.uc[i] = (reg[0] >> ((5 - i) << 3)) & 0xff; - } - - for (i = 0; i < 2; i++) - { - entry->addr.uc[i] = (reg[1] >> ((1 - i) << 3)) & 0xff; - } - - entry->white_list_en = A_FALSE; - SW_GET_FIELD_BY_REG(ADDR_TABLE_FUNC2, WL_EN, data, reg[2]); - if (1 == data) - { - entry->white_list_en = A_TRUE; - } - - return; -} - -static sw_error_t -_isis_atu_down_to_hw(a_uint32_t dev_id, a_uint32_t reg[]) -{ - sw_error_t rv; - - HSL_REG_ENTRY_SET(rv, dev_id, ADDR_TABLE_FUNC0, 0, - (a_uint8_t *) (®[0]), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - - HSL_REG_ENTRY_SET(rv, dev_id, ADDR_TABLE_FUNC1, 0, - (a_uint8_t *) (®[1]), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - - HSL_REG_ENTRY_SET(rv, dev_id, ADDR_TABLE_FUNC2, 0, - (a_uint8_t *) (®[2]), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - - HSL_REG_ENTRY_SET(rv, dev_id, ADDR_TABLE_FUNC3, 0, - (a_uint8_t *) (®[3]), sizeof (a_uint32_t)); - return rv; -} - -static sw_error_t -_isis_atu_up_to_sw(a_uint32_t dev_id, a_uint32_t reg[]) -{ - sw_error_t rv; - - HSL_REG_ENTRY_GET(rv, dev_id, ADDR_TABLE_FUNC0, 0, - (a_uint8_t *) (®[0]), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - - HSL_REG_ENTRY_GET(rv, dev_id, ADDR_TABLE_FUNC1, 0, - (a_uint8_t *) (®[1]), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - - HSL_REG_ENTRY_GET(rv, dev_id, ADDR_TABLE_FUNC2, 0, - (a_uint8_t *) (®[2]), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - - HSL_REG_ENTRY_GET(rv, dev_id, ADDR_TABLE_FUNC3, 0, - (a_uint8_t *) (®[3]), sizeof (a_uint32_t)); - return rv; -} - -static sw_error_t -_isis_fdb_commit(a_uint32_t dev_id, a_uint32_t op) -{ - sw_error_t rv; - a_uint32_t busy = 1; - a_uint32_t full_vio; - a_uint32_t i = 2000; - a_uint32_t entry = 0; - a_uint32_t hwop = op; - - while (busy && --i) - { - HSL_REG_ENTRY_GET(rv, dev_id, ADDR_TABLE_FUNC3, 0, - (a_uint8_t *) (&entry), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - SW_GET_FIELD_BY_REG(ADDR_TABLE_FUNC3, AT_BUSY, busy, entry); - aos_udelay(5); - } - - if (0 == i) - { - printk("%s BUSY\n", __FUNCTION__); - return SW_BUSY; - } - - if (ARL_FIRST_ENTRY == op) - { - hwop = ARL_NEXT_ENTRY; - } - - SW_SET_REG_BY_FIELD(ADDR_TABLE_FUNC3, AT_BUSY, 1, entry); - - if (ARL_FLUSH_PORT_AND_STATIC == hwop) - { - hwop = ARL_FLUSH_PORT_UNICAST; - SW_SET_REG_BY_FIELD(ADDR_TABLE_FUNC3, FLUSH_ST_EN, 1, entry); - } - - if (ARL_FLUSH_PORT_NO_STATIC == hwop) - { - hwop = ARL_FLUSH_PORT_UNICAST; - SW_SET_REG_BY_FIELD(ADDR_TABLE_FUNC3, FLUSH_ST_EN, 0, entry); - } - - SW_SET_REG_BY_FIELD(ADDR_TABLE_FUNC3, AT_FUNC, hwop, entry); - - HSL_REG_ENTRY_SET(rv, dev_id, ADDR_TABLE_FUNC3, 0, - (a_uint8_t *) (&entry), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - - busy = 1; - i = 2000; - while (busy && --i) - { - HSL_REG_ENTRY_GET(rv, dev_id, ADDR_TABLE_FUNC3, 0, - (a_uint8_t *) (&entry), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - SW_GET_FIELD_BY_REG(ADDR_TABLE_FUNC3, AT_BUSY, busy, entry); - } - - if (0 == i) - { - return SW_FAIL; - } - - SW_GET_FIELD_BY_REG(ADDR_TABLE_FUNC3, AT_FULL_VIO, full_vio, entry); - - if (full_vio) - { - /* must clear AT_FULL_VOI bit */ - entry = 0x1000; - HSL_REG_ENTRY_SET(rv, dev_id, ADDR_TABLE_FUNC3, 0, - (a_uint8_t *) (&entry), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - - if (ARL_LOAD_ENTRY == hwop) - { - return SW_FULL; - } - else if ((ARL_PURGE_ENTRY == hwop) - || (ARL_FLUSH_PORT_UNICAST == hwop)) - { - return SW_NOT_FOUND; - } - else - { - return SW_FAIL; - } - } - - return SW_OK; -} - -static sw_error_t -_isis_fdb_get(a_uint32_t dev_id, fal_fdb_op_t * option, fal_fdb_entry_t * entry, - a_uint32_t hwop) -{ - sw_error_t rv; - a_uint32_t i, port = 0, status, reg[4] = { 0 }; - - HSL_DEV_ID_CHECK(dev_id); - - if (A_TRUE == option->port_en) - { - SW_SET_REG_BY_FIELD(ADDR_TABLE_FUNC3, AT_PORT_EN, 1, reg[3]); - if (A_FALSE == entry->portmap_en) - { - if (A_TRUE != - hsl_port_prop_check(dev_id, entry->port.id, HSL_PP_INCL_CPU)) - { - return SW_BAD_PARAM; - } - port = entry->port.id; - } - else - { - if (A_FALSE == - hsl_mports_prop_check(dev_id, entry->port.map, - HSL_PP_INCL_CPU)) - { - return SW_BAD_PARAM; - } - - status = 0; - for (i = 0; i < SW_MAX_NR_PORT; i++) - { - if ((entry->port.map) & (0x1UL << i)) - { - if (status) - { - return SW_BAD_PARAM; - } - port = i; - status = 1; - } - } - } - SW_SET_REG_BY_FIELD(ADDR_TABLE_FUNC3, AT_PORT_NUM, port, reg[3]); - } - - if (A_TRUE == option->fid_en) - { - SW_SET_REG_BY_FIELD(ADDR_TABLE_FUNC3, AT_VID_EN, 1, reg[3]); - } - - if (A_TRUE == option->multicast_en) - { - SW_SET_REG_BY_FIELD(ADDR_TABLE_FUNC3, AT_MULTI_EN, 1, reg[3]); - } - - if (FAL_SVL_FID == entry->fid) - { - SW_SET_REG_BY_FIELD(ADDR_TABLE_FUNC2, AT_VID, 0, reg[2]); - SW_SET_REG_BY_FIELD(ADDR_TABLE_FUNC1, AT_SVL_EN, 1, reg[1]); - } - else if (ISIS_MAX_FID >= entry->fid) - { - SW_SET_REG_BY_FIELD(ADDR_TABLE_FUNC2, AT_VID, entry->fid, reg[2]); - SW_SET_REG_BY_FIELD(ADDR_TABLE_FUNC1, AT_SVL_EN, 0, reg[1]); - } - else - { - return SW_BAD_PARAM; - } - - if (ARL_FIRST_ENTRY != hwop) - { - SW_SET_REG_BY_FIELD(ADDR_TABLE_FUNC2, AT_STATUS, 0xf, reg[2]); - } - - _isis_fdb_fill_addr(entry->addr, ®[0], ®[1]); - - rv = _isis_atu_down_to_hw(dev_id, reg); - SW_RTN_ON_ERROR(rv); - - rv = _isis_fdb_commit(dev_id, hwop); - SW_RTN_ON_ERROR(rv); - - rv = _isis_atu_up_to_sw(dev_id, reg); - SW_RTN_ON_ERROR(rv); - - _isis_atu_hw_to_sw(reg, entry); - - SW_GET_FIELD_BY_REG(ADDR_TABLE_FUNC2, AT_STATUS, status, reg[2]); - if ((A_TRUE == _isis_fdb_is_zeroaddr(entry->addr)) - && (0 == status)) - { - if (ARL_NEXT_ENTRY == hwop) - { - return SW_NO_MORE; - } - else - { - return SW_NOT_FOUND; - } - } - else - { - return SW_OK; - } - - return SW_OK; -} - -static sw_error_t -_isis_fdb_add(a_uint32_t dev_id, const fal_fdb_entry_t * entry) -{ - sw_error_t rv; - a_uint32_t reg[4] = { 0 }; - - HSL_DEV_ID_CHECK(dev_id); - - rv = _isis_atu_sw_to_hw(dev_id, entry, reg); - SW_RTN_ON_ERROR(rv); - - rv = _isis_atu_down_to_hw(dev_id, reg); - SW_RTN_ON_ERROR(rv); - - rv = _isis_fdb_commit(dev_id, ARL_LOAD_ENTRY); - return rv; -} - -static sw_error_t -_isis_fdb_del_all(a_uint32_t dev_id, a_uint32_t flag) -{ - sw_error_t rv; - - HSL_DEV_ID_CHECK(dev_id); - - if (FAL_FDB_DEL_STATIC & flag) - { - rv = _isis_fdb_commit(dev_id, ARL_FLUSH_ALL); - } - else - { - rv = _isis_fdb_commit(dev_id, ARL_FLUSH_ALL_UNLOCK); - } - - return rv; -} - -static sw_error_t -_isis_fdb_del_by_port(a_uint32_t dev_id, fal_port_t port_id, a_uint32_t flag) -{ - sw_error_t rv; - a_uint32_t reg = 0; - - HSL_DEV_ID_CHECK(dev_id); - - if (A_FALSE == hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU)) - { - return SW_BAD_PARAM; - } - - SW_SET_REG_BY_FIELD(ADDR_TABLE_FUNC3, AT_PORT_NUM, port_id, reg); - - HSL_REG_ENTRY_SET(rv, dev_id, ADDR_TABLE_FUNC3, 0, (a_uint8_t *) (®), - sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - - if (FAL_FDB_DEL_STATIC & flag) - { - rv = _isis_fdb_commit(dev_id, ARL_FLUSH_PORT_AND_STATIC); - } - else - { - rv = _isis_fdb_commit(dev_id, ARL_FLUSH_PORT_NO_STATIC); - } - - return rv; -} - -static sw_error_t -_isis_fdb_del_by_mac(a_uint32_t dev_id, const fal_fdb_entry_t * entry) -{ - sw_error_t rv; - a_uint32_t reg0 = 0, reg1 = 0, reg2 = 0; - - HSL_DEV_ID_CHECK(dev_id); - - _isis_fdb_fill_addr(entry->addr, ®0, ®1); - - if (FAL_SVL_FID == entry->fid) - { - SW_SET_REG_BY_FIELD(ADDR_TABLE_FUNC2, AT_VID, 0, reg2); - SW_SET_REG_BY_FIELD(ADDR_TABLE_FUNC1, AT_SVL_EN, 1, reg1); - } - else if (ISIS_MAX_FID >= entry->fid) - { - SW_SET_REG_BY_FIELD(ADDR_TABLE_FUNC2, AT_VID, (entry->fid), reg2); - SW_SET_REG_BY_FIELD(ADDR_TABLE_FUNC1, AT_SVL_EN, 0, reg1); - } - else - { - return SW_BAD_PARAM; - } - - HSL_REG_ENTRY_SET(rv, dev_id, ADDR_TABLE_FUNC2, 0, (a_uint8_t *) (®2), - sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - - HSL_REG_ENTRY_SET(rv, dev_id, ADDR_TABLE_FUNC1, 0, (a_uint8_t *) (®1), - sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - - HSL_REG_ENTRY_SET(rv, dev_id, ADDR_TABLE_FUNC0, 0, (a_uint8_t *) (®0), - sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - - rv = _isis_fdb_commit(dev_id, ARL_PURGE_ENTRY); - return rv; -} - -static sw_error_t -_isis_fdb_find(a_uint32_t dev_id, fal_fdb_entry_t * entry) -{ - sw_error_t rv; - fal_fdb_op_t option; - - aos_mem_zero(&option, sizeof (fal_fdb_op_t)); - rv = _isis_fdb_get(dev_id, &option, entry, ARL_FIND_ENTRY); - return rv; -} - -static sw_error_t -_isis_fdb_extend_next(a_uint32_t dev_id, fal_fdb_op_t * option, - fal_fdb_entry_t * entry) -{ - sw_error_t rv; - - rv = _isis_fdb_get(dev_id, option, entry, ARL_NEXT_ENTRY); - return rv; -} - -static sw_error_t -_isis_fdb_extend_first(a_uint32_t dev_id, fal_fdb_op_t * option, - fal_fdb_entry_t * entry) -{ - sw_error_t rv; - - rv = _isis_fdb_get(dev_id, option, entry, ARL_FIRST_ENTRY); - return rv; -} - -static sw_error_t -_isis_fdb_transfer(a_uint32_t dev_id, fal_port_t old_port, fal_port_t new_port, - a_uint32_t fid, fal_fdb_op_t * option) -{ - sw_error_t rv; - a_uint32_t reg[4] = { 0 }; - - if (A_TRUE == option->port_en) - { - return SW_NOT_SUPPORTED; - } - - if (A_TRUE == option->fid_en) - { - SW_SET_REG_BY_FIELD(ADDR_TABLE_FUNC3, AT_VID_EN, 1, reg[3]); - } - - if (A_TRUE == option->multicast_en) - { - SW_SET_REG_BY_FIELD(ADDR_TABLE_FUNC3, AT_MULTI_EN, 1, reg[3]); - } - - if (FAL_SVL_FID == fid) - { - SW_SET_REG_BY_FIELD(ADDR_TABLE_FUNC2, AT_VID, 0, reg[2]); - SW_SET_REG_BY_FIELD(ADDR_TABLE_FUNC1, AT_SVL_EN, 1, reg[1]); - } - else if (ISIS_MAX_FID >= fid) - { - SW_SET_REG_BY_FIELD(ADDR_TABLE_FUNC2, AT_VID, fid, reg[2]); - SW_SET_REG_BY_FIELD(ADDR_TABLE_FUNC1, AT_SVL_EN, 0, reg[1]); - } - else - { - return SW_BAD_PARAM; - } - - SW_SET_REG_BY_FIELD(ADDR_TABLE_FUNC3, AT_PORT_NUM, old_port, reg[3]); - SW_SET_REG_BY_FIELD(ADDR_TABLE_FUNC3, NEW_PORT_NUM, new_port, reg[3]); - - rv = _isis_atu_down_to_hw(dev_id, reg); - SW_RTN_ON_ERROR(rv); - - rv = _isis_fdb_commit(dev_id, ARL_TRANSFER_ENTRY); - return rv; -} - -static sw_error_t -_isis_fdb_port_learn_set(a_uint32_t dev_id, fal_port_t port_id, a_bool_t enable) -{ - a_uint32_t data; - sw_error_t rv; - - HSL_DEV_ID_CHECK(dev_id); - - if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU)) - { - return SW_BAD_PARAM; - } - - if (A_TRUE == enable) - { - data = 1; - } - else if (A_FALSE == enable) - { - data = 0; - } - else - { - return SW_BAD_PARAM; - } - - HSL_REG_FIELD_SET(rv, dev_id, PORT_LOOKUP_CTL, port_id, LEARN_EN, - (a_uint8_t *) (&data), sizeof (a_uint32_t)); - return rv; -} - -static sw_error_t -_isis_fdb_port_learn_get(a_uint32_t dev_id, fal_port_t port_id, - a_bool_t * enable) -{ - a_uint32_t data = 0; - sw_error_t rv; - - HSL_DEV_ID_CHECK(dev_id); - - if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU)) - { - return SW_BAD_PARAM; - } - - HSL_REG_FIELD_GET(rv, dev_id, PORT_LOOKUP_CTL, port_id, LEARN_EN, - (a_uint8_t *) (&data), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - - if (1 == data) - { - *enable = A_TRUE; - } - else - { - *enable = A_FALSE; - } - - return SW_OK; -} - -static sw_error_t -_isis_fdb_age_ctrl_set(a_uint32_t dev_id, a_bool_t enable) -{ - a_uint32_t data; - sw_error_t rv; - - HSL_DEV_ID_CHECK(dev_id); - - if (A_TRUE == enable) - { - data = 1; - } - else if (A_FALSE == enable) - { - data = 0; - } - else - { - return SW_BAD_PARAM; - } - - HSL_REG_FIELD_SET(rv, dev_id, ADDR_TABLE_CTL, 0, AGE_EN, - (a_uint8_t *) (&data), sizeof (a_uint32_t)); - return rv; -} - -static sw_error_t -_isis_fdb_age_ctrl_get(a_uint32_t dev_id, a_bool_t * enable) -{ - a_uint32_t data = 0; - sw_error_t rv; - - HSL_DEV_ID_CHECK(dev_id); - - HSL_REG_FIELD_GET(rv, dev_id, ADDR_TABLE_CTL, 0, AGE_EN, - (a_uint8_t *) (&data), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - - if (1 == data) - { - *enable = A_TRUE; - } - else - { - *enable = A_FALSE; - } - - return SW_OK; -} - -static sw_error_t -_isis_fdb_age_time_set(a_uint32_t dev_id, a_uint32_t * time) -{ - a_uint32_t data; - sw_error_t rv; - - HSL_DEV_ID_CHECK(dev_id); - - if ((65535 * 7 < *time) || (7 > *time)) - { - return SW_BAD_PARAM; - } - data = *time / 7; - *time = data * 7; - HSL_REG_FIELD_SET(rv, dev_id, ADDR_TABLE_CTL, 0, AGE_TIME, - (a_uint8_t *) (&data), sizeof (a_uint32_t)); - return rv; -} - -static sw_error_t -_isis_fdb_age_time_get(a_uint32_t dev_id, a_uint32_t * time) -{ - a_uint32_t data = 0; - sw_error_t rv; - - HSL_DEV_ID_CHECK(dev_id); - - HSL_REG_FIELD_GET(rv, dev_id, ADDR_TABLE_CTL, 0, AGE_TIME, - (a_uint8_t *) (&data), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - - *time = data * 7; - return SW_OK; -} - -static sw_error_t -_isis_port_fdb_learn_limit_set(a_uint32_t dev_id, fal_port_t port_id, - a_bool_t enable, a_uint32_t cnt) -{ - sw_error_t rv; - a_uint32_t reg = 0; - - HSL_DEV_ID_CHECK(dev_id); - - if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU)) - { - return SW_BAD_PARAM; - } - - HSL_REG_ENTRY_GET(rv, dev_id, PORT_LEARN_LIMIT_CTL, port_id, - (a_uint8_t *) (®), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - - if (A_TRUE == enable) - { - if (ISIS_MAX_PORT_LEARN_LIMIT_CNT < cnt) - { - return SW_BAD_PARAM; - } - SW_SET_REG_BY_FIELD(PORT_LEARN_LIMIT_CTL, SA_LEARN_LIMIT_EN, 1, reg); - SW_SET_REG_BY_FIELD(PORT_LEARN_LIMIT_CTL, SA_LEARN_CNT, cnt, reg); - } - else if (A_FALSE == enable) - { - SW_SET_REG_BY_FIELD(PORT_LEARN_LIMIT_CTL, SA_LEARN_LIMIT_EN, 0, reg); - SW_SET_REG_BY_FIELD(PORT_LEARN_LIMIT_CTL, SA_LEARN_CNT, 0, reg); - } - else - { - return SW_BAD_PARAM; - } - - HSL_REG_ENTRY_SET(rv, dev_id, PORT_LEARN_LIMIT_CTL, port_id, - (a_uint8_t *) (®), sizeof (a_uint32_t)); - return rv; -} - -static sw_error_t -_isis_port_fdb_learn_limit_get(a_uint32_t dev_id, fal_port_t port_id, - a_bool_t * enable, a_uint32_t * cnt) -{ - sw_error_t rv; - a_uint32_t data, reg = 0; - - HSL_DEV_ID_CHECK(dev_id); - - if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU)) - { - return SW_BAD_PARAM; - } - - HSL_REG_ENTRY_GET(rv, dev_id, PORT_LEARN_LIMIT_CTL, port_id, - (a_uint8_t *) (®), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - - SW_GET_FIELD_BY_REG(PORT_LEARN_LIMIT_CTL, SA_LEARN_LIMIT_EN, data, reg); - if (data) - { - SW_GET_FIELD_BY_REG(PORT_LEARN_LIMIT_CTL, SA_LEARN_CNT, data, reg); - *enable = A_TRUE; - *cnt = data; - } - else - { - *enable = A_FALSE; - *cnt = 0; - } - - return SW_OK; -} - -static sw_error_t -_isis_port_fdb_learn_exceed_cmd_set(a_uint32_t dev_id, fal_port_t port_id, - fal_fwd_cmd_t cmd) -{ - sw_error_t rv; - a_uint32_t data = 0; - - HSL_DEV_ID_CHECK(dev_id); - - if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU)) - { - return SW_BAD_PARAM; - } - - if (FAL_MAC_DROP == cmd) - { - data = 1; - } - else if (FAL_MAC_RDT_TO_CPU == cmd) - { - data = 0; - } - else - { - return SW_NOT_SUPPORTED; - } - - HSL_REG_FIELD_SET(rv, dev_id, PORT_LEARN_LIMIT_CTL, port_id, - SA_LEARN_LIMIT_DROP_EN, (a_uint8_t *) (&data), - sizeof (a_uint32_t)); - return rv; -} - -static sw_error_t -_isis_port_fdb_learn_exceed_cmd_get(a_uint32_t dev_id, fal_port_t port_id, - fal_fwd_cmd_t * cmd) -{ - sw_error_t rv; - a_uint32_t data = 0; - - HSL_DEV_ID_CHECK(dev_id); - - if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU)) - { - return SW_BAD_PARAM; - } - - HSL_REG_FIELD_GET(rv, dev_id, PORT_LEARN_LIMIT_CTL, port_id, - SA_LEARN_LIMIT_DROP_EN, (a_uint8_t *) (&data), - sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - - if (data) - { - *cmd = FAL_MAC_DROP; - } - else - { - *cmd = FAL_MAC_RDT_TO_CPU; - } - - return SW_OK; -} - -static sw_error_t -_isis_fdb_learn_limit_set(a_uint32_t dev_id, a_bool_t enable, a_uint32_t cnt) -{ - sw_error_t rv; - a_uint32_t reg = 0; - - HSL_REG_ENTRY_GET(rv, dev_id, GLOBAL_LEARN_LIMIT_CTL, 0, - (a_uint8_t *) (®), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - - if (A_TRUE == enable) - { - if (ISIS_MAX_LEARN_LIMIT_CNT < cnt) - { - return SW_BAD_PARAM; - } - SW_SET_REG_BY_FIELD(GLOBAL_LEARN_LIMIT_CTL, GOL_SA_LEARN_LIMIT_EN, 1, - reg); - SW_SET_REG_BY_FIELD(GLOBAL_LEARN_LIMIT_CTL, GOL_SA_LEARN_CNT, cnt, reg); - } - else if (A_FALSE == enable) - { - SW_SET_REG_BY_FIELD(GLOBAL_LEARN_LIMIT_CTL, GOL_SA_LEARN_LIMIT_EN, 0, - reg); - SW_SET_REG_BY_FIELD(GLOBAL_LEARN_LIMIT_CTL, GOL_SA_LEARN_CNT, 0, reg); - } - else - { - return SW_BAD_PARAM; - } - - HSL_REG_ENTRY_SET(rv, dev_id, GLOBAL_LEARN_LIMIT_CTL, 0, - (a_uint8_t *) (®), sizeof (a_uint32_t)); - return rv; -} - -static sw_error_t -_isis_fdb_learn_limit_get(a_uint32_t dev_id, a_bool_t * enable, - a_uint32_t * cnt) -{ - sw_error_t rv; - a_uint32_t data, reg = 0; - - HSL_REG_ENTRY_GET(rv, dev_id, GLOBAL_LEARN_LIMIT_CTL, 0, - (a_uint8_t *) (®), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - - SW_GET_FIELD_BY_REG(GLOBAL_LEARN_LIMIT_CTL, GOL_SA_LEARN_LIMIT_EN, data, - reg); - if (data) - { - SW_GET_FIELD_BY_REG(GLOBAL_LEARN_LIMIT_CTL, GOL_SA_LEARN_CNT, data, - reg); - *enable = A_TRUE; - *cnt = data; - } - else - { - *enable = A_FALSE; - *cnt = 0; - } - - return SW_OK; -} - -static sw_error_t -_isis_fdb_learn_exceed_cmd_set(a_uint32_t dev_id, fal_fwd_cmd_t cmd) -{ - sw_error_t rv; - a_uint32_t data = 0; - - HSL_DEV_ID_CHECK(dev_id); - - if (FAL_MAC_DROP == cmd) - { - data = 1; - } - else if (FAL_MAC_RDT_TO_CPU == cmd) - { - data = 0; - } - else - { - return SW_NOT_SUPPORTED; - } - - HSL_REG_FIELD_SET(rv, dev_id, GLOBAL_LEARN_LIMIT_CTL, 0, - GOL_SA_LEARN_LIMIT_DROP_EN, (a_uint8_t *) (&data), - sizeof (a_uint32_t)); - return rv; -} - -static sw_error_t -_isis_fdb_learn_exceed_cmd_get(a_uint32_t dev_id, fal_fwd_cmd_t * cmd) -{ - sw_error_t rv; - a_uint32_t data = 0; - - HSL_DEV_ID_CHECK(dev_id); - - HSL_REG_FIELD_GET(rv, dev_id, GLOBAL_LEARN_LIMIT_CTL, 0, - GOL_SA_LEARN_LIMIT_DROP_EN, (a_uint8_t *) (&data), - sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - - if (data) - { - *cmd = FAL_MAC_DROP; - } - else - { - *cmd = FAL_MAC_RDT_TO_CPU; - } - - return SW_OK; -} - -#define ISIS_RESV_ADDR_NUM 32 -#define RESV_ADDR_TBL0_ADDR 0x3c000 -#define RESV_ADDR_TBL1_ADDR 0x3c004 -#define RESV_ADDR_TBL2_ADDR 0x3c008 - -static void -_isis_resv_addr_parse(const a_uint32_t reg[], fal_mac_addr_t * addr) -{ - a_uint32_t i; - - for (i = 2; i < 6; i++) - { - addr->uc[i] = (reg[0] >> ((5 - i) << 3)) & 0xff; - } - - for (i = 0; i < 2; i++) - { - addr->uc[i] = (reg[1] >> ((1 - i) << 3)) & 0xff; - } -} - -static sw_error_t -_isis_resv_atu_sw_to_hw(a_uint32_t dev_id, fal_fdb_entry_t * entry, - a_uint32_t reg[]) -{ - a_uint32_t port; - - if (A_FALSE == entry->portmap_en) - { - if (A_TRUE != - hsl_port_prop_check(dev_id, entry->port.id, HSL_PP_INCL_CPU)) - { - return SW_BAD_PARAM; - } - port = 0x1UL << entry->port.id; - } - else - { - if (A_FALSE == - hsl_mports_prop_check(dev_id, entry->port.map, HSL_PP_INCL_CPU)) - { - return SW_BAD_PARAM; - } - port = entry->port.map; - } - SW_SET_REG_BY_FIELD(RESV_ADDR_TBL1, RESV_DES_PORT, port, reg[1]); - - if (FAL_MAC_CPY_TO_CPU == entry->dacmd) - { - SW_SET_REG_BY_FIELD(RESV_ADDR_TBL1, RESV_COPY_TO_CPU, 1, reg[1]); - } - else if (FAL_MAC_RDT_TO_CPU == entry->dacmd) - { - SW_SET_REG_BY_FIELD(RESV_ADDR_TBL1, RESV_REDRCT_TO_CPU, 1, reg[1]); - } - else if (FAL_MAC_FRWRD != entry->dacmd) - { - return SW_NOT_SUPPORTED; - } - - if (FAL_MAC_FRWRD != entry->sacmd) - { - return SW_NOT_SUPPORTED; - } - - if (A_TRUE == entry->leaky_en) - { - SW_SET_REG_BY_FIELD(RESV_ADDR_TBL1, RESV_LEAKY_EN, 1, reg[1]); - } - else - { - SW_SET_REG_BY_FIELD(RESV_ADDR_TBL1, RESV_LEAKY_EN, 0, reg[1]); - } - - if (A_TRUE != entry->static_en) - { - return SW_NOT_SUPPORTED; - } - SW_SET_REG_BY_FIELD(RESV_ADDR_TBL2, RESV_STATUS, 1, reg[2]); - - if (A_TRUE == entry->mirror_en) - { - SW_SET_REG_BY_FIELD(RESV_ADDR_TBL1, RESV_MIRROR_EN, 1, reg[1]); - } - - if (A_TRUE == entry->cross_pt_state) - { - SW_SET_REG_BY_FIELD(RESV_ADDR_TBL1, RESV_CROSS_PT, 1, reg[1]); - } - - if (A_TRUE == entry->da_pri_en) - { - SW_SET_REG_BY_FIELD(RESV_ADDR_TBL1, RESV_PRI_EN, 1, reg[1]); - SW_SET_REG_BY_FIELD(RESV_ADDR_TBL1, RESV_PRI, (entry->da_queue & 0x7), - reg[1]); - } - - _isis_fdb_fill_addr(entry->addr, ®[0], ®[1]); - return SW_OK; -} - -static void -_isis_resv_atu_hw_to_sw(const a_uint32_t reg[], fal_fdb_entry_t * entry) -{ - a_uint32_t data; - - aos_mem_zero(entry, sizeof (fal_fdb_entry_t)); - - entry->fid = FAL_SVL_FID; - - entry->dacmd = FAL_MAC_FRWRD; - SW_GET_FIELD_BY_REG(RESV_ADDR_TBL1, RESV_COPY_TO_CPU, data, reg[1]); - if (1 == data) - { - entry->dacmd = FAL_MAC_CPY_TO_CPU; - } - - SW_GET_FIELD_BY_REG(RESV_ADDR_TBL1, RESV_REDRCT_TO_CPU, data, reg[1]); - if (1 == data) - { - entry->dacmd = FAL_MAC_RDT_TO_CPU; - } - - entry->sacmd = FAL_MAC_FRWRD; - - entry->leaky_en = A_FALSE; - SW_GET_FIELD_BY_REG(RESV_ADDR_TBL1, RESV_LEAKY_EN, data, reg[1]); - if (1 == data) - { - entry->leaky_en = A_TRUE; - } - - entry->static_en = A_TRUE; - - entry->mirror_en = A_FALSE; - SW_GET_FIELD_BY_REG(RESV_ADDR_TBL1, RESV_MIRROR_EN, data, reg[1]); - if (1 == data) - { - entry->mirror_en = A_TRUE; - } - - entry->da_pri_en = A_FALSE; - SW_GET_FIELD_BY_REG(RESV_ADDR_TBL1, RESV_PRI_EN, data, reg[1]); - if (1 == data) - { - SW_GET_FIELD_BY_REG(RESV_ADDR_TBL1, RESV_PRI, data, reg[1]); - entry->da_pri_en = A_TRUE; - entry->da_queue = data & 0x7; - } - - entry->cross_pt_state = A_FALSE; - SW_GET_FIELD_BY_REG(RESV_ADDR_TBL1, RESV_CROSS_PT, data, reg[1]); - if (1 == data) - { - entry->cross_pt_state = A_TRUE; - } - - SW_GET_FIELD_BY_REG(RESV_ADDR_TBL1, RESV_DES_PORT, data, reg[1]); - entry->portmap_en = A_TRUE; - entry->port.map = data; - - _isis_resv_addr_parse(reg, &(entry->addr)); - return; -} - -static sw_error_t -_isis_fdb_resv_commit(a_uint32_t dev_id, fal_fdb_entry_t * entry, a_uint32_t op, - a_uint32_t * empty) -{ - a_uint32_t index, addr, data, tbl[3] = { 0 }; - sw_error_t rv; - fal_mac_addr_t mac_tmp; - - *empty = ISIS_RESV_ADDR_NUM; - for (index = 0; index < ISIS_RESV_ADDR_NUM; index++) - { - addr = RESV_ADDR_TBL2_ADDR + (index << 4); - HSL_REG_ENTRY_GEN_GET(rv, dev_id, addr, sizeof (a_uint32_t), - (a_uint8_t *) (&(tbl[2])), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - - SW_GET_FIELD_BY_REG(RESV_ADDR_TBL2, RESV_STATUS, data, tbl[2]); - if (data) - { - addr = RESV_ADDR_TBL0_ADDR + (index << 4); - HSL_REG_ENTRY_GEN_GET(rv, dev_id, addr, sizeof (a_uint32_t), - (a_uint8_t *) (&(tbl[0])), - sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - - addr = RESV_ADDR_TBL1_ADDR + (index << 4); - HSL_REG_ENTRY_GEN_GET(rv, dev_id, addr, sizeof (a_uint32_t), - (a_uint8_t *) (&(tbl[1])), - sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - - _isis_resv_addr_parse(tbl, &mac_tmp); - if (!aos_mem_cmp - ((void *) &(entry->addr), (void *) &mac_tmp, - sizeof (fal_mac_addr_t))) - { - if (ARL_PURGE_ENTRY == op) - { - addr = RESV_ADDR_TBL2_ADDR + (index << 4); - tbl[2] = 0; - HSL_REG_ENTRY_GEN_SET(rv, dev_id, addr, sizeof (a_uint32_t), - (a_uint8_t *) (&(tbl[2])), - sizeof (a_uint32_t)); - return rv; - } - else if (ARL_LOAD_ENTRY == op) - { - return SW_ALREADY_EXIST; - } - else if (ARL_FIND_ENTRY == op) - { - _isis_resv_atu_hw_to_sw(tbl, entry); - return SW_OK; - } - } - } - else - { - *empty = index; - } - } - - return SW_NOT_FOUND; -} - -static sw_error_t -_isis_fdb_resv_add(a_uint32_t dev_id, fal_fdb_entry_t * entry) -{ - sw_error_t rv; - a_uint32_t i, empty, addr, tbl[3] = { 0 }; - - rv = _isis_resv_atu_sw_to_hw(dev_id, entry, tbl); - SW_RTN_ON_ERROR(rv); - - rv = _isis_fdb_resv_commit(dev_id, entry, ARL_LOAD_ENTRY, &empty); - if (SW_ALREADY_EXIST == rv) - { - return rv; - } - - if (ISIS_RESV_ADDR_NUM == empty) - { - return SW_NO_RESOURCE; - } - - for (i = 0; i < 3; i++) - { - addr = RESV_ADDR_TBL0_ADDR + (empty << 4) + (i << 2); - HSL_REG_ENTRY_GEN_SET(rv, dev_id, addr, sizeof (a_uint32_t), - (a_uint8_t *) (&(tbl[i])), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - } - - return SW_OK; -} - -static sw_error_t -_isis_fdb_resv_del(a_uint32_t dev_id, fal_fdb_entry_t * entry) -{ - sw_error_t rv; - a_uint32_t empty; - - rv = _isis_fdb_resv_commit(dev_id, entry, ARL_PURGE_ENTRY, &empty); - return rv; -} - -static sw_error_t -_isis_fdb_resv_find(a_uint32_t dev_id, fal_fdb_entry_t * entry) -{ - sw_error_t rv; - a_uint32_t empty; - - rv = _isis_fdb_resv_commit(dev_id, entry, ARL_FIND_ENTRY, &empty); - return rv; -} - -static sw_error_t -_isis_fdb_resv_iterate(a_uint32_t dev_id, a_uint32_t * iterator, - fal_fdb_entry_t * entry) -{ - a_uint32_t index, addr, data, tbl[3] = { 0 }; - sw_error_t rv; - - if ((NULL == iterator) || (NULL == entry)) - { - return SW_BAD_PTR; - } - - if (ISIS_RESV_ADDR_NUM < *iterator) - { - return SW_BAD_PARAM; - } - - for (index = *iterator; index < ISIS_RESV_ADDR_NUM; index++) - { - addr = RESV_ADDR_TBL2_ADDR + (index << 4); - HSL_REG_ENTRY_GEN_GET(rv, dev_id, addr, sizeof (a_uint32_t), - (a_uint8_t *) (&(tbl[2])), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - - SW_GET_FIELD_BY_REG(RESV_ADDR_TBL2, RESV_STATUS, data, tbl[2]); - if (data) - { - addr = RESV_ADDR_TBL0_ADDR + (index << 4); - HSL_REG_ENTRY_GEN_GET(rv, dev_id, addr, sizeof (a_uint32_t), - (a_uint8_t *) (&(tbl[0])), - sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - - addr = RESV_ADDR_TBL1_ADDR + (index << 4); - HSL_REG_ENTRY_GEN_GET(rv, dev_id, addr, sizeof (a_uint32_t), - (a_uint8_t *) (&(tbl[1])), - sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - - _isis_resv_atu_hw_to_sw(tbl, entry); - break; - } - } - - if (ISIS_RESV_ADDR_NUM == index) - { - return SW_NO_MORE; - } - - *iterator = index + 1; - return SW_OK; -} - -static sw_error_t -_isis_fdb_port_learn_static_set(a_uint32_t dev_id, fal_port_t port_id, - a_bool_t enable) -{ - a_uint32_t data; - sw_error_t rv; - - HSL_DEV_ID_CHECK(dev_id); - - if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU)) - { - return SW_BAD_PARAM; - } - - if (A_TRUE == enable) - { - data = 0xf; - } - else if (A_FALSE == enable) - { - data = 0x7; - } - else - { - return SW_BAD_PARAM; - } - - HSL_REG_FIELD_SET(rv, dev_id, PORT_LEARN_LIMIT_CTL, port_id, - SA_LEARN_STATUS, (a_uint8_t *) (&data), - sizeof (a_uint32_t)); - return rv; -} - -static sw_error_t -_isis_fdb_port_learn_static_get(a_uint32_t dev_id, fal_port_t port_id, - a_bool_t * enable) -{ - a_uint32_t data = 0; - sw_error_t rv; - - HSL_DEV_ID_CHECK(dev_id); - - if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU)) - { - return SW_BAD_PARAM; - } - - HSL_REG_FIELD_GET(rv, dev_id, PORT_LEARN_LIMIT_CTL, port_id, - SA_LEARN_STATUS, (a_uint8_t *) (&data), - sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - - if (0xf == data) - { - *enable = A_TRUE; - } - else - { - *enable = A_FALSE; - } - - return SW_OK; -} - -static sw_error_t -_isis_fdb_port_update(a_uint32_t dev_id, a_uint32_t fid, fal_mac_addr_t * addr, fal_port_t port_id, a_uint32_t op) -{ - sw_error_t rv; - fal_fdb_entry_t entry; - fal_fdb_op_t option; - a_uint32_t reg, port; - - HSL_DEV_ID_CHECK(dev_id); - - if (FAL_SVL_FID < fid) - { - return SW_BAD_PARAM; - } - - if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU)) - { - return SW_BAD_PARAM; - } - - aos_mem_zero(&option, sizeof(fal_fdb_op_t)); - aos_mem_copy(&(entry.addr), addr, sizeof(fal_mac_addr_t)); - entry.fid = fid & 0xffff; - rv = _isis_fdb_get(dev_id, &option, &entry, ARL_FIND_ENTRY); - SW_RTN_ON_ERROR(rv); - - HSL_REG_ENTRY_GET(rv, dev_id, ADDR_TABLE_FUNC1, 0, - (a_uint8_t *) (®), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - - SW_GET_FIELD_BY_REG(ADDR_TABLE_FUNC1, DES_PORT, port, reg); - if (op) - { - port |= (0x1 << port_id); - } - else - { - port &= (~(0x1 << port_id)); - } - SW_SET_REG_BY_FIELD(ADDR_TABLE_FUNC1, DES_PORT, port, reg); - HSL_REG_ENTRY_SET(rv, dev_id, ADDR_TABLE_FUNC1, 0, - (a_uint8_t *) (®), sizeof (a_uint32_t)); - - rv = _isis_fdb_commit(dev_id, ARL_LOAD_ENTRY); - return rv; -} - -/** - * @brief Add a Fdb entry - * @param[in] dev_id device id - * @param[in] entry fdb entry - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -isis_fdb_add(a_uint32_t dev_id, const fal_fdb_entry_t * entry) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _isis_fdb_add(dev_id, entry); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Delete all Fdb entries - * @details Comments: - * If set FAL_FDB_DEL_STATIC bit in flag which means delete all fdb - * entries otherwise only delete dynamic entries. - * @param[in] dev_id device id - * @param[in] flag delete operation option - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -isis_fdb_del_all(a_uint32_t dev_id, a_uint32_t flag) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _isis_fdb_del_all(dev_id, flag); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Delete Fdb entries on a particular port - * @details Comments: - * If set FAL_FDB_DEL_STATIC bit in flag which means delete all fdb - * entries otherwise only delete dynamic entries. - * @param[in] dev_id device id - * @param[in] port_id port id - * @param[in] flag delete operation option - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -isis_fdb_del_by_port(a_uint32_t dev_id, fal_port_t port_id, a_uint32_t flag) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _isis_fdb_del_by_port(dev_id, port_id, flag); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Delete a particular Fdb entry through mac address - * @details Comments: - * Only addr field in entry is meaning. For IVL learning vid or fid field - * also is meaning. - * @param[in] dev_id device id - * @param[in] entry fdb entry - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -isis_fdb_del_by_mac(a_uint32_t dev_id, const fal_fdb_entry_t * entry) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _isis_fdb_del_by_mac(dev_id, entry); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Find a particular Fdb entry from device through mac address. - * @details Comments: - For input parameter only addr field in entry is meaning. - * @param[in] dev_id device id - * @param[in] entry fdb entry - * @param[out] entry fdb entry - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -isis_fdb_find(a_uint32_t dev_id, fal_fdb_entry_t * entry) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _isis_fdb_find(dev_id, entry); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Get next Fdb entry from a particular device - * @param[in] dev_id device id - * @param[in] option next operation options - * @param[out] entry fdb entry - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -isis_fdb_extend_next(a_uint32_t dev_id, fal_fdb_op_t * option, - fal_fdb_entry_t * entry) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _isis_fdb_extend_next(dev_id, option, entry); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Get first Fdb entry from a particular device - * @param[in] dev_id device id - * @param[in] option first operation options - * @param[out] entry fdb entry - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -isis_fdb_extend_first(a_uint32_t dev_id, fal_fdb_op_t * option, - fal_fdb_entry_t * entry) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _isis_fdb_extend_first(dev_id, option, entry); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Transfer fdb entries port information on a particular device. - * @param[in] dev_id device id - * @param[in] old_port source port id - * @param[in] new_port destination port id - * @param[in] fid filter database id - * @param[in] option transfer operation options - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -isis_fdb_transfer(a_uint32_t dev_id, fal_port_t old_port, fal_port_t new_port, - a_uint32_t fid, fal_fdb_op_t * option) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _isis_fdb_transfer(dev_id, old_port, new_port, fid, option); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Set dynamic address learning status on a particular port. - * @details Comments: - * This operation will enable or disable dynamic address learning - * feature on a particular port. - * @param[in] dev_id device id - * @param[in] port_id port id - * @param[in] enable enable or disable - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -isis_fdb_port_learn_set(a_uint32_t dev_id, fal_port_t port_id, a_bool_t enable) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _isis_fdb_port_learn_set(dev_id, port_id, enable); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Get dynamic address learning status on a particular port. - * @param[in] dev_id device id - * @param[in] port_id port id - * @param[out] enable A_TRUE or A_FALSE - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -isis_fdb_port_learn_get(a_uint32_t dev_id, fal_port_t port_id, - a_bool_t * enable) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _isis_fdb_port_learn_get(dev_id, port_id, enable); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Set dynamic address aging status on particular device. - * @details Comments: - * This operation will enable or disable dynamic address aging - * feature on particular device. - * @param[in] dev_id device id - * @param[in] enable enable or disable - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -isis_fdb_age_ctrl_set(a_uint32_t dev_id, a_bool_t enable) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _isis_fdb_age_ctrl_set(dev_id, enable); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Get dynamic address aging status on particular device. - * @param[in] dev_id device id - * @param[in] enable enable or disable - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -isis_fdb_age_ctrl_get(a_uint32_t dev_id, a_bool_t * enable) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _isis_fdb_age_ctrl_get(dev_id, enable); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Set dynamic address aging time on a particular device. - * @details Comments: - * This operation will set dynamic address aging time on a particular device. - * The unit of time is second. Because different device has differnet - * hardware granularity function will return actual time in hardware. - * @param[in] dev_id device id - * @param time aging time - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -isis_fdb_age_time_set(a_uint32_t dev_id, a_uint32_t * time) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _isis_fdb_age_time_set(dev_id, time); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Get dynamic address aging time on a particular device. - * @param[in] dev_id device id - * @param[out] time aging time - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -isis_fdb_age_time_get(a_uint32_t dev_id, a_uint32_t * time) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _isis_fdb_age_time_get(dev_id, time); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Set dynamic address learning count limit on a particular port. - * @param[in] dev_id device id - * @param[in] port_id port id - * @param[in] enable A_TRUE or A_FALSE - * @param[in] cnt limit count - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -isis_port_fdb_learn_limit_set(a_uint32_t dev_id, fal_port_t port_id, - a_bool_t enable, a_uint32_t cnt) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _isis_port_fdb_learn_limit_set(dev_id, port_id, enable, cnt); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Get dynamic address learning count limit on a particular port. - * @param[in] dev_id device id - * @param[in] port_id port id - * @param[out] enable A_TRUE or A_FALSE - * @param[out] cnt limit count - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -isis_port_fdb_learn_limit_get(a_uint32_t dev_id, fal_port_t port_id, - a_bool_t * enable, a_uint32_t * cnt) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _isis_port_fdb_learn_limit_get(dev_id, port_id, enable, cnt); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Set dynamic address learning count exceed command on a particular port. - * @param[in] dev_id device id - * @param[in] port_id port id - * @param[in] cmd forwarding command - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -isis_port_fdb_learn_exceed_cmd_set(a_uint32_t dev_id, fal_port_t port_id, - fal_fwd_cmd_t cmd) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _isis_port_fdb_learn_exceed_cmd_set(dev_id, port_id, cmd); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Get dynamic address learning count exceed command on a particular port. - * @param[in] dev_id device id - * @param[in] port_id port id - * @param[out] cmd forwarding command - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -isis_port_fdb_learn_exceed_cmd_get(a_uint32_t dev_id, fal_port_t port_id, - fal_fwd_cmd_t * cmd) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _isis_port_fdb_learn_exceed_cmd_get(dev_id, port_id, cmd); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Set dynamic address learning count limit on a particular device. - * @param[in] dev_id device id - * @param[in] enable A_TRUE or A_FALSE - * @param[in] cnt limit count - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -isis_fdb_learn_limit_set(a_uint32_t dev_id, a_bool_t enable, a_uint32_t cnt) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _isis_fdb_learn_limit_set(dev_id, enable, cnt); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Get dynamic address learning count limit on a particular device. - * @param[in] dev_id device id - * @param[in] enable A_TRUE or A_FALSE - * @param[in] cnt limit count - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -isis_fdb_learn_limit_get(a_uint32_t dev_id, a_bool_t * enable, a_uint32_t * cnt) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _isis_fdb_learn_limit_get(dev_id, enable, cnt); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Set dynamic address learning count exceed command on a particular device. - * @param[in] dev_id device id - * @param[in] cmd forwarding command - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -isis_fdb_learn_exceed_cmd_set(a_uint32_t dev_id, fal_fwd_cmd_t cmd) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _isis_fdb_learn_exceed_cmd_set(dev_id, cmd); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Get dynamic address learning count exceed command on a particular device. - * @param[in] dev_id device id - * @param[out] cmd forwarding command - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -isis_fdb_learn_exceed_cmd_get(a_uint32_t dev_id, fal_fwd_cmd_t * cmd) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _isis_fdb_learn_exceed_cmd_get(dev_id, cmd); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Add a particular reserve Fdb entry - * @param[in] dev_id device id - * @param[in] entry reserve fdb entry - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -isis_fdb_resv_add(a_uint32_t dev_id, fal_fdb_entry_t * entry) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _isis_fdb_resv_add(dev_id, entry); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Delete a particular reserve Fdb entry through mac address - * @param[in] dev_id device id - * @param[in] entry reserve fdb entry - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -isis_fdb_resv_del(a_uint32_t dev_id, fal_fdb_entry_t * entry) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _isis_fdb_resv_del(dev_id, entry); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Find a particular reserve Fdb entry through mac address - * @param[in] dev_id device id - * @param[in] entry reserve fdb entry - * @param[out] entry reserve fdb entry - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -isis_fdb_resv_find(a_uint32_t dev_id, fal_fdb_entry_t * entry) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _isis_fdb_resv_find(dev_id, entry); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Iterate all reserve fdb entries on a particular device. - * @param[in] dev_id device id - * @param[in] iterator reserve fdb entry index if it's zero means get the first entry - * @param[out] iterator next valid fdb entry index - * @param[out] entry reserve fdb entry - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -isis_fdb_resv_iterate(a_uint32_t dev_id, a_uint32_t * iterator, - fal_fdb_entry_t * entry) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _isis_fdb_resv_iterate(dev_id, iterator, entry); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Set the static status of fdb entries which learned by hardware on a particular port. - * @param[in] dev_id device id - * @param[in] port_id port id - * @param[in] enable A_TRUE or A_FALSE - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -isis_fdb_port_learn_static_set(a_uint32_t dev_id, fal_port_t port_id, - a_bool_t enable) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _isis_fdb_port_learn_static_set(dev_id, port_id, enable); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Get the static status of fdb entries which learned by hardware on a particular port. - * @param[in] dev_id device id - * @param[in] port_id port id - * @param[out] enable A_TRUE or A_FALSE - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -isis_fdb_port_learn_static_get(a_uint32_t dev_id, fal_port_t port_id, - a_bool_t * enable) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _isis_fdb_port_learn_static_get(dev_id, port_id, enable); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Add a port to an exsiting entry - * @param[in] dev_id device id - * @param[in] fid filtering database id - * @param[in] addr MAC address - * @param[in] port_id port id - * @return SW_OK or error code, If entry not exist will return error. - */ -HSL_LOCAL sw_error_t -isis_fdb_port_add(a_uint32_t dev_id, a_uint32_t fid, fal_mac_addr_t * addr, fal_port_t port_id) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _isis_fdb_port_update(dev_id, fid, addr, port_id, 1); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Delete a port from an exsiting entry - * @param[in] dev_id device id - * @param[in] fid filtering database id - * @param[in] addr MAC address - * @param[in] port_id port id - * @return SW_OK or error code, If entry not exist will return error. - */ -HSL_LOCAL sw_error_t -isis_fdb_port_del(a_uint32_t dev_id, a_uint32_t fid, fal_mac_addr_t * addr, fal_port_t port_id) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _isis_fdb_port_update(dev_id, fid, addr, port_id, 0); - HSL_API_UNLOCK; - return rv; -} - -sw_error_t -isis_fdb_init(a_uint32_t dev_id) -{ - HSL_DEV_ID_CHECK(dev_id); - -#ifndef HSL_STANDALONG - { - hsl_api_t *p_api; - - SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id)); - - p_api->fdb_add = isis_fdb_add; - p_api->fdb_del_all = isis_fdb_del_all; - p_api->fdb_del_by_port = isis_fdb_del_by_port; - p_api->fdb_del_by_mac = isis_fdb_del_by_mac; - p_api->fdb_extend_first = isis_fdb_extend_first; - p_api->fdb_extend_next = isis_fdb_extend_next; - p_api->fdb_find = isis_fdb_find; - p_api->port_learn_set = isis_fdb_port_learn_set; - p_api->port_learn_get = isis_fdb_port_learn_get; - p_api->age_ctrl_set = isis_fdb_age_ctrl_set; - p_api->age_ctrl_get = isis_fdb_age_ctrl_get; - p_api->age_time_set = isis_fdb_age_time_set; - p_api->age_time_get = isis_fdb_age_time_get; - p_api->fdb_extend_next = isis_fdb_extend_next; - p_api->fdb_extend_first = isis_fdb_extend_first; - p_api->fdb_transfer = isis_fdb_transfer; - p_api->port_fdb_learn_limit_set = isis_port_fdb_learn_limit_set; - p_api->port_fdb_learn_limit_get = isis_port_fdb_learn_limit_get; - p_api->port_fdb_learn_exceed_cmd_set = isis_port_fdb_learn_exceed_cmd_set; - p_api->port_fdb_learn_exceed_cmd_get = isis_port_fdb_learn_exceed_cmd_get; - p_api->fdb_learn_limit_set = isis_fdb_learn_limit_set; - p_api->fdb_learn_limit_get = isis_fdb_learn_limit_get; - p_api->fdb_learn_exceed_cmd_set = isis_fdb_learn_exceed_cmd_set; - p_api->fdb_learn_exceed_cmd_get = isis_fdb_learn_exceed_cmd_get; - p_api->fdb_resv_add = isis_fdb_resv_add; - p_api->fdb_resv_del = isis_fdb_resv_del; - p_api->fdb_resv_find = isis_fdb_resv_find; - p_api->fdb_resv_iterate = isis_fdb_resv_iterate; - p_api->fdb_port_learn_static_set = isis_fdb_port_learn_static_set; - p_api->fdb_port_learn_static_get = isis_fdb_port_learn_static_get; - p_api->fdb_port_add = isis_fdb_port_add; - p_api->fdb_port_del = isis_fdb_port_del; - } -#endif - - return SW_OK; -} - -/** - * @} - */ - diff --git a/feeds/ipq807x/qca-ssdk/src/src/hsl/isis/isis_igmp.c b/feeds/ipq807x/qca-ssdk/src/src/hsl/isis/isis_igmp.c deleted file mode 100755 index 300dd0430..000000000 --- a/feeds/ipq807x/qca-ssdk/src/src/hsl/isis/isis_igmp.c +++ /dev/null @@ -1,1143 +0,0 @@ -/* - * Copyright (c) 2012, 2016, The Linux Foundation. All rights reserved. - * Permission to use, copy, modify, and/or distribute this software for - * any purpose with or without fee is hereby granted, provided that the - * above copyright notice and this permission notice appear in all copies. - * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES - * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR - * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES - * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN - * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT - * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. - */ - - -/** - * @defgroup isis_igmp ISIS_IGMP - * @{ - */ -#include "sw.h" -#include "hsl.h" -#include "hsl_dev.h" -#include "hsl_port_prop.h" -#include "isis_igmp.h" -#include "isis_reg.h" - -#define LEAVE_EN_OFFSET 2 -#define JOIN_EN_OFFSET 1 -#define IGMP_MLD_EN_OFFSET 0 - -#define ISIS_MAX_PORT_LEARN_LIMIT_CNT 1023 - -extern sw_error_t -isis_igmp_sg_entry_set(a_uint32_t dev_id, fal_igmp_sg_entry_t * entry); - -extern sw_error_t -isis_igmp_sg_entry_clear(a_uint32_t dev_id, fal_igmp_sg_entry_t * entry); - -extern sw_error_t -isis_igmp_sg_entry_show(a_uint32_t dev_id); - -static sw_error_t -_isis_port_igmp_property_set(a_uint32_t dev_id, fal_port_t port_id, - a_bool_t enable, a_uint32_t item) -{ - sw_error_t rv; - a_uint32_t reg = 0, val; - - HSL_DEV_ID_CHECK(dev_id); - - if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU)) - { - return SW_BAD_PARAM; - } - - if (A_TRUE == enable) - { - val = 1; - } - else if (A_FALSE == enable) - { - val = 0; - } - else - { - return SW_BAD_PARAM; - } - - if (3 >= port_id) - { - HSL_REG_ENTRY_GET(rv, dev_id, FRAME_ACK_CTL0, 0, - (a_uint8_t *) (®), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - - reg &= ~(0x1UL << ((port_id << 3) + item)); - reg |= (val << ((port_id << 3) + item)); - - HSL_REG_ENTRY_SET(rv, dev_id, FRAME_ACK_CTL0, 0, - (a_uint8_t *) (®), sizeof (a_uint32_t)); - } - else - { - HSL_REG_ENTRY_GET(rv, dev_id, FRAME_ACK_CTL1, 0, - (a_uint8_t *) (®), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - - reg &= ~(0x1UL << (((port_id - 4) << 3) + item)); - reg |= (val << (((port_id - 4) << 3) + item)); - - HSL_REG_ENTRY_SET(rv, dev_id, FRAME_ACK_CTL1, 0, - (a_uint8_t *) (®), sizeof (a_uint32_t)); - } - return rv; -} - -static sw_error_t -_isis_port_igmp_property_get(a_uint32_t dev_id, fal_port_t port_id, - a_bool_t * enable, a_uint32_t item) -{ - sw_error_t rv; - a_uint32_t reg = 0, val; - - HSL_DEV_ID_CHECK(dev_id); - - if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU)) - { - return SW_BAD_PARAM; - } - - if (3 >= port_id) - { - HSL_REG_ENTRY_GET(rv, dev_id, FRAME_ACK_CTL0, 0, - (a_uint8_t *) (®), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - - val = (reg >> ((port_id << 3) + item)) & 0x1UL; - } - else - { - HSL_REG_ENTRY_GET(rv, dev_id, FRAME_ACK_CTL1, 0, - (a_uint8_t *) (®), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - - val = (reg >> (((port_id - 4) << 3) + item)) & 0x1UL; - } - - if (1 == val) - { - *enable = A_TRUE; - } - else - { - *enable = A_FALSE; - } - - return SW_OK; -} - -static sw_error_t -_isis_igmp_mld_cmd_set(a_uint32_t dev_id, fal_fwd_cmd_t cmd) -{ - sw_error_t rv; - a_uint32_t val; - - HSL_DEV_ID_CHECK(dev_id); - - if (FAL_MAC_CPY_TO_CPU == cmd) - { - val = 1; - } - else if (FAL_MAC_RDT_TO_CPU == cmd) - { - val = 0; - } - else - { - return SW_NOT_SUPPORTED; - } - - HSL_REG_FIELD_SET(rv, dev_id, FORWARD_CTL0, 0, IGMP_COPY_EN, - (a_uint8_t *) (&val), sizeof (a_uint32_t)); - return rv; -} - -static sw_error_t -_isis_igmp_mld_cmd_get(a_uint32_t dev_id, fal_fwd_cmd_t * cmd) -{ - sw_error_t rv; - a_uint32_t val = 0; - - HSL_DEV_ID_CHECK(dev_id); - - HSL_REG_FIELD_GET(rv, dev_id, FORWARD_CTL0, 0, IGMP_COPY_EN, - (a_uint8_t *) (&val), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - - if (1 == val) - { - *cmd = FAL_MAC_CPY_TO_CPU; - } - else - { - *cmd = FAL_MAC_RDT_TO_CPU; - } - - return SW_OK; -} - -static sw_error_t -_isis_igmp_mld_rp_set(a_uint32_t dev_id, fal_pbmp_t pts) -{ - sw_error_t rv; - a_uint32_t val; - - HSL_DEV_ID_CHECK(dev_id); - - if (A_FALSE == hsl_mports_validity_check(dev_id, pts)) - { - return SW_BAD_PARAM; - } - val = pts; - HSL_REG_FIELD_SET(rv, dev_id, FORWARD_CTL1, 0, IGMP_DP, - (a_uint8_t *) (&val), sizeof (a_uint32_t)); - return rv; -} - -static sw_error_t -_isis_igmp_mld_rp_get(a_uint32_t dev_id, fal_pbmp_t * pts) -{ - sw_error_t rv; - a_uint32_t val = 0; - - HSL_DEV_ID_CHECK(dev_id); - - HSL_REG_FIELD_GET(rv, dev_id, FORWARD_CTL1, 0, IGMP_DP, - (a_uint8_t *) (&val), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - - *pts = val; - return SW_OK; -} - -static sw_error_t -_isis_igmp_mld_entry_creat_set(a_uint32_t dev_id, a_bool_t enable) -{ - sw_error_t rv; - a_uint32_t val; - - HSL_DEV_ID_CHECK(dev_id); - - if (A_TRUE == enable) - { - val = 1; - } - else if (A_FALSE == enable) - { - val = 0; - } - else - { - return SW_BAD_PARAM; - } - - HSL_REG_FIELD_SET(rv, dev_id, ADDR_TABLE_CTL, 0, IGMP_CREAT_EN, - (a_uint8_t *) (&val), sizeof (a_uint32_t)); - return rv; -} - -static sw_error_t -_isis_igmp_mld_entry_creat_get(a_uint32_t dev_id, a_bool_t * enable) -{ - sw_error_t rv; - a_uint32_t val = 0; - - HSL_DEV_ID_CHECK(dev_id); - - HSL_REG_FIELD_GET(rv, dev_id, ADDR_TABLE_CTL, 0, IGMP_CREAT_EN, - (a_uint8_t *) (&val), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - - if (val) - { - *enable = A_TRUE; - } - else - { - *enable = A_FALSE; - } - - return SW_OK; -} - -static sw_error_t -_isis_igmp_mld_entry_static_set(a_uint32_t dev_id, a_bool_t enable) -{ - sw_error_t rv; - a_uint32_t val; - - HSL_DEV_ID_CHECK(dev_id); - - if (A_TRUE == enable) - { - val = 0xf; - } - else if (A_FALSE == enable) - { - val = 0xe; - } - else - { - return SW_BAD_PARAM; - } - - HSL_REG_FIELD_SET(rv, dev_id, ADDR_TABLE_CTL, 0, IGMP_JOIN_STATIC, - (a_uint8_t *) (&val), sizeof (a_uint32_t)); - return rv; -} - -static sw_error_t -_isis_igmp_mld_entry_static_get(a_uint32_t dev_id, a_bool_t * enable) -{ - sw_error_t rv; - a_uint32_t val = 0; - - HSL_DEV_ID_CHECK(dev_id); - - HSL_REG_FIELD_GET(rv, dev_id, ADDR_TABLE_CTL, 0, IGMP_JOIN_STATIC, - (a_uint8_t *) (&val), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - - if (0xf == val) - { - *enable = A_TRUE; - } - else - { - *enable = A_FALSE; - } - - return SW_OK; -} - -static sw_error_t -_isis_igmp_mld_entry_leaky_set(a_uint32_t dev_id, a_bool_t enable) -{ - sw_error_t rv; - a_uint32_t val; - - HSL_DEV_ID_CHECK(dev_id); - - if (A_TRUE == enable) - { - val = 1; - } - else if (A_FALSE == enable) - { - val = 0; - } - else - { - return SW_BAD_PARAM; - } - - HSL_REG_FIELD_SET(rv, dev_id, ADDR_TABLE_CTL, 0, IGMP_JOIN_LEAKY, - (a_uint8_t *) (&val), sizeof (a_uint32_t)); - return rv; -} - -static sw_error_t -_isis_igmp_mld_entry_leaky_get(a_uint32_t dev_id, a_bool_t * enable) -{ - sw_error_t rv; - a_uint32_t val = 0; - - HSL_DEV_ID_CHECK(dev_id); - - HSL_REG_FIELD_GET(rv, dev_id, ADDR_TABLE_CTL, 0, IGMP_JOIN_LEAKY, - (a_uint8_t *) (&val), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - - if (val) - { - *enable = A_TRUE; - } - else - { - *enable = A_FALSE; - } - - return SW_OK; -} - -static sw_error_t -_isis_igmp_mld_entry_v3_set(a_uint32_t dev_id, a_bool_t enable) -{ - sw_error_t rv; - a_uint32_t val; - - HSL_DEV_ID_CHECK(dev_id); - - if (A_TRUE == enable) - { - val = 1; - } - else if (A_FALSE == enable) - { - val = 0; - } - else - { - return SW_BAD_PARAM; - } - - HSL_REG_FIELD_SET(rv, dev_id, FRAME_ACK_CTL1, 0, IGMP_V3_EN, - (a_uint8_t *) (&val), sizeof (a_uint32_t)); - return rv; -} - -static sw_error_t -_isis_igmp_mld_entry_v3_get(a_uint32_t dev_id, a_bool_t * enable) -{ - sw_error_t rv; - a_uint32_t val = 0; - - HSL_DEV_ID_CHECK(dev_id); - - HSL_REG_FIELD_GET(rv, dev_id, FRAME_ACK_CTL1, 0, IGMP_V3_EN, - (a_uint8_t *) (&val), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - - if (val) - { - *enable = A_TRUE; - } - else - { - *enable = A_FALSE; - } - - return SW_OK; -} - -static sw_error_t -_isis_igmp_mld_entry_queue_set(a_uint32_t dev_id, a_bool_t enable, - a_uint32_t queue) -{ - sw_error_t rv; - a_uint32_t entry = 0; - - HSL_DEV_ID_CHECK(dev_id); - - HSL_REG_ENTRY_GET(rv, dev_id, ADDR_TABLE_CTL, 0, - (a_uint8_t *) (&entry), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - - if (A_TRUE == enable) - { - SW_SET_REG_BY_FIELD(ADDR_TABLE_CTL, IGMP_PRI_EN, 1, entry); - SW_SET_REG_BY_FIELD(ADDR_TABLE_CTL, IGMP_PRI, queue, entry); - } - else if (A_FALSE == enable) - { - SW_SET_REG_BY_FIELD(ADDR_TABLE_CTL, IGMP_PRI_EN, 0, entry); - SW_SET_REG_BY_FIELD(ADDR_TABLE_CTL, IGMP_PRI, 0, entry); - } - else - { - return SW_BAD_PARAM; - } - - HSL_REG_ENTRY_SET(rv, dev_id, ADDR_TABLE_CTL, 0, - (a_uint8_t *) (&entry), sizeof (a_uint32_t)); - return rv; -} - -static sw_error_t -_isis_igmp_mld_entry_queue_get(a_uint32_t dev_id, a_bool_t * enable, - a_uint32_t * queue) -{ - sw_error_t rv; - a_uint32_t entry = 0, data; - - HSL_DEV_ID_CHECK(dev_id); - - HSL_REG_ENTRY_GET(rv, dev_id, ADDR_TABLE_CTL, 0, - (a_uint8_t *) (&entry), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - - SW_GET_FIELD_BY_REG(ADDR_TABLE_CTL, IGMP_PRI_EN, data, entry); - if (data) - { - *enable = A_TRUE; - SW_GET_FIELD_BY_REG(ADDR_TABLE_CTL, IGMP_PRI, data, entry); - *queue = data; - } - else - { - *enable = A_FALSE; - *queue = 0; - } - - return SW_OK; -} - -static sw_error_t -_isis_port_igmp_mld_learn_limit_set(a_uint32_t dev_id, fal_port_t port_id, - a_bool_t enable, a_uint32_t cnt) -{ - sw_error_t rv; - a_uint32_t reg = 0; - - HSL_DEV_ID_CHECK(dev_id); - - if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU)) - { - return SW_BAD_PARAM; - } - - HSL_REG_ENTRY_GET(rv, dev_id, PORT_LEARN_LIMIT_CTL, port_id, - (a_uint8_t *) (®), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - - if (A_TRUE == enable) - { - if (ISIS_MAX_PORT_LEARN_LIMIT_CNT < cnt) - { - return SW_BAD_PARAM; - } - SW_SET_REG_BY_FIELD(PORT_LEARN_LIMIT_CTL, IGMP_JOIN_LIMIT_EN, 1, reg); - SW_SET_REG_BY_FIELD(PORT_LEARN_LIMIT_CTL, IGMP_JOIN_CNT, cnt, reg); - } - else if (A_FALSE == enable) - { - SW_SET_REG_BY_FIELD(PORT_LEARN_LIMIT_CTL, IGMP_JOIN_LIMIT_EN, 0, reg); - SW_SET_REG_BY_FIELD(PORT_LEARN_LIMIT_CTL, IGMP_JOIN_CNT, 0, reg); - } - else - { - return SW_BAD_PARAM; - } - - HSL_REG_ENTRY_SET(rv, dev_id, PORT_LEARN_LIMIT_CTL, port_id, - (a_uint8_t *) (®), sizeof (a_uint32_t)); - return rv; -} - -static sw_error_t -_isis_port_igmp_mld_learn_limit_get(a_uint32_t dev_id, fal_port_t port_id, - a_bool_t * enable, a_uint32_t * cnt) -{ - sw_error_t rv; - a_uint32_t data, reg = 0; - - HSL_DEV_ID_CHECK(dev_id); - - if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU)) - { - return SW_BAD_PARAM; - } - - HSL_REG_ENTRY_GET(rv, dev_id, PORT_LEARN_LIMIT_CTL, port_id, - (a_uint8_t *) (®), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - - SW_GET_FIELD_BY_REG(PORT_LEARN_LIMIT_CTL, IGMP_JOIN_LIMIT_EN, data, reg); - if (data) - { - SW_GET_FIELD_BY_REG(PORT_LEARN_LIMIT_CTL, IGMP_JOIN_CNT, data, reg); - *enable = A_TRUE; - *cnt = data; - } - else - { - *enable = A_FALSE; - *cnt = data; - } - - return SW_OK; -} - -static sw_error_t -_isis_port_igmp_mld_learn_exceed_cmd_set(a_uint32_t dev_id, fal_port_t port_id, - fal_fwd_cmd_t cmd) -{ - sw_error_t rv; - a_uint32_t data = 0; - - HSL_DEV_ID_CHECK(dev_id); - - if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU)) - { - return SW_BAD_PARAM; - } - - if (FAL_MAC_DROP == cmd) - { - data = 1; - } - else if (FAL_MAC_RDT_TO_CPU == cmd) - { - data = 0; - } - else - { - return SW_NOT_SUPPORTED; - } - - HSL_REG_FIELD_SET(rv, dev_id, PORT_LEARN_LIMIT_CTL, port_id, - IGMP_JOIN_LIMIT_DROP_EN, (a_uint8_t *) (&data), - sizeof (a_uint32_t)); - return rv; -} - -static sw_error_t -_isis_port_igmp_mld_learn_exceed_cmd_get(a_uint32_t dev_id, fal_port_t port_id, - fal_fwd_cmd_t * cmd) -{ - sw_error_t rv; - a_uint32_t data = 0; - - HSL_DEV_ID_CHECK(dev_id); - - if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU)) - { - return SW_BAD_PARAM; - } - - HSL_REG_FIELD_GET(rv, dev_id, PORT_LEARN_LIMIT_CTL, port_id, - IGMP_JOIN_LIMIT_DROP_EN, (a_uint8_t *) (&data), - sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - - if (data) - { - *cmd = FAL_MAC_DROP; - } - else - { - *cmd = FAL_MAC_RDT_TO_CPU; - } - - return SW_OK; -} - -/** - * @brief Set igmp/mld packets snooping status on a particular port. - * @details Comments: - * After enabling igmp/mld snooping feature on a particular port all kinds - * igmp/mld packets received on this port would be acknowledged by hardware. - * Particular forwarding decision could be setted by fal_igmp_mld_cmd_set. - * @param[in] dev_id device id - * @param[in] port_id port id - * @param[in] enable A_TRUE or A_FALSE - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -isis_port_igmps_status_set(a_uint32_t dev_id, fal_port_t port_id, - a_bool_t enable) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _isis_port_igmp_property_set(dev_id, port_id, enable, - IGMP_MLD_EN_OFFSET); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Get igmp/mld packets snooping status on particular port. - * @param[in] dev_id device id - * @param[in] port_id port id - * @param[out] enable A_TRUE or A_FALSE - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -isis_port_igmps_status_get(a_uint32_t dev_id, fal_port_t port_id, - a_bool_t * enable) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _isis_port_igmp_property_get(dev_id, port_id, enable, - IGMP_MLD_EN_OFFSET); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Set igmp/mld packets forwarding command on a particular device. - * @details Comments: - * Particular device may only support parts of forwarding commands. - * This operation will take effect only after enabling igmp/mld snooping - * @param[in] dev_id device id - * @param[in] cmd forwarding command - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -isis_igmp_mld_cmd_set(a_uint32_t dev_id, fal_fwd_cmd_t cmd) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _isis_igmp_mld_cmd_set(dev_id, cmd); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Get igmp/mld packets forwarding command on a particular device. - * @param[in] dev_id device id - * @param[out] cmd forwarding command - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -isis_igmp_mld_cmd_get(a_uint32_t dev_id, fal_fwd_cmd_t * cmd) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _isis_igmp_mld_cmd_get(dev_id, cmd); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Set igmp/mld join packets hardware acknowledgement status on particular port. - * @details Comments: - * After enabling igmp/mld join feature on a particular port hardware will - * dynamic learning or changing multicast entry. - * @param[in] dev_id device id - * @param[in] port_id port id - * @param[in] enable A_TRUE or A_FALSE - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -isis_port_igmp_mld_join_set(a_uint32_t dev_id, fal_port_t port_id, - a_bool_t enable) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _isis_port_igmp_property_set(dev_id, port_id, enable, JOIN_EN_OFFSET); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Get igmp/mld join packets hardware acknowledgement status on a particular port. - * @param[in] dev_id device id - * @param[in] port_id port id - * @param[out] enable A_TRUE or A_FALSE - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -isis_port_igmp_mld_join_get(a_uint32_t dev_id, fal_port_t port_id, - a_bool_t * enable) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _isis_port_igmp_property_get(dev_id, port_id, enable, JOIN_EN_OFFSET); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Set igmp/mld leave packets hardware acknowledgement status on a particular port. - * @details Comments: - * After enabling igmp leave feature on a particular port hardware will dynamic - * deleting or changing multicast entry. - * @param[in] dev_id device id - * @param[in] port_id port id - * @param[in] enable A_TRUE or A_FALSE - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -isis_port_igmp_mld_leave_set(a_uint32_t dev_id, fal_port_t port_id, - a_bool_t enable) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _isis_port_igmp_property_set(dev_id, port_id, enable, LEAVE_EN_OFFSET); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Get igmp/mld leave packets hardware acknowledgement status on a particular port. - * @param[in] dev_id device id - * @param[in] port_id port id - * @param[out] enable A_TRUE or A_FALSE - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -isis_port_igmp_mld_leave_get(a_uint32_t dev_id, fal_port_t port_id, - a_bool_t * enable) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _isis_port_igmp_property_get(dev_id, port_id, enable, LEAVE_EN_OFFSET); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Set igmp/mld router ports on a particular device. - * @details Comments: - * After enabling igmp/mld join/leave feature on a particular port igmp/mld - * join/leave packets received on this port will be forwarded to router ports. - * @param[in] dev_id device id - * @param[in] pts dedicates ports - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -isis_igmp_mld_rp_set(a_uint32_t dev_id, fal_pbmp_t pts) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _isis_igmp_mld_rp_set(dev_id, pts); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Get igmp/mld router ports on a particular device. - * @param[in] dev_id device id - * @param[out] pts dedicates ports - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -isis_igmp_mld_rp_get(a_uint32_t dev_id, fal_pbmp_t * pts) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _isis_igmp_mld_rp_get(dev_id, pts); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Set the status of creating multicast entry during igmp/mld join/leave procedure. - * @details Comments: - * After enabling igmp/mld join/leave feature on a particular port if enable - * entry creat hardware will dynamic creat and delete multicast entry, - * otherwise hardware only can change destination ports of existing muticast entry. - * @param[in] dev_id device id - * @param[in] enable A_TRUE or A_FALSE - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -isis_igmp_mld_entry_creat_set(a_uint32_t dev_id, a_bool_t enable) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _isis_igmp_mld_entry_creat_set(dev_id, enable); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Get the status of creating multicast entry during igmp/mld join/leave procedure. - * @param[in] dev_id device id - * @param[out] enable A_TRUE or A_FALSE - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -isis_igmp_mld_entry_creat_get(a_uint32_t dev_id, a_bool_t * enable) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _isis_igmp_mld_entry_creat_get(dev_id, enable); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Set the static status of multicast entry which learned by hardware. - * @details Comments: - * After enabling igmp/mld join/leave feature on a particular port if enable - * static status hardware will not age out multicast entry which leardned by hardware, - * otherwise hardware will age out multicast entry which leardned by hardware. - * @param[in] dev_id device id - * @param[in] enable A_TRUE or A_FALSE - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -isis_igmp_mld_entry_static_set(a_uint32_t dev_id, a_bool_t enable) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _isis_igmp_mld_entry_static_set(dev_id, enable); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Get the static status of multicast entry which learned by hardware. - * @param[in] dev_id device id - * @param[out] enable A_TRUE or A_FALSE - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -isis_igmp_mld_entry_static_get(a_uint32_t dev_id, a_bool_t * enable) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _isis_igmp_mld_entry_static_get(dev_id, enable); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Set the leaky status of multicast entry which learned by hardware. - * @details Comments: - * After enabling igmp/mld join/leave feature on a particular port if enable - * leaky status hardware will set leaky flag of multicast entry which leardned by hardware, - * otherwise hardware will not set leaky flag of multicast entry which leardned by hardware. - * @param[in] dev_id device id - * @param[in] enable A_TRUE or A_FALSE - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -isis_igmp_mld_entry_leaky_set(a_uint32_t dev_id, a_bool_t enable) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _isis_igmp_mld_entry_leaky_set(dev_id, enable); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Get the leaky status of multicast entry which learned by hardware. - * @param[in] dev_id device id - * @param[out] enable A_TRUE or A_FALSE - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -isis_igmp_mld_entry_leaky_get(a_uint32_t dev_id, a_bool_t * enable) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _isis_igmp_mld_entry_leaky_get(dev_id, enable); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Set igmpv3/mldv2 packets hardware acknowledgement status on a particular device. - * @details Comments: - * After enabling igmp join/leave feature on a particular port hardware will dynamic - * creating or changing multicast entry after receiving igmpv3/mldv2 packets. - * @param[in] dev_id device id - * @param[in] enable A_TRUE or A_FALSE - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -isis_igmp_mld_entry_v3_set(a_uint32_t dev_id, a_bool_t enable) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _isis_igmp_mld_entry_v3_set(dev_id, enable); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Get igmpv3/mldv2 packets hardware acknowledgement status on a particular device. - * @param[in] dev_id device id - * @param[out] enable A_TRUE or A_FALSE - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -isis_igmp_mld_entry_v3_get(a_uint32_t dev_id, a_bool_t * enable) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _isis_igmp_mld_entry_v3_get(dev_id, enable); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Set the queue status of multicast entry which learned by hardware. - * @details Comments: - * After enabling igmp/mld join/leave feature on a particular port if enable - * leaky status hardware will set queue flag of multicast entry which leardned by hardware, - * otherwise hardware will not set queue flag of multicast entry which leardned by hardware. - * @param[in] dev_id device id - * @param[in] enable A_TRUE or A_FALSE - * @param[in] queue queue id - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -isis_igmp_mld_entry_queue_set(a_uint32_t dev_id, a_bool_t enable, - a_uint32_t queue) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _isis_igmp_mld_entry_queue_set(dev_id, enable, queue); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Get the queue status of multicast entry which learned by hardware. - * @param[in] dev_id device id - * @param[out] enable A_TRUE or A_FALSE - * @param[out] queue queue id - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -isis_igmp_mld_entry_queue_get(a_uint32_t dev_id, a_bool_t * enable, - a_uint32_t * queue) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _isis_igmp_mld_entry_queue_get(dev_id, enable, queue); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Set IGMP hardware learning count limit on a particular port. - * @param[in] dev_id device id - * @param[in] port_id port id - * @param[in] enable A_TRUE or A_FALSE - * @param[in] cnt limit count - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -isis_port_igmp_mld_learn_limit_set(a_uint32_t dev_id, fal_port_t port_id, - a_bool_t enable, a_uint32_t cnt) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _isis_port_igmp_mld_learn_limit_set(dev_id, port_id, enable, cnt); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Get IGMP hardware learning count limit on a particular port. - * @param[in] dev_id device id - * @param[in] port_id port id - * @param[out] enable A_TRUE or A_FALSE - * @param[out] cnt limit count - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -isis_port_igmp_mld_learn_limit_get(a_uint32_t dev_id, fal_port_t port_id, - a_bool_t * enable, a_uint32_t * cnt) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _isis_port_igmp_mld_learn_limit_get(dev_id, port_id, enable, cnt); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Set IGMP hardware learning count exceed command on a particular port. - * @param[in] dev_id device id - * @param[in] port_id port id - * @param[in] cmd forwarding command - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -isis_port_igmp_mld_learn_exceed_cmd_set(a_uint32_t dev_id, fal_port_t port_id, - fal_fwd_cmd_t cmd) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _isis_port_igmp_mld_learn_exceed_cmd_set(dev_id, port_id, cmd); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Get IGMP hardware learning count exceed command on a particular port. - * @param[in] dev_id device id - * @param[in] port_id port id - * @param[out] cmd forwarding command - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -isis_port_igmp_mld_learn_exceed_cmd_get(a_uint32_t dev_id, fal_port_t port_id, - fal_fwd_cmd_t * cmd) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _isis_port_igmp_mld_learn_exceed_cmd_get(dev_id, port_id, cmd); - HSL_API_UNLOCK; - return rv; -} - -sw_error_t -isis_igmp_init(a_uint32_t dev_id) -{ - HSL_DEV_ID_CHECK(dev_id); - -#ifndef HSL_STANDALONG - { - hsl_api_t *p_api; - - SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id)); - - p_api->port_igmps_status_set = isis_port_igmps_status_set; - p_api->port_igmps_status_get = isis_port_igmps_status_get; - p_api->igmp_mld_cmd_set = isis_igmp_mld_cmd_set; - p_api->igmp_mld_cmd_get = isis_igmp_mld_cmd_get; - p_api->port_igmp_join_set = isis_port_igmp_mld_join_set; - p_api->port_igmp_join_get = isis_port_igmp_mld_join_get; - p_api->port_igmp_leave_set = isis_port_igmp_mld_leave_set; - p_api->port_igmp_leave_get = isis_port_igmp_mld_leave_get; - p_api->igmp_rp_set = isis_igmp_mld_rp_set; - p_api->igmp_rp_get = isis_igmp_mld_rp_get; - p_api->igmp_entry_creat_set = isis_igmp_mld_entry_creat_set; - p_api->igmp_entry_creat_get = isis_igmp_mld_entry_creat_get; - p_api->igmp_entry_static_set = isis_igmp_mld_entry_static_set; - p_api->igmp_entry_static_get = isis_igmp_mld_entry_static_get; - p_api->igmp_entry_leaky_set = isis_igmp_mld_entry_leaky_set; - p_api->igmp_entry_leaky_get = isis_igmp_mld_entry_leaky_get; - p_api->igmp_entry_v3_set = isis_igmp_mld_entry_v3_set; - p_api->igmp_entry_v3_get = isis_igmp_mld_entry_v3_get; - p_api->igmp_entry_queue_set = isis_igmp_mld_entry_queue_set; - p_api->igmp_entry_queue_get = isis_igmp_mld_entry_queue_get; - p_api->port_igmp_mld_learn_limit_set = isis_port_igmp_mld_learn_limit_set; - p_api->port_igmp_mld_learn_limit_get = isis_port_igmp_mld_learn_limit_get; - p_api->port_igmp_mld_learn_exceed_cmd_set = isis_port_igmp_mld_learn_exceed_cmd_set; - p_api->port_igmp_mld_learn_exceed_cmd_get = isis_port_igmp_mld_learn_exceed_cmd_get; - p_api->igmp_sg_entry_set = isis_igmp_sg_entry_set; - p_api->igmp_sg_entry_clear = isis_igmp_sg_entry_clear; - p_api->igmp_sg_entry_show = isis_igmp_sg_entry_show; - } -#endif - - return SW_OK; -} - -/** - * @} - */ - diff --git a/feeds/ipq807x/qca-ssdk/src/src/hsl/isis/isis_init.c b/feeds/ipq807x/qca-ssdk/src/src/hsl/isis/isis_init.c deleted file mode 100755 index b854c2b45..000000000 --- a/feeds/ipq807x/qca-ssdk/src/src/hsl/isis/isis_init.c +++ /dev/null @@ -1,340 +0,0 @@ -/* - * Copyright (c) 2012, 2016-2017, The Linux Foundation. All rights reserved. - * Permission to use, copy, modify, and/or distribute this software for - * any purpose with or without fee is hereby granted, provided that the - * above copyright notice and this permission notice appear in all copies. - * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES - * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR - * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES - * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN - * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT - * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. - */ - - -/** - * @defgroup isis_init ISIS_INIT - * @{ - */ -#include "sw.h" -#include "hsl.h" -#include "hsl_dev.h" -#include "hsl_port_prop.h" -#include "isis_mib.h" -#include "isis_port_ctrl.h" -#include "isis_portvlan.h" -#include "isis_vlan.h" -#include "isis_fdb.h" -#include "isis_qos.h" -#include "isis_mirror.h" -#include "isis_stp.h" -#include "isis_rate.h" -#include "isis_misc.h" -#include "isis_leaky.h" -#include "isis_igmp.h" -#include "isis_acl.h" -#include "isis_led.h" -#include "isis_cosmap.h" -#include "isis_ip.h" -#include "isis_nat.h" -#if defined(IN_NAT_HELPER) -#include "isis_nat_helper.h" -#endif -#include "isis_sec.h" -#include "isis_trunk.h" -#include "isis_interface_ctrl.h" -#include "isis_reg_access.h" -#include "isis_reg.h" -#include "isis_init.h" -#include "f1_phy.h" - -static ssdk_init_cfg * isis_cfg[SW_MAX_NR_DEV] = { 0 }; -a_uint32_t isis_nat_global_status = 0; - -#if !(defined(KERNEL_MODULE) && defined(USER_MODE)) -/* For isis there are five internal PHY devices and seven MAC devices. - MAC0 always connect to external MAC device. - PHY4 can connect to MAC5 or external MAC device. - MAC6 always connect to external devices. - MAC1..MAC4 connect to internal PHY0..PHY3. -*/ -static sw_error_t -isis_portproperty_init(a_uint32_t dev_id, hsl_init_mode mode) -{ - hsl_port_prop_t p_type; - hsl_dev_t *pdev = NULL; - fal_port_t port_id; - - pdev = hsl_dev_ptr_get(dev_id); - if (pdev == NULL) - return SW_NOT_INITIALIZED; - - /* for port property set, SSDK should not generate some limitations */ - for (port_id = 0; port_id < pdev->nr_ports; port_id++) - { - hsl_port_prop_portmap_set(dev_id, port_id); - - for (p_type = HSL_PP_PHY; p_type < HSL_PP_BUTT; p_type++) - { - if (HSL_NO_CPU == mode) - { - SW_RTN_ON_ERROR(hsl_port_prop_set(dev_id, port_id, p_type)); - continue; - } - - switch (p_type) - { - case HSL_PP_PHY: - /* Only port0/port6 without PHY device */ - if ((port_id != pdev->cpu_port_nr) - && (port_id != pdev->nr_ports - 1)) - { - SW_RTN_ON_ERROR(hsl_port_prop_set(dev_id, port_id, p_type)); - } - break; - - case HSL_PP_INCL_CPU: - /* include cpu port but exclude wan port in some cases */ - /* but which port is wan port, we are no meaning */ - SW_RTN_ON_ERROR(hsl_port_prop_set(dev_id, port_id, p_type)); - break; - - case HSL_PP_EXCL_CPU: - /* exclude cpu port and wan port in some cases */ - /* which port is wan port, we are no meaning but port0 is - always CPU port */ - if (port_id != pdev->cpu_port_nr) - { - SW_RTN_ON_ERROR(hsl_port_prop_set(dev_id, port_id, p_type)); - } - break; - - default: - break; - } - } - - if (HSL_NO_CPU == mode) - { - SW_RTN_ON_ERROR(hsl_port_prop_set_phyid - (dev_id, port_id, port_id + 1)); - } - else - { - if (port_id != pdev->cpu_port_nr) - { - SW_RTN_ON_ERROR(hsl_port_prop_set_phyid - (dev_id, port_id, port_id - 1)); - } - } - } - - return SW_OK; -} - -static sw_error_t -isis_hw_init(a_uint32_t dev_id, ssdk_init_cfg *cfg) -{ - return SW_OK; -} - -#endif - -static sw_error_t -isis_dev_init(a_uint32_t dev_id, hsl_init_mode cpu_mode) -{ - a_uint32_t entry = 0; - sw_error_t rv; - hsl_dev_t *pdev = NULL; - - pdev = hsl_dev_ptr_get(dev_id); - if (pdev == NULL) - return SW_NOT_INITIALIZED; - - HSL_REG_FIELD_GET(rv, dev_id, MASK_CTL, 0, DEVICE_ID, - (a_uint8_t *) (&entry), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - - if (S17_DEVICE_ID == entry) - { - pdev->nr_ports = 7; - pdev->nr_phy = 5; - pdev->cpu_port_nr = 0; - pdev->nr_vlans = 4096; - pdev->hw_vlan_query = A_TRUE; - pdev->nr_queue = 6; - pdev->cpu_mode = cpu_mode; - } - else - { - pdev->nr_ports = 6; - pdev->nr_phy = 5; - pdev->cpu_port_nr = 0; - pdev->nr_vlans = 4096; - pdev->hw_vlan_query = A_TRUE; - pdev->nr_queue = 6; - pdev->cpu_mode = cpu_mode; - } - - return SW_OK; -} - - -static sw_error_t -_isis_reset(a_uint32_t dev_id) -{ -#if !(defined(KERNEL_MODULE) && defined(USER_MODE)) - sw_error_t rv; - a_uint32_t val; - - HSL_DEV_ID_CHECK(dev_id); - - val = 0x1; - HSL_REG_FIELD_SET(rv, dev_id, MASK_CTL, 0, SOFT_RST, - (a_uint8_t *) (&val), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - - rv = isis_hw_init(dev_id, isis_cfg[dev_id]); - SW_RTN_ON_ERROR(rv); - - ISIS_ACL_RESET(rv, dev_id); - ISIS_IP_RESET(rv, dev_id); - ISIS_NAT_RESET(rv, dev_id); -#endif - - return SW_OK; -} - -sw_error_t -isis_cleanup(a_uint32_t dev_id) -{ - sw_error_t rv; - - if (isis_cfg[dev_id]) - { -#if defined(IN_NAT_HELPER) - if(isis_nat_global_status) { - ISIS_NAT_HELPER_CLEANUP(rv, dev_id); - isis_nat_global_status = 0; - } -#endif - - ISIS_ACL_CLEANUP(rv, dev_id); - - SW_RTN_ON_ERROR(hsl_port_prop_cleanup_by_dev(dev_id)); - - aos_mem_free(isis_cfg[dev_id]); - isis_cfg[dev_id] = NULL; - } - - return SW_OK; -} - -/** - * @brief reset hsl layer. - * @details Comments: - * This operation will reset hsl layer - * @param[in] dev_id device id - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -isis_reset(a_uint32_t dev_id) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _isis_reset(dev_id); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Init hsl layer. - * @details Comments: - * This operation will init hsl layer and hsl layer - * @param[in] dev_id device id - * @param[in] cfg configuration for initialization - * @return SW_OK or error code - */ -sw_error_t -isis_init(a_uint32_t dev_id, ssdk_init_cfg *cfg) -{ - HSL_DEV_ID_CHECK(dev_id); - - if (NULL == isis_cfg[dev_id]) - { - isis_cfg[dev_id] = aos_mem_alloc(sizeof (ssdk_init_cfg)); - } - - if (NULL == isis_cfg[dev_id]) - { - return SW_OUT_OF_MEM; - } - - aos_mem_copy(isis_cfg[dev_id], cfg, sizeof (ssdk_init_cfg)); - - SW_RTN_ON_ERROR(isis_reg_access_init(dev_id, cfg->reg_mode)); - - SW_RTN_ON_ERROR(isis_dev_init(dev_id, cfg->cpu_mode)); - -#if !(defined(KERNEL_MODULE) && defined(USER_MODE)) - { - sw_error_t rv; - - SW_RTN_ON_ERROR(hsl_port_prop_init(dev_id)); - SW_RTN_ON_ERROR(hsl_port_prop_init_by_dev(dev_id)); - SW_RTN_ON_ERROR(isis_portproperty_init(dev_id, cfg->cpu_mode)); - - ISIS_MIB_INIT(rv, dev_id); - ISIS_PORT_CTRL_INIT(rv, dev_id); - ISIS_PORTVLAN_INIT(rv, dev_id); - ISIS_VLAN_INIT(rv, dev_id); - ISIS_FDB_INIT(rv, dev_id); - ISIS_QOS_INIT(rv, dev_id); - ISIS_STP_INIT(rv, dev_id); - ISIS_MIRR_INIT(rv, dev_id); - ISIS_RATE_INIT(rv, dev_id); - ISIS_MISC_INIT(rv, dev_id); - ISIS_LEAKY_INIT(rv, dev_id); - ISIS_IGMP_INIT(rv, dev_id); - ISIS_ACL_INIT(rv, dev_id); - ISIS_LED_INIT(rv, dev_id); - ISIS_COSMAP_INIT(rv, dev_id); - ISIS_IP_INIT(rv, dev_id); - ISIS_NAT_INIT(rv, dev_id); - ISIS_TRUNK_INIT(rv, dev_id); - ISIS_SEC_INIT(rv, dev_id); - ISIS_INTERFACE_CTRL_INIT(rv, dev_id); - - { - hsl_api_t *p_api; - - SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id)); - p_api->dev_reset = isis_reset; - p_api->dev_clean = isis_cleanup; - } - - SW_RTN_ON_ERROR(isis_hw_init(dev_id, cfg)); -#if 0 -#if defined(IN_NAT_HELPER) - if(!isis_nat_global_status) { - ISIS_NAT_HELPER_INIT(rv, dev_id); - isis_nat_global_status = 1; - } -#endif -#endif - -#if defined(IN_MACBLOCK) - qca_mac_scan_helper_init(); -#endif - } -#endif - - return SW_OK; -} - -/** - * @} - */ - diff --git a/feeds/ipq807x/qca-ssdk/src/src/hsl/isis/isis_interface_ctrl.c b/feeds/ipq807x/qca-ssdk/src/src/hsl/isis/isis_interface_ctrl.c deleted file mode 100755 index 8874ad1c5..000000000 --- a/feeds/ipq807x/qca-ssdk/src/src/hsl/isis/isis_interface_ctrl.c +++ /dev/null @@ -1,1710 +0,0 @@ -/* - * Copyright (c) 2012, 2015-2017, The Linux Foundation. All rights reserved. - * Permission to use, copy, modify, and/or distribute this software for - * any purpose with or without fee is hereby granted, provided that the - * above copyright notice and this permission notice appear in all copies. - * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES - * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR - * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES - * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN - * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT - * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. - */ - - -/** - * @defgroup isis_interface_ctrl ISIS_INTERFACE_CONTROL - * @{ - */ -#include "sw.h" -#include "hsl.h" -#include "hsl_dev.h" -#include "hsl_port_prop.h" -#include "isis_interface_ctrl.h" -#include "isis_reg.h" -#include "hsl_phy.h" - -#define ISIS_MAC_0 0 -#define ISIS_MAC_5 5 -#define ISIS_MAC_6 6 - -#define ISIS_PHY_MODE_PHY_ID 4 -#define ISIS_LPI_PORT1_OFFSET 4 -#define ISIS_LPI_BIT_STEP 2 - -/* we need to do more about MAC5/PHY4 connection... */ -#if 0 -static sw_error_t -_isis_port_mac5_internal_mode(a_uint32_t dev_id, a_bool_t * inter_mode) -{ - sw_error_t rv; - a_uint32_t reg, rgmii, gmii_mac, gmii_phy, mii_mac, mii_phy, sgmii; - - HSL_REG_ENTRY_GET(rv, dev_id, PORT5_PAD_CTRL, 0, - (a_uint8_t *) (®), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - - SW_GET_FIELD_BY_REG(PORT0_PAD_CTRL, MAC0_RGMII_EN, rgmii, reg); - SW_GET_FIELD_BY_REG(PORT0_PAD_CTRL, MAC0_MAC_GMII_EN, gmii_mac, reg); - SW_GET_FIELD_BY_REG(PORT0_PAD_CTRL, MAC0_PHY_GMII_EN, gmii_phy, reg); - SW_GET_FIELD_BY_REG(PORT0_PAD_CTRL, MAC0_MAC_MII_EN, mii_mac, reg); - SW_GET_FIELD_BY_REG(PORT0_PAD_CTRL, MAC0_PHY_MII_EN, mii_phy, reg); - SW_GET_FIELD_BY_REG(PORT0_PAD_CTRL, MAC0_SGMII_EN, sgmii, reg); - - if (rgmii || gmii_mac || gmii_phy || mii_mac || mii_phy || sgmii) - { - *inter_mode = A_FALSE; - } - else - { - *inter_mode = A_TRUE; - } - - return SW_OK; -} - -static sw_error_t -_isis_port_phy4_internal_mode(a_uint32_t dev_id, a_bool_t * inter_mode) -{ - sw_error_t rv; - a_uint32_t reg, rgmii, gmii, mii; - - HSL_REG_ENTRY_GET(rv, dev_id, PORT6_PAD_CTRL, 0, - (a_uint8_t *) (®), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - - SW_GET_FIELD_BY_REG(PORT6_PAD_CTRL, PHY4_RGMII_EN, rgmii, reg); - SW_GET_FIELD_BY_REG(PORT6_PAD_CTRL, PHY4_GMII_EN, gmii, reg); - SW_GET_FIELD_BY_REG(PORT6_PAD_CTRL, PHY4_MII_EN, mii, reg); - - if (rgmii || gmii || mii) - { - *inter_mode = A_FALSE; - } - else - { - *inter_mode = A_TRUE; - } - - return SW_OK; -} -#endif - -static sw_error_t -_isis_port_3az_status_set(a_uint32_t dev_id, fal_port_t port_id, a_bool_t enable) -{ - sw_error_t rv; - a_uint32_t reg = 0, field, offset, device_id, rev_id, reverse = 0; - - HSL_REG_ENTRY_GET(rv, dev_id, MASK_CTL, 0, - (a_uint8_t *) (®), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - - SW_GET_FIELD_BY_REG(MASK_CTL, DEVICE_ID, device_id, reg); - if (S17_DEVICE_ID != device_id) - { - return SW_NOT_SUPPORTED; - } - - SW_GET_FIELD_BY_REG(MASK_CTL, REV_ID, rev_id, reg); - if (S17_REVISION_A == rev_id) - { - reverse = 0; - } - else - { - reverse = 1; - } - - if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_PHY)) - { - return SW_BAD_PARAM; - } - - HSL_REG_ENTRY_GET(rv, dev_id, EEE_CTL, 0, - (a_uint8_t *) (®), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - - if (A_TRUE == enable) - { - field = 1; - } - else if (A_FALSE == enable) - { - field = 0; - } - else - { - return SW_BAD_PARAM; - } - - if (reverse) - { - field = (~field) & 0x1UL; - } - - offset = (port_id - 1) * ISIS_LPI_BIT_STEP + ISIS_LPI_PORT1_OFFSET; - reg &= (~(0x1UL << offset)); - reg |= (field << offset); - - HSL_REG_ENTRY_SET(rv, dev_id, EEE_CTL, 0, - (a_uint8_t *) (®), sizeof (a_uint32_t)); - return rv; -} - -static sw_error_t -_isis_port_3az_status_get(a_uint32_t dev_id, fal_port_t port_id, a_bool_t * enable) -{ - sw_error_t rv; - a_uint32_t reg = 0, field, offset, device_id, rev_id, reverse = 0; - - HSL_REG_ENTRY_GET(rv, dev_id, MASK_CTL, 0, - (a_uint8_t *) (®), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - - SW_GET_FIELD_BY_REG(MASK_CTL, DEVICE_ID, device_id, reg); - if (S17_DEVICE_ID != device_id) - { - return SW_NOT_SUPPORTED; - } - - SW_GET_FIELD_BY_REG(MASK_CTL, REV_ID, rev_id, reg); - if (S17_REVISION_A == rev_id) - { - reverse = 0; - } - else - { - reverse = 1; - } - - if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_PHY)) - { - return SW_BAD_PARAM; - } - - HSL_REG_ENTRY_GET(rv, dev_id, EEE_CTL, 0, - (a_uint8_t *) (®), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - - offset = (port_id - 1) * ISIS_LPI_BIT_STEP + ISIS_LPI_PORT1_OFFSET; - field = (reg >> offset) & 0x1; - - if (reverse) - { - field = (~field) & 0x1UL; - } - - if (field) - { - *enable = A_TRUE; - } - else - { - *enable = A_FALSE; - } - - return SW_OK; -} - -static sw_error_t -_isis_port_rgmii_mode_set(a_uint32_t dev_id, fal_port_t port_id, fal_mac_rgmii_config_t * config) -{ - sw_error_t rv; - a_uint32_t reg = 0; - - if (ISIS_MAC_0 == port_id) - { - HSL_REG_ENTRY_GET(rv, dev_id, PORT0_PAD_CTRL, 0, - (a_uint8_t *) (®), sizeof (a_uint32_t)); - } - else if (ISIS_MAC_5 == port_id) - { - HSL_REG_ENTRY_GET(rv, dev_id, PORT5_PAD_CTRL, 0, - (a_uint8_t *) (®), sizeof (a_uint32_t)); - } - else if (ISIS_MAC_6 == port_id) - { - HSL_REG_ENTRY_GET(rv, dev_id, PORT6_PAD_CTRL, 0, - (a_uint8_t *) (®), sizeof (a_uint32_t)); - } - else - { - return SW_BAD_PARAM; - } - SW_RTN_ON_ERROR(rv); - - SW_SET_REG_BY_FIELD(PORT0_PAD_CTRL, MAC0_RGMII_EN, 1, reg); - SW_SET_REG_BY_FIELD(PORT0_PAD_CTRL, MAC0_MAC_GMII_EN, 0, reg); - SW_SET_REG_BY_FIELD(PORT0_PAD_CTRL, MAC0_PHY_GMII_EN, 0, reg); - SW_SET_REG_BY_FIELD(PORT0_PAD_CTRL, MAC0_MAC_MII_EN, 0, reg); - SW_SET_REG_BY_FIELD(PORT0_PAD_CTRL, MAC0_PHY_MII_EN, 0, reg); - SW_SET_REG_BY_FIELD(PORT0_PAD_CTRL, MAC0_SGMII_EN, 0, reg); - - /* hardware suggestions: restore to defatult settings */ - SW_SET_REG_BY_FIELD(PORT0_PAD_CTRL, MAC0_PHY_GMII_TXCLK_SEL, 0, reg); - SW_SET_REG_BY_FIELD(PORT0_PAD_CTRL, MAC0_PHY_GMII_RXCLK_SEL, 0, reg); - SW_SET_REG_BY_FIELD(PORT0_PAD_CTRL, MAC0_PHY_MII_TXCLK_SEL, 0, reg); - SW_SET_REG_BY_FIELD(PORT0_PAD_CTRL, MAC0_PHY_MII_RXCLK_SEL, 0, reg); - SW_SET_REG_BY_FIELD(PORT0_PAD_CTRL, MAC0_MAC_GMII_TXCLK_SEL, 0, reg); - SW_SET_REG_BY_FIELD(PORT0_PAD_CTRL, MAC0_MAC_GMII_RXCLK_SEL, 0, reg); - SW_SET_REG_BY_FIELD(PORT0_PAD_CTRL, MAC0_MAC_MII_TXCLK_SEL, 0, reg); - SW_SET_REG_BY_FIELD(PORT0_PAD_CTRL, MAC0_MAC_MII_RXCLK_SEL, 0, reg); - - if (A_TRUE == config->txclk_delay_cmd) - { - SW_SET_REG_BY_FIELD(PORT0_PAD_CTRL, MAC0_RGMII_TXCLK_DELAY_EN, 1, reg); - SW_SET_REG_BY_FIELD(PORT0_PAD_CTRL, MAC0_RGMII_TXCLK_DELAY_SEL, config->txclk_delay_sel, reg); - } - else - { - SW_SET_REG_BY_FIELD(PORT0_PAD_CTRL, MAC0_RGMII_TXCLK_DELAY_EN, 0, reg); - SW_SET_REG_BY_FIELD(PORT0_PAD_CTRL, MAC0_RGMII_TXCLK_DELAY_SEL, 0, reg); - } - - if (A_TRUE == config->rxclk_delay_cmd) - { - SW_SET_REG_BY_FIELD(PORT0_PAD_CTRL, MAC0_RGMII_RXCLK_DELAY_EN, 1, reg); - SW_SET_REG_BY_FIELD(PORT0_PAD_CTRL, MAC0_RGMII_RXCLK_DELAY_SEL, config->rxclk_delay_sel, reg); - } - else - { - SW_SET_REG_BY_FIELD(PORT0_PAD_CTRL, MAC0_RGMII_RXCLK_DELAY_EN, 0, reg); - SW_SET_REG_BY_FIELD(PORT0_PAD_CTRL, MAC0_RGMII_RXCLK_DELAY_SEL, 0, reg); - } - - if (ISIS_MAC_0 == port_id) - { - HSL_REG_ENTRY_SET(rv, dev_id, PORT0_PAD_CTRL, 0, - (a_uint8_t *) (®), sizeof (a_uint32_t)); - } - else if (ISIS_MAC_5 == port_id) - { - HSL_REG_ENTRY_SET(rv, dev_id, PORT5_PAD_CTRL, 0, - (a_uint8_t *) (®), sizeof (a_uint32_t)); - } - else - { - HSL_REG_ENTRY_SET(rv, dev_id, PORT6_PAD_CTRL, 0, - (a_uint8_t *) (®), sizeof (a_uint32_t)); - } - SW_RTN_ON_ERROR(rv); - - /* Port status register setting */ - HSL_REG_ENTRY_GET(rv, dev_id, PORT_STATUS, port_id, - (a_uint8_t *) (®), sizeof (a_uint32_t)); - - /* setting port status default configuration */ - SW_SET_REG_BY_FIELD(PORT_STATUS, LINK_EN, 0, reg); - SW_SET_REG_BY_FIELD(PORT_STATUS, FLOW_LINK_EN, 0, reg); - SW_SET_REG_BY_FIELD(PORT_STATUS, RX_FLOW_EN, 1, reg); - SW_SET_REG_BY_FIELD(PORT_STATUS, TX_FLOW_EN, 1, reg); - SW_SET_REG_BY_FIELD(PORT_STATUS, DUPLEX_MODE, 1, reg); - SW_SET_REG_BY_FIELD(PORT_STATUS, RXMAC_EN, 1, reg); - SW_SET_REG_BY_FIELD(PORT_STATUS, TXMAC_EN, 1, reg); - SW_SET_REG_BY_FIELD(PORT_STATUS, SPEED_MODE, 2, reg); - HSL_REG_ENTRY_SET(rv, dev_id, PORT_STATUS, port_id, - (a_uint8_t *) (®), sizeof (a_uint32_t)); - return rv; -} - -static sw_error_t -_isis_port_rgmii_mode_get(a_uint32_t dev_id, fal_port_t port_id, fal_mac_rgmii_config_t * config) -{ - sw_error_t rv; - a_uint32_t reg = 0, field; - - if (ISIS_MAC_0 == port_id) - { - HSL_REG_ENTRY_GET(rv, dev_id, PORT0_PAD_CTRL, 0, - (a_uint8_t *) (®), sizeof (a_uint32_t)); - } - else if (ISIS_MAC_5 == port_id) - { - HSL_REG_ENTRY_GET(rv, dev_id, PORT5_PAD_CTRL, 0, - (a_uint8_t *) (®), sizeof (a_uint32_t)); - } - else if (ISIS_MAC_6 == port_id) - { - HSL_REG_ENTRY_GET(rv, dev_id, PORT6_PAD_CTRL, 0, - (a_uint8_t *) (®), sizeof (a_uint32_t)); - } - else - { - return SW_BAD_PARAM; - } - SW_RTN_ON_ERROR(rv); - - SW_GET_FIELD_BY_REG(PORT0_PAD_CTRL, MAC0_RGMII_TXCLK_DELAY_EN, field, reg); - if (field) - { - config->txclk_delay_cmd = A_TRUE; - SW_GET_FIELD_BY_REG(PORT0_PAD_CTRL, MAC0_RGMII_TXCLK_DELAY_SEL, field, reg); - config->txclk_delay_sel = field; - } - else - { - config->txclk_delay_cmd = A_FALSE; - config->txclk_delay_sel = 0; - } - - SW_GET_FIELD_BY_REG(PORT0_PAD_CTRL, MAC0_RGMII_RXCLK_DELAY_EN, field, reg); - if (field) - { - config->rxclk_delay_cmd = A_TRUE; - SW_GET_FIELD_BY_REG(PORT0_PAD_CTRL, MAC0_RGMII_RXCLK_DELAY_SEL, field, reg); - config->rxclk_delay_sel = field; - } - else - { - config->rxclk_delay_cmd = A_FALSE; - config->rxclk_delay_sel = 0; - } - - return SW_OK; -} - -static sw_error_t -_isis_port_gmii_mode_set(a_uint32_t dev_id, fal_port_t port_id, fal_mac_gmii_config_t * config) -{ - sw_error_t rv; - a_uint32_t reg = 0; - - if (ISIS_MAC_0 == port_id) - { - HSL_REG_ENTRY_GET(rv, dev_id, PORT0_PAD_CTRL, 0, - (a_uint8_t *) (®), sizeof (a_uint32_t)); - } - else if (ISIS_MAC_6 == port_id) - { - HSL_REG_ENTRY_GET(rv, dev_id, PORT6_PAD_CTRL, 0, - (a_uint8_t *) (®), sizeof (a_uint32_t)); - } - else - { - return SW_BAD_PARAM; - } - SW_RTN_ON_ERROR(rv); - - SW_SET_REG_BY_FIELD(PORT0_PAD_CTRL, MAC0_RGMII_EN, 0, reg); - SW_SET_REG_BY_FIELD(PORT0_PAD_CTRL, MAC0_MAC_MII_EN, 0, reg); - SW_SET_REG_BY_FIELD(PORT0_PAD_CTRL, MAC0_PHY_MII_EN, 0, reg); - SW_SET_REG_BY_FIELD(PORT0_PAD_CTRL, MAC0_SGMII_EN, 0, reg); - - /* hardware suggestions: restore to defatult settings */ - SW_SET_REG_BY_FIELD(PORT0_PAD_CTRL, MAC0_RGMII_TXCLK_DELAY_EN, 0, reg); - SW_SET_REG_BY_FIELD(PORT0_PAD_CTRL, MAC0_RGMII_RXCLK_DELAY_EN, 0, reg); - SW_SET_REG_BY_FIELD(PORT0_PAD_CTRL, MAC0_RGMII_TXCLK_DELAY_SEL, 0, reg); - SW_SET_REG_BY_FIELD(PORT0_PAD_CTRL, MAC0_RGMII_RXCLK_DELAY_SEL, 0, reg); - SW_SET_REG_BY_FIELD(PORT0_PAD_CTRL, MAC0_PHY_GMII_TXCLK_SEL, 0, reg); - SW_SET_REG_BY_FIELD(PORT0_PAD_CTRL, MAC0_PHY_GMII_RXCLK_SEL, 0, reg); - SW_SET_REG_BY_FIELD(PORT0_PAD_CTRL, MAC0_PHY_MII_TXCLK_SEL, 0, reg); - SW_SET_REG_BY_FIELD(PORT0_PAD_CTRL, MAC0_PHY_MII_RXCLK_SEL, 0, reg); - SW_SET_REG_BY_FIELD(PORT0_PAD_CTRL, MAC0_MAC_GMII_TXCLK_SEL, 0, reg); - SW_SET_REG_BY_FIELD(PORT0_PAD_CTRL, MAC0_MAC_GMII_RXCLK_SEL, 0, reg); - SW_SET_REG_BY_FIELD(PORT0_PAD_CTRL, MAC0_MAC_MII_TXCLK_SEL, 0, reg); - SW_SET_REG_BY_FIELD(PORT0_PAD_CTRL, MAC0_MAC_MII_RXCLK_SEL, 0, reg); - - if (FAL_INTERFACE_CLOCK_PHY_MODE == config->clock_mode) - { - SW_SET_REG_BY_FIELD(PORT0_PAD_CTRL, MAC0_MAC_GMII_EN, 0, reg); - SW_SET_REG_BY_FIELD(PORT0_PAD_CTRL, MAC0_PHY_GMII_EN, 1, reg); - SW_SET_REG_BY_FIELD(PORT0_PAD_CTRL, MAC0_PHY_GMII_TXCLK_SEL, config->txclk_select, reg); - SW_SET_REG_BY_FIELD(PORT0_PAD_CTRL, MAC0_PHY_GMII_RXCLK_SEL, config->rxclk_select, reg); - - } - else if (FAL_INTERFACE_CLOCK_MAC_MODE == config->clock_mode) - { - SW_SET_REG_BY_FIELD(PORT0_PAD_CTRL, MAC0_MAC_GMII_EN, 1, reg); - SW_SET_REG_BY_FIELD(PORT0_PAD_CTRL, MAC0_PHY_GMII_EN, 0, reg); - SW_SET_REG_BY_FIELD(PORT0_PAD_CTRL, MAC0_MAC_GMII_TXCLK_SEL, config->txclk_select, reg); - SW_SET_REG_BY_FIELD(PORT0_PAD_CTRL, MAC0_MAC_GMII_RXCLK_SEL, config->rxclk_select, reg); - - } - else - { - return SW_BAD_PARAM; - } - - if (ISIS_MAC_0 == port_id) - { - HSL_REG_ENTRY_SET(rv, dev_id, PORT0_PAD_CTRL, 0, - (a_uint8_t *) (®), sizeof (a_uint32_t)); - } - else - { - HSL_REG_ENTRY_SET(rv, dev_id, PORT6_PAD_CTRL, 0, - (a_uint8_t *) (®), sizeof (a_uint32_t)); - } - SW_RTN_ON_ERROR(rv); - - /* Port status register setting */ - HSL_REG_ENTRY_GET(rv, dev_id, PORT_STATUS, port_id, - (a_uint8_t *) (®), sizeof (a_uint32_t)); - - /* setting port status default configuration */ - SW_SET_REG_BY_FIELD(PORT_STATUS, LINK_EN, 0, reg); - SW_SET_REG_BY_FIELD(PORT_STATUS, FLOW_LINK_EN, 0, reg); - SW_SET_REG_BY_FIELD(PORT_STATUS, RX_FLOW_EN, 1, reg); - SW_SET_REG_BY_FIELD(PORT_STATUS, TX_FLOW_EN, 1, reg); - SW_SET_REG_BY_FIELD(PORT_STATUS, DUPLEX_MODE, 1, reg); - SW_SET_REG_BY_FIELD(PORT_STATUS, RXMAC_EN, 1, reg); - SW_SET_REG_BY_FIELD(PORT_STATUS, TXMAC_EN, 1, reg); - SW_SET_REG_BY_FIELD(PORT_STATUS, SPEED_MODE, 2, reg); - HSL_REG_ENTRY_SET(rv, dev_id, PORT_STATUS, port_id, - (a_uint8_t *) (®), sizeof (a_uint32_t)); - return rv; -} - -static sw_error_t -_isis_port_gmii_mode_get(a_uint32_t dev_id, fal_port_t port_id, fal_mac_gmii_config_t * config) -{ - sw_error_t rv; - a_uint32_t reg = 0, field; - - if (ISIS_MAC_0 == port_id) - { - HSL_REG_ENTRY_GET(rv, dev_id, PORT0_PAD_CTRL, 0, - (a_uint8_t *) (®), sizeof (a_uint32_t)); - } - else if (ISIS_MAC_6 == port_id) - { - HSL_REG_ENTRY_GET(rv, dev_id, PORT6_PAD_CTRL, 0, - (a_uint8_t *) (®), sizeof (a_uint32_t)); - } - else - { - return SW_BAD_PARAM; - } - SW_RTN_ON_ERROR(rv); - - SW_GET_FIELD_BY_REG(PORT0_PAD_CTRL, MAC0_PHY_GMII_EN, field, reg); - if (field) - { - config->clock_mode = FAL_INTERFACE_CLOCK_PHY_MODE; - SW_GET_FIELD_BY_REG(PORT0_PAD_CTRL, MAC0_PHY_GMII_TXCLK_SEL, field, reg); - config->txclk_select = field; - SW_GET_FIELD_BY_REG(PORT0_PAD_CTRL, MAC0_PHY_GMII_RXCLK_SEL, field, reg); - config->rxclk_select = field; - - } - else - { - config->clock_mode = FAL_INTERFACE_CLOCK_MAC_MODE; - SW_GET_FIELD_BY_REG(PORT0_PAD_CTRL, MAC0_MAC_GMII_TXCLK_SEL, field, reg); - config->txclk_select = field; - SW_GET_FIELD_BY_REG(PORT0_PAD_CTRL, MAC0_MAC_GMII_RXCLK_SEL, field, reg); - config->rxclk_select = field; - } - - return SW_OK; -} - -static sw_error_t -_isis_port_mii_mode_set(a_uint32_t dev_id, fal_port_t port_id, fal_mac_mii_config_t * config) -{ - sw_error_t rv; - a_uint32_t reg = 0; - - if (ISIS_MAC_0 == port_id) - { - HSL_REG_ENTRY_GET(rv, dev_id, PORT0_PAD_CTRL, 0, - (a_uint8_t *) (®), sizeof (a_uint32_t)); - } - else if (ISIS_MAC_5 == port_id) - { - HSL_REG_ENTRY_GET(rv, dev_id, PORT5_PAD_CTRL, 0, - (a_uint8_t *) (®), sizeof (a_uint32_t)); - } - else if (ISIS_MAC_6 == port_id) - { - HSL_REG_ENTRY_GET(rv, dev_id, PORT6_PAD_CTRL, 0, - (a_uint8_t *) (®), sizeof (a_uint32_t)); - } - else - { - return SW_BAD_PARAM; - } - SW_RTN_ON_ERROR(rv); - - SW_SET_REG_BY_FIELD(PORT0_PAD_CTRL, MAC0_RGMII_EN, 0, reg); - SW_SET_REG_BY_FIELD(PORT0_PAD_CTRL, MAC0_MAC_GMII_EN, 0, reg); - SW_SET_REG_BY_FIELD(PORT0_PAD_CTRL, MAC0_PHY_GMII_EN, 0, reg); - SW_SET_REG_BY_FIELD(PORT0_PAD_CTRL, MAC0_SGMII_EN, 0, reg); - - /* hardware suggestions: restore to defatult settings */ - SW_SET_REG_BY_FIELD(PORT0_PAD_CTRL, MAC0_RGMII_TXCLK_DELAY_EN, 0, reg); - SW_SET_REG_BY_FIELD(PORT0_PAD_CTRL, MAC0_RGMII_RXCLK_DELAY_EN, 0, reg); - SW_SET_REG_BY_FIELD(PORT0_PAD_CTRL, MAC0_RGMII_TXCLK_DELAY_SEL, 0, reg); - SW_SET_REG_BY_FIELD(PORT0_PAD_CTRL, MAC0_RGMII_RXCLK_DELAY_SEL, 0, reg); - SW_SET_REG_BY_FIELD(PORT0_PAD_CTRL, MAC0_PHY_GMII_TXCLK_SEL, 0, reg); - SW_SET_REG_BY_FIELD(PORT0_PAD_CTRL, MAC0_PHY_GMII_RXCLK_SEL, 0, reg); - SW_SET_REG_BY_FIELD(PORT0_PAD_CTRL, MAC0_PHY_MII_TXCLK_SEL, 0, reg); - SW_SET_REG_BY_FIELD(PORT0_PAD_CTRL, MAC0_PHY_MII_RXCLK_SEL, 0, reg); - SW_SET_REG_BY_FIELD(PORT0_PAD_CTRL, MAC0_MAC_GMII_TXCLK_SEL, 0, reg); - SW_SET_REG_BY_FIELD(PORT0_PAD_CTRL, MAC0_MAC_GMII_RXCLK_SEL, 0, reg); - SW_SET_REG_BY_FIELD(PORT0_PAD_CTRL, MAC0_MAC_MII_TXCLK_SEL, 0, reg); - SW_SET_REG_BY_FIELD(PORT0_PAD_CTRL, MAC0_MAC_MII_RXCLK_SEL, 0, reg); - - if (FAL_INTERFACE_CLOCK_PHY_MODE == config->clock_mode) - { - SW_SET_REG_BY_FIELD(PORT0_PAD_CTRL, MAC0_MAC_MII_EN, 0, reg); - SW_SET_REG_BY_FIELD(PORT0_PAD_CTRL, MAC0_PHY_MII_EN, 1, reg); - SW_SET_REG_BY_FIELD(PORT0_PAD_CTRL, MAC0_PHY_MII_TXCLK_SEL, config->txclk_select, reg); - SW_SET_REG_BY_FIELD(PORT0_PAD_CTRL, MAC0_PHY_MII_RXCLK_SEL, config->rxclk_select, reg); - } - else if (FAL_INTERFACE_CLOCK_MAC_MODE == config->clock_mode) - { - SW_SET_REG_BY_FIELD(PORT0_PAD_CTRL, MAC0_MAC_MII_EN, 1, reg); - SW_SET_REG_BY_FIELD(PORT0_PAD_CTRL, MAC0_PHY_MII_EN, 0, reg); - SW_SET_REG_BY_FIELD(PORT0_PAD_CTRL, MAC0_MAC_MII_TXCLK_SEL, config->txclk_select, reg); - SW_SET_REG_BY_FIELD(PORT0_PAD_CTRL, MAC0_MAC_MII_RXCLK_SEL, config->rxclk_select, reg); - } - else - { - return SW_BAD_PARAM; - } - - if (ISIS_MAC_0 == port_id) - { - HSL_REG_ENTRY_SET(rv, dev_id, PORT0_PAD_CTRL, 0, - (a_uint8_t *) (®), sizeof (a_uint32_t)); - } - else if (ISIS_MAC_5 == port_id) - { - HSL_REG_ENTRY_SET(rv, dev_id, PORT5_PAD_CTRL, 0, - (a_uint8_t *) (®), sizeof (a_uint32_t)); - } - else - { - HSL_REG_ENTRY_SET(rv, dev_id, PORT6_PAD_CTRL, 0, - (a_uint8_t *) (®), sizeof (a_uint32_t)); - } - SW_RTN_ON_ERROR(rv); - - /* Port status register setting */ - HSL_REG_ENTRY_GET(rv, dev_id, PORT_STATUS, port_id, - (a_uint8_t *) (®), sizeof (a_uint32_t)); - - /* setting port status default configuration */ - SW_SET_REG_BY_FIELD(PORT_STATUS, LINK_EN, 0, reg); - SW_SET_REG_BY_FIELD(PORT_STATUS, FLOW_LINK_EN, 0, reg); - SW_SET_REG_BY_FIELD(PORT_STATUS, RX_FLOW_EN, 1, reg); - SW_SET_REG_BY_FIELD(PORT_STATUS, TX_FLOW_EN, 1, reg); - SW_SET_REG_BY_FIELD(PORT_STATUS, DUPLEX_MODE, 1, reg); - SW_SET_REG_BY_FIELD(PORT_STATUS, RXMAC_EN, 1, reg); - SW_SET_REG_BY_FIELD(PORT_STATUS, TXMAC_EN, 1, reg); - SW_SET_REG_BY_FIELD(PORT_STATUS, SPEED_MODE, 1, reg); - HSL_REG_ENTRY_SET(rv, dev_id, PORT_STATUS, port_id, - (a_uint8_t *) (®), sizeof (a_uint32_t)); - return rv; -} - -static sw_error_t -_isis_port_mii_mode_get(a_uint32_t dev_id, fal_port_t port_id, fal_mac_mii_config_t * config) -{ - sw_error_t rv; - a_uint32_t reg = 0, field; - - if (ISIS_MAC_0 == port_id) - { - HSL_REG_ENTRY_GET(rv, dev_id, PORT0_PAD_CTRL, 0, - (a_uint8_t *) (®), sizeof (a_uint32_t)); - } - else if (ISIS_MAC_5 == port_id) - { - HSL_REG_ENTRY_GET(rv, dev_id, PORT5_PAD_CTRL, 0, - (a_uint8_t *) (®), sizeof (a_uint32_t)); - } - else if (ISIS_MAC_6 == port_id) - { - HSL_REG_ENTRY_GET(rv, dev_id, PORT6_PAD_CTRL, 0, - (a_uint8_t *) (®), sizeof (a_uint32_t)); - } - else - { - return SW_BAD_PARAM; - } - SW_RTN_ON_ERROR(rv); - - SW_GET_FIELD_BY_REG(PORT0_PAD_CTRL, MAC0_PHY_MII_EN, field, reg); - if (field) - { - config->clock_mode = FAL_INTERFACE_CLOCK_PHY_MODE; - SW_GET_FIELD_BY_REG(PORT0_PAD_CTRL, MAC0_PHY_MII_TXCLK_SEL, field, reg); - config->txclk_select = field; - SW_GET_FIELD_BY_REG(PORT0_PAD_CTRL, MAC0_PHY_MII_RXCLK_SEL, field, reg); - config->rxclk_select = field; - } - else - { - config->clock_mode = FAL_INTERFACE_CLOCK_MAC_MODE; - SW_GET_FIELD_BY_REG(PORT0_PAD_CTRL, MAC0_MAC_MII_TXCLK_SEL, field, reg); - config->txclk_select = field; - SW_GET_FIELD_BY_REG(PORT0_PAD_CTRL, MAC0_MAC_MII_RXCLK_SEL, field, reg); - config->rxclk_select = field; - } - - return SW_OK; -} - -static sw_error_t -_isis_port_sgmii_mode_set(a_uint32_t dev_id, fal_port_t port_id, fal_mac_sgmii_config_t * config) -{ - sw_error_t rv; - a_uint32_t reg = 0, field; - - if (ISIS_MAC_0 == port_id) - { - HSL_REG_ENTRY_GET(rv, dev_id, PORT0_PAD_CTRL, 0, - (a_uint8_t *) (®), sizeof (a_uint32_t)); - } - else if (ISIS_MAC_6 == port_id) - { - HSL_REG_ENTRY_GET(rv, dev_id, PORT6_PAD_CTRL, 0, - (a_uint8_t *) (®), sizeof (a_uint32_t)); - } - else - { - return SW_BAD_PARAM; - } - SW_RTN_ON_ERROR(rv); - - SW_SET_REG_BY_FIELD(PORT0_PAD_CTRL, MAC0_RGMII_EN, 0, reg); - SW_SET_REG_BY_FIELD(PORT0_PAD_CTRL, MAC0_MAC_GMII_EN, 0, reg); - SW_SET_REG_BY_FIELD(PORT0_PAD_CTRL, MAC0_PHY_GMII_EN, 0, reg); - SW_SET_REG_BY_FIELD(PORT0_PAD_CTRL, MAC0_MAC_MII_EN, 0, reg); - SW_SET_REG_BY_FIELD(PORT0_PAD_CTRL, MAC0_PHY_MII_EN, 0, reg); - SW_SET_REG_BY_FIELD(PORT0_PAD_CTRL, MAC0_SGMII_EN, 1, reg); - - /* hardware suggestions: restore to defatult settings */ - SW_SET_REG_BY_FIELD(PORT0_PAD_CTRL, MAC0_RGMII_TXCLK_DELAY_EN, 0, reg); - SW_SET_REG_BY_FIELD(PORT0_PAD_CTRL, MAC0_RGMII_RXCLK_DELAY_EN, 0, reg); - SW_SET_REG_BY_FIELD(PORT0_PAD_CTRL, MAC0_RGMII_TXCLK_DELAY_SEL, 0, reg); - SW_SET_REG_BY_FIELD(PORT0_PAD_CTRL, MAC0_RGMII_RXCLK_DELAY_SEL, 0, reg); - SW_SET_REG_BY_FIELD(PORT0_PAD_CTRL, MAC0_PHY_GMII_TXCLK_SEL, 0, reg); - SW_SET_REG_BY_FIELD(PORT0_PAD_CTRL, MAC0_PHY_GMII_RXCLK_SEL, 0, reg); - SW_SET_REG_BY_FIELD(PORT0_PAD_CTRL, MAC0_PHY_MII_TXCLK_SEL, 0, reg); - SW_SET_REG_BY_FIELD(PORT0_PAD_CTRL, MAC0_PHY_MII_RXCLK_SEL, 0, reg); - SW_SET_REG_BY_FIELD(PORT0_PAD_CTRL, MAC0_MAC_GMII_TXCLK_SEL, 0, reg); - SW_SET_REG_BY_FIELD(PORT0_PAD_CTRL, MAC0_MAC_GMII_RXCLK_SEL, 0, reg); - SW_SET_REG_BY_FIELD(PORT0_PAD_CTRL, MAC0_MAC_MII_TXCLK_SEL, 0, reg); - SW_SET_REG_BY_FIELD(PORT0_PAD_CTRL, MAC0_MAC_MII_RXCLK_SEL, 0, reg); - - if (ISIS_MAC_0 == port_id) - { - HSL_REG_ENTRY_SET(rv, dev_id, PORT0_PAD_CTRL, 0, - (a_uint8_t *) (®), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - - /* only support one SGMII interface, so we need to disable another SGMII */ - field = 0; - HSL_REG_FIELD_SET(rv, dev_id, PORT6_PAD_CTRL, port_id, MAC6_SGMII_EN, - (a_uint8_t *) (&field), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - } - else - { - HSL_REG_ENTRY_SET(rv, dev_id, PORT6_PAD_CTRL, 0, - (a_uint8_t *) (®), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - - /* only support one SGMII interface, so we need to disable another SGMII */ - field = 0; - HSL_REG_FIELD_SET(rv, dev_id, PORT0_PAD_CTRL, port_id, MAC0_SGMII_EN, - (a_uint8_t *) (&field), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - } - - /* SGMII global settings, for all SGMII interfaces, now we fix all the values */ - /* TX/RX clock setting */ - HSL_REG_ENTRY_GET(rv, dev_id, PORT0_PAD_CTRL, 0, - (a_uint8_t *) (®), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - - SW_SET_REG_BY_FIELD(PORT0_PAD_CTRL, SGMII_CLK125M_RX_SEL, 1, reg); - SW_SET_REG_BY_FIELD(PORT0_PAD_CTRL, SGMII_CLK125M_TX_SEL, 0, reg); - - HSL_REG_ENTRY_SET(rv, dev_id, PORT0_PAD_CTRL, 0, - (a_uint8_t *) (®), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - - /* SGMII control register setting */ - HSL_REG_ENTRY_GET(rv, dev_id, SGMII_CTRL, 0, - (a_uint8_t *) (®), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - - SW_SET_REG_BY_FIELD(SGMII_CTRL, SGMII_FIBER_MODE, 0, reg); - SW_SET_REG_BY_FIELD(SGMII_CTRL, SGMII_EN_PLL, 0, reg); - SW_SET_REG_BY_FIELD(SGMII_CTRL, SGMII_EN_RX, 0, reg); - SW_SET_REG_BY_FIELD(SGMII_CTRL, SGMII_EN_TX, 0, reg); - SW_SET_REG_BY_FIELD(SGMII_CTRL, SGMII_EN_SD, 1, reg); - if (FAL_INTERFACE_CLOCK_PHY_MODE == config->clock_mode) - { - SW_SET_REG_BY_FIELD(SGMII_CTRL, MODE_CTRL_25M, 1, reg); - } - else - { - SW_SET_REG_BY_FIELD(SGMII_CTRL, MODE_CTRL_25M, 2, reg); - } - HSL_REG_ENTRY_SET(rv, dev_id, SGMII_CTRL, 0, - (a_uint8_t *) (®), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - - /* Port status register setting */ - HSL_REG_ENTRY_GET(rv, dev_id, PORT_STATUS, port_id, - (a_uint8_t *) (®), sizeof (a_uint32_t)); - - /* setting port status default configuration */ - SW_SET_REG_BY_FIELD(PORT_STATUS, FLOW_LINK_EN, 0, reg); - SW_SET_REG_BY_FIELD(PORT_STATUS, RX_FLOW_EN, 1, reg); - SW_SET_REG_BY_FIELD(PORT_STATUS, TX_FLOW_EN, 1, reg); - SW_SET_REG_BY_FIELD(PORT_STATUS, DUPLEX_MODE, 1, reg); - SW_SET_REG_BY_FIELD(PORT_STATUS, RXMAC_EN, 1, reg); - SW_SET_REG_BY_FIELD(PORT_STATUS, TXMAC_EN, 1, reg); - SW_SET_REG_BY_FIELD(PORT_STATUS, SPEED_MODE, 2, reg); - if (A_TRUE == config->auto_neg) - { - SW_SET_REG_BY_FIELD(PORT_STATUS, LINK_EN, 1, reg); - } - else - { - SW_SET_REG_BY_FIELD(PORT_STATUS, LINK_EN, 0, reg); - } - - HSL_REG_ENTRY_SET(rv, dev_id, PORT_STATUS, port_id, - (a_uint8_t *) (®), sizeof (a_uint32_t)); - return rv; -} - -static sw_error_t -_isis_port_sgmii_mode_get(a_uint32_t dev_id, fal_port_t port_id, fal_mac_sgmii_config_t * config) -{ - sw_error_t rv; - a_uint32_t reg = 0, field; - - if (ISIS_MAC_0 == port_id) - { - /* nothing to do */ - } - else if (ISIS_MAC_6 == port_id) - { - /* nothing to do */ - } - else - { - return SW_BAD_PARAM; - } - - HSL_REG_ENTRY_GET(rv, dev_id, PORT_STATUS, port_id, - (a_uint8_t *) (®), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - - SW_GET_FIELD_BY_REG(PORT_STATUS, LINK_EN, field, reg); - if (field) - { - config->auto_neg = A_TRUE; - } - else - { - config->auto_neg = A_FALSE; - } - - HSL_REG_ENTRY_GET(rv, dev_id, SGMII_CTRL, 0, - (a_uint8_t *) (®), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - SW_GET_FIELD_BY_REG(SGMII_CTRL, MODE_CTRL_25M, field, reg); - if (1 == field) - { - config->clock_mode = FAL_INTERFACE_CLOCK_PHY_MODE; - } - else - { - config->clock_mode = FAL_INTERFACE_CLOCK_MAC_MODE; - } - - return SW_OK; -} - -static sw_error_t -_isis_port_fiber_mode_set(a_uint32_t dev_id, fal_port_t port_id, fal_mac_fiber_config_t * config) -{ - sw_error_t rv; - a_uint32_t reg = 0, field; - - if (ISIS_MAC_0 == port_id) - { - HSL_REG_ENTRY_GET(rv, dev_id, PORT0_PAD_CTRL, 0, - (a_uint8_t *) (®), sizeof (a_uint32_t)); - } - else if (ISIS_MAC_6 == port_id) - { - HSL_REG_ENTRY_GET(rv, dev_id, PORT6_PAD_CTRL, 0, - (a_uint8_t *) (®), sizeof (a_uint32_t)); - } - else - { - return SW_BAD_PARAM; - } - SW_RTN_ON_ERROR(rv); - - SW_SET_REG_BY_FIELD(PORT0_PAD_CTRL, MAC0_RGMII_EN, 0, reg); - SW_SET_REG_BY_FIELD(PORT0_PAD_CTRL, MAC0_MAC_GMII_EN, 0, reg); - SW_SET_REG_BY_FIELD(PORT0_PAD_CTRL, MAC0_PHY_GMII_EN, 0, reg); - SW_SET_REG_BY_FIELD(PORT0_PAD_CTRL, MAC0_MAC_MII_EN, 0, reg); - SW_SET_REG_BY_FIELD(PORT0_PAD_CTRL, MAC0_PHY_MII_EN, 0, reg); - SW_SET_REG_BY_FIELD(PORT0_PAD_CTRL, MAC0_SGMII_EN, 1, reg); - - /* hardware suggestions: restore to defatult settings */ - SW_SET_REG_BY_FIELD(PORT0_PAD_CTRL, MAC0_RGMII_TXCLK_DELAY_EN, 0, reg); - SW_SET_REG_BY_FIELD(PORT0_PAD_CTRL, MAC0_RGMII_RXCLK_DELAY_EN, 0, reg); - SW_SET_REG_BY_FIELD(PORT0_PAD_CTRL, MAC0_RGMII_TXCLK_DELAY_SEL, 0, reg); - SW_SET_REG_BY_FIELD(PORT0_PAD_CTRL, MAC0_RGMII_RXCLK_DELAY_SEL, 0, reg); - SW_SET_REG_BY_FIELD(PORT0_PAD_CTRL, MAC0_PHY_GMII_TXCLK_SEL, 0, reg); - SW_SET_REG_BY_FIELD(PORT0_PAD_CTRL, MAC0_PHY_GMII_RXCLK_SEL, 0, reg); - SW_SET_REG_BY_FIELD(PORT0_PAD_CTRL, MAC0_PHY_MII_TXCLK_SEL, 0, reg); - SW_SET_REG_BY_FIELD(PORT0_PAD_CTRL, MAC0_PHY_MII_RXCLK_SEL, 0, reg); - SW_SET_REG_BY_FIELD(PORT0_PAD_CTRL, MAC0_MAC_GMII_TXCLK_SEL, 0, reg); - SW_SET_REG_BY_FIELD(PORT0_PAD_CTRL, MAC0_MAC_GMII_RXCLK_SEL, 0, reg); - SW_SET_REG_BY_FIELD(PORT0_PAD_CTRL, MAC0_MAC_MII_TXCLK_SEL, 0, reg); - SW_SET_REG_BY_FIELD(PORT0_PAD_CTRL, MAC0_MAC_MII_RXCLK_SEL, 0, reg); - - if (ISIS_MAC_0 == port_id) - { - HSL_REG_ENTRY_SET(rv, dev_id, PORT0_PAD_CTRL, 0, - (a_uint8_t *) (®), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - - /* only support one SGMII interface, so we need to disable another SGMII */ - field = 0; - HSL_REG_FIELD_SET(rv, dev_id, PORT6_PAD_CTRL, port_id, MAC6_SGMII_EN, - (a_uint8_t *) (&field), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - } - else - { - HSL_REG_ENTRY_SET(rv, dev_id, PORT6_PAD_CTRL, 0, - (a_uint8_t *) (®), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - - /* only support one SGMII interface, so we need to disable another SGMII */ - field = 0; - HSL_REG_FIELD_SET(rv, dev_id, PORT0_PAD_CTRL, port_id, MAC0_SGMII_EN, - (a_uint8_t *) (&field), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - } - - /* SGMII global settings, for all SGMII interfaces, now we fix all the values */ - /* TX/RX clock setting */ - HSL_REG_ENTRY_GET(rv, dev_id, PORT0_PAD_CTRL, 0, - (a_uint8_t *) (®), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - - SW_SET_REG_BY_FIELD(PORT0_PAD_CTRL, SGMII_CLK125M_RX_SEL, 1, reg); - SW_SET_REG_BY_FIELD(PORT0_PAD_CTRL, SGMII_CLK125M_TX_SEL, 0, reg); - - HSL_REG_ENTRY_SET(rv, dev_id, PORT0_PAD_CTRL, 0, - (a_uint8_t *) (®), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - - /* SGMII control register setting */ - HSL_REG_ENTRY_GET(rv, dev_id, SGMII_CTRL, 0, - (a_uint8_t *) (®), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - - SW_SET_REG_BY_FIELD(SGMII_CTRL, MODE_CTRL_25M, 0, reg); - SW_SET_REG_BY_FIELD(SGMII_CTRL, SGMII_FIBER_MODE, 3, reg); - SW_SET_REG_BY_FIELD(SGMII_CTRL, SGMII_EN_PLL, 0, reg); - SW_SET_REG_BY_FIELD(SGMII_CTRL, SGMII_EN_RX, 0, reg); - SW_SET_REG_BY_FIELD(SGMII_CTRL, SGMII_EN_TX, 0, reg); - SW_SET_REG_BY_FIELD(SGMII_CTRL, SGMII_EN_SD, 1, reg); - - HSL_REG_ENTRY_SET(rv, dev_id, SGMII_CTRL, 0, - (a_uint8_t *) (®), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - - /* Power on strip register setting */ - HSL_REG_ENTRY_GET(rv, dev_id, POWER_STRIP, 0, - (a_uint8_t *) (®), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - if (A_TRUE == config->auto_neg) - { - SW_SET_REG_BY_FIELD(POWER_STRIP, SERDES_AN_EN, 1, reg); - } - else - { - SW_SET_REG_BY_FIELD(POWER_STRIP, SERDES_AN_EN, 0, reg); - } - HSL_REG_ENTRY_SET(rv, dev_id, POWER_STRIP, 0, - (a_uint8_t *) (®), sizeof (a_uint32_t)); - - /* Port status register setting */ - HSL_REG_ENTRY_GET(rv, dev_id, PORT_STATUS, port_id, - (a_uint8_t *) (®), sizeof (a_uint32_t)); - - /* setting port status default configuration */ - SW_SET_REG_BY_FIELD(PORT_STATUS, FLOW_LINK_EN, 0, reg); - SW_SET_REG_BY_FIELD(PORT_STATUS, LINK_EN, 0, reg); - SW_SET_REG_BY_FIELD(PORT_STATUS, RX_FLOW_EN, 1, reg); - SW_SET_REG_BY_FIELD(PORT_STATUS, TX_FLOW_EN, 1, reg); - SW_SET_REG_BY_FIELD(PORT_STATUS, DUPLEX_MODE, 1, reg); - SW_SET_REG_BY_FIELD(PORT_STATUS, RXMAC_EN, 1, reg); - SW_SET_REG_BY_FIELD(PORT_STATUS, TXMAC_EN, 1, reg); - SW_SET_REG_BY_FIELD(PORT_STATUS, SPEED_MODE, 2, reg); - if (A_TRUE == config->auto_neg) - { - SW_SET_REG_BY_FIELD(PORT_STATUS, LINK_EN, 1, reg); - } - else - { - SW_SET_REG_BY_FIELD(PORT_STATUS, LINK_EN, 0, reg); - } - - HSL_REG_ENTRY_SET(rv, dev_id, PORT_STATUS, port_id, - (a_uint8_t *) (®), sizeof (a_uint32_t)); - return rv; -} - -static sw_error_t -_isis_port_fiber_mode_get(a_uint32_t dev_id, fal_port_t port_id, fal_mac_fiber_config_t * config) -{ - sw_error_t rv; - a_uint32_t reg = 0, field; - - if (ISIS_MAC_0 == port_id) - { - /* nothing to do */ - } - else if (ISIS_MAC_6 == port_id) - { - /* nothing to do */ - } - else - { - return SW_BAD_PARAM; - } - - HSL_REG_ENTRY_GET(rv, dev_id, POWER_STRIP, 0, - (a_uint8_t *) (®), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - - SW_GET_FIELD_BY_REG(POWER_STRIP, SERDES_AN_EN, field, reg); - if (field) - { - config->auto_neg = A_TRUE; - } - else - { - config->auto_neg = A_FALSE; - } - - return SW_OK; -} - -static sw_error_t -_isis_port_default_mode_set(a_uint32_t dev_id, fal_port_t port_id) -{ - sw_error_t rv; - a_uint32_t reg = 0; - - if (ISIS_MAC_0 == port_id) - { - HSL_REG_ENTRY_GET(rv, dev_id, PORT0_PAD_CTRL, 0, - (a_uint8_t *) (®), sizeof (a_uint32_t)); - } - else if (ISIS_MAC_5 == port_id) - { - HSL_REG_ENTRY_GET(rv, dev_id, PORT5_PAD_CTRL, 0, - (a_uint8_t *) (®), sizeof (a_uint32_t)); - } - else if (ISIS_MAC_6 == port_id) - { - HSL_REG_ENTRY_GET(rv, dev_id, PORT6_PAD_CTRL, 0, - (a_uint8_t *) (®), sizeof (a_uint32_t)); - } - else - { - return SW_BAD_PARAM; - } - SW_RTN_ON_ERROR(rv); - - SW_SET_REG_BY_FIELD(PORT0_PAD_CTRL, MAC0_RGMII_EN, 0, reg); - SW_SET_REG_BY_FIELD(PORT0_PAD_CTRL, MAC0_MAC_GMII_EN, 0, reg); - SW_SET_REG_BY_FIELD(PORT0_PAD_CTRL, MAC0_PHY_GMII_EN, 0, reg); - SW_SET_REG_BY_FIELD(PORT0_PAD_CTRL, MAC0_MAC_MII_EN, 0, reg); - SW_SET_REG_BY_FIELD(PORT0_PAD_CTRL, MAC0_PHY_MII_EN, 0, reg); - SW_SET_REG_BY_FIELD(PORT0_PAD_CTRL, MAC0_SGMII_EN, 0, reg); - - /* hardware suggestions: restore to defatult settings */ - SW_SET_REG_BY_FIELD(PORT0_PAD_CTRL, MAC0_RGMII_TXCLK_DELAY_EN, 0, reg); - SW_SET_REG_BY_FIELD(PORT0_PAD_CTRL, MAC0_RGMII_RXCLK_DELAY_EN, 0, reg); - SW_SET_REG_BY_FIELD(PORT0_PAD_CTRL, MAC0_RGMII_TXCLK_DELAY_SEL, 0, reg); - SW_SET_REG_BY_FIELD(PORT0_PAD_CTRL, MAC0_RGMII_RXCLK_DELAY_SEL, 0, reg); - SW_SET_REG_BY_FIELD(PORT0_PAD_CTRL, MAC0_PHY_GMII_TXCLK_SEL, 0, reg); - SW_SET_REG_BY_FIELD(PORT0_PAD_CTRL, MAC0_PHY_GMII_RXCLK_SEL, 0, reg); - SW_SET_REG_BY_FIELD(PORT0_PAD_CTRL, MAC0_PHY_MII_TXCLK_SEL, 0, reg); - SW_SET_REG_BY_FIELD(PORT0_PAD_CTRL, MAC0_PHY_MII_RXCLK_SEL, 0, reg); - SW_SET_REG_BY_FIELD(PORT0_PAD_CTRL, MAC0_MAC_GMII_TXCLK_SEL, 0, reg); - SW_SET_REG_BY_FIELD(PORT0_PAD_CTRL, MAC0_MAC_GMII_RXCLK_SEL, 0, reg); - SW_SET_REG_BY_FIELD(PORT0_PAD_CTRL, MAC0_MAC_MII_TXCLK_SEL, 0, reg); - SW_SET_REG_BY_FIELD(PORT0_PAD_CTRL, MAC0_MAC_MII_RXCLK_SEL, 0, reg); - - if (ISIS_MAC_0 == port_id) - { - HSL_REG_ENTRY_SET(rv, dev_id, PORT0_PAD_CTRL, 0, - (a_uint8_t *) (®), sizeof (a_uint32_t)); - } - else if (ISIS_MAC_5 == port_id) - { - HSL_REG_ENTRY_SET(rv, dev_id, PORT5_PAD_CTRL, 0, - (a_uint8_t *) (®), sizeof (a_uint32_t)); - } - else - { - HSL_REG_ENTRY_SET(rv, dev_id, PORT6_PAD_CTRL, 0, - (a_uint8_t *) (®), sizeof (a_uint32_t)); - } - - return rv; -} - -static sw_error_t -_isis_interface_mac_mode_set(a_uint32_t dev_id, fal_port_t port_id, fal_mac_config_t * config) -{ - sw_error_t rv; - - HSL_DEV_ID_CHECK(dev_id); - - if (FAL_MAC_MODE_RGMII == config->mac_mode) - { - rv = _isis_port_rgmii_mode_set(dev_id, port_id, &(config->config.rgmii)); - } - else if (FAL_MAC_MODE_GMII == config->mac_mode) - { - rv = _isis_port_gmii_mode_set(dev_id, port_id, &(config->config.gmii)); - } - else if (FAL_MAC_MODE_MII == config->mac_mode) - { - rv = _isis_port_mii_mode_set(dev_id, port_id, &(config->config.mii)); - } - else if (FAL_MAC_MODE_SGMII == config->mac_mode) - { - rv = _isis_port_sgmii_mode_set(dev_id, port_id, &(config->config.sgmii)); - } - else if (FAL_MAC_MODE_FIBER == config->mac_mode) - { - rv = _isis_port_fiber_mode_set(dev_id, port_id, &(config->config.fiber)); - } - else if (FAL_MAC_MODE_DEFAULT == config->mac_mode) - { - rv = _isis_port_default_mode_set(dev_id, port_id); - } - else - { - return SW_BAD_PARAM; - } - - return rv; -} - -static sw_error_t -_isis_interface_mac_mode_get(a_uint32_t dev_id, fal_port_t port_id, fal_mac_config_t * config) -{ - sw_error_t rv; - a_uint32_t reg = 0, field, field2; - - HSL_DEV_ID_CHECK(dev_id); - - if (ISIS_MAC_0 == port_id) - { - HSL_REG_ENTRY_GET(rv, dev_id, PORT0_PAD_CTRL, 0, - (a_uint8_t *) (®), sizeof (a_uint32_t)); - } - else if (ISIS_MAC_5 == port_id) - { - HSL_REG_ENTRY_GET(rv, dev_id, PORT5_PAD_CTRL, 0, - (a_uint8_t *) (®), sizeof (a_uint32_t)); - } - else if (ISIS_MAC_6 == port_id) - { - HSL_REG_ENTRY_GET(rv, dev_id, PORT6_PAD_CTRL, 0, - (a_uint8_t *) (®), sizeof (a_uint32_t)); - } - else - { - return SW_BAD_PARAM; - } - SW_RTN_ON_ERROR(rv); - - aos_mem_zero(config, sizeof(fal_interface_mac_mode_t)); - - SW_GET_FIELD_BY_REG(PORT0_PAD_CTRL, MAC0_RGMII_EN, field, reg); - if (field) - { - config->mac_mode = FAL_MAC_MODE_RGMII; - rv = _isis_port_rgmii_mode_get(dev_id, port_id, &(config->config.rgmii)); - return rv; - } - - SW_GET_FIELD_BY_REG(PORT0_PAD_CTRL, MAC0_MAC_GMII_EN, field, reg); - SW_GET_FIELD_BY_REG(PORT0_PAD_CTRL, MAC0_PHY_GMII_EN, field2, reg); - if (field || field2) - { - config->mac_mode = FAL_MAC_MODE_GMII; - rv = _isis_port_gmii_mode_get(dev_id, port_id, &(config->config.gmii)); - return rv; - } - - SW_GET_FIELD_BY_REG(PORT0_PAD_CTRL, MAC0_MAC_MII_EN, field, reg); - SW_GET_FIELD_BY_REG(PORT0_PAD_CTRL, MAC0_PHY_MII_EN, field2, reg); - if (field || field2) - { - config->mac_mode = FAL_MAC_MODE_MII; - rv = _isis_port_mii_mode_get(dev_id, port_id, &(config->config.mii)); - return rv; - } - - SW_GET_FIELD_BY_REG(PORT0_PAD_CTRL, MAC0_SGMII_EN, field, reg); - if (field) - { - HSL_REG_ENTRY_GET(rv, dev_id, SGMII_CTRL, 0, - (a_uint8_t *) (®), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - - SW_GET_FIELD_BY_REG(SGMII_CTRL, SGMII_FIBER_MODE, field, reg); - if (3 == field) - { - config->mac_mode = FAL_MAC_MODE_FIBER; - rv = _isis_port_fiber_mode_get(dev_id, port_id, &(config->config.fiber)); - } - else - { - config->mac_mode = FAL_MAC_MODE_SGMII; - rv = _isis_port_sgmii_mode_get(dev_id, port_id, &(config->config.sgmii)); - } - return rv; - } - - config->mac_mode = FAL_MAC_MODE_DEFAULT; - return SW_OK; -} - -static sw_error_t -_isis_interface_phy_mode_set(a_uint32_t dev_id, a_uint32_t phy_id, fal_phy_config_t * config) -{ - sw_error_t rv; - a_uint16_t data; - a_bool_t tx_delay_cmd, rx_delay_cmd; - hsl_phy_ops_t *phy_drv; - a_uint32_t reg, rgmii_mode, tx_delay = 2, port_id; - - HSL_DEV_ID_CHECK(dev_id); - - /* only PHY4 support mode setting */ - if (ISIS_PHY_MODE_PHY_ID != phy_id) - { - return SW_BAD_PARAM; - } - - port_id = qca_ssdk_phy_addr_to_port(dev_id, phy_id); - SW_RTN_ON_NULL (phy_drv = hsl_phy_api_ops_get(dev_id, port_id)); - if ((NULL == phy_drv->phy_debug_write) || (NULL == phy_drv->phy_debug_read)) - return SW_NOT_SUPPORTED; - - HSL_REG_ENTRY_GET(rv, dev_id, PORT6_PAD_CTRL, 0, - (a_uint8_t *) (®), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - - if (FAL_MAC_MODE_RGMII == config->mac_mode) - { - SW_SET_REG_BY_FIELD(PORT6_PAD_CTRL, PHY4_RGMII_EN, 1, reg); - SW_SET_REG_BY_FIELD(PORT6_PAD_CTRL, PHY4_GMII_EN, 0, reg); - SW_SET_REG_BY_FIELD(PORT6_PAD_CTRL, PHY4_MII_EN, 0, reg); - rgmii_mode = 1; - /* PHY TX delay */ - if (A_TRUE == config->txclk_delay_cmd) - { - tx_delay_cmd = A_TRUE; - tx_delay = config->txclk_delay_sel; - } - else - { - tx_delay_cmd = A_FALSE; - } - - /* PHY RX delay */ - if (A_TRUE == config->rxclk_delay_cmd) - { - rx_delay_cmd = A_TRUE; - } - else - { - rx_delay_cmd = A_FALSE; - } - } - else if (FAL_MAC_MODE_GMII == config->mac_mode) - { - SW_SET_REG_BY_FIELD(PORT6_PAD_CTRL, PHY4_RGMII_EN, 0, reg); - SW_SET_REG_BY_FIELD(PORT6_PAD_CTRL, PHY4_GMII_EN, 1, reg); - SW_SET_REG_BY_FIELD(PORT6_PAD_CTRL, PHY4_MII_EN, 0, reg); - rgmii_mode = 0; - tx_delay_cmd = A_FALSE; - rx_delay_cmd = A_FALSE; - } - else if (FAL_MAC_MODE_MII == config->mac_mode) - { - SW_SET_REG_BY_FIELD(PORT6_PAD_CTRL, PHY4_RGMII_EN, 0, reg); - SW_SET_REG_BY_FIELD(PORT6_PAD_CTRL, PHY4_GMII_EN, 0, reg); - SW_SET_REG_BY_FIELD(PORT6_PAD_CTRL, PHY4_MII_EN, 1, reg); - rgmii_mode = 0; - tx_delay_cmd = A_FALSE; - rx_delay_cmd = A_FALSE; - } - else if (FAL_MAC_MODE_DEFAULT == config->mac_mode) - { - SW_SET_REG_BY_FIELD(PORT6_PAD_CTRL, PHY4_RGMII_EN, 0, reg); - SW_SET_REG_BY_FIELD(PORT6_PAD_CTRL, PHY4_GMII_EN, 0, reg); - SW_SET_REG_BY_FIELD(PORT6_PAD_CTRL, PHY4_MII_EN, 0, reg); - - rgmii_mode = 0; - tx_delay_cmd = A_FALSE; - rx_delay_cmd = A_FALSE; - } - else - { - return SW_BAD_PARAM; - } - - HSL_REG_ENTRY_SET(rv, dev_id, PORT6_PAD_CTRL, 0, - (a_uint8_t *) (®), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - - /* PHY RGMII mode, debug register18 bit3 */ - data = phy_drv->phy_debug_read(dev_id, ISIS_PHY_MODE_PHY_ID, 18); - data &= 0xfff7UL; - data |= ((rgmii_mode & 0x1) << 3); - rv = phy_drv->phy_debug_write(dev_id, ISIS_PHY_MODE_PHY_ID, 18, data); - SW_RTN_ON_ERROR(rv); - - /* PHY TX delay command, debug regigster5 bit8 */ - data = phy_drv->phy_debug_read(dev_id, ISIS_PHY_MODE_PHY_ID, 5); - if (A_TRUE == tx_delay_cmd) - { - data |= 0x0100UL; - } - else - { - data &= 0xfeffUL; - } - rv = phy_drv->phy_debug_write(dev_id, ISIS_PHY_MODE_PHY_ID, 5, data); - SW_RTN_ON_ERROR(rv); - - /* PHY TX delay select, debug register11 bit-6 */ - data = phy_drv->phy_debug_read(dev_id, ISIS_PHY_MODE_PHY_ID, 11); - data &= 0xff9fUL; - data |= ((tx_delay & 0x3UL) << 5); - if (A_TRUE == tx_delay_cmd) - { - data |= 0x0100UL; - } - else - { - data &= 0xfeffUL; - } - rv = phy_drv->phy_debug_write(dev_id, ISIS_PHY_MODE_PHY_ID, 11, data); - SW_RTN_ON_ERROR(rv); - - /* PHY RX delay command, debug regigster0 bit15 */ - data = phy_drv->phy_debug_read(dev_id, ISIS_PHY_MODE_PHY_ID, 0); - if (A_TRUE == rx_delay_cmd) - { - data |= 0x8000UL; - } - else - { - data &= 0x7fffUL; - } - rv = phy_drv->phy_debug_write(dev_id, ISIS_PHY_MODE_PHY_ID, 0, data); - SW_RTN_ON_ERROR(rv); - - /* PHY RX delay select, now hardware not support */ - - return SW_OK; -} - -static sw_error_t -_isis_interface_phy_mode_get(a_uint32_t dev_id, a_uint32_t phy_id, fal_phy_config_t * config) -{ - sw_error_t rv; - a_uint16_t data; - a_uint32_t reg = 0, rgmii, gmii, mii, port_id; - hsl_phy_ops_t *phy_drv; - - HSL_DEV_ID_CHECK(dev_id); - - port_id = qca_ssdk_phy_addr_to_port(dev_id, phy_id); - SW_RTN_ON_NULL (phy_drv = hsl_phy_api_ops_get(dev_id, port_id)); - if (NULL == phy_drv->phy_debug_read) - return SW_NOT_SUPPORTED; - - /* only one PHY device support this */ - if (ISIS_PHY_MODE_PHY_ID != phy_id) - { - return SW_BAD_PARAM; - } - - aos_mem_zero(config, sizeof(fal_phy_config_t)); - - HSL_REG_ENTRY_GET(rv, dev_id, PORT6_PAD_CTRL, 0, - (a_uint8_t *) (®), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - - SW_GET_FIELD_BY_REG(PORT6_PAD_CTRL, PHY4_RGMII_EN, rgmii, reg); - SW_GET_FIELD_BY_REG(PORT6_PAD_CTRL, PHY4_GMII_EN, gmii, reg); - SW_GET_FIELD_BY_REG(PORT6_PAD_CTRL, PHY4_MII_EN, mii, reg); - - if ((rgmii) && (!gmii) && (!mii)) - { - config->mac_mode = FAL_MAC_MODE_RGMII; - data = phy_drv->phy_debug_read(dev_id, ISIS_PHY_MODE_PHY_ID, 5); - if (data & 0x0100) - { - config->txclk_delay_cmd = A_TRUE; - data = phy_drv->phy_debug_read(dev_id, ISIS_PHY_MODE_PHY_ID, 11); - config->txclk_delay_sel = (data >> 5) & 0x3UL; - } - else - { - config->txclk_delay_cmd = A_FALSE; - } - - data = phy_drv->phy_debug_read(dev_id, ISIS_PHY_MODE_PHY_ID, 0); - if (data & 0x8000) - { - config->rxclk_delay_cmd = A_TRUE; - } - else - { - config->rxclk_delay_cmd = A_FALSE; - } - } - else if ((!rgmii) && (gmii) && (!mii)) - { - config->mac_mode = FAL_MAC_MODE_GMII; - } - else if ((!rgmii) && (!gmii) && (mii)) - { - config->mac_mode = FAL_MAC_MODE_MII; - } - else - { - config->mac_mode = FAL_MAC_MODE_DEFAULT; - } - - return SW_OK; -} - -static sw_error_t -_isis_interface_mac_sgmii_set(a_uint32_t dev_id,a_uint32_t value) -{ - sw_error_t rv; - a_uint32_t reg; - - reg = value; - - HSL_REG_ENTRY_SET(rv, dev_id, SGMII_CTRL, 0, - (a_uint8_t *) (®), sizeof (a_uint32_t)); - - return rv; -} - -static sw_error_t -_isis_interface_mac_sgmii_get(a_uint32_t dev_id, a_uint32_t *value) -{ - sw_error_t rv; - a_uint32_t reg = 0; - - HSL_REG_ENTRY_GET(rv, dev_id, SGMII_CTRL, 0, - (a_uint8_t *) (®), sizeof (a_uint32_t)); - - SW_RTN_ON_ERROR(rv); - - *value = reg; - - return rv; -} - -static sw_error_t -_isis_interface_mac_pad_set(a_uint32_t dev_id,a_uint32_t port_num, a_uint32_t value) -{ - sw_error_t rv; - a_uint32_t reg; - - reg = value; - - switch (port_num) - { - case ISIS_MAC_0: - HSL_REG_ENTRY_SET(rv, dev_id, PORT0_PAD_CTRL, 0, - (a_uint8_t *) (®), sizeof (a_uint32_t)); - break; - case ISIS_MAC_5: - HSL_REG_ENTRY_SET(rv, dev_id, PORT5_PAD_CTRL, 0, - (a_uint8_t *) (®), sizeof (a_uint32_t)); - break; - case ISIS_MAC_6: - HSL_REG_ENTRY_SET(rv, dev_id, PORT6_PAD_CTRL, 0, - (a_uint8_t *) (®), sizeof (a_uint32_t)); - break; - default: - return SW_BAD_PARAM; - } - - return rv; -} - -static sw_error_t -_isis_interface_mac_pad_get(a_uint32_t dev_id,a_uint32_t port_num, a_uint32_t *value) -{ - sw_error_t rv; - a_uint32_t reg = 0; - - switch (port_num) - { - case ISIS_MAC_0: - HSL_REG_ENTRY_GET(rv, dev_id, PORT0_PAD_CTRL, 0, - (a_uint8_t *) (®), sizeof (a_uint32_t)); - break; - case ISIS_MAC_5: - HSL_REG_ENTRY_GET(rv, dev_id, PORT5_PAD_CTRL, 0, - (a_uint8_t *) (®), sizeof (a_uint32_t)); - break; - case ISIS_MAC_6: - HSL_REG_ENTRY_GET(rv, dev_id, PORT6_PAD_CTRL, 0, - (a_uint8_t *) (®), sizeof (a_uint32_t)); - break; - default: - return SW_BAD_PARAM; - } - SW_RTN_ON_ERROR(rv); - - *value = reg; - - return rv; -} - - - -/** - * @brief Set 802.3az status on a particular port. - * @param[in] dev_id device id - * @param[in] port_id port id - * @param[in] enable A_TRUE or A_FALSE - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -isis_port_3az_status_set(a_uint32_t dev_id, fal_port_t port_id, a_bool_t enable) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _isis_port_3az_status_set(dev_id, port_id, enable); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Get 802.3az status on a particular port. - * @param[in] dev_id device id - * @param[in] port_id port id - * @param[out] enable A_TRUE or A_FALSE - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -isis_port_3az_status_get(a_uint32_t dev_id, fal_port_t port_id, a_bool_t * enable) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _isis_port_3az_status_get(dev_id, port_id, enable); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Set interface mode on a particular MAC device. - * @param[in] dev_id device id - * @param[in] mca_id MAC device ID - * @param[in] config interface configuration - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -isis_interface_mac_mode_set(a_uint32_t dev_id, fal_port_t port_id, fal_mac_config_t * config) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _isis_interface_mac_mode_set(dev_id, port_id, config); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Get interface mode on a particular MAC device. - * @param[in] dev_id device id - * @param[in] mca_id MAC device ID - * @param[out] config interface configuration - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -isis_interface_mac_mode_get(a_uint32_t dev_id, fal_port_t port_id, fal_mac_config_t * config) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _isis_interface_mac_mode_get(dev_id, port_id, config); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Set interface phy mode on a particular PHY device. - * @param[in] dev_id device id - * @param[in] phy_id PHY device ID - * @param[in] config interface configuration - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -isis_interface_phy_mode_set(a_uint32_t dev_id, a_uint32_t phy_id, fal_phy_config_t * config) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _isis_interface_phy_mode_set(dev_id, phy_id, config); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Get interface phy mode on a particular PHY device. - * @param[in] dev_id device id - * @param[in] phy_id PHY device ID - * @param[out] config interface configuration - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -isis_interface_phy_mode_get(a_uint32_t dev_id, a_uint32_t phy_id, fal_phy_config_t * config) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _isis_interface_phy_mode_get(dev_id, phy_id, config); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Get mac pad configuration. - * @param[in] dev_id device id - * @param[in] port_num port num - * @param[out] config value - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -isis_interface_mac_pad_get(a_uint32_t dev_id,a_uint32_t port_num, a_uint32_t* value) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _isis_interface_mac_pad_get(dev_id, port_num, value); - HSL_API_UNLOCK; - return rv; -} - - -/** - * @brief Set mac pad configuration. - * @param[in] dev_id device id - * @param[in] port_num port num - * @param[in] config value - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -isis_interface_mac_pad_set(a_uint32_t dev_id,a_uint32_t port_num, a_uint32_t value) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _isis_interface_mac_pad_set(dev_id,port_num,value); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Get mac SGMII configuration. - * @param[in] dev_id device id - * @param[out] config value - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -isis_interface_mac_sgmii_get(a_uint32_t dev_id, a_uint32_t* value) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _isis_interface_mac_sgmii_get(dev_id, value); - HSL_API_UNLOCK; - return rv; -} - - -/** - * @brief Set mac SGMII configuration. - * @param[in] dev_id device id - * @param[in] config value - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -isis_interface_mac_sgmii_set(a_uint32_t dev_id, a_uint32_t value) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _isis_interface_mac_sgmii_set(dev_id, value); - HSL_API_UNLOCK; - return rv; -} - - -sw_error_t -isis_interface_ctrl_init(a_uint32_t dev_id) -{ - HSL_DEV_ID_CHECK(dev_id); - -#ifndef HSL_STANDALONG - { - hsl_api_t *p_api; - - SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id)); - - p_api->port_3az_status_set = isis_port_3az_status_set; - p_api->port_3az_status_get = isis_port_3az_status_get; - p_api->interface_mac_mode_set = isis_interface_mac_mode_set; - p_api->interface_mac_mode_get = isis_interface_mac_mode_get; - p_api->interface_phy_mode_set = isis_interface_phy_mode_set; - p_api->interface_phy_mode_get = isis_interface_phy_mode_get; - p_api->interface_mac_pad_get = isis_interface_mac_pad_get; - p_api->interface_mac_pad_set = isis_interface_mac_pad_set; - p_api->interface_mac_sgmii_get = isis_interface_mac_sgmii_get; - p_api->interface_mac_sgmii_set = isis_interface_mac_sgmii_set; - } -#endif - - return SW_OK; -} - -/** - * @} - */ - diff --git a/feeds/ipq807x/qca-ssdk/src/src/hsl/isis/isis_ip.c b/feeds/ipq807x/qca-ssdk/src/src/hsl/isis/isis_ip.c deleted file mode 100755 index f216add4f..000000000 --- a/feeds/ipq807x/qca-ssdk/src/src/hsl/isis/isis_ip.c +++ /dev/null @@ -1,2516 +0,0 @@ -/* - * Copyright (c) 2012, 2016, The Linux Foundation. All rights reserved. - * Permission to use, copy, modify, and/or distribute this software for - * any purpose with or without fee is hereby granted, provided that the - * above copyright notice and this permission notice appear in all copies. - * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES - * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR - * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES - * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN - * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT - * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. - */ - - -/** - * @defgroup isis_ip ISIS_IP - * @{ - */ - -#include "sw.h" -#include "hsl.h" -#include "hsl_dev.h" -#include "hsl_port_prop.h" -#include "isis_ip.h" -#include "isis_reg.h" - -#define ISIS_HOST_ENTRY_DATA0_ADDR 0x0e48 -#define ISIS_HOST_ENTRY_DATA1_ADDR 0x0e4c -#define ISIS_HOST_ENTRY_DATA2_ADDR 0x0e50 -#define ISIS_HOST_ENTRY_DATA3_ADDR 0x0e54 -#define ISIS_HOST_ENTRY_DATA4_ADDR 0x0e58 - -#define ISIS_HOST_ENTRY_FLUSH 1 -#define ISIS_HOST_ENTRY_ADD 2 -#define ISIS_HOST_ENTRY_DEL 3 -#define ISIS_HOST_ENTRY_NEXT 4 -#define ISIS_HOST_ENTRY_SEARCH 5 - -#define ISIS_ENTRY_ARP 3 - -#define ISIS_INTF_MAC_ADDR_NUM 8 -#define ISIS_INTF_MAC_TBL0_ADDR 0x5a900 -#define ISIS_INTF_MAC_TBL1_ADDR 0x5a904 -#define ISIS_INTF_MAC_TBL2_ADDR 0x5a908 -#define ISIS_INTF_MAC_EDIT0_ADDR 0x02000 -#define ISIS_INTF_MAC_EDIT1_ADDR 0x02004 -#define ISIS_INTF_MAC_EDIT2_ADDR 0x02008 - -#define ISIS_IP6_BASE_ADDR 0x0470 - -#define ISIS_HOST_ENTRY_NUM 128 - -#define ISIS_IP_COUTER_ADDR 0x2b000 - -static a_uint32_t isis_mac_snap[SW_MAX_NR_DEV] = { 0 }; -static fal_intf_mac_entry_t isis_intf_snap[SW_MAX_NR_DEV][ISIS_INTF_MAC_ADDR_NUM]; - -static void -_isis_ip_pt_learn_save(a_uint32_t dev_id, a_uint32_t * status) -{ - sw_error_t rv; - a_uint32_t data = 0; - - HSL_REG_ENTRY_GET(rv, dev_id, ROUTER_PTCTRL2, 0, - (a_uint8_t *) (&data), sizeof (a_uint32_t)); - if (SW_OK != rv) - { - return; - } - - *status = (data & 0x7f7f); - - data &= 0xffff8080; - HSL_REG_ENTRY_SET(rv, dev_id, ROUTER_PTCTRL2, 0, - (a_uint8_t *) (&data), sizeof (a_uint32_t)); - return; -} - -static void -_isis_ip_pt_learn_restore(a_uint32_t dev_id, a_uint32_t status) -{ - sw_error_t rv; - a_uint32_t data = 0; - - HSL_REG_ENTRY_GET(rv, dev_id, ROUTER_PTCTRL2, 0, - (a_uint8_t *) (&data), sizeof (a_uint32_t)); - if (SW_OK != rv) - { - return; - } - - data &= 0xffff8080; - data |= (status & 0x7f7f); - - HSL_REG_ENTRY_SET(rv, dev_id, ROUTER_PTCTRL2, 0, - (a_uint8_t *) (&data), sizeof (a_uint32_t)); - return; -} - -static sw_error_t -_isis_ip_feature_check(a_uint32_t dev_id) -{ - sw_error_t rv; - a_uint32_t entry = 0; - - HSL_REG_FIELD_GET(rv, dev_id, MASK_CTL, 0, DEVICE_ID, - (a_uint8_t *) (&entry), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - - if (S17_DEVICE_ID == entry) - { - return SW_OK; - } - else - { - return SW_NOT_SUPPORTED; - } -} - -static sw_error_t -_isis_ip_counter_get(a_uint32_t dev_id, a_uint32_t cnt_id, - a_uint32_t counter[2]) -{ - sw_error_t rv; - a_uint32_t i, addr; - - addr = ISIS_IP_COUTER_ADDR + (cnt_id << 3); - for (i = 0; i < 2; i++) - { - HSL_REG_ENTRY_GEN_GET(rv, dev_id, addr, sizeof (a_uint32_t), - (a_uint8_t *) (&(counter[i])), - sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - - addr += 4; - } - - return SW_OK; -} - -static sw_error_t -_isis_host_entry_commit(a_uint32_t dev_id, a_uint32_t entry_type, a_uint32_t op) -{ - a_uint32_t busy = 1, i = 0x100, entry = 0, j, try_num; - a_uint32_t learn_status = 0; - sw_error_t rv; - - while (busy && --i) - { - HSL_REG_ENTRY_GET(rv, dev_id, HOST_ENTRY4, 0, (a_uint8_t *) (&entry), - sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - SW_GET_FIELD_BY_REG(HOST_ENTRY4, TBL_BUSY, busy, entry); - aos_udelay(500); - } - - if (i == 0) - { - printk("%s BUSY\n", __FUNCTION__); - return SW_BUSY; - } - - SW_SET_REG_BY_FIELD(HOST_ENTRY4, TBL_BUSY, 1, entry); - SW_SET_REG_BY_FIELD(HOST_ENTRY4, TBL_SEL, entry_type, entry); - SW_SET_REG_BY_FIELD(HOST_ENTRY4, ENTRY_FUNC, op, entry); - - HSL_REG_ENTRY_SET(rv, dev_id, HOST_ENTRY4, 0, (a_uint8_t *) (&entry), - sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - - /* hardware requirements, we should disable ARP learn at first */ - /* and maybe we should try several times... */ - _isis_ip_pt_learn_save(dev_id, &learn_status); - if (learn_status) - { - try_num = 10; - } - else - { - try_num = 1; - } - - for (j = 0; j < try_num; j++) - { - busy = 1; - i = 0x100; - while (busy && --i) - { - HSL_REG_ENTRY_GET(rv, dev_id, HOST_ENTRY4, 0, (a_uint8_t *) (&entry), - sizeof (a_uint32_t)); - if (SW_OK != rv) - { - _isis_ip_pt_learn_restore(dev_id, learn_status); - return rv; - } - SW_GET_FIELD_BY_REG(HOST_ENTRY4, TBL_BUSY, busy, entry); - aos_udelay(500); - } - - if (i == 0) - { - _isis_ip_pt_learn_restore(dev_id, learn_status); - printk("%s BUSY\n", __FUNCTION__); - return SW_BUSY; - } - - /* hardware requirement, we should read again... */ - HSL_REG_ENTRY_GET(rv, dev_id, HOST_ENTRY4, 0, (a_uint8_t *) (&entry), - sizeof (a_uint32_t)); - if (SW_OK != rv) - { - _isis_ip_pt_learn_restore(dev_id, learn_status); - return rv; - } - - /* operation success...... */ - SW_GET_FIELD_BY_REG(HOST_ENTRY4, TBL_STAUS, busy, entry); - if (busy) - { - _isis_ip_pt_learn_restore(dev_id, learn_status); - return SW_OK; - } - } - - _isis_ip_pt_learn_restore(dev_id, learn_status); - if (ISIS_HOST_ENTRY_NEXT == op) - { - return SW_NO_MORE; - } - else if (ISIS_HOST_ENTRY_SEARCH == op) - { - return SW_NOT_FOUND; - } - else if (ISIS_HOST_ENTRY_DEL == op) - { - return SW_NOT_FOUND; - } - else - { - return SW_FAIL; - } -} - -static sw_error_t -_isis_ip_intf_sw_to_hw(a_uint32_t dev_id, fal_host_entry_t * entry, - a_uint32_t * hw_intf) -{ - sw_error_t rv; - a_uint32_t addr, lvid, hvid, tbl[3] = {0}, i; - a_uint32_t sw_intf = entry->intf_id; - a_uint32_t vid_offset; - - for (i = 0; i < ISIS_INTF_MAC_ADDR_NUM; i++) - { - if (isis_mac_snap[dev_id] & (0x1 << i)) - { - addr = ISIS_INTF_MAC_TBL0_ADDR + (i << 4) + 4; - HSL_REG_ENTRY_GEN_GET(rv, dev_id, addr, sizeof (a_uint32_t), - (a_uint8_t *) (&(tbl[1])), - sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - - addr = ISIS_INTF_MAC_TBL0_ADDR + (i << 4) + 8; - HSL_REG_ENTRY_GEN_GET(rv, dev_id, addr, sizeof (a_uint32_t), - (a_uint8_t *) (&(tbl[2])), - sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - - SW_GET_FIELD_BY_REG(INTF_ADDR_ENTRY1, VID_HIGH0, hvid, tbl[1]); - SW_GET_FIELD_BY_REG(INTF_ADDR_ENTRY2, VID_HIGH1, lvid, tbl[2]); - hvid |= ((lvid & 0xff) << 4); - - SW_GET_FIELD_BY_REG(INTF_ADDR_ENTRY1, VID_LOW, lvid, tbl[1]); - - if ((lvid <= sw_intf) && (hvid >= sw_intf)) - { - vid_offset = entry->expect_vid ? (entry->expect_vid - lvid) : (sw_intf - lvid); - *hw_intf = (vid_offset << 3) | i; - return SW_OK; - } - } - } - - return SW_BAD_PARAM; -} - -static sw_error_t -_isis_ip_intf_hw_to_sw(a_uint32_t dev_id, a_uint32_t hw_intf, - a_uint32_t * sw_intf) -{ - sw_error_t rv; - a_uint32_t addr, lvid, tbl = 0, i; - - i = hw_intf & 0x7; - - addr = ISIS_INTF_MAC_TBL0_ADDR + (i << 4) + 4; - HSL_REG_ENTRY_GEN_GET(rv, dev_id, addr, sizeof (a_uint32_t), - (a_uint8_t *) (&tbl), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - - SW_GET_FIELD_BY_REG(INTF_ADDR_ENTRY1, VID_LOW, lvid, tbl); - *sw_intf = lvid + (hw_intf >> 3); - - return SW_OK; -} - -static sw_error_t -_isis_ip_age_time_set(a_uint32_t dev_id, a_uint32_t * time) -{ - sw_error_t rv; - a_uint32_t data; - - if (255 < ((*time + 5) / 6)) - { - return SW_BAD_PARAM; - } - - data = ((*time + 5) / 6); - *time = data * 6; - - HSL_REG_FIELD_SET(rv, dev_id, ROUTER_CTRL, 0, ARP_AGE_TIME, - (a_uint8_t *) (&data), sizeof (a_uint32_t)); - return rv; -} - -static sw_error_t -_isis_ip_age_time_get(a_uint32_t dev_id, a_uint32_t * time) -{ - sw_error_t rv; - a_uint32_t data = 0; - - HSL_REG_FIELD_GET(rv, dev_id, ROUTER_CTRL, 0, ARP_AGE_TIME, - (a_uint8_t *) (&data), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - - *time = data * 6; - return SW_OK; -} - -static sw_error_t -_isis_host_sw_to_hw(a_uint32_t dev_id, fal_host_entry_t * entry, - a_uint32_t reg[]) -{ - sw_error_t rv; - a_uint32_t data; - - if (FAL_IP_IP4_ADDR & entry->flags) - { - reg[0] = entry->ip4_addr; - } - - if (FAL_IP_IP6_ADDR & entry->flags) - { - return SW_NOT_SUPPORTED; - } - - SW_SET_REG_BY_FIELD(HOST_ENTRY1, MAC_ADDR2, entry->mac_addr.uc[2], reg[1]); - SW_SET_REG_BY_FIELD(HOST_ENTRY1, MAC_ADDR3, entry->mac_addr.uc[3], reg[1]); - SW_SET_REG_BY_FIELD(HOST_ENTRY1, MAC_ADDR4, entry->mac_addr.uc[4], reg[1]); - SW_SET_REG_BY_FIELD(HOST_ENTRY1, MAC_ADDR5, entry->mac_addr.uc[5], reg[1]); - SW_SET_REG_BY_FIELD(HOST_ENTRY2, MAC_ADDR0, entry->mac_addr.uc[0], reg[2]); - SW_SET_REG_BY_FIELD(HOST_ENTRY2, MAC_ADDR1, entry->mac_addr.uc[1], reg[2]); - - rv = _isis_ip_intf_sw_to_hw(dev_id, entry/*was:->intf_id*/, &data); - SW_RTN_ON_ERROR(rv); - SW_SET_REG_BY_FIELD(HOST_ENTRY2, INTF_ID, data, reg[2]); - - if (A_TRUE != hsl_port_prop_check(dev_id, entry->port_id, HSL_PP_INCL_CPU)) - { - return SW_BAD_PARAM; - } - SW_SET_REG_BY_FIELD(HOST_ENTRY2, SRC_PORT, entry->port_id, reg[2]); - - if (FAL_IP_CPU_ADDR & entry->flags) - { - SW_SET_REG_BY_FIELD(HOST_ENTRY2, CPU_ADDR, 1, reg[2]); - } - - SW_SET_REG_BY_FIELD(HOST_ENTRY3, AGE_FLAG, entry->status, reg[3]); - - if ((A_TRUE == entry->mirror_en) && (FAL_MAC_FRWRD != entry->action)) - { - return SW_NOT_SUPPORTED; - } - - if (A_TRUE == entry->counter_en) - { - SW_SET_REG_BY_FIELD(HOST_ENTRY3, CNT_EN, 1, reg[3]); - SW_SET_REG_BY_FIELD(HOST_ENTRY3, CNT_IDX, entry->counter_id, reg[3]); - } - - if (FAL_MAC_DROP == entry->action) - { - SW_SET_REG_BY_FIELD(HOST_ENTRY2, SRC_PORT, 7, reg[2]); - SW_SET_REG_BY_FIELD(HOST_ENTRY3, ACTION, 3, reg[3]); - } - else if (FAL_MAC_RDT_TO_CPU == entry->action) - { - SW_SET_REG_BY_FIELD(HOST_ENTRY3, ACTION, 1, reg[3]); - } - else if (FAL_MAC_CPY_TO_CPU == entry->action) - { - SW_SET_REG_BY_FIELD(HOST_ENTRY3, ACTION, 2, reg[3]); - } - else - { - if (A_TRUE == entry->mirror_en) - { - SW_SET_REG_BY_FIELD(HOST_ENTRY3, ACTION, 0, reg[3]); - } - else - { - SW_SET_REG_BY_FIELD(HOST_ENTRY3, ACTION, 3, reg[3]); - } - } - - return SW_OK; -} - -static sw_error_t -_isis_host_hw_to_sw(a_uint32_t dev_id, a_uint32_t reg[], - fal_host_entry_t * entry) -{ - sw_error_t rv; - a_uint32_t data, cnt[2] = {0}; - - SW_GET_FIELD_BY_REG(HOST_ENTRY3, IP_VER, data, reg[3]); - if (data) - { - entry->ip6_addr.ul[0] = reg[0]; - entry->flags |= FAL_IP_IP6_ADDR; - } - else - { - entry->ip4_addr = reg[0]; - entry->flags |= FAL_IP_IP4_ADDR; - } - - SW_GET_FIELD_BY_REG(HOST_ENTRY1, MAC_ADDR2, entry->mac_addr.uc[2], reg[1]); - SW_GET_FIELD_BY_REG(HOST_ENTRY1, MAC_ADDR3, entry->mac_addr.uc[3], reg[1]); - SW_GET_FIELD_BY_REG(HOST_ENTRY1, MAC_ADDR4, entry->mac_addr.uc[4], reg[1]); - SW_GET_FIELD_BY_REG(HOST_ENTRY1, MAC_ADDR5, entry->mac_addr.uc[5], reg[1]); - SW_GET_FIELD_BY_REG(HOST_ENTRY2, MAC_ADDR0, entry->mac_addr.uc[0], reg[2]); - SW_GET_FIELD_BY_REG(HOST_ENTRY2, MAC_ADDR1, entry->mac_addr.uc[1], reg[2]); - - SW_GET_FIELD_BY_REG(HOST_ENTRY2, INTF_ID, data, reg[2]); - rv = _isis_ip_intf_hw_to_sw(dev_id, data, &(entry->intf_id)); - SW_RTN_ON_ERROR(rv); - - SW_GET_FIELD_BY_REG(HOST_ENTRY2, SRC_PORT, entry->port_id, reg[2]); - - SW_GET_FIELD_BY_REG(HOST_ENTRY2, CPU_ADDR, data, reg[2]); - if (data) - { - entry->flags |= FAL_IP_CPU_ADDR; - } - - SW_GET_FIELD_BY_REG(HOST_ENTRY3, AGE_FLAG, entry->status, reg[3]); - - SW_GET_FIELD_BY_REG(HOST_ENTRY3, CNT_EN, data, reg[3]); - if (data) - { - entry->counter_en = A_TRUE; - SW_GET_FIELD_BY_REG(HOST_ENTRY3, CNT_IDX, entry->counter_id, reg[3]); - - rv = _isis_ip_counter_get(dev_id, entry->counter_id, cnt); - SW_RTN_ON_ERROR(rv); - - entry->packet = cnt[0]; - entry->byte = cnt[1]; - } - else - { - entry->counter_en = A_FALSE; - } - - SW_GET_FIELD_BY_REG(HOST_ENTRY3, PPPOE_EN, data, reg[3]); - if (data) - { - entry->pppoe_en = A_TRUE; - SW_GET_FIELD_BY_REG(HOST_ENTRY3, PPPOE_IDX, data, reg[3]); - entry->pppoe_id = data; - } - else - { - entry->pppoe_en = A_FALSE; - } - - if (7 == entry->port_id) - { - entry->port_id = 0; - entry->action = FAL_MAC_DROP; - } - else - { - SW_GET_FIELD_BY_REG(HOST_ENTRY3, ACTION, data, reg[3]); - entry->action = FAL_MAC_FRWRD; - if (0 == data) - { - entry->mirror_en = A_TRUE; - } - else if (1 == data) - { - entry->action = FAL_MAC_RDT_TO_CPU; - } - else if (2 == data) - { - entry->action = FAL_MAC_CPY_TO_CPU; - } - } - - return SW_OK; -} - -static sw_error_t -_isis_host_down_to_hw(a_uint32_t dev_id, a_uint32_t reg[]) -{ - sw_error_t rv; - a_uint32_t i, addr; - - for (i = 0; i < 5; i++) - { - addr = ISIS_HOST_ENTRY_DATA0_ADDR + (i << 2); - HSL_REG_ENTRY_GEN_SET(rv, dev_id, addr, sizeof (a_uint32_t), - (a_uint8_t *) (®[i]), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - } - - return SW_OK; -} - -static sw_error_t -_isis_host_up_to_sw(a_uint32_t dev_id, a_uint32_t reg[]) -{ - sw_error_t rv; - a_uint32_t i, addr; - - for (i = 0; i < 5; i++) - { - addr = ISIS_HOST_ENTRY_DATA0_ADDR + (i << 2); - HSL_REG_ENTRY_GEN_GET(rv, dev_id, addr, sizeof (a_uint32_t), - (a_uint8_t *) (®[i]), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - } - - return SW_OK; -} - -static sw_error_t -_isis_ip_host_add(a_uint32_t dev_id, fal_host_entry_t * entry) -{ - sw_error_t rv; - a_uint32_t reg[5] = { 0 }; - - HSL_DEV_ID_CHECK(dev_id); - - rv = _isis_ip_feature_check(dev_id); - SW_RTN_ON_ERROR(rv); - - rv = _isis_host_sw_to_hw(dev_id, entry, reg); - SW_RTN_ON_ERROR(rv); - - rv = _isis_host_down_to_hw(dev_id, reg); - SW_RTN_ON_ERROR(rv); - - rv = _isis_host_entry_commit(dev_id, ISIS_ENTRY_ARP, ISIS_HOST_ENTRY_ADD); - SW_RTN_ON_ERROR(rv); - - HSL_REG_ENTRY_GET(rv, dev_id, HOST_ENTRY4, 0, (a_uint8_t *) (®[4]), - sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - - SW_GET_FIELD_BY_REG(HOST_ENTRY4, TBL_IDX, entry->entry_id, reg[4]); - return SW_OK; -} - -static sw_error_t -_isis_ip_host_del(a_uint32_t dev_id, a_uint32_t del_mode, - fal_host_entry_t * entry) -{ - sw_error_t rv; - a_uint32_t data, reg[5] = { 0 }, op = ISIS_HOST_ENTRY_FLUSH; - - HSL_DEV_ID_CHECK(dev_id); - - rv = _isis_ip_feature_check(dev_id); - SW_RTN_ON_ERROR(rv); - - if (FAL_IP_ENTRY_ID_EN & del_mode) - { - return SW_NOT_SUPPORTED; - } - - if (FAL_IP_ENTRY_IPADDR_EN & del_mode) - { - op = ISIS_HOST_ENTRY_DEL; - if (FAL_IP_IP4_ADDR & entry->flags) - { - reg[0] = entry->ip4_addr; - } - - if (FAL_IP_IP6_ADDR & entry->flags) - { - return SW_NOT_SUPPORTED; - } - } - - if (FAL_IP_ENTRY_INTF_EN & del_mode) - { - rv = _isis_ip_intf_sw_to_hw(dev_id, entry/*was:->intf_id*/, &data); - SW_RTN_ON_ERROR(rv); - - SW_SET_REG_BY_FIELD(HOST_ENTRY4, SPEC_VID, 1, reg[4]); - SW_SET_REG_BY_FIELD(HOST_ENTRY2, INTF_ID, data, reg[2]); - } - - if (FAL_IP_ENTRY_PORT_EN & del_mode) - { - SW_SET_REG_BY_FIELD(HOST_ENTRY4, SPEC_SP, 1, reg[4]); - SW_SET_REG_BY_FIELD(HOST_ENTRY2, SRC_PORT, entry->port_id, reg[2]); - } - - if (FAL_IP_ENTRY_STATUS_EN & del_mode) - { - SW_SET_REG_BY_FIELD(HOST_ENTRY4, SPEC_STATUS, 1, reg[4]); - SW_SET_REG_BY_FIELD(HOST_ENTRY3, AGE_FLAG, entry->status, reg[3]); - } - - rv = _isis_host_down_to_hw(dev_id, reg); - SW_RTN_ON_ERROR(rv); - - rv = _isis_host_entry_commit(dev_id, ISIS_ENTRY_ARP, op); - return rv; -} - -static sw_error_t -_isis_ip_host_get(a_uint32_t dev_id, a_uint32_t get_mode, - fal_host_entry_t * entry) -{ - sw_error_t rv; - a_uint32_t reg[5] = { 0 }; - - HSL_DEV_ID_CHECK(dev_id); - - rv = _isis_ip_feature_check(dev_id); - SW_RTN_ON_ERROR(rv); - - if (FAL_IP_ENTRY_IPADDR_EN != get_mode) - { - return SW_NOT_SUPPORTED; - } - - if (FAL_IP_IP4_ADDR & entry->flags) - { - reg[0] = entry->ip4_addr; - } - else if (FAL_IP_IP6_ADDR & entry->flags) - { - return SW_NOT_SUPPORTED; - } - - rv = _isis_host_down_to_hw(dev_id, reg); - SW_RTN_ON_ERROR(rv); - - rv = _isis_host_entry_commit(dev_id, ISIS_ENTRY_ARP, - ISIS_HOST_ENTRY_SEARCH); - SW_RTN_ON_ERROR(rv); - - rv = _isis_host_up_to_sw(dev_id, reg); - SW_RTN_ON_ERROR(rv); - - aos_mem_zero(entry, sizeof (fal_host_entry_t)); - - rv = _isis_host_hw_to_sw(dev_id, reg, entry); - SW_RTN_ON_ERROR(rv); - - if (!(entry->status)) - { - return SW_NOT_FOUND; - } - - HSL_REG_ENTRY_GET(rv, dev_id, HOST_ENTRY4, 0, (a_uint8_t *) (®[4]), - sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - - SW_GET_FIELD_BY_REG(HOST_ENTRY4, TBL_IDX, entry->entry_id, reg[4]); - return SW_OK; -} - -static sw_error_t -_isis_ip_host_next(a_uint32_t dev_id, a_uint32_t next_mode, - fal_host_entry_t * entry) -{ - sw_error_t rv; - a_uint32_t idx, data, reg[5] = { 0 }; - - HSL_DEV_ID_CHECK(dev_id); - - rv = _isis_ip_feature_check(dev_id); - SW_RTN_ON_ERROR(rv); - - if (FAL_NEXT_ENTRY_FIRST_ID == entry->entry_id) - { - idx = ISIS_HOST_ENTRY_NUM - 1; - } - else - { - if ((ISIS_HOST_ENTRY_NUM - 1) == entry->entry_id) - { - return SW_NO_MORE; - } - else - { - idx = entry->entry_id; - } - } - - SW_SET_REG_BY_FIELD(HOST_ENTRY4, TBL_IDX, idx, reg[4]); - - if (FAL_IP_ENTRY_INTF_EN & next_mode) - { - rv = _isis_ip_intf_sw_to_hw(dev_id, entry/*was:->intf_id*/, &data); - SW_RTN_ON_ERROR(rv); - - SW_SET_REG_BY_FIELD(HOST_ENTRY4, SPEC_VID, 1, reg[4]); - SW_SET_REG_BY_FIELD(HOST_ENTRY2, INTF_ID, data, reg[2]); - } - - if (FAL_IP_ENTRY_PORT_EN & next_mode) - { - SW_SET_REG_BY_FIELD(HOST_ENTRY4, SPEC_SP, 1, reg[4]); - SW_SET_REG_BY_FIELD(HOST_ENTRY2, SRC_PORT, entry->port_id, reg[2]); - } - - if (FAL_IP_ENTRY_STATUS_EN & next_mode) - { - SW_SET_REG_BY_FIELD(HOST_ENTRY4, SPEC_STATUS, 1, reg[4]); - SW_SET_REG_BY_FIELD(HOST_ENTRY3, AGE_FLAG, entry->status, reg[3]); - } - - rv = _isis_host_down_to_hw(dev_id, reg); - SW_RTN_ON_ERROR(rv); - - rv = _isis_host_entry_commit(dev_id, ISIS_ENTRY_ARP, ISIS_HOST_ENTRY_NEXT); - SW_RTN_ON_ERROR(rv); - - rv = _isis_host_up_to_sw(dev_id, reg); - SW_RTN_ON_ERROR(rv); - - aos_mem_zero(entry, sizeof (fal_host_entry_t)); - - rv = _isis_host_hw_to_sw(dev_id, reg, entry); - SW_RTN_ON_ERROR(rv); - - if (!(entry->status)) - { - return SW_NO_MORE; - } - - SW_GET_FIELD_BY_REG(HOST_ENTRY4, TBL_IDX, entry->entry_id, reg[4]); - return SW_OK; -} - -static sw_error_t -_isis_ip_host_counter_bind(a_uint32_t dev_id, a_uint32_t entry_id, - a_uint32_t cnt_id, a_bool_t enable) -{ - sw_error_t rv; - a_uint32_t reg[5] = { 0 }, tbl[5] = { 0 }, tbl_idx; - - HSL_DEV_ID_CHECK(dev_id); - - rv = _isis_ip_feature_check(dev_id); - SW_RTN_ON_ERROR(rv); - - tbl_idx = (entry_id - 1) & 0x7f; - SW_SET_REG_BY_FIELD(HOST_ENTRY4, TBL_IDX, tbl_idx, reg[4]); - - rv = _isis_host_down_to_hw(dev_id, reg); - SW_RTN_ON_ERROR(rv); - - rv = _isis_host_entry_commit(dev_id, ISIS_ENTRY_ARP, ISIS_HOST_ENTRY_NEXT); - if (SW_OK != rv) - { - return SW_NOT_FOUND; - } - - rv = _isis_host_up_to_sw(dev_id, reg); - SW_RTN_ON_ERROR(rv); - - SW_GET_FIELD_BY_REG(HOST_ENTRY4, TBL_IDX, tbl_idx, reg[4]); - if (entry_id != tbl_idx) - { - return SW_NOT_FOUND; - } - - tbl[0] = reg[0]; - tbl[3] = (reg[3] >> 15) << 15; - rv = _isis_host_down_to_hw(dev_id, tbl); - SW_RTN_ON_ERROR(rv); - - rv = _isis_host_entry_commit(dev_id, ISIS_ENTRY_ARP, ISIS_HOST_ENTRY_DEL); - SW_RTN_ON_ERROR(rv); - - if (A_FALSE == enable) - { - SW_SET_REG_BY_FIELD(HOST_ENTRY3, CNT_EN, 0, reg[3]); - } - else if (A_TRUE == enable) - { - SW_SET_REG_BY_FIELD(HOST_ENTRY3, CNT_EN, 1, reg[3]); - SW_SET_REG_BY_FIELD(HOST_ENTRY3, CNT_IDX, cnt_id, reg[3]); - } - else - { - return SW_BAD_PARAM; - } - - reg[4] = 0x0; - rv = _isis_host_down_to_hw(dev_id, reg); - SW_RTN_ON_ERROR(rv); - - rv = _isis_host_entry_commit(dev_id, ISIS_ENTRY_ARP, ISIS_HOST_ENTRY_ADD); - return rv; -} - -static sw_error_t -_isis_ip_host_pppoe_bind(a_uint32_t dev_id, a_uint32_t entry_id, - a_uint32_t pppoe_id, a_bool_t enable) -{ - sw_error_t rv; - a_uint32_t reg[5] = { 0 }, tbl[5] = { 0 }, tbl_idx; - - HSL_DEV_ID_CHECK(dev_id); - - rv = _isis_ip_feature_check(dev_id); - SW_RTN_ON_ERROR(rv); - - tbl_idx = (entry_id - 1) & 0x7f; - SW_SET_REG_BY_FIELD(HOST_ENTRY4, TBL_IDX, tbl_idx, reg[4]); - - rv = _isis_host_down_to_hw(dev_id, reg); - SW_RTN_ON_ERROR(rv); - - rv = _isis_host_entry_commit(dev_id, ISIS_ENTRY_ARP, ISIS_HOST_ENTRY_NEXT); - SW_RTN_ON_ERROR(rv); - - rv = _isis_host_up_to_sw(dev_id, reg); - if (SW_OK != rv) - { - return SW_NOT_FOUND; - } - - SW_GET_FIELD_BY_REG(HOST_ENTRY4, TBL_IDX, tbl_idx, reg[4]); - if (entry_id != tbl_idx) - { - return SW_NOT_FOUND; - } - - if (A_FALSE == enable) - { - SW_SET_REG_BY_FIELD(HOST_ENTRY3, PPPOE_EN, 0, reg[3]); - } - else if (A_TRUE == enable) - { - SW_SET_REG_BY_FIELD(HOST_ENTRY3, PPPOE_EN, 1, reg[3]); - SW_SET_REG_BY_FIELD(HOST_ENTRY3, PPPOE_IDX, pppoe_id, reg[3]); - } - else - { - return SW_BAD_PARAM; - } - - tbl[0] = reg[0]; - tbl[3] = (reg[3] >> 15) << 15; - rv = _isis_host_down_to_hw(dev_id, tbl); - SW_RTN_ON_ERROR(rv); - - rv = _isis_host_entry_commit(dev_id, ISIS_ENTRY_ARP, ISIS_HOST_ENTRY_DEL); - SW_RTN_ON_ERROR(rv); - - reg[4] = 0x0; - rv = _isis_host_down_to_hw(dev_id, reg); - SW_RTN_ON_ERROR(rv); - - rv = _isis_host_entry_commit(dev_id, ISIS_ENTRY_ARP, ISIS_HOST_ENTRY_ADD); - SW_RTN_ON_ERROR(rv); - - rv = _isis_host_up_to_sw(dev_id, reg); - SW_RTN_ON_ERROR(rv); - - return SW_OK; -} - -static sw_error_t -_isis_ip_pt_arp_learn_set(a_uint32_t dev_id, fal_port_t port_id, - a_uint32_t flags) -{ - sw_error_t rv; - a_uint32_t data = 0; - - HSL_DEV_ID_CHECK(dev_id); - - rv = _isis_ip_feature_check(dev_id); - SW_RTN_ON_ERROR(rv); - - HSL_REG_ENTRY_GET(rv, dev_id, ROUTER_PTCTRL2, 0, - (a_uint8_t *) (&data), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - - if (FAL_ARP_LEARN_REQ & flags) - { - data |= (0x1 << port_id); - } - else - { - data &= (~(0x1 << port_id)); - } - - if (FAL_ARP_LEARN_ACK & flags) - { - data |= (0x1 << (ROUTER_PTCTRL2_ARP_LEARN_ACK_BOFFSET + port_id)); - } - else - { - data &= (~(0x1 << (ROUTER_PTCTRL2_ARP_LEARN_ACK_BOFFSET + port_id))); - } - - HSL_REG_ENTRY_SET(rv, dev_id, ROUTER_PTCTRL2, 0, - (a_uint8_t *) (&data), sizeof (a_uint32_t)); - return rv; -} - -static sw_error_t -_isis_ip_pt_arp_learn_get(a_uint32_t dev_id, fal_port_t port_id, - a_uint32_t * flags) -{ - sw_error_t rv; - a_uint32_t data = 0; - - HSL_DEV_ID_CHECK(dev_id); - - rv = _isis_ip_feature_check(dev_id); - SW_RTN_ON_ERROR(rv); - - *flags = 0; - - HSL_REG_ENTRY_GET(rv, dev_id, ROUTER_PTCTRL2, 0, - (a_uint8_t *) (&data), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - - if (data & (0x1 << port_id)) - { - *flags |= FAL_ARP_LEARN_REQ; - } - - if (data & (0x1 << (ROUTER_PTCTRL2_ARP_LEARN_ACK_BOFFSET + port_id))) - { - *flags |= FAL_ARP_LEARN_ACK; - } - - return SW_OK; -} - -static sw_error_t -_isis_ip_arp_learn_set(a_uint32_t dev_id, fal_arp_learn_mode_t mode) -{ - sw_error_t rv; - a_uint32_t data; - - HSL_DEV_ID_CHECK(dev_id); - - rv = _isis_ip_feature_check(dev_id); - SW_RTN_ON_ERROR(rv); - - if (FAL_ARP_LEARN_ALL == mode) - { - data = 1; - } - else if (FAL_ARP_LEARN_LOCAL == mode) - { - data = 0; - } - else - { - return SW_BAD_PARAM; - } - - HSL_REG_FIELD_SET(rv, dev_id, ROUTER_CTRL, 0, ARP_LEARN_MODE, - (a_uint8_t *) (&data), sizeof (a_uint32_t)); - return rv; -} - -static sw_error_t -_isis_ip_arp_learn_get(a_uint32_t dev_id, fal_arp_learn_mode_t * mode) -{ - sw_error_t rv; - a_uint32_t data = 0; - - HSL_DEV_ID_CHECK(dev_id); - - rv = _isis_ip_feature_check(dev_id); - SW_RTN_ON_ERROR(rv); - - HSL_REG_FIELD_GET(rv, dev_id, ROUTER_CTRL, 0, ARP_LEARN_MODE, - (a_uint8_t *) (&data), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - - if (data) - { - *mode = FAL_ARP_LEARN_ALL; - } - else - { - *mode = FAL_ARP_LEARN_LOCAL; - } - - return SW_OK; -} - -static sw_error_t -_isis_ip_source_guard_set(a_uint32_t dev_id, fal_port_t port_id, - fal_source_guard_mode_t mode) -{ - sw_error_t rv; - a_uint32_t reg = 0, data; - - HSL_DEV_ID_CHECK(dev_id); - - rv = _isis_ip_feature_check(dev_id); - SW_RTN_ON_ERROR(rv); - - HSL_REG_ENTRY_GET(rv, dev_id, ROUTER_PTCTRL1, 0, - (a_uint8_t *) (®), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - - if (FAL_NO_SOURCE_GUARD < mode) - { - return SW_BAD_PARAM; - } - - data = 0; - if (FAL_MAC_IP_GUARD == mode) - { - data = 1; - } - else if (FAL_MAC_IP_PORT_GUARD == mode) - { - data = 2; - } - else if (FAL_MAC_IP_VLAN_GUARD == mode) - { - data = 3; - } - else if (FAL_MAC_IP_PORT_VLAN_GUARD == mode) - { - data = 4; - } - reg &= (~(0x7 << (port_id * 3))); - reg |= ((data & 0x7) << (port_id * 3)); - - HSL_REG_ENTRY_SET(rv, dev_id, ROUTER_PTCTRL1, 0, - (a_uint8_t *) (®), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - - data = 1; - if (FAL_NO_SOURCE_GUARD == mode) - { - data = 0; - } - - HSL_REG_FIELD_SET(rv, dev_id, PORT_VLAN1, port_id, SP_CHECK_EN, - (a_uint8_t *) (&data), sizeof (a_uint32_t)); - return rv; -} - -static sw_error_t -_isis_ip_source_guard_get(a_uint32_t dev_id, fal_port_t port_id, - fal_source_guard_mode_t * mode) -{ - sw_error_t rv; - a_uint32_t reg = 0, data; - - HSL_DEV_ID_CHECK(dev_id); - - rv = _isis_ip_feature_check(dev_id); - SW_RTN_ON_ERROR(rv); - - HSL_REG_ENTRY_GET(rv, dev_id, ROUTER_PTCTRL1, 0, - (a_uint8_t *) (®), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - - data = (reg >> (port_id * 3)) & 0x7; - - *mode = FAL_NO_SOURCE_GUARD; - if (1 == data) - { - *mode = FAL_MAC_IP_GUARD; - } - else if (2 == data) - { - *mode = FAL_MAC_IP_PORT_GUARD; - } - else if (3 == data) - { - *mode = FAL_MAC_IP_VLAN_GUARD; - } - else if (4 == data) - { - *mode = FAL_MAC_IP_PORT_VLAN_GUARD; - } - - return SW_OK; -} - -static sw_error_t -_isis_ip_unk_source_cmd_set(a_uint32_t dev_id, fal_fwd_cmd_t cmd) -{ - sw_error_t rv; - a_uint32_t data; - - HSL_DEV_ID_CHECK(dev_id); - - rv = _isis_ip_feature_check(dev_id); - SW_RTN_ON_ERROR(rv); - - if (FAL_MAC_FRWRD == cmd) - { - data = 0; - } - else if (FAL_MAC_DROP == cmd) - { - data = 1; - } - else if (FAL_MAC_RDT_TO_CPU == cmd) - { - data = 2; - } - else - { - return SW_NOT_SUPPORTED; - } - - HSL_REG_FIELD_SET(rv, dev_id, FORWARD_CTL0, 0, IP_NOT_FOUND, - (a_uint8_t *) (&data), sizeof (a_uint32_t)); - return rv; -} - -static sw_error_t -_isis_ip_unk_source_cmd_get(a_uint32_t dev_id, fal_fwd_cmd_t * cmd) -{ - sw_error_t rv; - a_uint32_t data = 0; - - HSL_DEV_ID_CHECK(dev_id); - - rv = _isis_ip_feature_check(dev_id); - SW_RTN_ON_ERROR(rv); - - HSL_REG_FIELD_GET(rv, dev_id, FORWARD_CTL0, 0, IP_NOT_FOUND, - (a_uint8_t *) (&data), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - - if (0 == data) - { - *cmd = FAL_MAC_FRWRD; - } - else if (1 == data) - { - *cmd = FAL_MAC_DROP; - } - else - { - *cmd = FAL_MAC_RDT_TO_CPU; - } - - return SW_OK; -} - -static sw_error_t -_isis_ip_arp_guard_set(a_uint32_t dev_id, fal_port_t port_id, - fal_source_guard_mode_t mode) -{ - sw_error_t rv; - a_uint32_t reg = 0, data; - - HSL_DEV_ID_CHECK(dev_id); - - rv = _isis_ip_feature_check(dev_id); - SW_RTN_ON_ERROR(rv); - - HSL_DEV_ID_CHECK(dev_id); - - HSL_REG_ENTRY_GET(rv, dev_id, ROUTER_PTCTRL0, 0, - (a_uint8_t *) (®), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - - if (FAL_NO_SOURCE_GUARD < mode) - { - return SW_BAD_PARAM; - } - - data = 0; - if (FAL_MAC_IP_GUARD == mode) - { - data = 1; - } - else if (FAL_MAC_IP_PORT_GUARD == mode) - { - data = 2; - } - else if (FAL_MAC_IP_VLAN_GUARD == mode) - { - data = 3; - } - else if (FAL_MAC_IP_PORT_VLAN_GUARD == mode) - { - data = 4; - } - reg &= (~(0x7 << (port_id * 3))); - reg |= ((data & 0x7) << (port_id * 3)); - - HSL_REG_ENTRY_SET(rv, dev_id, ROUTER_PTCTRL0, 0, - (a_uint8_t *) (®), sizeof (a_uint32_t)); - return rv; -} - -static sw_error_t -_isis_ip_arp_guard_get(a_uint32_t dev_id, fal_port_t port_id, - fal_source_guard_mode_t * mode) -{ - sw_error_t rv; - a_uint32_t reg = 0, data; - - HSL_DEV_ID_CHECK(dev_id); - - rv = _isis_ip_feature_check(dev_id); - SW_RTN_ON_ERROR(rv); - - HSL_DEV_ID_CHECK(dev_id); - - HSL_REG_ENTRY_GET(rv, dev_id, ROUTER_PTCTRL0, 0, - (a_uint8_t *) (®), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - - data = (reg >> (port_id * 3)) & 0x7; - - *mode = FAL_NO_SOURCE_GUARD; - if (1 == data) - { - *mode = FAL_MAC_IP_GUARD; - } - else if (2 == data) - { - *mode = FAL_MAC_IP_PORT_GUARD; - } - else if (3 == data) - { - *mode = FAL_MAC_IP_VLAN_GUARD; - } - else if (4 == data) - { - *mode = FAL_MAC_IP_PORT_VLAN_GUARD; - } - - return SW_OK; -} - -static sw_error_t -_isis_arp_unk_source_cmd_set(a_uint32_t dev_id, fal_fwd_cmd_t cmd) -{ - sw_error_t rv; - a_uint32_t data; - - HSL_DEV_ID_CHECK(dev_id); - - rv = _isis_ip_feature_check(dev_id); - SW_RTN_ON_ERROR(rv); - - if (FAL_MAC_FRWRD == cmd) - { - data = 0; - } - else if (FAL_MAC_DROP == cmd) - { - data = 1; - } - else if (FAL_MAC_RDT_TO_CPU == cmd) - { - data = 2; - } - else - { - return SW_NOT_SUPPORTED; - } - - HSL_REG_FIELD_SET(rv, dev_id, FORWARD_CTL0, 0, ARP_NOT_FOUND, - (a_uint8_t *) (&data), sizeof (a_uint32_t)); - return rv; -} - -static sw_error_t -_isis_arp_unk_source_cmd_get(a_uint32_t dev_id, fal_fwd_cmd_t * cmd) -{ - sw_error_t rv; - a_uint32_t data = 0; - - HSL_DEV_ID_CHECK(dev_id); - - rv = _isis_ip_feature_check(dev_id); - SW_RTN_ON_ERROR(rv); - - HSL_REG_FIELD_GET(rv, dev_id, FORWARD_CTL0, 0, ARP_NOT_FOUND, - (a_uint8_t *) (&data), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - - if (0 == data) - { - *cmd = FAL_MAC_FRWRD; - } - else if (1 == data) - { - *cmd = FAL_MAC_DROP; - } - else - { - *cmd = FAL_MAC_RDT_TO_CPU; - } - - return SW_OK; -} - -static sw_error_t -_isis_ip_route_status_set(a_uint32_t dev_id, a_bool_t enable) -{ - sw_error_t rv; - a_uint32_t data; - - HSL_DEV_ID_CHECK(dev_id); - - rv = _isis_ip_feature_check(dev_id); - SW_RTN_ON_ERROR(rv); - - if (A_TRUE == enable) - { - data = 1; - } - else if (A_FALSE == enable) - { - data = 0; - } - else - { - return SW_BAD_PARAM; - } - - HSL_REG_FIELD_SET(rv, dev_id, ROUTER_CTRL, 0, ROUTER_EN, - (a_uint8_t *) (&data), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - - HSL_REG_FIELD_SET(rv, dev_id, MOD_ENABLE, 0, L3_EN, - (a_uint8_t *) (&data), sizeof (a_uint32_t)); - return rv; -} - -static sw_error_t -_isis_ip_route_status_get(a_uint32_t dev_id, a_bool_t * enable) -{ - sw_error_t rv; - a_uint32_t route_en = 0, l3_en = 0; - - HSL_DEV_ID_CHECK(dev_id); - - rv = _isis_ip_feature_check(dev_id); - SW_RTN_ON_ERROR(rv); - - HSL_REG_FIELD_GET(rv, dev_id, ROUTER_CTRL, 0, ROUTER_EN, - (a_uint8_t *) (&route_en), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - - HSL_REG_FIELD_GET(rv, dev_id, MOD_ENABLE, 0, L3_EN, - (a_uint8_t *) (&l3_en), sizeof (a_uint32_t)) - SW_RTN_ON_ERROR(rv); - - if (route_en && l3_en) - { - *enable = A_TRUE; - } - else - { - *enable = A_FALSE; - } - - return rv; -} - -static sw_error_t -_isis_ip_intf_entry_add(a_uint32_t dev_id, fal_intf_mac_entry_t * entry) -{ - sw_error_t rv; - a_uint32_t i, j, found = 0, addr, tbl[3] = { 0 }; - fal_intf_mac_entry_t * intf_entry; - - HSL_DEV_ID_CHECK(dev_id); - - rv = _isis_ip_feature_check(dev_id); - SW_RTN_ON_ERROR(rv); - - for (i = 0; i < ISIS_INTF_MAC_ADDR_NUM; i++) - { - if (isis_mac_snap[dev_id] & (0x1 << i)) - { - intf_entry = &(isis_intf_snap[dev_id][i]); - if ((entry->vid_low == intf_entry->vid_low) - && (entry->vid_high == intf_entry->vid_high) - &&(!memcmp(&entry->mac_addr, &intf_entry->mac_addr, 6))) - { - /* all same, return OK directly */ - if (!aos_mem_cmp(intf_entry, entry, sizeof(fal_intf_mac_entry_t))) - { - return SW_OK; - } - else - { - /* update entry */ - found = 1; - break; - } - } - else - { -#if 0 /* Different mac should be ok for VID range? */ - /* entry VID cross border, not support */ - if ((entry->vid_low >= intf_entry->vid_low) && (entry->vid_low <= intf_entry->vid_high)) - { - return SW_BAD_PARAM; - } - - /* entry VID cross border, not support */ - if ((entry->vid_high >= intf_entry->vid_low) && (entry->vid_low <= intf_entry->vid_high)) - { - return SW_BAD_PARAM; - } -#endif - } - } - } - - if (!found) - { - for (i = 0; i < ISIS_INTF_MAC_ADDR_NUM; i++) - { - if (!(isis_mac_snap[dev_id] & (0x1 << i))) - { - intf_entry = &(isis_intf_snap[dev_id][i]); - break; - } - } - } - - if (ISIS_INTF_MAC_ADDR_NUM == i) - { - return SW_NO_RESOURCE; - } - - if ((A_FALSE == entry->ip4_route) && (A_FALSE == entry->ip6_route)) - { - return SW_NOT_SUPPORTED; - } - - if (512 <= (entry->vid_high - entry->vid_low)) - { - return SW_BAD_PARAM; - } - - SW_SET_REG_BY_FIELD(INTF_ADDR_ENTRY0, MAC_ADDR2, entry->mac_addr.uc[2], - tbl[0]); - SW_SET_REG_BY_FIELD(INTF_ADDR_ENTRY0, MAC_ADDR3, entry->mac_addr.uc[3], - tbl[0]); - SW_SET_REG_BY_FIELD(INTF_ADDR_ENTRY0, MAC_ADDR4, entry->mac_addr.uc[4], - tbl[0]); - SW_SET_REG_BY_FIELD(INTF_ADDR_ENTRY0, MAC_ADDR5, entry->mac_addr.uc[5], - tbl[0]); - SW_SET_REG_BY_FIELD(INTF_ADDR_ENTRY1, MAC_ADDR0, entry->mac_addr.uc[0], - tbl[1]); - SW_SET_REG_BY_FIELD(INTF_ADDR_ENTRY1, MAC_ADDR1, entry->mac_addr.uc[1], - tbl[1]); - - SW_SET_REG_BY_FIELD(INTF_ADDR_ENTRY1, VID_LOW, entry->vid_low, tbl[1]); - SW_SET_REG_BY_FIELD(INTF_ADDR_ENTRY1, VID_HIGH0, (entry->vid_high & 0xf), - tbl[1]); - SW_SET_REG_BY_FIELD(INTF_ADDR_ENTRY2, VID_HIGH1, (entry->vid_high >> 4), - tbl[2]); - - if (A_TRUE == entry->ip4_route) - { - SW_SET_REG_BY_FIELD(INTF_ADDR_ENTRY2, IP4_ROUTE, 1, tbl[2]); - } - - if (A_TRUE == entry->ip6_route) - { - SW_SET_REG_BY_FIELD(INTF_ADDR_ENTRY2, IP6_ROUTE, 1, tbl[2]); - } - - for (j = 0; j < 2; j++) - { - addr = ISIS_INTF_MAC_EDIT0_ADDR + (i << 4) + (j << 2); - HSL_REG_ENTRY_GEN_SET(rv, dev_id, addr, sizeof (a_uint32_t), - (a_uint8_t *) (&(tbl[j])), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - } - - for (j = 0; j < 3; j++) - { - addr = ISIS_INTF_MAC_TBL0_ADDR + (i << 4) + (j << 2); - HSL_REG_ENTRY_GEN_SET(rv, dev_id, addr, sizeof (a_uint32_t), - (a_uint8_t *) (&(tbl[j])), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - } - - isis_mac_snap[dev_id] |= (0x1 << i); - *intf_entry = *entry; - entry->entry_id = i; - return SW_OK; -} - -static sw_error_t -_isis_ip_intf_entry_del(a_uint32_t dev_id, a_uint32_t del_mode, - fal_intf_mac_entry_t * entry) -{ - sw_error_t rv; - a_uint32_t addr, tbl[3] = { 0 }; - - HSL_DEV_ID_CHECK(dev_id); - - rv = _isis_ip_feature_check(dev_id); - SW_RTN_ON_ERROR(rv); - - if (!(FAL_IP_ENTRY_ID_EN & del_mode)) - { - return SW_NOT_SUPPORTED; - } - - if (ISIS_INTF_MAC_ADDR_NUM <= entry->entry_id) - { - return SW_BAD_PARAM; - } - - /* clear valid bits */ - addr = ISIS_INTF_MAC_TBL2_ADDR + (entry->entry_id << 4); - HSL_REG_ENTRY_GEN_SET(rv, dev_id, addr, sizeof (a_uint32_t), - (a_uint8_t *) (&(tbl[2])), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - - isis_mac_snap[dev_id] &= (~(0x1 << entry->entry_id)); - return SW_OK; -} - -static sw_error_t -_isis_ip_intf_entry_next(a_uint32_t dev_id, a_uint32_t next_mode, - fal_intf_mac_entry_t * entry) -{ - sw_error_t rv; - a_uint32_t i, j, idx, addr, tbl[3] = { 0 }; - - HSL_DEV_ID_CHECK(dev_id); - - rv = _isis_ip_feature_check(dev_id); - SW_RTN_ON_ERROR(rv); - - if (FAL_NEXT_ENTRY_FIRST_ID == entry->entry_id) - { - idx = 0; - } - else - { - if ((ISIS_INTF_MAC_ADDR_NUM - 1) == entry->entry_id) - { - return SW_NO_MORE; - } - else - { - idx = entry->entry_id + 1; - } - } - - for (i = idx; i < ISIS_INTF_MAC_ADDR_NUM; i++) - { - if (isis_mac_snap[dev_id] & (0x1 << i)) - { - break; - } - } - - if (ISIS_INTF_MAC_ADDR_NUM == i) - { - return SW_NO_MORE; - } - - for (j = 0; j < 3; j++) - { - addr = ISIS_INTF_MAC_TBL0_ADDR + (i << 4) + (j << 2); - HSL_REG_ENTRY_GEN_GET(rv, dev_id, addr, sizeof (a_uint32_t), - (a_uint8_t *) (&(tbl[j])), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - } - - aos_mem_zero(entry, sizeof (fal_intf_mac_entry_t)); - - SW_GET_FIELD_BY_REG(INTF_ADDR_ENTRY0, MAC_ADDR2, entry->mac_addr.uc[2], - tbl[0]); - SW_GET_FIELD_BY_REG(INTF_ADDR_ENTRY0, MAC_ADDR3, entry->mac_addr.uc[3], - tbl[0]); - SW_GET_FIELD_BY_REG(INTF_ADDR_ENTRY0, MAC_ADDR4, entry->mac_addr.uc[4], - tbl[0]); - SW_GET_FIELD_BY_REG(INTF_ADDR_ENTRY0, MAC_ADDR5, entry->mac_addr.uc[5], - tbl[0]); - SW_GET_FIELD_BY_REG(INTF_ADDR_ENTRY1, MAC_ADDR0, entry->mac_addr.uc[0], - tbl[1]); - SW_GET_FIELD_BY_REG(INTF_ADDR_ENTRY1, MAC_ADDR1, entry->mac_addr.uc[1], - tbl[1]); - - SW_GET_FIELD_BY_REG(INTF_ADDR_ENTRY1, VID_LOW, entry->vid_low, tbl[1]); - SW_GET_FIELD_BY_REG(INTF_ADDR_ENTRY1, VID_HIGH0, j, tbl[1]); - entry->vid_high = j & 0xf; - SW_GET_FIELD_BY_REG(INTF_ADDR_ENTRY2, VID_HIGH1, j, tbl[2]); - entry->vid_high |= ((j & 0xff) << 4); - - SW_GET_FIELD_BY_REG(INTF_ADDR_ENTRY2, IP4_ROUTE, j, tbl[2]); - if (j) - { - entry->ip4_route = A_TRUE; - } - - SW_GET_FIELD_BY_REG(INTF_ADDR_ENTRY2, IP6_ROUTE, j, tbl[2]); - if (j) - { - entry->ip6_route = A_TRUE; - } - - entry->entry_id = i; - return SW_OK; -} - -#define ISIS_WCMP_ENTRY_MAX_ID 3 -#define ISIS_WCMP_HASH_MAX_NUM 16 -#define ISIS_IP_ENTRY_MAX_ID 127 - -#define ISIS_WCMP_HASH_TBL_ADDR 0x0e10 -#define ISIS_WCMP_NHOP_TBL_ADDR 0x0e20 - -#if 0 -static sw_error_t -_isis_ip_wcmp_entry_set(a_uint32_t dev_id, a_uint32_t wcmp_id, fal_ip_wcmp_t * wcmp) -{ - sw_error_t rv; - a_uint32_t i, j, addr, data; - a_uint8_t idx, ptr[4] = { 0 }, pos[16] = { 0 }; - - HSL_DEV_ID_CHECK(dev_id); - - rv = _isis_ip_feature_check(dev_id); - SW_RTN_ON_ERROR(rv); - - if (ISIS_WCMP_ENTRY_MAX_ID < wcmp_id) - { - return SW_BAD_PARAM; - } - - if (ISIS_WCMP_HASH_MAX_NUM < wcmp->nh_nr) - { - return SW_BAD_PARAM; - } - - for (i = 0; i < wcmp->nh_nr; i++) - { - if (ISIS_IP_ENTRY_MAX_ID < wcmp->nh_id[i]) - { - return SW_BAD_PARAM; - } - - idx = 4; - for (j = 0; j < 4; j++) - { - if (ptr[j] & 0x80) - { - if ((ptr[j] & 0x7f) == wcmp->nh_id[i]) - { - idx = j; - break; - } - } - else - { - idx = j; - } - } - - if (4 == idx) - { - return SW_BAD_PARAM; - } - else - { - ptr[idx] = (wcmp->nh_id[i] & 0x7f) | 0x80; - pos[i] = idx; - } - } - - data = 0; - for (j = 0; j < 4; j++) - { - data |= (ptr[j] << (j << 3)); - } - - addr = ISIS_WCMP_NHOP_TBL_ADDR + (wcmp_id << 2); - HSL_REG_ENTRY_GEN_SET(rv, dev_id, addr, sizeof (a_uint32_t), - (a_uint8_t *) (&data), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - - data = 0; - for (j = 0; j < 16; j++) - { - data |= (pos[j] << (j << 1)); - } - - addr = ISIS_WCMP_HASH_TBL_ADDR + (wcmp_id << 2); - HSL_REG_ENTRY_GEN_SET(rv, dev_id, addr, sizeof (a_uint32_t), - (a_uint8_t *) (&data), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - - return SW_OK; -} - -static sw_error_t -_isis_ip_wcmp_entry_get(a_uint32_t dev_id, a_uint32_t wcmp_id, fal_ip_wcmp_t * wcmp) -{ - sw_error_t rv; - a_uint32_t i, addr, data= 0; - a_uint8_t ptr[4] = { 0 }, pos[16] = { 0 }; - - HSL_DEV_ID_CHECK(dev_id); - - rv = _isis_ip_feature_check(dev_id); - SW_RTN_ON_ERROR(rv); - - if (ISIS_WCMP_ENTRY_MAX_ID < wcmp_id) - { - return SW_BAD_PARAM; - } - - wcmp->nh_nr = ISIS_WCMP_HASH_MAX_NUM; - - addr = ISIS_WCMP_NHOP_TBL_ADDR + (wcmp_id << 2); - HSL_REG_ENTRY_GEN_GET(rv, dev_id, addr, sizeof (a_uint32_t), - (a_uint8_t *) (&data), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - - for (i = 0; i < 4; i++) - { - ptr[i] = (data >> (i << 3)) & 0x7f; - } - - addr = ISIS_WCMP_HASH_TBL_ADDR + (wcmp_id << 2); - HSL_REG_ENTRY_GEN_GET(rv, dev_id, addr, sizeof (a_uint32_t), - (a_uint8_t *) (&data), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - - for (i = 0; i < 16; i++) - { - pos[i] = (data >> (i << 1)) & 0x3; - } - - for (i = 0; i < 16; i++) - { - wcmp->nh_id[i] = ptr[pos[i]]; - } - - return SW_OK; -} -#endif - -static sw_error_t -_isis_ip_wcmp_hash_mode_set(a_uint32_t dev_id, a_uint32_t hash_mode) -{ - sw_error_t rv; - a_uint32_t data = 0; - - HSL_REG_ENTRY_GET(rv, dev_id, ROUTER_CTRL, 0, - (a_uint8_t *) (&data), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - - if (FAL_WCMP_HASH_KEY_SIP & hash_mode) - { - SW_SET_REG_BY_FIELD(ROUTER_CTRL, WCMP_HAHS_SIP, 1, data); - } - else - { - SW_SET_REG_BY_FIELD(ROUTER_CTRL, WCMP_HAHS_SIP, 0, data); - } - - if (FAL_WCMP_HASH_KEY_DIP & hash_mode) - { - SW_SET_REG_BY_FIELD(ROUTER_CTRL, WCMP_HAHS_DIP, 1, data); - } - else - { - SW_SET_REG_BY_FIELD(ROUTER_CTRL, WCMP_HAHS_DIP, 0, data); - } - - if (FAL_WCMP_HASH_KEY_SPORT & hash_mode) - { - SW_SET_REG_BY_FIELD(ROUTER_CTRL, WCMP_HAHS_SP, 1, data); - } - else - { - SW_SET_REG_BY_FIELD(ROUTER_CTRL, WCMP_HAHS_SP, 0, data); - } - - if (FAL_WCMP_HASH_KEY_DPORT & hash_mode) - { - SW_SET_REG_BY_FIELD(ROUTER_CTRL, WCMP_HAHS_DP, 1, data); - } - else - { - SW_SET_REG_BY_FIELD(ROUTER_CTRL, WCMP_HAHS_DP, 0, data); - } - - - HSL_REG_ENTRY_SET(rv, dev_id, ROUTER_CTRL, 0, - (a_uint8_t *) (&data), sizeof (a_uint32_t)); - return rv; -} - -static sw_error_t -_isis_ip_wcmp_hash_mode_get(a_uint32_t dev_id, a_uint32_t * hash_mode) -{ - sw_error_t rv; - a_uint32_t data = 0, field; - - *hash_mode = 0; - - HSL_REG_ENTRY_GET(rv, dev_id, ROUTER_CTRL, 0, - (a_uint8_t *) (&data), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - - SW_GET_FIELD_BY_REG(ROUTER_CTRL, WCMP_HAHS_SIP, field, data); - if (field) - { - *hash_mode |= FAL_WCMP_HASH_KEY_SIP; - } - - SW_GET_FIELD_BY_REG(ROUTER_CTRL, WCMP_HAHS_DIP, field, data); - if (field) - { - *hash_mode |= FAL_WCMP_HASH_KEY_DIP; - } - - SW_GET_FIELD_BY_REG(ROUTER_CTRL, WCMP_HAHS_SP, field, data); - if (field) - { - *hash_mode |= FAL_WCMP_HASH_KEY_SPORT; - } - - SW_GET_FIELD_BY_REG(ROUTER_CTRL, WCMP_HAHS_DP, field, data); - if (field) - { - *hash_mode |= FAL_WCMP_HASH_KEY_DPORT; - } - - return SW_OK; -} - -sw_error_t -isis_ip_reset(a_uint32_t dev_id) -{ - sw_error_t rv; - a_uint32_t i, addr, data = 0; - - HSL_DEV_ID_CHECK(dev_id); - - rv = _isis_ip_feature_check(dev_id); - SW_RTN_ON_ERROR(rv); - - HSL_REG_ENTRY_SET(rv, dev_id, HOST_ENTRY4, 0, (a_uint8_t *) (&data), - sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - - rv = _isis_host_entry_commit(dev_id, ISIS_ENTRY_ARP, ISIS_HOST_ENTRY_FLUSH); - SW_RTN_ON_ERROR(rv); - - isis_mac_snap[dev_id] = 0; - for (i = 0; i < ISIS_INTF_MAC_ADDR_NUM; i++) - { - addr = ISIS_INTF_MAC_TBL2_ADDR + (i << 4); - HSL_REG_ENTRY_GEN_SET(rv, dev_id, addr, sizeof (a_uint32_t), - (a_uint8_t *) (&data), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - } - - return SW_OK; -} - -/** - * @brief Add one host entry to one particular device. - * @details Comments: - * For ISIS the intf_id parameter in host_entry means vlan id. - Before host entry added related interface entry and ip6 base address - must be set at first. - Hardware entry id will be returned. - * @param[in] dev_id device id - * @param[in] host_entry host entry parameter - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -isis_ip_host_add(a_uint32_t dev_id, fal_host_entry_t * host_entry) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _isis_ip_host_add(dev_id, host_entry); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Delete one host entry from one particular device. - * @details Comments: - * For ISIS the intf_id parameter in host_entry means vlan id. - Before host entry deleted related interface entry and ip6 base address - must be set atfirst. - For del_mode please refer IP entry operation flags. - * @param[in] dev_id device id - * @param[in] del_mode delete operation mode - * @param[in] host_entry host entry parameter - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -isis_ip_host_del(a_uint32_t dev_id, a_uint32_t del_mode, - fal_host_entry_t * host_entry) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _isis_ip_host_del(dev_id, del_mode, host_entry); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Get one host entry from one particular device. - * @details Comments: - * For ISIS the intf_id parameter in host_entry means vlan id. - Before host entry deleted related interface entry and ip6 base address - must be set atfirst. - For get_mode please refer IP entry operation flags. - * @param[in] dev_id device id - * @param[in] get_mode get operation mode - * @param[out] host_entry host entry parameter - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -isis_ip_host_get(a_uint32_t dev_id, a_uint32_t get_mode, - fal_host_entry_t * host_entry) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _isis_ip_host_get(dev_id, get_mode, host_entry); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Next one host entry from one particular device. - * @details Comments: - * For ISIS the intf_id parameter in host_entry means vlan id. - Before host entry deleted related interface entry and ip6 base address - must be set atfirst. - For next_mode please refer IP entry operation flags. - For get the first entry please set entry id as FAL_NEXT_ENTRY_FIRST_ID - * @param[in] dev_id device id - * @param[in] next_mode next operation mode - * @param[out] host_entry host entry parameter - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -isis_ip_host_next(a_uint32_t dev_id, a_uint32_t next_mode, - fal_host_entry_t * host_entry) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _isis_ip_host_next(dev_id, next_mode, host_entry); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Bind one counter entry to one host entry on one particular device. - * @param[in] dev_id device id - * @param[in] entry_id host entry id - * @param[in] cnt_id counter entry id - * @param[in] enable A_TRUE means bind, A_FALSE means unbind - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -isis_ip_host_counter_bind(a_uint32_t dev_id, a_uint32_t entry_id, - a_uint32_t cnt_id, a_bool_t enable) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _isis_ip_host_counter_bind(dev_id, entry_id, cnt_id, enable); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Bind one pppoe session entry to one host entry on one particular device. - * @param[in] dev_id device id - * @param[in] entry_id host entry id - * @param[in] pppoe_id pppoe session entry id - * @param[in] enable A_TRUE means bind, A_FALSE means unbind - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -isis_ip_host_pppoe_bind(a_uint32_t dev_id, a_uint32_t entry_id, - a_uint32_t pppoe_id, a_bool_t enable) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _isis_ip_host_pppoe_bind(dev_id, entry_id, pppoe_id, enable); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Set arp packets type to learn on one particular port. - * @param[in] dev_id device id - * @param[in] port_id port id - * @param[in] flags arp type FAL_ARP_LEARN_REQ and/or FAL_ARP_LEARN_ACK - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -isis_ip_pt_arp_learn_set(a_uint32_t dev_id, fal_port_t port_id, - a_uint32_t flags) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _isis_ip_pt_arp_learn_set(dev_id, port_id, flags); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Get arp packets type to learn on one particular port. - * @param[in] dev_id device id - * @param[in] port_id port id - * @param[out] flags arp type FAL_ARP_LEARN_REQ and/or FAL_ARP_LEARN_ACK - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -isis_ip_pt_arp_learn_get(a_uint32_t dev_id, fal_port_t port_id, - a_uint32_t * flags) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _isis_ip_pt_arp_learn_get(dev_id, port_id, flags); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Set arp packets type to learn on one particular device. - * @param[in] dev_id device id - * @param[in] mode learning mode - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -isis_ip_arp_learn_set(a_uint32_t dev_id, fal_arp_learn_mode_t mode) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _isis_ip_arp_learn_set(dev_id, mode); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Get arp packets type to learn on one particular device. - * @param[in] dev_id device id - * @param[out] mode learning mode - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -isis_ip_arp_learn_get(a_uint32_t dev_id, fal_arp_learn_mode_t * mode) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _isis_ip_arp_learn_get(dev_id, mode); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Set ip packets source guarding mode on one particular port. - * @param[in] dev_id device id - * @param[in] port_id port id - * @param[in] mode source guarding mode - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -isis_ip_source_guard_set(a_uint32_t dev_id, fal_port_t port_id, - fal_source_guard_mode_t mode) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _isis_ip_source_guard_set(dev_id, port_id, mode); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Get ip packets source guarding mode on one particular port. - * @param[in] dev_id device id - * @param[in] port_id port id - * @param[out] mode source guarding mode - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -isis_ip_source_guard_get(a_uint32_t dev_id, fal_port_t port_id, - fal_source_guard_mode_t * mode) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _isis_ip_source_guard_get(dev_id, port_id, mode); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Set unkonw source ip packets forwarding command on one particular device. - * @details Comments: - * This settin is no meaning when ip source guard not enable - * @param[in] dev_id device id - * @param[in] cmd forwarding command - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -isis_ip_unk_source_cmd_set(a_uint32_t dev_id, fal_fwd_cmd_t cmd) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _isis_ip_unk_source_cmd_set(dev_id, cmd); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Get unkonw source ip packets forwarding command on one particular device. - * @param[in] dev_id device id - * @param[out] cmd forwarding command - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -isis_ip_unk_source_cmd_get(a_uint32_t dev_id, fal_fwd_cmd_t * cmd) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _isis_ip_unk_source_cmd_get(dev_id, cmd); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Set arp packets source guarding mode on one particular port. - * @param[in] dev_id device id - * @param[in] port_id port id - * @param[in] mode source guarding mode - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -isis_ip_arp_guard_set(a_uint32_t dev_id, fal_port_t port_id, - fal_source_guard_mode_t mode) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _isis_ip_arp_guard_set(dev_id, port_id, mode); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Get arp packets source guarding mode on one particular port. - * @param[in] dev_id device id - * @param[in] port_id port id - * @param[out] mode source guarding mode - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -isis_ip_arp_guard_get(a_uint32_t dev_id, fal_port_t port_id, - fal_source_guard_mode_t * mode) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _isis_ip_arp_guard_get(dev_id, port_id, mode); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Set unkonw source arp packets forwarding command on one particular device. - * @details Comments: - * This settin is no meaning when arp source guard not enable - * @param[in] dev_id device id - * @param[in] cmd forwarding command - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -isis_arp_unk_source_cmd_set(a_uint32_t dev_id, fal_fwd_cmd_t cmd) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _isis_arp_unk_source_cmd_set(dev_id, cmd); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Get unkonw source arp packets forwarding command on one particular device. - * @param[in] dev_id device id - * @param[out] cmd forwarding command - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -isis_arp_unk_source_cmd_get(a_uint32_t dev_id, fal_fwd_cmd_t * cmd) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _isis_arp_unk_source_cmd_get(dev_id, cmd); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Set IP unicast routing status on one particular device. - * @param[in] dev_id device id - * @param[in] enable A_TRUE or A_FALSE - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -isis_ip_route_status_set(a_uint32_t dev_id, a_bool_t enable) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _isis_ip_route_status_set(dev_id, enable); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Get IP unicast routing status on one particular device. - * @param[in] dev_id device id - * @param[out] enable A_TRUE or A_FALSE - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -isis_ip_route_status_get(a_uint32_t dev_id, a_bool_t * enable) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _isis_ip_route_status_get(dev_id, enable); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Add one interface entry to one particular device. - * @param[in] dev_id device id - * @param[in] entry interface entry - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -isis_ip_intf_entry_add(a_uint32_t dev_id, fal_intf_mac_entry_t * entry) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _isis_ip_intf_entry_add(dev_id, entry); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Delete one interface entry from one particular device. - * @param[in] dev_id device id - * @param[in] del_mode delete operation mode - * @param[in] entry interface entry - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -isis_ip_intf_entry_del(a_uint32_t dev_id, a_uint32_t del_mode, - fal_intf_mac_entry_t * entry) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _isis_ip_intf_entry_del(dev_id, del_mode, entry); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Next one interface entry from one particular device. - * @param[in] dev_id device id - * @param[in] next_mode next operation mode - * @param[out] entry interface entry - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -isis_ip_intf_entry_next(a_uint32_t dev_id, a_uint32_t next_mode, - fal_intf_mac_entry_t * entry) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _isis_ip_intf_entry_next(dev_id, next_mode, entry); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Set IP host entry aging time on one particular device. - * @details Comments: - * This operation will set dynamic entry aging time on a particular device. - * The unit of time is second. Because different device has differnet - * hardware granularity function will return actual time in hardware. - * @param[in] dev_id device id - * @param[in] time aging time - * @param[out] time actual aging time - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -isis_ip_age_time_set(a_uint32_t dev_id, a_uint32_t * time) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _isis_ip_age_time_set(dev_id, time); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Get IP host entry aging time on one particular device. - * @param[in] dev_id device id - * @param[out] time aging time - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -isis_ip_age_time_get(a_uint32_t dev_id, a_uint32_t * time) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _isis_ip_age_time_get(dev_id, time); - HSL_API_UNLOCK; - return rv; -} - -#if 0 -/** - * @brief Set IP WCMP table one particular device. - * @details Comments: - * Hardware only support 0 - 15 hash values and 4 different host tables. - * @param[in] dev_id device id - * @param[in] wcmp_id wcmp entry id - * @param[in] wcmp wcmp entry - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -isis_ip_wcmp_entry_set(a_uint32_t dev_id, a_uint32_t wcmp_id, fal_ip_wcmp_t * wcmp) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _isis_ip_wcmp_entry_set(dev_id, wcmp_id, wcmp); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Get IP WCMP table one particular device. - * @details Comments: - * Hardware only support 0 - 15 hash values and 4 different host tables. - * @param[in] dev_id device id - * @param[in] wcmp_id wcmp entry id - * @param[out] wcmp wcmp entry - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -isis_ip_wcmp_entry_get(a_uint32_t dev_id, a_uint32_t wcmp_id, fal_ip_wcmp_t * wcmp) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _isis_ip_wcmp_entry_get(dev_id, wcmp_id, wcmp); - HSL_API_UNLOCK; - return rv; -} -#endif - -/** - * @brief Set IP WCMP hash key mode. - * @param[in] dev_id device id - * @param[in] hash_mode hash mode - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -isis_ip_wcmp_hash_mode_set(a_uint32_t dev_id, a_uint32_t hash_mode) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _isis_ip_wcmp_hash_mode_set(dev_id, hash_mode); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Get IP WCMP hash key mode. - * @param[in] dev_id device id - * @param[out] hash_mode hash mode - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -isis_ip_wcmp_hash_mode_get(a_uint32_t dev_id, a_uint32_t * hash_mode) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _isis_ip_wcmp_hash_mode_get(dev_id, hash_mode); - HSL_API_UNLOCK; - return rv; -} - -sw_error_t -isis_ip_init(a_uint32_t dev_id) -{ - sw_error_t rv; - - HSL_DEV_ID_CHECK(dev_id); - - rv = isis_ip_reset(dev_id); - SW_RTN_ON_ERROR(rv); - -#ifndef HSL_STANDALONG - { - hsl_api_t *p_api; - - SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id)); - - p_api->ip_host_add = isis_ip_host_add; - p_api->ip_host_del = isis_ip_host_del; - p_api->ip_host_get = isis_ip_host_get; - p_api->ip_host_next = isis_ip_host_next; - p_api->ip_host_counter_bind = isis_ip_host_counter_bind; - p_api->ip_host_pppoe_bind = isis_ip_host_pppoe_bind; - p_api->ip_pt_arp_learn_set = isis_ip_pt_arp_learn_set; - p_api->ip_pt_arp_learn_get = isis_ip_pt_arp_learn_get; - p_api->ip_arp_learn_set = isis_ip_arp_learn_set; - p_api->ip_arp_learn_get = isis_ip_arp_learn_get; - p_api->ip_source_guard_set = isis_ip_source_guard_set; - p_api->ip_source_guard_get = isis_ip_source_guard_get; - p_api->ip_unk_source_cmd_set = isis_ip_unk_source_cmd_set; - p_api->ip_unk_source_cmd_get = isis_ip_unk_source_cmd_get; - p_api->ip_arp_guard_set = isis_ip_arp_guard_set; - p_api->ip_arp_guard_get = isis_ip_arp_guard_get; - p_api->arp_unk_source_cmd_set = isis_arp_unk_source_cmd_set; - p_api->arp_unk_source_cmd_get = isis_arp_unk_source_cmd_get; - p_api->ip_route_status_set = isis_ip_route_status_set; - p_api->ip_route_status_get = isis_ip_route_status_get; - p_api->ip_intf_entry_add = isis_ip_intf_entry_add; - p_api->ip_intf_entry_del = isis_ip_intf_entry_del; - p_api->ip_intf_entry_next = isis_ip_intf_entry_next; - p_api->ip_age_time_set = isis_ip_age_time_set; - p_api->ip_age_time_get = isis_ip_age_time_get; - p_api->ip_wcmp_hash_mode_set = isis_ip_wcmp_hash_mode_set; - p_api->ip_wcmp_hash_mode_get = isis_ip_wcmp_hash_mode_get; - } -#endif - - return SW_OK; -} - -/** - * @} - */ - diff --git a/feeds/ipq807x/qca-ssdk/src/src/hsl/isis/isis_leaky.c b/feeds/ipq807x/qca-ssdk/src/src/hsl/isis/isis_leaky.c deleted file mode 100755 index 0d720be03..000000000 --- a/feeds/ipq807x/qca-ssdk/src/src/hsl/isis/isis_leaky.c +++ /dev/null @@ -1,526 +0,0 @@ -/* - * Copyright (c) 2012, 2016 The Linux Foundation. All rights reserved. - * Permission to use, copy, modify, and/or distribute this software for - * any purpose with or without fee is hereby granted, provided that the - * above copyright notice and this permission notice appear in all copies. - * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES - * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR - * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES - * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN - * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT - * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. - */ - - -/** - * @defgroup isis_leaky ISIS_LEAKY - * @{ - */ -#include "sw.h" -#include "hsl.h" -#include "hsl_dev.h" -#include "hsl_port_prop.h" -#include "isis_leaky.h" -#include "isis_reg.h" - -static sw_error_t -_isis_uc_leaky_mode_set(a_uint32_t dev_id, - fal_leaky_ctrl_mode_t ctrl_mode) -{ - a_uint32_t data; - sw_error_t rv; - - HSL_DEV_ID_CHECK(dev_id); - - if (FAL_LEAKY_PORT_CTRL == ctrl_mode) - { - data = 0; - } - else if (FAL_LEAKY_FDB_CTRL == ctrl_mode) - { - data = 1; - } - else - { - return SW_BAD_PARAM; - } - - HSL_REG_FIELD_SET(rv, dev_id, FORWARD_CTL0, 0, ARL_UNI_LEAKY, - (a_uint8_t *) (&data), sizeof (a_uint32_t)); - return rv; -} - -static sw_error_t -_isis_uc_leaky_mode_get(a_uint32_t dev_id, - fal_leaky_ctrl_mode_t *ctrl_mode) -{ - a_uint32_t data = 0; - sw_error_t rv; - - HSL_DEV_ID_CHECK(dev_id); - - HSL_REG_FIELD_GET(rv, dev_id, FORWARD_CTL0, 0, ARL_UNI_LEAKY, - (a_uint8_t *) (&data), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - - if (1 == data) - { - *ctrl_mode = FAL_LEAKY_FDB_CTRL; - } - else - { - *ctrl_mode = FAL_LEAKY_PORT_CTRL; - } - - return SW_OK; -} - -static sw_error_t -_isis_mc_leaky_mode_set(a_uint32_t dev_id, - fal_leaky_ctrl_mode_t ctrl_mode) -{ - a_uint32_t data; - sw_error_t rv; - - HSL_DEV_ID_CHECK(dev_id); - - if (FAL_LEAKY_PORT_CTRL == ctrl_mode) - { - data = 0; - } - else if (FAL_LEAKY_FDB_CTRL == ctrl_mode) - { - data = 1; - } - else - { - return SW_BAD_PARAM; - } - - HSL_REG_FIELD_SET(rv, dev_id, FORWARD_CTL0, 0, ARL_MUL_LEAKY, - (a_uint8_t *) (&data), sizeof (a_uint32_t)); - return rv; -} - -static sw_error_t -_isis_mc_leaky_mode_get(a_uint32_t dev_id, - fal_leaky_ctrl_mode_t *ctrl_mode) -{ - a_uint32_t data = 0; - sw_error_t rv; - - HSL_DEV_ID_CHECK(dev_id); - - HSL_REG_FIELD_GET(rv, dev_id, FORWARD_CTL0, 0, ARL_MUL_LEAKY, - (a_uint8_t *) (&data), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - - if (1 == data) - { - *ctrl_mode = FAL_LEAKY_FDB_CTRL; - } - else - { - *ctrl_mode = FAL_LEAKY_PORT_CTRL; - } - - return SW_OK; -} - -static sw_error_t -_isis_port_arp_leaky_set(a_uint32_t dev_id, fal_port_t port_id, - a_bool_t enable) -{ - a_uint32_t data; - sw_error_t rv; - - HSL_DEV_ID_CHECK(dev_id); - - if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU)) - { - return SW_BAD_PARAM; - } - - if (A_TRUE == enable) - { - data = 1; - } - else if (A_FALSE == enable) - { - data = 0; - } - else - { - return SW_BAD_PARAM; - } - - HSL_REG_FIELD_SET(rv, dev_id, PORT_LOOKUP_CTL, port_id, ARP_LEAKY_EN, - (a_uint8_t *) (&data), sizeof (a_uint32_t)); - return rv; -} - -static sw_error_t -_isis_port_arp_leaky_get(a_uint32_t dev_id, fal_port_t port_id, - a_bool_t *enable) -{ - a_uint32_t data = 0; - sw_error_t rv; - - HSL_DEV_ID_CHECK(dev_id); - - if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU)) - { - return SW_BAD_PARAM; - } - - HSL_REG_FIELD_GET(rv, dev_id, PORT_LOOKUP_CTL, port_id, ARP_LEAKY_EN, - (a_uint8_t *) (&data), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - - if (1 == data) - { - *enable = A_TRUE; - } - else - { - *enable = A_FALSE; - } - - return SW_OK; -} - -static sw_error_t -_isis_port_uc_leaky_set(a_uint32_t dev_id, fal_port_t port_id, - a_bool_t enable) -{ - a_uint32_t data; - sw_error_t rv; - - HSL_DEV_ID_CHECK(dev_id); - - if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU)) - { - return SW_BAD_PARAM; - } - - if (A_TRUE == enable) - { - data = 1; - } - else if (A_FALSE == enable) - { - data = 0; - } - else - { - return SW_BAD_PARAM; - } - - HSL_REG_FIELD_SET(rv, dev_id, PORT_LOOKUP_CTL, port_id, UNI_LEAKY_EN, - (a_uint8_t *) (&data), sizeof (a_uint32_t)); - return rv; -} - -static sw_error_t -_isis_port_uc_leaky_get(a_uint32_t dev_id, fal_port_t port_id, - a_bool_t *enable) -{ - a_uint32_t data = 0; - sw_error_t rv; - - HSL_DEV_ID_CHECK(dev_id); - - if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU)) - { - return SW_BAD_PARAM; - } - - HSL_REG_FIELD_GET(rv, dev_id, PORT_LOOKUP_CTL, port_id, UNI_LEAKY_EN, - (a_uint8_t *) (&data), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - - if (1 == data) - { - *enable = A_TRUE; - } - else - { - *enable = A_FALSE; - } - - return SW_OK; -} - -static sw_error_t -_isis_port_mc_leaky_set(a_uint32_t dev_id, fal_port_t port_id, - a_bool_t enable) -{ - a_uint32_t data; - sw_error_t rv; - - HSL_DEV_ID_CHECK(dev_id); - - if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU)) - { - return SW_BAD_PARAM; - } - - if (A_TRUE == enable) - { - data = 1; - } - else if (A_FALSE == enable) - { - data = 0; - } - else - { - return SW_BAD_PARAM; - } - - HSL_REG_FIELD_SET(rv, dev_id, PORT_LOOKUP_CTL, port_id, MUL_LEAKY_EN, - (a_uint8_t *) (&data), sizeof (a_uint32_t)); - return rv; -} - -static sw_error_t -_isis_port_mc_leaky_get(a_uint32_t dev_id, fal_port_t port_id, - a_bool_t *enable) -{ - a_uint32_t data = 0; - sw_error_t rv; - - HSL_DEV_ID_CHECK(dev_id); - - if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU)) - { - return SW_BAD_PARAM; - } - - HSL_REG_FIELD_GET(rv, dev_id, PORT_LOOKUP_CTL, port_id, MUL_LEAKY_EN, - (a_uint8_t *) (&data), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - - if (1 == data) - { - *enable = A_TRUE; - } - else - { - *enable = A_FALSE; - } - - return SW_OK; -} - -/** -* @brief Set unicast packets leaky control mode on a particular device. -* @param[in] dev_id device id -* @param[in] ctrl_mode leaky control mode -* @return SW_OK or error code -*/ -HSL_LOCAL sw_error_t -isis_uc_leaky_mode_set(a_uint32_t dev_id, - fal_leaky_ctrl_mode_t ctrl_mode) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _isis_uc_leaky_mode_set(dev_id, ctrl_mode); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Get unicast packets leaky control mode on a particular device. - * @param[in] dev_id device id - * @param[out] ctrl_mode leaky control mode - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -isis_uc_leaky_mode_get(a_uint32_t dev_id, - fal_leaky_ctrl_mode_t *ctrl_mode) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _isis_uc_leaky_mode_get(dev_id, ctrl_mode); - HSL_API_UNLOCK; - return rv; -} - -/** -* @brief Set multicast packets leaky control mode on a particular device. -* @param[in] dev_id device id -* @param[in] ctrl_mode leaky control mode -* @return SW_OK or error code -*/ -HSL_LOCAL sw_error_t -isis_mc_leaky_mode_set(a_uint32_t dev_id, - fal_leaky_ctrl_mode_t ctrl_mode) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _isis_mc_leaky_mode_set(dev_id, ctrl_mode); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Get multicast packets leaky control mode on a particular device. - * @param[in] dev_id device id - * @param[out] ctrl_mode leaky control mode - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -isis_mc_leaky_mode_get(a_uint32_t dev_id, - fal_leaky_ctrl_mode_t *ctrl_mode) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _isis_mc_leaky_mode_get(dev_id, ctrl_mode); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Set arp packets leaky status on a particular port. - * @param[in] dev_id device id - * @param[in] enable A_TRUE or A_FALSE - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -isis_port_arp_leaky_set(a_uint32_t dev_id, fal_port_t port_id, - a_bool_t enable) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _isis_port_arp_leaky_set(dev_id, port_id, enable); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Get arp packets leaky status on a particular port. - * @param[in] dev_id device id - * @param[out] enable A_TRUE or A_FALSE - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -isis_port_arp_leaky_get(a_uint32_t dev_id, fal_port_t port_id, - a_bool_t *enable) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _isis_port_arp_leaky_get(dev_id, port_id, enable); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Set unicast packets leaky status on a particular port. - * @param[in] dev_id device id - * @param[in] enable A_TRUE or A_FALSE - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -isis_port_uc_leaky_set(a_uint32_t dev_id, fal_port_t port_id, - a_bool_t enable) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _isis_port_uc_leaky_set(dev_id, port_id, enable); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Get unicast packets leaky status on a particular port. - * @param[in] dev_id device id - * @param[out] enable A_TRUE or A_FALSE - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -isis_port_uc_leaky_get(a_uint32_t dev_id, fal_port_t port_id, - a_bool_t *enable) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _isis_port_uc_leaky_get(dev_id, port_id, enable); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Set multicast packets leaky status on a particular port. - * @param[in] dev_id device id - * @param[in] enable A_TRUE or A_FALSE - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -isis_port_mc_leaky_set(a_uint32_t dev_id, fal_port_t port_id, - a_bool_t enable) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _isis_port_mc_leaky_set(dev_id, port_id, enable); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Get multicast packets leaky status on a particular port. - * @param[in] dev_id device id - * @param[out] enable A_TRUE or A_FALSE - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -isis_port_mc_leaky_get(a_uint32_t dev_id, fal_port_t port_id, - a_bool_t *enable) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _isis_port_mc_leaky_get(dev_id, port_id, enable); - HSL_API_UNLOCK; - return rv; -} - -sw_error_t -isis_leaky_init(a_uint32_t dev_id) -{ - HSL_DEV_ID_CHECK(dev_id); - -#ifndef HSL_STANDALONG - { - hsl_api_t *p_api; - - SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id)); - p_api->uc_leaky_mode_set = isis_uc_leaky_mode_set; - p_api->uc_leaky_mode_get = isis_uc_leaky_mode_get; - p_api->mc_leaky_mode_set = isis_mc_leaky_mode_set; - p_api->mc_leaky_mode_get = isis_mc_leaky_mode_get; - p_api->port_arp_leaky_set = isis_port_arp_leaky_set; - p_api->port_arp_leaky_get = isis_port_arp_leaky_get; - p_api->port_uc_leaky_set = isis_port_uc_leaky_set; - p_api->port_uc_leaky_get = isis_port_uc_leaky_get; - p_api->port_mc_leaky_set = isis_port_mc_leaky_set; - p_api->port_mc_leaky_get = isis_port_mc_leaky_get; - } -#endif - - return SW_OK; -} - -/** - * @} - */ - diff --git a/feeds/ipq807x/qca-ssdk/src/src/hsl/isis/isis_led.c b/feeds/ipq807x/qca-ssdk/src/src/hsl/isis/isis_led.c deleted file mode 100755 index 1f52c67e4..000000000 --- a/feeds/ipq807x/qca-ssdk/src/src/hsl/isis/isis_led.c +++ /dev/null @@ -1,405 +0,0 @@ -/* - * Copyright (c) 2012, 2016 The Linux Foundation. All rights reserved. - * Permission to use, copy, modify, and/or distribute this software for - * any purpose with or without fee is hereby granted, provided that the - * above copyright notice and this permission notice appear in all copies. - * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES - * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR - * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES - * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN - * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT - * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. - */ - - -/** - * @defgroup isis_led ISIS_LED - * @{ - */ -#include "sw.h" -#include "hsl.h" -#include "hsl_dev.h" -#include "isis_led.h" -#include "isis_reg.h" - -#define MAX_LED_PATTERN_ID 2 -#define LED_PATTERN_ADDR 0x50 - -static sw_error_t -_isis_led_ctrl_pattern_set(a_uint32_t dev_id, led_pattern_group_t group, - led_pattern_id_t id, led_ctrl_pattern_t * pattern) -{ - a_uint32_t data = 0, reg = 0, mode; - a_uint32_t addr; - sw_error_t rv; - - HSL_DEV_ID_CHECK(dev_id); - - if ((LED_WAN_PORT_GROUP != group) && (LED_LAN_PORT_GROUP != group)) - { - return SW_BAD_PARAM; - } - - if (id > MAX_LED_PATTERN_ID) - { - return SW_BAD_PARAM; - } - - addr = LED_PATTERN_ADDR + (id << 2); - - if (LED_ALWAYS_OFF == pattern->mode) - { - mode = 0; - } - else if (LED_ALWAYS_BLINK == pattern->mode) - { - mode = 1; - } - else if (LED_ALWAYS_ON == pattern->mode) - { - mode = 2; - } - else if (LED_PATTERN_MAP_EN == pattern->mode) - { - mode = 3; - } - else - { - return SW_BAD_PARAM; - } - SW_SET_REG_BY_FIELD(LED_CTRL, PATTERN_EN, mode, data); - - if (pattern->map & (1 << FULL_DUPLEX_LIGHT_EN)) - { - SW_SET_REG_BY_FIELD(LED_CTRL, FULL_LIGHT_EN, 1, data); - } - - if (pattern->map & (1 << HALF_DUPLEX_LIGHT_EN)) - { - SW_SET_REG_BY_FIELD(LED_CTRL, HALF_LIGHT_EN, 1, data); - } - - if (pattern->map & (1 << POWER_ON_LIGHT_EN)) - { - SW_SET_REG_BY_FIELD(LED_CTRL, POWERON_LIGHT_EN, 1, data); - } - - if (pattern->map & (1 << LINK_1000M_LIGHT_EN)) - { - SW_SET_REG_BY_FIELD(LED_CTRL, GE_LIGHT_EN, 1, data); - } - - if (pattern->map & (1 << LINK_100M_LIGHT_EN)) - { - SW_SET_REG_BY_FIELD(LED_CTRL, FE_LIGHT_EN, 1, data); - } - - if (pattern->map & (1 << LINK_10M_LIGHT_EN)) - { - SW_SET_REG_BY_FIELD(LED_CTRL, ETH_LIGHT_EN, 1, data); - } - - if (pattern->map & (1 << COLLISION_BLINK_EN)) - { - SW_SET_REG_BY_FIELD(LED_CTRL, COL_BLINK_EN, 1, data); - } - - if (pattern->map & (1 << RX_TRAFFIC_BLINK_EN)) - { - SW_SET_REG_BY_FIELD(LED_CTRL, RX_BLINK_EN, 1, data); - } - - if (pattern->map & (1 << TX_TRAFFIC_BLINK_EN)) - { - SW_SET_REG_BY_FIELD(LED_CTRL, TX_BLINK_EN, 1, data); - } - - if (pattern->map & (1 << LINKUP_OVERRIDE_EN)) - { - SW_SET_REG_BY_FIELD(LED_CTRL, LINKUP_OVER_EN, 1, data); - } - else - { - SW_SET_REG_BY_FIELD(LED_CTRL, LINKUP_OVER_EN, 0, data); - } - - if (LED_BLINK_2HZ == pattern->freq) - { - SW_SET_REG_BY_FIELD(LED_CTRL, BLINK_FREQ, 0, data); - } - else if (LED_BLINK_4HZ == pattern->freq) - { - SW_SET_REG_BY_FIELD(LED_CTRL, BLINK_FREQ, 1, data); - } - else if (LED_BLINK_8HZ == pattern->freq) - { - SW_SET_REG_BY_FIELD(LED_CTRL, BLINK_FREQ, 2, data); - } - else if (LED_BLINK_TXRX == pattern->freq) - { - SW_SET_REG_BY_FIELD(LED_CTRL, BLINK_FREQ, 3, data); - } - else - { - return SW_BAD_PARAM; - } - - HSL_REG_ENTRY_GEN_GET(rv, dev_id, addr, sizeof (a_uint32_t), - (a_uint8_t *) (®), - sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - - if (LED_WAN_PORT_GROUP == group) - { - reg &= 0xffff; - reg |= (data << 16); - } - else - { - reg &= 0xffff0000; - reg |= data; - } - - HSL_REG_ENTRY_GEN_SET(rv, dev_id, addr, sizeof (a_uint32_t), - (a_uint8_t *) (®), - sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - - if (LED_WAN_PORT_GROUP == group) - { - return SW_OK; - } - - HSL_REG_ENTRY_GET(rv, dev_id, LED_PATTERN, 0, - (a_uint8_t *) (&data), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - - if (LED_LAN_PORT_GROUP == group) - { - if (0 == id) - { - SW_SET_REG_BY_FIELD(LED_PATTERN, P3L0_MODE, mode, data); - SW_SET_REG_BY_FIELD(LED_PATTERN, P2L0_MODE, mode, data); - SW_SET_REG_BY_FIELD(LED_PATTERN, P1L0_MODE, mode, data); - } - else if (1 == id) - { - SW_SET_REG_BY_FIELD(LED_PATTERN, P3L1_MODE, mode, data); - SW_SET_REG_BY_FIELD(LED_PATTERN, P2L1_MODE, mode, data); - SW_SET_REG_BY_FIELD(LED_PATTERN, P1L1_MODE, mode, data); - } - else - { - SW_SET_REG_BY_FIELD(LED_PATTERN, P3L2_MODE, mode, data); - SW_SET_REG_BY_FIELD(LED_PATTERN, P2L2_MODE, mode, data); - SW_SET_REG_BY_FIELD(LED_PATTERN, P1L2_MODE, mode, data); - } - } - - HSL_REG_ENTRY_SET(rv, dev_id, LED_PATTERN, 0, - (a_uint8_t *) (&data), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - - return SW_OK; -} - -static sw_error_t -_isis_led_ctrl_pattern_get(a_uint32_t dev_id, led_pattern_group_t group, - led_pattern_id_t id, led_ctrl_pattern_t * pattern) -{ - a_uint32_t data = 0, reg = 0, tmp; - a_uint32_t addr; - sw_error_t rv; - - HSL_DEV_ID_CHECK(dev_id); - - if ((LED_WAN_PORT_GROUP != group) && (LED_LAN_PORT_GROUP != group)) - { - return SW_BAD_PARAM; - } - - if (id > MAX_LED_PATTERN_ID) - { - return SW_BAD_PARAM; - } - - aos_mem_zero(pattern, sizeof(led_ctrl_pattern_t)); - - addr = LED_PATTERN_ADDR + (id << 2); - - HSL_REG_ENTRY_GEN_GET(rv, dev_id, addr, sizeof (a_uint32_t), - (a_uint8_t *) (®), - sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - - if (LED_WAN_PORT_GROUP == group) - { - data = (reg >> 16) & 0xffff; - } - else - { - data = reg & 0xffff; - } - - SW_GET_FIELD_BY_REG(LED_CTRL, PATTERN_EN, tmp, data); - if (0 == tmp) - { - pattern->mode = LED_ALWAYS_OFF; - } - else if (1 == tmp) - { - pattern->mode = LED_ALWAYS_BLINK; - } - else if (2 == tmp) - { - pattern->mode = LED_ALWAYS_ON; - } - else - { - pattern->mode = LED_PATTERN_MAP_EN; - } - - SW_GET_FIELD_BY_REG(LED_CTRL, FULL_LIGHT_EN, tmp, data); - if (1 == tmp) - { - pattern->map |= (1 << FULL_DUPLEX_LIGHT_EN); - } - - SW_GET_FIELD_BY_REG(LED_CTRL, HALF_LIGHT_EN, tmp, data); - if (1 == tmp) - { - pattern->map |= (1 << HALF_DUPLEX_LIGHT_EN); - } - - SW_GET_FIELD_BY_REG(LED_CTRL, POWERON_LIGHT_EN, tmp, data); - if (1 == tmp) - { - pattern->map |= (1 << POWER_ON_LIGHT_EN); - } - - SW_GET_FIELD_BY_REG(LED_CTRL, GE_LIGHT_EN, tmp, data); - if (1 == tmp) - { - pattern->map |= (1 << LINK_1000M_LIGHT_EN); - } - - SW_GET_FIELD_BY_REG(LED_CTRL, FE_LIGHT_EN, tmp, data); - if (1 == tmp) - { - pattern->map |= (1 << LINK_100M_LIGHT_EN); - } - - SW_GET_FIELD_BY_REG(LED_CTRL, ETH_LIGHT_EN, tmp, data); - if (1 == tmp) - { - pattern->map |= (1 << LINK_10M_LIGHT_EN); - } - - SW_GET_FIELD_BY_REG(LED_CTRL, COL_BLINK_EN, tmp, data); - if (1 == tmp) - { - pattern->map |= (1 << COLLISION_BLINK_EN); - } - - SW_GET_FIELD_BY_REG(LED_CTRL, RX_BLINK_EN, tmp, data); - if (1 == tmp) - { - pattern->map |= (1 << RX_TRAFFIC_BLINK_EN); - } - - SW_GET_FIELD_BY_REG(LED_CTRL, TX_BLINK_EN, tmp, data); - if (1 == tmp) - { - pattern->map |= (1 << TX_TRAFFIC_BLINK_EN); - } - - SW_GET_FIELD_BY_REG(LED_CTRL, LINKUP_OVER_EN, tmp, data); - if (1 == tmp) - { - pattern->map |= (1 << LINKUP_OVERRIDE_EN); - } - - SW_GET_FIELD_BY_REG(LED_CTRL, BLINK_FREQ, tmp, data); - if (0 == tmp) - { - pattern->freq = LED_BLINK_2HZ; - } - else if (1 == tmp) - { - pattern->freq = LED_BLINK_4HZ; - } - else if (2 == tmp) - { - pattern->freq = LED_BLINK_8HZ; - } - else - { - pattern->freq = LED_BLINK_TXRX; - } - - return SW_OK; -} - -/** -* @brief Set led control pattern on a particular device. -* @param[in] dev_id device id -* @param[in] group pattern group, lan or wan -* @param[in] id pattern id -* @param[in] pattern led control pattern -* @return SW_OK or error code -*/ -HSL_LOCAL sw_error_t -isis_led_ctrl_pattern_set(a_uint32_t dev_id, led_pattern_group_t group, - led_pattern_id_t id, led_ctrl_pattern_t * pattern) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _isis_led_ctrl_pattern_set(dev_id, group, id, pattern); - HSL_API_UNLOCK; - return rv; -} - -/** -* @brief Get led control pattern on a particular device. -* @param[in] dev_id device id -* @param[in] group pattern group, lan or wan -* @param[in] id pattern id -* @param[out] pattern led control pattern -* @return SW_OK or error code -*/ -HSL_LOCAL sw_error_t -isis_led_ctrl_pattern_get(a_uint32_t dev_id, led_pattern_group_t group, - led_pattern_id_t id, led_ctrl_pattern_t * pattern) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _isis_led_ctrl_pattern_get(dev_id, group, id, pattern); - HSL_API_UNLOCK; - return rv; -} - -sw_error_t -isis_led_init(a_uint32_t dev_id) -{ - HSL_DEV_ID_CHECK(dev_id); - -#ifndef HSL_STANDALONG - { - hsl_api_t *p_api; - - SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id)); - p_api->led_ctrl_pattern_set = isis_led_ctrl_pattern_set; - p_api->led_ctrl_pattern_get = isis_led_ctrl_pattern_get; - } -#endif - - return SW_OK; -} - -/** - * @} - */ - diff --git a/feeds/ipq807x/qca-ssdk/src/src/hsl/isis/isis_mac_block.c b/feeds/ipq807x/qca-ssdk/src/src/hsl/isis/isis_mac_block.c deleted file mode 100755 index 6a33202dd..000000000 --- a/feeds/ipq807x/qca-ssdk/src/src/hsl/isis/isis_mac_block.c +++ /dev/null @@ -1,388 +0,0 @@ -/* - * Copyright (c) 2012, The Linux Foundation. All rights reserved. - * Permission to use, copy, modify, and/or distribute this software for - * any purpose with or without fee is hereby granted, provided that the - * above copyright notice and this permission notice appear in all copies. - * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES - * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR - * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES - * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN - * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT - * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. - */ - - -/** - * @defgroup - * @{ - */ -#include "sw.h" -#include "hsl.h" -#include "hsl_dev.h" -#include "hsl_port_prop.h" -#include "isis_port_ctrl.h" -#include "isis_mib.h" -#include "isis_misc.h" -#include "isis_reg.h" -#include "f1_phy.h" - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -static struct task_struct *mac_scan_task; -static a_bool_t qca_phy_info[7] = {A_FALSE}; -static a_bool_t qca_portvlan_mem_info[7] = {A_FALSE}; -static struct net_device *master_dev = NULL; -static fal_port_t uplink_portid =5; - -static void qca_cpu_pkt_xmit(struct net_device *dev) -{ - if (dev) - { - arp_send(ARPOP_RREQUEST, ETH_P_RARP, 0, dev, 0, NULL, - dev->dev_addr, dev->dev_addr); - } -} - -static a_bool_t -_isis_port_phy_connected(a_uint32_t dev_id, fal_port_t port_id) -{ - if ((0 == port_id) || (6 == port_id)) - { - return A_FALSE; - } - else - { - return A_TRUE; - } -} - - - -static sw_error_t qca_isis_rec_port_speed_set(a_uint32_t dev_id, fal_port_t port_id, - fal_port_speed_t speed) -{ - sw_error_t rv; - a_uint32_t reg_val; - - HSL_REG_ENTRY_GET(rv, dev_id, PORT_STATUS, port_id, - (a_uint8_t *) (®_val), sizeof (a_uint32_t)); - - if (FAL_SPEED_10 == speed) - { - SW_SET_REG_BY_FIELD(PORT_STATUS, SPEED_MODE, 0, reg_val); - SW_SET_REG_BY_FIELD(PORT_STATUS, DUPLEX_MODE, 1, reg_val); - } - else if (FAL_SPEED_100 == speed) - { - SW_SET_REG_BY_FIELD(PORT_STATUS, SPEED_MODE, 1, reg_val); - SW_SET_REG_BY_FIELD(PORT_STATUS, DUPLEX_MODE, 1, reg_val); - } - else - { - SW_SET_REG_BY_FIELD(PORT_STATUS, SPEED_MODE, 2, reg_val); - SW_SET_REG_BY_FIELD(PORT_STATUS, DUPLEX_MODE, 1, reg_val); - } - - HSL_REG_ENTRY_SET(rv, dev_id, PORT_STATUS, port_id, - (a_uint8_t *) (®_val), sizeof (a_uint32_t)); -} - - -static sw_error_t qca_isis_nor_port_speed_set(a_uint32_t dev_id, fal_port_t port_id, - fal_port_speed_t speed, fal_port_duplex_t duplex) -{ - sw_error_t rv; - a_uint32_t reg_val; - - HSL_REG_ENTRY_GET(rv, dev_id, PORT_STATUS, port_id, - (a_uint8_t *) (®_val), sizeof (a_uint32_t)); - - if (FAL_SPEED_10 == speed) - { - SW_SET_REG_BY_FIELD(PORT_STATUS, SPEED_MODE, 0, reg_val); - } - else if (FAL_SPEED_100 == speed) - { - SW_SET_REG_BY_FIELD(PORT_STATUS, SPEED_MODE, 1, reg_val); - } - else - { - SW_SET_REG_BY_FIELD(PORT_STATUS, SPEED_MODE, 2, reg_val); - } - - if (duplex == FAL_FULL_DUPLEX) - { - SW_SET_REG_BY_FIELD(PORT_STATUS, DUPLEX_MODE, 1, reg_val); - } - else - { - SW_SET_REG_BY_FIELD(PORT_STATUS, DUPLEX_MODE, 0, reg_val); - } - - HSL_REG_ENTRY_SET(rv, dev_id, PORT_STATUS, port_id, - (a_uint8_t *) (®_val), sizeof (a_uint32_t)); -} - - -static void qca_mac_ctrl_init(void) -{ - hsl_dev_t *pdev = NULL; - fal_port_t port_id; - a_uint32_t dev_id = 0, reg_val = 0, reg_save = 0; - sw_error_t rv; - - pdev = hsl_dev_ptr_get(dev_id); - if (pdev == NULL) - return; - - /* for port property set, SSDK should not generate some limitations */ - for (port_id = 0; port_id < pdev->nr_ports; port_id++) - { - if (A_FALSE == _isis_port_phy_connected(dev_id, port_id)) - continue; - - HSL_REG_ENTRY_GET(rv, dev_id, PORT_STATUS, port_id, - (a_uint8_t *) (®_val), sizeof (a_uint32_t)); - - SW_SET_REG_BY_FIELD(PORT_STATUS, LINK_EN, 0, reg_val); - - reg_save = reg_val; - - HSL_REG_ENTRY_SET(rv, dev_id, PORT_STATUS, port_id, - (a_uint8_t *) (®_save), sizeof (a_uint32_t)); - - } - - isis_mib_status_set(dev_id, A_TRUE); -} - -static void qca_mac_phy_poll(void) -{ - hsl_dev_t *pdev = NULL; - fal_port_t port_id; - a_uint32_t dev_id = 0, phy_id = 0; - a_bool_t status, lastStatus; - fal_mib_info_t counter; - fal_port_speed_t speed; - fal_port_duplex_t duplex; - a_uint32_t txok = 0; - sw_error_t rv; - a_uint32_t reg_val; - a_uint32_t index; - fal_pbmp_t uplink_portvlanmem = 0; - - pdev = hsl_dev_ptr_get(dev_id); - if (pdev == NULL) - return; - - - /* for port property set, SSDK should not generate some limitations */ - for (port_id = 0; port_id < pdev->nr_ports; port_id++) - { - if (A_FALSE == _isis_port_phy_connected(dev_id, port_id)) - continue; - - rv = hsl_port_prop_get_phyid(dev_id, port_id, &phy_id); - if (rv != SW_OK) - continue; - - status = f1_phy_get_link_status(dev_id, phy_id); - - lastStatus = qca_phy_info[phy_id]; - - if (lastStatus) - { - /*phy from up to down, disable mac rx/tx*/ - if (!status) - { - - /*make sure UNI port doesn't forward these types of pkts*/ - isis_port_bc_filter_set(dev_id, port_id, A_TRUE); - isis_port_unk_mc_filter_set(dev_id, port_id, A_TRUE); - isis_port_unk_uc_filter_set(dev_id, port_id, A_TRUE); - - /*make sure traffic from uplink port doesn't go to UNI port*/ - isis_portvlan_member_get(0, uplink_portid, &uplink_portvlanmem); - if ((0x1UL<pid); -} - - -void -qca_mac_scan_helper_exit(void) -{ - if(mac_scan_task) - { - kthread_stop(mac_scan_task); - } -} - -void qca_set_master_dev(struct net_device *dev) -{ - master_dev = dev; - -} - - - diff --git a/feeds/ipq807x/qca-ssdk/src/src/hsl/isis/isis_mib.c b/feeds/ipq807x/qca-ssdk/src/src/hsl/isis/isis_mib.c deleted file mode 100755 index d2f9d3ceb..000000000 --- a/feeds/ipq807x/qca-ssdk/src/src/hsl/isis/isis_mib.c +++ /dev/null @@ -1,663 +0,0 @@ -/* - * Copyright (c) 2012, 2016 The Linux Foundation. All rights reserved. - * Permission to use, copy, modify, and/or distribute this software for - * any purpose with or without fee is hereby granted, provided that the - * above copyright notice and this permission notice appear in all copies. - * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES - * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR - * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES - * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN - * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT - * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. - */ - - -/** - * @defgroup isis_mib ISIS_MIB - * @{ - */ -#include "sw.h" -#include "hsl.h" -#include "hsl_dev.h" -#include "hsl_port_prop.h" -#include "isis_mib.h" -#include "isis_reg.h" - -static sw_error_t -_isis_get_mib_info(a_uint32_t dev_id, fal_port_t port_id, - fal_mib_info_t * mib_info) -{ - a_uint32_t val = 0; - sw_error_t rv; - - HSL_DEV_ID_CHECK(dev_id); - - if (A_FALSE == hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU)) - { - return SW_OUT_OF_RANGE; - } - - HSL_REG_ENTRY_GET(rv, dev_id, MIB_RXBROAD, port_id, - (a_uint8_t *) (&val), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - mib_info->RxBroad = val; - - HSL_REG_ENTRY_GET(rv, dev_id, MIB_RXPAUSE, port_id, - (a_uint8_t *) (&val), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - mib_info->RxPause = val; - - HSL_REG_ENTRY_GET(rv, dev_id, MIB_RXMULTI, port_id, - (a_uint8_t *) (&val), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - mib_info->RxMulti = val; - - HSL_REG_ENTRY_GET(rv, dev_id, MIB_RXFCSERR, port_id, - (a_uint8_t *) (&val), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - mib_info->RxFcsErr = val; - - HSL_REG_ENTRY_GET(rv, dev_id, MIB_RXALLIGNERR, port_id, - (a_uint8_t *) (&val), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - mib_info->RxAllignErr = val; - - HSL_REG_ENTRY_GET(rv, dev_id, MIB_RXRUNT, port_id, (a_uint8_t *) (&val), - sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - mib_info->RxRunt = val; - - HSL_REG_ENTRY_GET(rv, dev_id, MIB_RXFRAGMENT, port_id, - (a_uint8_t *) (&val), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - mib_info->RxFragment = val; - - HSL_REG_ENTRY_GET(rv, dev_id, MIB_RX64BYTE, port_id, - (a_uint8_t *) (&val), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - mib_info->Rx64Byte = val; - - HSL_REG_ENTRY_GET(rv, dev_id, MIB_RX128BYTE, port_id, - (a_uint8_t *) (&val), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - mib_info->Rx128Byte = val; - - HSL_REG_ENTRY_GET(rv, dev_id, MIB_RX256BYTE, port_id, - (a_uint8_t *) (&val), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - mib_info->Rx256Byte = val; - - HSL_REG_ENTRY_GET(rv, dev_id, MIB_RX512BYTE, port_id, - (a_uint8_t *) (&val), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - mib_info->Rx512Byte = val; - - HSL_REG_ENTRY_GET(rv, dev_id, MIB_RX1024BYTE, port_id, - (a_uint8_t *) (&val), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - mib_info->Rx1024Byte = val; - - HSL_REG_ENTRY_GET(rv, dev_id, MIB_RX1518BYTE, port_id, - (a_uint8_t *) (&val), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - mib_info->Rx1518Byte = val; - - HSL_REG_ENTRY_GET(rv, dev_id, MIB_RXMAXBYTE, port_id, - (a_uint8_t *) (&val), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - mib_info->RxMaxByte = val; - - HSL_REG_ENTRY_GET(rv, dev_id, MIB_RXTOOLONG, port_id, - (a_uint8_t *) (&val), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - mib_info->RxTooLong = val; - - HSL_REG_ENTRY_GET(rv, dev_id, MIB_RXGOODBYTE_LO, port_id, - (a_uint8_t *) (&val), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - mib_info->RxGoodByte_lo = val; - - HSL_REG_ENTRY_GET(rv, dev_id, MIB_RXGOODBYTE_HI, port_id, - (a_uint8_t *) (&val), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - mib_info->RxGoodByte_hi = val; - - HSL_REG_ENTRY_GET(rv, dev_id, MIB_RXBADBYTE_LO, port_id, - (a_uint8_t *) (&val), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - mib_info->RxBadByte_lo = val; - - HSL_REG_ENTRY_GET(rv, dev_id, MIB_RXBADBYTE_HI, port_id, - (a_uint8_t *) (&val), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - mib_info->RxBadByte_hi = val; - - HSL_REG_ENTRY_GET(rv, dev_id, MIB_RXOVERFLOW, port_id, - (a_uint8_t *) (&val), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - mib_info->RxOverFlow = val; - - HSL_REG_ENTRY_GET(rv, dev_id, MIB_FILTERED, port_id, - (a_uint8_t *) (&val), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - mib_info->Filtered = val; - - HSL_REG_ENTRY_GET(rv, dev_id, MIB_TXBROAD, port_id, (a_uint8_t *) (&val), - sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - mib_info->TxBroad = val; - - HSL_REG_ENTRY_GET(rv, dev_id, MIB_TXPAUSE, port_id, (a_uint8_t *) (&val), - sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - mib_info->TxPause = val; - - HSL_REG_ENTRY_GET(rv, dev_id, MIB_TXMULTI, port_id, (a_uint8_t *) (&val), - sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - mib_info->TxMulti = val; - - HSL_REG_ENTRY_GET(rv, dev_id, MIB_TXUNDERRUN, port_id, - (a_uint8_t *) (&val), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - mib_info->TxUnderRun = val; - - HSL_REG_ENTRY_GET(rv, dev_id, MIB_TX64BYTE, port_id, - (a_uint8_t *) (&val), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - mib_info->Tx64Byte = val; - - HSL_REG_ENTRY_GET(rv, dev_id, MIB_TX128BYTE, port_id, - (a_uint8_t *) (&val), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - mib_info->Tx128Byte = val; - - HSL_REG_ENTRY_GET(rv, dev_id, MIB_TX256BYTE, port_id, - (a_uint8_t *) (&val), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - mib_info->Tx256Byte = val; - - HSL_REG_ENTRY_GET(rv, dev_id, MIB_TX512BYTE, port_id, - (a_uint8_t *) (&val), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - mib_info->Tx512Byte = val; - - HSL_REG_ENTRY_GET(rv, dev_id, MIB_TX1024BYTE, port_id, - (a_uint8_t *) (&val), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - mib_info->Tx1024Byte = val; - - HSL_REG_ENTRY_GET(rv, dev_id, MIB_TX1518BYTE, port_id, - (a_uint8_t *) (&val), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - mib_info->Tx1518Byte = val; - - HSL_REG_ENTRY_GET(rv, dev_id, MIB_TXMAXBYTE, port_id, - (a_uint8_t *) (&val), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - mib_info->TxMaxByte = val; - - HSL_REG_ENTRY_GET(rv, dev_id, MIB_TXOVERSIZE, port_id, - (a_uint8_t *) (&val), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - mib_info->TxOverSize = val; - - HSL_REG_ENTRY_GET(rv, dev_id, MIB_TXBYTE_LO, port_id, - (a_uint8_t *) (&val), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - mib_info->TxByte_lo = val; - - HSL_REG_ENTRY_GET(rv, dev_id, MIB_TXBYTE_HI, port_id, - (a_uint8_t *) (&val), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - mib_info->TxByte_hi = val; - - HSL_REG_ENTRY_GET(rv, dev_id, MIB_TXCOLLISION, port_id, - (a_uint8_t *) (&val), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - mib_info->TxCollision = val; - - HSL_REG_ENTRY_GET(rv, dev_id, MIB_TXABORTCOL, port_id, - (a_uint8_t *) (&val), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - mib_info->TxAbortCol = val; - - HSL_REG_ENTRY_GET(rv, dev_id, MIB_TXMULTICOL, port_id, - (a_uint8_t *) (&val), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - mib_info->TxMultiCol = val; - - HSL_REG_ENTRY_GET(rv, dev_id, MIB_TXSINGALCOL, port_id, - (a_uint8_t *) (&val), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - mib_info->TxSingalCol = val; - - HSL_REG_ENTRY_GET(rv, dev_id, MIB_TXEXCDEFER, port_id, - (a_uint8_t *) (&val), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - mib_info->TxExcDefer = val; - - HSL_REG_ENTRY_GET(rv, dev_id, MIB_TXDEFER, port_id, (a_uint8_t *) (&val), - sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - mib_info->TxDefer = val; - - HSL_REG_ENTRY_GET(rv, dev_id, MIB_TXLATECOL, port_id, - (a_uint8_t *) (&val), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - mib_info->TxLateCol = val; - - return SW_OK; -} - -static sw_error_t -_isis_get_rx_mib_info(a_uint32_t dev_id, fal_port_t port_id, - fal_mib_info_t * mib_info) -{ - a_uint32_t val = 0; - sw_error_t rv; - - HSL_DEV_ID_CHECK(dev_id); - - if (A_FALSE == hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU)) - { - return SW_OUT_OF_RANGE; - } - - HSL_REG_ENTRY_GET(rv, dev_id, MIB_RXBROAD, port_id, - (a_uint8_t *) (&val), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - mib_info->RxBroad = val; - - HSL_REG_ENTRY_GET(rv, dev_id, MIB_RXPAUSE, port_id, - (a_uint8_t *) (&val), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - mib_info->RxPause = val; - - HSL_REG_ENTRY_GET(rv, dev_id, MIB_RXMULTI, port_id, - (a_uint8_t *) (&val), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - mib_info->RxMulti = val; - - HSL_REG_ENTRY_GET(rv, dev_id, MIB_RXFCSERR, port_id, - (a_uint8_t *) (&val), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - mib_info->RxFcsErr = val; - - HSL_REG_ENTRY_GET(rv, dev_id, MIB_RXALLIGNERR, port_id, - (a_uint8_t *) (&val), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - mib_info->RxAllignErr = val; - - HSL_REG_ENTRY_GET(rv, dev_id, MIB_RXRUNT, port_id, (a_uint8_t *) (&val), - sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - mib_info->RxRunt = val; - - HSL_REG_ENTRY_GET(rv, dev_id, MIB_RXFRAGMENT, port_id, - (a_uint8_t *) (&val), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - mib_info->RxFragment = val; - - HSL_REG_ENTRY_GET(rv, dev_id, MIB_RX64BYTE, port_id, - (a_uint8_t *) (&val), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - mib_info->Rx64Byte = val; - - HSL_REG_ENTRY_GET(rv, dev_id, MIB_RX128BYTE, port_id, - (a_uint8_t *) (&val), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - mib_info->Rx128Byte = val; - - HSL_REG_ENTRY_GET(rv, dev_id, MIB_RX256BYTE, port_id, - (a_uint8_t *) (&val), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - mib_info->Rx256Byte = val; - - HSL_REG_ENTRY_GET(rv, dev_id, MIB_RX512BYTE, port_id, - (a_uint8_t *) (&val), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - mib_info->Rx512Byte = val; - - HSL_REG_ENTRY_GET(rv, dev_id, MIB_RX1024BYTE, port_id, - (a_uint8_t *) (&val), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - mib_info->Rx1024Byte = val; - - HSL_REG_ENTRY_GET(rv, dev_id, MIB_RX1518BYTE, port_id, - (a_uint8_t *) (&val), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - mib_info->Rx1518Byte = val; - - HSL_REG_ENTRY_GET(rv, dev_id, MIB_RXMAXBYTE, port_id, - (a_uint8_t *) (&val), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - mib_info->RxMaxByte = val; - - HSL_REG_ENTRY_GET(rv, dev_id, MIB_RXTOOLONG, port_id, - (a_uint8_t *) (&val), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - mib_info->RxTooLong = val; - - HSL_REG_ENTRY_GET(rv, dev_id, MIB_RXGOODBYTE_LO, port_id, - (a_uint8_t *) (&val), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - mib_info->RxGoodByte_lo = val; - - HSL_REG_ENTRY_GET(rv, dev_id, MIB_RXGOODBYTE_HI, port_id, - (a_uint8_t *) (&val), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - mib_info->RxGoodByte_hi = val; - - HSL_REG_ENTRY_GET(rv, dev_id, MIB_RXBADBYTE_LO, port_id, - (a_uint8_t *) (&val), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - mib_info->RxBadByte_lo = val; - - HSL_REG_ENTRY_GET(rv, dev_id, MIB_RXBADBYTE_HI, port_id, - (a_uint8_t *) (&val), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - mib_info->RxBadByte_hi = val; - - HSL_REG_ENTRY_GET(rv, dev_id, MIB_RXOVERFLOW, port_id, - (a_uint8_t *) (&val), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - mib_info->RxOverFlow = val; - - HSL_REG_ENTRY_GET(rv, dev_id, MIB_FILTERED, port_id, - (a_uint8_t *) (&val), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - mib_info->Filtered = val; - - return SW_OK; -} - -static sw_error_t -_isis_get_tx_mib_info(a_uint32_t dev_id, fal_port_t port_id, - fal_mib_info_t * mib_info) -{ - a_uint32_t val = 0; - sw_error_t rv; - - HSL_DEV_ID_CHECK(dev_id); - - if (A_FALSE == hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU)) - { - return SW_OUT_OF_RANGE; - } - - HSL_REG_ENTRY_GET(rv, dev_id, MIB_TXBROAD, port_id, (a_uint8_t *) (&val), - sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - mib_info->TxBroad = val; - - HSL_REG_ENTRY_GET(rv, dev_id, MIB_TXPAUSE, port_id, (a_uint8_t *) (&val), - sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - mib_info->TxPause = val; - - HSL_REG_ENTRY_GET(rv, dev_id, MIB_TXMULTI, port_id, (a_uint8_t *) (&val), - sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - mib_info->TxMulti = val; - - HSL_REG_ENTRY_GET(rv, dev_id, MIB_TXUNDERRUN, port_id, - (a_uint8_t *) (&val), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - mib_info->TxUnderRun = val; - - HSL_REG_ENTRY_GET(rv, dev_id, MIB_TX64BYTE, port_id, - (a_uint8_t *) (&val), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - mib_info->Tx64Byte = val; - - HSL_REG_ENTRY_GET(rv, dev_id, MIB_TX128BYTE, port_id, - (a_uint8_t *) (&val), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - mib_info->Tx128Byte = val; - - HSL_REG_ENTRY_GET(rv, dev_id, MIB_TX256BYTE, port_id, - (a_uint8_t *) (&val), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - mib_info->Tx256Byte = val; - - HSL_REG_ENTRY_GET(rv, dev_id, MIB_TX512BYTE, port_id, - (a_uint8_t *) (&val), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - mib_info->Tx512Byte = val; - - HSL_REG_ENTRY_GET(rv, dev_id, MIB_TX1024BYTE, port_id, - (a_uint8_t *) (&val), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - mib_info->Tx1024Byte = val; - - HSL_REG_ENTRY_GET(rv, dev_id, MIB_TX1518BYTE, port_id, - (a_uint8_t *) (&val), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - mib_info->Tx1518Byte = val; - - HSL_REG_ENTRY_GET(rv, dev_id, MIB_TXMAXBYTE, port_id, - (a_uint8_t *) (&val), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - mib_info->TxMaxByte = val; - - HSL_REG_ENTRY_GET(rv, dev_id, MIB_TXOVERSIZE, port_id, - (a_uint8_t *) (&val), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - mib_info->TxOverSize = val; - - HSL_REG_ENTRY_GET(rv, dev_id, MIB_TXBYTE_LO, port_id, - (a_uint8_t *) (&val), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - mib_info->TxByte_lo = val; - - HSL_REG_ENTRY_GET(rv, dev_id, MIB_TXBYTE_HI, port_id, - (a_uint8_t *) (&val), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - mib_info->TxByte_hi = val; - - HSL_REG_ENTRY_GET(rv, dev_id, MIB_TXCOLLISION, port_id, - (a_uint8_t *) (&val), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - mib_info->TxCollision = val; - - HSL_REG_ENTRY_GET(rv, dev_id, MIB_TXABORTCOL, port_id, - (a_uint8_t *) (&val), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - mib_info->TxAbortCol = val; - - HSL_REG_ENTRY_GET(rv, dev_id, MIB_TXMULTICOL, port_id, - (a_uint8_t *) (&val), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - mib_info->TxMultiCol = val; - - HSL_REG_ENTRY_GET(rv, dev_id, MIB_TXSINGALCOL, port_id, - (a_uint8_t *) (&val), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - mib_info->TxSingalCol = val; - - HSL_REG_ENTRY_GET(rv, dev_id, MIB_TXEXCDEFER, port_id, - (a_uint8_t *) (&val), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - mib_info->TxExcDefer = val; - - HSL_REG_ENTRY_GET(rv, dev_id, MIB_TXDEFER, port_id, (a_uint8_t *) (&val), - sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - mib_info->TxDefer = val; - - HSL_REG_ENTRY_GET(rv, dev_id, MIB_TXLATECOL, port_id, - (a_uint8_t *) (&val), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - mib_info->TxLateCol = val; - - return SW_OK; -} - -static sw_error_t -_isis_mib_status_set(a_uint32_t dev_id, a_bool_t enable) -{ - sw_error_t rv; - a_uint32_t val; - - HSL_DEV_ID_CHECK(dev_id); - - if (A_TRUE == enable) - { - val = 1; - } - else if (A_FALSE == enable) - { - val = 0; - } - else - { - return SW_BAD_PARAM; - } - - HSL_REG_FIELD_SET(rv, dev_id, MOD_ENABLE, 0, MIB_EN, - (a_uint8_t *) (&val), sizeof (a_uint32_t)); - return rv; -} - -static sw_error_t -_isis_mib_status_get(a_uint32_t dev_id, a_bool_t * enable) -{ - sw_error_t rv; - a_uint32_t val = 0; - - HSL_DEV_ID_CHECK(dev_id); - - HSL_REG_FIELD_GET(rv, dev_id, MOD_ENABLE, 0, MIB_EN, - (a_uint8_t *) (&val), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - - if (1 == val) - { - *enable = A_TRUE; - } - else - { - *enable = A_FALSE; - } - - return SW_OK; -} - -/** - * @brief Get mib infomation on particular port. - * @param[in] dev_id device id - * @param[in] port_id port id - * @param[out] mib_info mib infomation - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -isis_get_mib_info(a_uint32_t dev_id, fal_port_t port_id, - fal_mib_info_t * mib_info) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _isis_get_mib_info(dev_id, port_id, mib_info); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Get RX mib infomation on particular port. - * @param[in] dev_id device id - * @param[in] port_id port id - * @param[out] mib_info mib infomation - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -isis_get_rx_mib_info(a_uint32_t dev_id, fal_port_t port_id, - fal_mib_info_t * mib_info) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _isis_get_rx_mib_info(dev_id, port_id, mib_info); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Get TX mib infomation on particular port. - * @param[in] dev_id device id - * @param[in] port_id port id - * @param[out] mib_info mib infomation - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -isis_get_tx_mib_info(a_uint32_t dev_id, fal_port_t port_id, - fal_mib_info_t * mib_info) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _isis_get_tx_mib_info(dev_id, port_id, mib_info); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Set mib status on a particular device. - * @param[in] dev_id device id - * @param[in] enable A_TRUE or A_FALSE - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -isis_mib_status_set(a_uint32_t dev_id, a_bool_t enable) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _isis_mib_status_set(dev_id, enable); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Get mib status on a particular device. - * @param[in] dev_id device id - * @param[out] enable A_TRUE or A_FALSE - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -isis_mib_status_get(a_uint32_t dev_id, a_bool_t * enable) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _isis_mib_status_get(dev_id, enable); - HSL_API_UNLOCK; - return rv; -} - -sw_error_t -isis_mib_init(a_uint32_t dev_id) -{ -#ifndef HSL_STANDALONG - hsl_api_t *p_api; -#endif - HSL_DEV_ID_CHECK(dev_id); - -#ifndef HSL_STANDALONG - SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id)); - - p_api->get_mib_info = isis_get_mib_info; - p_api->get_rx_mib_info = isis_get_rx_mib_info; - p_api->get_tx_mib_info = isis_get_tx_mib_info; - p_api->mib_status_set = isis_mib_status_set; - p_api->mib_status_get = isis_mib_status_get; -#endif - - return SW_OK; -} - -/** - * @} - */ - diff --git a/feeds/ipq807x/qca-ssdk/src/src/hsl/isis/isis_mirror.c b/feeds/ipq807x/qca-ssdk/src/src/hsl/isis/isis_mirror.c deleted file mode 100755 index 16a7d214e..000000000 --- a/feeds/ipq807x/qca-ssdk/src/src/hsl/isis/isis_mirror.c +++ /dev/null @@ -1,315 +0,0 @@ -/* - * Copyright (c) 2012, 2016, The Linux Foundation. All rights reserved. - * Permission to use, copy, modify, and/or distribute this software for - * any purpose with or without fee is hereby granted, provided that the - * above copyright notice and this permission notice appear in all copies. - * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES - * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR - * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES - * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN - * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT - * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. - */ - - -/** - * @defgroup isis_mirror ISIS_MIRROR - * @{ - */ -#include "sw.h" -#include "hsl.h" -#include "hsl_dev.h" -#include "hsl_port_prop.h" -#include "isis_mirror.h" -#include "isis_reg.h" - -static sw_error_t -_isis_mirr_analysis_port_set(a_uint32_t dev_id, fal_port_t port_id) -{ - sw_error_t rv; - a_uint32_t val; - - HSL_DEV_ID_CHECK(dev_id); - if (port_id != MIRROR_ANALYZER_NONE) { - if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU)) { - return SW_BAD_PARAM; - } - } - val = port_id; - HSL_REG_FIELD_SET(rv, dev_id, FORWARD_CTL0, 0, MIRROR_PORT_NUM, - (a_uint8_t *) (&val), sizeof (a_uint32_t)); - return rv; -} - -static sw_error_t -_isis_mirr_analysis_port_get(a_uint32_t dev_id, fal_port_t * port_id) -{ - sw_error_t rv; - a_uint32_t val = 0; - - HSL_DEV_ID_CHECK(dev_id); - - HSL_REG_FIELD_GET(rv, dev_id, FORWARD_CTL0, 0, MIRROR_PORT_NUM, - (a_uint8_t *) (&val), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - - *port_id = val; - return SW_OK; -} - -static sw_error_t -_isis_mirr_port_in_set(a_uint32_t dev_id, fal_port_t port_id, a_bool_t enable) -{ - sw_error_t rv; - a_uint32_t val; - - HSL_DEV_ID_CHECK(dev_id); - - if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU)) - { - return SW_BAD_PARAM; - } - - if (A_TRUE == enable) - { - val = 1; - } - else if (A_FALSE == enable) - { - val = 0; - } - else - { - return SW_BAD_PARAM; - } - - HSL_REG_FIELD_SET(rv, dev_id, PORT_LOOKUP_CTL, port_id, ING_MIRROR_EN, - (a_uint8_t *) (&val), sizeof (a_uint32_t)); - return rv; -} - -static sw_error_t -_isis_mirr_port_in_get(a_uint32_t dev_id, fal_port_t port_id, a_bool_t * enable) -{ - sw_error_t rv; - a_uint32_t val = 0; - - HSL_DEV_ID_CHECK(dev_id); - - if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU)) - { - return SW_BAD_PARAM; - } - - HSL_REG_FIELD_GET(rv, dev_id, PORT_LOOKUP_CTL, port_id, ING_MIRROR_EN, - (a_uint8_t *) (&val), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - - if (1 == val) - { - *enable = A_TRUE; - } - else - { - *enable = A_FALSE; - } - - return SW_OK; -} - -static sw_error_t -_isis_mirr_port_eg_set(a_uint32_t dev_id, fal_port_t port_id, a_bool_t enable) -{ - sw_error_t rv; - a_uint32_t val; - - HSL_DEV_ID_CHECK(dev_id); - - if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU)) - { - return SW_BAD_PARAM; - } - - if (A_TRUE == enable) - { - val = 1; - } - else if (A_FALSE == enable) - { - val = 0; - } - else - { - return SW_BAD_PARAM; - } - - HSL_REG_FIELD_SET(rv, dev_id, PORT_HOL_CTL1, port_id, EG_MIRROR_EN, - (a_uint8_t *) (&val), sizeof (a_uint32_t)); - return rv; -} - -static sw_error_t -_isis_mirr_port_eg_get(a_uint32_t dev_id, fal_port_t port_id, a_bool_t * enable) -{ - sw_error_t rv; - a_uint32_t val = 0; - - HSL_DEV_ID_CHECK(dev_id); - - if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU)) - { - return SW_BAD_PARAM; - } - - HSL_REG_FIELD_GET(rv, dev_id, PORT_HOL_CTL1, port_id, EG_MIRROR_EN, - (a_uint8_t *) (&val), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - - if (1 == val) - { - *enable = A_TRUE; - } - else - { - *enable = A_FALSE; - } - - return SW_OK; -} - -/** - * @details Comments: - * The analysis port works for both ingress and egress mirror. - * @brief Set mirror analyzer port on particular a device. - * @param[in] dev_id device id - * @param[in] port_id port id - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -isis_mirr_analysis_port_set(a_uint32_t dev_id, fal_port_t port_id) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _isis_mirr_analysis_port_set(dev_id, port_id); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Get mirror analysis port on particular a device. - * @param[in] dev_id device id - * @param[out] port_id port id - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -isis_mirr_analysis_port_get(a_uint32_t dev_id, fal_port_t * port_id) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _isis_mirr_analysis_port_get(dev_id, port_id); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Set ingress mirror status on particular a port. - * @param[in] dev_id device id - * @param[in] port_id port id - * @param[in] enable A_TRUE or A_FALSE - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -isis_mirr_port_in_set(a_uint32_t dev_id, fal_port_t port_id, a_bool_t enable) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _isis_mirr_port_in_set(dev_id, port_id, enable); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Get ingress mirror status on particular a port. - * @param[in] dev_id device id - * @param[in] port_id port id - * @param[out] enable A_TRUE or A_FALSE - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -isis_mirr_port_in_get(a_uint32_t dev_id, fal_port_t port_id, a_bool_t * enable) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _isis_mirr_port_in_get(dev_id, port_id, enable); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Set egress mirror status on a particular port. - * @param[in] dev_id device id - * @param[in] port_id port id - * @param[in] enable A_TRUE or A_FALSE - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -isis_mirr_port_eg_set(a_uint32_t dev_id, fal_port_t port_id, a_bool_t enable) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _isis_mirr_port_eg_set(dev_id, port_id, enable); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Get egress mirror status on a particular port. - * @param[in] dev_id device id - * @param[in] port_id port id - * @param[out] enable A_TRUE or A_FALSE - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -isis_mirr_port_eg_get(a_uint32_t dev_id, fal_port_t port_id, a_bool_t * enable) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _isis_mirr_port_eg_get(dev_id, port_id, enable); - HSL_API_UNLOCK; - return rv; -} - -sw_error_t -isis_mirr_init(a_uint32_t dev_id) -{ - HSL_DEV_ID_CHECK(dev_id); - -#ifndef HSL_STANDALONG - { - hsl_api_t *p_api; - - SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id)); - - p_api->mirr_analysis_port_set = isis_mirr_analysis_port_set; - p_api->mirr_analysis_port_get = isis_mirr_analysis_port_get; - p_api->mirr_port_in_set = isis_mirr_port_in_set; - p_api->mirr_port_in_get = isis_mirr_port_in_get; - p_api->mirr_port_eg_set = isis_mirr_port_eg_set; - p_api->mirr_port_eg_get = isis_mirr_port_eg_get; - } -#endif - - return SW_OK; -} - -/** - * @} - */ - diff --git a/feeds/ipq807x/qca-ssdk/src/src/hsl/isis/isis_misc.c b/feeds/ipq807x/qca-ssdk/src/src/hsl/isis/isis_misc.c deleted file mode 100755 index b2a8d3ddb..000000000 --- a/feeds/ipq807x/qca-ssdk/src/src/hsl/isis/isis_misc.c +++ /dev/null @@ -1,1835 +0,0 @@ -/* - * Copyright (c) 2012, 2015-2017, The Linux Foundation. All rights reserved. - * Permission to use, copy, modify, and/or distribute this software for - * any purpose with or without fee is hereby granted, provided that the - * above copyright notice and this permission notice appear in all copies. - * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES - * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR - * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES - * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN - * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT - * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. - */ - - -/** - * @defgroup isis_misc ISIS_MISC - * @{ - */ -#include "sw.h" -#include "hsl.h" -#include "hsl_dev.h" -#include "hsl_port_prop.h" -#include "isis_misc.h" -#include "isis_reg.h" -#include "hsl_phy.h" - - -#define ISIS_MAX_FRMAE_SIZE 9216 - -#define ARP_REQ_EN_OFFSET 6 -#define ARP_ACK_EN_OFFSET 5 -#define DHCP_EN_OFFSET 4 -#define EAPOL_EN_OFFSET 3 - -#define ISIS_SWITCH_INT_PHY_INT 0x8000 - -static sw_error_t -_isis_port_misc_property_set(a_uint32_t dev_id, fal_port_t port_id, - a_bool_t enable, a_uint32_t item) -{ - sw_error_t rv; - a_uint32_t reg = 0, val; - - HSL_DEV_ID_CHECK(dev_id); - - if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU)) - { - return SW_BAD_PARAM; - } - - if (A_TRUE == enable) - { - val = 1; - } - else if (A_FALSE == enable) - { - val = 0; - } - else - { - return SW_BAD_PARAM; - } - - if (3 >= port_id) - { - HSL_REG_ENTRY_GET(rv, dev_id, FRAME_ACK_CTL0, 0, - (a_uint8_t *) (®), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - - reg &= ~(0x1UL << ((port_id << 3) + item)); - reg |= (val << ((port_id << 3) + item)); - - HSL_REG_ENTRY_SET(rv, dev_id, FRAME_ACK_CTL0, 0, - (a_uint8_t *) (®), sizeof (a_uint32_t)); - } - else - { - HSL_REG_ENTRY_GET(rv, dev_id, FRAME_ACK_CTL1, 0, - (a_uint8_t *) (®), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - - reg &= ~(0x1UL << (((port_id - 4) << 3) + item)); - reg |= (val << (((port_id - 4) << 3) + item)); - - HSL_REG_ENTRY_SET(rv, dev_id, FRAME_ACK_CTL1, 0, - (a_uint8_t *) (®), sizeof (a_uint32_t)); - } - return rv; -} - -static sw_error_t -_isis_port_misc_property_get(a_uint32_t dev_id, fal_port_t port_id, - a_bool_t * enable, a_uint32_t item) -{ - sw_error_t rv; - a_uint32_t reg = 0, val; - - HSL_DEV_ID_CHECK(dev_id); - - if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU)) - { - return SW_BAD_PARAM; - } - - if (3 >= port_id) - { - HSL_REG_ENTRY_GET(rv, dev_id, FRAME_ACK_CTL0, 0, - (a_uint8_t *) (®), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - - val = (reg >> ((port_id << 3) + item)) & 0x1UL; - } - else - { - HSL_REG_ENTRY_GET(rv, dev_id, FRAME_ACK_CTL1, 0, - (a_uint8_t *) (®), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - - val = (reg >> (((port_id - 4) << 3) + item)) & 0x1UL; - } - - if (1 == val) - { - *enable = A_TRUE; - } - else - { - *enable = A_FALSE; - } - - return SW_OK; -} - -static sw_error_t -_isis_frame_max_size_set(a_uint32_t dev_id, a_uint32_t size) -{ - a_uint32_t data; - sw_error_t rv; - - HSL_DEV_ID_CHECK(dev_id); - - if (ISIS_MAX_FRMAE_SIZE < size) - { - return SW_BAD_PARAM; - } - - data = size; - HSL_REG_FIELD_SET(rv, dev_id, MAX_SIZE, 0, MAX_FRAME_SIZE, - (a_uint8_t *) (&data), sizeof (a_uint32_t)); - return rv; -} - -static sw_error_t -_isis_frame_max_size_get(a_uint32_t dev_id, a_uint32_t * size) -{ - a_uint32_t data = 0; - sw_error_t rv; - - HSL_DEV_ID_CHECK(dev_id); - - HSL_REG_FIELD_GET(rv, dev_id, MAX_SIZE, 0, MAX_FRAME_SIZE, - (a_uint8_t *) (&data), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - - *size = data; - return SW_OK; -} - -static sw_error_t -_isis_port_unk_uc_filter_set(a_uint32_t dev_id, fal_port_t port_id, - a_bool_t enable) -{ - sw_error_t rv; - a_uint32_t data = 0; - - HSL_DEV_ID_CHECK(dev_id); - - if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU)) - { - return SW_BAD_PARAM; - } - - HSL_REG_FIELD_GET(rv, dev_id, FORWARD_CTL1, 0, UNI_FLOOD_DP, - (a_uint8_t *) (&data), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - - if (A_TRUE == enable) - { - data &= (~((a_uint32_t) 0x1 << port_id)); - } - else if (A_FALSE == enable) - { - data |= (0x1 << port_id); - } - else - { - return SW_BAD_PARAM; - } - - HSL_REG_FIELD_SET(rv, dev_id, FORWARD_CTL1, 0, UNI_FLOOD_DP, - (a_uint8_t *) (&data), sizeof (a_uint32_t)); - return rv; -} - -static sw_error_t -_isis_port_unk_uc_filter_get(a_uint32_t dev_id, fal_port_t port_id, - a_bool_t * enable) -{ - sw_error_t rv; - a_uint32_t reg = 0, field; - - HSL_DEV_ID_CHECK(dev_id); - - if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU)) - { - return SW_BAD_PARAM; - } - - HSL_REG_FIELD_GET(rv, dev_id, FORWARD_CTL1, 0, UNI_FLOOD_DP, - (a_uint8_t *) (®), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - - field = reg & (0x1 << port_id); - if (field) - { - *enable = A_FALSE; - } - else - { - *enable = A_TRUE; - } - - return SW_OK; -} - -static sw_error_t -_isis_port_unk_mc_filter_set(a_uint32_t dev_id, fal_port_t port_id, - a_bool_t enable) -{ - sw_error_t rv; - a_uint32_t data = 0; - - HSL_DEV_ID_CHECK(dev_id); - - if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU)) - { - return SW_BAD_PARAM; - } - - HSL_REG_FIELD_GET(rv, dev_id, FORWARD_CTL1, 0, MUL_FLOOD_DP, - (a_uint8_t *) (&data), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - - if (A_TRUE == enable) - { - data &= (~((a_uint32_t) 0x1 << port_id)); - } - else if (A_FALSE == enable) - { - data |= (0x1 << port_id); - } - else - { - return SW_BAD_PARAM; - } - - HSL_REG_FIELD_SET(rv, dev_id, FORWARD_CTL1, 0, MUL_FLOOD_DP, - (a_uint8_t *) (&data), sizeof (a_uint32_t)); - return rv; -} - -static sw_error_t -_isis_port_unk_mc_filter_get(a_uint32_t dev_id, fal_port_t port_id, - a_bool_t * enable) -{ - sw_error_t rv; - a_uint32_t reg = 0, field; - - HSL_DEV_ID_CHECK(dev_id); - - if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU)) - { - return SW_BAD_PARAM; - } - - HSL_REG_FIELD_GET(rv, dev_id, FORWARD_CTL1, 0, MUL_FLOOD_DP, - (a_uint8_t *) (®), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - - field = reg & (0x1 << port_id); - if (field) - { - *enable = A_FALSE; - } - else - { - *enable = A_TRUE; - } - - return SW_OK; -} - -static sw_error_t -_isis_port_bc_filter_set(a_uint32_t dev_id, fal_port_t port_id, a_bool_t enable) -{ - sw_error_t rv; - a_uint32_t data = 0; - - HSL_DEV_ID_CHECK(dev_id); - - if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU)) - { - return SW_BAD_PARAM; - } - - HSL_REG_FIELD_GET(rv, dev_id, FORWARD_CTL1, 0, BC_FLOOD_DP, - (a_uint8_t *) (&data), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - - if (A_TRUE == enable) - { - data &= (~((a_uint32_t) 0x1 << port_id)); - } - else if (A_FALSE == enable) - { - data |= (0x1 << port_id); - } - else - { - return SW_BAD_PARAM; - } - - HSL_REG_FIELD_SET(rv, dev_id, FORWARD_CTL1, 0, BC_FLOOD_DP, - (a_uint8_t *) (&data), sizeof (a_uint32_t)); - return rv; -} - -static sw_error_t -_isis_port_bc_filter_get(a_uint32_t dev_id, fal_port_t port_id, - a_bool_t * enable) -{ - sw_error_t rv; - a_uint32_t reg = 0, field; - - HSL_DEV_ID_CHECK(dev_id); - - if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU)) - { - return SW_BAD_PARAM; - } - - HSL_REG_FIELD_GET(rv, dev_id, FORWARD_CTL1, 0, BC_FLOOD_DP, - (a_uint8_t *) (®), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - - field = reg & (0x1 << port_id); - if (field) - { - *enable = A_FALSE; - } - else - { - *enable = A_TRUE; - } - - return SW_OK; -} - -static sw_error_t -_isis_cpu_port_status_set(a_uint32_t dev_id, a_bool_t enable) -{ - sw_error_t rv; - a_uint32_t val; - - HSL_DEV_ID_CHECK(dev_id); - - if (A_TRUE == enable) - { - val = 1; - } - else if (A_FALSE == enable) - { - val = 0; - } - else - { - return SW_BAD_PARAM; - } - - HSL_REG_FIELD_SET(rv, dev_id, FORWARD_CTL0, 0, CPU_PORT_EN, - (a_uint8_t *) (&val), sizeof (a_uint32_t)); - return rv; -} - -static sw_error_t -_isis_cpu_port_status_get(a_uint32_t dev_id, a_bool_t * enable) -{ - sw_error_t rv; - a_uint32_t val = 0; - - HSL_DEV_ID_CHECK(dev_id); - - HSL_REG_FIELD_GET(rv, dev_id, FORWARD_CTL0, 0, CPU_PORT_EN, - (a_uint8_t *) (&val), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - - if (1 == val) - { - *enable = A_TRUE; - } - else - { - *enable = A_FALSE; - } - - return SW_OK; -} - -static sw_error_t -_isis_pppoe_cmd_set(a_uint32_t dev_id, fal_fwd_cmd_t cmd) -{ - sw_error_t rv; - a_uint32_t val; - - HSL_DEV_ID_CHECK(dev_id); - - if (FAL_MAC_FRWRD == cmd) - { - val = 0; - } - else if (FAL_MAC_RDT_TO_CPU == cmd) - { - val = 1; - } - else - { - return SW_NOT_SUPPORTED; - } - - HSL_REG_FIELD_SET(rv, dev_id, FORWARD_CTL0, 0, PPPOE_RDT_EN, - (a_uint8_t *) (&val), sizeof (a_uint32_t)); - return rv; -} - -static sw_error_t -_isis_pppoe_cmd_get(a_uint32_t dev_id, fal_fwd_cmd_t * cmd) -{ - sw_error_t rv; - a_uint32_t val = 0; - - HSL_DEV_ID_CHECK(dev_id); - - HSL_REG_FIELD_GET(rv, dev_id, FORWARD_CTL0, 0, PPPOE_RDT_EN, - (a_uint8_t *) (&val), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - - if (1 == val) - { - *cmd = FAL_MAC_RDT_TO_CPU; - } - else - { - *cmd = FAL_MAC_FRWRD; - } - - return SW_OK; -} - -static sw_error_t -_isis_pppoe_status_set(a_uint32_t dev_id, a_bool_t enable) -{ - sw_error_t rv; - a_uint32_t val; - - HSL_DEV_ID_CHECK(dev_id); - - if (A_TRUE == enable) - { - val = 1; - } - else if (A_FALSE == enable) - { - val = 0; - } - else - { - return SW_BAD_PARAM; - } - - HSL_REG_FIELD_SET(rv, dev_id, FRAME_ACK_CTL1, 0, PPPOE_EN, - (a_uint8_t *) (&val), sizeof (a_uint32_t)); - return rv; -} - -static sw_error_t -_isis_pppoe_status_get(a_uint32_t dev_id, a_bool_t * enable) -{ - sw_error_t rv; - a_uint32_t val = 0; - - HSL_DEV_ID_CHECK(dev_id); - - HSL_REG_FIELD_GET(rv, dev_id, FRAME_ACK_CTL1, 0, PPPOE_EN, - (a_uint8_t *) (&val), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - - if (1 == val) - { - *enable = A_TRUE; - } - else - { - *enable = A_FALSE; - } - - return SW_OK; -} - -static sw_error_t -_isis_arp_cmd_set(a_uint32_t dev_id, fal_fwd_cmd_t cmd) -{ - sw_error_t rv; - a_uint32_t val; - - HSL_DEV_ID_CHECK(dev_id); - - if (FAL_MAC_CPY_TO_CPU == cmd) - { - val = 1; - } - else if (FAL_MAC_RDT_TO_CPU == cmd) - { - val = 0; - } - else if (FAL_MAC_FRWRD == cmd) - { - val = 2; - } - else - { - return SW_NOT_SUPPORTED; - } - - HSL_REG_FIELD_SET(rv, dev_id, FORWARD_CTL0, 0, ARP_CMD, - (a_uint8_t *) (&val), sizeof (a_uint32_t)); - return rv; -} - -static sw_error_t -_isis_arp_cmd_get(a_uint32_t dev_id, fal_fwd_cmd_t * cmd) -{ - sw_error_t rv; - a_uint32_t val = 0; - - HSL_DEV_ID_CHECK(dev_id); - - HSL_REG_FIELD_GET(rv, dev_id, FORWARD_CTL0, 0, ARP_CMD, - (a_uint8_t *) (&val), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - - if (1 == val) - { - *cmd = FAL_MAC_CPY_TO_CPU; - } - else if (0 == val) - { - *cmd = FAL_MAC_RDT_TO_CPU; - } - else - { - *cmd = FAL_MAC_FRWRD; - } - - return SW_OK; -} - -static sw_error_t -_isis_eapol_cmd_set(a_uint32_t dev_id, fal_fwd_cmd_t cmd) -{ - sw_error_t rv; - a_uint32_t val; - - HSL_DEV_ID_CHECK(dev_id); - - if (FAL_MAC_CPY_TO_CPU == cmd) - { - val = 0; - } - else if (FAL_MAC_RDT_TO_CPU == cmd) - { - val = 1; - } - else - { - return SW_NOT_SUPPORTED; - } - - HSL_REG_FIELD_SET(rv, dev_id, FORWARD_CTL0, 0, EAPOL_CMD, - (a_uint8_t *) (&val), sizeof (a_uint32_t)); - return rv; -} - -static sw_error_t -_isis_eapol_cmd_get(a_uint32_t dev_id, fal_fwd_cmd_t * cmd) -{ - sw_error_t rv; - a_uint32_t val = 0; - - HSL_DEV_ID_CHECK(dev_id); - - HSL_REG_FIELD_GET(rv, dev_id, FORWARD_CTL0, 0, EAPOL_CMD, - (a_uint8_t *) (&val), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - - if (0 == val) - { - *cmd = FAL_MAC_CPY_TO_CPU; - } - else - { - *cmd = FAL_MAC_RDT_TO_CPU; - } - - return SW_OK; -} - -#define ISIS_MAX_PPPOE_SESSION 16 -#define ISIS_MAX_SESSION_ID 0xffff - -static sw_error_t -_isis_pppoe_session_add(a_uint32_t dev_id, fal_pppoe_session_t * session_tbl) -{ - sw_error_t rv; - a_uint32_t reg = 0, i, valid, id, entry_idx = ISIS_MAX_PPPOE_SESSION; - - HSL_DEV_ID_CHECK(dev_id); - - if (session_tbl->session_id > ISIS_MAX_SESSION_ID) - { - return SW_BAD_PARAM; - } - - if ((A_FALSE == session_tbl->multi_session) - && (A_TRUE == session_tbl->uni_session)) - { - return SW_BAD_PARAM; - } - - if ((A_FALSE == session_tbl->multi_session) - && (A_FALSE == session_tbl->uni_session)) - { - return SW_BAD_PARAM; - } - - for (i = 0; i < ISIS_MAX_PPPOE_SESSION; i++) - { - HSL_REG_ENTRY_GET(rv, dev_id, PPPOE_SESSION, i, - (a_uint8_t *) (®), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - - SW_GET_FIELD_BY_REG(PPPOE_SESSION, ENTRY_VALID, valid, reg); - SW_GET_FIELD_BY_REG(PPPOE_SESSION, SEESION_ID, id, reg); - - if (!valid) - { - entry_idx = i; - } - else if (id == session_tbl->session_id) - { - return SW_ALREADY_EXIST; - } - } - - if (ISIS_MAX_PPPOE_SESSION == entry_idx) - { - return SW_NO_RESOURCE; - } - - if (A_TRUE == session_tbl->uni_session) - { - SW_SET_REG_BY_FIELD(PPPOE_SESSION, ENTRY_VALID, 2, reg); - } - else - { - SW_SET_REG_BY_FIELD(PPPOE_SESSION, ENTRY_VALID, 1, reg); - } - SW_SET_REG_BY_FIELD(PPPOE_SESSION, SEESION_ID, session_tbl->session_id, - reg); - - HSL_REG_ENTRY_SET(rv, dev_id, PPPOE_SESSION, entry_idx, - (a_uint8_t *) (®), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - - session_tbl->entry_id = entry_idx; - return SW_OK; -} - -static sw_error_t -_isis_pppoe_session_del(a_uint32_t dev_id, fal_pppoe_session_t * session_tbl) -{ - sw_error_t rv; - a_uint32_t reg = 0, i, valid, id; - - HSL_DEV_ID_CHECK(dev_id); - - if (session_tbl->session_id > ISIS_MAX_SESSION_ID) - { - return SW_BAD_PARAM; - } - - for (i = 0; i < ISIS_MAX_PPPOE_SESSION; i++) - { - HSL_REG_ENTRY_GET(rv, dev_id, PPPOE_SESSION, i, - (a_uint8_t *) (®), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - - SW_GET_FIELD_BY_REG(PPPOE_SESSION, ENTRY_VALID, valid, reg); - SW_GET_FIELD_BY_REG(PPPOE_SESSION, SEESION_ID, id, reg); - - if (((1 == valid) || (2 == valid)) && (id == session_tbl->session_id)) - { - SW_SET_REG_BY_FIELD(PPPOE_SESSION, ENTRY_VALID, 0, reg); - SW_SET_REG_BY_FIELD(PPPOE_SESSION, SEESION_ID, 0, reg); - HSL_REG_ENTRY_SET(rv, dev_id, PPPOE_SESSION, i, - (a_uint8_t *) (®), sizeof (a_uint32_t)); - return rv; - } - } - - return SW_NOT_FOUND; -} - -static sw_error_t -_isis_pppoe_session_get(a_uint32_t dev_id, fal_pppoe_session_t * session_tbl) -{ - sw_error_t rv; - a_uint32_t reg = 0, i, valid, id; - - HSL_DEV_ID_CHECK(dev_id); - - if (session_tbl->session_id > ISIS_MAX_SESSION_ID) - { - return SW_BAD_PARAM; - } - - for (i = 0; i < ISIS_MAX_PPPOE_SESSION; i++) - { - HSL_REG_ENTRY_GET(rv, dev_id, PPPOE_SESSION, i, - (a_uint8_t *) (®), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - - SW_GET_FIELD_BY_REG(PPPOE_SESSION, ENTRY_VALID, valid, reg); - SW_GET_FIELD_BY_REG(PPPOE_SESSION, SEESION_ID, id, reg); - - if (((1 == valid) || (2 == valid)) && (id == session_tbl->session_id)) - { - if (1 == valid) - { - session_tbl->multi_session = A_TRUE; - session_tbl->uni_session = A_FALSE; - } - else - { - session_tbl->multi_session = A_TRUE; - session_tbl->uni_session = A_TRUE; - } - - session_tbl->entry_id = i; - return SW_OK; - } - } - - return SW_NOT_FOUND; -} - -static sw_error_t -_isis_pppoe_session_id_set(a_uint32_t dev_id, a_uint32_t index, - a_uint32_t id) -{ - sw_error_t rv; - a_uint32_t reg; - - if (ISIS_MAX_PPPOE_SESSION <= index) - { - return SW_BAD_PARAM; - } - - if (ISIS_MAX_SESSION_ID < id) - { - return SW_BAD_PARAM; - } - - reg = 0; - SW_SET_REG_BY_FIELD(PPPOE_EDIT, EDIT_ID, id, reg); - HSL_REG_ENTRY_SET(rv, dev_id, PPPOE_EDIT, index, (a_uint8_t *) (®), - sizeof (a_uint32_t)); - - return rv; -} - -static sw_error_t -_isis_pppoe_session_id_get(a_uint32_t dev_id, a_uint32_t index, - a_uint32_t * id) -{ - sw_error_t rv; - a_uint32_t reg = 0, tmp; - - if (ISIS_MAX_PPPOE_SESSION <= index) - { - return SW_BAD_PARAM; - } - - HSL_REG_ENTRY_GET(rv, dev_id, PPPOE_EDIT, index, (a_uint8_t *) (®), - sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - - tmp = 0; - SW_GET_FIELD_BY_REG(PPPOE_EDIT, EDIT_ID, tmp, reg); - *id = tmp; - return SW_OK; -} - -static sw_error_t -_isis_ripv1_status_set(a_uint32_t dev_id, a_bool_t enable) -{ - a_uint32_t data; - sw_error_t rv; - - HSL_DEV_ID_CHECK(dev_id); - - if (A_TRUE != hsl_port_prop_check(dev_id, 0, HSL_PP_INCL_CPU)) - { - return SW_BAD_PARAM; - } - - if (A_TRUE == enable) - { - data = 1; - } - else if (A_FALSE == enable) - { - data = 0; - } - else - { - return SW_BAD_PARAM; - } - - HSL_REG_FIELD_SET(rv, dev_id, FORWARD_CTL0, 0, RIP_CPY_EN, - (a_uint8_t *) (&data), sizeof (a_uint32_t)); - return rv; -} - -static sw_error_t -_isis_ripv1_status_get(a_uint32_t dev_id, a_bool_t * enable) -{ - a_uint32_t data = 0; - sw_error_t rv; - - HSL_DEV_ID_CHECK(dev_id); - - if (A_TRUE != hsl_port_prop_check(dev_id, 0, HSL_PP_INCL_CPU)) - { - return SW_BAD_PARAM; - } - - HSL_REG_FIELD_GET(rv, dev_id, FORWARD_CTL0, 0, RIP_CPY_EN, - (a_uint8_t *) (&data), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - - if (1 == data) - { - *enable = A_TRUE; - } - else - { - *enable = A_FALSE; - } - - return SW_OK; -} - -static sw_error_t -_isis_intr_mask_set(a_uint32_t dev_id, a_uint32_t intr_mask) -{ - sw_error_t rv; - a_uint32_t reg = 0; - - HSL_REG_ENTRY_GET(rv, dev_id, GBL_INT_MASK1, 0, (a_uint8_t *) (®), - sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - - if (intr_mask & FAL_SWITCH_INTR_LINK_STATUS) - { - reg |= ISIS_SWITCH_INT_PHY_INT; - } - else - { - reg &= (~ISIS_SWITCH_INT_PHY_INT); - } - - HSL_REG_ENTRY_SET(rv, dev_id, GBL_INT_MASK1, 0, (a_uint8_t *) (®), - sizeof (a_uint32_t)); - return rv; -} - -static sw_error_t -_isis_intr_mask_get(a_uint32_t dev_id, a_uint32_t * intr_mask) -{ - sw_error_t rv; - a_uint32_t reg = 0; - - *intr_mask = 0; - HSL_REG_ENTRY_GET(rv, dev_id, GBL_INT_MASK1, 0, (a_uint8_t *) (®), - sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - - if (reg & ISIS_SWITCH_INT_PHY_INT) - { - *intr_mask |= FAL_SWITCH_INTR_LINK_STATUS; - } - - return SW_OK; -} - -static sw_error_t -_isis_intr_status_get(a_uint32_t dev_id, a_uint32_t * intr_status) -{ - sw_error_t rv; - a_uint32_t reg = 0; - - *intr_status = 0; - HSL_REG_ENTRY_GET(rv, dev_id, GBL_INT_STATUS1, 0, (a_uint8_t *) (®), - sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - - if (reg & ISIS_SWITCH_INT_PHY_INT) - { - *intr_status |= FAL_SWITCH_INTR_LINK_STATUS; - } - - return SW_OK; -} - -static sw_error_t -_isis_intr_status_clear(a_uint32_t dev_id, a_uint32_t intr_status) -{ - sw_error_t rv; - a_uint32_t reg; - - reg = 0; - if (intr_status & FAL_SWITCH_INTR_LINK_STATUS) - { - reg |= ISIS_SWITCH_INT_PHY_INT; - } - - HSL_REG_ENTRY_SET(rv, dev_id, GBL_INT_STATUS1, 0, (a_uint8_t *) (®), - sizeof (a_uint32_t)); - return rv; -} - -static sw_error_t -_isis_port_link_intr_mask_set(a_uint32_t dev_id, a_uint32_t port_id, a_uint32_t intr_mask_flag) -{ - sw_error_t rv; - a_uint32_t phy_id; - hsl_phy_ops_t *phy_drv; - - HSL_DEV_ID_CHECK(dev_id); - - if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_PHY)) - { - return SW_BAD_PARAM; - } - - SW_RTN_ON_NULL (phy_drv = hsl_phy_api_ops_get (dev_id, port_id)); - if (NULL == phy_drv->phy_intr_mask_set) - return SW_NOT_SUPPORTED; - - rv = hsl_port_prop_get_phyid(dev_id, port_id, &phy_id); - SW_RTN_ON_ERROR(rv); - - rv = phy_drv->phy_intr_mask_set(dev_id, phy_id, intr_mask_flag); - return rv; -} - -static sw_error_t -_isis_port_link_intr_mask_get(a_uint32_t dev_id, a_uint32_t port_id, a_uint32_t * intr_mask_flag) -{ - sw_error_t rv; - a_uint32_t phy_id; - hsl_phy_ops_t *phy_drv; - - HSL_DEV_ID_CHECK(dev_id); - - if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_PHY)) - { - return SW_BAD_PARAM; - } - - SW_RTN_ON_NULL (phy_drv = hsl_phy_api_ops_get (dev_id, port_id)); - if (NULL == phy_drv->phy_intr_mask_get) - return SW_NOT_SUPPORTED; - - rv = hsl_port_prop_get_phyid(dev_id, port_id, &phy_id); - SW_RTN_ON_ERROR(rv); - - rv = phy_drv->phy_intr_mask_get(dev_id, phy_id, intr_mask_flag); - return rv; -} - -static sw_error_t -_isis_port_link_intr_status_get(a_uint32_t dev_id, a_uint32_t port_id, a_uint32_t * intr_mask_flag) -{ - sw_error_t rv; - a_uint32_t phy_id; - hsl_phy_ops_t *phy_drv; - - HSL_DEV_ID_CHECK(dev_id); - - if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_PHY)) - { - return SW_BAD_PARAM; - } - - SW_RTN_ON_NULL (phy_drv = hsl_phy_api_ops_get (dev_id, port_id)); - if (NULL == phy_drv->phy_intr_status_get) - return SW_NOT_SUPPORTED; - - rv = hsl_port_prop_get_phyid(dev_id, port_id, &phy_id); - SW_RTN_ON_ERROR(rv); - - rv = phy_drv->phy_intr_status_get(dev_id, phy_id, intr_mask_flag); - return rv; -} - -/** - * @brief Set max frame size which device can received on a particular device. - * @details Comments: - * The granularity of packets size is byte. - * @param[in] dev_id device id - * @param[in] size packet size - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -isis_frame_max_size_set(a_uint32_t dev_id, a_uint32_t size) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _isis_frame_max_size_set(dev_id, size); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Get max frame size which device can received on a particular device. - * @details Comments: - * The unit of packets size is byte. - * @param[in] dev_id device id - * @param[out] size packet size - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -isis_frame_max_size_get(a_uint32_t dev_id, a_uint32_t * size) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _isis_frame_max_size_get(dev_id, size); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Set flooding status of unknown unicast packets on a particular port. - * @details Comments: - * If enable unknown unicast packets filter on one port then unknown - * unicast packets can't flood out from this port. - * @param[in] dev_id device id - * @param[in] port_id port id - * @param[in] enable A_TRUE or A_FALSE - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -isis_port_unk_uc_filter_set(a_uint32_t dev_id, fal_port_t port_id, - a_bool_t enable) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _isis_port_unk_uc_filter_set(dev_id, port_id, enable); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Get flooding status of unknown unicast packets on a particular port. - * @param[in] dev_id device id - * @param[in] port_id port id - * @param[out] enable A_TRUE or A_FALSE - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -isis_port_unk_uc_filter_get(a_uint32_t dev_id, fal_port_t port_id, - a_bool_t * enable) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _isis_port_unk_uc_filter_get(dev_id, port_id, enable); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Set flooding status of unknown multicast packets on a particular port. - * @details Comments: - * If enable unknown multicast packets filter on one port then unknown - * multicast packets can't flood out from this port. - * @param[in] dev_id device id - * @param[in] port_id port id - * @param[in] enable A_TRUE or A_FALSE - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -isis_port_unk_mc_filter_set(a_uint32_t dev_id, fal_port_t port_id, - a_bool_t enable) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _isis_port_unk_mc_filter_set(dev_id, port_id, enable); - HSL_API_UNLOCK; - return rv; -} - -/** @brief Get flooding status of unknown multicast packets on a particular port. - * @param[in] dev_id device id - * @param[in] port_id port id - * @param[out] enable A_TRUE or A_FALSE - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -isis_port_unk_mc_filter_get(a_uint32_t dev_id, fal_port_t port_id, - a_bool_t * enable) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _isis_port_unk_mc_filter_get(dev_id, port_id, enable); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Set flooding status of broadcast packets on a particular port. - * @details Comments: - * If enable unknown multicast packets filter on one port then unknown - * multicast packets can't flood out from this port. - * @param[in] dev_id device id - * @param[in] port_id port id - * @param[in] enable A_TRUE or A_FALSE - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -isis_port_bc_filter_set(a_uint32_t dev_id, fal_port_t port_id, a_bool_t enable) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _isis_port_bc_filter_set(dev_id, port_id, enable); - HSL_API_UNLOCK; - return rv; -} - -/** @brief Get flooding status of broadcast packets on a particular port. - * @param[in] dev_id device id - * @param[in] port_id port id - * @param[out] enable A_TRUE or A_FALSE - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -isis_port_bc_filter_get(a_uint32_t dev_id, fal_port_t port_id, - a_bool_t * enable) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _isis_port_bc_filter_get(dev_id, port_id, enable); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Set cpu port status on a particular device. - * @param[in] dev_id device id - * @param[in] enable A_TRUE or A_FALSE - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -isis_cpu_port_status_set(a_uint32_t dev_id, a_bool_t enable) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _isis_cpu_port_status_set(dev_id, enable); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Get cpu port status on a particular device. - * @param[in] dev_id device id - * @param[in] enable A_TRUE or A_FALSE - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -isis_cpu_port_status_get(a_uint32_t dev_id, a_bool_t * enable) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _isis_cpu_port_status_get(dev_id, enable); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Set pppoe packets forwarding command on a particular device. - * @details comments: - * Particular device may only support parts of forwarding commands. - * Ihis operation will take effect only after enabling pppoe packets - * hardware acknowledgement - * @param[in] dev_id device id - * @param[in] cmd forwarding command - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -isis_pppoe_cmd_set(a_uint32_t dev_id, fal_fwd_cmd_t cmd) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _isis_pppoe_cmd_set(dev_id, cmd); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Get pppoe packets forwarding command on a particular device. - * @param[in] dev_id device id - * @param[out] cmd forwarding command - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -isis_pppoe_cmd_get(a_uint32_t dev_id, fal_fwd_cmd_t * cmd) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _isis_pppoe_cmd_get(dev_id, cmd); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Set pppoe packets hardware acknowledgement status on particular device. - * @details comments: - * Particular device may only support parts of pppoe packets. - * @param[in] dev_id device id - * @param[in] enable A_TRUE or A_FALSE - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -isis_pppoe_status_set(a_uint32_t dev_id, a_bool_t enable) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _isis_pppoe_status_set(dev_id, enable); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Get pppoe packets hardware acknowledgement status on a particular device. - * @param[in] dev_id device id - * @param[out] enable A_TRUE or A_FALSE - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -isis_pppoe_status_get(a_uint32_t dev_id, a_bool_t * enable) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _isis_pppoe_status_get(dev_id, enable); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Set dhcp packets hardware acknowledgement status on a particular device. - * @param[in] dev_id device id - * @param[in] enable A_TRUE or A_FALSE - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -isis_port_dhcp_set(a_uint32_t dev_id, fal_port_t port_id, a_bool_t enable) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _isis_port_misc_property_set(dev_id, port_id, enable, DHCP_EN_OFFSET); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Get dhcp packets hardware acknowledgement status on particular device. - * @param[in] dev_id device id - * @param[out] enable A_TRUE or A_FALSE - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -isis_port_dhcp_get(a_uint32_t dev_id, fal_port_t port_id, a_bool_t * enable) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _isis_port_misc_property_get(dev_id, port_id, enable, DHCP_EN_OFFSET); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Set arp packets forwarding command on a particular device. - * @details comments: - * Particular device may only support parts of forwarding commands. - * Ihis operation will take effect only after enabling arp packets - * hardware acknowledgement - * @param[in] dev_id device id - * @param[in] cmd forwarding command - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -isis_arp_cmd_set(a_uint32_t dev_id, fal_fwd_cmd_t cmd) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _isis_arp_cmd_set(dev_id, cmd); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Get arp packets forwarding command on a particular device. - * @param[in] dev_id device id - * @param[out] cmd forwarding command - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -isis_arp_cmd_get(a_uint32_t dev_id, fal_fwd_cmd_t * cmd) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _isis_arp_cmd_get(dev_id, cmd); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Set eapol packets forwarding command on a particular device. - * @details comments: - * Particular device may only support parts of forwarding commands. - * Ihis operation will take effect only after enabling eapol packets - * hardware acknowledgement - * @param[in] dev_id device id - * @param[in] cmd forwarding command - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -isis_eapol_cmd_set(a_uint32_t dev_id, fal_fwd_cmd_t cmd) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _isis_eapol_cmd_set(dev_id, cmd); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Get eapol packets forwarding command on a particular device. - * @param[in] dev_id device id - * @param[out] cmd forwarding command - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -isis_eapol_cmd_get(a_uint32_t dev_id, fal_fwd_cmd_t * cmd) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _isis_eapol_cmd_get(dev_id, cmd); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Add a pppoe session entry to a particular device. - * The entry only for pppoe/ppp header remove. - * @param[in] dev_id device id - * @param[in] session_tbl pppoe session table - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -isis_pppoe_session_table_add(a_uint32_t dev_id, - fal_pppoe_session_t * session_tbl) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _isis_pppoe_session_add(dev_id, session_tbl); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Delete a pppoe session entry from a particular device. - * The entry only for pppoe/ppp header remove. - * @param[in] dev_id device id - * @param[in] session_tbl pppoe session table - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -isis_pppoe_session_table_del(a_uint32_t dev_id, - fal_pppoe_session_t * session_tbl) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _isis_pppoe_session_del(dev_id, session_tbl); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Get a pppoe session entry from a particular device. - * The entry only for pppoe/ppp header remove. - * @param[in] dev_id device id - * @param[out] session_tbl pppoe session table - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -isis_pppoe_session_table_get(a_uint32_t dev_id, - fal_pppoe_session_t * session_tbl) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _isis_pppoe_session_get(dev_id, session_tbl); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Set a pppoe session id entry to a particular device. - * The entry only for pppoe/ppp header add. - * @param[in] dev_id device id - * @param[in] session_tbl pppoe session table - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -isis_pppoe_session_id_set(a_uint32_t dev_id, a_uint32_t index, - a_uint32_t id) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _isis_pppoe_session_id_set(dev_id, index, id); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Get a pppoe session id entry from a particular device. - * The entry only for pppoe/ppp header add. - * @param[in] dev_id device id - * @param[out] session_tbl pppoe session table - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -isis_pppoe_session_id_get(a_uint32_t dev_id, a_uint32_t index, - a_uint32_t * id) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _isis_pppoe_session_id_get(dev_id, index, id); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Set eapol packets hardware acknowledgement status on a particular port. - * @param[in] dev_id device id - * @param[in] port_id port id - * @param[in] enable A_TRUE or A_FALSE - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -isis_eapol_status_set(a_uint32_t dev_id, a_uint32_t port_id, a_bool_t enable) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _isis_port_misc_property_set(dev_id, port_id, enable, EAPOL_EN_OFFSET); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Get eapol packets hardware acknowledgement status on a particular port. - * @param[in] dev_id device id - * @param[in] port_id port id - * @param[out] enable A_TRUE or A_FALSE - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -isis_eapol_status_get(a_uint32_t dev_id, a_uint32_t port_id, a_bool_t * enable) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _isis_port_misc_property_get(dev_id, port_id, enable, EAPOL_EN_OFFSET); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Set rip v1 packets hardware acknowledgement status on a particular port. - * @param[in] dev_id device id - * @param[in] enable A_TRUE or A_FALSE - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -isis_ripv1_status_set(a_uint32_t dev_id, a_bool_t enable) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _isis_ripv1_status_set(dev_id, enable); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Get rip v1 packets hardware acknowledgement status on a particular port. - * @param[in] dev_id device id - * @param[out] enable A_TRUE or A_FALSE - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -isis_ripv1_status_get(a_uint32_t dev_id, a_bool_t * enable) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _isis_ripv1_status_get(dev_id, enable); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Set arp req packets hardware acknowledgement status on a particular device. - * @param[in] dev_id device id - * @param[in] enable A_TRUE or A_FALSE - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -isis_port_arp_req_status_set(a_uint32_t dev_id, fal_port_t port_id, - a_bool_t enable) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _isis_port_misc_property_set(dev_id, port_id, enable, - ARP_REQ_EN_OFFSET); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Get arp req packets hardware acknowledgement status on a particular device. - * @param[in] dev_id device id - * @param[out] enable A_TRUE or A_FALSE - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -isis_port_arp_req_status_get(a_uint32_t dev_id, fal_port_t port_id, - a_bool_t * enable) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _isis_port_misc_property_get(dev_id, port_id, enable, - ARP_REQ_EN_OFFSET); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Set arp ack packets hardware acknowledgement status on a particular device. - * @param[in] dev_id device id - * @param[in] enable A_TRUE or A_FALSE - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -isis_port_arp_ack_status_set(a_uint32_t dev_id, fal_port_t port_id, - a_bool_t enable) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _isis_port_misc_property_set(dev_id, port_id, enable, - ARP_ACK_EN_OFFSET); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Get arp ack packets hardware acknowledgement status on a particular device. - * @param[in] dev_id device id - * @param[out] enable A_TRUE or A_FALSE - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -isis_port_arp_ack_status_get(a_uint32_t dev_id, fal_port_t port_id, - a_bool_t * enable) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _isis_port_misc_property_get(dev_id, port_id, enable, - ARP_ACK_EN_OFFSET); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Set switch interrupt mask on one particular device. - * @param[in] dev_id device id - * @param[in] intr_mask mask - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -isis_intr_mask_set(a_uint32_t dev_id, a_uint32_t intr_mask) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _isis_intr_mask_set(dev_id, intr_mask); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Get switch interrupt mask on one particular device. - * @param[in] dev_id device id - * @param[in] intr_mask mask - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -isis_intr_mask_get(a_uint32_t dev_id, a_uint32_t * intr_mask) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _isis_intr_mask_get(dev_id, intr_mask); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Get switch interrupt status on one particular device. - * @param[in] dev_id device id - * @param[in] intr_status status - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -isis_intr_status_get(a_uint32_t dev_id, a_uint32_t * intr_status) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _isis_intr_status_get(dev_id, intr_status); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Clear switch interrupt status on one particular device. - * @param[in] dev_id device id - * @param[in] intr_status status - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -isis_intr_status_clear(a_uint32_t dev_id, a_uint32_t intr_status) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _isis_intr_status_clear(dev_id, intr_status); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Set link interrupt mask on particular port. - * @param[in] dev_id device id - * @param[in] port_id port id - * @param[in] intr_mask_flag interrupt mask - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -isis_intr_port_link_mask_set(a_uint32_t dev_id, a_uint32_t port_id, a_uint32_t intr_mask_flag) -{ - sw_error_t rv; - HSL_API_LOCK; - rv = _isis_port_link_intr_mask_set(dev_id, port_id, intr_mask_flag); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Get link interrupt mask on particular port. - * @param[in] dev_id device id - * @param[in] port_id port id - * @param[out] intr_mask_flag interrupt mask - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -isis_intr_port_link_mask_get(a_uint32_t dev_id, a_uint32_t port_id, a_uint32_t * intr_mask_flag) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _isis_port_link_intr_mask_get(dev_id, port_id, intr_mask_flag); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Get link interrupt status on particular port. - * @param[in] dev_id device id - * @param[in] port_id port id - * @param[out] intr_mask_flag interrupt mask - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -isis_intr_port_link_status_get(a_uint32_t dev_id, a_uint32_t port_id, a_uint32_t * intr_mask_flag) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _isis_port_link_intr_status_get(dev_id, port_id, intr_mask_flag); - HSL_API_UNLOCK; - return rv; -} - -sw_error_t -isis_misc_init(a_uint32_t dev_id) -{ - HSL_DEV_ID_CHECK(dev_id); - -#ifndef HSL_STANDALONG - { - hsl_api_t *p_api; - - SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id)); - - p_api->frame_max_size_set = isis_frame_max_size_set; - p_api->frame_max_size_get = isis_frame_max_size_get; - p_api->port_unk_uc_filter_set = isis_port_unk_uc_filter_set; - p_api->port_unk_uc_filter_get = isis_port_unk_uc_filter_get; - p_api->port_unk_mc_filter_set = isis_port_unk_mc_filter_set; - p_api->port_unk_mc_filter_get = isis_port_unk_mc_filter_get; - p_api->port_bc_filter_set = isis_port_bc_filter_set; - p_api->port_bc_filter_get = isis_port_bc_filter_get; - p_api->cpu_port_status_set = isis_cpu_port_status_set; - p_api->cpu_port_status_get = isis_cpu_port_status_get; - p_api->pppoe_cmd_set = isis_pppoe_cmd_set; - p_api->pppoe_cmd_get = isis_pppoe_cmd_get; - p_api->pppoe_status_set = isis_pppoe_status_set; - p_api->pppoe_status_get = isis_pppoe_status_get; - p_api->port_dhcp_set = isis_port_dhcp_set; - p_api->port_dhcp_get = isis_port_dhcp_get; - p_api->arp_cmd_set = isis_arp_cmd_set; - p_api->arp_cmd_get = isis_arp_cmd_get; - p_api->eapol_cmd_set = isis_eapol_cmd_set; - p_api->eapol_cmd_get = isis_eapol_cmd_get; - p_api->pppoe_session_table_add = isis_pppoe_session_table_add; - p_api->pppoe_session_table_del = isis_pppoe_session_table_del; - p_api->pppoe_session_table_get = isis_pppoe_session_table_get; - p_api->pppoe_session_id_set = isis_pppoe_session_id_set; - p_api->pppoe_session_id_get = isis_pppoe_session_id_get; - p_api->eapol_status_set = isis_eapol_status_set; - p_api->eapol_status_get = isis_eapol_status_get; - p_api->ripv1_status_set = isis_ripv1_status_set; - p_api->ripv1_status_get = isis_ripv1_status_get; - p_api->port_arp_req_status_set = isis_port_arp_req_status_set; - p_api->port_arp_req_status_get = isis_port_arp_req_status_get; - p_api->port_arp_ack_status_set = isis_port_arp_ack_status_set; - p_api->port_arp_ack_status_get = isis_port_arp_ack_status_get; - p_api->intr_mask_set = isis_intr_mask_set; - p_api->intr_mask_get = isis_intr_mask_get; - p_api->intr_status_get = isis_intr_status_get; - p_api->intr_status_clear = isis_intr_status_clear; - p_api->intr_port_link_mask_set = isis_intr_port_link_mask_set; - p_api->intr_port_link_mask_get = isis_intr_port_link_mask_get; - p_api->intr_port_link_status_get = isis_intr_port_link_status_get; - } -#endif - - return SW_OK; -} - -/** - * @} - */ diff --git a/feeds/ipq807x/qca-ssdk/src/src/hsl/isis/isis_multicast_acl.c b/feeds/ipq807x/qca-ssdk/src/src/hsl/isis/isis_multicast_acl.c deleted file mode 100755 index 19ad9c21e..000000000 --- a/feeds/ipq807x/qca-ssdk/src/src/hsl/isis/isis_multicast_acl.c +++ /dev/null @@ -1,985 +0,0 @@ -/* - * Copyright (c) 2012, 2016, The Linux Foundation. All rights reserved. - * Permission to use, copy, modify, and/or distribute this software for - * any purpose with or without fee is hereby granted, provided that the - * above copyright notice and this permission notice appear in all copies. - * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES - * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR - * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES - * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN - * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT - * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. - */ - - -#include "fal_nat.h" -#include "fal_ip.h" -#include "hsl_api.h" -#include "sw.h" -#include "hsl.h" -#include "hsl_dev.h" -#include "hsl_port_prop.h" -#include "isis_igmp.h" -#include "isis_reg.h" -#include "fal_multi.h" -#include "isis_acl.h" -#include "sal/os/aos_lock.h" - -#if 0 -/** - * I/F prototype for complete igmpv3 & mldv2 support - */ - -/*supports 32 entries*/ -#define FAL_IGMP_SG_ENTRY_MAX 32 - -typedef enum -{ - FAL_ADDR_IPV4 = 0, - FAL_ADDR_IPV6 -} fal_addr_type_t; - -typedef struct -{ - fal_addr_type_t type; - union - { - fal_ip4_addr_t ip4_addr; - fal_ip6_addr_t ip6_addr; - } u; -} fal_igmp_sg_addr_t; - -typedef struct -{ - fal_igmp_sg_addr_t source; - fal_igmp_sg_addr_t group; - fal_pbmp_t port_map; -} fal_igmp_sg_entry_t; - -/** - * @brief set PortMap of IGMP sg entry. - * search entry according to source/group address, - * update PortMap if SG entry is found, otherwise create a new sg entry. - * @param[in] dev_id device id - * @param[in-out] entry SG entry - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -isis_igmp_sg_entry_set(a_uint32_t dev_id, fal_igmp_sg_entry_t * entry); - -/** - * @brief clear PortMap of IGMP sg entry. - * search entry according to source/group address, - * update PortMap if SG entry is found, delete the entry in case PortMap was 0. - * SW_NOT_FOUND will be returned in case search failed. - * @param[in] dev_id device id - * @param[in-out] entry SG entry - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -isis_igmp_sg_entry_clear(a_uint32_t dev_id, fal_igmp_sg_entry_t * entry); - -#define MULTI_DEBUG_ -#ifdef MULTI_DEBUG_ -#define MULTI_DEBUG(x...) aos_printk(x) -#else -#define MULTI_DEBUG(x...) -#endif - -#define FAL_ACL_LIST_MULTICAST 55 -#define FAL_MULTICAST_PRI 5 - -#define MULT_ACTION_SET 1 -#define MULT_ACTION_CLEAR 1 - -static a_uint32_t rule_nr=1; - -typedef struct -{ - a_uint8_t index; //MAX is 32 - fal_igmp_sg_entry_t entry; //Stores the specific ACL rule info -} multi_acl_info_t; -#endif - -static a_uint32_t rule_nr=1; - -void -isis_multicast_init(a_uint32_t dev_id); - -HSL_LOCAL sw_error_t multi_portmap_aclreg_set(a_uint32_t pos, fal_igmp_sg_entry_t * entry); - -static multi_acl_info_t multi_acl_info[FAL_IGMP_SG_ENTRY_MAX]; -static multi_acl_info_t multi_acl_group[FAL_IGMP_SG_ENTRY_MAX]; - -static int ip6_addr_is_null(fal_ip6_addr_t *ip6) -{ - if (NULL == ip6) - { - aos_printk("Invalid ip6 address\n"); - return -1; - } - if(0 == ip6->ul[0] && 0 == ip6->ul[1] && 0 == ip6->ul[2] && 0 == ip6->ul[3]) - return 1; - else - return 0; -} -static int multi_source_is_null(fal_igmp_sg_addr_t *s) -{ - if (NULL == s) - { - aos_printk("Invalid source address\n"); - return -1; - } - if(0 == s->type && 0==s->u.ip4_addr) - return 1; - if(1 == s->type && 1 == ip6_addr_is_null(&(s->u.ip6_addr))) - return 1; - - return 0; -} - -HSL_LOCAL int iterate_multicast_acl_rule(int list_id, int start_n) -{ - a_uint32_t dev_id=0; - a_uint32_t rule_id; - sw_error_t ret; - fal_acl_rule_t rule= {0}; - - if(start_n>=FAL_IGMP_SG_ENTRY_MAX || start_n < 0) - { - return -1; - } - - for(rule_id=0; rule_id=FAL_IGMP_SG_ENTRY_MAX) - { - return -1; - } - multi_acl_info[rule_id+start_n].index = rule_id; // consider here... index is NOT related start_n - //MULTI_DEBUG("normal query1: rule dest_ip4_val=%x, src ip4=%x, dst_ip6=%x, ports=%x\n", - //rule.dest_ip4_val, rule.src_ip4_val, rule.dest_ip6_val.ul[0], rule.ports); - - if(rule.dest_ip4_val !=0 && ip6_addr_is_null(&rule.dest_ip6_val)) //only ip4 - { - multi_acl_info[rule_id+start_n].entry.group.type = FAL_ADDR_IPV4; - multi_acl_info[rule_id+start_n].entry.source.type = FAL_ADDR_IPV4; - multi_acl_info[rule_id+start_n].entry.group.u.ip4_addr = rule.dest_ip4_val; - multi_acl_info[rule_id+start_n].entry.source.u.ip4_addr = rule.src_ip4_val; - multi_acl_info[rule_id+start_n].entry.port_map= rule.ports; - } - else if(rule.dest_ip4_val ==0 && !ip6_addr_is_null(&rule.dest_ip6_val)) //only ip6 - { - multi_acl_info[rule_id+start_n].entry.group.type = FAL_ADDR_IPV6; - multi_acl_info[rule_id+start_n].entry.source.type = FAL_ADDR_IPV6; - memcpy(&(multi_acl_info[rule_id+start_n].entry.group.u.ip6_addr), &(rule.dest_ip6_val), sizeof(rule.dest_ip6_val)); - memcpy(&(multi_acl_info[rule_id+start_n].entry.source.u.ip6_addr), &(rule.src_ip6_val), sizeof(rule.src_ip6_val)); - multi_acl_info[rule_id+start_n].entry.port_map= rule.ports; - } - } - - return rule_id+start_n; -} -/* -** Iterate the total 32 multicast ACL entries. - After the function completes: - 1. Stores all multicast related ACL rules in multi_acl_info[32] - 2. return the number of multicast related ACL rules -*/ -HSL_LOCAL a_uint32_t isis_multicast_acl_query(void) -{ - int start_n; - int total_n; - //a_uint32_t i; - - start_n = iterate_multicast_acl_rule(FAL_ACL_LIST_MULTICAST, 0); - if(-1 == start_n) - aos_printk("ACL rule1 is FULL\n"); - total_n = iterate_multicast_acl_rule(FAL_ACL_LIST_MULTICAST+1, start_n); - if(-1 == total_n) - aos_printk("ACL rule2 is FULL\n"); - - MULTI_DEBUG("KKK, the total ACL rule number is %d, (G,S) number=%d\n", total_n, start_n); - /* - for(i=0;i>6)&0x3) == 0x3) || (((msk_valid>>6)&0x3) == 0x2)) - { - rv = multi_portmap_aclreg_set(i, entry); - break; - } - else if ((((msk_valid>>6)&0x3)) == 0x0 || (((msk_valid>>6)&0x3) == 0x1)) - { - rv = multi_portmap_aclreg_set(i, entry); - continue; - } - else - { - aos_printk("The rule valid bit:6 7 is wrong!!!"); - break; - } - } - return rv; -} -HSL_LOCAL sw_error_t multi_portmap_aclreg_set(a_uint32_t pos, fal_igmp_sg_entry_t * entry) -{ - a_uint32_t i, base, addr; - a_uint32_t dev_id=0; - sw_error_t rv; - a_uint32_t act[3]= {0}; - fal_pbmp_t pm; - - pm = entry->port_map; - - base = ISIS_FILTER_ACT_ADDR + (pos << 4); - for (i = 0; i < 3; i++) - { - addr = base + (i << 2); - HSL_REG_ENTRY_GEN_GET(rv, dev_id, addr, sizeof (a_uint32_t), - (a_uint8_t *) (&act[i]), - sizeof (a_uint32_t)); - //MULTI_DEBUG("2:Get register value 0x%x =%x\n", addr, act[i]); - SW_RTN_ON_ERROR(rv); - } - - act[1] &= ~(0x7<<29); // clear the high 3 bits - act[1] |= (pm&0x7)<<29; //the low 3 bits of pm means redirect port 0,1,2 - - /* New modification: update acl ACTION register from DENY to redirect */ - if (((act[2]>>6)&0x7) == 0x7) //DENY mode - { - if(pm) - { - act[2] &= ~(0x7<<6);//clear DENY bits - act[2] |= (0x1<<4); //DES_PORT_EN set 1, enable - } - } - else if (((act[2]>>4)&0x1) == 0x1) //redirect mode - { - if(pm==0) - { - act[2] &= ~(0x1<<4);//clear redirect bits - act[2] |= (0x7<<6); //set to DENY - } - } - - act[2] &= ~0xf; //clear the low 4 bits of port 3,4,5,6 - act[2] |= (pm>>3)&0xf; - - addr = base + (1<<2); - HSL_REG_ENTRY_GEN_SET(rv, dev_id, addr, sizeof (a_uint32_t), - (a_uint8_t *) (&act[1]), sizeof (a_uint32_t)); - addr = base + (2<<2); - HSL_REG_ENTRY_GEN_SET(rv, dev_id, addr, sizeof (a_uint32_t), - (a_uint8_t *) (&act[2]), sizeof (a_uint32_t)); - MULTI_DEBUG("pos=%d, before sync portmap, the new act=%x %x\n", pos, act[1],act[2]); - if((rv = isis_acl_rule_sync_multi_portmap(dev_id, pos, act)) < 0) - aos_printk("Sync multicast portmap error\n"); - return rv; -} - -HSL_LOCAL int multi_get_dp(void) -{ - a_uint32_t addr; - a_uint32_t dev_id=0; - sw_error_t rv; - int val=0; - - addr = 0x624;//GLOBAL_FW_CTRL1 - HSL_REG_ENTRY_GEN_GET(rv, dev_id, addr, sizeof (a_uint32_t), - (a_uint8_t *) (&val), - sizeof (a_uint32_t)); - if (rv != SW_OK) - aos_printk("Get entry value error\n"); - - val = (val>>24)&0x7f; //30:24, IGMP_JOIN_LEAVE_DP - - return val; -} -static int old_bind_p=-1; -HSL_LOCAL int multi_acl_bind(void) -{ - int bind_p; - int i; - - bind_p = multi_get_dp(); - if(bind_p == old_bind_p) - return 0; - old_bind_p = bind_p; - - for(i=0; i<6; i++) - { - isis_acl_list_unbind(0, FAL_ACL_LIST_MULTICAST, FAL_ACL_DIREC_IN, FAL_ACL_BIND_PORT, i); - isis_acl_list_unbind(0, FAL_ACL_LIST_MULTICAST+1, FAL_ACL_DIREC_IN, FAL_ACL_BIND_PORT, i); - } - - if(bind_p==0) - { - for(i=0; i<6; i++) - { - isis_acl_list_bind(0, FAL_ACL_LIST_MULTICAST, FAL_ACL_DIREC_IN, FAL_ACL_BIND_PORT, i); - isis_acl_list_bind(0, FAL_ACL_LIST_MULTICAST+1, FAL_ACL_DIREC_IN, FAL_ACL_BIND_PORT, i); - } - } - else - { - for(i=0; i<6; i++) - if((bind_p>>i) &0x1) - { - isis_acl_list_bind(0, FAL_ACL_LIST_MULTICAST, FAL_ACL_DIREC_IN, FAL_ACL_BIND_PORT, i); - isis_acl_list_bind(0, FAL_ACL_LIST_MULTICAST+1, FAL_ACL_DIREC_IN, FAL_ACL_BIND_PORT, i); - } - else - continue; - } - return 0; -} -/* -** Only update the related portmap from the privious input. -*/ -HSL_LOCAL sw_error_t isis_multicast_acl_update( int list_id, int acl_index, fal_igmp_sg_entry_t * entry, int action) -{ - a_uint32_t dev_id=0; - a_uint32_t rule_pos; - sw_error_t rv = SW_OK; - - if(acl_index<0) - { - aos_printk("Something is wrong...\n"); - return SW_FAIL; - } - - rule_pos = isis_acl_rule_get_offset(dev_id, list_id, multi_acl_group[acl_index].index); - if(MULT_ACTION_SET == action) - { - multi_acl_group[acl_index].entry.port_map |= entry->port_map; - if(entry->port_map == 0) - { - multi_acl_group[acl_index].entry.port_map = 0; - } - } - else if(MULT_ACTION_CLEAR == action) - multi_acl_group[acl_index].entry.port_map &= ~(entry->port_map); - - rv = multi_portmap_aclreg_set_all(rule_pos, &multi_acl_group[acl_index].entry); - - multi_acl_bind(); //Here need extra bind since IGMP join/leave would happen - return rv; -} - -HSL_LOCAL sw_error_t isis_multicast_acl_del(int list_id, int index) -{ - sw_error_t rv; - int rule_id; - - rule_id = multi_acl_group[index].index; - - rv = isis_acl_rule_delete(0, list_id, rule_id, 1); - multi_acl_bind(); //Here need extra bind since IGMP join/leave would happen - return rv; -} - -/* -** Add new acl rule with parameters: DIP, SIP, redirect port. -*/ -HSL_LOCAL sw_error_t isis_multicast_acl_add(int list_id, fal_igmp_sg_entry_t * entry) -{ - sw_error_t val; - a_uint32_t pos; - fal_acl_rule_t acl= {0}; - - /* IPv4 multicast */ - if( entry->group.type == FAL_ADDR_IPV4 ) - { - MULTI_DEBUG("KKK1, group[%d][%x], source[%d][%x]\n",entry->group.type, - entry->group.u.ip4_addr, entry->source.type, entry->source.u.ip4_addr); - - acl.rule_type = FAL_ACL_RULE_IP4; - - if(entry->group.u.ip4_addr!= 0) - { - acl.dest_ip4_val = entry->group.u.ip4_addr; - acl.dest_ip4_mask = 0xffffffff;//e->ip.dmsk.s_addr; - FAL_FIELD_FLG_SET(acl.field_flg, FAL_ACL_FIELD_IP4_DIP); - } - if(entry->source.u.ip4_addr!= 0) - { - acl.src_ip4_val = entry->source.u.ip4_addr; - acl.src_ip4_mask = 0xffffffff;//e->ip.smsk.s_addr; - FAL_FIELD_FLG_SET(acl.field_flg, FAL_ACL_FIELD_IP4_SIP); - } - if( entry->port_map==0 ) - FAL_ACTION_FLG_SET ( acl.action_flg, FAL_ACL_ACTION_DENY); - else - //FAL_FIELD_FLG_SET(acl.field_flg, FAL_ACL_FIELD_INVERSE_ALL); - FAL_ACTION_FLG_SET ( acl.action_flg, FAL_ACL_ACTION_PERMIT ); - - /* Be careful, _isis_acl_action_parse() will block FAL_ACL_ACTION_DENY action, So we change it. */ - if( entry->port_map ) - { - FAL_ACTION_FLG_SET(acl.action_flg, FAL_ACL_ACTION_REDPT); - acl.ports = entry->port_map; - } - } - else if( entry->group.type == FAL_ADDR_IPV6 ) - { - MULTI_DEBUG("KKK2, group[%d][%x], source[%d][%x], pm=%x\n",entry->group.type, - entry->group.u.ip6_addr.ul[0], entry->source.type, entry->source.u.ip6_addr.ul[0], entry->port_map); - - acl.rule_type = FAL_ACL_RULE_IP6; - - if(!ip6_addr_is_null(&(entry->group.u.ip6_addr))) - { - memcpy(&acl.dest_ip6_val, &(entry->group.u.ip6_addr), sizeof(entry->group.u.ip6_addr)); - acl.dest_ip6_mask.ul[0] = 0xffffffff; - acl.dest_ip6_mask.ul[1] = 0xffffffff; - acl.dest_ip6_mask.ul[2] = 0xffffffff; - acl.dest_ip6_mask.ul[3] = 0xffffffff; - FAL_FIELD_FLG_SET(acl.field_flg, FAL_ACL_FIELD_IP6_DIP); - } - if(!ip6_addr_is_null(&(entry->source.u.ip6_addr))) - { - memcpy(&acl.src_ip6_val, &(entry->source.u.ip6_addr), sizeof(entry->source.u.ip6_addr)); - acl.src_ip6_mask.ul[0] = 0xffffffff; - acl.src_ip6_mask.ul[1] = 0xffffffff; - acl.src_ip6_mask.ul[2] = 0xffffffff; - acl.src_ip6_mask.ul[3] = 0xffffffff; - FAL_FIELD_FLG_SET(acl.field_flg, FAL_ACL_FIELD_IP6_SIP); - } - - if( entry->port_map==0 ) - FAL_ACTION_FLG_SET ( acl.action_flg, FAL_ACL_ACTION_DENY); - else - //FAL_FIELD_FLG_SET(acl.field_flg, FAL_ACL_FIELD_INVERSE_ALL); - FAL_ACTION_FLG_SET ( acl.action_flg, FAL_ACL_ACTION_PERMIT ); - - /* Be careful, _isis_acl_action_parse() will block FAL_ACL_ACTION_DENY action, So we change it. */ - if( entry->port_map ) - { - FAL_ACTION_FLG_SET(acl.action_flg, FAL_ACL_ACTION_REDPT); - acl.ports = entry->port_map; - } - } - - pos = isis_multicast_acl_total_n(list_id); - - MULTI_DEBUG("In isis_multicast_acl_add, list_id=%d, rule_id=%d\n", list_id, pos); - val = isis_acl_rule_add(0, list_id, pos, rule_nr, &acl); - - multi_acl_bind(); - - return val; -} - - -HSL_LOCAL int iterate_multicast_acl_group(a_uint32_t number, fal_igmp_sg_entry_t * entry) -{ - int count=0; - int i; - - if (number == 0) - return 0; //no any ACL rules based the query - - for(i=0; igroup.type, entry->group.u.ip6_addr.ul[0], entry->port_map);*/ - - if(0 == memcmp(&(multi_acl_info[i].entry.group), &(entry->group), sizeof(entry->group))) - { - memcpy(&multi_acl_group[count], &multi_acl_info[i], sizeof(multi_acl_info[i])); - count++;//return the real number of multi_acl_group[] - MULTI_DEBUG("in iterate_multicast_acl_group, count=%d, i=%d\n", count, i); - } - } - - return count; -} - -HSL_LOCAL int mult_acl_has_entry(fal_igmp_sg_addr_t * group, fal_igmp_sg_addr_t *source) -{ - int rule_id; - int ret = 0; -#if 0 - if(source != NULL) - { - MULTI_DEBUG("new group[%d]= %x %x %x %x, new source[%d]=%x %x %x %x\n", - group->type, group->u.ip6_addr.ul[0], group->u.ip6_addr.ul[1], group->u.ip6_addr.ul[2], group->u.ip6_addr.ul[3], - source->type, source->u.ip6_addr.ul[0], source->u.ip6_addr.ul[1], source->u.ip6_addr.ul[2], source->u.ip6_addr.ul[3]); - - MULTI_DEBUG("old group[%d]= %x %x %x %x, old source[%d]=%x %x %x %x\n", - multi_acl_group[0].entry.group.type, multi_acl_group[0].entry.group.u.ip6_addr.ul[0], - multi_acl_group[0].entry.group.u.ip6_addr.ul[1], multi_acl_group[0].entry.group.u.ip6_addr.ul[2], multi_acl_group[0].entry.group.u.ip6_addr.ul[3], - multi_acl_group[0].entry.source.type, multi_acl_group[0].entry.source.u.ip6_addr.ul[0], - multi_acl_group[0].entry.source.u.ip6_addr.ul[1], multi_acl_group[0].entry.source.u.ip6_addr.ul[2], multi_acl_group[0].entry.source.u.ip6_addr.ul[3]); - } -#endif - if(source == NULL) - { - for(rule_id=0; rule_idport_map, g_source->source.u.ip4_addr, g_source->group.u.ip4_addr, - g_star->port_map, g_star->source.u.ip4_addr,g_star->group.u.ip4_addr);*/ - - if(multi_source_is_null(&(g_star->source))) - { - if((g_source->port_map|g_star->port_map) == g_star->port_map) - { - return 0; - } - } - - return 1; -} - - -HSL_LOCAL int portmap_clear_type(int count, int index, fal_pbmp_t portmap) -{ - if(count>=0 && index0; this means there're (G,*) and (G,S) - { - //if the new clear portmap will cause (G,S)=(G,*), Delete the (G,S) - if((multi_acl_group[index].entry.port_map & (~portmap)) == multi_acl_group[count].entry.port_map) - return 1; //delete - - - //The following means there must be at least one bit clear wrong. Clear the (G,*) portmap. - if( ((multi_acl_group[index].entry.port_map & (~portmap)) & (multi_acl_group[count].entry.port_map)) - != (multi_acl_group[count].entry.port_map)) - return 0; - - return 2; //Normal update - } - return 0; -} -sw_error_t isis_igmp_sg_entry_set(a_uint32_t dev_id, fal_igmp_sg_entry_t * entry) -{ - int number, count; - int new_index=0; - sw_error_t rv; - int action = MULT_ACTION_SET; - int i=0; - - HSL_API_LOCK; - (void)isis_multicast_init(0); - aos_mem_zero(multi_acl_info, FAL_IGMP_SG_ENTRY_MAX * sizeof (multi_acl_info_t)); - aos_mem_zero(multi_acl_group, FAL_IGMP_SG_ENTRY_MAX * sizeof (multi_acl_info_t)); - MULTI_DEBUG("Before query: group=%x, source=%x, portmap=%x\n", entry->group.u.ip4_addr, entry->source.u.ip4_addr, entry->port_map); - //number is the total multicast ACL rules amount, stores in multi_acl_info[]; - number = isis_multicast_acl_query(); - if(number > FAL_IGMP_SG_ENTRY_MAX) - return SW_FAIL; - //count the total specific multicast group ACL rules, stores in multi_acl_group[]; count <=number - count = iterate_multicast_acl_group(number, entry); - //new_index-1 is the found entry index in multi_acl_group[], the real index is [new_index-1], 0 means no entry - new_index = mult_acl_has_entry(&entry->group, &entry->source); - - MULTI_DEBUG("Start entry set: number=%d, count=%d, new_index=%d, pm=%x\n", number, count, new_index, entry->port_map); - if( 0==multi_source_is_null(&entry->source) ) // new entry is (G, S) - { - MULTI_DEBUG("the new entry is (G,S)\n"); - if(count>0 && 0 == portmap_valid(entry, &(multi_acl_group[count-1].entry))) //specfic group entry exist,(G,S) or (G,*) - { - //return SW_NO_CHANGE; // The new portmap is Not valid - MULTI_DEBUG("KKK, modified 1 !!!\n"); - } - - if(0 == new_index) //new entry, need add - { -#if 0 - /*The method: - 1. predict if the portmap should be modified. - 2. add new acl rule with new portmap value. - */ - if((tmp_index = mult_acl_has_entry(&entry->group, NULL))>0) // (G, *) entry exist - { - /*Here the update should new (G, S) OR orignal (G,*) portmap, - be careful, entry's portmap value will be modified, so I use tmp_entry. - */ - memcpy(tmp_entry, entry, sizeof(fal_igmp_sg_entry_t)); - MULTI_DEBUG("Here, (G,*) exist! tmp_index=%d\n", tmp_index); - sw_multicast_acl_update(FAL_ACL_LIST_MULTICAST+1, tmp_index-1, tmp_entry, action); - - isis_multicast_acl_add(FAL_ACL_LIST_MULTICAST, tmp_entry); - return SW_OK; - } -#endif - isis_multicast_acl_add(FAL_ACL_LIST_MULTICAST, entry); - MULTI_DEBUG("Here, need add (G, S), portmap=%x\n", entry->port_map); - return SW_OK; - } - else - { - //Here update Just: the old exist entry portmap OR the new entry portmap - isis_multicast_acl_update(FAL_ACL_LIST_MULTICAST, new_index-1, entry, action); - return SW_OK; - } - } //end of memcmp - else // new entry is (G, *) - { - if(0 == new_index) //new entry, need add - { - isis_multicast_acl_add(FAL_ACL_LIST_MULTICAST+1, entry); - rv = SW_OK; - } - else if(new_index > 0) // (G, *) entry exist? - { - //Update exist (G, *) portmap with new portmap - MULTI_DEBUG("(G,*) exist, before update, new_index=%d\n", new_index ); - isis_multicast_acl_update(FAL_ACL_LIST_MULTICAST+1, new_index-1, entry, action); - rv = SW_OK; - } - - if(new_index>0&&count>1) //(G,S*) and (G,*) exist, new entry is (G,*) - { - for(i=count-2; i>=0&&i0) //only exist (G,S*) orignally - { - for(i=count-1; i>=0&&iport_map); - isis_multicast_acl_del(FAL_ACL_LIST_MULTICAST, i); - rv = SW_NO_MORE; - } - else - { - MULTI_DEBUG("2:Start update all (G,S),i=%d, portmap=%x\n", i, entry->port_map); - //Update all (G,S) entry portmap with new(G, *) portmap - isis_multicast_acl_update(FAL_ACL_LIST_MULTICAST, i, entry, action); - rv = SW_OK; - } - } - } - } - HSL_API_UNLOCK; - return rv; -} - -sw_error_t isis_igmp_sg_entry_clear(a_uint32_t dev_id, fal_igmp_sg_entry_t * entry) -{ - a_uint32_t number, count; - int new_index=0; - sw_error_t rv = SW_OK; - int action= MULT_ACTION_CLEAR; - int i=0; - int pm_type; - - HSL_API_LOCK; - (void)isis_multicast_init(0); - aos_mem_zero(multi_acl_info, FAL_IGMP_SG_ENTRY_MAX * sizeof (multi_acl_info_t)); - aos_mem_zero(multi_acl_group, FAL_IGMP_SG_ENTRY_MAX * sizeof (multi_acl_info_t)); - //number is the total multicast ACL rules amount, stores in multi_acl_info[]; - number = isis_multicast_acl_query(); - if(number > FAL_IGMP_SG_ENTRY_MAX) - return SW_FAIL; - - //count the total specific multicast group ACL rules, stores in multi_acl_group[]; count <=number - count = iterate_multicast_acl_group(number, entry); - if(count == 0) - return SW_OK; - - //new_index-1 is the found entry index in multi_acl_group[] - new_index = mult_acl_has_entry(&entry->group, &entry->source); - - MULTI_DEBUG("Start entry clear: number=%d, count=%d, new_index=%d\n", number, count, new_index); - if(0 == new_index || new_index > FAL_IGMP_SG_ENTRY_MAX ||count > FAL_IGMP_SG_ENTRY_MAX) //new entry, the user command is wrong - { - return SW_NO_SUCH; - } - - if( 0==multi_source_is_null(&entry->source) ) // new entry is (G, S) - { - if (portmap_null(new_index-1, entry->port_map)) - { - MULTI_DEBUG("KKK entry clear, new(G,S), with null portmap. \n"); - isis_multicast_acl_del(FAL_ACL_LIST_MULTICAST, new_index-1); - return SW_OK; - } - else - { - MULTI_DEBUG("KKK entry clear, new(G,S), with NOT null portmap. \n"); - /* If (G,*) doesn't exist, [count-1] is the last specfic group, maybe(G,*) */ - if(0 == multi_source_is_null(&(multi_acl_group[count-1].entry.source))) - { - isis_multicast_acl_update(FAL_ACL_LIST_MULTICAST, new_index-1, entry, action); - } - else //(G,*) exist - { - pm_type = portmap_clear_type(count-1, new_index-1, entry->port_map); - if(pm_type == 0) - return SW_NO_CHANGE; - else if(pm_type == 1) - { - isis_multicast_acl_del(FAL_ACL_LIST_MULTICAST, new_index-1); - return SW_OK; - } - else - { - //normal update; consider here...wangson - isis_multicast_acl_update(FAL_ACL_LIST_MULTICAST, new_index-1, entry, action); - } - } - } - return SW_OK; - } - else //clear entry is (G,*) - { - MULTI_DEBUG("Here, new_index[%d]>=0, new portmap to clear is %x\n", new_index, entry->port_map); - if (portmap_null(new_index-1, entry->port_map)) - { - isis_multicast_acl_del(FAL_ACL_LIST_MULTICAST+1, new_index-1); - rv = SW_OK; - } - else - { - MULTI_DEBUG("Update (G,*)!, new_index=%d, pm=%x\n", new_index, entry->port_map); - isis_multicast_acl_update(FAL_ACL_LIST_MULTICAST+1, new_index-1, entry, action); - } - MULTI_DEBUG("KKK, ready clear (G, S*), count=%d\n", count); -#if 0 - if(count>1) // (G, S*) entry exist, if count=1 here, only exist(G,*)entry - { - //count must >=2 - for(i=count-2; i>=0; i--) - { - if(portmap_null(i, entry->port_map)) - { - MULTI_DEBUG("portmap_null, i=%d\n", i); - isis_multicast_acl_del(FAL_ACL_LIST_MULTICAST, i); - rv = SW_NO_MORE; - } - else - { - //Update all (G,S) entry portmap with new(G, *) portmap - isis_multicast_acl_update(FAL_ACL_LIST_MULTICAST, i, entry, action); - rv = SW_OK; - } - } - } -#else - if(count>1) // (G, S*) entry exist, if count=1 here, only exist(G,*)entry - { - //count must >=2 - for(i=count-2; i>=0&&iport_map))) == - multi_acl_group[i].entry.port_map) - isis_multicast_acl_del(FAL_ACL_LIST_MULTICAST, i); - else - //Update all (G,S) entry portmap with new(G, *) portmap - isis_multicast_acl_update(FAL_ACL_LIST_MULTICAST, i, entry, action); - rv = SW_OK; - } - } -#endif - } - HSL_API_UNLOCK; - return rv; -} - -static void -print_ip4addr(char * param_name, a_uint32_t * buf, - a_uint32_t size) -{ - a_uint32_t i; - fal_ip4_addr_t ip4; - - ip4 = *((fal_ip4_addr_t *) buf); - aos_printk("%s", param_name); - for (i = 0; i < 3; i++) - { - aos_printk("%d.", (ip4 >> (24 - i * 8)) & 0xff); - } - aos_printk("%d", (ip4 & 0xff)); -} -static void -print_ip6addr(char * param_name, a_uint32_t * buf, - a_uint32_t size) -{ - a_uint32_t i; - fal_ip6_addr_t ip6; - - ip6 = *(fal_ip6_addr_t *) buf; - aos_printk("%s", param_name); - for (i = 0; i < 3; i++) - { - aos_printk("%x:%x:", (ip6.ul[i] >> 16) & 0xffff, ip6.ul[i] & 0xffff); - } - aos_printk("%x:%x", (ip6.ul[3] >> 16) & 0xffff, ip6.ul[3] & 0xffff); -} -sw_error_t isis_igmp_sg_entry_show(a_uint32_t dev_id) -{ - a_uint32_t number; - int i; - - HSL_API_LOCK; - (void)isis_multicast_init(0); - aos_mem_zero(multi_acl_info, FAL_IGMP_SG_ENTRY_MAX * sizeof (multi_acl_info_t)); - aos_mem_zero(multi_acl_group, FAL_IGMP_SG_ENTRY_MAX * sizeof (multi_acl_info_t)); - //number is the total multicast ACL rules amount, stores in multi_acl_info[]; - number = isis_multicast_acl_query(); - - for(i=0; i> 16) & 0xf) << 8); - } - else - { - *hw_addr = sw_addr & 0xfff; - } - - return SW_OK; -} - -static sw_error_t -_isis_ip_prvaddr_hw_to_sw(a_uint32_t dev_id, a_uint32_t hw_addr, - fal_ip4_addr_t * sw_addr) -{ - sw_error_t rv; - a_uint32_t data = 0, addr = 0; - - HSL_REG_FIELD_GET(rv, dev_id, PRVIP_CTL, 0, BASEADDR_SEL, - (a_uint8_t *) (&data), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - - HSL_REG_FIELD_GET(rv, dev_id, PRVIP_CTL, 0, IP4_BASEADDR, - (a_uint8_t *) (&addr), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - - if (data) - { - *sw_addr = ((addr & 0xff) << 8) | (((addr >> 8) & 0xfff) << 8) - | (hw_addr & 0xff) | (((hw_addr >> 8) & 0xf) << 16); - } - else - { - *sw_addr = (addr << 12) | (hw_addr & 0xfff); - } - - return SW_OK; -} - -static sw_error_t -_isis_nat_counter_get(a_uint32_t dev_id, a_uint32_t cnt_id, - a_uint32_t counter[4]) -{ - sw_error_t rv; - a_uint32_t i, addr; - - addr = ISIS_NAT_COUTER_ADDR + (cnt_id << 4); - for (i = 0; i < 4; i++) - { - HSL_REG_ENTRY_GEN_GET(rv, dev_id, addr, sizeof (a_uint32_t), - (a_uint8_t *) (&(counter[i])), - sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - - addr += 4; - } - - return SW_OK; -} - -static sw_error_t -_isis_nat_entry_commit(a_uint32_t dev_id, a_uint32_t entry_type, a_uint32_t op) -{ - a_uint32_t busy = 1, i = 0x100, entry = 0; - sw_error_t rv; - - while (busy && --i) - { - HSL_REG_ENTRY_GET(rv, dev_id, HOST_ENTRY4, 0, (a_uint8_t *) (&entry), - sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - SW_GET_FIELD_BY_REG(HOST_ENTRY4, TBL_BUSY, busy, entry); - aos_udelay(500); - } - - if (i == 0) - { - printk("%s BUSY\n", __FUNCTION__); - return SW_BUSY; - } - - SW_SET_REG_BY_FIELD(HOST_ENTRY4, TBL_BUSY, 1, entry); - SW_SET_REG_BY_FIELD(HOST_ENTRY4, TBL_SEL, entry_type, entry); - SW_SET_REG_BY_FIELD(HOST_ENTRY4, ENTRY_FUNC, op, entry); - - HSL_REG_ENTRY_SET(rv, dev_id, HOST_ENTRY4, 0, (a_uint8_t *) (&entry), - sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - - busy = 1; - i = 0x100; - while (busy && --i) - { - HSL_REG_ENTRY_GET(rv, dev_id, HOST_ENTRY4, 0, (a_uint8_t *) (&entry), - sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - SW_GET_FIELD_BY_REG(HOST_ENTRY4, TBL_BUSY, busy, entry); - aos_udelay(500); -#if 1 - if(ISIS_NAT_ENTRY_SEARCH == op && busy) break; -#endif - } - - if (i == 0) - { - printk("%s BUSY\n", __FUNCTION__); - return SW_BUSY; - } - - /* hardware requirement, we should delay... */ - if ((ISIS_NAT_ENTRY_FLUSH == op) && (ISIS_ENTRY_NAPT == entry_type)) - { - aos_mdelay(10); - } - - /* hardware requirement, we should read again... */ - HSL_REG_ENTRY_GET(rv, dev_id, HOST_ENTRY4, 0, (a_uint8_t *) (&entry), - sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - - SW_GET_FIELD_BY_REG(HOST_ENTRY4, TBL_STAUS, busy, entry); - if (!busy) - { - if (ISIS_NAT_ENTRY_NEXT == op) - { - return SW_NO_MORE; - } - else if (ISIS_NAT_ENTRY_SEARCH == op) - { - return SW_NOT_FOUND; - } - else - { - return SW_FAIL; - } - } - - return SW_OK; -} - -static sw_error_t -_isis_nat_sw_to_hw(a_uint32_t dev_id, fal_nat_entry_t * entry, a_uint32_t reg[]) -{ - sw_error_t rv; - a_uint32_t data; - - if (FAL_NAT_ENTRY_TRANS_IPADDR_INDEX & entry->flags) - { - return SW_BAD_PARAM; - } - - reg[0] = entry->trans_addr; - - if (FAL_NAT_ENTRY_PORT_CHECK & entry->flags) - { - SW_SET_REG_BY_FIELD(NAT_ENTRY2, PORT_EN, 1, reg[2]); - SW_SET_REG_BY_FIELD(NAT_ENTRY1, PORT_RANGE, entry->port_range, reg[1]); - if (ISIS_NAT_PORT_NUM < entry->port_range) - { - return SW_BAD_PARAM; - } - SW_SET_REG_BY_FIELD(NAT_ENTRY1, PORT_NUM, entry->port_num, reg[1]); - } - else - { - SW_SET_REG_BY_FIELD(NAT_ENTRY2, PORT_EN, 0, reg[2]); - } - - rv = _isis_ip_prvaddr_sw_to_hw(dev_id, entry->src_addr, &data); - SW_RTN_ON_ERROR(rv); - - SW_SET_REG_BY_FIELD(NAT_ENTRY1, PRV_IPADDR0, data, reg[1]); - SW_SET_REG_BY_FIELD(NAT_ENTRY2, PRV_IPADDR1, (data >> 8), reg[2]); - - if (FAL_MAC_FRWRD == entry->action) - { - if (A_TRUE == entry->mirror_en) - { - SW_SET_REG_BY_FIELD(NAT_ENTRY2, ACTION, 0, reg[2]); - } - else - { - SW_SET_REG_BY_FIELD(NAT_ENTRY2, ACTION, 3, reg[2]); - } - } - else if (FAL_MAC_CPY_TO_CPU == entry->action) - { - SW_SET_REG_BY_FIELD(NAT_ENTRY2, ACTION, 2, reg[2]); - } - else if (FAL_MAC_RDT_TO_CPU == entry->action) - { - SW_SET_REG_BY_FIELD(NAT_ENTRY2, ACTION, 1, reg[2]); - } - else - { - return SW_NOT_SUPPORTED; - } - - if (A_TRUE == entry->counter_en) - { - SW_SET_REG_BY_FIELD(NAT_ENTRY2, CNT_EN, 1, reg[2]); - SW_SET_REG_BY_FIELD(NAT_ENTRY2, CNT_IDX, entry->counter_id, reg[2]); - } - - if (FAL_NAT_ENTRY_PROTOCOL_ANY & entry->flags) - { - data = 3; - } - else if ((FAL_NAT_ENTRY_PROTOCOL_TCP & entry->flags) - && (FAL_NAT_ENTRY_PROTOCOL_UDP & entry->flags)) - { - data = 2; - } - else if (FAL_NAT_ENTRY_PROTOCOL_TCP & entry->flags) - { - data = 0; - } - else if (FAL_NAT_ENTRY_PROTOCOL_UDP & entry->flags) - { - data = 1; - } - else - { - return SW_BAD_PARAM; - } - - SW_SET_REG_BY_FIELD(NAT_ENTRY2, PRO_TYP, data, reg[2]); - - SW_SET_REG_BY_FIELD(NAT_ENTRY2, HASH_KEY, entry->slct_idx, reg[2]); - - SW_SET_REG_BY_FIELD(NAT_ENTRY2, ENTRY_VALID, 1, reg[2]); - SW_SET_REG_BY_FIELD(HOST_ENTRY4, TBL_IDX, entry->entry_id, reg[4]); - return SW_OK; -} - -static sw_error_t -_isis_nat_hw_to_sw(a_uint32_t dev_id, a_uint32_t reg[], fal_nat_entry_t * entry) -{ - sw_error_t rv; - a_uint32_t data, cnt[4] = {0}; - - entry->trans_addr = reg[0]; - - SW_GET_FIELD_BY_REG(NAT_ENTRY2, PORT_EN, data, reg[2]); - if (data) - { - entry->flags |= FAL_NAT_ENTRY_PORT_CHECK; - SW_GET_FIELD_BY_REG(NAT_ENTRY1, PORT_RANGE, data, reg[1]); - entry->port_range = data; - SW_GET_FIELD_BY_REG(NAT_ENTRY1, PORT_NUM, data, reg[1]); - entry->port_num = data; - } - - SW_GET_FIELD_BY_REG(NAT_ENTRY1, PRV_IPADDR0, data, reg[1]); - entry->src_addr = data; - SW_GET_FIELD_BY_REG(NAT_ENTRY2, PRV_IPADDR1, data, reg[2]); - data = (entry->src_addr & 0xff) | (data << 8); - - rv = _isis_ip_prvaddr_hw_to_sw(dev_id, data, &(entry->src_addr)); - SW_RTN_ON_ERROR(rv); - - SW_GET_FIELD_BY_REG(NAT_ENTRY2, ACTION, data, reg[2]); - entry->action = FAL_MAC_FRWRD; - if (0 == data) - { - entry->mirror_en = A_TRUE; - } - else if (2 == data) - { - entry->action = FAL_MAC_CPY_TO_CPU; - } - else if (1 == data) - { - entry->action = FAL_MAC_RDT_TO_CPU; - } - - SW_GET_FIELD_BY_REG(NAT_ENTRY2, CNT_EN, data, reg[2]); - if (data) - { - entry->counter_en = A_TRUE; - SW_GET_FIELD_BY_REG(NAT_ENTRY2, CNT_IDX, entry->counter_id, reg[2]); - - rv = _isis_nat_counter_get(dev_id, entry->counter_id, cnt); - SW_RTN_ON_ERROR(rv); - - entry->ingress_packet = cnt[0]; - entry->ingress_byte = cnt[1]; - entry->egress_packet = cnt[2]; - entry->egress_byte = cnt[3]; - } - else - { - entry->counter_en = A_FALSE; - } - - SW_GET_FIELD_BY_REG(NAT_ENTRY2, PRO_TYP, data, reg[2]); - if (3 == data) - { - entry->flags |= FAL_NAT_ENTRY_PROTOCOL_ANY; - } - else if (2 == data) - { - entry->flags |= FAL_NAT_ENTRY_PROTOCOL_TCP; - entry->flags |= FAL_NAT_ENTRY_PROTOCOL_UDP; - } - else if (1 == data) - { - entry->flags |= FAL_NAT_ENTRY_PROTOCOL_UDP; - } - else if (0 == data) - { - entry->flags |= FAL_NAT_ENTRY_PROTOCOL_TCP; - } - - SW_GET_FIELD_BY_REG(NAT_ENTRY2, HASH_KEY, data, reg[2]); - entry->slct_idx = data; - - return SW_OK; -} - -static sw_error_t -_isis_napt_sw_to_hw(a_uint32_t dev_id, fal_napt_entry_t * entry, - a_uint32_t reg[]) -{ - sw_error_t rv; - a_uint32_t data; - - reg[0] = entry->dst_addr; - - SW_SET_REG_BY_FIELD(NAPT_ENTRY1, DST_PORT, entry->dst_port, reg[1]); - SW_SET_REG_BY_FIELD(NAPT_ENTRY1, SRC_PORT, entry->src_port, reg[1]); - SW_SET_REG_BY_FIELD(NAPT_ENTRY2, TRANS_PORT, entry->trans_port, reg[2]); - - rv = _isis_ip_prvaddr_sw_to_hw(dev_id, entry->src_addr, &data); - SW_RTN_ON_ERROR(rv); - SW_SET_REG_BY_FIELD(NAPT_ENTRY2, SRC_IPADDR, data, reg[2]); - - if (!(FAL_NAT_ENTRY_TRANS_IPADDR_INDEX & entry->flags)) - { - return SW_BAD_PARAM; - } - SW_SET_REG_BY_FIELD(NAPT_ENTRY2, TRANS_IPADDR, entry->trans_addr, reg[2]); - - if (FAL_MAC_FRWRD == entry->action) - { - if (A_TRUE == entry->mirror_en) - { - SW_SET_REG_BY_FIELD(NAPT_ENTRY3, ACTION, 0, reg[3]); - } - else - { - SW_SET_REG_BY_FIELD(NAPT_ENTRY3, ACTION, 3, reg[3]); - } - } - else if (FAL_MAC_CPY_TO_CPU == entry->action) - { - SW_SET_REG_BY_FIELD(NAPT_ENTRY3, ACTION, 2, reg[3]); - } - else if (FAL_MAC_RDT_TO_CPU == entry->action) - { - SW_SET_REG_BY_FIELD(NAPT_ENTRY3, ACTION, 1, reg[3]); - } - else - { - return SW_NOT_SUPPORTED; - } - - if (A_TRUE == entry->counter_en) - { - SW_SET_REG_BY_FIELD(NAPT_ENTRY3, CNT_EN, 1, reg[3]); - SW_SET_REG_BY_FIELD(NAPT_ENTRY3, CNT_IDX, entry->counter_id, reg[3]); - } - - data = 2; - if (FAL_NAT_ENTRY_PROTOCOL_TCP & entry->flags) - { - data = 0; - } - else if (FAL_NAT_ENTRY_PROTOCOL_UDP & entry->flags) - { - data = 1; - } - else if (FAL_NAT_ENTRY_PROTOCOL_PPTP & entry->flags) - { - data = 3; - } - SW_SET_REG_BY_FIELD(NAPT_ENTRY3, PROT_TYP, data, reg[3]); - - SW_SET_REG_BY_FIELD(NAPT_ENTRY3, AGE_FLAG, entry->status, reg[3]); - return SW_OK; -} - -static sw_error_t -_isis_napt_hw_to_sw(a_uint32_t dev_id, a_uint32_t reg[], - fal_napt_entry_t * entry) -{ - sw_error_t rv; - a_uint32_t data, cnt[4] = {0}; - - entry->dst_addr = reg[0]; - - SW_GET_FIELD_BY_REG(NAPT_ENTRY1, DST_PORT, entry->dst_port, reg[1]); - SW_GET_FIELD_BY_REG(NAPT_ENTRY1, SRC_PORT, entry->src_port, reg[1]); - SW_GET_FIELD_BY_REG(NAPT_ENTRY2, TRANS_PORT, entry->trans_port, reg[2]); - - SW_GET_FIELD_BY_REG(NAPT_ENTRY2, SRC_IPADDR, data, reg[2]); - rv = _isis_ip_prvaddr_hw_to_sw(dev_id, data, &(entry->src_addr)); - SW_RTN_ON_ERROR(rv); - - entry->flags |= FAL_NAT_ENTRY_TRANS_IPADDR_INDEX; - SW_GET_FIELD_BY_REG(NAPT_ENTRY2, TRANS_IPADDR, entry->trans_addr, reg[2]); - - SW_GET_FIELD_BY_REG(NAPT_ENTRY3, ACTION, data, reg[3]); - entry->action = FAL_MAC_FRWRD; - if (0 == data) - { - entry->mirror_en = A_TRUE; - } - else if (2 == data) - { - entry->action = FAL_MAC_CPY_TO_CPU; - } - else if (1 == data) - { - entry->action = FAL_MAC_RDT_TO_CPU; - } - - SW_GET_FIELD_BY_REG(NAPT_ENTRY3, CNT_EN, data, reg[3]); - if (data) - { - entry->counter_en = A_TRUE; - SW_GET_FIELD_BY_REG(NAPT_ENTRY3, CNT_IDX, entry->counter_id, reg[3]); - - rv = _isis_nat_counter_get(dev_id, entry->counter_id, cnt); - SW_RTN_ON_ERROR(rv); - - entry->ingress_packet = cnt[0]; - entry->ingress_byte = cnt[1]; - entry->egress_packet = cnt[2]; - entry->egress_byte = cnt[3]; - } - else - { - entry->counter_en = A_FALSE; - } - - SW_GET_FIELD_BY_REG(NAPT_ENTRY3, PROT_TYP, data, reg[3]); - if (0 == data) - { - entry->flags |= FAL_NAT_ENTRY_PROTOCOL_TCP; - } - else if (1 == data) - { - entry->flags |= FAL_NAT_ENTRY_PROTOCOL_UDP; - } - else if (3 == data) - { - entry->flags |= FAL_NAT_ENTRY_PROTOCOL_PPTP; - } - - SW_GET_FIELD_BY_REG(NAPT_ENTRY3, AGE_FLAG, entry->status, reg[3]); - return SW_OK; -} - -static sw_error_t -_isis_nat_down_to_hw(a_uint32_t dev_id, a_uint32_t reg[]) -{ - sw_error_t rv; - a_uint32_t i, addr; - - for (i = 0; i < 5; i++) - { - addr = ISIS_HOST_ENTRY_DATA0_ADDR + (i << 2); - HSL_REG_ENTRY_GEN_SET(rv, dev_id, addr, sizeof (a_uint32_t), - (a_uint8_t *) (®[i]), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - } - - return SW_OK; -} - -static sw_error_t -_isis_nat_up_to_sw(a_uint32_t dev_id, a_uint32_t reg[]) -{ - sw_error_t rv; - a_uint32_t i, addr; - - for (i = 0; i < 5; i++) - { - addr = ISIS_HOST_ENTRY_DATA0_ADDR + (i << 2); - HSL_REG_ENTRY_GEN_GET(rv, dev_id, addr, sizeof (a_uint32_t), - (a_uint8_t *) (®[i]), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - } - - return SW_OK; -} - -static sw_error_t -_isis_nat_add(a_uint32_t dev_id, fal_nat_entry_t * entry) -{ - sw_error_t rv; - a_uint32_t i, reg[5] = { 0 }; - - HSL_DEV_ID_CHECK(dev_id); - - rv = _isis_nat_feature_check(dev_id); - SW_RTN_ON_ERROR(rv); - - for (i = 0; i < ISIS_NAT_ENTRY_NUM; i++) - { - if (!(isis_nat_snap[dev_id] & (0x1 << i))) - { - break; - } - } - - if (ISIS_NAT_ENTRY_NUM == i) - { - return SW_NO_RESOURCE; - } - - entry->entry_id = i; - - rv = _isis_nat_sw_to_hw(dev_id, entry, reg); - SW_RTN_ON_ERROR(rv); - - rv = _isis_nat_down_to_hw(dev_id, reg); - SW_RTN_ON_ERROR(rv); - - rv = _isis_nat_entry_commit(dev_id, ISIS_ENTRY_NAT, ISIS_NAT_ENTRY_ADD); - SW_RTN_ON_ERROR(rv); - - isis_nat_snap[dev_id] |= (0x1 << i); - entry->entry_id = i; - return SW_OK; -} - -static sw_error_t -_isis_nat_del(a_uint32_t dev_id, a_uint32_t del_mode, fal_nat_entry_t * entry) -{ - sw_error_t rv; - a_uint32_t reg[5] = { 0 }; - - HSL_DEV_ID_CHECK(dev_id); - - rv = _isis_nat_feature_check(dev_id); - SW_RTN_ON_ERROR(rv); - - if (FAL_NAT_ENTRY_ID_EN & del_mode) - { - SW_SET_REG_BY_FIELD(HOST_ENTRY4, ENTRY_FUNC, ISIS_NAT_ENTRY_DEL, reg[4]); - SW_SET_REG_BY_FIELD(HOST_ENTRY4, TBL_IDX, entry->entry_id, reg[4]); - - rv = _isis_nat_down_to_hw(dev_id, reg); - SW_RTN_ON_ERROR(rv); - - rv = _isis_nat_entry_commit(dev_id, ISIS_ENTRY_NAT, ISIS_NAT_ENTRY_DEL); - SW_RTN_ON_ERROR(rv); - - isis_nat_snap[dev_id] &= (~(0x1 << entry->entry_id)); - } - else - { - rv = _isis_nat_down_to_hw(dev_id, reg); - SW_RTN_ON_ERROR(rv); - - rv = _isis_nat_entry_commit(dev_id, ISIS_ENTRY_NAT, ISIS_NAT_ENTRY_FLUSH); - SW_RTN_ON_ERROR(rv); - - isis_nat_snap[dev_id] = 0; - } - - return SW_OK; -} - -static sw_error_t -_isis_nat_get(a_uint32_t dev_id, a_uint32_t get_mode, fal_nat_entry_t * entry) -{ - sw_error_t rv; - a_uint32_t reg[5] = { 0 }; - - HSL_DEV_ID_CHECK(dev_id); - - rv = _isis_nat_feature_check(dev_id); - SW_RTN_ON_ERROR(rv); - - if (FAL_NAT_ENTRY_ID_EN != get_mode) - { - return SW_NOT_SUPPORTED; - } - - if (!(isis_nat_snap[dev_id] & (0x1 << entry->entry_id))) - { - return SW_NOT_FOUND; - } - - SW_SET_REG_BY_FIELD(HOST_ENTRY4, TBL_IDX, entry->entry_id, reg[4]); - - rv = _isis_nat_down_to_hw(dev_id, reg); - SW_RTN_ON_ERROR(rv); - - rv = _isis_nat_entry_commit(dev_id, ISIS_ENTRY_NAT, ISIS_NAT_ENTRY_SEARCH); - SW_RTN_ON_ERROR(rv); - - rv = _isis_nat_up_to_sw(dev_id, reg); - SW_RTN_ON_ERROR(rv); - - rv = _isis_nat_hw_to_sw(dev_id, reg, entry); - return rv; -} - -static sw_error_t -_isis_nat_next(a_uint32_t dev_id, a_uint32_t next_mode, - fal_nat_entry_t * nat_entry) -{ - a_uint32_t i, idx, reg[5] = { 0 }; - sw_error_t rv; - - HSL_DEV_ID_CHECK(dev_id); - - rv = _isis_nat_feature_check(dev_id); - SW_RTN_ON_ERROR(rv); - - if (FAL_NEXT_ENTRY_FIRST_ID == nat_entry->entry_id) - { - idx = 0; - } - else - { - if ((ISIS_NAT_ENTRY_NUM - 1) == nat_entry->entry_id) - { - return SW_NO_MORE; - } - else - { - idx = nat_entry->entry_id + 1; - } - } - - for (i = idx; i < ISIS_NAT_ENTRY_NUM; i++) - { - if (isis_nat_snap[dev_id] & (0x1 << i)) - { - break; - } - } - - if (ISIS_NAT_ENTRY_NUM == i) - { - return SW_NO_MORE; - } - - SW_SET_REG_BY_FIELD(HOST_ENTRY4, TBL_IDX, i, reg[4]); - - rv = _isis_nat_down_to_hw(dev_id, reg); - SW_RTN_ON_ERROR(rv); - - rv = _isis_nat_entry_commit(dev_id, ISIS_ENTRY_NAT, ISIS_NAT_ENTRY_SEARCH); - SW_RTN_ON_ERROR(rv); - - rv = _isis_nat_up_to_sw(dev_id, reg); - SW_RTN_ON_ERROR(rv); - - aos_mem_zero(nat_entry, sizeof (fal_nat_entry_t)); - - rv = _isis_nat_hw_to_sw(dev_id, reg, nat_entry); - SW_RTN_ON_ERROR(rv); - - nat_entry->entry_id = i; - return SW_OK; -} - -static sw_error_t -_isis_nat_counter_bind(a_uint32_t dev_id, a_uint32_t entry_id, - a_uint32_t cnt_id, a_bool_t enable) -{ - sw_error_t rv; - a_uint32_t reg[5] = { 0 }; - - HSL_DEV_ID_CHECK(dev_id); - - rv = _isis_nat_feature_check(dev_id); - SW_RTN_ON_ERROR(rv); - - if (!(isis_nat_snap[dev_id] & (0x1 << entry_id))) - { - return SW_NOT_FOUND; - } - - SW_SET_REG_BY_FIELD(HOST_ENTRY4, TBL_IDX, entry_id, reg[4]); - - rv = _isis_nat_entry_commit(dev_id, ISIS_ENTRY_NAT, ISIS_NAT_ENTRY_SEARCH); - SW_RTN_ON_ERROR(rv); - - rv = _isis_nat_up_to_sw(dev_id, reg); - SW_RTN_ON_ERROR(rv); - - if (A_FALSE == enable) - { - SW_SET_REG_BY_FIELD(NAT_ENTRY2, CNT_EN, 0, reg[2]); - } - else if (A_TRUE == enable) - { - SW_SET_REG_BY_FIELD(NAT_ENTRY2, CNT_EN, 1, reg[2]); - SW_SET_REG_BY_FIELD(NAT_ENTRY2, CNT_IDX, cnt_id, reg[2]); - } - else - { - return SW_BAD_PARAM; - } - - /* needn't set TBL_IDX, keep hardware register value */ - - rv = _isis_nat_entry_commit(dev_id, ISIS_ENTRY_NAT, ISIS_NAT_ENTRY_DEL); - SW_RTN_ON_ERROR(rv); - - rv = _isis_nat_down_to_hw(dev_id, reg); - SW_RTN_ON_ERROR(rv); - - /* needn't set TBL_IDX, keep hardware register value */ - - rv = _isis_nat_entry_commit(dev_id, ISIS_ENTRY_NAT, ISIS_NAT_ENTRY_ADD); - return rv; -} - -static sw_error_t -_isis_napt_add(a_uint32_t dev_id, fal_napt_entry_t * entry) -{ - sw_error_t rv; - a_uint32_t reg[5] = { 0 }; - - HSL_DEV_ID_CHECK(dev_id); - - rv = _isis_nat_feature_check(dev_id); - SW_RTN_ON_ERROR(rv); - - HSL_DEV_ID_CHECK(dev_id); - - rv = _isis_napt_sw_to_hw(dev_id, entry, reg); - SW_RTN_ON_ERROR(rv); - - rv = _isis_nat_down_to_hw(dev_id, reg); - SW_RTN_ON_ERROR(rv); - - rv = _isis_nat_entry_commit(dev_id, ISIS_ENTRY_NAPT, ISIS_NAT_ENTRY_ADD); - SW_RTN_ON_ERROR(rv); - - rv = _isis_nat_up_to_sw(dev_id, reg); - SW_RTN_ON_ERROR(rv); - - SW_GET_FIELD_BY_REG(HOST_ENTRY4, TBL_IDX, entry->entry_id, reg[4]); - return SW_OK; -} - -static sw_error_t -_isis_napt_del(a_uint32_t dev_id, a_uint32_t del_mode, fal_napt_entry_t * entry) -{ - sw_error_t rv; - a_uint32_t data, reg[5] = { 0 }; - - HSL_DEV_ID_CHECK(dev_id); - - rv = _isis_nat_feature_check(dev_id); - SW_RTN_ON_ERROR(rv); - - if (FAL_NAT_ENTRY_ID_EN & del_mode) - { - return SW_NOT_SUPPORTED; - } - - if (FAL_NAT_ENTRY_KEY_EN & del_mode) - { - rv = _isis_napt_sw_to_hw(dev_id, entry, reg); - SW_RTN_ON_ERROR(rv); - - rv = _isis_nat_down_to_hw(dev_id, reg); - SW_RTN_ON_ERROR(rv); - - rv = _isis_nat_entry_commit(dev_id, ISIS_ENTRY_NAPT, ISIS_NAT_ENTRY_DEL); - SW_RTN_ON_ERROR(rv); - - rv = _isis_nat_up_to_sw(dev_id, reg); - SW_RTN_ON_ERROR(rv); - - SW_GET_FIELD_BY_REG(HOST_ENTRY4, TBL_IDX, entry->entry_id, reg[4]); - return SW_OK; - } - else - { - if (FAL_NAT_ENTRY_PUBLIC_IP_EN & del_mode) - { - SW_SET_REG_BY_FIELD(HOST_ENTRY4, SPEC_PIP, 1, reg[4]); - SW_SET_REG_BY_FIELD(NAPT_ENTRY2, TRANS_IPADDR, entry->trans_addr, reg[2]); - } - - if (FAL_NAT_ENTRY_SOURCE_IP_EN & del_mode) - { - SW_SET_REG_BY_FIELD(HOST_ENTRY4, SPEC_SIP, 1, reg[4]); - rv = _isis_ip_prvaddr_sw_to_hw(dev_id, entry->src_addr, &data); - SW_RTN_ON_ERROR(rv); - SW_SET_REG_BY_FIELD(NAPT_ENTRY2, SRC_IPADDR, data, reg[2]); - } - - if (FAL_NAT_ENTRY_AGE_EN & del_mode) - { - SW_SET_REG_BY_FIELD(HOST_ENTRY4, SPEC_STATUS, 1, reg[4]); - SW_SET_REG_BY_FIELD(NAPT_ENTRY3, AGE_FLAG, entry->status, reg[3]); - } - - rv = _isis_nat_down_to_hw(dev_id, reg); - SW_RTN_ON_ERROR(rv); - - rv = _isis_nat_entry_commit(dev_id, ISIS_ENTRY_NAPT, ISIS_NAT_ENTRY_FLUSH); - return rv; - } -} - -static sw_error_t -_isis_napt_get(a_uint32_t dev_id, a_uint32_t get_mode, fal_napt_entry_t * entry) -{ - sw_error_t rv; - a_uint32_t found, age, reg[5] = { 0 }; - - HSL_DEV_ID_CHECK(dev_id); - - rv = _isis_nat_feature_check(dev_id); - SW_RTN_ON_ERROR(rv); - -#if 0 - if (FAL_NAT_ENTRY_ID_EN != get_mode) - { - return SW_NOT_SUPPORTED; - } - - SW_SET_REG_BY_FIELD(HOST_ENTRY4, TBL_IDX, entry->entry_id, reg[4]); -#else - rv = _isis_napt_sw_to_hw(dev_id, entry, reg); - SW_RTN_ON_ERROR(rv); -#endif - - rv = _isis_nat_down_to_hw(dev_id, reg); - SW_RTN_ON_ERROR(rv); - - rv = _isis_nat_entry_commit(dev_id, ISIS_ENTRY_NAPT, ISIS_NAT_ENTRY_SEARCH); - SW_RTN_ON_ERROR(rv); - - rv = _isis_nat_up_to_sw(dev_id, reg); - SW_RTN_ON_ERROR(rv); - - SW_GET_FIELD_BY_REG(HOST_ENTRY4, TBL_STAUS, found, reg[4]); - SW_GET_FIELD_BY_REG(NAPT_ENTRY3, AGE_FLAG, age, reg[3]); - if (found && age) - { - found = 1; - } - else - { - found = 0; - } - - rv = _isis_napt_hw_to_sw(dev_id, reg, entry); - SW_RTN_ON_ERROR(rv); - - if (!found) - { - return SW_NOT_FOUND; - } - - SW_GET_FIELD_BY_REG(HOST_ENTRY4, TBL_IDX, entry->entry_id, reg[4]); - return SW_OK; -} - -static sw_error_t -_isis_napt_next(a_uint32_t dev_id, a_uint32_t next_mode, - fal_napt_entry_t * napt_entry) -{ - a_uint32_t data, idx, reg[5] = { 0 }; - sw_error_t rv; - - HSL_DEV_ID_CHECK(dev_id); - - rv = _isis_nat_feature_check(dev_id); - SW_RTN_ON_ERROR(rv); - - if (FAL_NEXT_ENTRY_FIRST_ID == napt_entry->entry_id) - { - idx = ISIS_NAPT_ENTRY_NUM - 1; - } - else - { - if ((ISIS_NAPT_ENTRY_NUM - 1) == napt_entry->entry_id) - { - return SW_NO_MORE; - } - else - { - idx = napt_entry->entry_id; - } - } - - if (FAL_NAT_ENTRY_PUBLIC_IP_EN & next_mode) - { - SW_SET_REG_BY_FIELD(HOST_ENTRY4, SPEC_PIP, 1, reg[4]); - SW_SET_REG_BY_FIELD(NAPT_ENTRY2, TRANS_IPADDR, napt_entry->trans_addr, reg[2]); - } - - if (FAL_NAT_ENTRY_SOURCE_IP_EN & next_mode) - { - SW_SET_REG_BY_FIELD(HOST_ENTRY4, SPEC_SIP, 1, reg[4]); - rv = _isis_ip_prvaddr_sw_to_hw(dev_id, napt_entry->src_addr, &data); - SW_RTN_ON_ERROR(rv); - SW_SET_REG_BY_FIELD(NAPT_ENTRY2, SRC_IPADDR, data, reg[2]); - } - - if (FAL_NAT_ENTRY_AGE_EN & next_mode) - { - SW_SET_REG_BY_FIELD(HOST_ENTRY4, SPEC_STATUS, 1, reg[4]); - SW_SET_REG_BY_FIELD(NAPT_ENTRY3, AGE_FLAG, napt_entry->status, reg[3]); - } - - SW_SET_REG_BY_FIELD(HOST_ENTRY4, TBL_IDX, idx, reg[4]); - - rv = _isis_nat_down_to_hw(dev_id, reg); - SW_RTN_ON_ERROR(rv); - - rv = _isis_nat_entry_commit(dev_id, ISIS_ENTRY_NAPT, ISIS_NAT_ENTRY_NEXT); - SW_RTN_ON_ERROR(rv); - - rv = _isis_nat_up_to_sw(dev_id, reg); - SW_RTN_ON_ERROR(rv); - - aos_mem_zero(napt_entry, sizeof (fal_nat_entry_t)); - - rv = _isis_napt_hw_to_sw(dev_id, reg, napt_entry); - SW_RTN_ON_ERROR(rv); - -#if 0 - a_uint32_t temp=0, complete=0; - - HSL_REG_ENTRY_GET(rv, dev_id, HOST_ENTRY4, 0, (a_uint8_t *) (&temp), - sizeof (a_uint32_t)); - - SW_GET_FIELD_BY_REG(HOST_ENTRY4, TBL_STAUS, complete, temp); - - if (!complete) - { - return SW_NO_MORE; - } -#endif - - SW_GET_FIELD_BY_REG(HOST_ENTRY4, TBL_IDX, napt_entry->entry_id, reg[4]); - return SW_OK; -} - -static sw_error_t -_isis_napt_counter_bind(a_uint32_t dev_id, a_uint32_t entry_id, - a_uint32_t cnt_id, a_bool_t enable) -{ - sw_error_t rv; - a_uint32_t reg[5] = { 0 }, tbl_idx; - - HSL_DEV_ID_CHECK(dev_id); - - rv = _isis_nat_feature_check(dev_id); - SW_RTN_ON_ERROR(rv); - - tbl_idx = (entry_id - 1) & 0x3ff; - SW_SET_REG_BY_FIELD(HOST_ENTRY4, TBL_IDX, tbl_idx, reg[4]); - - rv = _isis_nat_down_to_hw(dev_id, reg); - SW_RTN_ON_ERROR(rv); - - rv = _isis_nat_entry_commit(dev_id, ISIS_ENTRY_NAPT, ISIS_NAT_ENTRY_NEXT); - if (SW_OK != rv) - { - return SW_NOT_FOUND; - } - - rv = _isis_nat_up_to_sw(dev_id, reg); - SW_RTN_ON_ERROR(rv); - - SW_GET_FIELD_BY_REG(HOST_ENTRY4, TBL_IDX, tbl_idx, reg[4]); - if (entry_id != tbl_idx) - { - return SW_NOT_FOUND; - } - - if (A_FALSE == enable) - { - SW_SET_REG_BY_FIELD(NAPT_ENTRY3, CNT_EN, 0, reg[3]); - } - else if (A_TRUE == enable) - { - SW_SET_REG_BY_FIELD(NAPT_ENTRY3, CNT_EN, 1, reg[3]); - SW_SET_REG_BY_FIELD(NAPT_ENTRY3, CNT_IDX, cnt_id, reg[3]); - } - else - { - return SW_BAD_PARAM; - } - - rv = _isis_nat_entry_commit(dev_id, ISIS_ENTRY_NAPT, ISIS_NAT_ENTRY_DEL); - SW_RTN_ON_ERROR(rv); - - reg[4] = 0x0; - rv = _isis_nat_down_to_hw(dev_id, reg); - SW_RTN_ON_ERROR(rv); - - rv = _isis_nat_entry_commit(dev_id, ISIS_ENTRY_NAPT, ISIS_NAT_ENTRY_ADD); - return rv; -} - -static sw_error_t -_isis_nat_status_set(a_uint32_t dev_id, a_bool_t enable) -{ - sw_error_t rv; - a_uint32_t data; - - HSL_DEV_ID_CHECK(dev_id); - - rv = _isis_nat_feature_check(dev_id); - SW_RTN_ON_ERROR(rv); - - if (A_TRUE == enable) - { - data = 1; - } - else if (A_FALSE == enable) - { - data = 0; - } - else - { - return SW_BAD_PARAM; - } - - HSL_REG_FIELD_SET(rv, dev_id, NAT_CTRL, 0, NAT_EN, - (a_uint8_t *) (&data), sizeof (a_uint32_t)); - return rv; -} - -static sw_error_t -_isis_nat_status_get(a_uint32_t dev_id, a_bool_t * enable) -{ - sw_error_t rv; - a_uint32_t data = 0; - - HSL_DEV_ID_CHECK(dev_id); - - rv = _isis_nat_feature_check(dev_id); - SW_RTN_ON_ERROR(rv); - - HSL_REG_FIELD_GET(rv, dev_id, NAT_CTRL, 0, NAT_EN, - (a_uint8_t *) (&data), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - - if (data) - { - *enable = A_TRUE; - } - else - { - *enable = A_FALSE; - } - - return rv; -} - -static sw_error_t -_isis_napt_status_set(a_uint32_t dev_id, a_bool_t enable) -{ - sw_error_t rv; - a_uint32_t data; - - HSL_DEV_ID_CHECK(dev_id); - - rv = _isis_nat_feature_check(dev_id); - SW_RTN_ON_ERROR(rv); - - if (A_TRUE == enable) - { - data = 1; - } - else if (A_FALSE == enable) - { - data = 0; - } - else - { - return SW_BAD_PARAM; - } - - HSL_REG_FIELD_SET(rv, dev_id, NAT_CTRL, 0, NAPT_EN, - (a_uint8_t *) (&data), sizeof (a_uint32_t)); - return rv; -} - -static sw_error_t -_isis_napt_status_get(a_uint32_t dev_id, a_bool_t * enable) -{ - sw_error_t rv; - a_uint32_t data = 0; - - HSL_DEV_ID_CHECK(dev_id); - - rv = _isis_nat_feature_check(dev_id); - SW_RTN_ON_ERROR(rv); - - HSL_REG_FIELD_GET(rv, dev_id, NAT_CTRL, 0, NAPT_EN, - (a_uint8_t *) (&data), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - - if (data) - { - *enable = A_TRUE; - } - else - { - *enable = A_FALSE; - } - - return rv; -} - -static sw_error_t -_isis_napt_mode_set(a_uint32_t dev_id, fal_napt_mode_t mode) -{ - sw_error_t rv; - a_uint32_t data; - - HSL_DEV_ID_CHECK(dev_id); - - rv = _isis_nat_feature_check(dev_id); - SW_RTN_ON_ERROR(rv); - - if (FAL_NAPT_FULL_CONE == mode) - { - data = 0; - } - else if (FAL_NAPT_STRICT_CONE == mode) - { - data = 1; - } - else if ((FAL_NAPT_PORT_STRICT == mode) - || (FAL_NAPT_SYNMETRIC == mode)) - { - data = 2; - } - else - { - return SW_BAD_PARAM; - } - - HSL_REG_FIELD_SET(rv, dev_id, NAT_CTRL, 0, NAPT_MODE, - (a_uint8_t *) (&data), sizeof (a_uint32_t)); - return rv; -} - -static sw_error_t -_isis_napt_mode_get(a_uint32_t dev_id, fal_napt_mode_t * mode) -{ - sw_error_t rv; - a_uint32_t data = 0; - - HSL_DEV_ID_CHECK(dev_id); - - rv = _isis_nat_feature_check(dev_id); - SW_RTN_ON_ERROR(rv); - - HSL_REG_FIELD_GET(rv, dev_id, NAT_CTRL, 0, NAPT_MODE, - (a_uint8_t *) (&data), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - - if (0 == data) - { - *mode = FAL_NAPT_FULL_CONE; - } - else if (1 == data) - { - *mode = FAL_NAPT_STRICT_CONE; - } - else - { - *mode = FAL_NAPT_PORT_STRICT; - } - - return SW_OK; -} - -static sw_error_t -_isis_nat_hash_mode_set(a_uint32_t dev_id, a_uint32_t mode) -{ - sw_error_t rv; - a_uint32_t data; - - HSL_DEV_ID_CHECK(dev_id); - - rv = _isis_nat_feature_check(dev_id); - SW_RTN_ON_ERROR(rv); - - if ((FAL_NAT_HASH_KEY_PORT & mode) - && (FAL_NAT_HASH_KEY_IPADDR & mode)) - { - data = 2; - } - else if (FAL_NAT_HASH_KEY_PORT & mode) - { - data = 0; - } - else if (FAL_NAT_HASH_KEY_IPADDR & mode) - { - data = 1; - } - else - { - return SW_BAD_PARAM; - } - - HSL_REG_FIELD_SET(rv, dev_id, NAT_CTRL, 0, NAT_HASH_MODE, - (a_uint8_t *) (&data), sizeof (a_uint32_t)); - return rv; -} - -static sw_error_t -_isis_nat_hash_mode_get(a_uint32_t dev_id, a_uint32_t * mode) -{ - sw_error_t rv; - a_uint32_t data = 0; - - HSL_DEV_ID_CHECK(dev_id); - - rv = _isis_nat_feature_check(dev_id); - SW_RTN_ON_ERROR(rv); - - HSL_REG_FIELD_GET(rv, dev_id, NAT_CTRL, 0, NAT_HASH_MODE, - (a_uint8_t *) (&data), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - - *mode = 0; - if (0 == data) - { - *mode = FAL_NAT_HASH_KEY_PORT; - } - else if (1 == data) - { - *mode = FAL_NAT_HASH_KEY_IPADDR; - } - else if (2 == data) - { - *mode = FAL_NAT_HASH_KEY_PORT; - *mode |= FAL_NAT_HASH_KEY_IPADDR; - } - - return SW_OK; -} - -static sw_error_t -_isis_nat_prv_base_addr_set(a_uint32_t dev_id, fal_ip4_addr_t addr) -{ - sw_error_t rv; - a_uint32_t data = 0; - - HSL_DEV_ID_CHECK(dev_id); - - rv = _isis_nat_feature_check(dev_id); - SW_RTN_ON_ERROR(rv); - - HSL_REG_FIELD_GET(rv, dev_id, PRVIP_CTL, 0, BASEADDR_SEL, - (a_uint8_t *) (&data), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - - if (data) - { - data = (((addr >> 20) & 0xfff) << 8) | ((addr >> 8) & 0xff); - } - else - { - data = (addr >> 12) & 0xfffff; - } - - HSL_REG_FIELD_SET(rv, dev_id, PRVIP_CTL, 0, IP4_BASEADDR, - (a_uint8_t *) (&data), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - - HSL_REG_FIELD_SET(rv, dev_id, OFFLOAD_PRVIP_CTL, 0, IP4_BASEADDR, - (a_uint8_t *) (&data), sizeof (a_uint32_t)); - return rv; -} - -static sw_error_t -_isis_nat_prv_base_addr_get(a_uint32_t dev_id, fal_ip4_addr_t * addr) -{ - sw_error_t rv; - a_uint32_t data = 0, tmp = 0; - - HSL_DEV_ID_CHECK(dev_id); - - rv = _isis_nat_feature_check(dev_id); - SW_RTN_ON_ERROR(rv); - - HSL_REG_FIELD_GET(rv, dev_id, PRVIP_CTL, 0, BASEADDR_SEL, - (a_uint8_t *) (&tmp), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - - HSL_REG_FIELD_GET(rv, dev_id, PRVIP_CTL, 0, IP4_BASEADDR, - (a_uint8_t *) (&data), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - - if (tmp) - { - *addr = ((data & 0xff) << 8) | (((data >> 8) & 0xfff) << 20); - } - else - { - *addr = (data & 0xfffff) << 12; - } - - return SW_OK; -} - -#if 0 -static sw_error_t -_isis_nat_psr_prv_base_addr_set(a_uint32_t dev_id, fal_ip4_addr_t addr) -{ - sw_error_t rv; - a_uint32_t data = 0; - - HSL_DEV_ID_CHECK(dev_id); - - rv = _isis_nat_feature_check(dev_id); - SW_RTN_ON_ERROR(rv); - - HSL_REG_FIELD_GET(rv, dev_id, PRVIP_CTL, 0, BASEADDR_SEL, - (a_uint8_t *) (&data), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - - if (data) - { - data = (((addr >> 20) & 0xfff) << 8) | ((addr >> 8) & 0xff); - } - else - { - data = (addr >> 12) & 0xfffff; - } - - HSL_REG_FIELD_SET(rv, dev_id, PRVIP_CTL, 0, IP4_BASEADDR, - (a_uint8_t *) (&data), sizeof (a_uint32_t)); - return rv; -} - -static sw_error_t -_isis_nat_psr_prv_base_addr_get(a_uint32_t dev_id, fal_ip4_addr_t * addr) -{ - sw_error_t rv; - a_uint32_t data, tmp = 0; - - HSL_DEV_ID_CHECK(dev_id); - - rv = _isis_nat_feature_check(dev_id); - SW_RTN_ON_ERROR(rv); - - HSL_REG_FIELD_GET(rv, dev_id, PRVIP_CTL, 0, BASEADDR_SEL, - (a_uint8_t *) (&tmp), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - - HSL_REG_FIELD_GET(rv, dev_id, PRVIP_CTL, 0, IP4_BASEADDR, - (a_uint8_t *) (&data), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - - if (tmp) - { - *addr = ((data & 0xff) << 8) | (((data >> 8) & 0xfff) << 20); - } - else - { - *addr = (data & 0xfffff) << 12; - } - - return SW_OK; -} -#endif - -static sw_error_t -_isis_nat_prv_addr_mode_set(a_uint32_t dev_id, a_bool_t map_en) -{ - sw_error_t rv; - a_uint32_t data; - - HSL_DEV_ID_CHECK(dev_id); - - rv = _isis_nat_feature_check(dev_id); - SW_RTN_ON_ERROR(rv); - - if (A_TRUE == map_en) - { - data = 1; - } - else if (A_FALSE == map_en) - { - data = 0; - } - else - { - return SW_BAD_PARAM; - } - - HSL_REG_FIELD_SET(rv, dev_id, PRVIP_CTL, 0, BASEADDR_SEL, - (a_uint8_t *) (&data), sizeof (a_uint32_t)); - return rv; -} - -static sw_error_t -_isis_nat_prv_addr_mode_get(a_uint32_t dev_id, a_bool_t * map_en) -{ - sw_error_t rv; - a_uint32_t data = 0; - - HSL_DEV_ID_CHECK(dev_id); - - rv = _isis_nat_feature_check(dev_id); - SW_RTN_ON_ERROR(rv); - - HSL_REG_FIELD_GET(rv, dev_id, PRVIP_CTL, 0, BASEADDR_SEL, - (a_uint8_t *) (&data), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - - if (data) - { - *map_en = A_TRUE; - } - else - { - *map_en = A_FALSE; - } - - return SW_OK; -} - -static sw_error_t -_isis_nat_pub_addr_commit(a_uint32_t dev_id, fal_nat_pub_addr_t * entry, - a_uint32_t op, a_uint32_t * empty) -{ - a_uint32_t index, addr, data, tbl[2] = { 0 }; - sw_error_t rv; - - *empty = ISIS_PUB_ADDR_NUM; - for (index = 0; index < ISIS_PUB_ADDR_NUM; index++) - { - addr = ISIS_PUB_ADDR_TBL1_ADDR + (index << 4); - HSL_REG_ENTRY_GEN_GET(rv, dev_id, addr, sizeof (a_uint32_t), - (a_uint8_t *) (&(tbl[1])), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - - SW_GET_FIELD_BY_REG(PUB_ADDR1, ADDR_VALID, data, tbl[1]); - if (data) - { - addr = ISIS_PUB_ADDR_TBL0_ADDR + (index << 4); - HSL_REG_ENTRY_GEN_GET(rv, dev_id, addr, sizeof (a_uint32_t), - (a_uint8_t *) (&(tbl[0])), - sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - - if (!aos_mem_cmp - ((void *) &(entry->pub_addr), (void *) &(tbl[0]), - sizeof (fal_ip4_addr_t))) - { - if (ISIS_NAT_ENTRY_DEL == op) - { - addr = ISIS_PUB_ADDR_TBL1_ADDR + (index << 4); - tbl[1] = 0; - HSL_REG_ENTRY_GEN_SET(rv, dev_id, addr, sizeof (a_uint32_t), - (a_uint8_t *) (&(tbl[1])), - sizeof (a_uint32_t)); - *empty = index; - return rv; - } - else if (ISIS_NAT_ENTRY_ADD == op) - { - entry->entry_id = index; - return SW_ALREADY_EXIST; - } - } - } - else - { - *empty = index; - } - } - - return SW_NOT_FOUND; -} - -static sw_error_t -_isis_nat_pub_addr_add(a_uint32_t dev_id, fal_nat_pub_addr_t * entry) -{ - sw_error_t rv; - a_uint32_t i, empty, addr, data = 0, tbl[2] = { 0 }; - - HSL_DEV_ID_CHECK(dev_id); - - rv = _isis_nat_feature_check(dev_id); - SW_RTN_ON_ERROR(rv); - - tbl[0] = entry->pub_addr; - tbl[1] = 1; - - rv = _isis_nat_pub_addr_commit(dev_id, entry, ISIS_NAT_ENTRY_ADD, &empty); - if (SW_ALREADY_EXIST == rv) - { - return rv; - } - - if (ISIS_PUB_ADDR_NUM == empty) - { - return SW_NO_RESOURCE; - } - - for (i = 0; i < 1; i++) - { - addr = ISIS_PUB_ADDR_EDIT0_ADDR + (empty << 4) + (i << 2); - HSL_REG_ENTRY_GEN_SET(rv, dev_id, addr, sizeof (a_uint32_t), - (a_uint8_t *) (&(tbl[i])), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - } - - addr = ISIS_PUB_ADDR_OFFLOAD_ADDR + (empty << 2); - HSL_REG_ENTRY_GEN_SET(rv, dev_id, addr, sizeof (a_uint32_t), - (a_uint8_t *) (&(tbl[0])), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - - addr = ISIS_PUB_ADDR_VALID_ADDR; - HSL_REG_ENTRY_GEN_GET(rv, dev_id, addr, sizeof (a_uint32_t), - (a_uint8_t *) (&data), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - - data |= (0x1 << empty); - HSL_REG_ENTRY_GEN_SET(rv, dev_id, addr, sizeof (a_uint32_t), - (a_uint8_t *) (&data), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - - for (i = 0; i < 2; i++) - { - addr = ISIS_PUB_ADDR_TBL0_ADDR + (empty << 4) + (i << 2); - HSL_REG_ENTRY_GEN_SET(rv, dev_id, addr, sizeof (a_uint32_t), - (a_uint8_t *) (&(tbl[i])), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - } - - entry->entry_id = empty; - return SW_OK; -} - -static sw_error_t -_isis_nat_pub_addr_del(a_uint32_t dev_id, a_uint32_t del_mode, - fal_nat_pub_addr_t * entry) -{ - sw_error_t rv; - a_uint32_t empty, addr, data = 0; - - HSL_DEV_ID_CHECK(dev_id); - - rv = _isis_nat_feature_check(dev_id); - SW_RTN_ON_ERROR(rv); - - rv = _isis_nat_pub_addr_commit(dev_id, entry, ISIS_NAT_ENTRY_DEL, &empty); - SW_RTN_ON_ERROR(rv); - - addr = ISIS_PUB_ADDR_VALID_ADDR; - HSL_REG_ENTRY_GEN_GET(rv, dev_id, addr, sizeof (a_uint32_t), - (a_uint8_t *) (&data), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - - data &= (~(0x1 << empty)); - HSL_REG_ENTRY_GEN_SET(rv, dev_id, addr, sizeof (a_uint32_t), - (a_uint8_t *) (&data), sizeof (a_uint32_t)); - - return rv; -} - -static sw_error_t -_isis_nat_pub_addr_next(a_uint32_t dev_id, a_uint32_t next_mode, - fal_nat_pub_addr_t * entry) -{ - sw_error_t rv; - a_uint32_t data, addr, idx, index, tbl[2] = {0}; - - HSL_DEV_ID_CHECK(dev_id); - - rv = _isis_nat_feature_check(dev_id); - SW_RTN_ON_ERROR(rv); - - if (FAL_NEXT_ENTRY_FIRST_ID == entry->entry_id) - { - idx = 0; - } - else - { - if ((ISIS_PUB_ADDR_NUM - 1) == entry->entry_id) - { - return SW_NO_MORE; - } - else - { - idx = entry->entry_id + 1; - } - } - - for (index = idx; index < ISIS_PUB_ADDR_NUM; index++) - { - addr = ISIS_PUB_ADDR_TBL1_ADDR + (index << 4); - HSL_REG_ENTRY_GEN_GET(rv, dev_id, addr, sizeof (a_uint32_t), - (a_uint8_t *) (&(tbl[1])), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - - SW_GET_FIELD_BY_REG(PUB_ADDR1, ADDR_VALID, data, tbl[1]); - if (data) - { - break; - } - } - - if (ISIS_PUB_ADDR_NUM == index) - { - return SW_NO_MORE; - } - - addr = ISIS_PUB_ADDR_TBL0_ADDR + (index << 4); - HSL_REG_ENTRY_GEN_GET(rv, dev_id, addr, sizeof (a_uint32_t), - (a_uint8_t *) (&(tbl[0])), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - - entry->entry_id = index; - entry->pub_addr = tbl[0]; - - return SW_OK; -} - -static sw_error_t -_isis_nat_unk_session_cmd_set(a_uint32_t dev_id, fal_fwd_cmd_t cmd) -{ - sw_error_t rv; - a_uint32_t data; - - HSL_DEV_ID_CHECK(dev_id); - - rv = _isis_nat_feature_check(dev_id); - SW_RTN_ON_ERROR(rv); - - if (FAL_MAC_DROP == cmd) - { - data = 1; - } - else if (FAL_MAC_RDT_TO_CPU == cmd) - { - data = 0; - } - else - { - return SW_NOT_SUPPORTED; - } - - HSL_REG_FIELD_SET(rv, dev_id, FORWARD_CTL0, 0, NAT_NOT_FOUND_DROP, - (a_uint8_t *) (&data), sizeof (a_uint32_t)); - return rv; -} - -static sw_error_t -_isis_nat_unk_session_cmd_get(a_uint32_t dev_id, fal_fwd_cmd_t * cmd) -{ - sw_error_t rv; - a_uint32_t data = 0; - - HSL_DEV_ID_CHECK(dev_id); - - rv = _isis_nat_feature_check(dev_id); - SW_RTN_ON_ERROR(rv); - - HSL_REG_FIELD_GET(rv, dev_id, FORWARD_CTL0, 0, NAT_NOT_FOUND_DROP, - (a_uint8_t *) (&data), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - - if (0 == data) - { - *cmd = FAL_MAC_RDT_TO_CPU; - } - else - { - *cmd = FAL_MAC_DROP; - } - - return SW_OK; -} - -sw_error_t -isis_nat_reset(a_uint32_t dev_id) -{ - sw_error_t rv; - a_uint32_t index, addr, data = 0; - - HSL_DEV_ID_CHECK(dev_id); - - rv = _isis_nat_feature_check(dev_id); - SW_RTN_ON_ERROR(rv); - - isis_nat_snap[dev_id] = 0; - - HSL_REG_ENTRY_SET(rv, dev_id, HOST_ENTRY4, 0, (a_uint8_t *) (&data), - sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - - rv = _isis_nat_entry_commit(dev_id, ISIS_ENTRY_NAT, ISIS_NAT_ENTRY_FLUSH); - SW_RTN_ON_ERROR(rv); - - HSL_REG_ENTRY_SET(rv, dev_id, HOST_ENTRY4, 0, (a_uint8_t *) (&data), - sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - - rv = _isis_nat_entry_commit(dev_id, ISIS_ENTRY_NAPT, ISIS_NAT_ENTRY_FLUSH); - SW_RTN_ON_ERROR(rv); - - for (index = 0; index < ISIS_PUB_ADDR_NUM; index++) - { - addr = ISIS_PUB_ADDR_TBL1_ADDR + (index << 4); - HSL_REG_ENTRY_GEN_SET(rv, dev_id, addr, sizeof (a_uint32_t), - (a_uint8_t *) (&data), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - } - - return SW_OK; -} - -/** - * @brief Add one NAT entry to one particular device. - * @details Comments: - Before NAT entry added ip4 private base address must be set - at first. - In parameter nat_entry entry flags must be set - Hardware entry id will be returned. - * @param[in] dev_id device id - * @param[in] nat_entry NAT entry parameter - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -isis_nat_add(a_uint32_t dev_id, fal_nat_entry_t * nat_entry) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _isis_nat_add(dev_id, nat_entry); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Del NAT entries from one particular device. - * @param[in] dev_id device id - * @param[in] del_mode NAT entry delete operation mode - * @param[in] nat_entry NAT entry parameter - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -isis_nat_del(a_uint32_t dev_id, a_uint32_t del_mode, - fal_nat_entry_t * nat_entry) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _isis_nat_del(dev_id, del_mode, nat_entry); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Get one NAT entry from one particular device. - * @param[in] dev_id device id - * @param[in] get_mode NAT entry get operation mode - * @param[in] nat_entry NAT entry parameter - * @param[out] nat_entry NAT entry parameter - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -isis_nat_get(a_uint32_t dev_id, a_uint32_t get_mode, - fal_nat_entry_t * nat_entry) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _isis_nat_get(dev_id, get_mode, nat_entry); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Next NAT entries from one particular device. - * @param[in] dev_id device id - * @param[in] next_mode NAT entry next operation mode - * @param[in] nat_entry NAT entry parameter - * @param[out] nat_entry NAT entry parameter - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -isis_nat_next(a_uint32_t dev_id, a_uint32_t next_mode, - fal_nat_entry_t * nat_entry) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _isis_nat_next(dev_id, next_mode, nat_entry); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Bind one counter entry to one NAT entry to one particular device. - * @param[in] dev_id device id - * @param[in] entry_id NAT entry id - * @param[in] cnt_id counter entry id - * @param[in] enable A_TRUE or A_FALSE - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -isis_nat_counter_bind(a_uint32_t dev_id, a_uint32_t entry_id, a_uint32_t cnt_id, - a_bool_t enable) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _isis_nat_counter_bind(dev_id, entry_id, cnt_id, enable); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Add one NAPT entry to one particular device. - * @details Comments: - Before NAPT entry added related ip4 private base address must be set - at first. - In parameter napt_entry related entry flags must be set - Hardware entry id will be returned. - * @param[in] dev_id device id - * @param[in] napt_entry NAPT entry parameter - * @return SW_OK or error code - */ - -HSL_LOCAL sw_error_t -isis_napt_add(a_uint32_t dev_id, fal_napt_entry_t * napt_entry) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _isis_napt_add(dev_id, napt_entry); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Del NAPT entries from one particular device. - * @param[in] dev_id device id - * @param[in] del_mode NAPT entry delete operation mode - * @param[in] napt_entry NAPT entry parameter - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -isis_napt_del(a_uint32_t dev_id, a_uint32_t del_mode, - fal_napt_entry_t * napt_entry) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _isis_napt_del(dev_id, del_mode, napt_entry); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Get one NAPT entry from one particular device. - * @param[in] dev_id device id - * @param[in] get_mode NAPT entry get operation mode - * @param[in] nat_entry NAPT entry parameter - * @param[out] nat_entry NAPT entry parameter - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -isis_napt_get(a_uint32_t dev_id, a_uint32_t get_mode, - fal_napt_entry_t * napt_entry) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _isis_napt_get(dev_id, get_mode, napt_entry); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Next NAPT entries from one particular device. - * @param[in] dev_id device id - * @param[in] next_mode NAPT entry next operation mode - * @param[in] napt_entry NAPT entry parameter - * @param[out] napt_entry NAPT entry parameter - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -isis_napt_next(a_uint32_t dev_id, a_uint32_t next_mode, - fal_napt_entry_t * napt_entry) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _isis_napt_next(dev_id, next_mode, napt_entry); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Bind one counter entry to one NAPT entry to one particular device. - * @param[in] dev_id device id - * @param[in] entry_id NAPT entry id - * @param[in] cnt_id counter entry id - * @param[in] enable A_TRUE or A_FALSE - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -isis_napt_counter_bind(a_uint32_t dev_id, a_uint32_t entry_id, - a_uint32_t cnt_id, a_bool_t enable) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _isis_napt_counter_bind(dev_id, entry_id, cnt_id, enable); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Set working status of NAT engine on a particular device - * @param[in] dev_id device id - * @param[in] enable A_TRUE or A_FALSE - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -isis_nat_status_set(a_uint32_t dev_id, a_bool_t enable) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _isis_nat_status_set(dev_id, enable); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Get working status of NAT engine on a particular device - * @param[in] dev_id device id - * @param[out] enable A_TRUE or A_FALSE - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -isis_nat_status_get(a_uint32_t dev_id, a_bool_t * enable) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _isis_nat_status_get(dev_id, enable); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Set NAT hash mode on a particular device - * @param[in] dev_id device id - * @param[in] mode NAT hash mode - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -isis_nat_hash_mode_set(a_uint32_t dev_id, a_uint32_t mode) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _isis_nat_hash_mode_set(dev_id, mode); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Get NAT hash mode on a particular device - * @param[in] dev_id device id - * @param[out] mode NAT hash mode - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -isis_nat_hash_mode_get(a_uint32_t dev_id, a_uint32_t * mode) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _isis_nat_hash_mode_get(dev_id, mode); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Set working status of NAPT engine on a particular device - * @param[in] dev_id device id - * @param[in] enable A_TRUE or A_FALSE - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -isis_napt_status_set(a_uint32_t dev_id, a_bool_t enable) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _isis_napt_status_set(dev_id, enable); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Get working status of NAPT engine on a particular device - * @param[in] dev_id device id - * @param[out] enable A_TRUE or A_FALSE - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -isis_napt_status_get(a_uint32_t dev_id, a_bool_t * enable) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _isis_napt_status_get(dev_id, enable); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Set working mode of NAPT engine on a particular device - * @param[in] dev_id device id - * @param[in] mode NAPT mode - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -isis_napt_mode_set(a_uint32_t dev_id, fal_napt_mode_t mode) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _isis_napt_mode_set(dev_id, mode); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Get working mode of NAPT engine on a particular device - * @param[in] dev_id device id - * @param[out] mode NAPT mode - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -isis_napt_mode_get(a_uint32_t dev_id, fal_napt_mode_t * mode) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _isis_napt_mode_get(dev_id, mode); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Set IP4 private base address on a particular device - * @details Comments: - Only 20bits is meaning which 20bits is determined by private address mode. - * @param[in] dev_id device id - * @param[in] addr private base address - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -isis_nat_prv_base_addr_set(a_uint32_t dev_id, fal_ip4_addr_t addr) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _isis_nat_prv_base_addr_set(dev_id, addr); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Get IP4 private base address on a particular device - * @param[in] dev_id device id - * @param[out] addr private base address - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -isis_nat_prv_base_addr_get(a_uint32_t dev_id, fal_ip4_addr_t * addr) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _isis_nat_prv_base_addr_get(dev_id, addr); - HSL_API_UNLOCK; - return rv; -} - -#if 0 -/** - * @brief Set IP4 private base address on a particular device - * @details Comments: - Only 20bits is meaning which 20bits is determined by private address mode. - * @param[in] dev_id device id - * @param[in] addr private base address - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -isis_nat_psr_prv_base_addr_set(a_uint32_t dev_id, fal_ip4_addr_t addr) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _isis_nat_psr_prv_base_addr_set(dev_id, addr); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Get IP4 private base address on a particular device - * @param[in] dev_id device id - * @param[out] addr private base address - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -isis_nat_psr_prv_base_addr_get(a_uint32_t dev_id, fal_ip4_addr_t * addr) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _isis_nat_psr_prv_base_addr_get(dev_id, addr); - HSL_API_UNLOCK; - return rv; -} -#endif - -/** - * @brief Set IP4 private base address mode on a particular device - * @details Comments: - If map_en equal true means bits31-20 bits15-8 are base address - else bits31-12 are base address. - * @param[in] dev_id device id - * @param[in] map_en private base mapping mode - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -isis_nat_prv_addr_mode_set(a_uint32_t dev_id, a_bool_t map_en) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _isis_nat_prv_addr_mode_set(dev_id, map_en); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Get IP4 private base address mode on a particular device - * @param[in] dev_id device id - * @param[out] map_en private base mapping mode - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -isis_nat_prv_addr_mode_get(a_uint32_t dev_id, a_bool_t * map_en) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _isis_nat_prv_addr_mode_get(dev_id, map_en); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Add one public address entry to one particular device. - * @details Comments: - Hardware entry id will be returned. - * @param[in] dev_id device id - * @param[in] entry public address entry parameter - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -isis_nat_pub_addr_add(a_uint32_t dev_id, fal_nat_pub_addr_t * entry) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _isis_nat_pub_addr_add(dev_id, entry); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Delete one public address entry from one particular device. - * @param[in] dev_id device id - * @param[in] del_mode delete operaton mode - * @param[in] entry public address entry parameter - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -isis_nat_pub_addr_del(a_uint32_t dev_id, a_uint32_t del_mode, - fal_nat_pub_addr_t * entry) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _isis_nat_pub_addr_del(dev_id, del_mode, entry); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Next public address entries from one particular device. - * @param[in] dev_id device id - * @param[in] next_mode next operaton mode - * @param[out] entry public address entry parameter - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -isis_nat_pub_addr_next(a_uint32_t dev_id, a_uint32_t next_mode, - fal_nat_pub_addr_t * entry) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _isis_nat_pub_addr_next(dev_id, next_mode, entry); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Set forwarding command for those packets miss NAT entries on a particular device. - * @param[in] dev_id device id - * @param[in] cmd forwarding command - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -isis_nat_unk_session_cmd_set(a_uint32_t dev_id, fal_fwd_cmd_t cmd) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _isis_nat_unk_session_cmd_set(dev_id, cmd); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Get forwarding command for those packets miss NAT entries on a particular device. - * @param[in] dev_id device id - * @param[out] cmd forwarding command - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -isis_nat_unk_session_cmd_get(a_uint32_t dev_id, fal_fwd_cmd_t * cmd) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _isis_nat_unk_session_cmd_get(dev_id, cmd); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Set working status of NAT engine on a particular device - * @param[in] dev_id device id - * @param[in] enable A_TRUE or A_FALSE - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -isis_nat_global_set(a_uint32_t dev_id, a_bool_t enable, a_uint32_t portbmp) -{ - sw_error_t rv = SW_OK; - - HSL_API_LOCK; - printk("enable:%d\n", enable); - if(enable) { - if(isis_nat_global_status == 0) { - isis_nat_global_status = 1; -#if defined(IN_NAT_HELPER) - ISIS_NAT_HELPER_INIT(rv, dev_id, portbmp); -#endif - } - } else { - if(isis_nat_global_status == 1) { - isis_nat_global_status = 0; -#if defined(IN_NAT_HELPER) - ISIS_NAT_HELPER_CLEANUP(rv, dev_id); -#endif - } - } - //rv = SW_OK; - HSL_API_UNLOCK; - return rv; -} - - -sw_error_t -isis_nat_init(a_uint32_t dev_id) -{ - sw_error_t rv; - - HSL_DEV_ID_CHECK(dev_id); - - rv = isis_nat_reset(dev_id); - SW_RTN_ON_ERROR(rv); - -#ifndef HSL_STANDALONG - { - hsl_api_t *p_api; - - SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id)); - - p_api->nat_add = isis_nat_add; - p_api->nat_del = isis_nat_del; - p_api->nat_get = isis_nat_get; - p_api->nat_next = isis_nat_next; - p_api->nat_counter_bind = isis_nat_counter_bind; - p_api->napt_add = isis_napt_add; - p_api->napt_del = isis_napt_del; - p_api->napt_get = isis_napt_get; - p_api->napt_next = isis_napt_next; - p_api->napt_counter_bind = isis_napt_counter_bind; - p_api->nat_status_set = isis_nat_status_set; - p_api->nat_status_get = isis_nat_status_get; - p_api->nat_hash_mode_set = isis_nat_hash_mode_set; - p_api->nat_hash_mode_get = isis_nat_hash_mode_get; - p_api->napt_status_set = isis_napt_status_set; - p_api->napt_status_get = isis_napt_status_get; - p_api->napt_mode_set = isis_napt_mode_set; - p_api->napt_mode_get = isis_napt_mode_get; - p_api->nat_prv_base_addr_set = isis_nat_prv_base_addr_set; - p_api->nat_prv_base_addr_get = isis_nat_prv_base_addr_get; - p_api->nat_prv_addr_mode_set = isis_nat_prv_addr_mode_set; - p_api->nat_prv_addr_mode_get = isis_nat_prv_addr_mode_get; - p_api->nat_pub_addr_add = isis_nat_pub_addr_add; - p_api->nat_pub_addr_del = isis_nat_pub_addr_del; - p_api->nat_pub_addr_next = isis_nat_pub_addr_next; - p_api->nat_unk_session_cmd_set = isis_nat_unk_session_cmd_set; - p_api->nat_unk_session_cmd_get = isis_nat_unk_session_cmd_get; - p_api->nat_global_set = isis_nat_global_set; - } -#endif - - return SW_OK; -} - -/** - * @} - */ diff --git a/feeds/ipq807x/qca-ssdk/src/src/hsl/isis/isis_port_ctrl.c b/feeds/ipq807x/qca-ssdk/src/src/hsl/isis/isis_port_ctrl.c deleted file mode 100755 index 00531cce1..000000000 --- a/feeds/ipq807x/qca-ssdk/src/src/hsl/isis/isis_port_ctrl.c +++ /dev/null @@ -1,2356 +0,0 @@ -/* - * Copyright (c) 2012, 2015-2017, The Linux Foundation. All rights reserved. - * Permission to use, copy, modify, and/or distribute this software for - * any purpose with or without fee is hereby granted, provided that the - * above copyright notice and this permission notice appear in all copies. - * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES - * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR - * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES - * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN - * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT - * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. - */ - - -/** - * @defgroup isis_port_ctrl ISIS_PORT_CONTROL - * @{ - */ -#include "sw.h" -#include "hsl.h" -#include "hsl_dev.h" -#include "hsl_port_prop.h" -#include "isis_port_ctrl.h" -#include "isis_reg.h" -#include "hsl_phy.h" - -static a_bool_t -_isis_port_phy_connected(a_uint32_t dev_id, fal_port_t port_id) -{ - if ((0 == port_id) || (6 == port_id)) - { - return A_FALSE; - } - else - { - return A_TRUE; - } -} - -static sw_error_t -_isis_port_duplex_set(a_uint32_t dev_id, fal_port_t port_id, - fal_port_duplex_t duplex) -{ - sw_error_t rv; - a_uint32_t phy_id, reg_save, reg_val = 0, force, tmp; - hsl_phy_ops_t *phy_drv; - - HSL_DEV_ID_CHECK(dev_id); - - if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU)) - { - return SW_BAD_PARAM; - } - - if (FAL_DUPLEX_BUTT <= duplex) - { - return SW_BAD_PARAM; - } - - HSL_REG_ENTRY_GET(rv, dev_id, PORT_STATUS, port_id, - (a_uint8_t *) (®_val), sizeof (a_uint32_t)); - SW_GET_FIELD_BY_REG(PORT_STATUS, DUPLEX_MODE, tmp, reg_val); - - /* for those ports without PHY device we set MAC register */ - if (A_FALSE == _isis_port_phy_connected(dev_id, port_id)) - { - SW_SET_REG_BY_FIELD(PORT_STATUS, LINK_EN, 0, reg_val); - if (FAL_HALF_DUPLEX == duplex) - { - if (tmp == 0) - return SW_OK; - SW_SET_REG_BY_FIELD(PORT_STATUS, DUPLEX_MODE, 0, reg_val); - } - else - { - if (tmp == 1) - return SW_OK; - SW_SET_REG_BY_FIELD(PORT_STATUS, DUPLEX_MODE, 1, reg_val); - } - reg_save = reg_val; - } - else - { - SW_RTN_ON_NULL (phy_drv = hsl_phy_api_ops_get (dev_id, port_id)); - if (NULL == phy_drv->phy_duplex_set) - return SW_NOT_SUPPORTED; - /* hardware requirement: set mac be config by sw and turn off RX/TX MAC */ - rv = hsl_port_prop_get_phyid(dev_id, port_id, &phy_id); - SW_RTN_ON_ERROR(rv); - rv = phy_drv->phy_duplex_get (dev_id, phy_id, &tmp); - SW_RTN_ON_ERROR(rv); - if (tmp == duplex) - return SW_OK; - reg_save = reg_val; - SW_SET_REG_BY_FIELD(PORT_STATUS, LINK_EN, 0, reg_val); - SW_SET_REG_BY_FIELD(PORT_STATUS, RXMAC_EN, 0, reg_val); - SW_SET_REG_BY_FIELD(PORT_STATUS, TXMAC_EN, 0, reg_val); - - HSL_REG_ENTRY_SET(rv, dev_id, PORT_STATUS, port_id, - (a_uint8_t *) (®_val), sizeof (a_uint32_t)); - - - rv = phy_drv->phy_duplex_set (dev_id, phy_id, duplex); - SW_RTN_ON_ERROR(rv); - - /* If MAC not in sync with PHY mode, the behavior is undefine. - You must be careful... */ - SW_GET_FIELD_BY_REG(PORT_STATUS, LINK_EN, force, reg_save); - if (!force) - { - if (FAL_HALF_DUPLEX == duplex) - { - SW_SET_REG_BY_FIELD(PORT_STATUS, DUPLEX_MODE, 0, reg_save); - } - else - { - SW_SET_REG_BY_FIELD(PORT_STATUS, DUPLEX_MODE, 1, reg_save); - } - } - } - - HSL_REG_ENTRY_SET(rv, dev_id, PORT_STATUS, port_id, - (a_uint8_t *) (®_save), sizeof (a_uint32_t)); - return rv; -} - -static sw_error_t -_isis_port_duplex_get(a_uint32_t dev_id, fal_port_t port_id, - fal_port_duplex_t * pduplex) -{ - sw_error_t rv; - a_uint32_t reg = 0, field; - HSL_DEV_ID_CHECK(dev_id); - - if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU)) - { - return SW_BAD_PARAM; - } - HSL_REG_ENTRY_GET(rv, dev_id, PORT_STATUS, port_id, - (a_uint8_t *) (®), sizeof (a_uint32_t)); - SW_GET_FIELD_BY_REG(PORT_STATUS, DUPLEX_MODE, field, reg); - if (field) - { - *pduplex = FAL_FULL_DUPLEX; - } - else - { - *pduplex = FAL_HALF_DUPLEX; - } - - return rv; -} - -static sw_error_t -_isis_port_speed_set(a_uint32_t dev_id, fal_port_t port_id, - fal_port_speed_t speed) -{ - sw_error_t rv; - a_uint32_t phy_id, reg_save, reg_val = 0, force, tmp; - hsl_phy_ops_t *phy_drv; - - HSL_DEV_ID_CHECK(dev_id); - - if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU)) - { - return SW_BAD_PARAM; - } - - if (FAL_SPEED_1000 < speed) - { - return SW_BAD_PARAM; - } - - HSL_REG_ENTRY_GET(rv, dev_id, PORT_STATUS, port_id, - (a_uint8_t *) (®_val), sizeof (a_uint32_t)); - SW_GET_FIELD_BY_REG(PORT_STATUS, SPEED_MODE, tmp, reg_val); - - /* for those ports without PHY device we set MAC register */ - if (A_FALSE == _isis_port_phy_connected(dev_id, port_id)) - { - SW_SET_REG_BY_FIELD(PORT_STATUS, LINK_EN, 0, reg_val); - if (FAL_SPEED_10 == speed) - { - if (tmp == 0) - return SW_OK; - SW_SET_REG_BY_FIELD(PORT_STATUS, SPEED_MODE, 0, reg_val); - } - else if (FAL_SPEED_100 == speed) - { - if (tmp == 1) - return SW_OK; - SW_SET_REG_BY_FIELD(PORT_STATUS, SPEED_MODE, 1, reg_val); - } - else - { - if (tmp == 2) - return SW_OK; - SW_SET_REG_BY_FIELD(PORT_STATUS, SPEED_MODE, 2, reg_val); - } - reg_save = reg_val; - - } - else - { - SW_RTN_ON_NULL (phy_drv = hsl_phy_api_ops_get (dev_id, port_id)); - if (NULL == phy_drv->phy_speed_set) - return SW_NOT_SUPPORTED; - /* hardware requirement: set mac be config by sw and turn off RX/TX MAC */ - rv = hsl_port_prop_get_phyid(dev_id, port_id, &phy_id); - SW_RTN_ON_ERROR(rv); - rv = phy_drv->phy_speed_get (dev_id, phy_id, &tmp); - SW_RTN_ON_ERROR(rv); - if (tmp == speed) - return SW_OK; - reg_save = reg_val; - SW_SET_REG_BY_FIELD(PORT_STATUS, LINK_EN, 0, reg_val); - SW_SET_REG_BY_FIELD(PORT_STATUS, RXMAC_EN, 0, reg_val); - SW_SET_REG_BY_FIELD(PORT_STATUS, TXMAC_EN, 0, reg_val); - - HSL_REG_ENTRY_SET(rv, dev_id, PORT_STATUS, port_id, - (a_uint8_t *) (®_val), sizeof (a_uint32_t)); - - rv = phy_drv->phy_speed_set (dev_id, phy_id, speed); - SW_RTN_ON_ERROR(rv); - - /* If MAC not in sync with PHY mode, the behavior is undefine. - You must be careful... */ - SW_GET_FIELD_BY_REG(PORT_STATUS, LINK_EN, force, reg_save); - if (!force) - { - if (FAL_SPEED_10 == speed) - { - SW_SET_REG_BY_FIELD(PORT_STATUS, SPEED_MODE, 0, reg_save); - } - else if (FAL_SPEED_100 == speed) - { - SW_SET_REG_BY_FIELD(PORT_STATUS, SPEED_MODE, 1, reg_save); - } - else - { - SW_SET_REG_BY_FIELD(PORT_STATUS, SPEED_MODE, 2, reg_save); - } - } - } - - HSL_REG_ENTRY_SET(rv, dev_id, PORT_STATUS, port_id, - (a_uint8_t *) (®_save), sizeof (a_uint32_t)); - return rv; -} - -static sw_error_t -_isis_port_speed_get(a_uint32_t dev_id, fal_port_t port_id, - fal_port_speed_t * pspeed) -{ - sw_error_t rv = SW_OK; - a_uint32_t reg = 0, field; - - HSL_DEV_ID_CHECK(dev_id); - - if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU)) - { - return SW_BAD_PARAM; - } - - HSL_REG_ENTRY_GET(rv, dev_id, PORT_STATUS, port_id, - (a_uint8_t *) (®), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - - SW_GET_FIELD_BY_REG(PORT_STATUS, SPEED_MODE, field, reg); - if (0 == field) - { - *pspeed = FAL_SPEED_10; - } - else if (1 == field) - { - *pspeed = FAL_SPEED_100; - } - else if (2 == field) - { - *pspeed = FAL_SPEED_1000; - } - else - { - *pspeed = FAL_SPEED_BUTT; - rv = SW_READ_ERROR; - } - - return rv; -} - -static sw_error_t -_isis_port_autoneg_status_get(a_uint32_t dev_id, fal_port_t port_id, - a_bool_t * status) -{ - a_uint32_t phy_id; - sw_error_t rv; - hsl_phy_ops_t *phy_drv; - - HSL_DEV_ID_CHECK(dev_id); - - if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_PHY)) - { - return SW_BAD_PARAM; - } - - SW_RTN_ON_NULL (phy_drv = hsl_phy_api_ops_get (dev_id, port_id)); - if (NULL == phy_drv->phy_autoneg_status_get) - return SW_NOT_SUPPORTED; - - rv = hsl_port_prop_get_phyid(dev_id, port_id, &phy_id); - SW_RTN_ON_ERROR(rv); - - *status = phy_drv->phy_autoneg_status_get (dev_id, phy_id); - - return SW_OK; -} - -static sw_error_t -_isis_port_autoneg_enable(a_uint32_t dev_id, fal_port_t port_id) -{ - sw_error_t rv; - a_uint32_t phy_id; - hsl_phy_ops_t *phy_drv; - - HSL_DEV_ID_CHECK(dev_id); - - if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_PHY)) - { - return SW_BAD_PARAM; - } - - SW_RTN_ON_NULL (phy_drv = hsl_phy_api_ops_get (dev_id, port_id)); - if (NULL == phy_drv->phy_autoneg_enable_set) - return SW_NOT_SUPPORTED; - - rv = hsl_port_prop_get_phyid(dev_id, port_id, &phy_id); - SW_RTN_ON_ERROR(rv); - - rv = phy_drv->phy_autoneg_enable_set(dev_id, phy_id); - return rv; -} - -static sw_error_t -_isis_port_autoneg_restart(a_uint32_t dev_id, fal_port_t port_id) -{ - sw_error_t rv; - a_uint32_t phy_id; - hsl_phy_ops_t *phy_drv; - - HSL_DEV_ID_CHECK(dev_id); - - if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_PHY)) - { - return SW_BAD_PARAM; - } - - SW_RTN_ON_NULL (phy_drv = hsl_phy_api_ops_get (dev_id, port_id)); - if (NULL == phy_drv->phy_restart_autoneg) - return SW_NOT_SUPPORTED; - - rv = hsl_port_prop_get_phyid(dev_id, port_id, &phy_id); - SW_RTN_ON_ERROR(rv); - - rv = phy_drv->phy_restart_autoneg (dev_id, phy_id); - return rv; -} - -static sw_error_t -_isis_port_autoneg_adv_set(a_uint32_t dev_id, fal_port_t port_id, - a_uint32_t autoadv) -{ - sw_error_t rv; - a_uint32_t phy_id; - hsl_phy_ops_t *phy_drv; - - HSL_DEV_ID_CHECK(dev_id); - - if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_PHY)) - { - return SW_BAD_PARAM; - } - - SW_RTN_ON_NULL (phy_drv = hsl_phy_api_ops_get (dev_id, port_id)); - if (NULL == phy_drv->phy_autoneg_adv_set) - return SW_NOT_SUPPORTED; - - rv = hsl_port_prop_get_phyid(dev_id, port_id, &phy_id); - SW_RTN_ON_ERROR(rv); - - rv = phy_drv->phy_autoneg_adv_set(dev_id, phy_id, autoadv); - SW_RTN_ON_ERROR(rv); - - return SW_OK; -} - -static sw_error_t -_isis_port_autoneg_adv_get(a_uint32_t dev_id, fal_port_t port_id, - a_uint32_t * autoadv) -{ - sw_error_t rv; - a_uint32_t phy_id; - hsl_phy_ops_t *phy_drv; - - HSL_DEV_ID_CHECK(dev_id); - - if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_PHY)) - { - return SW_BAD_PARAM; - } - - SW_RTN_ON_NULL (phy_drv = hsl_phy_api_ops_get (dev_id, port_id)); - if (NULL == phy_drv->phy_autoneg_adv_get) - return SW_NOT_SUPPORTED; - - rv = hsl_port_prop_get_phyid(dev_id, port_id, &phy_id); - SW_RTN_ON_ERROR(rv); - - *autoadv = 0; - rv = phy_drv->phy_autoneg_adv_get (dev_id, phy_id, autoadv); - SW_RTN_ON_ERROR(rv); - - return SW_OK; -} - -static sw_error_t -_isis_port_flowctrl_set(a_uint32_t dev_id, fal_port_t port_id, a_bool_t enable) -{ - sw_error_t rv; - a_uint32_t val, force, reg = 0, tmp; - - if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU)) - { - return SW_BAD_PARAM; - } - - if (A_TRUE == enable) - { - val = 1; - } - else if (A_FALSE == enable) - { - val = 0; - } - else - { - return SW_BAD_PARAM; - } - - HSL_REG_ENTRY_GET(rv, dev_id, PORT_STATUS, port_id, - (a_uint8_t *) (®), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - - SW_GET_FIELD_BY_REG(PORT_STATUS, FLOW_LINK_EN, force, reg); - if (force) - { - /* flow control isn't in force mode so can't set */ - return SW_DISABLE; - } - tmp = reg; - - SW_SET_REG_BY_FIELD(PORT_STATUS, RX_FLOW_EN, val, reg); - SW_SET_REG_BY_FIELD(PORT_STATUS, TX_FLOW_EN, val, reg); - SW_SET_REG_BY_FIELD(PORT_STATUS, TX_HALF_FLOW_EN, val, reg); - if (tmp == reg) - return SW_OK; - - HSL_REG_ENTRY_SET(rv, dev_id, PORT_STATUS, port_id, - (a_uint8_t *) (®), sizeof (a_uint32_t)); - return rv; -} - -static sw_error_t -_isis_port_flowctrl_get(a_uint32_t dev_id, fal_port_t port_id, - a_bool_t * enable) -{ - sw_error_t rv; - a_uint32_t rx, reg = 0; - - if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU)) - { - return SW_BAD_PARAM; - } - - HSL_REG_ENTRY_GET(rv, dev_id, PORT_STATUS, port_id, - (a_uint8_t *) (®), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - - SW_GET_FIELD_BY_REG(PORT_STATUS, RX_FLOW_EN, rx, reg); - - if (1 == rx) - { - *enable = A_TRUE; - } - else - { - *enable = A_FALSE; - } - - return SW_OK; -} - -static sw_error_t -_isis_port_flowctrl_forcemode_set(a_uint32_t dev_id, fal_port_t port_id, - a_bool_t enable) -{ - sw_error_t rv; - a_uint32_t reg = 0, tmp; - - if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU)) - { - return SW_BAD_PARAM; - } - - HSL_REG_ENTRY_GET(rv, dev_id, PORT_STATUS, port_id, - (a_uint8_t *) (®), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - SW_GET_FIELD_BY_REG(PORT_STATUS, FLOW_LINK_EN, tmp, reg); - - if (A_TRUE == enable) - { - if (tmp == 0) - return SW_OK; - SW_SET_REG_BY_FIELD(PORT_STATUS, FLOW_LINK_EN, 0, reg); - } - else if (A_FALSE == enable) - { - /* for those ports without PHY, it can't sync flow control status */ - if (A_FALSE == _isis_port_phy_connected(dev_id, port_id)) - { - return SW_DISABLE; - } - if (tmp == 1) - return SW_OK; - SW_SET_REG_BY_FIELD(PORT_STATUS, FLOW_LINK_EN, 1, reg); - } - else - { - return SW_BAD_PARAM; - } - - HSL_REG_ENTRY_SET(rv, dev_id, PORT_STATUS, port_id, - (a_uint8_t *) (®), sizeof (a_uint32_t)); - return rv; -} - -static sw_error_t -_isis_port_flowctrl_forcemode_get(a_uint32_t dev_id, fal_port_t port_id, - a_bool_t * enable) -{ - sw_error_t rv; - a_uint32_t force, reg = 0; - - if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU)) - { - return SW_BAD_PARAM; - } - - HSL_REG_ENTRY_GET(rv, dev_id, PORT_STATUS, port_id, - (a_uint8_t *) (®), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - - SW_GET_FIELD_BY_REG(PORT_STATUS, FLOW_LINK_EN, force, reg); - if (0 == force) - { - *enable = A_TRUE; - } - else - { - *enable = A_FALSE; - } - - return SW_OK; -} - -static sw_error_t -_isis_port_powersave_set(a_uint32_t dev_id, fal_port_t port_id, a_bool_t enable) -{ - sw_error_t rv; - a_uint32_t phy_id = 0; - hsl_phy_ops_t *phy_drv; - - HSL_DEV_ID_CHECK(dev_id); - - if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_PHY)) - { - return SW_BAD_PARAM; - } - - SW_RTN_ON_NULL (phy_drv = hsl_phy_api_ops_get (dev_id, port_id)); - if (NULL == phy_drv->phy_powersave_set) - return SW_NOT_SUPPORTED; - - rv = hsl_port_prop_get_phyid(dev_id, port_id, &phy_id); - SW_RTN_ON_ERROR(rv); - - rv = phy_drv->phy_powersave_set(dev_id, phy_id, enable); - - return rv; -} - -static sw_error_t -_isis_port_powersave_get(a_uint32_t dev_id, fal_port_t port_id, - a_bool_t * enable) -{ - sw_error_t rv; - a_uint32_t phy_id = 0; - hsl_phy_ops_t *phy_drv; - - HSL_DEV_ID_CHECK(dev_id); - - if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_PHY)) - { - return SW_BAD_PARAM; - } - - SW_RTN_ON_NULL (phy_drv = hsl_phy_api_ops_get (dev_id, port_id)); - if (NULL == phy_drv->phy_powersave_get) - return SW_NOT_SUPPORTED; - - rv = hsl_port_prop_get_phyid(dev_id, port_id, &phy_id); - SW_RTN_ON_ERROR(rv); - - rv = phy_drv->phy_powersave_get(dev_id, phy_id, enable); - - return rv; -} - -static sw_error_t -_isis_port_hibernate_set(a_uint32_t dev_id, fal_port_t port_id, a_bool_t enable) -{ - sw_error_t rv; - a_uint32_t phy_id = 0; - hsl_phy_ops_t *phy_drv; - - HSL_DEV_ID_CHECK(dev_id); - - if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_PHY)) - { - return SW_BAD_PARAM; - } - - SW_RTN_ON_NULL (phy_drv = hsl_phy_api_ops_get (dev_id, port_id)); - if (NULL == phy_drv->phy_hibernation_set) - return SW_NOT_SUPPORTED; - - rv = hsl_port_prop_get_phyid(dev_id, port_id, &phy_id); - SW_RTN_ON_ERROR(rv); - - rv = phy_drv->phy_hibernation_set (dev_id, phy_id, enable); - - return rv; -} - -static sw_error_t -_isis_port_hibernate_get(a_uint32_t dev_id, fal_port_t port_id, - a_bool_t * enable) -{ - sw_error_t rv; - a_uint32_t phy_id = 0; - hsl_phy_ops_t *phy_drv; - - HSL_DEV_ID_CHECK(dev_id); - - if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_PHY)) - { - return SW_BAD_PARAM; - } - - SW_RTN_ON_NULL (phy_drv = hsl_phy_api_ops_get (dev_id, port_id)); - if (NULL == phy_drv->phy_hibernation_get) - return SW_NOT_SUPPORTED; - - rv = hsl_port_prop_get_phyid(dev_id, port_id, &phy_id); - SW_RTN_ON_ERROR(rv); - - rv = phy_drv->phy_hibernation_get(dev_id, phy_id, enable); - - return rv; -} - -static sw_error_t -_isis_port_cdt(a_uint32_t dev_id, fal_port_t port_id, a_uint32_t mdi_pair, - fal_cable_status_t * cable_status, a_uint32_t * cable_len) -{ - sw_error_t rv; - a_uint32_t phy_id = 0; - hsl_phy_ops_t *phy_drv; - - HSL_DEV_ID_CHECK(dev_id); - - if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_PHY)) - { - return SW_BAD_PARAM; - } - - SW_RTN_ON_NULL (phy_drv = hsl_phy_api_ops_get (dev_id, port_id)); - if (NULL == phy_drv->phy_cdt) - return SW_NOT_SUPPORTED; - - rv = hsl_port_prop_get_phyid(dev_id, port_id, &phy_id); - SW_RTN_ON_ERROR(rv); - - rv = phy_drv->phy_cdt(dev_id, phy_id, mdi_pair, cable_status, cable_len); - - return rv; -} -static sw_error_t -_isis_port_8023az_set (a_uint32_t dev_id, fal_port_t port_id, a_bool_t enable) -{ - sw_error_t rv; - a_uint32_t phy_id = 0; - hsl_phy_ops_t *phy_drv; - - HSL_DEV_ID_CHECK (dev_id); - if (A_TRUE != hsl_port_prop_check (dev_id, port_id, HSL_PP_PHY)) - { - return SW_BAD_PARAM; - } - - SW_RTN_ON_NULL (phy_drv = hsl_phy_api_ops_get (dev_id, port_id)); - if (NULL == phy_drv->phy_8023az_set) - return SW_NOT_SUPPORTED; - - rv = hsl_port_prop_get_phyid (dev_id, port_id, &phy_id); - SW_RTN_ON_ERROR (rv); - - rv = phy_drv->phy_8023az_set (dev_id, phy_id, enable); - - return rv; -} - -static sw_error_t -_isis_port_8023az_get (a_uint32_t dev_id, fal_port_t port_id, - a_bool_t * enable) -{ - sw_error_t rv; - a_uint32_t phy_id = 0; - hsl_phy_ops_t *phy_drv; - - HSL_DEV_ID_CHECK (dev_id); - - if (A_TRUE != hsl_port_prop_check (dev_id, port_id, HSL_PP_PHY)) - { - return SW_BAD_PARAM; - } - - SW_RTN_ON_NULL (phy_drv = hsl_phy_api_ops_get (dev_id, port_id)); - if (NULL == phy_drv->phy_8023az_get) - return SW_NOT_SUPPORTED; - - rv = hsl_port_prop_get_phyid (dev_id, port_id, &phy_id); - SW_RTN_ON_ERROR (rv); - - rv = phy_drv->phy_8023az_get (dev_id, phy_id, enable); - - return rv; -} - -static sw_error_t -_isis_port_rxhdr_mode_set(a_uint32_t dev_id, fal_port_t port_id, - fal_port_header_mode_t mode) -{ - sw_error_t rv; - a_uint32_t val; - - HSL_DEV_ID_CHECK(dev_id); - - if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU)) - { - return SW_BAD_PARAM; - } - - if (FAL_NO_HEADER_EN == mode) - { - val = 0; - } - else if (FAL_ONLY_MANAGE_FRAME_EN == mode) - { - val = 1; - } - else if (FAL_ALL_TYPE_FRAME_EN == mode) - { - val = 2; - } - else - { - return SW_BAD_PARAM; - } - - HSL_REG_FIELD_SET(rv, dev_id, PORT_HDR_CTL, port_id, RXHDR_MODE, - (a_uint8_t *) (&val), sizeof (a_uint32_t)); - return rv; -} - -static sw_error_t -_isis_port_rxhdr_mode_get(a_uint32_t dev_id, fal_port_t port_id, - fal_port_header_mode_t * mode) -{ - sw_error_t rv; - a_uint32_t val = 0; - - HSL_DEV_ID_CHECK(dev_id); - - if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU)) - { - return SW_BAD_PARAM; - } - - HSL_REG_FIELD_GET(rv, dev_id, PORT_HDR_CTL, port_id, RXHDR_MODE, - (a_uint8_t *) (&val), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - - if (1 == val) - { - *mode = FAL_ONLY_MANAGE_FRAME_EN; - } - else if (2 == val) - { - *mode = FAL_ALL_TYPE_FRAME_EN; - } - else - { - *mode = FAL_NO_HEADER_EN; - } - - return SW_OK; -} - -static sw_error_t -_isis_port_txhdr_mode_set(a_uint32_t dev_id, fal_port_t port_id, - fal_port_header_mode_t mode) -{ - sw_error_t rv; - a_uint32_t val; - - HSL_DEV_ID_CHECK(dev_id); - - if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU)) - { - return SW_BAD_PARAM; - } - - if (FAL_NO_HEADER_EN == mode) - { - val = 0; - } - else if (FAL_ONLY_MANAGE_FRAME_EN == mode) - { - val = 1; - } - else if (FAL_ALL_TYPE_FRAME_EN == mode) - { - val = 2; - } - else - { - return SW_BAD_PARAM; - } - - HSL_REG_FIELD_SET(rv, dev_id, PORT_HDR_CTL, port_id, TXHDR_MODE, - (a_uint8_t *) (&val), sizeof (a_uint32_t)); - return rv; -} - -static sw_error_t -_isis_port_txhdr_mode_get(a_uint32_t dev_id, fal_port_t port_id, - fal_port_header_mode_t * mode) -{ - sw_error_t rv; - a_uint32_t val = 0; - - HSL_DEV_ID_CHECK(dev_id); - - if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU)) - { - return SW_BAD_PARAM; - } - - HSL_REG_FIELD_GET(rv, dev_id, PORT_HDR_CTL, port_id, TXHDR_MODE, - (a_uint8_t *) (&val), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - - if (1 == val) - { - *mode = FAL_ONLY_MANAGE_FRAME_EN; - } - else if (2 == val) - { - *mode = FAL_ALL_TYPE_FRAME_EN; - } - else - { - *mode = FAL_NO_HEADER_EN; - } - - return SW_OK; -} - -static sw_error_t -_isis_header_type_set(a_uint32_t dev_id, a_bool_t enable, a_uint32_t type) -{ - a_uint32_t reg = 0; - sw_error_t rv; - - HSL_DEV_ID_CHECK(dev_id); - - HSL_REG_ENTRY_GET(rv, dev_id, HEADER_CTL, 0, - (a_uint8_t *) (®), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - - if (A_TRUE == enable) - { - if (0xffff < type) - { - return SW_BAD_PARAM; - } - SW_SET_REG_BY_FIELD(HEADER_CTL, TYPE_LEN, 1, reg); - SW_SET_REG_BY_FIELD(HEADER_CTL, TYPE_VAL, type, reg); - } - else if (A_FALSE == enable) - { - SW_SET_REG_BY_FIELD(HEADER_CTL, TYPE_LEN, 0, reg); - SW_SET_REG_BY_FIELD(HEADER_CTL, TYPE_VAL, 0, reg); - } - else - { - return SW_BAD_PARAM; - } - - HSL_REG_ENTRY_SET(rv, dev_id, HEADER_CTL, 0, - (a_uint8_t *) (®), sizeof (a_uint32_t)); - return rv; -} - -static sw_error_t -_isis_header_type_get(a_uint32_t dev_id, a_bool_t * enable, a_uint32_t * type) -{ - a_uint32_t data, reg = 0; - sw_error_t rv; - - HSL_DEV_ID_CHECK(dev_id); - - HSL_REG_ENTRY_GET(rv, dev_id, HEADER_CTL, 0, - (a_uint8_t *) (®), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - - SW_GET_FIELD_BY_REG(HEADER_CTL, TYPE_LEN, data, reg); - if (data) - { - SW_GET_FIELD_BY_REG(HEADER_CTL, TYPE_VAL, data, reg); - *enable = A_TRUE; - *type = data; - } - else - { - *enable = A_FALSE; - *type = 0; - } - - return SW_OK; -} - -static sw_error_t -_isis_port_txmac_status_set(a_uint32_t dev_id, fal_port_t port_id, a_bool_t enable) -{ - sw_error_t rv; - a_uint32_t reg = 0, force, val, tmp; - - HSL_DEV_ID_CHECK(dev_id); - - if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU)) - { - return SW_BAD_PARAM; - } - - HSL_REG_ENTRY_GET(rv, dev_id, PORT_STATUS, port_id, - (a_uint8_t *) (®), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - - if (A_TRUE == enable) - { - val = 1; - } - else if (A_FALSE == enable) - { - val = 0; - } - else - { - return SW_BAD_PARAM; - } - tmp = reg; - - /* for those ports without PHY device we set MAC register */ - if (A_FALSE == _isis_port_phy_connected(dev_id, port_id)) - { - SW_SET_REG_BY_FIELD(PORT_STATUS, LINK_EN, 0, reg); - SW_SET_REG_BY_FIELD(PORT_STATUS, TXMAC_EN, val, reg); - } - else - { - SW_GET_FIELD_BY_REG(PORT_STATUS, LINK_EN, force, reg); - if (force) - { - /* link isn't in force mode so can't set */ - return SW_DISABLE; - } - else - { - SW_SET_REG_BY_FIELD(PORT_STATUS, TXMAC_EN, val, reg); - } - } - if (tmp == reg) - return SW_OK; - HSL_REG_ENTRY_SET(rv, dev_id, PORT_STATUS, port_id, - (a_uint8_t *) (®), sizeof (a_uint32_t)); - return rv; -} - -static sw_error_t -_isis_port_txmac_status_get(a_uint32_t dev_id, fal_port_t port_id, a_bool_t * enable) -{ - sw_error_t rv; - a_uint32_t val = 0; - - HSL_DEV_ID_CHECK(dev_id); - - if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU)) - { - return SW_BAD_PARAM; - } - - HSL_REG_FIELD_GET(rv, dev_id, PORT_STATUS, port_id, TXMAC_EN, - (a_uint8_t *) (&val), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - - if (val) - { - *enable = A_TRUE; - } - else - { - *enable = A_FALSE; - } - - return SW_OK; -} - -static sw_error_t -_isis_port_rxmac_status_set(a_uint32_t dev_id, fal_port_t port_id, a_bool_t enable) -{ - sw_error_t rv; - a_uint32_t reg = 0, force, val, tmp; - - HSL_DEV_ID_CHECK(dev_id); - - if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU)) - { - return SW_BAD_PARAM; - } - - HSL_REG_ENTRY_GET(rv, dev_id, PORT_STATUS, port_id, - (a_uint8_t *) (®), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - - if (A_TRUE == enable) - { - val = 1; - } - else if (A_FALSE == enable) - { - val = 0; - } - else - { - return SW_BAD_PARAM; - } - tmp = reg; - - /* for those ports without PHY device we set MAC register */ - if (A_FALSE == _isis_port_phy_connected(dev_id, port_id)) - { - SW_SET_REG_BY_FIELD(PORT_STATUS, LINK_EN, 0, reg); - SW_SET_REG_BY_FIELD(PORT_STATUS, RXMAC_EN, val, reg); - } - else - { - SW_GET_FIELD_BY_REG(PORT_STATUS, LINK_EN, force, reg); - if (force) - { - /* link isn't in force mode so can't set */ - return SW_DISABLE; - } - else - { - SW_SET_REG_BY_FIELD(PORT_STATUS, RXMAC_EN, val, reg); - } - } - if (tmp == reg) - return SW_OK; - HSL_REG_ENTRY_SET(rv, dev_id, PORT_STATUS, port_id, - (a_uint8_t *) (®), sizeof (a_uint32_t)); - return rv; -} - -static sw_error_t -_isis_port_rxmac_status_get(a_uint32_t dev_id, fal_port_t port_id, a_bool_t * enable) -{ - sw_error_t rv; - a_uint32_t val = 0; - - HSL_DEV_ID_CHECK(dev_id); - - if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU)) - { - return SW_BAD_PARAM; - } - - HSL_REG_FIELD_GET(rv, dev_id, PORT_STATUS, port_id, RXMAC_EN, - (a_uint8_t *) (&val), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - - if (val) - { - *enable = A_TRUE; - } - else - { - *enable = A_FALSE; - } - - return SW_OK; -} - -static sw_error_t -_isis_port_txfc_status_set(a_uint32_t dev_id, fal_port_t port_id, a_bool_t enable) -{ - sw_error_t rv; - a_uint32_t val, reg = 0, force, tmp; - - HSL_DEV_ID_CHECK(dev_id); - - if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU)) - { - return SW_BAD_PARAM; - } - - if (A_TRUE == enable) - { - val = 1; - } - else if (A_FALSE == enable) - { - val = 0; - } - else - { - return SW_BAD_PARAM; - } - - HSL_REG_ENTRY_GET(rv, dev_id, PORT_STATUS, port_id, - (a_uint8_t *) (®), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - tmp = reg; - - /* for those ports without PHY device we set MAC register */ - if (A_FALSE == _isis_port_phy_connected(dev_id, port_id)) - { - SW_SET_REG_BY_FIELD(PORT_STATUS, FLOW_LINK_EN, 0, reg); - SW_SET_REG_BY_FIELD(PORT_STATUS, TX_FLOW_EN, val, reg); - } - else - { - SW_GET_FIELD_BY_REG(PORT_STATUS, FLOW_LINK_EN, force, reg); - if (force) - { - /* flow control isn't in force mode so can't set */ - return SW_DISABLE; - } - else - { - SW_SET_REG_BY_FIELD(PORT_STATUS, TX_FLOW_EN, val, reg); - } - } - if ( tmp == reg) - return SW_OK; - HSL_REG_ENTRY_SET(rv, dev_id, PORT_STATUS, port_id, - (a_uint8_t *) (®), sizeof (a_uint32_t)); - return rv; -} - -static sw_error_t -_isis_port_txfc_status_get(a_uint32_t dev_id, fal_port_t port_id, a_bool_t * enable) -{ - sw_error_t rv; - a_uint32_t val = 0; - - HSL_DEV_ID_CHECK(dev_id); - - if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU)) - { - return SW_BAD_PARAM; - } - - HSL_REG_FIELD_GET(rv, dev_id, PORT_STATUS, port_id, TX_FLOW_EN, - (a_uint8_t *) (&val), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - - if (val) - { - *enable = A_TRUE; - } - else - { - *enable = A_FALSE; - } - - return SW_OK; -} - -static sw_error_t -_isis_port_rxfc_status_set(a_uint32_t dev_id, fal_port_t port_id, a_bool_t enable) -{ - sw_error_t rv; - a_uint32_t val, reg = 0, force, tmp; - - HSL_DEV_ID_CHECK(dev_id); - - if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU)) - { - return SW_BAD_PARAM; - } - - if (A_TRUE == enable) - { - val = 1; - } - else if (A_FALSE == enable) - { - val = 0; - } - else - { - return SW_BAD_PARAM; - } - - HSL_REG_ENTRY_GET(rv, dev_id, PORT_STATUS, port_id, - (a_uint8_t *) (®), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - tmp = reg; - - /* for those ports without PHY device we set MAC register */ - if (A_FALSE == _isis_port_phy_connected(dev_id, port_id)) - { - SW_SET_REG_BY_FIELD(PORT_STATUS, FLOW_LINK_EN, 0, reg); - SW_SET_REG_BY_FIELD(PORT_STATUS, RX_FLOW_EN, val, reg); - } - else - { - SW_GET_FIELD_BY_REG(PORT_STATUS, FLOW_LINK_EN, force, reg); - if (force) - { - /* flow control isn't in force mode so can't set */ - return SW_DISABLE; - } - else - { - SW_SET_REG_BY_FIELD(PORT_STATUS, RX_FLOW_EN, val, reg); - } - } - if ( tmp == reg) - return SW_OK; - HSL_REG_ENTRY_SET(rv, dev_id, PORT_STATUS, port_id, - (a_uint8_t *) (®), sizeof (a_uint32_t)); - return rv; -} - -static sw_error_t -_isis_port_rxfc_status_get(a_uint32_t dev_id, fal_port_t port_id, a_bool_t * enable) -{ - sw_error_t rv; - a_uint32_t val = 0; - - HSL_DEV_ID_CHECK(dev_id); - - if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU)) - { - return SW_BAD_PARAM; - } - - HSL_REG_FIELD_GET(rv, dev_id, PORT_STATUS, port_id, RX_FLOW_EN, - (a_uint8_t *) (&val), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - - if (val) - { - *enable = A_TRUE; - } - else - { - *enable = A_FALSE; - } - - return SW_OK; -} - -static sw_error_t -_isis_port_bp_status_set(a_uint32_t dev_id, fal_port_t port_id, a_bool_t enable) -{ - sw_error_t rv; - a_uint32_t val, tmp = 0; - - HSL_DEV_ID_CHECK(dev_id); - - if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU)) - { - return SW_BAD_PARAM; - } - - if (A_TRUE == enable) - { - val = 1; - } - else if (A_FALSE == enable) - { - val = 0; - } - else - { - return SW_BAD_PARAM; - } - HSL_REG_FIELD_GET(rv, dev_id, PORT_STATUS, port_id, TX_HALF_FLOW_EN, - (a_uint8_t *) (&tmp), sizeof (a_uint32_t)); - if (tmp == val) - return SW_OK; - HSL_REG_FIELD_SET(rv, dev_id, PORT_STATUS, port_id, TX_HALF_FLOW_EN, - (a_uint8_t *) (&val), sizeof (a_uint32_t)); - return rv; -} - -static sw_error_t -_isis_port_bp_status_get(a_uint32_t dev_id, fal_port_t port_id, a_bool_t * enable) -{ - sw_error_t rv; - a_uint32_t val = 0; - - HSL_DEV_ID_CHECK(dev_id); - - if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU)) - { - return SW_BAD_PARAM; - } - - HSL_REG_FIELD_GET(rv, dev_id, PORT_STATUS, port_id, TX_HALF_FLOW_EN, - (a_uint8_t *) (&val), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - - if (val) - { - *enable = A_TRUE; - } - else - { - *enable = A_FALSE; - } - - return SW_OK; -} - -static sw_error_t -_isis_port_link_forcemode_set(a_uint32_t dev_id, fal_port_t port_id, a_bool_t enable) -{ - sw_error_t rv; - a_uint32_t reg = 0, tmp; - - HSL_DEV_ID_CHECK(dev_id); - - if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU)) - { - return SW_BAD_PARAM; - } - - HSL_REG_ENTRY_GET(rv, dev_id, PORT_STATUS, port_id, - (a_uint8_t *) (®), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - SW_GET_FIELD_BY_REG(PORT_STATUS, LINK_EN, tmp, reg); - - if (A_TRUE == enable) - { - if(tmp == 0) - return SW_OK; - SW_SET_REG_BY_FIELD(PORT_STATUS, LINK_EN, 0, reg); - } - else if (A_FALSE == enable) - { - if(tmp == 1) - return SW_OK; - /* for those ports without PHY, it can't sync link status */ - if (A_FALSE == _isis_port_phy_connected(dev_id, port_id)) - { - return SW_DISABLE; - } - SW_SET_REG_BY_FIELD(PORT_STATUS, LINK_EN, 1, reg); - } - else - { - return SW_BAD_PARAM; - } - - HSL_REG_ENTRY_SET(rv, dev_id, PORT_STATUS, port_id, - (a_uint8_t *) (®), sizeof (a_uint32_t)); - return rv; -} - -static sw_error_t -_isis_port_link_forcemode_get(a_uint32_t dev_id, fal_port_t port_id, a_bool_t * enable) -{ - sw_error_t rv; - a_uint32_t val = 0; - - HSL_DEV_ID_CHECK(dev_id); - - if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU)) - { - return SW_BAD_PARAM; - } - - HSL_REG_FIELD_GET(rv, dev_id, PORT_STATUS, port_id, LINK_EN, - (a_uint8_t *) (&val), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - - if (0 == val) - { - *enable = A_TRUE; - } - else - { - *enable = A_FALSE; - } - - return SW_OK; -} - -static sw_error_t -_isis_port_link_status_get(a_uint32_t dev_id, fal_port_t port_id, a_bool_t * status) -{ - sw_error_t rv; - a_uint32_t phy_id; - hsl_phy_ops_t *phy_drv; - - HSL_DEV_ID_CHECK(dev_id); - - if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU)) - { - return SW_BAD_PARAM; - } - /* for those ports without PHY device supposed always link up */ - if (A_FALSE == _isis_port_phy_connected(dev_id, port_id)) - { - *status = A_TRUE; - } - else - { - SW_RTN_ON_NULL (phy_drv = hsl_phy_api_ops_get (dev_id, port_id)); - if (NULL == phy_drv->phy_link_status_get) - return SW_NOT_SUPPORTED; - - - rv = hsl_port_prop_get_phyid(dev_id, port_id, &phy_id); - SW_RTN_ON_ERROR(rv); - - if (A_TRUE == phy_drv->phy_link_status_get (dev_id, phy_id)) - { - *status = A_TRUE; - } - else - { - *status = A_FALSE; - } - } - - return SW_OK; -} - -static sw_error_t -_isis_port_mac_loopback_set(a_uint32_t dev_id, fal_port_t port_id, a_bool_t enable) -{ - sw_error_t rv; - a_uint32_t val; - - HSL_DEV_ID_CHECK(dev_id); - - if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU)) - { - return SW_BAD_PARAM; - } - - if (A_TRUE == enable) - { - val = 1; - } - else if (A_FALSE == enable) - { - val = 0; - } - else - { - return SW_BAD_PARAM; - } - - HSL_REG_FIELD_SET(rv, dev_id, PORT_HDR_CTL, port_id, LOOPBACK_EN, - (a_uint8_t *) (&val), sizeof (a_uint32_t)); - return rv; -} - -static sw_error_t -_isis_port_mac_loopback_get(a_uint32_t dev_id, fal_port_t port_id, a_bool_t *enable) -{ - sw_error_t rv; - a_uint32_t val = 0; - - HSL_DEV_ID_CHECK(dev_id); - - if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU)) - { - return SW_BAD_PARAM; - } - - HSL_REG_FIELD_GET(rv, dev_id, PORT_HDR_CTL, port_id, LOOPBACK_EN, - (a_uint8_t *) (&val), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - - if (0 == val) - { - *enable = A_FALSE; - } - else - { - *enable = A_TRUE; - } - - return SW_OK; -} - -/** - * @brief Set duplex mode on a particular port. - * @param[in] dev_id device id - * @param[in] port_id port id - * @param[in] duplex duplex mode - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -isis_port_duplex_set(a_uint32_t dev_id, fal_port_t port_id, - fal_port_duplex_t duplex) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _isis_port_duplex_set(dev_id, port_id, duplex); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Get duplex mode on a particular port. - * @param[in] dev_id device id - * @param[in] port_id port id - * @param[out] duplex duplex mode - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -isis_port_duplex_get(a_uint32_t dev_id, fal_port_t port_id, - fal_port_duplex_t * pduplex) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _isis_port_duplex_get(dev_id, port_id, pduplex); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Set speed on a particular port. - * @param[in] dev_id device id - * @param[in] port_id port id - * @param[in] speed port speed - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -isis_port_speed_set(a_uint32_t dev_id, fal_port_t port_id, - fal_port_speed_t speed) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _isis_port_speed_set(dev_id, port_id, speed); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Get speed on a particular port. - * @param[in] dev_id device id - * @param[in] port_id port id - * @param[out] speed port speed - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -isis_port_speed_get(a_uint32_t dev_id, fal_port_t port_id, - fal_port_speed_t * pspeed) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _isis_port_speed_get(dev_id, port_id, pspeed); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Get auto negotiation status on a particular port. - * @param[in] dev_id device id - * @param[in] port_id port id - * @param[out] status A_TRUE or A_FALSE - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -isis_port_autoneg_status_get(a_uint32_t dev_id, fal_port_t port_id, - a_bool_t * status) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _isis_port_autoneg_status_get(dev_id, port_id, status); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Enable auto negotiation status on a particular port. - * @param[in] dev_id device id - * @param[in] port_id port id - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -isis_port_autoneg_enable(a_uint32_t dev_id, fal_port_t port_id) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _isis_port_autoneg_enable(dev_id, port_id); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Restart auto negotiation procedule on a particular port. - * @param[in] dev_id device id - * @param[in] port_id port id - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -isis_port_autoneg_restart(a_uint32_t dev_id, fal_port_t port_id) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _isis_port_autoneg_restart(dev_id, port_id); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Set auto negotiation advtisement ability on a particular port. - * @details Comments: - * auto negotiation advtisement ability is defined by macro such as - * FAL_PHY_ADV_10T_HD, FAL_PHY_ADV_PAUSE... - * @param[in] dev_id device id - * @param[in] port_id port id - * @param[in] autoadv auto negotiation advtisement ability bit map - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -isis_port_autoneg_adv_set(a_uint32_t dev_id, fal_port_t port_id, - a_uint32_t autoadv) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _isis_port_autoneg_adv_set(dev_id, port_id, autoadv); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Get auto negotiation advtisement ability on a particular port. - * @param[in] dev_id device id - * @param[in] port_id port id - * @param[out] autoadv auto negotiation advtisement ability bit map - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -isis_port_autoneg_adv_get(a_uint32_t dev_id, fal_port_t port_id, - a_uint32_t * autoadv) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _isis_port_autoneg_adv_get(dev_id, port_id, autoadv); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Set flow control(rx/tx/bp) status on a particular port. - * @param[in] dev_id device id - * @param[in] port_id port id - * @param[in] enable A_TRUE or A_FALSE - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -isis_port_flowctrl_set(a_uint32_t dev_id, fal_port_t port_id, a_bool_t enable) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _isis_port_flowctrl_set(dev_id, port_id, enable); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Get flow control status on a particular port. - * @param[in] dev_id device id - * @param[in] port_id port id - * @param[out] enable A_TRUE or A_FALSE - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -isis_port_flowctrl_get(a_uint32_t dev_id, fal_port_t port_id, a_bool_t * enable) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _isis_port_flowctrl_get(dev_id, port_id, enable); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Set flow control force mode on a particular port. - * @param[in] dev_id device id - * @param[in] port_id port id - * @param[out] enable A_TRUE or A_FALSE - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -isis_port_flowctrl_forcemode_set(a_uint32_t dev_id, fal_port_t port_id, - a_bool_t enable) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _isis_port_flowctrl_forcemode_set(dev_id, port_id, enable); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Get flow control force mode on a particular port. - * @param[in] dev_id device id - * @param[in] port_id port id - * @param[out] enable A_TRUE or A_FALSE - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -isis_port_flowctrl_forcemode_get(a_uint32_t dev_id, fal_port_t port_id, - a_bool_t * enable) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _isis_port_flowctrl_forcemode_get(dev_id, port_id, enable); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Set powersaving status on a particular port. - * @param[in] dev_id device id - * @param[in] port_id port id - * @param[out] enable A_TRUE or A_FALSE - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -isis_port_powersave_set(a_uint32_t dev_id, fal_port_t port_id, a_bool_t enable) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _isis_port_powersave_set(dev_id, port_id, enable); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Get powersaving status on a particular port. - * @param[in] dev_id device id - * @param[in] port_id port id - * @param[out] enable A_TRUE or A_FALSE - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -isis_port_powersave_get(a_uint32_t dev_id, fal_port_t port_id, - a_bool_t * enable) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _isis_port_powersave_get(dev_id, port_id, enable); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Set hibernate status on a particular port. - * @param[in] dev_id device id - * @param[in] port_id port id - * @param[out] enable A_TRUE or A_FALSE - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -isis_port_hibernate_set(a_uint32_t dev_id, fal_port_t port_id, a_bool_t enable) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _isis_port_hibernate_set(dev_id, port_id, enable); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Get hibernate status on a particular port. - * @param[in] dev_id device id - * @param[in] port_id port id - * @param[out] enable A_TRUE or A_FALSE - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -isis_port_hibernate_get(a_uint32_t dev_id, fal_port_t port_id, - a_bool_t * enable) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _isis_port_hibernate_get(dev_id, port_id, enable); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Run cable diagnostic test on a particular port. - * @param[in] dev_id device id - * @param[in] port_id port id - * @param[in] mdi_pair mdi pair id - * @param[out] cable_status cable status - * @param[out] cable_len cable len - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -isis_port_cdt(a_uint32_t dev_id, fal_port_t port_id, a_uint32_t mdi_pair, - fal_cable_status_t * cable_status, a_uint32_t * cable_len) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _isis_port_cdt(dev_id, port_id, mdi_pair, cable_status, cable_len); - HSL_API_UNLOCK; - return rv; -} -/** - * @brief Set 802.3az status on a particular port. - * @param[in] dev_id device id - * @param[in] port_id port id - * @param[out] enable A_TRUE or A_FALSE - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -isis_port_8023az_set (a_uint32_t dev_id, fal_port_t port_id, a_bool_t enable) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _isis_port_8023az_set (dev_id, port_id, enable); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Get 8023az status on a particular port. - * @param[in] dev_id device id - * @param[in] port_id port id - * @param[out] enable A_TRUE or A_FALSE - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -isis_port_8023az_get (a_uint32_t dev_id, fal_port_t port_id, - a_bool_t * enable) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _isis_port_8023az_get (dev_id, port_id, enable); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Set status of Atheros header packets parsed on a particular port. - * @param[in] dev_id device id - * @param[in] port_id port id - * @param[in] enable A_TRUE or A_FALSE - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -isis_port_rxhdr_mode_set(a_uint32_t dev_id, fal_port_t port_id, - fal_port_header_mode_t mode) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _isis_port_rxhdr_mode_set(dev_id, port_id, mode); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Get status of Atheros header packets parsed on a particular port. - * @param[in] dev_id device id - * @param[in] port_id port id - * @param[out] enable A_TRUE or A_FALSE - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -isis_port_rxhdr_mode_get(a_uint32_t dev_id, fal_port_t port_id, - fal_port_header_mode_t * mode) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _isis_port_rxhdr_mode_get(dev_id, port_id, mode); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Set status of Atheros header packets parsed on a particular port. - * @param[in] dev_id device id - * @param[in] port_id port id - * @param[in] enable A_TRUE or A_FALSE - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -isis_port_txhdr_mode_set(a_uint32_t dev_id, fal_port_t port_id, - fal_port_header_mode_t mode) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _isis_port_txhdr_mode_set(dev_id, port_id, mode); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Get status of Atheros header packets parsed on a particular port. - * @param[in] dev_id device id - * @param[in] port_id port id - * @param[out] enable A_TRUE or A_FALSE - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -isis_port_txhdr_mode_get(a_uint32_t dev_id, fal_port_t port_id, - fal_port_header_mode_t * mode) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _isis_port_txhdr_mode_get(dev_id, port_id, mode); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Set status of Atheros header type value on a particular device. - * @param[in] dev_id device id - * @param[in] enable A_TRUE or A_FALSE - * @param[in] type header type value - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -isis_header_type_set(a_uint32_t dev_id, a_bool_t enable, a_uint32_t type) -{ - sw_error_t rv; - HSL_API_LOCK; - rv = _isis_header_type_set(dev_id, enable, type); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Get status of Atheros header type value on a particular device. - * @param[in] dev_id device id - * @param[out] enable A_TRUE or A_FALSE - * @param[out] type header type value - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -isis_header_type_get(a_uint32_t dev_id, a_bool_t * enable, a_uint32_t * type) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _isis_header_type_get(dev_id, enable, type); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Set status of txmac on a particular port. - * @param[in] dev_id device id - * @param[in] port_id port id - * @param[in] enable A_TRUE or A_FALSE - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -isis_port_txmac_status_set(a_uint32_t dev_id, fal_port_t port_id, a_bool_t enable) -{ - sw_error_t rv; - HSL_API_LOCK; - rv = _isis_port_txmac_status_set(dev_id, port_id, enable); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Get status of txmac on a particular port. - * @param[in] dev_id device id - * @param[in] port_id port id - * @param[out] enable A_TRUE or A_FALSE - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -isis_port_txmac_status_get(a_uint32_t dev_id, fal_port_t port_id, a_bool_t * enable) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _isis_port_txmac_status_get(dev_id, port_id, enable); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Set status of rxmac on a particular port. - * @param[in] dev_id device id - * @param[in] port_id port id - * @param[in] enable A_TRUE or A_FALSE - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -isis_port_rxmac_status_set(a_uint32_t dev_id, fal_port_t port_id, a_bool_t enable) -{ - sw_error_t rv; - HSL_API_LOCK; - rv = _isis_port_rxmac_status_set(dev_id, port_id, enable); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Get status of rxmac on a particular port. - * @param[in] dev_id device id - * @param[in] port_id port id - * @param[out] enable A_TRUE or A_FALSE - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -isis_port_rxmac_status_get(a_uint32_t dev_id, fal_port_t port_id, a_bool_t * enable) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _isis_port_rxmac_status_get(dev_id, port_id, enable); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Set status of tx flow control on a particular port. - * @param[in] dev_id device id - * @param[in] port_id port id - * @param[in] enable A_TRUE or A_FALSE - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -isis_port_txfc_status_set(a_uint32_t dev_id, fal_port_t port_id, a_bool_t enable) -{ - sw_error_t rv; - HSL_API_LOCK; - rv = _isis_port_txfc_status_set(dev_id, port_id, enable); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Get status of tx flow control on a particular port. - * @param[in] dev_id device id - * @param[in] port_id port id - * @param[out] enable A_TRUE or A_FALSE - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -isis_port_txfc_status_get(a_uint32_t dev_id, fal_port_t port_id, a_bool_t * enable) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _isis_port_txfc_status_get(dev_id, port_id, enable); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Set status of rx flow control on a particular port. - * @param[in] dev_id device id - * @param[in] port_id port id - * @param[in] enable A_TRUE or A_FALSE - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -isis_port_rxfc_status_set(a_uint32_t dev_id, fal_port_t port_id, a_bool_t enable) -{ - sw_error_t rv; - HSL_API_LOCK; - rv = _isis_port_rxfc_status_set(dev_id, port_id, enable); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Set status of rx flow control on a particular port. - * @param[in] dev_id device id - * @param[in] port_id port id - * @param[out] enable A_TRUE or A_FALSE - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -isis_port_rxfc_status_get(a_uint32_t dev_id, fal_port_t port_id, a_bool_t * enable) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _isis_port_rxfc_status_get(dev_id, port_id, enable); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Set status of back pressure on a particular port. - * @param[in] dev_id device id - * @param[in] port_id port id - * @param[in] enable A_TRUE or A_FALSE - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -isis_port_bp_status_set(a_uint32_t dev_id, fal_port_t port_id, a_bool_t enable) -{ - sw_error_t rv; - HSL_API_LOCK; - rv = _isis_port_bp_status_set(dev_id, port_id, enable); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Set status of back pressure on a particular port. - * @param[in] dev_id device id - * @param[in] port_id port id - * @param[out] enable A_TRUE or A_FALSE - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -isis_port_bp_status_get(a_uint32_t dev_id, fal_port_t port_id, a_bool_t * enable) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _isis_port_bp_status_get(dev_id, port_id, enable); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Set link force mode on a particular port. - * @param[in] dev_id device id - * @param[in] port_id port id - * @param[in] enable A_TRUE or A_FALSE - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -isis_port_link_forcemode_set(a_uint32_t dev_id, fal_port_t port_id, a_bool_t enable) -{ - sw_error_t rv; - HSL_API_LOCK; - rv = _isis_port_link_forcemode_set(dev_id, port_id, enable); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Get link force mode on a particular port. - * @param[in] dev_id device id - * @param[in] port_id port id - * @param[out] enable A_TRUE or A_FALSE - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -isis_port_link_forcemode_get(a_uint32_t dev_id, fal_port_t port_id, a_bool_t * enable) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _isis_port_link_forcemode_get(dev_id, port_id, enable); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Get link status on particular port. - * @param[in] dev_id device id - * @param[in] port_id port id - * @param[out] status link status up (A_TRUE) or down (A_FALSE) - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -isis_port_link_status_get(a_uint32_t dev_id, fal_port_t port_id, a_bool_t * status) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _isis_port_link_status_get(dev_id, port_id, status); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Set mac loop back on a particular port. - * @param[in] dev_id device id - * @param[in] port_id port id - * @param[in] enable A_TRUE or A_FALSE - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -isis_port_mac_loopback_set(a_uint32_t dev_id, fal_port_t port_id, a_bool_t enable) -{ - sw_error_t rv; - HSL_API_LOCK; - rv = _isis_port_mac_loopback_set(dev_id, port_id, enable); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Get mac loop back on a particular port. - * @param[in] dev_id device id - * @param[in] port_id port id - * @param[out] enable A_TRUE or A_FALSE - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -isis_port_mac_loopback_get(a_uint32_t dev_id, fal_port_t port_id, a_bool_t * enable) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _isis_port_mac_loopback_get(dev_id, port_id, enable); - HSL_API_UNLOCK; - return rv; -} - -sw_error_t -isis_port_ctrl_init(a_uint32_t dev_id) -{ - HSL_DEV_ID_CHECK(dev_id); - -#ifndef HSL_STANDALONG - { - hsl_api_t *p_api; - - SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id)); - - p_api->port_duplex_get = isis_port_duplex_get; - p_api->port_duplex_set = isis_port_duplex_set; - p_api->port_speed_get = isis_port_speed_get; - p_api->port_speed_set = isis_port_speed_set; - p_api->port_autoneg_status_get = isis_port_autoneg_status_get; - p_api->port_autoneg_enable = isis_port_autoneg_enable; - p_api->port_autoneg_restart = isis_port_autoneg_restart; - p_api->port_autoneg_adv_get = isis_port_autoneg_adv_get; - p_api->port_autoneg_adv_set = isis_port_autoneg_adv_set; - p_api->port_flowctrl_set = isis_port_flowctrl_set; - p_api->port_flowctrl_get = isis_port_flowctrl_get; - p_api->port_flowctrl_forcemode_set = isis_port_flowctrl_forcemode_set; - p_api->port_flowctrl_forcemode_get = isis_port_flowctrl_forcemode_get; - p_api->port_powersave_set = isis_port_powersave_set; - p_api->port_powersave_get = isis_port_powersave_get; - p_api->port_hibernate_set = isis_port_hibernate_set; - p_api->port_hibernate_get = isis_port_hibernate_get; - p_api->port_cdt = isis_port_cdt; - p_api->port_rxhdr_mode_set = isis_port_rxhdr_mode_set; - p_api->port_rxhdr_mode_get = isis_port_rxhdr_mode_get; - p_api->port_txhdr_mode_set = isis_port_txhdr_mode_set; - p_api->port_txhdr_mode_get = isis_port_txhdr_mode_get; - p_api->header_type_set = isis_header_type_set; - p_api->header_type_get = isis_header_type_get; - p_api->port_txmac_status_set = isis_port_txmac_status_set; - p_api->port_txmac_status_get = isis_port_txmac_status_get; - p_api->port_rxmac_status_set = isis_port_rxmac_status_set; - p_api->port_rxmac_status_get = isis_port_rxmac_status_get; - p_api->port_txfc_status_set = isis_port_txfc_status_set; - p_api->port_txfc_status_get = isis_port_txfc_status_get; - p_api->port_rxfc_status_set = isis_port_rxfc_status_set; - p_api->port_rxfc_status_get = isis_port_rxfc_status_get; - p_api->port_bp_status_set = isis_port_bp_status_set; - p_api->port_bp_status_get = isis_port_bp_status_get; - p_api->port_link_forcemode_set = isis_port_link_forcemode_set; - p_api->port_link_forcemode_get = isis_port_link_forcemode_get; - p_api->port_link_status_get = isis_port_link_status_get; - p_api->port_mac_loopback_set = isis_port_mac_loopback_set; - p_api->port_mac_loopback_get = isis_port_mac_loopback_get; - p_api->port_8023az_set = isis_port_8023az_set; - p_api->port_8023az_get = isis_port_8023az_get; - } -#endif - - return SW_OK; -} - -/** - * @} - */ - diff --git a/feeds/ipq807x/qca-ssdk/src/src/hsl/isis/isis_portvlan.c b/feeds/ipq807x/qca-ssdk/src/src/hsl/isis/isis_portvlan.c deleted file mode 100755 index 596bc469e..000000000 --- a/feeds/ipq807x/qca-ssdk/src/src/hsl/isis/isis_portvlan.c +++ /dev/null @@ -1,2130 +0,0 @@ -/* - * Copyright (c) 2012, 2016, The Linux Foundation. All rights reserved. - * Permission to use, copy, modify, and/or distribute this software for - * any purpose with or without fee is hereby granted, provided that the - * above copyright notice and this permission notice appear in all copies. - * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES - * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR - * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES - * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN - * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT - * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. - */ - - -/** - * @defgroup isis_port_vlan ISIS_PORT_VLAN - * @{ - */ -#include "sw.h" -#include "hsl.h" -#include "hsl_dev.h" -#include "hsl_port_prop.h" -#include "isis_portvlan.h" -#include "isis_reg.h" - -#define MAX_VLAN_ID 4095 -#define ISIS_MAX_VLAN_TRANS 64 -#define ISIS_VLAN_TRANS_ADDR 0x5ac00 - - -static sw_error_t -_isis_port_route_defv_set(a_uint32_t dev_id, fal_port_t port_id) -{ - sw_error_t rv; - a_uint32_t data = 0, reg = 0; - - HSL_REG_FIELD_GET(rv, dev_id, PORT_VLAN1, port_id, - COREP_EN, (a_uint8_t *) (&data), sizeof (a_uint32_t)); - - SW_RTN_ON_ERROR(rv); - - if (data) - { - HSL_REG_FIELD_GET(rv, dev_id, PORT_VLAN0, port_id, - DEF_SVID, (a_uint8_t *) (&data), sizeof (a_uint32_t)); - } - else - { - HSL_REG_FIELD_GET(rv, dev_id, PORT_VLAN0, port_id, - DEF_CVID, (a_uint8_t *) (&data), sizeof (a_uint32_t)); - } - - HSL_REG_ENTRY_GET(rv, dev_id, ROUTER_DEFV, (port_id / 2), - (a_uint8_t *) (®), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - - if (port_id % 2) - { - reg &= 0xffff; - reg |= ((data & 0xfff) << 16); - } - else - { - reg &= 0xffff0000; - reg |= (data & 0xfff); - } - - HSL_REG_ENTRY_SET(rv, dev_id, ROUTER_DEFV, (port_id / 2), - (a_uint8_t *) (®), sizeof (a_uint32_t)); - return rv; -} - -static sw_error_t -_isis_port_1qmode_set(a_uint32_t dev_id, fal_port_t port_id, - fal_pt_1qmode_t port_1qmode) -{ - sw_error_t rv; - a_uint32_t data, regval[FAL_1Q_MODE_BUTT] = { 0, 3, 2, 1 }; - - HSL_DEV_ID_CHECK(dev_id); - - if (A_FALSE == hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU)) - { - return SW_BAD_PARAM; - } - - if (FAL_1Q_MODE_BUTT <= port_1qmode) - { - return SW_BAD_PARAM; - } - - HSL_REG_FIELD_SET(rv, dev_id, PORT_LOOKUP_CTL, port_id, DOT1Q_MODE, - (a_uint8_t *) (®val[port_1qmode]), - sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - - if (FAL_1Q_DISABLE == port_1qmode) - { - data = 1; - } - else - { - data = 0; - } - - HSL_REG_FIELD_SET(rv, dev_id, PORT_VLAN1, port_id, VLAN_DIS, - (a_uint8_t *) (&data), sizeof (a_uint32_t)); - return rv; -} - -static sw_error_t -_isis_port_1qmode_get(a_uint32_t dev_id, fal_port_t port_id, - fal_pt_1qmode_t * pport_1qmode) -{ - sw_error_t rv; - a_uint32_t regval = 0; - fal_pt_1qmode_t retval[4] = { FAL_1Q_DISABLE, FAL_1Q_FALLBACK, - FAL_1Q_CHECK, FAL_1Q_SECURE - }; - - HSL_DEV_ID_CHECK(dev_id); - - if (A_FALSE == hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU)) - { - return SW_BAD_PARAM; - } - - SW_RTN_ON_NULL(pport_1qmode); - - HSL_REG_FIELD_GET(rv, dev_id, PORT_LOOKUP_CTL, port_id, DOT1Q_MODE, - (a_uint8_t *) (®val), sizeof (a_uint32_t)); - - SW_RTN_ON_ERROR(rv); - - *pport_1qmode = retval[regval & 0x3]; - - return SW_OK; -} - -static sw_error_t -_isis_port_egvlanmode_set(a_uint32_t dev_id, fal_port_t port_id, - fal_pt_1q_egmode_t port_egvlanmode) -{ - sw_error_t rv; - a_uint32_t data = 0, regval[FAL_EG_MODE_BUTT] = { 0, 1, 2, 3, 3 }; - - HSL_DEV_ID_CHECK(dev_id); - - if (A_FALSE == hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU)) - { - return SW_BAD_PARAM; - } - - if ((FAL_EG_MODE_BUTT <= port_egvlanmode) - || (FAL_EG_HYBRID == port_egvlanmode)) - { - return SW_BAD_PARAM; - } - - HSL_REG_FIELD_SET(rv, dev_id, PORT_VLAN1, port_id, EG_VLAN_MODE, - (a_uint8_t *) (®val[port_egvlanmode]), - sizeof (a_uint32_t)); - - SW_RTN_ON_ERROR(rv); - - HSL_REG_ENTRY_GET(rv, dev_id, ROUTER_EG, 0, - (a_uint8_t *) (&data), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - - data &= (~(0x3 << (port_id << 2))); - data |= (regval[port_egvlanmode] << (port_id << 2)); - - HSL_REG_ENTRY_SET(rv, dev_id, ROUTER_EG, 0, - (a_uint8_t *) (&data), sizeof (a_uint32_t)); - return rv; -} - -static sw_error_t -_isis_port_egvlanmode_get(a_uint32_t dev_id, fal_port_t port_id, - fal_pt_1q_egmode_t * pport_egvlanmode) -{ - sw_error_t rv; - a_uint32_t regval = 0; - fal_pt_1q_egmode_t retval[4] = { FAL_EG_UNMODIFIED, FAL_EG_UNTAGGED, - FAL_EG_TAGGED, FAL_EG_UNTOUCHED - }; - - HSL_DEV_ID_CHECK(dev_id); - - if (A_FALSE == hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU)) - { - return SW_BAD_PARAM; - } - - SW_RTN_ON_NULL(pport_egvlanmode); - - HSL_REG_FIELD_GET(rv, dev_id, PORT_VLAN1, port_id, EG_VLAN_MODE, - (a_uint8_t *) (®val), sizeof (a_uint32_t)); - - SW_RTN_ON_ERROR(rv); - - *pport_egvlanmode = retval[regval & 0x3]; - - return SW_OK; -} - -static sw_error_t -_isis_portvlan_member_add(a_uint32_t dev_id, fal_port_t port_id, - a_uint32_t mem_port_id) -{ - sw_error_t rv; - a_uint32_t regval = 0; - - HSL_DEV_ID_CHECK(dev_id); - - if (A_FALSE == hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU)) - { - return SW_BAD_PARAM; - } - - if (A_FALSE == hsl_port_prop_check(dev_id, mem_port_id, HSL_PP_INCL_CPU)) - { - return SW_BAD_PARAM; - } - - HSL_REG_FIELD_GET(rv, dev_id, PORT_LOOKUP_CTL, port_id, - PORT_VID_MEM, (a_uint8_t *) (®val), - sizeof (a_uint32_t)); - - SW_RTN_ON_ERROR(rv); - - regval |= (0x1UL << mem_port_id); - - HSL_REG_FIELD_SET(rv, dev_id, PORT_LOOKUP_CTL, port_id, - PORT_VID_MEM, (a_uint8_t *) (®val), - sizeof (a_uint32_t)); - - return rv; -} - -static sw_error_t -_isis_portvlan_member_del(a_uint32_t dev_id, fal_port_t port_id, - a_uint32_t mem_port_id) -{ - sw_error_t rv; - a_uint32_t regval = 0; - - HSL_DEV_ID_CHECK(dev_id); - - if (A_FALSE == hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU)) - { - return SW_BAD_PARAM; - } - - if (A_FALSE == hsl_port_prop_check(dev_id, mem_port_id, HSL_PP_INCL_CPU)) - { - return SW_BAD_PARAM; - } - - HSL_REG_FIELD_GET(rv, dev_id, PORT_LOOKUP_CTL, port_id, - PORT_VID_MEM, (a_uint8_t *) (®val), - sizeof (a_uint32_t)); - - SW_RTN_ON_ERROR(rv); - - regval &= (~(0x1UL << mem_port_id)); - - HSL_REG_FIELD_SET(rv, dev_id, PORT_LOOKUP_CTL, port_id, - PORT_VID_MEM, (a_uint8_t *) (®val), - sizeof (a_uint32_t)); - - return rv; -} - -static sw_error_t -_isis_portvlan_member_update(a_uint32_t dev_id, fal_port_t port_id, - fal_pbmp_t mem_port_map) -{ - sw_error_t rv; - - HSL_DEV_ID_CHECK(dev_id); - - if (A_FALSE == hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU)) - { - return SW_BAD_PARAM; - } - - if (A_FALSE == hsl_mports_prop_check(dev_id, mem_port_map, HSL_PP_INCL_CPU)) - { - return SW_BAD_PARAM; - } - - HSL_REG_FIELD_SET(rv, dev_id, PORT_LOOKUP_CTL, port_id, - PORT_VID_MEM, (a_uint8_t *) (&mem_port_map), - sizeof (a_uint32_t)); - - return rv; -} - -static sw_error_t -_isis_portvlan_member_get(a_uint32_t dev_id, fal_port_t port_id, - fal_pbmp_t * mem_port_map) -{ - sw_error_t rv; - - HSL_DEV_ID_CHECK(dev_id); - - if (A_FALSE == hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU)) - { - return SW_BAD_PARAM; - } - - *mem_port_map = 0; - HSL_REG_FIELD_GET(rv, dev_id, PORT_LOOKUP_CTL, port_id, - PORT_VID_MEM, (a_uint8_t *) mem_port_map, - sizeof (a_uint32_t)); - - SW_RTN_ON_ERROR(rv); - - return SW_OK; -} - -static sw_error_t -_isis_port_force_default_vid_set(a_uint32_t dev_id, fal_port_t port_id, - a_bool_t enable) -{ - sw_error_t rv; - a_uint32_t val; - - HSL_DEV_ID_CHECK(dev_id); - - if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU)) - { - return SW_BAD_PARAM; - } - - if (A_TRUE == enable) - { - val = 1; - } - else if (A_FALSE == enable) - { - val = 0; - } - else - { - return SW_BAD_PARAM; - } - - HSL_REG_FIELD_SET(rv, dev_id, PORT_VLAN1, port_id, - FORCE_DEF_VID, (a_uint8_t *) (&val), sizeof (a_uint32_t)); - return rv; -} - -static sw_error_t -_isis_port_force_default_vid_get(a_uint32_t dev_id, fal_port_t port_id, - a_bool_t * enable) -{ - sw_error_t rv; - a_uint32_t val = 0; - - HSL_DEV_ID_CHECK(dev_id); - - if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU)) - { - return SW_BAD_PARAM; - } - - HSL_REG_FIELD_GET(rv, dev_id, PORT_VLAN1, port_id, - FORCE_DEF_VID, (a_uint8_t *) (&val), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - - if (val) - { - *enable = A_TRUE; - } - else - { - *enable = A_FALSE; - } - - return SW_OK; -} - -static sw_error_t -_isis_port_force_portvlan_set(a_uint32_t dev_id, fal_port_t port_id, - a_bool_t enable) -{ - sw_error_t rv; - a_uint32_t val; - - HSL_DEV_ID_CHECK(dev_id); - - if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU)) - { - return SW_BAD_PARAM; - } - - if (A_TRUE == enable) - { - val = 1; - } - else if (A_FALSE == enable) - { - val = 0; - } - else - { - return SW_BAD_PARAM; - } - - HSL_REG_FIELD_SET(rv, dev_id, PORT_LOOKUP_CTL, port_id, - FORCE_PVLAN, (a_uint8_t *) (&val), sizeof (a_uint32_t)); - return rv; -} - -static sw_error_t -_isis_port_force_portvlan_get(a_uint32_t dev_id, fal_port_t port_id, - a_bool_t * enable) -{ - sw_error_t rv; - a_uint32_t val = 0; - - HSL_DEV_ID_CHECK(dev_id); - - if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU)) - { - return SW_BAD_PARAM; - } - - HSL_REG_FIELD_GET(rv, dev_id, PORT_LOOKUP_CTL, port_id, - FORCE_PVLAN, (a_uint8_t *) (&val), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - - if (val) - { - *enable = A_TRUE; - } - else - { - *enable = A_FALSE; - } - - return SW_OK; -} - -static sw_error_t -_isis_nestvlan_tpid_set(a_uint32_t dev_id, a_uint32_t tpid) -{ - sw_error_t rv; - a_uint32_t val; - - HSL_DEV_ID_CHECK(dev_id); - - val = tpid; - HSL_REG_FIELD_SET(rv, dev_id, SERVICE_TAG, 0, - TAG_VALUE, (a_uint8_t *) (&val), sizeof (a_uint32_t)); - return rv; -} - -static sw_error_t -_isis_nestvlan_tpid_get(a_uint32_t dev_id, a_uint32_t * tpid) -{ - sw_error_t rv; - a_uint32_t val = 0; - - HSL_DEV_ID_CHECK(dev_id); - - HSL_REG_FIELD_GET(rv, dev_id, SERVICE_TAG, 0, - TAG_VALUE, (a_uint8_t *) (&val), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - - *tpid = val; - return SW_OK; -} - -static sw_error_t -_isis_port_invlan_mode_set(a_uint32_t dev_id, fal_port_t port_id, - fal_pt_invlan_mode_t mode) -{ - sw_error_t rv; - a_uint32_t regval[FAL_INVLAN_MODE_BUTT] = { 0, 1, 2 }; - - HSL_DEV_ID_CHECK(dev_id); - - if (A_FALSE == hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU)) - { - return SW_BAD_PARAM; - } - - if (FAL_INVLAN_MODE_BUTT <= mode) - { - return SW_BAD_PARAM; - } - - HSL_REG_FIELD_SET(rv, dev_id, PORT_VLAN1, port_id, IN_VLAN_MODE, - (a_uint8_t *) (®val[mode]), sizeof (a_uint32_t)); - return rv; -} - -static sw_error_t -_isis_port_invlan_mode_get(a_uint32_t dev_id, fal_port_t port_id, - fal_pt_invlan_mode_t * mode) -{ - sw_error_t rv; - a_uint32_t regval = 0; - fal_pt_invlan_mode_t retval[FAL_INVLAN_MODE_BUTT] = { FAL_INVLAN_ADMIT_ALL, - FAL_INVLAN_ADMIT_TAGGED, FAL_INVLAN_ADMIT_UNTAGGED - }; - - HSL_DEV_ID_CHECK(dev_id); - - if (A_FALSE == hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU)) - { - return SW_BAD_PARAM; - } - - SW_RTN_ON_NULL(mode); - - HSL_REG_FIELD_GET(rv, dev_id, PORT_VLAN1, port_id, IN_VLAN_MODE, - (a_uint8_t *) (®val), sizeof (a_uint32_t)); - - SW_RTN_ON_ERROR(rv); - - if (regval >= 3) - { - return SW_FAIL; - } - *mode = retval[regval & 0x3]; - - return rv; -} - -static sw_error_t -_isis_port_tls_set(a_uint32_t dev_id, fal_port_t port_id, a_bool_t enable) -{ - sw_error_t rv; - a_uint32_t val; - - HSL_DEV_ID_CHECK(dev_id); - - if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU)) - { - return SW_BAD_PARAM; - } - - if (A_TRUE == enable) - { - val = 1; - } - else if (A_FALSE == enable) - { - val = 0; - } - else - { - return SW_BAD_PARAM; - } - - HSL_REG_FIELD_SET(rv, dev_id, PORT_VLAN1, port_id, - TLS_EN, (a_uint8_t *) (&val), sizeof (a_uint32_t)); - return rv; -} - -static sw_error_t -_isis_port_tls_get(a_uint32_t dev_id, fal_port_t port_id, a_bool_t * enable) -{ - sw_error_t rv; - a_uint32_t val = 0; - - HSL_DEV_ID_CHECK(dev_id); - - if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU)) - { - return SW_BAD_PARAM; - } - - HSL_REG_FIELD_GET(rv, dev_id, PORT_VLAN1, port_id, - TLS_EN, (a_uint8_t *) (&val), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - - if (1 == val) - { - *enable = A_TRUE; - } - else - { - *enable = A_FALSE; - } - - return SW_OK; -} - -static sw_error_t -_isis_port_pri_propagation_set(a_uint32_t dev_id, fal_port_t port_id, - a_bool_t enable) -{ - sw_error_t rv; - a_uint32_t val; - - HSL_DEV_ID_CHECK(dev_id); - - if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU)) - { - return SW_BAD_PARAM; - } - - if (A_TRUE == enable) - { - val = 1; - } - else if (A_FALSE == enable) - { - val = 0; - } - else - { - return SW_BAD_PARAM; - } - - HSL_REG_FIELD_SET(rv, dev_id, PORT_VLAN1, port_id, - PRI_PROPAGATION, (a_uint8_t *) (&val), - sizeof (a_uint32_t)); - return rv; -} - -static sw_error_t -_isis_port_pri_propagation_get(a_uint32_t dev_id, fal_port_t port_id, - a_bool_t * enable) -{ - sw_error_t rv; - a_uint32_t val = 0; - - HSL_DEV_ID_CHECK(dev_id); - - if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU)) - { - return SW_BAD_PARAM; - } - - HSL_REG_FIELD_GET(rv, dev_id, PORT_VLAN1, port_id, - PRI_PROPAGATION, (a_uint8_t *) (&val), - sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - - if (1 == val) - { - *enable = A_TRUE; - } - else - { - *enable = A_FALSE; - } - - return SW_OK; -} - -static sw_error_t -_isis_port_default_svid_set(a_uint32_t dev_id, fal_port_t port_id, - a_uint32_t vid) -{ - sw_error_t rv; - a_uint32_t val; - - HSL_DEV_ID_CHECK(dev_id); - - if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU)) - { - return SW_BAD_PARAM; - } - - if (vid > MAX_VLAN_ID) - { - return SW_BAD_PARAM; - } - - val = vid; - HSL_REG_FIELD_SET(rv, dev_id, PORT_VLAN0, port_id, - DEF_SVID, (a_uint8_t *) (&val), sizeof (a_uint32_t)); - - SW_RTN_ON_ERROR(rv); - - rv = _isis_port_route_defv_set(dev_id, port_id); - return rv; -} - -static sw_error_t -_isis_port_default_svid_get(a_uint32_t dev_id, fal_port_t port_id, - a_uint32_t * vid) -{ - sw_error_t rv; - a_uint32_t val = 0; - - HSL_DEV_ID_CHECK(dev_id); - - if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU)) - { - return SW_BAD_PARAM; - } - - HSL_REG_FIELD_GET(rv, dev_id, PORT_VLAN0, port_id, - DEF_SVID, (a_uint8_t *) (&val), sizeof (a_uint32_t)); - - *vid = val & 0xfff; - return rv; -} - -static sw_error_t -_isis_port_default_cvid_set(a_uint32_t dev_id, fal_port_t port_id, - a_uint32_t vid) -{ - sw_error_t rv; - a_uint32_t val; - - HSL_DEV_ID_CHECK(dev_id); - - if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU)) - { - return SW_BAD_PARAM; - } - - if (vid > MAX_VLAN_ID) - { - return SW_BAD_PARAM; - } - - val = vid; - HSL_REG_FIELD_SET(rv, dev_id, PORT_VLAN0, port_id, - DEF_CVID, (a_uint8_t *) (&val), sizeof (a_uint32_t)); - - SW_RTN_ON_ERROR(rv); - - rv = _isis_port_route_defv_set(dev_id, port_id); - return rv; -} - -static sw_error_t -_isis_port_default_cvid_get(a_uint32_t dev_id, fal_port_t port_id, - a_uint32_t * vid) -{ - sw_error_t rv; - a_uint32_t val = 0; - - HSL_DEV_ID_CHECK(dev_id); - - if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU)) - { - return SW_BAD_PARAM; - } - - HSL_REG_FIELD_GET(rv, dev_id, PORT_VLAN0, port_id, - DEF_CVID, (a_uint8_t *) (&val), sizeof (a_uint32_t)); - - *vid = val & 0xfff; - return rv; -} - -static sw_error_t -_isis_port_vlan_propagation_set(a_uint32_t dev_id, fal_port_t port_id, - fal_vlan_propagation_mode_t mode) -{ - sw_error_t rv; - a_uint32_t reg = 0, p, c; - - HSL_DEV_ID_CHECK(dev_id); - - if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU)) - { - return SW_BAD_PARAM; - } - - if (FAL_VLAN_PROPAGATION_DISABLE == mode) - { - p = 0; - c = 0; - } - else if (FAL_VLAN_PROPAGATION_CLONE == mode) - { - p = 1; - c = 1; - } - else if (FAL_VLAN_PROPAGATION_REPLACE == mode) - { - p = 1; - c = 0; - } - else - { - return SW_BAD_PARAM; - } - - HSL_REG_ENTRY_GET(rv, dev_id, PORT_VLAN1, port_id, - (a_uint8_t *) (®), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - - SW_SET_REG_BY_FIELD(PORT_VLAN1, PROPAGATION_EN, p, reg); - SW_SET_REG_BY_FIELD(PORT_VLAN1, CLONE, c, reg); - - HSL_REG_ENTRY_SET(rv, dev_id, PORT_VLAN1, port_id, - (a_uint8_t *) (®), sizeof (a_uint32_t)); - return rv; -} - -static sw_error_t -_isis_port_vlan_propagation_get(a_uint32_t dev_id, fal_port_t port_id, - fal_vlan_propagation_mode_t * mode) -{ - sw_error_t rv; - a_uint32_t reg = 0, p, c; - - HSL_DEV_ID_CHECK(dev_id); - - if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU)) - { - return SW_BAD_PARAM; - } - - HSL_REG_ENTRY_GET(rv, dev_id, PORT_VLAN1, port_id, - (a_uint8_t *) (®), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - - SW_GET_FIELD_BY_REG(PORT_VLAN1, PROPAGATION_EN, p, reg); - SW_GET_FIELD_BY_REG(PORT_VLAN1, CLONE, c, reg); - - if (p) - { - if (c) - { - *mode = FAL_VLAN_PROPAGATION_CLONE; - } - else - { - *mode = FAL_VLAN_PROPAGATION_REPLACE; - } - } - else - { - *mode = FAL_VLAN_PROPAGATION_DISABLE; - } - - return SW_OK; -} - -static sw_error_t -_isis_vlan_trans_read(a_uint32_t dev_id, a_uint32_t entry_idx, - fal_pbmp_t * pbmp, fal_vlan_trans_entry_t * entry) -{ - sw_error_t rv; - a_uint32_t i, addr, dir, table[2] = {0}; - - *pbmp = 0; - aos_mem_zero(entry, sizeof (fal_vlan_trans_entry_t)); - - addr = ISIS_VLAN_TRANS_ADDR + (entry_idx << 3); - /* get vlan trans table */ - for (i = 0; i < 2; i++) - { - HSL_REG_ENTRY_GEN_GET(rv, dev_id, addr + (i << 2), sizeof (a_uint32_t), - (a_uint8_t *) (&(table[i])), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - } - - dir = 0x3 & (table[1] >> 4); - if (!dir) - { - return SW_EMPTY; - } - - entry->o_vid = table[0] & 0xfff; - *pbmp = (table[1] >> 6) & 0x7f; - - if (3 == dir) - { - entry->bi_dir = A_TRUE; - entry->forward_dir = A_TRUE; - entry->reverse_dir = A_TRUE; - } - else if (1 == dir) - { - entry->bi_dir = A_FALSE; - entry->forward_dir = A_TRUE; - entry->reverse_dir = A_FALSE; - } - else - { - entry->bi_dir = A_FALSE; - entry->forward_dir = A_FALSE; - entry->reverse_dir = A_TRUE; - } - - entry->o_vid_is_cvid = (table[1] >> 13) & 0x1UL; - entry->one_2_one_vlan = (table[1] >> 16) & 0x1UL; - entry->s_vid_enable = (table[1] >> 14) & 0x1UL; - entry->c_vid_enable = (table[1] >> 15) & 0x1UL; - - if (A_TRUE == entry->s_vid_enable) - { - entry->s_vid = (table[0] >> 12) & 0xfff; - } - - if (A_TRUE == entry->c_vid_enable) - { - entry->c_vid = ((table[0] >> 24) & 0xff) | ((table[1] & 0xf) << 8); - } - - return SW_OK; -} - -static sw_error_t -_isis_vlan_trans_write(a_uint32_t dev_id, a_uint32_t entry_idx, fal_pbmp_t pbmp, - fal_vlan_trans_entry_t entry) -{ - sw_error_t rv; - a_uint32_t i, addr, table[2] = { 0 }; - - addr = ISIS_VLAN_TRANS_ADDR + (entry_idx << 3); - - if (0 != pbmp) - { - table[0] = entry.o_vid & 0xfff; - table[0] |= ((entry.s_vid & 0xfff) << 12); - table[0] |= ((entry.c_vid & 0xff) << 24); - table[1] = (entry.c_vid >> 8) & 0xf; - - if (A_TRUE == entry.bi_dir) - { - table[1] |= (0x3 << 4); - } - - if (A_TRUE == entry.forward_dir) - { - table[1] |= (0x1 << 4); - } - - if (A_TRUE == entry.reverse_dir) - { - table[1] |= (0x1 << 5); - } - - table[1] |= (pbmp << 6); - table[1] |= ((0x1UL & entry.o_vid_is_cvid) << 13); - table[1] |= ((0x1UL & entry.s_vid_enable) << 14); - table[1] |= ((0x1UL & entry.c_vid_enable) << 15); - table[1] |= ((0x1UL & entry.one_2_one_vlan) << 16); - } - - /* set vlan trans table */ - for (i = 0; i < 2; i++) - { - HSL_REG_ENTRY_GEN_SET(rv, dev_id, addr + (i << 2), sizeof (a_uint32_t), - (a_uint8_t *) (&(table[i])), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - } - - return SW_OK; -} - -static sw_error_t -_isis_port_vlan_trans_convert(fal_vlan_trans_entry_t * entry, - fal_vlan_trans_entry_t * local) -{ - aos_mem_copy(local, entry, sizeof (fal_vlan_trans_entry_t)); - - if ((A_TRUE == local->bi_dir) - || ((A_TRUE == local->forward_dir) - && (A_TRUE == local->reverse_dir))) - { - local->bi_dir = A_TRUE; - local->forward_dir = A_TRUE; - local->reverse_dir = A_TRUE; - } - - if (A_FALSE == local->s_vid_enable) - { - local->s_vid = 0; - } - - if (A_FALSE == local->c_vid_enable) - { - local->c_vid = 0; - } - - return SW_OK; -} - -static sw_error_t -_isis_port_vlan_trans_add(a_uint32_t dev_id, fal_port_t port_id, - fal_vlan_trans_entry_t * entry) -{ - sw_error_t rv; - fal_pbmp_t t_pbmp; - a_uint32_t idx, entry_idx = ISIS_MAX_VLAN_TRANS; - fal_vlan_trans_entry_t temp, local; - - HSL_DEV_ID_CHECK(dev_id); - - if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU)) - { - return SW_BAD_PARAM; - } - - if (NULL == entry) - { - return SW_BAD_PTR; - } - aos_mem_zero(&local, sizeof(fal_vlan_trans_entry_t)); - rv = _isis_port_vlan_trans_convert(entry, &local); - SW_RTN_ON_ERROR(rv); - - for (idx = 0; idx < ISIS_MAX_VLAN_TRANS; idx++) - { - rv = _isis_vlan_trans_read(dev_id, idx, &t_pbmp, &temp); - if (SW_EMPTY == rv) - { - entry_idx = idx; - continue; - } - SW_RTN_ON_ERROR(rv); - - if (!aos_mem_cmp(&local, &temp, sizeof (fal_vlan_trans_entry_t))) - { - if (SW_IS_PBMP_MEMBER(t_pbmp, port_id)) - { - return SW_ALREADY_EXIST; - } - entry_idx = idx; - break; - } - else - { - t_pbmp = 0; - } - } - - if (ISIS_MAX_VLAN_TRANS != entry_idx) - { - t_pbmp |= (0x1 << port_id); - } - else - { - return SW_NO_RESOURCE; - } - - return _isis_vlan_trans_write(dev_id, entry_idx, t_pbmp, local); -} - -static sw_error_t -_isis_port_vlan_trans_del(a_uint32_t dev_id, fal_port_t port_id, - fal_vlan_trans_entry_t * entry) -{ - sw_error_t rv; - fal_pbmp_t t_pbmp; - a_uint32_t idx, entry_idx = ISIS_MAX_VLAN_TRANS; - fal_vlan_trans_entry_t temp, local; - - HSL_DEV_ID_CHECK(dev_id); - - if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU)) - { - return SW_BAD_PARAM; - } - - if (NULL == entry) - { - return SW_BAD_PTR; - } - aos_mem_zero(&local, sizeof(fal_vlan_trans_entry_t)); - rv = _isis_port_vlan_trans_convert(entry, &local); - SW_RTN_ON_ERROR(rv); - - for (idx = 0; idx < ISIS_MAX_VLAN_TRANS; idx++) - { - rv = _isis_vlan_trans_read(dev_id, idx, &t_pbmp, &temp); - if (SW_EMPTY == rv) - { - continue; - } - SW_RTN_ON_ERROR(rv); - - if (!aos_mem_cmp(&temp, &local, sizeof (fal_vlan_trans_entry_t))) - { - if (SW_IS_PBMP_MEMBER(t_pbmp, port_id)) - { - entry_idx = idx; - break; - } - } - } - - if (ISIS_MAX_VLAN_TRANS != entry_idx) - { - t_pbmp &= (~(0x1 << port_id)); - } - else - { - return SW_NOT_FOUND; - } - - return _isis_vlan_trans_write(dev_id, entry_idx, t_pbmp, local); -} - -static sw_error_t -_isis_port_vlan_trans_get(a_uint32_t dev_id, fal_port_t port_id, - fal_vlan_trans_entry_t * entry) -{ - sw_error_t rv; - fal_pbmp_t t_pbmp; - a_uint32_t idx; - fal_vlan_trans_entry_t temp, local; - - HSL_DEV_ID_CHECK(dev_id); - - if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU)) - { - return SW_BAD_PARAM; - } - - if (NULL == entry) - { - return SW_BAD_PTR; - } - aos_mem_zero(&local, sizeof(fal_vlan_trans_entry_t)); - rv = _isis_port_vlan_trans_convert(entry, &local); - SW_RTN_ON_ERROR(rv); - - for (idx = 0; idx < ISIS_MAX_VLAN_TRANS; idx++) - { - rv = _isis_vlan_trans_read(dev_id, idx, &t_pbmp, &temp); - if (SW_EMPTY == rv) - { - continue; - } - SW_RTN_ON_ERROR(rv); - - if (!aos_mem_cmp(&temp, &local, sizeof (fal_vlan_trans_entry_t))) - { - if (SW_IS_PBMP_MEMBER(t_pbmp, port_id)) - { - return SW_OK; - } - } - } - - return SW_NOT_FOUND; -} - -static sw_error_t -_isis_port_vlan_trans_iterate(a_uint32_t dev_id, fal_port_t port_id, - a_uint32_t * iterator, - fal_vlan_trans_entry_t * entry) -{ - a_uint32_t index; - sw_error_t rv; - fal_vlan_trans_entry_t entry_t; - fal_pbmp_t pbmp_t; - - HSL_DEV_ID_CHECK(dev_id); - - if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU)) - { - return SW_BAD_PARAM; - } - - if ((NULL == iterator) || (NULL == entry)) - { - return SW_BAD_PTR; - } - - if (ISIS_MAX_VLAN_TRANS < *iterator) - { - return SW_BAD_PARAM; - } - - for (index = *iterator; index < ISIS_MAX_VLAN_TRANS; index++) - { - rv = _isis_vlan_trans_read(dev_id, index, &pbmp_t, &entry_t); - if (SW_EMPTY == rv) - { - continue; - } - - if (SW_IS_PBMP_MEMBER(pbmp_t, port_id)) - { - aos_mem_copy(entry, &entry_t, sizeof (fal_vlan_trans_entry_t)); - break; - } - } - - if (ISIS_MAX_VLAN_TRANS == index) - { - return SW_NO_MORE; - } - - *iterator = index + 1; - return SW_OK; -} - -static sw_error_t -_isis_qinq_mode_set(a_uint32_t dev_id, fal_qinq_mode_t mode) -{ - sw_error_t rv; - a_uint32_t stag = 0; - - HSL_DEV_ID_CHECK(dev_id); - - if (FAL_QINQ_MODE_BUTT <= mode) - { - return SW_BAD_PARAM; - } - - if (FAL_QINQ_STAG_MODE == mode) - { - stag = 1; - } - - HSL_REG_FIELD_SET(rv, dev_id, SERVICE_TAG, 0, - STAG_MODE, (a_uint8_t *) (&stag), sizeof (a_uint32_t)); - - return rv; -} - -static sw_error_t -_isis_qinq_mode_get(a_uint32_t dev_id, fal_qinq_mode_t * mode) -{ - sw_error_t rv; - a_uint32_t stag = 0; - - HSL_DEV_ID_CHECK(dev_id); - - HSL_REG_FIELD_GET(rv, dev_id, SERVICE_TAG, 0, - STAG_MODE, (a_uint8_t *) (&stag), sizeof (a_uint32_t)); - - SW_RTN_ON_ERROR(rv); - - if (stag) - { - *mode = FAL_QINQ_STAG_MODE; - } - else - { - *mode = FAL_QINQ_CTAG_MODE; - } - - return SW_OK; -} - -static sw_error_t -_isis_port_qinq_role_set(a_uint32_t dev_id, fal_port_t port_id, - fal_qinq_port_role_t role) -{ - sw_error_t rv; - a_uint32_t core = 0; - - HSL_DEV_ID_CHECK(dev_id); - - if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU)) - { - return SW_BAD_PARAM; - } - - if (FAL_QINQ_PORT_ROLE_BUTT <= role) - { - return SW_BAD_PARAM; - } - - if (FAL_QINQ_CORE_PORT == role) - { - core = 1; - } - - HSL_REG_FIELD_SET(rv, dev_id, PORT_VLAN1, port_id, - COREP_EN, (a_uint8_t *) (&core), sizeof (a_uint32_t)); - - SW_RTN_ON_ERROR(rv); - - rv = _isis_port_route_defv_set(dev_id, port_id); - return rv; -} - -static sw_error_t -_isis_port_qinq_role_get(a_uint32_t dev_id, fal_port_t port_id, - fal_qinq_port_role_t * role) -{ - sw_error_t rv; - a_uint32_t core = 0; - - HSL_DEV_ID_CHECK(dev_id); - - if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU)) - { - return SW_BAD_PARAM; - } - - HSL_REG_FIELD_GET(rv, dev_id, PORT_VLAN1, port_id, - COREP_EN, (a_uint8_t *) (&core), sizeof (a_uint32_t)); - - SW_RTN_ON_ERROR(rv); - - if (core) - { - *role = FAL_QINQ_CORE_PORT; - } - else - { - *role = FAL_QINQ_EDGE_PORT; - } - - return SW_OK; -} - -static sw_error_t -_isis_port_mac_vlan_xlt_set(a_uint32_t dev_id, fal_port_t port_id, - a_bool_t enable) -{ - sw_error_t rv; - a_uint32_t val; - - HSL_DEV_ID_CHECK(dev_id); - - if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU)) - { - return SW_BAD_PARAM; - } - - if (A_TRUE == enable) - { - val = 1; - } - else if (A_FALSE == enable) - { - val = 0; - } - else - { - return SW_BAD_PARAM; - } - - HSL_REG_FIELD_SET(rv, dev_id, PRI_CTL, port_id, - EG_MAC_BASE_VLAN_EN, (a_uint8_t *) (&val), sizeof (a_uint32_t)); - return rv; - -} - -static sw_error_t -_isis_port_mac_vlan_xlt_get(a_uint32_t dev_id, fal_port_t port_id, - a_bool_t * enable) -{ - sw_error_t rv; - a_uint32_t val = 0; - - HSL_DEV_ID_CHECK(dev_id); - - if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU)) - { - return SW_BAD_PARAM; - } - - HSL_REG_FIELD_GET(rv, dev_id, PRI_CTL, port_id, - EG_MAC_BASE_VLAN_EN, (a_uint8_t *) (&val), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - - if (1 == val) - { - *enable = A_TRUE; - } - else - { - *enable = A_FALSE; - } - - return SW_OK; -} - -/** - * @brief Set 802.1q work mode on a particular port. - * @param[in] dev_id device id - * @param[in] port_id port id - * @param[in] port_1qmode 802.1q work mode - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -isis_port_1qmode_set(a_uint32_t dev_id, fal_port_t port_id, - fal_pt_1qmode_t port_1qmode) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _isis_port_1qmode_set(dev_id, port_id, port_1qmode); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Get 802.1q work mode on a particular port. - * @param[in] dev_id device id - * @param[in] port_id port id - * @param[out] port_1qmode 802.1q work mode - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -isis_port_1qmode_get(a_uint32_t dev_id, fal_port_t port_id, - fal_pt_1qmode_t * pport_1qmode) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _isis_port_1qmode_get(dev_id, port_id, pport_1qmode); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Set packets transmitted out vlan tagged mode on a particular port. - * @param[in] dev_id device id - * @param[in] port_id port id - * @param[in] port_egvlanmode packets transmitted out vlan tagged mode - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -isis_port_egvlanmode_set(a_uint32_t dev_id, fal_port_t port_id, - fal_pt_1q_egmode_t port_egvlanmode) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _isis_port_egvlanmode_set(dev_id, port_id, port_egvlanmode); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Get packets transmitted out vlan tagged mode on a particular port. - * @param[in] dev_id device id - * @param[in] port_id port id - * @param[out] port_egvlanmode packets transmitted out vlan tagged mode - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -isis_port_egvlanmode_get(a_uint32_t dev_id, fal_port_t port_id, - fal_pt_1q_egmode_t * pport_egvlanmode) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _isis_port_egvlanmode_get(dev_id, port_id, pport_egvlanmode); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Add member of port based vlan on a particular port. - * @param[in] dev_id device id - * @param[in] port_id port id - * @param[in] mem_port_id port member - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -isis_portvlan_member_add(a_uint32_t dev_id, fal_port_t port_id, - a_uint32_t mem_port_id) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _isis_portvlan_member_add(dev_id, port_id, mem_port_id); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Delete member of port based vlan on a particular port. - * @param[in] dev_id device id - * @param[in] port_id port id - * @param[in] mem_port_id port member - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -isis_portvlan_member_del(a_uint32_t dev_id, fal_port_t port_id, - a_uint32_t mem_port_id) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _isis_portvlan_member_del(dev_id, port_id, mem_port_id); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Update member of port based vlan on a particular port. - * @param[in] dev_id device id - * @param[in] port_id port id - * @param[in] mem_port_map port members - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -isis_portvlan_member_update(a_uint32_t dev_id, fal_port_t port_id, - fal_pbmp_t mem_port_map) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _isis_portvlan_member_update(dev_id, port_id, mem_port_map); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Get member of port based vlan on a particular port. - * @param[in] dev_id device id - * @param[in] port_id port id - * @param[out] mem_port_map port members - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -isis_portvlan_member_get(a_uint32_t dev_id, fal_port_t port_id, - fal_pbmp_t * mem_port_map) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _isis_portvlan_member_get(dev_id, port_id, mem_port_map); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Set force default vlan id status on a particular port. - * @param[in] dev_id device id - * @param[in] port_id port id - * @param[in] enable A_TRUE or A_FALSE - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -isis_port_force_default_vid_set(a_uint32_t dev_id, fal_port_t port_id, - a_bool_t enable) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _isis_port_force_default_vid_set(dev_id, port_id, enable); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Get force default vlan id status on a particular port. - * @param[in] dev_id device id - * @param[in] port_id port id - * @param[out] enable A_TRUE or A_FALSE - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -isis_port_force_default_vid_get(a_uint32_t dev_id, fal_port_t port_id, - a_bool_t * enable) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _isis_port_force_default_vid_get(dev_id, port_id, enable); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Set force port based vlan status on a particular port. - * @param[in] dev_id device id - * @param[in] port_id port id - * @param[in] enable A_TRUE or A_FALSE - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -isis_port_force_portvlan_set(a_uint32_t dev_id, fal_port_t port_id, - a_bool_t enable) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _isis_port_force_portvlan_set(dev_id, port_id, enable); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Get force port based vlan status on a particular port. - * @param[in] dev_id device id - * @param[in] port_id port id - * @param[out] enable A_TRUE or A_FALSE - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -isis_port_force_portvlan_get(a_uint32_t dev_id, fal_port_t port_id, - a_bool_t * enable) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _isis_port_force_portvlan_get(dev_id, port_id, enable); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Set nest vlan tpid on a particular device. - * @param[in] dev_id device id - * @param[in] tpid tag protocol identification - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -isis_nestvlan_tpid_set(a_uint32_t dev_id, a_uint32_t tpid) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _isis_nestvlan_tpid_set(dev_id, tpid); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Get nest vlan tpid on a particular device. - * @param[in] dev_id device id - * @param[out] tpid tag protocol identification - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -isis_nestvlan_tpid_get(a_uint32_t dev_id, a_uint32_t * tpid) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _isis_nestvlan_tpid_get(dev_id, tpid); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Set ingress vlan mode mode on a particular port. - * @param[in] dev_id device id - * @param[in] port_id port id - * @param[in] mode ingress vlan mode - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -isis_port_invlan_mode_set(a_uint32_t dev_id, fal_port_t port_id, - fal_pt_invlan_mode_t mode) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _isis_port_invlan_mode_set(dev_id, port_id, mode); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Get ingress vlan mode mode on a particular port. - * @param[in] dev_id device id - * @param[in] port_id port id - * @param[out] mode ingress vlan mode - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -isis_port_invlan_mode_get(a_uint32_t dev_id, fal_port_t port_id, - fal_pt_invlan_mode_t * mode) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _isis_port_invlan_mode_get(dev_id, port_id, mode); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Set tls status on a particular port. - * @param[in] dev_id device id - * @param[in] port_id port id - * @param[in] enable A_TRUE or A_FALSE - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -isis_port_tls_set(a_uint32_t dev_id, fal_port_t port_id, a_bool_t enable) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _isis_port_tls_set(dev_id, port_id, enable); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Get tls status on a particular port. - * @param[in] dev_id device id - * @param[in] port_id port id - * @param[out] enable A_TRUE or A_FALSE - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -isis_port_tls_get(a_uint32_t dev_id, fal_port_t port_id, a_bool_t * enable) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _isis_port_tls_get(dev_id, port_id, enable); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Set priority propagation status on a particular port. - * @param[in] dev_id device id - * @param[in] port_id port id - * @param[in] enable A_TRUE or A_FALSE - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -isis_port_pri_propagation_set(a_uint32_t dev_id, fal_port_t port_id, - a_bool_t enable) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _isis_port_pri_propagation_set(dev_id, port_id, enable); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Get priority propagation status on a particular port. - * @param[in] dev_id device id - * @param[in] port_id port id - * @param[out] enable A_TRUE or A_FALSE - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -isis_port_pri_propagation_get(a_uint32_t dev_id, fal_port_t port_id, - a_bool_t * enable) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _isis_port_pri_propagation_get(dev_id, port_id, enable); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Set default s-vid on a particular port. - * @param[in] dev_id device id - * @param[in] port_id port id - * @param[in] vid s-vid - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -isis_port_default_svid_set(a_uint32_t dev_id, fal_port_t port_id, - a_uint32_t vid) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _isis_port_default_svid_set(dev_id, port_id, vid); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Get default s-vid on a particular port. - * @param[in] dev_id device id - * @param[in] port_id port id - * @param[out] vid s-vid - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -isis_port_default_svid_get(a_uint32_t dev_id, fal_port_t port_id, - a_uint32_t * vid) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _isis_port_default_svid_get(dev_id, port_id, vid); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Set default c-vid on a particular port. - * @param[in] dev_id device id - * @param[in] port_id port id - * @param[in] vid c-vid - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -isis_port_default_cvid_set(a_uint32_t dev_id, fal_port_t port_id, - a_uint32_t vid) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _isis_port_default_cvid_set(dev_id, port_id, vid); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Get default c-vid on a particular port. - * @param[in] dev_id device id - * @param[in] port_id port id - * @param[out] vid c-vid - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -isis_port_default_cvid_get(a_uint32_t dev_id, fal_port_t port_id, - a_uint32_t * vid) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _isis_port_default_cvid_get(dev_id, port_id, vid); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Set vlan propagation status on a particular port. - * @param[in] dev_id device id - * @param[in] port_id port id - * @param[in] mode vlan propagation mode - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -isis_port_vlan_propagation_set(a_uint32_t dev_id, fal_port_t port_id, - fal_vlan_propagation_mode_t mode) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _isis_port_vlan_propagation_set(dev_id, port_id, mode); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Get vlan propagation status on a particular port. - * @param[in] dev_id device id - * @param[in] port_id port id - * @param[out] mode vlan propagation mode - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -isis_port_vlan_propagation_get(a_uint32_t dev_id, fal_port_t port_id, - fal_vlan_propagation_mode_t * mode) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _isis_port_vlan_propagation_get(dev_id, port_id, mode); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Add a vlan translation entry to a particular port. - * @param[in] dev_id device id - * @param[in] port_id port id - * @param entry vlan translation entry - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -isis_port_vlan_trans_add(a_uint32_t dev_id, fal_port_t port_id, - fal_vlan_trans_entry_t * entry) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _isis_port_vlan_trans_add(dev_id, port_id, entry); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Delete a vlan translation entry from a particular port. - * @param[in] dev_id device id - * @param[in] port_id port id - * @param entry vlan translation entry - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -isis_port_vlan_trans_del(a_uint32_t dev_id, fal_port_t port_id, - fal_vlan_trans_entry_t * entry) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _isis_port_vlan_trans_del(dev_id, port_id, entry); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Get a vlan translation entry from a particular port. - * @param[in] dev_id device id - * @param[in] port_id port id - * @param entry vlan translation entry - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -isis_port_vlan_trans_get(a_uint32_t dev_id, fal_port_t port_id, - fal_vlan_trans_entry_t * entry) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _isis_port_vlan_trans_get(dev_id, port_id, entry); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Iterate all vlan translation entries from a particular port. - * @param[in] dev_id device id - * @param[in] port_id port id - * @param[in] iterator translation entry index if it's zero means get the first entry - * @param[out] iterator next valid translation entry index - * @param[out] entry vlan translation entry - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -isis_port_vlan_trans_iterate(a_uint32_t dev_id, fal_port_t port_id, - a_uint32_t * iterator, - fal_vlan_trans_entry_t * entry) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _isis_port_vlan_trans_iterate(dev_id, port_id, iterator, entry); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Set switch qinq work mode on a particular device. - * @param[in] dev_id device id - * @param[in] mode qinq work mode - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -isis_qinq_mode_set(a_uint32_t dev_id, fal_qinq_mode_t mode) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _isis_qinq_mode_set(dev_id, mode); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Get switch qinq work mode on a particular device. - * @param[in] dev_id device id - * @param[out] mode qinq work mode - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -isis_qinq_mode_get(a_uint32_t dev_id, fal_qinq_mode_t * mode) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _isis_qinq_mode_get(dev_id, mode); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Set qinq role on a particular port. - * @param[in] dev_id device id - * @param[in] port_id port id - * @param[in] role port role - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -isis_port_qinq_role_set(a_uint32_t dev_id, fal_port_t port_id, - fal_qinq_port_role_t role) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _isis_port_qinq_role_set(dev_id, port_id, role); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Get qinq role on a particular port. - * @param[in] dev_id device id - * @param[in] port_id port id - * @param[out] role port role - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -isis_port_qinq_role_get(a_uint32_t dev_id, fal_port_t port_id, - fal_qinq_port_role_t * role) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _isis_port_qinq_role_get(dev_id, port_id, role); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Set MAC_VLAN_XLT status on a particular port. - * @param[in] dev_id device id - * @param[in] port_id port id - * @param[in] role port role - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -isis_port_mac_vlan_xlt_set(a_uint32_t dev_id, fal_port_t port_id, - a_bool_t enable) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _isis_port_mac_vlan_xlt_set(dev_id, port_id, enable); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Get MAC_VLAN_XLT status on a particular port. - * @param[in] dev_id device id - * @param[in] port_id port id - * @param[out] role port role - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -isis_port_mac_vlan_xlt_get(a_uint32_t dev_id, fal_port_t port_id, - a_bool_t * enable) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _isis_port_mac_vlan_xlt_get(dev_id, port_id, enable); - HSL_API_UNLOCK; - return rv; -} - -#ifdef HSL_STANDALONG -HSL_LOCAL sw_error_t -isis_port_route_defv_set(a_uint32_t dev_id, fal_port_t port_id) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv =_isis_port_route_defv_set(dev_id, port_id); - HSL_API_UNLOCK; - return rv; -} -#endif - -sw_error_t -isis_portvlan_init(a_uint32_t dev_id) -{ - a_uint32_t i; - sw_error_t rv; - fal_vlan_trans_entry_t entry_init; - hsl_api_t *p_api; - - HSL_DEV_ID_CHECK(dev_id); - - aos_mem_set(&entry_init, 0, sizeof (fal_vlan_trans_entry_t)); - - for (i = 0; i < ISIS_MAX_VLAN_TRANS; i++) - { - rv = _isis_vlan_trans_write(dev_id, i, 0, entry_init); - SW_RTN_ON_ERROR(rv); - } - -#ifndef HSL_STANDALONG - - SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id)); - - p_api->port_1qmode_get = isis_port_1qmode_get; - p_api->port_1qmode_set = isis_port_1qmode_set; - p_api->port_egvlanmode_get = isis_port_egvlanmode_get; - p_api->port_egvlanmode_set = isis_port_egvlanmode_set; - p_api->portvlan_member_add = isis_portvlan_member_add; - p_api->portvlan_member_del = isis_portvlan_member_del; - p_api->portvlan_member_update = isis_portvlan_member_update; - p_api->portvlan_member_get = isis_portvlan_member_get; - p_api->port_force_default_vid_set = isis_port_force_default_vid_set; - p_api->port_force_default_vid_get = isis_port_force_default_vid_get; - p_api->port_force_portvlan_set = isis_port_force_portvlan_set; - p_api->port_force_portvlan_get = isis_port_force_portvlan_get; - p_api->nestvlan_tpid_set = isis_nestvlan_tpid_set; - p_api->nestvlan_tpid_get = isis_nestvlan_tpid_get; - p_api->port_invlan_mode_set = isis_port_invlan_mode_set; - p_api->port_invlan_mode_get = isis_port_invlan_mode_get; - p_api->port_tls_set = isis_port_tls_set; - p_api->port_tls_get = isis_port_tls_get; - p_api->port_pri_propagation_set = isis_port_pri_propagation_set; - p_api->port_pri_propagation_get = isis_port_pri_propagation_get; - p_api->port_default_svid_set = isis_port_default_svid_set; - p_api->port_default_svid_get = isis_port_default_svid_get; - p_api->port_default_cvid_set = isis_port_default_cvid_set; - p_api->port_default_cvid_get = isis_port_default_cvid_get; - p_api->port_vlan_propagation_set = isis_port_vlan_propagation_set; - p_api->port_vlan_propagation_get = isis_port_vlan_propagation_get; - p_api->port_vlan_trans_add = isis_port_vlan_trans_add; - p_api->port_vlan_trans_del = isis_port_vlan_trans_del; - p_api->port_vlan_trans_get = isis_port_vlan_trans_get; - p_api->qinq_mode_set = isis_qinq_mode_set; - p_api->qinq_mode_get = isis_qinq_mode_get; - p_api->port_qinq_role_set = isis_port_qinq_role_set; - p_api->port_qinq_role_get = isis_port_qinq_role_get; - p_api->port_vlan_trans_iterate = isis_port_vlan_trans_iterate; - p_api->port_mac_vlan_xlt_set = isis_port_mac_vlan_xlt_set; - p_api->port_mac_vlan_xlt_get = isis_port_mac_vlan_xlt_get; -#endif - - return SW_OK; -} - -/** - * @} - */ diff --git a/feeds/ipq807x/qca-ssdk/src/src/hsl/isis/isis_qos.c b/feeds/ipq807x/qca-ssdk/src/src/hsl/isis/isis_qos.c deleted file mode 100755 index 0162b3a82..000000000 --- a/feeds/ipq807x/qca-ssdk/src/src/hsl/isis/isis_qos.c +++ /dev/null @@ -1,1325 +0,0 @@ -/* - * Copyright (c) 2012, 2016, The Linux Foundation. All rights reserved. - * Permission to use, copy, modify, and/or distribute this software for - * any purpose with or without fee is hereby granted, provided that the - * above copyright notice and this permission notice appear in all copies. - * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES - * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR - * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES - * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN - * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT - * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. - */ - - -/** - * @defgroup isis_qos ISIS_QOS - * @{ - */ -#include "sw.h" -#include "hsl.h" -#include "hsl_dev.h" -#include "hsl_port_prop.h" -#include "isis_qos.h" -#include "isis_reg.h" - -#define ISIS_QOS_QUEUE_TX_BUFFER_MAX 60 -#define ISIS_QOS_PORT_TX_BUFFER_MAX 252 -#define ISIS_QOS_PORT_RX_BUFFER_MAX 60 - -//#define ISIS_MIN_QOS_MODE_PRI 0 -#define ISIS_MAX_QOS_MODE_PRI 3 -#define ISIS_MAX_PRI 7 -#define ISIS_MAX_QUEUE 3 -#define ISIS_MAX_EH_QUEUE 5 - -static sw_error_t -_isis_qos_queue_tx_buf_status_set(a_uint32_t dev_id, fal_port_t port_id, - a_bool_t enable) -{ - a_uint32_t val = 0; - sw_error_t rv; - - if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU)) - { - return SW_BAD_PARAM; - } - - if (A_TRUE == enable) - { - val = 1; - } - else if (A_FALSE == enable) - { - val = 0; - } - else - { - return SW_BAD_PARAM; - } - - HSL_REG_FIELD_SET(rv, dev_id, PORT_HOL_CTL1, port_id, QUEUE_DESC_EN, - (a_uint8_t *) (&val), sizeof (a_uint32_t)); - return rv; -} - -static sw_error_t -_isis_qos_queue_tx_buf_status_get(a_uint32_t dev_id, fal_port_t port_id, - a_bool_t * enable) -{ - a_uint32_t val = 0; - sw_error_t rv; - - if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU)) - { - return SW_BAD_PARAM; - } - - HSL_REG_FIELD_GET(rv, dev_id, PORT_HOL_CTL1, port_id, QUEUE_DESC_EN, - (a_uint8_t *) (&val), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - - if (1 == val) - { - *enable = A_TRUE; - } - else - { - *enable = A_FALSE; - } - - return SW_OK; -} - -static sw_error_t -_isis_qos_port_tx_buf_status_set(a_uint32_t dev_id, fal_port_t port_id, - a_bool_t enable) -{ - a_uint32_t val = 0; - sw_error_t rv; - - if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU)) - { - return SW_BAD_PARAM; - } - - if (A_TRUE == enable) - { - val = 1; - } - else if (A_FALSE == enable) - { - val = 0; - } - else - { - return SW_BAD_PARAM; - } - - HSL_REG_FIELD_SET(rv, dev_id, PORT_HOL_CTL1, port_id, PORT_DESC_EN, - (a_uint8_t *) (&val), sizeof (a_uint32_t)); - return rv; -} - -static sw_error_t -_isis_qos_port_tx_buf_status_get(a_uint32_t dev_id, fal_port_t port_id, - a_bool_t * enable) -{ - a_uint32_t val = 0; - sw_error_t rv; - - if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU)) - { - return SW_BAD_PARAM; - } - - HSL_REG_FIELD_GET(rv, dev_id, PORT_HOL_CTL1, port_id, PORT_DESC_EN, - (a_uint8_t *) (&val), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - - if (1 == val) - { - *enable = A_TRUE; - } - else - { - *enable = A_FALSE; - } - - return SW_OK; -} - -static sw_error_t -_isis_qos_port_queue_check(fal_port_t port_id, fal_queue_t queue_id) -{ - if ((0 == port_id) || (5 == port_id) || (6 == port_id)) - { - if (ISIS_MAX_EH_QUEUE < queue_id) - { - return SW_BAD_PARAM; - } - } - else - { - if (ISIS_MAX_QUEUE < queue_id) - { - return SW_BAD_PARAM; - } - } - - return SW_OK; -} - -static sw_error_t -_isis_qos_queue_tx_buf_nr_set(a_uint32_t dev_id, fal_port_t port_id, - fal_queue_t queue_id, a_uint32_t * number) -{ - a_uint32_t data = 0, val = 0; - sw_error_t rv; - - if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU)) - { - return SW_BAD_PARAM; - } - - if (ISIS_QOS_QUEUE_TX_BUFFER_MAX < *number) - { - return SW_BAD_PARAM; - } - - rv = _isis_qos_port_queue_check(port_id, queue_id); - SW_RTN_ON_ERROR(rv); - - val = *number / 4; - *number = val << 2; - - HSL_REG_ENTRY_GET(rv, dev_id, PORT_HOL_CTL0, port_id, (a_uint8_t *) (&data), - sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - - data &= (~(0xf << (queue_id << 2))); - data |= (val << (queue_id << 2)); - - HSL_REG_ENTRY_SET(rv, dev_id, PORT_HOL_CTL0, port_id, (a_uint8_t *) (&data), - sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - - return rv; -} - -static sw_error_t -_isis_qos_queue_tx_buf_nr_get(a_uint32_t dev_id, fal_port_t port_id, - fal_queue_t queue_id, a_uint32_t * number) -{ - a_uint32_t data= 0, val = 0; - sw_error_t rv; - - if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU)) - { - return SW_BAD_PARAM; - } - - rv = _isis_qos_port_queue_check(port_id, queue_id); - SW_RTN_ON_ERROR(rv); - - HSL_REG_ENTRY_GET(rv, dev_id, PORT_HOL_CTL0, port_id, (a_uint8_t *) (&data), - sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - - val = (data >> (queue_id << 2)) & 0xf; - *number = val << 2; - return SW_OK; -} - -static sw_error_t -_isis_qos_port_tx_buf_nr_set(a_uint32_t dev_id, fal_port_t port_id, - a_uint32_t * number) -{ - a_uint32_t val = 0; - sw_error_t rv; - - if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU)) - { - return SW_BAD_PARAM; - } - - if (ISIS_QOS_PORT_TX_BUFFER_MAX < *number) - { - return SW_BAD_PARAM; - } - - val = *number / 4; - *number = val << 2; - HSL_REG_FIELD_SET(rv, dev_id, PORT_HOL_CTL0, port_id, PORT_DESC_NR, - (a_uint8_t *) (&val), sizeof (a_uint32_t)); - return rv; -} - -static sw_error_t -_isis_qos_port_tx_buf_nr_get(a_uint32_t dev_id, fal_port_t port_id, - a_uint32_t * number) -{ - a_uint32_t val = 0; - sw_error_t rv; - - if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU)) - { - return SW_BAD_PARAM; - } - - HSL_REG_FIELD_GET(rv, dev_id, PORT_HOL_CTL0, port_id, PORT_DESC_NR, - (a_uint8_t *) (&val), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - - *number = val << 2; - return SW_OK; -} - -static sw_error_t -_isis_qos_port_rx_buf_nr_set(a_uint32_t dev_id, fal_port_t port_id, - a_uint32_t * number) -{ - a_uint32_t val = 0; - sw_error_t rv; - - if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU)) - { - return SW_BAD_PARAM; - } - - if (ISIS_QOS_PORT_RX_BUFFER_MAX < *number) - { - return SW_BAD_PARAM; - } - - val = *number / 4; - *number = val << 2; - HSL_REG_FIELD_SET(rv, dev_id, PORT_HOL_CTL1, port_id, PORT_IN_DESC_EN, - (a_uint8_t *) (&val), sizeof (a_uint32_t)); - return rv; -} - -static sw_error_t -_isis_qos_port_rx_buf_nr_get(a_uint32_t dev_id, fal_port_t port_id, - a_uint32_t * number) -{ - a_uint32_t val = 0; - sw_error_t rv; - - if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU)) - { - return SW_BAD_PARAM; - } - - HSL_REG_FIELD_GET(rv, dev_id, PORT_HOL_CTL1, port_id, PORT_IN_DESC_EN, - (a_uint8_t *) (&val), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - - *number = val << 2; - return SW_OK; -} - -static sw_error_t -_isis_qos_port_mode_set(a_uint32_t dev_id, fal_port_t port_id, - fal_qos_mode_t mode, a_bool_t enable) -{ - sw_error_t rv; - a_uint32_t val; - - HSL_DEV_ID_CHECK(dev_id); - - if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU)) - { - return SW_BAD_PARAM; - } - - if (A_TRUE == enable) - { - val = 1; - } - else if (A_FALSE == enable) - { - val = 0; - } - else - { - return SW_BAD_PARAM; - } - - if (FAL_QOS_DA_MODE == mode) - { - HSL_REG_FIELD_SET(rv, dev_id, PRI_CTL, port_id, DA_PRI_EN, - (a_uint8_t *) (&val), sizeof (a_uint32_t)); - } - else if (FAL_QOS_UP_MODE == mode) - { - HSL_REG_FIELD_SET(rv, dev_id, PRI_CTL, port_id, VLAN_PRI_EN, - (a_uint8_t *) (&val), sizeof (a_uint32_t)); - } - else if (FAL_QOS_DSCP_MODE == mode) - { - HSL_REG_FIELD_SET(rv, dev_id, PRI_CTL, port_id, IP_PRI_EN, - (a_uint8_t *) (&val), sizeof (a_uint32_t)); - } - else - { - return SW_BAD_PARAM; - } - - return rv; -} - -static sw_error_t -_isis_qos_port_mode_get(a_uint32_t dev_id, fal_port_t port_id, - fal_qos_mode_t mode, a_bool_t * enable) -{ - sw_error_t rv; - a_uint32_t val = 0; - - HSL_DEV_ID_CHECK(dev_id); - - if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU)) - { - return SW_BAD_PARAM; - } - - if (FAL_QOS_DA_MODE == mode) - { - HSL_REG_FIELD_GET(rv, dev_id, PRI_CTL, port_id, DA_PRI_EN, - (a_uint8_t *) (&val), sizeof (a_uint32_t)); - } - else if (FAL_QOS_UP_MODE == mode) - { - HSL_REG_FIELD_GET(rv, dev_id, PRI_CTL, port_id, VLAN_PRI_EN, - (a_uint8_t *) (&val), sizeof (a_uint32_t)); - } - else if (FAL_QOS_DSCP_MODE == mode) - { - HSL_REG_FIELD_GET(rv, dev_id, PRI_CTL, port_id, IP_PRI_EN, - (a_uint8_t *) (&val), sizeof (a_uint32_t)); - } - else - { - return SW_BAD_PARAM; - } - SW_RTN_ON_ERROR(rv); - - if (1 == val) - { - *enable = A_TRUE; - } - else - { - *enable = A_FALSE; - } - - return SW_OK; -} - -static sw_error_t -_isis_qos_port_mode_pri_set(a_uint32_t dev_id, fal_port_t port_id, - fal_qos_mode_t mode, a_uint32_t pri) -{ - sw_error_t rv; - a_uint32_t val = 0; - - HSL_DEV_ID_CHECK(dev_id); - - if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU)) - { - return SW_BAD_PARAM; - } - - if (ISIS_MAX_QOS_MODE_PRI < pri) - { - return SW_BAD_PARAM; - } - - HSL_REG_ENTRY_GET(rv, dev_id, PRI_CTL, port_id, (a_uint8_t *) (&val), - sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - - if (FAL_QOS_DA_MODE == mode) - { - SW_SET_REG_BY_FIELD(PRI_CTL, DA_PRI_SEL, pri, val); - } - else if (FAL_QOS_UP_MODE == mode) - { - SW_SET_REG_BY_FIELD(PRI_CTL, VLAN_PRI_SEL, pri, val); - } - else if (FAL_QOS_DSCP_MODE == mode) - { - SW_SET_REG_BY_FIELD(PRI_CTL, IP_PRI_SEL, pri, val); - } - else - { - return SW_NOT_SUPPORTED; - } - - HSL_REG_ENTRY_SET(rv, dev_id, PRI_CTL, port_id, (a_uint8_t *) (&val), - sizeof (a_uint32_t)); - return rv; -} - -static sw_error_t -_isis_qos_port_mode_pri_get(a_uint32_t dev_id, fal_port_t port_id, - fal_qos_mode_t mode, a_uint32_t * pri) -{ - sw_error_t rv; - a_uint32_t entry = 0, f_val; - - HSL_DEV_ID_CHECK(dev_id); - - if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU)) - { - return SW_BAD_PARAM; - } - - HSL_REG_ENTRY_GET(rv, dev_id, PRI_CTL, port_id, (a_uint8_t *) (&entry), - sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - - if (FAL_QOS_DA_MODE == mode) - { - SW_GET_FIELD_BY_REG(PRI_CTL, DA_PRI_SEL, f_val, entry); - } - else if (FAL_QOS_UP_MODE == mode) - { - SW_GET_FIELD_BY_REG(PRI_CTL, VLAN_PRI_SEL, f_val, entry); - } - else if (FAL_QOS_DSCP_MODE == mode) - { - SW_GET_FIELD_BY_REG(PRI_CTL, IP_PRI_SEL, f_val, entry); - } - else - { - return SW_NOT_SUPPORTED; - } - - *pri = f_val; - return SW_OK; -} - -static sw_error_t -_isis_qos_port_sch_mode_set(a_uint32_t dev_id, a_uint32_t port_id, - fal_sch_mode_t mode, const a_uint32_t weight[]) -{ - sw_error_t rv; - a_uint32_t reg = 0, val, w[6] = { 0 }; - a_int32_t i, _index; - - HSL_DEV_ID_CHECK(dev_id); - - if (FAL_SCH_SP_MODE == mode) - { - val = 0; - _index = -1; - } - else if (FAL_SCH_WRR_MODE == mode) - { - val = 3; - _index = 5; - } - else if (FAL_SCH_MIX_MODE == mode) - { - val = 1; - _index = 4; - } - else if (FAL_SCH_MIX_PLUS_MODE == mode) - { - val = 2; - _index = 3; - } - else - { - return SW_NOT_SUPPORTED; - } - - for (i = _index; i >= 0; i--) - { - if (weight[i] > 0x1f) - { - return SW_BAD_PARAM; - } - w[i] = weight[i]; - } - - HSL_REG_ENTRY_GET(rv, dev_id, WRR_CTRL, port_id, (a_uint8_t *) (®), - sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - - SW_SET_REG_BY_FIELD(WRR_CTRL, SCH_MODE, val, reg); - SW_SET_REG_BY_FIELD(WRR_CTRL, Q5_W, w[5], reg); - SW_SET_REG_BY_FIELD(WRR_CTRL, Q4_W, w[4], reg); - SW_SET_REG_BY_FIELD(WRR_CTRL, Q3_W, w[3], reg); - SW_SET_REG_BY_FIELD(WRR_CTRL, Q2_W, w[2], reg); - SW_SET_REG_BY_FIELD(WRR_CTRL, Q1_W, w[1], reg); - SW_SET_REG_BY_FIELD(WRR_CTRL, Q0_W, w[0], reg); - - HSL_REG_ENTRY_SET(rv, dev_id, WRR_CTRL, port_id, - (a_uint8_t *) (®), sizeof (a_uint32_t)); - return rv; -} - -static sw_error_t -_isis_qos_port_sch_mode_get(a_uint32_t dev_id, a_uint32_t port_id, - fal_sch_mode_t * mode, a_uint32_t weight[]) -{ - sw_error_t rv; - a_uint32_t val = 0, sch, w[6], i; - - HSL_DEV_ID_CHECK(dev_id); - - HSL_REG_ENTRY_GET(rv, dev_id, WRR_CTRL, port_id, (a_uint8_t *) (&val), - sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - - SW_GET_FIELD_BY_REG(WRR_CTRL, SCH_MODE, sch, val); - SW_GET_FIELD_BY_REG(WRR_CTRL, Q5_W, w[5], val); - SW_GET_FIELD_BY_REG(WRR_CTRL, Q4_W, w[4], val); - SW_GET_FIELD_BY_REG(WRR_CTRL, Q3_W, w[3], val); - SW_GET_FIELD_BY_REG(WRR_CTRL, Q2_W, w[2], val); - SW_GET_FIELD_BY_REG(WRR_CTRL, Q1_W, w[1], val); - SW_GET_FIELD_BY_REG(WRR_CTRL, Q0_W, w[0], val); - - if (0 == sch) - { - *mode = FAL_SCH_SP_MODE; - } - else if (1 == sch) - { - *mode = FAL_SCH_MIX_MODE; - } - else if (2 == sch) - { - *mode = FAL_SCH_MIX_PLUS_MODE; - } - else - { - *mode = FAL_SCH_WRR_MODE; - } - - for (i = 0; i < 6; i++) - { - weight[i] = w[i]; - } - - return SW_OK; -} - -static sw_error_t -_isis_qos_port_default_spri_set(a_uint32_t dev_id, fal_port_t port_id, - a_uint32_t spri) -{ - sw_error_t rv; - a_uint32_t val; - - HSL_DEV_ID_CHECK(dev_id); - - if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU)) - { - return SW_BAD_PARAM; - } - - if (ISIS_MAX_PRI < spri) - { - return SW_BAD_PARAM; - } - - val = spri; - HSL_REG_FIELD_SET(rv, dev_id, PORT_VLAN0, port_id, - ING_SPRI, (a_uint8_t *) (&val), sizeof (a_uint32_t)); - - return rv; -} - -static sw_error_t -_isis_qos_port_default_spri_get(a_uint32_t dev_id, fal_port_t port_id, - a_uint32_t * spri) -{ - sw_error_t rv; - a_uint32_t val = 0; - - HSL_DEV_ID_CHECK(dev_id); - - if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU)) - { - return SW_BAD_PARAM; - } - - HSL_REG_FIELD_GET(rv, dev_id, PORT_VLAN0, port_id, - ING_SPRI, (a_uint8_t *) (&val), sizeof (a_uint32_t)); - - *spri = val & 0x7; - return rv; -} - -static sw_error_t -_isis_qos_port_default_cpri_set(a_uint32_t dev_id, fal_port_t port_id, - a_uint32_t cpri) -{ - sw_error_t rv; - a_uint32_t val; - - HSL_DEV_ID_CHECK(dev_id); - - if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU)) - { - return SW_BAD_PARAM; - } - - if (ISIS_MAX_PRI < cpri) - { - return SW_BAD_PARAM; - } - - val = cpri; - HSL_REG_FIELD_SET(rv, dev_id, PORT_VLAN0, port_id, - ING_CPRI, (a_uint8_t *) (&val), sizeof (a_uint32_t)); - - return rv; -} - -HSL_LOCAL sw_error_t -_isis_qos_port_default_cpri_get(a_uint32_t dev_id, fal_port_t port_id, - a_uint32_t * cpri) -{ - sw_error_t rv; - a_uint32_t val = 0; - - HSL_DEV_ID_CHECK(dev_id); - - if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU)) - { - return SW_BAD_PARAM; - } - - HSL_REG_FIELD_GET(rv, dev_id, PORT_VLAN0, port_id, - ING_CPRI, (a_uint8_t *) (&val), sizeof (a_uint32_t)); - - *cpri = val & 0x7; - return rv; -} - -static sw_error_t -_isis_qos_queue_remark_table_set(a_uint32_t dev_id, fal_port_t port_id, - fal_queue_t queue_id, a_uint32_t tbl_id, a_bool_t enable) -{ - sw_error_t rv; - a_uint32_t addr, data = 0; - a_uint32_t base[7] = {0x0c40, 0x0c48, 0x0c4c, 0x0c50, 0x0c54, 0x0c58, 0x0c60}; - - rv = _isis_qos_port_queue_check(port_id, queue_id); - SW_RTN_ON_ERROR(rv); - - addr = base[port_id] + ((queue_id / 4) << 2); - HSL_REG_ENTRY_GEN_GET(rv, dev_id, addr, sizeof (a_uint32_t), - (a_uint8_t *) (&data), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - - data &= (~(0xff << ((queue_id % 4) << 3))); - data |= (((enable << 7 ) | (tbl_id & 0xf)) << ((queue_id % 4) << 3)); - - HSL_REG_ENTRY_GEN_SET(rv, dev_id, addr, sizeof (a_uint32_t), - (a_uint8_t *) (&data), sizeof (a_uint32_t)); - return rv; -} - -HSL_LOCAL sw_error_t -_isis_qos_queue_remark_table_get(a_uint32_t dev_id, fal_port_t port_id, - fal_queue_t queue_id, a_uint32_t * tbl_id, a_bool_t * enable) -{ - sw_error_t rv; - a_uint32_t addr, data = 0; - a_uint32_t base[7] = {0x0c40, 0x0c48, 0x0c4c, 0x0c50, 0x0c54, 0x0c58, 0x0c60}; - - rv = _isis_qos_port_queue_check(port_id, queue_id); - SW_RTN_ON_ERROR(rv); - - addr = base[port_id] + ((queue_id / 4) << 2); - HSL_REG_ENTRY_GEN_GET(rv, dev_id, addr, sizeof (a_uint32_t), - (a_uint8_t *) (&data), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - - *tbl_id = (data >> ((queue_id % 4) << 3)) & 0xf; - *enable = ((data >> ((queue_id % 4) << 3)) & 0x80) >> 7; - return SW_OK; -} - -HSL_LOCAL sw_error_t -_isis_port_static_thresh_get(a_uint32_t dev_id, fal_port_t port_id, - fal_bm_static_cfg_t *cfg) -{ - sw_error_t rv; - a_uint32_t reg_value, xon_value, xoff_value; - - HSL_REG_ENTRY_GET(rv, dev_id, PORT_FLOW_CTRL_THRESHOLD, port_id, - (a_uint8_t *) (®_value), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - - SW_GET_FIELD_BY_REG(PORT_FLOW_CTRL_THRESHOLD, XON_THRES, xon_value, reg_value); - SW_GET_FIELD_BY_REG(PORT_FLOW_CTRL_THRESHOLD, XOFF_THRES, xoff_value, reg_value); - cfg->max_thresh = xoff_value; - cfg->resume_off = xoff_value - xon_value; - - return SW_OK; -} - -HSL_LOCAL sw_error_t -_isis_port_static_thresh_set(a_uint32_t dev_id, fal_port_t port_id, - fal_bm_static_cfg_t *cfg) -{ - sw_error_t rv; - a_uint32_t reg_value = 0; - - SW_SET_REG_BY_FIELD(PORT_FLOW_CTRL_THRESHOLD, XON_THRES, cfg->max_thresh - cfg->resume_off, reg_value); - SW_SET_REG_BY_FIELD(PORT_FLOW_CTRL_THRESHOLD, XOFF_THRES, cfg->max_thresh, reg_value); - - HSL_REG_ENTRY_SET(rv, dev_id, PORT_FLOW_CTRL_THRESHOLD, port_id, - (a_uint8_t *) (®_value), sizeof (a_uint32_t)); - - return SW_OK; -} - -/** - * @brief Set buffer aggsinment status of transmitting queue on one particular port. - * @details Comments: - * If enable queue tx buffer on one port that means each queue of this port - * will have fixed number buffers when transmitting packets. Otherwise they - * share the whole buffers with other queues in device. - * @param[in] dev_id device id - * @param[in] port_id port id - * @param[in] enable A_TRUE or A_FALSE - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -isis_qos_queue_tx_buf_status_set(a_uint32_t dev_id, fal_port_t port_id, - a_bool_t enable) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _isis_qos_queue_tx_buf_status_set(dev_id, port_id, enable); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Get buffer aggsinment status of transmitting queue on particular port. - * @param[in] dev_id device id - * @param[in] port_id port id - * @param[in] enable A_TRUE or A_FALSE - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -isis_qos_queue_tx_buf_status_get(a_uint32_t dev_id, fal_port_t port_id, - a_bool_t * enable) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _isis_qos_queue_tx_buf_status_get(dev_id, port_id, enable); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Set buffer aggsinment status of transmitting port on one particular port. - * @details Comments: - If enable tx buffer on one port that means this port will have fixed - number buffers when transmitting packets. Otherwise they will - share the whole buffers with other ports in device. - * function will return actual buffer numbers in hardware. - * @param[in] dev_id device id - * @param[in] port_id port id - * @param[in] enable A_TRUE or A_FALSE - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -isis_qos_port_tx_buf_status_set(a_uint32_t dev_id, fal_port_t port_id, - a_bool_t enable) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _isis_qos_port_tx_buf_status_set(dev_id, port_id, enable); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Get buffer aggsinment status of transmitting port on one particular port. - * @param[in] dev_id device id - * @param[in] port_id port id - * @param[out] enable A_TRUE or A_FALSE - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -isis_qos_port_tx_buf_status_get(a_uint32_t dev_id, fal_port_t port_id, - a_bool_t * enable) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _isis_qos_port_tx_buf_status_get(dev_id, port_id, enable); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Set max occupied buffer number of transmitting queue on one particular port. - * @details Comments: - The step of buffer number in Garuda is 4, function will return actual - buffer numbers in hardware. - The buffer number range for queue is 4 to 60. - * share the whole buffers with other ports in device. - * @param[in] dev_id device id - * @param[in] port_id port id - * @param[in] queue_id queue id - * @param number buffer number - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -isis_qos_queue_tx_buf_nr_set(a_uint32_t dev_id, fal_port_t port_id, - fal_queue_t queue_id, a_uint32_t * number) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _isis_qos_queue_tx_buf_nr_set(dev_id, port_id, queue_id, number); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Get max occupied buffer number of transmitting queue on one particular port. - * @param[in] dev_id device id - * @param[in] port_id port id - * @param[in] queue_id queue id - * @param[out] number buffer number - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -isis_qos_queue_tx_buf_nr_get(a_uint32_t dev_id, fal_port_t port_id, - fal_queue_t queue_id, a_uint32_t * number) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _isis_qos_queue_tx_buf_nr_get(dev_id, port_id, queue_id, number); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Set max occupied buffer number of transmitting port on one particular port. - * @details Comments: - The step of buffer number in Garuda is four, function will return actual - buffer numbers in hardware. - The buffer number range for transmitting port is 4 to 124. - * @param[in] dev_id device id - * @param[in] port_id port id - * @param number buffer number - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -isis_qos_port_tx_buf_nr_set(a_uint32_t dev_id, fal_port_t port_id, - a_uint32_t * number) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _isis_qos_port_tx_buf_nr_set(dev_id, port_id, number); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Get max occupied buffer number of transmitting port on one particular port. - * @param[in] dev_id device id - * @param[in] port_id port id - * @param[out] number buffer number - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -isis_qos_port_tx_buf_nr_get(a_uint32_t dev_id, fal_port_t port_id, - a_uint32_t * number) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _isis_qos_port_tx_buf_nr_get(dev_id, port_id, number); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Set max occupied buffer number of receiving port on one particular port. - * @details Comments: - The step of buffer number in Shiva is four, function will return actual - buffer numbers in hardware. - The buffer number range for receiving port is 4 to 60. - * @param[in] dev_id device id - * @param[in] port_id port id - * @param number buffer number - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -isis_qos_port_rx_buf_nr_set(a_uint32_t dev_id, fal_port_t port_id, - a_uint32_t * number) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _isis_qos_port_rx_buf_nr_set(dev_id, port_id, number); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Get max occupied buffer number of receiving port on one particular port. - * @param[in] dev_id device id - * @param[in] port_id port id - * @param[out] number buffer number - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -isis_qos_port_rx_buf_nr_get(a_uint32_t dev_id, fal_port_t port_id, - a_uint32_t * number) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _isis_qos_port_rx_buf_nr_get(dev_id, port_id, number); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Set port qos mode on a particular port. - * @param[in] dev_id device id - * @param[in] port_id port id - * @param[in] mode qos mode - * @param[in] enable A_TRUE of A_FALSE - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -isis_qos_port_mode_set(a_uint32_t dev_id, fal_port_t port_id, - fal_qos_mode_t mode, a_bool_t enable) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _isis_qos_port_mode_set(dev_id, port_id, mode, enable); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Get port qos mode on a particular port. - * @param[in] dev_id device id - * @param[in] port_id port id - * @param[in] mode qos mode - * @param[out] enable A_TRUE of A_FALSE - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -isis_qos_port_mode_get(a_uint32_t dev_id, fal_port_t port_id, - fal_qos_mode_t mode, a_bool_t * enable) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _isis_qos_port_mode_get(dev_id, port_id, mode, enable); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Set priority of one particular qos mode on one particular port. - * @details Comments: - If the priority of a mode is more small then the priority is more high. - Differnet mode should have differnet priority. - * @param[in] dev_id device id - * @param[in] port_id port id - * @param[in] mode qos mode - * @param[in] pri priority of one particular qos mode - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -isis_qos_port_mode_pri_set(a_uint32_t dev_id, fal_port_t port_id, - fal_qos_mode_t mode, a_uint32_t pri) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _isis_qos_port_mode_pri_set(dev_id, port_id, mode, pri); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Get priority of one particular qos mode on one particular port. - * @param[in] dev_id device id - * @param[in] port_id port id - * @param[in] mode qos mode - * @param[out] pri priority of one particular qos mode - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -isis_qos_port_mode_pri_get(a_uint32_t dev_id, fal_port_t port_id, - fal_qos_mode_t mode, a_uint32_t * pri) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _isis_qos_port_mode_pri_get(dev_id, port_id, mode, pri); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Set traffic scheduling mode on particular one port. - * @details Comments: - * When scheduling mode is sp the weight is meaningless usually it's zero - * @param[in] dev_id device id - * @param[in] port_id port id - * @param[in] fal_sch_mode_t traffic scheduling mode - * @param[in] weight[] weight value for each queue when in wrr mode, - the max value supported by ISIS is 0x1f. - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -isis_qos_port_sch_mode_set(a_uint32_t dev_id, a_uint32_t port_id, - fal_sch_mode_t mode, const a_uint32_t weight[]) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _isis_qos_port_sch_mode_set(dev_id, port_id, mode, weight); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Get traffic scheduling mode on particular port. - * @param[in] dev_id device id - * @param[in] port_id port id - * @param[out] fal_sch_mode_t traffic scheduling mode - * @param[out] weight weight value for wrr mode - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -isis_qos_port_sch_mode_get(a_uint32_t dev_id, a_uint32_t port_id, - fal_sch_mode_t * mode, a_uint32_t weight[]) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _isis_qos_port_sch_mode_get(dev_id, port_id, mode, weight); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Set default stag priority on one particular port. - * @param[in] dev_id device id - * @param[in] port_id port id - * @param[in] spri vlan priority - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -isis_qos_port_default_spri_set(a_uint32_t dev_id, fal_port_t port_id, - a_uint32_t spri) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _isis_qos_port_default_spri_set(dev_id, port_id, spri); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Get default stag priority on one particular port. - * @param[in] dev_id device id - * @param[in] port_id port id - * @param[out] spri vlan priority - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -isis_qos_port_default_spri_get(a_uint32_t dev_id, fal_port_t port_id, - a_uint32_t * spri) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _isis_qos_port_default_spri_get(dev_id, port_id, spri); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Set default ctag priority on one particular port. - * @param[in] dev_id device id - * @param[in] port_id port id - * @param[in] cpri vlan priority - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -isis_qos_port_default_cpri_set(a_uint32_t dev_id, fal_port_t port_id, - a_uint32_t cpri) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _isis_qos_port_default_cpri_set(dev_id, port_id, cpri); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Get default ctag priority on one particular port. - * @param[in] dev_id device id - * @param[in] port_id port id - * @param[out] cpri vlan priority - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -isis_qos_port_default_cpri_get(a_uint32_t dev_id, fal_port_t port_id, - a_uint32_t * cpri) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _isis_qos_port_default_cpri_get(dev_id, port_id, cpri); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Set egress queue based CoS remark on one particular port. - * @param[in] dev_id device id - * @param[in] port_id port id - * @param[in] queue_id queue id - * @param[in] tbl_id CoS remark table id - * @param[in] enable A_TRUE or A_FALSE - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -isis_qos_queue_remark_table_set(a_uint32_t dev_id, fal_port_t port_id, - fal_queue_t queue_id, a_uint32_t tbl_id, a_bool_t enable) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _isis_qos_queue_remark_table_set(dev_id, port_id, queue_id, tbl_id, enable); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Get egress queue based CoS remark on one particular port. - * @param[in] dev_id device id - * @param[in] port_id port id - * @param[in] queue_id queue id - * @param[out] tbl_id CoS remark table id - * @param[out] enable A_TRUE or A_FALSE - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -isis_qos_queue_remark_table_get(a_uint32_t dev_id, fal_port_t port_id, - fal_queue_t queue_id, a_uint32_t * tbl_id, a_bool_t * enable) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _isis_qos_queue_remark_table_get(dev_id, port_id, queue_id, tbl_id, enable); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Get static flow control threshold on one particular port. - * @param[in] dev_id device id - * @param[in] port_id port id - * @param[out] static maximum threshold and resume offset - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -isis_port_static_thresh_get(a_uint32_t dev_id, fal_port_t port_id, - fal_bm_static_cfg_t *cfg) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _isis_port_static_thresh_get(dev_id, port_id, cfg); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Set static flow control threshold on one particular port. - * @param[in] dev_id device id - * @param[in] port_id port id - * @param[out] static maximum threshold and resume offset - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -isis_port_static_thresh_set(a_uint32_t dev_id, fal_port_t port_id, - fal_bm_static_cfg_t *cfg) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _isis_port_static_thresh_set(dev_id, port_id, cfg); - HSL_API_UNLOCK; - return rv; -} - -sw_error_t -isis_qos_init(a_uint32_t dev_id) -{ - HSL_DEV_ID_CHECK(dev_id); - -#ifndef HSL_STANDALONG - { - hsl_api_t *p_api; - - SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id)); - - p_api->qos_queue_tx_buf_status_set = isis_qos_queue_tx_buf_status_set; - p_api->qos_queue_tx_buf_status_get = isis_qos_queue_tx_buf_status_get; - p_api->qos_port_tx_buf_status_set = isis_qos_port_tx_buf_status_set; - p_api->qos_port_tx_buf_status_get = isis_qos_port_tx_buf_status_get; - p_api->qos_queue_tx_buf_nr_set = isis_qos_queue_tx_buf_nr_set; - p_api->qos_queue_tx_buf_nr_get = isis_qos_queue_tx_buf_nr_get; - p_api->qos_port_tx_buf_nr_set = isis_qos_port_tx_buf_nr_set; - p_api->qos_port_tx_buf_nr_get = isis_qos_port_tx_buf_nr_get; - p_api->qos_port_rx_buf_nr_set = isis_qos_port_rx_buf_nr_set; - p_api->qos_port_rx_buf_nr_get = isis_qos_port_rx_buf_nr_get; - p_api->qos_port_mode_set = isis_qos_port_mode_set; - p_api->qos_port_mode_get = isis_qos_port_mode_get; - p_api->qos_port_mode_pri_set = isis_qos_port_mode_pri_set; - p_api->qos_port_mode_pri_get = isis_qos_port_mode_pri_get; - p_api->qos_port_sch_mode_set = isis_qos_port_sch_mode_set; - p_api->qos_port_sch_mode_get = isis_qos_port_sch_mode_get; - p_api->qos_port_default_spri_set = isis_qos_port_default_spri_set; - p_api->qos_port_default_spri_get = isis_qos_port_default_spri_get; - p_api->qos_port_default_cpri_set = isis_qos_port_default_cpri_set; - p_api->qos_port_default_cpri_get = isis_qos_port_default_cpri_get; - p_api->qos_queue_remark_table_set = isis_qos_queue_remark_table_set; - p_api->qos_queue_remark_table_get = isis_qos_queue_remark_table_get; - - p_api->port_static_thresh_get = isis_port_static_thresh_get; - p_api->port_static_thresh_set = isis_port_static_thresh_set; - } -#endif - - return SW_OK; -} - -/** - * @} - */ diff --git a/feeds/ipq807x/qca-ssdk/src/src/hsl/isis/isis_rate.c b/feeds/ipq807x/qca-ssdk/src/src/hsl/isis/isis_rate.c deleted file mode 100755 index 8e516ed3e..000000000 --- a/feeds/ipq807x/qca-ssdk/src/src/hsl/isis/isis_rate.c +++ /dev/null @@ -1,1549 +0,0 @@ -/* - * Copyright (c) 2012, 2016 The Linux Foundation. All rights reserved. - * Permission to use, copy, modify, and/or distribute this software for - * any purpose with or without fee is hereby granted, provided that the - * above copyright notice and this permission notice appear in all copies. - * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES - * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR - * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES - * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN - * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT - * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. - */ - - -/** - * @defgroup isis_rate ISIS_RATE - * @{ - */ -#include "sw.h" -#include "hsl.h" -#include "hsl_dev.h" -#include "hsl_port_prop.h" -#include "isis_rate.h" -#include "isis_reg.h" - -#define ISIS_MAX_POLICER_ID 31 -#define ISIS_MAX_QUEUE 3 -#define ISIS_MAX_EH_QUEUE 5 - -#define ACL_POLICER_CNT_SEL_ADDR 0x09f0 -#define ACL_POLICER_CNT_MODE_ADDR 0x09f4 -#define ACL_POLICER_CNT_RST_ADDR 0x09f8 - -static sw_error_t -_isis_rate_port_queue_check(fal_port_t port_id, fal_queue_t queue_id) -{ - if ((0 == port_id) || (5 == port_id) || (6 == port_id)) - { - if (ISIS_MAX_EH_QUEUE < queue_id) - { - return SW_BAD_PARAM; - } - } - else - { - if (ISIS_MAX_QUEUE < queue_id) - { - return SW_BAD_PARAM; - } - } - - return SW_OK; -} - -static void -_isis_egress_bs_byte_sw_to_hw(a_uint32_t sw_bs, a_uint32_t * hw_bs) -{ - a_int32_t i; - a_uint32_t data[8] = - { - 0, 2 * 1024, 4 * 1024, 8 * 1024, 16 * 1024, 32 * 1024, 128 * 1024, - 512 * 1024 - }; - - for (i = 7; i >= 0; i--) - { - if (sw_bs >= data[i]) - { - *hw_bs = i; - break; - } - } -} - -static void -_isis_egress_bs_byte_hw_to_sw(a_uint32_t hw_bs, a_uint32_t * sw_bs) -{ - a_uint32_t data[8] = - { - 0, 2 * 1024, 4 * 1024, 8 * 1024, 16 * 1024, 32 * 1024, 128 * 1024, - 512 * 1024 - }; - - *sw_bs = data[hw_bs & 0x7]; -} - -static void -_isis_egress_bs_frame_sw_to_hw(a_uint32_t sw_bs, a_uint32_t * hw_bs) -{ - a_uint32_t data[8] = { 0, 2, 4, 16, 64, 256, 512, 1024 }; - a_int32_t i; - - for (i = 7; i >= 0; i--) - { - if (sw_bs >= data[i]) - { - *hw_bs = i; - break; - } - } -} - -static void -_isis_egress_bs_frame_hw_to_sw(a_uint32_t hw_bs, a_uint32_t * sw_bs) -{ - a_uint32_t data[8] = { 0, 2, 4, 16, 64, 256, 512, 1024 }; - - *sw_bs = data[hw_bs & 0x7]; -} - -static void -_isis_ingress_bs_byte_sw_to_hw(a_uint32_t sw_bs, a_uint32_t * hw_bs) -{ - a_int32_t i; - a_uint32_t data[8] = - { - 0, 4 * 1024, 32 * 1024, 128 * 1024, 512 * 1024, 2 * 1024 * 1024, - 8 * 1024 * 1024, 32 * 1024 * 1024 - }; - - for (i = 7; i >= 0; i--) - { - if (sw_bs >= data[i]) - { - *hw_bs = i; - break; - } - } -} - -static void -_isis_ingress_bs_byte_hw_to_sw(a_uint32_t hw_bs, a_uint32_t * sw_bs) -{ - a_uint32_t data[8] = - { - 0, 4 * 1024, 32 * 1024, 128 * 1024, 512 * 1024, 2 * 1024 * 1024, - 8 * 1024 * 1024, 32 * 1024 * 1024 - }; - - *sw_bs = data[hw_bs & 0x7]; -} - -static void -_isis_ingress_bs_frame_sw_to_hw(a_uint32_t sw_bs, a_uint32_t * hw_bs) -{ - a_uint32_t data[8] = { 0, 4, 16, 64, 256, 1024, 4096, 16384 }; - a_int32_t i; - - for (i = 7; i >= 0; i--) - { - if (sw_bs >= data[i]) - { - *hw_bs = i; - break; - } - } -} - -static void -_isis_ingress_bs_frame_hw_to_sw(a_uint32_t hw_bs, a_uint32_t * sw_bs) -{ - a_uint32_t data[8] = { 0, 4, 16, 64, 256, 1024, 4096, 16384 }; - - *sw_bs = data[hw_bs & 0x7]; -} - -static void -_isis_rate_flag_parse(a_uint32_t sw_flag, a_uint32_t * hw_flag) -{ - *hw_flag = 0; - - if (FAL_INGRESS_POLICING_TCP_CTRL & sw_flag) - { - *hw_flag |= (0x1 << 1); - } - - if (FAL_INGRESS_POLICING_MANAGEMENT & sw_flag) - { - *hw_flag |= (0x1 << 2); - } - - if (FAL_INGRESS_POLICING_BROAD & sw_flag) - { - *hw_flag |= (0x1 << 3); - } - - if (FAL_INGRESS_POLICING_UNK_UNI & sw_flag) - { - *hw_flag |= (0x1 << 4); - } - - if (FAL_INGRESS_POLICING_UNK_MUL & sw_flag) - { - *hw_flag |= (0x1 << 5); - } - - if (FAL_INGRESS_POLICING_UNI & sw_flag) - { - *hw_flag |= (0x1 << 6); - } - - if (FAL_INGRESS_POLICING_MUL & sw_flag) - { - *hw_flag |= (0x1 << 7); - } -} - -static void -_isis_rate_flag_reparse(a_uint32_t hw_flag, a_uint32_t * sw_flag) -{ - *sw_flag = 0; - - if (hw_flag & 0x2) - { - *sw_flag |= FAL_INGRESS_POLICING_TCP_CTRL; - } - - if (hw_flag & 0x4) - { - *sw_flag |= FAL_INGRESS_POLICING_MANAGEMENT; - } - - if (hw_flag & 0x8) - { - *sw_flag |= FAL_INGRESS_POLICING_BROAD; - } - - if (hw_flag & 0x10) - { - *sw_flag |= FAL_INGRESS_POLICING_UNK_UNI; - } - - if (hw_flag & 0x20) - { - *sw_flag |= FAL_INGRESS_POLICING_UNK_MUL; - } - - if (hw_flag & 0x40) - { - *sw_flag |= FAL_INGRESS_POLICING_UNI; - } - - if (hw_flag & 0x80) - { - *sw_flag |= FAL_INGRESS_POLICING_MUL; - } -} - -static void -_isis_rate_ts_parse(fal_rate_mt_t sw, a_uint32_t * hw) -{ - if (FAL_RATE_MI_100US == sw) - { - *hw = 0; - } - else if (FAL_RATE_MI_1MS == sw) - { - *hw = 1; - } - else if (FAL_RATE_MI_10MS == sw) - { - *hw = 2; - } - else if (FAL_RATE_MI_100MS) - { - *hw = 3; - } - else - { - *hw = 0; - } -} - -static void -_isis_rate_ts_reparse(a_uint32_t hw, fal_rate_mt_t * sw) -{ - if (0 == hw) - { - *sw = FAL_RATE_MI_100US; - } - else if (1 == hw) - { - *sw = FAL_RATE_MI_1MS; - } - else if (2 == hw) - { - *sw = FAL_RATE_MI_10MS; - } - else - { - *sw = FAL_RATE_MI_100MS; - } -} - -static sw_error_t -_isis_rate_port_policer_set(a_uint32_t dev_id, fal_port_t port_id, - fal_port_policer_t * policer) -{ - sw_error_t rv; - a_uint32_t cir = 0x7fff, eir = 0x7fff, cbs = 0, ebs = 0, tmp, data[3] = { 0 }; - - HSL_DEV_ID_CHECK(dev_id); - - if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU)) - { - return SW_BAD_PARAM; - } - - data[0] = 0x18000000; - if (FAL_BYTE_BASED == policer->meter_unit) - { - if (A_TRUE == policer->c_enable) - { - cir = policer->cir >> 5; - policer->cir = cir << 5; - _isis_ingress_bs_byte_sw_to_hw(policer->cbs, &cbs); - _isis_ingress_bs_byte_hw_to_sw(cbs, &(policer->cbs)); - } - - if (A_TRUE == policer->e_enable) - { - eir = policer->eir >> 5; - policer->eir = eir << 5; - _isis_ingress_bs_byte_sw_to_hw(policer->ebs, &ebs); - _isis_ingress_bs_byte_hw_to_sw(ebs, &(policer->ebs)); - } - - SW_SET_REG_BY_FIELD(INGRESS_POLICER1, INGRESS_UNIT, 0, data[1]); - } - else if (FAL_FRAME_BASED == policer->meter_unit) - { - if (A_TRUE == policer->c_enable) - { - cir = (policer->cir * 2) / 125; - policer->cir = cir / 2 * 125 + cir % 2 * 63; - _isis_ingress_bs_frame_sw_to_hw(policer->cbs, &cbs); - _isis_ingress_bs_frame_hw_to_sw(cbs, &(policer->cbs)); - } - - if (A_TRUE == policer->e_enable) - { - eir = (policer->eir * 2) / 125; - policer->eir = eir / 2 * 125 + eir % 2 * 63; - _isis_ingress_bs_frame_sw_to_hw(policer->ebs, &ebs); - _isis_ingress_bs_frame_hw_to_sw(ebs, &(policer->ebs)); - } - - SW_SET_REG_BY_FIELD(INGRESS_POLICER1, INGRESS_UNIT, 1, data[1]); - } - else - { - return SW_BAD_PARAM; - } - - SW_SET_REG_BY_FIELD(INGRESS_POLICER0, INGRESS_CIR, cir, data[0]); - SW_SET_REG_BY_FIELD(INGRESS_POLICER0, INGRESS_CBS, cbs, data[0]); - SW_SET_REG_BY_FIELD(INGRESS_POLICER1, INGRESS_EIR, eir, data[1]); - SW_SET_REG_BY_FIELD(INGRESS_POLICER1, INGRESS_EBS, ebs, data[1]); - - if (A_TRUE == policer->combine_mode) - { - SW_SET_REG_BY_FIELD(INGRESS_POLICER0, RATE_MODE, 1, data[0]); - } - - if (A_TRUE == policer->deficit_en) - { - SW_SET_REG_BY_FIELD(INGRESS_POLICER1, INGRESS_BORROW, 1, data[1]); - } - - if (A_TRUE == policer->color_mode) - { - SW_SET_REG_BY_FIELD(INGRESS_POLICER1, INGRESS_CM, 1, data[1]); - } - - if (A_TRUE == policer->couple_flag) - { - SW_SET_REG_BY_FIELD(INGRESS_POLICER1, INGRESS_CF, 1, data[1]); - } - - _isis_rate_ts_parse(policer->c_meter_interval, &tmp); - SW_SET_REG_BY_FIELD(INGRESS_POLICER0, C_ING_TS, tmp, data[0]); - - _isis_rate_ts_parse(policer->e_meter_interval, &tmp); - SW_SET_REG_BY_FIELD(INGRESS_POLICER1, E_ING_TS, tmp, data[1]); - - _isis_rate_flag_parse(policer->c_rate_flag, &tmp); - data[2] = (tmp << 8) & 0xff00; - - _isis_rate_flag_parse(policer->e_rate_flag, &tmp); - data[2] |= (tmp & 0xff); - - HSL_REG_ENTRY_SET(rv, dev_id, INGRESS_POLICER0, port_id, - (a_uint8_t *) (&data[0]), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - - HSL_REG_ENTRY_SET(rv, dev_id, INGRESS_POLICER1, port_id, - (a_uint8_t *) (&data[1]), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - - HSL_REG_ENTRY_SET(rv, dev_id, INGRESS_POLICER2, port_id, - (a_uint8_t *) (&data[2]), sizeof (a_uint32_t)); - return rv; -} - -static sw_error_t -_isis_rate_port_policer_get(a_uint32_t dev_id, fal_port_t port_id, - fal_port_policer_t * policer) -{ - sw_error_t rv; - a_uint32_t unit, ts, cir, eir, cbs, ebs, data[3] = {0}; - - HSL_DEV_ID_CHECK(dev_id); - - if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU)) - { - return SW_BAD_PARAM; - } - - HSL_REG_ENTRY_GET(rv, dev_id, INGRESS_POLICER0, port_id, - (a_uint8_t *) (&data[0]), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - - HSL_REG_ENTRY_GET(rv, dev_id, INGRESS_POLICER1, port_id, - (a_uint8_t *) (&data[1]), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - - HSL_REG_ENTRY_GET(rv, dev_id, INGRESS_POLICER2, port_id, - (a_uint8_t *) (&data[2]), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - - SW_GET_FIELD_BY_REG(INGRESS_POLICER0, INGRESS_CIR, cir, data[0]); - SW_GET_FIELD_BY_REG(INGRESS_POLICER0, INGRESS_CBS, cbs, data[0]); - SW_GET_FIELD_BY_REG(INGRESS_POLICER1, INGRESS_EIR, eir, data[1]); - SW_GET_FIELD_BY_REG(INGRESS_POLICER1, INGRESS_EBS, ebs, data[1]); - SW_GET_FIELD_BY_REG(INGRESS_POLICER1, INGRESS_UNIT, unit, data[1]); - - policer->c_enable = A_TRUE; - if (0x7fff == cir) - { - policer->c_enable = A_FALSE; - cir = 0; - } - - policer->e_enable = A_TRUE; - if (0x7fff == eir) - { - policer->e_enable = A_FALSE; - eir = 0; - } - - if (unit) - { - policer->meter_unit = FAL_FRAME_BASED; - policer->cir = cir / 2 * 125 + cir % 2 * 63; - policer->eir = eir / 2 * 125 + eir % 2 * 63; - _isis_ingress_bs_frame_hw_to_sw(cbs, &(policer->cbs)); - _isis_ingress_bs_frame_hw_to_sw(ebs, &(policer->ebs)); - } - else - { - policer->meter_unit = FAL_BYTE_BASED; - policer->cir = cir << 5; - policer->eir = eir << 5; - _isis_ingress_bs_byte_hw_to_sw(cbs, &(policer->cbs)); - _isis_ingress_bs_byte_hw_to_sw(ebs, &(policer->ebs)); - } - - SW_GET_FIELD_BY_REG(INGRESS_POLICER0, RATE_MODE, policer->combine_mode, - data[0]); - SW_GET_FIELD_BY_REG(INGRESS_POLICER1, INGRESS_BORROW, policer->deficit_en, - data[1]); - SW_GET_FIELD_BY_REG(INGRESS_POLICER1, INGRESS_CF, policer->couple_flag, - data[1]); - SW_GET_FIELD_BY_REG(INGRESS_POLICER1, INGRESS_CM, policer->color_mode, - data[1]); - - ts = (data[2] >> 8) & 0xff; - _isis_rate_flag_reparse(ts, &(policer->c_rate_flag)); - - ts = data[2] & 0xff; - _isis_rate_flag_reparse(ts, &(policer->e_rate_flag)); - - SW_GET_FIELD_BY_REG(INGRESS_POLICER0, C_ING_TS, ts, data[0]); - _isis_rate_ts_reparse(ts, &(policer->c_meter_interval)); - - SW_GET_FIELD_BY_REG(INGRESS_POLICER1, E_ING_TS, ts, data[1]); - _isis_rate_ts_reparse(ts, &(policer->e_meter_interval)); - - return SW_OK; -} - -static sw_error_t -_isis_rate_port_shaper_set(a_uint32_t dev_id, fal_port_t port_id, - a_bool_t enable, fal_egress_shaper_t * shaper) -{ - sw_error_t rv; - a_uint32_t data, cir, eir, cbs = 0, ebs = 0; - - HSL_DEV_ID_CHECK(dev_id); - - if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU)) - { - return SW_BAD_PARAM; - } - - if (A_FALSE == enable) - { - aos_mem_zero(shaper, sizeof (fal_egress_shaper_t)); - - cir = 0x7fff; - eir = 0x7fff; - } - else - { - if (FAL_BYTE_BASED == shaper->meter_unit) - { - cir = shaper->cir >> 5; - shaper->cir = cir << 5; - - eir = shaper->eir >> 5; - shaper->eir = eir << 5; - - _isis_egress_bs_byte_sw_to_hw(shaper->cbs, &cbs); - _isis_egress_bs_byte_hw_to_sw(cbs, &(shaper->cbs)); - - _isis_egress_bs_byte_sw_to_hw(shaper->ebs, &ebs); - _isis_egress_bs_byte_hw_to_sw(ebs, &(shaper->ebs)); - - data = 0; - } - else if (FAL_FRAME_BASED == shaper->meter_unit) - { - cir = (shaper->cir * 2) / 125; - shaper->cir = cir / 2 * 125 + cir % 2 * 63; - - eir = (shaper->eir * 2) / 125; - shaper->eir = eir / 2 * 125 + eir % 2 * 63; - - _isis_egress_bs_frame_sw_to_hw(shaper->cbs, &cbs); - _isis_egress_bs_frame_hw_to_sw(cbs, &(shaper->cbs)); - - _isis_egress_bs_frame_sw_to_hw(shaper->ebs, &ebs); - _isis_egress_bs_frame_hw_to_sw(ebs, &(shaper->ebs)); - - data = 1; - } - else - { - return SW_BAD_PARAM; - } - - HSL_REG_FIELD_SET(rv, dev_id, EG_SHAPER7, port_id, EG_Q0_UNIT, - (a_uint8_t *) (&data), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - - data = 1; - HSL_REG_FIELD_SET(rv, dev_id, EG_SHAPER7, port_id, EG_PT, - (a_uint8_t *) (&data), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - } - - HSL_REG_FIELD_SET(rv, dev_id, EG_SHAPER0, port_id, EG_Q0_CIR, - (a_uint8_t *) (&cir), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - - HSL_REG_FIELD_SET(rv, dev_id, EG_SHAPER3, port_id, EG_Q0_EIR, - (a_uint8_t *) (&eir), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - - HSL_REG_FIELD_SET(rv, dev_id, EG_SHAPER6, port_id, EG_Q0_CBS, - (a_uint8_t *) (&cbs), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - - HSL_REG_FIELD_SET(rv, dev_id, EG_SHAPER6, port_id, EG_Q0_EBS, - (a_uint8_t *) (&ebs), sizeof (a_uint32_t)); - return rv; -} - -static sw_error_t -_isis_rate_port_shaper_get(a_uint32_t dev_id, fal_port_t port_id, - a_bool_t * enable, fal_egress_shaper_t * shaper) -{ - sw_error_t rv; - a_uint32_t data = 0, cir = 0, eir = 0, cbs = 0, ebs = 0; - - HSL_DEV_ID_CHECK(dev_id); - - if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU)) - { - return SW_BAD_PARAM; - } - - aos_mem_zero(shaper, sizeof (fal_egress_shaper_t)); - - HSL_REG_FIELD_GET(rv, dev_id, EG_SHAPER7, port_id, EG_PT, - (a_uint8_t *) (&data), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - - if (!data) - { - *enable = A_FALSE; - return SW_OK; - } - - HSL_REG_FIELD_GET(rv, dev_id, EG_SHAPER0, port_id, EG_Q0_CIR, - (a_uint8_t *) (&cir), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - - HSL_REG_FIELD_GET(rv, dev_id, EG_SHAPER3, port_id, EG_Q0_EIR, - (a_uint8_t *) (&eir), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - - HSL_REG_FIELD_GET(rv, dev_id, EG_SHAPER6, port_id, EG_Q0_CBS, - (a_uint8_t *) (&cbs), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - - HSL_REG_FIELD_GET(rv, dev_id, EG_SHAPER6, port_id, EG_Q0_EBS, - (a_uint8_t *) (&ebs), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - - if ((0x7fff == cir) && (0x7fff == eir)) - { - *enable = A_FALSE; - return SW_OK; - } - - *enable = A_TRUE; - HSL_REG_FIELD_GET(rv, dev_id, EG_SHAPER7, port_id, EG_Q0_UNIT, - (a_uint8_t *) (&data), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - - if (data) - { - shaper->meter_unit = FAL_FRAME_BASED; - shaper->cir = cir / 2 * 125 + cir % 2 * 63; - shaper->eir = eir / 2 * 125 + eir % 2 * 63; - _isis_egress_bs_frame_hw_to_sw(cbs, &(shaper->cbs)); - _isis_egress_bs_frame_hw_to_sw(ebs, &(shaper->ebs)); - } - else - { - shaper->meter_unit = FAL_BYTE_BASED; - shaper->cir = cir << 5; - shaper->eir = eir << 5; - _isis_egress_bs_byte_hw_to_sw(cbs, &(shaper->cbs)); - _isis_egress_bs_byte_hw_to_sw(ebs, &(shaper->ebs)); - } - - return SW_OK; -} - -static sw_error_t -_isis_rate_queue_shaper_set(a_uint32_t dev_id, fal_port_t port_id, - fal_queue_t queue_id, a_bool_t enable, - fal_egress_shaper_t * shaper) -{ - sw_error_t rv; - a_uint32_t unit = 0, data, cir, eir, cbs = 0, ebs = 0; - - HSL_DEV_ID_CHECK(dev_id); - - if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU)) - { - return SW_BAD_PARAM; - } - - rv = _isis_rate_port_queue_check(port_id, queue_id); - SW_RTN_ON_ERROR(rv); - - if (A_FALSE == enable) - { - aos_mem_zero(shaper, sizeof (fal_egress_shaper_t)); - - cir = 0x7fff; - eir = 0x7fff; - } - else - { - if (FAL_BYTE_BASED == shaper->meter_unit) - { - cir = shaper->cir >> 5; - shaper->cir = cir << 5; - - eir = shaper->eir >> 5; - shaper->eir = eir << 5; - - _isis_egress_bs_byte_sw_to_hw(shaper->cbs, &cbs); - _isis_egress_bs_byte_hw_to_sw(cbs, &(shaper->cbs)); - - _isis_egress_bs_byte_sw_to_hw(shaper->ebs, &ebs); - _isis_egress_bs_byte_hw_to_sw(ebs, &(shaper->ebs)); - - unit = 0; - } - else if (FAL_FRAME_BASED == shaper->meter_unit) - { - cir = (shaper->cir * 2) / 125; - shaper->cir = cir / 2 * 125 + cir % 2 * 63; - - eir = (shaper->eir * 2) / 125; - shaper->eir = eir / 2 * 125 + eir % 2 * 63; - - _isis_egress_bs_frame_sw_to_hw(shaper->cbs, &cbs); - _isis_egress_bs_frame_hw_to_sw(cbs, &(shaper->cbs)); - - _isis_egress_bs_frame_sw_to_hw(shaper->ebs, &ebs); - _isis_egress_bs_frame_hw_to_sw(ebs, &(shaper->ebs)); - - unit = 1; - } - - data = 0; - HSL_REG_FIELD_SET(rv, dev_id, EG_SHAPER7, port_id, EG_PT, - (a_uint8_t *) (&data), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - } - - if (0 == queue_id) - { - HSL_REG_FIELD_SET(rv, dev_id, EG_SHAPER0, port_id, EG_Q0_CIR, - (a_uint8_t *) (&cir), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - - HSL_REG_FIELD_SET(rv, dev_id, EG_SHAPER3, port_id, EG_Q0_EIR, - (a_uint8_t *) (&eir), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - - HSL_REG_FIELD_SET(rv, dev_id, EG_SHAPER6, port_id, EG_Q0_CBS, - (a_uint8_t *) (&cbs), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - - HSL_REG_FIELD_SET(rv, dev_id, EG_SHAPER6, port_id, EG_Q0_EBS, - (a_uint8_t *) (&ebs), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - - HSL_REG_FIELD_SET(rv, dev_id, EG_SHAPER7, port_id, EG_Q0_UNIT, - (a_uint8_t *) (&unit), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - } - else if (1 == queue_id) - { - HSL_REG_FIELD_SET(rv, dev_id, EG_SHAPER0, port_id, EG_Q1_CIR, - (a_uint8_t *) (&cir), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - - HSL_REG_FIELD_SET(rv, dev_id, EG_SHAPER3, port_id, EG_Q1_EIR, - (a_uint8_t *) (&eir), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - - HSL_REG_FIELD_SET(rv, dev_id, EG_SHAPER6, port_id, EG_Q1_CBS, - (a_uint8_t *) (&cbs), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - - HSL_REG_FIELD_SET(rv, dev_id, EG_SHAPER6, port_id, EG_Q1_EBS, - (a_uint8_t *) (&ebs), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - - HSL_REG_FIELD_SET(rv, dev_id, EG_SHAPER7, port_id, EG_Q1_UNIT, - (a_uint8_t *) (&unit), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - } - else if (2 == queue_id) - { - HSL_REG_FIELD_SET(rv, dev_id, EG_SHAPER1, port_id, EG_Q2_CIR, - (a_uint8_t *) (&cir), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - - HSL_REG_FIELD_SET(rv, dev_id, EG_SHAPER4, port_id, EG_Q2_EIR, - (a_uint8_t *) (&eir), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - - HSL_REG_FIELD_SET(rv, dev_id, EG_SHAPER6, port_id, EG_Q2_CBS, - (a_uint8_t *) (&cbs), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - - HSL_REG_FIELD_SET(rv, dev_id, EG_SHAPER6, port_id, EG_Q2_EBS, - (a_uint8_t *) (&ebs), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - - HSL_REG_FIELD_SET(rv, dev_id, EG_SHAPER7, port_id, EG_Q2_UNIT, - (a_uint8_t *) (&unit), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - } - else if (3 == queue_id) - { - HSL_REG_FIELD_SET(rv, dev_id, EG_SHAPER1, port_id, EG_Q3_CIR, - (a_uint8_t *) (&cir), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - - HSL_REG_FIELD_SET(rv, dev_id, EG_SHAPER4, port_id, EG_Q3_EIR, - (a_uint8_t *) (&eir), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - - HSL_REG_FIELD_SET(rv, dev_id, EG_SHAPER6, port_id, EG_Q3_CBS, - (a_uint8_t *) (&cbs), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - - HSL_REG_FIELD_SET(rv, dev_id, EG_SHAPER6, port_id, EG_Q3_EBS, - (a_uint8_t *) (&ebs), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - - HSL_REG_FIELD_SET(rv, dev_id, EG_SHAPER7, port_id, EG_Q3_UNIT, - (a_uint8_t *) (&unit), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - } - else if (4 == queue_id) - { - HSL_REG_FIELD_SET(rv, dev_id, EG_SHAPER2, port_id, EG_Q4_CIR, - (a_uint8_t *) (&cir), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - - HSL_REG_FIELD_SET(rv, dev_id, EG_SHAPER5, port_id, EG_Q4_EIR, - (a_uint8_t *) (&eir), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - - HSL_REG_FIELD_SET(rv, dev_id, EG_SHAPER7, port_id, EG_Q4_CBS, - (a_uint8_t *) (&cbs), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - - HSL_REG_FIELD_SET(rv, dev_id, EG_SHAPER7, port_id, EG_Q4_EBS, - (a_uint8_t *) (&ebs), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - - HSL_REG_FIELD_SET(rv, dev_id, EG_SHAPER7, port_id, EG_Q4_UNIT, - (a_uint8_t *) (&unit), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - } - else - { - HSL_REG_FIELD_SET(rv, dev_id, EG_SHAPER2, port_id, EG_Q5_CIR, - (a_uint8_t *) (&cir), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - - HSL_REG_FIELD_SET(rv, dev_id, EG_SHAPER5, port_id, EG_Q5_EIR, - (a_uint8_t *) (&eir), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - - HSL_REG_FIELD_SET(rv, dev_id, EG_SHAPER7, port_id, EG_Q5_CBS, - (a_uint8_t *) (&cbs), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - - HSL_REG_FIELD_SET(rv, dev_id, EG_SHAPER7, port_id, EG_Q5_EBS, - (a_uint8_t *) (&ebs), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - - HSL_REG_FIELD_SET(rv, dev_id, EG_SHAPER7, port_id, EG_Q5_UNIT, - (a_uint8_t *) (&unit), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - } - - return SW_OK; -} - -static sw_error_t -_isis_rate_queue_shaper_get(a_uint32_t dev_id, fal_port_t port_id, - fal_queue_t queue_id, a_bool_t * enable, - fal_egress_shaper_t * shaper) -{ - sw_error_t rv; - a_uint32_t data = 0, cir = 0, eir = 0, cbs = 0, ebs = 0; - - HSL_DEV_ID_CHECK(dev_id); - - if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU)) - { - return SW_BAD_PARAM; - } - - rv = _isis_rate_port_queue_check(port_id, queue_id); - SW_RTN_ON_ERROR(rv); - - aos_mem_zero(shaper, sizeof (fal_egress_shaper_t)); - - HSL_REG_FIELD_GET(rv, dev_id, EG_SHAPER7, port_id, EG_PT, - (a_uint8_t *) (&data), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - - if (data) - { - *enable = A_FALSE; - return SW_OK; - } - - if (0 == queue_id) - { - HSL_REG_FIELD_GET(rv, dev_id, EG_SHAPER0, port_id, EG_Q0_CIR, - (a_uint8_t *) (&cir), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - - HSL_REG_FIELD_GET(rv, dev_id, EG_SHAPER3, port_id, EG_Q0_EIR, - (a_uint8_t *) (&eir), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - - HSL_REG_FIELD_GET(rv, dev_id, EG_SHAPER6, port_id, EG_Q0_CBS, - (a_uint8_t *) (&cbs), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - - HSL_REG_FIELD_GET(rv, dev_id, EG_SHAPER6, port_id, EG_Q0_EBS, - (a_uint8_t *) (&ebs), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - - HSL_REG_FIELD_GET(rv, dev_id, EG_SHAPER7, port_id, EG_Q0_UNIT, - (a_uint8_t *) (&data), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - } - else if (1 == queue_id) - { - HSL_REG_FIELD_GET(rv, dev_id, EG_SHAPER0, port_id, EG_Q1_CIR, - (a_uint8_t *) (&cir), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - - HSL_REG_FIELD_GET(rv, dev_id, EG_SHAPER3, port_id, EG_Q1_EIR, - (a_uint8_t *) (&eir), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - - HSL_REG_FIELD_GET(rv, dev_id, EG_SHAPER6, port_id, EG_Q1_CBS, - (a_uint8_t *) (&cbs), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - - HSL_REG_FIELD_GET(rv, dev_id, EG_SHAPER6, port_id, EG_Q1_EBS, - (a_uint8_t *) (&ebs), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - - HSL_REG_FIELD_GET(rv, dev_id, EG_SHAPER7, port_id, EG_Q1_UNIT, - (a_uint8_t *) (&data), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - } - else if (2 == queue_id) - { - HSL_REG_FIELD_GET(rv, dev_id, EG_SHAPER1, port_id, EG_Q2_CIR, - (a_uint8_t *) (&cir), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - - HSL_REG_FIELD_GET(rv, dev_id, EG_SHAPER4, port_id, EG_Q2_EIR, - (a_uint8_t *) (&eir), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - - HSL_REG_FIELD_GET(rv, dev_id, EG_SHAPER6, port_id, EG_Q2_CBS, - (a_uint8_t *) (&cbs), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - - HSL_REG_FIELD_GET(rv, dev_id, EG_SHAPER6, port_id, EG_Q2_EBS, - (a_uint8_t *) (&ebs), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - - HSL_REG_FIELD_GET(rv, dev_id, EG_SHAPER7, port_id, EG_Q2_UNIT, - (a_uint8_t *) (&data), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - } - else if (3 == queue_id) - { - HSL_REG_FIELD_GET(rv, dev_id, EG_SHAPER1, port_id, EG_Q3_CIR, - (a_uint8_t *) (&cir), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - - HSL_REG_FIELD_GET(rv, dev_id, EG_SHAPER4, port_id, EG_Q3_EIR, - (a_uint8_t *) (&eir), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - - HSL_REG_FIELD_GET(rv, dev_id, EG_SHAPER6, port_id, EG_Q3_CBS, - (a_uint8_t *) (&cbs), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - - HSL_REG_FIELD_GET(rv, dev_id, EG_SHAPER6, port_id, EG_Q3_EBS, - (a_uint8_t *) (&ebs), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - - HSL_REG_FIELD_GET(rv, dev_id, EG_SHAPER7, port_id, EG_Q3_UNIT, - (a_uint8_t *) (&data), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - } - else if (4 == queue_id) - { - HSL_REG_FIELD_GET(rv, dev_id, EG_SHAPER2, port_id, EG_Q4_CIR, - (a_uint8_t *) (&cir), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - - HSL_REG_FIELD_GET(rv, dev_id, EG_SHAPER5, port_id, EG_Q4_EIR, - (a_uint8_t *) (&eir), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - - HSL_REG_FIELD_GET(rv, dev_id, EG_SHAPER7, port_id, EG_Q4_CBS, - (a_uint8_t *) (&cbs), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - - HSL_REG_FIELD_GET(rv, dev_id, EG_SHAPER7, port_id, EG_Q4_EBS, - (a_uint8_t *) (&ebs), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - - HSL_REG_FIELD_GET(rv, dev_id, EG_SHAPER7, port_id, EG_Q4_UNIT, - (a_uint8_t *) (&data), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - } - else - { - HSL_REG_FIELD_GET(rv, dev_id, EG_SHAPER2, port_id, EG_Q5_CIR, - (a_uint8_t *) (&cir), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - - HSL_REG_FIELD_GET(rv, dev_id, EG_SHAPER5, port_id, EG_Q5_EIR, - (a_uint8_t *) (&eir), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - - HSL_REG_FIELD_GET(rv, dev_id, EG_SHAPER7, port_id, EG_Q5_CBS, - (a_uint8_t *) (&cbs), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - - HSL_REG_FIELD_GET(rv, dev_id, EG_SHAPER7, port_id, EG_Q5_EBS, - (a_uint8_t *) (&ebs), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - - HSL_REG_FIELD_GET(rv, dev_id, EG_SHAPER7, port_id, EG_Q5_UNIT, - (a_uint8_t *) (&data), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - } - - if ((0x7fff == cir) && (0x7fff == eir)) - { - *enable = A_FALSE; - return SW_OK; - } - - *enable = A_TRUE; - if (data) - { - shaper->meter_unit = FAL_FRAME_BASED; - shaper->cir = cir / 2 * 125 + cir % 2 * 63; - shaper->eir = eir / 2 * 125 + eir % 2 * 63; - _isis_egress_bs_frame_hw_to_sw(cbs, &(shaper->cbs)); - _isis_egress_bs_frame_hw_to_sw(ebs, &(shaper->ebs)); - } - else - { - shaper->meter_unit = FAL_BYTE_BASED; - shaper->cir = cir << 5; - shaper->eir = eir << 5; - _isis_egress_bs_byte_hw_to_sw(cbs, &(shaper->cbs)); - _isis_egress_bs_byte_hw_to_sw(ebs, &(shaper->ebs)); - } - - return SW_OK; -} - -static sw_error_t -_isis_rate_acl_policer_set(a_uint32_t dev_id, a_uint32_t policer_id, - fal_acl_policer_t * policer) -{ - sw_error_t rv; - a_uint32_t ts, cir, eir, cbs = 0, ebs = 0, addr, data[2] = { 0 }; - - HSL_DEV_ID_CHECK(dev_id); - - if (ISIS_MAX_POLICER_ID < policer_id) - { - return SW_BAD_PARAM; - } - - if (A_TRUE == policer->counter_mode) - { - addr = ACL_POLICER_CNT_SEL_ADDR; - data[0] = 0x1; - HSL_REG_FIELD_GEN_SET(rv, dev_id, addr, 1, policer_id, - (a_uint8_t *) (&data[0]), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - - addr = ACL_POLICER_CNT_MODE_ADDR; - if (FAL_FRAME_BASED == policer->meter_unit) - { - data[0] = 0x0; - } - else - { - data[0] = 0x1; - } - HSL_REG_FIELD_GEN_SET(rv, dev_id, addr, 1, policer_id, - (a_uint8_t *) (&data[0]), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - - addr = ACL_POLICER_CNT_RST_ADDR; - data[0] = 0x1; - HSL_REG_FIELD_GEN_SET(rv, dev_id, addr, 1, policer_id, - (a_uint8_t *) (&data[0]), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - - data[0] = 0x0; - HSL_REG_FIELD_GEN_SET(rv, dev_id, addr, 1, policer_id, - (a_uint8_t *) (&data[0]), sizeof (a_uint32_t)); - return rv; - } - - addr = ACL_POLICER_CNT_SEL_ADDR; - data[0] = 0x0; - HSL_REG_FIELD_GEN_SET(rv, dev_id, addr, 1, policer_id, - (a_uint8_t *) (&data[0]), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - - if (FAL_BYTE_BASED == policer->meter_unit) - { - cir = policer->cir >> 5; - policer->cir = cir << 5; - - eir = policer->eir >> 5; - policer->eir = eir << 5; - - _isis_ingress_bs_byte_sw_to_hw(policer->cbs, &cbs); - _isis_ingress_bs_byte_hw_to_sw(cbs, &(policer->cbs)); - - _isis_ingress_bs_byte_sw_to_hw(policer->ebs, &ebs); - _isis_ingress_bs_byte_hw_to_sw(ebs, &(policer->ebs)); - - SW_SET_REG_BY_FIELD(ACL_POLICER1, ACL_UNIT, 0, data[1]); - } - else if (FAL_FRAME_BASED == policer->meter_unit) - { - cir = (policer->cir * 2) / 125; - policer->cir = cir / 2 * 125 + cir % 2 * 63; - - eir = (policer->eir * 2) / 125; - policer->eir = eir / 2 * 125 + eir % 2 * 63; - - _isis_ingress_bs_frame_sw_to_hw(policer->cbs, &cbs); - _isis_ingress_bs_frame_hw_to_sw(cbs, &(policer->cbs)); - - _isis_ingress_bs_frame_sw_to_hw(policer->ebs, &ebs); - _isis_ingress_bs_frame_hw_to_sw(ebs, &(policer->ebs)); - - SW_SET_REG_BY_FIELD(ACL_POLICER1, ACL_UNIT, 1, data[1]); - } - else - { - return SW_BAD_PARAM; - } - - SW_SET_REG_BY_FIELD(ACL_POLICER0, ACL_CIR, cir, data[0]); - SW_SET_REG_BY_FIELD(ACL_POLICER0, ACL_CBS, cbs, data[0]); - SW_SET_REG_BY_FIELD(ACL_POLICER1, ACL_EIR, eir, data[1]); - SW_SET_REG_BY_FIELD(ACL_POLICER1, ACL_EBS, ebs, data[1]); - - if (A_TRUE == policer->deficit_en) - { - SW_SET_REG_BY_FIELD(ACL_POLICER1, ACL_BORROW, 1, data[1]); - } - - if (A_TRUE == policer->color_mode) - { - SW_SET_REG_BY_FIELD(ACL_POLICER1, ACL_CM, 1, data[1]); - } - - if (A_TRUE == policer->couple_flag) - { - SW_SET_REG_BY_FIELD(ACL_POLICER1, ACL_CF, 1, data[1]); - } - - _isis_rate_ts_parse(policer->meter_interval, &ts); - SW_SET_REG_BY_FIELD(ACL_POLICER1, ACL_TS, ts, data[1]); - - HSL_REG_ENTRY_SET(rv, dev_id, ACL_POLICER0, policer_id, - (a_uint8_t *) (&data[0]), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - - HSL_REG_ENTRY_SET(rv, dev_id, ACL_POLICER1, policer_id, - (a_uint8_t *) (&data[1]), sizeof (a_uint32_t)); - - return rv; -} - -static sw_error_t -_isis_rate_acl_policer_get(a_uint32_t dev_id, a_uint32_t policer_id, - fal_acl_policer_t * policer) -{ - sw_error_t rv; - a_uint32_t unit, ts, cir, eir, cbs, ebs, addr, data[2] = {0}; - - HSL_DEV_ID_CHECK(dev_id); - - if (ISIS_MAX_POLICER_ID < policer_id) - { - return SW_BAD_PARAM; - } - - aos_mem_zero(policer, sizeof (policer)); - - addr = ACL_POLICER_CNT_SEL_ADDR; - HSL_REG_FIELD_GEN_GET(rv, dev_id, addr, 1, policer_id, - (a_uint8_t *) (&data[0]), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - - if (data[0]) - { - policer->counter_mode = A_TRUE; - - addr = ACL_POLICER_CNT_MODE_ADDR; - HSL_REG_FIELD_GEN_GET(rv, dev_id, addr, 1, policer_id, - (a_uint8_t *) (&data[0]), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - - if (data[0]) - { - policer->meter_unit = FAL_BYTE_BASED; - } - else - { - policer->meter_unit = FAL_FRAME_BASED; - } - - HSL_REG_ENTRY_GET(rv, dev_id, ACL_COUNTER0, policer_id, - (a_uint8_t *) (&data[0]), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - - HSL_REG_ENTRY_GET(rv, dev_id, ACL_COUNTER1, policer_id, - (a_uint8_t *) (&data[1]), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - - policer->counter_low = data[0]; - policer->counter_high = data[1]; - - return SW_OK; - } - - HSL_REG_ENTRY_GET(rv, dev_id, ACL_POLICER0, policer_id, - (a_uint8_t *) (&data[0]), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - - HSL_REG_ENTRY_GET(rv, dev_id, ACL_POLICER1, policer_id, - (a_uint8_t *) (&data[1]), sizeof (a_uint32_t)); - - SW_GET_FIELD_BY_REG(ACL_POLICER0, ACL_CIR, cir, data[0]); - SW_GET_FIELD_BY_REG(ACL_POLICER0, ACL_CBS, cbs, data[0]); - SW_GET_FIELD_BY_REG(ACL_POLICER1, ACL_EIR, eir, data[1]); - SW_GET_FIELD_BY_REG(ACL_POLICER1, ACL_EBS, ebs, data[1]); - SW_GET_FIELD_BY_REG(ACL_POLICER1, ACL_UNIT, unit, data[1]); - if (unit) - { - policer->meter_unit = FAL_FRAME_BASED; - policer->cir = cir / 2 * 125 + cir % 2 * 63; - policer->eir = eir / 2 * 125 + eir % 2 * 63; - _isis_ingress_bs_frame_hw_to_sw(cbs, &(policer->cbs)); - _isis_ingress_bs_frame_hw_to_sw(ebs, &(policer->ebs)); - - } - else - { - policer->meter_unit = FAL_BYTE_BASED; - policer->cir = cir << 5; - policer->eir = eir << 5; - _isis_ingress_bs_byte_hw_to_sw(cbs, &(policer->cbs)); - _isis_ingress_bs_byte_hw_to_sw(ebs, &(policer->ebs)); - } - - SW_GET_FIELD_BY_REG(ACL_POLICER1, ACL_CF, policer->couple_flag, data[1]); - SW_GET_FIELD_BY_REG(ACL_POLICER1, ACL_CM, policer->color_mode, data[1]); - - SW_GET_FIELD_BY_REG(ACL_POLICER1, ACL_TS, ts, data[1]); - _isis_rate_ts_reparse(ts, &(policer->meter_interval)); - - return SW_OK; -} - -sw_error_t -_isis_rate_port_add_rate_byte_set(a_uint32_t dev_id, fal_port_t port_id, - a_uint32_t number) -{ - a_uint32_t val = number; - sw_error_t rv; - - HSL_DEV_ID_CHECK(dev_id); - - if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU)) - { - return SW_BAD_PARAM; - } - - if (val>255) - return SW_BAD_PARAM; - - HSL_REG_FIELD_SET(rv, dev_id, INGRESS_POLICER0, port_id, ADD_RATE_BYTE, - (a_uint8_t *) (&val), sizeof (a_uint32_t)); - - return rv; -} - -sw_error_t -_isis_rate_port_add_rate_byte_get(a_uint32_t dev_id, fal_port_t port_id, - a_uint32_t *number) -{ - a_uint32_t val = 0; - sw_error_t rv = SW_OK; - - HSL_DEV_ID_CHECK(dev_id); - - if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU)) - { - return SW_BAD_PARAM; - } - - - HSL_REG_FIELD_GET(rv, dev_id, INGRESS_POLICER0, port_id, ADD_RATE_BYTE, - (a_uint8_t *) (&val), sizeof (a_uint32_t)); - *number = val; - - return rv; -} - -/** - * @brief Set port ingress policer parameters on one particular port. - * @details Comments: - The granularity of speed is 32kbps or 62.5fps. - Because of hardware granularity function will return actual speed in hardware. - When disable port ingress policer input parameter speed is meaningless. - * @param[in] dev_id device id - * @param[in] port_id port id - * @param[in] policer port ingress policer parameter - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -isis_rate_port_policer_set(a_uint32_t dev_id, fal_port_t port_id, - fal_port_policer_t * policer) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _isis_rate_port_policer_set(dev_id, port_id, policer); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Get port ingress policer parameters on one particular port. - * @details Comments: - The granularity of speed is 32kbps or 62.5fps. - Because of hardware granularity function will return actual speed in hardware. - When disable port ingress policer input parameter speed is meaningless. - * @param[in] dev_id device id - * @param[in] port_id port id - * @param[out] policer port ingress policer parameter - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -isis_rate_port_policer_get(a_uint32_t dev_id, fal_port_t port_id, - fal_port_policer_t * policer) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _isis_rate_port_policer_get(dev_id, port_id, policer); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Set port egress shaper parameters on one particular port. - * @details Comments: - The granularity of speed is 32kbps or 62.5fps. - Because of hardware granularity function will return actual speed in hardware. - When disable port egress shaper parameters is meaningless. - * @param[in] port_id port id - * @param[in] enable A_TRUE or A_FALSE - * @param[in] shaper port egress shaper parameter - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -isis_rate_port_shaper_set(a_uint32_t dev_id, fal_port_t port_id, - a_bool_t enable, fal_egress_shaper_t * shaper) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _isis_rate_port_shaper_set(dev_id, port_id, enable, shaper); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Get port egress shaper parameters on one particular port. - * @details Comments: - The granularity of speed is 32kbps or 62.5fps. - Because of hardware granularity function will return actual speed in hardware. - When disable port egress shaper parameters is meaningless. - * @param[in] dev_id device id - * @param[in] port_id port id - * @param[out] enable A_TRUE or A_FALSE - * @param[out] shaper port egress shaper parameter - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -isis_rate_port_shaper_get(a_uint32_t dev_id, fal_port_t port_id, - a_bool_t * enable, fal_egress_shaper_t * shaper) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _isis_rate_port_shaper_get(dev_id, port_id, enable, shaper); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Set queue egress shaper parameters on one particular port. - * @details Comments: - The granularity of speed is 32kbps or 62.5fps. - Because of hardware granularity function will return actual speed in hardware. - When disable queue egress shaper parameters is meaningless. - * @param[in] port_id port id - * @param[in] queue_id queue id - * @param[in] enable A_TRUE or A_FALSE - * @param[in] shaper port egress shaper parameter - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -isis_rate_queue_shaper_set(a_uint32_t dev_id, fal_port_t port_id, - fal_queue_t queue_id, a_bool_t enable, - fal_egress_shaper_t * shaper) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _isis_rate_queue_shaper_set(dev_id, port_id, queue_id, enable, shaper); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Get queue egress shaper parameters on one particular port. - * @details Comments: - The granularity of speed is 32kbps or 62.5fps. - Because of hardware granularity function will return actual speed in hardware. - When disable queue egress shaper parameters is meaningless. - * @param[in] port_id port id - * @param[in] queue_id queue id - * @param[out] enable A_TRUE or A_FALSE - * @param[out] shaper port egress shaper parameter - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -isis_rate_queue_shaper_get(a_uint32_t dev_id, fal_port_t port_id, - fal_queue_t queue_id, a_bool_t * enable, - fal_egress_shaper_t * shaper) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _isis_rate_queue_shaper_get(dev_id, port_id, queue_id, enable, shaper); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Set ACL ingress policer parameters. - * @details Comments: - The granularity of speed is 32kbps or 62.5fps. - Because of hardware granularity function will return actual speed in hardware. - * @param[in] dev_id device id - * @param[in] policer_id ACL policer id - * @param[in] policer ACL ingress policer parameters - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -isis_rate_acl_policer_set(a_uint32_t dev_id, a_uint32_t policer_id, - fal_acl_policer_t * policer) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _isis_rate_acl_policer_set(dev_id, policer_id, policer); - HSL_API_UNLOCK; - return rv; -} - - - -/** - * @brief Get ACL ingress policer parameters. - * @details Comments: - The granularity of speed is 32kbps or 62.5fps. - Because of hardware granularity function will return actual speed in hardware. - * @param[in] dev_id device id - * @param[in] policer_id ACL policer id - * @param[in] policer ACL ingress policer parameters - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -isis_rate_acl_policer_get(a_uint32_t dev_id, a_uint32_t policer_id, - fal_acl_policer_t * policer) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _isis_rate_acl_policer_get(dev_id, policer_id, policer); - HSL_API_UNLOCK; - return rv; -} - -HSL_LOCAL sw_error_t -isis_rate_port_add_rate_byte_set(a_uint32_t dev_id, fal_port_t port_id, - a_uint32_t number) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _isis_rate_port_add_rate_byte_set(dev_id, port_id, number); - HSL_API_UNLOCK; - return rv; -} - -HSL_LOCAL sw_error_t -isis_rate_port_add_rate_byte_get(a_uint32_t dev_id, fal_port_t port_id, - a_uint32_t *number) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _isis_rate_port_add_rate_byte_get(dev_id, port_id, number); - HSL_API_UNLOCK; - return rv; -} - -sw_error_t -isis_rate_init(a_uint32_t dev_id) -{ - HSL_DEV_ID_CHECK(dev_id); - -#ifndef HSL_STANDALONG - { - hsl_api_t *p_api; - - SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id)); - - p_api->rate_port_policer_set = isis_rate_port_policer_set; - p_api->rate_port_policer_get = isis_rate_port_policer_get; - p_api->rate_port_shaper_set = isis_rate_port_shaper_set; - p_api->rate_port_shaper_get = isis_rate_port_shaper_get; - p_api->rate_queue_shaper_set = isis_rate_queue_shaper_set; - p_api->rate_queue_shaper_get = isis_rate_queue_shaper_get; - p_api->rate_acl_policer_set = isis_rate_acl_policer_set; - p_api->rate_acl_policer_get = isis_rate_acl_policer_get; - p_api->rate_port_add_rate_byte_set = isis_rate_port_add_rate_byte_set; - p_api->rate_port_add_rate_byte_get = isis_rate_port_add_rate_byte_get; - - } -#endif - - return SW_OK; -} - -/** - * @} - */ - diff --git a/feeds/ipq807x/qca-ssdk/src/src/hsl/isis/isis_reg_access.c b/feeds/ipq807x/qca-ssdk/src/src/hsl/isis/isis_reg_access.c deleted file mode 100755 index bdcfc9ed0..000000000 --- a/feeds/ipq807x/qca-ssdk/src/src/hsl/isis/isis_reg_access.c +++ /dev/null @@ -1,507 +0,0 @@ -/* - * Copyright (c) 2012, 2016, The Linux Foundation. All rights reserved. - * Permission to use, copy, modify, and/or distribute this software for - * any purpose with or without fee is hereby granted, provided that the - * above copyright notice and this permission notice appear in all copies. - * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES - * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR - * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES - * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN - * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT - * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. - */ - - -#include "sw.h" -#include "hsl.h" -#include "hsl_dev.h" -#include "sd.h" -#include "isis_reg_access.h" - -static hsl_access_mode reg_mode; - -#if defined(API_LOCK) -static aos_lock_t mdio_lock; -#define MDIO_LOCKER_INIT aos_lock_init(&mdio_lock) -#define MDIO_LOCKER_LOCK aos_lock(&mdio_lock) -#define MDIO_LOCKER_UNLOCK aos_unlock(&mdio_lock) -#else -#define MDIO_LOCKER_INIT -#define MDIO_LOCKER_LOCK -#define MDIO_LOCKER_UNLOCK -#endif - -#if defined(REG_ACCESS_SPEEDUP) -static a_uint32_t mdio_base_addr = 0xffffffff; -#endif - -int -isis_reg_config_header (a_uint8_t *header, a_uint8_t wr_flag, - a_uint32_t reg_addr, a_uint8_t cmd_len, - a_uint8_t *val, a_uint32_t seq_num) -{ - athrs_header_t athrs_header; - athrs_header_regcmd_t reg_cmd; - a_uint16_t head_offset = ISIS_HEADER_CMD_LEN + ISIS_HEADER_DATA_LEN; - a_uint8_t buf[ISIS_HEADER_CMD_LEN+ISIS_HEADER_LEN+ISIS_HEADER_MAX_DATA_LEN] = { 0 }; - a_uint16_t data2_offset = ISIS_HEADER_CMD_LEN + ISIS_HEADER_DATA_LEN + ISIS_HEADER_LEN; - - aos_mem_set(&athrs_header, 0, sizeof(athrs_header)); - aos_mem_set(®_cmd, 0, sizeof(reg_cmd)); - aos_mem_set(buf, 0, sizeof(buf)); - - /*fill atheros header*/ - athrs_header.version = 2; - athrs_header.priority = 0; - athrs_header.type = 1;/*READ_WRITE_REG*/ - athrs_header.broadcast = 0; - athrs_header.from_cpu = 1; - athrs_header.port_num = 0; - - /*fill in 4 byte type atheros header witch specific header type - must config reg 0x98*/ - buf[head_offset] = (ATHRS_HEADER_4BYTE_VAL & 0xff00)>>8; - buf[head_offset+1] = ATHRS_HEADER_4BYTE_VAL & 0xff; - - buf[head_offset+2] = athrs_header.type; - buf[head_offset+2] |= athrs_header.priority << 3; - buf[head_offset+2] |= athrs_header.version << 6; - buf[head_offset+3] = athrs_header.port_num; - buf[head_offset+3] |= athrs_header.from_cpu << 7; - - /*fill reg cmd*/ - if(cmd_len > ISIS_HEADER_MAX_DATA_LEN) - cmd_len = ISIS_HEADER_MAX_DATA_LEN;//maximum data length is16 bytes - reg_cmd.reg_addr = reg_addr&0x7fffc; /*bit 0:18, lower 2 bits must be 0*/ - reg_cmd.cmd_len = cmd_len; - reg_cmd.cmd = wr_flag; - reg_cmd.check_code = 5; - reg_cmd.seq_num = seq_num; - - /*bit[0:18], reg addr*/ - buf[0] = reg_cmd.reg_addr & 0xff; - buf[1] = (reg_cmd.reg_addr & 0xff00) >> 8; - buf[2] = (reg_cmd.reg_addr & 0x70000) >> 16; - /*bit[19:23], cmd data length*/ - buf[2] |= reg_cmd.cmd_len << 3; - /*bit[28], cmd type, read/write*/ - buf[3] = reg_cmd.cmd << 4; - /*bit[29:31], check code, must be 3'b101*/ - buf[3] |= reg_cmd.check_code << 5; - /*bit[32:63], sequence num*/ - buf[4] = (reg_cmd.seq_num & 0xff); - buf[5] = (reg_cmd.seq_num & 0xff00) >> 8; - buf[6] = (reg_cmd.seq_num & 0xff0000) >> 16; - buf[7] = (reg_cmd.seq_num & 0xff000000) >> 24; - - if(!wr_flag)//write - { - aos_mem_copy(buf+ ISIS_HEADER_CMD_LEN , val, ISIS_HEADER_DATA_LEN); - if (cmd_len >4 ) - aos_mem_copy(buf+ data2_offset , val + ISIS_HEADER_DATA_LEN, cmd_len - ISIS_HEADER_DATA_LEN); - } - - aos_mem_copy(header, buf, sizeof(buf)); - return 0; -} - - -sw_error_t isis_reg_parser_header_skb(a_uint8_t *header_buf, athrs_cmd_resp_t *cmd_resp) -{ - a_uint16_t data2_offset = ISIS_HEADER_CMD_LEN + ISIS_HEADER_DATA_LEN + ISIS_HEADER_LEN; - aos_mem_set(cmd_resp, 0, sizeof(cmd_resp)); - cmd_resp->len = header_buf[2] >> 3; - if (cmd_resp->len > ISIS_HEADER_MAX_DATA_LEN) - return SW_BAD_LEN; - - cmd_resp->seq = 0; - cmd_resp->seq = header_buf[4]; - cmd_resp->seq |= header_buf[5] << 8; - cmd_resp->seq |= header_buf[6] << 16; - cmd_resp->seq |= header_buf[7] << 24; - - aos_mem_copy (cmd_resp->data, (header_buf + ISIS_HEADER_CMD_LEN), ISIS_HEADER_DATA_LEN); - if (cmd_resp->len > 4) - aos_mem_copy ((cmd_resp->data+ISIS_HEADER_DATA_LEN), (header_buf + data2_offset), cmd_resp->len-4); - return SW_OK; -} - -static sw_error_t -_isis_mdio_reg_get(a_uint32_t dev_id, a_uint32_t reg_addr, - a_uint8_t value[], a_uint32_t value_len) -{ -#if 0 - a_uint32_t reg_word_addr; - a_uint32_t phy_addr, reg_val; - a_uint16_t phy_val, tmp_val; - a_uint8_t phy_reg; - sw_error_t rv; -#else - a_uint32_t reg_val; -#endif - - if (value_len != sizeof (a_uint32_t)) - return SW_BAD_LEN; - -#if 0 - /* change reg_addr to 16-bit word address, 32-bit aligned */ - reg_word_addr = (reg_addr & 0xfffffffc) >> 1; - - /* configure register high address */ - phy_addr = 0x18; - phy_reg = 0x0; - phy_val = (a_uint16_t) ((reg_word_addr >> 8) & 0x3ff); /* bit16-8 of reg address */ - -#if defined(REG_ACCESS_SPEEDUP) - if (phy_val != mdio_base_addr) - { - rv = sd_reg_mdio_set(dev_id, phy_addr, phy_reg, phy_val); - SW_RTN_ON_ERROR(rv); - - mdio_base_addr = phy_val; - } -#else - rv = sd_reg_mdio_set(dev_id, phy_addr, phy_reg, phy_val); - SW_RTN_ON_ERROR(rv); -#endif - - /* For some registers such as MIBs, since it is read/clear, we should */ - /* read the lower 16-bit register then the higher one */ - - /* read register in lower address */ - phy_addr = 0x10 | ((reg_word_addr >> 5) & 0x7); /* bit7-5 of reg address */ - phy_reg = (a_uint8_t) (reg_word_addr & 0x1f); /* bit4-0 of reg address */ - rv = sd_reg_mdio_get(dev_id, phy_addr, phy_reg, &tmp_val); - SW_RTN_ON_ERROR(rv); - reg_val = tmp_val; - - /* read register in higher address */ - reg_word_addr++; - phy_addr = 0x10 | ((reg_word_addr >> 5) & 0x7); /* bit7-5 of reg address */ - phy_reg = (a_uint8_t) (reg_word_addr & 0x1f); /* bit4-0 of reg address */ - rv = sd_reg_mdio_get(dev_id, phy_addr, phy_reg, &tmp_val); - SW_RTN_ON_ERROR(rv); - reg_val |= (((a_uint32_t)tmp_val) << 16); - -#else - reg_val = sd_reg_mii_get(dev_id, reg_addr); -#endif - aos_mem_copy(value, ®_val, sizeof (a_uint32_t)); - - return SW_OK; -} - -static sw_error_t -_isis_mdio_reg_set(a_uint32_t dev_id, a_uint32_t reg_addr, a_uint8_t value[], - a_uint32_t value_len) -{ -#if 0 - a_uint32_t reg_word_addr; - a_uint32_t phy_addr, reg_val; - a_uint16_t phy_val; - a_uint8_t phy_reg; - sw_error_t rv; -#else - a_uint32_t reg_val = 0; -#endif - - if (value_len != sizeof (a_uint32_t)) - return SW_BAD_LEN; - - aos_mem_copy(®_val, value, sizeof (a_uint32_t)); - -#if 0 - /* change reg_addr to 16-bit word address, 32-bit aligned */ - reg_word_addr = (reg_addr & 0xfffffffc) >> 1; - - /* configure register high address */ - phy_addr = 0x18; - phy_reg = 0x0; - phy_val = (a_uint16_t) ((reg_word_addr >> 8) & 0x3ff); /* bit16-8 of reg address */ - -#if defined(REG_ACCESS_SPEEDUP) - if (phy_val != mdio_base_addr) - { - rv = sd_reg_mdio_set(dev_id, phy_addr, phy_reg, phy_val); - SW_RTN_ON_ERROR(rv); - - mdio_base_addr = phy_val; - } -#else - rv = sd_reg_mdio_set(dev_id, phy_addr, phy_reg, phy_val); - SW_RTN_ON_ERROR(rv); -#endif - - /* For some registers such as ARL and VLAN, since they include BUSY bit */ - /* in higher address, we should write the lower 16-bit register then the */ - /* higher one */ - - /* write register in lower address */ - phy_addr = 0x10 | ((reg_word_addr >> 5) & 0x7); /* bit7-5 of reg address */ - phy_reg = (a_uint8_t) (reg_word_addr & 0x1f); /* bit4-0 of reg address */ - phy_val = (a_uint16_t) (reg_val & 0xffff); - rv = sd_reg_mdio_set(dev_id, phy_addr, phy_reg, phy_val); - SW_RTN_ON_ERROR(rv); - - /* write register in higher address */ - reg_word_addr++; - phy_addr = 0x10 | ((reg_word_addr >> 5) & 0x7); /* bit7-5 of reg address */ - phy_reg = (a_uint8_t) (reg_word_addr & 0x1f); /* bit4-0 of reg address */ - phy_val = (a_uint16_t) ((reg_val >> 16) & 0xffff); - rv = sd_reg_mdio_set(dev_id, phy_addr, phy_reg, phy_val); - SW_RTN_ON_ERROR(rv); - -#else - sd_reg_mii_set(dev_id, reg_addr, reg_val); -#endif - return SW_OK; -} - -sw_error_t -isis_phy_get(a_uint32_t dev_id, a_uint32_t phy_addr, - a_uint32_t reg, a_uint16_t * value) -{ - sw_error_t rv; - - MDIO_LOCKER_LOCK; - rv = sd_reg_mdio_get(dev_id, phy_addr, reg, value); - MDIO_LOCKER_UNLOCK; - return rv; -} - -sw_error_t -isis_phy_set(a_uint32_t dev_id, a_uint32_t phy_addr, - a_uint32_t reg, a_uint16_t value) -{ - sw_error_t rv; - - MDIO_LOCKER_LOCK; - rv = sd_reg_mdio_set(dev_id, phy_addr, reg, value); - MDIO_LOCKER_UNLOCK; - return rv; -} - -sw_error_t -isis_reg_get(a_uint32_t dev_id, a_uint32_t reg_addr, a_uint8_t value[], - a_uint32_t value_len) -{ - sw_error_t rv; - - MDIO_LOCKER_LOCK; - if (HSL_MDIO == reg_mode) - { - rv = _isis_mdio_reg_get(dev_id, reg_addr, value, value_len); - } - else - { - rv = sd_reg_hdr_get(dev_id, reg_addr, value, value_len); - } - MDIO_LOCKER_UNLOCK; - - return rv; -} - -sw_error_t -isis_reg_set(a_uint32_t dev_id, a_uint32_t reg_addr, a_uint8_t value[], - a_uint32_t value_len) -{ - sw_error_t rv; - - MDIO_LOCKER_LOCK; - if (HSL_MDIO == reg_mode) - { - rv = _isis_mdio_reg_set(dev_id, reg_addr, value, value_len); - } - else - { - rv = sd_reg_hdr_set(dev_id, reg_addr, value, value_len); - } - MDIO_LOCKER_UNLOCK; - - return rv; -} - -sw_error_t -isis_reg_field_get(a_uint32_t dev_id, a_uint32_t reg_addr, - a_uint32_t bit_offset, a_uint32_t field_len, - a_uint8_t value[], a_uint32_t value_len) -{ - a_uint32_t reg_val = 0; - - if ((bit_offset >= 32 || (field_len > 32)) || (field_len == 0)) - return SW_OUT_OF_RANGE; - - if (value_len != sizeof (a_uint32_t)) - return SW_BAD_LEN; - - SW_RTN_ON_ERROR(isis_reg_get(dev_id, reg_addr, (a_uint8_t *) & reg_val, sizeof (a_uint32_t))); - - *((a_uint32_t *) value) = SW_REG_2_FIELD(reg_val, bit_offset, field_len); - return SW_OK; -} - -sw_error_t -isis_reg_field_set(a_uint32_t dev_id, a_uint32_t reg_addr, - a_uint32_t bit_offset, a_uint32_t field_len, - const a_uint8_t value[], a_uint32_t value_len) -{ - a_uint32_t reg_val = 0; - a_uint32_t field_val = *((a_uint32_t *) value); - - if ((bit_offset >= 32 || (field_len > 32)) || (field_len == 0)) - return SW_OUT_OF_RANGE; - - if (value_len != sizeof (a_uint32_t)) - return SW_BAD_LEN; - - SW_RTN_ON_ERROR(isis_reg_get(dev_id, reg_addr, (a_uint8_t *) & reg_val, sizeof (a_uint32_t))); - - SW_REG_SET_BY_FIELD_U32(reg_val, field_val, bit_offset, field_len); - - SW_RTN_ON_ERROR(isis_reg_set(dev_id, reg_addr, (a_uint8_t *) & reg_val, sizeof (a_uint32_t))); - - return SW_OK; -} - -static sw_error_t -_isis_regsiter_dump(a_uint32_t dev_id,a_uint32_t register_idx, fal_reg_dump_t * reg_dump) -{ - sw_error_t rv = SW_OK; - typedef struct { - a_uint32_t reg_base; - a_uint32_t reg_end; - char name[30]; - } regdump; - - regdump reg_dumps[8] = - { - {0x0, 0xE4, "0.Global control registers"}, - {0x100, 0x168, "1.EEE control registers"}, - {0x200, 0x270, "2.Parser control registers"}, - {0x400, 0x474, "3.ACL control registers"}, - {0x600, 0x718, "4.Lookup control registers"}, - {0x800, 0xb70, "5.QM control registers"}, - {0xc00, 0xc80, "6.PKT edit control registers"}, - {0x820, 0x820, "7.QM debug registers"} - }; - - a_uint32_t dump_addr, reg_count, reg_val = 0; - switch (register_idx) - { - case 0: - case 1: - case 2: - case 3: - case 4: - case 5: - case 6: - reg_count = 0; - for (dump_addr = reg_dumps[register_idx].reg_base; dump_addr <= reg_dumps[register_idx].reg_end; reg_count++) - { - rv = isis_reg_get(dev_id, dump_addr, (a_uint8_t *) & reg_val, sizeof (a_uint32_t)); - reg_dump->reg_value[reg_count] = reg_val; - dump_addr += 4; - } - reg_dump->reg_count = reg_count; - reg_dump->reg_base = reg_dumps[register_idx].reg_base; - reg_dump->reg_end = reg_dumps[register_idx].reg_end; - snprintf((char *)reg_dump->reg_name,sizeof(reg_dump->reg_name),"%s",reg_dumps[register_idx].name); - break; - default: - return SW_BAD_PARAM; - } - - return rv; -} - -static sw_error_t -_isis_debug_regsiter_dump(a_uint32_t dev_id,fal_debug_reg_dump_t * dbg_reg_dump) -{ - sw_error_t rv = SW_OK; - a_uint32_t reg; - a_uint32_t reg_count, reg_val = 0; - - reg_count = 0; - - for(reg=0;reg<=0x1F;reg++) - { - isis_reg_set(dev_id, 0x820, (a_uint8_t *) & reg, sizeof (a_uint32_t)); - rv = isis_reg_get(dev_id, 0x824, (a_uint8_t *) & reg_val, sizeof (a_uint32_t)); - dbg_reg_dump->reg_value[reg_count] = reg_val; - dbg_reg_dump->reg_addr[reg_count] = reg; - reg_count++; - } - dbg_reg_dump->reg_count = reg_count; - - snprintf((char *)dbg_reg_dump->reg_name,sizeof(dbg_reg_dump->reg_name),"QM debug registers"); - - return rv; -} - - -/** - * @brief dump registers. - * @param[in] dev_id device id - * @param[in] register_idx register group id - * @param[out] reg_dump register dump result - * @return SW_OK or error code - */ -sw_error_t -isis_regsiter_dump(a_uint32_t dev_id,a_uint32_t register_idx, fal_reg_dump_t * reg_dump) -{ - sw_error_t rv = SW_OK; - - FAL_API_LOCK; - rv = _isis_regsiter_dump(dev_id,register_idx,reg_dump); - FAL_API_UNLOCK; - return rv; -} - -/** - * @brief dump registers. - * @param[in] dev_id device id - * @param[out] reg_dump debug register dump - * @return SW_OK or error code - */ -sw_error_t -isis_debug_regsiter_dump(a_uint32_t dev_id, fal_debug_reg_dump_t * dbg_reg_dump) -{ - sw_error_t rv = SW_OK; - - FAL_API_LOCK; - rv = _isis_debug_regsiter_dump(dev_id,dbg_reg_dump); - FAL_API_UNLOCK; - return rv; -} - - -sw_error_t -isis_reg_access_init(a_uint32_t dev_id, hsl_access_mode mode) -{ - hsl_api_t *p_api; - - MDIO_LOCKER_INIT; - reg_mode = mode; - - SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id)); - p_api->phy_get = isis_phy_get; - p_api->phy_set = isis_phy_set; - p_api->reg_get = isis_reg_get; - p_api->reg_set = isis_reg_set; - p_api->reg_field_get = isis_reg_field_get; - p_api->reg_field_set = isis_reg_field_set; - p_api->register_dump = isis_regsiter_dump; - p_api->debug_register_dump = isis_debug_regsiter_dump; - - return SW_OK; -} - -sw_error_t -isis_access_mode_set(a_uint32_t dev_id, hsl_access_mode mode) -{ - reg_mode = mode; - return SW_OK; - -} - diff --git a/feeds/ipq807x/qca-ssdk/src/src/hsl/isis/isis_sec.c b/feeds/ipq807x/qca-ssdk/src/src/hsl/isis/isis_sec.c deleted file mode 100755 index 912d09c3c..000000000 --- a/feeds/ipq807x/qca-ssdk/src/src/hsl/isis/isis_sec.c +++ /dev/null @@ -1,787 +0,0 @@ -/* - * Copyright (c) 2012, 2016, The Linux Foundation. All rights reserved. - * Permission to use, copy, modify, and/or distribute this software for - * any purpose with or without fee is hereby granted, provided that the - * above copyright notice and this permission notice appear in all copies. - * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES - * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR - * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES - * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN - * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT - * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. - */ - - -/** - * @defgroup isis_sec ISIS_SEC - * @{ - */ -#include "sw.h" -#include "hsl.h" -#include "hsl_dev.h" -#include "hsl_port_prop.h" -#include "isis_sec.h" -#include "isis_reg.h" - -#define NORM_CTRL0_ADDR 0x0200 -#define NORM_CTRL1_ADDR 0x0204 -#define NORM_CTRL2_ADDR 0x0208 -#define NORM_CTRL3_ADDR 0x0c00 - -static sw_error_t -_isis_sec_norm_item_set(a_uint32_t dev_id, fal_norm_item_t item, void *value) -{ - sw_error_t rv; - fal_fwd_cmd_t cmd; - a_bool_t enable; - a_uint32_t addr, offset, len, reg = 0, val; - - HSL_DEV_ID_CHECK(dev_id); - - cmd = *((fal_fwd_cmd_t *) value); - enable = *((a_bool_t *) value); - val = *((a_uint32_t *) value); - - len = 1; - switch (item) - { - case FAL_NORM_MAC_RESV_VID_CMD: - addr = NORM_CTRL0_ADDR; - offset = 0; - goto cmd_chk; - - case FAL_NORM_MAC_INVALID_SRC_ADDR_CMD: - addr = NORM_CTRL1_ADDR; - offset = 20; - goto cmd_chk; - - case FAL_NORM_IP_INVALID_VER_CMD: - addr = NORM_CTRL0_ADDR; - offset = 1; - goto cmd_chk; - - case FAL_NROM_IP_SAME_ADDR_CMD: - addr = NORM_CTRL0_ADDR; - offset = 2; - goto cmd_chk; - break; - - case FAL_NROM_IP_TTL_CHANGE_STATUS: - addr = NORM_CTRL3_ADDR; - offset = 11; - goto sts_chk; - - case FAL_NROM_IP_TTL_VALUE: - addr = NORM_CTRL3_ADDR; - offset = 12; - len = 8; - goto set_reg; - - case FAL_NROM_IP4_INVALID_HL_CMD: - addr = NORM_CTRL0_ADDR; - offset = 3; - goto cmd_chk; - - case FAL_NROM_IP4_HDR_OPTIONS_CMD: - addr = NORM_CTRL0_ADDR; - offset = 4; - len = 2; - goto s_cmd_chk; - - case FAL_NROM_IP4_INVALID_DF_CMD: - addr = NORM_CTRL0_ADDR; - offset = 7; - goto cmd_chk; - - case FAL_NROM_IP4_FRAG_OFFSET_MIN_LEN_CMD: - addr = NORM_CTRL0_ADDR; - offset = 8; - goto cmd_chk; - - case FAL_NROM_IP4_FRAG_OFFSET_MIN_SIZE: - addr = NORM_CTRL1_ADDR; - offset = 24; - len = 8; - goto set_reg; - - case FAL_NROM_IP4_FRAG_OFFSET_MAX_LEN_CMD: - addr = NORM_CTRL0_ADDR; - offset = 9; - goto cmd_chk; - - case FAL_NROM_IP4_INVALID_FRAG_OFFSET_CMD: - addr = NORM_CTRL0_ADDR; - offset = 10; - goto cmd_chk; - - case FAL_NROM_IP4_INVALID_SIP_CMD: - addr = NORM_CTRL0_ADDR; - offset = 11; - len = 1; - goto cmd_chk; - - case FAL_NROM_IP4_INVALID_DIP_CMD: - addr = NORM_CTRL0_ADDR; - offset = 12; - goto cmd_chk; - - case FAL_NROM_IP4_INVALID_CHKSUM_CMD: - addr = NORM_CTRL0_ADDR; - offset = 13; - goto cmd_chk; - - case FAL_NROM_IP4_INVALID_PL_CMD: - addr = NORM_CTRL1_ADDR; - offset = 19; - goto cmd_chk; - - case FAL_NROM_IP4_DF_CLEAR_STATUS: - addr = NORM_CTRL3_ADDR; - offset = 9; - goto sts_chk; - - case FAL_NROM_IP4_IPID_RANDOM_STATUS: - addr = NORM_CTRL3_ADDR; - offset = 10; - goto sts_chk; - - case FAL_NROM_IP6_INVALID_DIP_CMD: - addr = NORM_CTRL1_ADDR; - offset = 16; - goto cmd_chk; - - case FAL_NROM_IP6_INVALID_SIP_CMD: - addr = NORM_CTRL1_ADDR; - offset = 17; - goto cmd_chk; - - case FAL_NROM_IP6_INVALID_PL_CMD: - addr = NORM_CTRL1_ADDR; - offset = 18; - goto cmd_chk; - - case FAL_NROM_TCP_BLAT_CMD: - addr = NORM_CTRL0_ADDR; - offset = 14; - goto cmd_chk; - - case FAL_NROM_TCP_INVALID_HL_CMD: - addr = NORM_CTRL0_ADDR; - offset = 15; - goto cmd_chk; - - case FAL_NROM_TCP_MIN_HDR_SIZE: - addr = NORM_CTRL1_ADDR; - offset = 12; - len = 4; - goto set_reg; - - case FAL_NROM_TCP_INVALID_SYN_CMD: - addr = NORM_CTRL0_ADDR; - offset = 16; - goto cmd_chk; - break; - - case FAL_NROM_TCP_SU_BLOCK_CMD: - addr = NORM_CTRL0_ADDR; - offset = 17; - goto cmd_chk; - - case FAL_NROM_TCP_SP_BLOCK_CMD: - addr = NORM_CTRL0_ADDR; - offset = 18; - goto cmd_chk; - - case FAL_NROM_TCP_SAP_BLOCK_CMD: - addr = NORM_CTRL0_ADDR; - offset = 19; - goto cmd_chk; - - case FAL_NROM_TCP_XMAS_SCAN_CMD: - addr = NORM_CTRL0_ADDR; - offset = 20; - goto cmd_chk; - - case FAL_NROM_TCP_NULL_SCAN_CMD: - addr = NORM_CTRL0_ADDR; - offset = 21; - goto cmd_chk; - - case FAL_NROM_TCP_SR_BLOCK_CMD: - addr = NORM_CTRL0_ADDR; - offset = 22; - goto cmd_chk; - - case FAL_NROM_TCP_SF_BLOCK_CMD: - addr = NORM_CTRL0_ADDR; - offset = 23; - goto cmd_chk; - - case FAL_NROM_TCP_SAR_BLOCK_CMD: - addr = NORM_CTRL0_ADDR; - offset = 24; - goto cmd_chk; - - case FAL_NROM_TCP_RST_SCAN_CMD: - addr = NORM_CTRL0_ADDR; - offset = 25; - goto cmd_chk; - - case FAL_NROM_TCP_SYN_WITH_DATA_CMD: - addr = NORM_CTRL0_ADDR; - offset = 26; - goto cmd_chk; - - case FAL_NROM_TCP_RST_WITH_DATA_CMD: - addr = NORM_CTRL0_ADDR; - offset = 27; - goto cmd_chk; - - case FAL_NROM_TCP_FA_BLOCK_CMD: - addr = NORM_CTRL0_ADDR; - offset = 28; - goto cmd_chk; - - case FAL_NROM_TCP_PA_BLOCK_CMD: - addr = NORM_CTRL0_ADDR; - offset = 29; - goto cmd_chk; - - case FAL_NROM_TCP_UA_BLOCK_CMD: - addr = NORM_CTRL1_ADDR; - offset = 0; - goto cmd_chk; - - case FAL_NROM_TCP_INVALID_CHKSUM_CMD: - addr = NORM_CTRL1_ADDR; - offset = 1; - goto cmd_chk; - - case FAL_NROM_TCP_INVALID_URGPTR_CMD: - addr = NORM_CTRL1_ADDR; - offset = 2; - goto cmd_chk; - - case FAL_NROM_TCP_INVALID_OPTIONS_CMD: - addr = NORM_CTRL1_ADDR; - offset = 3; - goto cmd_chk; - - case FAL_NROM_UDP_BLAT_CMD: - addr = NORM_CTRL1_ADDR; - offset = 4; - goto cmd_chk; - - case FAL_NROM_UDP_INVALID_LEN_CMD: - addr = NORM_CTRL1_ADDR; - offset = 5; - goto cmd_chk; - - case FAL_NROM_UDP_INVALID_CHKSUM_CMD: - addr = NORM_CTRL1_ADDR; - offset = 6; - goto cmd_chk; - - case FAL_NROM_ICMP4_PING_PL_EXCEED_CMD: - addr = NORM_CTRL1_ADDR; - offset = 7; - goto cmd_chk; - - case FAL_NROM_ICMP6_PING_PL_EXCEED_CMD: - addr = NORM_CTRL1_ADDR; - offset = 8; - goto cmd_chk; - - case FAL_NROM_ICMP4_PING_FRAG_CMD: - addr = NORM_CTRL1_ADDR; - offset = 9; - goto cmd_chk; - - case FAL_NROM_ICMP6_PING_FRAG_CMD: - addr = NORM_CTRL1_ADDR; - offset = 10; - goto cmd_chk; - - case FAL_NROM_ICMP4_PING_MAX_PL_VALUE: - addr = NORM_CTRL2_ADDR; - offset = 0; - len = 14; - goto set_reg; - - case FAL_NROM_ICMP6_PING_MAX_PL_VALUE: - addr = NORM_CTRL2_ADDR; - offset = 16; - len = 14; - goto set_reg; - - default: - return SW_BAD_PARAM; - } - -sts_chk: - if (A_TRUE == enable) - { - val = 1; - } - else if (A_FALSE == enable) - { - val = 0; - } - else - { - return SW_BAD_PARAM; - } - goto set_reg; - -s_cmd_chk: - if (FAL_MAC_FRWRD == cmd) - { - val = 0; - } - else if (FAL_MAC_DROP == cmd) - { - val = 3; - } - else if (FAL_MAC_RDT_TO_CPU == cmd) - { - val = 2; - } - else - { - return SW_BAD_PARAM; - } - goto set_reg; - -cmd_chk: - if (FAL_MAC_FRWRD == cmd) - { - val = 0; - } - else if (FAL_MAC_DROP == cmd) - { - val = 1; - } - else - { - return SW_BAD_PARAM; - } - -set_reg: - HSL_REG_ENTRY_GEN_GET(rv, dev_id, addr, sizeof (a_uint32_t), - (a_uint8_t *) (®), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - - SW_REG_SET_BY_FIELD_U32(reg, val, offset, len); - - HSL_REG_ENTRY_GEN_SET(rv, dev_id, addr, sizeof (a_uint32_t), - (a_uint8_t *) (®), sizeof (a_uint32_t)); - return rv; -} - -static sw_error_t -_isis_sec_norm_item_get(a_uint32_t dev_id, fal_norm_item_t item, void *value) -{ - sw_error_t rv; - a_uint32_t addr, offset, len, reg = 0, val; - a_uint32_t status_chk = 0, val_chk = 0, scmd_chk = 0; - - HSL_DEV_ID_CHECK(dev_id); - - len = 1; - switch (item) - { - case FAL_NORM_MAC_RESV_VID_CMD: - addr = NORM_CTRL0_ADDR; - offset = 0; - break; - - case FAL_NORM_MAC_INVALID_SRC_ADDR_CMD: - addr = NORM_CTRL1_ADDR; - offset = 20; - break; - - case FAL_NORM_IP_INVALID_VER_CMD: - addr = NORM_CTRL0_ADDR; - offset = 1; - break; - - case FAL_NROM_IP_SAME_ADDR_CMD: - addr = NORM_CTRL0_ADDR; - offset = 2; - break; - - case FAL_NROM_IP_TTL_CHANGE_STATUS: - addr = NORM_CTRL3_ADDR; - offset = 11; - status_chk = 1; - break; - - case FAL_NROM_IP_TTL_VALUE: - addr = NORM_CTRL3_ADDR; - offset = 12; - len = 8; - val_chk = 1; - break; - - case FAL_NROM_IP4_INVALID_HL_CMD: - addr = NORM_CTRL0_ADDR; - offset = 3; - break; - - case FAL_NROM_IP4_HDR_OPTIONS_CMD: - addr = NORM_CTRL0_ADDR; - offset = 4; - len = 2; - scmd_chk = 1; - break; - - case FAL_NROM_IP4_INVALID_DF_CMD: - addr = NORM_CTRL0_ADDR; - offset = 7; - break; - - case FAL_NROM_IP4_FRAG_OFFSET_MIN_LEN_CMD: - addr = NORM_CTRL0_ADDR; - offset = 8; - break; - - case FAL_NROM_IP4_FRAG_OFFSET_MIN_SIZE: - addr = NORM_CTRL1_ADDR; - offset = 24; - len = 8; - val_chk = 1; - break; - - case FAL_NROM_IP4_FRAG_OFFSET_MAX_LEN_CMD: - addr = NORM_CTRL0_ADDR; - offset = 9; - break; - - case FAL_NROM_IP4_INVALID_FRAG_OFFSET_CMD: - addr = NORM_CTRL0_ADDR; - offset = 10; - break; - - case FAL_NROM_IP4_INVALID_SIP_CMD: - addr = NORM_CTRL0_ADDR; - offset = 11; - len = 1; - break; - - case FAL_NROM_IP4_INVALID_DIP_CMD: - addr = NORM_CTRL0_ADDR; - offset = 12; - break; - - case FAL_NROM_IP4_INVALID_CHKSUM_CMD: - addr = NORM_CTRL0_ADDR; - offset = 13; - break; - - case FAL_NROM_IP4_INVALID_PL_CMD: - addr = NORM_CTRL1_ADDR; - offset = 19; - break; - - case FAL_NROM_IP4_DF_CLEAR_STATUS: - addr = NORM_CTRL3_ADDR; - offset = 9; - status_chk = 1; - break; - - case FAL_NROM_IP4_IPID_RANDOM_STATUS: - addr = NORM_CTRL3_ADDR; - offset = 10; - status_chk = 1; - break; - - case FAL_NROM_IP6_INVALID_DIP_CMD: - addr = NORM_CTRL1_ADDR; - offset = 16; - break; - - case FAL_NROM_IP6_INVALID_SIP_CMD: - addr = NORM_CTRL1_ADDR; - offset = 17; - break; - - case FAL_NROM_IP6_INVALID_PL_CMD: - addr = NORM_CTRL1_ADDR; - offset = 18; - break; - - case FAL_NROM_TCP_BLAT_CMD: - addr = NORM_CTRL0_ADDR; - offset = 14; - break; - - case FAL_NROM_TCP_INVALID_HL_CMD: - addr = NORM_CTRL0_ADDR; - offset = 15; - break; - - case FAL_NROM_TCP_MIN_HDR_SIZE: - addr = NORM_CTRL1_ADDR; - offset = 12; - len = 4; - val_chk = 1; - break; - - case FAL_NROM_TCP_INVALID_SYN_CMD: - addr = NORM_CTRL0_ADDR; - offset = 16; - break; - - case FAL_NROM_TCP_SU_BLOCK_CMD: - addr = NORM_CTRL0_ADDR; - offset = 17; - break; - - case FAL_NROM_TCP_SP_BLOCK_CMD: - addr = NORM_CTRL0_ADDR; - offset = 18; - break; - - case FAL_NROM_TCP_SAP_BLOCK_CMD: - addr = NORM_CTRL0_ADDR; - offset = 19; - break; - - case FAL_NROM_TCP_XMAS_SCAN_CMD: - addr = NORM_CTRL0_ADDR; - offset = 20; - break; - - case FAL_NROM_TCP_NULL_SCAN_CMD: - addr = NORM_CTRL0_ADDR; - offset = 21; - break; - - case FAL_NROM_TCP_SR_BLOCK_CMD: - addr = NORM_CTRL0_ADDR; - offset = 22; - break; - - case FAL_NROM_TCP_SF_BLOCK_CMD: - addr = NORM_CTRL0_ADDR; - offset = 23; - break; - - case FAL_NROM_TCP_SAR_BLOCK_CMD: - addr = NORM_CTRL0_ADDR; - offset = 24; - break; - - case FAL_NROM_TCP_RST_SCAN_CMD: - addr = NORM_CTRL0_ADDR; - offset = 25; - break; - - case FAL_NROM_TCP_SYN_WITH_DATA_CMD: - addr = NORM_CTRL0_ADDR; - offset = 26; - break; - - case FAL_NROM_TCP_RST_WITH_DATA_CMD: - addr = NORM_CTRL0_ADDR; - offset = 27; - break; - - case FAL_NROM_TCP_FA_BLOCK_CMD: - addr = NORM_CTRL0_ADDR; - offset = 28; - break; - - case FAL_NROM_TCP_PA_BLOCK_CMD: - addr = NORM_CTRL0_ADDR; - offset = 29; - break; - - case FAL_NROM_TCP_UA_BLOCK_CMD: - addr = NORM_CTRL1_ADDR; - offset = 0; - break; - - case FAL_NROM_TCP_INVALID_CHKSUM_CMD: - addr = NORM_CTRL1_ADDR; - offset = 1; - break; - - case FAL_NROM_TCP_INVALID_URGPTR_CMD: - addr = NORM_CTRL1_ADDR; - offset = 2; - break; - - case FAL_NROM_TCP_INVALID_OPTIONS_CMD: - addr = NORM_CTRL1_ADDR; - offset = 3; - break; - - case FAL_NROM_UDP_BLAT_CMD: - addr = NORM_CTRL1_ADDR; - offset = 4; - break; - - case FAL_NROM_UDP_INVALID_LEN_CMD: - addr = NORM_CTRL1_ADDR; - offset = 5; - break; - - case FAL_NROM_UDP_INVALID_CHKSUM_CMD: - addr = NORM_CTRL1_ADDR; - offset = 6; - break; - - case FAL_NROM_ICMP4_PING_PL_EXCEED_CMD: - addr = NORM_CTRL1_ADDR; - offset = 7; - break; - - case FAL_NROM_ICMP6_PING_PL_EXCEED_CMD: - addr = NORM_CTRL1_ADDR; - offset = 8; - break; - - case FAL_NROM_ICMP4_PING_FRAG_CMD: - addr = NORM_CTRL1_ADDR; - offset = 9; - break; - - case FAL_NROM_ICMP6_PING_FRAG_CMD: - addr = NORM_CTRL1_ADDR; - offset = 10; - break; - - case FAL_NROM_ICMP4_PING_MAX_PL_VALUE: - addr = NORM_CTRL2_ADDR; - offset = 0; - len = 14; - val_chk = 1; - break; - - case FAL_NROM_ICMP6_PING_MAX_PL_VALUE: - addr = NORM_CTRL2_ADDR; - offset = 16; - len = 14; - val_chk = 1; - break; - - default: - return SW_BAD_PARAM; - } - - HSL_REG_ENTRY_GEN_GET(rv, dev_id, addr, sizeof (a_uint32_t), - (a_uint8_t *) (®), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - - SW_FIELD_GET_BY_REG_U32(reg, val, offset, len); - - if (val_chk) - { - *((a_uint32_t *) value) = val; - } - else if (status_chk) - { - if (val) - { - *((a_bool_t *) value) = A_TRUE; - } - else - { - *((a_bool_t *) value) = A_FALSE; - } - } - else if (scmd_chk) - { - if (2 == val) - { - *((fal_fwd_cmd_t *) value) = FAL_MAC_RDT_TO_CPU; - } - else if (3 == val) - { - *((fal_fwd_cmd_t *) value) = FAL_MAC_DROP; - } - else - { - *((fal_fwd_cmd_t *) value) = FAL_MAC_FRWRD; - } - } - else - { - if (val) - { - *((fal_fwd_cmd_t *) value) = FAL_MAC_DROP; - } - else - { - *((fal_fwd_cmd_t *) value) = FAL_MAC_FRWRD; - } - } - - return SW_OK; -} - -/** - * @brief Set normalization particular item types value. - * @details Comments: - * This operation will set normalization item values on a particular device. - * The prototye of value based on the item type. - * @param[in] dev_id device id - * @param[in] item normalizaton item type - * @param[in] value normalizaton item value - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -isis_sec_norm_item_set(a_uint32_t dev_id, fal_norm_item_t item, void *value) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _isis_sec_norm_item_set(dev_id, item, value); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Get normalization particular item types value. - * @details Comments: - * This operation will set normalization item values on a particular device. - * The prototye of value based on the item type. - * @param[in] dev_id device id - * @param[in] item normalizaton item type - * @param[out] value normalizaton item value - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -isis_sec_norm_item_get(a_uint32_t dev_id, fal_norm_item_t item, void *value) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _isis_sec_norm_item_get(dev_id, item, value); - HSL_API_UNLOCK; - return rv; -} - -sw_error_t -isis_sec_init(a_uint32_t dev_id) -{ - HSL_DEV_ID_CHECK(dev_id); - -#ifndef HSL_STANDALONG - { - hsl_api_t *p_api; - - SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id)); - p_api->sec_norm_item_set = isis_sec_norm_item_set; - p_api->sec_norm_item_get = isis_sec_norm_item_get; - } -#endif - - return SW_OK; -} - -/** - * @} - */ diff --git a/feeds/ipq807x/qca-ssdk/src/src/hsl/isis/isis_stp.c b/feeds/ipq807x/qca-ssdk/src/src/hsl/isis/isis_stp.c deleted file mode 100755 index 3d0581b97..000000000 --- a/feeds/ipq807x/qca-ssdk/src/src/hsl/isis/isis_stp.c +++ /dev/null @@ -1,193 +0,0 @@ -/* - * Copyright (c) 2012, 2016, The Linux Foundation. All rights reserved. - * Permission to use, copy, modify, and/or distribute this software for - * any purpose with or without fee is hereby granted, provided that the - * above copyright notice and this permission notice appear in all copies. - * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES - * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR - * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES - * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN - * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT - * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. - */ - - -/** - * @defgroup isis_stp ISIS_STP - * @{ - */ -#include "sw.h" -#include "hsl.h" -#include "hsl_dev.h" -#include "hsl_port_prop.h" -#include "isis_stp.h" -#include "isis_reg.h" - -#define ISIS_PORT_DISABLED 0 -#define ISIS_STP_BLOCKING 1 -#define ISIS_STP_LISTENING 2 -#define ISIS_STP_LEARNING 3 -#define ISIS_STP_FARWARDING 4 - -static sw_error_t -_isis_stp_port_state_set(a_uint32_t dev_id, a_uint32_t st_id, - fal_port_t port_id, fal_stp_state_t state) -{ - sw_error_t rv; - a_uint32_t val; - - HSL_DEV_ID_CHECK(dev_id); - - if (FAL_SINGLE_STP_ID != st_id) - { - return SW_BAD_PARAM; - } - - if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_EXCL_CPU)) - { - return SW_BAD_PARAM; - } - - switch (state) - { - case FAL_STP_BLOKING: - val = ISIS_STP_BLOCKING; - break; - case FAL_STP_LISTENING: - val = ISIS_STP_LISTENING; - break; - case FAL_STP_LEARNING: - val = ISIS_STP_LEARNING; - break; - case FAL_STP_FARWARDING: - val = ISIS_STP_FARWARDING; - break; - case FAL_STP_DISABLED: - val = ISIS_PORT_DISABLED; - break; - default: - return SW_BAD_PARAM; - } - - HSL_REG_FIELD_SET(rv, dev_id, PORT_LOOKUP_CTL, port_id, PORT_STATE, - (a_uint8_t *) (&val), sizeof (a_uint32_t)); - return rv; -} - -static sw_error_t -_isis_stp_port_state_get(a_uint32_t dev_id, a_uint32_t st_id, - fal_port_t port_id, fal_stp_state_t * state) -{ - sw_error_t rv; - a_uint32_t val = 0; - - HSL_DEV_ID_CHECK(dev_id); - - if (FAL_SINGLE_STP_ID != st_id) - { - return SW_BAD_PARAM; - } - - if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_EXCL_CPU)) - { - return SW_BAD_PARAM; - } - - HSL_REG_FIELD_GET(rv, dev_id, PORT_LOOKUP_CTL, port_id, PORT_STATE, - (a_uint8_t *) (&val), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - - switch (val) - { - case ISIS_STP_BLOCKING: - *state = FAL_STP_BLOKING; - break; - case ISIS_STP_LISTENING: - *state = FAL_STP_LISTENING; - break; - case ISIS_STP_LEARNING: - *state = FAL_STP_LEARNING; - break; - case ISIS_STP_FARWARDING: - *state = FAL_STP_FARWARDING; - break; - case ISIS_PORT_DISABLED: - *state = FAL_STP_DISABLED; - break; - default: - return SW_FAIL; - } - - return SW_OK; -} - -/** - * @brief Set port stp state on a particular spanning tree and port. - * @details Comments: - Garuda only support single spanning tree so st_id should be - FAL_SINGLE_STP_ID that is zero. - * @param[in] dev_id device id - * @param[in] st_id spanning tree id - * @param[in] port_id port id - * @param[in] state port state for spanning tree - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -isis_stp_port_state_set(a_uint32_t dev_id, a_uint32_t st_id, - fal_port_t port_id, fal_stp_state_t state) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _isis_stp_port_state_set(dev_id, st_id, port_id, state); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Get port stp state on a particular spanning tree and port. - * @details Comments: - Garuda only support single spanning tree so st_id should be - FAL_SINGLE_STP_ID that is zero. - * @param[in] dev_id device id - * @param[in] st_id spanning tree id - * @param[in] port_id port id - * @param[out] state port state for spanning tree - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -isis_stp_port_state_get(a_uint32_t dev_id, a_uint32_t st_id, - fal_port_t port_id, fal_stp_state_t * state) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _isis_stp_port_state_get(dev_id, st_id, port_id, state); - HSL_API_UNLOCK; - return rv; -} - -sw_error_t -isis_stp_init(a_uint32_t dev_id) -{ - HSL_DEV_ID_CHECK(dev_id); - -#ifndef HSL_STANDALONG - { - hsl_api_t *p_api; - - SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id)); - - p_api->stp_port_state_set = isis_stp_port_state_set; - p_api->stp_port_state_get = isis_stp_port_state_get; - } -#endif - - return SW_OK; -} - -/** - * @} - */ - diff --git a/feeds/ipq807x/qca-ssdk/src/src/hsl/isis/isis_trunk.c b/feeds/ipq807x/qca-ssdk/src/src/hsl/isis/isis_trunk.c deleted file mode 100755 index d0767d290..000000000 --- a/feeds/ipq807x/qca-ssdk/src/src/hsl/isis/isis_trunk.c +++ /dev/null @@ -1,692 +0,0 @@ -/* - * Copyright (c) 2012, 2016, The Linux Foundation. All rights reserved. - * Permission to use, copy, modify, and/or distribute this software for - * any purpose with or without fee is hereby granted, provided that the - * above copyright notice and this permission notice appear in all copies. - * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES - * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR - * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES - * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN - * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT - * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. - */ - - - -/** - * @defgroup isis_trunk ISIS_TRUNK - * @{ - */ -#include "sw.h" -#include "hsl.h" -#include "hsl_dev.h" -#include "hsl_port_prop.h" -#include "isis_trunk.h" -#include "isis_reg.h" - -#define ISIS_MAX_TRUNK_ID 3 - -/*feature on/off for manipulating dp within trunk group*/ -#define ISIS_TRUNK_MANIPULATE_DP_ON 1 -#define ISIS_TRUNK_MANIPULATE_HEADER_LEN 12 -#define MAC_LEN 6 -#define HASH_SIZE 4 - -enum isis_trunk_reg_id -{ - ISIS_TRUNK_HASH_EN = 0, /*0x270*/ - ISIS_TRUNK_CTRL_0, /*0x700*/ - ISIS_TRUNK_CTRL_1, /*0x704*/ - ISIS_TRUNK_CTRL_2, /*0x708*/ - ISIS_TRUNK_REG_MAX -}; - -static a_uint32_t isis_trunk_regs[ISIS_TRUNK_REG_MAX] = -{ - 0xf, 0x0, 0x0, 0x0 -}; - -static a_uint8_t sa_hash[HASH_SIZE][MAC_LEN] = -{ - { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 }, - { 0x00, 0x00, 0x00, 0x00, 0x00, 0x01 }, - { 0x00, 0x00, 0x00, 0x00, 0x00, 0x02 }, - { 0x00, 0x00, 0x00, 0x00, 0x00, 0x03 } -}; - -static sw_error_t -_isis_trunk_group_set(a_uint32_t dev_id, a_uint32_t trunk_id, - a_bool_t enable, fal_pbmp_t member) -{ - sw_error_t rv; - a_uint32_t i, reg = 0, cnt = 0, data0 = 0, data1 = 0; - - if (ISIS_MAX_TRUNK_ID < trunk_id) - { - return SW_BAD_PARAM; - } - - if (A_FALSE == hsl_mports_prop_check(dev_id, member, HSL_PP_INCL_CPU)) - { - return SW_BAD_PARAM; - } - - if (A_TRUE == enable) - { - data0 = (0x1 << 7) | member; - - for (i = 0; i < 7; i++) - { - if (member & (0x1 << i)) - { - if (4 <= cnt) - { - return SW_BAD_PARAM; - } - - data1 |= (i << (cnt << 2)); - data1 |= (1 << (3 + (cnt << 2))); - cnt++; - } - } - } - else if (A_FALSE == enable) - { - - } - else - { - return SW_BAD_PARAM; - } - - /* set trunk port member bitmap info */ - HSL_REG_ENTRY_GET(rv, dev_id, GOL_TRUNK_CTL0, 0, - (a_uint8_t *) (®), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - - reg &= (~(0xff << (trunk_id << 3))); - reg |= (data0 << (trunk_id << 3)); - - HSL_REG_ENTRY_SET(rv, dev_id, GOL_TRUNK_CTL0, 0, - (a_uint8_t *) (®), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - - isis_trunk_regs[ISIS_TRUNK_CTRL_0] = reg; - - /* set trunk port member id info */ - HSL_REG_ENTRY_GET(rv, dev_id, GOL_TRUNK_CTL1, (trunk_id >> 1), - (a_uint8_t *) (®), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - - reg &= (~(0xffff << ((trunk_id % 2) << 4))); - reg |= (data1 << ((trunk_id % 2) << 4)); - - HSL_REG_ENTRY_SET(rv, dev_id, GOL_TRUNK_CTL1, (trunk_id >> 1), - (a_uint8_t *) (®), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - - isis_trunk_regs[ISIS_TRUNK_CTRL_1 + (trunk_id >> 1)] = reg; - - return SW_OK; -} - -static sw_error_t -_isis_trunk_group_get(a_uint32_t dev_id, a_uint32_t trunk_id, - a_bool_t * enable, fal_pbmp_t * member) -{ - sw_error_t rv; - a_uint32_t data, reg = 0; - - if (ISIS_MAX_TRUNK_ID < trunk_id) - { - return SW_BAD_PARAM; - } - - HSL_REG_ENTRY_GET(rv, dev_id, GOL_TRUNK_CTL0, 0, - (a_uint8_t *) (®), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - - data = (reg >> (trunk_id << 3)) & 0xff; - if (0x80 & data) - { - *enable = A_TRUE; - *member = data & 0x7f; - } - else - { - *enable = A_FALSE; - *member = 0; - } - - return SW_OK; -} - -#if 0 -static sw_error_t -_isis_trunk_group_sw_get(a_uint32_t dev_id, a_uint32_t trunk_id, - a_bool_t * enable, fal_pbmp_t * member) -{ - a_uint32_t data, reg; - - if (ISIS_MAX_TRUNK_ID < trunk_id) - { - return SW_BAD_PARAM; - } - - reg = isis_trunk_regs[ISIS_TRUNK_CTRL_0]; - - data = (reg >> (trunk_id << 3)) & 0xff; - if (0x80 & data) - { - *enable = A_TRUE; - *member = data & 0x7f; - } - else - { - *enable = A_FALSE; - *member = 0; - } - - return SW_OK; -} -#endif - -static sw_error_t -_isis_trunk_hash_mode_set(a_uint32_t dev_id, a_uint32_t hash_mode) -{ - sw_error_t rv; - a_uint32_t data = 0; - - if (FAL_TRUNK_HASH_KEY_DA & hash_mode) - { - SW_SET_REG_BY_FIELD(TRUNK_HASH_MODE, DA_EN, 1, data); - } - - if (FAL_TRUNK_HASH_KEY_SA & hash_mode) - { - SW_SET_REG_BY_FIELD(TRUNK_HASH_MODE, SA_EN, 1, data); - } - - if (FAL_TRUNK_HASH_KEY_DIP & hash_mode) - { - SW_SET_REG_BY_FIELD(TRUNK_HASH_MODE, DIP_EN, 1, data); - } - - if (FAL_TRUNK_HASH_KEY_SIP & hash_mode) - { - SW_SET_REG_BY_FIELD(TRUNK_HASH_MODE, SIP_EN, 1, data); - } - - HSL_REG_ENTRY_SET(rv, dev_id, TRUNK_HASH_MODE, 0, - (a_uint8_t *) (&data), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - - isis_trunk_regs[ISIS_TRUNK_HASH_EN] = data; - - return rv; -} - -static sw_error_t -_isis_trunk_hash_mode_get(a_uint32_t dev_id, a_uint32_t * hash_mode) -{ - sw_error_t rv; - a_uint32_t reg = 0, data = 0; - - HSL_REG_ENTRY_GET(rv, dev_id, TRUNK_HASH_MODE, 0, - (a_uint8_t *) (®), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - - *hash_mode = 0; - - SW_GET_FIELD_BY_REG(TRUNK_HASH_MODE, DA_EN, data, reg); - if (data) - { - *hash_mode |= FAL_TRUNK_HASH_KEY_DA; - } - - SW_GET_FIELD_BY_REG(TRUNK_HASH_MODE, SA_EN, data, reg); - if (data) - { - *hash_mode |= FAL_TRUNK_HASH_KEY_SA; - } - - SW_GET_FIELD_BY_REG(TRUNK_HASH_MODE, DIP_EN, data, reg); - if (data) - { - *hash_mode |= FAL_TRUNK_HASH_KEY_DIP; - } - - SW_GET_FIELD_BY_REG(TRUNK_HASH_MODE, SIP_EN, data, reg); - if (data) - { - *hash_mode |= FAL_TRUNK_HASH_KEY_SIP; - } - - return SW_OK; -} - -#define BYTE_B2R(x, mask) ((x) ^ (mask)) -#define BYTE_B1C(x) ((((((x&0x55)+((x&0xaa)>>1))&0x33)+((((x&0x55)+((x&0xaa)>>1))&0xcc)>>2))&0x0f)+((((((x&0x55)+((x&0xaa)>>1))&0x33)+((((x&0x55)+((x&0xaa)>>1))&0xcc)>>2))&0xf0)>>4)) - -static sw_error_t -_isis_trunk_manipulate_sa_set(a_uint32_t dev_id, fal_mac_addr_t * addr) -{ - a_uint32_t i; - - for (i = 0; i < HASH_SIZE; i++) - { - memcpy(sa_hash[i], addr->uc, MAC_LEN); - sa_hash[i][MAC_LEN - 1] = BYTE_B2R(sa_hash[i][MAC_LEN - 1], i); - } - - return SW_OK; -} - -static sw_error_t -_isis_trunk_manipulate_sa_get(a_uint32_t dev_id, fal_mac_addr_t * addr) -{ - memcpy(addr->uc, sa_hash[0], MAC_LEN); - return SW_OK; -} - -#if 0 -static sw_error_t -_isis_trunk_hash_mode_sw_get(a_uint32_t dev_id, a_uint32_t * hash_mode) -{ - a_uint32_t reg, data = 0; - - reg = isis_trunk_regs[ISIS_TRUNK_HASH_EN]; - - *hash_mode = 0; - - SW_GET_FIELD_BY_REG(TRUNK_HASH_MODE, DA_EN, data, reg); - if (data) - { - *hash_mode |= FAL_TRUNK_HASH_KEY_DA; - } - - SW_GET_FIELD_BY_REG(TRUNK_HASH_MODE, SA_EN, data, reg); - if (data) - { - *hash_mode |= FAL_TRUNK_HASH_KEY_SA; - } - - SW_GET_FIELD_BY_REG(TRUNK_HASH_MODE, DIP_EN, data, reg); - if (data) - { - *hash_mode |= FAL_TRUNK_HASH_KEY_DIP; - } - - SW_GET_FIELD_BY_REG(TRUNK_HASH_MODE, SIP_EN, data, reg); - if (data) - { - *hash_mode |= FAL_TRUNK_HASH_KEY_SIP; - } - - return SW_OK; -} - -static sw_error_t -_isis_trunk_id_member_get(a_uint32_t dev_id, a_uint8_t expect_dp, - a_uint32_t * trunk_id, fal_pbmp_t * member) -{ - sw_error_t rv; - a_bool_t enable; - a_uint32_t i; - - for (i = 0; i <= ISIS_MAX_TRUNK_ID; i++) - { - rv = _isis_trunk_group_sw_get(dev_id, i, &enable, member); - SW_RTN_ON_ERROR(rv); - if (enable && (*member & expect_dp)) - { - *trunk_id = i; - return SW_OK; - } - } - - return SW_NOT_FOUND; -} - -static sw_error_t -_isis_trunk_hash_dp_get(a_uint32_t dev_id, a_uint8_t * header, a_uint32_t len, - a_uint32_t trunk_id, a_uint32_t mode, a_uint8_t * hash_dp) -{ -#define BIT2_MASK 0x03 -#define TRUNK_MEM_EN_MASK 0x8 -#define TRUNK_MEM_PT_MASK 0x7 -#define TRUNK_HASH_DP_SEL 4 - sw_error_t rv; - a_uint32_t i, hash_mode, reg, data1 = 0; - a_uint32_t da_xor = 0, sa_xor = 0; /*consider da-hash & sa-hash (TBD: dip-hash & sip-hash)*/ - a_uint8_t xor_dp = 0; - - rv = _isis_trunk_hash_mode_sw_get(dev_id, &hash_mode); - SW_RTN_ON_ERROR(rv); - - if (!hash_mode) - { - return SW_DISABLE; - } - - *hash_dp = 0; - - if ((mode & FAL_TRUNK_HASH_KEY_DA) && (hash_mode & FAL_TRUNK_HASH_KEY_DA)) - { - for (i = 0; i < MAC_LEN; i++) - { - da_xor ^= (header[i] & BIT2_MASK) ^ - ((header[i] >> 2) & BIT2_MASK) ^ - ((header[i] >> 4) & BIT2_MASK) ^ - ((header[i] >> 6) & BIT2_MASK); - } - *hash_dp = da_xor; - } - if ((mode & FAL_TRUNK_HASH_KEY_SA) && (hash_mode & FAL_TRUNK_HASH_KEY_SA)) - { - for (i = 6; i < 2 * MAC_LEN; i++) - { - sa_xor ^= (header[i] & BIT2_MASK) ^ - ((header[i] >> 2) & BIT2_MASK) ^ - ((header[i] >> 4) & BIT2_MASK) ^ - ((header[i] >> 6) & BIT2_MASK); - } - *hash_dp = (*hash_dp) ^ sa_xor; - } - - /*dp translation*/ -#if 0 - HSL_REG_ENTRY_GET(rv, dev_id, GOL_TRUNK_CTL1, (trunk_id >> 1), - (a_uint8_t *) (®), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); -#else /*sw*/ - reg = isis_trunk_regs[ISIS_TRUNK_CTRL_1 + (trunk_id >> 1)]; -#endif - - for (i = 0; i < TRUNK_HASH_DP_SEL; i++) - { - xor_dp = BYTE_B2R(*hash_dp, i); - data1 = (0x0f & (reg >> (((trunk_id % 2) << 4) + (xor_dp << 2)))); - if (data1 & TRUNK_MEM_EN_MASK) - { - *hash_dp = data1 & TRUNK_MEM_PT_MASK; - *hash_dp = 0x01 << (*hash_dp); /*bmp*/ - return SW_OK; - } - } - - return SW_NOT_FOUND; -} - -static sw_error_t -_isis_trunk_sa_spoofing( a_uint32_t dev_id, a_uint8_t * header, a_uint32_t len, - a_uint8_t expect_dp, a_uint32_t trunk_id, fal_pbmp_t member) -{ - sw_error_t rv; - a_uint32_t i, hash_mode; - a_uint8_t hash_dp; - a_uint8_t ori_sa[MAC_LEN]; - - rv = _isis_trunk_hash_mode_sw_get(dev_id, &hash_mode); - SW_RTN_ON_ERROR(rv); - - if (!(hash_mode & FAL_TRUNK_HASH_KEY_SA)) - { - return SW_DISABLE; - } - - memcpy(ori_sa, &header[MAC_LEN], MAC_LEN); - - for (i = 0; i < HASH_SIZE/*not HASH_SIZE, for RAD only*/; i++) - { - memcpy(&header[MAC_LEN], sa_hash[i], MAC_LEN); - rv = _isis_trunk_hash_dp_get(dev_id, header, len, trunk_id, - FAL_TRUNK_HASH_KEY_DA | FAL_TRUNK_HASH_KEY_SA, &hash_dp); - SW_RTN_ON_ERROR(rv); - if (expect_dp == hash_dp) - { - // printk("expect_dp = 0x%x, hash_dp(DA+SA) = 0x%x, sa_id = %d\n", expect_dp, hash_dp, i); - return SW_OK; - } - } - - /*should never here*/ - memcpy(&header[MAC_LEN], ori_sa, MAC_LEN); - return SW_FAIL; -} - -static sw_error_t -_isis_trunk_manipulate_dp(a_uint32_t dev_id, a_uint8_t * header, - a_uint32_t len, fal_pbmp_t dp_member) -{ - sw_error_t rv; - a_uint8_t expect_dp, hash_dp; /*bitmap*/ - a_uint32_t i, trunk_id; - fal_pbmp_t member; - - if (!ISIS_TRUNK_MANIPULATE_DP_ON) - { - return SW_OK; /*feature not enabled*/ - } - - if (!header || len < ISIS_TRUNK_MANIPULATE_HEADER_LEN) - { - return SW_BAD_VALUE; - } - -#if 0 /*de-comment this to ignore broadcast packets*/ - const a_uint8_t bc_mac[MAC_LEN] = { 0xff, 0xff, 0xff, 0xff, 0xff, 0xff }; - if (!memcmp(header, bc_mac, MAC_LEN)) /*not for broadcast*/ - { - return SW_OK; - } -#endif - - /*expect_dp within trunk group*/ - expect_dp = dp_member & 0x7f; - for (i = 0; i < 7; i++) - { - if (expect_dp & (0x01 << i)) - { - rv = _isis_trunk_id_member_get(dev_id, (0x01 << i), &trunk_id, &member); - if (rv != SW_OK) - { - expect_dp &= ~(0x01 << i); /*not the dp doesn't belong to trunk*/ - } - } - } - - if (BYTE_B1C(expect_dp) != 1) /*supports 1 dp only*/ - { - return SW_OK; /*ignore none-dp or multi-dp*/ - } - - rv = _isis_trunk_id_member_get(dev_id, expect_dp, &trunk_id, &member); - SW_RTN_ON_ERROR(rv); - - member &= 0x7f; - if (BYTE_B1C(member) == 1) /*trunk group w/ one port*/ - { - return SW_OK; - } - - rv = _isis_trunk_hash_dp_get(dev_id, header, len, trunk_id, - FAL_TRUNK_HASH_KEY_DA | FAL_TRUNK_HASH_KEY_SA, &hash_dp); - SW_RTN_ON_ERROR(rv); - - // printk("expect_dp = 0x%x, hash_dp(DA+SA) = 0x%x, member = 0x%x\n", expect_dp, hash_dp, member); - if (expect_dp == hash_dp) - { - return SW_OK; - } - - rv = _isis_trunk_sa_spoofing(dev_id, header, len, expect_dp, trunk_id, member); - SW_RTN_ON_ERROR(rv); - - return rv; -} -#endif - -/** - * @brief Set particular trunk group information on particular device. - * @param[in] dev_id device id - * @param[in] trunk_id trunk group id - * @param[in] enable trunk group status, enable or disable - * @param[in] member port member information - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -isis_trunk_group_set(a_uint32_t dev_id, a_uint32_t trunk_id, - a_bool_t enable, fal_pbmp_t member) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _isis_trunk_group_set(dev_id, trunk_id, enable, member); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Get particular trunk group information on particular device. - * @param[in] dev_id device id - * @param[in] trunk_id trunk group id - * @param[out] enable trunk group status, enable or disable - * @param[out] member port member information - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -isis_trunk_group_get(a_uint32_t dev_id, a_uint32_t trunk_id, - a_bool_t * enable, fal_pbmp_t * member) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _isis_trunk_group_get(dev_id, trunk_id, enable, member); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Set trunk hash mode on particular device. - * @details Comments: - hash mode is listed below - FAL_TRUNK_HASH_KEY_DA, FAL_TRUNK_HASH_KEY_SA, FAL_TRUNK_HASH_KEY_DIP and FAL_TRUNK_HASH_KEY_SIP - * @param[in] dev_id device id - * @param[in] hash_mode trunk hash mode - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -isis_trunk_hash_mode_set(a_uint32_t dev_id, a_uint32_t hash_mode) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _isis_trunk_hash_mode_set(dev_id, hash_mode); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Get trunk hash mode on particular device. - * @param[in] dev_id device id - * @param[out] hash_mode trunk hash mode - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -isis_trunk_hash_mode_get(a_uint32_t dev_id, a_uint32_t * hash_mode) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _isis_trunk_hash_mode_get(dev_id, hash_mode); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Set trunk manipulate SA on particular device. - * @param[in] dev_id device id - * @param[in] addr manipulate SA - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -isis_trunk_manipulate_sa_set(a_uint32_t dev_id, fal_mac_addr_t * addr) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _isis_trunk_manipulate_sa_set(dev_id, addr); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Get trunk manipulate SA on particular device. - * @param[in] dev_id device id - * @param[out] addr manipulate SA - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -isis_trunk_manipulate_sa_get(a_uint32_t dev_id, fal_mac_addr_t * addr) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _isis_trunk_manipulate_sa_get(dev_id, addr); - HSL_API_UNLOCK; - return rv; -} - -#if 0 -/** - * @brief manipulate destination port within a trunk group - * @details Comments: - * supporting hash mode include: FAL_TRUNK_HASH_KEY_DA & FAL_TRUNK_HASH_KEY_SA; - * FAL_TRUNK_HASH_KEY_DIP & FAL_TRUNK_HASH_KEY_SIP are NOT covered in current design - * @param[in] dev_id device id - * @param[in-out] header packet header, accept format: [DA:6B][SA:6B] - * @param[in] len length of packet header, should be 12 in current design (6B DA + 6B SA) - * @param[in] dp_member expect destination port members, bitmap format - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -isis_trunk_manipulate_dp(a_uint32_t dev_id, a_uint8_t * header, - a_uint32_t len, fal_pbmp_t dp_member) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _isis_trunk_manipulate_dp(dev_id, header, len, dp_member); - HSL_API_UNLOCK; - return rv; -} -#endif - -sw_error_t -isis_trunk_init(a_uint32_t dev_id) -{ - HSL_DEV_ID_CHECK(dev_id); - -#ifndef HSL_STANDALONG - { - hsl_api_t *p_api; - - SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id)); - p_api->trunk_group_set = isis_trunk_group_set; - p_api->trunk_group_get = isis_trunk_group_get; - p_api->trunk_hash_mode_set = isis_trunk_hash_mode_set; - p_api->trunk_hash_mode_get = isis_trunk_hash_mode_get; - p_api->trunk_manipulate_sa_set = isis_trunk_manipulate_sa_set; - p_api->trunk_manipulate_sa_get = isis_trunk_manipulate_sa_get; - } -#endif - - return SW_OK; -} - -/** - * @} - */ - diff --git a/feeds/ipq807x/qca-ssdk/src/src/hsl/isis/isis_vlan.c b/feeds/ipq807x/qca-ssdk/src/src/hsl/isis/isis_vlan.c deleted file mode 100755 index 248623bd4..000000000 --- a/feeds/ipq807x/qca-ssdk/src/src/hsl/isis/isis_vlan.c +++ /dev/null @@ -1,909 +0,0 @@ -/* - * Copyright (c) 2012, The Linux Foundation. All rights reserved. - * Permission to use, copy, modify, and/or distribute this software for - * any purpose with or without fee is hereby granted, provided that the - * above copyright notice and this permission notice appear in all copies. - * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES - * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR - * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES - * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN - * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT - * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. - */ - - -/** - * @defgroup isis_vlan ISIS_VLAN - * @{ - */ -#include "sw.h" -#include "hsl.h" -#include "hsl_dev.h" -#include "hsl_port_prop.h" -#include "isis_vlan.h" -#include "isis_reg.h" - -#define MAX_VLAN_ID 4095 - -#define VLAN_FLUSH 1 -#define VLAN_LOAD_ENTRY 2 -#define VLAN_PURGE_ENTRY 3 -#define VLAN_REMOVE_PORT 4 -#define VLAN_NEXT_ENTRY 5 -#define VLAN_FIND_ENTRY 6 - -static void -_isis_vlan_hw_to_sw(a_uint32_t reg[], fal_vlan_t * vlan_entry) -{ - a_uint32_t i, data, tmp; - - aos_mem_zero(vlan_entry, sizeof (fal_vlan_t)); - - SW_GET_FIELD_BY_REG(VLAN_TABLE_FUNC1, VLAN_ID, data, reg[1]); - vlan_entry->vid = data & 0xfff; - - SW_GET_FIELD_BY_REG(VLAN_TABLE_FUNC0, IVL_EN, data, reg[0]); - if (1 == data) - { - vlan_entry->fid = vlan_entry->vid; - } - else - { - vlan_entry->fid = FAL_SVL_FID; - } - - SW_GET_FIELD_BY_REG(VLAN_TABLE_FUNC0, LEARN_DIS, data, reg[0]); - if (1 == data) - { - vlan_entry->learn_dis = A_TRUE; - } - else - { - vlan_entry->learn_dis = A_FALSE; - } - - SW_GET_FIELD_BY_REG(VLAN_TABLE_FUNC0, VT_PRI_EN, data, reg[0]); - if (1 == data) - { - vlan_entry->vid_pri_en = A_TRUE; - - SW_GET_FIELD_BY_REG(VLAN_TABLE_FUNC0, VT_PRI, data, reg[0]); - vlan_entry->vid_pri = data & 0xff; - } - else - { - vlan_entry->vid_pri_en = A_FALSE; - } - - SW_GET_FIELD_BY_REG(VLAN_TABLE_FUNC0, VID_MEM, data, reg[0]); - for (i = 0; i < 7; i++) - { - tmp = (data >> (i << 1)) & 0x3UL; - if (0 == tmp) - { - vlan_entry->mem_ports |= (0x1UL << i); - vlan_entry->unmodify_ports |= (0x1UL << i); - } - else if (1 == tmp) - { - vlan_entry->mem_ports |= (0x1UL << i); - vlan_entry->untagged_ports |= (0x1UL << i); - } - else if (2 == tmp) - { - vlan_entry->mem_ports |= (0x1UL << i); - vlan_entry->tagged_ports |= (0x1UL << i); - } - } - - return; -} - -static sw_error_t -_isis_vlan_sw_to_hw(a_uint32_t dev_id, const fal_vlan_t * vlan_entry, - a_uint32_t reg[]) -{ - a_uint32_t i, tag, untag, unmodify, member = 0; - - if (vlan_entry->vid > MAX_VLAN_ID) - { - return SW_OUT_OF_RANGE; - } - - if (A_FALSE == - hsl_mports_prop_check(dev_id, vlan_entry->mem_ports, HSL_PP_INCL_CPU)) - { - return SW_BAD_PARAM; - } - - SW_SET_REG_BY_FIELD(VLAN_TABLE_FUNC0, VT_VALID, 1, reg[0]); - - if (FAL_SVL_FID == vlan_entry->fid) - { - SW_SET_REG_BY_FIELD(VLAN_TABLE_FUNC0, IVL_EN, 0, reg[0]); - } - else if (vlan_entry->vid == vlan_entry->fid) - { - SW_SET_REG_BY_FIELD(VLAN_TABLE_FUNC0, IVL_EN, 1, reg[0]); - } - else - { - return SW_BAD_VALUE; - } - - if (A_TRUE == vlan_entry->learn_dis) - { - SW_SET_REG_BY_FIELD(VLAN_TABLE_FUNC0, LEARN_DIS, 1, reg[0]); - } - else - { - SW_SET_REG_BY_FIELD(VLAN_TABLE_FUNC0, LEARN_DIS, 0, reg[0]); - } - - for (i = 0; i < 7; i++) - { - if ((vlan_entry->mem_ports >> i) & 0x1UL) - { - tag = (vlan_entry->tagged_ports >> i) & 0x1UL; - untag = (vlan_entry->untagged_ports >> i) & 0x1UL; - unmodify = (vlan_entry->unmodify_ports >> i) & 0x1UL; - - if ((0 == (tag + untag + unmodify)) - || (1 < (tag + untag + unmodify))) - { - return SW_BAD_VALUE; - } - - if (tag) - { - member |= (2 << (i << 1)); - } - else if (untag) - { - member |= (1 << (i << 1)); - } - } - else - { - member |= (3 << (i << 1)); - } - } - SW_SET_REG_BY_FIELD(VLAN_TABLE_FUNC0, VID_MEM, member, reg[0]); - - if (A_TRUE == vlan_entry->vid_pri_en) - { - SW_SET_REG_BY_FIELD(VLAN_TABLE_FUNC0, VT_PRI_EN, 1, reg[0]); - SW_SET_REG_BY_FIELD(VLAN_TABLE_FUNC0, VT_PRI, vlan_entry->vid_pri, - reg[0]); - } - else - { - SW_SET_REG_BY_FIELD(VLAN_TABLE_FUNC0, VT_PRI_EN, 0, reg[0]); - } - - SW_SET_REG_BY_FIELD(VLAN_TABLE_FUNC1, VLAN_ID, vlan_entry->vid, reg[1]); - - return SW_OK; -} - -static sw_error_t -_isis_vlan_down_to_hw(a_uint32_t dev_id, a_uint32_t reg[]) -{ - sw_error_t rv; - - HSL_REG_ENTRY_SET(rv, dev_id, VLAN_TABLE_FUNC0, 0, - (a_uint8_t *) (®[0]), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - - HSL_REG_ENTRY_SET(rv, dev_id, VLAN_TABLE_FUNC1, 0, - (a_uint8_t *) (®[1]), sizeof (a_uint32_t)); - return rv; -} - -static sw_error_t -_isis_vlan_up_to_sw(a_uint32_t dev_id, a_uint32_t reg[]) -{ - sw_error_t rv; - - HSL_REG_ENTRY_GET(rv, dev_id, VLAN_TABLE_FUNC0, 0, - (a_uint8_t *) (®[0]), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - - HSL_REG_ENTRY_GET(rv, dev_id, VLAN_TABLE_FUNC1, 0, - (a_uint8_t *) (®[1]), sizeof (a_uint32_t)); - return rv; -} - -static sw_error_t -_isis_vlan_commit(a_uint32_t dev_id, a_uint32_t op) -{ - a_uint32_t vt_busy = 1, i = 0x1000, vt_full, val; - sw_error_t rv; - - while (vt_busy && --i) - { - HSL_REG_FIELD_GET(rv, dev_id, VLAN_TABLE_FUNC1, 0, VT_BUSY, - (a_uint8_t *) (&vt_busy), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - aos_udelay(5); - } - - if (i == 0) - { - printk("%s BUSY\n", __FUNCTION__); - return SW_BUSY; - } - - HSL_REG_ENTRY_GET(rv, dev_id, VLAN_TABLE_FUNC1, 0, - (a_uint8_t *) (&val), sizeof (a_uint32_t)); - SW_SET_REG_BY_FIELD(VLAN_TABLE_FUNC1, VT_FUNC, op, val); - SW_SET_REG_BY_FIELD(VLAN_TABLE_FUNC1, VT_BUSY, 1, val); - - HSL_REG_ENTRY_SET(rv, dev_id, VLAN_TABLE_FUNC1, 0, - (a_uint8_t *) (&val), sizeof (a_uint32_t)); - - SW_RTN_ON_ERROR(rv); - - vt_busy = 1; - i = 0x1000; - while (vt_busy && --i) - { - HSL_REG_FIELD_GET(rv, dev_id, VLAN_TABLE_FUNC1, 0, VT_BUSY, - (a_uint8_t *) (&vt_busy), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - aos_udelay(5); - } - - if (i == 0) - return SW_FAIL; - - HSL_REG_FIELD_GET(rv, dev_id, VLAN_TABLE_FUNC1, 0, VT_FULL_VIO, - (a_uint8_t *) (&vt_full), sizeof (a_uint32_t)); - - SW_RTN_ON_ERROR(rv); - - if (vt_full) - { - val = 0x10; - HSL_REG_ENTRY_SET(rv, dev_id, VLAN_TABLE_FUNC1, 0, - (a_uint8_t *) (&val), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - if (VLAN_LOAD_ENTRY == op) - { - return SW_FULL; - } - else if (VLAN_PURGE_ENTRY == op) - { - return SW_NOT_FOUND; - } - } - - HSL_REG_FIELD_GET(rv, dev_id, VLAN_TABLE_FUNC0, 0, VT_VALID, - (a_uint8_t *) (&val), sizeof (a_uint32_t)); - - SW_RTN_ON_ERROR(rv); - - if (!val) - { - if (VLAN_FIND_ENTRY == op) - return SW_NOT_FOUND; - - if (VLAN_NEXT_ENTRY == op) - return SW_NO_MORE; - } - - return SW_OK; -} - -static sw_error_t -_isis_vlan_hwentry_get(a_uint32_t dev_id, a_uint32_t vlan_id, a_uint32_t reg[]) -{ - sw_error_t rv; - - if (vlan_id > MAX_VLAN_ID) - { - return SW_OUT_OF_RANGE; - } - - SW_SET_REG_BY_FIELD(VLAN_TABLE_FUNC1, VLAN_ID, vlan_id, reg[1]); - HSL_REG_ENTRY_SET(rv, dev_id, VLAN_TABLE_FUNC1, 0, - (a_uint8_t *) (®[1]), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - - rv = _isis_vlan_commit(dev_id, VLAN_FIND_ENTRY); - SW_RTN_ON_ERROR(rv); - - rv = _isis_vlan_up_to_sw(dev_id, reg); - return rv; -} - -static sw_error_t -_isis_vlan_entry_append(a_uint32_t dev_id, const fal_vlan_t * vlan_entry) -{ - sw_error_t rv; - a_uint32_t reg[2] = { 0 }; - - HSL_DEV_ID_CHECK(dev_id); - - rv = _isis_vlan_sw_to_hw(dev_id, vlan_entry, reg); - SW_RTN_ON_ERROR(rv); - - rv = _isis_vlan_down_to_hw(dev_id, reg); - SW_RTN_ON_ERROR(rv); - - rv = _isis_vlan_commit(dev_id, VLAN_LOAD_ENTRY); - return rv; -} - -static sw_error_t -_isis_vlan_create(a_uint32_t dev_id, a_uint32_t vlan_id) -{ - sw_error_t rv; - a_uint32_t reg[2] = { 0 }; - - HSL_DEV_ID_CHECK(dev_id); - - if (vlan_id > MAX_VLAN_ID) - { - return SW_OUT_OF_RANGE; - } - - SW_SET_REG_BY_FIELD(VLAN_TABLE_FUNC0, VT_VALID, 1, reg[0]); - SW_SET_REG_BY_FIELD(VLAN_TABLE_FUNC0, IVL_EN, 1, reg[0]); - SW_SET_REG_BY_FIELD(VLAN_TABLE_FUNC0, LEARN_DIS, 0, reg[0]); - SW_SET_REG_BY_FIELD(VLAN_TABLE_FUNC0, VID_MEM, 0x3fff, reg[0]); - SW_SET_REG_BY_FIELD(VLAN_TABLE_FUNC1, VLAN_ID, vlan_id, reg[1]); - - rv = _isis_vlan_down_to_hw(dev_id, reg); - SW_RTN_ON_ERROR(rv); - - rv = _isis_vlan_commit(dev_id, VLAN_LOAD_ENTRY); - return rv; -} - -static sw_error_t -_isis_vlan_next(a_uint32_t dev_id, a_uint32_t vlan_id, fal_vlan_t * p_vlan) -{ - sw_error_t rv; - a_uint32_t reg[2] = { 0 }; - - HSL_DEV_ID_CHECK(dev_id); - - if (FAL_NEXT_ENTRY_FIRST_ID == vlan_id) - { - rv = _isis_vlan_hwentry_get(dev_id, 0, reg); - - if (SW_OK == rv) - { - _isis_vlan_hw_to_sw(reg, p_vlan); - return SW_OK; - } - else - { - vlan_id = 0; - } - } - - if (vlan_id > MAX_VLAN_ID) - return SW_OUT_OF_RANGE; - - SW_SET_REG_BY_FIELD(VLAN_TABLE_FUNC1, VLAN_ID, vlan_id, reg[1]); - HSL_REG_ENTRY_SET(rv, dev_id, VLAN_TABLE_FUNC1, 0, - (a_uint8_t *) (®[1]), sizeof (a_uint32_t)); - - SW_RTN_ON_ERROR(rv); - - rv = _isis_vlan_commit(dev_id, VLAN_NEXT_ENTRY); - SW_RTN_ON_ERROR(rv); - - rv = _isis_vlan_up_to_sw(dev_id, reg); - SW_RTN_ON_ERROR(rv); - - _isis_vlan_hw_to_sw(reg, p_vlan); - - if (0 == p_vlan->vid) - { - return SW_NO_MORE; - } - else - { - return SW_OK; - } -} - -static sw_error_t -_isis_vlan_find(a_uint32_t dev_id, a_uint32_t vlan_id, fal_vlan_t * p_vlan) -{ - sw_error_t rv; - a_uint32_t reg[2] = { 0 }; - - HSL_DEV_ID_CHECK(dev_id); - - rv = _isis_vlan_hwentry_get(dev_id, vlan_id, reg); - SW_RTN_ON_ERROR(rv); - - _isis_vlan_hw_to_sw(reg, p_vlan); - return SW_OK; -} - -static sw_error_t -_isis_vlan_delete(a_uint32_t dev_id, a_uint32_t vlan_id) -{ - sw_error_t rv; - a_uint32_t reg; - - HSL_DEV_ID_CHECK(dev_id); - - if (vlan_id > MAX_VLAN_ID) - { - return SW_OUT_OF_RANGE; - } - - reg = (a_int32_t) vlan_id; - HSL_REG_FIELD_SET(rv, dev_id, VLAN_TABLE_FUNC1, 0, VLAN_ID, - (a_uint8_t *) (®), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - - rv = _isis_vlan_commit(dev_id, VLAN_PURGE_ENTRY); - return rv; -} - -static sw_error_t -_isis_vlan_flush(a_uint32_t dev_id) -{ - sw_error_t rv; - - HSL_DEV_ID_CHECK(dev_id); - - rv = _isis_vlan_commit(dev_id, VLAN_FLUSH); - return rv; -} - -static sw_error_t -_isis_vlan_fid_set(a_uint32_t dev_id, a_uint32_t vlan_id, a_uint32_t fid) -{ - sw_error_t rv; - a_uint32_t reg[2] = { 0 }; - - HSL_DEV_ID_CHECK(dev_id); - - if ((MAX_VLAN_ID < fid) && (FAL_SVL_FID != fid)) - { - return SW_BAD_PARAM; - } - - if ((MAX_VLAN_ID >= fid) && (vlan_id != fid)) - { - return SW_BAD_PARAM; - } - - rv = _isis_vlan_hwentry_get(dev_id, vlan_id, reg); - SW_RTN_ON_ERROR(rv); - - if (FAL_SVL_FID == fid) - { - SW_SET_REG_BY_FIELD(VLAN_TABLE_FUNC0, IVL_EN, 0, reg[0]); - } - else - { - SW_SET_REG_BY_FIELD(VLAN_TABLE_FUNC0, IVL_EN, 1, reg[0]); - } - - rv = _isis_vlan_down_to_hw(dev_id, reg); - SW_RTN_ON_ERROR(rv); - - rv = _isis_vlan_commit(dev_id, VLAN_LOAD_ENTRY); - if (SW_FULL == rv) - { - rv = SW_OK; - } - return rv; -} - -static sw_error_t -_isis_vlan_fid_get(a_uint32_t dev_id, a_uint32_t vlan_id, a_uint32_t * fid) -{ - sw_error_t rv; - a_uint32_t data, reg[2] = { 0 }; - - HSL_DEV_ID_CHECK(dev_id); - - rv = _isis_vlan_hwentry_get(dev_id, vlan_id, reg); - SW_RTN_ON_ERROR(rv); - - SW_GET_FIELD_BY_REG(VLAN_TABLE_FUNC0, IVL_EN, data, reg[0]); - if (data) - { - *fid = vlan_id; - } - else - { - *fid = FAL_SVL_FID; - } - return SW_OK; -} - -static sw_error_t -_isis_vlan_member_update(a_uint32_t dev_id, a_uint32_t vlan_id, - fal_port_t port_id, a_uint32_t port_info) -{ - sw_error_t rv; - a_uint32_t data, reg[2] = { 0 }; - - HSL_DEV_ID_CHECK(dev_id); - - if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU)) - { - return SW_BAD_PARAM; - } - - rv = _isis_vlan_hwentry_get(dev_id, vlan_id, reg); - SW_RTN_ON_ERROR(rv); - - SW_GET_FIELD_BY_REG(VLAN_TABLE_FUNC0, VID_MEM, data, reg[0]); - data &= (~(0x3 << (port_id << 1))); - data |= ((port_info & 0x3) << (port_id << 1)); - SW_SET_REG_BY_FIELD(VLAN_TABLE_FUNC0, VID_MEM, data, reg[0]); - - rv = _isis_vlan_down_to_hw(dev_id, reg); - SW_RTN_ON_ERROR(rv); - - rv = _isis_vlan_commit(dev_id, VLAN_LOAD_ENTRY); - if (SW_FULL == rv) - { - rv = SW_OK; - } - return rv; -} - -static sw_error_t -_isis_vlan_member_add(a_uint32_t dev_id, a_uint32_t vlan_id, - fal_port_t port_id, fal_pt_1q_egmode_t port_info) -{ - sw_error_t rv; - a_uint32_t info = 0; - - if (FAL_EG_UNMODIFIED == port_info) - { - info = 0; - } - else if (FAL_EG_TAGGED == port_info) - { - info = 0x2; - } - else if (FAL_EG_UNTAGGED == port_info) - { - info = 0x1; - } - else - { - return SW_BAD_PARAM; - } - - rv = _isis_vlan_member_update(dev_id, vlan_id, port_id, info); - return rv; -} - -static sw_error_t -_isis_vlan_member_del(a_uint32_t dev_id, a_uint32_t vlan_id, fal_port_t port_id) -{ - sw_error_t rv; - a_uint32_t info = 0x3; - - rv = _isis_vlan_member_update(dev_id, vlan_id, port_id, info); - return rv; -} - -static sw_error_t -_isis_vlan_learning_state_set(a_uint32_t dev_id, a_uint32_t vlan_id, - a_bool_t enable) -{ - sw_error_t rv; - a_uint32_t reg[2] = { 0 }; - - HSL_DEV_ID_CHECK(dev_id); - - rv = _isis_vlan_hwentry_get(dev_id, vlan_id, reg); - SW_RTN_ON_ERROR(rv); - - if (A_TRUE == enable) - { - SW_SET_REG_BY_FIELD(VLAN_TABLE_FUNC0, LEARN_DIS, 0, reg[0]); - } - else if (A_FALSE == enable) - { - SW_SET_REG_BY_FIELD(VLAN_TABLE_FUNC0, LEARN_DIS, 1, reg[0]); - } - else - { - return SW_BAD_PARAM; - } - - rv = _isis_vlan_down_to_hw(dev_id, reg); - SW_RTN_ON_ERROR(rv); - - rv = _isis_vlan_commit(dev_id, VLAN_LOAD_ENTRY); - if (SW_FULL == rv) - { - rv = SW_OK; - } - return rv; -} - -static sw_error_t -_isis_vlan_learning_state_get(a_uint32_t dev_id, a_uint32_t vlan_id, - a_bool_t * enable) -{ - sw_error_t rv; - a_uint32_t data, reg[2] = { 0 }; - - HSL_DEV_ID_CHECK(dev_id); - - rv = _isis_vlan_hwentry_get(dev_id, vlan_id, reg); - SW_RTN_ON_ERROR(rv); - - SW_GET_FIELD_BY_REG(VLAN_TABLE_FUNC0, LEARN_DIS, data, reg[0]); - if (data) - { - *enable = A_FALSE; - } - else - { - *enable = A_TRUE; - } - return SW_OK; -} - -/** - * @brief Append a vlan entry on paticular device. - * @param[in] dev_id device id - * @param[in] vlan_entry vlan entry - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -isis_vlan_entry_append(a_uint32_t dev_id, const fal_vlan_t * vlan_entry) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _isis_vlan_entry_append(dev_id, vlan_entry); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Creat a vlan entry through vlan id on a paticular device. - * @details Comments: - * After this operation the member ports of the created vlan entry are null. - * @param[in] dev_id device id - * @param[in] vlan_id vlan id - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -isis_vlan_create(a_uint32_t dev_id, a_uint32_t vlan_id) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _isis_vlan_create(dev_id, vlan_id); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Next a vlan entry through vlan id on a paticular device. - * @details Comments: - * If the value of vid is zero this operation will get the first entry. - * @param[in] dev_id device id - * @param[in] vlan_id vlan id - * @param[out] p_vlan vlan entry - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -isis_vlan_next(a_uint32_t dev_id, a_uint32_t vlan_id, fal_vlan_t * p_vlan) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _isis_vlan_next(dev_id, vlan_id, p_vlan); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Find a vlan entry through vlan id on paticular device. - * @param[in] dev_id device id - * @param[in] vlan_id vlan id - * @param[out] p_vlan vlan entry - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -isis_vlan_find(a_uint32_t dev_id, a_uint32_t vlan_id, fal_vlan_t * p_vlan) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _isis_vlan_find(dev_id, vlan_id, p_vlan); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Delete a vlan entry through vlan id on a paticular device. - * @param[in] dev_id device id - * @param[in] vlan_id vlan id - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -isis_vlan_delete(a_uint32_t dev_id, a_uint32_t vlan_id) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _isis_vlan_delete(dev_id, vlan_id); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Flush all vlan entries on a paticular device. - * @param[in] dev_id device id - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -isis_vlan_flush(a_uint32_t dev_id) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _isis_vlan_flush(dev_id); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Set FID of a paticular vlan entry on a paticular device. - * @param[in] dev_id device id - * @param[in] vlan_id vlan id - * @param[in] fid FDB id - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -isis_vlan_fid_set(a_uint32_t dev_id, a_uint32_t vlan_id, a_uint32_t fid) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _isis_vlan_fid_set(dev_id, vlan_id, fid); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Get FID of a paticular vlan entry on a paticular device. - * @param[in] dev_id device id - * @param[in] vlan_id vlan id - * @param[out] fid FDB id - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -isis_vlan_fid_get(a_uint32_t dev_id, a_uint32_t vlan_id, a_uint32_t * fid) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _isis_vlan_fid_get(dev_id, vlan_id, fid); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Add a port member to a paticular vlan entry on a paticular device. - * @param[in] dev_id device id - * @param[in] vlan_id vlan id - * @param[in] port_id port id - * @param[in] port_info port tag information - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -isis_vlan_member_add(a_uint32_t dev_id, a_uint32_t vlan_id, - fal_port_t port_id, fal_pt_1q_egmode_t port_info) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _isis_vlan_member_add(dev_id, vlan_id, port_id, port_info); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Del a port member from a paticular vlan entry on a paticular device. - * @param[in] dev_id device id - * @param[in] vlan_id vlan id - * @param[in] port_id port id - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -isis_vlan_member_del(a_uint32_t dev_id, a_uint32_t vlan_id, fal_port_t port_id) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _isis_vlan_member_del(dev_id, vlan_id, port_id); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Set FDB learning status of a paticular vlan entry on a paticular device. - * @param[in] dev_id device id - * @param[in] vlan_id vlan id - * @param[in] enable A_TRUE or A_FALSE - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -isis_vlan_learning_state_set(a_uint32_t dev_id, a_uint32_t vlan_id, - a_bool_t enable) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _isis_vlan_learning_state_set(dev_id, vlan_id, enable); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Get FDB learning status of a paticular vlan entry on a paticular device. - * @param[in] dev_id device id - * @param[in] vlan_id vlan id - * @param[out] enable A_TRUE or A_FALSE - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -isis_vlan_learning_state_get(a_uint32_t dev_id, a_uint32_t vlan_id, - a_bool_t * enable) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _isis_vlan_learning_state_get(dev_id, vlan_id, enable); - HSL_API_UNLOCK; - return rv; -} - -sw_error_t -isis_vlan_init(a_uint32_t dev_id) -{ - hsl_api_t *p_api; - HSL_DEV_ID_CHECK(dev_id); - -#ifndef HSL_STANDALONG - - SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id)); - - p_api->vlan_entry_append = isis_vlan_entry_append; - p_api->vlan_creat = isis_vlan_create; - p_api->vlan_delete = isis_vlan_delete; - p_api->vlan_next = isis_vlan_next; - p_api->vlan_find = isis_vlan_find; - p_api->vlan_flush = isis_vlan_flush; - p_api->vlan_fid_set = isis_vlan_fid_set; - p_api->vlan_fid_get = isis_vlan_fid_get; - p_api->vlan_member_add = isis_vlan_member_add; - p_api->vlan_member_del = isis_vlan_member_del; - p_api->vlan_learning_state_set = isis_vlan_learning_state_set; - p_api->vlan_learning_state_get = isis_vlan_learning_state_get; - - -#endif - - return SW_OK; -} - -/** - * @} - */ - diff --git a/feeds/ipq807x/qca-ssdk/src/src/hsl/isisc/Makefile b/feeds/ipq807x/qca-ssdk/src/src/hsl/isisc/Makefile deleted file mode 100755 index 4990ff0b0..000000000 --- a/feeds/ipq807x/qca-ssdk/src/src/hsl/isisc/Makefile +++ /dev/null @@ -1,122 +0,0 @@ -LOC_DIR=src/hsl/isisc -LIB=HSL - -include $(PRJ_PATH)/make/config.mk - -SRC_LIST=isisc_reg_access.c isisc_init.c - -ifeq (TRUE, $(IN_ACL)) - SRC_LIST += isisc_acl.c isisc_acl_parse.c -endif - -ifeq (TRUE, $(IN_FDB)) - SRC_LIST += isisc_fdb.c -endif - -ifeq (TRUE, $(IN_IGMP)) - SRC_LIST += isisc_igmp.c - ifeq (TRUE, $(IN_ACL)) - SRC_LIST += isisc_multicast_acl.c - endif -endif - -ifeq (TRUE, $(IN_LEAKY)) - SRC_LIST += isisc_leaky.c -endif - -ifeq (TRUE, $(IN_LED)) - SRC_LIST += isisc_led.c -endif - -ifeq (TRUE, $(IN_MIB)) - SRC_LIST += isisc_mib.c -endif - -ifeq (TRUE, $(IN_MIRROR)) - SRC_LIST += isisc_mirror.c -endif - -ifeq (TRUE, $(IN_MISC)) - SRC_LIST += isisc_misc.c -endif - -ifeq (TRUE, $(IN_PORTCONTROL)) - SRC_LIST += isisc_port_ctrl.c -endif - -ifeq (TRUE, $(IN_PORTVLAN)) - SRC_LIST += isisc_portvlan.c -endif - -ifeq (TRUE, $(IN_QOS)) - SRC_LIST += isisc_qos.c -endif - -ifeq (TRUE, $(IN_RATE)) - SRC_LIST += isisc_rate.c -endif - -ifeq (TRUE, $(IN_STP)) - SRC_LIST += isisc_stp.c -endif - -ifeq (TRUE, $(IN_VLAN)) - SRC_LIST += isisc_vlan.c -endif - -ifeq (TRUE, $(IN_REDUCED_ACL)) - SRC_LIST += isisc_reduced_acl.c -endif - -ifeq (TRUE, $(IN_COSMAP)) - SRC_LIST += isisc_cosmap.c -endif - -ifeq (TRUE, $(IN_IP)) - SRC_LIST += isisc_ip.c -endif - -ifeq (TRUE, $(IN_NAT)) - SRC_LIST += isisc_nat.c -endif - -ifeq (TRUE, $(IN_NAT_HELPER)) - SRC_LIST += nat_helper_dt.c - SRC_LIST += nat_helper_hsl.c - SRC_LIST += nat_ipt_helper.c - SRC_LIST += napt_helper.c - SRC_LIST += host_helper.c - SRC_LIST += nat_helper.c - SRC_LIST += napt_acl.c - SRC_LIST += napt_procfs.c -endif - -ifeq (TRUE, $(IN_TRUNK)) - SRC_LIST += isisc_trunk.c -endif - -ifeq (TRUE, $(IN_SEC)) - SRC_LIST += isisc_sec.c -endif - -ifeq (TRUE, $(IN_INTERFACECONTROL)) - SRC_LIST += isisc_interface_ctrl.c -endif - -ifeq (linux, $(OS)) - ifeq (KSLIB, $(MODULE_TYPE)) - ifneq (TRUE, $(KERNEL_MODE)) - SRC_LIST=isisc_reg_access.c isisc_init.c - endif - endif -endif - -ifeq (, $(findstring ISISC, $(SUPPORT_CHIP))) - SRC_LIST= -endif - -include $(PRJ_PATH)/make/components.mk -include $(PRJ_PATH)/make/defs.mk -include $(PRJ_PATH)/make/target.mk - -all: dep obj diff --git a/feeds/ipq807x/qca-ssdk/src/src/hsl/isisc/isisc_acl.c b/feeds/ipq807x/qca-ssdk/src/src/hsl/isisc/isisc_acl.c deleted file mode 100755 index a446a2d10..000000000 --- a/feeds/ipq807x/qca-ssdk/src/src/hsl/isisc/isisc_acl.c +++ /dev/null @@ -1,2035 +0,0 @@ -/* - * Copyright (c) 2012, 2016, 2018, The Linux Foundation. All rights reserved. - * Permission to use, copy, modify, and/or distribute this software for - * any purpose with or without fee is hereby granted, provided that the - * above copyright notice and this permission notice appear in all copies. - * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES - * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR - * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES - * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN - * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT - * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. - */ - - -/** - * @defgroup isisc_acl ISISC_ACL - * @{ - */ -#include "sw.h" -#include "hsl.h" -#include "hsl_dev.h" -#include "hsl_acl.h" -#include "isisc_acl.h" -#include "isisc_reg.h" -#include "isisc_acl_prv.h" - -//#define ISISC_ACL_DEBUG -//#define ISISC_SW_ENTRY -#define ISISC_HW_ENTRY - -static isisc_acl_list_t *sw_list_ent[SW_MAX_NR_DEV]; -static isisc_acl_rule_t *sw_rule_ent[SW_MAX_NR_DEV]; - -static isisc_acl_rule_t *sw_rule_tmp[SW_MAX_NR_DEV]; -static isisc_acl_rule_t *hw_rule_tmp[SW_MAX_NR_DEV]; -#ifdef ISISC_SW_ENTRY -static a_uint8_t *sw_filter_mem = NULL; -#endif - -static sw_error_t -_isisc_filter_valid_set(a_uint32_t dev_id, a_uint32_t flt_idx, a_uint32_t flag); - -static sw_error_t -_isisc_filter_ports_bind(a_uint32_t dev_id, a_uint32_t flt_idx, - a_uint32_t ports); - -#ifdef ISISC_SW_ENTRY -static sw_error_t -_isisc_filter_write(a_uint32_t dev_id, a_uint32_t reg[], a_uint32_t flt_idx, - a_uint32_t op); - -static sw_error_t -_isisc_filter_read(a_uint32_t dev_id, a_uint32_t reg[], a_uint32_t flt_idx, - a_uint32_t op); -#endif - -static sw_error_t -_isisc_filter_down_to_hw(a_uint32_t dev_id, hw_filter_t * filter, - a_uint32_t flt_idx); - -static sw_error_t -_isisc_filter_up_to_sw(a_uint32_t dev_id, hw_filter_t * filter, - a_uint32_t flt_idx); - -static sw_error_t -_isisc_acl_rule_src_filter_sts_set(a_uint32_t dev_id, - a_uint32_t rule_id, a_bool_t enable); - -static void -_isisc_acl_list_dump(a_uint32_t dev_id) -{ - a_uint32_t i; - isisc_acl_list_t *sw_list; - - aos_printk("\ndev_id=%d list control infomation:", dev_id); - for (i = 0; i < ISISC_MAX_FILTER; i++) - { - sw_list = &(sw_list_ent[dev_id][i]); - if (ENT_USED & sw_list->status) - { - aos_printk - ("\nlist_id=%02d list_pri=%02d rule_nr=%02d [pts_map]:0x%02x idx=%02d ", - sw_list->list_id, sw_list->list_pri, sw_list->rule_nr, - sw_list->bind_pts, i); - } - } - aos_printk("\n"); -} - -static void -_isisc_acl_sw_rule_dump(char *info, isisc_acl_rule_t * sw_rule) -{ -#ifdef ISISC_ACL_DEBUG - a_uint32_t flt_idx, i; - - aos_printk("\n%s", info); - for (flt_idx = 0; flt_idx < ISISC_MAX_FILTER; flt_idx++) - { - aos_printk("\n%d software filter:", flt_idx); - aos_printk("\nact:"); - for (i = 0; i < 3; i++) - { - aos_printk("%08x ", sw_rule[flt_idx].filter.act[i]); - } - - aos_printk("\nvlu:"); - for (i = 0; i < 5; i++) - { - aos_printk("%08x ", sw_rule[flt_idx].filter.vlu[i]); - } - - aos_printk("\nmsk:"); - for (i = 0; i < 5; i++) - { - aos_printk("%08x ", sw_rule[flt_idx].filter.msk[i]); - } - - aos_printk("\nctl:status[%02d] list_id[%02d] rule_id[%02d]", - sw_rule[flt_idx].status, - sw_rule[flt_idx].list_id, sw_rule[flt_idx].rule_id); - - aos_printk("\n\n"); - } -#else - return; -#endif -} - -static isisc_acl_list_t * -_isisc_acl_list_loc(a_uint32_t dev_id, a_uint32_t list_id) -{ - a_uint32_t i; - - for (i = 0; i < ISISC_MAX_FILTER; i++) - { - if ((ENT_USED & sw_list_ent[dev_id][i].status) - && (list_id == sw_list_ent[dev_id][i].list_id)) - { - return &(sw_list_ent[dev_id][i]); - } - } - return NULL; -} - -static sw_error_t -_isisc_filter_valid_set(a_uint32_t dev_id, a_uint32_t flt_idx, a_uint32_t flag) -{ -#ifdef ISISC_SW_ENTRY - hw_filter_t filter; - - _isisc_filter_up_to_sw(dev_id, &filter, flt_idx); - - filter.msk[4] &= 0xfffffff8; - filter.msk[4] |= (flag & 0x7); - - _isisc_filter_down_to_hw(dev_id, &filter, flt_idx); - - return SW_OK; -#else -#ifdef ISISC_HW_ENTRY - hw_filter_t filter; - - filter = sw_rule_ent[dev_id][flt_idx].filter; - - filter.msk[4] &= 0xfffffff8; - filter.msk[4] |= (flag & 0x7); - - _isisc_filter_down_to_hw(dev_id, &filter, flt_idx); - return SW_OK; -#else - sw_error_t rv; - a_uint32_t addr, data = 0; - - /* read filter mask at first */ - addr = ISISC_RULE_FUNC_ADDR; - data = (flt_idx & 0x7f) | (0x1 << 8) | (0x1 << 10) | (0x1 << 31); - HSL_REG_ENTRY_GEN_SET(rv, dev_id, addr, sizeof (a_uint32_t), - (a_uint8_t *) (&data), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - - /* get filter mask and modify it */ - addr = ISISC_RULE_FUNC_ADDR + 20; - HSL_REG_ENTRY_GEN_GET(rv, dev_id, addr, sizeof (a_uint32_t), - (a_uint8_t *) (&data), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - - data &= 0xfffffff8; - data |= (flag & 0x7); - HSL_REG_ENTRY_GEN_SET(rv, dev_id, addr, sizeof (a_uint32_t), - (a_uint8_t *) (&data), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - - /* write back filter mask */ - addr = ISISC_RULE_FUNC_ADDR; - data = (flt_idx & 0x7f) | (0x1 << 8) | (0x1 << 31); - HSL_REG_ENTRY_GEN_SET(rv, dev_id, addr, sizeof (a_uint32_t), - (a_uint8_t *) (&data), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - - return SW_OK; -#endif -#endif -} - -static sw_error_t -_isisc_filter_ports_bind(a_uint32_t dev_id, a_uint32_t flt_idx, a_uint32_t ports) -{ -#ifdef ISISC_SW_ENTRY - hw_filter_t filter; - - _isisc_filter_up_to_sw(dev_id, &filter, flt_idx); - - filter.vlu[4] &= 0xffffff80; - filter.vlu[4] |= (ports & 0x7f); - - _isisc_filter_down_to_hw(dev_id, &filter, flt_idx); - - return SW_OK; -#else -#ifdef ISISC_HW_ENTRY - hw_filter_t filter; - - filter = sw_rule_ent[dev_id][flt_idx].filter; - - filter.vlu[4] &= 0xffffff80; - filter.vlu[4] |= (ports & 0x7f); - - _isisc_filter_down_to_hw(dev_id, &filter, flt_idx); - - return SW_OK; -#else - sw_error_t rv; - a_uint32_t addr, data; - - /* read filter value at first */ - addr = ISISC_RULE_FUNC_ADDR; - data = (flt_idx & 0x7f) | (0x1 << 10) | (0x1 << 31); - HSL_REG_ENTRY_GEN_SET(rv, dev_id, addr, sizeof (a_uint32_t), - (a_uint8_t *) (&data), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - - /* get filter value and modify it */ - addr = ISISC_RULE_FUNC_ADDR + 20; - HSL_REG_ENTRY_GEN_GET(rv, dev_id, addr, sizeof (a_uint32_t), - (a_uint8_t *) (&data), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - - data &= 0xffffff80; - data |= (ports & 0x7f); - HSL_REG_ENTRY_GEN_SET(rv, dev_id, addr, sizeof (a_uint32_t), - (a_uint8_t *) (&data), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - - /* write back filter value */ - addr = ISISC_RULE_FUNC_ADDR; - data = (flt_idx & 0x7f) | (0x1 << 31); - HSL_REG_ENTRY_GEN_SET(rv, dev_id, addr, sizeof (a_uint32_t), - (a_uint8_t *) (&data), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - - return SW_OK; -#endif -#endif -} - -#ifdef ISISC_SW_ENTRY -static sw_error_t -_isisc_filter_write(a_uint32_t dev_id, a_uint32_t reg[], a_uint32_t flt_idx, - a_uint32_t op) -{ - a_uint32_t i, addr, data, idx = 6; - sw_error_t rv; - - if (ISISC_FILTER_ACT_OP == op) - { - idx = 4; - } - - for (i = 1; i < idx; i++) - { - addr = ISISC_RULE_FUNC_ADDR + (i << 2); - HSL_REG_ENTRY_GEN_SET(rv, dev_id, addr, sizeof (a_uint32_t), - (a_uint8_t *) (&(reg[i - 1])), - sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - } - - addr = ISISC_RULE_FUNC_ADDR; - data = (flt_idx & 0x7f) | (op << 8) | (0x1 << 31); - HSL_REG_ENTRY_GEN_SET(rv, dev_id, addr, sizeof (a_uint32_t), - (a_uint8_t *) (&data), sizeof (a_uint32_t)); - - return rv; -} - -static sw_error_t -_isisc_filter_read(a_uint32_t dev_id, a_uint32_t reg[], a_uint32_t flt_idx, - a_uint32_t op) -{ - a_uint32_t i, addr, data, idx = 6; - sw_error_t rv; - - addr = ISISC_RULE_FUNC_ADDR; - data = (flt_idx & 0x7f) | (op << 8) | (0x1 << 10) | (0x1 << 31); - HSL_REG_ENTRY_GEN_SET(rv, dev_id, addr, sizeof (a_uint32_t), - (a_uint8_t *) (&data), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - - if (ISISC_FILTER_ACT_OP == op) - { - idx = 4; - } - - for (i = 1; i < idx; i++) - { - addr = ISISC_RULE_FUNC_ADDR + (i << 2); - HSL_REG_ENTRY_GEN_GET(rv, dev_id, addr, sizeof (a_uint32_t), - (a_uint8_t *) (&(reg[i - 1])), - sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - } - - return SW_OK; -} -#endif - -static sw_error_t -_isisc_filter_down_to_hw(a_uint32_t dev_id, hw_filter_t * filter, - a_uint32_t flt_idx) -{ -#ifdef ISISC_SW_ENTRY - a_uint8_t *tbl = sw_filter_mem + sizeof (hw_filter_t) * flt_idx; - - aos_mem_copy(tbl, filter, sizeof (hw_filter_t)); -#else -#ifdef ISISC_HW_ENTRY - sw_error_t rv; - a_uint32_t i, base, addr; - - base = ISISC_FILTER_ACT_ADDR + (flt_idx << 4); - for (i = 0; i < 3; i++) - { - addr = base + (i << 2); - HSL_REG_ENTRY_GEN_SET(rv, dev_id, addr, sizeof (a_uint32_t), - (a_uint8_t *) (&(filter->act[i])), - sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - } - - base = ISISC_FILTER_VLU_ADDR + (flt_idx << 5); - for (i = 0; i < 5; i++) - { - addr = base + (i << 2); - HSL_REG_ENTRY_GEN_SET(rv, dev_id, addr, sizeof (a_uint32_t), - (a_uint8_t *) (&(filter->vlu[i])), - sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - } - - base = ISISC_FILTER_MSK_ADDR + (flt_idx << 5); - for (i = 0; i < 5; i++) - { - addr = base + (i << 2); - HSL_REG_ENTRY_GEN_SET(rv, dev_id, addr, sizeof (a_uint32_t), - (a_uint8_t *) (&(filter->msk[i])), - sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - } -#else - sw_error_t rv; - - rv = _isisc_filter_write(dev_id, &(filter->act[0]), flt_idx, - ISISC_FILTER_ACT_OP); - SW_RTN_ON_ERROR(rv); - - rv = _isisc_filter_write(dev_id, &(filter->vlu[0]), flt_idx, - ISISC_FILTER_VLU_OP); - SW_RTN_ON_ERROR(rv); - - rv = _isisc_filter_write(dev_id, &(filter->msk[0]), flt_idx, - ISISC_FILTER_MSK_OP); - SW_RTN_ON_ERROR(rv); -#endif -#endif - - return SW_OK; -} - -static sw_error_t -_isisc_filter_up_to_sw(a_uint32_t dev_id, hw_filter_t * filter, - a_uint32_t flt_idx) -{ -#ifdef ISISC_SW_ENTRY - a_uint8_t *tbl = sw_filter_mem + sizeof (hw_filter_t) * flt_idx; - - aos_mem_copy(filter, tbl, sizeof (hw_filter_t)); -#else -#ifdef ISISC_HW_ENTRY - sw_error_t rv; - a_uint32_t i, base, addr; - - base = ISISC_FILTER_VLU_ADDR + (flt_idx << 5); - for (i = 0; i < 5; i++) - { - addr = base + (i << 2); - HSL_REG_ENTRY_GEN_GET(rv, dev_id, addr, sizeof (a_uint32_t), - (a_uint8_t *) (&(filter->vlu[i])), - sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - } - - base = ISISC_FILTER_MSK_ADDR + (flt_idx << 5); - for (i = 0; i < 5; i++) - { - addr = base + (i << 2); - HSL_REG_ENTRY_GEN_GET(rv, dev_id, addr, sizeof (a_uint32_t), - (a_uint8_t *) (&(filter->msk[i])), - sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - } - - base = ISISC_FILTER_ACT_ADDR + (flt_idx << 4); - for (i = 0; i < 3; i++) - { - addr = base + (i << 2); - HSL_REG_ENTRY_GEN_GET(rv, dev_id, addr, sizeof (a_uint32_t), - (a_uint8_t *) (&(filter->act[i])), - sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - } -#else - sw_error_t rv; - - rv = _isisc_filter_read(dev_id, &(filter->vlu[0]), flt_idx, - ISISC_FILTER_VLU_OP); - SW_RTN_ON_ERROR(rv); - - rv = _isisc_filter_read(dev_id, &(filter->msk[0]), flt_idx, - ISISC_FILTER_MSK_OP); - SW_RTN_ON_ERROR(rv); - - rv = _isisc_filter_read(dev_id, &(filter->act[0]), flt_idx, - ISISC_FILTER_ACT_OP); - SW_RTN_ON_ERROR(rv); -#endif -#endif - - return SW_OK; -} - -static sw_error_t -_isisc_acl_list_insert(a_uint32_t dev_id, a_uint32_t * src_idx, - a_uint32_t * dst_idx, isisc_acl_rule_t * src_rule, - isisc_acl_rule_t * dst_rule) -{ - a_uint32_t i, data, rule_id, list_id, list_pri; - - rule_id = 0; - list_id = src_rule[*src_idx].list_id; - list_pri = src_rule[*src_idx].list_pri; - - for (i = *src_idx; i < ISISC_MAX_FILTER; i++) - { - if (!(ENT_USED & src_rule[i].status)) - { - continue; // was: break; - } - - if (src_rule[i].list_id != list_id) - { - break; - } - - SW_GET_FIELD_BY_REG(MAC_RUL_M4, RULE_TYP, data, - src_rule[i].filter.msk[4]); - if (!data) - { - continue; - } - - if (ISISC_MAX_FILTER <= *dst_idx) - { - return SW_NO_RESOURCE; - } - - if (ENT_USED & dst_rule[*dst_idx].status) - { - return SW_NO_RESOURCE; - } - - SW_GET_FIELD_BY_REG(MAC_RUL_M4, RULE_VALID, data, - src_rule[i].filter.msk[4]); - if ((FLT_START == data) && (*dst_idx % 2)) - { - if (*src_idx != i) - { - dst_rule[*dst_idx].src_flt_dis = src_rule[i].src_flt_dis; - dst_rule[*dst_idx].list_id = list_id; - dst_rule[*dst_idx].list_pri = list_pri; - dst_rule[*dst_idx].rule_id = rule_id - 1; - dst_rule[*dst_idx].status |= ENT_USED; - } - - (*dst_idx)++; - if (ISISC_MAX_FILTER <= *dst_idx) - { - return SW_NO_RESOURCE; - } - - if (ENT_USED & dst_rule[*dst_idx].status) - { - return SW_NO_RESOURCE; - } - } - - aos_mem_copy(&(dst_rule[*dst_idx].filter), &(src_rule[i].filter), - sizeof (hw_filter_t)); - dst_rule[*dst_idx].src_flt_dis = src_rule[i].src_flt_dis; - dst_rule[*dst_idx].list_id = list_id; - dst_rule[*dst_idx].list_pri = list_pri; - dst_rule[*dst_idx].rule_id = rule_id; - dst_rule[*dst_idx].status |= ENT_USED; - if (ENT_DEACTIVE & src_rule[i].status) - { - dst_rule[*dst_idx].status |= ENT_DEACTIVE; - } - (*dst_idx)++; - - if ((FLT_END == data) && (*dst_idx % 2)) - { - if (ISISC_MAX_FILTER > *dst_idx) - { - dst_rule[*dst_idx].src_flt_dis = src_rule[i].src_flt_dis; - dst_rule[*dst_idx].list_id = list_id; - dst_rule[*dst_idx].list_pri = list_pri; - dst_rule[*dst_idx].rule_id = rule_id; - dst_rule[*dst_idx].status |= ENT_USED; - (*dst_idx)++; - } - } - - if ((FLT_END == data) || (FLT_STARTEND == data)) - { - rule_id++; - } - } - - *src_idx = i; - return SW_OK; -} - -static sw_error_t -_isisc_acl_rule_alloc(a_uint32_t dev_id, isisc_acl_list_t * sw_list, - a_uint32_t filter_nr) -{ - a_uint32_t free_flt_nr, load_idx, begin_idx, start_idx, end_idx, i; - a_uint32_t largest_nr, largest_idx; - sw_error_t rv; - - /* calculate the proper location, [start_idx, end_idx) */ - start_idx = 0; - end_idx = ISISC_MAX_FILTER; - for (i = 0; i < ISISC_MAX_FILTER; i++) - { - if (ENT_USED & sw_rule_ent[dev_id][i].status) - { - if (sw_rule_ent[dev_id][i].list_pri < sw_list->list_pri) - { - start_idx = i + 1; - } - else if (sw_rule_ent[dev_id][i].list_pri > sw_list->list_pri) - { - end_idx = i; - break; - } - } - } - - /* find the larget free filters block */ - largest_nr = 0; - largest_idx = 0; - free_flt_nr = 0; - begin_idx = start_idx; - for (i = start_idx; i < end_idx; i++) - { - if (!(ENT_USED & sw_rule_ent[dev_id][i].status)) - { - free_flt_nr++; - } - else - { - if (free_flt_nr > largest_nr) - { - largest_nr = free_flt_nr; - largest_idx = begin_idx; - } - free_flt_nr = 0; - begin_idx = i + 1; - } - } - - if (free_flt_nr > largest_nr) - { - largest_nr = free_flt_nr; - largest_idx = begin_idx; - } - - if ((!largest_nr) || ((largest_nr + 1) < filter_nr)) - { - return SW_NO_RESOURCE; - } - - for (i = 0; i < ISISC_MAX_FILTER; i++) - { - if (ENT_USED & sw_rule_ent[dev_id][i].status) - { - aos_mem_copy(&(sw_rule_tmp[dev_id][i]), &(sw_rule_ent[dev_id][i]), - sizeof (isisc_acl_rule_t)); - } - } - - begin_idx = 0; - load_idx = largest_idx; - rv = _isisc_acl_list_insert(dev_id, &begin_idx, &load_idx, - hw_rule_tmp[dev_id], sw_rule_tmp[dev_id]); - return rv; -} - -static sw_error_t -_isisc_acl_rule_reorder(a_uint32_t dev_id, isisc_acl_list_t * sw_list) -{ - a_uint32_t i, src_idx, dst_idx; - sw_error_t rv; - - dst_idx = 0; - for (i = 0; i < ISISC_MAX_FILTER;) - { - if (ENT_USED & sw_rule_ent[dev_id][i].status) - { - if (sw_rule_ent[dev_id][i].list_pri <= sw_list->list_pri) - { - rv = _isisc_acl_list_insert(dev_id, &i, &dst_idx, - sw_rule_ent[dev_id], - sw_rule_tmp[dev_id]); - SW_RTN_ON_ERROR(rv); - } - else - { - break; - } - } - else - { - i++; - } - } - - src_idx = 0; - rv = _isisc_acl_list_insert(dev_id, &src_idx, &dst_idx, hw_rule_tmp[dev_id], - sw_rule_tmp[dev_id]); - SW_RTN_ON_ERROR(rv); - - for (; i < ISISC_MAX_FILTER;) - { - if (ENT_USED & sw_rule_ent[dev_id][i].status) - { - rv = _isisc_acl_list_insert(dev_id, &i, &dst_idx, - sw_rule_ent[dev_id], - sw_rule_tmp[dev_id]); - SW_RTN_ON_ERROR(rv); - } - else - { - i++; - } - } - - return SW_OK; -} - -static void -_isisc_acl_rule_sync(a_uint32_t dev_id, a_uint32_t flt_idx, a_uint32_t flt_nr) -{ - a_uint32_t i, data; - - for (i = flt_idx; i < (flt_idx + flt_nr); i++) - { - if (aos_mem_cmp - (&(sw_rule_ent[dev_id][i]), &(sw_rule_tmp[dev_id][i]), - sizeof (isisc_acl_rule_t))) - { - SW_GET_FIELD_BY_REG(MAC_RUL_M4, RULE_TYP, data, - sw_rule_tmp[dev_id][i].filter.msk[4]); - if (data) - { - _isisc_filter_down_to_hw(dev_id, - &(sw_rule_tmp[dev_id][i].filter), i); - } - else - { - _isisc_filter_valid_set(dev_id, i, 0); - } - - aos_mem_copy(&(sw_rule_ent[dev_id][i]), &(sw_rule_tmp[dev_id][i]), - sizeof (isisc_acl_rule_t)); - _isisc_acl_rule_src_filter_sts_set(dev_id, i, - !sw_rule_tmp[dev_id][i].src_flt_dis); - } - } -} - -static sw_error_t -_isisc_acl_list_creat(a_uint32_t dev_id, a_uint32_t list_id, a_uint32_t list_pri) -{ - a_uint32_t i, loc = ISISC_MAX_FILTER; - isisc_acl_list_t *sw_list; - - HSL_DEV_ID_CHECK(dev_id); - - if ((ISISC_MAX_LIST_ID < list_id) || (ISISC_MAX_LIST_PRI < list_pri)) - { - return SW_NOT_SUPPORTED; - } - - for (i = 0; i < ISISC_MAX_FILTER; i++) - { - sw_list = &(sw_list_ent[dev_id][i]); - if (ENT_USED & sw_list->status) - { - if (list_id == sw_list->list_id) - { - return SW_ALREADY_EXIST; - } - } - else - { - loc = i; - } - } - - if (ISISC_MAX_FILTER == loc) - { - return SW_NO_RESOURCE; - } - - sw_list = &(sw_list_ent[dev_id][loc]); - aos_mem_zero(sw_list, sizeof (isisc_acl_list_t)); - sw_list->list_id = list_id; - sw_list->list_pri = list_pri; - sw_list->status |= ENT_USED; - return SW_OK; -} - -static sw_error_t -_isisc_acl_list_destroy(a_uint32_t dev_id, a_uint32_t list_id) -{ - isisc_acl_list_t *sw_list; - - HSL_DEV_ID_CHECK(dev_id); - - if (ISISC_MAX_LIST_ID < list_id) - { - return SW_NOT_SUPPORTED; - } - - sw_list = _isisc_acl_list_loc(dev_id, list_id); - if (NULL == sw_list) - { - return SW_NOT_FOUND; - } - - if (0 != sw_list->bind_pts) - { - return SW_NOT_SUPPORTED; - } - - if (0 != sw_list->rule_nr) - { - return SW_NOT_SUPPORTED; - } - - aos_mem_zero(sw_list, sizeof (isisc_acl_list_t)); - return SW_OK; -} - -static sw_error_t -_isisc_acl_rule_add(a_uint32_t dev_id, a_uint32_t list_id, - a_uint32_t rule_id, a_uint32_t rule_nr, - fal_acl_rule_t * rule) -{ - sw_error_t rv; - isisc_acl_list_t *sw_list; - isisc_acl_rule_t *sw_rule; - a_uint32_t i, free_flt_nr, old_flt_nr, old_flt_idx, new_flt_nr, bind_pts; - - HSL_DEV_ID_CHECK(dev_id); - - if (ISISC_MAX_LIST_ID < list_id) - { - return SW_NOT_SUPPORTED; - } - - if ((0 == rule_nr) || (NULL == rule)) - { - return SW_BAD_PARAM; - } - - sw_list = _isisc_acl_list_loc(dev_id, list_id); - if (NULL == sw_list) - { - return SW_NOT_FOUND; - } - - if (rule_id != sw_list->rule_nr) - { - return SW_BAD_PARAM; - } - - old_flt_idx = 0; - old_flt_nr = 0; - free_flt_nr = 0; - aos_mem_zero(hw_rule_tmp[dev_id], - ISISC_HW_RULE_TMP_CNT * sizeof (isisc_acl_rule_t)); - aos_mem_zero(sw_rule_tmp[dev_id], - ISISC_MAX_FILTER * sizeof (isisc_acl_rule_t)); - for (i = 0; i < ISISC_MAX_FILTER; i++) - { - sw_rule = &(sw_rule_ent[dev_id][i]); - if (ENT_USED & sw_rule->status) - { - if (sw_rule->list_id == sw_list->list_id) - { - aos_mem_copy(&(hw_rule_tmp[dev_id][old_flt_nr]), sw_rule, - sizeof (isisc_acl_rule_t)); - if (!old_flt_nr) - { - old_flt_idx = i; - } - old_flt_nr++; - } - } - else - { - free_flt_nr++; - } - } - - if (!free_flt_nr) - { - return SW_NO_RESOURCE; - } - - /* parse rule entry and alloc rule resource */ - new_flt_nr = old_flt_nr; - for (i = 0; i < rule_nr; i++) - { - rv = _isisc_acl_rule_sw_to_hw(dev_id, &rule[i], hw_rule_tmp[dev_id], - &new_flt_nr); - SW_RTN_ON_ERROR(rv); - } - - if (free_flt_nr < (new_flt_nr - old_flt_nr)) - { - return SW_NO_RESOURCE; - } - - for (i = old_flt_nr; i < new_flt_nr; i++) - { - hw_rule_tmp[dev_id][i].status |= ENT_USED; - hw_rule_tmp[dev_id][i].list_id = sw_list->list_id; - hw_rule_tmp[dev_id][i].list_pri = sw_list->list_pri; - bind_pts = sw_list->bind_pts; - SW_SET_REG_BY_FIELD(MAC_RUL_V4, SRC_PT, bind_pts, - (hw_rule_tmp[dev_id][i].filter.vlu[4])); - } - - for (i = 0; i < old_flt_nr; i++) - { - sw_rule = &(sw_rule_ent[dev_id][old_flt_idx + i]); - sw_rule->status &= (~ENT_USED); - sw_rule->status |= (ENT_TMP); - } - - rv = _isisc_acl_rule_alloc(dev_id, sw_list, new_flt_nr); - if (SW_OK != rv) - { - aos_mem_zero(sw_rule_tmp[dev_id], - ISISC_MAX_FILTER * sizeof (isisc_acl_rule_t)); - rv = _isisc_acl_rule_reorder(dev_id, sw_list); - } - - for (i = 0; i < old_flt_nr; i++) - { - sw_rule = &(sw_rule_ent[dev_id][i + old_flt_idx]); - sw_rule->status |= (ENT_USED); - sw_rule->status &= (~ENT_TMP); - } - SW_RTN_ON_ERROR(rv); - - _isisc_acl_rule_sync(dev_id, 0, ISISC_MAX_FILTER); - sw_list->rule_nr += rule_nr; - - _isisc_acl_sw_rule_dump("sw rule after add", sw_rule_ent[dev_id]); - return SW_OK; -} - -static sw_error_t -_isisc_acl_rule_delete(a_uint32_t dev_id, a_uint32_t list_id, - a_uint32_t rule_id, a_uint32_t rule_nr) -{ - isisc_acl_rule_t *sw_rule; - isisc_acl_list_t *sw_list; - a_uint32_t i, flt_idx = 0, src_idx, dst_idx, del_nr = 0, flt_nr = 0; - sw_error_t rv; - - HSL_DEV_ID_CHECK(dev_id); - - if (ISISC_MAX_LIST_ID < list_id) - { - return SW_NOT_SUPPORTED; - } - - sw_list = _isisc_acl_list_loc(dev_id, list_id); - if (NULL == sw_list) - { - return SW_NOT_FOUND; - } - - if (sw_list->rule_nr < (rule_id + rule_nr)) - { - return SW_BAD_PARAM; - } - - aos_mem_zero(hw_rule_tmp[dev_id], - ISISC_HW_RULE_TMP_CNT * sizeof (isisc_acl_rule_t)); - aos_mem_zero(sw_rule_tmp[dev_id], - ISISC_MAX_FILTER * sizeof (isisc_acl_rule_t)); - - for (i = 0; i < ISISC_MAX_FILTER; i++) - { - sw_rule = &(sw_rule_ent[dev_id][i]); - if ((ENT_USED & sw_rule->status) && (sw_rule->list_id == list_id)) - { - if (!flt_nr) - { - flt_idx = i; - } - - if ((sw_rule->rule_id >= rule_id) - && (sw_rule->rule_id < (rule_id + rule_nr))) - { - del_nr++; - } - else - { - aos_mem_copy(&(hw_rule_tmp[dev_id][flt_idx + flt_nr]), sw_rule, - sizeof (isisc_acl_rule_t)); - } - flt_nr++; - } - } - - if (!del_nr) - { - return SW_NOT_FOUND; - } - - _isisc_acl_sw_rule_dump("hw rule before del", hw_rule_tmp[dev_id]); - - for (i = 0; i < flt_nr; i++) - { - sw_rule = &(hw_rule_tmp[dev_id][flt_idx + i]); - if (ENT_USED & sw_rule->status) - { - break; - } - } - - if (i != flt_nr) - { - src_idx = flt_idx + i; - dst_idx = flt_idx; - rv = _isisc_acl_list_insert(dev_id, &src_idx, &dst_idx, - hw_rule_tmp[dev_id], sw_rule_tmp[dev_id]); - SW_RTN_ON_ERROR(rv); - } - - _isisc_acl_rule_sync(dev_id, flt_idx, flt_nr); - sw_list->rule_nr -= rule_nr; - - _isisc_acl_sw_rule_dump("sw rule after del", sw_rule_ent[dev_id]); - return SW_OK; -} - -static sw_error_t -_isisc_acl_rule_query(a_uint32_t dev_id, a_uint32_t list_id, - a_uint32_t rule_id, fal_acl_rule_t * rule) -{ - sw_error_t rv; - isisc_acl_rule_t *sw_rule; - a_uint32_t flt_nr = 0, i; - - HSL_DEV_ID_CHECK(dev_id); - - if (ISISC_MAX_LIST_ID < list_id) - { - return SW_NOT_SUPPORTED; - } - - aos_mem_zero(hw_rule_tmp[dev_id], - ISISC_HW_RULE_TMP_CNT * sizeof (isisc_acl_rule_t)); - for (i = 0; i < ISISC_MAX_FILTER; i++) - { - sw_rule = &(sw_rule_ent[dev_id][i]); - if (ENT_USED & sw_rule->status) - { - if ((sw_rule->list_id == list_id) && (sw_rule->rule_id == rule_id)) - { - aos_mem_copy(&(hw_rule_tmp[dev_id][flt_nr]), sw_rule, - sizeof (isisc_acl_rule_t)); - flt_nr++; - } - } - } - - if (!flt_nr) - { - return SW_NOT_FOUND; - } - - aos_mem_zero(rule, sizeof (fal_acl_rule_t)); - rv = _isisc_acl_rule_hw_to_sw(dev_id, rule, hw_rule_tmp[dev_id], 0, flt_nr); - return rv; -} - -static sw_error_t -_isisc_acl_rule_bind(a_uint32_t dev_id, a_uint32_t list_id, a_uint32_t ports) -{ - sw_error_t rv; - a_uint32_t i; - isisc_acl_rule_t *sw_rule; - - for (i = 0; i < ISISC_MAX_FILTER; i++) - { - sw_rule = &(sw_rule_ent[dev_id][i]); - - if ((ENT_USED & sw_rule->status) - && (list_id == sw_rule->list_id) - && (!(ENT_DEACTIVE & sw_rule->status))) - { - rv = _isisc_filter_ports_bind(dev_id, i, ports); - SW_RTN_ON_ERROR(rv); - - SW_SET_REG_BY_FIELD(MAC_RUL_V4, SRC_PT, ports, - (sw_rule->filter.vlu[4])); - } - } - - return SW_OK; -} - -static sw_error_t -_isisc_acl_list_bind(a_uint32_t dev_id, a_uint32_t list_id, - fal_acl_direc_t direc, fal_acl_bind_obj_t obj_t, - a_uint32_t obj_idx) -{ - sw_error_t rv; - a_uint32_t ports; - isisc_acl_list_t *sw_list; - - HSL_DEV_ID_CHECK(dev_id); - - if (ISISC_MAX_LIST_ID < list_id) - { - return SW_NOT_SUPPORTED; - } - - if (FAL_ACL_DIREC_IN != direc) - { - return SW_NOT_SUPPORTED; - } - - sw_list = _isisc_acl_list_loc(dev_id, list_id); - if (NULL == sw_list) - { - return SW_NOT_FOUND; - } - - if (FAL_ACL_BIND_PORT == obj_t) - { - ports = (sw_list->bind_pts) | (0x1 << obj_idx); - } - else if (FAL_ACL_BIND_PORTBITMAP == obj_t) - { - ports = (sw_list->bind_pts) | obj_idx; - } - else - { - return SW_NOT_SUPPORTED; - } - - rv = _isisc_acl_rule_bind(dev_id, list_id, ports); - SW_RTN_ON_ERROR(rv); - - sw_list->bind_pts = ports; - return SW_OK; -} - -static sw_error_t -_isisc_acl_list_unbind(a_uint32_t dev_id, a_uint32_t list_id, - fal_acl_direc_t direc, fal_acl_bind_obj_t obj_t, - a_uint32_t obj_idx) -{ - sw_error_t rv; - a_uint32_t ports; - isisc_acl_list_t *sw_list; - - HSL_DEV_ID_CHECK(dev_id); - - if (ISISC_MAX_LIST_ID < list_id) - { - return SW_NOT_SUPPORTED; - } - - if (FAL_ACL_DIREC_IN != direc) - { - return SW_NOT_SUPPORTED; - } - - sw_list = _isisc_acl_list_loc(dev_id, list_id); - if (NULL == sw_list) - { - return SW_NOT_FOUND; - } - - if (FAL_ACL_BIND_PORT == obj_t) - { - ports = (sw_list->bind_pts) & (~(0x1UL << obj_idx)); - } - else if (FAL_ACL_BIND_PORTBITMAP == obj_t) - { - ports = (sw_list->bind_pts) & (~obj_idx); - } - else - { - return SW_NOT_SUPPORTED; - } - - rv = _isisc_acl_rule_bind(dev_id, list_id, ports); - SW_RTN_ON_ERROR(rv); - - sw_list->bind_pts = ports; - return SW_OK; -} - -static sw_error_t -_isisc_acl_status_set(a_uint32_t dev_id, a_bool_t enable) -{ - sw_error_t rv; - a_uint32_t val; - - HSL_DEV_ID_CHECK(dev_id); - - if (A_TRUE == enable) - { - val = 1; - } - else if (A_FALSE == enable) - { - val = 0; - } - else - { - return SW_BAD_PARAM; - } - - HSL_REG_FIELD_SET(rv, dev_id, MOD_ENABLE, 0, ACL_EN, (a_uint8_t *) (&val), - sizeof (a_uint32_t)); - return rv; -} - -static sw_error_t -_isisc_acl_status_get(a_uint32_t dev_id, a_bool_t * enable) -{ - sw_error_t rv; - a_uint32_t val = 0; - - HSL_DEV_ID_CHECK(dev_id); - - HSL_REG_FIELD_GET(rv, dev_id, MOD_ENABLE, 0, ACL_EN, (a_uint8_t *) (&val), - sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - - if (val) - { - *enable = A_TRUE; - } - else - { - *enable = A_FALSE; - } - - return SW_OK; -} - -static sw_error_t -_isisc_acl_port_udf_profile_set(a_uint32_t dev_id, fal_port_t port_id, - fal_acl_udf_type_t udf_type, a_uint32_t offset, - a_uint32_t length) -{ - sw_error_t rv; - a_uint32_t reg = 0; - - HSL_DEV_ID_CHECK(dev_id); - - if (ISISC_UDF_MAX_OFFSET < offset) - { - return SW_BAD_PARAM; - } - - if (ISISC_UDF_MAX_OFFSET < length) - { - return SW_BAD_PARAM; - } - - if ((FAL_ACL_UDF_TYPE_L2_SNAP == udf_type) - || (FAL_ACL_UDF_TYPE_L3_PLUS == udf_type)) - { - HSL_REG_ENTRY_GET(rv, dev_id, WIN_RULE_CTL1, port_id, - (a_uint8_t *) (®), sizeof (a_uint32_t)); - } - else - { - HSL_REG_ENTRY_GET(rv, dev_id, WIN_RULE_CTL0, port_id, - (a_uint8_t *) (®), sizeof (a_uint32_t)); - } - SW_RTN_ON_ERROR(rv); - - switch (udf_type) - { - case FAL_ACL_UDF_TYPE_L2: - SW_SET_REG_BY_FIELD(WIN_RULE_CTL0, L2_OFFSET, offset, reg); - SW_SET_REG_BY_FIELD(WIN_RULE_CTL0, L2_LENGTH, length, reg); - break; - case FAL_ACL_UDF_TYPE_L3: - SW_SET_REG_BY_FIELD(WIN_RULE_CTL0, L3_OFFSET, offset, reg); - SW_SET_REG_BY_FIELD(WIN_RULE_CTL0, L3_LENGTH, length, reg); - break; - case FAL_ACL_UDF_TYPE_L4: - SW_SET_REG_BY_FIELD(WIN_RULE_CTL0, L4_OFFSET, offset, reg); - SW_SET_REG_BY_FIELD(WIN_RULE_CTL0, L4_LENGTH, length, reg); - break; - case FAL_ACL_UDF_TYPE_L2_SNAP: - SW_SET_REG_BY_FIELD(WIN_RULE_CTL1, L2S_OFFSET, offset, reg); - SW_SET_REG_BY_FIELD(WIN_RULE_CTL1, L2S_LENGTH, length, reg); - break; - case FAL_ACL_UDF_TYPE_L3_PLUS: - SW_SET_REG_BY_FIELD(WIN_RULE_CTL1, L3P_OFFSET, offset, reg); - SW_SET_REG_BY_FIELD(WIN_RULE_CTL1, L3P_LENGTH, length, reg); - break; - default: - return SW_BAD_PARAM; - } - - if ((FAL_ACL_UDF_TYPE_L2_SNAP == udf_type) - || (FAL_ACL_UDF_TYPE_L3_PLUS == udf_type)) - { - HSL_REG_ENTRY_SET(rv, dev_id, WIN_RULE_CTL1, port_id, - (a_uint8_t *) (®), sizeof (a_uint32_t)); - } - else - { - HSL_REG_ENTRY_SET(rv, dev_id, WIN_RULE_CTL0, port_id, - (a_uint8_t *) (®), sizeof (a_uint32_t)); - } - - return rv; -} - -static sw_error_t -_isisc_acl_port_udf_profile_get(a_uint32_t dev_id, fal_port_t port_id, - fal_acl_udf_type_t udf_type, a_uint32_t * offset, - a_uint32_t * length) -{ - sw_error_t rv; - a_uint32_t reg = 0; - - HSL_DEV_ID_CHECK(dev_id); - - if ((FAL_ACL_UDF_TYPE_L2_SNAP == udf_type) - || (FAL_ACL_UDF_TYPE_L3_PLUS == udf_type)) - { - HSL_REG_ENTRY_GET(rv, dev_id, WIN_RULE_CTL1, port_id, - (a_uint8_t *) (®), sizeof (a_uint32_t)); - } - else - { - HSL_REG_ENTRY_GET(rv, dev_id, WIN_RULE_CTL0, port_id, - (a_uint8_t *) (®), sizeof (a_uint32_t)); - } - SW_RTN_ON_ERROR(rv); - - switch (udf_type) - { - case FAL_ACL_UDF_TYPE_L2: - SW_GET_FIELD_BY_REG(WIN_RULE_CTL0, L2_OFFSET, (*offset), reg); - SW_GET_FIELD_BY_REG(WIN_RULE_CTL0, L2_LENGTH, (*length), reg); - break; - case FAL_ACL_UDF_TYPE_L3: - SW_GET_FIELD_BY_REG(WIN_RULE_CTL0, L3_OFFSET, (*offset), reg); - SW_GET_FIELD_BY_REG(WIN_RULE_CTL0, L3_LENGTH, (*length), reg); - break; - case FAL_ACL_UDF_TYPE_L4: - SW_GET_FIELD_BY_REG(WIN_RULE_CTL0, L4_OFFSET, (*offset), reg); - SW_GET_FIELD_BY_REG(WIN_RULE_CTL0, L4_LENGTH, (*length), reg); - break; - case FAL_ACL_UDF_TYPE_L2_SNAP: - SW_GET_FIELD_BY_REG(WIN_RULE_CTL1, L2S_OFFSET, (*offset), reg); - SW_GET_FIELD_BY_REG(WIN_RULE_CTL1, L2S_LENGTH, (*length), reg); - break; - case FAL_ACL_UDF_TYPE_L3_PLUS: - SW_GET_FIELD_BY_REG(WIN_RULE_CTL1, L3P_OFFSET, (*offset), reg); - SW_GET_FIELD_BY_REG(WIN_RULE_CTL1, L3P_LENGTH, (*length), reg); - break; - default: - return SW_BAD_PARAM; - } - - return SW_OK; -} - -static sw_error_t -_isisc_acl_rule_active(a_uint32_t dev_id, a_uint32_t list_id, - a_uint32_t rule_id, a_uint32_t rule_nr, a_bool_t active) -{ - sw_error_t rv; - a_uint32_t i, ports; - isisc_acl_list_t *sw_list; - isisc_acl_rule_t *sw_rule; - - HSL_DEV_ID_CHECK(dev_id); - - sw_list = _isisc_acl_list_loc(dev_id, list_id); - if (NULL == sw_list) - { - return SW_NOT_FOUND; - } - - if (sw_list->rule_nr < (rule_id + rule_nr)) - { - return SW_BAD_PARAM; - } - - if (A_TRUE == active) - { - ports = (sw_list->bind_pts); - } - else - { - ports = 0; - } - - for (i = 0; i < ISISC_MAX_FILTER; i++) - { - sw_rule = &(sw_rule_ent[dev_id][i]); - - if ((ENT_USED & sw_rule->status) - && (list_id == sw_rule->list_id) - && (rule_id <= sw_rule->rule_id) - && ((rule_id + rule_nr) > sw_rule->rule_id)) - { - rv = _isisc_filter_ports_bind(dev_id, i, ports); - SW_RTN_ON_ERROR(rv); - - SW_SET_REG_BY_FIELD(MAC_RUL_V4, SRC_PT, ports, - (sw_rule->filter.vlu[4])); - - if (A_TRUE == active) - { - sw_rule->status &= (~ENT_DEACTIVE); - } - else - { - sw_rule->status |= (ENT_DEACTIVE); - } - } - } - - return SW_OK; -} - -static sw_error_t -_isisc_acl_rule_src_filter_sts_set(a_uint32_t dev_id, - a_uint32_t rule_id, a_bool_t enable) -{ - sw_error_t rv; - a_uint32_t reg = 0, regIdx; - isisc_acl_rule_t *sw_rule; - - HSL_DEV_ID_CHECK(dev_id); - - sw_rule = &sw_rule_ent[dev_id][rule_id]; - if (!(ENT_USED & sw_rule->status)) - { - return SW_NOT_FOUND; - } - - regIdx = rule_id >> 5; - - HSL_REG_ENTRY_GET(rv, dev_id, ACL_FWD_SRC_FILTER_CTL0, regIdx, - (a_uint8_t *) (®), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - - if (A_TRUE == enable) - { - reg |= (0x1 << (rule_id & 0x1F)); - sw_rule->src_flt_dis = 0; - } - else if (A_FALSE == enable) - { - reg &= ~(0x1 << (rule_id & 0x1F)); - sw_rule->src_flt_dis = 1; - } - else - { - return SW_BAD_PARAM; - } - - HSL_REG_ENTRY_SET(rv, dev_id, ACL_FWD_SRC_FILTER_CTL0, regIdx, - (a_uint8_t *) (®), sizeof (a_uint32_t)); - - return rv; -} - -static sw_error_t -_isisc_acl_rule_src_filter_sts_get(a_uint32_t dev_id, - a_uint32_t rule_id, a_bool_t* enable) -{ - sw_error_t rv; - a_uint32_t reg = 0, regIdx; - isisc_acl_rule_t *sw_rule; - - HSL_DEV_ID_CHECK(dev_id); - - sw_rule = &sw_rule_ent[dev_id][rule_id]; - if (!(ENT_USED & sw_rule->status)) - { - return SW_NOT_FOUND; - } - - regIdx = rule_id >> 5; - - HSL_REG_ENTRY_GET(rv, dev_id, ACL_FWD_SRC_FILTER_CTL0, regIdx, - (a_uint8_t *) (®), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - - if (reg & (0x1 << (rule_id & 0x1F))) - { - *enable = A_TRUE; - } - else - { - *enable = A_FALSE; - } - - return rv; -} - - -HSL_LOCAL sw_error_t -isisc_acl_list_dump(a_uint32_t dev_id) -{ - _isisc_acl_list_dump(dev_id); - return SW_OK; -} - -HSL_LOCAL sw_error_t -isisc_acl_rule_dump(a_uint32_t dev_id) -{ - a_uint32_t flt_idx, i; - sw_error_t rv; - hw_filter_t filter; - - aos_printk("\nisisc_acl_rule_dump:\n"); - - for (flt_idx = 0; flt_idx < ISISC_MAX_FILTER; flt_idx++) - { - aos_mem_zero(&filter, sizeof (hw_filter_t)); - - rv = _isisc_filter_up_to_sw(dev_id, &filter, flt_idx); - if (SW_OK != rv) - { - continue; - } - - aos_printk("\n%d filter dump:", flt_idx); - - aos_printk("\nhardware content:"); - aos_printk("\nact:"); - for (i = 0; i < (sizeof (filter.act) / sizeof (a_uint32_t)); i++) - { - aos_printk("%08x ", filter.act[i]); - } - - aos_printk("\nvlu:"); - for (i = 0; i < (sizeof (filter.vlu) / sizeof (a_uint32_t)); i++) - { - aos_printk("%08x ", filter.vlu[i]); - } - - aos_printk("\nmsk:"); - for (i = 0; i < (sizeof (filter.msk) / sizeof (a_uint32_t)); i++) - { - aos_printk("%08x ", filter.msk[i]); - } - - aos_printk("\nsoftware content:"); - aos_printk("\nact:"); - for (i = 0; i < (sizeof (filter.act) / sizeof (a_uint32_t)); i++) - { - aos_printk("%08x ", sw_rule_ent[dev_id][flt_idx].filter.act[i]); - } - - aos_printk("\nvlu:"); - for (i = 0; i < (sizeof (filter.vlu) / sizeof (a_uint32_t)); i++) - { - aos_printk("%08x ", sw_rule_ent[dev_id][flt_idx].filter.vlu[i]); - } - - aos_printk("\nmsk:"); - for (i = 0; i < (sizeof (filter.msk) / sizeof (a_uint32_t)); i++) - { - aos_printk("%08x ", sw_rule_ent[dev_id][flt_idx].filter.msk[i]); - } - - aos_printk("\nctl:status[%02d] list_id[%02d] rule_id[%02d] src_flt_dis[%02d]", - sw_rule_ent[dev_id][flt_idx].status, - sw_rule_ent[dev_id][flt_idx].list_id, - sw_rule_ent[dev_id][flt_idx].rule_id, - sw_rule_ent[dev_id][flt_idx].src_flt_dis); - - aos_printk("\n\n"); - } - - return SW_OK; -} - -sw_error_t -isisc_acl_reset(a_uint32_t dev_id) -{ - HSL_DEV_ID_CHECK(dev_id); - - aos_mem_zero(sw_list_ent[dev_id], - ISISC_MAX_FILTER * sizeof (isisc_acl_list_t)); - - aos_mem_zero(sw_rule_ent[dev_id], - ISISC_MAX_FILTER * sizeof (isisc_acl_rule_t)); - - return SW_OK; -} - -/** - * @brief Creat an acl list - * @details Comments: - * If the value of list_pri is more small then the priority is more high, - * that means the list could be first matched. - * @param[in] dev_id device id - * @param[in] list_id acl list id - * @param[in] list_pri acl list priority - * @return SW_OK or error code - */ -sw_error_t -isisc_acl_list_creat(a_uint32_t dev_id, a_uint32_t list_id, a_uint32_t list_pri) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _isisc_acl_list_creat(dev_id, list_id, list_pri); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Destroy an acl list - * @param[in] dev_id device id - * @param[in] list_id acl list id - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -isisc_acl_list_destroy(a_uint32_t dev_id, a_uint32_t list_id) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _isisc_acl_list_destroy(dev_id, list_id); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Add one rule or more rules to an existing acl list - * @param[in] dev_id device id - * @param[in] list_id acl list id - * @param[in] rule_id first rule id of this adding operation in list - * @param[in] rule_nr rule number of this adding operation - * @param[in] rule rules content of this adding operation - * @return SW_OK or error code - */ -sw_error_t -isisc_acl_rule_add(a_uint32_t dev_id, a_uint32_t list_id, - a_uint32_t rule_id, a_uint32_t rule_nr, fal_acl_rule_t * rule) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _isisc_acl_rule_add(dev_id, list_id, rule_id, rule_nr, rule); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Delete one rule or more rules from an existing acl list - * @param[in] dev_id device id - * @param[in] list_id acl list id - * @param[in] rule_id first rule id of this deleteing operation in list - * @param[in] rule_nr rule number of this deleteing operation - * @return SW_OK or error code - */ -sw_error_t -isisc_acl_rule_delete(a_uint32_t dev_id, a_uint32_t list_id, - a_uint32_t rule_id, a_uint32_t rule_nr) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _isisc_acl_rule_delete(dev_id, list_id, rule_id, rule_nr); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Query one particular rule in a particular acl list - * @param[in] dev_id device id - * @param[in] list_id acl list id - * @param[in] rule_id first rule id of this deleteing operation in list - * @param[out] rule rule content of this operation - * @return SW_OK or error code - */ -sw_error_t -isisc_acl_rule_query(a_uint32_t dev_id, a_uint32_t list_id, - a_uint32_t rule_id, fal_acl_rule_t * rule) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _isisc_acl_rule_query(dev_id, list_id, rule_id, rule); - HSL_API_UNLOCK; - return rv; -} - -a_uint32_t -isisc_acl_rule_get_offset(a_uint32_t dev_id, a_uint32_t list_id, a_uint32_t rule_id) -{ - a_uint32_t i, pos=0; - isisc_acl_rule_t *sw_rule; - - for (i = 0; i < ISISC_MAX_FILTER; i++) - { - sw_rule = &(sw_rule_ent[0][i]); - - if ((ENT_USED & sw_rule->status) - && (list_id == sw_rule->list_id) && (sw_rule->rule_id == rule_id) - && (!(ENT_DEACTIVE & sw_rule->status))) - { - pos = i; - break; - - } - } - - return pos; -} - - -sw_error_t -isisc_acl_rule_sync_multi_portmap(a_uint32_t dev_id, a_uint32_t pos, a_uint32_t *act) -{ - - HSL_DEV_ID_CHECK(dev_id); - - if (ISISC_MAX_LIST_ID < pos) - { - return SW_NOT_SUPPORTED; - } - - sw_rule_ent[dev_id][pos].filter.act[1] = act[1]; - sw_rule_ent[dev_id][pos].filter.act[2] = act[2]; - - sw_rule_tmp[dev_id][pos].filter.act[1] = act[1]; - sw_rule_tmp[dev_id][pos].filter.act[2] = act[2]; - - hw_rule_tmp[dev_id][pos].filter.act[1] = act[1]; - hw_rule_tmp[dev_id][pos].filter.act[2] = act[2]; - - - return SW_OK; -} - -/** - * @brief Bind an acl list to a particular object - * @details Comments: - * If obj_t equals FAL_ACL_BIND_PORT then obj_idx means port id - * @param[in] dev_id device id - * @param[in] list_id acl list id - * @param[in] direc direction of this binding operation - * @param[in] obj_t object type of this binding operation - * @param[in] obj_idx object index of this binding operation - * @return SW_OK or error code - */ -sw_error_t -isisc_acl_list_bind(a_uint32_t dev_id, a_uint32_t list_id, - fal_acl_direc_t direc, fal_acl_bind_obj_t obj_t, - a_uint32_t obj_idx) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _isisc_acl_list_bind(dev_id, list_id, direc, obj_t, obj_idx); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Unbind an acl list from a particular object - * @details Comments: - * If obj_t equals FAL_ACL_BIND_PORT then obj_idx means port id - * @param[in] dev_id device id - * @param[in] list_id acl list id - * @param[in] direc direction of this unbinding operation - * @param[in] obj_t object type of this unbinding operation - * @param[in] obj_idx object index of this unbinding operation - * @return SW_OK or error code - */ -sw_error_t -isisc_acl_list_unbind(a_uint32_t dev_id, a_uint32_t list_id, - fal_acl_direc_t direc, fal_acl_bind_obj_t obj_t, - a_uint32_t obj_idx) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _isisc_acl_list_unbind(dev_id, list_id, direc, obj_t, obj_idx); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Set working status of ACL engine on a particular device - * @param[in] dev_id device id - * @param[in] enable A_TRUE or A_FALSE - * @return SW_OK or error code - */ -sw_error_t -isisc_acl_status_set(a_uint32_t dev_id, a_bool_t enable) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _isisc_acl_status_set(dev_id, enable); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Get working status of ACL engine on a particular device - * @param[in] dev_id device id - * @param[out] enable A_TRUE or A_FALSE - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -isisc_acl_status_get(a_uint32_t dev_id, a_bool_t * enable) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _isisc_acl_status_get(dev_id, enable); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Set user define fields profile on a particular port - * @param[in] dev_id device id - * @param[in] port_id port id - * @param[in] udf_type udf type - * @param[in] offset udf offset - * @param[in] length udf length - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -isisc_acl_port_udf_profile_set(a_uint32_t dev_id, fal_port_t port_id, - fal_acl_udf_type_t udf_type, a_uint32_t offset, - a_uint32_t length) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _isisc_acl_port_udf_profile_set(dev_id, port_id, udf_type, offset, - length); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Get user define fields profile on a particular port - * @param[in] dev_id device id - * @param[in] port_id port id - * @param[in] udf_type udf type - * @param[out] offset udf offset - * @param[out] length udf length - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -isisc_acl_port_udf_profile_get(a_uint32_t dev_id, fal_port_t port_id, - fal_acl_udf_type_t udf_type, a_uint32_t * offset, - a_uint32_t * length) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _isisc_acl_port_udf_profile_get(dev_id, port_id, udf_type, offset, - length); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Active one or more rules in an existing acl list - * @param[in] dev_id device id - * @param[in] list_id acl list id - * @param[in] rule_id first rule id of this deactive operation in list - * @param[in] rule_nr rule number of this deactive operation - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -isisc_acl_rule_active(a_uint32_t dev_id, a_uint32_t list_id, - a_uint32_t rule_id, a_uint32_t rule_nr) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _isisc_acl_rule_active(dev_id, list_id, rule_id, rule_nr, A_TRUE); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Deactive one or more rules in an existing acl list - * @param[in] dev_id device id - * @param[in] list_id acl list id - * @param[in] rule_id first rule id of this deactive operation in list - * @param[in] rule_nr rule number of this deactive operation - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -isisc_acl_rule_deactive(a_uint32_t dev_id, a_uint32_t list_id, - a_uint32_t rule_id, a_uint32_t rule_nr) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _isisc_acl_rule_active(dev_id, list_id, rule_id, rule_nr, A_FALSE); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief enable acl forward source filter of one rule. - * @param[in] dev_id device id - * @param[in] rule_id first rule id of this deactive operation in list - * @param[in] enable A_TRUE or A_FALSE - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -isisc_acl_rule_src_filter_sts_set(a_uint32_t dev_id, - a_uint32_t rule_id, a_bool_t enable) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _isisc_acl_rule_src_filter_sts_set(dev_id, rule_id, enable); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief get the status of acl forward source filter of one rule. - * @param[in] dev_id device id - * @param[in] rule_id first rule id of this deactive operation in list - * @param[out] enable A_TRUE or A_FALSE - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -isisc_acl_rule_src_filter_sts_get(a_uint32_t dev_id, - a_uint32_t rule_id, a_bool_t* enable) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _isisc_acl_rule_src_filter_sts_get(dev_id, rule_id, enable); - HSL_API_UNLOCK; - return rv; -} - - - -sw_error_t -isisc_acl_init(a_uint32_t dev_id) -{ - HSL_DEV_ID_CHECK(dev_id); - - sw_list_ent[dev_id] = - (isisc_acl_list_t *) aos_mem_alloc(ISISC_MAX_FILTER * - sizeof (isisc_acl_list_t)); - if (NULL == sw_list_ent[dev_id]) - { - return SW_NO_RESOURCE; - } - aos_mem_zero(sw_list_ent[dev_id], - ISISC_MAX_FILTER * sizeof (isisc_acl_list_t)); - - sw_rule_ent[dev_id] = - (isisc_acl_rule_t *) aos_mem_alloc(ISISC_MAX_FILTER * - sizeof (isisc_acl_rule_t)); - if (NULL == sw_rule_ent[dev_id]) - { - return SW_NO_RESOURCE; - } - aos_mem_zero(sw_rule_ent[dev_id], - ISISC_MAX_FILTER * sizeof (isisc_acl_rule_t)); - - hw_rule_tmp[dev_id] = - (isisc_acl_rule_t *) aos_mem_alloc(ISISC_HW_RULE_TMP_CNT * - sizeof (isisc_acl_rule_t)); - if (NULL == hw_rule_tmp[dev_id]) - { - return SW_NO_RESOURCE; - } - - sw_rule_tmp[dev_id] = - (isisc_acl_rule_t *) aos_mem_alloc(ISISC_MAX_FILTER * - sizeof (isisc_acl_rule_t)); - if (NULL == sw_rule_tmp[dev_id]) - { - return SW_NO_RESOURCE; - } -#ifdef ISISC_SW_ENTRY - sw_filter_mem = aos_mem_alloc(ISISC_MAX_FILTER * sizeof (hw_filter_t)); - if (NULL == sw_filter_mem) - { - return SW_NO_RESOURCE; - } - aos_mem_zero(sw_filter_mem, ISISC_MAX_FILTER * sizeof (hw_filter_t)); -#endif - -#ifndef HSL_STANDALONG - { - hsl_api_t *p_api; - - SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id)); - - p_api->acl_list_creat = isisc_acl_list_creat; - p_api->acl_list_destroy = isisc_acl_list_destroy; - p_api->acl_list_bind = isisc_acl_list_bind; - p_api->acl_list_unbind = isisc_acl_list_unbind; - p_api->acl_rule_add = isisc_acl_rule_add; - p_api->acl_rule_delete = isisc_acl_rule_delete; - p_api->acl_rule_query = isisc_acl_rule_query; - p_api->acl_status_set = isisc_acl_status_set; - p_api->acl_status_get = isisc_acl_status_get; - p_api->acl_list_dump = isisc_acl_list_dump; - p_api->acl_rule_dump = isisc_acl_rule_dump; - p_api->acl_port_udf_profile_set = isisc_acl_port_udf_profile_set; - p_api->acl_port_udf_profile_get = isisc_acl_port_udf_profile_get; - p_api->acl_rule_active = isisc_acl_rule_active; - p_api->acl_rule_deactive = isisc_acl_rule_deactive; - p_api->acl_rule_src_filter_sts_set = isisc_acl_rule_src_filter_sts_set; - p_api->acl_rule_src_filter_sts_get = isisc_acl_rule_src_filter_sts_get; - p_api->acl_rule_get_offset = isisc_acl_rule_get_offset; - p_api->acl_rule_sync_multi_portmap = isisc_acl_rule_sync_multi_portmap; - } -#endif - - return SW_OK; -} - -sw_error_t -isisc_acl_cleanup(a_uint32_t dev_id) -{ - HSL_DEV_ID_CHECK(dev_id); - - if (NULL != sw_list_ent[dev_id]) - { - aos_mem_free(sw_list_ent[dev_id]); - } - - if (NULL != sw_rule_ent[dev_id]) - { - aos_mem_free(sw_rule_ent[dev_id]); - } - - if (NULL != hw_rule_tmp[dev_id]) - { - aos_mem_free(hw_rule_tmp[dev_id]); - } - - if (NULL != sw_rule_tmp[dev_id]) - { - aos_mem_free(sw_rule_tmp[dev_id]); - } -#ifdef DESS_SW_ENTRY - if (NULL != sw_filter_mem) - { - aos_mem_free(sw_filter_mem); - } -#endif - - return SW_OK; -} - -/** - * @} - */ - diff --git a/feeds/ipq807x/qca-ssdk/src/src/hsl/isisc/isisc_acl_parse.c b/feeds/ipq807x/qca-ssdk/src/src/hsl/isisc/isisc_acl_parse.c deleted file mode 100755 index 9fb7b5ecc..000000000 --- a/feeds/ipq807x/qca-ssdk/src/src/hsl/isisc/isisc_acl_parse.c +++ /dev/null @@ -1,2452 +0,0 @@ -/* - * Copyright (c) 2012, The Linux Foundation. All rights reserved. - * Permission to use, copy, modify, and/or distribute this software for - * any purpose with or without fee is hereby granted, provided that the - * above copyright notice and this permission notice appear in all copies. - * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES - * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR - * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES - * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN - * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT - * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. - */ - - - -#include "sw.h" -#include "hsl.h" -#include "hsl_dev.h" -#include "hsl_acl.h" -#include "isisc_acl.h" -#include "isisc_reg.h" -#include "isisc_acl_prv.h" - -#define DAH 0x1 -#define SAH 0x2 -#define TAG 0x4 -#define STAG 0x8 -#define CTAG 0x10 - -typedef sw_error_t(*parse_func_t) (fal_acl_rule_t * sw, - hw_filter_t * hw_filter_snap, - a_bool_t * b_care); - -static a_bool_t -_isisc_acl_zero_addr(const fal_mac_addr_t addr) -{ - a_uint32_t i; - - for (i = 0; i < 6; i++) - { - if (addr.uc[i]) - { - return A_FALSE; - } - } - return A_TRUE; -} - -static a_bool_t -_isisc_acl_field_care(fal_acl_field_op_t op, a_uint32_t val, a_uint32_t mask, - a_uint32_t chkvlu) -{ - if (FAL_ACL_FIELD_MASK == op) - { - if (0 == mask) - return A_FALSE; - } - else if (FAL_ACL_FIELD_RANGE == op) - { - if ((0 == val) && (chkvlu == mask)) - return A_FALSE; - } - else if (FAL_ACL_FIELD_LE == op) - { - if (chkvlu == val) - return A_FALSE; - } - else if (FAL_ACL_FIELD_GE == op) - { - if (0 == val) - return A_FALSE; - } - else if (FAL_ACL_FIELD_NE == op) - { - return A_TRUE; - } - - return A_TRUE; -} - -static sw_error_t -_isisc_acl_rule_bmac_parse(fal_acl_rule_t * sw, - hw_filter_t * hw, a_bool_t * b_care) -{ - a_uint32_t i; - - *b_care = A_FALSE; - aos_mem_zero(&(hw->vlu[0]), sizeof (hw->vlu)); - aos_mem_zero(&(hw->msk[0]), sizeof (hw->msk)); - - FIELD_SET_MASK(MAC_RUL_M4, RULE_TYP, ISISC_MAC_FILTER); - - if (FAL_FIELD_FLG_TST(sw->field_flg, FAL_ACL_FIELD_MAC_DA)) - { - if (A_TRUE != _isisc_acl_zero_addr(sw->dest_mac_mask)) - { - *b_care = A_TRUE; - } - - for (i = 0; i < 6; i++) - { - sw->dest_mac_val.uc[i] &= sw->dest_mac_mask.uc[i]; - } - - FIELD_SET(MAC_RUL_V0, DAV_BYTE2, sw->dest_mac_val.uc[2]); - FIELD_SET(MAC_RUL_V0, DAV_BYTE3, sw->dest_mac_val.uc[3]); - FIELD_SET(MAC_RUL_V0, DAV_BYTE4, sw->dest_mac_val.uc[4]); - FIELD_SET(MAC_RUL_V0, DAV_BYTE5, sw->dest_mac_val.uc[5]); - FIELD_SET(MAC_RUL_V1, DAV_BYTE0, sw->dest_mac_val.uc[0]); - FIELD_SET(MAC_RUL_V1, DAV_BYTE1, sw->dest_mac_val.uc[1]); - - FIELD_SET_MASK(MAC_RUL_M0, DAM_BYTE2, sw->dest_mac_mask.uc[2]); - FIELD_SET_MASK(MAC_RUL_M0, DAM_BYTE3, sw->dest_mac_mask.uc[3]); - FIELD_SET_MASK(MAC_RUL_M0, DAM_BYTE4, sw->dest_mac_mask.uc[4]); - FIELD_SET_MASK(MAC_RUL_M0, DAM_BYTE5, sw->dest_mac_mask.uc[5]); - FIELD_SET_MASK(MAC_RUL_M1, DAM_BYTE0, sw->dest_mac_mask.uc[0]); - FIELD_SET_MASK(MAC_RUL_M1, DAM_BYTE1, sw->dest_mac_mask.uc[1]); - } - - if (FAL_FIELD_FLG_TST(sw->field_flg, FAL_ACL_FIELD_MAC_SA)) - { - if (A_TRUE != _isisc_acl_zero_addr(sw->src_mac_mask)) - { - *b_care = A_TRUE; - } - - for (i = 0; i < 6; i++) - { - sw->src_mac_val.uc[i] &= sw->src_mac_mask.uc[i]; - } - - FIELD_SET(MAC_RUL_V1, SAV_BYTE4, sw->src_mac_val.uc[4]); - FIELD_SET(MAC_RUL_V1, SAV_BYTE5, sw->src_mac_val.uc[5]); - FIELD_SET(MAC_RUL_V2, SAV_BYTE0, sw->src_mac_val.uc[0]); - FIELD_SET(MAC_RUL_V2, SAV_BYTE1, sw->src_mac_val.uc[1]); - FIELD_SET(MAC_RUL_V2, SAV_BYTE2, sw->src_mac_val.uc[2]); - FIELD_SET(MAC_RUL_V2, SAV_BYTE3, sw->src_mac_val.uc[3]); - - FIELD_SET_MASK(MAC_RUL_M1, SAM_BYTE4, sw->src_mac_mask.uc[4]); - FIELD_SET_MASK(MAC_RUL_M1, SAM_BYTE5, sw->src_mac_mask.uc[5]); - FIELD_SET_MASK(MAC_RUL_M2, SAM_BYTE0, sw->src_mac_mask.uc[0]); - FIELD_SET_MASK(MAC_RUL_M2, SAM_BYTE1, sw->src_mac_mask.uc[1]); - FIELD_SET_MASK(MAC_RUL_M2, SAM_BYTE2, sw->src_mac_mask.uc[2]); - FIELD_SET_MASK(MAC_RUL_M2, SAM_BYTE3, sw->src_mac_mask.uc[3]); - } - - if (FAL_FIELD_FLG_TST(sw->field_flg, FAL_ACL_FIELD_MAC_ETHTYPE)) - { - if (0x0 != sw->ethtype_mask) - { - *b_care = A_TRUE; - } - - sw->ethtype_val &= sw->ethtype_mask; - FIELD_SET(MAC_RUL_V3, ETHTYPV, sw->ethtype_val); - FIELD_SET_MASK(MAC_RUL_M3, ETHTYPM, sw->ethtype_mask); - } - - if (FAL_FIELD_FLG_TST(sw->field_flg, FAL_ACL_FIELD_MAC_TAGGED)) - { - if (0x0 != sw->tagged_mask) - { - *b_care = A_TRUE; - } - - sw->tagged_val &= sw->tagged_mask; - FIELD_SET_MASK(MAC_RUL_M4, TAGGEDV, sw->tagged_val); - FIELD_SET_MASK(MAC_RUL_M4, TAGGEDM, sw->tagged_mask); - } - - if (FAL_FIELD_FLG_TST(sw->field_flg, FAL_ACL_FIELD_MAC_UP)) - { - if (0x0 != sw->up_mask) - { - *b_care = A_TRUE; - } - - sw->up_val &= sw->up_mask; - FIELD_SET(MAC_RUL_V3, VLANPRIV, sw->up_val); - FIELD_SET_MASK(MAC_RUL_M3, VLANPRIM, sw->up_mask); - } - - FIELD_SET_MASK(MAC_RUL_M4, VIDMSK, 1); - if (FAL_FIELD_FLG_TST(sw->field_flg, FAL_ACL_FIELD_MAC_VID)) - { - if ((FAL_ACL_FIELD_MASK != sw->vid_op) - && (FAL_ACL_FIELD_RANGE != sw->vid_op) - && (FAL_ACL_FIELD_LE != sw->vid_op) - && (FAL_ACL_FIELD_GE != sw->vid_op)) - { - return SW_NOT_SUPPORTED; - } - - if (A_TRUE == - _isisc_acl_field_care(sw->vid_op, sw->vid_val, sw->vid_mask, - 0xfff)) - { - *b_care = A_TRUE; - } - - FIELD_SET_MASK(MAC_RUL_M4, VIDMSK, 0); - if (FAL_ACL_FIELD_MASK == sw->vid_op) - { - sw->vid_val &= sw->vid_mask; - FIELD_SET(MAC_RUL_V3, VLANIDV, sw->vid_val); - FIELD_SET_MASK(MAC_RUL_M3, VLANIDM, sw->vid_mask); - FIELD_SET_MASK(MAC_RUL_M4, VIDMSK, 1); - } - else if (FAL_ACL_FIELD_RANGE == sw->vid_op) - { - FIELD_SET(MAC_RUL_V3, VLANIDV, sw->vid_val); - FIELD_SET_MASK(MAC_RUL_M3, VLANIDM, sw->vid_mask); - } - else if (FAL_ACL_FIELD_LE == sw->vid_op) - { - FIELD_SET(MAC_RUL_V3, VLANIDV, 0); - FIELD_SET_MASK(MAC_RUL_M3, VLANIDM, sw->vid_val); - } - else - { - FIELD_SET(MAC_RUL_V3, VLANIDV, sw->vid_val); - FIELD_SET_MASK(MAC_RUL_M3, VLANIDM, 0xfff); - } - } - - if (FAL_FIELD_FLG_TST(sw->field_flg, FAL_ACL_FIELD_MAC_CFI)) - { - if (0x0 != sw->cfi_mask) - { - *b_care = A_TRUE; - } - - sw->cfi_val &= sw->cfi_mask; - FIELD_SET(MAC_RUL_V3, VLANCFIV, sw->cfi_val); - FIELD_SET_MASK(MAC_RUL_M3, VLANCFIM, sw->cfi_mask); - } - - if (FAL_FIELD_FLG_TST(sw->field_flg, FAL_ACL_FIELD_INVERSE_ALL)) - { - FIELD_SET(MAC_RUL_V4, RULE_INV, 1); - } - - return SW_OK; -} - -static sw_error_t -_isisc_acl_rule_ehmac_parse(fal_acl_rule_t * sw, - hw_filter_t * hw, a_bool_t * b_care) -{ - a_uint32_t i; - a_bool_t da_h = A_FALSE, sa_h = A_FALSE; - - *b_care = A_FALSE; - aos_mem_zero(&(hw->vlu[0]), sizeof (hw->vlu)); - aos_mem_zero(&(hw->msk[0]), sizeof (hw->msk)); - - FIELD_SET_MASK(MAC_RUL_M4, RULE_TYP, ISISC_EHMAC_FILTER); - - if (FAL_FIELD_FLG_TST(sw->field_flg, FAL_ACL_FIELD_MAC_DA)) - { - for (i = 0; i < 3; i++) - { - if (sw->dest_mac_mask.uc[i]) - { - da_h = A_TRUE; - break; - } - } - } - - if (FAL_FIELD_FLG_TST(sw->field_flg, FAL_ACL_FIELD_MAC_SA)) - { - for (i = 0; i < 3; i++) - { - if (sw->src_mac_mask.uc[i]) - { - sa_h = A_TRUE; - break; - } - } - } - - /* if sa_h and da_h both are true need't process mac address fileds */ - if ((A_TRUE == da_h) && ((A_TRUE == sa_h))) - { - da_h = A_FALSE; - sa_h = A_FALSE; - } - - if (A_TRUE == da_h) - { - FIELD_SET(EHMAC_RUL_V3, DA_EN, 1); - - if (A_TRUE != _isisc_acl_zero_addr(sw->dest_mac_mask)) - { - *b_care = A_TRUE; - } - - for (i = 0; i < 6; i++) - { - sw->dest_mac_val.uc[i] &= sw->dest_mac_mask.uc[i]; - } - - FIELD_SET(EHMAC_RUL_V0, DAV_BYTE2, sw->dest_mac_val.uc[2]); - FIELD_SET(EHMAC_RUL_V0, DAV_BYTE3, sw->dest_mac_val.uc[3]); - FIELD_SET(EHMAC_RUL_V0, DAV_BYTE4, sw->dest_mac_val.uc[4]); - FIELD_SET(EHMAC_RUL_V0, DAV_BYTE5, sw->dest_mac_val.uc[5]); - FIELD_SET(EHMAC_RUL_V1, DAV_BYTE0, sw->dest_mac_val.uc[0]); - FIELD_SET(EHMAC_RUL_V1, DAV_BYTE1, sw->dest_mac_val.uc[1]); - - FIELD_SET_MASK(EHMAC_RUL_M0, DAM_BYTE2, sw->dest_mac_mask.uc[2]); - FIELD_SET_MASK(EHMAC_RUL_M0, DAM_BYTE3, sw->dest_mac_mask.uc[3]); - FIELD_SET_MASK(EHMAC_RUL_M0, DAM_BYTE4, sw->dest_mac_mask.uc[4]); - FIELD_SET_MASK(EHMAC_RUL_M0, DAM_BYTE5, sw->dest_mac_mask.uc[5]); - FIELD_SET_MASK(EHMAC_RUL_M1, DAM_BYTE0, sw->dest_mac_mask.uc[0]); - FIELD_SET_MASK(EHMAC_RUL_M1, DAM_BYTE1, sw->dest_mac_mask.uc[1]); - - if (FAL_FIELD_FLG_TST(sw->field_flg, FAL_ACL_FIELD_MAC_SA)) - { - if (A_TRUE != _isisc_acl_zero_addr(sw->src_mac_mask)) - { - *b_care = A_TRUE; - } - - for (i = 0; i < 6; i++) - { - sw->src_mac_val.uc[i] &= sw->src_mac_mask.uc[i]; - } - - FIELD_SET(EHMAC_RUL_V2, SAV_BYTE3, sw->src_mac_val.uc[3]); - FIELD_SET(EHMAC_RUL_V1, SAV_BYTE4, sw->src_mac_val.uc[4]); - FIELD_SET(EHMAC_RUL_V1, SAV_BYTE5, sw->src_mac_val.uc[5]); - - FIELD_SET_MASK(EHMAC_RUL_M2, SAM_BYTE3, sw->src_mac_mask.uc[3]); - FIELD_SET_MASK(EHMAC_RUL_M1, SAM_BYTE4, sw->src_mac_mask.uc[4]); - FIELD_SET_MASK(EHMAC_RUL_M1, SAM_BYTE5, sw->src_mac_mask.uc[5]); - } - } - - if (A_TRUE == sa_h) - { - if (A_TRUE != _isisc_acl_zero_addr(sw->src_mac_mask)) - { - *b_care = A_TRUE; - } - - for (i = 0; i < 6; i++) - { - sw->src_mac_val.uc[i] &= sw->src_mac_mask.uc[i]; - } - - FIELD_SET(EHMAC_RUL_V0, DAV_BYTE2, sw->src_mac_val.uc[2]); - FIELD_SET(EHMAC_RUL_V0, DAV_BYTE3, sw->src_mac_val.uc[3]); - FIELD_SET(EHMAC_RUL_V0, DAV_BYTE4, sw->src_mac_val.uc[4]); - FIELD_SET(EHMAC_RUL_V0, DAV_BYTE5, sw->src_mac_val.uc[5]); - FIELD_SET(EHMAC_RUL_V1, DAV_BYTE0, sw->src_mac_val.uc[0]); - FIELD_SET(EHMAC_RUL_V1, DAV_BYTE1, sw->src_mac_val.uc[1]); - - FIELD_SET_MASK(EHMAC_RUL_M0, DAM_BYTE2, sw->src_mac_mask.uc[2]); - FIELD_SET_MASK(EHMAC_RUL_M0, DAM_BYTE3, sw->src_mac_mask.uc[3]); - FIELD_SET_MASK(EHMAC_RUL_M0, DAM_BYTE4, sw->src_mac_mask.uc[4]); - FIELD_SET_MASK(EHMAC_RUL_M0, DAM_BYTE5, sw->src_mac_mask.uc[5]); - FIELD_SET_MASK(EHMAC_RUL_M1, DAM_BYTE0, sw->src_mac_mask.uc[0]); - FIELD_SET_MASK(EHMAC_RUL_M1, DAM_BYTE1, sw->src_mac_mask.uc[1]); - - if (FAL_FIELD_FLG_TST(sw->field_flg, FAL_ACL_FIELD_MAC_DA)) - { - if (A_TRUE != _isisc_acl_zero_addr(sw->dest_mac_mask)) - { - *b_care = A_TRUE; - } - - for (i = 0; i < 6; i++) - { - sw->dest_mac_val.uc[i] &= sw->dest_mac_mask.uc[i]; - } - - FIELD_SET(EHMAC_RUL_V2, SAV_BYTE3, sw->dest_mac_val.uc[3]); - FIELD_SET(EHMAC_RUL_V1, SAV_BYTE4, sw->dest_mac_val.uc[4]); - FIELD_SET(EHMAC_RUL_V1, SAV_BYTE5, sw->dest_mac_val.uc[5]); - - FIELD_SET_MASK(EHMAC_RUL_M2, SAM_BYTE3, sw->dest_mac_mask.uc[3]); - FIELD_SET_MASK(EHMAC_RUL_M1, SAM_BYTE4, sw->dest_mac_mask.uc[4]); - FIELD_SET_MASK(EHMAC_RUL_M1, SAM_BYTE5, sw->dest_mac_mask.uc[5]); - } - } - - if (FAL_FIELD_FLG_TST(sw->field_flg, FAL_ACL_FIELD_MAC_ETHTYPE)) - { - if (0x0 != sw->ethtype_mask) - { - *b_care = A_TRUE; - } - - sw->ethtype_val &= sw->ethtype_mask; - FIELD_SET(EHMAC_RUL_V3, ETHTYPV, sw->ethtype_val); - FIELD_SET_MASK(EHMAC_RUL_M3, ETHTYPM, sw->ethtype_mask); - } - - /* Process Stag Fields */ - if (FAL_FIELD_FLG_TST(sw->field_flg, FAL_ACL_FIELD_MAC_STAGGED)) - { - if (0x0 != sw->stagged_mask) - { - *b_care = A_TRUE; - } - - sw->stagged_val &= sw->stagged_mask; - FIELD_SET(EHMAC_RUL_V3, STAGGEDV, sw->stagged_val); - FIELD_SET(EHMAC_RUL_V3, STAGGEDM, sw->stagged_mask); - } - - FIELD_SET(EHMAC_RUL_V3, SVIDMSK, 1); - if (FAL_FIELD_FLG_TST(sw->field_flg, FAL_ACL_FIELD_MAC_STAG_VID)) - { - if ((FAL_ACL_FIELD_MASK != sw->stag_vid_op) - && (FAL_ACL_FIELD_RANGE != sw->stag_vid_op) - && (FAL_ACL_FIELD_LE != sw->stag_vid_op) - && (FAL_ACL_FIELD_GE != sw->stag_vid_op)) - { - return SW_NOT_SUPPORTED; - } - - if (A_TRUE == - _isisc_acl_field_care(sw->stag_vid_op, sw->stag_vid_val, - sw->stag_vid_mask, 0xfff)) - { - *b_care = A_TRUE; - } - - FIELD_SET(EHMAC_RUL_V3, SVIDMSK, 0); - if (FAL_ACL_FIELD_MASK == sw->stag_vid_op) - { - sw->stag_vid_val &= sw->stag_vid_mask; - FIELD_SET(EHMAC_RUL_V2, STAG_VIDV, sw->stag_vid_val); - FIELD_SET_MASK(EHMAC_RUL_M2, STAG_VIDM, sw->stag_vid_mask); - FIELD_SET(EHMAC_RUL_V3, SVIDMSK, 1); - - } - else if (FAL_ACL_FIELD_RANGE == sw->stag_vid_op) - { - FIELD_SET(EHMAC_RUL_V2, STAG_VIDV, sw->stag_vid_val); - FIELD_SET_MASK(EHMAC_RUL_M2, STAG_VIDM, sw->stag_vid_mask); - - } - else if (FAL_ACL_FIELD_LE == sw->stag_vid_op) - { - FIELD_SET(EHMAC_RUL_V2, STAG_VIDV, 0); - FIELD_SET_MASK(EHMAC_RUL_M2, STAG_VIDM, sw->stag_vid_val); - - } - else - { - FIELD_SET(EHMAC_RUL_V2, STAG_VIDV, sw->stag_vid_val); - FIELD_SET_MASK(EHMAC_RUL_M2, STAG_VIDM, 0xfff); - } - } - - if (FAL_FIELD_FLG_TST(sw->field_flg, FAL_ACL_FIELD_MAC_STAG_PRI)) - { - if (0x0 != sw->stag_pri_mask) - { - *b_care = A_TRUE; - } - - sw->stag_pri_val &= sw->stag_pri_mask; - FIELD_SET(EHMAC_RUL_V2, STAG_PRIV, sw->stag_pri_val); - FIELD_SET_MASK(EHMAC_RUL_M2, STAG_PRIM, sw->stag_pri_mask); - } - - if (FAL_FIELD_FLG_TST(sw->field_flg, FAL_ACL_FIELD_MAC_STAG_DEI)) - { - if (0x0 != sw->stag_dei_mask) - { - *b_care = A_TRUE; - } - - sw->stag_dei_val &= sw->stag_dei_mask; - FIELD_SET(EHMAC_RUL_V2, STAG_DEIV, sw->stag_dei_val); - FIELD_SET_MASK(EHMAC_RUL_M2, STAG_DEIM, sw->stag_dei_mask); - } - - /* Process Ctag Fields */ - if (FAL_FIELD_FLG_TST(sw->field_flg, FAL_ACL_FIELD_MAC_CTAGGED)) - { - if (0x0 != sw->ctagged_mask) - { - *b_care = A_TRUE; - } - - sw->ctagged_val &= sw->ctagged_mask; - FIELD_SET_MASK(EHMAC_RUL_M4, CTAGGEDV, sw->ctagged_val); - FIELD_SET_MASK(EHMAC_RUL_M4, CTAGGEDM, sw->ctagged_mask); - } - - FIELD_SET_MASK(EHMAC_RUL_M4, CVIDMSK, 1); - if (FAL_FIELD_FLG_TST(sw->field_flg, FAL_ACL_FIELD_MAC_CTAG_VID)) - { - if ((FAL_ACL_FIELD_MASK != sw->ctag_vid_op) - && (FAL_ACL_FIELD_RANGE != sw->ctag_vid_op) - && (FAL_ACL_FIELD_LE != sw->ctag_vid_op) - && (FAL_ACL_FIELD_GE != sw->ctag_vid_op)) - { - return SW_NOT_SUPPORTED; - } - - if (A_TRUE == - _isisc_acl_field_care(sw->ctag_vid_op, sw->ctag_vid_val, - sw->ctag_vid_mask, 0xfff)) - { - *b_care = A_TRUE; - } - - FIELD_SET_MASK(EHMAC_RUL_M4, CVIDMSK, 0); - if (FAL_ACL_FIELD_MASK == sw->ctag_vid_op) - { - sw->ctag_vid_val &= sw->ctag_vid_mask; - FIELD_SET(EHMAC_RUL_V2, CTAG_VIDLV, sw->ctag_vid_val); - FIELD_SET(EHMAC_RUL_V3, CTAG_VIDHV, (sw->ctag_vid_val >> 8)); - FIELD_SET_MASK(EHMAC_RUL_M2, CTAG_VIDLM, sw->ctag_vid_mask); - FIELD_SET_MASK(EHMAC_RUL_M3, CTAG_VIDHM, (sw->ctag_vid_mask >> 8)); - FIELD_SET_MASK(EHMAC_RUL_M4, CVIDMSK, 1); - - } - else if (FAL_ACL_FIELD_RANGE == sw->ctag_vid_op) - { - FIELD_SET(EHMAC_RUL_V2, CTAG_VIDLV, sw->ctag_vid_val); - FIELD_SET(EHMAC_RUL_V3, CTAG_VIDHV, (sw->ctag_vid_val >> 8)); - FIELD_SET_MASK(EHMAC_RUL_M2, CTAG_VIDLM, sw->ctag_vid_mask); - FIELD_SET_MASK(EHMAC_RUL_M3, CTAG_VIDHM, (sw->ctag_vid_mask >> 8)); - - } - else if (FAL_ACL_FIELD_LE == sw->ctag_vid_op) - { - FIELD_SET(EHMAC_RUL_V2, CTAG_VIDLV, 0); - FIELD_SET(EHMAC_RUL_V3, CTAG_VIDHV, 0); - FIELD_SET_MASK(EHMAC_RUL_M2, CTAG_VIDLM, sw->ctag_vid_val); - FIELD_SET_MASK(EHMAC_RUL_M3, CTAG_VIDHM, (sw->ctag_vid_val >> 8)); - - } - else - { - FIELD_SET(EHMAC_RUL_V2, CTAG_VIDLV, sw->ctag_vid_val); - FIELD_SET(EHMAC_RUL_V3, CTAG_VIDHV, (sw->ctag_vid_val >> 8)); - FIELD_SET_MASK(EHMAC_RUL_M2, CTAG_VIDLM, 0xff); - FIELD_SET_MASK(EHMAC_RUL_M3, CTAG_VIDHM, 0xf); - } - } - - if (FAL_FIELD_FLG_TST(sw->field_flg, FAL_ACL_FIELD_MAC_CTAG_PRI)) - { - if (0x0 != sw->ctag_pri_mask) - { - *b_care = A_TRUE; - } - - sw->ctag_pri_val &= sw->ctag_pri_mask; - FIELD_SET(EHMAC_RUL_V3, CTAG_PRIV, sw->ctag_pri_val); - FIELD_SET_MASK(EHMAC_RUL_M3, CTAG_PRIM, sw->ctag_pri_mask); - } - - if (FAL_FIELD_FLG_TST(sw->field_flg, FAL_ACL_FIELD_MAC_CTAG_CFI)) - { - if (0x0 != sw->ctag_cfi_mask) - { - *b_care = A_TRUE; - } - - sw->ctag_cfi_val &= sw->ctag_cfi_mask; - FIELD_SET(EHMAC_RUL_V3, CTAG_CFIV, sw->ctag_cfi_val); - FIELD_SET_MASK(EHMAC_RUL_M3, CTAG_CFIM, sw->ctag_cfi_mask); - } - - if (FAL_FIELD_FLG_TST(sw->field_flg, FAL_ACL_FIELD_INVERSE_ALL)) - { - FIELD_SET(MAC_RUL_V4, RULE_INV, 1); - } - - return SW_OK; -} - -static void -_isisc_acl_rule_mac_preparse(fal_acl_rule_t * sw, a_bool_t * b_mac, - a_bool_t * eh_mac) -{ - a_uint32_t bm = 0, i, tmp; - - *b_mac = A_FALSE; - *eh_mac = A_FALSE; - if (FAL_FIELD_FLG_TST(sw->field_flg, FAL_ACL_FIELD_MAC_DA)) - { - for (i = 0; i < 3; i++) - { - if (sw->dest_mac_mask.uc[i]) - { - bm |= DAH; - break; - } - } - } - - if (FAL_FIELD_FLG_TST(sw->field_flg, FAL_ACL_FIELD_MAC_SA)) - { - for (i = 0; i < 3; i++) - { - if (sw->src_mac_mask.uc[i]) - { - bm |= SAH; - break; - } - } - } - - tmp = 0; - if (FAL_FIELD_FLG_TST(sw->field_flg, FAL_ACL_FIELD_MAC_TAGGED)) - { - tmp |= ((sw->tagged_mask & 0x1) << 16); - } - if (FAL_FIELD_FLG_TST(sw->field_flg, FAL_ACL_FIELD_MAC_UP)) - { - tmp |= ((sw->up_mask & 0x7) << 13); - } - if (FAL_FIELD_FLG_TST(sw->field_flg, FAL_ACL_FIELD_MAC_CFI)) - { - tmp |= ((sw->cfi_mask & 0x1) << 12); - } - if (FAL_FIELD_FLG_TST(sw->field_flg, FAL_ACL_FIELD_MAC_VID)) - { - if (A_TRUE == - _isisc_acl_field_care(sw->vid_op, sw->vid_val, sw->vid_mask, - 0xfff)) - { - tmp |= 0xfff; - } - } - if (tmp) - { - bm |= TAG; - } - - tmp = 0; - if (FAL_FIELD_FLG_TST(sw->field_flg, FAL_ACL_FIELD_MAC_STAGGED)) - { - tmp |= ((sw->stagged_mask & 0x1) << 16); - } - if (FAL_FIELD_FLG_TST(sw->field_flg, FAL_ACL_FIELD_MAC_STAG_PRI)) - { - tmp |= ((sw->stag_pri_mask & 0x7) << 13); - } - if (FAL_FIELD_FLG_TST(sw->field_flg, FAL_ACL_FIELD_MAC_STAG_DEI)) - { - tmp |= ((sw->stag_dei_mask & 0x1) << 12); - } - if (FAL_FIELD_FLG_TST(sw->field_flg, FAL_ACL_FIELD_MAC_STAG_VID)) - { - if (A_TRUE == - _isisc_acl_field_care(sw->stag_vid_op, sw->stag_vid_val, - sw->stag_vid_mask, 0xfff)) - { - tmp |= 0xfff; - } - } - if (tmp) - { - bm |= STAG; - } - - tmp = 0; - if (FAL_FIELD_FLG_TST(sw->field_flg, FAL_ACL_FIELD_MAC_CTAGGED)) - { - tmp |= ((sw->ctagged_mask & 0x1) << 16); - } - if (FAL_FIELD_FLG_TST(sw->field_flg, FAL_ACL_FIELD_MAC_CTAG_PRI)) - { - tmp |= ((sw->ctag_pri_mask & 0x7) << 13); - } - if (FAL_FIELD_FLG_TST(sw->field_flg, FAL_ACL_FIELD_MAC_CTAG_CFI)) - { - tmp |= ((sw->ctag_cfi_mask & 0x1) << 12); - } - if (FAL_FIELD_FLG_TST(sw->field_flg, FAL_ACL_FIELD_MAC_CTAG_VID)) - { - if (A_TRUE == - _isisc_acl_field_care(sw->ctag_vid_op, sw->ctag_vid_val, - sw->ctag_vid_mask, 0xfff)) - { - tmp |= 0xfff; - } - } - if (tmp) - { - bm |= CTAG; - } - - if ((bm & CTAG) || (bm & STAG)) - { - *eh_mac = A_TRUE; - } - - if ((bm & TAG) || ((bm & DAH) && (bm & SAH))) - { - *b_mac = A_TRUE; - } -} - -static sw_error_t -_isisc_acl_rule_ip4_parse(fal_acl_rule_t * sw, - hw_filter_t * hw, a_bool_t * b_care) -{ - *b_care = A_FALSE; - aos_mem_zero(&(hw->vlu[0]), sizeof (hw->vlu)); - aos_mem_zero(&(hw->msk[0]), sizeof (hw->msk)); - - FIELD_SET_MASK(MAC_RUL_M4, RULE_TYP, ISISC_IP4_FILTER); - - if (FAL_FIELD_FLG_TST(sw->field_flg, FAL_ACL_FIELD_IP_DSCP)) - { - if (0x0 != sw->ip_dscp_mask) - { - *b_care = A_TRUE; - } - - sw->ip_dscp_val &= sw->ip_dscp_mask; - FIELD_SET(IP4_RUL_V2, IP4DSCPV, sw->ip_dscp_val); - FIELD_SET_MASK(IP4_RUL_M2, IP4DSCPM, sw->ip_dscp_mask); - } - - if (FAL_FIELD_FLG_TST(sw->field_flg, FAL_ACL_FIELD_IP_PROTO)) - { - if (0x0 != sw->ip_proto_mask) - { - *b_care = A_TRUE; - } - - sw->ip_proto_val &= sw->ip_proto_mask; - FIELD_SET(IP4_RUL_V2, IP4PROTV, sw->ip_proto_val); - FIELD_SET_MASK(IP4_RUL_M2, IP4PROTM, sw->ip_proto_mask); - } - - if (FAL_FIELD_FLG_TST(sw->field_flg, FAL_ACL_FIELD_IP4_SIP)) - { - if (0x0 != sw->src_ip4_mask) - { - *b_care = A_TRUE; - } - sw->src_ip4_val &= sw->src_ip4_mask; - hw->vlu[1] = sw->src_ip4_val; - hw->msk[1] = sw->src_ip4_mask; - } - - if (FAL_FIELD_FLG_TST(sw->field_flg, FAL_ACL_FIELD_IP4_DIP)) - { - if (0x0 != sw->dest_ip4_mask) - { - *b_care = A_TRUE; - } - sw->dest_ip4_val &= sw->dest_ip4_mask; - hw->vlu[0] = sw->dest_ip4_val; - hw->msk[0] = sw->dest_ip4_mask; - } - - if ((FAL_FIELD_FLG_TST(sw->field_flg, FAL_ACL_FIELD_L4_SPORT)) - && ((FAL_FIELD_FLG_TST(sw->field_flg, FAL_ACL_FIELD_ICMP_TYPE)) - || (FAL_FIELD_FLG_TST(sw->field_flg, FAL_ACL_FIELD_ICMP_CODE)))) - { - return SW_BAD_PARAM; - } - - FIELD_SET_MASK(IP4_RUL_M3, IP4SPORTM_EN, 1); - if (FAL_FIELD_FLG_TST(sw->field_flg, FAL_ACL_FIELD_L4_SPORT)) - { - if ((FAL_ACL_FIELD_MASK != sw->src_l4port_op) - && (FAL_ACL_FIELD_RANGE != sw->src_l4port_op) - && (FAL_ACL_FIELD_LE != sw->src_l4port_op) - && (FAL_ACL_FIELD_GE != sw->src_l4port_op)) - { - return SW_NOT_SUPPORTED; - } - - if (A_FALSE == - _isisc_acl_field_care(sw->src_l4port_op, sw->src_l4port_val, - sw->src_l4port_mask, 0xffff)) - { - if (FAL_ACL_FIELD_MASK == sw->src_l4port_op) - { - sw->src_l4port_op = FAL_ACL_FIELD_RANGE; - sw->src_l4port_val = 0; - sw->src_l4port_mask = 0xffff; - } - } - *b_care = A_TRUE; - - FIELD_SET_MASK(IP4_RUL_M3, IP4SPORTM_EN, 0); - if (FAL_ACL_FIELD_MASK == sw->src_l4port_op) - { - sw->src_l4port_val &= sw->src_l4port_mask; - FIELD_SET(IP4_RUL_V3, IP4SPORTV, sw->src_l4port_val); - FIELD_SET_MASK(IP4_RUL_M3, IP4SPORTM, sw->src_l4port_mask); - FIELD_SET_MASK(IP4_RUL_M3, IP4SPORTM_EN, 1); - } - else if (FAL_ACL_FIELD_RANGE == sw->src_l4port_op) - { - FIELD_SET(IP4_RUL_V3, IP4SPORTV, sw->src_l4port_val); - FIELD_SET_MASK(IP4_RUL_M3, IP4SPORTM, sw->src_l4port_mask); - } - else if (FAL_ACL_FIELD_LE == sw->src_l4port_op) - { - FIELD_SET(IP4_RUL_V3, IP4SPORTV, 0); - FIELD_SET_MASK(IP4_RUL_M3, IP4SPORTM, sw->src_l4port_val); - } - else - { - FIELD_SET(IP4_RUL_V3, IP4SPORTV, sw->src_l4port_val); - FIELD_SET_MASK(IP4_RUL_M3, IP4SPORTM, 0xffff); - } - } - - FIELD_SET_MASK(IP4_RUL_M3, IP4DPORTM_EN, 1); - if (FAL_FIELD_FLG_TST(sw->field_flg, FAL_ACL_FIELD_L4_DPORT)) - { - if ((FAL_ACL_FIELD_MASK != sw->dest_l4port_op) - && (FAL_ACL_FIELD_RANGE != sw->dest_l4port_op) - && (FAL_ACL_FIELD_LE != sw->dest_l4port_op) - && (FAL_ACL_FIELD_GE != sw->dest_l4port_op)) - { - return SW_NOT_SUPPORTED; - } - - if (A_FALSE == - _isisc_acl_field_care(sw->dest_l4port_op, sw->dest_l4port_val, - sw->dest_l4port_mask, 0xffff)) - { - if (FAL_ACL_FIELD_MASK == sw->dest_l4port_op) - { - sw->dest_l4port_op = FAL_ACL_FIELD_RANGE; - sw->dest_l4port_val = 0; - sw->dest_l4port_mask = 0xffff; - } - } - *b_care = A_TRUE; - - FIELD_SET_MASK(IP4_RUL_M3, IP4DPORTM_EN, 0); - if (FAL_ACL_FIELD_MASK == sw->dest_l4port_op) - { - sw->dest_l4port_val &= sw->dest_l4port_mask; - FIELD_SET(IP4_RUL_V2, IP4DPORTV, sw->dest_l4port_val); - FIELD_SET_MASK(IP4_RUL_M2, IP4DPORTM, sw->dest_l4port_mask); - FIELD_SET_MASK(IP4_RUL_M3, IP4DPORTM_EN, 1); - } - else if (FAL_ACL_FIELD_RANGE == sw->dest_l4port_op) - { - FIELD_SET(IP4_RUL_V2, IP4DPORTV, sw->dest_l4port_val); - FIELD_SET_MASK(IP4_RUL_M2, IP4DPORTM, sw->dest_l4port_mask); - } - else if (FAL_ACL_FIELD_LE == sw->dest_l4port_op) - { - FIELD_SET(IP4_RUL_V2, IP4DPORTV, 0); - FIELD_SET_MASK(IP4_RUL_M2, IP4DPORTM, sw->dest_l4port_val); - } - else - { - FIELD_SET(IP4_RUL_V2, IP4DPORTV, sw->dest_l4port_val); - FIELD_SET_MASK(IP4_RUL_M2, IP4DPORTM, 0xffff); - } - } - - if (FAL_FIELD_FLG_TST(sw->field_flg, FAL_ACL_FIELD_ICMP_TYPE)) - { - if (0x0 != sw->icmp_type_mask) - { - *b_care = A_TRUE; - } - FIELD_SET(IP4_RUL_V3, ICMP_EN, 1); - - sw->icmp_type_val &= sw->icmp_type_mask; - FIELD_SET(IP4_RUL_V3, IP4ICMPTYPV, sw->icmp_type_val); - FIELD_SET_MASK(IP4_RUL_M3, IP4ICMPTYPM, sw->icmp_type_mask); - } - - if (FAL_FIELD_FLG_TST(sw->field_flg, FAL_ACL_FIELD_ICMP_CODE)) - { - if (0x0 != sw->icmp_code_mask) - { - *b_care = A_TRUE; - } - FIELD_SET(IP4_RUL_V3, ICMP_EN, 1); - - sw->icmp_code_val &= sw->icmp_code_mask; - FIELD_SET(IP4_RUL_V3, IP4ICMPCODEV, sw->icmp_code_val); - FIELD_SET_MASK(IP4_RUL_M3, IP4ICMPCODEM, sw->icmp_code_mask); - } - - if (FAL_FIELD_FLG_TST(sw->field_flg, FAL_ACL_FIELD_TCP_FLAG)) - { - if (0x0 != sw->tcp_flag_mask) - { - *b_care = A_TRUE; - } - - sw->tcp_flag_val &= sw->tcp_flag_mask; - FIELD_SET(IP4_RUL_V3, IP4TCPFLAGV, sw->tcp_flag_val); - FIELD_SET_MASK(IP4_RUL_M3, IP4TCPFLAGM, sw->tcp_flag_mask); - } - - if (FAL_FIELD_FLG_TST(sw->field_flg, FAL_ACL_FIELD_RIPV1)) - { - if (0x0 != sw->ripv1_mask) - { - *b_care = A_TRUE; - } - - sw->ripv1_val &= sw->ripv1_mask; - FIELD_SET(IP4_RUL_V3, IP4RIPV, sw->ripv1_val); - FIELD_SET_MASK(IP4_RUL_M3, IP4RIPM, sw->ripv1_mask); - } - - if (FAL_FIELD_FLG_TST(sw->field_flg, FAL_ACL_FIELD_DHCPV4)) - { - if (0x0 != sw->dhcpv4_mask) - { - *b_care = A_TRUE; - } - - sw->dhcpv4_val &= sw->dhcpv4_mask; - FIELD_SET(IP4_RUL_V3, IP4DHCPV, sw->dhcpv4_val); - FIELD_SET_MASK(IP4_RUL_M3, IP4DHCPM, sw->dhcpv4_mask); - } - - if (FAL_FIELD_FLG_TST(sw->field_flg, FAL_ACL_FIELD_INVERSE_ALL)) - { - FIELD_SET(MAC_RUL_V4, RULE_INV, 1); - } - - return SW_OK; -} - -static sw_error_t -_isisc_acl_rule_ip6r1_parse(fal_acl_rule_t * sw, - hw_filter_t * hw, a_bool_t * b_care) -{ - a_uint32_t i; - - *b_care = A_FALSE; - aos_mem_zero(&(hw->vlu[0]), sizeof (hw->vlu)); - aos_mem_zero(&(hw->msk[0]), sizeof (hw->msk)); - - FIELD_SET_MASK(MAC_RUL_M4, RULE_TYP, ISISC_IP6R1_FILTER); - - if (FAL_FIELD_FLG_TST(sw->field_flg, FAL_ACL_FIELD_IP6_DIP)) - { - for (i = 0; i < 4; i++) - { - if (0x0 != sw->dest_ip6_mask.ul[i]) - { - *b_care = A_TRUE; - } - - sw->dest_ip6_val.ul[3 - i] &= sw->dest_ip6_mask.ul[3 - i]; - hw->vlu[i] = sw->dest_ip6_val.ul[3 - i]; - hw->msk[i] = sw->dest_ip6_mask.ul[3 - i]; - } - } - - if (FAL_FIELD_FLG_TST(sw->field_flg, FAL_ACL_FIELD_INVERSE_ALL)) - { - FIELD_SET(MAC_RUL_V4, RULE_INV, 1); - } - - return SW_OK; -} - -static sw_error_t -_isisc_acl_rule_ip6r2_parse(fal_acl_rule_t * sw, - hw_filter_t * hw, a_bool_t * b_care) -{ - a_uint32_t i; - - *b_care = A_FALSE; - aos_mem_zero(&(hw->vlu[0]), sizeof (hw->vlu)); - aos_mem_zero(&(hw->msk[0]), sizeof (hw->msk)); - - FIELD_SET_MASK(MAC_RUL_M4, RULE_TYP, ISISC_IP6R2_FILTER); - - if (FAL_FIELD_FLG_TST(sw->field_flg, FAL_ACL_FIELD_IP6_SIP)) - { - for (i = 0; i < 4; i++) - { - if (0x0 != sw->src_ip6_mask.ul[i]) - { - *b_care = A_TRUE; - } - - sw->src_ip6_val.ul[3 - i] &= sw->src_ip6_mask.ul[3 - i]; - hw->vlu[i] = sw->src_ip6_val.ul[3 - i]; - hw->msk[i] = sw->src_ip6_mask.ul[3 - i]; - } - } - - if (FAL_FIELD_FLG_TST(sw->field_flg, FAL_ACL_FIELD_INVERSE_ALL)) - { - FIELD_SET(MAC_RUL_V4, RULE_INV, 1); - } - - return SW_OK; -} - -static sw_error_t -_isisc_acl_rule_ip6r3_parse(fal_acl_rule_t * sw, - hw_filter_t * hw, a_bool_t * b_care) -{ - *b_care = A_FALSE; - aos_mem_zero(&(hw->vlu[0]), sizeof (hw->vlu)); - aos_mem_zero(&(hw->msk[0]), sizeof (hw->msk)); - - FIELD_SET_MASK(MAC_RUL_M4, RULE_TYP, ISISC_IP6R3_FILTER); - - if (FAL_FIELD_FLG_TST(sw->field_flg, FAL_ACL_FIELD_IP6_LABEL)) - { - if (0x0 != sw->ip6_lable_mask) - { - *b_care = A_TRUE; - } - - sw->ip6_lable_val &= sw->ip6_lable_mask; - FIELD_SET(IP6_RUL3_V1, IP6LABEL1V, sw->ip6_lable_val); - FIELD_SET_MASK(IP6_RUL3_M1, IP6LABEL1M, sw->ip6_lable_mask); - - FIELD_SET(IP6_RUL3_V2, IP6LABEL2V, (sw->ip6_lable_val >> 16)); - FIELD_SET_MASK(IP6_RUL3_M2, IP6LABEL2M, (sw->ip6_lable_mask >> 16)); - } - - if (FAL_FIELD_FLG_TST(sw->field_flg, FAL_ACL_FIELD_IP_PROTO)) - { - if (0x0 != sw->ip_proto_mask) - { - *b_care = A_TRUE; - } - - sw->ip_proto_val &= sw->ip_proto_mask; - FIELD_SET(IP6_RUL3_V0, IP6PROTV, sw->ip_proto_val); - FIELD_SET_MASK(IP6_RUL3_M0, IP6PROTM, sw->ip_proto_mask); - } - - if (FAL_FIELD_FLG_TST(sw->field_flg, FAL_ACL_FIELD_IP_DSCP)) - { - if (0x0 != sw->ip_dscp_mask) - { - *b_care = A_TRUE; - } - - sw->ip_dscp_val &= sw->ip_dscp_mask; - FIELD_SET(IP6_RUL3_V0, IP6DSCPV, sw->ip_dscp_val); - FIELD_SET_MASK(IP6_RUL3_M0, IP6DSCPM, sw->ip_dscp_mask); - } - - if ((FAL_FIELD_FLG_TST(sw->field_flg, FAL_ACL_FIELD_L4_SPORT)) - && ((FAL_FIELD_FLG_TST(sw->field_flg, FAL_ACL_FIELD_ICMP_TYPE)) - || (FAL_FIELD_FLG_TST(sw->field_flg, FAL_ACL_FIELD_ICMP_CODE)))) - { - return SW_BAD_PARAM; - } - - FIELD_SET_MASK(IP6_RUL3_M3, IP6SPORTM_EN, 1); - if (FAL_FIELD_FLG_TST(sw->field_flg, FAL_ACL_FIELD_L4_SPORT)) - { - if ((FAL_ACL_FIELD_MASK != sw->src_l4port_op) - && (FAL_ACL_FIELD_RANGE != sw->src_l4port_op) - && (FAL_ACL_FIELD_LE != sw->src_l4port_op) - && (FAL_ACL_FIELD_GE != sw->src_l4port_op)) - { - return SW_NOT_SUPPORTED; - } - - if (A_FALSE == - _isisc_acl_field_care(sw->src_l4port_op, sw->src_l4port_val, - sw->src_l4port_mask, 0xffff)) - { - if (FAL_ACL_FIELD_MASK == sw->src_l4port_op) - { - sw->src_l4port_op = FAL_ACL_FIELD_RANGE; - sw->src_l4port_val = 0; - sw->src_l4port_mask = 0xffff; - } - } - *b_care = A_TRUE; - - FIELD_SET_MASK(IP6_RUL3_M3, IP6SPORTM_EN, 0); - if (FAL_ACL_FIELD_MASK == sw->src_l4port_op) - { - sw->src_l4port_val &= sw->src_l4port_mask; - FIELD_SET(IP6_RUL3_V3, IP6SPORTV, sw->src_l4port_val); - FIELD_SET_MASK(IP6_RUL3_M3, IP6SPORTM, sw->src_l4port_mask); - FIELD_SET_MASK(IP6_RUL3_M3, IP6SPORTM_EN, 1); - - } - else if (FAL_ACL_FIELD_RANGE == sw->src_l4port_op) - { - FIELD_SET(IP6_RUL3_V3, IP6SPORTV, sw->src_l4port_val); - FIELD_SET_MASK(IP6_RUL3_M3, IP6SPORTM, sw->src_l4port_mask); - - } - else if (FAL_ACL_FIELD_LE == sw->src_l4port_op) - { - FIELD_SET(IP6_RUL3_V3, IP6SPORTV, 0); - FIELD_SET_MASK(IP6_RUL3_M3, IP6SPORTM, sw->src_l4port_val); - - } - else - { - FIELD_SET(IP6_RUL3_V3, IP6SPORTV, sw->src_l4port_val); - FIELD_SET_MASK(IP6_RUL3_M3, IP6SPORTM, 0xffff); - } - } - - FIELD_SET_MASK(IP6_RUL3_M3, IP6DPORTM_EN, 1); - if (FAL_FIELD_FLG_TST(sw->field_flg, FAL_ACL_FIELD_L4_DPORT)) - { - if ((FAL_ACL_FIELD_MASK != sw->dest_l4port_op) - && (FAL_ACL_FIELD_RANGE != sw->dest_l4port_op) - && (FAL_ACL_FIELD_LE != sw->dest_l4port_op) - && (FAL_ACL_FIELD_GE != sw->dest_l4port_op)) - { - return SW_NOT_SUPPORTED; - } - - if (A_FALSE == - _isisc_acl_field_care(sw->dest_l4port_op, sw->dest_l4port_val, - sw->dest_l4port_mask, 0xffff)) - { - if (FAL_ACL_FIELD_MASK == sw->dest_l4port_op) - { - sw->dest_l4port_op = FAL_ACL_FIELD_RANGE; - sw->dest_l4port_val = 0; - sw->dest_l4port_mask = 0xffff; - } - } - *b_care = A_TRUE; - - FIELD_SET_MASK(IP6_RUL3_M3, IP6DPORTM_EN, 0); - if (FAL_ACL_FIELD_MASK == sw->dest_l4port_op) - { - sw->dest_l4port_val &= sw->dest_l4port_mask; - FIELD_SET(IP6_RUL3_V2, IP6DPORTV, sw->dest_l4port_val); - FIELD_SET_MASK(IP6_RUL3_M2, IP6DPORTM, sw->dest_l4port_mask); - FIELD_SET_MASK(IP6_RUL3_M3, IP6DPORTM_EN, 1); - } - else if (FAL_ACL_FIELD_RANGE == sw->dest_l4port_op) - { - FIELD_SET(IP6_RUL3_V2, IP6DPORTV, sw->dest_l4port_val); - FIELD_SET_MASK(IP6_RUL3_M2, IP6DPORTM, sw->dest_l4port_mask); - } - else if (FAL_ACL_FIELD_LE == sw->dest_l4port_op) - { - FIELD_SET(IP6_RUL3_V2, IP6DPORTV, 0); - FIELD_SET_MASK(IP6_RUL3_M2, IP6DPORTM, sw->dest_l4port_val); - } - else - { - FIELD_SET(IP6_RUL3_V2, IP6DPORTV, sw->dest_l4port_val); - FIELD_SET_MASK(IP6_RUL3_M2, IP6DPORTM, 0xffff); - } - } - - if (FAL_FIELD_FLG_TST(sw->field_flg, FAL_ACL_FIELD_ICMP_TYPE)) - { - if (0x0 != sw->icmp_type_mask) - { - *b_care = A_TRUE; - } - FIELD_SET(IP6_RUL3_V3, ICMP6_EN, 1); - - sw->icmp_type_val &= sw->icmp_type_mask; - FIELD_SET(IP6_RUL3_V3, IP6ICMPTYPV, sw->icmp_type_val); - FIELD_SET_MASK(IP6_RUL3_M3, IP6ICMPTYPM, sw->icmp_type_mask); - } - - if (FAL_FIELD_FLG_TST(sw->field_flg, FAL_ACL_FIELD_ICMP_CODE)) - { - if (0x0 != sw->icmp_code_mask) - { - *b_care = A_TRUE; - } - FIELD_SET(IP6_RUL3_V3, ICMP6_EN, 1); - - sw->icmp_code_val &= sw->icmp_code_mask; - FIELD_SET(IP6_RUL3_V3, IP6ICMPCODEV, sw->icmp_code_val); - FIELD_SET_MASK(IP6_RUL3_M3, IP6ICMPCODEM, sw->icmp_code_mask); - } - - if (FAL_FIELD_FLG_TST(sw->field_flg, FAL_ACL_FIELD_TCP_FLAG)) - { - if (0x0 != sw->tcp_flag_mask) - { - *b_care = A_TRUE; - } - - sw->tcp_flag_val &= sw->tcp_flag_mask; - FIELD_SET(IP6_RUL3_V3, IP6TCPFLAGV, sw->tcp_flag_val); - FIELD_SET_MASK(IP6_RUL3_M3, IP6TCPFLAGM, sw->tcp_flag_mask); - } - - if (FAL_FIELD_FLG_TST(sw->field_flg, FAL_ACL_FIELD_DHCPV6)) - { - if (0x0 != sw->dhcpv6_mask) - { - *b_care = A_TRUE; - } - - sw->dhcpv6_val &= sw->dhcpv6_mask; - FIELD_SET(IP6_RUL3_V3, IP6DHCPV, sw->dhcpv6_val); - FIELD_SET_MASK(IP6_RUL3_M3, IP6DHCPM, sw->dhcpv6_mask); - } - - if (FAL_FIELD_FLG_TST(sw->field_flg, FAL_ACL_FIELD_INVERSE_ALL)) - { - FIELD_SET(MAC_RUL_V4, RULE_INV, 1); - } - - return SW_OK; -} - -static sw_error_t -_isisc_acl_rule_udf_parse(fal_acl_rule_t * sw, - hw_filter_t * hw, a_bool_t * b_care) -{ - a_uint32_t i; - - *b_care = A_FALSE; - aos_mem_zero(&(hw->vlu[0]), sizeof (hw->vlu)); - aos_mem_zero(&(hw->msk[0]), sizeof (hw->msk)); - - FIELD_SET_MASK(MAC_RUL_M4, RULE_TYP, ISISC_UDF_FILTER); - - if (!FAL_FIELD_FLG_TST(sw->field_flg, FAL_ACL_FIELD_UDF)) - { - if (FAL_ACL_RULE_UDF == sw->rule_type) - { - if (FAL_FIELD_FLG_TST(sw->field_flg, FAL_ACL_FIELD_INVERSE_ALL)) - { - FIELD_SET(MAC_RUL_V4, RULE_INV, 1); - } - *b_care = A_TRUE; - } - return SW_OK; - } - - if (ISISC_MAX_UDF_LENGTH < sw->udf_len) - { - return SW_NOT_SUPPORTED; - } - - *b_care = A_TRUE; - for (i = 0; i < sw->udf_len; i++) - { - hw->vlu[3 - i / 4] |= - ((sw->udf_mask[i] & sw->udf_val[i]) << (24 - 8 * (i % 4))); - hw->msk[3 - i / 4] |= ((sw->udf_mask[i]) << (24 - 8 * (i % 4))); - } - - if (FAL_FIELD_FLG_TST(sw->field_flg, FAL_ACL_FIELD_INVERSE_ALL)) - { - FIELD_SET(MAC_RUL_V4, RULE_INV, 1); - } - - return SW_OK; -} - -static sw_error_t -_isisc_acl_action_parse(a_uint32_t dev_id, const fal_acl_rule_t * sw, - hw_filter_t * hw) -{ - fal_pbmp_t des_pts; - - aos_mem_zero(&(hw->act[0]), sizeof (hw->act)); - - if (FAL_ACTION_FLG_TST(sw->action_flg, FAL_ACL_ACTION_MATCH_TRIGGER_INTR)) - { - FIELD_SET_ACTION(ACL_RSLT2, TRIGGER_INTR, 1); - } - - /* FAL_ACL_ACTION_PERMIT need't process */ - - if ((FAL_ACTION_FLG_TST(sw->action_flg, FAL_ACL_ACTION_RDTCPU)) - && (FAL_ACTION_FLG_TST(sw->action_flg, FAL_ACL_ACTION_CPYCPU))) - { - return SW_BAD_PARAM; - } - - if (FAL_ACTION_FLG_TST(sw->action_flg, FAL_ACL_ACTION_RDTCPU)) - { - FIELD_SET_ACTION(ACL_RSLT2, FWD_CMD, 0x3); - } - - if (FAL_ACTION_FLG_TST(sw->action_flg, FAL_ACL_ACTION_CPYCPU)) - { - FIELD_SET_ACTION(ACL_RSLT2, FWD_CMD, 0x1); - } - - if (FAL_ACTION_FLG_TST(sw->action_flg, FAL_ACL_ACTION_DENY)) - { - FIELD_SET_ACTION(ACL_RSLT2, FWD_CMD, 0x7); - } - - if (FAL_ACTION_FLG_TST(sw->action_flg, FAL_ACL_ACTION_MIRROR)) - { - FIELD_SET_ACTION(ACL_RSLT2, MIRR_EN, 1); - } - - if (FAL_ACTION_FLG_TST(sw->action_flg, FAL_ACL_ACTION_REDPT)) - { - FIELD_SET_ACTION(ACL_RSLT2, DES_PORT_EN, 1); - - des_pts = (sw->ports >> 3) & 0xf; - FIELD_SET_ACTION(ACL_RSLT2, DES_PORT1, des_pts); - - des_pts = sw->ports & 0x7; - FIELD_SET_ACTION(ACL_RSLT1, DES_PORT0, des_pts); - } - - if (FAL_ACTION_FLG_TST(sw->action_flg, FAL_ACL_ACTION_REMARK_UP)) - { - return SW_NOT_SUPPORTED; - } - - if (FAL_ACTION_FLG_TST(sw->action_flg, FAL_ACL_ACTION_REMARK_QUEUE)) - { - FIELD_SET_ACTION(ACL_RSLT1, PRI_QU_EN, 1); - FIELD_SET_ACTION(ACL_RSLT1, PRI_QU, sw->queue); - } - - if ((FAL_ACTION_FLG_TST(sw->action_flg, FAL_ACL_ACTION_MODIFY_VLAN)) - || (FAL_ACTION_FLG_TST(sw->action_flg, FAL_ACL_ACTION_NEST_VLAN))) - { - return SW_NOT_SUPPORTED; - } - - if (FAL_ACTION_FLG_TST(sw->action_flg, FAL_ACL_ACTION_REMARK_DSCP)) - { - FIELD_SET_ACTION(ACL_RSLT1, DSCPV, sw->dscp); - FIELD_SET_ACTION(ACL_RSLT1, DSCP_REMAP, 1); - } - - FIELD_SET_ACTION(ACL_RSLT0, STAGVID, sw->stag_vid); - if (FAL_ACTION_FLG_TST(sw->action_flg, FAL_ACL_ACTION_REMARK_STAG_VID)) - { - FIELD_SET_ACTION(ACL_RSLT1, TRANS_SVID_CHG, 1); - } - - if (FAL_ACTION_FLG_TST(sw->action_flg, FAL_ACL_ACTION_REMARK_STAG_PRI)) - { - FIELD_SET_ACTION(ACL_RSLT0, STAGPRI, sw->stag_pri); - FIELD_SET_ACTION(ACL_RSLT1, STAG_PRI_REMAP, 1); - } - - if (FAL_ACTION_FLG_TST(sw->action_flg, FAL_ACL_ACTION_REMARK_STAG_DEI)) - { - FIELD_SET_ACTION(ACL_RSLT0, STAGDEI, sw->stag_dei); - FIELD_SET_ACTION(ACL_RSLT1, STAG_DEI_CHG, 1); - } - - FIELD_SET_ACTION(ACL_RSLT0, CTAGVID, sw->ctag_vid); - if (FAL_ACTION_FLG_TST(sw->action_flg, FAL_ACL_ACTION_REMARK_CTAG_VID)) - { - FIELD_SET_ACTION(ACL_RSLT1, TRANS_CVID_CHG, 1); - } - - if (FAL_ACTION_FLG_TST(sw->action_flg, FAL_ACL_ACTION_REMARK_CTAG_PRI)) - { - FIELD_SET_ACTION(ACL_RSLT0, CTAGPRI, sw->ctag_pri); - FIELD_SET_ACTION(ACL_RSLT1, CTAG_PRI_REMAP, 1); - } - - if (FAL_ACTION_FLG_TST(sw->action_flg, FAL_ACL_ACTION_REMARK_CTAG_CFI)) - { - FIELD_SET_ACTION(ACL_RSLT0, CTAGCFI, sw->ctag_cfi); - FIELD_SET_ACTION(ACL_RSLT1, CTAG_CFI_CHG, 1); - } - - if (FAL_ACTION_FLG_TST(sw->action_flg, FAL_ACL_ACTION_REMARK_LOOKUP_VID)) - { - FIELD_SET_ACTION(ACL_RSLT1, LOOK_VID_CHG, 1); - } - - if (FAL_ACTION_FLG_TST(sw->action_flg, FAL_ACL_ACTION_POLICER_EN)) - { - FIELD_SET_ACTION(ACL_RSLT2, POLICER_PTR, sw->policer_ptr); - FIELD_SET_ACTION(ACL_RSLT2, POLICER_EN, 1); - } - - if ((FAL_ACTION_FLG_TST(sw->action_flg, FAL_ACL_ACTION_ARP_EN)) - && (FAL_ACTION_FLG_TST(sw->action_flg, FAL_ACL_ACTION_WCMP_EN))) - { - return SW_NOT_SUPPORTED; - } - - if (FAL_ACTION_FLG_TST(sw->action_flg, FAL_ACL_ACTION_ARP_EN)) - { - FIELD_SET_ACTION(ACL_RSLT1, ARP_PTR, sw->arp_ptr); - FIELD_SET_ACTION(ACL_RSLT1, ARP_PTR_EN, 1); - } - - if (FAL_ACTION_FLG_TST(sw->action_flg, FAL_ACL_ACTION_WCMP_EN)) - { - FIELD_SET_ACTION(ACL_RSLT1, ARP_PTR, sw->wcmp_ptr); - FIELD_SET_ACTION(ACL_RSLT1, WCMP_EN, 1); - FIELD_SET_ACTION(ACL_RSLT1, ARP_PTR_EN, 1); - } - - FIELD_SET_ACTION(ACL_RSLT1, FORCE_L3_MODE, 0x0); - if (FAL_ACTION_FLG_TST(sw->action_flg, FAL_ACL_ACTION_POLICY_FORWARD_EN)) - { - if (FAL_ACL_POLICY_ROUTE == sw->policy_fwd) - { - return SW_NOT_SUPPORTED; - } - else if (FAL_ACL_POLICY_SNAT == sw->policy_fwd) - { - FIELD_SET_ACTION(ACL_RSLT1, FORCE_L3_MODE, 0x1); - } - else if (FAL_ACL_POLICY_DNAT == sw->policy_fwd) - { - FIELD_SET_ACTION(ACL_RSLT1, FORCE_L3_MODE, 0x2); - } - else if (FAL_ACL_POLICY_RESERVE == sw->policy_fwd) - { - FIELD_SET_ACTION(ACL_RSLT1, FORCE_L3_MODE, 0x3); - } - else - { - return SW_BAD_PARAM; - } - } - - if (FAL_ACTION_FLG_TST(sw->action_flg, FAL_ACL_ACTION_BYPASS_EGRESS_TRANS)) - { - FIELD_SET_ACTION(ACL_RSLT2, EG_BYPASS, 1); - } - - if (FAL_ACTION_FLG_TST(sw->action_flg, FAL_ACL_ACTION_MATCH_TRIGGER_INTR)) - { - FIELD_SET_ACTION(ACL_RSLT2, TRIGGER_INTR, 1); - } - - return SW_OK; -} - -static sw_error_t -_isisc_acl_rule_bmac_reparse(fal_acl_rule_t * sw, const hw_filter_t * hw) -{ - a_uint32_t mask_en; - - /* destnation mac address */ - FIELD_GET(MAC_RUL_V0, DAV_BYTE2, sw->dest_mac_val.uc[2]); - FIELD_GET(MAC_RUL_V0, DAV_BYTE3, sw->dest_mac_val.uc[3]); - FIELD_GET(MAC_RUL_V0, DAV_BYTE4, sw->dest_mac_val.uc[4]); - FIELD_GET(MAC_RUL_V0, DAV_BYTE5, sw->dest_mac_val.uc[5]); - FIELD_GET(MAC_RUL_V1, DAV_BYTE0, sw->dest_mac_val.uc[0]); - FIELD_GET(MAC_RUL_V1, DAV_BYTE1, sw->dest_mac_val.uc[1]); - - FIELD_GET_MASK(MAC_RUL_M0, DAM_BYTE2, sw->dest_mac_mask.uc[2]); - FIELD_GET_MASK(MAC_RUL_M0, DAM_BYTE3, sw->dest_mac_mask.uc[3]); - FIELD_GET_MASK(MAC_RUL_M0, DAM_BYTE4, sw->dest_mac_mask.uc[4]); - FIELD_GET_MASK(MAC_RUL_M0, DAM_BYTE5, sw->dest_mac_mask.uc[5]); - FIELD_GET_MASK(MAC_RUL_M1, DAM_BYTE0, sw->dest_mac_mask.uc[0]); - FIELD_GET_MASK(MAC_RUL_M1, DAM_BYTE1, sw->dest_mac_mask.uc[1]); - if (A_FALSE == _isisc_acl_zero_addr(sw->dest_mac_mask)) - { - FAL_FIELD_FLG_SET(sw->field_flg, FAL_ACL_FIELD_MAC_DA); - } - - /* source mac address */ - FIELD_GET(MAC_RUL_V2, SAV_BYTE0, sw->src_mac_val.uc[0]); - FIELD_GET(MAC_RUL_V2, SAV_BYTE1, sw->src_mac_val.uc[1]); - FIELD_GET(MAC_RUL_V2, SAV_BYTE2, sw->src_mac_val.uc[2]); - FIELD_GET(MAC_RUL_V2, SAV_BYTE3, sw->src_mac_val.uc[3]); - FIELD_GET(MAC_RUL_V1, SAV_BYTE4, sw->src_mac_val.uc[4]); - FIELD_GET(MAC_RUL_V1, SAV_BYTE5, sw->src_mac_val.uc[5]); - - FIELD_GET_MASK(MAC_RUL_M2, SAM_BYTE0, sw->src_mac_mask.uc[0]); - FIELD_GET_MASK(MAC_RUL_M2, SAM_BYTE1, sw->src_mac_mask.uc[1]); - FIELD_GET_MASK(MAC_RUL_M2, SAM_BYTE2, sw->src_mac_mask.uc[2]); - FIELD_GET_MASK(MAC_RUL_M2, SAM_BYTE3, sw->src_mac_mask.uc[3]); - FIELD_GET_MASK(MAC_RUL_M1, SAM_BYTE4, sw->src_mac_mask.uc[4]); - FIELD_GET_MASK(MAC_RUL_M1, SAM_BYTE5, sw->src_mac_mask.uc[5]); - if (A_FALSE == _isisc_acl_zero_addr(sw->src_mac_mask)) - { - FAL_FIELD_FLG_SET(sw->field_flg, FAL_ACL_FIELD_MAC_SA); - } - - /* ethernet type */ - FIELD_GET(MAC_RUL_V3, ETHTYPV, sw->ethtype_val); - FIELD_GET_MASK(MAC_RUL_M3, ETHTYPM, sw->ethtype_mask); - if (0x0 != sw->ethtype_mask) - { - FAL_FIELD_FLG_SET(sw->field_flg, FAL_ACL_FIELD_MAC_ETHTYPE); - } - - /* packet tagged */ - FIELD_GET_MASK(MAC_RUL_M4, TAGGEDV, sw->tagged_val); - FIELD_GET_MASK(MAC_RUL_M4, TAGGEDM, sw->tagged_mask); - if (0x0 != sw->tagged_mask) - { - FAL_FIELD_FLG_SET(sw->field_flg, FAL_ACL_FIELD_MAC_TAGGED); - } - - /* vlan priority */ - FIELD_GET(MAC_RUL_V3, VLANPRIV, sw->up_val); - FIELD_GET_MASK(MAC_RUL_M3, VLANPRIM, sw->up_mask); - if (0x0 != sw->up_mask) - { - FAL_FIELD_FLG_SET(sw->field_flg, FAL_ACL_FIELD_MAC_UP); - } - - /* vlanid */ - FIELD_GET(MAC_RUL_V3, VLANIDV, sw->vid_val); - FIELD_GET_MASK(MAC_RUL_M3, VLANIDM, sw->vid_mask); - FIELD_GET_MASK(MAC_RUL_M4, VIDMSK, mask_en); - if (mask_en) - { - sw->vid_op = FAL_ACL_FIELD_MASK; - } - else - { - sw->vid_op = FAL_ACL_FIELD_RANGE; - } - - if (A_TRUE == - _isisc_acl_field_care(sw->vid_op, (a_uint32_t) sw->vid_val, - (a_uint32_t) sw->vid_mask, 0xfff)) - { - FAL_FIELD_FLG_SET(sw->field_flg, FAL_ACL_FIELD_MAC_VID); - } - - /* vlan cfi */ - FIELD_GET(MAC_RUL_V3, VLANCFIV, sw->cfi_val); - FIELD_GET_MASK(MAC_RUL_M3, VLANCFIM, sw->cfi_mask); - if (0x0 != sw->cfi_mask) - { - FAL_FIELD_FLG_SET(sw->field_flg, FAL_ACL_FIELD_MAC_CFI); - } - - FIELD_GET(MAC_RUL_V4, RULE_INV, mask_en); - if (mask_en) - { - FAL_FIELD_FLG_SET(sw->field_flg, FAL_ACL_FIELD_INVERSE_ALL); - } - - return SW_OK; -} - -static sw_error_t -_isisc_acl_rule_ehmac_reparse(fal_acl_rule_t * sw, const hw_filter_t * hw) -{ - a_uint32_t i, mask_en, data; - - FIELD_GET(EHMAC_RUL_V3, DA_EN, data); - if (data) - { - for (i = 2; i < 6; i++) - { - sw->dest_mac_val.uc[i] = ((hw->vlu[0]) >> ((5 - i) << 3)) & 0xff; - sw->dest_mac_mask.uc[i] = ((hw->msk[0]) >> ((5 - i) << 3)) & 0xff; - } - - for (i = 0; i < 2; i++) - { - sw->dest_mac_val.uc[i] = ((hw->vlu[1]) >> ((1 - i) << 3)) & 0xff; - sw->dest_mac_mask.uc[i] = ((hw->msk[1]) >> ((1 - i) << 3)) & 0xff; - } - - if (A_FALSE == _isisc_acl_zero_addr(sw->dest_mac_mask)) - { - FAL_FIELD_FLG_SET(sw->field_flg, FAL_ACL_FIELD_MAC_DA); - } - - FIELD_GET(EHMAC_RUL_V2, SAV_BYTE3, sw->src_mac_val.uc[3]); - FIELD_GET(EHMAC_RUL_V1, SAV_BYTE4, sw->src_mac_val.uc[4]); - FIELD_GET(EHMAC_RUL_V1, SAV_BYTE5, sw->src_mac_val.uc[5]); - - FIELD_GET_MASK(EHMAC_RUL_M2, SAM_BYTE3, sw->src_mac_mask.uc[3]); - FIELD_GET_MASK(EHMAC_RUL_M1, SAM_BYTE4, sw->src_mac_mask.uc[4]); - FIELD_GET_MASK(EHMAC_RUL_M1, SAM_BYTE5, sw->src_mac_mask.uc[5]); - - if (A_FALSE == _isisc_acl_zero_addr(sw->src_mac_mask)) - { - FAL_FIELD_FLG_SET(sw->field_flg, FAL_ACL_FIELD_MAC_SA); - } - } - else - { - for (i = 2; i < 6; i++) - { - sw->src_mac_val.uc[i] = ((hw->vlu[0]) >> ((5 - i) << 3)) & 0xff; - sw->src_mac_mask.uc[i] = ((hw->msk[0]) >> ((5 - i) << 3)) & 0xff; - } - - for (i = 0; i < 2; i++) - { - sw->src_mac_val.uc[i] = ((hw->vlu[1]) >> ((1 - i) << 3)) & 0xff; - sw->src_mac_mask.uc[i] = ((hw->msk[1]) >> ((1 - i) << 3)) & 0xff; - } - - if (A_FALSE == _isisc_acl_zero_addr(sw->src_mac_mask)) - { - FAL_FIELD_FLG_SET(sw->field_flg, FAL_ACL_FIELD_MAC_SA); - } - - FIELD_GET(EHMAC_RUL_V2, SAV_BYTE3, sw->dest_mac_val.uc[3]); - FIELD_GET(EHMAC_RUL_V1, SAV_BYTE4, sw->dest_mac_val.uc[4]); - FIELD_GET(EHMAC_RUL_V1, SAV_BYTE5, sw->dest_mac_val.uc[5]); - - FIELD_GET_MASK(EHMAC_RUL_M2, SAM_BYTE3, sw->dest_mac_mask.uc[3]); - FIELD_GET_MASK(EHMAC_RUL_M1, SAM_BYTE4, sw->dest_mac_mask.uc[4]); - FIELD_GET_MASK(EHMAC_RUL_M1, SAM_BYTE5, sw->dest_mac_mask.uc[5]); - if (A_FALSE == _isisc_acl_zero_addr(sw->dest_mac_mask)) - { - FAL_FIELD_FLG_SET(sw->field_flg, FAL_ACL_FIELD_MAC_DA); - } - } - - /* ethernet type */ - FIELD_GET(EHMAC_RUL_V3, ETHTYPV, sw->ethtype_val); - FIELD_GET_MASK(EHMAC_RUL_M3, ETHTYPM, sw->ethtype_mask); - if (0x0 != sw->ethtype_mask) - { - FAL_FIELD_FLG_SET(sw->field_flg, FAL_ACL_FIELD_MAC_ETHTYPE); - } - - /* packet stagged */ - FIELD_GET(EHMAC_RUL_V3, STAGGEDV, sw->stagged_val); - FIELD_GET(EHMAC_RUL_V3, STAGGEDM, sw->stagged_mask); - if (0x0 != sw->stagged_mask) - { - FAL_FIELD_FLG_SET(sw->field_flg, FAL_ACL_FIELD_MAC_STAGGED); - } - - /* stag vid */ - FIELD_GET(EHMAC_RUL_V2, STAG_VIDV, sw->stag_vid_val); - FIELD_GET_MASK(EHMAC_RUL_M2, STAG_VIDM, sw->stag_vid_mask); - FIELD_GET(EHMAC_RUL_V3, SVIDMSK, mask_en); - if (mask_en) - { - sw->stag_vid_op = FAL_ACL_FIELD_MASK; - } - else - { - sw->stag_vid_op = FAL_ACL_FIELD_RANGE; - } - - if (A_TRUE == - _isisc_acl_field_care(sw->stag_vid_op, (a_uint32_t) sw->stag_vid_val, - (a_uint32_t) sw->stag_vid_mask, 0xfff)) - { - FAL_FIELD_FLG_SET(sw->field_flg, FAL_ACL_FIELD_MAC_STAG_VID); - } - - /* stag priority */ - FIELD_GET(EHMAC_RUL_V2, STAG_PRIV, sw->stag_pri_val); - FIELD_GET_MASK(EHMAC_RUL_M2, STAG_PRIM, sw->stag_pri_mask); - if (0x0 != sw->stag_pri_mask) - { - FAL_FIELD_FLG_SET(sw->field_flg, FAL_ACL_FIELD_MAC_STAG_PRI); - } - - /* stag dei */ - FIELD_GET(EHMAC_RUL_V2, STAG_DEIV, sw->stag_dei_val); - FIELD_GET_MASK(EHMAC_RUL_M2, STAG_DEIM, sw->stag_dei_mask); - if (0x0 != sw->stag_dei_mask) - { - FAL_FIELD_FLG_SET(sw->field_flg, FAL_ACL_FIELD_MAC_STAG_DEI); - } - - /* packet ctagged */ - FIELD_GET_MASK(EHMAC_RUL_M4, CTAGGEDV, sw->ctagged_val); - FIELD_GET_MASK(EHMAC_RUL_M4, CTAGGEDM, sw->ctagged_mask); - if (0x0 != sw->ctagged_mask) - { - FAL_FIELD_FLG_SET(sw->field_flg, FAL_ACL_FIELD_MAC_CTAGGED); - } - - /* ctag vid */ - FIELD_GET(EHMAC_RUL_V2, CTAG_VIDLV, sw->ctag_vid_val); - FIELD_GET(EHMAC_RUL_V3, CTAG_VIDHV, data); - sw->ctag_vid_val |= (data << 8); - FIELD_GET_MASK(EHMAC_RUL_M2, CTAG_VIDLM, sw->ctag_vid_mask); - FIELD_GET_MASK(EHMAC_RUL_M3, CTAG_VIDHM, data); - sw->ctag_vid_mask |= (data << 8); - - FIELD_GET_MASK(EHMAC_RUL_M4, CVIDMSK, mask_en); - if (mask_en) - { - sw->ctag_vid_op = FAL_ACL_FIELD_MASK; - } - else - { - sw->ctag_vid_op = FAL_ACL_FIELD_RANGE; - } - - if (A_TRUE == - _isisc_acl_field_care(sw->ctag_vid_op, (a_uint32_t) sw->ctag_vid_val, - (a_uint32_t) sw->ctag_vid_mask, 0xfff)) - { - FAL_FIELD_FLG_SET(sw->field_flg, FAL_ACL_FIELD_MAC_CTAG_VID); - } - - /* ctag priority */ - FIELD_GET(EHMAC_RUL_V3, CTAG_PRIV, sw->ctag_pri_val); - FIELD_GET_MASK(EHMAC_RUL_M3, CTAG_PRIM, sw->ctag_pri_mask); - if (0x0 != sw->ctag_pri_mask) - { - FAL_FIELD_FLG_SET(sw->field_flg, FAL_ACL_FIELD_MAC_CTAG_PRI); - } - - /* ctag dei */ - FIELD_GET(EHMAC_RUL_V3, CTAG_CFIV, sw->ctag_cfi_val); - FIELD_GET_MASK(EHMAC_RUL_M3, CTAG_CFIM, sw->ctag_cfi_mask); - if (0x0 != sw->ctag_cfi_mask) - { - FAL_FIELD_FLG_SET(sw->field_flg, FAL_ACL_FIELD_MAC_CTAG_CFI); - } - - FIELD_GET(MAC_RUL_V4, RULE_INV, mask_en); - if (mask_en) - { - FAL_FIELD_FLG_SET(sw->field_flg, FAL_ACL_FIELD_INVERSE_ALL); - } - - return SW_OK; -} - -static sw_error_t -_isisc_acl_rule_ip4_reparse(fal_acl_rule_t * sw, const hw_filter_t * hw) -{ - a_uint32_t mask_en, icmp_en; - - sw->dest_ip4_val = hw->vlu[0]; - sw->dest_ip4_mask = hw->msk[0]; - if (0x0 != sw->dest_ip4_mask) - { - FAL_FIELD_FLG_SET(sw->field_flg, FAL_ACL_FIELD_IP4_DIP); - } - - sw->src_ip4_val = hw->vlu[1]; - sw->src_ip4_mask = hw->msk[1]; - if (0x0 != sw->src_ip4_mask) - { - FAL_FIELD_FLG_SET(sw->field_flg, FAL_ACL_FIELD_IP4_SIP); - } - - FIELD_GET(IP4_RUL_V2, IP4PROTV, sw->ip_proto_val); - FIELD_GET_MASK(IP4_RUL_M2, IP4PROTM, sw->ip_proto_mask); - if (0x0 != sw->ip_proto_mask) - { - FAL_FIELD_FLG_SET(sw->field_flg, FAL_ACL_FIELD_IP_PROTO); - } - - FIELD_GET(IP4_RUL_V2, IP4DSCPV, sw->ip_dscp_val); - FIELD_GET_MASK(IP4_RUL_M2, IP4DSCPM, sw->ip_dscp_mask); - if (0x0 != sw->ip_dscp_mask) - { - FAL_FIELD_FLG_SET(sw->field_flg, FAL_ACL_FIELD_IP_DSCP); - } - - FIELD_GET(IP4_RUL_V2, IP4DPORTV, sw->dest_l4port_val); - FIELD_GET_MASK(IP4_RUL_M2, IP4DPORTM, sw->dest_l4port_mask); - FIELD_GET_MASK(IP4_RUL_M3, IP4DPORTM_EN, mask_en); - if (mask_en) - { - sw->dest_l4port_op = FAL_ACL_FIELD_MASK; - } - else - { - sw->dest_l4port_op = FAL_ACL_FIELD_RANGE; - } - - if (A_TRUE == - _isisc_acl_field_care(sw->dest_l4port_op, - (a_uint32_t) sw->dest_l4port_val, - (a_uint32_t) sw->dest_l4port_mask, 0xffff)) - { - FAL_FIELD_FLG_SET(sw->field_flg, FAL_ACL_FIELD_L4_DPORT); - } - else if (FAL_ACL_FIELD_RANGE == sw->dest_l4port_op) - { - FAL_FIELD_FLG_SET(sw->field_flg, FAL_ACL_FIELD_L4_DPORT); - } - - FIELD_GET(IP4_RUL_V3, ICMP_EN, icmp_en); - if (icmp_en) - { - FIELD_GET(IP4_RUL_V3, IP4ICMPTYPV, sw->icmp_type_val); - FIELD_GET_MASK(IP4_RUL_M3, IP4ICMPTYPM, sw->icmp_type_mask); - if (0x0 != sw->icmp_type_mask) - { - FAL_FIELD_FLG_SET(sw->field_flg, FAL_ACL_FIELD_ICMP_TYPE); - } - - FIELD_GET(IP4_RUL_V3, IP4ICMPCODEV, sw->icmp_code_val); - FIELD_GET_MASK(IP4_RUL_M3, IP4ICMPCODEM, sw->icmp_code_mask); - if (0x0 != sw->icmp_code_mask) - { - FAL_FIELD_FLG_SET(sw->field_flg, FAL_ACL_FIELD_ICMP_CODE); - } - } - else - { - FIELD_GET(IP4_RUL_V3, IP4SPORTV, sw->src_l4port_val); - FIELD_GET_MASK(IP4_RUL_M3, IP4SPORTM, sw->src_l4port_mask); - FIELD_GET_MASK(IP4_RUL_M3, IP4SPORTM_EN, mask_en); - if (mask_en) - { - sw->src_l4port_op = FAL_ACL_FIELD_MASK; - } - else - { - sw->src_l4port_op = FAL_ACL_FIELD_RANGE; - } - - if (A_TRUE == - _isisc_acl_field_care(sw->src_l4port_op, - (a_uint32_t) sw->src_l4port_val, - (a_uint32_t) sw->src_l4port_mask, 0xffff)) - { - FAL_FIELD_FLG_SET(sw->field_flg, FAL_ACL_FIELD_L4_SPORT); - } - else if (FAL_ACL_FIELD_RANGE == sw->src_l4port_op) - { - FAL_FIELD_FLG_SET(sw->field_flg, FAL_ACL_FIELD_L4_SPORT); - } - } - - FIELD_GET(IP4_RUL_V3, IP4TCPFLAGV, sw->tcp_flag_val); - FIELD_GET_MASK(IP4_RUL_M3, IP4TCPFLAGM, sw->tcp_flag_mask); - if (0x0 != sw->tcp_flag_mask) - { - FAL_FIELD_FLG_SET(sw->field_flg, FAL_ACL_FIELD_TCP_FLAG); - } - - FIELD_GET(IP4_RUL_V3, IP4RIPV, sw->ripv1_val); - FIELD_GET_MASK(IP4_RUL_M3, IP4RIPM, sw->ripv1_mask); - if (0x0 != sw->ripv1_mask) - { - FAL_FIELD_FLG_SET(sw->field_flg, FAL_ACL_FIELD_RIPV1); - } - - FIELD_GET(IP4_RUL_V3, IP4DHCPV, sw->dhcpv4_val); - FIELD_GET_MASK(IP4_RUL_M3, IP4DHCPM, sw->dhcpv4_mask); - if (0x0 != sw->dhcpv4_mask) - { - FAL_FIELD_FLG_SET(sw->field_flg, FAL_ACL_FIELD_DHCPV4); - } - - FIELD_GET(MAC_RUL_V4, RULE_INV, mask_en); - if (mask_en) - { - FAL_FIELD_FLG_SET(sw->field_flg, FAL_ACL_FIELD_INVERSE_ALL); - } - - return SW_OK; -} - -static sw_error_t -_isisc_acl_rule_ip6r1_reparse(fal_acl_rule_t * sw, const hw_filter_t * hw) -{ - a_uint32_t i; - - for (i = 0; i < 4; i++) - { - sw->dest_ip6_val.ul[i] = hw->vlu[3 - i]; - sw->dest_ip6_mask.ul[i] = hw->msk[3 - i]; - if (0x0 != sw->dest_ip6_mask.ul[i]) - { - FAL_FIELD_FLG_SET(sw->field_flg, FAL_ACL_FIELD_IP6_DIP); - } - } - - FIELD_GET(MAC_RUL_V4, RULE_INV, i); - if (i) - { - FAL_FIELD_FLG_SET(sw->field_flg, FAL_ACL_FIELD_INVERSE_ALL); - } - - return SW_OK; -} - -static sw_error_t -_isisc_acl_rule_ip6r2_reparse(fal_acl_rule_t * sw, const hw_filter_t * hw) -{ - a_uint32_t i; - - for (i = 0; i < 4; i++) - { - sw->src_ip6_val.ul[i] = hw->vlu[3 - i]; - sw->src_ip6_mask.ul[i] = hw->msk[3 - i]; - if (0x0 != sw->src_ip6_mask.ul[i]) - { - FAL_FIELD_FLG_SET(sw->field_flg, FAL_ACL_FIELD_IP6_SIP); - } - } - - FIELD_GET(MAC_RUL_V4, RULE_INV, i); - if (i) - { - FAL_FIELD_FLG_SET(sw->field_flg, FAL_ACL_FIELD_INVERSE_ALL); - } - - return SW_OK; -} - -static sw_error_t -_isisc_acl_rule_ip6r3_reparse(fal_acl_rule_t * sw, const hw_filter_t * hw) -{ - a_uint32_t mask_en, icmp6_en, tmp; - - FIELD_GET(IP6_RUL3_V0, IP6PROTV, sw->ip_proto_val); - FIELD_GET_MASK(IP6_RUL3_M0, IP6PROTM, sw->ip_proto_mask); - if (0x0 != sw->ip_proto_mask) - { - FAL_FIELD_FLG_SET(sw->field_flg, FAL_ACL_FIELD_IP_PROTO); - } - - FIELD_GET(IP6_RUL3_V0, IP6DSCPV, sw->ip_dscp_val); - FIELD_GET_MASK(IP6_RUL3_M0, IP6DSCPM, sw->ip_dscp_mask); - if (0x0 != sw->ip_dscp_mask) - { - FAL_FIELD_FLG_SET(sw->field_flg, FAL_ACL_FIELD_IP_DSCP); - } - - FIELD_GET(IP6_RUL3_V2, IP6DPORTV, sw->dest_l4port_val); - FIELD_GET_MASK(IP6_RUL3_M2, IP6DPORTM, sw->dest_l4port_mask); - FIELD_GET_MASK(IP6_RUL3_M3, IP6DPORTM_EN, mask_en); - if (mask_en) - { - sw->dest_l4port_op = FAL_ACL_FIELD_MASK; - } - else - { - sw->dest_l4port_op = FAL_ACL_FIELD_RANGE; - } - - if (A_TRUE == - _isisc_acl_field_care(sw->dest_l4port_op, - (a_uint32_t) sw->dest_l4port_val, - (a_uint32_t) sw->dest_l4port_mask, 0xffff)) - { - FAL_FIELD_FLG_SET(sw->field_flg, FAL_ACL_FIELD_L4_DPORT); - } - else if (FAL_ACL_FIELD_RANGE == sw->dest_l4port_op) - { - FAL_FIELD_FLG_SET(sw->field_flg, FAL_ACL_FIELD_L4_DPORT); - } - - FIELD_GET(IP6_RUL3_V3, ICMP6_EN, icmp6_en); - if (icmp6_en) - { - FIELD_GET(IP6_RUL3_V3, IP6ICMPTYPV, sw->icmp_type_val); - FIELD_GET_MASK(IP6_RUL3_M3, IP6ICMPTYPM, sw->icmp_type_mask); - if (0x0 != sw->icmp_type_mask) - { - FAL_FIELD_FLG_SET(sw->field_flg, FAL_ACL_FIELD_ICMP_TYPE); - } - - FIELD_GET(IP6_RUL3_V3, IP6ICMPCODEV, sw->icmp_code_val); - FIELD_GET_MASK(IP6_RUL3_M3, IP6ICMPCODEM, sw->icmp_code_mask); - if (0x0 != sw->icmp_code_mask) - { - FAL_FIELD_FLG_SET(sw->field_flg, FAL_ACL_FIELD_ICMP_CODE); - } - } - else - { - FIELD_GET(IP6_RUL3_V3, IP6SPORTV, sw->src_l4port_val); - FIELD_GET_MASK(IP6_RUL3_M3, IP6SPORTM, sw->src_l4port_mask); - FIELD_GET_MASK(IP6_RUL3_M3, IP6SPORTM_EN, mask_en); - if (mask_en) - { - sw->src_l4port_op = FAL_ACL_FIELD_MASK; - } - else - { - sw->src_l4port_op = FAL_ACL_FIELD_RANGE; - } - - if (A_TRUE == - _isisc_acl_field_care(sw->src_l4port_op, - (a_uint32_t) sw->src_l4port_val, - (a_uint32_t) sw->src_l4port_mask, 0xffff)) - { - FAL_FIELD_FLG_SET(sw->field_flg, FAL_ACL_FIELD_L4_SPORT); - } - else if (FAL_ACL_FIELD_RANGE == sw->src_l4port_op) - { - FAL_FIELD_FLG_SET(sw->field_flg, FAL_ACL_FIELD_L4_SPORT); - } - } - - FIELD_GET(IP6_RUL3_V1, IP6LABEL1V, sw->ip6_lable_val); - FIELD_GET_MASK(IP6_RUL3_M1, IP6LABEL1M, sw->ip6_lable_mask); - - FIELD_GET(IP6_RUL3_V2, IP6LABEL2V, tmp); - sw->ip6_lable_val |= (tmp << 16); - FIELD_GET_MASK(IP6_RUL3_M2, IP6LABEL2M, tmp); - sw->ip6_lable_mask |= (tmp << 16); - - if (0x0 != sw->ip6_lable_mask) - { - FAL_FIELD_FLG_SET(sw->field_flg, FAL_ACL_FIELD_IP6_LABEL); - } - - FIELD_GET(IP6_RUL3_V3, IP6TCPFLAGV, sw->tcp_flag_val); - FIELD_GET_MASK(IP6_RUL3_M3, IP6TCPFLAGM, sw->tcp_flag_mask); - if (0x0 != sw->tcp_flag_mask) - { - FAL_FIELD_FLG_SET(sw->field_flg, FAL_ACL_FIELD_TCP_FLAG); - } - - FIELD_GET(IP6_RUL3_V3, IP6DHCPV, sw->dhcpv6_val); - FIELD_GET_MASK(IP6_RUL3_M3, IP6DHCPM, sw->dhcpv6_mask); - if (0x0 != sw->dhcpv6_mask) - { - FAL_FIELD_FLG_SET(sw->field_flg, FAL_ACL_FIELD_DHCPV6); - } - - FIELD_GET(MAC_RUL_V4, RULE_INV, mask_en); - if (mask_en) - { - FAL_FIELD_FLG_SET(sw->field_flg, FAL_ACL_FIELD_INVERSE_ALL); - } - - return SW_OK; -} - -static sw_error_t -_isisc_acl_rule_udf_reparse(fal_acl_rule_t * sw, const hw_filter_t * hw) -{ - a_uint32_t i; - - FAL_FIELD_FLG_SET(sw->field_flg, FAL_ACL_FIELD_UDF); - - /* for ISIS UDF type, length and offset no meanging in rules, just set default value */ - sw->udf_type = FAL_ACL_UDF_TYPE_L2; - sw->udf_len = 16; - sw->udf_offset = 0; - - for (i = 0; i < ISISC_MAX_UDF_LENGTH; i++) - { - sw->udf_val[i] = ((hw->vlu[3 - i / 4]) >> (24 - 8 * (i % 4))) & 0xff; - sw->udf_mask[i] = ((hw->msk[3 - i / 4]) >> (24 - 8 * (i % 4))) & 0xff; - } - - FIELD_GET(MAC_RUL_V4, RULE_INV, i); - if (i) - { - FAL_FIELD_FLG_SET(sw->field_flg, FAL_ACL_FIELD_INVERSE_ALL); - } - - return SW_OK; -} - -static sw_error_t -_isisc_acl_rule_action_reparse(fal_acl_rule_t * sw, const hw_filter_t * hw) -{ - a_uint32_t data; - - sw->action_flg = 0; - - FIELD_GET_ACTION(ACL_RSLT2, DES_PORT_EN, data); - if (1 == data) - { - FAL_ACTION_FLG_SET(sw->action_flg, FAL_ACL_ACTION_REDPT); - FIELD_GET_ACTION(ACL_RSLT1, DES_PORT0, sw->ports); - FIELD_GET_ACTION(ACL_RSLT2, DES_PORT1, data); - sw->ports |= (data << 3); - } - - FIELD_GET_ACTION(ACL_RSLT2, FWD_CMD, data); - if (0x7 == data) - { - FAL_ACTION_FLG_SET(sw->action_flg, FAL_ACL_ACTION_DENY); - } - else if (0x3 == data) - { - FAL_ACTION_FLG_SET(sw->action_flg, FAL_ACL_ACTION_RDTCPU); - } - else if (0x1 == data) - { - FAL_ACTION_FLG_SET(sw->action_flg, FAL_ACL_ACTION_CPYCPU); - } - else - { - /* need't set permit action */ - } - - FIELD_GET_ACTION(ACL_RSLT2, MIRR_EN, data); - if (1 == data) - { - FAL_ACTION_FLG_SET(sw->action_flg, FAL_ACL_ACTION_MIRROR); - } - - FIELD_GET_ACTION(ACL_RSLT1, PRI_QU_EN, data); - if (1 == data) - { - FAL_ACTION_FLG_SET(sw->action_flg, FAL_ACL_ACTION_REMARK_QUEUE); - FIELD_GET_ACTION(ACL_RSLT1, PRI_QU, sw->queue); - } - - FIELD_GET_ACTION(ACL_RSLT1, DSCP_REMAP, data); - if (data) - { - FAL_ACTION_FLG_SET(sw->action_flg, FAL_ACL_ACTION_REMARK_DSCP); - FIELD_GET_ACTION(ACL_RSLT1, DSCPV, sw->dscp); - } - - FIELD_GET_ACTION(ACL_RSLT0, STAGVID, sw->stag_vid); - - FIELD_GET_ACTION(ACL_RSLT1, TRANS_SVID_CHG, data); - if (data) - { - FAL_ACTION_FLG_SET(sw->action_flg, FAL_ACL_ACTION_REMARK_STAG_VID); - } - - FIELD_GET_ACTION(ACL_RSLT1, STAG_PRI_REMAP, data); - if (data) - { - FAL_ACTION_FLG_SET(sw->action_flg, FAL_ACL_ACTION_REMARK_STAG_PRI); - FIELD_GET_ACTION(ACL_RSLT0, STAGPRI, sw->stag_pri); - } - - FIELD_GET_ACTION(ACL_RSLT1, STAG_DEI_CHG, data); - if (data) - { - FAL_ACTION_FLG_SET(sw->action_flg, FAL_ACL_ACTION_REMARK_STAG_DEI); - FIELD_GET_ACTION(ACL_RSLT0, STAGDEI, sw->stag_dei); - } - - FIELD_GET_ACTION(ACL_RSLT0, CTAGVID, sw->ctag_vid); - - FIELD_GET_ACTION(ACL_RSLT1, TRANS_CVID_CHG, data); - if (data) - { - FAL_ACTION_FLG_SET(sw->action_flg, FAL_ACL_ACTION_REMARK_CTAG_VID); - } - - FIELD_GET_ACTION(ACL_RSLT1, CTAG_PRI_REMAP, data); - if (data) - { - FAL_ACTION_FLG_SET(sw->action_flg, FAL_ACL_ACTION_REMARK_CTAG_PRI); - FIELD_GET_ACTION(ACL_RSLT0, CTAGPRI, sw->ctag_pri); - } - - FIELD_GET_ACTION(ACL_RSLT1, CTAG_CFI_CHG, data); - if (data) - { - FAL_ACTION_FLG_SET(sw->action_flg, FAL_ACL_ACTION_REMARK_CTAG_CFI); - FIELD_GET_ACTION(ACL_RSLT0, CTAGCFI, sw->ctag_cfi); - } - - FIELD_GET_ACTION(ACL_RSLT1, LOOK_VID_CHG, data); - if (data) - { - FAL_ACTION_FLG_SET(sw->action_flg, FAL_ACL_ACTION_REMARK_LOOKUP_VID); - } - - FIELD_GET_ACTION(ACL_RSLT2, POLICER_EN, data); - if (data) - { - FAL_ACTION_FLG_SET(sw->action_flg, FAL_ACL_ACTION_POLICER_EN); - FIELD_GET_ACTION(ACL_RSLT2, POLICER_PTR, sw->policer_ptr); - } - - FIELD_GET_ACTION(ACL_RSLT1, ARP_PTR_EN, data); - if (data) - { - FIELD_GET_ACTION(ACL_RSLT1, WCMP_EN, data); - if (data) - { - FAL_ACTION_FLG_SET(sw->action_flg, FAL_ACL_ACTION_WCMP_EN); - FIELD_GET_ACTION(ACL_RSLT1, ARP_PTR, sw->wcmp_ptr); - } - else - { - FAL_ACTION_FLG_SET(sw->action_flg, FAL_ACL_ACTION_ARP_EN); - FIELD_GET_ACTION(ACL_RSLT1, ARP_PTR, sw->arp_ptr); - } - } - - FIELD_GET_ACTION(ACL_RSLT1, FORCE_L3_MODE, data); - if ((0 != data) && (3 != data)) - { - FAL_ACTION_FLG_SET(sw->action_flg, FAL_ACL_ACTION_POLICY_FORWARD_EN); - if (0x1 == data) - { - sw->policy_fwd = FAL_ACL_POLICY_SNAT; - } - else - { - sw->policy_fwd = FAL_ACL_POLICY_DNAT; - } - } - - FIELD_GET_ACTION(ACL_RSLT2, EG_BYPASS, data); - if (data) - { - FAL_ACTION_FLG_SET(sw->action_flg, FAL_ACL_ACTION_BYPASS_EGRESS_TRANS); - } - - FIELD_GET_ACTION(ACL_RSLT2, TRIGGER_INTR, data); - if (data) - { - FAL_ACTION_FLG_SET(sw->action_flg, FAL_ACL_ACTION_MATCH_TRIGGER_INTR); - } - - return SW_OK; -} - -sw_error_t -_isisc_acl_rule_sw_to_hw(a_uint32_t dev_id, fal_acl_rule_t * sw, - isisc_acl_rule_t * hw_rule_snap, a_uint32_t * idx) -{ - sw_error_t rv; - a_uint32_t tmp_idx, i, b_rule[7] = { 0 }; - parse_func_t ptr[7] = { NULL }; - a_bool_t b_care, b_mac, eh_mac; - - rv = _isisc_acl_action_parse(dev_id, sw, &(hw_rule_snap[*idx].filter)); - SW_RTN_ON_ERROR(rv); - - ptr[0] = _isisc_acl_rule_udf_parse; - _isisc_acl_rule_mac_preparse(sw, &b_mac, &eh_mac); - - /* ehmac rule must be parsed bofore mac rule. - it's important for reparse process */ - if (A_TRUE == eh_mac) - { - ptr[1] = _isisc_acl_rule_ehmac_parse; - } - - if (A_TRUE == b_mac) - { - ptr[2] = _isisc_acl_rule_bmac_parse; - } - - if ((A_FALSE == b_mac) && (A_FALSE == eh_mac)) - { - ptr[2] = _isisc_acl_rule_bmac_parse; - } - - if (FAL_ACL_RULE_MAC == sw->rule_type) - { - } - else if (FAL_ACL_RULE_IP4 == sw->rule_type) - { - ptr[3] = _isisc_acl_rule_ip4_parse; - } - else if (FAL_ACL_RULE_IP6 == sw->rule_type) - { - ptr[4] = _isisc_acl_rule_ip6r1_parse; - ptr[5] = _isisc_acl_rule_ip6r2_parse; - ptr[6] = _isisc_acl_rule_ip6r3_parse; - } - else if (FAL_ACL_RULE_UDF == sw->rule_type) - { - ptr[1] = NULL; - ptr[2] = NULL; - } - else - { - return SW_NOT_SUPPORTED; - } - - tmp_idx = *idx; - for (i = 0; i < 7; i++) - { - if (ptr[i]) - { - if (ISISC_HW_RULE_TMP_CNT <= tmp_idx) - { - return SW_NO_RESOURCE; - } - - rv = ptr[i] (sw, &(hw_rule_snap[tmp_idx].filter), &b_care); - SW_RTN_ON_ERROR(rv); - if (A_TRUE == b_care) - { - tmp_idx++; - b_rule[i] = 1; - } - } - } - - if (FAL_ACL_RULE_IP6 == sw->rule_type) - { - if ((!b_rule[4]) && (!b_rule[5]) && (!b_rule[6])) - { - tmp_idx++; - } - } - - if (FAL_ACL_RULE_IP4 == sw->rule_type) - { - if (!b_rule[3]) - { - tmp_idx++; - } - } - - if (tmp_idx == *idx) - { - /* set type start & end */ - SW_SET_REG_BY_FIELD(MAC_RUL_M4, RULE_VALID, FLT_STARTEND, - (hw_rule_snap[*idx].filter.msk[4])); - (*idx)++; - } - else - { - if (1 == (tmp_idx - *idx)) - { - if (FAL_ACL_COMBINED_START == sw->combined) - { - SW_SET_REG_BY_FIELD(MAC_RUL_M4, RULE_VALID, FLT_START, - (hw_rule_snap[*idx].filter.msk[4])); - } - else if (FAL_ACL_COMBINED_CONTINUE == sw->combined) - { - SW_SET_REG_BY_FIELD(MAC_RUL_M4, RULE_VALID, FLT_CONTINUE, - (hw_rule_snap[*idx].filter.msk[4])); - } - else if (FAL_ACL_COMBINED_END == sw->combined) - { - SW_SET_REG_BY_FIELD(MAC_RUL_M4, RULE_VALID, FLT_END, - (hw_rule_snap[*idx].filter.msk[4])); - } - else - { - SW_SET_REG_BY_FIELD(MAC_RUL_M4, RULE_VALID, FLT_STARTEND, - (hw_rule_snap[*idx].filter.msk[4])); - } - } - else - { - for (i = *idx; i < tmp_idx; i++) - { - if (i == *idx) - { - SW_SET_REG_BY_FIELD(MAC_RUL_M4, RULE_VALID, FLT_START, - (hw_rule_snap[i].filter.msk[4])); - } - else if (i == (tmp_idx - 1)) - { - SW_SET_REG_BY_FIELD(MAC_RUL_M4, RULE_VALID, FLT_END, - (hw_rule_snap[i].filter.msk[4])); - } - else - { - SW_SET_REG_BY_FIELD(MAC_RUL_M4, RULE_VALID, FLT_CONTINUE, - (hw_rule_snap[i].filter.msk[4])); - } - aos_mem_copy(&(hw_rule_snap[i].filter.act[0]), - &(hw_rule_snap[*idx].filter.act[0]), - sizeof (hw_rule_snap[*idx].filter.act)); - } - } - *idx = tmp_idx; - } - - return SW_OK; -} - -sw_error_t -_isisc_acl_rule_hw_to_sw(a_uint32_t dev_id, fal_acl_rule_t * sw, - isisc_acl_rule_t * hw_rule_snap, a_uint32_t idx, - a_uint32_t ent_nr) -{ - a_bool_t b_mac = A_FALSE, b_ip4 = A_FALSE, b_ip6 = A_FALSE; - sw_error_t rv; - a_uint32_t i, flt_typ; - hw_filter_t *hw; - - rv = _isisc_acl_rule_action_reparse(sw, &(hw_rule_snap[idx].filter)); - SW_RTN_ON_ERROR(rv); - - sw->rule_type = FAL_ACL_RULE_UDF; - for (i = 0; i < ent_nr; i++) - { - hw = &(hw_rule_snap[idx + i].filter); - FIELD_GET_MASK(MAC_RUL_M4, RULE_TYP, flt_typ); - - if (ISISC_UDF_FILTER == flt_typ) - { - rv = _isisc_acl_rule_udf_reparse(sw, hw); - SW_RTN_ON_ERROR(rv); - } - else if (ISISC_MAC_FILTER == flt_typ) - { - rv = _isisc_acl_rule_bmac_reparse(sw, hw); - SW_RTN_ON_ERROR(rv); - b_mac = A_TRUE; - } - else if (ISISC_EHMAC_FILTER == flt_typ) - { - rv = _isisc_acl_rule_ehmac_reparse(sw, hw); - SW_RTN_ON_ERROR(rv); - b_mac = A_TRUE; - } - else if (ISISC_IP4_FILTER == flt_typ) - { - rv = _isisc_acl_rule_ip4_reparse(sw, hw); - SW_RTN_ON_ERROR(rv); - b_ip4 = A_TRUE; - } - else if (ISISC_IP6R1_FILTER == flt_typ) - { - rv = _isisc_acl_rule_ip6r1_reparse(sw, hw); - SW_RTN_ON_ERROR(rv); - b_ip6 = A_TRUE; - } - else if (ISISC_IP6R2_FILTER == flt_typ) - { - rv = _isisc_acl_rule_ip6r2_reparse(sw, hw); - SW_RTN_ON_ERROR(rv); - b_ip6 = A_TRUE; - } - else if (ISISC_IP6R3_FILTER == flt_typ) - { - rv = _isisc_acl_rule_ip6r3_reparse(sw, hw); - SW_RTN_ON_ERROR(rv); - b_ip6 = A_TRUE; - } - else - { - /* ignore fill gap filters */ - } - } - - if (A_TRUE == b_mac) - { - sw->rule_type = FAL_ACL_RULE_MAC; - } - - if (A_TRUE == b_ip4) - { - sw->rule_type = FAL_ACL_RULE_IP4; - } - - if (A_TRUE == b_ip6) - { - sw->rule_type = FAL_ACL_RULE_IP6; - } - - return SW_OK; -} diff --git a/feeds/ipq807x/qca-ssdk/src/src/hsl/isisc/isisc_acl_prv.h b/feeds/ipq807x/qca-ssdk/src/src/hsl/isisc/isisc_acl_prv.h deleted file mode 100755 index cd5540aca..000000000 --- a/feeds/ipq807x/qca-ssdk/src/src/hsl/isisc/isisc_acl_prv.h +++ /dev/null @@ -1,126 +0,0 @@ -/* - * Copyright (c) 2012, The Linux Foundation. All rights reserved. - * Permission to use, copy, modify, and/or distribute this software for - * any purpose with or without fee is hereby granted, provided that the - * above copyright notice and this permission notice appear in all copies. - * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES - * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR - * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES - * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN - * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT - * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. - */ - - - -typedef struct -{ - a_uint8_t status; - a_uint8_t list_id; - a_uint8_t list_pri; - a_uint8_t rule_nr; - fal_pbmp_t bind_pts; -} isisc_acl_list_t; - - -typedef struct -{ - a_uint32_t vlu[5]; - a_uint32_t msk[5]; - a_uint32_t act[3]; -} hw_filter_t; - - -typedef struct -{ - a_uint8_t status; - a_uint8_t list_id; - a_uint8_t list_pri; - a_uint8_t rule_id; - hw_filter_t filter; - a_uint32_t src_flt_dis; /* src filter disabled */ -} isisc_acl_rule_t; - - -#define ENT_USED 0x1 -#define ENT_TMP 0x2 -#define ENT_DEACTIVE 0x4 - -#define FLT_START 0x0 -#define FLT_CONTINUE 0x1 -#define FLT_END 0x2 -#define FLT_STARTEND 0x3 - - -#define ISISC_MAC_FILTER 1 -#define ISISC_IP4_FILTER 2 -#define ISISC_IP6R1_FILTER 3 -#define ISISC_IP6R2_FILTER 4 -#define ISISC_IP6R3_FILTER 5 -#define ISISC_UDF_FILTER 6 -#define ISISC_EHMAC_FILTER 7 - - -#define ISISC_MAX_UDF_OFFSET 31 -#define ISISC_MAX_UDF_LENGTH 16 - - -#define ISISC_FILTER_VLU_OP 0x0 -#define ISISC_FILTER_MSK_OP 0x1 -#define ISISC_FILTER_ACT_OP 0x2 - - - -//#define ISISC_MAX_FILTER 8 -#define ISISC_MAX_FILTER 96 -#define ISISC_RULE_FUNC_ADDR 0x0400 -#define ISISC_HW_RULE_TMP_CNT (ISISC_MAX_FILTER + 4) - -#define ISISC_MAX_LIST_ID 255 -#define ISISC_MAX_LIST_PRI 255 - -#define ISISC_UDF_MAX_LENGTH 15 -#define ISISC_UDF_MAX_OFFSET 31 - -#define WIN_RULE_CTL0_ADDR 0x218 -#define WIN_RULE_CTL1_ADDR 0x234 - - -#define ISISC_FILTER_VLU_ADDR 0x58000 -#define ISISC_FILTER_MSK_ADDR 0x59000 -#define ISISC_FILTER_ACT_ADDR 0x5a000 - - -#define FIELD_SET(reg, field, val) \ - SW_REG_SET_BY_FIELD_U32(hw->vlu[reg], val, reg##_##field##_BOFFSET, \ - reg##_##field##_BLEN) - -#define FIELD_GET(reg, field, val) \ - SW_FIELD_GET_BY_REG_U32(hw->vlu[reg], val, reg##_##field##_BOFFSET, \ - reg##_##field##_BLEN) - -#define FIELD_SET_MASK(reg, field, val) \ - SW_REG_SET_BY_FIELD_U32(hw->msk[reg-5], val, reg##_##field##_BOFFSET, \ - reg##_##field##_BLEN) - -#define FIELD_GET_MASK(reg, field, val) \ - SW_FIELD_GET_BY_REG_U32(hw->msk[reg-5], val, reg##_##field##_BOFFSET, \ - reg##_##field##_BLEN) - -#define FIELD_SET_ACTION(reg, field, val) \ - SW_REG_SET_BY_FIELD_U32(hw->act[reg-10], val, reg##_##field##_BOFFSET, \ - reg##_##field##_BLEN) - -#define FIELD_GET_ACTION(reg, field, val) \ - SW_FIELD_GET_BY_REG_U32(hw->act[reg-10], val, reg##_##field##_BOFFSET, \ - reg##_##field##_BLEN) - -sw_error_t -_isisc_acl_rule_sw_to_hw(a_uint32_t dev_id, fal_acl_rule_t * sw, isisc_acl_rule_t * hw_filter_snap, a_uint32_t * idx); - - -sw_error_t -_isisc_acl_rule_hw_to_sw(a_uint32_t dev_id, fal_acl_rule_t * sw, isisc_acl_rule_t * hw_filter_snap, a_uint32_t idx, a_uint32_t ent_nr); - - diff --git a/feeds/ipq807x/qca-ssdk/src/src/hsl/isisc/isisc_cosmap.c b/feeds/ipq807x/qca-ssdk/src/src/hsl/isisc/isisc_cosmap.c deleted file mode 100755 index 49473d5ea..000000000 --- a/feeds/ipq807x/qca-ssdk/src/src/hsl/isisc/isisc_cosmap.c +++ /dev/null @@ -1,647 +0,0 @@ -/* - * Copyright (c) 2012, 2016, The Linux Foundation. All rights reserved. - * Permission to use, copy, modify, and/or distribute this software for - * any purpose with or without fee is hereby granted, provided that the - * above copyright notice and this permission notice appear in all copies. - * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES - * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR - * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES - * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN - * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT - * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. - */ - - -/** - * @defgroup isisc_cosmap ISISC_COSMAP - * @{ - */ -#include "sw.h" -#include "hsl.h" -#include "hsl_dev.h" -#include "hsl_port_prop.h" -#include "isisc_cosmap.h" -#include "isisc_reg.h" - -#define ISISC_MAX_DSCP 63 -#define ISISC_MAX_UP 7 -#define ISISC_MAX_PRI 7 -#define ISISC_MAX_DP 1 -#define ISISC_MAX_QUEUE 3 -#define ISISC_MAX_EH_QUEUE 5 - -#define ISISC_DSCP_TO_PRI 0 -#define ISISC_DSCP_TO_DP 1 -#define ISISC_UP_TO_PRI 2 -#define ISISC_UP_TO_DP 3 - -#define ISISC_EGRESS_REAMRK_ADDR 0x5ae00 -#define ISISC_EGRESS_REAMRK_NUM 16 - -#ifndef IN_COSMAP_MINI -static sw_error_t -_isisc_cosmap_dscp_to_pri_dp_set(a_uint32_t dev_id, a_uint32_t mode, - a_uint32_t dscp, a_uint32_t val) -{ - sw_error_t rv; - a_uint32_t index, data = 0; - - if (ISISC_MAX_DSCP < dscp) - { - return SW_BAD_PARAM; - } - - index = dscp >> 3; - HSL_REG_ENTRY_GET(rv, dev_id, DSCP_TO_PRI, index, (a_uint8_t *) (&data), - sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - - if (ISISC_DSCP_TO_PRI == mode) - { - if (ISISC_MAX_PRI < val) - { - return SW_BAD_PARAM; - } - - data &= (~(0x7 << ((dscp & 0x7) << 2))); - data |= (val << ((dscp & 0x7) << 2)); - } - else - { - if (ISISC_MAX_DP < val) - { - return SW_BAD_PARAM; - } - - data &= (~(0x1 << (((dscp & 0x7) << 2) + 3))); - data |= (val << (((dscp & 0x7) << 2) + 3)); - } - - HSL_REG_ENTRY_SET(rv, dev_id, DSCP_TO_PRI, index, (a_uint8_t *) (&data), - sizeof (a_uint32_t)); - return rv; -} - -static sw_error_t -_isisc_cosmap_dscp_to_pri_dp_get(a_uint32_t dev_id, a_uint32_t mode, - a_uint32_t dscp, a_uint32_t * val) -{ - sw_error_t rv; - a_uint32_t index, data = 0; - - if (ISISC_MAX_DSCP < dscp) - { - return SW_BAD_PARAM; - } - - index = dscp >> 3; - HSL_REG_ENTRY_GET(rv, dev_id, DSCP_TO_PRI, index, (a_uint8_t *) (&data), - sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - - data = (data >> ((dscp & 0x7) << 2)) & 0xf; - if (ISISC_DSCP_TO_PRI == mode) - { - *val = data & 0x7; - } - else - { - *val = (data & 0x8) >> 3; - } - - return SW_OK; -} - -static sw_error_t -_isisc_cosmap_up_to_pri_dp_set(a_uint32_t dev_id, a_uint32_t mode, a_uint32_t up, - a_uint32_t val) -{ - sw_error_t rv; - a_uint32_t data = 0; - - if (ISISC_MAX_UP < up) - { - return SW_BAD_PARAM; - } - - HSL_REG_ENTRY_GET(rv, dev_id, UP_TO_PRI, 0, (a_uint8_t *) (&data), - sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - - if (ISISC_UP_TO_PRI == mode) - { - if (ISISC_MAX_PRI < val) - { - return SW_BAD_PARAM; - } - - data &= (~(0x7 << (up << 2))); - data |= (val << (up << 2)); - } - else - { - if (ISISC_MAX_DP < val) - { - return SW_BAD_PARAM; - } - - data &= (~(0x1 << ((up << 2) + 3))); - data |= (val << ((up << 2) + 3)); - } - - HSL_REG_ENTRY_SET(rv, dev_id, UP_TO_PRI, 0, (a_uint8_t *) (&data), - sizeof (a_uint32_t)); - return rv; -} - -static sw_error_t -_isisc_cosmap_up_to_pri_dp_get(a_uint32_t dev_id, a_uint32_t mode, a_uint32_t up, - a_uint32_t * val) -{ - sw_error_t rv; - a_uint32_t data = 0; - - if (ISISC_MAX_UP < up) - { - return SW_BAD_PARAM; - } - - HSL_REG_ENTRY_GET(rv, dev_id, UP_TO_PRI, 0, (a_uint8_t *) (&data), - sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - - data = (data >> (up << 2)) & 0xf; - - if (ISISC_UP_TO_PRI == mode) - { - *val = (data & 0x7); - } - else - { - *val = (data & 0x8) >> 3; - } - - return SW_OK; -} -#endif - -static sw_error_t -_isisc_cosmap_pri_to_queue_set(a_uint32_t dev_id, a_uint32_t pri, - a_uint32_t queue) -{ - sw_error_t rv; - a_uint32_t data = 0; - - if ((ISISC_MAX_PRI < pri) || (ISISC_MAX_QUEUE < queue)) - { - return SW_BAD_PARAM; - } - - HSL_REG_ENTRY_GET(rv, dev_id, PRI_TO_QUEUE, 0, (a_uint8_t *) (&data), - sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - - data &= (~(0x3 << (pri << 2))); - data |= (queue << (pri << 2)); - - HSL_REG_ENTRY_SET(rv, dev_id, PRI_TO_QUEUE, 0, (a_uint8_t *) (&data), - sizeof (a_uint32_t)); - return rv; -} - -static sw_error_t -_isisc_cosmap_pri_to_ehqueue_set(a_uint32_t dev_id, a_uint32_t pri, - a_uint32_t queue) -{ - sw_error_t rv; - a_uint32_t data = 0; - - if ((ISISC_MAX_PRI < pri) || (ISISC_MAX_EH_QUEUE < queue)) - { - return SW_BAD_PARAM; - } - - HSL_REG_ENTRY_GET(rv, dev_id, PRI_TO_EHQUEUE, 0, (a_uint8_t *) (&data), - sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - - data &= (~(0x7 << (pri << 2))); - data |= (queue << (pri << 2)); - - HSL_REG_ENTRY_SET(rv, dev_id, PRI_TO_EHQUEUE, 0, (a_uint8_t *) (&data), - sizeof (a_uint32_t)); - return rv; -} - -#ifndef IN_COSMAP_MINI -static sw_error_t -_isisc_cosmap_pri_to_queue_get(a_uint32_t dev_id, a_uint32_t pri, - a_uint32_t * queue) -{ - sw_error_t rv; - a_uint32_t data = 0; - - if (ISISC_MAX_PRI < pri) - { - return SW_BAD_PARAM; - } - - HSL_REG_ENTRY_GET(rv, dev_id, PRI_TO_QUEUE, 0, (a_uint8_t *) (&data), - sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - - *queue = (data >> (pri << 2)) & 0x3; - return SW_OK; -} - -static sw_error_t -_isisc_cosmap_pri_to_ehqueue_get(a_uint32_t dev_id, a_uint32_t pri, - a_uint32_t * queue) -{ - sw_error_t rv; - a_uint32_t data = 0; - - if (ISISC_MAX_PRI < pri) - { - return SW_BAD_PARAM; - } - - HSL_REG_ENTRY_GET(rv, dev_id, PRI_TO_EHQUEUE, 0, (a_uint8_t *) (&data), - sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - - *queue = (data >> (pri << 2)) & 0x7; - return SW_OK; -} - -static sw_error_t -_isisc_cosmap_egress_remark_set(a_uint32_t dev_id, a_uint32_t tbl_id, - fal_egress_remark_table_t * tbl) -{ - sw_error_t rv; - a_uint32_t data, addr; - - if (ISISC_EGRESS_REAMRK_NUM <= tbl_id) - { - return SW_BAD_PARAM; - } - - data = (tbl->y_up & 0x7) - | ((tbl->g_up & 0x7) << 4) - | ((tbl->y_dscp & 0x3f) << 8) - | ((tbl->g_dscp & 0x3f) << 16) - | ((tbl->remark_dscp & 0x1) << 23) - | ((tbl->remark_up & 0x1) << 22); - - addr = ISISC_EGRESS_REAMRK_ADDR + (tbl_id << 4); - HSL_REG_ENTRY_GEN_SET(rv, dev_id, addr, sizeof (a_uint32_t), - (a_uint8_t *) (&data), sizeof (a_uint32_t)); - return rv; -} - -static sw_error_t -_isisc_cosmap_egress_remark_get(a_uint32_t dev_id, a_uint32_t tbl_id, - fal_egress_remark_table_t * tbl) -{ - sw_error_t rv; - a_uint32_t data = 0, addr; - - if (ISISC_EGRESS_REAMRK_NUM <= tbl_id) - { - return SW_BAD_PARAM; - } - - aos_mem_zero(tbl, sizeof (fal_egress_remark_table_t)); - - addr = ISISC_EGRESS_REAMRK_ADDR + (tbl_id << 4); - HSL_REG_ENTRY_GEN_GET(rv, dev_id, addr, sizeof (a_uint32_t), - (a_uint8_t *) (&data), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - - if (data & (0x1 << 23)) - { - tbl->remark_dscp = A_TRUE; - tbl->y_dscp = (data >> 8) & 0x3f; - tbl->g_dscp = (data >> 16) & 0x3f; - } - - if (data & (0x1 << 22)) - { - tbl->remark_up = A_TRUE; - tbl->y_up = data & 0x7; - tbl->g_up = (data >> 4) & 0x7; - } - - return SW_OK; -} - -/** - * @brief Set dscp to internal priority mapping on one particular device. - * @param[in] dev_id device id - * @param[in] dscp dscp - * @param[in] pri internal priority - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -isisc_cosmap_dscp_to_pri_set(a_uint32_t dev_id, a_uint32_t dscp, a_uint32_t pri) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _isisc_cosmap_dscp_to_pri_dp_set(dev_id, ISISC_DSCP_TO_PRI, dscp, pri); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Get dscp to internal priority mapping on one particular device. - * @param[in] dev_id device id - * @param[in] dscp dscp - * @param[out] pri internal priority - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -isisc_cosmap_dscp_to_pri_get(a_uint32_t dev_id, a_uint32_t dscp, - a_uint32_t * pri) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _isisc_cosmap_dscp_to_pri_dp_get(dev_id, ISISC_DSCP_TO_PRI, dscp, pri); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Set dscp to internal drop precedence mapping on one particular device. - * @param[in] dev_id device id - * @param[in] dscp dscp - * @param[in] dp internal drop precedence - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -isisc_cosmap_dscp_to_dp_set(a_uint32_t dev_id, a_uint32_t dscp, a_uint32_t dp) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _isisc_cosmap_dscp_to_pri_dp_set(dev_id, ISISC_DSCP_TO_DP, dscp, dp); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Get dscp to internal drop precedence mapping on one particular device. - * @param[in] dev_id device id - * @param[in] dscp dscp - * @param[out] dp internal drop precedence - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -isisc_cosmap_dscp_to_dp_get(a_uint32_t dev_id, a_uint32_t dscp, a_uint32_t * dp) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _isisc_cosmap_dscp_to_pri_dp_get(dev_id, ISISC_DSCP_TO_DP, dscp, dp); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Set dot1p to internal priority mapping on one particular device. - * @param[in] dev_id device id - * @param[in] up dot1p - * @param[in] pri internal priority - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -isisc_cosmap_up_to_pri_set(a_uint32_t dev_id, a_uint32_t up, a_uint32_t pri) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _isisc_cosmap_up_to_pri_dp_set(dev_id, ISISC_UP_TO_PRI, up, pri); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Get dot1p to internal priority mapping on one particular device. - * @param[in] dev_id device id - * @param[in] up dot1p - * @param[out] pri internal priority - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -isisc_cosmap_up_to_pri_get(a_uint32_t dev_id, a_uint32_t up, a_uint32_t * pri) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _isisc_cosmap_up_to_pri_dp_get(dev_id, ISISC_UP_TO_PRI, up, pri); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Set dot1p to internal drop precedence mapping on one particular device. - * @param[in] dev_id device id - * @param[in] up dot1p - * @param[in] dp internal drop precedence - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -isisc_cosmap_up_to_dp_set(a_uint32_t dev_id, a_uint32_t up, a_uint32_t dp) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _isisc_cosmap_up_to_pri_dp_set(dev_id, ISISC_UP_TO_DP, up, dp); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Get dot1p to internal drop precedence mapping on one particular device. - * @param[in] dev_id device id - * @param[in] up dot1p - * @param[in] dp internal drop precedence - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -isisc_cosmap_up_to_dp_get(a_uint32_t dev_id, a_uint32_t up, a_uint32_t * dp) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _isisc_cosmap_up_to_pri_dp_get(dev_id, ISISC_UP_TO_DP, up, dp); - HSL_API_UNLOCK; - return rv; -} -#endif - -/** - * @brief Set internal priority to queue mapping on one particular device. - * @details Comments: - * This function is for port 1/2/3/4 which have four egress queues - * @param[in] dev_id device id - * @param[in] pri internal priority - * @param[in] queue queue id - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -isisc_cosmap_pri_to_queue_set(a_uint32_t dev_id, a_uint32_t pri, - a_uint32_t queue) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _isisc_cosmap_pri_to_queue_set(dev_id, pri, queue); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Set internal priority to queue mapping on one particular device. - * @details Comments: - * This function is for port 0/5/6 which have six egress queues - * @param[in] dev_id device id - * @param[in] pri internal priority - * @param[in] queue queue id - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -isisc_cosmap_pri_to_ehqueue_set(a_uint32_t dev_id, a_uint32_t pri, - a_uint32_t queue) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _isisc_cosmap_pri_to_ehqueue_set(dev_id, pri, queue); - HSL_API_UNLOCK; - return rv; -} - -#ifndef IN_COSMAP_MINI -/** - * @brief Get internal priority to queue mapping on one particular device. - * @details Comments: - * This function is for port 1/2/3/4 which have four egress queues - * @param[in] dev_id device id - * @param[in] pri internal priority - * @param[out] queue queue id - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -isisc_cosmap_pri_to_queue_get(a_uint32_t dev_id, a_uint32_t pri, - a_uint32_t * queue) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _isisc_cosmap_pri_to_queue_get(dev_id, pri, queue); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Get internal priority to queue mapping on one particular device. - * @details Comments: - * This function is for port 0/5/6 which have six egress queues - * @param[in] dev_id device id - * @param[in] pri internal priority - * @param[in] queue queue id - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -isisc_cosmap_pri_to_ehqueue_get(a_uint32_t dev_id, a_uint32_t pri, - a_uint32_t * queue) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _isisc_cosmap_pri_to_ehqueue_get(dev_id, pri, queue); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Set egress queue based CoS remap table on one particular device. - * @param[in] dev_id device id - * @param[in] tbl_id CoS remap table id - * @param[in] tbl CoS remap table - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -isisc_cosmap_egress_remark_set(a_uint32_t dev_id, a_uint32_t tbl_id, - fal_egress_remark_table_t * tbl) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _isisc_cosmap_egress_remark_set(dev_id, tbl_id, tbl); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Get egress queue based CoS remap table on one particular device. - * @param[in] dev_id device id - * @param[in] tbl_id CoS remap table id - * @param[out] tbl CoS remap table - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -isisc_cosmap_egress_remark_get(a_uint32_t dev_id, a_uint32_t tbl_id, - fal_egress_remark_table_t * tbl) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _isisc_cosmap_egress_remark_get(dev_id, tbl_id, tbl); - HSL_API_UNLOCK; - return rv; -} -#endif - -sw_error_t -isisc_cosmap_init(a_uint32_t dev_id) -{ - HSL_DEV_ID_CHECK(dev_id); - -#ifndef HSL_STANDALONG - { - hsl_api_t *p_api; - - SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id)); - -#ifndef IN_COSMAP_MINI - p_api->cosmap_dscp_to_pri_set = isisc_cosmap_dscp_to_pri_set; - p_api->cosmap_dscp_to_pri_get = isisc_cosmap_dscp_to_pri_get; - p_api->cosmap_dscp_to_dp_set = isisc_cosmap_dscp_to_dp_set; - p_api->cosmap_dscp_to_dp_get = isisc_cosmap_dscp_to_dp_get; - p_api->cosmap_up_to_pri_set = isisc_cosmap_up_to_pri_set; - p_api->cosmap_up_to_pri_get = isisc_cosmap_up_to_pri_get; - p_api->cosmap_up_to_dp_set = isisc_cosmap_up_to_dp_set; - p_api->cosmap_up_to_dp_get = isisc_cosmap_up_to_dp_get; -#endif - p_api->cosmap_pri_to_queue_set = isisc_cosmap_pri_to_queue_set; - p_api->cosmap_pri_to_ehqueue_set = isisc_cosmap_pri_to_ehqueue_set; -#ifndef IN_COSMAP_MINI - p_api->cosmap_pri_to_queue_get = isisc_cosmap_pri_to_queue_get; - p_api->cosmap_pri_to_ehqueue_get = isisc_cosmap_pri_to_ehqueue_get; - p_api->cosmap_egress_remark_set = isisc_cosmap_egress_remark_set; - p_api->cosmap_egress_remark_get = isisc_cosmap_egress_remark_get; -#endif - } -#endif - - return SW_OK; -} - -/** - * @} - */ - diff --git a/feeds/ipq807x/qca-ssdk/src/src/hsl/isisc/isisc_fdb.c b/feeds/ipq807x/qca-ssdk/src/src/hsl/isisc/isisc_fdb.c deleted file mode 100755 index 6a47bee0e..000000000 --- a/feeds/ipq807x/qca-ssdk/src/src/hsl/isisc/isisc_fdb.c +++ /dev/null @@ -1,2294 +0,0 @@ -/* - * Copyright (c) 2012, 2016, The Linux Foundation. All rights reserved. - * Permission to use, copy, modify, and/or distribute this software for - * any purpose with or without fee is hereby granted, provided that the - * above copyright notice and this permission notice appear in all copies. - * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES - * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR - * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES - * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN - * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT - * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. - */ - - -/** - * @defgroup isisc_fdb ISISC_FDB - * @{ - */ -#include "sw.h" -#include "hsl.h" -#include "hsl_dev.h" -#include "hsl_port_prop.h" -#include "isisc_fdb.h" -#include "isisc_reg.h" -#include "isisc_fdb_prv.h" - -#ifndef IN_FDB_MINI -static sw_error_t -_isisc_wl_feature_check(a_uint32_t dev_id) -{ - sw_error_t rv; - a_uint32_t entry = 0; - - HSL_REG_FIELD_GET(rv, dev_id, MASK_CTL, 0, DEVICE_ID, - (a_uint8_t *) (&entry), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - - if (S17C_DEVICE_ID == entry) - { - return SW_OK; - } - else - { - return SW_NOT_SUPPORTED; - } -} -#endif - -static a_bool_t -_isisc_fdb_is_zeroaddr(fal_mac_addr_t addr) -{ - a_uint32_t i; - - for (i = 0; i < 6; i++) - { - if (addr.uc[i]) - { - return A_FALSE; - } - } - - return A_TRUE; -} - -static void -_isisc_fdb_fill_addr(fal_mac_addr_t addr, a_uint32_t * reg0, a_uint32_t * reg1) -{ - SW_SET_REG_BY_FIELD(ADDR_TABLE_FUNC1, AT_ADDR_BYTE0, addr.uc[0], *reg1); - SW_SET_REG_BY_FIELD(ADDR_TABLE_FUNC1, AT_ADDR_BYTE1, addr.uc[1], *reg1); - - SW_SET_REG_BY_FIELD(ADDR_TABLE_FUNC0, AT_ADDR_BYTE2, addr.uc[2], *reg0); - SW_SET_REG_BY_FIELD(ADDR_TABLE_FUNC0, AT_ADDR_BYTE3, addr.uc[3], *reg0); - SW_SET_REG_BY_FIELD(ADDR_TABLE_FUNC0, AT_ADDR_BYTE4, addr.uc[4], *reg0); - SW_SET_REG_BY_FIELD(ADDR_TABLE_FUNC0, AT_ADDR_BYTE5, addr.uc[5], *reg0); - - return; -} - -#ifndef IN_FDB_MINI -static sw_error_t -_isisc_atu_sw_to_hw(a_uint32_t dev_id, const fal_fdb_entry_t * entry, - a_uint32_t reg[]) -{ - a_uint32_t port; - sw_error_t rv; - - if (A_TRUE == entry->white_list_en) - { - rv = _isisc_wl_feature_check(dev_id); - SW_RTN_ON_ERROR(rv); - - SW_SET_REG_BY_FIELD(ADDR_TABLE_FUNC2, WL_EN, 1, reg[2]); - } - - if (FAL_SVL_FID == entry->fid) - { - SW_SET_REG_BY_FIELD(ADDR_TABLE_FUNC2, AT_VID, 0, reg[2]); - SW_SET_REG_BY_FIELD(ADDR_TABLE_FUNC1, AT_SVL_EN, 1, reg[1]); - } - else if (ISISC_MAX_FID >= entry->fid) - { - SW_SET_REG_BY_FIELD(ADDR_TABLE_FUNC2, AT_VID, (entry->fid), reg[2]); - SW_SET_REG_BY_FIELD(ADDR_TABLE_FUNC1, AT_SVL_EN, 0, reg[1]); - } - else - { - return SW_BAD_PARAM; - } - - if (A_FALSE == entry->portmap_en) - { - if (A_TRUE != - hsl_port_prop_check(dev_id, entry->port.id, HSL_PP_INCL_CPU)) - { - return SW_BAD_PARAM; - } - - port = 0x1UL << entry->port.id; - } - else - { - if (A_FALSE == - hsl_mports_prop_check(dev_id, entry->port.map, HSL_PP_INCL_CPU)) - { - return SW_BAD_PARAM; - } - - port = entry->port.map; - } - SW_SET_REG_BY_FIELD(ADDR_TABLE_FUNC1, DES_PORT, port, reg[1]); - - if (FAL_MAC_CPY_TO_CPU == entry->dacmd) - { - SW_SET_REG_BY_FIELD(ADDR_TABLE_FUNC2, COPY_TO_CPU, 1, reg[2]); - } - else if (FAL_MAC_RDT_TO_CPU == entry->dacmd) - { - SW_SET_REG_BY_FIELD(ADDR_TABLE_FUNC2, REDRCT_TO_CPU, 1, reg[2]); - } - else if (FAL_MAC_FRWRD != entry->dacmd) - { - return SW_NOT_SUPPORTED; - } - - if (A_TRUE == entry->leaky_en) - { - SW_SET_REG_BY_FIELD(ADDR_TABLE_FUNC2, LEAKY_EN, 1, reg[2]); - } - else - { - SW_SET_REG_BY_FIELD(ADDR_TABLE_FUNC2, LEAKY_EN, 0, reg[2]); - } - - if (A_TRUE == entry->static_en) - { - SW_SET_REG_BY_FIELD(ADDR_TABLE_FUNC2, AT_STATUS, 15, reg[2]); - } - else - { - SW_SET_REG_BY_FIELD(ADDR_TABLE_FUNC2, AT_STATUS, 7, reg[2]); - } - - if (FAL_MAC_DROP == entry->sacmd) - { - SW_SET_REG_BY_FIELD(ADDR_TABLE_FUNC1, SA_DROP_EN, 1, reg[1]); - } - else if (FAL_MAC_FRWRD != entry->sacmd) - { - return SW_NOT_SUPPORTED; - } - - if (A_TRUE == entry->mirror_en) - { - SW_SET_REG_BY_FIELD(ADDR_TABLE_FUNC1, MIRROR_EN, 1, reg[1]); - } - - if (A_TRUE == entry->cross_pt_state) - { - SW_SET_REG_BY_FIELD(ADDR_TABLE_FUNC1, CROSS_PT, 1, reg[1]); - } - else - { - SW_SET_REG_BY_FIELD(ADDR_TABLE_FUNC1, CROSS_PT, 0, reg[1]); - } - - if (A_TRUE == entry->da_pri_en) - { - SW_SET_REG_BY_FIELD(ADDR_TABLE_FUNC1, AT_PRI_EN, 1, reg[1]); - SW_SET_REG_BY_FIELD(ADDR_TABLE_FUNC1, AT_PRI, (entry->da_queue & 0x7), - reg[1]); - } - else - { - SW_SET_REG_BY_FIELD(ADDR_TABLE_FUNC1, AT_PRI_EN, 0, reg[1]); - } - - _isisc_fdb_fill_addr(entry->addr, ®[0], ®[1]); - return SW_OK; -} -#endif - -static void -_isisc_atu_hw_to_sw(const a_uint32_t reg[], fal_fdb_entry_t * entry) -{ - a_uint32_t i, data; - - aos_mem_zero(entry, sizeof (fal_fdb_entry_t)); - - SW_GET_FIELD_BY_REG(ADDR_TABLE_FUNC1, AT_SVL_EN, data, reg[1]); - if (data) - { - entry->fid = FAL_SVL_FID; - } - else - { - SW_GET_FIELD_BY_REG(ADDR_TABLE_FUNC2, AT_VID, data, reg[2]); - entry->fid = data; - } - - entry->dacmd = FAL_MAC_FRWRD; - SW_GET_FIELD_BY_REG(ADDR_TABLE_FUNC2, COPY_TO_CPU, data, reg[2]); - if (1 == data) - { - entry->dacmd = FAL_MAC_CPY_TO_CPU; - } - - SW_GET_FIELD_BY_REG(ADDR_TABLE_FUNC2, REDRCT_TO_CPU, data, reg[2]); - if (1 == data) - { - entry->dacmd = FAL_MAC_RDT_TO_CPU; - } - - entry->sacmd = FAL_MAC_FRWRD; - SW_GET_FIELD_BY_REG(ADDR_TABLE_FUNC1, SA_DROP_EN, data, reg[1]); - if (1 == data) - { - entry->sacmd = FAL_MAC_DROP; - } - - entry->leaky_en = A_FALSE; - SW_GET_FIELD_BY_REG(ADDR_TABLE_FUNC2, LEAKY_EN, data, reg[2]); - if (1 == data) - { - entry->leaky_en = A_TRUE; - } - - entry->static_en = A_FALSE; - SW_GET_FIELD_BY_REG(ADDR_TABLE_FUNC2, AT_STATUS, data, reg[2]); - if (0xf == data) - { - entry->static_en = A_TRUE; - } - - entry->mirror_en = A_FALSE; - SW_GET_FIELD_BY_REG(ADDR_TABLE_FUNC1, MIRROR_EN, data, reg[1]); - if (1 == data) - { - entry->mirror_en = A_TRUE; - } - - entry->da_pri_en = A_FALSE; - SW_GET_FIELD_BY_REG(ADDR_TABLE_FUNC1, AT_PRI_EN, data, reg[1]); - if (1 == data) - { - SW_GET_FIELD_BY_REG(ADDR_TABLE_FUNC1, AT_PRI, data, reg[1]); - entry->da_pri_en = A_TRUE; - entry->da_queue = data & 0x7; - } - - entry->cross_pt_state = A_FALSE; - SW_GET_FIELD_BY_REG(ADDR_TABLE_FUNC1, CROSS_PT, data, reg[1]); - if (1 == data) - { - entry->cross_pt_state = A_TRUE; - } - - SW_GET_FIELD_BY_REG(ADDR_TABLE_FUNC1, DES_PORT, data, reg[1]); - entry->portmap_en = A_TRUE; - entry->port.map = data; - - for (i = 2; i < 6; i++) - { - entry->addr.uc[i] = (reg[0] >> ((5 - i) << 3)) & 0xff; - } - - for (i = 0; i < 2; i++) - { - entry->addr.uc[i] = (reg[1] >> ((1 - i) << 3)) & 0xff; - } - - entry->white_list_en = A_FALSE; - SW_GET_FIELD_BY_REG(ADDR_TABLE_FUNC2, WL_EN, data, reg[2]); - if (1 == data) - { - entry->white_list_en = A_TRUE; - } - - return; -} - -static sw_error_t -_isisc_atu_down_to_hw(a_uint32_t dev_id, a_uint32_t reg[]) -{ - sw_error_t rv; - - HSL_REG_ENTRY_SET(rv, dev_id, ADDR_TABLE_FUNC0, 0, - (a_uint8_t *) (®[0]), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - - HSL_REG_ENTRY_SET(rv, dev_id, ADDR_TABLE_FUNC1, 0, - (a_uint8_t *) (®[1]), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - - HSL_REG_ENTRY_SET(rv, dev_id, ADDR_TABLE_FUNC2, 0, - (a_uint8_t *) (®[2]), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - - HSL_REG_ENTRY_SET(rv, dev_id, ADDR_TABLE_FUNC3, 0, - (a_uint8_t *) (®[3]), sizeof (a_uint32_t)); - return rv; -} - -static sw_error_t -_isisc_atu_up_to_sw(a_uint32_t dev_id, a_uint32_t reg[]) -{ - sw_error_t rv; - - HSL_REG_ENTRY_GET(rv, dev_id, ADDR_TABLE_FUNC0, 0, - (a_uint8_t *) (®[0]), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - - HSL_REG_ENTRY_GET(rv, dev_id, ADDR_TABLE_FUNC1, 0, - (a_uint8_t *) (®[1]), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - - HSL_REG_ENTRY_GET(rv, dev_id, ADDR_TABLE_FUNC2, 0, - (a_uint8_t *) (®[2]), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - - HSL_REG_ENTRY_GET(rv, dev_id, ADDR_TABLE_FUNC3, 0, - (a_uint8_t *) (®[3]), sizeof (a_uint32_t)); - return rv; -} - -static sw_error_t -_isisc_fdb_commit(a_uint32_t dev_id, a_uint32_t op) -{ - sw_error_t rv; - a_uint32_t busy = 1; - a_uint32_t full_vio; - a_uint32_t i = 2000; - a_uint32_t entry = 0; - a_uint32_t hwop = op; - - while (busy && --i) - { - HSL_REG_ENTRY_GET(rv, dev_id, ADDR_TABLE_FUNC3, 0, - (a_uint8_t *) (&entry), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - SW_GET_FIELD_BY_REG(ADDR_TABLE_FUNC3, AT_BUSY, busy, entry); - } - - if (0 == i) - { - return SW_BUSY; - } - - if (ARL_FIRST_ENTRY == op) - { - hwop = ARL_NEXT_ENTRY; - } - - SW_SET_REG_BY_FIELD(ADDR_TABLE_FUNC3, AT_BUSY, 1, entry); - - if (ARL_FLUSH_PORT_AND_STATIC == hwop) - { - hwop = ARL_FLUSH_PORT_UNICAST; - SW_SET_REG_BY_FIELD(ADDR_TABLE_FUNC3, FLUSH_ST_EN, 1, entry); - } - - if (ARL_FLUSH_PORT_NO_STATIC == hwop) - { - hwop = ARL_FLUSH_PORT_UNICAST; - SW_SET_REG_BY_FIELD(ADDR_TABLE_FUNC3, FLUSH_ST_EN, 0, entry); - } - - SW_SET_REG_BY_FIELD(ADDR_TABLE_FUNC3, AT_FUNC, hwop, entry); - - HSL_REG_ENTRY_SET(rv, dev_id, ADDR_TABLE_FUNC3, 0, - (a_uint8_t *) (&entry), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - - busy = 1; - i = 2000; - while (busy && --i) - { - HSL_REG_ENTRY_GET(rv, dev_id, ADDR_TABLE_FUNC3, 0, - (a_uint8_t *) (&entry), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - SW_GET_FIELD_BY_REG(ADDR_TABLE_FUNC3, AT_BUSY, busy, entry); - } - - if (0 == i) - { - return SW_FAIL; - } - - SW_GET_FIELD_BY_REG(ADDR_TABLE_FUNC3, AT_FULL_VIO, full_vio, entry); - - if (full_vio) - { - /* must clear AT_FULL_VOI bit */ - entry = 0x1000; - HSL_REG_ENTRY_SET(rv, dev_id, ADDR_TABLE_FUNC3, 0, - (a_uint8_t *) (&entry), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - - if (ARL_LOAD_ENTRY == hwop) - { - return SW_FULL; - } - else if ((ARL_PURGE_ENTRY == hwop) - || (ARL_FLUSH_PORT_UNICAST == hwop)) - { - return SW_NOT_FOUND; - } - else - { - return SW_FAIL; - } - } - - return SW_OK; -} - -static sw_error_t -_isisc_fdb_get(a_uint32_t dev_id, fal_fdb_op_t * option, fal_fdb_entry_t * entry, - a_uint32_t hwop) -{ - sw_error_t rv; - a_uint32_t i, port = 0, status, reg[4] = { 0 }; - - HSL_DEV_ID_CHECK(dev_id); - - if (A_TRUE == option->port_en) - { - SW_SET_REG_BY_FIELD(ADDR_TABLE_FUNC3, AT_PORT_EN, 1, reg[3]); - if (A_FALSE == entry->portmap_en) - { - if (A_TRUE != - hsl_port_prop_check(dev_id, entry->port.id, HSL_PP_INCL_CPU)) - { - return SW_BAD_PARAM; - } - port = entry->port.id; - } - else - { - if (A_FALSE == - hsl_mports_prop_check(dev_id, entry->port.map, - HSL_PP_INCL_CPU)) - { - return SW_BAD_PARAM; - } - - status = 0; - for (i = 0; i < SW_MAX_NR_PORT; i++) - { - if ((entry->port.map) & (0x1UL << i)) - { - if (status) - { - return SW_BAD_PARAM; - } - port = i; - status = 1; - } - } - } - SW_SET_REG_BY_FIELD(ADDR_TABLE_FUNC3, AT_PORT_NUM, port, reg[3]); - } - - if (A_TRUE == option->fid_en) - { - SW_SET_REG_BY_FIELD(ADDR_TABLE_FUNC3, AT_VID_EN, 1, reg[3]); - } - - if (A_TRUE == option->multicast_en) - { - SW_SET_REG_BY_FIELD(ADDR_TABLE_FUNC3, AT_MULTI_EN, 1, reg[3]); - } - - if (FAL_SVL_FID == entry->fid) - { - SW_SET_REG_BY_FIELD(ADDR_TABLE_FUNC2, AT_VID, 0, reg[2]); - SW_SET_REG_BY_FIELD(ADDR_TABLE_FUNC1, AT_SVL_EN, 1, reg[1]); - } - else if (ISISC_MAX_FID >= entry->fid) - { - SW_SET_REG_BY_FIELD(ADDR_TABLE_FUNC2, AT_VID, entry->fid, reg[2]); - SW_SET_REG_BY_FIELD(ADDR_TABLE_FUNC1, AT_SVL_EN, 0, reg[1]); - } - else - { - return SW_BAD_PARAM; - } - - if (ARL_FIRST_ENTRY != hwop) - { - SW_SET_REG_BY_FIELD(ADDR_TABLE_FUNC2, AT_STATUS, 0xf, reg[2]); - } - - _isisc_fdb_fill_addr(entry->addr, ®[0], ®[1]); - - rv = _isisc_atu_down_to_hw(dev_id, reg); - SW_RTN_ON_ERROR(rv); - - rv = _isisc_fdb_commit(dev_id, hwop); - SW_RTN_ON_ERROR(rv); - - rv = _isisc_atu_up_to_sw(dev_id, reg); - SW_RTN_ON_ERROR(rv); - - _isisc_atu_hw_to_sw(reg, entry); - - SW_GET_FIELD_BY_REG(ADDR_TABLE_FUNC2, AT_STATUS, status, reg[2]); - if ((A_TRUE == _isisc_fdb_is_zeroaddr(entry->addr)) - && (0 == status)) - { - if (ARL_NEXT_ENTRY == hwop) - { - return SW_NO_MORE; - } - else - { - return SW_NOT_FOUND; - } - } - else - { - return SW_OK; - } - - return SW_OK; -} - -#ifndef IN_FDB_MINI -static sw_error_t -_isisc_fdb_add(a_uint32_t dev_id, const fal_fdb_entry_t * entry) -{ - sw_error_t rv; - a_uint32_t reg[4] = { 0 }; - - HSL_DEV_ID_CHECK(dev_id); - - rv = _isisc_atu_sw_to_hw(dev_id, entry, reg); - SW_RTN_ON_ERROR(rv); - - rv = _isisc_atu_down_to_hw(dev_id, reg); - SW_RTN_ON_ERROR(rv); - - rv = _isisc_fdb_commit(dev_id, ARL_LOAD_ENTRY); - return rv; -} -#endif - -static sw_error_t -_isisc_fdb_del_all(a_uint32_t dev_id, a_uint32_t flag) -{ - sw_error_t rv; - - HSL_DEV_ID_CHECK(dev_id); - - if (FAL_FDB_DEL_STATIC & flag) - { - rv = _isisc_fdb_commit(dev_id, ARL_FLUSH_ALL); - } - else - { - rv = _isisc_fdb_commit(dev_id, ARL_FLUSH_ALL_UNLOCK); - } - - return rv; -} -#ifndef IN_FDB_MINI -static sw_error_t -_isisc_fdb_del_by_port(a_uint32_t dev_id, fal_port_t port_id, a_uint32_t flag) -{ - sw_error_t rv; - a_uint32_t reg = 0; - - HSL_DEV_ID_CHECK(dev_id); - - if (A_FALSE == hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU)) - { - return SW_BAD_PARAM; - } - - SW_SET_REG_BY_FIELD(ADDR_TABLE_FUNC3, AT_PORT_NUM, port_id, reg); - - HSL_REG_ENTRY_SET(rv, dev_id, ADDR_TABLE_FUNC3, 0, (a_uint8_t *) (®), - sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - - if (FAL_FDB_DEL_STATIC & flag) - { - rv = _isisc_fdb_commit(dev_id, ARL_FLUSH_PORT_AND_STATIC); - } - else - { - rv = _isisc_fdb_commit(dev_id, ARL_FLUSH_PORT_NO_STATIC); - } - - return rv; -} - -static sw_error_t -_isisc_fdb_del_by_mac(a_uint32_t dev_id, const fal_fdb_entry_t * entry) -{ - sw_error_t rv; - a_uint32_t reg0 = 0, reg1 = 0, reg2 = 0; - - HSL_DEV_ID_CHECK(dev_id); - - _isisc_fdb_fill_addr(entry->addr, ®0, ®1); - - if (FAL_SVL_FID == entry->fid) - { - SW_SET_REG_BY_FIELD(ADDR_TABLE_FUNC2, AT_VID, 0, reg2); - SW_SET_REG_BY_FIELD(ADDR_TABLE_FUNC1, AT_SVL_EN, 1, reg1); - } - else if (ISISC_MAX_FID >= entry->fid) - { - SW_SET_REG_BY_FIELD(ADDR_TABLE_FUNC2, AT_VID, (entry->fid), reg2); - SW_SET_REG_BY_FIELD(ADDR_TABLE_FUNC1, AT_SVL_EN, 0, reg1); - } - else - { - return SW_BAD_PARAM; - } - - HSL_REG_ENTRY_SET(rv, dev_id, ADDR_TABLE_FUNC2, 0, (a_uint8_t *) (®2), - sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - - HSL_REG_ENTRY_SET(rv, dev_id, ADDR_TABLE_FUNC1, 0, (a_uint8_t *) (®1), - sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - - HSL_REG_ENTRY_SET(rv, dev_id, ADDR_TABLE_FUNC0, 0, (a_uint8_t *) (®0), - sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - - rv = _isisc_fdb_commit(dev_id, ARL_PURGE_ENTRY); - return rv; -} - -static sw_error_t -_isisc_fdb_find(a_uint32_t dev_id, fal_fdb_entry_t * entry) -{ - sw_error_t rv; - fal_fdb_op_t option; - - aos_mem_zero(&option, sizeof (fal_fdb_op_t)); - rv = _isisc_fdb_get(dev_id, &option, entry, ARL_FIND_ENTRY); - return rv; -} -#endif -static sw_error_t -_isisc_fdb_extend_next(a_uint32_t dev_id, fal_fdb_op_t * option, - fal_fdb_entry_t * entry) -{ - sw_error_t rv; - - rv = _isisc_fdb_get(dev_id, option, entry, ARL_NEXT_ENTRY); - return rv; -} - -static sw_error_t -_isisc_fdb_extend_first(a_uint32_t dev_id, fal_fdb_op_t * option, - fal_fdb_entry_t * entry) -{ - sw_error_t rv; - - rv = _isisc_fdb_get(dev_id, option, entry, ARL_FIRST_ENTRY); - return rv; -} -#ifndef IN_FDB_MINI -static sw_error_t -_isisc_fdb_transfer(a_uint32_t dev_id, fal_port_t old_port, fal_port_t new_port, - a_uint32_t fid, fal_fdb_op_t * option) -{ - sw_error_t rv; - a_uint32_t reg[4] = { 0 }; - - if (A_TRUE == option->port_en) - { - return SW_NOT_SUPPORTED; - } - - if (A_TRUE == option->fid_en) - { - SW_SET_REG_BY_FIELD(ADDR_TABLE_FUNC3, AT_VID_EN, 1, reg[3]); - } - - if (A_TRUE == option->multicast_en) - { - SW_SET_REG_BY_FIELD(ADDR_TABLE_FUNC3, AT_MULTI_EN, 1, reg[3]); - } - - if (FAL_SVL_FID == fid) - { - SW_SET_REG_BY_FIELD(ADDR_TABLE_FUNC2, AT_VID, 0, reg[2]); - SW_SET_REG_BY_FIELD(ADDR_TABLE_FUNC1, AT_SVL_EN, 1, reg[1]); - } - else if (ISISC_MAX_FID >= fid) - { - SW_SET_REG_BY_FIELD(ADDR_TABLE_FUNC2, AT_VID, fid, reg[2]); - SW_SET_REG_BY_FIELD(ADDR_TABLE_FUNC1, AT_SVL_EN, 0, reg[1]); - } - else - { - return SW_BAD_PARAM; - } - - SW_SET_REG_BY_FIELD(ADDR_TABLE_FUNC3, AT_PORT_NUM, old_port, reg[3]); - SW_SET_REG_BY_FIELD(ADDR_TABLE_FUNC3, NEW_PORT_NUM, new_port, reg[3]); - - rv = _isisc_atu_down_to_hw(dev_id, reg); - SW_RTN_ON_ERROR(rv); - - rv = _isisc_fdb_commit(dev_id, ARL_TRANSFER_ENTRY); - return rv; -} -#endif -static sw_error_t -_isisc_fdb_port_learn_set(a_uint32_t dev_id, fal_port_t port_id, a_bool_t enable) -{ - a_uint32_t data; - sw_error_t rv; - - HSL_DEV_ID_CHECK(dev_id); - - if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU)) - { - return SW_BAD_PARAM; - } - - if (A_TRUE == enable) - { - data = 1; - } - else if (A_FALSE == enable) - { - data = 0; - } - else - { - return SW_BAD_PARAM; - } - - HSL_REG_FIELD_SET(rv, dev_id, PORT_LOOKUP_CTL, port_id, LEARN_EN, - (a_uint8_t *) (&data), sizeof (a_uint32_t)); - return rv; -} -#ifndef IN_FDB_MINI -static sw_error_t -_isisc_fdb_port_learn_get(a_uint32_t dev_id, fal_port_t port_id, - a_bool_t * enable) -{ - a_uint32_t data = 0; - sw_error_t rv; - - HSL_DEV_ID_CHECK(dev_id); - - if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU)) - { - return SW_BAD_PARAM; - } - - HSL_REG_FIELD_GET(rv, dev_id, PORT_LOOKUP_CTL, port_id, LEARN_EN, - (a_uint8_t *) (&data), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - - if (1 == data) - { - *enable = A_TRUE; - } - else - { - *enable = A_FALSE; - } - - return SW_OK; -} - -static sw_error_t -_isisc_fdb_age_ctrl_set(a_uint32_t dev_id, a_bool_t enable) -{ - a_uint32_t data; - sw_error_t rv; - - HSL_DEV_ID_CHECK(dev_id); - - if (A_TRUE == enable) - { - data = 1; - } - else if (A_FALSE == enable) - { - data = 0; - } - else - { - return SW_BAD_PARAM; - } - - HSL_REG_FIELD_SET(rv, dev_id, ADDR_TABLE_CTL, 0, AGE_EN, - (a_uint8_t *) (&data), sizeof (a_uint32_t)); - return rv; -} - -static sw_error_t -_isisc_fdb_vlan_ivl_svl_set(a_uint32_t dev_id, fal_fdb_smode smode) -{ - a_uint32_t data; - sw_error_t rv; - - HSL_DEV_ID_CHECK(dev_id); - - data = smode; - - HSL_REG_FIELD_SET(rv, dev_id, ADDR_TABLE_CTL, 0, ARL_INI_EN, - (a_uint8_t *) (&data), sizeof (a_uint32_t)); - return rv; -} - -static sw_error_t -_isisc_fdb_vlan_ivl_svl_get(a_uint32_t dev_id, fal_fdb_smode* smode) -{ - a_uint32_t data = 0; - sw_error_t rv; - - HSL_DEV_ID_CHECK(dev_id); - - HSL_REG_FIELD_GET(rv, dev_id, ADDR_TABLE_CTL, 0, ARL_INI_EN, - (a_uint8_t *) (&data), sizeof (a_uint32_t)); - - *smode = data; - - return rv; -} - - - -static sw_error_t -_isisc_fdb_age_ctrl_get(a_uint32_t dev_id, a_bool_t * enable) -{ - a_uint32_t data = 0; - sw_error_t rv; - - HSL_DEV_ID_CHECK(dev_id); - - HSL_REG_FIELD_GET(rv, dev_id, ADDR_TABLE_CTL, 0, AGE_EN, - (a_uint8_t *) (&data), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - - if (1 == data) - { - *enable = A_TRUE; - } - else - { - *enable = A_FALSE; - } - - return SW_OK; -} - -static sw_error_t -_isisc_fdb_age_time_set(a_uint32_t dev_id, a_uint32_t * time) -{ - a_uint32_t data; - sw_error_t rv; - - HSL_DEV_ID_CHECK(dev_id); - - if ((65535 * 7 < *time) || (7 > *time)) - { - return SW_BAD_PARAM; - } - data = *time / 7; - *time = data * 7; - HSL_REG_FIELD_SET(rv, dev_id, ADDR_TABLE_CTL, 0, AGE_TIME, - (a_uint8_t *) (&data), sizeof (a_uint32_t)); - return rv; -} - -static sw_error_t -_isisc_fdb_age_time_get(a_uint32_t dev_id, a_uint32_t * time) -{ - a_uint32_t data = 0; - sw_error_t rv; - - HSL_DEV_ID_CHECK(dev_id); - - HSL_REG_FIELD_GET(rv, dev_id, ADDR_TABLE_CTL, 0, AGE_TIME, - (a_uint8_t *) (&data), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - - *time = data * 7; - return SW_OK; -} - -static sw_error_t -_isisc_port_fdb_learn_limit_set(a_uint32_t dev_id, fal_port_t port_id, - a_bool_t enable, a_uint32_t cnt) -{ - sw_error_t rv; - a_uint32_t reg = 0; - - HSL_DEV_ID_CHECK(dev_id); - - if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU)) - { - return SW_BAD_PARAM; - } - - HSL_REG_ENTRY_GET(rv, dev_id, PORT_LEARN_LIMIT_CTL, port_id, - (a_uint8_t *) (®), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - - if (A_TRUE == enable) - { - if (ISISC_MAX_PORT_LEARN_LIMIT_CNT < cnt) - { - return SW_BAD_PARAM; - } - SW_SET_REG_BY_FIELD(PORT_LEARN_LIMIT_CTL, SA_LEARN_LIMIT_EN, 1, reg); - SW_SET_REG_BY_FIELD(PORT_LEARN_LIMIT_CTL, SA_LEARN_CNT, cnt, reg); - } - else if (A_FALSE == enable) - { - SW_SET_REG_BY_FIELD(PORT_LEARN_LIMIT_CTL, SA_LEARN_LIMIT_EN, 0, reg); - SW_SET_REG_BY_FIELD(PORT_LEARN_LIMIT_CTL, SA_LEARN_CNT, 0, reg); - } - else - { - return SW_BAD_PARAM; - } - - HSL_REG_ENTRY_SET(rv, dev_id, PORT_LEARN_LIMIT_CTL, port_id, - (a_uint8_t *) (®), sizeof (a_uint32_t)); - return rv; -} - -static sw_error_t -_isisc_port_fdb_learn_limit_get(a_uint32_t dev_id, fal_port_t port_id, - a_bool_t * enable, a_uint32_t * cnt) -{ - sw_error_t rv; - a_uint32_t data, reg = 0; - - HSL_DEV_ID_CHECK(dev_id); - - if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU)) - { - return SW_BAD_PARAM; - } - - HSL_REG_ENTRY_GET(rv, dev_id, PORT_LEARN_LIMIT_CTL, port_id, - (a_uint8_t *) (®), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - - SW_GET_FIELD_BY_REG(PORT_LEARN_LIMIT_CTL, SA_LEARN_LIMIT_EN, data, reg); - if (data) - { - SW_GET_FIELD_BY_REG(PORT_LEARN_LIMIT_CTL, SA_LEARN_CNT, data, reg); - *enable = A_TRUE; - *cnt = data; - } - else - { - *enable = A_FALSE; - *cnt = 0; - } - - return SW_OK; -} - -static sw_error_t -_isisc_port_fdb_learn_exceed_cmd_set(a_uint32_t dev_id, fal_port_t port_id, - fal_fwd_cmd_t cmd) -{ - sw_error_t rv; - a_uint32_t data = 0; - - HSL_DEV_ID_CHECK(dev_id); - - if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU)) - { - return SW_BAD_PARAM; - } - - if (FAL_MAC_DROP == cmd) - { - data = 1; - } - else if (FAL_MAC_RDT_TO_CPU == cmd) - { - data = 0; - } - else - { - return SW_NOT_SUPPORTED; - } - - HSL_REG_FIELD_SET(rv, dev_id, PORT_LEARN_LIMIT_CTL, port_id, - SA_LEARN_LIMIT_DROP_EN, (a_uint8_t *) (&data), - sizeof (a_uint32_t)); - return rv; -} - -static sw_error_t -_isisc_port_fdb_learn_exceed_cmd_get(a_uint32_t dev_id, fal_port_t port_id, - fal_fwd_cmd_t * cmd) -{ - sw_error_t rv; - a_uint32_t data = 0; - - HSL_DEV_ID_CHECK(dev_id); - - if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU)) - { - return SW_BAD_PARAM; - } - - HSL_REG_FIELD_GET(rv, dev_id, PORT_LEARN_LIMIT_CTL, port_id, - SA_LEARN_LIMIT_DROP_EN, (a_uint8_t *) (&data), - sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - - if (data) - { - *cmd = FAL_MAC_DROP; - } - else - { - *cmd = FAL_MAC_RDT_TO_CPU; - } - - return SW_OK; -} - -static sw_error_t -_isisc_fdb_learn_limit_set(a_uint32_t dev_id, a_bool_t enable, a_uint32_t cnt) -{ - sw_error_t rv; - a_uint32_t reg = 0; - - HSL_REG_ENTRY_GET(rv, dev_id, GLOBAL_LEARN_LIMIT_CTL, 0, - (a_uint8_t *) (®), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - - if (A_TRUE == enable) - { - if (ISISC_MAX_LEARN_LIMIT_CNT < cnt) - { - return SW_BAD_PARAM; - } - SW_SET_REG_BY_FIELD(GLOBAL_LEARN_LIMIT_CTL, GOL_SA_LEARN_LIMIT_EN, 1, - reg); - SW_SET_REG_BY_FIELD(GLOBAL_LEARN_LIMIT_CTL, GOL_SA_LEARN_CNT, cnt, reg); - } - else if (A_FALSE == enable) - { - SW_SET_REG_BY_FIELD(GLOBAL_LEARN_LIMIT_CTL, GOL_SA_LEARN_LIMIT_EN, 0, - reg); - SW_SET_REG_BY_FIELD(GLOBAL_LEARN_LIMIT_CTL, GOL_SA_LEARN_CNT, 0, reg); - } - else - { - return SW_BAD_PARAM; - } - - HSL_REG_ENTRY_SET(rv, dev_id, GLOBAL_LEARN_LIMIT_CTL, 0, - (a_uint8_t *) (®), sizeof (a_uint32_t)); - return rv; -} - -static sw_error_t -_isisc_fdb_learn_limit_get(a_uint32_t dev_id, a_bool_t * enable, - a_uint32_t * cnt) -{ - sw_error_t rv; - a_uint32_t data, reg = 0; - - HSL_REG_ENTRY_GET(rv, dev_id, GLOBAL_LEARN_LIMIT_CTL, 0, - (a_uint8_t *) (®), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - - SW_GET_FIELD_BY_REG(GLOBAL_LEARN_LIMIT_CTL, GOL_SA_LEARN_LIMIT_EN, data, - reg); - if (data) - { - SW_GET_FIELD_BY_REG(GLOBAL_LEARN_LIMIT_CTL, GOL_SA_LEARN_CNT, data, - reg); - *enable = A_TRUE; - *cnt = data; - } - else - { - *enable = A_FALSE; - *cnt = 0; - } - - return SW_OK; -} - -static sw_error_t -_isisc_fdb_learn_exceed_cmd_set(a_uint32_t dev_id, fal_fwd_cmd_t cmd) -{ - sw_error_t rv; - a_uint32_t data = 0; - - HSL_DEV_ID_CHECK(dev_id); - - if (FAL_MAC_DROP == cmd) - { - data = 1; - } - else if (FAL_MAC_RDT_TO_CPU == cmd) - { - data = 0; - } - else - { - return SW_NOT_SUPPORTED; - } - - HSL_REG_FIELD_SET(rv, dev_id, GLOBAL_LEARN_LIMIT_CTL, 0, - GOL_SA_LEARN_LIMIT_DROP_EN, (a_uint8_t *) (&data), - sizeof (a_uint32_t)); - return rv; -} - -static sw_error_t -_isisc_fdb_learn_exceed_cmd_get(a_uint32_t dev_id, fal_fwd_cmd_t * cmd) -{ - sw_error_t rv; - a_uint32_t data = 0; - - HSL_DEV_ID_CHECK(dev_id); - - HSL_REG_FIELD_GET(rv, dev_id, GLOBAL_LEARN_LIMIT_CTL, 0, - GOL_SA_LEARN_LIMIT_DROP_EN, (a_uint8_t *) (&data), - sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - - if (data) - { - *cmd = FAL_MAC_DROP; - } - else - { - *cmd = FAL_MAC_RDT_TO_CPU; - } - - return SW_OK; -} - -#define ISISC_RESV_ADDR_NUM 32 -#define RESV_ADDR_TBL0_ADDR 0x3c000 -#define RESV_ADDR_TBL1_ADDR 0x3c004 -#define RESV_ADDR_TBL2_ADDR 0x3c008 - -static void -_isisc_resv_addr_parse(const a_uint32_t reg[], fal_mac_addr_t * addr) -{ - a_uint32_t i; - - for (i = 2; i < 6; i++) - { - addr->uc[i] = (reg[0] >> ((5 - i) << 3)) & 0xff; - } - - for (i = 0; i < 2; i++) - { - addr->uc[i] = (reg[1] >> ((1 - i) << 3)) & 0xff; - } -} - -static sw_error_t -_isisc_resv_atu_sw_to_hw(a_uint32_t dev_id, fal_fdb_entry_t * entry, - a_uint32_t reg[]) -{ - a_uint32_t port; - - if (A_FALSE == entry->portmap_en) - { - if (A_TRUE != - hsl_port_prop_check(dev_id, entry->port.id, HSL_PP_INCL_CPU)) - { - return SW_BAD_PARAM; - } - port = 0x1UL << entry->port.id; - } - else - { - if (A_FALSE == - hsl_mports_prop_check(dev_id, entry->port.map, HSL_PP_INCL_CPU)) - { - return SW_BAD_PARAM; - } - port = entry->port.map; - } - SW_SET_REG_BY_FIELD(RESV_ADDR_TBL1, RESV_DES_PORT, port, reg[1]); - - if (FAL_MAC_CPY_TO_CPU == entry->dacmd) - { - SW_SET_REG_BY_FIELD(RESV_ADDR_TBL1, RESV_COPY_TO_CPU, 1, reg[1]); - } - else if (FAL_MAC_RDT_TO_CPU == entry->dacmd) - { - SW_SET_REG_BY_FIELD(RESV_ADDR_TBL1, RESV_REDRCT_TO_CPU, 1, reg[1]); - } - else if (FAL_MAC_FRWRD != entry->dacmd) - { - return SW_NOT_SUPPORTED; - } - - if (FAL_MAC_FRWRD != entry->sacmd) - { - return SW_NOT_SUPPORTED; - } - - if (A_TRUE == entry->leaky_en) - { - SW_SET_REG_BY_FIELD(RESV_ADDR_TBL1, RESV_LEAKY_EN, 1, reg[1]); - } - else - { - SW_SET_REG_BY_FIELD(RESV_ADDR_TBL1, RESV_LEAKY_EN, 0, reg[1]); - } - - if (A_TRUE != entry->static_en) - { - return SW_NOT_SUPPORTED; - } - SW_SET_REG_BY_FIELD(RESV_ADDR_TBL2, RESV_STATUS, 1, reg[2]); - - if (A_TRUE == entry->mirror_en) - { - SW_SET_REG_BY_FIELD(RESV_ADDR_TBL1, RESV_MIRROR_EN, 1, reg[1]); - } - - if (A_TRUE == entry->cross_pt_state) - { - SW_SET_REG_BY_FIELD(RESV_ADDR_TBL1, RESV_CROSS_PT, 1, reg[1]); - } - - if (A_TRUE == entry->da_pri_en) - { - SW_SET_REG_BY_FIELD(RESV_ADDR_TBL1, RESV_PRI_EN, 1, reg[1]); - SW_SET_REG_BY_FIELD(RESV_ADDR_TBL1, RESV_PRI, (entry->da_queue & 0x7), - reg[1]); - } - - _isisc_fdb_fill_addr(entry->addr, ®[0], ®[1]); - return SW_OK; -} - -static void -_isisc_resv_atu_hw_to_sw(const a_uint32_t reg[], fal_fdb_entry_t * entry) -{ - a_uint32_t data; - - aos_mem_zero(entry, sizeof (fal_fdb_entry_t)); - - entry->fid = FAL_SVL_FID; - - entry->dacmd = FAL_MAC_FRWRD; - SW_GET_FIELD_BY_REG(RESV_ADDR_TBL1, RESV_COPY_TO_CPU, data, reg[1]); - if (1 == data) - { - entry->dacmd = FAL_MAC_CPY_TO_CPU; - } - - SW_GET_FIELD_BY_REG(RESV_ADDR_TBL1, RESV_REDRCT_TO_CPU, data, reg[1]); - if (1 == data) - { - entry->dacmd = FAL_MAC_RDT_TO_CPU; - } - - entry->sacmd = FAL_MAC_FRWRD; - - entry->leaky_en = A_FALSE; - SW_GET_FIELD_BY_REG(RESV_ADDR_TBL1, RESV_LEAKY_EN, data, reg[1]); - if (1 == data) - { - entry->leaky_en = A_TRUE; - } - - entry->static_en = A_TRUE; - - entry->mirror_en = A_FALSE; - SW_GET_FIELD_BY_REG(RESV_ADDR_TBL1, RESV_MIRROR_EN, data, reg[1]); - if (1 == data) - { - entry->mirror_en = A_TRUE; - } - - entry->da_pri_en = A_FALSE; - SW_GET_FIELD_BY_REG(RESV_ADDR_TBL1, RESV_PRI_EN, data, reg[1]); - if (1 == data) - { - SW_GET_FIELD_BY_REG(RESV_ADDR_TBL1, RESV_PRI, data, reg[1]); - entry->da_pri_en = A_TRUE; - entry->da_queue = data & 0x7; - } - - entry->cross_pt_state = A_FALSE; - SW_GET_FIELD_BY_REG(RESV_ADDR_TBL1, RESV_CROSS_PT, data, reg[1]); - if (1 == data) - { - entry->cross_pt_state = A_TRUE; - } - - SW_GET_FIELD_BY_REG(RESV_ADDR_TBL1, RESV_DES_PORT, data, reg[1]); - entry->portmap_en = A_TRUE; - entry->port.map = data; - - _isisc_resv_addr_parse(reg, &(entry->addr)); - return; -} - -static sw_error_t -_isisc_fdb_resv_commit(a_uint32_t dev_id, fal_fdb_entry_t * entry, a_uint32_t op, - a_uint32_t * empty) -{ - a_uint32_t index, addr, data, tbl[3] = { 0 }; - sw_error_t rv; - fal_mac_addr_t mac_tmp; - - *empty = ISISC_RESV_ADDR_NUM; - for (index = 0; index < ISISC_RESV_ADDR_NUM; index++) - { - addr = RESV_ADDR_TBL2_ADDR + (index << 4); - HSL_REG_ENTRY_GEN_GET(rv, dev_id, addr, sizeof (a_uint32_t), - (a_uint8_t *) (&(tbl[2])), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - - SW_GET_FIELD_BY_REG(RESV_ADDR_TBL2, RESV_STATUS, data, tbl[2]); - if (data) - { - addr = RESV_ADDR_TBL0_ADDR + (index << 4); - HSL_REG_ENTRY_GEN_GET(rv, dev_id, addr, sizeof (a_uint32_t), - (a_uint8_t *) (&(tbl[0])), - sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - - addr = RESV_ADDR_TBL1_ADDR + (index << 4); - HSL_REG_ENTRY_GEN_GET(rv, dev_id, addr, sizeof (a_uint32_t), - (a_uint8_t *) (&(tbl[1])), - sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - - _isisc_resv_addr_parse(tbl, &mac_tmp); - if (!aos_mem_cmp - ((void *) &(entry->addr), (void *) &mac_tmp, - sizeof (fal_mac_addr_t))) - { - if (ARL_PURGE_ENTRY == op) - { - addr = RESV_ADDR_TBL2_ADDR + (index << 4); - tbl[2] = 0; - HSL_REG_ENTRY_GEN_SET(rv, dev_id, addr, sizeof (a_uint32_t), - (a_uint8_t *) (&(tbl[2])), - sizeof (a_uint32_t)); - return rv; - } - else if (ARL_LOAD_ENTRY == op) - { - return SW_ALREADY_EXIST; - } - else if (ARL_FIND_ENTRY == op) - { - _isisc_resv_atu_hw_to_sw(tbl, entry); - return SW_OK; - } - } - } - else - { - *empty = index; - } - } - - return SW_NOT_FOUND; -} - -static sw_error_t -_isisc_fdb_resv_add(a_uint32_t dev_id, fal_fdb_entry_t * entry) -{ - sw_error_t rv; - a_uint32_t i, empty, addr, tbl[3] = { 0 }; - - rv = _isisc_resv_atu_sw_to_hw(dev_id, entry, tbl); - SW_RTN_ON_ERROR(rv); - - rv = _isisc_fdb_resv_commit(dev_id, entry, ARL_LOAD_ENTRY, &empty); - if (SW_ALREADY_EXIST == rv) - { - return rv; - } - - if (ISISC_RESV_ADDR_NUM == empty) - { - return SW_NO_RESOURCE; - } - - for (i = 0; i < 3; i++) - { - addr = RESV_ADDR_TBL0_ADDR + (empty << 4) + (i << 2); - HSL_REG_ENTRY_GEN_SET(rv, dev_id, addr, sizeof (a_uint32_t), - (a_uint8_t *) (&(tbl[i])), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - } - - return SW_OK; -} - -static sw_error_t -_isisc_fdb_resv_del(a_uint32_t dev_id, fal_fdb_entry_t * entry) -{ - sw_error_t rv; - a_uint32_t empty; - - rv = _isisc_fdb_resv_commit(dev_id, entry, ARL_PURGE_ENTRY, &empty); - return rv; -} - -static sw_error_t -_isisc_fdb_resv_find(a_uint32_t dev_id, fal_fdb_entry_t * entry) -{ - sw_error_t rv; - a_uint32_t empty; - - rv = _isisc_fdb_resv_commit(dev_id, entry, ARL_FIND_ENTRY, &empty); - return rv; -} - -static sw_error_t -_isisc_fdb_resv_iterate(a_uint32_t dev_id, a_uint32_t * iterator, - fal_fdb_entry_t * entry) -{ - a_uint32_t index, addr, data, tbl[3] = { 0 }; - sw_error_t rv; - - if ((NULL == iterator) || (NULL == entry)) - { - return SW_BAD_PTR; - } - - if (ISISC_RESV_ADDR_NUM < *iterator) - { - return SW_BAD_PARAM; - } - - for (index = *iterator; index < ISISC_RESV_ADDR_NUM; index++) - { - addr = RESV_ADDR_TBL2_ADDR + (index << 4); - HSL_REG_ENTRY_GEN_GET(rv, dev_id, addr, sizeof (a_uint32_t), - (a_uint8_t *) (&(tbl[2])), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - - SW_GET_FIELD_BY_REG(RESV_ADDR_TBL2, RESV_STATUS, data, tbl[2]); - if (data) - { - addr = RESV_ADDR_TBL0_ADDR + (index << 4); - HSL_REG_ENTRY_GEN_GET(rv, dev_id, addr, sizeof (a_uint32_t), - (a_uint8_t *) (&(tbl[0])), - sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - - addr = RESV_ADDR_TBL1_ADDR + (index << 4); - HSL_REG_ENTRY_GEN_GET(rv, dev_id, addr, sizeof (a_uint32_t), - (a_uint8_t *) (&(tbl[1])), - sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - - _isisc_resv_atu_hw_to_sw(tbl, entry); - break; - } - } - - if (ISISC_RESV_ADDR_NUM == index) - { - return SW_NO_MORE; - } - - *iterator = index + 1; - return SW_OK; -} - -static sw_error_t -_isisc_fdb_port_learn_static_set(a_uint32_t dev_id, fal_port_t port_id, - a_bool_t enable) -{ - a_uint32_t data; - sw_error_t rv; - - HSL_DEV_ID_CHECK(dev_id); - - if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU)) - { - return SW_BAD_PARAM; - } - - if (A_TRUE == enable) - { - data = 0xf; - } - else if (A_FALSE == enable) - { - data = 0x7; - } - else - { - return SW_BAD_PARAM; - } - - HSL_REG_FIELD_SET(rv, dev_id, PORT_LEARN_LIMIT_CTL, port_id, - SA_LEARN_STATUS, (a_uint8_t *) (&data), - sizeof (a_uint32_t)); - return rv; -} - -static sw_error_t -_isisc_fdb_port_learn_static_get(a_uint32_t dev_id, fal_port_t port_id, - a_bool_t * enable) -{ - a_uint32_t data = 0; - sw_error_t rv; - - HSL_DEV_ID_CHECK(dev_id); - - if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU)) - { - return SW_BAD_PARAM; - } - - HSL_REG_FIELD_GET(rv, dev_id, PORT_LEARN_LIMIT_CTL, port_id, - SA_LEARN_STATUS, (a_uint8_t *) (&data), - sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - - if (0xf == data) - { - *enable = A_TRUE; - } - else - { - *enable = A_FALSE; - } - - return SW_OK; -} - -static sw_error_t -_isisc_fdb_port_update(a_uint32_t dev_id, a_uint32_t fid, fal_mac_addr_t * addr, fal_port_t port_id, a_uint32_t op) -{ - sw_error_t rv; - fal_fdb_entry_t entry; - fal_fdb_op_t option; - a_uint32_t reg, port; - - HSL_DEV_ID_CHECK(dev_id); - - if (FAL_SVL_FID < fid) - { - return SW_BAD_PARAM; - } - - if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU)) - { - return SW_BAD_PARAM; - } - - aos_mem_zero(&option, sizeof(fal_fdb_op_t)); - aos_mem_copy(&(entry.addr), addr, sizeof(fal_mac_addr_t)); - entry.fid = fid & 0xffff; - rv = _isisc_fdb_get(dev_id, &option, &entry, ARL_FIND_ENTRY); - SW_RTN_ON_ERROR(rv); - - HSL_REG_ENTRY_GET(rv, dev_id, ADDR_TABLE_FUNC1, 0, - (a_uint8_t *) (®), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - - SW_GET_FIELD_BY_REG(ADDR_TABLE_FUNC1, DES_PORT, port, reg); - if (op) - { - port |= (0x1 << port_id); - } - else - { - port &= (~(0x1 << port_id)); - } - SW_SET_REG_BY_FIELD(ADDR_TABLE_FUNC1, DES_PORT, port, reg); - HSL_REG_ENTRY_SET(rv, dev_id, ADDR_TABLE_FUNC1, 0, - (a_uint8_t *) (®), sizeof (a_uint32_t)); - - rv = _isisc_fdb_commit(dev_id, ARL_LOAD_ENTRY); - return rv; -} - -sw_error_t -inter_isisc_fdb_flush(a_uint32_t dev_id, a_uint32_t flag) -{ - if (FAL_FDB_DEL_STATIC & flag) - { - return _isisc_fdb_commit(dev_id, ARL_FLUSH_ALL); - } - else - { - return _isisc_fdb_commit(dev_id, ARL_FLUSH_ALL_UNLOCK); - } -} - -/** - * @brief Add a Fdb entry - * @param[in] dev_id device id - * @param[in] entry fdb entry - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -isisc_fdb_add(a_uint32_t dev_id, const fal_fdb_entry_t * entry) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _isisc_fdb_add(dev_id, entry); - HSL_API_UNLOCK; - return rv; -} -#endif -/** - * @brief Delete all Fdb entries - * @details Comments: - * If set FAL_FDB_DEL_STATIC bit in flag which means delete all fdb - * entries otherwise only delete dynamic entries. - * @param[in] dev_id device id - * @param[in] flag delete operation option - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -isisc_fdb_del_all(a_uint32_t dev_id, a_uint32_t flag) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _isisc_fdb_del_all(dev_id, flag); - HSL_API_UNLOCK; - return rv; -} -#ifndef IN_FDB_MINI -/** - * @brief Delete Fdb entries on a particular port - * @details Comments: - * If set FAL_FDB_DEL_STATIC bit in flag which means delete all fdb - * entries otherwise only delete dynamic entries. - * @param[in] dev_id device id - * @param[in] port_id port id - * @param[in] flag delete operation option - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -isisc_fdb_del_by_port(a_uint32_t dev_id, fal_port_t port_id, a_uint32_t flag) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _isisc_fdb_del_by_port(dev_id, port_id, flag); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Delete a particular Fdb entry through mac address - * @details Comments: - * Only addr field in entry is meaning. For IVL learning vid or fid field - * also is meaning. - * @param[in] dev_id device id - * @param[in] entry fdb entry - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -isisc_fdb_del_by_mac(a_uint32_t dev_id, const fal_fdb_entry_t * entry) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _isisc_fdb_del_by_mac(dev_id, entry); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Find a particular Fdb entry from device through mac address. - * @details Comments: - For input parameter only addr field in entry is meaning. - * @param[in] dev_id device id - * @param[in] entry fdb entry - * @param[out] entry fdb entry - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -isisc_fdb_find(a_uint32_t dev_id, fal_fdb_entry_t * entry) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _isisc_fdb_find(dev_id, entry); - HSL_API_UNLOCK; - return rv; -} -#endif -/** - * @brief Get next Fdb entry from a particular device - * @param[in] dev_id device id - * @param[in] option next operation options - * @param[out] entry fdb entry - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -isisc_fdb_extend_next(a_uint32_t dev_id, fal_fdb_op_t * option, - fal_fdb_entry_t * entry) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _isisc_fdb_extend_next(dev_id, option, entry); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Get first Fdb entry from a particular device - * @param[in] dev_id device id - * @param[in] option first operation options - * @param[out] entry fdb entry - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -isisc_fdb_extend_first(a_uint32_t dev_id, fal_fdb_op_t * option, - fal_fdb_entry_t * entry) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _isisc_fdb_extend_first(dev_id, option, entry); - HSL_API_UNLOCK; - return rv; -} -#ifndef IN_FDB_MINI -/** - * @brief Transfer fdb entries port information on a particular device. - * @param[in] dev_id device id - * @param[in] old_port source port id - * @param[in] new_port destination port id - * @param[in] fid filter database id - * @param[in] option transfer operation options - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -isisc_fdb_transfer(a_uint32_t dev_id, fal_port_t old_port, fal_port_t new_port, - a_uint32_t fid, fal_fdb_op_t * option) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _isisc_fdb_transfer(dev_id, old_port, new_port, fid, option); - HSL_API_UNLOCK; - return rv; -} -#endif -/** - * @brief Set dynamic address learning status on a particular port. - * @details Comments: - * This operation will enable or disable dynamic address learning - * feature on a particular port. - * @param[in] dev_id device id - * @param[in] port_id port id - * @param[in] enable enable or disable - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -isisc_fdb_port_learn_set(a_uint32_t dev_id, fal_port_t port_id, a_bool_t enable) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _isisc_fdb_port_learn_set(dev_id, port_id, enable); - HSL_API_UNLOCK; - return rv; -} -#ifndef IN_FDB_MINI -/** - * @brief Get dynamic address learning status on a particular port. - * @param[in] dev_id device id - * @param[in] port_id port id - * @param[out] enable A_TRUE or A_FALSE - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -isisc_fdb_port_learn_get(a_uint32_t dev_id, fal_port_t port_id, - a_bool_t * enable) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _isisc_fdb_port_learn_get(dev_id, port_id, enable); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Set dynamic address aging status on particular device. - * @details Comments: - * This operation will enable or disable dynamic address aging - * feature on particular device. - * @param[in] dev_id device id - * @param[in] enable enable or disable - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -isisc_fdb_age_ctrl_set(a_uint32_t dev_id, a_bool_t enable) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _isisc_fdb_age_ctrl_set(dev_id, enable); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Get dynamic address aging status on particular device. - * @param[in] dev_id device id - * @param[in] enable enable or disable - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -isisc_fdb_age_ctrl_get(a_uint32_t dev_id, a_bool_t * enable) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _isisc_fdb_age_ctrl_get(dev_id, enable); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief set arl search mode as ivl or svl when vlan invalid. - * @param[in] dev_id device id - * @param[in] smode INVALID_VLAN_IVL or INVALID_VLAN_SVL - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -isisc_fdb_vlan_ivl_svl_set(a_uint32_t dev_id, fal_fdb_smode smode) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _isisc_fdb_vlan_ivl_svl_set(dev_id, smode); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief get arl search mode when vlan invalid. - * @param[in] dev_id device id - * @param[out] smode INVALID_VLAN_IVL or INVALID_VLAN_SVL - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -isisc_fdb_vlan_ivl_svl_get(a_uint32_t dev_id, fal_fdb_smode* smode) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _isisc_fdb_vlan_ivl_svl_get(dev_id, smode); - HSL_API_UNLOCK; - return rv; -} - - - -/** - * @brief Set dynamic address aging time on a particular device. - * @details Comments: - * This operation will set dynamic address aging time on a particular device. - * The unit of time is second. Because different device has differnet - * hardware granularity function will return actual time in hardware. - * @param[in] dev_id device id - * @param time aging time - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -isisc_fdb_age_time_set(a_uint32_t dev_id, a_uint32_t * time) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _isisc_fdb_age_time_set(dev_id, time); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Get dynamic address aging time on a particular device. - * @param[in] dev_id device id - * @param[out] time aging time - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -isisc_fdb_age_time_get(a_uint32_t dev_id, a_uint32_t * time) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _isisc_fdb_age_time_get(dev_id, time); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Set dynamic address learning count limit on a particular port. - * @param[in] dev_id device id - * @param[in] port_id port id - * @param[in] enable A_TRUE or A_FALSE - * @param[in] cnt limit count - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -isisc_port_fdb_learn_limit_set(a_uint32_t dev_id, fal_port_t port_id, - a_bool_t enable, a_uint32_t cnt) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _isisc_port_fdb_learn_limit_set(dev_id, port_id, enable, cnt); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Get dynamic address learning count limit on a particular port. - * @param[in] dev_id device id - * @param[in] port_id port id - * @param[out] enable A_TRUE or A_FALSE - * @param[out] cnt limit count - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -isisc_port_fdb_learn_limit_get(a_uint32_t dev_id, fal_port_t port_id, - a_bool_t * enable, a_uint32_t * cnt) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _isisc_port_fdb_learn_limit_get(dev_id, port_id, enable, cnt); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Set dynamic address learning count exceed command on a particular port. - * @param[in] dev_id device id - * @param[in] port_id port id - * @param[in] cmd forwarding command - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -isisc_port_fdb_learn_exceed_cmd_set(a_uint32_t dev_id, fal_port_t port_id, - fal_fwd_cmd_t cmd) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _isisc_port_fdb_learn_exceed_cmd_set(dev_id, port_id, cmd); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Get dynamic address learning count exceed command on a particular port. - * @param[in] dev_id device id - * @param[in] port_id port id - * @param[out] cmd forwarding command - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -isisc_port_fdb_learn_exceed_cmd_get(a_uint32_t dev_id, fal_port_t port_id, - fal_fwd_cmd_t * cmd) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _isisc_port_fdb_learn_exceed_cmd_get(dev_id, port_id, cmd); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Set dynamic address learning count limit on a particular device. - * @param[in] dev_id device id - * @param[in] enable A_TRUE or A_FALSE - * @param[in] cnt limit count - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -isisc_fdb_learn_limit_set(a_uint32_t dev_id, a_bool_t enable, a_uint32_t cnt) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _isisc_fdb_learn_limit_set(dev_id, enable, cnt); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Get dynamic address learning count limit on a particular device. - * @param[in] dev_id device id - * @param[in] enable A_TRUE or A_FALSE - * @param[in] cnt limit count - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -isisc_fdb_learn_limit_get(a_uint32_t dev_id, a_bool_t * enable, a_uint32_t * cnt) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _isisc_fdb_learn_limit_get(dev_id, enable, cnt); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Set dynamic address learning count exceed command on a particular device. - * @param[in] dev_id device id - * @param[in] cmd forwarding command - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -isisc_fdb_learn_exceed_cmd_set(a_uint32_t dev_id, fal_fwd_cmd_t cmd) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _isisc_fdb_learn_exceed_cmd_set(dev_id, cmd); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Get dynamic address learning count exceed command on a particular device. - * @param[in] dev_id device id - * @param[out] cmd forwarding command - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -isisc_fdb_learn_exceed_cmd_get(a_uint32_t dev_id, fal_fwd_cmd_t * cmd) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _isisc_fdb_learn_exceed_cmd_get(dev_id, cmd); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Add a particular reserve Fdb entry - * @param[in] dev_id device id - * @param[in] entry reserve fdb entry - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -isisc_fdb_resv_add(a_uint32_t dev_id, fal_fdb_entry_t * entry) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _isisc_fdb_resv_add(dev_id, entry); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Delete a particular reserve Fdb entry through mac address - * @param[in] dev_id device id - * @param[in] entry reserve fdb entry - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -isisc_fdb_resv_del(a_uint32_t dev_id, fal_fdb_entry_t * entry) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _isisc_fdb_resv_del(dev_id, entry); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Find a particular reserve Fdb entry through mac address - * @param[in] dev_id device id - * @param[in] entry reserve fdb entry - * @param[out] entry reserve fdb entry - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -isisc_fdb_resv_find(a_uint32_t dev_id, fal_fdb_entry_t * entry) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _isisc_fdb_resv_find(dev_id, entry); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Iterate all reserve fdb entries on a particular device. - * @param[in] dev_id device id - * @param[in] iterator reserve fdb entry index if it's zero means get the first entry - * @param[out] iterator next valid fdb entry index - * @param[out] entry reserve fdb entry - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -isisc_fdb_resv_iterate(a_uint32_t dev_id, a_uint32_t * iterator, - fal_fdb_entry_t * entry) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _isisc_fdb_resv_iterate(dev_id, iterator, entry); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Set the static status of fdb entries which learned by hardware on a particular port. - * @param[in] dev_id device id - * @param[in] port_id port id - * @param[in] enable A_TRUE or A_FALSE - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -isisc_fdb_port_learn_static_set(a_uint32_t dev_id, fal_port_t port_id, - a_bool_t enable) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _isisc_fdb_port_learn_static_set(dev_id, port_id, enable); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Get the static status of fdb entries which learned by hardware on a particular port. - * @param[in] dev_id device id - * @param[in] port_id port id - * @param[out] enable A_TRUE or A_FALSE - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -isisc_fdb_port_learn_static_get(a_uint32_t dev_id, fal_port_t port_id, - a_bool_t * enable) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _isisc_fdb_port_learn_static_get(dev_id, port_id, enable); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Add a port to an exsiting entry - * @param[in] dev_id device id - * @param[in] fid filtering database id - * @param[in] addr MAC address - * @param[in] port_id port id - * @return SW_OK or error code, If entry not exist will return error. - */ -HSL_LOCAL sw_error_t -isisc_fdb_port_add(a_uint32_t dev_id, a_uint32_t fid, fal_mac_addr_t * addr, fal_port_t port_id) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _isisc_fdb_port_update(dev_id, fid, addr, port_id, 1); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Delete a port from an exsiting entry - * @param[in] dev_id device id - * @param[in] fid filtering database id - * @param[in] addr MAC address - * @param[in] port_id port id - * @return SW_OK or error code, If entry not exist will return error. - */ -HSL_LOCAL sw_error_t -isisc_fdb_port_del(a_uint32_t dev_id, a_uint32_t fid, fal_mac_addr_t * addr, fal_port_t port_id) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _isisc_fdb_port_update(dev_id, fid, addr, port_id, 0); - HSL_API_UNLOCK; - return rv; -} -#endif -sw_error_t -isisc_fdb_init(a_uint32_t dev_id) -{ - HSL_DEV_ID_CHECK(dev_id); - -#ifndef HSL_STANDALONG - { - hsl_api_t *p_api; - - SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id)); -#ifndef IN_FDB_MINI - p_api->fdb_add = isisc_fdb_add; -#endif - p_api->fdb_del_all = isisc_fdb_del_all; -#ifndef IN_FDB_MINI - p_api->fdb_del_by_port = isisc_fdb_del_by_port; - p_api->fdb_del_by_mac = isisc_fdb_del_by_mac; - p_api->fdb_find = isisc_fdb_find; -#endif - p_api->port_learn_set = isisc_fdb_port_learn_set; -#ifndef IN_FDB_MINI - p_api->port_learn_get = isisc_fdb_port_learn_get; - p_api->age_ctrl_set = isisc_fdb_age_ctrl_set; - p_api->age_ctrl_get = isisc_fdb_age_ctrl_get; - p_api->vlan_ivl_svl_set = isisc_fdb_vlan_ivl_svl_set; - p_api->vlan_ivl_svl_get = isisc_fdb_vlan_ivl_svl_get; - p_api->age_time_set = isisc_fdb_age_time_set; - p_api->age_time_get = isisc_fdb_age_time_get; -#endif - p_api->fdb_extend_next = isisc_fdb_extend_next; - p_api->fdb_extend_first = isisc_fdb_extend_first; -#ifndef IN_FDB_MINI - p_api->fdb_transfer = isisc_fdb_transfer; - p_api->port_fdb_learn_limit_set = isisc_port_fdb_learn_limit_set; - p_api->port_fdb_learn_limit_get = isisc_port_fdb_learn_limit_get; - p_api->port_fdb_learn_exceed_cmd_set = isisc_port_fdb_learn_exceed_cmd_set; - p_api->port_fdb_learn_exceed_cmd_get = isisc_port_fdb_learn_exceed_cmd_get; - p_api->fdb_learn_limit_set = isisc_fdb_learn_limit_set; - p_api->fdb_learn_limit_get = isisc_fdb_learn_limit_get; - p_api->fdb_learn_exceed_cmd_set = isisc_fdb_learn_exceed_cmd_set; - p_api->fdb_learn_exceed_cmd_get = isisc_fdb_learn_exceed_cmd_get; - p_api->fdb_resv_add = isisc_fdb_resv_add; - p_api->fdb_resv_del = isisc_fdb_resv_del; - p_api->fdb_resv_find = isisc_fdb_resv_find; - p_api->fdb_resv_iterate = isisc_fdb_resv_iterate; - p_api->fdb_port_learn_static_set = isisc_fdb_port_learn_static_set; - p_api->fdb_port_learn_static_get = isisc_fdb_port_learn_static_get; - p_api->fdb_port_add = isisc_fdb_port_add; - p_api->fdb_port_del = isisc_fdb_port_del; -#endif - } -#endif - - return SW_OK; -} - -/** - * @} - */ - diff --git a/feeds/ipq807x/qca-ssdk/src/src/hsl/isisc/isisc_igmp.c b/feeds/ipq807x/qca-ssdk/src/src/hsl/isisc/isisc_igmp.c deleted file mode 100755 index 83a3df46e..000000000 --- a/feeds/ipq807x/qca-ssdk/src/src/hsl/isisc/isisc_igmp.c +++ /dev/null @@ -1,1147 +0,0 @@ -/* - * Copyright (c) 2012, 2016 The Linux Foundation. All rights reserved. - * Permission to use, copy, modify, and/or distribute this software for - * any purpose with or without fee is hereby granted, provided that the - * above copyright notice and this permission notice appear in all copies. - * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES - * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR - * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES - * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN - * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT - * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. - */ - - -/** - * @defgroup isisc_igmp ISISC_IGMP - * @{ - */ -#include "sw.h" -#include "hsl.h" -#include "hsl_dev.h" -#include "hsl_port_prop.h" -#include "isisc_igmp.h" -#include "isisc_reg.h" - -#define LEAVE_EN_OFFSET 2 -#define JOIN_EN_OFFSET 1 -#define IGMP_MLD_EN_OFFSET 0 - -#define ISISC_MAX_PORT_LEARN_LIMIT_CNT 1024 - -extern sw_error_t -isisc_igmp_sg_entry_set(a_uint32_t dev_id, fal_igmp_sg_entry_t * entry); - -extern sw_error_t -isisc_igmp_sg_entry_clear(a_uint32_t dev_id, fal_igmp_sg_entry_t * entry); - -extern sw_error_t -isisc_igmp_sg_entry_show(a_uint32_t dev_id); - -extern sw_error_t -isisc_igmp_sg_entry_query(a_uint32_t dev_id, fal_igmp_sg_info_t * info); - -static sw_error_t -_isisc_port_igmp_property_set(a_uint32_t dev_id, fal_port_t port_id, - a_bool_t enable, a_uint32_t item) -{ - sw_error_t rv; - a_uint32_t reg = 0, val; - - HSL_DEV_ID_CHECK(dev_id); - - if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU)) - { - return SW_BAD_PARAM; - } - - if (A_TRUE == enable) - { - val = 1; - } - else if (A_FALSE == enable) - { - val = 0; - } - else - { - return SW_BAD_PARAM; - } - - if (3 >= port_id) - { - HSL_REG_ENTRY_GET(rv, dev_id, FRAME_ACK_CTL0, 0, - (a_uint8_t *) (®), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - - reg &= ~(0x1UL << ((port_id << 3) + item)); - reg |= (val << ((port_id << 3) + item)); - - HSL_REG_ENTRY_SET(rv, dev_id, FRAME_ACK_CTL0, 0, - (a_uint8_t *) (®), sizeof (a_uint32_t)); - } - else - { - HSL_REG_ENTRY_GET(rv, dev_id, FRAME_ACK_CTL1, 0, - (a_uint8_t *) (®), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - - reg &= ~(0x1UL << (((port_id - 4) << 3) + item)); - reg |= (val << (((port_id - 4) << 3) + item)); - - HSL_REG_ENTRY_SET(rv, dev_id, FRAME_ACK_CTL1, 0, - (a_uint8_t *) (®), sizeof (a_uint32_t)); - } - return rv; -} - -static sw_error_t -_isisc_port_igmp_property_get(a_uint32_t dev_id, fal_port_t port_id, - a_bool_t * enable, a_uint32_t item) -{ - sw_error_t rv; - a_uint32_t reg = 0, val; - - HSL_DEV_ID_CHECK(dev_id); - - if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU)) - { - return SW_BAD_PARAM; - } - - if (3 >= port_id) - { - HSL_REG_ENTRY_GET(rv, dev_id, FRAME_ACK_CTL0, 0, - (a_uint8_t *) (®), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - - val = (reg >> ((port_id << 3) + item)) & 0x1UL; - } - else - { - HSL_REG_ENTRY_GET(rv, dev_id, FRAME_ACK_CTL1, 0, - (a_uint8_t *) (®), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - - val = (reg >> (((port_id - 4) << 3) + item)) & 0x1UL; - } - - if (1 == val) - { - *enable = A_TRUE; - } - else - { - *enable = A_FALSE; - } - - return SW_OK; -} - -static sw_error_t -_isisc_igmp_mld_cmd_set(a_uint32_t dev_id, fal_fwd_cmd_t cmd) -{ - sw_error_t rv; - a_uint32_t val; - - HSL_DEV_ID_CHECK(dev_id); - - if (FAL_MAC_CPY_TO_CPU == cmd) - { - val = 1; - } - else if (FAL_MAC_RDT_TO_CPU == cmd) - { - val = 0; - } - else - { - return SW_NOT_SUPPORTED; - } - - HSL_REG_FIELD_SET(rv, dev_id, FORWARD_CTL0, 0, IGMP_COPY_EN, - (a_uint8_t *) (&val), sizeof (a_uint32_t)); - return rv; -} - -static sw_error_t -_isisc_igmp_mld_cmd_get(a_uint32_t dev_id, fal_fwd_cmd_t * cmd) -{ - sw_error_t rv; - a_uint32_t val = 0; - - HSL_DEV_ID_CHECK(dev_id); - - HSL_REG_FIELD_GET(rv, dev_id, FORWARD_CTL0, 0, IGMP_COPY_EN, - (a_uint8_t *) (&val), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - - if (1 == val) - { - *cmd = FAL_MAC_CPY_TO_CPU; - } - else - { - *cmd = FAL_MAC_RDT_TO_CPU; - } - - return SW_OK; -} - -static sw_error_t -_isisc_igmp_mld_rp_set(a_uint32_t dev_id, fal_pbmp_t pts) -{ - sw_error_t rv; - a_uint32_t val; - - HSL_DEV_ID_CHECK(dev_id); - - if (A_FALSE == hsl_mports_validity_check(dev_id, pts)) - { - return SW_BAD_PARAM; - } - val = pts; - HSL_REG_FIELD_SET(rv, dev_id, FORWARD_CTL1, 0, IGMP_DP, - (a_uint8_t *) (&val), sizeof (a_uint32_t)); - return rv; -} - -static sw_error_t -_isisc_igmp_mld_rp_get(a_uint32_t dev_id, fal_pbmp_t * pts) -{ - sw_error_t rv; - a_uint32_t val = 0; - - HSL_DEV_ID_CHECK(dev_id); - - HSL_REG_FIELD_GET(rv, dev_id, FORWARD_CTL1, 0, IGMP_DP, - (a_uint8_t *) (&val), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - - *pts = val; - return SW_OK; -} - -static sw_error_t -_isisc_igmp_mld_entry_creat_set(a_uint32_t dev_id, a_bool_t enable) -{ - sw_error_t rv; - a_uint32_t val; - - HSL_DEV_ID_CHECK(dev_id); - - if (A_TRUE == enable) - { - val = 1; - } - else if (A_FALSE == enable) - { - val = 0; - } - else - { - return SW_BAD_PARAM; - } - - HSL_REG_FIELD_SET(rv, dev_id, ADDR_TABLE_CTL, 0, IGMP_CREAT_EN, - (a_uint8_t *) (&val), sizeof (a_uint32_t)); - return rv; -} - -static sw_error_t -_isisc_igmp_mld_entry_creat_get(a_uint32_t dev_id, a_bool_t * enable) -{ - sw_error_t rv; - a_uint32_t val = 0; - - HSL_DEV_ID_CHECK(dev_id); - - HSL_REG_FIELD_GET(rv, dev_id, ADDR_TABLE_CTL, 0, IGMP_CREAT_EN, - (a_uint8_t *) (&val), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - - if (val) - { - *enable = A_TRUE; - } - else - { - *enable = A_FALSE; - } - - return SW_OK; -} - -static sw_error_t -_isisc_igmp_mld_entry_static_set(a_uint32_t dev_id, a_bool_t enable) -{ - sw_error_t rv; - a_uint32_t val; - - HSL_DEV_ID_CHECK(dev_id); - - if (A_TRUE == enable) - { - val = 0xf; - } - else if (A_FALSE == enable) - { - val = 0xe; - } - else - { - return SW_BAD_PARAM; - } - - HSL_REG_FIELD_SET(rv, dev_id, ADDR_TABLE_CTL, 0, IGMP_JOIN_STATIC, - (a_uint8_t *) (&val), sizeof (a_uint32_t)); - return rv; -} - -static sw_error_t -_isisc_igmp_mld_entry_static_get(a_uint32_t dev_id, a_bool_t * enable) -{ - sw_error_t rv; - a_uint32_t val = 0; - - HSL_DEV_ID_CHECK(dev_id); - - HSL_REG_FIELD_GET(rv, dev_id, ADDR_TABLE_CTL, 0, IGMP_JOIN_STATIC, - (a_uint8_t *) (&val), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - - if (0xf == val) - { - *enable = A_TRUE; - } - else - { - *enable = A_FALSE; - } - - return SW_OK; -} - -static sw_error_t -_isisc_igmp_mld_entry_leaky_set(a_uint32_t dev_id, a_bool_t enable) -{ - sw_error_t rv; - a_uint32_t val; - - HSL_DEV_ID_CHECK(dev_id); - - if (A_TRUE == enable) - { - val = 1; - } - else if (A_FALSE == enable) - { - val = 0; - } - else - { - return SW_BAD_PARAM; - } - - HSL_REG_FIELD_SET(rv, dev_id, ADDR_TABLE_CTL, 0, IGMP_JOIN_LEAKY, - (a_uint8_t *) (&val), sizeof (a_uint32_t)); - return rv; -} - -static sw_error_t -_isisc_igmp_mld_entry_leaky_get(a_uint32_t dev_id, a_bool_t * enable) -{ - sw_error_t rv; - a_uint32_t val = 0; - - HSL_DEV_ID_CHECK(dev_id); - - HSL_REG_FIELD_GET(rv, dev_id, ADDR_TABLE_CTL, 0, IGMP_JOIN_LEAKY, - (a_uint8_t *) (&val), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - - if (val) - { - *enable = A_TRUE; - } - else - { - *enable = A_FALSE; - } - - return SW_OK; -} - -static sw_error_t -_isisc_igmp_mld_entry_v3_set(a_uint32_t dev_id, a_bool_t enable) -{ - sw_error_t rv; - a_uint32_t val; - - HSL_DEV_ID_CHECK(dev_id); - - if (A_TRUE == enable) - { - val = 1; - } - else if (A_FALSE == enable) - { - val = 0; - } - else - { - return SW_BAD_PARAM; - } - - HSL_REG_FIELD_SET(rv, dev_id, FRAME_ACK_CTL1, 0, IGMP_V3_EN, - (a_uint8_t *) (&val), sizeof (a_uint32_t)); - return rv; -} - -static sw_error_t -_isisc_igmp_mld_entry_v3_get(a_uint32_t dev_id, a_bool_t * enable) -{ - sw_error_t rv; - a_uint32_t val = 0; - - HSL_DEV_ID_CHECK(dev_id); - - HSL_REG_FIELD_GET(rv, dev_id, FRAME_ACK_CTL1, 0, IGMP_V3_EN, - (a_uint8_t *) (&val), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - - if (val) - { - *enable = A_TRUE; - } - else - { - *enable = A_FALSE; - } - - return SW_OK; -} - -static sw_error_t -_isisc_igmp_mld_entry_queue_set(a_uint32_t dev_id, a_bool_t enable, - a_uint32_t queue) -{ - sw_error_t rv; - a_uint32_t entry = 0; - - HSL_DEV_ID_CHECK(dev_id); - - HSL_REG_ENTRY_GET(rv, dev_id, ADDR_TABLE_CTL, 0, - (a_uint8_t *) (&entry), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - - if (A_TRUE == enable) - { - SW_SET_REG_BY_FIELD(ADDR_TABLE_CTL, IGMP_PRI_EN, 1, entry); - SW_SET_REG_BY_FIELD(ADDR_TABLE_CTL, IGMP_PRI, queue, entry); - } - else if (A_FALSE == enable) - { - SW_SET_REG_BY_FIELD(ADDR_TABLE_CTL, IGMP_PRI_EN, 0, entry); - SW_SET_REG_BY_FIELD(ADDR_TABLE_CTL, IGMP_PRI, 0, entry); - } - else - { - return SW_BAD_PARAM; - } - - HSL_REG_ENTRY_SET(rv, dev_id, ADDR_TABLE_CTL, 0, - (a_uint8_t *) (&entry), sizeof (a_uint32_t)); - return rv; -} - -static sw_error_t -_isisc_igmp_mld_entry_queue_get(a_uint32_t dev_id, a_bool_t * enable, - a_uint32_t * queue) -{ - sw_error_t rv; - a_uint32_t entry = 0, data; - - HSL_DEV_ID_CHECK(dev_id); - - HSL_REG_ENTRY_GET(rv, dev_id, ADDR_TABLE_CTL, 0, - (a_uint8_t *) (&entry), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - - SW_GET_FIELD_BY_REG(ADDR_TABLE_CTL, IGMP_PRI_EN, data, entry); - if (data) - { - *enable = A_TRUE; - SW_GET_FIELD_BY_REG(ADDR_TABLE_CTL, IGMP_PRI, data, entry); - *queue = data; - } - else - { - *enable = A_FALSE; - *queue = 0; - } - - return SW_OK; -} - -static sw_error_t -_isisc_port_igmp_mld_learn_limit_set(a_uint32_t dev_id, fal_port_t port_id, - a_bool_t enable, a_uint32_t cnt) -{ - sw_error_t rv; - a_uint32_t reg = 0; - - HSL_DEV_ID_CHECK(dev_id); - - if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU)) - { - return SW_BAD_PARAM; - } - - HSL_REG_ENTRY_GET(rv, dev_id, PORT_LEARN_LIMIT_CTL, port_id, - (a_uint8_t *) (®), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - - if (A_TRUE == enable) - { - if (ISISC_MAX_PORT_LEARN_LIMIT_CNT < cnt) - { - return SW_BAD_PARAM; - } - SW_SET_REG_BY_FIELD(PORT_LEARN_LIMIT_CTL, IGMP_JOIN_LIMIT_EN, 1, reg); - SW_SET_REG_BY_FIELD(PORT_LEARN_LIMIT_CTL, IGMP_JOIN_CNT, cnt, reg); - } - else if (A_FALSE == enable) - { - SW_SET_REG_BY_FIELD(PORT_LEARN_LIMIT_CTL, IGMP_JOIN_LIMIT_EN, 0, reg); - SW_SET_REG_BY_FIELD(PORT_LEARN_LIMIT_CTL, IGMP_JOIN_CNT, 0, reg); - } - else - { - return SW_BAD_PARAM; - } - - HSL_REG_ENTRY_SET(rv, dev_id, PORT_LEARN_LIMIT_CTL, port_id, - (a_uint8_t *) (®), sizeof (a_uint32_t)); - return rv; -} - -static sw_error_t -_isisc_port_igmp_mld_learn_limit_get(a_uint32_t dev_id, fal_port_t port_id, - a_bool_t * enable, a_uint32_t * cnt) -{ - sw_error_t rv; - a_uint32_t data, reg = 0; - - HSL_DEV_ID_CHECK(dev_id); - - if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU)) - { - return SW_BAD_PARAM; - } - - HSL_REG_ENTRY_GET(rv, dev_id, PORT_LEARN_LIMIT_CTL, port_id, - (a_uint8_t *) (®), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - - SW_GET_FIELD_BY_REG(PORT_LEARN_LIMIT_CTL, IGMP_JOIN_LIMIT_EN, data, reg); - if (data) - { - SW_GET_FIELD_BY_REG(PORT_LEARN_LIMIT_CTL, IGMP_JOIN_CNT, data, reg); - *enable = A_TRUE; - *cnt = data; - } - else - { - *enable = A_FALSE; - *cnt = data; - } - - return SW_OK; -} - -static sw_error_t -_isisc_port_igmp_mld_learn_exceed_cmd_set(a_uint32_t dev_id, fal_port_t port_id, - fal_fwd_cmd_t cmd) -{ - sw_error_t rv; - a_uint32_t data = 0; - - HSL_DEV_ID_CHECK(dev_id); - - if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU)) - { - return SW_BAD_PARAM; - } - - if (FAL_MAC_DROP == cmd) - { - data = 1; - } - else if (FAL_MAC_RDT_TO_CPU == cmd) - { - data = 0; - } - else - { - return SW_NOT_SUPPORTED; - } - - HSL_REG_FIELD_SET(rv, dev_id, PORT_LEARN_LIMIT_CTL, port_id, - IGMP_JOIN_LIMIT_DROP_EN, (a_uint8_t *) (&data), - sizeof (a_uint32_t)); - return rv; -} - -static sw_error_t -_isisc_port_igmp_mld_learn_exceed_cmd_get(a_uint32_t dev_id, fal_port_t port_id, - fal_fwd_cmd_t * cmd) -{ - sw_error_t rv; - a_uint32_t data = 0; - - HSL_DEV_ID_CHECK(dev_id); - - if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU)) - { - return SW_BAD_PARAM; - } - - HSL_REG_FIELD_GET(rv, dev_id, PORT_LEARN_LIMIT_CTL, port_id, - IGMP_JOIN_LIMIT_DROP_EN, (a_uint8_t *) (&data), - sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - - if (data) - { - *cmd = FAL_MAC_DROP; - } - else - { - *cmd = FAL_MAC_RDT_TO_CPU; - } - - return SW_OK; -} - -/** - * @brief Set igmp/mld packets snooping status on a particular port. - * @details Comments: - * After enabling igmp/mld snooping feature on a particular port all kinds - * igmp/mld packets received on this port would be acknowledged by hardware. - * Particular forwarding decision could be setted by fal_igmp_mld_cmd_set. - * @param[in] dev_id device id - * @param[in] port_id port id - * @param[in] enable A_TRUE or A_FALSE - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -isisc_port_igmps_status_set(a_uint32_t dev_id, fal_port_t port_id, - a_bool_t enable) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _isisc_port_igmp_property_set(dev_id, port_id, enable, - IGMP_MLD_EN_OFFSET); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Get igmp/mld packets snooping status on particular port. - * @param[in] dev_id device id - * @param[in] port_id port id - * @param[out] enable A_TRUE or A_FALSE - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -isisc_port_igmps_status_get(a_uint32_t dev_id, fal_port_t port_id, - a_bool_t * enable) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _isisc_port_igmp_property_get(dev_id, port_id, enable, - IGMP_MLD_EN_OFFSET); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Set igmp/mld packets forwarding command on a particular device. - * @details Comments: - * Particular device may only support parts of forwarding commands. - * This operation will take effect only after enabling igmp/mld snooping - * @param[in] dev_id device id - * @param[in] cmd forwarding command - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -isisc_igmp_mld_cmd_set(a_uint32_t dev_id, fal_fwd_cmd_t cmd) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _isisc_igmp_mld_cmd_set(dev_id, cmd); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Get igmp/mld packets forwarding command on a particular device. - * @param[in] dev_id device id - * @param[out] cmd forwarding command - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -isisc_igmp_mld_cmd_get(a_uint32_t dev_id, fal_fwd_cmd_t * cmd) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _isisc_igmp_mld_cmd_get(dev_id, cmd); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Set igmp/mld join packets hardware acknowledgement status on particular port. - * @details Comments: - * After enabling igmp/mld join feature on a particular port hardware will - * dynamic learning or changing multicast entry. - * @param[in] dev_id device id - * @param[in] port_id port id - * @param[in] enable A_TRUE or A_FALSE - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -isisc_port_igmp_mld_join_set(a_uint32_t dev_id, fal_port_t port_id, - a_bool_t enable) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _isisc_port_igmp_property_set(dev_id, port_id, enable, JOIN_EN_OFFSET); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Get igmp/mld join packets hardware acknowledgement status on a particular port. - * @param[in] dev_id device id - * @param[in] port_id port id - * @param[out] enable A_TRUE or A_FALSE - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -isisc_port_igmp_mld_join_get(a_uint32_t dev_id, fal_port_t port_id, - a_bool_t * enable) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _isisc_port_igmp_property_get(dev_id, port_id, enable, JOIN_EN_OFFSET); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Set igmp/mld leave packets hardware acknowledgement status on a particular port. - * @details Comments: - * After enabling igmp leave feature on a particular port hardware will dynamic - * deleting or changing multicast entry. - * @param[in] dev_id device id - * @param[in] port_id port id - * @param[in] enable A_TRUE or A_FALSE - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -isisc_port_igmp_mld_leave_set(a_uint32_t dev_id, fal_port_t port_id, - a_bool_t enable) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _isisc_port_igmp_property_set(dev_id, port_id, enable, LEAVE_EN_OFFSET); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Get igmp/mld leave packets hardware acknowledgement status on a particular port. - * @param[in] dev_id device id - * @param[in] port_id port id - * @param[out] enable A_TRUE or A_FALSE - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -isisc_port_igmp_mld_leave_get(a_uint32_t dev_id, fal_port_t port_id, - a_bool_t * enable) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _isisc_port_igmp_property_get(dev_id, port_id, enable, LEAVE_EN_OFFSET); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Set igmp/mld router ports on a particular device. - * @details Comments: - * After enabling igmp/mld join/leave feature on a particular port igmp/mld - * join/leave packets received on this port will be forwarded to router ports. - * @param[in] dev_id device id - * @param[in] pts dedicates ports - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -isisc_igmp_mld_rp_set(a_uint32_t dev_id, fal_pbmp_t pts) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _isisc_igmp_mld_rp_set(dev_id, pts); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Get igmp/mld router ports on a particular device. - * @param[in] dev_id device id - * @param[out] pts dedicates ports - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -isisc_igmp_mld_rp_get(a_uint32_t dev_id, fal_pbmp_t * pts) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _isisc_igmp_mld_rp_get(dev_id, pts); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Set the status of creating multicast entry during igmp/mld join/leave procedure. - * @details Comments: - * After enabling igmp/mld join/leave feature on a particular port if enable - * entry creat hardware will dynamic creat and delete multicast entry, - * otherwise hardware only can change destination ports of existing muticast entry. - * @param[in] dev_id device id - * @param[in] enable A_TRUE or A_FALSE - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -isisc_igmp_mld_entry_creat_set(a_uint32_t dev_id, a_bool_t enable) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _isisc_igmp_mld_entry_creat_set(dev_id, enable); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Get the status of creating multicast entry during igmp/mld join/leave procedure. - * @param[in] dev_id device id - * @param[out] enable A_TRUE or A_FALSE - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -isisc_igmp_mld_entry_creat_get(a_uint32_t dev_id, a_bool_t * enable) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _isisc_igmp_mld_entry_creat_get(dev_id, enable); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Set the static status of multicast entry which learned by hardware. - * @details Comments: - * After enabling igmp/mld join/leave feature on a particular port if enable - * static status hardware will not age out multicast entry which leardned by hardware, - * otherwise hardware will age out multicast entry which leardned by hardware. - * @param[in] dev_id device id - * @param[in] enable A_TRUE or A_FALSE - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -isisc_igmp_mld_entry_static_set(a_uint32_t dev_id, a_bool_t enable) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _isisc_igmp_mld_entry_static_set(dev_id, enable); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Get the static status of multicast entry which learned by hardware. - * @param[in] dev_id device id - * @param[out] enable A_TRUE or A_FALSE - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -isisc_igmp_mld_entry_static_get(a_uint32_t dev_id, a_bool_t * enable) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _isisc_igmp_mld_entry_static_get(dev_id, enable); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Set the leaky status of multicast entry which learned by hardware. - * @details Comments: - * After enabling igmp/mld join/leave feature on a particular port if enable - * leaky status hardware will set leaky flag of multicast entry which leardned by hardware, - * otherwise hardware will not set leaky flag of multicast entry which leardned by hardware. - * @param[in] dev_id device id - * @param[in] enable A_TRUE or A_FALSE - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -isisc_igmp_mld_entry_leaky_set(a_uint32_t dev_id, a_bool_t enable) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _isisc_igmp_mld_entry_leaky_set(dev_id, enable); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Get the leaky status of multicast entry which learned by hardware. - * @param[in] dev_id device id - * @param[out] enable A_TRUE or A_FALSE - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -isisc_igmp_mld_entry_leaky_get(a_uint32_t dev_id, a_bool_t * enable) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _isisc_igmp_mld_entry_leaky_get(dev_id, enable); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Set igmpv3/mldv2 packets hardware acknowledgement status on a particular device. - * @details Comments: - * After enabling igmp join/leave feature on a particular port hardware will dynamic - * creating or changing multicast entry after receiving igmpv3/mldv2 packets. - * @param[in] dev_id device id - * @param[in] enable A_TRUE or A_FALSE - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -isisc_igmp_mld_entry_v3_set(a_uint32_t dev_id, a_bool_t enable) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _isisc_igmp_mld_entry_v3_set(dev_id, enable); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Get igmpv3/mldv2 packets hardware acknowledgement status on a particular device. - * @param[in] dev_id device id - * @param[out] enable A_TRUE or A_FALSE - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -isisc_igmp_mld_entry_v3_get(a_uint32_t dev_id, a_bool_t * enable) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _isisc_igmp_mld_entry_v3_get(dev_id, enable); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Set the queue status of multicast entry which learned by hardware. - * @details Comments: - * After enabling igmp/mld join/leave feature on a particular port if enable - * leaky status hardware will set queue flag of multicast entry which leardned by hardware, - * otherwise hardware will not set queue flag of multicast entry which leardned by hardware. - * @param[in] dev_id device id - * @param[in] enable A_TRUE or A_FALSE - * @param[in] queue queue id - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -isisc_igmp_mld_entry_queue_set(a_uint32_t dev_id, a_bool_t enable, - a_uint32_t queue) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _isisc_igmp_mld_entry_queue_set(dev_id, enable, queue); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Get the queue status of multicast entry which learned by hardware. - * @param[in] dev_id device id - * @param[out] enable A_TRUE or A_FALSE - * @param[out] queue queue id - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -isisc_igmp_mld_entry_queue_get(a_uint32_t dev_id, a_bool_t * enable, - a_uint32_t * queue) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _isisc_igmp_mld_entry_queue_get(dev_id, enable, queue); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Set IGMP hardware learning count limit on a particular port. - * @param[in] dev_id device id - * @param[in] port_id port id - * @param[in] enable A_TRUE or A_FALSE - * @param[in] cnt limit count - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -isisc_port_igmp_mld_learn_limit_set(a_uint32_t dev_id, fal_port_t port_id, - a_bool_t enable, a_uint32_t cnt) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _isisc_port_igmp_mld_learn_limit_set(dev_id, port_id, enable, cnt); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Get IGMP hardware learning count limit on a particular port. - * @param[in] dev_id device id - * @param[in] port_id port id - * @param[out] enable A_TRUE or A_FALSE - * @param[out] cnt limit count - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -isisc_port_igmp_mld_learn_limit_get(a_uint32_t dev_id, fal_port_t port_id, - a_bool_t * enable, a_uint32_t * cnt) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _isisc_port_igmp_mld_learn_limit_get(dev_id, port_id, enable, cnt); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Set IGMP hardware learning count exceed command on a particular port. - * @param[in] dev_id device id - * @param[in] port_id port id - * @param[in] cmd forwarding command - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -isisc_port_igmp_mld_learn_exceed_cmd_set(a_uint32_t dev_id, fal_port_t port_id, - fal_fwd_cmd_t cmd) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _isisc_port_igmp_mld_learn_exceed_cmd_set(dev_id, port_id, cmd); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Get IGMP hardware learning count exceed command on a particular port. - * @param[in] dev_id device id - * @param[in] port_id port id - * @param[out] cmd forwarding command - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -isisc_port_igmp_mld_learn_exceed_cmd_get(a_uint32_t dev_id, fal_port_t port_id, - fal_fwd_cmd_t * cmd) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _isisc_port_igmp_mld_learn_exceed_cmd_get(dev_id, port_id, cmd); - HSL_API_UNLOCK; - return rv; -} - -sw_error_t -isisc_igmp_init(a_uint32_t dev_id) -{ - HSL_DEV_ID_CHECK(dev_id); - -#ifndef HSL_STANDALONG - { - hsl_api_t *p_api; - - SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id)); - - p_api->port_igmps_status_set = isisc_port_igmps_status_set; - p_api->port_igmps_status_get = isisc_port_igmps_status_get; - p_api->igmp_mld_cmd_set = isisc_igmp_mld_cmd_set; - p_api->igmp_mld_cmd_get = isisc_igmp_mld_cmd_get; - p_api->port_igmp_join_set = isisc_port_igmp_mld_join_set; - p_api->port_igmp_join_get = isisc_port_igmp_mld_join_get; - p_api->port_igmp_leave_set = isisc_port_igmp_mld_leave_set; - p_api->port_igmp_leave_get = isisc_port_igmp_mld_leave_get; - p_api->igmp_rp_set = isisc_igmp_mld_rp_set; - p_api->igmp_rp_get = isisc_igmp_mld_rp_get; - p_api->igmp_entry_creat_set = isisc_igmp_mld_entry_creat_set; - p_api->igmp_entry_creat_get = isisc_igmp_mld_entry_creat_get; - p_api->igmp_entry_static_set = isisc_igmp_mld_entry_static_set; - p_api->igmp_entry_static_get = isisc_igmp_mld_entry_static_get; - p_api->igmp_entry_leaky_set = isisc_igmp_mld_entry_leaky_set; - p_api->igmp_entry_leaky_get = isisc_igmp_mld_entry_leaky_get; - p_api->igmp_entry_v3_set = isisc_igmp_mld_entry_v3_set; - p_api->igmp_entry_v3_get = isisc_igmp_mld_entry_v3_get; - p_api->igmp_entry_queue_set = isisc_igmp_mld_entry_queue_set; - p_api->igmp_entry_queue_get = isisc_igmp_mld_entry_queue_get; - p_api->port_igmp_mld_learn_limit_set = isisc_port_igmp_mld_learn_limit_set; - p_api->port_igmp_mld_learn_limit_get = isisc_port_igmp_mld_learn_limit_get; - p_api->port_igmp_mld_learn_exceed_cmd_set = isisc_port_igmp_mld_learn_exceed_cmd_set; - p_api->port_igmp_mld_learn_exceed_cmd_get = isisc_port_igmp_mld_learn_exceed_cmd_get; - p_api->igmp_sg_entry_set = isisc_igmp_sg_entry_set; - p_api->igmp_sg_entry_clear = isisc_igmp_sg_entry_clear; - p_api->igmp_sg_entry_show = isisc_igmp_sg_entry_show; - p_api->igmp_sg_entry_query = isisc_igmp_sg_entry_query; - } -#endif - - return SW_OK; -} - -/** - * @} - */ - diff --git a/feeds/ipq807x/qca-ssdk/src/src/hsl/isisc/isisc_init.c b/feeds/ipq807x/qca-ssdk/src/src/hsl/isisc/isisc_init.c deleted file mode 100755 index e55fa18d6..000000000 --- a/feeds/ipq807x/qca-ssdk/src/src/hsl/isisc/isisc_init.c +++ /dev/null @@ -1,337 +0,0 @@ -/* - * Copyright (c) 2012, 2016-2017, The Linux Foundation. All rights reserved. - * Permission to use, copy, modify, and/or distribute this software for - * any purpose with or without fee is hereby granted, provided that the - * above copyright notice and this permission notice appear in all copies. - * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES - * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR - * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES - * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN - * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT - * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. - */ - - -/** - * @defgroup isisc_init ISISC_INIT - * @{ - */ -#include "sw.h" -#include "hsl.h" -#include "hsl_dev.h" -#include "hsl_port_prop.h" -#include "isisc_mib.h" -#include "isisc_port_ctrl.h" -#include "isisc_portvlan.h" -#include "isisc_vlan.h" -#include "isisc_fdb.h" -#include "isisc_qos.h" -#include "isisc_mirror.h" -#include "isisc_stp.h" -#include "isisc_rate.h" -#include "isisc_misc.h" -#include "isisc_leaky.h" -#include "isisc_igmp.h" -#include "isisc_acl.h" -#include "isisc_led.h" -#include "isisc_cosmap.h" -#include "isisc_ip.h" -#include "isisc_nat.h" -#if defined(IN_NAT_HELPER) -#include "isisc_nat_helper.h" -#endif -#include "isisc_sec.h" -#include "isisc_trunk.h" -#include "isisc_interface_ctrl.h" -#include "isisc_reg_access.h" -#include "isisc_reg.h" -#include "isisc_init.h" -#include "f1_phy.h" - -static ssdk_init_cfg * isisc_cfg[SW_MAX_NR_DEV] = { 0 }; -a_uint32_t isisc_nat_global_status = 0; - -#if !(defined(KERNEL_MODULE) && defined(USER_MODE)) -/* For isis there are five internal PHY devices and seven MAC devices. - MAC0 always connect to external MAC device. - PHY4 can connect to MAC5 or external MAC device. - MAC6 always connect to external devices. - MAC1..MAC4 connect to internal PHY0..PHY3. -*/ -static sw_error_t -isisc_portproperty_init(a_uint32_t dev_id, hsl_init_mode mode) -{ - hsl_port_prop_t p_type; - hsl_dev_t *pdev = NULL; - fal_port_t port_id; - - pdev = hsl_dev_ptr_get(dev_id); - if (pdev == NULL) - return SW_NOT_INITIALIZED; - - /* for port property set, SSDK should not generate some limitations */ - for (port_id = 0; port_id < pdev->nr_ports; port_id++) - { - hsl_port_prop_portmap_set(dev_id, port_id); - - for (p_type = HSL_PP_PHY; p_type < HSL_PP_BUTT; p_type++) - { - if (HSL_NO_CPU == mode) - { - SW_RTN_ON_ERROR(hsl_port_prop_set(dev_id, port_id, p_type)); - continue; - } - - switch (p_type) - { - case HSL_PP_PHY: - /* Only port0/port6 without PHY device */ - if ((port_id != pdev->cpu_port_nr) - && (port_id != pdev->nr_ports - 1)) - { - SW_RTN_ON_ERROR(hsl_port_prop_set(dev_id, port_id, p_type)); - } - break; - - case HSL_PP_INCL_CPU: - /* include cpu port but exclude wan port in some cases */ - /* but which port is wan port, we are no meaning */ - SW_RTN_ON_ERROR(hsl_port_prop_set(dev_id, port_id, p_type)); - break; - - case HSL_PP_EXCL_CPU: - /* exclude cpu port and wan port in some cases */ - /* which port is wan port, we are no meaning but port0 is - always CPU port */ - if (port_id != pdev->cpu_port_nr) - { - SW_RTN_ON_ERROR(hsl_port_prop_set(dev_id, port_id, p_type)); - } - break; - - default: - break; - } - } - - if (HSL_NO_CPU == mode) - { - SW_RTN_ON_ERROR(hsl_port_prop_set_phyid - (dev_id, port_id, port_id + 1)); - } - else - { - if (port_id != pdev->cpu_port_nr) - { - SW_RTN_ON_ERROR(hsl_port_prop_set_phyid - (dev_id, port_id, port_id - 1)); - } - } - } - - return SW_OK; -} - -static sw_error_t -isisc_hw_init(a_uint32_t dev_id, ssdk_init_cfg *cfg) -{ - return SW_OK; -} - -#endif - -static sw_error_t -isisc_dev_init(a_uint32_t dev_id, hsl_init_mode cpu_mode) -{ - a_uint32_t entry = 0; - sw_error_t rv; - hsl_dev_t *pdev = NULL; - - pdev = hsl_dev_ptr_get(dev_id); - if (pdev == NULL) - return SW_NOT_INITIALIZED; - - HSL_REG_FIELD_GET(rv, dev_id, MASK_CTL, 0, DEVICE_ID, - (a_uint8_t *) (&entry), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - - if (S17C_DEVICE_ID == entry) - { - pdev->nr_ports = 7; - pdev->nr_phy = 5; - pdev->cpu_port_nr = 0; - pdev->nr_vlans = 4096; - pdev->hw_vlan_query = A_TRUE; - pdev->nr_queue = 6; - pdev->cpu_mode = cpu_mode; - } - else - { - pdev->nr_ports = 6; - pdev->nr_phy = 5; - pdev->cpu_port_nr = 0; - pdev->nr_vlans = 4096; - pdev->hw_vlan_query = A_TRUE; - pdev->nr_queue = 6; - pdev->cpu_mode = cpu_mode; - } - - return SW_OK; -} - - -static sw_error_t -_isisc_reset(a_uint32_t dev_id) -{ -#if !(defined(KERNEL_MODULE) && defined(USER_MODE)) - sw_error_t rv; - a_uint32_t val; - - HSL_DEV_ID_CHECK(dev_id); - - val = 0x1; - HSL_REG_FIELD_SET(rv, dev_id, MASK_CTL, 0, SOFT_RST, - (a_uint8_t *) (&val), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - - rv = isisc_hw_init(dev_id, isisc_cfg[dev_id]); - SW_RTN_ON_ERROR(rv); - - ISISC_ACL_RESET(rv, dev_id); - ISISC_IP_RESET(rv, dev_id); - ISISC_NAT_RESET(rv, dev_id); -#endif - - return SW_OK; -} - -sw_error_t -isisc_cleanup(a_uint32_t dev_id) -{ - sw_error_t rv; - - if (isisc_cfg[dev_id]) - { -#if defined(IN_NAT_HELPER) - if(isisc_nat_global_status) { - ISISC_NAT_HELPER_CLEANUP(rv, dev_id); - isisc_nat_global_status = 0; - } -#endif - - ISISC_ACL_CLEANUP(rv, dev_id); - - SW_RTN_ON_ERROR(hsl_port_prop_cleanup_by_dev(dev_id)); - - aos_mem_free(isisc_cfg[dev_id]); - isisc_cfg[dev_id] = NULL; - } - - return SW_OK; -} - -/** - * @brief reset hsl layer. - * @details Comments: - * This operation will reset hsl layer - * @param[in] dev_id device id - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -isisc_reset(a_uint32_t dev_id) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _isisc_reset(dev_id); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Init hsl layer. - * @details Comments: - * This operation will init hsl layer and hsl layer - * @param[in] dev_id device id - * @param[in] cfg configuration for initialization - * @return SW_OK or error code - */ -sw_error_t -isisc_init(a_uint32_t dev_id, ssdk_init_cfg *cfg) -{ - HSL_DEV_ID_CHECK(dev_id); - - if (NULL == isisc_cfg[dev_id]) - { - isisc_cfg[dev_id] = aos_mem_alloc(sizeof (ssdk_init_cfg)); - } - - if (NULL == isisc_cfg[dev_id]) - { - return SW_OUT_OF_MEM; - } - - aos_mem_copy(isisc_cfg[dev_id], cfg, sizeof (ssdk_init_cfg)); - - SW_RTN_ON_ERROR(isisc_reg_access_init(dev_id, cfg->reg_mode)); - - SW_RTN_ON_ERROR(isisc_dev_init(dev_id, cfg->cpu_mode)); - -#if !(defined(KERNEL_MODULE) && defined(USER_MODE)) - { - sw_error_t rv; - - SW_RTN_ON_ERROR(hsl_port_prop_init(dev_id)); - SW_RTN_ON_ERROR(hsl_port_prop_init_by_dev(dev_id)); - SW_RTN_ON_ERROR(isisc_portproperty_init(dev_id, cfg->cpu_mode)); - - ISISC_MIB_INIT(rv, dev_id); - ISISC_PORT_CTRL_INIT(rv, dev_id); - ISISC_PORTVLAN_INIT(rv, dev_id); - ISISC_VLAN_INIT(rv, dev_id); - ISISC_FDB_INIT(rv, dev_id); - ISISC_QOS_INIT(rv, dev_id); - ISISC_STP_INIT(rv, dev_id); - ISISC_MIRR_INIT(rv, dev_id); - ISISC_RATE_INIT(rv, dev_id); - ISISC_MISC_INIT(rv, dev_id); - ISISC_LEAKY_INIT(rv, dev_id); - ISISC_IGMP_INIT(rv, dev_id); - ISISC_ACL_INIT(rv, dev_id); - ISISC_LED_INIT(rv, dev_id); - ISISC_COSMAP_INIT(rv, dev_id); - ISISC_IP_INIT(rv, dev_id); - ISISC_NAT_INIT(rv, dev_id); - ISISC_TRUNK_INIT(rv, dev_id); - ISISC_SEC_INIT(rv, dev_id); - ISISC_INTERFACE_CTRL_INIT(rv, dev_id); - - { - hsl_api_t *p_api; - - SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id)); - p_api->dev_reset = isisc_reset; - p_api->dev_clean = isisc_cleanup; - } - - SW_RTN_ON_ERROR(isisc_hw_init(dev_id, cfg)); -#if 0 -#if defined(IN_NAT_HELPER) - if(!isisc_nat_global_status) { - ISISC_NAT_HELPER_INIT(rv, dev_id); - isisc_nat_global_status = 1; - } - -#endif -#endif - } -#endif - - return SW_OK; -} - -/** - * @} - */ - diff --git a/feeds/ipq807x/qca-ssdk/src/src/hsl/isisc/isisc_interface_ctrl.c b/feeds/ipq807x/qca-ssdk/src/src/hsl/isisc/isisc_interface_ctrl.c deleted file mode 100755 index 7c45a34ae..000000000 --- a/feeds/ipq807x/qca-ssdk/src/src/hsl/isisc/isisc_interface_ctrl.c +++ /dev/null @@ -1,2324 +0,0 @@ -/* - * Copyright (c) 2012, 2015-2017, The Linux Foundation. All rights reserved. - * Permission to use, copy, modify, and/or distribute this software for - * any purpose with or without fee is hereby granted, provided that the - * above copyright notice and this permission notice appear in all copies. - * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES - * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR - * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES - * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN - * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT - * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. - */ - - -/** - * @defgroup isisc_interface_ctrl ISISC_INTERFACE_CONTROL - * @{ - */ -#include "sw.h" -#include "hsl.h" -#include "hsl_dev.h" -#include "hsl_port_prop.h" -#include "isisc_interface_ctrl.h" -#include "isisc_reg.h" -#include "hsl_phy.h" - -#define ISISC_MAC_0 0 -#define ISISC_MAC_5 5 -#define ISISC_MAC_6 6 - -#define ISISC_PHY_MODE_PHY_ID 4 -#define ISISC_LPI_PORT1_OFFSET 4 -#define ISISC_LPI_BIT_STEP 2 - -/* we need to do more about MAC5/PHY4 connection... */ -#if 0 -static sw_error_t -_isisc_port_mac5_internal_mode(a_uint32_t dev_id, a_bool_t * inter_mode) -{ - sw_error_t rv; - a_uint32_t reg, rgmii, gmii_mac, gmii_phy, mii_mac, mii_phy, sgmii; - - HSL_REG_ENTRY_GET(rv, dev_id, PORT5_PAD_CTRL, 0, - (a_uint8_t *) (®), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - - SW_GET_FIELD_BY_REG(PORT0_PAD_CTRL, MAC0_RGMII_EN, rgmii, reg); - SW_GET_FIELD_BY_REG(PORT0_PAD_CTRL, MAC0_MAC_GMII_EN, gmii_mac, reg); - SW_GET_FIELD_BY_REG(PORT0_PAD_CTRL, MAC0_PHY_GMII_EN, gmii_phy, reg); - SW_GET_FIELD_BY_REG(PORT0_PAD_CTRL, MAC0_MAC_MII_EN, mii_mac, reg); - SW_GET_FIELD_BY_REG(PORT0_PAD_CTRL, MAC0_PHY_MII_EN, mii_phy, reg); - SW_GET_FIELD_BY_REG(PORT0_PAD_CTRL, MAC0_SGMII_EN, sgmii, reg); - - if (rgmii || gmii_mac || gmii_phy || mii_mac || mii_phy || sgmii) - { - *inter_mode = A_FALSE; - } - else - { - *inter_mode = A_TRUE; - } - - return SW_OK; -} - -static sw_error_t -_isisc_port_phy4_internal_mode(a_uint32_t dev_id, a_bool_t * inter_mode) -{ - sw_error_t rv; - a_uint32_t reg, rgmii, gmii, mii; - - HSL_REG_ENTRY_GET(rv, dev_id, PORT6_PAD_CTRL, 0, - (a_uint8_t *) (®), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - - SW_GET_FIELD_BY_REG(PORT6_PAD_CTRL, PHY4_RGMII_EN, rgmii, reg); - SW_GET_FIELD_BY_REG(PORT6_PAD_CTRL, PHY4_GMII_EN, gmii, reg); - SW_GET_FIELD_BY_REG(PORT6_PAD_CTRL, PHY4_MII_EN, mii, reg); - - if (rgmii || gmii || mii) - { - *inter_mode = A_FALSE; - } - else - { - *inter_mode = A_TRUE; - } - - return SW_OK; -} -#endif - -static sw_error_t -_isisc_port_3az_status_set(a_uint32_t dev_id, fal_port_t port_id, a_bool_t enable) -{ - sw_error_t rv; - a_uint32_t reg = 0, field, offset, device_id, rev_id, reverse = 0; - - HSL_REG_ENTRY_GET(rv, dev_id, MASK_CTL, 0, - (a_uint8_t *) (®), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - - SW_GET_FIELD_BY_REG(MASK_CTL, DEVICE_ID, device_id, reg); - if (S17C_DEVICE_ID != device_id) - { - return SW_NOT_SUPPORTED; - } - - SW_GET_FIELD_BY_REG(MASK_CTL, REV_ID, rev_id, reg); - if (S17_REVISION_A == rev_id) - { - reverse = 0; - } - else - { - reverse = 1; - } - - if (rev_id == 0) - { - reverse = 1; - } - else - { - reverse = 0; - } - - if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_PHY)) - { - return SW_BAD_PARAM; - } - - HSL_REG_ENTRY_GET(rv, dev_id, EEE_CTL, 0, - (a_uint8_t *) (®), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - - if (A_TRUE == enable) - { - field = 1; - } - else if (A_FALSE == enable) - { - field = 0; - } - else - { - return SW_BAD_PARAM; - } - - if (reverse) - { - field = (~field) & 0x1UL; - } - - offset = (port_id - 1) * ISISC_LPI_BIT_STEP + ISISC_LPI_PORT1_OFFSET; - reg &= (~(0x1UL << offset)); - reg |= (field << offset); - - HSL_REG_ENTRY_SET(rv, dev_id, EEE_CTL, 0, - (a_uint8_t *) (®), sizeof (a_uint32_t)); - return rv; -} - -static sw_error_t -_isisc_port_3az_status_get(a_uint32_t dev_id, fal_port_t port_id, a_bool_t * enable) -{ - sw_error_t rv; - a_uint32_t reg = 0, field, offset, device_id, rev_id, reverse = 0; - - HSL_REG_ENTRY_GET(rv, dev_id, MASK_CTL, 0, - (a_uint8_t *) (®), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - - SW_GET_FIELD_BY_REG(MASK_CTL, DEVICE_ID, device_id, reg); - if (S17C_DEVICE_ID != device_id) - { - return SW_NOT_SUPPORTED; - } - - SW_GET_FIELD_BY_REG(MASK_CTL, REV_ID, rev_id, reg); - if (S17_REVISION_A == rev_id) - { - reverse = 0; - } - else - { - reverse = 1; - } - - if (rev_id == 0) - { - reverse = 1; - } - else - { - reverse = 0; - } - - if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_PHY)) - { - return SW_BAD_PARAM; - } - - HSL_REG_ENTRY_GET(rv, dev_id, EEE_CTL, 0, - (a_uint8_t *) (®), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - - offset = (port_id - 1) * ISISC_LPI_BIT_STEP + ISISC_LPI_PORT1_OFFSET; - field = (reg >> offset) & 0x1; - - if (reverse) - { - field = (~field) & 0x1UL; - } - - if (field) - { - *enable = A_TRUE; - } - else - { - *enable = A_FALSE; - } - - return SW_OK; -} - -static sw_error_t -_isisc_port_rgmii_mode_set(a_uint32_t dev_id, fal_port_t port_id, fal_mac_rgmii_config_t * config) -{ - sw_error_t rv; - a_uint32_t reg = 0; - - if (ISISC_MAC_0 == port_id) - { - HSL_REG_ENTRY_GET(rv, dev_id, PORT0_PAD_CTRL, 0, - (a_uint8_t *) (®), sizeof (a_uint32_t)); - } - else if (ISISC_MAC_5 == port_id) - { - HSL_REG_ENTRY_GET(rv, dev_id, PORT5_PAD_CTRL, 0, - (a_uint8_t *) (®), sizeof (a_uint32_t)); - } - else if (ISISC_MAC_6 == port_id) - { - HSL_REG_ENTRY_GET(rv, dev_id, PORT6_PAD_CTRL, 0, - (a_uint8_t *) (®), sizeof (a_uint32_t)); - } - else - { - return SW_BAD_PARAM; - } - SW_RTN_ON_ERROR(rv); - - SW_SET_REG_BY_FIELD(PORT0_PAD_CTRL, MAC0_RGMII_EN, 1, reg); - SW_SET_REG_BY_FIELD(PORT0_PAD_CTRL, MAC0_MAC_GMII_EN, 0, reg); - SW_SET_REG_BY_FIELD(PORT0_PAD_CTRL, MAC0_PHY_GMII_EN, 0, reg); - SW_SET_REG_BY_FIELD(PORT0_PAD_CTRL, MAC0_MAC_MII_EN, 0, reg); - SW_SET_REG_BY_FIELD(PORT0_PAD_CTRL, MAC0_PHY_MII_EN, 0, reg); - SW_SET_REG_BY_FIELD(PORT0_PAD_CTRL, MAC0_SGMII_EN, 0, reg); - SW_SET_REG_BY_FIELD(PORT0_PAD_CTRL, RMII_MASTER_EN, 0, reg); - SW_SET_REG_BY_FIELD(PORT0_PAD_CTRL, RMII_SLAVE_EN, 0, reg); - - /* hardware suggestions: restore to defatult settings */ - SW_SET_REG_BY_FIELD(PORT0_PAD_CTRL, MAC0_PHY_GMII_TXCLK_SEL, 0, reg); - SW_SET_REG_BY_FIELD(PORT0_PAD_CTRL, MAC0_PHY_GMII_RXCLK_SEL, 0, reg); - SW_SET_REG_BY_FIELD(PORT0_PAD_CTRL, MAC0_PHY_MII_TXCLK_SEL, 0, reg); - SW_SET_REG_BY_FIELD(PORT0_PAD_CTRL, MAC0_PHY_MII_RXCLK_SEL, 0, reg); - SW_SET_REG_BY_FIELD(PORT0_PAD_CTRL, MAC0_MAC_GMII_TXCLK_SEL, 0, reg); - SW_SET_REG_BY_FIELD(PORT0_PAD_CTRL, MAC0_MAC_GMII_RXCLK_SEL, 0, reg); - SW_SET_REG_BY_FIELD(PORT0_PAD_CTRL, MAC0_MAC_MII_TXCLK_SEL, 0, reg); - SW_SET_REG_BY_FIELD(PORT0_PAD_CTRL, MAC0_MAC_MII_RXCLK_SEL, 0, reg); - - if (A_TRUE == config->txclk_delay_cmd) - { - SW_SET_REG_BY_FIELD(PORT0_PAD_CTRL, MAC0_RGMII_TXCLK_DELAY_EN, 1, reg); - SW_SET_REG_BY_FIELD(PORT0_PAD_CTRL, MAC0_RGMII_TXCLK_DELAY_SEL, config->txclk_delay_sel, reg); - } - else - { - SW_SET_REG_BY_FIELD(PORT0_PAD_CTRL, MAC0_RGMII_TXCLK_DELAY_EN, 0, reg); - SW_SET_REG_BY_FIELD(PORT0_PAD_CTRL, MAC0_RGMII_TXCLK_DELAY_SEL, 0, reg); - } - - if (A_TRUE == config->rxclk_delay_cmd) - { - SW_SET_REG_BY_FIELD(PORT0_PAD_CTRL, MAC0_RGMII_RXCLK_DELAY_EN, 1, reg); - SW_SET_REG_BY_FIELD(PORT0_PAD_CTRL, MAC0_RGMII_RXCLK_DELAY_SEL, config->rxclk_delay_sel, reg); - } - else - { - SW_SET_REG_BY_FIELD(PORT0_PAD_CTRL, MAC0_RGMII_RXCLK_DELAY_EN, 0, reg); - SW_SET_REG_BY_FIELD(PORT0_PAD_CTRL, MAC0_RGMII_RXCLK_DELAY_SEL, 0, reg); - } - - if (ISISC_MAC_0 == port_id) - { - HSL_REG_ENTRY_SET(rv, dev_id, PORT0_PAD_CTRL, 0, - (a_uint8_t *) (®), sizeof (a_uint32_t)); - } - else if (ISISC_MAC_5 == port_id) - { - HSL_REG_ENTRY_SET(rv, dev_id, PORT5_PAD_CTRL, 0, - (a_uint8_t *) (®), sizeof (a_uint32_t)); - } - else - { - HSL_REG_ENTRY_SET(rv, dev_id, PORT6_PAD_CTRL, 0, - (a_uint8_t *) (®), sizeof (a_uint32_t)); - } - SW_RTN_ON_ERROR(rv); - - /* Port status register setting */ - HSL_REG_ENTRY_GET(rv, dev_id, PORT_STATUS, port_id, - (a_uint8_t *) (®), sizeof (a_uint32_t)); - - /* setting port status default configuration */ - SW_SET_REG_BY_FIELD(PORT_STATUS, LINK_EN, 0, reg); - SW_SET_REG_BY_FIELD(PORT_STATUS, FLOW_LINK_EN, 0, reg); - SW_SET_REG_BY_FIELD(PORT_STATUS, RX_FLOW_EN, 1, reg); - SW_SET_REG_BY_FIELD(PORT_STATUS, TX_FLOW_EN, 1, reg); - SW_SET_REG_BY_FIELD(PORT_STATUS, DUPLEX_MODE, 1, reg); - SW_SET_REG_BY_FIELD(PORT_STATUS, RXMAC_EN, 1, reg); - SW_SET_REG_BY_FIELD(PORT_STATUS, TXMAC_EN, 1, reg); - SW_SET_REG_BY_FIELD(PORT_STATUS, SPEED_MODE, 2, reg); - HSL_REG_ENTRY_SET(rv, dev_id, PORT_STATUS, port_id, - (a_uint8_t *) (®), sizeof (a_uint32_t)); - return rv; -} - -static sw_error_t -_isisc_port_rgmii_mode_get(a_uint32_t dev_id, fal_port_t port_id, fal_mac_rgmii_config_t * config) -{ - sw_error_t rv; - a_uint32_t reg = 0, field; - - if (ISISC_MAC_0 == port_id) - { - HSL_REG_ENTRY_GET(rv, dev_id, PORT0_PAD_CTRL, 0, - (a_uint8_t *) (®), sizeof (a_uint32_t)); - } - else if (ISISC_MAC_5 == port_id) - { - HSL_REG_ENTRY_GET(rv, dev_id, PORT5_PAD_CTRL, 0, - (a_uint8_t *) (®), sizeof (a_uint32_t)); - } - else if (ISISC_MAC_6 == port_id) - { - HSL_REG_ENTRY_GET(rv, dev_id, PORT6_PAD_CTRL, 0, - (a_uint8_t *) (®), sizeof (a_uint32_t)); - } - else - { - return SW_BAD_PARAM; - } - SW_RTN_ON_ERROR(rv); - - SW_GET_FIELD_BY_REG(PORT0_PAD_CTRL, MAC0_RGMII_TXCLK_DELAY_EN, field, reg); - if (field) - { - config->txclk_delay_cmd = A_TRUE; - SW_GET_FIELD_BY_REG(PORT0_PAD_CTRL, MAC0_RGMII_TXCLK_DELAY_SEL, field, reg); - config->txclk_delay_sel = field; - } - else - { - config->txclk_delay_cmd = A_FALSE; - config->txclk_delay_sel = 0; - } - - SW_GET_FIELD_BY_REG(PORT0_PAD_CTRL, MAC0_RGMII_RXCLK_DELAY_EN, field, reg); - if (field) - { - config->rxclk_delay_cmd = A_TRUE; - SW_GET_FIELD_BY_REG(PORT0_PAD_CTRL, MAC0_RGMII_RXCLK_DELAY_SEL, field, reg); - config->rxclk_delay_sel = field; - } - else - { - config->rxclk_delay_cmd = A_FALSE; - config->rxclk_delay_sel = 0; - } - - return SW_OK; -} - -static sw_error_t -_isisc_interface_mac06_exch_set(a_uint32_t dev_id, a_bool_t enable) -{ - sw_error_t rv; - a_uint32_t reg = 0; - - - HSL_REG_ENTRY_GET(rv, dev_id, PORT0_PAD_CTRL, 0, - (a_uint8_t *) (®), sizeof (a_uint32_t)); - - SW_RTN_ON_ERROR(rv); - - if (A_TRUE == enable) - { - SW_SET_REG_BY_FIELD(PORT0_PAD_CTRL, RMII_MAC06_EXCH_EN, 1, reg); - } - else - { - SW_SET_REG_BY_FIELD(PORT0_PAD_CTRL, RMII_MAC06_EXCH_EN, 0, reg); - } - - HSL_REG_ENTRY_SET(rv, dev_id, PORT0_PAD_CTRL, 0, - (a_uint8_t *) (®), sizeof (a_uint32_t)); - - return rv; -} - -static sw_error_t -_isisc_interface_mac06_exch_get(a_uint32_t dev_id, a_bool_t* enable) -{ - sw_error_t rv; - a_uint32_t reg = 0,field; - - - HSL_REG_ENTRY_GET(rv, dev_id, PORT0_PAD_CTRL, 0, - (a_uint8_t *) (®), sizeof (a_uint32_t)); - - SW_RTN_ON_ERROR(rv); - - SW_GET_FIELD_BY_REG(PORT0_PAD_CTRL, RMII_MAC06_EXCH_EN, field, reg); - if (field) - { - *enable = A_TRUE; - } - else - { - *enable = A_FALSE; - } - - return rv; -} - - -static sw_error_t -_isisc_interface_mac_sgmii_set(a_uint32_t dev_id,a_uint32_t value) -{ - sw_error_t rv; - a_uint32_t reg; - reg = value; - - HSL_REG_ENTRY_SET(rv, dev_id, SGMII_CTRL, 0, - (a_uint8_t *) (®), sizeof (a_uint32_t)); - - return rv; -} - -static sw_error_t -_isisc_interface_mac_sgmii_get(a_uint32_t dev_id, a_uint32_t *value) -{ - sw_error_t rv; - a_uint32_t reg = 0; - - HSL_REG_ENTRY_GET(rv, dev_id, SGMII_CTRL, 0, - (a_uint8_t *) (®), sizeof (a_uint32_t)); - - SW_RTN_ON_ERROR(rv); - - *value = reg; - - return rv; -} - -static sw_error_t -_isisc_interface_mac_pad_set(a_uint32_t dev_id,a_uint32_t port_num, a_uint32_t value) -{ - sw_error_t rv; - a_uint32_t reg; - - reg = value; - - switch (port_num) - { - case ISISC_MAC_0: - HSL_REG_ENTRY_SET(rv, dev_id, PORT0_PAD_CTRL, 0, - (a_uint8_t *) (®), sizeof (a_uint32_t)); - break; - case ISISC_MAC_5: - HSL_REG_ENTRY_SET(rv, dev_id, PORT5_PAD_CTRL, 0, - (a_uint8_t *) (®), sizeof (a_uint32_t)); - break; - case ISISC_MAC_6: - HSL_REG_ENTRY_SET(rv, dev_id, PORT6_PAD_CTRL, 0, - (a_uint8_t *) (®), sizeof (a_uint32_t)); - break; - default: - return SW_BAD_PARAM; - } - - return rv; -} - -static sw_error_t -_isisc_interface_mac_pad_get(a_uint32_t dev_id,a_uint32_t port_num, a_uint32_t *value) -{ - sw_error_t rv; - a_uint32_t reg = 0; - - switch (port_num) - { - case ISISC_MAC_0: - HSL_REG_ENTRY_GET(rv, dev_id, PORT0_PAD_CTRL, 0, - (a_uint8_t *) (®), sizeof (a_uint32_t)); - break; - case ISISC_MAC_5: - HSL_REG_ENTRY_GET(rv, dev_id, PORT5_PAD_CTRL, 0, - (a_uint8_t *) (®), sizeof (a_uint32_t)); - break; - case ISISC_MAC_6: - HSL_REG_ENTRY_GET(rv, dev_id, PORT6_PAD_CTRL, 0, - (a_uint8_t *) (®), sizeof (a_uint32_t)); - break; - default: - return SW_BAD_PARAM; - } - SW_RTN_ON_ERROR(rv); - - *value = reg; - - return rv; -} - - - -static sw_error_t -_isisc_port_rmii_mode_set(a_uint32_t dev_id, fal_port_t port_id, fal_mac_rmii_config_t * config) -{ - sw_error_t rv; - a_uint32_t reg = 0; - - if (ISISC_MAC_0 == port_id) - { - HSL_REG_ENTRY_GET(rv, dev_id, PORT0_PAD_CTRL, 0, - (a_uint8_t *) (®), sizeof (a_uint32_t)); - } - else - { - return SW_BAD_PARAM; - } - - if (config->master_mode == config->slave_mode) - { - return SW_BAD_PARAM; - } - - SW_RTN_ON_ERROR(rv); - if (A_TRUE == config->master_mode) - { - SW_SET_REG_BY_FIELD(PORT0_PAD_CTRL, RMII_MASTER_EN, 1, reg); - SW_SET_REG_BY_FIELD(PORT0_PAD_CTRL, RMII_SLAVE_EN, 0, reg); - } - else - { - SW_SET_REG_BY_FIELD(PORT0_PAD_CTRL, RMII_MASTER_EN, 0, reg); - SW_SET_REG_BY_FIELD(PORT0_PAD_CTRL, RMII_SLAVE_EN, 1, reg); - } - - SW_SET_REG_BY_FIELD(PORT0_PAD_CTRL, MAC0_RGMII_EN, 0, reg); - SW_SET_REG_BY_FIELD(PORT0_PAD_CTRL, MAC0_MAC_GMII_EN, 0, reg); - SW_SET_REG_BY_FIELD(PORT0_PAD_CTRL, MAC0_PHY_GMII_EN, 0, reg); - SW_SET_REG_BY_FIELD(PORT0_PAD_CTRL, MAC0_MAC_MII_EN, 0, reg); - SW_SET_REG_BY_FIELD(PORT0_PAD_CTRL, MAC0_PHY_MII_EN, 0, reg); - SW_SET_REG_BY_FIELD(PORT0_PAD_CTRL, MAC0_SGMII_EN, 0, reg); - - /* hardware suggestions: restore to defatult settings */ - SW_SET_REG_BY_FIELD(PORT0_PAD_CTRL, MAC0_PHY_GMII_TXCLK_SEL, 0, reg); - SW_SET_REG_BY_FIELD(PORT0_PAD_CTRL, MAC0_PHY_GMII_RXCLK_SEL, 0, reg); - SW_SET_REG_BY_FIELD(PORT0_PAD_CTRL, MAC0_PHY_MII_TXCLK_SEL, 0, reg); - SW_SET_REG_BY_FIELD(PORT0_PAD_CTRL, MAC0_PHY_MII_RXCLK_SEL, 0, reg); - SW_SET_REG_BY_FIELD(PORT0_PAD_CTRL, MAC0_MAC_GMII_TXCLK_SEL, 0, reg); - SW_SET_REG_BY_FIELD(PORT0_PAD_CTRL, MAC0_MAC_GMII_RXCLK_SEL, 0, reg); - SW_SET_REG_BY_FIELD(PORT0_PAD_CTRL, MAC0_MAC_MII_TXCLK_SEL, 0, reg); - SW_SET_REG_BY_FIELD(PORT0_PAD_CTRL, MAC0_MAC_MII_RXCLK_SEL, 0, reg); - - if (A_TRUE == config->clock_inverse) - { - SW_SET_REG_BY_FIELD(PORT0_PAD_CTRL, RMII_SEL, 1, reg); - } - else - { - SW_SET_REG_BY_FIELD(PORT0_PAD_CTRL, RMII_SEL, 0, reg); - } - - if (A_TRUE == config->pipe_rxclk_sel) - { - SW_SET_REG_BY_FIELD(PORT0_PAD_CTRL, RMII_PIPE_RXCLK_SEL, 1, reg); - } - else - { - SW_SET_REG_BY_FIELD(PORT0_PAD_CTRL, RMII_PIPE_RXCLK_SEL, 0, reg); - } - - if (ISISC_MAC_0 == port_id) - { - HSL_REG_ENTRY_SET(rv, dev_id, PORT0_PAD_CTRL, 0, - (a_uint8_t *) (®), sizeof (a_uint32_t)); - } - - SW_RTN_ON_ERROR(rv); - - /* Port status register setting */ - HSL_REG_ENTRY_GET(rv, dev_id, PORT_STATUS, port_id, - (a_uint8_t *) (®), sizeof (a_uint32_t)); - - /* setting port status default configuration */ - SW_SET_REG_BY_FIELD(PORT_STATUS, LINK_EN, 0, reg); - SW_SET_REG_BY_FIELD(PORT_STATUS, FLOW_LINK_EN, 0, reg); - SW_SET_REG_BY_FIELD(PORT_STATUS, RX_FLOW_EN, 1, reg); - SW_SET_REG_BY_FIELD(PORT_STATUS, TX_FLOW_EN, 1, reg); - SW_SET_REG_BY_FIELD(PORT_STATUS, DUPLEX_MODE, 1, reg); - SW_SET_REG_BY_FIELD(PORT_STATUS, RXMAC_EN, 1, reg); - SW_SET_REG_BY_FIELD(PORT_STATUS, TXMAC_EN, 1, reg); - SW_SET_REG_BY_FIELD(PORT_STATUS, SPEED_MODE, 2, reg); - HSL_REG_ENTRY_SET(rv, dev_id, PORT_STATUS, port_id, - (a_uint8_t *) (®), sizeof (a_uint32_t)); - return rv; -} - -static sw_error_t -_isisc_port_rmii_mode_get(a_uint32_t dev_id, fal_port_t port_id, fal_mac_rmii_config_t * config) -{ - sw_error_t rv; - a_uint32_t reg = 0, field; - - if (ISISC_MAC_0 == port_id) - { - HSL_REG_ENTRY_GET(rv, dev_id, PORT0_PAD_CTRL, 0, - (a_uint8_t *) (®), sizeof (a_uint32_t)); - } - else - { - return SW_BAD_PARAM; - } - SW_RTN_ON_ERROR(rv); - - SW_GET_FIELD_BY_REG(PORT0_PAD_CTRL, RMII_MASTER_EN, field, reg); - if (field) - { - config->master_mode = A_TRUE; - } - else - { - config->master_mode = A_FALSE; - } - - SW_GET_FIELD_BY_REG(PORT0_PAD_CTRL, RMII_SLAVE_EN, field, reg); - if (field) - { - config->slave_mode = A_TRUE; - } - else - { - config->slave_mode = A_FALSE; - } - - SW_GET_FIELD_BY_REG(PORT0_PAD_CTRL, RMII_SEL, field, reg); - if (field) - { - config->clock_inverse = A_TRUE; - } - else - { - config->clock_inverse = A_FALSE; - } - - SW_GET_FIELD_BY_REG(PORT0_PAD_CTRL, RMII_PIPE_RXCLK_SEL, field, reg); - if (field) - { - config->pipe_rxclk_sel = A_TRUE; - } - else - { - config->pipe_rxclk_sel = A_FALSE; - } - - - return SW_OK; -} - -static sw_error_t -_isisc_port_gmii_mode_set(a_uint32_t dev_id, fal_port_t port_id, fal_mac_gmii_config_t * config) -{ - sw_error_t rv; - a_uint32_t reg = 0; - - if (ISISC_MAC_0 == port_id) - { - HSL_REG_ENTRY_GET(rv, dev_id, PORT0_PAD_CTRL, 0, - (a_uint8_t *) (®), sizeof (a_uint32_t)); - } - else - { - return SW_BAD_PARAM; - } - SW_RTN_ON_ERROR(rv); - - SW_SET_REG_BY_FIELD(PORT0_PAD_CTRL, MAC0_RGMII_EN, 0, reg); - SW_SET_REG_BY_FIELD(PORT0_PAD_CTRL, MAC0_MAC_MII_EN, 0, reg); - SW_SET_REG_BY_FIELD(PORT0_PAD_CTRL, MAC0_PHY_MII_EN, 0, reg); - SW_SET_REG_BY_FIELD(PORT0_PAD_CTRL, MAC0_SGMII_EN, 0, reg); - SW_SET_REG_BY_FIELD(PORT0_PAD_CTRL, RMII_MASTER_EN, 0, reg); - SW_SET_REG_BY_FIELD(PORT0_PAD_CTRL, RMII_SLAVE_EN, 0, reg); - - /* hardware suggestions: restore to defatult settings */ - SW_SET_REG_BY_FIELD(PORT0_PAD_CTRL, MAC0_RGMII_TXCLK_DELAY_EN, 0, reg); - SW_SET_REG_BY_FIELD(PORT0_PAD_CTRL, MAC0_RGMII_RXCLK_DELAY_EN, 0, reg); - SW_SET_REG_BY_FIELD(PORT0_PAD_CTRL, MAC0_RGMII_TXCLK_DELAY_SEL, 0, reg); - SW_SET_REG_BY_FIELD(PORT0_PAD_CTRL, MAC0_RGMII_RXCLK_DELAY_SEL, 0, reg); - SW_SET_REG_BY_FIELD(PORT0_PAD_CTRL, MAC0_PHY_GMII_TXCLK_SEL, 0, reg); - SW_SET_REG_BY_FIELD(PORT0_PAD_CTRL, MAC0_PHY_GMII_RXCLK_SEL, 0, reg); - SW_SET_REG_BY_FIELD(PORT0_PAD_CTRL, MAC0_PHY_MII_TXCLK_SEL, 0, reg); - SW_SET_REG_BY_FIELD(PORT0_PAD_CTRL, MAC0_PHY_MII_RXCLK_SEL, 0, reg); - SW_SET_REG_BY_FIELD(PORT0_PAD_CTRL, MAC0_MAC_GMII_TXCLK_SEL, 0, reg); - SW_SET_REG_BY_FIELD(PORT0_PAD_CTRL, MAC0_MAC_GMII_RXCLK_SEL, 0, reg); - SW_SET_REG_BY_FIELD(PORT0_PAD_CTRL, MAC0_MAC_MII_TXCLK_SEL, 0, reg); - SW_SET_REG_BY_FIELD(PORT0_PAD_CTRL, MAC0_MAC_MII_RXCLK_SEL, 0, reg); - - if (FAL_INTERFACE_CLOCK_PHY_MODE == config->clock_mode) - { - SW_SET_REG_BY_FIELD(PORT0_PAD_CTRL, MAC0_MAC_GMII_EN, 0, reg); - SW_SET_REG_BY_FIELD(PORT0_PAD_CTRL, MAC0_PHY_GMII_EN, 1, reg); - SW_SET_REG_BY_FIELD(PORT0_PAD_CTRL, MAC0_PHY_GMII_TXCLK_SEL, config->txclk_select, reg); - SW_SET_REG_BY_FIELD(PORT0_PAD_CTRL, MAC0_PHY_GMII_RXCLK_SEL, config->rxclk_select, reg); - - } - else if (FAL_INTERFACE_CLOCK_MAC_MODE == config->clock_mode) - { - SW_SET_REG_BY_FIELD(PORT0_PAD_CTRL, MAC0_MAC_GMII_EN, 1, reg); - SW_SET_REG_BY_FIELD(PORT0_PAD_CTRL, MAC0_PHY_GMII_EN, 0, reg); - SW_SET_REG_BY_FIELD(PORT0_PAD_CTRL, MAC0_MAC_GMII_TXCLK_SEL, config->txclk_select, reg); - SW_SET_REG_BY_FIELD(PORT0_PAD_CTRL, MAC0_MAC_GMII_RXCLK_SEL, config->rxclk_select, reg); - - } - else - { - return SW_BAD_PARAM; - } - - if (ISISC_MAC_0 == port_id) - { - HSL_REG_ENTRY_SET(rv, dev_id, PORT0_PAD_CTRL, 0, - (a_uint8_t *) (®), sizeof (a_uint32_t)); - } - else - { - HSL_REG_ENTRY_SET(rv, dev_id, PORT6_PAD_CTRL, 0, - (a_uint8_t *) (®), sizeof (a_uint32_t)); - } - SW_RTN_ON_ERROR(rv); - - /* Port status register setting */ - HSL_REG_ENTRY_GET(rv, dev_id, PORT_STATUS, port_id, - (a_uint8_t *) (®), sizeof (a_uint32_t)); - - /* setting port status default configuration */ - SW_SET_REG_BY_FIELD(PORT_STATUS, LINK_EN, 0, reg); - SW_SET_REG_BY_FIELD(PORT_STATUS, FLOW_LINK_EN, 0, reg); - SW_SET_REG_BY_FIELD(PORT_STATUS, RX_FLOW_EN, 1, reg); - SW_SET_REG_BY_FIELD(PORT_STATUS, TX_FLOW_EN, 1, reg); - SW_SET_REG_BY_FIELD(PORT_STATUS, DUPLEX_MODE, 1, reg); - SW_SET_REG_BY_FIELD(PORT_STATUS, RXMAC_EN, 1, reg); - SW_SET_REG_BY_FIELD(PORT_STATUS, TXMAC_EN, 1, reg); - SW_SET_REG_BY_FIELD(PORT_STATUS, SPEED_MODE, 2, reg); - HSL_REG_ENTRY_SET(rv, dev_id, PORT_STATUS, port_id, - (a_uint8_t *) (®), sizeof (a_uint32_t)); - return rv; -} - -static sw_error_t -_isisc_port_gmii_mode_get(a_uint32_t dev_id, fal_port_t port_id, fal_mac_gmii_config_t * config) -{ - sw_error_t rv; - a_uint32_t reg = 0, field; - - if (ISISC_MAC_0 == port_id) - { - HSL_REG_ENTRY_GET(rv, dev_id, PORT0_PAD_CTRL, 0, - (a_uint8_t *) (®), sizeof (a_uint32_t)); - } - else if (ISISC_MAC_6 == port_id) - { - HSL_REG_ENTRY_GET(rv, dev_id, PORT6_PAD_CTRL, 0, - (a_uint8_t *) (®), sizeof (a_uint32_t)); - } - else - { - return SW_BAD_PARAM; - } - SW_RTN_ON_ERROR(rv); - - SW_GET_FIELD_BY_REG(PORT0_PAD_CTRL, MAC0_PHY_GMII_EN, field, reg); - if (field) - { - config->clock_mode = FAL_INTERFACE_CLOCK_PHY_MODE; - SW_GET_FIELD_BY_REG(PORT0_PAD_CTRL, MAC0_PHY_GMII_TXCLK_SEL, field, reg); - config->txclk_select = field; - SW_GET_FIELD_BY_REG(PORT0_PAD_CTRL, MAC0_PHY_GMII_RXCLK_SEL, field, reg); - config->rxclk_select = field; - - } - else - { - config->clock_mode = FAL_INTERFACE_CLOCK_MAC_MODE; - SW_GET_FIELD_BY_REG(PORT0_PAD_CTRL, MAC0_MAC_GMII_TXCLK_SEL, field, reg); - config->txclk_select = field; - SW_GET_FIELD_BY_REG(PORT0_PAD_CTRL, MAC0_MAC_GMII_RXCLK_SEL, field, reg); - config->rxclk_select = field; - } - - return SW_OK; -} - -static sw_error_t -_isisc_port_mii_mode_set(a_uint32_t dev_id, fal_port_t port_id, fal_mac_mii_config_t * config) -{ - sw_error_t rv; - a_uint32_t reg = 0; - - if (ISISC_MAC_0 == port_id) - { - HSL_REG_ENTRY_GET(rv, dev_id, PORT0_PAD_CTRL, 0, - (a_uint8_t *) (®), sizeof (a_uint32_t)); - } - else if (ISISC_MAC_5 == port_id) - { - HSL_REG_ENTRY_GET(rv, dev_id, PORT5_PAD_CTRL, 0, - (a_uint8_t *) (®), sizeof (a_uint32_t)); - } - else if (ISISC_MAC_6 == port_id) - { - HSL_REG_ENTRY_GET(rv, dev_id, PORT6_PAD_CTRL, 0, - (a_uint8_t *) (®), sizeof (a_uint32_t)); - } - else - { - return SW_BAD_PARAM; - } - SW_RTN_ON_ERROR(rv); - - SW_SET_REG_BY_FIELD(PORT0_PAD_CTRL, MAC0_RGMII_EN, 0, reg); - SW_SET_REG_BY_FIELD(PORT0_PAD_CTRL, MAC0_MAC_GMII_EN, 0, reg); - SW_SET_REG_BY_FIELD(PORT0_PAD_CTRL, MAC0_PHY_GMII_EN, 0, reg); - SW_SET_REG_BY_FIELD(PORT0_PAD_CTRL, MAC0_SGMII_EN, 0, reg); - SW_SET_REG_BY_FIELD(PORT0_PAD_CTRL, RMII_MASTER_EN, 0, reg); - SW_SET_REG_BY_FIELD(PORT0_PAD_CTRL, RMII_SLAVE_EN, 0, reg); - - /* hardware suggestions: restore to defatult settings */ - SW_SET_REG_BY_FIELD(PORT0_PAD_CTRL, MAC0_RGMII_TXCLK_DELAY_EN, 0, reg); - SW_SET_REG_BY_FIELD(PORT0_PAD_CTRL, MAC0_RGMII_RXCLK_DELAY_EN, 0, reg); - SW_SET_REG_BY_FIELD(PORT0_PAD_CTRL, MAC0_RGMII_TXCLK_DELAY_SEL, 0, reg); - SW_SET_REG_BY_FIELD(PORT0_PAD_CTRL, MAC0_RGMII_RXCLK_DELAY_SEL, 0, reg); - SW_SET_REG_BY_FIELD(PORT0_PAD_CTRL, MAC0_PHY_GMII_TXCLK_SEL, 0, reg); - SW_SET_REG_BY_FIELD(PORT0_PAD_CTRL, MAC0_PHY_GMII_RXCLK_SEL, 0, reg); - SW_SET_REG_BY_FIELD(PORT0_PAD_CTRL, MAC0_PHY_MII_TXCLK_SEL, 0, reg); - SW_SET_REG_BY_FIELD(PORT0_PAD_CTRL, MAC0_PHY_MII_RXCLK_SEL, 0, reg); - SW_SET_REG_BY_FIELD(PORT0_PAD_CTRL, MAC0_MAC_GMII_TXCLK_SEL, 0, reg); - SW_SET_REG_BY_FIELD(PORT0_PAD_CTRL, MAC0_MAC_GMII_RXCLK_SEL, 0, reg); - SW_SET_REG_BY_FIELD(PORT0_PAD_CTRL, MAC0_MAC_MII_TXCLK_SEL, 0, reg); - SW_SET_REG_BY_FIELD(PORT0_PAD_CTRL, MAC0_MAC_MII_RXCLK_SEL, 0, reg); - - if (FAL_INTERFACE_CLOCK_PHY_MODE == config->clock_mode) - { - SW_SET_REG_BY_FIELD(PORT0_PAD_CTRL, MAC0_MAC_MII_EN, 0, reg); - SW_SET_REG_BY_FIELD(PORT0_PAD_CTRL, MAC0_PHY_MII_EN, 1, reg); - SW_SET_REG_BY_FIELD(PORT0_PAD_CTRL, MAC0_PHY_MII_TXCLK_SEL, config->txclk_select, reg); - SW_SET_REG_BY_FIELD(PORT0_PAD_CTRL, MAC0_PHY_MII_RXCLK_SEL, config->rxclk_select, reg); - } - else if (FAL_INTERFACE_CLOCK_MAC_MODE == config->clock_mode) - { - SW_SET_REG_BY_FIELD(PORT0_PAD_CTRL, MAC0_MAC_MII_EN, 1, reg); - SW_SET_REG_BY_FIELD(PORT0_PAD_CTRL, MAC0_PHY_MII_EN, 0, reg); - SW_SET_REG_BY_FIELD(PORT0_PAD_CTRL, MAC0_MAC_MII_TXCLK_SEL, config->txclk_select, reg); - SW_SET_REG_BY_FIELD(PORT0_PAD_CTRL, MAC0_MAC_MII_RXCLK_SEL, config->rxclk_select, reg); - } - else - { - return SW_BAD_PARAM; - } - - if (ISISC_MAC_0 == port_id) - { - HSL_REG_ENTRY_SET(rv, dev_id, PORT0_PAD_CTRL, 0, - (a_uint8_t *) (®), sizeof (a_uint32_t)); - } - else if (ISISC_MAC_5 == port_id) - { - HSL_REG_ENTRY_SET(rv, dev_id, PORT5_PAD_CTRL, 0, - (a_uint8_t *) (®), sizeof (a_uint32_t)); - } - else - { - HSL_REG_ENTRY_SET(rv, dev_id, PORT6_PAD_CTRL, 0, - (a_uint8_t *) (®), sizeof (a_uint32_t)); - } - SW_RTN_ON_ERROR(rv); - - /* Port status register setting */ - HSL_REG_ENTRY_GET(rv, dev_id, PORT_STATUS, port_id, - (a_uint8_t *) (®), sizeof (a_uint32_t)); - - /* setting port status default configuration */ - SW_SET_REG_BY_FIELD(PORT_STATUS, LINK_EN, 0, reg); - SW_SET_REG_BY_FIELD(PORT_STATUS, FLOW_LINK_EN, 0, reg); - SW_SET_REG_BY_FIELD(PORT_STATUS, RX_FLOW_EN, 1, reg); - SW_SET_REG_BY_FIELD(PORT_STATUS, TX_FLOW_EN, 1, reg); - SW_SET_REG_BY_FIELD(PORT_STATUS, DUPLEX_MODE, 1, reg); - SW_SET_REG_BY_FIELD(PORT_STATUS, RXMAC_EN, 1, reg); - SW_SET_REG_BY_FIELD(PORT_STATUS, TXMAC_EN, 1, reg); - SW_SET_REG_BY_FIELD(PORT_STATUS, SPEED_MODE, 1, reg); - HSL_REG_ENTRY_SET(rv, dev_id, PORT_STATUS, port_id, - (a_uint8_t *) (®), sizeof (a_uint32_t)); - return rv; -} - -static sw_error_t -_isisc_port_mii_mode_get(a_uint32_t dev_id, fal_port_t port_id, fal_mac_mii_config_t * config) -{ - sw_error_t rv; - a_uint32_t reg = 0, field; - - if (ISISC_MAC_0 == port_id) - { - HSL_REG_ENTRY_GET(rv, dev_id, PORT0_PAD_CTRL, 0, - (a_uint8_t *) (®), sizeof (a_uint32_t)); - } - else if (ISISC_MAC_5 == port_id) - { - HSL_REG_ENTRY_GET(rv, dev_id, PORT5_PAD_CTRL, 0, - (a_uint8_t *) (®), sizeof (a_uint32_t)); - } - else if (ISISC_MAC_6 == port_id) - { - HSL_REG_ENTRY_GET(rv, dev_id, PORT6_PAD_CTRL, 0, - (a_uint8_t *) (®), sizeof (a_uint32_t)); - } - else - { - return SW_BAD_PARAM; - } - SW_RTN_ON_ERROR(rv); - - SW_GET_FIELD_BY_REG(PORT0_PAD_CTRL, MAC0_PHY_MII_EN, field, reg); - if (field) - { - config->clock_mode = FAL_INTERFACE_CLOCK_PHY_MODE; - SW_GET_FIELD_BY_REG(PORT0_PAD_CTRL, MAC0_PHY_MII_TXCLK_SEL, field, reg); - config->txclk_select = field; - SW_GET_FIELD_BY_REG(PORT0_PAD_CTRL, MAC0_PHY_MII_RXCLK_SEL, field, reg); - config->rxclk_select = field; - } - else - { - config->clock_mode = FAL_INTERFACE_CLOCK_MAC_MODE; - SW_GET_FIELD_BY_REG(PORT0_PAD_CTRL, MAC0_MAC_MII_TXCLK_SEL, field, reg); - config->txclk_select = field; - SW_GET_FIELD_BY_REG(PORT0_PAD_CTRL, MAC0_MAC_MII_RXCLK_SEL, field, reg); - config->rxclk_select = field; - } - - return SW_OK; -} - -static sw_error_t -_isisc_port_sgmii_mode_set(a_uint32_t dev_id, fal_port_t port_id, fal_mac_sgmii_config_t * config) -{ - sw_error_t rv; - a_uint32_t reg = 0, field; - - if (ISISC_MAC_0 == port_id) - { - HSL_REG_ENTRY_GET(rv, dev_id, PORT0_PAD_CTRL, 0, - (a_uint8_t *) (®), sizeof (a_uint32_t)); - } - else if (ISISC_MAC_6 == port_id) - { - HSL_REG_ENTRY_GET(rv, dev_id, PORT6_PAD_CTRL, 0, - (a_uint8_t *) (®), sizeof (a_uint32_t)); - } - else - { - return SW_BAD_PARAM; - } - SW_RTN_ON_ERROR(rv); - - SW_SET_REG_BY_FIELD(PORT0_PAD_CTRL, MAC0_RGMII_EN, 0, reg); - SW_SET_REG_BY_FIELD(PORT0_PAD_CTRL, MAC0_MAC_GMII_EN, 0, reg); - SW_SET_REG_BY_FIELD(PORT0_PAD_CTRL, MAC0_PHY_GMII_EN, 0, reg); - SW_SET_REG_BY_FIELD(PORT0_PAD_CTRL, MAC0_MAC_MII_EN, 0, reg); - SW_SET_REG_BY_FIELD(PORT0_PAD_CTRL, MAC0_PHY_MII_EN, 0, reg); - SW_SET_REG_BY_FIELD(PORT0_PAD_CTRL, MAC0_SGMII_EN, 1, reg); - SW_SET_REG_BY_FIELD(PORT0_PAD_CTRL, RMII_MASTER_EN, 0, reg); - SW_SET_REG_BY_FIELD(PORT0_PAD_CTRL, RMII_SLAVE_EN, 0, reg); - - /* hardware suggestions: restore to defatult settings */ - SW_SET_REG_BY_FIELD(PORT0_PAD_CTRL, MAC0_RGMII_TXCLK_DELAY_EN, 0, reg); - SW_SET_REG_BY_FIELD(PORT0_PAD_CTRL, MAC0_RGMII_RXCLK_DELAY_EN, 0, reg); - SW_SET_REG_BY_FIELD(PORT0_PAD_CTRL, MAC0_RGMII_TXCLK_DELAY_SEL, 0, reg); - SW_SET_REG_BY_FIELD(PORT0_PAD_CTRL, MAC0_RGMII_RXCLK_DELAY_SEL, 0, reg); - SW_SET_REG_BY_FIELD(PORT0_PAD_CTRL, MAC0_PHY_GMII_TXCLK_SEL, 0, reg); - SW_SET_REG_BY_FIELD(PORT0_PAD_CTRL, MAC0_PHY_GMII_RXCLK_SEL, 0, reg); - SW_SET_REG_BY_FIELD(PORT0_PAD_CTRL, MAC0_PHY_MII_TXCLK_SEL, 0, reg); - SW_SET_REG_BY_FIELD(PORT0_PAD_CTRL, MAC0_PHY_MII_RXCLK_SEL, 0, reg); - SW_SET_REG_BY_FIELD(PORT0_PAD_CTRL, MAC0_MAC_GMII_TXCLK_SEL, 0, reg); - SW_SET_REG_BY_FIELD(PORT0_PAD_CTRL, MAC0_MAC_GMII_RXCLK_SEL, 0, reg); - SW_SET_REG_BY_FIELD(PORT0_PAD_CTRL, MAC0_MAC_MII_TXCLK_SEL, 0, reg); - SW_SET_REG_BY_FIELD(PORT0_PAD_CTRL, MAC0_MAC_MII_RXCLK_SEL, 0, reg); - - - if (A_TRUE == config->force_speed) - { - SW_SET_REG_BY_FIELD(PORT0_PAD_CTRL, MAC0_MAC_SGMII_FORCE_SPEED, 1, reg); - } - else - { - SW_SET_REG_BY_FIELD(PORT0_PAD_CTRL, MAC0_MAC_SGMII_FORCE_SPEED, 0, reg); - } - - if (A_TRUE == config->prbs_enable) - { - SW_SET_REG_BY_FIELD(PORT0_PAD_CTRL, SGMII_PRBS_BERT_EN, 1, reg); - } - else - { - SW_SET_REG_BY_FIELD(PORT0_PAD_CTRL, SGMII_PRBS_BERT_EN, 0, reg); - } - - if (A_TRUE == config->rem_phy_lpbk) - { - SW_SET_REG_BY_FIELD(PORT0_PAD_CTRL, SGMII_REM_PHY_LPBK_EN, 1, reg); - } - else - { - SW_SET_REG_BY_FIELD(PORT0_PAD_CTRL, SGMII_REM_PHY_LPBK_EN, 0, reg); - } - - if (ISISC_MAC_0 == port_id) - { - HSL_REG_ENTRY_SET(rv, dev_id, PORT0_PAD_CTRL, 0, - (a_uint8_t *) (®), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - - /* only support one SGMII interface, so we need to disable another SGMII */ - field = 0; - HSL_REG_FIELD_SET(rv, dev_id, PORT6_PAD_CTRL, port_id, MAC6_SGMII_EN, - (a_uint8_t *) (&field), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - } - else - { - HSL_REG_ENTRY_SET(rv, dev_id, PORT6_PAD_CTRL, 0, - (a_uint8_t *) (®), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - - /* only support one SGMII interface, so we need to disable another SGMII */ - field = 0; - HSL_REG_FIELD_SET(rv, dev_id, PORT0_PAD_CTRL, port_id, MAC0_SGMII_EN, - (a_uint8_t *) (&field), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - } - - /* SGMII global settings, for all SGMII interfaces, now we fix all the values */ - /* TX/RX clock setting */ - HSL_REG_ENTRY_GET(rv, dev_id, PORT0_PAD_CTRL, 0, - (a_uint8_t *) (®), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - - SW_SET_REG_BY_FIELD(PORT0_PAD_CTRL, SGMII_CLK125M_RX_SEL, 1, reg); - SW_SET_REG_BY_FIELD(PORT0_PAD_CTRL, SGMII_CLK125M_TX_SEL, 0, reg); - - HSL_REG_ENTRY_SET(rv, dev_id, PORT0_PAD_CTRL, 0, - (a_uint8_t *) (®), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - - /* SGMII control register setting */ - HSL_REG_ENTRY_GET(rv, dev_id, SGMII_CTRL, 0, - (a_uint8_t *) (®), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - - SW_SET_REG_BY_FIELD(SGMII_CTRL, SGMII_FIBER_MODE, 0, reg); - SW_SET_REG_BY_FIELD(SGMII_CTRL, SGMII_EN_PLL, 1, reg); - SW_SET_REG_BY_FIELD(SGMII_CTRL, SGMII_EN_RX, 1, reg); - SW_SET_REG_BY_FIELD(SGMII_CTRL, SGMII_EN_TX, 1, reg); - SW_SET_REG_BY_FIELD(SGMII_CTRL, SGMII_EN_SD, 1, reg); - if (FAL_INTERFACE_CLOCK_PHY_MODE == config->clock_mode) - { - SW_SET_REG_BY_FIELD(SGMII_CTRL, MODE_CTRL_25M, 1, reg); - } - else - { - SW_SET_REG_BY_FIELD(SGMII_CTRL, MODE_CTRL_25M, 2, reg); - } - HSL_REG_ENTRY_SET(rv, dev_id, SGMII_CTRL, 0, - (a_uint8_t *) (®), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - - /* Port status register setting */ - HSL_REG_ENTRY_GET(rv, dev_id, PORT_STATUS, port_id, - (a_uint8_t *) (®), sizeof (a_uint32_t)); - - /* setting port status default configuration */ - SW_SET_REG_BY_FIELD(PORT_STATUS, FLOW_LINK_EN, 0, reg); - SW_SET_REG_BY_FIELD(PORT_STATUS, RX_FLOW_EN, 1, reg); - SW_SET_REG_BY_FIELD(PORT_STATUS, TX_FLOW_EN, 1, reg); - SW_SET_REG_BY_FIELD(PORT_STATUS, DUPLEX_MODE, 1, reg); - SW_SET_REG_BY_FIELD(PORT_STATUS, RXMAC_EN, 1, reg); - SW_SET_REG_BY_FIELD(PORT_STATUS, TXMAC_EN, 1, reg); - SW_SET_REG_BY_FIELD(PORT_STATUS, SPEED_MODE, 2, reg); - if (A_TRUE == config->auto_neg) - { - SW_SET_REG_BY_FIELD(PORT_STATUS, LINK_EN, 1, reg); - } - else - { - SW_SET_REG_BY_FIELD(PORT_STATUS, LINK_EN, 0, reg); - } - - HSL_REG_ENTRY_SET(rv, dev_id, PORT_STATUS, port_id, - (a_uint8_t *) (®), sizeof (a_uint32_t)); - return rv; -} - -static sw_error_t -_isisc_port_sgmii_mode_get(a_uint32_t dev_id, fal_port_t port_id, fal_mac_sgmii_config_t * config) -{ - sw_error_t rv; - a_uint32_t reg = 0, field; - - if (ISISC_MAC_0 == port_id) - { - /* nothing to do */ - } - else if (ISISC_MAC_6 == port_id) - { - /* nothing to do */ - } - else - { - return SW_BAD_PARAM; - } - - HSL_REG_ENTRY_GET(rv, dev_id, PORT_STATUS, port_id, - (a_uint8_t *) (®), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - - SW_GET_FIELD_BY_REG(PORT_STATUS, LINK_EN, field, reg); - if (field) - { - config->auto_neg = A_TRUE; - } - else - { - config->auto_neg = A_FALSE; - } - - HSL_REG_ENTRY_GET(rv, dev_id, SGMII_CTRL, 0, - (a_uint8_t *) (®), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - SW_GET_FIELD_BY_REG(SGMII_CTRL, MODE_CTRL_25M, field, reg); - if (1 == field) - { - config->clock_mode = FAL_INTERFACE_CLOCK_PHY_MODE; - } - else - { - config->clock_mode = FAL_INTERFACE_CLOCK_MAC_MODE; - } - HSL_REG_ENTRY_GET(rv, dev_id, PORT0_PAD_CTRL, 0, - (a_uint8_t *) (®), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - SW_GET_FIELD_BY_REG(PORT0_PAD_CTRL, SGMII_PRBS_BERT_EN, field, reg); - if (1 == field) - { - config->prbs_enable = A_TRUE; - } - else - { - config->prbs_enable = A_FALSE; - } - - SW_GET_FIELD_BY_REG(PORT0_PAD_CTRL, SGMII_REM_PHY_LPBK_EN, field, reg); - if (1 == field) - { - config->rem_phy_lpbk = A_TRUE; - } - else - { - config->rem_phy_lpbk = A_FALSE; - } - - return SW_OK; -} - -static sw_error_t -_isisc_port_fiber_mode_set(a_uint32_t dev_id, fal_port_t port_id, fal_mac_fiber_config_t * config) -{ - sw_error_t rv; - a_uint32_t reg = 0, field; - - if (ISISC_MAC_0 == port_id) - { - HSL_REG_ENTRY_GET(rv, dev_id, PORT0_PAD_CTRL, 0, - (a_uint8_t *) (®), sizeof (a_uint32_t)); - } - else if (ISISC_MAC_6 == port_id) - { - HSL_REG_ENTRY_GET(rv, dev_id, PORT6_PAD_CTRL, 0, - (a_uint8_t *) (®), sizeof (a_uint32_t)); - } - else - { - return SW_BAD_PARAM; - } - SW_RTN_ON_ERROR(rv); - - SW_SET_REG_BY_FIELD(PORT0_PAD_CTRL, MAC0_RGMII_EN, 0, reg); - SW_SET_REG_BY_FIELD(PORT0_PAD_CTRL, MAC0_MAC_GMII_EN, 0, reg); - SW_SET_REG_BY_FIELD(PORT0_PAD_CTRL, MAC0_PHY_GMII_EN, 0, reg); - SW_SET_REG_BY_FIELD(PORT0_PAD_CTRL, MAC0_MAC_MII_EN, 0, reg); - SW_SET_REG_BY_FIELD(PORT0_PAD_CTRL, MAC0_PHY_MII_EN, 0, reg); - SW_SET_REG_BY_FIELD(PORT0_PAD_CTRL, MAC0_SGMII_EN, 1, reg); - SW_SET_REG_BY_FIELD(PORT0_PAD_CTRL, RMII_MASTER_EN, 0, reg); - SW_SET_REG_BY_FIELD(PORT0_PAD_CTRL, RMII_SLAVE_EN, 0, reg); - - /* hardware suggestions: restore to defatult settings */ - SW_SET_REG_BY_FIELD(PORT0_PAD_CTRL, MAC0_RGMII_TXCLK_DELAY_EN, 0, reg); - SW_SET_REG_BY_FIELD(PORT0_PAD_CTRL, MAC0_RGMII_RXCLK_DELAY_EN, 0, reg); - SW_SET_REG_BY_FIELD(PORT0_PAD_CTRL, MAC0_RGMII_TXCLK_DELAY_SEL, 0, reg); - SW_SET_REG_BY_FIELD(PORT0_PAD_CTRL, MAC0_RGMII_RXCLK_DELAY_SEL, 0, reg); - SW_SET_REG_BY_FIELD(PORT0_PAD_CTRL, MAC0_PHY_GMII_TXCLK_SEL, 0, reg); - SW_SET_REG_BY_FIELD(PORT0_PAD_CTRL, MAC0_PHY_GMII_RXCLK_SEL, 0, reg); - SW_SET_REG_BY_FIELD(PORT0_PAD_CTRL, MAC0_PHY_MII_TXCLK_SEL, 0, reg); - SW_SET_REG_BY_FIELD(PORT0_PAD_CTRL, MAC0_PHY_MII_RXCLK_SEL, 0, reg); - SW_SET_REG_BY_FIELD(PORT0_PAD_CTRL, MAC0_MAC_GMII_TXCLK_SEL, 0, reg); - SW_SET_REG_BY_FIELD(PORT0_PAD_CTRL, MAC0_MAC_GMII_RXCLK_SEL, 0, reg); - SW_SET_REG_BY_FIELD(PORT0_PAD_CTRL, MAC0_MAC_MII_TXCLK_SEL, 0, reg); - SW_SET_REG_BY_FIELD(PORT0_PAD_CTRL, MAC0_MAC_MII_RXCLK_SEL, 0, reg); - - if (ISISC_MAC_0 == port_id) - { - HSL_REG_ENTRY_SET(rv, dev_id, PORT0_PAD_CTRL, 0, - (a_uint8_t *) (®), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - - /* only support one SGMII interface, so we need to disable another SGMII */ - field = 0; - HSL_REG_FIELD_SET(rv, dev_id, PORT6_PAD_CTRL, port_id, MAC6_SGMII_EN, - (a_uint8_t *) (&field), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - } - else - { - HSL_REG_ENTRY_SET(rv, dev_id, PORT6_PAD_CTRL, 0, - (a_uint8_t *) (®), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - - /* only support one SGMII interface, so we need to disable another SGMII */ - field = 0; - HSL_REG_FIELD_SET(rv, dev_id, PORT0_PAD_CTRL, port_id, MAC0_SGMII_EN, - (a_uint8_t *) (&field), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - } - - /* SGMII global settings, for all SGMII interfaces, now we fix all the values */ - /* TX/RX clock setting */ - HSL_REG_ENTRY_GET(rv, dev_id, PORT0_PAD_CTRL, 0, - (a_uint8_t *) (®), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - - SW_SET_REG_BY_FIELD(PORT0_PAD_CTRL, SGMII_CLK125M_RX_SEL, 1, reg); - SW_SET_REG_BY_FIELD(PORT0_PAD_CTRL, SGMII_CLK125M_TX_SEL, 0, reg); - - if (A_TRUE == config->fx100_enable) - { - SW_SET_REG_BY_FIELD(PORT0_PAD_CTRL, SGMII_FX100_EN, 1, reg); - } - else - { - SW_SET_REG_BY_FIELD(PORT0_PAD_CTRL, SGMII_FX100_EN, 0, reg); - } - - HSL_REG_ENTRY_SET(rv, dev_id, PORT0_PAD_CTRL, 0, - (a_uint8_t *) (®), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - - /* SGMII control register setting */ - HSL_REG_ENTRY_GET(rv, dev_id, SGMII_CTRL, 0, - (a_uint8_t *) (®), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - - SW_SET_REG_BY_FIELD(SGMII_CTRL, MODE_CTRL_25M, 0, reg); - SW_SET_REG_BY_FIELD(SGMII_CTRL, SGMII_FIBER_MODE, 3, reg); - SW_SET_REG_BY_FIELD(SGMII_CTRL, SGMII_EN_PLL, 1, reg); - SW_SET_REG_BY_FIELD(SGMII_CTRL, SGMII_EN_RX, 1, reg); - SW_SET_REG_BY_FIELD(SGMII_CTRL, SGMII_EN_TX, 1, reg); - SW_SET_REG_BY_FIELD(SGMII_CTRL, SGMII_EN_SD, 1, reg); - - HSL_REG_ENTRY_SET(rv, dev_id, SGMII_CTRL, 0, - (a_uint8_t *) (®), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - - /* Power on strip register setting */ - HSL_REG_ENTRY_GET(rv, dev_id, POWER_STRIP, 0, - (a_uint8_t *) (®), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - if (A_TRUE == config->auto_neg) - { - SW_SET_REG_BY_FIELD(POWER_STRIP, SERDES_AN_EN, 1, reg); - } - else - { - SW_SET_REG_BY_FIELD(POWER_STRIP, SERDES_AN_EN, 0, reg); - } - HSL_REG_ENTRY_SET(rv, dev_id, POWER_STRIP, 0, - (a_uint8_t *) (®), sizeof (a_uint32_t)); - - /* Port status register setting */ - HSL_REG_ENTRY_GET(rv, dev_id, PORT_STATUS, port_id, - (a_uint8_t *) (®), sizeof (a_uint32_t)); - - /* setting port status default configuration */ - SW_SET_REG_BY_FIELD(PORT_STATUS, FLOW_LINK_EN, 0, reg); - SW_SET_REG_BY_FIELD(PORT_STATUS, LINK_EN, 0, reg); - SW_SET_REG_BY_FIELD(PORT_STATUS, RX_FLOW_EN, 1, reg); - SW_SET_REG_BY_FIELD(PORT_STATUS, TX_FLOW_EN, 1, reg); - SW_SET_REG_BY_FIELD(PORT_STATUS, DUPLEX_MODE, 1, reg); - SW_SET_REG_BY_FIELD(PORT_STATUS, RXMAC_EN, 1, reg); - SW_SET_REG_BY_FIELD(PORT_STATUS, TXMAC_EN, 1, reg); - SW_SET_REG_BY_FIELD(PORT_STATUS, SPEED_MODE, 2, reg); - if (A_TRUE == config->auto_neg) - { - SW_SET_REG_BY_FIELD(PORT_STATUS, LINK_EN, 1, reg); - } - else - { - SW_SET_REG_BY_FIELD(PORT_STATUS, LINK_EN, 0, reg); - } - - HSL_REG_ENTRY_SET(rv, dev_id, PORT_STATUS, port_id, - (a_uint8_t *) (®), sizeof (a_uint32_t)); - return rv; -} - -static sw_error_t -_isisc_port_fiber_mode_get(a_uint32_t dev_id, fal_port_t port_id, fal_mac_fiber_config_t * config) -{ - sw_error_t rv; - a_uint32_t reg = 0, field; - - if (ISISC_MAC_0 == port_id) - { - /* nothing to do */ - } - else if (ISISC_MAC_6 == port_id) - { - /* nothing to do */ - } - else - { - return SW_BAD_PARAM; - } - - HSL_REG_ENTRY_GET(rv, dev_id, POWER_STRIP, 0, - (a_uint8_t *) (®), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - - SW_GET_FIELD_BY_REG(POWER_STRIP, SERDES_AN_EN, field, reg); - if (field) - { - config->auto_neg = A_TRUE; - } - else - { - config->auto_neg = A_FALSE; - } - - HSL_REG_ENTRY_GET(rv, dev_id, PORT0_PAD_CTRL, 0, - (a_uint8_t *) (®), sizeof (a_uint32_t)); - - SW_GET_FIELD_BY_REG(PORT0_PAD_CTRL, SGMII_FX100_EN, field, reg); - - if (field) - { - config->fx100_enable = A_TRUE; - } - else - { - config->fx100_enable = A_FALSE; - } - - return SW_OK; -} - -static sw_error_t -_isisc_port_default_mode_set(a_uint32_t dev_id, fal_port_t port_id) -{ - sw_error_t rv; - a_uint32_t reg = 0; - - if (ISISC_MAC_0 == port_id) - { - HSL_REG_ENTRY_GET(rv, dev_id, PORT0_PAD_CTRL, 0, - (a_uint8_t *) (®), sizeof (a_uint32_t)); - } - else if (ISISC_MAC_5 == port_id) - { - HSL_REG_ENTRY_GET(rv, dev_id, PORT5_PAD_CTRL, 0, - (a_uint8_t *) (®), sizeof (a_uint32_t)); - } - else if (ISISC_MAC_6 == port_id) - { - HSL_REG_ENTRY_GET(rv, dev_id, PORT6_PAD_CTRL, 0, - (a_uint8_t *) (®), sizeof (a_uint32_t)); - } - else - { - return SW_BAD_PARAM; - } - SW_RTN_ON_ERROR(rv); - - SW_SET_REG_BY_FIELD(PORT0_PAD_CTRL, MAC0_RGMII_EN, 0, reg); - SW_SET_REG_BY_FIELD(PORT0_PAD_CTRL, MAC0_MAC_GMII_EN, 0, reg); - SW_SET_REG_BY_FIELD(PORT0_PAD_CTRL, MAC0_PHY_GMII_EN, 0, reg); - SW_SET_REG_BY_FIELD(PORT0_PAD_CTRL, MAC0_MAC_MII_EN, 0, reg); - SW_SET_REG_BY_FIELD(PORT0_PAD_CTRL, MAC0_PHY_MII_EN, 0, reg); - SW_SET_REG_BY_FIELD(PORT0_PAD_CTRL, MAC0_SGMII_EN, 0, reg); - SW_SET_REG_BY_FIELD(PORT0_PAD_CTRL, RMII_MASTER_EN, 0, reg); - SW_SET_REG_BY_FIELD(PORT0_PAD_CTRL, RMII_SLAVE_EN, 0, reg); - - /* hardware suggestions: restore to defatult settings */ - SW_SET_REG_BY_FIELD(PORT0_PAD_CTRL, MAC0_RGMII_TXCLK_DELAY_EN, 0, reg); - SW_SET_REG_BY_FIELD(PORT0_PAD_CTRL, MAC0_RGMII_RXCLK_DELAY_EN, 0, reg); - SW_SET_REG_BY_FIELD(PORT0_PAD_CTRL, MAC0_RGMII_TXCLK_DELAY_SEL, 0, reg); - SW_SET_REG_BY_FIELD(PORT0_PAD_CTRL, MAC0_RGMII_RXCLK_DELAY_SEL, 0, reg); - SW_SET_REG_BY_FIELD(PORT0_PAD_CTRL, MAC0_PHY_GMII_TXCLK_SEL, 0, reg); - SW_SET_REG_BY_FIELD(PORT0_PAD_CTRL, MAC0_PHY_GMII_RXCLK_SEL, 0, reg); - SW_SET_REG_BY_FIELD(PORT0_PAD_CTRL, MAC0_PHY_MII_TXCLK_SEL, 0, reg); - SW_SET_REG_BY_FIELD(PORT0_PAD_CTRL, MAC0_PHY_MII_RXCLK_SEL, 0, reg); - SW_SET_REG_BY_FIELD(PORT0_PAD_CTRL, MAC0_MAC_GMII_TXCLK_SEL, 0, reg); - SW_SET_REG_BY_FIELD(PORT0_PAD_CTRL, MAC0_MAC_GMII_RXCLK_SEL, 0, reg); - SW_SET_REG_BY_FIELD(PORT0_PAD_CTRL, MAC0_MAC_MII_TXCLK_SEL, 0, reg); - SW_SET_REG_BY_FIELD(PORT0_PAD_CTRL, MAC0_MAC_MII_RXCLK_SEL, 0, reg); - - if (ISISC_MAC_0 == port_id) - { - HSL_REG_ENTRY_SET(rv, dev_id, PORT0_PAD_CTRL, 0, - (a_uint8_t *) (®), sizeof (a_uint32_t)); - } - else if (ISISC_MAC_5 == port_id) - { - HSL_REG_ENTRY_SET(rv, dev_id, PORT5_PAD_CTRL, 0, - (a_uint8_t *) (®), sizeof (a_uint32_t)); - } - else - { - HSL_REG_ENTRY_SET(rv, dev_id, PORT6_PAD_CTRL, 0, - (a_uint8_t *) (®), sizeof (a_uint32_t)); - } - - return rv; -} - -static sw_error_t -_isisc_interface_mac_mode_set(a_uint32_t dev_id, fal_port_t port_id, fal_mac_config_t * config) -{ - sw_error_t rv; - - HSL_DEV_ID_CHECK(dev_id); - - if (FAL_MAC_MODE_RGMII == config->mac_mode) - { - rv = _isisc_port_rgmii_mode_set(dev_id, port_id, &(config->config.rgmii)); - } - else if (FAL_MAC_MODE_GMII == config->mac_mode) - { - rv = _isisc_port_gmii_mode_set(dev_id, port_id, &(config->config.gmii)); - } - else if (FAL_MAC_MODE_MII == config->mac_mode) - { - rv = _isisc_port_mii_mode_set(dev_id, port_id, &(config->config.mii)); - } - else if (FAL_MAC_MODE_SGMII == config->mac_mode) - { - rv = _isisc_port_sgmii_mode_set(dev_id, port_id, &(config->config.sgmii)); - } - else if (FAL_MAC_MODE_FIBER == config->mac_mode) - { - rv = _isisc_port_fiber_mode_set(dev_id, port_id, &(config->config.fiber)); - } - else if (FAL_MAC_MODE_DEFAULT == config->mac_mode) - { - rv = _isisc_port_default_mode_set(dev_id, port_id); - } - else if (FAL_MAC_MODE_RMII == config->mac_mode) - { - rv = _isisc_port_rmii_mode_set(dev_id, port_id, &(config->config.rmii)); - } - else - { - return SW_BAD_PARAM; - } - - return rv; -} - -static sw_error_t -_isisc_interface_mac_mode_get(a_uint32_t dev_id, fal_port_t port_id, fal_mac_config_t * config) -{ - sw_error_t rv; - a_uint32_t reg = 0, field, field2; - - HSL_DEV_ID_CHECK(dev_id); - - if (ISISC_MAC_0 == port_id) - { - HSL_REG_ENTRY_GET(rv, dev_id, PORT0_PAD_CTRL, 0, - (a_uint8_t *) (®), sizeof (a_uint32_t)); - } - else if (ISISC_MAC_5 == port_id) - { - HSL_REG_ENTRY_GET(rv, dev_id, PORT5_PAD_CTRL, 0, - (a_uint8_t *) (®), sizeof (a_uint32_t)); - } - else if (ISISC_MAC_6 == port_id) - { - HSL_REG_ENTRY_GET(rv, dev_id, PORT6_PAD_CTRL, 0, - (a_uint8_t *) (®), sizeof (a_uint32_t)); - } - else - { - return SW_BAD_PARAM; - } - SW_RTN_ON_ERROR(rv); - - aos_mem_zero(config, sizeof(fal_interface_mac_mode_t)); - - SW_GET_FIELD_BY_REG(PORT0_PAD_CTRL, MAC0_RGMII_EN, field, reg); - if (field) - { - config->mac_mode = FAL_MAC_MODE_RGMII; - rv = _isisc_port_rgmii_mode_get(dev_id, port_id, &(config->config.rgmii)); - return rv; - } - - SW_GET_FIELD_BY_REG(PORT0_PAD_CTRL, RMII_MASTER_EN, field, reg); - SW_GET_FIELD_BY_REG(PORT0_PAD_CTRL, RMII_SLAVE_EN, field2, reg); - if (field || field2) - { - config->mac_mode = FAL_MAC_MODE_RMII; - rv = _isisc_port_rmii_mode_get(dev_id, port_id, &(config->config.rmii)); - return rv; - } - - SW_GET_FIELD_BY_REG(PORT0_PAD_CTRL, MAC0_MAC_GMII_EN, field, reg); - SW_GET_FIELD_BY_REG(PORT0_PAD_CTRL, MAC0_PHY_GMII_EN, field2, reg); - if (field || field2) - { - config->mac_mode = FAL_MAC_MODE_GMII; - rv = _isisc_port_gmii_mode_get(dev_id, port_id, &(config->config.gmii)); - return rv; - } - - SW_GET_FIELD_BY_REG(PORT0_PAD_CTRL, MAC0_MAC_MII_EN, field, reg); - SW_GET_FIELD_BY_REG(PORT0_PAD_CTRL, MAC0_PHY_MII_EN, field2, reg); - if (field || field2) - { - config->mac_mode = FAL_MAC_MODE_MII; - rv = _isisc_port_mii_mode_get(dev_id, port_id, &(config->config.mii)); - return rv; - } - - SW_GET_FIELD_BY_REG(PORT0_PAD_CTRL, MAC0_SGMII_EN, field, reg); - SW_GET_FIELD_BY_REG(PORT0_PAD_CTRL, MAC0_MAC_SGMII_FORCE_SPEED, field2, reg); - - if (field) - { - HSL_REG_ENTRY_GET(rv, dev_id, SGMII_CTRL, 0, - (a_uint8_t *) (®), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - - SW_GET_FIELD_BY_REG(SGMII_CTRL, SGMII_FIBER_MODE, field, reg); - if (3 == field) - { - config->mac_mode = FAL_MAC_MODE_FIBER; - rv = _isisc_port_fiber_mode_get(dev_id, port_id, &(config->config.fiber)); - } - else - { - config->mac_mode = FAL_MAC_MODE_SGMII; - rv = _isisc_port_sgmii_mode_get(dev_id, port_id, &(config->config.sgmii)); - if (field2) - config->config.sgmii.force_speed = A_TRUE; - else - config->config.sgmii.force_speed = A_FALSE; - } - return rv; - } - - config->mac_mode = FAL_MAC_MODE_DEFAULT; - return SW_OK; -} - -static sw_error_t -_isisc_interface_phy_mode_set(a_uint32_t dev_id, a_uint32_t phy_id, fal_phy_config_t * config) -{ - sw_error_t rv; - a_uint16_t data; - a_bool_t tx_delay_cmd, rx_delay_cmd; - hsl_phy_ops_t *phy_drv; - a_uint32_t reg, rgmii_mode, tx_delay = 2, port_id; - - HSL_DEV_ID_CHECK(dev_id); - - /* only PHY4 support mode setting */ - if (ISISC_PHY_MODE_PHY_ID != phy_id) - { - return SW_BAD_PARAM; - } - - port_id = qca_ssdk_phy_addr_to_port(dev_id, phy_id); - SW_RTN_ON_NULL (phy_drv = hsl_phy_api_ops_get(dev_id, port_id)); - if ((NULL == phy_drv->phy_debug_write) || (NULL == phy_drv->phy_debug_read)) - return SW_NOT_SUPPORTED; - - HSL_REG_ENTRY_GET(rv, dev_id, PORT6_PAD_CTRL, 0, - (a_uint8_t *) (®), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - - if (FAL_MAC_MODE_RGMII == config->mac_mode) - { - SW_SET_REG_BY_FIELD(PORT6_PAD_CTRL, PHY4_RGMII_EN, 1, reg); - rgmii_mode = 1; - /* PHY TX delay */ - if (A_TRUE == config->txclk_delay_cmd) - { - tx_delay_cmd = A_TRUE; - tx_delay = config->txclk_delay_sel; - } - else - { - tx_delay_cmd = A_FALSE; - } - - /* PHY RX delay */ - if (A_TRUE == config->rxclk_delay_cmd) - { - rx_delay_cmd = A_TRUE; - } - else - { - rx_delay_cmd = A_FALSE; - } - } - else if (FAL_MAC_MODE_DEFAULT == config->mac_mode) - { - SW_SET_REG_BY_FIELD(PORT6_PAD_CTRL, PHY4_RGMII_EN, 0, reg); - rgmii_mode = 0; - tx_delay_cmd = A_FALSE; - rx_delay_cmd = A_FALSE; - } - else - { - return SW_BAD_PARAM; - } - - HSL_REG_ENTRY_SET(rv, dev_id, PORT6_PAD_CTRL, 0, - (a_uint8_t *) (®), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - - /* PHY RGMII mode, debug register18 bit3 */ - data = phy_drv->phy_debug_read(dev_id, ISISC_PHY_MODE_PHY_ID, 18); - data &= 0xfff7UL; - data |= ((rgmii_mode & 0x1) << 3); - rv = phy_drv->phy_debug_write(dev_id, ISISC_PHY_MODE_PHY_ID, 18, data); - SW_RTN_ON_ERROR(rv); - - /* PHY TX delay command, debug regigster5 bit8 */ - data = phy_drv->phy_debug_read(dev_id, ISISC_PHY_MODE_PHY_ID, 5); - if (A_TRUE == tx_delay_cmd) - { - data |= 0x0100UL; - } - else - { - data &= 0xfeffUL; - } - rv = phy_drv->phy_debug_write(dev_id, ISISC_PHY_MODE_PHY_ID, 5, data); - SW_RTN_ON_ERROR(rv); - - /* PHY TX delay select, debug register11 bit-6 */ - data = phy_drv->phy_debug_read(dev_id, ISISC_PHY_MODE_PHY_ID, 11); - data &= 0xff9fUL; - data |= ((tx_delay & 0x3UL) << 5); - if (A_TRUE == tx_delay_cmd) - { - data |= 0x0100UL; - } - else - { - data &= 0xfeffUL; - } - rv = phy_drv->phy_debug_write(dev_id, ISISC_PHY_MODE_PHY_ID, 11, data); - SW_RTN_ON_ERROR(rv); - - /* PHY RX delay command, debug regigster0 bit15 */ - data = phy_drv->phy_debug_read(dev_id, ISISC_PHY_MODE_PHY_ID, 0); - if (A_TRUE == rx_delay_cmd) - { - data |= 0x8000UL; - } - else - { - data &= 0x7fffUL; - } - rv = phy_drv->phy_debug_write(dev_id, ISISC_PHY_MODE_PHY_ID, 0, data); - SW_RTN_ON_ERROR(rv); - - /* PHY RX delay select, now hardware not support */ - - return SW_OK; -} - -static sw_error_t -_isisc_interface_phy_mode_get(a_uint32_t dev_id, a_uint32_t phy_id, fal_phy_config_t * config) -{ - sw_error_t rv; - a_uint16_t data; - a_uint32_t reg = 0, rgmii, port_id; - hsl_phy_ops_t *phy_drv; - - HSL_DEV_ID_CHECK(dev_id); - - /* only one PHY device support this */ - if (ISISC_PHY_MODE_PHY_ID != phy_id) - { - return SW_BAD_PARAM; - } - - port_id = qca_ssdk_phy_addr_to_port(dev_id, phy_id); - SW_RTN_ON_NULL (phy_drv = hsl_phy_api_ops_get(dev_id, port_id)); - if (NULL == phy_drv->phy_debug_read) - return SW_NOT_SUPPORTED; - - aos_mem_zero(config, sizeof(fal_phy_config_t)); - - HSL_REG_ENTRY_GET(rv, dev_id, PORT6_PAD_CTRL, 0, - (a_uint8_t *) (®), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - - SW_GET_FIELD_BY_REG(PORT6_PAD_CTRL, PHY4_RGMII_EN, rgmii, reg); - - if (rgmii) - { - config->mac_mode = FAL_MAC_MODE_RGMII; - data = phy_drv->phy_debug_read(dev_id, ISISC_PHY_MODE_PHY_ID, 5); - if (data & 0x0100) - { - config->txclk_delay_cmd = A_TRUE; - data = phy_drv->phy_debug_read(dev_id, ISISC_PHY_MODE_PHY_ID, 11); - config->txclk_delay_sel = (data >> 5) & 0x3UL; - } - else - { - config->txclk_delay_cmd = A_FALSE; - } - - data = phy_drv->phy_debug_read(dev_id, ISISC_PHY_MODE_PHY_ID, 0); - if (data & 0x8000) - { - config->rxclk_delay_cmd = A_TRUE; - } - else - { - config->rxclk_delay_cmd = A_FALSE; - } - } - else - { - config->mac_mode = FAL_MAC_MODE_DEFAULT; - } - - return SW_OK; -} - -static sw_error_t -_isisc_interface_fx100_ctrl_set(a_uint32_t dev_id, fal_fx100_ctrl_config_t* config) -{ - sw_error_t rv; - a_uint32_t reg = 0; - - HSL_DEV_ID_CHECK(dev_id); - - HSL_REG_ENTRY_GET(rv, dev_id, FX100_CTRL, 0, - (a_uint8_t *) (®), sizeof (a_uint32_t)); - - SW_RTN_ON_ERROR(rv); - - if (Fx100BASE_MODE == config->link_mode) - { - SW_SET_REG_BY_FIELD(FX100_CTRL, LINK_CTRL, Fx100BASE_MODE, reg); - } - else - { - return SW_BAD_PARAM; - } - - if (A_TRUE == config->overshoot) - { - SW_SET_REG_BY_FIELD(FX100_CTRL, OVERSHOOT_MODE, 1, reg); - } - else - { - SW_SET_REG_BY_FIELD(FX100_CTRL, OVERSHOOT_MODE, 0, reg); - } - - if (A_TRUE == config->loopback) - { - SW_SET_REG_BY_FIELD(FX100_CTRL, LOOPBACK_MODE, 1, reg); - } - else - { - SW_SET_REG_BY_FIELD(FX100_CTRL, LOOPBACK_MODE, 0, reg); - } - - if (A_TRUE == config->fd_mode) - { - SW_SET_REG_BY_FIELD(FX100_CTRL, FD_MODE, 1, reg); - } - else - { - SW_SET_REG_BY_FIELD(FX100_CTRL, FD_MODE, 0, reg); - } - - if (A_TRUE == config->col_test) - { - SW_SET_REG_BY_FIELD(FX100_CTRL, COL_TEST, 1, reg); - } - else - { - SW_SET_REG_BY_FIELD(FX100_CTRL, COL_TEST, 0, reg); - } - - if (FX100_SERDS_MODE == config->sgmii_fiber_mode) - { - SW_SET_REG_BY_FIELD(FX100_CTRL, SGMII_FIBER, FX100_SERDS_MODE, reg); - } - else - { - return SW_BAD_PARAM; - } - - if (A_TRUE == config->crs_ctrl) - { - SW_SET_REG_BY_FIELD(FX100_CTRL, CRS_CTRL, 1, reg); - } - else - { - SW_SET_REG_BY_FIELD(FX100_CTRL, CRS_CTRL, 0, reg); - } - - if (A_TRUE == config->loopback_ctrl) - { - SW_SET_REG_BY_FIELD(FX100_CTRL, LOOPBACK_TEST, 1, reg); - } - else - { - SW_SET_REG_BY_FIELD(FX100_CTRL, LOOPBACK_TEST, 0, reg); - } - - if (A_TRUE == config->crs_col_100_ctrl) - { - SW_SET_REG_BY_FIELD(FX100_CTRL, CRS_COL_100_CTRL, 1, reg); - } - else - { - SW_SET_REG_BY_FIELD(FX100_CTRL, CRS_COL_100_CTRL, 0, reg); - } - - if (A_TRUE == config->loop_en) - { - SW_SET_REG_BY_FIELD(FX100_CTRL, FX100_LOOP_EN, 1, reg); - } - else - { - SW_SET_REG_BY_FIELD(FX100_CTRL, FX100_LOOP_EN, 0, reg); - } - - HSL_REG_ENTRY_SET(rv, dev_id, FX100_CTRL, 0, - (a_uint8_t *) (®), sizeof (a_uint32_t)); - - SW_RTN_ON_ERROR(rv); - - return SW_OK; -} - -static sw_error_t -_isisc_interface_fx100_ctrl_get(a_uint32_t dev_id, fal_fx100_ctrl_config_t* config) -{ - sw_error_t rv; - a_uint32_t reg = 0, field; - - HSL_DEV_ID_CHECK(dev_id); - - HSL_REG_ENTRY_GET(rv, dev_id, FX100_CTRL, 0, - (a_uint8_t *) (®), sizeof (a_uint32_t)); - - SW_RTN_ON_ERROR(rv); - - SW_GET_FIELD_BY_REG(FX100_CTRL, LINK_CTRL, field, reg); - if (field == Fx100BASE_MODE) - { - config->link_mode = Fx100BASE_MODE; - } - - SW_GET_FIELD_BY_REG(FX100_CTRL, OVERSHOOT_MODE, field, reg); - if (A_TRUE == field) - { - config->overshoot = A_TRUE; - } - else - { - config->overshoot = A_FALSE; - } - - SW_GET_FIELD_BY_REG(FX100_CTRL, LOOPBACK_MODE, field, reg); - if (A_TRUE == field) - { - config->loopback = A_TRUE; - } - else - { - config->loopback = A_FALSE; - } - - SW_GET_FIELD_BY_REG(FX100_CTRL, FD_MODE, field, reg); - config->fd_mode =field; - - SW_GET_FIELD_BY_REG(FX100_CTRL, COL_TEST, field, reg); - if (A_TRUE == field) - { - config->col_test = A_TRUE; - } - else - { - config->col_test = A_FALSE; - } - - SW_GET_FIELD_BY_REG(FX100_CTRL, SGMII_FIBER, field, reg); - if (FX100_SERDS_MODE == field) - { - config->sgmii_fiber_mode = FX100_SERDS_MODE; - } - - SW_GET_FIELD_BY_REG(FX100_CTRL, CRS_CTRL, field, reg); - if (A_TRUE == field) - { - config->crs_ctrl = A_TRUE; - } - else - { - config->crs_ctrl = A_FALSE; - } - - SW_GET_FIELD_BY_REG(FX100_CTRL, LOOPBACK_TEST, field, reg); - if (A_TRUE == field) - { - config->loopback_ctrl = A_TRUE; - } - else - { - config->loopback_ctrl = A_FALSE; - } - - SW_GET_FIELD_BY_REG(FX100_CTRL, CRS_COL_100_CTRL, field, reg); - if (A_TRUE == field) - { - config->crs_col_100_ctrl = A_TRUE; - } - else - { - config->crs_col_100_ctrl = A_FALSE; - } - - SW_GET_FIELD_BY_REG(FX100_CTRL, FX100_LOOP_EN, field, reg); - if (A_TRUE == field) - { - config->loop_en = A_TRUE; - } - else - { - config->loop_en = A_FALSE; - } - - return SW_OK; -} - -static sw_error_t -_isisc_interface_fx100_status_get(a_uint32_t dev_id, a_uint32_t* status) -{ - sw_error_t rv; - a_uint32_t reg = 0, field; - - HSL_DEV_ID_CHECK(dev_id); - - HSL_REG_ENTRY_GET(rv, dev_id, FX100_CTRL, 0, - (a_uint8_t *) (®), sizeof (a_uint32_t)); - - SW_RTN_ON_ERROR(rv); - - SW_GET_FIELD_BY_REG(FX100_CTRL, FX100_STATUS, field, reg); - - *status = field; - - return SW_OK; -} - -/** - * @brief Set 802.3az status on a particular port. - * @param[in] dev_id device id - * @param[in] port_id port id - * @param[in] enable A_TRUE or A_FALSE - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -isisc_port_3az_status_set(a_uint32_t dev_id, fal_port_t port_id, a_bool_t enable) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _isisc_port_3az_status_set(dev_id, port_id, enable); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Get 802.3az status on a particular port. - * @param[in] dev_id device id - * @param[in] port_id port id - * @param[out] enable A_TRUE or A_FALSE - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -isisc_port_3az_status_get(a_uint32_t dev_id, fal_port_t port_id, a_bool_t * enable) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _isisc_port_3az_status_get(dev_id, port_id, enable); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Set interface mode on a particular MAC device. - * @param[in] dev_id device id - * @param[in] mca_id MAC device ID - * @param[in] config interface configuration - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -isisc_interface_mac_mode_set(a_uint32_t dev_id, fal_port_t port_id, fal_mac_config_t * config) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _isisc_interface_mac_mode_set(dev_id, port_id, config); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Get interface mode on a particular MAC device. - * @param[in] dev_id device id - * @param[in] mca_id MAC device ID - * @param[out] config interface configuration - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -isisc_interface_mac_mode_get(a_uint32_t dev_id, fal_port_t port_id, fal_mac_config_t * config) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _isisc_interface_mac_mode_get(dev_id, port_id, config); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Set interface phy mode on a particular PHY device. - * @param[in] dev_id device id - * @param[in] phy_id PHY device ID - * @param[in] config interface configuration - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -isisc_interface_phy_mode_set(a_uint32_t dev_id, a_uint32_t phy_id, fal_phy_config_t * config) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _isisc_interface_phy_mode_set(dev_id, phy_id, config); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Get interface phy mode on a particular PHY device. - * @param[in] dev_id device id - * @param[in] phy_id PHY device ID - * @param[out] config interface configuration - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -isisc_interface_phy_mode_get(a_uint32_t dev_id, a_uint32_t phy_id, fal_phy_config_t * config) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _isisc_interface_phy_mode_get(dev_id, phy_id, config); - HSL_API_UNLOCK; - return rv; -} - - -/** - * @brief Set fx100 control configuration. - * @param[in] dev_id device id - * @param[in] config fx100 control configuration - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -isisc_interface_fx100_ctrl_set(a_uint32_t dev_id, fal_fx100_ctrl_config_t* config) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _isisc_interface_fx100_ctrl_set(dev_id, config); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Get fx100 control configuration. - * @param[in] dev_id device id - * @param[out] config fx100 control configuration - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -isisc_interface_fx100_ctrl_get(a_uint32_t dev_id, fal_fx100_ctrl_config_t* config) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _isisc_interface_fx100_ctrl_get(dev_id, config); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Get fx100 status. - * @param[in] dev_id device id - * @param[out] the value of fx100 status - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -isisc_interface_fx100_status_get(a_uint32_t dev_id, a_uint32_t* status) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _isisc_interface_fx100_status_get(dev_id, status); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Set mac0 and mac6 exchange status. - * @param[in] dev_id device id - * @param[in] enable A_TRUE or A_FALSE - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -isisc_interface_mac06_exch_set(a_uint32_t dev_id, a_bool_t enable) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _isisc_interface_mac06_exch_set(dev_id, enable); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Get mac0 and mac6 exchange status. - * @param[in] dev_id device id - * @param[out] enable A_TRUE or A_FALSE - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -isisc_interface_mac06_exch_get(a_uint32_t dev_id, a_bool_t* enable) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _isisc_interface_mac06_exch_get(dev_id, enable); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Get mac pad configuration. - * @param[in] dev_id device id - * @param[in] port_num port num - * @param[out] config value - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -isisc_interface_mac_pad_get(a_uint32_t dev_id,a_uint32_t port_num, a_uint32_t* value) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _isisc_interface_mac_pad_get(dev_id, port_num, value); - HSL_API_UNLOCK; - return rv; -} - - -/** - * @brief Set mac pad configuration. - * @param[in] dev_id device id - * @param[in] port_num port num - * @param[in] config value - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -isisc_interface_mac_pad_set(a_uint32_t dev_id,a_uint32_t port_num, a_uint32_t value) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _isisc_interface_mac_pad_set(dev_id,port_num,value); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Get mac SGMII configuration. - * @param[in] dev_id device id - * @param[out] config value - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -isisc_interface_mac_sgmii_get(a_uint32_t dev_id, a_uint32_t* value) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _isisc_interface_mac_sgmii_get(dev_id, value); - HSL_API_UNLOCK; - return rv; -} - - -/** - * @brief Set mac SGMII configuration. - * @param[in] dev_id device id - * @param[in] config value - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -isisc_interface_mac_sgmii_set(a_uint32_t dev_id, a_uint32_t value) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _isisc_interface_mac_sgmii_set(dev_id, value); - HSL_API_UNLOCK; - return rv; -} - - -sw_error_t -isisc_interface_ctrl_init(a_uint32_t dev_id) -{ - HSL_DEV_ID_CHECK(dev_id); - -#ifndef HSL_STANDALONG - { - hsl_api_t *p_api; - - SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id)); - - p_api->port_3az_status_set = isisc_port_3az_status_set; - p_api->port_3az_status_get = isisc_port_3az_status_get; - p_api->interface_mac_mode_set = isisc_interface_mac_mode_set; - p_api->interface_mac_mode_get = isisc_interface_mac_mode_get; - p_api->interface_phy_mode_set = isisc_interface_phy_mode_set; - p_api->interface_phy_mode_get = isisc_interface_phy_mode_get; - p_api->interface_fx100_ctrl_set = isisc_interface_fx100_ctrl_set; - p_api->interface_fx100_ctrl_get = isisc_interface_fx100_ctrl_get; - p_api->interface_fx100_status_get = isisc_interface_fx100_status_get; - p_api->interface_mac06_exch_set = isisc_interface_mac06_exch_set; - p_api->interface_mac06_exch_get = isisc_interface_mac06_exch_get; - p_api->interface_mac_pad_get = isisc_interface_mac_pad_get; - p_api->interface_mac_pad_set = isisc_interface_mac_pad_set; - p_api->interface_mac_sgmii_get = isisc_interface_mac_sgmii_get; - p_api->interface_mac_sgmii_set = isisc_interface_mac_sgmii_set; - } -#endif - - return SW_OK; -} - -/** - * @} - */ - diff --git a/feeds/ipq807x/qca-ssdk/src/src/hsl/isisc/isisc_ip.c b/feeds/ipq807x/qca-ssdk/src/src/hsl/isisc/isisc_ip.c deleted file mode 100755 index b8851bff9..000000000 --- a/feeds/ipq807x/qca-ssdk/src/src/hsl/isisc/isisc_ip.c +++ /dev/null @@ -1,2555 +0,0 @@ -/* - * Copyright (c) 2012, 2016, The Linux Foundation. All rights reserved. - * Permission to use, copy, modify, and/or distribute this software for - * any purpose with or without fee is hereby granted, provided that the - * above copyright notice and this permission notice appear in all copies. - * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES - * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR - * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES - * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN - * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT - * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. - */ - - -/** - * @defgroup isisc_ip ISISC_IP - * @{ - */ - -#include "sw.h" -#include "hsl.h" -#include "hsl_dev.h" -#include "hsl_port_prop.h" -#include "isisc_ip.h" -#include "isisc_reg.h" - -#define ISISC_HOST_ENTRY_DATA0_ADDR 0x0e80 -#define ISISC_HOST_ENTRY_DATA1_ADDR 0x0e84 -#define ISISC_HOST_ENTRY_DATA2_ADDR 0x0e88 -#define ISISC_HOST_ENTRY_DATA3_ADDR 0x0e8c -#define ISISC_HOST_ENTRY_DATA4_ADDR 0x0e90 -#define ISISC_HOST_ENTRY_DATA5_ADDR 0x0e94 -#define ISISC_HOST_ENTRY_DATA6_ADDR 0x0e98 -#define ISISC_HOST_ENTRY_DATA7_ADDR 0x0e58 - -#define ISISC_HOST_ENTRY_REG_NUM 8 - -#define ISISC_HOST_ENTRY_FLUSH 1 -#define ISISC_HOST_ENTRY_ADD 2 -#define ISISC_HOST_ENTRY_DEL 3 -#define ISISC_HOST_ENTRY_NEXT 4 -#define ISISC_HOST_ENTRY_SEARCH 5 - -#define ISISC_ENTRY_ARP 3 - -#define ISISC_INTF_MAC_ADDR_NUM 8 -#define ISISC_INTF_MAC_TBL0_ADDR 0x5a900 -#define ISISC_INTF_MAC_TBL1_ADDR 0x5a904 -#define ISISC_INTF_MAC_TBL2_ADDR 0x5a908 -#define ISISC_INTF_MAC_EDIT0_ADDR 0x02000 -#define ISISC_INTF_MAC_EDIT1_ADDR 0x02004 -#define ISISC_INTF_MAC_EDIT2_ADDR 0x02008 - -#define ISISC_IP6_BASE_ADDR 0x0470 - -#define ISISC_HOST_ENTRY_NUM 128 - -#define ISISC_IP_COUTER_ADDR 0x2b000 - -static a_uint32_t isisc_mac_snap[SW_MAX_NR_DEV] = { 0 }; -static fal_intf_mac_entry_t isisc_intf_snap[SW_MAX_NR_DEV][ISISC_INTF_MAC_ADDR_NUM]; - -static void -_isisc_ip_pt_learn_save(a_uint32_t dev_id, a_uint32_t * status) -{ - sw_error_t rv; - a_uint32_t data = 0; - - HSL_REG_ENTRY_GET(rv, dev_id, ROUTER_PTCTRL2, 0, - (a_uint8_t *) (&data), sizeof (a_uint32_t)); - if (SW_OK != rv) - { - return; - } - - *status = (data & 0x7f7f); - - data &= 0xffff8080; - HSL_REG_ENTRY_SET(rv, dev_id, ROUTER_PTCTRL2, 0, - (a_uint8_t *) (&data), sizeof (a_uint32_t)); - return; -} - -static void -_isisc_ip_pt_learn_restore(a_uint32_t dev_id, a_uint32_t status) -{ - sw_error_t rv; - a_uint32_t data = 0; - - HSL_REG_ENTRY_GET(rv, dev_id, ROUTER_PTCTRL2, 0, - (a_uint8_t *) (&data), sizeof (a_uint32_t)); - if (SW_OK != rv) - { - return; - } - - data &= 0xffff8080; - data |= (status & 0x7f7f); - - HSL_REG_ENTRY_SET(rv, dev_id, ROUTER_PTCTRL2, 0, - (a_uint8_t *) (&data), sizeof (a_uint32_t)); - return; -} - -static sw_error_t -_isisc_ip_feature_check(a_uint32_t dev_id) -{ - sw_error_t rv; - a_uint32_t entry = 0; - - HSL_REG_FIELD_GET(rv, dev_id, MASK_CTL, 0, DEVICE_ID, - (a_uint8_t *) (&entry), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - - if (S17C_DEVICE_ID == entry) - { - return SW_OK; - } - else - { - return SW_NOT_SUPPORTED; - } -} - -static sw_error_t -_isisc_ip_counter_get(a_uint32_t dev_id, a_uint32_t cnt_id, - a_uint32_t counter[2]) -{ - sw_error_t rv; - a_uint32_t i, addr; - - addr = ISISC_IP_COUTER_ADDR + (cnt_id << 3); - for (i = 0; i < 2; i++) - { - HSL_REG_ENTRY_GEN_GET(rv, dev_id, addr, sizeof (a_uint32_t), - (a_uint8_t *) (&(counter[i])), - sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - - addr += 4; - } - - return SW_OK; -} - -static sw_error_t -_isisc_host_entry_commit(a_uint32_t dev_id, a_uint32_t entry_type, a_uint32_t op) -{ - a_uint32_t busy = 1, i = 0x100, entry = 0, j, try_num; - a_uint32_t learn_status = 0; - sw_error_t rv; - - while (busy && --i) - { - HSL_REG_ENTRY_GET(rv, dev_id, HOST_ENTRY7, 0, (a_uint8_t *) (&entry), - sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - SW_GET_FIELD_BY_REG(HOST_ENTRY7, TBL_BUSY, busy, entry); - } - - if (i == 0) - { - return SW_BUSY; - } - - SW_SET_REG_BY_FIELD(HOST_ENTRY7, TBL_BUSY, 1, entry); - SW_SET_REG_BY_FIELD(HOST_ENTRY7, TBL_SEL, entry_type, entry); - SW_SET_REG_BY_FIELD(HOST_ENTRY7, ENTRY_FUNC, op, entry); - - HSL_REG_ENTRY_SET(rv, dev_id, HOST_ENTRY7, 0, (a_uint8_t *) (&entry), - sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - - /* hardware requirements, we should disable ARP learn at first */ - /* and maybe we should try several times... */ - _isisc_ip_pt_learn_save(dev_id, &learn_status); - if (learn_status) - { - try_num = 10; - } - else - { - try_num = 1; - } - - for (j = 0; j < try_num; j++) - { - busy = 1; - i = 0x1000; - while (busy && --i) - { - HSL_REG_ENTRY_GET(rv, dev_id, HOST_ENTRY7, 0, (a_uint8_t *) (&entry), - sizeof (a_uint32_t)); - if (SW_OK != rv) - { - _isisc_ip_pt_learn_restore(dev_id, learn_status); - return rv; - } - SW_GET_FIELD_BY_REG(HOST_ENTRY7, TBL_BUSY, busy, entry); - } - - if (i == 0) - { - _isisc_ip_pt_learn_restore(dev_id, learn_status); - return SW_BUSY; - } - - /* hardware requirement, we should read again... */ - HSL_REG_ENTRY_GET(rv, dev_id, HOST_ENTRY7, 0, (a_uint8_t *) (&entry), - sizeof (a_uint32_t)); - if (SW_OK != rv) - { - _isisc_ip_pt_learn_restore(dev_id, learn_status); - return rv; - } - - /* operation success...... */ - SW_GET_FIELD_BY_REG(HOST_ENTRY7, TBL_STAUS, busy, entry); - if (busy) - { - _isisc_ip_pt_learn_restore(dev_id, learn_status); - return SW_OK; - } - } - - _isisc_ip_pt_learn_restore(dev_id, learn_status); - if (ISISC_HOST_ENTRY_NEXT == op) - { - return SW_NO_MORE; - } - else if (ISISC_HOST_ENTRY_SEARCH == op) - { - return SW_NOT_FOUND; - } - else if (ISISC_HOST_ENTRY_DEL == op) - { - return SW_NOT_FOUND; - } - else - { - return SW_FAIL; - } -} - -static sw_error_t -_isisc_ip_intf_sw_to_hw(a_uint32_t dev_id, fal_host_entry_t * entry, - a_uint32_t * hw_intf) -{ - sw_error_t rv; - a_uint32_t addr, lvid, hvid, tbl[3] = {0}, i; - a_uint32_t sw_intf = entry->intf_id; - a_uint32_t vid_offset; - - for (i = 0; i < ISISC_INTF_MAC_ADDR_NUM; i++) - { - if (isisc_mac_snap[dev_id] & (0x1 << i)) - { - addr = ISISC_INTF_MAC_TBL0_ADDR + (i << 4) + 4; - HSL_REG_ENTRY_GEN_GET(rv, dev_id, addr, sizeof (a_uint32_t), - (a_uint8_t *) (&(tbl[1])), - sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - - addr = ISISC_INTF_MAC_TBL0_ADDR + (i << 4) + 8; - HSL_REG_ENTRY_GEN_GET(rv, dev_id, addr, sizeof (a_uint32_t), - (a_uint8_t *) (&(tbl[2])), - sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - - SW_GET_FIELD_BY_REG(INTF_ADDR_ENTRY1, VID_HIGH0, hvid, tbl[1]); - SW_GET_FIELD_BY_REG(INTF_ADDR_ENTRY2, VID_HIGH1, lvid, tbl[2]); - hvid |= ((lvid & 0xff) << 4); - - SW_GET_FIELD_BY_REG(INTF_ADDR_ENTRY1, VID_LOW, lvid, tbl[1]); - - if ((lvid <= sw_intf) && (hvid >= sw_intf)) - { - vid_offset = entry->expect_vid ? (entry->expect_vid - lvid) : (sw_intf - lvid); - *hw_intf = (vid_offset << 3) | i; - return SW_OK; - } - } - } - - return SW_BAD_PARAM; -} - -static sw_error_t -_isisc_ip_intf_hw_to_sw(a_uint32_t dev_id, a_uint32_t hw_intf, - a_uint32_t * sw_intf) -{ - sw_error_t rv; - a_uint32_t addr, lvid, tbl = 0, i; - - i = hw_intf & 0x7; - - addr = ISISC_INTF_MAC_TBL0_ADDR + (i << 4) + 4; - HSL_REG_ENTRY_GEN_GET(rv, dev_id, addr, sizeof (a_uint32_t), - (a_uint8_t *) (&tbl), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - - SW_GET_FIELD_BY_REG(INTF_ADDR_ENTRY1, VID_LOW, lvid, tbl); - *sw_intf = lvid + (hw_intf >> 3); - - return SW_OK; -} - -static sw_error_t -_isisc_ip_age_time_set(a_uint32_t dev_id, a_uint32_t * time) -{ - sw_error_t rv; - a_uint32_t data; - - if (255 < ((*time + 5) / 6)) - { - return SW_BAD_PARAM; - } - - data = ((*time + 5) / 6); - *time = data * 6; - - HSL_REG_FIELD_SET(rv, dev_id, ROUTER_CTRL, 0, ARP_AGE_TIME, - (a_uint8_t *) (&data), sizeof (a_uint32_t)); - return rv; -} - -static sw_error_t -_isisc_ip_age_time_get(a_uint32_t dev_id, a_uint32_t * time) -{ - sw_error_t rv; - a_uint32_t data = 0; - - HSL_REG_FIELD_GET(rv, dev_id, ROUTER_CTRL, 0, ARP_AGE_TIME, - (a_uint8_t *) (&data), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - - *time = data * 6; - return SW_OK; -} - -static sw_error_t -_isisc_host_sw_to_hw(a_uint32_t dev_id, fal_host_entry_t * entry, - a_uint32_t reg[]) -{ - sw_error_t rv; - a_uint32_t data; - - if (FAL_IP_IP4_ADDR & entry->flags) - { - reg[0] = entry->ip4_addr; - SW_SET_REG_BY_FIELD(HOST_ENTRY6, IP_VER, 0, reg[6]); - } - - if (FAL_IP_IP6_ADDR & entry->flags) - { - reg[0] = entry->ip6_addr.ul[3]; - reg[1] = entry->ip6_addr.ul[2]; - reg[2] = entry->ip6_addr.ul[1]; - reg[3] = entry->ip6_addr.ul[0]; - SW_SET_REG_BY_FIELD(HOST_ENTRY6, IP_VER, 1, reg[6]); - } - - SW_SET_REG_BY_FIELD(HOST_ENTRY4, MAC_ADDR2, entry->mac_addr.uc[2], reg[4]); - SW_SET_REG_BY_FIELD(HOST_ENTRY4, MAC_ADDR3, entry->mac_addr.uc[3], reg[4]); - SW_SET_REG_BY_FIELD(HOST_ENTRY4, MAC_ADDR4, entry->mac_addr.uc[4], reg[4]); - SW_SET_REG_BY_FIELD(HOST_ENTRY4, MAC_ADDR5, entry->mac_addr.uc[5], reg[4]); - SW_SET_REG_BY_FIELD(HOST_ENTRY5, MAC_ADDR0, entry->mac_addr.uc[0], reg[5]); - SW_SET_REG_BY_FIELD(HOST_ENTRY5, MAC_ADDR1, entry->mac_addr.uc[1], reg[5]); - - rv = _isisc_ip_intf_sw_to_hw(dev_id, entry/*was:->intf_id*/, &data); - - SW_RTN_ON_ERROR(rv); - SW_SET_REG_BY_FIELD(HOST_ENTRY5, INTF_ID, data, reg[5]); - -#if 0 - if (A_TRUE != hsl_port_prop_check(dev_id, entry->port_id, HSL_PP_INCL_CPU)) - { - return SW_BAD_PARAM; - } -#endif - - SW_SET_REG_BY_FIELD(HOST_ENTRY5, SRC_PORT, entry->port_id, reg[5]); - - if (FAL_IP_CPU_ADDR & entry->flags) - { - SW_SET_REG_BY_FIELD(HOST_ENTRY5, CPU_ADDR, 1, reg[5]); - } - - SW_SET_REG_BY_FIELD(HOST_ENTRY6, AGE_FLAG, entry->status, reg[6]); - - if ((A_TRUE == entry->mirror_en) && (FAL_MAC_FRWRD != entry->action)) - { - return SW_NOT_SUPPORTED; - } - - if (A_TRUE == entry->counter_en) - { - SW_SET_REG_BY_FIELD(HOST_ENTRY6, CNT_EN, 1, reg[6]); - SW_SET_REG_BY_FIELD(HOST_ENTRY6, CNT_IDX, entry->counter_id, reg[6]); - } - - if (FAL_MAC_DROP == entry->action) - { - SW_SET_REG_BY_FIELD(HOST_ENTRY5, SRC_PORT, 7, reg[5]); - SW_SET_REG_BY_FIELD(HOST_ENTRY6, ACTION, 3, reg[6]); - } - else if (FAL_MAC_RDT_TO_CPU == entry->action) - { - SW_SET_REG_BY_FIELD(HOST_ENTRY6, ACTION, 1, reg[6]); - } - else if (FAL_MAC_CPY_TO_CPU == entry->action) - { - SW_SET_REG_BY_FIELD(HOST_ENTRY6, ACTION, 2, reg[6]); - } - else - { - if (A_TRUE == entry->mirror_en) - { - SW_SET_REG_BY_FIELD(HOST_ENTRY6, ACTION, 0, reg[6]); - } - else - { - SW_SET_REG_BY_FIELD(HOST_ENTRY6, ACTION, 3, reg[6]); - } - } - - return SW_OK; -} - -static sw_error_t -_isisc_host_hw_to_sw(a_uint32_t dev_id, a_uint32_t reg[], - fal_host_entry_t * entry) -{ - sw_error_t rv; - a_uint32_t data, cnt[2] = {0}; - - SW_GET_FIELD_BY_REG(HOST_ENTRY6, IP_VER, data, reg[6]); - if (data) - { - entry->ip6_addr.ul[0] = reg[3]; - entry->ip6_addr.ul[1] = reg[2]; - entry->ip6_addr.ul[2] = reg[1]; - entry->ip6_addr.ul[3] = reg[0]; - entry->flags |= FAL_IP_IP6_ADDR; - } - else - { - entry->ip4_addr = reg[0]; - entry->flags |= FAL_IP_IP4_ADDR; - } - - SW_GET_FIELD_BY_REG(HOST_ENTRY4, MAC_ADDR2, entry->mac_addr.uc[2], reg[4]); - SW_GET_FIELD_BY_REG(HOST_ENTRY4, MAC_ADDR3, entry->mac_addr.uc[3], reg[4]); - SW_GET_FIELD_BY_REG(HOST_ENTRY4, MAC_ADDR4, entry->mac_addr.uc[4], reg[4]); - SW_GET_FIELD_BY_REG(HOST_ENTRY4, MAC_ADDR5, entry->mac_addr.uc[5], reg[4]); - SW_GET_FIELD_BY_REG(HOST_ENTRY5, MAC_ADDR0, entry->mac_addr.uc[0], reg[5]); - SW_GET_FIELD_BY_REG(HOST_ENTRY5, MAC_ADDR1, entry->mac_addr.uc[1], reg[5]); - - SW_GET_FIELD_BY_REG(HOST_ENTRY5, INTF_ID, data, reg[5]); - rv = _isisc_ip_intf_hw_to_sw(dev_id, data, &(entry->intf_id)); - SW_RTN_ON_ERROR(rv); - - SW_GET_FIELD_BY_REG(HOST_ENTRY5, SRC_PORT, entry->port_id, reg[5]); - - SW_GET_FIELD_BY_REG(HOST_ENTRY5, CPU_ADDR, data, reg[5]); - if (data) - { - entry->flags |= FAL_IP_CPU_ADDR; - } - - SW_GET_FIELD_BY_REG(HOST_ENTRY6, AGE_FLAG, entry->status, reg[6]); - - SW_GET_FIELD_BY_REG(HOST_ENTRY6, CNT_EN, data, reg[6]); - if (data) - { - entry->counter_en = A_TRUE; - SW_GET_FIELD_BY_REG(HOST_ENTRY6, CNT_IDX, entry->counter_id, reg[6]); - - rv = _isisc_ip_counter_get(dev_id, entry->counter_id, cnt); - SW_RTN_ON_ERROR(rv); - - entry->packet = cnt[0]; - entry->byte = cnt[1]; - } - else - { - entry->counter_en = A_FALSE; - } - - SW_GET_FIELD_BY_REG(HOST_ENTRY6, PPPOE_EN, data, reg[6]); - if (data) - { - entry->pppoe_en = A_TRUE; - SW_GET_FIELD_BY_REG(HOST_ENTRY6, PPPOE_IDX, data, reg[6]); - entry->pppoe_id = data; - } - else - { - entry->pppoe_en = A_FALSE; - } - - if (7 == entry->port_id) - { - entry->port_id = 0; - entry->action = FAL_MAC_DROP; - } - else - { - SW_GET_FIELD_BY_REG(HOST_ENTRY6, ACTION, data, reg[6]); - entry->action = FAL_MAC_FRWRD; - if (0 == data) - { - entry->mirror_en = A_TRUE; - } - else if (1 == data) - { - entry->action = FAL_MAC_RDT_TO_CPU; - } - else if (2 == data) - { - entry->action = FAL_MAC_CPY_TO_CPU; - } - } - - return SW_OK; -} - -static sw_error_t -_isisc_host_down_to_hw(a_uint32_t dev_id, a_uint32_t reg[]) -{ - sw_error_t rv; - a_uint32_t i, addr; - - for (i = 0; i < ISISC_HOST_ENTRY_REG_NUM; i++) - { - if((ISISC_HOST_ENTRY_REG_NUM - 1) == i) - { - addr = ISISC_HOST_ENTRY_DATA7_ADDR; - } - else - { - addr = ISISC_HOST_ENTRY_DATA0_ADDR + (i << 2); - } - - HSL_REG_ENTRY_GEN_SET(rv, dev_id, addr, sizeof (a_uint32_t), - (a_uint8_t *) (®[i]), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - } - - return SW_OK; -} - -static sw_error_t -_isisc_host_up_to_sw(a_uint32_t dev_id, a_uint32_t reg[]) -{ - sw_error_t rv; - a_uint32_t i, addr; - - for (i = 0; i < ISISC_HOST_ENTRY_REG_NUM; i++) - { - if((ISISC_HOST_ENTRY_REG_NUM - 1) == i) - { - addr = ISISC_HOST_ENTRY_DATA7_ADDR; - } - else - { - addr = ISISC_HOST_ENTRY_DATA0_ADDR + (i << 2); - } - HSL_REG_ENTRY_GEN_GET(rv, dev_id, addr, sizeof (a_uint32_t), - (a_uint8_t *) (®[i]), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - } - - return SW_OK; -} - -static sw_error_t -_isisc_ip_host_add(a_uint32_t dev_id, fal_host_entry_t * entry) -{ - sw_error_t rv; - a_uint32_t reg[ISISC_HOST_ENTRY_REG_NUM] = { 0 }; - - HSL_DEV_ID_CHECK(dev_id); - - rv = _isisc_ip_feature_check(dev_id); - SW_RTN_ON_ERROR(rv); - - rv = _isisc_host_sw_to_hw(dev_id, entry, reg); - SW_RTN_ON_ERROR(rv); - - rv = _isisc_host_down_to_hw(dev_id, reg); - SW_RTN_ON_ERROR(rv); - - rv = _isisc_host_entry_commit(dev_id, ISISC_ENTRY_ARP, ISISC_HOST_ENTRY_ADD); - SW_RTN_ON_ERROR(rv); - - HSL_REG_ENTRY_GET(rv, dev_id, HOST_ENTRY7, 0, (a_uint8_t *) (®[7]), - sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - - SW_GET_FIELD_BY_REG(HOST_ENTRY7, TBL_IDX, entry->entry_id, reg[7]); - return SW_OK; -} - -static sw_error_t -_isisc_ip_host_del(a_uint32_t dev_id, a_uint32_t del_mode, - fal_host_entry_t * entry) -{ - sw_error_t rv; - a_uint32_t data, reg[ISISC_HOST_ENTRY_REG_NUM] = { 0 }, op = ISISC_HOST_ENTRY_FLUSH; - - HSL_DEV_ID_CHECK(dev_id); - - rv = _isisc_ip_feature_check(dev_id); - SW_RTN_ON_ERROR(rv); - - if (FAL_IP_ENTRY_ID_EN & del_mode) - { - return SW_NOT_SUPPORTED; - } - - if (FAL_IP_ENTRY_IPADDR_EN & del_mode) - { - op = ISISC_HOST_ENTRY_DEL; - if (FAL_IP_IP4_ADDR & entry->flags) - { - reg[0] = entry->ip4_addr; - } - - if (FAL_IP_IP6_ADDR & entry->flags) - { - reg[0] = entry->ip6_addr.ul[3]; - reg[1] = entry->ip6_addr.ul[2]; - reg[2] = entry->ip6_addr.ul[1]; - reg[3] = entry->ip6_addr.ul[0]; - SW_SET_REG_BY_FIELD(HOST_ENTRY6, IP_VER, 1, reg[6]); - } - } - - if (FAL_IP_ENTRY_INTF_EN & del_mode) - { - rv = _isisc_ip_intf_sw_to_hw(dev_id, entry/*was:->intf_id*/, &data); - SW_RTN_ON_ERROR(rv); - - SW_SET_REG_BY_FIELD(HOST_ENTRY7, SPEC_VID, 1, reg[7]); - SW_SET_REG_BY_FIELD(HOST_ENTRY5, INTF_ID, data, reg[5]); - } - - if (FAL_IP_ENTRY_PORT_EN & del_mode) - { - SW_SET_REG_BY_FIELD(HOST_ENTRY7, SPEC_SP, 1, reg[7]); - SW_SET_REG_BY_FIELD(HOST_ENTRY5, SRC_PORT, entry->port_id, reg[5]); - } - - if (FAL_IP_ENTRY_STATUS_EN & del_mode) - { - SW_SET_REG_BY_FIELD(HOST_ENTRY7, SPEC_STATUS, 1, reg[7]); - SW_SET_REG_BY_FIELD(HOST_ENTRY6, AGE_FLAG, entry->status, reg[6]); - } - - rv = _isisc_host_down_to_hw(dev_id, reg); - SW_RTN_ON_ERROR(rv); - - rv = _isisc_host_entry_commit(dev_id, ISISC_ENTRY_ARP, op); - return rv; -} - -static sw_error_t -_isisc_ip_host_get(a_uint32_t dev_id, a_uint32_t get_mode, - fal_host_entry_t * entry) -{ - sw_error_t rv; - a_uint32_t reg[ISISC_HOST_ENTRY_REG_NUM] = { 0 }; - - HSL_DEV_ID_CHECK(dev_id); - - rv = _isisc_ip_feature_check(dev_id); - SW_RTN_ON_ERROR(rv); - - if (FAL_IP_ENTRY_IPADDR_EN != get_mode) - { - return SW_NOT_SUPPORTED; - } - - if (FAL_IP_IP4_ADDR & entry->flags) - { - reg[0] = entry->ip4_addr; - } - else - { - reg[0] = entry->ip6_addr.ul[3]; - reg[1] = entry->ip6_addr.ul[2]; - reg[2] = entry->ip6_addr.ul[1]; - reg[3] = entry->ip6_addr.ul[0]; - SW_SET_REG_BY_FIELD(HOST_ENTRY6, IP_VER, 1, reg[6]); - } - - rv = _isisc_host_down_to_hw(dev_id, reg); - SW_RTN_ON_ERROR(rv); - - rv = _isisc_host_entry_commit(dev_id, ISISC_ENTRY_ARP, - ISISC_HOST_ENTRY_SEARCH); - SW_RTN_ON_ERROR(rv); - - rv = _isisc_host_up_to_sw(dev_id, reg); - SW_RTN_ON_ERROR(rv); - - aos_mem_zero(entry, sizeof (fal_host_entry_t)); - - rv = _isisc_host_hw_to_sw(dev_id, reg, entry); - SW_RTN_ON_ERROR(rv); - - if (!(entry->status)) - { - return SW_NOT_FOUND; - } - - HSL_REG_ENTRY_GET(rv, dev_id, HOST_ENTRY7, 0, (a_uint8_t *) (®[7]), - sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - - SW_GET_FIELD_BY_REG(HOST_ENTRY7, TBL_IDX, entry->entry_id, reg[7]); - return SW_OK; -} - -static sw_error_t -_isisc_ip_host_next(a_uint32_t dev_id, a_uint32_t next_mode, - fal_host_entry_t * entry) -{ - sw_error_t rv; - a_uint32_t idx, data, reg[ISISC_HOST_ENTRY_REG_NUM] = { 0 }; - - HSL_DEV_ID_CHECK(dev_id); - - rv = _isisc_ip_feature_check(dev_id); - SW_RTN_ON_ERROR(rv); - - if (FAL_NEXT_ENTRY_FIRST_ID == entry->entry_id) - { - idx = ISISC_HOST_ENTRY_NUM - 1; - } - else - { - if ((ISISC_HOST_ENTRY_NUM - 1) == entry->entry_id) - { - return SW_NO_MORE; - } - else - { - idx = entry->entry_id; - } - } - - SW_SET_REG_BY_FIELD(HOST_ENTRY7, TBL_IDX, idx, reg[7]); - - if (FAL_IP_ENTRY_INTF_EN & next_mode) - { - rv = _isisc_ip_intf_sw_to_hw(dev_id, entry/*was:->intf_id*/, &data); - SW_RTN_ON_ERROR(rv); - - SW_SET_REG_BY_FIELD(HOST_ENTRY7, SPEC_VID, 1, reg[7]); - SW_SET_REG_BY_FIELD(HOST_ENTRY5, INTF_ID, data, reg[5]); - } - - if (FAL_IP_ENTRY_PORT_EN & next_mode) - { - SW_SET_REG_BY_FIELD(HOST_ENTRY7, SPEC_SP, 1, reg[7]); - SW_SET_REG_BY_FIELD(HOST_ENTRY5, SRC_PORT, entry->port_id, reg[5]); - } - - if (FAL_IP_ENTRY_STATUS_EN & next_mode) - { - SW_SET_REG_BY_FIELD(HOST_ENTRY7, SPEC_STATUS, 1, reg[7]); - SW_SET_REG_BY_FIELD(HOST_ENTRY6, AGE_FLAG, entry->status, reg[6]); - } - - rv = _isisc_host_down_to_hw(dev_id, reg); - SW_RTN_ON_ERROR(rv); - - rv = _isisc_host_entry_commit(dev_id, ISISC_ENTRY_ARP, ISISC_HOST_ENTRY_NEXT); - SW_RTN_ON_ERROR(rv); - - rv = _isisc_host_up_to_sw(dev_id, reg); - SW_RTN_ON_ERROR(rv); - - aos_mem_zero(entry, sizeof (fal_host_entry_t)); - - rv = _isisc_host_hw_to_sw(dev_id, reg, entry); - SW_RTN_ON_ERROR(rv); - - if (!(entry->status)) - { - return SW_NO_MORE; - } - - SW_GET_FIELD_BY_REG(HOST_ENTRY7, TBL_IDX, entry->entry_id, reg[7]); - return SW_OK; -} - -static sw_error_t -_isisc_ip_host_counter_bind(a_uint32_t dev_id, a_uint32_t entry_id, - a_uint32_t cnt_id, a_bool_t enable) -{ - sw_error_t rv; - a_uint32_t reg[ISISC_HOST_ENTRY_REG_NUM] = { 0 }, tbl[ISISC_HOST_ENTRY_REG_NUM] = { 0 }, tbl_idx; - - HSL_DEV_ID_CHECK(dev_id); - - rv = _isisc_ip_feature_check(dev_id); - SW_RTN_ON_ERROR(rv); - - tbl_idx = (entry_id - 1) & 0x7f; - SW_SET_REG_BY_FIELD(HOST_ENTRY7, TBL_IDX, tbl_idx, reg[7]); - - rv = _isisc_host_down_to_hw(dev_id, reg); - SW_RTN_ON_ERROR(rv); - - rv = _isisc_host_entry_commit(dev_id, ISISC_ENTRY_ARP, ISISC_HOST_ENTRY_NEXT); - if (SW_OK != rv) - { - return SW_NOT_FOUND; - } - - rv = _isisc_host_up_to_sw(dev_id, reg); - SW_RTN_ON_ERROR(rv); - - SW_GET_FIELD_BY_REG(HOST_ENTRY7, TBL_IDX, tbl_idx, reg[7]); - if (entry_id != tbl_idx) - { - return SW_NOT_FOUND; - } - - tbl[0] = reg[0]; - tbl[1] = reg[1]; - tbl[2] = reg[2]; - tbl[3] = reg[3]; - tbl[6] = (reg[6] >> 15) << 15; - rv = _isisc_host_down_to_hw(dev_id, tbl); - SW_RTN_ON_ERROR(rv); - - rv = _isisc_host_entry_commit(dev_id, ISISC_ENTRY_ARP, ISISC_HOST_ENTRY_DEL); - SW_RTN_ON_ERROR(rv); - - if (A_FALSE == enable) - { - SW_SET_REG_BY_FIELD(HOST_ENTRY6, CNT_EN, 0, reg[6]); - } - else if (A_TRUE == enable) - { - SW_SET_REG_BY_FIELD(HOST_ENTRY6, CNT_EN, 1, reg[6]); - SW_SET_REG_BY_FIELD(HOST_ENTRY6, CNT_IDX, cnt_id, reg[6]); - } - else - { - return SW_BAD_PARAM; - } - - reg[7] = 0x0; - rv = _isisc_host_down_to_hw(dev_id, reg); - SW_RTN_ON_ERROR(rv); - - rv = _isisc_host_entry_commit(dev_id, ISISC_ENTRY_ARP, ISISC_HOST_ENTRY_ADD); - return rv; -} - -static sw_error_t -_isisc_ip_host_pppoe_bind(a_uint32_t dev_id, a_uint32_t entry_id, - a_uint32_t pppoe_id, a_bool_t enable) -{ - sw_error_t rv; - a_uint32_t reg[ISISC_HOST_ENTRY_REG_NUM] = { 0 }, tbl[ISISC_HOST_ENTRY_REG_NUM] = { 0 }, tbl_idx; - - HSL_DEV_ID_CHECK(dev_id); - - rv = _isisc_ip_feature_check(dev_id); - SW_RTN_ON_ERROR(rv); - - tbl_idx = (entry_id - 1) & 0x7f; - SW_SET_REG_BY_FIELD(HOST_ENTRY7, TBL_IDX, tbl_idx, reg[7]); - - rv = _isisc_host_down_to_hw(dev_id, reg); - SW_RTN_ON_ERROR(rv); - - rv = _isisc_host_entry_commit(dev_id, ISISC_ENTRY_ARP, ISISC_HOST_ENTRY_NEXT); - SW_RTN_ON_ERROR(rv); - - rv = _isisc_host_up_to_sw(dev_id, reg); - if (SW_OK != rv) - { - return SW_NOT_FOUND; - } - - SW_GET_FIELD_BY_REG(HOST_ENTRY7, TBL_IDX, tbl_idx, reg[7]); - if (entry_id != tbl_idx) - { - return SW_NOT_FOUND; - } - - if (A_FALSE == enable) - { - SW_SET_REG_BY_FIELD(HOST_ENTRY6, PPPOE_EN, 0, reg[6]); - } - else if (A_TRUE == enable) - { - SW_SET_REG_BY_FIELD(HOST_ENTRY6, PPPOE_EN, 1, reg[6]); - SW_SET_REG_BY_FIELD(HOST_ENTRY6, PPPOE_IDX, pppoe_id, reg[6]); - } - else - { - return SW_BAD_PARAM; - } - - tbl[0] = reg[0]; - tbl[1] = reg[1]; - tbl[2] = reg[2]; - tbl[3] = reg[3]; - tbl[6] = (reg[6] >> 15) << 15; - rv = _isisc_host_down_to_hw(dev_id, tbl); - SW_RTN_ON_ERROR(rv); - - rv = _isisc_host_entry_commit(dev_id, ISISC_ENTRY_ARP, ISISC_HOST_ENTRY_DEL); - SW_RTN_ON_ERROR(rv); - - reg[7] = 0x0; - rv = _isisc_host_down_to_hw(dev_id, reg); - SW_RTN_ON_ERROR(rv); - - rv = _isisc_host_entry_commit(dev_id, ISISC_ENTRY_ARP, ISISC_HOST_ENTRY_ADD); - SW_RTN_ON_ERROR(rv); - - rv = _isisc_host_up_to_sw(dev_id, reg); - SW_RTN_ON_ERROR(rv); - - return SW_OK; -} - -static sw_error_t -_isisc_ip_pt_arp_learn_set(a_uint32_t dev_id, fal_port_t port_id, - a_uint32_t flags) -{ - sw_error_t rv; - a_uint32_t data = 0; - - HSL_DEV_ID_CHECK(dev_id); - - rv = _isisc_ip_feature_check(dev_id); - SW_RTN_ON_ERROR(rv); - - HSL_REG_ENTRY_GET(rv, dev_id, ROUTER_PTCTRL2, 0, - (a_uint8_t *) (&data), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - - if (FAL_ARP_LEARN_REQ & flags) - { - data |= (0x1 << port_id); - } - else - { - data &= (~(0x1 << port_id)); - } - - if (FAL_ARP_LEARN_ACK & flags) - { - data |= (0x1 << (ROUTER_PTCTRL2_ARP_LEARN_ACK_BOFFSET + port_id)); - } - else - { - data &= (~(0x1 << (ROUTER_PTCTRL2_ARP_LEARN_ACK_BOFFSET + port_id))); - } - - HSL_REG_ENTRY_SET(rv, dev_id, ROUTER_PTCTRL2, 0, - (a_uint8_t *) (&data), sizeof (a_uint32_t)); - return rv; -} - -static sw_error_t -_isisc_ip_pt_arp_learn_get(a_uint32_t dev_id, fal_port_t port_id, - a_uint32_t * flags) -{ - sw_error_t rv; - a_uint32_t data = 0; - - HSL_DEV_ID_CHECK(dev_id); - - rv = _isisc_ip_feature_check(dev_id); - SW_RTN_ON_ERROR(rv); - - *flags = 0; - - HSL_REG_ENTRY_GET(rv, dev_id, ROUTER_PTCTRL2, 0, - (a_uint8_t *) (&data), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - - if (data & (0x1 << port_id)) - { - *flags |= FAL_ARP_LEARN_REQ; - } - - if (data & (0x1 << (ROUTER_PTCTRL2_ARP_LEARN_ACK_BOFFSET + port_id))) - { - *flags |= FAL_ARP_LEARN_ACK; - } - - return SW_OK; -} - -static sw_error_t -_isisc_ip_arp_learn_set(a_uint32_t dev_id, fal_arp_learn_mode_t mode) -{ - sw_error_t rv; - a_uint32_t data; - - HSL_DEV_ID_CHECK(dev_id); - - rv = _isisc_ip_feature_check(dev_id); - SW_RTN_ON_ERROR(rv); - - if (FAL_ARP_LEARN_ALL == mode) - { - data = 1; - } - else if (FAL_ARP_LEARN_LOCAL == mode) - { - data = 0; - } - else - { - return SW_BAD_PARAM; - } - - HSL_REG_FIELD_SET(rv, dev_id, ROUTER_CTRL, 0, ARP_LEARN_MODE, - (a_uint8_t *) (&data), sizeof (a_uint32_t)); - return rv; -} - -static sw_error_t -_isisc_ip_arp_learn_get(a_uint32_t dev_id, fal_arp_learn_mode_t * mode) -{ - sw_error_t rv; - a_uint32_t data = 0; - - HSL_DEV_ID_CHECK(dev_id); - - rv = _isisc_ip_feature_check(dev_id); - SW_RTN_ON_ERROR(rv); - - HSL_REG_FIELD_GET(rv, dev_id, ROUTER_CTRL, 0, ARP_LEARN_MODE, - (a_uint8_t *) (&data), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - - if (data) - { - *mode = FAL_ARP_LEARN_ALL; - } - else - { - *mode = FAL_ARP_LEARN_LOCAL; - } - - return SW_OK; -} - -static sw_error_t -_isisc_ip_source_guard_set(a_uint32_t dev_id, fal_port_t port_id, - fal_source_guard_mode_t mode) -{ - sw_error_t rv; - a_uint32_t reg = 0, data; - - HSL_DEV_ID_CHECK(dev_id); - - rv = _isisc_ip_feature_check(dev_id); - SW_RTN_ON_ERROR(rv); - - HSL_REG_ENTRY_GET(rv, dev_id, ROUTER_PTCTRL1, 0, - (a_uint8_t *) (®), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - - if (FAL_NO_SOURCE_GUARD < mode) - { - return SW_BAD_PARAM; - } - - data = 0; - if (FAL_MAC_IP_GUARD == mode) - { - data = 1; - } - else if (FAL_MAC_IP_PORT_GUARD == mode) - { - data = 2; - } - else if (FAL_MAC_IP_VLAN_GUARD == mode) - { - data = 3; - } - else if (FAL_MAC_IP_PORT_VLAN_GUARD == mode) - { - data = 4; - } - reg &= (~(0x7 << (port_id * 3))); - reg |= ((data & 0x7) << (port_id * 3)); - - HSL_REG_ENTRY_SET(rv, dev_id, ROUTER_PTCTRL1, 0, - (a_uint8_t *) (®), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - - data = 1; - if (FAL_NO_SOURCE_GUARD == mode) - { - data = 0; - } - - HSL_REG_FIELD_SET(rv, dev_id, PORT_VLAN1, port_id, SP_CHECK_EN, - (a_uint8_t *) (&data), sizeof (a_uint32_t)); - return rv; -} - -static sw_error_t -_isisc_ip_source_guard_get(a_uint32_t dev_id, fal_port_t port_id, - fal_source_guard_mode_t * mode) -{ - sw_error_t rv; - a_uint32_t reg = 0, data; - - HSL_DEV_ID_CHECK(dev_id); - - rv = _isisc_ip_feature_check(dev_id); - SW_RTN_ON_ERROR(rv); - - HSL_REG_ENTRY_GET(rv, dev_id, ROUTER_PTCTRL1, 0, - (a_uint8_t *) (®), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - - data = (reg >> (port_id * 3)) & 0x7; - - *mode = FAL_NO_SOURCE_GUARD; - if (1 == data) - { - *mode = FAL_MAC_IP_GUARD; - } - else if (2 == data) - { - *mode = FAL_MAC_IP_PORT_GUARD; - } - else if (3 == data) - { - *mode = FAL_MAC_IP_VLAN_GUARD; - } - else if (4 == data) - { - *mode = FAL_MAC_IP_PORT_VLAN_GUARD; - } - - return SW_OK; -} - -static sw_error_t -_isisc_ip_unk_source_cmd_set(a_uint32_t dev_id, fal_fwd_cmd_t cmd) -{ - sw_error_t rv; - a_uint32_t data; - - HSL_DEV_ID_CHECK(dev_id); - - rv = _isisc_ip_feature_check(dev_id); - SW_RTN_ON_ERROR(rv); - - if (FAL_MAC_FRWRD == cmd) - { - data = 0; - } - else if (FAL_MAC_DROP == cmd) - { - data = 1; - } - else if (FAL_MAC_RDT_TO_CPU == cmd) - { - data = 2; - } - else - { - return SW_NOT_SUPPORTED; - } - - HSL_REG_FIELD_SET(rv, dev_id, FORWARD_CTL0, 0, IP_NOT_FOUND, - (a_uint8_t *) (&data), sizeof (a_uint32_t)); - return rv; -} - -static sw_error_t -_isisc_ip_unk_source_cmd_get(a_uint32_t dev_id, fal_fwd_cmd_t * cmd) -{ - sw_error_t rv; - a_uint32_t data = 0; - - HSL_DEV_ID_CHECK(dev_id); - - rv = _isisc_ip_feature_check(dev_id); - SW_RTN_ON_ERROR(rv); - - HSL_REG_FIELD_GET(rv, dev_id, FORWARD_CTL0, 0, IP_NOT_FOUND, - (a_uint8_t *) (&data), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - - if (0 == data) - { - *cmd = FAL_MAC_FRWRD; - } - else if (1 == data) - { - *cmd = FAL_MAC_DROP; - } - else - { - *cmd = FAL_MAC_RDT_TO_CPU; - } - - return SW_OK; -} - -static sw_error_t -_isisc_ip_arp_guard_set(a_uint32_t dev_id, fal_port_t port_id, - fal_source_guard_mode_t mode) -{ - sw_error_t rv; - a_uint32_t reg = 0, data; - - HSL_DEV_ID_CHECK(dev_id); - - rv = _isisc_ip_feature_check(dev_id); - SW_RTN_ON_ERROR(rv); - - HSL_DEV_ID_CHECK(dev_id); - - HSL_REG_ENTRY_GET(rv, dev_id, ROUTER_PTCTRL0, 0, - (a_uint8_t *) (®), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - - if (FAL_NO_SOURCE_GUARD < mode) - { - return SW_BAD_PARAM; - } - - data = 0; - if (FAL_MAC_IP_GUARD == mode) - { - data = 1; - } - else if (FAL_MAC_IP_PORT_GUARD == mode) - { - data = 2; - } - else if (FAL_MAC_IP_VLAN_GUARD == mode) - { - data = 3; - } - else if (FAL_MAC_IP_PORT_VLAN_GUARD == mode) - { - data = 4; - } - reg &= (~(0x7 << (port_id * 3))); - reg |= ((data & 0x7) << (port_id * 3)); - - HSL_REG_ENTRY_SET(rv, dev_id, ROUTER_PTCTRL0, 0, - (a_uint8_t *) (®), sizeof (a_uint32_t)); - return rv; -} - -static sw_error_t -_isisc_ip_arp_guard_get(a_uint32_t dev_id, fal_port_t port_id, - fal_source_guard_mode_t * mode) -{ - sw_error_t rv; - a_uint32_t reg = 0, data; - - HSL_DEV_ID_CHECK(dev_id); - - rv = _isisc_ip_feature_check(dev_id); - SW_RTN_ON_ERROR(rv); - - HSL_DEV_ID_CHECK(dev_id); - - HSL_REG_ENTRY_GET(rv, dev_id, ROUTER_PTCTRL0, 0, - (a_uint8_t *) (®), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - - data = (reg >> (port_id * 3)) & 0x7; - - *mode = FAL_NO_SOURCE_GUARD; - if (1 == data) - { - *mode = FAL_MAC_IP_GUARD; - } - else if (2 == data) - { - *mode = FAL_MAC_IP_PORT_GUARD; - } - else if (3 == data) - { - *mode = FAL_MAC_IP_VLAN_GUARD; - } - else if (4 == data) - { - *mode = FAL_MAC_IP_PORT_VLAN_GUARD; - } - - return SW_OK; -} - -static sw_error_t -_isisc_arp_unk_source_cmd_set(a_uint32_t dev_id, fal_fwd_cmd_t cmd) -{ - sw_error_t rv; - a_uint32_t data; - - HSL_DEV_ID_CHECK(dev_id); - - rv = _isisc_ip_feature_check(dev_id); - SW_RTN_ON_ERROR(rv); - - if (FAL_MAC_FRWRD == cmd) - { - data = 0; - } - else if (FAL_MAC_DROP == cmd) - { - data = 1; - } - else if (FAL_MAC_RDT_TO_CPU == cmd) - { - data = 2; - } - else - { - return SW_NOT_SUPPORTED; - } - - HSL_REG_FIELD_SET(rv, dev_id, FORWARD_CTL0, 0, ARP_NOT_FOUND, - (a_uint8_t *) (&data), sizeof (a_uint32_t)); - return rv; -} - -static sw_error_t -_isisc_arp_unk_source_cmd_get(a_uint32_t dev_id, fal_fwd_cmd_t * cmd) -{ - sw_error_t rv; - a_uint32_t data = 0; - - HSL_DEV_ID_CHECK(dev_id); - - rv = _isisc_ip_feature_check(dev_id); - SW_RTN_ON_ERROR(rv); - - HSL_REG_FIELD_GET(rv, dev_id, FORWARD_CTL0, 0, ARP_NOT_FOUND, - (a_uint8_t *) (&data), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - - if (0 == data) - { - *cmd = FAL_MAC_FRWRD; - } - else if (1 == data) - { - *cmd = FAL_MAC_DROP; - } - else - { - *cmd = FAL_MAC_RDT_TO_CPU; - } - - return SW_OK; -} - -static sw_error_t -_isisc_ip_route_status_set(a_uint32_t dev_id, a_bool_t enable) -{ - sw_error_t rv; - a_uint32_t data; - - HSL_DEV_ID_CHECK(dev_id); - - rv = _isisc_ip_feature_check(dev_id); - SW_RTN_ON_ERROR(rv); - - if (A_TRUE == enable) - { - data = 1; - } - else if (A_FALSE == enable) - { - data = 0; - } - else - { - return SW_BAD_PARAM; - } - - HSL_REG_FIELD_SET(rv, dev_id, ROUTER_CTRL, 0, ROUTER_EN, - (a_uint8_t *) (&data), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - - HSL_REG_FIELD_SET(rv, dev_id, MOD_ENABLE, 0, L3_EN, - (a_uint8_t *) (&data), sizeof (a_uint32_t)); - return rv; -} - -static sw_error_t -_isisc_ip_route_status_get(a_uint32_t dev_id, a_bool_t * enable) -{ - sw_error_t rv; - a_uint32_t route_en = 0, l3_en = 0; - - HSL_DEV_ID_CHECK(dev_id); - - rv = _isisc_ip_feature_check(dev_id); - SW_RTN_ON_ERROR(rv); - - HSL_REG_FIELD_GET(rv, dev_id, ROUTER_CTRL, 0, ROUTER_EN, - (a_uint8_t *) (&route_en), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - - HSL_REG_FIELD_GET(rv, dev_id, MOD_ENABLE, 0, L3_EN, - (a_uint8_t *) (&l3_en), sizeof (a_uint32_t)) - SW_RTN_ON_ERROR(rv); - - if (route_en && l3_en) - { - *enable = A_TRUE; - } - else - { - *enable = A_FALSE; - } - - return rv; -} - -static sw_error_t -_isisc_ip_intf_entry_add(a_uint32_t dev_id, fal_intf_mac_entry_t * entry) -{ - sw_error_t rv; - a_uint32_t i, j, found = 0, addr, tbl[3] = { 0 }; - fal_intf_mac_entry_t * intf_entry = NULL; - - HSL_DEV_ID_CHECK(dev_id); - - rv = _isisc_ip_feature_check(dev_id); - SW_RTN_ON_ERROR(rv); - - for (i = 0; i < ISISC_INTF_MAC_ADDR_NUM; i++) - { - if (isisc_mac_snap[dev_id] & (0x1 << i)) - { - intf_entry = &(isisc_intf_snap[dev_id][i]); - if ((entry->vid_low == intf_entry->vid_low) - && (entry->vid_high == intf_entry->vid_high)) - { - /* all same, return OK directly */ - if (!aos_mem_cmp(intf_entry, entry, sizeof(fal_intf_mac_entry_t))) - { - return SW_OK; - } - else - { - /* update entry */ - found = 1; - break; - } - } - else - { - /* entry VID cross border, not support */ - if ((entry->vid_low >= intf_entry->vid_low) && (entry->vid_low <= intf_entry->vid_high)) - { - return SW_BAD_PARAM; - } - - /* entry VID cross border, not support */ - if ((entry->vid_high >= intf_entry->vid_low) && (entry->vid_low <= intf_entry->vid_high)) - { - return SW_BAD_PARAM; - } - } - } - } - - if (!found) - { - for (i = 0; i < ISISC_INTF_MAC_ADDR_NUM; i++) - { - if (!(isisc_mac_snap[dev_id] & (0x1 << i))) - { - intf_entry = &(isisc_intf_snap[dev_id][i]); - break; - } - } - } - - if (ISISC_INTF_MAC_ADDR_NUM == i) - { - return SW_NO_RESOURCE; - } - - if ((A_FALSE == entry->ip4_route) && (A_FALSE == entry->ip6_route)) - { - return SW_NOT_SUPPORTED; - } - - if (512 <= (entry->vid_high - entry->vid_low)) - { - return SW_BAD_PARAM; - } - - SW_SET_REG_BY_FIELD(INTF_ADDR_ENTRY0, MAC_ADDR2, entry->mac_addr.uc[2], - tbl[0]); - SW_SET_REG_BY_FIELD(INTF_ADDR_ENTRY0, MAC_ADDR3, entry->mac_addr.uc[3], - tbl[0]); - SW_SET_REG_BY_FIELD(INTF_ADDR_ENTRY0, MAC_ADDR4, entry->mac_addr.uc[4], - tbl[0]); - SW_SET_REG_BY_FIELD(INTF_ADDR_ENTRY0, MAC_ADDR5, entry->mac_addr.uc[5], - tbl[0]); - SW_SET_REG_BY_FIELD(INTF_ADDR_ENTRY1, MAC_ADDR0, entry->mac_addr.uc[0], - tbl[1]); - SW_SET_REG_BY_FIELD(INTF_ADDR_ENTRY1, MAC_ADDR1, entry->mac_addr.uc[1], - tbl[1]); - - SW_SET_REG_BY_FIELD(INTF_ADDR_ENTRY1, VID_LOW, entry->vid_low, tbl[1]); - SW_SET_REG_BY_FIELD(INTF_ADDR_ENTRY1, VID_HIGH0, (entry->vid_high & 0xf), - tbl[1]); - SW_SET_REG_BY_FIELD(INTF_ADDR_ENTRY2, VID_HIGH1, (entry->vid_high >> 4), - tbl[2]); - - if (A_TRUE == entry->ip4_route) - { - SW_SET_REG_BY_FIELD(INTF_ADDR_ENTRY2, IP4_ROUTE, 1, tbl[2]); - } - - if (A_TRUE == entry->ip6_route) - { - SW_SET_REG_BY_FIELD(INTF_ADDR_ENTRY2, IP6_ROUTE, 1, tbl[2]); - } - - for (j = 0; j < 2; j++) - { - addr = ISISC_INTF_MAC_EDIT0_ADDR + (i << 4) + (j << 2); - HSL_REG_ENTRY_GEN_SET(rv, dev_id, addr, sizeof (a_uint32_t), - (a_uint8_t *) (&(tbl[j])), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - } - - for (j = 0; j < 3; j++) - { - addr = ISISC_INTF_MAC_TBL0_ADDR + (i << 4) + (j << 2); - HSL_REG_ENTRY_GEN_SET(rv, dev_id, addr, sizeof (a_uint32_t), - (a_uint8_t *) (&(tbl[j])), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - } - - isisc_mac_snap[dev_id] |= (0x1 << i); - *intf_entry = *entry; - entry->entry_id = i; - return SW_OK; -} - -static sw_error_t -_isisc_ip_intf_entry_del(a_uint32_t dev_id, a_uint32_t del_mode, - fal_intf_mac_entry_t * entry) -{ - sw_error_t rv; - a_uint32_t addr, tbl[3] = { 0 }; - - HSL_DEV_ID_CHECK(dev_id); - - rv = _isisc_ip_feature_check(dev_id); - SW_RTN_ON_ERROR(rv); - - if (!(FAL_IP_ENTRY_ID_EN & del_mode)) - { - return SW_NOT_SUPPORTED; - } - - if (ISISC_INTF_MAC_ADDR_NUM <= entry->entry_id) - { - return SW_BAD_PARAM; - } - - /* clear valid bits */ - addr = ISISC_INTF_MAC_TBL2_ADDR + (entry->entry_id << 4); - HSL_REG_ENTRY_GEN_SET(rv, dev_id, addr, sizeof (a_uint32_t), - (a_uint8_t *) (&(tbl[2])), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - - isisc_mac_snap[dev_id] &= (~(0x1 << entry->entry_id)); - return SW_OK; -} - -static sw_error_t -_isisc_ip_intf_entry_next(a_uint32_t dev_id, a_uint32_t next_mode, - fal_intf_mac_entry_t * entry) -{ - sw_error_t rv; - a_uint32_t i, j, idx, addr, tbl[3] = { 0 }; - - HSL_DEV_ID_CHECK(dev_id); - - rv = _isisc_ip_feature_check(dev_id); - SW_RTN_ON_ERROR(rv); - - if (FAL_NEXT_ENTRY_FIRST_ID == entry->entry_id) - { - idx = 0; - } - else - { - if ((ISISC_INTF_MAC_ADDR_NUM - 1) == entry->entry_id) - { - return SW_NO_MORE; - } - else - { - idx = entry->entry_id + 1; - } - } - - for (i = idx; i < ISISC_INTF_MAC_ADDR_NUM; i++) - { - if (isisc_mac_snap[dev_id] & (0x1 << i)) - { - break; - } - } - - if (ISISC_INTF_MAC_ADDR_NUM == i) - { - return SW_NO_MORE; - } - - for (j = 0; j < 3; j++) - { - addr = ISISC_INTF_MAC_TBL0_ADDR + (i << 4) + (j << 2); - HSL_REG_ENTRY_GEN_GET(rv, dev_id, addr, sizeof (a_uint32_t), - (a_uint8_t *) (&(tbl[j])), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - } - - aos_mem_zero(entry, sizeof (fal_intf_mac_entry_t)); - - SW_GET_FIELD_BY_REG(INTF_ADDR_ENTRY0, MAC_ADDR2, entry->mac_addr.uc[2], - tbl[0]); - SW_GET_FIELD_BY_REG(INTF_ADDR_ENTRY0, MAC_ADDR3, entry->mac_addr.uc[3], - tbl[0]); - SW_GET_FIELD_BY_REG(INTF_ADDR_ENTRY0, MAC_ADDR4, entry->mac_addr.uc[4], - tbl[0]); - SW_GET_FIELD_BY_REG(INTF_ADDR_ENTRY0, MAC_ADDR5, entry->mac_addr.uc[5], - tbl[0]); - SW_GET_FIELD_BY_REG(INTF_ADDR_ENTRY1, MAC_ADDR0, entry->mac_addr.uc[0], - tbl[1]); - SW_GET_FIELD_BY_REG(INTF_ADDR_ENTRY1, MAC_ADDR1, entry->mac_addr.uc[1], - tbl[1]); - - SW_GET_FIELD_BY_REG(INTF_ADDR_ENTRY1, VID_LOW, entry->vid_low, tbl[1]); - SW_GET_FIELD_BY_REG(INTF_ADDR_ENTRY1, VID_HIGH0, j, tbl[1]); - entry->vid_high = j & 0xf; - SW_GET_FIELD_BY_REG(INTF_ADDR_ENTRY2, VID_HIGH1, j, tbl[2]); - entry->vid_high |= ((j & 0xff) << 4); - - SW_GET_FIELD_BY_REG(INTF_ADDR_ENTRY2, IP4_ROUTE, j, tbl[2]); - if (j) - { - entry->ip4_route = A_TRUE; - } - - SW_GET_FIELD_BY_REG(INTF_ADDR_ENTRY2, IP6_ROUTE, j, tbl[2]); - if (j) - { - entry->ip6_route = A_TRUE; - } - - entry->entry_id = i; - return SW_OK; -} - -#define ISISC_WCMP_ENTRY_MAX_ID 3 -#define ISISC_WCMP_HASH_MAX_NUM 16 -#define ISISC_IP_ENTRY_MAX_ID 127 - -#define ISISC_WCMP_HASH_TBL_ADDR 0x0e10 -#define ISISC_WCMP_NHOP_TBL_ADDR 0x0e20 - -#if 0 -static sw_error_t -_isisc_ip_wcmp_entry_set(a_uint32_t dev_id, a_uint32_t wcmp_id, fal_ip_wcmp_t * wcmp) -{ - sw_error_t rv; - a_uint32_t i, j, addr, data; - a_uint8_t idx, ptr[4] = { 0 }, pos[16] = { 0 }; - - HSL_DEV_ID_CHECK(dev_id); - - rv = _isisc_ip_feature_check(dev_id); - SW_RTN_ON_ERROR(rv); - - if (ISISC_WCMP_ENTRY_MAX_ID < wcmp_id) - { - return SW_BAD_PARAM; - } - - if (ISISC_WCMP_HASH_MAX_NUM < wcmp->nh_nr) - { - return SW_BAD_PARAM; - } - - for (i = 0; i < wcmp->nh_nr; i++) - { - if (ISISC_IP_ENTRY_MAX_ID < wcmp->nh_id[i]) - { - return SW_BAD_PARAM; - } - - idx = 4; - for (j = 0; j < 4; j++) - { - if (ptr[j] & 0x80) - { - if ((ptr[j] & 0x7f) == wcmp->nh_id[i]) - { - idx = j; - break; - } - } - else - { - idx = j; - } - } - - if (4 == idx) - { - return SW_BAD_PARAM; - } - else - { - ptr[idx] = (wcmp->nh_id[i] & 0x7f) | 0x80; - pos[i] = idx; - } - } - - data = 0; - for (j = 0; j < 4; j++) - { - data |= (ptr[j] << (j << 3)); - } - - addr = ISISC_WCMP_NHOP_TBL_ADDR + (wcmp_id << 2); - HSL_REG_ENTRY_GEN_SET(rv, dev_id, addr, sizeof (a_uint32_t), - (a_uint8_t *) (&data), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - - data = 0; - for (j = 0; j < 16; j++) - { - data |= (pos[j] << (j << 1)); - } - - addr = ISISC_WCMP_HASH_TBL_ADDR + (wcmp_id << 2); - HSL_REG_ENTRY_GEN_SET(rv, dev_id, addr, sizeof (a_uint32_t), - (a_uint8_t *) (&data), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - - return SW_OK; -} - -static sw_error_t -_isisc_ip_wcmp_entry_get(a_uint32_t dev_id, a_uint32_t wcmp_id, fal_ip_wcmp_t * wcmp) -{ - sw_error_t rv; - a_uint32_t i, addr, data = 0; - a_uint8_t ptr[4] = { 0 }, pos[16] = { 0 }; - - HSL_DEV_ID_CHECK(dev_id); - - rv = _isisc_ip_feature_check(dev_id); - SW_RTN_ON_ERROR(rv); - - if (ISISC_WCMP_ENTRY_MAX_ID < wcmp_id) - { - return SW_BAD_PARAM; - } - - wcmp->nh_nr = ISISC_WCMP_HASH_MAX_NUM; - - addr = ISISC_WCMP_NHOP_TBL_ADDR + (wcmp_id << 2); - HSL_REG_ENTRY_GEN_GET(rv, dev_id, addr, sizeof (a_uint32_t), - (a_uint8_t *) (&data), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - - for (i = 0; i < 4; i++) - { - ptr[i] = (data >> (i << 3)) & 0x7f; - } - - addr = ISISC_WCMP_HASH_TBL_ADDR + (wcmp_id << 2); - HSL_REG_ENTRY_GEN_GET(rv, dev_id, addr, sizeof (a_uint32_t), - (a_uint8_t *) (&data), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - - for (i = 0; i < 16; i++) - { - pos[i] = (data >> (i << 1)) & 0x3; - } - - for (i = 0; i < 16; i++) - { - wcmp->nh_id[i] = ptr[pos[i]]; - } - - return SW_OK; -} -#endif - -static sw_error_t -_isisc_ip_wcmp_hash_mode_set(a_uint32_t dev_id, a_uint32_t hash_mode) -{ - sw_error_t rv; - a_uint32_t data = 0; - - HSL_REG_ENTRY_GET(rv, dev_id, ROUTER_CTRL, 0, - (a_uint8_t *) (&data), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - - if (FAL_WCMP_HASH_KEY_SIP & hash_mode) - { - SW_SET_REG_BY_FIELD(ROUTER_CTRL, WCMP_HAHS_SIP, 1, data); - } - else - { - SW_SET_REG_BY_FIELD(ROUTER_CTRL, WCMP_HAHS_SIP, 0, data); - } - - if (FAL_WCMP_HASH_KEY_DIP & hash_mode) - { - SW_SET_REG_BY_FIELD(ROUTER_CTRL, WCMP_HAHS_DIP, 1, data); - } - else - { - SW_SET_REG_BY_FIELD(ROUTER_CTRL, WCMP_HAHS_DIP, 0, data); - } - - if (FAL_WCMP_HASH_KEY_SPORT & hash_mode) - { - SW_SET_REG_BY_FIELD(ROUTER_CTRL, WCMP_HAHS_SP, 1, data); - } - else - { - SW_SET_REG_BY_FIELD(ROUTER_CTRL, WCMP_HAHS_SP, 0, data); - } - - if (FAL_WCMP_HASH_KEY_DPORT & hash_mode) - { - SW_SET_REG_BY_FIELD(ROUTER_CTRL, WCMP_HAHS_DP, 1, data); - } - else - { - SW_SET_REG_BY_FIELD(ROUTER_CTRL, WCMP_HAHS_DP, 0, data); - } - - - HSL_REG_ENTRY_SET(rv, dev_id, ROUTER_CTRL, 0, - (a_uint8_t *) (&data), sizeof (a_uint32_t)); - return rv; -} - -static sw_error_t -_isisc_ip_wcmp_hash_mode_get(a_uint32_t dev_id, a_uint32_t * hash_mode) -{ - sw_error_t rv; - a_uint32_t data = 0, field; - - *hash_mode = 0; - - HSL_REG_ENTRY_GET(rv, dev_id, ROUTER_CTRL, 0, - (a_uint8_t *) (&data), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - - SW_GET_FIELD_BY_REG(ROUTER_CTRL, WCMP_HAHS_SIP, field, data); - if (field) - { - *hash_mode |= FAL_WCMP_HASH_KEY_SIP; - } - - SW_GET_FIELD_BY_REG(ROUTER_CTRL, WCMP_HAHS_DIP, field, data); - if (field) - { - *hash_mode |= FAL_WCMP_HASH_KEY_DIP; - } - - SW_GET_FIELD_BY_REG(ROUTER_CTRL, WCMP_HAHS_SP, field, data); - if (field) - { - *hash_mode |= FAL_WCMP_HASH_KEY_SPORT; - } - - SW_GET_FIELD_BY_REG(ROUTER_CTRL, WCMP_HAHS_DP, field, data); - if (field) - { - *hash_mode |= FAL_WCMP_HASH_KEY_DPORT; - } - - return SW_OK; -} - -sw_error_t -isisc_ip_reset(a_uint32_t dev_id) -{ - sw_error_t rv; - a_uint32_t i, addr, data = 0; - - HSL_DEV_ID_CHECK(dev_id); - - rv = _isisc_ip_feature_check(dev_id); - SW_RTN_ON_ERROR(rv); - - HSL_REG_ENTRY_SET(rv, dev_id, HOST_ENTRY7, 0, (a_uint8_t *) (&data), - sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - - rv = _isisc_host_entry_commit(dev_id, ISISC_ENTRY_ARP, ISISC_HOST_ENTRY_FLUSH); - SW_RTN_ON_ERROR(rv); - - isisc_mac_snap[dev_id] = 0; - for (i = 0; i < ISISC_INTF_MAC_ADDR_NUM; i++) - { - addr = ISISC_INTF_MAC_TBL2_ADDR + (i << 4); - HSL_REG_ENTRY_GEN_SET(rv, dev_id, addr, sizeof (a_uint32_t), - (a_uint8_t *) (&data), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - } - - return SW_OK; -} - -/** - * @brief Add one host entry to one particular device. - * @details Comments: - * For ISIS the intf_id parameter in host_entry means vlan id. - Before host entry added related interface entry and ip6 base address - must be set at first. - Hardware entry id will be returned. - * @param[in] dev_id device id - * @param[in] host_entry host entry parameter - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -isisc_ip_host_add(a_uint32_t dev_id, fal_host_entry_t * host_entry) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _isisc_ip_host_add(dev_id, host_entry); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Delete one host entry from one particular device. - * @details Comments: - * For ISIS the intf_id parameter in host_entry means vlan id. - Before host entry deleted related interface entry and ip6 base address - must be set atfirst. - For del_mode please refer IP entry operation flags. - * @param[in] dev_id device id - * @param[in] del_mode delete operation mode - * @param[in] host_entry host entry parameter - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -isisc_ip_host_del(a_uint32_t dev_id, a_uint32_t del_mode, - fal_host_entry_t * host_entry) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _isisc_ip_host_del(dev_id, del_mode, host_entry); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Get one host entry from one particular device. - * @details Comments: - * For ISIS the intf_id parameter in host_entry means vlan id. - Before host entry deleted related interface entry and ip6 base address - must be set atfirst. - For get_mode please refer IP entry operation flags. - * @param[in] dev_id device id - * @param[in] get_mode get operation mode - * @param[out] host_entry host entry parameter - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -isisc_ip_host_get(a_uint32_t dev_id, a_uint32_t get_mode, - fal_host_entry_t * host_entry) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _isisc_ip_host_get(dev_id, get_mode, host_entry); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Next one host entry from one particular device. - * @details Comments: - * For ISIS the intf_id parameter in host_entry means vlan id. - Before host entry deleted related interface entry and ip6 base address - must be set atfirst. - For next_mode please refer IP entry operation flags. - For get the first entry please set entry id as FAL_NEXT_ENTRY_FIRST_ID - * @param[in] dev_id device id - * @param[in] next_mode next operation mode - * @param[out] host_entry host entry parameter - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -isisc_ip_host_next(a_uint32_t dev_id, a_uint32_t next_mode, - fal_host_entry_t * host_entry) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _isisc_ip_host_next(dev_id, next_mode, host_entry); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Bind one counter entry to one host entry on one particular device. - * @param[in] dev_id device id - * @param[in] entry_id host entry id - * @param[in] cnt_id counter entry id - * @param[in] enable A_TRUE means bind, A_FALSE means unbind - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -isisc_ip_host_counter_bind(a_uint32_t dev_id, a_uint32_t entry_id, - a_uint32_t cnt_id, a_bool_t enable) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _isisc_ip_host_counter_bind(dev_id, entry_id, cnt_id, enable); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Bind one pppoe session entry to one host entry on one particular device. - * @param[in] dev_id device id - * @param[in] entry_id host entry id - * @param[in] pppoe_id pppoe session entry id - * @param[in] enable A_TRUE means bind, A_FALSE means unbind - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -isisc_ip_host_pppoe_bind(a_uint32_t dev_id, a_uint32_t entry_id, - a_uint32_t pppoe_id, a_bool_t enable) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _isisc_ip_host_pppoe_bind(dev_id, entry_id, pppoe_id, enable); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Set arp packets type to learn on one particular port. - * @param[in] dev_id device id - * @param[in] port_id port id - * @param[in] flags arp type FAL_ARP_LEARN_REQ and/or FAL_ARP_LEARN_ACK - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -isisc_ip_pt_arp_learn_set(a_uint32_t dev_id, fal_port_t port_id, - a_uint32_t flags) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _isisc_ip_pt_arp_learn_set(dev_id, port_id, flags); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Get arp packets type to learn on one particular port. - * @param[in] dev_id device id - * @param[in] port_id port id - * @param[out] flags arp type FAL_ARP_LEARN_REQ and/or FAL_ARP_LEARN_ACK - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -isisc_ip_pt_arp_learn_get(a_uint32_t dev_id, fal_port_t port_id, - a_uint32_t * flags) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _isisc_ip_pt_arp_learn_get(dev_id, port_id, flags); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Set arp packets type to learn on one particular device. - * @param[in] dev_id device id - * @param[in] mode learning mode - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -isisc_ip_arp_learn_set(a_uint32_t dev_id, fal_arp_learn_mode_t mode) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _isisc_ip_arp_learn_set(dev_id, mode); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Get arp packets type to learn on one particular device. - * @param[in] dev_id device id - * @param[out] mode learning mode - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -isisc_ip_arp_learn_get(a_uint32_t dev_id, fal_arp_learn_mode_t * mode) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _isisc_ip_arp_learn_get(dev_id, mode); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Set ip packets source guarding mode on one particular port. - * @param[in] dev_id device id - * @param[in] port_id port id - * @param[in] mode source guarding mode - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -isisc_ip_source_guard_set(a_uint32_t dev_id, fal_port_t port_id, - fal_source_guard_mode_t mode) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _isisc_ip_source_guard_set(dev_id, port_id, mode); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Get ip packets source guarding mode on one particular port. - * @param[in] dev_id device id - * @param[in] port_id port id - * @param[out] mode source guarding mode - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -isisc_ip_source_guard_get(a_uint32_t dev_id, fal_port_t port_id, - fal_source_guard_mode_t * mode) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _isisc_ip_source_guard_get(dev_id, port_id, mode); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Set unkonw source ip packets forwarding command on one particular device. - * @details Comments: - * This settin is no meaning when ip source guard not enable - * @param[in] dev_id device id - * @param[in] cmd forwarding command - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -isisc_ip_unk_source_cmd_set(a_uint32_t dev_id, fal_fwd_cmd_t cmd) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _isisc_ip_unk_source_cmd_set(dev_id, cmd); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Get unkonw source ip packets forwarding command on one particular device. - * @param[in] dev_id device id - * @param[out] cmd forwarding command - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -isisc_ip_unk_source_cmd_get(a_uint32_t dev_id, fal_fwd_cmd_t * cmd) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _isisc_ip_unk_source_cmd_get(dev_id, cmd); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Set arp packets source guarding mode on one particular port. - * @param[in] dev_id device id - * @param[in] port_id port id - * @param[in] mode source guarding mode - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -isisc_ip_arp_guard_set(a_uint32_t dev_id, fal_port_t port_id, - fal_source_guard_mode_t mode) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _isisc_ip_arp_guard_set(dev_id, port_id, mode); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Get arp packets source guarding mode on one particular port. - * @param[in] dev_id device id - * @param[in] port_id port id - * @param[out] mode source guarding mode - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -isisc_ip_arp_guard_get(a_uint32_t dev_id, fal_port_t port_id, - fal_source_guard_mode_t * mode) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _isisc_ip_arp_guard_get(dev_id, port_id, mode); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Set unkonw source arp packets forwarding command on one particular device. - * @details Comments: - * This settin is no meaning when arp source guard not enable - * @param[in] dev_id device id - * @param[in] cmd forwarding command - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -isisc_arp_unk_source_cmd_set(a_uint32_t dev_id, fal_fwd_cmd_t cmd) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _isisc_arp_unk_source_cmd_set(dev_id, cmd); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Get unkonw source arp packets forwarding command on one particular device. - * @param[in] dev_id device id - * @param[out] cmd forwarding command - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -isisc_arp_unk_source_cmd_get(a_uint32_t dev_id, fal_fwd_cmd_t * cmd) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _isisc_arp_unk_source_cmd_get(dev_id, cmd); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Set IP unicast routing status on one particular device. - * @param[in] dev_id device id - * @param[in] enable A_TRUE or A_FALSE - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -isisc_ip_route_status_set(a_uint32_t dev_id, a_bool_t enable) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _isisc_ip_route_status_set(dev_id, enable); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Get IP unicast routing status on one particular device. - * @param[in] dev_id device id - * @param[out] enable A_TRUE or A_FALSE - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -isisc_ip_route_status_get(a_uint32_t dev_id, a_bool_t * enable) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _isisc_ip_route_status_get(dev_id, enable); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Add one interface entry to one particular device. - * @param[in] dev_id device id - * @param[in] entry interface entry - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -isisc_ip_intf_entry_add(a_uint32_t dev_id, fal_intf_mac_entry_t * entry) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _isisc_ip_intf_entry_add(dev_id, entry); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Delete one interface entry from one particular device. - * @param[in] dev_id device id - * @param[in] del_mode delete operation mode - * @param[in] entry interface entry - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -isisc_ip_intf_entry_del(a_uint32_t dev_id, a_uint32_t del_mode, - fal_intf_mac_entry_t * entry) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _isisc_ip_intf_entry_del(dev_id, del_mode, entry); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Next one interface entry from one particular device. - * @param[in] dev_id device id - * @param[in] next_mode next operation mode - * @param[out] entry interface entry - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -isisc_ip_intf_entry_next(a_uint32_t dev_id, a_uint32_t next_mode, - fal_intf_mac_entry_t * entry) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _isisc_ip_intf_entry_next(dev_id, next_mode, entry); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Set IP host entry aging time on one particular device. - * @details Comments: - * This operation will set dynamic entry aging time on a particular device. - * The unit of time is second. Because different device has differnet - * hardware granularity function will return actual time in hardware. - * @param[in] dev_id device id - * @param[in] time aging time - * @param[out] time actual aging time - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -isisc_ip_age_time_set(a_uint32_t dev_id, a_uint32_t * time) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _isisc_ip_age_time_set(dev_id, time); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Get IP host entry aging time on one particular device. - * @param[in] dev_id device id - * @param[out] time aging time - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -isisc_ip_age_time_get(a_uint32_t dev_id, a_uint32_t * time) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _isisc_ip_age_time_get(dev_id, time); - HSL_API_UNLOCK; - return rv; -} - -#if 0 -/** - * @brief Set IP WCMP table one particular device. - * @details Comments: - * Hardware only support 0 - 15 hash values and 4 different host tables. - * @param[in] dev_id device id - * @param[in] wcmp_id wcmp entry id - * @param[in] wcmp wcmp entry - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -isisc_ip_wcmp_entry_set(a_uint32_t dev_id, a_uint32_t wcmp_id, fal_ip_wcmp_t * wcmp) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _isisc_ip_wcmp_entry_set(dev_id, wcmp_id, wcmp); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Get IP WCMP table one particular device. - * @details Comments: - * Hardware only support 0 - 15 hash values and 4 different host tables. - * @param[in] dev_id device id - * @param[in] wcmp_id wcmp entry id - * @param[out] wcmp wcmp entry - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -isisc_ip_wcmp_entry_get(a_uint32_t dev_id, a_uint32_t wcmp_id, fal_ip_wcmp_t * wcmp) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _isisc_ip_wcmp_entry_get(dev_id, wcmp_id, wcmp); - HSL_API_UNLOCK; - return rv; -} -#endif - -/** - * @brief Set IP WCMP hash key mode. - * @param[in] dev_id device id - * @param[in] hash_mode hash mode - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -isisc_ip_wcmp_hash_mode_set(a_uint32_t dev_id, a_uint32_t hash_mode) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _isisc_ip_wcmp_hash_mode_set(dev_id, hash_mode); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Get IP WCMP hash key mode. - * @param[in] dev_id device id - * @param[out] hash_mode hash mode - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -isisc_ip_wcmp_hash_mode_get(a_uint32_t dev_id, a_uint32_t * hash_mode) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _isisc_ip_wcmp_hash_mode_get(dev_id, hash_mode); - HSL_API_UNLOCK; - return rv; -} - -sw_error_t -isisc_ip_init(a_uint32_t dev_id) -{ - sw_error_t rv; - - HSL_DEV_ID_CHECK(dev_id); - - rv = isisc_ip_reset(dev_id); - SW_RTN_ON_ERROR(rv); - -#ifndef HSL_STANDALONG - { - hsl_api_t *p_api; - - SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id)); - - p_api->ip_host_add = isisc_ip_host_add; - p_api->ip_host_del = isisc_ip_host_del; - p_api->ip_host_get = isisc_ip_host_get; - p_api->ip_host_next = isisc_ip_host_next; - p_api->ip_host_counter_bind = isisc_ip_host_counter_bind; - p_api->ip_host_pppoe_bind = isisc_ip_host_pppoe_bind; - p_api->ip_pt_arp_learn_set = isisc_ip_pt_arp_learn_set; - p_api->ip_pt_arp_learn_get = isisc_ip_pt_arp_learn_get; - p_api->ip_arp_learn_set = isisc_ip_arp_learn_set; - p_api->ip_arp_learn_get = isisc_ip_arp_learn_get; - p_api->ip_source_guard_set = isisc_ip_source_guard_set; - p_api->ip_source_guard_get = isisc_ip_source_guard_get; - p_api->ip_unk_source_cmd_set = isisc_ip_unk_source_cmd_set; - p_api->ip_unk_source_cmd_get = isisc_ip_unk_source_cmd_get; - p_api->ip_arp_guard_set = isisc_ip_arp_guard_set; - p_api->ip_arp_guard_get = isisc_ip_arp_guard_get; - p_api->arp_unk_source_cmd_set = isisc_arp_unk_source_cmd_set; - p_api->arp_unk_source_cmd_get = isisc_arp_unk_source_cmd_get; - p_api->ip_route_status_set = isisc_ip_route_status_set; - p_api->ip_route_status_get = isisc_ip_route_status_get; - p_api->ip_intf_entry_add = isisc_ip_intf_entry_add; - p_api->ip_intf_entry_del = isisc_ip_intf_entry_del; - p_api->ip_intf_entry_next = isisc_ip_intf_entry_next; - p_api->ip_age_time_set = isisc_ip_age_time_set; - p_api->ip_age_time_get = isisc_ip_age_time_get; - p_api->ip_wcmp_hash_mode_set = isisc_ip_wcmp_hash_mode_set; - p_api->ip_wcmp_hash_mode_get = isisc_ip_wcmp_hash_mode_get; - } -#endif - - return SW_OK; -} - -/** - * @} - */ - diff --git a/feeds/ipq807x/qca-ssdk/src/src/hsl/isisc/isisc_leaky.c b/feeds/ipq807x/qca-ssdk/src/src/hsl/isisc/isisc_leaky.c deleted file mode 100755 index 14a3ddaf8..000000000 --- a/feeds/ipq807x/qca-ssdk/src/src/hsl/isisc/isisc_leaky.c +++ /dev/null @@ -1,526 +0,0 @@ -/* - * Copyright (c) 2012, 2016 The Linux Foundation. All rights reserved. - * Permission to use, copy, modify, and/or distribute this software for - * any purpose with or without fee is hereby granted, provided that the - * above copyright notice and this permission notice appear in all copies. - * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES - * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR - * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES - * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN - * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT - * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. - */ - - -/** - * @defgroup isisc_leaky ISISC_LEAKY - * @{ - */ -#include "sw.h" -#include "hsl.h" -#include "hsl_dev.h" -#include "hsl_port_prop.h" -#include "isisc_leaky.h" -#include "isisc_reg.h" - -static sw_error_t -_isisc_uc_leaky_mode_set(a_uint32_t dev_id, - fal_leaky_ctrl_mode_t ctrl_mode) -{ - a_uint32_t data; - sw_error_t rv; - - HSL_DEV_ID_CHECK(dev_id); - - if (FAL_LEAKY_PORT_CTRL == ctrl_mode) - { - data = 0; - } - else if (FAL_LEAKY_FDB_CTRL == ctrl_mode) - { - data = 1; - } - else - { - return SW_BAD_PARAM; - } - - HSL_REG_FIELD_SET(rv, dev_id, FORWARD_CTL0, 0, ARL_UNI_LEAKY, - (a_uint8_t *) (&data), sizeof (a_uint32_t)); - return rv; -} - -static sw_error_t -_isisc_uc_leaky_mode_get(a_uint32_t dev_id, - fal_leaky_ctrl_mode_t *ctrl_mode) -{ - a_uint32_t data = 0; - sw_error_t rv; - - HSL_DEV_ID_CHECK(dev_id); - - HSL_REG_FIELD_GET(rv, dev_id, FORWARD_CTL0, 0, ARL_UNI_LEAKY, - (a_uint8_t *) (&data), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - - if (1 == data) - { - *ctrl_mode = FAL_LEAKY_FDB_CTRL; - } - else - { - *ctrl_mode = FAL_LEAKY_PORT_CTRL; - } - - return SW_OK; -} - -static sw_error_t -_isisc_mc_leaky_mode_set(a_uint32_t dev_id, - fal_leaky_ctrl_mode_t ctrl_mode) -{ - a_uint32_t data; - sw_error_t rv; - - HSL_DEV_ID_CHECK(dev_id); - - if (FAL_LEAKY_PORT_CTRL == ctrl_mode) - { - data = 0; - } - else if (FAL_LEAKY_FDB_CTRL == ctrl_mode) - { - data = 1; - } - else - { - return SW_BAD_PARAM; - } - - HSL_REG_FIELD_SET(rv, dev_id, FORWARD_CTL0, 0, ARL_MUL_LEAKY, - (a_uint8_t *) (&data), sizeof (a_uint32_t)); - return rv; -} - -static sw_error_t -_isisc_mc_leaky_mode_get(a_uint32_t dev_id, - fal_leaky_ctrl_mode_t *ctrl_mode) -{ - a_uint32_t data = 0; - sw_error_t rv; - - HSL_DEV_ID_CHECK(dev_id); - - HSL_REG_FIELD_GET(rv, dev_id, FORWARD_CTL0, 0, ARL_MUL_LEAKY, - (a_uint8_t *) (&data), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - - if (1 == data) - { - *ctrl_mode = FAL_LEAKY_FDB_CTRL; - } - else - { - *ctrl_mode = FAL_LEAKY_PORT_CTRL; - } - - return SW_OK; -} - -static sw_error_t -_isisc_port_arp_leaky_set(a_uint32_t dev_id, fal_port_t port_id, - a_bool_t enable) -{ - a_uint32_t data; - sw_error_t rv; - - HSL_DEV_ID_CHECK(dev_id); - - if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU)) - { - return SW_BAD_PARAM; - } - - if (A_TRUE == enable) - { - data = 1; - } - else if (A_FALSE == enable) - { - data = 0; - } - else - { - return SW_BAD_PARAM; - } - - HSL_REG_FIELD_SET(rv, dev_id, PORT_LOOKUP_CTL, port_id, ARP_LEAKY_EN, - (a_uint8_t *) (&data), sizeof (a_uint32_t)); - return rv; -} - -static sw_error_t -_isisc_port_arp_leaky_get(a_uint32_t dev_id, fal_port_t port_id, - a_bool_t *enable) -{ - a_uint32_t data = 0; - sw_error_t rv; - - HSL_DEV_ID_CHECK(dev_id); - - if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU)) - { - return SW_BAD_PARAM; - } - - HSL_REG_FIELD_GET(rv, dev_id, PORT_LOOKUP_CTL, port_id, ARP_LEAKY_EN, - (a_uint8_t *) (&data), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - - if (1 == data) - { - *enable = A_TRUE; - } - else - { - *enable = A_FALSE; - } - - return SW_OK; -} - -static sw_error_t -_isisc_port_uc_leaky_set(a_uint32_t dev_id, fal_port_t port_id, - a_bool_t enable) -{ - a_uint32_t data; - sw_error_t rv; - - HSL_DEV_ID_CHECK(dev_id); - - if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU)) - { - return SW_BAD_PARAM; - } - - if (A_TRUE == enable) - { - data = 1; - } - else if (A_FALSE == enable) - { - data = 0; - } - else - { - return SW_BAD_PARAM; - } - - HSL_REG_FIELD_SET(rv, dev_id, PORT_LOOKUP_CTL, port_id, UNI_LEAKY_EN, - (a_uint8_t *) (&data), sizeof (a_uint32_t)); - return rv; -} - -static sw_error_t -_isisc_port_uc_leaky_get(a_uint32_t dev_id, fal_port_t port_id, - a_bool_t *enable) -{ - a_uint32_t data = 0; - sw_error_t rv; - - HSL_DEV_ID_CHECK(dev_id); - - if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU)) - { - return SW_BAD_PARAM; - } - - HSL_REG_FIELD_GET(rv, dev_id, PORT_LOOKUP_CTL, port_id, UNI_LEAKY_EN, - (a_uint8_t *) (&data), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - - if (1 == data) - { - *enable = A_TRUE; - } - else - { - *enable = A_FALSE; - } - - return SW_OK; -} - -static sw_error_t -_isisc_port_mc_leaky_set(a_uint32_t dev_id, fal_port_t port_id, - a_bool_t enable) -{ - a_uint32_t data; - sw_error_t rv; - - HSL_DEV_ID_CHECK(dev_id); - - if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU)) - { - return SW_BAD_PARAM; - } - - if (A_TRUE == enable) - { - data = 1; - } - else if (A_FALSE == enable) - { - data = 0; - } - else - { - return SW_BAD_PARAM; - } - - HSL_REG_FIELD_SET(rv, dev_id, PORT_LOOKUP_CTL, port_id, MUL_LEAKY_EN, - (a_uint8_t *) (&data), sizeof (a_uint32_t)); - return rv; -} - -static sw_error_t -_isisc_port_mc_leaky_get(a_uint32_t dev_id, fal_port_t port_id, - a_bool_t *enable) -{ - a_uint32_t data = 0; - sw_error_t rv; - - HSL_DEV_ID_CHECK(dev_id); - - if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU)) - { - return SW_BAD_PARAM; - } - - HSL_REG_FIELD_GET(rv, dev_id, PORT_LOOKUP_CTL, port_id, MUL_LEAKY_EN, - (a_uint8_t *) (&data), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - - if (1 == data) - { - *enable = A_TRUE; - } - else - { - *enable = A_FALSE; - } - - return SW_OK; -} - -/** -* @brief Set unicast packets leaky control mode on a particular device. -* @param[in] dev_id device id -* @param[in] ctrl_mode leaky control mode -* @return SW_OK or error code -*/ -HSL_LOCAL sw_error_t -isisc_uc_leaky_mode_set(a_uint32_t dev_id, - fal_leaky_ctrl_mode_t ctrl_mode) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _isisc_uc_leaky_mode_set(dev_id, ctrl_mode); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Get unicast packets leaky control mode on a particular device. - * @param[in] dev_id device id - * @param[out] ctrl_mode leaky control mode - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -isisc_uc_leaky_mode_get(a_uint32_t dev_id, - fal_leaky_ctrl_mode_t *ctrl_mode) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _isisc_uc_leaky_mode_get(dev_id, ctrl_mode); - HSL_API_UNLOCK; - return rv; -} - -/** -* @brief Set multicast packets leaky control mode on a particular device. -* @param[in] dev_id device id -* @param[in] ctrl_mode leaky control mode -* @return SW_OK or error code -*/ -HSL_LOCAL sw_error_t -isisc_mc_leaky_mode_set(a_uint32_t dev_id, - fal_leaky_ctrl_mode_t ctrl_mode) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _isisc_mc_leaky_mode_set(dev_id, ctrl_mode); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Get multicast packets leaky control mode on a particular device. - * @param[in] dev_id device id - * @param[out] ctrl_mode leaky control mode - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -isisc_mc_leaky_mode_get(a_uint32_t dev_id, - fal_leaky_ctrl_mode_t *ctrl_mode) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _isisc_mc_leaky_mode_get(dev_id, ctrl_mode); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Set arp packets leaky status on a particular port. - * @param[in] dev_id device id - * @param[in] enable A_TRUE or A_FALSE - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -isisc_port_arp_leaky_set(a_uint32_t dev_id, fal_port_t port_id, - a_bool_t enable) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _isisc_port_arp_leaky_set(dev_id, port_id, enable); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Get arp packets leaky status on a particular port. - * @param[in] dev_id device id - * @param[out] enable A_TRUE or A_FALSE - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -isisc_port_arp_leaky_get(a_uint32_t dev_id, fal_port_t port_id, - a_bool_t *enable) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _isisc_port_arp_leaky_get(dev_id, port_id, enable); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Set unicast packets leaky status on a particular port. - * @param[in] dev_id device id - * @param[in] enable A_TRUE or A_FALSE - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -isisc_port_uc_leaky_set(a_uint32_t dev_id, fal_port_t port_id, - a_bool_t enable) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _isisc_port_uc_leaky_set(dev_id, port_id, enable); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Get unicast packets leaky status on a particular port. - * @param[in] dev_id device id - * @param[out] enable A_TRUE or A_FALSE - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -isisc_port_uc_leaky_get(a_uint32_t dev_id, fal_port_t port_id, - a_bool_t *enable) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _isisc_port_uc_leaky_get(dev_id, port_id, enable); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Set multicast packets leaky status on a particular port. - * @param[in] dev_id device id - * @param[in] enable A_TRUE or A_FALSE - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -isisc_port_mc_leaky_set(a_uint32_t dev_id, fal_port_t port_id, - a_bool_t enable) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _isisc_port_mc_leaky_set(dev_id, port_id, enable); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Get multicast packets leaky status on a particular port. - * @param[in] dev_id device id - * @param[out] enable A_TRUE or A_FALSE - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -isisc_port_mc_leaky_get(a_uint32_t dev_id, fal_port_t port_id, - a_bool_t *enable) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _isisc_port_mc_leaky_get(dev_id, port_id, enable); - HSL_API_UNLOCK; - return rv; -} - -sw_error_t -isisc_leaky_init(a_uint32_t dev_id) -{ - HSL_DEV_ID_CHECK(dev_id); - -#ifndef HSL_STANDALONG - { - hsl_api_t *p_api; - - SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id)); - p_api->uc_leaky_mode_set = isisc_uc_leaky_mode_set; - p_api->uc_leaky_mode_get = isisc_uc_leaky_mode_get; - p_api->mc_leaky_mode_set = isisc_mc_leaky_mode_set; - p_api->mc_leaky_mode_get = isisc_mc_leaky_mode_get; - p_api->port_arp_leaky_set = isisc_port_arp_leaky_set; - p_api->port_arp_leaky_get = isisc_port_arp_leaky_get; - p_api->port_uc_leaky_set = isisc_port_uc_leaky_set; - p_api->port_uc_leaky_get = isisc_port_uc_leaky_get; - p_api->port_mc_leaky_set = isisc_port_mc_leaky_set; - p_api->port_mc_leaky_get = isisc_port_mc_leaky_get; - } -#endif - - return SW_OK; -} - -/** - * @} - */ - diff --git a/feeds/ipq807x/qca-ssdk/src/src/hsl/isisc/isisc_led.c b/feeds/ipq807x/qca-ssdk/src/src/hsl/isisc/isisc_led.c deleted file mode 100755 index fd3aebc38..000000000 --- a/feeds/ipq807x/qca-ssdk/src/src/hsl/isisc/isisc_led.c +++ /dev/null @@ -1,405 +0,0 @@ -/* - * Copyright (c) 2012, 2016, The Linux Foundation. All rights reserved. - * Permission to use, copy, modify, and/or distribute this software for - * any purpose with or without fee is hereby granted, provided that the - * above copyright notice and this permission notice appear in all copies. - * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES - * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR - * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES - * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN - * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT - * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. - */ - - -/** - * @defgroup isisc_led ISISC_LED - * @{ - */ -#include "sw.h" -#include "hsl.h" -#include "hsl_dev.h" -#include "isisc_led.h" -#include "isisc_reg.h" - -#define MAX_LED_PATTERN_ID 2 -#define LED_PATTERN_ADDR 0x50 - -static sw_error_t -_isisc_led_ctrl_pattern_set(a_uint32_t dev_id, led_pattern_group_t group, - led_pattern_id_t id, led_ctrl_pattern_t * pattern) -{ - a_uint32_t data = 0, reg, mode; - a_uint32_t addr; - sw_error_t rv; - - HSL_DEV_ID_CHECK(dev_id); - - if ((LED_WAN_PORT_GROUP != group) && (LED_LAN_PORT_GROUP != group)) - { - return SW_BAD_PARAM; - } - - if (id > MAX_LED_PATTERN_ID) - { - return SW_BAD_PARAM; - } - - addr = LED_PATTERN_ADDR + (id << 2); - - if (LED_ALWAYS_OFF == pattern->mode) - { - mode = 0; - } - else if (LED_ALWAYS_BLINK == pattern->mode) - { - mode = 1; - } - else if (LED_ALWAYS_ON == pattern->mode) - { - mode = 2; - } - else if (LED_PATTERN_MAP_EN == pattern->mode) - { - mode = 3; - } - else - { - return SW_BAD_PARAM; - } - SW_SET_REG_BY_FIELD(LED_CTRL, PATTERN_EN, mode, data); - - if (pattern->map & (1 << FULL_DUPLEX_LIGHT_EN)) - { - SW_SET_REG_BY_FIELD(LED_CTRL, FULL_LIGHT_EN, 1, data); - } - - if (pattern->map & (1 << HALF_DUPLEX_LIGHT_EN)) - { - SW_SET_REG_BY_FIELD(LED_CTRL, HALF_LIGHT_EN, 1, data); - } - - if (pattern->map & (1 << POWER_ON_LIGHT_EN)) - { - SW_SET_REG_BY_FIELD(LED_CTRL, POWERON_LIGHT_EN, 1, data); - } - - if (pattern->map & (1 << LINK_1000M_LIGHT_EN)) - { - SW_SET_REG_BY_FIELD(LED_CTRL, GE_LIGHT_EN, 1, data); - } - - if (pattern->map & (1 << LINK_100M_LIGHT_EN)) - { - SW_SET_REG_BY_FIELD(LED_CTRL, FE_LIGHT_EN, 1, data); - } - - if (pattern->map & (1 << LINK_10M_LIGHT_EN)) - { - SW_SET_REG_BY_FIELD(LED_CTRL, ETH_LIGHT_EN, 1, data); - } - - if (pattern->map & (1 << COLLISION_BLINK_EN)) - { - SW_SET_REG_BY_FIELD(LED_CTRL, COL_BLINK_EN, 1, data); - } - - if (pattern->map & (1 << RX_TRAFFIC_BLINK_EN)) - { - SW_SET_REG_BY_FIELD(LED_CTRL, RX_BLINK_EN, 1, data); - } - - if (pattern->map & (1 << TX_TRAFFIC_BLINK_EN)) - { - SW_SET_REG_BY_FIELD(LED_CTRL, TX_BLINK_EN, 1, data); - } - - if (pattern->map & (1 << LINKUP_OVERRIDE_EN)) - { - SW_SET_REG_BY_FIELD(LED_CTRL, LINKUP_OVER_EN, 1, data); - } - else - { - SW_SET_REG_BY_FIELD(LED_CTRL, LINKUP_OVER_EN, 0, data); - } - - if (LED_BLINK_2HZ == pattern->freq) - { - SW_SET_REG_BY_FIELD(LED_CTRL, BLINK_FREQ, 0, data); - } - else if (LED_BLINK_4HZ == pattern->freq) - { - SW_SET_REG_BY_FIELD(LED_CTRL, BLINK_FREQ, 1, data); - } - else if (LED_BLINK_8HZ == pattern->freq) - { - SW_SET_REG_BY_FIELD(LED_CTRL, BLINK_FREQ, 2, data); - } - else if (LED_BLINK_TXRX == pattern->freq) - { - SW_SET_REG_BY_FIELD(LED_CTRL, BLINK_FREQ, 3, data); - } - else - { - return SW_BAD_PARAM; - } - - HSL_REG_ENTRY_GEN_GET(rv, dev_id, addr, sizeof (a_uint32_t), - (a_uint8_t *) (®), - sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - - if (LED_WAN_PORT_GROUP == group) - { - reg &= 0xffff; - reg |= (data << 16); - } - else - { - reg &= 0xffff0000; - reg |= data; - } - - HSL_REG_ENTRY_GEN_SET(rv, dev_id, addr, sizeof (a_uint32_t), - (a_uint8_t *) (®), - sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - - if (LED_WAN_PORT_GROUP == group) - { - return SW_OK; - } - - HSL_REG_ENTRY_GET(rv, dev_id, LED_PATTERN, 0, - (a_uint8_t *) (&data), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - - if (LED_LAN_PORT_GROUP == group) - { - if (0 == id) - { - SW_SET_REG_BY_FIELD(LED_PATTERN, P3L0_MODE, mode, data); - SW_SET_REG_BY_FIELD(LED_PATTERN, P2L0_MODE, mode, data); - SW_SET_REG_BY_FIELD(LED_PATTERN, P1L0_MODE, mode, data); - } - else if (1 == id) - { - SW_SET_REG_BY_FIELD(LED_PATTERN, P3L1_MODE, mode, data); - SW_SET_REG_BY_FIELD(LED_PATTERN, P2L1_MODE, mode, data); - SW_SET_REG_BY_FIELD(LED_PATTERN, P1L1_MODE, mode, data); - } - else - { - SW_SET_REG_BY_FIELD(LED_PATTERN, P3L2_MODE, mode, data); - SW_SET_REG_BY_FIELD(LED_PATTERN, P2L2_MODE, mode, data); - SW_SET_REG_BY_FIELD(LED_PATTERN, P1L2_MODE, mode, data); - } - } - - HSL_REG_ENTRY_SET(rv, dev_id, LED_PATTERN, 0, - (a_uint8_t *) (&data), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - - return SW_OK; -} - -static sw_error_t -_isisc_led_ctrl_pattern_get(a_uint32_t dev_id, led_pattern_group_t group, - led_pattern_id_t id, led_ctrl_pattern_t * pattern) -{ - a_uint32_t data = 0, reg = 0, tmp; - a_uint32_t addr; - sw_error_t rv; - - HSL_DEV_ID_CHECK(dev_id); - - if ((LED_WAN_PORT_GROUP != group) && (LED_LAN_PORT_GROUP != group)) - { - return SW_BAD_PARAM; - } - - if (id > MAX_LED_PATTERN_ID) - { - return SW_BAD_PARAM; - } - - aos_mem_zero(pattern, sizeof(led_ctrl_pattern_t)); - - addr = LED_PATTERN_ADDR + (id << 2); - - HSL_REG_ENTRY_GEN_GET(rv, dev_id, addr, sizeof (a_uint32_t), - (a_uint8_t *) (®), - sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - - if (LED_WAN_PORT_GROUP == group) - { - data = (reg >> 16) & 0xffff; - } - else - { - data = reg & 0xffff; - } - - SW_GET_FIELD_BY_REG(LED_CTRL, PATTERN_EN, tmp, data); - if (0 == tmp) - { - pattern->mode = LED_ALWAYS_OFF; - } - else if (1 == tmp) - { - pattern->mode = LED_ALWAYS_BLINK; - } - else if (2 == tmp) - { - pattern->mode = LED_ALWAYS_ON; - } - else - { - pattern->mode = LED_PATTERN_MAP_EN; - } - - SW_GET_FIELD_BY_REG(LED_CTRL, FULL_LIGHT_EN, tmp, data); - if (1 == tmp) - { - pattern->map |= (1 << FULL_DUPLEX_LIGHT_EN); - } - - SW_GET_FIELD_BY_REG(LED_CTRL, HALF_LIGHT_EN, tmp, data); - if (1 == tmp) - { - pattern->map |= (1 << HALF_DUPLEX_LIGHT_EN); - } - - SW_GET_FIELD_BY_REG(LED_CTRL, POWERON_LIGHT_EN, tmp, data); - if (1 == tmp) - { - pattern->map |= (1 << POWER_ON_LIGHT_EN); - } - - SW_GET_FIELD_BY_REG(LED_CTRL, GE_LIGHT_EN, tmp, data); - if (1 == tmp) - { - pattern->map |= (1 << LINK_1000M_LIGHT_EN); - } - - SW_GET_FIELD_BY_REG(LED_CTRL, FE_LIGHT_EN, tmp, data); - if (1 == tmp) - { - pattern->map |= (1 << LINK_100M_LIGHT_EN); - } - - SW_GET_FIELD_BY_REG(LED_CTRL, ETH_LIGHT_EN, tmp, data); - if (1 == tmp) - { - pattern->map |= (1 << LINK_10M_LIGHT_EN); - } - - SW_GET_FIELD_BY_REG(LED_CTRL, COL_BLINK_EN, tmp, data); - if (1 == tmp) - { - pattern->map |= (1 << COLLISION_BLINK_EN); - } - - SW_GET_FIELD_BY_REG(LED_CTRL, RX_BLINK_EN, tmp, data); - if (1 == tmp) - { - pattern->map |= (1 << RX_TRAFFIC_BLINK_EN); - } - - SW_GET_FIELD_BY_REG(LED_CTRL, TX_BLINK_EN, tmp, data); - if (1 == tmp) - { - pattern->map |= (1 << TX_TRAFFIC_BLINK_EN); - } - - SW_GET_FIELD_BY_REG(LED_CTRL, LINKUP_OVER_EN, tmp, data); - if (1 == tmp) - { - pattern->map |= (1 << LINKUP_OVERRIDE_EN); - } - - SW_GET_FIELD_BY_REG(LED_CTRL, BLINK_FREQ, tmp, data); - if (0 == tmp) - { - pattern->freq = LED_BLINK_2HZ; - } - else if (1 == tmp) - { - pattern->freq = LED_BLINK_4HZ; - } - else if (2 == tmp) - { - pattern->freq = LED_BLINK_8HZ; - } - else - { - pattern->freq = LED_BLINK_TXRX; - } - - return SW_OK; -} - -/** -* @brief Set led control pattern on a particular device. -* @param[in] dev_id device id -* @param[in] group pattern group, lan or wan -* @param[in] id pattern id -* @param[in] pattern led control pattern -* @return SW_OK or error code -*/ -HSL_LOCAL sw_error_t -isisc_led_ctrl_pattern_set(a_uint32_t dev_id, led_pattern_group_t group, - led_pattern_id_t id, led_ctrl_pattern_t * pattern) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _isisc_led_ctrl_pattern_set(dev_id, group, id, pattern); - HSL_API_UNLOCK; - return rv; -} - -/** -* @brief Get led control pattern on a particular device. -* @param[in] dev_id device id -* @param[in] group pattern group, lan or wan -* @param[in] id pattern id -* @param[out] pattern led control pattern -* @return SW_OK or error code -*/ -HSL_LOCAL sw_error_t -isisc_led_ctrl_pattern_get(a_uint32_t dev_id, led_pattern_group_t group, - led_pattern_id_t id, led_ctrl_pattern_t * pattern) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _isisc_led_ctrl_pattern_get(dev_id, group, id, pattern); - HSL_API_UNLOCK; - return rv; -} - -sw_error_t -isisc_led_init(a_uint32_t dev_id) -{ - HSL_DEV_ID_CHECK(dev_id); - -#ifndef HSL_STANDALONG - { - hsl_api_t *p_api; - - SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id)); - p_api->led_ctrl_pattern_set = isisc_led_ctrl_pattern_set; - p_api->led_ctrl_pattern_get = isisc_led_ctrl_pattern_get; - } -#endif - - return SW_OK; -} - -/** - * @} - */ - diff --git a/feeds/ipq807x/qca-ssdk/src/src/hsl/isisc/isisc_mib.c b/feeds/ipq807x/qca-ssdk/src/src/hsl/isisc/isisc_mib.c deleted file mode 100755 index 5ca5def34..000000000 --- a/feeds/ipq807x/qca-ssdk/src/src/hsl/isisc/isisc_mib.c +++ /dev/null @@ -1,860 +0,0 @@ -/* - * Copyright (c) 2012, 2016 The Linux Foundation. All rights reserved. - * Permission to use, copy, modify, and/or distribute this software for - * any purpose with or without fee is hereby granted, provided that the - * above copyright notice and this permission notice appear in all copies. - * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES - * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR - * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES - * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN - * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT - * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. - */ - - -/** - * @defgroup isisc_mib ISISC_MIB - * @{ - */ -#include "sw.h" -#include "hsl.h" -#include "hsl_dev.h" -#include "hsl_port_prop.h" -#include "isisc_mib.h" -#include "isisc_reg.h" - - -#define MIB_FLUSH_ALL_PORTS 0x1 -#define MIB_FLUSH_ONE_PORT 0x2 -#define MIB_AUTOCAST_ALL_PORTS 0x3 - -static sw_error_t -_isisc_mib_op_commit(a_uint32_t dev_id, a_uint32_t op) -{ - a_uint32_t mib_busy = 1, i = 0x1000, val; - sw_error_t rv; - - while (mib_busy && --i) - { - HSL_REG_FIELD_GET(rv, dev_id, MIB_FUNC, 0, MIB_BUSY, - (a_uint8_t *) (&mib_busy), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - aos_udelay(5); - } - - if (i == 0) - return SW_BUSY; - - HSL_REG_ENTRY_GET(rv, dev_id, MIB_FUNC, 0, - (a_uint8_t *) (&val), sizeof (a_uint32_t)); - SW_SET_REG_BY_FIELD(MIB_FUNC, MIB_FUN, op, val); - SW_SET_REG_BY_FIELD(MIB_FUNC, MIB_BUSY, 1, val); - - HSL_REG_ENTRY_SET(rv, dev_id, MIB_FUNC, 0, - (a_uint8_t *) (&val), sizeof (a_uint32_t)); - - SW_RTN_ON_ERROR(rv); - - mib_busy = 1; - i = 0x1000; - while (mib_busy && --i) - { - HSL_REG_FIELD_GET(rv, dev_id, MIB_FUNC, 0, MIB_BUSY, - (a_uint8_t *) (&mib_busy), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - aos_udelay(5); - } - - if (i == 0) - return SW_FAIL; - - return SW_OK; -} - -static sw_error_t -_isisc_get_mib_info(a_uint32_t dev_id, fal_port_t port_id, - fal_mib_info_t * mib_info) -{ - a_uint32_t val = 0; - sw_error_t rv; - - HSL_DEV_ID_CHECK(dev_id); - - if (A_FALSE == hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU)) - { - return SW_OUT_OF_RANGE; - } - - HSL_REG_ENTRY_GET(rv, dev_id, MIB_RXBROAD, port_id, - (a_uint8_t *) (&val), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - mib_info->RxBroad = val; - - HSL_REG_ENTRY_GET(rv, dev_id, MIB_RXPAUSE, port_id, - (a_uint8_t *) (&val), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - mib_info->RxPause = val; - - HSL_REG_ENTRY_GET(rv, dev_id, MIB_RXMULTI, port_id, - (a_uint8_t *) (&val), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - mib_info->RxMulti = val; - - HSL_REG_ENTRY_GET(rv, dev_id, MIB_RXFCSERR, port_id, - (a_uint8_t *) (&val), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - mib_info->RxFcsErr = val; - - HSL_REG_ENTRY_GET(rv, dev_id, MIB_RXALLIGNERR, port_id, - (a_uint8_t *) (&val), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - mib_info->RxAllignErr = val; - - HSL_REG_ENTRY_GET(rv, dev_id, MIB_RXRUNT, port_id, (a_uint8_t *) (&val), - sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - mib_info->RxRunt = val; - - HSL_REG_ENTRY_GET(rv, dev_id, MIB_RXFRAGMENT, port_id, - (a_uint8_t *) (&val), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - mib_info->RxFragment = val; - - HSL_REG_ENTRY_GET(rv, dev_id, MIB_RX64BYTE, port_id, - (a_uint8_t *) (&val), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - mib_info->Rx64Byte = val; - - HSL_REG_ENTRY_GET(rv, dev_id, MIB_RX128BYTE, port_id, - (a_uint8_t *) (&val), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - mib_info->Rx128Byte = val; - - HSL_REG_ENTRY_GET(rv, dev_id, MIB_RX256BYTE, port_id, - (a_uint8_t *) (&val), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - mib_info->Rx256Byte = val; - - HSL_REG_ENTRY_GET(rv, dev_id, MIB_RX512BYTE, port_id, - (a_uint8_t *) (&val), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - mib_info->Rx512Byte = val; - - HSL_REG_ENTRY_GET(rv, dev_id, MIB_RX1024BYTE, port_id, - (a_uint8_t *) (&val), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - mib_info->Rx1024Byte = val; - - HSL_REG_ENTRY_GET(rv, dev_id, MIB_RX1518BYTE, port_id, - (a_uint8_t *) (&val), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - mib_info->Rx1518Byte = val; - - HSL_REG_ENTRY_GET(rv, dev_id, MIB_RXMAXBYTE, port_id, - (a_uint8_t *) (&val), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - mib_info->RxMaxByte = val; - - HSL_REG_ENTRY_GET(rv, dev_id, MIB_RXTOOLONG, port_id, - (a_uint8_t *) (&val), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - mib_info->RxTooLong = val; - - HSL_REG_ENTRY_GET(rv, dev_id, MIB_RXGOODBYTE_LO, port_id, - (a_uint8_t *) (&val), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - mib_info->RxGoodByte_lo = val; - - HSL_REG_ENTRY_GET(rv, dev_id, MIB_RXGOODBYTE_HI, port_id, - (a_uint8_t *) (&val), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - mib_info->RxGoodByte_hi = val; - - HSL_REG_ENTRY_GET(rv, dev_id, MIB_RXBADBYTE_LO, port_id, - (a_uint8_t *) (&val), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - mib_info->RxBadByte_lo = val; - - HSL_REG_ENTRY_GET(rv, dev_id, MIB_RXBADBYTE_HI, port_id, - (a_uint8_t *) (&val), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - mib_info->RxBadByte_hi = val; - - HSL_REG_ENTRY_GET(rv, dev_id, MIB_RXOVERFLOW, port_id, - (a_uint8_t *) (&val), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - mib_info->RxOverFlow = val; - - HSL_REG_ENTRY_GET(rv, dev_id, MIB_FILTERED, port_id, - (a_uint8_t *) (&val), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - mib_info->Filtered = val; - - HSL_REG_ENTRY_GET(rv, dev_id, MIB_TXBROAD, port_id, (a_uint8_t *) (&val), - sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - mib_info->TxBroad = val; - - HSL_REG_ENTRY_GET(rv, dev_id, MIB_TXPAUSE, port_id, (a_uint8_t *) (&val), - sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - mib_info->TxPause = val; - - HSL_REG_ENTRY_GET(rv, dev_id, MIB_TXMULTI, port_id, (a_uint8_t *) (&val), - sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - mib_info->TxMulti = val; - - HSL_REG_ENTRY_GET(rv, dev_id, MIB_TXUNDERRUN, port_id, - (a_uint8_t *) (&val), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - mib_info->TxUnderRun = val; - - HSL_REG_ENTRY_GET(rv, dev_id, MIB_TX64BYTE, port_id, - (a_uint8_t *) (&val), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - mib_info->Tx64Byte = val; - - HSL_REG_ENTRY_GET(rv, dev_id, MIB_TX128BYTE, port_id, - (a_uint8_t *) (&val), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - mib_info->Tx128Byte = val; - - HSL_REG_ENTRY_GET(rv, dev_id, MIB_TX256BYTE, port_id, - (a_uint8_t *) (&val), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - mib_info->Tx256Byte = val; - - HSL_REG_ENTRY_GET(rv, dev_id, MIB_TX512BYTE, port_id, - (a_uint8_t *) (&val), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - mib_info->Tx512Byte = val; - - HSL_REG_ENTRY_GET(rv, dev_id, MIB_TX1024BYTE, port_id, - (a_uint8_t *) (&val), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - mib_info->Tx1024Byte = val; - - HSL_REG_ENTRY_GET(rv, dev_id, MIB_TX1518BYTE, port_id, - (a_uint8_t *) (&val), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - mib_info->Tx1518Byte = val; - - HSL_REG_ENTRY_GET(rv, dev_id, MIB_TXMAXBYTE, port_id, - (a_uint8_t *) (&val), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - mib_info->TxMaxByte = val; - - HSL_REG_ENTRY_GET(rv, dev_id, MIB_TXOVERSIZE, port_id, - (a_uint8_t *) (&val), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - mib_info->TxOverSize = val; - - HSL_REG_ENTRY_GET(rv, dev_id, MIB_TXBYTE_LO, port_id, - (a_uint8_t *) (&val), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - mib_info->TxByte_lo = val; - - HSL_REG_ENTRY_GET(rv, dev_id, MIB_TXBYTE_HI, port_id, - (a_uint8_t *) (&val), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - mib_info->TxByte_hi = val; - - HSL_REG_ENTRY_GET(rv, dev_id, MIB_TXCOLLISION, port_id, - (a_uint8_t *) (&val), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - mib_info->TxCollision = val; - - HSL_REG_ENTRY_GET(rv, dev_id, MIB_TXABORTCOL, port_id, - (a_uint8_t *) (&val), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - mib_info->TxAbortCol = val; - - HSL_REG_ENTRY_GET(rv, dev_id, MIB_TXMULTICOL, port_id, - (a_uint8_t *) (&val), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - mib_info->TxMultiCol = val; - - HSL_REG_ENTRY_GET(rv, dev_id, MIB_TXSINGALCOL, port_id, - (a_uint8_t *) (&val), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - mib_info->TxSingalCol = val; - - HSL_REG_ENTRY_GET(rv, dev_id, MIB_TXEXCDEFER, port_id, - (a_uint8_t *) (&val), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - mib_info->TxExcDefer = val; - - HSL_REG_ENTRY_GET(rv, dev_id, MIB_TXDEFER, port_id, (a_uint8_t *) (&val), - sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - mib_info->TxDefer = val; - - HSL_REG_ENTRY_GET(rv, dev_id, MIB_TXLATECOL, port_id, - (a_uint8_t *) (&val), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - mib_info->TxLateCol = val; - - HSL_REG_ENTRY_GET(rv, dev_id, MIB_RXUNICAST, port_id, - (a_uint8_t *) (&val), sizeof - (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - mib_info->RxUniCast = val; - - HSL_REG_ENTRY_GET(rv, dev_id, MIB_TXUNICAST, port_id, - (a_uint8_t *) (&val), sizeof - (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - mib_info->TxUniCast = val; - - return SW_OK; -} - -static sw_error_t -_isisc_get_rx_mib_info(a_uint32_t dev_id, fal_port_t port_id, - fal_mib_info_t * mib_info) -{ - a_uint32_t val = 0; - sw_error_t rv; - - HSL_DEV_ID_CHECK(dev_id); - - if (A_FALSE == hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU)) - { - return SW_OUT_OF_RANGE; - } - - HSL_REG_ENTRY_GET(rv, dev_id, MIB_RXBROAD, port_id, - (a_uint8_t *) (&val), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - mib_info->RxBroad = val; - - HSL_REG_ENTRY_GET(rv, dev_id, MIB_RXPAUSE, port_id, - (a_uint8_t *) (&val), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - mib_info->RxPause = val; - - HSL_REG_ENTRY_GET(rv, dev_id, MIB_RXMULTI, port_id, - (a_uint8_t *) (&val), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - mib_info->RxMulti = val; - - HSL_REG_ENTRY_GET(rv, dev_id, MIB_RXFCSERR, port_id, - (a_uint8_t *) (&val), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - mib_info->RxFcsErr = val; - - HSL_REG_ENTRY_GET(rv, dev_id, MIB_RXALLIGNERR, port_id, - (a_uint8_t *) (&val), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - mib_info->RxAllignErr = val; - - HSL_REG_ENTRY_GET(rv, dev_id, MIB_RXRUNT, port_id, (a_uint8_t *) (&val), - sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - mib_info->RxRunt = val; - - HSL_REG_ENTRY_GET(rv, dev_id, MIB_RXFRAGMENT, port_id, - (a_uint8_t *) (&val), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - mib_info->RxFragment = val; - - HSL_REG_ENTRY_GET(rv, dev_id, MIB_RX64BYTE, port_id, - (a_uint8_t *) (&val), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - mib_info->Rx64Byte = val; - - HSL_REG_ENTRY_GET(rv, dev_id, MIB_RX128BYTE, port_id, - (a_uint8_t *) (&val), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - mib_info->Rx128Byte = val; - - HSL_REG_ENTRY_GET(rv, dev_id, MIB_RX256BYTE, port_id, - (a_uint8_t *) (&val), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - mib_info->Rx256Byte = val; - - HSL_REG_ENTRY_GET(rv, dev_id, MIB_RX512BYTE, port_id, - (a_uint8_t *) (&val), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - mib_info->Rx512Byte = val; - - HSL_REG_ENTRY_GET(rv, dev_id, MIB_RX1024BYTE, port_id, - (a_uint8_t *) (&val), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - mib_info->Rx1024Byte = val; - - HSL_REG_ENTRY_GET(rv, dev_id, MIB_RX1518BYTE, port_id, - (a_uint8_t *) (&val), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - mib_info->Rx1518Byte = val; - - HSL_REG_ENTRY_GET(rv, dev_id, MIB_RXMAXBYTE, port_id, - (a_uint8_t *) (&val), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - mib_info->RxMaxByte = val; - - HSL_REG_ENTRY_GET(rv, dev_id, MIB_RXTOOLONG, port_id, - (a_uint8_t *) (&val), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - mib_info->RxTooLong = val; - - HSL_REG_ENTRY_GET(rv, dev_id, MIB_RXGOODBYTE_LO, port_id, - (a_uint8_t *) (&val), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - mib_info->RxGoodByte_lo = val; - - HSL_REG_ENTRY_GET(rv, dev_id, MIB_RXGOODBYTE_HI, port_id, - (a_uint8_t *) (&val), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - mib_info->RxGoodByte_hi = val; - - HSL_REG_ENTRY_GET(rv, dev_id, MIB_RXBADBYTE_LO, port_id, - (a_uint8_t *) (&val), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - mib_info->RxBadByte_lo = val; - - HSL_REG_ENTRY_GET(rv, dev_id, MIB_RXBADBYTE_HI, port_id, - (a_uint8_t *) (&val), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - mib_info->RxBadByte_hi = val; - - HSL_REG_ENTRY_GET(rv, dev_id, MIB_RXOVERFLOW, port_id, - (a_uint8_t *) (&val), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - mib_info->RxOverFlow = val; - - HSL_REG_ENTRY_GET(rv, dev_id, MIB_FILTERED, port_id, - (a_uint8_t *) (&val), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - mib_info->Filtered = val; - - HSL_REG_ENTRY_GET(rv, dev_id, MIB_RXUNICAST, port_id, - (a_uint8_t *) (&val), sizeof - (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - mib_info->RxUniCast = val; - - return SW_OK; -} - -static sw_error_t -_isisc_get_tx_mib_info(a_uint32_t dev_id, fal_port_t port_id, - fal_mib_info_t * mib_info) -{ - a_uint32_t val = 0; - sw_error_t rv; - - HSL_DEV_ID_CHECK(dev_id); - - if (A_FALSE == hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU)) - { - return SW_OUT_OF_RANGE; - } - - HSL_REG_ENTRY_GET(rv, dev_id, MIB_TXBROAD, port_id, (a_uint8_t *) (&val), - sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - mib_info->TxBroad = val; - - HSL_REG_ENTRY_GET(rv, dev_id, MIB_TXPAUSE, port_id, (a_uint8_t *) (&val), - sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - mib_info->TxPause = val; - - HSL_REG_ENTRY_GET(rv, dev_id, MIB_TXMULTI, port_id, (a_uint8_t *) (&val), - sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - mib_info->TxMulti = val; - - HSL_REG_ENTRY_GET(rv, dev_id, MIB_TXUNDERRUN, port_id, - (a_uint8_t *) (&val), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - mib_info->TxUnderRun = val; - - HSL_REG_ENTRY_GET(rv, dev_id, MIB_TX64BYTE, port_id, - (a_uint8_t *) (&val), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - mib_info->Tx64Byte = val; - - HSL_REG_ENTRY_GET(rv, dev_id, MIB_TX128BYTE, port_id, - (a_uint8_t *) (&val), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - mib_info->Tx128Byte = val; - - HSL_REG_ENTRY_GET(rv, dev_id, MIB_TX256BYTE, port_id, - (a_uint8_t *) (&val), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - mib_info->Tx256Byte = val; - - HSL_REG_ENTRY_GET(rv, dev_id, MIB_TX512BYTE, port_id, - (a_uint8_t *) (&val), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - mib_info->Tx512Byte = val; - - HSL_REG_ENTRY_GET(rv, dev_id, MIB_TX1024BYTE, port_id, - (a_uint8_t *) (&val), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - mib_info->Tx1024Byte = val; - - HSL_REG_ENTRY_GET(rv, dev_id, MIB_TX1518BYTE, port_id, - (a_uint8_t *) (&val), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - mib_info->Tx1518Byte = val; - - HSL_REG_ENTRY_GET(rv, dev_id, MIB_TXMAXBYTE, port_id, - (a_uint8_t *) (&val), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - mib_info->TxMaxByte = val; - - HSL_REG_ENTRY_GET(rv, dev_id, MIB_TXOVERSIZE, port_id, - (a_uint8_t *) (&val), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - mib_info->TxOverSize = val; - - HSL_REG_ENTRY_GET(rv, dev_id, MIB_TXBYTE_LO, port_id, - (a_uint8_t *) (&val), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - mib_info->TxByte_lo = val; - - HSL_REG_ENTRY_GET(rv, dev_id, MIB_TXBYTE_HI, port_id, - (a_uint8_t *) (&val), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - mib_info->TxByte_hi = val; - - HSL_REG_ENTRY_GET(rv, dev_id, MIB_TXCOLLISION, port_id, - (a_uint8_t *) (&val), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - mib_info->TxCollision = val; - - HSL_REG_ENTRY_GET(rv, dev_id, MIB_TXABORTCOL, port_id, - (a_uint8_t *) (&val), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - mib_info->TxAbortCol = val; - - HSL_REG_ENTRY_GET(rv, dev_id, MIB_TXMULTICOL, port_id, - (a_uint8_t *) (&val), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - mib_info->TxMultiCol = val; - - HSL_REG_ENTRY_GET(rv, dev_id, MIB_TXSINGALCOL, port_id, - (a_uint8_t *) (&val), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - mib_info->TxSingalCol = val; - - HSL_REG_ENTRY_GET(rv, dev_id, MIB_TXEXCDEFER, port_id, - (a_uint8_t *) (&val), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - mib_info->TxExcDefer = val; - - HSL_REG_ENTRY_GET(rv, dev_id, MIB_TXDEFER, port_id, (a_uint8_t *) (&val), - sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - mib_info->TxDefer = val; - - HSL_REG_ENTRY_GET(rv, dev_id, MIB_TXLATECOL, port_id, - (a_uint8_t *) (&val), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - mib_info->TxLateCol = val; - - HSL_REG_ENTRY_GET(rv, dev_id, MIB_TXUNICAST, port_id, - (a_uint8_t *) (&val), sizeof - (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - mib_info->TxUniCast = val; - - return SW_OK; -} - -static sw_error_t -_isisc_mib_status_set(a_uint32_t dev_id, a_bool_t enable) -{ - sw_error_t rv; - a_uint32_t val; - - HSL_DEV_ID_CHECK(dev_id); - - if (A_TRUE == enable) - { - val = 1; - } - else if (A_FALSE == enable) - { - val = 0; - } - else - { - return SW_BAD_PARAM; - } - - HSL_REG_FIELD_SET(rv, dev_id, MOD_ENABLE, 0, MIB_EN, - (a_uint8_t *) (&val), sizeof (a_uint32_t)); - return rv; -} - -static sw_error_t -_isisc_mib_status_get(a_uint32_t dev_id, a_bool_t * enable) -{ - sw_error_t rv; - a_uint32_t val = 0; - - HSL_DEV_ID_CHECK(dev_id); - - HSL_REG_FIELD_GET(rv, dev_id, MOD_ENABLE, 0, MIB_EN, - (a_uint8_t *) (&val), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - - if (1 == val) - { - *enable = A_TRUE; - } - else - { - *enable = A_FALSE; - } - - return SW_OK; -} - -static sw_error_t -_isisc_mib_cpukeep_set(a_uint32_t dev_id, a_bool_t enable) -{ - sw_error_t rv; - a_uint32_t val; - - HSL_DEV_ID_CHECK(dev_id); - - if (A_TRUE == enable) - { - val = 1; - } - else if (A_FALSE == enable) - { - val = 0; - } - else - { - return SW_BAD_PARAM; - } - - HSL_REG_FIELD_SET(rv, dev_id, MIB_FUNC, 0, MIB_CPU_KEEP, - (a_uint8_t *) (&val), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - - return rv; -} - -static sw_error_t -_isisc_mib_cpukeep_get(a_uint32_t dev_id, a_bool_t * enable) -{ - sw_error_t rv; - a_uint32_t val = 0; - - HSL_DEV_ID_CHECK(dev_id); - - HSL_REG_FIELD_GET(rv, dev_id, MIB_FUNC, 0, MIB_CPU_KEEP, - (a_uint8_t *) (&val), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - - if (1 == val) - { - *enable = A_TRUE; - } - else - { - *enable = A_FALSE; - } - - return SW_OK; -} - -static sw_error_t -_isisc_mib_port_flush_counters(a_uint32_t dev_id, fal_port_t port_id) -{ - a_uint32_t val; - sw_error_t rv; - - HSL_DEV_ID_CHECK(dev_id); - - if (A_FALSE == hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU)) - { - return SW_OUT_OF_RANGE; - } - - if (port_id>7) - return SW_BAD_PARAM; - - val = port_id; - HSL_REG_FIELD_SET(rv, dev_id, MIB_FUNC, 0, MIB_FLUSH_PORT, - (a_uint8_t *) (&val), sizeof (a_uint32_t)); - - rv = _isisc_mib_op_commit( dev_id, MIB_FLUSH_ONE_PORT); - - return rv; -} - -/** - * @brief Get mib infomation on particular port. - * @param[in] dev_id device id - * @param[in] port_id port id - * @param[out] mib_info mib infomation - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -isisc_get_mib_info(a_uint32_t dev_id, fal_port_t port_id, - fal_mib_info_t * mib_info) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _isisc_get_mib_info(dev_id, port_id, mib_info); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Get RX mib infomation on particular port. - * @param[in] dev_id device id - * @param[in] port_id port id - * @param[out] mib_info mib infomation - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -isisc_get_rx_mib_info(a_uint32_t dev_id, fal_port_t port_id, - fal_mib_info_t * mib_info) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _isisc_get_rx_mib_info(dev_id, port_id, mib_info); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Get TX mib infomation on particular port. - * @param[in] dev_id device id - * @param[in] port_id port id - * @param[out] mib_info mib infomation - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -isisc_get_tx_mib_info(a_uint32_t dev_id, fal_port_t port_id, - fal_mib_info_t * mib_info) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _isisc_get_tx_mib_info(dev_id, port_id, mib_info); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Set mib status on a particular device. - * @param[in] dev_id device id - * @param[in] enable A_TRUE or A_FALSE - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -isisc_mib_status_set(a_uint32_t dev_id, a_bool_t enable) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _isisc_mib_status_set(dev_id, enable); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Get mib status on a particular device. - * @param[in] dev_id device id - * @param[out] enable A_TRUE or A_FALSE - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -isisc_mib_status_get(a_uint32_t dev_id, a_bool_t * enable) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _isisc_mib_status_get(dev_id, enable); - HSL_API_UNLOCK; - return rv; -} - -HSL_LOCAL sw_error_t -isisc_mib_port_flush_counters(a_uint32_t dev_id, fal_port_t port_id) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _isisc_mib_port_flush_counters(dev_id, port_id); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Set mib cpu keep bit on a particular device. - * @param[in] dev_id device id - * @param[in] enable A_TRUE or A_FALSE - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -isisc_mib_cpukeep_set(a_uint32_t dev_id, a_bool_t enable) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _isisc_mib_cpukeep_set(dev_id, enable); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Get mib keep bit on a particular device. - * @param[in] dev_id device id - * @param[out] enable A_TRUE or A_FALSE - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -isisc_mib_cpukeep_get(a_uint32_t dev_id, a_bool_t * enable) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _isisc_mib_cpukeep_get(dev_id, enable); - HSL_API_UNLOCK; - return rv; -} - -sw_error_t -isisc_mib_init(a_uint32_t dev_id) -{ -#ifndef HSL_STANDALONG - hsl_api_t *p_api; -#endif - HSL_DEV_ID_CHECK(dev_id); - -#ifndef HSL_STANDALONG - SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id)); - - p_api->get_mib_info = isisc_get_mib_info; - p_api->get_rx_mib_info = isisc_get_rx_mib_info; - p_api->get_tx_mib_info = isisc_get_tx_mib_info; - p_api->mib_status_set = isisc_mib_status_set; - p_api->mib_status_get = isisc_mib_status_get; - p_api->mib_port_flush_counters = isisc_mib_port_flush_counters; - p_api->mib_cpukeep_set = isisc_mib_cpukeep_set; - p_api->mib_cpukeep_get = isisc_mib_cpukeep_get; -#endif - - return SW_OK; -} - -/** - * @} - */ - diff --git a/feeds/ipq807x/qca-ssdk/src/src/hsl/isisc/isisc_mirror.c b/feeds/ipq807x/qca-ssdk/src/src/hsl/isisc/isisc_mirror.c deleted file mode 100755 index 12441dc63..000000000 --- a/feeds/ipq807x/qca-ssdk/src/src/hsl/isisc/isisc_mirror.c +++ /dev/null @@ -1,315 +0,0 @@ -/* - * Copyright (c) 2012, 2016, The Linux Foundation. All rights reserved. - * Permission to use, copy, modify, and/or distribute this software for - * any purpose with or without fee is hereby granted, provided that the - * above copyright notice and this permission notice appear in all copies. - * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES - * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR - * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES - * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN - * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT - * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. - */ - - -/** - * @defgroup isisc_mirror ISISC_MIRROR - * @{ - */ -#include "sw.h" -#include "hsl.h" -#include "hsl_dev.h" -#include "hsl_port_prop.h" -#include "isisc_mirror.h" -#include "isisc_reg.h" - -static sw_error_t -_isisc_mirr_analysis_port_set(a_uint32_t dev_id, fal_port_t port_id) -{ - sw_error_t rv; - a_uint32_t val; - - HSL_DEV_ID_CHECK(dev_id); - if (port_id != MIRROR_ANALYZER_NONE) { - if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU)) { - return SW_BAD_PARAM; - } - } - val = port_id; - HSL_REG_FIELD_SET(rv, dev_id, FORWARD_CTL0, 0, MIRROR_PORT_NUM, - (a_uint8_t *) (&val), sizeof (a_uint32_t)); - return rv; -} - -static sw_error_t -_isisc_mirr_analysis_port_get(a_uint32_t dev_id, fal_port_t * port_id) -{ - sw_error_t rv; - a_uint32_t val = 0; - - HSL_DEV_ID_CHECK(dev_id); - - HSL_REG_FIELD_GET(rv, dev_id, FORWARD_CTL0, 0, MIRROR_PORT_NUM, - (a_uint8_t *) (&val), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - - *port_id = val; - return SW_OK; -} - -static sw_error_t -_isisc_mirr_port_in_set(a_uint32_t dev_id, fal_port_t port_id, a_bool_t enable) -{ - sw_error_t rv; - a_uint32_t val; - - HSL_DEV_ID_CHECK(dev_id); - - if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU)) - { - return SW_BAD_PARAM; - } - - if (A_TRUE == enable) - { - val = 1; - } - else if (A_FALSE == enable) - { - val = 0; - } - else - { - return SW_BAD_PARAM; - } - - HSL_REG_FIELD_SET(rv, dev_id, PORT_LOOKUP_CTL, port_id, ING_MIRROR_EN, - (a_uint8_t *) (&val), sizeof (a_uint32_t)); - return rv; -} - -static sw_error_t -_isisc_mirr_port_in_get(a_uint32_t dev_id, fal_port_t port_id, a_bool_t * enable) -{ - sw_error_t rv; - a_uint32_t val = 0; - - HSL_DEV_ID_CHECK(dev_id); - - if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU)) - { - return SW_BAD_PARAM; - } - - HSL_REG_FIELD_GET(rv, dev_id, PORT_LOOKUP_CTL, port_id, ING_MIRROR_EN, - (a_uint8_t *) (&val), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - - if (1 == val) - { - *enable = A_TRUE; - } - else - { - *enable = A_FALSE; - } - - return SW_OK; -} - -static sw_error_t -_isisc_mirr_port_eg_set(a_uint32_t dev_id, fal_port_t port_id, a_bool_t enable) -{ - sw_error_t rv; - a_uint32_t val; - - HSL_DEV_ID_CHECK(dev_id); - - if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU)) - { - return SW_BAD_PARAM; - } - - if (A_TRUE == enable) - { - val = 1; - } - else if (A_FALSE == enable) - { - val = 0; - } - else - { - return SW_BAD_PARAM; - } - - HSL_REG_FIELD_SET(rv, dev_id, PORT_HOL_CTL1, port_id, EG_MIRROR_EN, - (a_uint8_t *) (&val), sizeof (a_uint32_t)); - return rv; -} - -static sw_error_t -_isisc_mirr_port_eg_get(a_uint32_t dev_id, fal_port_t port_id, a_bool_t * enable) -{ - sw_error_t rv; - a_uint32_t val = 0; - - HSL_DEV_ID_CHECK(dev_id); - - if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU)) - { - return SW_BAD_PARAM; - } - - HSL_REG_FIELD_GET(rv, dev_id, PORT_HOL_CTL1, port_id, EG_MIRROR_EN, - (a_uint8_t *) (&val), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - - if (1 == val) - { - *enable = A_TRUE; - } - else - { - *enable = A_FALSE; - } - - return SW_OK; -} - -/** - * @details Comments: - * The analysis port works for both ingress and egress mirror. - * @brief Set mirror analyzer port on particular a device. - * @param[in] dev_id device id - * @param[in] port_id port id - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -isisc_mirr_analysis_port_set(a_uint32_t dev_id, fal_port_t port_id) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _isisc_mirr_analysis_port_set(dev_id, port_id); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Get mirror analysis port on particular a device. - * @param[in] dev_id device id - * @param[out] port_id port id - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -isisc_mirr_analysis_port_get(a_uint32_t dev_id, fal_port_t * port_id) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _isisc_mirr_analysis_port_get(dev_id, port_id); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Set ingress mirror status on particular a port. - * @param[in] dev_id device id - * @param[in] port_id port id - * @param[in] enable A_TRUE or A_FALSE - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -isisc_mirr_port_in_set(a_uint32_t dev_id, fal_port_t port_id, a_bool_t enable) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _isisc_mirr_port_in_set(dev_id, port_id, enable); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Get ingress mirror status on particular a port. - * @param[in] dev_id device id - * @param[in] port_id port id - * @param[out] enable A_TRUE or A_FALSE - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -isisc_mirr_port_in_get(a_uint32_t dev_id, fal_port_t port_id, a_bool_t * enable) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _isisc_mirr_port_in_get(dev_id, port_id, enable); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Set egress mirror status on a particular port. - * @param[in] dev_id device id - * @param[in] port_id port id - * @param[in] enable A_TRUE or A_FALSE - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -isisc_mirr_port_eg_set(a_uint32_t dev_id, fal_port_t port_id, a_bool_t enable) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _isisc_mirr_port_eg_set(dev_id, port_id, enable); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Get egress mirror status on a particular port. - * @param[in] dev_id device id - * @param[in] port_id port id - * @param[out] enable A_TRUE or A_FALSE - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -isisc_mirr_port_eg_get(a_uint32_t dev_id, fal_port_t port_id, a_bool_t * enable) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _isisc_mirr_port_eg_get(dev_id, port_id, enable); - HSL_API_UNLOCK; - return rv; -} - -sw_error_t -isisc_mirr_init(a_uint32_t dev_id) -{ - HSL_DEV_ID_CHECK(dev_id); - -#ifndef HSL_STANDALONG - { - hsl_api_t *p_api; - - SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id)); - - p_api->mirr_analysis_port_set = isisc_mirr_analysis_port_set; - p_api->mirr_analysis_port_get = isisc_mirr_analysis_port_get; - p_api->mirr_port_in_set = isisc_mirr_port_in_set; - p_api->mirr_port_in_get = isisc_mirr_port_in_get; - p_api->mirr_port_eg_set = isisc_mirr_port_eg_set; - p_api->mirr_port_eg_get = isisc_mirr_port_eg_get; - } -#endif - - return SW_OK; -} - -/** - * @} - */ - diff --git a/feeds/ipq807x/qca-ssdk/src/src/hsl/isisc/isisc_misc.c b/feeds/ipq807x/qca-ssdk/src/src/hsl/isisc/isisc_misc.c deleted file mode 100755 index bc79d4915..000000000 --- a/feeds/ipq807x/qca-ssdk/src/src/hsl/isisc/isisc_misc.c +++ /dev/null @@ -1,2207 +0,0 @@ -/* - * Copyright (c) 2012, 2015-2017, The Linux Foundation. All rights reserved. - * Permission to use, copy, modify, and/or distribute this software for - * any purpose with or without fee is hereby granted, provided that the - * above copyright notice and this permission notice appear in all copies. - * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES - * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR - * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES - * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN - * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT - * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. - */ - - -/** - * @defgroup isisc_misc ISISC_MISC - * @{ - */ -#include "sw.h" -#include "hsl.h" -#include "hsl_dev.h" -#include "hsl_port_prop.h" -#include "isisc_misc.h" -#include "isisc_reg.h" -#include "hsl_phy.h" - - -#define ISISC_MAX_FRMAE_SIZE 9216 - -#define ARP_REQ_EN_OFFSET 6 -#define ARP_ACK_EN_OFFSET 5 -#define DHCP_EN_OFFSET 4 -#define EAPOL_EN_OFFSET 3 - -#define ISISC_SWITCH_INT_PHY_INT 0x8000 - - -static sw_error_t -_isisc_port_misc_property_set(a_uint32_t dev_id, fal_port_t port_id, - a_bool_t enable, a_uint32_t item) -{ - sw_error_t rv; - a_uint32_t reg = 0, val; - - HSL_DEV_ID_CHECK(dev_id); - - if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU)) - { - return SW_BAD_PARAM; - } - - if (A_TRUE == enable) - { - val = 1; - } - else if (A_FALSE == enable) - { - val = 0; - } - else - { - return SW_BAD_PARAM; - } - - if (3 >= port_id) - { - HSL_REG_ENTRY_GET(rv, dev_id, FRAME_ACK_CTL0, 0, - (a_uint8_t *) (®), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - - reg &= ~(0x1UL << ((port_id << 3) + item)); - reg |= (val << ((port_id << 3) + item)); - - HSL_REG_ENTRY_SET(rv, dev_id, FRAME_ACK_CTL0, 0, - (a_uint8_t *) (®), sizeof (a_uint32_t)); - } - else - { - HSL_REG_ENTRY_GET(rv, dev_id, FRAME_ACK_CTL1, 0, - (a_uint8_t *) (®), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - - reg &= ~(0x1UL << (((port_id - 4) << 3) + item)); - reg |= (val << (((port_id - 4) << 3) + item)); - - HSL_REG_ENTRY_SET(rv, dev_id, FRAME_ACK_CTL1, 0, - (a_uint8_t *) (®), sizeof (a_uint32_t)); - } - return rv; -} - -#ifndef IN_MISC_MINI -static sw_error_t -_isisc_port_misc_property_get(a_uint32_t dev_id, fal_port_t port_id, - a_bool_t * enable, a_uint32_t item) -{ - sw_error_t rv; - a_uint32_t reg = 0, val; - - HSL_DEV_ID_CHECK(dev_id); - - if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU)) - { - return SW_BAD_PARAM; - } - - if (3 >= port_id) - { - HSL_REG_ENTRY_GET(rv, dev_id, FRAME_ACK_CTL0, 0, - (a_uint8_t *) (®), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - - val = (reg >> ((port_id << 3) + item)) & 0x1UL; - } - else - { - HSL_REG_ENTRY_GET(rv, dev_id, FRAME_ACK_CTL1, 0, - (a_uint8_t *) (®), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - - val = (reg >> (((port_id - 4) << 3) + item)) & 0x1UL; - } - - if (1 == val) - { - *enable = A_TRUE; - } - else - { - *enable = A_FALSE; - } - - return SW_OK; -} -#endif - -static sw_error_t -_isisc_frame_max_size_set(a_uint32_t dev_id, a_uint32_t size) -{ - a_uint32_t data; - sw_error_t rv; - - HSL_DEV_ID_CHECK(dev_id); - - if (ISISC_MAX_FRMAE_SIZE < size) - { - return SW_BAD_PARAM; - } - - data = size; - HSL_REG_FIELD_SET(rv, dev_id, MAX_SIZE, 0, MAX_FRAME_SIZE, - (a_uint8_t *) (&data), sizeof (a_uint32_t)); - return rv; -} - -static sw_error_t -_isisc_frame_max_size_get(a_uint32_t dev_id, a_uint32_t * size) -{ - a_uint32_t data = 0; - sw_error_t rv; - - HSL_DEV_ID_CHECK(dev_id); - - HSL_REG_FIELD_GET(rv, dev_id, MAX_SIZE, 0, MAX_FRAME_SIZE, - (a_uint8_t *) (&data), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - - *size = data; - return SW_OK; -} - -static sw_error_t -_isisc_port_unk_uc_filter_set(a_uint32_t dev_id, fal_port_t port_id, - a_bool_t enable) -{ - sw_error_t rv; - a_uint32_t data = 0; - - HSL_DEV_ID_CHECK(dev_id); - - if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU)) - { - return SW_BAD_PARAM; - } - - HSL_REG_FIELD_GET(rv, dev_id, FORWARD_CTL1, 0, UNI_FLOOD_DP, - (a_uint8_t *) (&data), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - - if (A_TRUE == enable) - { - data &= (~((a_uint32_t) 0x1 << port_id)); - } - else if (A_FALSE == enable) - { - data |= (0x1 << port_id); - } - else - { - return SW_BAD_PARAM; - } - - HSL_REG_FIELD_SET(rv, dev_id, FORWARD_CTL1, 0, UNI_FLOOD_DP, - (a_uint8_t *) (&data), sizeof (a_uint32_t)); - return rv; -} - - -static sw_error_t -_isisc_port_unk_mc_filter_set(a_uint32_t dev_id, fal_port_t port_id, - a_bool_t enable) -{ - sw_error_t rv; - a_uint32_t data = 0; - - HSL_DEV_ID_CHECK(dev_id); - - if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU)) - { - return SW_BAD_PARAM; - } - - HSL_REG_FIELD_GET(rv, dev_id, FORWARD_CTL1, 0, MUL_FLOOD_DP, - (a_uint8_t *) (&data), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - - if (A_TRUE == enable) - { - data &= (~((a_uint32_t) 0x1 << port_id)); - } - else if (A_FALSE == enable) - { - data |= (0x1 << port_id); - } - else - { - return SW_BAD_PARAM; - } - - HSL_REG_FIELD_SET(rv, dev_id, FORWARD_CTL1, 0, MUL_FLOOD_DP, - (a_uint8_t *) (&data), sizeof (a_uint32_t)); - return rv; -} - - -static sw_error_t -_isisc_port_bc_filter_set(a_uint32_t dev_id, fal_port_t port_id, a_bool_t enable) -{ - sw_error_t rv; - a_uint32_t data = 0; - - HSL_DEV_ID_CHECK(dev_id); - - if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU)) - { - return SW_BAD_PARAM; - } - - HSL_REG_FIELD_GET(rv, dev_id, FORWARD_CTL1, 0, BC_FLOOD_DP, - (a_uint8_t *) (&data), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - - if (A_TRUE == enable) - { - data &= (~((a_uint32_t) 0x1 << port_id)); - } - else if (A_FALSE == enable) - { - data |= (0x1 << port_id); - } - else - { - return SW_BAD_PARAM; - } - - HSL_REG_FIELD_SET(rv, dev_id, FORWARD_CTL1, 0, BC_FLOOD_DP, - (a_uint8_t *) (&data), sizeof (a_uint32_t)); - return rv; -} - -static sw_error_t -_isisc_cpu_port_status_set(a_uint32_t dev_id, a_bool_t enable) -{ - sw_error_t rv; - a_uint32_t val; - - HSL_DEV_ID_CHECK(dev_id); - - if (A_TRUE == enable) - { - val = 1; - } - else if (A_FALSE == enable) - { - val = 0; - } - else - { - return SW_BAD_PARAM; - } - - HSL_REG_FIELD_SET(rv, dev_id, FORWARD_CTL0, 0, CPU_PORT_EN, - (a_uint8_t *) (&val), sizeof (a_uint32_t)); - return rv; -} - -#ifndef IN_MISC_MINI -static sw_error_t -_isisc_port_bc_filter_get(a_uint32_t dev_id, fal_port_t port_id, - a_bool_t * enable) -{ - sw_error_t rv; - a_uint32_t reg = 0, field; - - HSL_DEV_ID_CHECK(dev_id); - - if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU)) - { - return SW_BAD_PARAM; - } - - HSL_REG_FIELD_GET(rv, dev_id, FORWARD_CTL1, 0, BC_FLOOD_DP, - (a_uint8_t *) (®), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - - field = reg & (0x1 << port_id); - if (field) - { - *enable = A_FALSE; - } - else - { - *enable = A_TRUE; - } - - return SW_OK; -} - -static sw_error_t -_isisc_port_unk_uc_filter_get(a_uint32_t dev_id, fal_port_t port_id, - a_bool_t * enable) -{ - sw_error_t rv; - a_uint32_t reg = 0, field; - - HSL_DEV_ID_CHECK(dev_id); - - if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU)) - { - return SW_BAD_PARAM; - } - - HSL_REG_FIELD_GET(rv, dev_id, FORWARD_CTL1, 0, UNI_FLOOD_DP, - (a_uint8_t *) (®), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - - field = reg & (0x1 << port_id); - if (field) - { - *enable = A_FALSE; - } - else - { - *enable = A_TRUE; - } - - return SW_OK; -} - -static sw_error_t -_isisc_port_unk_mc_filter_get(a_uint32_t dev_id, fal_port_t port_id, - a_bool_t * enable) -{ - sw_error_t rv; - a_uint32_t reg = 0, field; - - HSL_DEV_ID_CHECK(dev_id); - - if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU)) - { - return SW_BAD_PARAM; - } - - HSL_REG_FIELD_GET(rv, dev_id, FORWARD_CTL1, 0, MUL_FLOOD_DP, - (a_uint8_t *) (®), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - - field = reg & (0x1 << port_id); - if (field) - { - *enable = A_FALSE; - } - else - { - *enable = A_TRUE; - } - - return SW_OK; -} - -static sw_error_t -_isisc_cpu_port_status_get(a_uint32_t dev_id, a_bool_t * enable) -{ - sw_error_t rv; - a_uint32_t val = 0; - - HSL_DEV_ID_CHECK(dev_id); - - HSL_REG_FIELD_GET(rv, dev_id, FORWARD_CTL0, 0, CPU_PORT_EN, - (a_uint8_t *) (&val), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - - if (1 == val) - { - *enable = A_TRUE; - } - else - { - *enable = A_FALSE; - } - - return SW_OK; -} - -static sw_error_t -_isisc_cpu_vid_en_set(a_uint32_t dev_id, a_bool_t enable) -{ - sw_error_t rv; - a_uint32_t val; - - HSL_DEV_ID_CHECK(dev_id); - - if (A_TRUE == enable) - { - val = 1; - } - else if (A_FALSE == enable) - { - val = 0; - } - else - { - return SW_BAD_PARAM; - } - - HSL_REG_FIELD_SET(rv, dev_id, PKT_CTRL, 0, CPU_VID_EN, - (a_uint8_t *) (&val), sizeof (a_uint32_t)); - return rv; -} - -static sw_error_t -_isisc_cpu_vid_en_get(a_uint32_t dev_id, a_bool_t * enable) -{ - sw_error_t rv; - a_uint32_t val = 0; - - HSL_DEV_ID_CHECK(dev_id); - - HSL_REG_FIELD_GET(rv, dev_id, PKT_CTRL, 0, CPU_VID_EN, - (a_uint8_t *) (&val), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - - if (1 == val) - { - *enable = A_TRUE; - } - else - { - *enable = A_FALSE; - } - - return SW_OK; -} - -static sw_error_t -_isisc_rtd_pppoe_en_set(a_uint32_t dev_id, a_bool_t enable) -{ - sw_error_t rv; - a_uint32_t val; - - HSL_DEV_ID_CHECK(dev_id); - - if (A_TRUE == enable) - { - val = 1; - } - else if (A_FALSE == enable) - { - val = 0; - } - else - { - return SW_BAD_PARAM; - } - - HSL_REG_FIELD_SET(rv, dev_id, PKT_CTRL, 0, RTD_PPPOE_EN, - (a_uint8_t *) (&val), sizeof (a_uint32_t)); - return rv; -} - -static sw_error_t -_isisc_rtd_pppoe_en_get(a_uint32_t dev_id, a_bool_t * enable) -{ - sw_error_t rv; - a_uint32_t val = 0; - - HSL_DEV_ID_CHECK(dev_id); - - HSL_REG_FIELD_GET(rv, dev_id, PKT_CTRL, 0, RTD_PPPOE_EN, - (a_uint8_t *) (&val), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - - if (1 == val) - { - *enable = A_TRUE; - } - else - { - *enable = A_FALSE; - } - - return SW_OK; -} - - -static sw_error_t -_isisc_pppoe_cmd_set(a_uint32_t dev_id, fal_fwd_cmd_t cmd) -{ - sw_error_t rv; - a_uint32_t val; - - HSL_DEV_ID_CHECK(dev_id); - - if (FAL_MAC_FRWRD == cmd) - { - val = 0; - } - else if (FAL_MAC_RDT_TO_CPU == cmd) - { - val = 1; - } - else - { - return SW_NOT_SUPPORTED; - } - - HSL_REG_FIELD_SET(rv, dev_id, FORWARD_CTL0, 0, PPPOE_RDT_EN, - (a_uint8_t *) (&val), sizeof (a_uint32_t)); - return rv; -} - -static sw_error_t -_isisc_pppoe_cmd_get(a_uint32_t dev_id, fal_fwd_cmd_t * cmd) -{ - sw_error_t rv; - a_uint32_t val = 0; - - HSL_DEV_ID_CHECK(dev_id); - - HSL_REG_FIELD_GET(rv, dev_id, FORWARD_CTL0, 0, PPPOE_RDT_EN, - (a_uint8_t *) (&val), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - - if (1 == val) - { - *cmd = FAL_MAC_RDT_TO_CPU; - } - else - { - *cmd = FAL_MAC_FRWRD; - } - - return SW_OK; -} - -static sw_error_t -_isisc_pppoe_status_set(a_uint32_t dev_id, a_bool_t enable) -{ - sw_error_t rv; - a_uint32_t val; - - HSL_DEV_ID_CHECK(dev_id); - - if (A_TRUE == enable) - { - val = 1; - } - else if (A_FALSE == enable) - { - val = 0; - } - else - { - return SW_BAD_PARAM; - } - - HSL_REG_FIELD_SET(rv, dev_id, FRAME_ACK_CTL1, 0, PPPOE_EN, - (a_uint8_t *) (&val), sizeof (a_uint32_t)); - return rv; -} - -static sw_error_t -_isisc_pppoe_status_get(a_uint32_t dev_id, a_bool_t * enable) -{ - sw_error_t rv; - a_uint32_t val = 0; - - HSL_DEV_ID_CHECK(dev_id); - - HSL_REG_FIELD_GET(rv, dev_id, FRAME_ACK_CTL1, 0, PPPOE_EN, - (a_uint8_t *) (&val), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - - if (1 == val) - { - *enable = A_TRUE; - } - else - { - *enable = A_FALSE; - } - - return SW_OK; -} - -static sw_error_t -_isisc_arp_cmd_set(a_uint32_t dev_id, fal_fwd_cmd_t cmd) -{ - sw_error_t rv; - a_uint32_t val; - - HSL_DEV_ID_CHECK(dev_id); - - if (FAL_MAC_CPY_TO_CPU == cmd) - { - val = 1; - } - else if (FAL_MAC_RDT_TO_CPU == cmd) - { - val = 0; - } - else if (FAL_MAC_FRWRD == cmd) - { - val = 2; - } - else - { - return SW_NOT_SUPPORTED; - } - - HSL_REG_FIELD_SET(rv, dev_id, FORWARD_CTL0, 0, ARP_CMD, - (a_uint8_t *) (&val), sizeof (a_uint32_t)); - return rv; -} - -static sw_error_t -_isisc_arp_cmd_get(a_uint32_t dev_id, fal_fwd_cmd_t * cmd) -{ - sw_error_t rv; - a_uint32_t val = 0; - - HSL_DEV_ID_CHECK(dev_id); - - HSL_REG_FIELD_GET(rv, dev_id, FORWARD_CTL0, 0, ARP_CMD, - (a_uint8_t *) (&val), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - - if (1 == val) - { - *cmd = FAL_MAC_CPY_TO_CPU; - } - else if (0 == val) - { - *cmd = FAL_MAC_RDT_TO_CPU; - } - else - { - *cmd = FAL_MAC_FRWRD; - } - - return SW_OK; -} -#endif - -static sw_error_t -_isisc_eapol_cmd_set(a_uint32_t dev_id, fal_fwd_cmd_t cmd) -{ - sw_error_t rv; - a_uint32_t val; - - HSL_DEV_ID_CHECK(dev_id); - - if (FAL_MAC_CPY_TO_CPU == cmd) - { - val = 0; - } - else if (FAL_MAC_RDT_TO_CPU == cmd) - { - val = 1; - } - else - { - return SW_NOT_SUPPORTED; - } - - HSL_REG_FIELD_SET(rv, dev_id, FORWARD_CTL0, 0, EAPOL_CMD, - (a_uint8_t *) (&val), sizeof (a_uint32_t)); - return rv; -} - -#ifndef IN_MISC_MINI -static sw_error_t -_isisc_eapol_cmd_get(a_uint32_t dev_id, fal_fwd_cmd_t * cmd) -{ - sw_error_t rv; - a_uint32_t val = 0; - - HSL_DEV_ID_CHECK(dev_id); - - HSL_REG_FIELD_GET(rv, dev_id, FORWARD_CTL0, 0, EAPOL_CMD, - (a_uint8_t *) (&val), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - - if (0 == val) - { - *cmd = FAL_MAC_CPY_TO_CPU; - } - else - { - *cmd = FAL_MAC_RDT_TO_CPU; - } - - return SW_OK; -} - -#define ISISC_MAX_PPPOE_SESSION 16 -#define ISISC_MAX_SESSION_ID 0xffff - -static sw_error_t -_isisc_pppoe_session_add(a_uint32_t dev_id, fal_pppoe_session_t * session_tbl) -{ - sw_error_t rv; - a_uint32_t reg = 0, i, valid, id, entry_idx = ISISC_MAX_PPPOE_SESSION; - - HSL_DEV_ID_CHECK(dev_id); - - if (session_tbl->session_id > ISISC_MAX_SESSION_ID) - { - return SW_BAD_PARAM; - } - - if ((A_FALSE == session_tbl->multi_session) - && (A_TRUE == session_tbl->uni_session)) - { - return SW_BAD_PARAM; - } - - if ((A_FALSE == session_tbl->multi_session) - && (A_FALSE == session_tbl->uni_session)) - { - return SW_BAD_PARAM; - } - - for (i = 0; i < ISISC_MAX_PPPOE_SESSION; i++) - { - HSL_REG_ENTRY_GET(rv, dev_id, PPPOE_SESSION, i, - (a_uint8_t *) (®), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - - SW_GET_FIELD_BY_REG(PPPOE_SESSION, ENTRY_VALID, valid, reg); - SW_GET_FIELD_BY_REG(PPPOE_SESSION, SEESION_ID, id, reg); - - if (!valid) - { - entry_idx = i; - } - else if (id == session_tbl->session_id) - { - return SW_ALREADY_EXIST; - } - } - - if (ISISC_MAX_PPPOE_SESSION == entry_idx) - { - return SW_NO_RESOURCE; - } - -#if 0 - if (A_TRUE == session_tbl->uni_session) - { - SW_SET_REG_BY_FIELD(PPPOE_SESSION, ENTRY_VALID, 2, reg); - } - else -#endif - { - SW_SET_REG_BY_FIELD(PPPOE_SESSION, ENTRY_VALID, 1, reg); - } - SW_SET_REG_BY_FIELD(PPPOE_SESSION, SEESION_ID, session_tbl->session_id, - reg); - - HSL_REG_ENTRY_SET(rv, dev_id, PPPOE_SESSION, entry_idx, - (a_uint8_t *) (®), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - - session_tbl->entry_id = entry_idx; - return SW_OK; -} - -static sw_error_t -_isisc_pppoe_session_del(a_uint32_t dev_id, fal_pppoe_session_t * session_tbl) -{ - sw_error_t rv; - a_uint32_t reg = 0, i, valid, id; - - HSL_DEV_ID_CHECK(dev_id); - - if (session_tbl->session_id > ISISC_MAX_SESSION_ID) - { - return SW_BAD_PARAM; - } - - for (i = 0; i < ISISC_MAX_PPPOE_SESSION; i++) - { - HSL_REG_ENTRY_GET(rv, dev_id, PPPOE_SESSION, i, - (a_uint8_t *) (®), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - - SW_GET_FIELD_BY_REG(PPPOE_SESSION, ENTRY_VALID, valid, reg); - SW_GET_FIELD_BY_REG(PPPOE_SESSION, SEESION_ID, id, reg); - - if (((1 == valid) || (2 == valid)) && (id == session_tbl->session_id)) - { - SW_SET_REG_BY_FIELD(PPPOE_SESSION, ENTRY_VALID, 0, reg); - SW_SET_REG_BY_FIELD(PPPOE_SESSION, SEESION_ID, 0, reg); - HSL_REG_ENTRY_SET(rv, dev_id, PPPOE_SESSION, i, - (a_uint8_t *) (®), sizeof (a_uint32_t)); - return rv; - } - } - - return SW_NOT_FOUND; -} - -static sw_error_t -_isisc_pppoe_session_get(a_uint32_t dev_id, fal_pppoe_session_t * session_tbl) -{ - sw_error_t rv; - a_uint32_t reg = 0, i, valid, id; - - HSL_DEV_ID_CHECK(dev_id); - - if (session_tbl->session_id > ISISC_MAX_SESSION_ID) - { - return SW_BAD_PARAM; - } - - for (i = 0; i < ISISC_MAX_PPPOE_SESSION; i++) - { - HSL_REG_ENTRY_GET(rv, dev_id, PPPOE_SESSION, i, - (a_uint8_t *) (®), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - - SW_GET_FIELD_BY_REG(PPPOE_SESSION, ENTRY_VALID, valid, reg); - SW_GET_FIELD_BY_REG(PPPOE_SESSION, SEESION_ID, id, reg); - - if (((1 == valid) || (2 == valid)) && (id == session_tbl->session_id)) - { - if (1 == valid) - { - session_tbl->multi_session = A_TRUE; - session_tbl->uni_session = A_FALSE; - } - else - { - session_tbl->multi_session = A_TRUE; - session_tbl->uni_session = A_TRUE; - } - - session_tbl->entry_id = i; - return SW_OK; - } - } - - return SW_NOT_FOUND; -} - -static sw_error_t -_isisc_pppoe_session_id_set(a_uint32_t dev_id, a_uint32_t index, - a_uint32_t id) -{ - sw_error_t rv; - a_uint32_t reg; - - if (ISISC_MAX_PPPOE_SESSION <= index) - { - return SW_BAD_PARAM; - } - - if (ISISC_MAX_SESSION_ID < id) - { - return SW_BAD_PARAM; - } - - reg = 0; - SW_SET_REG_BY_FIELD(PPPOE_EDIT, EDIT_ID, id, reg); - HSL_REG_ENTRY_SET(rv, dev_id, PPPOE_EDIT, index, (a_uint8_t *) (®), - sizeof (a_uint32_t)); - - return rv; -} - -static sw_error_t -_isisc_pppoe_session_id_get(a_uint32_t dev_id, a_uint32_t index, - a_uint32_t * id) -{ - sw_error_t rv; - a_uint32_t reg = 0, tmp; - - if (ISISC_MAX_PPPOE_SESSION <= index) - { - return SW_BAD_PARAM; - } - - HSL_REG_ENTRY_GET(rv, dev_id, PPPOE_EDIT, index, (a_uint8_t *) (®), - sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - - tmp = 0; - SW_GET_FIELD_BY_REG(PPPOE_EDIT, EDIT_ID, tmp, reg); - *id = tmp; - return SW_OK; -} - -static sw_error_t -_isisc_ripv1_status_set(a_uint32_t dev_id, a_bool_t enable) -{ - a_uint32_t data; - sw_error_t rv; - - HSL_DEV_ID_CHECK(dev_id); - - if (A_TRUE != hsl_port_prop_check(dev_id, 0, HSL_PP_INCL_CPU)) - { - return SW_BAD_PARAM; - } - - if (A_TRUE == enable) - { - data = 1; - } - else if (A_FALSE == enable) - { - data = 0; - } - else - { - return SW_BAD_PARAM; - } - - HSL_REG_FIELD_SET(rv, dev_id, FORWARD_CTL0, 0, RIP_CPY_EN, - (a_uint8_t *) (&data), sizeof (a_uint32_t)); - return rv; -} - -static sw_error_t -_isisc_ripv1_status_get(a_uint32_t dev_id, a_bool_t * enable) -{ - a_uint32_t data = 0; - sw_error_t rv; - - HSL_DEV_ID_CHECK(dev_id); - - if (A_TRUE != hsl_port_prop_check(dev_id, 0, HSL_PP_INCL_CPU)) - { - return SW_BAD_PARAM; - } - - HSL_REG_FIELD_GET(rv, dev_id, FORWARD_CTL0, 0, RIP_CPY_EN, - (a_uint8_t *) (&data), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - - if (1 == data) - { - *enable = A_TRUE; - } - else - { - *enable = A_FALSE; - } - - return SW_OK; -} - -static sw_error_t -_isisc_intr_mask_set(a_uint32_t dev_id, a_uint32_t intr_mask) -{ - sw_error_t rv; - a_uint32_t reg = 0; - - HSL_REG_ENTRY_GET(rv, dev_id, GBL_INT_MASK1, 0, (a_uint8_t *) (®), - sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - - if (intr_mask & FAL_SWITCH_INTR_LINK_STATUS) - { - reg |= ISISC_SWITCH_INT_PHY_INT; - } - else - { - reg &= (~ISISC_SWITCH_INT_PHY_INT); - } - - HSL_REG_ENTRY_SET(rv, dev_id, GBL_INT_MASK1, 0, (a_uint8_t *) (®), - sizeof (a_uint32_t)); - return rv; -} - -static sw_error_t -_isisc_intr_mask_get(a_uint32_t dev_id, a_uint32_t * intr_mask) -{ - sw_error_t rv; - a_uint32_t reg = 0; - - *intr_mask = 0; - HSL_REG_ENTRY_GET(rv, dev_id, GBL_INT_MASK1, 0, (a_uint8_t *) (®), - sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - - if (reg & ISISC_SWITCH_INT_PHY_INT) - { - *intr_mask |= FAL_SWITCH_INTR_LINK_STATUS; - } - - return SW_OK; -} - -static sw_error_t -_isisc_intr_status_get(a_uint32_t dev_id, a_uint32_t * intr_status) -{ - sw_error_t rv; - a_uint32_t reg = 0; - - *intr_status = 0; - HSL_REG_ENTRY_GET(rv, dev_id, GBL_INT_STATUS1, 0, (a_uint8_t *) (®), - sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - - if (reg & ISISC_SWITCH_INT_PHY_INT) - { - *intr_status |= FAL_SWITCH_INTR_LINK_STATUS; - } - - return SW_OK; -} - -static sw_error_t -_isisc_intr_status_clear(a_uint32_t dev_id, a_uint32_t intr_status) -{ - sw_error_t rv; - a_uint32_t reg; - - reg = 0; - if (intr_status & FAL_SWITCH_INTR_LINK_STATUS) - { - reg |= ISISC_SWITCH_INT_PHY_INT; - } - - HSL_REG_ENTRY_SET(rv, dev_id, GBL_INT_STATUS1, 0, (a_uint8_t *) (®), - sizeof (a_uint32_t)); - return rv; -} - -static sw_error_t -_isisc_port_link_intr_mask_set(a_uint32_t dev_id, a_uint32_t port_id, a_uint32_t intr_mask_flag) -{ - sw_error_t rv; - a_uint32_t phy_id; - hsl_phy_ops_t *phy_drv; - - HSL_DEV_ID_CHECK(dev_id); - - if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_PHY)) - { - return SW_BAD_PARAM; - } - - SW_RTN_ON_NULL (phy_drv = hsl_phy_api_ops_get (dev_id, port_id)); - if (NULL == phy_drv->phy_intr_mask_set) - return SW_NOT_SUPPORTED; - - rv = hsl_port_prop_get_phyid(dev_id, port_id, &phy_id); - SW_RTN_ON_ERROR(rv); - - rv = phy_drv->phy_intr_mask_set(dev_id, phy_id, intr_mask_flag); - return rv; -} - -static sw_error_t -_isisc_port_link_intr_mask_get(a_uint32_t dev_id, a_uint32_t port_id, a_uint32_t * intr_mask_flag) -{ - sw_error_t rv; - a_uint32_t phy_id; - hsl_phy_ops_t *phy_drv; - - HSL_DEV_ID_CHECK(dev_id); - - if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_PHY)) - { - return SW_BAD_PARAM; - } - - SW_RTN_ON_NULL (phy_drv = hsl_phy_api_ops_get (dev_id, port_id)); - if (NULL == phy_drv->phy_intr_mask_get) - return SW_NOT_SUPPORTED; - - rv = hsl_port_prop_get_phyid(dev_id, port_id, &phy_id); - SW_RTN_ON_ERROR(rv); - - rv = phy_drv->phy_intr_mask_get(dev_id, phy_id, intr_mask_flag); - return rv; -} - -static sw_error_t -_isisc_port_link_intr_status_get(a_uint32_t dev_id, a_uint32_t port_id, a_uint32_t * intr_mask_flag) -{ - sw_error_t rv; - a_uint32_t phy_id; - hsl_phy_ops_t *phy_drv; - - HSL_DEV_ID_CHECK(dev_id); - - if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_PHY)) - { - return SW_BAD_PARAM; - } - - SW_RTN_ON_NULL (phy_drv = hsl_phy_api_ops_get (dev_id, port_id)); - if (NULL == phy_drv->phy_intr_status_get) - return SW_NOT_SUPPORTED; - - rv = hsl_port_prop_get_phyid(dev_id, port_id, &phy_id); - SW_RTN_ON_ERROR(rv); - - rv = phy_drv->phy_intr_status_get(dev_id, phy_id, intr_mask_flag); - return rv; -} - -static sw_error_t -_isisc_intr_mask_mac_linkchg_set(a_uint32_t dev_id, a_uint32_t port_id, a_bool_t enable) -{ - sw_error_t rv; - a_uint32_t data = 0; - - HSL_DEV_ID_CHECK(dev_id); - - if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU)) - { - return SW_BAD_PARAM; - } - - HSL_REG_FIELD_GET(rv, dev_id, GBL_INT_MASK1, 0, LINK_CHG_INT_M, - (a_uint8_t *) (&data), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - - if (A_FALSE == enable) - { - data &= (~((a_uint32_t) 0x1 << port_id)); - } - else if (A_TRUE == enable) - { - data |= (0x1 << port_id); - } - else - { - return SW_BAD_PARAM; - } - - HSL_REG_FIELD_SET(rv, dev_id, GBL_INT_MASK1, 0, LINK_CHG_INT_M, - (a_uint8_t *) (&data), sizeof (a_uint32_t)); - - return rv; -} - - -static sw_error_t -_isisc_intr_mask_mac_linkchg_get(a_uint32_t dev_id, a_uint32_t port_id, a_bool_t * enable) -{ - sw_error_t rv; - a_uint32_t reg = 0, field; - - HSL_DEV_ID_CHECK(dev_id); - - if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU)) - { - return SW_BAD_PARAM; - } - - HSL_REG_FIELD_GET(rv, dev_id, GBL_INT_MASK1, 0, LINK_CHG_INT_M, - (a_uint8_t *) (®), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - - field = reg & (0x1 << port_id); - if (field) - { - *enable = A_TRUE; - } - else - { - *enable = A_FALSE; - } - - return SW_OK; -} - - -static sw_error_t -_isisc_intr_status_mac_linkchg_get(a_uint32_t dev_id, fal_pbmp_t* port_bitmap) -{ - sw_error_t rv; - a_uint32_t reg = 0; - - HSL_DEV_ID_CHECK(dev_id); - - HSL_REG_FIELD_GET(rv, dev_id, GBL_INT_STATUS1, 0, LINK_CHG_INT_S, - (a_uint8_t *) (®), sizeof (a_uint32_t)); - *port_bitmap = reg; - - return rv; - -} - -static sw_error_t -_isisc_intr_status_mac_linkchg_clear(a_uint32_t dev_id) -{ - sw_error_t rv; - a_uint32_t reg; - - HSL_DEV_ID_CHECK(dev_id); - - HSL_REG_FIELD_GET(rv, dev_id, GBL_INT_STATUS1, 0, LINK_CHG_INT_S, - (a_uint8_t *) (®), sizeof (a_uint32_t)); - - HSL_REG_FIELD_SET(rv, dev_id, GBL_INT_STATUS1, 0, LINK_CHG_INT_S, - (a_uint8_t *) (®), sizeof (a_uint32_t)); - - return rv; - -} -#endif - -/** - * @brief Set max frame size which device can received on a particular device. - * @details Comments: - * The granularity of packets size is byte. - * @param[in] dev_id device id - * @param[in] size packet size - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -isisc_frame_max_size_set(a_uint32_t dev_id, a_uint32_t size) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _isisc_frame_max_size_set(dev_id, size); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Get max frame size which device can received on a particular device. - * @details Comments: - * The unit of packets size is byte. - * @param[in] dev_id device id - * @param[out] size packet size - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -isisc_frame_max_size_get(a_uint32_t dev_id, a_uint32_t * size) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _isisc_frame_max_size_get(dev_id, size); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Set flooding status of unknown unicast packets on a particular port. - * @details Comments: - * If enable unknown unicast packets filter on one port then unknown - * unicast packets can't flood out from this port. - * @param[in] dev_id device id - * @param[in] port_id port id - * @param[in] enable A_TRUE or A_FALSE - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -isisc_port_unk_uc_filter_set(a_uint32_t dev_id, fal_port_t port_id, - a_bool_t enable) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _isisc_port_unk_uc_filter_set(dev_id, port_id, enable); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Set flooding status of unknown multicast packets on a particular port. - * @details Comments: - * If enable unknown multicast packets filter on one port then unknown - * multicast packets can't flood out from this port. - * @param[in] dev_id device id - * @param[in] port_id port id - * @param[in] enable A_TRUE or A_FALSE - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -isisc_port_unk_mc_filter_set(a_uint32_t dev_id, fal_port_t port_id, - a_bool_t enable) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _isisc_port_unk_mc_filter_set(dev_id, port_id, enable); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Set flooding status of broadcast packets on a particular port. - * @details Comments: - * If enable unknown multicast packets filter on one port then unknown - * multicast packets can't flood out from this port. - * @param[in] dev_id device id - * @param[in] port_id port id - * @param[in] enable A_TRUE or A_FALSE - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -isisc_port_bc_filter_set(a_uint32_t dev_id, fal_port_t port_id, a_bool_t enable) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _isisc_port_bc_filter_set(dev_id, port_id, enable); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Set cpu port status on a particular device. - * @param[in] dev_id device id - * @param[in] enable A_TRUE or A_FALSE - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -isisc_cpu_port_status_set(a_uint32_t dev_id, a_bool_t enable) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _isisc_cpu_port_status_set(dev_id, enable); - HSL_API_UNLOCK; - return rv; -} - -#ifndef IN_MISC_MINI -/** - * @brief Get flooding status of unknown unicast packets on a particular port. - * @param[in] dev_id device id - * @param[in] port_id port id - * @param[out] enable A_TRUE or A_FALSE - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -isisc_port_unk_uc_filter_get(a_uint32_t dev_id, fal_port_t port_id, - a_bool_t * enable) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _isisc_port_unk_uc_filter_get(dev_id, port_id, enable); - HSL_API_UNLOCK; - return rv; -} - -/** @brief Get flooding status of unknown multicast packets on a particular port. - * @param[in] dev_id device id - * @param[in] port_id port id - * @param[out] enable A_TRUE or A_FALSE - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -isisc_port_unk_mc_filter_get(a_uint32_t dev_id, fal_port_t port_id, - a_bool_t * enable) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _isisc_port_unk_mc_filter_get(dev_id, port_id, enable); - HSL_API_UNLOCK; - return rv; -} - -/** @brief Get flooding status of broadcast packets on a particular port. - * @param[in] dev_id device id - * @param[in] port_id port id - * @param[out] enable A_TRUE or A_FALSE - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -isisc_port_bc_filter_get(a_uint32_t dev_id, fal_port_t port_id, - a_bool_t * enable) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _isisc_port_bc_filter_get(dev_id, port_id, enable); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Get cpu port status on a particular device. - * @param[in] dev_id device id - * @param[in] enable A_TRUE or A_FALSE - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -isisc_cpu_port_status_get(a_uint32_t dev_id, a_bool_t * enable) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _isisc_cpu_port_status_get(dev_id, enable); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Set pppoe packets forwarding command on a particular device. - * @details comments: - * Particular device may only support parts of forwarding commands. - * Ihis operation will take effect only after enabling pppoe packets - * hardware acknowledgement - * @param[in] dev_id device id - * @param[in] cmd forwarding command - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -isisc_pppoe_cmd_set(a_uint32_t dev_id, fal_fwd_cmd_t cmd) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _isisc_pppoe_cmd_set(dev_id, cmd); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Get pppoe packets forwarding command on a particular device. - * @param[in] dev_id device id - * @param[out] cmd forwarding command - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -isisc_pppoe_cmd_get(a_uint32_t dev_id, fal_fwd_cmd_t * cmd) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _isisc_pppoe_cmd_get(dev_id, cmd); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Set pppoe packets hardware acknowledgement status on particular device. - * @details comments: - * Particular device may only support parts of pppoe packets. - * @param[in] dev_id device id - * @param[in] enable A_TRUE or A_FALSE - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -isisc_pppoe_status_set(a_uint32_t dev_id, a_bool_t enable) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _isisc_pppoe_status_set(dev_id, enable); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Get pppoe packets hardware acknowledgement status on a particular device. - * @param[in] dev_id device id - * @param[out] enable A_TRUE or A_FALSE - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -isisc_pppoe_status_get(a_uint32_t dev_id, a_bool_t * enable) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _isisc_pppoe_status_get(dev_id, enable); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Set dhcp packets hardware acknowledgement status on a particular device. - * @param[in] dev_id device id - * @param[in] enable A_TRUE or A_FALSE - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -isisc_port_dhcp_set(a_uint32_t dev_id, fal_port_t port_id, a_bool_t enable) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _isisc_port_misc_property_set(dev_id, port_id, enable, DHCP_EN_OFFSET); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Get dhcp packets hardware acknowledgement status on particular device. - * @param[in] dev_id device id - * @param[out] enable A_TRUE or A_FALSE - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -isisc_port_dhcp_get(a_uint32_t dev_id, fal_port_t port_id, a_bool_t * enable) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _isisc_port_misc_property_get(dev_id, port_id, enable, DHCP_EN_OFFSET); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Set arp packets forwarding command on a particular device. - * @details comments: - * Particular device may only support parts of forwarding commands. - * Ihis operation will take effect only after enabling arp packets - * hardware acknowledgement - * @param[in] dev_id device id - * @param[in] cmd forwarding command - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -isisc_arp_cmd_set(a_uint32_t dev_id, fal_fwd_cmd_t cmd) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _isisc_arp_cmd_set(dev_id, cmd); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Get arp packets forwarding command on a particular device. - * @param[in] dev_id device id - * @param[out] cmd forwarding command - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -isisc_arp_cmd_get(a_uint32_t dev_id, fal_fwd_cmd_t * cmd) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _isisc_arp_cmd_get(dev_id, cmd); - HSL_API_UNLOCK; - return rv; -} -#endif - -/** - * @brief Set eapol packets forwarding command on a particular device. - * @details comments: - * Particular device may only support parts of forwarding commands. - * Ihis operation will take effect only after enabling eapol packets - * hardware acknowledgement - * @param[in] dev_id device id - * @param[in] cmd forwarding command - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -isisc_eapol_cmd_set(a_uint32_t dev_id, fal_fwd_cmd_t cmd) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _isisc_eapol_cmd_set(dev_id, cmd); - HSL_API_UNLOCK; - return rv; -} - -#ifndef IN_MISC_MINI -/** - * @brief Get eapol packets forwarding command on a particular device. - * @param[in] dev_id device id - * @param[out] cmd forwarding command - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -isisc_eapol_cmd_get(a_uint32_t dev_id, fal_fwd_cmd_t * cmd) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _isisc_eapol_cmd_get(dev_id, cmd); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Add a pppoe session entry to a particular device. - * The entry only for pppoe/ppp header remove. - * @param[in] dev_id device id - * @param[in] session_tbl pppoe session table - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -isisc_pppoe_session_table_add(a_uint32_t dev_id, - fal_pppoe_session_t * session_tbl) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _isisc_pppoe_session_add(dev_id, session_tbl); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Delete a pppoe session entry from a particular device. - * The entry only for pppoe/ppp header remove. - * @param[in] dev_id device id - * @param[in] session_tbl pppoe session table - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -isisc_pppoe_session_table_del(a_uint32_t dev_id, - fal_pppoe_session_t * session_tbl) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _isisc_pppoe_session_del(dev_id, session_tbl); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Get a pppoe session entry from a particular device. - * The entry only for pppoe/ppp header remove. - * @param[in] dev_id device id - * @param[out] session_tbl pppoe session table - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -isisc_pppoe_session_table_get(a_uint32_t dev_id, - fal_pppoe_session_t * session_tbl) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _isisc_pppoe_session_get(dev_id, session_tbl); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Set a pppoe session id entry to a particular device. - * The entry only for pppoe/ppp header add. - * @param[in] dev_id device id - * @param[in] session_tbl pppoe session table - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -isisc_pppoe_session_id_set(a_uint32_t dev_id, a_uint32_t index, - a_uint32_t id) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _isisc_pppoe_session_id_set(dev_id, index, id); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Get a pppoe session id entry from a particular device. - * The entry only for pppoe/ppp header add. - * @param[in] dev_id device id - * @param[out] session_tbl pppoe session table - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -isisc_pppoe_session_id_get(a_uint32_t dev_id, a_uint32_t index, - a_uint32_t * id) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _isisc_pppoe_session_id_get(dev_id, index, id); - HSL_API_UNLOCK; - return rv; -} -#endif - -/** - * @brief Set eapol packets hardware acknowledgement status on a particular port. - * @param[in] dev_id device id - * @param[in] port_id port id - * @param[in] enable A_TRUE or A_FALSE - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -isisc_eapol_status_set(a_uint32_t dev_id, a_uint32_t port_id, a_bool_t enable) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _isisc_port_misc_property_set(dev_id, port_id, enable, EAPOL_EN_OFFSET); - HSL_API_UNLOCK; - return rv; -} - -#ifndef IN_MISC_MINI -/** - * @brief Get eapol packets hardware acknowledgement status on a particular port. - * @param[in] dev_id device id - * @param[in] port_id port id - * @param[out] enable A_TRUE or A_FALSE - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -isisc_eapol_status_get(a_uint32_t dev_id, a_uint32_t port_id, a_bool_t * enable) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _isisc_port_misc_property_get(dev_id, port_id, enable, EAPOL_EN_OFFSET); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Set rip v1 packets hardware acknowledgement status on a particular port. - * @param[in] dev_id device id - * @param[in] enable A_TRUE or A_FALSE - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -isisc_ripv1_status_set(a_uint32_t dev_id, a_bool_t enable) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _isisc_ripv1_status_set(dev_id, enable); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Get rip v1 packets hardware acknowledgement status on a particular port. - * @param[in] dev_id device id - * @param[out] enable A_TRUE or A_FALSE - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -isisc_ripv1_status_get(a_uint32_t dev_id, a_bool_t * enable) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _isisc_ripv1_status_get(dev_id, enable); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Set arp req packets hardware acknowledgement status on a particular device. - * @param[in] dev_id device id - * @param[in] enable A_TRUE or A_FALSE - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -isisc_port_arp_req_status_set(a_uint32_t dev_id, fal_port_t port_id, - a_bool_t enable) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _isisc_port_misc_property_set(dev_id, port_id, enable, - ARP_REQ_EN_OFFSET); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Get arp req packets hardware acknowledgement status on a particular device. - * @param[in] dev_id device id - * @param[out] enable A_TRUE or A_FALSE - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -isisc_port_arp_req_status_get(a_uint32_t dev_id, fal_port_t port_id, - a_bool_t * enable) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _isisc_port_misc_property_get(dev_id, port_id, enable, - ARP_REQ_EN_OFFSET); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Set arp ack packets hardware acknowledgement status on a particular device. - * @param[in] dev_id device id - * @param[in] enable A_TRUE or A_FALSE - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -isisc_port_arp_ack_status_set(a_uint32_t dev_id, fal_port_t port_id, - a_bool_t enable) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _isisc_port_misc_property_set(dev_id, port_id, enable, - ARP_ACK_EN_OFFSET); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Get arp ack packets hardware acknowledgement status on a particular device. - * @param[in] dev_id device id - * @param[out] enable A_TRUE or A_FALSE - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -isisc_port_arp_ack_status_get(a_uint32_t dev_id, fal_port_t port_id, - a_bool_t * enable) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _isisc_port_misc_property_get(dev_id, port_id, enable, - ARP_ACK_EN_OFFSET); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Set switch interrupt mask on one particular device. - * @param[in] dev_id device id - * @param[in] intr_mask mask - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -isisc_intr_mask_set(a_uint32_t dev_id, a_uint32_t intr_mask) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _isisc_intr_mask_set(dev_id, intr_mask); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Get switch interrupt mask on one particular device. - * @param[in] dev_id device id - * @param[in] intr_mask mask - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -isisc_intr_mask_get(a_uint32_t dev_id, a_uint32_t * intr_mask) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _isisc_intr_mask_get(dev_id, intr_mask); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Get switch interrupt status on one particular device. - * @param[in] dev_id device id - * @param[in] intr_status status - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -isisc_intr_status_get(a_uint32_t dev_id, a_uint32_t * intr_status) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _isisc_intr_status_get(dev_id, intr_status); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Clear switch interrupt status on one particular device. - * @param[in] dev_id device id - * @param[in] intr_status status - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -isisc_intr_status_clear(a_uint32_t dev_id, a_uint32_t intr_status) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _isisc_intr_status_clear(dev_id, intr_status); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Set link interrupt mask on particular port. - * @param[in] dev_id device id - * @param[in] port_id port id - * @param[in] intr_mask_flag interrupt mask - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -isisc_intr_port_link_mask_set(a_uint32_t dev_id, a_uint32_t port_id, a_uint32_t intr_mask_flag) -{ - sw_error_t rv; - HSL_API_LOCK; - rv = _isisc_port_link_intr_mask_set(dev_id, port_id, intr_mask_flag); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Get link interrupt mask on particular port. - * @param[in] dev_id device id - * @param[in] port_id port id - * @param[out] intr_mask_flag interrupt mask - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -isisc_intr_port_link_mask_get(a_uint32_t dev_id, a_uint32_t port_id, a_uint32_t * intr_mask_flag) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _isisc_port_link_intr_mask_get(dev_id, port_id, intr_mask_flag); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Get link interrupt status on particular port. - * @param[in] dev_id device id - * @param[in] port_id port id - * @param[out] intr_mask_flag interrupt mask - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -isisc_intr_port_link_status_get(a_uint32_t dev_id, a_uint32_t port_id, a_uint32_t * intr_mask_flag) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _isisc_port_link_intr_status_get(dev_id, port_id, intr_mask_flag); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Set mac link change interrupt mask on particular port. - * @param[in] dev_id device id - * @param[in] port_id port id - * @param[in] enable ports intr mask enabled - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -isisc_intr_mask_mac_linkchg_set(a_uint32_t dev_id, a_uint32_t port_id, a_bool_t enable) -{ - sw_error_t rv; - FAL_API_LOCK; - rv = _isisc_intr_mask_mac_linkchg_set(dev_id, port_id, enable); - FAL_API_UNLOCK; - return rv; -} - -/** - * @brief Get mac link change interrupt mask on particular port. - * @param[in] dev_id device id - * @param[in] port_id port id - * @param[out] port interrupt mask or not - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -isisc_intr_mask_mac_linkchg_get(a_uint32_t dev_id, a_uint32_t port_id, a_bool_t * enable) -{ - sw_error_t rv; - - FAL_API_LOCK; - rv = _isisc_intr_mask_mac_linkchg_get(dev_id, port_id, enable); - FAL_API_UNLOCK; - return rv; -} - -/** - * @brief Get link change interrupt status for all ports. - * @param[in] dev_id device id - * @param[in] port_id port id - * @param[out] ports bitmap which generates interrupt - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -isisc_intr_status_mac_linkchg_get(a_uint32_t dev_id, fal_pbmp_t* port_bitmap) -{ - sw_error_t rv; - - FAL_API_LOCK; - rv = _isisc_intr_status_mac_linkchg_get(dev_id, port_bitmap); - FAL_API_UNLOCK; - return rv; -} - -/** - * @brief Set cpu vid enable status on a particular device. - * @param[in] dev_id device id - * @param[in] enable A_TRUE or A_FALSE - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -isisc_cpu_vid_en_set(a_uint32_t dev_id, a_bool_t enable) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _isisc_cpu_vid_en_set(dev_id, enable); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Get cpu vid enable status on a particular device. - * @param[in] dev_id device id - * @param[in] enable A_TRUE or A_FALSE - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -isisc_cpu_vid_en_get(a_uint32_t dev_id, a_bool_t * enable) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _isisc_cpu_vid_en_get(dev_id, enable); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Set RM_RTD_PPPOE_EN status on a particular device. - * @param[in] dev_id device id - * @param[in] enable A_TRUE or A_FALSE - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -isisc_rtd_pppoe_en_set(a_uint32_t dev_id, a_bool_t enable) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _isisc_rtd_pppoe_en_set(dev_id, enable); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Get RM_RTD_PPPOE_EN status on a particular device. - * @param[in] dev_id device id - * @param[in] enable A_TRUE or A_FALSE - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -isisc_rtd_pppoe_en_get(a_uint32_t dev_id, a_bool_t * enable) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _isisc_rtd_pppoe_en_get(dev_id, enable); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Clear link change interrupt status for all ports. - * @param[in] dev_id device id - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -isisc_intr_status_mac_linkchg_clear(a_uint32_t dev_id) -{ - sw_error_t rv; - - FAL_API_LOCK; - rv = _isisc_intr_status_mac_linkchg_clear(dev_id); - FAL_API_UNLOCK; - return rv; -} -#endif - -sw_error_t -isisc_misc_init(a_uint32_t dev_id) -{ - HSL_DEV_ID_CHECK(dev_id); - -#ifndef HSL_STANDALONG - { - hsl_api_t *p_api; - - SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id)); - - p_api->frame_max_size_set = isisc_frame_max_size_set; - p_api->frame_max_size_get = isisc_frame_max_size_get; - p_api->port_unk_uc_filter_set = isisc_port_unk_uc_filter_set; - p_api->port_unk_mc_filter_set = isisc_port_unk_mc_filter_set; - p_api->port_bc_filter_set = isisc_port_bc_filter_set; - p_api->cpu_port_status_set = isisc_cpu_port_status_set; -#ifndef IN_MISC_MINI - p_api->port_unk_uc_filter_get = isisc_port_unk_uc_filter_get; - p_api->port_unk_mc_filter_get = isisc_port_unk_mc_filter_get; - p_api->port_bc_filter_get = isisc_port_bc_filter_get; - p_api->cpu_port_status_get = isisc_cpu_port_status_get; - p_api->pppoe_cmd_set = isisc_pppoe_cmd_set; - p_api->pppoe_cmd_get = isisc_pppoe_cmd_get; - p_api->pppoe_status_set = isisc_pppoe_status_set; - p_api->pppoe_status_get = isisc_pppoe_status_get; - p_api->port_dhcp_set = isisc_port_dhcp_set; - p_api->port_dhcp_get = isisc_port_dhcp_get; - p_api->arp_cmd_set = isisc_arp_cmd_set; - p_api->arp_cmd_get = isisc_arp_cmd_get; -#endif - p_api->eapol_cmd_set = isisc_eapol_cmd_set; -#ifndef IN_MISC_MINI - p_api->eapol_cmd_get = isisc_eapol_cmd_get; - p_api->pppoe_session_table_add = isisc_pppoe_session_table_add; - p_api->pppoe_session_table_del = isisc_pppoe_session_table_del; - p_api->pppoe_session_table_get = isisc_pppoe_session_table_get; - p_api->pppoe_session_id_set = isisc_pppoe_session_id_set; - p_api->pppoe_session_id_get = isisc_pppoe_session_id_get; -#endif - p_api->eapol_status_set = isisc_eapol_status_set; -#ifndef IN_MISC_MINI - p_api->eapol_status_get = isisc_eapol_status_get; - p_api->ripv1_status_set = isisc_ripv1_status_set; - p_api->ripv1_status_get = isisc_ripv1_status_get; - p_api->port_arp_req_status_set = isisc_port_arp_req_status_set; - p_api->port_arp_req_status_get = isisc_port_arp_req_status_get; - p_api->port_arp_ack_status_set = isisc_port_arp_ack_status_set; - p_api->port_arp_ack_status_get = isisc_port_arp_ack_status_get; - p_api->intr_mask_set = isisc_intr_mask_set; - p_api->intr_mask_get = isisc_intr_mask_get; - p_api->intr_status_get = isisc_intr_status_get; - p_api->intr_status_clear = isisc_intr_status_clear; - p_api->intr_port_link_mask_set = isisc_intr_port_link_mask_set; - p_api->intr_port_link_mask_get = isisc_intr_port_link_mask_get; - p_api->intr_port_link_status_get = isisc_intr_port_link_status_get; - p_api->intr_mask_mac_linkchg_set = isisc_intr_mask_mac_linkchg_set; - p_api->intr_mask_mac_linkchg_get = isisc_intr_mask_mac_linkchg_get; - p_api->intr_status_mac_linkchg_get = isisc_intr_status_mac_linkchg_get; - p_api->cpu_vid_en_set = isisc_cpu_vid_en_set; - p_api->cpu_vid_en_get = isisc_cpu_vid_en_get; - p_api->rtd_pppoe_en_set = isisc_rtd_pppoe_en_set; - p_api->rtd_pppoe_en_get = isisc_rtd_pppoe_en_get; - p_api->intr_status_mac_linkchg_clear = isisc_intr_status_mac_linkchg_clear; -#endif - - } -#endif - - return SW_OK; -} - -/** - * @} - */ diff --git a/feeds/ipq807x/qca-ssdk/src/src/hsl/isisc/isisc_multicast_acl.c b/feeds/ipq807x/qca-ssdk/src/src/hsl/isisc/isisc_multicast_acl.c deleted file mode 100755 index bd2c91c9e..000000000 --- a/feeds/ipq807x/qca-ssdk/src/src/hsl/isisc/isisc_multicast_acl.c +++ /dev/null @@ -1,1024 +0,0 @@ -/* - * Copyright (c) 2012, 2016, The Linux Foundation. All rights reserved. - * Permission to use, copy, modify, and/or distribute this software for - * any purpose with or without fee is hereby granted, provided that the - * above copyright notice and this permission notice appear in all copies. - * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES - * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR - * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES - * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN - * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT - * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. - */ - - - -#include "fal_nat.h" -#include "fal_ip.h" -#include "hsl_api.h" -#include "sw.h" -#include "hsl.h" -#include "hsl_dev.h" -#include "hsl_port_prop.h" -#include "isisc_igmp.h" -#include "isisc_reg.h" -#include "isisc_acl.h" -#include "fal_multi.h" -#include "sal/os/aos_lock.h" - -#if 0 -/** - * I/F prototype for complete igmpv3 & mldv2 support - */ - -/*supports 32 entries*/ -#define FAL_IGMP_SG_ENTRY_MAX 32 - -typedef enum -{ - FAL_ADDR_IPV4 = 0, - FAL_ADDR_IPV6 -} fal_addr_type_t; - -typedef struct -{ - fal_addr_type_t type; - union - { - fal_ip4_addr_t ip4_addr; - fal_ip6_addr_t ip6_addr; - } u; -} fal_igmp_sg_addr_t; - -typedef struct -{ - fal_igmp_sg_addr_t source; - fal_igmp_sg_addr_t group; - fal_pbmp_t port_map; -} fal_igmp_sg_entry_t; - -/** - * @brief set PortMap of IGMP sg entry. - * search entry according to source/group address, - * update PortMap if SG entry is found, otherwise create a new sg entry. - * @param[in] dev_id device id - * @param[in-out] entry SG entry - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -isisc_igmp_sg_entry_set(a_uint32_t dev_id, fal_igmp_sg_entry_t * entry); - -/** - * @brief clear PortMap of IGMP sg entry. - * search entry according to source/group address, - * update PortMap if SG entry is found, delete the entry in case PortMap was 0. - * SW_NOT_FOUND will be returned in case search failed. - * @param[in] dev_id device id - * @param[in-out] entry SG entry - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -isisc_igmp_sg_entry_clear(a_uint32_t dev_id, fal_igmp_sg_entry_t * entry); - -#define MULTI_DEBUG_ -#ifdef MULTI_DEBUG_ -#define MULTI_DEBUG(x...) aos_printk(x) -#else -#define MULTI_DEBUG(x...) -#endif - -#define FAL_ACL_LIST_MULTICAST 55 -#define FAL_MULTICAST_PRI 5 - -#define MULT_ACTION_SET 1 -#define MULT_ACTION_CLEAR 1 - -static a_uint32_t rule_nr=1; - -typedef struct -{ - a_uint8_t index; //MAX is 32 - fal_igmp_sg_entry_t entry; //Stores the specific ACL rule info -} multi_acl_info_t; -#endif - -static a_uint32_t mul_rule_nr=1; - -void -isisc_multicast_init(a_uint32_t dev_id); - -HSL_LOCAL sw_error_t multi_portmap_aclreg_set(a_uint32_t dev_id, a_uint32_t pos, fal_igmp_sg_entry_t * entry); - -static multi_acl_info_t multi_acl_info[FAL_IGMP_SG_ENTRY_MAX]; -static multi_acl_info_t multi_acl_group[FAL_IGMP_SG_ENTRY_MAX]; - -static int ip6_addr_is_null(fal_ip6_addr_t *ip6) -{ - if (NULL == ip6) - { - aos_printk("Invalid ip6 address\n"); - return -1; - } - if(0 == ip6->ul[0] && 0 == ip6->ul[1] && 0 == ip6->ul[2] && 0 == ip6->ul[3]) - return 1; - else - return 0; -} -static int multi_source_is_null(fal_igmp_sg_addr_t *s) -{ - if (NULL == s) - { - aos_printk("Invalid source address\n"); - return -1; - } - if(0 == s->type && 0==s->u.ip4_addr) - return 1; - if(1 == s->type && 1 == ip6_addr_is_null(&(s->u.ip6_addr))) - return 1; - - return 0; -} - -HSL_LOCAL int iterate_multicast_acl_rule(a_uint32_t dev_id, int list_id, int start_n) -{ - a_uint32_t rule_id; - sw_error_t ret; - fal_acl_rule_t rule= {0}; - - if(start_n>=FAL_IGMP_SG_ENTRY_MAX || start_n < 0) - { - return -1; - } - - for(rule_id=0; rule_id=FAL_IGMP_SG_ENTRY_MAX) - { - return -1; - } - - multi_acl_info[rule_id+start_n].index = rule_id; // consider here... index is NOT related start_n - //MULTI_DEBUG("normal query1: rule dest_ip4_val=%x, src ip4=%x, dst_ip6=%x, ports=%x\n", - //rule.dest_ip4_val, rule.src_ip4_val, rule.dest_ip6_val.ul[0], rule.ports); - - if(rule.dest_ip4_val !=0 && ip6_addr_is_null(&rule.dest_ip6_val)) //only ip4 - { - multi_acl_info[rule_id+start_n].entry.group.type = FAL_ADDR_IPV4; - multi_acl_info[rule_id+start_n].entry.source.type = FAL_ADDR_IPV4; - multi_acl_info[rule_id+start_n].entry.group.u.ip4_addr = rule.dest_ip4_val; - multi_acl_info[rule_id+start_n].entry.source.u.ip4_addr = rule.src_ip4_val; - multi_acl_info[rule_id+start_n].entry.port_map= rule.ports; - } - else if(rule.dest_ip4_val ==0 && !ip6_addr_is_null(&rule.dest_ip6_val)) //only ip6 - { - multi_acl_info[rule_id+start_n].entry.group.type = FAL_ADDR_IPV6; - multi_acl_info[rule_id+start_n].entry.source.type = FAL_ADDR_IPV6; - memcpy(&(multi_acl_info[rule_id+start_n].entry.group.u.ip6_addr), &(rule.dest_ip6_val), sizeof(rule.dest_ip6_val)); - memcpy(&(multi_acl_info[rule_id+start_n].entry.source.u.ip6_addr), &(rule.src_ip6_val), sizeof(rule.src_ip6_val)); - multi_acl_info[rule_id+start_n].entry.port_map= rule.ports; - } - if (FAL_FIELD_FLG_TST(rule.field_flg, FAL_ACL_FIELD_MAC_VID)) - { - multi_acl_info[rule_id+start_n].entry.vlan_id = rule.vid_val; - } - else - { - multi_acl_info[rule_id+start_n].entry.vlan_id = 0xffff; - } - } - - return rule_id+start_n; -} -/* -** Iterate the total 32 multicast ACL entries. - After the function completes: - 1. Stores all multicast related ACL rules in multi_acl_info[32] - 2. return the number of multicast related ACL rules -*/ -HSL_LOCAL a_uint32_t isisc_multicast_acl_query(a_uint32_t dev_id) -{ - int start_n; - int total_n; - //a_uint32_t i; - - start_n = iterate_multicast_acl_rule(dev_id, FAL_ACL_LIST_MULTICAST, 0); - if(-1 == start_n) - aos_printk("ACL rule1 is FULL\n"); - total_n = iterate_multicast_acl_rule(dev_id, FAL_ACL_LIST_MULTICAST+1, start_n); - if(-1 == total_n) - aos_printk("ACL rule2 is FULL\n"); - - MULTI_DEBUG("KKK, the total ACL rule number is %d, (G,S) number=%d\n", total_n, start_n); - /* - for(i=0;i>6)&0x3) == 0x3) || (((msk_valid>>6)&0x3) == 0x2)) - { - rv = multi_portmap_aclreg_set(dev_id, i, entry); - break; - } - else if ((((msk_valid>>6)&0x3)) == 0x0 || (((msk_valid>>6)&0x3) == 0x1)) - { - rv = multi_portmap_aclreg_set(dev_id, i, entry); - continue; - } - else - { - aos_printk("The rule valid bit:6 7 is wrong!!!"); - break; - } - } - return rv; -} -HSL_LOCAL sw_error_t multi_portmap_aclreg_set(a_uint32_t dev_id, a_uint32_t pos, fal_igmp_sg_entry_t * entry) -{ - a_uint32_t i, base, addr; - sw_error_t rv; - a_uint32_t act[3]= {0}; - fal_pbmp_t pm; - - pm = entry->port_map; - - base = ISISC_FILTER_ACT_ADDR + (pos << 4); - for (i = 0; i < 3; i++) - { - addr = base + (i << 2); - HSL_REG_ENTRY_GEN_GET(rv, dev_id, addr, sizeof (a_uint32_t), - (a_uint8_t *) (&act[i]), - sizeof (a_uint32_t)); - //MULTI_DEBUG("2:Get register value 0x%x =%x\n", addr, act[i]); - SW_RTN_ON_ERROR(rv); - } - - act[1] &= ~(0x7<<29); // clear the high 3 bits - act[1] |= (pm&0x7)<<29; //the low 3 bits of pm means redirect port 0,1,2 - - /* New modification: update acl ACTION register from DENY to redirect */ - if (((act[2]>>6)&0x7) == 0x7) //DENY mode - { - if(pm) - { - act[2] &= ~(0x7<<6);//clear DENY bits - act[2] |= (0x1<<4); //DES_PORT_EN set 1, enable - } - } - else if (((act[2]>>4)&0x1) == 0x1) //redirect mode - { - if(pm==0) - { - act[2] &= ~(0x1<<4);//clear redirect bits - act[2] |= (0x7<<6); //set to DENY - } - } - - act[2] &= ~0xf; //clear the low 4 bits of port 3,4,5,6 - act[2] |= (pm>>3)&0xf; - - addr = base + (1<<2); - HSL_REG_ENTRY_GEN_SET(rv, dev_id, addr, sizeof (a_uint32_t), - (a_uint8_t *) (&act[1]), sizeof (a_uint32_t)); - addr = base + (2<<2); - HSL_REG_ENTRY_GEN_SET(rv, dev_id, addr, sizeof (a_uint32_t), - (a_uint8_t *) (&act[2]), sizeof (a_uint32_t)); - MULTI_DEBUG("pos=%d, before sync portmap, the new act=%x %x\n", pos, act[1],act[2]); - if((rv = isisc_acl_rule_sync_multi_portmap(dev_id, pos, act)) < 0) - aos_printk("Sync multicast portmap error\n"); - return rv; -} - -HSL_LOCAL int multi_get_dp(a_uint32_t dev_id) -{ - a_uint32_t addr; - sw_error_t rv; - int val=0; - - addr = 0x624;//GLOBAL_FW_CTRL1 - HSL_REG_ENTRY_GEN_GET(rv, dev_id, addr, sizeof (a_uint32_t), - (a_uint8_t *) (&val), - sizeof (a_uint32_t)); - if (rv != SW_OK) - aos_printk("Get entry value error\n"); - - val = (val>>24)&0x7f; //30:24, IGMP_JOIN_LEAVE_DP - - return val; -} -static int old_bind_p=-1; -HSL_LOCAL int multi_acl_bind(a_uint32_t dev_id) -{ - int bind_p; - int i; - - bind_p = multi_get_dp(dev_id); - if(bind_p == old_bind_p) - return 0; - old_bind_p = bind_p; - - for(i=0; i<7; i++) - { - isisc_acl_list_unbind(dev_id, FAL_ACL_LIST_MULTICAST, FAL_ACL_DIREC_IN, FAL_ACL_BIND_PORT, i); - isisc_acl_list_unbind(dev_id, FAL_ACL_LIST_MULTICAST+1, FAL_ACL_DIREC_IN, FAL_ACL_BIND_PORT, i); - } - - if(bind_p==0) - { - for(i=0; i<7; i++) - { - isisc_acl_list_bind(dev_id, FAL_ACL_LIST_MULTICAST, FAL_ACL_DIREC_IN, FAL_ACL_BIND_PORT, i); - isisc_acl_list_bind(dev_id, FAL_ACL_LIST_MULTICAST+1, FAL_ACL_DIREC_IN, FAL_ACL_BIND_PORT, i); - } - } - else - { - for(i=0; i<7; i++) - if((bind_p>>i) &0x1) - { - isisc_acl_list_bind(dev_id, FAL_ACL_LIST_MULTICAST, FAL_ACL_DIREC_IN, FAL_ACL_BIND_PORT, i); - isisc_acl_list_bind(dev_id, FAL_ACL_LIST_MULTICAST+1, FAL_ACL_DIREC_IN, FAL_ACL_BIND_PORT, i); - } - else - continue; - } - return 0; -} -/* -** Only update the related portmap from the privious input. -*/ -HSL_LOCAL sw_error_t isisc_multicast_acl_update(a_uint32_t dev_id, int list_id, int acl_index, fal_igmp_sg_entry_t * entry, int action) -{ - a_uint32_t rule_pos; - sw_error_t rv; - - if(acl_index<0) - { - aos_printk("Something is wrong...\n"); - return SW_FAIL; - } - - rule_pos = isisc_acl_rule_get_offset(dev_id, list_id, multi_acl_group[acl_index].index); - if(MULT_ACTION_SET == action) - { - multi_acl_group[acl_index].entry.port_map |= entry->port_map; - if(entry->port_map == 0) - { - multi_acl_group[acl_index].entry.port_map = 0; - } - } - else if(MULT_ACTION_CLEAR == action) - multi_acl_group[acl_index].entry.port_map &= ~(entry->port_map); - - rv = multi_portmap_aclreg_set_all(dev_id, rule_pos, &multi_acl_group[acl_index].entry); - - multi_acl_bind(dev_id); //Here need extra bind since IGMP join/leave would happen - return rv; -} - -HSL_LOCAL sw_error_t isisc_multicast_acl_del(a_uint32_t dev_id, int list_id, int index) -{ - sw_error_t rv; - int rule_id; - - rule_id = multi_acl_group[index].index; - - rv = isisc_acl_rule_delete(dev_id, list_id, rule_id, 1); - multi_acl_bind(dev_id); //Here need extra bind since IGMP join/leave would happen - return rv; -} - -/* -** Add new acl rule with parameters: DIP, SIP, redirect port. -*/ -HSL_LOCAL sw_error_t isisc_multicast_acl_add(a_uint32_t dev_id, int list_id, fal_igmp_sg_entry_t * entry) -{ - sw_error_t val; - a_uint32_t pos; - fal_acl_rule_t acl= {0}; - - /* IPv4 multicast */ - if( entry->group.type == FAL_ADDR_IPV4 ) - { - MULTI_DEBUG("KKK1, group[%d][%x], source[%d][%x]\n",entry->group.type, - entry->group.u.ip4_addr, entry->source.type, entry->source.u.ip4_addr); - - acl.rule_type = FAL_ACL_RULE_IP4; - - if(entry->group.u.ip4_addr!= 0) - { - acl.dest_ip4_val = entry->group.u.ip4_addr; - acl.dest_ip4_mask = 0xffffffff;//e->ip.dmsk.s_addr; - FAL_FIELD_FLG_SET(acl.field_flg, FAL_ACL_FIELD_IP4_DIP); - } - if(entry->source.u.ip4_addr!= 0) - { - acl.src_ip4_val = entry->source.u.ip4_addr; - acl.src_ip4_mask = 0xffffffff;//e->ip.smsk.s_addr; - FAL_FIELD_FLG_SET(acl.field_flg, FAL_ACL_FIELD_IP4_SIP); - } - if( entry->port_map==0 ) - FAL_ACTION_FLG_SET ( acl.action_flg, FAL_ACL_ACTION_DENY); - else - //FAL_FIELD_FLG_SET(acl.field_flg, FAL_ACL_FIELD_INVERSE_ALL); - FAL_ACTION_FLG_SET ( acl.action_flg, FAL_ACL_ACTION_PERMIT ); - - /* Be careful, _isisc_acl_action_parse() will block FAL_ACL_ACTION_DENY action, So we change it. */ - if( entry->port_map ) - { - FAL_ACTION_FLG_SET(acl.action_flg, FAL_ACL_ACTION_REDPT); - acl.ports = entry->port_map; - } - } - else if( entry->group.type == FAL_ADDR_IPV6 ) - { - MULTI_DEBUG("KKK2, group[%d][%x], source[%d][%x], pm=%x\n",entry->group.type, - entry->group.u.ip6_addr.ul[0], entry->source.type, entry->source.u.ip6_addr.ul[0], entry->port_map); - - acl.rule_type = FAL_ACL_RULE_IP6; - - if(!ip6_addr_is_null(&(entry->group.u.ip6_addr))) - { - memcpy(&acl.dest_ip6_val, &(entry->group.u.ip6_addr), sizeof(entry->group.u.ip6_addr)); - acl.dest_ip6_mask.ul[0] = 0xffffffff; - acl.dest_ip6_mask.ul[1] = 0xffffffff; - acl.dest_ip6_mask.ul[2] = 0xffffffff; - acl.dest_ip6_mask.ul[3] = 0xffffffff; - FAL_FIELD_FLG_SET(acl.field_flg, FAL_ACL_FIELD_IP6_DIP); - } - if(!ip6_addr_is_null(&(entry->source.u.ip6_addr))) - { - memcpy(&acl.src_ip6_val, &(entry->source.u.ip6_addr), sizeof(entry->source.u.ip6_addr)); - acl.src_ip6_mask.ul[0] = 0xffffffff; - acl.src_ip6_mask.ul[1] = 0xffffffff; - acl.src_ip6_mask.ul[2] = 0xffffffff; - acl.src_ip6_mask.ul[3] = 0xffffffff; - FAL_FIELD_FLG_SET(acl.field_flg, FAL_ACL_FIELD_IP6_SIP); - } - - if( entry->port_map==0 ) - FAL_ACTION_FLG_SET ( acl.action_flg, FAL_ACL_ACTION_DENY); - else - //FAL_FIELD_FLG_SET(acl.field_flg, FAL_ACL_FIELD_INVERSE_ALL); - FAL_ACTION_FLG_SET ( acl.action_flg, FAL_ACL_ACTION_PERMIT ); - - /* Be careful, _isisc_acl_action_parse() will block FAL_ACL_ACTION_DENY action, So we change it. */ - if( entry->port_map ) - { - FAL_ACTION_FLG_SET(acl.action_flg, FAL_ACL_ACTION_REDPT); - acl.ports = entry->port_map; - } - } - - if (entry->vlan_id < 4096) - { - FAL_FIELD_FLG_SET(acl.field_flg, FAL_ACL_FIELD_MAC_VID); - acl.vid_val = entry->vlan_id; - acl.vid_op = FAL_ACL_FIELD_MASK; - acl.vid_mask = 0xfff; - } - - pos = isisc_multicast_acl_total_n(dev_id, list_id); - - MULTI_DEBUG("In isisc_multicast_acl_add, list_id=%d, rule_id=%d\n", list_id, pos); - val = isisc_acl_rule_add(dev_id, list_id, pos, mul_rule_nr, &acl); - - multi_acl_bind(dev_id); - - return val; -} - - -HSL_LOCAL int iterate_multicast_acl_group(a_uint32_t number, fal_igmp_sg_entry_t * entry) -{ - int count=0; - int i; - - if (number == 0) - return 0; //no any ACL rules based the query - - for(i=0; igroup.type, entry->group.u.ip6_addr.ul[0], entry->port_map);*/ - - if(0 == memcmp(&(multi_acl_info[i].entry.group), &(entry->group), sizeof(entry->group))) - { - memcpy(&multi_acl_group[count], &multi_acl_info[i], sizeof(multi_acl_info[i])); - count++;//return the real number of multi_acl_group[] - MULTI_DEBUG("in iterate_multicast_acl_group, count=%d, i=%d\n", count, i); - } - } - - return count; -} - -HSL_LOCAL int mult_acl_has_entry(fal_igmp_sg_addr_t * group, fal_igmp_sg_addr_t *source) -{ - int rule_id; - int ret = 0; -#if 0 - if(source != NULL) - { - MULTI_DEBUG("new group[%d]= %x %x %x %x, new source[%d]=%x %x %x %x\n", - group->type, group->u.ip6_addr.ul[0], group->u.ip6_addr.ul[1], group->u.ip6_addr.ul[2], group->u.ip6_addr.ul[3], - source->type, source->u.ip6_addr.ul[0], source->u.ip6_addr.ul[1], source->u.ip6_addr.ul[2], source->u.ip6_addr.ul[3]); - - MULTI_DEBUG("old group[%d]= %x %x %x %x, old source[%d]=%x %x %x %x\n", - multi_acl_group[0].entry.group.type, multi_acl_group[0].entry.group.u.ip6_addr.ul[0], - multi_acl_group[0].entry.group.u.ip6_addr.ul[1], multi_acl_group[0].entry.group.u.ip6_addr.ul[2], multi_acl_group[0].entry.group.u.ip6_addr.ul[3], - multi_acl_group[0].entry.source.type, multi_acl_group[0].entry.source.u.ip6_addr.ul[0], - multi_acl_group[0].entry.source.u.ip6_addr.ul[1], multi_acl_group[0].entry.source.u.ip6_addr.ul[2], multi_acl_group[0].entry.source.u.ip6_addr.ul[3]); - } -#endif - if(source == NULL) - { - for(rule_id=0; rule_idport_map, g_source->source.u.ip4_addr, g_source->group.u.ip4_addr, - g_star->port_map, g_star->source.u.ip4_addr,g_star->group.u.ip4_addr);*/ - - if(multi_source_is_null(&(g_star->source))) - { - if((g_source->port_map|g_star->port_map) == g_star->port_map) - { - return 0; - } - } - - return 1; -} - - -HSL_LOCAL int portmap_clear_type(int count, int index, fal_pbmp_t portmap) -{ - if(count>=0 && index0; this means there're (G,*) and (G,S) - { - //if the new clear portmap will cause (G,S)=(G,*), Delete the (G,S) - if((multi_acl_group[index].entry.port_map & (~portmap)) == multi_acl_group[count].entry.port_map) - return 1; //delete - - - //The following means there must be at least one bit clear wrong. Clear the (G,*) portmap. - if( ((multi_acl_group[index].entry.port_map & (~portmap)) & (multi_acl_group[count].entry.port_map)) - != (multi_acl_group[count].entry.port_map)) - return 0; - - return 2; //Normal update - } - return 0; -} -sw_error_t isisc_igmp_sg_entry_set(a_uint32_t dev_id, fal_igmp_sg_entry_t * entry) -{ - int number, count; - int new_index=0; - sw_error_t rv; - int action = MULT_ACTION_SET; - int i=0; - - HSL_API_LOCK; - isisc_multicast_init(dev_id); - aos_mem_zero(multi_acl_info, FAL_IGMP_SG_ENTRY_MAX * sizeof (multi_acl_info_t)); - aos_mem_zero(multi_acl_group, FAL_IGMP_SG_ENTRY_MAX * sizeof (multi_acl_info_t)); - MULTI_DEBUG("Before query: group=%x, source=%x, portmap=%x\n", entry->group.u.ip4_addr, entry->source.u.ip4_addr, entry->port_map); - //number is the total multicast ACL rules amount, stores in multi_acl_info[]; - number = isisc_multicast_acl_query(dev_id); - if(number > FAL_IGMP_SG_ENTRY_MAX) - return SW_FAIL; - //count the total specific multicast group ACL rules, stores in multi_acl_group[]; count <=number - count = iterate_multicast_acl_group(number, entry); - //new_index-1 is the found entry index in multi_acl_group[], the real index is [new_index-1], 0 means no entry - new_index = mult_acl_has_entry(&entry->group, &entry->source); - - MULTI_DEBUG("Start entry set: number=%d, count=%d, new_index=%d, pm=%x\n", number, count, new_index, entry->port_map); - if( 0==multi_source_is_null(&entry->source) ) // new entry is (G, S) - { - MULTI_DEBUG("the new entry is (G,S)\n"); - if(count>0 && 0 == portmap_valid(entry, &(multi_acl_group[count-1].entry))) //specfic group entry exist,(G,S) or (G,*) - { - //return SW_NO_CHANGE; // The new portmap is Not valid - MULTI_DEBUG("KKK, modified 1 !!!\n"); - } - - if(0 == new_index) //new entry, need add - { -#if 0 - /*The method: - 1. predict if the portmap should be modified. - 2. add new acl rule with new portmap value. - */ - if((tmp_index = mult_acl_has_entry(&entry->group, NULL))>0) // (G, *) entry exist - { - /*Here the update should new (G, S) OR orignal (G,*) portmap, - be careful, entry's portmap value will be modified, so I use tmp_entry. - */ - memcpy(tmp_entry, entry, sizeof(fal_igmp_sg_entry_t)); - MULTI_DEBUG("Here, (G,*) exist! tmp_index=%d\n", tmp_index); - sw_multicast_acl_update(FAL_ACL_LIST_MULTICAST+1, tmp_index-1, tmp_entry, action); - - isisc_multicast_acl_add(FAL_ACL_LIST_MULTICAST, tmp_entry); - return SW_OK; - } -#endif - isisc_multicast_acl_add(dev_id, FAL_ACL_LIST_MULTICAST, entry); - MULTI_DEBUG("Here, need add (G, S), portmap=%x\n", entry->port_map); - return SW_OK; - } - else - { - //Here update Just: the old exist entry portmap OR the new entry portmap - isisc_multicast_acl_update(dev_id, FAL_ACL_LIST_MULTICAST, new_index-1, entry, action); - return SW_OK; - } - } //end of memcmp - else // new entry is (G, *) - { - if(0 == new_index) //new entry, need add - { - isisc_multicast_acl_add(dev_id, FAL_ACL_LIST_MULTICAST+1, entry); - rv = SW_OK; - } - else if(new_index > 0) // (G, *) entry exist? - { - //Update exist (G, *) portmap with new portmap - MULTI_DEBUG("(G,*) exist, before update, new_index=%d\n", new_index ); - isisc_multicast_acl_update(dev_id, FAL_ACL_LIST_MULTICAST+1, new_index-1, entry, action); - rv = SW_OK; - } - - if(new_index>0&&count>1) //(G,S*) and (G,*) exist, new entry is (G,*) - { - for(i=count-2; i>=0&&i0) //only exist (G,S*) orignally - { - for(i=count-1; i>=0&&iport_map); - isisc_multicast_acl_del(dev_id, FAL_ACL_LIST_MULTICAST, i); - rv = SW_NO_MORE; - } - else - { - MULTI_DEBUG("2:Start update all (G,S),i=%d, portmap=%x\n", i, entry->port_map); - //Update all (G,S) entry portmap with new(G, *) portmap - isisc_multicast_acl_update(dev_id, FAL_ACL_LIST_MULTICAST, i, entry, action); - rv = SW_OK; - } - } - } - } - HSL_API_UNLOCK; - return rv; -} - -sw_error_t isisc_igmp_sg_entry_clear(a_uint32_t dev_id, fal_igmp_sg_entry_t * entry) -{ - a_uint32_t number, count; - int new_index=0; - sw_error_t rv = SW_OK; - int action= MULT_ACTION_CLEAR; - int i=0; - int pm_type; - - HSL_API_LOCK; - isisc_multicast_init(dev_id); - aos_mem_zero(multi_acl_info, FAL_IGMP_SG_ENTRY_MAX * sizeof (multi_acl_info_t)); - aos_mem_zero(multi_acl_group, FAL_IGMP_SG_ENTRY_MAX * sizeof (multi_acl_info_t)); - //number is the total multicast ACL rules amount, stores in multi_acl_info[]; - number = isisc_multicast_acl_query(dev_id); - if(number > FAL_IGMP_SG_ENTRY_MAX) - return SW_FAIL; - //count the total specific multicast group ACL rules, stores in multi_acl_group[]; count <=number - count = iterate_multicast_acl_group(number, entry); - if(count == 0) - return SW_OK; - - //new_index-1 is the found entry index in multi_acl_group[] - new_index = mult_acl_has_entry(&entry->group, &entry->source); - - MULTI_DEBUG("Start entry clear: number=%d, count=%d, new_index=%d\n", number, count, new_index); - if(0 == new_index || new_index > FAL_IGMP_SG_ENTRY_MAX || count > FAL_IGMP_SG_ENTRY_MAX) //new entry, the user command is wrong - { - return SW_NO_SUCH; - } - - if( 0==multi_source_is_null(&entry->source) ) // new entry is (G, S) - { - if (portmap_null(new_index-1, entry->port_map)) - { - MULTI_DEBUG("KKK entry clear, new(G,S), with null portmap. \n"); - isisc_multicast_acl_del(dev_id, FAL_ACL_LIST_MULTICAST, new_index-1); - return SW_OK; - } - else - { - MULTI_DEBUG("KKK entry clear, new(G,S), with NOT null portmap. \n"); - /* If (G,*) doesn't exist, [count-1] is the last specfic group, maybe(G,*) */ - if(0 == multi_source_is_null(&(multi_acl_group[count-1].entry.source))) - { - isisc_multicast_acl_update(dev_id, FAL_ACL_LIST_MULTICAST, new_index-1, entry, action); - } - else //(G,*) exist - { - pm_type = portmap_clear_type(count-1, new_index-1, entry->port_map); - if(pm_type == 0) - return SW_NO_CHANGE; - else if(pm_type == 1) - { - isisc_multicast_acl_del(dev_id, FAL_ACL_LIST_MULTICAST, new_index-1); - return SW_OK; - } - else - { - //normal update; consider here...wangson - isisc_multicast_acl_update(dev_id, FAL_ACL_LIST_MULTICAST, new_index-1, entry, action); - } - } - } - return SW_OK; - } - else //clear entry is (G,*) - { - MULTI_DEBUG("Here, new_index[%d]>=0, new portmap to clear is %x\n", new_index, entry->port_map); - if (portmap_null(new_index-1, entry->port_map)) - { - isisc_multicast_acl_del(dev_id, FAL_ACL_LIST_MULTICAST+1, new_index-1); - rv = SW_OK; - } - else - { - MULTI_DEBUG("Update (G,*)!, new_index=%d, pm=%x\n", new_index, entry->port_map); - isisc_multicast_acl_update(dev_id, FAL_ACL_LIST_MULTICAST+1, new_index-1, entry, action); - } - MULTI_DEBUG("KKK, ready clear (G, S*), count=%d\n", count); -#if 0 - if(count>1) // (G, S*) entry exist, if count=1 here, only exist(G,*)entry - { - //count must >=2 - for(i=count-2; i>=0; i--) - { - if(portmap_null(i, entry->port_map)) - { - MULTI_DEBUG("portmap_null, i=%d\n", i); - isisc_multicast_acl_del(FAL_ACL_LIST_MULTICAST, i); - rv = SW_NO_MORE; - } - else - { - //Update all (G,S) entry portmap with new(G, *) portmap - isisc_multicast_acl_update(FAL_ACL_LIST_MULTICAST, i, entry, action); - rv = SW_OK; - } - } - } -#else - if(count>1) // (G, S*) entry exist, if count=1 here, only exist(G,*)entry - { - //count must >=2 - for(i=count-2; i>=0&&iport_map))) == - multi_acl_group[i].entry.port_map) - isisc_multicast_acl_del(dev_id, FAL_ACL_LIST_MULTICAST, i); - else - //Update all (G,S) entry portmap with new(G, *) portmap - isisc_multicast_acl_update(dev_id, FAL_ACL_LIST_MULTICAST, i, entry, action); - rv = SW_OK; - } - } -#endif - } - HSL_API_UNLOCK; - return rv; -} - -static void -print_ip4addr(char * param_name, a_uint32_t * buf, - a_uint32_t size) -{ - a_uint32_t i; - fal_ip4_addr_t ip4; - - ip4 = *((fal_ip4_addr_t *) buf); - aos_printk("%s", param_name); - for (i = 0; i < 3; i++) - { - aos_printk("%d.", (ip4 >> (24 - i * 8)) & 0xff); - } - aos_printk("%d", (ip4 & 0xff)); -} -static void -print_ip6addr(char * param_name, a_uint32_t * buf, - a_uint32_t size) -{ - a_uint32_t i; - fal_ip6_addr_t ip6; - - ip6 = *(fal_ip6_addr_t *) buf; - aos_printk("%s", param_name); - for (i = 0; i < 3; i++) - { - aos_printk("%x:%x:", (ip6.ul[i] >> 16) & 0xffff, ip6.ul[i] & 0xffff); - } - aos_printk("%x:%x", (ip6.ul[3] >> 16) & 0xffff, ip6.ul[3] & 0xffff); -} -sw_error_t isisc_igmp_sg_entry_show(a_uint32_t dev_id) -{ - a_uint32_t number; - int i; - - HSL_API_LOCK; - isisc_multicast_init(dev_id); - aos_mem_zero(multi_acl_info, FAL_IGMP_SG_ENTRY_MAX * sizeof (multi_acl_info_t)); - aos_mem_zero(multi_acl_group, FAL_IGMP_SG_ENTRY_MAX * sizeof (multi_acl_info_t)); - //number is the total multicast ACL rules amount, stores in multi_acl_info[]; - number = isisc_multicast_acl_query(dev_id); - - for(i=0; i FAL_IGMP_SG_ENTRY_MAX) - { - HSL_API_UNLOCK; - return SW_FAIL; - } - info->cnt = number; - - for(i=0; iacl_info[i]), &(multi_acl_info[i]), sizeof(multi_acl_info_t)); - } - HSL_API_UNLOCK; - - return SW_OK; -} - diff --git a/feeds/ipq807x/qca-ssdk/src/src/hsl/isisc/isisc_nat.c b/feeds/ipq807x/qca-ssdk/src/src/hsl/isisc/isisc_nat.c deleted file mode 100755 index 830976128..000000000 --- a/feeds/ipq807x/qca-ssdk/src/src/hsl/isisc/isisc_nat.c +++ /dev/null @@ -1,2468 +0,0 @@ -/* - * Copyright (c) 2012, 2016, The Linux Foundation. All rights reserved. - * Permission to use, copy, modify, and/or distribute this software for - * any purpose with or without fee is hereby granted, provided that the - * above copyright notice and this permission notice appear in all copies. - * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES - * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR - * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES - * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN - * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT - * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. - */ - - -/** - * @defgroup isisc_ip ISISC_NAT - * @{ - */ - -#include "sw.h" -#include "hsl.h" -#include "hsl_dev.h" -#include "hsl_port_prop.h" -#include "isisc_nat.h" -#include "isisc_reg.h" -#if defined(IN_NAT_HELPER) -#include "isisc_nat_helper.h" -#endif - -#define ISISC_HOST_ENTRY_DATA0_ADDR 0x0e80 -#define ISISC_HOST_ENTRY_DATA1_ADDR 0x0e84 -#define ISISC_HOST_ENTRY_DATA2_ADDR 0x0e88 -#define ISISC_HOST_ENTRY_DATA3_ADDR 0x0e8c -#define ISISC_HOST_ENTRY_DATA4_ADDR 0x0e90 -#define ISISC_HOST_ENTRY_DATA5_ADDR 0x0e94 -#define ISISC_HOST_ENTRY_DATA6_ADDR 0x0e98 -#define ISISC_HOST_ENTRY_DATA7_ADDR 0x0e58 - -#define ISISC_HOST_ENTRY_REG_NUM 8 - -#define ISISC_NAT_ENTRY_FLUSH 1 -#define ISISC_NAT_ENTRY_ADD 2 -#define ISISC_NAT_ENTRY_DEL 3 -#define ISISC_NAT_ENTRY_NEXT 4 -#define ISISC_NAT_ENTRY_SEARCH 5 - -#define ISISC_ENTRY_NAPT 0 -#define ISISC_ENTRY_NAT 2 -#define ISISC_ENTRY_ARP 3 - -#define ISISC_PUB_ADDR_NUM 16 -#define ISISC_PUB_ADDR_TBL0_ADDR 0x5aa00 -#define ISISC_PUB_ADDR_TBL1_ADDR 0x5aa04 -#define ISISC_PUB_ADDR_EDIT0_ADDR 0x02100 -#define ISISC_PUB_ADDR_EDIT1_ADDR 0x02104 -#define ISISC_PUB_ADDR_OFFLOAD_ADDR 0x2f000 -#define ISISC_PUB_ADDR_VALID_ADDR 0x2f040 - -#define ISISC_NAT_ENTRY_NUM 32 -#define ISISC_NAPT_ENTRY_NUM 1024 - -#define ISISC_NAT_COUTER_ADDR 0x2b000 - -#define ISISC_NAT_PORT_NUM 255 - -static a_uint32_t isisc_nat_snap[SW_MAX_NR_DEV] = { 0 }; -extern a_uint32_t isisc_nat_global_status; - -static sw_error_t -_isisc_nat_feature_check(a_uint32_t dev_id) -{ - sw_error_t rv; - a_uint32_t entry = 0; - - HSL_REG_FIELD_GET(rv, dev_id, MASK_CTL, 0, DEVICE_ID, - (a_uint8_t *) (&entry), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - - if (S17C_DEVICE_ID == entry) - { - return SW_OK; - } - else - { - return SW_NOT_SUPPORTED; - } -} - -static sw_error_t -_isisc_ip_prvaddr_sw_to_hw(a_uint32_t dev_id, fal_ip4_addr_t sw_addr, - a_uint32_t * hw_addr) -{ - /* - sw_error_t rv; - a_uint32_t data; - - HSL_REG_FIELD_GET(rv, dev_id, PRVIP_CTL, 0, BASEADDR_SEL, - (a_uint8_t *) (&data), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - - if (data) { - *hw_addr = (sw_addr & 0xff) | (((sw_addr >> 16) & 0xf) << 8); - } else { - *hw_addr = sw_addr & 0xfff; - } - */ - *hw_addr = sw_addr; - return SW_OK; -} - -static sw_error_t -_isisc_ip_prvaddr_hw_to_sw(a_uint32_t dev_id, a_uint32_t hw_addr, - fal_ip4_addr_t * sw_addr) -{ - /* - sw_error_t rv; - a_uint32_t data, addr; - - HSL_REG_FIELD_GET(rv, dev_id, PRVIP_CTL, 0, BASEADDR_SEL, - (a_uint8_t *) (&data), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - - HSL_REG_FIELD_GET(rv, dev_id, PRVIP_CTL, 0, IP4_BASEADDR, - (a_uint8_t *) (&addr), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - - if (data) { - *sw_addr = ((addr & 0xff) << 8) | (((addr >> 8) & 0xfff) << 8) - | (hw_addr & 0xff) | (((hw_addr >> 8) & 0xf) << 16); - } else { - *sw_addr = (addr << 12) | (hw_addr & 0xfff); - } - */ - *sw_addr = hw_addr; - - return SW_OK; -} - -static sw_error_t -_isisc_nat_counter_get(a_uint32_t dev_id, a_uint32_t cnt_id, - a_uint32_t counter[4]) -{ - sw_error_t rv; - a_uint32_t i, addr; - - addr = ISISC_NAT_COUTER_ADDR + (cnt_id << 4); - for (i = 0; i < 4; i++) - { - HSL_REG_ENTRY_GEN_GET(rv, dev_id, addr, sizeof (a_uint32_t), - (a_uint8_t *) (&(counter[i])), - sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - - addr += 4; - } - - return SW_OK; -} - -static sw_error_t -_isisc_nat_entry_commit(a_uint32_t dev_id, a_uint32_t entry_type, a_uint32_t op) -{ - a_uint32_t busy = 1, i = 0x100, entry = 0; - sw_error_t rv; - - while (busy && --i) - { - HSL_REG_ENTRY_GET(rv, dev_id, HOST_ENTRY7, 0, (a_uint8_t *) (&entry), - sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - SW_GET_FIELD_BY_REG(HOST_ENTRY7, TBL_BUSY, busy, entry); - } - - if (i == 0) - { - return SW_BUSY; - } - - SW_SET_REG_BY_FIELD(HOST_ENTRY7, TBL_BUSY, 1, entry); - SW_SET_REG_BY_FIELD(HOST_ENTRY7, TBL_SEL, entry_type, entry); - SW_SET_REG_BY_FIELD(HOST_ENTRY7, ENTRY_FUNC, op, entry); - - HSL_REG_ENTRY_SET(rv, dev_id, HOST_ENTRY7, 0, (a_uint8_t *) (&entry), - sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - - busy = 1; - i = 0x1000; - while (busy && --i) - { - HSL_REG_ENTRY_GET(rv, dev_id, HOST_ENTRY7, 0, (a_uint8_t *) (&entry), - sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - SW_GET_FIELD_BY_REG(HOST_ENTRY7, TBL_BUSY, busy, entry); -#if 1 - if(ISISC_NAT_ENTRY_SEARCH == op && busy) break; -#endif - } - - if (i == 0) - { - return SW_BUSY; - } - - /* hardware requirement, we should delay... */ - if ((ISISC_NAT_ENTRY_FLUSH == op) && (ISISC_ENTRY_NAPT == entry_type)) - { - aos_mdelay(10); - } - - /* hardware requirement, we should read again... */ - HSL_REG_ENTRY_GET(rv, dev_id, HOST_ENTRY7, 0, (a_uint8_t *) (&entry), - sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - - SW_GET_FIELD_BY_REG(HOST_ENTRY7, TBL_STAUS, busy, entry); - if (!busy) - { - if (ISISC_NAT_ENTRY_NEXT == op) - { - return SW_NO_MORE; - } - else if (ISISC_NAT_ENTRY_SEARCH == op) - { - return SW_NOT_FOUND; - } - else - { - return SW_FAIL; - } - } - - return SW_OK; -} - -static sw_error_t -_isisc_nat_sw_to_hw(a_uint32_t dev_id, fal_nat_entry_t * entry, a_uint32_t reg[]) -{ - sw_error_t rv; - a_uint32_t data; - - if (FAL_NAT_ENTRY_TRANS_IPADDR_INDEX & entry->flags) - { - return SW_BAD_PARAM; - } - - reg[0] = entry->trans_addr; - - if (FAL_NAT_ENTRY_PORT_CHECK & entry->flags) - { - SW_SET_REG_BY_FIELD(NAT_ENTRY3, PORT_EN, 1, reg[3]); - SW_SET_REG_BY_FIELD(NAT_ENTRY1, PORT_RANGE, entry->port_range, reg[1]); - if (ISISC_NAT_PORT_NUM < entry->port_range) - { - return SW_BAD_PARAM; - } - SW_SET_REG_BY_FIELD(NAT_ENTRY1, PORT_NUM, entry->port_num, reg[1]); - } - else - { - SW_SET_REG_BY_FIELD(NAT_ENTRY3, PORT_EN, 0, reg[3]); - } - - rv = _isisc_ip_prvaddr_sw_to_hw(dev_id, entry->src_addr, &data); - SW_RTN_ON_ERROR(rv); - - SW_SET_REG_BY_FIELD(NAT_ENTRY1, PRV_IPADDR0, data, reg[1]); - SW_SET_REG_BY_FIELD(NAT_ENTRY2, PRV_IPADDR1, (data >> 8), reg[2]); - - if (FAL_MAC_FRWRD == entry->action) - { - if (A_TRUE == entry->mirror_en) - { - SW_SET_REG_BY_FIELD(NAT_ENTRY2, ACTION, 0, reg[2]); - } - else - { - SW_SET_REG_BY_FIELD(NAT_ENTRY2, ACTION, 3, reg[2]); - } - } - else if (FAL_MAC_CPY_TO_CPU == entry->action) - { - SW_SET_REG_BY_FIELD(NAT_ENTRY2, ACTION, 2, reg[2]); - } - else if (FAL_MAC_RDT_TO_CPU == entry->action) - { - SW_SET_REG_BY_FIELD(NAT_ENTRY2, ACTION, 1, reg[2]); - } - else - { - return SW_NOT_SUPPORTED; - } - - if (A_TRUE == entry->counter_en) - { - SW_SET_REG_BY_FIELD(NAT_ENTRY2, CNT_EN, 1, reg[2]); - SW_SET_REG_BY_FIELD(NAT_ENTRY2, CNT_IDX, entry->counter_id, reg[2]); - } - - if (FAL_NAT_ENTRY_PROTOCOL_ANY & entry->flags) - { - data = 3; - } - else if ((FAL_NAT_ENTRY_PROTOCOL_TCP & entry->flags) - && (FAL_NAT_ENTRY_PROTOCOL_UDP & entry->flags)) - { - data = 2; - } - else if (FAL_NAT_ENTRY_PROTOCOL_TCP & entry->flags) - { - data = 0; - } - else if (FAL_NAT_ENTRY_PROTOCOL_UDP & entry->flags) - { - data = 1; - } - else - { - return SW_BAD_PARAM; - } - - SW_SET_REG_BY_FIELD(NAT_ENTRY3, PRO_TYP, data, reg[3]); - - SW_SET_REG_BY_FIELD(NAT_ENTRY2, HASH_KEY, entry->slct_idx, reg[2]); - - SW_SET_REG_BY_FIELD(NAT_ENTRY3, ENTRY_VALID, 1, reg[3]); - SW_SET_REG_BY_FIELD(HOST_ENTRY7, TBL_IDX, entry->entry_id, reg[7]); - return SW_OK; -} - -static sw_error_t -_isisc_nat_hw_to_sw(a_uint32_t dev_id, a_uint32_t reg[], fal_nat_entry_t * entry) -{ - sw_error_t rv; - a_uint32_t data, cnt[4] = {0}; - - entry->trans_addr = reg[0]; - - SW_GET_FIELD_BY_REG(NAT_ENTRY3, PORT_EN, data, reg[3]); - if (data) - { - entry->flags |= FAL_NAT_ENTRY_PORT_CHECK; - SW_GET_FIELD_BY_REG(NAT_ENTRY1, PORT_RANGE, data, reg[1]); - entry->port_range = data; - SW_GET_FIELD_BY_REG(NAT_ENTRY1, PORT_NUM, data, reg[1]); - entry->port_num = data; - } - - SW_GET_FIELD_BY_REG(NAT_ENTRY1, PRV_IPADDR0, data, reg[1]); - entry->src_addr = data; - SW_GET_FIELD_BY_REG(NAT_ENTRY2, PRV_IPADDR1, data, reg[2]); - data = (entry->src_addr & 0xff) | (data << 8); - - rv = _isisc_ip_prvaddr_hw_to_sw(dev_id, data, &(entry->src_addr)); - SW_RTN_ON_ERROR(rv); - - SW_GET_FIELD_BY_REG(NAT_ENTRY2, ACTION, data, reg[2]); - entry->action = FAL_MAC_FRWRD; - if (0 == data) - { - entry->mirror_en = A_TRUE; - } - else if (2 == data) - { - entry->action = FAL_MAC_CPY_TO_CPU; - } - else if (1 == data) - { - entry->action = FAL_MAC_RDT_TO_CPU; - } - - SW_GET_FIELD_BY_REG(NAT_ENTRY2, CNT_EN, data, reg[2]); - if (data) - { - entry->counter_en = A_TRUE; - SW_GET_FIELD_BY_REG(NAT_ENTRY2, CNT_IDX, entry->counter_id, reg[2]); - - rv = _isisc_nat_counter_get(dev_id, entry->counter_id, cnt); - SW_RTN_ON_ERROR(rv); - - entry->ingress_packet = cnt[0]; - entry->ingress_byte = cnt[1]; - entry->egress_packet = cnt[2]; - entry->egress_byte = cnt[3]; - } - else - { - entry->counter_en = A_FALSE; - } - - SW_GET_FIELD_BY_REG(NAT_ENTRY3, PRO_TYP, data, reg[3]); - if (3 == data) - { - entry->flags |= FAL_NAT_ENTRY_PROTOCOL_ANY; - } - else if (2 == data) - { - entry->flags |= FAL_NAT_ENTRY_PROTOCOL_TCP; - entry->flags |= FAL_NAT_ENTRY_PROTOCOL_UDP; - } - else if (1 == data) - { - entry->flags |= FAL_NAT_ENTRY_PROTOCOL_UDP; - } - else if (0 == data) - { - entry->flags |= FAL_NAT_ENTRY_PROTOCOL_TCP; - } - - SW_GET_FIELD_BY_REG(NAT_ENTRY2, HASH_KEY, data, reg[2]); - entry->slct_idx = data; - - return SW_OK; -} - -static sw_error_t -_isisc_napt_sw_to_hw(a_uint32_t dev_id, fal_napt_entry_t * entry, - a_uint32_t reg[]) -{ - sw_error_t rv; - a_uint32_t data; - - reg[0] = entry->dst_addr; - - SW_SET_REG_BY_FIELD(NAPT_ENTRY1, DST_PORT, entry->dst_port, reg[1]); - SW_SET_REG_BY_FIELD(NAPT_ENTRY1, SRC_PORT, entry->src_port, reg[1]); - SW_SET_REG_BY_FIELD(NAPT_ENTRY2, TRANS_PORT, entry->trans_port, reg[2]); - - rv = _isisc_ip_prvaddr_sw_to_hw(dev_id, entry->src_addr, &data); - SW_RTN_ON_ERROR(rv); - - SW_SET_REG_BY_FIELD(NAPT_ENTRY2, SRC_IPADDR0, (data & 0xfff), reg[2]); - SW_SET_REG_BY_FIELD(NAPT_ENTRY3, SRC_IPADDR1, (data >> 12), reg[3]); - - if (!(FAL_NAT_ENTRY_TRANS_IPADDR_INDEX & entry->flags)) - { - return SW_BAD_PARAM; - } - SW_SET_REG_BY_FIELD(NAPT_ENTRY2, TRANS_IPADDR, entry->trans_addr, reg[2]); - - if (FAL_MAC_FRWRD == entry->action) - { - if (A_TRUE == entry->mirror_en) - { - SW_SET_REG_BY_FIELD(NAPT_ENTRY3, ACTION, 0, reg[3]); - } - else - { - SW_SET_REG_BY_FIELD(NAPT_ENTRY3, ACTION, 3, reg[3]); - } - } - else if (FAL_MAC_CPY_TO_CPU == entry->action) - { - SW_SET_REG_BY_FIELD(NAPT_ENTRY3, ACTION, 2, reg[3]); - } - else if (FAL_MAC_RDT_TO_CPU == entry->action) - { - SW_SET_REG_BY_FIELD(NAPT_ENTRY3, ACTION, 1, reg[3]); - } - else - { - return SW_NOT_SUPPORTED; - } - - if (A_TRUE == entry->counter_en) - { - SW_SET_REG_BY_FIELD(NAPT_ENTRY3, CNT_EN, 1, reg[3]); - SW_SET_REG_BY_FIELD(NAPT_ENTRY3, CNT_IDX, entry->counter_id, reg[3]); - } - - data = 2; - if (FAL_NAT_ENTRY_PROTOCOL_TCP & entry->flags) - { - data = 0; - } - else if (FAL_NAT_ENTRY_PROTOCOL_UDP & entry->flags) - { - data = 1; - } - else if (FAL_NAT_ENTRY_PROTOCOL_PPTP & entry->flags) - { - data = 3; - } - SW_SET_REG_BY_FIELD(NAPT_ENTRY3, PROT_TYP, data, reg[3]); - - SW_SET_REG_BY_FIELD(NAPT_ENTRY4, AGE_FLAG, entry->status, reg[4]); - return SW_OK; -} - -static sw_error_t -_isisc_napt_hw_to_sw(a_uint32_t dev_id, a_uint32_t reg[], - fal_napt_entry_t * entry) -{ - sw_error_t rv; - a_uint32_t data, cnt[4] = {0}; - - entry->dst_addr = reg[0]; - - SW_GET_FIELD_BY_REG(NAPT_ENTRY1, DST_PORT, entry->dst_port, reg[1]); - SW_GET_FIELD_BY_REG(NAPT_ENTRY1, SRC_PORT, entry->src_port, reg[1]); - SW_GET_FIELD_BY_REG(NAPT_ENTRY2, TRANS_PORT, entry->trans_port, reg[2]); - - SW_GET_FIELD_BY_REG(NAPT_ENTRY2, SRC_IPADDR0, data, reg[2]); - entry->src_addr = data; - SW_GET_FIELD_BY_REG(NAPT_ENTRY3, SRC_IPADDR1, data, reg[3]); - data = (entry->src_addr & 0xfff) | (data << 12); - rv = _isisc_ip_prvaddr_hw_to_sw(dev_id, data, &(entry->src_addr)); - SW_RTN_ON_ERROR(rv); - - entry->flags |= FAL_NAT_ENTRY_TRANS_IPADDR_INDEX; - SW_GET_FIELD_BY_REG(NAPT_ENTRY2, TRANS_IPADDR, entry->trans_addr, reg[2]); - - SW_GET_FIELD_BY_REG(NAPT_ENTRY3, ACTION, data, reg[3]); - entry->action = FAL_MAC_FRWRD; - if (0 == data) - { - entry->mirror_en = A_TRUE; - } - else if (2 == data) - { - entry->action = FAL_MAC_CPY_TO_CPU; - } - else if (1 == data) - { - entry->action = FAL_MAC_RDT_TO_CPU; - } - - SW_GET_FIELD_BY_REG(NAPT_ENTRY3, CNT_EN, data, reg[3]); - if (data) - { - entry->counter_en = A_TRUE; - SW_GET_FIELD_BY_REG(NAPT_ENTRY3, CNT_IDX, entry->counter_id, reg[3]); - - rv = _isisc_nat_counter_get(dev_id, entry->counter_id, cnt); - SW_RTN_ON_ERROR(rv); - - entry->ingress_packet = cnt[0]; - entry->ingress_byte = cnt[1]; - entry->egress_packet = cnt[2]; - entry->egress_byte = cnt[3]; - } - else - { - entry->counter_en = A_FALSE; - } - - SW_GET_FIELD_BY_REG(NAPT_ENTRY3, PROT_TYP, data, reg[3]); - if (0 == data) - { - entry->flags |= FAL_NAT_ENTRY_PROTOCOL_TCP; - } - else if (1 == data) - { - entry->flags |= FAL_NAT_ENTRY_PROTOCOL_UDP; - } - else if (3 == data) - { - entry->flags |= FAL_NAT_ENTRY_PROTOCOL_PPTP; - } - - SW_GET_FIELD_BY_REG(NAPT_ENTRY4, AGE_FLAG, entry->status, reg[4]); - return SW_OK; -} - -static sw_error_t -_isisc_nat_down_to_hw(a_uint32_t dev_id, a_uint32_t reg[]) -{ - sw_error_t rv; - a_uint32_t i, addr; - - for (i = 0; i < ISISC_HOST_ENTRY_REG_NUM; i++) - { - if((ISISC_HOST_ENTRY_REG_NUM - 1) == i) - { - addr = ISISC_HOST_ENTRY_DATA7_ADDR; - } - else - { - addr = ISISC_HOST_ENTRY_DATA0_ADDR + (i << 2); - } - - HSL_REG_ENTRY_GEN_SET(rv, dev_id, addr, sizeof (a_uint32_t), - (a_uint8_t *) (®[i]), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - } - - return SW_OK; -} - -static sw_error_t -_isisc_nat_up_to_sw(a_uint32_t dev_id, a_uint32_t reg[]) -{ - sw_error_t rv; - a_uint32_t i, addr; - - for (i = 0; i < ISISC_HOST_ENTRY_REG_NUM; i++) - { - if((ISISC_HOST_ENTRY_REG_NUM -1) == i) - { - addr = ISISC_HOST_ENTRY_DATA7_ADDR; - } - else - { - addr = ISISC_HOST_ENTRY_DATA0_ADDR + (i << 2); - } - - HSL_REG_ENTRY_GEN_GET(rv, dev_id, addr, sizeof (a_uint32_t), - (a_uint8_t *) (®[i]), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - } - - return SW_OK; -} - -static sw_error_t -_isisc_nat_add(a_uint32_t dev_id, fal_nat_entry_t * entry) -{ - sw_error_t rv; - a_uint32_t i, reg[ISISC_HOST_ENTRY_REG_NUM] = { 0 }; - - HSL_DEV_ID_CHECK(dev_id); - - rv = _isisc_nat_feature_check(dev_id); - SW_RTN_ON_ERROR(rv); - - for (i = 0; i < ISISC_NAT_ENTRY_NUM; i++) - { - if (!(isisc_nat_snap[dev_id] & (0x1 << i))) - { - break; - } - } - - if (ISISC_NAT_ENTRY_NUM == i) - { - return SW_NO_RESOURCE; - } - - entry->entry_id = i; - - rv = _isisc_nat_sw_to_hw(dev_id, entry, reg); - SW_RTN_ON_ERROR(rv); - - rv = _isisc_nat_down_to_hw(dev_id, reg); - SW_RTN_ON_ERROR(rv); - - rv = _isisc_nat_entry_commit(dev_id, ISISC_ENTRY_NAT, ISISC_NAT_ENTRY_ADD); - SW_RTN_ON_ERROR(rv); - - isisc_nat_snap[dev_id] |= (0x1 << i); - entry->entry_id = i; - return SW_OK; -} - -static sw_error_t -_isisc_nat_del(a_uint32_t dev_id, a_uint32_t del_mode, fal_nat_entry_t * entry) -{ - sw_error_t rv; - a_uint32_t reg[ISISC_HOST_ENTRY_REG_NUM] = { 0 }; - - HSL_DEV_ID_CHECK(dev_id); - - rv = _isisc_nat_feature_check(dev_id); - SW_RTN_ON_ERROR(rv); - - if (FAL_NAT_ENTRY_ID_EN & del_mode) - { - SW_SET_REG_BY_FIELD(HOST_ENTRY7, ENTRY_FUNC, ISISC_NAT_ENTRY_DEL, reg[7]); - SW_SET_REG_BY_FIELD(HOST_ENTRY7, TBL_IDX, entry->entry_id, reg[7]); - - rv = _isisc_nat_down_to_hw(dev_id, reg); - SW_RTN_ON_ERROR(rv); - - rv = _isisc_nat_entry_commit(dev_id, ISISC_ENTRY_NAT, ISISC_NAT_ENTRY_DEL); - SW_RTN_ON_ERROR(rv); - - isisc_nat_snap[dev_id] &= (~(0x1 << entry->entry_id)); - } - else - { - rv = _isisc_nat_down_to_hw(dev_id, reg); - SW_RTN_ON_ERROR(rv); - - rv = _isisc_nat_entry_commit(dev_id, ISISC_ENTRY_NAT, ISISC_NAT_ENTRY_FLUSH); - SW_RTN_ON_ERROR(rv); - - isisc_nat_snap[dev_id] = 0; - } - - return SW_OK; -} - -static sw_error_t -_isisc_nat_get(a_uint32_t dev_id, a_uint32_t get_mode, fal_nat_entry_t * entry) -{ - sw_error_t rv; - a_uint32_t reg[ISISC_HOST_ENTRY_REG_NUM] = { 0 }; - - HSL_DEV_ID_CHECK(dev_id); - - rv = _isisc_nat_feature_check(dev_id); - SW_RTN_ON_ERROR(rv); - - if (FAL_NAT_ENTRY_ID_EN != get_mode) - { - return SW_NOT_SUPPORTED; - } - - if (!(isisc_nat_snap[dev_id] & (0x1 << entry->entry_id))) - { - return SW_NOT_FOUND; - } - - SW_SET_REG_BY_FIELD(HOST_ENTRY7, TBL_IDX, entry->entry_id, reg[7]); - - rv = _isisc_nat_down_to_hw(dev_id, reg); - SW_RTN_ON_ERROR(rv); - - rv = _isisc_nat_entry_commit(dev_id, ISISC_ENTRY_NAT, ISISC_NAT_ENTRY_SEARCH); - SW_RTN_ON_ERROR(rv); - - rv = _isisc_nat_up_to_sw(dev_id, reg); - SW_RTN_ON_ERROR(rv); - - rv = _isisc_nat_hw_to_sw(dev_id, reg, entry); - return rv; -} - -static sw_error_t -_isisc_nat_next(a_uint32_t dev_id, a_uint32_t next_mode, - fal_nat_entry_t * nat_entry) -{ - a_uint32_t i, idx, reg[ISISC_HOST_ENTRY_REG_NUM] = { 0 }; - sw_error_t rv; - - HSL_DEV_ID_CHECK(dev_id); - - rv = _isisc_nat_feature_check(dev_id); - SW_RTN_ON_ERROR(rv); - - if (FAL_NEXT_ENTRY_FIRST_ID == nat_entry->entry_id) - { - idx = 0; - } - else - { - if ((ISISC_NAT_ENTRY_NUM - 1) == nat_entry->entry_id) - { - return SW_NO_MORE; - } - else - { - idx = nat_entry->entry_id + 1; - } - } - - for (i = idx; i < ISISC_NAT_ENTRY_NUM; i++) - { - if (isisc_nat_snap[dev_id] & (0x1 << i)) - { - break; - } - } - - if (ISISC_NAT_ENTRY_NUM == i) - { - return SW_NO_MORE; - } - - SW_SET_REG_BY_FIELD(HOST_ENTRY7, TBL_IDX, i, reg[7]); - - rv = _isisc_nat_down_to_hw(dev_id, reg); - SW_RTN_ON_ERROR(rv); - - rv = _isisc_nat_entry_commit(dev_id, ISISC_ENTRY_NAT, ISISC_NAT_ENTRY_SEARCH); - SW_RTN_ON_ERROR(rv); - - rv = _isisc_nat_up_to_sw(dev_id, reg); - SW_RTN_ON_ERROR(rv); - - aos_mem_zero(nat_entry, sizeof (fal_nat_entry_t)); - - rv = _isisc_nat_hw_to_sw(dev_id, reg, nat_entry); - SW_RTN_ON_ERROR(rv); - - nat_entry->entry_id = i; - return SW_OK; -} - -static sw_error_t -_isisc_nat_counter_bind(a_uint32_t dev_id, a_uint32_t entry_id, - a_uint32_t cnt_id, a_bool_t enable) -{ - sw_error_t rv; - a_uint32_t reg[ISISC_HOST_ENTRY_REG_NUM] = { 0 }; - - HSL_DEV_ID_CHECK(dev_id); - - rv = _isisc_nat_feature_check(dev_id); - SW_RTN_ON_ERROR(rv); - - if (!(isisc_nat_snap[dev_id] & (0x1 << entry_id))) - { - return SW_NOT_FOUND; - } - - SW_SET_REG_BY_FIELD(HOST_ENTRY7, TBL_IDX, entry_id, reg[7]); - - rv = _isisc_nat_entry_commit(dev_id, ISISC_ENTRY_NAT, ISISC_NAT_ENTRY_SEARCH); - SW_RTN_ON_ERROR(rv); - - rv = _isisc_nat_up_to_sw(dev_id, reg); - SW_RTN_ON_ERROR(rv); - - if (A_FALSE == enable) - { - SW_SET_REG_BY_FIELD(NAT_ENTRY2, CNT_EN, 0, reg[2]); - } - else if (A_TRUE == enable) - { - SW_SET_REG_BY_FIELD(NAT_ENTRY2, CNT_EN, 1, reg[2]); - SW_SET_REG_BY_FIELD(NAT_ENTRY2, CNT_IDX, cnt_id, reg[2]); - } - else - { - return SW_BAD_PARAM; - } - - /* needn't set TBL_IDX, keep hardware register value */ - - rv = _isisc_nat_entry_commit(dev_id, ISISC_ENTRY_NAT, ISISC_NAT_ENTRY_DEL); - SW_RTN_ON_ERROR(rv); - - rv = _isisc_nat_down_to_hw(dev_id, reg); - SW_RTN_ON_ERROR(rv); - - /* needn't set TBL_IDX, keep hardware register value */ - - rv = _isisc_nat_entry_commit(dev_id, ISISC_ENTRY_NAT, ISISC_NAT_ENTRY_ADD); - return rv; -} - -static sw_error_t -_isisc_napt_add(a_uint32_t dev_id, fal_napt_entry_t * entry) -{ - sw_error_t rv; - a_uint32_t reg[ISISC_HOST_ENTRY_REG_NUM] = { 0 }; - - HSL_DEV_ID_CHECK(dev_id); - - rv = _isisc_nat_feature_check(dev_id); - SW_RTN_ON_ERROR(rv); - - HSL_DEV_ID_CHECK(dev_id); - - rv = _isisc_napt_sw_to_hw(dev_id, entry, reg); - SW_RTN_ON_ERROR(rv); - - rv = _isisc_nat_down_to_hw(dev_id, reg); - SW_RTN_ON_ERROR(rv); - - rv = _isisc_nat_entry_commit(dev_id, ISISC_ENTRY_NAPT, ISISC_NAT_ENTRY_ADD); - SW_RTN_ON_ERROR(rv); - - rv = _isisc_nat_up_to_sw(dev_id, reg); - SW_RTN_ON_ERROR(rv); - - SW_GET_FIELD_BY_REG(HOST_ENTRY7, TBL_IDX, entry->entry_id, reg[7]); - return SW_OK; -} - -static sw_error_t -_isisc_napt_del(a_uint32_t dev_id, a_uint32_t del_mode, fal_napt_entry_t * entry) -{ - sw_error_t rv; - a_uint32_t data, reg[ISISC_HOST_ENTRY_REG_NUM] = { 0 }; - - HSL_DEV_ID_CHECK(dev_id); - - rv = _isisc_nat_feature_check(dev_id); - SW_RTN_ON_ERROR(rv); - - if (FAL_NAT_ENTRY_ID_EN & del_mode) - { - return SW_NOT_SUPPORTED; - } - - if (FAL_NAT_ENTRY_KEY_EN & del_mode) - { - rv = _isisc_napt_sw_to_hw(dev_id, entry, reg); - SW_RTN_ON_ERROR(rv); - - rv = _isisc_nat_down_to_hw(dev_id, reg); - SW_RTN_ON_ERROR(rv); - - rv = _isisc_nat_entry_commit(dev_id, ISISC_ENTRY_NAPT, ISISC_NAT_ENTRY_DEL); - SW_RTN_ON_ERROR(rv); - - rv = _isisc_nat_up_to_sw(dev_id, reg); - SW_RTN_ON_ERROR(rv); - - SW_GET_FIELD_BY_REG(HOST_ENTRY7, TBL_IDX, entry->entry_id, reg[7]); - return SW_OK; - } - else - { - if (FAL_NAT_ENTRY_PUBLIC_IP_EN & del_mode) - { - SW_SET_REG_BY_FIELD(HOST_ENTRY7, SPEC_PIP, 1, reg[7]); - SW_SET_REG_BY_FIELD(NAPT_ENTRY2, TRANS_IPADDR, entry->trans_addr, reg[2]); - } - - if (FAL_NAT_ENTRY_SOURCE_IP_EN & del_mode) - { - SW_SET_REG_BY_FIELD(HOST_ENTRY7, SPEC_SIP, 1, reg[7]); - rv = _isisc_ip_prvaddr_sw_to_hw(dev_id, entry->src_addr, &data); - SW_RTN_ON_ERROR(rv); - SW_SET_REG_BY_FIELD(NAPT_ENTRY2, SRC_IPADDR0, (data & 0xfff), reg[2]); - SW_SET_REG_BY_FIELD(NAPT_ENTRY3, SRC_IPADDR1, (data >> 12), reg[3]); - } - - if (FAL_NAT_ENTRY_AGE_EN & del_mode) - { - SW_SET_REG_BY_FIELD(HOST_ENTRY7, SPEC_STATUS, 1, reg[7]); - SW_SET_REG_BY_FIELD(NAPT_ENTRY4, AGE_FLAG, entry->status, reg[4]); - } - - rv = _isisc_nat_down_to_hw(dev_id, reg); - SW_RTN_ON_ERROR(rv); - - rv = _isisc_nat_entry_commit(dev_id, ISISC_ENTRY_NAPT, ISISC_NAT_ENTRY_FLUSH); - return rv; - } -} - -static sw_error_t -_isisc_napt_get(a_uint32_t dev_id, a_uint32_t get_mode, fal_napt_entry_t * entry) -{ - sw_error_t rv; - a_uint32_t found, age, reg[ISISC_HOST_ENTRY_REG_NUM] = { 0 }; - - HSL_DEV_ID_CHECK(dev_id); - - rv = _isisc_nat_feature_check(dev_id); - SW_RTN_ON_ERROR(rv); - -#if 0 - if (FAL_NAT_ENTRY_ID_EN != get_mode) - { - return SW_NOT_SUPPORTED; - } - - SW_SET_REG_BY_FIELD(HOST_ENTRY7, TBL_IDX, entry->entry_id, reg[7]); -#else - rv = _isisc_napt_sw_to_hw(dev_id, entry, reg); - SW_RTN_ON_ERROR(rv); -#endif - - rv = _isisc_nat_down_to_hw(dev_id, reg); - SW_RTN_ON_ERROR(rv); - - rv = _isisc_nat_entry_commit(dev_id, ISISC_ENTRY_NAPT, ISISC_NAT_ENTRY_SEARCH); - SW_RTN_ON_ERROR(rv); - - rv = _isisc_nat_up_to_sw(dev_id, reg); - SW_RTN_ON_ERROR(rv); - - SW_GET_FIELD_BY_REG(HOST_ENTRY7, TBL_STAUS, found, reg[7]); - SW_GET_FIELD_BY_REG(NAPT_ENTRY4, AGE_FLAG, age, reg[4]); - if (found && age) - { - found = 1; - } - else - { - found = 0; - } - - rv = _isisc_napt_hw_to_sw(dev_id, reg, entry); - SW_RTN_ON_ERROR(rv); - - if (!found) - { - return SW_NOT_FOUND; - } - - SW_GET_FIELD_BY_REG(HOST_ENTRY7, TBL_IDX, entry->entry_id, reg[7]); - return SW_OK; -} - -static sw_error_t -_isisc_napt_next(a_uint32_t dev_id, a_uint32_t next_mode, - fal_napt_entry_t * napt_entry) -{ - a_uint32_t data, idx, reg[ISISC_HOST_ENTRY_REG_NUM] = { 0 }; - sw_error_t rv; - - HSL_DEV_ID_CHECK(dev_id); - - rv = _isisc_nat_feature_check(dev_id); - SW_RTN_ON_ERROR(rv); - - if (FAL_NEXT_ENTRY_FIRST_ID == napt_entry->entry_id) - { - idx = ISISC_NAPT_ENTRY_NUM - 1; - } - else - { - if ((ISISC_NAPT_ENTRY_NUM - 1) == napt_entry->entry_id) - { - return SW_NO_MORE; - } - else - { - idx = napt_entry->entry_id; - } - } - - if (FAL_NAT_ENTRY_PUBLIC_IP_EN & next_mode) - { - SW_SET_REG_BY_FIELD(HOST_ENTRY7, SPEC_PIP, 1, reg[7]); - SW_SET_REG_BY_FIELD(NAPT_ENTRY2, TRANS_IPADDR, napt_entry->trans_addr, reg[2]); - } - - if (FAL_NAT_ENTRY_SOURCE_IP_EN & next_mode) - { - SW_SET_REG_BY_FIELD(HOST_ENTRY7, SPEC_SIP, 1, reg[7]); - rv = _isisc_ip_prvaddr_sw_to_hw(dev_id, napt_entry->src_addr, &data); - SW_RTN_ON_ERROR(rv); - SW_SET_REG_BY_FIELD(NAPT_ENTRY2, SRC_IPADDR0, (data & 0xfff), reg[2]); - SW_SET_REG_BY_FIELD(NAPT_ENTRY3, SRC_IPADDR1, (data >> 12), reg[3]); - } - - if (FAL_NAT_ENTRY_AGE_EN & next_mode) - { - SW_SET_REG_BY_FIELD(HOST_ENTRY7, SPEC_STATUS, 1, reg[7]); - SW_SET_REG_BY_FIELD(NAPT_ENTRY4, AGE_FLAG, napt_entry->status, reg[4]); - } - - SW_SET_REG_BY_FIELD(HOST_ENTRY7, TBL_IDX, idx, reg[7]); - - rv = _isisc_nat_down_to_hw(dev_id, reg); - SW_RTN_ON_ERROR(rv); - - rv = _isisc_nat_entry_commit(dev_id, ISISC_ENTRY_NAPT, ISISC_NAT_ENTRY_NEXT); - SW_RTN_ON_ERROR(rv); - - rv = _isisc_nat_up_to_sw(dev_id, reg); - SW_RTN_ON_ERROR(rv); - - aos_mem_zero(napt_entry, sizeof (fal_nat_entry_t)); - - rv = _isisc_napt_hw_to_sw(dev_id, reg, napt_entry); - SW_RTN_ON_ERROR(rv); - -#if 0 - a_uint32_t temp=0, complete=0; - - HSL_REG_ENTRY_GET(rv, dev_id, HOST_ENTRY7, 0, (a_uint8_t *) (&temp), - sizeof (a_uint32_t)); - - SW_GET_FIELD_BY_REG(HOST_ENTRY7, TBL_STAUS, complete, temp); - - if (!complete) - { - return SW_NO_MORE; - } -#endif - - SW_GET_FIELD_BY_REG(HOST_ENTRY7, TBL_IDX, napt_entry->entry_id, reg[7]); - return SW_OK; -} - -static sw_error_t -_isisc_napt_counter_bind(a_uint32_t dev_id, a_uint32_t entry_id, - a_uint32_t cnt_id, a_bool_t enable) -{ - sw_error_t rv; - a_uint32_t reg[ISISC_HOST_ENTRY_REG_NUM] = { 0 }, tbl_idx; - - HSL_DEV_ID_CHECK(dev_id); - - rv = _isisc_nat_feature_check(dev_id); - SW_RTN_ON_ERROR(rv); - - tbl_idx = (entry_id - 1) & 0x3ff; - SW_SET_REG_BY_FIELD(HOST_ENTRY7, TBL_IDX, tbl_idx, reg[7]); - - rv = _isisc_nat_down_to_hw(dev_id, reg); - SW_RTN_ON_ERROR(rv); - - rv = _isisc_nat_entry_commit(dev_id, ISISC_ENTRY_NAPT, ISISC_NAT_ENTRY_NEXT); - if (SW_OK != rv) - { - return SW_NOT_FOUND; - } - - rv = _isisc_nat_up_to_sw(dev_id, reg); - SW_RTN_ON_ERROR(rv); - - SW_GET_FIELD_BY_REG(HOST_ENTRY7, TBL_IDX, tbl_idx, reg[7]); - if (entry_id != tbl_idx) - { - return SW_NOT_FOUND; - } - - if (A_FALSE == enable) - { - SW_SET_REG_BY_FIELD(NAPT_ENTRY3, CNT_EN, 0, reg[3]); - } - else if (A_TRUE == enable) - { - SW_SET_REG_BY_FIELD(NAPT_ENTRY3, CNT_EN, 1, reg[3]); - SW_SET_REG_BY_FIELD(NAPT_ENTRY3, CNT_IDX, cnt_id, reg[3]); - } - else - { - return SW_BAD_PARAM; - } - - rv = _isisc_nat_entry_commit(dev_id, ISISC_ENTRY_NAPT, ISISC_NAT_ENTRY_DEL); - SW_RTN_ON_ERROR(rv); - - reg[4] = 0x0; - rv = _isisc_nat_down_to_hw(dev_id, reg); - SW_RTN_ON_ERROR(rv); - - rv = _isisc_nat_entry_commit(dev_id, ISISC_ENTRY_NAPT, ISISC_NAT_ENTRY_ADD); - return rv; -} - -static sw_error_t -_isisc_nat_status_set(a_uint32_t dev_id, a_bool_t enable) -{ - sw_error_t rv; - a_uint32_t data; - - HSL_DEV_ID_CHECK(dev_id); - - rv = _isisc_nat_feature_check(dev_id); - SW_RTN_ON_ERROR(rv); - - if (A_TRUE == enable) - { - data = 1; - } - else if (A_FALSE == enable) - { - data = 0; - } - else - { - return SW_BAD_PARAM; - } - - HSL_REG_FIELD_SET(rv, dev_id, NAT_CTRL, 0, NAT_EN, - (a_uint8_t *) (&data), sizeof (a_uint32_t)); - return rv; -} - -static sw_error_t -_isisc_nat_status_get(a_uint32_t dev_id, a_bool_t * enable) -{ - sw_error_t rv; - a_uint32_t data = 0; - - HSL_DEV_ID_CHECK(dev_id); - - rv = _isisc_nat_feature_check(dev_id); - SW_RTN_ON_ERROR(rv); - - HSL_REG_FIELD_GET(rv, dev_id, NAT_CTRL, 0, NAT_EN, - (a_uint8_t *) (&data), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - - if (data) - { - *enable = A_TRUE; - } - else - { - *enable = A_FALSE; - } - - return rv; -} - -static sw_error_t -_isisc_napt_status_set(a_uint32_t dev_id, a_bool_t enable) -{ - sw_error_t rv; - a_uint32_t data; - - HSL_DEV_ID_CHECK(dev_id); - - rv = _isisc_nat_feature_check(dev_id); - SW_RTN_ON_ERROR(rv); - - if (A_TRUE == enable) - { - data = 1; - } - else if (A_FALSE == enable) - { - data = 0; - } - else - { - return SW_BAD_PARAM; - } - - HSL_REG_FIELD_SET(rv, dev_id, NAT_CTRL, 0, NAPT_EN, - (a_uint8_t *) (&data), sizeof (a_uint32_t)); - return rv; -} - -static sw_error_t -_isisc_napt_status_get(a_uint32_t dev_id, a_bool_t * enable) -{ - sw_error_t rv; - a_uint32_t data = 0; - - HSL_DEV_ID_CHECK(dev_id); - - rv = _isisc_nat_feature_check(dev_id); - SW_RTN_ON_ERROR(rv); - - HSL_REG_FIELD_GET(rv, dev_id, NAT_CTRL, 0, NAPT_EN, - (a_uint8_t *) (&data), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - - if (data) - { - *enable = A_TRUE; - } - else - { - *enable = A_FALSE; - } - - return rv; -} - -static sw_error_t -_isisc_napt_mode_set(a_uint32_t dev_id, fal_napt_mode_t mode) -{ - sw_error_t rv; - a_uint32_t data; - - HSL_DEV_ID_CHECK(dev_id); - - rv = _isisc_nat_feature_check(dev_id); - SW_RTN_ON_ERROR(rv); - - if (FAL_NAPT_FULL_CONE == mode) - { - data = 0; - } - else if (FAL_NAPT_STRICT_CONE == mode) - { - data = 1; - } - else if ((FAL_NAPT_PORT_STRICT == mode) - || (FAL_NAPT_SYNMETRIC == mode)) - { - data = 2; - } - else - { - return SW_BAD_PARAM; - } - - HSL_REG_FIELD_SET(rv, dev_id, NAT_CTRL, 0, NAPT_MODE, - (a_uint8_t *) (&data), sizeof (a_uint32_t)); - return rv; -} - -static sw_error_t -_isisc_napt_mode_get(a_uint32_t dev_id, fal_napt_mode_t * mode) -{ - sw_error_t rv; - a_uint32_t data = 0; - - HSL_DEV_ID_CHECK(dev_id); - - rv = _isisc_nat_feature_check(dev_id); - SW_RTN_ON_ERROR(rv); - - HSL_REG_FIELD_GET(rv, dev_id, NAT_CTRL, 0, NAPT_MODE, - (a_uint8_t *) (&data), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - - if (0 == data) - { - *mode = FAL_NAPT_FULL_CONE; - } - else if (1 == data) - { - *mode = FAL_NAPT_STRICT_CONE; - } - else - { - *mode = FAL_NAPT_PORT_STRICT; - } - - return SW_OK; -} - -static sw_error_t -_isisc_nat_hash_mode_set(a_uint32_t dev_id, a_uint32_t mode) -{ - sw_error_t rv; - a_uint32_t data; - - HSL_DEV_ID_CHECK(dev_id); - - rv = _isisc_nat_feature_check(dev_id); - SW_RTN_ON_ERROR(rv); - - if ((FAL_NAT_HASH_KEY_PORT & mode) - && (FAL_NAT_HASH_KEY_IPADDR & mode)) - { - data = 2; - } - else if (FAL_NAT_HASH_KEY_PORT & mode) - { - data = 0; - } - else if (FAL_NAT_HASH_KEY_IPADDR & mode) - { - data = 1; - } - else - { - return SW_BAD_PARAM; - } - - HSL_REG_FIELD_SET(rv, dev_id, NAT_CTRL, 0, NAT_HASH_MODE, - (a_uint8_t *) (&data), sizeof (a_uint32_t)); - return rv; -} - -static sw_error_t -_isisc_nat_hash_mode_get(a_uint32_t dev_id, a_uint32_t * mode) -{ - sw_error_t rv; - a_uint32_t data = 0; - - HSL_DEV_ID_CHECK(dev_id); - - rv = _isisc_nat_feature_check(dev_id); - SW_RTN_ON_ERROR(rv); - - HSL_REG_FIELD_GET(rv, dev_id, NAT_CTRL, 0, NAT_HASH_MODE, - (a_uint8_t *) (&data), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - - *mode = 0; - if (0 == data) - { - *mode = FAL_NAT_HASH_KEY_PORT; - } - else if (1 == data) - { - *mode = FAL_NAT_HASH_KEY_IPADDR; - } - else if (2 == data) - { - *mode = FAL_NAT_HASH_KEY_PORT; - *mode |= FAL_NAT_HASH_KEY_IPADDR; - } - - return SW_OK; -} - -static sw_error_t -_isisc_nat_prv_base_addr_set(a_uint32_t dev_id, fal_ip4_addr_t addr) -{ - sw_error_t rv; - a_uint32_t data; - - HSL_DEV_ID_CHECK(dev_id); - - rv = _isisc_nat_feature_check(dev_id); - SW_RTN_ON_ERROR(rv); - - data = addr; - HSL_REG_FIELD_SET(rv, dev_id, PRVIP_ADDR, 0, IP4_BASEADDR, - (a_uint8_t *) (&data), sizeof (a_uint32_t)); - return rv; -} - -static sw_error_t -_isisc_nat_prv_base_addr_get(a_uint32_t dev_id, fal_ip4_addr_t * addr) -{ - sw_error_t rv; - a_uint32_t data = 0; - - HSL_DEV_ID_CHECK(dev_id); - - rv = _isisc_nat_feature_check(dev_id); - SW_RTN_ON_ERROR(rv); - - HSL_REG_FIELD_GET(rv, dev_id, PRVIP_ADDR, 0, IP4_BASEADDR, - (a_uint8_t *) (&data), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - *addr = data; - - return SW_OK; -} - -static sw_error_t -_isisc_nat_prv_base_mask_set(a_uint32_t dev_id, fal_ip4_addr_t mask) -{ - sw_error_t rv; - a_uint32_t data; - - HSL_DEV_ID_CHECK(dev_id); - - rv = _isisc_nat_feature_check(dev_id); - SW_RTN_ON_ERROR(rv); - - data = mask; - HSL_REG_FIELD_SET(rv, dev_id, PRVIP_MASK, 0, IP4_BASEMASK, - (a_uint8_t *) (&data), sizeof (a_uint32_t)); - return rv; -} - -#if 0 -static sw_error_t -_isisc_nat_psr_prv_base_addr_set(a_uint32_t dev_id, fal_ip4_addr_t addr) -{ -#if 0 - sw_error_t rv; - a_uint32_t data; - - HSL_DEV_ID_CHECK(dev_id); - - rv = _isisc_nat_feature_check(dev_id); - SW_RTN_ON_ERROR(rv); - - HSL_REG_FIELD_GET(rv, dev_id, PRVIP_CTL, 0, BASEADDR_SEL, - (a_uint8_t *) (&data), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - - if (data) - { - data = (((addr >> 20) & 0xfff) << 8) | ((addr >> 8) & 0xff); - } - else - { - data = (addr >> 12) & 0xfffff; - } - - HSL_REG_FIELD_SET(rv, dev_id, PRVIP_CTL, 0, IP4_BASEADDR, - (a_uint8_t *) (&data), sizeof (a_uint32_t)); - return rv; -#endif - return SW_OK; -} - -static sw_error_t -_isisc_nat_psr_prv_base_addr_get(a_uint32_t dev_id, fal_ip4_addr_t * addr) -{ -#if 0 - sw_error_t rv; - a_uint32_t data, tmp; - - HSL_DEV_ID_CHECK(dev_id); - - rv = _isisc_nat_feature_check(dev_id); - SW_RTN_ON_ERROR(rv); - - HSL_REG_FIELD_GET(rv, dev_id, PRVIP_CTL, 0, BASEADDR_SEL, - (a_uint8_t *) (&tmp), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - - HSL_REG_FIELD_GET(rv, dev_id, PRVIP_CTL, 0, IP4_BASEADDR, - (a_uint8_t *) (&data), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - - if (tmp) - { - *addr = ((data & 0xff) << 8) | (((data >> 8) & 0xfff) << 20); - } - else - { - *addr = (data & 0xfffff) << 12; - } -#endif - return SW_OK; -} -#endif - -static sw_error_t -_isisc_nat_prv_base_mask_get(a_uint32_t dev_id, fal_ip4_addr_t * mask) -{ - sw_error_t rv; - a_uint32_t data = 0; - - HSL_DEV_ID_CHECK(dev_id); - - rv = _isisc_nat_feature_check(dev_id); - SW_RTN_ON_ERROR(rv); - - HSL_REG_FIELD_GET(rv, dev_id, PRVIP_MASK, 0, IP4_BASEMASK, - (a_uint8_t *) (&data), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - - *mask = data; - return SW_OK; -} - -static sw_error_t -_isisc_nat_pub_addr_commit(a_uint32_t dev_id, fal_nat_pub_addr_t * entry, - a_uint32_t op, a_uint32_t * empty) -{ - a_uint32_t index, addr, data, tbl[2] = { 0 }; - sw_error_t rv; - - *empty = ISISC_PUB_ADDR_NUM; - for (index = 0; index < ISISC_PUB_ADDR_NUM; index++) - { - addr = ISISC_PUB_ADDR_TBL1_ADDR + (index << 4); - HSL_REG_ENTRY_GEN_GET(rv, dev_id, addr, sizeof (a_uint32_t), - (a_uint8_t *) (&(tbl[1])), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - - SW_GET_FIELD_BY_REG(PUB_ADDR1, ADDR_VALID, data, tbl[1]); - if (data) - { - addr = ISISC_PUB_ADDR_TBL0_ADDR + (index << 4); - HSL_REG_ENTRY_GEN_GET(rv, dev_id, addr, sizeof (a_uint32_t), - (a_uint8_t *) (&(tbl[0])), - sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - - if (!aos_mem_cmp - ((void *) &(entry->pub_addr), (void *) &(tbl[0]), - sizeof (fal_ip4_addr_t))) - { - if (ISISC_NAT_ENTRY_DEL == op) - { - addr = ISISC_PUB_ADDR_TBL1_ADDR + (index << 4); - tbl[1] = 0; - HSL_REG_ENTRY_GEN_SET(rv, dev_id, addr, sizeof (a_uint32_t), - (a_uint8_t *) (&(tbl[1])), - sizeof (a_uint32_t)); - *empty = index; - return rv; - } - else if (ISISC_NAT_ENTRY_ADD == op) - { - entry->entry_id = index; - return SW_ALREADY_EXIST; - } - } - } - else - { - *empty = index; - } - } - - return SW_NOT_FOUND; -} - -static sw_error_t -_isisc_nat_pub_addr_add(a_uint32_t dev_id, fal_nat_pub_addr_t * entry) -{ - sw_error_t rv; - a_uint32_t i, empty, addr, data = 0, tbl[2] = { 0 }; - - HSL_DEV_ID_CHECK(dev_id); - - rv = _isisc_nat_feature_check(dev_id); - SW_RTN_ON_ERROR(rv); - - tbl[0] = entry->pub_addr; - tbl[1] = 1; - - rv = _isisc_nat_pub_addr_commit(dev_id, entry, ISISC_NAT_ENTRY_ADD, &empty); - if (SW_ALREADY_EXIST == rv) - { - return rv; - } - - if (ISISC_PUB_ADDR_NUM == empty) - { - return SW_NO_RESOURCE; - } - - for (i = 0; i < 1; i++) - { - addr = ISISC_PUB_ADDR_EDIT0_ADDR + (empty << 4) + (i << 2); - HSL_REG_ENTRY_GEN_SET(rv, dev_id, addr, sizeof (a_uint32_t), - (a_uint8_t *) (&(tbl[i])), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - } - - addr = ISISC_PUB_ADDR_OFFLOAD_ADDR + (empty << 2); - HSL_REG_ENTRY_GEN_SET(rv, dev_id, addr, sizeof (a_uint32_t), - (a_uint8_t *) (&(tbl[0])), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - - addr = ISISC_PUB_ADDR_VALID_ADDR; - HSL_REG_ENTRY_GEN_GET(rv, dev_id, addr, sizeof (a_uint32_t), - (a_uint8_t *) (&data), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - - data |= (0x1 << empty); - HSL_REG_ENTRY_GEN_SET(rv, dev_id, addr, sizeof (a_uint32_t), - (a_uint8_t *) (&data), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - - for (i = 0; i < 2; i++) - { - addr = ISISC_PUB_ADDR_TBL0_ADDR + (empty << 4) + (i << 2); - HSL_REG_ENTRY_GEN_SET(rv, dev_id, addr, sizeof (a_uint32_t), - (a_uint8_t *) (&(tbl[i])), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - } - - entry->entry_id = empty; - return SW_OK; -} - -static sw_error_t -_isisc_nat_pub_addr_del(a_uint32_t dev_id, a_uint32_t del_mode, - fal_nat_pub_addr_t * entry) -{ - sw_error_t rv; - a_uint32_t empty, addr, data = 0; - - HSL_DEV_ID_CHECK(dev_id); - - rv = _isisc_nat_feature_check(dev_id); - SW_RTN_ON_ERROR(rv); - - rv = _isisc_nat_pub_addr_commit(dev_id, entry, ISISC_NAT_ENTRY_DEL, &empty); - SW_RTN_ON_ERROR(rv); - - addr = ISISC_PUB_ADDR_VALID_ADDR; - HSL_REG_ENTRY_GEN_GET(rv, dev_id, addr, sizeof (a_uint32_t), - (a_uint8_t *) (&data), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - - data &= (~(0x1 << empty)); - HSL_REG_ENTRY_GEN_SET(rv, dev_id, addr, sizeof (a_uint32_t), - (a_uint8_t *) (&data), sizeof (a_uint32_t)); - - return rv; -} - -static sw_error_t -_isisc_nat_pub_addr_next(a_uint32_t dev_id, a_uint32_t next_mode, - fal_nat_pub_addr_t * entry) -{ - sw_error_t rv; - a_uint32_t data, addr, idx, index, tbl[2] = {0}; - - HSL_DEV_ID_CHECK(dev_id); - - rv = _isisc_nat_feature_check(dev_id); - SW_RTN_ON_ERROR(rv); - - if (FAL_NEXT_ENTRY_FIRST_ID == entry->entry_id) - { - idx = 0; - } - else - { - if ((ISISC_PUB_ADDR_NUM - 1) == entry->entry_id) - { - return SW_NO_MORE; - } - else - { - idx = entry->entry_id + 1; - } - } - - for (index = idx; index < ISISC_PUB_ADDR_NUM; index++) - { - addr = ISISC_PUB_ADDR_TBL1_ADDR + (index << 4); - HSL_REG_ENTRY_GEN_GET(rv, dev_id, addr, sizeof (a_uint32_t), - (a_uint8_t *) (&(tbl[1])), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - - SW_GET_FIELD_BY_REG(PUB_ADDR1, ADDR_VALID, data, tbl[1]); - if (data) - { - break; - } - } - - if (ISISC_PUB_ADDR_NUM == index) - { - return SW_NO_MORE; - } - - addr = ISISC_PUB_ADDR_TBL0_ADDR + (index << 4); - HSL_REG_ENTRY_GEN_GET(rv, dev_id, addr, sizeof (a_uint32_t), - (a_uint8_t *) (&(tbl[0])), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - - entry->entry_id = index; - entry->pub_addr = tbl[0]; - - return SW_OK; -} - -static sw_error_t -_isisc_nat_unk_session_cmd_set(a_uint32_t dev_id, fal_fwd_cmd_t cmd) -{ - sw_error_t rv; - a_uint32_t data; - - HSL_DEV_ID_CHECK(dev_id); - - rv = _isisc_nat_feature_check(dev_id); - SW_RTN_ON_ERROR(rv); - - if (FAL_MAC_DROP == cmd) - { - data = 1; - } - else if (FAL_MAC_RDT_TO_CPU == cmd) - { - data = 0; - } - else - { - return SW_NOT_SUPPORTED; - } - - HSL_REG_FIELD_SET(rv, dev_id, FORWARD_CTL0, 0, NAT_NOT_FOUND_DROP, - (a_uint8_t *) (&data), sizeof (a_uint32_t)); - return rv; -} - -static sw_error_t -_isisc_nat_unk_session_cmd_get(a_uint32_t dev_id, fal_fwd_cmd_t * cmd) -{ - sw_error_t rv; - a_uint32_t data = 0; - - HSL_DEV_ID_CHECK(dev_id); - - rv = _isisc_nat_feature_check(dev_id); - SW_RTN_ON_ERROR(rv); - - HSL_REG_FIELD_GET(rv, dev_id, FORWARD_CTL0, 0, NAT_NOT_FOUND_DROP, - (a_uint8_t *) (&data), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - - if (0 == data) - { - *cmd = FAL_MAC_RDT_TO_CPU; - } - else - { - *cmd = FAL_MAC_DROP; - } - - return SW_OK; -} - -sw_error_t -isisc_nat_reset(a_uint32_t dev_id) -{ - sw_error_t rv; - a_uint32_t index, addr, data = 0; - - HSL_DEV_ID_CHECK(dev_id); - - rv = _isisc_nat_feature_check(dev_id); - SW_RTN_ON_ERROR(rv); - - isisc_nat_snap[dev_id] = 0; - - HSL_REG_ENTRY_SET(rv, dev_id, HOST_ENTRY7, 0, (a_uint8_t *) (&data), - sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - - rv = _isisc_nat_entry_commit(dev_id, ISISC_ENTRY_NAT, ISISC_NAT_ENTRY_FLUSH); - SW_RTN_ON_ERROR(rv); - - HSL_REG_ENTRY_SET(rv, dev_id, HOST_ENTRY7, 0, (a_uint8_t *) (&data), - sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - - rv = _isisc_nat_entry_commit(dev_id, ISISC_ENTRY_NAPT, ISISC_NAT_ENTRY_FLUSH); - SW_RTN_ON_ERROR(rv); - - for (index = 0; index < ISISC_PUB_ADDR_NUM; index++) - { - addr = ISISC_PUB_ADDR_TBL1_ADDR + (index << 4); - HSL_REG_ENTRY_GEN_SET(rv, dev_id, addr, sizeof (a_uint32_t), - (a_uint8_t *) (&data), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - } - - return SW_OK; -} - -/** - * @brief Add one NAT entry to one particular device. - * @details Comments: - Before NAT entry added ip4 private base address must be set - at first. - In parameter nat_entry entry flags must be set - Hardware entry id will be returned. - * @param[in] dev_id device id - * @param[in] nat_entry NAT entry parameter - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -isisc_nat_add(a_uint32_t dev_id, fal_nat_entry_t * nat_entry) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _isisc_nat_add(dev_id, nat_entry); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Del NAT entries from one particular device. - * @param[in] dev_id device id - * @param[in] del_mode NAT entry delete operation mode - * @param[in] nat_entry NAT entry parameter - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -isisc_nat_del(a_uint32_t dev_id, a_uint32_t del_mode, - fal_nat_entry_t * nat_entry) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _isisc_nat_del(dev_id, del_mode, nat_entry); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Get one NAT entry from one particular device. - * @param[in] dev_id device id - * @param[in] get_mode NAT entry get operation mode - * @param[in] nat_entry NAT entry parameter - * @param[out] nat_entry NAT entry parameter - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -isisc_nat_get(a_uint32_t dev_id, a_uint32_t get_mode, - fal_nat_entry_t * nat_entry) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _isisc_nat_get(dev_id, get_mode, nat_entry); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Next NAT entries from one particular device. - * @param[in] dev_id device id - * @param[in] next_mode NAT entry next operation mode - * @param[in] nat_entry NAT entry parameter - * @param[out] nat_entry NAT entry parameter - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -isisc_nat_next(a_uint32_t dev_id, a_uint32_t next_mode, - fal_nat_entry_t * nat_entry) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _isisc_nat_next(dev_id, next_mode, nat_entry); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Bind one counter entry to one NAT entry to one particular device. - * @param[in] dev_id device id - * @param[in] entry_id NAT entry id - * @param[in] cnt_id counter entry id - * @param[in] enable A_TRUE or A_FALSE - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -isisc_nat_counter_bind(a_uint32_t dev_id, a_uint32_t entry_id, a_uint32_t cnt_id, - a_bool_t enable) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _isisc_nat_counter_bind(dev_id, entry_id, cnt_id, enable); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Add one NAPT entry to one particular device. - * @details Comments: - Before NAPT entry added related ip4 private base address must be set - at first. - In parameter napt_entry related entry flags must be set - Hardware entry id will be returned. - * @param[in] dev_id device id - * @param[in] napt_entry NAPT entry parameter - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -isisc_napt_add(a_uint32_t dev_id, fal_napt_entry_t * napt_entry) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _isisc_napt_add(dev_id, napt_entry); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Del NAPT entries from one particular device. - * @param[in] dev_id device id - * @param[in] del_mode NAPT entry delete operation mode - * @param[in] napt_entry NAPT entry parameter - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -isisc_napt_del(a_uint32_t dev_id, a_uint32_t del_mode, - fal_napt_entry_t * napt_entry) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _isisc_napt_del(dev_id, del_mode, napt_entry); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Get one NAPT entry from one particular device. - * @param[in] dev_id device id - * @param[in] get_mode NAPT entry get operation mode - * @param[in] nat_entry NAPT entry parameter - * @param[out] nat_entry NAPT entry parameter - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -isisc_napt_get(a_uint32_t dev_id, a_uint32_t get_mode, - fal_napt_entry_t * napt_entry) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _isisc_napt_get(dev_id, get_mode, napt_entry); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Next NAPT entries from one particular device. - * @param[in] dev_id device id - * @param[in] next_mode NAPT entry next operation mode - * @param[in] napt_entry NAPT entry parameter - * @param[out] napt_entry NAPT entry parameter - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -isisc_napt_next(a_uint32_t dev_id, a_uint32_t next_mode, - fal_napt_entry_t * napt_entry) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _isisc_napt_next(dev_id, next_mode, napt_entry); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Bind one counter entry to one NAPT entry to one particular device. - * @param[in] dev_id device id - * @param[in] entry_id NAPT entry id - * @param[in] cnt_id counter entry id - * @param[in] enable A_TRUE or A_FALSE - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -isisc_napt_counter_bind(a_uint32_t dev_id, a_uint32_t entry_id, - a_uint32_t cnt_id, a_bool_t enable) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _isisc_napt_counter_bind(dev_id, entry_id, cnt_id, enable); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Set working status of NAT engine on a particular device - * @param[in] dev_id device id - * @param[in] enable A_TRUE or A_FALSE - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -isisc_nat_status_set(a_uint32_t dev_id, a_bool_t enable) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _isisc_nat_status_set(dev_id, enable); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Get working status of NAT engine on a particular device - * @param[in] dev_id device id - * @param[out] enable A_TRUE or A_FALSE - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -isisc_nat_status_get(a_uint32_t dev_id, a_bool_t * enable) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _isisc_nat_status_get(dev_id, enable); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Set NAT hash mode on a particular device - * @param[in] dev_id device id - * @param[in] mode NAT hash mode - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -isisc_nat_hash_mode_set(a_uint32_t dev_id, a_uint32_t mode) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _isisc_nat_hash_mode_set(dev_id, mode); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Get NAT hash mode on a particular device - * @param[in] dev_id device id - * @param[out] mode NAT hash mode - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -isisc_nat_hash_mode_get(a_uint32_t dev_id, a_uint32_t * mode) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _isisc_nat_hash_mode_get(dev_id, mode); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Set working status of NAPT engine on a particular device - * @param[in] dev_id device id - * @param[in] enable A_TRUE or A_FALSE - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -isisc_napt_status_set(a_uint32_t dev_id, a_bool_t enable) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _isisc_napt_status_set(dev_id, enable); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Get working status of NAPT engine on a particular device - * @param[in] dev_id device id - * @param[out] enable A_TRUE or A_FALSE - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -isisc_napt_status_get(a_uint32_t dev_id, a_bool_t * enable) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _isisc_napt_status_get(dev_id, enable); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Set working mode of NAPT engine on a particular device - * @param[in] dev_id device id - * @param[in] mode NAPT mode - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -isisc_napt_mode_set(a_uint32_t dev_id, fal_napt_mode_t mode) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _isisc_napt_mode_set(dev_id, mode); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Get working mode of NAPT engine on a particular device - * @param[in] dev_id device id - * @param[out] mode NAPT mode - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -isisc_napt_mode_get(a_uint32_t dev_id, fal_napt_mode_t * mode) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _isisc_napt_mode_get(dev_id, mode); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Set IP4 private base address on a particular device - * @details Comments: - Only 20bits is meaning which 20bits is determined by private address mode. - * @param[in] dev_id device id - * @param[in] addr private base address - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -isisc_nat_prv_base_addr_set(a_uint32_t dev_id, fal_ip4_addr_t addr) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _isisc_nat_prv_base_addr_set(dev_id, addr); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Get IP4 private base address on a particular device - * @param[in] dev_id device id - * @param[out] addr private base address - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -isisc_nat_prv_base_addr_get(a_uint32_t dev_id, fal_ip4_addr_t * addr) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _isisc_nat_prv_base_addr_get(dev_id, addr); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Set IP4 private base address on a particular device - * @param[in] dev_id device id - * @param[in] mask private base mask - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -isisc_nat_prv_base_mask_set(a_uint32_t dev_id, fal_ip4_addr_t mask) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _isisc_nat_prv_base_mask_set(dev_id, mask); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Get IP4 private base address on a particular device - * @param[in] dev_id device id - * @param[out] mask private base mask - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -isisc_nat_prv_base_mask_get(a_uint32_t dev_id, fal_ip4_addr_t * mask) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _isisc_nat_prv_base_mask_get(dev_id, mask); - HSL_API_UNLOCK; - return rv; -} - -#if 0 -/** - * @brief Set IP4 private base address on a particular device - * @details Comments: - Only 20bits is meaning which 20bits is determined by private address mode. - * @param[in] dev_id device id - * @param[in] addr private base address - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -isisc_nat_psr_prv_base_addr_set(a_uint32_t dev_id, fal_ip4_addr_t addr) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _isisc_nat_psr_prv_base_addr_set(dev_id, addr); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Get IP4 private base address on a particular device - * @param[in] dev_id device id - * @param[out] addr private base address - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -isisc_nat_psr_prv_base_addr_get(a_uint32_t dev_id, fal_ip4_addr_t * addr) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _isisc_nat_psr_prv_base_addr_get(dev_id, addr); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Set IP4 private base address mode on a particular device - * @details Comments: - If map_en equal true means bits31-20 bits15-8 are base address - else bits31-12 are base address. - * @param[in] dev_id device id - * @param[in] map_en private base mapping mode - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -isisc_nat_prv_addr_mode_set(a_uint32_t dev_id, a_bool_t map_en) -{ - sw_error_t rv = SW_OK; - - HSL_API_LOCK; - /*rv = _isisc_nat_prv_addr_mode_set(dev_id, map_en);*/ - HSL_API_UNLOCK; - return rv; -} -#endif - -/** - * @brief Get IP4 private base address mode on a particular device - * @param[in] dev_id device id - * @param[out] map_en private base mapping mode - * @return SW_OK or error code - */ -sw_error_t -isisc_nat_prv_addr_mode_get(a_uint32_t dev_id, a_bool_t * map_en) -{ - sw_error_t rv = SW_OK; - - HSL_API_LOCK; - /*rv = _isisc_nat_prv_addr_mode_get(dev_id, map_en);*/ - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Add one public address entry to one particular device. - * @details Comments: - Hardware entry id will be returned. - * @param[in] dev_id device id - * @param[in] entry public address entry parameter - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -isisc_nat_pub_addr_add(a_uint32_t dev_id, fal_nat_pub_addr_t * entry) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _isisc_nat_pub_addr_add(dev_id, entry); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Delete one public address entry from one particular device. - * @param[in] dev_id device id - * @param[in] del_mode delete operaton mode - * @param[in] entry public address entry parameter - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -isisc_nat_pub_addr_del(a_uint32_t dev_id, a_uint32_t del_mode, - fal_nat_pub_addr_t * entry) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _isisc_nat_pub_addr_del(dev_id, del_mode, entry); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Next public address entries from one particular device. - * @param[in] dev_id device id - * @param[in] next_mode next operaton mode - * @param[out] entry public address entry parameter - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -isisc_nat_pub_addr_next(a_uint32_t dev_id, a_uint32_t next_mode, - fal_nat_pub_addr_t * entry) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _isisc_nat_pub_addr_next(dev_id, next_mode, entry); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Set forwarding command for those packets miss NAT entries on a particular device. - * @param[in] dev_id device id - * @param[in] cmd forwarding command - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -isisc_nat_unk_session_cmd_set(a_uint32_t dev_id, fal_fwd_cmd_t cmd) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _isisc_nat_unk_session_cmd_set(dev_id, cmd); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Get forwarding command for those packets miss NAT entries on a particular device. - * @param[in] dev_id device id - * @param[out] cmd forwarding command - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -isisc_nat_unk_session_cmd_get(a_uint32_t dev_id, fal_fwd_cmd_t * cmd) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _isisc_nat_unk_session_cmd_get(dev_id, cmd); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Set working status of NAT engine on a particular device - * @param[in] dev_id device id - * @param[in] enable A_TRUE or A_FALSE - * @param[in] portbmp port bitmap - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -isisc_nat_global_set(a_uint32_t dev_id, a_bool_t enable, a_uint32_t portbmp) -{ - sw_error_t rv = SW_OK; - - HSL_API_LOCK; - printk("enable:%d\n", enable); - if(enable) { - if(isisc_nat_global_status == 0) { - isisc_nat_global_status = 1; -#if defined(IN_NAT_HELPER) - ISISC_NAT_HELPER_INIT(rv, dev_id, portbmp); -#endif - } - } else { - if(isisc_nat_global_status == 1) { - isisc_nat_global_status = 0; -#if defined(IN_NAT_HELPER) - ISISC_NAT_HELPER_CLEANUP(rv, dev_id); -#endif - } - } - //rv = SW_OK; - HSL_API_UNLOCK; - return rv; -} - -sw_error_t -isisc_nat_init(a_uint32_t dev_id) -{ - sw_error_t rv; - - HSL_DEV_ID_CHECK(dev_id); - - rv = isisc_nat_reset(dev_id); - SW_RTN_ON_ERROR(rv); - -#ifndef HSL_STANDALONG - { - hsl_api_t *p_api; - - SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id)); - - p_api->nat_add = isisc_nat_add; - p_api->nat_del = isisc_nat_del; - p_api->nat_get = isisc_nat_get; - p_api->nat_next = isisc_nat_next; - p_api->nat_counter_bind = isisc_nat_counter_bind; - p_api->napt_add = isisc_napt_add; - p_api->napt_del = isisc_napt_del; - p_api->napt_get = isisc_napt_get; - p_api->napt_next = isisc_napt_next; - p_api->napt_counter_bind = isisc_napt_counter_bind; - p_api->nat_status_set = isisc_nat_status_set; - p_api->nat_status_get = isisc_nat_status_get; - p_api->nat_hash_mode_set = isisc_nat_hash_mode_set; - p_api->nat_hash_mode_get = isisc_nat_hash_mode_get; - p_api->napt_status_set = isisc_napt_status_set; - p_api->napt_status_get = isisc_napt_status_get; - p_api->napt_mode_set = isisc_napt_mode_set; - p_api->napt_mode_get = isisc_napt_mode_get; - p_api->nat_pub_addr_add = isisc_nat_pub_addr_add; - p_api->nat_pub_addr_del = isisc_nat_pub_addr_del; - p_api->nat_pub_addr_next = isisc_nat_pub_addr_next; - p_api->nat_unk_session_cmd_set = isisc_nat_unk_session_cmd_set; - p_api->nat_unk_session_cmd_get = isisc_nat_unk_session_cmd_get; - p_api->nat_prv_base_addr_set = isisc_nat_prv_base_addr_set; - p_api->nat_prv_base_addr_get = isisc_nat_prv_base_addr_get; - p_api->nat_prv_base_mask_set = isisc_nat_prv_base_mask_set; - p_api->nat_prv_base_mask_get = isisc_nat_prv_base_mask_get; - p_api->nat_global_set = isisc_nat_global_set; - } -#endif - - return SW_OK; -} - -/** - * @} - */ diff --git a/feeds/ipq807x/qca-ssdk/src/src/hsl/isisc/isisc_port_ctrl.c b/feeds/ipq807x/qca-ssdk/src/src/hsl/isisc/isisc_port_ctrl.c deleted file mode 100755 index 2549b0d0a..000000000 --- a/feeds/ipq807x/qca-ssdk/src/src/hsl/isisc/isisc_port_ctrl.c +++ /dev/null @@ -1,2797 +0,0 @@ -/* - * Copyright (c) 2012, 2015-2018, The Linux Foundation. All rights reserved. - * Permission to use, copy, modify, and/or distribute this software for - * any purpose with or without fee is hereby granted, provided that the - * above copyright notice and this permission notice appear in all copies. - * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES - * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR - * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES - * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN - * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT - * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. - */ - - -/** - * @defgroup isisc_port_ctrl ISISC_PORT_CONTROL - * @{ - */ -#include "sw.h" -#include "hsl.h" -#include "hsl_dev.h" -#include "hsl_port_prop.h" -#include "isisc_port_ctrl.h" -#include "isisc_reg.h" -#include "hsl_phy.h" - -static a_bool_t -_isisc_port_phy_connected(a_uint32_t dev_id, fal_port_t port_id) -{ - if ((0 == port_id) || (6 == port_id)) - { - return A_FALSE; - } - else - { - return A_TRUE; - } -} - -static sw_error_t -_isisc_port_duplex_set(a_uint32_t dev_id, fal_port_t port_id, - fal_port_duplex_t duplex) -{ - sw_error_t rv; - a_uint32_t phy_id, reg_save, reg_val = 0, force, tmp; - hsl_phy_ops_t *phy_drv; - a_bool_t status; - - HSL_DEV_ID_CHECK(dev_id); - - if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU)) - { - return SW_BAD_PARAM; - } - - if (FAL_DUPLEX_BUTT <= duplex) - { - return SW_BAD_PARAM; - } - - HSL_REG_ENTRY_GET(rv, dev_id, PORT_STATUS, port_id, - (a_uint8_t *) (®_val), sizeof (a_uint32_t)); - SW_GET_FIELD_BY_REG(PORT_STATUS, DUPLEX_MODE, tmp, reg_val); - - /* for those ports without PHY device we set MAC register */ - if (A_FALSE == _isisc_port_phy_connected(dev_id, port_id)) - { - SW_SET_REG_BY_FIELD(PORT_STATUS, LINK_EN, 0, reg_val); - if (FAL_HALF_DUPLEX == duplex) - { - if (tmp == 0) - return SW_OK; - SW_SET_REG_BY_FIELD(PORT_STATUS, DUPLEX_MODE, 0, reg_val); - } - else - { - if (tmp == 1) - return SW_OK; - SW_SET_REG_BY_FIELD(PORT_STATUS, DUPLEX_MODE, 1, reg_val); - } - reg_save = reg_val; - } - else - { - SW_RTN_ON_NULL (phy_drv = hsl_phy_api_ops_get (dev_id, port_id)); - if (NULL == phy_drv->phy_duplex_set) - return SW_NOT_SUPPORTED; - /* hardware requirement: set mac be config by sw and turn off RX/TX MAC */ - rv = hsl_port_prop_get_phyid(dev_id, port_id, &phy_id); - SW_RTN_ON_ERROR(rv); - rv = phy_drv->phy_duplex_get (dev_id, phy_id, &tmp); - SW_RTN_ON_ERROR(rv); - status = phy_drv->phy_autoneg_status_get (dev_id, phy_id); - if ((tmp == duplex) && (status == A_FALSE)) - return SW_OK; - reg_save = reg_val; - SW_SET_REG_BY_FIELD(PORT_STATUS, LINK_EN, 0, reg_val); - SW_SET_REG_BY_FIELD(PORT_STATUS, RXMAC_EN, 0, reg_val); - SW_SET_REG_BY_FIELD(PORT_STATUS, TXMAC_EN, 0, reg_val); - - HSL_REG_ENTRY_SET(rv, dev_id, PORT_STATUS, port_id, - (a_uint8_t *) (®_val), sizeof (a_uint32_t)); - - rv = phy_drv->phy_duplex_set (dev_id, phy_id, duplex); - SW_RTN_ON_ERROR(rv); - - /* If MAC not in sync with PHY mode, the behavior is undefine. - You must be careful... */ - SW_GET_FIELD_BY_REG(PORT_STATUS, LINK_EN, force, reg_save); - if (!force) - { - if (FAL_HALF_DUPLEX == duplex) - { - SW_SET_REG_BY_FIELD(PORT_STATUS, DUPLEX_MODE, 0, reg_save); - } - else - { - SW_SET_REG_BY_FIELD(PORT_STATUS, DUPLEX_MODE, 1, reg_save); - } - } - } - - HSL_REG_ENTRY_SET(rv, dev_id, PORT_STATUS, port_id, - (a_uint8_t *) (®_save), sizeof (a_uint32_t)); - return rv; -} - -static sw_error_t -_isisc_port_speed_set(a_uint32_t dev_id, fal_port_t port_id, - fal_port_speed_t speed) -{ - sw_error_t rv; - a_uint32_t phy_id, reg_save, reg_val = 0, force, tmp; - hsl_phy_ops_t *phy_drv; - a_bool_t status; - - HSL_DEV_ID_CHECK(dev_id); - - if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU)) - { - return SW_BAD_PARAM; - } - - if (FAL_SPEED_1000 < speed) - { - return SW_BAD_PARAM; - } - - HSL_REG_ENTRY_GET(rv, dev_id, PORT_STATUS, port_id, - (a_uint8_t *) (®_val), sizeof (a_uint32_t)); - SW_GET_FIELD_BY_REG(PORT_STATUS, SPEED_MODE, tmp, reg_val); - - /* for those ports without PHY device we set MAC register */ - if (A_FALSE == _isisc_port_phy_connected(dev_id, port_id)) - { - SW_SET_REG_BY_FIELD(PORT_STATUS, LINK_EN, 0, reg_val); - if (FAL_SPEED_10 == speed) - { - if (tmp == 0) - return SW_OK; - SW_SET_REG_BY_FIELD(PORT_STATUS, SPEED_MODE, 0, reg_val); - } - else if (FAL_SPEED_100 == speed) - { - if (tmp == 1) - return SW_OK; - SW_SET_REG_BY_FIELD(PORT_STATUS, SPEED_MODE, 1, reg_val); - } - else - { - if (tmp == 2) - return SW_OK; - SW_SET_REG_BY_FIELD(PORT_STATUS, SPEED_MODE, 2, reg_val); - } - reg_save = reg_val; - - } - else - { - SW_RTN_ON_NULL (phy_drv = hsl_phy_api_ops_get (dev_id, port_id)); - if (NULL == phy_drv->phy_speed_set) - return SW_NOT_SUPPORTED; - /* hardware requirement: set mac be config by sw and turn off RX/TX MAC */ - rv = hsl_port_prop_get_phyid(dev_id, port_id, &phy_id); - SW_RTN_ON_ERROR(rv); - rv = phy_drv->phy_speed_get (dev_id, phy_id, &tmp); - SW_RTN_ON_ERROR(rv); - status = phy_drv->phy_autoneg_status_get (dev_id, phy_id); - if ((tmp == speed) && (status == A_FALSE)) - return SW_OK; - reg_save = reg_val; - SW_SET_REG_BY_FIELD(PORT_STATUS, LINK_EN, 0, reg_val); - SW_SET_REG_BY_FIELD(PORT_STATUS, RXMAC_EN, 0, reg_val); - SW_SET_REG_BY_FIELD(PORT_STATUS, TXMAC_EN, 0, reg_val); - - HSL_REG_ENTRY_SET(rv, dev_id, PORT_STATUS, port_id, - (a_uint8_t *) (®_val), sizeof (a_uint32_t)); - - - rv = phy_drv->phy_speed_set (dev_id, phy_id, speed); - SW_RTN_ON_ERROR(rv); - - /* If MAC not in sync with PHY mode, the behavior is undefine. - You must be careful... */ - SW_GET_FIELD_BY_REG(PORT_STATUS, LINK_EN, force, reg_save); - if (!force) - { - if (FAL_SPEED_10 == speed) - { - SW_SET_REG_BY_FIELD(PORT_STATUS, SPEED_MODE, 0, reg_save); - } - else if (FAL_SPEED_100 == speed) - { - SW_SET_REG_BY_FIELD(PORT_STATUS, SPEED_MODE, 1, reg_save); - } - else - { - SW_SET_REG_BY_FIELD(PORT_STATUS, SPEED_MODE, 2, reg_save); - } - } - } - - HSL_REG_ENTRY_SET(rv, dev_id, PORT_STATUS, port_id, - (a_uint8_t *) (®_save), sizeof (a_uint32_t)); - return rv; -} - -static sw_error_t -_isisc_port_flowctrl_set(a_uint32_t dev_id, fal_port_t port_id, a_bool_t enable) -{ - sw_error_t rv; - a_uint32_t val, force, reg = 0, tmp; - - if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU)) - { - return SW_BAD_PARAM; - } - - if (A_TRUE == enable) - { - val = 1; - } - else if (A_FALSE == enable) - { - val = 0; - } - else - { - return SW_BAD_PARAM; - } - - HSL_REG_ENTRY_GET(rv, dev_id, PORT_STATUS, port_id, - (a_uint8_t *) (®), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - - SW_GET_FIELD_BY_REG(PORT_STATUS, FLOW_LINK_EN, force, reg); - if (force) - { - /* flow control isn't in force mode so can't set */ - return SW_DISABLE; - } - tmp = reg; - - SW_SET_REG_BY_FIELD(PORT_STATUS, RX_FLOW_EN, val, reg); - SW_SET_REG_BY_FIELD(PORT_STATUS, TX_FLOW_EN, val, reg); - SW_SET_REG_BY_FIELD(PORT_STATUS, TX_HALF_FLOW_EN, val, reg); - if (tmp == reg) - return SW_OK; - - HSL_REG_ENTRY_SET(rv, dev_id, PORT_STATUS, port_id, - (a_uint8_t *) (®), sizeof (a_uint32_t)); - return rv; -} - -static sw_error_t -_isisc_port_flowctrl_forcemode_set(a_uint32_t dev_id, fal_port_t port_id, - a_bool_t enable) -{ - sw_error_t rv; - a_uint32_t reg = 0, tmp; - - if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU)) - { - return SW_BAD_PARAM; - } - - HSL_REG_ENTRY_GET(rv, dev_id, PORT_STATUS, port_id, - (a_uint8_t *) (®), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - SW_GET_FIELD_BY_REG(PORT_STATUS, FLOW_LINK_EN, tmp, reg); - - if (A_TRUE == enable) - { - if (tmp == 0) - return SW_OK; - SW_SET_REG_BY_FIELD(PORT_STATUS, FLOW_LINK_EN, 0, reg); - } - else if (A_FALSE == enable) - { - /* for those ports without PHY, it can't sync flow control status */ - if (A_FALSE == _isisc_port_phy_connected(dev_id, port_id)) - { - return SW_DISABLE; - } - if (tmp == 1) - return SW_OK; - SW_SET_REG_BY_FIELD(PORT_STATUS, FLOW_LINK_EN, 1, reg); - } - else - { - return SW_BAD_PARAM; - } - - HSL_REG_ENTRY_SET(rv, dev_id, PORT_STATUS, port_id, - (a_uint8_t *) (®), sizeof (a_uint32_t)); - return rv; -} - -static sw_error_t -_isisc_port_speed_get(a_uint32_t dev_id, fal_port_t port_id, - fal_port_speed_t * pspeed) -{ - sw_error_t rv = SW_OK; - a_uint32_t phy_id; - hsl_phy_ops_t *phy_drv; - - HSL_DEV_ID_CHECK(dev_id); - - if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU)) - { - return SW_BAD_PARAM; - } - /* for those ports without PHY device supposed always 1000Mbps */ - if (A_FALSE == _isisc_port_phy_connected(dev_id, port_id)) - { - *pspeed = FAL_SPEED_1000; - } - else - { - SW_RTN_ON_NULL (phy_drv = hsl_phy_api_ops_get (dev_id, port_id)); - if (NULL == phy_drv->phy_speed_get) - return SW_NOT_SUPPORTED; - - rv = hsl_port_prop_get_phyid (dev_id, port_id, &phy_id); - SW_RTN_ON_ERROR (rv); - - rv = phy_drv->phy_speed_get (dev_id, phy_id, pspeed); - SW_RTN_ON_ERROR (rv); - } -#if 0 - HSL_REG_ENTRY_GET(rv, dev_id, PORT_STATUS, port_id, - (a_uint8_t *) (®), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - - SW_GET_FIELD_BY_REG(PORT_STATUS, SPEED_MODE, field, reg); - if (0 == field) - { - *pspeed = FAL_SPEED_10; - } - else if (1 == field) - { - *pspeed = FAL_SPEED_100; - } - else if (2 == field) - { - *pspeed = FAL_SPEED_1000; - } - else - { - *pspeed = FAL_SPEED_BUTT; - rv = SW_READ_ERROR; - } -#endif - return rv; -} -static sw_error_t -_isisc_port_duplex_get(a_uint32_t dev_id, fal_port_t port_id, - fal_port_duplex_t * pduplex) -{ - sw_error_t rv = SW_OK; - a_uint32_t phy_id; - hsl_phy_ops_t *phy_drv; - - HSL_DEV_ID_CHECK(dev_id); - - if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU)) - { - return SW_BAD_PARAM; - } - - /* for those ports without PHY device supposed always full */ - if (A_FALSE == _isisc_port_phy_connected(dev_id, port_id)) - { - *pduplex = FAL_FULL_DUPLEX; - } - else - { - SW_RTN_ON_NULL (phy_drv = hsl_phy_api_ops_get (dev_id, port_id)); - if (NULL == phy_drv->phy_duplex_get) - return SW_NOT_SUPPORTED; - - rv = hsl_port_prop_get_phyid (dev_id, port_id, &phy_id); - SW_RTN_ON_ERROR (rv); - - rv = phy_drv->phy_duplex_get (dev_id, phy_id, pduplex); - SW_RTN_ON_ERROR (rv); - } -#if 0 - HSL_REG_ENTRY_GET(rv, dev_id, PORT_STATUS, port_id, - (a_uint8_t *) (®), sizeof (a_uint32_t)); - SW_GET_FIELD_BY_REG(PORT_STATUS, DUPLEX_MODE, field, reg); - if (field) - { - *pduplex = FAL_FULL_DUPLEX; - } - else - { - *pduplex = FAL_HALF_DUPLEX; - } -#endif - return rv; -} - -static sw_error_t -_isisc_port_autoneg_restart(a_uint32_t dev_id, fal_port_t port_id) -{ - sw_error_t rv; - a_uint32_t phy_id; - hsl_phy_ops_t *phy_drv; - - HSL_DEV_ID_CHECK(dev_id); - - if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_PHY)) - { - return SW_BAD_PARAM; - } - - SW_RTN_ON_NULL (phy_drv = hsl_phy_api_ops_get (dev_id, port_id)); - if (NULL == phy_drv->phy_restart_autoneg) - return SW_NOT_SUPPORTED; - - rv = hsl_port_prop_get_phyid(dev_id, port_id, &phy_id); - SW_RTN_ON_ERROR(rv); - - rv = phy_drv->phy_restart_autoneg (dev_id, phy_id); - return rv; -} - -static sw_error_t -_isisc_port_autoneg_adv_set(a_uint32_t dev_id, fal_port_t port_id, - a_uint32_t autoadv) -{ - sw_error_t rv; - a_uint32_t phy_id; - hsl_phy_ops_t *phy_drv; - - HSL_DEV_ID_CHECK(dev_id); - - if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_PHY)) - { - return SW_BAD_PARAM; - } - - SW_RTN_ON_NULL (phy_drv = hsl_phy_api_ops_get (dev_id, port_id)); - if (NULL == phy_drv->phy_autoneg_adv_set) - return SW_NOT_SUPPORTED; - - rv = hsl_port_prop_get_phyid(dev_id, port_id, &phy_id); - SW_RTN_ON_ERROR(rv); - - rv = phy_drv->phy_autoneg_adv_set (dev_id, phy_id, autoadv); - SW_RTN_ON_ERROR(rv); - - return SW_OK; -} - -static sw_error_t -_isisc_port_autoneg_status_get(a_uint32_t dev_id, fal_port_t port_id, - a_bool_t * status) -{ - a_uint32_t phy_id; - sw_error_t rv; - hsl_phy_ops_t *phy_drv; - - HSL_DEV_ID_CHECK(dev_id); - - if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_PHY)) - { - return SW_BAD_PARAM; - } - - SW_RTN_ON_NULL (phy_drv = hsl_phy_api_ops_get (dev_id, port_id)); - if (NULL == phy_drv->phy_autoneg_status_get) - return SW_NOT_SUPPORTED; - - rv = hsl_port_prop_get_phyid(dev_id, port_id, &phy_id); - SW_RTN_ON_ERROR(rv); - - *status = phy_drv->phy_autoneg_status_get (dev_id, phy_id); - - return SW_OK; -} - -static sw_error_t -_isisc_port_autoneg_enable(a_uint32_t dev_id, fal_port_t port_id) -{ - sw_error_t rv; - a_uint32_t phy_id; - hsl_phy_ops_t *phy_drv; - - HSL_DEV_ID_CHECK(dev_id); - - if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_PHY)) - { - return SW_BAD_PARAM; - } - - SW_RTN_ON_NULL (phy_drv = hsl_phy_api_ops_get (dev_id, port_id)); - if (NULL == phy_drv->phy_autoneg_enable_set) - return SW_NOT_SUPPORTED; - - rv = hsl_port_prop_get_phyid(dev_id, port_id, &phy_id); - SW_RTN_ON_ERROR(rv); - - rv = phy_drv->phy_autoneg_enable_set (dev_id, phy_id); - return rv; -} - - -static sw_error_t -_isisc_port_autoneg_adv_get(a_uint32_t dev_id, fal_port_t port_id, - a_uint32_t * autoadv) -{ - sw_error_t rv; - a_uint32_t phy_id; - hsl_phy_ops_t *phy_drv; - - HSL_DEV_ID_CHECK(dev_id); - - if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_PHY)) - { - return SW_BAD_PARAM; - } - - SW_RTN_ON_NULL (phy_drv = hsl_phy_api_ops_get (dev_id, port_id)); - if (NULL == phy_drv->phy_autoneg_adv_get) - return SW_NOT_SUPPORTED; - - rv = hsl_port_prop_get_phyid(dev_id, port_id, &phy_id); - SW_RTN_ON_ERROR(rv); - - *autoadv = 0; - rv = phy_drv->phy_autoneg_adv_get (dev_id, phy_id, autoadv); - SW_RTN_ON_ERROR(rv); - - return SW_OK; -} - - -#ifndef IN_PORTCONTROL_MINI -static sw_error_t -_isisc_port_flowctrl_get(a_uint32_t dev_id, fal_port_t port_id, - a_bool_t * enable) -{ - sw_error_t rv; - a_uint32_t rx, reg = 0; - - if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU)) - { - return SW_BAD_PARAM; - } - - HSL_REG_ENTRY_GET(rv, dev_id, PORT_STATUS, port_id, - (a_uint8_t *) (®), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - - SW_GET_FIELD_BY_REG(PORT_STATUS, RX_FLOW_EN, rx, reg); - - if (1 == rx) - { - *enable = A_TRUE; - } - else - { - *enable = A_FALSE; - } - - return SW_OK; -} - - -static sw_error_t -_isisc_port_flowctrl_forcemode_get(a_uint32_t dev_id, fal_port_t port_id, - a_bool_t * enable) -{ - sw_error_t rv; - a_uint32_t force, reg; - - if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU)) - { - return SW_BAD_PARAM; - } - - HSL_REG_ENTRY_GET(rv, dev_id, PORT_STATUS, port_id, - (a_uint8_t *) (®), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - - SW_GET_FIELD_BY_REG(PORT_STATUS, FLOW_LINK_EN, force, reg); - if (0 == force) - { - *enable = A_TRUE; - } - else - { - *enable = A_FALSE; - } - - return SW_OK; -} - -static sw_error_t -_isisc_port_powersave_set(a_uint32_t dev_id, fal_port_t port_id, a_bool_t enable) -{ - sw_error_t rv; - a_uint32_t phy_id = 0; - hsl_phy_ops_t *phy_drv; - - HSL_DEV_ID_CHECK(dev_id); - - if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_PHY)) - { - return SW_BAD_PARAM; - } - - SW_RTN_ON_NULL (phy_drv = hsl_phy_api_ops_get (dev_id, port_id)); - if (NULL == phy_drv->phy_powersave_set) - return SW_NOT_SUPPORTED; - - rv = hsl_port_prop_get_phyid(dev_id, port_id, &phy_id); - SW_RTN_ON_ERROR(rv); - - rv = phy_drv->phy_powersave_set (dev_id, phy_id, enable); - - return rv; -} - -static sw_error_t -_isisc_port_powersave_get(a_uint32_t dev_id, fal_port_t port_id, - a_bool_t * enable) -{ - sw_error_t rv; - a_uint32_t phy_id = 0; - hsl_phy_ops_t *phy_drv; - - HSL_DEV_ID_CHECK(dev_id); - - if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_PHY)) - { - return SW_BAD_PARAM; - } - - SW_RTN_ON_NULL (phy_drv = hsl_phy_api_ops_get (dev_id, port_id)); - if (NULL == phy_drv->phy_powersave_get) - return SW_NOT_SUPPORTED; - - rv = hsl_port_prop_get_phyid(dev_id, port_id, &phy_id); - SW_RTN_ON_ERROR(rv); - - rv = phy_drv->phy_powersave_get (dev_id, phy_id, enable); - - return rv; -} - -static sw_error_t -_isisc_port_hibernate_set(a_uint32_t dev_id, fal_port_t port_id, a_bool_t enable) -{ - sw_error_t rv; - a_uint32_t phy_id = 0; - hsl_phy_ops_t *phy_drv; - - HSL_DEV_ID_CHECK(dev_id); - - if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_PHY)) - { - return SW_BAD_PARAM; - } - - SW_RTN_ON_NULL (phy_drv = hsl_phy_api_ops_get (dev_id, port_id)); - if (NULL == phy_drv->phy_hibernation_set) - return SW_NOT_SUPPORTED; - - rv = hsl_port_prop_get_phyid(dev_id, port_id, &phy_id); - SW_RTN_ON_ERROR(rv); - - rv = phy_drv->phy_hibernation_set (dev_id, phy_id, enable); - - return rv; -} - -static sw_error_t -_isisc_port_hibernate_get(a_uint32_t dev_id, fal_port_t port_id, - a_bool_t * enable) -{ - sw_error_t rv; - a_uint32_t phy_id = 0; - hsl_phy_ops_t *phy_drv; - - HSL_DEV_ID_CHECK(dev_id); - - if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_PHY)) - { - return SW_BAD_PARAM; - } - - SW_RTN_ON_NULL (phy_drv = hsl_phy_api_ops_get (dev_id, port_id)); - if (NULL == phy_drv->phy_hibernation_get) - return SW_NOT_SUPPORTED; - - rv = hsl_port_prop_get_phyid(dev_id, port_id, &phy_id); - SW_RTN_ON_ERROR(rv); - - rv = phy_drv->phy_hibernation_get (dev_id, phy_id, enable); - - return rv; -} - -static sw_error_t -_isisc_port_cdt(a_uint32_t dev_id, fal_port_t port_id, a_uint32_t mdi_pair, - fal_cable_status_t * cable_status, a_uint32_t * cable_len) -{ - sw_error_t rv; - a_uint32_t phy_id = 0; - hsl_phy_ops_t *phy_drv; - - HSL_DEV_ID_CHECK(dev_id); - - if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_PHY)) - { - return SW_BAD_PARAM; - } - - SW_RTN_ON_NULL (phy_drv = hsl_phy_api_ops_get (dev_id, port_id)); - if (NULL == phy_drv->phy_cdt) - return SW_NOT_SUPPORTED; - - rv = hsl_port_prop_get_phyid(dev_id, port_id, &phy_id); - SW_RTN_ON_ERROR(rv); - - rv = phy_drv->phy_cdt (dev_id, phy_id, mdi_pair, cable_status, cable_len); - - return rv; -} - -static sw_error_t -_isisc_port_phy_id_get (a_uint32_t dev_id, fal_port_t port_id, - a_uint16_t * org_id, a_uint16_t * rev_id) -{ - sw_error_t rv; - a_uint32_t phy_id = 0; - hsl_phy_ops_t *phy_drv; - a_uint32_t phy_data; - - HSL_DEV_ID_CHECK (dev_id); - - if (A_TRUE != hsl_port_prop_check (dev_id, port_id, HSL_PP_PHY)) - { - return SW_BAD_PARAM; - } - - SW_RTN_ON_NULL (phy_drv = hsl_phy_api_ops_get (dev_id, port_id)); - if (NULL == phy_drv->phy_id_get) - return SW_NOT_SUPPORTED; - - rv = hsl_port_prop_get_phyid (dev_id, port_id, &phy_id); - SW_RTN_ON_ERROR (rv); - - rv = phy_drv->phy_id_get (dev_id, phy_id, &phy_data); - SW_RTN_ON_ERROR (rv); - - *org_id = (phy_data >> 16) & 0xffff; - *rev_id = phy_data & 0xffff; - - return rv; -} - -static sw_error_t -_isisc_port_8023az_set (a_uint32_t dev_id, fal_port_t port_id, a_bool_t enable) -{ - sw_error_t rv; - a_uint32_t phy_id = 0; - hsl_phy_ops_t *phy_drv; - - HSL_DEV_ID_CHECK (dev_id); - if (A_TRUE != hsl_port_prop_check (dev_id, port_id, HSL_PP_PHY)) - { - return SW_BAD_PARAM; - } - - SW_RTN_ON_NULL (phy_drv = hsl_phy_api_ops_get (dev_id, port_id)); - if (NULL == phy_drv->phy_8023az_set) - return SW_NOT_SUPPORTED; - - rv = hsl_port_prop_get_phyid (dev_id, port_id, &phy_id); - SW_RTN_ON_ERROR (rv); - - rv = phy_drv->phy_8023az_set (dev_id, phy_id, enable); - - return rv; -} - -static sw_error_t -_isisc_port_8023az_get (a_uint32_t dev_id, fal_port_t port_id, - a_bool_t * enable) -{ - sw_error_t rv; - a_uint32_t phy_id = 0; - hsl_phy_ops_t *phy_drv; - - HSL_DEV_ID_CHECK (dev_id); - - if (A_TRUE != hsl_port_prop_check (dev_id, port_id, HSL_PP_PHY)) - { - return SW_BAD_PARAM; - } - - SW_RTN_ON_NULL (phy_drv = hsl_phy_api_ops_get (dev_id, port_id)); - if (NULL == phy_drv->phy_8023az_get) - return SW_NOT_SUPPORTED; - - rv = hsl_port_prop_get_phyid (dev_id, port_id, &phy_id); - SW_RTN_ON_ERROR (rv); - - rv = phy_drv->phy_8023az_get (dev_id, phy_id, enable); - - return rv; -} - -static sw_error_t -_isisc_port_local_loopback_set(a_uint32_t dev_id, a_uint32_t port_id, - a_bool_t enable) -{ - sw_error_t rv; - a_uint32_t phy_id = 0; - hsl_phy_ops_t *phy_drv; - - HSL_DEV_ID_CHECK (dev_id); - if (A_TRUE != hsl_port_prop_check (dev_id, port_id, HSL_PP_PHY)) - { - return SW_BAD_PARAM; - } - - SW_RTN_ON_NULL (phy_drv = hsl_phy_api_ops_get (dev_id, port_id)); - if (NULL == phy_drv->phy_local_loopback_set) - { - return SW_NOT_SUPPORTED; - } - - rv = hsl_port_prop_get_phyid (dev_id, port_id, &phy_id); - SW_RTN_ON_ERROR (rv); - - rv = phy_drv->phy_local_loopback_set (dev_id, phy_id, enable); - - return rv; -} - -static sw_error_t -_isisc_port_local_loopback_get(a_uint32_t dev_id, a_uint32_t port_id, - a_bool_t *enable) -{ - sw_error_t rv; - a_uint32_t phy_id = 0; - hsl_phy_ops_t *phy_drv; - - HSL_DEV_ID_CHECK (dev_id); - if (A_TRUE != hsl_port_prop_check (dev_id, port_id, HSL_PP_PHY)) - { - return SW_BAD_PARAM; - } - - SW_RTN_ON_NULL (phy_drv = hsl_phy_api_ops_get (dev_id, port_id)); - if (NULL == phy_drv->phy_local_loopback_set) - { - return SW_NOT_SUPPORTED; - } - - rv = hsl_port_prop_get_phyid (dev_id, port_id, &phy_id); - SW_RTN_ON_ERROR (rv); - - rv = phy_drv->phy_local_loopback_get (dev_id, phy_id, enable); - - return rv; -} - -static sw_error_t -_isisc_port_remote_loopback_set(a_uint32_t dev_id, a_uint32_t port_id, - a_bool_t enable) -{ - sw_error_t rv; - a_uint32_t phy_id = 0; - hsl_phy_ops_t *phy_drv; - - HSL_DEV_ID_CHECK (dev_id); - if (A_TRUE != hsl_port_prop_check (dev_id, port_id, HSL_PP_PHY)) - { - return SW_BAD_PARAM; - } - - SW_RTN_ON_NULL (phy_drv = hsl_phy_api_ops_get (dev_id, port_id)); - if (NULL == phy_drv->phy_remote_loopback_set) - { - return SW_NOT_SUPPORTED; - } - - rv = hsl_port_prop_get_phyid (dev_id, port_id, &phy_id); - SW_RTN_ON_ERROR (rv); - - rv = phy_drv->phy_remote_loopback_set (dev_id, phy_id, enable); - - return rv; -} - -static sw_error_t -_isisc_port_remote_loopback_get(a_uint32_t dev_id, a_uint32_t port_id, - a_bool_t *enable) -{ - sw_error_t rv; - a_uint32_t phy_id = 0; - hsl_phy_ops_t *phy_drv; - - HSL_DEV_ID_CHECK (dev_id); - if (A_TRUE != hsl_port_prop_check (dev_id, port_id, HSL_PP_PHY)) - { - return SW_BAD_PARAM; - } - - SW_RTN_ON_NULL (phy_drv = hsl_phy_api_ops_get (dev_id, port_id)); - if (NULL == phy_drv->phy_remote_loopback_set) - { - return SW_NOT_SUPPORTED; - } - - rv = hsl_port_prop_get_phyid (dev_id, port_id, &phy_id); - SW_RTN_ON_ERROR (rv); - - rv = phy_drv->phy_remote_loopback_get (dev_id, phy_id, enable); - - return rv; -} - -#endif -static sw_error_t -_isisc_port_rxhdr_mode_set(a_uint32_t dev_id, fal_port_t port_id, - fal_port_header_mode_t mode) -{ - sw_error_t rv; - a_uint32_t val = 0; - - HSL_DEV_ID_CHECK(dev_id); - - if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU)) - { - return SW_BAD_PARAM; - } - - if (FAL_NO_HEADER_EN == mode) - { - val = 0; - } - else if (FAL_ONLY_MANAGE_FRAME_EN == mode) - { - val = 1; - } - else if (FAL_ALL_TYPE_FRAME_EN == mode) - { - val = 2; - } - else - { - return SW_BAD_PARAM; - } - - HSL_REG_FIELD_SET(rv, dev_id, PORT_HDR_CTL, port_id, RXHDR_MODE, - (a_uint8_t *) (&val), sizeof (a_uint32_t)); - return rv; -} -#ifndef IN_PORTCONTROL_MINI -static sw_error_t -_isisc_port_rxhdr_mode_get(a_uint32_t dev_id, fal_port_t port_id, - fal_port_header_mode_t * mode) -{ - sw_error_t rv; - a_uint32_t val; - - HSL_DEV_ID_CHECK(dev_id); - - if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU)) - { - return SW_BAD_PARAM; - } - - HSL_REG_FIELD_GET(rv, dev_id, PORT_HDR_CTL, port_id, RXHDR_MODE, - (a_uint8_t *) (&val), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - - if (1 == val) - { - *mode = FAL_ONLY_MANAGE_FRAME_EN; - } - else if (2 == val) - { - *mode = FAL_ALL_TYPE_FRAME_EN; - } - else - { - *mode = FAL_NO_HEADER_EN; - } - - return SW_OK; -} -#endif -static sw_error_t -_isisc_port_txhdr_mode_set(a_uint32_t dev_id, fal_port_t port_id, - fal_port_header_mode_t mode) -{ - sw_error_t rv; - a_uint32_t val = 0; - - HSL_DEV_ID_CHECK(dev_id); - - if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU)) - { - return SW_BAD_PARAM; - } - - if (FAL_NO_HEADER_EN == mode) - { - val = 0; - } - else if (FAL_ONLY_MANAGE_FRAME_EN == mode) - { - val = 1; - } - else if (FAL_ALL_TYPE_FRAME_EN == mode) - { - val = 2; - } - else - { - return SW_BAD_PARAM; - } - - HSL_REG_FIELD_SET(rv, dev_id, PORT_HDR_CTL, port_id, TXHDR_MODE, - (a_uint8_t *) (&val), sizeof (a_uint32_t)); - return rv; -} -#ifndef IN_PORTCONTROL_MINI -static sw_error_t -_isisc_port_txhdr_mode_get(a_uint32_t dev_id, fal_port_t port_id, - fal_port_header_mode_t * mode) -{ - sw_error_t rv; - a_uint32_t val; - - HSL_DEV_ID_CHECK(dev_id); - - if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU)) - { - return SW_BAD_PARAM; - } - - HSL_REG_FIELD_GET(rv, dev_id, PORT_HDR_CTL, port_id, TXHDR_MODE, - (a_uint8_t *) (&val), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - - if (1 == val) - { - *mode = FAL_ONLY_MANAGE_FRAME_EN; - } - else if (2 == val) - { - *mode = FAL_ALL_TYPE_FRAME_EN; - } - else - { - *mode = FAL_NO_HEADER_EN; - } - - return SW_OK; -} -#endif -static sw_error_t -_isisc_header_type_set(a_uint32_t dev_id, a_bool_t enable, a_uint32_t type) -{ - a_uint32_t reg = 0; - sw_error_t rv; - - HSL_DEV_ID_CHECK(dev_id); - - HSL_REG_ENTRY_GET(rv, dev_id, HEADER_CTL, 0, - (a_uint8_t *) (®), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - - if (A_TRUE == enable) - { - if (0xffff < type) - { - return SW_BAD_PARAM; - } - SW_SET_REG_BY_FIELD(HEADER_CTL, TYPE_LEN, 1, reg); - SW_SET_REG_BY_FIELD(HEADER_CTL, TYPE_VAL, type, reg); - } - else if (A_FALSE == enable) - { - SW_SET_REG_BY_FIELD(HEADER_CTL, TYPE_LEN, 0, reg); - SW_SET_REG_BY_FIELD(HEADER_CTL, TYPE_VAL, 0, reg); - } - else - { - return SW_BAD_PARAM; - } - - HSL_REG_ENTRY_SET(rv, dev_id, HEADER_CTL, 0, - (a_uint8_t *) (®), sizeof (a_uint32_t)); - return rv; -} -#ifndef IN_PORTCONTROL_MINI -static sw_error_t -_isisc_header_type_get(a_uint32_t dev_id, a_bool_t * enable, a_uint32_t * type) -{ - a_uint32_t data, reg = 0; - sw_error_t rv; - - HSL_DEV_ID_CHECK(dev_id); - - HSL_REG_ENTRY_GET(rv, dev_id, HEADER_CTL, 0, - (a_uint8_t *) (®), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - - SW_GET_FIELD_BY_REG(HEADER_CTL, TYPE_LEN, data, reg); - if (data) - { - SW_GET_FIELD_BY_REG(HEADER_CTL, TYPE_VAL, data, reg); - *enable = A_TRUE; - *type = data; - } - else - { - *enable = A_FALSE; - *type = 0; - } - - return SW_OK; -} -#endif -static sw_error_t -_isisc_port_txmac_status_set(a_uint32_t dev_id, fal_port_t port_id, a_bool_t enable) -{ - sw_error_t rv; - a_uint32_t reg, force, val = 0, tmp; - - HSL_DEV_ID_CHECK(dev_id); - - if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU)) - { - return SW_BAD_PARAM; - } - - HSL_REG_ENTRY_GET(rv, dev_id, PORT_STATUS, port_id, - (a_uint8_t *) (®), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - - if (A_TRUE == enable) - { - val = 1; - } - else if (A_FALSE == enable) - { - val = 0; - } - else - { - return SW_BAD_PARAM; - } - tmp = reg; - - /* for those ports without PHY device we set MAC register */ - if (A_FALSE == _isisc_port_phy_connected(dev_id, port_id)) - { - SW_SET_REG_BY_FIELD(PORT_STATUS, LINK_EN, 0, reg); - SW_SET_REG_BY_FIELD(PORT_STATUS, TXMAC_EN, val, reg); - } - else - { - SW_GET_FIELD_BY_REG(PORT_STATUS, LINK_EN, force, reg); - if (force) - { - /* link isn't in force mode so can't set */ - return SW_DISABLE; - } - else - { - SW_SET_REG_BY_FIELD(PORT_STATUS, TXMAC_EN, val, reg); - } - } - if (tmp == reg) - return SW_OK; - HSL_REG_ENTRY_SET(rv, dev_id, PORT_STATUS, port_id, - (a_uint8_t *) (®), sizeof (a_uint32_t)); - return rv; -} -#ifndef IN_PORTCONTROL_MINI -static sw_error_t -_isisc_port_txmac_status_get(a_uint32_t dev_id, fal_port_t port_id, a_bool_t * enable) -{ - sw_error_t rv; - a_uint32_t val = 0; - - HSL_DEV_ID_CHECK(dev_id); - - if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU)) - { - return SW_BAD_PARAM; - } - - HSL_REG_FIELD_GET(rv, dev_id, PORT_STATUS, port_id, TXMAC_EN, - (a_uint8_t *) (&val), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - - if (val) - { - *enable = A_TRUE; - } - else - { - *enable = A_FALSE; - } - - return SW_OK; -} -#endif -static sw_error_t -_isisc_port_rxmac_status_set(a_uint32_t dev_id, fal_port_t port_id, a_bool_t enable) -{ - sw_error_t rv; - a_uint32_t reg = 0, force, val = 0, tmp; - - HSL_DEV_ID_CHECK(dev_id); - - if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU)) - { - return SW_BAD_PARAM; - } - - HSL_REG_ENTRY_GET(rv, dev_id, PORT_STATUS, port_id, - (a_uint8_t *) (®), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - - if (A_TRUE == enable) - { - val = 1; - } - else if (A_FALSE == enable) - { - val = 0; - } - else - { - return SW_BAD_PARAM; - } - tmp = reg; - - /* for those ports without PHY device we set MAC register */ - if (A_FALSE == _isisc_port_phy_connected(dev_id, port_id)) - { - SW_SET_REG_BY_FIELD(PORT_STATUS, LINK_EN, 0, reg); - SW_SET_REG_BY_FIELD(PORT_STATUS, RXMAC_EN, val, reg); - } - else - { - SW_GET_FIELD_BY_REG(PORT_STATUS, LINK_EN, force, reg); - if (force) - { - /* link isn't in force mode so can't set */ - return SW_DISABLE; - } - else - { - SW_SET_REG_BY_FIELD(PORT_STATUS, RXMAC_EN, val, reg); - } - } - if (tmp == reg) - return SW_OK; - HSL_REG_ENTRY_SET(rv, dev_id, PORT_STATUS, port_id, - (a_uint8_t *) (®), sizeof (a_uint32_t)); - return rv; -} -#ifndef IN_PORTCONTROL_MINI -static sw_error_t -_isisc_port_rxmac_status_get(a_uint32_t dev_id, fal_port_t port_id, a_bool_t * enable) -{ - sw_error_t rv; - a_uint32_t val; - - HSL_DEV_ID_CHECK(dev_id); - - if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU)) - { - return SW_BAD_PARAM; - } - - HSL_REG_FIELD_GET(rv, dev_id, PORT_STATUS, port_id, RXMAC_EN, - (a_uint8_t *) (&val), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - - if (val) - { - *enable = A_TRUE; - } - else - { - *enable = A_FALSE; - } - - return SW_OK; -} -#endif -static sw_error_t -_isisc_port_txfc_status_set(a_uint32_t dev_id, fal_port_t port_id, a_bool_t enable) -{ - sw_error_t rv; - a_uint32_t val, reg = 0, force, tmp; - - HSL_DEV_ID_CHECK(dev_id); - - if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU)) - { - return SW_BAD_PARAM; - } - - if (A_TRUE == enable) - { - val = 1; - } - else if (A_FALSE == enable) - { - val = 0; - } - else - { - return SW_BAD_PARAM; - } - - HSL_REG_ENTRY_GET(rv, dev_id, PORT_STATUS, port_id, - (a_uint8_t *) (®), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - tmp = reg; - - /* for those ports without PHY device we set MAC register */ - if (A_FALSE == _isisc_port_phy_connected(dev_id, port_id)) - { - SW_SET_REG_BY_FIELD(PORT_STATUS, FLOW_LINK_EN, 0, reg); - SW_SET_REG_BY_FIELD(PORT_STATUS, TX_FLOW_EN, val, reg); - } - else - { - SW_GET_FIELD_BY_REG(PORT_STATUS, FLOW_LINK_EN, force, reg); - if (force) - { - /* flow control isn't in force mode so can't set */ - return SW_DISABLE; - } - else - { - SW_SET_REG_BY_FIELD(PORT_STATUS, TX_FLOW_EN, val, reg); - } - } - if (tmp == reg) - return SW_OK; - HSL_REG_ENTRY_SET(rv, dev_id, PORT_STATUS, port_id, - (a_uint8_t *) (®), sizeof (a_uint32_t)); - return rv; -} - -static sw_error_t -_isisc_port_txfc_status_get(a_uint32_t dev_id, fal_port_t port_id, a_bool_t * enable) -{ - sw_error_t rv; - a_uint32_t val; - - HSL_DEV_ID_CHECK(dev_id); - - if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU)) - { - return SW_BAD_PARAM; - } - - HSL_REG_FIELD_GET(rv, dev_id, PORT_STATUS, port_id, TX_FLOW_EN, - (a_uint8_t *) (&val), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - - if (val) - { - *enable = A_TRUE; - } - else - { - *enable = A_FALSE; - } - - return SW_OK; -} - -static sw_error_t -_isisc_port_rxfc_status_set(a_uint32_t dev_id, fal_port_t port_id, a_bool_t enable) -{ - sw_error_t rv; - a_uint32_t val = 0, reg, force, tmp; - - HSL_DEV_ID_CHECK(dev_id); - - if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU)) - { - return SW_BAD_PARAM; - } - - if (A_TRUE == enable) - { - val = 1; - } - else if (A_FALSE == enable) - { - val = 0; - } - else - { - return SW_BAD_PARAM; - } - - HSL_REG_ENTRY_GET(rv, dev_id, PORT_STATUS, port_id, - (a_uint8_t *) (®), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - tmp = reg; - - /* for those ports without PHY device we set MAC register */ - if (A_FALSE == _isisc_port_phy_connected(dev_id, port_id)) - { - SW_SET_REG_BY_FIELD(PORT_STATUS, FLOW_LINK_EN, 0, reg); - SW_SET_REG_BY_FIELD(PORT_STATUS, RX_FLOW_EN, val, reg); - } - else - { - SW_GET_FIELD_BY_REG(PORT_STATUS, FLOW_LINK_EN, force, reg); - if (force) - { - /* flow control isn't in force mode so can't set */ - return SW_DISABLE; - } - else - { - SW_SET_REG_BY_FIELD(PORT_STATUS, RX_FLOW_EN, val, reg); - } - } - if ( tmp == reg) - return SW_OK; - HSL_REG_ENTRY_SET(rv, dev_id, PORT_STATUS, port_id, - (a_uint8_t *) (®), sizeof (a_uint32_t)); - return rv; -} - -static sw_error_t -_isisc_port_rxfc_status_get(a_uint32_t dev_id, fal_port_t port_id, a_bool_t * enable) -{ - sw_error_t rv; - a_uint32_t val; - - HSL_DEV_ID_CHECK(dev_id); - - if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU)) - { - return SW_BAD_PARAM; - } - - HSL_REG_FIELD_GET(rv, dev_id, PORT_STATUS, port_id, RX_FLOW_EN, - (a_uint8_t *) (&val), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - - if (val) - { - *enable = A_TRUE; - } - else - { - *enable = A_FALSE; - } - - return SW_OK; -} -static sw_error_t -_isisc_port_link_status_get(a_uint32_t dev_id, fal_port_t port_id, a_bool_t * status) -{ - sw_error_t rv; - a_uint32_t phy_id; - hsl_phy_ops_t *phy_drv; - - HSL_DEV_ID_CHECK(dev_id); - - if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU)) - { - return SW_BAD_PARAM; - } - - - /* for those ports without PHY device supposed always link up */ - if (A_FALSE == _isisc_port_phy_connected(dev_id, port_id)) - { - *status = A_TRUE; - } - else - { - SW_RTN_ON_NULL (phy_drv = hsl_phy_api_ops_get (dev_id, port_id)); - if (NULL == phy_drv->phy_link_status_get) - return SW_NOT_SUPPORTED; - - rv = hsl_port_prop_get_phyid(dev_id, port_id, &phy_id); - SW_RTN_ON_ERROR(rv); - - if (A_TRUE == phy_drv->phy_link_status_get (dev_id, phy_id)) - { - *status = A_TRUE; - } - else - { - *status = A_FALSE; - } - } - - return SW_OK; -} - -static sw_error_t -_isisc_port_power_off (a_uint32_t dev_id, fal_port_t port_id) -{ - sw_error_t rv; - a_uint32_t phy_id = 0; - hsl_phy_ops_t *phy_drv; - - HSL_DEV_ID_CHECK (dev_id); - - if (A_TRUE != hsl_port_prop_check (dev_id, port_id, HSL_PP_PHY)) - { - return SW_BAD_PARAM; - } - - SW_RTN_ON_NULL (phy_drv = hsl_phy_api_ops_get (dev_id, port_id)); - if (NULL == phy_drv->phy_power_off) - return SW_NOT_SUPPORTED; - - rv = hsl_port_prop_get_phyid (dev_id, port_id, &phy_id); - SW_RTN_ON_ERROR (rv); - - rv = phy_drv->phy_power_off(dev_id, phy_id); - - return rv; -} - -static sw_error_t -_isisc_port_power_on (a_uint32_t dev_id, fal_port_t port_id) -{ - sw_error_t rv; - a_uint32_t phy_id = 0; - hsl_phy_ops_t *phy_drv; - - HSL_DEV_ID_CHECK (dev_id); - - if (A_TRUE != hsl_port_prop_check (dev_id, port_id, HSL_PP_PHY)) - { - return SW_BAD_PARAM; - } - - SW_RTN_ON_NULL (phy_drv = hsl_phy_api_ops_get (dev_id, port_id)); - if (NULL == phy_drv->phy_power_on) - return SW_NOT_SUPPORTED; - - rv = hsl_port_prop_get_phyid (dev_id, port_id, &phy_id); - SW_RTN_ON_ERROR (rv); - - rv = phy_drv->phy_power_on(dev_id, phy_id); - - return rv; -} - -static sw_error_t -_isisc_port_link_forcemode_set(a_uint32_t dev_id, fal_port_t port_id, a_bool_t enable) -{ - sw_error_t rv; - a_uint32_t reg = 0, tmp = 0; - - HSL_DEV_ID_CHECK(dev_id); - - if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU)) - { - return SW_BAD_PARAM; - } - - HSL_REG_ENTRY_GET(rv, dev_id, PORT_STATUS, port_id, - (a_uint8_t *) (®), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - - SW_GET_FIELD_BY_REG(PORT_STATUS, LINK_EN, tmp, reg); - - if (A_TRUE == enable) - { - if(tmp == 0) - return SW_OK; - - SW_SET_REG_BY_FIELD(PORT_STATUS, LINK_EN, 0, reg); - } - else if (A_FALSE == enable) - { - if(tmp == 1) - return SW_OK; - - /* for those ports without PHY, it can't sync link status */ - if (A_FALSE == _isisc_port_phy_connected(dev_id, port_id)) - { - return SW_DISABLE; - } - SW_SET_REG_BY_FIELD(PORT_STATUS, LINK_EN, 1, reg); - } - else - { - return SW_BAD_PARAM; - } - - HSL_REG_ENTRY_SET(rv, dev_id, PORT_STATUS, port_id, - (a_uint8_t *) (®), sizeof (a_uint32_t)); - return rv; -} - -static sw_error_t -_isisc_port_link_forcemode_get(a_uint32_t dev_id, fal_port_t port_id, a_bool_t * enable) -{ - sw_error_t rv; - a_uint32_t val = 0; - - HSL_DEV_ID_CHECK(dev_id); - - if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU)) - { - return SW_BAD_PARAM; - } - - HSL_REG_FIELD_GET(rv, dev_id, PORT_STATUS, port_id, LINK_EN, - (a_uint8_t *) (&val), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - - if (0 == val) - { - *enable = A_TRUE; - } - else - { - *enable = A_FALSE; - } - - return SW_OK; -} - -#ifndef IN_PORTCONTROL_MINI -static sw_error_t -_isisc_port_bp_status_set(a_uint32_t dev_id, fal_port_t port_id, a_bool_t enable) -{ - sw_error_t rv; - a_uint32_t val = 0, tmp; - - HSL_DEV_ID_CHECK(dev_id); - - if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU)) - { - return SW_BAD_PARAM; - } - - if (A_TRUE == enable) - { - val = 1; - } - else if (A_FALSE == enable) - { - val = 0; - } - else - { - return SW_BAD_PARAM; - } - HSL_REG_FIELD_GET(rv, dev_id, PORT_STATUS, port_id, TX_HALF_FLOW_EN, - (a_uint8_t *) (&tmp), sizeof (a_uint32_t)); - if (tmp == val) - return SW_OK; - - HSL_REG_FIELD_SET(rv, dev_id, PORT_STATUS, port_id, TX_HALF_FLOW_EN, - (a_uint8_t *) (&val), sizeof (a_uint32_t)); - return rv; -} - -static sw_error_t -_isisc_port_bp_status_get(a_uint32_t dev_id, fal_port_t port_id, a_bool_t * enable) -{ - sw_error_t rv; - a_uint32_t val; - - HSL_DEV_ID_CHECK(dev_id); - - if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU)) - { - return SW_BAD_PARAM; - } - - HSL_REG_FIELD_GET(rv, dev_id, PORT_STATUS, port_id, TX_HALF_FLOW_EN, - (a_uint8_t *) (&val), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - - if (val) - { - *enable = A_TRUE; - } - else - { - *enable = A_FALSE; - } - - return SW_OK; -} - - -static sw_error_t -_isisc_ports_link_status_get(a_uint32_t dev_id, a_uint32_t * status) -{ - sw_error_t rv; - a_uint32_t port_id; - a_uint32_t phy_id; - hsl_dev_t *pdev = NULL; - hsl_phy_ops_t *phy_drv; - a_uint32_t port_bmp[SW_MAX_NR_DEV] = {0}; - HSL_DEV_ID_CHECK(dev_id); - - pdev = hsl_dev_ptr_get(dev_id); - if (pdev == NULL) - return SW_NOT_INITIALIZED; - - port_bmp[dev_id] = qca_ssdk_phy_type_port_bmp_get(dev_id, F1_PHY_CHIP); - - *status = 0x0; - for (port_id = 0; port_id < pdev->nr_ports; port_id++) - { - if (port_id >= SW_MAX_NR_PORT) - break; - /* for those ports without PHY device supposed always link up */ - if (A_FALSE == _isisc_port_phy_connected(dev_id, port_id)) - { - *status |= (0x1 << port_id); - } - else - { - if(port_bmp[dev_id] & (0x1 << port_id)) - { - SW_RTN_ON_NULL (phy_drv = hsl_phy_api_ops_get (dev_id, port_id)); - if (NULL == phy_drv->phy_link_status_get) - return SW_NOT_SUPPORTED; - - rv = hsl_port_prop_get_phyid(dev_id, port_id, &phy_id); - SW_RTN_ON_ERROR(rv); - - if (A_TRUE == phy_drv->phy_link_status_get (dev_id, phy_id)) - { - *status |= (0x1 << port_id); - } - else - { - *status &= ~(0x1 << port_id); - } - } - } - } - return SW_OK; -} - -static sw_error_t -_isisc_port_mac_loopback_set(a_uint32_t dev_id, fal_port_t port_id, a_bool_t enable) -{ - sw_error_t rv; - a_uint32_t val = 0; - - HSL_DEV_ID_CHECK(dev_id); - - if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU)) - { - return SW_BAD_PARAM; - } - - if (A_TRUE == enable) - { - val = 1; - } - else if (A_FALSE == enable) - { - val = 0; - } - else - { - return SW_BAD_PARAM; - } - - HSL_REG_FIELD_SET(rv, dev_id, PORT_HDR_CTL, port_id, LOOPBACK_EN, - (a_uint8_t *) (&val), sizeof (a_uint32_t)); - return rv; -} - -static sw_error_t -_isisc_port_mac_loopback_get(a_uint32_t dev_id, fal_port_t port_id, a_bool_t *enable) -{ - sw_error_t rv; - a_uint32_t val; - - HSL_DEV_ID_CHECK(dev_id); - - if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU)) - { - return SW_BAD_PARAM; - } - - HSL_REG_FIELD_GET(rv, dev_id, PORT_HDR_CTL, port_id, LOOPBACK_EN, - (a_uint8_t *) (&val), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - - if (0 == val) - { - *enable = A_FALSE; - } - else - { - *enable = A_TRUE; - } - - return SW_OK; -} -#endif -/** - * @brief Set duplex mode on a particular port. - * @param[in] dev_id device id - * @param[in] port_id port id - * @param[in] duplex duplex mode - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -isisc_port_duplex_set(a_uint32_t dev_id, fal_port_t port_id, - fal_port_duplex_t duplex) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _isisc_port_duplex_set(dev_id, port_id, duplex); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Set speed on a particular port. - * @param[in] dev_id device id - * @param[in] port_id port id - * @param[in] speed port speed - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -isisc_port_speed_set(a_uint32_t dev_id, fal_port_t port_id, - fal_port_speed_t speed) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _isisc_port_speed_set(dev_id, port_id, speed); - HSL_API_UNLOCK; - return rv; -} -/** - * @brief Get duplex mode on a particular port. - * @param[in] dev_id device id - * @param[in] port_id port id - * @param[out] duplex duplex mode - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -isisc_port_duplex_get(a_uint32_t dev_id, fal_port_t port_id, - fal_port_duplex_t * pduplex) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _isisc_port_duplex_get(dev_id, port_id, pduplex); - HSL_API_UNLOCK; - return rv; -} - - - -/** - * @brief Get speed on a particular port. - * @param[in] dev_id device id - * @param[in] port_id port id - * @param[out] speed port speed - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -isisc_port_speed_get(a_uint32_t dev_id, fal_port_t port_id, - fal_port_speed_t * pspeed) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _isisc_port_speed_get(dev_id, port_id, pspeed); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Enable auto negotiation status on a particular port. - * @param[in] dev_id device id - * @param[in] port_id port id - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -isisc_port_autoneg_enable(a_uint32_t dev_id, fal_port_t port_id) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _isisc_port_autoneg_enable(dev_id, port_id); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Restart auto negotiation procedule on a particular port. - * @param[in] dev_id device id - * @param[in] port_id port id - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -isisc_port_autoneg_restart(a_uint32_t dev_id, fal_port_t port_id) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _isisc_port_autoneg_restart(dev_id, port_id); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Set auto negotiation advtisement ability on a particular port. - * @details Comments: - * auto negotiation advtisement ability is defined by macro such as - * FAL_PHY_ADV_10T_HD, FAL_PHY_ADV_PAUSE... - * @param[in] dev_id device id - * @param[in] port_id port id - * @param[in] autoadv auto negotiation advtisement ability bit map - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -isisc_port_autoneg_adv_set(a_uint32_t dev_id, fal_port_t port_id, - a_uint32_t autoadv) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _isisc_port_autoneg_adv_set(dev_id, port_id, autoadv); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Get auto negotiation status on a particular port. - * @param[in] dev_id device id - * @param[in] port_id port id - * @param[out] status A_TRUE or A_FALSE - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -isisc_port_autoneg_status_get(a_uint32_t dev_id, fal_port_t port_id, - a_bool_t * status) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _isisc_port_autoneg_status_get(dev_id, port_id, status); - HSL_API_UNLOCK; - return rv; -} - - -/** - * @brief Get auto negotiation advtisement ability on a particular port. - * @param[in] dev_id device id - * @param[in] port_id port id - * @param[out] autoadv auto negotiation advtisement ability bit map - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -isisc_port_autoneg_adv_get(a_uint32_t dev_id, fal_port_t port_id, - a_uint32_t * autoadv) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _isisc_port_autoneg_adv_get(dev_id, port_id, autoadv); - HSL_API_UNLOCK; - return rv; -} - -#ifndef IN_PORTCONTROL_MINI -/** - * @brief Get flow control status on a particular port. - * @param[in] dev_id device id - * @param[in] port_id port id - * @param[out] enable A_TRUE or A_FALSE - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -isisc_port_flowctrl_get(a_uint32_t dev_id, fal_port_t port_id, a_bool_t * enable) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _isisc_port_flowctrl_get(dev_id, port_id, enable); - HSL_API_UNLOCK; - return rv; -} - - - -/** - * @brief Get flow control force mode on a particular port. - * @param[in] dev_id device id - * @param[in] port_id port id - * @param[out] enable A_TRUE or A_FALSE - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -isisc_port_flowctrl_forcemode_get(a_uint32_t dev_id, fal_port_t port_id, - a_bool_t * enable) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _isisc_port_flowctrl_forcemode_get(dev_id, port_id, enable); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Set powersaving status on a particular port. - * @param[in] dev_id device id - * @param[in] port_id port id - * @param[out] enable A_TRUE or A_FALSE - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -isisc_port_powersave_set(a_uint32_t dev_id, fal_port_t port_id, a_bool_t enable) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _isisc_port_powersave_set(dev_id, port_id, enable); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Get powersaving status on a particular port. - * @param[in] dev_id device id - * @param[in] port_id port id - * @param[out] enable A_TRUE or A_FALSE - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -isisc_port_powersave_get(a_uint32_t dev_id, fal_port_t port_id, - a_bool_t * enable) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _isisc_port_powersave_get(dev_id, port_id, enable); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Set hibernate status on a particular port. - * @param[in] dev_id device id - * @param[in] port_id port id - * @param[out] enable A_TRUE or A_FALSE - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -isisc_port_hibernate_set(a_uint32_t dev_id, fal_port_t port_id, a_bool_t enable) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _isisc_port_hibernate_set(dev_id, port_id, enable); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Get hibernate status on a particular port. - * @param[in] dev_id device id - * @param[in] port_id port id - * @param[out] enable A_TRUE or A_FALSE - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -isisc_port_hibernate_get(a_uint32_t dev_id, fal_port_t port_id, - a_bool_t * enable) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _isisc_port_hibernate_get(dev_id, port_id, enable); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Run cable diagnostic test on a particular port. - * @param[in] dev_id device id - * @param[in] port_id port id - * @param[in] mdi_pair mdi pair id - * @param[out] cable_status cable status - * @param[out] cable_len cable len - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -isisc_port_cdt(a_uint32_t dev_id, fal_port_t port_id, a_uint32_t mdi_pair, - fal_cable_status_t * cable_status, a_uint32_t * cable_len) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _isisc_port_cdt(dev_id, port_id, mdi_pair, cable_status, cable_len); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Get phy id on a particular port. - * @param[in] dev_id device id - * @param[in] port_id port id - * @param[out] org_id and rev_id - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -isisc_port_phy_id_get (a_uint32_t dev_id, fal_port_t port_id, - a_uint16_t * org_id, a_uint16_t * rev_id) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _isisc_port_phy_id_get (dev_id, port_id, org_id, rev_id); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Set 802.3az status on a particular port. - * @param[in] dev_id device id - * @param[in] port_id port id - * @param[out] enable A_TRUE or A_FALSE - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -isisc_port_8023az_set (a_uint32_t dev_id, fal_port_t port_id, a_bool_t enable) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _isisc_port_8023az_set (dev_id, port_id, enable); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Get 8023az status on a particular port. - * @param[in] dev_id device id - * @param[in] port_id port id - * @param[out] enable A_TRUE or A_FALSE - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -isisc_port_8023az_get (a_uint32_t dev_id, fal_port_t port_id, - a_bool_t * enable) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _isisc_port_8023az_get (dev_id, port_id, enable); - HSL_API_UNLOCK; - return rv; -} - -HSL_LOCAL sw_error_t -isisc_port_local_loopback_set(a_uint32_t dev_id, fal_port_t port_id, - a_bool_t enable) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _isisc_port_local_loopback_set(dev_id, port_id, enable); - HSL_API_UNLOCK; - return rv; -} - -HSL_LOCAL sw_error_t -isisc_port_local_loopback_get(a_uint32_t dev_id, fal_port_t port_id, - a_bool_t *enable) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _isisc_port_local_loopback_get(dev_id, port_id, enable); - HSL_API_UNLOCK; - return rv; -} - -HSL_LOCAL sw_error_t -isisc_port_remote_loopback_set(a_uint32_t dev_id, fal_port_t port_id, - a_bool_t enable) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _isisc_port_remote_loopback_set(dev_id, port_id, enable); - HSL_API_UNLOCK; - return rv; -} - -HSL_LOCAL sw_error_t -isisc_port_remote_loopback_get(a_uint32_t dev_id, fal_port_t port_id, - a_bool_t *enable) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _isisc_port_remote_loopback_get(dev_id, port_id, enable); - HSL_API_UNLOCK; - return rv; -} - -#endif - -/** - * @brief Set flow control(rx/tx/bp) status on a particular port. - * @param[in] dev_id device id - * @param[in] port_id port id - * @param[in] enable A_TRUE or A_FALSE - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -isisc_port_flowctrl_set(a_uint32_t dev_id, fal_port_t port_id, a_bool_t enable) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _isisc_port_flowctrl_set(dev_id, port_id, enable); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Set flow control force mode on a particular port. - * @param[in] dev_id device id - * @param[in] port_id port id - * @param[out] enable A_TRUE or A_FALSE - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -isisc_port_flowctrl_forcemode_set(a_uint32_t dev_id, fal_port_t port_id, - a_bool_t enable) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _isisc_port_flowctrl_forcemode_set(dev_id, port_id, enable); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Set status of Atheros header packets parsed on a particular port. - * @param[in] dev_id device id - * @param[in] port_id port id - * @param[in] enable A_TRUE or A_FALSE - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -isisc_port_rxhdr_mode_set(a_uint32_t dev_id, fal_port_t port_id, - fal_port_header_mode_t mode) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _isisc_port_rxhdr_mode_set(dev_id, port_id, mode); - HSL_API_UNLOCK; - return rv; -} -#ifndef IN_PORTCONTROL_MINI -/** - * @brief Get status of Atheros header packets parsed on a particular port. - * @param[in] dev_id device id - * @param[in] port_id port id - * @param[out] enable A_TRUE or A_FALSE - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -isisc_port_rxhdr_mode_get(a_uint32_t dev_id, fal_port_t port_id, - fal_port_header_mode_t * mode) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _isisc_port_rxhdr_mode_get(dev_id, port_id, mode); - HSL_API_UNLOCK; - return rv; -} -#endif -/** - * @brief Set status of Atheros header packets parsed on a particular port. - * @param[in] dev_id device id - * @param[in] port_id port id - * @param[in] enable A_TRUE or A_FALSE - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -isisc_port_txhdr_mode_set(a_uint32_t dev_id, fal_port_t port_id, - fal_port_header_mode_t mode) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _isisc_port_txhdr_mode_set(dev_id, port_id, mode); - HSL_API_UNLOCK; - return rv; -} -#ifndef IN_PORTCONTROL_MINI -/** - * @brief Get status of Atheros header packets parsed on a particular port. - * @param[in] dev_id device id - * @param[in] port_id port id - * @param[out] enable A_TRUE or A_FALSE - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -isisc_port_txhdr_mode_get(a_uint32_t dev_id, fal_port_t port_id, - fal_port_header_mode_t * mode) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _isisc_port_txhdr_mode_get(dev_id, port_id, mode); - HSL_API_UNLOCK; - return rv; -} -#endif -/** - * @brief Set status of Atheros header type value on a particular device. - * @param[in] dev_id device id - * @param[in] enable A_TRUE or A_FALSE - * @param[in] type header type value - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -isisc_header_type_set(a_uint32_t dev_id, a_bool_t enable, a_uint32_t type) -{ - sw_error_t rv; - HSL_API_LOCK; - rv = _isisc_header_type_set(dev_id, enable, type); - HSL_API_UNLOCK; - return rv; -} -#ifndef IN_PORTCONTROL_MINI -/** - * @brief Get status of Atheros header type value on a particular device. - * @param[in] dev_id device id - * @param[out] enable A_TRUE or A_FALSE - * @param[out] type header type value - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -isisc_header_type_get(a_uint32_t dev_id, a_bool_t * enable, a_uint32_t * type) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _isisc_header_type_get(dev_id, enable, type); - HSL_API_UNLOCK; - return rv; -} -#endif -/** - * @brief Set status of txmac on a particular port. - * @param[in] dev_id device id - * @param[in] port_id port id - * @param[in] enable A_TRUE or A_FALSE - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -isisc_port_txmac_status_set(a_uint32_t dev_id, fal_port_t port_id, a_bool_t enable) -{ - sw_error_t rv; - HSL_API_LOCK; - rv = _isisc_port_txmac_status_set(dev_id, port_id, enable); - HSL_API_UNLOCK; - return rv; -} -#ifndef IN_PORTCONTROL_MINI -/** - * @brief Get status of txmac on a particular port. - * @param[in] dev_id device id - * @param[in] port_id port id - * @param[out] enable A_TRUE or A_FALSE - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -isisc_port_txmac_status_get(a_uint32_t dev_id, fal_port_t port_id, a_bool_t * enable) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _isisc_port_txmac_status_get(dev_id, port_id, enable); - HSL_API_UNLOCK; - return rv; -} -#endif -/** - * @brief Set status of rxmac on a particular port. - * @param[in] dev_id device id - * @param[in] port_id port id - * @param[in] enable A_TRUE or A_FALSE - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -isisc_port_rxmac_status_set(a_uint32_t dev_id, fal_port_t port_id, a_bool_t enable) -{ - sw_error_t rv; - HSL_API_LOCK; - rv = _isisc_port_rxmac_status_set(dev_id, port_id, enable); - HSL_API_UNLOCK; - return rv; -} -#ifndef IN_PORTCONTROL_MINI -/** - * @brief Get status of rxmac on a particular port. - * @param[in] dev_id device id - * @param[in] port_id port id - * @param[out] enable A_TRUE or A_FALSE - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -isisc_port_rxmac_status_get(a_uint32_t dev_id, fal_port_t port_id, a_bool_t * enable) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _isisc_port_rxmac_status_get(dev_id, port_id, enable); - HSL_API_UNLOCK; - return rv; -} -#endif -/** - * @brief Set status of tx flow control on a particular port. - * @param[in] dev_id device id - * @param[in] port_id port id - * @param[in] enable A_TRUE or A_FALSE - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -isisc_port_txfc_status_set(a_uint32_t dev_id, fal_port_t port_id, a_bool_t enable) -{ - sw_error_t rv; - HSL_API_LOCK; - rv = _isisc_port_txfc_status_set(dev_id, port_id, enable); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Get status of tx flow control on a particular port. - * @param[in] dev_id device id - * @param[in] port_id port id - * @param[out] enable A_TRUE or A_FALSE - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -isisc_port_txfc_status_get(a_uint32_t dev_id, fal_port_t port_id, a_bool_t * enable) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _isisc_port_txfc_status_get(dev_id, port_id, enable); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Set status of rx flow control on a particular port. - * @param[in] dev_id device id - * @param[in] port_id port id - * @param[in] enable A_TRUE or A_FALSE - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -isisc_port_rxfc_status_set(a_uint32_t dev_id, fal_port_t port_id, a_bool_t enable) -{ - sw_error_t rv; - HSL_API_LOCK; - rv = _isisc_port_rxfc_status_set(dev_id, port_id, enable); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Set status of rx flow control on a particular port. - * @param[in] dev_id device id - * @param[in] port_id port id - * @param[out] enable A_TRUE or A_FALSE - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -isisc_port_rxfc_status_get(a_uint32_t dev_id, fal_port_t port_id, a_bool_t * enable) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _isisc_port_rxfc_status_get(dev_id, port_id, enable); - HSL_API_UNLOCK; - return rv; -} -/** - * @brief Get link status on particular port. - * @param[in] dev_id device id - * @param[in] port_id port id - * @param[out] status link status up (A_TRUE) or down (A_FALSE) - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -isisc_port_link_status_get(a_uint32_t dev_id, fal_port_t port_id, a_bool_t * status) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _isisc_port_link_status_get(dev_id, port_id, status); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief phy power off on a particular port. - * @param[in] dev_id device id - * @param[in] port_id port id - * @param[in] - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -isisc_port_power_off (a_uint32_t dev_id, fal_port_t port_id) -{ - sw_error_t rv; - HSL_API_LOCK; - rv = _isisc_port_power_off (dev_id, port_id); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief phy power on on a particular port. - * @param[in] dev_id device id - * @param[in] port_id port id - * @param[in] - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -isisc_port_power_on (a_uint32_t dev_id, fal_port_t port_id) -{ - sw_error_t rv; - HSL_API_LOCK; - rv = _isisc_port_power_on (dev_id, port_id); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Set link force mode on a particular port. - * @param[in] dev_id device id - * @param[in] port_id port id - * @param[in] enable A_TRUE or A_FALSE - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -isisc_port_link_forcemode_set(a_uint32_t dev_id, fal_port_t port_id, a_bool_t enable) -{ - sw_error_t rv; - HSL_API_LOCK; - rv = _isisc_port_link_forcemode_set(dev_id, port_id, enable); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Get link force mode on a particular port. - * @param[in] dev_id device id - * @param[in] port_id port id - * @param[out] enable A_TRUE or A_FALSE - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -isisc_port_link_forcemode_get(a_uint32_t dev_id, fal_port_t port_id, a_bool_t * enable) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _isisc_port_link_forcemode_get(dev_id, port_id, enable); - HSL_API_UNLOCK; - return rv; -} - -#ifndef IN_PORTCONTROL_MINI -/** - * @brief Set status of back pressure on a particular port. - * @param[in] dev_id device id - * @param[in] port_id port id - * @param[in] enable A_TRUE or A_FALSE - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -isisc_port_bp_status_set(a_uint32_t dev_id, fal_port_t port_id, a_bool_t enable) -{ - sw_error_t rv; - HSL_API_LOCK; - rv = _isisc_port_bp_status_set(dev_id, port_id, enable); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Set status of back pressure on a particular port. - * @param[in] dev_id device id - * @param[in] port_id port id - * @param[out] enable A_TRUE or A_FALSE - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -isisc_port_bp_status_get(a_uint32_t dev_id, fal_port_t port_id, a_bool_t * enable) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _isisc_port_bp_status_get(dev_id, port_id, enable); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Get link status on all ports. - * @param[in] dev_id device id - * @param[out] status link status bitmap and bit 0 for port 0, bi 1 for port 1, ..., etc. - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -isisc_ports_link_status_get(a_uint32_t dev_id, a_uint32_t * status) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _isisc_ports_link_status_get(dev_id, status); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Set mac loop back on a particular port. - * @param[in] dev_id device id - * @param[in] port_id port id - * @param[in] enable A_TRUE or A_FALSE - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -isisc_port_mac_loopback_set(a_uint32_t dev_id, fal_port_t port_id, a_bool_t enable) -{ - sw_error_t rv; - HSL_API_LOCK; - rv = _isisc_port_mac_loopback_set(dev_id, port_id, enable); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Get mac loop back on a particular port. - * @param[in] dev_id device id - * @param[in] port_id port id - * @param[out] enable A_TRUE or A_FALSE - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -isisc_port_mac_loopback_get(a_uint32_t dev_id, fal_port_t port_id, a_bool_t * enable) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _isisc_port_mac_loopback_get(dev_id, port_id, enable); - HSL_API_UNLOCK; - return rv; -} -#endif -sw_error_t -isisc_port_ctrl_init(a_uint32_t dev_id) -{ - HSL_DEV_ID_CHECK(dev_id); - -#ifndef HSL_STANDALONG - { - hsl_api_t *p_api; - - SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id)); - - p_api->port_duplex_set = isisc_port_duplex_set; - p_api->port_speed_set = isisc_port_speed_set; - p_api->port_flowctrl_set = isisc_port_flowctrl_set; - p_api->port_flowctrl_forcemode_set = isisc_port_flowctrl_forcemode_set; - p_api->port_duplex_get = isisc_port_duplex_get; - p_api->port_speed_get = isisc_port_speed_get; - p_api->port_autoneg_enable = isisc_port_autoneg_enable; - p_api->port_autoneg_restart = isisc_port_autoneg_restart; - p_api->port_autoneg_adv_set = isisc_port_autoneg_adv_set; - p_api->port_autoneg_status_get = isisc_port_autoneg_status_get; - p_api->port_autoneg_adv_get = isisc_port_autoneg_adv_get; -#ifndef IN_PORTCONTROL_MINI - p_api->port_flowctrl_get = isisc_port_flowctrl_get; - p_api->port_flowctrl_forcemode_get = isisc_port_flowctrl_forcemode_get; - p_api->port_powersave_set = isisc_port_powersave_set; - p_api->port_powersave_get = isisc_port_powersave_get; - p_api->port_hibernate_set = isisc_port_hibernate_set; - p_api->port_hibernate_get = isisc_port_hibernate_get; - p_api->port_cdt = isisc_port_cdt; - p_api->port_phy_id_get = isisc_port_phy_id_get; - p_api->port_rxhdr_mode_get = isisc_port_rxhdr_mode_get; - p_api->port_txhdr_mode_get = isisc_port_txhdr_mode_get; - p_api->header_type_get = isisc_header_type_get; - p_api->port_txmac_status_get = isisc_port_txmac_status_get; - p_api->port_rxmac_status_get = isisc_port_rxmac_status_get; - p_api->port_8023az_set = isisc_port_8023az_set; - p_api->port_8023az_get = isisc_port_8023az_get; - p_api->port_local_loopback_set = isisc_port_local_loopback_set; - p_api->port_local_loopback_get = isisc_port_local_loopback_get; - p_api->port_remote_loopback_set = isisc_port_remote_loopback_set; - p_api->port_remote_loopback_get = isisc_port_remote_loopback_get; - -#endif - p_api->port_txfc_status_get = isisc_port_txfc_status_get; - p_api->port_rxhdr_mode_set = isisc_port_rxhdr_mode_set; - p_api->port_txhdr_mode_set = isisc_port_txhdr_mode_set; - p_api->header_type_set = isisc_header_type_set; - p_api->port_txmac_status_set = isisc_port_txmac_status_set; - p_api->port_rxmac_status_set = isisc_port_rxmac_status_set; - p_api->port_txfc_status_set = isisc_port_txfc_status_set; - p_api->port_rxfc_status_set = isisc_port_rxfc_status_set; - p_api->port_link_status_get = isisc_port_link_status_get; - p_api->port_rxfc_status_get = isisc_port_rxfc_status_get; - p_api->port_power_off = isisc_port_power_off; - p_api->port_power_on = isisc_port_power_on; - p_api->port_link_forcemode_set = isisc_port_link_forcemode_set; - p_api->port_link_forcemode_get = isisc_port_link_forcemode_get; -#ifndef IN_PORTCONTROL_MINI - p_api->port_bp_status_set = isisc_port_bp_status_set; - p_api->port_bp_status_get = isisc_port_bp_status_get; - p_api->ports_link_status_get = isisc_ports_link_status_get; - p_api->port_mac_loopback_set=isisc_port_mac_loopback_set; - p_api->port_mac_loopback_get=isisc_port_mac_loopback_get; -#endif - } -#endif - - return SW_OK; -} - -/** - * @} - */ - diff --git a/feeds/ipq807x/qca-ssdk/src/src/hsl/isisc/isisc_portvlan.c b/feeds/ipq807x/qca-ssdk/src/src/hsl/isisc/isisc_portvlan.c deleted file mode 100755 index bf47d0060..000000000 --- a/feeds/ipq807x/qca-ssdk/src/src/hsl/isisc/isisc_portvlan.c +++ /dev/null @@ -1,2291 +0,0 @@ -/* - * Copyright (c) 2012, 2016, The Linux Foundation. All rights reserved. - * Permission to use, copy, modify, and/or distribute this software for - * any purpose with or without fee is hereby granted, provided that the - * above copyright notice and this permission notice appear in all copies. - * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES - * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR - * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES - * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN - * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT - * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. - */ - - -/** - * @defgroup isisc_port_vlan ISISC_PORT_VLAN - * @{ - */ -#include "sw.h" -#include "hsl.h" -#include "hsl_dev.h" -#include "hsl_port_prop.h" -#include "isisc_portvlan.h" -#include "isisc_reg.h" - -#define MAX_VLAN_ID 4095 -#define ISISC_MAX_VLAN_TRANS 64 -#define ISISC_VLAN_TRANS_ADDR 0x5ac00 - - -static sw_error_t -_isisc_port_route_defv_set(a_uint32_t dev_id, fal_port_t port_id) -{ - sw_error_t rv; - a_uint32_t data = 0, reg = 0; - - HSL_REG_FIELD_GET(rv, dev_id, PORT_VLAN1, port_id, - COREP_EN, (a_uint8_t *) (&data), sizeof (a_uint32_t)); - - SW_RTN_ON_ERROR(rv); - - if (data) - { - HSL_REG_FIELD_GET(rv, dev_id, PORT_VLAN0, port_id, - DEF_SVID, (a_uint8_t *) (&data), sizeof (a_uint32_t)); - } - else - { - HSL_REG_FIELD_GET(rv, dev_id, PORT_VLAN0, port_id, - DEF_CVID, (a_uint8_t *) (&data), sizeof (a_uint32_t)); - } - - HSL_REG_ENTRY_GET(rv, dev_id, ROUTER_DEFV, (port_id / 2), - (a_uint8_t *) (®), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - - if (port_id % 2) - { - reg &= 0xffff; - reg |= ((data & 0xfff) << 16); - } - else - { - reg &= 0xffff0000; - reg |= (data & 0xfff); - } - - HSL_REG_ENTRY_SET(rv, dev_id, ROUTER_DEFV, (port_id / 2), - (a_uint8_t *) (®), sizeof (a_uint32_t)); - return rv; -} - -static sw_error_t -_isisc_port_1qmode_set(a_uint32_t dev_id, fal_port_t port_id, - fal_pt_1qmode_t port_1qmode) -{ - sw_error_t rv; - a_uint32_t data, regval[FAL_1Q_MODE_BUTT] = { 0, 3, 2, 1 }; - - HSL_DEV_ID_CHECK(dev_id); - - if (A_FALSE == hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU)) - { - return SW_BAD_PARAM; - } - - if (FAL_1Q_MODE_BUTT <= port_1qmode) - { - return SW_BAD_PARAM; - } - - HSL_REG_FIELD_SET(rv, dev_id, PORT_LOOKUP_CTL, port_id, DOT1Q_MODE, - (a_uint8_t *) (®val[port_1qmode]), - sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - - if (FAL_1Q_DISABLE == port_1qmode) - { - data = 1; - } - else - { - data = 0; - } - - HSL_REG_FIELD_SET(rv, dev_id, PORT_VLAN1, port_id, VLAN_DIS, - (a_uint8_t *) (&data), sizeof (a_uint32_t)); - return rv; -} -#ifndef IN_PORTVLAN_MINI -static sw_error_t -_isisc_port_1qmode_get(a_uint32_t dev_id, fal_port_t port_id, - fal_pt_1qmode_t * pport_1qmode) -{ - sw_error_t rv; - a_uint32_t regval = 0; - fal_pt_1qmode_t retval[4] = { FAL_1Q_DISABLE, FAL_1Q_FALLBACK, - FAL_1Q_CHECK, FAL_1Q_SECURE - }; - - HSL_DEV_ID_CHECK(dev_id); - - if (A_FALSE == hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU)) - { - return SW_BAD_PARAM; - } - - SW_RTN_ON_NULL(pport_1qmode); - - HSL_REG_FIELD_GET(rv, dev_id, PORT_LOOKUP_CTL, port_id, DOT1Q_MODE, - (a_uint8_t *) (®val), sizeof (a_uint32_t)); - - SW_RTN_ON_ERROR(rv); - - *pport_1qmode = retval[regval & 0x3]; - - return SW_OK; -} -#endif -static sw_error_t -_isisc_port_egvlanmode_set(a_uint32_t dev_id, fal_port_t port_id, - fal_pt_1q_egmode_t port_egvlanmode) -{ - sw_error_t rv; - a_uint32_t data = 0, regval[FAL_EG_MODE_BUTT] = { 0, 1, 2, 3, 3 }; - - HSL_DEV_ID_CHECK(dev_id); - - if (A_FALSE == hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU)) - { - return SW_BAD_PARAM; - } - - if ((FAL_EG_MODE_BUTT <= port_egvlanmode) - || (FAL_EG_HYBRID == port_egvlanmode)) - { - return SW_BAD_PARAM; - } - - HSL_REG_FIELD_SET(rv, dev_id, PORT_VLAN1, port_id, EG_VLAN_MODE, - (a_uint8_t *) (®val[port_egvlanmode]), - sizeof (a_uint32_t)); - - SW_RTN_ON_ERROR(rv); - - HSL_REG_ENTRY_GET(rv, dev_id, ROUTER_EG, 0, - (a_uint8_t *) (&data), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - - data &= (~(0x3 << (port_id << 2))); - data |= (regval[port_egvlanmode] << (port_id << 2)); - - HSL_REG_ENTRY_SET(rv, dev_id, ROUTER_EG, 0, - (a_uint8_t *) (&data), sizeof (a_uint32_t)); - return rv; -} -#ifndef IN_PORTVLAN_MINI -static sw_error_t -_isisc_port_egvlanmode_get(a_uint32_t dev_id, fal_port_t port_id, - fal_pt_1q_egmode_t * pport_egvlanmode) -{ - sw_error_t rv; - a_uint32_t regval = 0; - fal_pt_1q_egmode_t retval[4] = { FAL_EG_UNMODIFIED, FAL_EG_UNTAGGED, - FAL_EG_TAGGED, FAL_EG_UNTOUCHED - }; - - HSL_DEV_ID_CHECK(dev_id); - - if (A_FALSE == hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU)) - { - return SW_BAD_PARAM; - } - - SW_RTN_ON_NULL(pport_egvlanmode); - - HSL_REG_FIELD_GET(rv, dev_id, PORT_VLAN1, port_id, EG_VLAN_MODE, - (a_uint8_t *) (®val), sizeof (a_uint32_t)); - - SW_RTN_ON_ERROR(rv); - - *pport_egvlanmode = retval[regval & 0x3]; - - return SW_OK; -} -#endif -static sw_error_t -_isisc_portvlan_member_add(a_uint32_t dev_id, fal_port_t port_id, - a_uint32_t mem_port_id) -{ - sw_error_t rv; - a_uint32_t regval = 0; - - HSL_DEV_ID_CHECK(dev_id); - - if (A_FALSE == hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU)) - { - return SW_BAD_PARAM; - } - - if (A_FALSE == hsl_port_prop_check(dev_id, mem_port_id, HSL_PP_INCL_CPU)) - { - return SW_BAD_PARAM; - } - - HSL_REG_FIELD_GET(rv, dev_id, PORT_LOOKUP_CTL, port_id, - PORT_VID_MEM, (a_uint8_t *) (®val), - sizeof (a_uint32_t)); - - SW_RTN_ON_ERROR(rv); - - regval |= (0x1UL << mem_port_id); - - HSL_REG_FIELD_SET(rv, dev_id, PORT_LOOKUP_CTL, port_id, - PORT_VID_MEM, (a_uint8_t *) (®val), - sizeof (a_uint32_t)); - - return rv; -} - -static sw_error_t -_isisc_portvlan_member_del(a_uint32_t dev_id, fal_port_t port_id, - a_uint32_t mem_port_id) -{ - sw_error_t rv; - a_uint32_t regval = 0; - - HSL_DEV_ID_CHECK(dev_id); - - if (A_FALSE == hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU)) - { - return SW_BAD_PARAM; - } - - if (A_FALSE == hsl_port_prop_check(dev_id, mem_port_id, HSL_PP_INCL_CPU)) - { - return SW_BAD_PARAM; - } - - HSL_REG_FIELD_GET(rv, dev_id, PORT_LOOKUP_CTL, port_id, - PORT_VID_MEM, (a_uint8_t *) (®val), - sizeof (a_uint32_t)); - - SW_RTN_ON_ERROR(rv); - - regval &= (~(0x1UL << mem_port_id)); - - HSL_REG_FIELD_SET(rv, dev_id, PORT_LOOKUP_CTL, port_id, - PORT_VID_MEM, (a_uint8_t *) (®val), - sizeof (a_uint32_t)); - - return rv; -} - -static sw_error_t -_isisc_portvlan_member_update(a_uint32_t dev_id, fal_port_t port_id, - fal_pbmp_t mem_port_map) -{ - sw_error_t rv; - - HSL_DEV_ID_CHECK(dev_id); - - if (A_FALSE == hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU)) - { - return SW_BAD_PARAM; - } - - if (A_FALSE == hsl_mports_prop_check(dev_id, mem_port_map, HSL_PP_INCL_CPU)) - { - return SW_BAD_PARAM; - } - - HSL_REG_FIELD_SET(rv, dev_id, PORT_LOOKUP_CTL, port_id, - PORT_VID_MEM, (a_uint8_t *) (&mem_port_map), - sizeof (a_uint32_t)); - - return rv; -} -#ifndef IN_PORTVLAN_MINI -static sw_error_t -_isisc_portvlan_member_get(a_uint32_t dev_id, fal_port_t port_id, - fal_pbmp_t * mem_port_map) -{ - sw_error_t rv; - - HSL_DEV_ID_CHECK(dev_id); - - if (A_FALSE == hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU)) - { - return SW_BAD_PARAM; - } - - *mem_port_map = 0; - HSL_REG_FIELD_GET(rv, dev_id, PORT_LOOKUP_CTL, port_id, - PORT_VID_MEM, (a_uint8_t *) mem_port_map, - sizeof (a_uint32_t)); - - SW_RTN_ON_ERROR(rv); - - return SW_OK; -} -#endif -static sw_error_t -_isisc_port_force_default_vid_set(a_uint32_t dev_id, fal_port_t port_id, - a_bool_t enable) -{ - sw_error_t rv; - a_uint32_t val; - - HSL_DEV_ID_CHECK(dev_id); - - if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU)) - { - return SW_BAD_PARAM; - } - - if (A_TRUE == enable) - { - val = 1; - } - else if (A_FALSE == enable) - { - val = 0; - } - else - { - return SW_BAD_PARAM; - } - - HSL_REG_FIELD_SET(rv, dev_id, PORT_VLAN1, port_id, - FORCE_DEF_VID, (a_uint8_t *) (&val), sizeof (a_uint32_t)); - return rv; -} -#ifndef IN_PORTVLAN_MINI -static sw_error_t -_isisc_port_force_default_vid_get(a_uint32_t dev_id, fal_port_t port_id, - a_bool_t * enable) -{ - sw_error_t rv; - a_uint32_t val = 0; - - HSL_DEV_ID_CHECK(dev_id); - - if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU)) - { - return SW_BAD_PARAM; - } - - HSL_REG_FIELD_GET(rv, dev_id, PORT_VLAN1, port_id, - FORCE_DEF_VID, (a_uint8_t *) (&val), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - - if (val) - { - *enable = A_TRUE; - } - else - { - *enable = A_FALSE; - } - - return SW_OK; -} -#endif -static sw_error_t -_isisc_port_force_portvlan_set(a_uint32_t dev_id, fal_port_t port_id, - a_bool_t enable) -{ - sw_error_t rv; - a_uint32_t val; - - HSL_DEV_ID_CHECK(dev_id); - - if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU)) - { - return SW_BAD_PARAM; - } - - if (A_TRUE == enable) - { - val = 1; - } - else if (A_FALSE == enable) - { - val = 0; - } - else - { - return SW_BAD_PARAM; - } - - HSL_REG_FIELD_SET(rv, dev_id, PORT_LOOKUP_CTL, port_id, - FORCE_PVLAN, (a_uint8_t *) (&val), sizeof (a_uint32_t)); - return rv; -} -#ifndef IN_PORTVLAN_MINI -static sw_error_t -_isisc_port_force_portvlan_get(a_uint32_t dev_id, fal_port_t port_id, - a_bool_t * enable) -{ - sw_error_t rv; - a_uint32_t val = 0; - - HSL_DEV_ID_CHECK(dev_id); - - if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU)) - { - return SW_BAD_PARAM; - } - - HSL_REG_FIELD_GET(rv, dev_id, PORT_LOOKUP_CTL, port_id, - FORCE_PVLAN, (a_uint8_t *) (&val), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - - if (val) - { - *enable = A_TRUE; - } - else - { - *enable = A_FALSE; - } - - return SW_OK; -} -#endif -static sw_error_t -_isisc_nestvlan_tpid_set(a_uint32_t dev_id, a_uint32_t tpid) -{ - sw_error_t rv; - a_uint32_t val; - - HSL_DEV_ID_CHECK(dev_id); - - val = tpid; - HSL_REG_FIELD_SET(rv, dev_id, SERVICE_TAG, 0, - TAG_VALUE, (a_uint8_t *) (&val), sizeof (a_uint32_t)); - return rv; -} -#ifndef IN_PORTVLAN_MINI -static sw_error_t -_isisc_nestvlan_tpid_get(a_uint32_t dev_id, a_uint32_t * tpid) -{ - sw_error_t rv; - a_uint32_t val = 0; - - HSL_DEV_ID_CHECK(dev_id); - - HSL_REG_FIELD_GET(rv, dev_id, SERVICE_TAG, 0, - TAG_VALUE, (a_uint8_t *) (&val), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - - *tpid = val; - return SW_OK; -} -#endif -static sw_error_t -_isisc_port_invlan_mode_set(a_uint32_t dev_id, fal_port_t port_id, - fal_pt_invlan_mode_t mode) -{ - sw_error_t rv; - a_uint32_t regval[FAL_INVLAN_MODE_BUTT] = { 0, 1, 2 }; - - HSL_DEV_ID_CHECK(dev_id); - - if (A_FALSE == hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU)) - { - return SW_BAD_PARAM; - } - - if (FAL_INVLAN_MODE_BUTT <= mode) - { - return SW_BAD_PARAM; - } - - HSL_REG_FIELD_SET(rv, dev_id, PORT_VLAN1, port_id, IN_VLAN_MODE, - (a_uint8_t *) (®val[mode]), sizeof (a_uint32_t)); - return rv; -} -#ifndef IN_PORTVLAN_MINI -static sw_error_t -_isisc_port_invlan_mode_get(a_uint32_t dev_id, fal_port_t port_id, - fal_pt_invlan_mode_t * mode) -{ - sw_error_t rv; - a_uint32_t regval = 0; - fal_pt_invlan_mode_t retval[FAL_INVLAN_MODE_BUTT] = { FAL_INVLAN_ADMIT_ALL, - FAL_INVLAN_ADMIT_TAGGED, FAL_INVLAN_ADMIT_UNTAGGED - }; - - HSL_DEV_ID_CHECK(dev_id); - - if (A_FALSE == hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU)) - { - return SW_BAD_PARAM; - } - - SW_RTN_ON_NULL(mode); - - HSL_REG_FIELD_GET(rv, dev_id, PORT_VLAN1, port_id, IN_VLAN_MODE, - (a_uint8_t *) (®val), sizeof (a_uint32_t)); - - SW_RTN_ON_ERROR(rv); - - if (regval >= 3) - { - return SW_FAIL; - } - *mode = retval[regval & 0x3]; - - return rv; -} -#endif - -static sw_error_t -_isisc_port_tls_set(a_uint32_t dev_id, fal_port_t port_id, a_bool_t enable) -{ - sw_error_t rv; - a_uint32_t val; - - HSL_DEV_ID_CHECK(dev_id); - - if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU)) - { - return SW_BAD_PARAM; - } - - if (A_TRUE == enable) - { - val = 1; - } - else if (A_FALSE == enable) - { - val = 0; - } - else - { - return SW_BAD_PARAM; - } - - HSL_REG_FIELD_SET(rv, dev_id, PORT_VLAN1, port_id, - TLS_EN, (a_uint8_t *) (&val), sizeof (a_uint32_t)); - return rv; -} -#ifndef IN_PORTVLAN_MINI -static sw_error_t -_isisc_port_tls_get(a_uint32_t dev_id, fal_port_t port_id, a_bool_t * enable) -{ - sw_error_t rv; - a_uint32_t val = 0; - - HSL_DEV_ID_CHECK(dev_id); - - if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU)) - { - return SW_BAD_PARAM; - } - - HSL_REG_FIELD_GET(rv, dev_id, PORT_VLAN1, port_id, - TLS_EN, (a_uint8_t *) (&val), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - - if (1 == val) - { - *enable = A_TRUE; - } - else - { - *enable = A_FALSE; - } - - return SW_OK; -} - -static sw_error_t -_isisc_port_pri_propagation_set(a_uint32_t dev_id, fal_port_t port_id, - a_bool_t enable) -{ - sw_error_t rv; - a_uint32_t val; - - HSL_DEV_ID_CHECK(dev_id); - - if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU)) - { - return SW_BAD_PARAM; - } - - if (A_TRUE == enable) - { - val = 1; - } - else if (A_FALSE == enable) - { - val = 0; - } - else - { - return SW_BAD_PARAM; - } - - HSL_REG_FIELD_SET(rv, dev_id, PORT_VLAN1, port_id, - PRI_PROPAGATION, (a_uint8_t *) (&val), - sizeof (a_uint32_t)); - return rv; -} - -static sw_error_t -_isisc_port_pri_propagation_get(a_uint32_t dev_id, fal_port_t port_id, - a_bool_t * enable) -{ - sw_error_t rv; - a_uint32_t val = 0; - - HSL_DEV_ID_CHECK(dev_id); - - if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU)) - { - return SW_BAD_PARAM; - } - - HSL_REG_FIELD_GET(rv, dev_id, PORT_VLAN1, port_id, - PRI_PROPAGATION, (a_uint8_t *) (&val), - sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - - if (1 == val) - { - *enable = A_TRUE; - } - else - { - *enable = A_FALSE; - } - - return SW_OK; -} -#endif -static sw_error_t -_isisc_port_default_svid_set(a_uint32_t dev_id, fal_port_t port_id, - a_uint32_t vid) -{ - sw_error_t rv; - a_uint32_t val; - - HSL_DEV_ID_CHECK(dev_id); - - if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU)) - { - return SW_BAD_PARAM; - } - - if (vid > MAX_VLAN_ID) - { - return SW_BAD_PARAM; - } - - val = vid; - HSL_REG_FIELD_SET(rv, dev_id, PORT_VLAN0, port_id, - DEF_SVID, (a_uint8_t *) (&val), sizeof (a_uint32_t)); - - SW_RTN_ON_ERROR(rv); - - rv = _isisc_port_route_defv_set(dev_id, port_id); - return rv; -} -#ifndef IN_PORTVLAN_MINI -static sw_error_t -_isisc_port_default_svid_get(a_uint32_t dev_id, fal_port_t port_id, - a_uint32_t * vid) -{ - sw_error_t rv; - a_uint32_t val = 0; - - HSL_DEV_ID_CHECK(dev_id); - - if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU)) - { - return SW_BAD_PARAM; - } - - HSL_REG_FIELD_GET(rv, dev_id, PORT_VLAN0, port_id, - DEF_SVID, (a_uint8_t *) (&val), sizeof (a_uint32_t)); - - *vid = val & 0xfff; - return rv; -} -#endif -static sw_error_t -_isisc_port_default_cvid_set(a_uint32_t dev_id, fal_port_t port_id, - a_uint32_t vid) -{ - sw_error_t rv; - a_uint32_t val; - - HSL_DEV_ID_CHECK(dev_id); - - if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU)) - { - return SW_BAD_PARAM; - } - - if (vid > MAX_VLAN_ID) - { - return SW_BAD_PARAM; - } - - val = vid; - HSL_REG_FIELD_SET(rv, dev_id, PORT_VLAN0, port_id, - DEF_CVID, (a_uint8_t *) (&val), sizeof (a_uint32_t)); - - SW_RTN_ON_ERROR(rv); - - rv = _isisc_port_route_defv_set(dev_id, port_id); - return rv; -} -#ifndef IN_PORTVLAN_MINI -static sw_error_t -_isisc_port_default_cvid_get(a_uint32_t dev_id, fal_port_t port_id, - a_uint32_t * vid) -{ - sw_error_t rv; - a_uint32_t val = 0; - - HSL_DEV_ID_CHECK(dev_id); - - if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU)) - { - return SW_BAD_PARAM; - } - - HSL_REG_FIELD_GET(rv, dev_id, PORT_VLAN0, port_id, - DEF_CVID, (a_uint8_t *) (&val), sizeof (a_uint32_t)); - - *vid = val & 0xfff; - return rv; -} -#endif -static sw_error_t -_isisc_port_vlan_propagation_set(a_uint32_t dev_id, fal_port_t port_id, - fal_vlan_propagation_mode_t mode) -{ - sw_error_t rv; - a_uint32_t reg = 0, p, c; - - HSL_DEV_ID_CHECK(dev_id); - - if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU)) - { - return SW_BAD_PARAM; - } - - if (FAL_VLAN_PROPAGATION_DISABLE == mode) - { - p = 0; - c = 0; - } - else if (FAL_VLAN_PROPAGATION_CLONE == mode) - { - p = 1; - c = 1; - } - else if (FAL_VLAN_PROPAGATION_REPLACE == mode) - { - p = 1; - c = 0; - } - else - { - return SW_BAD_PARAM; - } - - HSL_REG_ENTRY_GET(rv, dev_id, PORT_VLAN1, port_id, - (a_uint8_t *) (®), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - - SW_SET_REG_BY_FIELD(PORT_VLAN1, PROPAGATION_EN, p, reg); - SW_SET_REG_BY_FIELD(PORT_VLAN1, CLONE, c, reg); - - HSL_REG_ENTRY_SET(rv, dev_id, PORT_VLAN1, port_id, - (a_uint8_t *) (®), sizeof (a_uint32_t)); - return rv; -} -static sw_error_t -_isisc_vlan_trans_write(a_uint32_t dev_id, a_uint32_t entry_idx, fal_pbmp_t pbmp, - fal_vlan_trans_entry_t entry) -{ - sw_error_t rv; - a_uint32_t i, addr, table[2] = { 0 }; - - addr = ISISC_VLAN_TRANS_ADDR + (entry_idx << 3); - - if (0 != pbmp) - { - table[0] = entry.o_vid & 0xfff; - table[0] |= ((entry.s_vid & 0xfff) << 12); - table[0] |= ((entry.c_vid & 0xff) << 24); - table[1] = (entry.c_vid >> 8) & 0xf; - - if (A_TRUE == entry.bi_dir) - { - table[1] |= (0x3 << 4); - } - - if (A_TRUE == entry.forward_dir) - { - table[1] |= (0x1 << 4); - } - - if (A_TRUE == entry.reverse_dir) - { - table[1] |= (0x1 << 5); - } - - table[1] |= (pbmp << 6); - table[1] |= ((0x1UL & entry.o_vid_is_cvid) << 13); - table[1] |= ((0x1UL & entry.s_vid_enable) << 14); - table[1] |= ((0x1UL & entry.c_vid_enable) << 15); - table[1] |= ((0x1UL & entry.one_2_one_vlan) << 16); - } - - /* set vlan trans table */ - for (i = 0; i < 2; i++) - { - HSL_REG_ENTRY_GEN_SET(rv, dev_id, addr + (i << 2), sizeof (a_uint32_t), - (a_uint8_t *) (&(table[i])), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - } - - return SW_OK; -} -#ifndef IN_PORTVLAN_MINI - -static sw_error_t -_isisc_port_vlan_propagation_get(a_uint32_t dev_id, fal_port_t port_id, - fal_vlan_propagation_mode_t * mode) -{ - sw_error_t rv; - a_uint32_t reg = 0, p, c; - - HSL_DEV_ID_CHECK(dev_id); - - if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU)) - { - return SW_BAD_PARAM; - } - - HSL_REG_ENTRY_GET(rv, dev_id, PORT_VLAN1, port_id, - (a_uint8_t *) (®), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - - SW_GET_FIELD_BY_REG(PORT_VLAN1, PROPAGATION_EN, p, reg); - SW_GET_FIELD_BY_REG(PORT_VLAN1, CLONE, c, reg); - - if (p) - { - if (c) - { - *mode = FAL_VLAN_PROPAGATION_CLONE; - } - else - { - *mode = FAL_VLAN_PROPAGATION_REPLACE; - } - } - else - { - *mode = FAL_VLAN_PROPAGATION_DISABLE; - } - - return SW_OK; -} -#endif - -static sw_error_t -_isisc_vlan_trans_read(a_uint32_t dev_id, a_uint32_t entry_idx, - fal_pbmp_t * pbmp, fal_vlan_trans_entry_t * entry) -{ - sw_error_t rv; - a_uint32_t i, addr, dir, table[2] = {0}; - - *pbmp = 0; - aos_mem_zero(entry, sizeof (fal_vlan_trans_entry_t)); - - addr = ISISC_VLAN_TRANS_ADDR + (entry_idx << 3); - /* get vlan trans table */ - for (i = 0; i < 2; i++) - { - HSL_REG_ENTRY_GEN_GET(rv, dev_id, addr + (i << 2), sizeof (a_uint32_t), - (a_uint8_t *) (&(table[i])), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - } - - dir = 0x3 & (table[1] >> 4); - if (!dir) - { - return SW_EMPTY; - } - - entry->o_vid = table[0] & 0xfff; - *pbmp = (table[1] >> 6) & 0x7f; - - if (3 == dir) - { - entry->bi_dir = A_TRUE; - entry->forward_dir = A_TRUE; - entry->reverse_dir = A_TRUE; - } - else if (1 == dir) - { - entry->bi_dir = A_FALSE; - entry->forward_dir = A_TRUE; - entry->reverse_dir = A_FALSE; - } - else - { - entry->bi_dir = A_FALSE; - entry->forward_dir = A_FALSE; - entry->reverse_dir = A_TRUE; - } - - entry->o_vid_is_cvid = (table[1] >> 13) & 0x1UL; - entry->one_2_one_vlan = (table[1] >> 16) & 0x1UL; - entry->s_vid_enable = (table[1] >> 14) & 0x1UL; - entry->c_vid_enable = (table[1] >> 15) & 0x1UL; - - if (A_TRUE == entry->s_vid_enable) - { - entry->s_vid = (table[0] >> 12) & 0xfff; - } - - if (A_TRUE == entry->c_vid_enable) - { - entry->c_vid = ((table[0] >> 24) & 0xff) | ((table[1] & 0xf) << 8); - } - - return SW_OK; -} - - - -static sw_error_t -_isisc_port_vlan_trans_convert(fal_vlan_trans_entry_t * entry, - fal_vlan_trans_entry_t * local) -{ - aos_mem_copy(local, entry, sizeof (fal_vlan_trans_entry_t)); - - if ((A_TRUE == local->bi_dir) - || ((A_TRUE == local->forward_dir) - && (A_TRUE == local->reverse_dir))) - { - local->bi_dir = A_TRUE; - local->forward_dir = A_TRUE; - local->reverse_dir = A_TRUE; - } - - if (A_FALSE == local->s_vid_enable) - { - local->s_vid = 0; - } - - if (A_FALSE == local->c_vid_enable) - { - local->c_vid = 0; - } - - return SW_OK; -} - -static sw_error_t -_isisc_port_vlan_trans_add(a_uint32_t dev_id, fal_port_t port_id, - fal_vlan_trans_entry_t * entry) -{ - sw_error_t rv; - fal_pbmp_t t_pbmp; - a_uint32_t idx, entry_idx = ISISC_MAX_VLAN_TRANS; - fal_vlan_trans_entry_t temp, local; - - HSL_DEV_ID_CHECK(dev_id); - - if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU)) - { - return SW_BAD_PARAM; - } - - if (NULL == entry) - { - return SW_BAD_PTR; - } - aos_mem_zero(&local, sizeof(fal_vlan_trans_entry_t)); - rv = _isisc_port_vlan_trans_convert(entry, &local); - SW_RTN_ON_ERROR(rv); - - for (idx = 0; idx < ISISC_MAX_VLAN_TRANS; idx++) - { - rv = _isisc_vlan_trans_read(dev_id, idx, &t_pbmp, &temp); - if (SW_EMPTY == rv) - { - entry_idx = idx; - continue; - } - SW_RTN_ON_ERROR(rv); - - if (!aos_mem_cmp(&local, &temp, sizeof (fal_vlan_trans_entry_t))) - { - if (SW_IS_PBMP_MEMBER(t_pbmp, port_id)) - { - return SW_ALREADY_EXIST; - } - entry_idx = idx; - break; - } - else - { - t_pbmp = 0; - } - } - - if (ISISC_MAX_VLAN_TRANS != entry_idx) - { - t_pbmp |= (0x1 << port_id); - } - else - { - return SW_NO_RESOURCE; - } - - return _isisc_vlan_trans_write(dev_id, entry_idx, t_pbmp, local); -} - -#ifndef IN_PORTVLAN_MINI -static sw_error_t -_isisc_port_vlan_trans_del(a_uint32_t dev_id, fal_port_t port_id, - fal_vlan_trans_entry_t * entry) -{ - sw_error_t rv; - fal_pbmp_t t_pbmp; - a_uint32_t idx, entry_idx = ISISC_MAX_VLAN_TRANS; - fal_vlan_trans_entry_t temp, local; - - HSL_DEV_ID_CHECK(dev_id); - - if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU)) - { - return SW_BAD_PARAM; - } - - if (NULL == entry) - { - return SW_BAD_PTR; - } - aos_mem_zero(&local, sizeof(fal_vlan_trans_entry_t)); - rv = _isisc_port_vlan_trans_convert(entry, &local); - SW_RTN_ON_ERROR(rv); - - for (idx = 0; idx < ISISC_MAX_VLAN_TRANS; idx++) - { - rv = _isisc_vlan_trans_read(dev_id, idx, &t_pbmp, &temp); - if (SW_EMPTY == rv) - { - continue; - } - SW_RTN_ON_ERROR(rv); - - if (!aos_mem_cmp(&temp, &local, sizeof (fal_vlan_trans_entry_t))) - { - if (SW_IS_PBMP_MEMBER(t_pbmp, port_id)) - { - entry_idx = idx; - break; - } - } - } - - if (ISISC_MAX_VLAN_TRANS != entry_idx) - { - t_pbmp &= (~(0x1 << port_id)); - } - else - { - return SW_NOT_FOUND; - } - - return _isisc_vlan_trans_write(dev_id, entry_idx, t_pbmp, local); -} - -static sw_error_t -_isisc_port_vlan_trans_get(a_uint32_t dev_id, fal_port_t port_id, - fal_vlan_trans_entry_t * entry) -{ - sw_error_t rv; - fal_pbmp_t t_pbmp; - a_uint32_t idx; - fal_vlan_trans_entry_t temp, local; - - HSL_DEV_ID_CHECK(dev_id); - - if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU)) - { - return SW_BAD_PARAM; - } - - if (NULL == entry) - { - return SW_BAD_PTR; - } - aos_mem_zero(&local, sizeof(fal_vlan_trans_entry_t)); - rv = _isisc_port_vlan_trans_convert(entry, &local); - SW_RTN_ON_ERROR(rv); - - for (idx = 0; idx < ISISC_MAX_VLAN_TRANS; idx++) - { - rv = _isisc_vlan_trans_read(dev_id, idx, &t_pbmp, &temp); - if (SW_EMPTY == rv) - { - continue; - } - SW_RTN_ON_ERROR(rv); - - if (!aos_mem_cmp(&temp, &local, sizeof (fal_vlan_trans_entry_t))) - { - if (SW_IS_PBMP_MEMBER(t_pbmp, port_id)) - { - return SW_OK; - } - } - } - - return SW_NOT_FOUND; -} - -static sw_error_t -_isisc_port_vlan_trans_iterate(a_uint32_t dev_id, fal_port_t port_id, - a_uint32_t * iterator, - fal_vlan_trans_entry_t * entry) -{ - a_uint32_t index; - sw_error_t rv; - fal_vlan_trans_entry_t entry_t; - fal_pbmp_t pbmp_t; - - HSL_DEV_ID_CHECK(dev_id); - - if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU)) - { - return SW_BAD_PARAM; - } - - if ((NULL == iterator) || (NULL == entry)) - { - return SW_BAD_PTR; - } - - if (ISISC_MAX_VLAN_TRANS < *iterator) - { - return SW_BAD_PARAM; - } - - for (index = *iterator; index < ISISC_MAX_VLAN_TRANS; index++) - { - rv = _isisc_vlan_trans_read(dev_id, index, &pbmp_t, &entry_t); - if (SW_EMPTY == rv) - { - continue; - } - - if (SW_IS_PBMP_MEMBER(pbmp_t, port_id)) - { - aos_mem_copy(entry, &entry_t, sizeof (fal_vlan_trans_entry_t)); - break; - } - } - - if (ISISC_MAX_VLAN_TRANS == index) - { - return SW_NO_MORE; - } - - *iterator = index + 1; - return SW_OK; -} -#endif - -static sw_error_t -_isisc_qinq_mode_set(a_uint32_t dev_id, fal_qinq_mode_t mode) -{ - sw_error_t rv; - a_uint32_t stag = 0; - - HSL_DEV_ID_CHECK(dev_id); - - if (FAL_QINQ_MODE_BUTT <= mode) - { - return SW_BAD_PARAM; - } - - if (FAL_QINQ_STAG_MODE == mode) - { - stag = 1; - } - - HSL_REG_FIELD_SET(rv, dev_id, SERVICE_TAG, 0, - STAG_MODE, (a_uint8_t *) (&stag), sizeof (a_uint32_t)); - - return rv; -} - -#ifndef IN_PORTVLAN_MINI -static sw_error_t -_isisc_qinq_mode_get(a_uint32_t dev_id, fal_qinq_mode_t * mode) -{ - sw_error_t rv; - a_uint32_t stag = 0; - - HSL_DEV_ID_CHECK(dev_id); - - HSL_REG_FIELD_GET(rv, dev_id, SERVICE_TAG, 0, - STAG_MODE, (a_uint8_t *) (&stag), sizeof (a_uint32_t)); - - SW_RTN_ON_ERROR(rv); - - if (stag) - { - *mode = FAL_QINQ_STAG_MODE; - } - else - { - *mode = FAL_QINQ_CTAG_MODE; - } - - return SW_OK; -} -#endif - -static sw_error_t -_isisc_port_qinq_role_set(a_uint32_t dev_id, fal_port_t port_id, - fal_qinq_port_role_t role) -{ - sw_error_t rv; - a_uint32_t core = 0; - - HSL_DEV_ID_CHECK(dev_id); - - if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU)) - { - return SW_BAD_PARAM; - } - - if (FAL_QINQ_PORT_ROLE_BUTT <= role) - { - return SW_BAD_PARAM; - } - - if (FAL_QINQ_CORE_PORT == role) - { - core = 1; - } - - HSL_REG_FIELD_SET(rv, dev_id, PORT_VLAN1, port_id, - COREP_EN, (a_uint8_t *) (&core), sizeof (a_uint32_t)); - - SW_RTN_ON_ERROR(rv); - - rv = _isisc_port_route_defv_set(dev_id, port_id); - return rv; -} - -#ifndef IN_PORTVLAN_MINI -static sw_error_t -_isisc_port_qinq_role_get(a_uint32_t dev_id, fal_port_t port_id, - fal_qinq_port_role_t * role) -{ - sw_error_t rv; - a_uint32_t core = 0; - - HSL_DEV_ID_CHECK(dev_id); - - if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU)) - { - return SW_BAD_PARAM; - } - - HSL_REG_FIELD_GET(rv, dev_id, PORT_VLAN1, port_id, - COREP_EN, (a_uint8_t *) (&core), sizeof (a_uint32_t)); - - SW_RTN_ON_ERROR(rv); - - if (core) - { - *role = FAL_QINQ_CORE_PORT; - } - else - { - *role = FAL_QINQ_EDGE_PORT; - } - - return SW_OK; -} - -static sw_error_t -_isisc_port_mac_vlan_xlt_set(a_uint32_t dev_id, fal_port_t port_id, - a_bool_t enable) -{ - sw_error_t rv; - a_uint32_t val; - - HSL_DEV_ID_CHECK(dev_id); - - if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU)) - { - return SW_BAD_PARAM; - } - - if (A_TRUE == enable) - { - val = 1; - } - else if (A_FALSE == enable) - { - val = 0; - } - else - { - return SW_BAD_PARAM; - } - - HSL_REG_FIELD_SET(rv, dev_id, PRI_CTL, port_id, - EG_MAC_BASE_VLAN_EN, (a_uint8_t *) (&val), sizeof (a_uint32_t)); - return rv; - -} - -static sw_error_t -_isisc_port_mac_vlan_xlt_get(a_uint32_t dev_id, fal_port_t port_id, - a_bool_t * enable) -{ - sw_error_t rv; - a_uint32_t val = 0; - - HSL_DEV_ID_CHECK(dev_id); - - if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU)) - { - return SW_BAD_PARAM; - } - - HSL_REG_FIELD_GET(rv, dev_id, PRI_CTL, port_id, - EG_MAC_BASE_VLAN_EN, (a_uint8_t *) (&val), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - - if (1 == val) - { - *enable = A_TRUE; - } - else - { - *enable = A_FALSE; - } - - return SW_OK; -} - -static sw_error_t -_isisc_netisolate_set(a_uint32_t dev_id, a_uint32_t enable) -{ - sw_error_t rv; - a_uint32_t val; - - HSL_DEV_ID_CHECK(dev_id); - - val = enable; - HSL_REG_FIELD_SET(rv, dev_id, VLAN_TRANS, 0, - NET_ISO, (a_uint8_t *) (&val), sizeof (a_uint32_t)); - return rv; -} - -static sw_error_t -_isisc_netisolate_get(a_uint32_t dev_id, a_uint32_t * enable) -{ - sw_error_t rv; - a_uint32_t val = 0; - - HSL_DEV_ID_CHECK(dev_id); - - HSL_REG_FIELD_GET(rv, dev_id, VLAN_TRANS, 0, - NET_ISO, (a_uint8_t *) (&val), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - - *enable = val; - return SW_OK; -} - -static sw_error_t -_isisc_eg_trans_filter_bypass_en_set(a_uint32_t dev_id, a_uint32_t enable) -{ - sw_error_t rv; - a_uint32_t val; - - HSL_DEV_ID_CHECK(dev_id); - - val = enable; - HSL_REG_FIELD_SET(rv, dev_id, VLAN_TRANS, 0, - EG_FLTR_BYPASS_EN, (a_uint8_t *) (&val), sizeof (a_uint32_t)); - return rv; -} - -static sw_error_t -_isisc_eg_trans_filter_bypass_en_get(a_uint32_t dev_id, a_uint32_t * enable) -{ - sw_error_t rv; - a_uint32_t val = 0; - - HSL_DEV_ID_CHECK(dev_id); - - HSL_REG_FIELD_GET(rv, dev_id, VLAN_TRANS, 0, - EG_FLTR_BYPASS_EN, (a_uint8_t *) (&val), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - - *enable = val; - return SW_OK; -} -#endif - - -/** - * @brief Set 802.1q work mode on a particular port. - * @param[in] dev_id device id - * @param[in] port_id port id - * @param[in] port_1qmode 802.1q work mode - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -isisc_port_1qmode_set(a_uint32_t dev_id, fal_port_t port_id, - fal_pt_1qmode_t port_1qmode) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _isisc_port_1qmode_set(dev_id, port_id, port_1qmode); - HSL_API_UNLOCK; - return rv; -} -#ifndef IN_PORTVLAN_MINI -/** - * @brief Get 802.1q work mode on a particular port. - * @param[in] dev_id device id - * @param[in] port_id port id - * @param[out] port_1qmode 802.1q work mode - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -isisc_port_1qmode_get(a_uint32_t dev_id, fal_port_t port_id, - fal_pt_1qmode_t * pport_1qmode) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _isisc_port_1qmode_get(dev_id, port_id, pport_1qmode); - HSL_API_UNLOCK; - return rv; -} -#endif -/** - * @brief Set packets transmitted out vlan tagged mode on a particular port. - * @param[in] dev_id device id - * @param[in] port_id port id - * @param[in] port_egvlanmode packets transmitted out vlan tagged mode - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -isisc_port_egvlanmode_set(a_uint32_t dev_id, fal_port_t port_id, - fal_pt_1q_egmode_t port_egvlanmode) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _isisc_port_egvlanmode_set(dev_id, port_id, port_egvlanmode); - HSL_API_UNLOCK; - return rv; -} -#ifndef IN_PORTVLAN_MINI -/** - * @brief Get packets transmitted out vlan tagged mode on a particular port. - * @param[in] dev_id device id - * @param[in] port_id port id - * @param[out] port_egvlanmode packets transmitted out vlan tagged mode - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -isisc_port_egvlanmode_get(a_uint32_t dev_id, fal_port_t port_id, - fal_pt_1q_egmode_t * pport_egvlanmode) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _isisc_port_egvlanmode_get(dev_id, port_id, pport_egvlanmode); - HSL_API_UNLOCK; - return rv; -} -#endif -/** - * @brief Add member of port based vlan on a particular port. - * @param[in] dev_id device id - * @param[in] port_id port id - * @param[in] mem_port_id port member - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -isisc_portvlan_member_add(a_uint32_t dev_id, fal_port_t port_id, - a_uint32_t mem_port_id) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _isisc_portvlan_member_add(dev_id, port_id, mem_port_id); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Delete member of port based vlan on a particular port. - * @param[in] dev_id device id - * @param[in] port_id port id - * @param[in] mem_port_id port member - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -isisc_portvlan_member_del(a_uint32_t dev_id, fal_port_t port_id, - a_uint32_t mem_port_id) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _isisc_portvlan_member_del(dev_id, port_id, mem_port_id); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Update member of port based vlan on a particular port. - * @param[in] dev_id device id - * @param[in] port_id port id - * @param[in] mem_port_map port members - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -isisc_portvlan_member_update(a_uint32_t dev_id, fal_port_t port_id, - fal_pbmp_t mem_port_map) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _isisc_portvlan_member_update(dev_id, port_id, mem_port_map); - HSL_API_UNLOCK; - return rv; -} -#ifndef IN_PORTVLAN_MINI -/** - * @brief Get member of port based vlan on a particular port. - * @param[in] dev_id device id - * @param[in] port_id port id - * @param[out] mem_port_map port members - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -isisc_portvlan_member_get(a_uint32_t dev_id, fal_port_t port_id, - fal_pbmp_t * mem_port_map) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _isisc_portvlan_member_get(dev_id, port_id, mem_port_map); - HSL_API_UNLOCK; - return rv; -} -#endif -/** - * @brief Set force default vlan id status on a particular port. - * @param[in] dev_id device id - * @param[in] port_id port id - * @param[in] enable A_TRUE or A_FALSE - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -isisc_port_force_default_vid_set(a_uint32_t dev_id, fal_port_t port_id, - a_bool_t enable) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _isisc_port_force_default_vid_set(dev_id, port_id, enable); - HSL_API_UNLOCK; - return rv; -} -#ifndef IN_PORTVLAN_MINI -/** - * @brief Get force default vlan id status on a particular port. - * @param[in] dev_id device id - * @param[in] port_id port id - * @param[out] enable A_TRUE or A_FALSE - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -isisc_port_force_default_vid_get(a_uint32_t dev_id, fal_port_t port_id, - a_bool_t * enable) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _isisc_port_force_default_vid_get(dev_id, port_id, enable); - HSL_API_UNLOCK; - return rv; -} -#endif -/** - * @brief Set force port based vlan status on a particular port. - * @param[in] dev_id device id - * @param[in] port_id port id - * @param[in] enable A_TRUE or A_FALSE - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -isisc_port_force_portvlan_set(a_uint32_t dev_id, fal_port_t port_id, - a_bool_t enable) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _isisc_port_force_portvlan_set(dev_id, port_id, enable); - HSL_API_UNLOCK; - return rv; -} -#ifndef IN_PORTVLAN_MINI -/** - * @brief Get force port based vlan status on a particular port. - * @param[in] dev_id device id - * @param[in] port_id port id - * @param[out] enable A_TRUE or A_FALSE - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -isisc_port_force_portvlan_get(a_uint32_t dev_id, fal_port_t port_id, - a_bool_t * enable) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _isisc_port_force_portvlan_get(dev_id, port_id, enable); - HSL_API_UNLOCK; - return rv; -} -#endif -/** - * @brief Set nest vlan tpid on a particular device. - * @param[in] dev_id device id - * @param[in] tpid tag protocol identification - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -isisc_nestvlan_tpid_set(a_uint32_t dev_id, a_uint32_t tpid) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _isisc_nestvlan_tpid_set(dev_id, tpid); - HSL_API_UNLOCK; - return rv; -} -#ifndef IN_PORTVLAN_MINI -/** - * @brief Get nest vlan tpid on a particular device. - * @param[in] dev_id device id - * @param[out] tpid tag protocol identification - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -isisc_nestvlan_tpid_get(a_uint32_t dev_id, a_uint32_t * tpid) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _isisc_nestvlan_tpid_get(dev_id, tpid); - HSL_API_UNLOCK; - return rv; -} -#endif -/** - * @brief Set ingress vlan mode mode on a particular port. - * @param[in] dev_id device id - * @param[in] port_id port id - * @param[in] mode ingress vlan mode - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -isisc_port_invlan_mode_set(a_uint32_t dev_id, fal_port_t port_id, - fal_pt_invlan_mode_t mode) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _isisc_port_invlan_mode_set(dev_id, port_id, mode); - HSL_API_UNLOCK; - return rv; -} -#ifndef IN_PORTVLAN_MINI -/** - * @brief Get ingress vlan mode mode on a particular port. - * @param[in] dev_id device id - * @param[in] port_id port id - * @param[out] mode ingress vlan mode - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -isisc_port_invlan_mode_get(a_uint32_t dev_id, fal_port_t port_id, - fal_pt_invlan_mode_t * mode) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _isisc_port_invlan_mode_get(dev_id, port_id, mode); - HSL_API_UNLOCK; - return rv; -} -#endif -/** - * @brief Set tls status on a particular port. - * @param[in] dev_id device id - * @param[in] port_id port id - * @param[in] enable A_TRUE or A_FALSE - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -isisc_port_tls_set(a_uint32_t dev_id, fal_port_t port_id, a_bool_t enable) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _isisc_port_tls_set(dev_id, port_id, enable); - HSL_API_UNLOCK; - return rv; -} -#ifndef IN_PORTVLAN_MINI - - -/** - * @brief Get tls status on a particular port. - * @param[in] dev_id device id - * @param[in] port_id port id - * @param[out] enable A_TRUE or A_FALSE - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -isisc_port_tls_get(a_uint32_t dev_id, fal_port_t port_id, a_bool_t * enable) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _isisc_port_tls_get(dev_id, port_id, enable); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Set priority propagation status on a particular port. - * @param[in] dev_id device id - * @param[in] port_id port id - * @param[in] enable A_TRUE or A_FALSE - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -isisc_port_pri_propagation_set(a_uint32_t dev_id, fal_port_t port_id, - a_bool_t enable) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _isisc_port_pri_propagation_set(dev_id, port_id, enable); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Get priority propagation status on a particular port. - * @param[in] dev_id device id - * @param[in] port_id port id - * @param[out] enable A_TRUE or A_FALSE - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -isisc_port_pri_propagation_get(a_uint32_t dev_id, fal_port_t port_id, - a_bool_t * enable) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _isisc_port_pri_propagation_get(dev_id, port_id, enable); - HSL_API_UNLOCK; - return rv; -} -#endif -/** - * @brief Set default s-vid on a particular port. - * @param[in] dev_id device id - * @param[in] port_id port id - * @param[in] vid s-vid - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -isisc_port_default_svid_set(a_uint32_t dev_id, fal_port_t port_id, - a_uint32_t vid) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _isisc_port_default_svid_set(dev_id, port_id, vid); - HSL_API_UNLOCK; - return rv; -} -#ifndef IN_PORTVLAN_MINI -/** - * @brief Get default s-vid on a particular port. - * @param[in] dev_id device id - * @param[in] port_id port id - * @param[out] vid s-vid - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -isisc_port_default_svid_get(a_uint32_t dev_id, fal_port_t port_id, - a_uint32_t * vid) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _isisc_port_default_svid_get(dev_id, port_id, vid); - HSL_API_UNLOCK; - return rv; -} -#endif -/** - * @brief Set default c-vid on a particular port. - * @param[in] dev_id device id - * @param[in] port_id port id - * @param[in] vid c-vid - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -isisc_port_default_cvid_set(a_uint32_t dev_id, fal_port_t port_id, - a_uint32_t vid) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _isisc_port_default_cvid_set(dev_id, port_id, vid); - HSL_API_UNLOCK; - return rv; -} -#ifndef IN_PORTVLAN_MINI -/** - * @brief Get default c-vid on a particular port. - * @param[in] dev_id device id - * @param[in] port_id port id - * @param[out] vid c-vid - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -isisc_port_default_cvid_get(a_uint32_t dev_id, fal_port_t port_id, - a_uint32_t * vid) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _isisc_port_default_cvid_get(dev_id, port_id, vid); - HSL_API_UNLOCK; - return rv; -} -#endif -/** - * @brief Set vlan propagation status on a particular port. - * @param[in] dev_id device id - * @param[in] port_id port id - * @param[in] mode vlan propagation mode - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -isisc_port_vlan_propagation_set(a_uint32_t dev_id, fal_port_t port_id, - fal_vlan_propagation_mode_t mode) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _isisc_port_vlan_propagation_set(dev_id, port_id, mode); - HSL_API_UNLOCK; - return rv; -} -#ifndef IN_PORTVLAN_MINI - - -/** - * @brief Get vlan propagation status on a particular port. - * @param[in] dev_id device id - * @param[in] port_id port id - * @param[out] mode vlan propagation mode - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -isisc_port_vlan_propagation_get(a_uint32_t dev_id, fal_port_t port_id, - fal_vlan_propagation_mode_t * mode) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _isisc_port_vlan_propagation_get(dev_id, port_id, mode); - HSL_API_UNLOCK; - return rv; -} -#endif - -/** - * @brief Add a vlan translation entry to a particular port. - * @param[in] dev_id device id - * @param[in] port_id port id - * @param entry vlan translation entry - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -isisc_port_vlan_trans_add(a_uint32_t dev_id, fal_port_t port_id, - fal_vlan_trans_entry_t * entry) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _isisc_port_vlan_trans_add(dev_id, port_id, entry); - HSL_API_UNLOCK; - return rv; -} - -#ifndef IN_PORTVLAN_MINI -/** - * @brief Delete a vlan translation entry from a particular port. - * @param[in] dev_id device id - * @param[in] port_id port id - * @param entry vlan translation entry - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -isisc_port_vlan_trans_del(a_uint32_t dev_id, fal_port_t port_id, - fal_vlan_trans_entry_t * entry) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _isisc_port_vlan_trans_del(dev_id, port_id, entry); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Get a vlan translation entry from a particular port. - * @param[in] dev_id device id - * @param[in] port_id port id - * @param entry vlan translation entry - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -isisc_port_vlan_trans_get(a_uint32_t dev_id, fal_port_t port_id, - fal_vlan_trans_entry_t * entry) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _isisc_port_vlan_trans_get(dev_id, port_id, entry); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Iterate all vlan translation entries from a particular port. - * @param[in] dev_id device id - * @param[in] port_id port id - * @param[in] iterator translation entry index if it's zero means get the first entry - * @param[out] iterator next valid translation entry index - * @param[out] entry vlan translation entry - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -isisc_port_vlan_trans_iterate(a_uint32_t dev_id, fal_port_t port_id, - a_uint32_t * iterator, - fal_vlan_trans_entry_t * entry) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _isisc_port_vlan_trans_iterate(dev_id, port_id, iterator, entry); - HSL_API_UNLOCK; - return rv; -} -#endif - -/** - * @brief Set switch qinq work mode on a particular device. - * @param[in] dev_id device id - * @param[in] mode qinq work mode - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -isisc_qinq_mode_set(a_uint32_t dev_id, fal_qinq_mode_t mode) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _isisc_qinq_mode_set(dev_id, mode); - HSL_API_UNLOCK; - return rv; -} - -#ifndef IN_PORTVLAN_MINI -/** - * @brief Get switch qinq work mode on a particular device. - * @param[in] dev_id device id - * @param[out] mode qinq work mode - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -isisc_qinq_mode_get(a_uint32_t dev_id, fal_qinq_mode_t * mode) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _isisc_qinq_mode_get(dev_id, mode); - HSL_API_UNLOCK; - return rv; -} - -#endif -/** - * @brief Set qinq role on a particular port. - * @param[in] dev_id device id - * @param[in] port_id port id - * @param[in] role port role - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -isisc_port_qinq_role_set(a_uint32_t dev_id, fal_port_t port_id, - fal_qinq_port_role_t role) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _isisc_port_qinq_role_set(dev_id, port_id, role); - HSL_API_UNLOCK; - return rv; -} - -#ifndef IN_PORTVLAN_MINI -/** - * @brief Get qinq role on a particular port. - * @param[in] dev_id device id - * @param[in] port_id port id - * @param[out] role port role - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -isisc_port_qinq_role_get(a_uint32_t dev_id, fal_port_t port_id, - fal_qinq_port_role_t * role) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _isisc_port_qinq_role_get(dev_id, port_id, role); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Set MAC_VLAN_XLT status on a particular port. - * @param[in] dev_id device id - * @param[in] port_id port id - * @param[in] role port role - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -isisc_port_mac_vlan_xlt_set(a_uint32_t dev_id, fal_port_t port_id, - a_bool_t enable) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _isisc_port_mac_vlan_xlt_set(dev_id, port_id, enable); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Get MAC_VLAN_XLT status on a particular port. - * @param[in] dev_id device id - * @param[in] port_id port id - * @param[out] role port role - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -isisc_port_mac_vlan_xlt_get(a_uint32_t dev_id, fal_port_t port_id, - a_bool_t * enable) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _isisc_port_mac_vlan_xlt_get(dev_id, port_id, enable); - HSL_API_UNLOCK; - return rv; -} - -#ifdef HSL_STANDALONG -HSL_LOCAL sw_error_t -isisc_port_route_defv_set(a_uint32_t dev_id, fal_port_t port_id) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv =_isisc_port_route_defv_set(dev_id, port_id); - HSL_API_UNLOCK; - return rv; -} -#endif - -/** - * @brief Set NET_ISOLATE_EN - * @param[in] dev_id device id - * @param[in] role port role - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -isisc_netisolate_set(a_uint32_t dev_id, a_bool_t enable) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _isisc_netisolate_set(dev_id, enable); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Get NET_ISOLATE_EN status - * @param[in] dev_id device id - * @param[out] role port role - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -isisc_netisolate_get(a_uint32_t dev_id, a_bool_t *enable) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _isisc_netisolate_get(dev_id, enable); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Set egress translation filter bypass enable - * @param[in] dev_id device id - * @param[in] enable A_TRUE or A_FALSE - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -isisc_eg_trans_filter_bypass_en_set(a_uint32_t dev_id, a_bool_t enable) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _isisc_eg_trans_filter_bypass_en_set(dev_id, enable); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Get egress translation filter bypass enable - * @param[in] dev_id device id - * @param[in] enable A_TRUE or A_FALSE - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -isisc_eg_trans_filter_bypass_en_get(a_uint32_t dev_id, a_bool_t* enable) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _isisc_eg_trans_filter_bypass_en_get(dev_id, enable); - HSL_API_UNLOCK; - return rv; -} -#endif - - -sw_error_t -isisc_portvlan_init(a_uint32_t dev_id) -{ - a_uint32_t i; - sw_error_t rv; - fal_vlan_trans_entry_t entry_init; - hsl_api_t *p_api; - - HSL_DEV_ID_CHECK(dev_id); - - aos_mem_set(&entry_init, 0, sizeof (fal_vlan_trans_entry_t)); - - for (i = 0; i < ISISC_MAX_VLAN_TRANS; i++) - { - rv = _isisc_vlan_trans_write(dev_id, i, 0, entry_init); - SW_RTN_ON_ERROR(rv); - } - -#ifndef HSL_STANDALONG - - SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id)); - - p_api->port_1qmode_set = isisc_port_1qmode_set; - p_api->port_egvlanmode_set = isisc_port_egvlanmode_set; - p_api->portvlan_member_add = isisc_portvlan_member_add; - p_api->portvlan_member_del = isisc_portvlan_member_del; - p_api->portvlan_member_update = isisc_portvlan_member_update; - p_api->port_force_default_vid_set = isisc_port_force_default_vid_set; - p_api->port_force_portvlan_set = isisc_port_force_portvlan_set; - p_api->nestvlan_tpid_set = isisc_nestvlan_tpid_set; - p_api->port_invlan_mode_set = isisc_port_invlan_mode_set; - p_api->port_tls_set = isisc_port_tls_set; - #ifndef IN_PORTVLAN_MINI - p_api->port_1qmode_get = isisc_port_1qmode_get; - p_api->port_egvlanmode_get = isisc_port_egvlanmode_get; - p_api->portvlan_member_get = isisc_portvlan_member_get; - p_api->port_force_default_vid_get = isisc_port_force_default_vid_get; - p_api->port_force_portvlan_get = isisc_port_force_portvlan_get; - p_api->nestvlan_tpid_get = isisc_nestvlan_tpid_get; - p_api->port_invlan_mode_get = isisc_port_invlan_mode_get; - p_api->port_tls_get = isisc_port_tls_get; - p_api->port_pri_propagation_set = isisc_port_pri_propagation_set; - p_api->port_pri_propagation_get = isisc_port_pri_propagation_get; - #endif - p_api->port_default_svid_set = isisc_port_default_svid_set; - p_api->port_default_cvid_set = isisc_port_default_cvid_set; - p_api->port_vlan_propagation_set = isisc_port_vlan_propagation_set; - #ifndef IN_PORTVLAN_MINI - p_api->port_default_cvid_get = isisc_port_default_cvid_get; - p_api->port_default_svid_get = isisc_port_default_svid_get; - p_api->port_vlan_propagation_get = isisc_port_vlan_propagation_get; - p_api->port_vlan_trans_del = isisc_port_vlan_trans_del; - p_api->port_vlan_trans_get = isisc_port_vlan_trans_get; -#endif - p_api->port_vlan_trans_add = isisc_port_vlan_trans_add; - p_api->qinq_mode_set = isisc_qinq_mode_set; - p_api->port_qinq_role_set = isisc_port_qinq_role_set; -#ifndef IN_PORTVLAN_MINI - p_api->port_qinq_role_get = isisc_port_qinq_role_get; - p_api->qinq_mode_get = isisc_qinq_mode_get; - p_api->port_vlan_trans_iterate = isisc_port_vlan_trans_iterate; - p_api->port_mac_vlan_xlt_set = isisc_port_mac_vlan_xlt_set; - p_api->port_mac_vlan_xlt_get = isisc_port_mac_vlan_xlt_get; - p_api->netisolate_set = isisc_netisolate_set; - p_api->netisolate_get = isisc_netisolate_get; - p_api->eg_trans_filter_bypass_en_set = isisc_eg_trans_filter_bypass_en_set; - p_api->eg_trans_filter_bypass_en_get = isisc_eg_trans_filter_bypass_en_get; - #endif -#endif - - return SW_OK; -} - -/** - * @} - */ diff --git a/feeds/ipq807x/qca-ssdk/src/src/hsl/isisc/isisc_qos.c b/feeds/ipq807x/qca-ssdk/src/src/hsl/isisc/isisc_qos.c deleted file mode 100755 index e62d75eb2..000000000 --- a/feeds/ipq807x/qca-ssdk/src/src/hsl/isisc/isisc_qos.c +++ /dev/null @@ -1,1639 +0,0 @@ -/* - * Copyright (c) 2012, 2016, The Linux Foundation. All rights reserved. - * Permission to use, copy, modify, and/or distribute this software for - * any purpose with or without fee is hereby granted, provided that the - * above copyright notice and this permission notice appear in all copies. - * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES - * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR - * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES - * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN - * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT - * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. - */ - - -/** - * @defgroup isisc_qos ISISC_QOS - * @{ - */ -#include "sw.h" -#include "hsl.h" -#include "hsl_dev.h" -#include "hsl_port_prop.h" -#include "isisc_qos.h" -#include "isisc_reg.h" - -#define ISISC_QOS_QUEUE_TX_BUFFER_MAX 120 -#define ISISC_QOS_PORT_TX_BUFFER_MAX 504 -#define ISISC_QOS_PORT_RX_BUFFER_MAX 120 - -#define ISISC_QOS_HOL_STEP 8 -#define ISISC_QOS_HOL_MOD 3 - -//#define ISISC_MIN_QOS_MODE_PRI 0 -#define ISISC_MAX_QOS_MODE_PRI 3 -#define ISISC_MAX_PRI 7 -#define ISISC_MAX_QUEUE 3 -#define ISISC_MAX_EH_QUEUE 5 - -static sw_error_t -_isisc_qos_port_queue_check(fal_port_t port_id, fal_queue_t queue_id) -{ - if ((0 == port_id) || (5 == port_id) || (6 == port_id)) - { - if (ISISC_MAX_EH_QUEUE < queue_id) - { - return SW_BAD_PARAM; - } - } - else - { - if (ISISC_MAX_QUEUE < queue_id) - { - return SW_BAD_PARAM; - } - } - - return SW_OK; -} - - -#ifndef IN_QOS_MINI -static sw_error_t -_isisc_qos_queue_tx_buf_status_set(a_uint32_t dev_id, fal_port_t port_id, - a_bool_t enable) -{ - a_uint32_t val = 0; - sw_error_t rv; - - if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU)) - { - return SW_BAD_PARAM; - } - - if (A_TRUE == enable) - { - val = 1; - } - else if (A_FALSE == enable) - { - val = 0; - } - else - { - return SW_BAD_PARAM; - } - - HSL_REG_FIELD_SET(rv, dev_id, PORT_HOL_CTL1, port_id, QUEUE_DESC_EN, - (a_uint8_t *) (&val), sizeof (a_uint32_t)); - return rv; -} - -static sw_error_t -_isisc_qos_queue_tx_buf_status_get(a_uint32_t dev_id, fal_port_t port_id, - a_bool_t * enable) -{ - a_uint32_t val = 0; - sw_error_t rv; - - if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU)) - { - return SW_BAD_PARAM; - } - - HSL_REG_FIELD_GET(rv, dev_id, PORT_HOL_CTL1, port_id, QUEUE_DESC_EN, - (a_uint8_t *) (&val), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - - if (1 == val) - { - *enable = A_TRUE; - } - else - { - *enable = A_FALSE; - } - - return SW_OK; -} - -static sw_error_t -_isisc_qos_port_tx_buf_status_set(a_uint32_t dev_id, fal_port_t port_id, - a_bool_t enable) -{ - a_uint32_t val = 0; - sw_error_t rv; - - if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU)) - { - return SW_BAD_PARAM; - } - - if (A_TRUE == enable) - { - val = 1; - } - else if (A_FALSE == enable) - { - val = 0; - } - else - { - return SW_BAD_PARAM; - } - - HSL_REG_FIELD_SET(rv, dev_id, PORT_HOL_CTL1, port_id, PORT_DESC_EN, - (a_uint8_t *) (&val), sizeof (a_uint32_t)); - return rv; -} - -static sw_error_t -_isisc_qos_port_tx_buf_status_get(a_uint32_t dev_id, fal_port_t port_id, - a_bool_t * enable) -{ - a_uint32_t val = 0; - sw_error_t rv; - - if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU)) - { - return SW_BAD_PARAM; - } - - HSL_REG_FIELD_GET(rv, dev_id, PORT_HOL_CTL1, port_id, PORT_DESC_EN, - (a_uint8_t *) (&val), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - - if (1 == val) - { - *enable = A_TRUE; - } - else - { - *enable = A_FALSE; - } - - return SW_OK; -} - - - - -static sw_error_t -_isisc_qos_port_red_en_get(a_uint32_t dev_id, fal_port_t port_id, - a_bool_t * enable) -{ - a_uint32_t val = 0; - sw_error_t rv; - - if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU)) - { - return SW_BAD_PARAM; - } - - HSL_REG_FIELD_GET(rv, dev_id, PORT_HOL_CTL1, port_id, PORT_RED_EN, - (a_uint8_t *) (&val), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - - if (1 == val) - { - *enable = A_TRUE; - } - else - { - *enable = A_FALSE; - } - - return SW_OK; -} - - - - - -static sw_error_t -_isisc_qos_queue_tx_buf_nr_get(a_uint32_t dev_id, fal_port_t port_id, - fal_queue_t queue_id, a_uint32_t * number) -{ - a_uint32_t data = 0, val = 0; - sw_error_t rv; - - if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU)) - { - return SW_BAD_PARAM; - } - - rv = _isisc_qos_port_queue_check(port_id, queue_id); - SW_RTN_ON_ERROR(rv); - - HSL_REG_ENTRY_GET(rv, dev_id, PORT_HOL_CTL0, port_id, (a_uint8_t *) (&data), - sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - - val = (data >> (queue_id << 2)) & 0xf; - *number = val << ISISC_QOS_HOL_MOD; - return SW_OK; -} - - -static sw_error_t -_isisc_qos_port_tx_buf_nr_get(a_uint32_t dev_id, fal_port_t port_id, - a_uint32_t * number) -{ - a_uint32_t val = 0; - sw_error_t rv; - - if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU)) - { - return SW_BAD_PARAM; - } - - HSL_REG_FIELD_GET(rv, dev_id, PORT_HOL_CTL0, port_id, PORT_DESC_NR, - (a_uint8_t *) (&val), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - - *number = val << ISISC_QOS_HOL_MOD; - return SW_OK; -} - - -static sw_error_t -_isisc_qos_port_rx_buf_nr_get(a_uint32_t dev_id, fal_port_t port_id, - a_uint32_t * number) -{ - a_uint32_t val = 0; - sw_error_t rv; - - if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU)) - { - return SW_BAD_PARAM; - } - - HSL_REG_FIELD_GET(rv, dev_id, PORT_HOL_CTL1, port_id, PORT_IN_DESC_EN, - (a_uint8_t *) (&val), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - - *number = val << ISISC_QOS_HOL_MOD; - return SW_OK; -} -#endif -static sw_error_t -_isisc_qos_port_red_en_set(a_uint32_t dev_id, fal_port_t port_id, - a_bool_t enable) -{ - a_uint32_t val = 0; - sw_error_t rv; - - if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU)) - { - return SW_BAD_PARAM; - } - if (A_TRUE == enable) - { - val = 1; - } - else if (A_FALSE == enable) - { - val = 0; - } - else - { - return SW_BAD_PARAM; - } - - HSL_REG_FIELD_SET(rv, dev_id, PORT_HOL_CTL1, port_id, PORT_RED_EN, - (a_uint8_t *) (&val), sizeof (a_uint32_t)); - return rv; -} - -static sw_error_t -_isisc_qos_queue_tx_buf_nr_set(a_uint32_t dev_id, fal_port_t port_id, - fal_queue_t queue_id, a_uint32_t * number) -{ - a_uint32_t data = 0, val = 0; - sw_error_t rv; - - if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU)) - { - return SW_BAD_PARAM; - } - - if (ISISC_QOS_QUEUE_TX_BUFFER_MAX < *number) - { - return SW_BAD_PARAM; - } - - rv = _isisc_qos_port_queue_check(port_id, queue_id); - SW_RTN_ON_ERROR(rv); - - val = *number / ISISC_QOS_HOL_STEP; - *number = val << ISISC_QOS_HOL_MOD; - - HSL_REG_ENTRY_GET(rv, dev_id, PORT_HOL_CTL0, port_id, (a_uint8_t *) (&data), - sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - - data &= (~(0xf << (queue_id << 2))); - data |= (val << (queue_id << 2)); - - HSL_REG_ENTRY_SET(rv, dev_id, PORT_HOL_CTL0, port_id, (a_uint8_t *) (&data), - sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - - return rv; -} - -static sw_error_t -_isisc_qos_port_tx_buf_nr_set(a_uint32_t dev_id, fal_port_t port_id, - a_uint32_t * number) -{ - a_uint32_t val = 0; - sw_error_t rv; - - if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU)) - { - return SW_BAD_PARAM; - } - - if (ISISC_QOS_PORT_TX_BUFFER_MAX < *number) - { - return SW_BAD_PARAM; - } - - val = *number / ISISC_QOS_HOL_STEP; - *number = val << ISISC_QOS_HOL_MOD; - HSL_REG_FIELD_SET(rv, dev_id, PORT_HOL_CTL0, port_id, PORT_DESC_NR, - (a_uint8_t *) (&val), sizeof (a_uint32_t)); - return rv; -} - -static sw_error_t -_isisc_qos_port_rx_buf_nr_set(a_uint32_t dev_id, fal_port_t port_id, - a_uint32_t * number) -{ - a_uint32_t val = 0; - sw_error_t rv; - - if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU)) - { - return SW_BAD_PARAM; - } - - if (ISISC_QOS_PORT_RX_BUFFER_MAX < *number) - { - return SW_BAD_PARAM; - } - - val = *number / ISISC_QOS_HOL_STEP; - *number = val << ISISC_QOS_HOL_MOD; - HSL_REG_FIELD_SET(rv, dev_id, PORT_HOL_CTL1, port_id, PORT_IN_DESC_EN, - (a_uint8_t *) (&val), sizeof (a_uint32_t)); - return rv; -} - -static sw_error_t -_isisc_qos_port_mode_set(a_uint32_t dev_id, fal_port_t port_id, - fal_qos_mode_t mode, a_bool_t enable) -{ - sw_error_t rv; - a_uint32_t val; - - HSL_DEV_ID_CHECK(dev_id); - - if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU)) - { - return SW_BAD_PARAM; - } - - if (A_TRUE == enable) - { - val = 1; - } - else if (A_FALSE == enable) - { - val = 0; - } - else - { - return SW_BAD_PARAM; - } - - if (FAL_QOS_DA_MODE == mode) - { - HSL_REG_FIELD_SET(rv, dev_id, PRI_CTL, port_id, DA_PRI_EN, - (a_uint8_t *) (&val), sizeof (a_uint32_t)); - } - else if (FAL_QOS_UP_MODE == mode) - { - HSL_REG_FIELD_SET(rv, dev_id, PRI_CTL, port_id, VLAN_PRI_EN, - (a_uint8_t *) (&val), sizeof (a_uint32_t)); - } - else if (FAL_QOS_DSCP_MODE == mode) - { - HSL_REG_FIELD_SET(rv, dev_id, PRI_CTL, port_id, IP_PRI_EN, - (a_uint8_t *) (&val), sizeof (a_uint32_t)); - } - else - { - return SW_BAD_PARAM; - } - - return rv; -} - -#ifndef IN_QOS_MINI -static sw_error_t -_isisc_qos_port_mode_get(a_uint32_t dev_id, fal_port_t port_id, - fal_qos_mode_t mode, a_bool_t * enable) -{ - sw_error_t rv; - a_uint32_t val = 0; - - HSL_DEV_ID_CHECK(dev_id); - - if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU)) - { - return SW_BAD_PARAM; - } - - if (FAL_QOS_DA_MODE == mode) - { - HSL_REG_FIELD_GET(rv, dev_id, PRI_CTL, port_id, DA_PRI_EN, - (a_uint8_t *) (&val), sizeof (a_uint32_t)); - } - else if (FAL_QOS_UP_MODE == mode) - { - HSL_REG_FIELD_GET(rv, dev_id, PRI_CTL, port_id, VLAN_PRI_EN, - (a_uint8_t *) (&val), sizeof (a_uint32_t)); - } - else if (FAL_QOS_DSCP_MODE == mode) - { - HSL_REG_FIELD_GET(rv, dev_id, PRI_CTL, port_id, IP_PRI_EN, - (a_uint8_t *) (&val), sizeof (a_uint32_t)); - } - else - { - return SW_BAD_PARAM; - } - SW_RTN_ON_ERROR(rv); - - if (1 == val) - { - *enable = A_TRUE; - } - else - { - *enable = A_FALSE; - } - - return SW_OK; -} - -static sw_error_t -_isisc_qos_port_mode_pri_set(a_uint32_t dev_id, fal_port_t port_id, - fal_qos_mode_t mode, a_uint32_t pri) -{ - sw_error_t rv; - a_uint32_t val = 0; - - HSL_DEV_ID_CHECK(dev_id); - - if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU)) - { - return SW_BAD_PARAM; - } - - if (ISISC_MAX_QOS_MODE_PRI < pri) - { - return SW_BAD_PARAM; - } - - HSL_REG_ENTRY_GET(rv, dev_id, PRI_CTL, port_id, (a_uint8_t *) (&val), - sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - - if (FAL_QOS_DA_MODE == mode) - { - SW_SET_REG_BY_FIELD(PRI_CTL, DA_PRI_SEL, pri, val); - } - else if (FAL_QOS_UP_MODE == mode) - { - SW_SET_REG_BY_FIELD(PRI_CTL, VLAN_PRI_SEL, pri, val); - } - else if (FAL_QOS_DSCP_MODE == mode) - { - SW_SET_REG_BY_FIELD(PRI_CTL, IP_PRI_SEL, pri, val); - } - else - { - return SW_NOT_SUPPORTED; - } - - HSL_REG_ENTRY_SET(rv, dev_id, PRI_CTL, port_id, (a_uint8_t *) (&val), - sizeof (a_uint32_t)); - return rv; -} - -static sw_error_t -_isisc_qos_port_mode_pri_get(a_uint32_t dev_id, fal_port_t port_id, - fal_qos_mode_t mode, a_uint32_t * pri) -{ - sw_error_t rv; - a_uint32_t entry = 0, f_val; - - HSL_DEV_ID_CHECK(dev_id); - - if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU)) - { - return SW_BAD_PARAM; - } - - HSL_REG_ENTRY_GET(rv, dev_id, PRI_CTL, port_id, (a_uint8_t *) (&entry), - sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - - if (FAL_QOS_DA_MODE == mode) - { - SW_GET_FIELD_BY_REG(PRI_CTL, DA_PRI_SEL, f_val, entry); - } - else if (FAL_QOS_UP_MODE == mode) - { - SW_GET_FIELD_BY_REG(PRI_CTL, VLAN_PRI_SEL, f_val, entry); - } - else if (FAL_QOS_DSCP_MODE == mode) - { - SW_GET_FIELD_BY_REG(PRI_CTL, IP_PRI_SEL, f_val, entry); - } - else - { - return SW_NOT_SUPPORTED; - } - - *pri = f_val; - return SW_OK; -} - -static sw_error_t -_isisc_qos_port_sch_mode_set(a_uint32_t dev_id, a_uint32_t port_id, - fal_sch_mode_t mode, const a_uint32_t weight[]) -{ - sw_error_t rv; - a_uint32_t reg = 0, val, w[6] = { 0 }; - a_int32_t i, _index; - - HSL_DEV_ID_CHECK(dev_id); - - if (FAL_SCH_SP_MODE == mode) - { - val = 0; - _index = -1; - } - else if (FAL_SCH_WRR_MODE == mode) - { - val = 3; - _index = 5; - } - else if (FAL_SCH_MIX_MODE == mode) - { - val = 1; - _index = 4; - } - else if (FAL_SCH_MIX_PLUS_MODE == mode) - { - val = 2; - _index = 3; - } - else - { - return SW_NOT_SUPPORTED; - } - - for (i = _index; i >= 0; i--) - { - if (weight[i] > 0x1f) - { - return SW_BAD_PARAM; - } - w[i] = weight[i]; - } - - HSL_REG_ENTRY_GET(rv, dev_id, WRR_CTRL, port_id, (a_uint8_t *) (®), - sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - - SW_SET_REG_BY_FIELD(WRR_CTRL, SCH_MODE, val, reg); - SW_SET_REG_BY_FIELD(WRR_CTRL, Q5_W, w[5], reg); - SW_SET_REG_BY_FIELD(WRR_CTRL, Q4_W, w[4], reg); - SW_SET_REG_BY_FIELD(WRR_CTRL, Q3_W, w[3], reg); - SW_SET_REG_BY_FIELD(WRR_CTRL, Q2_W, w[2], reg); - SW_SET_REG_BY_FIELD(WRR_CTRL, Q1_W, w[1], reg); - SW_SET_REG_BY_FIELD(WRR_CTRL, Q0_W, w[0], reg); - - HSL_REG_ENTRY_SET(rv, dev_id, WRR_CTRL, port_id, - (a_uint8_t *) (®), sizeof (a_uint32_t)); - return rv; -} - -static sw_error_t -_isisc_qos_port_sch_mode_get(a_uint32_t dev_id, a_uint32_t port_id, - fal_sch_mode_t * mode, a_uint32_t weight[]) -{ - sw_error_t rv; - a_uint32_t val = 0, sch, w[6], i; - - HSL_DEV_ID_CHECK(dev_id); - - HSL_REG_ENTRY_GET(rv, dev_id, WRR_CTRL, port_id, (a_uint8_t *) (&val), - sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - - SW_GET_FIELD_BY_REG(WRR_CTRL, SCH_MODE, sch, val); - SW_GET_FIELD_BY_REG(WRR_CTRL, Q5_W, w[5], val); - SW_GET_FIELD_BY_REG(WRR_CTRL, Q4_W, w[4], val); - SW_GET_FIELD_BY_REG(WRR_CTRL, Q3_W, w[3], val); - SW_GET_FIELD_BY_REG(WRR_CTRL, Q2_W, w[2], val); - SW_GET_FIELD_BY_REG(WRR_CTRL, Q1_W, w[1], val); - SW_GET_FIELD_BY_REG(WRR_CTRL, Q0_W, w[0], val); - - if (0 == sch) - { - *mode = FAL_SCH_SP_MODE; - } - else if (1 == sch) - { - *mode = FAL_SCH_MIX_MODE; - } - else if (2 == sch) - { - *mode = FAL_SCH_MIX_PLUS_MODE; - } - else - { - *mode = FAL_SCH_WRR_MODE; - } - - for (i = 0; i < 6; i++) - { - weight[i] = w[i]; - } - - return SW_OK; -} - -static sw_error_t -_isisc_qos_port_default_spri_set(a_uint32_t dev_id, fal_port_t port_id, - a_uint32_t spri) -{ - sw_error_t rv; - a_uint32_t val; - - HSL_DEV_ID_CHECK(dev_id); - - if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU)) - { - return SW_BAD_PARAM; - } - - if (ISISC_MAX_PRI < spri) - { - return SW_BAD_PARAM; - } - - val = spri; - HSL_REG_FIELD_SET(rv, dev_id, PORT_VLAN0, port_id, - ING_SPRI, (a_uint8_t *) (&val), sizeof (a_uint32_t)); - - return rv; -} - -static sw_error_t -_isisc_qos_port_default_spri_get(a_uint32_t dev_id, fal_port_t port_id, - a_uint32_t * spri) -{ - sw_error_t rv; - a_uint32_t val = 0; - - HSL_DEV_ID_CHECK(dev_id); - - if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU)) - { - return SW_BAD_PARAM; - } - - HSL_REG_FIELD_GET(rv, dev_id, PORT_VLAN0, port_id, - ING_SPRI, (a_uint8_t *) (&val), sizeof (a_uint32_t)); - - *spri = val & 0x7; - return rv; -} - -static sw_error_t -_isisc_qos_port_default_cpri_set(a_uint32_t dev_id, fal_port_t port_id, - a_uint32_t cpri) -{ - sw_error_t rv; - a_uint32_t val; - - HSL_DEV_ID_CHECK(dev_id); - - if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU)) - { - return SW_BAD_PARAM; - } - - if (ISISC_MAX_PRI < cpri) - { - return SW_BAD_PARAM; - } - - val = cpri; - HSL_REG_FIELD_SET(rv, dev_id, PORT_VLAN0, port_id, - ING_CPRI, (a_uint8_t *) (&val), sizeof (a_uint32_t)); - - return rv; -} - -HSL_LOCAL sw_error_t -_isisc_qos_port_default_cpri_get(a_uint32_t dev_id, fal_port_t port_id, - a_uint32_t * cpri) -{ - sw_error_t rv; - a_uint32_t val = 0; - - HSL_DEV_ID_CHECK(dev_id); - - if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU)) - { - return SW_BAD_PARAM; - } - - HSL_REG_FIELD_GET(rv, dev_id, PORT_VLAN0, port_id, - ING_CPRI, (a_uint8_t *) (&val), sizeof (a_uint32_t)); - - *cpri = val & 0x7; - return rv; -} - -HSL_LOCAL sw_error_t -_isisc_qos_port_force_spri_status_set(a_uint32_t dev_id, fal_port_t port_id, - a_bool_t enable) -{ - sw_error_t rv; - a_uint32_t val; - - HSL_DEV_ID_CHECK(dev_id); - - if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU)) - { - return SW_BAD_PARAM; - } - - if (A_TRUE == enable) - { - val = 1; - } - else if (A_FALSE == enable) - { - val = 0; - } - else - { - return SW_BAD_PARAM; - } - - HSL_REG_FIELD_SET(rv, dev_id, PORT_VLAN0, port_id, - ING_FORCE_SPRI, (a_uint8_t *) (&val), sizeof (a_uint32_t)); - return rv; -} - -HSL_LOCAL sw_error_t -_isisc_qos_port_force_spri_status_get(a_uint32_t dev_id, fal_port_t port_id, - a_bool_t* enable) -{ - sw_error_t rv; - a_uint32_t val = 0; - - HSL_DEV_ID_CHECK(dev_id); - if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU)) - { - return SW_BAD_PARAM; - } - - HSL_REG_FIELD_GET(rv, dev_id, PORT_VLAN0, port_id, - ING_FORCE_SPRI, (a_uint8_t *) (&val), sizeof (a_uint32_t)); - - if (1 == val) - { - *enable = A_TRUE; - } - else - { - *enable = A_FALSE; - } - - return rv; -} - -HSL_LOCAL sw_error_t -_isisc_qos_port_force_cpri_status_set(a_uint32_t dev_id, fal_port_t port_id, - a_bool_t enable) -{ - sw_error_t rv; - a_uint32_t val; - - HSL_DEV_ID_CHECK(dev_id); - - if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU)) - { - return SW_BAD_PARAM; - } - - val = enable ? 1 : 0; - - HSL_REG_FIELD_SET(rv, dev_id, PORT_VLAN0, port_id, - ING_FORCE_CPRI, (a_uint8_t *) (&val), sizeof (a_uint32_t)); - - return rv; -} - -HSL_LOCAL sw_error_t -_isisc_qos_port_force_cpri_status_get(a_uint32_t dev_id, fal_port_t port_id, - a_bool_t* enable) -{ - sw_error_t rv; - a_uint32_t val = 0; - - HSL_DEV_ID_CHECK(dev_id); - - if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU)) - { - return SW_BAD_PARAM; - } - - HSL_REG_FIELD_GET(rv, dev_id, PORT_VLAN0, port_id, - ING_FORCE_CPRI, (a_uint8_t *) (&val), sizeof (a_uint32_t)); - - if (1 == val) - { - *enable = A_TRUE; - } - else - { - *enable = A_FALSE; - } - - return rv; -} - -static sw_error_t -_isisc_qos_queue_remark_table_set(a_uint32_t dev_id, fal_port_t port_id, - fal_queue_t queue_id, a_uint32_t tbl_id, a_bool_t enable) -{ - sw_error_t rv; - a_uint32_t addr, data = 0; - a_uint32_t base[7] = {0x0c40, 0x0c48, 0x0c4c, 0x0c50, 0x0c54, 0x0c58, 0x0c60}; - - rv = _isisc_qos_port_queue_check(port_id, queue_id); - SW_RTN_ON_ERROR(rv); - - addr = base[port_id] + ((queue_id / 4) << 2); - HSL_REG_ENTRY_GEN_GET(rv, dev_id, addr, sizeof (a_uint32_t), - (a_uint8_t *) (&data), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - - data &= (~(0xff << ((queue_id % 4) << 3))); - data |= (((enable << 7 ) | (tbl_id & 0xf)) << ((queue_id % 4) << 3)); - - HSL_REG_ENTRY_GEN_SET(rv, dev_id, addr, sizeof (a_uint32_t), - (a_uint8_t *) (&data), sizeof (a_uint32_t)); - return rv; -} - -HSL_LOCAL sw_error_t -_isisc_qos_queue_remark_table_get(a_uint32_t dev_id, fal_port_t port_id, - fal_queue_t queue_id, a_uint32_t * tbl_id, a_bool_t * enable) -{ - sw_error_t rv; - a_uint32_t addr, data = 0; - a_uint32_t base[7] = {0x0c40, 0x0c48, 0x0c4c, 0x0c50, 0x0c54, 0x0c58, 0x0c60}; - - rv = _isisc_qos_port_queue_check(port_id, queue_id); - SW_RTN_ON_ERROR(rv); - - addr = base[port_id] + ((queue_id / 4) << 2); - HSL_REG_ENTRY_GEN_GET(rv, dev_id, addr, sizeof (a_uint32_t), - (a_uint8_t *) (&data), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - - *tbl_id = (data >> ((queue_id % 4) << 3)) & 0xf; - *enable = ((data >> ((queue_id % 4) << 3)) & 0x80) >> 7; - return SW_OK; -} - -HSL_LOCAL sw_error_t -_isisc_port_static_thresh_get(a_uint32_t dev_id, fal_port_t port_id, - fal_bm_static_cfg_t *cfg) -{ - sw_error_t rv; - a_uint32_t reg_value, xon_value, xoff_value; - - HSL_REG_ENTRY_GET(rv, dev_id, PORT_FLOW_CTRL_THRESHOLD, port_id, - (a_uint8_t *) (®_value), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - - SW_GET_FIELD_BY_REG(PORT_FLOW_CTRL_THRESHOLD, XON_THRES, xon_value, reg_value); - SW_GET_FIELD_BY_REG(PORT_FLOW_CTRL_THRESHOLD, XOFF_THRES, xoff_value, reg_value); - cfg->max_thresh = xoff_value; - cfg->resume_off = xoff_value - xon_value; - - return SW_OK; -} - -HSL_LOCAL sw_error_t -_isisc_port_static_thresh_set(a_uint32_t dev_id, fal_port_t port_id, - fal_bm_static_cfg_t *cfg) -{ - sw_error_t rv; - a_uint32_t reg_value = 0; - - SW_SET_REG_BY_FIELD(PORT_FLOW_CTRL_THRESHOLD, XON_THRES, cfg->max_thresh - cfg->resume_off, reg_value); - SW_SET_REG_BY_FIELD(PORT_FLOW_CTRL_THRESHOLD, XOFF_THRES, cfg->max_thresh, reg_value); - - HSL_REG_ENTRY_SET(rv, dev_id, PORT_FLOW_CTRL_THRESHOLD, port_id, - (a_uint8_t *) (®_value), sizeof (a_uint32_t)); - - return SW_OK; -} -#endif - -#ifndef IN_QOS_MINI -/** - * @brief Set buffer aggsinment status of transmitting queue on one particular port. - * @details Comments: - * If enable queue tx buffer on one port that means each queue of this port - * will have fixed number buffers when transmitting packets. Otherwise they - * share the whole buffers with other queues in device. - * @param[in] dev_id device id - * @param[in] port_id port id - * @param[in] enable A_TRUE or A_FALSE - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -isisc_qos_queue_tx_buf_status_set(a_uint32_t dev_id, fal_port_t port_id, - a_bool_t enable) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _isisc_qos_queue_tx_buf_status_set(dev_id, port_id, enable); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Get buffer aggsinment status of transmitting queue on particular port. - * @param[in] dev_id device id - * @param[in] port_id port id - * @param[in] enable A_TRUE or A_FALSE - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -isisc_qos_queue_tx_buf_status_get(a_uint32_t dev_id, fal_port_t port_id, - a_bool_t * enable) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _isisc_qos_queue_tx_buf_status_get(dev_id, port_id, enable); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Set buffer aggsinment status of transmitting port on one particular port. - * @details Comments: - If enable tx buffer on one port that means this port will have fixed - number buffers when transmitting packets. Otherwise they will - share the whole buffers with other ports in device. - * function will return actual buffer numbers in hardware. - * @param[in] dev_id device id - * @param[in] port_id port id - * @param[in] enable A_TRUE or A_FALSE - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -isisc_qos_port_tx_buf_status_set(a_uint32_t dev_id, fal_port_t port_id, - a_bool_t enable) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _isisc_qos_port_tx_buf_status_set(dev_id, port_id, enable); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Get buffer aggsinment status of transmitting port on one particular port. - * @param[in] dev_id device id - * @param[in] port_id port id - * @param[out] enable A_TRUE or A_FALSE - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -isisc_qos_port_tx_buf_status_get(a_uint32_t dev_id, fal_port_t port_id, - a_bool_t * enable) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _isisc_qos_port_tx_buf_status_get(dev_id, port_id, enable); - HSL_API_UNLOCK; - return rv; -} - - - -/** - * @brief Set status of port red on one particular port. - * @param[in] dev_id device id - * @param[in] port_id port id - * @param[in] enable A_TRUE or A_FALSE - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -isisc_qos_port_red_en_get(a_uint32_t dev_id, fal_port_t port_id, - a_bool_t* enable) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _isisc_qos_port_red_en_get(dev_id, port_id, enable); - HSL_API_UNLOCK; - return rv; -} - - - - -/** - * @brief Get max occupied buffer number of transmitting queue on one particular port. - * @param[in] dev_id device id - * @param[in] port_id port id - * @param[in] queue_id queue id - * @param[out] number buffer number - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -isisc_qos_queue_tx_buf_nr_get(a_uint32_t dev_id, fal_port_t port_id, - fal_queue_t queue_id, a_uint32_t * number) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _isisc_qos_queue_tx_buf_nr_get(dev_id, port_id, queue_id, number); - HSL_API_UNLOCK; - return rv; -} - - - -/** - * @brief Get max occupied buffer number of transmitting port on one particular port. - * @param[in] dev_id device id - * @param[in] port_id port id - * @param[out] number buffer number - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -isisc_qos_port_tx_buf_nr_get(a_uint32_t dev_id, fal_port_t port_id, - a_uint32_t * number) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _isisc_qos_port_tx_buf_nr_get(dev_id, port_id, number); - HSL_API_UNLOCK; - return rv; -} - - - -/** - * @brief Get max occupied buffer number of receiving port on one particular port. - * @param[in] dev_id device id - * @param[in] port_id port id - * @param[out] number buffer number - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -isisc_qos_port_rx_buf_nr_get(a_uint32_t dev_id, fal_port_t port_id, - a_uint32_t * number) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _isisc_qos_port_rx_buf_nr_get(dev_id, port_id, number); - HSL_API_UNLOCK; - return rv; -} -#endif -/** - * @brief Set status of port red on one particular port. - * @param[in] dev_id device id - * @param[in] port_id port id - * @param[in] enable A_TRUE or A_FALSE - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -isisc_qos_port_red_en_set(a_uint32_t dev_id, fal_port_t port_id, - a_bool_t enable) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _isisc_qos_port_red_en_set(dev_id, port_id, enable); - HSL_API_UNLOCK; - return rv; -} -/** - * @brief Set max occupied buffer number of transmitting queue on one particular port. - * @details Comments: - The step of buffer number in Garuda is 4, function will return actual - buffer numbers in hardware. - The buffer number range for queue is 4 to 60. - * share the whole buffers with other ports in device. - * @param[in] dev_id device id - * @param[in] port_id port id - * @param[in] queue_id queue id - * @param number buffer number - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -isisc_qos_queue_tx_buf_nr_set(a_uint32_t dev_id, fal_port_t port_id, - fal_queue_t queue_id, a_uint32_t * number) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _isisc_qos_queue_tx_buf_nr_set(dev_id, port_id, queue_id, number); - HSL_API_UNLOCK; - return rv; -} -/** - * @brief Set max occupied buffer number of transmitting port on one particular port. - * @details Comments: - The step of buffer number in Garuda is four, function will return actual - buffer numbers in hardware. - The buffer number range for transmitting port is 4 to 124. - * @param[in] dev_id device id - * @param[in] port_id port id - * @param number buffer number - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -isisc_qos_port_tx_buf_nr_set(a_uint32_t dev_id, fal_port_t port_id, - a_uint32_t * number) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _isisc_qos_port_tx_buf_nr_set(dev_id, port_id, number); - HSL_API_UNLOCK; - return rv; -} -/** - * @brief Set max occupied buffer number of receiving port on one particular port. - * @details Comments: - The step of buffer number in Shiva is four, function will return actual - buffer numbers in hardware. - The buffer number range for receiving port is 4 to 60. - * @param[in] dev_id device id - * @param[in] port_id port id - * @param number buffer number - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -isisc_qos_port_rx_buf_nr_set(a_uint32_t dev_id, fal_port_t port_id, - a_uint32_t * number) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _isisc_qos_port_rx_buf_nr_set(dev_id, port_id, number); - HSL_API_UNLOCK; - return rv; -} -/** - * @brief Set port qos mode on a particular port. - * @param[in] dev_id device id - * @param[in] port_id port id - * @param[in] mode qos mode - * @param[in] enable A_TRUE of A_FALSE - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -isisc_qos_port_mode_set(a_uint32_t dev_id, fal_port_t port_id, - fal_qos_mode_t mode, a_bool_t enable) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _isisc_qos_port_mode_set(dev_id, port_id, mode, enable); - HSL_API_UNLOCK; - return rv; -} - - -#ifndef IN_QOS_MINI -/** - * @brief Get port qos mode on a particular port. - * @param[in] dev_id device id - * @param[in] port_id port id - * @param[in] mode qos mode - * @param[out] enable A_TRUE of A_FALSE - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -isisc_qos_port_mode_get(a_uint32_t dev_id, fal_port_t port_id, - fal_qos_mode_t mode, a_bool_t * enable) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _isisc_qos_port_mode_get(dev_id, port_id, mode, enable); - HSL_API_UNLOCK; - return rv; -} -/** - * @brief Set priority of one particular qos mode on one particular port. - * @details Comments: - If the priority of a mode is more small then the priority is more high. - Differnet mode should have differnet priority. - * @param[in] dev_id device id - * @param[in] port_id port id - * @param[in] mode qos mode - * @param[in] pri priority of one particular qos mode - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -isisc_qos_port_mode_pri_set(a_uint32_t dev_id, fal_port_t port_id, - fal_qos_mode_t mode, a_uint32_t pri) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _isisc_qos_port_mode_pri_set(dev_id, port_id, mode, pri); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Get priority of one particular qos mode on one particular port. - * @param[in] dev_id device id - * @param[in] port_id port id - * @param[in] mode qos mode - * @param[out] pri priority of one particular qos mode - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -isisc_qos_port_mode_pri_get(a_uint32_t dev_id, fal_port_t port_id, - fal_qos_mode_t mode, a_uint32_t * pri) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _isisc_qos_port_mode_pri_get(dev_id, port_id, mode, pri); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Set traffic scheduling mode on particular one port. - * @details Comments: - * When scheduling mode is sp the weight is meaningless usually it's zero - * @param[in] dev_id device id - * @param[in] port_id port id - * @param[in] fal_sch_mode_t traffic scheduling mode - * @param[in] weight[] weight value for each queue when in wrr mode, - the max value supported by ISIS is 0x1f. - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -isisc_qos_port_sch_mode_set(a_uint32_t dev_id, a_uint32_t port_id, - fal_sch_mode_t mode, const a_uint32_t weight[]) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _isisc_qos_port_sch_mode_set(dev_id, port_id, mode, weight); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Get traffic scheduling mode on particular port. - * @param[in] dev_id device id - * @param[in] port_id port id - * @param[out] fal_sch_mode_t traffic scheduling mode - * @param[out] weight weight value for wrr mode - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -isisc_qos_port_sch_mode_get(a_uint32_t dev_id, a_uint32_t port_id, - fal_sch_mode_t * mode, a_uint32_t weight[]) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _isisc_qos_port_sch_mode_get(dev_id, port_id, mode, weight); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Set default stag priority on one particular port. - * @param[in] dev_id device id - * @param[in] port_id port id - * @param[in] spri vlan priority - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -isisc_qos_port_default_spri_set(a_uint32_t dev_id, fal_port_t port_id, - a_uint32_t spri) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _isisc_qos_port_default_spri_set(dev_id, port_id, spri); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Get default stag priority on one particular port. - * @param[in] dev_id device id - * @param[in] port_id port id - * @param[out] spri vlan priority - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -isisc_qos_port_default_spri_get(a_uint32_t dev_id, fal_port_t port_id, - a_uint32_t * spri) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _isisc_qos_port_default_spri_get(dev_id, port_id, spri); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Set default ctag priority on one particular port. - * @param[in] dev_id device id - * @param[in] port_id port id - * @param[in] cpri vlan priority - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -isisc_qos_port_default_cpri_set(a_uint32_t dev_id, fal_port_t port_id, - a_uint32_t cpri) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _isisc_qos_port_default_cpri_set(dev_id, port_id, cpri); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Get default ctag priority on one particular port. - * @param[in] dev_id device id - * @param[in] port_id port id - * @param[out] cpri vlan priority - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -isisc_qos_port_default_cpri_get(a_uint32_t dev_id, fal_port_t port_id, - a_uint32_t * cpri) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _isisc_qos_port_default_cpri_get(dev_id, port_id, cpri); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Set port force stag priority enable flag one particular port. - * @param[in] dev_id device id - * @param[in] port_id port id - * @param[in] enable A_TRUE or A_FALSE - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -isisc_qos_port_force_spri_status_set(a_uint32_t dev_id, fal_port_t port_id, - a_bool_t enable) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _isisc_qos_port_force_spri_status_set(dev_id, port_id, enable); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Get port force stag priority enable flag one particular port. - * @param[in] dev_id device id - * @param[in] port_id port id - * @param[out] enable A_TRUE or A_FALSE - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -isisc_qos_port_force_spri_status_get(a_uint32_t dev_id, fal_port_t port_id, - a_bool_t* enable) -{ - sw_error_t rv; - HSL_API_LOCK; - rv = _isisc_qos_port_force_spri_status_get(dev_id, port_id, enable); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Set port force ctag priority enable flag one particular port. - * @param[in] dev_id device id - * @param[in] port_id port id - * @param[in] enable A_TRUE or A_FALSE - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -isisc_qos_port_force_cpri_status_set(a_uint32_t dev_id, fal_port_t port_id, - a_bool_t enable) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _isisc_qos_port_force_cpri_status_set(dev_id, port_id, enable); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Get port force ctag priority enable flag one particular port. - * @param[in] dev_id device id - * @param[in] port_id port id - * @param[out] enable A_TRUE or A_FALSE - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -isisc_qos_port_force_cpri_status_get(a_uint32_t dev_id, fal_port_t port_id, - a_bool_t* enable) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _isisc_qos_port_force_cpri_status_get(dev_id, port_id, enable); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Set egress queue based CoS remark on one particular port. - * @param[in] dev_id device id - * @param[in] port_id port id - * @param[in] queue_id queue id - * @param[in] tbl_id CoS remark table id - * @param[in] enable A_TRUE or A_FALSE - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -isisc_qos_queue_remark_table_set(a_uint32_t dev_id, fal_port_t port_id, - fal_queue_t queue_id, a_uint32_t tbl_id, a_bool_t enable) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _isisc_qos_queue_remark_table_set(dev_id, port_id, queue_id, tbl_id, enable); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Get egress queue based CoS remark on one particular port. - * @param[in] dev_id device id - * @param[in] port_id port id - * @param[in] queue_id queue id - * @param[out] tbl_id CoS remark table id - * @param[out] enable A_TRUE or A_FALSE - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -isisc_qos_queue_remark_table_get(a_uint32_t dev_id, fal_port_t port_id, - fal_queue_t queue_id, a_uint32_t * tbl_id, a_bool_t * enable) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _isisc_qos_queue_remark_table_get(dev_id, port_id, queue_id, tbl_id, enable); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Get static flow control threshold on one particular port. - * @param[in] dev_id device id - * @param[in] port_id port id - * @param[out] static maximum threshold and resume offset - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -isisc_port_static_thresh_get(a_uint32_t dev_id, fal_port_t port_id, - fal_bm_static_cfg_t *cfg) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _isisc_port_static_thresh_get(dev_id, port_id, cfg); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Set static flow control threshold on one particular port. - * @param[in] dev_id device id - * @param[in] port_id port id - * @param[out] static maximum threshold and resume offset - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -isisc_port_static_thresh_set(a_uint32_t dev_id, fal_port_t port_id, - fal_bm_static_cfg_t *cfg) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _isisc_port_static_thresh_set(dev_id, port_id, cfg); - HSL_API_UNLOCK; - return rv; -} -#endif - -sw_error_t -isisc_qos_init(a_uint32_t dev_id) -{ - HSL_DEV_ID_CHECK(dev_id); - -#ifndef HSL_STANDALONG - { - hsl_api_t *p_api; - - SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id)); - p_api->qos_queue_tx_buf_nr_set = isisc_qos_queue_tx_buf_nr_set; - p_api->qos_port_red_en_set = isisc_qos_port_red_en_set; - p_api->qos_port_tx_buf_nr_set = isisc_qos_port_tx_buf_nr_set; - p_api->qos_port_rx_buf_nr_set = isisc_qos_port_rx_buf_nr_set; - #ifndef IN_QOS_MINI - p_api->qos_queue_tx_buf_status_set = isisc_qos_queue_tx_buf_status_set; - p_api->qos_queue_tx_buf_status_get = isisc_qos_queue_tx_buf_status_get; - p_api->qos_port_tx_buf_status_set = isisc_qos_port_tx_buf_status_set; - p_api->qos_port_tx_buf_status_get = isisc_qos_port_tx_buf_status_get; - p_api->qos_port_red_en_get = isisc_qos_port_red_en_get; - p_api->qos_queue_tx_buf_nr_get = isisc_qos_queue_tx_buf_nr_get; - p_api->qos_port_tx_buf_nr_get = isisc_qos_port_tx_buf_nr_get; - p_api->qos_port_rx_buf_nr_get = isisc_qos_port_rx_buf_nr_get; - #endif - p_api->qos_port_mode_set = isisc_qos_port_mode_set; - - #ifndef IN_QOS_MINI - p_api->qos_port_mode_get = isisc_qos_port_mode_get; - p_api->qos_port_mode_pri_set = isisc_qos_port_mode_pri_set; - p_api->qos_port_mode_pri_get = isisc_qos_port_mode_pri_get; - p_api->qos_port_sch_mode_set = isisc_qos_port_sch_mode_set; - p_api->qos_port_sch_mode_get = isisc_qos_port_sch_mode_get; - p_api->qos_port_default_spri_set = isisc_qos_port_default_spri_set; - p_api->qos_port_default_spri_get = isisc_qos_port_default_spri_get; - p_api->qos_port_default_cpri_set = isisc_qos_port_default_cpri_set; - p_api->qos_port_default_cpri_get = isisc_qos_port_default_cpri_get; - p_api->qos_port_force_spri_status_set = isisc_qos_port_force_spri_status_set; - p_api->qos_port_force_spri_status_get = isisc_qos_port_force_spri_status_get; - p_api->qos_port_force_cpri_status_set = isisc_qos_port_force_cpri_status_set; - p_api->qos_port_force_cpri_status_get = isisc_qos_port_force_cpri_status_get; - p_api->qos_queue_remark_table_set = isisc_qos_queue_remark_table_set; - p_api->qos_queue_remark_table_get = isisc_qos_queue_remark_table_get; - p_api->port_static_thresh_get = isisc_port_static_thresh_get; - p_api->port_static_thresh_set = isisc_port_static_thresh_set; - #endif - } -#endif - - return SW_OK; -} - -/** - * @} - */ diff --git a/feeds/ipq807x/qca-ssdk/src/src/hsl/isisc/isisc_rate.c b/feeds/ipq807x/qca-ssdk/src/src/hsl/isisc/isisc_rate.c deleted file mode 100755 index 0cbe6b044..000000000 --- a/feeds/ipq807x/qca-ssdk/src/src/hsl/isisc/isisc_rate.c +++ /dev/null @@ -1,1662 +0,0 @@ -/* - * Copyright (c) 2012, 2016 The Linux Foundation. All rights reserved. - * Permission to use, copy, modify, and/or distribute this software for - * any purpose with or without fee is hereby granted, provided that the - * above copyright notice and this permission notice appear in all copies. - * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES - * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR - * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES - * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN - * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT - * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. - */ - - -/** - * @defgroup isisc_rate ISISC_RATE - * @{ - */ -#include "sw.h" -#include "hsl.h" -#include "hsl_dev.h" -#include "hsl_port_prop.h" -#include "isisc_rate.h" -#include "isisc_reg.h" - -#define ISISC_MAX_POLICER_ID 31 -#define ISISC_MAX_QUEUE 3 -#define ISISC_MAX_EH_QUEUE 5 - -#define ACL_POLICER_CNT_SEL_ADDR 0x09f0 -#define ACL_POLICER_CNT_MODE_ADDR 0x09f4 -#define ACL_POLICER_CNT_RST_ADDR 0x09f8 - -static sw_error_t -_isisc_rate_port_queue_check(fal_port_t port_id, fal_queue_t queue_id) -{ - if ((0 == port_id) || (5 == port_id) || (6 == port_id)) - { - if (ISISC_MAX_EH_QUEUE < queue_id) - { - return SW_BAD_PARAM; - } - } - else - { - if (ISISC_MAX_QUEUE < queue_id) - { - return SW_BAD_PARAM; - } - } - - return SW_OK; -} - -static void -_isisc_egress_bs_byte_sw_to_hw(a_uint32_t sw_bs, a_uint32_t * hw_bs) -{ - a_int32_t i; - a_uint32_t data[8] = - { - 0, 2 * 1024, 4 * 1024, 8 * 1024, 16 * 1024, 32 * 1024, 128 * 1024, - 512 * 1024 - }; - - for (i = 7; i >= 0; i--) - { - if (sw_bs >= data[i]) - { - *hw_bs = i; - break; - } - } -} - -static void -_isisc_egress_bs_byte_hw_to_sw(a_uint32_t hw_bs, a_uint32_t * sw_bs) -{ - a_uint32_t data[8] = - { - 0, 2 * 1024, 4 * 1024, 8 * 1024, 16 * 1024, 32 * 1024, 128 * 1024, - 512 * 1024 - }; - - *sw_bs = data[hw_bs & 0x7]; -} - -static void -_isisc_egress_bs_frame_sw_to_hw(a_uint32_t sw_bs, a_uint32_t * hw_bs) -{ - a_uint32_t data[8] = { 0, 2, 4, 16, 64, 256, 512, 1024 }; - a_int32_t i; - - for (i = 7; i >= 0; i--) - { - if (sw_bs >= data[i]) - { - *hw_bs = i; - break; - } - } -} - -static void -_isisc_egress_bs_frame_hw_to_sw(a_uint32_t hw_bs, a_uint32_t * sw_bs) -{ - a_uint32_t data[8] = { 0, 2, 4, 16, 64, 256, 512, 1024 }; - - *sw_bs = data[hw_bs & 0x7]; -} - -static void -_isisc_ingress_bs_byte_sw_to_hw(a_uint32_t sw_bs, a_uint32_t * hw_bs) -{ - a_int32_t i; - a_uint32_t data[8] = - { - 0, 4 * 1024, 32 * 1024, 128 * 1024, 512 * 1024, 2 * 1024 * 1024, - 8 * 1024 * 1024, 32 * 1024 * 1024 - }; - - for (i = 7; i >= 0; i--) - { - if (sw_bs >= data[i]) - { - *hw_bs = i; - break; - } - } -} - -static void -_isisc_ingress_bs_byte_hw_to_sw(a_uint32_t hw_bs, a_uint32_t * sw_bs) -{ - a_uint32_t data[8] = - { - 0, 4 * 1024, 32 * 1024, 128 * 1024, 512 * 1024, 2 * 1024 * 1024, - 8 * 1024 * 1024, 32 * 1024 * 1024 - }; - - *sw_bs = data[hw_bs & 0x7]; -} - -static void -_isisc_ingress_bs_frame_sw_to_hw(a_uint32_t sw_bs, a_uint32_t * hw_bs) -{ - a_uint32_t data[8] = { 0, 4, 16, 64, 256, 1024, 4096, 16384 }; - a_int32_t i; - - for (i = 7; i >= 0; i--) - { - if (sw_bs >= data[i]) - { - *hw_bs = i; - break; - } - } -} - -static void -_isisc_ingress_bs_frame_hw_to_sw(a_uint32_t hw_bs, a_uint32_t * sw_bs) -{ - a_uint32_t data[8] = { 0, 4, 16, 64, 256, 1024, 4096, 16384 }; - - *sw_bs = data[hw_bs & 0x7]; -} - -static void -_isisc_rate_flag_parse(a_uint32_t sw_flag, a_uint32_t * hw_flag) -{ - *hw_flag = 0; - - if (FAL_INGRESS_POLICING_TCP_CTRL & sw_flag) - { - *hw_flag |= (0x1 << 1); - } - - if (FAL_INGRESS_POLICING_MANAGEMENT & sw_flag) - { - *hw_flag |= (0x1 << 2); - } - - if (FAL_INGRESS_POLICING_BROAD & sw_flag) - { - *hw_flag |= (0x1 << 3); - } - - if (FAL_INGRESS_POLICING_UNK_UNI & sw_flag) - { - *hw_flag |= (0x1 << 4); - } - - if (FAL_INGRESS_POLICING_UNK_MUL & sw_flag) - { - *hw_flag |= (0x1 << 5); - } - - if (FAL_INGRESS_POLICING_UNI & sw_flag) - { - *hw_flag |= (0x1 << 6); - } - - if (FAL_INGRESS_POLICING_MUL & sw_flag) - { - *hw_flag |= (0x1 << 7); - } -} - -static void -_isisc_rate_flag_reparse(a_uint32_t hw_flag, a_uint32_t * sw_flag) -{ - *sw_flag = 0; - - if (hw_flag & 0x2) - { - *sw_flag |= FAL_INGRESS_POLICING_TCP_CTRL; - } - - if (hw_flag & 0x4) - { - *sw_flag |= FAL_INGRESS_POLICING_MANAGEMENT; - } - - if (hw_flag & 0x8) - { - *sw_flag |= FAL_INGRESS_POLICING_BROAD; - } - - if (hw_flag & 0x10) - { - *sw_flag |= FAL_INGRESS_POLICING_UNK_UNI; - } - - if (hw_flag & 0x20) - { - *sw_flag |= FAL_INGRESS_POLICING_UNK_MUL; - } - - if (hw_flag & 0x40) - { - *sw_flag |= FAL_INGRESS_POLICING_UNI; - } - - if (hw_flag & 0x80) - { - *sw_flag |= FAL_INGRESS_POLICING_MUL; - } -} - -static void -_isisc_rate_ts_parse(fal_rate_mt_t sw, a_uint32_t * hw) -{ - if (FAL_RATE_MI_100US == sw) - { - *hw = 0; - } - else if (FAL_RATE_MI_1MS == sw) - { - *hw = 1; - } - else if (FAL_RATE_MI_10MS == sw) - { - *hw = 2; - } - else if (FAL_RATE_MI_100MS) - { - *hw = 3; - } - else - { - *hw = 0; - } -} - -static void -_isisc_rate_ts_reparse(a_uint32_t hw, fal_rate_mt_t * sw) -{ - if (0 == hw) - { - *sw = FAL_RATE_MI_100US; - } - else if (1 == hw) - { - *sw = FAL_RATE_MI_1MS; - } - else if (2 == hw) - { - *sw = FAL_RATE_MI_10MS; - } - else - { - *sw = FAL_RATE_MI_100MS; - } -} - -static sw_error_t -_isisc_rate_port_policer_set(a_uint32_t dev_id, fal_port_t port_id, - fal_port_policer_t * policer) -{ - sw_error_t rv; - a_uint32_t cir = 0x7fff, eir = 0x7fff, cbs = 0, ebs = 0, tmp, data[3] = { 0 }; - - HSL_DEV_ID_CHECK(dev_id); - - if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU)) - { - return SW_BAD_PARAM; - } - - data[0] = 0x18000000; - if (FAL_BYTE_BASED == policer->meter_unit) - { - if (A_TRUE == policer->c_enable) - { - cir = policer->cir >> 5; - policer->cir = cir << 5; - _isisc_ingress_bs_byte_sw_to_hw(policer->cbs, &cbs); - _isisc_ingress_bs_byte_hw_to_sw(cbs, &(policer->cbs)); - } - - if (A_TRUE == policer->e_enable) - { - eir = policer->eir >> 5; - policer->eir = eir << 5; - _isisc_ingress_bs_byte_sw_to_hw(policer->ebs, &ebs); - _isisc_ingress_bs_byte_hw_to_sw(ebs, &(policer->ebs)); - } - - SW_SET_REG_BY_FIELD(INGRESS_POLICER1, INGRESS_UNIT, 0, data[1]); - } - else if (FAL_FRAME_BASED == policer->meter_unit) - { - if (A_TRUE == policer->c_enable) - { - cir = (policer->cir * 2) / 125; - policer->cir = cir / 2 * 125 + cir % 2 * 63; - _isisc_ingress_bs_frame_sw_to_hw(policer->cbs, &cbs); - _isisc_ingress_bs_frame_hw_to_sw(cbs, &(policer->cbs)); - } - - if (A_TRUE == policer->e_enable) - { - eir = (policer->eir * 2) / 125; - policer->eir = eir / 2 * 125 + eir % 2 * 63; - _isisc_ingress_bs_frame_sw_to_hw(policer->ebs, &ebs); - _isisc_ingress_bs_frame_hw_to_sw(ebs, &(policer->ebs)); - } - - SW_SET_REG_BY_FIELD(INGRESS_POLICER1, INGRESS_UNIT, 1, data[1]); - } - else - { - return SW_BAD_PARAM; - } - - SW_SET_REG_BY_FIELD(INGRESS_POLICER0, INGRESS_CIR, cir, data[0]); - SW_SET_REG_BY_FIELD(INGRESS_POLICER0, INGRESS_CBS, cbs, data[0]); - SW_SET_REG_BY_FIELD(INGRESS_POLICER1, INGRESS_EIR, eir, data[1]); - SW_SET_REG_BY_FIELD(INGRESS_POLICER1, INGRESS_EBS, ebs, data[1]); - - if (A_TRUE == policer->combine_mode) - { - SW_SET_REG_BY_FIELD(INGRESS_POLICER0, RATE_MODE, 1, data[0]); - } - - if (A_TRUE == policer->deficit_en) - { - SW_SET_REG_BY_FIELD(INGRESS_POLICER1, INGRESS_BORROW, 1, data[1]); - } - - if (A_TRUE == policer->color_mode) - { - SW_SET_REG_BY_FIELD(INGRESS_POLICER1, INGRESS_CM, 1, data[1]); - } - - if (A_TRUE == policer->couple_flag) - { - SW_SET_REG_BY_FIELD(INGRESS_POLICER1, INGRESS_CF, 1, data[1]); - } - - _isisc_rate_ts_parse(policer->c_meter_interval, &tmp); - SW_SET_REG_BY_FIELD(INGRESS_POLICER0, C_ING_TS, tmp, data[0]); - - _isisc_rate_ts_parse(policer->e_meter_interval, &tmp); - SW_SET_REG_BY_FIELD(INGRESS_POLICER1, E_ING_TS, tmp, data[1]); - - _isisc_rate_flag_parse(policer->c_rate_flag, &tmp); - data[2] = (tmp << 8) & 0xff00; - - _isisc_rate_flag_parse(policer->e_rate_flag, &tmp); - data[2] |= (tmp & 0xff); - - HSL_REG_ENTRY_SET(rv, dev_id, INGRESS_POLICER0, port_id, - (a_uint8_t *) (&data[0]), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - - HSL_REG_ENTRY_SET(rv, dev_id, INGRESS_POLICER1, port_id, - (a_uint8_t *) (&data[1]), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - - HSL_REG_ENTRY_SET(rv, dev_id, INGRESS_POLICER2, port_id, - (a_uint8_t *) (&data[2]), sizeof (a_uint32_t)); - return rv; -} - -static sw_error_t -_isisc_rate_port_policer_get(a_uint32_t dev_id, fal_port_t port_id, - fal_port_policer_t * policer) -{ - sw_error_t rv; - a_uint32_t unit, ts, cir, eir, cbs, ebs, data[3] = {0}; - - HSL_DEV_ID_CHECK(dev_id); - - if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU)) - { - return SW_BAD_PARAM; - } - - HSL_REG_ENTRY_GET(rv, dev_id, INGRESS_POLICER0, port_id, - (a_uint8_t *) (&data[0]), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - - HSL_REG_ENTRY_GET(rv, dev_id, INGRESS_POLICER1, port_id, - (a_uint8_t *) (&data[1]), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - - HSL_REG_ENTRY_GET(rv, dev_id, INGRESS_POLICER2, port_id, - (a_uint8_t *) (&data[2]), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - - SW_GET_FIELD_BY_REG(INGRESS_POLICER0, INGRESS_CIR, cir, data[0]); - SW_GET_FIELD_BY_REG(INGRESS_POLICER0, INGRESS_CBS, cbs, data[0]); - SW_GET_FIELD_BY_REG(INGRESS_POLICER1, INGRESS_EIR, eir, data[1]); - SW_GET_FIELD_BY_REG(INGRESS_POLICER1, INGRESS_EBS, ebs, data[1]); - SW_GET_FIELD_BY_REG(INGRESS_POLICER1, INGRESS_UNIT, unit, data[1]); - - policer->c_enable = A_TRUE; - if (0x7fff == cir) - { - policer->c_enable = A_FALSE; - cir = 0; - } - - policer->e_enable = A_TRUE; - if (0x7fff == eir) - { - policer->e_enable = A_FALSE; - eir = 0; - } - - if (unit) - { - policer->meter_unit = FAL_FRAME_BASED; - policer->cir = cir / 2 * 125 + cir % 2 * 63; - policer->eir = eir / 2 * 125 + eir % 2 * 63; - _isisc_ingress_bs_frame_hw_to_sw(cbs, &(policer->cbs)); - _isisc_ingress_bs_frame_hw_to_sw(ebs, &(policer->ebs)); - } - else - { - policer->meter_unit = FAL_BYTE_BASED; - policer->cir = cir << 5; - policer->eir = eir << 5; - _isisc_ingress_bs_byte_hw_to_sw(cbs, &(policer->cbs)); - _isisc_ingress_bs_byte_hw_to_sw(ebs, &(policer->ebs)); - } - - SW_GET_FIELD_BY_REG(INGRESS_POLICER0, RATE_MODE, policer->combine_mode, - data[0]); - SW_GET_FIELD_BY_REG(INGRESS_POLICER1, INGRESS_BORROW, policer->deficit_en, - data[1]); - SW_GET_FIELD_BY_REG(INGRESS_POLICER1, INGRESS_CF, policer->couple_flag, - data[1]); - SW_GET_FIELD_BY_REG(INGRESS_POLICER1, INGRESS_CM, policer->color_mode, - data[1]); - - ts = (data[2] >> 8) & 0xff; - _isisc_rate_flag_reparse(ts, &(policer->c_rate_flag)); - - ts = data[2] & 0xff; - _isisc_rate_flag_reparse(ts, &(policer->e_rate_flag)); - - SW_GET_FIELD_BY_REG(INGRESS_POLICER0, C_ING_TS, ts, data[0]); - _isisc_rate_ts_reparse(ts, &(policer->c_meter_interval)); - - SW_GET_FIELD_BY_REG(INGRESS_POLICER1, E_ING_TS, ts, data[1]); - _isisc_rate_ts_reparse(ts, &(policer->e_meter_interval)); - - return SW_OK; -} - -static sw_error_t -_isisc_rate_port_shaper_set(a_uint32_t dev_id, fal_port_t port_id, - a_bool_t enable, fal_egress_shaper_t * shaper) -{ - sw_error_t rv; - a_uint32_t data, cir, eir, cbs = 0, ebs = 0; - - HSL_DEV_ID_CHECK(dev_id); - - if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU)) - { - return SW_BAD_PARAM; - } - - if (A_FALSE == enable) - { - aos_mem_zero(shaper, sizeof (fal_egress_shaper_t)); - - cir = 0x7fff; - eir = 0x7fff; - } - else - { - if (FAL_BYTE_BASED == shaper->meter_unit) - { - cir = shaper->cir >> 5; - shaper->cir = cir << 5; - - eir = shaper->eir >> 5; - shaper->eir = eir << 5; - - _isisc_egress_bs_byte_sw_to_hw(shaper->cbs, &cbs); - _isisc_egress_bs_byte_hw_to_sw(cbs, &(shaper->cbs)); - - _isisc_egress_bs_byte_sw_to_hw(shaper->ebs, &ebs); - _isisc_egress_bs_byte_hw_to_sw(ebs, &(shaper->ebs)); - - data = 0; - } - else if (FAL_FRAME_BASED == shaper->meter_unit) - { - cir = (shaper->cir * 2) / 125; - shaper->cir = cir / 2 * 125 + cir % 2 * 63; - - eir = (shaper->eir * 2) / 125; - shaper->eir = eir / 2 * 125 + eir % 2 * 63; - - _isisc_egress_bs_frame_sw_to_hw(shaper->cbs, &cbs); - _isisc_egress_bs_frame_hw_to_sw(cbs, &(shaper->cbs)); - - _isisc_egress_bs_frame_sw_to_hw(shaper->ebs, &ebs); - _isisc_egress_bs_frame_hw_to_sw(ebs, &(shaper->ebs)); - - data = 1; - } - else - { - return SW_BAD_PARAM; - } - - HSL_REG_FIELD_SET(rv, dev_id, EG_SHAPER7, port_id, EG_Q0_UNIT, - (a_uint8_t *) (&data), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - - data = 1; - HSL_REG_FIELD_SET(rv, dev_id, EG_SHAPER7, port_id, EG_PT, - (a_uint8_t *) (&data), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - } - - HSL_REG_FIELD_SET(rv, dev_id, EG_SHAPER0, port_id, EG_Q0_CIR, - (a_uint8_t *) (&cir), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - - HSL_REG_FIELD_SET(rv, dev_id, EG_SHAPER3, port_id, EG_Q0_EIR, - (a_uint8_t *) (&eir), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - - HSL_REG_FIELD_SET(rv, dev_id, EG_SHAPER6, port_id, EG_Q0_CBS, - (a_uint8_t *) (&cbs), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - - HSL_REG_FIELD_SET(rv, dev_id, EG_SHAPER6, port_id, EG_Q0_EBS, - (a_uint8_t *) (&ebs), sizeof (a_uint32_t)); - return rv; -} - -static sw_error_t -_isisc_rate_port_shaper_get(a_uint32_t dev_id, fal_port_t port_id, - a_bool_t * enable, fal_egress_shaper_t * shaper) -{ - sw_error_t rv; - a_uint32_t data = 0, cir = 0, eir = 0, cbs = 0, ebs = 0; - - HSL_DEV_ID_CHECK(dev_id); - - if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU)) - { - return SW_BAD_PARAM; - } - - aos_mem_zero(shaper, sizeof (fal_egress_shaper_t)); - - HSL_REG_FIELD_GET(rv, dev_id, EG_SHAPER7, port_id, EG_PT, - (a_uint8_t *) (&data), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - - if (!data) - { - *enable = A_FALSE; - return SW_OK; - } - - HSL_REG_FIELD_GET(rv, dev_id, EG_SHAPER0, port_id, EG_Q0_CIR, - (a_uint8_t *) (&cir), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - - HSL_REG_FIELD_GET(rv, dev_id, EG_SHAPER3, port_id, EG_Q0_EIR, - (a_uint8_t *) (&eir), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - - HSL_REG_FIELD_GET(rv, dev_id, EG_SHAPER6, port_id, EG_Q0_CBS, - (a_uint8_t *) (&cbs), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - - HSL_REG_FIELD_GET(rv, dev_id, EG_SHAPER6, port_id, EG_Q0_EBS, - (a_uint8_t *) (&ebs), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - - if ((0x7fff == cir) && (0x7fff == eir)) - { - *enable = A_FALSE; - return SW_OK; - } - - *enable = A_TRUE; - HSL_REG_FIELD_GET(rv, dev_id, EG_SHAPER7, port_id, EG_Q0_UNIT, - (a_uint8_t *) (&data), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - - if (data) - { - shaper->meter_unit = FAL_FRAME_BASED; - shaper->cir = cir / 2 * 125 + cir % 2 * 63; - shaper->eir = eir / 2 * 125 + eir % 2 * 63; - _isisc_egress_bs_frame_hw_to_sw(cbs, &(shaper->cbs)); - _isisc_egress_bs_frame_hw_to_sw(ebs, &(shaper->ebs)); - } - else - { - shaper->meter_unit = FAL_BYTE_BASED; - shaper->cir = cir << 5; - shaper->eir = eir << 5; - _isisc_egress_bs_byte_hw_to_sw(cbs, &(shaper->cbs)); - _isisc_egress_bs_byte_hw_to_sw(ebs, &(shaper->ebs)); - } - - return SW_OK; -} - -static sw_error_t -_isisc_rate_queue_shaper_set(a_uint32_t dev_id, fal_port_t port_id, - fal_queue_t queue_id, a_bool_t enable, - fal_egress_shaper_t * shaper) -{ - sw_error_t rv; - a_uint32_t unit = 0, data, cir, eir, cbs = 0, ebs = 0; - - HSL_DEV_ID_CHECK(dev_id); - - if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU)) - { - return SW_BAD_PARAM; - } - - rv = _isisc_rate_port_queue_check(port_id, queue_id); - SW_RTN_ON_ERROR(rv); - - if (A_FALSE == enable) - { - aos_mem_zero(shaper, sizeof (fal_egress_shaper_t)); - - cir = 0x7fff; - eir = 0x7fff; - } - else - { - if (FAL_BYTE_BASED == shaper->meter_unit) - { - cir = shaper->cir >> 5; - shaper->cir = cir << 5; - - eir = shaper->eir >> 5; - shaper->eir = eir << 5; - - _isisc_egress_bs_byte_sw_to_hw(shaper->cbs, &cbs); - _isisc_egress_bs_byte_hw_to_sw(cbs, &(shaper->cbs)); - - _isisc_egress_bs_byte_sw_to_hw(shaper->ebs, &ebs); - _isisc_egress_bs_byte_hw_to_sw(ebs, &(shaper->ebs)); - - unit = 0; - } - else if (FAL_FRAME_BASED == shaper->meter_unit) - { - cir = (shaper->cir * 2) / 125; - shaper->cir = cir / 2 * 125 + cir % 2 * 63; - - eir = (shaper->eir * 2) / 125; - shaper->eir = eir / 2 * 125 + eir % 2 * 63; - - _isisc_egress_bs_frame_sw_to_hw(shaper->cbs, &cbs); - _isisc_egress_bs_frame_hw_to_sw(cbs, &(shaper->cbs)); - - _isisc_egress_bs_frame_sw_to_hw(shaper->ebs, &ebs); - _isisc_egress_bs_frame_hw_to_sw(ebs, &(shaper->ebs)); - - unit = 1; - } - - data = 0; - HSL_REG_FIELD_SET(rv, dev_id, EG_SHAPER7, port_id, EG_PT, - (a_uint8_t *) (&data), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - } - - if (0 == queue_id) - { - HSL_REG_FIELD_SET(rv, dev_id, EG_SHAPER0, port_id, EG_Q0_CIR, - (a_uint8_t *) (&cir), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - - HSL_REG_FIELD_SET(rv, dev_id, EG_SHAPER3, port_id, EG_Q0_EIR, - (a_uint8_t *) (&eir), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - - HSL_REG_FIELD_SET(rv, dev_id, EG_SHAPER6, port_id, EG_Q0_CBS, - (a_uint8_t *) (&cbs), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - - HSL_REG_FIELD_SET(rv, dev_id, EG_SHAPER6, port_id, EG_Q0_EBS, - (a_uint8_t *) (&ebs), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - - HSL_REG_FIELD_SET(rv, dev_id, EG_SHAPER7, port_id, EG_Q0_UNIT, - (a_uint8_t *) (&unit), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - } - else if (1 == queue_id) - { - HSL_REG_FIELD_SET(rv, dev_id, EG_SHAPER0, port_id, EG_Q1_CIR, - (a_uint8_t *) (&cir), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - - HSL_REG_FIELD_SET(rv, dev_id, EG_SHAPER3, port_id, EG_Q1_EIR, - (a_uint8_t *) (&eir), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - - HSL_REG_FIELD_SET(rv, dev_id, EG_SHAPER6, port_id, EG_Q1_CBS, - (a_uint8_t *) (&cbs), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - - HSL_REG_FIELD_SET(rv, dev_id, EG_SHAPER6, port_id, EG_Q1_EBS, - (a_uint8_t *) (&ebs), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - - HSL_REG_FIELD_SET(rv, dev_id, EG_SHAPER7, port_id, EG_Q1_UNIT, - (a_uint8_t *) (&unit), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - } - else if (2 == queue_id) - { - HSL_REG_FIELD_SET(rv, dev_id, EG_SHAPER1, port_id, EG_Q2_CIR, - (a_uint8_t *) (&cir), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - - HSL_REG_FIELD_SET(rv, dev_id, EG_SHAPER4, port_id, EG_Q2_EIR, - (a_uint8_t *) (&eir), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - - HSL_REG_FIELD_SET(rv, dev_id, EG_SHAPER6, port_id, EG_Q2_CBS, - (a_uint8_t *) (&cbs), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - - HSL_REG_FIELD_SET(rv, dev_id, EG_SHAPER6, port_id, EG_Q2_EBS, - (a_uint8_t *) (&ebs), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - - HSL_REG_FIELD_SET(rv, dev_id, EG_SHAPER7, port_id, EG_Q2_UNIT, - (a_uint8_t *) (&unit), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - } - else if (3 == queue_id) - { - HSL_REG_FIELD_SET(rv, dev_id, EG_SHAPER1, port_id, EG_Q3_CIR, - (a_uint8_t *) (&cir), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - - HSL_REG_FIELD_SET(rv, dev_id, EG_SHAPER4, port_id, EG_Q3_EIR, - (a_uint8_t *) (&eir), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - - HSL_REG_FIELD_SET(rv, dev_id, EG_SHAPER6, port_id, EG_Q3_CBS, - (a_uint8_t *) (&cbs), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - - HSL_REG_FIELD_SET(rv, dev_id, EG_SHAPER6, port_id, EG_Q3_EBS, - (a_uint8_t *) (&ebs), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - - HSL_REG_FIELD_SET(rv, dev_id, EG_SHAPER7, port_id, EG_Q3_UNIT, - (a_uint8_t *) (&unit), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - } - else if (4 == queue_id) - { - HSL_REG_FIELD_SET(rv, dev_id, EG_SHAPER2, port_id, EG_Q4_CIR, - (a_uint8_t *) (&cir), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - - HSL_REG_FIELD_SET(rv, dev_id, EG_SHAPER5, port_id, EG_Q4_EIR, - (a_uint8_t *) (&eir), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - - HSL_REG_FIELD_SET(rv, dev_id, EG_SHAPER7, port_id, EG_Q4_CBS, - (a_uint8_t *) (&cbs), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - - HSL_REG_FIELD_SET(rv, dev_id, EG_SHAPER7, port_id, EG_Q4_EBS, - (a_uint8_t *) (&ebs), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - - HSL_REG_FIELD_SET(rv, dev_id, EG_SHAPER7, port_id, EG_Q4_UNIT, - (a_uint8_t *) (&unit), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - } - else - { - HSL_REG_FIELD_SET(rv, dev_id, EG_SHAPER2, port_id, EG_Q5_CIR, - (a_uint8_t *) (&cir), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - - HSL_REG_FIELD_SET(rv, dev_id, EG_SHAPER5, port_id, EG_Q5_EIR, - (a_uint8_t *) (&eir), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - - HSL_REG_FIELD_SET(rv, dev_id, EG_SHAPER7, port_id, EG_Q5_CBS, - (a_uint8_t *) (&cbs), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - - HSL_REG_FIELD_SET(rv, dev_id, EG_SHAPER7, port_id, EG_Q5_EBS, - (a_uint8_t *) (&ebs), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - - HSL_REG_FIELD_SET(rv, dev_id, EG_SHAPER7, port_id, EG_Q5_UNIT, - (a_uint8_t *) (&unit), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - } - - return SW_OK; -} - -static sw_error_t -_isisc_rate_queue_shaper_get(a_uint32_t dev_id, fal_port_t port_id, - fal_queue_t queue_id, a_bool_t * enable, - fal_egress_shaper_t * shaper) -{ - sw_error_t rv; - a_uint32_t data = 0, cir = 0, eir = 0, cbs = 0, ebs = 0; - - HSL_DEV_ID_CHECK(dev_id); - - if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU)) - { - return SW_BAD_PARAM; - } - - rv = _isisc_rate_port_queue_check(port_id, queue_id); - SW_RTN_ON_ERROR(rv); - - aos_mem_zero(shaper, sizeof (fal_egress_shaper_t)); - - HSL_REG_FIELD_GET(rv, dev_id, EG_SHAPER7, port_id, EG_PT, - (a_uint8_t *) (&data), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - - if (data) - { - *enable = A_FALSE; - return SW_OK; - } - - if (0 == queue_id) - { - HSL_REG_FIELD_GET(rv, dev_id, EG_SHAPER0, port_id, EG_Q0_CIR, - (a_uint8_t *) (&cir), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - - HSL_REG_FIELD_GET(rv, dev_id, EG_SHAPER3, port_id, EG_Q0_EIR, - (a_uint8_t *) (&eir), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - - HSL_REG_FIELD_GET(rv, dev_id, EG_SHAPER6, port_id, EG_Q0_CBS, - (a_uint8_t *) (&cbs), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - - HSL_REG_FIELD_GET(rv, dev_id, EG_SHAPER6, port_id, EG_Q0_EBS, - (a_uint8_t *) (&ebs), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - - HSL_REG_FIELD_GET(rv, dev_id, EG_SHAPER7, port_id, EG_Q0_UNIT, - (a_uint8_t *) (&data), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - } - else if (1 == queue_id) - { - HSL_REG_FIELD_GET(rv, dev_id, EG_SHAPER0, port_id, EG_Q1_CIR, - (a_uint8_t *) (&cir), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - - HSL_REG_FIELD_GET(rv, dev_id, EG_SHAPER3, port_id, EG_Q1_EIR, - (a_uint8_t *) (&eir), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - - HSL_REG_FIELD_GET(rv, dev_id, EG_SHAPER6, port_id, EG_Q1_CBS, - (a_uint8_t *) (&cbs), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - - HSL_REG_FIELD_GET(rv, dev_id, EG_SHAPER6, port_id, EG_Q1_EBS, - (a_uint8_t *) (&ebs), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - - HSL_REG_FIELD_GET(rv, dev_id, EG_SHAPER7, port_id, EG_Q1_UNIT, - (a_uint8_t *) (&data), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - } - else if (2 == queue_id) - { - HSL_REG_FIELD_GET(rv, dev_id, EG_SHAPER1, port_id, EG_Q2_CIR, - (a_uint8_t *) (&cir), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - - HSL_REG_FIELD_GET(rv, dev_id, EG_SHAPER4, port_id, EG_Q2_EIR, - (a_uint8_t *) (&eir), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - - HSL_REG_FIELD_GET(rv, dev_id, EG_SHAPER6, port_id, EG_Q2_CBS, - (a_uint8_t *) (&cbs), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - - HSL_REG_FIELD_GET(rv, dev_id, EG_SHAPER6, port_id, EG_Q2_EBS, - (a_uint8_t *) (&ebs), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - - HSL_REG_FIELD_GET(rv, dev_id, EG_SHAPER7, port_id, EG_Q2_UNIT, - (a_uint8_t *) (&data), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - } - else if (3 == queue_id) - { - HSL_REG_FIELD_GET(rv, dev_id, EG_SHAPER1, port_id, EG_Q3_CIR, - (a_uint8_t *) (&cir), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - - HSL_REG_FIELD_GET(rv, dev_id, EG_SHAPER4, port_id, EG_Q3_EIR, - (a_uint8_t *) (&eir), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - - HSL_REG_FIELD_GET(rv, dev_id, EG_SHAPER6, port_id, EG_Q3_CBS, - (a_uint8_t *) (&cbs), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - - HSL_REG_FIELD_GET(rv, dev_id, EG_SHAPER6, port_id, EG_Q3_EBS, - (a_uint8_t *) (&ebs), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - - HSL_REG_FIELD_GET(rv, dev_id, EG_SHAPER7, port_id, EG_Q3_UNIT, - (a_uint8_t *) (&data), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - } - else if (4 == queue_id) - { - HSL_REG_FIELD_GET(rv, dev_id, EG_SHAPER2, port_id, EG_Q4_CIR, - (a_uint8_t *) (&cir), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - - HSL_REG_FIELD_GET(rv, dev_id, EG_SHAPER5, port_id, EG_Q4_EIR, - (a_uint8_t *) (&eir), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - - HSL_REG_FIELD_GET(rv, dev_id, EG_SHAPER7, port_id, EG_Q4_CBS, - (a_uint8_t *) (&cbs), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - - HSL_REG_FIELD_GET(rv, dev_id, EG_SHAPER7, port_id, EG_Q4_EBS, - (a_uint8_t *) (&ebs), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - - HSL_REG_FIELD_GET(rv, dev_id, EG_SHAPER7, port_id, EG_Q4_UNIT, - (a_uint8_t *) (&data), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - } - else - { - HSL_REG_FIELD_GET(rv, dev_id, EG_SHAPER2, port_id, EG_Q5_CIR, - (a_uint8_t *) (&cir), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - - HSL_REG_FIELD_GET(rv, dev_id, EG_SHAPER5, port_id, EG_Q5_EIR, - (a_uint8_t *) (&eir), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - - HSL_REG_FIELD_GET(rv, dev_id, EG_SHAPER7, port_id, EG_Q5_CBS, - (a_uint8_t *) (&cbs), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - - HSL_REG_FIELD_GET(rv, dev_id, EG_SHAPER7, port_id, EG_Q5_EBS, - (a_uint8_t *) (&ebs), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - - HSL_REG_FIELD_GET(rv, dev_id, EG_SHAPER7, port_id, EG_Q5_UNIT, - (a_uint8_t *) (&data), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - } - - if ((0x7fff == cir) && (0x7fff == eir)) - { - *enable = A_FALSE; - return SW_OK; - } - - *enable = A_TRUE; - if (data) - { - shaper->meter_unit = FAL_FRAME_BASED; - shaper->cir = cir / 2 * 125 + cir % 2 * 63; - shaper->eir = eir / 2 * 125 + eir % 2 * 63; - _isisc_egress_bs_frame_hw_to_sw(cbs, &(shaper->cbs)); - _isisc_egress_bs_frame_hw_to_sw(ebs, &(shaper->ebs)); - } - else - { - shaper->meter_unit = FAL_BYTE_BASED; - shaper->cir = cir << 5; - shaper->eir = eir << 5; - _isisc_egress_bs_byte_hw_to_sw(cbs, &(shaper->cbs)); - _isisc_egress_bs_byte_hw_to_sw(ebs, &(shaper->ebs)); - } - - return SW_OK; -} - -static sw_error_t -_isisc_rate_acl_policer_set(a_uint32_t dev_id, a_uint32_t policer_id, - fal_acl_policer_t * policer) -{ - sw_error_t rv; - a_uint32_t ts, cir, eir, cbs = 0, ebs = 0, addr, data[2] = { 0 }; - - HSL_DEV_ID_CHECK(dev_id); - - if (ISISC_MAX_POLICER_ID < policer_id) - { - return SW_BAD_PARAM; - } - - if (A_TRUE == policer->counter_mode) - { - addr = ACL_POLICER_CNT_SEL_ADDR; - data[0] = 0x1; - HSL_REG_FIELD_GEN_SET(rv, dev_id, addr, 1, policer_id, - (a_uint8_t *) (&data[0]), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - - addr = ACL_POLICER_CNT_MODE_ADDR; - if (FAL_FRAME_BASED == policer->meter_unit) - { - data[0] = 0x0; - } - else - { - data[0] = 0x1; - } - HSL_REG_FIELD_GEN_SET(rv, dev_id, addr, 1, policer_id, - (a_uint8_t *) (&data[0]), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - - addr = ACL_POLICER_CNT_RST_ADDR; - data[0] = 0x1; - HSL_REG_FIELD_GEN_SET(rv, dev_id, addr, 1, policer_id, - (a_uint8_t *) (&data[0]), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - - data[0] = 0x0; - HSL_REG_FIELD_GEN_SET(rv, dev_id, addr, 1, policer_id, - (a_uint8_t *) (&data[0]), sizeof (a_uint32_t)); - return rv; - } - - addr = ACL_POLICER_CNT_SEL_ADDR; - data[0] = 0x0; - HSL_REG_FIELD_GEN_SET(rv, dev_id, addr, 1, policer_id, - (a_uint8_t *) (&data[0]), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - - if (FAL_BYTE_BASED == policer->meter_unit) - { - cir = policer->cir >> 5; - policer->cir = cir << 5; - - eir = policer->eir >> 5; - policer->eir = eir << 5; - - _isisc_ingress_bs_byte_sw_to_hw(policer->cbs, &cbs); - _isisc_ingress_bs_byte_hw_to_sw(cbs, &(policer->cbs)); - - _isisc_ingress_bs_byte_sw_to_hw(policer->ebs, &ebs); - _isisc_ingress_bs_byte_hw_to_sw(ebs, &(policer->ebs)); - - SW_SET_REG_BY_FIELD(ACL_POLICER1, ACL_UNIT, 0, data[1]); - } - else if (FAL_FRAME_BASED == policer->meter_unit) - { - cir = (policer->cir * 2) / 125; - policer->cir = cir / 2 * 125 + cir % 2 * 63; - - eir = (policer->eir * 2) / 125; - policer->eir = eir / 2 * 125 + eir % 2 * 63; - - _isisc_ingress_bs_frame_sw_to_hw(policer->cbs, &cbs); - _isisc_ingress_bs_frame_hw_to_sw(cbs, &(policer->cbs)); - - _isisc_ingress_bs_frame_sw_to_hw(policer->ebs, &ebs); - _isisc_ingress_bs_frame_hw_to_sw(ebs, &(policer->ebs)); - - SW_SET_REG_BY_FIELD(ACL_POLICER1, ACL_UNIT, 1, data[1]); - } - else - { - return SW_BAD_PARAM; - } - - SW_SET_REG_BY_FIELD(ACL_POLICER0, ACL_CIR, cir, data[0]); - SW_SET_REG_BY_FIELD(ACL_POLICER0, ACL_CBS, cbs, data[0]); - SW_SET_REG_BY_FIELD(ACL_POLICER1, ACL_EIR, eir, data[1]); - SW_SET_REG_BY_FIELD(ACL_POLICER1, ACL_EBS, ebs, data[1]); - - if (A_TRUE == policer->deficit_en) - { - SW_SET_REG_BY_FIELD(ACL_POLICER1, ACL_BORROW, 1, data[1]); - } - - if (A_TRUE == policer->color_mode) - { - SW_SET_REG_BY_FIELD(ACL_POLICER1, ACL_CM, 1, data[1]); - } - - if (A_TRUE == policer->couple_flag) - { - SW_SET_REG_BY_FIELD(ACL_POLICER1, ACL_CF, 1, data[1]); - } - - _isisc_rate_ts_parse(policer->meter_interval, &ts); - SW_SET_REG_BY_FIELD(ACL_POLICER1, ACL_TS, ts, data[1]); - - HSL_REG_ENTRY_SET(rv, dev_id, ACL_POLICER0, policer_id, - (a_uint8_t *) (&data[0]), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - - HSL_REG_ENTRY_SET(rv, dev_id, ACL_POLICER1, policer_id, - (a_uint8_t *) (&data[1]), sizeof (a_uint32_t)); - - return rv; -} - -static sw_error_t -_isisc_rate_acl_policer_get(a_uint32_t dev_id, a_uint32_t policer_id, - fal_acl_policer_t * policer) -{ - sw_error_t rv; - a_uint32_t unit, ts, cir, eir, cbs, ebs, addr, data[2] = {0}; - - HSL_DEV_ID_CHECK(dev_id); - - if (ISISC_MAX_POLICER_ID < policer_id) - { - return SW_BAD_PARAM; - } - - aos_mem_zero(policer, sizeof (policer)); - - addr = ACL_POLICER_CNT_SEL_ADDR; - HSL_REG_FIELD_GEN_GET(rv, dev_id, addr, 1, policer_id, - (a_uint8_t *) (&data[0]), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - - if (data[0]) - { - policer->counter_mode = A_TRUE; - - addr = ACL_POLICER_CNT_MODE_ADDR; - HSL_REG_FIELD_GEN_GET(rv, dev_id, addr, 1, policer_id, - (a_uint8_t *) (&data[0]), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - - if (data[0]) - { - policer->meter_unit = FAL_BYTE_BASED; - } - else - { - policer->meter_unit = FAL_FRAME_BASED; - } - - HSL_REG_ENTRY_GET(rv, dev_id, ACL_COUNTER0, policer_id, - (a_uint8_t *) (&data[0]), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - - HSL_REG_ENTRY_GET(rv, dev_id, ACL_COUNTER1, policer_id, - (a_uint8_t *) (&data[1]), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - - policer->counter_low = data[0]; - policer->counter_high = data[1]; - - return SW_OK; - } - - HSL_REG_ENTRY_GET(rv, dev_id, ACL_POLICER0, policer_id, - (a_uint8_t *) (&data[0]), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - - HSL_REG_ENTRY_GET(rv, dev_id, ACL_POLICER1, policer_id, - (a_uint8_t *) (&data[1]), sizeof (a_uint32_t)); - - SW_GET_FIELD_BY_REG(ACL_POLICER0, ACL_CIR, cir, data[0]); - SW_GET_FIELD_BY_REG(ACL_POLICER0, ACL_CBS, cbs, data[0]); - SW_GET_FIELD_BY_REG(ACL_POLICER1, ACL_EIR, eir, data[1]); - SW_GET_FIELD_BY_REG(ACL_POLICER1, ACL_EBS, ebs, data[1]); - SW_GET_FIELD_BY_REG(ACL_POLICER1, ACL_UNIT, unit, data[1]); - if (unit) - { - policer->meter_unit = FAL_FRAME_BASED; - policer->cir = cir / 2 * 125 + cir % 2 * 63; - policer->eir = eir / 2 * 125 + eir % 2 * 63; - _isisc_ingress_bs_frame_hw_to_sw(cbs, &(policer->cbs)); - _isisc_ingress_bs_frame_hw_to_sw(ebs, &(policer->ebs)); - - } - else - { - policer->meter_unit = FAL_BYTE_BASED; - policer->cir = cir << 5; - policer->eir = eir << 5; - _isisc_ingress_bs_byte_hw_to_sw(cbs, &(policer->cbs)); - _isisc_ingress_bs_byte_hw_to_sw(ebs, &(policer->ebs)); - } - - SW_GET_FIELD_BY_REG(ACL_POLICER1, ACL_BORROW, policer->deficit_en, - data[1]); - SW_GET_FIELD_BY_REG(ACL_POLICER1, ACL_CF, policer->couple_flag, data[1]); - SW_GET_FIELD_BY_REG(ACL_POLICER1, ACL_CM, policer->color_mode, data[1]); - - SW_GET_FIELD_BY_REG(ACL_POLICER1, ACL_TS, ts, data[1]); - _isisc_rate_ts_reparse(ts, &(policer->meter_interval)); - - return SW_OK; -} - -sw_error_t -_isisc_rate_port_add_rate_byte_set(a_uint32_t dev_id, fal_port_t port_id, - a_uint32_t number) -{ - a_uint32_t val = number; - sw_error_t rv; - - HSL_DEV_ID_CHECK(dev_id); - - if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU)) - { - return SW_BAD_PARAM; - } - - if (val>255) - return SW_BAD_PARAM; - - HSL_REG_FIELD_SET(rv, dev_id, INGRESS_POLICER0, port_id, ADD_RATE_BYTE, - (a_uint8_t *) (&val), sizeof (a_uint32_t)); - - return rv; -} - -sw_error_t -_isisc_rate_port_add_rate_byte_get(a_uint32_t dev_id, fal_port_t port_id, - a_uint32_t *number) -{ - a_uint32_t val = 0; - sw_error_t rv = SW_OK; - - HSL_DEV_ID_CHECK(dev_id); - - if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU)) - { - return SW_BAD_PARAM; - } - - - HSL_REG_FIELD_GET(rv, dev_id, INGRESS_POLICER0, port_id, ADD_RATE_BYTE, - (a_uint8_t *) (&val), sizeof (a_uint32_t)); - *number = val; - - return rv; -} - -sw_error_t -_isisc_rate_port_gol_flow_en_set(a_uint32_t dev_id, fal_port_t port_id, - a_bool_t enable) -{ - a_uint32_t val = 0; - sw_error_t rv; - - HSL_DEV_ID_CHECK(dev_id); - - if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU)) - { - return SW_BAD_PARAM; - } - - HSL_REG_ENTRY_GET(rv, dev_id, QM_CTRL_REG, 0, - (a_uint8_t *) (&val), sizeof (a_uint32_t)); - - SW_RTN_ON_ERROR(rv); - - - if (A_TRUE == enable) - { - val |= (0x1<<(16+port_id)); - } - else if (A_FALSE == enable) - { - val &= ~(0x1<<(16+port_id)); - } - else - { - return SW_BAD_PARAM; - } - - HSL_REG_ENTRY_SET(rv, dev_id, QM_CTRL_REG, 0, - (a_uint8_t *) (&val), sizeof (a_uint32_t)); - - return rv; -} - -sw_error_t -_isisc_rate_port_gol_flow_en_get(a_uint32_t dev_id, fal_port_t port_id, - a_bool_t* enable) -{ - a_uint32_t val = 0; - sw_error_t rv; - - HSL_DEV_ID_CHECK(dev_id); - - if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU)) - { - return SW_BAD_PARAM; - } - - HSL_REG_ENTRY_GET(rv, dev_id, QM_CTRL_REG, 0, - (a_uint8_t *) (&val), sizeof (a_uint32_t)); - - SW_RTN_ON_ERROR(rv); - - if (val&(0x1<<(16+port_id))) - { - *enable = A_TRUE; - } - else - { - *enable = A_FALSE; - } - - return rv; -} - - - -/** - * @brief Set port ingress policer parameters on one particular port. - * @details Comments: - The granularity of speed is 32kbps or 62.5fps. - Because of hardware granularity function will return actual speed in hardware. - When disable port ingress policer input parameter speed is meaningless. - * @param[in] dev_id device id - * @param[in] port_id port id - * @param[in] policer port ingress policer parameter - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -isisc_rate_port_policer_set(a_uint32_t dev_id, fal_port_t port_id, - fal_port_policer_t * policer) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _isisc_rate_port_policer_set(dev_id, port_id, policer); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Get port ingress policer parameters on one particular port. - * @details Comments: - The granularity of speed is 32kbps or 62.5fps. - Because of hardware granularity function will return actual speed in hardware. - When disable port ingress policer input parameter speed is meaningless. - * @param[in] dev_id device id - * @param[in] port_id port id - * @param[out] policer port ingress policer parameter - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -isisc_rate_port_policer_get(a_uint32_t dev_id, fal_port_t port_id, - fal_port_policer_t * policer) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _isisc_rate_port_policer_get(dev_id, port_id, policer); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Set port egress shaper parameters on one particular port. - * @details Comments: - The granularity of speed is 32kbps or 62.5fps. - Because of hardware granularity function will return actual speed in hardware. - When disable port egress shaper parameters is meaningless. - * @param[in] port_id port id - * @param[in] enable A_TRUE or A_FALSE - * @param[in] shaper port egress shaper parameter - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -isisc_rate_port_shaper_set(a_uint32_t dev_id, fal_port_t port_id, - a_bool_t enable, fal_egress_shaper_t * shaper) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _isisc_rate_port_shaper_set(dev_id, port_id, enable, shaper); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Get port egress shaper parameters on one particular port. - * @details Comments: - The granularity of speed is 32kbps or 62.5fps. - Because of hardware granularity function will return actual speed in hardware. - When disable port egress shaper parameters is meaningless. - * @param[in] dev_id device id - * @param[in] port_id port id - * @param[out] enable A_TRUE or A_FALSE - * @param[out] shaper port egress shaper parameter - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -isisc_rate_port_shaper_get(a_uint32_t dev_id, fal_port_t port_id, - a_bool_t * enable, fal_egress_shaper_t * shaper) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _isisc_rate_port_shaper_get(dev_id, port_id, enable, shaper); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Set queue egress shaper parameters on one particular port. - * @details Comments: - The granularity of speed is 32kbps or 62.5fps. - Because of hardware granularity function will return actual speed in hardware. - When disable queue egress shaper parameters is meaningless. - * @param[in] port_id port id - * @param[in] queue_id queue id - * @param[in] enable A_TRUE or A_FALSE - * @param[in] shaper port egress shaper parameter - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -isisc_rate_queue_shaper_set(a_uint32_t dev_id, fal_port_t port_id, - fal_queue_t queue_id, a_bool_t enable, - fal_egress_shaper_t * shaper) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _isisc_rate_queue_shaper_set(dev_id, port_id, queue_id, enable, shaper); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Get queue egress shaper parameters on one particular port. - * @details Comments: - The granularity of speed is 32kbps or 62.5fps. - Because of hardware granularity function will return actual speed in hardware. - When disable queue egress shaper parameters is meaningless. - * @param[in] port_id port id - * @param[in] queue_id queue id - * @param[out] enable A_TRUE or A_FALSE - * @param[out] shaper port egress shaper parameter - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -isisc_rate_queue_shaper_get(a_uint32_t dev_id, fal_port_t port_id, - fal_queue_t queue_id, a_bool_t * enable, - fal_egress_shaper_t * shaper) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _isisc_rate_queue_shaper_get(dev_id, port_id, queue_id, enable, shaper); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Set ACL ingress policer parameters. - * @details Comments: - The granularity of speed is 32kbps or 62.5fps. - Because of hardware granularity function will return actual speed in hardware. - * @param[in] dev_id device id - * @param[in] policer_id ACL policer id - * @param[in] policer ACL ingress policer parameters - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -isisc_rate_acl_policer_set(a_uint32_t dev_id, a_uint32_t policer_id, - fal_acl_policer_t * policer) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _isisc_rate_acl_policer_set(dev_id, policer_id, policer); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Get ACL ingress policer parameters. - * @details Comments: - The granularity of speed is 32kbps or 62.5fps. - Because of hardware granularity function will return actual speed in hardware. - * @param[in] dev_id device id - * @param[in] policer_id ACL policer id - * @param[in] policer ACL ingress policer parameters - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -isisc_rate_acl_policer_get(a_uint32_t dev_id, a_uint32_t policer_id, - fal_acl_policer_t * policer) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _isisc_rate_acl_policer_get(dev_id, policer_id, policer); - HSL_API_UNLOCK; - return rv; -} - -HSL_LOCAL sw_error_t -isisc_rate_port_add_rate_byte_set(a_uint32_t dev_id, fal_port_t port_id, - a_uint32_t number) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _isisc_rate_port_add_rate_byte_set(dev_id, port_id, number); - HSL_API_UNLOCK; - return rv; -} - -HSL_LOCAL sw_error_t -isisc_rate_port_add_rate_byte_get(a_uint32_t dev_id, fal_port_t port_id, - a_uint32_t *number) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _isisc_rate_port_add_rate_byte_get(dev_id, port_id, number); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Set status of port global flow control when global threshold is reached. - * @param[in] dev_id device id - * @param[in] port_id port id - * @param[in] enable A_TRUE or A_FALSE - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -isisc_rate_port_gol_flow_en_set(a_uint32_t dev_id, fal_port_t port_id, - a_bool_t enable) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _isisc_rate_port_gol_flow_en_set(dev_id, port_id, enable); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief get status of port global flow control when global threshold is reached. - * @param[in] dev_id device id - * @param[in] port_id port id - * @param[out] enable A_TRUE or A_FALSE - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -isisc_rate_port_gol_flow_en_get(a_uint32_t dev_id, fal_port_t port_id, - a_bool_t* enable) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _isisc_rate_port_gol_flow_en_get(dev_id, port_id, enable); - HSL_API_UNLOCK; - return rv; -} - - - -sw_error_t -isisc_rate_init(a_uint32_t dev_id) -{ - HSL_DEV_ID_CHECK(dev_id); - -#ifndef HSL_STANDALONG - { - hsl_api_t *p_api; - - SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id)); - - p_api->rate_port_policer_set = isisc_rate_port_policer_set; - p_api->rate_port_policer_get = isisc_rate_port_policer_get; - p_api->rate_port_shaper_set = isisc_rate_port_shaper_set; - p_api->rate_port_shaper_get = isisc_rate_port_shaper_get; - p_api->rate_queue_shaper_set = isisc_rate_queue_shaper_set; - p_api->rate_queue_shaper_get = isisc_rate_queue_shaper_get; - p_api->rate_acl_policer_set = isisc_rate_acl_policer_set; - p_api->rate_acl_policer_get = isisc_rate_acl_policer_get; - p_api->rate_port_gol_flow_en_set = isisc_rate_port_gol_flow_en_set; - p_api->rate_port_gol_flow_en_get = isisc_rate_port_gol_flow_en_get; - p_api->rate_port_add_rate_byte_set=isisc_rate_port_add_rate_byte_set; - p_api->rate_port_add_rate_byte_get=isisc_rate_port_add_rate_byte_get; - } -#endif - - return SW_OK; -} - -/** - * @} - */ - diff --git a/feeds/ipq807x/qca-ssdk/src/src/hsl/isisc/isisc_reg_access.c b/feeds/ipq807x/qca-ssdk/src/src/hsl/isisc/isisc_reg_access.c deleted file mode 100755 index 8b90afc51..000000000 --- a/feeds/ipq807x/qca-ssdk/src/src/hsl/isisc/isisc_reg_access.c +++ /dev/null @@ -1,459 +0,0 @@ -/* - * Copyright (c) 2012, 2016, The Linux Foundation. All rights reserved. - * Permission to use, copy, modify, and/or distribute this software for - * any purpose with or without fee is hereby granted, provided that the - * above copyright notice and this permission notice appear in all copies. - * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES - * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR - * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES - * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN - * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT - * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. - */ - - -#include "sw.h" -#include "hsl.h" -#include "hsl_dev.h" -#include "sd.h" -#include "isisc_reg_access.h" - -#if 0 -#include -#include -#include -#include -#include -#endif - -static hsl_access_mode reg_mode; - -#if defined(API_LOCK) -static aos_lock_t mdio_lock; -#define MDIO_LOCKER_INIT aos_lock_init(&mdio_lock) -#define MDIO_LOCKER_LOCK aos_lock(&mdio_lock) -#define MDIO_LOCKER_UNLOCK aos_unlock(&mdio_lock) -#else -#define MDIO_LOCKER_INIT -#define MDIO_LOCKER_LOCK -#define MDIO_LOCKER_UNLOCK -#endif - -#if defined(REG_ACCESS_SPEEDUP) -static a_uint32_t mdio_base_addr = 0xffffffff; -#endif - -static sw_error_t -_isisc_mdio_reg_get(a_uint32_t dev_id, a_uint32_t reg_addr, - a_uint8_t value[], a_uint32_t value_len) -{ - a_uint32_t reg_val; - - if (value_len != sizeof (a_uint32_t)) - return SW_BAD_LEN; - -#if 0 - /* change reg_addr to 16-bit word address, 32-bit aligned */ - reg_word_addr = (reg_addr & 0xfffffffc) >> 1; - - /* configure register high address */ - phy_addr = 0x18; - phy_reg = 0x0; - phy_val = (a_uint16_t) ((reg_word_addr >> 8) & 0x3ff); /* bit16-8 of reg address */ - -#if defined(REG_ACCESS_SPEEDUP) - if (phy_val != mdio_base_addr) - { - rv = sd_reg_mdio_set(dev_id, phy_addr, phy_reg, phy_val); - SW_RTN_ON_ERROR(rv); - - mdio_base_addr = phy_val; - } -#else - rv = sd_reg_mdio_set(dev_id, phy_addr, phy_reg, phy_val); - SW_RTN_ON_ERROR(rv); -#endif - - /* For some registers such as MIBs, since it is read/clear, we should */ - /* read the lower 16-bit register then the higher one */ - - /* read register in lower address */ - phy_addr = 0x10 | ((reg_word_addr >> 5) & 0x7); /* bit7-5 of reg address */ - phy_reg = (a_uint8_t) (reg_word_addr & 0x1f); /* bit4-0 of reg address */ - rv = sd_reg_mdio_get(dev_id, phy_addr, phy_reg, &tmp_val); - SW_RTN_ON_ERROR(rv); - reg_val = tmp_val; - - /* read register in higher address */ - reg_word_addr++; - phy_addr = 0x10 | ((reg_word_addr >> 5) & 0x7); /* bit7-5 of reg address */ - phy_reg = (a_uint8_t) (reg_word_addr & 0x1f); /* bit4-0 of reg address */ - rv = sd_reg_mdio_get(dev_id, phy_addr, phy_reg, &tmp_val); - SW_RTN_ON_ERROR(rv); - reg_val |= (((a_uint32_t)tmp_val) << 16); -#else - reg_val = sd_reg_mii_get(dev_id, reg_addr); -#endif - aos_mem_copy(value, ®_val, sizeof (a_uint32_t)); - - return SW_OK; -} - -static sw_error_t -_isisc_mdio_reg_set(a_uint32_t dev_id, a_uint32_t reg_addr, a_uint8_t value[], - a_uint32_t value_len) -{ - a_uint32_t reg_val = 0; - - if (value_len != sizeof (a_uint32_t)) - return SW_BAD_LEN; - - aos_mem_copy(®_val, value, sizeof (a_uint32_t)); - -#if 0 - /* change reg_addr to 16-bit word address, 32-bit aligned */ - reg_word_addr = (reg_addr & 0xfffffffc) >> 1; - - /* configure register high address */ - phy_addr = 0x18; - phy_reg = 0x0; - phy_val = (a_uint16_t) ((reg_word_addr >> 8) & 0x3ff); /* bit16-8 of reg address */ - -#if defined(REG_ACCESS_SPEEDUP) - if (phy_val != mdio_base_addr) - { - rv = sd_reg_mdio_set(dev_id, phy_addr, phy_reg, phy_val); - SW_RTN_ON_ERROR(rv); - - mdio_base_addr = phy_val; - } -#else - rv = sd_reg_mdio_set(dev_id, phy_addr, phy_reg, phy_val); - SW_RTN_ON_ERROR(rv); -#endif - - /* For some registers such as ARL and VLAN, since they include BUSY bit */ - /* in higher address, we should write the lower 16-bit register then the */ - /* higher one */ - - /* write register in lower address */ - phy_addr = 0x10 | ((reg_word_addr >> 5) & 0x7); /* bit7-5 of reg address */ - phy_reg = (a_uint8_t) (reg_word_addr & 0x1f); /* bit4-0 of reg address */ - phy_val = (a_uint16_t) (reg_val & 0xffff); - rv = sd_reg_mdio_set(dev_id, phy_addr, phy_reg, phy_val); - SW_RTN_ON_ERROR(rv); - - /* write register in higher address */ - reg_word_addr++; - phy_addr = 0x10 | ((reg_word_addr >> 5) & 0x7); /* bit7-5 of reg address */ - phy_reg = (a_uint8_t) (reg_word_addr & 0x1f); /* bit4-0 of reg address */ - phy_val = (a_uint16_t) ((reg_val >> 16) & 0xffff); - rv = sd_reg_mdio_set(dev_id, phy_addr, phy_reg, phy_val); - SW_RTN_ON_ERROR(rv); -#else - sd_reg_mii_set(dev_id, reg_addr, reg_val); -#endif - return SW_OK; -} - -sw_error_t -isisc_phy_get(a_uint32_t dev_id, a_uint32_t phy_addr, - a_uint32_t reg, a_uint16_t * value) -{ - sw_error_t rv; - - MDIO_LOCKER_LOCK; - rv = sd_reg_mdio_get(dev_id, phy_addr, reg, value); - MDIO_LOCKER_UNLOCK; - return rv; -} - -sw_error_t -isisc_phy_set(a_uint32_t dev_id, a_uint32_t phy_addr, - a_uint32_t reg, a_uint16_t value) -{ - sw_error_t rv; - - MDIO_LOCKER_LOCK; - rv = sd_reg_mdio_set(dev_id, phy_addr, reg, value); - MDIO_LOCKER_UNLOCK; - return rv; -} - -sw_error_t -isisc_reg_get(a_uint32_t dev_id, a_uint32_t reg_addr, a_uint8_t value[], - a_uint32_t value_len) -{ - sw_error_t rv; - - MDIO_LOCKER_LOCK; - if (HSL_MDIO == reg_mode) - { - rv = _isisc_mdio_reg_get(dev_id, reg_addr, value, value_len); - } - else - { - rv = sd_reg_hdr_get(dev_id, reg_addr, value, value_len); - } - MDIO_LOCKER_UNLOCK; - - return rv; -} - -sw_error_t -isisc_reg_set(a_uint32_t dev_id, a_uint32_t reg_addr, a_uint8_t value[], - a_uint32_t value_len) -{ - sw_error_t rv; -#if 0 - unsigned long flags; - - struct file *filp; - // mm_segment_t fs; - a_uint32_t rt_value = 0; - a_uint32_t write_flag = 0; - char s[20]= {0}; - a_uint32_t tmp_val = *((a_uint32_t *) value); - - /*get MODULE_EN reg rsv */ - SW_RTN_ON_ERROR(isisc_reg_get(dev_id, 0x30,(void *)&rt_value,4)); - write_flag = (rt_value>>15) & 0x1; -#endif - MDIO_LOCKER_LOCK; - if (HSL_MDIO == reg_mode) - { - rv = _isisc_mdio_reg_set(dev_id, reg_addr, value, value_len); - } - else - { - rv = sd_reg_hdr_set(dev_id, reg_addr, value, value_len); - } - MDIO_LOCKER_UNLOCK; - -#if 0 - if(write_flag) - { - filp = filp_open("/tmp/asic_output", O_RDWR|O_APPEND, 0644); - if(IS_ERR(filp)) - { - printk("open error...\n"); - return; - } - - fs=get_fs(); - - set_fs(KERNEL_DS); - sprintf(s,"%08x %08x\n",reg_addr,tmp_val); - filp->f_op->write(filp, s, strlen(s),&filp->f_pos); - - set_fs(fs); - - filp_close(filp,NULL); - } -#endif - - return rv; -} - -sw_error_t -isisc_reg_field_get(a_uint32_t dev_id, a_uint32_t reg_addr, - a_uint32_t bit_offset, a_uint32_t field_len, - a_uint8_t value[], a_uint32_t value_len) -{ - a_uint32_t reg_val = 0; - - if ((bit_offset >= 32 || (field_len > 32)) || (field_len == 0)) - return SW_OUT_OF_RANGE; - - if (value_len != sizeof (a_uint32_t)) - return SW_BAD_LEN; - - SW_RTN_ON_ERROR(isisc_reg_get(dev_id, reg_addr, (a_uint8_t *) & reg_val, sizeof (a_uint32_t))); - - - if(32 == field_len) - { - *((a_uint32_t *) value) = reg_val; - } - else - { - *((a_uint32_t *) value) = SW_REG_2_FIELD(reg_val, bit_offset, field_len); - } - return SW_OK; -} - -sw_error_t -isisc_reg_field_set(a_uint32_t dev_id, a_uint32_t reg_addr, - a_uint32_t bit_offset, a_uint32_t field_len, - const a_uint8_t value[], a_uint32_t value_len) -{ - a_uint32_t reg_val = 0; - a_uint32_t field_val = *((a_uint32_t *) value); - - if ((bit_offset >= 32 || (field_len > 32)) || (field_len == 0)) - return SW_OUT_OF_RANGE; - - if (value_len != sizeof (a_uint32_t)) - return SW_BAD_LEN; - - SW_RTN_ON_ERROR(isisc_reg_get(dev_id, reg_addr, (a_uint8_t *) & reg_val, sizeof (a_uint32_t))); - - if(32 == field_len) - { - reg_val = field_val; - } - else - { - SW_REG_SET_BY_FIELD_U32(reg_val, field_val, bit_offset, field_len); - } - - - SW_RTN_ON_ERROR(isisc_reg_set(dev_id, reg_addr, (a_uint8_t *) & reg_val, sizeof (a_uint32_t))); - - return SW_OK; -} - - -static sw_error_t -_isisc_regsiter_dump(a_uint32_t dev_id,a_uint32_t register_idx, fal_reg_dump_t * reg_dump) -{ - sw_error_t rv = SW_OK; - typedef struct { - a_uint32_t reg_base; - a_uint32_t reg_end; - char name[30]; - } regdump; - - regdump reg_dumps[8] = - { - {0x0, 0xE4, "0.Global control registers"}, - {0x100, 0x168, "1.EEE control registers"}, - {0x200, 0x270, "2.Parser control registers"}, - {0x400, 0x474, "3.ACL control registers"}, - {0x600, 0x718, "4.Lookup control registers"}, - {0x800, 0xb70, "5.QM control registers"}, - {0xc00, 0xc80, "6.PKT edit control registers"}, - {0x820, 0x820, "7.QM debug registers"} - }; - - a_uint32_t dump_addr, reg_count, reg_val = 0; - switch (register_idx) - { - case 0: - case 1: - case 2: - case 3: - case 4: - case 5: - case 6: - reg_count = 0; - for (dump_addr = reg_dumps[register_idx].reg_base; dump_addr <= reg_dumps[register_idx].reg_end; reg_count++) - { - rv = isisc_reg_get(dev_id, dump_addr, (a_uint8_t *) & reg_val, sizeof (a_uint32_t)); - reg_dump->reg_value[reg_count] = reg_val; - dump_addr += 4; - } - reg_dump->reg_count = reg_count; - reg_dump->reg_base = reg_dumps[register_idx].reg_base; - reg_dump->reg_end = reg_dumps[register_idx].reg_end; - snprintf((char *)reg_dump->reg_name,sizeof(reg_dump->reg_name),"%s",reg_dumps[register_idx].name); - break; - default: - return SW_BAD_PARAM; - } - - return rv; -} - -static sw_error_t -_isisc_debug_regsiter_dump(a_uint32_t dev_id,fal_debug_reg_dump_t * dbg_reg_dump) -{ - sw_error_t rv = SW_OK; - a_uint32_t reg; - a_uint32_t reg_count, reg_val = 0; - - reg_count = 0; - - for(reg=0;reg<=0x1F;reg++) - { - isisc_reg_set(dev_id, 0x820, (a_uint8_t *) & reg, sizeof (a_uint32_t)); - rv = isisc_reg_get(dev_id, 0x824, (a_uint8_t *) & reg_val, sizeof (a_uint32_t)); - dbg_reg_dump->reg_value[reg_count] = reg_val; - dbg_reg_dump->reg_addr[reg_count] = reg; - reg_count++; - } - dbg_reg_dump->reg_count = reg_count; - - snprintf((char *)dbg_reg_dump->reg_name,sizeof(dbg_reg_dump->reg_name),"QM debug registers"); - - return rv; -} - - -/** - * @brief dump registers. - * @param[in] dev_id device id - * @param[in] register_idx register group id - * @param[out] reg_dump register dump result - * @return SW_OK or error code - */ -sw_error_t -isisc_regsiter_dump(a_uint32_t dev_id,a_uint32_t register_idx, fal_reg_dump_t * reg_dump) -{ - sw_error_t rv = SW_OK; - - FAL_API_LOCK; - rv = _isisc_regsiter_dump(dev_id,register_idx,reg_dump); - FAL_API_UNLOCK; - return rv; -} - -/** - * @brief dump registers. - * @param[in] dev_id device id - * @param[out] reg_dump debug register dump - * @return SW_OK or error code - */ -sw_error_t -isisc_debug_regsiter_dump(a_uint32_t dev_id, fal_debug_reg_dump_t * dbg_reg_dump) -{ - sw_error_t rv = SW_OK; - - FAL_API_LOCK; - rv = _isisc_debug_regsiter_dump(dev_id,dbg_reg_dump); - FAL_API_UNLOCK; - return rv; -} - - - -sw_error_t -isisc_reg_access_init(a_uint32_t dev_id, hsl_access_mode mode) -{ - hsl_api_t *p_api; - - MDIO_LOCKER_INIT; - reg_mode = mode; - - SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id)); - p_api->phy_get = isisc_phy_get; - p_api->phy_set = isisc_phy_set; - p_api->reg_get = isisc_reg_get; - p_api->reg_set = isisc_reg_set; - p_api->reg_field_get = isisc_reg_field_get; - p_api->reg_field_set = isisc_reg_field_set; - p_api->register_dump = isisc_regsiter_dump; - p_api->debug_register_dump = isisc_debug_regsiter_dump; - - return SW_OK; -} - -sw_error_t -isisc_access_mode_set(a_uint32_t dev_id, hsl_access_mode mode) -{ - reg_mode = mode; - return SW_OK; - -} - diff --git a/feeds/ipq807x/qca-ssdk/src/src/hsl/isisc/isisc_sec.c b/feeds/ipq807x/qca-ssdk/src/src/hsl/isisc/isisc_sec.c deleted file mode 100755 index 579868f77..000000000 --- a/feeds/ipq807x/qca-ssdk/src/src/hsl/isisc/isisc_sec.c +++ /dev/null @@ -1,787 +0,0 @@ -/* - * Copyright (c) 2012, 2016, The Linux Foundation. All rights reserved. - * Permission to use, copy, modify, and/or distribute this software for - * any purpose with or without fee is hereby granted, provided that the - * above copyright notice and this permission notice appear in all copies. - * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES - * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR - * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES - * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN - * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT - * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. - */ - - -/** - * @defgroup isisc_sec ISISC_SEC - * @{ - */ -#include "sw.h" -#include "hsl.h" -#include "hsl_dev.h" -#include "hsl_port_prop.h" -#include "isisc_sec.h" -#include "isisc_reg.h" - -#define NORM_CTRL0_ADDR 0x0200 -#define NORM_CTRL1_ADDR 0x0204 -#define NORM_CTRL2_ADDR 0x0208 -#define NORM_CTRL3_ADDR 0x0c00 - -static sw_error_t -_isisc_sec_norm_item_set(a_uint32_t dev_id, fal_norm_item_t item, void *value) -{ - sw_error_t rv; - fal_fwd_cmd_t cmd; - a_bool_t enable; - a_uint32_t addr, offset, len, reg = 0, val; - - HSL_DEV_ID_CHECK(dev_id); - - cmd = *((fal_fwd_cmd_t *) value); - enable = *((a_bool_t *) value); - val = *((a_uint32_t *) value); - - len = 1; - switch (item) - { - case FAL_NORM_MAC_RESV_VID_CMD: - addr = NORM_CTRL0_ADDR; - offset = 0; - goto cmd_chk; - - case FAL_NORM_MAC_INVALID_SRC_ADDR_CMD: - addr = NORM_CTRL1_ADDR; - offset = 20; - goto cmd_chk; - - case FAL_NORM_IP_INVALID_VER_CMD: - addr = NORM_CTRL0_ADDR; - offset = 1; - goto cmd_chk; - - case FAL_NROM_IP_SAME_ADDR_CMD: - addr = NORM_CTRL0_ADDR; - offset = 2; - goto cmd_chk; - break; - - case FAL_NROM_IP_TTL_CHANGE_STATUS: - addr = NORM_CTRL3_ADDR; - offset = 11; - goto sts_chk; - - case FAL_NROM_IP_TTL_VALUE: - addr = NORM_CTRL3_ADDR; - offset = 12; - len = 8; - goto set_reg; - - case FAL_NROM_IP4_INVALID_HL_CMD: - addr = NORM_CTRL0_ADDR; - offset = 3; - goto cmd_chk; - - case FAL_NROM_IP4_HDR_OPTIONS_CMD: - addr = NORM_CTRL0_ADDR; - offset = 4; - len = 2; - goto s_cmd_chk; - - case FAL_NROM_IP4_INVALID_DF_CMD: - addr = NORM_CTRL0_ADDR; - offset = 7; - goto cmd_chk; - - case FAL_NROM_IP4_FRAG_OFFSET_MIN_LEN_CMD: - addr = NORM_CTRL0_ADDR; - offset = 8; - goto cmd_chk; - - case FAL_NROM_IP4_FRAG_OFFSET_MIN_SIZE: - addr = NORM_CTRL1_ADDR; - offset = 24; - len = 8; - goto set_reg; - - case FAL_NROM_IP4_FRAG_OFFSET_MAX_LEN_CMD: - addr = NORM_CTRL0_ADDR; - offset = 9; - goto cmd_chk; - - case FAL_NROM_IP4_INVALID_FRAG_OFFSET_CMD: - addr = NORM_CTRL0_ADDR; - offset = 10; - goto cmd_chk; - - case FAL_NROM_IP4_INVALID_SIP_CMD: - addr = NORM_CTRL0_ADDR; - offset = 11; - len = 1; - goto cmd_chk; - - case FAL_NROM_IP4_INVALID_DIP_CMD: - addr = NORM_CTRL0_ADDR; - offset = 12; - goto cmd_chk; - - case FAL_NROM_IP4_INVALID_CHKSUM_CMD: - addr = NORM_CTRL0_ADDR; - offset = 13; - goto cmd_chk; - - case FAL_NROM_IP4_INVALID_PL_CMD: - addr = NORM_CTRL1_ADDR; - offset = 19; - goto cmd_chk; - - case FAL_NROM_IP4_DF_CLEAR_STATUS: - addr = NORM_CTRL3_ADDR; - offset = 9; - goto sts_chk; - - case FAL_NROM_IP4_IPID_RANDOM_STATUS: - addr = NORM_CTRL3_ADDR; - offset = 10; - goto sts_chk; - - case FAL_NROM_IP6_INVALID_DIP_CMD: - addr = NORM_CTRL1_ADDR; - offset = 16; - goto cmd_chk; - - case FAL_NROM_IP6_INVALID_SIP_CMD: - addr = NORM_CTRL1_ADDR; - offset = 17; - goto cmd_chk; - - case FAL_NROM_IP6_INVALID_PL_CMD: - addr = NORM_CTRL1_ADDR; - offset = 18; - goto cmd_chk; - - case FAL_NROM_TCP_BLAT_CMD: - addr = NORM_CTRL0_ADDR; - offset = 14; - goto cmd_chk; - - case FAL_NROM_TCP_INVALID_HL_CMD: - addr = NORM_CTRL0_ADDR; - offset = 15; - goto cmd_chk; - - case FAL_NROM_TCP_MIN_HDR_SIZE: - addr = NORM_CTRL1_ADDR; - offset = 12; - len = 4; - goto set_reg; - - case FAL_NROM_TCP_INVALID_SYN_CMD: - addr = NORM_CTRL0_ADDR; - offset = 16; - goto cmd_chk; - break; - - case FAL_NROM_TCP_SU_BLOCK_CMD: - addr = NORM_CTRL0_ADDR; - offset = 17; - goto cmd_chk; - - case FAL_NROM_TCP_SP_BLOCK_CMD: - addr = NORM_CTRL0_ADDR; - offset = 18; - goto cmd_chk; - - case FAL_NROM_TCP_SAP_BLOCK_CMD: - addr = NORM_CTRL0_ADDR; - offset = 19; - goto cmd_chk; - - case FAL_NROM_TCP_XMAS_SCAN_CMD: - addr = NORM_CTRL0_ADDR; - offset = 20; - goto cmd_chk; - - case FAL_NROM_TCP_NULL_SCAN_CMD: - addr = NORM_CTRL0_ADDR; - offset = 21; - goto cmd_chk; - - case FAL_NROM_TCP_SR_BLOCK_CMD: - addr = NORM_CTRL0_ADDR; - offset = 22; - goto cmd_chk; - - case FAL_NROM_TCP_SF_BLOCK_CMD: - addr = NORM_CTRL0_ADDR; - offset = 23; - goto cmd_chk; - - case FAL_NROM_TCP_SAR_BLOCK_CMD: - addr = NORM_CTRL0_ADDR; - offset = 24; - goto cmd_chk; - - case FAL_NROM_TCP_RST_SCAN_CMD: - addr = NORM_CTRL0_ADDR; - offset = 25; - goto cmd_chk; - - case FAL_NROM_TCP_SYN_WITH_DATA_CMD: - addr = NORM_CTRL0_ADDR; - offset = 26; - goto cmd_chk; - - case FAL_NROM_TCP_RST_WITH_DATA_CMD: - addr = NORM_CTRL0_ADDR; - offset = 27; - goto cmd_chk; - - case FAL_NROM_TCP_FA_BLOCK_CMD: - addr = NORM_CTRL0_ADDR; - offset = 28; - goto cmd_chk; - - case FAL_NROM_TCP_PA_BLOCK_CMD: - addr = NORM_CTRL0_ADDR; - offset = 29; - goto cmd_chk; - - case FAL_NROM_TCP_UA_BLOCK_CMD: - addr = NORM_CTRL1_ADDR; - offset = 0; - goto cmd_chk; - - case FAL_NROM_TCP_INVALID_CHKSUM_CMD: - addr = NORM_CTRL1_ADDR; - offset = 1; - goto cmd_chk; - - case FAL_NROM_TCP_INVALID_URGPTR_CMD: - addr = NORM_CTRL1_ADDR; - offset = 2; - goto cmd_chk; - - case FAL_NROM_TCP_INVALID_OPTIONS_CMD: - addr = NORM_CTRL1_ADDR; - offset = 3; - goto cmd_chk; - - case FAL_NROM_UDP_BLAT_CMD: - addr = NORM_CTRL1_ADDR; - offset = 4; - goto cmd_chk; - - case FAL_NROM_UDP_INVALID_LEN_CMD: - addr = NORM_CTRL1_ADDR; - offset = 5; - goto cmd_chk; - - case FAL_NROM_UDP_INVALID_CHKSUM_CMD: - addr = NORM_CTRL1_ADDR; - offset = 6; - goto cmd_chk; - - case FAL_NROM_ICMP4_PING_PL_EXCEED_CMD: - addr = NORM_CTRL1_ADDR; - offset = 7; - goto cmd_chk; - - case FAL_NROM_ICMP6_PING_PL_EXCEED_CMD: - addr = NORM_CTRL1_ADDR; - offset = 8; - goto cmd_chk; - - case FAL_NROM_ICMP4_PING_FRAG_CMD: - addr = NORM_CTRL1_ADDR; - offset = 9; - goto cmd_chk; - - case FAL_NROM_ICMP6_PING_FRAG_CMD: - addr = NORM_CTRL1_ADDR; - offset = 10; - goto cmd_chk; - - case FAL_NROM_ICMP4_PING_MAX_PL_VALUE: - addr = NORM_CTRL2_ADDR; - offset = 0; - len = 14; - goto set_reg; - - case FAL_NROM_ICMP6_PING_MAX_PL_VALUE: - addr = NORM_CTRL2_ADDR; - offset = 16; - len = 14; - goto set_reg; - - default: - return SW_BAD_PARAM; - } - -sts_chk: - if (A_TRUE == enable) - { - val = 1; - } - else if (A_FALSE == enable) - { - val = 0; - } - else - { - return SW_BAD_PARAM; - } - goto set_reg; - -s_cmd_chk: - if (FAL_MAC_FRWRD == cmd) - { - val = 0; - } - else if (FAL_MAC_DROP == cmd) - { - val = 3; - } - else if (FAL_MAC_RDT_TO_CPU == cmd) - { - val = 2; - } - else - { - return SW_BAD_PARAM; - } - goto set_reg; - -cmd_chk: - if (FAL_MAC_FRWRD == cmd) - { - val = 0; - } - else if (FAL_MAC_DROP == cmd) - { - val = 1; - } - else - { - return SW_BAD_PARAM; - } - -set_reg: - HSL_REG_ENTRY_GEN_GET(rv, dev_id, addr, sizeof (a_uint32_t), - (a_uint8_t *) (®), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - - SW_REG_SET_BY_FIELD_U32(reg, val, offset, len); - - HSL_REG_ENTRY_GEN_SET(rv, dev_id, addr, sizeof (a_uint32_t), - (a_uint8_t *) (®), sizeof (a_uint32_t)); - return rv; -} - -static sw_error_t -_isisc_sec_norm_item_get(a_uint32_t dev_id, fal_norm_item_t item, void *value) -{ - sw_error_t rv; - a_uint32_t addr, offset, len, reg = 0, val; - a_uint32_t status_chk = 0, val_chk = 0, scmd_chk = 0; - - HSL_DEV_ID_CHECK(dev_id); - - len = 1; - switch (item) - { - case FAL_NORM_MAC_RESV_VID_CMD: - addr = NORM_CTRL0_ADDR; - offset = 0; - break; - - case FAL_NORM_MAC_INVALID_SRC_ADDR_CMD: - addr = NORM_CTRL1_ADDR; - offset = 20; - break; - - case FAL_NORM_IP_INVALID_VER_CMD: - addr = NORM_CTRL0_ADDR; - offset = 1; - break; - - case FAL_NROM_IP_SAME_ADDR_CMD: - addr = NORM_CTRL0_ADDR; - offset = 2; - break; - - case FAL_NROM_IP_TTL_CHANGE_STATUS: - addr = NORM_CTRL3_ADDR; - offset = 11; - status_chk = 1; - break; - - case FAL_NROM_IP_TTL_VALUE: - addr = NORM_CTRL3_ADDR; - offset = 12; - len = 8; - val_chk = 1; - break; - - case FAL_NROM_IP4_INVALID_HL_CMD: - addr = NORM_CTRL0_ADDR; - offset = 3; - break; - - case FAL_NROM_IP4_HDR_OPTIONS_CMD: - addr = NORM_CTRL0_ADDR; - offset = 4; - len = 2; - scmd_chk = 1; - break; - - case FAL_NROM_IP4_INVALID_DF_CMD: - addr = NORM_CTRL0_ADDR; - offset = 7; - break; - - case FAL_NROM_IP4_FRAG_OFFSET_MIN_LEN_CMD: - addr = NORM_CTRL0_ADDR; - offset = 8; - break; - - case FAL_NROM_IP4_FRAG_OFFSET_MIN_SIZE: - addr = NORM_CTRL1_ADDR; - offset = 24; - len = 8; - val_chk = 1; - break; - - case FAL_NROM_IP4_FRAG_OFFSET_MAX_LEN_CMD: - addr = NORM_CTRL0_ADDR; - offset = 9; - break; - - case FAL_NROM_IP4_INVALID_FRAG_OFFSET_CMD: - addr = NORM_CTRL0_ADDR; - offset = 10; - break; - - case FAL_NROM_IP4_INVALID_SIP_CMD: - addr = NORM_CTRL0_ADDR; - offset = 11; - len = 1; - break; - - case FAL_NROM_IP4_INVALID_DIP_CMD: - addr = NORM_CTRL0_ADDR; - offset = 12; - break; - - case FAL_NROM_IP4_INVALID_CHKSUM_CMD: - addr = NORM_CTRL0_ADDR; - offset = 13; - break; - - case FAL_NROM_IP4_INVALID_PL_CMD: - addr = NORM_CTRL1_ADDR; - offset = 19; - break; - - case FAL_NROM_IP4_DF_CLEAR_STATUS: - addr = NORM_CTRL3_ADDR; - offset = 9; - status_chk = 1; - break; - - case FAL_NROM_IP4_IPID_RANDOM_STATUS: - addr = NORM_CTRL3_ADDR; - offset = 10; - status_chk = 1; - break; - - case FAL_NROM_IP6_INVALID_DIP_CMD: - addr = NORM_CTRL1_ADDR; - offset = 16; - break; - - case FAL_NROM_IP6_INVALID_SIP_CMD: - addr = NORM_CTRL1_ADDR; - offset = 17; - break; - - case FAL_NROM_IP6_INVALID_PL_CMD: - addr = NORM_CTRL1_ADDR; - offset = 18; - break; - - case FAL_NROM_TCP_BLAT_CMD: - addr = NORM_CTRL0_ADDR; - offset = 14; - break; - - case FAL_NROM_TCP_INVALID_HL_CMD: - addr = NORM_CTRL0_ADDR; - offset = 15; - break; - - case FAL_NROM_TCP_MIN_HDR_SIZE: - addr = NORM_CTRL1_ADDR; - offset = 12; - len = 4; - val_chk = 1; - break; - - case FAL_NROM_TCP_INVALID_SYN_CMD: - addr = NORM_CTRL0_ADDR; - offset = 16; - break; - - case FAL_NROM_TCP_SU_BLOCK_CMD: - addr = NORM_CTRL0_ADDR; - offset = 17; - break; - - case FAL_NROM_TCP_SP_BLOCK_CMD: - addr = NORM_CTRL0_ADDR; - offset = 18; - break; - - case FAL_NROM_TCP_SAP_BLOCK_CMD: - addr = NORM_CTRL0_ADDR; - offset = 19; - break; - - case FAL_NROM_TCP_XMAS_SCAN_CMD: - addr = NORM_CTRL0_ADDR; - offset = 20; - break; - - case FAL_NROM_TCP_NULL_SCAN_CMD: - addr = NORM_CTRL0_ADDR; - offset = 21; - break; - - case FAL_NROM_TCP_SR_BLOCK_CMD: - addr = NORM_CTRL0_ADDR; - offset = 22; - break; - - case FAL_NROM_TCP_SF_BLOCK_CMD: - addr = NORM_CTRL0_ADDR; - offset = 23; - break; - - case FAL_NROM_TCP_SAR_BLOCK_CMD: - addr = NORM_CTRL0_ADDR; - offset = 24; - break; - - case FAL_NROM_TCP_RST_SCAN_CMD: - addr = NORM_CTRL0_ADDR; - offset = 25; - break; - - case FAL_NROM_TCP_SYN_WITH_DATA_CMD: - addr = NORM_CTRL0_ADDR; - offset = 26; - break; - - case FAL_NROM_TCP_RST_WITH_DATA_CMD: - addr = NORM_CTRL0_ADDR; - offset = 27; - break; - - case FAL_NROM_TCP_FA_BLOCK_CMD: - addr = NORM_CTRL0_ADDR; - offset = 28; - break; - - case FAL_NROM_TCP_PA_BLOCK_CMD: - addr = NORM_CTRL0_ADDR; - offset = 29; - break; - - case FAL_NROM_TCP_UA_BLOCK_CMD: - addr = NORM_CTRL1_ADDR; - offset = 0; - break; - - case FAL_NROM_TCP_INVALID_CHKSUM_CMD: - addr = NORM_CTRL1_ADDR; - offset = 1; - break; - - case FAL_NROM_TCP_INVALID_URGPTR_CMD: - addr = NORM_CTRL1_ADDR; - offset = 2; - break; - - case FAL_NROM_TCP_INVALID_OPTIONS_CMD: - addr = NORM_CTRL1_ADDR; - offset = 3; - break; - - case FAL_NROM_UDP_BLAT_CMD: - addr = NORM_CTRL1_ADDR; - offset = 4; - break; - - case FAL_NROM_UDP_INVALID_LEN_CMD: - addr = NORM_CTRL1_ADDR; - offset = 5; - break; - - case FAL_NROM_UDP_INVALID_CHKSUM_CMD: - addr = NORM_CTRL1_ADDR; - offset = 6; - break; - - case FAL_NROM_ICMP4_PING_PL_EXCEED_CMD: - addr = NORM_CTRL1_ADDR; - offset = 7; - break; - - case FAL_NROM_ICMP6_PING_PL_EXCEED_CMD: - addr = NORM_CTRL1_ADDR; - offset = 8; - break; - - case FAL_NROM_ICMP4_PING_FRAG_CMD: - addr = NORM_CTRL1_ADDR; - offset = 9; - break; - - case FAL_NROM_ICMP6_PING_FRAG_CMD: - addr = NORM_CTRL1_ADDR; - offset = 10; - break; - - case FAL_NROM_ICMP4_PING_MAX_PL_VALUE: - addr = NORM_CTRL2_ADDR; - offset = 0; - len = 14; - val_chk = 1; - break; - - case FAL_NROM_ICMP6_PING_MAX_PL_VALUE: - addr = NORM_CTRL2_ADDR; - offset = 16; - len = 14; - val_chk = 1; - break; - - default: - return SW_BAD_PARAM; - } - - HSL_REG_ENTRY_GEN_GET(rv, dev_id, addr, sizeof (a_uint32_t), - (a_uint8_t *) (®), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - - SW_FIELD_GET_BY_REG_U32(reg, val, offset, len); - - if (val_chk) - { - *((a_uint32_t *) value) = val; - } - else if (status_chk) - { - if (val) - { - *((a_bool_t *) value) = A_TRUE; - } - else - { - *((a_bool_t *) value) = A_FALSE; - } - } - else if (scmd_chk) - { - if (2 == val) - { - *((fal_fwd_cmd_t *) value) = FAL_MAC_RDT_TO_CPU; - } - else if (3 == val) - { - *((fal_fwd_cmd_t *) value) = FAL_MAC_DROP; - } - else - { - *((fal_fwd_cmd_t *) value) = FAL_MAC_FRWRD; - } - } - else - { - if (val) - { - *((fal_fwd_cmd_t *) value) = FAL_MAC_DROP; - } - else - { - *((fal_fwd_cmd_t *) value) = FAL_MAC_FRWRD; - } - } - - return SW_OK; -} - -/** - * @brief Set normalization particular item types value. - * @details Comments: - * This operation will set normalization item values on a particular device. - * The prototye of value based on the item type. - * @param[in] dev_id device id - * @param[in] item normalizaton item type - * @param[in] value normalizaton item value - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -isisc_sec_norm_item_set(a_uint32_t dev_id, fal_norm_item_t item, void *value) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _isisc_sec_norm_item_set(dev_id, item, value); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Get normalization particular item types value. - * @details Comments: - * This operation will set normalization item values on a particular device. - * The prototye of value based on the item type. - * @param[in] dev_id device id - * @param[in] item normalizaton item type - * @param[out] value normalizaton item value - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -isisc_sec_norm_item_get(a_uint32_t dev_id, fal_norm_item_t item, void *value) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _isisc_sec_norm_item_get(dev_id, item, value); - HSL_API_UNLOCK; - return rv; -} - -sw_error_t -isisc_sec_init(a_uint32_t dev_id) -{ - HSL_DEV_ID_CHECK(dev_id); - -#ifndef HSL_STANDALONG - { - hsl_api_t *p_api; - - SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id)); - p_api->sec_norm_item_set = isisc_sec_norm_item_set; - p_api->sec_norm_item_get = isisc_sec_norm_item_get; - } -#endif - - return SW_OK; -} - -/** - * @} - */ diff --git a/feeds/ipq807x/qca-ssdk/src/src/hsl/isisc/isisc_stp.c b/feeds/ipq807x/qca-ssdk/src/src/hsl/isisc/isisc_stp.c deleted file mode 100755 index dc1716220..000000000 --- a/feeds/ipq807x/qca-ssdk/src/src/hsl/isisc/isisc_stp.c +++ /dev/null @@ -1,193 +0,0 @@ -/* - * Copyright (c) 2012, 2016, The Linux Foundation. All rights reserved. - * Permission to use, copy, modify, and/or distribute this software for - * any purpose with or without fee is hereby granted, provided that the - * above copyright notice and this permission notice appear in all copies. - * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES - * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR - * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES - * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN - * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT - * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. - */ - - -/** - * @defgroup isisc_stp ISISC_STP - * @{ - */ -#include "sw.h" -#include "hsl.h" -#include "hsl_dev.h" -#include "hsl_port_prop.h" -#include "isisc_stp.h" -#include "isisc_reg.h" - -#define ISISC_PORT_DISABLED 0 -#define ISISC_STP_BLOCKING 1 -#define ISISC_STP_LISTENING 2 -#define ISISC_STP_LEARNING 3 -#define ISISC_STP_FARWARDING 4 - -static sw_error_t -_isisc_stp_port_state_set(a_uint32_t dev_id, a_uint32_t st_id, - fal_port_t port_id, fal_stp_state_t state) -{ - sw_error_t rv; - a_uint32_t val; - - HSL_DEV_ID_CHECK(dev_id); - - if (FAL_SINGLE_STP_ID != st_id) - { - return SW_BAD_PARAM; - } - - if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_EXCL_CPU)) - { - return SW_BAD_PARAM; - } - - switch (state) - { - case FAL_STP_BLOKING: - val = ISISC_STP_BLOCKING; - break; - case FAL_STP_LISTENING: - val = ISISC_STP_LISTENING; - break; - case FAL_STP_LEARNING: - val = ISISC_STP_LEARNING; - break; - case FAL_STP_FARWARDING: - val = ISISC_STP_FARWARDING; - break; - case FAL_STP_DISABLED: - val = ISISC_PORT_DISABLED; - break; - default: - return SW_BAD_PARAM; - } - - HSL_REG_FIELD_SET(rv, dev_id, PORT_LOOKUP_CTL, port_id, PORT_STATE, - (a_uint8_t *) (&val), sizeof (a_uint32_t)); - return rv; -} - -static sw_error_t -_isisc_stp_port_state_get(a_uint32_t dev_id, a_uint32_t st_id, - fal_port_t port_id, fal_stp_state_t * state) -{ - sw_error_t rv; - a_uint32_t val = 0; - - HSL_DEV_ID_CHECK(dev_id); - - if (FAL_SINGLE_STP_ID != st_id) - { - return SW_BAD_PARAM; - } - - if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_EXCL_CPU)) - { - return SW_BAD_PARAM; - } - - HSL_REG_FIELD_GET(rv, dev_id, PORT_LOOKUP_CTL, port_id, PORT_STATE, - (a_uint8_t *) (&val), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - - switch (val) - { - case ISISC_STP_BLOCKING: - *state = FAL_STP_BLOKING; - break; - case ISISC_STP_LISTENING: - *state = FAL_STP_LISTENING; - break; - case ISISC_STP_LEARNING: - *state = FAL_STP_LEARNING; - break; - case ISISC_STP_FARWARDING: - *state = FAL_STP_FARWARDING; - break; - case ISISC_PORT_DISABLED: - *state = FAL_STP_DISABLED; - break; - default: - return SW_FAIL; - } - - return SW_OK; -} - -/** - * @brief Set port stp state on a particular spanning tree and port. - * @details Comments: - Garuda only support single spanning tree so st_id should be - FAL_SINGLE_STP_ID that is zero. - * @param[in] dev_id device id - * @param[in] st_id spanning tree id - * @param[in] port_id port id - * @param[in] state port state for spanning tree - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -isisc_stp_port_state_set(a_uint32_t dev_id, a_uint32_t st_id, - fal_port_t port_id, fal_stp_state_t state) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _isisc_stp_port_state_set(dev_id, st_id, port_id, state); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Get port stp state on a particular spanning tree and port. - * @details Comments: - Garuda only support single spanning tree so st_id should be - FAL_SINGLE_STP_ID that is zero. - * @param[in] dev_id device id - * @param[in] st_id spanning tree id - * @param[in] port_id port id - * @param[out] state port state for spanning tree - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -isisc_stp_port_state_get(a_uint32_t dev_id, a_uint32_t st_id, - fal_port_t port_id, fal_stp_state_t * state) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _isisc_stp_port_state_get(dev_id, st_id, port_id, state); - HSL_API_UNLOCK; - return rv; -} - -sw_error_t -isisc_stp_init(a_uint32_t dev_id) -{ - HSL_DEV_ID_CHECK(dev_id); - -#ifndef HSL_STANDALONG - { - hsl_api_t *p_api; - - SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id)); - - p_api->stp_port_state_set = isisc_stp_port_state_set; - p_api->stp_port_state_get = isisc_stp_port_state_get; - } -#endif - - return SW_OK; -} - -/** - * @} - */ - diff --git a/feeds/ipq807x/qca-ssdk/src/src/hsl/isisc/isisc_trunk.c b/feeds/ipq807x/qca-ssdk/src/src/hsl/isisc/isisc_trunk.c deleted file mode 100755 index 2ed7936db..000000000 --- a/feeds/ipq807x/qca-ssdk/src/src/hsl/isisc/isisc_trunk.c +++ /dev/null @@ -1,692 +0,0 @@ -/* - * Copyright (c) 2012, 2016, The Linux Foundation. All rights reserved. - * Permission to use, copy, modify, and/or distribute this software for - * any purpose with or without fee is hereby granted, provided that the - * above copyright notice and this permission notice appear in all copies. - * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES - * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR - * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES - * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN - * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT - * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. - */ - - - -/** - * @defgroup isisc_trunk ISISC_TRUNK - * @{ - */ -#include "sw.h" -#include "hsl.h" -#include "hsl_dev.h" -#include "hsl_port_prop.h" -#include "isisc_trunk.h" -#include "isisc_reg.h" - -#define ISISC_MAX_TRUNK_ID 3 - -/*feature on/off for manipulating dp within trunk group*/ -#define ISISC_TRUNK_MANIPULATE_DP_ON 1 -#define ISISC_TRUNK_MANIPULATE_HEADER_LEN 12 -#define MAC_LEN 6 -#define HASH_SIZE 4 - -enum isisc_trunk_reg_id -{ - ISISC_TRUNK_HASH_EN = 0, /*0x270*/ - ISISC_TRUNK_CTRL_0, /*0x700*/ - ISISC_TRUNK_CTRL_1, /*0x704*/ - ISISC_TRUNK_CTRL_2, /*0x708*/ - ISISC_TRUNK_REG_MAX -}; - -static a_uint32_t isisc_trunk_regs[ISISC_TRUNK_REG_MAX] = -{ - 0xf, 0x0, 0x0, 0x0 -}; - -static a_uint8_t sa_hash[HASH_SIZE][MAC_LEN] = -{ - { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 }, - { 0x00, 0x00, 0x00, 0x00, 0x00, 0x01 }, - { 0x00, 0x00, 0x00, 0x00, 0x00, 0x02 }, - { 0x00, 0x00, 0x00, 0x00, 0x00, 0x03 } -}; - -static sw_error_t -_isisc_trunk_group_set(a_uint32_t dev_id, a_uint32_t trunk_id, - a_bool_t enable, fal_pbmp_t member) -{ - sw_error_t rv; - a_uint32_t i, reg = 0, cnt = 0, data0 = 0, data1 = 0; - - if (ISISC_MAX_TRUNK_ID < trunk_id) - { - return SW_BAD_PARAM; - } - - if (A_FALSE == hsl_mports_prop_check(dev_id, member, HSL_PP_INCL_CPU)) - { - return SW_BAD_PARAM; - } - - if (A_TRUE == enable) - { - data0 = (0x1 << 7) | member; - - for (i = 0; i < 7; i++) - { - if (member & (0x1 << i)) - { - if (4 <= cnt) - { - return SW_BAD_PARAM; - } - - data1 |= (i << (cnt << 2)); - data1 |= (1 << (3 + (cnt << 2))); - cnt++; - } - } - } - else if (A_FALSE == enable) - { - - } - else - { - return SW_BAD_PARAM; - } - - /* set trunk port member bitmap info */ - HSL_REG_ENTRY_GET(rv, dev_id, GOL_TRUNK_CTL0, 0, - (a_uint8_t *) (®), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - - reg &= (~(0xff << (trunk_id << 3))); - reg |= (data0 << (trunk_id << 3)); - - HSL_REG_ENTRY_SET(rv, dev_id, GOL_TRUNK_CTL0, 0, - (a_uint8_t *) (®), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - - isisc_trunk_regs[ISISC_TRUNK_CTRL_0] = reg; - - /* set trunk port member id info */ - HSL_REG_ENTRY_GET(rv, dev_id, GOL_TRUNK_CTL1, (trunk_id >> 1), - (a_uint8_t *) (®), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - - reg &= (~(0xffff << ((trunk_id % 2) << 4))); - reg |= (data1 << ((trunk_id % 2) << 4)); - - HSL_REG_ENTRY_SET(rv, dev_id, GOL_TRUNK_CTL1, (trunk_id >> 1), - (a_uint8_t *) (®), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - - isisc_trunk_regs[ISISC_TRUNK_CTRL_1 + (trunk_id >> 1)] = reg; - - return SW_OK; -} - -static sw_error_t -_isisc_trunk_group_get(a_uint32_t dev_id, a_uint32_t trunk_id, - a_bool_t * enable, fal_pbmp_t * member) -{ - sw_error_t rv; - a_uint32_t data, reg = 0; - - if (ISISC_MAX_TRUNK_ID < trunk_id) - { - return SW_BAD_PARAM; - } - - HSL_REG_ENTRY_GET(rv, dev_id, GOL_TRUNK_CTL0, 0, - (a_uint8_t *) (®), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - - data = (reg >> (trunk_id << 3)) & 0xff; - if (0x80 & data) - { - *enable = A_TRUE; - *member = data & 0x7f; - } - else - { - *enable = A_FALSE; - *member = 0; - } - - return SW_OK; -} - -#if 0 -static sw_error_t -_isisc_trunk_group_sw_get(a_uint32_t dev_id, a_uint32_t trunk_id, - a_bool_t * enable, fal_pbmp_t * member) -{ - a_uint32_t data, reg; - - if (ISISC_MAX_TRUNK_ID < trunk_id) - { - return SW_BAD_PARAM; - } - - reg = isisc_trunk_regs[ISISC_TRUNK_CTRL_0]; - - data = (reg >> (trunk_id << 3)) & 0xff; - if (0x80 & data) - { - *enable = A_TRUE; - *member = data & 0x7f; - } - else - { - *enable = A_FALSE; - *member = 0; - } - - return SW_OK; -} -#endif - -static sw_error_t -_isisc_trunk_hash_mode_set(a_uint32_t dev_id, a_uint32_t hash_mode) -{ - sw_error_t rv; - a_uint32_t data = 0; - - if (FAL_TRUNK_HASH_KEY_DA & hash_mode) - { - SW_SET_REG_BY_FIELD(TRUNK_HASH_MODE, DA_EN, 1, data); - } - - if (FAL_TRUNK_HASH_KEY_SA & hash_mode) - { - SW_SET_REG_BY_FIELD(TRUNK_HASH_MODE, SA_EN, 1, data); - } - - if (FAL_TRUNK_HASH_KEY_DIP & hash_mode) - { - SW_SET_REG_BY_FIELD(TRUNK_HASH_MODE, DIP_EN, 1, data); - } - - if (FAL_TRUNK_HASH_KEY_SIP & hash_mode) - { - SW_SET_REG_BY_FIELD(TRUNK_HASH_MODE, SIP_EN, 1, data); - } - - HSL_REG_ENTRY_SET(rv, dev_id, TRUNK_HASH_MODE, 0, - (a_uint8_t *) (&data), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - - isisc_trunk_regs[ISISC_TRUNK_HASH_EN] = data; - - return rv; -} - -static sw_error_t -_isisc_trunk_hash_mode_get(a_uint32_t dev_id, a_uint32_t * hash_mode) -{ - sw_error_t rv; - a_uint32_t reg = 0, data = 0; - - HSL_REG_ENTRY_GET(rv, dev_id, TRUNK_HASH_MODE, 0, - (a_uint8_t *) (®), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - - *hash_mode = 0; - - SW_GET_FIELD_BY_REG(TRUNK_HASH_MODE, DA_EN, data, reg); - if (data) - { - *hash_mode |= FAL_TRUNK_HASH_KEY_DA; - } - - SW_GET_FIELD_BY_REG(TRUNK_HASH_MODE, SA_EN, data, reg); - if (data) - { - *hash_mode |= FAL_TRUNK_HASH_KEY_SA; - } - - SW_GET_FIELD_BY_REG(TRUNK_HASH_MODE, DIP_EN, data, reg); - if (data) - { - *hash_mode |= FAL_TRUNK_HASH_KEY_DIP; - } - - SW_GET_FIELD_BY_REG(TRUNK_HASH_MODE, SIP_EN, data, reg); - if (data) - { - *hash_mode |= FAL_TRUNK_HASH_KEY_SIP; - } - - return SW_OK; -} - -#define BYTE_B2R(x, mask) ((x) ^ (mask)) -#define BYTE_B1C(x) ((((((x&0x55)+((x&0xaa)>>1))&0x33)+((((x&0x55)+((x&0xaa)>>1))&0xcc)>>2))&0x0f)+((((((x&0x55)+((x&0xaa)>>1))&0x33)+((((x&0x55)+((x&0xaa)>>1))&0xcc)>>2))&0xf0)>>4)) - -static sw_error_t -_isisc_trunk_manipulate_sa_set(a_uint32_t dev_id, fal_mac_addr_t * addr) -{ - a_uint32_t i; - - for (i = 0; i < HASH_SIZE; i++) - { - memcpy(sa_hash[i], addr->uc, MAC_LEN); - sa_hash[i][MAC_LEN - 1] = BYTE_B2R(sa_hash[i][MAC_LEN - 1], i); - } - - return SW_OK; -} - -static sw_error_t -_isisc_trunk_manipulate_sa_get(a_uint32_t dev_id, fal_mac_addr_t * addr) -{ - memcpy(addr->uc, sa_hash[0], MAC_LEN); - return SW_OK; -} - -#if 0 -static sw_error_t -_isisc_trunk_hash_mode_sw_get(a_uint32_t dev_id, a_uint32_t * hash_mode) -{ - a_uint32_t reg, data = 0; - - reg = isisc_trunk_regs[ISISC_TRUNK_HASH_EN]; - - *hash_mode = 0; - - SW_GET_FIELD_BY_REG(TRUNK_HASH_MODE, DA_EN, data, reg); - if (data) - { - *hash_mode |= FAL_TRUNK_HASH_KEY_DA; - } - - SW_GET_FIELD_BY_REG(TRUNK_HASH_MODE, SA_EN, data, reg); - if (data) - { - *hash_mode |= FAL_TRUNK_HASH_KEY_SA; - } - - SW_GET_FIELD_BY_REG(TRUNK_HASH_MODE, DIP_EN, data, reg); - if (data) - { - *hash_mode |= FAL_TRUNK_HASH_KEY_DIP; - } - - SW_GET_FIELD_BY_REG(TRUNK_HASH_MODE, SIP_EN, data, reg); - if (data) - { - *hash_mode |= FAL_TRUNK_HASH_KEY_SIP; - } - - return SW_OK; -} - -static sw_error_t -_isisc_trunk_id_member_get(a_uint32_t dev_id, a_uint8_t expect_dp, - a_uint32_t * trunk_id, fal_pbmp_t * member) -{ - sw_error_t rv; - a_bool_t enable; - a_uint32_t i; - - for (i = 0; i <= ISISC_MAX_TRUNK_ID; i++) - { - rv = _isisc_trunk_group_sw_get(dev_id, i, &enable, member); - SW_RTN_ON_ERROR(rv); - if (enable && (*member & expect_dp)) - { - *trunk_id = i; - return SW_OK; - } - } - - return SW_NOT_FOUND; -} - -static sw_error_t -_isisc_trunk_hash_dp_get(a_uint32_t dev_id, a_uint8_t * header, a_uint32_t len, - a_uint32_t trunk_id, a_uint32_t mode, a_uint8_t * hash_dp) -{ -#define BIT2_MASK 0x03 -#define TRUNK_MEM_EN_MASK 0x8 -#define TRUNK_MEM_PT_MASK 0x7 -#define TRUNK_HASH_DP_SEL 4 - sw_error_t rv; - a_uint32_t i, hash_mode, reg, data1 = 0; - a_uint32_t da_xor = 0, sa_xor = 0; /*consider da-hash & sa-hash (TBD: dip-hash & sip-hash)*/ - a_uint8_t xor_dp = 0; - - rv = _isisc_trunk_hash_mode_sw_get(dev_id, &hash_mode); - SW_RTN_ON_ERROR(rv); - - if (!hash_mode) - { - return SW_DISABLE; - } - - *hash_dp = 0; - - if ((mode & FAL_TRUNK_HASH_KEY_DA) && (hash_mode & FAL_TRUNK_HASH_KEY_DA)) - { - for (i = 0; i < MAC_LEN; i++) - { - da_xor ^= (header[i] & BIT2_MASK) ^ - ((header[i] >> 2) & BIT2_MASK) ^ - ((header[i] >> 4) & BIT2_MASK) ^ - ((header[i] >> 6) & BIT2_MASK); - } - *hash_dp = da_xor; - } - if ((mode & FAL_TRUNK_HASH_KEY_SA) && (hash_mode & FAL_TRUNK_HASH_KEY_SA)) - { - for (i = 6; i < 2 * MAC_LEN; i++) - { - sa_xor ^= (header[i] & BIT2_MASK) ^ - ((header[i] >> 2) & BIT2_MASK) ^ - ((header[i] >> 4) & BIT2_MASK) ^ - ((header[i] >> 6) & BIT2_MASK); - } - *hash_dp = (*hash_dp) ^ sa_xor; - } - - /*dp translation*/ -#if 0 - HSL_REG_ENTRY_GET(rv, dev_id, GOL_TRUNK_CTL1, (trunk_id >> 1), - (a_uint8_t *) (®), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); -#else /*sw*/ - reg = isisc_trunk_regs[ISISC_TRUNK_CTRL_1 + (trunk_id >> 1)]; -#endif - - for (i = 0; i < TRUNK_HASH_DP_SEL; i++) - { - xor_dp = BYTE_B2R(*hash_dp, i); - data1 = (0x0f & (reg >> (((trunk_id % 2) << 4) + (xor_dp << 2)))); - if (data1 & TRUNK_MEM_EN_MASK) - { - *hash_dp = data1 & TRUNK_MEM_PT_MASK; - *hash_dp = 0x01 << (*hash_dp); /*bmp*/ - return SW_OK; - } - } - - return SW_NOT_FOUND; -} - -static sw_error_t -_isisc_trunk_sa_spoofing( a_uint32_t dev_id, a_uint8_t * header, a_uint32_t len, - a_uint8_t expect_dp, a_uint32_t trunk_id, fal_pbmp_t member) -{ - sw_error_t rv; - a_uint32_t i, hash_mode; - a_uint8_t hash_dp; - a_uint8_t ori_sa[MAC_LEN]; - - rv = _isisc_trunk_hash_mode_sw_get(dev_id, &hash_mode); - SW_RTN_ON_ERROR(rv); - - if (!(hash_mode & FAL_TRUNK_HASH_KEY_SA)) - { - return SW_DISABLE; - } - - memcpy(ori_sa, &header[MAC_LEN], MAC_LEN); - - for (i = 0; i < HASH_SIZE/*not HASH_SIZE, for RAD only*/; i++) - { - memcpy(&header[MAC_LEN], sa_hash[i], MAC_LEN); - rv = _isisc_trunk_hash_dp_get(dev_id, header, len, trunk_id, - FAL_TRUNK_HASH_KEY_DA | FAL_TRUNK_HASH_KEY_SA, &hash_dp); - SW_RTN_ON_ERROR(rv); - if (expect_dp == hash_dp) - { - // printk("expect_dp = 0x%x, hash_dp(DA+SA) = 0x%x, sa_id = %d\n", expect_dp, hash_dp, i); - return SW_OK; - } - } - - /*should never here*/ - memcpy(&header[MAC_LEN], ori_sa, MAC_LEN); - return SW_FAIL; -} - -static sw_error_t -_isisc_trunk_manipulate_dp(a_uint32_t dev_id, a_uint8_t * header, - a_uint32_t len, fal_pbmp_t dp_member) -{ - sw_error_t rv; - a_uint8_t expect_dp, hash_dp; /*bitmap*/ - a_uint32_t i, trunk_id; - fal_pbmp_t member; - - if (!ISISC_TRUNK_MANIPULATE_DP_ON) - { - return SW_OK; /*feature not enabled*/ - } - - if (!header || len < ISISC_TRUNK_MANIPULATE_HEADER_LEN) - { - return SW_BAD_VALUE; - } - -#if 0 /*de-comment this to ignore broadcast packets*/ - const a_uint8_t bc_mac[MAC_LEN] = { 0xff, 0xff, 0xff, 0xff, 0xff, 0xff }; - if (!memcmp(header, bc_mac, MAC_LEN)) /*not for broadcast*/ - { - return SW_OK; - } -#endif - - /*expect_dp within trunk group*/ - expect_dp = dp_member & 0x7f; - for (i = 0; i < 7; i++) - { - if (expect_dp & (0x01 << i)) - { - rv = _isisc_trunk_id_member_get(dev_id, (0x01 << i), &trunk_id, &member); - if (rv != SW_OK) - { - expect_dp &= ~(0x01 << i); /*not the dp doesn't belong to trunk*/ - } - } - } - - if (BYTE_B1C(expect_dp) != 1) /*supports 1 dp only*/ - { - return SW_OK; /*ignore none-dp or multi-dp*/ - } - - rv = _isisc_trunk_id_member_get(dev_id, expect_dp, &trunk_id, &member); - SW_RTN_ON_ERROR(rv); - - member &= 0x7f; - if (BYTE_B1C(member) == 1) /*trunk group w/ one port*/ - { - return SW_OK; - } - - rv = _isisc_trunk_hash_dp_get(dev_id, header, len, trunk_id, - FAL_TRUNK_HASH_KEY_DA | FAL_TRUNK_HASH_KEY_SA, &hash_dp); - SW_RTN_ON_ERROR(rv); - - // printk("expect_dp = 0x%x, hash_dp(DA+SA) = 0x%x, member = 0x%x\n", expect_dp, hash_dp, member); - if (expect_dp == hash_dp) - { - return SW_OK; - } - - rv = _isisc_trunk_sa_spoofing(dev_id, header, len, expect_dp, trunk_id, member); - SW_RTN_ON_ERROR(rv); - - return rv; -} -#endif - -/** - * @brief Set particular trunk group information on particular device. - * @param[in] dev_id device id - * @param[in] trunk_id trunk group id - * @param[in] enable trunk group status, enable or disable - * @param[in] member port member information - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -isisc_trunk_group_set(a_uint32_t dev_id, a_uint32_t trunk_id, - a_bool_t enable, fal_pbmp_t member) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _isisc_trunk_group_set(dev_id, trunk_id, enable, member); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Get particular trunk group information on particular device. - * @param[in] dev_id device id - * @param[in] trunk_id trunk group id - * @param[out] enable trunk group status, enable or disable - * @param[out] member port member information - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -isisc_trunk_group_get(a_uint32_t dev_id, a_uint32_t trunk_id, - a_bool_t * enable, fal_pbmp_t * member) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _isisc_trunk_group_get(dev_id, trunk_id, enable, member); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Set trunk hash mode on particular device. - * @details Comments: - hash mode is listed below - FAL_TRUNK_HASH_KEY_DA, FAL_TRUNK_HASH_KEY_SA, FAL_TRUNK_HASH_KEY_DIP and FAL_TRUNK_HASH_KEY_SIP - * @param[in] dev_id device id - * @param[in] hash_mode trunk hash mode - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -isisc_trunk_hash_mode_set(a_uint32_t dev_id, a_uint32_t hash_mode) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _isisc_trunk_hash_mode_set(dev_id, hash_mode); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Get trunk hash mode on particular device. - * @param[in] dev_id device id - * @param[out] hash_mode trunk hash mode - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -isisc_trunk_hash_mode_get(a_uint32_t dev_id, a_uint32_t * hash_mode) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _isisc_trunk_hash_mode_get(dev_id, hash_mode); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Set trunk manipulate SA on particular device. - * @param[in] dev_id device id - * @param[in] addr manipulate SA - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -isisc_trunk_manipulate_sa_set(a_uint32_t dev_id, fal_mac_addr_t * addr) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _isisc_trunk_manipulate_sa_set(dev_id, addr); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Get trunk manipulate SA on particular device. - * @param[in] dev_id device id - * @param[out] addr manipulate SA - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -isisc_trunk_manipulate_sa_get(a_uint32_t dev_id, fal_mac_addr_t * addr) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _isisc_trunk_manipulate_sa_get(dev_id, addr); - HSL_API_UNLOCK; - return rv; -} - -#if 0 -/** - * @brief manipulate destination port within a trunk group - * @details Comments: - * supporting hash mode include: FAL_TRUNK_HASH_KEY_DA & FAL_TRUNK_HASH_KEY_SA; - * FAL_TRUNK_HASH_KEY_DIP & FAL_TRUNK_HASH_KEY_SIP are NOT covered in current design - * @param[in] dev_id device id - * @param[in-out] header packet header, accept format: [DA:6B][SA:6B] - * @param[in] len length of packet header, should be 12 in current design (6B DA + 6B SA) - * @param[in] dp_member expect destination port members, bitmap format - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -isisc_trunk_manipulate_dp(a_uint32_t dev_id, a_uint8_t * header, - a_uint32_t len, fal_pbmp_t dp_member) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _isisc_trunk_manipulate_dp(dev_id, header, len, dp_member); - HSL_API_UNLOCK; - return rv; -} -#endif - -sw_error_t -isisc_trunk_init(a_uint32_t dev_id) -{ - HSL_DEV_ID_CHECK(dev_id); - -#ifndef HSL_STANDALONG - { - hsl_api_t *p_api; - - SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id)); - p_api->trunk_group_set = isisc_trunk_group_set; - p_api->trunk_group_get = isisc_trunk_group_get; - p_api->trunk_hash_mode_set = isisc_trunk_hash_mode_set; - p_api->trunk_hash_mode_get = isisc_trunk_hash_mode_get; - p_api->trunk_manipulate_sa_set = isisc_trunk_manipulate_sa_set; - p_api->trunk_manipulate_sa_get = isisc_trunk_manipulate_sa_get; - } -#endif - - return SW_OK; -} - -/** - * @} - */ - diff --git a/feeds/ipq807x/qca-ssdk/src/src/hsl/isisc/isisc_vlan.c b/feeds/ipq807x/qca-ssdk/src/src/hsl/isisc/isisc_vlan.c deleted file mode 100755 index 1d613175c..000000000 --- a/feeds/ipq807x/qca-ssdk/src/src/hsl/isisc/isisc_vlan.c +++ /dev/null @@ -1,906 +0,0 @@ -/* - * Copyright (c) 2012, The Linux Foundation. All rights reserved. - * Permission to use, copy, modify, and/or distribute this software for - * any purpose with or without fee is hereby granted, provided that the - * above copyright notice and this permission notice appear in all copies. - * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES - * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR - * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES - * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN - * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT - * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. - */ - - -/** - * @defgroup isisc_vlan ISISC_VLAN - * @{ - */ -#include "sw.h" -#include "hsl.h" -#include "hsl_dev.h" -#include "hsl_port_prop.h" -#include "isisc_vlan.h" -#include "isisc_reg.h" - -#define MAX_VLAN_ID 4095 - -#define VLAN_FLUSH 1 -#define VLAN_LOAD_ENTRY 2 -#define VLAN_PURGE_ENTRY 3 -#define VLAN_REMOVE_PORT 4 -#define VLAN_NEXT_ENTRY 5 -#define VLAN_FIND_ENTRY 6 - -static void -_isisc_vlan_hw_to_sw(a_uint32_t reg[], fal_vlan_t * vlan_entry) -{ - a_uint32_t i, data, tmp; - - aos_mem_zero(vlan_entry, sizeof (fal_vlan_t)); - - SW_GET_FIELD_BY_REG(VLAN_TABLE_FUNC1, VLAN_ID, data, reg[1]); - vlan_entry->vid = data & 0xfff; - - SW_GET_FIELD_BY_REG(VLAN_TABLE_FUNC0, IVL_EN, data, reg[0]); - if (1 == data) - { - vlan_entry->fid = vlan_entry->vid; - } - else - { - vlan_entry->fid = FAL_SVL_FID; - } - - SW_GET_FIELD_BY_REG(VLAN_TABLE_FUNC0, LEARN_DIS, data, reg[0]); - if (1 == data) - { - vlan_entry->learn_dis = A_TRUE; - } - else - { - vlan_entry->learn_dis = A_FALSE; - } - - SW_GET_FIELD_BY_REG(VLAN_TABLE_FUNC0, VT_PRI_EN, data, reg[0]); - if (1 == data) - { - vlan_entry->vid_pri_en = A_TRUE; - - SW_GET_FIELD_BY_REG(VLAN_TABLE_FUNC0, VT_PRI, data, reg[0]); - vlan_entry->vid_pri = data & 0xff; - } - else - { - vlan_entry->vid_pri_en = A_FALSE; - } - - SW_GET_FIELD_BY_REG(VLAN_TABLE_FUNC0, VID_MEM, data, reg[0]); - for (i = 0; i < 7; i++) - { - tmp = (data >> (i << 1)) & 0x3UL; - if (0 == tmp) - { - vlan_entry->mem_ports |= (0x1UL << i); - vlan_entry->unmodify_ports |= (0x1UL << i); - } - else if (1 == tmp) - { - vlan_entry->mem_ports |= (0x1UL << i); - vlan_entry->untagged_ports |= (0x1UL << i); - } - else if (2 == tmp) - { - vlan_entry->mem_ports |= (0x1UL << i); - vlan_entry->tagged_ports |= (0x1UL << i); - } - } - - return; -} - -static sw_error_t -_isisc_vlan_sw_to_hw(a_uint32_t dev_id, const fal_vlan_t * vlan_entry, - a_uint32_t reg[]) -{ - a_uint32_t i, tag, untag, unmodify, member = 0; - - if (vlan_entry->vid > MAX_VLAN_ID) - { - return SW_OUT_OF_RANGE; - } - - if (A_FALSE == - hsl_mports_prop_check(dev_id, vlan_entry->mem_ports, HSL_PP_INCL_CPU)) - { - return SW_BAD_PARAM; - } - - SW_SET_REG_BY_FIELD(VLAN_TABLE_FUNC0, VT_VALID, 1, reg[0]); - - if (FAL_SVL_FID == vlan_entry->fid) - { - SW_SET_REG_BY_FIELD(VLAN_TABLE_FUNC0, IVL_EN, 0, reg[0]); - } - else if (vlan_entry->vid == vlan_entry->fid) - { - SW_SET_REG_BY_FIELD(VLAN_TABLE_FUNC0, IVL_EN, 1, reg[0]); - } - else - { - return SW_BAD_VALUE; - } - - if (A_TRUE == vlan_entry->learn_dis) - { - SW_SET_REG_BY_FIELD(VLAN_TABLE_FUNC0, LEARN_DIS, 1, reg[0]); - } - else - { - SW_SET_REG_BY_FIELD(VLAN_TABLE_FUNC0, LEARN_DIS, 0, reg[0]); - } - - for (i = 0; i < 7; i++) - { - if ((vlan_entry->mem_ports >> i) & 0x1UL) - { - tag = (vlan_entry->tagged_ports >> i) & 0x1UL; - untag = (vlan_entry->untagged_ports >> i) & 0x1UL; - unmodify = (vlan_entry->unmodify_ports >> i) & 0x1UL; - - if ((0 == (tag + untag + unmodify)) - || (1 < (tag + untag + unmodify))) - { - return SW_BAD_VALUE; - } - - if (tag) - { - member |= (2 << (i << 1)); - } - else if (untag) - { - member |= (1 << (i << 1)); - } - } - else - { - member |= (3 << (i << 1)); - } - } - SW_SET_REG_BY_FIELD(VLAN_TABLE_FUNC0, VID_MEM, member, reg[0]); - - if (A_TRUE == vlan_entry->vid_pri_en) - { - SW_SET_REG_BY_FIELD(VLAN_TABLE_FUNC0, VT_PRI_EN, 1, reg[0]); - SW_SET_REG_BY_FIELD(VLAN_TABLE_FUNC0, VT_PRI, vlan_entry->vid_pri, - reg[0]); - } - else - { - SW_SET_REG_BY_FIELD(VLAN_TABLE_FUNC0, VT_PRI_EN, 0, reg[0]); - } - - SW_SET_REG_BY_FIELD(VLAN_TABLE_FUNC1, VLAN_ID, vlan_entry->vid, reg[1]); - - return SW_OK; -} - -static sw_error_t -_isisc_vlan_down_to_hw(a_uint32_t dev_id, a_uint32_t reg[]) -{ - sw_error_t rv; - - HSL_REG_ENTRY_SET(rv, dev_id, VLAN_TABLE_FUNC0, 0, - (a_uint8_t *) (®[0]), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - - HSL_REG_ENTRY_SET(rv, dev_id, VLAN_TABLE_FUNC1, 0, - (a_uint8_t *) (®[1]), sizeof (a_uint32_t)); - return rv; -} - -static sw_error_t -_isisc_vlan_up_to_sw(a_uint32_t dev_id, a_uint32_t reg[]) -{ - sw_error_t rv; - - HSL_REG_ENTRY_GET(rv, dev_id, VLAN_TABLE_FUNC0, 0, - (a_uint8_t *) (®[0]), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - - HSL_REG_ENTRY_GET(rv, dev_id, VLAN_TABLE_FUNC1, 0, - (a_uint8_t *) (®[1]), sizeof (a_uint32_t)); - return rv; -} - -static sw_error_t -_isisc_vlan_commit(a_uint32_t dev_id, a_uint32_t op) -{ - a_uint32_t vt_busy = 1, i = 0x1000, vt_full, val; - sw_error_t rv; - - while (vt_busy && --i) - { - HSL_REG_FIELD_GET(rv, dev_id, VLAN_TABLE_FUNC1, 0, VT_BUSY, - (a_uint8_t *) (&vt_busy), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - aos_udelay(5); - } - - if (i == 0) - return SW_BUSY; - - HSL_REG_ENTRY_GET(rv, dev_id, VLAN_TABLE_FUNC1, 0, - (a_uint8_t *) (&val), sizeof (a_uint32_t)); - SW_SET_REG_BY_FIELD(VLAN_TABLE_FUNC1, VT_FUNC, op, val); - SW_SET_REG_BY_FIELD(VLAN_TABLE_FUNC1, VT_BUSY, 1, val); - - HSL_REG_ENTRY_SET(rv, dev_id, VLAN_TABLE_FUNC1, 0, - (a_uint8_t *) (&val), sizeof (a_uint32_t)); - - SW_RTN_ON_ERROR(rv); - - vt_busy = 1; - i = 0x1000; - while (vt_busy && --i) - { - HSL_REG_FIELD_GET(rv, dev_id, VLAN_TABLE_FUNC1, 0, VT_BUSY, - (a_uint8_t *) (&vt_busy), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - aos_udelay(5); - } - - if (i == 0) - return SW_FAIL; - - HSL_REG_FIELD_GET(rv, dev_id, VLAN_TABLE_FUNC1, 0, VT_FULL_VIO, - (a_uint8_t *) (&vt_full), sizeof (a_uint32_t)); - - SW_RTN_ON_ERROR(rv); - - if (vt_full) - { - val = 0x10; - HSL_REG_ENTRY_SET(rv, dev_id, VLAN_TABLE_FUNC1, 0, - (a_uint8_t *) (&val), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - if (VLAN_LOAD_ENTRY == op) - { - return SW_FULL; - } - else if (VLAN_PURGE_ENTRY == op) - { - return SW_NOT_FOUND; - } - } - - HSL_REG_FIELD_GET(rv, dev_id, VLAN_TABLE_FUNC0, 0, VT_VALID, - (a_uint8_t *) (&val), sizeof (a_uint32_t)); - - SW_RTN_ON_ERROR(rv); - - if (!val) - { - if (VLAN_FIND_ENTRY == op) - return SW_NOT_FOUND; - - if (VLAN_NEXT_ENTRY == op) - return SW_NO_MORE; - } - - return SW_OK; -} - -static sw_error_t -_isisc_vlan_hwentry_get(a_uint32_t dev_id, a_uint32_t vlan_id, a_uint32_t reg[]) -{ - sw_error_t rv; - - if (vlan_id > MAX_VLAN_ID) - { - return SW_OUT_OF_RANGE; - } - - SW_SET_REG_BY_FIELD(VLAN_TABLE_FUNC1, VLAN_ID, vlan_id, reg[1]); - HSL_REG_ENTRY_SET(rv, dev_id, VLAN_TABLE_FUNC1, 0, - (a_uint8_t *) (®[1]), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - - rv = _isisc_vlan_commit(dev_id, VLAN_FIND_ENTRY); - SW_RTN_ON_ERROR(rv); - - rv = _isisc_vlan_up_to_sw(dev_id, reg); - return rv; -} - -static sw_error_t -_isisc_vlan_entry_append(a_uint32_t dev_id, const fal_vlan_t * vlan_entry) -{ - sw_error_t rv; - a_uint32_t reg[2] = { 0 }; - - HSL_DEV_ID_CHECK(dev_id); - - rv = _isisc_vlan_sw_to_hw(dev_id, vlan_entry, reg); - SW_RTN_ON_ERROR(rv); - - rv = _isisc_vlan_down_to_hw(dev_id, reg); - SW_RTN_ON_ERROR(rv); - - rv = _isisc_vlan_commit(dev_id, VLAN_LOAD_ENTRY); - return rv; -} - -static sw_error_t -_isisc_vlan_create(a_uint32_t dev_id, a_uint32_t vlan_id) -{ - sw_error_t rv; - a_uint32_t reg[2] = { 0 }; - - HSL_DEV_ID_CHECK(dev_id); - - if (vlan_id > MAX_VLAN_ID) - { - return SW_OUT_OF_RANGE; - } - - SW_SET_REG_BY_FIELD(VLAN_TABLE_FUNC0, VT_VALID, 1, reg[0]); - SW_SET_REG_BY_FIELD(VLAN_TABLE_FUNC0, IVL_EN, 1, reg[0]); - SW_SET_REG_BY_FIELD(VLAN_TABLE_FUNC0, LEARN_DIS, 0, reg[0]); - SW_SET_REG_BY_FIELD(VLAN_TABLE_FUNC0, VID_MEM, 0x3fff, reg[0]); - SW_SET_REG_BY_FIELD(VLAN_TABLE_FUNC1, VLAN_ID, vlan_id, reg[1]); - - rv = _isisc_vlan_down_to_hw(dev_id, reg); - SW_RTN_ON_ERROR(rv); - - rv = _isisc_vlan_commit(dev_id, VLAN_LOAD_ENTRY); - return rv; -} - -static sw_error_t -_isisc_vlan_next(a_uint32_t dev_id, a_uint32_t vlan_id, fal_vlan_t * p_vlan) -{ - sw_error_t rv; - a_uint32_t reg[2] = { 0 }; - - HSL_DEV_ID_CHECK(dev_id); - - if (FAL_NEXT_ENTRY_FIRST_ID == vlan_id) - { - rv = _isisc_vlan_hwentry_get(dev_id, 0, reg); - - if (SW_OK == rv) - { - _isisc_vlan_hw_to_sw(reg, p_vlan); - return SW_OK; - } - else - { - vlan_id = 0; - } - } - - if (vlan_id > MAX_VLAN_ID) - return SW_OUT_OF_RANGE; - - SW_SET_REG_BY_FIELD(VLAN_TABLE_FUNC1, VLAN_ID, vlan_id, reg[1]); - HSL_REG_ENTRY_SET(rv, dev_id, VLAN_TABLE_FUNC1, 0, - (a_uint8_t *) (®[1]), sizeof (a_uint32_t)); - - SW_RTN_ON_ERROR(rv); - - rv = _isisc_vlan_commit(dev_id, VLAN_NEXT_ENTRY); - SW_RTN_ON_ERROR(rv); - - rv = _isisc_vlan_up_to_sw(dev_id, reg); - SW_RTN_ON_ERROR(rv); - - _isisc_vlan_hw_to_sw(reg, p_vlan); - - if (0 == p_vlan->vid) - { - return SW_NO_MORE; - } - else - { - return SW_OK; - } -} - -static sw_error_t -_isisc_vlan_find(a_uint32_t dev_id, a_uint32_t vlan_id, fal_vlan_t * p_vlan) -{ - sw_error_t rv; - a_uint32_t reg[2] = { 0 }; - - HSL_DEV_ID_CHECK(dev_id); - - rv = _isisc_vlan_hwentry_get(dev_id, vlan_id, reg); - SW_RTN_ON_ERROR(rv); - - _isisc_vlan_hw_to_sw(reg, p_vlan); - return SW_OK; -} - -static sw_error_t -_isisc_vlan_delete(a_uint32_t dev_id, a_uint32_t vlan_id) -{ - sw_error_t rv; - a_uint32_t reg; - - HSL_DEV_ID_CHECK(dev_id); - - if (vlan_id > MAX_VLAN_ID) - { - return SW_OUT_OF_RANGE; - } - - reg = (a_int32_t) vlan_id; - HSL_REG_FIELD_SET(rv, dev_id, VLAN_TABLE_FUNC1, 0, VLAN_ID, - (a_uint8_t *) (®), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - - rv = _isisc_vlan_commit(dev_id, VLAN_PURGE_ENTRY); - return rv; -} - -static sw_error_t -_isisc_vlan_flush(a_uint32_t dev_id) -{ - sw_error_t rv; - - HSL_DEV_ID_CHECK(dev_id); - - rv = _isisc_vlan_commit(dev_id, VLAN_FLUSH); - return rv; -} - -static sw_error_t -_isisc_vlan_fid_set(a_uint32_t dev_id, a_uint32_t vlan_id, a_uint32_t fid) -{ - sw_error_t rv; - a_uint32_t reg[2] = { 0 }; - - HSL_DEV_ID_CHECK(dev_id); - - if ((MAX_VLAN_ID < fid) && (FAL_SVL_FID != fid)) - { - return SW_BAD_PARAM; - } - - if ((MAX_VLAN_ID >= fid) && (vlan_id != fid)) - { - return SW_BAD_PARAM; - } - - rv = _isisc_vlan_hwentry_get(dev_id, vlan_id, reg); - SW_RTN_ON_ERROR(rv); - - if (FAL_SVL_FID == fid) - { - SW_SET_REG_BY_FIELD(VLAN_TABLE_FUNC0, IVL_EN, 0, reg[0]); - } - else - { - SW_SET_REG_BY_FIELD(VLAN_TABLE_FUNC0, IVL_EN, 1, reg[0]); - } - - rv = _isisc_vlan_down_to_hw(dev_id, reg); - SW_RTN_ON_ERROR(rv); - - rv = _isisc_vlan_commit(dev_id, VLAN_LOAD_ENTRY); - if (SW_FULL == rv) - { - rv = SW_OK; - } - return rv; -} - -static sw_error_t -_isisc_vlan_fid_get(a_uint32_t dev_id, a_uint32_t vlan_id, a_uint32_t * fid) -{ - sw_error_t rv; - a_uint32_t data, reg[2] = { 0 }; - - HSL_DEV_ID_CHECK(dev_id); - - rv = _isisc_vlan_hwentry_get(dev_id, vlan_id, reg); - SW_RTN_ON_ERROR(rv); - - SW_GET_FIELD_BY_REG(VLAN_TABLE_FUNC0, IVL_EN, data, reg[0]); - if (data) - { - *fid = vlan_id; - } - else - { - *fid = FAL_SVL_FID; - } - return SW_OK; -} - -static sw_error_t -_isisc_vlan_member_update(a_uint32_t dev_id, a_uint32_t vlan_id, - fal_port_t port_id, a_uint32_t port_info) -{ - sw_error_t rv; - a_uint32_t data, reg[2] = { 0 }; - - HSL_DEV_ID_CHECK(dev_id); - - if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU)) - { - return SW_BAD_PARAM; - } - - rv = _isisc_vlan_hwentry_get(dev_id, vlan_id, reg); - SW_RTN_ON_ERROR(rv); - - SW_GET_FIELD_BY_REG(VLAN_TABLE_FUNC0, VID_MEM, data, reg[0]); - data &= (~(0x3 << (port_id << 1))); - data |= ((port_info & 0x3) << (port_id << 1)); - SW_SET_REG_BY_FIELD(VLAN_TABLE_FUNC0, VID_MEM, data, reg[0]); - - rv = _isisc_vlan_down_to_hw(dev_id, reg); - SW_RTN_ON_ERROR(rv); - - rv = _isisc_vlan_commit(dev_id, VLAN_LOAD_ENTRY); - if (SW_FULL == rv) - { - rv = SW_OK; - } - return rv; -} - -static sw_error_t -_isisc_vlan_member_add(a_uint32_t dev_id, a_uint32_t vlan_id, - fal_port_t port_id, fal_pt_1q_egmode_t port_info) -{ - sw_error_t rv; - a_uint32_t info = 0; - - if (FAL_EG_UNMODIFIED == port_info) - { - info = 0; - } - else if (FAL_EG_TAGGED == port_info) - { - info = 0x2; - } - else if (FAL_EG_UNTAGGED == port_info) - { - info = 0x1; - } - else - { - return SW_BAD_PARAM; - } - - rv = _isisc_vlan_member_update(dev_id, vlan_id, port_id, info); - return rv; -} - -static sw_error_t -_isisc_vlan_member_del(a_uint32_t dev_id, a_uint32_t vlan_id, fal_port_t port_id) -{ - sw_error_t rv; - a_uint32_t info = 0x3; - - rv = _isisc_vlan_member_update(dev_id, vlan_id, port_id, info); - return rv; -} - -static sw_error_t -_isisc_vlan_learning_state_set(a_uint32_t dev_id, a_uint32_t vlan_id, - a_bool_t enable) -{ - sw_error_t rv; - a_uint32_t reg[2] = { 0 }; - - HSL_DEV_ID_CHECK(dev_id); - - rv = _isisc_vlan_hwentry_get(dev_id, vlan_id, reg); - SW_RTN_ON_ERROR(rv); - - if (A_TRUE == enable) - { - SW_SET_REG_BY_FIELD(VLAN_TABLE_FUNC0, LEARN_DIS, 0, reg[0]); - } - else if (A_FALSE == enable) - { - SW_SET_REG_BY_FIELD(VLAN_TABLE_FUNC0, LEARN_DIS, 1, reg[0]); - } - else - { - return SW_BAD_PARAM; - } - - rv = _isisc_vlan_down_to_hw(dev_id, reg); - SW_RTN_ON_ERROR(rv); - - rv = _isisc_vlan_commit(dev_id, VLAN_LOAD_ENTRY); - if (SW_FULL == rv) - { - rv = SW_OK; - } - return rv; -} - -static sw_error_t -_isisc_vlan_learning_state_get(a_uint32_t dev_id, a_uint32_t vlan_id, - a_bool_t * enable) -{ - sw_error_t rv; - a_uint32_t data, reg[2] = { 0 }; - - HSL_DEV_ID_CHECK(dev_id); - - rv = _isisc_vlan_hwentry_get(dev_id, vlan_id, reg); - SW_RTN_ON_ERROR(rv); - - SW_GET_FIELD_BY_REG(VLAN_TABLE_FUNC0, LEARN_DIS, data, reg[0]); - if (data) - { - *enable = A_FALSE; - } - else - { - *enable = A_TRUE; - } - return SW_OK; -} - -/** - * @brief Append a vlan entry on paticular device. - * @param[in] dev_id device id - * @param[in] vlan_entry vlan entry - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -isisc_vlan_entry_append(a_uint32_t dev_id, const fal_vlan_t * vlan_entry) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _isisc_vlan_entry_append(dev_id, vlan_entry); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Creat a vlan entry through vlan id on a paticular device. - * @details Comments: - * After this operation the member ports of the created vlan entry are null. - * @param[in] dev_id device id - * @param[in] vlan_id vlan id - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -isisc_vlan_create(a_uint32_t dev_id, a_uint32_t vlan_id) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _isisc_vlan_create(dev_id, vlan_id); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Next a vlan entry through vlan id on a paticular device. - * @details Comments: - * If the value of vid is zero this operation will get the first entry. - * @param[in] dev_id device id - * @param[in] vlan_id vlan id - * @param[out] p_vlan vlan entry - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -isisc_vlan_next(a_uint32_t dev_id, a_uint32_t vlan_id, fal_vlan_t * p_vlan) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _isisc_vlan_next(dev_id, vlan_id, p_vlan); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Find a vlan entry through vlan id on paticular device. - * @param[in] dev_id device id - * @param[in] vlan_id vlan id - * @param[out] p_vlan vlan entry - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -isisc_vlan_find(a_uint32_t dev_id, a_uint32_t vlan_id, fal_vlan_t * p_vlan) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _isisc_vlan_find(dev_id, vlan_id, p_vlan); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Delete a vlan entry through vlan id on a paticular device. - * @param[in] dev_id device id - * @param[in] vlan_id vlan id - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -isisc_vlan_delete(a_uint32_t dev_id, a_uint32_t vlan_id) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _isisc_vlan_delete(dev_id, vlan_id); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Flush all vlan entries on a paticular device. - * @param[in] dev_id device id - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -isisc_vlan_flush(a_uint32_t dev_id) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _isisc_vlan_flush(dev_id); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Set FID of a paticular vlan entry on a paticular device. - * @param[in] dev_id device id - * @param[in] vlan_id vlan id - * @param[in] fid FDB id - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -isisc_vlan_fid_set(a_uint32_t dev_id, a_uint32_t vlan_id, a_uint32_t fid) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _isisc_vlan_fid_set(dev_id, vlan_id, fid); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Get FID of a paticular vlan entry on a paticular device. - * @param[in] dev_id device id - * @param[in] vlan_id vlan id - * @param[out] fid FDB id - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -isisc_vlan_fid_get(a_uint32_t dev_id, a_uint32_t vlan_id, a_uint32_t * fid) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _isisc_vlan_fid_get(dev_id, vlan_id, fid); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Add a port member to a paticular vlan entry on a paticular device. - * @param[in] dev_id device id - * @param[in] vlan_id vlan id - * @param[in] port_id port id - * @param[in] port_info port tag information - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -isisc_vlan_member_add(a_uint32_t dev_id, a_uint32_t vlan_id, - fal_port_t port_id, fal_pt_1q_egmode_t port_info) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _isisc_vlan_member_add(dev_id, vlan_id, port_id, port_info); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Del a port member from a paticular vlan entry on a paticular device. - * @param[in] dev_id device id - * @param[in] vlan_id vlan id - * @param[in] port_id port id - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -isisc_vlan_member_del(a_uint32_t dev_id, a_uint32_t vlan_id, fal_port_t port_id) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _isisc_vlan_member_del(dev_id, vlan_id, port_id); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Set FDB learning status of a paticular vlan entry on a paticular device. - * @param[in] dev_id device id - * @param[in] vlan_id vlan id - * @param[in] enable A_TRUE or A_FALSE - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -isisc_vlan_learning_state_set(a_uint32_t dev_id, a_uint32_t vlan_id, - a_bool_t enable) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _isisc_vlan_learning_state_set(dev_id, vlan_id, enable); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Get FDB learning status of a paticular vlan entry on a paticular device. - * @param[in] dev_id device id - * @param[in] vlan_id vlan id - * @param[out] enable A_TRUE or A_FALSE - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -isisc_vlan_learning_state_get(a_uint32_t dev_id, a_uint32_t vlan_id, - a_bool_t * enable) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _isisc_vlan_learning_state_get(dev_id, vlan_id, enable); - HSL_API_UNLOCK; - return rv; -} - -sw_error_t -isisc_vlan_init(a_uint32_t dev_id) -{ - hsl_api_t *p_api; - HSL_DEV_ID_CHECK(dev_id); - -#ifndef HSL_STANDALONG - - SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id)); - - p_api->vlan_entry_append = isisc_vlan_entry_append; - p_api->vlan_creat = isisc_vlan_create; - p_api->vlan_delete = isisc_vlan_delete; - p_api->vlan_next = isisc_vlan_next; - p_api->vlan_find = isisc_vlan_find; - p_api->vlan_flush = isisc_vlan_flush; - p_api->vlan_fid_set = isisc_vlan_fid_set; - p_api->vlan_fid_get = isisc_vlan_fid_get; - p_api->vlan_member_add = isisc_vlan_member_add; - p_api->vlan_member_del = isisc_vlan_member_del; - p_api->vlan_learning_state_set = isisc_vlan_learning_state_set; - p_api->vlan_learning_state_get = isisc_vlan_learning_state_get; - - -#endif - - return SW_OK; -} - -/** - * @} - */ - diff --git a/feeds/ipq807x/qca-ssdk/src/src/hsl/mp/Makefile b/feeds/ipq807x/qca-ssdk/src/src/hsl/mp/Makefile deleted file mode 100755 index cfa823424..000000000 --- a/feeds/ipq807x/qca-ssdk/src/src/hsl/mp/Makefile +++ /dev/null @@ -1,26 +0,0 @@ -LOC_DIR=src/hsl/mp -LIB=HSL - -include $(PRJ_PATH)/make/config.mk - -ifeq (TRUE, $(IN_MIB)) - SRC_LIST+=mp_mib.c -endif - -ifeq (TRUE, $(IN_PORTCONTROL)) - SRC_LIST+=mp_portctrl.c -endif - -ifeq (TRUE, $(IN_UNIPHY)) - SRC_LIST+=mp_uniphy.c -endif - -ifeq (, $(filter MP, $(SUPPORT_CHIP))) - SRC_LIST= -endif - -include $(PRJ_PATH)/make/components.mk -include $(PRJ_PATH)/make/defs.mk -include $(PRJ_PATH)/make/target.mk - -all: dep obj diff --git a/feeds/ipq807x/qca-ssdk/src/src/hsl/mp/mp_mib.c b/feeds/ipq807x/qca-ssdk/src/src/hsl/mp/mp_mib.c deleted file mode 100755 index e3188a15d..000000000 --- a/feeds/ipq807x/qca-ssdk/src/src/hsl/mp/mp_mib.c +++ /dev/null @@ -1,816 +0,0 @@ -/* - * Copyright (c) 2020, The Linux Foundation. All rights reserved. - * - * Permission to use, copy, modify, and/or distribute this software for any - * purpose with or without fee is hereby granted, provided that the above - * copyright notice and this permission notice appear in all copies. - * - * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES - * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR - * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES - * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN - * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF - * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. - */ - -#include "sw.h" -#include "hsl.h" -#include "scomphy_reg_access.h" -#include "mp_mib_reg.h" -#include "mp_mib.h" - -sw_error_t -mp_mmc_control_get( - a_uint32_t dev_id, - a_uint32_t index, - union mmc_control_u *value) -{ - if (index >= MMC_CONTROL_MAX_ENTRY) - return SW_OUT_OF_RANGE; - return scomphy_reg_get( - dev_id, - MMC_CONTROL_ADDRESS + \ - index * MMC_CONTROL_INC, - (a_uint8_t *)&value->val, 4); -} - -sw_error_t -mp_mmc_control_set( - a_uint32_t dev_id, - a_uint32_t index, - union mmc_control_u *value) -{ - if (index >= MMC_CONTROL_MAX_ENTRY) - return SW_OUT_OF_RANGE; - return scomphy_reg_set( - dev_id, - MMC_CONTROL_ADDRESS + \ - index * MMC_CONTROL_INC, - (a_uint8_t *)&value->val, 4); -} - -sw_error_t -mp_tx_octet_count_good_bad_get( - a_uint32_t dev_id, - a_uint32_t index, - union tx_octet_count_good_bad_u *value) -{ - if (index >= TX_OCTET_COUNT_GOOD_BAD_MAX_ENTRY) - return SW_OUT_OF_RANGE; - return scomphy_reg_get( - dev_id, - TX_OCTET_COUNT_GOOD_BAD_ADDRESS + \ - index * TX_OCTET_COUNT_GOOD_BAD_INC, - (a_uint8_t *)&value->val, 4); -} - -sw_error_t -mp_tx_frame_count_good_bad_get( - a_uint32_t dev_id, - a_uint32_t index, - union tx_frame_count_good_bad_u *value) -{ - if (index >= TX_FRAME_COUNT_GOOD_BAD_MAX_ENTRY) - return SW_OUT_OF_RANGE; - return scomphy_reg_get( - dev_id, - TX_FRAME_COUNT_GOOD_BAD_ADDRESS + \ - index * TX_FRAME_COUNT_GOOD_BAD_INC, - (a_uint8_t *)&value->val, 4); -} - -sw_error_t -mp_tx_broadcast_frames_good_get( - a_uint32_t dev_id, - a_uint32_t index, - union tx_broadcast_frames_good_u *value) -{ - if (index >= TX_BROADCAST_FRAMES_GOOD_MAX_ENTRY) - return SW_OUT_OF_RANGE; - return scomphy_reg_get( - dev_id, - TX_BROADCAST_FRAMES_GOOD_ADDRESS + \ - index * TX_BROADCAST_FRAMES_GOOD_INC, - (a_uint8_t *)&value->val, 4); -} - -sw_error_t -mp_tx_multicast_frames_good_get( - a_uint32_t dev_id, - a_uint32_t index, - union tx_multicast_frames_good_u *value) -{ - if (index >= TX_MULTICAST_FRAMES_GOOD_MAX_ENTRY) - return SW_OUT_OF_RANGE; - return scomphy_reg_get( - dev_id, - TX_MULTICAST_FRAMES_GOOD_ADDRESS + \ - index * TX_MULTICAST_FRAMES_GOOD_INC, - (a_uint8_t *)&value->val, 4); -} - -sw_error_t -mp_tx_64octets_frames_good_bad_get( - a_uint32_t dev_id, - a_uint32_t index, - union tx_64octets_frames_good_bad_u *value) -{ - if (index >= TX_64OCTETS_FRAMES_GOOD_BAD_MAX_ENTRY) - return SW_OUT_OF_RANGE; - return scomphy_reg_get( - dev_id, - TX_64OCTETS_FRAMES_GOOD_BAD_ADDRESS + \ - index * TX_64OCTETS_FRAMES_GOOD_BAD_INC, - (a_uint8_t *)&value->val, 4); -} - -sw_error_t -mp_tx_65to127octets_frames_good_bad_get( - a_uint32_t dev_id, - a_uint32_t index, - union tx_65to127octets_frames_good_bad_u *value) -{ - if (index >= TX_65TO127OCTETS_FRAMES_GOOD_BAD_MAX_ENTRY) - return SW_OUT_OF_RANGE; - return scomphy_reg_get( - dev_id, - TX_65TO127OCTETS_FRAMES_GOOD_BAD_ADDRESS + \ - index * TX_65TO127OCTETS_FRAMES_GOOD_BAD_INC, - (a_uint8_t *)&value->val, 4); -} - -sw_error_t -mp_tx_128to255octets_frames_good_bad_get( - a_uint32_t dev_id, - a_uint32_t index, - union tx_128to255octets_frames_good_bad_u *value) -{ - if (index >= TX_128TO255OCTETS_FRAMES_GOOD_BAD_MAX_ENTRY) - return SW_OUT_OF_RANGE; - return scomphy_reg_get( - dev_id, - TX_128TO255OCTETS_FRAMES_GOOD_BAD_ADDRESS + \ - index * TX_128TO255OCTETS_FRAMES_GOOD_BAD_INC, - (a_uint8_t *)&value->val, 4); -} - -sw_error_t -mp_tx_256to511octets_frames_good_bad_get( - a_uint32_t dev_id, - a_uint32_t index, - union tx_256to511octets_frames_good_bad_u *value) -{ - if (index >= TX_256TO511OCTETS_FRAMES_GOOD_BAD_MAX_ENTRY) - return SW_OUT_OF_RANGE; - return scomphy_reg_get( - dev_id, - TX_256TO511OCTETS_FRAMES_GOOD_BAD_ADDRESS + \ - index * TX_256TO511OCTETS_FRAMES_GOOD_BAD_INC, - (a_uint8_t *)&value->val, 4); -} - -sw_error_t -mp_tx_512to1023octets_frames_good_bad_get( - a_uint32_t dev_id, - a_uint32_t index, - union tx_512to1023octets_frames_good_bad_u *value) -{ - if (index >= TX_512TO1023OCTETS_FRAMES_GOOD_BAD_MAX_ENTRY) - return SW_OUT_OF_RANGE; - return scomphy_reg_get( - dev_id, - TX_512TO1023OCTETS_FRAMES_GOOD_BAD_ADDRESS + \ - index * TX_512TO1023OCTETS_FRAMES_GOOD_BAD_INC, - (a_uint8_t *)&value->val, 4); -} - -sw_error_t -mp_tx_1024tomaxoctets_frames_good_bad_get( - a_uint32_t dev_id, - a_uint32_t index, - union tx_1024tomaxoctets_frames_good_bad_u *value) -{ - if (index >= TX_1024TOMAXOCTETS_FRAMES_GOOD_BAD_MAX_ENTRY) - return SW_OUT_OF_RANGE; - return scomphy_reg_get( - dev_id, - TX_1024TOMAXOCTETS_FRAMES_GOOD_BAD_ADDRESS + \ - index * TX_1024TOMAXOCTETS_FRAMES_GOOD_BAD_INC, - (a_uint8_t *)&value->val, 4); -} - -sw_error_t -mp_tx_unicast_frames_good_bad_get( - a_uint32_t dev_id, - a_uint32_t index, - union tx_unicast_frames_good_bad_u *value) -{ - if (index >= TX_UNICAST_FRAMES_GOOD_BAD_MAX_ENTRY) - return SW_OUT_OF_RANGE; - return scomphy_reg_get( - dev_id, - TX_UNICAST_FRAMES_GOOD_BAD_ADDRESS + \ - index * TX_UNICAST_FRAMES_GOOD_BAD_INC, - (a_uint8_t *)&value->val, 4); -} - -sw_error_t -mp_tx_multicast_frames_good_bad_get( - a_uint32_t dev_id, - a_uint32_t index, - union tx_multicast_frames_good_bad_u *value) -{ - if (index >= TX_MULTICAST_FRAMES_GOOD_BAD_MAX_ENTRY) - return SW_OUT_OF_RANGE; - return scomphy_reg_get( - dev_id, - TX_MULTICAST_FRAMES_GOOD_BAD_ADDRESS + \ - index * TX_MULTICAST_FRAMES_GOOD_BAD_INC, - (a_uint8_t *)&value->val, 4); -} - -sw_error_t -mp_tx_broadcast_frames_good_bad_get( - a_uint32_t dev_id, - a_uint32_t index, - union tx_broadcast_frames_good_bad_u *value) -{ - if (index >= TX_BROADCAST_FRAMES_GOOD_BAD_MAX_ENTRY) - return SW_OUT_OF_RANGE; - return scomphy_reg_get( - dev_id, - TX_BROADCAST_FRAMES_GOOD_BAD_ADDRESS + \ - index * TX_BROADCAST_FRAMES_GOOD_BAD_INC, - (a_uint8_t *)&value->val, 4); -} - -sw_error_t -mp_tx_underflow_error_frames_get( - a_uint32_t dev_id, - a_uint32_t index, - union tx_underflow_error_frames_u *value) -{ - if (index >= TX_UNDERFERROR_FRAMES_MAX_ENTRY) - return SW_OUT_OF_RANGE; - return scomphy_reg_get( - dev_id, - TX_UNDERFLOW_ERROR_FRAMES_ADDRESS + \ - index * TX_UNDERFLOW_ERROR_FRAMES_INC, - (a_uint8_t *)&value->val, 4); -} - -sw_error_t -mp_tx_single_col_good_frames_get( - a_uint32_t dev_id, - a_uint32_t index, - union tx_single_collision_good_frames_u *value) -{ - if (index >= TX_SINGLE_COLLISION_GOOD_FRAMES_MAX_ENTRY) - return SW_OUT_OF_RANGE; - return scomphy_reg_get( - dev_id, - TX_SINGLE_COLLISION_GOOD_FRAMES_ADDRESS + \ - index * TX_SINGLE_COLLISION_GOOD_FRAMES_INC, - (a_uint8_t *)&value->val, 4); -} - -sw_error_t -mp_t_multi_col_good_frames_get( - a_uint32_t dev_id, - a_uint32_t index, - union tx_multiple_collision_good_frames_u *value) -{ - if (index >= TX_MULTIPLE_COLLISION_GOOD_FRAMES_MAX_ENTRY) - return SW_OUT_OF_RANGE; - return scomphy_reg_get( - dev_id, - TX_MULTIPLE_COLLISION_GOOD_FRAMES_ADDRESS + \ - index * TX_MULTIPLE_COLLISION_GOOD_FRAMES_INC, - (a_uint8_t *)&value->val, 4); -} - -sw_error_t -mp_tx_defer_frames_get( - a_uint32_t dev_id, - a_uint32_t index, - union tx_deferred_frames_u *value) -{ - if (index >= TX_DEFERRED_FRAMES_MAX_ENTRY) - return SW_OUT_OF_RANGE; - return scomphy_reg_get( - dev_id, - TX_DEFERRED_FRAMES_ADDRESS + \ - index * TX_DEFERRED_FRAMES_INC, - (a_uint8_t *)&value->val, 4); -} - -sw_error_t -mp_tx_late_col_frames_get( - a_uint32_t dev_id, - a_uint32_t index, - union tx_late_collision_frames_u *value) -{ - if (index >= TX_LATE_COLLISION_FRAMES_MAX_ENTRY) - return SW_OUT_OF_RANGE; - return scomphy_reg_get( - dev_id, - TX_LATE_COLLISION_FRAMES_ADDRESS + \ - index * TX_LATE_COLLISION_FRAMES_INC, - (a_uint8_t *)&value->val, 4); -} - -sw_error_t -mp_tx_excessive_col_frames_get( - a_uint32_t dev_id, - a_uint32_t index, - union tx_excessive_collision_frames_u *value) -{ - if (index >= TX_EXCESSIVE_COLLISION_FRAMES_MAX_ENTRY) - return SW_OUT_OF_RANGE; - return scomphy_reg_get( - dev_id, - TX_EXCESSIVE_COLLISION_FRAMES_ADDRESS + \ - index * TX_EXCESSIVE_COLLISION_FRAMES_INC, - (a_uint8_t *)&value->val, 4); -} - -sw_error_t -mp_tx_carrier_error_frames_get( - a_uint32_t dev_id, - a_uint32_t index, - union tx_carrier_error_frames_u *value) -{ - if (index >= TX_CARRIER_ERROR_FRAMES_MAX_ENTRY) - return SW_OUT_OF_RANGE; - return scomphy_reg_get( - dev_id, - TX_CARRIER_ERROR_FRAMES_ADDRESS + \ - index * TX_CARRIER_ERROR_FRAMES_INC, - (a_uint8_t *)&value->val, 4); -} - -sw_error_t -mp_tx_octet_count_good_get( - a_uint32_t dev_id, - a_uint32_t index, - union tx_octet_count_good_u *value) -{ - if (index >= TX_OCTET_COUNT_GOOD_MAX_ENTRY) - return SW_OUT_OF_RANGE; - return scomphy_reg_get( - dev_id, - TX_OCTET_COUNT_GOOD_ADDRESS + \ - index * TX_OCTET_COUNT_GOOD_INC, - (a_uint8_t *)&value->val, 4); -} - -sw_error_t -mp_tx_frame_count_good_get( - a_uint32_t dev_id, - a_uint32_t index, - union tx_frame_count_good_u *value) -{ - if (index >= TX_FRAME_COUNT_GOOD_MAX_ENTRY) - return SW_OUT_OF_RANGE; - return scomphy_reg_get( - dev_id, - TX_FRAME_COUNT_GOOD_ADDRESS + \ - index * TX_FRAME_COUNT_GOOD_INC, - (a_uint8_t *)&value->val, 4); -} - -sw_error_t -mp_tx_pause_frames_get( - a_uint32_t dev_id, - a_uint32_t index, - union tx_pause_frames_u *value) -{ - if (index >= TX_PAUSE_FRAMES_MAX_ENTRY) - return SW_OUT_OF_RANGE; - return scomphy_reg_get( - dev_id, - TX_PAUSE_FRAMES_ADDRESS + \ - index * TX_PAUSE_FRAMES_INC, - (a_uint8_t *)&value->val, 4); -} - -sw_error_t -mp_tx_vlan_frames_good_get( - a_uint32_t dev_id, - a_uint32_t index, - union tx_vlan_frames_good_u *value) -{ - if (index >= TX_VLAN_FRAMES_GOOD_MAX_ENTRY) - return SW_OUT_OF_RANGE; - return scomphy_reg_get( - dev_id, - TX_VLAN_FRAMES_GOOD_ADDRESS + \ - index * TX_VLAN_FRAMES_GOOD_INC, - (a_uint8_t *)&value->val, 4); -} - -sw_error_t -mp_tx_osize_frames_good_get( - a_uint32_t dev_id, - a_uint32_t index, - union tx_osize_frames_good_u *value) -{ - if (index >= TX_OSIZE_FRAMES_GOOD_MAX_ENTRY) - return SW_OUT_OF_RANGE; - return scomphy_reg_get( - dev_id, - TX_OSIZE_FRAMES_GOOD_ADDRESS + \ - index * TX_OSIZE_FRAMES_GOOD_INC, - (a_uint8_t *)&value->val, 4); -} - -sw_error_t -mp_rx_frame_count_good_bad_get( - a_uint32_t dev_id, - a_uint32_t index, - union rx_frame_count_good_bad_u *value) -{ - if (index >= RX_FRAME_COUNT_GOOD_BAD_MAX_ENTRY) - return SW_OUT_OF_RANGE; - return scomphy_reg_get( - dev_id, - RX_FRAME_COUNT_GOOD_BAD_ADDRESS + \ - index * RX_FRAME_COUNT_GOOD_BAD_INC, - (a_uint8_t *)&value->val, 4); -} - -sw_error_t -mp_rx_octet_count_good_bad_get( - a_uint32_t dev_id, - a_uint32_t index, - union rx_octet_count_good_bad_u *value) -{ - if (index >= RX_OCTET_COUNT_GOOD_BAD_MAX_ENTRY) - return SW_OUT_OF_RANGE; - return scomphy_reg_get( - dev_id, - RX_OCTET_COUNT_GOOD_BAD_ADDRESS + \ - index * RX_OCTET_COUNT_GOOD_BAD_INC, - (a_uint8_t *)&value->val, 4); -} - -sw_error_t -mp_rx_octet_count_good_get( - a_uint32_t dev_id, - a_uint32_t index, - union rx_octet_count_good_u *value) -{ - if (index >= RX_OCTET_COUNT_GOOD_MAX_ENTRY) - return SW_OUT_OF_RANGE; - return scomphy_reg_get( - dev_id, - RX_OCTET_COUNT_GOOD_ADDRESS + \ - index * RX_OCTET_COUNT_GOOD_INC, - (a_uint8_t *)&value->val, 4); -} - -sw_error_t -mp_rx_broadcast_frames_good_get( - a_uint32_t dev_id, - a_uint32_t index, - union rx_broadcast_frames_good_u *value) -{ - if (index >= RX_BROADCAST_FRAMES_GOOD_MAX_ENTRY) - return SW_OUT_OF_RANGE; - return scomphy_reg_get( - dev_id, - RX_BROADCAST_FRAMES_GOOD_ADDRESS + \ - index * RX_BROADCAST_FRAMES_GOOD_INC, - (a_uint8_t *)&value->val, 4); -} - -sw_error_t -mp_rx_multicast_frames_good_get( - a_uint32_t dev_id, - a_uint32_t index, - union rx_multicast_frames_good_u *value) -{ - if (index >= RX_MULTICAST_FRAMES_GOOD_MAX_ENTRY) - return SW_OUT_OF_RANGE; - return scomphy_reg_get( - dev_id, - RX_MULTICAST_FRAMES_GOOD_ADDRESS + \ - index * RX_MULTICAST_FRAMES_GOOD_INC, - (a_uint8_t *)&value->val, 4); -} - -sw_error_t -mp_rx_crc_error_frames_get( - a_uint32_t dev_id, - a_uint32_t index, - union rx_crc_error_frames_u *value) -{ - if (index >= RX_CRC_ERROR_FRAMES_MAX_ENTRY) - return SW_OUT_OF_RANGE; - return scomphy_reg_get( - dev_id, - RX_CRC_ERROR_FRAMES_ADDRESS + \ - index * RX_CRC_ERROR_FRAMES_INC, - (a_uint8_t *)&value->val, 4); -} - -sw_error_t -mp_rx_alignment_error_frames_get( - a_uint32_t dev_id, - a_uint32_t index, - union rx_crc_error_frames_u *value) -{ - if (index >= RX_ALIGNMENT_ERROR_FRAMES_MAX_ENTRY) - return SW_OUT_OF_RANGE; - return scomphy_reg_get( - dev_id, - RX_ALIGNMENT_ERROR_FRAMES_ADDRESS + \ - index * RX_ALIGNMENT_ERROR_FRAMES_INC, - (a_uint8_t *)&value->val, 4); -} - -sw_error_t -mp_rx_runt_error_frames_get( - a_uint32_t dev_id, - a_uint32_t index, - union rx_runt_error_frames_u *value) -{ - if (index >= RX_RUNT_ERROR_FRAMES_MAX_ENTRY) - return SW_OUT_OF_RANGE; - return scomphy_reg_get( - dev_id, - RX_RUNT_ERROR_FRAMES_ADDRESS + \ - index * RX_RUNT_ERROR_FRAMES_INC, - (a_uint8_t *)&value->val, 4); -} - -sw_error_t -mp_rx_jabber_error_frames_get( - a_uint32_t dev_id, - a_uint32_t index, - union rx_jabber_error_frames_u *value) -{ - if (index >= RX_JABBER_ERROR_FRAMES_MAX_ENTRY) - return SW_OUT_OF_RANGE; - return scomphy_reg_get( - dev_id, - RX_JABBER_ERROR_FRAMES_ADDRESS + \ - index * RX_JABBER_ERROR_FRAMES_INC, - (a_uint8_t *)&value->val, 4); -} - -sw_error_t -mp_rx_undersize_frames_good_get( - a_uint32_t dev_id, - a_uint32_t index, - union rx_undersize_frames_good_u *value) -{ - if (index >= RX_UNDERSIZE_FRAMES_GOOD_MAX_ENTRY) - return SW_OUT_OF_RANGE; - return scomphy_reg_get( - dev_id, - RX_UNDERSIZE_FRAMES_GOOD_ADDRESS + \ - index * RX_UNDERSIZE_FRAMES_GOOD_INC, - (a_uint8_t *)&value->val, 4); -} - -sw_error_t -mp_rx_oversize_frames_good_get( - a_uint32_t dev_id, - a_uint32_t index, - union rx_oversize_frames_good_u *value) -{ - if (index >= RX_OVERSIZE_FRAMES_GOOD_MAX_ENTRY) - return SW_OUT_OF_RANGE; - return scomphy_reg_get( - dev_id, - RX_OVERSIZE_FRAMES_GOOD_ADDRESS + \ - index * RX_OVERSIZE_FRAMES_GOOD_INC, - (a_uint8_t *)&value->val, 4); -} - -sw_error_t -mp_rx_64octets_frames_good_bad_get( - a_uint32_t dev_id, - a_uint32_t index, - union rx_64octets_frames_good_bad_u *value) -{ - if (index >= RX_64OCTETS_FRAMES_GOOD_BAD_MAX_ENTRY) - return SW_OUT_OF_RANGE; - return scomphy_reg_get( - dev_id, - RX_64OCTETS_FRAMES_GOOD_BAD_ADDRESS + \ - index * RX_64OCTETS_FRAMES_GOOD_BAD_INC, - (a_uint8_t *)&value->val, 4); -} - -sw_error_t -mp_rx_65to127octets_frames_good_bad_get( - a_uint32_t dev_id, - a_uint32_t index, - union rx_65to127octets_frames_good_bad_u *value) -{ - if (index >= RX_65TO127OCTETS_FRAMES_GOOD_BAD_MAX_ENTRY) - return SW_OUT_OF_RANGE; - return scomphy_reg_get( - dev_id, - RX_65TO127OCTETS_FRAMES_GOOD_BAD_ADDRESS + \ - index * RX_65TO127OCTETS_FRAMES_GOOD_BAD_INC, - (a_uint8_t *)&value->val, 4); -} - -sw_error_t -mp_rx_128to255octets_frames_good_bad_get( - a_uint32_t dev_id, - a_uint32_t index, - union rx_128to255octets_frames_good_bad_u *value) -{ - if (index >= RX_128TO255OCTETS_FRAMES_GOOD_BAD_MAX_ENTRY) - return SW_OUT_OF_RANGE; - return scomphy_reg_get( - dev_id, - RX_128TO255OCTETS_FRAMES_GOOD_BAD_ADDRESS + \ - index * RX_128TO255OCTETS_FRAMES_GOOD_BAD_INC, - (a_uint8_t *)&value->val, 4); -} - -sw_error_t -mp_rx_256to511octets_frames_good_bad_get( - a_uint32_t dev_id, - a_uint32_t index, - union rx_256to511octets_frames_good_bad_u *value) -{ - if (index >= RX_256TO511OCTETS_FRAMES_GOOD_BAD_MAX_ENTRY) - return SW_OUT_OF_RANGE; - return scomphy_reg_get( - dev_id, - RX_256TO511OCTETS_FRAMES_GOOD_BAD_ADDRESS + \ - index * RX_256TO511OCTETS_FRAMES_GOOD_BAD_INC, - (a_uint8_t *)&value->val, 4); -} - -sw_error_t -mp_rx_512to1023octets_frames_good_bad_get( - a_uint32_t dev_id, - a_uint32_t index, - union rx_512to1023octets_frames_good_bad_u *value) -{ - if (index >= RX_512TO1023OCTETS_FRAMES_GOOD_BAD_MAX_ENTRY) - return SW_OUT_OF_RANGE; - return scomphy_reg_get( - dev_id, - RX_512TO1023OCTETS_FRAMES_GOOD_BAD_ADDRESS + \ - index * RX_512TO1023OCTETS_FRAMES_GOOD_BAD_INC, - (a_uint8_t *)&value->val, 4); -} - -sw_error_t -mp_rx_1024tomaxoctets_frames_good_bad_get( - a_uint32_t dev_id, - a_uint32_t index, - union rx_1024tomaxoctets_frames_good_bad_u *value) -{ - if (index >= RX_1024TOMAXOCTETS_FRAMES_GOOD_BAD_MAX_ENTRY) - return SW_OUT_OF_RANGE; - return scomphy_reg_get( - dev_id, - RX_1024TOMAXOCTETS_FRAMES_GOOD_BAD_ADDRESS + \ - index * RX_1024TOMAXOCTETS_FRAMES_GOOD_BAD_INC, - (a_uint8_t *)&value->val, 4); -} - -sw_error_t -mp_rx_unicast_frames_good_get( - a_uint32_t dev_id, - a_uint32_t index, - union rx_unicast_frames_good_u *value) -{ - if (index >= RX_UNICAST_FRAMES_GOOD_MAX_ENTRY) - return SW_OUT_OF_RANGE; - return scomphy_reg_get( - dev_id, - RX_UNICAST_FRAMES_GOOD_ADDRESS + \ - index * RX_UNICAST_FRAMES_GOOD_INC, - (a_uint8_t *)&value->val, 4); -} - -sw_error_t -mp_rx_length_error_frames_get( - a_uint32_t dev_id, - a_uint32_t index, - union rx_length_error_frames_u *value) -{ - if (index >= RX_LENGTH_ERROR_FRAMES_MAX_ENTRY) - return SW_OUT_OF_RANGE; - return scomphy_reg_get( - dev_id, - RX_LENGTH_ERROR_FRAMES_ADDRESS + \ - index * RX_LENGTH_ERROR_FRAMES_INC, - (a_uint8_t *)&value->val, 4); -} - -sw_error_t -mp_rx_outofrange_frames_get( - a_uint32_t dev_id, - a_uint32_t index, - union rx_outofrange_frames_u *value) -{ - if (index >= RX_OUTOFRANGE_FRAMES_MAX_ENTRY) - return SW_OUT_OF_RANGE; - return scomphy_reg_get( - dev_id, - RX_OUTOFRANGE_FRAMES_ADDRESS + \ - index * RX_OUTOFRANGE_FRAMES_INC, - (a_uint8_t *)&value->val, 4); -} - -sw_error_t -mp_rx_pause_frames_get( - a_uint32_t dev_id, - a_uint32_t index, - union rx_pause_frames_u *value) -{ - if (index >= RX_PAUSE_FRAMES_MAX_ENTRY) - return SW_OUT_OF_RANGE; - return scomphy_reg_get( - dev_id, - RX_PAUSE_FRAMES_ADDRESS + \ - index * RX_PAUSE_FRAMES_INC, - (a_uint8_t *)&value->val, 4); -} - -sw_error_t -mp_rx_fifo_over_flow_frames_get( - a_uint32_t dev_id, - a_uint32_t index, - union rx_fifo_over_flow_frames_u *value) -{ - if (index >= RX_FIFO_OVER_FLOW_FRAMES_MAX_ENTRY) - return SW_OUT_OF_RANGE; - return scomphy_reg_get( - dev_id, - RX_FIFOOVERFW_FRAMES_ADDRESS + \ - index * RX_FIFOOVERFW_FRAMES_INC, - (a_uint8_t *)&value->val, 4); -} - -sw_error_t -mp_rx_vlan_frames_good_bad_get( - a_uint32_t dev_id, - a_uint32_t index, - union rx_vlan_frames_good_bad_u *value) -{ - if (index >= RX_VLAN_FRAMES_GOOD_BAD_MAX_ENTRY) - return SW_OUT_OF_RANGE; - return scomphy_reg_get( - dev_id, - RX_VLAN_FRAMES_GOOD_BAD_ADDRESS + \ - index * RX_VLAN_FRAMES_GOOD_BAD_INC, - (a_uint8_t *)&value->val, 4); -} - -sw_error_t -mp_rx_watchdog_error_frames_get( - a_uint32_t dev_id, - a_uint32_t index, - union rx_watchdog_error_frames_u *value) -{ - if (index >= RX_WATCHDOG_ERROR_FRAMES_MAX_ENTRY) - return SW_OUT_OF_RANGE; - return scomphy_reg_get( - dev_id, - RX_WATCHDOG_ERROR_FRAMES_ADDRESS + \ - index * RX_WATCHDOG_ERROR_FRAMES_INC, - (a_uint8_t *)&value->val, 4); -} - -sw_error_t -mp_rx_receive_error_frames_get( - a_uint32_t dev_id, - a_uint32_t index, - union rx_receive_error_frames_u *value) -{ - if (index >= RX_RECEIVE_ERROR_FRAMES_MAX_ENTRY) - return SW_OUT_OF_RANGE; - return scomphy_reg_get( - dev_id, - RX_RECEIVE_ERROR_FRAMES_ADDRESS + \ - index * RX_RECEIVE_ERROR_FRAMES_INC, - (a_uint8_t *)&value->val, 4); -} - -sw_error_t -mp_rx_control_frames_good_get( - a_uint32_t dev_id, - a_uint32_t index, - union rx_control_frames_good_u *value) -{ - if (index >= RX_CONTROL_FRAMES_GOOD_MAX_ENTRY) - return SW_OUT_OF_RANGE; - return scomphy_reg_get( - dev_id, - RX_CONTROL_FRAMES_GOOD_ADDRESS + \ - index * RX_CONTROL_FRAMES_GOOD_INC, - (a_uint8_t *)&value->val, 4); -} diff --git a/feeds/ipq807x/qca-ssdk/src/src/hsl/mp/mp_portctrl.c b/feeds/ipq807x/qca-ssdk/src/src/hsl/mp/mp_portctrl.c deleted file mode 100755 index e4931ce4a..000000000 --- a/feeds/ipq807x/qca-ssdk/src/src/hsl/mp/mp_portctrl.c +++ /dev/null @@ -1,231 +0,0 @@ -/* - * Copyright (c) 2020, The Linux Foundation. All rights reserved. - * - * Permission to use, copy, modify, and/or distribute this software for any - * purpose with or without fee is hereby granted, provided that the above - * copyright notice and this permission notice appear in all copies. - * - * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES - * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR - * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES - * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN - * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF - * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. - */ -#include "sw.h" -#include "hsl.h" -#include "scomphy_reg_access.h" -#include "mp_portctrl_reg.h" -#include "mp_portctrl.h" - -sw_error_t -mp_mac_configuration_get( - a_uint32_t dev_id, - a_uint32_t index, - union mac_configuration_u *value) -{ - if (index >= MAC_CONFIGURATION_MAX_ENTRY) - return SW_OUT_OF_RANGE; - return scomphy_reg_get( - dev_id, - MAC_CONFIGURATION_ADDRESS + \ - index * MAC_CONFIGURATION_INC, - (a_uint8_t *)&value->val, 4); -} - -sw_error_t -mp_mac_configuration_set( - a_uint32_t dev_id, - a_uint32_t index, - union mac_configuration_u *value) -{ - if (index >= MAC_CONFIGURATION_MAX_ENTRY) - return SW_OUT_OF_RANGE; - return scomphy_reg_set( - dev_id, - MAC_CONFIGURATION_ADDRESS + \ - index * MAC_CONFIGURATION_INC, - (a_uint8_t *)&value->val, 4); -} - -sw_error_t -mp_mac_frame_filter_get( - a_uint32_t dev_id, - a_uint32_t index, - union mac_frame_filter_u *value) -{ - if (index >= MAC_FRAME_FILTER_MAX_ENTRY) - return SW_OUT_OF_RANGE; - return scomphy_reg_get( - dev_id, - MAC_FRAME_FILTER_ADDRESS + \ - index * MAC_FRAME_FILTER_INC, - (a_uint8_t *)&value->val, 4); -} - -sw_error_t -mp_mac_frame_filter_set( - a_uint32_t dev_id, - a_uint32_t index, - union mac_frame_filter_u *value) -{ - if (index >= MAC_FRAME_FILTER_MAX_ENTRY) - return SW_OUT_OF_RANGE; - return scomphy_reg_set( - dev_id, - MAC_FRAME_FILTER_ADDRESS + \ - index * MAC_FRAME_FILTER_INC, - (a_uint8_t *)&value->val, 4); -} - -sw_error_t -mp_mac_flowctrl_get( - a_uint32_t dev_id, - a_uint32_t index, - union mac_flow_ctrl_u *value) -{ - if (index >= MAC_FLOW_CTRL_MAX_ENTRY) - return SW_OUT_OF_RANGE; - return scomphy_reg_get( - dev_id, - MAC_FLOW_CTRL_ADDRESS + \ - index * MAC_FLOW_CTRL_INC, - (a_uint8_t *)&value->val, 4); -} - -sw_error_t -mp_mac_flowctrl_set( - a_uint32_t dev_id, - a_uint32_t index, - union mac_flow_ctrl_u *value) -{ - if (index >= MAC_FLOW_CTRL_MAX_ENTRY) - return SW_OUT_OF_RANGE; - return scomphy_reg_set( - dev_id, - MAC_FLOW_CTRL_ADDRESS + \ - index * MAC_FLOW_CTRL_INC, - (a_uint8_t *)&value->val, 4); -} - -sw_error_t -mp_mac_lpi_ctrl_status_get( - a_uint32_t dev_id, - a_uint32_t index, - union mac_lpi_ctrl_status_u *value) -{ - if (index >= MAC_LPI_CTRL_STATUS_MAX_ENTRY) - return SW_OUT_OF_RANGE; - return scomphy_reg_get( - dev_id, - MAC_LPI_CTRL_STATUS_ADDRESS + \ - index * MAC_LPI_CTRL_STATUS_INC, - (a_uint8_t *)&value->val, 4); -} - -sw_error_t -mp_mac_lpi_ctrl_status_set( - a_uint32_t dev_id, - a_uint32_t index, - union mac_lpi_ctrl_status_u *value) -{ - if (index >= MAC_LPI_CTRL_STATUS_MAX_ENTRY) - return SW_OUT_OF_RANGE; - return scomphy_reg_set( - dev_id, - MAC_LPI_CTRL_STATUS_ADDRESS + \ - index * MAC_LPI_CTRL_STATUS_INC, - (a_uint8_t *)&value->val, 4); -} - -sw_error_t -mp_mac_lpi_timer_ctrl_get( - a_uint32_t dev_id, - a_uint32_t index, - union mac_lpi_timer_ctrl_u *value) -{ - if (index >= MAC_LPI_TIMER_CTRL_MAX_ENTRY) - return SW_OUT_OF_RANGE; - return scomphy_reg_get( - dev_id, - MAC_LPI_TIMER_CTRL_ADDRESS + \ - index * MAC_LPI_TIMER_CTRL_INC, - (a_uint8_t *)&value->val, 4); -} - -sw_error_t -mp_mac_lpi_timer_ctrl_set( - a_uint32_t dev_id, - a_uint32_t index, - union mac_lpi_timer_ctrl_u *value) -{ - if (index >= MAC_LPI_TIMER_CTRL_MAX_ENTRY) - return SW_OUT_OF_RANGE; - return scomphy_reg_set( - dev_id, - MAC_LPI_TIMER_CTRL_ADDRESS + \ - index * MAC_LPI_TIMER_CTRL_INC, - (a_uint8_t *)&value->val, 4); -} - -sw_error_t -mp_mac_max_frame_ctrl_get( - a_uint32_t dev_id, - a_uint32_t index, - union mac_max_frame_ctrl_u *value) -{ - if (index >= MAC_MAX_FRAME_CTRL_MAX_ENTRY) - return SW_OUT_OF_RANGE; - return scomphy_reg_get( - dev_id, - MAC_MAX_FRAME_CTRL_ADDRESS + \ - index * MAC_MAX_FRAME_CTRL_INC, - (a_uint8_t *)&value->val, 4); -} - -sw_error_t -mp_mac_max_frame_ctrl_set( - a_uint32_t dev_id, - a_uint32_t index, - union mac_max_frame_ctrl_u *value) -{ - if (index >= MAC_MAX_FRAME_CTRL_MAX_ENTRY) - return SW_OUT_OF_RANGE; - return scomphy_reg_set( - dev_id, - MAC_MAX_FRAME_CTRL_ADDRESS + \ - index * MAC_MAX_FRAME_CTRL_INC, - (a_uint8_t *)&value->val, 4); -} - -sw_error_t -mp_mac_operation_mode_ctrl_get( - a_uint32_t dev_id, - a_uint32_t index, - union mac_operation_mode_ctrl_u *value) -{ - if (index >= MAC_OPERATION_MODE_CTRL_MAX_ENTRY) - return SW_OUT_OF_RANGE; - return scomphy_reg_get( - dev_id, - MAC_OPERATION_MODE_CTRL_ADDRESS + \ - index * MAC_OPERATION_MODE_CTRL_INC, - (a_uint8_t *)&value->val, 4); -} - -sw_error_t -mp_mac_operation_mode_ctrl_set( - a_uint32_t dev_id, - a_uint32_t index, - union mac_operation_mode_ctrl_u *value) -{ - if (index >= MAC_OPERATION_MODE_CTRL_MAX_ENTRY) - return SW_OUT_OF_RANGE; - return scomphy_reg_set( - dev_id, - MAC_OPERATION_MODE_CTRL_ADDRESS + \ - index * MAC_OPERATION_MODE_CTRL_INC, - (a_uint8_t *)&value->val, 4); -} - diff --git a/feeds/ipq807x/qca-ssdk/src/src/hsl/mp/mp_uniphy.c b/feeds/ipq807x/qca-ssdk/src/src/hsl/mp/mp_uniphy.c deleted file mode 100755 index 5d49a7e97..000000000 --- a/feeds/ipq807x/qca-ssdk/src/src/hsl/mp/mp_uniphy.c +++ /dev/null @@ -1,55 +0,0 @@ -/* - * Copyright (c) 2020, The Linux Foundation. All rights reserved. - * - * Permission to use, copy, modify, and/or distribute this software for any - * purpose with or without fee is hereby granted, provided that the above - * copyright notice and this permission notice appear in all copies. - * - * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES - * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR - * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES - * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN - * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF - * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. - */ - -/** - * @defgroup - * @{ - */ - -#include "sw.h" -#include "hppe_reg_access.h" -#include "mp_uniphy_reg.h" -#include "mp_uniphy.h" - -sw_error_t -mp_uniphy_clock_output_control_get( - a_uint32_t dev_id, - a_uint32_t index, - union uniphy_clock_output_control_u *value) -{ - if (index >= UNIPHY_CLOCK_OUTPUT_CONTROL_MAX_ENTRY) - return SW_OUT_OF_RANGE; - return hppe_uniphy_reg_get( - dev_id, - NSS_UNIPHY_BASE_ADDR + UNIPHY_CLOCK_OUTPUT_CONTROL_ADDRESS, - index * UNIPHY_CLOCK_OUTPUT_CONTROL_INC, - &value->val); -} - -sw_error_t -mp_uniphy_clock_output_control_set( - a_uint32_t dev_id, - a_uint32_t index, - union uniphy_clock_output_control_u *value) -{ - if (index >= UNIPHY_CLOCK_OUTPUT_CONTROL_MAX_ENTRY) - return SW_OUT_OF_RANGE; - return hppe_uniphy_reg_set( - dev_id, - NSS_UNIPHY_BASE_ADDR + UNIPHY_CLOCK_OUTPUT_CONTROL_ADDRESS, - index * UNIPHY_CLOCK_OUTPUT_CONTROL_INC, - value->val); -} diff --git a/feeds/ipq807x/qca-ssdk/src/src/hsl/phy/Makefile b/feeds/ipq807x/qca-ssdk/src/src/hsl/phy/Makefile deleted file mode 100644 index 51d6d0b2e..000000000 --- a/feeds/ipq807x/qca-ssdk/src/src/hsl/phy/Makefile +++ /dev/null @@ -1,96 +0,0 @@ -LOC_DIR=src/hsl/phy -LIB=HSL - -include $(PRJ_PATH)/make/config.mk - -ifeq (ATHENA, $(CHIP_TYPE)) - SRC_LIST = f2_phy.c -endif - -ifeq (GARUDA, $(CHIP_TYPE)) - SRC_LIST = f1_phy.c -endif - -ifeq (SHIVA, $(CHIP_TYPE)) - SRC_LIST = f2_phy.c -endif - -ifeq (HORUS, $(CHIP_TYPE)) - SRC_LIST = f2_phy.c -endif - -ifeq (ISIS, $(CHIP_TYPE)) - SRC_LIST = f1_phy.c -endif - -ifeq (MP, $(CHIP_TYPE)) - SRC_LIST = mpge_phy.c -ifeq (TRUE, $(IN_LED)) - SRC_LIST += mpge_led.c -endif -endif - -ifneq (,$(filter ISISC, $(SUPPORT_CHIP))) - SRC_LIST += f1_phy.c -endif - -ifeq (TRUE, $(IN_MALIBU_PHY)) - SRC_LIST += malibu_phy.c -endif - -ifeq (ALL_CHIP, $(CHIP_TYPE)) - SRC_LIST = f1_phy.c f2_phy.c malibu_phy.c -ifneq (,$(filter MP, $(SUPPORT_CHIP))) - SRC_LIST += mpge_phy.c -ifeq (TRUE, $(IN_LED)) - SRC_LIST += mpge_led.c -endif -endif -endif - -ifeq (NONHK_CHIP, $(CHIP_TYPE)) - SRC_LIST = f1_phy.c f2_phy.c malibu_phy.c -endif - -ifeq (TRUE, $(IN_AQUANTIA_PHY)) - SRC_LIST += aquantia_phy.c -endif - -ifeq (TRUE, $(IN_QCA803X_PHY)) - SRC_LIST += qca803x_phy.c -endif - -ifeq (TRUE, $(IN_QCA808X_PHY)) - SRC_LIST += qca808x_phy.c - SRC_LIST += qca808x.c -ifeq (TRUE, $(IN_LED)) - SRC_LIST += qca808x_led.c -endif -ifeq (TRUE, $(IN_PTP)) - SRC_LIST += qca808x_ptp.c - SRC_LIST += qca808x_ptp_api.c -ifeq ($(CONFIG_PTP_1588_CLOCK), y) - SRC_LIST += qca808x_phc.c -endif -endif -endif - -ifeq (TRUE, $(IN_SFP_PHY)) - SRC_LIST += sfp_phy.c -endif - -SRC_LIST += hsl_phy.c - -ifeq (linux, $(OS)) - ifeq (KSLIB, $(MODULE_TYPE)) - ifneq (TRUE, $(KERNEL_MODE)) - SRC_LIST= - endif - endif -endif - -include $(PRJ_PATH)/make/components.mk -include $(PRJ_PATH)/make/defs.mk -include $(PRJ_PATH)/make/target.mk - -all: dep obj diff --git a/feeds/ipq807x/qca-ssdk/src/src/hsl/phy/aquantia_phy.c b/feeds/ipq807x/qca-ssdk/src/src/hsl/phy/aquantia_phy.c deleted file mode 100755 index 1a1f9ab64..000000000 --- a/feeds/ipq807x/qca-ssdk/src/src/hsl/phy/aquantia_phy.c +++ /dev/null @@ -1,2205 +0,0 @@ -/* - * Copyright (c) 2017-2018, The Linux Foundation. All rights reserved. - * Permission to use, copy, modify, and/or distribute this software for - * any purpose with or without fee is hereby granted, provided that the - * above copyright notice and this permission notice appear in all copies. - * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES - * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR - * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES - * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN - * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT - * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. - */ - -#include "sw.h" -#include "fal_port_ctrl.h" -#include "hsl_api.h" -#include "hsl.h" -#include "aquantia_phy.h" -#include "hsl_phy.h" -#include "ssdk_plat.h" - -/* #define aquantia_phy_reg_read _phy_reg_read */ -/* #define aquantia_phy_reg_write _phy_reg_write */ - -/****************************************************************************** -* -* aquantia_phy_mii_read - mii register read -* -* mii register read -*/ -static sw_error_t -aquantia_phy_reg_read(a_uint32_t dev_id, a_uint32_t phy_id, a_uint32_t reg_mmd, - a_uint32_t reg_id, a_uint16_t *phy_data) -{ - sw_error_t rv; - - reg_id = AQUANTIA_REG_ADDRESS(reg_mmd, reg_id); - HSL_PHY_GET(rv, dev_id, phy_id, reg_id, phy_data); - - return rv; -} - -/****************************************************************************** -* -* aquantia_phy_mii_write - mii register write -* -* mii register write -*/ -static sw_error_t -aquantia_phy_reg_write(a_uint32_t dev_id, a_uint32_t phy_id, a_uint32_t reg_mmd, - a_uint32_t reg_id, a_uint16_t reg_val) -{ - sw_error_t rv; - - reg_id = AQUANTIA_REG_ADDRESS(reg_mmd, reg_id); - HSL_PHY_SET(rv, dev_id, phy_id, reg_id, reg_val); - - return rv; -} -#ifndef IN_PORTCONTROL_MINI -/****************************************************************************** -* -* aquantia_phy_get_phy_id - get the phy id -* -*/ -sw_error_t -aquantia_phy_get_phy_id(a_uint32_t dev_id, a_uint32_t phy_id, - a_uint32_t *phy_data) -{ - sw_error_t rv; - a_uint16_t org_id, rev_id; - - rv = aquantia_phy_reg_read(dev_id, phy_id, AQUANTIA_MMD_PHY_XS_REGISTERS, - AQUANTIA_PHY_ID1, &org_id); - SW_RTN_ON_ERROR(rv); - rv = aquantia_phy_reg_read(dev_id, phy_id, AQUANTIA_MMD_PHY_XS_REGISTERS, - AQUANTIA_PHY_ID2, &rev_id); - SW_RTN_ON_ERROR(rv); - - *phy_data = ((org_id & 0xffff) << 16) | (rev_id & 0xffff); - - return rv; -} -#endif -sw_error_t -aquantia_phy_get_speed(a_uint32_t dev_id, a_uint32_t phy_id, - fal_port_speed_t * speed) -{ - a_uint16_t phy_data; - sw_error_t rv = SW_OK; - a_bool_t link_status; - - link_status = aquantia_phy_get_link_status(dev_id, phy_id); - if (link_status != A_TRUE) { - /*the speed register(0x4007c800) is not stable when aquantia phy is down, - but some APIs such as aquantia_phy_set_duplex() aquantia_phy_interface_set_mode() - need to get the speed, so set the speed default value as 100M when link down*/ - *speed = FAL_SPEED_100; - return SW_OK; - } - - rv = aquantia_phy_reg_read(dev_id, phy_id, AQUANTIA_MMD_AUTONEG, - AQUANTIA_REG_AUTONEG_VENDOR_STATUS, &phy_data); - SW_RTN_ON_ERROR(rv); - switch ((phy_data & AQUANTIA_STATUS_SPEED_MASK) >> 1) { - case AQUANTIA_STATUS_SPEED_100MBS: - *speed = FAL_SPEED_100; - break; - case AQUANTIA_STATUS_SPEED_1000MBS: - *speed = FAL_SPEED_1000; - break; - case AQUANTIA_STATUS_SPEED_10000MBS: - *speed = FAL_SPEED_10000; - break; - case AQUANTIA_STATUS_SPEED_2500MBS: - *speed = FAL_SPEED_2500; - break; - case AQUANTIA_STATUS_SPEED_5000MBS: - *speed = FAL_SPEED_5000; - break; - default: - return SW_READ_ERROR; - } - - return rv; -} - -/****************************************************************************** -* -* aquantia_phy_get_duplex - Determines the speed of phy ports associated with the -* specified device. -*/ -sw_error_t -aquantia_phy_get_duplex(a_uint32_t dev_id, a_uint32_t phy_id, - fal_port_duplex_t * duplex) -{ - a_uint16_t phy_data; - sw_error_t rv = SW_OK; - a_bool_t link_status; - - link_status = aquantia_phy_get_link_status(dev_id, phy_id); - if (link_status != A_TRUE) - { - return SW_OK; - } - - rv = aquantia_phy_reg_read(dev_id, phy_id, AQUANTIA_MMD_AUTONEG, - AQUANTIA_REG_AUTONEG_VENDOR_STATUS, &phy_data); - SW_RTN_ON_ERROR(rv); - //read duplex - if (phy_data & AQUANTIA_STATUS_FULL_DUPLEX) - { - *duplex = FAL_FULL_DUPLEX; - } - else - { - *duplex = FAL_HALF_DUPLEX; - } - - return rv; -} -#ifndef IN_PORTCONTROL_MINI -/****************************************************************************** -* -* aquantia_phy_reset - reset the phy -* -* reset the phy -*/ -sw_error_t aquantia_phy_reset(a_uint32_t dev_id, a_uint32_t phy_id) -{ - a_uint16_t phy_data; - sw_error_t rv = SW_OK; - - rv = aquantia_phy_reg_read(dev_id, phy_id, AQUANTIA_MMD_GLOBAL_REGISTERS, - AQUANTIA_GLOBAL_STANDARD_CONTROL1, &phy_data); - SW_RTN_ON_ERROR(rv); - rv = aquantia_phy_reg_write(dev_id, phy_id, AQUANTIA_MMD_GLOBAL_REGISTERS, - AQUANTIA_GLOBAL_STANDARD_CONTROL1, phy_data | AQUANTIA_CTRL_SOFTWARE_RESET); - aos_mdelay(100); - - return rv; -} - -/****************************************************************************** -* -* aquantia_phy_set_powersave - set power saving status -* -* set power saving status -*/ -sw_error_t -aquantia_phy_set_powersave(a_uint32_t dev_id, a_uint32_t phy_id, a_bool_t enable) -{ - a_uint16_t phy_data; - sw_error_t rv; - - rv = aquantia_phy_reg_read(dev_id, phy_id, AQUANTIA_MMD_GLOBAL_REGISTERS, - AQUANTIA_GLOBAL_RESERVED_PROVISIONING6, &phy_data); - SW_RTN_ON_ERROR(rv); - if (enable == A_TRUE) - { - phy_data |= AQUANTIA_POWER_SAVE; - } - else - { - phy_data &= ~AQUANTIA_POWER_SAVE; - } - rv = aquantia_phy_reg_write(dev_id, phy_id, AQUANTIA_MMD_GLOBAL_REGISTERS, - AQUANTIA_GLOBAL_RESERVED_PROVISIONING6,phy_data); - SW_RTN_ON_ERROR(rv); - rv = aquantia_phy_restart_autoneg(dev_id, phy_id); - - return rv; -} - -/****************************************************************************** -* -* aquantia_phy_get_powersave - get power saving status -* -* set power saving status -*/ -sw_error_t -aquantia_phy_get_powersave(a_uint32_t dev_id, a_uint32_t phy_id, - a_bool_t * enable) -{ - a_uint16_t phy_data; - sw_error_t rv = SW_OK; - - rv = aquantia_phy_reg_read(dev_id, phy_id, AQUANTIA_MMD_GLOBAL_REGISTERS, - AQUANTIA_GLOBAL_RESERVED_PROVISIONING6, &phy_data); - SW_RTN_ON_ERROR(rv); - if (phy_data& AQUANTIA_POWER_SAVE) - { - *enable = A_TRUE; - } - else - { - *enable = A_FALSE; - } - - return rv; -} - -/****************************************************************************** -* -* aquantia_phy_set_mdix - -* -* set phy mdix configuraiton -*/ -sw_error_t -aquantia_phy_set_mdix(a_uint32_t dev_id, a_uint32_t phy_id, - fal_port_mdix_mode_t mode) -{ - a_uint16_t phy_data; - sw_error_t rv = SW_OK; - - rv = aquantia_phy_reg_read(dev_id, phy_id, AQUANTIA_MMD_AUTONEG, - AQUANTIA_RESERVED_VENDOR_PROVISIONING1, &phy_data); - SW_RTN_ON_ERROR(rv); - phy_data &= ~(BITS(0,2)); - switch(mode) - { - case PHY_MDIX_AUTO: - phy_data |= AQUANTIA_PHY_MDIX_AUTO; - break; - case PHY_MDIX_MDIX: - phy_data |= AQUANTIA_PHY_MDIX; - break; - case PHY_MDIX_MDI: - phy_data |= AQUANTIA_PHY_MDI; - break; - default: - return SW_BAD_PARAM; - } - rv = aquantia_phy_reg_write(dev_id, phy_id, AQUANTIA_MMD_AUTONEG, - AQUANTIA_RESERVED_VENDOR_PROVISIONING1,phy_data); - SW_RTN_ON_ERROR(rv); - rv = aquantia_phy_restart_autoneg(dev_id, phy_id); - - return rv; -} - -/****************************************************************************** -* -* aquantia_phy_get_mdix -* -* get phy mdix configuration -*/ -sw_error_t -aquantia_phy_get_mdix(a_uint32_t dev_id, a_uint32_t phy_id, - fal_port_mdix_mode_t * mode) -{ - a_uint16_t phy_data; - sw_error_t rv = SW_OK; - - rv = aquantia_phy_reg_read(dev_id, phy_id, AQUANTIA_MMD_AUTONEG, - AQUANTIA_RESERVED_VENDOR_PROVISIONING1,&phy_data); - SW_RTN_ON_ERROR(rv); - phy_data &= BITS(0,2); - switch(phy_data) - { - case AQUANTIA_PHY_MDIX_AUTO: - *mode = PHY_MDIX_AUTO; - break; - case AQUANTIA_PHY_MDIX: - *mode = PHY_MDIX_MDIX; - break; - case AQUANTIA_PHY_MDI: - *mode = PHY_MDIX_MDI; - break; - default: - return SW_NOT_SUPPORTED; - } - - return rv; -} - -/****************************************************************************** -* -* aquantia_phy_get_mdix status -* -* get phy mdix status -*/ -sw_error_t -aquantia_phy_get_mdix_status(a_uint32_t dev_id, a_uint32_t phy_id, - fal_port_mdix_status_t * mode) -{ - a_uint16_t phy_data; - sw_error_t rv = SW_OK; - - rv = aquantia_phy_reg_read(dev_id, phy_id, AQUANTIA_MMD_AUTONEG, - AQUANTIA_RESERVED_VENDOR_STATUS1, &phy_data); - SW_RTN_ON_ERROR(rv); - *mode = (phy_data & AQUANTIA_PHY_MDIX_STATUS) ? PHY_MDIX_STATUS_MDIX : - PHY_MDIX_STATUS_MDI; - - return rv; -} - -/****************************************************************************** -* -* aquantia_phy_set_local_loopback -* -* set phy local loopback -*/ -sw_error_t -aquantia_phy_set_local_loopback(a_uint32_t dev_id, a_uint32_t phy_id, - a_bool_t enable) -{ - a_uint16_t phy_data; - fal_port_speed_t old_speed; - sw_error_t rv = SW_OK; - - rv = aquantia_phy_reg_read(dev_id, phy_id, AQUANTIA_MMD_PHY_XS_REGISTERS, - AQUANTIA_PHY_XS_TRANAMIT_RESERVED_VENDOR_PROVISION5, &phy_data); - SW_RTN_ON_ERROR(rv); - if (enable == A_TRUE) - { - phy_data |= AQUANTIA_INTERNAL_LOOPBACK; - rv = aquantia_phy_get_speed(dev_id, phy_id, &old_speed); - SW_RTN_ON_ERROR(rv); - switch(old_speed) - { - case FAL_SPEED_100: - phy_data |= AQUANTIA_100M_LOOPBACK; - break; - case FAL_SPEED_1000: - phy_data |= AQUANTIA_1000M_LOOPBACK; - break; - case FAL_SPEED_10000: - phy_data |= AQUANTIA_10000M_LOOPBACK; - break; - case FAL_SPEED_2500: - phy_data |= AQUANTIA_2500M_LOOPBACK; - break; - case FAL_SPEED_5000: - phy_data |= AQUANTIA_5000M_LOOPBACK; - break; - default: - return SW_FAIL; - } - } - else - { - phy_data &= ~(AQUANTIA_INTERNAL_LOOPBACK | AQUANTIA_ALL_SPEED_LOOPBACK); - } - rv = aquantia_phy_reg_write(dev_id, phy_id, AQUANTIA_MMD_PHY_XS_REGISTERS, - AQUANTIA_PHY_XS_TRANAMIT_RESERVED_VENDOR_PROVISION5,phy_data); - - return rv; -} - -/****************************************************************************** -* -* aquantia_phy_get_local_loopback -* -* get phy local loopback -*/ -sw_error_t -aquantia_phy_get_local_loopback(a_uint32_t dev_id, a_uint32_t phy_id, - a_bool_t * enable) -{ - a_uint16_t phy_data; - sw_error_t rv = SW_OK; - - rv = aquantia_phy_reg_read(dev_id, phy_id, AQUANTIA_MMD_PHY_XS_REGISTERS, - AQUANTIA_PHY_XS_TRANAMIT_RESERVED_VENDOR_PROVISION5, &phy_data); - SW_RTN_ON_ERROR(rv); - if (phy_data & AQUANTIA_INTERNAL_LOOPBACK) - { - *enable = A_TRUE; - } - else - { - *enable = A_FALSE; - } - - return rv; -} - -sw_error_t -aquantia_phy_set_remote_loopback(a_uint32_t dev_id, a_uint32_t phy_id, - a_bool_t enable) -{ - a_uint16_t phy_data; - fal_port_speed_t speed; - sw_error_t rv = SW_OK; - - rv = aquantia_phy_reg_read(dev_id, phy_id, AQUANTIA_MMD_PHY_XS_REGISTERS, - AQUANTIA_PHY_XS_TRANAMIT_RESERVED_VENDOR_PROVISION5, &phy_data); - SW_RTN_ON_ERROR(rv); - - if (enable == A_TRUE) - { - rv = aquantia_phy_get_speed(dev_id, phy_id, &speed); - SW_RTN_ON_ERROR(rv); - switch(speed) - { - case FAL_SPEED_100: - phy_data |= AQUANTIA_100M_LOOPBACK; - break; - case FAL_SPEED_1000: - phy_data |= AQUANTIA_1000M_LOOPBACK; - break; - case FAL_SPEED_2500: - phy_data |= AQUANTIA_2500M_LOOPBACK; - break; - case FAL_SPEED_5000: - phy_data |= AQUANTIA_5000M_LOOPBACK; - break; - case FAL_SPEED_10000: - phy_data |= AQUANTIA_10000M_LOOPBACK; - break; - default: - break; - } - phy_data |= AQUANTIA_PHY_REMOTE_LOOPBACK; - } - else - { - phy_data &= ~(AQUANTIA_PHY_REMOTE_LOOPBACK |AQUANTIA_ALL_SPEED_LOOPBACK); - } - rv = aquantia_phy_reg_write(dev_id, phy_id, AQUANTIA_MMD_PHY_XS_REGISTERS, - AQUANTIA_PHY_XS_TRANAMIT_RESERVED_VENDOR_PROVISION5, phy_data); - - return rv; -} - -/****************************************************************************** -* -* aquantia_phy_get_remote_loopback -* -* get phy remote loopback -*/ -sw_error_t -aquantia_phy_get_remote_loopback(a_uint32_t dev_id, a_uint32_t phy_id, - a_bool_t * enable) -{ - a_uint16_t phy_data; - sw_error_t rv = SW_OK; - - rv = aquantia_phy_reg_read(dev_id, phy_id, AQUANTIA_MMD_PHY_XS_REGISTERS, - AQUANTIA_PHY_XS_TRANAMIT_RESERVED_VENDOR_PROVISION5, &phy_data); - SW_RTN_ON_ERROR(rv); - if (phy_data & AQUANTIA_PHY_REMOTE_LOOPBACK) - { - *enable = A_TRUE; - } - else - { - *enable = A_FALSE; - } - - return rv; -} - -/****************************************************************************** -* -* aquantia_phy_cdt - cable diagnostic test -* -* cable diagnostic test -*/ -static inline fal_cable_status_t _phy_cdt_status_mapping(a_uint32_t pair_type, a_uint16_t status) -{ - fal_cable_status_t status_mapping = FAL_CABLE_STATUS_INVALID; - - switch(status) - { - case 0: - status_mapping = FAL_CABLE_STATUS_NORMAL; - break; - case 1: - if(pair_type == CABLE_PAIR_B) - status_mapping = FAL_CABLE_STATUS_CROSSOVERA; - else if(pair_type == CABLE_PAIR_C) - status_mapping = FAL_CABLE_STATUS_CROSSOVERB; - else if(pair_type == CABLE_PAIR_D) - status_mapping = FAL_CABLE_STATUS_CROSSOVERC; - else - status_mapping = FAL_CABLE_STATUS_INVALID; - break; - case 2: - if(pair_type == CABLE_PAIR_C) - status_mapping = FAL_CABLE_STATUS_CROSSOVERA; - else if(pair_type == CABLE_PAIR_D) - status_mapping = FAL_CABLE_STATUS_CROSSOVERB; - else - status_mapping = FAL_CABLE_STATUS_INVALID; - break; - case 3: - if(pair_type == CABLE_PAIR_D) - status_mapping = FAL_CABLE_STATUS_CROSSOVERA; - else - status_mapping = FAL_CABLE_STATUS_INVALID; - break; - case 4: - status_mapping = FAL_CABLE_STATUS_SHORT; - break; - case 5: - status_mapping = FAL_CABLE_STATUS_LOW_MISMATCH; - break; - case 6: - status_mapping = FAL_CABLE_STATUS_HIGH_MISMATCH; - break; - case 7: - status_mapping = FAL_CABLE_STATUS_OPENED; - break; - default: - status_mapping = FAL_CABLE_STATUS_INVALID; - break; - } - - return status_mapping; -} - -sw_error_t -aquantia_phy_cdt_get(a_uint32_t dev_id, a_uint32_t phy_id, - fal_port_cdt_t * port_cdt) -{ - a_uint16_t status = 0; - sw_error_t rv = SW_OK; - a_uint16_t phy_data; - - if ((!port_cdt) || (phy_id > 7)) { - return SW_FAIL; - } - /* Get cable status */ - rv = aquantia_phy_reg_read(dev_id, phy_id, AQUANTIA_MMD_GLOBAL_REGISTERS, - AQUANTIA_CABLE_DIAGNOSTIC_STATUS1, &status); - SW_RTN_ON_ERROR(rv); - port_cdt->pair_a_status = (status & AQUANTIA_CABLE_DIAGNOSTIC_STATUS_PAIRA) >> 12 - & BITS(0, 3); - port_cdt->pair_b_status = (status & AQUANTIA_CABLE_DIAGNOSTIC_STATUS_PAIRB) >> 8 - & BITS(0, 3); - port_cdt->pair_c_status = (status & AQUANTIA_CABLE_DIAGNOSTIC_STATUS_PAIRC) >> 4 - & BITS(0, 3); - port_cdt->pair_d_status = (status & AQUANTIA_CABLE_DIAGNOSTIC_STATUS_PAIRD) - & BITS(0, 3); - SSDK_DEBUG("status:%x, pair_a_status:%x,pair_b_status:%x,pair_c_status:%x, pair_d_status:%x\n", - status, port_cdt->pair_a_status,port_cdt->pair_b_status, - port_cdt->pair_c_status, port_cdt->pair_d_status); - /* Get Cable Length value */ - rv = aquantia_phy_reg_read(dev_id, phy_id, AQUANTIA_MMD_GLOBAL_REGISTERS, - AQUANTIA_CABLE_DIAGNOSTIC_STATUS2, &phy_data); - SW_RTN_ON_ERROR(rv); - port_cdt->pair_a_len = phy_data >> 8 & BITS(0, 8); - - rv = aquantia_phy_reg_read(dev_id, phy_id, AQUANTIA_MMD_GLOBAL_REGISTERS, - AQUANTIA_CABLE_DIAGNOSTIC_STATUS4, &phy_data); - SW_RTN_ON_ERROR(rv); - port_cdt->pair_b_len = phy_data >> 8 & BITS(0, 8); - - rv = aquantia_phy_reg_read(dev_id, phy_id, AQUANTIA_MMD_GLOBAL_REGISTERS, - AQUANTIA_CABLE_DIAGNOSTIC_STATUS6, &phy_data); - SW_RTN_ON_ERROR(rv); - port_cdt->pair_c_len = phy_data >> 8 & BITS(0, 8); - - rv = aquantia_phy_reg_read(dev_id, phy_id, AQUANTIA_MMD_GLOBAL_REGISTERS, - AQUANTIA_CABLE_DIAGNOSTIC_STATUS8, &phy_data); - SW_RTN_ON_ERROR(rv); - port_cdt->pair_d_len = phy_data >> 8 & BITS(0, 8); - - return rv; -} - -sw_error_t aquatia_phy_cdt_start(a_uint32_t dev_id, a_uint32_t phy_id) -{ - a_uint16_t status = 0, phy_data = 0; - a_uint32_t aq_phy_id; - a_uint16_t ii = 300; - sw_error_t rv = SW_OK; - - /*select mode0 if aq107, and select mode2 if aq109*/ - rv = aquantia_phy_get_phy_id(dev_id, phy_id, &aq_phy_id); - SW_RTN_ON_ERROR(rv); - rv = aquantia_phy_reg_read(dev_id, phy_id, AQUANTIA_MMD_GLOBAL_REGISTERS, - AQUANTIA_GLOBAL_CDT_CONTROL, &phy_data); - SW_RTN_ON_ERROR(rv); - if(aq_phy_id == AQUANTIA_PHY_109) - { - phy_data |= AQUANTIA_PHY_CDT_MODE2; - } - else - { - phy_data |= AQUANTIA_PHY_CDT_MODE0; - } - - phy_data |= AQUANTIA_NORMAL_CABLE_DIAGNOSTICS; - rv = aquantia_phy_reg_write(dev_id, phy_id, AQUANTIA_MMD_GLOBAL_REGISTERS, - AQUANTIA_GLOBAL_CDT_CONTROL, phy_data); - SW_RTN_ON_ERROR(rv); - do { - aos_mdelay(30); - rv = aquantia_phy_reg_read(dev_id, phy_id, AQUANTIA_MMD_GLOBAL_REGISTERS, - AQUANTIA_GLOBAL_GENERAL_STATUS, &status); - SW_RTN_ON_ERROR(rv); - } - while ((status & AQUANTIA_CABLE_DIAGNOSTICS_STATUS) && (--ii)); - - return rv; -} - -sw_error_t -aquantia_phy_cdt(a_uint32_t dev_id, a_uint32_t phy_id, a_uint32_t mdi_pair, - fal_cable_status_t * cable_status, a_uint32_t * cable_len) -{ - fal_port_cdt_t aquantia_port_cdt; - sw_error_t rv = SW_OK; - - if ((mdi_pair >= 4) || (phy_id > 7)) { - return SW_BAD_PARAM; - } - rv = aquatia_phy_cdt_start(dev_id, phy_id); - SW_RTN_ON_ERROR(rv); - rv = aquantia_phy_cdt_get(dev_id, phy_id, &aquantia_port_cdt); - SW_RTN_ON_ERROR(rv); - switch (mdi_pair) - { - case 0: - *cable_status = - _phy_cdt_status_mapping(CABLE_PAIR_A, aquantia_port_cdt.pair_a_status); - /* Get Cable Length value */ - *cable_len = aquantia_port_cdt.pair_a_len; - break; - case 1: - *cable_status = - _phy_cdt_status_mapping(CABLE_PAIR_B, aquantia_port_cdt.pair_b_status); - /* Get Cable Length value */ - *cable_len = aquantia_port_cdt.pair_b_len; - break; - case 2: - *cable_status = - _phy_cdt_status_mapping(CABLE_PAIR_C, aquantia_port_cdt.pair_c_status); - /* Get Cable Length value */ - *cable_len = aquantia_port_cdt.pair_c_len; - break; - case 3: - *cable_status = - _phy_cdt_status_mapping(CABLE_PAIR_D, aquantia_port_cdt.pair_d_status); - /* Get Cable Length value */ - *cable_len = aquantia_port_cdt.pair_d_len; - break; - default: - break; - } - - return rv; -} -#endif -/****************************************************************************** -* -* AQUANTIA_autoneg_done -* -* AQUANTIA_autoneg_done -*/ -a_bool_t aquantia_autoneg_done(a_uint32_t dev_id, a_uint32_t phy_id) -{ - a_uint16_t phy_data; - a_uint16_t ii = 200; - sw_error_t rv = SW_OK; - - do { - rv = aquantia_phy_reg_read(dev_id, phy_id, AQUANTIA_MMD_AUTONEG, - AQUANTIA_AUTONEG_STANDARD_STATUS1, &phy_data); - SW_RTN_ON_ERROR(rv); - aos_mdelay(10); - } - while ((!AQUANTIA_AUTONEG_DONE(phy_data)) && --ii); - - if (ii == 0) - return A_FALSE; - - return A_TRUE; -} -#ifndef IN_PORTCONTROL_MINI -/****************************************************************************** -* -* aquantia_phy_get_ability - get the phy ability -* -* -*/ -sw_error_t -aquantia_phy_get_partner_ability(a_uint32_t dev_id, a_uint32_t phy_id, - a_uint32_t * ability) -{ - a_uint16_t phy_data; - sw_error_t rv = SW_OK; - - *ability = 0; - rv = aquantia_phy_reg_read(dev_id, phy_id, AQUANTIA_MMD_AUTONEG, - AQUANTIA_AUTONEG_LINK_PARTNER_ABILITY, &phy_data); - SW_RTN_ON_ERROR(rv); - if (phy_data & AQUANTIA_LINK_10BASETX_HALF_DUPLEX) - { - *ability |= FAL_PHY_PART_10T_HD; - } - if (phy_data & AQUANTIA_LINK_10BASETX_FULL_DUPLEX) - { - *ability |= FAL_PHY_PART_10T_FD; - } - if (phy_data & AQUANTIA_LINK_100BASETX_HALF_DUPLEX) - { - *ability |= FAL_PHY_PART_100TX_HD; - } - if (phy_data & AQUANTIA_LINK_100BASETX_FULL_DUPLEX) - { - *ability |= FAL_PHY_PART_100TX_FD; - } - - rv = aquantia_phy_reg_read(dev_id, phy_id, AQUANTIA_MMD_AUTONEG, - AQUANTIA_AUTONEG_LINK_PARTNER_5G_ABILITY, &phy_data); - SW_RTN_ON_ERROR(rv); - if (phy_data & AQUANTIA_LINK_1000BASETX_FULL_DUPLEX) - { - *ability |= FAL_PHY_PART_1000T_FD; - } - if (phy_data & AQUANTIA_LINK_5000BASETX_FULL_DUPLEX) - { - *ability |= FAL_PHY_PART_5000T_FD; - } - if (phy_data & AQUANTIA_LINK_2500BASETX_FULL_DUPLEX) - { - *ability |= FAL_PHY_PART_2500T_FD; - } - - rv = aquantia_phy_reg_read(dev_id, phy_id, AQUANTIA_MMD_AUTONEG, - AQUANTIA_AUTONEG_LINK_PARTNER_10G_ABILITY, &phy_data); - if (phy_data & AQUANTIA_LINK_10000BASETX_FULL_DUPLEX) - { - *ability |= FAL_PHY_PART_10000T_FD; - } - - return rv; -} -#endif -/****************************************************************************** -* -* aquantia_phy_status - test to see if the specified phy link is alive -* -* RETURNS: -* A_TRUE --> link is alive -* A_FALSE --> link is down -*/ -a_bool_t aquantia_phy_get_link_status(a_uint32_t dev_id, a_uint32_t phy_id) -{ - a_uint16_t phy_data; - sw_error_t rv = SW_OK; - - /*in order to get the link status of real time, need to read the link status two times */ - rv = aquantia_phy_reg_read(dev_id, phy_id, AQUANTIA_MMD_AUTONEG, - AQUANTIA_AUTONEG_STANDARD_STATUS1, &phy_data); - if(rv != SW_OK) - { - return A_FALSE; - } - rv = aquantia_phy_reg_read(dev_id, phy_id, AQUANTIA_MMD_AUTONEG, - AQUANTIA_AUTONEG_STANDARD_STATUS1, &phy_data); - if(rv != SW_OK) - { - return A_FALSE; - } - if (phy_data & AQUANTIA_STATUS_LINK) - { - return A_TRUE; - } - - return A_FALSE; -} - -/****************************************************************************** -* -* AQUANTIA_set_autoneg_adv - set the phy autoneg Advertisement -* -*/ -sw_error_t -aquantia_phy_set_autoneg_adv(a_uint32_t dev_id, a_uint32_t phy_id, - a_uint32_t autoneg) -{ - a_uint16_t phy_data = 0, phy_data1 = 0 ; - sw_error_t rv = SW_OK; - - if ((autoneg & FAL_PHY_ADV_10T_FD) ||(autoneg & FAL_PHY_ADV_10T_HD)|| - (autoneg & FAL_PHY_ADV_100TX_HD)) - { - return SW_NOT_SUPPORTED; - } - - rv = aquantia_phy_reg_read(dev_id, phy_id, AQUANTIA_MMD_AUTONEG, - AQUANTIA_AUTONEG_ADVERTISEMENT_REGISTER, &phy_data); - SW_RTN_ON_ERROR(rv); - phy_data &= ~AQUANTIA_ADVERTISE_MEGA_ALL; - phy_data &= - ~(AQUANTIA_ADVERTISE_PAUSE | AQUANTIA_ADVERTISE_ASYM_PAUSE); - if (autoneg & FAL_PHY_ADV_100TX_FD) - { - phy_data |= AQUANTIA_ADVERTISE_100FULL; - } - if (autoneg & FAL_PHY_ADV_PAUSE) - { - phy_data |= AQUANTIA_ADVERTISE_PAUSE; - } - if (autoneg & FAL_PHY_ADV_ASY_PAUSE) - { - phy_data |= AQUANTIA_ADVERTISE_ASYM_PAUSE; - } - rv = aquantia_phy_reg_write(dev_id, phy_id, AQUANTIA_MMD_AUTONEG, - AQUANTIA_AUTONEG_ADVERTISEMENT_REGISTER, phy_data); - SW_RTN_ON_ERROR(rv); - - rv = aquantia_phy_reg_read(dev_id, phy_id, AQUANTIA_MMD_AUTONEG, - AQUANTIA_AUTONEG_VENDOR_PROVISION1, &phy_data); - SW_RTN_ON_ERROR(rv); - phy_data &= ~AQUANTIA_ADVERTISE_GIGA_ALL; - - rv = aquantia_phy_reg_read(dev_id, phy_id, AQUANTIA_MMD_AUTONEG, - AQUANTIA_AUTONEG_10GBASE_T_CONTROL_REGISTER, &phy_data1); - SW_RTN_ON_ERROR(rv); - phy_data1 &= ~AQUANTIA_ADVERTISE_GIGA_PLUS_ALL; - if (autoneg & FAL_PHY_ADV_1000T_FD) - { - phy_data |= AQUANTIA_ADVERTISE_1000FULL; - } - if (autoneg & FAL_PHY_ADV_2500T_FD) - { - phy_data |= AQUANTIA_ADVERTISE_2500FULL; - phy_data1 |= AQUANTIA_ADVERTISE_8023BZ_2500FULL; - } - if (autoneg & FAL_PHY_ADV_5000T_FD) - { - phy_data |= AQUANTIA_ADVERTISE_5000FULL; - phy_data1 |= AQUANTIA_ADVERTISE_8023BZ_5000FULL; - } - rv = aquantia_phy_reg_write(dev_id, phy_id, AQUANTIA_MMD_AUTONEG, - AQUANTIA_AUTONEG_VENDOR_PROVISION1, phy_data); - SW_RTN_ON_ERROR(rv); - - if (autoneg & FAL_PHY_ADV_10000T_FD) - phy_data1 |= AQUANTIA_ADVERTISE_10000FULL; - rv = aquantia_phy_reg_write(dev_id, phy_id, AQUANTIA_MMD_AUTONEG, - AQUANTIA_AUTONEG_10GBASE_T_CONTROL_REGISTER,phy_data1); - - return rv; -} - -/****************************************************************************** -* -* AQUANTIA_get_autoneg_adv - get the phy autoneg Advertisement -* -*/ -sw_error_t -aquantia_phy_get_autoneg_adv(a_uint32_t dev_id, a_uint32_t phy_id, - a_uint32_t * autoneg) -{ - a_uint16_t phy_data = 0, phy_data1 = 0; - sw_error_t rv = SW_OK; - - *autoneg = 0; - rv = aquantia_phy_reg_read(dev_id, phy_id, AQUANTIA_MMD_AUTONEG, - AQUANTIA_AUTONEG_ADVERTISEMENT_REGISTER, &phy_data); - SW_RTN_ON_ERROR(rv); - if (phy_data & AQUANTIA_ADVERTISE_100FULL) - { - *autoneg |= FAL_PHY_ADV_100TX_FD; - } - if (phy_data & AQUANTIA_ADVERTISE_PAUSE) - { - *autoneg |= FAL_PHY_ADV_PAUSE; - } - if (phy_data & AQUANTIA_ADVERTISE_ASYM_PAUSE) - { - *autoneg |= FAL_PHY_ADV_ASY_PAUSE; - } - - rv = aquantia_phy_reg_read(dev_id, phy_id, AQUANTIA_MMD_AUTONEG, - AQUANTIA_AUTONEG_VENDOR_PROVISION1, &phy_data); - SW_RTN_ON_ERROR(rv); - rv = aquantia_phy_reg_read(dev_id, phy_id, AQUANTIA_MMD_AUTONEG, - AQUANTIA_AUTONEG_10GBASE_T_CONTROL_REGISTER, &phy_data1); - SW_RTN_ON_ERROR(rv); - if (phy_data & AQUANTIA_ADVERTISE_1000FULL) - { - *autoneg |= FAL_PHY_ADV_1000T_FD; - } - if ((phy_data & AQUANTIA_ADVERTISE_2500FULL) && - (phy_data1 & AQUANTIA_ADVERTISE_8023BZ_2500FULL)) - { - *autoneg |= FAL_PHY_ADV_2500T_FD; - } - if ((phy_data & AQUANTIA_ADVERTISE_5000FULL) && - (phy_data1 & AQUANTIA_ADVERTISE_8023BZ_5000FULL)) - { - *autoneg |= FAL_PHY_ADV_5000T_FD; - } - - if (phy_data1 & AQUANTIA_ADVERTISE_10000FULL) - { - *autoneg |= FAL_PHY_ADV_10000T_FD; - } - - return rv; -} - -/****************************************************************************** -* -* aquantia_phy_enable_autonego -* -*/ -a_bool_t aquantia_phy_autoneg_status(a_uint32_t dev_id, a_uint32_t phy_id) -{ - a_uint16_t phy_data; - sw_error_t rv = SW_OK; - - rv = aquantia_phy_reg_read(dev_id, phy_id, AQUANTIA_MMD_AUTONEG, - AQUANTIA_AUTONEG_STANDARD_CONTROL1, &phy_data); - SW_RTN_ON_ERROR(rv); - if (phy_data & AQUANTIA_CTRL_AUTONEGOTIATION_ENABLE) - { - return A_TRUE; - } - - return A_FALSE; -} -/****************************************************************************** -* -* AQUANTIA_restart_autoneg - restart the phy autoneg -* -*/ -sw_error_t aquantia_phy_restart_autoneg(a_uint32_t dev_id, a_uint32_t phy_id) -{ - a_uint16_t phy_data = 0; - sw_error_t rv = SW_OK; - - rv = aquantia_phy_reg_read(dev_id, phy_id, AQUANTIA_MMD_PHY_XS_REGISTERS, - AQUANTIA_PHY_XS_USX_TRANSMIT, &phy_data); - SW_RTN_ON_ERROR(rv); - if (!(phy_data & AQUANTIA_PHY_USX_AUTONEG_ENABLE)) - { - rv = aquantia_phy_reg_write(dev_id, phy_id, AQUANTIA_MMD_PHY_XS_REGISTERS, - AQUANTIA_PHY_XS_USX_TRANSMIT, - phy_data | AQUANTIA_PHY_USX_AUTONEG_ENABLE); - SW_RTN_ON_ERROR(rv); - } - rv = aquantia_phy_reg_read(dev_id, phy_id, AQUANTIA_MMD_AUTONEG, - AQUANTIA_AUTONEG_STANDARD_CONTROL1, &phy_data); - phy_data |= AQUANTIA_CTRL_AUTONEGOTIATION_ENABLE; - SW_RTN_ON_ERROR(rv); - rv = aquantia_phy_reg_write(dev_id, phy_id, AQUANTIA_MMD_AUTONEG, - AQUANTIA_AUTONEG_STANDARD_CONTROL1, - phy_data | AQUANTIA_CTRL_RESTART_AUTONEGOTIATION); - - return rv; -} - -/****************************************************************************** -* -* aquantia_phy_enable_autonego -* -*/ -sw_error_t aquantia_phy_enable_autoneg(a_uint32_t dev_id, a_uint32_t phy_id) -{ - a_uint16_t phy_data = 0; - sw_error_t rv = SW_OK; - - rv = aquantia_phy_reg_read(dev_id, phy_id, AQUANTIA_MMD_AUTONEG, - AQUANTIA_AUTONEG_STANDARD_CONTROL1, &phy_data); - SW_RTN_ON_ERROR(rv); - rv = aquantia_phy_reg_write(dev_id, phy_id, AQUANTIA_MMD_AUTONEG, - AQUANTIA_AUTONEG_STANDARD_CONTROL1, - phy_data | AQUANTIA_CTRL_AUTONEGOTIATION_ENABLE); - - return rv; -} -#ifndef IN_PORTCONTROL_MINI -/****************************************************************************** -* -* aquantia_phy_set_802.3az -* -* set 802.3az status -*/ -sw_error_t -aquantia_phy_set_8023az(a_uint32_t dev_id, a_uint32_t phy_id, a_bool_t enable) -{ - a_uint16_t phy_data = 0, phy_data1 = 0; - sw_error_t rv = SW_OK; - - rv = aquantia_phy_reg_read(dev_id, phy_id, AQUANTIA_MMD_AUTONEG, - AQUANTIA_EEE_ADVERTISTMENT_REGISTER, &phy_data); - SW_RTN_ON_ERROR(rv); - rv = aquantia_phy_reg_read(dev_id, phy_id, AQUANTIA_MMD_AUTONEG, - AQUANTIA_EEE_ADVERTISTMENT_REGISTER1, &phy_data1); - SW_RTN_ON_ERROR(rv); - if(enable == A_TRUE) - { - phy_data |= (AQUANTIA_EEE_ADV_10000M | AQUANTIA_EEE_ADV_1000M); - phy_data1 |= (AQUANTIA_EEE_ADV_2500M | AQUANTIA_EEE_ADV_5000M); - } - else - { - phy_data &= ~(AQUANTIA_EEE_ADV_10000M | AQUANTIA_EEE_ADV_1000M); - phy_data1 &= ~(AQUANTIA_EEE_ADV_2500M | AQUANTIA_EEE_ADV_5000M); - } - rv = aquantia_phy_reg_write(dev_id, phy_id, AQUANTIA_MMD_AUTONEG, - AQUANTIA_EEE_ADVERTISTMENT_REGISTER, phy_data); - SW_RTN_ON_ERROR(rv); - rv = aquantia_phy_reg_write(dev_id, phy_id, AQUANTIA_MMD_AUTONEG, - AQUANTIA_EEE_ADVERTISTMENT_REGISTER1, phy_data1); - SW_RTN_ON_ERROR(rv); - rv = aquantia_phy_restart_autoneg(dev_id, phy_id); - - return rv; -} - -/****************************************************************************** -* -* aquantia_phy_get_8023az status -* -* get 8023az status -*/ -sw_error_t -aquantia_phy_get_8023az(a_uint32_t dev_id, a_uint32_t phy_id, a_bool_t * enable) -{ - a_uint16_t phy_data = 0, phy_data1 = 0; - sw_error_t rv = SW_OK; - - rv = aquantia_phy_reg_read(dev_id, phy_id, AQUANTIA_MMD_AUTONEG, - AQUANTIA_EEE_ADVERTISTMENT_REGISTER, &phy_data); - SW_RTN_ON_ERROR(rv); - - rv = aquantia_phy_reg_read(dev_id, phy_id, AQUANTIA_MMD_AUTONEG, - AQUANTIA_EEE_ADVERTISTMENT_REGISTER1, &phy_data1); - SW_RTN_ON_ERROR(rv); - - if((phy_data & (AQUANTIA_EEE_ADV_1000M | AQUANTIA_EEE_ADV_10000M)) && - (phy_data1 & (AQUANTIA_EEE_ADV_2500M | AQUANTIA_EEE_ADV_5000M))) - { - *enable = A_TRUE; - } - else - { - *enable = A_FALSE; - } - - return rv; -} -#endif -/****************************************************************************** -* -* aquantia_phy_set_speed - Determines the speed of phy ports associated with the -* specified device. -*/ -static sw_error_t _aquantia_phy_set_100speed(a_uint32_t dev_id, a_uint32_t phy_id, fal_port_duplex_t duplex) -{ - a_uint16_t phy_data = 0; - sw_error_t rv = SW_OK; - /*set 100M */ - rv = aquantia_phy_reg_read(dev_id, phy_id, AQUANTIA_MMD_AUTONEG, - AQUANTIA_AUTONEG_ADVERTISEMENT_REGISTER, &phy_data); - SW_RTN_ON_ERROR(rv); - phy_data &= ~(AQUANTIA_ADVERTISE_MEGA_ALL); - if(duplex == FAL_FULL_DUPLEX) - { - phy_data |= AQUANTIA_ADVERTISE_100FULL; - } - else - { - phy_data |= AQUANTIA_ADVERTISE_100HALF; - } - rv = aquantia_phy_reg_write(dev_id, phy_id, AQUANTIA_MMD_AUTONEG, - AQUANTIA_AUTONEG_ADVERTISEMENT_REGISTER, phy_data); - SW_RTN_ON_ERROR(rv); - /*disable 1000M, 2500M, 5000M speed*/ - rv = aquantia_phy_reg_read(dev_id, phy_id, AQUANTIA_MMD_AUTONEG, - AQUANTIA_AUTONEG_VENDOR_PROVISION1, &phy_data); - SW_RTN_ON_ERROR(rv); - phy_data &= ~(AQUANTIA_ADVERTISE_GIGA_ALL); - rv = aquantia_phy_reg_write(dev_id, phy_id, AQUANTIA_MMD_AUTONEG, - AQUANTIA_AUTONEG_VENDOR_PROVISION1, phy_data); - SW_RTN_ON_ERROR(rv); - /*disable 10000M speed*/ - rv = aquantia_phy_reg_read(dev_id, phy_id, AQUANTIA_MMD_AUTONEG, - AQUANTIA_AUTONEG_10GBASE_T_CONTROL_REGISTER, &phy_data); - SW_RTN_ON_ERROR(rv); - phy_data &= ~(AQUANTIA_ADVERTISE_GIGA_PLUS_ALL); - rv = aquantia_phy_reg_write(dev_id, phy_id, AQUANTIA_MMD_AUTONEG, - AQUANTIA_AUTONEG_10GBASE_T_CONTROL_REGISTER, phy_data); - - return rv; -} - -static sw_error_t _aquantia_phy_set_giga_speed(a_uint32_t dev_id, a_uint32_t phy_id, fal_port_speed_t speed) -{ - a_uint16_t phy_data = 0, phy_data1 = 0; - sw_error_t rv = SW_OK; - /*set 1000M and disable 2500M, 5000M */ - rv = aquantia_phy_reg_read(dev_id, phy_id, AQUANTIA_MMD_AUTONEG, - AQUANTIA_AUTONEG_VENDOR_PROVISION1, &phy_data); - SW_RTN_ON_ERROR(rv); - phy_data &= ~(AQUANTIA_ADVERTISE_GIGA_ALL); - rv = aquantia_phy_reg_read(dev_id, phy_id, AQUANTIA_MMD_AUTONEG, - AQUANTIA_AUTONEG_10GBASE_T_CONTROL_REGISTER, &phy_data1); - SW_RTN_ON_ERROR(rv); - phy_data1 &= ~(AQUANTIA_ADVERTISE_GIGA_PLUS_ALL); - switch(speed) - { - case FAL_SPEED_1000: - phy_data |= AQUANTIA_ADVERTISE_1000FULL; - break; - case FAL_SPEED_2500: - phy_data |= AQUANTIA_ADVERTISE_2500FULL; - phy_data1 |= AQUANTIA_ADVERTISE_8023BZ_2500FULL; - break; - case FAL_SPEED_5000: - phy_data |= AQUANTIA_ADVERTISE_5000FULL; - phy_data1 |= AQUANTIA_ADVERTISE_8023BZ_5000FULL; - break; - default: - return SW_NOT_SUPPORTED; - } - rv = aquantia_phy_reg_write(dev_id, phy_id, AQUANTIA_MMD_AUTONEG, - AQUANTIA_AUTONEG_VENDOR_PROVISION1, phy_data); - SW_RTN_ON_ERROR(rv); - rv = aquantia_phy_reg_write(dev_id, phy_id, AQUANTIA_MMD_AUTONEG, - AQUANTIA_AUTONEG_10GBASE_T_CONTROL_REGISTER, phy_data1); - SW_RTN_ON_ERROR(rv); - - /*disable 100M speed*/ - rv = aquantia_phy_reg_read(dev_id, phy_id, AQUANTIA_MMD_AUTONEG, - AQUANTIA_AUTONEG_ADVERTISEMENT_REGISTER, &phy_data); - SW_RTN_ON_ERROR(rv); - phy_data &= ~(AQUANTIA_ADVERTISE_MEGA_ALL); - rv = aquantia_phy_reg_write(dev_id, phy_id, AQUANTIA_MMD_AUTONEG, - AQUANTIA_AUTONEG_ADVERTISEMENT_REGISTER, phy_data); - - return rv; -} - -static sw_error_t _aquantia_phy_set_10g_speed(a_uint32_t dev_id, a_uint32_t phy_id) -{ - a_uint16_t phy_data = 0; - sw_error_t rv = SW_OK; - /*set giga speed */ - rv = aquantia_phy_reg_read(dev_id, phy_id, AQUANTIA_MMD_AUTONEG, - AQUANTIA_AUTONEG_10GBASE_T_CONTROL_REGISTER,&phy_data); - SW_RTN_ON_ERROR(rv); - phy_data &= ~(AQUANTIA_ADVERTISE_GIGA_PLUS_ALL); - phy_data |= AQUANTIA_ADVERTISE_10000FULL; - rv = aquantia_phy_reg_write(dev_id, phy_id, AQUANTIA_MMD_AUTONEG, - AQUANTIA_AUTONEG_10GBASE_T_CONTROL_REGISTER, phy_data); - SW_RTN_ON_ERROR(rv); - - /*disable 100M speed*/ - rv = aquantia_phy_reg_read(dev_id, phy_id, AQUANTIA_MMD_AUTONEG, - AQUANTIA_AUTONEG_ADVERTISEMENT_REGISTER, &phy_data); - SW_RTN_ON_ERROR(rv); - phy_data &= ~(AQUANTIA_ADVERTISE_MEGA_ALL); - rv = aquantia_phy_reg_write(dev_id, phy_id, AQUANTIA_MMD_AUTONEG, - AQUANTIA_AUTONEG_ADVERTISEMENT_REGISTER, phy_data); - SW_RTN_ON_ERROR(rv); - - /*disable 1000M 2500M 5000M speed*/ - rv = aquantia_phy_reg_read(dev_id, phy_id, AQUANTIA_MMD_AUTONEG, - AQUANTIA_AUTONEG_VENDOR_PROVISION1, &phy_data); - SW_RTN_ON_ERROR(rv); - phy_data &= ~(AQUANTIA_ADVERTISE_GIGA_ALL); - rv = aquantia_phy_reg_write(dev_id, phy_id, AQUANTIA_MMD_AUTONEG, - AQUANTIA_AUTONEG_VENDOR_PROVISION1, phy_data); - - return rv; -} - -sw_error_t -aquantia_phy_set_speed(a_uint32_t dev_id, a_uint32_t phy_id, - fal_port_speed_t speed) -{ - fal_port_duplex_t old_duplex; - sw_error_t rv; - - rv = aquantia_phy_get_duplex(dev_id, phy_id, &old_duplex); - SW_RTN_ON_ERROR(rv); - if (old_duplex == FAL_FULL_DUPLEX) { - if (FAL_SPEED_100 == speed) { - rv = _aquantia_phy_set_100speed(dev_id, phy_id, FAL_FULL_DUPLEX); - SW_RTN_ON_ERROR(rv); - } else if(FAL_SPEED_2500 == speed ||FAL_SPEED_5000 == speed || FAL_SPEED_1000 == speed){ - rv = _aquantia_phy_set_giga_speed(dev_id, phy_id, speed); - SW_RTN_ON_ERROR(rv); - } else if(FAL_SPEED_10000 == speed){ - rv = _aquantia_phy_set_10g_speed(dev_id, phy_id); - SW_RTN_ON_ERROR(rv); - } else { - return SW_BAD_PARAM; - } - } else if (old_duplex == FAL_HALF_DUPLEX) { - if (FAL_SPEED_100 == speed) { - rv = _aquantia_phy_set_100speed(dev_id, phy_id, FAL_HALF_DUPLEX); - SW_RTN_ON_ERROR(rv); - } else { - return SW_BAD_PARAM; - } - } else { - return SW_FAIL; - } - rv = aquantia_phy_restart_autoneg(dev_id, phy_id); - - return rv; -} - -/****************************************************************************** -* -* aquantia_phy_set_duplex - Determines the speed of phy ports associated with the -* specified device. -*/ -sw_error_t -aquantia_phy_set_duplex(a_uint32_t dev_id, a_uint32_t phy_id, - fal_port_duplex_t duplex) -{ - a_uint16_t phy_data = 0; - fal_port_speed_t old_speed; - sw_error_t rv = SW_OK; - - rv = aquantia_phy_get_speed(dev_id, phy_id, &old_speed); - SW_RTN_ON_ERROR(rv); - if (old_speed == FAL_SPEED_100){ - rv = aquantia_phy_reg_read(dev_id, phy_id, AQUANTIA_MMD_AUTONEG, - AQUANTIA_AUTONEG_ADVERTISEMENT_REGISTER, &phy_data); - SW_RTN_ON_ERROR(rv); - if (duplex == FAL_FULL_DUPLEX) { - phy_data &= ~(AQUANTIA_ADVERTISE_MEGA_ALL); - phy_data |= AQUANTIA_ADVERTISE_100FULL; - rv = aquantia_phy_reg_write(dev_id, phy_id, AQUANTIA_MMD_AUTONEG, - AQUANTIA_AUTONEG_ADVERTISEMENT_REGISTER, phy_data); - SW_RTN_ON_ERROR(rv); - } else { - phy_data &= ~(AQUANTIA_ADVERTISE_MEGA_ALL); - phy_data |= AQUANTIA_ADVERTISE_100HALF; - rv = aquantia_phy_reg_write(dev_id, phy_id, AQUANTIA_MMD_AUTONEG, - AQUANTIA_AUTONEG_ADVERTISEMENT_REGISTER, phy_data); - SW_RTN_ON_ERROR(rv); - } - } else { - return SW_NOT_SUPPORTED; - } - rv = aquantia_phy_restart_autoneg(dev_id, phy_id); - - return rv; -} -#ifndef IN_PORTCONTROL_MINI -/****************************************************************************** -* -* aquantia_phy_set wol enable or disable -* -* set phy wol enable or disable -*/ -sw_error_t -aquantia_phy_set_wol_status(a_uint32_t dev_id, a_uint32_t phy_id, a_bool_t enable) -{ - a_uint16_t phy_data0, phy_data1, phy_data2; - sw_error_t rv = SW_OK; - - rv = aquantia_phy_reg_read(dev_id, phy_id, AQUANTIA_MMD_AUTONEG, - AQUANTIA_RESERVED_VENDOR_PROVISIONING1, &phy_data0); - SW_RTN_ON_ERROR(rv); - rv = aquantia_phy_reg_read(dev_id, phy_id, AQUANTIA_MMD_GBE_STANDARD_REGISTERS, - AQUANTIA_MAGIC_ENGINE_REGISTER1, &phy_data1); - SW_RTN_ON_ERROR(rv); - rv = aquantia_phy_reg_read(dev_id, phy_id, AQUANTIA_MMD_GBE_STANDARD_REGISTERS, - AQUANTIA_MAGIC_ENGINE_REGISTER2, &phy_data2); - - if (enable == A_TRUE) - { - phy_data0 |= AQUANTIA_PHY_WOL_ENABLE; - phy_data1 |= AQUANTIA_MAGIC_PACKETS_ENABLE; - phy_data2 |= AQUANTIA_MAGIC_PACKETS_ENABLE; - } - else - { - phy_data0 &= ~AQUANTIA_PHY_WOL_ENABLE; - phy_data1 &= ~AQUANTIA_MAGIC_PACKETS_ENABLE; - phy_data2 &= ~AQUANTIA_MAGIC_PACKETS_ENABLE; - } - rv = aquantia_phy_reg_write(dev_id, phy_id, AQUANTIA_MMD_AUTONEG, - AQUANTIA_RESERVED_VENDOR_PROVISIONING1, phy_data0); - SW_RTN_ON_ERROR(rv); - rv = aquantia_phy_reg_write(dev_id, phy_id, AQUANTIA_MMD_GBE_STANDARD_REGISTERS, - AQUANTIA_MAGIC_ENGINE_REGISTER1, phy_data1); - SW_RTN_ON_ERROR(rv); - rv = aquantia_phy_reg_write(dev_id, phy_id, AQUANTIA_MMD_GBE_STANDARD_REGISTERS, - AQUANTIA_MAGIC_ENGINE_REGISTER2, phy_data2); - - return rv; -} - -/****************************************************************************** -* -* aquantia_phy_get_wol status -* -* get wol status -*/ -sw_error_t -aquantia_phy_get_wol_status(a_uint32_t dev_id, a_uint32_t phy_id, a_bool_t * enable) -{ - a_uint16_t phy_data; - sw_error_t rv = SW_OK; - - *enable = A_FALSE; - rv = aquantia_phy_reg_read(dev_id, phy_id, AQUANTIA_MMD_AUTONEG, - AQUANTIA_RESERVED_VENDOR_PROVISIONING1, &phy_data); - SW_RTN_ON_ERROR(rv); - if (phy_data & AQUANTIA_PHY_WOL_ENABLE) - { - *enable = A_TRUE; - } - - return rv; -} - -/****************************************************************************** -* -* aquantia_phy_set wol frame mac address -* -* set phy wol frame mac address -*/ -sw_error_t -aquantia_phy_set_magic_frame_mac(a_uint32_t dev_id, a_uint32_t phy_id, - fal_mac_addr_t * mac) -{ - a_uint16_t phy_data1; - a_uint16_t phy_data2; - a_uint16_t phy_data3; - sw_error_t rv = SW_OK; - - phy_data1 = (mac->uc[1] << 8) | mac->uc[0]; - phy_data2 = (mac->uc[3] << 8) | mac->uc[2]; - phy_data3 = (mac->uc[5] << 8) | mac->uc[4]; - rv = aquantia_phy_reg_write(dev_id, phy_id, AQUANTIA_MMD_GBE_STANDARD_REGISTERS, - AQUANTIA_MAGIC_FRAME_MAC0, phy_data1); - SW_RTN_ON_ERROR(rv); - rv = aquantia_phy_reg_write(dev_id, phy_id, AQUANTIA_MMD_GBE_STANDARD_REGISTERS, - AQUANTIA_MAGIC_FRAME_MAC1, phy_data2); - SW_RTN_ON_ERROR(rv); - rv = aquantia_phy_reg_write(dev_id, phy_id, AQUANTIA_MMD_GBE_STANDARD_REGISTERS, - AQUANTIA_MAGIC_FRAME_MAC2, phy_data3); - - return rv; -} - -/****************************************************************************** -* -* aquantia_phy_get wol frame mac address -* -* get phy wol frame mac address -*/ -sw_error_t -aquantia_phy_get_magic_frame_mac(a_uint32_t dev_id, a_uint32_t phy_id, - fal_mac_addr_t * mac) -{ - a_uint16_t phy_data1; - a_uint16_t phy_data2; - a_uint16_t phy_data3; - sw_error_t rv = SW_OK; - - rv = aquantia_phy_reg_read(dev_id, phy_id, AQUANTIA_MMD_GBE_STANDARD_REGISTERS, - AQUANTIA_MAGIC_FRAME_MAC0, &phy_data1); - SW_RTN_ON_ERROR(rv); - rv = aquantia_phy_reg_read(dev_id, phy_id, AQUANTIA_MMD_GBE_STANDARD_REGISTERS, - AQUANTIA_MAGIC_FRAME_MAC1, &phy_data2); - SW_RTN_ON_ERROR(rv); - rv = aquantia_phy_reg_read(dev_id, phy_id, AQUANTIA_MMD_GBE_STANDARD_REGISTERS, - AQUANTIA_MAGIC_FRAME_MAC2, &phy_data3); - SW_RTN_ON_ERROR(rv); - mac->uc[0] = (phy_data1 & BITS(0, 8)); - mac->uc[1] = (phy_data1 >> 8) & BITS(0, 8); - mac->uc[2] = (phy_data2 & BITS(0, 8)); - mac->uc[3] = (phy_data2 >> 8) & BITS(0, 8); - mac->uc[4] = (phy_data3 & BITS(0, 8)); - mac->uc[5] = (phy_data3 >> 8) & BITS(0, 8); - - return rv; -} -#endif -sw_error_t -aquantia_phy_interface_set_mode(a_uint32_t dev_id, a_uint32_t phy_id, fal_port_interface_mode_t interface_mode) -{ - a_uint16_t phy_data; - a_uint32_t phy_register; - fal_port_speed_t speed; - sw_error_t rv =SW_OK; - - rv = aquantia_phy_get_speed(dev_id, phy_id, &speed); - SW_RTN_ON_ERROR(rv); - switch (speed) - { - case FAL_SPEED_100: - phy_register = AQUANTIA_GLOBAL_SYS_CONFIG_FOR_100M; - break; - case FAL_SPEED_1000: - phy_register = AQUANTIA_GLOBAL_SYS_CONFIG_FOR_1000M; - break; - case FAL_SPEED_2500: - phy_register = AQUANTIA_GLOBAL_SYS_CONFIG_FOR_2500M; - break; - case FAL_SPEED_5000: - phy_register = AQUANTIA_GLOBAL_SYS_CONFIG_FOR_5000M; - break; - case FAL_SPEED_10000: - phy_register = AQUANTIA_GLOBAL_SYS_CONFIG_FOR_10000M; - break; - default: - return SW_NOT_SUPPORTED; - } - rv = aquantia_phy_reg_read(dev_id, phy_id, AQUANTIA_MMD_GLOBAL_REGISTERS, - phy_register, &phy_data); - SW_RTN_ON_ERROR(rv); - phy_data &= ~(BITS(0, 3)); - switch(interface_mode) - { - case PHY_SGMII_BASET: - if(speed == FAL_SPEED_100 || speed == FAL_SPEED_1000) - { - phy_data |= AQUANTIA_SERDES_MODE_SGMII; - } - else - { - return SW_NOT_SUPPORTED; - } - break; - case PORT_USXGMII: - phy_data |= AQUANTIA_SERDES_MODE_XFI; - break; - case PORT_SGMII_PLUS: - if(speed == FAL_SPEED_2500) - { - phy_data |= AQUANTIA_SERDES_MODE_OCSGMII; - } - else - { - return SW_NOT_SUPPORTED; - } - break; - default: - return SW_NOT_SUPPORTED; - } - rv = aquantia_phy_reg_write(dev_id, phy_id, AQUANTIA_MMD_GLOBAL_REGISTERS, - phy_register, phy_data); - - return rv; -} - -/****************************************************************************** -* -* aquantia_phy_interface mode status get -* -* get aquantia phy interface mode status -*/ -sw_error_t -aquantia_phy_interface_get_mode_status(a_uint32_t dev_id, a_uint32_t phy_id, - fal_port_interface_mode_t *interface_mode_status) -{ - a_uint16_t phy_data; - a_uint32_t phy_register; - fal_port_speed_t speed; - sw_error_t rv = SW_OK; - - rv = aquantia_phy_get_speed(dev_id, phy_id, &speed); - SW_RTN_ON_ERROR(rv); - switch (speed) - { - case FAL_SPEED_100: - phy_register = AQUANTIA_GLOBAL_SYS_CONFIG_FOR_100M; - break; - case FAL_SPEED_1000: - phy_register = AQUANTIA_GLOBAL_SYS_CONFIG_FOR_1000M; - break; - case FAL_SPEED_2500: - phy_register = AQUANTIA_GLOBAL_SYS_CONFIG_FOR_2500M; - break; - case FAL_SPEED_5000: - phy_register = AQUANTIA_GLOBAL_SYS_CONFIG_FOR_5000M; - break; - case FAL_SPEED_10000: - phy_register = AQUANTIA_GLOBAL_SYS_CONFIG_FOR_10000M; - break; - default: - return SW_NOT_SUPPORTED; - } - rv = aquantia_phy_reg_read(dev_id, phy_id, AQUANTIA_MMD_GLOBAL_REGISTERS, - phy_register, &phy_data); - SW_RTN_ON_ERROR(rv); - phy_data &= (BITS(0, 3)); - switch(phy_data) - { - case AQUANTIA_SERDES_MODE_SGMII: - *interface_mode_status = PHY_SGMII_BASET; - break; - case AQUANTIA_SERDES_MODE_XFI: - *interface_mode_status = PORT_USXGMII; - break; - case AQUANTIA_SERDES_MODE_OCSGMII: - *interface_mode_status = PORT_SGMII_PLUS; - break; - default: - return SW_NOT_SUPPORTED; - } - - return rv; -} -#ifndef IN_PORTCONTROL_MINI -/****************************************************************************** -* -* aquantia_phy_intr_mask_set - Set interrupt mask with the -* specified device. -*/ -sw_error_t -aquantia_phy_intr_mask_set(a_uint32_t dev_id, a_uint32_t phy_id, - a_uint32_t intr_mask_flag) -{ - a_uint16_t phy_data = 0; - sw_error_t rv = SW_OK; - - if ((FAL_PHY_INTR_STATUS_DOWN_CHANGE |FAL_PHY_INTR_STATUS_UP_CHANGE) - & intr_mask_flag) - { - rv = aquantia_phy_reg_read(dev_id, phy_id, AQUANTIA_MMD_AUTONEG, - AQUANTIA_AUTONEG_TRANSMIT_VENDOR_INTR_MASK, &phy_data); - SW_RTN_ON_ERROR(rv); - phy_data |= AQUANTIA_INTR_LINK_STATUS_CHANGE; - rv = aquantia_phy_reg_write(dev_id, phy_id, AQUANTIA_MMD_AUTONEG, - AQUANTIA_AUTONEG_TRANSMIT_VENDOR_INTR_MASK, phy_data); - SW_RTN_ON_ERROR(rv); - - rv = aquantia_phy_reg_read(dev_id, phy_id, AQUANTIA_MMD_GLOBAL_REGISTERS, - AQUANTIA_GLOBAL_INTR_VENDOR_MASK, &phy_data); - SW_RTN_ON_ERROR(rv); - phy_data |= AQUANTIA_AUTO_AND_ALARMS_INTR_MASK; - rv = aquantia_phy_reg_write(dev_id, phy_id, AQUANTIA_MMD_GLOBAL_REGISTERS, - AQUANTIA_GLOBAL_INTR_VENDOR_MASK, phy_data); - SW_RTN_ON_ERROR(rv); - - rv = aquantia_phy_reg_read(dev_id, phy_id, AQUANTIA_MMD_GLOBAL_REGISTERS, - AQUANTIA_GLOBAL_INTR_STANDARD_MASK, &phy_data); - SW_RTN_ON_ERROR(rv); - phy_data |= AQUANTIA_ALL_VENDOR_ALARMS_INTR_MASK; - rv = aquantia_phy_reg_write(dev_id, phy_id, AQUANTIA_MMD_GLOBAL_REGISTERS, - AQUANTIA_GLOBAL_INTR_STANDARD_MASK, phy_data); - } - - return rv; -} - -/****************************************************************************** -* -* aquantia_phy_intr_mask_get - Get interrupt mask with the -* specified device. -*/ -sw_error_t -aquantia_phy_intr_mask_get(a_uint32_t dev_id, a_uint32_t phy_id, - a_uint32_t * intr_mask_flag) -{ - a_uint16_t phy_data1 = 0, phy_data2 = 0, phy_data3 = 0; - sw_error_t rv = SW_OK; - - rv = aquantia_phy_reg_read(dev_id, phy_id, AQUANTIA_MMD_AUTONEG, - AQUANTIA_AUTONEG_TRANSMIT_VENDOR_INTR_MASK, &phy_data1); - SW_RTN_ON_ERROR(rv); - rv = aquantia_phy_reg_read(dev_id, phy_id, AQUANTIA_MMD_GLOBAL_REGISTERS, - AQUANTIA_GLOBAL_INTR_VENDOR_MASK, &phy_data2); - SW_RTN_ON_ERROR(rv); - rv = aquantia_phy_reg_read(dev_id, phy_id, AQUANTIA_MMD_GLOBAL_REGISTERS, - AQUANTIA_GLOBAL_INTR_STANDARD_MASK, &phy_data3); - if ((AQUANTIA_INTR_LINK_STATUS_CHANGE & phy_data1) && - (AQUANTIA_AUTO_AND_ALARMS_INTR_MASK & phy_data2) && - (AQUANTIA_ALL_VENDOR_ALARMS_INTR_MASK & phy_data3)) - { - *intr_mask_flag = FAL_PHY_INTR_STATUS_DOWN_CHANGE | - FAL_PHY_INTR_STATUS_UP_CHANGE; - } - - return rv; -} -#endif -/****************************************************************************** -* -* aquantia_phy_off - power off the phy -* -* Power off the phy -*/ -sw_error_t aquantia_phy_poweroff(a_uint32_t dev_id, a_uint32_t phy_id) -{ - a_uint16_t phy_data; - sw_error_t rv; - - rv = aquantia_phy_reg_read(dev_id, phy_id, AQUANTIA_MMD_GLOBAL_REGISTERS, - AQUANTIA_GLOBAL_STANDARD_CONTROL1, &phy_data); - SW_RTN_ON_ERROR(rv); - phy_data |= AQUANTIA_POWER_DOWN; - rv = aquantia_phy_reg_write(dev_id, phy_id, AQUANTIA_MMD_GLOBAL_REGISTERS, - AQUANTIA_GLOBAL_STANDARD_CONTROL1,phy_data); - - return rv; -} - -/****************************************************************************** -* -* aquantia_phy_on - power on the phy -* -* Power on the phy -*/ -sw_error_t aquantia_phy_poweron(a_uint32_t dev_id, a_uint32_t phy_id) -{ - a_uint16_t phy_data; - sw_error_t rv; - - rv = aquantia_phy_reg_read(dev_id, phy_id, AQUANTIA_MMD_GLOBAL_REGISTERS, - AQUANTIA_GLOBAL_STANDARD_CONTROL1, &phy_data); - SW_RTN_ON_ERROR(rv); - phy_data &= ~AQUANTIA_POWER_DOWN; - rv = aquantia_phy_reg_write(dev_id, phy_id, AQUANTIA_MMD_GLOBAL_REGISTERS, - AQUANTIA_GLOBAL_STANDARD_CONTROL1,phy_data); - - return rv; -} -#ifndef IN_PORTCONTROL_MINI -static sw_error_t -_aquantia_phy_line_side_counter_get(a_uint32_t dev_id, a_uint32_t phy_id, - fal_port_counter_info_t * counter_infor) -{ - a_uint16_t msw_counter; - a_uint16_t lsw_counter; - sw_error_t rv = SW_OK; - - /*get line side tx good packets*/ - rv = aquantia_phy_reg_read(dev_id, phy_id, AQUANTIA_MMD_PCS_REGISTERS, - AQUANTIA_LINE_SIDE_TRANSMIT_GOOD_FRAME_COUNTER2, &msw_counter); - SW_RTN_ON_ERROR(rv); - rv = aquantia_phy_reg_read(dev_id, phy_id, AQUANTIA_MMD_PCS_REGISTERS, - AQUANTIA_LINE_SIDE_TRANSMIT_GOOD_FRAME_COUNTER1, &lsw_counter); - SW_RTN_ON_ERROR(rv); - counter_infor->TxGoodFrame = (msw_counter << 16) | lsw_counter; - - /*get line side tx bad packets*/ - rv = aquantia_phy_reg_read(dev_id, phy_id, AQUANTIA_MMD_PCS_REGISTERS, - AQUANTIA_LINE_SIDE_TRANSMIT_ERROR_FRAME_COUNTER2, &msw_counter); - SW_RTN_ON_ERROR(rv); - rv = aquantia_phy_reg_read(dev_id, phy_id, AQUANTIA_MMD_PCS_REGISTERS, - AQUANTIA_LINE_SIDE_TRANSMIT_ERROR_FRAME_COUNTER1, &lsw_counter); - SW_RTN_ON_ERROR(rv); - counter_infor->TxBadCRC = (msw_counter << 16) | lsw_counter; - - /*get line side rx good packets*/ - rv = aquantia_phy_reg_read(dev_id, phy_id, AQUANTIA_MMD_PCS_REGISTERS, - AQUANTIA_LINE_SIDE_RECEIVE_GOOD_FRAME_COUNTER2, &msw_counter); - SW_RTN_ON_ERROR(rv); - rv = aquantia_phy_reg_read(dev_id, phy_id, AQUANTIA_MMD_PCS_REGISTERS, - AQUANTIA_LINE_SIDE_RECEIVE_GOOD_FRAME_COUNTER1, &lsw_counter); - SW_RTN_ON_ERROR(rv); - counter_infor->RxGoodFrame = (msw_counter << 16) | lsw_counter; - - /*get line side rx bad packets*/ - rv = aquantia_phy_reg_read(dev_id, phy_id, AQUANTIA_MMD_PCS_REGISTERS, - AQUANTIA_LINE_SIDE_RECEIVE_ERROR_FRAME_COUNTER2, &msw_counter); - SW_RTN_ON_ERROR(rv); - rv = aquantia_phy_reg_read(dev_id, phy_id, AQUANTIA_MMD_PCS_REGISTERS, - AQUANTIA_LINE_SIDE_RECEIVE_ERROR_FRAME_COUNTER1, &lsw_counter); - SW_RTN_ON_ERROR(rv); - counter_infor->RxBadCRC = (msw_counter << 16) | lsw_counter; - - return rv; -} - -static sw_error_t -_aquantia_phy_system_side_counter_get(a_uint32_t dev_id, a_uint32_t phy_id, - fal_port_counter_info_t * counter_infor) -{ - a_uint16_t msw_counter; - a_uint16_t lsw_counter; - sw_error_t rv = SW_OK; - - /*get system tx good packets*/ - rv = aquantia_phy_reg_read(dev_id, phy_id, AQUANTIA_MMD_PCS_REGISTERS, - AQUANTIA_SYSTEM_SIDE_TRANSMIT_GOOD_FRAME_COUNTER2, &msw_counter); - SW_RTN_ON_ERROR(rv); - rv = aquantia_phy_reg_read(dev_id, phy_id, AQUANTIA_MMD_PCS_REGISTERS, - AQUANTIA_SYSTEM_SIDE_TRANSMIT_GOOD_FRAME_COUNTER1, &lsw_counter); - SW_RTN_ON_ERROR(rv); - counter_infor->SysTxGoodFrame = (msw_counter << 16) | lsw_counter; - - /*get system tx bad packets*/ - rv = aquantia_phy_reg_read(dev_id, phy_id, AQUANTIA_MMD_PCS_REGISTERS, - AQUANTIA_SYSTEM_SIDE_TRANSMIT_ERROR_FRAME_COUNTER2, &msw_counter); - SW_RTN_ON_ERROR(rv); - rv = aquantia_phy_reg_read(dev_id, phy_id, AQUANTIA_MMD_PCS_REGISTERS, - AQUANTIA_SYSTEM_SIDE_TRANSMIT_ERROR_FRAME_COUNTER1, &lsw_counter); - SW_RTN_ON_ERROR(rv); - counter_infor->SysTxBadCRC = (msw_counter << 16) | lsw_counter; - - /*get system rx good packets*/ - rv = aquantia_phy_reg_read(dev_id, phy_id, AQUANTIA_MMD_PCS_REGISTERS, - AQUANTIA_SYSTEM_SIDE_RECEIVE_GOOD_FRAME_COUNTER2, &msw_counter); - SW_RTN_ON_ERROR(rv); - rv = aquantia_phy_reg_read(dev_id, phy_id, AQUANTIA_MMD_PCS_REGISTERS, - AQUANTIA_SYSTEM_SIDE_RECEIVE_GOOD_FRAME_COUNTER1, &lsw_counter); - SW_RTN_ON_ERROR(rv); - counter_infor->SysRxGoodFrame = (msw_counter << 16) | lsw_counter; - - /*get system rx bad packets*/ - rv = aquantia_phy_reg_read(dev_id, phy_id, AQUANTIA_MMD_PCS_REGISTERS, - AQUANTIA_SYSTEM_SIDE_RECEIVE_ERROR_FRAME_COUNTER2, &msw_counter); - SW_RTN_ON_ERROR(rv); - rv = aquantia_phy_reg_read(dev_id, phy_id, AQUANTIA_MMD_PCS_REGISTERS, - AQUANTIA_SYSTEM_SIDE_RECEIVE_ERROR_FRAME_COUNTER1, &lsw_counter); - SW_RTN_ON_ERROR(rv); - counter_infor->SysRxBadCRC = (msw_counter << 16) | lsw_counter; - - return rv; -} - -/****************************************************************************** -* -* aquantia_phy_show show counter statistics -* -* show counter statistics -*/ -sw_error_t -aquantia_phy_show_counter(a_uint32_t dev_id, a_uint32_t phy_id, - fal_port_counter_info_t * counter_infor) -{ - sw_error_t rv = SW_OK; - fal_port_speed_t speed; - - rv = aquantia_phy_get_speed(dev_id, phy_id, &speed); - SW_RTN_ON_ERROR(rv); - if(speed == FAL_SPEED_2500 || speed == FAL_SPEED_5000 || speed == FAL_SPEED_10000) - { - rv = _aquantia_phy_line_side_counter_get(dev_id, phy_id, counter_infor); - SW_RTN_ON_ERROR(rv); - } - rv = _aquantia_phy_system_side_counter_get(dev_id, phy_id, counter_infor); - - return rv; -} -#endif -/****************************************************************************** -* -* aquantia_phy_get_status -* -* get phy status -*/ -sw_error_t -aquantia_phy_get_status(a_uint32_t dev_id, a_uint32_t phy_id, - struct port_phy_status *phy_status) -{ - sw_error_t rv = SW_OK; - a_uint16_t phy_data; - - /*get phy link status*/ - phy_status->link_status = aquantia_phy_get_link_status(dev_id, phy_id); - if(phy_status->link_status != A_TRUE) - { - return SW_OK; - } - /*get phy speed and duplex*/ - rv = aquantia_phy_reg_read(dev_id, phy_id, AQUANTIA_MMD_AUTONEG, - AQUANTIA_REG_AUTONEG_VENDOR_STATUS, &phy_data); - SW_RTN_ON_ERROR(rv); - switch ((phy_data & AQUANTIA_STATUS_SPEED_MASK) >>1) - { - case AQUANTIA_STATUS_SPEED_100MBS: - phy_status->speed = FAL_SPEED_100; - break; - case AQUANTIA_STATUS_SPEED_1000MBS: - phy_status->speed = FAL_SPEED_1000; - break; - case AQUANTIA_STATUS_SPEED_2500MBS: - phy_status->speed = FAL_SPEED_2500; - break; - case AQUANTIA_STATUS_SPEED_5000MBS: - phy_status->speed = FAL_SPEED_5000; - break; - case AQUANTIA_STATUS_SPEED_10000MBS: - phy_status->speed = FAL_SPEED_10000; - break; - default: - return SW_READ_ERROR; - } - if (phy_data & AQUANTIA_STATUS_FULL_DUPLEX) - { - phy_status->duplex = FAL_FULL_DUPLEX; - } - else - { - phy_status->duplex = FAL_HALF_DUPLEX; - } - /* get phy tx flowctrl and rx flowctrl resolution status */ - rv = aquantia_phy_reg_read(dev_id, phy_id, AQUANTIA_MMD_AUTONEG, - AQUANTIA_RESERVED_VENDOR_STATUS1, &phy_data); - SW_RTN_ON_ERROR(rv); - if(phy_data & AQUANTIA_PHY_TX_FLOWCTRL_STATUS) - { - phy_status->tx_flowctrl = A_TRUE; - } - else - { - phy_status->tx_flowctrl = A_FALSE; - } - if(phy_data & AQUANTIA_PHY_RX_FLOWCTRL_STATUS) - { - phy_status->rx_flowctrl = A_TRUE; - } - else - { - phy_status->rx_flowctrl = A_FALSE; - } - - return rv; -} - -/****************************************************************************** -* -* aquantia_phy_set_eee_advertisement -* -* set eee advertisement -*/ -sw_error_t -aquantia_phy_set_eee_adv(a_uint32_t dev_id, a_uint32_t phy_id, - a_uint32_t adv) -{ - a_uint16_t phy_data = 0, phy_data1 = 0; - sw_error_t rv = SW_OK; - - rv = aquantia_phy_reg_read(dev_id, phy_id, AQUANTIA_MMD_AUTONEG, - AQUANTIA_EEE_ADVERTISTMENT_REGISTER, &phy_data); - SW_RTN_ON_ERROR(rv); - rv = aquantia_phy_reg_read(dev_id, phy_id, AQUANTIA_MMD_AUTONEG, - AQUANTIA_EEE_ADVERTISTMENT_REGISTER1, &phy_data1); - SW_RTN_ON_ERROR(rv); - - phy_data &= ~(AQUANTIA_EEE_ADV_1000M | AQUANTIA_EEE_ADV_10000M); - if (adv & FAL_PHY_EEE_1000BASE_T) { - phy_data |= AQUANTIA_EEE_ADV_1000M; - } - if (adv & FAL_PHY_EEE_10000BASE_T) { - phy_data |= AQUANTIA_EEE_ADV_10000M; - } - - phy_data1 &= ~(AQUANTIA_EEE_ADV_2500M | AQUANTIA_EEE_ADV_5000M); - if (adv & FAL_PHY_EEE_2500BASE_T) { - phy_data1 |= AQUANTIA_EEE_ADV_2500M; - } - if (adv & FAL_PHY_EEE_5000BASE_T) { - phy_data1 |= AQUANTIA_EEE_ADV_5000M; - } - - rv = aquantia_phy_reg_write(dev_id, phy_id, AQUANTIA_MMD_AUTONEG, - AQUANTIA_EEE_ADVERTISTMENT_REGISTER, phy_data); - SW_RTN_ON_ERROR(rv); - rv = aquantia_phy_reg_write(dev_id, phy_id, AQUANTIA_MMD_AUTONEG, - AQUANTIA_EEE_ADVERTISTMENT_REGISTER1, phy_data1); - SW_RTN_ON_ERROR(rv); - rv = aquantia_phy_restart_autoneg(dev_id, phy_id); - - return rv; -} - -/****************************************************************************** -* -* aquantia_phy_get_eee_advertisement -* -* get eee advertisement -*/ -sw_error_t -aquantia_phy_get_eee_adv(a_uint32_t dev_id, a_uint32_t phy_id, - a_uint32_t *adv) -{ - a_uint16_t phy_data = 0; - sw_error_t rv = SW_OK; - - *adv = 0; - rv = aquantia_phy_reg_read(dev_id, phy_id, AQUANTIA_MMD_AUTONEG, - AQUANTIA_EEE_ADVERTISTMENT_REGISTER, &phy_data); - SW_RTN_ON_ERROR(rv); - - if (phy_data & AQUANTIA_EEE_ADV_1000M) { - *adv |= FAL_PHY_EEE_1000BASE_T; - } - if (phy_data & AQUANTIA_EEE_ADV_10000M){ - *adv |= FAL_PHY_EEE_10000BASE_T; - } - phy_data = 0; - rv = aquantia_phy_reg_read(dev_id, phy_id, AQUANTIA_MMD_AUTONEG, - AQUANTIA_EEE_ADVERTISTMENT_REGISTER1, &phy_data); - SW_RTN_ON_ERROR(rv); - - if (phy_data & AQUANTIA_EEE_ADV_2500M) { - *adv |= FAL_PHY_EEE_2500BASE_T; - } - if (phy_data & AQUANTIA_EEE_ADV_5000M) { - *adv |= FAL_PHY_EEE_5000BASE_T; - } - - return rv; -} -/****************************************************************************** -* -* aquantia_phy_get_eee_partner_advertisement -* -* get eee partner advertisement -*/ -sw_error_t -aquantia_phy_get_eee_partner_adv(a_uint32_t dev_id, a_uint32_t phy_id, - a_uint32_t *adv) -{ - a_uint16_t phy_data = 0; - sw_error_t rv = SW_OK; - - *adv = 0; - rv = aquantia_phy_reg_read(dev_id, phy_id, AQUANTIA_MMD_AUTONEG, - AQUANTIA_EEE_PARTNER_ADVERTISTMENT_REGISTER, &phy_data); - SW_RTN_ON_ERROR(rv); - - if (phy_data & AQUANTIA_EEE_PARTNER_ADV_1000M) { - *adv |= FAL_PHY_EEE_1000BASE_T; - } - if (phy_data & AQUANTIA_EEE_PARTNER_ADV_10000M){ - *adv |= FAL_PHY_EEE_10000BASE_T; - } - phy_data = 0; - rv = aquantia_phy_reg_read(dev_id, phy_id, AQUANTIA_MMD_AUTONEG, - AQUANTIA_EEE_PARTNER_ADVERTISTMENT_REGISTER1, &phy_data); - SW_RTN_ON_ERROR(rv); - - if (phy_data & AQUANTIA_EEE_PARTNER_ADV_2500M) { - *adv |= FAL_PHY_EEE_2500BASE_T; - } - if (phy_data & AQUANTIA_EEE_PARTNER_ADV_5000M) { - *adv |= FAL_PHY_EEE_5000BASE_T; - } - - return rv; -} -/****************************************************************************** -* -* aquantia_phy_get_eee_capability -* -* get eee capability -*/ -sw_error_t -aquantia_phy_get_eee_cap(a_uint32_t dev_id, a_uint32_t phy_id, - a_uint32_t *cap) -{ - a_uint16_t phy_data = 0; - sw_error_t rv = SW_OK; - - *cap = 0; - rv = aquantia_phy_reg_read(dev_id, phy_id, AQUANTIA_MMD_PCS_REGISTERS, - AQUANTIA_EEE_CAPABILITY_REGISTER, &phy_data); - SW_RTN_ON_ERROR(rv); - - if (phy_data & AQUANTIA_EEE_CAPABILITY_1000M) { - *cap |= FAL_PHY_EEE_1000BASE_T; - } - if (phy_data & AQUANTIA_EEE_CAPABILITY_10000M){ - *cap |= FAL_PHY_EEE_10000BASE_T; - } - phy_data = 0; - rv = aquantia_phy_reg_read(dev_id, phy_id, AQUANTIA_MMD_PCS_REGISTERS, - AQUANTIA_EEE_CAPABILITY_REGISTER1, &phy_data); - SW_RTN_ON_ERROR(rv); - - if (phy_data & AQUANTIA_EEE_CAPABILITY_2500M) { - *cap |= FAL_PHY_EEE_2500BASE_T; - } - if (phy_data & AQUANTIA_EEE_CAPABILITY_5000M) { - *cap |= FAL_PHY_EEE_5000BASE_T; - } - - return rv; -} -/****************************************************************************** -* -* aquantia_phy_get_eee_status -* -* get eee status -*/ -sw_error_t -aquantia_phy_get_eee_status(a_uint32_t dev_id, a_uint32_t phy_id, - a_uint32_t *status) -{ - a_uint32_t adv = 0, lp_adv = 0; - sw_error_t rv = SW_OK; - - rv = aquantia_phy_get_eee_adv(dev_id, phy_id, &adv); - SW_RTN_ON_ERROR(rv); - - rv = aquantia_phy_get_eee_partner_adv(dev_id, phy_id, &lp_adv); - SW_RTN_ON_ERROR(rv); - - *status = (adv & lp_adv); - - return rv; -} - -/****************************************************************************** -* -* aquantia_phy_hw_register init to avoid packet loss -* -*/ -sw_error_t -aquantia_phy_hw_init(a_uint32_t dev_id, a_uint32_t port_bmp) -{ - a_uint16_t phy_data = 0; - a_uint32_t port_id = 0, phy_addr = 0; - sw_error_t rv = SW_OK; - - for (port_id = 0; port_id < SW_MAX_NR_PORT; port_id ++) - { - if (port_bmp & (0x1 << port_id)) - { - phy_addr = qca_ssdk_port_to_phy_addr(dev_id, port_id); - /*set auto neg of aq*/ - rv = aquantia_phy_reg_read(dev_id, phy_addr, AQUANTIA_MMD_PHY_XS_REGISTERS, - AQUANTIA_PHY_XS_USX_TRANSMIT, &phy_data); - SW_RTN_ON_ERROR(rv); - phy_data |= AQUANTIA_PHY_USX_AUTONEG_ENABLE; - rv = aquantia_phy_reg_write(dev_id, phy_addr, AQUANTIA_MMD_PHY_XS_REGISTERS, - AQUANTIA_PHY_XS_USX_TRANSMIT,phy_data); - SW_RTN_ON_ERROR(rv); - /*config interrupt of aq*/ - rv = aquantia_phy_reg_read(dev_id, phy_addr, AQUANTIA_MMD_AUTONEG, - AQUANTIA_AUTONEG_TRANSMIT_VENDOR_INTR_MASK, &phy_data); - SW_RTN_ON_ERROR(rv); - phy_data |= AQUANTIA_INTR_LINK_STATUS_CHANGE; - rv = aquantia_phy_reg_write(dev_id, phy_addr, AQUANTIA_MMD_AUTONEG, - AQUANTIA_AUTONEG_TRANSMIT_VENDOR_INTR_MASK, phy_data); - SW_RTN_ON_ERROR(rv); - rv = aquantia_phy_reg_read(dev_id, phy_addr, AQUANTIA_MMD_GLOBAL_REGISTERS, - AQUANTIA_GLOBAL_INTR_STANDARD_MASK, &phy_data); - SW_RTN_ON_ERROR(rv); - phy_data |= AQUANTIA_ALL_VENDOR_ALARMS_INTR_MASK; - rv = aquantia_phy_reg_write(dev_id, phy_addr, AQUANTIA_MMD_GLOBAL_REGISTERS, - AQUANTIA_GLOBAL_INTR_STANDARD_MASK, phy_data); - SW_RTN_ON_ERROR(rv); - rv = aquantia_phy_reg_read(dev_id, phy_addr, AQUANTIA_MMD_GLOBAL_REGISTERS, - AQUANTIA_GLOBAL_INTR_VENDOR_MASK, &phy_data); - SW_RTN_ON_ERROR(rv); - phy_data |= AQUANTIA_AUTO_AND_ALARMS_INTR_MASK; - rv = aquantia_phy_reg_write(dev_id, phy_addr, AQUANTIA_MMD_GLOBAL_REGISTERS, - AQUANTIA_GLOBAL_INTR_VENDOR_MASK, phy_data); - SW_RTN_ON_ERROR(rv); - - /* config aq phy ACT and LINK led behavior*/ - phy_data = AQUANTIA_ACT_LED_VALUE; - rv = aquantia_phy_reg_write(dev_id, phy_addr, AQUANTIA_MMD_GLOBAL_REGISTERS, - AQUANTIA_ACT_LED_STATUS, phy_data); - SW_RTN_ON_ERROR(rv); - phy_data = AQUANTIA_LINK_LED_VALUE; - rv = aquantia_phy_reg_write(dev_id, phy_addr, AQUANTIA_MMD_GLOBAL_REGISTERS, - AQUANTIA_LINK_LED_STATUS, phy_data); - SW_RTN_ON_ERROR(rv); - /*add all ability of aq phy*/ - rv = aquantia_phy_set_autoneg_adv(dev_id, phy_addr, - FAL_PHY_ADV_XGE_SPEED_ALL | FAL_PHY_ADV_100TX_FD | - FAL_PHY_ADV_1000T_FD); - SW_RTN_ON_ERROR(rv); -#if 0 - rv = aquantia_phy_set_eee_adv(dev_id, phy_addr, FAL_PHY_EEE_1000BASE_T - | FAL_PHY_EEE_2500BASE_T | FAL_PHY_EEE_5000BASE_T | - FAL_PHY_EEE_10000BASE_T); - SW_RTN_ON_ERROR(rv); -#endif - } - } - - return rv; -} - -static int aquantia_phy_api_ops_init(void) -{ - int ret; - hsl_phy_ops_t *aquantia_phy_api_ops = NULL; - - aquantia_phy_api_ops = kzalloc(sizeof(hsl_phy_ops_t), GFP_KERNEL); - if (aquantia_phy_api_ops == NULL) { - SSDK_ERROR("aquantia phy ops kzalloc failed!\n"); - return -ENOMEM; - } - - phy_api_ops_init(AQUANTIA_PHY_CHIP); - - aquantia_phy_api_ops->phy_speed_get = aquantia_phy_get_speed; - aquantia_phy_api_ops->phy_speed_set = aquantia_phy_set_speed; - aquantia_phy_api_ops->phy_duplex_get = aquantia_phy_get_duplex; - aquantia_phy_api_ops->phy_duplex_set = aquantia_phy_set_duplex; - aquantia_phy_api_ops->phy_autoneg_enable_set = aquantia_phy_enable_autoneg; - aquantia_phy_api_ops->phy_restart_autoneg = aquantia_phy_restart_autoneg; - aquantia_phy_api_ops->phy_autoneg_status_get = aquantia_phy_autoneg_status; - aquantia_phy_api_ops->phy_autoneg_adv_set = aquantia_phy_set_autoneg_adv; - aquantia_phy_api_ops->phy_autoneg_adv_get = aquantia_phy_get_autoneg_adv; -#ifndef IN_PORTCONTROL_MINI - aquantia_phy_api_ops->phy_powersave_set = aquantia_phy_set_powersave; - aquantia_phy_api_ops->phy_powersave_get = aquantia_phy_get_powersave; - aquantia_phy_api_ops->phy_8023az_set = aquantia_phy_set_8023az; - aquantia_phy_api_ops->phy_8023az_get = aquantia_phy_get_8023az; -#endif - aquantia_phy_api_ops->phy_power_on = aquantia_phy_poweron; - aquantia_phy_api_ops->phy_power_off = aquantia_phy_poweroff; -#ifndef IN_PORTCONTROL_MINI - aquantia_phy_api_ops->phy_cdt = aquantia_phy_cdt; -#endif - aquantia_phy_api_ops->phy_link_status_get = aquantia_phy_get_link_status; -#ifndef IN_PORTCONTROL_MINI - aquantia_phy_api_ops->phy_mdix_set = aquantia_phy_set_mdix; - aquantia_phy_api_ops->phy_mdix_get = aquantia_phy_get_mdix; - aquantia_phy_api_ops->phy_mdix_status_get = aquantia_phy_get_mdix_status; - aquantia_phy_api_ops->phy_local_loopback_set = aquantia_phy_set_local_loopback; - aquantia_phy_api_ops->phy_local_loopback_get = aquantia_phy_get_local_loopback; - aquantia_phy_api_ops->phy_remote_loopback_set = aquantia_phy_set_remote_loopback; - aquantia_phy_api_ops->phy_remote_loopback_get = aquantia_phy_get_remote_loopback; - aquantia_phy_api_ops->phy_reset = aquantia_phy_reset; - aquantia_phy_api_ops->phy_wol_status_set = aquantia_phy_set_wol_status; - aquantia_phy_api_ops->phy_wol_status_get = aquantia_phy_get_wol_status; - aquantia_phy_api_ops->phy_magic_frame_mac_get = aquantia_phy_get_magic_frame_mac; - aquantia_phy_api_ops->phy_magic_frame_mac_set = aquantia_phy_set_magic_frame_mac; - aquantia_phy_api_ops->phy_intr_mask_set = aquantia_phy_intr_mask_set; - aquantia_phy_api_ops->phy_intr_mask_get = aquantia_phy_intr_mask_get; - aquantia_phy_api_ops->phy_id_get = aquantia_phy_get_phy_id; -#endif - aquantia_phy_api_ops->phy_interface_mode_set = aquantia_phy_interface_set_mode; - aquantia_phy_api_ops->phy_interface_mode_status_get=aquantia_phy_interface_get_mode_status; - aquantia_phy_api_ops->phy_get_status = aquantia_phy_get_status; -#ifndef IN_PORTCONTROL_MINI - aquantia_phy_api_ops->phy_counter_show = aquantia_phy_show_counter; -#endif - aquantia_phy_api_ops->phy_eee_adv_set = aquantia_phy_set_eee_adv; - aquantia_phy_api_ops->phy_eee_adv_get = aquantia_phy_get_eee_adv; - aquantia_phy_api_ops->phy_eee_partner_adv_get = aquantia_phy_get_eee_partner_adv; - aquantia_phy_api_ops->phy_eee_cap_get = aquantia_phy_get_eee_cap; - aquantia_phy_api_ops->phy_eee_status_get = aquantia_phy_get_eee_status; - ret = hsl_phy_api_ops_register(AQUANTIA_PHY_CHIP, aquantia_phy_api_ops); - if (ret == 0) - SSDK_INFO("qca probe aquantia phy driver succeeded!\n"); - else - SSDK_ERROR("qca probe aquantia phy driver failed! (code: %d)\n", ret); - - return ret; -} - -/****************************************************************************** -* -* aquantia_phy_init - -* -*/ -int aquantia_phy_init(a_uint32_t dev_id, a_uint32_t port_bmp) -{ - static a_uint32_t phy_ops_flag = 0; - - if(phy_ops_flag == 0) { - aquantia_phy_api_ops_init(); - phy_ops_flag = 1; - } - aquantia_phy_hw_init(dev_id, port_bmp); - - return 0; - -} - diff --git a/feeds/ipq807x/qca-ssdk/src/src/hsl/phy/f1_phy.c b/feeds/ipq807x/qca-ssdk/src/src/hsl/phy/f1_phy.c deleted file mode 100755 index b3017b00d..000000000 --- a/feeds/ipq807x/qca-ssdk/src/src/hsl/phy/f1_phy.c +++ /dev/null @@ -1,1534 +0,0 @@ -/* - * Copyright (c) 2012, 2015-2018, The Linux Foundation. All rights reserved. - * Permission to use, copy, modify, and/or distribute this software for - * any purpose with or without fee is hereby granted, provided that the - * above copyright notice and this permission notice appear in all copies. - * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES - * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR - * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES - * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN - * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT - * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. - */ - -#include "sw.h" -#include "fal_port_ctrl.h" -#include "hsl_api.h" -#include "hsl.h" -#include "f1_phy.h" -#include "hsl_phy.h" -#include "ssdk_plat.h" - -static a_uint16_t -_phy_reg_read(a_uint32_t dev_id, a_uint32_t phy_addr, a_uint32_t reg) -{ - sw_error_t rv; - a_uint16_t val = 0; - - HSL_PHY_GET(rv, dev_id, phy_addr, reg, &val); - if (SW_OK != rv) - return 0xFFFF; - - return val; -} - -static sw_error_t -_phy_reg_write(a_uint32_t dev_id, a_uint32_t phy_addr, a_uint32_t reg, - a_uint16_t val) -{ - sw_error_t rv; - - HSL_PHY_SET(rv, dev_id, phy_addr, reg, val); - - return rv; -} - -/* #define f1_phy_reg_read _phy_reg_read */ -/* #define f1_phy_reg_write _phy_reg_write */ - -/****************************************************************************** -* -* f1_phy_mii_read - mii register read -* -* mil register read -*/ -a_uint16_t -f1_phy_reg_read(a_uint32_t dev_id, a_uint32_t phy_id, a_uint32_t reg_id) -{ - return _phy_reg_read(dev_id, phy_id, reg_id); - -} - -/****************************************************************************** -* -* f1_phy_reg_write - mii register write -* -* mii register write -*/ -sw_error_t -f1_phy_reg_write(a_uint32_t dev_id, a_uint32_t phy_id, a_uint32_t reg_id, - a_uint16_t reg_val) -{ - - _phy_reg_write(dev_id,phy_id, reg_id, reg_val); - - return SW_OK; -} - - -/****************************************************************************** -* -* f1_phy_debug_write - debug port write -* -* debug port write -*/ -sw_error_t -f1_phy_debug_write(a_uint32_t dev_id, a_uint32_t phy_id, a_uint16_t reg_id, - a_uint16_t reg_val) -{ - f1_phy_reg_write(dev_id, phy_id, F1_DEBUG_PORT_ADDRESS, reg_id); - f1_phy_reg_write(dev_id, phy_id, F1_DEBUG_PORT_DATA, reg_val); - - return SW_OK; -} - -/****************************************************************************** -* -* f1_phy_debug_read - debug port read -* -* debug port read -*/ -a_uint16_t -f1_phy_debug_read(a_uint32_t dev_id, a_uint32_t phy_id, a_uint16_t reg_id) -{ - f1_phy_reg_write(dev_id, phy_id, F1_DEBUG_PORT_ADDRESS, reg_id); - return f1_phy_reg_read(dev_id, phy_id, F1_DEBUG_PORT_DATA); -} - -/****************************************************************************** -* -* f1_phy_mmd_write - PHY MMD register write -* -* PHY MMD register write -*/ -sw_error_t -f1_phy_mmd_write(a_uint32_t dev_id, a_uint32_t phy_id, - a_uint16_t mmd_num, - a_uint16_t reg_id, - a_uint16_t reg_val) -{ - f1_phy_reg_write(dev_id, phy_id, F1_MMD_CTRL_REG, mmd_num); - f1_phy_reg_write(dev_id, phy_id, F1_MMD_DATA_REG, reg_id); - f1_phy_reg_write(dev_id, phy_id, F1_MMD_CTRL_REG, 0x4000|mmd_num); - f1_phy_reg_write(dev_id, phy_id, F1_MMD_DATA_REG, reg_val); - - return SW_OK; -} - -/****************************************************************************** -* -* f1_phy_mmd_read - PHY MMD register read -* -* PHY MMD register read -*/ -a_uint16_t -f1_phy_mmd_read(a_uint32_t dev_id, a_uint32_t phy_id, - a_uint16_t mmd_num, - a_uint16_t reg_id) -{ - f1_phy_reg_write(dev_id, phy_id, F1_MMD_CTRL_REG, mmd_num); - f1_phy_reg_write(dev_id, phy_id, F1_MMD_DATA_REG, reg_id); - f1_phy_reg_write(dev_id, phy_id, F1_MMD_CTRL_REG, 0x4000|mmd_num); - - return f1_phy_reg_read(dev_id, phy_id, F1_MMD_DATA_REG); -} - - -/****************************************************************************** -* -* f1_phy_set_powersave - set power saving status -* -* set power saving status -*/ -sw_error_t -f1_phy_set_powersave(a_uint32_t dev_id, a_uint32_t phy_id, a_bool_t enable) -{ - a_uint16_t phy_data; - f1_phy_reg_write(dev_id, phy_id, F1_DEBUG_PORT_ADDRESS, 0x29); - phy_data = f1_phy_reg_read(dev_id, phy_id, F1_DEBUG_PORT_DATA); - - if(enable == A_TRUE) - { - phy_data |= 0x8000; - } - else - { - phy_data &= ~0x8000; - } - - f1_phy_reg_write(dev_id, phy_id, F1_DEBUG_PORT_DATA, phy_data); - - return SW_OK; -} - -/****************************************************************************** -* -* f1_phy_get_powersave - get power saving status -* -* set power saving status -*/ -sw_error_t -f1_phy_get_powersave(a_uint32_t dev_id, a_uint32_t phy_id, a_bool_t *enable) -{ - a_uint16_t phy_data; - *enable = A_FALSE; - - f1_phy_reg_write(dev_id, phy_id, F1_DEBUG_PORT_ADDRESS, 0x29); - phy_data = f1_phy_reg_read(dev_id, phy_id, F1_DEBUG_PORT_DATA); - - if(phy_data & 0x8000) - *enable = A_TRUE; - - return SW_OK; -} - -/****************************************************************************** -* -* f1_phy_set_hibernate - set hibernate status -* -* set hibernate status -*/ -sw_error_t -f1_phy_set_hibernate(a_uint32_t dev_id, a_uint32_t phy_id, a_bool_t enable) -{ - a_uint16_t phy_data; - f1_phy_reg_write(dev_id, phy_id, F1_DEBUG_PORT_ADDRESS, 0xb); - phy_data = f1_phy_reg_read(dev_id, phy_id, F1_DEBUG_PORT_DATA); - - if(enable == A_TRUE) - { - phy_data |= 0x8000; - } - else - { - phy_data &= ~0x8000; - } - - f1_phy_reg_write(dev_id, phy_id, F1_DEBUG_PORT_DATA, phy_data); - - return SW_OK; -} - -/****************************************************************************** -* -* f1_phy_get_hibernate - get hibernate status -* -* get hibernate status -*/ -sw_error_t -f1_phy_get_hibernate(a_uint32_t dev_id, a_uint32_t phy_id, a_bool_t *enable) -{ - a_uint16_t phy_data; - *enable = A_FALSE; - - f1_phy_reg_write(dev_id, phy_id, F1_DEBUG_PORT_ADDRESS, 0xb); - phy_data = f1_phy_reg_read(dev_id, phy_id, F1_DEBUG_PORT_DATA); - - if(phy_data & 0x8000) - *enable = A_TRUE; - - return SW_OK; -} - -/****************************************************************************** -* -* f1_phy_cdt - cable diagnostic test -* -* cable diagnostic test -*/ -#ifdef ISISC -#define RUN_CDT 0x8000 -#define CABLE_LENGTH_UNIT 0x0400 -sw_error_t f1_phy_reset(a_uint32_t dev_id, a_uint32_t phy_id); -a_bool_t f1_phy_reset_done(a_uint32_t dev_id, a_uint32_t phy_id); -a_bool_t f1_phy_get_link_status(a_uint32_t dev_id, a_uint32_t phy_id); - -static inline fal_cable_status_t -_fal_cdt_status_mapping(a_uint16_t status) -{ - fal_cable_status_t status_mapping = FAL_CABLE_STATUS_INVALID; - - if (0 == status) - status_mapping = FAL_CABLE_STATUS_INVALID; - else if (1 == status) - status_mapping = FAL_CABLE_STATUS_NORMAL; - else if (2 == status) - status_mapping = FAL_CABLE_STATUS_OPENED; - else if (3 == status) - status_mapping = FAL_CABLE_STATUS_SHORT; - - return status_mapping; -} - -static sw_error_t -f1_phy_cdt_start(a_uint32_t dev_id, a_uint32_t phy_id) -{ - a_uint16_t status = 0; - a_uint16_t ii = 100; - - /* RUN CDT */ - f1_phy_reg_write(dev_id, phy_id, F1_PHY_CDT_CONTROL, RUN_CDT|CABLE_LENGTH_UNIT); - do - { - aos_mdelay(30); - status = f1_phy_reg_read(dev_id, phy_id, F1_PHY_CDT_CONTROL); - } - while ((status & RUN_CDT) && (--ii)); - - return SW_OK; -} - -sw_error_t -f1_phy_cdt_get(a_uint32_t dev_id, a_uint32_t phy_id, fal_port_cdt_t *port_cdt) -{ - a_uint16_t status = 0; - a_uint16_t cable_delta_time = 0; - a_uint16_t org_debug_value = 0; - int ii = 100; - a_bool_t link_st = A_FALSE; - a_uint16_t reg806e = 0; - int i; - - if((!port_cdt) || (phy_id > 4)) - { - return SW_FAIL; - } - - /*disable clock gating*/ - org_debug_value = f1_phy_debug_read(dev_id, phy_id, 0x3f); - f1_phy_debug_write(dev_id, phy_id, 0x3f, 0); - - f1_phy_cdt_start(dev_id, phy_id); - - /* Get cable status */ - status = f1_phy_mmd_read(dev_id, phy_id, 3, 0x8064); - - /* Workaround for cable lenth less than 20M */ - port_cdt->pair_c_status = (status >> 4) & 0x3; - /* Get Cable Length value */ - cable_delta_time = f1_phy_mmd_read(dev_id, phy_id, 3, 0x8067); - /* the actual cable length equals to CableDeltaTime * 0.824*/ - port_cdt->pair_c_len = (cable_delta_time * 824) /1000; - if ((1 == port_cdt->pair_c_status) && - (port_cdt->pair_c_len > 0) && (port_cdt->pair_c_len <= 20)) - { - reg806e = f1_phy_mmd_read(dev_id, phy_id, 3, 0x806e); - f1_phy_mmd_write(dev_id, phy_id, 3, 0x806e, reg806e & (~0x8000)); - - f1_phy_reset(dev_id, phy_id); - f1_phy_reset_done(dev_id, phy_id); - do - { - link_st = f1_phy_get_link_status(dev_id, phy_id); - aos_mdelay(100); - } while ((A_FALSE == link_st) && (--ii)); - - f1_phy_cdt_start(dev_id, phy_id); - /* Get cable status */ - status = f1_phy_mmd_read(dev_id, phy_id, 3, 0x8064); - } - - for (i=0;i<4;i++) - { - switch(i) - { - case 0: - port_cdt->pair_a_status = (status >> 12) & 0x3; - /* Get Cable Length value */ - cable_delta_time = f1_phy_mmd_read(dev_id, phy_id, 3, 0x8065); - /* the actual cable length equals to CableDeltaTime * 0.824*/ - port_cdt->pair_a_len = (cable_delta_time * 824) /1000; - - break; - case 1: - port_cdt->pair_b_status = (status >> 8) & 0x3; - /* Get Cable Length value */ - cable_delta_time = f1_phy_mmd_read(dev_id, phy_id, 3, 0x8066); - /* the actual cable length equals to CableDeltaTime * 0.824*/ - port_cdt->pair_b_len = (cable_delta_time * 824) /1000; - break; - case 2: - port_cdt->pair_c_status = (status >> 4) & 0x3; - /* Get Cable Length value */ - cable_delta_time = f1_phy_mmd_read(dev_id, phy_id, 3, 0x8067); - /* the actual cable length equals to CableDeltaTime * 0.824*/ - port_cdt->pair_c_len = (cable_delta_time * 824) /1000; - break; - case 3: - port_cdt->pair_d_status = status & 0x3; - /* Get Cable Length value */ - cable_delta_time = f1_phy_mmd_read(dev_id, phy_id, 3, 0x8068); - /* the actual cable length equals to CableDeltaTime * 0.824*/ - port_cdt->pair_d_len = (cable_delta_time * 824) /1000; - break; - default: - break; - } - } - - /*restore debug port value*/ - f1_phy_debug_write(dev_id, phy_id, 0x3f, org_debug_value); - - return SW_OK; -} - -sw_error_t -f1_phy_cdt(a_uint32_t dev_id, a_uint32_t phy_id, a_uint32_t mdi_pair, - fal_cable_status_t *cable_status, a_uint32_t *cable_len) -{ - fal_port_cdt_t f1_port_cdt; - - if((mdi_pair >= 4) || (phy_id > 4)) - { - //There are only 4 mdi pairs in 1000BASE-T - return SW_BAD_PARAM; - } - - f1_phy_cdt_get(dev_id, phy_id, &f1_port_cdt); - - switch(mdi_pair) - { - case 0: - *cable_status = _fal_cdt_status_mapping(f1_port_cdt.pair_a_status); - /* Get Cable Length value */ - *cable_len = f1_port_cdt.pair_a_len; - break; - case 1: - *cable_status = _fal_cdt_status_mapping(f1_port_cdt.pair_b_status); - /* Get Cable Length value */ - *cable_len = f1_port_cdt.pair_b_len; - break; - case 2: - *cable_status = _fal_cdt_status_mapping(f1_port_cdt.pair_c_status); - /* Get Cable Length value */ - *cable_len = f1_port_cdt.pair_c_len; - break; - case 3: - *cable_status = _fal_cdt_status_mapping(f1_port_cdt.pair_d_status); - /* Get Cable Length value */ - *cable_len = f1_port_cdt.pair_d_len; - break; - default: - break; - } - - return SW_OK; -} -#else -sw_error_t -f1_phy_cdt(a_uint32_t dev_id, a_uint32_t phy_id, a_uint32_t mdi_pair, - fal_cable_status_t *cable_status, a_uint32_t *cable_len) -{ - a_uint16_t status = 0; - a_uint16_t ii = 100; - a_uint16_t org_debug_value; - a_uint16_t cable_delta_time; - - if(!cable_status || !cable_len) - { - return SW_FAIL; - } - - if(mdi_pair >= 4) - { - //There are only 4 mdi pairs in 1000BASE-T - return SW_BAD_PARAM; - } - - org_debug_value = f1_phy_debug_read(dev_id, phy_id, 0x3f); - - /*disable clock gating*/ - f1_phy_debug_write(dev_id, phy_id, 0x3f, 0); - f1_phy_reg_write(dev_id, phy_id, F1_PHY_CDT_CONTROL, (mdi_pair << 8) | 0x0001); - - do - { - aos_mdelay(30); - status = f1_phy_reg_read(dev_id, phy_id, F1_PHY_CDT_CONTROL); - } - while ((status & 0x0001) && (--ii)); - - status = f1_phy_reg_read(dev_id, phy_id, F1_PHY_CDT_STATUS); - - *cable_status = (status&0x300) >> 8; - if ( (*cable_status == 1) || (*cable_status == 2)) - { - if ( mdi_pair == 1 || mdi_pair == 3 ) - { - /*Reverse the mdi status for channel 1 and channel 3*/ - *cable_status = (~(*cable_status)) & 0x3; - } - } - - /* the actual cable length equals to CableDeltaTime * 0.824*/ - cable_delta_time = status & 0xff; - *cable_len = (cable_delta_time * 824) /1000; - - /*restore debug port value*/ - f1_phy_debug_write(dev_id, phy_id, 0x3f, org_debug_value); - //f1_phy_reg_write(dev_id, phy_id, 0x00, 0x9000);//Reset the PHY if necessary - - return SW_OK; -} -#endif - -/****************************************************************************** -* -* f1_phy_reset_done - reset the phy -* -* reset the phy -*/ -a_bool_t -f1_phy_reset_done(a_uint32_t dev_id, a_uint32_t phy_id) -{ - a_uint16_t phy_data; - a_uint16_t ii = 200; - - do - { - phy_data = f1_phy_reg_read(dev_id, phy_id, F1_PHY_CONTROL); - aos_mdelay(10); - } - while ((!F1_RESET_DONE(phy_data)) && --ii); - - if (ii == 0) - return A_FALSE; - - return A_TRUE; -} - -/****************************************************************************** -* -* f1_autoneg_done -* -* f1_autoneg_done -*/ -a_bool_t -f1_autoneg_done(a_uint32_t dev_id, a_uint32_t phy_id) -{ - a_uint16_t phy_data; - a_uint16_t ii = 200; - - do - { - phy_data = f1_phy_reg_read(dev_id, phy_id, F1_PHY_STATUS); - aos_mdelay(10); - } - while ((!F1_AUTONEG_DONE(phy_data)) && --ii); - - if (ii == 0) - return A_FALSE; - - return A_TRUE; -} - -/****************************************************************************** -* -* f1_phy_Speed_Duplex_Resolved - - reset the phy -* -* reset the phy -*/ -a_bool_t -f1_phy_speed_duplex_resolved(a_uint32_t dev_id, a_uint32_t phy_id) -{ - a_uint16_t phy_data; - a_uint16_t ii = 200; - - do - { - phy_data = f1_phy_reg_read(dev_id, phy_id, F1_PHY_SPEC_STATUS); - aos_mdelay(10); - } - while ((!F1_SPEED_DUPLEX_RESOVLED(phy_data)) && --ii); - - if (ii == 0) - return A_FALSE; - - return A_TRUE; -} - -/****************************************************************************** -* -* f1_phy_reset - reset the phy -* -* reset the phy -*/ -sw_error_t -f1_phy_reset(a_uint32_t dev_id, a_uint32_t phy_id) -{ - a_uint16_t phy_data; - - phy_data = f1_phy_reg_read(dev_id, phy_id, F1_PHY_CONTROL); - f1_phy_reg_write(dev_id, phy_id, F1_PHY_CONTROL, - phy_data | F1_CTRL_SOFTWARE_RESET); - - return SW_OK; -} - -/****************************************************************************** -* -* f1_phy_off - power off the phy to change its speed -* -* Power off the phy -*/ -sw_error_t -f1_phy_poweroff(a_uint32_t dev_id, a_uint32_t phy_id) -{ - a_uint16_t phy_data; - - phy_data = f1_phy_reg_read(dev_id, phy_id, F1_PHY_CONTROL); - f1_phy_reg_write(dev_id, phy_id, F1_PHY_CONTROL, - phy_data | F1_CTRL_POWER_DOWN); - - return SW_OK; -} - -/****************************************************************************** -* -* f1_phy_on - power on the phy after speed changed -* -* Power on the phy -*/ -sw_error_t -f1_phy_poweron(a_uint32_t dev_id, a_uint32_t phy_id) -{ - a_uint16_t phy_data; - - phy_data = f1_phy_reg_read(dev_id, phy_id, F1_PHY_CONTROL); - f1_phy_reg_write(dev_id, phy_id, F1_PHY_CONTROL, - phy_data & ~F1_CTRL_POWER_DOWN); - - aos_mdelay(200); - - return SW_OK; -} - -/****************************************************************************** -* -* f1_phy_get_ability - get the phy ability -* -* -*/ -sw_error_t -f1_phy_get_ability(a_uint32_t dev_id, a_uint32_t phy_id, - a_uint32_t * ability) -{ - a_uint16_t phy_data; - - *ability = 0; - phy_data = f1_phy_reg_read(dev_id, phy_id, F1_PHY_STATUS); - - if (phy_data & F1_STATUS_AUTONEG_CAPS) - *ability |= FAL_PHY_AUTONEG_CAPS; - - if (phy_data & F1_STATUS_100T2_HD_CAPS) - *ability |= FAL_PHY_100T2_HD_CAPS; - - if (phy_data & F1_STATUS_100T2_FD_CAPS) - *ability |= FAL_PHY_100T2_FD_CAPS; - - if (phy_data & F1_STATUS_10T_HD_CAPS) - *ability |= FAL_PHY_10T_HD_CAPS; - - if (phy_data & F1_STATUS_10T_FD_CAPS) - *ability |= FAL_PHY_10T_FD_CAPS; - - if (phy_data & F1_STATUS_100X_HD_CAPS) - *ability |= FAL_PHY_100X_HD_CAPS; - - if (phy_data & F1_STATUS_100X_FD_CAPS) - *ability |= FAL_PHY_100X_FD_CAPS; - - if (phy_data & F1_STATUS_100T4_CAPS) - *ability |= FAL_PHY_100T4_CAPS; - - if (phy_data & F1_STATUS_EXTENDED_STATUS) - { - phy_data = f1_phy_reg_read(dev_id, phy_id, F1_EXTENDED_STATUS); - - if (phy_data & F1_STATUS_1000T_FD_CAPS) - { - *ability |= FAL_PHY_1000T_FD_CAPS; - } - - if (phy_data & F1_STATUS_1000X_FD_CAPS) - { - *ability |= FAL_PHY_1000X_FD_CAPS; - } - } - - return SW_OK; -} - -/****************************************************************************** -* -* f1_phy_get_ability - get the phy ability -* -* -*/ -sw_error_t -f1_phy_get_partner_ability(a_uint32_t dev_id, a_uint32_t phy_id, - a_uint32_t * ability) -{ - a_uint16_t phy_data; - - *ability = 0; - phy_data = f1_phy_reg_read(dev_id, phy_id, F1_LINK_PARTNER_ABILITY); - - if (phy_data & F1_LINK_10BASETX_HALF_DUPLEX) - *ability |= FAL_PHY_PART_10T_HD; - - if (phy_data & F1_LINK_10BASETX_FULL_DUPLEX) - *ability |= FAL_PHY_PART_10T_FD; - - if (phy_data & F1_LINK_100BASETX_HALF_DUPLEX) - *ability |= FAL_PHY_PART_100TX_HD; - - if (phy_data & F1_LINK_100BASETX_FULL_DUPLEX) - *ability |= FAL_PHY_PART_100TX_FD; - - if (phy_data & F1_LINK_NPAGE) - { - phy_data = f1_phy_reg_read(dev_id, phy_id, F1_1000BASET_STATUS); - - if (phy_data & F1_LINK_1000BASETX_FULL_DUPLEX) - *ability |= FAL_PHY_PART_1000T_FD; - } - - return SW_OK; -} - -/****************************************************************************** -* -* f1_phy_status - test to see if the specified phy link is alive -* -* RETURNS: -* A_TRUE --> link is alive -* A_FALSE --> link is down -*/ -a_bool_t -f1_phy_get_link_status(a_uint32_t dev_id, a_uint32_t phy_id) -{ - a_uint16_t phy_data; - - phy_data = f1_phy_reg_read(dev_id, phy_id, F1_PHY_SPEC_STATUS); - - if (phy_data & F1_STATUS_LINK_PASS) - return A_TRUE; - - return A_FALSE; -} - -/****************************************************************************** -* -* f1_set_autoneg_adv - set the phy autoneg Advertisement -* -*/ -sw_error_t -f1_phy_set_autoneg_adv(a_uint32_t dev_id, a_uint32_t phy_id, - a_uint32_t autoneg) -{ - a_uint16_t phy_data = 0; - - phy_data = f1_phy_reg_read(dev_id, phy_id, F1_AUTONEG_ADVERT); - phy_data &= ~F1_ADVERTISE_MEGA_ALL; - phy_data &= ~(F1_ADVERTISE_PAUSE | F1_ADVERTISE_ASYM_PAUSE); - - if (autoneg & FAL_PHY_ADV_100TX_FD) - phy_data |= F1_ADVERTISE_100FULL; - - if (autoneg & FAL_PHY_ADV_100TX_HD) - phy_data |= F1_ADVERTISE_100HALF; - - if (autoneg & FAL_PHY_ADV_10T_FD) - phy_data |= F1_ADVERTISE_10FULL; - - if (autoneg & FAL_PHY_ADV_10T_HD) - phy_data |= F1_ADVERTISE_10HALF; - - if (autoneg & FAL_PHY_ADV_PAUSE) - phy_data |= F1_ADVERTISE_PAUSE; - - if (autoneg & FAL_PHY_ADV_ASY_PAUSE) - phy_data |= F1_ADVERTISE_ASYM_PAUSE; - - f1_phy_reg_write(dev_id, phy_id, F1_AUTONEG_ADVERT, phy_data); - - phy_data = f1_phy_reg_read(dev_id, phy_id, F1_1000BASET_CONTROL); - phy_data &= ~F1_ADVERTISE_1000FULL; - phy_data &= ~F1_ADVERTISE_1000HALF; - - if (autoneg & FAL_PHY_ADV_1000T_FD) - phy_data |= F1_ADVERTISE_1000FULL; - - f1_phy_reg_write(dev_id, phy_id, F1_1000BASET_CONTROL, phy_data); - - return SW_OK; -} - -/****************************************************************************** -* -* f1_get_autoneg_adv - get the phy autoneg Advertisement -* -*/ -sw_error_t -f1_phy_get_autoneg_adv(a_uint32_t dev_id, a_uint32_t phy_id, - a_uint32_t * autoneg) -{ - a_uint16_t phy_data = 0; - - *autoneg = 0; - phy_data = f1_phy_reg_read(dev_id, phy_id, F1_AUTONEG_ADVERT); - - if (phy_data & F1_ADVERTISE_100FULL) - *autoneg |= FAL_PHY_ADV_100TX_FD; - - if (phy_data & F1_ADVERTISE_100HALF) - *autoneg |= FAL_PHY_ADV_100TX_HD; - - if (phy_data & F1_ADVERTISE_10FULL) - *autoneg |= FAL_PHY_ADV_10T_FD; - - if (phy_data & F1_ADVERTISE_10HALF) - *autoneg |= FAL_PHY_ADV_10T_HD; - - if (phy_data & F1_ADVERTISE_PAUSE) - *autoneg |= FAL_PHY_ADV_PAUSE; - - if (phy_data & F1_ADVERTISE_ASYM_PAUSE) - *autoneg |= FAL_PHY_ADV_ASY_PAUSE; - - phy_data = f1_phy_reg_read(dev_id, phy_id, F1_1000BASET_CONTROL); - - if (phy_data & F1_ADVERTISE_1000FULL) - *autoneg |= FAL_PHY_ADV_1000T_FD; - - return SW_OK; -} - -/****************************************************************************** -* -* f1_phy_enable_autonego - power off the phy to change its speed -* -* Power off the phy -*/ -a_bool_t -f1_phy_autoneg_status(a_uint32_t dev_id, a_uint32_t phy_id) -{ - a_uint16_t phy_data; - - phy_data = f1_phy_reg_read(dev_id, phy_id, F1_PHY_CONTROL); - - if (phy_data & F1_CTRL_AUTONEGOTIATION_ENABLE) - return A_TRUE; - - return A_FALSE; -} - -/****************************************************************************** -* -* f1_restart_autoneg - restart the phy autoneg -* -*/ -sw_error_t -f1_phy_restart_autoneg(a_uint32_t dev_id, a_uint32_t phy_id) -{ - a_uint16_t phy_data = 0; - - phy_data = f1_phy_reg_read(dev_id, phy_id, F1_PHY_CONTROL); - - phy_data |= F1_CTRL_AUTONEGOTIATION_ENABLE; - f1_phy_reg_write(dev_id, phy_id, F1_PHY_CONTROL, - phy_data | F1_CTRL_RESTART_AUTONEGOTIATION); - - return SW_OK; -} - -/****************************************************************************** -* -* f1_phy_enable_autonego - power off the phy to change its speed -* -* Power off the phy -*/ -sw_error_t -f1_phy_enable_autoneg(a_uint32_t dev_id, a_uint32_t phy_id) -{ - a_uint16_t phy_data = 0; - - phy_data = f1_phy_reg_read(dev_id, phy_id, F1_PHY_CONTROL); - - f1_phy_reg_write(dev_id, phy_id, F1_PHY_CONTROL, - phy_data | F1_CTRL_AUTONEGOTIATION_ENABLE); - - return SW_OK; -} - - -/****************************************************************************** -* -* f1_phy_get_speed - Determines the speed of phy ports associated with the -* specified device. -*/ - -sw_error_t -f1_phy_get_speed(a_uint32_t dev_id, a_uint32_t phy_id, - fal_port_speed_t * speed) -{ - a_uint16_t phy_data; - a_bool_t auto_neg; - - auto_neg = f1_phy_autoneg_status(dev_id, phy_id); - if (A_TRUE == auto_neg ) { - phy_data = f1_phy_reg_read(dev_id, phy_id, F1_PHY_SPEC_STATUS); - switch (phy_data & F1_STATUS_SPEED_MASK) - { - case F1_STATUS_SPEED_1000MBS: - *speed = FAL_SPEED_1000; - break; - case F1_STATUS_SPEED_100MBS: - *speed = FAL_SPEED_100; - break; - case F1_STATUS_SPEED_10MBS: - *speed = FAL_SPEED_10; - break; - default: - return SW_READ_ERROR; - } - } - else - { - phy_data = f1_phy_reg_read(dev_id, phy_id, F1_PHY_CONTROL); - switch (phy_data & F1_CTRL_SPEED_MASK) - { - case F1_CTRL_SPEED_1000: - *speed = FAL_SPEED_1000; - break; - case F1_CTRL_SPEED_100: - *speed = FAL_SPEED_100; - break; - case F1_CTRL_SPEED_10: - *speed = FAL_SPEED_10; - break; - default: - return SW_READ_ERROR; - } - } - return SW_OK; -} - -/****************************************************************************** -* -* f1_phy_set_speed - Determines the speed of phy ports associated with the -* specified device. -*/ -sw_error_t -f1_phy_set_speed(a_uint32_t dev_id, a_uint32_t phy_id, - fal_port_speed_t speed) -{ - a_uint16_t phy_data = 0; - a_uint16_t phy_status = 0; - - a_uint32_t autoneg, oldneg; - fal_port_duplex_t old_duplex; - - if (FAL_SPEED_1000 == speed) - { - phy_data |= F1_CTRL_SPEED_1000; - phy_data |= F1_CTRL_AUTONEGOTIATION_ENABLE; - } - else if (FAL_SPEED_100 == speed) - { - phy_data |= F1_CTRL_SPEED_100; - phy_data &= ~F1_CTRL_AUTONEGOTIATION_ENABLE; - } - else if (FAL_SPEED_10 == speed) - { - phy_data |= F1_CTRL_SPEED_10; - phy_data &= ~F1_CTRL_AUTONEGOTIATION_ENABLE; - } - else - { - return SW_BAD_PARAM; - } - - (void)f1_phy_get_autoneg_adv(dev_id, phy_id, &autoneg); - oldneg = autoneg; - autoneg &= ~FAL_PHY_ADV_GE_SPEED_ALL; - - (void)f1_phy_get_duplex(dev_id, phy_id, &old_duplex); - - if (old_duplex == FAL_FULL_DUPLEX) - { - phy_data |= F1_CTRL_FULL_DUPLEX; - - if (FAL_SPEED_1000 == speed) - { - autoneg |= FAL_PHY_ADV_1000T_FD; - } - else if (FAL_SPEED_100 == speed) - { - autoneg |= FAL_PHY_ADV_100TX_FD; - } - else - { - autoneg |= FAL_PHY_ADV_10T_FD; - } - } - else if (old_duplex == FAL_HALF_DUPLEX) - { - phy_data &= ~F1_CTRL_FULL_DUPLEX; - - if (FAL_SPEED_100 == speed) - { - autoneg |= FAL_PHY_ADV_100TX_HD; - } - else - { - autoneg |= FAL_PHY_ADV_10T_HD; - } - } - else - { - return SW_FAIL; - } - - (void)f1_phy_set_autoneg_adv(dev_id, phy_id, autoneg); - (void)f1_phy_restart_autoneg(dev_id, phy_id); - if(f1_phy_get_link_status(dev_id, phy_id)) - { - do - { - phy_status = f1_phy_reg_read(dev_id, phy_id, F1_PHY_STATUS); - } - while(!F1_AUTONEG_DONE(phy_status)); - } - - f1_phy_reg_write(dev_id, phy_id, F1_PHY_CONTROL, phy_data); - (void)f1_phy_set_autoneg_adv(dev_id, phy_id, oldneg); - - return SW_OK; - -} - -/****************************************************************************** -* -* f1_phy_get_duplex - Determines the speed of phy ports associated with the -* specified device. -*/ -sw_error_t -f1_phy_get_duplex(a_uint32_t dev_id, a_uint32_t phy_id, - fal_port_duplex_t * duplex) -{ - a_uint16_t phy_data; - a_bool_t auto_neg; - - auto_neg = f1_phy_autoneg_status(dev_id, phy_id); - if (A_TRUE == auto_neg ) { - phy_data = f1_phy_reg_read(dev_id, phy_id, F1_PHY_SPEC_STATUS); - - //read duplex - if (phy_data & F1_STATUS_FULL_DUPLEX) - *duplex = FAL_FULL_DUPLEX; - else - *duplex = FAL_HALF_DUPLEX; - } - else - { - phy_data = f1_phy_reg_read(dev_id, phy_id, F1_PHY_CONTROL); - //read duplex - if (phy_data & F1_CTRL_FULL_DUPLEX) - *duplex = FAL_FULL_DUPLEX; - else - *duplex = FAL_HALF_DUPLEX; - } - return SW_OK; -} - -/****************************************************************************** -* -* f1_phy_set_duplex - Determines the speed of phy ports associated with the -* specified device. -*/ -sw_error_t -f1_phy_set_duplex(a_uint32_t dev_id, a_uint32_t phy_id, - fal_port_duplex_t duplex) -{ - a_uint16_t phy_data = 0; - a_uint16_t phy_status = 0; - - fal_port_speed_t old_speed = FAL_SPEED_10; - a_uint32_t oldneg, autoneg; - - if (A_TRUE == f1_phy_autoneg_status(dev_id, phy_id)) - phy_data &= ~F1_CTRL_AUTONEGOTIATION_ENABLE; - - (void)f1_phy_get_autoneg_adv(dev_id, phy_id, &autoneg); - oldneg = autoneg; - autoneg &= ~FAL_PHY_ADV_GE_SPEED_ALL; - (void)f1_phy_get_speed(dev_id, phy_id, &old_speed); - - if (FAL_SPEED_1000 == old_speed) - { - phy_data |= F1_CTRL_SPEED_1000; - phy_data |= F1_CTRL_AUTONEGOTIATION_ENABLE; - } - else if (FAL_SPEED_100 == old_speed) - { - phy_data |= F1_CTRL_SPEED_100; - } - else if (FAL_SPEED_10 == old_speed) - { - phy_data |= F1_CTRL_SPEED_10; - } - else - { - return SW_FAIL; - } - - if (duplex == FAL_FULL_DUPLEX) - { - phy_data |= F1_CTRL_FULL_DUPLEX; - - if (FAL_SPEED_1000 == old_speed) - { - autoneg = FAL_PHY_ADV_1000T_FD; - } - else if (FAL_SPEED_100 == old_speed) - { - autoneg = FAL_PHY_ADV_100TX_FD; - } - else - { - autoneg = FAL_PHY_ADV_10T_FD; - } - } - else if (duplex == FAL_HALF_DUPLEX) - { - phy_data &= ~F1_CTRL_FULL_DUPLEX; - - if (FAL_SPEED_100 == old_speed) - { - autoneg = FAL_PHY_ADV_100TX_HD; - } - else - { - autoneg = FAL_PHY_ADV_10T_HD; - } - } - else - { - return SW_BAD_PARAM; - } - - (void)f1_phy_set_autoneg_adv(dev_id, phy_id, autoneg); - (void)f1_phy_restart_autoneg(dev_id, phy_id); - if(f1_phy_get_link_status(dev_id, phy_id)) - { - do - { - phy_status = f1_phy_reg_read(dev_id, phy_id, F1_PHY_STATUS); - } - while(!F1_AUTONEG_DONE(phy_status)); - } - - f1_phy_reg_write(dev_id, phy_id, F1_PHY_CONTROL, phy_data); - (void)f1_phy_set_autoneg_adv(dev_id, phy_id, oldneg); - - return SW_OK; -} - -/****************************************************************************** -* -* f1_phy_get_phy_id - get the phy id -* -*/ -static sw_error_t -f1_phy_get_phy_id(a_uint32_t dev_id, a_uint32_t phy_id, - a_uint32_t *phy_data) -{ - a_uint16_t org_id, rev_id; - - org_id = f1_phy_reg_read(dev_id, phy_id, F1_PHY_ID1); - rev_id = f1_phy_reg_read(dev_id, phy_id, F1_PHY_ID2); - *phy_data = ((org_id & 0xffff) << 16) | (rev_id & 0xffff); - - return SW_OK; -} - -/****************************************************************************** -* -* f1_phy_intr_mask_set - Set interrupt mask with the -* specified device. -*/ -sw_error_t -f1_phy_intr_mask_set(a_uint32_t dev_id, a_uint32_t phy_id, - a_uint32_t intr_mask_flag) -{ - a_uint16_t phy_data = 0; - - phy_data = f1_phy_reg_read(dev_id, phy_id, F1_PHY_INTR_MASK); - - if (FAL_PHY_INTR_STATUS_UP_CHANGE & intr_mask_flag) - { - phy_data |= F1_INTR_STATUS_UP_CHANGE; - } - else - { - phy_data &= (~F1_INTR_STATUS_UP_CHANGE); - } - - if (FAL_PHY_INTR_STATUS_DOWN_CHANGE & intr_mask_flag) - { - phy_data |= F1_INTR_STATUS_DOWN_CHANGE; - } - else - { - phy_data &= (~F1_INTR_STATUS_DOWN_CHANGE); - } - - if (FAL_PHY_INTR_SPEED_CHANGE & intr_mask_flag) - { - phy_data |= F1_INTR_SPEED_CHANGE; - } - else - { - phy_data &= (~F1_INTR_SPEED_CHANGE); - } - - if (FAL_PHY_INTR_DUPLEX_CHANGE & intr_mask_flag) - { - phy_data |= F1_INTR_DUPLEX_CHANGE; - } - else - { - phy_data &= (~F1_INTR_DUPLEX_CHANGE); - } - - f1_phy_reg_write(dev_id, phy_id, F1_PHY_INTR_MASK, phy_data); - return SW_OK; -} - -/****************************************************************************** -* -* f1_phy_intr_mask_get - Get interrupt mask with the -* specified device. -*/ -sw_error_t -f1_phy_intr_mask_get(a_uint32_t dev_id, a_uint32_t phy_id, - a_uint32_t * intr_mask_flag) -{ - a_uint16_t phy_data = 0; - - phy_data = f1_phy_reg_read(dev_id, phy_id, F1_PHY_INTR_MASK); - - *intr_mask_flag = 0; - if (F1_INTR_STATUS_UP_CHANGE & phy_data) - { - *intr_mask_flag |= FAL_PHY_INTR_STATUS_UP_CHANGE; - } - - if (F1_INTR_STATUS_DOWN_CHANGE & phy_data) - { - *intr_mask_flag |= FAL_PHY_INTR_STATUS_DOWN_CHANGE; - } - - if (F1_INTR_SPEED_CHANGE & phy_data) - { - *intr_mask_flag |= FAL_PHY_INTR_SPEED_CHANGE; - } - - if (F1_INTR_DUPLEX_CHANGE & phy_data) - { - *intr_mask_flag |= FAL_PHY_INTR_DUPLEX_CHANGE; - } - - return SW_OK; -} - -/****************************************************************************** -* -* f1_phy_intr_status_get - Get interrupt status with the -* specified device. -*/ -sw_error_t -f1_phy_intr_status_get(a_uint32_t dev_id, a_uint32_t phy_id, - a_uint32_t * intr_status_flag) -{ - a_uint16_t phy_data = 0; - - phy_data = f1_phy_reg_read(dev_id, phy_id, F1_PHY_INTR_STATUS); - - *intr_status_flag = 0; - if (F1_INTR_STATUS_UP_CHANGE & phy_data) - { - *intr_status_flag |= FAL_PHY_INTR_STATUS_UP_CHANGE; - } - - if (F1_INTR_STATUS_DOWN_CHANGE & phy_data) - { - *intr_status_flag |= FAL_PHY_INTR_STATUS_DOWN_CHANGE; - } - - if (F1_INTR_SPEED_CHANGE & phy_data) - { - *intr_status_flag |= FAL_PHY_INTR_SPEED_CHANGE; - } - - if (F1_INTR_DUPLEX_CHANGE & phy_data) - { - *intr_status_flag |= FAL_PHY_INTR_DUPLEX_CHANGE; - } - - return SW_OK; -} -/****************************************************************************** -* -*f1_phy_set_8023az status -* -* get 8023az status -*/ - -sw_error_t -f1_phy_set_8023az(a_uint32_t dev_id, a_uint32_t phy_id, a_bool_t enable) -{ - a_uint16_t phy_data; - - phy_data = f1_phy_mmd_read(dev_id, phy_id, F1_PHY_MMD7_NUM, - F1_PHY_8023AZ_EEE_CTRL); - if (enable == A_TRUE) { - phy_data |= F1_PHY_AZ_ENABLE; - - f1_phy_mmd_write(dev_id, phy_id, F1_PHY_MMD7_NUM, - F1_PHY_8023AZ_EEE_CTRL, phy_data); - } else { - phy_data &= ~F1_PHY_AZ_ENABLE; - - f1_phy_mmd_write(dev_id, phy_id, F1_PHY_MMD7_NUM, - F1_PHY_8023AZ_EEE_CTRL, phy_data); - } - - f1_phy_restart_autoneg(dev_id, phy_id); - - return SW_OK; -} - -/****************************************************************************** -* -*f1_phy_get_8023az status -* -* get 8023az status -*/ -sw_error_t -f1_phy_get_8023az(a_uint32_t dev_id, a_uint32_t phy_id, a_bool_t * enable) -{ - a_uint16_t phy_data; - - *enable = A_FALSE; - - phy_data = f1_phy_mmd_read(dev_id, phy_id, F1_PHY_MMD7_NUM, - F1_PHY_8023AZ_EEE_CTRL); - - if ((phy_data & 0x6) == F1_PHY_AZ_ENABLE) - *enable = A_TRUE; - - return SW_OK; -} - -/****************************************************************************** -* -* f1_phy_set_local_loopback -* -* set phy local loopback -*/ -sw_error_t -f1_phy_set_local_loopback(a_uint32_t dev_id, a_uint32_t phy_id, a_bool_t enable) -{ - a_uint16_t phy_data; - fal_port_speed_t old_speed; - sw_error_t rv = SW_OK; - - if (enable == A_TRUE) { - rv = f1_phy_get_speed(dev_id, phy_id, &old_speed); - SW_RTN_ON_ERROR(rv); - - if (old_speed == FAL_SPEED_1000) { - phy_data = F1_1000M_LOOPBACK; - } else if (old_speed == FAL_SPEED_100) { - phy_data = F1_100M_LOOPBACK; - } else if (old_speed == FAL_SPEED_10) { - phy_data = F1_10M_LOOPBACK; - } else { - return SW_FAIL; - } - phy_data |= F1_CTRL_FULL_DUPLEX; - } else { - phy_data = F1_COMMON_CTRL; - } - - rv = f1_phy_reg_write(dev_id, phy_id, F1_PHY_CONTROL, phy_data); - - return rv; -} - -/****************************************************************************** -* -* f1_phy_get_local_loopback -* -* get phy local loopback -*/ -sw_error_t -f1_phy_get_local_loopback(a_uint32_t dev_id, a_uint32_t phy_id, a_bool_t * enable) -{ - a_uint16_t phy_data; - - phy_data = f1_phy_reg_read(dev_id, phy_id, F1_PHY_CONTROL); - - if (phy_data & F1_LOCAL_LOOPBACK_ENABLE) - { - *enable = A_TRUE; - } - else - { - *enable = A_FALSE; - } - - return SW_OK; -} - -/****************************************************************************** -* -* f1_phy_set_remote_loopback -* -* set phy remote loopback -*/ -sw_error_t -f1_phy_set_remote_loopback(a_uint32_t dev_id, a_uint32_t phy_id, a_bool_t enable) -{ - a_uint16_t phy_data; - sw_error_t rv = SW_OK; - - phy_data = f1_phy_mmd_read(dev_id, phy_id, F1_PHY_MMD3_NUM, - F1_PHY_MMD3_ADDR_REMOTE_LOOPBACK_CTRL); - - if (enable == A_TRUE) - { - phy_data |= F1_PHY_REMOTE_LOOPBACK_ENABLE; - } - else - { - phy_data &= ~F1_PHY_REMOTE_LOOPBACK_ENABLE; - } - - rv = f1_phy_mmd_write(dev_id, phy_id, F1_PHY_MMD3_NUM, - F1_PHY_MMD3_ADDR_REMOTE_LOOPBACK_CTRL, phy_data); - - return rv; -} - -/****************************************************************************** -* -* f1_phy_get_remote_loopback -* -* get phy remote loopback -*/ -sw_error_t -f1_phy_get_remote_loopback(a_uint32_t dev_id, a_uint32_t phy_id, a_bool_t * enable) -{ - a_uint16_t phy_data; - - phy_data = f1_phy_mmd_read(dev_id, phy_id, F1_PHY_MMD3_NUM, - F1_PHY_MMD3_ADDR_REMOTE_LOOPBACK_CTRL); - - if (phy_data & F1_PHY_REMOTE_LOOPBACK_ENABLE) - { - *enable = A_TRUE; - } - else - { - *enable = A_FALSE; - } - - return SW_OK; -} - -static int f1_phy_api_ops_init(void) -{ - int ret; - hsl_phy_ops_t *f1_phy_api_ops = NULL; - - f1_phy_api_ops = kzalloc(sizeof(hsl_phy_ops_t), GFP_KERNEL); - if (f1_phy_api_ops == NULL) { - SSDK_ERROR("f1 phy ops kzalloc failed!\n"); - return -ENOMEM; - } - - phy_api_ops_init(F1_PHY_CHIP); - - f1_phy_api_ops->phy_hibernation_set = f1_phy_set_hibernate; - f1_phy_api_ops->phy_hibernation_get = f1_phy_get_hibernate; - f1_phy_api_ops->phy_speed_get = f1_phy_get_speed; - f1_phy_api_ops->phy_speed_set = f1_phy_set_speed; - f1_phy_api_ops->phy_duplex_get = f1_phy_get_duplex; - f1_phy_api_ops->phy_duplex_set = f1_phy_set_duplex; - f1_phy_api_ops->phy_autoneg_enable_set = f1_phy_enable_autoneg; - f1_phy_api_ops->phy_restart_autoneg = f1_phy_restart_autoneg; - f1_phy_api_ops->phy_autoneg_status_get = f1_phy_autoneg_status; - f1_phy_api_ops->phy_autoneg_adv_set = f1_phy_set_autoneg_adv; - f1_phy_api_ops->phy_autoneg_adv_get = f1_phy_get_autoneg_adv; - f1_phy_api_ops->phy_powersave_set = f1_phy_set_powersave; - f1_phy_api_ops->phy_powersave_get = f1_phy_get_powersave; - f1_phy_api_ops->phy_cdt = f1_phy_cdt; - f1_phy_api_ops->phy_link_status_get = f1_phy_get_link_status; - f1_phy_api_ops->phy_reset = f1_phy_reset; - f1_phy_api_ops->phy_power_off = f1_phy_poweroff; - f1_phy_api_ops->phy_power_on = f1_phy_poweron; - f1_phy_api_ops->phy_id_get = f1_phy_get_phy_id; - f1_phy_api_ops->phy_reg_write = f1_phy_reg_write; - f1_phy_api_ops->phy_reg_read = f1_phy_reg_read; - f1_phy_api_ops->phy_debug_write = f1_phy_debug_write; - f1_phy_api_ops->phy_debug_read = f1_phy_debug_read; - f1_phy_api_ops->phy_mmd_write = f1_phy_mmd_write; - f1_phy_api_ops->phy_mmd_read = f1_phy_mmd_read; - f1_phy_api_ops->phy_local_loopback_set = f1_phy_set_local_loopback; - f1_phy_api_ops->phy_local_loopback_get = f1_phy_get_local_loopback; - f1_phy_api_ops->phy_remote_loopback_set = f1_phy_set_remote_loopback; - f1_phy_api_ops->phy_remote_loopback_get = f1_phy_get_remote_loopback; - f1_phy_api_ops->phy_intr_mask_set = f1_phy_intr_mask_set; - f1_phy_api_ops->phy_intr_mask_get = f1_phy_intr_mask_get; - f1_phy_api_ops->phy_intr_status_get = f1_phy_intr_status_get; - f1_phy_api_ops->phy_8023az_set = f1_phy_set_8023az; - f1_phy_api_ops->phy_8023az_get = f1_phy_get_8023az; - - ret = hsl_phy_api_ops_register(F1_PHY_CHIP, f1_phy_api_ops); - - if (ret == 0) - SSDK_INFO("qca probe f1 phy driver succeeded!\n"); - else - SSDK_ERROR("qca probe f1 phy driver failed! (code: %d)\n", ret); - return ret; -} - -int f1_phy_init(a_uint32_t dev_id, a_uint32_t port_bmp) -{ - static a_uint32_t phy_ops_flag = 0; - - if(phy_ops_flag == 0) { - f1_phy_api_ops_init(); - phy_ops_flag = 1; - } - - return 0; -} - diff --git a/feeds/ipq807x/qca-ssdk/src/src/hsl/phy/f2_phy.c b/feeds/ipq807x/qca-ssdk/src/src/hsl/phy/f2_phy.c deleted file mode 100755 index 07429446c..000000000 --- a/feeds/ipq807x/qca-ssdk/src/src/hsl/phy/f2_phy.c +++ /dev/null @@ -1,918 +0,0 @@ -/* - * Copyright (c) 2012, 2015-2018, The Linux Foundation. All rights reserved. - * Permission to use, copy, modify, and/or distribute this software for - * any purpose with or without fee is hereby granted, provided that the - * above copyright notice and this permission notice appear in all copies. - * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES - * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR - * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES - * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN - * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT - * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. - */ - -#include "sw.h" -#include "fal_port_ctrl.h" -#include "hsl_api.h" -#include "hsl.h" -#include "f2_phy.h" -#include "hsl_phy.h" -#include "ssdk_plat.h" - -static a_uint16_t -_phy_reg_read(a_uint32_t dev_id, a_uint32_t phy_addr, a_uint8_t reg) -{ - sw_error_t rv; - a_uint16_t val = 0; - - HSL_PHY_GET(rv, dev_id, phy_addr, reg, &val); - if (SW_OK != rv) - return 0xFFFF; - - return val; -} - - -static sw_error_t -_phy_reg_write(a_uint32_t dev_id, a_uint32_t phy_addr, a_uint8_t reg, - a_uint16_t val) -{ - sw_error_t rv; - - HSL_PHY_SET(rv, dev_id, phy_addr, reg, val); - - return rv; -} - -/* #define f2_phy_reg_read _phy_reg_read */ -/* #define f2_phy_reg_write _phy_reg_write */ - -/****************************************************************************** -* -* f2_phy_mii_read - mii register read -* -* mil register read -*/ -a_uint16_t -f2_phy_reg_read(a_uint32_t dev_id, a_uint32_t phy_id, a_uint32_t reg_id) -{ - return _phy_reg_read(dev_id, phy_id, reg_id); - -} - -/****************************************************************************** -* -* f2_phy_reg_write - mii register write -* -* mii register write -*/ -sw_error_t -f2_phy_reg_write(a_uint32_t dev_id, a_uint32_t phy_id, a_uint32_t reg_id, - a_uint16_t reg_val) -{ - - _phy_reg_write(dev_id,phy_id, reg_id, reg_val); - - return SW_OK; -} - - -/****************************************************************************** -* -* f2_phy_debug_write - debug port write -* -* debug port write -*/ -sw_error_t -f2_phy_debug_write(a_uint32_t dev_id, a_uint32_t phy_id, a_uint16_t reg_id, - a_uint16_t reg_val) -{ - f2_phy_reg_write(dev_id, phy_id, F2_DEBUG_PORT_ADDRESS, reg_id); - f2_phy_reg_write(dev_id, phy_id, F2_DEBUG_PORT_DATA, reg_val); - - return SW_OK; -} - -/****************************************************************************** -* -* f2_phy_debug_read - debug port read -* -* debug port read -*/ -a_uint16_t -f2_phy_debug_read(a_uint32_t dev_id, a_uint32_t phy_id, a_uint16_t reg_id) -{ - f2_phy_reg_write(dev_id, phy_id, F2_DEBUG_PORT_ADDRESS, reg_id); - return f2_phy_reg_read(dev_id, phy_id, F2_DEBUG_PORT_DATA); -} - -/****************************************************************************** -* -* f2_phy_set_powersave - set power saving status -* -* set power saving status -*/ -sw_error_t -f2_phy_set_powersave(a_uint32_t dev_id, a_uint32_t phy_id, a_bool_t enable) -{ - a_uint16_t phy_data; - f2_phy_reg_write(dev_id, phy_id, F2_DEBUG_PORT_ADDRESS, 0x29); - phy_data = f2_phy_reg_read(dev_id, phy_id, F2_DEBUG_PORT_DATA); - - if(enable == A_TRUE) - { - phy_data |= 0x8000; - } - else - { - phy_data &= ~0x8000; - } - - f2_phy_reg_write(dev_id, phy_id, F2_DEBUG_PORT_DATA, phy_data); - - return SW_OK; -} - -/****************************************************************************** -* -* f2_phy_get_powersave - get power saving status -* -* set power saving status -*/ -sw_error_t -f2_phy_get_powersave(a_uint32_t dev_id, a_uint32_t phy_id, a_bool_t *enable) -{ - a_uint16_t phy_data; - *enable = A_FALSE; - - f2_phy_reg_write(dev_id, phy_id, F2_DEBUG_PORT_ADDRESS, 0x29); - phy_data = f2_phy_reg_read(dev_id, phy_id, F2_DEBUG_PORT_DATA); - - if(phy_data & 0x8000) - *enable = A_TRUE; - - return SW_OK; -} - -/****************************************************************************** -* -* f2_phy_set_hibernate - set hibernate status -* -* set hibernate status -*/ -sw_error_t -f2_phy_set_hibernate(a_uint32_t dev_id, a_uint32_t phy_id, a_bool_t enable) -{ - a_uint16_t phy_data; - f2_phy_reg_write(dev_id, phy_id, F2_DEBUG_PORT_ADDRESS, 0xb); - phy_data = f2_phy_reg_read(dev_id, phy_id, F2_DEBUG_PORT_DATA); - - if(enable == A_TRUE) - { - phy_data |= 0x8000; - } - else - { - phy_data &= ~0x8000; - } - - f2_phy_reg_write(dev_id, phy_id, F2_DEBUG_PORT_DATA, phy_data); - - return SW_OK; -} - -/****************************************************************************** -* -* f2_phy_get_hibernate - get hibernate status -* -* get hibernate status -*/ -sw_error_t -f2_phy_get_hibernate(a_uint32_t dev_id, a_uint32_t phy_id, a_bool_t *enable) -{ - a_uint16_t phy_data; - *enable = A_FALSE; - - f2_phy_reg_write(dev_id, phy_id, F2_DEBUG_PORT_ADDRESS, 0xb); - phy_data = f2_phy_reg_read(dev_id, phy_id, F2_DEBUG_PORT_DATA); - - if(phy_data & 0x8000) - *enable = A_TRUE; - - return SW_OK; -} - -/****************************************************************************** -* -* f2_phy_cdt - cable diagnostic test -* -* cable diagnostic test -*/ -sw_error_t -f2_phy_cdt(a_uint32_t dev_id, a_uint32_t phy_id, a_uint32_t mdi_pair, - fal_cable_status_t *cable_status, a_uint32_t *cable_len) -{ - a_uint16_t status = 0; - a_uint16_t ii = 100; - a_uint16_t cable_delta_time; - - if(!cable_status || !cable_len) - { - return SW_FAIL; - } - - if(mdi_pair >= 2) - { - //There are only 4 mdi pairs in 1000BASE-T - return SW_BAD_PARAM; - } - - f2_phy_reg_write(dev_id, phy_id, F2_PHY_CDT_CONTROL, (mdi_pair << 8) | 0x0001); - - do - { - aos_mdelay(30); - status = f2_phy_reg_read(dev_id, phy_id, F2_PHY_CDT_CONTROL); - } - while ((status & 0x0001) && (--ii)); - - status = f2_phy_reg_read(dev_id, phy_id, F2_PHY_CDT_STATUS); - *cable_status = (status & 0x300) >> 8;//(00:normal 01:short 10:opened 11:invalid) - - /*the actual cable length equals to CableDeltaTime * 0.824*/ - cable_delta_time = status & 0xff; - *cable_len = (cable_delta_time * 824) /1000; - - /*workaround*/ - if(*cable_len <= 2 && *cable_status == 1) - *cable_status = 2; - - //f2_phy_reg_write(dev_id, phy_id, 0x00, 0x9000); //Reset the PHY if necessary - - return SW_OK; -} - -/****************************************************************************** -* -* f2_phy_reset_done - reset the phy -* -* reset the phy -*/ -a_bool_t -f2_phy_reset_done(a_uint32_t dev_id, a_uint32_t phy_id) -{ - a_uint16_t phy_data; - a_uint16_t ii = 200; - - do - { - phy_data = f2_phy_reg_read(dev_id, phy_id, F2_PHY_CONTROL); - aos_mdelay(10); - } - while ((!F2_RESET_DONE(phy_data)) && --ii); - - if (ii == 0) - return A_FALSE; - - return A_TRUE; -} - -/****************************************************************************** -* -* f2_autoneg_done -* -* f2_autoneg_done -*/ -a_bool_t -f2_autoneg_done(a_uint32_t dev_id, a_uint32_t phy_id) -{ - a_uint16_t phy_data; - a_uint16_t ii = 200; - - do - { - phy_data = f2_phy_reg_read(dev_id, phy_id, F2_PHY_STATUS); - aos_mdelay(10); - } - while ((!F2_AUTONEG_DONE(phy_data)) && --ii); - - if (ii == 0) - return A_FALSE; - - return A_TRUE; -} - -/****************************************************************************** -* -* f2_phy_Speed_Duplex_Resolved - - reset the phy -* -* reset the phy -*/ -a_bool_t -f2_phy_speed_duplex_resolved(a_uint32_t dev_id, a_uint32_t phy_id) -{ - a_uint16_t phy_data; - a_uint16_t ii = 200; - - do - { - phy_data = f2_phy_reg_read(dev_id, phy_id, F2_PHY_SPEC_STATUS); - aos_mdelay(10); - } - while ((!F2_SPEED_DUPLEX_RESOVLED(phy_data)) && --ii); - - if (ii == 0) - return A_FALSE; - - return A_TRUE; -} - -/****************************************************************************** -* -* f2_phy_reset - reset the phy -* -* reset the phy -*/ -sw_error_t -f2_phy_reset(a_uint32_t dev_id, a_uint32_t phy_id) -{ - a_uint16_t phy_data; - - phy_data = f2_phy_reg_read(dev_id, phy_id, F2_PHY_CONTROL); - f2_phy_reg_write(dev_id, phy_id, F2_PHY_CONTROL, - phy_data | F2_CTRL_SOFTWARE_RESET); - - return SW_OK; -} - -/****************************************************************************** -* -* f2_phy_off - power off the phy to change its speed -* -* Power off the phy -*/ -sw_error_t -f2_phy_poweroff(a_uint32_t dev_id, a_uint32_t phy_id) -{ - a_uint16_t phy_data; - - phy_data = f2_phy_reg_read(dev_id, phy_id, F2_PHY_CONTROL); - f2_phy_reg_write(dev_id, phy_id, F2_PHY_CONTROL, - phy_data | F2_CTRL_POWER_DOWN); - - return SW_OK; -} - -/****************************************************************************** -* -* f2_phy_on - power on the phy after speed changed -* -* Power on the phy -*/ -sw_error_t -f2_phy_poweron(a_uint32_t dev_id, a_uint32_t phy_id) -{ - a_uint16_t phy_data; - - phy_data = f2_phy_reg_read(dev_id, phy_id, F2_PHY_CONTROL); - f2_phy_reg_write(dev_id, phy_id, F2_PHY_CONTROL, - phy_data & ~F2_CTRL_POWER_DOWN); - - aos_mdelay(200); - - return SW_OK; -} - -/****************************************************************************** -* -* f2_phy_get_ability - get the phy ability -* -* -*/ -sw_error_t -f2_phy_get_ability(a_uint32_t dev_id, a_uint32_t phy_id, - a_uint16_t * ability) -{ - a_uint16_t phy_data; - - *ability = 0; - - phy_data = f2_phy_reg_read(dev_id, phy_id, F2_PHY_STATUS); - - if (phy_data & F2_STATUS_AUTONEG_CAPS) - *ability |= FAL_PHY_AUTONEG_CAPS; - - if (phy_data & F2_STATUS_100T2_HD_CAPS) - *ability |= FAL_PHY_100T2_HD_CAPS; - - if (phy_data & F2_STATUS_100T2_FD_CAPS) - *ability |= FAL_PHY_100T2_FD_CAPS; - - if (phy_data & F2_STATUS_10T_HD_CAPS) - *ability |= FAL_PHY_10T_HD_CAPS; - - if (phy_data & F2_STATUS_10T_FD_CAPS) - *ability |= FAL_PHY_10T_FD_CAPS; - - if (phy_data & F2_STATUS_100X_HD_CAPS) - *ability |= FAL_PHY_100X_HD_CAPS; - - if (phy_data & F2_STATUS_100X_FD_CAPS) - *ability |= FAL_PHY_100X_FD_CAPS; - - if (phy_data & F2_STATUS_100T4_CAPS) - *ability |= FAL_PHY_100T4_CAPS; - - return SW_OK; -} - -/****************************************************************************** -* -* f2_phy_get_ability - get the phy ability -* -* -*/ -sw_error_t -f2_phy_get_partner_ability(a_uint32_t dev_id, a_uint32_t phy_id, - a_uint16_t * ability) -{ - a_uint16_t phy_data; - - *ability = 0; - - phy_data = f2_phy_reg_read(dev_id, phy_id, F2_LINK_PARTNER_ABILITY); - - if (phy_data & F2_LINK_10BASETX_HALF_DUPLEX) - *ability |= FAL_PHY_PART_10T_HD; - - if (phy_data & F2_LINK_10BASETX_FULL_DUPLEX) - *ability |= FAL_PHY_PART_10T_FD; - - if (phy_data & F2_LINK_100BASETX_HALF_DUPLEX) - *ability |= FAL_PHY_PART_100TX_HD; - - if (phy_data & F2_LINK_100BASETX_FULL_DUPLEX) - *ability |= FAL_PHY_PART_100TX_FD; - - return SW_OK; -} - -/****************************************************************************** -* -* f2_phy_status - test to see if the specified phy link is alive -* -* RETURNS: -* A_TRUE --> link is alive -* A_FALSE --> link is down -*/ -a_bool_t -f2_phy_get_link_status(a_uint32_t dev_id, a_uint32_t phy_id) -{ - a_uint16_t phy_data; - - phy_data = f2_phy_reg_read(dev_id, phy_id, F2_PHY_STATUS); - - if (phy_data & F2_STATUS_LINK_STATUS_UP) - return A_TRUE; - - return A_FALSE; -} - -/****************************************************************************** -* -* f2_set_autoneg_adv - set the phy autoneg Advertisement -* -*/ -sw_error_t -f2_phy_set_autoneg_adv(a_uint32_t dev_id, a_uint32_t phy_id, - a_uint32_t autoneg) -{ - a_uint16_t phy_data = 0; - - phy_data = f2_phy_reg_read(dev_id, phy_id, F2_AUTONEG_ADVERT); - phy_data &= ~F2_ADVERTISE_ALL; - phy_data &= ~(F2_ADVERTISE_PAUSE | F2_ADVERTISE_ASYM_PAUSE); - - if (autoneg & FAL_PHY_ADV_100TX_FD) - phy_data |= F2_ADVERTISE_100FULL; - - if (autoneg & FAL_PHY_ADV_100TX_HD) - phy_data |= F2_ADVERTISE_100HALF; - - if (autoneg & FAL_PHY_ADV_10T_FD) - phy_data |= F2_ADVERTISE_10FULL; - - if (autoneg & FAL_PHY_ADV_10T_HD) - phy_data |= F2_ADVERTISE_10HALF; - - if (autoneg & FAL_PHY_ADV_PAUSE) - phy_data |= F2_ADVERTISE_PAUSE; - - if (autoneg & FAL_PHY_ADV_ASY_PAUSE) - phy_data |= F2_ADVERTISE_ASYM_PAUSE; - - f2_phy_reg_write(dev_id, phy_id, F2_AUTONEG_ADVERT, phy_data); - - return SW_OK; -} - -/****************************************************************************** -* -* f2_get_autoneg_adv - get the phy autoneg Advertisement -* -*/ -sw_error_t -f2_phy_get_autoneg_adv(a_uint32_t dev_id, a_uint32_t phy_id, - a_uint32_t * autoneg) -{ - a_uint16_t phy_data = 0; - - *autoneg = 0; - - phy_data = f2_phy_reg_read(dev_id, phy_id, F2_AUTONEG_ADVERT); - - if (phy_data & F2_ADVERTISE_100FULL) - *autoneg |= FAL_PHY_ADV_100TX_FD; - - if (phy_data & F2_ADVERTISE_100HALF) - *autoneg |= FAL_PHY_ADV_100TX_HD; - - if (phy_data & F2_ADVERTISE_10FULL) - *autoneg |= FAL_PHY_ADV_10T_FD; - - if (phy_data & F2_ADVERTISE_10HALF) - *autoneg |= FAL_PHY_ADV_10T_HD; - - if (phy_data & F2_ADVERTISE_PAUSE) - *autoneg |= FAL_PHY_ADV_PAUSE; - - if (phy_data & F2_ADVERTISE_ASYM_PAUSE) - *autoneg |= FAL_PHY_ADV_ASY_PAUSE; - - return SW_OK; -} - -/****************************************************************************** -* -* f2_phy_enable_autonego - power off the phy to change its speed -* -* Power off the phy -*/ -a_bool_t -f2_phy_autoneg_status(a_uint32_t dev_id, a_uint32_t phy_id) -{ - a_uint16_t phy_data; - - phy_data = f2_phy_reg_read(dev_id, phy_id, F2_PHY_CONTROL); - - if (phy_data & F2_CTRL_AUTONEGOTIATION_ENABLE) - return A_TRUE; - - return A_FALSE; -} - -/****************************************************************************** -* -* f2_restart_autoneg - restart the phy autoneg -* -*/ -sw_error_t -f2_phy_restart_autoneg(a_uint32_t dev_id, a_uint32_t phy_id) -{ - a_uint16_t phy_data = 0; - - phy_data = f2_phy_reg_read(dev_id, phy_id, F2_PHY_CONTROL); - - phy_data |= F2_CTRL_AUTONEGOTIATION_ENABLE; - f2_phy_reg_write(dev_id, phy_id, F2_PHY_CONTROL, - phy_data | F2_CTRL_RESTART_AUTONEGOTIATION); - - return SW_OK; -} - -/****************************************************************************** -* -* f2_phy_enable_autonego - power off the phy to change its speed -* -* Power off the phy -*/ -sw_error_t -f2_phy_enable_autoneg(a_uint32_t dev_id, a_uint32_t phy_id) -{ - a_uint16_t phy_data = 0; - - phy_data = f2_phy_reg_read(dev_id, phy_id, F2_PHY_CONTROL); - - f2_phy_reg_write(dev_id, phy_id, F2_PHY_CONTROL, - phy_data | F2_CTRL_AUTONEGOTIATION_ENABLE); - - return SW_OK; -} - - -/****************************************************************************** -* -* f2_phy_get_speed - Determines the speed of phy ports associated with the -* specified device. -* -* RETURNS: -* AG7100_PHY_SPEED_10T, AG7100_PHY_SPEED_100TX; -* AG7100_PHY_SPEED_1000T; -*/ - -sw_error_t -f2_phy_get_speed(a_uint32_t dev_id, a_uint32_t phy_id, - fal_port_speed_t * speed) -{ - a_uint16_t phy_data; - - phy_data = f2_phy_reg_read(dev_id, phy_id, F2_PHY_SPEC_STATUS); - - //read speed - switch (phy_data & F2_STATUS_SPEED_MASK) - { - case F2_STATUS_SPEED_1000MBS: - *speed = FAL_SPEED_1000; - break; - case F2_STATUS_SPEED_100MBS: - *speed = FAL_SPEED_100; - break; - case F2_STATUS_SPEED_10MBS: - *speed = FAL_SPEED_10; - break; - default: - return SW_READ_ERROR; - } - - return SW_OK; -} - -/****************************************************************************** -* -* f2_phy_set_speed - Determines the speed of phy ports associated with the -* specified device. -* -* RETURNS: -* AG7100_PHY_SPEED_10T, AG7100_PHY_SPEED_100TX; -* AG7100_PHY_SPEED_1000T; -*/ -sw_error_t -f2_phy_set_speed(a_uint32_t dev_id, a_uint32_t phy_id, - fal_port_speed_t speed) -{ - a_uint16_t phy_data = 0; - a_uint16_t phy_status = 0; - a_uint32_t autoneg, oldneg; - fal_port_duplex_t old_duplex; - - phy_data &= ~F2_CTRL_AUTONEGOTIATION_ENABLE; - - (void)f2_phy_get_autoneg_adv(dev_id, phy_id, &autoneg); - oldneg = autoneg; - autoneg &= ~FAL_PHY_ADV_FE_SPEED_ALL; - - (void)f2_phy_get_duplex(dev_id, phy_id, &old_duplex); - - if (old_duplex == FAL_FULL_DUPLEX) - { - phy_data |= F2_CTRL_FULL_DUPLEX; - - if (speed == FAL_SPEED_100) - autoneg |= FAL_PHY_ADV_100TX_FD; - else - autoneg |= FAL_PHY_ADV_10T_FD; - } - else if (old_duplex == FAL_HALF_DUPLEX) - { - phy_data &= ~F2_CTRL_FULL_DUPLEX; - - if (speed == FAL_SPEED_100) - autoneg |= FAL_PHY_ADV_100TX_HD; - else - autoneg |= FAL_PHY_ADV_10T_HD; - } - else - return SW_FAIL; - - (void)f2_phy_set_autoneg_adv(dev_id, phy_id, autoneg); - (void)f2_phy_restart_autoneg(dev_id, phy_id); - - if(f2_phy_get_link_status(dev_id, phy_id)) - { - do - { - phy_status = f2_phy_reg_read(dev_id, phy_id, F2_PHY_STATUS); - } - while(!F2_AUTONEG_DONE(phy_status)); - } - - if (speed == FAL_SPEED_100) - phy_data |= F2_CTRL_SPEED_100; - else if (speed == FAL_SPEED_10) - phy_data |= F2_CTRL_SPEED_10; - else - return SW_BAD_PARAM; - - f2_phy_reg_write(dev_id, phy_id, F2_PHY_CONTROL, phy_data); - (void)f2_phy_set_autoneg_adv(dev_id, phy_id, oldneg); - - return SW_OK; - -} - -/****************************************************************************** -* -* f2_phy_get_duplex - Determines the speed of phy ports associated with the -* specified device. -* -* RETURNS: -* AG7100_PHY_SPEED_10T, AG7100_PHY_SPEED_100TX; -* AG7100_PHY_SPEED_1000T; -*/ -sw_error_t -f2_phy_get_duplex(a_uint32_t dev_id, a_uint32_t phy_id, - fal_port_duplex_t * duplex) -{ - a_uint16_t phy_data; - -#if 0 - //a_uint16_t ii = 200; - a_uint16_t ii = 2; - - if (phy_id >= F2_PHY_MAX) - return SW_BAD_PARAM; - - do - { - phy_data = f2_phy_reg_read(dev_id, phy_id, F2_PHY_SPEC_STATUS); - aos_mdelay(10); - } - while ((!(phy_data & F2_STATUS_RESOVLED)) && --ii); - - //read time out - if (ii == 0) - return SW_DISABLE; -#endif - - phy_data = f2_phy_reg_read(dev_id, phy_id, F2_PHY_SPEC_STATUS); - - //read duplex - if (phy_data & F2_STATUS_FULL_DUPLEX) - *duplex = FAL_FULL_DUPLEX; - else - *duplex = FAL_HALF_DUPLEX; - - return SW_OK; -} - -/****************************************************************************** -* -* f2_phy_set_duplex - Determines the speed of phy ports associated with the -* specified device. -* -* RETURNS: -* AG7100_PHY_SPEED_10T, AG7100_PHY_SPEED_100TX; -* AG7100_PHY_SPEED_1000T; -*/ -sw_error_t -f2_phy_set_duplex(a_uint32_t dev_id, a_uint32_t phy_id, - fal_port_duplex_t duplex) -{ - a_uint16_t phy_data = 0; - a_uint16_t phy_status = 0; - - fal_port_speed_t old_speed = FAL_SPEED_10; - a_uint32_t autoneg, oldneg; - - if (f2_phy_autoneg_status(dev_id, phy_id)) - phy_data &= ~F2_CTRL_AUTONEGOTIATION_ENABLE; - - (void)f2_phy_get_autoneg_adv(dev_id, phy_id, &autoneg); - oldneg = autoneg; - autoneg &= ~FAL_PHY_ADV_FE_SPEED_ALL; - - (void)f2_phy_get_speed(dev_id, phy_id, &old_speed); - - if (old_speed == FAL_SPEED_100) - phy_data |= F2_CTRL_SPEED_100; - else if (old_speed == FAL_SPEED_10) - phy_data |= F2_CTRL_SPEED_10; - else - return SW_FAIL; - - if (duplex == FAL_FULL_DUPLEX) - { - phy_data |= F2_CTRL_FULL_DUPLEX; - - if (old_speed == FAL_SPEED_100) - autoneg = FAL_PHY_ADV_100TX_FD; - else - autoneg = FAL_PHY_ADV_10T_FD; - } - else if (duplex == FAL_HALF_DUPLEX) - { - phy_data &= ~F2_CTRL_FULL_DUPLEX; - - if (old_speed == FAL_SPEED_100) - autoneg = FAL_PHY_ADV_100TX_HD; - else - autoneg = FAL_PHY_ADV_10T_HD; - } - else - return SW_BAD_PARAM; - - (void)f2_phy_set_autoneg_adv(dev_id, phy_id, autoneg); - (void)f2_phy_restart_autoneg(dev_id, phy_id); - - if(f2_phy_get_link_status(dev_id, phy_id)) - { - do - { - phy_status = f2_phy_reg_read(dev_id, phy_id, F2_PHY_STATUS); - } - while(!F2_AUTONEG_DONE(phy_status)); - } - - f2_phy_reg_write(dev_id, phy_id, F2_PHY_CONTROL, phy_data); - (void)f2_phy_set_autoneg_adv(dev_id, phy_id, oldneg); - - return SW_OK; -} - -/****************************************************************************** -* -* f2_phy_get_phy_id - get the phy id -* -*/ -static sw_error_t -f2_phy_get_phy_id(a_uint32_t dev_id, a_uint32_t phy_id, - a_uint32_t *phy_data) -{ - a_uint16_t org_id, rev_id; - - org_id = f2_phy_reg_read(dev_id, phy_id, F2_PHY_ID1); - rev_id = f2_phy_reg_read(dev_id, phy_id, F2_PHY_ID2); - *phy_data = ((org_id & 0xffff) << 16) | (rev_id & 0xffff); - - return SW_OK; -} -static int f2_phy_api_ops_init(void) -{ - int ret; - hsl_phy_ops_t *f2_phy_api_ops = NULL; - - f2_phy_api_ops = kzalloc(sizeof(hsl_phy_ops_t), GFP_KERNEL); - if (f2_phy_api_ops == NULL) { - SSDK_ERROR("f2 phy ops kzalloc failed!\n"); - return -ENOMEM; - } - - phy_api_ops_init(F2_PHY_CHIP); - - f2_phy_api_ops->phy_hibernation_set = f2_phy_set_hibernate; - f2_phy_api_ops->phy_hibernation_get = f2_phy_get_hibernate; - f2_phy_api_ops->phy_speed_get = f2_phy_get_speed; - f2_phy_api_ops->phy_speed_set = f2_phy_set_speed; - f2_phy_api_ops->phy_duplex_get = f2_phy_get_duplex; - f2_phy_api_ops->phy_duplex_set = f2_phy_set_duplex; - f2_phy_api_ops->phy_autoneg_enable_set = f2_phy_enable_autoneg; - f2_phy_api_ops->phy_restart_autoneg = f2_phy_restart_autoneg; - f2_phy_api_ops->phy_autoneg_status_get = f2_phy_autoneg_status; - f2_phy_api_ops->phy_autoneg_adv_set = f2_phy_set_autoneg_adv; - f2_phy_api_ops->phy_autoneg_adv_get = f2_phy_get_autoneg_adv; - f2_phy_api_ops->phy_powersave_set = f2_phy_set_powersave; - f2_phy_api_ops->phy_powersave_get = f2_phy_get_powersave; - f2_phy_api_ops->phy_cdt = f2_phy_cdt; - f2_phy_api_ops->phy_link_status_get = f2_phy_get_link_status; - f2_phy_api_ops->phy_reset = f2_phy_reset; - f2_phy_api_ops->phy_power_off = f2_phy_poweroff; - f2_phy_api_ops->phy_power_on = f2_phy_poweron; - f2_phy_api_ops->phy_id_get = f2_phy_get_phy_id; - f2_phy_api_ops->phy_reg_write = f2_phy_reg_write; - f2_phy_api_ops->phy_reg_read = f2_phy_reg_read; - f2_phy_api_ops->phy_debug_write = f2_phy_debug_write; - f2_phy_api_ops->phy_debug_read = f2_phy_debug_read; - - ret = hsl_phy_api_ops_register(F2_PHY_CHIP, f2_phy_api_ops); - - if (ret == 0) - SSDK_INFO("qca probe f2 phy driver succeeded!\n"); - else - SSDK_ERROR("qca probe f2 phy driver failed! (code: %d)\n", ret); - - return ret; -} -int f2_phy_init(a_uint32_t dev_id, a_uint32_t port_bmp) -{ - static a_uint32_t phy_ops_flag = 0; - - if(phy_ops_flag == 0) { - f2_phy_api_ops_init(); - phy_ops_flag = 1; - } - - return 0; -} - diff --git a/feeds/ipq807x/qca-ssdk/src/src/hsl/phy/hsl_phy.c b/feeds/ipq807x/qca-ssdk/src/src/hsl/phy/hsl_phy.c deleted file mode 100755 index 5866a522e..000000000 --- a/feeds/ipq807x/qca-ssdk/src/src/hsl/phy/hsl_phy.c +++ /dev/null @@ -1,827 +0,0 @@ -/* - * Copyright (c) 2015, 2017-2021, The Linux Foundation. All rights reserved. - * Permission to use, copy, modify, and/or distribute this software for - * any purpose with or without fee is hereby granted, provided that the - * above copyright notice and this permission notice appear in all copies. - * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES - * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR - * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES - * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN - * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT - * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. - */ -/*qca808x_start*/ -#include "sw.h" -#include "hsl_phy.h" -#include "hsl.h" -/*qca808x_end*/ -#include "ssdk_dts.h" -#if defined(ISIS) ||defined(ISISC) ||defined(GARUDA) -#include -#endif -#if defined(ATHENA) ||defined(SHIVA) ||defined(HORUS) -#include -#endif -#ifdef MP -#include "mpge_phy.h" -#endif -#ifdef IN_MALIBU_PHY -#include -#endif -#ifdef IN_AQUANTIA_PHY -#include -#endif -#ifdef IN_QCA803X_PHY -#include -#endif -#ifdef IN_SFP_PHY -#include -#endif -#ifdef IN_QCA808X_PHY -/*qca808x_start*/ -#include -/*qca808x_end*/ -#endif -#include -/*qca808x_start*/ -#include "sw.h" -#include "ssdk_plat.h" -#include "hsl_port_prop.h" - -phy_info_t *phy_info[SW_MAX_NR_DEV] = {0}; -a_uint32_t port_bmp[SW_MAX_NR_DEV] = {0}; - - -phy_driver_instance_t ssdk_phy_driver[] = -{ -/*qca808x_end*/ - #if defined(ISIS) ||defined(ISISC) ||defined(GARUDA) - {F1_PHY_CHIP, {0}, NULL, f1_phy_init, NULL}, - #else - {F1_PHY_CHIP, {0}, NULL, NULL, NULL}, - #endif - #if defined(ATHENA) ||defined(SHIVA) ||defined(HORUS) - {F2_PHY_CHIP, {0}, NULL, f2_phy_init, NULL}, - #else - {F2_PHY_CHIP, {0}, NULL, NULL, NULL}, - #endif - #ifdef IN_MALIBU_PHY - {MALIBU_PHY_CHIP, {0}, NULL, malibu_phy_init, NULL}, - #else - {MALIBU_PHY_CHIP, {0}, NULL, NULL, NULL}, - #endif - #ifdef IN_AQUANTIA_PHY - {AQUANTIA_PHY_CHIP, {0}, NULL, aquantia_phy_init, NULL}, - #else - {AQUANTIA_PHY_CHIP, {0}, NULL, NULL, NULL}, - #endif - #ifdef IN_QCA803X_PHY - {QCA803X_PHY_CHIP, {0}, NULL, qca803x_phy_init, NULL}, - #else - {QCA803X_PHY_CHIP, {0}, NULL, NULL, NULL}, - #endif - #ifdef IN_SFP_PHY - {SFP_PHY_CHIP, {0}, NULL, sfp_phy_init, sfp_phy_exit}, - #else - {SFP_PHY_CHIP, {0}, NULL, NULL, NULL}, - #endif - #ifdef MP - {MPGE_PHY_CHIP, {0}, NULL, mpge_phy_init, NULL}, - #else - {MPGE_PHY_CHIP, {0}, NULL, NULL, NULL}, - #endif - #ifdef IN_QCA808X_PHY -/*qca808x_start*/ - {QCA808X_PHY_CHIP, {0}, NULL, qca808x_phy_init, qca808x_phy_exit}, -/*qca808x_end*/ - #else - {QCA808X_PHY_CHIP, {0}, NULL, NULL, NULL}, - #endif -/*qca808x_start*/ - {MAX_PHY_CHIP, {0}, NULL, NULL, NULL} -}; -sw_error_t hsl_phy_api_ops_register(phy_type_t phy_type, hsl_phy_ops_t * phy_api_ops) -{ - - ssdk_phy_driver[phy_type].phy_ops = phy_api_ops; - - return SW_OK; - -} - -sw_error_t hsl_phy_api_ops_unregister(phy_type_t phy_type, hsl_phy_ops_t * phy_api_ops) -{ - - ssdk_phy_driver[phy_type].phy_ops = NULL; - - return SW_OK; - -} - -hsl_phy_ops_t *hsl_phy_api_ops_get(a_uint32_t dev_id, a_uint32_t port_id) -{ - phy_type_t phytype = 0; - - if (dev_id >= SW_MAX_NR_DEV) - return NULL; - - phytype = phy_info[dev_id]->phy_type[port_id]; - if(phytype == MAX_PHY_CHIP) - { - return NULL; - } - - return ssdk_phy_driver[phytype].phy_ops; - -} - -sw_error_t phy_api_ops_init(phy_type_t phy_type) -{ - - if (MAX_PHY_CHIP <= phy_type) - return SW_BAD_PARAM; - - if(ssdk_phy_driver[phy_type].phy_ops != NULL) - { - kfree(ssdk_phy_driver[phy_type].phy_ops); - ssdk_phy_driver[phy_type].phy_ops = NULL; - } - return SW_OK; -} - -a_bool_t hsl_port_is_sfp(a_uint32_t dev_id, a_uint32_t port_id, ssdk_init_cfg *cfg) -{ - if ((cfg->chip_type == CHIP_HPPE) && - (((SSDK_PHYSICAL_PORT5 == port_id) && - ((cfg->mac_mode1 == PORT_WRAPPER_10GBASE_R) || - (cfg->mac_mode1 == PORT_WRAPPER_SGMII_FIBER))) || - ((SSDK_PHYSICAL_PORT6 == port_id) && - ((cfg->mac_mode2 == PORT_WRAPPER_10GBASE_R) || - (cfg->mac_mode2 == PORT_WRAPPER_SGMII_FIBER))))) - return A_TRUE; - else - return A_FALSE; -} - -a_uint32_t hsl_phyid_get(a_uint32_t dev_id, - a_uint32_t port_id, ssdk_init_cfg *cfg) -{ - a_uint16_t org_id = 0, rev_id = 0; - a_uint32_t reg_pad = 0, phy_id = 0; - -/*qca808x_end*/ - if(ssdk_is_emulation(dev_id) && ssdk_emu_chip_ver_get(dev_id) == MP_GEPHY){ - return MP_GEPHY; - } -/*qca808x_start*/ - if (hsl_port_is_sfp(dev_id, port_id, cfg)){ - return SFP_PHY; - } - - if (phy_info[dev_id]->phy_c45[port_id] == A_TRUE){ - reg_pad = BIT(30) | BIT(16); - } - -#if defined(IN_PHY_I2C_MODE) - if (hsl_port_phy_access_type_get(dev_id, port_id) == PHY_I2C_ACCESS) { - cfg->reg_func.i2c_get(dev_id, - phy_info[dev_id]->phy_address[port_id], reg_pad | 2, &org_id); - cfg->reg_func.i2c_get(dev_id, - phy_info[dev_id]->phy_address[port_id], reg_pad | 3, &rev_id); - if(((org_id << 16) | rev_id) == INVALID_PHY_ID) { - return QCA8081_PHY_V1_1; - } - } - else -#endif - { - cfg->reg_func.mdio_get(dev_id, - phy_info[dev_id]->phy_address[port_id], reg_pad | 2, &org_id); - cfg->reg_func.mdio_get(dev_id, - phy_info[dev_id]->phy_address[port_id], reg_pad | 3, &rev_id); - } - - phy_id = (org_id<<16) | rev_id; - - return phy_id; -} - -phy_type_t hsl_phytype_get_by_phyid(a_uint32_t dev_id, a_uint32_t phy_id) -{ - phy_type_t phytype = MAX_PHY_CHIP; - - switch (phy_id) - { -/*qca808x_end*/ - case F1V1_PHY: - case F1V2_PHY: - case F1V3_PHY: - case F1V4_PHY: - phytype = F1_PHY_CHIP; - break; - case F2V1_PHY: - phytype = F2_PHY_CHIP; - break; - case MALIBU2PORT_PHY: - case MALIBU5PORT_PHY: - phytype = MALIBU_PHY_CHIP; - break; - case AQUANTIA_PHY_107: - case AQUANTIA_PHY_108: - case AQUANTIA_PHY_109: - case AQUANTIA_PHY_111: - case AQUANTIA_PHY_111B0: - case AQUANTIA_PHY_112: - case AQUANTIA_PHY_113C_A0: - case AQUANTIA_PHY_113C_A1: - case AQUANTIA_PHY_112C: - phytype = AQUANTIA_PHY_CHIP; - break; - case QCA8030_PHY: - case QCA8033_PHY: - case QCA8035_PHY: - phytype = QCA803X_PHY_CHIP; - break; - case SFP_PHY: - phytype = SFP_PHY_CHIP; - break; - case MP_GEPHY: - phytype = MPGE_PHY_CHIP; - break; -/*qca808x_start*/ - case QCA8081_PHY_V1_1: - phytype = QCA808X_PHY_CHIP; - break; - default: - phytype = MAX_PHY_CHIP; - } - - return phytype; -} -/*qca808x_end*/ -sw_error_t hsl_phydriver_update(a_uint32_t dev_id, a_uint32_t port_id, - a_uint32_t mode) -{ - a_uint32_t phy_id; - phy_type_t phytype; - ssdk_init_cfg cfg; - - cfg.chip_type = CHIP_HPPE; - if(port_id == SSDK_PHYSICAL_PORT5) - { - cfg.mac_mode1 = mode; - } - else if(port_id == SSDK_PHYSICAL_PORT6) - { - cfg.mac_mode2 = mode; - } - else - { - return SW_NOT_SUPPORTED; - } - if (hsl_port_phy_access_type_get(dev_id, port_id) == PHY_I2C_ACCESS) - { - cfg.reg_func.i2c_get = hsl_phy_i2c_get; - } - else - { - cfg.reg_func.mdio_get = reduce_hsl_phy_get; - } - phy_id = hsl_phyid_get(dev_id, port_id, &cfg); - phytype = hsl_phytype_get_by_phyid(dev_id, phy_id); - SSDK_DEBUG("port_id is %x, phy_id is %x, phy_type is:%x\n", - port_id, phy_id, phytype); - if (MAX_PHY_CHIP != phytype) - { - phy_info[dev_id]->phy_type[port_id] = phytype; - ssdk_phy_driver[phytype].port_bmp[dev_id] |= (0x1 << port_id); - } - - return SW_OK; -} -/*qca808x_start*/ -int ssdk_phy_driver_init(a_uint32_t dev_id, ssdk_init_cfg *cfg) -{ - - int i = 0; - a_uint32_t phy_id = 0; - phy_type_t phytype = MAX_PHY_CHIP; - - for (i = 0; i < SW_MAX_NR_PORT; i++) - { - if (port_bmp[dev_id] & (0x1 << i)) - { -/*qca808x_end*/ - if(ssdk_port_feature_get(dev_id, i, PHY_F_FORCE)) { - continue; - } -/*qca808x_start*/ - phy_id = hsl_phyid_get(dev_id, i, cfg); - phytype = hsl_phytype_get_by_phyid(dev_id, phy_id); - if (MAX_PHY_CHIP != phytype) { - phy_info[dev_id]->phy_type[i] = phytype; - ssdk_phy_driver[phytype].port_bmp[dev_id] |= (0x1 << i); - } else { - SSDK_INFO("dev_id = %d, phy_adress = %d, phy_id = 0x%x phy" - "type doesn't match\n", dev_id, - phy_info[dev_id]->phy_address[i], phy_id); - } - } - } - - for(i = 0; i < MAX_PHY_CHIP;i++) { - if(ssdk_phy_driver[i].port_bmp[dev_id] != 0 && - ssdk_phy_driver[i].init != NULL) { - ssdk_phy_driver[i].init(dev_id, ssdk_phy_driver[i].port_bmp[dev_id]); - } - } - return 0; -} - -#ifdef QCA808X_PORTS_INFO -typedef struct { - a_uint32_t port_id; - a_uint32_t phy_address; - a_uint8_t phy_access_type; -} qca808x_phy_info_t; -/*5 is port_id, 0x1c is qca808x phy address, PHY_MDIO_ACCESS is mdio -mode to access qca808x phy, PHY_I2C_ACCESS is I2C mode to access -qca808x phy*/ -static qca808x_phy_info_t qca808x_phy_info[] = { - {5,0x7c,PHY_I2C_ACCESS} -}; -static int qca_ssdk_qca808x_phy_info_init(a_uint32_t dev_id) -{ - a_uint32_t port_bmp = 0, port_id = 0, port_index = 0, port_index_max = 0; - - port_index_max = sizeof(qca808x_phy_info)/(sizeof(qca808x_phy_info_t)); - for(port_index = 0; port_index < port_index_max; port_index++) { - port_id = qca808x_phy_info[port_index].port_id; - port_bmp |= (1 << port_id); - /*qca808x phy address*/ - phy_info[dev_id]->phy_address[port_id] = - qca808x_phy_info[port_index].phy_address; - /*qca808x access mode, 1:i2c, 0:mdio*/ - phy_info[dev_id]->phy_access_type[port_id] = - qca808x_phy_info[port_index].phy_access_type; - } - qca_ssdk_port_bmp_set(dev_id, port_bmp); - - return 0; -} -#endif - -int qca_ssdk_phy_info_init(a_uint32_t dev_id) -{ - a_uint32_t j = 0; - phy_info_t *phy_information; - - phy_information = kzalloc(sizeof(phy_info_t), GFP_KERNEL); - if (phy_information == NULL) { - SSDK_ERROR("phy_information kzalloc failed!\n"); - return -ENOMEM; - } - memset(phy_information, 0, sizeof(*phy_information)); - phy_info[dev_id] = phy_information; - - for (j = SSDK_PHYSICAL_PORT0; j < SW_MAX_NR_PORT; j ++) - { - phy_info[dev_id]->phy_type[j] = MAX_PHY_CHIP; - if(j == SSDK_PHYSICAL_PORT0) - { - phy_info[dev_id]->phy_address[j] = INVALID_PHY_ADDR; - } - else - { - phy_info[dev_id]->phy_address[j] = j - 1; - } - } -#ifdef QCA808X_PORTS_INFO - qca_ssdk_qca808x_phy_info_init(dev_id); -#endif - - return 0; -} -void qca_ssdk_port_bmp_init(a_uint32_t dev_id) -{ - port_bmp[dev_id] = 0x3e; - - return; -} -/*qca808x_end*/ -void hsl_phy_address_init(a_uint32_t dev_id, a_uint32_t i, - a_uint32_t value) -{ - phy_info[dev_id]->phy_address[i] = value; - - return; -} -/*qca808x_start*/ -void qca_ssdk_port_bmp_set(a_uint32_t dev_id, a_uint32_t value) -{ - port_bmp[dev_id] = value; - - return; -} - -a_uint32_t qca_ssdk_port_bmp_get(a_uint32_t dev_id) -{ - - return port_bmp[dev_id]; -} -/*qca808x_end*/ -a_uint32_t qca_ssdk_phy_type_port_bmp_get(a_uint32_t dev_id, - phy_type_t phy_type) -{ - - return ssdk_phy_driver[phy_type].port_bmp[dev_id]; -} - -void -qca_ssdk_phy_address_set(a_uint32_t dev_id, a_uint32_t port_id, - a_uint32_t phy_addr) -{ - phy_info[dev_id]->phy_address[port_id] = phy_addr; - - return; -} - -a_uint32_t -qca_ssdk_port_to_phy_mdio_fake_addr(a_uint32_t dev_id, a_uint32_t port_id) -{ - return phy_info[dev_id]->phy_mdio_fake_address[port_id]; -} - -void qca_ssdk_phy_mdio_fake_address_set(a_uint32_t dev_id, a_uint32_t i, - a_uint32_t value) -{ - phy_info[dev_id]->phy_mdio_fake_address[i] = value; - - return; -} - -a_uint32_t -qca_ssdk_phy_mdio_fake_addr_to_port(a_uint32_t dev_id, a_uint32_t phy_mdio_fake_addr) -{ - a_uint32_t i = 0; - - for (i = 0; i < SW_MAX_NR_PORT; i ++) - { - if (phy_info[dev_id]->phy_mdio_fake_address[i] == phy_mdio_fake_addr) - return i; - } - SSDK_ERROR("doesn't match port_id to specified phy_mdio_fake_addr !\n"); - return 0; -} -/*qca808x_start*/ -a_uint32_t -qca_ssdk_port_to_phy_addr(a_uint32_t dev_id, a_uint32_t port_id) -{ - return phy_info[dev_id]->phy_address[port_id]; -} - -a_uint32_t -qca_ssdk_phy_addr_to_port(a_uint32_t dev_id, a_uint32_t phy_addr) -{ - a_uint32_t i = 0; - - for (i = 0; i < SW_MAX_NR_PORT; i ++) - { - if (phy_info[dev_id]->phy_address[i] == phy_addr) - return i; - } - SSDK_ERROR("doesn't match port_id to specified phy_addr !\n"); - return 0; -} - -a_bool_t -hsl_port_phy_combo_capability_get(a_uint32_t dev_id, a_uint32_t port_id) -{ - if (dev_id >= SW_MAX_NR_DEV) - return A_FALSE; - - return phy_info[dev_id]->phy_combo[port_id]; -} - -void -hsl_port_phy_combo_capability_set(a_uint32_t dev_id, a_uint32_t port_id, - a_bool_t enable) -{ - if (dev_id >= SW_MAX_NR_DEV) - return; - - phy_info[dev_id]->phy_combo[port_id] = enable; - - return; -} - -a_uint8_t -hsl_port_phy_access_type_get(a_uint32_t dev_id, a_uint32_t port_id) -{ - if (dev_id >= SW_MAX_NR_DEV) - return 0; - - return phy_info[dev_id]->phy_access_type[port_id]; -} - -void -hsl_port_phy_access_type_set(a_uint32_t dev_id, a_uint32_t port_id, - a_uint8_t access_type) -{ - if (dev_id >= SW_MAX_NR_DEV) - return; - - phy_info[dev_id]->phy_access_type[port_id] = access_type; - - return; -} -/*qca808x_end*/ -void -hsl_port_phy_c45_capability_set(a_uint32_t dev_id, a_uint32_t port_id, - a_bool_t enable) -{ - phy_info[dev_id]->phy_c45[port_id] = enable; - - return; -} -sw_error_t -hsl_port_phy_serdes_reset(a_uint32_t dev_id) -{ - sw_error_t rv; - int i = 0; - hsl_phy_ops_t *phy_drv; - - for (i = 0; i < SW_MAX_NR_PORT; i++) - { - if (phy_info[dev_id]->phy_type[i] == MALIBU_PHY_CHIP) - { - SW_RTN_ON_NULL(phy_drv = hsl_phy_api_ops_get (dev_id, i)); - if (NULL == phy_drv->phy_serdes_reset) - return SW_NOT_SUPPORTED; - rv = phy_drv->phy_serdes_reset(dev_id); - return rv; - } - } - - return SW_OK; -} - -sw_error_t hsl_port_phy_hw_init(a_uint32_t dev_id, a_uint32_t port_id) -{ - phy_type_t phytype; - - phytype = hsl_phy_type_get(dev_id, port_id); - - if(ssdk_phy_driver[phytype].port_bmp[dev_id] != 0 && - ssdk_phy_driver[phytype].init != NULL) - { - ssdk_phy_driver[phytype].init(dev_id, - ssdk_phy_driver[phytype].port_bmp[dev_id]); - } - - return SW_OK; -} - -a_uint32_t -hsl_port_phyid_get(a_uint32_t dev_id, fal_port_t port_id) -{ - sw_error_t rv = SW_OK; - a_uint32_t phy_addr, phy_id; - hsl_phy_ops_t *phy_drv; - - phy_drv = hsl_phy_api_ops_get (dev_id, port_id); - if (phy_drv == NULL) { - return INVALID_PHY_ID; - } - if (NULL == phy_drv->phy_id_get) { - return INVALID_PHY_ID; - } - - rv = hsl_port_prop_get_phyid (dev_id, port_id, &phy_addr); - if(rv) { - return INVALID_PHY_ID; - } - - rv = phy_drv->phy_id_get (dev_id, phy_addr, &phy_id); - if(rv) { - return INVALID_PHY_ID; - } - - return phy_id; -} - -sw_error_t -hsl_port_phy_mode_set(a_uint32_t dev_id, fal_port_interface_mode_t mode) -{ - sw_error_t rv; - a_uint32_t i = 0, phy_addr = 0; - hsl_phy_ops_t *phy_drv; - - for (i = 0; i < SW_MAX_NR_PORT; i++) - { - if (phy_info[dev_id]->phy_type[i] == MALIBU_PHY_CHIP) - { - SW_RTN_ON_NULL(phy_drv = hsl_phy_api_ops_get (dev_id, i)); - if (NULL == phy_drv->phy_interface_mode_set) - return SW_NOT_SUPPORTED; - - phy_addr = qca_ssdk_port_to_phy_addr(dev_id, i); - rv = phy_drv->phy_interface_mode_set(dev_id, phy_addr, mode); - return rv; - } - } - - return SW_OK; -} -phy_type_t hsl_phy_type_get(a_uint32_t dev_id, a_uint32_t port_id) -{ - - if (dev_id >= SW_MAX_NR_DEV) - return MAX_PHY_CHIP; - - return phy_info[dev_id]->phy_type[port_id]; -} - -a_uint32_t hsl_port_phy_reset_gpio_get(a_uint32_t dev_id, a_uint32_t port_id) -{ - return phy_info[dev_id]->phy_reset_gpio[port_id]; -} - -void hsl_port_phy_reset_gpio_set(a_uint32_t dev_id, a_uint32_t port_id, - a_uint32_t phy_reset_gpio) -{ - phy_info[dev_id]->phy_reset_gpio[port_id] = phy_reset_gpio; - - return; -} - -void hsl_port_phy_gpio_reset(a_uint32_t dev_id, a_uint32_t port_id) - -{ - a_uint32_t gpio_num, ret = 0; - - gpio_num = hsl_port_phy_reset_gpio_get(dev_id, port_id); - - if(gpio_num == SSDK_INVALID_GPIO) - { - return; - } - ret = gpio_request(gpio_num, "phy_reset_gpio"); - if(ret) - { - SSDK_ERROR("gpio request failed, ret:%d\n", ret); - return; - } - ret = gpio_direction_output(gpio_num, SSDK_GPIO_RESET); - if(ret) - { - SSDK_ERROR("when reset, gpio set failed, ret:%d\n", - ret); - return; - } - msleep(200); - gpio_set_value(gpio_num, SSDK_GPIO_RELEASE); - SSDK_INFO("GPIO%d reset PHY done\n", gpio_num); - - gpio_free(gpio_num); - - return; -} - -void -hsl_port_phy_dac_get(a_uint32_t dev_id, a_uint32_t port_id, - phy_dac_t *phy_dac) -{ - phy_dac->mdac = phy_info[dev_id]->phy_dac[port_id].mdac; - phy_dac->edac = phy_info[dev_id]->phy_dac[port_id].edac; - - return; -} - -void -hsl_port_phy_dac_set(a_uint32_t dev_id, a_uint32_t port_id, - phy_dac_t phy_dac) -{ - phy_info[dev_id]->phy_dac[port_id].mdac = phy_dac.mdac; - phy_info[dev_id]->phy_dac[port_id].edac = phy_dac.edac; - - return; -} - -#if (LINUX_VERSION_CODE >= KERNEL_VERSION(5, 0, 0)) -static sw_error_t -hsl_phy_adv_to_linkmode_adv(a_uint32_t autoadv, a_ulong_t *advertising) -{ - linkmode_mod_bit(ETHTOOL_LINK_MODE_Pause_BIT, - advertising, autoadv & FAL_PHY_ADV_PAUSE); - linkmode_mod_bit(ETHTOOL_LINK_MODE_Asym_Pause_BIT, - advertising, autoadv & FAL_PHY_ADV_ASY_PAUSE); - - linkmode_mod_bit(ETHTOOL_LINK_MODE_10baseT_Half_BIT, - advertising, autoadv & FAL_PHY_ADV_10T_HD); - linkmode_mod_bit(ETHTOOL_LINK_MODE_10baseT_Full_BIT, - advertising, autoadv & FAL_PHY_ADV_10T_FD); - - linkmode_mod_bit(ETHTOOL_LINK_MODE_100baseT_Half_BIT, - advertising, autoadv & FAL_PHY_ADV_100TX_HD); - linkmode_mod_bit(ETHTOOL_LINK_MODE_100baseT_Full_BIT, - advertising, autoadv & FAL_PHY_ADV_100TX_FD); - - linkmode_mod_bit(ETHTOOL_LINK_MODE_1000baseT_Full_BIT, - advertising, autoadv & FAL_PHY_ADV_1000T_FD); - - linkmode_mod_bit(ETHTOOL_LINK_MODE_2500baseT_Full_BIT, - advertising, autoadv & FAL_PHY_ADV_2500T_FD); - - linkmode_mod_bit(ETHTOOL_LINK_MODE_5000baseT_Full_BIT, - advertising, autoadv & FAL_PHY_ADV_5000T_FD); - - linkmode_mod_bit(ETHTOOL_LINK_MODE_10000baseT_Full_BIT, - advertising, autoadv & FAL_PHY_ADV_10000T_FD); - - SSDK_DEBUG("autoadv:0x%x, advertising::0x%lx\n", - autoadv, *advertising); - - return SW_OK; -} - -static sw_error_t -hsl_port_phydev_get(a_uint32_t dev_id, a_uint32_t port_id, - struct phy_device **phydev) -{ - struct qca_phy_priv *priv; - a_uint32_t phy_addr; - - priv = ssdk_phy_priv_data_get(dev_id); - SW_RTN_ON_NULL(priv); - -#if defined(IN_PHY_I2C_MODE) - if (hsl_port_phy_access_type_get(dev_id, port_id) == PHY_I2C_ACCESS) - { - phy_addr = qca_ssdk_port_to_phy_mdio_fake_addr(dev_id, port_id); - } - else -#endif - { - phy_addr = qca_ssdk_port_to_phy_addr(dev_id, port_id); - } - SW_RTN_ON_NULL(phydev); - *phydev = mdiobus_get_phy(priv->miibus, phy_addr); - if(*phydev == NULL) - { - SSDK_ERROR("port %d phydev is NULL\n", port_id); - return SW_NOT_INITIALIZED; - } - SSDK_DEBUG("phy[%d]: device %s, driver %s\n", - (*phydev)->mdio.addr, phydev_name(*phydev), - (*phydev)->drv ? (*phydev)->drv->name : "unknown"); - - return SW_OK; -} - -sw_error_t -hsl_port_phydev_adv_update(a_uint32_t dev_id, a_uint32_t port_id, - a_uint32_t autoadv) -{ - sw_error_t rv = SW_OK; - struct phy_device *phydev; - - rv = hsl_port_phydev_get(dev_id, port_id, &phydev); - SW_RTN_ON_ERROR(rv); - rv = hsl_phy_adv_to_linkmode_adv(autoadv, phydev->advertising); - - return rv; -} -#endif - -/*qca808x_start*/ -sw_error_t ssdk_phy_driver_cleanup(void) -{ - a_uint32_t i = 0, j = 0; - - for (i = 0; i < MAX_PHY_CHIP;i++) { - for (j = 0; j < SW_MAX_NR_DEV; j++) { - if (ssdk_phy_driver[i].port_bmp[j] != 0 && - ssdk_phy_driver[i].exit != NULL) { - ssdk_phy_driver[i].exit(j, ssdk_phy_driver[i].port_bmp[j]); - } - } - if(ssdk_phy_driver[i].phy_ops != NULL) - { - kfree(ssdk_phy_driver[i].phy_ops); - ssdk_phy_driver[i].phy_ops = NULL; - } - } - - for(i = 0; i < SW_MAX_NR_DEV;i++) { - - if(phy_info[i] != NULL) - { - kfree(phy_info[i]); - phy_info[i] = NULL; - } - } - return SW_OK; -} -/*qca808x_end*/ diff --git a/feeds/ipq807x/qca-ssdk/src/src/hsl/phy/malibu_phy.c b/feeds/ipq807x/qca-ssdk/src/src/hsl/phy/malibu_phy.c deleted file mode 100644 index 1f4dba156..000000000 --- a/feeds/ipq807x/qca-ssdk/src/src/hsl/phy/malibu_phy.c +++ /dev/null @@ -1,2871 +0,0 @@ -/* - * Copyright (c) 2015-2019, The Linux Foundation. All rights reserved. - * Permission to use, copy, modify, and/or distribute this software for - * any purpose with or without fee is hereby granted, provided that the - * above copyright notice and this permission notice appear in all copies. - * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES - * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR - * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES - * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN - * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT - * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. - */ - -#include "sw.h" -#include "fal_port_ctrl.h" -#include "hsl_api.h" -#include "hsl.h" -#include "malibu_phy.h" -#include "hsl_phy.h" -#include "ssdk_plat.h" - -static a_uint32_t first_phy_addr = MAX_PHY_ADDR; - -static a_uint16_t -_phy_reg_read(a_uint32_t dev_id, a_uint32_t phy_addr, a_uint32_t reg) -{ - sw_error_t rv; - a_uint16_t phy_data = 0; - - HSL_PHY_GET(rv, dev_id, phy_addr, reg, &phy_data); - if (SW_OK != rv) - return 0xFFFF; - - return phy_data; - -} - -static sw_error_t -_phy_reg_write(a_uint32_t dev_id, a_uint32_t phy_addr, a_uint32_t reg, - a_uint16_t phy_data) -{ - sw_error_t rv; - - HSL_PHY_SET(rv, dev_id, phy_addr, reg, phy_data); - - return rv; -} - -/* #define malibu_phy_reg_read _phy_reg_read */ -/* #define malibu_phy_reg_write _phy_reg_write */ - -/****************************************************************************** -* -* malibu_phy_mii_read - mii register read -* -* mii register read -*/ -a_uint16_t -malibu_phy_reg_read(a_uint32_t dev_id, a_uint32_t phy_id, a_uint32_t reg_id) -{ - return _phy_reg_read(dev_id, phy_id, reg_id); - -} - -/****************************************************************************** -* -* malibu_phy_mii_write - mii register write -* -* mii register write -*/ -sw_error_t -malibu_phy_reg_write(a_uint32_t dev_id, a_uint32_t phy_id, a_uint32_t reg_id, - a_uint16_t reg_val) -{ - - _phy_reg_write(dev_id,phy_id, reg_id, reg_val); - - return SW_OK; -} - -/****************************************************************************** -* -* phy4 medium is fiber 100fx -* -* get phy4 medium is 100fx -*/ -static a_bool_t __medium_is_fiber_100fx(a_uint32_t dev_id, a_uint32_t phy_id) -{ - a_uint16_t phy_data = 0; - - phy_data = malibu_phy_reg_read(dev_id, phy_id, MALIBU_PHY_SGMII_STATUS); - - if (phy_data & MALIBU_PHY4_AUTO_FX100_SELECT) { - return A_TRUE; - } - /* Link down */ - if ((!(phy_data & MALIBU_PHY4_AUTO_COPPER_SELECT)) && - (!(phy_data & MALIBU_PHY4_AUTO_BX1000_SELECT)) && - (!(phy_data & MALIBU_PHY4_AUTO_SGMII_SELECT))) { - - phy_data = - malibu_phy_reg_read(dev_id, phy_id, MALIBU_PHY_CHIP_CONFIG); - if ((phy_data & MALIBU_PHY4_PREFER_FIBER) - && (!(phy_data & MALIBU_PHY4_FIBER_MODE_1000BX))) { - return A_TRUE; - } - } - - return A_FALSE; -} - -/****************************************************************************** -* -* phy4 prfer medium -* -* get phy4 prefer medum, fiber or copper; -*/ -static malibu_phy_medium_t __phy_prefer_medium_get(a_uint32_t dev_id, - a_uint32_t phy_id) -{ - a_uint16_t phy_medium = 0; - - phy_medium = - malibu_phy_reg_read(dev_id, phy_id, MALIBU_PHY_CHIP_CONFIG); - - return ((phy_medium & MALIBU_PHY4_PREFER_FIBER) ? - MALIBU_PHY_MEDIUM_FIBER : MALIBU_PHY_MEDIUM_COPPER); -} - -/****************************************************************************** -* -* phy4 activer medium -* -* get phy4 current active medium, fiber or copper; -*/ -static malibu_phy_medium_t __phy_active_medium_get(a_uint32_t dev_id, - a_uint32_t phy_id) -{ - a_uint16_t phy_data = 0; - a_uint16_t phy_mode = 0; - - phy_mode = malibu_phy_reg_read(dev_id, phy_id, MALIBU_PHY_CHIP_CONFIG); - phy_mode &= 0x000f; - - if (phy_mode == MALIBU_PHY_PSGMII_AMDET) { - - phy_data = malibu_phy_reg_read(dev_id, phy_id, MALIBU_PHY_SGMII_STATUS); - - if ((phy_data & MALIBU_PHY4_AUTO_COPPER_SELECT)) { - return MALIBU_PHY_MEDIUM_COPPER; - } else if ((phy_data & MALIBU_PHY4_AUTO_BX1000_SELECT)) { - return MALIBU_PHY_MEDIUM_FIBER; /*PHY_MEDIUM_FIBER_BX1000 */ - } else if ((phy_data & MALIBU_PHY4_AUTO_FX100_SELECT)) { - return MALIBU_PHY_MEDIUM_FIBER; /*PHY_MEDIUM_FIBER_FX100 */ - } - /* link down */ - return __phy_prefer_medium_get(dev_id, phy_id); - } else if ((phy_mode == MALIBU_PHY_PSGMII_BASET) ||(phy_mode == MALIBU_PHY_SGMII_BASET) ) { - return MALIBU_PHY_MEDIUM_COPPER; - } else if ((phy_mode == MALIBU_PHY_PSGMII_BX1000) ||(phy_mode == MALIBU_PHY_PSGMII_FX100)) { - return MALIBU_PHY_MEDIUM_FIBER; - } else { - return MALIBU_PHY_MEDIUM_COPPER; - } -} - -/****************************************************************************** -* -* phy4 copper page or fiber page select -* -* set phy4 copper or fiber page -*/ - -static sw_error_t __phy_reg_pages_sel(a_uint32_t dev_id, a_uint32_t phy_id, - malibu_phy_reg_pages_t phy_reg_pages) -{ - a_uint16_t reg_pages = 0; - reg_pages = malibu_phy_reg_read(dev_id, phy_id, MALIBU_PHY_CHIP_CONFIG); - - if (phy_reg_pages == MALIBU_PHY_COPPER_PAGES) { - reg_pages |= 0x8000; - } else if (phy_reg_pages == MALIBU_PHY_SGBX_PAGES) { - reg_pages &= ~0x8000; - } else - return SW_BAD_PARAM; - - malibu_phy_reg_write(dev_id, phy_id, MALIBU_PHY_CHIP_CONFIG, reg_pages); - - return SW_OK; -} - -/****************************************************************************** -* -* phy4 reg pages selection by active medium -* -* phy4 reg pages selection -*/ -static sw_error_t __phy_reg_pages_sel_by_active_medium(a_uint32_t dev_id, - a_uint32_t phy_id) -{ - malibu_phy_medium_t phy_medium; - malibu_phy_reg_pages_t reg_pages; - - phy_medium = __phy_active_medium_get(dev_id, phy_id); - if (phy_medium == MALIBU_PHY_MEDIUM_FIBER) { - reg_pages = MALIBU_PHY_SGBX_PAGES; - } else if (phy_medium == MALIBU_PHY_MEDIUM_COPPER) { - - reg_pages = MALIBU_PHY_COPPER_PAGES; - } else - - return SW_BAD_VALUE; - - return __phy_reg_pages_sel(dev_id, phy_id, reg_pages); -} - -/****************************************************************************** -* -* malibu_phy_debug_write - debug port write -* -* debug port write -*/ -sw_error_t -malibu_phy_debug_write(a_uint32_t dev_id, a_uint32_t phy_id, a_uint16_t reg_id, - a_uint16_t reg_val) -{ - malibu_phy_reg_write(dev_id, phy_id, MALIBU_DEBUG_PORT_ADDRESS, reg_id); - malibu_phy_reg_write(dev_id, phy_id, MALIBU_DEBUG_PORT_DATA, reg_val); - - return SW_OK; -} - -/****************************************************************************** -* -* malibu_phy_debug_read - debug port read -* -* debug port read -*/ -a_uint16_t -malibu_phy_debug_read(a_uint32_t dev_id, a_uint32_t phy_id, a_uint16_t reg_id) -{ - malibu_phy_reg_write(dev_id, phy_id, MALIBU_DEBUG_PORT_ADDRESS, reg_id); - return malibu_phy_reg_read(dev_id, phy_id, MALIBU_DEBUG_PORT_DATA); -} - -/****************************************************************************** -* -* malibu_phy_mmd_write - PHY MMD register write -* -* PHY MMD register write -*/ -sw_error_t -malibu_phy_mmd_write(a_uint32_t dev_id, a_uint32_t phy_id, - a_uint16_t mmd_num, a_uint16_t reg_id, a_uint16_t reg_val) -{ - malibu_phy_reg_write(dev_id, phy_id, MALIBU_MMD_CTRL_REG, mmd_num); - malibu_phy_reg_write(dev_id, phy_id, MALIBU_MMD_DATA_REG, reg_id); - malibu_phy_reg_write(dev_id, phy_id, MALIBU_MMD_CTRL_REG, - 0x4000 | mmd_num); - malibu_phy_reg_write(dev_id, phy_id, MALIBU_MMD_DATA_REG, reg_val); - - return SW_OK; -} - -/****************************************************************************** -* -* malibu_phy_mmd_read - PHY MMD register read -* -* PHY MMD register read -*/ -a_uint16_t -malibu_phy_mmd_read(a_uint32_t dev_id, a_uint32_t phy_id, - a_uint16_t mmd_num, a_uint16_t reg_id) -{ - malibu_phy_reg_write(dev_id, phy_id, MALIBU_MMD_CTRL_REG, mmd_num); - malibu_phy_reg_write(dev_id, phy_id, MALIBU_MMD_DATA_REG, reg_id); - malibu_phy_reg_write(dev_id, phy_id, MALIBU_MMD_CTRL_REG, - 0x4000 | mmd_num); - - return malibu_phy_reg_read(dev_id, phy_id, MALIBU_MMD_DATA_REG); -} - -/****************************************************************************** -* -* malibu_phy_get_speed - Determines the speed of phy ports associated with the -* specified device. -*/ - -sw_error_t -malibu_phy_get_speed(a_uint32_t dev_id, a_uint32_t phy_id, - fal_port_speed_t * speed) -{ - a_uint16_t phy_data; - - if (phy_id == COMBO_PHY_ID) { - __phy_reg_pages_sel_by_active_medium(dev_id, phy_id); - } - phy_data = malibu_phy_reg_read(dev_id, phy_id, MALIBU_PHY_SPEC_STATUS); - - switch (phy_data & MALIBU_STATUS_SPEED_MASK) { - case MALIBU_STATUS_SPEED_1000MBS: - *speed = FAL_SPEED_1000; - break; - case MALIBU_STATUS_SPEED_100MBS: - *speed = FAL_SPEED_100; - break; - case MALIBU_STATUS_SPEED_10MBS: - *speed = FAL_SPEED_10; - break; - default: - return SW_READ_ERROR; - } - - return SW_OK; -} - -/****************************************************************************** -* -* malibu_phy_get_duplex - Determines the speed of phy ports associated with the -* specified device. -*/ -sw_error_t -malibu_phy_get_duplex(a_uint32_t dev_id, a_uint32_t phy_id, - fal_port_duplex_t * duplex) -{ - a_uint16_t phy_data; - - if (phy_id == COMBO_PHY_ID) { - __phy_reg_pages_sel_by_active_medium(dev_id, phy_id); - } - - phy_data = malibu_phy_reg_read(dev_id, phy_id, MALIBU_PHY_SPEC_STATUS); - - //read duplex - if (phy_data & MALIBU_STATUS_FULL_DUPLEX) - *duplex = FAL_FULL_DUPLEX; - else - *duplex = FAL_HALF_DUPLEX; - - return SW_OK; -} -#ifndef IN_PORTCONTROL_MINI -/****************************************************************************** -* -* malibu_phy_reset - reset the phy -* -* reset the phy -*/ -sw_error_t malibu_phy_reset(a_uint32_t dev_id, a_uint32_t phy_id) -{ - a_uint16_t phy_data; - - if (phy_id == COMBO_PHY_ID) - __phy_reg_pages_sel_by_active_medium(dev_id, phy_id); - - phy_data = malibu_phy_reg_read(dev_id, phy_id, MALIBU_PHY_CONTROL); - malibu_phy_reg_write(dev_id, phy_id, MALIBU_PHY_CONTROL, - phy_data | MALIBU_CTRL_SOFTWARE_RESET); - - return SW_OK; -} -#endif -/****************************************************************************** -* -* malibu_phy_set_powersave - set power saving status -* -* set power saving status -*/ -sw_error_t -malibu_phy_set_powersave(a_uint32_t dev_id, a_uint32_t phy_id, a_bool_t enable) -{ - a_uint16_t phy_data; - a_bool_t status; - - if (phy_id == COMBO_PHY_ID) { - if (MALIBU_PHY_MEDIUM_COPPER != - __phy_active_medium_get(dev_id, phy_id)) - return SW_NOT_SUPPORTED; - } - - if (enable == A_TRUE) { - malibu_phy_get_8023az (dev_id,phy_id,&status); - if (status == A_FALSE) { - phy_data = malibu_phy_mmd_read(dev_id, phy_id, MALIBU_PHY_MMD3_NUM, - MALIBU_PHY_MMD3_ADDR_8023AZ_TIMER_CTRL); - phy_data &= ~(1<<14); - malibu_phy_mmd_write(dev_id, phy_id, MALIBU_PHY_MMD3_NUM, - MALIBU_PHY_MMD3_ADDR_8023AZ_TIMER_CTRL, phy_data); - } - phy_data = malibu_phy_mmd_read(dev_id, phy_id, MALIBU_PHY_MMD3_NUM, - MALIBU_PHY_MMD3_ADDR_CLD_CTRL5); - phy_data &= ~(1<<14); - malibu_phy_mmd_write(dev_id, phy_id, MALIBU_PHY_MMD3_NUM, - MALIBU_PHY_MMD3_ADDR_CLD_CTRL5, phy_data); - phy_data = malibu_phy_mmd_read(dev_id, phy_id, MALIBU_PHY_MMD3_NUM, - MALIBU_PHY_MMD3_ADDR_CLD_CTRL3); - phy_data &= ~(1<<15); - malibu_phy_mmd_write(dev_id, phy_id, MALIBU_PHY_MMD3_NUM, - MALIBU_PHY_MMD3_ADDR_CLD_CTRL3, phy_data); - - } else { - phy_data = malibu_phy_mmd_read(dev_id, phy_id, MALIBU_PHY_MMD3_NUM, - MALIBU_PHY_MMD3_ADDR_8023AZ_TIMER_CTRL); - phy_data|= (1<<14); - malibu_phy_mmd_write(dev_id, phy_id, MALIBU_PHY_MMD3_NUM, - MALIBU_PHY_MMD3_ADDR_8023AZ_TIMER_CTRL, phy_data); - phy_data = malibu_phy_mmd_read(dev_id, phy_id, MALIBU_PHY_MMD3_NUM, - MALIBU_PHY_MMD3_ADDR_CLD_CTRL5); - phy_data|= (1<<14); - malibu_phy_mmd_write(dev_id, phy_id, MALIBU_PHY_MMD3_NUM, - MALIBU_PHY_MMD3_ADDR_CLD_CTRL5, phy_data); - phy_data = malibu_phy_mmd_read(dev_id, phy_id, MALIBU_PHY_MMD3_NUM, - MALIBU_PHY_MMD3_ADDR_CLD_CTRL3); - phy_data|= (1<<15); - malibu_phy_mmd_write(dev_id, phy_id, MALIBU_PHY_MMD3_NUM, - MALIBU_PHY_MMD3_ADDR_CLD_CTRL3, phy_data); - - } - malibu_phy_reg_write(dev_id, phy_id, MALIBU_PHY_CONTROL, 0x9040); - - return SW_OK; -} -#ifndef IN_PORTCONTROL_MINI -/****************************************************************************** -* -* malibu_phy_get_powersave - get power saving status -* -* set power saving status -*/ -sw_error_t -malibu_phy_get_powersave(a_uint32_t dev_id, a_uint32_t phy_id, - a_bool_t * enable) -{ - a_uint16_t phy_data; - a_uint16_t phy_data1; - - if (phy_id == COMBO_PHY_ID) { - if (MALIBU_PHY_MEDIUM_COPPER != - __phy_active_medium_get(dev_id, phy_id)) - return SW_NOT_SUPPORTED; - } - - phy_data = malibu_phy_mmd_read(dev_id, phy_id, MALIBU_PHY_MMD3_NUM, - MALIBU_PHY_MMD3_ADDR_CLD_CTRL5); - phy_data1 = malibu_phy_mmd_read(dev_id, phy_id, MALIBU_PHY_MMD3_NUM, - MALIBU_PHY_MMD3_ADDR_CLD_CTRL3); - if (!(phy_data& 0x4000) && !(phy_data1 & 0x8000)) { - *enable = A_TRUE; - } - if ((phy_data& 0x4000) && (phy_data1 & 0x8000)) { - *enable = A_FALSE; - } - return SW_OK; -} -#endif -/****************************************************************************** -* -* malibu_phy_set_802.3az -* -* set 802.3az status -*/ -sw_error_t -malibu_phy_set_8023az(a_uint32_t dev_id, a_uint32_t phy_id, a_bool_t enable) -{ - a_uint16_t phy_data; - - if (phy_id == COMBO_PHY_ID) { - if (MALIBU_PHY_MEDIUM_COPPER != - __phy_active_medium_get(dev_id, phy_id)) - return SW_NOT_SUPPORTED; - } - - phy_data = malibu_phy_mmd_read(dev_id, phy_id, MALIBU_PHY_MMD7_NUM, - MALIBU_PHY_MMD7_ADDR_8023AZ_EEE_CTRL); - if (enable == A_TRUE) { - phy_data |= 0x0006; - - malibu_phy_mmd_write(dev_id, phy_id, MALIBU_PHY_MMD7_NUM, - MALIBU_PHY_MMD7_ADDR_8023AZ_EEE_CTRL, phy_data); - } else { - phy_data &= ~0x0006; - - malibu_phy_mmd_write(dev_id, phy_id, MALIBU_PHY_MMD7_NUM, - MALIBU_PHY_MMD7_ADDR_8023AZ_EEE_CTRL, phy_data); - } - - malibu_phy_restart_autoneg(dev_id, phy_id); - - return SW_OK; -} - -/****************************************************************************** -* -* malibu_phy_get_8023az status -* -* get 8023az status -*/ -sw_error_t -malibu_phy_get_8023az(a_uint32_t dev_id, a_uint32_t phy_id, a_bool_t * enable) -{ - a_uint16_t phy_data; - if (phy_id == COMBO_PHY_ID) { - if (MALIBU_PHY_MEDIUM_COPPER != - __phy_active_medium_get(dev_id, phy_id)) - return SW_NOT_SUPPORTED; - } - - *enable = A_FALSE; - - phy_data = malibu_phy_mmd_read(dev_id, phy_id, MALIBU_PHY_MMD7_NUM, - MALIBU_PHY_MMD7_ADDR_8023AZ_EEE_CTRL); - - if ((phy_data & 0x0004) && (phy_data & 0x0002)) - *enable = A_TRUE; - - return SW_OK; -} - -/****************************************************************************** -* -* malibu_phy_set_hibernate - set hibernate status -* -* set hibernate status -*/ -sw_error_t -malibu_phy_set_hibernate(a_uint32_t dev_id, a_uint32_t phy_id, a_bool_t enable) -{ - a_uint16_t phy_data; - - malibu_phy_reg_write(dev_id, phy_id, MALIBU_DEBUG_PORT_ADDRESS, - MALIBU_DEBUG_PHY_HIBERNATION_CTRL); - phy_data = malibu_phy_reg_read(dev_id, phy_id, MALIBU_DEBUG_PORT_DATA); - - if (enable == A_TRUE) { - phy_data |= 0x8000; - } else { - phy_data &= ~0x8000; - } - - malibu_phy_reg_write(dev_id, phy_id, MALIBU_DEBUG_PORT_DATA, phy_data); - - return SW_OK; -} -#ifndef IN_PORTCONTROL_MINI -/****************************************************************************** -* -* malibu_phy_get_hibernate - get hibernate status -* -* get hibernate status -*/ -sw_error_t -malibu_phy_get_hibernate(a_uint32_t dev_id, a_uint32_t phy_id, - a_bool_t * enable) -{ - a_uint16_t phy_data; - - *enable = A_FALSE; - - malibu_phy_reg_write(dev_id, phy_id, MALIBU_DEBUG_PORT_ADDRESS, - MALIBU_DEBUG_PHY_HIBERNATION_CTRL); - phy_data = malibu_phy_reg_read(dev_id, phy_id, MALIBU_DEBUG_PORT_DATA); - - if (phy_data & 0x8000) - *enable = A_TRUE; - - return SW_OK; -} - -/****************************************************************************** -* -* malibu_phy_set combo medium type -* -* set combo medium fiber or copper -*/ -sw_error_t -malibu_phy_set_combo_prefer_medium(a_uint32_t dev_id, a_uint32_t phy_id, - fal_port_medium_t phy_medium) -{ - a_uint16_t phy_data; - if (phy_id != COMBO_PHY_ID) - return SW_NOT_SUPPORTED; - - phy_data = malibu_phy_reg_read(dev_id, phy_id, MALIBU_PHY_CHIP_CONFIG); - - if (phy_medium == PHY_MEDIUM_FIBER) { - phy_data |= MALIBU_PHY4_PREFER_FIBER; - phy_data &= ~0x8000; - } else if (phy_medium == PHY_MEDIUM_COPPER) { - phy_data &= ~MALIBU_PHY4_PREFER_FIBER; - phy_data |= 0x8000; - } else { - return SW_BAD_PARAM; - } - malibu_phy_reg_write(dev_id, phy_id, MALIBU_PHY_CHIP_CONFIG, phy_data); - - return SW_OK; -} - -/****************************************************************************** -* -* malibu_phy_get combo medium type -* -* get combo medium fiber or copper -*/ -sw_error_t -malibu_phy_get_combo_prefer_medium(a_uint32_t dev_id, a_uint32_t phy_id, - fal_port_medium_t * phy_medium) -{ - a_uint16_t phy_data; - if (phy_id != COMBO_PHY_ID) - return SW_NOT_SUPPORTED; - - phy_data = malibu_phy_reg_read(dev_id, phy_id, MALIBU_PHY_CHIP_CONFIG); - - *phy_medium = - (phy_data & MALIBU_PHY4_PREFER_FIBER) ? PHY_MEDIUM_FIBER : - PHY_MEDIUM_COPPER; - - return SW_OK; -} - -/****************************************************************************** -* -* malibu_phy_get current combo medium type copper or fiber -* -* get current combo medium type -*/ -sw_error_t -malibu_phy_get_combo_current_medium_type(a_uint32_t dev_id, a_uint32_t phy_id, - fal_port_medium_t * phy_medium) -{ - - if (phy_id != COMBO_PHY_ID) - return SW_NOT_SUPPORTED; - - *phy_medium = __phy_active_medium_get(dev_id, phy_id); - - return SW_OK; -} - -/****************************************************************************** -* -* malibu_phy_set fiber mode 1000bx or 100fx -* -* set combo fbier mode -*/ -sw_error_t -malibu_phy_set_combo_fiber_mode(a_uint32_t dev_id, a_uint32_t phy_id, - fal_port_fiber_mode_t fiber_mode) -{ - a_uint16_t phy_data; - if (phy_id != COMBO_PHY_ID) - return SW_NOT_SUPPORTED; - - phy_data = malibu_phy_reg_read(dev_id, phy_id, MALIBU_PHY_CHIP_CONFIG); - - if (fiber_mode == PHY_FIBER_1000BX) { - phy_data |= MALIBU_PHY4_FIBER_MODE_1000BX; - } else if (fiber_mode == PHY_FIBER_100FX) { - phy_data &= ~MALIBU_PHY4_FIBER_MODE_1000BX; - } else { - return SW_BAD_PARAM; - } - - malibu_phy_reg_write(dev_id, phy_id, MALIBU_PHY_CHIP_CONFIG, phy_data); - - return SW_OK; -} - -/****************************************************************************** -* -* malibu_phy_get fiber mode 1000bx or 100fx -* -* get combo fbier mode -*/ -sw_error_t -malibu_phy_get_combo_fiber_mode(a_uint32_t dev_id, a_uint32_t phy_id, - fal_port_fiber_mode_t * fiber_mode) -{ - a_uint16_t phy_data; - if (phy_id != COMBO_PHY_ID) - return SW_NOT_SUPPORTED; - - phy_data = malibu_phy_reg_read(dev_id, phy_id, MALIBU_PHY_CHIP_CONFIG); - - *fiber_mode = - (phy_data & MALIBU_PHY4_FIBER_MODE_1000BX) ? PHY_FIBER_1000BX : - PHY_FIBER_100FX; - - return SW_OK; -} - -/****************************************************************************** -* -* malibu_phy_set_mdix - -* -* set phy mdix configuraiton -*/ -sw_error_t -malibu_phy_set_mdix(a_uint32_t dev_id, a_uint32_t phy_id, - fal_port_mdix_mode_t mode) -{ - a_uint16_t phy_data; - - if ((phy_id == COMBO_PHY_ID) - && (MALIBU_PHY_MEDIUM_COPPER != - __phy_active_medium_get(dev_id, phy_id))) - - return SW_NOT_SUPPORTED; - - phy_data = malibu_phy_reg_read(dev_id, phy_id, MALIBU_PHY_SPEC_CONTROL); - - if (mode == PHY_MDIX_AUTO) { - phy_data |= MALIBU_PHY_MDIX_AUTO; - } else if (mode == PHY_MDIX_MDIX) { - phy_data &= ~MALIBU_PHY_MDIX_AUTO; - phy_data |= MALIBU_PHY_MDIX; - } else if (mode == PHY_MDIX_MDI) { - phy_data &= ~MALIBU_PHY_MDIX_AUTO; - } else { - return SW_BAD_PARAM; - } - - malibu_phy_reg_write(dev_id, phy_id, MALIBU_PHY_SPEC_CONTROL, phy_data); - - malibu_phy_reset(dev_id, phy_id); - return SW_OK; -} - -/****************************************************************************** -* -* malibu_phy_get_mdix -* -* get phy mdix configuration -*/ -sw_error_t -malibu_phy_get_mdix(a_uint32_t dev_id, a_uint32_t phy_id, - fal_port_mdix_mode_t * mode) -{ - a_uint16_t phy_data; - - if ((phy_id == COMBO_PHY_ID) - && (MALIBU_PHY_MEDIUM_COPPER != - __phy_active_medium_get(dev_id, phy_id))) - - return SW_NOT_SUPPORTED; - - phy_data = malibu_phy_reg_read(dev_id, phy_id, MALIBU_PHY_SPEC_CONTROL); - - if ((phy_data & MALIBU_PHY_MDIX_AUTO) == MALIBU_PHY_MDIX_AUTO) { - *mode = PHY_MDIX_AUTO; - } else if ((phy_data & MALIBU_PHY_MDIX) == MALIBU_PHY_MDIX) { - *mode = PHY_MDIX_MDIX; - } else { - *mode = PHY_MDIX_MDI; - } - - return SW_OK; - -} - -/****************************************************************************** -* -* malibu_phy_get_mdix status -* -* get phy mdix status -*/ -sw_error_t -malibu_phy_get_mdix_status(a_uint32_t dev_id, a_uint32_t phy_id, - fal_port_mdix_status_t * mode) -{ - a_uint16_t phy_data; - - if (phy_id == COMBO_PHY_ID) { - - if (MALIBU_PHY_MEDIUM_COPPER != - __phy_active_medium_get(dev_id, phy_id)) - return SW_NOT_SUPPORTED; - - __phy_reg_pages_sel(dev_id, phy_id, MALIBU_PHY_COPPER_PAGES); - } - - phy_data = malibu_phy_reg_read(dev_id, phy_id, MALIBU_PHY_SPEC_STATUS); - - *mode = - (phy_data & MALIBU_PHY_MDIX_STATUS) ? PHY_MDIX_STATUS_MDIX : - PHY_MDIX_STATUS_MDI; - - return SW_OK; - -} - -/****************************************************************************** -* -* malibu_phy_set_local_loopback -* -* set phy local loopback -*/ -sw_error_t -malibu_phy_set_local_loopback(a_uint32_t dev_id, a_uint32_t phy_id, - a_bool_t enable) -{ - a_uint16_t phy_data; - fal_port_speed_t old_speed; - - if (enable == A_TRUE) { - if (phy_id == COMBO_PHY_ID) { - - if (MALIBU_PHY_MEDIUM_COPPER != - __phy_active_medium_get(dev_id, phy_id)) { - - __phy_reg_pages_sel(dev_id, phy_id, - MALIBU_PHY_SGBX_PAGES); - - if (__medium_is_fiber_100fx(dev_id, phy_id)) { - - phy_data = MALIBU_100M_LOOPBACK; - - } else { - phy_data = MALIBU_1000M_LOOPBACK; - } - malibu_phy_reg_write(dev_id, phy_id, MALIBU_PHY_CONTROL, phy_data); - return SW_OK; - } - __phy_reg_pages_sel(dev_id, phy_id, - MALIBU_PHY_COPPER_PAGES); - } - - malibu_phy_get_speed(dev_id, phy_id, &old_speed); - if (old_speed == FAL_SPEED_1000) { - phy_data = MALIBU_1000M_LOOPBACK; - } else if (old_speed == FAL_SPEED_100) { - phy_data = MALIBU_100M_LOOPBACK; - } else if (old_speed == FAL_SPEED_10) { - phy_data = MALIBU_10M_LOOPBACK; - } else { - return SW_FAIL; - } - } else { - if (phy_id == COMBO_PHY_ID) { - if (MALIBU_PHY_MEDIUM_COPPER != - __phy_active_medium_get(dev_id, phy_id)) { - - __phy_reg_pages_sel(dev_id, phy_id, - MALIBU_PHY_SGBX_PAGES); - - } else { - __phy_reg_pages_sel(dev_id, phy_id, - MALIBU_PHY_COPPER_PAGES); - } - } - phy_data = MALIBU_COMMON_CTRL; - } - - - malibu_phy_reg_write(dev_id, phy_id, MALIBU_PHY_CONTROL, phy_data); - return SW_OK; - -} - -/****************************************************************************** -* -* malibu_phy_get_local_loopback -* -* get phy local loopback -*/ -sw_error_t -malibu_phy_get_local_loopback(a_uint32_t dev_id, a_uint32_t phy_id, - a_bool_t * enable) -{ - a_uint16_t phy_data; - - if (phy_id == COMBO_PHY_ID) { - - __phy_reg_pages_sel_by_active_medium(dev_id, phy_id); - - } - - phy_data = malibu_phy_reg_read(dev_id, phy_id, MALIBU_PHY_CONTROL); - - if (phy_data & MALIBU_LOCAL_LOOPBACK_ENABLE) { - *enable = A_TRUE; - } else { - *enable = A_FALSE; - } - - return SW_OK; - -} - -/****************************************************************************** -* -* malibu_phy_set_remote_loopback -* -* set phy remote loopback -*/ -sw_error_t -malibu_phy_set_remote_loopback(a_uint32_t dev_id, a_uint32_t phy_id, - a_bool_t enable) -{ - a_uint16_t phy_data; - - phy_data = malibu_phy_mmd_read(dev_id, phy_id, MALIBU_PHY_MMD3_NUM, - MALIBU_PHY_MMD3_ADDR_REMOTE_LOOPBACK_CTRL); - - if (enable == A_TRUE) { - phy_data |= 0x0001; - } else { - phy_data &= ~0x0001; - } - - malibu_phy_mmd_write(dev_id, phy_id, MALIBU_PHY_MMD3_NUM, - MALIBU_PHY_MMD3_ADDR_REMOTE_LOOPBACK_CTRL, - phy_data); - return SW_OK; - -} - -/****************************************************************************** -* -* malibu_phy_get_remote_loopback -* -* get phy remote loopback -*/ -sw_error_t -malibu_phy_get_remote_loopback(a_uint32_t dev_id, a_uint32_t phy_id, - a_bool_t * enable) -{ - a_uint16_t phy_data; - - phy_data = malibu_phy_mmd_read(dev_id, phy_id, MALIBU_PHY_MMD3_NUM, - MALIBU_PHY_MMD3_ADDR_REMOTE_LOOPBACK_CTRL); - - if (phy_data & 0x0001) { - *enable = A_TRUE; - } else { - *enable = A_FALSE; - } - - return SW_OK; - -} - -/****************************************************************************** -* -* malibu_phy_cdt - cable diagnostic test -* -* cable diagnostic test -*/ - -static inline fal_cable_status_t _phy_cdt_status_mapping(a_uint16_t status) -{ - fal_cable_status_t status_mapping = FAL_CABLE_STATUS_INVALID; - - if (0 == status) - status_mapping = FAL_CABLE_STATUS_INVALID; - else if (1 == status) - status_mapping = FAL_CABLE_STATUS_NORMAL; - else if (2 == status) - status_mapping = FAL_CABLE_STATUS_OPENED; - else if (3 == status) - status_mapping = FAL_CABLE_STATUS_SHORT; - - return status_mapping; -} - -static sw_error_t malibu_phy_cdt_start(a_uint32_t dev_id, a_uint32_t phy_id) -{ - a_uint16_t status = 0; - a_uint16_t ii = 100; - - if (phy_id == COMBO_PHY_ID) { - - if (MALIBU_PHY_MEDIUM_COPPER != - __phy_active_medium_get(dev_id, phy_id)) - return SW_NOT_SUPPORTED; - - __phy_reg_pages_sel(dev_id, phy_id, MALIBU_PHY_COPPER_PAGES); - } - - /* RUN CDT */ - malibu_phy_reg_write(dev_id, phy_id, MALIBU_PHY_CDT_CONTROL, - RUN_CDT | CABLE_LENGTH_UNIT); - do { - aos_mdelay(30); - status = - malibu_phy_reg_read(dev_id, phy_id, MALIBU_PHY_CDT_CONTROL); - } - while ((status & RUN_CDT) && (--ii)); - - return SW_OK; -} - -sw_error_t -malibu_phy_cdt_get(a_uint32_t dev_id, a_uint32_t phy_id, - fal_port_cdt_t * port_cdt) -{ - a_uint16_t status = 0; - a_uint16_t cable_delta_time = 0; - int i; - - if ((!port_cdt) || (phy_id > 4)) { - return SW_FAIL; - } - - - malibu_phy_cdt_start(dev_id, phy_id); - - /* Get cable status */ - status = malibu_phy_mmd_read(dev_id, phy_id, 3, 0x8064); - - - - for (i = 0; i < 4; i++) { - switch (i) { - case 0: - port_cdt->pair_a_status = (status >> 12) & 0x3; - /* Get Cable Length value */ - cable_delta_time = - malibu_phy_mmd_read(dev_id, phy_id, 3, 0x8065); - /* the actual cable length equals to CableDeltaTime * 0.824 */ - port_cdt->pair_a_len = - ((cable_delta_time & 0xff) * 800) / 1000; - - break; - case 1: - port_cdt->pair_b_status = (status >> 8) & 0x3; - /* Get Cable Length value */ - cable_delta_time = - malibu_phy_mmd_read(dev_id, phy_id, 3, 0x8066); - /* the actual cable length equals to CableDeltaTime * 0.824 */ - port_cdt->pair_b_len = - ((cable_delta_time & 0xff) * 800) / 1000; - break; - case 2: - port_cdt->pair_c_status = (status >> 4) & 0x3; - /* Get Cable Length value */ - cable_delta_time = - malibu_phy_mmd_read(dev_id, phy_id, 3, 0x8067); - /* the actual cable length equals to CableDeltaTime * 0.824 */ - port_cdt->pair_c_len = - ((cable_delta_time & 0xff) * 800) / 1000; - break; - case 3: - port_cdt->pair_d_status = status & 0x3; - /* Get Cable Length value */ - cable_delta_time = - malibu_phy_mmd_read(dev_id, phy_id, 3, 0x8068); - /* the actual cable length equals to CableDeltaTime * 0.824 */ - port_cdt->pair_d_len = - ((cable_delta_time & 0xff) * 800) / 1000; - break; - default: - break; - } - } - - - return SW_OK; -} - -sw_error_t -malibu_phy_cdt(a_uint32_t dev_id, a_uint32_t phy_id, a_uint32_t mdi_pair, - fal_cable_status_t * cable_status, a_uint32_t * cable_len) -{ - fal_port_cdt_t malibu_port_cdt; - - if (phy_id == COMBO_PHY_ID) { - - if (MALIBU_PHY_MEDIUM_COPPER != - __phy_active_medium_get(dev_id, phy_id)) - return SW_NOT_SUPPORTED; - - __phy_reg_pages_sel(dev_id, phy_id, MALIBU_PHY_COPPER_PAGES); - } - - if ((mdi_pair >= 4) || (phy_id > 4)) { - //There are only 4 mdi pairs in 1000BASE-T - return SW_BAD_PARAM; - } - - malibu_phy_cdt_get(dev_id, phy_id, &malibu_port_cdt); - - switch (mdi_pair) { - case 0: - *cable_status = - _phy_cdt_status_mapping(malibu_port_cdt.pair_a_status); - /* Get Cable Length value */ - *cable_len = malibu_port_cdt.pair_a_len; - break; - case 1: - *cable_status = - _phy_cdt_status_mapping(malibu_port_cdt.pair_b_status); - /* Get Cable Length value */ - *cable_len = malibu_port_cdt.pair_b_len; - break; - case 2: - *cable_status = - _phy_cdt_status_mapping(malibu_port_cdt.pair_c_status); - /* Get Cable Length value */ - *cable_len = malibu_port_cdt.pair_c_len; - break; - case 3: - *cable_status = - _phy_cdt_status_mapping(malibu_port_cdt.pair_d_status); - /* Get Cable Length value */ - *cable_len = malibu_port_cdt.pair_d_len; - break; - default: - break; - } - - return SW_OK; -} - -/****************************************************************************** -* -* malibu_phy_reset_done - reset the phy -* -* reset the phy -*/ -a_bool_t malibu_phy_reset_done(a_uint32_t dev_id, a_uint32_t phy_id) -{ - a_uint16_t phy_data; - a_uint16_t ii = 200; - - if (phy_id == COMBO_PHY_ID) - __phy_reg_pages_sel_by_active_medium(dev_id, phy_id); - - do { - phy_data = - malibu_phy_reg_read(dev_id, phy_id, MALIBU_PHY_CONTROL); - aos_mdelay(10); - } - while ((!MALIBU_RESET_DONE(phy_data)) && --ii); - - if (ii == 0) - return A_FALSE; - - return A_TRUE; -} - -/****************************************************************************** -* -* malibu_autoneg_done -* -* malibu_autoneg_done -*/ -a_bool_t malibu_autoneg_done(a_uint32_t dev_id, a_uint32_t phy_id) -{ - a_uint16_t phy_data; - a_uint16_t ii = 200; - - if (phy_id == COMBO_PHY_ID) - __phy_reg_pages_sel_by_active_medium(dev_id, phy_id); - - do { - phy_data = - malibu_phy_reg_read(dev_id, phy_id, MALIBU_PHY_STATUS); - aos_mdelay(10); - } - while ((!MALIBU_AUTONEG_DONE(phy_data)) && --ii); - - if (ii == 0) - return A_FALSE; - - return A_TRUE; -} - -/****************************************************************************** -* -* malibu_phy_Speed_Duplex_Resolved - - reset the phy -* -* reset the phy -*/ -a_bool_t malibu_phy_speed_duplex_resolved(a_uint32_t dev_id, a_uint32_t phy_id) -{ - a_uint16_t phy_data; - a_uint16_t ii = 200; - - if (phy_id == COMBO_PHY_ID) - __phy_reg_pages_sel_by_active_medium(dev_id, phy_id); - - do { - phy_data = - malibu_phy_reg_read(dev_id, phy_id, MALIBU_PHY_SPEC_STATUS); - aos_mdelay(10); - } - while ((!MALIBU_SPEED_DUPLEX_RESOVLED(phy_data)) && --ii); - - if (ii == 0) - return A_FALSE; - - return A_TRUE; -} -#endif -/****************************************************************************** -* -* malibu_phy_off - power off the phy -* -* Power off the phy -*/ -sw_error_t malibu_phy_poweroff(a_uint32_t dev_id, a_uint32_t phy_id) -{ - a_uint16_t phy_data; - if (phy_id == COMBO_PHY_ID) { - __phy_reg_pages_sel(dev_id, phy_id, MALIBU_PHY_SGBX_PAGES); - phy_data = - malibu_phy_reg_read(dev_id, phy_id, MALIBU_PHY_CONTROL); - malibu_phy_reg_write(dev_id, phy_id, MALIBU_PHY_CONTROL, - phy_data | MALIBU_CTRL_POWER_DOWN); - - __phy_reg_pages_sel(dev_id, phy_id, MALIBU_PHY_COPPER_PAGES); - phy_data = - malibu_phy_reg_read(dev_id, phy_id, MALIBU_PHY_CONTROL); - malibu_phy_reg_write(dev_id, phy_id, MALIBU_PHY_CONTROL, - phy_data | MALIBU_CTRL_POWER_DOWN); - } else { - phy_data = - malibu_phy_reg_read(dev_id, phy_id, MALIBU_PHY_CONTROL); - malibu_phy_reg_write(dev_id, phy_id, MALIBU_PHY_CONTROL, - phy_data | MALIBU_CTRL_POWER_DOWN); - } - return SW_OK; -} - -/****************************************************************************** -* -* malibu_phy_on - power on the phy -* -* Power on the phy -*/ -sw_error_t malibu_phy_poweron(a_uint32_t dev_id, a_uint32_t phy_id) -{ - a_uint16_t phy_data; - if (phy_id == COMBO_PHY_ID) { - __phy_reg_pages_sel(dev_id, phy_id, MALIBU_PHY_SGBX_PAGES); - phy_data = - malibu_phy_reg_read(dev_id, phy_id, MALIBU_PHY_CONTROL); - malibu_phy_reg_write(dev_id, phy_id, MALIBU_PHY_CONTROL, - phy_data & ~MALIBU_CTRL_POWER_DOWN); - - __phy_reg_pages_sel(dev_id, phy_id, MALIBU_PHY_COPPER_PAGES); - phy_data = - malibu_phy_reg_read(dev_id, phy_id, MALIBU_PHY_CONTROL); - malibu_phy_reg_write(dev_id, phy_id, MALIBU_PHY_CONTROL, - phy_data & ~MALIBU_CTRL_POWER_DOWN); - - } else { - phy_data = - malibu_phy_reg_read(dev_id, phy_id, MALIBU_PHY_CONTROL); - malibu_phy_reg_write(dev_id, phy_id, MALIBU_PHY_CONTROL, - phy_data & ~MALIBU_CTRL_POWER_DOWN); - } - - aos_mdelay(200); - - return SW_OK; -} -#ifndef IN_PORTCONTROL_MINI -/****************************************************************************** -* -* malibu_phy_get_ability - get the phy ability -* -* -*/ -sw_error_t -malibu_phy_get_ability(a_uint32_t dev_id, a_uint32_t phy_id, - a_uint32_t * ability) -{ - a_uint16_t phy_data; - - *ability = 0; - if (phy_id == COMBO_PHY_ID) - __phy_reg_pages_sel_by_active_medium(dev_id, phy_id); - - phy_data = malibu_phy_reg_read(dev_id, phy_id, MALIBU_PHY_STATUS); - - if (phy_data & MALIBU_STATUS_AUTONEG_CAPS) - *ability |= FAL_PHY_AUTONEG_CAPS; - - if (phy_data & MALIBU_STATUS_100T2_HD_CAPS) - *ability |= FAL_PHY_100T2_HD_CAPS; - - if (phy_data & MALIBU_STATUS_100T2_FD_CAPS) - *ability |= FAL_PHY_100T2_FD_CAPS; - - if (phy_data & MALIBU_STATUS_10T_HD_CAPS) - *ability |= FAL_PHY_10T_HD_CAPS; - - if (phy_data & MALIBU_STATUS_10T_FD_CAPS) - *ability |= FAL_PHY_10T_FD_CAPS; - - if (phy_data & MALIBU_STATUS_100X_HD_CAPS) - *ability |= FAL_PHY_100X_HD_CAPS; - - if (phy_data & MALIBU_STATUS_100X_FD_CAPS) - *ability |= FAL_PHY_100X_FD_CAPS; - - if (phy_data & MALIBU_STATUS_100T4_CAPS) - *ability |= FAL_PHY_100T4_CAPS; - - if (phy_data & MALIBU_STATUS_EXTENDED_STATUS) { - phy_data = - malibu_phy_reg_read(dev_id, phy_id, MALIBU_EXTENDED_STATUS); - - if (phy_data & MALIBU_STATUS_1000T_FD_CAPS) { - *ability |= FAL_PHY_1000T_FD_CAPS; - } - - if (phy_data & MALIBU_STATUS_1000X_FD_CAPS) { - *ability |= FAL_PHY_1000X_FD_CAPS; - } - } - - return SW_OK; -} - -/****************************************************************************** -* -* malibu_phy_get_ability - get the phy ability -* -* -*/ -sw_error_t -malibu_phy_get_partner_ability(a_uint32_t dev_id, a_uint32_t phy_id, - a_uint32_t * ability) -{ - a_uint16_t phy_data; - - *ability = 0; - - if (phy_id == COMBO_PHY_ID) - __phy_reg_pages_sel_by_active_medium(dev_id, phy_id); - - phy_data = - malibu_phy_reg_read(dev_id, phy_id, MALIBU_LINK_PARTNER_ABILITY); - - if (phy_data & MALIBU_LINK_10BASETX_HALF_DUPLEX) - *ability |= FAL_PHY_PART_10T_HD; - - if (phy_data & MALIBU_LINK_10BASETX_FULL_DUPLEX) - *ability |= FAL_PHY_PART_10T_FD; - - if (phy_data & MALIBU_LINK_100BASETX_HALF_DUPLEX) - *ability |= FAL_PHY_PART_100TX_HD; - - if (phy_data & MALIBU_LINK_100BASETX_FULL_DUPLEX) - *ability |= FAL_PHY_PART_100TX_FD; - - if (phy_data & MALIBU_LINK_NPAGE) { - phy_data = - malibu_phy_reg_read(dev_id, phy_id, - MALIBU_1000BASET_STATUS); - - if (phy_data & MALIBU_LINK_1000BASETX_FULL_DUPLEX) - *ability |= FAL_PHY_PART_1000T_FD; - } - - return SW_OK; -} -#endif -/****************************************************************************** -* -* malibu_phy_status - test to see if the specified phy link is alive -* -* RETURNS: -* A_TRUE --> link is alive -* A_FALSE --> link is down -*/ -a_bool_t malibu_phy_get_link_status(a_uint32_t dev_id, a_uint32_t phy_id) -{ - a_uint16_t phy_data; - if (phy_id == COMBO_PHY_ID) - __phy_reg_pages_sel_by_active_medium(dev_id, phy_id); - phy_data = malibu_phy_reg_read(dev_id, phy_id, MALIBU_PHY_SPEC_STATUS); - - if (phy_data & MALIBU_STATUS_LINK_PASS) - return A_TRUE; - - return A_FALSE; -} - -/****************************************************************************** -* -* malibu_set_autoneg_adv - set the phy autoneg Advertisement -* -*/ -sw_error_t -malibu_phy_set_autoneg_adv(a_uint32_t dev_id, a_uint32_t phy_id, - a_uint32_t autoneg) -{ - a_uint16_t phy_data = 0; - if (phy_id == COMBO_PHY_ID) { - if (__medium_is_fiber_100fx(dev_id, phy_id)) - return SW_NOT_SUPPORTED; - - if (MALIBU_PHY_MEDIUM_COPPER == - __phy_active_medium_get(dev_id, phy_id)) { - - __phy_reg_pages_sel(dev_id, phy_id, - MALIBU_PHY_COPPER_PAGES); - phy_data = - malibu_phy_reg_read(dev_id, phy_id, - MALIBU_AUTONEG_ADVERT); - phy_data &= ~MALIBU_ADVERTISE_MEGA_ALL; - phy_data &= - ~(MALIBU_ADVERTISE_PAUSE | - MALIBU_ADVERTISE_ASYM_PAUSE); - - if (autoneg & FAL_PHY_ADV_100TX_FD) { - phy_data |= MALIBU_ADVERTISE_100FULL; - } - if (autoneg & FAL_PHY_ADV_100TX_HD) { - phy_data |= MALIBU_ADVERTISE_100HALF; - } - if (autoneg & FAL_PHY_ADV_10T_FD) { - phy_data |= MALIBU_ADVERTISE_10FULL; - } - if (autoneg & FAL_PHY_ADV_10T_HD) { - phy_data |= MALIBU_ADVERTISE_10HALF; - } - if (autoneg & FAL_PHY_ADV_PAUSE) { - phy_data |= MALIBU_ADVERTISE_PAUSE; - } - if (autoneg & FAL_PHY_ADV_ASY_PAUSE) { - phy_data |= MALIBU_ADVERTISE_ASYM_PAUSE; - } - __phy_reg_pages_sel(dev_id, phy_id, - MALIBU_PHY_COPPER_PAGES); - if (autoneg & FAL_PHY_ADV_1000T_FD) { - phy_data |= MALIBU_EXTENDED_NEXT_PAGE_EN; - } else { - phy_data &= ~MALIBU_EXTENDED_NEXT_PAGE_EN; - } - malibu_phy_reg_write(dev_id, phy_id, - MALIBU_AUTONEG_ADVERT, phy_data); - - phy_data = - malibu_phy_reg_read(dev_id, phy_id, - MALIBU_1000BASET_CONTROL); - phy_data &= ~MALIBU_ADVERTISE_1000FULL; - phy_data &= ~MALIBU_ADVERTISE_1000HALF; - - if (autoneg & FAL_PHY_ADV_1000T_FD) { - phy_data |= MALIBU_ADVERTISE_1000FULL; - } - malibu_phy_reg_write(dev_id, phy_id, - MALIBU_1000BASET_CONTROL, - phy_data); - } else { - - __phy_reg_pages_sel(dev_id, phy_id, - MALIBU_PHY_SGBX_PAGES); - phy_data = - malibu_phy_reg_read(dev_id, phy_id, - MALIBU_AUTONEG_ADVERT); - phy_data &= ~MALIBU_BX_ADVERTISE_ALL; - - if (autoneg & FAL_PHY_ADV_1000BX_FD) { - phy_data |= MALIBU_BX_ADVERTISE_1000FULL; - } - if (autoneg & FAL_PHY_ADV_1000BX_HD) { - phy_data |= MALIBU_BX_ADVERTISE_1000HALF; - } - if (autoneg & FAL_PHY_ADV_PAUSE) { - phy_data |= MALIBU_BX_ADVERTISE_PAUSE; - } - if (autoneg & FAL_PHY_ADV_ASY_PAUSE) { - phy_data |= MALIBU_BX_ADVERTISE_ASYM_PAUSE; - } - __phy_reg_pages_sel(dev_id, phy_id, - MALIBU_PHY_SGBX_PAGES); - - malibu_phy_reg_write(dev_id, phy_id, - MALIBU_AUTONEG_ADVERT, phy_data); - } - } else { - - phy_data = - malibu_phy_reg_read(dev_id, phy_id, MALIBU_AUTONEG_ADVERT); - phy_data &= ~MALIBU_ADVERTISE_MEGA_ALL; - phy_data &= - ~(MALIBU_ADVERTISE_PAUSE | MALIBU_ADVERTISE_ASYM_PAUSE); - - if (autoneg & FAL_PHY_ADV_100TX_FD) { - phy_data |= MALIBU_ADVERTISE_100FULL; - } - if (autoneg & FAL_PHY_ADV_100TX_HD) { - phy_data |= MALIBU_ADVERTISE_100HALF; - } - if (autoneg & FAL_PHY_ADV_10T_FD) { - phy_data |= MALIBU_ADVERTISE_10FULL; - } - if (autoneg & FAL_PHY_ADV_10T_HD) { - phy_data |= MALIBU_ADVERTISE_10HALF; - } - if (autoneg & FAL_PHY_ADV_PAUSE) { - phy_data |= MALIBU_ADVERTISE_PAUSE; - } - if (autoneg & FAL_PHY_ADV_ASY_PAUSE) { - phy_data |= MALIBU_ADVERTISE_ASYM_PAUSE; - } - malibu_phy_reg_write(dev_id, phy_id, MALIBU_AUTONEG_ADVERT, - phy_data); - - phy_data = - malibu_phy_reg_read(dev_id, phy_id, - MALIBU_1000BASET_CONTROL); - phy_data &= ~MALIBU_ADVERTISE_1000FULL; - phy_data &= ~MALIBU_ADVERTISE_1000HALF; - - if (autoneg & FAL_PHY_ADV_1000T_FD) { - phy_data |= MALIBU_ADVERTISE_1000FULL; - } - malibu_phy_reg_write(dev_id, phy_id, MALIBU_1000BASET_CONTROL, - phy_data); - - } - - return SW_OK; -} - -/****************************************************************************** -* -* malibu_get_autoneg_adv - get the phy autoneg Advertisement -* -*/ -sw_error_t -malibu_phy_get_autoneg_adv(a_uint32_t dev_id, a_uint32_t phy_id, - a_uint32_t * autoneg) -{ - a_uint16_t phy_data = 0; - - *autoneg = 0; - - if (phy_id == COMBO_PHY_ID) { - if (__medium_is_fiber_100fx(dev_id, phy_id)) - return SW_NOT_SUPPORTED; - - if (MALIBU_PHY_MEDIUM_COPPER == - __phy_active_medium_get(dev_id, phy_id)) { - - __phy_reg_pages_sel(dev_id, phy_id, - MALIBU_PHY_COPPER_PAGES); - - phy_data = - malibu_phy_reg_read(dev_id, phy_id, - MALIBU_AUTONEG_ADVERT); - - if (phy_data & MALIBU_ADVERTISE_100FULL) - *autoneg |= FAL_PHY_ADV_100TX_FD; - - if (phy_data & MALIBU_ADVERTISE_100HALF) - *autoneg |= FAL_PHY_ADV_100TX_HD; - - if (phy_data & MALIBU_ADVERTISE_10FULL) - *autoneg |= FAL_PHY_ADV_10T_FD; - - if (phy_data & MALIBU_ADVERTISE_10HALF) - *autoneg |= FAL_PHY_ADV_10T_HD; - - if (phy_data & MALIBU_ADVERTISE_PAUSE) - *autoneg |= FAL_PHY_ADV_PAUSE; - - if (phy_data & MALIBU_ADVERTISE_ASYM_PAUSE) - *autoneg |= FAL_PHY_ADV_ASY_PAUSE; - - phy_data = - malibu_phy_reg_read(dev_id, phy_id, - MALIBU_1000BASET_CONTROL); - - if (phy_data & MALIBU_ADVERTISE_1000FULL) - *autoneg |= FAL_PHY_ADV_1000T_FD; - - } else { - - __phy_reg_pages_sel(dev_id, phy_id, - MALIBU_PHY_SGBX_PAGES); - phy_data = - malibu_phy_reg_read(dev_id, phy_id, - MALIBU_AUTONEG_ADVERT); - - if (phy_data & MALIBU_BX_ADVERTISE_PAUSE) - *autoneg |= FAL_PHY_ADV_PAUSE; - - if (phy_data & MALIBU_BX_ADVERTISE_ASYM_PAUSE) - *autoneg |= FAL_PHY_ADV_ASY_PAUSE; - - if (phy_data & MALIBU_BX_ADVERTISE_1000HALF) - *autoneg |= FAL_PHY_ADV_1000BX_HD; - - if (phy_data & MALIBU_BX_ADVERTISE_1000FULL) - *autoneg |= FAL_PHY_ADV_1000BX_FD; - } - } else { - - phy_data = - malibu_phy_reg_read(dev_id, phy_id, MALIBU_AUTONEG_ADVERT); - - if (phy_data & MALIBU_ADVERTISE_100FULL) - *autoneg |= FAL_PHY_ADV_100TX_FD; - - if (phy_data & MALIBU_ADVERTISE_100HALF) - *autoneg |= FAL_PHY_ADV_100TX_HD; - - if (phy_data & MALIBU_ADVERTISE_10FULL) - *autoneg |= FAL_PHY_ADV_10T_FD; - - if (phy_data & MALIBU_ADVERTISE_10HALF) - *autoneg |= FAL_PHY_ADV_10T_HD; - - if (phy_data & MALIBU_ADVERTISE_PAUSE) - *autoneg |= FAL_PHY_ADV_PAUSE; - - if (phy_data & MALIBU_ADVERTISE_ASYM_PAUSE) - *autoneg |= FAL_PHY_ADV_ASY_PAUSE; - - phy_data = - malibu_phy_reg_read(dev_id, phy_id, - MALIBU_1000BASET_CONTROL); - if (phy_data & MALIBU_ADVERTISE_1000FULL) - *autoneg |= FAL_PHY_ADV_1000T_FD; - } - - return SW_OK; -} - -/****************************************************************************** -* -* malibu_phy_enable_autonego -* -* Power off the phy -*/ -a_bool_t malibu_phy_autoneg_status(a_uint32_t dev_id, a_uint32_t phy_id) -{ - a_uint16_t phy_data; - - if (phy_id == COMBO_PHY_ID) { - - if (__medium_is_fiber_100fx(dev_id, phy_id)) - return A_FALSE; - __phy_reg_pages_sel_by_active_medium(dev_id, phy_id); - } - - phy_data = malibu_phy_reg_read(dev_id, phy_id, MALIBU_PHY_CONTROL); - - if (phy_data & MALIBU_CTRL_AUTONEGOTIATION_ENABLE) - return A_TRUE; - - return A_FALSE; -} - -/****************************************************************************** -* -* malibu_restart_autoneg - restart the phy autoneg -* -*/ -sw_error_t malibu_phy_restart_autoneg(a_uint32_t dev_id, a_uint32_t phy_id) -{ - a_uint16_t phy_data = 0; - - if (phy_id == COMBO_PHY_ID) { - if (__medium_is_fiber_100fx(dev_id, phy_id)) - return SW_NOT_SUPPORTED; - __phy_reg_pages_sel_by_active_medium(dev_id, phy_id); - } - phy_data = malibu_phy_reg_read(dev_id, phy_id, MALIBU_PHY_CONTROL); - - phy_data |= MALIBU_CTRL_AUTONEGOTIATION_ENABLE; - malibu_phy_reg_write(dev_id, phy_id, MALIBU_PHY_CONTROL, - phy_data | MALIBU_CTRL_RESTART_AUTONEGOTIATION); - - return SW_OK; -} - -/****************************************************************************** -* -* malibu_phy_enable_autonego -* -*/ -sw_error_t malibu_phy_enable_autoneg(a_uint32_t dev_id, a_uint32_t phy_id) -{ - a_uint16_t phy_data = 0; - - if (phy_id == COMBO_PHY_ID) { - if (__medium_is_fiber_100fx(dev_id, phy_id)) - return SW_NOT_SUPPORTED; - __phy_reg_pages_sel_by_active_medium(dev_id, phy_id); - } - phy_data = malibu_phy_reg_read(dev_id, phy_id, MALIBU_PHY_CONTROL); - - malibu_phy_reg_write(dev_id, phy_id, MALIBU_PHY_CONTROL, - phy_data | MALIBU_CTRL_AUTONEGOTIATION_ENABLE); - - return SW_OK; -} - -/****************************************************************************** -* -* malibu_phy_set_speed - Determines the speed of phy ports associated with the -* specified device. -*/ -sw_error_t -malibu_phy_set_speed(a_uint32_t dev_id, a_uint32_t phy_id, - fal_port_speed_t speed) -{ - a_uint16_t phy_data = 0; - fal_port_duplex_t old_duplex; - - if (phy_id == COMBO_PHY_ID) { - if (MALIBU_PHY_MEDIUM_COPPER != - __phy_active_medium_get(dev_id, phy_id)) - - return SW_NOT_SUPPORTED; - - __phy_reg_pages_sel(dev_id, phy_id, MALIBU_PHY_COPPER_PAGES); - } - - phy_data = malibu_phy_reg_read(dev_id, phy_id, MALIBU_PHY_CONTROL); - - malibu_phy_get_duplex(dev_id, phy_id, &old_duplex); - - if (old_duplex == FAL_FULL_DUPLEX) { - phy_data |= MALIBU_CTRL_FULL_DUPLEX; - - if (FAL_SPEED_1000 == speed) { - phy_data |= MALIBU_CTRL_SPEED_1000; - phy_data &= ~MALIBU_CTRL_SPEED_100; - phy_data |= MALIBU_CTRL_AUTONEGOTIATION_ENABLE; - } else if (FAL_SPEED_100 == speed) { - phy_data |= MALIBU_CTRL_SPEED_100; - phy_data &= ~MALIBU_CTRL_SPEED_1000; - phy_data &= ~MALIBU_CTRL_AUTONEGOTIATION_ENABLE; - } else if (FAL_SPEED_10 == speed){ - phy_data &= ~MALIBU_CTRL_SPEED_100; - phy_data &= ~MALIBU_CTRL_SPEED_1000; - phy_data &= ~MALIBU_CTRL_AUTONEGOTIATION_ENABLE; - } else { - return SW_BAD_PARAM; - } - } else if (old_duplex == FAL_HALF_DUPLEX) { - phy_data &= ~MALIBU_CTRL_FULL_DUPLEX; - - if (FAL_SPEED_100 == speed) { - phy_data |= MALIBU_CTRL_SPEED_100; - phy_data &= ~MALIBU_CTRL_SPEED_1000; - phy_data &= ~MALIBU_CTRL_AUTONEGOTIATION_ENABLE; - } else if (FAL_SPEED_10 == speed) { - phy_data &= ~MALIBU_CTRL_SPEED_100; - phy_data &= ~MALIBU_CTRL_SPEED_1000; - phy_data &= ~MALIBU_CTRL_AUTONEGOTIATION_ENABLE; - } else if (FAL_SPEED_1000 == speed){ - phy_data |= MALIBU_CTRL_FULL_DUPLEX; - phy_data |= MALIBU_CTRL_SPEED_1000; - phy_data &= ~MALIBU_CTRL_SPEED_100; - phy_data |= MALIBU_CTRL_AUTONEGOTIATION_ENABLE; - } else { - return SW_BAD_PARAM; - } - } else { - return SW_FAIL; - } - - malibu_phy_reg_write(dev_id, phy_id, MALIBU_PHY_CONTROL, phy_data); - return SW_OK; - -} - -/****************************************************************************** -* -* malibu_phy_set_duplex - Determines the speed of phy ports associated with the -* specified device. -*/ -sw_error_t -malibu_phy_set_duplex(a_uint32_t dev_id, a_uint32_t phy_id, - fal_port_duplex_t duplex) -{ - a_uint16_t phy_data = 0; - fal_port_speed_t old_speed; - - if (phy_id == COMBO_PHY_ID) { - - if (MALIBU_PHY_MEDIUM_COPPER != - __phy_active_medium_get(dev_id, phy_id)) { - - __phy_reg_pages_sel(dev_id, phy_id, - MALIBU_PHY_SGBX_PAGES); - - phy_data = - malibu_phy_reg_read(dev_id, phy_id, - MALIBU_PHY_CONTROL); - - if (__medium_is_fiber_100fx(dev_id, phy_id)) { - - if (duplex == FAL_FULL_DUPLEX) { - phy_data |= MALIBU_CTRL_FULL_DUPLEX; - } else if (duplex == FAL_HALF_DUPLEX) { - phy_data &= ~MALIBU_CTRL_FULL_DUPLEX; - } else { - return SW_BAD_PARAM; - } - } else { - - if (duplex == FAL_FULL_DUPLEX) { - phy_data |= MALIBU_CTRL_FULL_DUPLEX; - phy_data &= ~MALIBU_CTRL_AUTONEGOTIATION_ENABLE; - } else if (duplex == FAL_HALF_DUPLEX) { - phy_data &= ~MALIBU_CTRL_FULL_DUPLEX; - phy_data &= ~MALIBU_CTRL_AUTONEGOTIATION_ENABLE; - } else { - return SW_BAD_PARAM; - } - } - malibu_phy_reg_write(dev_id, phy_id, - MALIBU_PHY_CONTROL, - phy_data); - - return SW_OK; - } - __phy_reg_pages_sel(dev_id, phy_id, - MALIBU_PHY_COPPER_PAGES); - } - - phy_data = malibu_phy_reg_read(dev_id, phy_id, MALIBU_PHY_CONTROL); - - malibu_phy_get_speed(dev_id, phy_id, &old_speed); - - if (old_speed == FAL_SPEED_1000) { - - phy_data |= MALIBU_CTRL_SPEED_1000; - phy_data &= ~MALIBU_CTRL_SPEED_100; - phy_data |= MALIBU_CTRL_AUTONEGOTIATION_ENABLE; - - if (duplex == FAL_FULL_DUPLEX) { - phy_data |= MALIBU_CTRL_FULL_DUPLEX; - - } else if (duplex == FAL_HALF_DUPLEX) { - - return SW_NOT_SUPPORTED; - } else { - return SW_BAD_PARAM; - } - } else if (old_speed == FAL_SPEED_100) { - phy_data |= MALIBU_CTRL_SPEED_100; - phy_data &= ~MALIBU_CTRL_SPEED_1000; - phy_data &= ~MALIBU_CTRL_AUTONEGOTIATION_ENABLE; - - if (duplex == FAL_FULL_DUPLEX) { - phy_data |= MALIBU_CTRL_FULL_DUPLEX; - - } else if (duplex == FAL_HALF_DUPLEX) { - - phy_data &= ~MALIBU_CTRL_FULL_DUPLEX; - - } else { - return SW_BAD_PARAM; - } - } else if (old_speed == FAL_SPEED_10) { - phy_data &= ~MALIBU_CTRL_SPEED_100; - phy_data &= ~MALIBU_CTRL_SPEED_1000; - phy_data &= ~MALIBU_CTRL_AUTONEGOTIATION_ENABLE; - - if (duplex == FAL_FULL_DUPLEX) { - phy_data |= MALIBU_CTRL_FULL_DUPLEX; - - } else if (duplex == FAL_HALF_DUPLEX) { - - phy_data &= ~MALIBU_CTRL_FULL_DUPLEX; - - } else { - return SW_BAD_PARAM; - } - } else { - return SW_FAIL; - } - malibu_phy_reg_write(dev_id, phy_id, MALIBU_PHY_CONTROL, phy_data); - - return SW_OK; -} - -/****************************************************************************** -* -* malibu_phy_get_phy_id - get the phy id -* -*/ -sw_error_t -malibu_phy_get_phy_id(a_uint32_t dev_id, a_uint32_t phy_id, - a_uint32_t *phy_data) -{ - a_uint16_t org_id, rev_id; - - org_id = malibu_phy_reg_read(dev_id, phy_id, MALIBU_PHY_ID1); - rev_id = malibu_phy_reg_read(dev_id, phy_id, MALIBU_PHY_ID2); - - *phy_data = ((org_id & 0xffff) << 16) | (rev_id & 0xffff); - - return SW_OK; -} -#ifndef IN_PORTCONTROL_MINI -/****************************************************************************** -* -* malibu_phy_set wol frame mac address -* -* set phy wol frame mac address -*/ -sw_error_t -malibu_phy_set_magic_frame_mac(a_uint32_t dev_id, a_uint32_t phy_id, - fal_mac_addr_t * mac) -{ - a_uint16_t phy_data1; - a_uint16_t phy_data2; - a_uint16_t phy_data3; - - phy_data1 = (mac->uc[0] << 8) | mac->uc[1]; - phy_data2 = (mac->uc[2] << 8) | mac->uc[3]; - phy_data3 = (mac->uc[4] << 8) | mac->uc[5]; - - malibu_phy_mmd_write(dev_id, phy_id, MALIBU_PHY_MMD3_NUM, - MALIBU_PHY_MMD3_WOL_MAGIC_MAC_CTRL1, phy_data1); - - malibu_phy_mmd_write(dev_id, phy_id, MALIBU_PHY_MMD3_NUM, - MALIBU_PHY_MMD3_WOL_MAGIC_MAC_CTRL2, phy_data2); - - malibu_phy_mmd_write(dev_id, phy_id, MALIBU_PHY_MMD3_NUM, - MALIBU_PHY_MMD3_WOL_MAGIC_MAC_CTRL3, phy_data3); - - return SW_OK; -} - -/****************************************************************************** -* -* malibu_phy_get wol frame mac address -* -* get phy wol frame mac address -*/ -sw_error_t -malibu_phy_get_magic_frame_mac(a_uint32_t dev_id, a_uint32_t phy_id, - fal_mac_addr_t * mac) -{ - a_uint16_t phy_data1; - a_uint16_t phy_data2; - a_uint16_t phy_data3; - - phy_data1 = malibu_phy_mmd_read(dev_id, phy_id, MALIBU_PHY_MMD3_NUM, - MALIBU_PHY_MMD3_WOL_MAGIC_MAC_CTRL1); - - phy_data2 = malibu_phy_mmd_read(dev_id, phy_id, MALIBU_PHY_MMD3_NUM, - MALIBU_PHY_MMD3_WOL_MAGIC_MAC_CTRL2); - - phy_data3 = malibu_phy_mmd_read(dev_id, phy_id, MALIBU_PHY_MMD3_NUM, - MALIBU_PHY_MMD3_WOL_MAGIC_MAC_CTRL3); - - mac->uc[0] = (phy_data1 >> 8); - mac->uc[1] = (phy_data1 & 0x00ff); - mac->uc[2] = (phy_data2 >> 8); - mac->uc[3] = (phy_data2 & 0x00ff); - mac->uc[4] = (phy_data3 >> 8); - mac->uc[5] = (phy_data3 & 0x00ff); - phy_data2 = (mac->uc[2] << 8) | mac->uc[3]; - phy_data3 = (mac->uc[4] << 8) | mac->uc[5]; - - return SW_OK; -} - -/****************************************************************************** -* -* malibu_phy_set wol enable or disable -* -* set phy wol enable or disable -*/ -sw_error_t -malibu_phy_set_wol_status(a_uint32_t dev_id, a_uint32_t phy_id, a_bool_t enable) -{ - a_uint16_t phy_data; - phy_data = malibu_phy_mmd_read(dev_id, phy_id, MALIBU_PHY_MMD3_NUM, - MALIBU_PHY_MMD3_WOL_CTRL); - - if (enable == A_TRUE) { - phy_data |= 0x0020; - } else { - phy_data &= ~0x0020; - } - - malibu_phy_mmd_write(dev_id, phy_id, MALIBU_PHY_MMD3_NUM, - MALIBU_PHY_MMD3_WOL_CTRL, phy_data); - - return SW_OK; -} - -/****************************************************************************** -* -* malibu_phy_get_wol status -* -* get wol status -*/ -sw_error_t -malibu_phy_get_wol_status(a_uint32_t dev_id, a_uint32_t phy_id, a_bool_t * enable) -{ - a_uint16_t phy_data; - - *enable = A_FALSE; - - phy_data = malibu_phy_mmd_read(dev_id, phy_id, MALIBU_PHY_MMD3_NUM, - MALIBU_PHY_MMD3_WOL_CTRL); - - if (phy_data & 0x0020) - *enable = A_TRUE; - - return SW_OK; -} -#endif -/****************************************************************************** -* -* malibu_serdes_reset - malibu psgmii serdes reset -* -* reset serdes -*/ -sw_error_t -malibu_phy_serdes_reset(a_uint32_t dev_id) -{ - - malibu_phy_reg_write(dev_id, first_phy_addr + MALIBU_PHY_PSGMII_ADDR_INC, - MALIBU_MODE_RESET_REG, MALIBU_MODE_CHANAGE_RESET); - mdelay(100); - malibu_phy_reg_write(dev_id, first_phy_addr + MALIBU_PHY_PSGMII_ADDR_INC, - MALIBU_MODE_RESET_REG, MALIBU_MODE_RESET_DEFAULT_VALUE); - - return SW_OK; -} - -/****************************************************************************** -* -* malibu_phy_interface mode set -* -* set malibu phy interface mode -*/ -sw_error_t -malibu_phy_interface_set_mode(a_uint32_t dev_id, a_uint32_t phy_id, fal_port_interface_mode_t interface_mode) -{ - a_uint16_t phy_data; - - if ((phy_id < first_phy_addr) || - (phy_id > (first_phy_addr + MALIBU_PHY_MAX_ADDR_INC))) - return SW_NOT_SUPPORTED; - - phy_data = malibu_phy_reg_read(dev_id, - first_phy_addr + MALIBU_PHY_MAX_ADDR_INC, MALIBU_PHY_CHIP_CONFIG); - phy_data &= 0xfff0; - - if (interface_mode == PHY_PSGMII_BASET) { - phy_data |= MALIBU_PHY_PSGMII_BASET; - } else if (interface_mode == PHY_PSGMII_BX1000) { - phy_data |= MALIBU_PHY_PSGMII_BX1000; - } else if (interface_mode == PHY_PSGMII_FX100) { - phy_data |= MALIBU_PHY_PSGMII_FX100; - } else if (interface_mode == PHY_PSGMII_AMDET) { - phy_data |= MALIBU_PHY_PSGMII_AMDET; - } else if (interface_mode == PHY_SGMII_BASET || - interface_mode == PORT_QSGMII) { - phy_data |= MALIBU_PHY_SGMII_BASET; - } else if (interface_mode == PHY_PSGMII_FIBER) { - phy_data |= MALIBU_PHY_PSGMII_AMDET; - } else { - return SW_BAD_PARAM; - } - - malibu_phy_reg_write(dev_id, - first_phy_addr + MALIBU_PHY_MAX_ADDR_INC, MALIBU_PHY_CHIP_CONFIG, phy_data); - - /* reset operation */ - malibu_phy_serdes_reset(dev_id); - - if (interface_mode == PHY_PSGMII_FIBER) { - malibu_phy_reg_write(dev_id, first_phy_addr + MALIBU_PHY_MAX_ADDR_INC, - MALIBU_PHY_CHIP_CONFIG, MALIBU_MODECTRL_DFLT); - malibu_phy_reg_write(dev_id, first_phy_addr + MALIBU_PHY_MAX_ADDR_INC, - MALIBU_PHY_CONTROL, MALIBU_MIICTRL_DFLT); - } - - return SW_OK; -} - -/****************************************************************************** -* -* malibu_phy_interface mode get -* -* get malibu phy interface mode -*/ -sw_error_t -malibu_phy_interface_get_mode(a_uint32_t dev_id, a_uint32_t phy_id, fal_port_interface_mode_t *interface_mode) -{ - a_uint16_t phy_data; - a_uint16_t copper_mode; - - if ((phy_id < first_phy_addr) || - (phy_id > (first_phy_addr + MALIBU_PHY_MAX_ADDR_INC))) { - return SW_NOT_SUPPORTED; - } - - phy_data = malibu_phy_reg_read(dev_id, - first_phy_addr + MALIBU_PHY_MAX_ADDR_INC, MALIBU_PHY_CHIP_CONFIG); - copper_mode = ((phy_data & MALIBU_PHY_COPPER_MODE) >> 0xf); - phy_data &= 0x000f; - - switch (phy_data) { - case MALIBU_PHY_PSGMII_BASET: - *interface_mode = PHY_PSGMII_BASET; - break; - case MALIBU_PHY_PSGMII_BX1000: - *interface_mode = PHY_PSGMII_BX1000; - break; - case MALIBU_PHY_PSGMII_FX100: - *interface_mode = PHY_PSGMII_FX100; - break; - case MALIBU_PHY_PSGMII_AMDET: - if (copper_mode) { - *interface_mode = PHY_PSGMII_AMDET; - } else { - if (phy_id == first_phy_addr + MALIBU_PHY_MAX_ADDR_INC) - *interface_mode = PHY_PSGMII_FIBER; - else - *interface_mode = PHY_PSGMII_AMDET; - } - break; - case MALIBU_PHY_SGMII_BASET: - if (phy_id == first_phy_addr + MALIBU_PHY_MAX_ADDR_INC) - *interface_mode = PHY_SGMII_BASET; - else - *interface_mode = PORT_QSGMII; - break; - default: - *interface_mode = PORT_INTERFACE_MODE_MAX; - break; - } - - return SW_OK; -} - -/****************************************************************************** -* -* malibu_phy_interface mode status get -* -* get malibu phy interface mode status -*/ -sw_error_t -malibu_phy_interface_get_mode_status(a_uint32_t dev_id, a_uint32_t phy_id, fal_port_interface_mode_t *interface_mode_status) -{ - a_uint16_t phy_data; - a_uint16_t copper_mode; - - if ((phy_id < first_phy_addr) || - (phy_id > (first_phy_addr + MALIBU_PHY_MAX_ADDR_INC))) { - return SW_NOT_SUPPORTED; - } - - phy_data = malibu_phy_reg_read(dev_id, - first_phy_addr + MALIBU_PHY_MAX_ADDR_INC, MALIBU_PHY_CHIP_CONFIG); - copper_mode = ((phy_data & MALIBU_PHY_COPPER_MODE) >> 0xf); - phy_data &= 0x00f0; - phy_data = (phy_data >>4); - - switch (phy_data) { - case MALIBU_PHY_PSGMII_BASET: - *interface_mode_status = PHY_PSGMII_BASET; - break; - case MALIBU_PHY_PSGMII_BX1000: - *interface_mode_status = PHY_PSGMII_BX1000; - break; - case MALIBU_PHY_PSGMII_FX100: - *interface_mode_status = PHY_PSGMII_FX100; - break; - case MALIBU_PHY_PSGMII_AMDET: - if (copper_mode) { - *interface_mode_status = PHY_PSGMII_BASET; - } else { - if (phy_id == first_phy_addr + MALIBU_PHY_MAX_ADDR_INC) - *interface_mode_status = PHY_PSGMII_FIBER; - else - *interface_mode_status = PHY_PSGMII_BASET; - } - break; - case MALIBU_PHY_SGMII_BASET: - if (phy_id == first_phy_addr + MALIBU_PHY_MAX_ADDR_INC) - *interface_mode_status = PHY_SGMII_BASET; - else - *interface_mode_status = PORT_QSGMII; - break; - default: - *interface_mode_status = PORT_INTERFACE_MODE_MAX; - break; - } - - return SW_OK; -} -#ifndef IN_PORTCONTROL_MINI -/****************************************************************************** -* -* malibu_phy_intr_mask_set - Set interrupt mask with the -* specified device. -*/ -sw_error_t -malibu_phy_intr_mask_set(a_uint32_t dev_id, a_uint32_t phy_id, - a_uint32_t intr_mask_flag) -{ - a_uint16_t phy_data = 0; - - phy_data = malibu_phy_reg_read(dev_id, phy_id, MALIBU_PHY_INTR_MASK); - - if (FAL_PHY_INTR_STATUS_UP_CHANGE & intr_mask_flag) { - phy_data |= MALIBU_INTR_STATUS_UP_CHANGE; - } else { - phy_data &= (~MALIBU_INTR_STATUS_UP_CHANGE); - } - - if (FAL_PHY_INTR_STATUS_DOWN_CHANGE & intr_mask_flag) { - phy_data |= MALIBU_INTR_STATUS_DOWN_CHANGE; - } else { - phy_data &= (~MALIBU_INTR_STATUS_DOWN_CHANGE); - } - - if (FAL_PHY_INTR_SPEED_CHANGE & intr_mask_flag) { - phy_data |= MALIBU_INTR_SPEED_CHANGE; - } else { - phy_data &= (~MALIBU_INTR_SPEED_CHANGE); - } - - if (FAL_PHY_INTR_DUPLEX_CHANGE & intr_mask_flag) { - phy_data |= MALIBU_INTR_DUPLEX_CHANGE; - } else { - phy_data &= (~MALIBU_INTR_DUPLEX_CHANGE); - } - - if (FAL_PHY_INTR_BX_FX_STATUS_UP_CHANGE & intr_mask_flag) { - phy_data |= MALIBU_INTR_BX_FX_STATUS_UP_CHANGE; - } else { - phy_data &= (~MALIBU_INTR_BX_FX_STATUS_UP_CHANGE); - } - - if (FAL_PHY_INTR_BX_FX_STATUS_DOWN_CHANGE & intr_mask_flag) { - phy_data |= MALIBU_INTR_BX_FX_STATUS_DOWN_CHANGE; - } else { - phy_data &= (~MALIBU_INTR_BX_FX_STATUS_DOWN_CHANGE); - } - - if (FAL_PHY_INTR_MEDIA_STATUS_CHANGE & intr_mask_flag) { - phy_data |= MALIBU_INTR_MEDIA_STATUS_CHANGE; - } else { - phy_data &= (~MALIBU_INTR_MEDIA_STATUS_CHANGE); - } - - if (FAL_PHY_INTR_WOL_STATUS & intr_mask_flag) { - phy_data |= MALIBU_INTR_WOL; - } else { - phy_data &= (~MALIBU_INTR_WOL); - } - - if (FAL_PHY_INTR_POE_STATUS & intr_mask_flag) { - phy_data |= MALIBU_INTR_POE; - } else { - phy_data &= (~MALIBU_INTR_POE); - } - - malibu_phy_reg_write(dev_id, phy_id, MALIBU_PHY_INTR_MASK, phy_data); - return SW_OK; -} - -/****************************************************************************** -* -* malibu_phy_intr_mask_get - Get interrupt mask with the -* specified device. -*/ -sw_error_t -malibu_phy_intr_mask_get(a_uint32_t dev_id, a_uint32_t phy_id, - a_uint32_t * intr_mask_flag) -{ - a_uint16_t phy_data = 0; - - phy_data = malibu_phy_reg_read(dev_id, phy_id, MALIBU_PHY_INTR_MASK); - - *intr_mask_flag = 0; - if (MALIBU_INTR_STATUS_UP_CHANGE & phy_data) { - *intr_mask_flag |= FAL_PHY_INTR_STATUS_UP_CHANGE; - } - - if (MALIBU_INTR_STATUS_DOWN_CHANGE & phy_data) { - *intr_mask_flag |= FAL_PHY_INTR_STATUS_DOWN_CHANGE; - } - - if (MALIBU_INTR_SPEED_CHANGE & phy_data) { - *intr_mask_flag |= FAL_PHY_INTR_SPEED_CHANGE; - } - - if (MALIBU_INTR_DUPLEX_CHANGE & phy_data) { - *intr_mask_flag |= FAL_PHY_INTR_DUPLEX_CHANGE; - } - - if (MALIBU_INTR_BX_FX_STATUS_UP_CHANGE & phy_data) { - *intr_mask_flag |= FAL_PHY_INTR_BX_FX_STATUS_UP_CHANGE; - } - - if (MALIBU_INTR_BX_FX_STATUS_DOWN_CHANGE & phy_data) { - *intr_mask_flag |= FAL_PHY_INTR_BX_FX_STATUS_DOWN_CHANGE; - } - - if (MALIBU_INTR_MEDIA_STATUS_CHANGE & phy_data) { - *intr_mask_flag |= FAL_PHY_INTR_MEDIA_STATUS_CHANGE; - } - - if (MALIBU_INTR_WOL & phy_data) { - *intr_mask_flag |= FAL_PHY_INTR_WOL_STATUS; - } - - if (MALIBU_INTR_POE & phy_data) { - *intr_mask_flag |= FAL_PHY_INTR_POE_STATUS; - } - - return SW_OK; -} - -/****************************************************************************** -* -* malibu_phy_intr_status_get - Get interrupt status with the -* specified device. -*/ -sw_error_t -malibu_phy_intr_status_get(a_uint32_t dev_id, a_uint32_t phy_id, - a_uint32_t * intr_status_flag) -{ - a_uint16_t phy_data = 0; - - phy_data = malibu_phy_reg_read(dev_id, phy_id, MALIBU_PHY_INTR_STATUS); - - *intr_status_flag = 0; - if (MALIBU_INTR_STATUS_UP_CHANGE & phy_data) { - *intr_status_flag |= FAL_PHY_INTR_STATUS_UP_CHANGE; - } - - if (MALIBU_INTR_STATUS_DOWN_CHANGE & phy_data) { - *intr_status_flag |= FAL_PHY_INTR_STATUS_DOWN_CHANGE; - } - - if (MALIBU_INTR_SPEED_CHANGE & phy_data) { - *intr_status_flag |= FAL_PHY_INTR_SPEED_CHANGE; - } - - if (MALIBU_INTR_DUPLEX_CHANGE & phy_data) { - *intr_status_flag |= FAL_PHY_INTR_DUPLEX_CHANGE; - } - - if (MALIBU_INTR_BX_FX_STATUS_UP_CHANGE & phy_data) { - *intr_status_flag |= FAL_PHY_INTR_BX_FX_STATUS_UP_CHANGE; - } - - if (MALIBU_INTR_BX_FX_STATUS_DOWN_CHANGE & phy_data) { - *intr_status_flag |= FAL_PHY_INTR_BX_FX_STATUS_DOWN_CHANGE; - } - if (MALIBU_INTR_MEDIA_STATUS_CHANGE & phy_data) { - *intr_status_flag |= FAL_PHY_INTR_MEDIA_STATUS_CHANGE; - } - - if (MALIBU_INTR_WOL & phy_data) { - *intr_status_flag |= FAL_PHY_INTR_WOL_STATUS; - } - - if (MALIBU_INTR_POE & phy_data) { - *intr_status_flag |= FAL_PHY_INTR_POE_STATUS; - } - - return SW_OK; -} - -/****************************************************************************** -* -* malibu_phy_set_counter - set counter status -* -* set counter status -*/ -sw_error_t -malibu_phy_set_counter(a_uint32_t dev_id, a_uint32_t phy_id, a_bool_t enable) -{ - a_uint16_t phy_data; - - phy_data = malibu_phy_mmd_read(dev_id, phy_id, MALIBU_PHY_MMD7_NUM, - MALIBU_PHY_MMD7_COUNTER_CTRL); - - if (enable == A_TRUE) { - phy_data |= 0x0003; - } else { - phy_data &= ~0x0003; - } - - malibu_phy_mmd_write(dev_id, phy_id, MALIBU_PHY_MMD7_NUM, - MALIBU_PHY_MMD7_COUNTER_CTRL, phy_data); - - return SW_OK; -} - -/****************************************************************************** -* -* malibu_phy_get_counter_status - get counter status -* -* set counter status -*/ -sw_error_t -malibu_phy_get_counter(a_uint32_t dev_id, a_uint32_t phy_id, - a_bool_t * enable) -{ - a_uint16_t phy_data; - - *enable = A_FALSE; - - phy_data = malibu_phy_mmd_read(dev_id, phy_id, MALIBU_PHY_MMD7_NUM, - MALIBU_PHY_MMD7_COUNTER_CTRL); - - if (phy_data & 0x0001) - *enable = A_TRUE; - - return SW_OK; -} - -/****************************************************************************** -* -* malibu_phy_show show counter statistics -* -* show counter statistics -*/ -sw_error_t -malibu_phy_show_counter(a_uint32_t dev_id, a_uint32_t phy_id, - fal_port_counter_info_t * counter_infor) -{ - a_uint16_t ingress_high_counter; - a_uint16_t ingress_low_counter; - a_uint16_t egress_high_counter; - a_uint16_t egress_low_counter; - - ingress_high_counter = malibu_phy_mmd_read(dev_id, phy_id, MALIBU_PHY_MMD7_NUM, - MALIBU_PHY_MMD7_INGRESS_COUNTER_HIGH); - ingress_low_counter = malibu_phy_mmd_read(dev_id, phy_id, MALIBU_PHY_MMD7_NUM, - MALIBU_PHY_MMD7_INGRESS_COUNTER_LOW); - counter_infor->RxGoodFrame = (ingress_high_counter << 16 ) | ingress_low_counter; - counter_infor->RxBadCRC = malibu_phy_mmd_read(dev_id, phy_id, MALIBU_PHY_MMD7_NUM, - MALIBU_PHY_MMD7_INGRESS_ERROR_COUNTER); - - egress_high_counter = malibu_phy_mmd_read(dev_id, phy_id, MALIBU_PHY_MMD7_NUM, - MALIBU_PHY_MMD7_EGRESS_COUNTER_HIGH); - egress_low_counter = malibu_phy_mmd_read(dev_id, phy_id, MALIBU_PHY_MMD7_NUM, - MALIBU_PHY_MMD7_EGRESS_COUNTER_LOW); - counter_infor->TxGoodFrame = (egress_high_counter << 16 ) | egress_low_counter; - counter_infor->TxBadCRC = malibu_phy_mmd_read(dev_id, phy_id, MALIBU_PHY_MMD7_NUM, - MALIBU_PHY_MMD7_EGRESS_ERROR_COUNTER); - - return SW_OK; -} -#endif -/****************************************************************************** -* -* malibu_phy_get status -* -* get phy status -*/ -sw_error_t -malibu_phy_get_status(a_uint32_t dev_id, a_uint32_t phy_id, - struct port_phy_status *phy_status) -{ - a_uint16_t phy_data; - - if (phy_id == COMBO_PHY_ID) { - __phy_reg_pages_sel_by_active_medium(dev_id, phy_id); - } - - phy_data = malibu_phy_reg_read(dev_id, phy_id, MALIBU_PHY_SPEC_STATUS); - - /*get phy link status*/ - if (phy_data & MALIBU_STATUS_LINK_PASS) { - phy_status->link_status = A_TRUE; - } else { - phy_status->link_status = A_FALSE; - return SW_OK; - } - - /*get phy speed*/ - switch (phy_data & MALIBU_STATUS_SPEED_MASK) { - case MALIBU_STATUS_SPEED_1000MBS: - phy_status->speed = FAL_SPEED_1000; - break; - case MALIBU_STATUS_SPEED_100MBS: - phy_status->speed = FAL_SPEED_100; - break; - case MALIBU_STATUS_SPEED_10MBS: - phy_status->speed = FAL_SPEED_10; - break; - default: - return SW_READ_ERROR; - } - - /*get phy duplex*/ - if (phy_data & MALIBU_STATUS_FULL_DUPLEX) { - phy_status->duplex = FAL_FULL_DUPLEX; - } else { - phy_status->duplex = FAL_HALF_DUPLEX; - } - - /* get phy flowctrl resolution status */ - if (phy_data & MALIBU_PHY_RX_FLOWCTRL_STATUS) { - phy_status->rx_flowctrl = A_TRUE; - } else { - phy_status->rx_flowctrl = A_FALSE; - } - - if (phy_data & MALIBU_PHY_TX_FLOWCTRL_STATUS) { - phy_status->tx_flowctrl = A_TRUE; - } else { - phy_status->tx_flowctrl = A_FALSE; - } - - return SW_OK; -} -/****************************************************************************** -* -* malibu_phy_set_eee_advertisement -* -* set eee advertisement -*/ -sw_error_t -malibu_phy_set_eee_adv(a_uint32_t dev_id, a_uint32_t phy_id, - a_uint32_t adv) -{ - a_uint16_t phy_data = 0; - sw_error_t rv = SW_OK; - - if (phy_id == COMBO_PHY_ID) { - if (MALIBU_PHY_MEDIUM_COPPER != - __phy_active_medium_get(dev_id, phy_id)) - return SW_NOT_SUPPORTED; - } - - phy_data = malibu_phy_mmd_read(dev_id, phy_id, MALIBU_PHY_MMD7_NUM, - MALIBU_PHY_MMD7_ADDR_8023AZ_EEE_CTRL); - phy_data &= ~(MALIBU_PHY_EEE_ADV_100M | MALIBU_PHY_EEE_ADV_1000M); - - if (adv & FAL_PHY_EEE_100BASE_T) { - phy_data |= MALIBU_PHY_EEE_ADV_100M; - } - if (adv & FAL_PHY_EEE_1000BASE_T) { - phy_data |= MALIBU_PHY_EEE_ADV_1000M; - } - - rv = malibu_phy_mmd_write(dev_id, phy_id, MALIBU_PHY_MMD7_NUM, - MALIBU_PHY_MMD7_ADDR_8023AZ_EEE_CTRL, phy_data); - - rv = malibu_phy_restart_autoneg(dev_id, phy_id); - - return rv; - -} - -/****************************************************************************** -* -* malibu_phy_get_eee_advertisement -* -* get eee advertisement -*/ -sw_error_t -malibu_phy_get_eee_adv(a_uint32_t dev_id, a_uint32_t phy_id, - a_uint32_t *adv) -{ - a_uint16_t phy_data = 0; - sw_error_t rv = SW_OK; - - if (phy_id == COMBO_PHY_ID) { - if (MALIBU_PHY_MEDIUM_COPPER != - __phy_active_medium_get(dev_id, phy_id)) - return SW_NOT_SUPPORTED; - } - - *adv = 0; - phy_data = malibu_phy_mmd_read(dev_id, phy_id, MALIBU_PHY_MMD7_NUM, - MALIBU_PHY_MMD7_ADDR_8023AZ_EEE_CTRL); - - if (phy_data & MALIBU_PHY_EEE_ADV_100M) { - *adv |= FAL_PHY_EEE_100BASE_T; - } - if (phy_data & MALIBU_PHY_EEE_ADV_1000M) { - *adv |= FAL_PHY_EEE_1000BASE_T; - } - - return rv; -} -/****************************************************************************** -* -* malibu_phy_get_eee_partner_advertisement -* -* get eee partner advertisement -*/ -sw_error_t -malibu_phy_get_eee_partner_adv(a_uint32_t dev_id, a_uint32_t phy_id, - a_uint32_t *adv) -{ - a_uint16_t phy_data = 0; - sw_error_t rv = SW_OK; - - if (phy_id == COMBO_PHY_ID) { - if (MALIBU_PHY_MEDIUM_COPPER != - __phy_active_medium_get(dev_id, phy_id)) - return SW_NOT_SUPPORTED; - } - - *adv = 0; - phy_data = malibu_phy_mmd_read(dev_id, phy_id, MALIBU_PHY_MMD7_NUM, - MALIBU_PHY_MMD7_ADDR_8023AZ_EEE_PARTNER); - - if (phy_data & MALIBU_PHY_EEE_PARTNER_ADV_100M) { - *adv |= FAL_PHY_EEE_100BASE_T; - } - if (phy_data & MALIBU_PHY_EEE_PARTNER_ADV_1000M) { - *adv |= FAL_PHY_EEE_1000BASE_T; - } - - return rv; -} -/****************************************************************************** -* -* malibu_phy_get_eee_capability -* -* get eee capability -*/ -sw_error_t -malibu_phy_get_eee_cap(a_uint32_t dev_id, a_uint32_t phy_id, - a_uint32_t *cap) -{ - a_uint16_t phy_data = 0; - sw_error_t rv = SW_OK; - - if (phy_id == COMBO_PHY_ID) { - if (MALIBU_PHY_MEDIUM_COPPER != - __phy_active_medium_get(dev_id, phy_id)) - return SW_NOT_SUPPORTED; - } - - *cap = 0; - phy_data = malibu_phy_mmd_read(dev_id, phy_id, MALIBU_PHY_MMD3_NUM, - MALIBU_PHY_MMD3_ADDR_8023AZ_EEE_CAPABILITY); - - if (phy_data & MALIBU_PHY_EEE_CAPABILITY_100M) { - *cap |= FAL_PHY_EEE_100BASE_T; - } - if (phy_data & MALIBU_PHY_EEE_CAPABILITY_1000M) { - *cap |= FAL_PHY_EEE_1000BASE_T; - } - - return rv; -} -/****************************************************************************** -* -* malibu_phy_get_eee_status -* -* get eee status -*/ -sw_error_t -malibu_phy_get_eee_status(a_uint32_t dev_id, a_uint32_t phy_id, - a_uint32_t *status) -{ - a_uint16_t phy_data = 0; - sw_error_t rv = SW_OK; - - if (phy_id == COMBO_PHY_ID) { - if (MALIBU_PHY_MEDIUM_COPPER != - __phy_active_medium_get(dev_id, phy_id)) - return SW_NOT_SUPPORTED; - } - - *status = 0; - phy_data = malibu_phy_mmd_read(dev_id, phy_id, MALIBU_PHY_MMD7_NUM, - MALIBU_PHY_MMD7_ADDR_8023AZ_EEE_STATUS); - - if (phy_data & MALIBU_PHY_EEE_STATUS_100M) { - *status |= FAL_PHY_EEE_100BASE_T; - } - if (phy_data & MALIBU_PHY_EEE_STATUS_1000M) { - *status |= FAL_PHY_EEE_1000BASE_T; - } - - return rv; -} -/****************************************************************************** -* -* malibu_phy_hw_register init -* -*/ -sw_error_t -malibu_phy_hw_init(a_uint32_t dev_id, a_uint32_t port_bmp) -{ - a_uint32_t port_id = 0, phy_addr = 0, phy_cnt = 0; - a_uint16_t dac_value,led_status, phy_data; - a_uint32_t mode; - - for (port_id = 0; port_id < SW_MAX_NR_PORT; port_id ++) - { - if (port_bmp & (0x1 << port_id)) - { - phy_cnt ++; - phy_addr = qca_ssdk_port_to_phy_addr(dev_id, port_id); - if (phy_addr < first_phy_addr) - { - first_phy_addr = phy_addr; - } - /*enable phy power saving function by default */ - malibu_phy_set_8023az(dev_id, phy_addr, A_TRUE); - malibu_phy_set_powersave(dev_id, phy_addr, A_TRUE); - malibu_phy_set_hibernate(dev_id, phy_addr, A_TRUE); - /*change malibu control_dac[2:0] of MMD7 0x801A bit[9:7] from 111 to 101*/ - dac_value = malibu_phy_mmd_read(dev_id, phy_addr, MALIBU_PHY_MMD7_NUM, - MALIBU_PHY_MMD7_DAC_CTRL); - dac_value &= ~MALIBU_DAC_CTRL_MASK; - dac_value |= MALIBU_DAC_CTRL_VALUE; - malibu_phy_mmd_write(dev_id, phy_addr, MALIBU_PHY_MMD7_NUM, - MALIBU_PHY_MMD7_DAC_CTRL, dac_value); - - /* add 10M and 100M link LED behavior for QFN board*/ - led_status = malibu_phy_mmd_read(dev_id, phy_addr, MALIBU_PHY_MMD7_NUM, - MALIBU_PHY_MMD7_LED_1000_CTRL1); - led_status &= ~MALIBU_LED_1000_CTRL1_100_10_MASK; - led_status |= MALIBU_LED_1000_CTRL1_100_10_MASK; - malibu_phy_mmd_write(dev_id, phy_addr, MALIBU_PHY_MMD7_NUM, - MALIBU_PHY_MMD7_LED_1000_CTRL1, led_status); - /*disable Extended next page*/ - phy_data = malibu_phy_reg_read(dev_id, phy_addr, MALIBU_AUTONEG_ADVERT); - phy_data &= ~MALIBU_EXTENDED_NEXT_PAGE_EN; - malibu_phy_reg_write(dev_id, phy_addr, MALIBU_AUTONEG_ADVERT, phy_data); - } - } - /* qca 8072 two ports phy chip's firstly address to init phy chip */ - if ((phy_cnt == QCA8072_PHY_NUM) && (first_phy_addr >= 0x3)) { - first_phy_addr = first_phy_addr - 0x3; - } - - /*workaround to enable AZ transmitting ability*/ - malibu_phy_mmd_write(dev_id, first_phy_addr + 5, MALIBU_PHY_MMD1_NUM, - MALIBU_PSGMII_MODE_CTRL, MALIBU_PHY_PSGMII_MODE_CTRL_ADJUST_VALUE); - - /* adjust psgmii serdes tx amp */ - malibu_phy_reg_write(dev_id, first_phy_addr + 5, MALIBU_PSGMII_TX_DRIVER_1_CTRL, - MALIBU_PHY_PSGMII_REDUCE_SERDES_TX_AMP); - - /* to avoid psgmii module goes into hibernation, work with psgmii self test*/ - phy_data = malibu_phy_mmd_read(dev_id, first_phy_addr + 4, MALIBU_PHY_MMD3_NUM, - MALIBU_PHY_MMD3_ADDR_REMOTE_LOOPBACK_CTRL); - phy_data &= (~(1<<1)); - malibu_phy_mmd_write(dev_id, first_phy_addr + 4, MALIBU_PHY_MMD3_NUM, - MALIBU_PHY_MMD3_ADDR_REMOTE_LOOPBACK_CTRL, phy_data); - - - mode = ssdk_dt_global_get_mac_mode(dev_id, 0); - if (mode == PORT_WRAPPER_PSGMII_FIBER) - malibu_phy_interface_set_mode(dev_id, first_phy_addr, PHY_PSGMII_FIBER); - return SW_OK; -} - -static int malibu_phy_api_ops_init(void) -{ - - int ret; - hsl_phy_ops_t *malibu_phy_api_ops = NULL; - - malibu_phy_api_ops = kzalloc(sizeof(hsl_phy_ops_t), GFP_KERNEL); - if (malibu_phy_api_ops == NULL) { - SSDK_ERROR("malibu phy ops kzalloc failed!\n"); - return -ENOMEM; - } - - phy_api_ops_init(MALIBU_PHY_CHIP); -#ifndef IN_PORTCONTROL_MINI - malibu_phy_api_ops->phy_hibernation_set = malibu_phy_set_hibernate; - malibu_phy_api_ops->phy_hibernation_get = malibu_phy_get_hibernate; -#endif - malibu_phy_api_ops->phy_speed_get = malibu_phy_get_speed; - malibu_phy_api_ops->phy_speed_set = malibu_phy_set_speed; - malibu_phy_api_ops->phy_duplex_get = malibu_phy_get_duplex; - malibu_phy_api_ops->phy_duplex_set = malibu_phy_set_duplex; - malibu_phy_api_ops->phy_autoneg_enable_set = malibu_phy_enable_autoneg; - malibu_phy_api_ops->phy_restart_autoneg = malibu_phy_restart_autoneg; - malibu_phy_api_ops->phy_autoneg_status_get = malibu_phy_autoneg_status; - malibu_phy_api_ops->phy_autoneg_adv_set = malibu_phy_set_autoneg_adv; - malibu_phy_api_ops->phy_autoneg_adv_get = malibu_phy_get_autoneg_adv; -#ifndef IN_PORTCONTROL_MINI - malibu_phy_api_ops->phy_powersave_set = malibu_phy_set_powersave; - malibu_phy_api_ops->phy_powersave_get = malibu_phy_get_powersave; - malibu_phy_api_ops->phy_cdt = malibu_phy_cdt; -#endif - malibu_phy_api_ops->phy_link_status_get = malibu_phy_get_link_status; -#ifndef IN_PORTCONTROL_MINI - malibu_phy_api_ops->phy_mdix_set = malibu_phy_set_mdix; - malibu_phy_api_ops->phy_mdix_get = malibu_phy_get_mdix; - malibu_phy_api_ops->phy_mdix_status_get = malibu_phy_get_mdix_status; - malibu_phy_api_ops->phy_8023az_set = malibu_phy_set_8023az; - malibu_phy_api_ops->phy_8023az_get = malibu_phy_get_8023az; - malibu_phy_api_ops->phy_local_loopback_set = malibu_phy_set_local_loopback; - malibu_phy_api_ops->phy_local_loopback_get = malibu_phy_get_local_loopback; - malibu_phy_api_ops->phy_remote_loopback_set = malibu_phy_set_remote_loopback; - malibu_phy_api_ops->phy_remote_loopback_get = malibu_phy_get_remote_loopback; - malibu_phy_api_ops->phy_combo_prefer_medium_set = malibu_phy_set_combo_prefer_medium; - malibu_phy_api_ops->phy_combo_prefer_medium_get = malibu_phy_get_combo_prefer_medium; - malibu_phy_api_ops->phy_combo_medium_status_get = malibu_phy_get_combo_current_medium_type; - malibu_phy_api_ops->phy_combo_fiber_mode_set = malibu_phy_set_combo_fiber_mode; - malibu_phy_api_ops->phy_combo_fiber_mode_get = malibu_phy_get_combo_fiber_mode; - malibu_phy_api_ops->phy_reset = malibu_phy_reset; -#endif - malibu_phy_api_ops->phy_power_off = malibu_phy_poweroff; - malibu_phy_api_ops->phy_power_on = malibu_phy_poweron; - malibu_phy_api_ops->phy_id_get = malibu_phy_get_phy_id; - malibu_phy_api_ops->phy_reg_write = malibu_phy_reg_write; - malibu_phy_api_ops->phy_reg_read = malibu_phy_reg_read; - malibu_phy_api_ops->phy_debug_write = malibu_phy_debug_write; - malibu_phy_api_ops->phy_debug_read = malibu_phy_debug_read; - malibu_phy_api_ops->phy_mmd_write = malibu_phy_mmd_write; - malibu_phy_api_ops->phy_mmd_read = malibu_phy_mmd_read; -#ifndef IN_PORTCONTROL_MINI - malibu_phy_api_ops->phy_magic_frame_mac_set = malibu_phy_set_magic_frame_mac; - malibu_phy_api_ops->phy_magic_frame_mac_get = malibu_phy_get_magic_frame_mac; - malibu_phy_api_ops->phy_wol_status_set = malibu_phy_set_wol_status; - malibu_phy_api_ops->phy_wol_status_get = malibu_phy_get_wol_status; -#endif - malibu_phy_api_ops->phy_interface_mode_set = malibu_phy_interface_set_mode; - malibu_phy_api_ops->phy_interface_mode_get = malibu_phy_interface_get_mode; - malibu_phy_api_ops->phy_interface_mode_status_get = malibu_phy_interface_get_mode_status; -#ifndef IN_PORTCONTROL_MINI - malibu_phy_api_ops->phy_intr_mask_set = malibu_phy_intr_mask_set; - malibu_phy_api_ops->phy_intr_mask_get = malibu_phy_intr_mask_get; - malibu_phy_api_ops->phy_intr_status_get = malibu_phy_intr_status_get; - malibu_phy_api_ops->phy_counter_set = malibu_phy_set_counter; - malibu_phy_api_ops->phy_counter_get = malibu_phy_get_counter; - malibu_phy_api_ops->phy_counter_show = malibu_phy_show_counter; -#endif - malibu_phy_api_ops->phy_serdes_reset = malibu_phy_serdes_reset; - malibu_phy_api_ops->phy_get_status = malibu_phy_get_status; - malibu_phy_api_ops->phy_eee_adv_set = malibu_phy_set_eee_adv; - malibu_phy_api_ops->phy_eee_adv_get = malibu_phy_get_eee_adv; - malibu_phy_api_ops->phy_eee_partner_adv_get = malibu_phy_get_eee_partner_adv; - malibu_phy_api_ops->phy_eee_cap_get = malibu_phy_get_eee_cap; - malibu_phy_api_ops->phy_eee_status_get = malibu_phy_get_eee_status; - - ret = hsl_phy_api_ops_register(MALIBU_PHY_CHIP, malibu_phy_api_ops); - - if (ret == 0) - SSDK_INFO("qca probe malibu phy driver succeeded!\n"); - else - SSDK_ERROR("qca probe malibu phy driver failed! (code: %d)\n", ret); - return ret; -} - -/****************************************************************************** -* -* malibu_phy_init - -* -*/ -int malibu_phy_init(a_uint32_t dev_id, a_uint32_t port_bmp) -{ - static a_uint32_t phy_ops_flag = 0; - - if(phy_ops_flag == 0) { - malibu_phy_api_ops_init(); - phy_ops_flag = 1; - } - malibu_phy_hw_init(dev_id, port_bmp); - - return 0; -} - diff --git a/feeds/ipq807x/qca-ssdk/src/src/hsl/phy/mpge_led.c b/feeds/ipq807x/qca-ssdk/src/src/hsl/phy/mpge_led.c deleted file mode 100644 index 31f47f709..000000000 --- a/feeds/ipq807x/qca-ssdk/src/src/hsl/phy/mpge_led.c +++ /dev/null @@ -1,66 +0,0 @@ -/* - * Copyright (c) 2020, The Linux Foundation. All rights reserved. - * - * Permission to use, copy, modify, and/or distribute this software for any - * purpose with or without fee is hereby granted, provided that the above - * copyright notice and this permission notice appear in all copies. - * - * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES - * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR - * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES - * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN - * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF - * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. - */ - -#include "sw.h" -#include "hsl_phy.h" -#include "qca808x_led.h" - -/****************************************************************************** -* -* mpge_phy_led_ctrl_pattern_set - set led behavior -* -*/ -sw_error_t -mpge_phy_led_ctrl_pattern_set(a_uint32_t dev_id, a_uint32_t phy_id, - led_ctrl_pattern_t *pattern) -{ - return qca808x_phy_led_ctrl_pattern_set(dev_id, phy_id, pattern); -} - -/****************************************************************************** -* -* mpge_phy_led_ctrl_pattern_get - get led behavior -* -*/ -sw_error_t -mpge_phy_led_ctrl_pattern_get(a_uint32_t dev_id, a_uint32_t phy_id, - led_ctrl_pattern_t * pattern) -{ - return qca808x_phy_led_ctrl_pattern_get(dev_id, phy_id, pattern); -} -/****************************************************************************** -* -* mpge_phy_led_source_pattern_set - set led behavior based on source id -* -*/ -sw_error_t -mpge_phy_led_ctrl_source_set(a_uint32_t dev_id, a_uint32_t phy_id, - a_uint32_t source_id, led_ctrl_pattern_t * pattern) -{ - return qca808x_phy_led_ctrl_source_set(dev_id, phy_id, source_id, pattern); -} - -void mpge_phy_led_api_ops_init(hsl_phy_ops_t *mpge_phy_led_api_ops) -{ - if (!mpge_phy_led_api_ops) { - return; - } - mpge_phy_led_api_ops->phy_led_ctrl_pattern_get = mpge_phy_led_ctrl_pattern_get; - mpge_phy_led_api_ops->phy_led_ctrl_pattern_set = mpge_phy_led_ctrl_pattern_set; - mpge_phy_led_api_ops->phy_led_ctrl_source_set = mpge_phy_led_ctrl_source_set; - - return; -} diff --git a/feeds/ipq807x/qca-ssdk/src/src/hsl/phy/mpge_phy.c b/feeds/ipq807x/qca-ssdk/src/src/hsl/phy/mpge_phy.c deleted file mode 100644 index dc4d31ef1..000000000 --- a/feeds/ipq807x/qca-ssdk/src/src/hsl/phy/mpge_phy.c +++ /dev/null @@ -1,1117 +0,0 @@ -/* - * Copyright (c) 2020, The Linux Foundation. All rights reserved. - * - * Permission to use, copy, modify, and/or distribute this software for any - * purpose with or without fee is hereby granted, provided that the above - * copyright notice and this permission notice appear in all copies. - * - * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES - * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR - * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES - * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN - * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF - * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. - */ - -#include "sw.h" -#include "fal_port_ctrl.h" -#include "hsl_api.h" -#include "hsl.h" -#include "hsl_phy.h" -#include "ssdk_plat.h" -#include "qca808x_phy.h" -#include "mpge_phy.h" -#ifdef IN_LED -#include "mpge_led.h" -#endif - -#define PHY_DAC(val) (val<<8) - -/****************************************************************************** -* -* mpge_phy_mii_read - mii register read -* -*/ -static a_uint16_t -mpge_phy_reg_read (a_uint32_t dev_id, a_uint32_t phy_id, a_uint32_t reg_id) -{ - return qca808x_phy_reg_read (dev_id, phy_id, reg_id); -} - -/****************************************************************************** -* -* mpge_phy_mii_write - mii register write -* -*/ -static sw_error_t -mpge_phy_reg_write (a_uint32_t dev_id, a_uint32_t phy_id, a_uint32_t reg_id, - a_uint16_t reg_val) -{ - return qca808x_phy_reg_write (dev_id, phy_id, reg_id, reg_val); -} - -/****************************************************************************** -* -* mpge_phy_debug_read - debug port read -* -*/ -static a_uint16_t -mpge_phy_debug_read(a_uint32_t dev_id, a_uint32_t phy_id, a_uint16_t reg_id) -{ - return qca808x_phy_debug_read(dev_id, phy_id, reg_id); -} - -/****************************************************************************** -* -* mpge_phy_debug_write - debug port write -* -*/ -static sw_error_t -mpge_phy_debug_write(a_uint32_t dev_id, a_uint32_t phy_id, a_uint16_t reg_id, - a_uint16_t reg_val) -{ - return qca808x_phy_debug_write (dev_id, phy_id, reg_id, reg_val); -} - -/****************************************************************************** -* -* mpge_phy_mmd_read - PHY MMD register read -* -*/ -static a_uint16_t -mpge_phy_mmd_read(a_uint32_t dev_id, a_uint32_t phy_id, - a_uint16_t mmd_num, a_uint16_t reg_id) -{ - return qca808x_phy_mmd_read(dev_id, phy_id, mmd_num, reg_id); -} - -/****************************************************************************** -* -* mpge_phy_mmd_write - PHY MMD register write -* -*/ -static sw_error_t -mpge_phy_mmd_write(a_uint32_t dev_id, a_uint32_t phy_id, - a_uint16_t mmd_num, a_uint16_t reg_id, a_uint16_t reg_val) -{ - return qca808x_phy_mmd_write (dev_id, phy_id, mmd_num, - reg_id, reg_val); -} - -/****************************************************************************** -* -* mpge_phy_get_status - get the phy status -* -*/ -static sw_error_t -mpge_phy_get_status(a_uint32_t dev_id, a_uint32_t phy_id, - struct port_phy_status *phy_status) -{ - return qca808x_phy_get_status(dev_id, phy_id, phy_status); -} - -/****************************************************************************** -* -* mpge_set_autoneg_adv - set the phy autoneg Advertisement -* -*/ -static sw_error_t -mpge_phy_set_autoneg_adv(a_uint32_t dev_id, a_uint32_t phy_id, - a_uint32_t autoneg) -{ - if (autoneg & (~FAL_PHY_GE_ADV_ALL)) - { - SSDK_ERROR("autoneg adv caps 0x%x is not support for MP\n", autoneg); - return SW_BAD_PARAM; - } - return qca808x_phy_set_autoneg_adv(dev_id, phy_id, autoneg); -} - -/****************************************************************************** -* -* mpge_get_autoneg_adv - get the phy autoneg Advertisement -* -*/ -static sw_error_t -mpge_phy_get_autoneg_adv(a_uint32_t dev_id, a_uint32_t phy_id, - a_uint32_t * autoneg) -{ - return qca808x_phy_get_autoneg_adv(dev_id, phy_id, autoneg); -} - -/****************************************************************************** -* -* mpge_phy_get_speed - Determines the speed of phy ports associated with the -* specified device. -*/ - -static sw_error_t -mpge_phy_get_speed(a_uint32_t dev_id, a_uint32_t phy_id, - fal_port_speed_t * speed) -{ - return qca808x_phy_get_speed(dev_id, phy_id, speed); -} - -/****************************************************************************** -* -* mpge_phy_get_duplex - Determines the duplex of phy ports associated with the -* specified device. -*/ -static sw_error_t -mpge_phy_get_duplex(a_uint32_t dev_id, a_uint32_t phy_id, - fal_port_duplex_t * duplex) -{ - return qca808x_phy_get_duplex(dev_id, phy_id, duplex); -} - -/****************************************************************************** -* -* mpge_phy_set_speed - Set the speed of phy ports associated with the -* specified device. -*/ -static sw_error_t -mpge_phy_set_speed(a_uint32_t dev_id, a_uint32_t phy_id, - fal_port_speed_t speed) -{ - a_uint16_t phy_data = 0; - a_uint32_t autoneg = 0; - fal_port_duplex_t old_duplex = MPGE_CTRL_FULL_DUPLEX; - sw_error_t rv = SW_OK; - - phy_data = mpge_phy_reg_read(dev_id, phy_id, MPGE_PHY_CONTROL); - PHY_RTN_ON_READ_ERROR(phy_data); - - switch(speed) - { - case FAL_SPEED_1000: - rv = mpge_phy_get_autoneg_adv(dev_id, phy_id, &autoneg); - PHY_RTN_ON_ERROR(rv); - if (!(autoneg & FAL_PHY_ADV_1000T_FD)) { - rv = mpge_phy_set_autoneg_adv(dev_id, phy_id, - autoneg | FAL_PHY_ADV_1000T_FD); - PHY_RTN_ON_ERROR(rv); - } - phy_data |= MPGE_CTRL_FULL_DUPLEX; - phy_data |= MPGE_CTRL_AUTONEGOTIATION_ENABLE; - phy_data |= MPGE_CTRL_RESTART_AUTONEGOTIATION; - break; - case FAL_SPEED_100: - case FAL_SPEED_10: - phy_data &= ~MPGE_CONTROL_SPEED_MASK; - if (speed == FAL_SPEED_100) { - phy_data |= MPGE_CONTROL_100M; - } else { - phy_data |= MPGE_CONTROL_10M; - } - rv = mpge_phy_get_duplex(dev_id, phy_id, &old_duplex); - PHY_RTN_ON_ERROR(rv); - - if (old_duplex == FAL_FULL_DUPLEX) { - phy_data |= MPGE_CTRL_FULL_DUPLEX; - } - else if (old_duplex == FAL_HALF_DUPLEX) { - phy_data &= ~MPGE_CTRL_FULL_DUPLEX; - } - phy_data &= ~MPGE_CTRL_AUTONEGOTIATION_ENABLE; - break; - default: - return SW_BAD_PARAM; - } - rv = mpge_phy_reg_write(dev_id, phy_id, MPGE_PHY_CONTROL, phy_data); - - return rv; -} - -/****************************************************************************** -* -* mpge_phy_set_duplex - Set the duplex of phy ports associated with the -* specified device. -*/ -static sw_error_t -mpge_phy_set_duplex(a_uint32_t dev_id, a_uint32_t phy_id, - fal_port_duplex_t duplex) -{ - - a_uint16_t phy_data = 0; - a_uint32_t autoneg = 0; - fal_port_speed_t old_speed; - sw_error_t rv = SW_OK; - - phy_data = mpge_phy_reg_read(dev_id, phy_id, MPGE_PHY_CONTROL); - PHY_RTN_ON_READ_ERROR(phy_data); - - rv = mpge_phy_get_speed(dev_id, phy_id, &old_speed); - PHY_RTN_ON_ERROR(rv); - - switch(old_speed) - { - case FAL_SPEED_1000: - if (duplex == FAL_FULL_DUPLEX) { - phy_data |= MPGE_CTRL_FULL_DUPLEX; - } else { - return SW_NOT_SUPPORTED; - } - phy_data |= MPGE_CTRL_AUTONEGOTIATION_ENABLE; - rv = mpge_phy_get_autoneg_adv(dev_id, phy_id, &autoneg); - PHY_RTN_ON_ERROR(rv); - if (!(autoneg & FAL_PHY_ADV_1000T_FD)) { - rv = mpge_phy_set_autoneg_adv(dev_id, phy_id, - autoneg | FAL_PHY_ADV_1000T_FD); - PHY_RTN_ON_ERROR(rv); - } - break; - case FAL_SPEED_100: - case FAL_SPEED_10: - phy_data &= ~MPGE_CONTROL_SPEED_MASK; - if (old_speed == FAL_SPEED_100) { - phy_data |= MPGE_CONTROL_100M; - } else { - phy_data |= MPGE_CONTROL_10M; - } - phy_data &= ~MPGE_CTRL_AUTONEGOTIATION_ENABLE; - if (duplex == FAL_FULL_DUPLEX) { - phy_data |= MPGE_CTRL_FULL_DUPLEX; - } else { - phy_data &= ~MPGE_CTRL_FULL_DUPLEX; - } - break; - default: - return SW_FAIL; - } - rv = mpge_phy_reg_write(dev_id, phy_id, MPGE_PHY_CONTROL, phy_data); - - return rv; -} - -/****************************************************************************** -* -* mpge_phy_enable_autoneg - enable the phy autoneg -* -*/ -static sw_error_t -mpge_phy_enable_autoneg(a_uint32_t dev_id, a_uint32_t phy_id) -{ - return qca808x_phy_enable_autoneg(dev_id, phy_id); -} - -/****************************************************************************** -* -* mpge_restart_autoneg - restart the phy autoneg -* -*/ -static sw_error_t -mpge_phy_restart_autoneg(a_uint32_t dev_id, a_uint32_t phy_id) -{ - return qca808x_phy_restart_autoneg(dev_id, phy_id); -} - -/****************************************************************************** -* -* mpge_phy_autoneg_status - get the phy autoneg status -* -*/ -static a_bool_t -mpge_phy_autoneg_status(a_uint32_t dev_id, a_uint32_t phy_id) -{ - return qca808x_phy_autoneg_status(dev_id, phy_id); -} - -/****************************************************************************** -* -* mpge_phy_status - get the phy link status -* -* RETURNS: -* A_TRUE --> link is alive -* A_FALSE --> link is down -*/ -static a_bool_t -mpge_phy_get_link_status(a_uint32_t dev_id, a_uint32_t phy_id) -{ - return qca808x_phy_get_link_status(dev_id, phy_id); -} - -/****************************************************************************** -* -* mpge_phy_reset - reset the phy -* -*/ -static sw_error_t -mpge_phy_reset(a_uint32_t dev_id, a_uint32_t phy_id) -{ - return qca808x_phy_reset(dev_id, phy_id); -} - - -/****************************************************************************** -* -* mpge_phy_get_phy_id - get the phy id -* -*/ -static sw_error_t -mpge_phy_get_phy_id(a_uint32_t dev_id, a_uint32_t phy_id, - a_uint32_t *phy_data) -{ - return qca808x_phy_get_phy_id (dev_id, phy_id, phy_data); -} - -/****************************************************************************** -* -* mpge_phy_off - power off the phy -* -*/ -static sw_error_t -mpge_phy_poweroff(a_uint32_t dev_id, a_uint32_t phy_id) -{ - return qca808x_phy_poweroff (dev_id, phy_id); -} - -/****************************************************************************** -* -* mpge_phy_on - power on the phy -* -*/ -static sw_error_t -mpge_phy_poweron(a_uint32_t dev_id, a_uint32_t phy_id) -{ - return qca808x_phy_poweron (dev_id, phy_id); -} - -#ifndef IN_PORTCONTROL_MINI -/****************************************************************************** -* -* mpge_phy_set_hibernate - set hibernate status -* -*/ -static sw_error_t -mpge_phy_set_hibernate(a_uint32_t dev_id, a_uint32_t phy_id, a_bool_t enable) -{ - return qca808x_phy_set_hibernate (dev_id, phy_id, enable); -} - -/****************************************************************************** -* -* mpge_phy_get_hibernate - get hibernate status -* -*/ -static sw_error_t -mpge_phy_get_hibernate(a_uint32_t dev_id, a_uint32_t phy_id, - a_bool_t * enable) -{ - return qca808x_phy_get_hibernate (dev_id, phy_id, enable); -} - -/****************************************************************************** -* -* mpge_phy_cdt - cable diagnostic test -* -*/ -static sw_error_t -mpge_phy_cdt(a_uint32_t dev_id, a_uint32_t phy_id, a_uint32_t mdi_pair, - fal_cable_status_t * cable_status, a_uint32_t * cable_len) -{ - return qca808x_phy_cdt (dev_id, phy_id, mdi_pair, - cable_status, cable_len); -} - -/****************************************************************************** -* -* mpge_phy_set_mdix - set phy mdix configuration -* -*/ -static sw_error_t -mpge_phy_set_mdix(a_uint32_t dev_id, a_uint32_t phy_id, - fal_port_mdix_mode_t mode) -{ - return qca808x_phy_set_mdix(dev_id, phy_id, mode); -} - -/****************************************************************************** -* -* mpge_phy_get_mdix - get phy mdix configuration -* -*/ -static sw_error_t -mpge_phy_get_mdix(a_uint32_t dev_id, a_uint32_t phy_id, - fal_port_mdix_mode_t * mode) -{ - return qca808x_phy_get_mdix(dev_id, phy_id, mode); -} - -/****************************************************************************** -* -* mpge_phy_get_mdix_status - get phy mdix status -* -*/ -static sw_error_t -mpge_phy_get_mdix_status(a_uint32_t dev_id, a_uint32_t phy_id, - fal_port_mdix_status_t * mode) -{ - return qca808x_phy_get_mdix_status(dev_id, phy_id, mode); -} - -/****************************************************************************** -* -* mpge_phy_set_local_loopback -* -*/ -static sw_error_t -mpge_phy_set_local_loopback(a_uint32_t dev_id, a_uint32_t phy_id, - a_bool_t enable) -{ - a_uint16_t phy_data; - fal_port_speed_t old_speed; - sw_error_t rv = SW_OK; - - if (enable == A_TRUE) - { - mpge_phy_get_speed(dev_id, phy_id, &old_speed); - if (old_speed == FAL_SPEED_1000) - { - phy_data = MPGE_1000M_LOOPBACK; - } - else if (old_speed == FAL_SPEED_100) - { - phy_data = MPGE_100M_LOOPBACK; - } - else if (old_speed == FAL_SPEED_10) - { - phy_data = MPGE_10M_LOOPBACK; - } - else - { - return SW_FAIL; - } - } - else - { - phy_data = MPGE_COMMON_CTRL; - } - - rv = mpge_phy_reg_write(dev_id, phy_id, MPGE_PHY_CONTROL, phy_data); - - return rv; -} - -/****************************************************************************** -* -* mpge_phy_get_local_loopback -* -*/ -static sw_error_t -mpge_phy_get_local_loopback(a_uint32_t dev_id, a_uint32_t phy_id, - a_bool_t * enable) -{ - return qca808x_phy_get_local_loopback (dev_id, phy_id, enable); -} - -/****************************************************************************** -* -* mpge_phy_set_remote_loopback -* -*/ -static sw_error_t -mpge_phy_set_remote_loopback(a_uint32_t dev_id, a_uint32_t phy_id, - a_bool_t enable) -{ - return qca808x_phy_set_remote_loopback (dev_id, phy_id, enable); -} - -/****************************************************************************** -* -* mpge_phy_get_remote_loopback -* -*/ -static sw_error_t -mpge_phy_get_remote_loopback(a_uint32_t dev_id, a_uint32_t phy_id, - a_bool_t * enable) -{ - return qca808x_phy_get_remote_loopback (dev_id, phy_id, enable); - -} - -/****************************************************************************** -* -* mpge_phy_set_802.3az -* -*/ -static sw_error_t -mpge_phy_set_8023az(a_uint32_t dev_id, a_uint32_t phy_id, a_bool_t enable) -{ - return qca808x_phy_set_8023az (dev_id, phy_id, enable); -} - -/****************************************************************************** -* -* mpge_phy_get_8023az status -* -*/ -static sw_error_t -mpge_phy_get_8023az(a_uint32_t dev_id, a_uint32_t phy_id, a_bool_t * enable) -{ - return qca808x_phy_get_8023az (dev_id, phy_id, enable); -} - -/****************************************************************************** -* -* mpge_phy_set wol-frame mac address -* -*/ -static sw_error_t -mpge_phy_set_magic_frame_mac(a_uint32_t dev_id, a_uint32_t phy_id, - fal_mac_addr_t * mac) -{ - return qca808x_phy_set_magic_frame_mac (dev_id, phy_id, mac); -} - -/****************************************************************************** -* -* mpge_phy_get wol - frame mac address -* -*/ -static sw_error_t -mpge_phy_get_magic_frame_mac(a_uint32_t dev_id, a_uint32_t phy_id, - fal_mac_addr_t * mac) -{ - return qca808x_phy_get_magic_frame_mac (dev_id, phy_id, mac); -} - -/****************************************************************************** -* -* mpge_phy_set wol - enable or disable -* -*/ -static sw_error_t -mpge_phy_set_wol_status(a_uint32_t dev_id, a_uint32_t phy_id, a_bool_t enable) -{ - return qca808x_phy_set_wol_status (dev_id, phy_id, enable); -} - -/****************************************************************************** -* -* mpge_phy_get_wol status - get wol status -* -*/ -static sw_error_t -mpge_phy_get_wol_status(a_uint32_t dev_id, a_uint32_t phy_id, a_bool_t * enable) -{ - return qca808x_phy_get_wol_status (dev_id, phy_id, enable); -} - -/****************************************************************************** -* -* mpge_phy_set_counter - set counter status -* -*/ -static sw_error_t -mpge_phy_set_counter(a_uint32_t dev_id, a_uint32_t phy_id, a_bool_t enable) -{ - return qca808x_phy_set_counter (dev_id, phy_id, enable); -} - -/****************************************************************************** -* -* mpge_phy_get_counter_status - get counter status -* -*/ -static sw_error_t -mpge_phy_get_counter(a_uint32_t dev_id, a_uint32_t phy_id, - a_bool_t * enable) -{ - return qca808x_phy_get_counter (dev_id, phy_id, enable); -} - -/****************************************************************************** -* -* mpge_phy_show show - counter statistics -* -*/ -static sw_error_t -mpge_phy_show_counter(a_uint32_t dev_id, a_uint32_t phy_id, - fal_port_counter_info_t * counter_infor) -{ - return qca808x_phy_show_counter (dev_id, phy_id, counter_infor); -} - -/****************************************************************************** -* -* mpge_phy_set_intr_mask - Set interrupt mask with the -* specified device. -*/ -sw_error_t -mpge_phy_set_intr_mask(a_uint32_t dev_id, a_uint32_t phy_id, - a_uint32_t intr_mask_flag) -{ - a_uint16_t phy_data = 0; - sw_error_t rv = SW_OK; - - phy_data = mpge_phy_reg_read(dev_id, phy_id, MPGE_PHY_INTR_MASK); - PHY_RTN_ON_READ_ERROR(phy_data); - - if (intr_mask_flag & FAL_PHY_INTR_STATUS_UP_CHANGE) { - phy_data |= MPGE_INTR_STATUS_LINK_UP; - } else { - phy_data &= (~MPGE_INTR_STATUS_LINK_UP); - } - - if (intr_mask_flag & FAL_PHY_INTR_STATUS_DOWN_CHANGE) { - phy_data |= MPGE_INTR_STATUS_LINK_DOWN; - } else { - phy_data &= (~MPGE_INTR_STATUS_LINK_DOWN); - } - - if (intr_mask_flag & FAL_PHY_INTR_SPEED_CHANGE) { - phy_data |= MPGE_INTR_SPEED_CHANGE; - } else { - phy_data &= (~MPGE_INTR_SPEED_CHANGE); - } - - if (intr_mask_flag & FAL_PHY_INTR_DUPLEX_CHANGE) { - phy_data |= MPGE_INTR_DUPLEX_CHANGE; - } else { - phy_data &= (~MPGE_INTR_DUPLEX_CHANGE); - } - - if (intr_mask_flag & FAL_PHY_INTR_WOL_STATUS) { - phy_data |= MPGE_INTR_WOL; - } else { - phy_data &= (~MPGE_INTR_WOL); - } - - rv = mpge_phy_reg_write(dev_id, phy_id, MPGE_PHY_INTR_MASK, phy_data); - - return rv; -} - -/****************************************************************************** -* -* mpge_phy_get_intr_mask - Get interrupt mask with the -* specified device. -*/ -sw_error_t -mpge_phy_get_intr_mask(a_uint32_t dev_id, a_uint32_t phy_id, - a_uint32_t * intr_mask_flag) -{ - a_uint16_t phy_data = 0; - - phy_data = mpge_phy_reg_read(dev_id, phy_id, MPGE_PHY_INTR_MASK); - PHY_RTN_ON_READ_ERROR(phy_data); - - *intr_mask_flag = 0; - if (phy_data & MPGE_INTR_STATUS_LINK_UP) { - *intr_mask_flag |= FAL_PHY_INTR_STATUS_UP_CHANGE; - } - - if (phy_data & MPGE_INTR_STATUS_LINK_DOWN) { - *intr_mask_flag |= FAL_PHY_INTR_STATUS_DOWN_CHANGE; - } - - if (phy_data & MPGE_INTR_SPEED_CHANGE) { - *intr_mask_flag |= FAL_PHY_INTR_SPEED_CHANGE; - } - - if (phy_data & MPGE_INTR_DUPLEX_CHANGE) { - *intr_mask_flag |= FAL_PHY_INTR_DUPLEX_CHANGE; - } - - if (phy_data & MPGE_INTR_WOL) { - *intr_mask_flag |= FAL_PHY_INTR_WOL_STATUS; - } - - return SW_OK; -} - -/****************************************************************************** -* -* mpge_phy_get_intr_status - Get interrupt status with the -* specified device. -*/ -sw_error_t -mpge_phy_get_intr_status(a_uint32_t dev_id, a_uint32_t phy_id, - a_uint32_t * intr_status_flag) -{ - a_uint16_t phy_data = 0; - - phy_data = mpge_phy_reg_read(dev_id, phy_id, MPGE_PHY_INTR_STATUS); - PHY_RTN_ON_READ_ERROR(phy_data); - - *intr_status_flag = 0; - if (phy_data & MPGE_INTR_STATUS_LINK_UP) { - *intr_status_flag |= FAL_PHY_INTR_STATUS_UP_CHANGE; - } - - if (phy_data & MPGE_INTR_STATUS_LINK_DOWN) { - *intr_status_flag |= FAL_PHY_INTR_STATUS_DOWN_CHANGE; - } - - if (phy_data & MPGE_INTR_SPEED_CHANGE) { - *intr_status_flag |= FAL_PHY_INTR_SPEED_CHANGE; - } - - if (phy_data & MPGE_INTR_DUPLEX_CHANGE) { - *intr_status_flag |= FAL_PHY_INTR_DUPLEX_CHANGE; - } - - if (phy_data & MPGE_INTR_WOL) { - *intr_status_flag |= FAL_PHY_INTR_WOL_STATUS; - } - - return SW_OK; -} -#endif - -/****************************************************************************** -* -* mpge_phy_set_eee_advertisement -* -*/ -static sw_error_t -mpge_phy_set_eee_adv(a_uint32_t dev_id, a_uint32_t phy_id, - a_uint32_t adv) -{ - return qca808x_phy_set_eee_adv (dev_id, phy_id, adv); -} - -/****************************************************************************** -* -* mpge_phy_get_eee_advertisement -* -*/ -static sw_error_t -mpge_phy_get_eee_adv(a_uint32_t dev_id, a_uint32_t phy_id, - a_uint32_t *adv) -{ - return qca808x_phy_get_eee_adv (dev_id, phy_id, adv); -} - -/****************************************************************************** -* -* mpge_phy_get_eee_partner_advertisement -* -*/ -static sw_error_t -mpge_phy_get_eee_partner_adv(a_uint32_t dev_id, a_uint32_t phy_id, - a_uint32_t *adv) -{ - return qca808x_phy_get_eee_partner_adv (dev_id, phy_id, adv); -} - -/****************************************************************************** -* -* mpge_phy_get_eee_capability -* -*/ -static sw_error_t -mpge_phy_get_eee_cap(a_uint32_t dev_id, a_uint32_t phy_id, - a_uint32_t *cap) -{ - return qca808x_phy_get_eee_cap (dev_id, phy_id, cap); -} - -/****************************************************************************** -* -* mpge_phy_get_eee_status - get eee status -* -*/ -static sw_error_t -mpge_phy_get_eee_status(a_uint32_t dev_id, a_uint32_t phy_id, - a_uint32_t *status) -{ - return qca808x_phy_get_eee_status (dev_id, phy_id, status); -} -/****************************************************************************** -* -* mpge_phy_cdt_thresh_set - set CDT threshold -* -* set CDT threshold -*/ -static sw_error_t -mpge_phy_cdt_thresh_init(a_uint32_t dev_id, a_uint32_t phy_id) -{ - sw_error_t rv = SW_OK; - - rv = mpge_phy_mmd_write(dev_id, phy_id, MPGE_PHY_MMD3_NUM, - MPGE_PHY_MMD3_CDT_THRESH_CTRL3, - MPGE_PHY_MMD3_CDT_THRESH_CTRL3_VAL); - SW_RTN_ON_ERROR(rv); - rv = mpge_phy_mmd_write(dev_id, phy_id, MPGE_PHY_MMD3_NUM, - MPGE_PHY_MMD3_CDT_THRESH_CTRL4, - MPGE_PHY_MMD3_CDT_THRESH_CTRL4_VAL); - SW_RTN_ON_ERROR(rv); - rv = mpge_phy_mmd_write(dev_id, phy_id, MPGE_PHY_MMD3_NUM, - MPGE_PHY_MMD3_CDT_THRESH_CTRL5, - MPGE_PHY_MMD3_CDT_THRESH_CTRL5_VAL); - SW_RTN_ON_ERROR(rv); - rv = mpge_phy_mmd_write(dev_id, phy_id, MPGE_PHY_MMD3_NUM, - MPGE_PHY_MMD3_CDT_THRESH_CTRL6, - MPGE_PHY_MMD3_CDT_THRESH_CTRL6_VAL); - SW_RTN_ON_ERROR(rv); - rv = mpge_phy_mmd_write(dev_id, phy_id, MPGE_PHY_MMD3_NUM, - MPGE_PHY_MMD3_CDT_THRESH_CTRL7, - MPGE_PHY_MMD3_CDT_THRESH_CTRL7_VAL); - SW_RTN_ON_ERROR(rv); - rv = mpge_phy_mmd_write(dev_id, phy_id, MPGE_PHY_MMD3_NUM, - MPGE_PHY_MMD3_CDT_THRESH_CTRL9, - MPGE_PHY_MMD3_CDT_THRESH_CTRL9_VAL); - SW_RTN_ON_ERROR(rv); - rv = mpge_phy_mmd_write(dev_id, phy_id, MPGE_PHY_MMD3_NUM, - MPGE_PHY_MMD3_CDT_THRESH_CTRL13, - MPGE_PHY_MMD3_CDT_THRESH_CTRL13_VAL); - SW_RTN_ON_ERROR(rv); - rv = mpge_phy_mmd_write(dev_id, phy_id, MPGE_PHY_MMD3_NUM, - MPGE_PHY_MMD3_CDT_THRESH_CTRL14, - MPGE_PHY_MMD3_NEAR_ECHO_THRESH_VAL); - - return rv; -} - -/****************************************************************************** -* -* mpge_phy_function_reset - do function reset -* -*/ -static sw_error_t -mpge_phy_function_reset(a_uint32_t dev_id, a_uint32_t phy_id, - hsl_phy_function_reset_t phy_reset_type) -{ - a_uint16_t phy_data = 0; - sw_error_t rv = SW_OK; - - switch (phy_reset_type) - { - case PHY_FIFO_RESET: - phy_data = mpge_phy_reg_read (dev_id, phy_id, MPGE_PHY_FIFO_CONTROL); - PHY_RTN_ON_READ_ERROR(phy_data); - - rv = mpge_phy_reg_write(dev_id, phy_id, MPGE_PHY_FIFO_CONTROL, - phy_data & (~MPGE_PHY_FIFO_RESET)); - SW_RTN_ON_ERROR(rv); - - aos_mdelay(50); - - rv = mpge_phy_reg_write(dev_id, phy_id, MPGE_PHY_FIFO_CONTROL, - phy_data | MPGE_PHY_FIFO_RESET); - SW_RTN_ON_ERROR(rv); - break; - default: - return SW_NOT_SUPPORTED; - } - - return rv; -} - -static void -mpge_phy_lock_init(void) -{ - return qca808x_phy_lock_init(); -} - -static sw_error_t -mpge_phy_dac_set(a_uint32_t dev_id, a_uint32_t phy_id, phy_dac_t phy_dac) -{ - a_uint16_t phy_data = 0; - sw_error_t rv = SW_OK; - - if(phy_dac.mdac != PHY_INVALID_DAC) - { - SSDK_INFO("phy mdac is set as 0x%x\n", phy_dac.mdac); - /*set mdac value*/ - phy_data = mpge_phy_mmd_read(dev_id, phy_id, MPGE_PHY_MMD1_NUM, - MPGE_PHY_MMD1_DAC); - PHY_RTN_ON_READ_ERROR(phy_data); - phy_data &= ~(BITS(8,8)); - rv = mpge_phy_mmd_write(dev_id, phy_id, MPGE_PHY_MMD1_NUM, - MPGE_PHY_MMD1_DAC, phy_data | PHY_DAC(phy_dac.mdac)); - SW_RTN_ON_ERROR(rv); - } - if(phy_dac.edac != PHY_INVALID_DAC) - { - SSDK_INFO("phy edac is set as 0x%x\n", phy_dac.edac); - /*set edac value*/ - phy_data = mpge_phy_debug_read(dev_id, phy_id, MPGE_PHY_DEBUG_EDAC); - PHY_RTN_ON_READ_ERROR(phy_data); - phy_data &= ~(BITS(8,8)); - rv = mpge_phy_debug_write(dev_id, phy_id, MPGE_PHY_DEBUG_EDAC, - phy_data | PHY_DAC(phy_dac.edac)); - SW_RTN_ON_ERROR(rv); - } - - return rv; -} - -static void -mpge_phy_dac_init(a_uint32_t dev_id, a_uint32_t phy_id, - a_uint32_t port_id) -{ - phy_dac_t phy_dac; - - hsl_port_phy_dac_get(dev_id, port_id, &phy_dac); - mpge_phy_dac_set(dev_id, phy_id, phy_dac); - - return; -} - -static sw_error_t -mpge_phy_ldo_efuse_set(a_uint32_t dev_id, a_uint32_t phy_id, a_uint32_t efuse_value) -{ - a_uint16_t phy_data = 0, phy_data1 = 0; - sw_error_t rv = SW_OK; - - /*when set the register of MPGE_PHY_DEBUG_ANA_LDO_EFUSE, the register of - MPGE_PHY_DEBUG_ANA_DAC_FILTER will be changed automatically, so need to - save it and restore it*/ - phy_data1 = mpge_phy_debug_read(dev_id, phy_id, MPGE_PHY_DEBUG_ANA_DAC_FILTER); - PHY_RTN_ON_READ_ERROR(phy_data1); - - phy_data = mpge_phy_debug_read(dev_id, phy_id, MPGE_PHY_DEBUG_ANA_LDO_EFUSE); - PHY_RTN_ON_READ_ERROR(phy_data); - phy_data &= ~(BITS(4,4)); - rv = mpge_phy_debug_write(dev_id, phy_id, MPGE_PHY_DEBUG_ANA_LDO_EFUSE, - phy_data | efuse_value); - SW_RTN_ON_ERROR(rv); - rv = mpge_phy_debug_write(dev_id, phy_id, MPGE_PHY_DEBUG_ANA_DAC_FILTER, - phy_data1); - - return rv; -} - -static sw_error_t -mpge_phy_hw_init(a_uint32_t dev_id, a_uint32_t port_bmp) -{ - a_uint32_t port_id = 0, phy_addr = 0; - sw_error_t rv = SW_OK; - - for (port_id = SSDK_PHYSICAL_PORT0; port_id < SW_MAX_NR_PORT; port_id ++) - { - if (port_bmp & (0x1 << port_id)) - { - phy_addr = qca_ssdk_port_to_phy_addr(dev_id, port_id); - SW_RTN_ON_ERROR(rv); - /*configure the CDT threshold*/ - rv = mpge_phy_cdt_thresh_init (dev_id, phy_addr); - SW_RTN_ON_ERROR(rv); - /*set LDO efuse as default and make ICC efuse take effect only*/ - rv = mpge_phy_ldo_efuse_set(dev_id, phy_addr, - MPGE_PHY_DEBUG_ANA_LDO_EFUSE_DEFAULT); - /*special configuration for AZ*/ - rv = mpge_phy_mmd_write(dev_id, phy_addr, MPGE_PHY_MMD3_NUM, - MPGE_PHY_MMD3_AZ_CTRL1, MPGE_PHY_MMD3_AZ_CTRL1_VAL); - SW_RTN_ON_ERROR(rv); - rv = mpge_phy_mmd_write(dev_id, phy_addr, MPGE_PHY_MMD3_NUM, - MPGE_PHY_MMD3_AZ_CTRL2, MPGE_PHY_MMD3_AZ_CTRL2_VAL); - SW_RTN_ON_ERROR(rv); - /*configure MSE threshold and over threshold times*/ - rv = mpge_phy_mmd_write(dev_id, phy_addr, MPGE_PHY_MMD1_NUM, - MPGE_PHY_MMD1_MSE_THRESH1, MPGE_PHY_MMD1_MSE_THRESH1_VAL); - SW_RTN_ON_ERROR(rv); - rv = mpge_phy_mmd_write(dev_id, phy_addr, MPGE_PHY_MMD1_NUM, - MPGE_PHY_MMD1_MSE_THRESH2, MPGE_PHY_MMD1_MSE_THRESH2_VAL); - SW_RTN_ON_ERROR(rv); - mpge_phy_dac_init(dev_id, phy_addr, port_id); - } - } - - return rv; -} - -static sw_error_t mpge_phy_api_ops_init(void) -{ - sw_error_t ret = SW_OK; - hsl_phy_ops_t *mpge_phy_api_ops = NULL; - - mpge_phy_api_ops = kzalloc(sizeof(hsl_phy_ops_t), GFP_KERNEL); - if (mpge_phy_api_ops == NULL) - { - SSDK_ERROR("mpge phy ops kzalloc failed!\n"); - return -ENOMEM; - } - - phy_api_ops_init(MPGE_PHY_CHIP); - - mpge_phy_api_ops->phy_reg_write = mpge_phy_reg_write; - mpge_phy_api_ops->phy_reg_read = mpge_phy_reg_read; - mpge_phy_api_ops->phy_debug_write = mpge_phy_debug_write; - mpge_phy_api_ops->phy_debug_read = mpge_phy_debug_read; - mpge_phy_api_ops->phy_mmd_write = mpge_phy_mmd_write; - mpge_phy_api_ops->phy_mmd_read = mpge_phy_mmd_read; - mpge_phy_api_ops->phy_get_status = mpge_phy_get_status; - mpge_phy_api_ops->phy_speed_get = mpge_phy_get_speed; - mpge_phy_api_ops->phy_speed_set = mpge_phy_set_speed; - mpge_phy_api_ops->phy_duplex_get = mpge_phy_get_duplex; - mpge_phy_api_ops->phy_duplex_set = mpge_phy_set_duplex; - mpge_phy_api_ops->phy_autoneg_enable_set = mpge_phy_enable_autoneg; - mpge_phy_api_ops->phy_restart_autoneg = mpge_phy_restart_autoneg; - mpge_phy_api_ops->phy_autoneg_status_get = mpge_phy_autoneg_status; - mpge_phy_api_ops->phy_autoneg_adv_set = mpge_phy_set_autoneg_adv; - mpge_phy_api_ops->phy_autoneg_adv_get = mpge_phy_get_autoneg_adv; - mpge_phy_api_ops->phy_link_status_get = mpge_phy_get_link_status; - mpge_phy_api_ops->phy_reset = mpge_phy_reset; - mpge_phy_api_ops->phy_id_get = mpge_phy_get_phy_id; - mpge_phy_api_ops->phy_power_off = mpge_phy_poweroff; - mpge_phy_api_ops->phy_power_on = mpge_phy_poweron; -#ifndef IN_PORTCONTROL_MINI - mpge_phy_api_ops->phy_cdt = mpge_phy_cdt; - mpge_phy_api_ops->phy_mdix_set = mpge_phy_set_mdix; - mpge_phy_api_ops->phy_mdix_get = mpge_phy_get_mdix; - mpge_phy_api_ops->phy_mdix_status_get = mpge_phy_get_mdix_status; - mpge_phy_api_ops->phy_local_loopback_set = mpge_phy_set_local_loopback; - mpge_phy_api_ops->phy_local_loopback_get = mpge_phy_get_local_loopback; - mpge_phy_api_ops->phy_remote_loopback_set = mpge_phy_set_remote_loopback; - mpge_phy_api_ops->phy_remote_loopback_get = mpge_phy_get_remote_loopback; - mpge_phy_api_ops->phy_8023az_set = mpge_phy_set_8023az; - mpge_phy_api_ops->phy_8023az_get = mpge_phy_get_8023az; - mpge_phy_api_ops->phy_hibernation_set = mpge_phy_set_hibernate; - mpge_phy_api_ops->phy_hibernation_get = mpge_phy_get_hibernate; - mpge_phy_api_ops->phy_magic_frame_mac_set = mpge_phy_set_magic_frame_mac; - mpge_phy_api_ops->phy_magic_frame_mac_get = mpge_phy_get_magic_frame_mac; - mpge_phy_api_ops->phy_counter_set = mpge_phy_set_counter; - mpge_phy_api_ops->phy_counter_get = mpge_phy_get_counter; - mpge_phy_api_ops->phy_counter_show = mpge_phy_show_counter; - mpge_phy_api_ops->phy_wol_status_set = mpge_phy_set_wol_status; - mpge_phy_api_ops->phy_wol_status_get = mpge_phy_get_wol_status; - mpge_phy_api_ops->phy_intr_mask_set = mpge_phy_set_intr_mask; - mpge_phy_api_ops->phy_intr_mask_get = mpge_phy_get_intr_mask; - mpge_phy_api_ops->phy_intr_status_get = mpge_phy_get_intr_status; -#endif - mpge_phy_api_ops->phy_eee_adv_set = mpge_phy_set_eee_adv; - mpge_phy_api_ops->phy_eee_adv_get = mpge_phy_get_eee_adv; - mpge_phy_api_ops->phy_eee_partner_adv_get = mpge_phy_get_eee_partner_adv; - mpge_phy_api_ops->phy_eee_cap_get = mpge_phy_get_eee_cap; - mpge_phy_api_ops->phy_eee_status_get = mpge_phy_get_eee_status; - mpge_phy_api_ops->phy_function_reset = mpge_phy_function_reset; -#ifdef IN_LED - mpge_phy_led_api_ops_init(mpge_phy_api_ops); -#endif - ret = hsl_phy_api_ops_register(MPGE_PHY_CHIP, mpge_phy_api_ops); - - if (ret == SW_OK) - { - SSDK_INFO("qca probe mpge phy driver succeeded!\n"); - } - else - { - SSDK_ERROR("qca probe mpge phy driver failed! (code: %d)\n", ret); - } - - return ret; -} - -/****************************************************************************** -* -* mpge_phy_init - -* -*/ -int mpge_phy_init(a_uint32_t dev_id, a_uint32_t port_bmp) -{ - a_int32_t ret = 0; - static a_bool_t phy_ops_flag = A_FALSE; - - if(phy_ops_flag == A_FALSE && - mpge_phy_api_ops_init() == SW_OK) { - mpge_phy_lock_init(); - phy_ops_flag = A_TRUE; - } - mpge_phy_hw_init(dev_id, port_bmp); - - return ret; -} diff --git a/feeds/ipq807x/qca-ssdk/src/src/hsl/phy/qca803x_phy.c b/feeds/ipq807x/qca-ssdk/src/src/hsl/phy/qca803x_phy.c deleted file mode 100644 index e9ca3bc79..000000000 --- a/feeds/ipq807x/qca-ssdk/src/src/hsl/phy/qca803x_phy.c +++ /dev/null @@ -1,2341 +0,0 @@ -/* - * Copyright (c) 2017, 2019, The Linux Foundation. All rights reserved. - * Permission to use, copy, modify, and/or distribute this software for - * any purpose with or without fee is hereby granted, provided that the - * above copyright notice and this permission notice appear in all copies. - * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES - * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR - * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES - * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN - * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT - * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. - */ -#include "sw.h" -#include "fal_port_ctrl.h" -#include "hsl_api.h" -#include "hsl.h" -#include "qca803x_phy.h" -#include "hsl_phy.h" -#include "ssdk_plat.h" - -#define QCA803X_PHY_DELAYED_INIT_TICKS msecs_to_jiffies(1000) - -typedef struct { - a_uint32_t dev_id; - a_uint32_t combo_phy_bmp; - qca803x_phy_medium_t combo_cfg[SW_MAX_NR_PORT]; - struct delayed_work phy_sync_dwork; -} qca803x_priv_t; - -static qca803x_priv_t g_qca803x_phy; -static struct mutex qca803x_reg_lock; - -#define QCA803X_LOCKER_INIT mutex_init(&qca803x_reg_lock) -#define QCA803X_REG_LOCK mutex_lock(&qca803x_reg_lock) -#define QCA803X_REG_UNLOCK mutex_unlock(&qca803x_reg_lock) - - -/****************************************************************************** -* -* qca803x_phy_mii_read - mii register read -* -* mii register read -*/ -a_uint16_t -qca803x_phy_reg_read(a_uint32_t dev_id, a_uint32_t phy_id, a_uint32_t reg_id) -{ - sw_error_t rv = SW_OK; - a_uint16_t phy_data = 0; - - HSL_PHY_GET(rv, dev_id, phy_id, reg_id, &phy_data); - if (SW_OK != rv) { - return 0xffff; - } - - return phy_data; -} - -/****************************************************************************** -* -* qca803x_phy_mii_write - mii register write -* -* mii register write -*/ -sw_error_t -qca803x_phy_reg_write(a_uint32_t dev_id, a_uint32_t phy_id, a_uint32_t reg_id, - a_uint16_t reg_val) -{ - sw_error_t rv; - - HSL_PHY_SET(rv, dev_id, phy_id, reg_id, reg_val); - - return rv; - -} - -/****************************************************************************** -* -* qca803x_phy_debug_write - debug port write -* -* debug port write -*/ -sw_error_t -qca803x_phy_debug_write(a_uint32_t dev_id, a_uint32_t phy_id, a_uint16_t reg_id, - a_uint16_t reg_val) -{ - qca803x_phy_reg_write(dev_id, phy_id, QCA803X_DEBUG_PORT_ADDRESS, reg_id); - qca803x_phy_reg_write(dev_id, phy_id, QCA803X_DEBUG_PORT_DATA, reg_val); - - return SW_OK; -} - -/****************************************************************************** -* -* qca803x_phy_debug_read - debug port read -* -* debug port read -*/ -a_uint16_t -qca803x_phy_debug_read(a_uint32_t dev_id, a_uint32_t phy_id, a_uint16_t reg_id) -{ - qca803x_phy_reg_write(dev_id, phy_id, QCA803X_DEBUG_PORT_ADDRESS, reg_id); - return qca803x_phy_reg_read(dev_id, phy_id, QCA803X_DEBUG_PORT_DATA); -} - -/****************************************************************************** -* -* qca803x_phy_mmd_write - PHY MMD register write -* -* PHY MMD register write -*/ -sw_error_t -qca803x_phy_mmd_write(a_uint32_t dev_id, a_uint32_t phy_id, - a_uint16_t mmd_num, a_uint16_t reg_id, a_uint16_t reg_val) -{ - qca803x_phy_reg_write(dev_id, phy_id, QCA803X_MMD_CTRL_REG, mmd_num); - qca803x_phy_reg_write(dev_id, phy_id, QCA803X_MMD_DATA_REG, reg_id); - qca803x_phy_reg_write(dev_id, phy_id, QCA803X_MMD_CTRL_REG, - 0x4000 | mmd_num); - qca803x_phy_reg_write(dev_id, phy_id, QCA803X_MMD_DATA_REG, reg_val); - - return SW_OK; -} - -/****************************************************************************** -* -* qca803x_phy_mmd_read - PHY MMD register read -* -* PHY MMD register read -*/ -a_uint16_t -qca803x_phy_mmd_read(a_uint32_t dev_id, a_uint32_t phy_id, - a_uint16_t mmd_num, a_uint16_t reg_id) -{ - qca803x_phy_reg_write(dev_id, phy_id, QCA803X_MMD_CTRL_REG, mmd_num); - qca803x_phy_reg_write(dev_id, phy_id, QCA803X_MMD_DATA_REG, reg_id); - qca803x_phy_reg_write(dev_id, phy_id, QCA803X_MMD_CTRL_REG, - 0x4000 | mmd_num); - - return qca803x_phy_reg_read(dev_id, phy_id, QCA803X_MMD_DATA_REG); -} - -/****************************************************************************** -* -* qca803x_phy_get_speed - Determines the speed of phy ports associated with the -* specified device. -*/ - -sw_error_t -qca803x_phy_get_speed(a_uint32_t dev_id, a_uint32_t phy_id, - fal_port_speed_t * speed) -{ - a_uint16_t phy_data; - sw_error_t rv = SW_OK; - - phy_data = qca803x_phy_reg_read(dev_id, phy_id, QCA803X_PHY_SPEC_STATUS); - PHY_RTN_ON_READ_ERROR(phy_data); - - switch (phy_data & QCA803X_STATUS_SPEED_MASK) - { - case QCA803X_STATUS_SPEED_1000MBS: - *speed = FAL_SPEED_1000; - break; - case QCA803X_STATUS_SPEED_100MBS: - *speed = FAL_SPEED_100; - break; - case QCA803X_STATUS_SPEED_10MBS: - *speed = FAL_SPEED_10; - break; - default: - return SW_READ_ERROR; - } - - return rv; -} - -/****************************************************************************** -* -* qca803x_phy_set_speed - Determines the speed of phy ports associated with the -* specified device. -*/ -sw_error_t -qca803x_phy_set_speed(a_uint32_t dev_id, a_uint32_t phy_id, - fal_port_speed_t speed) -{ - a_uint16_t phy_data = 0; - fal_port_duplex_t old_duplex; - sw_error_t rv = SW_OK; - - phy_data = qca803x_phy_reg_read(dev_id, phy_id, QCA803X_PHY_CONTROL); - PHY_RTN_ON_READ_ERROR(phy_data); - - rv = qca803x_phy_get_duplex(dev_id, phy_id, &old_duplex); - if(rv != SW_OK) { - return rv; - } - - if (old_duplex == FAL_FULL_DUPLEX) { - phy_data |= QCA803X_CTRL_FULL_DUPLEX; - switch(speed) - { - case FAL_SPEED_1000: - phy_data |= QCA803X_CTRL_SPEED_1000; - phy_data &= ~QCA803X_CTRL_SPEED_100; - phy_data |= QCA803X_CTRL_AUTONEGOTIATION_ENABLE; - break; - case FAL_SPEED_100: - case FAL_SPEED_10: - phy_data &= ~QCA803X_CTRL_SPEED_1000; - phy_data &= ~QCA803X_CTRL_AUTONEGOTIATION_ENABLE; - if (FAL_SPEED_100 == speed) { - phy_data |= QCA803X_CTRL_SPEED_100; - } else { - phy_data &= ~QCA803X_CTRL_SPEED_100; - } - break; - default: - return SW_BAD_PARAM; - } - } else if (old_duplex == FAL_HALF_DUPLEX) { - phy_data &= ~QCA803X_CTRL_FULL_DUPLEX; - switch(speed) - { - case FAL_SPEED_100: - case FAL_SPEED_10: - phy_data &= ~QCA803X_CTRL_SPEED_1000; - phy_data &= ~QCA803X_CTRL_AUTONEGOTIATION_ENABLE; - if (FAL_SPEED_100 == speed) { - phy_data |= QCA803X_CTRL_SPEED_100; - } else { - phy_data &= ~QCA803X_CTRL_SPEED_100; - } - break; - case FAL_SPEED_1000: - phy_data |= QCA803X_CTRL_FULL_DUPLEX; - phy_data |= QCA803X_CTRL_SPEED_1000; - phy_data &= ~QCA803X_CTRL_SPEED_100; - phy_data |= QCA803X_CTRL_AUTONEGOTIATION_ENABLE; - break; - default: - return SW_BAD_PARAM; - } - } else { - return SW_FAIL; - } - rv = qca803x_phy_reg_write(dev_id, phy_id, QCA803X_PHY_CONTROL, phy_data); - - return rv; -} - -/****************************************************************************** -* -* qca803x_phy_set_duplex - Determines the speed of phy ports associated with the -* specified device. -*/ -sw_error_t -qca803x_phy_set_duplex(a_uint32_t dev_id, a_uint32_t phy_id, - fal_port_duplex_t duplex) -{ - a_uint16_t phy_data = 0; - fal_port_speed_t old_speed; - sw_error_t rv = SW_OK; - - phy_data = qca803x_phy_reg_read(dev_id, phy_id, QCA803X_PHY_CONTROL); - PHY_RTN_ON_READ_ERROR(phy_data); - - qca803x_phy_get_speed(dev_id, phy_id, &old_speed); - switch(old_speed) - { - case FAL_SPEED_1000: - phy_data |= QCA803X_CTRL_SPEED_1000; - phy_data &= ~QCA803X_CTRL_SPEED_100; - phy_data |= QCA803X_CTRL_AUTONEGOTIATION_ENABLE; - if (duplex == FAL_FULL_DUPLEX) { - phy_data |= QCA803X_CTRL_FULL_DUPLEX; - } else { - return SW_NOT_SUPPORTED; - } - break; - case FAL_SPEED_100: - case FAL_SPEED_10: - if(old_speed == FAL_SPEED_100) { - phy_data |= QCA803X_CTRL_SPEED_100; - } else { - phy_data &= ~QCA803X_CTRL_SPEED_100; - } - phy_data &= ~QCA803X_CTRL_SPEED_1000; - phy_data &= ~QCA803X_CTRL_AUTONEGOTIATION_ENABLE; - if (duplex == FAL_FULL_DUPLEX) { - phy_data |= QCA803X_CTRL_FULL_DUPLEX; - } else { - phy_data &= ~QCA803X_CTRL_FULL_DUPLEX; - } - break; - default: - return SW_FAIL; - } - rv = qca803x_phy_reg_write(dev_id, phy_id, QCA803X_PHY_CONTROL, phy_data); - - return rv; -} - -/****************************************************************************** -* -* qca803x_phy_get_duplex - Determines the speed of phy ports associated with the -* specified device. -*/ -sw_error_t -qca803x_phy_get_duplex(a_uint32_t dev_id, a_uint32_t phy_id, - fal_port_duplex_t * duplex) -{ - a_uint16_t phy_data; - sw_error_t rv = SW_OK; - - phy_data = qca803x_phy_reg_read(dev_id, phy_id, QCA803X_PHY_SPEC_STATUS); - PHY_RTN_ON_READ_ERROR(phy_data); - - //read duplex - if (phy_data & QCA803X_STATUS_FULL_DUPLEX) - *duplex = FAL_FULL_DUPLEX; - else - *duplex = FAL_HALF_DUPLEX; - - return rv; -} - -/****************************************************************************** -* -* qca803x_phy_reset - reset the phy -* -* reset the phy -*/ -sw_error_t qca803x_phy_reset(a_uint32_t dev_id, a_uint32_t phy_id) -{ - a_uint16_t phy_data; - sw_error_t rv = SW_OK; - - phy_data = qca803x_phy_reg_read(dev_id, phy_id, QCA803X_PHY_CONTROL); - PHY_RTN_ON_READ_ERROR(phy_data); - - rv = qca803x_phy_reg_write(dev_id, phy_id, QCA803X_PHY_CONTROL, - phy_data | QCA803X_CTRL_SOFTWARE_RESET); - - return rv; -} -/****************************************************************************** -* -* qca803x_phy_status - test to see if the specified phy link is alive -* -* RETURNS: -* A_TRUE --> link is alive -* A_FALSE --> link is down -*/ -a_bool_t qca803x_phy_get_link_status(a_uint32_t dev_id, a_uint32_t phy_id) -{ - a_uint16_t phy_data; - a_bool_t rv = A_TRUE; - phy_data = qca803x_phy_reg_read(dev_id, phy_id, QCA803X_PHY_SPEC_STATUS); - - if (phy_data & QCA803X_STATUS_LINK_PASS) { - rv = A_TRUE; - } else { - rv = A_FALSE; - } - return rv; -} -#ifndef IN_PORTCONTROL_MINI -/****************************************************************************** -* -* qca803x_phy_cdt - cable diagnostic test -* -* cable diagnostic test -*/ - -static inline fal_cable_status_t _phy_cdt_status_mapping(a_uint16_t status) -{ - fal_cable_status_t status_mapping = FAL_CABLE_STATUS_INVALID; - - switch (status) { - case 3: - status_mapping = FAL_CABLE_STATUS_INVALID; - break; - case 2: - status_mapping = FAL_CABLE_STATUS_OPENED; - break; - case 1: - status_mapping = FAL_CABLE_STATUS_SHORT; - break; - case 0: - status_mapping = FAL_CABLE_STATUS_NORMAL; - break; - } - return status_mapping; -} - -static sw_error_t qca803x_phy_cdt_start(a_uint32_t dev_id, a_uint32_t phy_id, a_uint32_t mdi_pair) -{ - a_uint16_t status = 0; - a_uint16_t ii = 100; - a_uint16_t MDI_PAIR_S = (mdi_pair << 8) & CDT_PAIR_MASK; - - /* RUN CDT */ - qca803x_phy_reg_write(dev_id, phy_id, QCA803X_PHY_CDT_CONTROL, - QCA803X_RUN_CDT | MDI_PAIR_S); - do { - aos_mdelay(30); - status = qca803x_phy_reg_read(dev_id, phy_id, QCA803X_PHY_CDT_CONTROL); - } - while ((status & QCA803X_RUN_CDT) && (--ii)); - - return SW_OK; -} - -sw_error_t -qca803x_phy_cdt(a_uint32_t dev_id, a_uint32_t phy_id, a_uint32_t mdi_pair, - fal_cable_status_t * cable_status, a_uint32_t * cable_len) -{ - a_uint16_t status = 0; - - if (mdi_pair >= QCA803X_MDI_PAIR_NUM) { - //There are only 4 mdi pairs in 1000BASE-T - return SW_BAD_PARAM; - } - - qca803x_phy_cdt_start(dev_id, phy_id, mdi_pair); - - /* Get cable status */ - status = qca803x_phy_reg_read(dev_id, phy_id, QCA803X_PHY_CDT_STATUS); - *cable_status = _phy_cdt_status_mapping((status >> 8) & 0x3); - /* the actual cable length equals to CableDeltaTime * 0.824 */ - *cable_len = ((status & 0xff) * 824) / 1000; - - return SW_OK; -} - -/****************************************************************************** -* -* qca803x_phy_set_mdix - -* -* set phy mdix configuraiton -*/ -sw_error_t -qca803x_phy_set_mdix(a_uint32_t dev_id, a_uint32_t phy_id, - fal_port_mdix_mode_t mode) -{ - a_uint16_t phy_data; - - phy_data = qca803x_phy_reg_read(dev_id, phy_id, QCA803X_PHY_SPEC_CONTROL); - PHY_RTN_ON_READ_ERROR(phy_data); - - if (mode == PHY_MDIX_AUTO) { - phy_data |= QCA803X_PHY_MDIX_AUTO; - } else if (mode == PHY_MDIX_MDIX) { - phy_data &= ~QCA803X_PHY_MDIX_AUTO; - phy_data |= QCA803X_PHY_MDIX; - } else if (mode == PHY_MDIX_MDI) { - phy_data &= ~QCA803X_PHY_MDIX_AUTO; - } else { - return SW_BAD_PARAM; - } - - qca803x_phy_reg_write(dev_id, phy_id, QCA803X_PHY_SPEC_CONTROL, phy_data); - - qca803x_phy_reset(dev_id, phy_id); - return SW_OK; -} - -/****************************************************************************** -* -* qca803x_phy_get_mdix -* -* get phy mdix configuration -*/ -sw_error_t -qca803x_phy_get_mdix(a_uint32_t dev_id, a_uint32_t phy_id, - fal_port_mdix_mode_t * mode) -{ - a_uint16_t phy_data; - - phy_data = qca803x_phy_reg_read(dev_id, phy_id, QCA803X_PHY_SPEC_CONTROL); - PHY_RTN_ON_READ_ERROR(phy_data); - - if ((phy_data & QCA803X_PHY_MDIX_AUTO) == QCA803X_PHY_MDIX_AUTO) { - *mode = PHY_MDIX_AUTO; - } else if ((phy_data & QCA803X_PHY_MDIX) == QCA803X_PHY_MDIX) { - *mode = PHY_MDIX_MDIX; - } else { - *mode = PHY_MDIX_MDI; - } - - return SW_OK; - -} - -/****************************************************************************** -* -* qca803x_phy_get_mdix status -* -* get phy mdix status -*/ -sw_error_t -qca803x_phy_get_mdix_status(a_uint32_t dev_id, a_uint32_t phy_id, - fal_port_mdix_status_t * mode) -{ - a_uint16_t phy_data; - - phy_data = qca803x_phy_reg_read(dev_id, phy_id, QCA803X_PHY_SPEC_STATUS); - PHY_RTN_ON_READ_ERROR(phy_data); - - *mode = - (phy_data & QCA803X_PHY_MDIX_STATUS) ? PHY_MDIX_STATUS_MDIX : - PHY_MDIX_STATUS_MDI; - - return SW_OK; - -} - -/****************************************************************************** -* -* qca803x_phy_set_local_loopback -* -* set phy local loopback -*/ -sw_error_t -qca803x_phy_set_local_loopback(a_uint32_t dev_id, a_uint32_t phy_id, - a_bool_t enable) -{ - a_uint16_t phy_data; - fal_port_speed_t old_speed; - - if (enable == A_TRUE) { - qca803x_phy_get_speed(dev_id, phy_id, &old_speed); - if (old_speed == FAL_SPEED_1000) { - phy_data = QCA803X_1000M_LOOPBACK; - } else if (old_speed == FAL_SPEED_100) { - phy_data = QCA803X_100M_LOOPBACK; - } else if (old_speed == FAL_SPEED_10) { - phy_data = QCA803X_10M_LOOPBACK; - } else { - return SW_FAIL; - } - } else { - phy_data = QCA803X_COMMON_CTRL; - } - - qca803x_phy_reg_write(dev_id, phy_id, QCA803X_PHY_CONTROL, phy_data); - return SW_OK; - -} - -/****************************************************************************** -* -* qca803x_phy_get_local_loopback -* -* get phy local loopback -*/ -sw_error_t -qca803x_phy_get_local_loopback(a_uint32_t dev_id, a_uint32_t phy_id, - a_bool_t * enable) -{ - a_uint16_t phy_data; - - phy_data = qca803x_phy_reg_read(dev_id, phy_id, QCA803X_PHY_CONTROL); - PHY_RTN_ON_READ_ERROR(phy_data); - - if (phy_data & QCA803X_LOCAL_LOOPBACK_ENABLE) { - *enable = A_TRUE; - } else { - *enable = A_FALSE; - } - - return SW_OK; - -} - -/****************************************************************************** -* -* qca803x_phy_set_remote_loopback -* -* set phy remote loopback -*/ -sw_error_t -qca803x_phy_set_remote_loopback(a_uint32_t dev_id, a_uint32_t phy_id, - a_bool_t enable) -{ - a_uint16_t phy_data; - - phy_data = qca803x_phy_mmd_read(dev_id, phy_id, QCA803X_PHY_MMD3_NUM, - QCA803X_PHY_MMD3_ADDR_REMOTE_LOOPBACK_CTRL); - PHY_RTN_ON_READ_ERROR(phy_data); - - if (enable == A_TRUE) { - phy_data |= 0x0001; - } else { - phy_data &= ~0x0001; - } - - qca803x_phy_mmd_write(dev_id, phy_id, QCA803X_PHY_MMD3_NUM, - QCA803X_PHY_MMD3_ADDR_REMOTE_LOOPBACK_CTRL, - phy_data); - return SW_OK; - -} - -/****************************************************************************** -* -* qca803x_phy_get_remote_loopback -* -* get phy remote loopback -*/ -sw_error_t -qca803x_phy_get_remote_loopback(a_uint32_t dev_id, a_uint32_t phy_id, - a_bool_t * enable) -{ - a_uint16_t phy_data; - - phy_data = qca803x_phy_mmd_read(dev_id, phy_id, QCA803X_PHY_MMD3_NUM, - QCA803X_PHY_MMD3_ADDR_REMOTE_LOOPBACK_CTRL); - PHY_RTN_ON_READ_ERROR(phy_data); - - if (phy_data & 0x0001) { - *enable = A_TRUE; - } else { - *enable = A_FALSE; - } - - return SW_OK; - -} -#endif -/****************************************************************************** -* -* qca803x_set_autoneg_adv - set the phy autoneg Advertisement -* -*/ -sw_error_t -qca803x_phy_set_autoneg_adv(a_uint32_t dev_id, a_uint32_t phy_id, - a_uint32_t autoneg) -{ - a_uint16_t phy_data = 0; - - phy_data = qca803x_phy_reg_read(dev_id, phy_id, - QCA803X_AUTONEG_ADVERT); - PHY_RTN_ON_READ_ERROR(phy_data); - - phy_data &= ~QCA803X_ADVERTISE_MEGA_ALL; - - if (autoneg & FAL_PHY_ADV_100TX_FD) { - phy_data |= QCA803X_ADVERTISE_100FULL; - } - if (autoneg & FAL_PHY_ADV_100TX_HD) { - phy_data |= QCA803X_ADVERTISE_100HALF; - } - if (autoneg & FAL_PHY_ADV_10T_FD) { - phy_data |= QCA803X_ADVERTISE_10FULL; - } - if (autoneg & FAL_PHY_ADV_10T_HD) { - phy_data |= QCA803X_ADVERTISE_10HALF; - } - if (autoneg & FAL_PHY_ADV_PAUSE) { - phy_data |= QCA803X_ADVERTISE_PAUSE; - } - if (autoneg & FAL_PHY_ADV_ASY_PAUSE) { - phy_data |= QCA803X_ADVERTISE_ASYM_PAUSE; - } - if (autoneg & FAL_PHY_ADV_1000T_FD) { - phy_data |= QCA803X_EXTENDED_NEXT_PAGE_EN; - } else { - phy_data &= ~QCA803X_EXTENDED_NEXT_PAGE_EN; - } - qca803x_phy_reg_write(dev_id, phy_id, QCA803X_AUTONEG_ADVERT, - phy_data); - - phy_data = qca803x_phy_reg_read(dev_id, phy_id, - QCA803X_1000BASET_CONTROL); - PHY_RTN_ON_READ_ERROR(phy_data); - - phy_data &= ~QCA803X_ADVERTISE_1000FULL; - phy_data &= ~QCA803X_ADVERTISE_1000HALF; - - if (autoneg & FAL_PHY_ADV_1000T_FD) { - phy_data |= QCA803X_ADVERTISE_1000FULL; - } - qca803x_phy_reg_write(dev_id, phy_id, QCA803X_1000BASET_CONTROL, - phy_data); - - return SW_OK; -} - -/****************************************************************************** -* -* qca803x_get_autoneg_adv - get the phy autoneg Advertisement -* -*/ -sw_error_t -qca803x_phy_get_autoneg_adv(a_uint32_t dev_id, a_uint32_t phy_id, - a_uint32_t * autoneg) -{ - a_uint16_t phy_data = 0; - - *autoneg = 0; - phy_data = - qca803x_phy_reg_read(dev_id, phy_id, QCA803X_AUTONEG_ADVERT); - PHY_RTN_ON_READ_ERROR(phy_data); - - if (phy_data & QCA803X_ADVERTISE_100FULL) - *autoneg |= FAL_PHY_ADV_100TX_FD; - - if (phy_data & QCA803X_ADVERTISE_100HALF) - *autoneg |= FAL_PHY_ADV_100TX_HD; - - if (phy_data & QCA803X_ADVERTISE_10FULL) - *autoneg |= FAL_PHY_ADV_10T_FD; - - if (phy_data & QCA803X_ADVERTISE_10HALF) - *autoneg |= FAL_PHY_ADV_10T_HD; - - if (phy_data & QCA803X_ADVERTISE_PAUSE) - *autoneg |= FAL_PHY_ADV_PAUSE; - - if (phy_data & QCA803X_ADVERTISE_ASYM_PAUSE) - *autoneg |= FAL_PHY_ADV_ASY_PAUSE; - - phy_data = qca803x_phy_reg_read(dev_id, phy_id, - QCA803X_1000BASET_CONTROL); - PHY_RTN_ON_READ_ERROR(phy_data); - - if (phy_data & QCA803X_ADVERTISE_1000FULL) - *autoneg |= FAL_PHY_ADV_1000T_FD; - - return SW_OK; -} - -/****************************************************************************** -* -* qca803x_phy_autoneg_status -* -* Power off the phy -*/ -a_bool_t qca803x_phy_autoneg_status(a_uint32_t dev_id, a_uint32_t phy_id) -{ - a_uint16_t phy_data; - - phy_data = qca803x_phy_reg_read(dev_id, phy_id, QCA803X_PHY_CONTROL); - - if (phy_data & QCA803X_CTRL_AUTONEGOTIATION_ENABLE) - return A_TRUE; - - return A_FALSE; -} - -/****************************************************************************** -* -* qca803x_restart_autoneg - restart the phy autoneg -* -*/ -sw_error_t qca803x_phy_restart_autoneg(a_uint32_t dev_id, a_uint32_t phy_id) -{ - a_uint16_t phy_data = 0; - sw_error_t rv = SW_OK; - - phy_data = qca803x_phy_reg_read(dev_id, phy_id, QCA803X_PHY_CONTROL); - PHY_RTN_ON_READ_ERROR(phy_data); - - phy_data |= QCA803X_CTRL_AUTONEGOTIATION_ENABLE; - rv = qca803x_phy_reg_write(dev_id, phy_id, QCA803X_PHY_CONTROL, - phy_data | QCA803X_CTRL_RESTART_AUTONEGOTIATION); - - return rv; -} -/****************************************************************************** -* -* qca803x_phy_enable_autonego -* -*/ -sw_error_t qca803x_phy_enable_autoneg(a_uint32_t dev_id, a_uint32_t phy_id) -{ - a_uint16_t phy_data = 0; - sw_error_t rv = SW_OK; - - phy_data = qca803x_phy_reg_read(dev_id, phy_id, QCA803X_PHY_CONTROL); - PHY_RTN_ON_READ_ERROR(phy_data); - - rv = qca803x_phy_reg_write(dev_id, phy_id, QCA803X_PHY_CONTROL, - phy_data | QCA803X_CTRL_AUTONEGOTIATION_ENABLE); - - return rv; -} -#ifndef IN_PORTCONTROL_MINI -/****************************************************************************** -* -* qca803x_phy_get_ability - get the phy ability -* -* -*/ -sw_error_t -qca803x_phy_get_ability(a_uint32_t dev_id, a_uint32_t phy_id, - a_uint32_t * ability) -{ - a_uint16_t phy_data; - - *ability = 0; - - phy_data = qca803x_phy_reg_read(dev_id, phy_id, QCA803X_PHY_STATUS); - PHY_RTN_ON_READ_ERROR(phy_data); - - if (phy_data & QCA803X_STATUS_AUTONEG_CAPS) - *ability |= FAL_PHY_AUTONEG_CAPS; - - if (phy_data & QCA803X_STATUS_100T2_HD_CAPS) - *ability |= FAL_PHY_100T2_HD_CAPS; - - if (phy_data & QCA803X_STATUS_100T2_FD_CAPS) - *ability |= FAL_PHY_100T2_FD_CAPS; - - if (phy_data & QCA803X_STATUS_10T_HD_CAPS) - *ability |= FAL_PHY_10T_HD_CAPS; - - if (phy_data & QCA803X_STATUS_10T_FD_CAPS) - *ability |= FAL_PHY_10T_FD_CAPS; - - if (phy_data & QCA803X_STATUS_100X_HD_CAPS) - *ability |= FAL_PHY_100X_HD_CAPS; - - if (phy_data & QCA803X_STATUS_100X_FD_CAPS) - *ability |= FAL_PHY_100X_FD_CAPS; - - if (phy_data & QCA803X_STATUS_100T4_CAPS) - *ability |= FAL_PHY_100T4_CAPS; - - if (phy_data & QCA803X_STATUS_EXTENDED_STATUS) { - phy_data = - qca803x_phy_reg_read(dev_id, phy_id, QCA803X_EXTENDED_STATUS); - PHY_RTN_ON_READ_ERROR(phy_data); - - if (phy_data & QCA803X_STATUS_1000T_FD_CAPS) { - *ability |= FAL_PHY_1000T_FD_CAPS; - } - - if (phy_data & QCA803X_STATUS_1000X_FD_CAPS) { - *ability |= FAL_PHY_1000X_FD_CAPS; - } - } - - return SW_OK; -} - -/****************************************************************************** -* -* qca803x_phy_get_partner_ability - get the phy ability -* -* -*/ -sw_error_t -qca803x_phy_get_partner_ability(a_uint32_t dev_id, a_uint32_t phy_id, - a_uint32_t * ability) -{ - a_uint16_t phy_data; - - *ability = 0; - - phy_data = - qca803x_phy_reg_read(dev_id, phy_id, QCA803X_LINK_PARTNER_ABILITY); - PHY_RTN_ON_READ_ERROR(phy_data); - - if (phy_data & QCA803X_LINK_10BASETX_HALF_DUPLEX) - *ability |= FAL_PHY_PART_10T_HD; - - if (phy_data & QCA803X_LINK_10BASETX_FULL_DUPLEX) - *ability |= FAL_PHY_PART_10T_FD; - - if (phy_data & QCA803X_LINK_100BASETX_HALF_DUPLEX) - *ability |= FAL_PHY_PART_100TX_HD; - - if (phy_data & QCA803X_LINK_100BASETX_FULL_DUPLEX) - *ability |= FAL_PHY_PART_100TX_FD; - - if (phy_data & QCA803X_LINK_NPAGE) { - phy_data = - qca803x_phy_reg_read(dev_id, phy_id, - QCA803X_1000BASET_STATUS); - PHY_RTN_ON_READ_ERROR(phy_data); - - if (phy_data & QCA803X_LINK_1000BASETX_FULL_DUPLEX) - *ability |= FAL_PHY_PART_1000T_FD; - } - - return SW_OK; -} - -/****************************************************************************** -* -* qca803x_phy_reset_done - reset the phy -* -* reset the phy -*/ -a_bool_t qca803x_phy_reset_done(a_uint32_t dev_id, a_uint32_t phy_id) -{ - a_uint16_t phy_data; - a_uint16_t ii = 200; - - do { - phy_data = - qca803x_phy_reg_read(dev_id, phy_id, QCA803X_PHY_CONTROL); - aos_mdelay(10); - } - while ((!QCA803X_RESET_DONE(phy_data)) && --ii); - - if (ii == 0) - return A_FALSE; - - return A_TRUE; -} - -/****************************************************************************** -* -* qca803x_autoneg_done -* -* qca803x_autoneg_done -*/ -a_bool_t qca803x_autoneg_done(a_uint32_t dev_id, a_uint32_t phy_id) -{ - a_uint16_t phy_data; - a_uint16_t ii = 200; - - do { - phy_data = - qca803x_phy_reg_read(dev_id, phy_id, QCA803X_PHY_STATUS); - aos_mdelay(10); - } - while ((!QCA803X_AUTONEG_DONE(phy_data)) && --ii); - - if (ii == 0) - return A_FALSE; - - return A_TRUE; -} - -/****************************************************************************** -* -* qca803x_phy_Speed_Duplex_Resolved - - reset the phy -* -* reset the phy -*/ -a_bool_t qca803x_phy_speed_duplex_resolved(a_uint32_t dev_id, a_uint32_t phy_id) -{ - a_uint16_t phy_data; - a_uint16_t ii = 200; - - do { - phy_data = - qca803x_phy_reg_read(dev_id, phy_id, QCA803X_PHY_SPEC_STATUS); - aos_mdelay(10); - } - while ((!QCA803X_SPEED_DUPLEX_RESOVLED(phy_data)) && --ii); - - if (ii == 0) - return A_FALSE; - - return A_TRUE; -} -#endif -/****************************************************************************** -* -* qca803x_phy_get_phy_id - get the phy id -* -*/ -sw_error_t -qca803x_phy_get_phy_id(a_uint32_t dev_id, a_uint32_t phy_id, - a_uint32_t *phy_data) -{ - a_uint16_t org_id, rev_id; - - org_id = qca803x_phy_reg_read(dev_id, phy_id, QCA803X_PHY_ID1); - rev_id = qca803x_phy_reg_read(dev_id, phy_id, QCA803X_PHY_ID2); - - *phy_data = ((org_id & 0xffff) << 16) | (rev_id & 0xffff); - - return SW_OK; -} - -/****************************************************************************** -* -* qca803x_phy_off - power off the phy -* -* Power off the phy -*/ -sw_error_t qca803x_phy_poweroff(a_uint32_t dev_id, a_uint32_t phy_id) -{ - a_uint16_t phy_data; - phy_data = qca803x_phy_reg_read(dev_id, phy_id, QCA803X_PHY_CONTROL); - PHY_RTN_ON_READ_ERROR(phy_data); - - qca803x_phy_reg_write(dev_id, phy_id, QCA803X_PHY_CONTROL, - phy_data | QCA803X_CTRL_POWER_DOWN); - return SW_OK; -} - -/****************************************************************************** -* -* qca803x_phy_on - power on the phy -* -* Power on the phy -*/ -sw_error_t qca803x_phy_poweron(a_uint32_t dev_id, a_uint32_t phy_id) -{ - a_uint16_t phy_data; - phy_data = qca803x_phy_reg_read(dev_id, phy_id, QCA803X_PHY_CONTROL); - PHY_RTN_ON_READ_ERROR(phy_data); - - qca803x_phy_reg_write(dev_id, phy_id, QCA803X_PHY_CONTROL, - phy_data & ~QCA803X_CTRL_POWER_DOWN); - - aos_mdelay(200); - - return SW_OK; -} -#ifndef IN_PORTCONTROL_MINI -/****************************************************************************** -* -* qca803x_phy_set_802.3az -* -* set 802.3az status -*/ -sw_error_t -qca803x_phy_set_8023az(a_uint32_t dev_id, a_uint32_t phy_id, a_bool_t enable) -{ - a_uint16_t phy_data; - - phy_data = qca803x_phy_mmd_read(dev_id, phy_id, QCA803X_PHY_MMD7_NUM, - QCA803X_PHY_MMD7_ADDR_8023AZ_EEE_CTRL); - PHY_RTN_ON_READ_ERROR(phy_data); - - if (enable == A_TRUE) { - phy_data |= 0x0006; - - qca803x_phy_mmd_write(dev_id, phy_id, QCA803X_PHY_MMD7_NUM, - QCA803X_PHY_MMD7_ADDR_8023AZ_EEE_CTRL, phy_data); - } else { - phy_data &= ~0x0006; - - qca803x_phy_mmd_write(dev_id, phy_id, QCA803X_PHY_MMD7_NUM, - QCA803X_PHY_MMD7_ADDR_8023AZ_EEE_CTRL, phy_data); - } - - qca803x_phy_restart_autoneg(dev_id, phy_id); - - return SW_OK; -} - -/****************************************************************************** -* -* qca803x_phy_get_8023az status -* -* get 8023az status -*/ -sw_error_t -qca803x_phy_get_8023az(a_uint32_t dev_id, a_uint32_t phy_id, a_bool_t * enable) -{ - a_uint16_t phy_data; - *enable = A_FALSE; - - phy_data = qca803x_phy_mmd_read(dev_id, phy_id, QCA803X_PHY_MMD7_NUM, - QCA803X_PHY_MMD7_ADDR_8023AZ_EEE_CTRL); - PHY_RTN_ON_READ_ERROR(phy_data); - - if ((phy_data & 0x0004) && (phy_data & 0x0002)) - *enable = A_TRUE; - - return SW_OK; -} - -/****************************************************************************** -* -* qca803x_phy_set_powersave - set power saving status -* -* set power saving status -*/ -sw_error_t -qca803x_phy_set_powersave(a_uint32_t dev_id, a_uint32_t phy_id, a_bool_t enable) -{ - a_uint16_t phy_data; - - phy_data = qca803x_phy_debug_read(dev_id, phy_id, QCA803X_PWR_SAVE); - PHY_RTN_ON_READ_ERROR(phy_data); - - if (enable == A_TRUE) - phy_data = phy_data | QCA803X_PWR_SAVE_EN; - else - phy_data = phy_data & ~QCA803X_PWR_SAVE_EN; - - qca803x_phy_debug_write(dev_id, phy_id, QCA803X_PWR_SAVE, phy_data); - - qca803x_phy_restart_autoneg(dev_id, phy_id); - - return SW_OK; -} - -/****************************************************************************** -* -* qca803x_phy_get_powersave - get power saving status -* -* set power saving status -*/ -sw_error_t -qca803x_phy_get_powersave(a_uint32_t dev_id, a_uint32_t phy_id, - a_bool_t * enable) -{ - a_uint16_t phy_data; - - phy_data = qca803x_phy_debug_read(dev_id, phy_id, QCA803X_PWR_SAVE); - PHY_RTN_ON_READ_ERROR(phy_data); - - if (phy_data & QCA803X_PWR_SAVE_EN) - *enable = A_FALSE; - else - *enable = A_TRUE; - - return SW_OK; -} - -/****************************************************************************** -* -* qca803x_phy_set wol frame mac address -* -* set phy wol frame mac address -*/ -sw_error_t -qca803x_phy_set_magic_frame_mac(a_uint32_t dev_id, a_uint32_t phy_id, - fal_mac_addr_t * mac) -{ - a_uint16_t phy_data1; - a_uint16_t phy_data2; - a_uint16_t phy_data3; - - phy_data1 = (mac->uc[0] << 8) | mac->uc[1]; - phy_data2 = (mac->uc[2] << 8) | mac->uc[3]; - phy_data3 = (mac->uc[4] << 8) | mac->uc[5]; - - qca803x_phy_mmd_write(dev_id, phy_id, QCA803X_PHY_MMD3_NUM, - QCA803X_PHY_MMD3_WOL_MAGIC_MAC_CTRL1, phy_data1); - - qca803x_phy_mmd_write(dev_id, phy_id, QCA803X_PHY_MMD3_NUM, - QCA803X_PHY_MMD3_WOL_MAGIC_MAC_CTRL2, phy_data2); - - qca803x_phy_mmd_write(dev_id, phy_id, QCA803X_PHY_MMD3_NUM, - QCA803X_PHY_MMD3_WOL_MAGIC_MAC_CTRL3, phy_data3); - - return SW_OK; -} - -/****************************************************************************** -* -* qca803x_phy_get wol frame mac address -* -* get phy wol frame mac address -*/ -sw_error_t -qca803x_phy_get_magic_frame_mac(a_uint32_t dev_id, a_uint32_t phy_id, - fal_mac_addr_t * mac) -{ - a_uint16_t phy_data1; - a_uint16_t phy_data2; - a_uint16_t phy_data3; - - phy_data1 = qca803x_phy_mmd_read(dev_id, phy_id, QCA803X_PHY_MMD3_NUM, - QCA803X_PHY_MMD3_WOL_MAGIC_MAC_CTRL1); - - phy_data2 = qca803x_phy_mmd_read(dev_id, phy_id, QCA803X_PHY_MMD3_NUM, - QCA803X_PHY_MMD3_WOL_MAGIC_MAC_CTRL2); - - phy_data3 = qca803x_phy_mmd_read(dev_id, phy_id, QCA803X_PHY_MMD3_NUM, - QCA803X_PHY_MMD3_WOL_MAGIC_MAC_CTRL3); - - mac->uc[0] = (phy_data1 >> 8); - mac->uc[1] = (phy_data1 & 0x00ff); - mac->uc[2] = (phy_data2 >> 8); - mac->uc[3] = (phy_data2 & 0x00ff); - mac->uc[4] = (phy_data3 >> 8); - mac->uc[5] = (phy_data3 & 0x00ff); - - return SW_OK; -} - -/****************************************************************************** -* -* qca803x_phy_set wol enable or disable -* -* set phy wol enable or disable -*/ -sw_error_t -qca803x_phy_set_wol_status(a_uint32_t dev_id, a_uint32_t phy_id, a_bool_t enable) -{ - a_uint16_t phy_data; - phy_data = qca803x_phy_mmd_read(dev_id, phy_id, QCA803X_PHY_MMD3_NUM, - QCA803X_PHY_MMD3_WOL_CTRL); - PHY_RTN_ON_READ_ERROR(phy_data); - - if (enable == A_TRUE) { - phy_data |= 0x0020; - } else { - phy_data &= ~0x0020; - } - - qca803x_phy_mmd_write(dev_id, phy_id, QCA803X_PHY_MMD3_NUM, - QCA803X_PHY_MMD3_WOL_CTRL, phy_data); - - return SW_OK; -} - -/****************************************************************************** -* -* qca803x_phy_get_wol status -* -* get wol status -*/ -sw_error_t -qca803x_phy_get_wol_status(a_uint32_t dev_id, a_uint32_t phy_id, a_bool_t * enable) -{ - a_uint16_t phy_data; - - *enable = A_FALSE; - - phy_data = qca803x_phy_mmd_read(dev_id, phy_id, QCA803X_PHY_MMD3_NUM, - QCA803X_PHY_MMD3_WOL_CTRL); - PHY_RTN_ON_READ_ERROR(phy_data); - - if (phy_data & 0x0020) - *enable = A_TRUE; - - return SW_OK; -} - -/****************************************************************************** -* -* qca803x_phy_set_hibernate - set hibernate status -* -* set hibernate status -*/ -sw_error_t -qca803x_phy_set_hibernate(a_uint32_t dev_id, a_uint32_t phy_id, a_bool_t enable) -{ - a_uint16_t phy_data; - - phy_data = qca803x_phy_debug_read(dev_id, phy_id, - QCA803X_DEBUG_PHY_HIBERNATION_CTRL); - PHY_RTN_ON_READ_ERROR(phy_data); - - if (enable == A_TRUE) { - phy_data |= 0x8000; - } else { - phy_data &= ~0x8000; - } - - qca803x_phy_debug_write(dev_id, phy_id, - QCA803X_DEBUG_PHY_HIBERNATION_CTRL, phy_data); - - return SW_OK; -} - -/****************************************************************************** -* -* qca803x_phy_get_hibernate - get hibernate status -* -* get hibernate status -*/ -sw_error_t -qca803x_phy_get_hibernate(a_uint32_t dev_id, a_uint32_t phy_id, - a_bool_t * enable) -{ - a_uint16_t phy_data; - - *enable = A_FALSE; - - phy_data = qca803x_phy_debug_read(dev_id, phy_id, - QCA803X_DEBUG_PHY_HIBERNATION_CTRL); - PHY_RTN_ON_READ_ERROR(phy_data); - - if (phy_data & 0x8000) - *enable = A_TRUE; - - return SW_OK; -} -#endif -sw_error_t -__phy_chip_config_get(a_uint32_t dev_id, a_uint32_t phy_id, - qca803x_cfg_type_t cfg_sel, qca803x_cfg_t *cfg_value) -{ - a_uint16_t phy_data; - phy_data = qca803x_phy_reg_read(dev_id, phy_id, QCA803X_PHY_CHIP_CONFIG); - PHY_RTN_ON_READ_ERROR(phy_data); - - if (cfg_sel == QCA803X_CHIP_CFG_STAT) - *cfg_value = (phy_data & QCA803X_PHY_CHIP_MODE_STAT) >> 4; - else - *cfg_value = phy_data & QCA803X_PHY_CHIP_MODE_CFG; - - return SW_OK; -} - -/****************************************************************************** -* -* qca803x_phy_interface mode set -* -* set qca803x phy interface mode -*/ -sw_error_t -qca803x_phy_interface_set_mode(a_uint32_t dev_id, a_uint32_t phy_id, fal_port_interface_mode_t interface_mode) -{ - a_uint16_t phy_data; - - QCA803X_REG_LOCK; - - phy_data = qca803x_phy_reg_read(dev_id, phy_id, QCA803X_PHY_CHIP_CONFIG); - - phy_data &= 0xfff0; - - switch (interface_mode) { - case PORT_RGMII_BASET: - phy_data |= QCA803X_PHY_RGMII_BASET; - break; - case PHY_SGMII_BASET: - phy_data |= QCA803X_PHY_SGMII_BASET; - break; - case PORT_RGMII_BX1000: - phy_data |= QCA803X_PHY_BX1000_RGMII_50; - break; - case PORT_RGMII_FX100: - phy_data |= QCA803X_PHY_FX100_RGMII_50; - break; - case PORT_RGMII_AMDET: - phy_data |= QCA803X_PHY_RGMII_AMDET; - break; - default: - QCA803X_REG_UNLOCK; - return SW_BAD_PARAM; - } - - qca803x_phy_reg_write(dev_id, phy_id, QCA803X_PHY_CHIP_CONFIG, phy_data); - - QCA803X_REG_UNLOCK; - - /* reset operation */ - qca803x_phy_reset(dev_id, phy_id); - - return SW_OK; -} - -/****************************************************************************** -* -* qca803x_phy_interface mode get -* -* get qca803x phy interface mode -*/ -sw_error_t -qca803x_phy_interface_get_mode(a_uint32_t dev_id, a_uint32_t phy_id, fal_port_interface_mode_t *interface_mode) -{ - qca803x_cfg_t cfg_value; - SW_RTN_ON_ERROR(__phy_chip_config_get(dev_id, phy_id, - QCA803X_CHIP_CFG_SET, &cfg_value)); - - switch (cfg_value) { - case QCA803X_PHY_RGMII_BASET: - *interface_mode = PORT_RGMII_BASET; - break; - case QCA803X_PHY_SGMII_BASET: - *interface_mode = PHY_SGMII_BASET; - break; - case QCA803X_PHY_BX1000_RGMII_50: - *interface_mode = PORT_RGMII_BX1000; - break; - case QCA803X_PHY_FX100_RGMII_50: - *interface_mode = PORT_RGMII_FX100; - break; - case QCA803X_PHY_RGMII_AMDET: - *interface_mode = PORT_RGMII_AMDET; - break; - default: - *interface_mode = PORT_INTERFACE_MODE_MAX; - break; - } - - return SW_OK; -} - -/****************************************************************************** -* -* qca803x_phy_interface mode status get -* -* get qca803x phy interface mode status -*/ -sw_error_t -qca803x_phy_interface_get_mode_status(a_uint32_t dev_id, a_uint32_t phy_id, fal_port_interface_mode_t *interface_mode_status) -{ - qca803x_cfg_t cfg_value; - - SW_RTN_ON_ERROR(__phy_chip_config_get(dev_id, phy_id, - QCA803X_CHIP_CFG_STAT, &cfg_value)); - - switch (cfg_value) { - case QCA803X_PHY_RGMII_BASET: - *interface_mode_status = PORT_RGMII_BASET; - break; - case QCA803X_PHY_SGMII_BASET: - *interface_mode_status = PHY_SGMII_BASET; - break; - case QCA803X_PHY_BX1000_RGMII_50: - *interface_mode_status = PORT_RGMII_BX1000; - break; - case QCA803X_PHY_FX100_RGMII_50: - *interface_mode_status = PORT_RGMII_FX100; - break; - case QCA803X_PHY_RGMII_AMDET: - *interface_mode_status = PORT_RGMII_AMDET; - break; - default: - *interface_mode_status = PORT_INTERFACE_MODE_MAX; - break; - } - - return SW_OK; -} -#ifndef IN_PORTCONTROL_MINI -/****************************************************************************** -* -* qca803x_phy_set_intr_mask - Set interrupt mask with the -* specified device. -*/ -sw_error_t -qca803x_phy_set_intr_mask(a_uint32_t dev_id, a_uint32_t phy_id, - a_uint32_t intr_mask_flag) -{ - a_uint16_t phy_data = 0; - - phy_data = qca803x_phy_reg_read(dev_id, phy_id, QCA803X_PHY_INTR_MASK); - PHY_RTN_ON_READ_ERROR(phy_data); - - if (FAL_PHY_INTR_STATUS_UP_CHANGE & intr_mask_flag) { - phy_data |= QCA803X_INTR_STATUS_UP_CHANGE; - } else { - phy_data &= (~QCA803X_INTR_STATUS_UP_CHANGE); - } - - if (FAL_PHY_INTR_STATUS_DOWN_CHANGE & intr_mask_flag) { - phy_data |= QCA803X_INTR_STATUS_DOWN_CHANGE; - } else { - phy_data &= (~QCA803X_INTR_STATUS_DOWN_CHANGE); - } - - if (FAL_PHY_INTR_SPEED_CHANGE & intr_mask_flag) { - phy_data |= QCA803X_INTR_SPEED_CHANGE; - } else { - phy_data &= (~QCA803X_INTR_SPEED_CHANGE); - } - - /* DUPLEX INTR bit is reserved for AR803X phy - if (FAL_PHY_INTR_DUPLEX_CHANGE & intr_mask_flag) { - phy_data |= QCA803X_INTR_DUPLEX_CHANGE; - } else { - phy_data &= (~QCA803X_INTR_DUPLEX_CHANGE); - } - */ - - if (FAL_PHY_INTR_BX_FX_STATUS_UP_CHANGE & intr_mask_flag) { - phy_data |= QCA803X_INTR_BX_FX_STATUS_UP_CHANGE; - } else { - phy_data &= (~QCA803X_INTR_BX_FX_STATUS_UP_CHANGE); - } - - if (FAL_PHY_INTR_BX_FX_STATUS_DOWN_CHANGE & intr_mask_flag) { - phy_data |= QCA803X_INTR_BX_FX_STATUS_DOWN_CHANGE; - } else { - phy_data &= (~QCA803X_INTR_BX_FX_STATUS_DOWN_CHANGE); - } - - if (FAL_PHY_INTR_MEDIA_STATUS_CHANGE & intr_mask_flag) { - phy_data |= QCA803X_INTR_MEDIA_STATUS_CHANGE; - } else { - phy_data &= (~QCA803X_INTR_MEDIA_STATUS_CHANGE); - } - - if (FAL_PHY_INTR_WOL_STATUS & intr_mask_flag) { - phy_data |= QCA803X_INTR_WOL; - } else { - phy_data &= (~QCA803X_INTR_WOL); - } - - if (FAL_PHY_INTR_POE_STATUS & intr_mask_flag) { - phy_data |= QCA803X_INTR_POE; - } else { - phy_data &= (~QCA803X_INTR_POE); - } - - qca803x_phy_reg_write(dev_id, phy_id, QCA803X_PHY_INTR_MASK, phy_data); - return SW_OK; -} - -/****************************************************************************** -* -* qca803x_phy_get_intr_mask - Get interrupt mask with the -* specified device. -*/ -sw_error_t -qca803x_phy_get_intr_mask(a_uint32_t dev_id, a_uint32_t phy_id, - a_uint32_t * intr_mask_flag) -{ - a_uint16_t phy_data = 0; - - phy_data = qca803x_phy_reg_read(dev_id, phy_id, QCA803X_PHY_INTR_MASK); - PHY_RTN_ON_READ_ERROR(phy_data); - - *intr_mask_flag = 0; - if (QCA803X_INTR_STATUS_UP_CHANGE & phy_data) { - *intr_mask_flag |= FAL_PHY_INTR_STATUS_UP_CHANGE; - } - - if (QCA803X_INTR_STATUS_DOWN_CHANGE & phy_data) { - *intr_mask_flag |= FAL_PHY_INTR_STATUS_DOWN_CHANGE; - } - - if (QCA803X_INTR_SPEED_CHANGE & phy_data) { - *intr_mask_flag |= FAL_PHY_INTR_SPEED_CHANGE; - } - - /* DUPLEX INTR bit is reserved for AR803X phy - if (QCA803X_INTR_DUPLEX_CHANGE & phy_data) { - *intr_mask_flag |= FAL_PHY_INTR_DUPLEX_CHANGE; - } - */ - - if (QCA803X_INTR_BX_FX_STATUS_UP_CHANGE & phy_data) { - *intr_mask_flag |= FAL_PHY_INTR_BX_FX_STATUS_UP_CHANGE; - } - - if (QCA803X_INTR_BX_FX_STATUS_DOWN_CHANGE & phy_data) { - *intr_mask_flag |= FAL_PHY_INTR_BX_FX_STATUS_DOWN_CHANGE; - } - - if (QCA803X_INTR_MEDIA_STATUS_CHANGE & phy_data) { - *intr_mask_flag |= FAL_PHY_INTR_MEDIA_STATUS_CHANGE; - } - - if (QCA803X_INTR_WOL & phy_data) { - *intr_mask_flag |= FAL_PHY_INTR_WOL_STATUS; - } - - if (QCA803X_INTR_POE & phy_data) { - *intr_mask_flag |= FAL_PHY_INTR_POE_STATUS; - } - - return SW_OK; -} - -/****************************************************************************** -* -* qca803x_phy_get_intr_status - Get interrupt status with the -* specified device. -*/ -sw_error_t -qca803x_phy_get_intr_status(a_uint32_t dev_id, a_uint32_t phy_id, - a_uint32_t * intr_status_flag) -{ - a_uint16_t phy_data = 0; - - phy_data = qca803x_phy_reg_read(dev_id, phy_id, QCA803X_PHY_INTR_STATUS); - PHY_RTN_ON_READ_ERROR(phy_data); - - *intr_status_flag = 0; - if (QCA803X_INTR_STATUS_UP_CHANGE & phy_data) { - *intr_status_flag |= FAL_PHY_INTR_STATUS_UP_CHANGE; - } - - if (QCA803X_INTR_STATUS_DOWN_CHANGE & phy_data) { - *intr_status_flag |= FAL_PHY_INTR_STATUS_DOWN_CHANGE; - } - - if (QCA803X_INTR_SPEED_CHANGE & phy_data) { - *intr_status_flag |= FAL_PHY_INTR_SPEED_CHANGE; - } - - /* DUPLEX INTR bit is reserved for AR803X phy - if (QCA803X_INTR_DUPLEX_CHANGE & phy_data) { - *intr_status_flag |= FAL_PHY_INTR_DUPLEX_CHANGE; - } - */ - - if (QCA803X_INTR_BX_FX_STATUS_UP_CHANGE & phy_data) { - *intr_status_flag |= FAL_PHY_INTR_BX_FX_STATUS_UP_CHANGE; - } - - if (QCA803X_INTR_BX_FX_STATUS_DOWN_CHANGE & phy_data) { - *intr_status_flag |= FAL_PHY_INTR_BX_FX_STATUS_DOWN_CHANGE; - } - if (QCA803X_INTR_MEDIA_STATUS_CHANGE & phy_data) { - *intr_status_flag |= FAL_PHY_INTR_MEDIA_STATUS_CHANGE; - } - - if (QCA803X_INTR_WOL & phy_data) { - *intr_status_flag |= FAL_PHY_INTR_WOL_STATUS; - } - - if (QCA803X_INTR_POE & phy_data) { - *intr_status_flag |= FAL_PHY_INTR_POE_STATUS; - } - - return SW_OK; -} - -/****************************************************************************** -* -* qca803x_phy_set combo medium type -* -* set combo medium fiber or copper -*/ -sw_error_t -qca803x_phy_set_combo_prefer_medium(a_uint32_t dev_id, a_uint32_t phy_id, - fal_port_medium_t phy_medium) -{ - a_uint16_t phy_data; - - QCA803X_REG_LOCK; - - phy_data = qca803x_phy_reg_read(dev_id, phy_id, QCA803X_PHY_CHIP_CONFIG); - - if (phy_medium == PHY_MEDIUM_FIBER) - phy_data |= QCA803X_PHY_PREFER_FIBER; - else if (phy_medium == PHY_MEDIUM_COPPER) - phy_data &= ~QCA803X_PHY_PREFER_FIBER; - else { - QCA803X_REG_UNLOCK; - return SW_BAD_PARAM; - } - - qca803x_phy_reg_write(dev_id, phy_id, QCA803X_PHY_CHIP_CONFIG, phy_data); - - QCA803X_REG_UNLOCK; - - /* soft reset after switching combo medium*/ - qca803x_phy_reset(dev_id, phy_id); - - return SW_OK; -} - -/****************************************************************************** -* -* qca803x_phy_get combo medium type -* -* get combo medium fiber or copper -*/ -sw_error_t -qca803x_phy_get_combo_prefer_medium(a_uint32_t dev_id, a_uint32_t phy_id, - fal_port_medium_t * phy_medium) -{ - a_uint16_t phy_data; - - phy_data = qca803x_phy_reg_read(dev_id, phy_id, QCA803X_PHY_CHIP_CONFIG); - PHY_RTN_ON_READ_ERROR(phy_data); - - *phy_medium = - (phy_data & QCA803X_PHY_PREFER_FIBER) ? PHY_MEDIUM_FIBER : - PHY_MEDIUM_COPPER; - - return SW_OK; -} - -/****************************************************************************** -* -* qca803x phy activer medium -* -* get qca803x phy current active medium, fiber or copper; -*/ -static qca803x_phy_medium_t __phy_active_medium_get(a_uint32_t dev_id, - a_uint32_t phy_id) -{ - qca803x_cfg_t cfg_value; - - SW_RTN_ON_ERROR(__phy_chip_config_get(dev_id, phy_id, - QCA803X_CHIP_CFG_STAT, &cfg_value)); - - switch (cfg_value) { - case QCA803X_PHY_RGMII_BASET: - case QCA803X_PHY_SGMII_BASET: - return QCA803X_PHY_MEDIUM_COPPER; - case QCA803X_PHY_BX1000_RGMII_50: - case QCA803X_PHY_FX100_RGMII_50: - return QCA803X_PHY_MEDIUM_FIBER; - case QCA803X_PHY_RGMII_AMDET: - default: - return QCA803X_PHY_MEDIUM_MAX; - } -} - -/****************************************************************************** -* -* qca803x_phy_get current combo medium type copper or fiber -* -* get current combo medium type -*/ -sw_error_t -qca803x_phy_get_combo_current_medium_type(a_uint32_t dev_id, a_uint32_t phy_id, - fal_port_medium_t * phy_medium) -{ - qca803x_phy_medium_t phy_cur_meduim = __phy_active_medium_get(dev_id, phy_id); - - /* auto media select is not done - * or link down, then return prefer medium */ - if (phy_cur_meduim == QCA803X_PHY_MEDIUM_MAX) - qca803x_phy_get_combo_prefer_medium(dev_id, phy_id, phy_medium); - else - *phy_medium = phy_cur_meduim; - - return SW_OK; -} - -/****************************************************************************** -* -* qca803x_phy_set fiber mode 1000bx or 100fx -* -* set combo fbier mode -*/ -sw_error_t -qca803x_phy_set_combo_fiber_mode(a_uint32_t dev_id, a_uint32_t phy_id, - fal_port_fiber_mode_t fiber_mode) -{ - a_uint16_t phy_data; - - QCA803X_REG_LOCK; - - phy_data = qca803x_phy_reg_read(dev_id, phy_id, QCA803X_PHY_CHIP_CONFIG); - - if (fiber_mode == PHY_FIBER_1000BX) { - phy_data |= QCA803X_PHY_FIBER_MODE_1000BX; - } else if (fiber_mode == PHY_FIBER_100FX) { - phy_data &= ~QCA803X_PHY_FIBER_MODE_1000BX; - } else { - QCA803X_REG_UNLOCK; - return SW_BAD_PARAM; - } - - qca803x_phy_reg_write(dev_id, phy_id, QCA803X_PHY_CHIP_CONFIG, phy_data); - - QCA803X_REG_UNLOCK; - - return SW_OK; -} - -/****************************************************************************** -* -* qca803x_phy_get fiber mode 1000bx or 100fx -* -* get combo fbier mode -*/ -sw_error_t -qca803x_phy_get_combo_fiber_mode(a_uint32_t dev_id, a_uint32_t phy_id, - fal_port_fiber_mode_t * fiber_mode) -{ - a_uint16_t phy_data; - - phy_data = qca803x_phy_reg_read(dev_id, phy_id, QCA803X_PHY_CHIP_CONFIG); - PHY_RTN_ON_READ_ERROR(phy_data); - - *fiber_mode = - (phy_data & QCA803X_PHY_FIBER_MODE_1000BX) ? PHY_FIBER_1000BX : - PHY_FIBER_100FX; - - return SW_OK; -} - -/****************************************************************************** -* -* qca803x_phy_set_counter_status - set counter status -* -*/ -sw_error_t -qca803x_phy_set_counter_status(a_uint32_t dev_id, a_uint32_t phy_id, - a_bool_t enable) -{ - a_uint16_t phy_data; - a_uint16_t frame_dir = 0; - - phy_data = qca803x_phy_mmd_read(dev_id, phy_id, - QCA803X_PHY_MMD7_NUM, - QCA803X_PHY_MMD7_FRAME_CTRL); - frame_dir = (phy_data & QCA803X_PHY_MMD7_FRAME_DIR) >> 14; - - /*for qca803x phy, tx and rx cannot be all enabled one time, - so we will enable tx or rx based current state, enable rx if - current is tx and enable tx if current is rx*/ - if (enable == A_TRUE) - { - phy_data |= QCA803X_PHY_MMD7_FRAME_CHECK; - /*enable RX counter*/ - if(frame_dir) - { - SSDK_INFO("ENABLE QCA803X RX COUNTER\n"); - phy_data &= ~QCA803X_PHY_MMD7_FRAME_DIR; - } - /*enable TX counter*/ - else - { - SSDK_INFO("ENABLE QCA803X TX COUNTER\n"); - phy_data |= QCA803X_PHY_MMD7_FRAME_DIR; - } - } - else - { - phy_data &= ~QCA803X_PHY_MMD7_FRAME_CHECK; - } - - qca803x_phy_mmd_write(dev_id, phy_id, QCA803X_PHY_MMD7_NUM, - QCA803X_PHY_MMD7_FRAME_CTRL, phy_data); - - return SW_OK; -} - -/****************************************************************************** -* -* qca803x_phy_get_counter_status - get counter status -* -*/ -sw_error_t -qca803x_phy_get_counter_status(a_uint32_t dev_id, a_uint32_t phy_id, - a_bool_t * enable) -{ - a_uint16_t phy_data; - *enable = A_FALSE; - - phy_data = qca803x_phy_mmd_read(dev_id, phy_id, - QCA803X_PHY_MMD7_NUM, - QCA803X_PHY_MMD7_FRAME_CTRL); - - if (phy_data & QCA803X_PHY_MMD7_FRAME_CHECK) { - *enable = A_TRUE; - } - - return SW_OK; -} - -/****************************************************************************** -* -* qca803x_phy_show_counter - show counter statistics -* -*/ -sw_error_t -qca803x_phy_show_counter(a_uint32_t dev_id, a_uint32_t phy_id, - fal_port_counter_info_t * counter_infor) -{ - a_uint16_t phy_data, phy_data1; - a_uint16_t frame_dir = 0; - - phy_data = qca803x_phy_mmd_read(dev_id, phy_id, - QCA803X_PHY_MMD7_NUM, - QCA803X_PHY_MMD7_FRAME_CTRL); - phy_data1 = qca803x_phy_mmd_read(dev_id, phy_id, - QCA803X_PHY_MMD7_NUM, - QCA803X_PHY_MMD7_FRAME_DATA); - frame_dir = (phy_data & QCA803X_PHY_MMD7_FRAME_DIR) >> 14; - - if(frame_dir) - { - /*get the counter of tx*/ - counter_infor->TxGoodFrame = phy_data1 & QCA803X_PHY_FRAME_CNT; - counter_infor->TxBadCRC = (phy_data1 & QCA803X_PHY_FRAME_ERROR) >> 8; - counter_infor->RxGoodFrame = 0; - counter_infor->RxBadCRC = 0; - } - else - { - /*get the counter of rx*/ - counter_infor->TxGoodFrame = 0; - counter_infor->TxBadCRC = 0; - counter_infor->RxGoodFrame = phy_data1 & QCA803X_PHY_FRAME_CNT; - counter_infor->RxBadCRC = (phy_data1 & QCA803X_PHY_FRAME_ERROR) >> 8; - } - - return SW_OK; -} - -#endif -/****************************************************************************** -* -* qca803x_phy_get status -* -* get phy status -*/ -sw_error_t -qca803x_phy_get_status(a_uint32_t dev_id, a_uint32_t phy_id, - struct port_phy_status *phy_status) -{ - a_uint16_t phy_data, phy_data1; - - phy_data = qca803x_phy_reg_read(dev_id, phy_id, QCA803X_PHY_SPEC_STATUS); - PHY_RTN_ON_READ_ERROR(phy_data); - phy_data1 = qca803x_phy_debug_read(dev_id, phy_id, - QCA803X_DEBUG_MSE_THRESH); - PHY_RTN_ON_READ_ERROR(phy_data1); - - /*get phy link status*/ - if (phy_data & QCA803X_STATUS_LINK_PASS) { - phy_status->link_status = A_TRUE; - if((phy_data1 & QCA803X_PHY_MSE_THRESH_MASK) != - QCA803X_PHY_MSE_THRESH_LINK_UP) { - phy_data1 &= ~QCA803X_PHY_MSE_THRESH_MASK; - SW_RTN_ON_ERROR(qca803x_phy_debug_write(dev_id, - phy_id, QCA803X_DEBUG_MSE_THRESH, - phy_data1 | QCA803X_PHY_MSE_THRESH_LINK_UP)); - } - } - else { - phy_status->link_status = A_FALSE; - if((phy_data1 & QCA803X_PHY_MSE_THRESH_MASK) != - QCA803X_PHY_MSE_THRESH_LINK_DOWN) { - phy_data1 &= ~QCA803X_PHY_MSE_THRESH_MASK; - SW_RTN_ON_ERROR(qca803x_phy_debug_write(dev_id, - phy_id, QCA803X_DEBUG_MSE_THRESH, - phy_data1 | QCA803X_PHY_MSE_THRESH_LINK_DOWN)); - } - return SW_OK; - } - - /*get phy speed*/ - switch (phy_data & QCA803X_STATUS_SPEED_MASK) { - case QCA803X_STATUS_SPEED_1000MBS: - phy_status->speed = FAL_SPEED_1000; - break; - case QCA803X_STATUS_SPEED_100MBS: - phy_status->speed = FAL_SPEED_100; - break; - case QCA803X_STATUS_SPEED_10MBS: - phy_status->speed = FAL_SPEED_10; - break; - default: - return SW_READ_ERROR; - } - - /*get phy duplex*/ - if (phy_data & QCA803X_STATUS_FULL_DUPLEX) - phy_status->duplex = FAL_FULL_DUPLEX; - else - phy_status->duplex = FAL_HALF_DUPLEX; - - /* get phy flowctrl resolution status */ - if (phy_data & QCA803X_PHY_RX_FLOWCTRL_STATUS) - phy_status->rx_flowctrl = A_TRUE; - else - phy_status->rx_flowctrl = A_FALSE; - - if (phy_data & QCA803X_PHY_TX_FLOWCTRL_STATUS) - phy_status->tx_flowctrl = A_TRUE; - else - phy_status->tx_flowctrl = A_FALSE; - - return SW_OK; -} -/****************************************************************************** -* -* qca803x_phy_set_eee_advertisement -* -* set eee advertisement -*/ -sw_error_t -qca803x_phy_set_eee_adv(a_uint32_t dev_id, a_uint32_t phy_id, - a_uint32_t adv) -{ - a_uint16_t phy_data = 0; - sw_error_t rv = SW_OK; - - phy_data = qca803x_phy_mmd_read(dev_id, phy_id, QCA803X_PHY_MMD7_NUM, - QCA803X_PHY_MMD7_ADDR_8023AZ_EEE_CTRL); - phy_data &= ~(QCA803X_PHY_EEE_ADV_100M | QCA803X_PHY_EEE_ADV_1000M); - - if (adv & FAL_PHY_EEE_100BASE_T) { - phy_data |= QCA803X_PHY_EEE_ADV_100M; - } - if (adv & FAL_PHY_EEE_1000BASE_T) { - phy_data |= QCA803X_PHY_EEE_ADV_1000M; - } - - rv = qca803x_phy_mmd_write(dev_id, phy_id, QCA803X_PHY_MMD7_NUM, - QCA803X_PHY_MMD7_ADDR_8023AZ_EEE_CTRL, phy_data); - - rv = qca803x_phy_restart_autoneg(dev_id, phy_id); - - return rv; -} - -/****************************************************************************** -* -* qca803x_phy_get_eee_advertisement -* -* get eee advertisement -*/ -sw_error_t -qca803x_phy_get_eee_adv(a_uint32_t dev_id, a_uint32_t phy_id, - a_uint32_t *adv) -{ - a_uint16_t phy_data = 0; - sw_error_t rv = SW_OK; - - *adv = 0; - phy_data = qca803x_phy_mmd_read(dev_id, phy_id, QCA803X_PHY_MMD7_NUM, - QCA803X_PHY_MMD7_ADDR_8023AZ_EEE_CTRL); - - if (phy_data & QCA803X_PHY_EEE_ADV_100M) { - *adv |= FAL_PHY_EEE_100BASE_T; - } - if (phy_data & QCA803X_PHY_EEE_ADV_1000M) { - *adv |= FAL_PHY_EEE_1000BASE_T; - } - - return rv; -} -/****************************************************************************** -* -* qca803x_phy_get_eee_partner_advertisement -* -* get eee partner advertisement -*/ -sw_error_t -qca803x_phy_get_eee_partner_adv(a_uint32_t dev_id, a_uint32_t phy_id, - a_uint32_t *adv) -{ - a_uint16_t phy_data = 0; - sw_error_t rv = SW_OK; - - *adv = 0; - phy_data = qca803x_phy_mmd_read(dev_id, phy_id, QCA803X_PHY_MMD7_NUM, - QCA803X_PHY_MMD7_ADDR_8023AZ_EEE_PARTNER); - - if (phy_data & QCA803X_PHY_EEE_PARTNER_ADV_100M) { - *adv |= FAL_PHY_EEE_100BASE_T; - } - if (phy_data & QCA803X_PHY_EEE_PARTNER_ADV_1000M) { - *adv |= FAL_PHY_EEE_1000BASE_T; - } - - return rv; -} -/****************************************************************************** -* -* qca803x_phy_get_eee_capability -* -* get eee capability -*/ -sw_error_t -qca803x_phy_get_eee_cap(a_uint32_t dev_id, a_uint32_t phy_id, - a_uint32_t *cap) -{ - a_uint16_t phy_data = 0; - sw_error_t rv = SW_OK; - - *cap = 0; - phy_data = qca803x_phy_mmd_read(dev_id, phy_id, QCA803X_PHY_MMD3_NUM, - QCA803X_PHY_MMD3_ADDR_8023AZ_EEE_CAPABILITY); - - if (phy_data & QCA803X_PHY_EEE_CAPABILITY_100M) { - *cap |= FAL_PHY_EEE_100BASE_T; - } - if (phy_data & QCA803X_PHY_EEE_CAPABILITY_1000M) { - *cap |= FAL_PHY_EEE_1000BASE_T; - } - - return rv; -} -/****************************************************************************** -* -* qca803x_phy_get_eee_status -* -* get eee status -*/ -sw_error_t -qca803x_phy_get_eee_status(a_uint32_t dev_id, a_uint32_t phy_id, - a_uint32_t *status) -{ - a_uint16_t phy_data = 0; - sw_error_t rv = SW_OK; - - *status = 0; - phy_data = qca803x_phy_mmd_read(dev_id, phy_id, QCA803X_PHY_MMD7_NUM, - QCA803X_PHY_MMD7_ADDR_8023AZ_EEE_STATUS); - - if (phy_data & QCA803X_PHY_EEE_STATUS_100M) { - *status |= FAL_PHY_EEE_100BASE_T; - } - if (phy_data & QCA803X_PHY_EEE_STATUS_1000M) { - *status |= FAL_PHY_EEE_1000BASE_T; - } - - return rv; -} - -static sw_error_t qca803x_phy_api_ops_init(void) -{ - sw_error_t ret = SW_OK; - hsl_phy_ops_t *qca803x_phy_api_ops = NULL; - - qca803x_phy_api_ops = kzalloc(sizeof(hsl_phy_ops_t), GFP_KERNEL); - if (qca803x_phy_api_ops == NULL) { - SSDK_ERROR("qca803x phy ops kzalloc failed!\n"); - return -ENOMEM; - } - - phy_api_ops_init(QCA803X_PHY_CHIP); - - qca803x_phy_api_ops->phy_speed_get = qca803x_phy_get_speed; - qca803x_phy_api_ops->phy_speed_set = qca803x_phy_set_speed; - qca803x_phy_api_ops->phy_duplex_get = qca803x_phy_get_duplex; - qca803x_phy_api_ops->phy_duplex_set = qca803x_phy_set_duplex; - qca803x_phy_api_ops->phy_autoneg_enable_set = qca803x_phy_enable_autoneg; - qca803x_phy_api_ops->phy_restart_autoneg = qca803x_phy_restart_autoneg; - qca803x_phy_api_ops->phy_autoneg_status_get = qca803x_phy_autoneg_status; - qca803x_phy_api_ops->phy_autoneg_adv_set = qca803x_phy_set_autoneg_adv; - qca803x_phy_api_ops->phy_autoneg_adv_get = qca803x_phy_get_autoneg_adv; - qca803x_phy_api_ops->phy_link_status_get = qca803x_phy_get_link_status; - qca803x_phy_api_ops->phy_reset = qca803x_phy_reset; -#ifndef IN_PORTCONTROL_MINI - qca803x_phy_api_ops->phy_powersave_set = qca803x_phy_set_powersave; - qca803x_phy_api_ops->phy_powersave_get = qca803x_phy_get_powersave; - qca803x_phy_api_ops->phy_cdt = qca803x_phy_cdt; - qca803x_phy_api_ops->phy_mdix_set = qca803x_phy_set_mdix; - qca803x_phy_api_ops->phy_mdix_get = qca803x_phy_get_mdix; - qca803x_phy_api_ops->phy_mdix_status_get = qca803x_phy_get_mdix_status; - qca803x_phy_api_ops->phy_local_loopback_set = qca803x_phy_set_local_loopback; - qca803x_phy_api_ops->phy_local_loopback_get = qca803x_phy_get_local_loopback; - qca803x_phy_api_ops->phy_remote_loopback_set = qca803x_phy_set_remote_loopback; - qca803x_phy_api_ops->phy_remote_loopback_get = qca803x_phy_get_remote_loopback; -#endif - qca803x_phy_api_ops->phy_reg_write = qca803x_phy_reg_write; - qca803x_phy_api_ops->phy_reg_read = qca803x_phy_reg_read; - qca803x_phy_api_ops->phy_debug_write = qca803x_phy_debug_write; - qca803x_phy_api_ops->phy_debug_read = qca803x_phy_debug_read; - qca803x_phy_api_ops->phy_mmd_write = qca803x_phy_mmd_write; - qca803x_phy_api_ops->phy_mmd_read = qca803x_phy_mmd_read; - qca803x_phy_api_ops->phy_id_get = qca803x_phy_get_phy_id; - qca803x_phy_api_ops->phy_power_off = qca803x_phy_poweroff; - qca803x_phy_api_ops->phy_power_on = qca803x_phy_poweron; -#ifndef IN_PORTCONTROL_MINI - qca803x_phy_api_ops->phy_8023az_set = qca803x_phy_set_8023az; - qca803x_phy_api_ops->phy_8023az_get = qca803x_phy_get_8023az; - qca803x_phy_api_ops->phy_hibernation_set = qca803x_phy_set_hibernate; - qca803x_phy_api_ops->phy_hibernation_get = qca803x_phy_get_hibernate; - qca803x_phy_api_ops->phy_magic_frame_mac_set = qca803x_phy_set_magic_frame_mac; - qca803x_phy_api_ops->phy_magic_frame_mac_get = qca803x_phy_get_magic_frame_mac; - qca803x_phy_api_ops->phy_wol_status_set = qca803x_phy_set_wol_status; - qca803x_phy_api_ops->phy_wol_status_get = qca803x_phy_get_wol_status; -#endif - qca803x_phy_api_ops->phy_interface_mode_set = qca803x_phy_interface_set_mode; - qca803x_phy_api_ops->phy_interface_mode_get = qca803x_phy_interface_get_mode; - qca803x_phy_api_ops->phy_interface_mode_status_get = qca803x_phy_interface_get_mode_status; -#ifndef IN_PORTCONTROL_MINI - qca803x_phy_api_ops->phy_intr_mask_set = qca803x_phy_set_intr_mask; - qca803x_phy_api_ops->phy_intr_mask_get = qca803x_phy_get_intr_mask; - qca803x_phy_api_ops->phy_intr_status_get = qca803x_phy_get_intr_status; - qca803x_phy_api_ops->phy_combo_prefer_medium_set = qca803x_phy_set_combo_prefer_medium; - qca803x_phy_api_ops->phy_combo_prefer_medium_get = qca803x_phy_get_combo_prefer_medium; - qca803x_phy_api_ops->phy_combo_medium_status_get = qca803x_phy_get_combo_current_medium_type; - qca803x_phy_api_ops->phy_combo_fiber_mode_set = qca803x_phy_set_combo_fiber_mode; - qca803x_phy_api_ops->phy_combo_fiber_mode_get = qca803x_phy_get_combo_fiber_mode; - qca803x_phy_api_ops->phy_counter_set = qca803x_phy_set_counter_status; - qca803x_phy_api_ops->phy_counter_get = qca803x_phy_get_counter_status; - qca803x_phy_api_ops->phy_counter_show = qca803x_phy_show_counter; -#endif - qca803x_phy_api_ops->phy_get_status = qca803x_phy_get_status; - qca803x_phy_api_ops->phy_eee_adv_set = qca803x_phy_set_eee_adv; - qca803x_phy_api_ops->phy_eee_adv_get = qca803x_phy_get_eee_adv; - qca803x_phy_api_ops->phy_eee_partner_adv_get = qca803x_phy_get_eee_partner_adv; - qca803x_phy_api_ops->phy_eee_cap_get = qca803x_phy_get_eee_cap; - qca803x_phy_api_ops->phy_eee_status_get = qca803x_phy_get_eee_status; - - ret = hsl_phy_api_ops_register(QCA803X_PHY_CHIP, qca803x_phy_api_ops); - - if (ret == SW_OK) - SSDK_INFO("qca probe qca803x phy driver succeeded!\n"); - else - SSDK_ERROR("qca probe qca803x phy driver failed! (code: %d)\n", ret); - - return ret; -} - -static sw_error_t -_qca803x_phy_set_combo_page_regs(a_uint32_t dev_id, a_uint32_t phy_id, - qca803x_phy_medium_t phy_medium) -{ - a_uint16_t phy_data; - - phy_data = qca803x_phy_reg_read(dev_id, phy_id, QCA803X_PHY_CHIP_CONFIG); - PHY_RTN_ON_READ_ERROR(phy_data); - - if (phy_medium == QCA803X_PHY_MEDIUM_FIBER) { - phy_data &= ~QCA803X_PHY_COPPER_PAGE_SEL; - } - else if (phy_medium == QCA803X_PHY_MEDIUM_COPPER) { - phy_data |= QCA803X_PHY_COPPER_PAGE_SEL; - } - else { - return SW_BAD_PARAM; - } - - qca803x_phy_reg_write(dev_id, phy_id, QCA803X_PHY_CHIP_CONFIG, phy_data); - - return SW_OK; -} - -void qca803x_combo_phy_polling(qca803x_priv_t *priv) -{ - - qca803x_cfg_t cfg_value; - a_uint32_t combo_phy_addr = 0; - a_uint32_t combo_bits = priv->combo_phy_bmp; - qca803x_phy_medium_t combo_cfg_new = QCA803X_PHY_MEDIUM_COPPER; - - while (combo_bits) { - if (combo_bits & 1) { - QCA803X_REG_LOCK; - __phy_chip_config_get(priv->dev_id, combo_phy_addr, - QCA803X_CHIP_CFG_STAT, &cfg_value); - - switch (cfg_value) { - case QCA803X_PHY_RGMII_BASET: - case QCA803X_PHY_SGMII_BASET: - combo_cfg_new = QCA803X_PHY_MEDIUM_COPPER; - break; - case QCA803X_PHY_BX1000_RGMII_50: - case QCA803X_PHY_FX100_RGMII_50: - combo_cfg_new = QCA803X_PHY_MEDIUM_FIBER; - break; - default: - combo_cfg_new = QCA803X_PHY_MEDIUM_COPPER; - } - - if (priv->combo_cfg[combo_phy_addr] != combo_cfg_new) { - priv->combo_cfg[combo_phy_addr] = combo_cfg_new; - _qca803x_phy_set_combo_page_regs(priv->dev_id, combo_phy_addr, combo_cfg_new); - } - - QCA803X_REG_UNLOCK; - } - combo_bits >>= 1; - combo_phy_addr++; - } -} - -void -qca803x_phy_polling_work(struct work_struct *work) -{ - qca803x_priv_t *priv = container_of(work, qca803x_priv_t, - phy_sync_dwork.work); - qca803x_combo_phy_polling(priv); - - schedule_delayed_work(&priv->phy_sync_dwork, - QCA803X_PHY_DELAYED_INIT_TICKS); -} - -sw_error_t -qca803x_phy_work_start(a_uint32_t dev_id) -{ - qca803x_priv_t *priv = &g_qca803x_phy; - priv->dev_id = dev_id; - - INIT_DELAYED_WORK(&priv->phy_sync_dwork, - qca803x_phy_polling_work); - schedule_delayed_work(&priv->phy_sync_dwork, - QCA803X_PHY_DELAYED_INIT_TICKS); - return SW_OK; -} - -/****************************************************************************** -* -* qca803x_phy_hw_init -* -*/ -sw_error_t -qca803x_phy_hw_init(a_uint32_t dev_id, a_uint32_t port_bmp) -{ - sw_error_t ret = SW_OK; - a_uint32_t port_id = 0, phy_addr = 0, mac_mode = 0; - a_uint16_t phy_data= 0; - - for (port_id = 0; port_id < SW_MAX_NR_PORT; port_id ++) - { - if (port_bmp & (0x1 << port_id)) - { - /*config phy mode based on the mac mode DT*/ - switch (port_id) { - case SSDK_PHYSICAL_PORT0: - mac_mode = ssdk_dt_global_get_mac_mode(dev_id, SSDK_UNIPHY_INSTANCE0); - break; - case SSDK_PHYSICAL_PORT6: - mac_mode = ssdk_dt_global_get_mac_mode(dev_id, SSDK_UNIPHY_INSTANCE2); - break; - default: - mac_mode = PORT_WRAPPER_MAX; - } - - phy_addr = qca_ssdk_port_to_phy_addr(dev_id, port_id); - if (mac_mode == PORT_WRAPPER_SGMII_CHANNEL0) - qca803x_phy_interface_set_mode(dev_id, phy_addr, PHY_SGMII_BASET); - else if (mac_mode == PORT_WRAPPER_RGMII) - qca803x_phy_interface_set_mode(dev_id, phy_addr, PORT_RGMII_BASET); - - if (A_TRUE == hsl_port_phy_combo_capability_get(dev_id, port_id)) { - g_qca803x_phy.combo_phy_bmp |= (0x1 << phy_addr); - qca803x_phy_interface_set_mode(dev_id, phy_addr, PORT_RGMII_AMDET); - } - /*config the times that MSE is over threshold as max*/ - phy_data = qca803x_phy_debug_read(dev_id, phy_addr, - QCA803X_DEBUG_MSE_OVER_THRESH_TIMES); - PHY_RTN_ON_READ_ERROR(phy_data); - ret = qca803x_phy_debug_write(dev_id, phy_addr, - QCA803X_DEBUG_MSE_OVER_THRESH_TIMES, phy_data | - QCA803X_PHY_MSE_OVER_THRESH_TIMES_MAX); - SW_RTN_ON_ERROR(ret); - } - } - - /* start polling task for the combo port */ - if (g_qca803x_phy.combo_phy_bmp) - qca803x_phy_work_start(dev_id); - - return ret; -} - -/****************************************************************************** -* -* qca803x_phy_init - -* -*/ -int qca803x_phy_init(a_uint32_t dev_id, a_uint32_t port_bmp) -{ - static a_uint32_t phy_ops_flag = 0; - - if(phy_ops_flag == 0) { - QCA803X_LOCKER_INIT; - qca803x_phy_api_ops_init(); - phy_ops_flag = 1; - } - - qca803x_phy_hw_init(dev_id, port_bmp); - return 0; -} diff --git a/feeds/ipq807x/qca-ssdk/src/src/hsl/phy/qca808x.c b/feeds/ipq807x/qca-ssdk/src/src/hsl/phy/qca808x.c deleted file mode 100755 index c1c7c15ba..000000000 --- a/feeds/ipq807x/qca-ssdk/src/src/hsl/phy/qca808x.c +++ /dev/null @@ -1,645 +0,0 @@ -/* - * Copyright (c) 2018-2019, 2021, The Linux Foundation. All rights reserved. - * Permission to use, copy, modify, and/or distribute this software for - * any purpose with or without fee is hereby granted, provided that the - * above copyright notice and this permission notice appear in all copies. - * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES - * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR - * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES - * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN - * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT - * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. - */ - -#include "qca808x.h" - -#if defined(IN_PHY_I2C_MODE) -#include "sfp_phy.h" -#endif - -#define PHY_INVALID_DATA 0xffff -#define QCA808X_INTR_INIT 0xec00 - -#define QCA808X_PHY_LINK_UP 1 -#define QCA808X_PHY_LINK_DOWN 0 - -LIST_HEAD(g_qca808x_phy_list); - -struct qca808x_phy_info* qca808x_phy_info_get(a_uint32_t phy_addr) -{ - struct qca808x_phy_info *pdata = NULL; - list_for_each_entry(pdata, &g_qca808x_phy_list, list) { - if (pdata->phydev_addr == phy_addr) { - return pdata; - } - } - - SSDK_ERROR("%s can't get the data for phy addr: %d\n", __func__, phy_addr); - return NULL; -} - -static a_bool_t qca808x_sfp_present(struct phy_device *phydev) -{ - qca808x_priv *priv = phydev->priv; - struct qca808x_phy_info *pdata = priv->phy_info; - a_uint32_t phy_id = 0; - sw_error_t rv = SW_OK; - - if (!pdata) { - SSDK_ERROR("pdata is null\n"); - return A_FALSE; - } - rv = qca808x_phy_get_phy_id(pdata->dev_id, pdata->phy_addr, &phy_id); - if(rv == SW_READ_ERROR) { - return A_FALSE; - } - - return A_TRUE; -} - -static sw_error_t qca808x_phy_config_init(struct phy_device *phydev) -{ - a_uint16_t phy_data; -#if (LINUX_VERSION_CODE < KERNEL_VERSION(5, 0, 0)) - a_uint32_t features; -#else - __ETHTOOL_DECLARE_LINK_MODE_MASK(mask) = { 0, }; -#endif - a_uint32_t dev_id = 0, phy_id = 0; - qca808x_priv *priv = phydev->priv; - struct qca808x_phy_info *pdata = priv->phy_info; - - if (!pdata) { - return SW_NOT_FOUND; - } - - dev_id = pdata->dev_id; - phy_id = pdata->phy_addr; - -#if (LINUX_VERSION_CODE < KERNEL_VERSION(5, 0, 0)) - features = SUPPORTED_TP | SUPPORTED_MII | - SUPPORTED_AUI | SUPPORTED_BNC; -#else - linkmode_set_bit(ETHTOOL_LINK_MODE_TP_BIT, mask); - linkmode_set_bit(ETHTOOL_LINK_MODE_MII_BIT, mask); - linkmode_set_bit(ETHTOOL_LINK_MODE_AUI_BIT, mask); - linkmode_set_bit(ETHTOOL_LINK_MODE_BNC_BIT, mask); -#endif - - phy_data = qca808x_phy_reg_read(dev_id, - phy_id, QCA808X_PHY_STATUS); - - if (phy_data == PHY_INVALID_DATA) { - return SW_READ_ERROR; - } - - if (phy_data & QCA808X_STATUS_AUTONEG_CAPS) { -#if (LINUX_VERSION_CODE < KERNEL_VERSION(5, 0, 0)) - features |= SUPPORTED_Autoneg; -#else - linkmode_set_bit(ETHTOOL_LINK_MODE_Autoneg_BIT, mask); -#endif - } - if (phy_data & QCA808X_STATUS_100TX_FD_CAPS) { -#if (LINUX_VERSION_CODE < KERNEL_VERSION(5, 0, 0)) - features |= SUPPORTED_100baseT_Full; -#else - linkmode_set_bit(ETHTOOL_LINK_MODE_100baseT_Full_BIT, mask); -#endif - } - if (phy_data & QCA808X_STATUS_100TX_HD_CAPS) { -#if (LINUX_VERSION_CODE < KERNEL_VERSION(5, 0, 0)) - features |= SUPPORTED_100baseT_Half; -#else - linkmode_set_bit(ETHTOOL_LINK_MODE_100baseT_Half_BIT, mask); -#endif - } - if (phy_data & QCA808X_STATUS_10T_FD_CAPS) { -#if (LINUX_VERSION_CODE < KERNEL_VERSION(5, 0, 0)) - features |= SUPPORTED_10baseT_Full; -#else - linkmode_set_bit(ETHTOOL_LINK_MODE_10baseT_Full_BIT, mask); -#endif - } - if (phy_data & QCA808X_STATUS_10T_HD_CAPS) { -#if (LINUX_VERSION_CODE < KERNEL_VERSION(5, 0, 0)) - features |= SUPPORTED_10baseT_Half; -#else - linkmode_set_bit(ETHTOOL_LINK_MODE_10baseT_Half_BIT, mask); -#endif - } - - if (phy_data & QCA808X_STATUS_EXTENDED_STATUS) { - phy_data = qca808x_phy_reg_read(dev_id, - phy_id, QCA808X_EXTENDED_STATUS); - - if (phy_data == PHY_INVALID_DATA) { - return SW_READ_ERROR; - } - if (phy_data & QCA808X_STATUS_1000T_FD_CAPS) { -#if (LINUX_VERSION_CODE < KERNEL_VERSION(5, 0, 0)) - features |= SUPPORTED_1000baseT_Full; -#else - linkmode_set_bit(ETHTOOL_LINK_MODE_1000baseT_Full_BIT, - mask); -#endif - } - if (phy_data & QCA808X_STATUS_1000T_HD_CAPS) { -#if (LINUX_VERSION_CODE < KERNEL_VERSION(5, 0, 0)) - features |= SUPPORTED_1000baseT_Half; -#else - linkmode_set_bit(ETHTOOL_LINK_MODE_1000baseT_Half_BIT, - mask); -#endif - } - } - - phy_data = qca808x_phy_mmd_read(dev_id, phy_id, QCA808X_PHY_MMD1_NUM, - QCA808X_MMD1_PMA_CAP_REG); - - if (phy_data & QCA808X_STATUS_2500T_FD_CAPS) { -#if (LINUX_VERSION_CODE < KERNEL_VERSION(5, 0, 0)) - features |= SUPPORTED_2500baseX_Full; -#else - linkmode_set_bit(ETHTOOL_LINK_MODE_2500baseT_Full_BIT, mask); -#endif - } - -#if (LINUX_VERSION_CODE < KERNEL_VERSION(5, 0, 0)) - phydev->supported = features; - phydev->advertising = features; -#else - linkmode_copy(phydev->supported, mask); - linkmode_copy(phydev->advertising, mask); -#endif - - return SW_OK; -} - -static a_bool_t qca808x_config_init_done = A_FALSE; -static int _qca808x_config_init(struct phy_device *phydev) -{ - int ret = 0; -#if defined(IN_LINUX_STD_PTP) - /* ptp function initialization */ - ret |= qca808x_ptp_config_init(phydev); -#endif - - ret |= qca808x_phy_config_init(phydev); - - return ret; -} - -static int qca808x_config_init(struct phy_device *phydev) -{ - int ret = 0; - - if(!qca808x_sfp_present(phydev)) - { - return 0; - } - ret = _qca808x_config_init(phydev); - if(!ret) - { - qca808x_config_init_done = A_TRUE; - } - - return ret; -} - -static int qca808x_config_intr(struct phy_device *phydev) -{ - int err; - a_uint16_t phy_data; - a_uint32_t dev_id = 0, phy_id = 0; - qca808x_priv *priv = phydev->priv; - const struct qca808x_phy_info *pdata = priv->phy_info; - - if (!pdata) { - return SW_FAIL; - } - - dev_id = pdata->dev_id; - phy_id = pdata->phy_addr; - - phy_data = qca808x_phy_reg_read(dev_id, phy_id, - QCA808X_PHY_INTR_MASK); - - if (phydev->interrupts == PHY_INTERRUPT_ENABLED) { - err = qca808x_phy_reg_write(dev_id, phy_id, - QCA808X_PHY_INTR_MASK, - phy_data | QCA808X_INTR_INIT); - } else { - err = qca808x_phy_reg_write(dev_id, phy_id, - QCA808X_PHY_INTR_MASK, 0); - } - - return err; -} - -static int qca808x_ack_interrupt(struct phy_device *phydev) -{ - int err; - a_uint32_t dev_id = 0, phy_id = 0; - qca808x_priv *priv = phydev->priv; - const struct qca808x_phy_info *pdata = priv->phy_info; - - if (!pdata) { - return SW_FAIL; - } - - dev_id = pdata->dev_id; - phy_id = pdata->phy_addr; - - err = qca808x_phy_reg_read(dev_id, phy_id, - QCA808X_PHY_INTR_STATUS); - - return (err < 0) ? err : 0; -} - -/* switch linux negtiation capability to fal avariable */ -#if (LINUX_VERSION_CODE < KERNEL_VERSION(5, 0, 0)) -static a_uint32_t qca808x_negtiation_cap_get(struct phy_device *phydev) -{ - a_uint32_t autoneg = 0; - a_uint32_t advertise = phydev->advertising & phydev->supported; - - if (advertise & ADVERTISED_Pause) { - autoneg |= FAL_PHY_ADV_PAUSE; - } - if (advertise & ADVERTISED_Asym_Pause) { - autoneg |= FAL_PHY_ADV_ASY_PAUSE; - } - if (advertise & ADVERTISED_10baseT_Half) { - autoneg |= FAL_PHY_ADV_10T_HD; - } - if (advertise & ADVERTISED_10baseT_Full) { - autoneg |= FAL_PHY_ADV_10T_FD; - } - if (advertise & ADVERTISED_100baseT_Half) { - autoneg |= FAL_PHY_ADV_100TX_HD; - } - if (advertise & ADVERTISED_100baseT_Full) { - autoneg |= FAL_PHY_ADV_100TX_FD; - } - if (advertise & ADVERTISED_1000baseT_Full) { - autoneg |= FAL_PHY_ADV_1000T_FD; - } - if (advertise & ADVERTISED_2500baseX_Full) { - autoneg |= FAL_PHY_ADV_2500T_FD; - } - - return autoneg; -} -#else -static a_uint32_t qca808x_negtiation_cap_get(struct phy_device *phydev) -{ - a_uint32_t autoneg = 0; - __ETHTOOL_DECLARE_LINK_MODE_MASK(advertising) = { 0, }; - - linkmode_and(advertising, phydev->advertising, phydev->supported); - - if (linkmode_test_bit(ETHTOOL_LINK_MODE_Pause_BIT, advertising)) { - autoneg |= FAL_PHY_ADV_PAUSE; - } - if (linkmode_test_bit(ETHTOOL_LINK_MODE_Asym_Pause_BIT, advertising)) { - autoneg |= FAL_PHY_ADV_ASY_PAUSE; - } - if (linkmode_test_bit(ETHTOOL_LINK_MODE_10baseT_Half_BIT, advertising)) { - autoneg |= FAL_PHY_ADV_10T_HD; - } - if (linkmode_test_bit(ETHTOOL_LINK_MODE_10baseT_Full_BIT, advertising)) { - autoneg |= FAL_PHY_ADV_10T_FD; - } - if (linkmode_test_bit(ETHTOOL_LINK_MODE_100baseT_Half_BIT, advertising)) { - autoneg |= FAL_PHY_ADV_100TX_HD; - } - if (linkmode_test_bit(ETHTOOL_LINK_MODE_100baseT_Full_BIT, advertising)) { - autoneg |= FAL_PHY_ADV_100TX_FD; - } - if (linkmode_test_bit(ETHTOOL_LINK_MODE_1000baseT_Full_BIT, advertising)) { - autoneg |= FAL_PHY_ADV_1000T_FD; - } - if (linkmode_test_bit(ETHTOOL_LINK_MODE_2500baseT_Full_BIT, advertising)) { - autoneg |= FAL_PHY_ADV_2500T_FD; - } - - return autoneg; -} -#endif - -static int qca808x_config_aneg(struct phy_device *phydev) -{ - a_uint32_t advertise = 0; - a_uint16_t phy_data = 0; - int err = 0; - a_uint32_t dev_id = 0, phy_id = 0; - qca808x_priv *priv = phydev->priv; - const struct qca808x_phy_info *pdata = priv->phy_info; - - if(!qca808x_sfp_present(phydev)) - { - return 0; - } - - if (!pdata) { - return SW_FAIL; - } - - dev_id = pdata->dev_id; - phy_id = pdata->phy_addr; - if (phydev->autoneg != AUTONEG_ENABLE) - { - /* force speed */ - phydev->pause = 0; - phydev->asym_pause = 0; - - phy_data = qca808x_phy_reg_read(dev_id, phy_id, QCA808X_PHY_CONTROL); - phy_data &= ~QCA808X_CTRL_AUTONEGOTIATION_ENABLE; - if (phydev->duplex == FAL_FULL_DUPLEX) { - phy_data |= QCA808X_CTRL_FULL_DUPLEX; - } else { - phy_data &= ~QCA808X_CTRL_FULL_DUPLEX; - } - qca808x_phy_reg_write(dev_id, phy_id, QCA808X_PHY_CONTROL, phy_data); - err = qca808x_phy_set_force_speed(dev_id, phy_id, phydev->speed); - } else { - /* autoneg enabled */ - advertise = qca808x_negtiation_cap_get(phydev); - err |= qca808x_phy_set_autoneg_adv(dev_id, phy_id, advertise); - err |= qca808x_phy_restart_autoneg(dev_id, phy_id); - } - - return err; -} - -static int qca808x_aneg_done(struct phy_device *phydev) -{ - - a_uint16_t phy_data; - a_uint32_t dev_id = 0, phy_id = 0; - qca808x_priv *priv = phydev->priv; - const struct qca808x_phy_info *pdata = priv->phy_info; - - if (!pdata) { - return SW_FAIL; - } - - dev_id = pdata->dev_id; - phy_id = pdata->phy_addr; - - phy_data = qca808x_phy_reg_read(dev_id, phy_id, - QCA808X_PHY_STATUS); - - return (phy_data < 0) ? phy_data : (phy_data & QCA808X_STATUS_AUTO_NEG_DONE); -} - -static int qca808x_read_status(struct phy_device *phydev) -{ - struct port_phy_status phy_status = {0}; - a_uint32_t dev_id = 0, phy_id = 0; - qca808x_priv *priv = phydev->priv; - const struct qca808x_phy_info *pdata = priv->phy_info; - - if(!qca808x_config_init_done) - { - if(!_qca808x_config_init(phydev)) - { - qca808x_config_init_done = A_TRUE; - } - } - - if (!pdata) { - return SW_FAIL; - } - - dev_id = pdata->dev_id; - phy_id = pdata->phy_addr; - - qca808x_phy_get_status(dev_id, phy_id, &phy_status); - - if (phy_status.link_status) { - phydev->link = QCA808X_PHY_LINK_UP; - } else { - phydev->link = QCA808X_PHY_LINK_DOWN; - } - - switch (phy_status.speed) { - case FAL_SPEED_2500: - phydev->speed = SPEED_2500; - break; - case FAL_SPEED_1000: - phydev->speed = SPEED_1000; - break; - case FAL_SPEED_100: - phydev->speed = SPEED_100; - break; - default: - phydev->speed = SPEED_10; - break; - } - - if (phy_status.duplex == FAL_FULL_DUPLEX) { - phydev->duplex = DUPLEX_FULL; - } else { - phydev->duplex = DUPLEX_HALF; - } - - return 0; -} - -static int qca808x_suspend(struct phy_device *phydev) -{ - a_uint32_t dev_id = 0, phy_id = 0; - qca808x_priv *priv = phydev->priv; - const struct qca808x_phy_info *pdata = priv->phy_info; - - if (!pdata) { - return SW_FAIL; - } - - dev_id = pdata->dev_id; - phy_id = pdata->phy_addr; - - return qca808x_phy_poweroff(dev_id, phy_id); -} - -static int qca808x_resume(struct phy_device *phydev) -{ - a_uint32_t dev_id = 0, phy_id = 0; - qca808x_priv *priv = phydev->priv; - const struct qca808x_phy_info *pdata = priv->phy_info; - - if (!pdata) { - return SW_FAIL; - } - - dev_id = pdata->dev_id; - phy_id = pdata->phy_addr; - - return qca808x_phy_poweron(dev_id, phy_id); -} - -#if (LINUX_VERSION_CODE >= KERNEL_VERSION(4,4,0)) -static int qca808x_soft_reset(struct phy_device *phydev) -{ - a_uint32_t dev_id = 0, phy_id = 0; - qca808x_priv *priv = phydev->priv; - const struct qca808x_phy_info *pdata = priv->phy_info; - - if(!qca808x_sfp_present(phydev)) { - return 0; - } - - if (!pdata) { - return SW_FAIL; - } - - dev_id = pdata->dev_id; - phy_id = pdata->phy_addr; - - return qca808x_phy_reset(dev_id, phy_id); -} - -static void qca808x_link_change_notify(struct phy_device *phydev) -{ -#if defined(IN_LINUX_STD_PTP) - qca808x_ptp_change_notify(phydev); -#endif -} -#endif - -static int qca808x_phy_probe(struct phy_device *phydev) -{ - qca808x_priv *priv; - int err = 0; - - priv = kzalloc(sizeof(qca808x_priv), GFP_KERNEL); - if (!priv) { - return -ENOMEM; - } - - priv->phydev = phydev; -#if (LINUX_VERSION_CODE < KERNEL_VERSION(4, 9, 0)) - priv->phy_info = qca808x_phy_info_get(phydev->addr); -#else - priv->phy_info = qca808x_phy_info_get(phydev->mdio.addr); -#endif - phydev->priv = priv; - -#if defined(IN_LINUX_STD_PTP) - err = qca808x_ptp_init(priv); -#endif - - return err; -} - -static void qca808x_phy_remove(struct phy_device *phydev) -{ - qca808x_priv *priv = phydev->priv; - -#if defined(IN_LINUX_STD_PTP) - qca808x_ptp_deinit(priv); -#endif - kfree(priv); -} - -struct phy_driver qca808x_phy_driver = { - .phy_id = QCA8081_PHY_V1_1, - .phy_id_mask = 0xffffffff, - .name = "QCA808X ethernet", - .features = PHY_GBIT_FEATURES, -#if (LINUX_VERSION_CODE < KERNEL_VERSION(5, 0, 0)) - .flags = PHY_HAS_INTERRUPT, -#endif - .probe = qca808x_phy_probe, - .remove = qca808x_phy_remove, - .config_init = qca808x_config_init, - .config_intr = qca808x_config_intr, - .config_aneg = qca808x_config_aneg, - .aneg_done = qca808x_aneg_done, - .ack_interrupt = qca808x_ack_interrupt, - .read_status = qca808x_read_status, - .suspend = qca808x_suspend, - .resume = qca808x_resume, -#if (LINUX_VERSION_CODE >= KERNEL_VERSION(4,4,0)) - .soft_reset = qca808x_soft_reset, - .link_change_notify = qca808x_link_change_notify, -#endif -#if defined(IN_LINUX_STD_PTP) -#if (LINUX_VERSION_CODE >= KERNEL_VERSION(4,4,0)) - .ts_info = qca808x_ts_info, -#endif - .hwtstamp = qca808x_hwtstamp, - .rxtstamp = qca808x_rxtstamp, - .txtstamp = qca808x_txtstamp, -#endif -#if (LINUX_VERSION_CODE >= KERNEL_VERSION(4,9,0)) - .mdiodrv.driver = { .owner = THIS_MODULE }, -#else - .driver = { .owner = THIS_MODULE }, -#endif -}; - -a_int32_t qca808x_phy_driver_register(void) -{ - a_int32_t ret; -#if (LINUX_VERSION_CODE >= KERNEL_VERSION(4,9,0)) - ret = phy_driver_register(&qca808x_phy_driver, THIS_MODULE); -#else - ret = phy_driver_register(&qca808x_phy_driver); -#endif - return ret; -} - -void qca808x_phy_driver_unregister(void) -{ - phy_driver_unregister(&qca808x_phy_driver); -} - -void qca808x_phydev_init(a_uint32_t dev_id, a_uint32_t port_id) -{ - struct qca808x_phy_info *pdata; - pdata = kzalloc(sizeof(struct qca808x_phy_info), GFP_KERNEL); - - if (!pdata) { - return; - } - list_add_tail(&pdata->list, &g_qca808x_phy_list); - pdata->dev_id = dev_id; - /* the phy address may be the i2c slave addr or mdio addr */ - pdata->phy_addr = qca_ssdk_port_to_phy_addr(dev_id, port_id); - pdata->phydev_addr = pdata->phy_addr; -#if defined(IN_PHY_I2C_MODE) - /* in i2c mode, need to register a fake phy device - * before the phy driver register */ - if (hsl_port_phy_access_type_get(dev_id, port_id) == PHY_I2C_ACCESS) { - a_uint32_t phy_id = QCA8081_PHY_V1_1; - qca808x_phy_get_phy_id(dev_id, pdata->phy_addr, &phy_id); - if(phy_id != QCA8081_PHY_V1_1 && phy_id != INVALID_PHY_ID) { - SSDK_ERROR("phy id 0x%x is not supported\n", phy_id); - return; - } - pdata->phydev_addr = qca_ssdk_port_to_phy_mdio_fake_addr(dev_id, port_id); - sfp_phy_device_setup(dev_id, port_id, phy_id); - } -#endif -} - -void qca808x_phydev_deinit(a_uint32_t dev_id, a_uint32_t port_id) -{ - struct qca808x_phy_info *pdata, *pnext; - -#if defined(IN_PHY_I2C_MODE) - /* in i2c mode, need to remove the fake phy device - * after the phy driver unregistered */ - if (hsl_port_phy_access_type_get(dev_id, port_id) == PHY_I2C_ACCESS) { - sfp_phy_device_remove(dev_id, port_id); - } -#endif - list_for_each_entry_safe(pdata, pnext, &g_qca808x_phy_list, list) { - list_del(&pdata->list); - kfree(pdata); - } -} diff --git a/feeds/ipq807x/qca-ssdk/src/src/hsl/phy/qca808x_led.c b/feeds/ipq807x/qca-ssdk/src/src/hsl/phy/qca808x_led.c deleted file mode 100644 index 7abca48bc..000000000 --- a/feeds/ipq807x/qca-ssdk/src/src/hsl/phy/qca808x_led.c +++ /dev/null @@ -1,272 +0,0 @@ -/* - * Copyright (c) 2020, The Linux Foundation. All rights reserved. - * - * Permission to use, copy, modify, and/or distribute this software for any - * purpose with or without fee is hereby granted, provided that the above - * copyright notice and this permission notice appear in all copies. - * - * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES - * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR - * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES - * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN - * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF - * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. - */ - -#include "sw.h" -#include "hsl_phy.h" -#include "ssdk_plat.h" -#include "qca808x_phy.h" -#include "qca808x_led.h" - -static sw_error_t -_qca808x_phy_led_active_set(a_uint32_t dev_id, a_uint32_t phy_id, - led_ctrl_pattern_t *pattern) -{ - sw_error_t rv = SW_OK; - a_uint16_t phy_data = 0; - - phy_data= qca808x_phy_mmd_read(dev_id, phy_id, QCA808X_PHY_MMD7_NUM, - QCA808X_PHY_MMD7_LED_POLARITY_CTRL); - PHY_RTN_ON_READ_ERROR(phy_data); - if(pattern->map & BIT(LED_ACTIVE_HIGH)) - { - phy_data |= QCA808X_PHY_MMD7_LED_POLARITY_MASK; - } - else - { - phy_data &= ~QCA808X_PHY_MMD7_LED_POLARITY_MASK; - } - rv = qca808x_phy_mmd_write(dev_id, phy_id, QCA808X_PHY_MMD7_NUM, - QCA808X_PHY_MMD7_LED_POLARITY_CTRL, phy_data); - - return rv; -} - -static sw_error_t -_qca808x_phy_led_active_get(a_uint32_t dev_id, a_uint32_t phy_id, - led_ctrl_pattern_t *pattern) -{ - a_uint16_t phy_data = 0; - - phy_data = qca808x_phy_mmd_read(dev_id, phy_id, QCA808X_PHY_MMD7_NUM, - QCA808X_PHY_MMD7_LED_POLARITY_CTRL); - PHY_RTN_ON_READ_ERROR(phy_data); - if(phy_data & QCA808X_PHY_MMD7_LED_POLARITY_MASK) - { - pattern->map |= BIT(LED_ACTIVE_HIGH); - } - - return SW_OK; -} - -static sw_error_t -_qca808x_phy_led_pattern_map_from_phy(a_uint32_t dev_id, a_uint32_t phy_id, - led_ctrl_pattern_t *pattern, a_uint16_t *phy_data) -{ - if (qca808x_phy_2500caps(dev_id, phy_id) == A_TRUE) - { - if(*phy_data & QCA808X_PHY_LINK_2500M_LIGHT_EN) - { - pattern->map |= BIT(LINK_2500M_LIGHT_EN); - } - } - if(*phy_data & QCA808X_PHY_LINK_1000M_LIGHT_EN) - { - pattern->map |= BIT(LINK_1000M_LIGHT_EN); - } - if(*phy_data & QCA808X_PHY_LINK_100M_LIGHT_EN) - { - pattern->map |= BIT(LINK_100M_LIGHT_EN); - } - if(*phy_data & QCA808X_PHY_LINK_10M_LIGHT_EN) - { - pattern->map |= BIT(LINK_10M_LIGHT_EN); - } - if (*phy_data & QCA808X_PHY_RX_TRAFFIC_BLINK_EN) - { - pattern->map |= BIT(RX_TRAFFIC_BLINK_EN); - } - if (*phy_data & QCA808X_PHY_TX_TRAFFIC_BLINK_EN) - { - pattern->map |= BIT(TX_TRAFFIC_BLINK_EN); - } - - return SW_OK; -} - -static sw_error_t -_qca808x_phy_led_pattern_map_to_phy(a_uint32_t dev_id, a_uint32_t phy_id, - led_ctrl_pattern_t *pattern, a_uint32_t *led_map) -{ - if (qca808x_phy_2500caps(dev_id, phy_id) == A_TRUE) - { - if (pattern->map & BIT(LINK_2500M_LIGHT_EN)) - { - *led_map |= QCA808X_PHY_LINK_2500M_LIGHT_EN; - } - } - if (pattern->map & BIT(LINK_1000M_LIGHT_EN)) - { - *led_map |= QCA808X_PHY_LINK_1000M_LIGHT_EN; - } - if (pattern->map & BIT(LINK_100M_LIGHT_EN)) - { - *led_map |= QCA808X_PHY_LINK_100M_LIGHT_EN; - } - if (pattern->map & BIT(LINK_10M_LIGHT_EN)) - { - *led_map |= QCA808X_PHY_LINK_10M_LIGHT_EN; - } - if (pattern->map & BIT(RX_TRAFFIC_BLINK_EN)) - { - *led_map |= QCA808X_PHY_RX_TRAFFIC_BLINK_EN; - } - if (pattern->map & BIT(TX_TRAFFIC_BLINK_EN)) - { - *led_map |= QCA808X_PHY_TX_TRAFFIC_BLINK_EN; - } - - return SW_OK; -} - -/****************************************************************************** -* -* qca808x_phy_led_ctrl_pattern_set -* -*/ -sw_error_t -qca808x_phy_led_ctrl_pattern_set(a_uint32_t dev_id, a_uint32_t phy_id, - led_ctrl_pattern_t *pattern) -{ - sw_error_t rv = SW_OK; - a_uint32_t source_id = 0; - - if(LED_PATTERN_MAP_EN != pattern->mode) - { - SSDK_ERROR("led mode %d is not supported\n", pattern->mode); - return SW_NOT_SUPPORTED; - } - for(source_id = QCA808X_PHY_LED_SOURCE0; source_id <= QCA808X_PHY_LED_SOURCE2; - source_id++) - { - /*three source use the same pattern*/ - rv = qca808x_phy_led_ctrl_source_set (dev_id, phy_id, source_id, pattern); - SW_RTN_ON_ERROR(rv); - } - - return rv; -} - -/****************************************************************************** -* -* qca808x_phy_led_ctrl_pattern_get -* -*/ -sw_error_t -qca808x_phy_led_ctrl_pattern_get(a_uint32_t dev_id, a_uint32_t phy_id, - led_ctrl_pattern_t *pattern) -{ - sw_error_t rv = SW_OK; - - /*three source use the same pattern*/ - rv = qca808x_phy_led_ctrl_source_get(dev_id, phy_id, QCA808X_PHY_LED_SOURCE0, - pattern); - - return rv; -} - -/****************************************************************************** -* -* qca808x_phy_led_source_pattern_set -* -*/ -sw_error_t -qca808x_phy_led_ctrl_source_set(a_uint32_t dev_id, a_uint32_t phy_id, - a_uint32_t source_id, led_ctrl_pattern_t *pattern) -{ - sw_error_t rv = SW_OK; - a_uint32_t led_map = 0; - a_uint16_t led_mmd_addr = 0; - - if(LED_PATTERN_MAP_EN != pattern->mode) - { - return SW_NOT_SUPPORTED; - } - - rv = _qca808x_phy_led_active_set(dev_id, phy_id, pattern); - SW_RTN_ON_ERROR(rv); - rv = _qca808x_phy_led_pattern_map_to_phy(dev_id, phy_id, pattern, &led_map); - SW_RTN_ON_ERROR(rv); - switch(source_id) - { - case QCA808X_PHY_LED_SOURCE0: - led_mmd_addr = QCA808X_PHY_MMD7_LED0_CTRL; - break; - case QCA808X_PHY_LED_SOURCE1: - led_mmd_addr = QCA808X_PHY_MMD7_LED1_CTRL; - break; - case QCA808X_PHY_LED_SOURCE2: - led_mmd_addr = QCA808X_PHY_MMD7_LED2_CTRL; - break; - default: - SSDK_ERROR("source %d is not support\n", source_id); - break; - } - rv = qca808x_phy_mmd_write(dev_id, phy_id, QCA808X_PHY_MMD7_NUM, - led_mmd_addr, led_map); - - return rv; -} -/****************************************************************************** -* -* qca808x_phy_led_source_pattern_get -* -*/ -sw_error_t -qca808x_phy_led_ctrl_source_get(a_uint32_t dev_id, a_uint32_t phy_id, - a_uint32_t source_id, led_ctrl_pattern_t *pattern) -{ - sw_error_t rv = SW_OK; - a_uint16_t phy_data = 0, led_mmd_addr = 0; - - pattern->map = 0; - pattern->mode = LED_PATTERN_MAP_EN; - rv = _qca808x_phy_led_active_get(dev_id, phy_id, pattern); - SW_RTN_ON_ERROR(rv); - switch(source_id) - { - case QCA808X_PHY_LED_SOURCE0: - led_mmd_addr = QCA808X_PHY_MMD7_LED0_CTRL; - break; - case QCA808X_PHY_LED_SOURCE1: - led_mmd_addr = QCA808X_PHY_MMD7_LED1_CTRL; - break; - case QCA808X_PHY_LED_SOURCE2: - led_mmd_addr = QCA808X_PHY_MMD7_LED2_CTRL; - break; - default: - SSDK_ERROR("source %d is not support\n", source_id); - break; - } - phy_data = qca808x_phy_mmd_read(dev_id, phy_id, QCA808X_PHY_MMD7_NUM, - led_mmd_addr); - PHY_RTN_ON_READ_ERROR(phy_data); - rv = _qca808x_phy_led_pattern_map_from_phy(dev_id, phy_id, pattern, - &phy_data); - - return rv; -} - -void qca808x_phy_led_api_ops_init(hsl_phy_ops_t *qca808x_phy_led_api_ops) -{ - if (!qca808x_phy_led_api_ops) { - return; - } - qca808x_phy_led_api_ops->phy_led_ctrl_pattern_get = qca808x_phy_led_ctrl_pattern_get; - qca808x_phy_led_api_ops->phy_led_ctrl_pattern_set = qca808x_phy_led_ctrl_pattern_set; - qca808x_phy_led_api_ops->phy_led_ctrl_source_set = qca808x_phy_led_ctrl_source_set; - - return; -} diff --git a/feeds/ipq807x/qca-ssdk/src/src/hsl/phy/qca808x_phc.c b/feeds/ipq807x/qca-ssdk/src/src/hsl/phy/qca808x_phc.c deleted file mode 100755 index 648ffaa95..000000000 --- a/feeds/ipq807x/qca-ssdk/src/src/hsl/phy/qca808x_phc.c +++ /dev/null @@ -1,1472 +0,0 @@ -/* - * Copyright (c) 2018, The Linux Foundation. All rights reserved. - * Permission to use, copy, modify, and/or distribute this software for - * any purpose with or without fee is hereby granted, provided that the - * above copyright notice and this permission notice appear in all copies. - * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES - * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR - * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES - * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN - * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT - * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. - */ - -#include -#include -#include - -#include "qca808x.h" - -#if (LINUX_VERSION_CODE >= KERNEL_VERSION(4,4,0)) -#include -#else -#include -#define ns_to_timespec64 ns_to_timespec -#define timespec64_to_ns timespec_to_ns -#define timespec64 timespec -#endif - -#include "qca808x_ptp.h" -#include "qca808x_ptp_reg.h" -#include "qca808x_ptp_api.h" - -#define QCA808X_PTP_EMBEDDED_MODE 0xa - -#define QCA808X_PTP_INCVAL_SYNC_MODE 0x8 -#define QCA808X_PTP_TICK_RATE_125M 8 -#define QCA808X_PTP_TICK_RATE_200M 5 - -#define PTP_HDR_RESERVED0_OFFSET 1 -#define PTP_HDR_RESERVED1_OFFSET 5 -#define PTP_HDR_CORRECTIONFIELD_OFFSET 8 -#define PTP_HDR_RESERVED2_OFFSET 16 - -#define SKB_TIMESTAMP_TIMEOUT 1 /* jiffies */ -#define GPS_WORK_TIMEOUT HZ - -#define HWTSTAMP_TX_ONESTEP_P2P (HWTSTAMP_TX_ONESTEP_SYNC + 1) - -extern struct list_head g_qca808x_phy_list; -void qca808x_ptp_gm_gps_seconds_sync_enable(a_uint32_t dev_id, - a_uint32_t phy_addr, a_bool_t en) -{ - struct qca808x_phy_info *pdata; -#if defined(IN_PHY_I2C_MODE) - a_uint32_t port_id; - port_id = qca_ssdk_phy_addr_to_port(dev_id, phy_addr); - if (hsl_port_phy_access_type_get(dev_id, port_id) == PHY_I2C_ACCESS) { - phy_addr = qca_ssdk_port_to_phy_mdio_fake_addr(dev_id, port_id); - } -#endif - - pdata = qca808x_phy_info_get(phy_addr); - if (pdata) { - pdata->gps_seconds_sync_en = en; - } - - if (en == A_TRUE) { - schedule_delayed_work(&pdata->ts_schedule_work, GPS_WORK_TIMEOUT); - } - - return; -} - -a_bool_t qca808x_ptp_gm_gps_seconds_sync_status_get(a_uint32_t dev_id, - a_uint32_t phy_addr) -{ - struct qca808x_phy_info *pdata; -#if defined(IN_PHY_I2C_MODE) - a_uint32_t port_id; - port_id = qca_ssdk_phy_addr_to_port(dev_id, phy_addr); - if (hsl_port_phy_access_type_get(dev_id, port_id) == PHY_I2C_ACCESS) { - phy_addr = qca_ssdk_port_to_phy_mdio_fake_addr(dev_id, port_id); - } -#endif - - pdata = qca808x_phy_info_get(phy_addr); - if (pdata) { - return pdata->gps_seconds_sync_en; - } - - return A_FALSE; -} - -void qca808x_ptp_clock_mode_config(a_uint32_t dev_id, - a_uint32_t phy_addr, a_uint16_t clock_mode, a_uint16_t step_mode) -{ - struct qca808x_phy_info *pdata; -#if defined(IN_PHY_I2C_MODE) - a_uint32_t port_id; - port_id = qca_ssdk_phy_addr_to_port(dev_id, phy_addr); - if (hsl_port_phy_access_type_get(dev_id, port_id) == PHY_I2C_ACCESS) { - phy_addr = qca_ssdk_port_to_phy_mdio_fake_addr(dev_id, port_id); - } -#endif - - pdata = qca808x_phy_info_get(phy_addr); - - if (pdata) { - pdata->clock_mode = clock_mode; - pdata->step_mode = step_mode; - } - - return; -} - -void qca808x_ptp_stat_update(struct qca808x_phy_info *pdata, fal_ptp_direction_t direction, - a_int32_t msg_type, a_int32_t seqid_matched) -{ - ptp_packet_stat *pkt_stat = NULL; - - if (((direction != FAL_RX_DIRECTION) && (direction != FAL_TX_DIRECTION)) || - (seqid_matched < PTP_PKT_SEQID_UNMATCHED) || - (seqid_matched >= PTP_PKT_SEQID_MATCH_MAX)) { - return; - } - - pkt_stat = &pdata->pkt_stat[direction]; - switch (msg_type) { - case QCA808X_PTP_MSG_SYNC: - pkt_stat->sync_cnt[seqid_matched]++; - break; - case QCA808X_PTP_MSG_DREQ: - pkt_stat->delay_req_cnt[seqid_matched]++; - break; - case QCA808X_PTP_MSG_PREQ: - pkt_stat->pdelay_req_cnt[seqid_matched]++; - break; - case QCA808X_PTP_MSG_PRESP: - pkt_stat->pdelay_resp_cnt[seqid_matched]++; - break; - case QCA808X_PTP_MSG_MAX: - pkt_stat->event_pkt_cnt++; - break; - default: - SSDK_DEBUG("%s: msg %x is not event frame\n", - __func__, msg_type); - } -} - -void qca808x_ptp_stat_get(void) -{ - int i = 0; - struct qca808x_phy_info *pdata = NULL; - ptp_packet_stat *pkt_stat; - - list_for_each_entry(pdata, &g_qca808x_phy_list, list) { - pkt_stat = pdata->pkt_stat; - SSDK_INFO("PHY [%#x] PTP event packet statistics:\n", pdata->phy_addr); - for (i=0; i <= FAL_TX_DIRECTION; i++) - { - if (i == FAL_TX_DIRECTION) { - SSDK_INFO("----------TX direction----------\n"); - } else { - SSDK_INFO("----------RX direction----------\n"); - } - - SSDK_INFO("even sum: %lld\n", - pkt_stat[i].event_pkt_cnt); - SSDK_INFO("seq id matched stat:\n"); - SSDK_INFO("sync: %lld\n", - pkt_stat[i].sync_cnt[PTP_PKT_SEQID_MATCHED]); - SSDK_INFO("delay_req: %lld\n", - pkt_stat[i].delay_req_cnt[PTP_PKT_SEQID_MATCHED]); - SSDK_INFO("pdelay_req: %lld\n", - pkt_stat[i].pdelay_req_cnt[PTP_PKT_SEQID_MATCHED]); - SSDK_INFO("pdelay_resp: %lld\n\n", - pkt_stat[i].pdelay_resp_cnt[PTP_PKT_SEQID_MATCHED]); - - SSDK_INFO("seq id unmatched stat:\n"); - SSDK_INFO("sync: %lld\n", - pkt_stat[i].sync_cnt[PTP_PKT_SEQID_UNMATCHED]); - SSDK_INFO("delay_req: %lld\n", - pkt_stat[i].delay_req_cnt[PTP_PKT_SEQID_UNMATCHED]); - SSDK_INFO("pdelay_req: %lld\n", - pkt_stat[i].pdelay_req_cnt[PTP_PKT_SEQID_UNMATCHED]); - SSDK_INFO("pdelay_resp: %lld\n\n", - pkt_stat[i].pdelay_resp_cnt[PTP_PKT_SEQID_UNMATCHED]); - } - } -} - -void qca808x_ptp_stat_set(void) -{ - struct qca808x_phy_info *pdata; - - list_for_each_entry(pdata, &g_qca808x_phy_list, list) { - memset(pdata->pkt_stat, 0, sizeof(pdata->pkt_stat)); - } -} - -static sw_error_t qca808x_ptp_clock_synce_clock_enable(a_uint32_t dev_id, - a_uint32_t phy_id, a_bool_t enable) -{ - a_uint16_t phy_data, phy_data1; - sw_error_t ret = SW_OK; - - phy_data = qca808x_phy_debug_read(dev_id, phy_id, - QCA808X_DEBUG_ANA_CLOCK_CTRL_REG); - - phy_data1 = qca808x_phy_mmd_read(dev_id, phy_id, QCA808X_PHY_MMD7_NUM, - QCA808X_MMD7_CLOCK_CTRL_REG); - - if (enable == A_TRUE) { - /* enable analog synce clock output */ - phy_data |= QCA808X_ANALOG_PHY_SYNCE_CLOCK_EN; - /* enable digital synce clock output */ - phy_data1 |= QCA808X_DIGITAL_PHY_SYNCE_CLOCK_EN; - } else { - phy_data &= ~QCA808X_ANALOG_PHY_SYNCE_CLOCK_EN; - phy_data1 &= ~QCA808X_DIGITAL_PHY_SYNCE_CLOCK_EN; - } - - ret = qca808x_phy_debug_write(dev_id, phy_id, - QCA808X_DEBUG_ANA_CLOCK_CTRL_REG, phy_data); - - ret |= qca808x_phy_mmd_write(dev_id, phy_id, QCA808X_PHY_MMD7_NUM, - QCA808X_MMD7_CLOCK_CTRL_REG, phy_data1); - return ret; -} - -static sw_error_t qca808x_ptp_clock_incval_mode_set(a_uint32_t dev_id, - a_uint32_t phy_id, a_bool_t enable) -{ - a_uint16_t phy_data; - sw_error_t ret = SW_OK; - - phy_data = qca808x_phy_mmd_read(dev_id, phy_id, QCA808X_PHY_MMD3_NUM, - PTP_RTC_EXT_CONF_REG_ADDRESS); - - if (enable == A_TRUE) { - phy_data |= QCA808X_PTP_INCVAL_SYNC_MODE; - } else { - phy_data &= ~QCA808X_PTP_INCVAL_SYNC_MODE; - } - - ret = qca808x_phy_mmd_write(dev_id, phy_id, QCA808X_PHY_MMD3_NUM, - PTP_RTC_EXT_CONF_REG_ADDRESS, phy_data); - - return ret; -} - -sw_error_t qca808x_ptp_config_init(struct phy_device *phydev) -{ - fal_ptp_config_t ptp_config; - fal_ptp_reference_clock_t ptp_ref_clock; - fal_ptp_rx_timestamp_mode_t rx_ts_mode; - fal_ptp_time_t ptp_time = {0}; - sw_error_t ret = SW_OK; - a_uint32_t dev_id = 0, phy_id = 0; - qca808x_priv *priv = phydev->priv; - const struct qca808x_phy_info *pdata = priv->phy_info; - struct qca808x_ptp_info *ptp_info = &priv->ptp_info; - - if (!pdata) { - return SW_FAIL; - } - - dev_id = pdata->dev_id; - phy_id = pdata->phy_addr; - - /* disable ptp function by default */ - ptp_info->hwts_tx_type = HWTSTAMP_TX_OFF; - ptp_info->hwts_rx_type = PTP_CLASS_NONE; - - ptp_config.ptp_en = A_FALSE; - ptp_config.clock_mode = FAL_OC_CLOCK_MODE; - ptp_config.step_mode = FAL_TWO_STEP_MODE; - ret = qca808x_phy_ptp_config_set(dev_id, phy_id, &ptp_config); - - qca808x_ptp_clock_mode_config(dev_id, phy_id, ptp_config.clock_mode, - ptp_config.step_mode); - - /* set rtc clock to asynchronization mode*/ - ret |= qca808x_ptp_clock_incval_mode_set(dev_id, phy_id, A_FALSE); - - /* adjust frequency to 8ns(125MHz) */ - ptp_time.nanoseconds = QCA808X_PTP_TICK_RATE_125M; - ret |= qca808x_phy_ptp_rtc_adjfreq_set(dev_id, phy_id, &ptp_time); - - /* use SyncE reference clock */ - ptp_ref_clock = FAL_REF_CLOCK_SYNCE; - ret |= qca808x_phy_ptp_reference_clock_set(dev_id, phy_id, ptp_ref_clock); - - /* use Embed mode to get RX timestamp */ - rx_ts_mode = FAL_RX_TS_EMBED; - ret |= qca808x_phy_ptp_rx_timestamp_mode_set(dev_id, phy_id, rx_ts_mode); - - /* disable SYNCE clock output */ - ret |= qca808x_ptp_clock_synce_clock_enable(dev_id, phy_id, A_FALSE); - - if (ret != SW_OK) { - SSDK_ERROR("%s failed\n", __func__); - } - - return ret; -} - -static a_uint8_t* skb_ptp_header(struct sk_buff *skb, int type) -{ - a_uint8_t *data = skb_mac_header(skb); - a_uint32_t offset = 0; - - if (type & PTP_CLASS_VLAN) { - offset += VLAN_HLEN; - } - - switch (type & PTP_CLASS_PMASK) { - case PTP_CLASS_IPV4: - offset += ETH_HLEN + IPV4_HLEN(data + offset) + UDP_HLEN; - break; - case PTP_CLASS_IPV6: - offset += ETH_HLEN + IP6_HLEN + UDP_HLEN; - break; - case PTP_CLASS_L2: - offset += ETH_HLEN; - break; - default: - return NULL; - } - - if (skb->len + ETH_HLEN < offset + - OFF_PTP_SEQUENCE_ID + sizeof(a_uint16_t)) { - return NULL; - } - - return data + offset; -} - -void qca808x_pkt_info_get(struct sk_buff *skb, - unsigned int type, fal_ptp_pkt_info_t *pkt_info) -{ - a_uint16_t *seqid, seqid_pkt; - a_uint32_t *clockid; - a_uint32_t clockid_lo; - a_uint64_t clockid_pkt; - a_uint16_t *portid, portid_pkt; - a_uint8_t msgtype_pkt; - a_uint8_t *ptp_header = NULL; - - ptp_header = skb_ptp_header(skb, type); - if (!ptp_header) { - return; - } - -#define OFF_PTP_CLOCK_ID 20 -#define OFF_PTP_PORT_ID 28 - - seqid = (a_uint16_t *)(ptp_header + OFF_PTP_SEQUENCE_ID); - seqid_pkt = ntohs(*seqid); - clockid = (a_uint32_t *)(ptp_header + OFF_PTP_CLOCK_ID); - clockid_pkt = ntohl(*clockid); - - clockid = (a_uint32_t *)(ptp_header + OFF_PTP_CLOCK_ID + 4); - clockid_lo = ntohl(*clockid); - clockid_pkt = (clockid_pkt << 32) | clockid_lo; - portid = (a_uint16_t *)(ptp_header + OFF_PTP_PORT_ID); - portid_pkt = ntohs(*portid); - msgtype_pkt = (*ptp_header) & 0xf; - - pkt_info->sequence_id = seqid_pkt; - pkt_info->clock_identify = clockid_pkt; - pkt_info->port_number = portid_pkt; - pkt_info->msg_type = msgtype_pkt; - return ; -} - -static void tx_timestamp_work(struct work_struct *work) -{ - struct sk_buff *skb; - struct skb_shared_hwtstamps shhwtstamps; - struct timespec64 ts; - a_uint64_t ns; - a_uint32_t dev_id, phy_id; - qca808x_ptp_cb *ptp_cb; - struct qca808x_phy_info *pdata; - fal_ptp_pkt_info_t pkt_info; - fal_ptp_time_t tx_time = {0}; - sw_error_t ret = SW_OK; - a_uint16_t times = 0; - a_uint16_t seqid = 0; - struct qca808x_ptp_info *ptp_data = - container_of(work, struct qca808x_ptp_info, tx_ts_work.work); - - qca808x_priv *priv = - container_of(ptp_data, qca808x_priv, ptp_info); - - pdata = priv->phy_info; - - if (!pdata) { - return; - } - - dev_id = pdata->dev_id; - phy_id = pdata->phy_addr; - - memset(&shhwtstamps, 0, sizeof(shhwtstamps)); - - while ((skb = skb_dequeue(&ptp_data->tx_queue))) { - ptp_cb = (qca808x_ptp_cb *)skb->cb; - qca808x_pkt_info_get(skb, ptp_cb->ptp_type, &pkt_info); - - times = 0; - do { - /* poll the seqid of the transmitted ptp packet to - * acquire the correspoding tx time stamp. - */ - seqid = qca808x_phy_mmd_read(dev_id, phy_id, QCA808X_PHY_MMD3_NUM, - PTP_TX_SEQID_REG_ADDRESS); - udelay(1); - times++; - } while (seqid != pkt_info.sequence_id && times < 100); - - ret = qca808x_phy_ptp_timestamp_get(dev_id, phy_id, - FAL_TX_DIRECTION, &pkt_info, &tx_time); - - if (ret == SW_NOT_FOUND) { - qca808x_ptp_stat_update(pdata, FAL_TX_DIRECTION, - pkt_info.msg_type, PTP_PKT_SEQID_UNMATCHED); - SSDK_DEBUG("Fail to get tx_ts: sequence_id:%x, clock_identify:%llx," - " port_number:%x, msg_type:%x\n", - pkt_info.sequence_id, pkt_info.clock_identify, - pkt_info.port_number, pkt_info.msg_type); - } else { - qca808x_ptp_stat_update(pdata, FAL_TX_DIRECTION, - pkt_info.msg_type, PTP_PKT_SEQID_MATCHED); - } - ts.tv_sec = tx_time.seconds; - ts.tv_nsec = tx_time.nanoseconds; - - ns = timespec64_to_ns(&ts); - - shhwtstamps.hwtstamp = ns_to_ktime(ns); - skb_complete_tx_timestamp(skb, &shhwtstamps); - } - - if (!skb_queue_empty(&ptp_data->tx_queue)) - schedule_delayed_work(&ptp_data->tx_ts_work, SKB_TIMESTAMP_TIMEOUT); -} - -static void ptp_ingress_time_sync(a_uint32_t phy_addr, a_uint32_t ingress_time, - a_bool_t forward) -{ - fal_ptp_time_t ingress_trig_time = {0}; - struct qca808x_phy_info *pdata = NULL; - - ingress_trig_time.nanoseconds = ingress_time; - - if (forward == A_FALSE) { - list_for_each_entry(pdata, &g_qca808x_phy_list, list) { - if (pdata->phydev_addr == phy_addr) { - qca808x_phy_ptp_pkt_timestamp_set(pdata->dev_id, - pdata->phy_addr, &ingress_trig_time); - break; - } - } - } else { - list_for_each_entry(pdata, &g_qca808x_phy_list, list) { - if (pdata->phydev_addr != phy_addr) { - qca808x_phy_ptp_pkt_timestamp_set(pdata->dev_id, - pdata->phy_addr, &ingress_trig_time); - } - } - } -} - -static void rx_timestamp_work(struct work_struct *work) -{ - struct sk_buff *skb; - struct skb_shared_hwtstamps *shhwtstamps = NULL; - struct timespec64 ts; - a_uint64_t ns; - a_uint32_t dev_id, phy_id; - qca808x_ptp_cb *ptp_cb; - struct qca808x_phy_info *pdata; - fal_ptp_pkt_info_t pkt_info; - fal_ptp_time_t rx_time = {0}; - sw_error_t ret = SW_OK; - - struct qca808x_ptp_info *ptp_data = - container_of(work, struct qca808x_ptp_info, rx_ts_work.work); - - qca808x_priv *priv = - container_of(ptp_data, qca808x_priv, ptp_info); - - pdata = priv->phy_info; - - if (!pdata) { - return; - } - dev_id = pdata->dev_id; - phy_id = pdata->phy_addr; - - /* Deliver packets */ - while ((skb = skb_dequeue(&ptp_data->rx_queue))) { - ptp_cb = (qca808x_ptp_cb *)skb->cb; - qca808x_pkt_info_get(skb, ptp_cb->ptp_type, &pkt_info); - - ret = qca808x_phy_ptp_timestamp_get(dev_id, phy_id, - FAL_RX_DIRECTION, &pkt_info, &rx_time); - if (ret == SW_NOT_FOUND) { - qca808x_ptp_stat_update(pdata, FAL_RX_DIRECTION, - pkt_info.msg_type, PTP_PKT_SEQID_UNMATCHED); - SSDK_DEBUG("Fail to get rx_ts: sequence_id:%x, clock_identify:%llx, " - "port_number:%x, msg_type:%x\n", - pkt_info.sequence_id, pkt_info.clock_identify, - pkt_info.port_number, pkt_info.msg_type); - } else { - qca808x_ptp_stat_update(pdata, FAL_RX_DIRECTION, - pkt_info.msg_type, PTP_PKT_SEQID_MATCHED); - } - - ts.tv_sec = rx_time.seconds; - ts.tv_nsec = rx_time.nanoseconds; - ns = timespec64_to_ns(&ts); - shhwtstamps = skb_hwtstamps(skb); - memset(shhwtstamps, 0, sizeof(*shhwtstamps)); - shhwtstamps->hwtstamp = ns_to_ktime(ns); - - /* OC/BC needs record ingress time stamp on receiving - * peer delay request message under one-step mode. - * TC one step mode should use the embeded mode for offloading - * function. - */ - if (pdata->step_mode == FAL_ONE_STEP_MODE) { - switch (pdata->clock_mode) { - case FAL_OC_CLOCK_MODE: - case FAL_BC_CLOCK_MODE: - if (pkt_info.msg_type == QCA808X_PTP_MSG_PREQ) { - ptp_ingress_time_sync(phy_id, - ts.tv_nsec, A_FALSE); - } - break; - default: - break; - } - } - netif_rx_ni(skb); - } - - if (!skb_queue_empty(&ptp_data->rx_queue)) - schedule_delayed_work(&ptp_data->rx_ts_work, SKB_TIMESTAMP_TIMEOUT); -} - -static void qca808x_gps_second_sync(struct qca808x_phy_info *pdata, a_int32_t *buf) -{ - fal_ptp_time_t time, old_time; - a_uint32_t dev_id, phy_id; - - if (!pdata) { - return; - } - dev_id = pdata->dev_id; - phy_id = pdata->phy_addr; - /* 0-3: time of week; 4-5: week number; 6-7: UTC offset - * Time(UTC) = Time(GPS) - UTC offset */ -#define WEEK_TIME 604800 - time.seconds = ((a_int64_t)buf[0] << 24 | buf[1] << 16 | buf[2] << 8 | buf[3]) + - ((buf[4] << 8 | buf[5]) * WEEK_TIME) - (buf[6] << 8 | buf[7]); - - time.nanoseconds = 0; - time.fracnanoseconds = 0; - - qca808x_phy_ptp_rtc_time_get(dev_id, phy_id, &old_time); - time.seconds -= old_time.seconds; - qca808x_phy_ptp_rtc_adjtime_set(dev_id, phy_id, &time); - - qca808x_ptp_gm_gps_seconds_sync_enable(dev_id, phy_id, A_FALSE); - return; -} - -static void gps_seconds_sync_thread(struct qca808x_phy_info *pdata) -{ - struct file *filp; - mm_segment_t fs; - a_uint32_t nread; - char buff[128]; - char *dev ="/dev/ttyMSM0"; - a_int32_t data[32]; - a_uint32_t i = 0, j = 0; - a_bool_t is_time_pkt = A_FALSE; - a_int32_t try_cycle = 32; - - filp = filp_open(dev, O_RDONLY, 0); - if (IS_ERR(filp)) - { - SSDK_ERROR("Open %s error\n", dev); - return; - } - - fs=get_fs(); - set_fs(KERNEL_DS); - while(1) - { - memset(data, 0, sizeof(data)); - memset(buff, 0, sizeof(buff)); - is_time_pkt = A_FALSE; - filp->f_pos = 0; - nread = filp->f_op->read(filp, buff, sizeof(buff), &filp->f_pos); - if (nread > 0) - { - /* the packet format: */ -#define PKT_DLE 0x10 -#define PKT_ETX 0x3 -#define PKT_PTIME_ID 0x8f -#define PKT_PTIME_SID 0xab -#define PKT_PTIME_LEN 0x10 - buff[nread+1]='\0'; - for(i = 0; i < nread; i++) - { - if (is_time_pkt == A_FALSE) - { - if (buff[i] == PKT_DLE && i+2 < nread && - buff[i+1] == PKT_PTIME_ID && - buff[i+2] == PKT_PTIME_SID) { - is_time_pkt = A_TRUE; - i = i + 2; - j = 0; - } - } else { - data[j++] = buff[i]; - if (j >= PKT_PTIME_LEN && data[j-2] == PKT_DLE && - data[j-1] == PKT_ETX) - { - qca808x_gps_second_sync(pdata, data); - goto gps_time_sync_exit; - } - - if (j > PKT_PTIME_LEN+2) { - is_time_pkt = A_FALSE; - } - } - } - } - - if (--try_cycle <= 0) { - break; - } - } - -gps_time_sync_exit: - set_fs(fs); - filp_close(filp, NULL); -} - -static void qca808x_ptp_schedule_work(struct work_struct *work) -{ - struct qca808x_phy_info *pdata = - container_of(work, struct qca808x_phy_info, ts_schedule_work.work); - - if (!pdata) { - return; - } - gps_seconds_sync_thread(pdata); - - if (pdata->gps_seconds_sync_en == A_TRUE) { - schedule_delayed_work(&pdata->ts_schedule_work, GPS_WORK_TIMEOUT); - } -} - -static void ingress_trig_time_work(struct work_struct *work) -{ - const struct qca808x_phy_info *pdata; - struct qca808x_ptp_info *ptp_data = - container_of(work, struct qca808x_ptp_info, ingress_trig_work.work); - - qca808x_priv *priv = - container_of(ptp_data, qca808x_priv, ptp_info); - - pdata = priv->phy_info; - - if (!pdata) { - return; - } - - switch (pdata->clock_mode) { - case FAL_P2PTC_CLOCK_MODE: - /* p2p tc one step just use ingress trig time for pdelay resp, - * the ingress timestamp should be recorded in the local phy. - */ - ptp_ingress_time_sync(pdata->phy_addr, ptp_data->ingress_time, A_FALSE); - break; - case FAL_E2ETC_CLOCK_MODE: - ptp_ingress_time_sync(pdata->phy_addr, ptp_data->ingress_time, A_TRUE); - break; - case FAL_OC_CLOCK_MODE: - case FAL_BC_CLOCK_MODE: - ptp_ingress_time_sync(pdata->phy_addr, ptp_data->ingress_time, A_FALSE); - break; - default: - break; - } - - return; -} - -/****************************************************************************** -* -* qca808x_ptp_settime - reset the rtc timecounter -* -* ptp: the ptp clock info structure -* ts: the new rtc timecounter -* -*/ -static int qca808x_ptp_settime(struct ptp_clock_info *ptp, - const struct timespec64 *ts) -{ - const struct qca808x_phy_info *pdata; - struct qca808x_ptp_clock *clock = - container_of(ptp, struct qca808x_ptp_clock, caps); - - fal_ptp_time_t ptp_time = {0}; - - qca808x_priv *priv = clock->priv; - pdata = priv->phy_info; - - if (!pdata) { - return SW_FAIL; - } - ptp_time.seconds = ts->tv_sec; - ptp_time.nanoseconds = ts->tv_nsec; - - mutex_lock(&clock->tsreg_lock); - qca808x_phy_ptp_rtc_time_set(pdata->dev_id, pdata->phy_addr, &ptp_time); - mutex_unlock(&clock->tsreg_lock); - return 0; -} - -/****************************************************************************** -* -* qca808x_ptp_gettime - read the rtc timecounter -* -* ptp: the ptp clock info structure -* ts: the timespace to hold the current rtc time -* -*/ -static int qca808x_ptp_gettime(struct ptp_clock_info *ptp, - struct timespec64 *ts) -{ - const struct qca808x_phy_info *pdata; - struct qca808x_ptp_clock *clock = - container_of(ptp, struct qca808x_ptp_clock, caps); - - fal_ptp_time_t ptp_time = {0}; - - qca808x_priv *priv = clock->priv; - pdata = priv->phy_info; - - if (!pdata) { - return SW_FAIL; - } - mutex_lock(&clock->tsreg_lock); - qca808x_phy_ptp_rtc_time_get(pdata->dev_id, pdata->phy_addr, &ptp_time); - mutex_unlock(&clock->tsreg_lock); - - ts->tv_sec = ptp_time.seconds; - ts->tv_nsec = ptp_time.nanoseconds; - return 0; -} - -/****************************************************************************** -* -* qca808x_ptp_adjtime - adjust the rtc timecounter offset -* -* ptp: the ptp clock info structure -* delta: offset to be adjusted per cycle counter -* -*/ -static int qca808x_ptp_adjtime(struct ptp_clock_info *ptp, s64 delta) -{ - struct timespec64 ts; - const struct qca808x_phy_info *pdata; - struct qca808x_ptp_clock *clock = - container_of(ptp, struct qca808x_ptp_clock, caps); - - fal_ptp_time_t ptp_time = {0}; - - qca808x_priv *priv = clock->priv; - pdata = priv->phy_info; - - if (!pdata) { - return SW_FAIL; - } - ts = ns_to_timespec64(delta); - ptp_time.seconds = ts.tv_sec; - ptp_time.nanoseconds = ts.tv_nsec; - - mutex_lock(&clock->tsreg_lock); - qca808x_phy_ptp_rtc_adjtime_set(pdata->dev_id, pdata->phy_addr, &ptp_time); - mutex_unlock(&clock->tsreg_lock); - return 0; -} - -static void qca808x_ppb_to_freq (a_int32_t speed, a_int32_t ppb, fal_ptp_time_t *ptp_time) -{ - a_uint64_t rate; - a_uint16_t ns, ns_tmp; - a_int32_t neg_adj = 0, tmp = 0; - - if (ppb < 0) { - neg_adj = 1; - ppb = -ppb; - } - - rate = ppb; - rate <<= 20; - /* divided by (200Mhz-ppb/8)/64 */ - if (speed == FAL_SPEED_2500) { - tmp = (ppb/5)/64; - ns_tmp = QCA808X_PTP_TICK_RATE_200M; - rate = div_u64(rate, 3125000 + tmp); - } else { - tmp = (ppb/8)/64; - ns_tmp = QCA808X_PTP_TICK_RATE_125M; - rate = div_u64(rate, 1953125 + tmp); - } - - if(neg_adj && rate != 0) { - ns = ns_tmp - 1; - rate = (2<<26)-rate; - } else { - ns = ns_tmp; - } - - /* remove the redundant bits, only 26 bits for fracnanoseconds */ - while (rate & 0xfc000000) { - rate >>= 1; - } - - ptp_time->seconds = 0; - ptp_time->nanoseconds = ns; - ptp_time->fracnanoseconds = rate; - - return; -} - -static void qca808x_ptp_adjfreq_sync(a_uint32_t phy_addr, - a_int32_t ppb, fal_ptp_time_t ptp_time_org) -{ - fal_ptp_reference_clock_t ref_clock = FAL_REF_CLOCK_LOCAL; - fal_ptp_time_t ptp_time = {0}; - struct qca808x_phy_info *pdata = NULL; - sw_error_t ret = SW_OK; - a_uint32_t gm_mode = 0; - - /* - * In BC mode, the SYNC clock, PPS and Toduart PINs are connected, - * the adjust frequency should be same among the ports to guaranteeing - * the RTC consistent. - */ - list_for_each_entry(pdata, &g_qca808x_phy_list, list) { - if (pdata->phydev_addr != phy_addr) { - ret = qca808x_ptp_gm_conf0_reg_grandmaster_mode_get(pdata->dev_id, - pdata->phy_addr, &gm_mode); - /* The grandmaster mode should be configured to sync RTC */ - if (ret == SW_OK && gm_mode == PTP_REG_BIT_TRUE) { - ptp_time = ptp_time_org; - ret = qca808x_phy_ptp_reference_clock_get(pdata->dev_id, - pdata->phy_addr, &ref_clock); - /* - * BC ports share the same RTC clock in the external mode - * so the adjust frequency should be also same, otherwise - * the ppb should be converted to the corresponding value - * of the adjust frequency. - */ - if (ret == SW_OK && ref_clock != FAL_REF_CLOCK_EXTERNAL) { - qca808x_ppb_to_freq(pdata->speed, ppb, &ptp_time); - } - qca808x_phy_ptp_rtc_adjfreq_set(pdata->dev_id, - pdata->phy_addr, &ptp_time); - } - } - } - - return; -} - -/****************************************************************************** -* -* qca808x_ptp_adjfreq - adjust the frequency of cycle counter -* -* ptp: the ptp clock info structure -* ppb: parts per billion adjustment from master -* -*/ -static int qca808x_ptp_adjfreq(struct ptp_clock_info *ptp, s32 ppb) -{ - const struct qca808x_phy_info *pdata; - struct qca808x_ptp_clock *clock = - container_of(ptp, struct qca808x_ptp_clock, caps); - - fal_ptp_time_t ptp_time = {0}; - - qca808x_priv *priv = clock->priv; - struct phy_device *phydev = priv->phydev; - pdata = priv->phy_info; - - if (!pdata || !phydev) { - return SW_FAIL; - } - - qca808x_ppb_to_freq(pdata->speed, ppb, &ptp_time); - - mutex_lock(&clock->tsreg_lock); - qca808x_phy_ptp_rtc_adjfreq_set(pdata->dev_id, pdata->phy_addr, &ptp_time); - if (pdata->clock_mode == FAL_BC_CLOCK_MODE) { - /* Keep RTC time consistent among BC ports */ - qca808x_ptp_adjfreq_sync(pdata->phy_addr, ppb, ptp_time); - } - mutex_unlock(&clock->tsreg_lock); - return 0; -} - -static int qca808x_ptp_enable(struct ptp_clock_info *ptp, - struct ptp_clock_request *rq, int on) -{ - return -EOPNOTSUPP; -} - -#if (LINUX_VERSION_CODE >= KERNEL_VERSION(4,4,0)) -static int qca808x_ptp_verify(struct ptp_clock_info *ptp, unsigned int pin, - enum ptp_pin_function func, unsigned int chan) -{ - return 1; -} -#endif - -void qca808x_ptp_change_notify(struct phy_device *phydev) -{ - fal_ptp_reference_clock_t ptp_ref_clock = FAL_REF_CLOCK_EXTERNAL; - fal_ptp_time_t ptp_cycle_time = {0}; - a_uint32_t nanoseconds = 0; - qca808x_priv *priv = phydev->priv; - struct qca808x_phy_info *pdata = priv->phy_info; - - if (!pdata) { - return; - } - - if (pdata->speed != phydev->speed) { - if (phydev->speed == SPEED_2500 && - pdata->speed < SPEED_2500) { - /* adjust frequency to 5ns(200MHz) */ - nanoseconds = QCA808X_PTP_TICK_RATE_200M; - } else if (pdata->speed == SPEED_2500 && - phydev->speed < SPEED_2500) { - /* adjust frequency to 8ns(125MHz) */ - nanoseconds = QCA808X_PTP_TICK_RATE_125M; - } - - if (phydev->speed == SPEED_10) { - /* local free running clock for 10M */ - ptp_ref_clock = FAL_REF_CLOCK_LOCAL; - } else if (pdata->speed == SPEED_10) { - ptp_ref_clock = FAL_REF_CLOCK_SYNCE; - } - - if (ptp_ref_clock != FAL_REF_CLOCK_EXTERNAL) { - qca808x_phy_ptp_reference_clock_set(pdata->dev_id, - pdata->phy_addr, ptp_ref_clock); - } - - pdata->speed = phydev->speed; - if (nanoseconds != 0) { - ptp_cycle_time.nanoseconds = nanoseconds; - qca808x_phy_ptp_rtc_adjfreq_set(pdata->dev_id, - pdata->phy_addr, &ptp_cycle_time); - } - } -} - -int qca808x_hwtstamp(struct phy_device *phydev, struct ifreq *ifr) -{ - struct hwtstamp_config cfg; - a_uint32_t gm_mode = 0; - fal_ptp_reference_clock_t ref_clock = FAL_REF_CLOCK_LOCAL; - sw_error_t ret = SW_OK; - fal_ptp_config_t ptp_config = {0}; - qca808x_priv *priv = phydev->priv; - struct qca808x_phy_info *pdata = priv->phy_info; - struct qca808x_ptp_info *ptp_info = &priv->ptp_info; - struct qca808x_ptp_clock *clock = ptp_info->clock; - - if (!pdata || !clock) { - return -EFAULT; - } - - if (copy_from_user(&cfg, ifr->ifr_data, sizeof(cfg))) - return -EFAULT; - if (cfg.flags) /* reserved for future extensions */ - return -EINVAL; - - if (cfg.tx_type < 0 || cfg.tx_type > HWTSTAMP_TX_ONESTEP_P2P) - return -ERANGE; - - ptp_info->hwts_tx_type = cfg.tx_type; - - switch (cfg.rx_filter) { - case HWTSTAMP_FILTER_NONE: - ptp_info->hwts_rx_type = PTP_CLASS_NONE; - break; - case HWTSTAMP_FILTER_PTP_V2_EVENT: - case HWTSTAMP_FILTER_PTP_V2_SYNC: - case HWTSTAMP_FILTER_PTP_V2_DELAY_REQ: - ptp_info->hwts_rx_type = PTP_CLASS_L4 | PTP_CLASS_L2; - break; - case HWTSTAMP_FILTER_PTP_V2_L4_EVENT: - case HWTSTAMP_FILTER_PTP_V2_L4_SYNC: - case HWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ: - ptp_info->hwts_rx_type = PTP_CLASS_L4; - break; - case HWTSTAMP_FILTER_PTP_V2_L2_EVENT: - case HWTSTAMP_FILTER_PTP_V2_L2_SYNC: - case HWTSTAMP_FILTER_PTP_V2_L2_DELAY_REQ: - ptp_info->hwts_rx_type = PTP_CLASS_L2; - break; - default: - return -ERANGE; - } - - mutex_lock(&clock->tsreg_lock); - ptp_config.clock_mode = pdata->clock_mode; - switch (ptp_info->hwts_tx_type) { - case HWTSTAMP_TX_ON: - ptp_config.ptp_en = A_TRUE; - ptp_config.step_mode = FAL_TWO_STEP_MODE; - break; - case HWTSTAMP_TX_ONESTEP_SYNC: - case HWTSTAMP_TX_ONESTEP_P2P: - ptp_config.ptp_en = A_TRUE; - ptp_config.step_mode = FAL_ONE_STEP_MODE; - break; - case HWTSTAMP_TX_OFF: - default: - ptp_config.ptp_en = A_FALSE; - ptp_config.step_mode = FAL_TWO_STEP_MODE; - break; - } - ret = qca808x_phy_ptp_config_set(pdata->dev_id, pdata->phy_addr, &ptp_config); - mutex_unlock(&clock->tsreg_lock); - if (ret != SW_OK) { - return -EFAULT; - } - - /* - * disable SYNCE clock output by default, - * only enabling the clock output under the - * BC mode && not in external reference mode - */ - qca808x_ptp_clock_synce_clock_enable(pdata->dev_id, pdata->phy_addr, A_FALSE); - - if (pdata->clock_mode == FAL_BC_CLOCK_MODE) { - ret = qca808x_ptp_gm_conf0_reg_grandmaster_mode_get(pdata->dev_id, - pdata->phy_addr, &gm_mode); - /* The grandmaster mode should be configured to sync RTC */ - if (ret == SW_OK && gm_mode != PTP_REG_BIT_TRUE) { - ret = qca808x_phy_ptp_reference_clock_get(pdata->dev_id, - pdata->phy_addr, &ref_clock); - /* - * The PHC should be with below PINs connected for clock synchronized - * so NAPA1 should be configured as sync or local reference clock, - * and NAPA2 is configured as FAL_REF_CLOCK_EXTERNAL & grandmaster mode. - * - * Napa1 ToD out --- > Napa2 ToD in. - * Napa1 PPS out --- > Napa2 PPS in. - * Napa1 sync clock out --- > Napa2 reference clock in. - */ - if (ret == SW_OK && ref_clock != FAL_REF_CLOCK_EXTERNAL) { - /* enable SYNCE clock output */ - qca808x_ptp_clock_synce_clock_enable(pdata->dev_id, - pdata->phy_addr, A_TRUE); - } - } - } - - pdata->step_mode = ptp_config.step_mode; - - return copy_to_user(ifr->ifr_data, &cfg, sizeof(cfg)) ? -EFAULT : 0; -} - -bool qca808x_rxtstamp(struct phy_device *phydev, - struct sk_buff *nskb, int type) -{ - struct skb_shared_hwtstamps *shhwtstamps = NULL; - struct timespec64 ts = {0}; - a_bool_t ingress_trig_flag = A_FALSE; - a_uint64_t ns; - a_int64_t *correction; - a_uint16_t *seqid; - a_int32_t ptp_class; - a_uint32_t *reserved2; - a_uint8_t *reserved0, *reserved1; - a_uint32_t *cf1; - a_uint8_t *ptp_header; - a_uint8_t embed_val, pkt_type; - qca808x_ptp_cb *ptp_cb = (qca808x_ptp_cb *)nskb->cb; - qca808x_priv *priv = phydev->priv; - struct qca808x_phy_info *pdata = priv->phy_info; - struct qca808x_ptp_info *ptp_info = &priv->ptp_info; - - if (ptp_info->hwts_rx_type == PTP_CLASS_NONE || !pdata) { - return false; - } - - /* The PTP_CLASS_NONE is passed, which indicates that the - * PTP class is not determined, calling ptp_classify_raw to - * classfy the packet. - */ - if (type == PTP_CLASS_NONE) { - __skb_push(nskb, ETH_HLEN); - /* dissecting the packet content to get ptp class */ - ptp_class = ptp_classify_raw(nskb); - __skb_pull(nskb, ETH_HLEN); - if (ptp_class == PTP_CLASS_NONE) { - /* this case should not happen, only ptp event packet passed */ - SSDK_ERROR("%s: No PTP event packet received\n", __func__); - return false; - } - type = ptp_class; - } - - if ((ptp_info->hwts_rx_type & type) == PTP_CLASS_NONE) { - return false; - } - - ptp_header = skb_ptp_header(nskb, type); - if (!ptp_header) { - return false; - } - shhwtstamps = skb_hwtstamps(nskb); - memset(shhwtstamps, 0, sizeof(*shhwtstamps)); - -#define PTP_HDR_CORRECTIONFIELD_CPY_SRC 11 -#define PTP_HDR_CORRECTIONFIELD_CPY_DST 9 -#define PTP_HDR_CORRECTIONFIELD_CPY_LEN 5 - - reserved0 = ptp_header + PTP_HDR_RESERVED0_OFFSET; - reserved1 = ptp_header + PTP_HDR_RESERVED1_OFFSET; - cf1 = (a_uint32_t *)(ptp_header + PTP_HDR_CORRECTIONFIELD_OFFSET); - correction = (a_uint64_t *)(ptp_header + PTP_HDR_CORRECTIONFIELD_OFFSET); - seqid = (a_uint16_t *)(ptp_header + OFF_PTP_SEQUENCE_ID); - reserved2 = (a_uint32_t *)(ptp_header + PTP_HDR_RESERVED2_OFFSET); - - embed_val = (*reserved0 & 0xf0) >> 4; - pkt_type = *ptp_header & 0xf; - - qca808x_ptp_stat_update(pdata, FAL_RX_DIRECTION, - QCA808X_PTP_MSG_MAX, PTP_PKT_SEQID_UNMATCHED); - - if (embed_val == QCA808X_PTP_EMBEDDED_MODE) { - ts.tv_sec = ntohl(*reserved2); - ts.tv_nsec = ((a_uint32_t)*reserved1 << 24) | (ntohl(*cf1) >> 8); - - if (pdata->step_mode == FAL_ONE_STEP_MODE) { - switch (pdata->clock_mode) { - case FAL_OC_CLOCK_MODE: - case FAL_BC_CLOCK_MODE: - case FAL_P2PTC_CLOCK_MODE: - /* message sync with the timestamp inserted into the ptp - * header, do not use the ingress_trig_time register, the - * ingress time will be acquired from ptp header. - * the ingress time of pdealy request msg should be - * recorded and will be copied the corresponding pdealy - * response msg. - */ - if (pkt_type == QCA808X_PTP_MSG_PREQ) { - ptp_info->embeded_ts.reserved0 = *reserved0; - ptp_info->embeded_ts.reserved1 = *reserved1; - ptp_info->embeded_ts.reserved2 = *reserved2; - ptp_info->embeded_ts.correction = *correction; - ptp_info->embeded_ts.seqid = *seqid; - ptp_info->embeded_ts.msg_type = pkt_type; - } - break; - case FAL_E2ETC_CLOCK_MODE: - ingress_trig_flag = A_TRUE; - break; - default: - break; - } - if (ingress_trig_flag == A_TRUE) { - ptp_info->ingress_time = ts.tv_nsec; - schedule_delayed_work(&ptp_info->ingress_trig_work, 0); - } - } - - /* restore the original correctionfield value except for - * the TC one-step mode offloading*/ - if (!(((pdata->clock_mode == FAL_P2PTC_CLOCK_MODE && - pkt_type == QCA808X_PTP_MSG_SYNC) || - pdata->clock_mode == FAL_E2ETC_CLOCK_MODE) && - pdata->step_mode == FAL_ONE_STEP_MODE)) - { - /* in embeded mode for the rx time stamp, the correction field - * is modfied to keep the low 50 bit of nanosecond and the - * fractional nanoseconds should be dropped - */ - *reserved0 = *reserved0 & 0xf; - memmove(ptp_header + PTP_HDR_CORRECTIONFIELD_CPY_DST, - ptp_header + PTP_HDR_CORRECTIONFIELD_CPY_SRC, - PTP_HDR_CORRECTIONFIELD_CPY_LEN); - memset(ptp_header + PTP_HDR_CORRECTIONFIELD_OFFSET, 0, 1); - memset(ptp_header + PTP_HDR_RESERVED2_OFFSET - 2, 0, 6); - } - } else { - ptp_cb->ptp_type = type; - ptp_cb->pkt_type = pkt_type; - skb_queue_tail(&ptp_info->rx_queue, nskb); - schedule_delayed_work(&ptp_info->rx_ts_work, 0); - return true; - } - ns = timespec64_to_ns(&ts); - - qca808x_ptp_stat_update(pdata, FAL_RX_DIRECTION, - pkt_type, PTP_PKT_SEQID_MATCHED); - - shhwtstamps->hwtstamp = ns_to_ktime(ns); - netif_rx_ni(nskb); - - return true; -} - -void qca808x_txtstamp(struct phy_device *phydev, - struct sk_buff *org_skb, int type) -{ - a_uint8_t msg_type; - struct sk_buff *skb; - qca808x_ptp_cb *ptp_cb; - a_uint8_t *ptp_header; - a_int64_t *correction; - a_uint32_t *reserved2; - a_uint8_t *reserved0, *reserved1; - a_uint16_t *seqid; - a_int32_t ptp_class; - qca808x_priv *priv = phydev->priv; - struct qca808x_ptp_info *ptp_info = &priv->ptp_info; - - /* The PTP_CLASS_NONE is passed, which indicates that the - * PTP class is not determined, calling ptp_classify_raw to - * classfy the packet. - */ - if (type == PTP_CLASS_NONE) { - ptp_class = ptp_classify_raw(org_skb); - if (ptp_class == PTP_CLASS_NONE) { - return; - } - skb = skb_clone_sk(org_skb); - if (!skb) { - SSDK_ERROR("%s: skb_clone_sk failed\n", __func__); - return; - } - type = ptp_class; - } else { - skb = org_skb; - } - - ptp_header = skb_ptp_header(skb, type); - if (!ptp_header) { - kfree_skb(skb); - return; - } - - ptp_cb = (qca808x_ptp_cb *)skb->cb; - seqid = (a_uint16_t *)(ptp_header + OFF_PTP_SEQUENCE_ID); - reserved0 = ptp_header + PTP_HDR_RESERVED0_OFFSET; - reserved1 = ptp_header + PTP_HDR_RESERVED1_OFFSET; - reserved2 = (a_uint32_t *)(ptp_header + PTP_HDR_RESERVED2_OFFSET); - correction = (a_uint64_t *)(ptp_header + PTP_HDR_CORRECTIONFIELD_OFFSET); - msg_type = *ptp_header & 0xf; - switch (ptp_info->hwts_tx_type) { - case HWTSTAMP_TX_ONESTEP_SYNC: - if (msg_type == QCA808X_PTP_MSG_SYNC) { - skb_shinfo(skb)->tx_flags |= SKBTX_IN_PROGRESS; - kfree_skb(skb); - return; - } - break; - case HWTSTAMP_TX_ONESTEP_P2P: - switch (msg_type) { - case QCA808X_PTP_MSG_PRESP: - if (ptp_info->embeded_ts.seqid == *seqid && - ptp_info->embeded_ts.msg_type == - QCA808X_PTP_MSG_PREQ) { - *reserved0 = ptp_info->embeded_ts.reserved0; - *reserved1 = ptp_info->embeded_ts.reserved1; - *reserved2 = ptp_info->embeded_ts.reserved2; - *correction = ptp_info->embeded_ts.correction; - } - /* fall down */ - case QCA808X_PTP_MSG_SYNC: - skb_shinfo(skb)->tx_flags |= SKBTX_IN_PROGRESS; - kfree_skb(skb); - return; - default: - break; - } - break; - case HWTSTAMP_TX_ON: - break; - /* enqueue skb to get tx timestamp */ - case HWTSTAMP_TX_OFF: - default: - kfree_skb(skb); - return; - } - - skb_shinfo(skb)->tx_flags |= SKBTX_IN_PROGRESS; - skb_queue_tail(&ptp_info->tx_queue, skb); - ptp_cb->ptp_type = type; - qca808x_ptp_stat_update(priv->phy_info, FAL_TX_DIRECTION, - QCA808X_PTP_MSG_MAX, PTP_PKT_SEQID_UNMATCHED); - schedule_delayed_work(&ptp_info->tx_ts_work, 0); -} - -#if (LINUX_VERSION_CODE >= KERNEL_VERSION(4,4,0)) -int qca808x_ts_info(struct phy_device *phydev, - struct ethtool_ts_info *info) -{ - qca808x_priv *priv = phydev->priv; - struct qca808x_ptp_info *ptp_info = &priv->ptp_info; - struct qca808x_ptp_clock *clock = ptp_info->clock; - - if (clock) { - info->phc_index = ptp_clock_index(clock->ptp_clock); - } - - info->so_timestamping = - SOF_TIMESTAMPING_TX_HARDWARE | - SOF_TIMESTAMPING_RX_HARDWARE | - SOF_TIMESTAMPING_RAW_HARDWARE; - info->tx_types = - (1 << HWTSTAMP_TX_OFF) | - (1 << HWTSTAMP_TX_ON) | - (1 << HWTSTAMP_TX_ONESTEP_SYNC) | - (1 << HWTSTAMP_TX_ONESTEP_P2P); - - info->rx_filters = - (1 << HWTSTAMP_FILTER_NONE) | - (1 << HWTSTAMP_FILTER_PTP_V2_L4_EVENT) | - (1 << HWTSTAMP_FILTER_PTP_V2_L2_EVENT) | - (1 << HWTSTAMP_FILTER_PTP_V2_EVENT); - - return 0; -} -#endif - -static int qca808x_ptp_register(struct phy_device *phydev) -{ - int err; - struct qca808x_ptp_clock *clock; - qca808x_priv *priv = phydev->priv; - struct qca808x_ptp_info *ptp_info = &priv->ptp_info; - - clock = kzalloc(sizeof(struct qca808x_ptp_clock), GFP_KERNEL); - if (!clock) { - return -ENOMEM; - } - - mutex_init(&clock->tsreg_lock); - clock->caps.owner = THIS_MODULE; -#if (LINUX_VERSION_CODE >= KERNEL_VERSION(4, 9, 0)) - snprintf(clock->caps.name, sizeof(clock->caps.name), "qca808x timer %x", phydev->mdio.addr); -#else - snprintf(clock->caps.name, sizeof(clock->caps.name), "qca808x timer %x", phydev->addr); -#endif - clock->caps.max_adj = 3124999; - clock->caps.n_alarm = 0; - clock->caps.n_ext_ts = 6; - clock->caps.n_per_out = 7; - clock->caps.pps = 0; -#if (LINUX_VERSION_CODE >= KERNEL_VERSION(4,4,0)) - clock->caps.n_pins = 0; - clock->caps.verify = qca808x_ptp_verify; - clock->caps.gettime64 = qca808x_ptp_gettime; - clock->caps.settime64 = qca808x_ptp_settime; -#else - clock->caps.gettime = qca808x_ptp_gettime; - clock->caps.settime = qca808x_ptp_settime; -#endif - clock->caps.adjfreq = qca808x_ptp_adjfreq; - clock->caps.adjtime = qca808x_ptp_adjtime; - clock->caps.enable = qca808x_ptp_enable; - -#if (LINUX_VERSION_CODE >= KERNEL_VERSION(4, 9, 0)) - clock->ptp_clock = ptp_clock_register(&clock->caps, &phydev->mdio.dev); -#else - clock->ptp_clock = ptp_clock_register(&clock->caps, &phydev->dev); -#endif - if (IS_ERR(clock->ptp_clock)) { - err = PTR_ERR(clock->ptp_clock); - kfree(clock); - return err; - } - ptp_info->clock = clock; - clock->priv = priv; - - SSDK_INFO("qca808x ptp clock registered\n"); - return 0; -} - -static void qca808x_ptp_unregister(struct phy_device *phydev) -{ - qca808x_priv *priv = phydev->priv; - struct qca808x_ptp_info *ptp_info = &priv->ptp_info; - struct qca808x_ptp_clock *clock = ptp_info->clock; - - if (clock) { - ptp_clock_unregister(clock->ptp_clock); - mutex_destroy(&clock->tsreg_lock); - kfree(clock); - } -} - -int qca808x_ptp_init(qca808x_priv *priv) -{ - int err; - struct qca808x_ptp_info *ptp_info; - struct qca808x_phy_info *pdata; - - if (!priv) { - return -1; - } - - ptp_info = &priv->ptp_info; - pdata = priv->phy_info; - INIT_DELAYED_WORK(&ptp_info->tx_ts_work, tx_timestamp_work); - INIT_DELAYED_WORK(&ptp_info->rx_ts_work, rx_timestamp_work); - skb_queue_head_init(&ptp_info->tx_queue); - skb_queue_head_init(&ptp_info->rx_queue); - - INIT_DELAYED_WORK(&ptp_info->ingress_trig_work, ingress_trig_time_work); - INIT_DELAYED_WORK(&pdata->ts_schedule_work, qca808x_ptp_schedule_work); - - err = qca808x_ptp_register(priv->phydev); - if (err <0) { - SSDK_ERROR("qca808x ptp clock register failed\n"); - kfree(ptp_info); - return err; - } - - return err; -} - -void qca808x_ptp_deinit(qca808x_priv *priv) -{ - struct qca808x_ptp_info *ptp_info; - struct qca808x_phy_info *pdata; - if (!priv) { - return; - } - - ptp_info = &priv->ptp_info; - pdata = priv->phy_info; - cancel_delayed_work_sync(&ptp_info->tx_ts_work); - cancel_delayed_work_sync(&ptp_info->rx_ts_work); - cancel_delayed_work_sync(&ptp_info->ingress_trig_work); - cancel_delayed_work_sync(&pdata->ts_schedule_work); - skb_queue_purge(&ptp_info->tx_queue); - skb_queue_purge(&ptp_info->rx_queue); - - qca808x_ptp_unregister(priv->phydev); -} diff --git a/feeds/ipq807x/qca-ssdk/src/src/hsl/phy/qca808x_phy.c b/feeds/ipq807x/qca-ssdk/src/src/hsl/phy/qca808x_phy.c deleted file mode 100755 index 4ca834a75..000000000 --- a/feeds/ipq807x/qca-ssdk/src/src/hsl/phy/qca808x_phy.c +++ /dev/null @@ -1,2265 +0,0 @@ -/* - * Copyright (c) 2018, 2020-2021, The Linux Foundation. All rights reserved. - * Permission to use, copy, modify, and/or distribute this software for - * any purpose with or without fee is hereby granted, provided that the - * above copyright notice and this permission notice appear in all copies. - * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES - * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR - * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES - * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN - * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT - * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. - */ -/*qca808x_start*/ -#include "sw.h" -#include "fal_port_ctrl.h" -#include "hsl_api.h" -#include "hsl.h" -#include "hsl_phy.h" -#include "ssdk_plat.h" -#include "qca808x_phy.h" -/*qca808x_end*/ -#if defined(IN_PTP) -#include "qca808x_ptp.h" -#endif -#include "qca808x.h" -#ifdef IN_LED -#include "qca808x_led.h" -#endif - -static a_bool_t phy_dev_drv_init_flag = A_FALSE; -/*qca808x_start*/ -static a_bool_t phy_ops_flag = A_FALSE; - -static struct mutex qca808x_reg_lock; - -#define QCA808X_LOCKER_INIT mutex_init(&qca808x_reg_lock) -#define QCA808X_REG_LOCK mutex_lock(&qca808x_reg_lock) -#define QCA808X_REG_UNLOCK mutex_unlock(&qca808x_reg_lock) - -/****************************************************************************** -* -* qca808x_phy_mii_read - mii register read -* -* mii register read -*/ -a_uint16_t -qca808x_phy_reg_read(a_uint32_t dev_id, a_uint32_t phy_id, a_uint32_t reg_id) -{ - sw_error_t rv = SW_OK; - a_uint16_t phy_data = 0; -#if defined(IN_PHY_I2C_MODE) - a_uint32_t port_id = qca_ssdk_phy_addr_to_port(dev_id, phy_id); - a_uint8_t phy_access_type = hsl_port_phy_access_type_get(dev_id, port_id); - - if (phy_access_type == PHY_I2C_ACCESS) { - HSL_PHY_I2C_GET(rv, dev_id, phy_id, reg_id, &phy_data); - } - else -#endif - { - HSL_PHY_GET(rv, dev_id, phy_id, reg_id, &phy_data); - } - - if (rv != SW_OK) { - return PHY_INVALID_DATA; - } - - return phy_data; -} - -/****************************************************************************** -* -* qca808x_phy_mii_write - mii register write -* -* mii register write -*/ -sw_error_t -qca808x_phy_reg_write(a_uint32_t dev_id, a_uint32_t phy_id, a_uint32_t reg_id, - a_uint16_t reg_val) -{ - sw_error_t rv; -#if defined(IN_PHY_I2C_MODE) - a_uint32_t port_id = qca_ssdk_phy_addr_to_port(dev_id, phy_id); - a_uint8_t phy_access_type = hsl_port_phy_access_type_get(dev_id, port_id); - - if (phy_access_type == PHY_I2C_ACCESS) { - HSL_PHY_I2C_SET(rv, dev_id, phy_id, reg_id, reg_val); - } - else -#endif - { - HSL_PHY_SET(rv, dev_id, phy_id, reg_id, reg_val); - } - - return rv; - -} - -/****************************************************************************** -* -* qca808x_phy_debug_write - debug port write -* -* debug port write -*/ -sw_error_t -qca808x_phy_debug_write(a_uint32_t dev_id, a_uint32_t phy_id, a_uint16_t reg_id, - a_uint16_t reg_val) -{ - sw_error_t rv = SW_OK; - - QCA808X_REG_LOCK; - rv = qca808x_phy_reg_write(dev_id, phy_id, QCA808X_DEBUG_PORT_ADDRESS, reg_id); - if (rv != SW_OK) - { - QCA808X_REG_UNLOCK; - SSDK_ERROR("qca808x_phy_reg_write failed\n"); - return SW_FAIL; - } - - rv = qca808x_phy_reg_write(dev_id, phy_id, QCA808X_DEBUG_PORT_DATA, reg_val); - if (rv != SW_OK) - { - QCA808X_REG_UNLOCK; - SSDK_ERROR("qca808x_phy_reg_write failed\n"); - return SW_FAIL; - } - QCA808X_REG_UNLOCK; - - return rv; -} - -/****************************************************************************** -* -* qca808x_phy_debug_read - debug port read -* -* debug port read -*/ -a_uint16_t -qca808x_phy_debug_read(a_uint32_t dev_id, a_uint32_t phy_id, a_uint16_t reg_id) -{ - sw_error_t rv = SW_OK; - a_uint16_t phy_data = 0; - - QCA808X_REG_LOCK; - rv = qca808x_phy_reg_write(dev_id, phy_id, QCA808X_DEBUG_PORT_ADDRESS, reg_id); - if (rv != SW_OK) { - QCA808X_REG_UNLOCK; - SSDK_DEBUG("qca808x_phy_reg_write failed\n"); - return PHY_INVALID_DATA; - } - phy_data = qca808x_phy_reg_read(dev_id, phy_id, QCA808X_DEBUG_PORT_DATA); - if (phy_data == PHY_INVALID_DATA) { - QCA808X_REG_UNLOCK; - SSDK_DEBUG("qca808x_phy_reg_read failed\n"); - return PHY_INVALID_DATA; - } - QCA808X_REG_UNLOCK; - - return phy_data; -} - -/****************************************************************************** -* -* qca808x_phy_mmd_write - PHY MMD register write -* -* PHY MMD register write -*/ -sw_error_t -qca808x_phy_mmd_write(a_uint32_t dev_id, a_uint32_t phy_id, - a_uint16_t mmd_num, a_uint16_t reg_id, a_uint16_t reg_val) -{ - sw_error_t rv; - a_uint32_t reg_id_c45 = QCA808X_REG_C45_ADDRESS(mmd_num, reg_id); -#if defined(IN_PHY_I2C_MODE) - a_uint32_t port_id = qca_ssdk_phy_addr_to_port(dev_id, phy_id); - a_uint8_t phy_access_type = hsl_port_phy_access_type_get(dev_id, port_id); - - if (phy_access_type == PHY_I2C_ACCESS) { - HSL_PHY_I2C_SET(rv, dev_id, phy_id, reg_id_c45, reg_val); - } - else -#endif - { - HSL_PHY_SET(rv, dev_id, phy_id, reg_id_c45, reg_val); - } - - return rv; -} - -/****************************************************************************** -* -* qca808x_phy_mmd_read - PHY MMD register read -* -* PHY MMD register read -*/ -a_uint16_t -qca808x_phy_mmd_read(a_uint32_t dev_id, a_uint32_t phy_id, - a_uint16_t mmd_num, a_uint16_t reg_id) -{ - sw_error_t rv = SW_OK; - a_uint16_t phy_data = 0; - a_uint32_t reg_id_c45 = QCA808X_REG_C45_ADDRESS(mmd_num, reg_id); -#if defined(IN_PHY_I2C_MODE) - a_uint32_t port_id = qca_ssdk_phy_addr_to_port(dev_id, phy_id); - a_uint8_t phy_access_type = hsl_port_phy_access_type_get(dev_id, port_id); - - if (phy_access_type == PHY_I2C_ACCESS) { - HSL_PHY_I2C_GET(rv, dev_id, phy_id, reg_id_c45, &phy_data); - } - else -#endif - { - HSL_PHY_GET(rv, dev_id, phy_id, reg_id_c45, &phy_data); - } - - if (rv != SW_OK) { - return PHY_INVALID_DATA; - } - - return phy_data; -} - -static sw_error_t -qca808x_phy_ms_random_seed_set(a_uint32_t dev_id, a_uint32_t phy_id) -{ - a_uint16_t phy_data; - sw_error_t rv = SW_OK; - - phy_data = qca808x_phy_debug_read(dev_id, phy_id, - QCA808X_DEBUG_LOCAL_SEED); - phy_data &= ~(QCA808X_MASTER_SLAVE_SEED_CFG); - phy_data |= (prandom_u32()%QCA808X_MASTER_SLAVE_SEED_RANGE) << 2; - SSDK_DEBUG("QCA808X_DEBUG_LOCAL_SEED:%x\n", phy_data); - rv = qca808x_phy_debug_write(dev_id, phy_id, - QCA808X_DEBUG_LOCAL_SEED, phy_data); - - return rv; -} - -static sw_error_t -qca808x_phy_ms_seed_enable(a_uint32_t dev_id, a_uint32_t phy_id, - a_bool_t enable) -{ - a_uint16_t phy_data; - sw_error_t rv = SW_OK; - - phy_data = qca808x_phy_debug_read(dev_id, phy_id, - QCA808X_DEBUG_LOCAL_SEED); - if(enable) - { - phy_data |= QCA808X_MASTER_SLAVE_SEED_ENABLE; - } - else - { - phy_data &= ~(QCA808X_MASTER_SLAVE_SEED_ENABLE); - } - rv = qca808x_phy_debug_write(dev_id, phy_id, - QCA808X_DEBUG_LOCAL_SEED, phy_data); - - return rv; -} - -a_bool_t -qca808x_phy_2500caps(a_uint32_t dev_id, a_uint32_t phy_id) -{ - a_uint16_t phy_data; - - phy_data = qca808x_phy_mmd_read(dev_id, phy_id, QCA808X_PHY_MMD1_NUM, - QCA808X_MMD1_PMA_CAP_REG); - - if (phy_data & QCA808X_STATUS_2500T_FD_CAPS) { - return A_TRUE; - } - - return A_FALSE; - -} - -/****************************************************************************** -* -* qca808x_phy_get status -* -* get phy status -*/ -sw_error_t -qca808x_phy_get_status(a_uint32_t dev_id, a_uint32_t phy_id, - struct port_phy_status *phy_status) -{ - a_uint16_t phy_data; - - phy_data = qca808x_phy_reg_read(dev_id, phy_id, QCA808X_PHY_SPEC_STATUS); - PHY_RTN_ON_READ_ERROR(phy_data); - - /*get phy link status*/ - if (phy_data & QCA808X_STATUS_LINK_PASS) { - phy_status->link_status = A_TRUE; - } - else { - phy_status->link_status = A_FALSE; - if (qca808x_phy_2500caps(dev_id, phy_id) == A_TRUE) { - SW_RTN_ON_ERROR( - qca808x_phy_ms_random_seed_set (dev_id, phy_id)); - /*protect logic, if MASTER_SLAVE_CONFIG_FAULT is 1, - then disable this logic*/ - phy_data = qca808x_phy_reg_read(dev_id, phy_id, - QCA808X_1000BASET_STATUS); - if ((phy_data & QCA808X_MASTER_SLAVE_CONFIG_FAULT) >> 15) - { - SW_RTN_ON_ERROR( - qca808x_phy_ms_seed_enable (dev_id, phy_id, A_FALSE)); - SSDK_INFO("master_slave_config_fault was set\n"); - } - } - - return SW_OK; - } - - /*get phy speed*/ - switch (phy_data & QCA808X_STATUS_SPEED_MASK) { - case QCA808X_STATUS_SPEED_2500MBS: - phy_status->speed = FAL_SPEED_2500; - break; - case QCA808X_STATUS_SPEED_1000MBS: - phy_status->speed = FAL_SPEED_1000; - break; - case QCA808X_STATUS_SPEED_100MBS: - phy_status->speed = FAL_SPEED_100; - break; - case QCA808X_STATUS_SPEED_10MBS: - phy_status->speed = FAL_SPEED_10; - break; - default: - return SW_READ_ERROR; - } - - /*get phy duplex*/ - if (phy_data & QCA808X_STATUS_FULL_DUPLEX) { - phy_status->duplex = FAL_FULL_DUPLEX; - } else { - phy_status->duplex = FAL_HALF_DUPLEX; - } - - /* get phy flowctrl resolution status */ - if (phy_data & QCA808X_PHY_RX_FLOWCTRL_STATUS) { - phy_status->rx_flowctrl = A_TRUE; - } else { - phy_status->rx_flowctrl = A_FALSE; - } - - if (phy_data & QCA808X_PHY_TX_FLOWCTRL_STATUS) { - phy_status->tx_flowctrl = A_TRUE; - } else { - phy_status->tx_flowctrl = A_FALSE; - } - - return SW_OK; -} - -/****************************************************************************** -* -* qca808x_phy_get_speed - Determines the speed of phy ports associated with the -* specified device. -*/ - -sw_error_t -qca808x_phy_get_speed(a_uint32_t dev_id, a_uint32_t phy_id, - fal_port_speed_t * speed) -{ - sw_error_t rv = SW_OK; - struct port_phy_status phy_status = {0}; - - rv = qca808x_phy_get_status(dev_id, phy_id, &phy_status); - PHY_RTN_ON_ERROR(rv); - - if (phy_status.link_status == A_TRUE) { - *speed = phy_status.speed; - } else { - *speed = FAL_SPEED_10; - } - - return rv; -} - -/****************************************************************************** -* -* qca808x_phy_set_force_speed - Force the speed of qca808x phy ports associated with the -* specified device. -*/ -sw_error_t -qca808x_phy_set_force_speed(a_uint32_t dev_id, a_uint32_t phy_id, - fal_port_speed_t speed) -{ - a_uint16_t phy_data1 = 0; - a_uint16_t phy_data2 = 0; - sw_error_t rv = SW_OK; - - /* the speed of qca808x controled by MMD1 PMA/PMD control register */ - phy_data1 = qca808x_phy_mmd_read(dev_id, phy_id, QCA808X_PHY_MMD1_NUM, - QCA808X_PHY_MMD1_PMA_CONTROL); - PHY_RTN_ON_READ_ERROR(phy_data1); - phy_data1 &= ~QCA808X_PMA_CONTROL_SPEED_MASK; - - phy_data2 = qca808x_phy_mmd_read(dev_id, phy_id, QCA808X_PHY_MMD1_NUM, - QCA808X_PHY_MMD1_PMA_TYPE); - PHY_RTN_ON_READ_ERROR(phy_data2); - phy_data2 &= ~QCA808X_PMA_TYPE_MASK; - - switch(speed) - { - case FAL_SPEED_2500: - phy_data1 |= QCA808X_PMA_CONTROL_2500M; - phy_data2 |= QCA808X_PMA_TYPE_2500M; - break; - case FAL_SPEED_1000: - phy_data1 |= QCA808X_PMA_CONTROL_1000M; - phy_data2 |= QCA808X_PMA_TYPE_1000M; - break; - case FAL_SPEED_100: - phy_data1 |= QCA808X_PMA_CONTROL_100M; - phy_data2 |= QCA808X_PMA_TYPE_100M; - break; - case FAL_SPEED_10: - phy_data1 |= QCA808X_PMA_CONTROL_10M; - phy_data2 |= QCA808X_PMA_TYPE_10M; - break; - default: - return SW_BAD_PARAM; - } - - rv = qca808x_phy_mmd_write(dev_id, phy_id, QCA808X_PHY_MMD1_NUM, - QCA808X_PHY_MMD1_PMA_CONTROL, phy_data1); - PHY_RTN_ON_ERROR(rv); - - rv = qca808x_phy_mmd_write(dev_id, phy_id, QCA808X_PHY_MMD1_NUM, - QCA808X_PHY_MMD1_PMA_TYPE, phy_data2); - - return rv; -} - -sw_error_t -_qca808x_phy_set_autoneg_adv_ext(a_uint32_t dev_id, a_uint32_t phy_id, a_uint32_t autoneg) -{ - a_uint16_t phy_data = 0; - sw_error_t rv = SW_OK; - - phy_data = qca808x_phy_mmd_read(dev_id, phy_id, QCA808X_PHY_MMD7_NUM, - QCA808X_PHY_MMD7_AUTONEGOTIATION_CONTROL); - PHY_RTN_ON_READ_ERROR(phy_data); - - if (autoneg & FAL_PHY_ADV_2500T_FD) { - phy_data |= QCA808X_ADVERTISE_2500FULL; - } else { - phy_data &= ~QCA808X_ADVERTISE_2500FULL; - } - - rv = qca808x_phy_mmd_write(dev_id, phy_id, QCA808X_PHY_MMD7_NUM, - QCA808X_PHY_MMD7_AUTONEGOTIATION_CONTROL, phy_data); - - return rv; - -} - -/****************************************************************************** -* -* qca808x_phy_set_speed - Determines the speed of phy ports associated with the -* specified device. -*/ -sw_error_t -qca808x_phy_set_speed(a_uint32_t dev_id, a_uint32_t phy_id, - fal_port_speed_t speed) -{ - a_uint16_t phy_data = 0; - fal_port_duplex_t old_duplex = QCA808X_CTRL_FULL_DUPLEX; - sw_error_t rv = SW_OK; - - phy_data = qca808x_phy_reg_read(dev_id, phy_id, QCA808X_PHY_CONTROL); - PHY_RTN_ON_READ_ERROR(phy_data); - - switch(speed) - { - case FAL_SPEED_2500: - case FAL_SPEED_1000: - if (speed == FAL_SPEED_2500) { - rv = _qca808x_phy_set_autoneg_adv_ext(dev_id, phy_id, - FAL_PHY_ADV_2500T_FD); - PHY_RTN_ON_ERROR(rv); - } else { - rv = _qca808x_phy_set_autoneg_adv_ext(dev_id, phy_id, - ~FAL_PHY_ADV_2500T_FD); - PHY_RTN_ON_ERROR(rv); - } - phy_data |= QCA808X_CTRL_FULL_DUPLEX; - phy_data |= QCA808X_CTRL_AUTONEGOTIATION_ENABLE; - phy_data |= QCA808X_CTRL_RESTART_AUTONEGOTIATION; - break; - case FAL_SPEED_100: - case FAL_SPEED_10: - /* set qca808x phy speed by pma control registers */ - rv = qca808x_phy_set_force_speed(dev_id, phy_id, speed); - PHY_RTN_ON_ERROR(rv); - rv = qca808x_phy_get_duplex(dev_id, phy_id, &old_duplex); - PHY_RTN_ON_ERROR(rv); - - if (old_duplex == FAL_FULL_DUPLEX) { - phy_data |= QCA808X_CTRL_FULL_DUPLEX; - } - else if (old_duplex == FAL_HALF_DUPLEX) { - phy_data &= ~QCA808X_CTRL_FULL_DUPLEX; - } - phy_data &= ~QCA808X_CTRL_AUTONEGOTIATION_ENABLE; - break; - default: - return SW_BAD_PARAM; - } - - rv = qca808x_phy_reg_write(dev_id, phy_id, QCA808X_PHY_CONTROL, phy_data); - - return rv; -} - -/****************************************************************************** -* -* qca808x_phy_set_duplex - Determines the duplex of phy ports associated with the -* specified device. -*/ -sw_error_t -qca808x_phy_set_duplex(a_uint32_t dev_id, a_uint32_t phy_id, - fal_port_duplex_t duplex) -{ - a_uint16_t phy_data = 0; - fal_port_speed_t old_speed; - sw_error_t rv = SW_OK; - - phy_data = qca808x_phy_reg_read(dev_id, phy_id, QCA808X_PHY_CONTROL); - PHY_RTN_ON_READ_ERROR(phy_data); - - rv = qca808x_phy_get_speed(dev_id, phy_id, &old_speed); - PHY_RTN_ON_ERROR(rv); - - switch(old_speed) - { - case FAL_SPEED_2500: - case FAL_SPEED_1000: - if (duplex == FAL_FULL_DUPLEX) { - phy_data |= QCA808X_CTRL_FULL_DUPLEX; - } else { - return SW_NOT_SUPPORTED; - } - phy_data |= QCA808X_CTRL_AUTONEGOTIATION_ENABLE; - - if (old_speed == FAL_SPEED_2500) { - rv = _qca808x_phy_set_autoneg_adv_ext(dev_id, phy_id, - FAL_PHY_ADV_2500T_FD); - PHY_RTN_ON_ERROR(rv); - } else { - rv = _qca808x_phy_set_autoneg_adv_ext(dev_id, phy_id, - ~FAL_PHY_ADV_2500T_FD); - PHY_RTN_ON_ERROR(rv); - } - break; - case FAL_SPEED_100: - case FAL_SPEED_10: - /* force the speed */ - rv = qca808x_phy_set_force_speed(dev_id, phy_id, old_speed); - PHY_RTN_ON_ERROR(rv); - phy_data &= ~QCA808X_CTRL_AUTONEGOTIATION_ENABLE; - if (duplex == FAL_FULL_DUPLEX) { - phy_data |= QCA808X_CTRL_FULL_DUPLEX; - } else { - phy_data &= ~QCA808X_CTRL_FULL_DUPLEX; - } - break; - default: - return SW_FAIL; - } - rv = qca808x_phy_reg_write(dev_id, phy_id, QCA808X_PHY_CONTROL, phy_data); - - return rv; -} - -/****************************************************************************** -* -* qca808x_phy_get_duplex - Determines the duplex of phy ports associated with the -* specified device. -*/ -sw_error_t -qca808x_phy_get_duplex(a_uint32_t dev_id, a_uint32_t phy_id, - fal_port_duplex_t * duplex) -{ - sw_error_t rv = SW_OK; - struct port_phy_status phy_status = {0}; - - rv = qca808x_phy_get_status(dev_id, phy_id, &phy_status); - PHY_RTN_ON_ERROR(rv); - - if (phy_status.link_status == A_TRUE) { - *duplex = phy_status.duplex; - } else { - *duplex = FAL_HALF_DUPLEX; - } - - return rv; -} - -/****************************************************************************** -* -* qca808x_phy_reset - reset the phy -* -* reset the phy -*/ -sw_error_t qca808x_phy_reset(a_uint32_t dev_id, a_uint32_t phy_id) -{ - a_uint16_t phy_data; - sw_error_t rv = SW_OK; - - phy_data = qca808x_phy_reg_read(dev_id, phy_id, QCA808X_PHY_CONTROL); - PHY_RTN_ON_READ_ERROR(phy_data); - - rv = qca808x_phy_reg_write(dev_id, phy_id, QCA808X_PHY_CONTROL, - phy_data | QCA808X_CTRL_SOFTWARE_RESET); - SW_RTN_ON_ERROR(rv); - /*the configure will lost when reset.*/ - rv = qca808x_phy_ms_seed_enable(dev_id, phy_id, A_TRUE); - - return rv; -} -/****************************************************************************** -* -* qca808x_phy_status - test to see if the specified phy link is alive -* -* RETURNS: -* A_TRUE --> link is alive -* A_FALSE --> link is down -*/ -a_bool_t qca808x_phy_get_link_status(a_uint32_t dev_id, a_uint32_t phy_id) -{ - struct port_phy_status phy_status = {0}; - sw_error_t rv = SW_OK; - - rv = qca808x_phy_get_status(dev_id, phy_id, &phy_status); - if (rv == SW_OK) { - return phy_status.link_status; - } else { - return A_FALSE; - } -} -#ifndef IN_PORTCONTROL_MINI -/****************************************************************************** -* -* qca808x_phy_cdt - cable diagnostic test -* -* cable diagnostic test -*/ - -static inline fal_cable_status_t _phy_cdt_status_mapping(a_uint16_t status) -{ - fal_cable_status_t status_mapping = FAL_CABLE_STATUS_INVALID; - - switch (status) { - case 0: - status_mapping = FAL_CABLE_STATUS_INVALID; - break; - case 1: - status_mapping = FAL_CABLE_STATUS_NORMAL; - break; - case 2: - status_mapping = FAL_CABLE_STATUS_OPENED; - break; - case 3: - status_mapping = FAL_CABLE_STATUS_SHORT; - break; - } - - return status_mapping; -} - -static sw_error_t qca808x_phy_cdt_start(a_uint32_t dev_id, a_uint32_t phy_id) -{ - a_uint16_t status = 0; - a_uint16_t ii = 100; - sw_error_t rv = SW_OK; - - /* RUN CDT */ - rv = qca808x_phy_reg_write(dev_id, phy_id, QCA808X_PHY_CDT_CONTROL, - QCA808X_RUN_CDT | QCA808X_CABLE_LENGTH_UNIT); - PHY_RTN_ON_ERROR(rv); - - do { - aos_mdelay(30); - status = - qca808x_phy_reg_read(dev_id, phy_id, QCA808X_PHY_CDT_CONTROL); - PHY_RTN_ON_READ_ERROR(status); - } - while ((status & QCA808X_RUN_CDT) && (--ii)); - - if (ii == 0) { - return SW_TIMEOUT; - } else { - return SW_OK; - } -} - -sw_error_t -qca808x_phy_cdt(a_uint32_t dev_id, a_uint32_t phy_id, a_uint32_t mdi_pair, - fal_cable_status_t * cable_status, a_uint32_t * cable_len) -{ - a_uint16_t cable_delta_time = 0; - a_uint16_t status; - sw_error_t rv; - - if ((mdi_pair >= QCA808X_MDI_PAIR_NUM)) { - return SW_BAD_PARAM; - } - - rv = qca808x_phy_cdt_start(dev_id, phy_id); - - if (rv != SW_OK) { - *cable_status = FAL_CABLE_STATUS_INVALID; - *cable_len = 0; - return rv; - } - - /* Get cable status */ - status = qca808x_phy_mmd_read(dev_id, phy_id, QCA808X_PHY_MMD3_NUM, - QCA808X_PHY_CDT_STATUS); - PHY_RTN_ON_READ_ERROR(status); - - switch (mdi_pair) { - case 0: - *cable_status = - _phy_cdt_status_mapping((status >> 12) & 0x3); - cable_delta_time = - qca808x_phy_mmd_read(dev_id, phy_id, QCA808X_PHY_MMD3_NUM, - QCA808X_PHY_CDT_DIAG_PAIR0); - PHY_RTN_ON_READ_ERROR(cable_delta_time); - - break; - case 1: - *cable_status = - _phy_cdt_status_mapping((status >> 8) & 0x3); - cable_delta_time = - qca808x_phy_mmd_read(dev_id, phy_id, QCA808X_PHY_MMD3_NUM, - QCA808X_PHY_CDT_DIAG_PAIR1); - PHY_RTN_ON_READ_ERROR(cable_delta_time); - - break; - case 2: - *cable_status = - _phy_cdt_status_mapping((status >> 4) & 0x3); - cable_delta_time = - qca808x_phy_mmd_read(dev_id, phy_id, QCA808X_PHY_MMD3_NUM, - QCA808X_PHY_CDT_DIAG_PAIR2); - PHY_RTN_ON_READ_ERROR(cable_delta_time); - - break; - case 3: - *cable_status = - _phy_cdt_status_mapping(status & 0x3); - cable_delta_time = - qca808x_phy_mmd_read(dev_id, phy_id, QCA808X_PHY_MMD3_NUM, - QCA808X_PHY_CDT_DIAG_PAIR3); - PHY_RTN_ON_READ_ERROR(cable_delta_time); - - break; - } - - /* the actual cable length equals to CableDeltaTime * 0.824 */ - *cable_len = ((cable_delta_time & 0xff) * 824) / 1000; - - return rv; -} - -/****************************************************************************** -* -* qca808x_phy_set_mdix - -* -* set phy mdix configuraiton -*/ -sw_error_t -qca808x_phy_set_mdix(a_uint32_t dev_id, a_uint32_t phy_id, - fal_port_mdix_mode_t mode) -{ - a_uint16_t phy_data; - sw_error_t rv; - - phy_data = qca808x_phy_reg_read(dev_id, phy_id, QCA808X_PHY_SPEC_CONTROL); - PHY_RTN_ON_READ_ERROR(phy_data); - - if (mode == PHY_MDIX_AUTO) { - phy_data |= QCA808X_PHY_MDIX_AUTO; - } else if (mode == PHY_MDIX_MDIX) { - phy_data &= ~QCA808X_PHY_MDIX_AUTO; - phy_data |= QCA808X_PHY_MDIX; - } else if (mode == PHY_MDIX_MDI) { - phy_data &= ~QCA808X_PHY_MDIX_AUTO; - } else { - return SW_BAD_PARAM; - } - - rv = qca808x_phy_reg_write(dev_id, phy_id, QCA808X_PHY_SPEC_CONTROL, phy_data); - PHY_RTN_ON_ERROR(rv); - - rv = qca808x_phy_reset(dev_id, phy_id); - return rv; -} - -/****************************************************************************** -* -* qca808x_phy_get_mdix -* -* get phy mdix configuration -*/ -sw_error_t -qca808x_phy_get_mdix(a_uint32_t dev_id, a_uint32_t phy_id, - fal_port_mdix_mode_t * mode) -{ - a_uint16_t phy_data; - - phy_data = qca808x_phy_reg_read(dev_id, phy_id, QCA808X_PHY_SPEC_CONTROL); - PHY_RTN_ON_READ_ERROR(phy_data); - - if ((phy_data & QCA808X_PHY_MDIX_AUTO) == QCA808X_PHY_MDIX_AUTO) { - *mode = PHY_MDIX_AUTO; - } else if ((phy_data & QCA808X_PHY_MDIX) == QCA808X_PHY_MDIX) { - *mode = PHY_MDIX_MDIX; - } else { - *mode = PHY_MDIX_MDI; - } - - return SW_OK; - -} - -/****************************************************************************** -* -* qca808x_phy_get_mdix status -* -* get phy mdix status -*/ -sw_error_t -qca808x_phy_get_mdix_status(a_uint32_t dev_id, a_uint32_t phy_id, - fal_port_mdix_status_t * mode) -{ - a_uint16_t phy_data; - - phy_data = qca808x_phy_reg_read(dev_id, phy_id, QCA808X_PHY_SPEC_STATUS); - PHY_RTN_ON_READ_ERROR(phy_data); - - *mode = - (phy_data & QCA808X_PHY_MDIX_STATUS) ? PHY_MDIX_STATUS_MDIX : - PHY_MDIX_STATUS_MDI; - - return SW_OK; - -} - -/****************************************************************************** -* -* qca808x_phy_set_local_loopback -* -* set phy local loopback -*/ -sw_error_t -qca808x_phy_set_local_loopback(a_uint32_t dev_id, a_uint32_t phy_id, - a_bool_t enable) -{ - a_uint16_t phy_data; - fal_port_speed_t old_speed; - sw_error_t rv = SW_OK; - - phy_data = qca808x_phy_reg_read(dev_id, phy_id, QCA808X_PHY_CONTROL); - PHY_RTN_ON_READ_ERROR(phy_data); - - if (enable == A_TRUE) { - /* get the link speed first, then force the corresponding - * speed to enable local loopback */ - rv = qca808x_phy_get_speed(dev_id, phy_id, &old_speed); - PHY_RTN_ON_ERROR(rv); - rv = qca808x_phy_set_force_speed(dev_id, phy_id, old_speed); - PHY_RTN_ON_ERROR(rv); - - phy_data &= ~QCA808X_CTRL_AUTONEGOTIATION_ENABLE; - phy_data |= QCA808X_LOCAL_LOOPBACK_ENABLE; - phy_data |= QCA808X_CTRL_FULL_DUPLEX; - } else { - phy_data = QCA808X_COMMON_CTRL; - } - - rv = qca808x_phy_reg_write(dev_id, phy_id, QCA808X_PHY_CONTROL, phy_data); - return rv; -} - -/****************************************************************************** -* -* qca808x_phy_get_local_loopback -* -* get phy local loopback -*/ -sw_error_t -qca808x_phy_get_local_loopback(a_uint32_t dev_id, a_uint32_t phy_id, - a_bool_t * enable) -{ - a_uint16_t phy_data; - - phy_data = qca808x_phy_reg_read(dev_id, phy_id, QCA808X_PHY_CONTROL); - PHY_RTN_ON_READ_ERROR(phy_data); - - if (phy_data & QCA808X_LOCAL_LOOPBACK_ENABLE) { - *enable = A_TRUE; - } else { - *enable = A_FALSE; - } - - return SW_OK; - -} - -/****************************************************************************** -* -* qca808x_phy_set_remote_loopback -* -* set phy remote loopback -*/ -sw_error_t -qca808x_phy_set_remote_loopback(a_uint32_t dev_id, a_uint32_t phy_id, - a_bool_t enable) -{ - a_uint16_t phy_data; - sw_error_t rv = SW_OK; - - phy_data = qca808x_phy_mmd_read(dev_id, phy_id, QCA808X_PHY_MMD3_NUM, - QCA808X_PHY_MMD3_ADDR_REMOTE_LOOPBACK_CTRL); - PHY_RTN_ON_READ_ERROR(phy_data); - - if (enable == A_TRUE) { - phy_data |= QCA808X_PHY_REMOTE_LOOPBACK_EN; - } else { - phy_data &= ~QCA808X_PHY_REMOTE_LOOPBACK_EN; - } - - rv = qca808x_phy_mmd_write(dev_id, phy_id, QCA808X_PHY_MMD3_NUM, - QCA808X_PHY_MMD3_ADDR_REMOTE_LOOPBACK_CTRL, - phy_data); - return rv; - -} - -/****************************************************************************** -* -* qca808x_phy_get_remote_loopback -* -* get phy remote loopback -*/ -sw_error_t -qca808x_phy_get_remote_loopback(a_uint32_t dev_id, a_uint32_t phy_id, - a_bool_t * enable) -{ - a_uint16_t phy_data; - - phy_data = qca808x_phy_mmd_read(dev_id, phy_id, QCA808X_PHY_MMD3_NUM, - QCA808X_PHY_MMD3_ADDR_REMOTE_LOOPBACK_CTRL); - PHY_RTN_ON_READ_ERROR(phy_data); - - if (phy_data & QCA808X_PHY_REMOTE_LOOPBACK_EN) { - *enable = A_TRUE; - } else { - *enable = A_FALSE; - } - - return SW_OK; - -} -#endif -/****************************************************************************** -* -* qca808x_set_autoneg_adv - set the phy autoneg Advertisement -* -*/ -sw_error_t -qca808x_phy_set_autoneg_adv(a_uint32_t dev_id, a_uint32_t phy_id, - a_uint32_t autoneg) -{ - a_uint16_t phy_data = 0; - sw_error_t rv = SW_OK; - - phy_data = qca808x_phy_reg_read(dev_id, phy_id, - QCA808X_AUTONEG_ADVERT); - PHY_RTN_ON_READ_ERROR(phy_data); - - phy_data &= ~QCA808X_ADVERTISE_MEGA_ALL; - - if (autoneg & FAL_PHY_ADV_100TX_FD) { - phy_data |= QCA808X_ADVERTISE_100FULL; - } - - if (autoneg & FAL_PHY_ADV_100TX_HD) { - phy_data |= QCA808X_ADVERTISE_100HALF; - } - - if (autoneg & FAL_PHY_ADV_10T_FD) { - phy_data |= QCA808X_ADVERTISE_10FULL; - } - - if (autoneg & FAL_PHY_ADV_10T_HD) { - phy_data |= QCA808X_ADVERTISE_10HALF; - } - - if (autoneg & FAL_PHY_ADV_PAUSE) { - phy_data |= QCA808X_ADVERTISE_PAUSE; - } - - if (autoneg & FAL_PHY_ADV_ASY_PAUSE) { - phy_data |= QCA808X_ADVERTISE_ASYM_PAUSE; - } - rv = qca808x_phy_reg_write(dev_id, phy_id, QCA808X_AUTONEG_ADVERT, - phy_data); - PHY_RTN_ON_ERROR(rv); - - phy_data = qca808x_phy_reg_read(dev_id, phy_id, - QCA808X_1000BASET_CONTROL); - PHY_RTN_ON_READ_ERROR(phy_data); - - phy_data &= ~QCA808X_ADVERTISE_1000FULL; - phy_data &= ~QCA808X_ADVERTISE_1000HALF; - - if (autoneg & FAL_PHY_ADV_1000T_FD) { - phy_data |= QCA808X_ADVERTISE_1000FULL; - } - - rv = qca808x_phy_reg_write(dev_id, phy_id, QCA808X_1000BASET_CONTROL, - phy_data); - PHY_RTN_ON_ERROR(rv); - - if (qca808x_phy_2500caps(dev_id, phy_id) == A_TRUE) { - rv = _qca808x_phy_set_autoneg_adv_ext(dev_id, phy_id, autoneg); - } - - return rv; -} - -sw_error_t -_qca808x_phy_get_autoneg_adv_ext(a_uint32_t dev_id, a_uint32_t phy_id, a_uint16_t *phy_data) -{ - *phy_data = qca808x_phy_mmd_read(dev_id, phy_id, QCA808X_PHY_MMD7_NUM, - QCA808X_PHY_MMD7_AUTONEGOTIATION_CONTROL); - PHY_RTN_ON_READ_ERROR(*phy_data); - - return SW_OK; -} - -/****************************************************************************** -* -* qca808x_get_autoneg_adv - get the phy autoneg Advertisement -* -*/ -sw_error_t -qca808x_phy_get_autoneg_adv(a_uint32_t dev_id, a_uint32_t phy_id, - a_uint32_t * autoneg) -{ - a_uint16_t phy_data = 0; - sw_error_t rv = SW_OK; - - *autoneg = 0; - phy_data = - qca808x_phy_reg_read(dev_id, phy_id, QCA808X_AUTONEG_ADVERT); - PHY_RTN_ON_READ_ERROR(phy_data); - - if (phy_data & QCA808X_ADVERTISE_100FULL) { - *autoneg |= FAL_PHY_ADV_100TX_FD; - } - - if (phy_data & QCA808X_ADVERTISE_100HALF) { - *autoneg |= FAL_PHY_ADV_100TX_HD; - } - - if (phy_data & QCA808X_ADVERTISE_10FULL) { - *autoneg |= FAL_PHY_ADV_10T_FD; - } - - if (phy_data & QCA808X_ADVERTISE_10HALF) { - *autoneg |= FAL_PHY_ADV_10T_HD; - } - - if (phy_data & QCA808X_ADVERTISE_PAUSE) { - *autoneg |= FAL_PHY_ADV_PAUSE; - } - - if (phy_data & QCA808X_ADVERTISE_ASYM_PAUSE) { - *autoneg |= FAL_PHY_ADV_ASY_PAUSE; - } - - phy_data = qca808x_phy_reg_read(dev_id, phy_id, - QCA808X_1000BASET_CONTROL); - PHY_RTN_ON_READ_ERROR(phy_data); - - if (phy_data & QCA808X_ADVERTISE_1000FULL) { - *autoneg |= FAL_PHY_ADV_1000T_FD; - } - - if (qca808x_phy_2500caps(dev_id, phy_id) == A_TRUE) { - rv = _qca808x_phy_get_autoneg_adv_ext(dev_id, phy_id, &phy_data); - if ((rv == SW_OK) && - (phy_data & QCA808X_ADVERTISE_2500FULL)) { - *autoneg |= FAL_PHY_ADV_2500T_FD; - } - } - - return rv; -} - -/****************************************************************************** -* -* qca808x_phy_autoneg_status - get the phy autoneg status -* -*/ -a_bool_t qca808x_phy_autoneg_status(a_uint32_t dev_id, a_uint32_t phy_id) -{ - a_uint16_t phy_data; - - phy_data = qca808x_phy_reg_read(dev_id, phy_id, QCA808X_PHY_CONTROL); - - if (phy_data & QCA808X_CTRL_AUTONEGOTIATION_ENABLE) { - return A_TRUE; - } - - return A_FALSE; -} - -/****************************************************************************** -* -* qca808x_restart_autoneg - restart the phy autoneg -* -*/ -sw_error_t qca808x_phy_restart_autoneg(a_uint32_t dev_id, a_uint32_t phy_id) -{ - a_uint16_t phy_data = 0; - sw_error_t rv = SW_OK; - - phy_data = qca808x_phy_reg_read(dev_id, phy_id, QCA808X_PHY_CONTROL); - PHY_RTN_ON_READ_ERROR(phy_data); - - phy_data |= QCA808X_CTRL_AUTONEGOTIATION_ENABLE; - rv = qca808x_phy_reg_write(dev_id, phy_id, QCA808X_PHY_CONTROL, - phy_data | QCA808X_CTRL_RESTART_AUTONEGOTIATION); - - return rv; -} - -/****************************************************************************** -* -* qca808x_phy_enable_autonego -* -*/ -sw_error_t qca808x_phy_enable_autoneg(a_uint32_t dev_id, a_uint32_t phy_id) -{ - a_uint16_t phy_data = 0; - sw_error_t rv = SW_OK; - - phy_data = qca808x_phy_reg_read(dev_id, phy_id, QCA808X_PHY_CONTROL); - PHY_RTN_ON_READ_ERROR(phy_data); - - rv = qca808x_phy_reg_write(dev_id, phy_id, QCA808X_PHY_CONTROL, - phy_data | QCA808X_CTRL_AUTONEGOTIATION_ENABLE); - - return rv; -} - -/****************************************************************************** -* -* qca808x_phy_get_phy_id - get the phy id -* -*/ -sw_error_t -qca808x_phy_get_phy_id(a_uint32_t dev_id, a_uint32_t phy_id, - a_uint32_t *phy_data) -{ - a_uint16_t org_id, rev_id; - org_id = qca808x_phy_reg_read(dev_id, phy_id, QCA808X_PHY_ID1); - PHY_RTN_ON_READ_ERROR(org_id); - - rev_id = qca808x_phy_reg_read(dev_id, phy_id, QCA808X_PHY_ID2); - PHY_RTN_ON_READ_ERROR(rev_id); - - *phy_data = ((org_id & 0xffff) << 16) | (rev_id & 0xffff); - - return SW_OK; -} - -/****************************************************************************** -* -* qca808x_phy_off - power off the phy -* -* Power off the phy -*/ -sw_error_t qca808x_phy_poweroff(a_uint32_t dev_id, a_uint32_t phy_id) -{ - a_uint16_t phy_data; - sw_error_t rv = SW_OK; - - phy_data = qca808x_phy_reg_read(dev_id, phy_id, QCA808X_PHY_CONTROL); - PHY_RTN_ON_READ_ERROR(phy_data); - - rv = qca808x_phy_reg_write(dev_id, phy_id, QCA808X_PHY_CONTROL, - phy_data | QCA808X_CTRL_POWER_DOWN); - return rv; -} - -/****************************************************************************** -* -* qca808x_phy_on - power on the phy -* -* Power on the phy -*/ -sw_error_t qca808x_phy_poweron(a_uint32_t dev_id, a_uint32_t phy_id) -{ - a_uint16_t phy_data; - sw_error_t rv = SW_OK; - - phy_data = qca808x_phy_reg_read(dev_id, phy_id, QCA808X_PHY_CONTROL); - PHY_RTN_ON_READ_ERROR(phy_data); - - rv = qca808x_phy_reg_write(dev_id, phy_id, QCA808X_PHY_CONTROL, - phy_data & ~QCA808X_CTRL_POWER_DOWN); - - aos_mdelay(200); - - return rv; -} -#ifndef IN_PORTCONTROL_MINI -/****************************************************************************** -* -* qca808x_phy_set_802.3az -* -* set 802.3az status -*/ -sw_error_t -qca808x_phy_set_8023az(a_uint32_t dev_id, a_uint32_t phy_id, a_bool_t enable) -{ - a_uint16_t phy_data; - sw_error_t rv = SW_OK; - - phy_data = qca808x_phy_mmd_read(dev_id, phy_id, QCA808X_PHY_MMD7_NUM, - QCA808X_PHY_MMD7_ADDR_8023AZ_EEE_CTRL); - PHY_RTN_ON_READ_ERROR(phy_data); - - if (enable == A_TRUE) { - phy_data |= QCA808X_PHY_8023AZ_EEE_1000BT; - phy_data |= QCA808X_PHY_8023AZ_EEE_100BT; - } else { - phy_data &= ~QCA808X_PHY_8023AZ_EEE_1000BT; - phy_data &= ~QCA808X_PHY_8023AZ_EEE_100BT; - } - - rv = qca808x_phy_mmd_write(dev_id, phy_id, QCA808X_PHY_MMD7_NUM, - QCA808X_PHY_MMD7_ADDR_8023AZ_EEE_CTRL, phy_data); - PHY_RTN_ON_ERROR(rv); - - rv = qca808x_phy_restart_autoneg(dev_id, phy_id); - - return rv; -} - -/****************************************************************************** -* -* qca808x_phy_get_8023az status -* -* get 8023az status -*/ -sw_error_t -qca808x_phy_get_8023az(a_uint32_t dev_id, a_uint32_t phy_id, a_bool_t * enable) -{ - a_uint16_t phy_data; - *enable = A_FALSE; - - phy_data = qca808x_phy_mmd_read(dev_id, phy_id, QCA808X_PHY_MMD7_NUM, - QCA808X_PHY_MMD7_ADDR_8023AZ_EEE_CTRL); - PHY_RTN_ON_READ_ERROR(phy_data); - - if ((phy_data & QCA808X_PHY_8023AZ_EEE_1000BT) && - (phy_data & QCA808X_PHY_8023AZ_EEE_100BT)) { - *enable = A_TRUE; - } - - return SW_OK; -} - -/****************************************************************************** -* -* _qca808x_phy_get_8023az_status status -* -* get 8023az status -*/ -sw_error_t -_qca808x_phy_get_8023az_status(a_uint32_t dev_id, a_uint32_t phy_id, a_bool_t * enable) -{ - a_uint16_t phy_data; - *enable = A_FALSE; - - phy_data = qca808x_phy_mmd_read(dev_id, phy_id, QCA808X_PHY_MMD3_NUM, - QCA808X_PHY_MMD3_ADDR_8023AZ_EEE_DB); - PHY_RTN_ON_READ_ERROR(phy_data); - - if (phy_data & QCA808X_PHY_8023AZ_EEE_LP_STAT) { - *enable = A_TRUE; - } - - return SW_OK; -} - -/****************************************************************************** -* -* qca808x_phy_set wol frame mac address -* -* set phy wol frame mac address -*/ -sw_error_t -qca808x_phy_set_magic_frame_mac(a_uint32_t dev_id, a_uint32_t phy_id, - fal_mac_addr_t * mac) -{ - a_uint16_t phy_data1; - a_uint16_t phy_data2; - a_uint16_t phy_data3; - sw_error_t rv = SW_OK; - - phy_data1 = (mac->uc[0] << 8) | mac->uc[1]; - phy_data2 = (mac->uc[2] << 8) | mac->uc[3]; - phy_data3 = (mac->uc[4] << 8) | mac->uc[5]; - - rv = qca808x_phy_mmd_write(dev_id, phy_id, QCA808X_PHY_MMD3_NUM, - QCA808X_PHY_MMD3_WOL_MAGIC_MAC_CTRL1, phy_data1); - PHY_RTN_ON_ERROR(rv); - - rv = qca808x_phy_mmd_write(dev_id, phy_id, QCA808X_PHY_MMD3_NUM, - QCA808X_PHY_MMD3_WOL_MAGIC_MAC_CTRL2, phy_data2); - PHY_RTN_ON_ERROR(rv); - - rv = qca808x_phy_mmd_write(dev_id, phy_id, QCA808X_PHY_MMD3_NUM, - QCA808X_PHY_MMD3_WOL_MAGIC_MAC_CTRL3, phy_data3); - - return rv; -} - -/****************************************************************************** -* -* qca808x_phy_get wol frame mac address -* -* get phy wol frame mac address -*/ -sw_error_t -qca808x_phy_get_magic_frame_mac(a_uint32_t dev_id, a_uint32_t phy_id, - fal_mac_addr_t * mac) -{ - a_uint16_t phy_data1; - a_uint16_t phy_data2; - a_uint16_t phy_data3; - - phy_data1 = qca808x_phy_mmd_read(dev_id, phy_id, QCA808X_PHY_MMD3_NUM, - QCA808X_PHY_MMD3_WOL_MAGIC_MAC_CTRL1); - PHY_RTN_ON_READ_ERROR(phy_data1); - - phy_data2 = qca808x_phy_mmd_read(dev_id, phy_id, QCA808X_PHY_MMD3_NUM, - QCA808X_PHY_MMD3_WOL_MAGIC_MAC_CTRL2); - PHY_RTN_ON_READ_ERROR(phy_data2); - - phy_data3 = qca808x_phy_mmd_read(dev_id, phy_id, QCA808X_PHY_MMD3_NUM, - QCA808X_PHY_MMD3_WOL_MAGIC_MAC_CTRL3); - PHY_RTN_ON_READ_ERROR(phy_data3); - - mac->uc[0] = (phy_data1 >> 8); - mac->uc[1] = (phy_data1 & 0x00ff); - mac->uc[2] = (phy_data2 >> 8); - mac->uc[3] = (phy_data2 & 0x00ff); - mac->uc[4] = (phy_data3 >> 8); - mac->uc[5] = (phy_data3 & 0x00ff); - - return SW_OK; -} - -/****************************************************************************** -* -* qca808x_phy_set wol enable or disable -* -* set phy wol enable or disable -*/ -sw_error_t -qca808x_phy_set_wol_status(a_uint32_t dev_id, a_uint32_t phy_id, a_bool_t enable) -{ - a_uint16_t phy_data; - sw_error_t rv = SW_OK; - - phy_data = qca808x_phy_mmd_read(dev_id, phy_id, QCA808X_PHY_MMD3_NUM, - QCA808X_PHY_MMD3_WOL_CTRL); - PHY_RTN_ON_READ_ERROR(phy_data); - - if (enable == A_TRUE) { - phy_data |= QCA808X_PHY_WOL_EN; - } else { - phy_data &= ~QCA808X_PHY_WOL_EN; - } - - rv = qca808x_phy_mmd_write(dev_id, phy_id, QCA808X_PHY_MMD3_NUM, - QCA808X_PHY_MMD3_WOL_CTRL, phy_data); - - return rv; -} - -/****************************************************************************** -* -* qca808x_phy_get_wol status -* -* get wol status -*/ -sw_error_t -qca808x_phy_get_wol_status(a_uint32_t dev_id, a_uint32_t phy_id, a_bool_t * enable) -{ - a_uint16_t phy_data; - - *enable = A_FALSE; - - phy_data = qca808x_phy_mmd_read(dev_id, phy_id, QCA808X_PHY_MMD3_NUM, - QCA808X_PHY_MMD3_WOL_CTRL); - PHY_RTN_ON_READ_ERROR(phy_data); - - if (phy_data & QCA808X_PHY_WOL_EN) { - *enable = A_TRUE; - } - - return SW_OK; -} - -/****************************************************************************** -* -* qca808x_phy_set_hibernate - set hibernate status -* -* set hibernate status -*/ -sw_error_t -qca808x_phy_set_hibernate(a_uint32_t dev_id, a_uint32_t phy_id, a_bool_t enable) -{ - a_uint16_t phy_data; - sw_error_t rv = SW_OK; - - phy_data = qca808x_phy_debug_read(dev_id, phy_id, - QCA808X_DEBUG_PHY_HIBERNATION_CTRL); - PHY_RTN_ON_READ_ERROR(phy_data); - - if (enable == A_TRUE) { - phy_data |= QCA808X_PHY_HIBERNATION_CFG; - } else { - phy_data &= ~QCA808X_PHY_HIBERNATION_CFG; - } - - rv = qca808x_phy_debug_write(dev_id, phy_id, - QCA808X_DEBUG_PHY_HIBERNATION_CTRL, phy_data); - - return rv; -} - -/****************************************************************************** -* -* qca808x_phy_get_hibernate - get hibernate status -* -* get hibernate status -*/ -sw_error_t -qca808x_phy_get_hibernate(a_uint32_t dev_id, a_uint32_t phy_id, - a_bool_t * enable) -{ - a_uint16_t phy_data; - - *enable = A_FALSE; - - phy_data = qca808x_phy_debug_read(dev_id, phy_id, - QCA808X_DEBUG_PHY_HIBERNATION_CTRL); - PHY_RTN_ON_READ_ERROR(phy_data); - - if (phy_data & QCA808X_PHY_HIBERNATION_CFG) { - *enable = A_TRUE; - } - - return SW_OK; -} - -/****************************************************************************** -* -* _qca808x_phy_get_hibernate_status - get hibernate status -* -* get hibernate status -*/ -sw_error_t -_qca808x_phy_get_hibernate_status(a_uint32_t dev_id, a_uint32_t phy_id, - a_bool_t * enable) -{ - a_uint16_t phy_data; - - *enable = A_TRUE; - - phy_data = qca808x_phy_debug_read(dev_id, phy_id, - QCA808X_DEBUG_PHY_HIBERNATION_STAT); - PHY_RTN_ON_READ_ERROR(phy_data); - - if (phy_data & QCA808X_PHY_HIBERNATION_STAT_EN) { - *enable = A_FALSE; - } - - return SW_OK; -} -#endif -/****************************************************************************** -* -* qca808x_phy_interface mode set -* -* set qca808x phy interface mode -*/ -sw_error_t -qca808x_phy_interface_set_mode(a_uint32_t dev_id, a_uint32_t phy_id, - fal_port_interface_mode_t interface_mode) -{ - /* qca808x phy will automatically switch the interface mode according - * to the speed, 2.5G works on SGMII+, other works on SGMII. - */ - - return SW_OK; -} - -/****************************************************************************** -* -* qca808x_phy_interface mode get -* -* get qca808x phy interface mode -*/ -sw_error_t -qca808x_phy_interface_get_mode(a_uint32_t dev_id, a_uint32_t phy_id, - fal_port_interface_mode_t *interface_mode) -{ - a_uint16_t phy_data; - phy_data = qca808x_phy_reg_read(dev_id, phy_id, QCA808X_PHY_CHIP_CONFIG); - PHY_RTN_ON_READ_ERROR(phy_data); - - phy_data &= QCA808X_PHY_CHIP_MODE_CFG; - if (phy_data == QCA808X_PHY_SGMII_BASET) { - *interface_mode = PHY_SGMII_BASET; - } - - return SW_OK; -} - -/****************************************************************************** -* -* qca808x_phy_interface mode status get -* -* get qca808x phy interface mode status -*/ -sw_error_t -qca808x_phy_interface_get_mode_status(a_uint32_t dev_id, a_uint32_t phy_id, - fal_port_interface_mode_t *interface_mode_status) -{ - a_uint16_t phy_data; - phy_data = qca808x_phy_reg_read(dev_id, phy_id, QCA808X_PHY_CHIP_CONFIG); - PHY_RTN_ON_READ_ERROR(phy_data); - - phy_data &= QCA808X_PHY_MODE_MASK; - switch (phy_data) { - case QCA808X_PHY_SGMII_PLUS_MODE: - *interface_mode_status = PORT_SGMII_PLUS; - break; - case QCA808X_PHY_SGMII_MODE: - *interface_mode_status = PHY_SGMII_BASET; - break; - default: - *interface_mode_status = PORT_INTERFACE_MODE_MAX; - break; - } - - return SW_OK; -} -#ifndef IN_PORTCONTROL_MINI -/****************************************************************************** -* -* qca808x_phy_set_intr_mask - Set interrupt mask with the -* specified device. -*/ -sw_error_t -qca808x_phy_set_intr_mask(a_uint32_t dev_id, a_uint32_t phy_id, - a_uint32_t intr_mask_flag) -{ - a_uint16_t phy_data = 0; - sw_error_t rv = SW_OK; - - phy_data = qca808x_phy_reg_read(dev_id, phy_id, QCA808X_PHY_INTR_MASK); - PHY_RTN_ON_READ_ERROR(phy_data); - - if (intr_mask_flag & FAL_PHY_INTR_STATUS_UP_CHANGE) { - phy_data |= QCA808X_INTR_STATUS_UP_CHANGE; - } else { - phy_data &= (~QCA808X_INTR_STATUS_UP_CHANGE); - } - - if (intr_mask_flag & FAL_PHY_INTR_STATUS_DOWN_CHANGE) { - phy_data |= QCA808X_INTR_STATUS_DOWN_CHANGE; - } else { - phy_data &= (~QCA808X_INTR_STATUS_DOWN_CHANGE); - } - - if (intr_mask_flag & FAL_PHY_INTR_SPEED_CHANGE) { - phy_data |= QCA808X_INTR_SPEED_CHANGE; - } else { - phy_data &= (~QCA808X_INTR_SPEED_CHANGE); - } - - if (intr_mask_flag & FAL_PHY_INTR_BX_FX_STATUS_UP_CHANGE) { - phy_data |= QCA808X_INTR_LINK_SUCCESS_SG; - } else { - phy_data &= (~QCA808X_INTR_LINK_SUCCESS_SG); - } - - if (intr_mask_flag & FAL_PHY_INTR_BX_FX_STATUS_DOWN_CHANGE) { - phy_data |= QCA808X_INTR_LINK_FAIL_SG; - } else { - phy_data &= (~QCA808X_INTR_LINK_FAIL_SG); - } - - if (intr_mask_flag & FAL_PHY_INTR_WOL_STATUS) { - phy_data |= QCA808X_INTR_WOL; - } else { - phy_data &= (~QCA808X_INTR_WOL); - } - - if (intr_mask_flag & FAL_PHY_INTR_POE_STATUS) { - phy_data |= QCA808X_INTR_POE; - } else { - phy_data &= (~QCA808X_INTR_POE); - } - - rv = qca808x_phy_reg_write(dev_id, phy_id, QCA808X_PHY_INTR_MASK, phy_data); - return rv; -} - -/****************************************************************************** -* -* qca808x_phy_get_intr_mask - Get interrupt mask with the -* specified device. -*/ -sw_error_t -qca808x_phy_get_intr_mask(a_uint32_t dev_id, a_uint32_t phy_id, - a_uint32_t * intr_mask_flag) -{ - a_uint16_t phy_data = 0; - - phy_data = qca808x_phy_reg_read(dev_id, phy_id, QCA808X_PHY_INTR_MASK); - PHY_RTN_ON_READ_ERROR(phy_data); - - *intr_mask_flag = 0; - if (phy_data & QCA808X_INTR_STATUS_UP_CHANGE) { - *intr_mask_flag |= FAL_PHY_INTR_STATUS_UP_CHANGE; - } - - if (phy_data & QCA808X_INTR_STATUS_DOWN_CHANGE) { - *intr_mask_flag |= FAL_PHY_INTR_STATUS_DOWN_CHANGE; - } - - if (phy_data & QCA808X_INTR_SPEED_CHANGE) { - *intr_mask_flag |= FAL_PHY_INTR_SPEED_CHANGE; - } - - if (phy_data & QCA808X_INTR_LINK_SUCCESS_SG) { - *intr_mask_flag |= FAL_PHY_INTR_BX_FX_STATUS_UP_CHANGE; - } - - if (phy_data & QCA808X_INTR_LINK_FAIL_SG) { - *intr_mask_flag |= FAL_PHY_INTR_BX_FX_STATUS_DOWN_CHANGE; - } - - if (phy_data & QCA808X_INTR_WOL) { - *intr_mask_flag |= FAL_PHY_INTR_WOL_STATUS; - } - - if (phy_data & QCA808X_INTR_POE) { - *intr_mask_flag |= FAL_PHY_INTR_POE_STATUS; - } - - return SW_OK; -} - -/****************************************************************************** -* -* qca808x_phy_get_intr_status - Get interrupt status with the -* specified device. -*/ -sw_error_t -qca808x_phy_get_intr_status(a_uint32_t dev_id, a_uint32_t phy_id, - a_uint32_t * intr_status_flag) -{ - a_uint16_t phy_data = 0; - - phy_data = qca808x_phy_reg_read(dev_id, phy_id, QCA808X_PHY_INTR_STATUS); - PHY_RTN_ON_READ_ERROR(phy_data); - - *intr_status_flag = 0; - if (phy_data & QCA808X_INTR_STATUS_UP_CHANGE) { - *intr_status_flag |= FAL_PHY_INTR_STATUS_UP_CHANGE; - } - - if (phy_data & QCA808X_INTR_STATUS_DOWN_CHANGE) { - *intr_status_flag |= FAL_PHY_INTR_STATUS_DOWN_CHANGE; - } - - if (phy_data & QCA808X_INTR_SPEED_CHANGE) { - *intr_status_flag |= FAL_PHY_INTR_SPEED_CHANGE; - } - - if (phy_data & QCA808X_INTR_LINK_SUCCESS_SG) { - *intr_status_flag |= FAL_PHY_INTR_BX_FX_STATUS_UP_CHANGE; - } - - if (phy_data & QCA808X_INTR_LINK_FAIL_SG) { - *intr_status_flag |= FAL_PHY_INTR_BX_FX_STATUS_DOWN_CHANGE; - } - - if (phy_data & QCA808X_INTR_WOL) { - *intr_status_flag |= FAL_PHY_INTR_WOL_STATUS; - } - - if (phy_data & QCA808X_INTR_POE) { - *intr_status_flag |= FAL_PHY_INTR_POE_STATUS; - } - - return SW_OK; -} - -/****************************************************************************** -* -* qca808x_phy_set_counter - set counter status -* -* set counter status -*/ -sw_error_t -qca808x_phy_set_counter(a_uint32_t dev_id, a_uint32_t phy_id, a_bool_t enable) -{ - a_uint16_t phy_data; - sw_error_t rv = SW_OK; - - phy_data = qca808x_phy_mmd_read(dev_id, phy_id, QCA808X_PHY_MMD7_NUM, - QCA808X_PHY_MMD7_COUNTER_CTRL); - PHY_RTN_ON_READ_ERROR(phy_data); - - if (enable == A_TRUE) { - phy_data |= QCA808X_PHY_FRAME_CHECK_EN; - phy_data |= QCA808X_PHY_XMIT_MAC_CNT_SELFCLR; - } else { - phy_data &= ~QCA808X_PHY_FRAME_CHECK_EN; - phy_data &= ~QCA808X_PHY_XMIT_MAC_CNT_SELFCLR; - } - - rv = qca808x_phy_mmd_write(dev_id, phy_id, QCA808X_PHY_MMD7_NUM, - QCA808X_PHY_MMD7_COUNTER_CTRL, phy_data); - - return rv; -} - -/****************************************************************************** -* -* qca808x_phy_get_counter_status - get counter status -* -* set counter status -*/ -sw_error_t -qca808x_phy_get_counter(a_uint32_t dev_id, a_uint32_t phy_id, - a_bool_t * enable) -{ - a_uint16_t phy_data; - - phy_data = qca808x_phy_mmd_read(dev_id, phy_id, QCA808X_PHY_MMD7_NUM, - QCA808X_PHY_MMD7_COUNTER_CTRL); - PHY_RTN_ON_READ_ERROR(phy_data); - - if (phy_data & QCA808X_PHY_FRAME_CHECK_EN) { - *enable = A_TRUE; - } else { - *enable = A_FALSE; - } - - return SW_OK; -} - -/****************************************************************************** -* -* qca808x_phy_show show counter statistics -* -* show counter statistics -*/ -sw_error_t -qca808x_phy_show_counter(a_uint32_t dev_id, a_uint32_t phy_id, - fal_port_counter_info_t * counter_infor) -{ - a_uint16_t ingress_high_counter = 0; - a_uint16_t ingress_low_counter = 0; - a_uint16_t egress_high_counter = 0; - a_uint16_t egress_low_counter = 0; - - ingress_high_counter = qca808x_phy_mmd_read(dev_id, phy_id, QCA808X_PHY_MMD7_NUM, - QCA808X_PHY_MMD7_INGRESS_COUNTER_HIGH); - ingress_low_counter = qca808x_phy_mmd_read(dev_id, phy_id, QCA808X_PHY_MMD7_NUM, - QCA808X_PHY_MMD7_INGRESS_COUNTER_LOW); - counter_infor->RxGoodFrame = (ingress_high_counter << 16 ) | ingress_low_counter; - counter_infor->RxBadCRC = qca808x_phy_mmd_read(dev_id, phy_id, QCA808X_PHY_MMD7_NUM, - QCA808X_PHY_MMD7_INGRESS_ERROR_COUNTER); - - egress_high_counter = qca808x_phy_mmd_read(dev_id, phy_id, QCA808X_PHY_MMD7_NUM, - QCA808X_PHY_MMD7_EGRESS_COUNTER_HIGH); - egress_low_counter = qca808x_phy_mmd_read(dev_id, phy_id, QCA808X_PHY_MMD7_NUM, - QCA808X_PHY_MMD7_EGRESS_COUNTER_LOW); - counter_infor->TxGoodFrame = (egress_high_counter << 16 ) | egress_low_counter; - counter_infor->TxBadCRC = qca808x_phy_mmd_read(dev_id, phy_id, QCA808X_PHY_MMD7_NUM, - QCA808X_PHY_MMD7_EGRESS_ERROR_COUNTER); - - return SW_OK; -} -#endif -/****************************************************************************** -* -* qca808x_phy_set_eee_advertisement -* -* set eee advertisement -*/ -sw_error_t -qca808x_phy_set_eee_adv(a_uint32_t dev_id, a_uint32_t phy_id, - a_uint32_t adv) -{ - a_uint16_t phy_data = 0; - sw_error_t rv = SW_OK; - - phy_data = qca808x_phy_mmd_read(dev_id, phy_id, QCA808X_PHY_MMD7_NUM, - QCA808X_PHY_MMD7_ADDR_8023AZ_EEE_CTRL); - phy_data &= ~(QCA808X_PHY_EEE_ADV_100M | QCA808X_PHY_EEE_ADV_1000M); - - if (adv & FAL_PHY_EEE_100BASE_T) { - phy_data |= QCA808X_PHY_EEE_ADV_100M; - } - if (adv & FAL_PHY_EEE_1000BASE_T) { - phy_data |= QCA808X_PHY_EEE_ADV_1000M; - } - - rv = qca808x_phy_mmd_write(dev_id, phy_id, QCA808X_PHY_MMD7_NUM, - QCA808X_PHY_MMD7_ADDR_8023AZ_EEE_CTRL, phy_data); - - rv = qca808x_phy_restart_autoneg(dev_id, phy_id); - - return rv; -} - -/****************************************************************************** -* -* qca808x_phy_get_eee_advertisement -* -* get eee advertisement -*/ -sw_error_t -qca808x_phy_get_eee_adv(a_uint32_t dev_id, a_uint32_t phy_id, - a_uint32_t *adv) -{ - a_uint16_t phy_data = 0; - sw_error_t rv = SW_OK; - - *adv = 0; - phy_data = qca808x_phy_mmd_read(dev_id, phy_id, QCA808X_PHY_MMD7_NUM, - QCA808X_PHY_MMD7_ADDR_8023AZ_EEE_CTRL); - - if (phy_data & QCA808X_PHY_EEE_ADV_100M) { - *adv |= FAL_PHY_EEE_100BASE_T; - } - if (phy_data & QCA808X_PHY_EEE_ADV_1000M) { - *adv |= FAL_PHY_EEE_1000BASE_T; - } - - return rv; -} -/****************************************************************************** -* -* qca808x_phy_get_eee_partner_advertisement -* -* get eee partner advertisement -*/ -sw_error_t -qca808x_phy_get_eee_partner_adv(a_uint32_t dev_id, a_uint32_t phy_id, - a_uint32_t *adv) -{ - a_uint16_t phy_data = 0; - sw_error_t rv = SW_OK; - - *adv = 0; - phy_data = qca808x_phy_mmd_read(dev_id, phy_id, QCA808X_PHY_MMD7_NUM, - QCA808X_PHY_MMD7_ADDR_8023AZ_EEE_PARTNER); - - if (phy_data & QCA808X_PHY_EEE_PARTNER_ADV_100M) { - *adv |= FAL_PHY_EEE_100BASE_T; - } - if (phy_data & QCA808X_PHY_EEE_PARTNER_ADV_1000M) { - *adv |= FAL_PHY_EEE_1000BASE_T; - } - - return rv; -} -/****************************************************************************** -* -* qca808x_phy_get_eee_capability -* -* get eee capability -*/ -sw_error_t -qca808x_phy_get_eee_cap(a_uint32_t dev_id, a_uint32_t phy_id, - a_uint32_t *cap) -{ - a_uint16_t phy_data = 0; - sw_error_t rv = SW_OK; - - *cap = 0; - phy_data = qca808x_phy_mmd_read(dev_id, phy_id, QCA808X_PHY_MMD3_NUM, - QCA808X_PHY_MMD3_ADDR_8023AZ_EEE_CAPABILITY); - - if (phy_data & QCA808X_PHY_EEE_CAPABILITY_100M) { - *cap |= FAL_PHY_EEE_100BASE_T; - } - if (phy_data & QCA808X_PHY_EEE_CAPABILITY_1000M) { - *cap |= FAL_PHY_EEE_1000BASE_T; - } - - return rv; -} -/****************************************************************************** -* -* qca808x_phy_get_eee_status -* -* get eee status -*/ -sw_error_t -qca808x_phy_get_eee_status(a_uint32_t dev_id, a_uint32_t phy_id, - a_uint32_t *status) -{ - a_uint16_t phy_data = 0; - sw_error_t rv = SW_OK; - - *status = 0; - phy_data = qca808x_phy_mmd_read(dev_id, phy_id, QCA808X_PHY_MMD7_NUM, - QCA808X_PHY_MMD7_ADDR_8023AZ_EEE_STATUS); - - if (phy_data & QCA808X_PHY_EEE_STATUS_100M) { - *status |= FAL_PHY_EEE_100BASE_T; - } - if (phy_data & QCA808X_PHY_EEE_STATUS_1000M) { - *status |= FAL_PHY_EEE_1000BASE_T; - } - - return rv; -} - -/****************************************************************************** -* -* qca808x_phy_led_init - set led behavior -* -* set led behavior -*/ -static sw_error_t -qca808x_phy_led_init(a_uint32_t dev_id, a_uint32_t phy_id) -{ - sw_error_t rv = SW_OK; - - rv = qca808x_phy_mmd_write(dev_id, phy_id, QCA808X_PHY_MMD7_NUM, - QCA808X_PHY_MMD7_LED_POLARITY_CTRL, - QCA808X_PHY_MMD7_LED_POLARITY_ACTIVE_HIGH); - SW_RTN_ON_ERROR(rv); - rv = qca808x_phy_mmd_write(dev_id, phy_id, QCA808X_PHY_MMD7_NUM, - QCA808X_PHY_MMD7_LED0_CTRL, - QCA808X_PHY_MMD7_LED0_CTRL_ENABLE); - SW_RTN_ON_ERROR(rv); - rv = qca808x_phy_mmd_write(dev_id, phy_id, QCA808X_PHY_MMD7_NUM, - QCA808X_PHY_MMD7_LED1_CTRL, - QCA808X_PHY_MMD7_LED1_CTRL_DISABLE); - SW_RTN_ON_ERROR(rv); - rv = qca808x_phy_mmd_write(dev_id, phy_id, QCA808X_PHY_MMD7_NUM, - QCA808X_PHY_MMD7_LED2_CTRL, - QCA808X_PHY_MMD7_LED2_CTRL_DISABLE); - SW_RTN_ON_ERROR(rv); - - return rv; -} - -static sw_error_t -qca808x_phy_fast_retrain_cfg(a_uint32_t dev_id, a_uint32_t phy_id) -{ - sw_error_t rv = SW_OK; - - rv = qca808x_phy_mmd_write(dev_id, phy_id, QCA808X_PHY_MMD7_NUM, - QCA808X_PHY_MMD7_AUTONEGOTIATION_CONTROL, - QCA808X_ADVERTISE_2500FULL | - QCA808X_PHY_FAST_RETRAIN_2500BT | - QCA808X_PHY_ADV_LOOP_TIMING); - SW_RTN_ON_ERROR(rv); - rv = qca808x_phy_mmd_write(dev_id, phy_id, QCA808X_PHY_MMD1_NUM, - QCA808X_PHY_MMD1_FAST_RETRAIN_STATUS_CTL, - QCA808X_PHY_FAST_RETRAIN_CTRL); - SW_RTN_ON_ERROR(rv); - rv = qca808x_phy_mmd_write(dev_id, phy_id, QCA808X_PHY_MMD1_NUM, - QCA808X_PHY_MMD1_MSE_THRESHOLD_20DB, - QCA808X_PHY_MSE_THRESHOLD_20DB_VALUE); - SW_RTN_ON_ERROR(rv); - rv = qca808x_phy_mmd_write(dev_id, phy_id, QCA808X_PHY_MMD1_NUM, - QCA808X_PHY_MMD1_MSE_THRESHOLD_17DB, - QCA808X_PHY_MSE_THRESHOLD_17DB_VALUE); - SW_RTN_ON_ERROR(rv); - rv = qca808x_phy_mmd_write(dev_id, phy_id, QCA808X_PHY_MMD1_NUM, - QCA808X_PHY_MMD1_MSE_THRESHOLD_27DB, - QCA808X_PHY_MSE_THRESHOLD_27DB_VALUE); - SW_RTN_ON_ERROR(rv); - rv = qca808x_phy_mmd_write(dev_id, phy_id, QCA808X_PHY_MMD1_NUM, - QCA808X_PHY_MMD1_MSE_THRESHOLD_28DB, - QCA808X_PHY_MSE_THRESHOLD_28DB_VALUE); - SW_RTN_ON_ERROR(rv); - rv = qca808x_phy_mmd_write(dev_id, phy_id, QCA808X_PHY_MMD7_NUM, - QCA808X_PHY_MMD7_ADDR_EEE_LP_ADVERTISEMENT, - QCA808X_PHY_EEE_ADV_THP); - SW_RTN_ON_ERROR(rv); - rv = qca808x_phy_mmd_write(dev_id, phy_id, QCA808X_PHY_MMD7_NUM, - QCA808X_PHY_MMD7_TOP_OPTION1, - QCA808X_PHY_TOP_OPTION1_DATA); - SW_RTN_ON_ERROR(rv); - /*adjust the threshold for link down*/ - rv = qca808x_phy_mmd_write(dev_id, phy_id, QCA808X_PHY_MMD3_NUM, - 0xa100, 0x9203); - SW_RTN_ON_ERROR(rv); - rv = qca808x_phy_mmd_write(dev_id, phy_id, QCA808X_PHY_MMD3_NUM, - 0xa105, 0x8001); - SW_RTN_ON_ERROR(rv); - rv = qca808x_phy_mmd_write(dev_id, phy_id, QCA808X_PHY_MMD3_NUM, - 0xa106, 0x1111); - SW_RTN_ON_ERROR(rv); - rv = qca808x_phy_mmd_write(dev_id, phy_id, QCA808X_PHY_MMD3_NUM, - 0xa103, 0x1698); - SW_RTN_ON_ERROR(rv); - rv = qca808x_phy_mmd_write(dev_id, phy_id, QCA808X_PHY_MMD3_NUM, - 0xa011, 0x5f85); - SW_RTN_ON_ERROR(rv); - rv = qca808x_phy_mmd_write(dev_id, phy_id, QCA808X_PHY_MMD3_NUM, - 0xa101, 0x48ad); - - return rv; -} - -void qca808x_phy_lock_init(void) -{ - static a_bool_t is_init = A_FALSE; - - if(!is_init) - { - QCA808X_LOCKER_INIT; - is_init = A_TRUE; - } - - return; -} - -static sw_error_t -qca808x_phy_adc_threshold_set(a_uint32_t dev_id, a_uint32_t phy_id, - a_uint32_t adc_thresold) -{ - sw_error_t rv = SW_OK; - a_uint16_t phy_data = 0; - - phy_data = qca808x_phy_debug_read(dev_id, phy_id, - QCA808X_PHY_ADC_THRESHOLD); - PHY_RTN_ON_READ_ERROR(phy_data); - phy_data &= ~(BITS(0, 8)); - rv = qca808x_phy_debug_write (dev_id, phy_id, - QCA808X_PHY_ADC_THRESHOLD, phy_data | adc_thresold); - - return rv; -} - -static sw_error_t -qca808x_phy_hw_init(a_uint32_t dev_id, a_uint32_t port_bmp) -{ - a_uint16_t phy_data = 0; - a_uint32_t port_id = 0, phy_addr = 0; - sw_error_t rv = SW_OK; - - for (port_id = SSDK_PHYSICAL_PORT0; port_id < SW_MAX_NR_PORT; port_id ++) - { - if (port_bmp & (0x1 << port_id)) - { - phy_addr = qca_ssdk_port_to_phy_addr(dev_id, port_id); - /*enable vga when init napa to fix 8023az issue*/ - phy_data = qca808x_phy_mmd_read(dev_id, phy_addr, QCA808X_PHY_MMD3_NUM, - QCA808X_PHY_MMD3_ADDR_CLD_CTRL7); - phy_data &= (~QCA808X_PHY_8023AZ_AFE_CTRL_MASK); - phy_data |= QCA808X_PHY_8023AZ_AFE_EN; - rv = qca808x_phy_mmd_write(dev_id, phy_addr, QCA808X_PHY_MMD3_NUM, - QCA808X_PHY_MMD3_ADDR_CLD_CTRL7, phy_data); - SW_RTN_ON_ERROR(rv); - /*set napa led pin behavior on HK board*/ - rv = qca808x_phy_led_init(dev_id, phy_addr); - SW_RTN_ON_ERROR(rv); - /*special configuration for AZ under 1G speed mode*/ - phy_data = QCA808X_PHY_MMD3_AZ_TRAINING_VAL; - rv = qca808x_phy_mmd_write(dev_id, phy_addr, QCA808X_PHY_MMD3_NUM, - QCA808X_PHY_MMD3_AZ_TRAINING_CTRL, phy_data); - SW_RTN_ON_ERROR(rv); - /*config the fast retrain*/ - rv = qca808x_phy_fast_retrain_cfg(dev_id, phy_addr); - SW_RTN_ON_ERROR(rv); - /*enable seed and configure ramdom seed in order that napa can be - as slave easier*/ - rv = qca808x_phy_ms_seed_enable(dev_id, phy_addr, A_TRUE); - SW_RTN_ON_ERROR(rv); - rv = qca808x_phy_ms_random_seed_set(dev_id, phy_addr); - SW_RTN_ON_ERROR(rv); - /*set adc threshold as 100mv for 10M*/ - rv = qca808x_phy_adc_threshold_set(dev_id, phy_addr, - QCA808X_PHY_ADC_THRESHOLD_100MV); - SW_RTN_ON_ERROR(rv); - } - } - - return rv; -} - -static sw_error_t qca808x_phy_api_ops_init(void) -{ - sw_error_t ret = SW_OK; - hsl_phy_ops_t *qca808x_phy_api_ops = NULL; - - qca808x_phy_api_ops = kzalloc(sizeof(hsl_phy_ops_t), GFP_KERNEL); - if (qca808x_phy_api_ops == NULL) { - SSDK_ERROR("qca808x phy ops kzalloc failed!\n"); - return -ENOMEM; - } - - phy_api_ops_init(QCA808X_PHY_CHIP); - - qca808x_phy_api_ops->phy_reg_write = qca808x_phy_reg_write; - qca808x_phy_api_ops->phy_reg_read = qca808x_phy_reg_read; - qca808x_phy_api_ops->phy_debug_write = qca808x_phy_debug_write; - qca808x_phy_api_ops->phy_debug_read = qca808x_phy_debug_read; - qca808x_phy_api_ops->phy_mmd_write = qca808x_phy_mmd_write; - qca808x_phy_api_ops->phy_mmd_read = qca808x_phy_mmd_read; - qca808x_phy_api_ops->phy_get_status = qca808x_phy_get_status; - qca808x_phy_api_ops->phy_speed_get = qca808x_phy_get_speed; - qca808x_phy_api_ops->phy_speed_set = qca808x_phy_set_speed; - qca808x_phy_api_ops->phy_duplex_get = qca808x_phy_get_duplex; - qca808x_phy_api_ops->phy_duplex_set = qca808x_phy_set_duplex; - qca808x_phy_api_ops->phy_autoneg_enable_set = qca808x_phy_enable_autoneg; - qca808x_phy_api_ops->phy_restart_autoneg = qca808x_phy_restart_autoneg; - qca808x_phy_api_ops->phy_autoneg_status_get = qca808x_phy_autoneg_status; - qca808x_phy_api_ops->phy_autoneg_adv_set = qca808x_phy_set_autoneg_adv; - qca808x_phy_api_ops->phy_autoneg_adv_get = qca808x_phy_get_autoneg_adv; - qca808x_phy_api_ops->phy_link_status_get = qca808x_phy_get_link_status; - qca808x_phy_api_ops->phy_reset = qca808x_phy_reset; -#ifndef IN_PORTCONTROL_MINI - qca808x_phy_api_ops->phy_cdt = qca808x_phy_cdt; - qca808x_phy_api_ops->phy_mdix_set = qca808x_phy_set_mdix; - qca808x_phy_api_ops->phy_mdix_get = qca808x_phy_get_mdix; - qca808x_phy_api_ops->phy_mdix_status_get = qca808x_phy_get_mdix_status; - qca808x_phy_api_ops->phy_local_loopback_set = qca808x_phy_set_local_loopback; - qca808x_phy_api_ops->phy_local_loopback_get = qca808x_phy_get_local_loopback; - qca808x_phy_api_ops->phy_remote_loopback_set = qca808x_phy_set_remote_loopback; - qca808x_phy_api_ops->phy_remote_loopback_get = qca808x_phy_get_remote_loopback; -#endif - qca808x_phy_api_ops->phy_id_get = qca808x_phy_get_phy_id; - qca808x_phy_api_ops->phy_power_off = qca808x_phy_poweroff; - qca808x_phy_api_ops->phy_power_on = qca808x_phy_poweron; -#ifndef IN_PORTCONTROL_MINI - qca808x_phy_api_ops->phy_8023az_set = qca808x_phy_set_8023az; - qca808x_phy_api_ops->phy_8023az_get = qca808x_phy_get_8023az; - qca808x_phy_api_ops->phy_hibernation_set = qca808x_phy_set_hibernate; - qca808x_phy_api_ops->phy_hibernation_get = qca808x_phy_get_hibernate; - qca808x_phy_api_ops->phy_magic_frame_mac_set = qca808x_phy_set_magic_frame_mac; - qca808x_phy_api_ops->phy_magic_frame_mac_get = qca808x_phy_get_magic_frame_mac; - qca808x_phy_api_ops->phy_wol_status_set = qca808x_phy_set_wol_status; - qca808x_phy_api_ops->phy_wol_status_get = qca808x_phy_get_wol_status; -#endif - qca808x_phy_api_ops->phy_interface_mode_set = qca808x_phy_interface_set_mode; - qca808x_phy_api_ops->phy_interface_mode_get = qca808x_phy_interface_get_mode; - qca808x_phy_api_ops->phy_interface_mode_status_get = qca808x_phy_interface_get_mode_status; -#ifndef IN_PORTCONTROL_MINI - qca808x_phy_api_ops->phy_intr_mask_set = qca808x_phy_set_intr_mask; - qca808x_phy_api_ops->phy_intr_mask_get = qca808x_phy_get_intr_mask; - qca808x_phy_api_ops->phy_intr_status_get = qca808x_phy_get_intr_status; - qca808x_phy_api_ops->phy_counter_set = qca808x_phy_set_counter; - qca808x_phy_api_ops->phy_counter_get = qca808x_phy_get_counter; - qca808x_phy_api_ops->phy_counter_show = qca808x_phy_show_counter; -#endif - qca808x_phy_api_ops->phy_eee_adv_set = qca808x_phy_set_eee_adv; - qca808x_phy_api_ops->phy_eee_adv_get = qca808x_phy_get_eee_adv; - qca808x_phy_api_ops->phy_eee_partner_adv_get = qca808x_phy_get_eee_partner_adv; - qca808x_phy_api_ops->phy_eee_cap_get = qca808x_phy_get_eee_cap; - qca808x_phy_api_ops->phy_eee_status_get = qca808x_phy_get_eee_status; -#ifdef IN_LED - qca808x_phy_led_api_ops_init(qca808x_phy_api_ops); -#endif -/*qca808x_end*/ -#if defined(IN_PTP) - qca808x_phy_ptp_api_ops_init(&qca808x_phy_api_ops->phy_ptp_ops); -#endif -/*qca808x_start*/ - ret = hsl_phy_api_ops_register(QCA808X_PHY_CHIP, qca808x_phy_api_ops); - - if (ret == SW_OK) { - SSDK_INFO("qca probe qca808x phy driver succeeded!\n"); - } else { - SSDK_ERROR("qca probe qca808x phy driver failed! (code: %d)\n", ret); - } - - return ret; -} - -/****************************************************************************** -* -* qca808x_phy_init - -* -*/ -int qca808x_phy_init(a_uint32_t dev_id, a_uint32_t port_bmp) -{ -/*qca808x_end*/ - a_uint32_t port_id = 0; -/*qca808x_start*/ - a_int32_t ret = 0; - - if(phy_ops_flag == A_FALSE && - qca808x_phy_api_ops_init() == SW_OK) { - qca808x_phy_lock_init(); - phy_ops_flag = A_TRUE; - } - qca808x_phy_hw_init(dev_id, port_bmp); - -/*qca808x_end*/ - if(phy_dev_drv_init_flag == A_FALSE) - { - for (port_id = 0; port_id < SW_MAX_NR_PORT; port_id ++) - { - if (port_bmp & (0x1 << port_id)) { - qca808x_phydev_init(dev_id, port_id); - } - } - ret = qca808x_phy_driver_register(); - phy_dev_drv_init_flag = A_TRUE; - } -/*qca808x_start*/ - return ret; -} - -void qca808x_phy_exit(a_uint32_t dev_id, a_uint32_t port_bmp) -{ -/*qca808x_end*/ - a_uint32_t port_id = 0; - - qca808x_phy_driver_unregister(); - for (port_id = 0; port_id < SW_MAX_NR_PORT; port_id ++) - { - if (port_bmp & (0x1 << port_id)) { - qca808x_phydev_deinit(dev_id, port_id); - } - } -/*qca808x_start*/ -} -/*qca808x_end*/ diff --git a/feeds/ipq807x/qca-ssdk/src/src/hsl/phy/qca808x_ptp.c b/feeds/ipq807x/qca-ssdk/src/src/hsl/phy/qca808x_ptp.c deleted file mode 100755 index c1e3e6589..000000000 --- a/feeds/ipq807x/qca-ssdk/src/src/hsl/phy/qca808x_ptp.c +++ /dev/null @@ -1,2843 +0,0 @@ -/* - * Copyright (c) 2018, The Linux Foundation. All rights reserved. - * Permission to use, copy, modify, and/or distribute this software for - * any purpose with or without fee is hereby granted, provided that the - * above copyright notice and this permission notice appear in all copies. - * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES - * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR - * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES - * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN - * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT - * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. - */ -#include "sw.h" -#include "hsl_api.h" -#include "hsl.h" -#include "hsl_phy.h" -#include "ssdk_plat.h" -#include "qca808x_phy.h" -#include "qca808x_ptp_reg.h" -#include "qca808x_ptp_api.h" -#include "qca808x_ptp.h" - -sw_error_t -qca808x_phy_ptp_config_set(a_uint32_t dev_id, - a_uint32_t phy_id, fal_ptp_config_t *config) -{ - union ptp_main_conf_reg_u ptp_main_conf_reg = {0}; - union ptp_misc_config_reg_u ptp_misc_config_reg = {0}; - union ptp_backup_reg_u ptp_backup_reg = {0}; - - SW_RTN_ON_ERROR(qca808x_ptp_main_conf_reg_get(dev_id, phy_id, &ptp_main_conf_reg)); - SW_RTN_ON_ERROR(qca808x_ptp_misc_config_reg_get(dev_id, phy_id, &ptp_misc_config_reg)); - SW_RTN_ON_ERROR(qca808x_ptp_backup_reg_get(dev_id, phy_id, &ptp_backup_reg)); - if (config->ptp_en == A_TRUE) - { - ptp_main_conf_reg.bf.ptp_bypass = PTP_REG_BIT_FALSE; - ptp_main_conf_reg.bf.disable_1588_phy = PTP_REG_BIT_FALSE; - } - else - { - ptp_main_conf_reg.bf.ptp_bypass = PTP_REG_BIT_TRUE; - ptp_main_conf_reg.bf.disable_1588_phy = PTP_REG_BIT_TRUE; - } - if (config->clock_mode == FAL_OC_CLOCK_MODE || config->clock_mode == FAL_BC_CLOCK_MODE) - { - if (config->step_mode == FAL_ONE_STEP_MODE) - { - ptp_main_conf_reg.bf.ptp_clock_mode = - PTP_MAIN_CONF_REG_PTP_CLOCK_MODE_OC_ONE_STEP; - } - else - { - ptp_main_conf_reg.bf.ptp_clock_mode = - PTP_MAIN_CONF_REG_PTP_CLOCK_MODE_OC_TWO_STEP; - } - } - else - { - if (config->clock_mode == FAL_P2PTC_CLOCK_MODE) - { - ptp_backup_reg.bf.p2p_tc_en = PTP_REG_BIT_TRUE; - } - else - { - ptp_backup_reg.bf.p2p_tc_en = PTP_REG_BIT_FALSE; - } - - if (config->step_mode == FAL_ONE_STEP_MODE && - ptp_misc_config_reg.bf.embed_ingress_time_en == PTP_REG_BIT_TRUE) - { - ptp_misc_config_reg.bf.tc_offload = PTP_REG_BIT_TRUE; - } - else - { - ptp_misc_config_reg.bf.tc_offload = PTP_REG_BIT_FALSE; - } - - if (config->step_mode == FAL_ONE_STEP_MODE) - { - ptp_main_conf_reg.bf.ptp_clock_mode = - PTP_MAIN_CONF_REG_PTP_CLOCK_MODE_TC_ONE_STEP; - } - else - { - ptp_main_conf_reg.bf.ptp_clock_mode = - PTP_MAIN_CONF_REG_PTP_CLOCK_MODE_TC_TWO_STEP; - } - } - if (config->step_mode == FAL_AUTO_MODE) - { - ptp_misc_config_reg.bf.pkt_one_step_en = PTP_REG_BIT_TRUE; - } - else - { - ptp_misc_config_reg.bf.pkt_one_step_en = PTP_REG_BIT_FALSE; - } -#if defined(IN_LINUX_STD_PTP) - qca808x_ptp_clock_mode_config(dev_id, phy_id, config->clock_mode, config->step_mode); -#endif - SW_RTN_ON_ERROR(qca808x_ptp_main_conf_reg_set(dev_id, phy_id, &ptp_main_conf_reg)); - SW_RTN_ON_ERROR(qca808x_ptp_misc_config_reg_set(dev_id, phy_id, &ptp_misc_config_reg)); - SW_RTN_ON_ERROR(qca808x_ptp_backup_reg_set(dev_id, phy_id, &ptp_backup_reg)); - - return SW_OK; -} - -sw_error_t -qca808x_phy_ptp_config_get(a_uint32_t dev_id, - a_uint32_t phy_id, fal_ptp_config_t *config) -{ - union ptp_main_conf_reg_u ptp_main_conf_reg = {0}; - union ptp_misc_config_reg_u ptp_misc_config_reg = {0}; - union ptp_backup_reg_u ptp_backup_reg = {0}; - - SW_RTN_ON_ERROR(qca808x_ptp_main_conf_reg_get(dev_id, phy_id, &ptp_main_conf_reg)); - SW_RTN_ON_ERROR(qca808x_ptp_misc_config_reg_get(dev_id, phy_id, &ptp_misc_config_reg)); - SW_RTN_ON_ERROR(qca808x_ptp_backup_reg_get(dev_id, phy_id, &ptp_backup_reg)); - if (ptp_main_conf_reg.bf.ptp_bypass == PTP_REG_BIT_FALSE && - ptp_main_conf_reg.bf.disable_1588_phy == PTP_REG_BIT_FALSE) - { - config->ptp_en = A_TRUE; - } - if (ptp_main_conf_reg.bf.ptp_clock_mode == - PTP_MAIN_CONF_REG_PTP_CLOCK_MODE_OC_TWO_STEP) - { - config->clock_mode = FAL_OC_CLOCK_MODE; - config->step_mode = FAL_TWO_STEP_MODE; - } - else if (ptp_main_conf_reg.bf.ptp_clock_mode == - PTP_MAIN_CONF_REG_PTP_CLOCK_MODE_OC_ONE_STEP) - { - config->clock_mode = FAL_OC_CLOCK_MODE; - config->step_mode = FAL_ONE_STEP_MODE; - } - else if (ptp_main_conf_reg.bf.ptp_clock_mode == - PTP_MAIN_CONF_REG_PTP_CLOCK_MODE_TC_TWO_STEP) - { - if (ptp_backup_reg.bf.p2p_tc_en == PTP_REG_BIT_TRUE) - { - config->clock_mode = FAL_P2PTC_CLOCK_MODE; - } - else - { - config->clock_mode = FAL_E2ETC_CLOCK_MODE; - } - - config->step_mode = FAL_TWO_STEP_MODE; - } - else - { - if (ptp_backup_reg.bf.p2p_tc_en == PTP_REG_BIT_TRUE) - { - config->clock_mode = FAL_P2PTC_CLOCK_MODE; - } - else - { - config->clock_mode = FAL_E2ETC_CLOCK_MODE; - } - - config->step_mode = FAL_ONE_STEP_MODE; - } - if (ptp_misc_config_reg.bf.pkt_one_step_en == PTP_REG_BIT_TRUE) - { - config->step_mode = FAL_AUTO_MODE; - } - - return SW_OK; -} - -sw_error_t -qca808x_phy_ptp_reference_clock_set(a_uint32_t dev_id, - a_uint32_t phy_id, fal_ptp_reference_clock_t ref_clock) -{ - union ptp_main_conf_reg_u ptp_main_conf_reg = {0}; - union ptp_rtc_clk_reg_u ptp_rtc_clk_reg = {0}; - - SW_RTN_ON_ERROR(qca808x_ptp_main_conf_reg_get(dev_id, phy_id, &ptp_main_conf_reg)); - SW_RTN_ON_ERROR(qca808x_ptp_rtc_clk_reg_get(dev_id, phy_id, &ptp_rtc_clk_reg)); - if (ref_clock == FAL_REF_CLOCK_LOCAL) - { - ptp_main_conf_reg.bf.ptp_clk_sel = PTP_REG_BIT_FALSE; - ptp_rtc_clk_reg.bf.rtc_clk_selection = PTP_REG_BIT_FALSE; - } - else if (ref_clock == FAL_REF_CLOCK_SYNCE) - { - ptp_main_conf_reg.bf.ptp_clk_sel = PTP_REG_BIT_TRUE; - ptp_rtc_clk_reg.bf.rtc_clk_selection = PTP_REG_BIT_FALSE; - } - else - { - ptp_main_conf_reg.bf.ptp_clk_sel = PTP_REG_BIT_FALSE; - ptp_rtc_clk_reg.bf.rtc_clk_selection = PTP_REG_BIT_TRUE; - } - SW_RTN_ON_ERROR(qca808x_ptp_main_conf_reg_set(dev_id, phy_id, &ptp_main_conf_reg)); - SW_RTN_ON_ERROR(qca808x_ptp_rtc_clk_reg_set(dev_id, phy_id, &ptp_rtc_clk_reg)); - - return SW_OK; -} - -sw_error_t -qca808x_phy_ptp_reference_clock_get(a_uint32_t dev_id, - a_uint32_t phy_id, fal_ptp_reference_clock_t *ref_clock) -{ - union ptp_main_conf_reg_u ptp_main_conf_reg = {0}; - union ptp_rtc_clk_reg_u ptp_rtc_clk_reg = {0}; - - SW_RTN_ON_ERROR(qca808x_ptp_main_conf_reg_get(dev_id, phy_id, &ptp_main_conf_reg)); - SW_RTN_ON_ERROR(qca808x_ptp_rtc_clk_reg_get(dev_id, phy_id, &ptp_rtc_clk_reg)); - if (ptp_main_conf_reg.bf.ptp_clk_sel == PTP_REG_BIT_FALSE && - ptp_rtc_clk_reg.bf.rtc_clk_selection == PTP_REG_BIT_FALSE) - { - *ref_clock = FAL_REF_CLOCK_LOCAL; - } - else if (ptp_main_conf_reg.bf.ptp_clk_sel == PTP_REG_BIT_TRUE && - ptp_rtc_clk_reg.bf.rtc_clk_selection == PTP_REG_BIT_FALSE) - { - *ref_clock = FAL_REF_CLOCK_SYNCE; - } - else - { - *ref_clock = FAL_REF_CLOCK_EXTERNAL; - } - - return SW_OK; -} - -sw_error_t -qca808x_phy_ptp_rx_timestamp_mode_set(a_uint32_t dev_id, - a_uint32_t phy_id, fal_ptp_rx_timestamp_mode_t ts_mode) -{ - union ptp_main_conf_reg_u ptp_main_conf_reg = {0}; - union ptp_misc_config_reg_u ptp_misc_config_reg = {0}; - - SW_RTN_ON_ERROR(qca808x_ptp_main_conf_reg_get(dev_id, phy_id, &ptp_main_conf_reg)); - SW_RTN_ON_ERROR(qca808x_ptp_misc_config_reg_get(dev_id, phy_id, &ptp_misc_config_reg)); - if (ts_mode == FAL_RX_TS_MDIO) - { - ptp_main_conf_reg.bf.ts_attach_mode = PTP_REG_BIT_FALSE; - ptp_main_conf_reg.bf.ipv6_embed_force_checksum_zero = PTP_REG_BIT_FALSE; - ptp_misc_config_reg.bf.embed_ingress_time_en = PTP_REG_BIT_FALSE; - ptp_misc_config_reg.bf.cf_from_pkt_en = PTP_REG_BIT_TRUE; - } - else - { - ptp_main_conf_reg.bf.ts_attach_mode = PTP_REG_BIT_FALSE; - ptp_main_conf_reg.bf.ipv6_embed_force_checksum_zero = PTP_REG_BIT_TRUE; - ptp_misc_config_reg.bf.embed_ingress_time_en = PTP_REG_BIT_TRUE; - ptp_misc_config_reg.bf.cf_from_pkt_en = PTP_REG_BIT_FALSE; - } - SW_RTN_ON_ERROR(qca808x_ptp_main_conf_reg_set(dev_id, phy_id, &ptp_main_conf_reg)); - SW_RTN_ON_ERROR(qca808x_ptp_misc_config_reg_set(dev_id, phy_id, &ptp_misc_config_reg)); - - return SW_OK; -} - -sw_error_t -qca808x_phy_ptp_rx_timestamp_mode_get(a_uint32_t dev_id, - a_uint32_t phy_id, fal_ptp_rx_timestamp_mode_t *ts_mode) -{ - union ptp_main_conf_reg_u ptp_main_conf_reg = {0}; - union ptp_misc_config_reg_u ptp_misc_config_reg = {0}; - - SW_RTN_ON_ERROR(qca808x_ptp_main_conf_reg_get(dev_id, phy_id, &ptp_main_conf_reg)); - SW_RTN_ON_ERROR(qca808x_ptp_misc_config_reg_get(dev_id, phy_id, &ptp_misc_config_reg)); - if (ptp_main_conf_reg.bf.ts_attach_mode == PTP_REG_BIT_FALSE && - ptp_misc_config_reg.bf.embed_ingress_time_en == PTP_REG_BIT_FALSE) - { - *ts_mode = FAL_RX_TS_MDIO; - } - else if (ptp_main_conf_reg.bf.ts_attach_mode == PTP_REG_BIT_FALSE && - ptp_misc_config_reg.bf.embed_ingress_time_en == PTP_REG_BIT_TRUE) - { - *ts_mode = FAL_RX_TS_EMBED; - } - else - { - return SW_BAD_VALUE; - } - - return SW_OK; -} - -sw_error_t -qca808x_phy_ptp_rx_timestamp0_get(a_uint32_t dev_id, a_uint32_t phy_id, - fal_ptp_pkt_info_t *pkt_info, fal_ptp_time_t *time) -{ - union ptp_rx_seqid0_reg_u ptp_rx_seqid0_reg = {0}; - - union ptp_rx_portid0_0_reg_u ptp_rx_portid0_0_reg = {0}; - union ptp_rx_portid0_1_reg_u ptp_rx_portid0_1_reg = {0}; - union ptp_rx_portid0_2_reg_u ptp_rx_portid0_2_reg = {0}; - union ptp_rx_portid0_3_reg_u ptp_rx_portid0_3_reg = {0}; - union ptp_rx_portid0_4_reg_u ptp_rx_portid0_4_reg = {0}; - union ptp_rx_ts0_0_reg_u ptp_rx_ts0_0_reg = {0}; - union ptp_rx_ts0_1_reg_u ptp_rx_ts0_1_reg = {0}; - union ptp_rx_ts0_2_reg_u ptp_rx_ts0_2_reg = {0}; - union ptp_rx_ts0_3_reg_u ptp_rx_ts0_3_reg = {0}; - union ptp_rx_ts0_4_reg_u ptp_rx_ts0_4_reg = {0}; - union ptp_rx_ts0_5_reg_u ptp_rx_ts0_5_reg = {0}; - union ptp_rx_ts0_6_reg_u ptp_rx_ts0_6_reg = {0}; - - a_uint64_t clock_id; - a_uint32_t port_num, msgtype; - - SW_RTN_ON_ERROR(qca808x_ptp_rx_seqid0_reg_get(dev_id, phy_id, &ptp_rx_seqid0_reg)); - if (pkt_info->sequence_id != ptp_rx_seqid0_reg.bf.rx_seqid) - { - return SW_NOT_FOUND; - } - - SW_RTN_ON_ERROR(qca808x_ptp_rx_portid0_0_reg_get(dev_id, - phy_id, &ptp_rx_portid0_0_reg)); - SW_RTN_ON_ERROR(qca808x_ptp_rx_portid0_1_reg_get(dev_id, - phy_id, &ptp_rx_portid0_1_reg)); - SW_RTN_ON_ERROR(qca808x_ptp_rx_portid0_2_reg_get(dev_id, - phy_id, &ptp_rx_portid0_2_reg)); - SW_RTN_ON_ERROR(qca808x_ptp_rx_portid0_3_reg_get(dev_id, - phy_id, &ptp_rx_portid0_3_reg)); - - SW_RTN_ON_ERROR(qca808x_ptp_rx_portid0_4_reg_get(dev_id, - phy_id, &ptp_rx_portid0_4_reg)); - - SW_RTN_ON_ERROR(qca808x_ptp_rx_ts0_0_reg_get(dev_id, - phy_id, &ptp_rx_ts0_0_reg)); - SW_RTN_ON_ERROR(qca808x_ptp_rx_ts0_1_reg_get(dev_id, - phy_id, &ptp_rx_ts0_1_reg)); - SW_RTN_ON_ERROR(qca808x_ptp_rx_ts0_2_reg_get(dev_id, - phy_id, &ptp_rx_ts0_2_reg)); - SW_RTN_ON_ERROR(qca808x_ptp_rx_ts0_3_reg_get(dev_id, - phy_id, &ptp_rx_ts0_3_reg)); - SW_RTN_ON_ERROR(qca808x_ptp_rx_ts0_4_reg_get(dev_id, - phy_id, &ptp_rx_ts0_4_reg)); - SW_RTN_ON_ERROR(qca808x_ptp_rx_ts0_5_reg_get(dev_id, - phy_id, &ptp_rx_ts0_5_reg)); - SW_RTN_ON_ERROR(qca808x_ptp_rx_ts0_6_reg_get(dev_id, - phy_id, &ptp_rx_ts0_6_reg)); - - clock_id = ((a_uint64_t)ptp_rx_portid0_0_reg.bf.rx_portid << 48) | - ((a_uint64_t)ptp_rx_portid0_1_reg.bf.rx_portid << 32) | - ((a_uint64_t)ptp_rx_portid0_2_reg.bf.rx_portid << 16) | - ptp_rx_portid0_3_reg.bf.rx_portid; - port_num = ptp_rx_portid0_4_reg.bf.rx_portid; - msgtype = ptp_rx_ts0_5_reg.bf.rx_msg_type; - - if (pkt_info->clock_identify == clock_id && - pkt_info->port_number == port_num && - pkt_info->msg_type == msgtype) - { - time->seconds = - ((a_int64_t)ptp_rx_ts0_0_reg.bf.rx_ts_sec << 32) | - ((a_int64_t)ptp_rx_ts0_1_reg.bf.rx_ts_sec << 16) | - ptp_rx_ts0_2_reg.bf.rx_ts_sec; - time->nanoseconds = - ((a_int32_t)ptp_rx_ts0_3_reg.bf.rx_ts_nsec << 16) | - ptp_rx_ts0_4_reg.bf.rx_ts_nsec; - time->fracnanoseconds = - ((a_int32_t)ptp_rx_ts0_5_reg.bf.rx_ts_nfsec << 8) | - ptp_rx_ts0_6_reg.bf.rx_ts_nfsec; - - return SW_OK; - } - return SW_NOT_FOUND; -} - -sw_error_t -qca808x_phy_ptp_rx_timestamp1_get(a_uint32_t dev_id, a_uint32_t phy_id, - fal_ptp_pkt_info_t *pkt_info, fal_ptp_time_t *time) -{ - union ptp_rx_seqid1_reg_u ptp_rx_seqid1_reg = {0}; - - union ptp_rx_portid1_0_reg_u ptp_rx_portid1_0_reg = {0}; - union ptp_rx_portid1_1_reg_u ptp_rx_portid1_1_reg = {0}; - union ptp_rx_portid1_2_reg_u ptp_rx_portid1_2_reg = {0}; - union ptp_rx_portid1_3_reg_u ptp_rx_portid1_3_reg = {0}; - union ptp_rx_portid1_4_reg_u ptp_rx_portid1_4_reg = {0}; - union ptp_rx_ts1_0_reg_u ptp_rx_ts1_0_reg = {0}; - union ptp_rx_ts1_1_reg_u ptp_rx_ts1_1_reg = {0}; - union ptp_rx_ts1_2_reg_u ptp_rx_ts1_2_reg = {0}; - union ptp_rx_ts1_3_reg_u ptp_rx_ts1_3_reg = {0}; - union ptp_rx_ts1_4_reg_u ptp_rx_ts1_4_reg = {0}; - union ptp_rx_ts1_5_reg_u ptp_rx_ts1_5_reg = {0}; - union ptp_rx_ts1_6_reg_u ptp_rx_ts1_6_reg = {0}; - - a_uint64_t clock_id; - a_uint32_t port_num, msgtype; - - SW_RTN_ON_ERROR(qca808x_ptp_rx_seqid1_reg_get(dev_id, phy_id, &ptp_rx_seqid1_reg)); - if (pkt_info->sequence_id != ptp_rx_seqid1_reg.bf.rx_seqid) - { - return SW_NOT_FOUND; - } - - SW_RTN_ON_ERROR(qca808x_ptp_rx_portid1_0_reg_get(dev_id, - phy_id, &ptp_rx_portid1_0_reg)); - SW_RTN_ON_ERROR(qca808x_ptp_rx_portid1_1_reg_get(dev_id, - phy_id, &ptp_rx_portid1_1_reg)); - SW_RTN_ON_ERROR(qca808x_ptp_rx_portid1_2_reg_get(dev_id, - phy_id, &ptp_rx_portid1_2_reg)); - SW_RTN_ON_ERROR(qca808x_ptp_rx_portid1_3_reg_get(dev_id, - phy_id, &ptp_rx_portid1_3_reg)); - SW_RTN_ON_ERROR(qca808x_ptp_rx_portid1_4_reg_get(dev_id, - phy_id, &ptp_rx_portid1_4_reg)); - SW_RTN_ON_ERROR(qca808x_ptp_rx_ts1_0_reg_get(dev_id, - phy_id, &ptp_rx_ts1_0_reg)); - SW_RTN_ON_ERROR(qca808x_ptp_rx_ts1_1_reg_get(dev_id, - phy_id, &ptp_rx_ts1_1_reg)); - SW_RTN_ON_ERROR(qca808x_ptp_rx_ts1_2_reg_get(dev_id, - phy_id, &ptp_rx_ts1_2_reg)); - SW_RTN_ON_ERROR(qca808x_ptp_rx_ts1_3_reg_get(dev_id, - phy_id, &ptp_rx_ts1_3_reg)); - SW_RTN_ON_ERROR(qca808x_ptp_rx_ts1_4_reg_get(dev_id, - phy_id, &ptp_rx_ts1_4_reg)); - SW_RTN_ON_ERROR(qca808x_ptp_rx_ts1_5_reg_get(dev_id, - phy_id, &ptp_rx_ts1_5_reg)); - SW_RTN_ON_ERROR(qca808x_ptp_rx_ts1_6_reg_get(dev_id, - phy_id, &ptp_rx_ts1_6_reg)); - - clock_id = ((a_uint64_t)ptp_rx_portid1_0_reg.bf.rx_portid << 48) | - ((a_uint64_t)ptp_rx_portid1_1_reg.bf.rx_portid << 32) | - ((a_uint64_t)ptp_rx_portid1_2_reg.bf.rx_portid << 16) | - ptp_rx_portid1_3_reg.bf.rx_portid; - - port_num = ptp_rx_portid1_4_reg.bf.rx_portid; - msgtype = ptp_rx_ts1_5_reg.bf.rx_msg_type; - if (pkt_info->clock_identify == clock_id && - pkt_info->port_number == port_num && - pkt_info->msg_type == msgtype) - { - time->seconds = - ((a_int64_t)ptp_rx_ts1_0_reg.bf.rx_ts_sec << 32) | - ((a_int64_t)ptp_rx_ts1_1_reg.bf.rx_ts_sec << 16) | - ptp_rx_ts1_2_reg.bf.rx_ts_sec; - time->nanoseconds = - ((a_int32_t)ptp_rx_ts1_3_reg.bf.rx_ts_nsec << 16) | - ptp_rx_ts1_4_reg.bf.rx_ts_nsec; - time->fracnanoseconds = - ((a_int32_t)ptp_rx_ts1_5_reg.bf.rx_ts_nfsec << 8) | - ptp_rx_ts1_6_reg.bf.rx_ts_nfsec; - - return SW_OK; - } - return SW_NOT_FOUND; -} - -sw_error_t -qca808x_phy_ptp_rx_timestamp2_get(a_uint32_t dev_id, a_uint32_t phy_id, - fal_ptp_pkt_info_t *pkt_info, fal_ptp_time_t *time) -{ - union ptp_rx_seqid2_reg_u ptp_rx_seqid2_reg = {0}; - union ptp_rx_portid2_0_reg_u ptp_rx_portid2_0_reg = {0}; - union ptp_rx_portid2_1_reg_u ptp_rx_portid2_1_reg = {0}; - union ptp_rx_portid2_2_reg_u ptp_rx_portid2_2_reg = {0}; - union ptp_rx_portid2_3_reg_u ptp_rx_portid2_3_reg = {0}; - union ptp_rx_portid2_4_reg_u ptp_rx_portid2_4_reg = {0}; - union ptp_rx_ts2_0_reg_u ptp_rx_ts2_0_reg = {0}; - union ptp_rx_ts2_1_reg_u ptp_rx_ts2_1_reg = {0}; - union ptp_rx_ts2_2_reg_u ptp_rx_ts2_2_reg = {0}; - union ptp_rx_ts2_3_reg_u ptp_rx_ts2_3_reg = {0}; - union ptp_rx_ts2_4_reg_u ptp_rx_ts2_4_reg = {0}; - union ptp_rx_ts2_5_reg_u ptp_rx_ts2_5_reg = {0}; - union ptp_rx_ts2_6_reg_u ptp_rx_ts2_6_reg = {0}; - - a_uint64_t clock_id; - a_uint32_t port_num, msgtype; - - SW_RTN_ON_ERROR(qca808x_ptp_rx_seqid2_reg_get(dev_id, phy_id, &ptp_rx_seqid2_reg)); - if (pkt_info->sequence_id != ptp_rx_seqid2_reg.bf.rx_seqid) - { - return SW_NOT_FOUND; - } - - SW_RTN_ON_ERROR(qca808x_ptp_rx_portid2_0_reg_get(dev_id, - phy_id, &ptp_rx_portid2_0_reg)); - SW_RTN_ON_ERROR(qca808x_ptp_rx_portid2_1_reg_get(dev_id, - phy_id, &ptp_rx_portid2_1_reg)); - SW_RTN_ON_ERROR(qca808x_ptp_rx_portid2_2_reg_get(dev_id, - phy_id, &ptp_rx_portid2_2_reg)); - SW_RTN_ON_ERROR(qca808x_ptp_rx_portid2_3_reg_get(dev_id, - phy_id, &ptp_rx_portid2_3_reg)); - SW_RTN_ON_ERROR(qca808x_ptp_rx_portid2_4_reg_get(dev_id, - phy_id, &ptp_rx_portid2_4_reg)); - SW_RTN_ON_ERROR(qca808x_ptp_rx_ts2_0_reg_get(dev_id, - phy_id, &ptp_rx_ts2_0_reg)); - SW_RTN_ON_ERROR(qca808x_ptp_rx_ts2_1_reg_get(dev_id, - phy_id, &ptp_rx_ts2_1_reg)); - SW_RTN_ON_ERROR(qca808x_ptp_rx_ts2_2_reg_get(dev_id, - phy_id, &ptp_rx_ts2_2_reg)); - SW_RTN_ON_ERROR(qca808x_ptp_rx_ts2_3_reg_get(dev_id, - phy_id, &ptp_rx_ts2_3_reg)); - SW_RTN_ON_ERROR(qca808x_ptp_rx_ts2_4_reg_get(dev_id, - phy_id, &ptp_rx_ts2_4_reg)); - SW_RTN_ON_ERROR(qca808x_ptp_rx_ts2_5_reg_get(dev_id, - phy_id, &ptp_rx_ts2_5_reg)); - SW_RTN_ON_ERROR(qca808x_ptp_rx_ts2_6_reg_get(dev_id, - phy_id, &ptp_rx_ts2_6_reg)); - - clock_id = ((a_uint64_t)ptp_rx_portid2_0_reg.bf.rx_portid << 48) | - ((a_uint64_t)ptp_rx_portid2_1_reg.bf.rx_portid << 32) | - ((a_uint64_t)ptp_rx_portid2_2_reg.bf.rx_portid << 16) | - ptp_rx_portid2_3_reg.bf.rx_portid; - port_num = ptp_rx_portid2_4_reg.bf.rx_portid; - msgtype = ptp_rx_ts2_5_reg.bf.rx_msg_type; - - if (pkt_info->clock_identify == clock_id && - pkt_info->port_number == port_num && - pkt_info->msg_type == msgtype) - { - time->seconds = - ((a_int64_t)ptp_rx_ts2_0_reg.bf.rx_ts_sec << 32) | - ((a_int64_t)ptp_rx_ts2_1_reg.bf.rx_ts_sec << 16) | - ptp_rx_ts2_2_reg.bf.rx_ts_sec; - time->nanoseconds = - ((a_int32_t)ptp_rx_ts2_3_reg.bf.rx_ts_nsec << 16) | - ptp_rx_ts2_4_reg.bf.rx_ts_nsec; - time->fracnanoseconds = - ((a_int32_t)ptp_rx_ts2_5_reg.bf.rx_ts_nfsec << 8) | - ptp_rx_ts2_6_reg.bf.rx_ts_nfsec; - - return SW_OK; - } - return SW_NOT_FOUND; -} - -sw_error_t -qca808x_phy_ptp_rx_timestamp3_get(a_uint32_t dev_id, a_uint32_t phy_id, - fal_ptp_pkt_info_t *pkt_info, fal_ptp_time_t *time) -{ - union ptp_rx_seqid3_reg_u ptp_rx_seqid3_reg = {0}; - union ptp_rx_portid3_0_reg_u ptp_rx_portid3_0_reg = {0}; - union ptp_rx_portid3_1_reg_u ptp_rx_portid3_1_reg = {0}; - union ptp_rx_portid3_2_reg_u ptp_rx_portid3_2_reg = {0}; - union ptp_rx_portid3_3_reg_u ptp_rx_portid3_3_reg = {0}; - union ptp_rx_portid3_4_reg_u ptp_rx_portid3_4_reg = {0}; - union ptp_rx_ts3_0_reg_u ptp_rx_ts3_0_reg = {0}; - union ptp_rx_ts3_1_reg_u ptp_rx_ts3_1_reg = {0}; - union ptp_rx_ts3_2_reg_u ptp_rx_ts3_2_reg = {0}; - union ptp_rx_ts3_3_reg_u ptp_rx_ts3_3_reg = {0}; - union ptp_rx_ts3_4_reg_u ptp_rx_ts3_4_reg = {0}; - union ptp_rx_ts3_5_reg_u ptp_rx_ts3_5_reg = {0}; - union ptp_rx_ts3_6_reg_u ptp_rx_ts3_6_reg = {0}; - - a_uint64_t clock_id; - a_uint32_t port_num, msgtype; - - SW_RTN_ON_ERROR(qca808x_ptp_rx_seqid3_reg_get(dev_id, phy_id, &ptp_rx_seqid3_reg)); - if (pkt_info->sequence_id != ptp_rx_seqid3_reg.bf.rx_seqid) - { - return SW_NOT_FOUND; - } - SW_RTN_ON_ERROR(qca808x_ptp_rx_portid3_0_reg_get(dev_id, - phy_id, &ptp_rx_portid3_0_reg)); - SW_RTN_ON_ERROR(qca808x_ptp_rx_portid3_1_reg_get(dev_id, - phy_id, &ptp_rx_portid3_1_reg)); - SW_RTN_ON_ERROR(qca808x_ptp_rx_portid3_2_reg_get(dev_id, - phy_id, &ptp_rx_portid3_2_reg)); - SW_RTN_ON_ERROR(qca808x_ptp_rx_portid3_3_reg_get(dev_id, - phy_id, &ptp_rx_portid3_3_reg)); - SW_RTN_ON_ERROR(qca808x_ptp_rx_portid3_4_reg_get(dev_id, - phy_id, &ptp_rx_portid3_4_reg)); - SW_RTN_ON_ERROR(qca808x_ptp_rx_ts3_0_reg_get(dev_id, - phy_id, &ptp_rx_ts3_0_reg)); - SW_RTN_ON_ERROR(qca808x_ptp_rx_ts3_1_reg_get(dev_id, - phy_id, &ptp_rx_ts3_1_reg)); - SW_RTN_ON_ERROR(qca808x_ptp_rx_ts3_2_reg_get(dev_id, - phy_id, &ptp_rx_ts3_2_reg)); - SW_RTN_ON_ERROR(qca808x_ptp_rx_ts3_3_reg_get(dev_id, - phy_id, &ptp_rx_ts3_3_reg)); - SW_RTN_ON_ERROR(qca808x_ptp_rx_ts3_4_reg_get(dev_id, - phy_id, &ptp_rx_ts3_4_reg)); - SW_RTN_ON_ERROR(qca808x_ptp_rx_ts3_5_reg_get(dev_id, - phy_id, &ptp_rx_ts3_5_reg)); - SW_RTN_ON_ERROR(qca808x_ptp_rx_ts3_6_reg_get(dev_id, - phy_id, &ptp_rx_ts3_6_reg)); - - clock_id = ((a_uint64_t)ptp_rx_portid3_0_reg.bf.rx_portid << 48) | - ((a_uint64_t)ptp_rx_portid3_1_reg.bf.rx_portid << 32) | - ((a_uint64_t)ptp_rx_portid3_2_reg.bf.rx_portid << 16) | - ptp_rx_portid3_3_reg.bf.rx_portid; - port_num = ptp_rx_portid3_4_reg.bf.rx_portid; - msgtype = ptp_rx_ts3_5_reg.bf.rx_msg_type; - if (pkt_info->clock_identify == clock_id && - pkt_info->port_number == port_num && - pkt_info->msg_type == msgtype) - { - time->seconds = - ((a_int64_t)ptp_rx_ts3_0_reg.bf.rx_ts_sec << 32) | - ((a_int64_t)ptp_rx_ts3_1_reg.bf.rx_ts_sec << 16) | - ptp_rx_ts3_2_reg.bf.rx_ts_sec; - time->nanoseconds = - ((a_int32_t)ptp_rx_ts3_3_reg.bf.rx_ts_nsec << 16) | - ptp_rx_ts3_4_reg.bf.rx_ts_nsec; - time->fracnanoseconds = - ((a_int32_t)ptp_rx_ts3_5_reg.bf.rx_ts_nfsec << 8) | - ptp_rx_ts3_6_reg.bf.rx_ts_nfsec; - - return SW_OK; - } - return SW_NOT_FOUND; -} - -sw_error_t -qca808x_phy_ptp_tx_timestamp0_get(a_uint32_t dev_id, a_uint32_t phy_id, - fal_ptp_pkt_info_t *pkt_info, fal_ptp_time_t *time) -{ - union ptp_tx_seqid_reg_u ptp_tx_seqid_reg = {0}; - union ptp_tx_portid0_reg_u ptp_tx_portid0_reg = {0}; - union ptp_tx_portid1_reg_u ptp_tx_portid1_reg = {0}; - union ptp_tx_portid2_reg_u ptp_tx_portid2_reg = {0}; - union ptp_tx_portid3_reg_u ptp_tx_portid3_reg = {0}; - union ptp_tx_portid4_reg_u ptp_tx_portid4_reg = {0}; - union ptp_tx_ts0_reg_u ptp_tx_ts0_reg = {0}; - union ptp_tx_ts1_reg_u ptp_tx_ts1_reg = {0}; - union ptp_tx_ts2_reg_u ptp_tx_ts2_reg = {0}; - union ptp_tx_ts3_reg_u ptp_tx_ts3_reg = {0}; - union ptp_tx_ts4_reg_u ptp_tx_ts4_reg = {0}; - union ptp_tx_ts5_reg_u ptp_tx_ts5_reg = {0}; - union ptp_tx_ts6_reg_u ptp_tx_ts6_reg = {0}; - - a_uint64_t clock_id; - a_uint32_t port_num, msgtype; - - SW_RTN_ON_ERROR(qca808x_ptp_tx_seqid_reg_get(dev_id, phy_id, &ptp_tx_seqid_reg)); - if (pkt_info->sequence_id != ptp_tx_seqid_reg.bf.tx_seqid) - { - return SW_NOT_FOUND; - } - - SW_RTN_ON_ERROR(qca808x_ptp_tx_portid0_reg_get(dev_id, - phy_id, &ptp_tx_portid0_reg)); - SW_RTN_ON_ERROR(qca808x_ptp_tx_portid1_reg_get(dev_id, - phy_id, &ptp_tx_portid1_reg)); - SW_RTN_ON_ERROR(qca808x_ptp_tx_portid2_reg_get(dev_id, - phy_id, &ptp_tx_portid2_reg)); - SW_RTN_ON_ERROR(qca808x_ptp_tx_portid3_reg_get(dev_id, - phy_id, &ptp_tx_portid3_reg)); - SW_RTN_ON_ERROR(qca808x_ptp_tx_portid4_reg_get(dev_id, - phy_id, &ptp_tx_portid4_reg)); - SW_RTN_ON_ERROR(qca808x_ptp_tx_ts0_reg_get(dev_id, - phy_id, &ptp_tx_ts0_reg)); - SW_RTN_ON_ERROR(qca808x_ptp_tx_ts1_reg_get(dev_id, - phy_id, &ptp_tx_ts1_reg)); - SW_RTN_ON_ERROR(qca808x_ptp_tx_ts2_reg_get(dev_id, - phy_id, &ptp_tx_ts2_reg)); - SW_RTN_ON_ERROR(qca808x_ptp_tx_ts3_reg_get(dev_id, - phy_id, &ptp_tx_ts3_reg)); - SW_RTN_ON_ERROR(qca808x_ptp_tx_ts4_reg_get(dev_id, - phy_id, &ptp_tx_ts4_reg)); - SW_RTN_ON_ERROR(qca808x_ptp_tx_ts5_reg_get(dev_id, - phy_id, &ptp_tx_ts5_reg)); - SW_RTN_ON_ERROR(qca808x_ptp_tx_ts6_reg_get(dev_id, - phy_id, &ptp_tx_ts6_reg)); - clock_id = ((a_uint64_t)ptp_tx_portid0_reg.bf.tx_portid << 48) | - ((a_uint64_t)ptp_tx_portid1_reg.bf.tx_portid << 32) | - ((a_uint64_t)ptp_tx_portid2_reg.bf.tx_portid << 16) | - ptp_tx_portid3_reg.bf.tx_portid; - port_num = ptp_tx_portid4_reg.bf.tx_portid; - msgtype = ptp_tx_ts5_reg.bf.tx_msg_type; - if (pkt_info->clock_identify == clock_id && - pkt_info->port_number == port_num && - pkt_info->msg_type == msgtype) - { - time->seconds = - ((a_int64_t)ptp_tx_ts0_reg.bf.tx_ts_sec << 32) | - ((a_int64_t)ptp_tx_ts1_reg.bf.tx_ts_sec << 16) | - ptp_tx_ts2_reg.bf.tx_ts_sec; - time->nanoseconds = - ((a_int32_t)ptp_tx_ts3_reg.bf.tx_ts_nsec << 16) | - ptp_tx_ts4_reg.bf.tx_ts_nsec; - time->fracnanoseconds = - ((a_int32_t)ptp_tx_ts5_reg.bf.tx_ts_nfsec << 8) | - ptp_tx_ts6_reg.bf.tx_ts_nfsec; - - return SW_OK; - } - return SW_NOT_FOUND; -} - -sw_error_t -qca808x_phy_ptp_timestamp_get(a_uint32_t dev_id, - a_uint32_t phy_id, fal_ptp_direction_t direction, - fal_ptp_pkt_info_t *pkt_info, fal_ptp_time_t *time) -{ - sw_error_t ret = SW_NOT_FOUND; - a_uint32_t seq = 0; - if (direction == FAL_RX_DIRECTION) - { - for (seq = 0; seq < 4; seq++) { - switch (seq) { - case 0: - ret = qca808x_phy_ptp_rx_timestamp0_get(dev_id, phy_id, - pkt_info, time); - if (ret == SW_OK) { - return ret; - } - break; - case 1: - ret = qca808x_phy_ptp_rx_timestamp1_get(dev_id, phy_id, - pkt_info, time); - if (ret == SW_OK) { - return ret; - } - break; - case 2: - ret = qca808x_phy_ptp_rx_timestamp2_get(dev_id, phy_id, - pkt_info, time); - if (ret == SW_OK) { - return ret; - } - break; - case 3: - ret = qca808x_phy_ptp_rx_timestamp3_get(dev_id, phy_id, - pkt_info, time); - if (ret == SW_OK) { - return ret; - } - break; - default: - break; - } - } - } else { - ret = qca808x_phy_ptp_tx_timestamp0_get(dev_id, phy_id, pkt_info, time); - } - - return ret; -} - -sw_error_t -qca808x_phy_ptp_pkt_timestamp_set(a_uint32_t dev_id, - a_uint32_t phy_id, fal_ptp_time_t *time) -{ - union ptp_in_trig0_reg_u ptp_in_trig0_reg = {0}; - union ptp_in_trig1_reg_u ptp_in_trig1_reg = {0}; - union ptp_in_trig2_reg_u ptp_in_trig2_reg = {0}; - union ptp_in_trig3_reg_u ptp_in_trig3_reg = {0}; - - SW_RTN_ON_ERROR(qca808x_ptp_in_trig0_reg_get(dev_id, phy_id, &ptp_in_trig0_reg)); - ptp_in_trig0_reg.bf.ptp_in_trig_nisec = time->nanoseconds >> 16; - SW_RTN_ON_ERROR(qca808x_ptp_in_trig0_reg_set(dev_id, phy_id, &ptp_in_trig0_reg)); - - SW_RTN_ON_ERROR(qca808x_ptp_in_trig1_reg_get(dev_id, phy_id, &ptp_in_trig1_reg)); - ptp_in_trig1_reg.bf.ptp_in_trig_nisec = time->nanoseconds & 0xffff; - SW_RTN_ON_ERROR(qca808x_ptp_in_trig1_reg_set(dev_id, phy_id, &ptp_in_trig1_reg)); - - SW_RTN_ON_ERROR(qca808x_ptp_in_trig2_reg_get(dev_id, phy_id, &ptp_in_trig2_reg)); - ptp_in_trig2_reg.bf.ptp_in_trig_nisec = time->fracnanoseconds >> 4; - SW_RTN_ON_ERROR(qca808x_ptp_in_trig2_reg_set(dev_id, phy_id, &ptp_in_trig2_reg)); - - SW_RTN_ON_ERROR(qca808x_ptp_in_trig3_reg_get(dev_id, phy_id, &ptp_in_trig3_reg)); - ptp_in_trig3_reg.bf.ptp_in_trig_nisec = time->fracnanoseconds & 0xf; - SW_RTN_ON_ERROR(qca808x_ptp_in_trig3_reg_set(dev_id, phy_id, &ptp_in_trig3_reg)); - - return SW_OK; -} - -sw_error_t -qca808x_phy_ptp_pkt_timestamp_get(a_uint32_t dev_id, - a_uint32_t phy_id, fal_ptp_time_t *time) -{ - union ptp_in_trig0_reg_u ptp_in_trig0_reg = {0}; - union ptp_in_trig1_reg_u ptp_in_trig1_reg = {0}; - union ptp_in_trig2_reg_u ptp_in_trig2_reg = {0}; - union ptp_in_trig3_reg_u ptp_in_trig3_reg = {0}; - - SW_RTN_ON_ERROR(qca808x_ptp_in_trig0_reg_get(dev_id, phy_id, &ptp_in_trig0_reg)); - SW_RTN_ON_ERROR(qca808x_ptp_in_trig1_reg_get(dev_id, phy_id, &ptp_in_trig1_reg)); - time->nanoseconds = (ptp_in_trig0_reg.bf.ptp_in_trig_nisec << 16) | - ptp_in_trig1_reg.bf.ptp_in_trig_nisec; - - SW_RTN_ON_ERROR(qca808x_ptp_in_trig2_reg_get(dev_id, phy_id, &ptp_in_trig2_reg)); - SW_RTN_ON_ERROR(qca808x_ptp_in_trig3_reg_get(dev_id, phy_id, &ptp_in_trig3_reg)); - time->fracnanoseconds = (ptp_in_trig2_reg.bf.ptp_in_trig_nisec << 4) | - (ptp_in_trig3_reg.bf.ptp_in_trig_nisec & 0xf); - - return SW_OK; -} - -sw_error_t -qca808x_phy_ptp_grandmaster_mode_set(a_uint32_t dev_id, - a_uint32_t phy_id, fal_ptp_grandmaster_mode_t *gm_mode) -{ - union ptp_gm_conf0_reg_u ptp_gm_conf0_reg = {0}; - union ptp_gm_conf1_reg_u ptp_gm_conf1_reg = {0}; - - SW_RTN_ON_ERROR(qca808x_ptp_gm_conf0_reg_get(dev_id, phy_id, &ptp_gm_conf0_reg)); - SW_RTN_ON_ERROR(qca808x_ptp_gm_conf1_reg_get(dev_id, phy_id, &ptp_gm_conf1_reg)); - ptp_gm_conf0_reg.bf.grandmaster_mode = gm_mode->grandmaster_mode_en; - if (gm_mode->ns_sync_mode == FAL_GM_PPSIN_MODE) - { - ptp_gm_conf0_reg.bf.gm_pps_sync = PTP_REG_BIT_TRUE; - ptp_gm_conf0_reg.bf.gm_pll_mode = PTP_REG_BIT_FALSE; - } - else if (gm_mode->ns_sync_mode == FAL_GM_HWPLL_MODE) - { - ptp_gm_conf0_reg.bf.gm_pps_sync = PTP_REG_BIT_FALSE; - ptp_gm_conf0_reg.bf.gm_pll_mode = PTP_REG_BIT_TRUE; - } - else - { - ptp_gm_conf0_reg.bf.gm_pps_sync = PTP_REG_BIT_FALSE; - ptp_gm_conf0_reg.bf.gm_pll_mode = PTP_REG_BIT_FALSE; - } - ptp_gm_conf0_reg.bf.gm_maxfreq_offset = gm_mode->freq_offset; - ptp_gm_conf1_reg.bf.gm_kp_ldn = - (gm_mode->right_shift_in_kp << (PTP_GM_CONF1_REG_GM_KP_LDN_LEN-1)) | - gm_mode->kp_value; - ptp_gm_conf1_reg.bf.gm_ki_ldn = - (gm_mode->right_shift_in_ki << (PTP_GM_CONF1_REG_GM_KI_LDN_LEN-1)) | - gm_mode->ki_value; - SW_RTN_ON_ERROR(qca808x_ptp_gm_conf0_reg_set(dev_id, phy_id, &ptp_gm_conf0_reg)); - SW_RTN_ON_ERROR(qca808x_ptp_gm_conf1_reg_set(dev_id, phy_id, &ptp_gm_conf1_reg)); - -#if defined(IN_LINUX_STD_PTP) - if (gm_mode->grandmaster_second_sync_en == A_TRUE) { - qca808x_ptp_gm_gps_seconds_sync_enable(dev_id, phy_id, A_TRUE); - } else { - qca808x_ptp_gm_gps_seconds_sync_enable(dev_id, phy_id, A_FALSE); - } -#endif - - return SW_OK; -} - -sw_error_t -qca808x_phy_ptp_grandmaster_mode_get(a_uint32_t dev_id, - a_uint32_t phy_id, fal_ptp_grandmaster_mode_t *gm_mode) -{ - union ptp_gm_conf0_reg_u ptp_gm_conf0_reg = {0}; - union ptp_gm_conf1_reg_u ptp_gm_conf1_reg = {0}; - - SW_RTN_ON_ERROR(qca808x_ptp_gm_conf0_reg_get(dev_id, phy_id, &ptp_gm_conf0_reg)); - SW_RTN_ON_ERROR(qca808x_ptp_gm_conf1_reg_get(dev_id, phy_id, &ptp_gm_conf1_reg)); - gm_mode->grandmaster_mode_en = ptp_gm_conf0_reg.bf.grandmaster_mode; - if (ptp_gm_conf0_reg.bf.gm_pps_sync == 1 && ptp_gm_conf0_reg.bf.gm_pll_mode == 0) - { - gm_mode->ns_sync_mode = FAL_GM_PPSIN_MODE; - } - else if (ptp_gm_conf0_reg.bf.gm_pps_sync == 0 && ptp_gm_conf0_reg.bf.gm_pll_mode == 1) - { - gm_mode->ns_sync_mode = FAL_GM_HWPLL_MODE; - } - else - { - gm_mode->ns_sync_mode = FAL_GM_SWPLL_MODE; - } - gm_mode->freq_offset = ptp_gm_conf0_reg.bf.gm_maxfreq_offset; - gm_mode->right_shift_in_kp = ptp_gm_conf1_reg.bf.gm_kp_ldn >> 5; - gm_mode->kp_value = ptp_gm_conf1_reg.bf.gm_kp_ldn & 0x1f; - gm_mode->right_shift_in_ki = ptp_gm_conf1_reg.bf.gm_ki_ldn >> 5; - gm_mode->ki_value = ptp_gm_conf1_reg.bf.gm_ki_ldn & 0x1f; - -#if defined(IN_LINUX_STD_PTP) - if (qca808x_ptp_gm_gps_seconds_sync_status_get(dev_id, phy_id) == A_TRUE) { - gm_mode->grandmaster_second_sync_en = A_TRUE; - } else { - gm_mode->grandmaster_second_sync_en = A_FALSE; - } -#endif - - return SW_OK; -} - -sw_error_t -qca808x_phy_ptp_rtc_time_get(a_uint32_t dev_id, - a_uint32_t phy_id, fal_ptp_time_t *time) -{ - union ptp_rtc0_reg_u ptp_rtc0_reg = {0}; - union ptp_rtc1_reg_u ptp_rtc1_reg = {0}; - union ptp_rtc2_reg_u ptp_rtc2_reg = {0}; - union ptp_rtc3_reg_u ptp_rtc3_reg = {0}; - union ptp_rtc4_reg_u ptp_rtc4_reg = {0}; - union ptp_rtc5_reg_u ptp_rtc5_reg = {0}; - union ptp_rtc6_reg_u ptp_rtc6_reg = {0}; - - SW_RTN_ON_ERROR(qca808x_ptp_rtc0_reg_get(dev_id, phy_id, &ptp_rtc0_reg)); - SW_RTN_ON_ERROR(qca808x_ptp_rtc1_reg_get(dev_id, phy_id, &ptp_rtc1_reg)); - SW_RTN_ON_ERROR(qca808x_ptp_rtc2_reg_get(dev_id, phy_id, &ptp_rtc2_reg)); - time->seconds = ((a_int64_t)ptp_rtc0_reg.bf.ptp_rtc_sec << 32) | - (ptp_rtc1_reg.bf.ptp_rtc_sec << 16) | ptp_rtc2_reg.bf.ptp_rtc_sec; - - SW_RTN_ON_ERROR(qca808x_ptp_rtc3_reg_get(dev_id, phy_id, &ptp_rtc3_reg)); - SW_RTN_ON_ERROR(qca808x_ptp_rtc4_reg_get(dev_id, phy_id, &ptp_rtc4_reg)); - time->nanoseconds = (ptp_rtc3_reg.bf.ptp_rtc_nisec << 16) | ptp_rtc4_reg.bf.ptp_rtc_nisec; - - SW_RTN_ON_ERROR(qca808x_ptp_rtc5_reg_get(dev_id, phy_id, &ptp_rtc5_reg)); - SW_RTN_ON_ERROR(qca808x_ptp_rtc6_reg_get(dev_id, phy_id, &ptp_rtc6_reg)); - time->fracnanoseconds = (ptp_rtc5_reg.bf.ptp_rtc_nfsec << 4) | - ptp_rtc6_reg.bf.ptp_rtc_nfsec; - - return SW_OK; -} - -sw_error_t -qca808x_phy_ptp_rtc_time_set(a_uint32_t dev_id, - a_uint32_t phy_id, fal_ptp_time_t *time) -{ - union ptp_rtc_preloaded0_reg_u ptp_rtc_preloaded0_reg = {0}; - union ptp_rtc_preloaded1_reg_u ptp_rtc_preloaded1_reg = {0}; - union ptp_rtc_preloaded2_reg_u ptp_rtc_preloaded2_reg = {0}; - union ptp_rtc_preloaded3_reg_u ptp_rtc_preloaded3_reg = {0}; - union ptp_rtc_preloaded4_reg_u ptp_rtc_preloaded4_reg = {0}; - union ptp_rtc_ext_conf_reg_u ptp_rtc_ext_conf_reg = {0}; - - ptp_rtc_preloaded0_reg.bf.ptp_rtc_preloaded_sec = (time->seconds >> 32) & 0xffff; - ptp_rtc_preloaded1_reg.bf.ptp_rtc_preloaded_sec = (time->seconds >> 16) & 0xffff; - ptp_rtc_preloaded2_reg.bf.ptp_rtc_preloaded_sec = time->seconds & 0xffff; - SW_RTN_ON_ERROR(qca808x_ptp_rtc_preloaded0_reg_set(dev_id, - phy_id, &ptp_rtc_preloaded0_reg)); - SW_RTN_ON_ERROR(qca808x_ptp_rtc_preloaded1_reg_set(dev_id, - phy_id, &ptp_rtc_preloaded1_reg)); - SW_RTN_ON_ERROR(qca808x_ptp_rtc_preloaded2_reg_set(dev_id, - phy_id, &ptp_rtc_preloaded2_reg)); - - ptp_rtc_preloaded3_reg.bf.ptp_rtc_preloaded_nisec = time->nanoseconds >> 16; - ptp_rtc_preloaded4_reg.bf.ptp_rtc_preloaded_nisec = time->nanoseconds & 0xffff; - SW_RTN_ON_ERROR(qca808x_ptp_rtc_preloaded3_reg_set(dev_id, - phy_id, &ptp_rtc_preloaded3_reg)); - SW_RTN_ON_ERROR(qca808x_ptp_rtc_preloaded4_reg_set(dev_id, - phy_id, &ptp_rtc_preloaded4_reg)); - - SW_RTN_ON_ERROR(qca808x_ptp_rtc_ext_conf_reg_get(dev_id, - phy_id, &ptp_rtc_ext_conf_reg)); - ptp_rtc_ext_conf_reg.bf.load_rtc = 1; - SW_RTN_ON_ERROR(qca808x_ptp_rtc_ext_conf_reg_set(dev_id, - phy_id, &ptp_rtc_ext_conf_reg)); - - return SW_OK; -} - -sw_error_t -qca808x_phy_ptp_rtc_time_clear(a_uint32_t dev_id, - a_uint32_t phy_id) -{ - union ptp_rtc_ext_conf_reg_u ptp_rtc_ext_conf_reg = {0}; - - SW_RTN_ON_ERROR(qca808x_ptp_rtc_ext_conf_reg_get(dev_id, phy_id, &ptp_rtc_ext_conf_reg)); - ptp_rtc_ext_conf_reg.bf.clear_rtc = PTP_REG_BIT_TRUE; - SW_RTN_ON_ERROR(qca808x_ptp_rtc_ext_conf_reg_set(dev_id, phy_id, &ptp_rtc_ext_conf_reg)); - - return SW_OK; -} - -sw_error_t -qca808x_phy_ptp_rtc_adjtime_set(a_uint32_t dev_id, - a_uint32_t phy_id, fal_ptp_time_t *time) -{ - union ptp_rtcoffs0_reg_u ptp_rtcoffs0_reg = {0}; - union ptp_rtcoffs1_reg_u ptp_rtcoffs1_reg = {0}; - union ptp_rtcoffs2_reg_u ptp_rtcoffs2_reg = {0}; - union ptp_rtcoffs3_reg_u ptp_rtcoffs3_reg = {0}; - union ptp_rtcoffs4_reg_u ptp_rtcoffs4_reg = {0}; - union ptp_rtcoffs_valid_reg_u ptp_rtcoffs_valid_reg = {0}; - - ptp_rtcoffs0_reg.bf.ptp_rtcoffs_nsec = time->nanoseconds >> 16; - ptp_rtcoffs1_reg.bf.ptp_rtcoffs_nsec = time->nanoseconds & 0xffff; - ptp_rtcoffs2_reg.bf.ptp_rtcoffs_sec = (time->seconds >> 32) & 0xffff; - ptp_rtcoffs3_reg.bf.ptp_rtcoffs_sec = (time->seconds >> 16) & 0xffff; - ptp_rtcoffs4_reg.bf.ptp_rtcoffs_sec = time->seconds & 0xffff; - ptp_rtcoffs_valid_reg.bf.ptp_rtcoffs_valid = 1; - SW_RTN_ON_ERROR(qca808x_ptp_rtcoffs0_reg_set(dev_id, phy_id, &ptp_rtcoffs0_reg)); - SW_RTN_ON_ERROR(qca808x_ptp_rtcoffs1_reg_set(dev_id, phy_id, &ptp_rtcoffs1_reg)); - SW_RTN_ON_ERROR(qca808x_ptp_rtcoffs2_reg_set(dev_id, phy_id, &ptp_rtcoffs2_reg)); - SW_RTN_ON_ERROR(qca808x_ptp_rtcoffs3_reg_set(dev_id, phy_id, &ptp_rtcoffs3_reg)); - SW_RTN_ON_ERROR(qca808x_ptp_rtcoffs4_reg_set(dev_id, phy_id, &ptp_rtcoffs4_reg)); - SW_RTN_ON_ERROR(qca808x_ptp_rtcoffs_valid_reg_set(dev_id, phy_id, &ptp_rtcoffs_valid_reg)); - - return SW_OK; -} - -sw_error_t -qca808x_phy_ptp_rtc_adjfreq_set(a_uint32_t dev_id, - a_uint32_t phy_id, fal_ptp_time_t *time) -{ - union ptp_rtc_ext_conf_reg_u ptp_rtc_ext_conf_reg = {0}; - union ptp_rtc_inc0_reg_u ptp_rtc_inc0_reg = {0}; - union ptp_rtc_inc1_reg_u ptp_rtc_inc1_reg = {0}; - - SW_RTN_ON_ERROR(qca808x_ptp_rtc_inc0_reg_get(dev_id, phy_id, &ptp_rtc_inc0_reg)); - ptp_rtc_inc0_reg.bf.ptp_rtc_inc_nis = time->nanoseconds & 0x3f; - ptp_rtc_inc0_reg.bf.ptp_rtc_inc_nfs = (time->fracnanoseconds >> 16) & 0x3ff; - SW_RTN_ON_ERROR(qca808x_ptp_rtc_inc0_reg_set(dev_id, phy_id, &ptp_rtc_inc0_reg)); - - SW_RTN_ON_ERROR(qca808x_ptp_rtc_inc1_reg_get(dev_id, phy_id, &ptp_rtc_inc1_reg)); - ptp_rtc_inc1_reg.bf.ptp_rtc_inc_nfs = time->fracnanoseconds & 0xffff; - SW_RTN_ON_ERROR(qca808x_ptp_rtc_inc1_reg_set(dev_id, phy_id, &ptp_rtc_inc1_reg)); - - SW_RTN_ON_ERROR(qca808x_ptp_rtc_ext_conf_reg_get(dev_id, phy_id, &ptp_rtc_ext_conf_reg)); - ptp_rtc_ext_conf_reg.bf.set_incval_valid = PTP_REG_BIT_TRUE; - SW_RTN_ON_ERROR(qca808x_ptp_rtc_ext_conf_reg_set(dev_id, phy_id, &ptp_rtc_ext_conf_reg)); - - return SW_OK; -} - -sw_error_t -qca808x_phy_ptp_rtc_adjfreq_get(a_uint32_t dev_id, - a_uint32_t phy_id, fal_ptp_time_t *time) -{ - union ptp_rtc_inc0_reg_u ptp_rtc_inc0_reg = {0}; - union ptp_rtc_inc1_reg_u ptp_rtc_inc1_reg = {0}; - - SW_RTN_ON_ERROR(qca808x_ptp_rtc_inc0_reg_get(dev_id, phy_id, &ptp_rtc_inc0_reg)); - SW_RTN_ON_ERROR(qca808x_ptp_rtc_inc1_reg_get(dev_id, phy_id, &ptp_rtc_inc1_reg)); - time->nanoseconds = ptp_rtc_inc0_reg.bf.ptp_rtc_inc_nis; - time->fracnanoseconds = (ptp_rtc_inc0_reg.bf.ptp_rtc_inc_nfs << 16) | - ptp_rtc_inc1_reg.bf.ptp_rtc_inc_nfs; - - return SW_OK; -} - -sw_error_t -qca808x_phy_ptp_link_delay_set(a_uint32_t dev_id, - a_uint32_t phy_id, fal_ptp_time_t *time) -{ - union ptp_link_delay_0_reg_u ptp_link_delay_0_reg = {0}; - union ptp_link_delay_1_reg_u ptp_link_delay_1_reg = {0}; - - SW_RTN_ON_ERROR(qca808x_ptp_link_delay_0_reg_get(dev_id, phy_id, &ptp_link_delay_0_reg)); - ptp_link_delay_0_reg.bf.link_delay = time->nanoseconds >> 16; - SW_RTN_ON_ERROR(qca808x_ptp_link_delay_0_reg_set(dev_id, phy_id, &ptp_link_delay_0_reg)); - - SW_RTN_ON_ERROR(qca808x_ptp_link_delay_1_reg_get(dev_id, phy_id, &ptp_link_delay_1_reg)); - ptp_link_delay_1_reg.bf.link_delay = time->nanoseconds & 0xffff; - SW_RTN_ON_ERROR(qca808x_ptp_link_delay_1_reg_set(dev_id, phy_id, &ptp_link_delay_1_reg)); - - return SW_OK; -} - -sw_error_t -qca808x_phy_ptp_link_delay_get(a_uint32_t dev_id, - a_uint32_t phy_id, fal_ptp_time_t *time) -{ - union ptp_link_delay_0_reg_u ptp_link_delay_0_reg = {0}; - union ptp_link_delay_1_reg_u ptp_link_delay_1_reg = {0}; - - SW_RTN_ON_ERROR(qca808x_ptp_link_delay_0_reg_get(dev_id, phy_id, &ptp_link_delay_0_reg)); - SW_RTN_ON_ERROR(qca808x_ptp_link_delay_1_reg_get(dev_id, phy_id, &ptp_link_delay_1_reg)); - time->nanoseconds = (ptp_link_delay_0_reg.bf.link_delay << 16) | - ptp_link_delay_1_reg.bf.link_delay; - - return SW_OK; -} - -sw_error_t -qca808x_phy_ptp_security_set(a_uint32_t dev_id, - a_uint32_t phy_id, fal_ptp_security_t *sec) -{ - union ptp_misc_config_reg_u ptp_misc_config_reg = {0}; - union ptp_main_conf_reg_u ptp_main_conf_reg = {0}; - - SW_RTN_ON_ERROR(qca808x_ptp_misc_config_reg_get(dev_id, phy_id, &ptp_misc_config_reg)); - ptp_misc_config_reg.bf.ptp_addr_chk_en = sec->address_check_en; - ptp_misc_config_reg.bf.ipv6_udp_chk_en = sec->ipv6_udp_checksum_recal_en; - ptp_misc_config_reg.bf.ptp_ver_chk_en = sec->version_check_en; - ptp_misc_config_reg.bf.ptp_version = sec->ptp_version; - SW_RTN_ON_ERROR(qca808x_ptp_misc_config_reg_set(dev_id, phy_id, &ptp_misc_config_reg)); - - SW_RTN_ON_ERROR(qca808x_ptp_main_conf_reg_get(dev_id, phy_id, &ptp_main_conf_reg)); - ptp_main_conf_reg.bf.ipv4_force_checksum_zero = - sec->ipv4_udp_checksum_force_zero_en; - ptp_main_conf_reg.bf.ipv6_embed_force_checksum_zero = - sec->ipv6_embed_udp_checksum_force_zero_en; - SW_RTN_ON_ERROR(qca808x_ptp_main_conf_reg_set(dev_id, phy_id, &ptp_main_conf_reg)); - - return SW_OK; -} - -sw_error_t -qca808x_phy_ptp_security_get(a_uint32_t dev_id, - a_uint32_t phy_id, fal_ptp_security_t *sec) -{ - union ptp_misc_config_reg_u ptp_misc_config_reg = {0}; - union ptp_main_conf_reg_u ptp_main_conf_reg = {0}; - - SW_RTN_ON_ERROR(qca808x_ptp_misc_config_reg_get(dev_id, phy_id, &ptp_misc_config_reg)); - sec->address_check_en = ptp_misc_config_reg.bf.ptp_addr_chk_en; - sec->ipv6_udp_checksum_recal_en = ptp_misc_config_reg.bf.ipv6_udp_chk_en; - sec->version_check_en = ptp_misc_config_reg.bf.ptp_ver_chk_en; - sec->ptp_version = ptp_misc_config_reg.bf.ptp_version; - - SW_RTN_ON_ERROR(qca808x_ptp_main_conf_reg_get(dev_id, phy_id, &ptp_main_conf_reg)); - sec->ipv4_udp_checksum_force_zero_en = ptp_main_conf_reg.bf.ipv4_force_checksum_zero; - sec->ipv6_embed_udp_checksum_force_zero_en = - ptp_main_conf_reg.bf.ipv6_embed_force_checksum_zero; - - return SW_OK; -} - -sw_error_t -qca808x_phy_ptp_pps_signal_control_set(a_uint32_t dev_id, - a_uint32_t phy_id, fal_ptp_pps_signal_control_t *sig_control) -{ - union ptp_ppsin_latency_reg_u ptp_ppsin_latency_reg = {0}; - union ptp_phase_adjust_0_reg_u ptp_phase_adjust_0_reg = {0}; - union ptp_phase_adjust_1_reg_u ptp_phase_adjust_1_reg = {0}; - union ptp_pps_pul_width_0_reg_u ptp_pps_pul_width_0_reg = {0}; - union ptp_pps_pul_width_1_reg_u ptp_pps_pul_width_1_reg = {0}; - - SW_RTN_ON_ERROR(qca808x_ptp_ppsin_latency_reg_get(dev_id, - phy_id, &ptp_ppsin_latency_reg)); - ptp_ppsin_latency_reg.bf.ptp_ppsin_latency_sign = sig_control->negative_in_latency; - ptp_ppsin_latency_reg.bf.ptp_ppsin_latency_value = sig_control->in_latency; - SW_RTN_ON_ERROR(qca808x_ptp_ppsin_latency_reg_set(dev_id, - phy_id, &ptp_ppsin_latency_reg)); - - SW_RTN_ON_ERROR(qca808x_ptp_phase_adjust_0_reg_get(dev_id, - phy_id, &ptp_phase_adjust_0_reg)); - ptp_phase_adjust_0_reg.bf.phase_value = sig_control->out_phase >> 16; - SW_RTN_ON_ERROR(qca808x_ptp_phase_adjust_0_reg_set(dev_id, - phy_id, &ptp_phase_adjust_0_reg)); - - SW_RTN_ON_ERROR(qca808x_ptp_phase_adjust_1_reg_get(dev_id, - phy_id, &ptp_phase_adjust_1_reg)); - ptp_phase_adjust_1_reg.bf.phase_value = sig_control->out_phase & 0xffff; - SW_RTN_ON_ERROR(qca808x_ptp_phase_adjust_1_reg_set(dev_id, - phy_id, &ptp_phase_adjust_1_reg)); - - SW_RTN_ON_ERROR(qca808x_ptp_pps_pul_width_0_reg_get(dev_id, - phy_id, &ptp_pps_pul_width_0_reg)); - ptp_pps_pul_width_0_reg.bf.pul_value = sig_control->out_pulse_width >> 16; - SW_RTN_ON_ERROR(qca808x_ptp_pps_pul_width_0_reg_set(dev_id, - phy_id, &ptp_pps_pul_width_0_reg)); - - SW_RTN_ON_ERROR(qca808x_ptp_pps_pul_width_1_reg_get(dev_id, - phy_id, &ptp_pps_pul_width_1_reg)); - ptp_pps_pul_width_1_reg.bf.pul_value = sig_control->out_pulse_width & 0xffff; - SW_RTN_ON_ERROR(qca808x_ptp_pps_pul_width_1_reg_set(dev_id, - phy_id, &ptp_pps_pul_width_1_reg)); - - return SW_OK; -} - -sw_error_t -qca808x_phy_ptp_pps_signal_control_get(a_uint32_t dev_id, - a_uint32_t phy_id, fal_ptp_pps_signal_control_t *sig_control) -{ - union ptp_ppsin_latency_reg_u ptp_ppsin_latency_reg = {0}; - union ptp_phase_adjust_0_reg_u ptp_phase_adjust_0_reg = {0}; - union ptp_phase_adjust_1_reg_u ptp_phase_adjust_1_reg = {0}; - union ptp_pps_pul_width_0_reg_u ptp_pps_pul_width_0_reg = {0}; - union ptp_pps_pul_width_1_reg_u ptp_pps_pul_width_1_reg = {0}; - - SW_RTN_ON_ERROR(qca808x_ptp_ppsin_latency_reg_get(dev_id, - phy_id, &ptp_ppsin_latency_reg)); - sig_control->negative_in_latency = ptp_ppsin_latency_reg.bf.ptp_ppsin_latency_sign; - sig_control->in_latency = ptp_ppsin_latency_reg.bf.ptp_ppsin_latency_value; - - SW_RTN_ON_ERROR(qca808x_ptp_phase_adjust_0_reg_get(dev_id, - phy_id, &ptp_phase_adjust_0_reg)); - SW_RTN_ON_ERROR(qca808x_ptp_phase_adjust_1_reg_get(dev_id, - phy_id, &ptp_phase_adjust_1_reg)); - sig_control->out_phase = (ptp_phase_adjust_0_reg.bf.phase_value << 16) | - ptp_phase_adjust_1_reg.bf.phase_value; - - SW_RTN_ON_ERROR(qca808x_ptp_pps_pul_width_0_reg_get(dev_id, - phy_id, &ptp_pps_pul_width_0_reg)); - SW_RTN_ON_ERROR(qca808x_ptp_pps_pul_width_1_reg_get(dev_id, - phy_id, &ptp_pps_pul_width_1_reg)); - sig_control->out_pulse_width = (ptp_pps_pul_width_0_reg.bf.pul_value << 16) | - ptp_pps_pul_width_1_reg.bf.pul_value; - - return SW_OK; -} - -sw_error_t -qca808x_phy_ptp_rx_crc_recalc_enable(a_uint32_t dev_id, - a_uint32_t phy_id, a_bool_t status) -{ - union ptp_misc_config_reg_u ptp_misc_config_reg = {0}; - - SW_RTN_ON_ERROR(qca808x_ptp_misc_config_reg_get(dev_id, phy_id, &ptp_misc_config_reg)); - ptp_misc_config_reg.bf.crc_validate_en = status; - SW_RTN_ON_ERROR(qca808x_ptp_misc_config_reg_set(dev_id, phy_id, &ptp_misc_config_reg)); - - return SW_OK; -} - -sw_error_t -qca808x_phy_ptp_rx_crc_recalc_status_get(a_uint32_t dev_id, - a_uint32_t phy_id, a_bool_t *status) -{ - union ptp_misc_config_reg_u ptp_misc_config_reg = {0}; - - SW_RTN_ON_ERROR(qca808x_ptp_misc_config_reg_get(dev_id, phy_id, &ptp_misc_config_reg)); - *status = ptp_misc_config_reg.bf.crc_validate_en; - - return SW_OK; -} - -sw_error_t -qca808x_phy_ptp_asym_correction_set(a_uint32_t dev_id, - a_uint32_t phy_id, fal_ptp_asym_correction_t *asym_cf) -{ - union ptp_misc_control_reg_u ptp_misc_control_reg = {0}; - union ptp_ingress_asymmetry_0_reg_u ptp_ingress_asymmetry_0_reg = {0}; - union ptp_ingress_asymmetry_1_reg_u ptp_ingress_asymmetry_1_reg = {0}; - union ptp_egress_asymmetry_0_reg_u ptp_egress_asymmetry_0_reg = {0}; - union ptp_egress_asymmetry_1_reg_u ptp_egress_asymmetry_1_reg = {0}; - - SW_RTN_ON_ERROR(qca808x_ptp_misc_control_reg_get(dev_id, - phy_id, &ptp_misc_control_reg)); - ptp_misc_control_reg.bf.eg_asym_en = asym_cf->eg_asym_en; - ptp_misc_control_reg.bf.in_asym_en = asym_cf->in_asym_en; - SW_RTN_ON_ERROR(qca808x_ptp_misc_control_reg_set(dev_id, - phy_id, &ptp_misc_control_reg)); - - SW_RTN_ON_ERROR(qca808x_ptp_ingress_asymmetry_0_reg_get(dev_id, - phy_id, &ptp_ingress_asymmetry_0_reg)); - ptp_ingress_asymmetry_0_reg.bf.in_asym = asym_cf->in_asym_value >> 16; - SW_RTN_ON_ERROR(qca808x_ptp_ingress_asymmetry_0_reg_set(dev_id, - phy_id, &ptp_ingress_asymmetry_0_reg)); - - SW_RTN_ON_ERROR(qca808x_ptp_ingress_asymmetry_1_reg_get(dev_id, - phy_id, &ptp_ingress_asymmetry_1_reg)); - ptp_ingress_asymmetry_1_reg.bf.in_asym = asym_cf->in_asym_value & 0xffff; - SW_RTN_ON_ERROR(qca808x_ptp_ingress_asymmetry_1_reg_set(dev_id, - phy_id, &ptp_ingress_asymmetry_1_reg)); - - SW_RTN_ON_ERROR(qca808x_ptp_egress_asymmetry_0_reg_get(dev_id, - phy_id, &ptp_egress_asymmetry_0_reg)); - ptp_egress_asymmetry_0_reg.bf.eg_asym = asym_cf->eg_asym_value >> 16; - SW_RTN_ON_ERROR(qca808x_ptp_egress_asymmetry_0_reg_get(dev_id, - phy_id, &ptp_egress_asymmetry_0_reg)); - - SW_RTN_ON_ERROR(qca808x_ptp_egress_asymmetry_1_reg_get(dev_id, - phy_id, &ptp_egress_asymmetry_1_reg)); - ptp_egress_asymmetry_1_reg.bf.eg_asym = asym_cf->eg_asym_value & 0xffff; - SW_RTN_ON_ERROR(qca808x_ptp_egress_asymmetry_1_reg_set(dev_id, - phy_id, &ptp_egress_asymmetry_1_reg)); - - return SW_OK; -} - -sw_error_t -qca808x_phy_ptp_asym_correction_get(a_uint32_t dev_id, - a_uint32_t phy_id, fal_ptp_asym_correction_t* asym_cf) -{ - union ptp_misc_control_reg_u ptp_misc_control_reg = {0}; - union ptp_ingress_asymmetry_0_reg_u ptp_ingress_asymmetry_0_reg = {0}; - union ptp_ingress_asymmetry_1_reg_u ptp_ingress_asymmetry_1_reg = {0}; - union ptp_egress_asymmetry_0_reg_u ptp_egress_asymmetry_0_reg = {0}; - union ptp_egress_asymmetry_1_reg_u ptp_egress_asymmetry_1_reg = {0}; - - SW_RTN_ON_ERROR(qca808x_ptp_misc_control_reg_get(dev_id, - phy_id, &ptp_misc_control_reg)); - asym_cf->eg_asym_en = ptp_misc_control_reg.bf.eg_asym_en; - asym_cf->in_asym_en = ptp_misc_control_reg.bf.in_asym_en; - - SW_RTN_ON_ERROR(qca808x_ptp_ingress_asymmetry_0_reg_get(dev_id, - phy_id, &ptp_ingress_asymmetry_0_reg)); - SW_RTN_ON_ERROR(qca808x_ptp_ingress_asymmetry_1_reg_get(dev_id, - phy_id, &ptp_ingress_asymmetry_1_reg)); - asym_cf->in_asym_value = (ptp_ingress_asymmetry_0_reg.bf.in_asym << 16) | - ptp_ingress_asymmetry_1_reg.bf.in_asym; - - SW_RTN_ON_ERROR(qca808x_ptp_egress_asymmetry_0_reg_get(dev_id, - phy_id, &ptp_egress_asymmetry_0_reg)); - SW_RTN_ON_ERROR(qca808x_ptp_egress_asymmetry_1_reg_get(dev_id, - phy_id, &ptp_egress_asymmetry_1_reg)); - asym_cf->eg_asym_value = (ptp_egress_asymmetry_0_reg.bf.eg_asym << 16) | - ptp_egress_asymmetry_1_reg.bf.eg_asym; - - return SW_OK; -} - -sw_error_t -qca808x_phy_ptp_output_waveform_set(a_uint32_t dev_id, - a_uint32_t phy_id, fal_ptp_output_waveform_t *waveform) -{ - union ptp_rtc_ext_conf_reg_u ptp_rtc_ext_conf_reg = {0}; - union ptp_freq_waveform_period_0_reg_u ptp_freq_waveform_period_0_reg = {0}; - union ptp_freq_waveform_period_1_reg_u ptp_freq_waveform_period_1_reg = {0}; - union ptp_freq_waveform_period_2_reg_u ptp_freq_waveform_period_2_reg = {0}; - - SW_RTN_ON_ERROR(qca808x_ptp_rtc_ext_conf_reg_get(dev_id, - phy_id, &ptp_rtc_ext_conf_reg)); - if (waveform->waveform_type == FAL_WAVE_FREQ) - { - ptp_rtc_ext_conf_reg.bf.select_output_waveform = - PTP_RTC_EXT_CONF_REG_SELECT_OUTPUT_WAVEFORM_FREQ; - } - else if (waveform->waveform_type == FAL_PULSE_10MS) - { - ptp_rtc_ext_conf_reg.bf.select_output_waveform = - PTP_RTC_EXT_CONF_REG_SELECT_OUTPUT_WAVEFORM_PULSE_10MS; - } - else if (waveform->waveform_type == FAL_TRIGGER0_GPIO) - { - ptp_rtc_ext_conf_reg.bf.select_output_waveform = - PTP_RTC_EXT_CONF_REG_SELECT_OUTPUT_WAVEFORM_TRIG0_GPIO; - } - else - { - ptp_rtc_ext_conf_reg.bf.select_output_waveform = - PTP_RTC_EXT_CONF_REG_SELECT_OUTPUT_WAVEFORM_RXTS_VALID; - } - SW_RTN_ON_ERROR(qca808x_ptp_rtc_ext_conf_reg_set(dev_id, phy_id, &ptp_rtc_ext_conf_reg)); - - ptp_freq_waveform_period_0_reg.bf.phase_ali = waveform->wave_align_pps_out_en; - ptp_freq_waveform_period_0_reg.bf.wave_period = (waveform->wave_period >> 32) & 0x7fff; - ptp_freq_waveform_period_1_reg.bf.wave_period = (waveform->wave_period >> 16) & 0xffff; - ptp_freq_waveform_period_2_reg.bf.wave_period = waveform->wave_period & 0xffff; - SW_RTN_ON_ERROR(qca808x_ptp_freq_waveform_period_0_reg_set(dev_id, - phy_id, &ptp_freq_waveform_period_0_reg)); - SW_RTN_ON_ERROR(qca808x_ptp_freq_waveform_period_1_reg_set(dev_id, - phy_id, &ptp_freq_waveform_period_1_reg)); - SW_RTN_ON_ERROR(qca808x_ptp_freq_waveform_period_2_reg_set(dev_id, - phy_id, &ptp_freq_waveform_period_2_reg)); - - return SW_OK; -} - -sw_error_t -qca808x_phy_ptp_output_waveform_get(a_uint32_t dev_id, - a_uint32_t phy_id, fal_ptp_output_waveform_t *waveform) -{ - union ptp_rtc_ext_conf_reg_u ptp_rtc_ext_conf_reg = {0}; - union ptp_freq_waveform_period_0_reg_u ptp_freq_waveform_period_0_reg = {0}; - union ptp_freq_waveform_period_1_reg_u ptp_freq_waveform_period_1_reg = {0}; - union ptp_freq_waveform_period_2_reg_u ptp_freq_waveform_period_2_reg = {0}; - - SW_RTN_ON_ERROR(qca808x_ptp_rtc_ext_conf_reg_get(dev_id, - phy_id, &ptp_rtc_ext_conf_reg)); - if (ptp_rtc_ext_conf_reg.bf.select_output_waveform == - PTP_RTC_EXT_CONF_REG_SELECT_OUTPUT_WAVEFORM_FREQ) - { - waveform->waveform_type = FAL_WAVE_FREQ; - } - else if (ptp_rtc_ext_conf_reg.bf.select_output_waveform == - PTP_RTC_EXT_CONF_REG_SELECT_OUTPUT_WAVEFORM_PULSE_10MS) - { - waveform->waveform_type = FAL_PULSE_10MS; - } - else if (ptp_rtc_ext_conf_reg.bf.select_output_waveform == - PTP_RTC_EXT_CONF_REG_SELECT_OUTPUT_WAVEFORM_TRIG0_GPIO) - { - waveform->waveform_type = FAL_TRIGGER0_GPIO; - } - else - { - waveform->waveform_type = FAL_RX_PTP_STATE; - } - - SW_RTN_ON_ERROR(qca808x_ptp_freq_waveform_period_0_reg_get(dev_id, - phy_id, &ptp_freq_waveform_period_0_reg)); - SW_RTN_ON_ERROR(qca808x_ptp_freq_waveform_period_1_reg_get(dev_id, - phy_id, &ptp_freq_waveform_period_1_reg)); - SW_RTN_ON_ERROR(qca808x_ptp_freq_waveform_period_2_reg_get(dev_id, - phy_id, &ptp_freq_waveform_period_2_reg)); - waveform->wave_align_pps_out_en = ptp_freq_waveform_period_0_reg.bf.phase_ali; - waveform->wave_period = ((a_int64_t)ptp_freq_waveform_period_0_reg.bf.wave_period << 32) | - (ptp_freq_waveform_period_1_reg.bf.wave_period << 16) | - ptp_freq_waveform_period_2_reg.bf.wave_period; - - return SW_OK; -} - -sw_error_t -qca808x_phy_ptp_rtc_time_snapshot_enable(a_uint32_t dev_id, - a_uint32_t phy_id, a_bool_t status) -{ - union ptp_rtc_ext_conf_reg_u ptp_rtc_ext_conf_reg= {0}; - - SW_RTN_ON_ERROR(qca808x_ptp_rtc_ext_conf_reg_get(dev_id, phy_id, &ptp_rtc_ext_conf_reg)); - ptp_rtc_ext_conf_reg.bf.rtc_read_mode = status; - if (status == A_TRUE) - { - ptp_rtc_ext_conf_reg.bf.rtc_snapshot = PTP_REG_BIT_TRUE; - } - - SW_RTN_ON_ERROR(qca808x_ptp_rtc_ext_conf_reg_set(dev_id, phy_id, &ptp_rtc_ext_conf_reg)); - - return SW_OK; -} - -sw_error_t -qca808x_phy_ptp_rtc_time_snapshot_status_get(a_uint32_t dev_id, - a_uint32_t phy_id, a_bool_t *status) -{ - union ptp_rtc_ext_conf_reg_u ptp_rtc_ext_conf_reg= {0}; - - SW_RTN_ON_ERROR(qca808x_ptp_rtc_ext_conf_reg_get(dev_id, phy_id, &ptp_rtc_ext_conf_reg)); - *status = ptp_rtc_ext_conf_reg.bf.rtc_read_mode; - - return SW_OK; -} - -sw_error_t -qca808x_phy_ptp_increment_sync_from_clock_enable(a_uint32_t dev_id, - a_uint32_t phy_id, a_bool_t status) -{ - union ptp_rtc_ext_conf_reg_u ptp_rtc_ext_conf_reg = {0}; - - SW_RTN_ON_ERROR(qca808x_ptp_rtc_ext_conf_reg_get(dev_id, phy_id, &ptp_rtc_ext_conf_reg)); - ptp_rtc_ext_conf_reg.bf.set_incval_mode = status; - if (status == A_TRUE) - { - ptp_rtc_ext_conf_reg.bf.set_incval_valid = PTP_REG_BIT_TRUE; - } - SW_RTN_ON_ERROR(qca808x_ptp_rtc_ext_conf_reg_set(dev_id, phy_id, &ptp_rtc_ext_conf_reg)); - - return SW_OK; -} - -sw_error_t -qca808x_phy_ptp_increment_sync_from_clock_status_get(a_uint32_t dev_id, - a_uint32_t phy_id, a_bool_t *status) -{ - union ptp_rtc_ext_conf_reg_u ptp_rtc_ext_conf_reg = {0}; - - SW_RTN_ON_ERROR(qca808x_ptp_rtc_ext_conf_reg_get(dev_id, phy_id, &ptp_rtc_ext_conf_reg)); - *status = ptp_rtc_ext_conf_reg.bf.set_incval_mode; - - return SW_OK; -} - -sw_error_t -qca808x_phy_ptp_tod_uart_set(a_uint32_t dev_id, - a_uint32_t phy_id, fal_ptp_tod_uart_t *tod_uart) -{ - union ptp_baud_config_reg_u ptp_baud_config_reg = {0}; - union ptp_uart_configuration_reg_u ptp_uart_configuration_reg = {0}; - union ptp_reset_buffer_reg_u ptp_reset_buffer_reg = {0}; - union ptp_tx_buffer_write_reg_u ptp_tx_buffer_write_reg = {0}; - - SW_RTN_ON_ERROR(qca808x_ptp_baud_config_reg_get(dev_id, phy_id, &ptp_baud_config_reg)); - ptp_baud_config_reg.bf.baud_rate = tod_uart->baud_config; - SW_RTN_ON_ERROR(qca808x_ptp_baud_config_reg_set(dev_id, phy_id, &ptp_baud_config_reg)); - - SW_RTN_ON_ERROR(qca808x_ptp_uart_configuration_reg_get(dev_id, - phy_id, &ptp_uart_configuration_reg)); - ptp_uart_configuration_reg.bf.start_polarity = tod_uart->uart_config_bmp & 0x1; - ptp_uart_configuration_reg.bf.msb_first = - (tod_uart->uart_config_bmp >> PTP_UART_CONFIGURATION_REG_MSB_FIRST_OFFSET) & 0x1; - ptp_uart_configuration_reg.bf.parity_en = - (tod_uart->uart_config_bmp >> PTP_UART_CONFIGURATION_REG_PARITY_EN_OFFSET) & 0x1; - ptp_uart_configuration_reg.bf.auto_tod_out_en = - (tod_uart->uart_config_bmp >> PTP_UART_CONFIGURATION_REG_AUTO_TOD_OUT_EN_OFFSET) & 0x1; - ptp_uart_configuration_reg.bf.auto_tod_in_en = - (tod_uart->uart_config_bmp >> PTP_UART_CONFIGURATION_REG_AUTO_TOD_IN_EN_OFFSET) & 0x1; - - SW_RTN_ON_ERROR(qca808x_ptp_uart_configuration_reg_set(dev_id, - phy_id, &ptp_uart_configuration_reg)); - - SW_RTN_ON_ERROR(qca808x_ptp_reset_buffer_reg_get(dev_id, phy_id, &ptp_reset_buffer_reg)); - ptp_reset_buffer_reg.bf.reset = tod_uart->reset_buf_en; - SW_RTN_ON_ERROR(qca808x_ptp_reset_buffer_reg_set(dev_id, phy_id, &ptp_reset_buffer_reg)); - - SW_RTN_ON_ERROR(qca808x_ptp_tx_buffer_write_reg_get(dev_id, - phy_id, &ptp_tx_buffer_write_reg)); - ptp_tx_buffer_write_reg.bf.tx_buffer = tod_uart->tx_buf_value; - SW_RTN_ON_ERROR(qca808x_ptp_tx_buffer_write_reg_set(dev_id, - phy_id, &ptp_tx_buffer_write_reg)); - - return SW_OK; -} - -sw_error_t -qca808x_phy_ptp_tod_uart_get(a_uint32_t dev_id, - a_uint32_t phy_id, fal_ptp_tod_uart_t *tod_uart) -{ - union ptp_baud_config_reg_u ptp_baud_config_reg = {0}; - union ptp_uart_configuration_reg_u ptp_uart_configuration_reg = {0}; - union ptp_buffer_status_reg_u ptp_buffer_status_reg = {0}; - union ptp_tx_buffer_write_reg_u ptp_tx_buffer_write_reg = {0}; - union ptp_rx_buffer_read_reg_u ptp_rx_buffer_read_reg = {0}; - - SW_RTN_ON_ERROR(qca808x_ptp_baud_config_reg_get(dev_id, phy_id, &ptp_baud_config_reg)); - tod_uart->baud_config = ptp_baud_config_reg.bf.baud_rate; - - SW_RTN_ON_ERROR(qca808x_ptp_uart_configuration_reg_get(dev_id, - phy_id, &ptp_uart_configuration_reg)); - tod_uart->uart_config_bmp = ptp_uart_configuration_reg.bf.start_polarity | - (ptp_uart_configuration_reg.bf.msb_first << - PTP_UART_CONFIGURATION_REG_MSB_FIRST_OFFSET) | - (ptp_uart_configuration_reg.bf.parity_en << - PTP_UART_CONFIGURATION_REG_PARITY_EN_OFFSET) | - (ptp_uart_configuration_reg.bf.auto_tod_out_en << - PTP_UART_CONFIGURATION_REG_AUTO_TOD_OUT_EN_OFFSET) | - (ptp_uart_configuration_reg.bf.auto_tod_in_en << - PTP_UART_CONFIGURATION_REG_AUTO_TOD_IN_EN_OFFSET); - - /* reset buffer is self clearing, always read as 0 */ - tod_uart->reset_buf_en = 0; - - SW_RTN_ON_ERROR(qca808x_ptp_buffer_status_reg_get(dev_id, phy_id, &ptp_buffer_status_reg)); - tod_uart->buf_status_bmp = ptp_buffer_status_reg.bf.tx_buffer_almost_empty | - (ptp_buffer_status_reg.bf.tx_buffer_almost_full << - PTP_BUFFER_STATUS_REG_TX_BUFFER_ALMOST_FULL_OFFSET) | - (ptp_buffer_status_reg.bf.tx_buffer_half_full << - PTP_BUFFER_STATUS_REG_TX_BUFFER_HALF_FULL_OFFSET) | - (ptp_buffer_status_reg.bf.tx_buffer_full << - PTP_BUFFER_STATUS_REG_TX_BUFFER_FULL_OFFSET) | - (ptp_buffer_status_reg.bf.rx_buffer_almost_empty << - PTP_BUFFER_STATUS_REG_RX_BUFFER_ALMOST_EMPTY_OFFSET) | - (ptp_buffer_status_reg.bf.rx_buffer_almost_full << - PTP_BUFFER_STATUS_REG_RX_BUFFER_ALMOST_FULL_OFFSET) | - (ptp_buffer_status_reg.bf.rx_buffer_half_full << - PTP_BUFFER_STATUS_REG_RX_BUFFER_HALF_FULL_OFFSET) | - (ptp_buffer_status_reg.bf.rx_buffer_full << - PTP_BUFFER_STATUS_REG_RX_BUFFER_FULL_OFFSET) | - (ptp_buffer_status_reg.bf.rx_buffer_data_present << - PTP_BUFFER_STATUS_REG_RX_BUFFER_DATA_PRESENT_OFFSET); - - - SW_RTN_ON_ERROR(qca808x_ptp_tx_buffer_write_reg_get(dev_id, - phy_id, &ptp_tx_buffer_write_reg)); - tod_uart->tx_buf_value = ptp_tx_buffer_write_reg.bf.tx_buffer; - - SW_RTN_ON_ERROR(qca808x_ptp_rx_buffer_read_reg_get(dev_id, - phy_id, &ptp_rx_buffer_read_reg)); - tod_uart->rx_buf_value = ptp_rx_buffer_read_reg.bf.rx_data; - - return SW_OK; -} - -sw_error_t -_qca808x_phy_ptp_enhanced_timestamp_engine_rx_set(a_uint32_t dev_id, - a_uint32_t phy_id, fal_ptp_enhanced_ts_engine_t *ts_engine) -{ - union ptp_rx_com_ts_ctrl_reg_u ptp_rx_com_ts_ctrl_reg = {0}; - union ptp_rx_filt_mac_da0_reg_u ptp_rx_filt_mac_da0_reg = {0}; - union ptp_rx_filt_mac_da1_reg_u ptp_rx_filt_mac_da1_reg = {0}; - union ptp_rx_filt_mac_da2_reg_u ptp_rx_filt_mac_da2_reg = {0}; - union ptp_rx_filt_ipv4_da0_reg_u ptp_rx_filt_ipv4_da0_reg = {0}; - union ptp_rx_filt_ipv4_da1_reg_u ptp_rx_filt_ipv4_da1_reg = {0}; - union ptp_rx_filt_ipv6_da0_reg_u ptp_rx_filt_ipv6_da0_reg = {0}; - union ptp_rx_filt_ipv6_da1_reg_u ptp_rx_filt_ipv6_da1_reg = {0}; - union ptp_rx_filt_ipv6_da2_reg_u ptp_rx_filt_ipv6_da2_reg = {0}; - union ptp_rx_filt_ipv6_da3_reg_u ptp_rx_filt_ipv6_da3_reg = {0}; - union ptp_rx_filt_ipv6_da4_reg_u ptp_rx_filt_ipv6_da4_reg = {0}; - union ptp_rx_filt_ipv6_da5_reg_u ptp_rx_filt_ipv6_da5_reg = {0}; - union ptp_rx_filt_ipv6_da6_reg_u ptp_rx_filt_ipv6_da6_reg = {0}; - union ptp_rx_filt_ipv6_da7_reg_u ptp_rx_filt_ipv6_da7_reg = {0}; - union ptp_rx_filt_mac_lengthtype_reg_u ptp_rx_filt_mac_lengthtype_reg = {0}; - union ptp_rx_filt_layer4_protocol_reg_u ptp_rx_filt_layer4_protocol_reg = {0}; - union ptp_rx_filt_udp_port_reg_u ptp_rx_filt_udp_port_reg = {0}; - - union ptp_loc_mac_addr_0_reg_u ptp_loc_mac_addr_0_reg = {0}; - union ptp_loc_mac_addr_1_reg_u ptp_loc_mac_addr_1_reg = {0}; - union ptp_loc_mac_addr_2_reg_u ptp_loc_mac_addr_2_reg = {0}; - - SW_RTN_ON_ERROR(qca808x_ptp_rx_com_ts_ctrl_reg_get(dev_id, - phy_id, &ptp_rx_com_ts_ctrl_reg)); - ptp_rx_com_ts_ctrl_reg.bf.filt_en = ts_engine->filt_en; - ptp_rx_com_ts_ctrl_reg.bf.mac_lengthtype_en = - (ts_engine->enhance_ts_conf_bmp >> (PTP_RX_COM_TS_CTRL_REG_MAC_LENGTHTYPE_EN_OFFSET-1) - ) & PTP_REG_BIT_TRUE; - ptp_rx_com_ts_ctrl_reg.bf.mac_da_en = - (ts_engine->enhance_ts_conf_bmp >> (PTP_RX_COM_TS_CTRL_REG_MAC_DA_EN_OFFSET-1) - ) & PTP_REG_BIT_TRUE; - ptp_rx_com_ts_ctrl_reg.bf.mac_ptp_filt_en = - (ts_engine->enhance_ts_conf_bmp >> (PTP_RX_COM_TS_CTRL_REG_MAC_PTP_FILT_EN_OFFSET-1) - ) & PTP_REG_BIT_TRUE; - ptp_rx_com_ts_ctrl_reg.bf.ipv4_layer4_protocol_en = - (ts_engine->enhance_ts_conf_bmp >> (PTP_RX_COM_TS_CTRL_REG_IPV4_LAYER4_PROTOCOL_EN_OFFSET-1) - ) & PTP_REG_BIT_TRUE; - ptp_rx_com_ts_ctrl_reg.bf.ipv4_da_en = - (ts_engine->enhance_ts_conf_bmp >> (PTP_RX_COM_TS_CTRL_REG_IPV4_DA_EN_OFFSET-1) - ) & PTP_REG_BIT_TRUE; - ptp_rx_com_ts_ctrl_reg.bf.ipv4_ptp_filt_en = - (ts_engine->enhance_ts_conf_bmp >> (PTP_RX_COM_TS_CTRL_REG_IPV4_PTP_FILT_EN_OFFSET-1) - ) & PTP_REG_BIT_TRUE; - ptp_rx_com_ts_ctrl_reg.bf.ipv6_next_header_en = - (ts_engine->enhance_ts_conf_bmp >> (PTP_RX_COM_TS_CTRL_REG_IPV6_NEXT_HEADER_EN_OFFSET-1) - ) & PTP_REG_BIT_TRUE; - ptp_rx_com_ts_ctrl_reg.bf.ipv6_da_filt_en = - (ts_engine->enhance_ts_conf_bmp >> (PTP_RX_COM_TS_CTRL_REG_IPV6_DA_FILT_EN_OFFSET-1) - ) & PTP_REG_BIT_TRUE; - ptp_rx_com_ts_ctrl_reg.bf.ipv6_ptp_filt_en = - (ts_engine->enhance_ts_conf_bmp >> (PTP_RX_COM_TS_CTRL_REG_IPV6_PTP_FILT_EN_OFFSET-1) - ) & PTP_REG_BIT_TRUE; - ptp_rx_com_ts_ctrl_reg.bf.udp_dport_en = - (ts_engine->enhance_ts_conf_bmp >> (PTP_RX_COM_TS_CTRL_REG_UDP_DPORT_EN_OFFSET-1) - ) & PTP_REG_BIT_TRUE; - ptp_rx_com_ts_ctrl_reg.bf.udp_ptp_event_filt_en = - (ts_engine->enhance_ts_conf_bmp >> (PTP_RX_COM_TS_CTRL_REG_UDP_PTP_EVENT_FILT_EN_OFFSET-1) - ) & PTP_REG_BIT_TRUE; - ptp_rx_com_ts_ctrl_reg.bf.y1731_en = - (ts_engine->enhance_ts_conf_bmp >> (PTP_RX_COM_TS_CTRL_REG_Y1731_EN_OFFSET-1) - ) & PTP_REG_BIT_TRUE; - ptp_rx_com_ts_ctrl_reg.bf.y1731_insert_ts_en = - (ts_engine->enhance_ts_conf_bmp >> (PTP_RX_COM_TS_CTRL_REG_Y1731_INSERT_TS_EN_OFFSET-1) - ) & PTP_REG_BIT_TRUE; - ptp_rx_com_ts_ctrl_reg.bf.y1731_da_chk_en = - (ts_engine->enhance_ts_conf_bmp >> (PTP_RX_COM_TS_CTRL_REG_Y1731_DA_CHK_EN_OFFSET-1) - ) & PTP_REG_BIT_TRUE; - SW_RTN_ON_ERROR(qca808x_ptp_rx_com_ts_ctrl_reg_set(dev_id, - phy_id, &ptp_rx_com_ts_ctrl_reg)); - - SW_RTN_ON_ERROR(qca808x_ptp_rx_filt_mac_lengthtype_reg_get(dev_id, - phy_id, &ptp_rx_filt_mac_lengthtype_reg)); - ptp_rx_filt_mac_lengthtype_reg.bf.length_type = ts_engine->eth_type; - SW_RTN_ON_ERROR(qca808x_ptp_rx_filt_mac_lengthtype_reg_set(dev_id, - phy_id, &ptp_rx_filt_mac_lengthtype_reg)); - - SW_RTN_ON_ERROR(qca808x_ptp_rx_filt_mac_da0_reg_get(dev_id, - phy_id, &ptp_rx_filt_mac_da0_reg)); - ptp_rx_filt_mac_da0_reg.bf.mac_addr = (ts_engine->dmac_addr.uc[0] << 8) | - ts_engine->dmac_addr.uc[1]; - SW_RTN_ON_ERROR(qca808x_ptp_rx_filt_mac_da0_reg_set(dev_id, - phy_id, &ptp_rx_filt_mac_da0_reg)); - - SW_RTN_ON_ERROR(qca808x_ptp_rx_filt_mac_da1_reg_get(dev_id, - phy_id, &ptp_rx_filt_mac_da1_reg)); - ptp_rx_filt_mac_da1_reg.bf.mac_addr = (ts_engine->dmac_addr.uc[2] << 8) | - ts_engine->dmac_addr.uc[3]; - SW_RTN_ON_ERROR(qca808x_ptp_rx_filt_mac_da1_reg_set(dev_id, - phy_id, &ptp_rx_filt_mac_da1_reg)); - - SW_RTN_ON_ERROR(qca808x_ptp_rx_filt_mac_da2_reg_get(dev_id, - phy_id, &ptp_rx_filt_mac_da2_reg)); - ptp_rx_filt_mac_da2_reg.bf.mac_addr = (ts_engine->dmac_addr.uc[4] << 8) | - ts_engine->dmac_addr.uc[5]; - SW_RTN_ON_ERROR(qca808x_ptp_rx_filt_mac_da2_reg_set(dev_id, - phy_id, &ptp_rx_filt_mac_da2_reg)); - - SW_RTN_ON_ERROR(qca808x_ptp_rx_filt_layer4_protocol_reg_get(dev_id, - phy_id, &ptp_rx_filt_layer4_protocol_reg)); - ptp_rx_filt_layer4_protocol_reg.bf.l4_protocol = ts_engine->ipv4_l4_proto; - SW_RTN_ON_ERROR(qca808x_ptp_rx_filt_layer4_protocol_reg_set(dev_id, - phy_id, &ptp_rx_filt_layer4_protocol_reg)); - - SW_RTN_ON_ERROR(qca808x_ptp_rx_filt_ipv4_da0_reg_get(dev_id, - phy_id, &ptp_rx_filt_ipv4_da0_reg)); - ptp_rx_filt_ipv4_da0_reg.bf.ip_addr = ts_engine->ipv4_dip >> 16; - SW_RTN_ON_ERROR(qca808x_ptp_rx_filt_ipv4_da0_reg_set(dev_id, - phy_id, &ptp_rx_filt_ipv4_da0_reg)); - - SW_RTN_ON_ERROR(qca808x_ptp_rx_filt_ipv4_da1_reg_get(dev_id, - phy_id, &ptp_rx_filt_ipv4_da1_reg)); - ptp_rx_filt_ipv4_da1_reg.bf.ip_addr = ts_engine->ipv4_dip & 0xffff; - SW_RTN_ON_ERROR(qca808x_ptp_rx_filt_ipv4_da1_reg_set(dev_id, - phy_id, &ptp_rx_filt_ipv4_da1_reg));; - - SW_RTN_ON_ERROR(qca808x_ptp_rx_filt_ipv6_da0_reg_get(dev_id, - phy_id, &ptp_rx_filt_ipv6_da0_reg)); - ptp_rx_filt_ipv6_da0_reg.bf.ip_addr = ts_engine->ipv6_dip.ul[0] >> 16; - SW_RTN_ON_ERROR(qca808x_ptp_rx_filt_ipv6_da0_reg_set(dev_id, - phy_id, &ptp_rx_filt_ipv6_da0_reg)); - - SW_RTN_ON_ERROR(qca808x_ptp_rx_filt_ipv6_da1_reg_get(dev_id, - phy_id, &ptp_rx_filt_ipv6_da1_reg)); - ptp_rx_filt_ipv6_da1_reg.bf.ip_addr = ts_engine->ipv6_dip.ul[0] & 0xffff; - SW_RTN_ON_ERROR(qca808x_ptp_rx_filt_ipv6_da1_reg_set(dev_id, - phy_id, &ptp_rx_filt_ipv6_da1_reg)); - - SW_RTN_ON_ERROR(qca808x_ptp_rx_filt_ipv6_da2_reg_get(dev_id, - phy_id, &ptp_rx_filt_ipv6_da2_reg)); - ptp_rx_filt_ipv6_da2_reg.bf.ip_addr = ts_engine->ipv6_dip.ul[1] >> 16; - SW_RTN_ON_ERROR(qca808x_ptp_rx_filt_ipv6_da2_reg_set(dev_id, - phy_id, &ptp_rx_filt_ipv6_da2_reg)); - - SW_RTN_ON_ERROR(qca808x_ptp_rx_filt_ipv6_da3_reg_get(dev_id, - phy_id, &ptp_rx_filt_ipv6_da3_reg)); - ptp_rx_filt_ipv6_da3_reg.bf.ip_addr = ts_engine->ipv6_dip.ul[1] & 0xffff; - SW_RTN_ON_ERROR(qca808x_ptp_rx_filt_ipv6_da3_reg_set(dev_id, - phy_id, &ptp_rx_filt_ipv6_da3_reg)); - - SW_RTN_ON_ERROR(qca808x_ptp_rx_filt_ipv6_da4_reg_get(dev_id, - phy_id, &ptp_rx_filt_ipv6_da4_reg)); - ptp_rx_filt_ipv6_da4_reg.bf.ip_addr = ts_engine->ipv6_dip.ul[2] >> 16; - SW_RTN_ON_ERROR(qca808x_ptp_rx_filt_ipv6_da4_reg_set(dev_id, - phy_id, &ptp_rx_filt_ipv6_da4_reg)); - - SW_RTN_ON_ERROR(qca808x_ptp_rx_filt_ipv6_da5_reg_get(dev_id, - phy_id, &ptp_rx_filt_ipv6_da5_reg)); - ptp_rx_filt_ipv6_da5_reg.bf.ip_addr = ts_engine->ipv6_dip.ul[2] & 0xffff; - SW_RTN_ON_ERROR(qca808x_ptp_rx_filt_ipv6_da5_reg_set(dev_id, - phy_id, &ptp_rx_filt_ipv6_da5_reg)); - - SW_RTN_ON_ERROR(qca808x_ptp_rx_filt_ipv6_da6_reg_get(dev_id, - phy_id, &ptp_rx_filt_ipv6_da6_reg)); - ptp_rx_filt_ipv6_da6_reg.bf.ip_addr = ts_engine->ipv6_dip.ul[3] >> 16; - SW_RTN_ON_ERROR(qca808x_ptp_rx_filt_ipv6_da6_reg_set(dev_id, - phy_id, &ptp_rx_filt_ipv6_da6_reg)); - - SW_RTN_ON_ERROR(qca808x_ptp_rx_filt_ipv6_da7_reg_get(dev_id, - phy_id, &ptp_rx_filt_ipv6_da7_reg)); - ptp_rx_filt_ipv6_da7_reg.bf.ip_addr = ts_engine->ipv6_dip.ul[3] & 0xffff; - SW_RTN_ON_ERROR(qca808x_ptp_rx_filt_ipv6_da7_reg_set(dev_id, - phy_id, &ptp_rx_filt_ipv6_da7_reg)); - - SW_RTN_ON_ERROR(qca808x_ptp_rx_filt_udp_port_reg_get(dev_id, - phy_id, &ptp_rx_filt_udp_port_reg)); - ptp_rx_filt_udp_port_reg.bf.udp_port = ts_engine->udp_dport; - SW_RTN_ON_ERROR(qca808x_ptp_rx_filt_udp_port_reg_set(dev_id, - phy_id, &ptp_rx_filt_udp_port_reg)); - - SW_RTN_ON_ERROR(qca808x_ptp_loc_mac_addr_0_reg_get(dev_id, - phy_id, &ptp_loc_mac_addr_0_reg)); - ptp_loc_mac_addr_0_reg.bf.mac_addr = (ts_engine->y1731_mac_addr.uc[0] << 8) | - ts_engine->y1731_mac_addr.uc[1]; - SW_RTN_ON_ERROR(qca808x_ptp_loc_mac_addr_0_reg_set(dev_id, - phy_id, &ptp_loc_mac_addr_0_reg)); - - SW_RTN_ON_ERROR(qca808x_ptp_loc_mac_addr_1_reg_get(dev_id, - phy_id, &ptp_loc_mac_addr_1_reg)); - ptp_loc_mac_addr_1_reg.bf.mac_addr = (ts_engine->y1731_mac_addr.uc[2] << 8) | - ts_engine->y1731_mac_addr.uc[3]; - SW_RTN_ON_ERROR(qca808x_ptp_loc_mac_addr_1_reg_set(dev_id, - phy_id, &ptp_loc_mac_addr_1_reg)); - - SW_RTN_ON_ERROR(qca808x_ptp_loc_mac_addr_2_reg_get(dev_id, - phy_id, &ptp_loc_mac_addr_2_reg)); - ptp_loc_mac_addr_2_reg.bf.mac_addr = (ts_engine->y1731_mac_addr.uc[4] << 8) | - ts_engine->y1731_mac_addr.uc[5]; - SW_RTN_ON_ERROR(qca808x_ptp_loc_mac_addr_2_reg_set(dev_id, - phy_id, &ptp_loc_mac_addr_2_reg)); - - return SW_OK; -} - - -sw_error_t -_qca808x_phy_ptp_enhanced_timestamp_engine_tx_set(a_uint32_t dev_id, - a_uint32_t phy_id, fal_ptp_enhanced_ts_engine_t *ts_engine) -{ - union ptp_tx_com_ts_ctrl_reg_u ptp_tx_com_ts_ctrl_reg = {0}; - union ptp_tx_filt_mac_da0_reg_u ptp_tx_filt_mac_da0_reg = {0}; - union ptp_tx_filt_mac_da1_reg_u ptp_tx_filt_mac_da1_reg = {0}; - union ptp_tx_filt_mac_da2_reg_u ptp_tx_filt_mac_da2_reg = {0}; - union ptp_tx_filt_ipv4_da0_reg_u ptp_tx_filt_ipv4_da0_reg = {0}; - union ptp_tx_filt_ipv4_da1_reg_u ptp_tx_filt_ipv4_da1_reg = {0}; - union ptp_tx_filt_ipv6_da0_reg_u ptp_tx_filt_ipv6_da0_reg = {0}; - union ptp_tx_filt_ipv6_da1_reg_u ptp_tx_filt_ipv6_da1_reg = {0}; - union ptp_tx_filt_ipv6_da2_reg_u ptp_tx_filt_ipv6_da2_reg = {0}; - union ptp_tx_filt_ipv6_da3_reg_u ptp_tx_filt_ipv6_da3_reg = {0}; - union ptp_tx_filt_ipv6_da4_reg_u ptp_tx_filt_ipv6_da4_reg = {0}; - union ptp_tx_filt_ipv6_da5_reg_u ptp_tx_filt_ipv6_da5_reg = {0}; - union ptp_tx_filt_ipv6_da6_reg_u ptp_tx_filt_ipv6_da6_reg = {0}; - union ptp_tx_filt_ipv6_da7_reg_u ptp_tx_filt_ipv6_da7_reg = {0}; - union ptp_tx_filt_mac_lengthtype_reg_u ptp_tx_filt_mac_lengthtype_reg = {0}; - union ptp_tx_filt_layer4_protocol_reg_u ptp_tx_filt_layer4_protocol_reg = {0}; - union ptp_tx_filt_udp_port_reg_u ptp_tx_filt_udp_port_reg = {0}; - - union ptp_loc_mac_addr_0_reg_u ptp_loc_mac_addr_0_reg = {0}; - union ptp_loc_mac_addr_1_reg_u ptp_loc_mac_addr_1_reg = {0}; - union ptp_loc_mac_addr_2_reg_u ptp_loc_mac_addr_2_reg = {0}; - - SW_RTN_ON_ERROR(qca808x_ptp_tx_com_ts_ctrl_reg_get(dev_id, - phy_id, &ptp_tx_com_ts_ctrl_reg)); - ptp_tx_com_ts_ctrl_reg.bf.filt_en = ts_engine->filt_en; - ptp_tx_com_ts_ctrl_reg.bf.mac_lengthtype_en = ts_engine->enhance_ts_conf_bmp & - PTP_REG_BIT_TRUE; - ptp_tx_com_ts_ctrl_reg.bf.mac_da_en = - (ts_engine->enhance_ts_conf_bmp >> (PTP_TX_COM_TS_CTRL_REG_MAC_DA_EN_OFFSET-1) - ) & PTP_REG_BIT_TRUE; - ptp_tx_com_ts_ctrl_reg.bf.mac_ptp_filt_en = - (ts_engine->enhance_ts_conf_bmp >> (PTP_TX_COM_TS_CTRL_REG_MAC_PTP_FILT_EN_OFFSET-1) - ) & PTP_REG_BIT_TRUE; - ptp_tx_com_ts_ctrl_reg.bf.ipv4_layer4_protocol_en = - (ts_engine->enhance_ts_conf_bmp >> (PTP_TX_COM_TS_CTRL_REG_IPV4_LAYER4_PROTOCOL_EN_OFFSET-1) - ) & PTP_REG_BIT_TRUE; - ptp_tx_com_ts_ctrl_reg.bf.ipv4_da_en = - (ts_engine->enhance_ts_conf_bmp >> (PTP_TX_COM_TS_CTRL_REG_IPV4_DA_EN_OFFSET-1) - ) & PTP_REG_BIT_TRUE; - ptp_tx_com_ts_ctrl_reg.bf.ipv4_ptp_filt_en = - (ts_engine->enhance_ts_conf_bmp >> (PTP_TX_COM_TS_CTRL_REG_IPV4_PTP_FILT_EN_OFFSET-1) - ) & PTP_REG_BIT_TRUE; - ptp_tx_com_ts_ctrl_reg.bf.ipv6_next_header_en = - (ts_engine->enhance_ts_conf_bmp >> (PTP_TX_COM_TS_CTRL_REG_IPV6_NEXT_HEADER_EN_OFFSET-1) - ) & PTP_REG_BIT_TRUE; - ptp_tx_com_ts_ctrl_reg.bf.ipv6_da_en = - (ts_engine->enhance_ts_conf_bmp >> (PTP_TX_COM_TS_CTRL_REG_IPV6_DA_EN_OFFSET-1) - ) & PTP_REG_BIT_TRUE; - ptp_tx_com_ts_ctrl_reg.bf.ipv6_ptp_filt_en = - (ts_engine->enhance_ts_conf_bmp >> (PTP_TX_COM_TS_CTRL_REG_IPV6_PTP_FILT_EN_OFFSET-1) - ) & PTP_REG_BIT_TRUE; - ptp_tx_com_ts_ctrl_reg.bf.udp_dport_en = - (ts_engine->enhance_ts_conf_bmp >> (PTP_TX_COM_TS_CTRL_REG_UDP_DPORT_EN_OFFSET-1) - ) & PTP_REG_BIT_TRUE; - ptp_tx_com_ts_ctrl_reg.bf.udp_ptp_event_filt_en = - (ts_engine->enhance_ts_conf_bmp >> (PTP_TX_COM_TS_CTRL_REG_UDP_PTP_EVENT_FILT_EN_OFFSET-1) - ) & PTP_REG_BIT_TRUE; - ptp_tx_com_ts_ctrl_reg.bf.y1731_en = - (ts_engine->enhance_ts_conf_bmp >> (PTP_TX_COM_TS_CTRL_REG_Y1731_EN_OFFSET-1) - ) & PTP_REG_BIT_TRUE; - ptp_tx_com_ts_ctrl_reg.bf.y1731_insert_ts_en = - (ts_engine->enhance_ts_conf_bmp >> (PTP_TX_COM_TS_CTRL_REG_Y1731_INSERT_TS_EN_OFFSET-1) - ) & PTP_REG_BIT_TRUE; - ptp_tx_com_ts_ctrl_reg.bf.y1731_sa_chk_en = - (ts_engine->enhance_ts_conf_bmp >> (PTP_TX_COM_TS_CTRL_REG_Y1731_SA_CHK_EN_OFFSET-1) - ) & PTP_REG_BIT_TRUE; - SW_RTN_ON_ERROR(qca808x_ptp_tx_com_ts_ctrl_reg_set(dev_id, - phy_id, &ptp_tx_com_ts_ctrl_reg)); - - SW_RTN_ON_ERROR(qca808x_ptp_tx_filt_mac_lengthtype_reg_get(dev_id, - phy_id, &ptp_tx_filt_mac_lengthtype_reg)); - ptp_tx_filt_mac_lengthtype_reg.bf.length_type = ts_engine->eth_type; - SW_RTN_ON_ERROR(qca808x_ptp_tx_filt_mac_lengthtype_reg_set(dev_id, - phy_id, &ptp_tx_filt_mac_lengthtype_reg)); - - SW_RTN_ON_ERROR(qca808x_ptp_tx_filt_mac_da0_reg_get(dev_id, - phy_id, &ptp_tx_filt_mac_da0_reg)); - ptp_tx_filt_mac_da0_reg.bf.mac_addr = (ts_engine->dmac_addr.uc[0] << 8) | - ts_engine->dmac_addr.uc[1]; - SW_RTN_ON_ERROR(qca808x_ptp_tx_filt_mac_da0_reg_set(dev_id, - phy_id, &ptp_tx_filt_mac_da0_reg)); - - SW_RTN_ON_ERROR(qca808x_ptp_tx_filt_mac_da1_reg_get(dev_id, - phy_id, &ptp_tx_filt_mac_da1_reg)); - ptp_tx_filt_mac_da1_reg.bf.mac_addr = (ts_engine->dmac_addr.uc[2] << 8) | - ts_engine->dmac_addr.uc[3]; - SW_RTN_ON_ERROR(qca808x_ptp_tx_filt_mac_da1_reg_set(dev_id, - phy_id, &ptp_tx_filt_mac_da1_reg)); - - SW_RTN_ON_ERROR(qca808x_ptp_tx_filt_mac_da2_reg_get(dev_id, - phy_id, &ptp_tx_filt_mac_da2_reg)); - ptp_tx_filt_mac_da2_reg.bf.mac_addr = (ts_engine->dmac_addr.uc[4] << 8) | - ts_engine->dmac_addr.uc[5]; - SW_RTN_ON_ERROR(qca808x_ptp_tx_filt_mac_da2_reg_set(dev_id, - phy_id, &ptp_tx_filt_mac_da2_reg)); - - SW_RTN_ON_ERROR(qca808x_ptp_tx_filt_layer4_protocol_reg_get(dev_id, - phy_id, &ptp_tx_filt_layer4_protocol_reg)); - ptp_tx_filt_layer4_protocol_reg.bf.l4_protocol = ts_engine->ipv4_l4_proto; - SW_RTN_ON_ERROR(qca808x_ptp_tx_filt_layer4_protocol_reg_set(dev_id, - phy_id, &ptp_tx_filt_layer4_protocol_reg)); - - SW_RTN_ON_ERROR(qca808x_ptp_tx_filt_ipv4_da0_reg_get(dev_id, - phy_id, &ptp_tx_filt_ipv4_da0_reg)); - ptp_tx_filt_ipv4_da0_reg.bf.ip_addr = ts_engine->ipv4_dip >> 16; - SW_RTN_ON_ERROR(qca808x_ptp_tx_filt_ipv4_da0_reg_set(dev_id, - phy_id, &ptp_tx_filt_ipv4_da0_reg)); - - SW_RTN_ON_ERROR(qca808x_ptp_tx_filt_ipv4_da1_reg_get(dev_id, - phy_id, &ptp_tx_filt_ipv4_da1_reg)); - ptp_tx_filt_ipv4_da1_reg.bf.ip_addr = ts_engine->ipv4_dip & 0xffff; - SW_RTN_ON_ERROR(qca808x_ptp_tx_filt_ipv4_da1_reg_set(dev_id, - phy_id, &ptp_tx_filt_ipv4_da1_reg));; - - SW_RTN_ON_ERROR(qca808x_ptp_tx_filt_ipv6_da0_reg_get(dev_id, - phy_id, &ptp_tx_filt_ipv6_da0_reg)); - ptp_tx_filt_ipv6_da0_reg.bf.ip_addr = ts_engine->ipv6_dip.ul[0] >> 16; - SW_RTN_ON_ERROR(qca808x_ptp_tx_filt_ipv6_da0_reg_set(dev_id, - phy_id, &ptp_tx_filt_ipv6_da0_reg)); - - SW_RTN_ON_ERROR(qca808x_ptp_tx_filt_ipv6_da1_reg_get(dev_id, - phy_id, &ptp_tx_filt_ipv6_da1_reg)); - ptp_tx_filt_ipv6_da1_reg.bf.ip_addr = ts_engine->ipv6_dip.ul[0] & 0xffff; - SW_RTN_ON_ERROR(qca808x_ptp_tx_filt_ipv6_da1_reg_set(dev_id, - phy_id, &ptp_tx_filt_ipv6_da1_reg)); - - SW_RTN_ON_ERROR(qca808x_ptp_tx_filt_ipv6_da2_reg_get(dev_id, - phy_id, &ptp_tx_filt_ipv6_da2_reg)); - ptp_tx_filt_ipv6_da2_reg.bf.ip_addr = ts_engine->ipv6_dip.ul[1] >> 16; - SW_RTN_ON_ERROR(qca808x_ptp_tx_filt_ipv6_da2_reg_set(dev_id, - phy_id, &ptp_tx_filt_ipv6_da2_reg)); - - SW_RTN_ON_ERROR(qca808x_ptp_tx_filt_ipv6_da3_reg_get(dev_id, - phy_id, &ptp_tx_filt_ipv6_da3_reg)); - ptp_tx_filt_ipv6_da3_reg.bf.ip_addr = ts_engine->ipv6_dip.ul[1] & 0xffff; - SW_RTN_ON_ERROR(qca808x_ptp_tx_filt_ipv6_da3_reg_set(dev_id, - phy_id, &ptp_tx_filt_ipv6_da3_reg)); - - SW_RTN_ON_ERROR(qca808x_ptp_tx_filt_ipv6_da4_reg_get(dev_id, - phy_id, &ptp_tx_filt_ipv6_da4_reg)); - ptp_tx_filt_ipv6_da4_reg.bf.ip_addr = ts_engine->ipv6_dip.ul[2] >> 16; - SW_RTN_ON_ERROR(qca808x_ptp_tx_filt_ipv6_da4_reg_set(dev_id, - phy_id, &ptp_tx_filt_ipv6_da4_reg)); - - SW_RTN_ON_ERROR(qca808x_ptp_tx_filt_ipv6_da5_reg_get(dev_id, - phy_id, &ptp_tx_filt_ipv6_da5_reg)); - ptp_tx_filt_ipv6_da5_reg.bf.ip_addr = ts_engine->ipv6_dip.ul[2] & 0xffff; - SW_RTN_ON_ERROR(qca808x_ptp_tx_filt_ipv6_da5_reg_set(dev_id, - phy_id, &ptp_tx_filt_ipv6_da5_reg)); - - SW_RTN_ON_ERROR(qca808x_ptp_tx_filt_ipv6_da6_reg_get(dev_id, - phy_id, &ptp_tx_filt_ipv6_da6_reg)); - ptp_tx_filt_ipv6_da6_reg.bf.ip_addr = ts_engine->ipv6_dip.ul[3] >> 16; - SW_RTN_ON_ERROR(qca808x_ptp_tx_filt_ipv6_da6_reg_set(dev_id, - phy_id, &ptp_tx_filt_ipv6_da6_reg)); - - SW_RTN_ON_ERROR(qca808x_ptp_tx_filt_ipv6_da7_reg_get(dev_id, - phy_id, &ptp_tx_filt_ipv6_da7_reg)); - ptp_tx_filt_ipv6_da7_reg.bf.ip_addr = ts_engine->ipv6_dip.ul[3] & 0xffff; - SW_RTN_ON_ERROR(qca808x_ptp_tx_filt_ipv6_da7_reg_set(dev_id, - phy_id, &ptp_tx_filt_ipv6_da7_reg)); - - SW_RTN_ON_ERROR(qca808x_ptp_tx_filt_udp_port_reg_get(dev_id, - phy_id, &ptp_tx_filt_udp_port_reg)); - ptp_tx_filt_udp_port_reg.bf.udp_port = ts_engine->udp_dport; - SW_RTN_ON_ERROR(qca808x_ptp_tx_filt_udp_port_reg_set(dev_id, - phy_id, &ptp_tx_filt_udp_port_reg)); - - SW_RTN_ON_ERROR(qca808x_ptp_loc_mac_addr_0_reg_get(dev_id, - phy_id, &ptp_loc_mac_addr_0_reg)); - ptp_loc_mac_addr_0_reg.bf.mac_addr = (ts_engine->y1731_mac_addr.uc[0] << 8) | - ts_engine->y1731_mac_addr.uc[1]; - SW_RTN_ON_ERROR(qca808x_ptp_loc_mac_addr_0_reg_set(dev_id, - phy_id, &ptp_loc_mac_addr_0_reg)); - - SW_RTN_ON_ERROR(qca808x_ptp_loc_mac_addr_1_reg_get(dev_id, - phy_id, &ptp_loc_mac_addr_1_reg)); - ptp_loc_mac_addr_1_reg.bf.mac_addr = (ts_engine->y1731_mac_addr.uc[2] << 8) | - ts_engine->y1731_mac_addr.uc[3]; - SW_RTN_ON_ERROR(qca808x_ptp_loc_mac_addr_1_reg_set(dev_id, - phy_id, &ptp_loc_mac_addr_1_reg)); - - SW_RTN_ON_ERROR(qca808x_ptp_loc_mac_addr_2_reg_get(dev_id, - phy_id, &ptp_loc_mac_addr_2_reg)); - ptp_loc_mac_addr_2_reg.bf.mac_addr = (ts_engine->y1731_mac_addr.uc[4] << 8) | - ts_engine->y1731_mac_addr.uc[5]; - SW_RTN_ON_ERROR(qca808x_ptp_loc_mac_addr_2_reg_set(dev_id, - phy_id, &ptp_loc_mac_addr_2_reg)); - - return SW_OK; -} - -sw_error_t -qca808x_phy_ptp_enhanced_timestamp_engine_set(a_uint32_t dev_id, - a_uint32_t phy_id, fal_ptp_direction_t direction, - fal_ptp_enhanced_ts_engine_t *ts_engine) -{ - if (direction == FAL_RX_DIRECTION) - { - return _qca808x_phy_ptp_enhanced_timestamp_engine_rx_set(dev_id, phy_id, ts_engine); - } - else - { - return _qca808x_phy_ptp_enhanced_timestamp_engine_tx_set(dev_id, phy_id, ts_engine); - } - - return SW_BAD_PARAM; -} - -sw_error_t -_qca808x_phy_ptp_enhanced_timestamp_engine_rx_com_ts_get(a_uint32_t dev_id, a_uint32_t phy_id, - fal_ptp_enhanced_ts_engine_t *ts_engine) -{ - sw_error_t ret = SW_OK; - - union ptp_rx_com_timestamp0_reg_u ptp_rx_com_timestamp0_reg = {0}; - union ptp_rx_com_timestamp1_reg_u ptp_rx_com_timestamp1_reg = {0}; - union ptp_rx_com_timestamp2_reg_u ptp_rx_com_timestamp2_reg = {0}; - union ptp_rx_com_timestamp3_reg_u ptp_rx_com_timestamp3_reg = {0}; - union ptp_rx_com_timestamp4_reg_u ptp_rx_com_timestamp4_reg = {0}; - union ptp_rx_com_frac_nano_reg_u ptp_rx_com_frac_nano_reg = {0}; - - SW_RTN_ON_ERROR(qca808x_ptp_rx_com_timestamp0_reg_get(dev_id, - phy_id, &ptp_rx_com_timestamp0_reg)); - SW_RTN_ON_ERROR(qca808x_ptp_rx_com_timestamp1_reg_get(dev_id, - phy_id, &ptp_rx_com_timestamp1_reg)); - SW_RTN_ON_ERROR(qca808x_ptp_rx_com_timestamp2_reg_get(dev_id, - phy_id, &ptp_rx_com_timestamp2_reg)); - ts_engine->timestamp.seconds = - ((a_int64_t)ptp_rx_com_timestamp0_reg.bf.com_ts << 32) | - (ptp_rx_com_timestamp1_reg.bf.com_ts << 16) | ptp_rx_com_timestamp2_reg.bf.com_ts; - - SW_RTN_ON_ERROR(qca808x_ptp_rx_com_timestamp3_reg_get(dev_id, - phy_id, &ptp_rx_com_timestamp3_reg)); - SW_RTN_ON_ERROR(qca808x_ptp_rx_com_timestamp4_reg_get(dev_id, - phy_id, &ptp_rx_com_timestamp4_reg)); - ts_engine->timestamp.nanoseconds = (ptp_rx_com_timestamp3_reg.bf.com_ts << 16) | - ptp_rx_com_timestamp4_reg.bf.com_ts; - - SW_RTN_ON_ERROR(qca808x_ptp_rx_com_frac_nano_reg_get(dev_id, - phy_id, &ptp_rx_com_frac_nano_reg)); - ts_engine->timestamp.fracnanoseconds = ptp_rx_com_frac_nano_reg.bf.frac_nano; - - return ret; -} - -sw_error_t -_qca808x_phy_ptp_enhanced_timestamp_engine_rx_com_ts_pre_get(a_uint32_t dev_id, a_uint32_t phy_id, - fal_ptp_enhanced_ts_engine_t *ts_engine) -{ - sw_error_t ret = SW_OK; - union ptp_rx_com_timestamp_pre0_reg_u ptp_rx_com_timestamp_pre0_reg = {0}; - union ptp_rx_com_timestamp_pre1_reg_u ptp_rx_com_timestamp_pre1_reg = {0}; - union ptp_rx_com_timestamp_pre2_reg_u ptp_rx_com_timestamp_pre2_reg = {0}; - union ptp_rx_com_timestamp_pre3_reg_u ptp_rx_com_timestamp_pre3_reg = {0}; - union ptp_rx_com_timestamp_pre4_reg_u ptp_rx_com_timestamp_pre4_reg = {0}; - union ptp_rx_com_frac_nano_pre_reg_u ptp_rx_com_frac_nano_pre_reg = {0}; - - SW_RTN_ON_ERROR(qca808x_ptp_rx_com_timestamp_pre0_reg_get(dev_id, - phy_id, &ptp_rx_com_timestamp_pre0_reg)); - SW_RTN_ON_ERROR(qca808x_ptp_rx_com_timestamp_pre1_reg_get(dev_id, - phy_id, &ptp_rx_com_timestamp_pre1_reg)); - SW_RTN_ON_ERROR(qca808x_ptp_rx_com_timestamp_pre2_reg_get(dev_id, - phy_id, &ptp_rx_com_timestamp_pre2_reg)); - ts_engine->timestamp_pre.seconds = - ((a_int64_t)ptp_rx_com_timestamp_pre0_reg.bf.com_ts_pre << 32) | - (ptp_rx_com_timestamp_pre1_reg.bf.com_ts_pre << 16) | - ptp_rx_com_timestamp_pre2_reg.bf.com_ts_pre; - - SW_RTN_ON_ERROR(qca808x_ptp_rx_com_timestamp_pre3_reg_get(dev_id, - phy_id, &ptp_rx_com_timestamp_pre3_reg)); - SW_RTN_ON_ERROR(qca808x_ptp_rx_com_timestamp_pre4_reg_get(dev_id, - phy_id, &ptp_rx_com_timestamp_pre4_reg)); - ts_engine->timestamp_pre.nanoseconds = - (ptp_rx_com_timestamp_pre3_reg.bf.com_ts_pre << 16) | - ptp_rx_com_timestamp_pre4_reg.bf.com_ts_pre; - - SW_RTN_ON_ERROR(qca808x_ptp_rx_com_frac_nano_pre_reg_get(dev_id, - phy_id, &ptp_rx_com_frac_nano_pre_reg)); - ts_engine->timestamp_pre.fracnanoseconds = - ptp_rx_com_frac_nano_pre_reg.bf.frac_nano_pre; - - return ret; -} - -sw_error_t -_qca808x_phy_ptp_enhanced_timestamp_engine_rx_get(a_uint32_t dev_id, - a_uint32_t phy_id, fal_ptp_enhanced_ts_engine_t *ts_engine) -{ - sw_error_t ret = SW_OK; - union ptp_rx_com_ts_ctrl_reg_u ctrl_reg = {0}; - union ptp_rx_filt_mac_da0_reg_u ptp_rx_filt_mac_da0_reg = {0}; - union ptp_rx_filt_mac_da1_reg_u ptp_rx_filt_mac_da1_reg = {0}; - union ptp_rx_filt_mac_da2_reg_u ptp_rx_filt_mac_da2_reg = {0}; - union ptp_rx_filt_ipv4_da0_reg_u ptp_rx_filt_ipv4_da0_reg = {0}; - union ptp_rx_filt_ipv4_da1_reg_u ptp_rx_filt_ipv4_da1_reg = {0}; - union ptp_rx_filt_ipv6_da0_reg_u ptp_rx_filt_ipv6_da0_reg = {0}; - union ptp_rx_filt_ipv6_da1_reg_u ptp_rx_filt_ipv6_da1_reg = {0}; - union ptp_rx_filt_ipv6_da2_reg_u ptp_rx_filt_ipv6_da2_reg = {0}; - union ptp_rx_filt_ipv6_da3_reg_u ptp_rx_filt_ipv6_da3_reg = {0}; - union ptp_rx_filt_ipv6_da4_reg_u ptp_rx_filt_ipv6_da4_reg = {0}; - union ptp_rx_filt_ipv6_da5_reg_u ptp_rx_filt_ipv6_da5_reg = {0}; - union ptp_rx_filt_ipv6_da6_reg_u ptp_rx_filt_ipv6_da6_reg = {0}; - union ptp_rx_filt_ipv6_da7_reg_u ptp_rx_filt_ipv6_da7_reg = {0}; - union ptp_rx_filt_mac_lengthtype_reg_u ptp_rx_filt_mac_lengthtype_reg = {0}; - union ptp_rx_filt_layer4_protocol_reg_u ptp_rx_filt_layer4_protocol_reg = {0}; - union ptp_rx_filt_udp_port_reg_u ptp_rx_filt_udp_port_reg = {0}; - union ptp_rx_com_ts_status_reg_u ptp_rx_com_ts_status_reg = {0}; - union ptp_rx_com_ts_status_pre_reg_u ptp_rx_com_ts_status_pre_reg = {0}; - union ptp_rx_y1731_identify_reg_u ptp_rx_y1731_identify_reg = {0}; - union ptp_rx_y1731_identify_pre_reg_u ptp_rx_y1731_identify_pre_reg = {0}; - - union ptp_loc_mac_addr_0_reg_u ptp_loc_mac_addr_0_reg = {0}; - union ptp_loc_mac_addr_1_reg_u ptp_loc_mac_addr_1_reg = {0}; - union ptp_loc_mac_addr_2_reg_u ptp_loc_mac_addr_2_reg = {0}; - - SW_RTN_ON_ERROR(qca808x_ptp_rx_com_ts_ctrl_reg_get(dev_id, - phy_id, &ctrl_reg)); - ts_engine->filt_en = ctrl_reg.bf.filt_en; - ts_engine->enhance_ts_conf_bmp = ctrl_reg.bf.mac_lengthtype_en | - (ctrl_reg.bf.mac_da_en << (PTP_RX_COM_TS_CTRL_REG_MAC_DA_EN_OFFSET-1)) | - (ctrl_reg.bf.mac_ptp_filt_en << (PTP_RX_COM_TS_CTRL_REG_MAC_PTP_FILT_EN_OFFSET-1)) | - (ctrl_reg.bf. - ipv4_layer4_protocol_en << (PTP_RX_COM_TS_CTRL_REG_IPV4_LAYER4_PROTOCOL_EN_OFFSET-1)) | - (ctrl_reg.bf.ipv4_da_en << (PTP_RX_COM_TS_CTRL_REG_IPV4_DA_EN_OFFSET-1)) | - (ctrl_reg.bf.ipv4_ptp_filt_en << (PTP_RX_COM_TS_CTRL_REG_IPV4_PTP_FILT_EN_OFFSET-1)) | - (ctrl_reg.bf.ipv6_next_header_en << (PTP_RX_COM_TS_CTRL_REG_IPV6_NEXT_HEADER_EN_OFFSET-1)) | - (ctrl_reg.bf.ipv6_da_filt_en << (PTP_RX_COM_TS_CTRL_REG_IPV6_DA_FILT_EN_OFFSET-1)) | - (ctrl_reg.bf.ipv6_ptp_filt_en << (PTP_RX_COM_TS_CTRL_REG_IPV6_PTP_FILT_EN_OFFSET-1)) | - (ctrl_reg.bf.udp_dport_en << (PTP_RX_COM_TS_CTRL_REG_UDP_DPORT_EN_OFFSET-1)) | - (ctrl_reg.bf. - udp_ptp_event_filt_en << (PTP_RX_COM_TS_CTRL_REG_UDP_PTP_EVENT_FILT_EN_OFFSET-1)) | - (ctrl_reg.bf.y1731_en << (PTP_RX_COM_TS_CTRL_REG_Y1731_EN_OFFSET-1)) | - (ctrl_reg.bf.y1731_insert_ts_en << (PTP_RX_COM_TS_CTRL_REG_Y1731_INSERT_TS_EN_OFFSET-1)) | - (ctrl_reg.bf.y1731_da_chk_en << (PTP_RX_COM_TS_CTRL_REG_Y1731_DA_CHK_EN_OFFSET-1)); - - SW_RTN_ON_ERROR(qca808x_ptp_rx_filt_mac_lengthtype_reg_get(dev_id, - phy_id, &ptp_rx_filt_mac_lengthtype_reg)); - ts_engine->eth_type = ptp_rx_filt_mac_lengthtype_reg.bf.length_type; - - SW_RTN_ON_ERROR(qca808x_ptp_rx_filt_mac_da0_reg_get(dev_id, - phy_id, &ptp_rx_filt_mac_da0_reg)); - ts_engine->dmac_addr.uc[0] = ptp_rx_filt_mac_da0_reg.bf.mac_addr >> 8; - ts_engine->dmac_addr.uc[1] = ptp_rx_filt_mac_da0_reg.bf.mac_addr & 0xff; - - SW_RTN_ON_ERROR(qca808x_ptp_rx_filt_mac_da1_reg_get(dev_id, - phy_id, &ptp_rx_filt_mac_da1_reg)); - ts_engine->dmac_addr.uc[2] = ptp_rx_filt_mac_da1_reg.bf.mac_addr >> 8; - ts_engine->dmac_addr.uc[3] = ptp_rx_filt_mac_da1_reg.bf.mac_addr & 0xff; - - SW_RTN_ON_ERROR(qca808x_ptp_rx_filt_mac_da2_reg_get(dev_id, - phy_id, &ptp_rx_filt_mac_da2_reg)); - ts_engine->dmac_addr.uc[4] = ptp_rx_filt_mac_da2_reg.bf.mac_addr >> 8; - ts_engine->dmac_addr.uc[5] = ptp_rx_filt_mac_da2_reg.bf.mac_addr & 0xff; - - SW_RTN_ON_ERROR(qca808x_ptp_rx_filt_layer4_protocol_reg_get(dev_id, - phy_id, &ptp_rx_filt_layer4_protocol_reg)); - ts_engine->ipv4_l4_proto = ptp_rx_filt_layer4_protocol_reg.bf.l4_protocol; - - SW_RTN_ON_ERROR(qca808x_ptp_rx_filt_ipv4_da0_reg_get(dev_id, - phy_id, &ptp_rx_filt_ipv4_da0_reg)); - SW_RTN_ON_ERROR(qca808x_ptp_rx_filt_ipv4_da1_reg_get(dev_id, - phy_id, &ptp_rx_filt_ipv4_da1_reg)); - ts_engine->ipv4_dip = (ptp_rx_filt_ipv4_da0_reg.bf.ip_addr << 16) | - ptp_rx_filt_ipv4_da1_reg.bf.ip_addr; - - SW_RTN_ON_ERROR(qca808x_ptp_rx_filt_ipv6_da0_reg_get(dev_id, - phy_id, &ptp_rx_filt_ipv6_da0_reg)); - SW_RTN_ON_ERROR(qca808x_ptp_rx_filt_ipv6_da1_reg_get(dev_id, - phy_id, &ptp_rx_filt_ipv6_da1_reg)); - ts_engine->ipv6_dip.ul[0] = (ptp_rx_filt_ipv6_da0_reg.bf.ip_addr << 16) | - ptp_rx_filt_ipv6_da1_reg.bf.ip_addr; - - SW_RTN_ON_ERROR(qca808x_ptp_rx_filt_ipv6_da2_reg_get(dev_id, - phy_id, &ptp_rx_filt_ipv6_da2_reg)); - SW_RTN_ON_ERROR(qca808x_ptp_rx_filt_ipv6_da3_reg_get(dev_id, - phy_id, &ptp_rx_filt_ipv6_da3_reg)); - ts_engine->ipv6_dip.ul[1] = (ptp_rx_filt_ipv6_da2_reg.bf.ip_addr << 16) | - ptp_rx_filt_ipv6_da3_reg.bf.ip_addr; - - SW_RTN_ON_ERROR(qca808x_ptp_rx_filt_ipv6_da4_reg_get(dev_id, - phy_id, &ptp_rx_filt_ipv6_da4_reg)); - SW_RTN_ON_ERROR(qca808x_ptp_rx_filt_ipv6_da5_reg_get(dev_id, - phy_id, &ptp_rx_filt_ipv6_da5_reg)); - ts_engine->ipv6_dip.ul[2] = (ptp_rx_filt_ipv6_da4_reg.bf.ip_addr << 16) | - ptp_rx_filt_ipv6_da5_reg.bf.ip_addr; - - SW_RTN_ON_ERROR(qca808x_ptp_rx_filt_ipv6_da6_reg_get(dev_id, - phy_id, &ptp_rx_filt_ipv6_da6_reg)); - SW_RTN_ON_ERROR(qca808x_ptp_rx_filt_ipv6_da7_reg_get(dev_id, - phy_id, &ptp_rx_filt_ipv6_da7_reg)); - ts_engine->ipv6_dip.ul[3] = (ptp_rx_filt_ipv6_da6_reg.bf.ip_addr << 16) | - ptp_rx_filt_ipv6_da7_reg.bf.ip_addr; - - SW_RTN_ON_ERROR(qca808x_ptp_rx_filt_udp_port_reg_get(dev_id, - phy_id, &ptp_rx_filt_udp_port_reg)); - ts_engine->udp_dport = ptp_rx_filt_udp_port_reg.bf.udp_port; - - SW_RTN_ON_ERROR(qca808x_ptp_loc_mac_addr_0_reg_get(dev_id, - phy_id, &ptp_loc_mac_addr_0_reg)); - ts_engine->y1731_mac_addr.uc[0] = ptp_loc_mac_addr_0_reg.bf.mac_addr >> 8; - ts_engine->y1731_mac_addr.uc[1] = ptp_loc_mac_addr_0_reg.bf.mac_addr & 0xff; - - SW_RTN_ON_ERROR(qca808x_ptp_loc_mac_addr_1_reg_get(dev_id, - phy_id, &ptp_loc_mac_addr_1_reg)); - ts_engine->y1731_mac_addr.uc[2] = ptp_loc_mac_addr_1_reg.bf.mac_addr >> 8; - ts_engine->y1731_mac_addr.uc[3] = ptp_loc_mac_addr_1_reg.bf.mac_addr & 0xff; - - SW_RTN_ON_ERROR(qca808x_ptp_loc_mac_addr_2_reg_get(dev_id, - phy_id, &ptp_loc_mac_addr_2_reg)); - ts_engine->y1731_mac_addr.uc[4] = ptp_loc_mac_addr_2_reg.bf.mac_addr >> 8; - ts_engine->y1731_mac_addr.uc[5] = ptp_loc_mac_addr_2_reg.bf.mac_addr & 0xff; - - SW_RTN_ON_ERROR(qca808x_ptp_rx_com_ts_status_reg_get(dev_id, - phy_id, &ptp_rx_com_ts_status_reg)); - ts_engine->enhance_ts_status_bmp = ptp_rx_com_ts_status_reg.bf.mac_lengthtype | - (ptp_rx_com_ts_status_reg.bf.mac_da << - PTP_RX_COM_TS_STATUS_REG_MAC_DA_OFFSET) | - (ptp_rx_com_ts_status_reg.bf.mac_ptp_prim_addr << - PTP_RX_COM_TS_STATUS_REG_MAC_PTP_PRIM_ADDR_OFFSET) | - (ptp_rx_com_ts_status_reg.bf.mac_ptp_pdelay_addr << - PTP_RX_COM_TS_STATUS_REG_MAC_PTP_PDELAY_ADDR_OFFSET) | - (ptp_rx_com_ts_status_reg.bf.ipv4_layer4_protocol << - PTP_RX_COM_TS_STATUS_REG_IPV4_LAYER4_PROTOCOL_OFFSET) | - (ptp_rx_com_ts_status_reg.bf.ipv4_da << - PTP_RX_COM_TS_STATUS_REG_IPV4_DA_OFFSET) | - (ptp_rx_com_ts_status_reg.bf.ipv4_ptp_prim_addr << - PTP_RX_COM_TS_STATUS_REG_IPV4_PTP_PRIM_ADDR_OFFSET) | - (ptp_rx_com_ts_status_reg.bf.ipv4_ptp_pdelay_addr << - PTP_RX_COM_TS_STATUS_REG_IPV4_PTP_PDELAY_ADDR_OFFSET) | - (ptp_rx_com_ts_status_reg.bf.ipv6_next_header << - PTP_RX_COM_TS_STATUS_REG_IPV6_NEXT_HEADER_OFFSET) | - (ptp_rx_com_ts_status_reg.bf.ipv6_da << - PTP_RX_COM_TS_STATUS_REG_IPV6_DA_OFFSET) | - (ptp_rx_com_ts_status_reg.bf.ipv6_ptp_prim_addr << - PTP_RX_COM_TS_STATUS_REG_IPV6_PTP_PRIM_ADDR_OFFSET) | - (ptp_rx_com_ts_status_reg.bf.ipv6_ptp_pdelay_addr << - PTP_RX_COM_TS_STATUS_REG_IPV6_PTP_PDELAY_ADDR_OFFSET) | - (ptp_rx_com_ts_status_reg.bf.udp_dport << - PTP_RX_COM_TS_STATUS_REG_UDP_DPORT_OFFSET) | - (ptp_rx_com_ts_status_reg.bf.udp_ptp_event_dport << - PTP_RX_COM_TS_STATUS_REG_UDP_PTP_EVENT_DPORT_OFFSET) | - (ptp_rx_com_ts_status_reg.bf.y1731_mach << - PTP_RX_COM_TS_STATUS_REG_Y1731_MACH_OFFSET); - - SW_RTN_ON_ERROR(qca808x_ptp_rx_com_ts_status_pre_reg_get(dev_id, - phy_id, &ptp_rx_com_ts_status_pre_reg)); - ts_engine->enhance_ts_status_pre_bmp = ptp_rx_com_ts_status_pre_reg.bf.mac_lengthtype | - (ptp_rx_com_ts_status_pre_reg.bf.mac_da << - PTP_RX_COM_TS_STATUS_REG_MAC_DA_OFFSET) | - (ptp_rx_com_ts_status_pre_reg.bf.mac_ptp_prim_addr << - PTP_RX_COM_TS_STATUS_REG_MAC_PTP_PRIM_ADDR_OFFSET) | - (ptp_rx_com_ts_status_pre_reg.bf.mac_ptp_pdelay_addr << - PTP_RX_COM_TS_STATUS_REG_MAC_PTP_PDELAY_ADDR_OFFSET) | - (ptp_rx_com_ts_status_pre_reg.bf.ipv4_layer4_protocol << - PTP_RX_COM_TS_STATUS_REG_IPV4_LAYER4_PROTOCOL_OFFSET) | - (ptp_rx_com_ts_status_pre_reg.bf.ipv4_da << - PTP_RX_COM_TS_STATUS_REG_IPV4_DA_OFFSET) | - (ptp_rx_com_ts_status_pre_reg.bf.ipv4_ptp_prim_addr << - PTP_RX_COM_TS_STATUS_REG_IPV4_PTP_PRIM_ADDR_OFFSET) | - (ptp_rx_com_ts_status_pre_reg.bf.ipv4_ptp_pdelay_addr << - PTP_RX_COM_TS_STATUS_REG_IPV4_PTP_PDELAY_ADDR_OFFSET) | - (ptp_rx_com_ts_status_pre_reg.bf.ipv6_next_header << - PTP_RX_COM_TS_STATUS_REG_IPV6_NEXT_HEADER_OFFSET) | - (ptp_rx_com_ts_status_pre_reg.bf.ipv6_da << - PTP_RX_COM_TS_STATUS_REG_IPV6_DA_OFFSET) | - (ptp_rx_com_ts_status_pre_reg.bf.ipv6_ptp_prim_addr << - PTP_RX_COM_TS_STATUS_REG_IPV6_PTP_PRIM_ADDR_OFFSET) | - (ptp_rx_com_ts_status_pre_reg.bf.ipv6_ptp_pdelay_addr << - PTP_RX_COM_TS_STATUS_REG_IPV6_PTP_PDELAY_ADDR_OFFSET) | - (ptp_rx_com_ts_status_pre_reg.bf.udp_dport << - PTP_RX_COM_TS_STATUS_REG_UDP_DPORT_OFFSET) | - (ptp_rx_com_ts_status_pre_reg.bf.udp_ptp_event_dport << - PTP_RX_COM_TS_STATUS_REG_UDP_PTP_EVENT_DPORT_OFFSET) | - (ptp_rx_com_ts_status_pre_reg.bf.y1731_mach << - PTP_RX_COM_TS_STATUS_REG_Y1731_MACH_OFFSET); - - SW_RTN_ON_ERROR(qca808x_ptp_rx_y1731_identify_reg_get(dev_id, - phy_id, &ptp_rx_y1731_identify_reg)); - ts_engine->y1731_identity = ptp_rx_y1731_identify_reg.bf.identify; - - SW_RTN_ON_ERROR(qca808x_ptp_rx_y1731_identify_pre_reg_get(dev_id, - phy_id, &ptp_rx_y1731_identify_pre_reg)); - ts_engine->y1731_identity_pre = ptp_rx_y1731_identify_pre_reg.bf.identify_pre; - - ret = _qca808x_phy_ptp_enhanced_timestamp_engine_rx_com_ts_get(dev_id, phy_id, - ts_engine); - if (ret != SW_OK) - { - return ret; - } - - ret = _qca808x_phy_ptp_enhanced_timestamp_engine_rx_com_ts_pre_get(dev_id, phy_id, - ts_engine); - - return ret; -} - -sw_error_t -_qca808x_phy_ptp_enhanced_timestamp_engine_tx_get(a_uint32_t dev_id, - a_uint32_t phy_id, fal_ptp_enhanced_ts_engine_t *ts_engine) -{ - union ptp_tx_com_ts_ctrl_reg_u ctrl_reg = {0}; - union ptp_tx_filt_mac_da0_reg_u ptp_tx_filt_mac_da0_reg = {0}; - union ptp_tx_filt_mac_da1_reg_u ptp_tx_filt_mac_da1_reg = {0}; - union ptp_tx_filt_mac_da2_reg_u ptp_tx_filt_mac_da2_reg = {0}; - union ptp_tx_filt_ipv4_da0_reg_u ptp_tx_filt_ipv4_da0_reg = {0}; - union ptp_tx_filt_ipv4_da1_reg_u ptp_tx_filt_ipv4_da1_reg = {0}; - union ptp_tx_filt_ipv6_da0_reg_u ptp_tx_filt_ipv6_da0_reg = {0}; - union ptp_tx_filt_ipv6_da1_reg_u ptp_tx_filt_ipv6_da1_reg = {0}; - union ptp_tx_filt_ipv6_da2_reg_u ptp_tx_filt_ipv6_da2_reg = {0}; - union ptp_tx_filt_ipv6_da3_reg_u ptp_tx_filt_ipv6_da3_reg = {0}; - union ptp_tx_filt_ipv6_da4_reg_u ptp_tx_filt_ipv6_da4_reg = {0}; - union ptp_tx_filt_ipv6_da5_reg_u ptp_tx_filt_ipv6_da5_reg = {0}; - union ptp_tx_filt_ipv6_da6_reg_u ptp_tx_filt_ipv6_da6_reg = {0}; - union ptp_tx_filt_ipv6_da7_reg_u ptp_tx_filt_ipv6_da7_reg = {0}; - union ptp_tx_filt_mac_lengthtype_reg_u ptp_tx_filt_mac_lengthtype_reg = {0}; - union ptp_tx_filt_layer4_protocol_reg_u ptp_tx_filt_layer4_protocol_reg = {0}; - union ptp_tx_filt_udp_port_reg_u ptp_tx_filt_udp_port_reg = {0}; - union ptp_tx_com_ts_status_reg_u ptp_tx_com_ts_status_reg = {0}; - union ptp_tx_com_timestamp0_reg_u ptp_tx_com_timestamp0_reg = {0}; - union ptp_tx_com_timestamp1_reg_u ptp_tx_com_timestamp1_reg = {0}; - union ptp_tx_com_timestamp2_reg_u ptp_tx_com_timestamp2_reg = {0}; - union ptp_tx_com_timestamp3_reg_u ptp_tx_com_timestamp3_reg = {0}; - union ptp_tx_com_timestamp4_reg_u ptp_tx_com_timestamp4_reg = {0}; - union ptp_tx_com_frac_nano_reg_u ptp_tx_com_frac_nano_reg = {0}; - union ptp_tx_y1731_identify_reg_u ptp_tx_y1731_identify_reg = {0}; - - union ptp_loc_mac_addr_0_reg_u ptp_loc_mac_addr_0_reg = {0}; - union ptp_loc_mac_addr_1_reg_u ptp_loc_mac_addr_1_reg = {0}; - union ptp_loc_mac_addr_2_reg_u ptp_loc_mac_addr_2_reg = {0}; - - SW_RTN_ON_ERROR(qca808x_ptp_tx_com_ts_ctrl_reg_get(dev_id, - phy_id, &ctrl_reg)); - ts_engine->filt_en = ctrl_reg.bf.filt_en; - ts_engine->enhance_ts_conf_bmp = ctrl_reg.bf.mac_lengthtype_en | - (ctrl_reg.bf.mac_da_en << (PTP_TX_COM_TS_CTRL_REG_MAC_DA_EN_OFFSET-1)) | - (ctrl_reg.bf.mac_ptp_filt_en << (PTP_TX_COM_TS_CTRL_REG_MAC_PTP_FILT_EN_OFFSET-1)) | - (ctrl_reg.bf. - ipv4_layer4_protocol_en << (PTP_TX_COM_TS_CTRL_REG_IPV4_LAYER4_PROTOCOL_EN_OFFSET-1)) | - (ctrl_reg.bf.ipv4_da_en << (PTP_TX_COM_TS_CTRL_REG_IPV4_DA_EN_OFFSET-1)) | - (ctrl_reg.bf.ipv4_ptp_filt_en << (PTP_TX_COM_TS_CTRL_REG_IPV4_PTP_FILT_EN_OFFSET-1)) | - (ctrl_reg.bf.ipv6_next_header_en << (PTP_TX_COM_TS_CTRL_REG_IPV6_NEXT_HEADER_EN_OFFSET-1)) | - (ctrl_reg.bf.ipv6_da_en << (PTP_TX_COM_TS_CTRL_REG_IPV6_DA_EN_OFFSET-1)) | - (ctrl_reg.bf.ipv6_ptp_filt_en << (PTP_TX_COM_TS_CTRL_REG_IPV6_PTP_FILT_EN_OFFSET-1)) | - (ctrl_reg.bf.udp_dport_en << (PTP_TX_COM_TS_CTRL_REG_UDP_DPORT_EN_OFFSET-1)) | - (ctrl_reg.bf. - udp_ptp_event_filt_en << (PTP_TX_COM_TS_CTRL_REG_UDP_PTP_EVENT_FILT_EN_OFFSET-1)) | - (ctrl_reg.bf.y1731_en << (PTP_TX_COM_TS_CTRL_REG_Y1731_EN_OFFSET-1)) | - (ctrl_reg.bf.y1731_insert_ts_en << (PTP_TX_COM_TS_CTRL_REG_Y1731_INSERT_TS_EN_OFFSET-1)) | - (ctrl_reg.bf.y1731_sa_chk_en << (PTP_TX_COM_TS_CTRL_REG_Y1731_SA_CHK_EN_OFFSET-1)); - - SW_RTN_ON_ERROR(qca808x_ptp_tx_filt_mac_lengthtype_reg_get(dev_id, - phy_id, &ptp_tx_filt_mac_lengthtype_reg)); - ts_engine->eth_type = ptp_tx_filt_mac_lengthtype_reg.bf.length_type; - - SW_RTN_ON_ERROR(qca808x_ptp_tx_filt_mac_da0_reg_get(dev_id, - phy_id, &ptp_tx_filt_mac_da0_reg)); - ts_engine->dmac_addr.uc[0] = ptp_tx_filt_mac_da0_reg.bf.mac_addr >> 8; - ts_engine->dmac_addr.uc[1] = ptp_tx_filt_mac_da0_reg.bf.mac_addr & 0xff; - - SW_RTN_ON_ERROR(qca808x_ptp_tx_filt_mac_da1_reg_get(dev_id, - phy_id, &ptp_tx_filt_mac_da1_reg)); - ts_engine->dmac_addr.uc[2] = ptp_tx_filt_mac_da1_reg.bf.mac_addr >> 8; - ts_engine->dmac_addr.uc[3] = ptp_tx_filt_mac_da1_reg.bf.mac_addr & 0xff; - - SW_RTN_ON_ERROR(qca808x_ptp_tx_filt_mac_da2_reg_get(dev_id, - phy_id, &ptp_tx_filt_mac_da2_reg)); - ts_engine->dmac_addr.uc[4] = ptp_tx_filt_mac_da2_reg.bf.mac_addr >> 8; - ts_engine->dmac_addr.uc[5] = ptp_tx_filt_mac_da2_reg.bf.mac_addr & 0xff; - - SW_RTN_ON_ERROR(qca808x_ptp_tx_filt_layer4_protocol_reg_get(dev_id, - phy_id, &ptp_tx_filt_layer4_protocol_reg)); - ts_engine->ipv4_l4_proto = ptp_tx_filt_layer4_protocol_reg.bf.l4_protocol; - - SW_RTN_ON_ERROR(qca808x_ptp_tx_filt_ipv4_da0_reg_get(dev_id, - phy_id, &ptp_tx_filt_ipv4_da0_reg)); - SW_RTN_ON_ERROR(qca808x_ptp_tx_filt_ipv4_da1_reg_get(dev_id, - phy_id, &ptp_tx_filt_ipv4_da1_reg)); - ts_engine->ipv4_dip = (ptp_tx_filt_ipv4_da0_reg.bf.ip_addr << 16) | - ptp_tx_filt_ipv4_da1_reg.bf.ip_addr; - - SW_RTN_ON_ERROR(qca808x_ptp_tx_filt_ipv6_da0_reg_get(dev_id, - phy_id, &ptp_tx_filt_ipv6_da0_reg)); - SW_RTN_ON_ERROR(qca808x_ptp_tx_filt_ipv6_da1_reg_get(dev_id, - phy_id, &ptp_tx_filt_ipv6_da1_reg)); - ts_engine->ipv6_dip.ul[0] = (ptp_tx_filt_ipv6_da0_reg.bf.ip_addr << 16) | - ptp_tx_filt_ipv6_da1_reg.bf.ip_addr; - - SW_RTN_ON_ERROR(qca808x_ptp_tx_filt_ipv6_da2_reg_get(dev_id, - phy_id, &ptp_tx_filt_ipv6_da2_reg)); - SW_RTN_ON_ERROR(qca808x_ptp_tx_filt_ipv6_da3_reg_get(dev_id, - phy_id, &ptp_tx_filt_ipv6_da3_reg)); - ts_engine->ipv6_dip.ul[1] = (ptp_tx_filt_ipv6_da2_reg.bf.ip_addr << 16) | - ptp_tx_filt_ipv6_da3_reg.bf.ip_addr; - - SW_RTN_ON_ERROR(qca808x_ptp_tx_filt_ipv6_da4_reg_get(dev_id, - phy_id, &ptp_tx_filt_ipv6_da4_reg)); - SW_RTN_ON_ERROR(qca808x_ptp_tx_filt_ipv6_da5_reg_get(dev_id, - phy_id, &ptp_tx_filt_ipv6_da5_reg)); - ts_engine->ipv6_dip.ul[2] = (ptp_tx_filt_ipv6_da4_reg.bf.ip_addr << 16) | - ptp_tx_filt_ipv6_da5_reg.bf.ip_addr; - - SW_RTN_ON_ERROR(qca808x_ptp_tx_filt_ipv6_da6_reg_get(dev_id, - phy_id, &ptp_tx_filt_ipv6_da6_reg)); - SW_RTN_ON_ERROR(qca808x_ptp_tx_filt_ipv6_da7_reg_get(dev_id, - phy_id, &ptp_tx_filt_ipv6_da7_reg)); - ts_engine->ipv6_dip.ul[3] = (ptp_tx_filt_ipv6_da6_reg.bf.ip_addr << 16) | - ptp_tx_filt_ipv6_da7_reg.bf.ip_addr; - - SW_RTN_ON_ERROR(qca808x_ptp_tx_filt_udp_port_reg_get(dev_id, - phy_id, &ptp_tx_filt_udp_port_reg)); - ts_engine->udp_dport = ptp_tx_filt_udp_port_reg.bf.udp_port; - - SW_RTN_ON_ERROR(qca808x_ptp_loc_mac_addr_0_reg_get(dev_id, - phy_id, &ptp_loc_mac_addr_0_reg)); - ts_engine->y1731_mac_addr.uc[0] = ptp_loc_mac_addr_0_reg.bf.mac_addr >> 8; - ts_engine->y1731_mac_addr.uc[1] = ptp_loc_mac_addr_0_reg.bf.mac_addr & 0xff; - - SW_RTN_ON_ERROR(qca808x_ptp_loc_mac_addr_1_reg_get(dev_id, - phy_id, &ptp_loc_mac_addr_1_reg)); - ts_engine->y1731_mac_addr.uc[2] = ptp_loc_mac_addr_1_reg.bf.mac_addr >> 8; - ts_engine->y1731_mac_addr.uc[3] = ptp_loc_mac_addr_1_reg.bf.mac_addr & 0xff; - - SW_RTN_ON_ERROR(qca808x_ptp_loc_mac_addr_2_reg_get(dev_id, - phy_id, &ptp_loc_mac_addr_2_reg)); - ts_engine->y1731_mac_addr.uc[4] = ptp_loc_mac_addr_2_reg.bf.mac_addr >> 8; - ts_engine->y1731_mac_addr.uc[5] = ptp_loc_mac_addr_2_reg.bf.mac_addr & 0xff; - - SW_RTN_ON_ERROR(qca808x_ptp_tx_com_ts_status_reg_get(dev_id, - phy_id, &ptp_tx_com_ts_status_reg)); - ts_engine->enhance_ts_status_bmp = ptp_tx_com_ts_status_reg.bf.mac_lengthtype | - (ptp_tx_com_ts_status_reg.bf.mac_da << - PTP_TX_COM_TS_STATUS_REG_MAC_DA_OFFSET) | - (ptp_tx_com_ts_status_reg.bf.mac_ptp_prim_addr << - PTP_TX_COM_TS_STATUS_REG_MAC_PTP_PRIM_ADDR_OFFSET) | - (ptp_tx_com_ts_status_reg.bf.mac_ptp_pdelay_addr << - PTP_TX_COM_TS_STATUS_REG_MAC_PTP_PDELAY_ADDR_OFFSET) | - (ptp_tx_com_ts_status_reg.bf.ipv4_layer4_protocol << - PTP_TX_COM_TS_STATUS_REG_IPV4_LAYER4_PROTOCOL_OFFSET) | - (ptp_tx_com_ts_status_reg.bf.ipv4_da << - PTP_TX_COM_TS_STATUS_REG_IPV4_DA_OFFSET) | - (ptp_tx_com_ts_status_reg.bf.ipv4_ptp_prim_addr << - PTP_TX_COM_TS_STATUS_REG_IPV4_PTP_PRIM_ADDR_OFFSET) | - (ptp_tx_com_ts_status_reg.bf.ipv4_ptp_pdelay_addr << - PTP_TX_COM_TS_STATUS_REG_IPV4_PTP_PDELAY_ADDR_OFFSET) | - (ptp_tx_com_ts_status_reg.bf.ipv6_next_header << - PTP_TX_COM_TS_STATUS_REG_IPV6_NEXT_HEADER_OFFSET) | - (ptp_tx_com_ts_status_reg.bf.ipv6_da << - PTP_TX_COM_TS_STATUS_REG_IPV6_DA_OFFSET) | - (ptp_tx_com_ts_status_reg.bf.ipv6_ptp_prim_addr << - PTP_TX_COM_TS_STATUS_REG_IPV6_PTP_PRIM_ADDR_OFFSET) | - (ptp_tx_com_ts_status_reg.bf.ipv6_ptp_pdelay_addr << - PTP_TX_COM_TS_STATUS_REG_IPV6_PTP_PDELAY_ADDR_OFFSET) | - (ptp_tx_com_ts_status_reg.bf.udp_dport << - PTP_TX_COM_TS_STATUS_REG_UDP_DPORT_OFFSET) | - (ptp_tx_com_ts_status_reg.bf.udp_ptp_event_dport << - PTP_TX_COM_TS_STATUS_REG_UDP_PTP_EVENT_DPORT_OFFSET) | - (ptp_tx_com_ts_status_reg.bf.y1731_mach << - PTP_TX_COM_TS_STATUS_REG_Y1731_MACH_OFFSET); - - ts_engine->enhance_ts_status_pre_bmp = 0; - - SW_RTN_ON_ERROR(qca808x_ptp_tx_y1731_identify_reg_get(dev_id, - phy_id, &ptp_tx_y1731_identify_reg)); - ts_engine->y1731_identity = ptp_tx_y1731_identify_reg.bf.identify; - - ts_engine->y1731_identity_pre = 0; - - SW_RTN_ON_ERROR(qca808x_ptp_tx_com_timestamp0_reg_get(dev_id, - phy_id, &ptp_tx_com_timestamp0_reg)); - SW_RTN_ON_ERROR(qca808x_ptp_tx_com_timestamp1_reg_get(dev_id, - phy_id, &ptp_tx_com_timestamp1_reg)); - SW_RTN_ON_ERROR(qca808x_ptp_tx_com_timestamp2_reg_get(dev_id, - phy_id, &ptp_tx_com_timestamp2_reg)); - ts_engine->timestamp.seconds = - ((a_int64_t)ptp_tx_com_timestamp0_reg.bf.com_ts << 32) | - (ptp_tx_com_timestamp1_reg.bf.com_ts << 16) | - ptp_tx_com_timestamp2_reg.bf.com_ts; - - SW_RTN_ON_ERROR(qca808x_ptp_tx_com_timestamp3_reg_get(dev_id, - phy_id, &ptp_tx_com_timestamp3_reg)); - SW_RTN_ON_ERROR(qca808x_ptp_tx_com_timestamp4_reg_get(dev_id, - phy_id, &ptp_tx_com_timestamp4_reg)); - ts_engine->timestamp.nanoseconds = (ptp_tx_com_timestamp3_reg.bf.com_ts << 16) | - ptp_tx_com_timestamp4_reg.bf.com_ts; - - SW_RTN_ON_ERROR(qca808x_ptp_tx_com_frac_nano_reg_get(dev_id, - phy_id, &ptp_tx_com_frac_nano_reg)); - ts_engine->timestamp.fracnanoseconds = ptp_tx_com_frac_nano_reg.bf.frac_nano; - - ts_engine->timestamp_pre.seconds = 0; - ts_engine->timestamp_pre.nanoseconds = 0; - ts_engine->timestamp_pre.fracnanoseconds = 0; - - return SW_OK; -} - -sw_error_t -qca808x_phy_ptp_enhanced_timestamp_engine_get(a_uint32_t dev_id, - a_uint32_t phy_id, fal_ptp_direction_t direction, - fal_ptp_enhanced_ts_engine_t *ts_engine) -{ - if (direction == FAL_RX_DIRECTION) - { - return _qca808x_phy_ptp_enhanced_timestamp_engine_rx_get(dev_id, - phy_id, ts_engine); - } - else - { - return _qca808x_phy_ptp_enhanced_timestamp_engine_tx_get(dev_id, - phy_id, ts_engine); - } - - return SW_BAD_PARAM; -} - -sw_error_t -qca808x_phy_ptp_trigger_set(a_uint32_t dev_id, - a_uint32_t phy_id, a_uint32_t trigger_id, - fal_ptp_trigger_t *triger) -{ - union ptp_trigger0_config_reg_u ptp_trigger0_config_reg = {0}; - union ptp_trigger1_config_reg_u ptp_trigger1_config_reg = {0}; - union ptp_trigger0_timestamp0_reg_u ptp_trigger0_timestamp0_reg = {0}; - union ptp_trigger0_timestamp1_reg_u ptp_trigger0_timestamp1_reg = {0}; - union ptp_trigger0_timestamp2_reg_u ptp_trigger0_timestamp2_reg = {0}; - union ptp_trigger0_timestamp3_reg_u ptp_trigger0_timestamp3_reg = {0}; - union ptp_trigger0_timestamp4_reg_u ptp_trigger0_timestamp4_reg = {0}; - union ptp_trigger1_timestamp0_reg_u ptp_trigger1_timestamp0_reg = {0}; - union ptp_trigger1_timestamp1_reg_u ptp_trigger1_timestamp1_reg = {0}; - union ptp_trigger1_timestamp2_reg_u ptp_trigger1_timestamp2_reg = {0}; - union ptp_trigger1_timestamp3_reg_u ptp_trigger1_timestamp3_reg = {0}; - union ptp_trigger1_timestamp4_reg_u ptp_trigger1_timestamp4_reg = {0}; - - if (trigger_id == 0) - { - SW_RTN_ON_ERROR(qca808x_ptp_trigger0_config_reg_get(dev_id, - phy_id, &ptp_trigger0_config_reg)); - ptp_trigger0_config_reg.bf.status = triger->trigger_conf.trigger_en; - ptp_trigger0_config_reg.bf.force_en = triger->trigger_conf.output_force_en; - ptp_trigger0_config_reg.bf.force_value = triger->trigger_conf.output_force_value; - ptp_trigger0_config_reg.bf.pattern = triger->trigger_conf.patten_select; - ptp_trigger0_config_reg.bf.if_late = triger->trigger_conf.late_operation; - ptp_trigger0_config_reg.bf.notify = triger->trigger_conf.notify; - ptp_trigger0_config_reg.bf.setting = triger->trigger_conf.trigger_effect; - SW_RTN_ON_ERROR(qca808x_ptp_trigger0_config_reg_set(dev_id, - phy_id, &ptp_trigger0_config_reg)); - - ptp_trigger0_timestamp0_reg.bf.ts_sec = - (triger->trigger_conf.tim.seconds >> 32) & 0xffff; - ptp_trigger0_timestamp1_reg.bf.ts_sec = - (triger->trigger_conf.tim.seconds >> 16) & 0xffff; - ptp_trigger0_timestamp2_reg.bf.ts_sec = - triger->trigger_conf.tim.seconds & 0xffff; - ptp_trigger0_timestamp3_reg.bf.ts_nsec = - triger->trigger_conf.tim.nanoseconds >> 16; - ptp_trigger0_timestamp4_reg.bf.ts_nsec = - triger->trigger_conf.tim.nanoseconds & 0xffff; - SW_RTN_ON_ERROR(qca808x_ptp_trigger0_timestamp0_reg_set(dev_id, - phy_id, &ptp_trigger0_timestamp0_reg)); - SW_RTN_ON_ERROR(qca808x_ptp_trigger0_timestamp1_reg_set(dev_id, - phy_id, &ptp_trigger0_timestamp1_reg)); - SW_RTN_ON_ERROR(qca808x_ptp_trigger0_timestamp2_reg_set(dev_id, - phy_id, &ptp_trigger0_timestamp2_reg)); - SW_RTN_ON_ERROR(qca808x_ptp_trigger0_timestamp3_reg_set(dev_id, - phy_id, &ptp_trigger0_timestamp3_reg)); - SW_RTN_ON_ERROR(qca808x_ptp_trigger0_timestamp4_reg_set(dev_id, - phy_id, &ptp_trigger0_timestamp4_reg)); - } else { - SW_RTN_ON_ERROR(qca808x_ptp_trigger1_config_reg_get(dev_id, - phy_id, &ptp_trigger1_config_reg)); - ptp_trigger1_config_reg.bf.status = triger->trigger_conf.trigger_en; - ptp_trigger1_config_reg.bf.force_en = triger->trigger_conf.output_force_en; - ptp_trigger1_config_reg.bf.force_value = triger->trigger_conf.output_force_value; - ptp_trigger1_config_reg.bf.pattern = triger->trigger_conf.patten_select; - ptp_trigger1_config_reg.bf.if_late = triger->trigger_conf.late_operation; - ptp_trigger1_config_reg.bf.notify = triger->trigger_conf.notify; - ptp_trigger1_config_reg.bf.setting = triger->trigger_conf.trigger_effect; - SW_RTN_ON_ERROR(qca808x_ptp_trigger1_config_reg_set(dev_id, - phy_id, &ptp_trigger1_config_reg)); - - ptp_trigger1_timestamp0_reg.bf.ts_sec = - (triger->trigger_conf.tim.seconds >> 32) & 0xffff; - ptp_trigger1_timestamp1_reg.bf.ts_sec = - (triger->trigger_conf.tim.seconds >> 16) & 0xffff; - ptp_trigger1_timestamp2_reg.bf.ts_sec = - triger->trigger_conf.tim.seconds & 0xffff; - ptp_trigger1_timestamp3_reg.bf.ts_nsec = - triger->trigger_conf.tim.nanoseconds >> 16; - ptp_trigger1_timestamp4_reg.bf.ts_nsec = - triger->trigger_conf.tim.nanoseconds & 0xffff; - SW_RTN_ON_ERROR(qca808x_ptp_trigger1_timestamp0_reg_set(dev_id, - phy_id, &ptp_trigger1_timestamp0_reg)); - SW_RTN_ON_ERROR(qca808x_ptp_trigger1_timestamp1_reg_set(dev_id, - phy_id, &ptp_trigger1_timestamp1_reg)); - SW_RTN_ON_ERROR(qca808x_ptp_trigger1_timestamp2_reg_set(dev_id, - phy_id, &ptp_trigger1_timestamp2_reg)); - SW_RTN_ON_ERROR(qca808x_ptp_trigger1_timestamp3_reg_set(dev_id, - phy_id, &ptp_trigger1_timestamp3_reg)); - SW_RTN_ON_ERROR(qca808x_ptp_trigger1_timestamp4_reg_set(dev_id, - phy_id, &ptp_trigger1_timestamp4_reg)); - } - - return SW_OK; -} - -sw_error_t -qca808x_phy_ptp_trigger_get(a_uint32_t dev_id, - a_uint32_t phy_id, a_uint32_t trigger_id, - fal_ptp_trigger_t *triger) -{ - union ptp_trigger0_config_reg_u ptp_trigger0_config_reg = {0}; - union ptp_trigger0_status_reg_u ptp_trigger0_status_reg = {0}; - union ptp_trigger1_config_reg_u ptp_trigger1_config_reg = {0}; - union ptp_trigger1_status_reg_u ptp_trigger1_status_reg = {0}; - union ptp_trigger0_timestamp0_reg_u ptp_trigger0_timestamp0_reg = {0}; - union ptp_trigger0_timestamp1_reg_u ptp_trigger0_timestamp1_reg = {0}; - union ptp_trigger0_timestamp2_reg_u ptp_trigger0_timestamp2_reg = {0}; - union ptp_trigger0_timestamp3_reg_u ptp_trigger0_timestamp3_reg = {0}; - union ptp_trigger0_timestamp4_reg_u ptp_trigger0_timestamp4_reg = {0}; - union ptp_trigger1_timestamp0_reg_u ptp_trigger1_timestamp0_reg = {0}; - union ptp_trigger1_timestamp1_reg_u ptp_trigger1_timestamp1_reg = {0}; - union ptp_trigger1_timestamp2_reg_u ptp_trigger1_timestamp2_reg = {0}; - union ptp_trigger1_timestamp3_reg_u ptp_trigger1_timestamp3_reg = {0}; - union ptp_trigger1_timestamp4_reg_u ptp_trigger1_timestamp4_reg = {0}; - - if (trigger_id == 0) - { - SW_RTN_ON_ERROR(qca808x_ptp_trigger0_config_reg_get(dev_id, - phy_id, &ptp_trigger0_config_reg)); - triger->trigger_conf.trigger_en = ptp_trigger0_config_reg.bf.status; - triger->trigger_conf.output_force_en = ptp_trigger0_config_reg.bf.force_en; - triger->trigger_conf.output_force_value = ptp_trigger0_config_reg.bf.force_value; - triger->trigger_conf.patten_select = ptp_trigger0_config_reg.bf.pattern; - triger->trigger_conf.late_operation = ptp_trigger0_config_reg.bf.if_late; - triger->trigger_conf.notify = ptp_trigger0_config_reg.bf.notify; - triger->trigger_conf.trigger_effect = ptp_trigger0_config_reg.bf.setting; - - SW_RTN_ON_ERROR(qca808x_ptp_trigger0_timestamp0_reg_get(dev_id, - phy_id, &ptp_trigger0_timestamp0_reg)); - SW_RTN_ON_ERROR(qca808x_ptp_trigger0_timestamp1_reg_get(dev_id, - phy_id, &ptp_trigger0_timestamp1_reg)); - SW_RTN_ON_ERROR(qca808x_ptp_trigger0_timestamp2_reg_get(dev_id, - phy_id, &ptp_trigger0_timestamp2_reg)); - SW_RTN_ON_ERROR(qca808x_ptp_trigger0_timestamp3_reg_get(dev_id, - phy_id, &ptp_trigger0_timestamp3_reg)); - SW_RTN_ON_ERROR(qca808x_ptp_trigger0_timestamp4_reg_get(dev_id, - phy_id, &ptp_trigger0_timestamp4_reg)); - triger->trigger_conf.tim.seconds = - ((a_int64_t)ptp_trigger0_timestamp0_reg.bf.ts_sec << 32) | - (ptp_trigger0_timestamp1_reg.bf.ts_sec << 16) | - ptp_trigger0_timestamp2_reg.bf.ts_sec; - triger->trigger_conf.tim.nanoseconds = - (ptp_trigger0_timestamp3_reg.bf.ts_nsec << 16) | - ptp_trigger0_timestamp4_reg.bf.ts_nsec; - - SW_RTN_ON_ERROR(qca808x_ptp_trigger0_status_reg_get(dev_id, - phy_id, &ptp_trigger0_status_reg)); - triger->trigger_status.trigger_finished = ptp_trigger0_status_reg.bf.finished; - triger->trigger_status.trigger_active = ptp_trigger0_status_reg.bf.active; - triger->trigger_status.trigger_error = ptp_trigger0_status_reg.bf.error; - } else { - SW_RTN_ON_ERROR(qca808x_ptp_trigger1_config_reg_get(dev_id, - phy_id, &ptp_trigger1_config_reg)); - triger->trigger_conf.trigger_en = ptp_trigger1_config_reg.bf.status; - triger->trigger_conf.output_force_en = ptp_trigger1_config_reg.bf.force_en; - triger->trigger_conf.output_force_value = ptp_trigger1_config_reg.bf.force_value; - triger->trigger_conf.patten_select = ptp_trigger1_config_reg.bf.pattern; - triger->trigger_conf.late_operation = ptp_trigger1_config_reg.bf.if_late; - triger->trigger_conf.notify = ptp_trigger1_config_reg.bf.notify; - triger->trigger_conf.trigger_effect = ptp_trigger1_config_reg.bf.setting; - - SW_RTN_ON_ERROR(qca808x_ptp_trigger1_timestamp0_reg_get(dev_id, - phy_id, &ptp_trigger1_timestamp0_reg)); - SW_RTN_ON_ERROR(qca808x_ptp_trigger1_timestamp1_reg_get(dev_id, - phy_id, &ptp_trigger1_timestamp1_reg)); - SW_RTN_ON_ERROR(qca808x_ptp_trigger1_timestamp2_reg_get(dev_id, - phy_id, &ptp_trigger1_timestamp2_reg)); - SW_RTN_ON_ERROR(qca808x_ptp_trigger1_timestamp3_reg_get(dev_id, - phy_id, &ptp_trigger1_timestamp3_reg)); - SW_RTN_ON_ERROR(qca808x_ptp_trigger1_timestamp4_reg_get(dev_id, - phy_id, &ptp_trigger1_timestamp4_reg)); - triger->trigger_conf.tim.seconds = - ((a_int64_t)ptp_trigger1_timestamp0_reg.bf.ts_sec << 32) | - (ptp_trigger1_timestamp1_reg.bf.ts_sec << 16) | - ptp_trigger1_timestamp2_reg.bf.ts_sec; - triger->trigger_conf.tim.nanoseconds = - (ptp_trigger1_timestamp3_reg.bf.ts_nsec << 16) | - ptp_trigger1_timestamp4_reg.bf.ts_nsec; - - SW_RTN_ON_ERROR(qca808x_ptp_trigger1_status_reg_get(dev_id, - phy_id, &ptp_trigger1_status_reg)); - triger->trigger_status.trigger_finished = ptp_trigger1_status_reg.bf.finished; - triger->trigger_status.trigger_active = ptp_trigger1_status_reg.bf.active; - triger->trigger_status.trigger_error = ptp_trigger1_status_reg.bf.error; - } - - return SW_OK; -} - -sw_error_t -qca808x_phy_ptp_capture_set(a_uint32_t dev_id, - a_uint32_t phy_id, a_uint32_t capture_id, - fal_ptp_capture_t *capture) -{ - union ptp_event0_config_reg_u ptp_event0_config_reg = {0}; - union ptp_event1_config_reg_u ptp_event1_config_reg = {0}; - - if (capture_id == 0) - { - SW_RTN_ON_ERROR(qca808x_ptp_event0_config_reg_get(dev_id, - phy_id, &ptp_event0_config_reg)); - ptp_event0_config_reg.bf.clear_stat = capture->capture_conf.status_clear; - ptp_event0_config_reg.bf.notify = capture->capture_conf.notify_event; - ptp_event0_config_reg.bf.single_cap = capture->capture_conf.single_multi_select; - ptp_event0_config_reg.bf.fall_en = capture->capture_conf.fall_edge_en; - ptp_event0_config_reg.bf.rise_en = capture->capture_conf.rise_edge_en; - SW_RTN_ON_ERROR(qca808x_ptp_event0_config_reg_set(dev_id, - phy_id, &ptp_event0_config_reg)); - } - else - { - SW_RTN_ON_ERROR(qca808x_ptp_event1_config_reg_get(dev_id, - phy_id, &ptp_event1_config_reg)); - ptp_event1_config_reg.bf.clear_stat = capture->capture_conf.status_clear; - ptp_event1_config_reg.bf.notify = capture->capture_conf.notify_event; - ptp_event1_config_reg.bf.single_cap = capture->capture_conf.single_multi_select; - ptp_event1_config_reg.bf.fall_en = capture->capture_conf.fall_edge_en; - ptp_event1_config_reg.bf.rise_en = capture->capture_conf.rise_edge_en; - SW_RTN_ON_ERROR(qca808x_ptp_event1_config_reg_set(dev_id, - phy_id, &ptp_event1_config_reg)); - } - - return SW_OK; -} - -sw_error_t -qca808x_phy_ptp_capture_get(a_uint32_t dev_id, - a_uint32_t phy_id, a_uint32_t capture_id, - fal_ptp_capture_t *capture) -{ - union ptp_event0_config_reg_u ptp_event0_config_reg = {0}; - union ptp_event0_status_reg_u ptp_event0_status_reg = {0}; - union ptp_event1_config_reg_u ptp_event1_config_reg = {0}; - union ptp_event1_status_reg_u ptp_event1_status_reg = {0}; - union ptp_event0_timestamp0_reg_u ptp_event0_timestamp0_reg = {0}; - union ptp_event0_timestamp1_reg_u ptp_event0_timestamp1_reg = {0}; - union ptp_event0_timestamp2_reg_u ptp_event0_timestamp2_reg = {0}; - union ptp_event0_timestamp3_reg_u ptp_event0_timestamp3_reg = {0}; - union ptp_event0_timestamp4_reg_u ptp_event0_timestamp4_reg = {0}; - union ptp_event1_timestamp0_reg_u ptp_event1_timestamp0_reg = {0}; - union ptp_event1_timestamp1_reg_u ptp_event1_timestamp1_reg = {0}; - union ptp_event1_timestamp2_reg_u ptp_event1_timestamp2_reg = {0}; - union ptp_event1_timestamp3_reg_u ptp_event1_timestamp3_reg = {0}; - union ptp_event1_timestamp4_reg_u ptp_event1_timestamp4_reg = {0}; - - if (capture_id == 0) - { - SW_RTN_ON_ERROR(qca808x_ptp_event0_config_reg_get(dev_id, - phy_id, &ptp_event0_config_reg)); - capture->capture_conf.status_clear = ptp_event0_config_reg.bf.clear_stat; - capture->capture_conf.notify_event = ptp_event0_config_reg.bf.notify; - capture->capture_conf.single_multi_select = ptp_event0_config_reg.bf.single_cap; - capture->capture_conf.fall_edge_en = ptp_event0_config_reg.bf.fall_en; - capture->capture_conf.rise_edge_en = ptp_event0_config_reg.bf.rise_en; - - SW_RTN_ON_ERROR(qca808x_ptp_event0_status_reg_get(dev_id, - phy_id, &ptp_event0_status_reg)); - capture->capture_status.event_detected = ptp_event0_status_reg.bf.detected; - capture->capture_status.fall_rise_edge_detected = - ptp_event0_status_reg.bf.dir_detected; - capture->capture_status.single_multi_detected = ptp_event0_status_reg.bf.mul_event; - capture->capture_status.event_missed_cnt = ptp_event0_status_reg.bf.missed_count; - - SW_RTN_ON_ERROR(qca808x_ptp_event0_timestamp0_reg_get(dev_id, - phy_id, &ptp_event0_timestamp0_reg)); - SW_RTN_ON_ERROR(qca808x_ptp_event0_timestamp1_reg_get(dev_id, - phy_id, &ptp_event0_timestamp1_reg)); - SW_RTN_ON_ERROR(qca808x_ptp_event0_timestamp2_reg_get(dev_id, - phy_id, &ptp_event0_timestamp2_reg)); - capture->capture_status.tim.seconds = - ((a_int64_t)ptp_event0_timestamp0_reg.bf.ts_nsec << 32) | - (ptp_event0_timestamp1_reg.bf.ts_nsec << 16) | - ptp_event0_timestamp2_reg.bf.ts_nsec; - SW_RTN_ON_ERROR(qca808x_ptp_event0_timestamp3_reg_get(dev_id, - phy_id, &ptp_event0_timestamp3_reg)); - SW_RTN_ON_ERROR(qca808x_ptp_event0_timestamp4_reg_get(dev_id, - phy_id, &ptp_event0_timestamp4_reg)); - capture->capture_status.tim.nanoseconds = - (ptp_event0_timestamp3_reg.bf.ts_nsec << 16) | - ptp_event0_timestamp4_reg.bf.ts_nsec; - } else { - SW_RTN_ON_ERROR(qca808x_ptp_event1_config_reg_get(dev_id, - phy_id, &ptp_event1_config_reg)); - capture->capture_conf.status_clear = ptp_event1_config_reg.bf.clear_stat; - capture->capture_conf.notify_event = ptp_event1_config_reg.bf.notify; - capture->capture_conf.single_multi_select = ptp_event1_config_reg.bf.single_cap; - capture->capture_conf.fall_edge_en = ptp_event1_config_reg.bf.fall_en; - capture->capture_conf.rise_edge_en = ptp_event1_config_reg.bf.rise_en; - - SW_RTN_ON_ERROR(qca808x_ptp_event1_status_reg_get(dev_id, - phy_id, &ptp_event1_status_reg)); - capture->capture_status.event_detected = ptp_event1_status_reg.bf.detected; - capture->capture_status.fall_rise_edge_detected = - ptp_event1_status_reg.bf.dir_detected; - capture->capture_status.single_multi_detected = ptp_event1_status_reg.bf.mul_event; - capture->capture_status.event_missed_cnt = ptp_event1_status_reg.bf.missed_count; - - SW_RTN_ON_ERROR(qca808x_ptp_event1_timestamp0_reg_get(dev_id, - phy_id, &ptp_event1_timestamp0_reg)); - SW_RTN_ON_ERROR(qca808x_ptp_event1_timestamp1_reg_get(dev_id, - phy_id, &ptp_event1_timestamp1_reg)); - SW_RTN_ON_ERROR(qca808x_ptp_event1_timestamp2_reg_get(dev_id, - phy_id, &ptp_event1_timestamp2_reg)); - capture->capture_status.tim.seconds = - ((a_int64_t)ptp_event1_timestamp0_reg.bf.ts_nsec << 32) | - (ptp_event1_timestamp1_reg.bf.ts_nsec << 16) | - ptp_event1_timestamp2_reg.bf.ts_nsec; - SW_RTN_ON_ERROR(qca808x_ptp_event1_timestamp3_reg_get(dev_id, - phy_id, &ptp_event1_timestamp3_reg)); - SW_RTN_ON_ERROR(qca808x_ptp_event1_timestamp4_reg_get(dev_id, - phy_id, &ptp_event1_timestamp4_reg)); - capture->capture_status.tim.nanoseconds = - (ptp_event1_timestamp3_reg.bf.ts_nsec << 16) | - ptp_event1_timestamp4_reg.bf.ts_nsec; - } - - return SW_OK; -} - -sw_error_t -qca808x_phy_ptp_interrupt_set(a_uint32_t dev_id, - a_uint32_t phy_id, fal_ptp_interrupt_t *interrupt) -{ - union ptp_imr_reg_u ptp_imr_reg = {0}; - union ptp_ext_imr_reg_u ptp_ext_imr_reg = {0}; - - SW_RTN_ON_ERROR(qca808x_ptp_imr_reg_get(dev_id, phy_id, &ptp_imr_reg)); - ptp_imr_reg.bf.mask_bmp &= (~(0x7 << 2)) & 0xffff; - ptp_imr_reg.bf.mask_bmp |= (interrupt->intr_mask & 0x7) << 2; - SW_RTN_ON_ERROR(qca808x_ptp_imr_reg_set(dev_id, phy_id, &ptp_imr_reg)); - - ptp_ext_imr_reg.bf.mask_bmp = interrupt->intr_mask >> 3; - SW_RTN_ON_ERROR(qca808x_ptp_ext_imr_reg_set(dev_id, phy_id, &ptp_ext_imr_reg)); - - return SW_OK; -} - -sw_error_t -qca808x_phy_ptp_interrupt_get(a_uint32_t dev_id, - a_uint32_t phy_id, fal_ptp_interrupt_t *interrupt) -{ - union ptp_imr_reg_u ptp_imr_reg = {0}; - union ptp_isr_reg_u ptp_isr_reg = {0}; - union ptp_ext_imr_reg_u ptp_ext_imr_reg = {0}; - union ptp_ext_isr_reg_u ptp_ext_isr_reg = {0}; - - SW_RTN_ON_ERROR(qca808x_ptp_imr_reg_get(dev_id, phy_id, &ptp_imr_reg)); - SW_RTN_ON_ERROR(qca808x_ptp_ext_imr_reg_get(dev_id, phy_id, &ptp_ext_imr_reg)); - interrupt->intr_mask = ((ptp_imr_reg.bf.mask_bmp >> 2) & 0x7) | - ((ptp_ext_imr_reg.bf.mask_bmp & 0x7ff) << 3); - - SW_RTN_ON_ERROR(qca808x_ptp_isr_reg_get(dev_id, phy_id, &ptp_isr_reg)); - SW_RTN_ON_ERROR(qca808x_ptp_ext_isr_reg_get(dev_id, phy_id, &ptp_ext_isr_reg)); - interrupt->intr_status = ((ptp_isr_reg.bf.status_bmp >> 2) & 0x7) | - ((ptp_ext_isr_reg.bf.status_bmp & 0x7ff) << 3); - - return SW_OK; -} - -void qca808x_phy_ptp_api_ops_init(hsl_phy_ptp_ops_t *ptp_ops) -{ - if (!ptp_ops) { - return; - } - ptp_ops->phy_ptp_security_set = qca808x_phy_ptp_security_set; - ptp_ops->phy_ptp_link_delay_set = qca808x_phy_ptp_link_delay_set; - ptp_ops->phy_ptp_rx_crc_recalc_status_get = qca808x_phy_ptp_rx_crc_recalc_status_get; - ptp_ops->phy_ptp_tod_uart_set = qca808x_phy_ptp_tod_uart_set; - ptp_ops->phy_ptp_pps_signal_control_set = qca808x_phy_ptp_pps_signal_control_set; - ptp_ops->phy_ptp_timestamp_get = qca808x_phy_ptp_timestamp_get; - ptp_ops->phy_ptp_asym_correction_get = qca808x_phy_ptp_asym_correction_get; - ptp_ops->phy_ptp_capture_set = qca808x_phy_ptp_capture_set; - ptp_ops->phy_ptp_rtc_adjfreq_set = qca808x_phy_ptp_rtc_adjfreq_set; - ptp_ops->phy_ptp_asym_correction_set = qca808x_phy_ptp_asym_correction_set; - ptp_ops->phy_ptp_pkt_timestamp_set = qca808x_phy_ptp_pkt_timestamp_set; - ptp_ops->phy_ptp_rtc_time_get = qca808x_phy_ptp_rtc_time_get; - ptp_ops->phy_ptp_rtc_time_set = qca808x_phy_ptp_rtc_time_set; - ptp_ops->phy_ptp_pkt_timestamp_get = qca808x_phy_ptp_pkt_timestamp_get; - ptp_ops->phy_ptp_interrupt_set = qca808x_phy_ptp_interrupt_set; - ptp_ops->phy_ptp_trigger_set = qca808x_phy_ptp_trigger_set; - ptp_ops->phy_ptp_pps_signal_control_get = qca808x_phy_ptp_pps_signal_control_get; - ptp_ops->phy_ptp_capture_get = qca808x_phy_ptp_capture_get; - ptp_ops->phy_ptp_rx_crc_recalc_enable = qca808x_phy_ptp_rx_crc_recalc_enable; - ptp_ops->phy_ptp_security_get = qca808x_phy_ptp_security_get; - ptp_ops->phy_ptp_tod_uart_get = qca808x_phy_ptp_tod_uart_get; - ptp_ops->phy_ptp_rtc_time_clear = qca808x_phy_ptp_rtc_time_clear; - ptp_ops->phy_ptp_reference_clock_set = qca808x_phy_ptp_reference_clock_set; - ptp_ops->phy_ptp_output_waveform_set = qca808x_phy_ptp_output_waveform_set; - ptp_ops->phy_ptp_rx_timestamp_mode_set = qca808x_phy_ptp_rx_timestamp_mode_set; - ptp_ops->phy_ptp_grandmaster_mode_set = qca808x_phy_ptp_grandmaster_mode_set; - ptp_ops->phy_ptp_config_set = qca808x_phy_ptp_config_set; - ptp_ops->phy_ptp_trigger_get = qca808x_phy_ptp_trigger_get; - ptp_ops->phy_ptp_rtc_adjfreq_get = qca808x_phy_ptp_rtc_adjfreq_get; - ptp_ops->phy_ptp_grandmaster_mode_get = qca808x_phy_ptp_grandmaster_mode_get; - ptp_ops->phy_ptp_rx_timestamp_mode_get = qca808x_phy_ptp_rx_timestamp_mode_get; - ptp_ops->phy_ptp_rtc_adjtime_set = qca808x_phy_ptp_rtc_adjtime_set; - ptp_ops->phy_ptp_link_delay_get = qca808x_phy_ptp_link_delay_get; - ptp_ops->phy_ptp_config_get = qca808x_phy_ptp_config_get; - ptp_ops->phy_ptp_output_waveform_get = qca808x_phy_ptp_output_waveform_get; - ptp_ops->phy_ptp_interrupt_get = qca808x_phy_ptp_interrupt_get; - ptp_ops->phy_ptp_rtc_time_snapshot_enable = qca808x_phy_ptp_rtc_time_snapshot_enable; - ptp_ops->phy_ptp_reference_clock_get = qca808x_phy_ptp_reference_clock_get; - ptp_ops->phy_ptp_enhanced_timestamp_engine_set = - qca808x_phy_ptp_enhanced_timestamp_engine_set; - ptp_ops->phy_ptp_rtc_time_snapshot_status_get = - qca808x_phy_ptp_rtc_time_snapshot_status_get; - ptp_ops->phy_ptp_enhanced_timestamp_engine_get = - qca808x_phy_ptp_enhanced_timestamp_engine_get; - ptp_ops->phy_ptp_increment_sync_from_clock_enable = - qca808x_phy_ptp_increment_sync_from_clock_enable; - ptp_ops->phy_ptp_increment_sync_from_clock_status_get = - qca808x_phy_ptp_increment_sync_from_clock_status_get; -} diff --git a/feeds/ipq807x/qca-ssdk/src/src/hsl/phy/qca808x_ptp_api.c b/feeds/ipq807x/qca-ssdk/src/src/hsl/phy/qca808x_ptp_api.c deleted file mode 100755 index e0342e9f6..000000000 --- a/feeds/ipq807x/qca-ssdk/src/src/hsl/phy/qca808x_ptp_api.c +++ /dev/null @@ -1,15319 +0,0 @@ -/* - * Copyright (c) 2018, The Linux Foundation. All rights reserved. - * Permission to use, copy, modify, and/or distribute this software for - * any purpose with or without fee is hereby granted, provided that the - * above copyright notice and this permission notice appear in all copies. - * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES - * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR - * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES - * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN - * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT - * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. - */ - - -/** - * @defgroup - * @{ - */ - -#include "sw.h" -#include "hsl_api.h" -#include "hsl.h" -#include "hsl_phy.h" -#include "ssdk_plat.h" -#include "qca808x_ptp_reg.h" -#include "qca808x_ptp_api.h" -#include "qca808x_phy.h" - - -sw_error_t -qca808x_phy_ptp_reg_read(a_uint32_t dev_id, a_uint32_t phy_id, a_uint32_t reg, a_uint32_t * val) -{ - *val = qca808x_phy_reg_read(dev_id, phy_id, reg); - return SW_OK; -} - -sw_error_t -qca808x_phy_ptp_reg_write(a_uint32_t dev_id, a_uint32_t phy_id, a_uint32_t reg, a_uint32_t val) -{ - return qca808x_phy_reg_write(dev_id, phy_id, reg, (a_uint16_t)val); -} - -sw_error_t -qca808x_phy_ptp_mmd_read(a_uint32_t dev_id, a_uint32_t phy_id, a_uint16_t mmd_num, - a_uint32_t reg, a_uint32_t * val) -{ - *val = qca808x_phy_mmd_read(dev_id, phy_id, mmd_num, (a_uint16_t)reg); - return SW_OK; -} - -sw_error_t -qca808x_phy_ptp_mmd_write(a_uint32_t dev_id, a_uint32_t phy_id, a_uint16_t mmd_num, - a_uint32_t reg, a_uint32_t val) -{ - return qca808x_phy_mmd_write(dev_id, phy_id, mmd_num, (a_uint16_t)reg, (a_uint16_t)val); -} - -sw_error_t -qca808x_ptp_imr_reg_get(a_uint32_t dev_id, a_uint32_t phy_id, union ptp_imr_reg_u *value) -{ - return qca808x_phy_ptp_reg_read( - dev_id, - phy_id, PTP_IMR_REG_ADDRESS, - &value->val); -} - -sw_error_t -qca808x_ptp_imr_reg_set(a_uint32_t dev_id, a_uint32_t phy_id, union ptp_imr_reg_u *value) -{ - return qca808x_phy_ptp_reg_write( - dev_id, - phy_id, PTP_IMR_REG_ADDRESS, - value->val); -} - -sw_error_t -qca808x_ptp_isr_reg_get(a_uint32_t dev_id, a_uint32_t phy_id, union ptp_isr_reg_u *value) -{ - return qca808x_phy_ptp_reg_read( - dev_id, - phy_id, PTP_ISR_REG_ADDRESS, - &value->val); -} - -sw_error_t -qca808x_ptp_isr_reg_set(a_uint32_t dev_id, a_uint32_t phy_id, union ptp_isr_reg_u *value) -{ - return qca808x_phy_ptp_reg_write( - dev_id, - phy_id, PTP_ISR_REG_ADDRESS, - value->val); -} - -sw_error_t -qca808x_ptp_hw_enable_reg_get(a_uint32_t dev_id, a_uint32_t phy_id, - union ptp_hw_enable_reg_u *value) -{ - return qca808x_phy_ptp_mmd_read( - dev_id, - phy_id, QCA808X_PHY_MMD3_NUM, PTP_HW_ENABLE_REG_ADDRESS, - &value->val); -} - -sw_error_t -qca808x_ptp_hw_enable_reg_set(a_uint32_t dev_id, a_uint32_t phy_id, - union ptp_hw_enable_reg_u *value) -{ - return qca808x_phy_ptp_mmd_write( - dev_id, - phy_id, QCA808X_PHY_MMD3_NUM, PTP_HW_ENABLE_REG_ADDRESS, - value->val); -} - -sw_error_t -qca808x_ptp_main_conf_reg_get(a_uint32_t dev_id, a_uint32_t phy_id, - union ptp_main_conf_reg_u *value) -{ - return qca808x_phy_ptp_mmd_read( - dev_id, - phy_id, QCA808X_PHY_MMD3_NUM, PTP_MAIN_CONF_REG_ADDRESS, - &value->val); -} - -sw_error_t -qca808x_ptp_main_conf_reg_set(a_uint32_t dev_id, a_uint32_t phy_id, - union ptp_main_conf_reg_u *value) -{ - return qca808x_phy_ptp_mmd_write( - dev_id, - phy_id, QCA808X_PHY_MMD3_NUM, PTP_MAIN_CONF_REG_ADDRESS, - value->val); -} - -sw_error_t -qca808x_ptp_rx_seqid0_reg_get(a_uint32_t dev_id, a_uint32_t phy_id, - union ptp_rx_seqid0_reg_u *value) -{ - return qca808x_phy_ptp_mmd_read( - dev_id, - phy_id, QCA808X_PHY_MMD3_NUM, PTP_RX_SEQID0_REG_ADDRESS, - &value->val); -} - -sw_error_t -qca808x_ptp_rx_seqid0_reg_set(a_uint32_t dev_id, a_uint32_t phy_id, - union ptp_rx_seqid0_reg_u *value) -{ - return qca808x_phy_ptp_mmd_write( - dev_id, - phy_id, QCA808X_PHY_MMD3_NUM, PTP_RX_SEQID0_REG_ADDRESS, - value->val); -} - -sw_error_t -qca808x_ptp_rx_portid0_0_reg_get(a_uint32_t dev_id, a_uint32_t phy_id, - union ptp_rx_portid0_0_reg_u *value) -{ - return qca808x_phy_ptp_mmd_read( - dev_id, - phy_id, QCA808X_PHY_MMD3_NUM, PTP_RX_PORTID0_0_REG_ADDRESS, - &value->val); -} - -sw_error_t -qca808x_ptp_rx_portid0_0_reg_set(a_uint32_t dev_id, a_uint32_t phy_id, - union ptp_rx_portid0_0_reg_u *value) -{ - return qca808x_phy_ptp_mmd_write( - dev_id, - phy_id, QCA808X_PHY_MMD3_NUM, PTP_RX_PORTID0_0_REG_ADDRESS, - value->val); -} - -sw_error_t -qca808x_ptp_rx_portid0_1_reg_get(a_uint32_t dev_id, a_uint32_t phy_id, - union ptp_rx_portid0_1_reg_u *value) -{ - return qca808x_phy_ptp_mmd_read( - dev_id, - phy_id, QCA808X_PHY_MMD3_NUM, PTP_RX_PORTID0_1_REG_ADDRESS, - &value->val); -} - -sw_error_t -qca808x_ptp_rx_portid0_1_reg_set(a_uint32_t dev_id, a_uint32_t phy_id, - union ptp_rx_portid0_1_reg_u *value) -{ - return qca808x_phy_ptp_mmd_write( - dev_id, - phy_id, QCA808X_PHY_MMD3_NUM, PTP_RX_PORTID0_1_REG_ADDRESS, - value->val); -} - -sw_error_t -qca808x_ptp_rx_portid0_2_reg_get(a_uint32_t dev_id, a_uint32_t phy_id, - union ptp_rx_portid0_2_reg_u *value) -{ - return qca808x_phy_ptp_mmd_read( - dev_id, - phy_id, QCA808X_PHY_MMD3_NUM, PTP_RX_PORTID0_2_REG_ADDRESS, - &value->val); -} - -sw_error_t -qca808x_ptp_rx_portid0_2_reg_set(a_uint32_t dev_id, a_uint32_t phy_id, - union ptp_rx_portid0_2_reg_u *value) -{ - return qca808x_phy_ptp_mmd_write( - dev_id, - phy_id, QCA808X_PHY_MMD3_NUM, PTP_RX_PORTID0_2_REG_ADDRESS, - value->val); -} - -sw_error_t -qca808x_ptp_rx_portid0_3_reg_get(a_uint32_t dev_id, a_uint32_t phy_id, - union ptp_rx_portid0_3_reg_u *value) -{ - return qca808x_phy_ptp_mmd_read( - dev_id, - phy_id, QCA808X_PHY_MMD3_NUM, PTP_RX_PORTID0_3_REG_ADDRESS, - &value->val); -} - -sw_error_t -qca808x_ptp_rx_portid0_3_reg_set(a_uint32_t dev_id, a_uint32_t phy_id, - union ptp_rx_portid0_3_reg_u *value) -{ - return qca808x_phy_ptp_mmd_write( - dev_id, - phy_id, QCA808X_PHY_MMD3_NUM, PTP_RX_PORTID0_3_REG_ADDRESS, - value->val); -} - -sw_error_t -qca808x_ptp_rx_portid0_4_reg_get(a_uint32_t dev_id, a_uint32_t phy_id, - union ptp_rx_portid0_4_reg_u *value) -{ - return qca808x_phy_ptp_mmd_read( - dev_id, - phy_id, QCA808X_PHY_MMD3_NUM, PTP_RX_PORTID0_4_REG_ADDRESS, - &value->val); -} - -sw_error_t -qca808x_ptp_rx_portid0_4_reg_set(a_uint32_t dev_id, a_uint32_t phy_id, - union ptp_rx_portid0_4_reg_u *value) -{ - return qca808x_phy_ptp_mmd_write( - dev_id, - phy_id, QCA808X_PHY_MMD3_NUM, PTP_RX_PORTID0_4_REG_ADDRESS, - value->val); -} - -sw_error_t -qca808x_ptp_rtc_clk_reg_get(a_uint32_t dev_id, a_uint32_t phy_id, - union ptp_rtc_clk_reg_u *value) -{ - return qca808x_phy_ptp_mmd_read( - dev_id, - phy_id, QCA808X_PHY_MMD7_NUM, PTP_RTC_CLK_REG_ADDRESS, - &value->val); -} - -sw_error_t -qca808x_ptp_rtc_clk_reg_set(a_uint32_t dev_id, a_uint32_t phy_id, - union ptp_rtc_clk_reg_u *value) -{ - return qca808x_phy_ptp_mmd_write( - dev_id, - phy_id, QCA808X_PHY_MMD7_NUM, PTP_RTC_CLK_REG_ADDRESS, - value->val); -} - -sw_error_t -qca808x_ptp_rx_ts0_0_reg_get(a_uint32_t dev_id, a_uint32_t phy_id, - union ptp_rx_ts0_0_reg_u *value) -{ - return qca808x_phy_ptp_mmd_read( - dev_id, - phy_id, QCA808X_PHY_MMD3_NUM, PTP_RX_TS0_0_REG_ADDRESS, - &value->val); -} - -sw_error_t -qca808x_ptp_rx_ts0_0_reg_set(a_uint32_t dev_id, a_uint32_t phy_id, - union ptp_rx_ts0_0_reg_u *value) -{ - return qca808x_phy_ptp_mmd_write( - dev_id, - phy_id, QCA808X_PHY_MMD3_NUM, PTP_RX_TS0_0_REG_ADDRESS, - value->val); -} - -sw_error_t -qca808x_ptp_rx_ts0_1_reg_get(a_uint32_t dev_id, a_uint32_t phy_id, - union ptp_rx_ts0_1_reg_u *value) -{ - return qca808x_phy_ptp_mmd_read( - dev_id, - phy_id, QCA808X_PHY_MMD3_NUM, PTP_RX_TS0_1_REG_ADDRESS, - &value->val); -} - -sw_error_t -qca808x_ptp_rx_ts0_1_reg_set(a_uint32_t dev_id, a_uint32_t phy_id, - union ptp_rx_ts0_1_reg_u *value) -{ - return qca808x_phy_ptp_mmd_write( - dev_id, - phy_id, QCA808X_PHY_MMD3_NUM, PTP_RX_TS0_1_REG_ADDRESS, - value->val); -} - -sw_error_t -qca808x_ptp_rx_ts0_2_reg_get(a_uint32_t dev_id, a_uint32_t phy_id, - union ptp_rx_ts0_2_reg_u *value) -{ - return qca808x_phy_ptp_mmd_read( - dev_id, - phy_id, QCA808X_PHY_MMD3_NUM, PTP_RX_TS0_2_REG_ADDRESS, - &value->val); -} - -sw_error_t -qca808x_ptp_rx_ts0_2_reg_set(a_uint32_t dev_id, a_uint32_t phy_id, - union ptp_rx_ts0_2_reg_u *value) -{ - return qca808x_phy_ptp_mmd_write( - dev_id, - phy_id, QCA808X_PHY_MMD3_NUM, PTP_RX_TS0_2_REG_ADDRESS, - value->val); -} - -sw_error_t -qca808x_ptp_rx_ts0_3_reg_get(a_uint32_t dev_id, a_uint32_t phy_id, - union ptp_rx_ts0_3_reg_u *value) -{ - return qca808x_phy_ptp_mmd_read( - dev_id, - phy_id, QCA808X_PHY_MMD3_NUM, PTP_RX_TS0_3_REG_ADDRESS, - &value->val); -} - -sw_error_t -qca808x_ptp_rx_ts0_3_reg_set(a_uint32_t dev_id, a_uint32_t phy_id, - union ptp_rx_ts0_3_reg_u *value) -{ - return qca808x_phy_ptp_mmd_write( - dev_id, - phy_id, QCA808X_PHY_MMD3_NUM, PTP_RX_TS0_3_REG_ADDRESS, - value->val); -} - -sw_error_t -qca808x_ptp_rx_ts0_4_reg_get(a_uint32_t dev_id, a_uint32_t phy_id, - union ptp_rx_ts0_4_reg_u *value) -{ - return qca808x_phy_ptp_mmd_read( - dev_id, - phy_id, QCA808X_PHY_MMD3_NUM, PTP_RX_TS0_4_REG_ADDRESS, - &value->val); -} - -sw_error_t -qca808x_ptp_rx_ts0_4_reg_set(a_uint32_t dev_id, a_uint32_t phy_id, - union ptp_rx_ts0_4_reg_u *value) -{ - return qca808x_phy_ptp_mmd_write( - dev_id, - phy_id, QCA808X_PHY_MMD3_NUM, PTP_RX_TS0_4_REG_ADDRESS, - value->val); -} - -sw_error_t -qca808x_ptp_rx_ts0_5_reg_get(a_uint32_t dev_id, a_uint32_t phy_id, - union ptp_rx_ts0_5_reg_u *value) -{ - return qca808x_phy_ptp_mmd_read( - dev_id, - phy_id, QCA808X_PHY_MMD3_NUM, PTP_RX_TS0_5_REG_ADDRESS, - &value->val); -} - -sw_error_t -qca808x_ptp_rx_ts0_5_reg_set(a_uint32_t dev_id, a_uint32_t phy_id, - union ptp_rx_ts0_5_reg_u *value) -{ - return qca808x_phy_ptp_mmd_write( - dev_id, - phy_id, QCA808X_PHY_MMD3_NUM, PTP_RX_TS0_5_REG_ADDRESS, - value->val); -} - -sw_error_t -qca808x_ptp_rx_ts0_6_reg_get(a_uint32_t dev_id, a_uint32_t phy_id, - union ptp_rx_ts0_6_reg_u *value) -{ - return qca808x_phy_ptp_mmd_read( - dev_id, - phy_id, QCA808X_PHY_MMD3_NUM, PTP_RX_TS0_6_REG_ADDRESS, - &value->val); -} - -sw_error_t -qca808x_ptp_rx_ts0_6_reg_set(a_uint32_t dev_id, a_uint32_t phy_id, - union ptp_rx_ts0_6_reg_u *value) -{ - return qca808x_phy_ptp_mmd_write( - dev_id, - phy_id, QCA808X_PHY_MMD3_NUM, PTP_RX_TS0_6_REG_ADDRESS, - value->val); -} - -sw_error_t -qca808x_ptp_tx_seqid_reg_get(a_uint32_t dev_id, a_uint32_t phy_id, - union ptp_tx_seqid_reg_u *value) -{ - return qca808x_phy_ptp_mmd_read( - dev_id, - phy_id, QCA808X_PHY_MMD3_NUM, PTP_TX_SEQID_REG_ADDRESS, - &value->val); -} - -sw_error_t -qca808x_ptp_tx_seqid_reg_set(a_uint32_t dev_id, a_uint32_t phy_id, - union ptp_tx_seqid_reg_u *value) -{ - return qca808x_phy_ptp_mmd_write( - dev_id, - phy_id, QCA808X_PHY_MMD3_NUM, PTP_TX_SEQID_REG_ADDRESS, - value->val); -} - -sw_error_t -qca808x_ptp_tx_portid0_reg_get(a_uint32_t dev_id, a_uint32_t phy_id, - union ptp_tx_portid0_reg_u *value) -{ - return qca808x_phy_ptp_mmd_read( - dev_id, - phy_id, QCA808X_PHY_MMD3_NUM, PTP_TX_PORTID0_REG_ADDRESS, - &value->val); -} - -sw_error_t -qca808x_ptp_tx_portid0_reg_set(a_uint32_t dev_id, a_uint32_t phy_id, - union ptp_tx_portid0_reg_u *value) -{ - return qca808x_phy_ptp_mmd_write( - dev_id, - phy_id, QCA808X_PHY_MMD3_NUM, PTP_TX_PORTID0_REG_ADDRESS, - value->val); -} - -sw_error_t -qca808x_ptp_tx_portid1_reg_get(a_uint32_t dev_id, a_uint32_t phy_id, - union ptp_tx_portid1_reg_u *value) -{ - return qca808x_phy_ptp_mmd_read( - dev_id, - phy_id, QCA808X_PHY_MMD3_NUM, PTP_TX_PORTID1_REG_ADDRESS, - &value->val); -} - -sw_error_t -qca808x_ptp_tx_portid1_reg_set(a_uint32_t dev_id, a_uint32_t phy_id, - union ptp_tx_portid1_reg_u *value) -{ - return qca808x_phy_ptp_mmd_write( - dev_id, - phy_id, QCA808X_PHY_MMD3_NUM, PTP_TX_PORTID1_REG_ADDRESS, - value->val); -} - -sw_error_t -qca808x_ptp_tx_portid2_reg_get(a_uint32_t dev_id, a_uint32_t phy_id, - union ptp_tx_portid2_reg_u *value) -{ - return qca808x_phy_ptp_mmd_read( - dev_id, - phy_id, QCA808X_PHY_MMD3_NUM, PTP_TX_PORTID2_REG_ADDRESS, - &value->val); -} - -sw_error_t -qca808x_ptp_tx_portid2_reg_set(a_uint32_t dev_id, a_uint32_t phy_id, - union ptp_tx_portid2_reg_u *value) -{ - return qca808x_phy_ptp_mmd_write( - dev_id, - phy_id, QCA808X_PHY_MMD3_NUM, PTP_TX_PORTID2_REG_ADDRESS, - value->val); -} - -sw_error_t -qca808x_ptp_tx_portid3_reg_get(a_uint32_t dev_id, a_uint32_t phy_id, - union ptp_tx_portid3_reg_u *value) -{ - return qca808x_phy_ptp_mmd_read( - dev_id, - phy_id, QCA808X_PHY_MMD3_NUM, PTP_TX_PORTID3_REG_ADDRESS, - &value->val); -} - -sw_error_t -qca808x_ptp_tx_portid3_reg_set(a_uint32_t dev_id, a_uint32_t phy_id, - union ptp_tx_portid3_reg_u *value) -{ - return qca808x_phy_ptp_mmd_write( - dev_id, - phy_id, QCA808X_PHY_MMD3_NUM, PTP_TX_PORTID3_REG_ADDRESS, - value->val); -} - -sw_error_t -qca808x_ptp_tx_portid4_reg_get(a_uint32_t dev_id, a_uint32_t phy_id, - union ptp_tx_portid4_reg_u *value) -{ - return qca808x_phy_ptp_mmd_read( - dev_id, - phy_id, QCA808X_PHY_MMD3_NUM, PTP_TX_PORTID4_REG_ADDRESS, - &value->val); -} - -sw_error_t -qca808x_ptp_tx_portid4_reg_set(a_uint32_t dev_id, a_uint32_t phy_id, - union ptp_tx_portid4_reg_u *value) -{ - return qca808x_phy_ptp_mmd_write( - dev_id, - phy_id, QCA808X_PHY_MMD3_NUM, PTP_TX_PORTID4_REG_ADDRESS, - value->val); -} - -sw_error_t -qca808x_ptp_tx_ts0_reg_get(a_uint32_t dev_id, a_uint32_t phy_id, - union ptp_tx_ts0_reg_u *value) -{ - return qca808x_phy_ptp_mmd_read( - dev_id, - phy_id, QCA808X_PHY_MMD3_NUM, PTP_TX_TS0_REG_ADDRESS, - &value->val); -} - -sw_error_t -qca808x_ptp_tx_ts0_reg_set(a_uint32_t dev_id, a_uint32_t phy_id, - union ptp_tx_ts0_reg_u *value) -{ - return qca808x_phy_ptp_mmd_write( - dev_id, - phy_id, QCA808X_PHY_MMD3_NUM, PTP_TX_TS0_REG_ADDRESS, - value->val); -} - -sw_error_t -qca808x_ptp_tx_ts1_reg_get(a_uint32_t dev_id, a_uint32_t phy_id, - union ptp_tx_ts1_reg_u *value) -{ - return qca808x_phy_ptp_mmd_read( - dev_id, - phy_id, QCA808X_PHY_MMD3_NUM, PTP_TX_TS1_REG_ADDRESS, - &value->val); -} - -sw_error_t -qca808x_ptp_tx_ts1_reg_set(a_uint32_t dev_id, a_uint32_t phy_id, - union ptp_tx_ts1_reg_u *value) -{ - return qca808x_phy_ptp_mmd_write( - dev_id, - phy_id, QCA808X_PHY_MMD3_NUM, PTP_TX_TS1_REG_ADDRESS, - value->val); -} - -sw_error_t -qca808x_ptp_tx_ts2_reg_get(a_uint32_t dev_id, a_uint32_t phy_id, - union ptp_tx_ts2_reg_u *value) -{ - return qca808x_phy_ptp_mmd_read( - dev_id, - phy_id, QCA808X_PHY_MMD3_NUM, PTP_TX_TS2_REG_ADDRESS, - &value->val); -} - -sw_error_t -qca808x_ptp_tx_ts2_reg_set(a_uint32_t dev_id, a_uint32_t phy_id, - union ptp_tx_ts2_reg_u *value) -{ - return qca808x_phy_ptp_mmd_write( - dev_id, - phy_id, QCA808X_PHY_MMD3_NUM, PTP_TX_TS2_REG_ADDRESS, - value->val); -} - -sw_error_t -qca808x_ptp_tx_ts3_reg_get(a_uint32_t dev_id, a_uint32_t phy_id, - union ptp_tx_ts3_reg_u *value) -{ - return qca808x_phy_ptp_mmd_read( - dev_id, - phy_id, QCA808X_PHY_MMD3_NUM, PTP_TX_TS3_REG_ADDRESS, - &value->val); -} - -sw_error_t -qca808x_ptp_tx_ts3_reg_set(a_uint32_t dev_id, a_uint32_t phy_id, - union ptp_tx_ts3_reg_u *value) -{ - return qca808x_phy_ptp_mmd_write( - dev_id, - phy_id, QCA808X_PHY_MMD3_NUM, PTP_TX_TS3_REG_ADDRESS, - value->val); -} - -sw_error_t -qca808x_ptp_tx_ts4_reg_get(a_uint32_t dev_id, a_uint32_t phy_id, - union ptp_tx_ts4_reg_u *value) -{ - return qca808x_phy_ptp_mmd_read( - dev_id, - phy_id, QCA808X_PHY_MMD3_NUM, PTP_TX_TS4_REG_ADDRESS, - &value->val); -} - -sw_error_t -qca808x_ptp_tx_ts4_reg_set(a_uint32_t dev_id, a_uint32_t phy_id, - union ptp_tx_ts4_reg_u *value) -{ - return qca808x_phy_ptp_mmd_write( - dev_id, - phy_id, QCA808X_PHY_MMD3_NUM, PTP_TX_TS4_REG_ADDRESS, - value->val); -} - -sw_error_t -qca808x_ptp_tx_ts5_reg_get(a_uint32_t dev_id, a_uint32_t phy_id, - union ptp_tx_ts5_reg_u *value) -{ - return qca808x_phy_ptp_mmd_read( - dev_id, - phy_id, QCA808X_PHY_MMD3_NUM, PTP_TX_TS5_REG_ADDRESS, - &value->val); -} - -sw_error_t -qca808x_ptp_tx_ts5_reg_set(a_uint32_t dev_id, a_uint32_t phy_id, - union ptp_tx_ts5_reg_u *value) -{ - return qca808x_phy_ptp_mmd_write( - dev_id, - phy_id, QCA808X_PHY_MMD3_NUM, PTP_TX_TS5_REG_ADDRESS, - value->val); -} - -sw_error_t -qca808x_ptp_tx_ts6_reg_get(a_uint32_t dev_id, a_uint32_t phy_id, - union ptp_tx_ts6_reg_u *value) -{ - return qca808x_phy_ptp_mmd_read( - dev_id, - phy_id, QCA808X_PHY_MMD3_NUM, PTP_TX_TS6_REG_ADDRESS, - &value->val); -} - -sw_error_t -qca808x_ptp_tx_ts6_reg_set(a_uint32_t dev_id, a_uint32_t phy_id, - union ptp_tx_ts6_reg_u *value) -{ - return qca808x_phy_ptp_mmd_write( - dev_id, - phy_id, QCA808X_PHY_MMD3_NUM, PTP_TX_TS6_REG_ADDRESS, - value->val); -} - -sw_error_t -qca808x_ptp_orig_corr0_reg_get(a_uint32_t dev_id, a_uint32_t phy_id, - union ptp_orig_corr0_reg_u *value) -{ - return qca808x_phy_ptp_mmd_read( - dev_id, - phy_id, QCA808X_PHY_MMD3_NUM, PTP_ORIG_CORR0_REG_ADDRESS, - &value->val); -} - -sw_error_t -qca808x_ptp_orig_corr0_reg_set(a_uint32_t dev_id, a_uint32_t phy_id, - union ptp_orig_corr0_reg_u *value) -{ - return qca808x_phy_ptp_mmd_write( - dev_id, - phy_id, QCA808X_PHY_MMD3_NUM, PTP_ORIG_CORR0_REG_ADDRESS, - value->val); -} - -sw_error_t -qca808x_ptp_orig_corr1_reg_get(a_uint32_t dev_id, a_uint32_t phy_id, - union ptp_orig_corr1_reg_u *value) -{ - return qca808x_phy_ptp_mmd_read( - dev_id, - phy_id, QCA808X_PHY_MMD3_NUM, PTP_ORIG_CORR1_REG_ADDRESS, - &value->val); -} - -sw_error_t -qca808x_ptp_orig_corr1_reg_set(a_uint32_t dev_id, a_uint32_t phy_id, - union ptp_orig_corr1_reg_u *value) -{ - return qca808x_phy_ptp_mmd_write( - dev_id, - phy_id, QCA808X_PHY_MMD3_NUM, PTP_ORIG_CORR1_REG_ADDRESS, - value->val); -} - -sw_error_t -qca808x_ptp_orig_corr2_reg_get(a_uint32_t dev_id, a_uint32_t phy_id, - union ptp_orig_corr2_reg_u *value) -{ - return qca808x_phy_ptp_mmd_read( - dev_id, - phy_id, QCA808X_PHY_MMD3_NUM, PTP_ORIG_CORR2_REG_ADDRESS, - &value->val); -} - -sw_error_t -qca808x_ptp_orig_corr2_reg_set(a_uint32_t dev_id, a_uint32_t phy_id, - union ptp_orig_corr2_reg_u *value) -{ - return qca808x_phy_ptp_mmd_write( - dev_id, - phy_id, QCA808X_PHY_MMD3_NUM, PTP_ORIG_CORR2_REG_ADDRESS, - value->val); -} - -sw_error_t -qca808x_ptp_orig_corr3_reg_get(a_uint32_t dev_id, a_uint32_t phy_id, - union ptp_orig_corr3_reg_u *value) -{ - return qca808x_phy_ptp_mmd_read( - dev_id, - phy_id, QCA808X_PHY_MMD3_NUM, PTP_ORIG_CORR3_REG_ADDRESS, - &value->val); -} - -sw_error_t -qca808x_ptp_orig_corr3_reg_set(a_uint32_t dev_id, a_uint32_t phy_id, - union ptp_orig_corr3_reg_u *value) -{ - return qca808x_phy_ptp_mmd_write( - dev_id, - phy_id, QCA808X_PHY_MMD3_NUM, PTP_ORIG_CORR3_REG_ADDRESS, - value->val); -} - -sw_error_t -qca808x_ptp_in_trig0_reg_get(a_uint32_t dev_id, a_uint32_t phy_id, - union ptp_in_trig0_reg_u *value) -{ - return qca808x_phy_ptp_mmd_read( - dev_id, - phy_id, QCA808X_PHY_MMD3_NUM, PTP_IN_TRIG0_REG_ADDRESS, - &value->val); -} - -sw_error_t -qca808x_ptp_in_trig0_reg_set(a_uint32_t dev_id, a_uint32_t phy_id, - union ptp_in_trig0_reg_u *value) -{ - return qca808x_phy_ptp_mmd_write( - dev_id, - phy_id, QCA808X_PHY_MMD3_NUM, PTP_IN_TRIG0_REG_ADDRESS, - value->val); -} - -sw_error_t -qca808x_ptp_in_trig1_reg_get(a_uint32_t dev_id, a_uint32_t phy_id, - union ptp_in_trig1_reg_u *value) -{ - return qca808x_phy_ptp_mmd_read( - dev_id, - phy_id, QCA808X_PHY_MMD3_NUM, PTP_IN_TRIG1_REG_ADDRESS, - &value->val); -} - -sw_error_t -qca808x_ptp_in_trig1_reg_set(a_uint32_t dev_id, a_uint32_t phy_id, - union ptp_in_trig1_reg_u *value) -{ - return qca808x_phy_ptp_mmd_write( - dev_id, - phy_id, QCA808X_PHY_MMD3_NUM, PTP_IN_TRIG1_REG_ADDRESS, - value->val); -} - -sw_error_t -qca808x_ptp_in_trig2_reg_get(a_uint32_t dev_id, a_uint32_t phy_id, - union ptp_in_trig2_reg_u *value) -{ - return qca808x_phy_ptp_mmd_read( - dev_id, - phy_id, QCA808X_PHY_MMD3_NUM, PTP_IN_TRIG2_REG_ADDRESS, - &value->val); -} - -sw_error_t -qca808x_ptp_in_trig2_reg_set(a_uint32_t dev_id, a_uint32_t phy_id, - union ptp_in_trig2_reg_u *value) -{ - return qca808x_phy_ptp_mmd_write( - dev_id, - phy_id, QCA808X_PHY_MMD3_NUM, PTP_IN_TRIG2_REG_ADDRESS, - value->val); -} - -sw_error_t -qca808x_ptp_in_trig3_reg_get( - a_uint32_t dev_id, a_uint32_t phy_id, - union ptp_in_trig3_reg_u *value) -{ - return qca808x_phy_ptp_mmd_read( - dev_id, - phy_id, QCA808X_PHY_MMD3_NUM, PTP_IN_TRIG3_REG_ADDRESS, - &value->val); -} - -sw_error_t -qca808x_ptp_in_trig3_reg_set( - a_uint32_t dev_id, a_uint32_t phy_id, - union ptp_in_trig3_reg_u *value) -{ - return qca808x_phy_ptp_mmd_write( - dev_id, - phy_id, QCA808X_PHY_MMD3_NUM, PTP_IN_TRIG3_REG_ADDRESS, - value->val); -} - -sw_error_t -qca808x_ptp_tx_latency_reg_get( - a_uint32_t dev_id, a_uint32_t phy_id, - union ptp_tx_latency_reg_u *value) -{ - return qca808x_phy_ptp_mmd_read( - dev_id, - phy_id, QCA808X_PHY_MMD3_NUM, PTP_TX_LATENCY_REG_ADDRESS, - &value->val); -} - -sw_error_t -qca808x_ptp_tx_latency_reg_set( - a_uint32_t dev_id, a_uint32_t phy_id, - union ptp_tx_latency_reg_u *value) -{ - return qca808x_phy_ptp_mmd_write( - dev_id, - phy_id, QCA808X_PHY_MMD3_NUM, PTP_TX_LATENCY_REG_ADDRESS, - value->val); -} - -sw_error_t -qca808x_ptp_rtc_inc0_reg_get( - a_uint32_t dev_id, a_uint32_t phy_id, - union ptp_rtc_inc0_reg_u *value) -{ - return qca808x_phy_ptp_mmd_read( - dev_id, - phy_id, QCA808X_PHY_MMD3_NUM, PTP_RTC_INC0_REG_ADDRESS, - &value->val); -} - -sw_error_t -qca808x_ptp_rtc_inc0_reg_set( - a_uint32_t dev_id, a_uint32_t phy_id, - union ptp_rtc_inc0_reg_u *value) -{ - return qca808x_phy_ptp_mmd_write( - dev_id, - phy_id, QCA808X_PHY_MMD3_NUM, PTP_RTC_INC0_REG_ADDRESS, - value->val); -} - -sw_error_t -qca808x_ptp_rtc_inc1_reg_get( - a_uint32_t dev_id, a_uint32_t phy_id, - union ptp_rtc_inc1_reg_u *value) -{ - return qca808x_phy_ptp_mmd_read( - dev_id, - phy_id, QCA808X_PHY_MMD3_NUM, PTP_RTC_INC1_REG_ADDRESS, - &value->val); -} - -sw_error_t -qca808x_ptp_rtc_inc1_reg_set( - a_uint32_t dev_id, a_uint32_t phy_id, - union ptp_rtc_inc1_reg_u *value) -{ - return qca808x_phy_ptp_mmd_write( - dev_id, - phy_id, QCA808X_PHY_MMD3_NUM, PTP_RTC_INC1_REG_ADDRESS, - value->val); -} - -sw_error_t -qca808x_ptp_rtcoffs0_reg_get( - a_uint32_t dev_id, a_uint32_t phy_id, - union ptp_rtcoffs0_reg_u *value) -{ - return qca808x_phy_ptp_mmd_read( - dev_id, - phy_id, QCA808X_PHY_MMD3_NUM, PTP_RTCOFFS0_REG_ADDRESS, - &value->val); -} - -sw_error_t -qca808x_ptp_rtcoffs0_reg_set( - a_uint32_t dev_id, a_uint32_t phy_id, - union ptp_rtcoffs0_reg_u *value) -{ - return qca808x_phy_ptp_mmd_write( - dev_id, - phy_id, QCA808X_PHY_MMD3_NUM, PTP_RTCOFFS0_REG_ADDRESS, - value->val); -} - -sw_error_t -qca808x_ptp_rtcoffs1_reg_get( - a_uint32_t dev_id, a_uint32_t phy_id, - union ptp_rtcoffs1_reg_u *value) -{ - return qca808x_phy_ptp_mmd_read( - dev_id, - phy_id, QCA808X_PHY_MMD3_NUM, PTP_RTCOFFS1_REG_ADDRESS, - &value->val); -} - -sw_error_t -qca808x_ptp_rtcoffs1_reg_set( - a_uint32_t dev_id, a_uint32_t phy_id, - union ptp_rtcoffs1_reg_u *value) -{ - return qca808x_phy_ptp_mmd_write( - dev_id, - phy_id, QCA808X_PHY_MMD3_NUM, PTP_RTCOFFS1_REG_ADDRESS, - value->val); -} - -sw_error_t -qca808x_ptp_rtcoffs2_reg_get( - a_uint32_t dev_id, a_uint32_t phy_id, - union ptp_rtcoffs2_reg_u *value) -{ - return qca808x_phy_ptp_mmd_read( - dev_id, - phy_id, QCA808X_PHY_MMD3_NUM, PTP_RTCOFFS2_REG_ADDRESS, - &value->val); -} - -sw_error_t -qca808x_ptp_rtcoffs2_reg_set( - a_uint32_t dev_id, a_uint32_t phy_id, - union ptp_rtcoffs2_reg_u *value) -{ - return qca808x_phy_ptp_mmd_write( - dev_id, - phy_id, QCA808X_PHY_MMD3_NUM, PTP_RTCOFFS2_REG_ADDRESS, - value->val); -} - -sw_error_t -qca808x_ptp_rtcoffs3_reg_get( - a_uint32_t dev_id, a_uint32_t phy_id, - union ptp_rtcoffs3_reg_u *value) -{ - return qca808x_phy_ptp_mmd_read( - dev_id, - phy_id, QCA808X_PHY_MMD3_NUM, PTP_RTCOFFS3_REG_ADDRESS, - &value->val); -} - -sw_error_t -qca808x_ptp_rtcoffs3_reg_set( - a_uint32_t dev_id, a_uint32_t phy_id, - union ptp_rtcoffs3_reg_u *value) -{ - return qca808x_phy_ptp_mmd_write( - dev_id, - phy_id, QCA808X_PHY_MMD3_NUM, PTP_RTCOFFS3_REG_ADDRESS, - value->val); -} - -sw_error_t -qca808x_ptp_rtcoffs4_reg_get( - a_uint32_t dev_id, a_uint32_t phy_id, - union ptp_rtcoffs4_reg_u *value) -{ - return qca808x_phy_ptp_mmd_read( - dev_id, - phy_id, QCA808X_PHY_MMD3_NUM, PTP_RTCOFFS4_REG_ADDRESS, - &value->val); -} - -sw_error_t -qca808x_ptp_rtcoffs4_reg_set( - a_uint32_t dev_id, a_uint32_t phy_id, - union ptp_rtcoffs4_reg_u *value) -{ - return qca808x_phy_ptp_mmd_write( - dev_id, - phy_id, QCA808X_PHY_MMD3_NUM, PTP_RTCOFFS4_REG_ADDRESS, - value->val); -} - -sw_error_t -qca808x_ptp_rtc0_reg_get( - a_uint32_t dev_id, a_uint32_t phy_id, - union ptp_rtc0_reg_u *value) -{ - return qca808x_phy_ptp_mmd_read( - dev_id, - phy_id, QCA808X_PHY_MMD3_NUM, PTP_RTC0_REG_ADDRESS, - &value->val); -} - -sw_error_t -qca808x_ptp_rtc0_reg_set( - a_uint32_t dev_id, a_uint32_t phy_id, - union ptp_rtc0_reg_u *value) -{ - return qca808x_phy_ptp_mmd_write( - dev_id, - phy_id, QCA808X_PHY_MMD3_NUM, PTP_RTC0_REG_ADDRESS, - value->val); -} - -sw_error_t -qca808x_ptp_rtc1_reg_get( - a_uint32_t dev_id, a_uint32_t phy_id, - union ptp_rtc1_reg_u *value) -{ - return qca808x_phy_ptp_mmd_read( - dev_id, - phy_id, QCA808X_PHY_MMD3_NUM, PTP_RTC1_REG_ADDRESS, - &value->val); -} - -sw_error_t -qca808x_ptp_rtc1_reg_set( - a_uint32_t dev_id, a_uint32_t phy_id, - union ptp_rtc1_reg_u *value) -{ - return qca808x_phy_ptp_mmd_write( - dev_id, - phy_id, QCA808X_PHY_MMD3_NUM, PTP_RTC1_REG_ADDRESS, - value->val); -} - -sw_error_t -qca808x_ptp_rtc2_reg_get( - a_uint32_t dev_id, a_uint32_t phy_id, - union ptp_rtc2_reg_u *value) -{ - return qca808x_phy_ptp_mmd_read( - dev_id, - phy_id, QCA808X_PHY_MMD3_NUM, PTP_RTC2_REG_ADDRESS, - &value->val); -} - -sw_error_t -qca808x_ptp_rtc2_reg_set( - a_uint32_t dev_id, a_uint32_t phy_id, - union ptp_rtc2_reg_u *value) -{ - return qca808x_phy_ptp_mmd_write( - dev_id, - phy_id, QCA808X_PHY_MMD3_NUM, PTP_RTC2_REG_ADDRESS, - value->val); -} - -sw_error_t -qca808x_ptp_rtc3_reg_get( - a_uint32_t dev_id, a_uint32_t phy_id, - union ptp_rtc3_reg_u *value) -{ - return qca808x_phy_ptp_mmd_read( - dev_id, - phy_id, QCA808X_PHY_MMD3_NUM, PTP_RTC3_REG_ADDRESS, - &value->val); -} - -sw_error_t -qca808x_ptp_rtc3_reg_set( - a_uint32_t dev_id, a_uint32_t phy_id, - union ptp_rtc3_reg_u *value) -{ - return qca808x_phy_ptp_mmd_write( - dev_id, - phy_id, QCA808X_PHY_MMD3_NUM, PTP_RTC3_REG_ADDRESS, - value->val); -} - -sw_error_t -qca808x_ptp_rtc4_reg_get( - a_uint32_t dev_id, a_uint32_t phy_id, - union ptp_rtc4_reg_u *value) -{ - return qca808x_phy_ptp_mmd_read( - dev_id, - phy_id, QCA808X_PHY_MMD3_NUM, PTP_RTC4_REG_ADDRESS, - &value->val); -} - -sw_error_t -qca808x_ptp_rtc4_reg_set( - a_uint32_t dev_id, a_uint32_t phy_id, - union ptp_rtc4_reg_u *value) -{ - return qca808x_phy_ptp_mmd_write( - dev_id, - phy_id, QCA808X_PHY_MMD3_NUM, PTP_RTC4_REG_ADDRESS, - value->val); -} - -sw_error_t -qca808x_ptp_rtc5_reg_get( - a_uint32_t dev_id, a_uint32_t phy_id, - union ptp_rtc5_reg_u *value) -{ - return qca808x_phy_ptp_mmd_read( - dev_id, - phy_id, QCA808X_PHY_MMD3_NUM, PTP_RTC5_REG_ADDRESS, - &value->val); -} - -sw_error_t -qca808x_ptp_rtc5_reg_set( - a_uint32_t dev_id, a_uint32_t phy_id, - union ptp_rtc5_reg_u *value) -{ - return qca808x_phy_ptp_mmd_write( - dev_id, - phy_id, QCA808X_PHY_MMD3_NUM, PTP_RTC5_REG_ADDRESS, - value->val); -} - -sw_error_t -qca808x_ptp_rtc6_reg_get( - a_uint32_t dev_id, a_uint32_t phy_id, - union ptp_rtc6_reg_u *value) -{ - return qca808x_phy_ptp_mmd_read( - dev_id, - phy_id, QCA808X_PHY_MMD3_NUM, PTP_RTC6_REG_ADDRESS, - &value->val); -} - -sw_error_t -qca808x_ptp_rtc6_reg_set( - a_uint32_t dev_id, a_uint32_t phy_id, - union ptp_rtc6_reg_u *value) -{ - return qca808x_phy_ptp_mmd_write( - dev_id, - phy_id, QCA808X_PHY_MMD3_NUM, PTP_RTC6_REG_ADDRESS, - value->val); -} - -sw_error_t -qca808x_ptp_rtcoffs_valid_reg_get( - a_uint32_t dev_id, a_uint32_t phy_id, - union ptp_rtcoffs_valid_reg_u *value) -{ - return qca808x_phy_ptp_mmd_read( - dev_id, - phy_id, QCA808X_PHY_MMD3_NUM, PTP_RTCOFFS_VALID_REG_ADDRESS, - &value->val); -} - -sw_error_t -qca808x_ptp_rtcoffs_valid_reg_set( - a_uint32_t dev_id, a_uint32_t phy_id, - union ptp_rtcoffs_valid_reg_u *value) -{ - return qca808x_phy_ptp_mmd_write( - dev_id, - phy_id, QCA808X_PHY_MMD3_NUM, PTP_RTCOFFS_VALID_REG_ADDRESS, - value->val); -} - -sw_error_t -qca808x_ptp_misc_config_reg_get( - a_uint32_t dev_id, a_uint32_t phy_id, - union ptp_misc_config_reg_u *value) -{ - return qca808x_phy_ptp_mmd_read( - dev_id, - phy_id, QCA808X_PHY_MMD3_NUM, PTP_MISC_CONFIG_REG_ADDRESS, - &value->val); -} - -sw_error_t -qca808x_ptp_misc_config_reg_set( - a_uint32_t dev_id, a_uint32_t phy_id, - union ptp_misc_config_reg_u *value) -{ - return qca808x_phy_ptp_mmd_write( - dev_id, - phy_id, QCA808X_PHY_MMD3_NUM, PTP_MISC_CONFIG_REG_ADDRESS, - value->val); -} - -sw_error_t -qca808x_ptp_ext_imr_reg_get( - a_uint32_t dev_id, a_uint32_t phy_id, - union ptp_ext_imr_reg_u *value) -{ - return qca808x_phy_ptp_mmd_read( - dev_id, - phy_id, QCA808X_PHY_MMD3_NUM, PTP_EXT_IMR_REG_ADDRESS, - &value->val); -} - -sw_error_t -qca808x_ptp_ext_imr_reg_set( - a_uint32_t dev_id, a_uint32_t phy_id, - union ptp_ext_imr_reg_u *value) -{ - return qca808x_phy_ptp_mmd_write( - dev_id, - phy_id, QCA808X_PHY_MMD3_NUM, PTP_EXT_IMR_REG_ADDRESS, - value->val); -} - -sw_error_t -qca808x_ptp_ext_isr_reg_get( - a_uint32_t dev_id, a_uint32_t phy_id, - union ptp_ext_isr_reg_u *value) -{ - return qca808x_phy_ptp_mmd_read( - dev_id, - phy_id, QCA808X_PHY_MMD3_NUM, PTP_EXT_ISR_REG_ADDRESS, - &value->val); -} - -sw_error_t -qca808x_ptp_ext_isr_reg_set( - a_uint32_t dev_id, a_uint32_t phy_id, - union ptp_ext_isr_reg_u *value) -{ - return qca808x_phy_ptp_mmd_write( - dev_id, - phy_id, QCA808X_PHY_MMD3_NUM, PTP_EXT_ISR_REG_ADDRESS, - value->val); -} - -sw_error_t -qca808x_ptp_rtc_ext_conf_reg_get( - a_uint32_t dev_id, a_uint32_t phy_id, - union ptp_rtc_ext_conf_reg_u *value) -{ - return qca808x_phy_ptp_mmd_read( - dev_id, - phy_id, QCA808X_PHY_MMD3_NUM, PTP_RTC_EXT_CONF_REG_ADDRESS, - &value->val); -} - -sw_error_t -qca808x_ptp_rtc_ext_conf_reg_set( - a_uint32_t dev_id, a_uint32_t phy_id, - union ptp_rtc_ext_conf_reg_u *value) -{ - return qca808x_phy_ptp_mmd_write( - dev_id, - phy_id, QCA808X_PHY_MMD3_NUM, PTP_RTC_EXT_CONF_REG_ADDRESS, - value->val); -} - -sw_error_t -qca808x_ptp_rtc_preloaded0_reg_get( - a_uint32_t dev_id, a_uint32_t phy_id, - union ptp_rtc_preloaded0_reg_u *value) -{ - return qca808x_phy_ptp_mmd_read( - dev_id, - phy_id, QCA808X_PHY_MMD3_NUM, PTP_RTC_PRELOADED0_REG_ADDRESS, - &value->val); -} - -sw_error_t -qca808x_ptp_rtc_preloaded0_reg_set( - a_uint32_t dev_id, a_uint32_t phy_id, - union ptp_rtc_preloaded0_reg_u *value) -{ - return qca808x_phy_ptp_mmd_write( - dev_id, - phy_id, QCA808X_PHY_MMD3_NUM, PTP_RTC_PRELOADED0_REG_ADDRESS, - value->val); -} - -sw_error_t -qca808x_ptp_rtc_preloaded1_reg_get( - a_uint32_t dev_id, a_uint32_t phy_id, - union ptp_rtc_preloaded1_reg_u *value) -{ - return qca808x_phy_ptp_mmd_read( - dev_id, - phy_id, QCA808X_PHY_MMD3_NUM, PTP_RTC_PRELOADED1_REG_ADDRESS, - &value->val); -} - -sw_error_t -qca808x_ptp_rtc_preloaded1_reg_set( - a_uint32_t dev_id, a_uint32_t phy_id, - union ptp_rtc_preloaded1_reg_u *value) -{ - return qca808x_phy_ptp_mmd_write( - dev_id, - phy_id, QCA808X_PHY_MMD3_NUM, PTP_RTC_PRELOADED1_REG_ADDRESS, - value->val); -} - -sw_error_t -qca808x_ptp_rtc_preloaded2_reg_get( - a_uint32_t dev_id, a_uint32_t phy_id, - union ptp_rtc_preloaded2_reg_u *value) -{ - return qca808x_phy_ptp_mmd_read( - dev_id, - phy_id, QCA808X_PHY_MMD3_NUM, PTP_RTC_PRELOADED2_REG_ADDRESS, - &value->val); -} - -sw_error_t -qca808x_ptp_rtc_preloaded2_reg_set( - a_uint32_t dev_id, a_uint32_t phy_id, - union ptp_rtc_preloaded2_reg_u *value) -{ - return qca808x_phy_ptp_mmd_write( - dev_id, - phy_id, QCA808X_PHY_MMD3_NUM, PTP_RTC_PRELOADED2_REG_ADDRESS, - value->val); -} - -sw_error_t -qca808x_ptp_rtc_preloaded3_reg_get( - a_uint32_t dev_id, a_uint32_t phy_id, - union ptp_rtc_preloaded3_reg_u *value) -{ - return qca808x_phy_ptp_mmd_read( - dev_id, - phy_id, QCA808X_PHY_MMD3_NUM, PTP_RTC_PRELOADED3_REG_ADDRESS, - &value->val); -} - -sw_error_t -qca808x_ptp_rtc_preloaded3_reg_set( - a_uint32_t dev_id, a_uint32_t phy_id, - union ptp_rtc_preloaded3_reg_u *value) -{ - return qca808x_phy_ptp_mmd_write( - dev_id, - phy_id, QCA808X_PHY_MMD3_NUM, PTP_RTC_PRELOADED3_REG_ADDRESS, - value->val); -} - -sw_error_t -qca808x_ptp_rtc_preloaded4_reg_get( - a_uint32_t dev_id, a_uint32_t phy_id, - union ptp_rtc_preloaded4_reg_u *value) -{ - return qca808x_phy_ptp_mmd_read( - dev_id, - phy_id, QCA808X_PHY_MMD3_NUM, PTP_RTC_PRELOADED4_REG_ADDRESS, - &value->val); -} - -sw_error_t -qca808x_ptp_rtc_preloaded4_reg_set( - a_uint32_t dev_id, a_uint32_t phy_id, - union ptp_rtc_preloaded4_reg_u *value) -{ - return qca808x_phy_ptp_mmd_write( - dev_id, - phy_id, QCA808X_PHY_MMD3_NUM, PTP_RTC_PRELOADED4_REG_ADDRESS, - value->val); -} - -sw_error_t -qca808x_ptp_gm_conf0_reg_get( - a_uint32_t dev_id, a_uint32_t phy_id, - union ptp_gm_conf0_reg_u *value) -{ - return qca808x_phy_ptp_mmd_read( - dev_id, - phy_id, QCA808X_PHY_MMD3_NUM, PTP_GM_CONF0_REG_ADDRESS, - &value->val); -} - -sw_error_t -qca808x_ptp_gm_conf0_reg_set( - a_uint32_t dev_id, a_uint32_t phy_id, - union ptp_gm_conf0_reg_u *value) -{ - return qca808x_phy_ptp_mmd_write( - dev_id, - phy_id, QCA808X_PHY_MMD3_NUM, PTP_GM_CONF0_REG_ADDRESS, - value->val); -} - -sw_error_t -qca808x_ptp_gm_conf1_reg_get( - a_uint32_t dev_id, a_uint32_t phy_id, - union ptp_gm_conf1_reg_u *value) -{ - return qca808x_phy_ptp_mmd_read( - dev_id, - phy_id, QCA808X_PHY_MMD3_NUM, PTP_GM_CONF1_REG_ADDRESS, - &value->val); -} - -sw_error_t -qca808x_ptp_gm_conf1_reg_set( - a_uint32_t dev_id, a_uint32_t phy_id, - union ptp_gm_conf1_reg_u *value) -{ - return qca808x_phy_ptp_mmd_write( - dev_id, - phy_id, QCA808X_PHY_MMD3_NUM, PTP_GM_CONF1_REG_ADDRESS, - value->val); -} - -sw_error_t -qca808x_ptp_ppsin_ts0_reg_get( - a_uint32_t dev_id, a_uint32_t phy_id, - union ptp_ppsin_ts0_reg_u *value) -{ - return qca808x_phy_ptp_mmd_read( - dev_id, - phy_id, QCA808X_PHY_MMD3_NUM, PTP_PPSIN_TS0_REG_ADDRESS, - &value->val); -} - -sw_error_t -qca808x_ptp_ppsin_ts0_reg_set( - a_uint32_t dev_id, a_uint32_t phy_id, - union ptp_ppsin_ts0_reg_u *value) -{ - return qca808x_phy_ptp_mmd_write( - dev_id, - phy_id, QCA808X_PHY_MMD3_NUM, PTP_PPSIN_TS0_REG_ADDRESS, - value->val); -} - -sw_error_t -qca808x_ptp_ppsin_ts1_reg_get( - a_uint32_t dev_id, a_uint32_t phy_id, - union ptp_ppsin_ts1_reg_u *value) -{ - return qca808x_phy_ptp_mmd_read( - dev_id, - phy_id, QCA808X_PHY_MMD3_NUM, PTP_PPSIN_TS1_REG_ADDRESS, - &value->val); -} - -sw_error_t -qca808x_ptp_ppsin_ts1_reg_set( - a_uint32_t dev_id, a_uint32_t phy_id, - union ptp_ppsin_ts1_reg_u *value) -{ - return qca808x_phy_ptp_mmd_write( - dev_id, - phy_id, QCA808X_PHY_MMD3_NUM, PTP_PPSIN_TS1_REG_ADDRESS, - value->val); -} - -sw_error_t -qca808x_ptp_ppsin_ts2_reg_get( - a_uint32_t dev_id, a_uint32_t phy_id, - union ptp_ppsin_ts2_reg_u *value) -{ - return qca808x_phy_ptp_mmd_read( - dev_id, - phy_id, QCA808X_PHY_MMD3_NUM, PTP_PPSIN_TS2_REG_ADDRESS, - &value->val); -} - -sw_error_t -qca808x_ptp_ppsin_ts2_reg_set( - a_uint32_t dev_id, a_uint32_t phy_id, - union ptp_ppsin_ts2_reg_u *value) -{ - return qca808x_phy_ptp_mmd_write( - dev_id, - phy_id, QCA808X_PHY_MMD3_NUM, PTP_PPSIN_TS2_REG_ADDRESS, - value->val); -} - -sw_error_t -qca808x_ptp_ppsin_ts3_reg_get( - a_uint32_t dev_id, a_uint32_t phy_id, - union ptp_ppsin_ts3_reg_u *value) -{ - return qca808x_phy_ptp_mmd_read( - dev_id, - phy_id, QCA808X_PHY_MMD3_NUM, PTP_PPSIN_TS3_REG_ADDRESS, - &value->val); -} - -sw_error_t -qca808x_ptp_ppsin_ts3_reg_set( - a_uint32_t dev_id, a_uint32_t phy_id, - union ptp_ppsin_ts3_reg_u *value) -{ - return qca808x_phy_ptp_mmd_write( - dev_id, - phy_id, QCA808X_PHY_MMD3_NUM, PTP_PPSIN_TS3_REG_ADDRESS, - value->val); -} - -sw_error_t -qca808x_ptp_ppsin_ts4_reg_get( - a_uint32_t dev_id, a_uint32_t phy_id, - union ptp_ppsin_ts4_reg_u *value) -{ - return qca808x_phy_ptp_mmd_read( - dev_id, - phy_id, QCA808X_PHY_MMD3_NUM, PTP_PPSIN_TS4_REG_ADDRESS, - &value->val); -} - -sw_error_t -qca808x_ptp_ppsin_ts4_reg_set( - a_uint32_t dev_id, a_uint32_t phy_id, - union ptp_ppsin_ts4_reg_u *value) -{ - return qca808x_phy_ptp_mmd_write( - dev_id, - phy_id, QCA808X_PHY_MMD3_NUM, PTP_PPSIN_TS4_REG_ADDRESS, - value->val); -} - -sw_error_t -qca808x_ptp_hwpll_inc0_reg_get( - a_uint32_t dev_id, a_uint32_t phy_id, - union ptp_hwpll_inc0_reg_u *value) -{ - return qca808x_phy_ptp_mmd_read( - dev_id, - phy_id, QCA808X_PHY_MMD3_NUM, PTP_HWPLL_INC0_REG_ADDRESS, - &value->val); -} - -sw_error_t -qca808x_ptp_hwpll_inc0_reg_set( - a_uint32_t dev_id, a_uint32_t phy_id, - union ptp_hwpll_inc0_reg_u *value) -{ - return qca808x_phy_ptp_mmd_write( - dev_id, - phy_id, QCA808X_PHY_MMD3_NUM, PTP_HWPLL_INC0_REG_ADDRESS, - value->val); -} - -sw_error_t -qca808x_ptp_hwpll_inc1_reg_get( - a_uint32_t dev_id, a_uint32_t phy_id, - union ptp_hwpll_inc1_reg_u *value) -{ - return qca808x_phy_ptp_mmd_read( - dev_id, - phy_id, QCA808X_PHY_MMD3_NUM, PTP_HWPLL_INC1_REG_ADDRESS, - &value->val); -} - -sw_error_t -qca808x_ptp_hwpll_inc1_reg_set( - a_uint32_t dev_id, a_uint32_t phy_id, - union ptp_hwpll_inc1_reg_u *value) -{ - return qca808x_phy_ptp_mmd_write( - dev_id, - phy_id, QCA808X_PHY_MMD3_NUM, PTP_HWPLL_INC1_REG_ADDRESS, - value->val); -} - -sw_error_t -qca808x_ptp_ppsin_latency_reg_get( - a_uint32_t dev_id, a_uint32_t phy_id, - union ptp_ppsin_latency_reg_u *value) -{ - return qca808x_phy_ptp_mmd_read( - dev_id, - phy_id, QCA808X_PHY_MMD3_NUM, PTP_PPSIN_LATENCY_REG_ADDRESS, - &value->val); -} - -sw_error_t -qca808x_ptp_ppsin_latency_reg_set( - a_uint32_t dev_id, a_uint32_t phy_id, - union ptp_ppsin_latency_reg_u *value) -{ - return qca808x_phy_ptp_mmd_write( - dev_id, - phy_id, QCA808X_PHY_MMD3_NUM, PTP_PPSIN_LATENCY_REG_ADDRESS, - value->val); -} - -sw_error_t -qca808x_ptp_trigger0_config_reg_get( - a_uint32_t dev_id, a_uint32_t phy_id, - union ptp_trigger0_config_reg_u *value) -{ - return qca808x_phy_ptp_mmd_read( - dev_id, - phy_id, QCA808X_PHY_MMD3_NUM, PTP_TRIGGER0_CONFIG_REG_ADDRESS, - &value->val); -} - -sw_error_t -qca808x_ptp_trigger0_config_reg_set( - a_uint32_t dev_id, a_uint32_t phy_id, - union ptp_trigger0_config_reg_u *value) -{ - return qca808x_phy_ptp_mmd_write( - dev_id, - phy_id, QCA808X_PHY_MMD3_NUM, PTP_TRIGGER0_CONFIG_REG_ADDRESS, - value->val); -} - -sw_error_t -qca808x_ptp_trigger0_status_reg_get( - a_uint32_t dev_id, a_uint32_t phy_id, - union ptp_trigger0_status_reg_u *value) -{ - return qca808x_phy_ptp_mmd_read( - dev_id, - phy_id, QCA808X_PHY_MMD3_NUM, PTP_TRIGGER0_STATUS_REG_ADDRESS, - &value->val); -} - -sw_error_t -qca808x_ptp_trigger0_status_reg_set( - a_uint32_t dev_id, a_uint32_t phy_id, - union ptp_trigger0_status_reg_u *value) -{ - return qca808x_phy_ptp_mmd_write( - dev_id, - phy_id, QCA808X_PHY_MMD3_NUM, PTP_TRIGGER0_STATUS_REG_ADDRESS, - value->val); -} - -sw_error_t -qca808x_ptp_trigger1_config_reg_get( - a_uint32_t dev_id, a_uint32_t phy_id, - union ptp_trigger1_config_reg_u *value) -{ - return qca808x_phy_ptp_mmd_read( - dev_id, - phy_id, QCA808X_PHY_MMD3_NUM, PTP_TRIGGER1_CONFIG_REG_ADDRESS, - &value->val); -} - -sw_error_t -qca808x_ptp_trigger1_config_reg_set( - a_uint32_t dev_id, a_uint32_t phy_id, - union ptp_trigger1_config_reg_u *value) -{ - return qca808x_phy_ptp_mmd_write( - dev_id, - phy_id, QCA808X_PHY_MMD3_NUM, PTP_TRIGGER1_CONFIG_REG_ADDRESS, - value->val); -} - -sw_error_t -qca808x_ptp_trigger1_status_reg_get( - a_uint32_t dev_id, a_uint32_t phy_id, - union ptp_trigger1_status_reg_u *value) -{ - return qca808x_phy_ptp_mmd_read( - dev_id, - phy_id, QCA808X_PHY_MMD3_NUM, PTP_TRIGGER1_STATUS_REG_ADDRESS, - &value->val); -} - -sw_error_t -qca808x_ptp_trigger1_status_reg_set( - a_uint32_t dev_id, a_uint32_t phy_id, - union ptp_trigger1_status_reg_u *value) -{ - return qca808x_phy_ptp_mmd_write( - dev_id, - phy_id, QCA808X_PHY_MMD3_NUM, PTP_TRIGGER1_STATUS_REG_ADDRESS, - value->val); -} - -sw_error_t -qca808x_ptp_trigger0_timestamp0_reg_get( - a_uint32_t dev_id, a_uint32_t phy_id, - union ptp_trigger0_timestamp0_reg_u *value) -{ - return qca808x_phy_ptp_mmd_read( - dev_id, - phy_id, QCA808X_PHY_MMD3_NUM, PTP_TRIGGER0_TIMESTAMP0_REG_ADDRESS, - &value->val); -} - -sw_error_t -qca808x_ptp_trigger0_timestamp0_reg_set( - a_uint32_t dev_id, a_uint32_t phy_id, - union ptp_trigger0_timestamp0_reg_u *value) -{ - return qca808x_phy_ptp_mmd_write( - dev_id, - phy_id, QCA808X_PHY_MMD3_NUM, PTP_TRIGGER0_TIMESTAMP0_REG_ADDRESS, - value->val); -} - -sw_error_t -qca808x_ptp_trigger0_timestamp1_reg_get( - a_uint32_t dev_id, a_uint32_t phy_id, - union ptp_trigger0_timestamp1_reg_u *value) -{ - return qca808x_phy_ptp_mmd_read( - dev_id, - phy_id, QCA808X_PHY_MMD3_NUM, PTP_TRIGGER0_TIMESTAMP1_REG_ADDRESS, - &value->val); -} - -sw_error_t -qca808x_ptp_trigger0_timestamp1_reg_set( - a_uint32_t dev_id, a_uint32_t phy_id, - union ptp_trigger0_timestamp1_reg_u *value) -{ - return qca808x_phy_ptp_mmd_write( - dev_id, - phy_id, QCA808X_PHY_MMD3_NUM, PTP_TRIGGER0_TIMESTAMP1_REG_ADDRESS, - value->val); -} - -sw_error_t -qca808x_ptp_trigger0_timestamp2_reg_get( - a_uint32_t dev_id, a_uint32_t phy_id, - union ptp_trigger0_timestamp2_reg_u *value) -{ - return qca808x_phy_ptp_mmd_read( - dev_id, - phy_id, QCA808X_PHY_MMD3_NUM, PTP_TRIGGER0_TIMESTAMP2_REG_ADDRESS, - &value->val); -} - -sw_error_t -qca808x_ptp_trigger0_timestamp2_reg_set( - a_uint32_t dev_id, a_uint32_t phy_id, - union ptp_trigger0_timestamp2_reg_u *value) -{ - return qca808x_phy_ptp_mmd_write( - dev_id, - phy_id, QCA808X_PHY_MMD3_NUM, PTP_TRIGGER0_TIMESTAMP2_REG_ADDRESS, - value->val); -} - -sw_error_t -qca808x_ptp_trigger0_timestamp3_reg_get( - a_uint32_t dev_id, a_uint32_t phy_id, - union ptp_trigger0_timestamp3_reg_u *value) -{ - return qca808x_phy_ptp_mmd_read( - dev_id, - phy_id, QCA808X_PHY_MMD3_NUM, PTP_TRIGGER0_TIMESTAMP3_REG_ADDRESS, - &value->val); -} - -sw_error_t -qca808x_ptp_trigger0_timestamp3_reg_set( - a_uint32_t dev_id, a_uint32_t phy_id, - union ptp_trigger0_timestamp3_reg_u *value) -{ - return qca808x_phy_ptp_mmd_write( - dev_id, - phy_id, QCA808X_PHY_MMD3_NUM, PTP_TRIGGER0_TIMESTAMP3_REG_ADDRESS, - value->val); -} - -sw_error_t -qca808x_ptp_trigger0_timestamp4_reg_get( - a_uint32_t dev_id, a_uint32_t phy_id, - union ptp_trigger0_timestamp4_reg_u *value) -{ - return qca808x_phy_ptp_mmd_read( - dev_id, - phy_id, QCA808X_PHY_MMD3_NUM, PTP_TRIGGER0_TIMESTAMP4_REG_ADDRESS, - &value->val); -} - -sw_error_t -qca808x_ptp_trigger0_timestamp4_reg_set( - a_uint32_t dev_id, a_uint32_t phy_id, - union ptp_trigger0_timestamp4_reg_u *value) -{ - return qca808x_phy_ptp_mmd_write( - dev_id, - phy_id, QCA808X_PHY_MMD3_NUM, PTP_TRIGGER0_TIMESTAMP4_REG_ADDRESS, - value->val); -} - -sw_error_t -qca808x_ptp_trigger1_timestamp0_reg_get( - a_uint32_t dev_id, a_uint32_t phy_id, - union ptp_trigger1_timestamp0_reg_u *value) -{ - return qca808x_phy_ptp_mmd_read( - dev_id, - phy_id, QCA808X_PHY_MMD3_NUM, PTP_TRIGGER1_TIMESTAMP0_REG_ADDRESS, - &value->val); -} - -sw_error_t -qca808x_ptp_trigger1_timestamp0_reg_set( - a_uint32_t dev_id, a_uint32_t phy_id, - union ptp_trigger1_timestamp0_reg_u *value) -{ - return qca808x_phy_ptp_mmd_write( - dev_id, - phy_id, QCA808X_PHY_MMD3_NUM, PTP_TRIGGER1_TIMESTAMP0_REG_ADDRESS, - value->val); -} - -sw_error_t -qca808x_ptp_trigger1_timestamp1_reg_get( - a_uint32_t dev_id, a_uint32_t phy_id, - union ptp_trigger1_timestamp1_reg_u *value) -{ - return qca808x_phy_ptp_mmd_read( - dev_id, - phy_id, QCA808X_PHY_MMD3_NUM, PTP_TRIGGER1_TIMESTAMP1_REG_ADDRESS, - &value->val); -} - -sw_error_t -qca808x_ptp_trigger1_timestamp1_reg_set( - a_uint32_t dev_id, a_uint32_t phy_id, - union ptp_trigger1_timestamp1_reg_u *value) -{ - return qca808x_phy_ptp_mmd_write( - dev_id, - phy_id, QCA808X_PHY_MMD3_NUM, PTP_TRIGGER1_TIMESTAMP1_REG_ADDRESS, - value->val); -} - -sw_error_t -qca808x_ptp_trigger1_timestamp2_reg_get( - a_uint32_t dev_id, a_uint32_t phy_id, - union ptp_trigger1_timestamp2_reg_u *value) -{ - return qca808x_phy_ptp_mmd_read( - dev_id, - phy_id, QCA808X_PHY_MMD3_NUM, PTP_TRIGGER1_TIMESTAMP2_REG_ADDRESS, - &value->val); -} - -sw_error_t -qca808x_ptp_trigger1_timestamp2_reg_set( - a_uint32_t dev_id, a_uint32_t phy_id, - union ptp_trigger1_timestamp2_reg_u *value) -{ - return qca808x_phy_ptp_mmd_write( - dev_id, - phy_id, QCA808X_PHY_MMD3_NUM, PTP_TRIGGER1_TIMESTAMP2_REG_ADDRESS, - value->val); -} - -sw_error_t -qca808x_ptp_trigger1_timestamp3_reg_get( - a_uint32_t dev_id, a_uint32_t phy_id, - union ptp_trigger1_timestamp3_reg_u *value) -{ - return qca808x_phy_ptp_mmd_read( - dev_id, - phy_id, QCA808X_PHY_MMD3_NUM, PTP_TRIGGER1_TIMESTAMP3_REG_ADDRESS, - &value->val); -} - -sw_error_t -qca808x_ptp_trigger1_timestamp3_reg_set( - a_uint32_t dev_id, a_uint32_t phy_id, - union ptp_trigger1_timestamp3_reg_u *value) -{ - return qca808x_phy_ptp_mmd_write( - dev_id, - phy_id, QCA808X_PHY_MMD3_NUM, PTP_TRIGGER1_TIMESTAMP3_REG_ADDRESS, - value->val); -} - -sw_error_t -qca808x_ptp_trigger1_timestamp4_reg_get( - a_uint32_t dev_id, a_uint32_t phy_id, - union ptp_trigger1_timestamp4_reg_u *value) -{ - return qca808x_phy_ptp_mmd_read( - dev_id, - phy_id, QCA808X_PHY_MMD3_NUM, PTP_TRIGGER1_TIMESTAMP4_REG_ADDRESS, - &value->val); -} - -sw_error_t -qca808x_ptp_trigger1_timestamp4_reg_set( - a_uint32_t dev_id, a_uint32_t phy_id, - union ptp_trigger1_timestamp4_reg_u *value) -{ - return qca808x_phy_ptp_mmd_write( - dev_id, - phy_id, QCA808X_PHY_MMD3_NUM, PTP_TRIGGER1_TIMESTAMP4_REG_ADDRESS, - value->val); -} - -sw_error_t -qca808x_ptp_event0_config_reg_get( - a_uint32_t dev_id, a_uint32_t phy_id, - union ptp_event0_config_reg_u *value) -{ - return qca808x_phy_ptp_mmd_read( - dev_id, - phy_id, QCA808X_PHY_MMD3_NUM, PTP_EVENT0_CONFIG_REG_ADDRESS, - &value->val); -} - -sw_error_t -qca808x_ptp_event0_config_reg_set( - a_uint32_t dev_id, a_uint32_t phy_id, - union ptp_event0_config_reg_u *value) -{ - return qca808x_phy_ptp_mmd_write( - dev_id, - phy_id, QCA808X_PHY_MMD3_NUM, PTP_EVENT0_CONFIG_REG_ADDRESS, - value->val); -} - -sw_error_t -qca808x_ptp_event0_status_reg_get( - a_uint32_t dev_id, a_uint32_t phy_id, - union ptp_event0_status_reg_u *value) -{ - return qca808x_phy_ptp_mmd_read( - dev_id, - phy_id, QCA808X_PHY_MMD3_NUM, PTP_EVENT0_STATUS_REG_ADDRESS, - &value->val); -} - -sw_error_t -qca808x_ptp_event0_status_reg_set( - a_uint32_t dev_id, a_uint32_t phy_id, - union ptp_event0_status_reg_u *value) -{ - return qca808x_phy_ptp_mmd_write( - dev_id, - phy_id, QCA808X_PHY_MMD3_NUM, PTP_EVENT0_STATUS_REG_ADDRESS, - value->val); -} - -sw_error_t -qca808x_ptp_event1_config_reg_get( - a_uint32_t dev_id, a_uint32_t phy_id, - union ptp_event1_config_reg_u *value) -{ - return qca808x_phy_ptp_mmd_read( - dev_id, - phy_id, QCA808X_PHY_MMD3_NUM, PTP_EVENT1_CONFIG_REG_ADDRESS, - &value->val); -} - -sw_error_t -qca808x_ptp_event1_config_reg_set( - a_uint32_t dev_id, a_uint32_t phy_id, - union ptp_event1_config_reg_u *value) -{ - return qca808x_phy_ptp_mmd_write( - dev_id, - phy_id, QCA808X_PHY_MMD3_NUM, PTP_EVENT1_CONFIG_REG_ADDRESS, - value->val); -} - -sw_error_t -qca808x_ptp_event1_status_reg_get( - a_uint32_t dev_id, a_uint32_t phy_id, - union ptp_event1_status_reg_u *value) -{ - return qca808x_phy_ptp_mmd_read( - dev_id, - phy_id, QCA808X_PHY_MMD3_NUM, PTP_EVENT1_STATUS_REG_ADDRESS, - &value->val); -} - -sw_error_t -qca808x_ptp_event1_status_reg_set( - a_uint32_t dev_id, a_uint32_t phy_id, - union ptp_event1_status_reg_u *value) -{ - return qca808x_phy_ptp_mmd_write( - dev_id, - phy_id, QCA808X_PHY_MMD3_NUM, PTP_EVENT1_STATUS_REG_ADDRESS, - value->val); -} - -sw_error_t -qca808x_ptp_event0_timestamp0_reg_get( - a_uint32_t dev_id, a_uint32_t phy_id, - union ptp_event0_timestamp0_reg_u *value) -{ - return qca808x_phy_ptp_mmd_read( - dev_id, - phy_id, QCA808X_PHY_MMD3_NUM, PTP_EVENT0_TIMESTAMP0_REG_ADDRESS, - &value->val); -} - -sw_error_t -qca808x_ptp_event0_timestamp0_reg_set( - a_uint32_t dev_id, a_uint32_t phy_id, - union ptp_event0_timestamp0_reg_u *value) -{ - return qca808x_phy_ptp_mmd_write( - dev_id, - phy_id, QCA808X_PHY_MMD3_NUM, PTP_EVENT0_TIMESTAMP0_REG_ADDRESS, - value->val); -} - -sw_error_t -qca808x_ptp_event0_timestamp1_reg_get( - a_uint32_t dev_id, a_uint32_t phy_id, - union ptp_event0_timestamp1_reg_u *value) -{ - return qca808x_phy_ptp_mmd_read( - dev_id, - phy_id, QCA808X_PHY_MMD3_NUM, PTP_EVENT0_TIMESTAMP1_REG_ADDRESS, - &value->val); -} - -sw_error_t -qca808x_ptp_event0_timestamp1_reg_set( - a_uint32_t dev_id, a_uint32_t phy_id, - union ptp_event0_timestamp1_reg_u *value) -{ - return qca808x_phy_ptp_mmd_write( - dev_id, - phy_id, QCA808X_PHY_MMD3_NUM, PTP_EVENT0_TIMESTAMP1_REG_ADDRESS, - value->val); -} - -sw_error_t -qca808x_ptp_event0_timestamp2_reg_get( - a_uint32_t dev_id, a_uint32_t phy_id, - union ptp_event0_timestamp2_reg_u *value) -{ - return qca808x_phy_ptp_mmd_read( - dev_id, - phy_id, QCA808X_PHY_MMD3_NUM, PTP_EVENT0_TIMESTAMP2_REG_ADDRESS, - &value->val); -} - -sw_error_t -qca808x_ptp_event0_timestamp2_reg_set( - a_uint32_t dev_id, a_uint32_t phy_id, - union ptp_event0_timestamp2_reg_u *value) -{ - return qca808x_phy_ptp_mmd_write( - dev_id, - phy_id, QCA808X_PHY_MMD3_NUM, PTP_EVENT0_TIMESTAMP2_REG_ADDRESS, - value->val); -} - -sw_error_t -qca808x_ptp_event0_timestamp3_reg_get( - a_uint32_t dev_id, a_uint32_t phy_id, - union ptp_event0_timestamp3_reg_u *value) -{ - return qca808x_phy_ptp_mmd_read( - dev_id, - phy_id, QCA808X_PHY_MMD3_NUM, PTP_EVENT0_TIMESTAMP3_REG_ADDRESS, - &value->val); -} - -sw_error_t -qca808x_ptp_event0_timestamp3_reg_set( - a_uint32_t dev_id, a_uint32_t phy_id, - union ptp_event0_timestamp3_reg_u *value) -{ - return qca808x_phy_ptp_mmd_write( - dev_id, - phy_id, QCA808X_PHY_MMD3_NUM, PTP_EVENT0_TIMESTAMP3_REG_ADDRESS, - value->val); -} - -sw_error_t -qca808x_ptp_event0_timestamp4_reg_get( - a_uint32_t dev_id, a_uint32_t phy_id, - union ptp_event0_timestamp4_reg_u *value) -{ - return qca808x_phy_ptp_mmd_read( - dev_id, - phy_id, QCA808X_PHY_MMD3_NUM, PTP_EVENT0_TIMESTAMP4_REG_ADDRESS, - &value->val); -} - -sw_error_t -qca808x_ptp_event0_timestamp4_reg_set( - a_uint32_t dev_id, a_uint32_t phy_id, - union ptp_event0_timestamp4_reg_u *value) -{ - return qca808x_phy_ptp_mmd_write( - dev_id, - phy_id, QCA808X_PHY_MMD3_NUM, PTP_EVENT0_TIMESTAMP4_REG_ADDRESS, - value->val); -} - -sw_error_t -qca808x_ptp_event1_timestamp0_reg_get( - a_uint32_t dev_id, a_uint32_t phy_id, - union ptp_event1_timestamp0_reg_u *value) -{ - return qca808x_phy_ptp_mmd_read( - dev_id, - phy_id, QCA808X_PHY_MMD3_NUM, PTP_EVENT1_TIMESTAMP0_REG_ADDRESS, - &value->val); -} - -sw_error_t -qca808x_ptp_event1_timestamp0_reg_set( - a_uint32_t dev_id, a_uint32_t phy_id, - union ptp_event1_timestamp0_reg_u *value) -{ - return qca808x_phy_ptp_mmd_write( - dev_id, - phy_id, QCA808X_PHY_MMD3_NUM, PTP_EVENT1_TIMESTAMP0_REG_ADDRESS, - value->val); -} - -sw_error_t -qca808x_ptp_event1_timestamp1_reg_get( - a_uint32_t dev_id, a_uint32_t phy_id, - union ptp_event1_timestamp1_reg_u *value) -{ - return qca808x_phy_ptp_mmd_read( - dev_id, - phy_id, QCA808X_PHY_MMD3_NUM, PTP_EVENT1_TIMESTAMP1_REG_ADDRESS, - &value->val); -} - -sw_error_t -qca808x_ptp_event1_timestamp1_reg_set( - a_uint32_t dev_id, a_uint32_t phy_id, - union ptp_event1_timestamp1_reg_u *value) -{ - return qca808x_phy_ptp_mmd_write( - dev_id, - phy_id, QCA808X_PHY_MMD3_NUM, PTP_EVENT1_TIMESTAMP1_REG_ADDRESS, - value->val); -} - -sw_error_t -qca808x_ptp_event1_timestamp2_reg_get( - a_uint32_t dev_id, a_uint32_t phy_id, - union ptp_event1_timestamp2_reg_u *value) -{ - return qca808x_phy_ptp_mmd_read( - dev_id, - phy_id, QCA808X_PHY_MMD3_NUM, PTP_EVENT1_TIMESTAMP2_REG_ADDRESS, - &value->val); -} - -sw_error_t -qca808x_ptp_event1_timestamp2_reg_set( - a_uint32_t dev_id, a_uint32_t phy_id, - union ptp_event1_timestamp2_reg_u *value) -{ - return qca808x_phy_ptp_mmd_write( - dev_id, - phy_id, QCA808X_PHY_MMD3_NUM, PTP_EVENT1_TIMESTAMP2_REG_ADDRESS, - value->val); -} - -sw_error_t -qca808x_ptp_event1_timestamp3_reg_get( - a_uint32_t dev_id, a_uint32_t phy_id, - union ptp_event1_timestamp3_reg_u *value) -{ - return qca808x_phy_ptp_mmd_read( - dev_id, - phy_id, QCA808X_PHY_MMD3_NUM, PTP_EVENT1_TIMESTAMP3_REG_ADDRESS, - &value->val); -} - -sw_error_t -qca808x_ptp_event1_timestamp3_reg_set( - a_uint32_t dev_id, a_uint32_t phy_id, - union ptp_event1_timestamp3_reg_u *value) -{ - return qca808x_phy_ptp_mmd_write( - dev_id, - phy_id, QCA808X_PHY_MMD3_NUM, PTP_EVENT1_TIMESTAMP3_REG_ADDRESS, - value->val); -} - -sw_error_t -qca808x_ptp_event1_timestamp4_reg_get( - a_uint32_t dev_id, a_uint32_t phy_id, - union ptp_event1_timestamp4_reg_u *value) -{ - return qca808x_phy_ptp_mmd_read( - dev_id, - phy_id, QCA808X_PHY_MMD3_NUM, PTP_EVENT1_TIMESTAMP4_REG_ADDRESS, - &value->val); -} - -sw_error_t -qca808x_ptp_event1_timestamp4_reg_set( - a_uint32_t dev_id, a_uint32_t phy_id, - union ptp_event1_timestamp4_reg_u *value) -{ - return qca808x_phy_ptp_mmd_write( - dev_id, - phy_id, QCA808X_PHY_MMD3_NUM, PTP_EVENT1_TIMESTAMP4_REG_ADDRESS, - value->val); -} - -sw_error_t -qca808x_ptp_rx_seqid1_reg_get( - a_uint32_t dev_id, a_uint32_t phy_id, - union ptp_rx_seqid1_reg_u *value) -{ - return qca808x_phy_ptp_mmd_read( - dev_id, - phy_id, QCA808X_PHY_MMD3_NUM, PTP_RX_SEQID1_REG_ADDRESS, - &value->val); -} - -sw_error_t -qca808x_ptp_rx_seqid1_reg_set( - a_uint32_t dev_id, a_uint32_t phy_id, - union ptp_rx_seqid1_reg_u *value) -{ - return qca808x_phy_ptp_mmd_write( - dev_id, - phy_id, QCA808X_PHY_MMD3_NUM, PTP_RX_SEQID1_REG_ADDRESS, - value->val); -} - -sw_error_t -qca808x_ptp_rx_portid1_0_reg_get( - a_uint32_t dev_id, a_uint32_t phy_id, - union ptp_rx_portid1_0_reg_u *value) -{ - return qca808x_phy_ptp_mmd_read( - dev_id, - phy_id, QCA808X_PHY_MMD3_NUM, PTP_RX_PORTID1_0_REG_ADDRESS, - &value->val); -} - -sw_error_t -qca808x_ptp_rx_portid1_0_reg_set( - a_uint32_t dev_id, a_uint32_t phy_id, - union ptp_rx_portid1_0_reg_u *value) -{ - return qca808x_phy_ptp_mmd_write( - dev_id, - phy_id, QCA808X_PHY_MMD3_NUM, PTP_RX_PORTID1_0_REG_ADDRESS, - value->val); -} - -sw_error_t -qca808x_ptp_rx_portid1_1_reg_get( - a_uint32_t dev_id, a_uint32_t phy_id, - union ptp_rx_portid1_1_reg_u *value) -{ - return qca808x_phy_ptp_mmd_read( - dev_id, - phy_id, QCA808X_PHY_MMD3_NUM, PTP_RX_PORTID1_1_REG_ADDRESS, - &value->val); -} - -sw_error_t -qca808x_ptp_rx_portid1_1_reg_set( - a_uint32_t dev_id, a_uint32_t phy_id, - union ptp_rx_portid1_1_reg_u *value) -{ - return qca808x_phy_ptp_mmd_write( - dev_id, - phy_id, QCA808X_PHY_MMD3_NUM, PTP_RX_PORTID1_1_REG_ADDRESS, - value->val); -} - -sw_error_t -qca808x_ptp_rx_portid1_2_reg_get( - a_uint32_t dev_id, a_uint32_t phy_id, - union ptp_rx_portid1_2_reg_u *value) -{ - return qca808x_phy_ptp_mmd_read( - dev_id, - phy_id, QCA808X_PHY_MMD3_NUM, PTP_RX_PORTID1_2_REG_ADDRESS, - &value->val); -} - -sw_error_t -qca808x_ptp_rx_portid1_2_reg_set( - a_uint32_t dev_id, a_uint32_t phy_id, - union ptp_rx_portid1_2_reg_u *value) -{ - return qca808x_phy_ptp_mmd_write( - dev_id, - phy_id, QCA808X_PHY_MMD3_NUM, PTP_RX_PORTID1_2_REG_ADDRESS, - value->val); -} - -sw_error_t -qca808x_ptp_rx_portid1_3_reg_get( - a_uint32_t dev_id, a_uint32_t phy_id, - union ptp_rx_portid1_3_reg_u *value) -{ - return qca808x_phy_ptp_mmd_read( - dev_id, - phy_id, QCA808X_PHY_MMD3_NUM, PTP_RX_PORTID1_3_REG_ADDRESS, - &value->val); -} - -sw_error_t -qca808x_ptp_rx_portid1_3_reg_set( - a_uint32_t dev_id, a_uint32_t phy_id, - union ptp_rx_portid1_3_reg_u *value) -{ - return qca808x_phy_ptp_mmd_write( - dev_id, - phy_id, QCA808X_PHY_MMD3_NUM, PTP_RX_PORTID1_3_REG_ADDRESS, - value->val); -} - -sw_error_t -qca808x_ptp_rx_portid1_4_reg_get( - a_uint32_t dev_id, a_uint32_t phy_id, - union ptp_rx_portid1_4_reg_u *value) -{ - return qca808x_phy_ptp_mmd_read( - dev_id, - phy_id, QCA808X_PHY_MMD3_NUM, PTP_RX_PORTID1_4_REG_ADDRESS, - &value->val); -} - -sw_error_t -qca808x_ptp_rx_portid1_4_reg_set( - a_uint32_t dev_id, a_uint32_t phy_id, - union ptp_rx_portid1_4_reg_u *value) -{ - return qca808x_phy_ptp_mmd_write( - dev_id, - phy_id, QCA808X_PHY_MMD3_NUM, PTP_RX_PORTID1_4_REG_ADDRESS, - value->val); -} - -sw_error_t -qca808x_ptp_rx_ts1_0_reg_get( - a_uint32_t dev_id, a_uint32_t phy_id, - union ptp_rx_ts1_0_reg_u *value) -{ - return qca808x_phy_ptp_mmd_read( - dev_id, - phy_id, QCA808X_PHY_MMD3_NUM, PTP_RX_TS1_0_REG_ADDRESS, - &value->val); -} - -sw_error_t -qca808x_ptp_rx_ts1_0_reg_set( - a_uint32_t dev_id, a_uint32_t phy_id, - union ptp_rx_ts1_0_reg_u *value) -{ - return qca808x_phy_ptp_mmd_write( - dev_id, - phy_id, QCA808X_PHY_MMD3_NUM, PTP_RX_TS1_0_REG_ADDRESS, - value->val); -} - -sw_error_t -qca808x_ptp_rx_ts1_1_reg_get( - a_uint32_t dev_id, a_uint32_t phy_id, - union ptp_rx_ts1_1_reg_u *value) -{ - return qca808x_phy_ptp_mmd_read( - dev_id, - phy_id, QCA808X_PHY_MMD3_NUM, PTP_RX_TS1_1_REG_ADDRESS, - &value->val); -} - -sw_error_t -qca808x_ptp_rx_ts1_1_reg_set( - a_uint32_t dev_id, a_uint32_t phy_id, - union ptp_rx_ts1_1_reg_u *value) -{ - return qca808x_phy_ptp_mmd_write( - dev_id, - phy_id, QCA808X_PHY_MMD3_NUM, PTP_RX_TS1_1_REG_ADDRESS, - value->val); -} - -sw_error_t -qca808x_ptp_rx_ts1_2_reg_get( - a_uint32_t dev_id, a_uint32_t phy_id, - union ptp_rx_ts1_2_reg_u *value) -{ - return qca808x_phy_ptp_mmd_read( - dev_id, - phy_id, QCA808X_PHY_MMD3_NUM, PTP_RX_TS1_2_REG_ADDRESS, - &value->val); -} - -sw_error_t -qca808x_ptp_rx_ts1_2_reg_set( - a_uint32_t dev_id, a_uint32_t phy_id, - union ptp_rx_ts1_2_reg_u *value) -{ - return qca808x_phy_ptp_mmd_write( - dev_id, - phy_id, QCA808X_PHY_MMD3_NUM, PTP_RX_TS1_2_REG_ADDRESS, - value->val); -} - -sw_error_t -qca808x_ptp_rx_ts1_3_reg_get( - a_uint32_t dev_id, a_uint32_t phy_id, - union ptp_rx_ts1_3_reg_u *value) -{ - return qca808x_phy_ptp_mmd_read( - dev_id, - phy_id, QCA808X_PHY_MMD3_NUM, PTP_RX_TS1_3_REG_ADDRESS, - &value->val); -} - -sw_error_t -qca808x_ptp_rx_ts1_3_reg_set( - a_uint32_t dev_id, a_uint32_t phy_id, - union ptp_rx_ts1_3_reg_u *value) -{ - return qca808x_phy_ptp_mmd_write( - dev_id, - phy_id, QCA808X_PHY_MMD3_NUM, PTP_RX_TS1_3_REG_ADDRESS, - value->val); -} - -sw_error_t -qca808x_ptp_rx_ts1_4_reg_get( - a_uint32_t dev_id, a_uint32_t phy_id, - union ptp_rx_ts1_4_reg_u *value) -{ - return qca808x_phy_ptp_mmd_read( - dev_id, - phy_id, QCA808X_PHY_MMD3_NUM, PTP_RX_TS1_4_REG_ADDRESS, - &value->val); -} - -sw_error_t -qca808x_ptp_rx_ts1_4_reg_set( - a_uint32_t dev_id, a_uint32_t phy_id, - union ptp_rx_ts1_4_reg_u *value) -{ - return qca808x_phy_ptp_mmd_write( - dev_id, - phy_id, QCA808X_PHY_MMD3_NUM, PTP_RX_TS1_4_REG_ADDRESS, - value->val); -} - -sw_error_t -qca808x_ptp_rx_ts1_5_reg_get( - a_uint32_t dev_id, a_uint32_t phy_id, - union ptp_rx_ts1_5_reg_u *value) -{ - return qca808x_phy_ptp_mmd_read( - dev_id, - phy_id, QCA808X_PHY_MMD3_NUM, PTP_RX_TS1_5_REG_ADDRESS, - &value->val); -} - -sw_error_t -qca808x_ptp_rx_ts1_5_reg_set( - a_uint32_t dev_id, a_uint32_t phy_id, - union ptp_rx_ts1_5_reg_u *value) -{ - return qca808x_phy_ptp_mmd_write( - dev_id, - phy_id, QCA808X_PHY_MMD3_NUM, PTP_RX_TS1_5_REG_ADDRESS, - value->val); -} - -sw_error_t -qca808x_ptp_rx_ts1_6_reg_get( - a_uint32_t dev_id, a_uint32_t phy_id, - union ptp_rx_ts1_6_reg_u *value) -{ - return qca808x_phy_ptp_mmd_read( - dev_id, - phy_id, QCA808X_PHY_MMD3_NUM, PTP_RX_TS1_6_REG_ADDRESS, - &value->val); -} - -sw_error_t -qca808x_ptp_rx_ts1_6_reg_set( - a_uint32_t dev_id, a_uint32_t phy_id, - union ptp_rx_ts1_6_reg_u *value) -{ - return qca808x_phy_ptp_mmd_write( - dev_id, - phy_id, QCA808X_PHY_MMD3_NUM, PTP_RX_TS1_6_REG_ADDRESS, - value->val); -} - -sw_error_t -qca808x_ptp_rx_seqid2_reg_get( - a_uint32_t dev_id, a_uint32_t phy_id, - union ptp_rx_seqid2_reg_u *value) -{ - return qca808x_phy_ptp_mmd_read( - dev_id, - phy_id, QCA808X_PHY_MMD3_NUM, PTP_RX_SEQID2_REG_ADDRESS, - &value->val); -} - -sw_error_t -qca808x_ptp_rx_seqid2_reg_set( - a_uint32_t dev_id, a_uint32_t phy_id, - union ptp_rx_seqid2_reg_u *value) -{ - return qca808x_phy_ptp_mmd_write( - dev_id, - phy_id, QCA808X_PHY_MMD3_NUM, PTP_RX_SEQID2_REG_ADDRESS, - value->val); -} - -sw_error_t -qca808x_ptp_rx_portid2_0_reg_get( - a_uint32_t dev_id, a_uint32_t phy_id, - union ptp_rx_portid2_0_reg_u *value) -{ - return qca808x_phy_ptp_mmd_read( - dev_id, - phy_id, QCA808X_PHY_MMD3_NUM, PTP_RX_PORTID2_0_REG_ADDRESS, - &value->val); -} - -sw_error_t -qca808x_ptp_rx_portid2_0_reg_set( - a_uint32_t dev_id, a_uint32_t phy_id, - union ptp_rx_portid2_0_reg_u *value) -{ - return qca808x_phy_ptp_mmd_write( - dev_id, - phy_id, QCA808X_PHY_MMD3_NUM, PTP_RX_PORTID2_0_REG_ADDRESS, - value->val); -} - -sw_error_t -qca808x_ptp_rx_portid2_1_reg_get( - a_uint32_t dev_id, a_uint32_t phy_id, - union ptp_rx_portid2_1_reg_u *value) -{ - return qca808x_phy_ptp_mmd_read( - dev_id, - phy_id, QCA808X_PHY_MMD3_NUM, PTP_RX_PORTID2_1_REG_ADDRESS, - &value->val); -} - -sw_error_t -qca808x_ptp_rx_portid2_1_reg_set( - a_uint32_t dev_id, a_uint32_t phy_id, - union ptp_rx_portid2_1_reg_u *value) -{ - return qca808x_phy_ptp_mmd_write( - dev_id, - phy_id, QCA808X_PHY_MMD3_NUM, PTP_RX_PORTID2_1_REG_ADDRESS, - value->val); -} - -sw_error_t -qca808x_ptp_rx_portid2_2_reg_get( - a_uint32_t dev_id, a_uint32_t phy_id, - union ptp_rx_portid2_2_reg_u *value) -{ - return qca808x_phy_ptp_mmd_read( - dev_id, - phy_id, QCA808X_PHY_MMD3_NUM, PTP_RX_PORTID2_2_REG_ADDRESS, - &value->val); -} - -sw_error_t -qca808x_ptp_rx_portid2_2_reg_set( - a_uint32_t dev_id, a_uint32_t phy_id, - union ptp_rx_portid2_2_reg_u *value) -{ - return qca808x_phy_ptp_mmd_write( - dev_id, - phy_id, QCA808X_PHY_MMD3_NUM, PTP_RX_PORTID2_2_REG_ADDRESS, - value->val); -} - -sw_error_t -qca808x_ptp_rx_portid2_3_reg_get( - a_uint32_t dev_id, a_uint32_t phy_id, - union ptp_rx_portid2_3_reg_u *value) -{ - return qca808x_phy_ptp_mmd_read( - dev_id, - phy_id, QCA808X_PHY_MMD3_NUM, PTP_RX_PORTID2_3_REG_ADDRESS, - &value->val); -} - -sw_error_t -qca808x_ptp_rx_portid2_3_reg_set( - a_uint32_t dev_id, a_uint32_t phy_id, - union ptp_rx_portid2_3_reg_u *value) -{ - return qca808x_phy_ptp_mmd_write( - dev_id, - phy_id, QCA808X_PHY_MMD3_NUM, PTP_RX_PORTID2_3_REG_ADDRESS, - value->val); -} - -sw_error_t -qca808x_ptp_rx_portid2_4_reg_get( - a_uint32_t dev_id, a_uint32_t phy_id, - union ptp_rx_portid2_4_reg_u *value) -{ - return qca808x_phy_ptp_mmd_read( - dev_id, - phy_id, QCA808X_PHY_MMD3_NUM, PTP_RX_PORTID2_4_REG_ADDRESS, - &value->val); -} - -sw_error_t -qca808x_ptp_rx_portid2_4_reg_set( - a_uint32_t dev_id, a_uint32_t phy_id, - union ptp_rx_portid2_4_reg_u *value) -{ - return qca808x_phy_ptp_mmd_write( - dev_id, - phy_id, QCA808X_PHY_MMD3_NUM, PTP_RX_PORTID2_4_REG_ADDRESS, - value->val); -} - -sw_error_t -qca808x_ptp_rx_ts2_0_reg_get( - a_uint32_t dev_id, a_uint32_t phy_id, - union ptp_rx_ts2_0_reg_u *value) -{ - return qca808x_phy_ptp_mmd_read( - dev_id, - phy_id, QCA808X_PHY_MMD3_NUM, PTP_RX_TS2_0_REG_ADDRESS, - &value->val); -} - -sw_error_t -qca808x_ptp_rx_ts2_0_reg_set( - a_uint32_t dev_id, a_uint32_t phy_id, - union ptp_rx_ts2_0_reg_u *value) -{ - return qca808x_phy_ptp_mmd_write( - dev_id, - phy_id, QCA808X_PHY_MMD3_NUM, PTP_RX_TS2_0_REG_ADDRESS, - value->val); -} - -sw_error_t -qca808x_ptp_rx_ts2_1_reg_get( - a_uint32_t dev_id, a_uint32_t phy_id, - union ptp_rx_ts2_1_reg_u *value) -{ - return qca808x_phy_ptp_mmd_read( - dev_id, - phy_id, QCA808X_PHY_MMD3_NUM, PTP_RX_TS2_1_REG_ADDRESS, - &value->val); -} - -sw_error_t -qca808x_ptp_rx_ts2_1_reg_set( - a_uint32_t dev_id, a_uint32_t phy_id, - union ptp_rx_ts2_1_reg_u *value) -{ - return qca808x_phy_ptp_mmd_write( - dev_id, - phy_id, QCA808X_PHY_MMD3_NUM, PTP_RX_TS2_1_REG_ADDRESS, - value->val); -} - -sw_error_t -qca808x_ptp_rx_ts2_2_reg_get( - a_uint32_t dev_id, a_uint32_t phy_id, - union ptp_rx_ts2_2_reg_u *value) -{ - return qca808x_phy_ptp_mmd_read( - dev_id, - phy_id, QCA808X_PHY_MMD3_NUM, PTP_RX_TS2_2_REG_ADDRESS, - &value->val); -} - -sw_error_t -qca808x_ptp_rx_ts2_2_reg_set( - a_uint32_t dev_id, a_uint32_t phy_id, - union ptp_rx_ts2_2_reg_u *value) -{ - return qca808x_phy_ptp_mmd_write( - dev_id, - phy_id, QCA808X_PHY_MMD3_NUM, PTP_RX_TS2_2_REG_ADDRESS, - value->val); -} - -sw_error_t -qca808x_ptp_rx_ts2_3_reg_get( - a_uint32_t dev_id, a_uint32_t phy_id, - union ptp_rx_ts2_3_reg_u *value) -{ - return qca808x_phy_ptp_mmd_read( - dev_id, - phy_id, QCA808X_PHY_MMD3_NUM, PTP_RX_TS2_3_REG_ADDRESS, - &value->val); -} - -sw_error_t -qca808x_ptp_rx_ts2_3_reg_set( - a_uint32_t dev_id, a_uint32_t phy_id, - union ptp_rx_ts2_3_reg_u *value) -{ - return qca808x_phy_ptp_mmd_write( - dev_id, - phy_id, QCA808X_PHY_MMD3_NUM, PTP_RX_TS2_3_REG_ADDRESS, - value->val); -} - -sw_error_t -qca808x_ptp_rx_ts2_4_reg_get( - a_uint32_t dev_id, a_uint32_t phy_id, - union ptp_rx_ts2_4_reg_u *value) -{ - return qca808x_phy_ptp_mmd_read( - dev_id, - phy_id, QCA808X_PHY_MMD3_NUM, PTP_RX_TS2_4_REG_ADDRESS, - &value->val); -} - -sw_error_t -qca808x_ptp_rx_ts2_4_reg_set( - a_uint32_t dev_id, a_uint32_t phy_id, - union ptp_rx_ts2_4_reg_u *value) -{ - return qca808x_phy_ptp_mmd_write( - dev_id, - phy_id, QCA808X_PHY_MMD3_NUM, PTP_RX_TS2_4_REG_ADDRESS, - value->val); -} - -sw_error_t -qca808x_ptp_rx_ts2_5_reg_get( - a_uint32_t dev_id, a_uint32_t phy_id, - union ptp_rx_ts2_5_reg_u *value) -{ - return qca808x_phy_ptp_mmd_read( - dev_id, - phy_id, QCA808X_PHY_MMD3_NUM, PTP_RX_TS2_5_REG_ADDRESS, - &value->val); -} - -sw_error_t -qca808x_ptp_rx_ts2_5_reg_set( - a_uint32_t dev_id, a_uint32_t phy_id, - union ptp_rx_ts2_5_reg_u *value) -{ - return qca808x_phy_ptp_mmd_write( - dev_id, - phy_id, QCA808X_PHY_MMD3_NUM, PTP_RX_TS2_5_REG_ADDRESS, - value->val); -} - -sw_error_t -qca808x_ptp_rx_ts2_6_reg_get( - a_uint32_t dev_id, a_uint32_t phy_id, - union ptp_rx_ts2_6_reg_u *value) -{ - return qca808x_phy_ptp_mmd_read( - dev_id, - phy_id, QCA808X_PHY_MMD3_NUM, PTP_RX_TS2_6_REG_ADDRESS, - &value->val); -} - -sw_error_t -qca808x_ptp_rx_ts2_6_reg_set( - a_uint32_t dev_id, a_uint32_t phy_id, - union ptp_rx_ts2_6_reg_u *value) -{ - return qca808x_phy_ptp_mmd_write( - dev_id, - phy_id, QCA808X_PHY_MMD3_NUM, PTP_RX_TS2_6_REG_ADDRESS, - value->val); -} - -sw_error_t -qca808x_ptp_rx_seqid3_reg_get( - a_uint32_t dev_id, a_uint32_t phy_id, - union ptp_rx_seqid3_reg_u *value) -{ - return qca808x_phy_ptp_mmd_read( - dev_id, - phy_id, QCA808X_PHY_MMD3_NUM, PTP_RX_SEQID3_REG_ADDRESS, - &value->val); -} - -sw_error_t -qca808x_ptp_rx_seqid3_reg_set( - a_uint32_t dev_id, a_uint32_t phy_id, - union ptp_rx_seqid3_reg_u *value) -{ - return qca808x_phy_ptp_mmd_write( - dev_id, - phy_id, QCA808X_PHY_MMD3_NUM, PTP_RX_SEQID3_REG_ADDRESS, - value->val); -} - -sw_error_t -qca808x_ptp_rx_portid3_0_reg_get( - a_uint32_t dev_id, a_uint32_t phy_id, - union ptp_rx_portid3_0_reg_u *value) -{ - return qca808x_phy_ptp_mmd_read( - dev_id, - phy_id, QCA808X_PHY_MMD3_NUM, PTP_RX_PORTID3_0_REG_ADDRESS, - &value->val); -} - -sw_error_t -qca808x_ptp_rx_portid3_0_reg_set( - a_uint32_t dev_id, a_uint32_t phy_id, - union ptp_rx_portid3_0_reg_u *value) -{ - return qca808x_phy_ptp_mmd_write( - dev_id, - phy_id, QCA808X_PHY_MMD3_NUM, PTP_RX_PORTID3_0_REG_ADDRESS, - value->val); -} - -sw_error_t -qca808x_ptp_rx_portid3_1_reg_get( - a_uint32_t dev_id, a_uint32_t phy_id, - union ptp_rx_portid3_1_reg_u *value) -{ - return qca808x_phy_ptp_mmd_read( - dev_id, - phy_id, QCA808X_PHY_MMD3_NUM, PTP_RX_PORTID3_1_REG_ADDRESS, - &value->val); -} - -sw_error_t -qca808x_ptp_rx_portid3_1_reg_set( - a_uint32_t dev_id, a_uint32_t phy_id, - union ptp_rx_portid3_1_reg_u *value) -{ - return qca808x_phy_ptp_mmd_write( - dev_id, - phy_id, QCA808X_PHY_MMD3_NUM, PTP_RX_PORTID3_1_REG_ADDRESS, - value->val); -} - -sw_error_t -qca808x_ptp_rx_portid3_2_reg_get( - a_uint32_t dev_id, a_uint32_t phy_id, - union ptp_rx_portid3_2_reg_u *value) -{ - return qca808x_phy_ptp_mmd_read( - dev_id, - phy_id, QCA808X_PHY_MMD3_NUM, PTP_RX_PORTID3_2_REG_ADDRESS, - &value->val); -} - -sw_error_t -qca808x_ptp_rx_portid3_2_reg_set( - a_uint32_t dev_id, a_uint32_t phy_id, - union ptp_rx_portid3_2_reg_u *value) -{ - return qca808x_phy_ptp_mmd_write( - dev_id, - phy_id, QCA808X_PHY_MMD3_NUM, PTP_RX_PORTID3_2_REG_ADDRESS, - value->val); -} - -sw_error_t -qca808x_ptp_rx_portid3_3_reg_get( - a_uint32_t dev_id, a_uint32_t phy_id, - union ptp_rx_portid3_3_reg_u *value) -{ - return qca808x_phy_ptp_mmd_read( - dev_id, - phy_id, QCA808X_PHY_MMD3_NUM, PTP_RX_PORTID3_3_REG_ADDRESS, - &value->val); -} - -sw_error_t -qca808x_ptp_rx_portid3_3_reg_set( - a_uint32_t dev_id, a_uint32_t phy_id, - union ptp_rx_portid3_3_reg_u *value) -{ - return qca808x_phy_ptp_mmd_write( - dev_id, - phy_id, QCA808X_PHY_MMD3_NUM, PTP_RX_PORTID3_3_REG_ADDRESS, - value->val); -} - -sw_error_t -qca808x_ptp_rx_portid3_4_reg_get( - a_uint32_t dev_id, a_uint32_t phy_id, - union ptp_rx_portid3_4_reg_u *value) -{ - return qca808x_phy_ptp_mmd_read( - dev_id, - phy_id, QCA808X_PHY_MMD3_NUM, PTP_RX_PORTID3_4_REG_ADDRESS, - &value->val); -} - -sw_error_t -qca808x_ptp_rx_portid3_4_reg_set( - a_uint32_t dev_id, a_uint32_t phy_id, - union ptp_rx_portid3_4_reg_u *value) -{ - return qca808x_phy_ptp_mmd_write( - dev_id, - phy_id, QCA808X_PHY_MMD3_NUM, PTP_RX_PORTID3_4_REG_ADDRESS, - value->val); -} - -sw_error_t -qca808x_ptp_rx_ts3_0_reg_get( - a_uint32_t dev_id, a_uint32_t phy_id, - union ptp_rx_ts3_0_reg_u *value) -{ - return qca808x_phy_ptp_mmd_read( - dev_id, - phy_id, QCA808X_PHY_MMD3_NUM, PTP_RX_TS3_0_REG_ADDRESS, - &value->val); -} - -sw_error_t -qca808x_ptp_rx_ts3_0_reg_set( - a_uint32_t dev_id, a_uint32_t phy_id, - union ptp_rx_ts3_0_reg_u *value) -{ - return qca808x_phy_ptp_mmd_write( - dev_id, - phy_id, QCA808X_PHY_MMD3_NUM, PTP_RX_TS3_0_REG_ADDRESS, - value->val); -} - -sw_error_t -qca808x_ptp_rx_ts3_1_reg_get( - a_uint32_t dev_id, a_uint32_t phy_id, - union ptp_rx_ts3_1_reg_u *value) -{ - return qca808x_phy_ptp_mmd_read( - dev_id, - phy_id, QCA808X_PHY_MMD3_NUM, PTP_RX_TS3_1_REG_ADDRESS, - &value->val); -} - -sw_error_t -qca808x_ptp_rx_ts3_1_reg_set( - a_uint32_t dev_id, a_uint32_t phy_id, - union ptp_rx_ts3_1_reg_u *value) -{ - return qca808x_phy_ptp_mmd_write( - dev_id, - phy_id, QCA808X_PHY_MMD3_NUM, PTP_RX_TS3_1_REG_ADDRESS, - value->val); -} - -sw_error_t -qca808x_ptp_rx_ts3_2_reg_get( - a_uint32_t dev_id, a_uint32_t phy_id, - union ptp_rx_ts3_2_reg_u *value) -{ - return qca808x_phy_ptp_mmd_read( - dev_id, - phy_id, QCA808X_PHY_MMD3_NUM, PTP_RX_TS3_2_REG_ADDRESS, - &value->val); -} - -sw_error_t -qca808x_ptp_rx_ts3_2_reg_set( - a_uint32_t dev_id, a_uint32_t phy_id, - union ptp_rx_ts3_2_reg_u *value) -{ - return qca808x_phy_ptp_mmd_write( - dev_id, - phy_id, QCA808X_PHY_MMD3_NUM, PTP_RX_TS3_2_REG_ADDRESS, - value->val); -} - -sw_error_t -qca808x_ptp_rx_ts3_3_reg_get( - a_uint32_t dev_id, a_uint32_t phy_id, - union ptp_rx_ts3_3_reg_u *value) -{ - return qca808x_phy_ptp_mmd_read( - dev_id, - phy_id, QCA808X_PHY_MMD3_NUM, PTP_RX_TS3_3_REG_ADDRESS, - &value->val); -} - -sw_error_t -qca808x_ptp_rx_ts3_3_reg_set( - a_uint32_t dev_id, a_uint32_t phy_id, - union ptp_rx_ts3_3_reg_u *value) -{ - return qca808x_phy_ptp_mmd_write( - dev_id, - phy_id, QCA808X_PHY_MMD3_NUM, PTP_RX_TS3_3_REG_ADDRESS, - value->val); -} - -sw_error_t -qca808x_ptp_rx_ts3_4_reg_get( - a_uint32_t dev_id, a_uint32_t phy_id, - union ptp_rx_ts3_4_reg_u *value) -{ - return qca808x_phy_ptp_mmd_read( - dev_id, - phy_id, QCA808X_PHY_MMD3_NUM, PTP_RX_TS3_4_REG_ADDRESS, - &value->val); -} - -sw_error_t -qca808x_ptp_rx_ts3_4_reg_set( - a_uint32_t dev_id, a_uint32_t phy_id, - union ptp_rx_ts3_4_reg_u *value) -{ - return qca808x_phy_ptp_mmd_write( - dev_id, - phy_id, QCA808X_PHY_MMD3_NUM, PTP_RX_TS3_4_REG_ADDRESS, - value->val); -} - -sw_error_t -qca808x_ptp_rx_ts3_5_reg_get( - a_uint32_t dev_id, a_uint32_t phy_id, - union ptp_rx_ts3_5_reg_u *value) -{ - return qca808x_phy_ptp_mmd_read( - dev_id, - phy_id, QCA808X_PHY_MMD3_NUM, PTP_RX_TS3_5_REG_ADDRESS, - &value->val); -} - -sw_error_t -qca808x_ptp_rx_ts3_5_reg_set( - a_uint32_t dev_id, a_uint32_t phy_id, - union ptp_rx_ts3_5_reg_u *value) -{ - return qca808x_phy_ptp_mmd_write( - dev_id, - phy_id, QCA808X_PHY_MMD3_NUM, PTP_RX_TS3_5_REG_ADDRESS, - value->val); -} - -sw_error_t -qca808x_ptp_rx_ts3_6_reg_get( - a_uint32_t dev_id, a_uint32_t phy_id, - union ptp_rx_ts3_6_reg_u *value) -{ - return qca808x_phy_ptp_mmd_read( - dev_id, - phy_id, QCA808X_PHY_MMD3_NUM, PTP_RX_TS3_6_REG_ADDRESS, - &value->val); -} - -sw_error_t -qca808x_ptp_rx_ts3_6_reg_set( - a_uint32_t dev_id, a_uint32_t phy_id, - union ptp_rx_ts3_6_reg_u *value) -{ - return qca808x_phy_ptp_mmd_write( - dev_id, - phy_id, QCA808X_PHY_MMD3_NUM, PTP_RX_TS3_6_REG_ADDRESS, - value->val); -} - -sw_error_t -qca808x_ptp_imr_reg_mask_bmp_get( - a_uint32_t dev_id, a_uint32_t phy_id, - a_uint32_t *value) -{ - union ptp_imr_reg_u reg_val; - sw_error_t ret = SW_OK; - - ret = qca808x_ptp_imr_reg_get(dev_id, phy_id, ®_val); - *value = reg_val.bf.mask_bmp; - return ret; -} - -sw_error_t -qca808x_ptp_imr_reg_mask_bmp_set( - a_uint32_t dev_id, a_uint32_t phy_id, - a_uint32_t value) -{ - union ptp_imr_reg_u reg_val; - sw_error_t ret = SW_OK; - - ret = qca808x_ptp_imr_reg_get(dev_id, phy_id, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.mask_bmp = value; - ret = qca808x_ptp_imr_reg_set(dev_id, phy_id, ®_val); - return ret; -} - -sw_error_t -qca808x_ptp_isr_reg_status_bmp_get( - a_uint32_t dev_id, a_uint32_t phy_id, - a_uint32_t *value) -{ - union ptp_isr_reg_u reg_val; - sw_error_t ret = SW_OK; - - ret = qca808x_ptp_isr_reg_get(dev_id, phy_id, ®_val); - *value = reg_val.bf.status_bmp; - return ret; -} - -sw_error_t -qca808x_ptp_isr_reg_status_bmp_set( - a_uint32_t dev_id, a_uint32_t phy_id, - a_uint32_t value) -{ - union ptp_isr_reg_u reg_val; - sw_error_t ret = SW_OK; - - ret = qca808x_ptp_isr_reg_get(dev_id, phy_id, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.status_bmp = value; - ret = qca808x_ptp_isr_reg_set(dev_id, phy_id, ®_val); - return ret; -} - -sw_error_t -qca808x_ptp_hw_enable_reg_ptp_hw_enable_get( - a_uint32_t dev_id, a_uint32_t phy_id, - a_uint32_t *value) -{ - union ptp_hw_enable_reg_u reg_val; - sw_error_t ret = SW_OK; - - ret = qca808x_ptp_hw_enable_reg_get(dev_id, phy_id, ®_val); - *value = reg_val.bf.ptp_hw_enable; - return ret; -} - -sw_error_t -qca808x_ptp_hw_enable_reg_ptp_hw_enable_set( - a_uint32_t dev_id, a_uint32_t phy_id, - a_uint32_t value) -{ - union ptp_hw_enable_reg_u reg_val; - sw_error_t ret = SW_OK; - - ret = qca808x_ptp_hw_enable_reg_get(dev_id, phy_id, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.ptp_hw_enable = value; - ret = qca808x_ptp_hw_enable_reg_set(dev_id, phy_id, ®_val); - return ret; -} - -sw_error_t -qca808x_ptp_main_conf_reg_ts_attach_mode_get( - a_uint32_t dev_id, a_uint32_t phy_id, - a_uint32_t *value) -{ - union ptp_main_conf_reg_u reg_val; - sw_error_t ret = SW_OK; - - ret = qca808x_ptp_main_conf_reg_get(dev_id, phy_id, ®_val); - *value = reg_val.bf.ts_attach_mode; - return ret; -} - -sw_error_t -qca808x_ptp_main_conf_reg_ts_attach_mode_set( - a_uint32_t dev_id, a_uint32_t phy_id, - a_uint32_t value) -{ - union ptp_main_conf_reg_u reg_val; - sw_error_t ret = SW_OK; - - ret = qca808x_ptp_main_conf_reg_get(dev_id, phy_id, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.ts_attach_mode = value; - ret = qca808x_ptp_main_conf_reg_set(dev_id, phy_id, ®_val); - return ret; -} - -sw_error_t -qca808x_ptp_main_conf_reg_ptp_clk_sel_get( - a_uint32_t dev_id, a_uint32_t phy_id, - a_uint32_t *value) -{ - union ptp_main_conf_reg_u reg_val; - sw_error_t ret = SW_OK; - - ret = qca808x_ptp_main_conf_reg_get(dev_id, phy_id, ®_val); - *value = reg_val.bf.ptp_clk_sel; - return ret; -} - -sw_error_t -qca808x_ptp_main_conf_reg_ptp_clk_sel_set( - a_uint32_t dev_id, a_uint32_t phy_id, - a_uint32_t value) -{ - union ptp_main_conf_reg_u reg_val; - sw_error_t ret = SW_OK; - - ret = qca808x_ptp_main_conf_reg_get(dev_id, phy_id, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.ptp_clk_sel = value; - ret = qca808x_ptp_main_conf_reg_set(dev_id, phy_id, ®_val); - return ret; -} - -sw_error_t -qca808x_ptp_main_conf_reg_disable_1588_phy_get( - a_uint32_t dev_id, a_uint32_t phy_id, - a_uint32_t *value) -{ - union ptp_main_conf_reg_u reg_val; - sw_error_t ret = SW_OK; - - ret = qca808x_ptp_main_conf_reg_get(dev_id, phy_id, ®_val); - *value = reg_val.bf.disable_1588_phy; - return ret; -} - -sw_error_t -qca808x_ptp_main_conf_reg_disable_1588_phy_set( - a_uint32_t dev_id, a_uint32_t phy_id, - a_uint32_t value) -{ - union ptp_main_conf_reg_u reg_val; - sw_error_t ret = SW_OK; - - ret = qca808x_ptp_main_conf_reg_get(dev_id, phy_id, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.disable_1588_phy = value; - ret = qca808x_ptp_main_conf_reg_set(dev_id, phy_id, ®_val); - return ret; -} - -sw_error_t -qca808x_ptp_main_conf_reg_attach_crc_recal_get( - a_uint32_t dev_id, a_uint32_t phy_id, - a_uint32_t *value) -{ - union ptp_main_conf_reg_u reg_val; - sw_error_t ret = SW_OK; - - ret = qca808x_ptp_main_conf_reg_get(dev_id, phy_id, ®_val); - *value = reg_val.bf.attach_crc_recal; - return ret; -} - -sw_error_t -qca808x_ptp_main_conf_reg_attach_crc_recal_set( - a_uint32_t dev_id, a_uint32_t phy_id, - a_uint32_t value) -{ - union ptp_main_conf_reg_u reg_val; - sw_error_t ret = SW_OK; - - ret = qca808x_ptp_main_conf_reg_get(dev_id, phy_id, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.attach_crc_recal = value; - ret = qca808x_ptp_main_conf_reg_set(dev_id, phy_id, ®_val); - return ret; -} - -sw_error_t -qca808x_ptp_main_conf_reg_ipv4_force_checksum_zero_get( - a_uint32_t dev_id, a_uint32_t phy_id, - a_uint32_t *value) -{ - union ptp_main_conf_reg_u reg_val; - sw_error_t ret = SW_OK; - - ret = qca808x_ptp_main_conf_reg_get(dev_id, phy_id, ®_val); - *value = reg_val.bf.ipv4_force_checksum_zero; - return ret; -} - -sw_error_t -qca808x_ptp_main_conf_reg_ipv4_force_checksum_zero_set( - a_uint32_t dev_id, a_uint32_t phy_id, - a_uint32_t value) -{ - union ptp_main_conf_reg_u reg_val; - sw_error_t ret = SW_OK; - - ret = qca808x_ptp_main_conf_reg_get(dev_id, phy_id, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.ipv4_force_checksum_zero = value; - ret = qca808x_ptp_main_conf_reg_set(dev_id, phy_id, ®_val); - return ret; -} - -sw_error_t -qca808x_ptp_main_conf_reg_ipv6_embed_force_checksum_zero_get( - a_uint32_t dev_id, a_uint32_t phy_id, - a_uint32_t *value) -{ - union ptp_main_conf_reg_u reg_val; - sw_error_t ret = SW_OK; - - ret = qca808x_ptp_main_conf_reg_get(dev_id, phy_id, ®_val); - *value = reg_val.bf.ipv6_embed_force_checksum_zero; - return ret; -} - -sw_error_t -qca808x_ptp_main_conf_reg_ipv6_embed_force_checksum_zero_set( - a_uint32_t dev_id, a_uint32_t phy_id, - a_uint32_t value) -{ - union ptp_main_conf_reg_u reg_val; - sw_error_t ret = SW_OK; - - ret = qca808x_ptp_main_conf_reg_get(dev_id, phy_id, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.ipv6_embed_force_checksum_zero = value; - ret = qca808x_ptp_main_conf_reg_set(dev_id, phy_id, ®_val); - return ret; -} - -sw_error_t -qca808x_ptp_main_conf_reg_ptp_bypass_get( - a_uint32_t dev_id, a_uint32_t phy_id, - a_uint32_t *value) -{ - union ptp_main_conf_reg_u reg_val; - sw_error_t ret = SW_OK; - - ret = qca808x_ptp_main_conf_reg_get(dev_id, phy_id, ®_val); - *value = reg_val.bf.ptp_bypass; - return ret; -} - -sw_error_t -qca808x_ptp_main_conf_reg_ptp_bypass_set( - a_uint32_t dev_id, a_uint32_t phy_id, - a_uint32_t value) -{ - union ptp_main_conf_reg_u reg_val; - sw_error_t ret = SW_OK; - - ret = qca808x_ptp_main_conf_reg_get(dev_id, phy_id, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.ptp_bypass = value; - ret = qca808x_ptp_main_conf_reg_set(dev_id, phy_id, ®_val); - return ret; -} - -sw_error_t -qca808x_ptp_main_conf_reg_wol_en_get( - a_uint32_t dev_id, a_uint32_t phy_id, - a_uint32_t *value) -{ - union ptp_main_conf_reg_u reg_val; - sw_error_t ret = SW_OK; - - ret = qca808x_ptp_main_conf_reg_get(dev_id, phy_id, ®_val); - *value = reg_val.bf.wol_en; - return ret; -} - -sw_error_t -qca808x_ptp_main_conf_reg_wol_en_set( - a_uint32_t dev_id, a_uint32_t phy_id, - a_uint32_t value) -{ - union ptp_main_conf_reg_u reg_val; - sw_error_t ret = SW_OK; - - ret = qca808x_ptp_main_conf_reg_get(dev_id, phy_id, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.wol_en = value; - ret = qca808x_ptp_main_conf_reg_set(dev_id, phy_id, ®_val); - return ret; -} - -sw_error_t -qca808x_ptp_main_conf_reg_ptp_clock_mode_get( - a_uint32_t dev_id, a_uint32_t phy_id, - a_uint32_t *value) -{ - union ptp_main_conf_reg_u reg_val; - sw_error_t ret = SW_OK; - - ret = qca808x_ptp_main_conf_reg_get(dev_id, phy_id, ®_val); - *value = reg_val.bf.ptp_clock_mode; - return ret; -} - -sw_error_t -qca808x_ptp_main_conf_reg_ptp_clock_mode_set( - a_uint32_t dev_id, a_uint32_t phy_id, - a_uint32_t value) -{ - union ptp_main_conf_reg_u reg_val; - sw_error_t ret = SW_OK; - - ret = qca808x_ptp_main_conf_reg_get(dev_id, phy_id, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.ptp_clock_mode = value; - ret = qca808x_ptp_main_conf_reg_set(dev_id, phy_id, ®_val); - return ret; -} - -sw_error_t -qca808x_ptp_rx_seqid0_reg_rx_seqid_get( - a_uint32_t dev_id, a_uint32_t phy_id, - a_uint32_t *value) -{ - union ptp_rx_seqid0_reg_u reg_val; - sw_error_t ret = SW_OK; - - ret = qca808x_ptp_rx_seqid0_reg_get(dev_id, phy_id, ®_val); - *value = reg_val.bf.rx_seqid; - return ret; -} - -sw_error_t -qca808x_ptp_rx_seqid0_reg_rx_seqid_set( - a_uint32_t dev_id, a_uint32_t phy_id, - a_uint32_t value) -{ - union ptp_rx_seqid0_reg_u reg_val; - sw_error_t ret = SW_OK; - - ret = qca808x_ptp_rx_seqid0_reg_get(dev_id, phy_id, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.rx_seqid = value; - ret = qca808x_ptp_rx_seqid0_reg_set(dev_id, phy_id, ®_val); - return ret; -} - -sw_error_t -qca808x_ptp_rx_portid0_0_reg_rx_portid_get( - a_uint32_t dev_id, a_uint32_t phy_id, - a_uint32_t *value) -{ - union ptp_rx_portid0_0_reg_u reg_val; - sw_error_t ret = SW_OK; - - ret = qca808x_ptp_rx_portid0_0_reg_get(dev_id, phy_id, ®_val); - *value = reg_val.bf.rx_portid; - return ret; -} - -sw_error_t -qca808x_ptp_rx_portid0_0_reg_rx_portid_set( - a_uint32_t dev_id, a_uint32_t phy_id, - a_uint32_t value) -{ - union ptp_rx_portid0_0_reg_u reg_val; - sw_error_t ret = SW_OK; - - ret = qca808x_ptp_rx_portid0_0_reg_get(dev_id, phy_id, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.rx_portid = value; - ret = qca808x_ptp_rx_portid0_0_reg_set(dev_id, phy_id, ®_val); - return ret; -} - -sw_error_t -qca808x_ptp_rx_portid0_1_reg_rx_portid_get( - a_uint32_t dev_id, a_uint32_t phy_id, - a_uint32_t *value) -{ - union ptp_rx_portid0_1_reg_u reg_val; - sw_error_t ret = SW_OK; - - ret = qca808x_ptp_rx_portid0_1_reg_get(dev_id, phy_id, ®_val); - *value = reg_val.bf.rx_portid; - return ret; -} - -sw_error_t -qca808x_ptp_rx_portid0_1_reg_rx_portid_set( - a_uint32_t dev_id, a_uint32_t phy_id, - a_uint32_t value) -{ - union ptp_rx_portid0_1_reg_u reg_val; - sw_error_t ret = SW_OK; - - ret = qca808x_ptp_rx_portid0_1_reg_get(dev_id, phy_id, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.rx_portid = value; - ret = qca808x_ptp_rx_portid0_1_reg_set(dev_id, phy_id, ®_val); - return ret; -} - -sw_error_t -qca808x_ptp_rx_portid0_2_reg_rx_portid_get( - a_uint32_t dev_id, a_uint32_t phy_id, - a_uint32_t *value) -{ - union ptp_rx_portid0_2_reg_u reg_val; - sw_error_t ret = SW_OK; - - ret = qca808x_ptp_rx_portid0_2_reg_get(dev_id, phy_id, ®_val); - *value = reg_val.bf.rx_portid; - return ret; -} - -sw_error_t -qca808x_ptp_rx_portid0_2_reg_rx_portid_set( - a_uint32_t dev_id, a_uint32_t phy_id, - a_uint32_t value) -{ - union ptp_rx_portid0_2_reg_u reg_val; - sw_error_t ret = SW_OK; - - ret = qca808x_ptp_rx_portid0_2_reg_get(dev_id, phy_id, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.rx_portid = value; - ret = qca808x_ptp_rx_portid0_2_reg_set(dev_id, phy_id, ®_val); - return ret; -} - -sw_error_t -qca808x_ptp_rx_portid0_3_reg_rx_portid_get( - a_uint32_t dev_id, a_uint32_t phy_id, - a_uint32_t *value) -{ - union ptp_rx_portid0_3_reg_u reg_val; - sw_error_t ret = SW_OK; - - ret = qca808x_ptp_rx_portid0_3_reg_get(dev_id, phy_id, ®_val); - *value = reg_val.bf.rx_portid; - return ret; -} - -sw_error_t -qca808x_ptp_rx_portid0_3_reg_rx_portid_set( - a_uint32_t dev_id, a_uint32_t phy_id, - a_uint32_t value) -{ - union ptp_rx_portid0_3_reg_u reg_val; - sw_error_t ret = SW_OK; - - ret = qca808x_ptp_rx_portid0_3_reg_get(dev_id, phy_id, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.rx_portid = value; - ret = qca808x_ptp_rx_portid0_3_reg_set(dev_id, phy_id, ®_val); - return ret; -} - -sw_error_t -qca808x_ptp_rx_portid0_4_reg_rx_portid_get( - a_uint32_t dev_id, a_uint32_t phy_id, - a_uint32_t *value) -{ - union ptp_rx_portid0_4_reg_u reg_val; - sw_error_t ret = SW_OK; - - ret = qca808x_ptp_rx_portid0_4_reg_get(dev_id, phy_id, ®_val); - *value = reg_val.bf.rx_portid; - return ret; -} - -sw_error_t -qca808x_ptp_rx_portid0_4_reg_rx_portid_set( - a_uint32_t dev_id, a_uint32_t phy_id, - a_uint32_t value) -{ - union ptp_rx_portid0_4_reg_u reg_val; - sw_error_t ret = SW_OK; - - ret = qca808x_ptp_rx_portid0_4_reg_get(dev_id, phy_id, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.rx_portid = value; - ret = qca808x_ptp_rx_portid0_4_reg_set(dev_id, phy_id, ®_val); - return ret; -} - -sw_error_t -qca808x_ptp_rtc_clk_reg_rtc_clk_selection_get( - a_uint32_t dev_id, a_uint32_t phy_id, - a_uint32_t *value) -{ - union ptp_rtc_clk_reg_u reg_val; - sw_error_t ret = SW_OK; - - ret = qca808x_ptp_rtc_clk_reg_get(dev_id, phy_id, ®_val); - *value = reg_val.bf.rtc_clk_selection; - return ret; -} - -sw_error_t -qca808x_ptp_rtc_clk_reg_rtc_clk_selection_set( - a_uint32_t dev_id, a_uint32_t phy_id, - a_uint32_t value) -{ - union ptp_rtc_clk_reg_u reg_val; - sw_error_t ret = SW_OK; - - ret = qca808x_ptp_rtc_clk_reg_get(dev_id, phy_id, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.rtc_clk_selection = value; - ret = qca808x_ptp_rtc_clk_reg_set(dev_id, phy_id, ®_val); - return ret; -} - -sw_error_t -qca808x_ptp_rx_ts0_0_reg_rx_ts_sec_get( - a_uint32_t dev_id, a_uint32_t phy_id, - a_uint32_t *value) -{ - union ptp_rx_ts0_0_reg_u reg_val; - sw_error_t ret = SW_OK; - - ret = qca808x_ptp_rx_ts0_0_reg_get(dev_id, phy_id, ®_val); - *value = reg_val.bf.rx_ts_sec; - return ret; -} - -sw_error_t -qca808x_ptp_rx_ts0_0_reg_rx_ts_sec_set( - a_uint32_t dev_id, a_uint32_t phy_id, - a_uint32_t value) -{ - union ptp_rx_ts0_0_reg_u reg_val; - sw_error_t ret = SW_OK; - - ret = qca808x_ptp_rx_ts0_0_reg_get(dev_id, phy_id, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.rx_ts_sec = value; - ret = qca808x_ptp_rx_ts0_0_reg_set(dev_id, phy_id, ®_val); - return ret; -} - -sw_error_t -qca808x_ptp_rx_ts0_1_reg_rx_ts_sec_get( - a_uint32_t dev_id, a_uint32_t phy_id, - a_uint32_t *value) -{ - union ptp_rx_ts0_1_reg_u reg_val; - sw_error_t ret = SW_OK; - - ret = qca808x_ptp_rx_ts0_1_reg_get(dev_id, phy_id, ®_val); - *value = reg_val.bf.rx_ts_sec; - return ret; -} - -sw_error_t -qca808x_ptp_rx_ts0_1_reg_rx_ts_sec_set( - a_uint32_t dev_id, a_uint32_t phy_id, - a_uint32_t value) -{ - union ptp_rx_ts0_1_reg_u reg_val; - sw_error_t ret = SW_OK; - - ret = qca808x_ptp_rx_ts0_1_reg_get(dev_id, phy_id, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.rx_ts_sec = value; - ret = qca808x_ptp_rx_ts0_1_reg_set(dev_id, phy_id, ®_val); - return ret; -} - -sw_error_t -qca808x_ptp_rx_ts0_2_reg_rx_ts_sec_get( - a_uint32_t dev_id, a_uint32_t phy_id, - a_uint32_t *value) -{ - union ptp_rx_ts0_2_reg_u reg_val; - sw_error_t ret = SW_OK; - - ret = qca808x_ptp_rx_ts0_2_reg_get(dev_id, phy_id, ®_val); - *value = reg_val.bf.rx_ts_sec; - return ret; -} - -sw_error_t -qca808x_ptp_rx_ts0_2_reg_rx_ts_sec_set( - a_uint32_t dev_id, a_uint32_t phy_id, - a_uint32_t value) -{ - union ptp_rx_ts0_2_reg_u reg_val; - sw_error_t ret = SW_OK; - - ret = qca808x_ptp_rx_ts0_2_reg_get(dev_id, phy_id, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.rx_ts_sec = value; - ret = qca808x_ptp_rx_ts0_2_reg_set(dev_id, phy_id, ®_val); - return ret; -} - -sw_error_t -qca808x_ptp_rx_ts0_3_reg_rx_ts_nsec_get( - a_uint32_t dev_id, a_uint32_t phy_id, - a_uint32_t *value) -{ - union ptp_rx_ts0_3_reg_u reg_val; - sw_error_t ret = SW_OK; - - ret = qca808x_ptp_rx_ts0_3_reg_get(dev_id, phy_id, ®_val); - *value = reg_val.bf.rx_ts_nsec; - return ret; -} - -sw_error_t -qca808x_ptp_rx_ts0_3_reg_rx_ts_nsec_set( - a_uint32_t dev_id, a_uint32_t phy_id, - a_uint32_t value) -{ - union ptp_rx_ts0_3_reg_u reg_val; - sw_error_t ret = SW_OK; - - ret = qca808x_ptp_rx_ts0_3_reg_get(dev_id, phy_id, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.rx_ts_nsec = value; - ret = qca808x_ptp_rx_ts0_3_reg_set(dev_id, phy_id, ®_val); - return ret; -} - -sw_error_t -qca808x_ptp_rx_ts0_4_reg_rx_ts_nsec_get( - a_uint32_t dev_id, a_uint32_t phy_id, - a_uint32_t *value) -{ - union ptp_rx_ts0_4_reg_u reg_val; - sw_error_t ret = SW_OK; - - ret = qca808x_ptp_rx_ts0_4_reg_get(dev_id, phy_id, ®_val); - *value = reg_val.bf.rx_ts_nsec; - return ret; -} - -sw_error_t -qca808x_ptp_rx_ts0_4_reg_rx_ts_nsec_set( - a_uint32_t dev_id, a_uint32_t phy_id, - a_uint32_t value) -{ - union ptp_rx_ts0_4_reg_u reg_val; - sw_error_t ret = SW_OK; - - ret = qca808x_ptp_rx_ts0_4_reg_get(dev_id, phy_id, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.rx_ts_nsec = value; - ret = qca808x_ptp_rx_ts0_4_reg_set(dev_id, phy_id, ®_val); - return ret; -} - -sw_error_t -qca808x_ptp_rx_ts0_5_reg_rx_ts_nfsec_get( - a_uint32_t dev_id, a_uint32_t phy_id, - a_uint32_t *value) -{ - union ptp_rx_ts0_5_reg_u reg_val; - sw_error_t ret = SW_OK; - - ret = qca808x_ptp_rx_ts0_5_reg_get(dev_id, phy_id, ®_val); - *value = reg_val.bf.rx_ts_nfsec; - return ret; -} - -sw_error_t -qca808x_ptp_rx_ts0_5_reg_rx_ts_nfsec_set( - a_uint32_t dev_id, a_uint32_t phy_id, - a_uint32_t value) -{ - union ptp_rx_ts0_5_reg_u reg_val; - sw_error_t ret = SW_OK; - - ret = qca808x_ptp_rx_ts0_5_reg_get(dev_id, phy_id, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.rx_ts_nfsec = value; - ret = qca808x_ptp_rx_ts0_5_reg_set(dev_id, phy_id, ®_val); - return ret; -} - -sw_error_t -qca808x_ptp_rx_ts0_5_reg_rx_msg_type_get( - a_uint32_t dev_id, a_uint32_t phy_id, - a_uint32_t *value) -{ - union ptp_rx_ts0_5_reg_u reg_val; - sw_error_t ret = SW_OK; - - ret = qca808x_ptp_rx_ts0_5_reg_get(dev_id, phy_id, ®_val); - *value = reg_val.bf.rx_msg_type; - return ret; -} - -sw_error_t -qca808x_ptp_rx_ts0_5_reg_rx_msg_type_set( - a_uint32_t dev_id, a_uint32_t phy_id, - a_uint32_t value) -{ - union ptp_rx_ts0_5_reg_u reg_val; - sw_error_t ret = SW_OK; - - ret = qca808x_ptp_rx_ts0_5_reg_get(dev_id, phy_id, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.rx_msg_type = value; - ret = qca808x_ptp_rx_ts0_5_reg_set(dev_id, phy_id, ®_val); - return ret; -} - -sw_error_t -qca808x_ptp_rx_ts0_6_reg_rx_ts_nfsec_get( - a_uint32_t dev_id, a_uint32_t phy_id, - a_uint32_t *value) -{ - union ptp_rx_ts0_6_reg_u reg_val; - sw_error_t ret = SW_OK; - - ret = qca808x_ptp_rx_ts0_6_reg_get(dev_id, phy_id, ®_val); - *value = reg_val.bf.rx_ts_nfsec; - return ret; -} - -sw_error_t -qca808x_ptp_rx_ts0_6_reg_rx_ts_nfsec_set( - a_uint32_t dev_id, a_uint32_t phy_id, - a_uint32_t value) -{ - union ptp_rx_ts0_6_reg_u reg_val; - sw_error_t ret = SW_OK; - - ret = qca808x_ptp_rx_ts0_6_reg_get(dev_id, phy_id, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.rx_ts_nfsec = value; - ret = qca808x_ptp_rx_ts0_6_reg_set(dev_id, phy_id, ®_val); - return ret; -} - -sw_error_t -qca808x_ptp_tx_seqid_reg_tx_seqid_get( - a_uint32_t dev_id, a_uint32_t phy_id, - a_uint32_t *value) -{ - union ptp_tx_seqid_reg_u reg_val; - sw_error_t ret = SW_OK; - - ret = qca808x_ptp_tx_seqid_reg_get(dev_id, phy_id, ®_val); - *value = reg_val.bf.tx_seqid; - return ret; -} - -sw_error_t -qca808x_ptp_tx_seqid_reg_tx_seqid_set( - a_uint32_t dev_id, a_uint32_t phy_id, - a_uint32_t value) -{ - union ptp_tx_seqid_reg_u reg_val; - sw_error_t ret = SW_OK; - - ret = qca808x_ptp_tx_seqid_reg_get(dev_id, phy_id, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.tx_seqid = value; - ret = qca808x_ptp_tx_seqid_reg_set(dev_id, phy_id, ®_val); - return ret; -} - -sw_error_t -qca808x_ptp_tx_portid0_reg_tx_portid_get( - a_uint32_t dev_id, a_uint32_t phy_id, - a_uint32_t *value) -{ - union ptp_tx_portid0_reg_u reg_val; - sw_error_t ret = SW_OK; - - ret = qca808x_ptp_tx_portid0_reg_get(dev_id, phy_id, ®_val); - *value = reg_val.bf.tx_portid; - return ret; -} - -sw_error_t -qca808x_ptp_tx_portid0_reg_tx_portid_set( - a_uint32_t dev_id, a_uint32_t phy_id, - a_uint32_t value) -{ - union ptp_tx_portid0_reg_u reg_val; - sw_error_t ret = SW_OK; - - ret = qca808x_ptp_tx_portid0_reg_get(dev_id, phy_id, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.tx_portid = value; - ret = qca808x_ptp_tx_portid0_reg_set(dev_id, phy_id, ®_val); - return ret; -} - -sw_error_t -qca808x_ptp_tx_portid1_reg_tx_portid_get( - a_uint32_t dev_id, a_uint32_t phy_id, - a_uint32_t *value) -{ - union ptp_tx_portid1_reg_u reg_val; - sw_error_t ret = SW_OK; - - ret = qca808x_ptp_tx_portid1_reg_get(dev_id, phy_id, ®_val); - *value = reg_val.bf.tx_portid; - return ret; -} - -sw_error_t -qca808x_ptp_tx_portid1_reg_tx_portid_set( - a_uint32_t dev_id, a_uint32_t phy_id, - a_uint32_t value) -{ - union ptp_tx_portid1_reg_u reg_val; - sw_error_t ret = SW_OK; - - ret = qca808x_ptp_tx_portid1_reg_get(dev_id, phy_id, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.tx_portid = value; - ret = qca808x_ptp_tx_portid1_reg_set(dev_id, phy_id, ®_val); - return ret; -} - -sw_error_t -qca808x_ptp_tx_portid2_reg_tx_portid_get( - a_uint32_t dev_id, a_uint32_t phy_id, - a_uint32_t *value) -{ - union ptp_tx_portid2_reg_u reg_val; - sw_error_t ret = SW_OK; - - ret = qca808x_ptp_tx_portid2_reg_get(dev_id, phy_id, ®_val); - *value = reg_val.bf.tx_portid; - return ret; -} - -sw_error_t -qca808x_ptp_tx_portid2_reg_tx_portid_set( - a_uint32_t dev_id, a_uint32_t phy_id, - a_uint32_t value) -{ - union ptp_tx_portid2_reg_u reg_val; - sw_error_t ret = SW_OK; - - ret = qca808x_ptp_tx_portid2_reg_get(dev_id, phy_id, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.tx_portid = value; - ret = qca808x_ptp_tx_portid2_reg_set(dev_id, phy_id, ®_val); - return ret; -} - -sw_error_t -qca808x_ptp_tx_portid3_reg_tx_portid_get( - a_uint32_t dev_id, a_uint32_t phy_id, - a_uint32_t *value) -{ - union ptp_tx_portid3_reg_u reg_val; - sw_error_t ret = SW_OK; - - ret = qca808x_ptp_tx_portid3_reg_get(dev_id, phy_id, ®_val); - *value = reg_val.bf.tx_portid; - return ret; -} - -sw_error_t -qca808x_ptp_tx_portid3_reg_tx_portid_set( - a_uint32_t dev_id, a_uint32_t phy_id, - a_uint32_t value) -{ - union ptp_tx_portid3_reg_u reg_val; - sw_error_t ret = SW_OK; - - ret = qca808x_ptp_tx_portid3_reg_get(dev_id, phy_id, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.tx_portid = value; - ret = qca808x_ptp_tx_portid3_reg_set(dev_id, phy_id, ®_val); - return ret; -} - -sw_error_t -qca808x_ptp_tx_portid4_reg_tx_portid_get( - a_uint32_t dev_id, a_uint32_t phy_id, - a_uint32_t *value) -{ - union ptp_tx_portid4_reg_u reg_val; - sw_error_t ret = SW_OK; - - ret = qca808x_ptp_tx_portid4_reg_get(dev_id, phy_id, ®_val); - *value = reg_val.bf.tx_portid; - return ret; -} - -sw_error_t -qca808x_ptp_tx_portid4_reg_tx_portid_set( - a_uint32_t dev_id, a_uint32_t phy_id, - a_uint32_t value) -{ - union ptp_tx_portid4_reg_u reg_val; - sw_error_t ret = SW_OK; - - ret = qca808x_ptp_tx_portid4_reg_get(dev_id, phy_id, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.tx_portid = value; - ret = qca808x_ptp_tx_portid4_reg_set(dev_id, phy_id, ®_val); - return ret; -} - -sw_error_t -qca808x_ptp_tx_ts0_reg_tx_ts_sec_get( - a_uint32_t dev_id, a_uint32_t phy_id, - a_uint32_t *value) -{ - union ptp_tx_ts0_reg_u reg_val; - sw_error_t ret = SW_OK; - - ret = qca808x_ptp_tx_ts0_reg_get(dev_id, phy_id, ®_val); - *value = reg_val.bf.tx_ts_sec; - return ret; -} - -sw_error_t -qca808x_ptp_tx_ts0_reg_tx_ts_sec_set( - a_uint32_t dev_id, a_uint32_t phy_id, - a_uint32_t value) -{ - union ptp_tx_ts0_reg_u reg_val; - sw_error_t ret = SW_OK; - - ret = qca808x_ptp_tx_ts0_reg_get(dev_id, phy_id, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.tx_ts_sec = value; - ret = qca808x_ptp_tx_ts0_reg_set(dev_id, phy_id, ®_val); - return ret; -} - -sw_error_t -qca808x_ptp_tx_ts1_reg_tx_ts_sec_get( - a_uint32_t dev_id, a_uint32_t phy_id, - a_uint32_t *value) -{ - union ptp_tx_ts1_reg_u reg_val; - sw_error_t ret = SW_OK; - - ret = qca808x_ptp_tx_ts1_reg_get(dev_id, phy_id, ®_val); - *value = reg_val.bf.tx_ts_sec; - return ret; -} - -sw_error_t -qca808x_ptp_tx_ts1_reg_tx_ts_sec_set( - a_uint32_t dev_id, a_uint32_t phy_id, - a_uint32_t value) -{ - union ptp_tx_ts1_reg_u reg_val; - sw_error_t ret = SW_OK; - - ret = qca808x_ptp_tx_ts1_reg_get(dev_id, phy_id, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.tx_ts_sec = value; - ret = qca808x_ptp_tx_ts1_reg_set(dev_id, phy_id, ®_val); - return ret; -} - -sw_error_t -qca808x_ptp_tx_ts2_reg_tx_ts_sec_get( - a_uint32_t dev_id, a_uint32_t phy_id, - a_uint32_t *value) -{ - union ptp_tx_ts2_reg_u reg_val; - sw_error_t ret = SW_OK; - - ret = qca808x_ptp_tx_ts2_reg_get(dev_id, phy_id, ®_val); - *value = reg_val.bf.tx_ts_sec; - return ret; -} - -sw_error_t -qca808x_ptp_tx_ts2_reg_tx_ts_sec_set( - a_uint32_t dev_id, a_uint32_t phy_id, - a_uint32_t value) -{ - union ptp_tx_ts2_reg_u reg_val; - sw_error_t ret = SW_OK; - - ret = qca808x_ptp_tx_ts2_reg_get(dev_id, phy_id, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.tx_ts_sec = value; - ret = qca808x_ptp_tx_ts2_reg_set(dev_id, phy_id, ®_val); - return ret; -} - -sw_error_t -qca808x_ptp_tx_ts3_reg_tx_ts_nsec_get( - a_uint32_t dev_id, a_uint32_t phy_id, - a_uint32_t *value) -{ - union ptp_tx_ts3_reg_u reg_val; - sw_error_t ret = SW_OK; - - ret = qca808x_ptp_tx_ts3_reg_get(dev_id, phy_id, ®_val); - *value = reg_val.bf.tx_ts_nsec; - return ret; -} - -sw_error_t -qca808x_ptp_tx_ts3_reg_tx_ts_nsec_set( - a_uint32_t dev_id, a_uint32_t phy_id, - a_uint32_t value) -{ - union ptp_tx_ts3_reg_u reg_val; - sw_error_t ret = SW_OK; - - ret = qca808x_ptp_tx_ts3_reg_get(dev_id, phy_id, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.tx_ts_nsec = value; - ret = qca808x_ptp_tx_ts3_reg_set(dev_id, phy_id, ®_val); - return ret; -} - -sw_error_t -qca808x_ptp_tx_ts4_reg_tx_ts_nsec_get( - a_uint32_t dev_id, a_uint32_t phy_id, - a_uint32_t *value) -{ - union ptp_tx_ts4_reg_u reg_val; - sw_error_t ret = SW_OK; - - ret = qca808x_ptp_tx_ts4_reg_get(dev_id, phy_id, ®_val); - *value = reg_val.bf.tx_ts_nsec; - return ret; -} - -sw_error_t -qca808x_ptp_tx_ts4_reg_tx_ts_nsec_set( - a_uint32_t dev_id, a_uint32_t phy_id, - a_uint32_t value) -{ - union ptp_tx_ts4_reg_u reg_val; - sw_error_t ret = SW_OK; - - ret = qca808x_ptp_tx_ts4_reg_get(dev_id, phy_id, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.tx_ts_nsec = value; - ret = qca808x_ptp_tx_ts4_reg_set(dev_id, phy_id, ®_val); - return ret; -} - -sw_error_t -qca808x_ptp_tx_ts5_reg_tx_ts_nfsec_get( - a_uint32_t dev_id, a_uint32_t phy_id, - a_uint32_t *value) -{ - union ptp_tx_ts5_reg_u reg_val; - sw_error_t ret = SW_OK; - - ret = qca808x_ptp_tx_ts5_reg_get(dev_id, phy_id, ®_val); - *value = reg_val.bf.tx_ts_nfsec; - return ret; -} - -sw_error_t -qca808x_ptp_tx_ts5_reg_tx_ts_nfsec_set( - a_uint32_t dev_id, a_uint32_t phy_id, - a_uint32_t value) -{ - union ptp_tx_ts5_reg_u reg_val; - sw_error_t ret = SW_OK; - - ret = qca808x_ptp_tx_ts5_reg_get(dev_id, phy_id, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.tx_ts_nfsec = value; - ret = qca808x_ptp_tx_ts5_reg_set(dev_id, phy_id, ®_val); - return ret; -} - -sw_error_t -qca808x_ptp_tx_ts5_reg_tx_msg_type_get( - a_uint32_t dev_id, a_uint32_t phy_id, - a_uint32_t *value) -{ - union ptp_tx_ts5_reg_u reg_val; - sw_error_t ret = SW_OK; - - ret = qca808x_ptp_tx_ts5_reg_get(dev_id, phy_id, ®_val); - *value = reg_val.bf.tx_msg_type; - return ret; -} - -sw_error_t -qca808x_ptp_tx_ts5_reg_tx_msg_type_set( - a_uint32_t dev_id, a_uint32_t phy_id, - a_uint32_t value) -{ - union ptp_tx_ts5_reg_u reg_val; - sw_error_t ret = SW_OK; - - ret = qca808x_ptp_tx_ts5_reg_get(dev_id, phy_id, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.tx_msg_type = value; - ret = qca808x_ptp_tx_ts5_reg_set(dev_id, phy_id, ®_val); - return ret; -} - -sw_error_t -qca808x_ptp_tx_ts6_reg_tx_ts_nfsec_get( - a_uint32_t dev_id, a_uint32_t phy_id, - a_uint32_t *value) -{ - union ptp_tx_ts6_reg_u reg_val; - sw_error_t ret = SW_OK; - - ret = qca808x_ptp_tx_ts6_reg_get(dev_id, phy_id, ®_val); - *value = reg_val.bf.tx_ts_nfsec; - return ret; -} - -sw_error_t -qca808x_ptp_tx_ts6_reg_tx_ts_nfsec_set( - a_uint32_t dev_id, a_uint32_t phy_id, - a_uint32_t value) -{ - union ptp_tx_ts6_reg_u reg_val; - sw_error_t ret = SW_OK; - - ret = qca808x_ptp_tx_ts6_reg_get(dev_id, phy_id, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.tx_ts_nfsec = value; - ret = qca808x_ptp_tx_ts6_reg_set(dev_id, phy_id, ®_val); - return ret; -} - -sw_error_t -qca808x_ptp_orig_corr0_reg_ptp_orig_corr_get( - a_uint32_t dev_id, a_uint32_t phy_id, - a_uint32_t *value) -{ - union ptp_orig_corr0_reg_u reg_val; - sw_error_t ret = SW_OK; - - ret = qca808x_ptp_orig_corr0_reg_get(dev_id, phy_id, ®_val); - *value = reg_val.bf.ptp_orig_corr; - return ret; -} - -sw_error_t -qca808x_ptp_orig_corr0_reg_ptp_orig_corr_set( - a_uint32_t dev_id, a_uint32_t phy_id, - a_uint32_t value) -{ - union ptp_orig_corr0_reg_u reg_val; - sw_error_t ret = SW_OK; - - ret = qca808x_ptp_orig_corr0_reg_get(dev_id, phy_id, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.ptp_orig_corr = value; - ret = qca808x_ptp_orig_corr0_reg_set(dev_id, phy_id, ®_val); - return ret; -} - -sw_error_t -qca808x_ptp_orig_corr1_reg_ptp_orig_corr_get( - a_uint32_t dev_id, a_uint32_t phy_id, - a_uint32_t *value) -{ - union ptp_orig_corr1_reg_u reg_val; - sw_error_t ret = SW_OK; - - ret = qca808x_ptp_orig_corr1_reg_get(dev_id, phy_id, ®_val); - *value = reg_val.bf.ptp_orig_corr; - return ret; -} - -sw_error_t -qca808x_ptp_orig_corr1_reg_ptp_orig_corr_set( - a_uint32_t dev_id, a_uint32_t phy_id, - a_uint32_t value) -{ - union ptp_orig_corr1_reg_u reg_val; - sw_error_t ret = SW_OK; - - ret = qca808x_ptp_orig_corr1_reg_get(dev_id, phy_id, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.ptp_orig_corr = value; - ret = qca808x_ptp_orig_corr1_reg_set(dev_id, phy_id, ®_val); - return ret; -} - -sw_error_t -qca808x_ptp_orig_corr2_reg_ptp_orig_corr_get( - a_uint32_t dev_id, a_uint32_t phy_id, - a_uint32_t *value) -{ - union ptp_orig_corr2_reg_u reg_val; - sw_error_t ret = SW_OK; - - ret = qca808x_ptp_orig_corr2_reg_get(dev_id, phy_id, ®_val); - *value = reg_val.bf.ptp_orig_corr; - return ret; -} - -sw_error_t -qca808x_ptp_orig_corr2_reg_ptp_orig_corr_set( - a_uint32_t dev_id, a_uint32_t phy_id, - a_uint32_t value) -{ - union ptp_orig_corr2_reg_u reg_val; - sw_error_t ret = SW_OK; - - ret = qca808x_ptp_orig_corr2_reg_get(dev_id, phy_id, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.ptp_orig_corr = value; - ret = qca808x_ptp_orig_corr2_reg_set(dev_id, phy_id, ®_val); - return ret; -} - -sw_error_t -qca808x_ptp_orig_corr3_reg_ptp_orig_corr_get( - a_uint32_t dev_id, a_uint32_t phy_id, - a_uint32_t *value) -{ - union ptp_orig_corr3_reg_u reg_val; - sw_error_t ret = SW_OK; - - ret = qca808x_ptp_orig_corr3_reg_get(dev_id, phy_id, ®_val); - *value = reg_val.bf.ptp_orig_corr; - return ret; -} - -sw_error_t -qca808x_ptp_orig_corr3_reg_ptp_orig_corr_set( - a_uint32_t dev_id, a_uint32_t phy_id, - a_uint32_t value) -{ - union ptp_orig_corr3_reg_u reg_val; - sw_error_t ret = SW_OK; - - ret = qca808x_ptp_orig_corr3_reg_get(dev_id, phy_id, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.ptp_orig_corr = value; - ret = qca808x_ptp_orig_corr3_reg_set(dev_id, phy_id, ®_val); - return ret; -} - -sw_error_t -qca808x_ptp_in_trig0_reg_ptp_in_trig_nisec_get( - a_uint32_t dev_id, a_uint32_t phy_id, - a_uint32_t *value) -{ - union ptp_in_trig0_reg_u reg_val; - sw_error_t ret = SW_OK; - - ret = qca808x_ptp_in_trig0_reg_get(dev_id, phy_id, ®_val); - *value = reg_val.bf.ptp_in_trig_nisec; - return ret; -} - -sw_error_t -qca808x_ptp_in_trig0_reg_ptp_in_trig_nisec_set( - a_uint32_t dev_id, a_uint32_t phy_id, - a_uint32_t value) -{ - union ptp_in_trig0_reg_u reg_val; - sw_error_t ret = SW_OK; - - ret = qca808x_ptp_in_trig0_reg_get(dev_id, phy_id, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.ptp_in_trig_nisec = value; - ret = qca808x_ptp_in_trig0_reg_set(dev_id, phy_id, ®_val); - return ret; -} - -sw_error_t -qca808x_ptp_in_trig1_reg_ptp_in_trig_nisec_get( - a_uint32_t dev_id, a_uint32_t phy_id, - a_uint32_t *value) -{ - union ptp_in_trig1_reg_u reg_val; - sw_error_t ret = SW_OK; - - ret = qca808x_ptp_in_trig1_reg_get(dev_id, phy_id, ®_val); - *value = reg_val.bf.ptp_in_trig_nisec; - return ret; -} - -sw_error_t -qca808x_ptp_in_trig1_reg_ptp_in_trig_nisec_set( - a_uint32_t dev_id, a_uint32_t phy_id, - a_uint32_t value) -{ - union ptp_in_trig1_reg_u reg_val; - sw_error_t ret = SW_OK; - - ret = qca808x_ptp_in_trig1_reg_get(dev_id, phy_id, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.ptp_in_trig_nisec = value; - ret = qca808x_ptp_in_trig1_reg_set(dev_id, phy_id, ®_val); - return ret; -} - -sw_error_t -qca808x_ptp_in_trig2_reg_ptp_in_trig_nisec_get( - a_uint32_t dev_id, a_uint32_t phy_id, - a_uint32_t *value) -{ - union ptp_in_trig2_reg_u reg_val; - sw_error_t ret = SW_OK; - - ret = qca808x_ptp_in_trig2_reg_get(dev_id, phy_id, ®_val); - *value = reg_val.bf.ptp_in_trig_nisec; - return ret; -} - -sw_error_t -qca808x_ptp_in_trig2_reg_ptp_in_trig_nisec_set( - a_uint32_t dev_id, a_uint32_t phy_id, - a_uint32_t value) -{ - union ptp_in_trig2_reg_u reg_val; - sw_error_t ret = SW_OK; - - ret = qca808x_ptp_in_trig2_reg_get(dev_id, phy_id, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.ptp_in_trig_nisec = value; - ret = qca808x_ptp_in_trig2_reg_set(dev_id, phy_id, ®_val); - return ret; -} - -sw_error_t -qca808x_ptp_in_trig3_reg_ptp_in_trig_nisec_get( - a_uint32_t dev_id, a_uint32_t phy_id, - a_uint32_t *value) -{ - union ptp_in_trig3_reg_u reg_val; - sw_error_t ret = SW_OK; - - ret = qca808x_ptp_in_trig3_reg_get(dev_id, phy_id, ®_val); - *value = reg_val.bf.ptp_in_trig_nisec; - return ret; -} - -sw_error_t -qca808x_ptp_in_trig3_reg_ptp_in_trig_nisec_set( - a_uint32_t dev_id, a_uint32_t phy_id, - a_uint32_t value) -{ - union ptp_in_trig3_reg_u reg_val; - sw_error_t ret = SW_OK; - - ret = qca808x_ptp_in_trig3_reg_get(dev_id, phy_id, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.ptp_in_trig_nisec = value; - ret = qca808x_ptp_in_trig3_reg_set(dev_id, phy_id, ®_val); - return ret; -} - -sw_error_t -qca808x_ptp_tx_latency_reg_ptp_tx_latency_get( - a_uint32_t dev_id, a_uint32_t phy_id, - a_uint32_t *value) -{ - union ptp_tx_latency_reg_u reg_val; - sw_error_t ret = SW_OK; - - ret = qca808x_ptp_tx_latency_reg_get(dev_id, phy_id, ®_val); - *value = reg_val.bf.ptp_tx_latency; - return ret; -} - -sw_error_t -qca808x_ptp_tx_latency_reg_ptp_tx_latency_set( - a_uint32_t dev_id, a_uint32_t phy_id, - a_uint32_t value) -{ - union ptp_tx_latency_reg_u reg_val; - sw_error_t ret = SW_OK; - - ret = qca808x_ptp_tx_latency_reg_get(dev_id, phy_id, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.ptp_tx_latency = value; - ret = qca808x_ptp_tx_latency_reg_set(dev_id, phy_id, ®_val); - return ret; -} - -sw_error_t -qca808x_ptp_rtc_inc0_reg_ptp_rtc_inc_nis_get( - a_uint32_t dev_id, a_uint32_t phy_id, - a_uint32_t *value) -{ - union ptp_rtc_inc0_reg_u reg_val; - sw_error_t ret = SW_OK; - - ret = qca808x_ptp_rtc_inc0_reg_get(dev_id, phy_id, ®_val); - *value = reg_val.bf.ptp_rtc_inc_nis; - return ret; -} - -sw_error_t -qca808x_ptp_rtc_inc0_reg_ptp_rtc_inc_nis_set( - a_uint32_t dev_id, a_uint32_t phy_id, - a_uint32_t value) -{ - union ptp_rtc_inc0_reg_u reg_val; - sw_error_t ret = SW_OK; - - ret = qca808x_ptp_rtc_inc0_reg_get(dev_id, phy_id, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.ptp_rtc_inc_nis = value; - ret = qca808x_ptp_rtc_inc0_reg_set(dev_id, phy_id, ®_val); - return ret; -} - -sw_error_t -qca808x_ptp_rtc_inc0_reg_ptp_rtc_inc_nfs_get( - a_uint32_t dev_id, a_uint32_t phy_id, - a_uint32_t *value) -{ - union ptp_rtc_inc0_reg_u reg_val; - sw_error_t ret = SW_OK; - - ret = qca808x_ptp_rtc_inc0_reg_get(dev_id, phy_id, ®_val); - *value = reg_val.bf.ptp_rtc_inc_nfs; - return ret; -} - -sw_error_t -qca808x_ptp_rtc_inc0_reg_ptp_rtc_inc_nfs_set( - a_uint32_t dev_id, a_uint32_t phy_id, - a_uint32_t value) -{ - union ptp_rtc_inc0_reg_u reg_val; - sw_error_t ret = SW_OK; - - ret = qca808x_ptp_rtc_inc0_reg_get(dev_id, phy_id, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.ptp_rtc_inc_nfs = value; - ret = qca808x_ptp_rtc_inc0_reg_set(dev_id, phy_id, ®_val); - return ret; -} - -sw_error_t -qca808x_ptp_rtc_inc1_reg_ptp_rtc_inc_nfs_get( - a_uint32_t dev_id, a_uint32_t phy_id, - a_uint32_t *value) -{ - union ptp_rtc_inc1_reg_u reg_val; - sw_error_t ret = SW_OK; - - ret = qca808x_ptp_rtc_inc1_reg_get(dev_id, phy_id, ®_val); - *value = reg_val.bf.ptp_rtc_inc_nfs; - return ret; -} - -sw_error_t -qca808x_ptp_rtc_inc1_reg_ptp_rtc_inc_nfs_set( - a_uint32_t dev_id, a_uint32_t phy_id, - a_uint32_t value) -{ - union ptp_rtc_inc1_reg_u reg_val; - sw_error_t ret = SW_OK; - - ret = qca808x_ptp_rtc_inc1_reg_get(dev_id, phy_id, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.ptp_rtc_inc_nfs = value; - ret = qca808x_ptp_rtc_inc1_reg_set(dev_id, phy_id, ®_val); - return ret; -} - -sw_error_t -qca808x_ptp_rtcoffs0_reg_ptp_rtcoffs_nsec_get( - a_uint32_t dev_id, a_uint32_t phy_id, - a_uint32_t *value) -{ - union ptp_rtcoffs0_reg_u reg_val; - sw_error_t ret = SW_OK; - - ret = qca808x_ptp_rtcoffs0_reg_get(dev_id, phy_id, ®_val); - *value = reg_val.bf.ptp_rtcoffs_nsec; - return ret; -} - -sw_error_t -qca808x_ptp_rtcoffs0_reg_ptp_rtcoffs_nsec_set( - a_uint32_t dev_id, a_uint32_t phy_id, - a_uint32_t value) -{ - union ptp_rtcoffs0_reg_u reg_val; - sw_error_t ret = SW_OK; - - ret = qca808x_ptp_rtcoffs0_reg_get(dev_id, phy_id, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.ptp_rtcoffs_nsec = value; - ret = qca808x_ptp_rtcoffs0_reg_set(dev_id, phy_id, ®_val); - return ret; -} - -sw_error_t -qca808x_ptp_rtcoffs1_reg_ptp_rtcoffs_nsec_get( - a_uint32_t dev_id, a_uint32_t phy_id, - a_uint32_t *value) -{ - union ptp_rtcoffs1_reg_u reg_val; - sw_error_t ret = SW_OK; - - ret = qca808x_ptp_rtcoffs1_reg_get(dev_id, phy_id, ®_val); - *value = reg_val.bf.ptp_rtcoffs_nsec; - return ret; -} - -sw_error_t -qca808x_ptp_rtcoffs1_reg_ptp_rtcoffs_nsec_set( - a_uint32_t dev_id, a_uint32_t phy_id, - a_uint32_t value) -{ - union ptp_rtcoffs1_reg_u reg_val; - sw_error_t ret = SW_OK; - - ret = qca808x_ptp_rtcoffs1_reg_get(dev_id, phy_id, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.ptp_rtcoffs_nsec = value; - ret = qca808x_ptp_rtcoffs1_reg_set(dev_id, phy_id, ®_val); - return ret; -} - -sw_error_t -qca808x_ptp_rtcoffs2_reg_ptp_rtcoffs_sec_get( - a_uint32_t dev_id, a_uint32_t phy_id, - a_uint32_t *value) -{ - union ptp_rtcoffs2_reg_u reg_val; - sw_error_t ret = SW_OK; - - ret = qca808x_ptp_rtcoffs2_reg_get(dev_id, phy_id, ®_val); - *value = reg_val.bf.ptp_rtcoffs_sec; - return ret; -} - -sw_error_t -qca808x_ptp_rtcoffs2_reg_ptp_rtcoffs_sec_set( - a_uint32_t dev_id, a_uint32_t phy_id, - a_uint32_t value) -{ - union ptp_rtcoffs2_reg_u reg_val; - sw_error_t ret = SW_OK; - - ret = qca808x_ptp_rtcoffs2_reg_get(dev_id, phy_id, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.ptp_rtcoffs_sec = value; - ret = qca808x_ptp_rtcoffs2_reg_set(dev_id, phy_id, ®_val); - return ret; -} - -sw_error_t -qca808x_ptp_rtcoffs3_reg_ptp_rtcoffs_sec_get( - a_uint32_t dev_id, a_uint32_t phy_id, - a_uint32_t *value) -{ - union ptp_rtcoffs3_reg_u reg_val; - sw_error_t ret = SW_OK; - - ret = qca808x_ptp_rtcoffs3_reg_get(dev_id, phy_id, ®_val); - *value = reg_val.bf.ptp_rtcoffs_sec; - return ret; -} - -sw_error_t -qca808x_ptp_rtcoffs3_reg_ptp_rtcoffs_sec_set( - a_uint32_t dev_id, a_uint32_t phy_id, - a_uint32_t value) -{ - union ptp_rtcoffs3_reg_u reg_val; - sw_error_t ret = SW_OK; - - ret = qca808x_ptp_rtcoffs3_reg_get(dev_id, phy_id, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.ptp_rtcoffs_sec = value; - ret = qca808x_ptp_rtcoffs3_reg_set(dev_id, phy_id, ®_val); - return ret; -} - -sw_error_t -qca808x_ptp_rtcoffs4_reg_ptp_rtcoffs_sec_get( - a_uint32_t dev_id, a_uint32_t phy_id, - a_uint32_t *value) -{ - union ptp_rtcoffs4_reg_u reg_val; - sw_error_t ret = SW_OK; - - ret = qca808x_ptp_rtcoffs4_reg_get(dev_id, phy_id, ®_val); - *value = reg_val.bf.ptp_rtcoffs_sec; - return ret; -} - -sw_error_t -qca808x_ptp_rtcoffs4_reg_ptp_rtcoffs_sec_set( - a_uint32_t dev_id, a_uint32_t phy_id, - a_uint32_t value) -{ - union ptp_rtcoffs4_reg_u reg_val; - sw_error_t ret = SW_OK; - - ret = qca808x_ptp_rtcoffs4_reg_get(dev_id, phy_id, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.ptp_rtcoffs_sec = value; - ret = qca808x_ptp_rtcoffs4_reg_set(dev_id, phy_id, ®_val); - return ret; -} - -sw_error_t -qca808x_ptp_rtc0_reg_ptp_rtc_sec_get( - a_uint32_t dev_id, a_uint32_t phy_id, - a_uint32_t *value) -{ - union ptp_rtc0_reg_u reg_val; - sw_error_t ret = SW_OK; - - ret = qca808x_ptp_rtc0_reg_get(dev_id, phy_id, ®_val); - *value = reg_val.bf.ptp_rtc_sec; - return ret; -} - -sw_error_t -qca808x_ptp_rtc0_reg_ptp_rtc_sec_set( - a_uint32_t dev_id, a_uint32_t phy_id, - a_uint32_t value) -{ - union ptp_rtc0_reg_u reg_val; - sw_error_t ret = SW_OK; - - ret = qca808x_ptp_rtc0_reg_get(dev_id, phy_id, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.ptp_rtc_sec = value; - ret = qca808x_ptp_rtc0_reg_set(dev_id, phy_id, ®_val); - return ret; -} - -sw_error_t -qca808x_ptp_rtc1_reg_ptp_rtc_sec_get( - a_uint32_t dev_id, a_uint32_t phy_id, - a_uint32_t *value) -{ - union ptp_rtc1_reg_u reg_val; - sw_error_t ret = SW_OK; - - ret = qca808x_ptp_rtc1_reg_get(dev_id, phy_id, ®_val); - *value = reg_val.bf.ptp_rtc_sec; - return ret; -} - -sw_error_t -qca808x_ptp_rtc1_reg_ptp_rtc_sec_set( - a_uint32_t dev_id, a_uint32_t phy_id, - a_uint32_t value) -{ - union ptp_rtc1_reg_u reg_val; - sw_error_t ret = SW_OK; - - ret = qca808x_ptp_rtc1_reg_get(dev_id, phy_id, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.ptp_rtc_sec = value; - ret = qca808x_ptp_rtc1_reg_set(dev_id, phy_id, ®_val); - return ret; -} - -sw_error_t -qca808x_ptp_rtc2_reg_ptp_rtc_sec_get( - a_uint32_t dev_id, a_uint32_t phy_id, - a_uint32_t *value) -{ - union ptp_rtc2_reg_u reg_val; - sw_error_t ret = SW_OK; - - ret = qca808x_ptp_rtc2_reg_get(dev_id, phy_id, ®_val); - *value = reg_val.bf.ptp_rtc_sec; - return ret; -} - -sw_error_t -qca808x_ptp_rtc2_reg_ptp_rtc_sec_set( - a_uint32_t dev_id, a_uint32_t phy_id, - a_uint32_t value) -{ - union ptp_rtc2_reg_u reg_val; - sw_error_t ret = SW_OK; - - ret = qca808x_ptp_rtc2_reg_get(dev_id, phy_id, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.ptp_rtc_sec = value; - ret = qca808x_ptp_rtc2_reg_set(dev_id, phy_id, ®_val); - return ret; -} - -sw_error_t -qca808x_ptp_rtc3_reg_ptp_rtc_nisec_get( - a_uint32_t dev_id, a_uint32_t phy_id, - a_uint32_t *value) -{ - union ptp_rtc3_reg_u reg_val; - sw_error_t ret = SW_OK; - - ret = qca808x_ptp_rtc3_reg_get(dev_id, phy_id, ®_val); - *value = reg_val.bf.ptp_rtc_nisec; - return ret; -} - -sw_error_t -qca808x_ptp_rtc3_reg_ptp_rtc_nisec_set( - a_uint32_t dev_id, a_uint32_t phy_id, - a_uint32_t value) -{ - union ptp_rtc3_reg_u reg_val; - sw_error_t ret = SW_OK; - - ret = qca808x_ptp_rtc3_reg_get(dev_id, phy_id, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.ptp_rtc_nisec = value; - ret = qca808x_ptp_rtc3_reg_set(dev_id, phy_id, ®_val); - return ret; -} - -sw_error_t -qca808x_ptp_rtc4_reg_ptp_rtc_nisec_get( - a_uint32_t dev_id, a_uint32_t phy_id, - a_uint32_t *value) -{ - union ptp_rtc4_reg_u reg_val; - sw_error_t ret = SW_OK; - - ret = qca808x_ptp_rtc4_reg_get(dev_id, phy_id, ®_val); - *value = reg_val.bf.ptp_rtc_nisec; - return ret; -} - -sw_error_t -qca808x_ptp_rtc4_reg_ptp_rtc_nisec_set( - a_uint32_t dev_id, a_uint32_t phy_id, - a_uint32_t value) -{ - union ptp_rtc4_reg_u reg_val; - sw_error_t ret = SW_OK; - - ret = qca808x_ptp_rtc4_reg_get(dev_id, phy_id, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.ptp_rtc_nisec = value; - ret = qca808x_ptp_rtc4_reg_set(dev_id, phy_id, ®_val); - return ret; -} - -sw_error_t -qca808x_ptp_rtc5_reg_ptp_rtc_nfsec_get( - a_uint32_t dev_id, a_uint32_t phy_id, - a_uint32_t *value) -{ - union ptp_rtc5_reg_u reg_val; - sw_error_t ret = SW_OK; - - ret = qca808x_ptp_rtc5_reg_get(dev_id, phy_id, ®_val); - *value = reg_val.bf.ptp_rtc_nfsec; - return ret; -} - -sw_error_t -qca808x_ptp_rtc5_reg_ptp_rtc_nfsec_set( - a_uint32_t dev_id, a_uint32_t phy_id, - a_uint32_t value) -{ - union ptp_rtc5_reg_u reg_val; - sw_error_t ret = SW_OK; - - ret = qca808x_ptp_rtc5_reg_get(dev_id, phy_id, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.ptp_rtc_nfsec = value; - ret = qca808x_ptp_rtc5_reg_set(dev_id, phy_id, ®_val); - return ret; -} - -sw_error_t -qca808x_ptp_rtc6_reg_ptp_rtc_nfsec_get( - a_uint32_t dev_id, a_uint32_t phy_id, - a_uint32_t *value) -{ - union ptp_rtc6_reg_u reg_val; - sw_error_t ret = SW_OK; - - ret = qca808x_ptp_rtc6_reg_get(dev_id, phy_id, ®_val); - *value = reg_val.bf.ptp_rtc_nfsec; - return ret; -} - -sw_error_t -qca808x_ptp_rtc6_reg_ptp_rtc_nfsec_set( - a_uint32_t dev_id, a_uint32_t phy_id, - a_uint32_t value) -{ - union ptp_rtc6_reg_u reg_val; - sw_error_t ret = SW_OK; - - ret = qca808x_ptp_rtc6_reg_get(dev_id, phy_id, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.ptp_rtc_nfsec = value; - ret = qca808x_ptp_rtc6_reg_set(dev_id, phy_id, ®_val); - return ret; -} - -sw_error_t -qca808x_ptp_rtcoffs_valid_reg_ptp_rtcoffs_valid_get( - a_uint32_t dev_id, a_uint32_t phy_id, - a_uint32_t *value) -{ - union ptp_rtcoffs_valid_reg_u reg_val; - sw_error_t ret = SW_OK; - - ret = qca808x_ptp_rtcoffs_valid_reg_get(dev_id, phy_id, ®_val); - *value = reg_val.bf.ptp_rtcoffs_valid; - return ret; -} - -sw_error_t -qca808x_ptp_rtcoffs_valid_reg_ptp_rtcoffs_valid_set( - a_uint32_t dev_id, a_uint32_t phy_id, - a_uint32_t value) -{ - union ptp_rtcoffs_valid_reg_u reg_val; - sw_error_t ret = SW_OK; - - ret = qca808x_ptp_rtcoffs_valid_reg_get(dev_id, phy_id, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.ptp_rtcoffs_valid = value; - ret = qca808x_ptp_rtcoffs_valid_reg_set(dev_id, phy_id, ®_val); - return ret; -} - -sw_error_t -qca808x_ptp_misc_config_reg_ptp_ver_chk_en_get( - a_uint32_t dev_id, a_uint32_t phy_id, - a_uint32_t *value) -{ - union ptp_misc_config_reg_u reg_val; - sw_error_t ret = SW_OK; - - ret = qca808x_ptp_misc_config_reg_get(dev_id, phy_id, ®_val); - *value = reg_val.bf.ptp_ver_chk_en; - return ret; -} - -sw_error_t -qca808x_ptp_misc_config_reg_ptp_ver_chk_en_set( - a_uint32_t dev_id, a_uint32_t phy_id, - a_uint32_t value) -{ - union ptp_misc_config_reg_u reg_val; - sw_error_t ret = SW_OK; - - ret = qca808x_ptp_misc_config_reg_get(dev_id, phy_id, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.ptp_ver_chk_en = value; - ret = qca808x_ptp_misc_config_reg_set(dev_id, phy_id, ®_val); - return ret; -} - -sw_error_t -qca808x_ptp_misc_config_reg_ipv6_udp_chk_en_get( - a_uint32_t dev_id, a_uint32_t phy_id, - a_uint32_t *value) -{ - union ptp_misc_config_reg_u reg_val; - sw_error_t ret = SW_OK; - - ret = qca808x_ptp_misc_config_reg_get(dev_id, phy_id, ®_val); - *value = reg_val.bf.ipv6_udp_chk_en; - return ret; -} - -sw_error_t -qca808x_ptp_misc_config_reg_ipv6_udp_chk_en_set( - a_uint32_t dev_id, a_uint32_t phy_id, - a_uint32_t value) -{ - union ptp_misc_config_reg_u reg_val; - sw_error_t ret = SW_OK; - - ret = qca808x_ptp_misc_config_reg_get(dev_id, phy_id, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.ipv6_udp_chk_en = value; - ret = qca808x_ptp_misc_config_reg_set(dev_id, phy_id, ®_val); - return ret; -} - -sw_error_t -qca808x_ptp_misc_config_reg_cf_from_pkt_en_get( - a_uint32_t dev_id, a_uint32_t phy_id, - a_uint32_t *value) -{ - union ptp_misc_config_reg_u reg_val; - sw_error_t ret = SW_OK; - - ret = qca808x_ptp_misc_config_reg_get(dev_id, phy_id, ®_val); - *value = reg_val.bf.cf_from_pkt_en; - return ret; -} - -sw_error_t -qca808x_ptp_misc_config_reg_cf_from_pkt_en_set( - a_uint32_t dev_id, a_uint32_t phy_id, - a_uint32_t value) -{ - union ptp_misc_config_reg_u reg_val; - sw_error_t ret = SW_OK; - - ret = qca808x_ptp_misc_config_reg_get(dev_id, phy_id, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.cf_from_pkt_en = value; - ret = qca808x_ptp_misc_config_reg_set(dev_id, phy_id, ®_val); - return ret; -} - -sw_error_t -qca808x_ptp_misc_config_reg_embed_ingress_time_en_get( - a_uint32_t dev_id, a_uint32_t phy_id, - a_uint32_t *value) -{ - union ptp_misc_config_reg_u reg_val; - sw_error_t ret = SW_OK; - - ret = qca808x_ptp_misc_config_reg_get(dev_id, phy_id, ®_val); - *value = reg_val.bf.embed_ingress_time_en; - return ret; -} - -sw_error_t -qca808x_ptp_misc_config_reg_embed_ingress_time_en_set( - a_uint32_t dev_id, a_uint32_t phy_id, - a_uint32_t value) -{ - union ptp_misc_config_reg_u reg_val; - sw_error_t ret = SW_OK; - - ret = qca808x_ptp_misc_config_reg_get(dev_id, phy_id, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.embed_ingress_time_en = value; - ret = qca808x_ptp_misc_config_reg_set(dev_id, phy_id, ®_val); - return ret; -} - -sw_error_t -qca808x_ptp_misc_config_reg_ptp_addr_chk_en_get( - a_uint32_t dev_id, a_uint32_t phy_id, - a_uint32_t *value) -{ - union ptp_misc_config_reg_u reg_val; - sw_error_t ret = SW_OK; - - ret = qca808x_ptp_misc_config_reg_get(dev_id, phy_id, ®_val); - *value = reg_val.bf.ptp_addr_chk_en; - return ret; -} - -sw_error_t -qca808x_ptp_misc_config_reg_ptp_addr_chk_en_set( - a_uint32_t dev_id, a_uint32_t phy_id, - a_uint32_t value) -{ - union ptp_misc_config_reg_u reg_val; - sw_error_t ret = SW_OK; - - ret = qca808x_ptp_misc_config_reg_get(dev_id, phy_id, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.ptp_addr_chk_en = value; - ret = qca808x_ptp_misc_config_reg_set(dev_id, phy_id, ®_val); - return ret; -} - -sw_error_t -qca808x_ptp_misc_config_reg_crc_validate_en_get( - a_uint32_t dev_id, a_uint32_t phy_id, - a_uint32_t *value) -{ - union ptp_misc_config_reg_u reg_val; - sw_error_t ret = SW_OK; - - ret = qca808x_ptp_misc_config_reg_get(dev_id, phy_id, ®_val); - *value = reg_val.bf.crc_validate_en; - return ret; -} - -sw_error_t -qca808x_ptp_misc_config_reg_crc_validate_en_set( - a_uint32_t dev_id, a_uint32_t phy_id, - a_uint32_t value) -{ - union ptp_misc_config_reg_u reg_val; - sw_error_t ret = SW_OK; - - ret = qca808x_ptp_misc_config_reg_get(dev_id, phy_id, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.crc_validate_en = value; - ret = qca808x_ptp_misc_config_reg_set(dev_id, phy_id, ®_val); - return ret; -} - -sw_error_t -qca808x_ptp_misc_config_reg_pkt_one_step_en_get( - a_uint32_t dev_id, a_uint32_t phy_id, - a_uint32_t *value) -{ - union ptp_misc_config_reg_u reg_val; - sw_error_t ret = SW_OK; - - ret = qca808x_ptp_misc_config_reg_get(dev_id, phy_id, ®_val); - *value = reg_val.bf.pkt_one_step_en; - return ret; -} - -sw_error_t -qca808x_ptp_misc_config_reg_pkt_one_step_en_set( - a_uint32_t dev_id, a_uint32_t phy_id, - a_uint32_t value) -{ - union ptp_misc_config_reg_u reg_val; - sw_error_t ret = SW_OK; - - ret = qca808x_ptp_misc_config_reg_get(dev_id, phy_id, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.pkt_one_step_en = value; - ret = qca808x_ptp_misc_config_reg_set(dev_id, phy_id, ®_val); - return ret; -} - -sw_error_t -qca808x_ptp_misc_config_reg_ptp_version_get( - a_uint32_t dev_id, a_uint32_t phy_id, - a_uint32_t *value) -{ - union ptp_misc_config_reg_u reg_val; - sw_error_t ret = SW_OK; - - ret = qca808x_ptp_misc_config_reg_get(dev_id, phy_id, ®_val); - *value = reg_val.bf.ptp_version; - return ret; -} - -sw_error_t -qca808x_ptp_misc_config_reg_ptp_version_set( - a_uint32_t dev_id, a_uint32_t phy_id, - a_uint32_t value) -{ - union ptp_misc_config_reg_u reg_val; - sw_error_t ret = SW_OK; - - ret = qca808x_ptp_misc_config_reg_get(dev_id, phy_id, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.ptp_version = value; - ret = qca808x_ptp_misc_config_reg_set(dev_id, phy_id, ®_val); - return ret; -} - -sw_error_t -qca808x_ptp_misc_config_reg_appended_timestamp_size_get( - a_uint32_t dev_id, a_uint32_t phy_id, - a_uint32_t *value) -{ - union ptp_misc_config_reg_u reg_val; - sw_error_t ret = SW_OK; - - ret = qca808x_ptp_misc_config_reg_get(dev_id, phy_id, ®_val); - *value = reg_val.bf.appended_timestamp_size; - return ret; -} - -sw_error_t -qca808x_ptp_misc_config_reg_appended_timestamp_size_set( - a_uint32_t dev_id, a_uint32_t phy_id, - a_uint32_t value) -{ - union ptp_misc_config_reg_u reg_val; - sw_error_t ret = SW_OK; - - ret = qca808x_ptp_misc_config_reg_get(dev_id, phy_id, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.appended_timestamp_size = value; - ret = qca808x_ptp_misc_config_reg_set(dev_id, phy_id, ®_val); - return ret; -} - -sw_error_t -qca808x_ptp_misc_config_reg_ts_rtc_select_get( - a_uint32_t dev_id, a_uint32_t phy_id, - a_uint32_t *value) -{ - union ptp_misc_config_reg_u reg_val; - sw_error_t ret = SW_OK; - - ret = qca808x_ptp_misc_config_reg_get(dev_id, phy_id, ®_val); - *value = reg_val.bf.ts_rtc_select; - return ret; -} - -sw_error_t -qca808x_ptp_misc_config_reg_ts_rtc_select_set( - a_uint32_t dev_id, a_uint32_t phy_id, - a_uint32_t value) -{ - union ptp_misc_config_reg_u reg_val; - sw_error_t ret = SW_OK; - - ret = qca808x_ptp_misc_config_reg_get(dev_id, phy_id, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.ts_rtc_select = value; - ret = qca808x_ptp_misc_config_reg_set(dev_id, phy_id, ®_val); - return ret; -} - -sw_error_t -qca808x_ptp_ext_imr_reg_mask_bmp_get( - a_uint32_t dev_id, a_uint32_t phy_id, - a_uint32_t *value) -{ - union ptp_ext_imr_reg_u reg_val; - sw_error_t ret = SW_OK; - - ret = qca808x_ptp_ext_imr_reg_get(dev_id, phy_id, ®_val); - *value = reg_val.bf.mask_bmp; - return ret; -} - -sw_error_t -qca808x_ptp_ext_imr_reg_mask_bmp_set( - a_uint32_t dev_id, a_uint32_t phy_id, - a_uint32_t value) -{ - union ptp_ext_imr_reg_u reg_val; - sw_error_t ret = SW_OK; - - ret = qca808x_ptp_ext_imr_reg_get(dev_id, phy_id, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.mask_bmp = value; - ret = qca808x_ptp_ext_imr_reg_set(dev_id, phy_id, ®_val); - return ret; -} - -sw_error_t -qca808x_ptp_ext_isr_reg_status_bmp_get( - a_uint32_t dev_id, a_uint32_t phy_id, - a_uint32_t *value) -{ - union ptp_ext_isr_reg_u reg_val; - sw_error_t ret = SW_OK; - - ret = qca808x_ptp_ext_isr_reg_get(dev_id, phy_id, ®_val); - *value = reg_val.bf.status_bmp; - return ret; -} - -sw_error_t -qca808x_ptp_ext_isr_reg_status_bmp_set( - a_uint32_t dev_id, a_uint32_t phy_id, - a_uint32_t value) -{ - union ptp_ext_isr_reg_u reg_val; - sw_error_t ret = SW_OK; - - ret = qca808x_ptp_ext_isr_reg_get(dev_id, phy_id, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.status_bmp = value; - ret = qca808x_ptp_ext_isr_reg_set(dev_id, phy_id, ®_val); - return ret; -} - -sw_error_t -qca808x_ptp_rtc_ext_conf_reg_rtc_snapshot_get( - a_uint32_t dev_id, a_uint32_t phy_id, - a_uint32_t *value) -{ - union ptp_rtc_ext_conf_reg_u reg_val; - sw_error_t ret = SW_OK; - - ret = qca808x_ptp_rtc_ext_conf_reg_get(dev_id, phy_id, ®_val); - *value = reg_val.bf.rtc_snapshot; - return ret; -} - -sw_error_t -qca808x_ptp_rtc_ext_conf_reg_rtc_snapshot_set( - a_uint32_t dev_id, a_uint32_t phy_id, - a_uint32_t value) -{ - union ptp_rtc_ext_conf_reg_u reg_val; - sw_error_t ret = SW_OK; - - ret = qca808x_ptp_rtc_ext_conf_reg_get(dev_id, phy_id, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.rtc_snapshot = value; - ret = qca808x_ptp_rtc_ext_conf_reg_set(dev_id, phy_id, ®_val); - return ret; -} - -sw_error_t -qca808x_ptp_rtc_ext_conf_reg_set_incval_mode_get( - a_uint32_t dev_id, a_uint32_t phy_id, - a_uint32_t *value) -{ - union ptp_rtc_ext_conf_reg_u reg_val; - sw_error_t ret = SW_OK; - - ret = qca808x_ptp_rtc_ext_conf_reg_get(dev_id, phy_id, ®_val); - *value = reg_val.bf.set_incval_mode; - return ret; -} - -sw_error_t -qca808x_ptp_rtc_ext_conf_reg_set_incval_mode_set( - a_uint32_t dev_id, a_uint32_t phy_id, - a_uint32_t value) -{ - union ptp_rtc_ext_conf_reg_u reg_val; - sw_error_t ret = SW_OK; - - ret = qca808x_ptp_rtc_ext_conf_reg_get(dev_id, phy_id, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.set_incval_mode = value; - ret = qca808x_ptp_rtc_ext_conf_reg_set(dev_id, phy_id, ®_val); - return ret; -} - -sw_error_t -qca808x_ptp_rtc_ext_conf_reg_load_rtc_get( - a_uint32_t dev_id, a_uint32_t phy_id, - a_uint32_t *value) -{ - union ptp_rtc_ext_conf_reg_u reg_val; - sw_error_t ret = SW_OK; - - ret = qca808x_ptp_rtc_ext_conf_reg_get(dev_id, phy_id, ®_val); - *value = reg_val.bf.load_rtc; - return ret; -} - -sw_error_t -qca808x_ptp_rtc_ext_conf_reg_load_rtc_set( - a_uint32_t dev_id, a_uint32_t phy_id, - a_uint32_t value) -{ - union ptp_rtc_ext_conf_reg_u reg_val; - sw_error_t ret = SW_OK; - - ret = qca808x_ptp_rtc_ext_conf_reg_get(dev_id, phy_id, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.load_rtc = value; - ret = qca808x_ptp_rtc_ext_conf_reg_set(dev_id, phy_id, ®_val); - return ret; -} - -sw_error_t -qca808x_ptp_rtc_ext_conf_reg_clear_rtc_get( - a_uint32_t dev_id, a_uint32_t phy_id, - a_uint32_t *value) -{ - union ptp_rtc_ext_conf_reg_u reg_val; - sw_error_t ret = SW_OK; - - ret = qca808x_ptp_rtc_ext_conf_reg_get(dev_id, phy_id, ®_val); - *value = reg_val.bf.clear_rtc; - return ret; -} - -sw_error_t -qca808x_ptp_rtc_ext_conf_reg_clear_rtc_set( - a_uint32_t dev_id, a_uint32_t phy_id, - a_uint32_t value) -{ - union ptp_rtc_ext_conf_reg_u reg_val; - sw_error_t ret = SW_OK; - - ret = qca808x_ptp_rtc_ext_conf_reg_get(dev_id, phy_id, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.clear_rtc = value; - ret = qca808x_ptp_rtc_ext_conf_reg_set(dev_id, phy_id, ®_val); - return ret; -} - -sw_error_t -qca808x_ptp_rtc_ext_conf_reg_rtc_read_mode_get( - a_uint32_t dev_id, a_uint32_t phy_id, - a_uint32_t *value) -{ - union ptp_rtc_ext_conf_reg_u reg_val; - sw_error_t ret = SW_OK; - - ret = qca808x_ptp_rtc_ext_conf_reg_get(dev_id, phy_id, ®_val); - *value = reg_val.bf.rtc_read_mode; - return ret; -} - -sw_error_t -qca808x_ptp_rtc_ext_conf_reg_rtc_read_mode_set( - a_uint32_t dev_id, a_uint32_t phy_id, - a_uint32_t value) -{ - union ptp_rtc_ext_conf_reg_u reg_val; - sw_error_t ret = SW_OK; - - ret = qca808x_ptp_rtc_ext_conf_reg_get(dev_id, phy_id, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.rtc_read_mode = value; - ret = qca808x_ptp_rtc_ext_conf_reg_set(dev_id, phy_id, ®_val); - return ret; -} - -sw_error_t -qca808x_ptp_rtc_ext_conf_reg_select_output_waveform_get( - a_uint32_t dev_id, a_uint32_t phy_id, - a_uint32_t *value) -{ - union ptp_rtc_ext_conf_reg_u reg_val; - sw_error_t ret = SW_OK; - - ret = qca808x_ptp_rtc_ext_conf_reg_get(dev_id, phy_id, ®_val); - *value = reg_val.bf.select_output_waveform; - return ret; -} - -sw_error_t -qca808x_ptp_rtc_ext_conf_reg_select_output_waveform_set( - a_uint32_t dev_id, a_uint32_t phy_id, - a_uint32_t value) -{ - union ptp_rtc_ext_conf_reg_u reg_val; - sw_error_t ret = SW_OK; - - ret = qca808x_ptp_rtc_ext_conf_reg_get(dev_id, phy_id, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.select_output_waveform = value; - ret = qca808x_ptp_rtc_ext_conf_reg_set(dev_id, phy_id, ®_val); - return ret; -} - -sw_error_t -qca808x_ptp_rtc_ext_conf_reg_set_incval_valid_get( - a_uint32_t dev_id, a_uint32_t phy_id, - a_uint32_t *value) -{ - union ptp_rtc_ext_conf_reg_u reg_val; - sw_error_t ret = SW_OK; - - ret = qca808x_ptp_rtc_ext_conf_reg_get(dev_id, phy_id, ®_val); - *value = reg_val.bf.set_incval_valid; - return ret; -} - -sw_error_t -qca808x_ptp_rtc_ext_conf_reg_set_incval_valid_set( - a_uint32_t dev_id, a_uint32_t phy_id, - a_uint32_t value) -{ - union ptp_rtc_ext_conf_reg_u reg_val; - sw_error_t ret = SW_OK; - - ret = qca808x_ptp_rtc_ext_conf_reg_get(dev_id, phy_id, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.set_incval_valid = value; - ret = qca808x_ptp_rtc_ext_conf_reg_set(dev_id, phy_id, ®_val); - return ret; -} - -sw_error_t -qca808x_ptp_rtc_preloaded0_reg_ptp_rtc_preloaded_sec_get( - a_uint32_t dev_id, a_uint32_t phy_id, - a_uint32_t *value) -{ - union ptp_rtc_preloaded0_reg_u reg_val; - sw_error_t ret = SW_OK; - - ret = qca808x_ptp_rtc_preloaded0_reg_get(dev_id, phy_id, ®_val); - *value = reg_val.bf.ptp_rtc_preloaded_sec; - return ret; -} - -sw_error_t -qca808x_ptp_rtc_preloaded0_reg_ptp_rtc_preloaded_sec_set( - a_uint32_t dev_id, a_uint32_t phy_id, - a_uint32_t value) -{ - union ptp_rtc_preloaded0_reg_u reg_val; - sw_error_t ret = SW_OK; - - ret = qca808x_ptp_rtc_preloaded0_reg_get(dev_id, phy_id, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.ptp_rtc_preloaded_sec = value; - ret = qca808x_ptp_rtc_preloaded0_reg_set(dev_id, phy_id, ®_val); - return ret; -} - -sw_error_t -qca808x_ptp_rtc_preloaded1_reg_ptp_rtc_preloaded_sec_get( - a_uint32_t dev_id, a_uint32_t phy_id, - a_uint32_t *value) -{ - union ptp_rtc_preloaded1_reg_u reg_val; - sw_error_t ret = SW_OK; - - ret = qca808x_ptp_rtc_preloaded1_reg_get(dev_id, phy_id, ®_val); - *value = reg_val.bf.ptp_rtc_preloaded_sec; - return ret; -} - -sw_error_t -qca808x_ptp_rtc_preloaded1_reg_ptp_rtc_preloaded_sec_set( - a_uint32_t dev_id, a_uint32_t phy_id, - a_uint32_t value) -{ - union ptp_rtc_preloaded1_reg_u reg_val; - sw_error_t ret = SW_OK; - - ret = qca808x_ptp_rtc_preloaded1_reg_get(dev_id, phy_id, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.ptp_rtc_preloaded_sec = value; - ret = qca808x_ptp_rtc_preloaded1_reg_set(dev_id, phy_id, ®_val); - return ret; -} - -sw_error_t -qca808x_ptp_rtc_preloaded2_reg_ptp_rtc_preloaded_sec_get( - a_uint32_t dev_id, a_uint32_t phy_id, - a_uint32_t *value) -{ - union ptp_rtc_preloaded2_reg_u reg_val; - sw_error_t ret = SW_OK; - - ret = qca808x_ptp_rtc_preloaded2_reg_get(dev_id, phy_id, ®_val); - *value = reg_val.bf.ptp_rtc_preloaded_sec; - return ret; -} - -sw_error_t -qca808x_ptp_rtc_preloaded2_reg_ptp_rtc_preloaded_sec_set( - a_uint32_t dev_id, a_uint32_t phy_id, - a_uint32_t value) -{ - union ptp_rtc_preloaded2_reg_u reg_val; - sw_error_t ret = SW_OK; - - ret = qca808x_ptp_rtc_preloaded2_reg_get(dev_id, phy_id, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.ptp_rtc_preloaded_sec = value; - ret = qca808x_ptp_rtc_preloaded2_reg_set(dev_id, phy_id, ®_val); - return ret; -} - -sw_error_t -qca808x_ptp_rtc_preloaded3_reg_ptp_rtc_preloaded_nisec_get( - a_uint32_t dev_id, a_uint32_t phy_id, - a_uint32_t *value) -{ - union ptp_rtc_preloaded3_reg_u reg_val; - sw_error_t ret = SW_OK; - - ret = qca808x_ptp_rtc_preloaded3_reg_get(dev_id, phy_id, ®_val); - *value = reg_val.bf.ptp_rtc_preloaded_nisec; - return ret; -} - -sw_error_t -qca808x_ptp_rtc_preloaded3_reg_ptp_rtc_preloaded_nisec_set( - a_uint32_t dev_id, a_uint32_t phy_id, - a_uint32_t value) -{ - union ptp_rtc_preloaded3_reg_u reg_val; - sw_error_t ret = SW_OK; - - ret = qca808x_ptp_rtc_preloaded3_reg_get(dev_id, phy_id, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.ptp_rtc_preloaded_nisec = value; - ret = qca808x_ptp_rtc_preloaded3_reg_set(dev_id, phy_id, ®_val); - return ret; -} - -sw_error_t -qca808x_ptp_rtc_preloaded4_reg_ptp_rtc_preloaded_nisec_get( - a_uint32_t dev_id, a_uint32_t phy_id, - a_uint32_t *value) -{ - union ptp_rtc_preloaded4_reg_u reg_val; - sw_error_t ret = SW_OK; - - ret = qca808x_ptp_rtc_preloaded4_reg_get(dev_id, phy_id, ®_val); - *value = reg_val.bf.ptp_rtc_preloaded_nisec; - return ret; -} - -sw_error_t -qca808x_ptp_rtc_preloaded4_reg_ptp_rtc_preloaded_nisec_set( - a_uint32_t dev_id, a_uint32_t phy_id, - a_uint32_t value) -{ - union ptp_rtc_preloaded4_reg_u reg_val; - sw_error_t ret = SW_OK; - - ret = qca808x_ptp_rtc_preloaded4_reg_get(dev_id, phy_id, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.ptp_rtc_preloaded_nisec = value; - ret = qca808x_ptp_rtc_preloaded4_reg_set(dev_id, phy_id, ®_val); - return ret; -} - -sw_error_t -qca808x_ptp_gm_conf0_reg_gm_pps_sync_get( - a_uint32_t dev_id, a_uint32_t phy_id, - a_uint32_t *value) -{ - union ptp_gm_conf0_reg_u reg_val; - sw_error_t ret = SW_OK; - - ret = qca808x_ptp_gm_conf0_reg_get(dev_id, phy_id, ®_val); - *value = reg_val.bf.gm_pps_sync; - return ret; -} - -sw_error_t -qca808x_ptp_gm_conf0_reg_gm_pps_sync_set( - a_uint32_t dev_id, a_uint32_t phy_id, - a_uint32_t value) -{ - union ptp_gm_conf0_reg_u reg_val; - sw_error_t ret = SW_OK; - - ret = qca808x_ptp_gm_conf0_reg_get(dev_id, phy_id, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.gm_pps_sync = value; - ret = qca808x_ptp_gm_conf0_reg_set(dev_id, phy_id, ®_val); - return ret; -} - -sw_error_t -qca808x_ptp_gm_conf0_reg_gm_pll_mode_get( - a_uint32_t dev_id, a_uint32_t phy_id, - a_uint32_t *value) -{ - union ptp_gm_conf0_reg_u reg_val; - sw_error_t ret = SW_OK; - - ret = qca808x_ptp_gm_conf0_reg_get(dev_id, phy_id, ®_val); - *value = reg_val.bf.gm_pll_mode; - return ret; -} - -sw_error_t -qca808x_ptp_gm_conf0_reg_gm_pll_mode_set( - a_uint32_t dev_id, a_uint32_t phy_id, - a_uint32_t value) -{ - union ptp_gm_conf0_reg_u reg_val; - sw_error_t ret = SW_OK; - - ret = qca808x_ptp_gm_conf0_reg_get(dev_id, phy_id, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.gm_pll_mode = value; - ret = qca808x_ptp_gm_conf0_reg_set(dev_id, phy_id, ®_val); - return ret; -} - -sw_error_t -qca808x_ptp_gm_conf0_reg_gm_maxfreq_offset_get( - a_uint32_t dev_id, a_uint32_t phy_id, - a_uint32_t *value) -{ - union ptp_gm_conf0_reg_u reg_val; - sw_error_t ret = SW_OK; - - ret = qca808x_ptp_gm_conf0_reg_get(dev_id, phy_id, ®_val); - *value = reg_val.bf.gm_maxfreq_offset; - return ret; -} - -sw_error_t -qca808x_ptp_gm_conf0_reg_gm_maxfreq_offset_set( - a_uint32_t dev_id, a_uint32_t phy_id, - a_uint32_t value) -{ - union ptp_gm_conf0_reg_u reg_val; - sw_error_t ret = SW_OK; - - ret = qca808x_ptp_gm_conf0_reg_get(dev_id, phy_id, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.gm_maxfreq_offset = value; - ret = qca808x_ptp_gm_conf0_reg_set(dev_id, phy_id, ®_val); - return ret; -} - -sw_error_t -qca808x_ptp_gm_conf0_reg_grandmaster_mode_get( - a_uint32_t dev_id, a_uint32_t phy_id, - a_uint32_t *value) -{ - union ptp_gm_conf0_reg_u reg_val; - sw_error_t ret = SW_OK; - - ret = qca808x_ptp_gm_conf0_reg_get(dev_id, phy_id, ®_val); - *value = reg_val.bf.grandmaster_mode; - return ret; -} - -sw_error_t -qca808x_ptp_gm_conf0_reg_grandmaster_mode_set( - a_uint32_t dev_id, a_uint32_t phy_id, - a_uint32_t value) -{ - union ptp_gm_conf0_reg_u reg_val; - sw_error_t ret = SW_OK; - - ret = qca808x_ptp_gm_conf0_reg_get(dev_id, phy_id, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.grandmaster_mode = value; - ret = qca808x_ptp_gm_conf0_reg_set(dev_id, phy_id, ®_val); - return ret; -} - -sw_error_t -qca808x_ptp_gm_conf1_reg_gm_kp_ldn_get( - a_uint32_t dev_id, a_uint32_t phy_id, - a_uint32_t *value) -{ - union ptp_gm_conf1_reg_u reg_val; - sw_error_t ret = SW_OK; - - ret = qca808x_ptp_gm_conf1_reg_get(dev_id, phy_id, ®_val); - *value = reg_val.bf.gm_kp_ldn; - return ret; -} - -sw_error_t -qca808x_ptp_gm_conf1_reg_gm_kp_ldn_set( - a_uint32_t dev_id, a_uint32_t phy_id, - a_uint32_t value) -{ - union ptp_gm_conf1_reg_u reg_val; - sw_error_t ret = SW_OK; - - ret = qca808x_ptp_gm_conf1_reg_get(dev_id, phy_id, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.gm_kp_ldn = value; - ret = qca808x_ptp_gm_conf1_reg_set(dev_id, phy_id, ®_val); - return ret; -} - -sw_error_t -qca808x_ptp_gm_conf1_reg_gm_ki_ldn_get( - a_uint32_t dev_id, a_uint32_t phy_id, - a_uint32_t *value) -{ - union ptp_gm_conf1_reg_u reg_val; - sw_error_t ret = SW_OK; - - ret = qca808x_ptp_gm_conf1_reg_get(dev_id, phy_id, ®_val); - *value = reg_val.bf.gm_ki_ldn; - return ret; -} - -sw_error_t -qca808x_ptp_gm_conf1_reg_gm_ki_ldn_set( - a_uint32_t dev_id, a_uint32_t phy_id, - a_uint32_t value) -{ - union ptp_gm_conf1_reg_u reg_val; - sw_error_t ret = SW_OK; - - ret = qca808x_ptp_gm_conf1_reg_get(dev_id, phy_id, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.gm_ki_ldn = value; - ret = qca808x_ptp_gm_conf1_reg_set(dev_id, phy_id, ®_val); - return ret; -} - -sw_error_t -qca808x_ptp_ppsin_ts0_reg_rx_ts_sec_get( - a_uint32_t dev_id, a_uint32_t phy_id, - a_uint32_t *value) -{ - union ptp_ppsin_ts0_reg_u reg_val; - sw_error_t ret = SW_OK; - - ret = qca808x_ptp_ppsin_ts0_reg_get(dev_id, phy_id, ®_val); - *value = reg_val.bf.rx_ts_sec; - return ret; -} - -sw_error_t -qca808x_ptp_ppsin_ts0_reg_rx_ts_sec_set( - a_uint32_t dev_id, a_uint32_t phy_id, - a_uint32_t value) -{ - union ptp_ppsin_ts0_reg_u reg_val; - sw_error_t ret = SW_OK; - - ret = qca808x_ptp_ppsin_ts0_reg_get(dev_id, phy_id, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.rx_ts_sec = value; - ret = qca808x_ptp_ppsin_ts0_reg_set(dev_id, phy_id, ®_val); - return ret; -} - -sw_error_t -qca808x_ptp_ppsin_ts1_reg_rx_ts_sec_get( - a_uint32_t dev_id, a_uint32_t phy_id, - a_uint32_t *value) -{ - union ptp_ppsin_ts1_reg_u reg_val; - sw_error_t ret = SW_OK; - - ret = qca808x_ptp_ppsin_ts1_reg_get(dev_id, phy_id, ®_val); - *value = reg_val.bf.rx_ts_sec; - return ret; -} - -sw_error_t -qca808x_ptp_ppsin_ts1_reg_rx_ts_sec_set( - a_uint32_t dev_id, a_uint32_t phy_id, - a_uint32_t value) -{ - union ptp_ppsin_ts1_reg_u reg_val; - sw_error_t ret = SW_OK; - - ret = qca808x_ptp_ppsin_ts1_reg_get(dev_id, phy_id, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.rx_ts_sec = value; - ret = qca808x_ptp_ppsin_ts1_reg_set(dev_id, phy_id, ®_val); - return ret; -} - -sw_error_t -qca808x_ptp_ppsin_ts2_reg_rx_ts_sec_get( - a_uint32_t dev_id, a_uint32_t phy_id, - a_uint32_t *value) -{ - union ptp_ppsin_ts2_reg_u reg_val; - sw_error_t ret = SW_OK; - - ret = qca808x_ptp_ppsin_ts2_reg_get(dev_id, phy_id, ®_val); - *value = reg_val.bf.rx_ts_sec; - return ret; -} - -sw_error_t -qca808x_ptp_ppsin_ts2_reg_rx_ts_sec_set( - a_uint32_t dev_id, a_uint32_t phy_id, - a_uint32_t value) -{ - union ptp_ppsin_ts2_reg_u reg_val; - sw_error_t ret = SW_OK; - - ret = qca808x_ptp_ppsin_ts2_reg_get(dev_id, phy_id, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.rx_ts_sec = value; - ret = qca808x_ptp_ppsin_ts2_reg_set(dev_id, phy_id, ®_val); - return ret; -} - -sw_error_t -qca808x_ptp_ppsin_ts3_reg_rx_ts_nsec_get( - a_uint32_t dev_id, a_uint32_t phy_id, - a_uint32_t *value) -{ - union ptp_ppsin_ts3_reg_u reg_val; - sw_error_t ret = SW_OK; - - ret = qca808x_ptp_ppsin_ts3_reg_get(dev_id, phy_id, ®_val); - *value = reg_val.bf.rx_ts_nsec; - return ret; -} - -sw_error_t -qca808x_ptp_ppsin_ts3_reg_rx_ts_nsec_set( - a_uint32_t dev_id, a_uint32_t phy_id, - a_uint32_t value) -{ - union ptp_ppsin_ts3_reg_u reg_val; - sw_error_t ret = SW_OK; - - ret = qca808x_ptp_ppsin_ts3_reg_get(dev_id, phy_id, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.rx_ts_nsec = value; - ret = qca808x_ptp_ppsin_ts3_reg_set(dev_id, phy_id, ®_val); - return ret; -} - -sw_error_t -qca808x_ptp_ppsin_ts4_reg_rx_ts_nsec_get( - a_uint32_t dev_id, a_uint32_t phy_id, - a_uint32_t *value) -{ - union ptp_ppsin_ts4_reg_u reg_val; - sw_error_t ret = SW_OK; - - ret = qca808x_ptp_ppsin_ts4_reg_get(dev_id, phy_id, ®_val); - *value = reg_val.bf.rx_ts_nsec; - return ret; -} - -sw_error_t -qca808x_ptp_ppsin_ts4_reg_rx_ts_nsec_set( - a_uint32_t dev_id, a_uint32_t phy_id, - a_uint32_t value) -{ - union ptp_ppsin_ts4_reg_u reg_val; - sw_error_t ret = SW_OK; - - ret = qca808x_ptp_ppsin_ts4_reg_get(dev_id, phy_id, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.rx_ts_nsec = value; - ret = qca808x_ptp_ppsin_ts4_reg_set(dev_id, phy_id, ®_val); - return ret; -} - -sw_error_t -qca808x_ptp_hwpll_inc0_reg_ptp_rtc_inc_nfs1_get( - a_uint32_t dev_id, a_uint32_t phy_id, - a_uint32_t *value) -{ - union ptp_hwpll_inc0_reg_u reg_val; - sw_error_t ret = SW_OK; - - ret = qca808x_ptp_hwpll_inc0_reg_get(dev_id, phy_id, ®_val); - *value = reg_val.bf.ptp_rtc_inc_nfs1; - return ret; -} - -sw_error_t -qca808x_ptp_hwpll_inc0_reg_ptp_rtc_inc_nfs1_set( - a_uint32_t dev_id, a_uint32_t phy_id, - a_uint32_t value) -{ - union ptp_hwpll_inc0_reg_u reg_val; - sw_error_t ret = SW_OK; - - ret = qca808x_ptp_hwpll_inc0_reg_get(dev_id, phy_id, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.ptp_rtc_inc_nfs1 = value; - ret = qca808x_ptp_hwpll_inc0_reg_set(dev_id, phy_id, ®_val); - return ret; -} - -sw_error_t -qca808x_ptp_hwpll_inc0_reg_ptp_rtc_inc_nis_get( - a_uint32_t dev_id, a_uint32_t phy_id, - a_uint32_t *value) -{ - union ptp_hwpll_inc0_reg_u reg_val; - sw_error_t ret = SW_OK; - - ret = qca808x_ptp_hwpll_inc0_reg_get(dev_id, phy_id, ®_val); - *value = reg_val.bf.ptp_rtc_inc_nis; - return ret; -} - -sw_error_t -qca808x_ptp_hwpll_inc0_reg_ptp_rtc_inc_nis_set( - a_uint32_t dev_id, a_uint32_t phy_id, - a_uint32_t value) -{ - union ptp_hwpll_inc0_reg_u reg_val; - sw_error_t ret = SW_OK; - - ret = qca808x_ptp_hwpll_inc0_reg_get(dev_id, phy_id, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.ptp_rtc_inc_nis = value; - ret = qca808x_ptp_hwpll_inc0_reg_set(dev_id, phy_id, ®_val); - return ret; -} - -sw_error_t -qca808x_ptp_hwpll_inc1_reg_ptp_rtc_inc_nfs0_get( - a_uint32_t dev_id, a_uint32_t phy_id, - a_uint32_t *value) -{ - union ptp_hwpll_inc1_reg_u reg_val; - sw_error_t ret = SW_OK; - - ret = qca808x_ptp_hwpll_inc1_reg_get(dev_id, phy_id, ®_val); - *value = reg_val.bf.ptp_rtc_inc_nfs0; - return ret; -} - -sw_error_t -qca808x_ptp_hwpll_inc1_reg_ptp_rtc_inc_nfs0_set( - a_uint32_t dev_id, a_uint32_t phy_id, - a_uint32_t value) -{ - union ptp_hwpll_inc1_reg_u reg_val; - sw_error_t ret = SW_OK; - - ret = qca808x_ptp_hwpll_inc1_reg_get(dev_id, phy_id, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.ptp_rtc_inc_nfs0 = value; - ret = qca808x_ptp_hwpll_inc1_reg_set(dev_id, phy_id, ®_val); - return ret; -} - -sw_error_t -qca808x_ptp_ppsin_latency_reg_ptp_ppsin_latency_sign_get( - a_uint32_t dev_id, a_uint32_t phy_id, - a_uint32_t *value) -{ - union ptp_ppsin_latency_reg_u reg_val; - sw_error_t ret = SW_OK; - - ret = qca808x_ptp_ppsin_latency_reg_get(dev_id, phy_id, ®_val); - *value = reg_val.bf.ptp_ppsin_latency_sign; - return ret; -} - -sw_error_t -qca808x_ptp_ppsin_latency_reg_ptp_ppsin_latency_sign_set( - a_uint32_t dev_id, a_uint32_t phy_id, - a_uint32_t value) -{ - union ptp_ppsin_latency_reg_u reg_val; - sw_error_t ret = SW_OK; - - ret = qca808x_ptp_ppsin_latency_reg_get(dev_id, phy_id, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.ptp_ppsin_latency_sign = value; - ret = qca808x_ptp_ppsin_latency_reg_set(dev_id, phy_id, ®_val); - return ret; -} - -sw_error_t -qca808x_ptp_ppsin_latency_reg_ptp_ppsin_latency_value_get( - a_uint32_t dev_id, a_uint32_t phy_id, - a_uint32_t *value) -{ - union ptp_ppsin_latency_reg_u reg_val; - sw_error_t ret = SW_OK; - - ret = qca808x_ptp_ppsin_latency_reg_get(dev_id, phy_id, ®_val); - *value = reg_val.bf.ptp_ppsin_latency_value; - return ret; -} - -sw_error_t -qca808x_ptp_ppsin_latency_reg_ptp_ppsin_latency_value_set( - a_uint32_t dev_id, a_uint32_t phy_id, - a_uint32_t value) -{ - union ptp_ppsin_latency_reg_u reg_val; - sw_error_t ret = SW_OK; - - ret = qca808x_ptp_ppsin_latency_reg_get(dev_id, phy_id, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.ptp_ppsin_latency_value = value; - ret = qca808x_ptp_ppsin_latency_reg_set(dev_id, phy_id, ®_val); - return ret; -} - -sw_error_t -qca808x_ptp_trigger0_config_reg_force_value_get( - a_uint32_t dev_id, a_uint32_t phy_id, - a_uint32_t *value) -{ - union ptp_trigger0_config_reg_u reg_val; - sw_error_t ret = SW_OK; - - ret = qca808x_ptp_trigger0_config_reg_get(dev_id, phy_id, ®_val); - *value = reg_val.bf.force_value; - return ret; -} - -sw_error_t -qca808x_ptp_trigger0_config_reg_force_value_set( - a_uint32_t dev_id, a_uint32_t phy_id, - a_uint32_t value) -{ - union ptp_trigger0_config_reg_u reg_val; - sw_error_t ret = SW_OK; - - ret = qca808x_ptp_trigger0_config_reg_get(dev_id, phy_id, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.force_value = value; - ret = qca808x_ptp_trigger0_config_reg_set(dev_id, phy_id, ®_val); - return ret; -} - -sw_error_t -qca808x_ptp_trigger0_config_reg_pattern_get( - a_uint32_t dev_id, a_uint32_t phy_id, - a_uint32_t *value) -{ - union ptp_trigger0_config_reg_u reg_val; - sw_error_t ret = SW_OK; - - ret = qca808x_ptp_trigger0_config_reg_get(dev_id, phy_id, ®_val); - *value = reg_val.bf.pattern; - return ret; -} - -sw_error_t -qca808x_ptp_trigger0_config_reg_pattern_set( - a_uint32_t dev_id, a_uint32_t phy_id, - a_uint32_t value) -{ - union ptp_trigger0_config_reg_u reg_val; - sw_error_t ret = SW_OK; - - ret = qca808x_ptp_trigger0_config_reg_get(dev_id, phy_id, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.pattern = value; - ret = qca808x_ptp_trigger0_config_reg_set(dev_id, phy_id, ®_val); - return ret; -} - -sw_error_t -qca808x_ptp_trigger0_config_reg_status_get( - a_uint32_t dev_id, a_uint32_t phy_id, - a_uint32_t *value) -{ - union ptp_trigger0_config_reg_u reg_val; - sw_error_t ret = SW_OK; - - ret = qca808x_ptp_trigger0_config_reg_get(dev_id, phy_id, ®_val); - *value = reg_val.bf.status; - return ret; -} - -sw_error_t -qca808x_ptp_trigger0_config_reg_status_set( - a_uint32_t dev_id, a_uint32_t phy_id, - a_uint32_t value) -{ - union ptp_trigger0_config_reg_u reg_val; - sw_error_t ret = SW_OK; - - ret = qca808x_ptp_trigger0_config_reg_get(dev_id, phy_id, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.status = value; - ret = qca808x_ptp_trigger0_config_reg_set(dev_id, phy_id, ®_val); - return ret; -} - -sw_error_t -qca808x_ptp_trigger0_config_reg_force_en_get( - a_uint32_t dev_id, a_uint32_t phy_id, - a_uint32_t *value) -{ - union ptp_trigger0_config_reg_u reg_val; - sw_error_t ret = SW_OK; - - ret = qca808x_ptp_trigger0_config_reg_get(dev_id, phy_id, ®_val); - *value = reg_val.bf.force_en; - return ret; -} - -sw_error_t -qca808x_ptp_trigger0_config_reg_force_en_set( - a_uint32_t dev_id, a_uint32_t phy_id, - a_uint32_t value) -{ - union ptp_trigger0_config_reg_u reg_val; - sw_error_t ret = SW_OK; - - ret = qca808x_ptp_trigger0_config_reg_get(dev_id, phy_id, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.force_en = value; - ret = qca808x_ptp_trigger0_config_reg_set(dev_id, phy_id, ®_val); - return ret; -} - -sw_error_t -qca808x_ptp_trigger0_config_reg_setting_get( - a_uint32_t dev_id, a_uint32_t phy_id, - a_uint32_t *value) -{ - union ptp_trigger0_config_reg_u reg_val; - sw_error_t ret = SW_OK; - - ret = qca808x_ptp_trigger0_config_reg_get(dev_id, phy_id, ®_val); - *value = reg_val.bf.setting; - return ret; -} - -sw_error_t -qca808x_ptp_trigger0_config_reg_setting_set( - a_uint32_t dev_id, a_uint32_t phy_id, - a_uint32_t value) -{ - union ptp_trigger0_config_reg_u reg_val; - sw_error_t ret = SW_OK; - - ret = qca808x_ptp_trigger0_config_reg_get(dev_id, phy_id, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.setting = value; - ret = qca808x_ptp_trigger0_config_reg_set(dev_id, phy_id, ®_val); - return ret; -} - -sw_error_t -qca808x_ptp_trigger0_config_reg_notify_get( - a_uint32_t dev_id, a_uint32_t phy_id, - a_uint32_t *value) -{ - union ptp_trigger0_config_reg_u reg_val; - sw_error_t ret = SW_OK; - - ret = qca808x_ptp_trigger0_config_reg_get(dev_id, phy_id, ®_val); - *value = reg_val.bf.notify; - return ret; -} - -sw_error_t -qca808x_ptp_trigger0_config_reg_notify_set( - a_uint32_t dev_id, a_uint32_t phy_id, - a_uint32_t value) -{ - union ptp_trigger0_config_reg_u reg_val; - sw_error_t ret = SW_OK; - - ret = qca808x_ptp_trigger0_config_reg_get(dev_id, phy_id, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.notify = value; - ret = qca808x_ptp_trigger0_config_reg_set(dev_id, phy_id, ®_val); - return ret; -} - -sw_error_t -qca808x_ptp_trigger0_config_reg_if_late_get( - a_uint32_t dev_id, a_uint32_t phy_id, - a_uint32_t *value) -{ - union ptp_trigger0_config_reg_u reg_val; - sw_error_t ret = SW_OK; - - ret = qca808x_ptp_trigger0_config_reg_get(dev_id, phy_id, ®_val); - *value = reg_val.bf.if_late; - return ret; -} - -sw_error_t -qca808x_ptp_trigger0_config_reg_if_late_set( - a_uint32_t dev_id, a_uint32_t phy_id, - a_uint32_t value) -{ - union ptp_trigger0_config_reg_u reg_val; - sw_error_t ret = SW_OK; - - ret = qca808x_ptp_trigger0_config_reg_get(dev_id, phy_id, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.if_late = value; - ret = qca808x_ptp_trigger0_config_reg_set(dev_id, phy_id, ®_val); - return ret; -} - -sw_error_t -qca808x_ptp_trigger0_status_reg_error_get( - a_uint32_t dev_id, a_uint32_t phy_id, - a_uint32_t *value) -{ - union ptp_trigger0_status_reg_u reg_val; - sw_error_t ret = SW_OK; - - ret = qca808x_ptp_trigger0_status_reg_get(dev_id, phy_id, ®_val); - *value = reg_val.bf.error; - return ret; -} - -sw_error_t -qca808x_ptp_trigger0_status_reg_error_set( - a_uint32_t dev_id, a_uint32_t phy_id, - a_uint32_t value) -{ - union ptp_trigger0_status_reg_u reg_val; - sw_error_t ret = SW_OK; - - ret = qca808x_ptp_trigger0_status_reg_get(dev_id, phy_id, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.error = value; - ret = qca808x_ptp_trigger0_status_reg_set(dev_id, phy_id, ®_val); - return ret; -} - -sw_error_t -qca808x_ptp_trigger0_status_reg_active_get( - a_uint32_t dev_id, a_uint32_t phy_id, - a_uint32_t *value) -{ - union ptp_trigger0_status_reg_u reg_val; - sw_error_t ret = SW_OK; - - ret = qca808x_ptp_trigger0_status_reg_get(dev_id, phy_id, ®_val); - *value = reg_val.bf.active; - return ret; -} - -sw_error_t -qca808x_ptp_trigger0_status_reg_active_set( - a_uint32_t dev_id, a_uint32_t phy_id, - a_uint32_t value) -{ - union ptp_trigger0_status_reg_u reg_val; - sw_error_t ret = SW_OK; - - ret = qca808x_ptp_trigger0_status_reg_get(dev_id, phy_id, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.active = value; - ret = qca808x_ptp_trigger0_status_reg_set(dev_id, phy_id, ®_val); - return ret; -} - -sw_error_t -qca808x_ptp_trigger0_status_reg_finished_get( - a_uint32_t dev_id, a_uint32_t phy_id, - a_uint32_t *value) -{ - union ptp_trigger0_status_reg_u reg_val; - sw_error_t ret = SW_OK; - - ret = qca808x_ptp_trigger0_status_reg_get(dev_id, phy_id, ®_val); - *value = reg_val.bf.finished; - return ret; -} - -sw_error_t -qca808x_ptp_trigger0_status_reg_finished_set( - a_uint32_t dev_id, a_uint32_t phy_id, - a_uint32_t value) -{ - union ptp_trigger0_status_reg_u reg_val; - sw_error_t ret = SW_OK; - - ret = qca808x_ptp_trigger0_status_reg_get(dev_id, phy_id, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.finished = value; - ret = qca808x_ptp_trigger0_status_reg_set(dev_id, phy_id, ®_val); - return ret; -} - -sw_error_t -qca808x_ptp_trigger1_config_reg_force_value_get( - a_uint32_t dev_id, a_uint32_t phy_id, - a_uint32_t *value) -{ - union ptp_trigger1_config_reg_u reg_val; - sw_error_t ret = SW_OK; - - ret = qca808x_ptp_trigger1_config_reg_get(dev_id, phy_id, ®_val); - *value = reg_val.bf.force_value; - return ret; -} - -sw_error_t -qca808x_ptp_trigger1_config_reg_force_value_set( - a_uint32_t dev_id, a_uint32_t phy_id, - a_uint32_t value) -{ - union ptp_trigger1_config_reg_u reg_val; - sw_error_t ret = SW_OK; - - ret = qca808x_ptp_trigger1_config_reg_get(dev_id, phy_id, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.force_value = value; - ret = qca808x_ptp_trigger1_config_reg_set(dev_id, phy_id, ®_val); - return ret; -} - -sw_error_t -qca808x_ptp_trigger1_config_reg_pattern_get( - a_uint32_t dev_id, a_uint32_t phy_id, - a_uint32_t *value) -{ - union ptp_trigger1_config_reg_u reg_val; - sw_error_t ret = SW_OK; - - ret = qca808x_ptp_trigger1_config_reg_get(dev_id, phy_id, ®_val); - *value = reg_val.bf.pattern; - return ret; -} - -sw_error_t -qca808x_ptp_trigger1_config_reg_pattern_set( - a_uint32_t dev_id, a_uint32_t phy_id, - a_uint32_t value) -{ - union ptp_trigger1_config_reg_u reg_val; - sw_error_t ret = SW_OK; - - ret = qca808x_ptp_trigger1_config_reg_get(dev_id, phy_id, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.pattern = value; - ret = qca808x_ptp_trigger1_config_reg_set(dev_id, phy_id, ®_val); - return ret; -} - -sw_error_t -qca808x_ptp_trigger1_config_reg_status_get( - a_uint32_t dev_id, a_uint32_t phy_id, - a_uint32_t *value) -{ - union ptp_trigger1_config_reg_u reg_val; - sw_error_t ret = SW_OK; - - ret = qca808x_ptp_trigger1_config_reg_get(dev_id, phy_id, ®_val); - *value = reg_val.bf.status; - return ret; -} - -sw_error_t -qca808x_ptp_trigger1_config_reg_status_set( - a_uint32_t dev_id, a_uint32_t phy_id, - a_uint32_t value) -{ - union ptp_trigger1_config_reg_u reg_val; - sw_error_t ret = SW_OK; - - ret = qca808x_ptp_trigger1_config_reg_get(dev_id, phy_id, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.status = value; - ret = qca808x_ptp_trigger1_config_reg_set(dev_id, phy_id, ®_val); - return ret; -} - -sw_error_t -qca808x_ptp_trigger1_config_reg_force_en_get( - a_uint32_t dev_id, a_uint32_t phy_id, - a_uint32_t *value) -{ - union ptp_trigger1_config_reg_u reg_val; - sw_error_t ret = SW_OK; - - ret = qca808x_ptp_trigger1_config_reg_get(dev_id, phy_id, ®_val); - *value = reg_val.bf.force_en; - return ret; -} - -sw_error_t -qca808x_ptp_trigger1_config_reg_force_en_set( - a_uint32_t dev_id, a_uint32_t phy_id, - a_uint32_t value) -{ - union ptp_trigger1_config_reg_u reg_val; - sw_error_t ret = SW_OK; - - ret = qca808x_ptp_trigger1_config_reg_get(dev_id, phy_id, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.force_en = value; - ret = qca808x_ptp_trigger1_config_reg_set(dev_id, phy_id, ®_val); - return ret; -} - -sw_error_t -qca808x_ptp_trigger1_config_reg_setting_get( - a_uint32_t dev_id, a_uint32_t phy_id, - a_uint32_t *value) -{ - union ptp_trigger1_config_reg_u reg_val; - sw_error_t ret = SW_OK; - - ret = qca808x_ptp_trigger1_config_reg_get(dev_id, phy_id, ®_val); - *value = reg_val.bf.setting; - return ret; -} - -sw_error_t -qca808x_ptp_trigger1_config_reg_setting_set( - a_uint32_t dev_id, a_uint32_t phy_id, - a_uint32_t value) -{ - union ptp_trigger1_config_reg_u reg_val; - sw_error_t ret = SW_OK; - - ret = qca808x_ptp_trigger1_config_reg_get(dev_id, phy_id, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.setting = value; - ret = qca808x_ptp_trigger1_config_reg_set(dev_id, phy_id, ®_val); - return ret; -} - -sw_error_t -qca808x_ptp_trigger1_config_reg_notify_get( - a_uint32_t dev_id, a_uint32_t phy_id, - a_uint32_t *value) -{ - union ptp_trigger1_config_reg_u reg_val; - sw_error_t ret = SW_OK; - - ret = qca808x_ptp_trigger1_config_reg_get(dev_id, phy_id, ®_val); - *value = reg_val.bf.notify; - return ret; -} - -sw_error_t -qca808x_ptp_trigger1_config_reg_notify_set( - a_uint32_t dev_id, a_uint32_t phy_id, - a_uint32_t value) -{ - union ptp_trigger1_config_reg_u reg_val; - sw_error_t ret = SW_OK; - - ret = qca808x_ptp_trigger1_config_reg_get(dev_id, phy_id, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.notify = value; - ret = qca808x_ptp_trigger1_config_reg_set(dev_id, phy_id, ®_val); - return ret; -} - -sw_error_t -qca808x_ptp_trigger1_config_reg_if_late_get( - a_uint32_t dev_id, a_uint32_t phy_id, - a_uint32_t *value) -{ - union ptp_trigger1_config_reg_u reg_val; - sw_error_t ret = SW_OK; - - ret = qca808x_ptp_trigger1_config_reg_get(dev_id, phy_id, ®_val); - *value = reg_val.bf.if_late; - return ret; -} - -sw_error_t -qca808x_ptp_trigger1_config_reg_if_late_set( - a_uint32_t dev_id, a_uint32_t phy_id, - a_uint32_t value) -{ - union ptp_trigger1_config_reg_u reg_val; - sw_error_t ret = SW_OK; - - ret = qca808x_ptp_trigger1_config_reg_get(dev_id, phy_id, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.if_late = value; - ret = qca808x_ptp_trigger1_config_reg_set(dev_id, phy_id, ®_val); - return ret; -} - -sw_error_t -qca808x_ptp_trigger1_status_reg_error_get( - a_uint32_t dev_id, a_uint32_t phy_id, - a_uint32_t *value) -{ - union ptp_trigger1_status_reg_u reg_val; - sw_error_t ret = SW_OK; - - ret = qca808x_ptp_trigger1_status_reg_get(dev_id, phy_id, ®_val); - *value = reg_val.bf.error; - return ret; -} - -sw_error_t -qca808x_ptp_trigger1_status_reg_error_set( - a_uint32_t dev_id, a_uint32_t phy_id, - a_uint32_t value) -{ - union ptp_trigger1_status_reg_u reg_val; - sw_error_t ret = SW_OK; - - ret = qca808x_ptp_trigger1_status_reg_get(dev_id, phy_id, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.error = value; - ret = qca808x_ptp_trigger1_status_reg_set(dev_id, phy_id, ®_val); - return ret; -} - -sw_error_t -qca808x_ptp_trigger1_status_reg_active_get( - a_uint32_t dev_id, a_uint32_t phy_id, - a_uint32_t *value) -{ - union ptp_trigger1_status_reg_u reg_val; - sw_error_t ret = SW_OK; - - ret = qca808x_ptp_trigger1_status_reg_get(dev_id, phy_id, ®_val); - *value = reg_val.bf.active; - return ret; -} - -sw_error_t -qca808x_ptp_trigger1_status_reg_active_set( - a_uint32_t dev_id, a_uint32_t phy_id, - a_uint32_t value) -{ - union ptp_trigger1_status_reg_u reg_val; - sw_error_t ret = SW_OK; - - ret = qca808x_ptp_trigger1_status_reg_get(dev_id, phy_id, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.active = value; - ret = qca808x_ptp_trigger1_status_reg_set(dev_id, phy_id, ®_val); - return ret; -} - -sw_error_t -qca808x_ptp_trigger1_status_reg_finished_get( - a_uint32_t dev_id, a_uint32_t phy_id, - a_uint32_t *value) -{ - union ptp_trigger1_status_reg_u reg_val; - sw_error_t ret = SW_OK; - - ret = qca808x_ptp_trigger1_status_reg_get(dev_id, phy_id, ®_val); - *value = reg_val.bf.finished; - return ret; -} - -sw_error_t -qca808x_ptp_trigger1_status_reg_finished_set( - a_uint32_t dev_id, a_uint32_t phy_id, - a_uint32_t value) -{ - union ptp_trigger1_status_reg_u reg_val; - sw_error_t ret = SW_OK; - - ret = qca808x_ptp_trigger1_status_reg_get(dev_id, phy_id, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.finished = value; - ret = qca808x_ptp_trigger1_status_reg_set(dev_id, phy_id, ®_val); - return ret; -} - -sw_error_t -qca808x_ptp_trigger0_timestamp0_reg_ts_sec_get( - a_uint32_t dev_id, a_uint32_t phy_id, - a_uint32_t *value) -{ - union ptp_trigger0_timestamp0_reg_u reg_val; - sw_error_t ret = SW_OK; - - ret = qca808x_ptp_trigger0_timestamp0_reg_get(dev_id, phy_id, ®_val); - *value = reg_val.bf.ts_sec; - return ret; -} - -sw_error_t -qca808x_ptp_trigger0_timestamp0_reg_ts_sec_set( - a_uint32_t dev_id, a_uint32_t phy_id, - a_uint32_t value) -{ - union ptp_trigger0_timestamp0_reg_u reg_val; - sw_error_t ret = SW_OK; - - ret = qca808x_ptp_trigger0_timestamp0_reg_get(dev_id, phy_id, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.ts_sec = value; - ret = qca808x_ptp_trigger0_timestamp0_reg_set(dev_id, phy_id, ®_val); - return ret; -} - -sw_error_t -qca808x_ptp_trigger0_timestamp1_reg_ts_sec_get( - a_uint32_t dev_id, a_uint32_t phy_id, - a_uint32_t *value) -{ - union ptp_trigger0_timestamp1_reg_u reg_val; - sw_error_t ret = SW_OK; - - ret = qca808x_ptp_trigger0_timestamp1_reg_get(dev_id, phy_id, ®_val); - *value = reg_val.bf.ts_sec; - return ret; -} - -sw_error_t -qca808x_ptp_trigger0_timestamp1_reg_ts_sec_set( - a_uint32_t dev_id, a_uint32_t phy_id, - a_uint32_t value) -{ - union ptp_trigger0_timestamp1_reg_u reg_val; - sw_error_t ret = SW_OK; - - ret = qca808x_ptp_trigger0_timestamp1_reg_get(dev_id, phy_id, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.ts_sec = value; - ret = qca808x_ptp_trigger0_timestamp1_reg_set(dev_id, phy_id, ®_val); - return ret; -} - -sw_error_t -qca808x_ptp_trigger0_timestamp2_reg_ts_sec_get( - a_uint32_t dev_id, a_uint32_t phy_id, - a_uint32_t *value) -{ - union ptp_trigger0_timestamp2_reg_u reg_val; - sw_error_t ret = SW_OK; - - ret = qca808x_ptp_trigger0_timestamp2_reg_get(dev_id, phy_id, ®_val); - *value = reg_val.bf.ts_sec; - return ret; -} - -sw_error_t -qca808x_ptp_trigger0_timestamp2_reg_ts_sec_set( - a_uint32_t dev_id, a_uint32_t phy_id, - a_uint32_t value) -{ - union ptp_trigger0_timestamp2_reg_u reg_val; - sw_error_t ret = SW_OK; - - ret = qca808x_ptp_trigger0_timestamp2_reg_get(dev_id, phy_id, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.ts_sec = value; - ret = qca808x_ptp_trigger0_timestamp2_reg_set(dev_id, phy_id, ®_val); - return ret; -} - -sw_error_t -qca808x_ptp_trigger0_timestamp3_reg_ts_nsec_get( - a_uint32_t dev_id, a_uint32_t phy_id, - a_uint32_t *value) -{ - union ptp_trigger0_timestamp3_reg_u reg_val; - sw_error_t ret = SW_OK; - - ret = qca808x_ptp_trigger0_timestamp3_reg_get(dev_id, phy_id, ®_val); - *value = reg_val.bf.ts_nsec; - return ret; -} - -sw_error_t -qca808x_ptp_trigger0_timestamp3_reg_ts_nsec_set( - a_uint32_t dev_id, a_uint32_t phy_id, - a_uint32_t value) -{ - union ptp_trigger0_timestamp3_reg_u reg_val; - sw_error_t ret = SW_OK; - - ret = qca808x_ptp_trigger0_timestamp3_reg_get(dev_id, phy_id, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.ts_nsec = value; - ret = qca808x_ptp_trigger0_timestamp3_reg_set(dev_id, phy_id, ®_val); - return ret; -} - -sw_error_t -qca808x_ptp_trigger0_timestamp4_reg_ts_nsec_get( - a_uint32_t dev_id, a_uint32_t phy_id, - a_uint32_t *value) -{ - union ptp_trigger0_timestamp4_reg_u reg_val; - sw_error_t ret = SW_OK; - - ret = qca808x_ptp_trigger0_timestamp4_reg_get(dev_id, phy_id, ®_val); - *value = reg_val.bf.ts_nsec; - return ret; -} - -sw_error_t -qca808x_ptp_trigger0_timestamp4_reg_ts_nsec_set( - a_uint32_t dev_id, a_uint32_t phy_id, - a_uint32_t value) -{ - union ptp_trigger0_timestamp4_reg_u reg_val; - sw_error_t ret = SW_OK; - - ret = qca808x_ptp_trigger0_timestamp4_reg_get(dev_id, phy_id, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.ts_nsec = value; - ret = qca808x_ptp_trigger0_timestamp4_reg_set(dev_id, phy_id, ®_val); - return ret; -} - -sw_error_t -qca808x_ptp_trigger1_timestamp0_reg_ts_sec_get( - a_uint32_t dev_id, a_uint32_t phy_id, - a_uint32_t *value) -{ - union ptp_trigger1_timestamp0_reg_u reg_val; - sw_error_t ret = SW_OK; - - ret = qca808x_ptp_trigger1_timestamp0_reg_get(dev_id, phy_id, ®_val); - *value = reg_val.bf.ts_sec; - return ret; -} - -sw_error_t -qca808x_ptp_trigger1_timestamp0_reg_ts_sec_set( - a_uint32_t dev_id, a_uint32_t phy_id, - a_uint32_t value) -{ - union ptp_trigger1_timestamp0_reg_u reg_val; - sw_error_t ret = SW_OK; - - ret = qca808x_ptp_trigger1_timestamp0_reg_get(dev_id, phy_id, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.ts_sec = value; - ret = qca808x_ptp_trigger1_timestamp0_reg_set(dev_id, phy_id, ®_val); - return ret; -} - -sw_error_t -qca808x_ptp_trigger1_timestamp1_reg_ts_sec_get( - a_uint32_t dev_id, a_uint32_t phy_id, - a_uint32_t *value) -{ - union ptp_trigger1_timestamp1_reg_u reg_val; - sw_error_t ret = SW_OK; - - ret = qca808x_ptp_trigger1_timestamp1_reg_get(dev_id, phy_id, ®_val); - *value = reg_val.bf.ts_sec; - return ret; -} - -sw_error_t -qca808x_ptp_trigger1_timestamp1_reg_ts_sec_set( - a_uint32_t dev_id, a_uint32_t phy_id, - a_uint32_t value) -{ - union ptp_trigger1_timestamp1_reg_u reg_val; - sw_error_t ret = SW_OK; - - ret = qca808x_ptp_trigger1_timestamp1_reg_get(dev_id, phy_id, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.ts_sec = value; - ret = qca808x_ptp_trigger1_timestamp1_reg_set(dev_id, phy_id, ®_val); - return ret; -} - -sw_error_t -qca808x_ptp_trigger1_timestamp2_reg_ts_sec_get( - a_uint32_t dev_id, a_uint32_t phy_id, - a_uint32_t *value) -{ - union ptp_trigger1_timestamp2_reg_u reg_val; - sw_error_t ret = SW_OK; - - ret = qca808x_ptp_trigger1_timestamp2_reg_get(dev_id, phy_id, ®_val); - *value = reg_val.bf.ts_sec; - return ret; -} - -sw_error_t -qca808x_ptp_trigger1_timestamp2_reg_ts_sec_set( - a_uint32_t dev_id, a_uint32_t phy_id, - a_uint32_t value) -{ - union ptp_trigger1_timestamp2_reg_u reg_val; - sw_error_t ret = SW_OK; - - ret = qca808x_ptp_trigger1_timestamp2_reg_get(dev_id, phy_id, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.ts_sec = value; - ret = qca808x_ptp_trigger1_timestamp2_reg_set(dev_id, phy_id, ®_val); - return ret; -} - -sw_error_t -qca808x_ptp_trigger1_timestamp3_reg_ts_nsec_get( - a_uint32_t dev_id, a_uint32_t phy_id, - a_uint32_t *value) -{ - union ptp_trigger1_timestamp3_reg_u reg_val; - sw_error_t ret = SW_OK; - - ret = qca808x_ptp_trigger1_timestamp3_reg_get(dev_id, phy_id, ®_val); - *value = reg_val.bf.ts_nsec; - return ret; -} - -sw_error_t -qca808x_ptp_trigger1_timestamp3_reg_ts_nsec_set( - a_uint32_t dev_id, a_uint32_t phy_id, - a_uint32_t value) -{ - union ptp_trigger1_timestamp3_reg_u reg_val; - sw_error_t ret = SW_OK; - - ret = qca808x_ptp_trigger1_timestamp3_reg_get(dev_id, phy_id, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.ts_nsec = value; - ret = qca808x_ptp_trigger1_timestamp3_reg_set(dev_id, phy_id, ®_val); - return ret; -} - -sw_error_t -qca808x_ptp_trigger1_timestamp4_reg_ts_nsec_get( - a_uint32_t dev_id, a_uint32_t phy_id, - a_uint32_t *value) -{ - union ptp_trigger1_timestamp4_reg_u reg_val; - sw_error_t ret = SW_OK; - - ret = qca808x_ptp_trigger1_timestamp4_reg_get(dev_id, phy_id, ®_val); - *value = reg_val.bf.ts_nsec; - return ret; -} - -sw_error_t -qca808x_ptp_trigger1_timestamp4_reg_ts_nsec_set( - a_uint32_t dev_id, a_uint32_t phy_id, - a_uint32_t value) -{ - union ptp_trigger1_timestamp4_reg_u reg_val; - sw_error_t ret = SW_OK; - - ret = qca808x_ptp_trigger1_timestamp4_reg_get(dev_id, phy_id, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.ts_nsec = value; - ret = qca808x_ptp_trigger1_timestamp4_reg_set(dev_id, phy_id, ®_val); - return ret; -} - -sw_error_t -qca808x_ptp_event0_config_reg_rise_en_get( - a_uint32_t dev_id, a_uint32_t phy_id, - a_uint32_t *value) -{ - union ptp_event0_config_reg_u reg_val; - sw_error_t ret = SW_OK; - - ret = qca808x_ptp_event0_config_reg_get(dev_id, phy_id, ®_val); - *value = reg_val.bf.rise_en; - return ret; -} - -sw_error_t -qca808x_ptp_event0_config_reg_rise_en_set( - a_uint32_t dev_id, a_uint32_t phy_id, - a_uint32_t value) -{ - union ptp_event0_config_reg_u reg_val; - sw_error_t ret = SW_OK; - - ret = qca808x_ptp_event0_config_reg_get(dev_id, phy_id, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.rise_en = value; - ret = qca808x_ptp_event0_config_reg_set(dev_id, phy_id, ®_val); - return ret; -} - -sw_error_t -qca808x_ptp_event0_config_reg_single_cap_get( - a_uint32_t dev_id, a_uint32_t phy_id, - a_uint32_t *value) -{ - union ptp_event0_config_reg_u reg_val; - sw_error_t ret = SW_OK; - - ret = qca808x_ptp_event0_config_reg_get(dev_id, phy_id, ®_val); - *value = reg_val.bf.single_cap; - return ret; -} - -sw_error_t -qca808x_ptp_event0_config_reg_single_cap_set( - a_uint32_t dev_id, a_uint32_t phy_id, - a_uint32_t value) -{ - union ptp_event0_config_reg_u reg_val; - sw_error_t ret = SW_OK; - - ret = qca808x_ptp_event0_config_reg_get(dev_id, phy_id, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.single_cap = value; - ret = qca808x_ptp_event0_config_reg_set(dev_id, phy_id, ®_val); - return ret; -} - -sw_error_t -qca808x_ptp_event0_config_reg_fall_en_get( - a_uint32_t dev_id, a_uint32_t phy_id, - a_uint32_t *value) -{ - union ptp_event0_config_reg_u reg_val; - sw_error_t ret = SW_OK; - - ret = qca808x_ptp_event0_config_reg_get(dev_id, phy_id, ®_val); - *value = reg_val.bf.fall_en; - return ret; -} - -sw_error_t -qca808x_ptp_event0_config_reg_fall_en_set( - a_uint32_t dev_id, a_uint32_t phy_id, - a_uint32_t value) -{ - union ptp_event0_config_reg_u reg_val; - sw_error_t ret = SW_OK; - - ret = qca808x_ptp_event0_config_reg_get(dev_id, phy_id, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.fall_en = value; - ret = qca808x_ptp_event0_config_reg_set(dev_id, phy_id, ®_val); - return ret; -} - -sw_error_t -qca808x_ptp_event0_config_reg_notify_get( - a_uint32_t dev_id, a_uint32_t phy_id, - a_uint32_t *value) -{ - union ptp_event0_config_reg_u reg_val; - sw_error_t ret = SW_OK; - - ret = qca808x_ptp_event0_config_reg_get(dev_id, phy_id, ®_val); - *value = reg_val.bf.notify; - return ret; -} - -sw_error_t -qca808x_ptp_event0_config_reg_notify_set( - a_uint32_t dev_id, a_uint32_t phy_id, - a_uint32_t value) -{ - union ptp_event0_config_reg_u reg_val; - sw_error_t ret = SW_OK; - - ret = qca808x_ptp_event0_config_reg_get(dev_id, phy_id, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.notify = value; - ret = qca808x_ptp_event0_config_reg_set(dev_id, phy_id, ®_val); - return ret; -} - -sw_error_t -qca808x_ptp_event0_config_reg_clear_stat_get( - a_uint32_t dev_id, a_uint32_t phy_id, - a_uint32_t *value) -{ - union ptp_event0_config_reg_u reg_val; - sw_error_t ret = SW_OK; - - ret = qca808x_ptp_event0_config_reg_get(dev_id, phy_id, ®_val); - *value = reg_val.bf.clear_stat; - return ret; -} - -sw_error_t -qca808x_ptp_event0_config_reg_clear_stat_set( - a_uint32_t dev_id, a_uint32_t phy_id, - a_uint32_t value) -{ - union ptp_event0_config_reg_u reg_val; - sw_error_t ret = SW_OK; - - ret = qca808x_ptp_event0_config_reg_get(dev_id, phy_id, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.clear_stat = value; - ret = qca808x_ptp_event0_config_reg_set(dev_id, phy_id, ®_val); - return ret; -} - -sw_error_t -qca808x_ptp_event0_status_reg_mul_event_get( - a_uint32_t dev_id, a_uint32_t phy_id, - a_uint32_t *value) -{ - union ptp_event0_status_reg_u reg_val; - sw_error_t ret = SW_OK; - - ret = qca808x_ptp_event0_status_reg_get(dev_id, phy_id, ®_val); - *value = reg_val.bf.mul_event; - return ret; -} - -sw_error_t -qca808x_ptp_event0_status_reg_mul_event_set( - a_uint32_t dev_id, a_uint32_t phy_id, - a_uint32_t value) -{ - union ptp_event0_status_reg_u reg_val; - sw_error_t ret = SW_OK; - - ret = qca808x_ptp_event0_status_reg_get(dev_id, phy_id, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.mul_event = value; - ret = qca808x_ptp_event0_status_reg_set(dev_id, phy_id, ®_val); - return ret; -} - -sw_error_t -qca808x_ptp_event0_status_reg_missed_count_get( - a_uint32_t dev_id, a_uint32_t phy_id, - a_uint32_t *value) -{ - union ptp_event0_status_reg_u reg_val; - sw_error_t ret = SW_OK; - - ret = qca808x_ptp_event0_status_reg_get(dev_id, phy_id, ®_val); - *value = reg_val.bf.missed_count; - return ret; -} - -sw_error_t -qca808x_ptp_event0_status_reg_missed_count_set( - a_uint32_t dev_id, a_uint32_t phy_id, - a_uint32_t value) -{ - union ptp_event0_status_reg_u reg_val; - sw_error_t ret = SW_OK; - - ret = qca808x_ptp_event0_status_reg_get(dev_id, phy_id, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.missed_count = value; - ret = qca808x_ptp_event0_status_reg_set(dev_id, phy_id, ®_val); - return ret; -} - -sw_error_t -qca808x_ptp_event0_status_reg_dir_detected_get( - a_uint32_t dev_id, a_uint32_t phy_id, - a_uint32_t *value) -{ - union ptp_event0_status_reg_u reg_val; - sw_error_t ret = SW_OK; - - ret = qca808x_ptp_event0_status_reg_get(dev_id, phy_id, ®_val); - *value = reg_val.bf.dir_detected; - return ret; -} - -sw_error_t -qca808x_ptp_event0_status_reg_dir_detected_set( - a_uint32_t dev_id, a_uint32_t phy_id, - a_uint32_t value) -{ - union ptp_event0_status_reg_u reg_val; - sw_error_t ret = SW_OK; - - ret = qca808x_ptp_event0_status_reg_get(dev_id, phy_id, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.dir_detected = value; - ret = qca808x_ptp_event0_status_reg_set(dev_id, phy_id, ®_val); - return ret; -} - -sw_error_t -qca808x_ptp_event0_status_reg_detected_get( - a_uint32_t dev_id, a_uint32_t phy_id, - a_uint32_t *value) -{ - union ptp_event0_status_reg_u reg_val; - sw_error_t ret = SW_OK; - - ret = qca808x_ptp_event0_status_reg_get(dev_id, phy_id, ®_val); - *value = reg_val.bf.detected; - return ret; -} - -sw_error_t -qca808x_ptp_event0_status_reg_detected_set( - a_uint32_t dev_id, a_uint32_t phy_id, - a_uint32_t value) -{ - union ptp_event0_status_reg_u reg_val; - sw_error_t ret = SW_OK; - - ret = qca808x_ptp_event0_status_reg_get(dev_id, phy_id, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.detected = value; - ret = qca808x_ptp_event0_status_reg_set(dev_id, phy_id, ®_val); - return ret; -} - -sw_error_t -qca808x_ptp_event1_config_reg_rise_en_get( - a_uint32_t dev_id, a_uint32_t phy_id, - a_uint32_t *value) -{ - union ptp_event1_config_reg_u reg_val; - sw_error_t ret = SW_OK; - - ret = qca808x_ptp_event1_config_reg_get(dev_id, phy_id, ®_val); - *value = reg_val.bf.rise_en; - return ret; -} - -sw_error_t -qca808x_ptp_event1_config_reg_rise_en_set( - a_uint32_t dev_id, a_uint32_t phy_id, - a_uint32_t value) -{ - union ptp_event1_config_reg_u reg_val; - sw_error_t ret = SW_OK; - - ret = qca808x_ptp_event1_config_reg_get(dev_id, phy_id, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.rise_en = value; - ret = qca808x_ptp_event1_config_reg_set(dev_id, phy_id, ®_val); - return ret; -} - -sw_error_t -qca808x_ptp_event1_config_reg_single_cap_get( - a_uint32_t dev_id, a_uint32_t phy_id, - a_uint32_t *value) -{ - union ptp_event1_config_reg_u reg_val; - sw_error_t ret = SW_OK; - - ret = qca808x_ptp_event1_config_reg_get(dev_id, phy_id, ®_val); - *value = reg_val.bf.single_cap; - return ret; -} - -sw_error_t -qca808x_ptp_event1_config_reg_single_cap_set( - a_uint32_t dev_id, a_uint32_t phy_id, - a_uint32_t value) -{ - union ptp_event1_config_reg_u reg_val; - sw_error_t ret = SW_OK; - - ret = qca808x_ptp_event1_config_reg_get(dev_id, phy_id, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.single_cap = value; - ret = qca808x_ptp_event1_config_reg_set(dev_id, phy_id, ®_val); - return ret; -} - -sw_error_t -qca808x_ptp_event1_config_reg_fall_en_get( - a_uint32_t dev_id, a_uint32_t phy_id, - a_uint32_t *value) -{ - union ptp_event1_config_reg_u reg_val; - sw_error_t ret = SW_OK; - - ret = qca808x_ptp_event1_config_reg_get(dev_id, phy_id, ®_val); - *value = reg_val.bf.fall_en; - return ret; -} - -sw_error_t -qca808x_ptp_event1_config_reg_fall_en_set( - a_uint32_t dev_id, a_uint32_t phy_id, - a_uint32_t value) -{ - union ptp_event1_config_reg_u reg_val; - sw_error_t ret = SW_OK; - - ret = qca808x_ptp_event1_config_reg_get(dev_id, phy_id, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.fall_en = value; - ret = qca808x_ptp_event1_config_reg_set(dev_id, phy_id, ®_val); - return ret; -} - -sw_error_t -qca808x_ptp_event1_config_reg_notify_get( - a_uint32_t dev_id, a_uint32_t phy_id, - a_uint32_t *value) -{ - union ptp_event1_config_reg_u reg_val; - sw_error_t ret = SW_OK; - - ret = qca808x_ptp_event1_config_reg_get(dev_id, phy_id, ®_val); - *value = reg_val.bf.notify; - return ret; -} - -sw_error_t -qca808x_ptp_event1_config_reg_notify_set( - a_uint32_t dev_id, a_uint32_t phy_id, - a_uint32_t value) -{ - union ptp_event1_config_reg_u reg_val; - sw_error_t ret = SW_OK; - - ret = qca808x_ptp_event1_config_reg_get(dev_id, phy_id, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.notify = value; - ret = qca808x_ptp_event1_config_reg_set(dev_id, phy_id, ®_val); - return ret; -} - -sw_error_t -qca808x_ptp_event1_config_reg_clear_stat_get( - a_uint32_t dev_id, a_uint32_t phy_id, - a_uint32_t *value) -{ - union ptp_event1_config_reg_u reg_val; - sw_error_t ret = SW_OK; - - ret = qca808x_ptp_event1_config_reg_get(dev_id, phy_id, ®_val); - *value = reg_val.bf.clear_stat; - return ret; -} - -sw_error_t -qca808x_ptp_event1_config_reg_clear_stat_set( - a_uint32_t dev_id, a_uint32_t phy_id, - a_uint32_t value) -{ - union ptp_event1_config_reg_u reg_val; - sw_error_t ret = SW_OK; - - ret = qca808x_ptp_event1_config_reg_get(dev_id, phy_id, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.clear_stat = value; - ret = qca808x_ptp_event1_config_reg_set(dev_id, phy_id, ®_val); - return ret; -} - -sw_error_t -qca808x_ptp_event1_status_reg_mul_event_get( - a_uint32_t dev_id, a_uint32_t phy_id, - a_uint32_t *value) -{ - union ptp_event1_status_reg_u reg_val; - sw_error_t ret = SW_OK; - - ret = qca808x_ptp_event1_status_reg_get(dev_id, phy_id, ®_val); - *value = reg_val.bf.mul_event; - return ret; -} - -sw_error_t -qca808x_ptp_event1_status_reg_mul_event_set( - a_uint32_t dev_id, a_uint32_t phy_id, - a_uint32_t value) -{ - union ptp_event1_status_reg_u reg_val; - sw_error_t ret = SW_OK; - - ret = qca808x_ptp_event1_status_reg_get(dev_id, phy_id, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.mul_event = value; - ret = qca808x_ptp_event1_status_reg_set(dev_id, phy_id, ®_val); - return ret; -} - -sw_error_t -qca808x_ptp_event1_status_reg_missed_count_get( - a_uint32_t dev_id, a_uint32_t phy_id, - a_uint32_t *value) -{ - union ptp_event1_status_reg_u reg_val; - sw_error_t ret = SW_OK; - - ret = qca808x_ptp_event1_status_reg_get(dev_id, phy_id, ®_val); - *value = reg_val.bf.missed_count; - return ret; -} - -sw_error_t -qca808x_ptp_event1_status_reg_missed_count_set( - a_uint32_t dev_id, a_uint32_t phy_id, - a_uint32_t value) -{ - union ptp_event1_status_reg_u reg_val; - sw_error_t ret = SW_OK; - - ret = qca808x_ptp_event1_status_reg_get(dev_id, phy_id, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.missed_count = value; - ret = qca808x_ptp_event1_status_reg_set(dev_id, phy_id, ®_val); - return ret; -} - -sw_error_t -qca808x_ptp_event1_status_reg_dir_detected_get( - a_uint32_t dev_id, a_uint32_t phy_id, - a_uint32_t *value) -{ - union ptp_event1_status_reg_u reg_val; - sw_error_t ret = SW_OK; - - ret = qca808x_ptp_event1_status_reg_get(dev_id, phy_id, ®_val); - *value = reg_val.bf.dir_detected; - return ret; -} - -sw_error_t -qca808x_ptp_event1_status_reg_dir_detected_set( - a_uint32_t dev_id, a_uint32_t phy_id, - a_uint32_t value) -{ - union ptp_event1_status_reg_u reg_val; - sw_error_t ret = SW_OK; - - ret = qca808x_ptp_event1_status_reg_get(dev_id, phy_id, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.dir_detected = value; - ret = qca808x_ptp_event1_status_reg_set(dev_id, phy_id, ®_val); - return ret; -} - -sw_error_t -qca808x_ptp_event1_status_reg_detected_get( - a_uint32_t dev_id, a_uint32_t phy_id, - a_uint32_t *value) -{ - union ptp_event1_status_reg_u reg_val; - sw_error_t ret = SW_OK; - - ret = qca808x_ptp_event1_status_reg_get(dev_id, phy_id, ®_val); - *value = reg_val.bf.detected; - return ret; -} - -sw_error_t -qca808x_ptp_event1_status_reg_detected_set( - a_uint32_t dev_id, a_uint32_t phy_id, - a_uint32_t value) -{ - union ptp_event1_status_reg_u reg_val; - sw_error_t ret = SW_OK; - - ret = qca808x_ptp_event1_status_reg_get(dev_id, phy_id, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.detected = value; - ret = qca808x_ptp_event1_status_reg_set(dev_id, phy_id, ®_val); - return ret; -} - -sw_error_t -qca808x_ptp_event0_timestamp0_reg_ts_nsec_get( - a_uint32_t dev_id, a_uint32_t phy_id, - a_uint32_t *value) -{ - union ptp_event0_timestamp0_reg_u reg_val; - sw_error_t ret = SW_OK; - - ret = qca808x_ptp_event0_timestamp0_reg_get(dev_id, phy_id, ®_val); - *value = reg_val.bf.ts_nsec; - return ret; -} - -sw_error_t -qca808x_ptp_event0_timestamp0_reg_ts_nsec_set( - a_uint32_t dev_id, a_uint32_t phy_id, - a_uint32_t value) -{ - union ptp_event0_timestamp0_reg_u reg_val; - sw_error_t ret = SW_OK; - - ret = qca808x_ptp_event0_timestamp0_reg_get(dev_id, phy_id, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.ts_nsec = value; - ret = qca808x_ptp_event0_timestamp0_reg_set(dev_id, phy_id, ®_val); - return ret; -} - -sw_error_t -qca808x_ptp_event0_timestamp1_reg_ts_nsec_get( - a_uint32_t dev_id, a_uint32_t phy_id, - a_uint32_t *value) -{ - union ptp_event0_timestamp1_reg_u reg_val; - sw_error_t ret = SW_OK; - - ret = qca808x_ptp_event0_timestamp1_reg_get(dev_id, phy_id, ®_val); - *value = reg_val.bf.ts_nsec; - return ret; -} - -sw_error_t -qca808x_ptp_event0_timestamp1_reg_ts_nsec_set( - a_uint32_t dev_id, a_uint32_t phy_id, - a_uint32_t value) -{ - union ptp_event0_timestamp1_reg_u reg_val; - sw_error_t ret = SW_OK; - - ret = qca808x_ptp_event0_timestamp1_reg_get(dev_id, phy_id, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.ts_nsec = value; - ret = qca808x_ptp_event0_timestamp1_reg_set(dev_id, phy_id, ®_val); - return ret; -} - -sw_error_t -qca808x_ptp_event0_timestamp2_reg_ts_nsec_get( - a_uint32_t dev_id, a_uint32_t phy_id, - a_uint32_t *value) -{ - union ptp_event0_timestamp2_reg_u reg_val; - sw_error_t ret = SW_OK; - - ret = qca808x_ptp_event0_timestamp2_reg_get(dev_id, phy_id, ®_val); - *value = reg_val.bf.ts_nsec; - return ret; -} - -sw_error_t -qca808x_ptp_event0_timestamp2_reg_ts_nsec_set( - a_uint32_t dev_id, a_uint32_t phy_id, - a_uint32_t value) -{ - union ptp_event0_timestamp2_reg_u reg_val; - sw_error_t ret = SW_OK; - - ret = qca808x_ptp_event0_timestamp2_reg_get(dev_id, phy_id, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.ts_nsec = value; - ret = qca808x_ptp_event0_timestamp2_reg_set(dev_id, phy_id, ®_val); - return ret; -} - -sw_error_t -qca808x_ptp_event0_timestamp3_reg_ts_nsec_get( - a_uint32_t dev_id, a_uint32_t phy_id, - a_uint32_t *value) -{ - union ptp_event0_timestamp3_reg_u reg_val; - sw_error_t ret = SW_OK; - - ret = qca808x_ptp_event0_timestamp3_reg_get(dev_id, phy_id, ®_val); - *value = reg_val.bf.ts_nsec; - return ret; -} - -sw_error_t -qca808x_ptp_event0_timestamp3_reg_ts_nsec_set( - a_uint32_t dev_id, a_uint32_t phy_id, - a_uint32_t value) -{ - union ptp_event0_timestamp3_reg_u reg_val; - sw_error_t ret = SW_OK; - - ret = qca808x_ptp_event0_timestamp3_reg_get(dev_id, phy_id, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.ts_nsec = value; - ret = qca808x_ptp_event0_timestamp3_reg_set(dev_id, phy_id, ®_val); - return ret; -} - -sw_error_t -qca808x_ptp_event0_timestamp4_reg_ts_nsec_get( - a_uint32_t dev_id, a_uint32_t phy_id, - a_uint32_t *value) -{ - union ptp_event0_timestamp4_reg_u reg_val; - sw_error_t ret = SW_OK; - - ret = qca808x_ptp_event0_timestamp4_reg_get(dev_id, phy_id, ®_val); - *value = reg_val.bf.ts_nsec; - return ret; -} - -sw_error_t -qca808x_ptp_event0_timestamp4_reg_ts_nsec_set( - a_uint32_t dev_id, a_uint32_t phy_id, - a_uint32_t value) -{ - union ptp_event0_timestamp4_reg_u reg_val; - sw_error_t ret = SW_OK; - - ret = qca808x_ptp_event0_timestamp4_reg_get(dev_id, phy_id, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.ts_nsec = value; - ret = qca808x_ptp_event0_timestamp4_reg_set(dev_id, phy_id, ®_val); - return ret; -} - -sw_error_t -qca808x_ptp_event1_timestamp0_reg_ts_nsec_get( - a_uint32_t dev_id, a_uint32_t phy_id, - a_uint32_t *value) -{ - union ptp_event1_timestamp0_reg_u reg_val; - sw_error_t ret = SW_OK; - - ret = qca808x_ptp_event1_timestamp0_reg_get(dev_id, phy_id, ®_val); - *value = reg_val.bf.ts_nsec; - return ret; -} - -sw_error_t -qca808x_ptp_event1_timestamp0_reg_ts_nsec_set( - a_uint32_t dev_id, a_uint32_t phy_id, - a_uint32_t value) -{ - union ptp_event1_timestamp0_reg_u reg_val; - sw_error_t ret = SW_OK; - - ret = qca808x_ptp_event1_timestamp0_reg_get(dev_id, phy_id, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.ts_nsec = value; - ret = qca808x_ptp_event1_timestamp0_reg_set(dev_id, phy_id, ®_val); - return ret; -} - -sw_error_t -qca808x_ptp_event1_timestamp1_reg_ts_nsec_get( - a_uint32_t dev_id, a_uint32_t phy_id, - a_uint32_t *value) -{ - union ptp_event1_timestamp1_reg_u reg_val; - sw_error_t ret = SW_OK; - - ret = qca808x_ptp_event1_timestamp1_reg_get(dev_id, phy_id, ®_val); - *value = reg_val.bf.ts_nsec; - return ret; -} - -sw_error_t -qca808x_ptp_event1_timestamp1_reg_ts_nsec_set( - a_uint32_t dev_id, a_uint32_t phy_id, - a_uint32_t value) -{ - union ptp_event1_timestamp1_reg_u reg_val; - sw_error_t ret = SW_OK; - - ret = qca808x_ptp_event1_timestamp1_reg_get(dev_id, phy_id, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.ts_nsec = value; - ret = qca808x_ptp_event1_timestamp1_reg_set(dev_id, phy_id, ®_val); - return ret; -} - -sw_error_t -qca808x_ptp_event1_timestamp2_reg_ts_nsec_get( - a_uint32_t dev_id, a_uint32_t phy_id, - a_uint32_t *value) -{ - union ptp_event1_timestamp2_reg_u reg_val; - sw_error_t ret = SW_OK; - - ret = qca808x_ptp_event1_timestamp2_reg_get(dev_id, phy_id, ®_val); - *value = reg_val.bf.ts_nsec; - return ret; -} - -sw_error_t -qca808x_ptp_event1_timestamp2_reg_ts_nsec_set( - a_uint32_t dev_id, a_uint32_t phy_id, - a_uint32_t value) -{ - union ptp_event1_timestamp2_reg_u reg_val; - sw_error_t ret = SW_OK; - - ret = qca808x_ptp_event1_timestamp2_reg_get(dev_id, phy_id, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.ts_nsec = value; - ret = qca808x_ptp_event1_timestamp2_reg_set(dev_id, phy_id, ®_val); - return ret; -} - -sw_error_t -qca808x_ptp_event1_timestamp3_reg_ts_nsec_get( - a_uint32_t dev_id, a_uint32_t phy_id, - a_uint32_t *value) -{ - union ptp_event1_timestamp3_reg_u reg_val; - sw_error_t ret = SW_OK; - - ret = qca808x_ptp_event1_timestamp3_reg_get(dev_id, phy_id, ®_val); - *value = reg_val.bf.ts_nsec; - return ret; -} - -sw_error_t -qca808x_ptp_event1_timestamp3_reg_ts_nsec_set( - a_uint32_t dev_id, a_uint32_t phy_id, - a_uint32_t value) -{ - union ptp_event1_timestamp3_reg_u reg_val; - sw_error_t ret = SW_OK; - - ret = qca808x_ptp_event1_timestamp3_reg_get(dev_id, phy_id, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.ts_nsec = value; - ret = qca808x_ptp_event1_timestamp3_reg_set(dev_id, phy_id, ®_val); - return ret; -} - -sw_error_t -qca808x_ptp_event1_timestamp4_reg_ts_nsec_get( - a_uint32_t dev_id, a_uint32_t phy_id, - a_uint32_t *value) -{ - union ptp_event1_timestamp4_reg_u reg_val; - sw_error_t ret = SW_OK; - - ret = qca808x_ptp_event1_timestamp4_reg_get(dev_id, phy_id, ®_val); - *value = reg_val.bf.ts_nsec; - return ret; -} - -sw_error_t -qca808x_ptp_event1_timestamp4_reg_ts_nsec_set( - a_uint32_t dev_id, a_uint32_t phy_id, - a_uint32_t value) -{ - union ptp_event1_timestamp4_reg_u reg_val; - sw_error_t ret = SW_OK; - - ret = qca808x_ptp_event1_timestamp4_reg_get(dev_id, phy_id, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.ts_nsec = value; - ret = qca808x_ptp_event1_timestamp4_reg_set(dev_id, phy_id, ®_val); - return ret; -} - -sw_error_t -qca808x_ptp_rx_seqid1_reg_rx_seqid_get( - a_uint32_t dev_id, a_uint32_t phy_id, - a_uint32_t *value) -{ - union ptp_rx_seqid1_reg_u reg_val; - sw_error_t ret = SW_OK; - - ret = qca808x_ptp_rx_seqid1_reg_get(dev_id, phy_id, ®_val); - *value = reg_val.bf.rx_seqid; - return ret; -} - -sw_error_t -qca808x_ptp_rx_seqid1_reg_rx_seqid_set( - a_uint32_t dev_id, a_uint32_t phy_id, - a_uint32_t value) -{ - union ptp_rx_seqid1_reg_u reg_val; - sw_error_t ret = SW_OK; - - ret = qca808x_ptp_rx_seqid1_reg_get(dev_id, phy_id, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.rx_seqid = value; - ret = qca808x_ptp_rx_seqid1_reg_set(dev_id, phy_id, ®_val); - return ret; -} - -sw_error_t -qca808x_ptp_rx_portid1_0_reg_rx_portid_get( - a_uint32_t dev_id, a_uint32_t phy_id, - a_uint32_t *value) -{ - union ptp_rx_portid1_0_reg_u reg_val; - sw_error_t ret = SW_OK; - - ret = qca808x_ptp_rx_portid1_0_reg_get(dev_id, phy_id, ®_val); - *value = reg_val.bf.rx_portid; - return ret; -} - -sw_error_t -qca808x_ptp_rx_portid1_0_reg_rx_portid_set( - a_uint32_t dev_id, a_uint32_t phy_id, - a_uint32_t value) -{ - union ptp_rx_portid1_0_reg_u reg_val; - sw_error_t ret = SW_OK; - - ret = qca808x_ptp_rx_portid1_0_reg_get(dev_id, phy_id, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.rx_portid = value; - ret = qca808x_ptp_rx_portid1_0_reg_set(dev_id, phy_id, ®_val); - return ret; -} - -sw_error_t -qca808x_ptp_rx_portid1_1_reg_rx_portid_get( - a_uint32_t dev_id, a_uint32_t phy_id, - a_uint32_t *value) -{ - union ptp_rx_portid1_1_reg_u reg_val; - sw_error_t ret = SW_OK; - - ret = qca808x_ptp_rx_portid1_1_reg_get(dev_id, phy_id, ®_val); - *value = reg_val.bf.rx_portid; - return ret; -} - -sw_error_t -qca808x_ptp_rx_portid1_1_reg_rx_portid_set( - a_uint32_t dev_id, a_uint32_t phy_id, - a_uint32_t value) -{ - union ptp_rx_portid1_1_reg_u reg_val; - sw_error_t ret = SW_OK; - - ret = qca808x_ptp_rx_portid1_1_reg_get(dev_id, phy_id, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.rx_portid = value; - ret = qca808x_ptp_rx_portid1_1_reg_set(dev_id, phy_id, ®_val); - return ret; -} - -sw_error_t -qca808x_ptp_rx_portid1_2_reg_rx_portid_get( - a_uint32_t dev_id, a_uint32_t phy_id, - a_uint32_t *value) -{ - union ptp_rx_portid1_2_reg_u reg_val; - sw_error_t ret = SW_OK; - - ret = qca808x_ptp_rx_portid1_2_reg_get(dev_id, phy_id, ®_val); - *value = reg_val.bf.rx_portid; - return ret; -} - -sw_error_t -qca808x_ptp_rx_portid1_2_reg_rx_portid_set( - a_uint32_t dev_id, a_uint32_t phy_id, - a_uint32_t value) -{ - union ptp_rx_portid1_2_reg_u reg_val; - sw_error_t ret = SW_OK; - - ret = qca808x_ptp_rx_portid1_2_reg_get(dev_id, phy_id, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.rx_portid = value; - ret = qca808x_ptp_rx_portid1_2_reg_set(dev_id, phy_id, ®_val); - return ret; -} - -sw_error_t -qca808x_ptp_rx_portid1_3_reg_rx_portid_get( - a_uint32_t dev_id, a_uint32_t phy_id, - a_uint32_t *value) -{ - union ptp_rx_portid1_3_reg_u reg_val; - sw_error_t ret = SW_OK; - - ret = qca808x_ptp_rx_portid1_3_reg_get(dev_id, phy_id, ®_val); - *value = reg_val.bf.rx_portid; - return ret; -} - -sw_error_t -qca808x_ptp_rx_portid1_3_reg_rx_portid_set( - a_uint32_t dev_id, a_uint32_t phy_id, - a_uint32_t value) -{ - union ptp_rx_portid1_3_reg_u reg_val; - sw_error_t ret = SW_OK; - - ret = qca808x_ptp_rx_portid1_3_reg_get(dev_id, phy_id, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.rx_portid = value; - ret = qca808x_ptp_rx_portid1_3_reg_set(dev_id, phy_id, ®_val); - return ret; -} - -sw_error_t -qca808x_ptp_rx_portid1_4_reg_rx_portid_get( - a_uint32_t dev_id, a_uint32_t phy_id, - a_uint32_t *value) -{ - union ptp_rx_portid1_4_reg_u reg_val; - sw_error_t ret = SW_OK; - - ret = qca808x_ptp_rx_portid1_4_reg_get(dev_id, phy_id, ®_val); - *value = reg_val.bf.rx_portid; - return ret; -} - -sw_error_t -qca808x_ptp_rx_portid1_4_reg_rx_portid_set( - a_uint32_t dev_id, a_uint32_t phy_id, - a_uint32_t value) -{ - union ptp_rx_portid1_4_reg_u reg_val; - sw_error_t ret = SW_OK; - - ret = qca808x_ptp_rx_portid1_4_reg_get(dev_id, phy_id, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.rx_portid = value; - ret = qca808x_ptp_rx_portid1_4_reg_set(dev_id, phy_id, ®_val); - return ret; -} - -sw_error_t -qca808x_ptp_rx_ts1_0_reg_rx_ts_sec_get( - a_uint32_t dev_id, a_uint32_t phy_id, - a_uint32_t *value) -{ - union ptp_rx_ts1_0_reg_u reg_val; - sw_error_t ret = SW_OK; - - ret = qca808x_ptp_rx_ts1_0_reg_get(dev_id, phy_id, ®_val); - *value = reg_val.bf.rx_ts_sec; - return ret; -} - -sw_error_t -qca808x_ptp_rx_ts1_0_reg_rx_ts_sec_set( - a_uint32_t dev_id, a_uint32_t phy_id, - a_uint32_t value) -{ - union ptp_rx_ts1_0_reg_u reg_val; - sw_error_t ret = SW_OK; - - ret = qca808x_ptp_rx_ts1_0_reg_get(dev_id, phy_id, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.rx_ts_sec = value; - ret = qca808x_ptp_rx_ts1_0_reg_set(dev_id, phy_id, ®_val); - return ret; -} - -sw_error_t -qca808x_ptp_rx_ts1_1_reg_rx_ts_sec_get( - a_uint32_t dev_id, a_uint32_t phy_id, - a_uint32_t *value) -{ - union ptp_rx_ts1_1_reg_u reg_val; - sw_error_t ret = SW_OK; - - ret = qca808x_ptp_rx_ts1_1_reg_get(dev_id, phy_id, ®_val); - *value = reg_val.bf.rx_ts_sec; - return ret; -} - -sw_error_t -qca808x_ptp_rx_ts1_1_reg_rx_ts_sec_set( - a_uint32_t dev_id, a_uint32_t phy_id, - a_uint32_t value) -{ - union ptp_rx_ts1_1_reg_u reg_val; - sw_error_t ret = SW_OK; - - ret = qca808x_ptp_rx_ts1_1_reg_get(dev_id, phy_id, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.rx_ts_sec = value; - ret = qca808x_ptp_rx_ts1_1_reg_set(dev_id, phy_id, ®_val); - return ret; -} - -sw_error_t -qca808x_ptp_rx_ts1_2_reg_rx_ts_sec_get( - a_uint32_t dev_id, a_uint32_t phy_id, - a_uint32_t *value) -{ - union ptp_rx_ts1_2_reg_u reg_val; - sw_error_t ret = SW_OK; - - ret = qca808x_ptp_rx_ts1_2_reg_get(dev_id, phy_id, ®_val); - *value = reg_val.bf.rx_ts_sec; - return ret; -} - -sw_error_t -qca808x_ptp_rx_ts1_2_reg_rx_ts_sec_set( - a_uint32_t dev_id, a_uint32_t phy_id, - a_uint32_t value) -{ - union ptp_rx_ts1_2_reg_u reg_val; - sw_error_t ret = SW_OK; - - ret = qca808x_ptp_rx_ts1_2_reg_get(dev_id, phy_id, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.rx_ts_sec = value; - ret = qca808x_ptp_rx_ts1_2_reg_set(dev_id, phy_id, ®_val); - return ret; -} - -sw_error_t -qca808x_ptp_rx_ts1_3_reg_rx_ts_nsec_get( - a_uint32_t dev_id, a_uint32_t phy_id, - a_uint32_t *value) -{ - union ptp_rx_ts1_3_reg_u reg_val; - sw_error_t ret = SW_OK; - - ret = qca808x_ptp_rx_ts1_3_reg_get(dev_id, phy_id, ®_val); - *value = reg_val.bf.rx_ts_nsec; - return ret; -} - -sw_error_t -qca808x_ptp_rx_ts1_3_reg_rx_ts_nsec_set( - a_uint32_t dev_id, a_uint32_t phy_id, - a_uint32_t value) -{ - union ptp_rx_ts1_3_reg_u reg_val; - sw_error_t ret = SW_OK; - - ret = qca808x_ptp_rx_ts1_3_reg_get(dev_id, phy_id, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.rx_ts_nsec = value; - ret = qca808x_ptp_rx_ts1_3_reg_set(dev_id, phy_id, ®_val); - return ret; -} - -sw_error_t -qca808x_ptp_rx_ts1_4_reg_rx_ts_nsec_get( - a_uint32_t dev_id, a_uint32_t phy_id, - a_uint32_t *value) -{ - union ptp_rx_ts1_4_reg_u reg_val; - sw_error_t ret = SW_OK; - - ret = qca808x_ptp_rx_ts1_4_reg_get(dev_id, phy_id, ®_val); - *value = reg_val.bf.rx_ts_nsec; - return ret; -} - -sw_error_t -qca808x_ptp_rx_ts1_4_reg_rx_ts_nsec_set( - a_uint32_t dev_id, a_uint32_t phy_id, - a_uint32_t value) -{ - union ptp_rx_ts1_4_reg_u reg_val; - sw_error_t ret = SW_OK; - - ret = qca808x_ptp_rx_ts1_4_reg_get(dev_id, phy_id, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.rx_ts_nsec = value; - ret = qca808x_ptp_rx_ts1_4_reg_set(dev_id, phy_id, ®_val); - return ret; -} - -sw_error_t -qca808x_ptp_rx_ts1_5_reg_rx_ts_nfsec_get( - a_uint32_t dev_id, a_uint32_t phy_id, - a_uint32_t *value) -{ - union ptp_rx_ts1_5_reg_u reg_val; - sw_error_t ret = SW_OK; - - ret = qca808x_ptp_rx_ts1_5_reg_get(dev_id, phy_id, ®_val); - *value = reg_val.bf.rx_ts_nfsec; - return ret; -} - -sw_error_t -qca808x_ptp_rx_ts1_5_reg_rx_ts_nfsec_set( - a_uint32_t dev_id, a_uint32_t phy_id, - a_uint32_t value) -{ - union ptp_rx_ts1_5_reg_u reg_val; - sw_error_t ret = SW_OK; - - ret = qca808x_ptp_rx_ts1_5_reg_get(dev_id, phy_id, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.rx_ts_nfsec = value; - ret = qca808x_ptp_rx_ts1_5_reg_set(dev_id, phy_id, ®_val); - return ret; -} - -sw_error_t -qca808x_ptp_rx_ts1_5_reg_rx_msg_type_get( - a_uint32_t dev_id, a_uint32_t phy_id, - a_uint32_t *value) -{ - union ptp_rx_ts1_5_reg_u reg_val; - sw_error_t ret = SW_OK; - - ret = qca808x_ptp_rx_ts1_5_reg_get(dev_id, phy_id, ®_val); - *value = reg_val.bf.rx_msg_type; - return ret; -} - -sw_error_t -qca808x_ptp_rx_ts1_5_reg_rx_msg_type_set( - a_uint32_t dev_id, a_uint32_t phy_id, - a_uint32_t value) -{ - union ptp_rx_ts1_5_reg_u reg_val; - sw_error_t ret = SW_OK; - - ret = qca808x_ptp_rx_ts1_5_reg_get(dev_id, phy_id, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.rx_msg_type = value; - ret = qca808x_ptp_rx_ts1_5_reg_set(dev_id, phy_id, ®_val); - return ret; -} - -sw_error_t -qca808x_ptp_rx_ts1_6_reg_rx_ts_nfsec_get( - a_uint32_t dev_id, a_uint32_t phy_id, - a_uint32_t *value) -{ - union ptp_rx_ts1_6_reg_u reg_val; - sw_error_t ret = SW_OK; - - ret = qca808x_ptp_rx_ts1_6_reg_get(dev_id, phy_id, ®_val); - *value = reg_val.bf.rx_ts_nfsec; - return ret; -} - -sw_error_t -qca808x_ptp_rx_ts1_6_reg_rx_ts_nfsec_set( - a_uint32_t dev_id, a_uint32_t phy_id, - a_uint32_t value) -{ - union ptp_rx_ts1_6_reg_u reg_val; - sw_error_t ret = SW_OK; - - ret = qca808x_ptp_rx_ts1_6_reg_get(dev_id, phy_id, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.rx_ts_nfsec = value; - ret = qca808x_ptp_rx_ts1_6_reg_set(dev_id, phy_id, ®_val); - return ret; -} - -sw_error_t -qca808x_ptp_rx_seqid2_reg_rx_seqid_get( - a_uint32_t dev_id, a_uint32_t phy_id, - a_uint32_t *value) -{ - union ptp_rx_seqid2_reg_u reg_val; - sw_error_t ret = SW_OK; - - ret = qca808x_ptp_rx_seqid2_reg_get(dev_id, phy_id, ®_val); - *value = reg_val.bf.rx_seqid; - return ret; -} - -sw_error_t -qca808x_ptp_rx_seqid2_reg_rx_seqid_set( - a_uint32_t dev_id, a_uint32_t phy_id, - a_uint32_t value) -{ - union ptp_rx_seqid2_reg_u reg_val; - sw_error_t ret = SW_OK; - - ret = qca808x_ptp_rx_seqid2_reg_get(dev_id, phy_id, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.rx_seqid = value; - ret = qca808x_ptp_rx_seqid2_reg_set(dev_id, phy_id, ®_val); - return ret; -} - -sw_error_t -qca808x_ptp_rx_portid2_0_reg_rx_portid_get( - a_uint32_t dev_id, a_uint32_t phy_id, - a_uint32_t *value) -{ - union ptp_rx_portid2_0_reg_u reg_val; - sw_error_t ret = SW_OK; - - ret = qca808x_ptp_rx_portid2_0_reg_get(dev_id, phy_id, ®_val); - *value = reg_val.bf.rx_portid; - return ret; -} - -sw_error_t -qca808x_ptp_rx_portid2_0_reg_rx_portid_set( - a_uint32_t dev_id, a_uint32_t phy_id, - a_uint32_t value) -{ - union ptp_rx_portid2_0_reg_u reg_val; - sw_error_t ret = SW_OK; - - ret = qca808x_ptp_rx_portid2_0_reg_get(dev_id, phy_id, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.rx_portid = value; - ret = qca808x_ptp_rx_portid2_0_reg_set(dev_id, phy_id, ®_val); - return ret; -} - -sw_error_t -qca808x_ptp_rx_portid2_1_reg_rx_portid_get( - a_uint32_t dev_id, a_uint32_t phy_id, - a_uint32_t *value) -{ - union ptp_rx_portid2_1_reg_u reg_val; - sw_error_t ret = SW_OK; - - ret = qca808x_ptp_rx_portid2_1_reg_get(dev_id, phy_id, ®_val); - *value = reg_val.bf.rx_portid; - return ret; -} - -sw_error_t -qca808x_ptp_rx_portid2_1_reg_rx_portid_set( - a_uint32_t dev_id, a_uint32_t phy_id, - a_uint32_t value) -{ - union ptp_rx_portid2_1_reg_u reg_val; - sw_error_t ret = SW_OK; - - ret = qca808x_ptp_rx_portid2_1_reg_get(dev_id, phy_id, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.rx_portid = value; - ret = qca808x_ptp_rx_portid2_1_reg_set(dev_id, phy_id, ®_val); - return ret; -} - -sw_error_t -qca808x_ptp_rx_portid2_2_reg_rx_portid_get( - a_uint32_t dev_id, a_uint32_t phy_id, - a_uint32_t *value) -{ - union ptp_rx_portid2_2_reg_u reg_val; - sw_error_t ret = SW_OK; - - ret = qca808x_ptp_rx_portid2_2_reg_get(dev_id, phy_id, ®_val); - *value = reg_val.bf.rx_portid; - return ret; -} - -sw_error_t -qca808x_ptp_rx_portid2_2_reg_rx_portid_set( - a_uint32_t dev_id, a_uint32_t phy_id, - a_uint32_t value) -{ - union ptp_rx_portid2_2_reg_u reg_val; - sw_error_t ret = SW_OK; - - ret = qca808x_ptp_rx_portid2_2_reg_get(dev_id, phy_id, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.rx_portid = value; - ret = qca808x_ptp_rx_portid2_2_reg_set(dev_id, phy_id, ®_val); - return ret; -} - -sw_error_t -qca808x_ptp_rx_portid2_3_reg_rx_portid_get( - a_uint32_t dev_id, a_uint32_t phy_id, - a_uint32_t *value) -{ - union ptp_rx_portid2_3_reg_u reg_val; - sw_error_t ret = SW_OK; - - ret = qca808x_ptp_rx_portid2_3_reg_get(dev_id, phy_id, ®_val); - *value = reg_val.bf.rx_portid; - return ret; -} - -sw_error_t -qca808x_ptp_rx_portid2_3_reg_rx_portid_set( - a_uint32_t dev_id, a_uint32_t phy_id, - a_uint32_t value) -{ - union ptp_rx_portid2_3_reg_u reg_val; - sw_error_t ret = SW_OK; - - ret = qca808x_ptp_rx_portid2_3_reg_get(dev_id, phy_id, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.rx_portid = value; - ret = qca808x_ptp_rx_portid2_3_reg_set(dev_id, phy_id, ®_val); - return ret; -} - -sw_error_t -qca808x_ptp_rx_portid2_4_reg_rx_portid_get( - a_uint32_t dev_id, a_uint32_t phy_id, - a_uint32_t *value) -{ - union ptp_rx_portid2_4_reg_u reg_val; - sw_error_t ret = SW_OK; - - ret = qca808x_ptp_rx_portid2_4_reg_get(dev_id, phy_id, ®_val); - *value = reg_val.bf.rx_portid; - return ret; -} - -sw_error_t -qca808x_ptp_rx_portid2_4_reg_rx_portid_set( - a_uint32_t dev_id, a_uint32_t phy_id, - a_uint32_t value) -{ - union ptp_rx_portid2_4_reg_u reg_val; - sw_error_t ret = SW_OK; - - ret = qca808x_ptp_rx_portid2_4_reg_get(dev_id, phy_id, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.rx_portid = value; - ret = qca808x_ptp_rx_portid2_4_reg_set(dev_id, phy_id, ®_val); - return ret; -} - -sw_error_t -qca808x_ptp_rx_ts2_0_reg_rx_ts_sec_get( - a_uint32_t dev_id, a_uint32_t phy_id, - a_uint32_t *value) -{ - union ptp_rx_ts2_0_reg_u reg_val; - sw_error_t ret = SW_OK; - - ret = qca808x_ptp_rx_ts2_0_reg_get(dev_id, phy_id, ®_val); - *value = reg_val.bf.rx_ts_sec; - return ret; -} - -sw_error_t -qca808x_ptp_rx_ts2_0_reg_rx_ts_sec_set( - a_uint32_t dev_id, a_uint32_t phy_id, - a_uint32_t value) -{ - union ptp_rx_ts2_0_reg_u reg_val; - sw_error_t ret = SW_OK; - - ret = qca808x_ptp_rx_ts2_0_reg_get(dev_id, phy_id, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.rx_ts_sec = value; - ret = qca808x_ptp_rx_ts2_0_reg_set(dev_id, phy_id, ®_val); - return ret; -} - -sw_error_t -qca808x_ptp_rx_ts2_1_reg_rx_ts_sec_get( - a_uint32_t dev_id, a_uint32_t phy_id, - a_uint32_t *value) -{ - union ptp_rx_ts2_1_reg_u reg_val; - sw_error_t ret = SW_OK; - - ret = qca808x_ptp_rx_ts2_1_reg_get(dev_id, phy_id, ®_val); - *value = reg_val.bf.rx_ts_sec; - return ret; -} - -sw_error_t -qca808x_ptp_rx_ts2_1_reg_rx_ts_sec_set( - a_uint32_t dev_id, a_uint32_t phy_id, - a_uint32_t value) -{ - union ptp_rx_ts2_1_reg_u reg_val; - sw_error_t ret = SW_OK; - - ret = qca808x_ptp_rx_ts2_1_reg_get(dev_id, phy_id, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.rx_ts_sec = value; - ret = qca808x_ptp_rx_ts2_1_reg_set(dev_id, phy_id, ®_val); - return ret; -} - -sw_error_t -qca808x_ptp_rx_ts2_2_reg_rx_ts_sec_get( - a_uint32_t dev_id, a_uint32_t phy_id, - a_uint32_t *value) -{ - union ptp_rx_ts2_2_reg_u reg_val; - sw_error_t ret = SW_OK; - - ret = qca808x_ptp_rx_ts2_2_reg_get(dev_id, phy_id, ®_val); - *value = reg_val.bf.rx_ts_sec; - return ret; -} - -sw_error_t -qca808x_ptp_rx_ts2_2_reg_rx_ts_sec_set( - a_uint32_t dev_id, a_uint32_t phy_id, - a_uint32_t value) -{ - union ptp_rx_ts2_2_reg_u reg_val; - sw_error_t ret = SW_OK; - - ret = qca808x_ptp_rx_ts2_2_reg_get(dev_id, phy_id, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.rx_ts_sec = value; - ret = qca808x_ptp_rx_ts2_2_reg_set(dev_id, phy_id, ®_val); - return ret; -} - -sw_error_t -qca808x_ptp_rx_ts2_3_reg_rx_ts_nsec_get( - a_uint32_t dev_id, a_uint32_t phy_id, - a_uint32_t *value) -{ - union ptp_rx_ts2_3_reg_u reg_val; - sw_error_t ret = SW_OK; - - ret = qca808x_ptp_rx_ts2_3_reg_get(dev_id, phy_id, ®_val); - *value = reg_val.bf.rx_ts_nsec; - return ret; -} - -sw_error_t -qca808x_ptp_rx_ts2_3_reg_rx_ts_nsec_set( - a_uint32_t dev_id, a_uint32_t phy_id, - a_uint32_t value) -{ - union ptp_rx_ts2_3_reg_u reg_val; - sw_error_t ret = SW_OK; - - ret = qca808x_ptp_rx_ts2_3_reg_get(dev_id, phy_id, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.rx_ts_nsec = value; - ret = qca808x_ptp_rx_ts2_3_reg_set(dev_id, phy_id, ®_val); - return ret; -} - -sw_error_t -qca808x_ptp_rx_ts2_4_reg_rx_ts_nsec_get( - a_uint32_t dev_id, a_uint32_t phy_id, - a_uint32_t *value) -{ - union ptp_rx_ts2_4_reg_u reg_val; - sw_error_t ret = SW_OK; - - ret = qca808x_ptp_rx_ts2_4_reg_get(dev_id, phy_id, ®_val); - *value = reg_val.bf.rx_ts_nsec; - return ret; -} - -sw_error_t -qca808x_ptp_rx_ts2_4_reg_rx_ts_nsec_set( - a_uint32_t dev_id, a_uint32_t phy_id, - a_uint32_t value) -{ - union ptp_rx_ts2_4_reg_u reg_val; - sw_error_t ret = SW_OK; - - ret = qca808x_ptp_rx_ts2_4_reg_get(dev_id, phy_id, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.rx_ts_nsec = value; - ret = qca808x_ptp_rx_ts2_4_reg_set(dev_id, phy_id, ®_val); - return ret; -} - -sw_error_t -qca808x_ptp_rx_ts2_5_reg_rx_ts_nfsec_get( - a_uint32_t dev_id, a_uint32_t phy_id, - a_uint32_t *value) -{ - union ptp_rx_ts2_5_reg_u reg_val; - sw_error_t ret = SW_OK; - - ret = qca808x_ptp_rx_ts2_5_reg_get(dev_id, phy_id, ®_val); - *value = reg_val.bf.rx_ts_nfsec; - return ret; -} - -sw_error_t -qca808x_ptp_rx_ts2_5_reg_rx_ts_nfsec_set( - a_uint32_t dev_id, a_uint32_t phy_id, - a_uint32_t value) -{ - union ptp_rx_ts2_5_reg_u reg_val; - sw_error_t ret = SW_OK; - - ret = qca808x_ptp_rx_ts2_5_reg_get(dev_id, phy_id, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.rx_ts_nfsec = value; - ret = qca808x_ptp_rx_ts2_5_reg_set(dev_id, phy_id, ®_val); - return ret; -} - -sw_error_t -qca808x_ptp_rx_ts2_5_reg_rx_msg_type_get( - a_uint32_t dev_id, a_uint32_t phy_id, - a_uint32_t *value) -{ - union ptp_rx_ts2_5_reg_u reg_val; - sw_error_t ret = SW_OK; - - ret = qca808x_ptp_rx_ts2_5_reg_get(dev_id, phy_id, ®_val); - *value = reg_val.bf.rx_msg_type; - return ret; -} - -sw_error_t -qca808x_ptp_rx_ts2_5_reg_rx_msg_type_set( - a_uint32_t dev_id, a_uint32_t phy_id, - a_uint32_t value) -{ - union ptp_rx_ts2_5_reg_u reg_val; - sw_error_t ret = SW_OK; - - ret = qca808x_ptp_rx_ts2_5_reg_get(dev_id, phy_id, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.rx_msg_type = value; - ret = qca808x_ptp_rx_ts2_5_reg_set(dev_id, phy_id, ®_val); - return ret; -} - -sw_error_t -qca808x_ptp_rx_ts2_6_reg_rx_ts_nfsec_get( - a_uint32_t dev_id, a_uint32_t phy_id, - a_uint32_t *value) -{ - union ptp_rx_ts2_6_reg_u reg_val; - sw_error_t ret = SW_OK; - - ret = qca808x_ptp_rx_ts2_6_reg_get(dev_id, phy_id, ®_val); - *value = reg_val.bf.rx_ts_nfsec; - return ret; -} - -sw_error_t -qca808x_ptp_rx_ts2_6_reg_rx_ts_nfsec_set( - a_uint32_t dev_id, a_uint32_t phy_id, - a_uint32_t value) -{ - union ptp_rx_ts2_6_reg_u reg_val; - sw_error_t ret = SW_OK; - - ret = qca808x_ptp_rx_ts2_6_reg_get(dev_id, phy_id, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.rx_ts_nfsec = value; - ret = qca808x_ptp_rx_ts2_6_reg_set(dev_id, phy_id, ®_val); - return ret; -} - -sw_error_t -qca808x_ptp_rx_seqid3_reg_rx_seqid_get( - a_uint32_t dev_id, a_uint32_t phy_id, - a_uint32_t *value) -{ - union ptp_rx_seqid3_reg_u reg_val; - sw_error_t ret = SW_OK; - - ret = qca808x_ptp_rx_seqid3_reg_get(dev_id, phy_id, ®_val); - *value = reg_val.bf.rx_seqid; - return ret; -} - -sw_error_t -qca808x_ptp_rx_seqid3_reg_rx_seqid_set( - a_uint32_t dev_id, a_uint32_t phy_id, - a_uint32_t value) -{ - union ptp_rx_seqid3_reg_u reg_val; - sw_error_t ret = SW_OK; - - ret = qca808x_ptp_rx_seqid3_reg_get(dev_id, phy_id, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.rx_seqid = value; - ret = qca808x_ptp_rx_seqid3_reg_set(dev_id, phy_id, ®_val); - return ret; -} - -sw_error_t -qca808x_ptp_rx_portid3_0_reg_rx_portid_get( - a_uint32_t dev_id, a_uint32_t phy_id, - a_uint32_t *value) -{ - union ptp_rx_portid3_0_reg_u reg_val; - sw_error_t ret = SW_OK; - - ret = qca808x_ptp_rx_portid3_0_reg_get(dev_id, phy_id, ®_val); - *value = reg_val.bf.rx_portid; - return ret; -} - -sw_error_t -qca808x_ptp_rx_portid3_0_reg_rx_portid_set( - a_uint32_t dev_id, a_uint32_t phy_id, - a_uint32_t value) -{ - union ptp_rx_portid3_0_reg_u reg_val; - sw_error_t ret = SW_OK; - - ret = qca808x_ptp_rx_portid3_0_reg_get(dev_id, phy_id, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.rx_portid = value; - ret = qca808x_ptp_rx_portid3_0_reg_set(dev_id, phy_id, ®_val); - return ret; -} - -sw_error_t -qca808x_ptp_rx_portid3_1_reg_rx_portid_get( - a_uint32_t dev_id, a_uint32_t phy_id, - a_uint32_t *value) -{ - union ptp_rx_portid3_1_reg_u reg_val; - sw_error_t ret = SW_OK; - - ret = qca808x_ptp_rx_portid3_1_reg_get(dev_id, phy_id, ®_val); - *value = reg_val.bf.rx_portid; - return ret; -} - -sw_error_t -qca808x_ptp_rx_portid3_1_reg_rx_portid_set( - a_uint32_t dev_id, a_uint32_t phy_id, - a_uint32_t value) -{ - union ptp_rx_portid3_1_reg_u reg_val; - sw_error_t ret = SW_OK; - - ret = qca808x_ptp_rx_portid3_1_reg_get(dev_id, phy_id, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.rx_portid = value; - ret = qca808x_ptp_rx_portid3_1_reg_set(dev_id, phy_id, ®_val); - return ret; -} - -sw_error_t -qca808x_ptp_rx_portid3_2_reg_rx_portid_get( - a_uint32_t dev_id, a_uint32_t phy_id, - a_uint32_t *value) -{ - union ptp_rx_portid3_2_reg_u reg_val; - sw_error_t ret = SW_OK; - - ret = qca808x_ptp_rx_portid3_2_reg_get(dev_id, phy_id, ®_val); - *value = reg_val.bf.rx_portid; - return ret; -} - -sw_error_t -qca808x_ptp_rx_portid3_2_reg_rx_portid_set( - a_uint32_t dev_id, a_uint32_t phy_id, - a_uint32_t value) -{ - union ptp_rx_portid3_2_reg_u reg_val; - sw_error_t ret = SW_OK; - - ret = qca808x_ptp_rx_portid3_2_reg_get(dev_id, phy_id, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.rx_portid = value; - ret = qca808x_ptp_rx_portid3_2_reg_set(dev_id, phy_id, ®_val); - return ret; -} - -sw_error_t -qca808x_ptp_rx_portid3_3_reg_rx_portid_get( - a_uint32_t dev_id, a_uint32_t phy_id, - a_uint32_t *value) -{ - union ptp_rx_portid3_3_reg_u reg_val; - sw_error_t ret = SW_OK; - - ret = qca808x_ptp_rx_portid3_3_reg_get(dev_id, phy_id, ®_val); - *value = reg_val.bf.rx_portid; - return ret; -} - -sw_error_t -qca808x_ptp_rx_portid3_3_reg_rx_portid_set( - a_uint32_t dev_id, a_uint32_t phy_id, - a_uint32_t value) -{ - union ptp_rx_portid3_3_reg_u reg_val; - sw_error_t ret = SW_OK; - - ret = qca808x_ptp_rx_portid3_3_reg_get(dev_id, phy_id, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.rx_portid = value; - ret = qca808x_ptp_rx_portid3_3_reg_set(dev_id, phy_id, ®_val); - return ret; -} - -sw_error_t -qca808x_ptp_rx_portid3_4_reg_rx_portid_get( - a_uint32_t dev_id, a_uint32_t phy_id, - a_uint32_t *value) -{ - union ptp_rx_portid3_4_reg_u reg_val; - sw_error_t ret = SW_OK; - - ret = qca808x_ptp_rx_portid3_4_reg_get(dev_id, phy_id, ®_val); - *value = reg_val.bf.rx_portid; - return ret; -} - -sw_error_t -qca808x_ptp_rx_portid3_4_reg_rx_portid_set( - a_uint32_t dev_id, a_uint32_t phy_id, - a_uint32_t value) -{ - union ptp_rx_portid3_4_reg_u reg_val; - sw_error_t ret = SW_OK; - - ret = qca808x_ptp_rx_portid3_4_reg_get(dev_id, phy_id, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.rx_portid = value; - ret = qca808x_ptp_rx_portid3_4_reg_set(dev_id, phy_id, ®_val); - return ret; -} - -sw_error_t -qca808x_ptp_rx_ts3_0_reg_rx_ts_sec_get( - a_uint32_t dev_id, a_uint32_t phy_id, - a_uint32_t *value) -{ - union ptp_rx_ts3_0_reg_u reg_val; - sw_error_t ret = SW_OK; - - ret = qca808x_ptp_rx_ts3_0_reg_get(dev_id, phy_id, ®_val); - *value = reg_val.bf.rx_ts_sec; - return ret; -} - -sw_error_t -qca808x_ptp_rx_ts3_0_reg_rx_ts_sec_set( - a_uint32_t dev_id, a_uint32_t phy_id, - a_uint32_t value) -{ - union ptp_rx_ts3_0_reg_u reg_val; - sw_error_t ret = SW_OK; - - ret = qca808x_ptp_rx_ts3_0_reg_get(dev_id, phy_id, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.rx_ts_sec = value; - ret = qca808x_ptp_rx_ts3_0_reg_set(dev_id, phy_id, ®_val); - return ret; -} - -sw_error_t -qca808x_ptp_rx_ts3_1_reg_rx_ts_sec_get( - a_uint32_t dev_id, a_uint32_t phy_id, - a_uint32_t *value) -{ - union ptp_rx_ts3_1_reg_u reg_val; - sw_error_t ret = SW_OK; - - ret = qca808x_ptp_rx_ts3_1_reg_get(dev_id, phy_id, ®_val); - *value = reg_val.bf.rx_ts_sec; - return ret; -} - -sw_error_t -qca808x_ptp_rx_ts3_1_reg_rx_ts_sec_set( - a_uint32_t dev_id, a_uint32_t phy_id, - a_uint32_t value) -{ - union ptp_rx_ts3_1_reg_u reg_val; - sw_error_t ret = SW_OK; - - ret = qca808x_ptp_rx_ts3_1_reg_get(dev_id, phy_id, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.rx_ts_sec = value; - ret = qca808x_ptp_rx_ts3_1_reg_set(dev_id, phy_id, ®_val); - return ret; -} - -sw_error_t -qca808x_ptp_rx_ts3_2_reg_rx_ts_sec_get( - a_uint32_t dev_id, a_uint32_t phy_id, - a_uint32_t *value) -{ - union ptp_rx_ts3_2_reg_u reg_val; - sw_error_t ret = SW_OK; - - ret = qca808x_ptp_rx_ts3_2_reg_get(dev_id, phy_id, ®_val); - *value = reg_val.bf.rx_ts_sec; - return ret; -} - -sw_error_t -qca808x_ptp_rx_ts3_2_reg_rx_ts_sec_set( - a_uint32_t dev_id, a_uint32_t phy_id, - a_uint32_t value) -{ - union ptp_rx_ts3_2_reg_u reg_val; - sw_error_t ret = SW_OK; - - ret = qca808x_ptp_rx_ts3_2_reg_get(dev_id, phy_id, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.rx_ts_sec = value; - ret = qca808x_ptp_rx_ts3_2_reg_set(dev_id, phy_id, ®_val); - return ret; -} - -sw_error_t -qca808x_ptp_rx_ts3_3_reg_rx_ts_nsec_get( - a_uint32_t dev_id, a_uint32_t phy_id, - a_uint32_t *value) -{ - union ptp_rx_ts3_3_reg_u reg_val; - sw_error_t ret = SW_OK; - - ret = qca808x_ptp_rx_ts3_3_reg_get(dev_id, phy_id, ®_val); - *value = reg_val.bf.rx_ts_nsec; - return ret; -} - -sw_error_t -qca808x_ptp_rx_ts3_3_reg_rx_ts_nsec_set( - a_uint32_t dev_id, a_uint32_t phy_id, - a_uint32_t value) -{ - union ptp_rx_ts3_3_reg_u reg_val; - sw_error_t ret = SW_OK; - - ret = qca808x_ptp_rx_ts3_3_reg_get(dev_id, phy_id, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.rx_ts_nsec = value; - ret = qca808x_ptp_rx_ts3_3_reg_set(dev_id, phy_id, ®_val); - return ret; -} - -sw_error_t -qca808x_ptp_rx_ts3_4_reg_rx_ts_nsec_get( - a_uint32_t dev_id, a_uint32_t phy_id, - a_uint32_t *value) -{ - union ptp_rx_ts3_4_reg_u reg_val; - sw_error_t ret = SW_OK; - - ret = qca808x_ptp_rx_ts3_4_reg_get(dev_id, phy_id, ®_val); - *value = reg_val.bf.rx_ts_nsec; - return ret; -} - -sw_error_t -qca808x_ptp_rx_ts3_4_reg_rx_ts_nsec_set( - a_uint32_t dev_id, a_uint32_t phy_id, - a_uint32_t value) -{ - union ptp_rx_ts3_4_reg_u reg_val; - sw_error_t ret = SW_OK; - - ret = qca808x_ptp_rx_ts3_4_reg_get(dev_id, phy_id, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.rx_ts_nsec = value; - ret = qca808x_ptp_rx_ts3_4_reg_set(dev_id, phy_id, ®_val); - return ret; -} - -sw_error_t -qca808x_ptp_rx_ts3_5_reg_rx_ts_nfsec_get( - a_uint32_t dev_id, a_uint32_t phy_id, - a_uint32_t *value) -{ - union ptp_rx_ts3_5_reg_u reg_val; - sw_error_t ret = SW_OK; - - ret = qca808x_ptp_rx_ts3_5_reg_get(dev_id, phy_id, ®_val); - *value = reg_val.bf.rx_ts_nfsec; - return ret; -} - -sw_error_t -qca808x_ptp_rx_ts3_5_reg_rx_ts_nfsec_set( - a_uint32_t dev_id, a_uint32_t phy_id, - a_uint32_t value) -{ - union ptp_rx_ts3_5_reg_u reg_val; - sw_error_t ret = SW_OK; - - ret = qca808x_ptp_rx_ts3_5_reg_get(dev_id, phy_id, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.rx_ts_nfsec = value; - ret = qca808x_ptp_rx_ts3_5_reg_set(dev_id, phy_id, ®_val); - return ret; -} - -sw_error_t -qca808x_ptp_rx_ts3_5_reg_rx_msg_type_get( - a_uint32_t dev_id, a_uint32_t phy_id, - a_uint32_t *value) -{ - union ptp_rx_ts3_5_reg_u reg_val; - sw_error_t ret = SW_OK; - - ret = qca808x_ptp_rx_ts3_5_reg_get(dev_id, phy_id, ®_val); - *value = reg_val.bf.rx_msg_type; - return ret; -} - -sw_error_t -qca808x_ptp_rx_ts3_5_reg_rx_msg_type_set( - a_uint32_t dev_id, a_uint32_t phy_id, - a_uint32_t value) -{ - union ptp_rx_ts3_5_reg_u reg_val; - sw_error_t ret = SW_OK; - - ret = qca808x_ptp_rx_ts3_5_reg_get(dev_id, phy_id, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.rx_msg_type = value; - ret = qca808x_ptp_rx_ts3_5_reg_set(dev_id, phy_id, ®_val); - return ret; -} - -sw_error_t -qca808x_ptp_rx_ts3_6_reg_rx_ts_nfsec_get( - a_uint32_t dev_id, a_uint32_t phy_id, - a_uint32_t *value) -{ - union ptp_rx_ts3_6_reg_u reg_val; - sw_error_t ret = SW_OK; - - ret = qca808x_ptp_rx_ts3_6_reg_get(dev_id, phy_id, ®_val); - *value = reg_val.bf.rx_ts_nfsec; - return ret; -} - -sw_error_t -qca808x_ptp_rx_ts3_6_reg_rx_ts_nfsec_set( - a_uint32_t dev_id, a_uint32_t phy_id, - a_uint32_t value) -{ - union ptp_rx_ts3_6_reg_u reg_val; - sw_error_t ret = SW_OK; - - ret = qca808x_ptp_rx_ts3_6_reg_get(dev_id, phy_id, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.rx_ts_nfsec = value; - ret = qca808x_ptp_rx_ts3_6_reg_set(dev_id, phy_id, ®_val); - return ret; -} - -sw_error_t -qca808x_ptp_phase_adjust_0_reg_get( - a_uint32_t dev_id, a_uint32_t phy_id, - union ptp_phase_adjust_0_reg_u *value) -{ - return qca808x_phy_ptp_mmd_read( - dev_id, - phy_id, QCA808X_PHY_MMD3_NUM, PTP_PHASE_ADJUST_0_REG_ADDRESS, - &value->val); -} - -sw_error_t -qca808x_ptp_phase_adjust_0_reg_set( - a_uint32_t dev_id, a_uint32_t phy_id, - union ptp_phase_adjust_0_reg_u *value) -{ - return qca808x_phy_ptp_mmd_write( - dev_id, - phy_id, QCA808X_PHY_MMD3_NUM, PTP_PHASE_ADJUST_0_REG_ADDRESS, - value->val); -} - -sw_error_t -qca808x_ptp_phase_adjust_0_reg_phase_value_get( - a_uint32_t dev_id, a_uint32_t phy_id, - a_uint32_t *value) -{ - union ptp_phase_adjust_0_reg_u reg_val; - sw_error_t ret = SW_OK; - - ret = qca808x_ptp_phase_adjust_0_reg_get(dev_id, phy_id, ®_val); - *value = reg_val.bf.phase_value; - return ret; -} - -sw_error_t -qca808x_ptp_phase_adjust_0_reg_phase_value_set( - a_uint32_t dev_id, a_uint32_t phy_id, - a_uint32_t value) -{ - union ptp_phase_adjust_0_reg_u reg_val; - sw_error_t ret = SW_OK; - - ret = qca808x_ptp_phase_adjust_0_reg_get(dev_id, phy_id, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.phase_value = value; - ret = qca808x_ptp_phase_adjust_0_reg_set(dev_id, phy_id, ®_val); - return ret; -} - -sw_error_t -qca808x_ptp_phase_adjust_1_reg_get( - a_uint32_t dev_id, a_uint32_t phy_id, - union ptp_phase_adjust_1_reg_u *value) -{ - return qca808x_phy_ptp_mmd_read( - dev_id, - phy_id, QCA808X_PHY_MMD3_NUM, PTP_PHASE_ADJUST_1_REG_ADDRESS, - &value->val); -} - -sw_error_t -qca808x_ptp_phase_adjust_1_reg_set( - a_uint32_t dev_id, a_uint32_t phy_id, - union ptp_phase_adjust_1_reg_u *value) -{ - return qca808x_phy_ptp_mmd_write( - dev_id, - phy_id, QCA808X_PHY_MMD3_NUM, PTP_PHASE_ADJUST_1_REG_ADDRESS, - value->val); -} - -sw_error_t -qca808x_ptp_phase_adjust_1_reg_phase_value_get( - a_uint32_t dev_id, a_uint32_t phy_id, - a_uint32_t *value) -{ - union ptp_phase_adjust_1_reg_u reg_val; - sw_error_t ret = SW_OK; - - ret = qca808x_ptp_phase_adjust_1_reg_get(dev_id, phy_id, ®_val); - *value = reg_val.bf.phase_value; - return ret; -} - -sw_error_t -qca808x_ptp_phase_adjust_1_reg_phase_value_set( - a_uint32_t dev_id, a_uint32_t phy_id, - a_uint32_t value) -{ - union ptp_phase_adjust_1_reg_u reg_val; - sw_error_t ret = SW_OK; - - ret = qca808x_ptp_phase_adjust_1_reg_get(dev_id, phy_id, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.phase_value = value; - ret = qca808x_ptp_phase_adjust_1_reg_set(dev_id, phy_id, ®_val); - return ret; -} - -sw_error_t -qca808x_ptp_pps_pul_width_0_reg_get( - a_uint32_t dev_id, a_uint32_t phy_id, - union ptp_pps_pul_width_0_reg_u *value) -{ - return qca808x_phy_ptp_mmd_read( - dev_id, - phy_id, QCA808X_PHY_MMD3_NUM, PTP_PPS_PUL_WIDTH_0_REG_ADDRESS, - &value->val); -} - -sw_error_t -qca808x_ptp_pps_pul_width_0_reg_set( - a_uint32_t dev_id, a_uint32_t phy_id, - union ptp_pps_pul_width_0_reg_u *value) -{ - return qca808x_phy_ptp_mmd_write( - dev_id, - phy_id, QCA808X_PHY_MMD3_NUM, PTP_PPS_PUL_WIDTH_0_REG_ADDRESS, - value->val); -} - -sw_error_t -qca808x_ptp_pps_pul_width_0_reg_pul_value_get( - a_uint32_t dev_id, a_uint32_t phy_id, - a_uint32_t *value) -{ - union ptp_pps_pul_width_0_reg_u reg_val; - sw_error_t ret = SW_OK; - - ret = qca808x_ptp_pps_pul_width_0_reg_get(dev_id, phy_id, ®_val); - *value = reg_val.bf.pul_value; - return ret; -} - -sw_error_t -qca808x_ptp_pps_pul_width_0_reg_pul_value_set( - a_uint32_t dev_id, a_uint32_t phy_id, - a_uint32_t value) -{ - union ptp_pps_pul_width_0_reg_u reg_val; - sw_error_t ret = SW_OK; - - ret = qca808x_ptp_pps_pul_width_0_reg_get(dev_id, phy_id, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.pul_value = value; - ret = qca808x_ptp_pps_pul_width_0_reg_set(dev_id, phy_id, ®_val); - return ret; -} - -sw_error_t -qca808x_ptp_pps_pul_width_1_reg_get( - a_uint32_t dev_id, a_uint32_t phy_id, - union ptp_pps_pul_width_1_reg_u *value) -{ - return qca808x_phy_ptp_mmd_read( - dev_id, - phy_id, QCA808X_PHY_MMD3_NUM, PTP_PPS_PUL_WIDTH_1_REG_ADDRESS, - &value->val); -} - -sw_error_t -qca808x_ptp_pps_pul_width_1_reg_set( - a_uint32_t dev_id, a_uint32_t phy_id, - union ptp_pps_pul_width_1_reg_u *value) -{ - return qca808x_phy_ptp_mmd_write( - dev_id, - phy_id, QCA808X_PHY_MMD3_NUM, PTP_PPS_PUL_WIDTH_1_REG_ADDRESS, - value->val); -} - -sw_error_t -qca808x_ptp_pps_pul_width_1_reg_pul_value_get( - a_uint32_t dev_id, a_uint32_t phy_id, - a_uint32_t *value) -{ - union ptp_pps_pul_width_1_reg_u reg_val; - sw_error_t ret = SW_OK; - - ret = qca808x_ptp_pps_pul_width_1_reg_get(dev_id, phy_id, ®_val); - *value = reg_val.bf.pul_value; - return ret; -} - -sw_error_t -qca808x_ptp_pps_pul_width_1_reg_pul_value_set( - a_uint32_t dev_id, a_uint32_t phy_id, - a_uint32_t value) -{ - union ptp_pps_pul_width_1_reg_u reg_val; - sw_error_t ret = SW_OK; - - ret = qca808x_ptp_pps_pul_width_1_reg_get(dev_id, phy_id, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.pul_value = value; - ret = qca808x_ptp_pps_pul_width_1_reg_set(dev_id, phy_id, ®_val); - return ret; -} - - -sw_error_t -qca808x_ptp_freq_waveform_period_0_reg_get( - a_uint32_t dev_id, a_uint32_t phy_id, - union ptp_freq_waveform_period_0_reg_u *value) -{ - return qca808x_phy_ptp_mmd_read( - dev_id, - phy_id, QCA808X_PHY_MMD3_NUM, PTP_FREQ_WAVEFORM_PERIOD_0_REG_ADDRESS, - &value->val); -} - -sw_error_t -qca808x_ptp_freq_waveform_period_0_reg_set( - a_uint32_t dev_id, a_uint32_t phy_id, - union ptp_freq_waveform_period_0_reg_u *value) -{ - return qca808x_phy_ptp_mmd_write( - dev_id, - phy_id, QCA808X_PHY_MMD3_NUM, PTP_FREQ_WAVEFORM_PERIOD_0_REG_ADDRESS, - value->val); -} - -sw_error_t -qca808x_ptp_freq_waveform_period_0_reg_wave_period_get( - a_uint32_t dev_id, a_uint32_t phy_id, - a_uint32_t *value) -{ - union ptp_freq_waveform_period_0_reg_u reg_val; - sw_error_t ret = SW_OK; - - ret = qca808x_ptp_freq_waveform_period_0_reg_get(dev_id, phy_id, ®_val); - *value = reg_val.bf.wave_period; - return ret; -} - -sw_error_t -qca808x_ptp_freq_waveform_period_0_reg_wave_period_set( - a_uint32_t dev_id, a_uint32_t phy_id, - a_uint32_t value) -{ - union ptp_freq_waveform_period_0_reg_u reg_val; - sw_error_t ret = SW_OK; - - ret = qca808x_ptp_freq_waveform_period_0_reg_get(dev_id, phy_id, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.wave_period = value; - ret = qca808x_ptp_freq_waveform_period_0_reg_set(dev_id, phy_id, ®_val); - return ret; -} - -sw_error_t -qca808x_ptp_freq_waveform_period_0_reg_phase_ali_get( - a_uint32_t dev_id, a_uint32_t phy_id, - a_uint32_t *value) -{ - union ptp_freq_waveform_period_0_reg_u reg_val; - sw_error_t ret = SW_OK; - - ret = qca808x_ptp_freq_waveform_period_0_reg_get(dev_id, phy_id, ®_val); - *value = reg_val.bf.phase_ali; - return ret; -} - -sw_error_t -qca808x_ptp_freq_waveform_period_0_reg_phase_ali_set( - a_uint32_t dev_id, a_uint32_t phy_id, - a_uint32_t value) -{ - union ptp_freq_waveform_period_0_reg_u reg_val; - sw_error_t ret = SW_OK; - - ret = qca808x_ptp_freq_waveform_period_0_reg_get(dev_id, phy_id, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.phase_ali = value; - ret = qca808x_ptp_freq_waveform_period_0_reg_set(dev_id, phy_id, ®_val); - return ret; -} - -sw_error_t -qca808x_ptp_freq_waveform_period_1_reg_get( - a_uint32_t dev_id, a_uint32_t phy_id, - union ptp_freq_waveform_period_1_reg_u *value) -{ - return qca808x_phy_ptp_mmd_read( - dev_id, - phy_id, QCA808X_PHY_MMD3_NUM, PTP_FREQ_WAVEFORM_PERIOD_1_REG_ADDRESS, - &value->val); -} - -sw_error_t -qca808x_ptp_freq_waveform_period_1_reg_set( - a_uint32_t dev_id, a_uint32_t phy_id, - union ptp_freq_waveform_period_1_reg_u *value) -{ - return qca808x_phy_ptp_mmd_write( - dev_id, - phy_id, QCA808X_PHY_MMD3_NUM, PTP_FREQ_WAVEFORM_PERIOD_1_REG_ADDRESS, - value->val); -} - -sw_error_t -qca808x_ptp_freq_waveform_period_1_reg_wave_period_get( - a_uint32_t dev_id, a_uint32_t phy_id, - a_uint32_t *value) -{ - union ptp_freq_waveform_period_1_reg_u reg_val; - sw_error_t ret = SW_OK; - - ret = qca808x_ptp_freq_waveform_period_1_reg_get(dev_id, phy_id, ®_val); - *value = reg_val.bf.wave_period; - return ret; -} - -sw_error_t -qca808x_ptp_freq_waveform_period_1_reg_wave_period_set( - a_uint32_t dev_id, a_uint32_t phy_id, - a_uint32_t value) -{ - union ptp_freq_waveform_period_1_reg_u reg_val; - sw_error_t ret = SW_OK; - - ret = qca808x_ptp_freq_waveform_period_1_reg_get(dev_id, phy_id, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.wave_period = value; - ret = qca808x_ptp_freq_waveform_period_1_reg_set(dev_id, phy_id, ®_val); - return ret; -} - -sw_error_t -qca808x_ptp_freq_waveform_period_2_reg_get( - a_uint32_t dev_id, a_uint32_t phy_id, - union ptp_freq_waveform_period_2_reg_u *value) -{ - return qca808x_phy_ptp_mmd_read( - dev_id, - phy_id, QCA808X_PHY_MMD3_NUM, PTP_FREQ_WAVEFORM_PERIOD_2_REG_ADDRESS, - &value->val); -} - -sw_error_t -qca808x_ptp_freq_waveform_period_2_reg_set( - a_uint32_t dev_id, a_uint32_t phy_id, - union ptp_freq_waveform_period_2_reg_u *value) -{ - return qca808x_phy_ptp_mmd_write( - dev_id, - phy_id, QCA808X_PHY_MMD3_NUM, PTP_FREQ_WAVEFORM_PERIOD_2_REG_ADDRESS, - value->val); -} - -sw_error_t -qca808x_ptp_freq_waveform_period_2_reg_wave_period_get( - a_uint32_t dev_id, a_uint32_t phy_id, - a_uint32_t *value) -{ - union ptp_freq_waveform_period_2_reg_u reg_val; - sw_error_t ret = SW_OK; - - ret = qca808x_ptp_freq_waveform_period_2_reg_get(dev_id, phy_id, ®_val); - *value = reg_val.bf.wave_period; - return ret; -} - -sw_error_t -qca808x_ptp_freq_waveform_period_2_reg_wave_period_set( - a_uint32_t dev_id, a_uint32_t phy_id, - a_uint32_t value) -{ - union ptp_freq_waveform_period_2_reg_u reg_val; - sw_error_t ret = SW_OK; - - ret = qca808x_ptp_freq_waveform_period_2_reg_get(dev_id, phy_id, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.wave_period = value; - ret = qca808x_ptp_freq_waveform_period_2_reg_set(dev_id, phy_id, ®_val); - return ret; -} - -sw_error_t -qca808x_ptp_rx_com_ts_ctrl_reg_get( - a_uint32_t dev_id, a_uint32_t phy_id, - union ptp_rx_com_ts_ctrl_reg_u *value) -{ - return qca808x_phy_ptp_mmd_read( - dev_id, - phy_id, QCA808X_PHY_MMD3_NUM, PTP_RX_COM_TS_CTRL_REG_ADDRESS, - &value->val); -} - -sw_error_t -qca808x_ptp_rx_com_ts_ctrl_reg_set( - a_uint32_t dev_id, a_uint32_t phy_id, - union ptp_rx_com_ts_ctrl_reg_u *value) -{ - return qca808x_phy_ptp_mmd_write( - dev_id, - phy_id, QCA808X_PHY_MMD3_NUM, PTP_RX_COM_TS_CTRL_REG_ADDRESS, - value->val); -} - -sw_error_t -qca808x_ptp_rx_filt_mac_da0_reg_get( - a_uint32_t dev_id, a_uint32_t phy_id, - union ptp_rx_filt_mac_da0_reg_u *value) -{ - return qca808x_phy_ptp_mmd_read( - dev_id, - phy_id, QCA808X_PHY_MMD3_NUM, PTP_RX_FILT_MAC_DA0_REG_ADDRESS, - &value->val); -} - -sw_error_t -qca808x_ptp_rx_filt_mac_da0_reg_set( - a_uint32_t dev_id, a_uint32_t phy_id, - union ptp_rx_filt_mac_da0_reg_u *value) -{ - return qca808x_phy_ptp_mmd_write( - dev_id, - phy_id, QCA808X_PHY_MMD3_NUM, PTP_RX_FILT_MAC_DA0_REG_ADDRESS, - value->val); -} - -sw_error_t -qca808x_ptp_rx_filt_mac_da1_reg_get( - a_uint32_t dev_id, a_uint32_t phy_id, - union ptp_rx_filt_mac_da1_reg_u *value) -{ - return qca808x_phy_ptp_mmd_read( - dev_id, - phy_id, QCA808X_PHY_MMD3_NUM, PTP_RX_FILT_MAC_DA1_REG_ADDRESS, - &value->val); -} - -sw_error_t -qca808x_ptp_rx_filt_mac_da1_reg_set( - a_uint32_t dev_id, a_uint32_t phy_id, - union ptp_rx_filt_mac_da1_reg_u *value) -{ - return qca808x_phy_ptp_mmd_write( - dev_id, - phy_id, QCA808X_PHY_MMD3_NUM, PTP_RX_FILT_MAC_DA1_REG_ADDRESS, - value->val); -} - -sw_error_t -qca808x_ptp_rx_filt_mac_da2_reg_get( - a_uint32_t dev_id, a_uint32_t phy_id, - union ptp_rx_filt_mac_da2_reg_u *value) -{ - return qca808x_phy_ptp_mmd_read( - dev_id, - phy_id, QCA808X_PHY_MMD3_NUM, PTP_RX_FILT_MAC_DA2_REG_ADDRESS, - &value->val); -} - -sw_error_t -qca808x_ptp_rx_filt_mac_da2_reg_set( - a_uint32_t dev_id, a_uint32_t phy_id, - union ptp_rx_filt_mac_da2_reg_u *value) -{ - return qca808x_phy_ptp_mmd_write( - dev_id, - phy_id, QCA808X_PHY_MMD3_NUM, PTP_RX_FILT_MAC_DA2_REG_ADDRESS, - value->val); -} - -sw_error_t -qca808x_ptp_rx_filt_ipv4_da0_reg_get( - a_uint32_t dev_id, a_uint32_t phy_id, - union ptp_rx_filt_ipv4_da0_reg_u *value) -{ - return qca808x_phy_ptp_mmd_read( - dev_id, - phy_id, QCA808X_PHY_MMD3_NUM, PTP_RX_FILT_IPV4_DA0_REG_ADDRESS, - &value->val); -} - -sw_error_t -qca808x_ptp_rx_filt_ipv4_da0_reg_set( - a_uint32_t dev_id, a_uint32_t phy_id, - union ptp_rx_filt_ipv4_da0_reg_u *value) -{ - return qca808x_phy_ptp_mmd_write( - dev_id, - phy_id, QCA808X_PHY_MMD3_NUM, PTP_RX_FILT_IPV4_DA0_REG_ADDRESS, - value->val); -} - -sw_error_t -qca808x_ptp_rx_filt_ipv4_da1_reg_get( - a_uint32_t dev_id, a_uint32_t phy_id, - union ptp_rx_filt_ipv4_da1_reg_u *value) -{ - return qca808x_phy_ptp_mmd_read( - dev_id, - phy_id, QCA808X_PHY_MMD3_NUM, PTP_RX_FILT_IPV4_DA1_REG_ADDRESS, - &value->val); -} - -sw_error_t -qca808x_ptp_rx_filt_ipv4_da1_reg_set( - a_uint32_t dev_id, a_uint32_t phy_id, - union ptp_rx_filt_ipv4_da1_reg_u *value) -{ - return qca808x_phy_ptp_mmd_write( - dev_id, - phy_id, QCA808X_PHY_MMD3_NUM, PTP_RX_FILT_IPV4_DA1_REG_ADDRESS, - value->val); -} - -sw_error_t -qca808x_ptp_rx_filt_ipv6_da0_reg_get( - a_uint32_t dev_id, a_uint32_t phy_id, - union ptp_rx_filt_ipv6_da0_reg_u *value) -{ - return qca808x_phy_ptp_mmd_read( - dev_id, - phy_id, QCA808X_PHY_MMD3_NUM, PTP_RX_FILT_IPV6_DA0_REG_ADDRESS, - &value->val); -} - -sw_error_t -qca808x_ptp_rx_filt_ipv6_da0_reg_set( - a_uint32_t dev_id, a_uint32_t phy_id, - union ptp_rx_filt_ipv6_da0_reg_u *value) -{ - return qca808x_phy_ptp_mmd_write( - dev_id, - phy_id, QCA808X_PHY_MMD3_NUM, PTP_RX_FILT_IPV6_DA0_REG_ADDRESS, - value->val); -} - -sw_error_t -qca808x_ptp_rx_filt_ipv6_da1_reg_get( - a_uint32_t dev_id, a_uint32_t phy_id, - union ptp_rx_filt_ipv6_da1_reg_u *value) -{ - return qca808x_phy_ptp_mmd_read( - dev_id, - phy_id, QCA808X_PHY_MMD3_NUM, PTP_RX_FILT_IPV6_DA1_REG_ADDRESS, - &value->val); -} - -sw_error_t -qca808x_ptp_rx_filt_ipv6_da1_reg_set( - a_uint32_t dev_id, a_uint32_t phy_id, - union ptp_rx_filt_ipv6_da1_reg_u *value) -{ - return qca808x_phy_ptp_mmd_write( - dev_id, - phy_id, QCA808X_PHY_MMD3_NUM, PTP_RX_FILT_IPV6_DA1_REG_ADDRESS, - value->val); -} - -sw_error_t -qca808x_ptp_rx_filt_ipv6_da2_reg_get( - a_uint32_t dev_id, a_uint32_t phy_id, - union ptp_rx_filt_ipv6_da2_reg_u *value) -{ - return qca808x_phy_ptp_mmd_read( - dev_id, - phy_id, QCA808X_PHY_MMD3_NUM, PTP_RX_FILT_IPV6_DA2_REG_ADDRESS, - &value->val); -} - -sw_error_t -qca808x_ptp_rx_filt_ipv6_da2_reg_set( - a_uint32_t dev_id, a_uint32_t phy_id, - union ptp_rx_filt_ipv6_da2_reg_u *value) -{ - return qca808x_phy_ptp_mmd_write( - dev_id, - phy_id, QCA808X_PHY_MMD3_NUM, PTP_RX_FILT_IPV6_DA2_REG_ADDRESS, - value->val); -} - -sw_error_t -qca808x_ptp_rx_filt_ipv6_da3_reg_get( - a_uint32_t dev_id, a_uint32_t phy_id, - union ptp_rx_filt_ipv6_da3_reg_u *value) -{ - return qca808x_phy_ptp_mmd_read( - dev_id, - phy_id, QCA808X_PHY_MMD3_NUM, PTP_RX_FILT_IPV6_DA3_REG_ADDRESS, - &value->val); -} - -sw_error_t -qca808x_ptp_rx_filt_ipv6_da3_reg_set( - a_uint32_t dev_id, a_uint32_t phy_id, - union ptp_rx_filt_ipv6_da3_reg_u *value) -{ - return qca808x_phy_ptp_mmd_write( - dev_id, - phy_id, QCA808X_PHY_MMD3_NUM, PTP_RX_FILT_IPV6_DA3_REG_ADDRESS, - value->val); -} - -sw_error_t -qca808x_ptp_rx_filt_ipv6_da4_reg_get( - a_uint32_t dev_id, a_uint32_t phy_id, - union ptp_rx_filt_ipv6_da4_reg_u *value) -{ - return qca808x_phy_ptp_mmd_read( - dev_id, - phy_id, QCA808X_PHY_MMD3_NUM, PTP_RX_FILT_IPV6_DA4_REG_ADDRESS, - &value->val); -} - -sw_error_t -qca808x_ptp_rx_filt_ipv6_da4_reg_set( - a_uint32_t dev_id, a_uint32_t phy_id, - union ptp_rx_filt_ipv6_da4_reg_u *value) -{ - return qca808x_phy_ptp_mmd_write( - dev_id, - phy_id, QCA808X_PHY_MMD3_NUM, PTP_RX_FILT_IPV6_DA4_REG_ADDRESS, - value->val); -} - -sw_error_t -qca808x_ptp_rx_filt_ipv6_da5_reg_get( - a_uint32_t dev_id, a_uint32_t phy_id, - union ptp_rx_filt_ipv6_da5_reg_u *value) -{ - return qca808x_phy_ptp_mmd_read( - dev_id, - phy_id, QCA808X_PHY_MMD3_NUM, PTP_RX_FILT_IPV6_DA5_REG_ADDRESS, - &value->val); -} - -sw_error_t -qca808x_ptp_rx_filt_ipv6_da5_reg_set( - a_uint32_t dev_id, a_uint32_t phy_id, - union ptp_rx_filt_ipv6_da5_reg_u *value) -{ - return qca808x_phy_ptp_mmd_write( - dev_id, - phy_id, QCA808X_PHY_MMD3_NUM, PTP_RX_FILT_IPV6_DA5_REG_ADDRESS, - value->val); -} - -sw_error_t -qca808x_ptp_rx_filt_ipv6_da6_reg_get( - a_uint32_t dev_id, a_uint32_t phy_id, - union ptp_rx_filt_ipv6_da6_reg_u *value) -{ - return qca808x_phy_ptp_mmd_read( - dev_id, - phy_id, QCA808X_PHY_MMD3_NUM, PTP_RX_FILT_IPV6_DA6_REG_ADDRESS, - &value->val); -} - -sw_error_t -qca808x_ptp_rx_filt_ipv6_da6_reg_set( - a_uint32_t dev_id, a_uint32_t phy_id, - union ptp_rx_filt_ipv6_da6_reg_u *value) -{ - return qca808x_phy_ptp_mmd_write( - dev_id, - phy_id, QCA808X_PHY_MMD3_NUM, PTP_RX_FILT_IPV6_DA6_REG_ADDRESS, - value->val); -} - -sw_error_t -qca808x_ptp_rx_filt_ipv6_da7_reg_get( - a_uint32_t dev_id, a_uint32_t phy_id, - union ptp_rx_filt_ipv6_da7_reg_u *value) -{ - return qca808x_phy_ptp_mmd_read( - dev_id, - phy_id, QCA808X_PHY_MMD3_NUM, PTP_RX_FILT_IPV6_DA7_REG_ADDRESS, - &value->val); -} - -sw_error_t -qca808x_ptp_rx_filt_ipv6_da7_reg_set( - a_uint32_t dev_id, a_uint32_t phy_id, - union ptp_rx_filt_ipv6_da7_reg_u *value) -{ - return qca808x_phy_ptp_mmd_write( - dev_id, - phy_id, QCA808X_PHY_MMD3_NUM, PTP_RX_FILT_IPV6_DA7_REG_ADDRESS, - value->val); -} - -sw_error_t -qca808x_ptp_rx_filt_mac_lengthtype_reg_get( - a_uint32_t dev_id, a_uint32_t phy_id, - union ptp_rx_filt_mac_lengthtype_reg_u *value) -{ - return qca808x_phy_ptp_mmd_read( - dev_id, - phy_id, QCA808X_PHY_MMD3_NUM, PTP_RX_FILT_MAC_LENGTHTYPE_REG_ADDRESS, - &value->val); -} - -sw_error_t -qca808x_ptp_rx_filt_mac_lengthtype_reg_set( - a_uint32_t dev_id, a_uint32_t phy_id, - union ptp_rx_filt_mac_lengthtype_reg_u *value) -{ - return qca808x_phy_ptp_mmd_write( - dev_id, - phy_id, QCA808X_PHY_MMD3_NUM, PTP_RX_FILT_MAC_LENGTHTYPE_REG_ADDRESS, - value->val); -} - -sw_error_t -qca808x_ptp_rx_filt_layer4_protocol_reg_get( - a_uint32_t dev_id, a_uint32_t phy_id, - union ptp_rx_filt_layer4_protocol_reg_u *value) -{ - return qca808x_phy_ptp_mmd_read( - dev_id, - phy_id, QCA808X_PHY_MMD3_NUM, PTP_RX_FILT_LAYER4_PROTOCOL_REG_ADDRESS, - &value->val); -} - -sw_error_t -qca808x_ptp_rx_filt_layer4_protocol_reg_set( - a_uint32_t dev_id, a_uint32_t phy_id, - union ptp_rx_filt_layer4_protocol_reg_u *value) -{ - return qca808x_phy_ptp_mmd_write( - dev_id, - phy_id, QCA808X_PHY_MMD3_NUM, PTP_RX_FILT_LAYER4_PROTOCOL_REG_ADDRESS, - value->val); -} - -sw_error_t -qca808x_ptp_rx_filt_udp_port_reg_get( - a_uint32_t dev_id, a_uint32_t phy_id, - union ptp_rx_filt_udp_port_reg_u *value) -{ - return qca808x_phy_ptp_mmd_read( - dev_id, - phy_id, QCA808X_PHY_MMD3_NUM, PTP_RX_FILT_UDP_PORT_REG_ADDRESS, - &value->val); -} - -sw_error_t -qca808x_ptp_rx_filt_udp_port_reg_set( - a_uint32_t dev_id, a_uint32_t phy_id, - union ptp_rx_filt_udp_port_reg_u *value) -{ - return qca808x_phy_ptp_mmd_write( - dev_id, - phy_id, QCA808X_PHY_MMD3_NUM, PTP_RX_FILT_UDP_PORT_REG_ADDRESS, - value->val); -} - -sw_error_t -qca808x_ptp_rx_com_ts_status_reg_get( - a_uint32_t dev_id, a_uint32_t phy_id, - union ptp_rx_com_ts_status_reg_u *value) -{ - return qca808x_phy_ptp_mmd_read( - dev_id, - phy_id, QCA808X_PHY_MMD3_NUM, PTP_RX_COM_TS_STATUS_REG_ADDRESS, - &value->val); -} - -sw_error_t -qca808x_ptp_rx_com_ts_status_reg_set( - a_uint32_t dev_id, a_uint32_t phy_id, - union ptp_rx_com_ts_status_reg_u *value) -{ - return qca808x_phy_ptp_mmd_write( - dev_id, - phy_id, QCA808X_PHY_MMD3_NUM, PTP_RX_COM_TS_STATUS_REG_ADDRESS, - value->val); -} - -sw_error_t -qca808x_ptp_rx_com_timestamp0_reg_get( - a_uint32_t dev_id, a_uint32_t phy_id, - union ptp_rx_com_timestamp0_reg_u *value) -{ - return qca808x_phy_ptp_mmd_read( - dev_id, - phy_id, QCA808X_PHY_MMD3_NUM, PTP_RX_COM_TIMESTAMP0_REG_ADDRESS, - &value->val); -} - -sw_error_t -qca808x_ptp_rx_com_timestamp0_reg_set( - a_uint32_t dev_id, a_uint32_t phy_id, - union ptp_rx_com_timestamp0_reg_u *value) -{ - return qca808x_phy_ptp_mmd_write( - dev_id, - phy_id, QCA808X_PHY_MMD3_NUM, PTP_RX_COM_TIMESTAMP0_REG_ADDRESS, - value->val); -} - -sw_error_t -qca808x_ptp_rx_com_timestamp1_reg_get( - a_uint32_t dev_id, a_uint32_t phy_id, - union ptp_rx_com_timestamp1_reg_u *value) -{ - return qca808x_phy_ptp_mmd_read( - dev_id, - phy_id, QCA808X_PHY_MMD3_NUM, PTP_RX_COM_TIMESTAMP1_REG_ADDRESS, - &value->val); -} - -sw_error_t -qca808x_ptp_rx_com_timestamp1_reg_set( - a_uint32_t dev_id, a_uint32_t phy_id, - union ptp_rx_com_timestamp1_reg_u *value) -{ - return qca808x_phy_ptp_mmd_write( - dev_id, - phy_id, QCA808X_PHY_MMD3_NUM, PTP_RX_COM_TIMESTAMP1_REG_ADDRESS, - value->val); -} - -sw_error_t -qca808x_ptp_rx_com_timestamp2_reg_get( - a_uint32_t dev_id, a_uint32_t phy_id, - union ptp_rx_com_timestamp2_reg_u *value) -{ - return qca808x_phy_ptp_mmd_read( - dev_id, - phy_id, QCA808X_PHY_MMD3_NUM, PTP_RX_COM_TIMESTAMP2_REG_ADDRESS, - &value->val); -} - -sw_error_t -qca808x_ptp_rx_com_timestamp2_reg_set( - a_uint32_t dev_id, a_uint32_t phy_id, - union ptp_rx_com_timestamp2_reg_u *value) -{ - return qca808x_phy_ptp_mmd_write( - dev_id, - phy_id, QCA808X_PHY_MMD3_NUM, PTP_RX_COM_TIMESTAMP2_REG_ADDRESS, - value->val); -} - -sw_error_t -qca808x_ptp_rx_com_timestamp3_reg_get( - a_uint32_t dev_id, a_uint32_t phy_id, - union ptp_rx_com_timestamp3_reg_u *value) -{ - return qca808x_phy_ptp_mmd_read( - dev_id, - phy_id, QCA808X_PHY_MMD3_NUM, PTP_RX_COM_TIMESTAMP3_REG_ADDRESS, - &value->val); -} - -sw_error_t -qca808x_ptp_rx_com_timestamp3_reg_set( - a_uint32_t dev_id, a_uint32_t phy_id, - union ptp_rx_com_timestamp3_reg_u *value) -{ - return qca808x_phy_ptp_mmd_write( - dev_id, - phy_id, QCA808X_PHY_MMD3_NUM, PTP_RX_COM_TIMESTAMP3_REG_ADDRESS, - value->val); -} - -sw_error_t -qca808x_ptp_rx_com_timestamp4_reg_get( - a_uint32_t dev_id, a_uint32_t phy_id, - union ptp_rx_com_timestamp4_reg_u *value) -{ - return qca808x_phy_ptp_mmd_read( - dev_id, - phy_id, QCA808X_PHY_MMD3_NUM, PTP_RX_COM_TIMESTAMP4_REG_ADDRESS, - &value->val); -} - -sw_error_t -qca808x_ptp_rx_com_timestamp4_reg_set( - a_uint32_t dev_id, a_uint32_t phy_id, - union ptp_rx_com_timestamp4_reg_u *value) -{ - return qca808x_phy_ptp_mmd_write( - dev_id, - phy_id, QCA808X_PHY_MMD3_NUM, PTP_RX_COM_TIMESTAMP4_REG_ADDRESS, - value->val); -} - -sw_error_t -qca808x_ptp_rx_com_frac_nano_reg_get( - a_uint32_t dev_id, a_uint32_t phy_id, - union ptp_rx_com_frac_nano_reg_u *value) -{ - return qca808x_phy_ptp_mmd_read( - dev_id, - phy_id, QCA808X_PHY_MMD3_NUM, PTP_RX_COM_FRAC_NANO_REG_ADDRESS, - &value->val); -} - -sw_error_t -qca808x_ptp_rx_com_frac_nano_reg_set( - a_uint32_t dev_id, a_uint32_t phy_id, - union ptp_rx_com_frac_nano_reg_u *value) -{ - return qca808x_phy_ptp_mmd_write( - dev_id, - phy_id, QCA808X_PHY_MMD3_NUM, PTP_RX_COM_FRAC_NANO_REG_ADDRESS, - value->val); -} - -sw_error_t -qca808x_ptp_rx_com_timestamp_pre0_reg_get( - a_uint32_t dev_id, a_uint32_t phy_id, - union ptp_rx_com_timestamp_pre0_reg_u *value) -{ - return qca808x_phy_ptp_mmd_read( - dev_id, - phy_id, QCA808X_PHY_MMD3_NUM, PTP_RX_COM_TIMESTAMP_PRE0_REG_ADDRESS, - &value->val); -} - -sw_error_t -qca808x_ptp_rx_com_timestamp_pre0_reg_set( - a_uint32_t dev_id, a_uint32_t phy_id, - union ptp_rx_com_timestamp_pre0_reg_u *value) -{ - return qca808x_phy_ptp_mmd_write( - dev_id, - phy_id, QCA808X_PHY_MMD3_NUM, PTP_RX_COM_TIMESTAMP_PRE0_REG_ADDRESS, - value->val); -} - -sw_error_t -qca808x_ptp_rx_com_timestamp_pre1_reg_get( - a_uint32_t dev_id, a_uint32_t phy_id, - union ptp_rx_com_timestamp_pre1_reg_u *value) -{ - return qca808x_phy_ptp_mmd_read( - dev_id, - phy_id, QCA808X_PHY_MMD3_NUM, PTP_RX_COM_TIMESTAMP_PRE1_REG_ADDRESS, - &value->val); -} - -sw_error_t -qca808x_ptp_rx_com_timestamp_pre1_reg_set( - a_uint32_t dev_id, a_uint32_t phy_id, - union ptp_rx_com_timestamp_pre1_reg_u *value) -{ - return qca808x_phy_ptp_mmd_write( - dev_id, - phy_id, QCA808X_PHY_MMD3_NUM, PTP_RX_COM_TIMESTAMP_PRE1_REG_ADDRESS, - value->val); -} - -sw_error_t -qca808x_ptp_rx_com_timestamp_pre2_reg_get( - a_uint32_t dev_id, a_uint32_t phy_id, - union ptp_rx_com_timestamp_pre2_reg_u *value) -{ - return qca808x_phy_ptp_mmd_read( - dev_id, - phy_id, QCA808X_PHY_MMD3_NUM, PTP_RX_COM_TIMESTAMP_PRE2_REG_ADDRESS, - &value->val); -} - -sw_error_t -qca808x_ptp_rx_com_timestamp_pre2_reg_set( - a_uint32_t dev_id, a_uint32_t phy_id, - union ptp_rx_com_timestamp_pre2_reg_u *value) -{ - return qca808x_phy_ptp_mmd_write( - dev_id, - phy_id, QCA808X_PHY_MMD3_NUM, PTP_RX_COM_TIMESTAMP_PRE2_REG_ADDRESS, - value->val); -} - -sw_error_t -qca808x_ptp_rx_com_timestamp_pre3_reg_get( - a_uint32_t dev_id, a_uint32_t phy_id, - union ptp_rx_com_timestamp_pre3_reg_u *value) -{ - return qca808x_phy_ptp_mmd_read( - dev_id, - phy_id, QCA808X_PHY_MMD3_NUM, PTP_RX_COM_TIMESTAMP_PRE3_REG_ADDRESS, - &value->val); -} - -sw_error_t -qca808x_ptp_rx_com_timestamp_pre3_reg_set( - a_uint32_t dev_id, a_uint32_t phy_id, - union ptp_rx_com_timestamp_pre3_reg_u *value) -{ - return qca808x_phy_ptp_mmd_write( - dev_id, - phy_id, QCA808X_PHY_MMD3_NUM, PTP_RX_COM_TIMESTAMP_PRE3_REG_ADDRESS, - value->val); -} - -sw_error_t -qca808x_ptp_rx_com_timestamp_pre4_reg_get( - a_uint32_t dev_id, a_uint32_t phy_id, - union ptp_rx_com_timestamp_pre4_reg_u *value) -{ - return qca808x_phy_ptp_mmd_read( - dev_id, - phy_id, QCA808X_PHY_MMD3_NUM, PTP_RX_COM_TIMESTAMP_PRE4_REG_ADDRESS, - &value->val); -} - -sw_error_t -qca808x_ptp_rx_com_timestamp_pre4_reg_set( - a_uint32_t dev_id, a_uint32_t phy_id, - union ptp_rx_com_timestamp_pre4_reg_u *value) -{ - return qca808x_phy_ptp_mmd_write( - dev_id, - phy_id, QCA808X_PHY_MMD3_NUM, PTP_RX_COM_TIMESTAMP_PRE4_REG_ADDRESS, - value->val); -} - -sw_error_t -qca808x_ptp_rx_com_frac_nano_pre_reg_get( - a_uint32_t dev_id, a_uint32_t phy_id, - union ptp_rx_com_frac_nano_pre_reg_u *value) -{ - return qca808x_phy_ptp_mmd_read( - dev_id, - phy_id, QCA808X_PHY_MMD3_NUM, PTP_RX_COM_FRAC_NANO_PRE_REG_ADDRESS, - &value->val); -} - -sw_error_t -qca808x_ptp_rx_com_frac_nano_pre_reg_set( - a_uint32_t dev_id, a_uint32_t phy_id, - union ptp_rx_com_frac_nano_pre_reg_u *value) -{ - return qca808x_phy_ptp_mmd_write( - dev_id, - phy_id, QCA808X_PHY_MMD3_NUM, PTP_RX_COM_FRAC_NANO_PRE_REG_ADDRESS, - value->val); -} - -sw_error_t -qca808x_ptp_rx_y1731_identify_reg_get( - a_uint32_t dev_id, a_uint32_t phy_id, - union ptp_rx_y1731_identify_reg_u *value) -{ - return qca808x_phy_ptp_mmd_read( - dev_id, - phy_id, QCA808X_PHY_MMD3_NUM, PTP_RX_Y1731_IDENTIFY_REG_ADDRESS, - &value->val); -} - -sw_error_t -qca808x_ptp_rx_y1731_identify_reg_set( - a_uint32_t dev_id, a_uint32_t phy_id, - union ptp_rx_y1731_identify_reg_u *value) -{ - return qca808x_phy_ptp_mmd_write( - dev_id, - phy_id, QCA808X_PHY_MMD3_NUM, PTP_RX_Y1731_IDENTIFY_REG_ADDRESS, - value->val); -} - -sw_error_t -qca808x_ptp_rx_y1731_identify_pre_reg_get( - a_uint32_t dev_id, a_uint32_t phy_id, - union ptp_rx_y1731_identify_pre_reg_u *value) -{ - return qca808x_phy_ptp_mmd_read( - dev_id, - phy_id, QCA808X_PHY_MMD3_NUM, PTP_RX_Y1731_IDENTIFY_PRE_REG_ADDRESS, - &value->val); -} - -sw_error_t -qca808x_ptp_rx_y1731_identify_pre_reg_set( - a_uint32_t dev_id, a_uint32_t phy_id, - union ptp_rx_y1731_identify_pre_reg_u *value) -{ - return qca808x_phy_ptp_mmd_write( - dev_id, - phy_id, QCA808X_PHY_MMD3_NUM, PTP_RX_Y1731_IDENTIFY_PRE_REG_ADDRESS, - value->val); -} - -sw_error_t -qca808x_ptp_tx_com_ts_ctrl_reg_get( - a_uint32_t dev_id, a_uint32_t phy_id, - union ptp_tx_com_ts_ctrl_reg_u *value) -{ - return qca808x_phy_ptp_mmd_read( - dev_id, - phy_id, QCA808X_PHY_MMD3_NUM, PTP_TX_COM_TS_CTRL_REG_ADDRESS, - &value->val); -} - -sw_error_t -qca808x_ptp_tx_com_ts_ctrl_reg_set( - a_uint32_t dev_id, a_uint32_t phy_id, - union ptp_tx_com_ts_ctrl_reg_u *value) -{ - return qca808x_phy_ptp_mmd_write( - dev_id, - phy_id, QCA808X_PHY_MMD3_NUM, PTP_TX_COM_TS_CTRL_REG_ADDRESS, - value->val); -} - -sw_error_t -qca808x_ptp_tx_filt_mac_da0_reg_get( - a_uint32_t dev_id, a_uint32_t phy_id, - union ptp_tx_filt_mac_da0_reg_u *value) -{ - return qca808x_phy_ptp_mmd_read( - dev_id, - phy_id, QCA808X_PHY_MMD3_NUM, PTP_TX_FILT_MAC_DA0_REG_ADDRESS, - &value->val); -} - -sw_error_t -qca808x_ptp_tx_filt_mac_da0_reg_set( - a_uint32_t dev_id, a_uint32_t phy_id, - union ptp_tx_filt_mac_da0_reg_u *value) -{ - return qca808x_phy_ptp_mmd_write( - dev_id, - phy_id, QCA808X_PHY_MMD3_NUM, PTP_TX_FILT_MAC_DA0_REG_ADDRESS, - value->val); -} - -sw_error_t -qca808x_ptp_tx_filt_mac_da1_reg_get( - a_uint32_t dev_id, a_uint32_t phy_id, - union ptp_tx_filt_mac_da1_reg_u *value) -{ - return qca808x_phy_ptp_mmd_read( - dev_id, - phy_id, QCA808X_PHY_MMD3_NUM, PTP_TX_FILT_MAC_DA1_REG_ADDRESS, - &value->val); -} - -sw_error_t -qca808x_ptp_tx_filt_mac_da1_reg_set( - a_uint32_t dev_id, a_uint32_t phy_id, - union ptp_tx_filt_mac_da1_reg_u *value) -{ - return qca808x_phy_ptp_mmd_write( - dev_id, - phy_id, QCA808X_PHY_MMD3_NUM, PTP_TX_FILT_MAC_DA1_REG_ADDRESS, - value->val); -} - -sw_error_t -qca808x_ptp_tx_filt_mac_da2_reg_get( - a_uint32_t dev_id, a_uint32_t phy_id, - union ptp_tx_filt_mac_da2_reg_u *value) -{ - return qca808x_phy_ptp_mmd_read( - dev_id, - phy_id, QCA808X_PHY_MMD3_NUM, PTP_TX_FILT_MAC_DA2_REG_ADDRESS, - &value->val); -} - -sw_error_t -qca808x_ptp_tx_filt_mac_da2_reg_set( - a_uint32_t dev_id, a_uint32_t phy_id, - union ptp_tx_filt_mac_da2_reg_u *value) -{ - return qca808x_phy_ptp_mmd_write( - dev_id, - phy_id, QCA808X_PHY_MMD3_NUM, PTP_TX_FILT_MAC_DA2_REG_ADDRESS, - value->val); -} - -sw_error_t -qca808x_ptp_tx_filt_ipv4_da0_reg_get( - a_uint32_t dev_id, a_uint32_t phy_id, - union ptp_tx_filt_ipv4_da0_reg_u *value) -{ - return qca808x_phy_ptp_mmd_read( - dev_id, - phy_id, QCA808X_PHY_MMD3_NUM, PTP_TX_FILT_IPV4_DA0_REG_ADDRESS, - &value->val); -} - -sw_error_t -qca808x_ptp_tx_filt_ipv4_da0_reg_set( - a_uint32_t dev_id, a_uint32_t phy_id, - union ptp_tx_filt_ipv4_da0_reg_u *value) -{ - return qca808x_phy_ptp_mmd_write( - dev_id, - phy_id, QCA808X_PHY_MMD3_NUM, PTP_TX_FILT_IPV4_DA0_REG_ADDRESS, - value->val); -} - -sw_error_t -qca808x_ptp_tx_filt_ipv4_da1_reg_get( - a_uint32_t dev_id, a_uint32_t phy_id, - union ptp_tx_filt_ipv4_da1_reg_u *value) -{ - return qca808x_phy_ptp_mmd_read( - dev_id, - phy_id, QCA808X_PHY_MMD3_NUM, PTP_TX_FILT_IPV4_DA1_REG_ADDRESS, - &value->val); -} - -sw_error_t -qca808x_ptp_tx_filt_ipv4_da1_reg_set( - a_uint32_t dev_id, a_uint32_t phy_id, - union ptp_tx_filt_ipv4_da1_reg_u *value) -{ - return qca808x_phy_ptp_mmd_write( - dev_id, - phy_id, QCA808X_PHY_MMD3_NUM, PTP_TX_FILT_IPV4_DA1_REG_ADDRESS, - value->val); -} - -sw_error_t -qca808x_ptp_tx_filt_ipv6_da0_reg_get( - a_uint32_t dev_id, a_uint32_t phy_id, - union ptp_tx_filt_ipv6_da0_reg_u *value) -{ - return qca808x_phy_ptp_mmd_read( - dev_id, - phy_id, QCA808X_PHY_MMD3_NUM, PTP_TX_FILT_IPV6_DA0_REG_ADDRESS, - &value->val); -} - -sw_error_t -qca808x_ptp_tx_filt_ipv6_da0_reg_set( - a_uint32_t dev_id, a_uint32_t phy_id, - union ptp_tx_filt_ipv6_da0_reg_u *value) -{ - return qca808x_phy_ptp_mmd_write( - dev_id, - phy_id, QCA808X_PHY_MMD3_NUM, PTP_TX_FILT_IPV6_DA0_REG_ADDRESS, - value->val); -} - -sw_error_t -qca808x_ptp_tx_filt_ipv6_da1_reg_get( - a_uint32_t dev_id, a_uint32_t phy_id, - union ptp_tx_filt_ipv6_da1_reg_u *value) -{ - return qca808x_phy_ptp_mmd_read( - dev_id, - phy_id, QCA808X_PHY_MMD3_NUM, PTP_TX_FILT_IPV6_DA1_REG_ADDRESS, - &value->val); -} - -sw_error_t -qca808x_ptp_tx_filt_ipv6_da1_reg_set( - a_uint32_t dev_id, a_uint32_t phy_id, - union ptp_tx_filt_ipv6_da1_reg_u *value) -{ - return qca808x_phy_ptp_mmd_write( - dev_id, - phy_id, QCA808X_PHY_MMD3_NUM, PTP_TX_FILT_IPV6_DA1_REG_ADDRESS, - value->val); -} - -sw_error_t -qca808x_ptp_tx_filt_ipv6_da2_reg_get( - a_uint32_t dev_id, a_uint32_t phy_id, - union ptp_tx_filt_ipv6_da2_reg_u *value) -{ - return qca808x_phy_ptp_mmd_read( - dev_id, - phy_id, QCA808X_PHY_MMD3_NUM, PTP_TX_FILT_IPV6_DA2_REG_ADDRESS, - &value->val); -} - -sw_error_t -qca808x_ptp_tx_filt_ipv6_da2_reg_set( - a_uint32_t dev_id, a_uint32_t phy_id, - union ptp_tx_filt_ipv6_da2_reg_u *value) -{ - return qca808x_phy_ptp_mmd_write( - dev_id, - phy_id, QCA808X_PHY_MMD3_NUM, PTP_TX_FILT_IPV6_DA2_REG_ADDRESS, - value->val); -} - -sw_error_t -qca808x_ptp_tx_filt_ipv6_da3_reg_get( - a_uint32_t dev_id, a_uint32_t phy_id, - union ptp_tx_filt_ipv6_da3_reg_u *value) -{ - return qca808x_phy_ptp_mmd_read( - dev_id, - phy_id, QCA808X_PHY_MMD3_NUM, PTP_TX_FILT_IPV6_DA3_REG_ADDRESS, - &value->val); -} - -sw_error_t -qca808x_ptp_tx_filt_ipv6_da3_reg_set( - a_uint32_t dev_id, a_uint32_t phy_id, - union ptp_tx_filt_ipv6_da3_reg_u *value) -{ - return qca808x_phy_ptp_mmd_write( - dev_id, - phy_id, QCA808X_PHY_MMD3_NUM, PTP_TX_FILT_IPV6_DA3_REG_ADDRESS, - value->val); -} - -sw_error_t -qca808x_ptp_tx_filt_ipv6_da4_reg_get( - a_uint32_t dev_id, a_uint32_t phy_id, - union ptp_tx_filt_ipv6_da4_reg_u *value) -{ - return qca808x_phy_ptp_mmd_read( - dev_id, - phy_id, QCA808X_PHY_MMD3_NUM, PTP_TX_FILT_IPV6_DA4_REG_ADDRESS, - &value->val); -} - -sw_error_t -qca808x_ptp_tx_filt_ipv6_da4_reg_set( - a_uint32_t dev_id, a_uint32_t phy_id, - union ptp_tx_filt_ipv6_da4_reg_u *value) -{ - return qca808x_phy_ptp_mmd_write( - dev_id, - phy_id, QCA808X_PHY_MMD3_NUM, PTP_TX_FILT_IPV6_DA4_REG_ADDRESS, - value->val); -} - -sw_error_t -qca808x_ptp_tx_filt_ipv6_da5_reg_get( - a_uint32_t dev_id, a_uint32_t phy_id, - union ptp_tx_filt_ipv6_da5_reg_u *value) -{ - return qca808x_phy_ptp_mmd_read( - dev_id, - phy_id, QCA808X_PHY_MMD3_NUM, PTP_TX_FILT_IPV6_DA5_REG_ADDRESS, - &value->val); -} - -sw_error_t -qca808x_ptp_tx_filt_ipv6_da5_reg_set( - a_uint32_t dev_id, a_uint32_t phy_id, - union ptp_tx_filt_ipv6_da5_reg_u *value) -{ - return qca808x_phy_ptp_mmd_write( - dev_id, - phy_id, QCA808X_PHY_MMD3_NUM, PTP_TX_FILT_IPV6_DA5_REG_ADDRESS, - value->val); -} - -sw_error_t -qca808x_ptp_tx_filt_ipv6_da6_reg_get( - a_uint32_t dev_id, a_uint32_t phy_id, - union ptp_tx_filt_ipv6_da6_reg_u *value) -{ - return qca808x_phy_ptp_mmd_read( - dev_id, - phy_id, QCA808X_PHY_MMD3_NUM, PTP_TX_FILT_IPV6_DA6_REG_ADDRESS, - &value->val); -} - -sw_error_t -qca808x_ptp_tx_filt_ipv6_da6_reg_set( - a_uint32_t dev_id, a_uint32_t phy_id, - union ptp_tx_filt_ipv6_da6_reg_u *value) -{ - return qca808x_phy_ptp_mmd_write( - dev_id, - phy_id, QCA808X_PHY_MMD3_NUM, PTP_TX_FILT_IPV6_DA6_REG_ADDRESS, - value->val); -} - -sw_error_t -qca808x_ptp_tx_filt_ipv6_da7_reg_get( - a_uint32_t dev_id, a_uint32_t phy_id, - union ptp_tx_filt_ipv6_da7_reg_u *value) -{ - return qca808x_phy_ptp_mmd_read( - dev_id, - phy_id, QCA808X_PHY_MMD3_NUM, PTP_TX_FILT_IPV6_DA7_REG_ADDRESS, - &value->val); -} - -sw_error_t -qca808x_ptp_tx_filt_ipv6_da7_reg_set( - a_uint32_t dev_id, a_uint32_t phy_id, - union ptp_tx_filt_ipv6_da7_reg_u *value) -{ - return qca808x_phy_ptp_mmd_write( - dev_id, - phy_id, QCA808X_PHY_MMD3_NUM, PTP_TX_FILT_IPV6_DA7_REG_ADDRESS, - value->val); -} - -sw_error_t -qca808x_ptp_tx_filt_mac_lengthtype_reg_get( - a_uint32_t dev_id, a_uint32_t phy_id, - union ptp_tx_filt_mac_lengthtype_reg_u *value) -{ - return qca808x_phy_ptp_mmd_read( - dev_id, - phy_id, QCA808X_PHY_MMD3_NUM, PTP_TX_FILT_MAC_LENGTHTYPE_REG_ADDRESS, - &value->val); -} - -sw_error_t -qca808x_ptp_tx_filt_mac_lengthtype_reg_set( - a_uint32_t dev_id, a_uint32_t phy_id, - union ptp_tx_filt_mac_lengthtype_reg_u *value) -{ - return qca808x_phy_ptp_mmd_write( - dev_id, - phy_id, QCA808X_PHY_MMD3_NUM, PTP_TX_FILT_MAC_LENGTHTYPE_REG_ADDRESS, - value->val); -} - -sw_error_t -qca808x_ptp_tx_filt_layer4_protocol_reg_get( - a_uint32_t dev_id, a_uint32_t phy_id, - union ptp_tx_filt_layer4_protocol_reg_u *value) -{ - return qca808x_phy_ptp_mmd_read( - dev_id, - phy_id, QCA808X_PHY_MMD3_NUM, PTP_TX_FILT_LAYER4_PROTOCOL_REG_ADDRESS, - &value->val); -} - -sw_error_t -qca808x_ptp_tx_filt_layer4_protocol_reg_set( - a_uint32_t dev_id, a_uint32_t phy_id, - union ptp_tx_filt_layer4_protocol_reg_u *value) -{ - return qca808x_phy_ptp_mmd_write( - dev_id, - phy_id, QCA808X_PHY_MMD3_NUM, PTP_TX_FILT_LAYER4_PROTOCOL_REG_ADDRESS, - value->val); -} - -sw_error_t -qca808x_ptp_tx_filt_udp_port_reg_get( - a_uint32_t dev_id, a_uint32_t phy_id, - union ptp_tx_filt_udp_port_reg_u *value) -{ - return qca808x_phy_ptp_mmd_read( - dev_id, - phy_id, QCA808X_PHY_MMD3_NUM, PTP_TX_FILT_UDP_PORT_REG_ADDRESS, - &value->val); -} - -sw_error_t -qca808x_ptp_tx_filt_udp_port_reg_set( - a_uint32_t dev_id, a_uint32_t phy_id, - union ptp_tx_filt_udp_port_reg_u *value) -{ - return qca808x_phy_ptp_mmd_write( - dev_id, - phy_id, QCA808X_PHY_MMD3_NUM, PTP_TX_FILT_UDP_PORT_REG_ADDRESS, - value->val); -} - -sw_error_t -qca808x_ptp_tx_com_ts_status_reg_get( - a_uint32_t dev_id, a_uint32_t phy_id, - union ptp_tx_com_ts_status_reg_u *value) -{ - return qca808x_phy_ptp_mmd_read( - dev_id, - phy_id, QCA808X_PHY_MMD3_NUM, PTP_TX_COM_TS_STATUS_REG_ADDRESS, - &value->val); -} - -sw_error_t -qca808x_ptp_tx_com_ts_status_reg_set( - a_uint32_t dev_id, a_uint32_t phy_id, - union ptp_tx_com_ts_status_reg_u *value) -{ - return qca808x_phy_ptp_mmd_write( - dev_id, - phy_id, QCA808X_PHY_MMD3_NUM, PTP_TX_COM_TS_STATUS_REG_ADDRESS, - value->val); -} - -sw_error_t -qca808x_ptp_tx_com_timestamp0_reg_get( - a_uint32_t dev_id, a_uint32_t phy_id, - union ptp_tx_com_timestamp0_reg_u *value) -{ - return qca808x_phy_ptp_mmd_read( - dev_id, - phy_id, QCA808X_PHY_MMD3_NUM, PTP_TX_COM_TIMESTAMP0_REG_ADDRESS, - &value->val); -} - -sw_error_t -qca808x_ptp_tx_com_timestamp0_reg_set( - a_uint32_t dev_id, a_uint32_t phy_id, - union ptp_tx_com_timestamp0_reg_u *value) -{ - return qca808x_phy_ptp_mmd_write( - dev_id, - phy_id, QCA808X_PHY_MMD3_NUM, PTP_TX_COM_TIMESTAMP0_REG_ADDRESS, - value->val); -} - -sw_error_t -qca808x_ptp_tx_com_timestamp1_reg_get( - a_uint32_t dev_id, a_uint32_t phy_id, - union ptp_tx_com_timestamp1_reg_u *value) -{ - return qca808x_phy_ptp_mmd_read( - dev_id, - phy_id, QCA808X_PHY_MMD3_NUM, PTP_TX_COM_TIMESTAMP1_REG_ADDRESS, - &value->val); -} - -sw_error_t -qca808x_ptp_tx_com_timestamp1_reg_set( - a_uint32_t dev_id, a_uint32_t phy_id, - union ptp_tx_com_timestamp1_reg_u *value) -{ - return qca808x_phy_ptp_mmd_write( - dev_id, - phy_id, QCA808X_PHY_MMD3_NUM, PTP_TX_COM_TIMESTAMP1_REG_ADDRESS, - value->val); -} - -sw_error_t -qca808x_ptp_tx_com_timestamp2_reg_get( - a_uint32_t dev_id, a_uint32_t phy_id, - union ptp_tx_com_timestamp2_reg_u *value) -{ - return qca808x_phy_ptp_mmd_read( - dev_id, - phy_id, QCA808X_PHY_MMD3_NUM, PTP_TX_COM_TIMESTAMP2_REG_ADDRESS, - &value->val); -} - -sw_error_t -qca808x_ptp_tx_com_timestamp2_reg_set( - a_uint32_t dev_id, a_uint32_t phy_id, - union ptp_tx_com_timestamp2_reg_u *value) -{ - return qca808x_phy_ptp_mmd_write( - dev_id, - phy_id, QCA808X_PHY_MMD3_NUM, PTP_TX_COM_TIMESTAMP2_REG_ADDRESS, - value->val); -} - -sw_error_t -qca808x_ptp_tx_com_timestamp3_reg_get( - a_uint32_t dev_id, a_uint32_t phy_id, - union ptp_tx_com_timestamp3_reg_u *value) -{ - return qca808x_phy_ptp_mmd_read( - dev_id, - phy_id, QCA808X_PHY_MMD3_NUM, PTP_TX_COM_TIMESTAMP3_REG_ADDRESS, - &value->val); -} - -sw_error_t -qca808x_ptp_tx_com_timestamp3_reg_set( - a_uint32_t dev_id, a_uint32_t phy_id, - union ptp_tx_com_timestamp3_reg_u *value) -{ - return qca808x_phy_ptp_mmd_write( - dev_id, - phy_id, QCA808X_PHY_MMD3_NUM, PTP_TX_COM_TIMESTAMP3_REG_ADDRESS, - value->val); -} - -sw_error_t -qca808x_ptp_tx_com_timestamp4_reg_get( - a_uint32_t dev_id, a_uint32_t phy_id, - union ptp_tx_com_timestamp4_reg_u *value) -{ - return qca808x_phy_ptp_mmd_read( - dev_id, - phy_id, QCA808X_PHY_MMD3_NUM, PTP_TX_COM_TIMESTAMP4_REG_ADDRESS, - &value->val); -} - -sw_error_t -qca808x_ptp_tx_com_timestamp4_reg_set( - a_uint32_t dev_id, a_uint32_t phy_id, - union ptp_tx_com_timestamp4_reg_u *value) -{ - return qca808x_phy_ptp_mmd_write( - dev_id, - phy_id, QCA808X_PHY_MMD3_NUM, PTP_TX_COM_TIMESTAMP4_REG_ADDRESS, - value->val); -} - -sw_error_t -qca808x_ptp_tx_com_frac_nano_reg_get( - a_uint32_t dev_id, a_uint32_t phy_id, - union ptp_tx_com_frac_nano_reg_u *value) -{ - return qca808x_phy_ptp_mmd_read( - dev_id, - phy_id, QCA808X_PHY_MMD3_NUM, PTP_TX_COM_FRAC_NANO_REG_ADDRESS, - &value->val); -} - -sw_error_t -qca808x_ptp_tx_com_frac_nano_reg_set( - a_uint32_t dev_id, a_uint32_t phy_id, - union ptp_tx_com_frac_nano_reg_u *value) -{ - return qca808x_phy_ptp_mmd_write( - dev_id, - phy_id, QCA808X_PHY_MMD3_NUM, PTP_TX_COM_FRAC_NANO_REG_ADDRESS, - value->val); -} - -sw_error_t -qca808x_ptp_tx_y1731_identify_reg_get( - a_uint32_t dev_id, a_uint32_t phy_id, - union ptp_tx_y1731_identify_reg_u *value) -{ - return qca808x_phy_ptp_mmd_read( - dev_id, - phy_id, QCA808X_PHY_MMD3_NUM, PTP_TX_Y1731_IDENTIFY_REG_ADDRESS, - &value->val); -} - -sw_error_t -qca808x_ptp_tx_y1731_identify_reg_set( - a_uint32_t dev_id, a_uint32_t phy_id, - union ptp_tx_y1731_identify_reg_u *value) -{ - return qca808x_phy_ptp_mmd_write( - dev_id, - phy_id, QCA808X_PHY_MMD3_NUM, PTP_TX_Y1731_IDENTIFY_REG_ADDRESS, - value->val); -} - -sw_error_t -qca808x_ptp_y1731_dm_control_reg_get( - a_uint32_t dev_id, a_uint32_t phy_id, - union ptp_y1731_dm_control_reg_u *value) -{ - return qca808x_phy_ptp_mmd_read( - dev_id, - phy_id, QCA808X_PHY_MMD3_NUM, PTP_Y1731_DM_CONTROL_REG_ADDRESS, - &value->val); -} - -sw_error_t -qca808x_ptp_y1731_dm_control_reg_set( - a_uint32_t dev_id, a_uint32_t phy_id, - union ptp_y1731_dm_control_reg_u *value) -{ - return qca808x_phy_ptp_mmd_write( - dev_id, - phy_id, QCA808X_PHY_MMD3_NUM, PTP_Y1731_DM_CONTROL_REG_ADDRESS, - value->val); -} - -sw_error_t -qca808x_ptp_rx_com_ts_status_pre_reg_get( - a_uint32_t dev_id, a_uint32_t phy_id, - union ptp_rx_com_ts_status_pre_reg_u *value) -{ - return qca808x_phy_ptp_mmd_read( - dev_id, - phy_id, QCA808X_PHY_MMD3_NUM, PTP_RX_COM_TS_STATUS_PRE_REG_ADDRESS, - &value->val); -} - -sw_error_t -qca808x_ptp_rx_com_ts_status_pre_reg_set( - a_uint32_t dev_id, a_uint32_t phy_id, - union ptp_rx_com_ts_status_pre_reg_u *value) -{ - return qca808x_phy_ptp_mmd_write( - dev_id, - phy_id, QCA808X_PHY_MMD3_NUM, PTP_RX_COM_TS_STATUS_PRE_REG_ADDRESS, - value->val); -} - -sw_error_t -qca808x_ptp_baud_config_reg_get( - a_uint32_t dev_id, a_uint32_t phy_id, - union ptp_baud_config_reg_u *value) -{ - return qca808x_phy_ptp_mmd_read( - dev_id, - phy_id, QCA808X_PHY_MMD3_NUM, PTP_BAUD_CONFIG_REG_ADDRESS, - &value->val); -} - -sw_error_t -qca808x_ptp_baud_config_reg_set( - a_uint32_t dev_id, a_uint32_t phy_id, - union ptp_baud_config_reg_u *value) -{ - return qca808x_phy_ptp_mmd_write( - dev_id, - phy_id, QCA808X_PHY_MMD3_NUM, PTP_BAUD_CONFIG_REG_ADDRESS, - value->val); -} - -sw_error_t -qca808x_ptp_uart_configuration_reg_get( - a_uint32_t dev_id, a_uint32_t phy_id, - union ptp_uart_configuration_reg_u *value) -{ - return qca808x_phy_ptp_mmd_read( - dev_id, - phy_id, QCA808X_PHY_MMD3_NUM, PTP_UART_CONFIGURATION_REG_ADDRESS, - &value->val); -} - -sw_error_t -qca808x_ptp_uart_configuration_reg_set( - a_uint32_t dev_id, a_uint32_t phy_id, - union ptp_uart_configuration_reg_u *value) -{ - return qca808x_phy_ptp_mmd_write( - dev_id, - phy_id, QCA808X_PHY_MMD3_NUM, PTP_UART_CONFIGURATION_REG_ADDRESS, - value->val); -} - -sw_error_t -qca808x_ptp_reset_buffer_reg_get( - a_uint32_t dev_id, a_uint32_t phy_id, - union ptp_reset_buffer_reg_u *value) -{ - return qca808x_phy_ptp_mmd_read( - dev_id, - phy_id, QCA808X_PHY_MMD3_NUM, PTP_RESET_BUFFER_REG_ADDRESS, - &value->val); -} - -sw_error_t -qca808x_ptp_reset_buffer_reg_set( - a_uint32_t dev_id, a_uint32_t phy_id, - union ptp_reset_buffer_reg_u *value) -{ - return qca808x_phy_ptp_mmd_write( - dev_id, - phy_id, QCA808X_PHY_MMD3_NUM, PTP_RESET_BUFFER_REG_ADDRESS, - value->val); -} - -sw_error_t -qca808x_ptp_buffer_status_reg_get( - a_uint32_t dev_id, a_uint32_t phy_id, - union ptp_buffer_status_reg_u *value) -{ - return qca808x_phy_ptp_mmd_read( - dev_id, - phy_id, QCA808X_PHY_MMD3_NUM, PTP_BUFFER_STATUS_REG_ADDRESS, - &value->val); -} - -sw_error_t -qca808x_ptp_buffer_status_reg_set( - a_uint32_t dev_id, a_uint32_t phy_id, - union ptp_buffer_status_reg_u *value) -{ - return qca808x_phy_ptp_mmd_write( - dev_id, - phy_id, QCA808X_PHY_MMD3_NUM, PTP_BUFFER_STATUS_REG_ADDRESS, - value->val); -} - -sw_error_t -qca808x_ptp_tx_buffer_write_reg_get( - a_uint32_t dev_id, a_uint32_t phy_id, - union ptp_tx_buffer_write_reg_u *value) -{ - return qca808x_phy_ptp_mmd_read( - dev_id, - phy_id, QCA808X_PHY_MMD3_NUM, PTP_TX_BUFFER_WRITE_REG_ADDRESS, - &value->val); -} - -sw_error_t -qca808x_ptp_tx_buffer_write_reg_set( - a_uint32_t dev_id, a_uint32_t phy_id, - union ptp_tx_buffer_write_reg_u *value) -{ - return qca808x_phy_ptp_mmd_write( - dev_id, - phy_id, QCA808X_PHY_MMD3_NUM, PTP_TX_BUFFER_WRITE_REG_ADDRESS, - value->val); -} - -sw_error_t -qca808x_ptp_rx_buffer_read_reg_get( - a_uint32_t dev_id, a_uint32_t phy_id, - union ptp_rx_buffer_read_reg_u *value) -{ - return qca808x_phy_ptp_mmd_read( - dev_id, - phy_id, QCA808X_PHY_MMD3_NUM, PTP_RX_BUFFER_READ_REG_ADDRESS, - &value->val); -} - -sw_error_t -qca808x_ptp_rx_buffer_read_reg_set( - a_uint32_t dev_id, a_uint32_t phy_id, - union ptp_rx_buffer_read_reg_u *value) -{ - return qca808x_phy_ptp_mmd_write( - dev_id, - phy_id, QCA808X_PHY_MMD3_NUM, PTP_RX_BUFFER_READ_REG_ADDRESS, - value->val); -} - -sw_error_t -qca808x_ptp_rx_com_ts_ctrl_reg_ipv4_da_en_get( - a_uint32_t dev_id, a_uint32_t phy_id, - a_uint32_t *value) -{ - union ptp_rx_com_ts_ctrl_reg_u reg_val; - sw_error_t ret = SW_OK; - - ret = qca808x_ptp_rx_com_ts_ctrl_reg_get(dev_id, phy_id, ®_val); - *value = reg_val.bf.ipv4_da_en; - return ret; -} - -sw_error_t -qca808x_ptp_rx_com_ts_ctrl_reg_ipv4_da_en_set( - a_uint32_t dev_id, a_uint32_t phy_id, - a_uint32_t value) -{ - union ptp_rx_com_ts_ctrl_reg_u reg_val; - sw_error_t ret = SW_OK; - - ret = qca808x_ptp_rx_com_ts_ctrl_reg_get(dev_id, phy_id, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.ipv4_da_en = value; - ret = qca808x_ptp_rx_com_ts_ctrl_reg_set(dev_id, phy_id, ®_val); - return ret; -} - -sw_error_t -qca808x_ptp_rx_com_ts_ctrl_reg_mac_lengthtype_en_get( - a_uint32_t dev_id, a_uint32_t phy_id, - a_uint32_t *value) -{ - union ptp_rx_com_ts_ctrl_reg_u reg_val; - sw_error_t ret = SW_OK; - - ret = qca808x_ptp_rx_com_ts_ctrl_reg_get(dev_id, phy_id, ®_val); - *value = reg_val.bf.mac_lengthtype_en; - return ret; -} - -sw_error_t -qca808x_ptp_rx_com_ts_ctrl_reg_mac_lengthtype_en_set( - a_uint32_t dev_id, a_uint32_t phy_id, - a_uint32_t value) -{ - union ptp_rx_com_ts_ctrl_reg_u reg_val; - sw_error_t ret = SW_OK; - - ret = qca808x_ptp_rx_com_ts_ctrl_reg_get(dev_id, phy_id, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.mac_lengthtype_en = value; - ret = qca808x_ptp_rx_com_ts_ctrl_reg_set(dev_id, phy_id, ®_val); - return ret; -} - -sw_error_t -qca808x_ptp_rx_com_ts_ctrl_reg_y1731_da_chk_en_get( - a_uint32_t dev_id, a_uint32_t phy_id, - a_uint32_t *value) -{ - union ptp_rx_com_ts_ctrl_reg_u reg_val; - sw_error_t ret = SW_OK; - - ret = qca808x_ptp_rx_com_ts_ctrl_reg_get(dev_id, phy_id, ®_val); - *value = reg_val.bf.y1731_da_chk_en; - return ret; -} - -sw_error_t -qca808x_ptp_rx_com_ts_ctrl_reg_y1731_da_chk_en_set( - a_uint32_t dev_id, a_uint32_t phy_id, - a_uint32_t value) -{ - union ptp_rx_com_ts_ctrl_reg_u reg_val; - sw_error_t ret = SW_OK; - - ret = qca808x_ptp_rx_com_ts_ctrl_reg_get(dev_id, phy_id, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.y1731_da_chk_en = value; - ret = qca808x_ptp_rx_com_ts_ctrl_reg_set(dev_id, phy_id, ®_val); - return ret; -} - -sw_error_t -qca808x_ptp_rx_com_ts_ctrl_reg_pw_mac_en_get( - a_uint32_t dev_id, a_uint32_t phy_id, - a_uint32_t *value) -{ - union ptp_rx_com_ts_ctrl_reg_u reg_val; - sw_error_t ret = SW_OK; - - ret = qca808x_ptp_rx_com_ts_ctrl_reg_get(dev_id, phy_id, ®_val); - *value = reg_val.bf.pw_mac_en; - return ret; -} - -sw_error_t -qca808x_ptp_rx_com_ts_ctrl_reg_pw_mac_en_set( - a_uint32_t dev_id, a_uint32_t phy_id, - a_uint32_t value) -{ - union ptp_rx_com_ts_ctrl_reg_u reg_val; - sw_error_t ret = SW_OK; - - ret = qca808x_ptp_rx_com_ts_ctrl_reg_get(dev_id, phy_id, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.pw_mac_en = value; - ret = qca808x_ptp_rx_com_ts_ctrl_reg_set(dev_id, phy_id, ®_val); - return ret; -} - -sw_error_t -qca808x_ptp_rx_com_ts_ctrl_reg_udp_ptp_event_filt_en_get( - a_uint32_t dev_id, a_uint32_t phy_id, - a_uint32_t *value) -{ - union ptp_rx_com_ts_ctrl_reg_u reg_val; - sw_error_t ret = SW_OK; - - ret = qca808x_ptp_rx_com_ts_ctrl_reg_get(dev_id, phy_id, ®_val); - *value = reg_val.bf.udp_ptp_event_filt_en; - return ret; -} - -sw_error_t -qca808x_ptp_rx_com_ts_ctrl_reg_udp_ptp_event_filt_en_set( - a_uint32_t dev_id, a_uint32_t phy_id, - a_uint32_t value) -{ - union ptp_rx_com_ts_ctrl_reg_u reg_val; - sw_error_t ret = SW_OK; - - ret = qca808x_ptp_rx_com_ts_ctrl_reg_get(dev_id, phy_id, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.udp_ptp_event_filt_en = value; - ret = qca808x_ptp_rx_com_ts_ctrl_reg_set(dev_id, phy_id, ®_val); - return ret; -} - -sw_error_t -qca808x_ptp_rx_com_ts_ctrl_reg_udp_dport_en_get( - a_uint32_t dev_id, a_uint32_t phy_id, - a_uint32_t *value) -{ - union ptp_rx_com_ts_ctrl_reg_u reg_val; - sw_error_t ret = SW_OK; - - ret = qca808x_ptp_rx_com_ts_ctrl_reg_get(dev_id, phy_id, ®_val); - *value = reg_val.bf.udp_dport_en; - return ret; -} - -sw_error_t -qca808x_ptp_rx_com_ts_ctrl_reg_udp_dport_en_set( - a_uint32_t dev_id, a_uint32_t phy_id, - a_uint32_t value) -{ - union ptp_rx_com_ts_ctrl_reg_u reg_val; - sw_error_t ret = SW_OK; - - ret = qca808x_ptp_rx_com_ts_ctrl_reg_get(dev_id, phy_id, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.udp_dport_en = value; - ret = qca808x_ptp_rx_com_ts_ctrl_reg_set(dev_id, phy_id, ®_val); - return ret; -} - -sw_error_t -qca808x_ptp_rx_com_ts_ctrl_reg_mac_ptp_filt_en_get( - a_uint32_t dev_id, a_uint32_t phy_id, - a_uint32_t *value) -{ - union ptp_rx_com_ts_ctrl_reg_u reg_val; - sw_error_t ret = SW_OK; - - ret = qca808x_ptp_rx_com_ts_ctrl_reg_get(dev_id, phy_id, ®_val); - *value = reg_val.bf.mac_ptp_filt_en; - return ret; -} - -sw_error_t -qca808x_ptp_rx_com_ts_ctrl_reg_mac_ptp_filt_en_set( - a_uint32_t dev_id, a_uint32_t phy_id, - a_uint32_t value) -{ - union ptp_rx_com_ts_ctrl_reg_u reg_val; - sw_error_t ret = SW_OK; - - ret = qca808x_ptp_rx_com_ts_ctrl_reg_get(dev_id, phy_id, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.mac_ptp_filt_en = value; - ret = qca808x_ptp_rx_com_ts_ctrl_reg_set(dev_id, phy_id, ®_val); - return ret; -} - -sw_error_t -qca808x_ptp_rx_com_ts_ctrl_reg_ipv6_da_filt_en_get( - a_uint32_t dev_id, a_uint32_t phy_id, - a_uint32_t *value) -{ - union ptp_rx_com_ts_ctrl_reg_u reg_val; - sw_error_t ret = SW_OK; - - ret = qca808x_ptp_rx_com_ts_ctrl_reg_get(dev_id, phy_id, ®_val); - *value = reg_val.bf.ipv6_da_filt_en; - return ret; -} - -sw_error_t -qca808x_ptp_rx_com_ts_ctrl_reg_ipv6_da_filt_en_set( - a_uint32_t dev_id, a_uint32_t phy_id, - a_uint32_t value) -{ - union ptp_rx_com_ts_ctrl_reg_u reg_val; - sw_error_t ret = SW_OK; - - ret = qca808x_ptp_rx_com_ts_ctrl_reg_get(dev_id, phy_id, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.ipv6_da_filt_en = value; - ret = qca808x_ptp_rx_com_ts_ctrl_reg_set(dev_id, phy_id, ®_val); - return ret; -} - -sw_error_t -qca808x_ptp_rx_com_ts_ctrl_reg_ipv6_next_header_en_get( - a_uint32_t dev_id, a_uint32_t phy_id, - a_uint32_t *value) -{ - union ptp_rx_com_ts_ctrl_reg_u reg_val; - sw_error_t ret = SW_OK; - - ret = qca808x_ptp_rx_com_ts_ctrl_reg_get(dev_id, phy_id, ®_val); - *value = reg_val.bf.ipv6_next_header_en; - return ret; -} - -sw_error_t -qca808x_ptp_rx_com_ts_ctrl_reg_ipv6_next_header_en_set( - a_uint32_t dev_id, a_uint32_t phy_id, - a_uint32_t value) -{ - union ptp_rx_com_ts_ctrl_reg_u reg_val; - sw_error_t ret = SW_OK; - - ret = qca808x_ptp_rx_com_ts_ctrl_reg_get(dev_id, phy_id, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.ipv6_next_header_en = value; - ret = qca808x_ptp_rx_com_ts_ctrl_reg_set(dev_id, phy_id, ®_val); - return ret; -} - -sw_error_t -qca808x_ptp_rx_com_ts_ctrl_reg_ipv4_layer4_protocol_en_get( - a_uint32_t dev_id, a_uint32_t phy_id, - a_uint32_t *value) -{ - union ptp_rx_com_ts_ctrl_reg_u reg_val; - sw_error_t ret = SW_OK; - - ret = qca808x_ptp_rx_com_ts_ctrl_reg_get(dev_id, phy_id, ®_val); - *value = reg_val.bf.ipv4_layer4_protocol_en; - return ret; -} - -sw_error_t -qca808x_ptp_rx_com_ts_ctrl_reg_ipv4_layer4_protocol_en_set( - a_uint32_t dev_id, a_uint32_t phy_id, - a_uint32_t value) -{ - union ptp_rx_com_ts_ctrl_reg_u reg_val; - sw_error_t ret = SW_OK; - - ret = qca808x_ptp_rx_com_ts_ctrl_reg_get(dev_id, phy_id, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.ipv4_layer4_protocol_en = value; - ret = qca808x_ptp_rx_com_ts_ctrl_reg_set(dev_id, phy_id, ®_val); - return ret; -} - -sw_error_t -qca808x_ptp_rx_com_ts_ctrl_reg_y1731_en_get( - a_uint32_t dev_id, a_uint32_t phy_id, - a_uint32_t *value) -{ - union ptp_rx_com_ts_ctrl_reg_u reg_val; - sw_error_t ret = SW_OK; - - ret = qca808x_ptp_rx_com_ts_ctrl_reg_get(dev_id, phy_id, ®_val); - *value = reg_val.bf.y1731_en; - return ret; -} - -sw_error_t -qca808x_ptp_rx_com_ts_ctrl_reg_y1731_en_set( - a_uint32_t dev_id, a_uint32_t phy_id, - a_uint32_t value) -{ - union ptp_rx_com_ts_ctrl_reg_u reg_val; - sw_error_t ret = SW_OK; - - ret = qca808x_ptp_rx_com_ts_ctrl_reg_get(dev_id, phy_id, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.y1731_en = value; - ret = qca808x_ptp_rx_com_ts_ctrl_reg_set(dev_id, phy_id, ®_val); - return ret; -} - -sw_error_t -qca808x_ptp_rx_com_ts_ctrl_reg_filt_en_get( - a_uint32_t dev_id, a_uint32_t phy_id, - a_uint32_t *value) -{ - union ptp_rx_com_ts_ctrl_reg_u reg_val; - sw_error_t ret = SW_OK; - - ret = qca808x_ptp_rx_com_ts_ctrl_reg_get(dev_id, phy_id, ®_val); - *value = reg_val.bf.filt_en; - return ret; -} - -sw_error_t -qca808x_ptp_rx_com_ts_ctrl_reg_filt_en_set( - a_uint32_t dev_id, a_uint32_t phy_id, - a_uint32_t value) -{ - union ptp_rx_com_ts_ctrl_reg_u reg_val; - sw_error_t ret = SW_OK; - - ret = qca808x_ptp_rx_com_ts_ctrl_reg_get(dev_id, phy_id, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.filt_en = value; - ret = qca808x_ptp_rx_com_ts_ctrl_reg_set(dev_id, phy_id, ®_val); - return ret; -} - -sw_error_t -qca808x_ptp_rx_com_ts_ctrl_reg_ipv6_ptp_filt_en_get( - a_uint32_t dev_id, a_uint32_t phy_id, - a_uint32_t *value) -{ - union ptp_rx_com_ts_ctrl_reg_u reg_val; - sw_error_t ret = SW_OK; - - ret = qca808x_ptp_rx_com_ts_ctrl_reg_get(dev_id, phy_id, ®_val); - *value = reg_val.bf.ipv6_ptp_filt_en; - return ret; -} - -sw_error_t -qca808x_ptp_rx_com_ts_ctrl_reg_ipv6_ptp_filt_en_set( - a_uint32_t dev_id, a_uint32_t phy_id, - a_uint32_t value) -{ - union ptp_rx_com_ts_ctrl_reg_u reg_val; - sw_error_t ret = SW_OK; - - ret = qca808x_ptp_rx_com_ts_ctrl_reg_get(dev_id, phy_id, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.ipv6_ptp_filt_en = value; - ret = qca808x_ptp_rx_com_ts_ctrl_reg_set(dev_id, phy_id, ®_val); - return ret; -} - -sw_error_t -qca808x_ptp_rx_com_ts_ctrl_reg_ipv4_ptp_filt_en_get( - a_uint32_t dev_id, a_uint32_t phy_id, - a_uint32_t *value) -{ - union ptp_rx_com_ts_ctrl_reg_u reg_val; - sw_error_t ret = SW_OK; - - ret = qca808x_ptp_rx_com_ts_ctrl_reg_get(dev_id, phy_id, ®_val); - *value = reg_val.bf.ipv4_ptp_filt_en; - return ret; -} - -sw_error_t -qca808x_ptp_rx_com_ts_ctrl_reg_ipv4_ptp_filt_en_set( - a_uint32_t dev_id, a_uint32_t phy_id, - a_uint32_t value) -{ - union ptp_rx_com_ts_ctrl_reg_u reg_val; - sw_error_t ret = SW_OK; - - ret = qca808x_ptp_rx_com_ts_ctrl_reg_get(dev_id, phy_id, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.ipv4_ptp_filt_en = value; - ret = qca808x_ptp_rx_com_ts_ctrl_reg_set(dev_id, phy_id, ®_val); - return ret; -} - -sw_error_t -qca808x_ptp_rx_com_ts_ctrl_reg_y1731_insert_ts_en_get( - a_uint32_t dev_id, a_uint32_t phy_id, - a_uint32_t *value) -{ - union ptp_rx_com_ts_ctrl_reg_u reg_val; - sw_error_t ret = SW_OK; - - ret = qca808x_ptp_rx_com_ts_ctrl_reg_get(dev_id, phy_id, ®_val); - *value = reg_val.bf.y1731_insert_ts_en; - return ret; -} - -sw_error_t -qca808x_ptp_rx_com_ts_ctrl_reg_y1731_insert_ts_en_set( - a_uint32_t dev_id, a_uint32_t phy_id, - a_uint32_t value) -{ - union ptp_rx_com_ts_ctrl_reg_u reg_val; - sw_error_t ret = SW_OK; - - ret = qca808x_ptp_rx_com_ts_ctrl_reg_get(dev_id, phy_id, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.y1731_insert_ts_en = value; - ret = qca808x_ptp_rx_com_ts_ctrl_reg_set(dev_id, phy_id, ®_val); - return ret; -} - -sw_error_t -qca808x_ptp_rx_com_ts_ctrl_reg_mac_da_en_get( - a_uint32_t dev_id, a_uint32_t phy_id, - a_uint32_t *value) -{ - union ptp_rx_com_ts_ctrl_reg_u reg_val; - sw_error_t ret = SW_OK; - - ret = qca808x_ptp_rx_com_ts_ctrl_reg_get(dev_id, phy_id, ®_val); - *value = reg_val.bf.mac_da_en; - return ret; -} - -sw_error_t -qca808x_ptp_rx_com_ts_ctrl_reg_mac_da_en_set( - a_uint32_t dev_id, a_uint32_t phy_id, - a_uint32_t value) -{ - union ptp_rx_com_ts_ctrl_reg_u reg_val; - sw_error_t ret = SW_OK; - - ret = qca808x_ptp_rx_com_ts_ctrl_reg_get(dev_id, phy_id, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.mac_da_en = value; - ret = qca808x_ptp_rx_com_ts_ctrl_reg_set(dev_id, phy_id, ®_val); - return ret; -} - -sw_error_t -qca808x_ptp_rx_filt_mac_da0_reg_mac_addr_get( - a_uint32_t dev_id, a_uint32_t phy_id, - a_uint32_t *value) -{ - union ptp_rx_filt_mac_da0_reg_u reg_val; - sw_error_t ret = SW_OK; - - ret = qca808x_ptp_rx_filt_mac_da0_reg_get(dev_id, phy_id, ®_val); - *value = reg_val.bf.mac_addr; - return ret; -} - -sw_error_t -qca808x_ptp_rx_filt_mac_da0_reg_mac_addr_set( - a_uint32_t dev_id, a_uint32_t phy_id, - a_uint32_t value) -{ - union ptp_rx_filt_mac_da0_reg_u reg_val; - sw_error_t ret = SW_OK; - - ret = qca808x_ptp_rx_filt_mac_da0_reg_get(dev_id, phy_id, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.mac_addr = value; - ret = qca808x_ptp_rx_filt_mac_da0_reg_set(dev_id, phy_id, ®_val); - return ret; -} - -sw_error_t -qca808x_ptp_rx_filt_mac_da1_reg_mac_addr_get( - a_uint32_t dev_id, a_uint32_t phy_id, - a_uint32_t *value) -{ - union ptp_rx_filt_mac_da1_reg_u reg_val; - sw_error_t ret = SW_OK; - - ret = qca808x_ptp_rx_filt_mac_da1_reg_get(dev_id, phy_id, ®_val); - *value = reg_val.bf.mac_addr; - return ret; -} - -sw_error_t -qca808x_ptp_rx_filt_mac_da1_reg_mac_addr_set( - a_uint32_t dev_id, a_uint32_t phy_id, - a_uint32_t value) -{ - union ptp_rx_filt_mac_da1_reg_u reg_val; - sw_error_t ret = SW_OK; - - ret = qca808x_ptp_rx_filt_mac_da1_reg_get(dev_id, phy_id, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.mac_addr = value; - ret = qca808x_ptp_rx_filt_mac_da1_reg_set(dev_id, phy_id, ®_val); - return ret; -} - -sw_error_t -qca808x_ptp_rx_filt_mac_da2_reg_mac_addr_get( - a_uint32_t dev_id, a_uint32_t phy_id, - a_uint32_t *value) -{ - union ptp_rx_filt_mac_da2_reg_u reg_val; - sw_error_t ret = SW_OK; - - ret = qca808x_ptp_rx_filt_mac_da2_reg_get(dev_id, phy_id, ®_val); - *value = reg_val.bf.mac_addr; - return ret; -} - -sw_error_t -qca808x_ptp_rx_filt_mac_da2_reg_mac_addr_set( - a_uint32_t dev_id, a_uint32_t phy_id, - a_uint32_t value) -{ - union ptp_rx_filt_mac_da2_reg_u reg_val; - sw_error_t ret = SW_OK; - - ret = qca808x_ptp_rx_filt_mac_da2_reg_get(dev_id, phy_id, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.mac_addr = value; - ret = qca808x_ptp_rx_filt_mac_da2_reg_set(dev_id, phy_id, ®_val); - return ret; -} - -sw_error_t -qca808x_ptp_rx_filt_ipv4_da0_reg_ip_addr_get( - a_uint32_t dev_id, a_uint32_t phy_id, - a_uint32_t *value) -{ - union ptp_rx_filt_ipv4_da0_reg_u reg_val; - sw_error_t ret = SW_OK; - - ret = qca808x_ptp_rx_filt_ipv4_da0_reg_get(dev_id, phy_id, ®_val); - *value = reg_val.bf.ip_addr; - return ret; -} - -sw_error_t -qca808x_ptp_rx_filt_ipv4_da0_reg_ip_addr_set( - a_uint32_t dev_id, a_uint32_t phy_id, - a_uint32_t value) -{ - union ptp_rx_filt_ipv4_da0_reg_u reg_val; - sw_error_t ret = SW_OK; - - ret = qca808x_ptp_rx_filt_ipv4_da0_reg_get(dev_id, phy_id, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.ip_addr = value; - ret = qca808x_ptp_rx_filt_ipv4_da0_reg_set(dev_id, phy_id, ®_val); - return ret; -} - -sw_error_t -qca808x_ptp_rx_filt_ipv4_da1_reg_ip_addr_get( - a_uint32_t dev_id, a_uint32_t phy_id, - a_uint32_t *value) -{ - union ptp_rx_filt_ipv4_da1_reg_u reg_val; - sw_error_t ret = SW_OK; - - ret = qca808x_ptp_rx_filt_ipv4_da1_reg_get(dev_id, phy_id, ®_val); - *value = reg_val.bf.ip_addr; - return ret; -} - -sw_error_t -qca808x_ptp_rx_filt_ipv4_da1_reg_ip_addr_set( - a_uint32_t dev_id, a_uint32_t phy_id, - a_uint32_t value) -{ - union ptp_rx_filt_ipv4_da1_reg_u reg_val; - sw_error_t ret = SW_OK; - - ret = qca808x_ptp_rx_filt_ipv4_da1_reg_get(dev_id, phy_id, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.ip_addr = value; - ret = qca808x_ptp_rx_filt_ipv4_da1_reg_set(dev_id, phy_id, ®_val); - return ret; -} - -sw_error_t -qca808x_ptp_rx_filt_ipv6_da0_reg_ip_addr_get( - a_uint32_t dev_id, a_uint32_t phy_id, - a_uint32_t *value) -{ - union ptp_rx_filt_ipv6_da0_reg_u reg_val; - sw_error_t ret = SW_OK; - - ret = qca808x_ptp_rx_filt_ipv6_da0_reg_get(dev_id, phy_id, ®_val); - *value = reg_val.bf.ip_addr; - return ret; -} - -sw_error_t -qca808x_ptp_rx_filt_ipv6_da0_reg_ip_addr_set( - a_uint32_t dev_id, a_uint32_t phy_id, - a_uint32_t value) -{ - union ptp_rx_filt_ipv6_da0_reg_u reg_val; - sw_error_t ret = SW_OK; - - ret = qca808x_ptp_rx_filt_ipv6_da0_reg_get(dev_id, phy_id, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.ip_addr = value; - ret = qca808x_ptp_rx_filt_ipv6_da0_reg_set(dev_id, phy_id, ®_val); - return ret; -} - -sw_error_t -qca808x_ptp_rx_filt_ipv6_da1_reg_ip_addr_get( - a_uint32_t dev_id, a_uint32_t phy_id, - a_uint32_t *value) -{ - union ptp_rx_filt_ipv6_da1_reg_u reg_val; - sw_error_t ret = SW_OK; - - ret = qca808x_ptp_rx_filt_ipv6_da1_reg_get(dev_id, phy_id, ®_val); - *value = reg_val.bf.ip_addr; - return ret; -} - -sw_error_t -qca808x_ptp_rx_filt_ipv6_da1_reg_ip_addr_set( - a_uint32_t dev_id, a_uint32_t phy_id, - a_uint32_t value) -{ - union ptp_rx_filt_ipv6_da1_reg_u reg_val; - sw_error_t ret = SW_OK; - - ret = qca808x_ptp_rx_filt_ipv6_da1_reg_get(dev_id, phy_id, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.ip_addr = value; - ret = qca808x_ptp_rx_filt_ipv6_da1_reg_set(dev_id, phy_id, ®_val); - return ret; -} - -sw_error_t -qca808x_ptp_rx_filt_ipv6_da2_reg_ip_addr_get( - a_uint32_t dev_id, a_uint32_t phy_id, - a_uint32_t *value) -{ - union ptp_rx_filt_ipv6_da2_reg_u reg_val; - sw_error_t ret = SW_OK; - - ret = qca808x_ptp_rx_filt_ipv6_da2_reg_get(dev_id, phy_id, ®_val); - *value = reg_val.bf.ip_addr; - return ret; -} - -sw_error_t -qca808x_ptp_rx_filt_ipv6_da2_reg_ip_addr_set( - a_uint32_t dev_id, a_uint32_t phy_id, - a_uint32_t value) -{ - union ptp_rx_filt_ipv6_da2_reg_u reg_val; - sw_error_t ret = SW_OK; - - ret = qca808x_ptp_rx_filt_ipv6_da2_reg_get(dev_id, phy_id, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.ip_addr = value; - ret = qca808x_ptp_rx_filt_ipv6_da2_reg_set(dev_id, phy_id, ®_val); - return ret; -} - -sw_error_t -qca808x_ptp_rx_filt_ipv6_da3_reg_ip_addr_get( - a_uint32_t dev_id, a_uint32_t phy_id, - a_uint32_t *value) -{ - union ptp_rx_filt_ipv6_da3_reg_u reg_val; - sw_error_t ret = SW_OK; - - ret = qca808x_ptp_rx_filt_ipv6_da3_reg_get(dev_id, phy_id, ®_val); - *value = reg_val.bf.ip_addr; - return ret; -} - -sw_error_t -qca808x_ptp_rx_filt_ipv6_da3_reg_ip_addr_set( - a_uint32_t dev_id, a_uint32_t phy_id, - a_uint32_t value) -{ - union ptp_rx_filt_ipv6_da3_reg_u reg_val; - sw_error_t ret = SW_OK; - - ret = qca808x_ptp_rx_filt_ipv6_da3_reg_get(dev_id, phy_id, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.ip_addr = value; - ret = qca808x_ptp_rx_filt_ipv6_da3_reg_set(dev_id, phy_id, ®_val); - return ret; -} - -sw_error_t -qca808x_ptp_rx_filt_ipv6_da4_reg_ip_addr_get( - a_uint32_t dev_id, a_uint32_t phy_id, - a_uint32_t *value) -{ - union ptp_rx_filt_ipv6_da4_reg_u reg_val; - sw_error_t ret = SW_OK; - - ret = qca808x_ptp_rx_filt_ipv6_da4_reg_get(dev_id, phy_id, ®_val); - *value = reg_val.bf.ip_addr; - return ret; -} - -sw_error_t -qca808x_ptp_rx_filt_ipv6_da4_reg_ip_addr_set( - a_uint32_t dev_id, a_uint32_t phy_id, - a_uint32_t value) -{ - union ptp_rx_filt_ipv6_da4_reg_u reg_val; - sw_error_t ret = SW_OK; - - ret = qca808x_ptp_rx_filt_ipv6_da4_reg_get(dev_id, phy_id, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.ip_addr = value; - ret = qca808x_ptp_rx_filt_ipv6_da4_reg_set(dev_id, phy_id, ®_val); - return ret; -} - -sw_error_t -qca808x_ptp_rx_filt_ipv6_da5_reg_ip_addr_get( - a_uint32_t dev_id, a_uint32_t phy_id, - a_uint32_t *value) -{ - union ptp_rx_filt_ipv6_da5_reg_u reg_val; - sw_error_t ret = SW_OK; - - ret = qca808x_ptp_rx_filt_ipv6_da5_reg_get(dev_id, phy_id, ®_val); - *value = reg_val.bf.ip_addr; - return ret; -} - -sw_error_t -qca808x_ptp_rx_filt_ipv6_da5_reg_ip_addr_set( - a_uint32_t dev_id, a_uint32_t phy_id, - a_uint32_t value) -{ - union ptp_rx_filt_ipv6_da5_reg_u reg_val; - sw_error_t ret = SW_OK; - - ret = qca808x_ptp_rx_filt_ipv6_da5_reg_get(dev_id, phy_id, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.ip_addr = value; - ret = qca808x_ptp_rx_filt_ipv6_da5_reg_set(dev_id, phy_id, ®_val); - return ret; -} - -sw_error_t -qca808x_ptp_rx_filt_ipv6_da6_reg_ip_addr_get( - a_uint32_t dev_id, a_uint32_t phy_id, - a_uint32_t *value) -{ - union ptp_rx_filt_ipv6_da6_reg_u reg_val; - sw_error_t ret = SW_OK; - - ret = qca808x_ptp_rx_filt_ipv6_da6_reg_get(dev_id, phy_id, ®_val); - *value = reg_val.bf.ip_addr; - return ret; -} - -sw_error_t -qca808x_ptp_rx_filt_ipv6_da6_reg_ip_addr_set( - a_uint32_t dev_id, a_uint32_t phy_id, - a_uint32_t value) -{ - union ptp_rx_filt_ipv6_da6_reg_u reg_val; - sw_error_t ret = SW_OK; - - ret = qca808x_ptp_rx_filt_ipv6_da6_reg_get(dev_id, phy_id, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.ip_addr = value; - ret = qca808x_ptp_rx_filt_ipv6_da6_reg_set(dev_id, phy_id, ®_val); - return ret; -} - -sw_error_t -qca808x_ptp_rx_filt_ipv6_da7_reg_ip_addr_get( - a_uint32_t dev_id, a_uint32_t phy_id, - a_uint32_t *value) -{ - union ptp_rx_filt_ipv6_da7_reg_u reg_val; - sw_error_t ret = SW_OK; - - ret = qca808x_ptp_rx_filt_ipv6_da7_reg_get(dev_id, phy_id, ®_val); - *value = reg_val.bf.ip_addr; - return ret; -} - -sw_error_t -qca808x_ptp_rx_filt_ipv6_da7_reg_ip_addr_set( - a_uint32_t dev_id, a_uint32_t phy_id, - a_uint32_t value) -{ - union ptp_rx_filt_ipv6_da7_reg_u reg_val; - sw_error_t ret = SW_OK; - - ret = qca808x_ptp_rx_filt_ipv6_da7_reg_get(dev_id, phy_id, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.ip_addr = value; - ret = qca808x_ptp_rx_filt_ipv6_da7_reg_set(dev_id, phy_id, ®_val); - return ret; -} - -sw_error_t -qca808x_ptp_rx_filt_mac_lengthtype_reg_length_type_get( - a_uint32_t dev_id, a_uint32_t phy_id, - a_uint32_t *value) -{ - union ptp_rx_filt_mac_lengthtype_reg_u reg_val; - sw_error_t ret = SW_OK; - - ret = qca808x_ptp_rx_filt_mac_lengthtype_reg_get(dev_id, phy_id, ®_val); - *value = reg_val.bf.length_type; - return ret; -} - -sw_error_t -qca808x_ptp_rx_filt_mac_lengthtype_reg_length_type_set( - a_uint32_t dev_id, a_uint32_t phy_id, - a_uint32_t value) -{ - union ptp_rx_filt_mac_lengthtype_reg_u reg_val; - sw_error_t ret = SW_OK; - - ret = qca808x_ptp_rx_filt_mac_lengthtype_reg_get(dev_id, phy_id, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.length_type = value; - ret = qca808x_ptp_rx_filt_mac_lengthtype_reg_set(dev_id, phy_id, ®_val); - return ret; -} - -sw_error_t -qca808x_ptp_rx_filt_layer4_protocol_reg_l4_protocol_get( - a_uint32_t dev_id, a_uint32_t phy_id, - a_uint32_t *value) -{ - union ptp_rx_filt_layer4_protocol_reg_u reg_val; - sw_error_t ret = SW_OK; - - ret = qca808x_ptp_rx_filt_layer4_protocol_reg_get(dev_id, phy_id, ®_val); - *value = reg_val.bf.l4_protocol; - return ret; -} - -sw_error_t -qca808x_ptp_rx_filt_layer4_protocol_reg_l4_protocol_set( - a_uint32_t dev_id, a_uint32_t phy_id, - a_uint32_t value) -{ - union ptp_rx_filt_layer4_protocol_reg_u reg_val; - sw_error_t ret = SW_OK; - - ret = qca808x_ptp_rx_filt_layer4_protocol_reg_get(dev_id, phy_id, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.l4_protocol = value; - ret = qca808x_ptp_rx_filt_layer4_protocol_reg_set(dev_id, phy_id, ®_val); - return ret; -} - -sw_error_t -qca808x_ptp_rx_filt_udp_port_reg_udp_port_get( - a_uint32_t dev_id, a_uint32_t phy_id, - a_uint32_t *value) -{ - union ptp_rx_filt_udp_port_reg_u reg_val; - sw_error_t ret = SW_OK; - - ret = qca808x_ptp_rx_filt_udp_port_reg_get(dev_id, phy_id, ®_val); - *value = reg_val.bf.udp_port; - return ret; -} - -sw_error_t -qca808x_ptp_rx_filt_udp_port_reg_udp_port_set( - a_uint32_t dev_id, a_uint32_t phy_id, - a_uint32_t value) -{ - union ptp_rx_filt_udp_port_reg_u reg_val; - sw_error_t ret = SW_OK; - - ret = qca808x_ptp_rx_filt_udp_port_reg_get(dev_id, phy_id, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.udp_port = value; - ret = qca808x_ptp_rx_filt_udp_port_reg_set(dev_id, phy_id, ®_val); - return ret; -} - -sw_error_t -qca808x_ptp_rx_com_ts_status_reg_mac_ptp_pdelay_addr_get( - a_uint32_t dev_id, a_uint32_t phy_id, - a_uint32_t *value) -{ - union ptp_rx_com_ts_status_reg_u reg_val; - sw_error_t ret = SW_OK; - - ret = qca808x_ptp_rx_com_ts_status_reg_get(dev_id, phy_id, ®_val); - *value = reg_val.bf.mac_ptp_pdelay_addr; - return ret; -} - -sw_error_t -qca808x_ptp_rx_com_ts_status_reg_mac_ptp_pdelay_addr_set( - a_uint32_t dev_id, a_uint32_t phy_id, - a_uint32_t value) -{ - union ptp_rx_com_ts_status_reg_u reg_val; - sw_error_t ret = SW_OK; - - ret = qca808x_ptp_rx_com_ts_status_reg_get(dev_id, phy_id, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.mac_ptp_pdelay_addr = value; - ret = qca808x_ptp_rx_com_ts_status_reg_set(dev_id, phy_id, ®_val); - return ret; -} - -sw_error_t -qca808x_ptp_rx_com_ts_status_reg_mac_da_get( - a_uint32_t dev_id, a_uint32_t phy_id, - a_uint32_t *value) -{ - union ptp_rx_com_ts_status_reg_u reg_val; - sw_error_t ret = SW_OK; - - ret = qca808x_ptp_rx_com_ts_status_reg_get(dev_id, phy_id, ®_val); - *value = reg_val.bf.mac_da; - return ret; -} - -sw_error_t -qca808x_ptp_rx_com_ts_status_reg_mac_da_set( - a_uint32_t dev_id, a_uint32_t phy_id, - a_uint32_t value) -{ - union ptp_rx_com_ts_status_reg_u reg_val; - sw_error_t ret = SW_OK; - - ret = qca808x_ptp_rx_com_ts_status_reg_get(dev_id, phy_id, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.mac_da = value; - ret = qca808x_ptp_rx_com_ts_status_reg_set(dev_id, phy_id, ®_val); - return ret; -} - -sw_error_t -qca808x_ptp_rx_com_ts_status_reg_ipv4_ptp_pdelay_addr_get( - a_uint32_t dev_id, a_uint32_t phy_id, - a_uint32_t *value) -{ - union ptp_rx_com_ts_status_reg_u reg_val; - sw_error_t ret = SW_OK; - - ret = qca808x_ptp_rx_com_ts_status_reg_get(dev_id, phy_id, ®_val); - *value = reg_val.bf.ipv4_ptp_pdelay_addr; - return ret; -} - -sw_error_t -qca808x_ptp_rx_com_ts_status_reg_ipv4_ptp_pdelay_addr_set( - a_uint32_t dev_id, a_uint32_t phy_id, - a_uint32_t value) -{ - union ptp_rx_com_ts_status_reg_u reg_val; - sw_error_t ret = SW_OK; - - ret = qca808x_ptp_rx_com_ts_status_reg_get(dev_id, phy_id, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.ipv4_ptp_pdelay_addr = value; - ret = qca808x_ptp_rx_com_ts_status_reg_set(dev_id, phy_id, ®_val); - return ret; -} - -sw_error_t -qca808x_ptp_rx_com_ts_status_reg_mac_lengthtype_get( - a_uint32_t dev_id, a_uint32_t phy_id, - a_uint32_t *value) -{ - union ptp_rx_com_ts_status_reg_u reg_val; - sw_error_t ret = SW_OK; - - ret = qca808x_ptp_rx_com_ts_status_reg_get(dev_id, phy_id, ®_val); - *value = reg_val.bf.mac_lengthtype; - return ret; -} - -sw_error_t -qca808x_ptp_rx_com_ts_status_reg_mac_lengthtype_set( - a_uint32_t dev_id, a_uint32_t phy_id, - a_uint32_t value) -{ - union ptp_rx_com_ts_status_reg_u reg_val; - sw_error_t ret = SW_OK; - - ret = qca808x_ptp_rx_com_ts_status_reg_get(dev_id, phy_id, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.mac_lengthtype = value; - ret = qca808x_ptp_rx_com_ts_status_reg_set(dev_id, phy_id, ®_val); - return ret; -} - -sw_error_t -qca808x_ptp_rx_com_ts_status_reg_udp_dport_get( - a_uint32_t dev_id, a_uint32_t phy_id, - a_uint32_t *value) -{ - union ptp_rx_com_ts_status_reg_u reg_val; - sw_error_t ret = SW_OK; - - ret = qca808x_ptp_rx_com_ts_status_reg_get(dev_id, phy_id, ®_val); - *value = reg_val.bf.udp_dport; - return ret; -} - -sw_error_t -qca808x_ptp_rx_com_ts_status_reg_udp_dport_set( - a_uint32_t dev_id, a_uint32_t phy_id, - a_uint32_t value) -{ - union ptp_rx_com_ts_status_reg_u reg_val; - sw_error_t ret = SW_OK; - - ret = qca808x_ptp_rx_com_ts_status_reg_get(dev_id, phy_id, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.udp_dport = value; - ret = qca808x_ptp_rx_com_ts_status_reg_set(dev_id, phy_id, ®_val); - return ret; -} - -sw_error_t -qca808x_ptp_rx_com_ts_status_reg_ipv4_layer4_protocol_get( - a_uint32_t dev_id, a_uint32_t phy_id, - a_uint32_t *value) -{ - union ptp_rx_com_ts_status_reg_u reg_val; - sw_error_t ret = SW_OK; - - ret = qca808x_ptp_rx_com_ts_status_reg_get(dev_id, phy_id, ®_val); - *value = reg_val.bf.ipv4_layer4_protocol; - return ret; -} - -sw_error_t -qca808x_ptp_rx_com_ts_status_reg_ipv4_layer4_protocol_set( - a_uint32_t dev_id, a_uint32_t phy_id, - a_uint32_t value) -{ - union ptp_rx_com_ts_status_reg_u reg_val; - sw_error_t ret = SW_OK; - - ret = qca808x_ptp_rx_com_ts_status_reg_get(dev_id, phy_id, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.ipv4_layer4_protocol = value; - ret = qca808x_ptp_rx_com_ts_status_reg_set(dev_id, phy_id, ®_val); - return ret; -} - -sw_error_t -qca808x_ptp_rx_com_ts_status_reg_udp_ptp_event_dport_get( - a_uint32_t dev_id, a_uint32_t phy_id, - a_uint32_t *value) -{ - union ptp_rx_com_ts_status_reg_u reg_val; - sw_error_t ret = SW_OK; - - ret = qca808x_ptp_rx_com_ts_status_reg_get(dev_id, phy_id, ®_val); - *value = reg_val.bf.udp_ptp_event_dport; - return ret; -} - -sw_error_t -qca808x_ptp_rx_com_ts_status_reg_udp_ptp_event_dport_set( - a_uint32_t dev_id, a_uint32_t phy_id, - a_uint32_t value) -{ - union ptp_rx_com_ts_status_reg_u reg_val; - sw_error_t ret = SW_OK; - - ret = qca808x_ptp_rx_com_ts_status_reg_get(dev_id, phy_id, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.udp_ptp_event_dport = value; - ret = qca808x_ptp_rx_com_ts_status_reg_set(dev_id, phy_id, ®_val); - return ret; -} - -sw_error_t -qca808x_ptp_rx_com_ts_status_reg_ipv6_da_get( - a_uint32_t dev_id, a_uint32_t phy_id, - a_uint32_t *value) -{ - union ptp_rx_com_ts_status_reg_u reg_val; - sw_error_t ret = SW_OK; - - ret = qca808x_ptp_rx_com_ts_status_reg_get(dev_id, phy_id, ®_val); - *value = reg_val.bf.ipv6_da; - return ret; -} - -sw_error_t -qca808x_ptp_rx_com_ts_status_reg_ipv6_da_set( - a_uint32_t dev_id, a_uint32_t phy_id, - a_uint32_t value) -{ - union ptp_rx_com_ts_status_reg_u reg_val; - sw_error_t ret = SW_OK; - - ret = qca808x_ptp_rx_com_ts_status_reg_get(dev_id, phy_id, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.ipv6_da = value; - ret = qca808x_ptp_rx_com_ts_status_reg_set(dev_id, phy_id, ®_val); - return ret; -} - -sw_error_t -qca808x_ptp_rx_com_ts_status_reg_ipv4_ptp_prim_addr_get( - a_uint32_t dev_id, a_uint32_t phy_id, - a_uint32_t *value) -{ - union ptp_rx_com_ts_status_reg_u reg_val; - sw_error_t ret = SW_OK; - - ret = qca808x_ptp_rx_com_ts_status_reg_get(dev_id, phy_id, ®_val); - *value = reg_val.bf.ipv4_ptp_prim_addr; - return ret; -} - -sw_error_t -qca808x_ptp_rx_com_ts_status_reg_ipv4_ptp_prim_addr_set( - a_uint32_t dev_id, a_uint32_t phy_id, - a_uint32_t value) -{ - union ptp_rx_com_ts_status_reg_u reg_val; - sw_error_t ret = SW_OK; - - ret = qca808x_ptp_rx_com_ts_status_reg_get(dev_id, phy_id, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.ipv4_ptp_prim_addr = value; - ret = qca808x_ptp_rx_com_ts_status_reg_set(dev_id, phy_id, ®_val); - return ret; -} - -sw_error_t -qca808x_ptp_rx_com_ts_status_reg_ipv4_da_get( - a_uint32_t dev_id, a_uint32_t phy_id, - a_uint32_t *value) -{ - union ptp_rx_com_ts_status_reg_u reg_val; - sw_error_t ret = SW_OK; - - ret = qca808x_ptp_rx_com_ts_status_reg_get(dev_id, phy_id, ®_val); - *value = reg_val.bf.ipv4_da; - return ret; -} - -sw_error_t -qca808x_ptp_rx_com_ts_status_reg_ipv4_da_set( - a_uint32_t dev_id, a_uint32_t phy_id, - a_uint32_t value) -{ - union ptp_rx_com_ts_status_reg_u reg_val; - sw_error_t ret = SW_OK; - - ret = qca808x_ptp_rx_com_ts_status_reg_get(dev_id, phy_id, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.ipv4_da = value; - ret = qca808x_ptp_rx_com_ts_status_reg_set(dev_id, phy_id, ®_val); - return ret; -} - -sw_error_t -qca808x_ptp_rx_com_ts_status_reg_ipv6_ptp_pdelay_addr_get( - a_uint32_t dev_id, a_uint32_t phy_id, - a_uint32_t *value) -{ - union ptp_rx_com_ts_status_reg_u reg_val; - sw_error_t ret = SW_OK; - - ret = qca808x_ptp_rx_com_ts_status_reg_get(dev_id, phy_id, ®_val); - *value = reg_val.bf.ipv6_ptp_pdelay_addr; - return ret; -} - -sw_error_t -qca808x_ptp_rx_com_ts_status_reg_ipv6_ptp_pdelay_addr_set( - a_uint32_t dev_id, a_uint32_t phy_id, - a_uint32_t value) -{ - union ptp_rx_com_ts_status_reg_u reg_val; - sw_error_t ret = SW_OK; - - ret = qca808x_ptp_rx_com_ts_status_reg_get(dev_id, phy_id, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.ipv6_ptp_pdelay_addr = value; - ret = qca808x_ptp_rx_com_ts_status_reg_set(dev_id, phy_id, ®_val); - return ret; -} - -sw_error_t -qca808x_ptp_rx_com_ts_status_reg_ipv6_ptp_prim_addr_get( - a_uint32_t dev_id, a_uint32_t phy_id, - a_uint32_t *value) -{ - union ptp_rx_com_ts_status_reg_u reg_val; - sw_error_t ret = SW_OK; - - ret = qca808x_ptp_rx_com_ts_status_reg_get(dev_id, phy_id, ®_val); - *value = reg_val.bf.ipv6_ptp_prim_addr; - return ret; -} - -sw_error_t -qca808x_ptp_rx_com_ts_status_reg_ipv6_ptp_prim_addr_set( - a_uint32_t dev_id, a_uint32_t phy_id, - a_uint32_t value) -{ - union ptp_rx_com_ts_status_reg_u reg_val; - sw_error_t ret = SW_OK; - - ret = qca808x_ptp_rx_com_ts_status_reg_get(dev_id, phy_id, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.ipv6_ptp_prim_addr = value; - ret = qca808x_ptp_rx_com_ts_status_reg_set(dev_id, phy_id, ®_val); - return ret; -} - -sw_error_t -qca808x_ptp_rx_com_ts_status_reg_ipv6_next_header_get( - a_uint32_t dev_id, a_uint32_t phy_id, - a_uint32_t *value) -{ - union ptp_rx_com_ts_status_reg_u reg_val; - sw_error_t ret = SW_OK; - - ret = qca808x_ptp_rx_com_ts_status_reg_get(dev_id, phy_id, ®_val); - *value = reg_val.bf.ipv6_next_header; - return ret; -} - -sw_error_t -qca808x_ptp_rx_com_ts_status_reg_ipv6_next_header_set( - a_uint32_t dev_id, a_uint32_t phy_id, - a_uint32_t value) -{ - union ptp_rx_com_ts_status_reg_u reg_val; - sw_error_t ret = SW_OK; - - ret = qca808x_ptp_rx_com_ts_status_reg_get(dev_id, phy_id, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.ipv6_next_header = value; - ret = qca808x_ptp_rx_com_ts_status_reg_set(dev_id, phy_id, ®_val); - return ret; -} - -sw_error_t -qca808x_ptp_rx_com_ts_status_reg_y1731_mach_get( - a_uint32_t dev_id, a_uint32_t phy_id, - a_uint32_t *value) -{ - union ptp_rx_com_ts_status_reg_u reg_val; - sw_error_t ret = SW_OK; - - ret = qca808x_ptp_rx_com_ts_status_reg_get(dev_id, phy_id, ®_val); - *value = reg_val.bf.y1731_mach; - return ret; -} - -sw_error_t -qca808x_ptp_rx_com_ts_status_reg_y1731_mach_set( - a_uint32_t dev_id, a_uint32_t phy_id, - a_uint32_t value) -{ - union ptp_rx_com_ts_status_reg_u reg_val; - sw_error_t ret = SW_OK; - - ret = qca808x_ptp_rx_com_ts_status_reg_get(dev_id, phy_id, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.y1731_mach = value; - ret = qca808x_ptp_rx_com_ts_status_reg_set(dev_id, phy_id, ®_val); - return ret; -} - -sw_error_t -qca808x_ptp_rx_com_ts_status_reg_mac_ptp_prim_addr_get( - a_uint32_t dev_id, a_uint32_t phy_id, - a_uint32_t *value) -{ - union ptp_rx_com_ts_status_reg_u reg_val; - sw_error_t ret = SW_OK; - - ret = qca808x_ptp_rx_com_ts_status_reg_get(dev_id, phy_id, ®_val); - *value = reg_val.bf.mac_ptp_prim_addr; - return ret; -} - -sw_error_t -qca808x_ptp_rx_com_ts_status_reg_mac_ptp_prim_addr_set( - a_uint32_t dev_id, a_uint32_t phy_id, - a_uint32_t value) -{ - union ptp_rx_com_ts_status_reg_u reg_val; - sw_error_t ret = SW_OK; - - ret = qca808x_ptp_rx_com_ts_status_reg_get(dev_id, phy_id, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.mac_ptp_prim_addr = value; - ret = qca808x_ptp_rx_com_ts_status_reg_set(dev_id, phy_id, ®_val); - return ret; -} - -sw_error_t -qca808x_ptp_rx_com_timestamp0_reg_com_ts_get( - a_uint32_t dev_id, a_uint32_t phy_id, - a_uint32_t *value) -{ - union ptp_rx_com_timestamp0_reg_u reg_val; - sw_error_t ret = SW_OK; - - ret = qca808x_ptp_rx_com_timestamp0_reg_get(dev_id, phy_id, ®_val); - *value = reg_val.bf.com_ts; - return ret; -} - -sw_error_t -qca808x_ptp_rx_com_timestamp0_reg_com_ts_set( - a_uint32_t dev_id, a_uint32_t phy_id, - a_uint32_t value) -{ - union ptp_rx_com_timestamp0_reg_u reg_val; - sw_error_t ret = SW_OK; - - ret = qca808x_ptp_rx_com_timestamp0_reg_get(dev_id, phy_id, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.com_ts = value; - ret = qca808x_ptp_rx_com_timestamp0_reg_set(dev_id, phy_id, ®_val); - return ret; -} - -sw_error_t -qca808x_ptp_rx_com_timestamp1_reg_com_ts_get( - a_uint32_t dev_id, a_uint32_t phy_id, - a_uint32_t *value) -{ - union ptp_rx_com_timestamp1_reg_u reg_val; - sw_error_t ret = SW_OK; - - ret = qca808x_ptp_rx_com_timestamp1_reg_get(dev_id, phy_id, ®_val); - *value = reg_val.bf.com_ts; - return ret; -} - -sw_error_t -qca808x_ptp_rx_com_timestamp1_reg_com_ts_set( - a_uint32_t dev_id, a_uint32_t phy_id, - a_uint32_t value) -{ - union ptp_rx_com_timestamp1_reg_u reg_val; - sw_error_t ret = SW_OK; - - ret = qca808x_ptp_rx_com_timestamp1_reg_get(dev_id, phy_id, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.com_ts = value; - ret = qca808x_ptp_rx_com_timestamp1_reg_set(dev_id, phy_id, ®_val); - return ret; -} - -sw_error_t -qca808x_ptp_rx_com_timestamp2_reg_com_ts_get( - a_uint32_t dev_id, a_uint32_t phy_id, - a_uint32_t *value) -{ - union ptp_rx_com_timestamp2_reg_u reg_val; - sw_error_t ret = SW_OK; - - ret = qca808x_ptp_rx_com_timestamp2_reg_get(dev_id, phy_id, ®_val); - *value = reg_val.bf.com_ts; - return ret; -} - -sw_error_t -qca808x_ptp_rx_com_timestamp2_reg_com_ts_set( - a_uint32_t dev_id, a_uint32_t phy_id, - a_uint32_t value) -{ - union ptp_rx_com_timestamp2_reg_u reg_val; - sw_error_t ret = SW_OK; - - ret = qca808x_ptp_rx_com_timestamp2_reg_get(dev_id, phy_id, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.com_ts = value; - ret = qca808x_ptp_rx_com_timestamp2_reg_set(dev_id, phy_id, ®_val); - return ret; -} - -sw_error_t -qca808x_ptp_rx_com_timestamp3_reg_com_ts_get( - a_uint32_t dev_id, a_uint32_t phy_id, - a_uint32_t *value) -{ - union ptp_rx_com_timestamp3_reg_u reg_val; - sw_error_t ret = SW_OK; - - ret = qca808x_ptp_rx_com_timestamp3_reg_get(dev_id, phy_id, ®_val); - *value = reg_val.bf.com_ts; - return ret; -} - -sw_error_t -qca808x_ptp_rx_com_timestamp3_reg_com_ts_set( - a_uint32_t dev_id, a_uint32_t phy_id, - a_uint32_t value) -{ - union ptp_rx_com_timestamp3_reg_u reg_val; - sw_error_t ret = SW_OK; - - ret = qca808x_ptp_rx_com_timestamp3_reg_get(dev_id, phy_id, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.com_ts = value; - ret = qca808x_ptp_rx_com_timestamp3_reg_set(dev_id, phy_id, ®_val); - return ret; -} - -sw_error_t -qca808x_ptp_rx_com_timestamp4_reg_com_ts_get( - a_uint32_t dev_id, a_uint32_t phy_id, - a_uint32_t *value) -{ - union ptp_rx_com_timestamp4_reg_u reg_val; - sw_error_t ret = SW_OK; - - ret = qca808x_ptp_rx_com_timestamp4_reg_get(dev_id, phy_id, ®_val); - *value = reg_val.bf.com_ts; - return ret; -} - -sw_error_t -qca808x_ptp_rx_com_timestamp4_reg_com_ts_set( - a_uint32_t dev_id, a_uint32_t phy_id, - a_uint32_t value) -{ - union ptp_rx_com_timestamp4_reg_u reg_val; - sw_error_t ret = SW_OK; - - ret = qca808x_ptp_rx_com_timestamp4_reg_get(dev_id, phy_id, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.com_ts = value; - ret = qca808x_ptp_rx_com_timestamp4_reg_set(dev_id, phy_id, ®_val); - return ret; -} - -sw_error_t -qca808x_ptp_rx_com_frac_nano_reg_frac_nano_get( - a_uint32_t dev_id, a_uint32_t phy_id, - a_uint32_t *value) -{ - union ptp_rx_com_frac_nano_reg_u reg_val; - sw_error_t ret = SW_OK; - - ret = qca808x_ptp_rx_com_frac_nano_reg_get(dev_id, phy_id, ®_val); - *value = reg_val.bf.frac_nano; - return ret; -} - -sw_error_t -qca808x_ptp_rx_com_frac_nano_reg_frac_nano_set( - a_uint32_t dev_id, a_uint32_t phy_id, - a_uint32_t value) -{ - union ptp_rx_com_frac_nano_reg_u reg_val; - sw_error_t ret = SW_OK; - - ret = qca808x_ptp_rx_com_frac_nano_reg_get(dev_id, phy_id, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.frac_nano = value; - ret = qca808x_ptp_rx_com_frac_nano_reg_set(dev_id, phy_id, ®_val); - return ret; -} - -sw_error_t -qca808x_ptp_rx_com_timestamp_pre0_reg_com_ts_pre_get( - a_uint32_t dev_id, a_uint32_t phy_id, - a_uint32_t *value) -{ - union ptp_rx_com_timestamp_pre0_reg_u reg_val; - sw_error_t ret = SW_OK; - - ret = qca808x_ptp_rx_com_timestamp_pre0_reg_get(dev_id, phy_id, ®_val); - *value = reg_val.bf.com_ts_pre; - return ret; -} - -sw_error_t -qca808x_ptp_rx_com_timestamp_pre0_reg_com_ts_pre_set( - a_uint32_t dev_id, a_uint32_t phy_id, - a_uint32_t value) -{ - union ptp_rx_com_timestamp_pre0_reg_u reg_val; - sw_error_t ret = SW_OK; - - ret = qca808x_ptp_rx_com_timestamp_pre0_reg_get(dev_id, phy_id, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.com_ts_pre = value; - ret = qca808x_ptp_rx_com_timestamp_pre0_reg_set(dev_id, phy_id, ®_val); - return ret; -} - -sw_error_t -qca808x_ptp_rx_com_timestamp_pre1_reg_com_ts_pre_get( - a_uint32_t dev_id, a_uint32_t phy_id, - a_uint32_t *value) -{ - union ptp_rx_com_timestamp_pre1_reg_u reg_val; - sw_error_t ret = SW_OK; - - ret = qca808x_ptp_rx_com_timestamp_pre1_reg_get(dev_id, phy_id, ®_val); - *value = reg_val.bf.com_ts_pre; - return ret; -} - -sw_error_t -qca808x_ptp_rx_com_timestamp_pre1_reg_com_ts_pre_set( - a_uint32_t dev_id, a_uint32_t phy_id, - a_uint32_t value) -{ - union ptp_rx_com_timestamp_pre1_reg_u reg_val; - sw_error_t ret = SW_OK; - - ret = qca808x_ptp_rx_com_timestamp_pre1_reg_get(dev_id, phy_id, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.com_ts_pre = value; - ret = qca808x_ptp_rx_com_timestamp_pre1_reg_set(dev_id, phy_id, ®_val); - return ret; -} - -sw_error_t -qca808x_ptp_rx_com_timestamp_pre2_reg_com_ts_pre_get( - a_uint32_t dev_id, a_uint32_t phy_id, - a_uint32_t *value) -{ - union ptp_rx_com_timestamp_pre2_reg_u reg_val; - sw_error_t ret = SW_OK; - - ret = qca808x_ptp_rx_com_timestamp_pre2_reg_get(dev_id, phy_id, ®_val); - *value = reg_val.bf.com_ts_pre; - return ret; -} - -sw_error_t -qca808x_ptp_rx_com_timestamp_pre2_reg_com_ts_pre_set( - a_uint32_t dev_id, a_uint32_t phy_id, - a_uint32_t value) -{ - union ptp_rx_com_timestamp_pre2_reg_u reg_val; - sw_error_t ret = SW_OK; - - ret = qca808x_ptp_rx_com_timestamp_pre2_reg_get(dev_id, phy_id, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.com_ts_pre = value; - ret = qca808x_ptp_rx_com_timestamp_pre2_reg_set(dev_id, phy_id, ®_val); - return ret; -} - -sw_error_t -qca808x_ptp_rx_com_timestamp_pre3_reg_com_ts_pre_get( - a_uint32_t dev_id, a_uint32_t phy_id, - a_uint32_t *value) -{ - union ptp_rx_com_timestamp_pre3_reg_u reg_val; - sw_error_t ret = SW_OK; - - ret = qca808x_ptp_rx_com_timestamp_pre3_reg_get(dev_id, phy_id, ®_val); - *value = reg_val.bf.com_ts_pre; - return ret; -} - -sw_error_t -qca808x_ptp_rx_com_timestamp_pre3_reg_com_ts_pre_set( - a_uint32_t dev_id, a_uint32_t phy_id, - a_uint32_t value) -{ - union ptp_rx_com_timestamp_pre3_reg_u reg_val; - sw_error_t ret = SW_OK; - - ret = qca808x_ptp_rx_com_timestamp_pre3_reg_get(dev_id, phy_id, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.com_ts_pre = value; - ret = qca808x_ptp_rx_com_timestamp_pre3_reg_set(dev_id, phy_id, ®_val); - return ret; -} - -sw_error_t -qca808x_ptp_rx_com_timestamp_pre4_reg_com_ts_pre_get( - a_uint32_t dev_id, a_uint32_t phy_id, - a_uint32_t *value) -{ - union ptp_rx_com_timestamp_pre4_reg_u reg_val; - sw_error_t ret = SW_OK; - - ret = qca808x_ptp_rx_com_timestamp_pre4_reg_get(dev_id, phy_id, ®_val); - *value = reg_val.bf.com_ts_pre; - return ret; -} - -sw_error_t -qca808x_ptp_rx_com_timestamp_pre4_reg_com_ts_pre_set( - a_uint32_t dev_id, a_uint32_t phy_id, - a_uint32_t value) -{ - union ptp_rx_com_timestamp_pre4_reg_u reg_val; - sw_error_t ret = SW_OK; - - ret = qca808x_ptp_rx_com_timestamp_pre4_reg_get(dev_id, phy_id, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.com_ts_pre = value; - ret = qca808x_ptp_rx_com_timestamp_pre4_reg_set(dev_id, phy_id, ®_val); - return ret; -} - -sw_error_t -qca808x_ptp_rx_com_frac_nano_pre_reg_frac_nano_pre_get( - a_uint32_t dev_id, a_uint32_t phy_id, - a_uint32_t *value) -{ - union ptp_rx_com_frac_nano_pre_reg_u reg_val; - sw_error_t ret = SW_OK; - - ret = qca808x_ptp_rx_com_frac_nano_pre_reg_get(dev_id, phy_id, ®_val); - *value = reg_val.bf.frac_nano_pre; - return ret; -} - -sw_error_t -qca808x_ptp_rx_com_frac_nano_pre_reg_frac_nano_pre_set( - a_uint32_t dev_id, a_uint32_t phy_id, - a_uint32_t value) -{ - union ptp_rx_com_frac_nano_pre_reg_u reg_val; - sw_error_t ret = SW_OK; - - ret = qca808x_ptp_rx_com_frac_nano_pre_reg_get(dev_id, phy_id, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.frac_nano_pre = value; - ret = qca808x_ptp_rx_com_frac_nano_pre_reg_set(dev_id, phy_id, ®_val); - return ret; -} - -sw_error_t -qca808x_ptp_rx_y1731_identify_reg_identify_get( - a_uint32_t dev_id, a_uint32_t phy_id, - a_uint32_t *value) -{ - union ptp_rx_y1731_identify_reg_u reg_val; - sw_error_t ret = SW_OK; - - ret = qca808x_ptp_rx_y1731_identify_reg_get(dev_id, phy_id, ®_val); - *value = reg_val.bf.identify; - return ret; -} - -sw_error_t -qca808x_ptp_rx_y1731_identify_reg_identify_set( - a_uint32_t dev_id, a_uint32_t phy_id, - a_uint32_t value) -{ - union ptp_rx_y1731_identify_reg_u reg_val; - sw_error_t ret = SW_OK; - - ret = qca808x_ptp_rx_y1731_identify_reg_get(dev_id, phy_id, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.identify = value; - ret = qca808x_ptp_rx_y1731_identify_reg_set(dev_id, phy_id, ®_val); - return ret; -} - -sw_error_t -qca808x_ptp_rx_y1731_identify_pre_reg_identify_pre_get( - a_uint32_t dev_id, a_uint32_t phy_id, - a_uint32_t *value) -{ - union ptp_rx_y1731_identify_pre_reg_u reg_val; - sw_error_t ret = SW_OK; - - ret = qca808x_ptp_rx_y1731_identify_pre_reg_get(dev_id, phy_id, ®_val); - *value = reg_val.bf.identify_pre; - return ret; -} - -sw_error_t -qca808x_ptp_rx_y1731_identify_pre_reg_identify_pre_set( - a_uint32_t dev_id, a_uint32_t phy_id, - a_uint32_t value) -{ - union ptp_rx_y1731_identify_pre_reg_u reg_val; - sw_error_t ret = SW_OK; - - ret = qca808x_ptp_rx_y1731_identify_pre_reg_get(dev_id, phy_id, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.identify_pre = value; - ret = qca808x_ptp_rx_y1731_identify_pre_reg_set(dev_id, phy_id, ®_val); - return ret; -} - -sw_error_t -qca808x_ptp_tx_com_ts_ctrl_reg_ipv4_da_en_get( - a_uint32_t dev_id, a_uint32_t phy_id, - a_uint32_t *value) -{ - union ptp_tx_com_ts_ctrl_reg_u reg_val; - sw_error_t ret = SW_OK; - - ret = qca808x_ptp_tx_com_ts_ctrl_reg_get(dev_id, phy_id, ®_val); - *value = reg_val.bf.ipv4_da_en; - return ret; -} - -sw_error_t -qca808x_ptp_tx_com_ts_ctrl_reg_ipv4_da_en_set( - a_uint32_t dev_id, a_uint32_t phy_id, - a_uint32_t value) -{ - union ptp_tx_com_ts_ctrl_reg_u reg_val; - sw_error_t ret = SW_OK; - - ret = qca808x_ptp_tx_com_ts_ctrl_reg_get(dev_id, phy_id, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.ipv4_da_en = value; - ret = qca808x_ptp_tx_com_ts_ctrl_reg_set(dev_id, phy_id, ®_val); - return ret; -} - -sw_error_t -qca808x_ptp_tx_com_ts_ctrl_reg_mac_lengthtype_en_get( - a_uint32_t dev_id, a_uint32_t phy_id, - a_uint32_t *value) -{ - union ptp_tx_com_ts_ctrl_reg_u reg_val; - sw_error_t ret = SW_OK; - - ret = qca808x_ptp_tx_com_ts_ctrl_reg_get(dev_id, phy_id, ®_val); - *value = reg_val.bf.mac_lengthtype_en; - return ret; -} - -sw_error_t -qca808x_ptp_tx_com_ts_ctrl_reg_mac_lengthtype_en_set( - a_uint32_t dev_id, a_uint32_t phy_id, - a_uint32_t value) -{ - union ptp_tx_com_ts_ctrl_reg_u reg_val; - sw_error_t ret = SW_OK; - - ret = qca808x_ptp_tx_com_ts_ctrl_reg_get(dev_id, phy_id, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.mac_lengthtype_en = value; - ret = qca808x_ptp_tx_com_ts_ctrl_reg_set(dev_id, phy_id, ®_val); - return ret; -} - -sw_error_t -qca808x_ptp_tx_com_ts_ctrl_reg_ipv6_da_en_get( - a_uint32_t dev_id, a_uint32_t phy_id, - a_uint32_t *value) -{ - union ptp_tx_com_ts_ctrl_reg_u reg_val; - sw_error_t ret = SW_OK; - - ret = qca808x_ptp_tx_com_ts_ctrl_reg_get(dev_id, phy_id, ®_val); - *value = reg_val.bf.ipv6_da_en; - return ret; -} - -sw_error_t -qca808x_ptp_tx_com_ts_ctrl_reg_ipv6_da_en_set( - a_uint32_t dev_id, a_uint32_t phy_id, - a_uint32_t value) -{ - union ptp_tx_com_ts_ctrl_reg_u reg_val; - sw_error_t ret = SW_OK; - - ret = qca808x_ptp_tx_com_ts_ctrl_reg_get(dev_id, phy_id, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.ipv6_da_en = value; - ret = qca808x_ptp_tx_com_ts_ctrl_reg_set(dev_id, phy_id, ®_val); - return ret; -} - -sw_error_t -qca808x_ptp_tx_com_ts_ctrl_reg_pw_mac_en_get( - a_uint32_t dev_id, a_uint32_t phy_id, - a_uint32_t *value) -{ - union ptp_tx_com_ts_ctrl_reg_u reg_val; - sw_error_t ret = SW_OK; - - ret = qca808x_ptp_tx_com_ts_ctrl_reg_get(dev_id, phy_id, ®_val); - *value = reg_val.bf.pw_mac_en; - return ret; -} - -sw_error_t -qca808x_ptp_tx_com_ts_ctrl_reg_pw_mac_en_set( - a_uint32_t dev_id, a_uint32_t phy_id, - a_uint32_t value) -{ - union ptp_tx_com_ts_ctrl_reg_u reg_val; - sw_error_t ret = SW_OK; - - ret = qca808x_ptp_tx_com_ts_ctrl_reg_get(dev_id, phy_id, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.pw_mac_en = value; - ret = qca808x_ptp_tx_com_ts_ctrl_reg_set(dev_id, phy_id, ®_val); - return ret; -} - -sw_error_t -qca808x_ptp_tx_com_ts_ctrl_reg_udp_ptp_event_filt_en_get( - a_uint32_t dev_id, a_uint32_t phy_id, - a_uint32_t *value) -{ - union ptp_tx_com_ts_ctrl_reg_u reg_val; - sw_error_t ret = SW_OK; - - ret = qca808x_ptp_tx_com_ts_ctrl_reg_get(dev_id, phy_id, ®_val); - *value = reg_val.bf.udp_ptp_event_filt_en; - return ret; -} - -sw_error_t -qca808x_ptp_tx_com_ts_ctrl_reg_udp_ptp_event_filt_en_set( - a_uint32_t dev_id, a_uint32_t phy_id, - a_uint32_t value) -{ - union ptp_tx_com_ts_ctrl_reg_u reg_val; - sw_error_t ret = SW_OK; - - ret = qca808x_ptp_tx_com_ts_ctrl_reg_get(dev_id, phy_id, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.udp_ptp_event_filt_en = value; - ret = qca808x_ptp_tx_com_ts_ctrl_reg_set(dev_id, phy_id, ®_val); - return ret; -} - -sw_error_t -qca808x_ptp_tx_com_ts_ctrl_reg_udp_dport_en_get( - a_uint32_t dev_id, a_uint32_t phy_id, - a_uint32_t *value) -{ - union ptp_tx_com_ts_ctrl_reg_u reg_val; - sw_error_t ret = SW_OK; - - ret = qca808x_ptp_tx_com_ts_ctrl_reg_get(dev_id, phy_id, ®_val); - *value = reg_val.bf.udp_dport_en; - return ret; -} - -sw_error_t -qca808x_ptp_tx_com_ts_ctrl_reg_udp_dport_en_set( - a_uint32_t dev_id, a_uint32_t phy_id, - a_uint32_t value) -{ - union ptp_tx_com_ts_ctrl_reg_u reg_val; - sw_error_t ret = SW_OK; - - ret = qca808x_ptp_tx_com_ts_ctrl_reg_get(dev_id, phy_id, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.udp_dport_en = value; - ret = qca808x_ptp_tx_com_ts_ctrl_reg_set(dev_id, phy_id, ®_val); - return ret; -} - -sw_error_t -qca808x_ptp_tx_com_ts_ctrl_reg_mac_ptp_filt_en_get( - a_uint32_t dev_id, a_uint32_t phy_id, - a_uint32_t *value) -{ - union ptp_tx_com_ts_ctrl_reg_u reg_val; - sw_error_t ret = SW_OK; - - ret = qca808x_ptp_tx_com_ts_ctrl_reg_get(dev_id, phy_id, ®_val); - *value = reg_val.bf.mac_ptp_filt_en; - return ret; -} - -sw_error_t -qca808x_ptp_tx_com_ts_ctrl_reg_mac_ptp_filt_en_set( - a_uint32_t dev_id, a_uint32_t phy_id, - a_uint32_t value) -{ - union ptp_tx_com_ts_ctrl_reg_u reg_val; - sw_error_t ret = SW_OK; - - ret = qca808x_ptp_tx_com_ts_ctrl_reg_get(dev_id, phy_id, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.mac_ptp_filt_en = value; - ret = qca808x_ptp_tx_com_ts_ctrl_reg_set(dev_id, phy_id, ®_val); - return ret; -} - -sw_error_t -qca808x_ptp_tx_com_ts_ctrl_reg_ipv6_next_header_en_get( - a_uint32_t dev_id, a_uint32_t phy_id, - a_uint32_t *value) -{ - union ptp_tx_com_ts_ctrl_reg_u reg_val; - sw_error_t ret = SW_OK; - - ret = qca808x_ptp_tx_com_ts_ctrl_reg_get(dev_id, phy_id, ®_val); - *value = reg_val.bf.ipv6_next_header_en; - return ret; -} - -sw_error_t -qca808x_ptp_tx_com_ts_ctrl_reg_ipv6_next_header_en_set( - a_uint32_t dev_id, a_uint32_t phy_id, - a_uint32_t value) -{ - union ptp_tx_com_ts_ctrl_reg_u reg_val; - sw_error_t ret = SW_OK; - - ret = qca808x_ptp_tx_com_ts_ctrl_reg_get(dev_id, phy_id, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.ipv6_next_header_en = value; - ret = qca808x_ptp_tx_com_ts_ctrl_reg_set(dev_id, phy_id, ®_val); - return ret; -} - -sw_error_t -qca808x_ptp_tx_com_ts_ctrl_reg_ipv4_layer4_protocol_en_get( - a_uint32_t dev_id, a_uint32_t phy_id, - a_uint32_t *value) -{ - union ptp_tx_com_ts_ctrl_reg_u reg_val; - sw_error_t ret = SW_OK; - - ret = qca808x_ptp_tx_com_ts_ctrl_reg_get(dev_id, phy_id, ®_val); - *value = reg_val.bf.ipv4_layer4_protocol_en; - return ret; -} - -sw_error_t -qca808x_ptp_tx_com_ts_ctrl_reg_ipv4_layer4_protocol_en_set( - a_uint32_t dev_id, a_uint32_t phy_id, - a_uint32_t value) -{ - union ptp_tx_com_ts_ctrl_reg_u reg_val; - sw_error_t ret = SW_OK; - - ret = qca808x_ptp_tx_com_ts_ctrl_reg_get(dev_id, phy_id, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.ipv4_layer4_protocol_en = value; - ret = qca808x_ptp_tx_com_ts_ctrl_reg_set(dev_id, phy_id, ®_val); - return ret; -} - -sw_error_t -qca808x_ptp_tx_com_ts_ctrl_reg_y1731_en_get( - a_uint32_t dev_id, a_uint32_t phy_id, - a_uint32_t *value) -{ - union ptp_tx_com_ts_ctrl_reg_u reg_val; - sw_error_t ret = SW_OK; - - ret = qca808x_ptp_tx_com_ts_ctrl_reg_get(dev_id, phy_id, ®_val); - *value = reg_val.bf.y1731_en; - return ret; -} - -sw_error_t -qca808x_ptp_tx_com_ts_ctrl_reg_y1731_en_set( - a_uint32_t dev_id, a_uint32_t phy_id, - a_uint32_t value) -{ - union ptp_tx_com_ts_ctrl_reg_u reg_val; - sw_error_t ret = SW_OK; - - ret = qca808x_ptp_tx_com_ts_ctrl_reg_get(dev_id, phy_id, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.y1731_en = value; - ret = qca808x_ptp_tx_com_ts_ctrl_reg_set(dev_id, phy_id, ®_val); - return ret; -} - -sw_error_t -qca808x_ptp_tx_com_ts_ctrl_reg_filt_en_get( - a_uint32_t dev_id, a_uint32_t phy_id, - a_uint32_t *value) -{ - union ptp_tx_com_ts_ctrl_reg_u reg_val; - sw_error_t ret = SW_OK; - - ret = qca808x_ptp_tx_com_ts_ctrl_reg_get(dev_id, phy_id, ®_val); - *value = reg_val.bf.filt_en; - return ret; -} - -sw_error_t -qca808x_ptp_tx_com_ts_ctrl_reg_filt_en_set( - a_uint32_t dev_id, a_uint32_t phy_id, - a_uint32_t value) -{ - union ptp_tx_com_ts_ctrl_reg_u reg_val; - sw_error_t ret = SW_OK; - - ret = qca808x_ptp_tx_com_ts_ctrl_reg_get(dev_id, phy_id, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.filt_en = value; - ret = qca808x_ptp_tx_com_ts_ctrl_reg_set(dev_id, phy_id, ®_val); - return ret; -} - -sw_error_t -qca808x_ptp_tx_com_ts_ctrl_reg_ipv6_ptp_filt_en_get( - a_uint32_t dev_id, a_uint32_t phy_id, - a_uint32_t *value) -{ - union ptp_tx_com_ts_ctrl_reg_u reg_val; - sw_error_t ret = SW_OK; - - ret = qca808x_ptp_tx_com_ts_ctrl_reg_get(dev_id, phy_id, ®_val); - *value = reg_val.bf.ipv6_ptp_filt_en; - return ret; -} - -sw_error_t -qca808x_ptp_tx_com_ts_ctrl_reg_ipv6_ptp_filt_en_set( - a_uint32_t dev_id, a_uint32_t phy_id, - a_uint32_t value) -{ - union ptp_tx_com_ts_ctrl_reg_u reg_val; - sw_error_t ret = SW_OK; - - ret = qca808x_ptp_tx_com_ts_ctrl_reg_get(dev_id, phy_id, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.ipv6_ptp_filt_en = value; - ret = qca808x_ptp_tx_com_ts_ctrl_reg_set(dev_id, phy_id, ®_val); - return ret; -} - -sw_error_t -qca808x_ptp_tx_com_ts_ctrl_reg_ipv4_ptp_filt_en_get( - a_uint32_t dev_id, a_uint32_t phy_id, - a_uint32_t *value) -{ - union ptp_tx_com_ts_ctrl_reg_u reg_val; - sw_error_t ret = SW_OK; - - ret = qca808x_ptp_tx_com_ts_ctrl_reg_get(dev_id, phy_id, ®_val); - *value = reg_val.bf.ipv4_ptp_filt_en; - return ret; -} - -sw_error_t -qca808x_ptp_tx_com_ts_ctrl_reg_ipv4_ptp_filt_en_set( - a_uint32_t dev_id, a_uint32_t phy_id, - a_uint32_t value) -{ - union ptp_tx_com_ts_ctrl_reg_u reg_val; - sw_error_t ret = SW_OK; - - ret = qca808x_ptp_tx_com_ts_ctrl_reg_get(dev_id, phy_id, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.ipv4_ptp_filt_en = value; - ret = qca808x_ptp_tx_com_ts_ctrl_reg_set(dev_id, phy_id, ®_val); - return ret; -} - -sw_error_t -qca808x_ptp_tx_com_ts_ctrl_reg_y1731_insert_ts_en_get( - a_uint32_t dev_id, a_uint32_t phy_id, - a_uint32_t *value) -{ - union ptp_tx_com_ts_ctrl_reg_u reg_val; - sw_error_t ret = SW_OK; - - ret = qca808x_ptp_tx_com_ts_ctrl_reg_get(dev_id, phy_id, ®_val); - *value = reg_val.bf.y1731_insert_ts_en; - return ret; -} - -sw_error_t -qca808x_ptp_tx_com_ts_ctrl_reg_y1731_insert_ts_en_set( - a_uint32_t dev_id, a_uint32_t phy_id, - a_uint32_t value) -{ - union ptp_tx_com_ts_ctrl_reg_u reg_val; - sw_error_t ret = SW_OK; - - ret = qca808x_ptp_tx_com_ts_ctrl_reg_get(dev_id, phy_id, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.y1731_insert_ts_en = value; - ret = qca808x_ptp_tx_com_ts_ctrl_reg_set(dev_id, phy_id, ®_val); - return ret; -} - -sw_error_t -qca808x_ptp_tx_com_ts_ctrl_reg_mac_da_en_get( - a_uint32_t dev_id, a_uint32_t phy_id, - a_uint32_t *value) -{ - union ptp_tx_com_ts_ctrl_reg_u reg_val; - sw_error_t ret = SW_OK; - - ret = qca808x_ptp_tx_com_ts_ctrl_reg_get(dev_id, phy_id, ®_val); - *value = reg_val.bf.mac_da_en; - return ret; -} - -sw_error_t -qca808x_ptp_tx_com_ts_ctrl_reg_mac_da_en_set( - a_uint32_t dev_id, a_uint32_t phy_id, - a_uint32_t value) -{ - union ptp_tx_com_ts_ctrl_reg_u reg_val; - sw_error_t ret = SW_OK; - - ret = qca808x_ptp_tx_com_ts_ctrl_reg_get(dev_id, phy_id, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.mac_da_en = value; - ret = qca808x_ptp_tx_com_ts_ctrl_reg_set(dev_id, phy_id, ®_val); - return ret; -} - -sw_error_t -qca808x_ptp_tx_com_ts_ctrl_reg_y1731_sa_chk_en_get( - a_uint32_t dev_id, a_uint32_t phy_id, - a_uint32_t *value) -{ - union ptp_tx_com_ts_ctrl_reg_u reg_val; - sw_error_t ret = SW_OK; - - ret = qca808x_ptp_tx_com_ts_ctrl_reg_get(dev_id, phy_id, ®_val); - *value = reg_val.bf.y1731_sa_chk_en; - return ret; -} - -sw_error_t -qca808x_ptp_tx_com_ts_ctrl_reg_y1731_sa_chk_en_set( - a_uint32_t dev_id, a_uint32_t phy_id, - a_uint32_t value) -{ - union ptp_tx_com_ts_ctrl_reg_u reg_val; - sw_error_t ret = SW_OK; - - ret = qca808x_ptp_tx_com_ts_ctrl_reg_get(dev_id, phy_id, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.y1731_sa_chk_en = value; - ret = qca808x_ptp_tx_com_ts_ctrl_reg_set(dev_id, phy_id, ®_val); - return ret; -} - -sw_error_t -qca808x_ptp_tx_filt_mac_da0_reg_mac_addr_get( - a_uint32_t dev_id, a_uint32_t phy_id, - a_uint32_t *value) -{ - union ptp_tx_filt_mac_da0_reg_u reg_val; - sw_error_t ret = SW_OK; - - ret = qca808x_ptp_tx_filt_mac_da0_reg_get(dev_id, phy_id, ®_val); - *value = reg_val.bf.mac_addr; - return ret; -} - -sw_error_t -qca808x_ptp_tx_filt_mac_da0_reg_mac_addr_set( - a_uint32_t dev_id, a_uint32_t phy_id, - a_uint32_t value) -{ - union ptp_tx_filt_mac_da0_reg_u reg_val; - sw_error_t ret = SW_OK; - - ret = qca808x_ptp_tx_filt_mac_da0_reg_get(dev_id, phy_id, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.mac_addr = value; - ret = qca808x_ptp_tx_filt_mac_da0_reg_set(dev_id, phy_id, ®_val); - return ret; -} - -sw_error_t -qca808x_ptp_tx_filt_mac_da1_reg_mac_addr_get( - a_uint32_t dev_id, a_uint32_t phy_id, - a_uint32_t *value) -{ - union ptp_tx_filt_mac_da1_reg_u reg_val; - sw_error_t ret = SW_OK; - - ret = qca808x_ptp_tx_filt_mac_da1_reg_get(dev_id, phy_id, ®_val); - *value = reg_val.bf.mac_addr; - return ret; -} - -sw_error_t -qca808x_ptp_tx_filt_mac_da1_reg_mac_addr_set( - a_uint32_t dev_id, a_uint32_t phy_id, - a_uint32_t value) -{ - union ptp_tx_filt_mac_da1_reg_u reg_val; - sw_error_t ret = SW_OK; - - ret = qca808x_ptp_tx_filt_mac_da1_reg_get(dev_id, phy_id, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.mac_addr = value; - ret = qca808x_ptp_tx_filt_mac_da1_reg_set(dev_id, phy_id, ®_val); - return ret; -} - -sw_error_t -qca808x_ptp_tx_filt_mac_da2_reg_mac_addr_get( - a_uint32_t dev_id, a_uint32_t phy_id, - a_uint32_t *value) -{ - union ptp_tx_filt_mac_da2_reg_u reg_val; - sw_error_t ret = SW_OK; - - ret = qca808x_ptp_tx_filt_mac_da2_reg_get(dev_id, phy_id, ®_val); - *value = reg_val.bf.mac_addr; - return ret; -} - -sw_error_t -qca808x_ptp_tx_filt_mac_da2_reg_mac_addr_set( - a_uint32_t dev_id, a_uint32_t phy_id, - a_uint32_t value) -{ - union ptp_tx_filt_mac_da2_reg_u reg_val; - sw_error_t ret = SW_OK; - - ret = qca808x_ptp_tx_filt_mac_da2_reg_get(dev_id, phy_id, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.mac_addr = value; - ret = qca808x_ptp_tx_filt_mac_da2_reg_set(dev_id, phy_id, ®_val); - return ret; -} - -sw_error_t -qca808x_ptp_tx_filt_ipv4_da0_reg_ip_addr_get( - a_uint32_t dev_id, a_uint32_t phy_id, - a_uint32_t *value) -{ - union ptp_tx_filt_ipv4_da0_reg_u reg_val; - sw_error_t ret = SW_OK; - - ret = qca808x_ptp_tx_filt_ipv4_da0_reg_get(dev_id, phy_id, ®_val); - *value = reg_val.bf.ip_addr; - return ret; -} - -sw_error_t -qca808x_ptp_tx_filt_ipv4_da0_reg_ip_addr_set( - a_uint32_t dev_id, a_uint32_t phy_id, - a_uint32_t value) -{ - union ptp_tx_filt_ipv4_da0_reg_u reg_val; - sw_error_t ret = SW_OK; - - ret = qca808x_ptp_tx_filt_ipv4_da0_reg_get(dev_id, phy_id, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.ip_addr = value; - ret = qca808x_ptp_tx_filt_ipv4_da0_reg_set(dev_id, phy_id, ®_val); - return ret; -} - -sw_error_t -qca808x_ptp_tx_filt_ipv4_da1_reg_ip_addr_get( - a_uint32_t dev_id, a_uint32_t phy_id, - a_uint32_t *value) -{ - union ptp_tx_filt_ipv4_da1_reg_u reg_val; - sw_error_t ret = SW_OK; - - ret = qca808x_ptp_tx_filt_ipv4_da1_reg_get(dev_id, phy_id, ®_val); - *value = reg_val.bf.ip_addr; - return ret; -} - -sw_error_t -qca808x_ptp_tx_filt_ipv4_da1_reg_ip_addr_set( - a_uint32_t dev_id, a_uint32_t phy_id, - a_uint32_t value) -{ - union ptp_tx_filt_ipv4_da1_reg_u reg_val; - sw_error_t ret = SW_OK; - - ret = qca808x_ptp_tx_filt_ipv4_da1_reg_get(dev_id, phy_id, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.ip_addr = value; - ret = qca808x_ptp_tx_filt_ipv4_da1_reg_set(dev_id, phy_id, ®_val); - return ret; -} - -sw_error_t -qca808x_ptp_tx_filt_ipv6_da0_reg_ip_addr_get( - a_uint32_t dev_id, a_uint32_t phy_id, - a_uint32_t *value) -{ - union ptp_tx_filt_ipv6_da0_reg_u reg_val; - sw_error_t ret = SW_OK; - - ret = qca808x_ptp_tx_filt_ipv6_da0_reg_get(dev_id, phy_id, ®_val); - *value = reg_val.bf.ip_addr; - return ret; -} - -sw_error_t -qca808x_ptp_tx_filt_ipv6_da0_reg_ip_addr_set( - a_uint32_t dev_id, a_uint32_t phy_id, - a_uint32_t value) -{ - union ptp_tx_filt_ipv6_da0_reg_u reg_val; - sw_error_t ret = SW_OK; - - ret = qca808x_ptp_tx_filt_ipv6_da0_reg_get(dev_id, phy_id, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.ip_addr = value; - ret = qca808x_ptp_tx_filt_ipv6_da0_reg_set(dev_id, phy_id, ®_val); - return ret; -} - -sw_error_t -qca808x_ptp_tx_filt_ipv6_da1_reg_ip_addr_get( - a_uint32_t dev_id, a_uint32_t phy_id, - a_uint32_t *value) -{ - union ptp_tx_filt_ipv6_da1_reg_u reg_val; - sw_error_t ret = SW_OK; - - ret = qca808x_ptp_tx_filt_ipv6_da1_reg_get(dev_id, phy_id, ®_val); - *value = reg_val.bf.ip_addr; - return ret; -} - -sw_error_t -qca808x_ptp_tx_filt_ipv6_da1_reg_ip_addr_set( - a_uint32_t dev_id, a_uint32_t phy_id, - a_uint32_t value) -{ - union ptp_tx_filt_ipv6_da1_reg_u reg_val; - sw_error_t ret = SW_OK; - - ret = qca808x_ptp_tx_filt_ipv6_da1_reg_get(dev_id, phy_id, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.ip_addr = value; - ret = qca808x_ptp_tx_filt_ipv6_da1_reg_set(dev_id, phy_id, ®_val); - return ret; -} - -sw_error_t -qca808x_ptp_tx_filt_ipv6_da2_reg_ip_addr_get( - a_uint32_t dev_id, a_uint32_t phy_id, - a_uint32_t *value) -{ - union ptp_tx_filt_ipv6_da2_reg_u reg_val; - sw_error_t ret = SW_OK; - - ret = qca808x_ptp_tx_filt_ipv6_da2_reg_get(dev_id, phy_id, ®_val); - *value = reg_val.bf.ip_addr; - return ret; -} - -sw_error_t -qca808x_ptp_tx_filt_ipv6_da2_reg_ip_addr_set( - a_uint32_t dev_id, a_uint32_t phy_id, - a_uint32_t value) -{ - union ptp_tx_filt_ipv6_da2_reg_u reg_val; - sw_error_t ret = SW_OK; - - ret = qca808x_ptp_tx_filt_ipv6_da2_reg_get(dev_id, phy_id, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.ip_addr = value; - ret = qca808x_ptp_tx_filt_ipv6_da2_reg_set(dev_id, phy_id, ®_val); - return ret; -} - -sw_error_t -qca808x_ptp_tx_filt_ipv6_da3_reg_ip_addr_get( - a_uint32_t dev_id, a_uint32_t phy_id, - a_uint32_t *value) -{ - union ptp_tx_filt_ipv6_da3_reg_u reg_val; - sw_error_t ret = SW_OK; - - ret = qca808x_ptp_tx_filt_ipv6_da3_reg_get(dev_id, phy_id, ®_val); - *value = reg_val.bf.ip_addr; - return ret; -} - -sw_error_t -qca808x_ptp_tx_filt_ipv6_da3_reg_ip_addr_set( - a_uint32_t dev_id, a_uint32_t phy_id, - a_uint32_t value) -{ - union ptp_tx_filt_ipv6_da3_reg_u reg_val; - sw_error_t ret = SW_OK; - - ret = qca808x_ptp_tx_filt_ipv6_da3_reg_get(dev_id, phy_id, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.ip_addr = value; - ret = qca808x_ptp_tx_filt_ipv6_da3_reg_set(dev_id, phy_id, ®_val); - return ret; -} - -sw_error_t -qca808x_ptp_tx_filt_ipv6_da4_reg_ip_addr_get( - a_uint32_t dev_id, a_uint32_t phy_id, - a_uint32_t *value) -{ - union ptp_tx_filt_ipv6_da4_reg_u reg_val; - sw_error_t ret = SW_OK; - - ret = qca808x_ptp_tx_filt_ipv6_da4_reg_get(dev_id, phy_id, ®_val); - *value = reg_val.bf.ip_addr; - return ret; -} - -sw_error_t -qca808x_ptp_tx_filt_ipv6_da4_reg_ip_addr_set( - a_uint32_t dev_id, a_uint32_t phy_id, - a_uint32_t value) -{ - union ptp_tx_filt_ipv6_da4_reg_u reg_val; - sw_error_t ret = SW_OK; - - ret = qca808x_ptp_tx_filt_ipv6_da4_reg_get(dev_id, phy_id, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.ip_addr = value; - ret = qca808x_ptp_tx_filt_ipv6_da4_reg_set(dev_id, phy_id, ®_val); - return ret; -} - -sw_error_t -qca808x_ptp_tx_filt_ipv6_da5_reg_ip_addr_get( - a_uint32_t dev_id, a_uint32_t phy_id, - a_uint32_t *value) -{ - union ptp_tx_filt_ipv6_da5_reg_u reg_val; - sw_error_t ret = SW_OK; - - ret = qca808x_ptp_tx_filt_ipv6_da5_reg_get(dev_id, phy_id, ®_val); - *value = reg_val.bf.ip_addr; - return ret; -} - -sw_error_t -qca808x_ptp_tx_filt_ipv6_da5_reg_ip_addr_set( - a_uint32_t dev_id, a_uint32_t phy_id, - a_uint32_t value) -{ - union ptp_tx_filt_ipv6_da5_reg_u reg_val; - sw_error_t ret = SW_OK; - - ret = qca808x_ptp_tx_filt_ipv6_da5_reg_get(dev_id, phy_id, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.ip_addr = value; - ret = qca808x_ptp_tx_filt_ipv6_da5_reg_set(dev_id, phy_id, ®_val); - return ret; -} - -sw_error_t -qca808x_ptp_tx_filt_ipv6_da6_reg_ip_addr_get( - a_uint32_t dev_id, a_uint32_t phy_id, - a_uint32_t *value) -{ - union ptp_tx_filt_ipv6_da6_reg_u reg_val; - sw_error_t ret = SW_OK; - - ret = qca808x_ptp_tx_filt_ipv6_da6_reg_get(dev_id, phy_id, ®_val); - *value = reg_val.bf.ip_addr; - return ret; -} - -sw_error_t -qca808x_ptp_tx_filt_ipv6_da6_reg_ip_addr_set( - a_uint32_t dev_id, a_uint32_t phy_id, - a_uint32_t value) -{ - union ptp_tx_filt_ipv6_da6_reg_u reg_val; - sw_error_t ret = SW_OK; - - ret = qca808x_ptp_tx_filt_ipv6_da6_reg_get(dev_id, phy_id, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.ip_addr = value; - ret = qca808x_ptp_tx_filt_ipv6_da6_reg_set(dev_id, phy_id, ®_val); - return ret; -} - -sw_error_t -qca808x_ptp_tx_filt_ipv6_da7_reg_ip_addr_get( - a_uint32_t dev_id, a_uint32_t phy_id, - a_uint32_t *value) -{ - union ptp_tx_filt_ipv6_da7_reg_u reg_val; - sw_error_t ret = SW_OK; - - ret = qca808x_ptp_tx_filt_ipv6_da7_reg_get(dev_id, phy_id, ®_val); - *value = reg_val.bf.ip_addr; - return ret; -} - -sw_error_t -qca808x_ptp_tx_filt_ipv6_da7_reg_ip_addr_set( - a_uint32_t dev_id, a_uint32_t phy_id, - a_uint32_t value) -{ - union ptp_tx_filt_ipv6_da7_reg_u reg_val; - sw_error_t ret = SW_OK; - - ret = qca808x_ptp_tx_filt_ipv6_da7_reg_get(dev_id, phy_id, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.ip_addr = value; - ret = qca808x_ptp_tx_filt_ipv6_da7_reg_set(dev_id, phy_id, ®_val); - return ret; -} - -sw_error_t -qca808x_ptp_tx_filt_mac_lengthtype_reg_length_type_get( - a_uint32_t dev_id, a_uint32_t phy_id, - a_uint32_t *value) -{ - union ptp_tx_filt_mac_lengthtype_reg_u reg_val; - sw_error_t ret = SW_OK; - - ret = qca808x_ptp_tx_filt_mac_lengthtype_reg_get(dev_id, phy_id, ®_val); - *value = reg_val.bf.length_type; - return ret; -} - -sw_error_t -qca808x_ptp_tx_filt_mac_lengthtype_reg_length_type_set( - a_uint32_t dev_id, a_uint32_t phy_id, - a_uint32_t value) -{ - union ptp_tx_filt_mac_lengthtype_reg_u reg_val; - sw_error_t ret = SW_OK; - - ret = qca808x_ptp_tx_filt_mac_lengthtype_reg_get(dev_id, phy_id, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.length_type = value; - ret = qca808x_ptp_tx_filt_mac_lengthtype_reg_set(dev_id, phy_id, ®_val); - return ret; -} - -sw_error_t -qca808x_ptp_tx_filt_layer4_protocol_reg_l4_protocol_get( - a_uint32_t dev_id, a_uint32_t phy_id, - a_uint32_t *value) -{ - union ptp_tx_filt_layer4_protocol_reg_u reg_val; - sw_error_t ret = SW_OK; - - ret = qca808x_ptp_tx_filt_layer4_protocol_reg_get(dev_id, phy_id, ®_val); - *value = reg_val.bf.l4_protocol; - return ret; -} - -sw_error_t -qca808x_ptp_tx_filt_layer4_protocol_reg_l4_protocol_set( - a_uint32_t dev_id, a_uint32_t phy_id, - a_uint32_t value) -{ - union ptp_tx_filt_layer4_protocol_reg_u reg_val; - sw_error_t ret = SW_OK; - - ret = qca808x_ptp_tx_filt_layer4_protocol_reg_get(dev_id, phy_id, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.l4_protocol = value; - ret = qca808x_ptp_tx_filt_layer4_protocol_reg_set(dev_id, phy_id, ®_val); - return ret; -} - -sw_error_t -qca808x_ptp_tx_filt_udp_port_reg_udp_port_get( - a_uint32_t dev_id, a_uint32_t phy_id, - a_uint32_t *value) -{ - union ptp_tx_filt_udp_port_reg_u reg_val; - sw_error_t ret = SW_OK; - - ret = qca808x_ptp_tx_filt_udp_port_reg_get(dev_id, phy_id, ®_val); - *value = reg_val.bf.udp_port; - return ret; -} - -sw_error_t -qca808x_ptp_tx_filt_udp_port_reg_udp_port_set( - a_uint32_t dev_id, a_uint32_t phy_id, - a_uint32_t value) -{ - union ptp_tx_filt_udp_port_reg_u reg_val; - sw_error_t ret = SW_OK; - - ret = qca808x_ptp_tx_filt_udp_port_reg_get(dev_id, phy_id, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.udp_port = value; - ret = qca808x_ptp_tx_filt_udp_port_reg_set(dev_id, phy_id, ®_val); - return ret; -} - -sw_error_t -qca808x_ptp_tx_com_ts_status_reg_mac_ptp_pdelay_addr_get( - a_uint32_t dev_id, a_uint32_t phy_id, - a_uint32_t *value) -{ - union ptp_tx_com_ts_status_reg_u reg_val; - sw_error_t ret = SW_OK; - - ret = qca808x_ptp_tx_com_ts_status_reg_get(dev_id, phy_id, ®_val); - *value = reg_val.bf.mac_ptp_pdelay_addr; - return ret; -} - -sw_error_t -qca808x_ptp_tx_com_ts_status_reg_mac_ptp_pdelay_addr_set( - a_uint32_t dev_id, a_uint32_t phy_id, - a_uint32_t value) -{ - union ptp_tx_com_ts_status_reg_u reg_val; - sw_error_t ret = SW_OK; - - ret = qca808x_ptp_tx_com_ts_status_reg_get(dev_id, phy_id, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.mac_ptp_pdelay_addr = value; - ret = qca808x_ptp_tx_com_ts_status_reg_set(dev_id, phy_id, ®_val); - return ret; -} - -sw_error_t -qca808x_ptp_tx_com_ts_status_reg_mac_da_get( - a_uint32_t dev_id, a_uint32_t phy_id, - a_uint32_t *value) -{ - union ptp_tx_com_ts_status_reg_u reg_val; - sw_error_t ret = SW_OK; - - ret = qca808x_ptp_tx_com_ts_status_reg_get(dev_id, phy_id, ®_val); - *value = reg_val.bf.mac_da; - return ret; -} - -sw_error_t -qca808x_ptp_tx_com_ts_status_reg_mac_da_set( - a_uint32_t dev_id, a_uint32_t phy_id, - a_uint32_t value) -{ - union ptp_tx_com_ts_status_reg_u reg_val; - sw_error_t ret = SW_OK; - - ret = qca808x_ptp_tx_com_ts_status_reg_get(dev_id, phy_id, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.mac_da = value; - ret = qca808x_ptp_tx_com_ts_status_reg_set(dev_id, phy_id, ®_val); - return ret; -} - -sw_error_t -qca808x_ptp_tx_com_ts_status_reg_ipv4_ptp_pdelay_addr_get( - a_uint32_t dev_id, a_uint32_t phy_id, - a_uint32_t *value) -{ - union ptp_tx_com_ts_status_reg_u reg_val; - sw_error_t ret = SW_OK; - - ret = qca808x_ptp_tx_com_ts_status_reg_get(dev_id, phy_id, ®_val); - *value = reg_val.bf.ipv4_ptp_pdelay_addr; - return ret; -} - -sw_error_t -qca808x_ptp_tx_com_ts_status_reg_ipv4_ptp_pdelay_addr_set( - a_uint32_t dev_id, a_uint32_t phy_id, - a_uint32_t value) -{ - union ptp_tx_com_ts_status_reg_u reg_val; - sw_error_t ret = SW_OK; - - ret = qca808x_ptp_tx_com_ts_status_reg_get(dev_id, phy_id, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.ipv4_ptp_pdelay_addr = value; - ret = qca808x_ptp_tx_com_ts_status_reg_set(dev_id, phy_id, ®_val); - return ret; -} - -sw_error_t -qca808x_ptp_tx_com_ts_status_reg_mac_lengthtype_get( - a_uint32_t dev_id, a_uint32_t phy_id, - a_uint32_t *value) -{ - union ptp_tx_com_ts_status_reg_u reg_val; - sw_error_t ret = SW_OK; - - ret = qca808x_ptp_tx_com_ts_status_reg_get(dev_id, phy_id, ®_val); - *value = reg_val.bf.mac_lengthtype; - return ret; -} - -sw_error_t -qca808x_ptp_tx_com_ts_status_reg_mac_lengthtype_set( - a_uint32_t dev_id, a_uint32_t phy_id, - a_uint32_t value) -{ - union ptp_tx_com_ts_status_reg_u reg_val; - sw_error_t ret = SW_OK; - - ret = qca808x_ptp_tx_com_ts_status_reg_get(dev_id, phy_id, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.mac_lengthtype = value; - ret = qca808x_ptp_tx_com_ts_status_reg_set(dev_id, phy_id, ®_val); - return ret; -} - -sw_error_t -qca808x_ptp_tx_com_ts_status_reg_udp_dport_get( - a_uint32_t dev_id, a_uint32_t phy_id, - a_uint32_t *value) -{ - union ptp_tx_com_ts_status_reg_u reg_val; - sw_error_t ret = SW_OK; - - ret = qca808x_ptp_tx_com_ts_status_reg_get(dev_id, phy_id, ®_val); - *value = reg_val.bf.udp_dport; - return ret; -} - -sw_error_t -qca808x_ptp_tx_com_ts_status_reg_udp_dport_set( - a_uint32_t dev_id, a_uint32_t phy_id, - a_uint32_t value) -{ - union ptp_tx_com_ts_status_reg_u reg_val; - sw_error_t ret = SW_OK; - - ret = qca808x_ptp_tx_com_ts_status_reg_get(dev_id, phy_id, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.udp_dport = value; - ret = qca808x_ptp_tx_com_ts_status_reg_set(dev_id, phy_id, ®_val); - return ret; -} - -sw_error_t -qca808x_ptp_tx_com_ts_status_reg_ipv4_layer4_protocol_get( - a_uint32_t dev_id, a_uint32_t phy_id, - a_uint32_t *value) -{ - union ptp_tx_com_ts_status_reg_u reg_val; - sw_error_t ret = SW_OK; - - ret = qca808x_ptp_tx_com_ts_status_reg_get(dev_id, phy_id, ®_val); - *value = reg_val.bf.ipv4_layer4_protocol; - return ret; -} - -sw_error_t -qca808x_ptp_tx_com_ts_status_reg_ipv4_layer4_protocol_set( - a_uint32_t dev_id, a_uint32_t phy_id, - a_uint32_t value) -{ - union ptp_tx_com_ts_status_reg_u reg_val; - sw_error_t ret = SW_OK; - - ret = qca808x_ptp_tx_com_ts_status_reg_get(dev_id, phy_id, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.ipv4_layer4_protocol = value; - ret = qca808x_ptp_tx_com_ts_status_reg_set(dev_id, phy_id, ®_val); - return ret; -} - -sw_error_t -qca808x_ptp_tx_com_ts_status_reg_udp_ptp_event_dport_get( - a_uint32_t dev_id, a_uint32_t phy_id, - a_uint32_t *value) -{ - union ptp_tx_com_ts_status_reg_u reg_val; - sw_error_t ret = SW_OK; - - ret = qca808x_ptp_tx_com_ts_status_reg_get(dev_id, phy_id, ®_val); - *value = reg_val.bf.udp_ptp_event_dport; - return ret; -} - -sw_error_t -qca808x_ptp_tx_com_ts_status_reg_udp_ptp_event_dport_set( - a_uint32_t dev_id, a_uint32_t phy_id, - a_uint32_t value) -{ - union ptp_tx_com_ts_status_reg_u reg_val; - sw_error_t ret = SW_OK; - - ret = qca808x_ptp_tx_com_ts_status_reg_get(dev_id, phy_id, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.udp_ptp_event_dport = value; - ret = qca808x_ptp_tx_com_ts_status_reg_set(dev_id, phy_id, ®_val); - return ret; -} - -sw_error_t -qca808x_ptp_tx_com_ts_status_reg_ipv6_da_get( - a_uint32_t dev_id, a_uint32_t phy_id, - a_uint32_t *value) -{ - union ptp_tx_com_ts_status_reg_u reg_val; - sw_error_t ret = SW_OK; - - ret = qca808x_ptp_tx_com_ts_status_reg_get(dev_id, phy_id, ®_val); - *value = reg_val.bf.ipv6_da; - return ret; -} - -sw_error_t -qca808x_ptp_tx_com_ts_status_reg_ipv6_da_set( - a_uint32_t dev_id, a_uint32_t phy_id, - a_uint32_t value) -{ - union ptp_tx_com_ts_status_reg_u reg_val; - sw_error_t ret = SW_OK; - - ret = qca808x_ptp_tx_com_ts_status_reg_get(dev_id, phy_id, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.ipv6_da = value; - ret = qca808x_ptp_tx_com_ts_status_reg_set(dev_id, phy_id, ®_val); - return ret; -} - -sw_error_t -qca808x_ptp_tx_com_ts_status_reg_ipv4_ptp_prim_addr_get( - a_uint32_t dev_id, a_uint32_t phy_id, - a_uint32_t *value) -{ - union ptp_tx_com_ts_status_reg_u reg_val; - sw_error_t ret = SW_OK; - - ret = qca808x_ptp_tx_com_ts_status_reg_get(dev_id, phy_id, ®_val); - *value = reg_val.bf.ipv4_ptp_prim_addr; - return ret; -} - -sw_error_t -qca808x_ptp_tx_com_ts_status_reg_ipv4_ptp_prim_addr_set( - a_uint32_t dev_id, a_uint32_t phy_id, - a_uint32_t value) -{ - union ptp_tx_com_ts_status_reg_u reg_val; - sw_error_t ret = SW_OK; - - ret = qca808x_ptp_tx_com_ts_status_reg_get(dev_id, phy_id, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.ipv4_ptp_prim_addr = value; - ret = qca808x_ptp_tx_com_ts_status_reg_set(dev_id, phy_id, ®_val); - return ret; -} - -sw_error_t -qca808x_ptp_tx_com_ts_status_reg_ipv4_da_get( - a_uint32_t dev_id, a_uint32_t phy_id, - a_uint32_t *value) -{ - union ptp_tx_com_ts_status_reg_u reg_val; - sw_error_t ret = SW_OK; - - ret = qca808x_ptp_tx_com_ts_status_reg_get(dev_id, phy_id, ®_val); - *value = reg_val.bf.ipv4_da; - return ret; -} - -sw_error_t -qca808x_ptp_tx_com_ts_status_reg_ipv4_da_set( - a_uint32_t dev_id, a_uint32_t phy_id, - a_uint32_t value) -{ - union ptp_tx_com_ts_status_reg_u reg_val; - sw_error_t ret = SW_OK; - - ret = qca808x_ptp_tx_com_ts_status_reg_get(dev_id, phy_id, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.ipv4_da = value; - ret = qca808x_ptp_tx_com_ts_status_reg_set(dev_id, phy_id, ®_val); - return ret; -} - -sw_error_t -qca808x_ptp_tx_com_ts_status_reg_ipv6_ptp_pdelay_addr_get( - a_uint32_t dev_id, a_uint32_t phy_id, - a_uint32_t *value) -{ - union ptp_tx_com_ts_status_reg_u reg_val; - sw_error_t ret = SW_OK; - - ret = qca808x_ptp_tx_com_ts_status_reg_get(dev_id, phy_id, ®_val); - *value = reg_val.bf.ipv6_ptp_pdelay_addr; - return ret; -} - -sw_error_t -qca808x_ptp_tx_com_ts_status_reg_ipv6_ptp_pdelay_addr_set( - a_uint32_t dev_id, a_uint32_t phy_id, - a_uint32_t value) -{ - union ptp_tx_com_ts_status_reg_u reg_val; - sw_error_t ret = SW_OK; - - ret = qca808x_ptp_tx_com_ts_status_reg_get(dev_id, phy_id, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.ipv6_ptp_pdelay_addr = value; - ret = qca808x_ptp_tx_com_ts_status_reg_set(dev_id, phy_id, ®_val); - return ret; -} - -sw_error_t -qca808x_ptp_tx_com_ts_status_reg_ipv6_ptp_prim_addr_get( - a_uint32_t dev_id, a_uint32_t phy_id, - a_uint32_t *value) -{ - union ptp_tx_com_ts_status_reg_u reg_val; - sw_error_t ret = SW_OK; - - ret = qca808x_ptp_tx_com_ts_status_reg_get(dev_id, phy_id, ®_val); - *value = reg_val.bf.ipv6_ptp_prim_addr; - return ret; -} - -sw_error_t -qca808x_ptp_tx_com_ts_status_reg_ipv6_ptp_prim_addr_set( - a_uint32_t dev_id, a_uint32_t phy_id, - a_uint32_t value) -{ - union ptp_tx_com_ts_status_reg_u reg_val; - sw_error_t ret = SW_OK; - - ret = qca808x_ptp_tx_com_ts_status_reg_get(dev_id, phy_id, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.ipv6_ptp_prim_addr = value; - ret = qca808x_ptp_tx_com_ts_status_reg_set(dev_id, phy_id, ®_val); - return ret; -} - -sw_error_t -qca808x_ptp_tx_com_ts_status_reg_ipv6_next_header_get( - a_uint32_t dev_id, a_uint32_t phy_id, - a_uint32_t *value) -{ - union ptp_tx_com_ts_status_reg_u reg_val; - sw_error_t ret = SW_OK; - - ret = qca808x_ptp_tx_com_ts_status_reg_get(dev_id, phy_id, ®_val); - *value = reg_val.bf.ipv6_next_header; - return ret; -} - -sw_error_t -qca808x_ptp_tx_com_ts_status_reg_ipv6_next_header_set( - a_uint32_t dev_id, a_uint32_t phy_id, - a_uint32_t value) -{ - union ptp_tx_com_ts_status_reg_u reg_val; - sw_error_t ret = SW_OK; - - ret = qca808x_ptp_tx_com_ts_status_reg_get(dev_id, phy_id, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.ipv6_next_header = value; - ret = qca808x_ptp_tx_com_ts_status_reg_set(dev_id, phy_id, ®_val); - return ret; -} - -sw_error_t -qca808x_ptp_tx_com_ts_status_reg_y1731_mach_get( - a_uint32_t dev_id, a_uint32_t phy_id, - a_uint32_t *value) -{ - union ptp_tx_com_ts_status_reg_u reg_val; - sw_error_t ret = SW_OK; - - ret = qca808x_ptp_tx_com_ts_status_reg_get(dev_id, phy_id, ®_val); - *value = reg_val.bf.y1731_mach; - return ret; -} - -sw_error_t -qca808x_ptp_tx_com_ts_status_reg_y1731_mach_set( - a_uint32_t dev_id, a_uint32_t phy_id, - a_uint32_t value) -{ - union ptp_tx_com_ts_status_reg_u reg_val; - sw_error_t ret = SW_OK; - - ret = qca808x_ptp_tx_com_ts_status_reg_get(dev_id, phy_id, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.y1731_mach = value; - ret = qca808x_ptp_tx_com_ts_status_reg_set(dev_id, phy_id, ®_val); - return ret; -} - -sw_error_t -qca808x_ptp_tx_com_ts_status_reg_mac_ptp_prim_addr_get( - a_uint32_t dev_id, a_uint32_t phy_id, - a_uint32_t *value) -{ - union ptp_tx_com_ts_status_reg_u reg_val; - sw_error_t ret = SW_OK; - - ret = qca808x_ptp_tx_com_ts_status_reg_get(dev_id, phy_id, ®_val); - *value = reg_val.bf.mac_ptp_prim_addr; - return ret; -} - -sw_error_t -qca808x_ptp_tx_com_ts_status_reg_mac_ptp_prim_addr_set( - a_uint32_t dev_id, a_uint32_t phy_id, - a_uint32_t value) -{ - union ptp_tx_com_ts_status_reg_u reg_val; - sw_error_t ret = SW_OK; - - ret = qca808x_ptp_tx_com_ts_status_reg_get(dev_id, phy_id, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.mac_ptp_prim_addr = value; - ret = qca808x_ptp_tx_com_ts_status_reg_set(dev_id, phy_id, ®_val); - return ret; -} - -sw_error_t -qca808x_ptp_tx_com_timestamp0_reg_com_ts_get( - a_uint32_t dev_id, a_uint32_t phy_id, - a_uint32_t *value) -{ - union ptp_tx_com_timestamp0_reg_u reg_val; - sw_error_t ret = SW_OK; - - ret = qca808x_ptp_tx_com_timestamp0_reg_get(dev_id, phy_id, ®_val); - *value = reg_val.bf.com_ts; - return ret; -} - -sw_error_t -qca808x_ptp_tx_com_timestamp0_reg_com_ts_set( - a_uint32_t dev_id, a_uint32_t phy_id, - a_uint32_t value) -{ - union ptp_tx_com_timestamp0_reg_u reg_val; - sw_error_t ret = SW_OK; - - ret = qca808x_ptp_tx_com_timestamp0_reg_get(dev_id, phy_id, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.com_ts = value; - ret = qca808x_ptp_tx_com_timestamp0_reg_set(dev_id, phy_id, ®_val); - return ret; -} - -sw_error_t -qca808x_ptp_tx_com_timestamp1_reg_com_ts_get( - a_uint32_t dev_id, a_uint32_t phy_id, - a_uint32_t *value) -{ - union ptp_tx_com_timestamp1_reg_u reg_val; - sw_error_t ret = SW_OK; - - ret = qca808x_ptp_tx_com_timestamp1_reg_get(dev_id, phy_id, ®_val); - *value = reg_val.bf.com_ts; - return ret; -} - -sw_error_t -qca808x_ptp_tx_com_timestamp1_reg_com_ts_set( - a_uint32_t dev_id, a_uint32_t phy_id, - a_uint32_t value) -{ - union ptp_tx_com_timestamp1_reg_u reg_val; - sw_error_t ret = SW_OK; - - ret = qca808x_ptp_tx_com_timestamp1_reg_get(dev_id, phy_id, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.com_ts = value; - ret = qca808x_ptp_tx_com_timestamp1_reg_set(dev_id, phy_id, ®_val); - return ret; -} - -sw_error_t -qca808x_ptp_tx_com_timestamp2_reg_com_ts_get( - a_uint32_t dev_id, a_uint32_t phy_id, - a_uint32_t *value) -{ - union ptp_tx_com_timestamp2_reg_u reg_val; - sw_error_t ret = SW_OK; - - ret = qca808x_ptp_tx_com_timestamp2_reg_get(dev_id, phy_id, ®_val); - *value = reg_val.bf.com_ts; - return ret; -} - -sw_error_t -qca808x_ptp_tx_com_timestamp2_reg_com_ts_set( - a_uint32_t dev_id, a_uint32_t phy_id, - a_uint32_t value) -{ - union ptp_tx_com_timestamp2_reg_u reg_val; - sw_error_t ret = SW_OK; - - ret = qca808x_ptp_tx_com_timestamp2_reg_get(dev_id, phy_id, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.com_ts = value; - ret = qca808x_ptp_tx_com_timestamp2_reg_set(dev_id, phy_id, ®_val); - return ret; -} - -sw_error_t -qca808x_ptp_tx_com_timestamp3_reg_com_ts_get( - a_uint32_t dev_id, a_uint32_t phy_id, - a_uint32_t *value) -{ - union ptp_tx_com_timestamp3_reg_u reg_val; - sw_error_t ret = SW_OK; - - ret = qca808x_ptp_tx_com_timestamp3_reg_get(dev_id, phy_id, ®_val); - *value = reg_val.bf.com_ts; - return ret; -} - -sw_error_t -qca808x_ptp_tx_com_timestamp3_reg_com_ts_set( - a_uint32_t dev_id, a_uint32_t phy_id, - a_uint32_t value) -{ - union ptp_tx_com_timestamp3_reg_u reg_val; - sw_error_t ret = SW_OK; - - ret = qca808x_ptp_tx_com_timestamp3_reg_get(dev_id, phy_id, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.com_ts = value; - ret = qca808x_ptp_tx_com_timestamp3_reg_set(dev_id, phy_id, ®_val); - return ret; -} - -sw_error_t -qca808x_ptp_tx_com_timestamp4_reg_com_ts_get( - a_uint32_t dev_id, a_uint32_t phy_id, - a_uint32_t *value) -{ - union ptp_tx_com_timestamp4_reg_u reg_val; - sw_error_t ret = SW_OK; - - ret = qca808x_ptp_tx_com_timestamp4_reg_get(dev_id, phy_id, ®_val); - *value = reg_val.bf.com_ts; - return ret; -} - -sw_error_t -qca808x_ptp_tx_com_timestamp4_reg_com_ts_set( - a_uint32_t dev_id, a_uint32_t phy_id, - a_uint32_t value) -{ - union ptp_tx_com_timestamp4_reg_u reg_val; - sw_error_t ret = SW_OK; - - ret = qca808x_ptp_tx_com_timestamp4_reg_get(dev_id, phy_id, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.com_ts = value; - ret = qca808x_ptp_tx_com_timestamp4_reg_set(dev_id, phy_id, ®_val); - return ret; -} - -sw_error_t -qca808x_ptp_tx_com_frac_nano_reg_frac_nano_get( - a_uint32_t dev_id, a_uint32_t phy_id, - a_uint32_t *value) -{ - union ptp_tx_com_frac_nano_reg_u reg_val; - sw_error_t ret = SW_OK; - - ret = qca808x_ptp_tx_com_frac_nano_reg_get(dev_id, phy_id, ®_val); - *value = reg_val.bf.frac_nano; - return ret; -} - -sw_error_t -qca808x_ptp_tx_com_frac_nano_reg_frac_nano_set( - a_uint32_t dev_id, a_uint32_t phy_id, - a_uint32_t value) -{ - union ptp_tx_com_frac_nano_reg_u reg_val; - sw_error_t ret = SW_OK; - - ret = qca808x_ptp_tx_com_frac_nano_reg_get(dev_id, phy_id, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.frac_nano = value; - ret = qca808x_ptp_tx_com_frac_nano_reg_set(dev_id, phy_id, ®_val); - return ret; -} - -sw_error_t -qca808x_ptp_tx_y1731_identify_reg_identify_get( - a_uint32_t dev_id, a_uint32_t phy_id, - a_uint32_t *value) -{ - union ptp_tx_y1731_identify_reg_u reg_val; - sw_error_t ret = SW_OK; - - ret = qca808x_ptp_tx_y1731_identify_reg_get(dev_id, phy_id, ®_val); - *value = reg_val.bf.identify; - return ret; -} - -sw_error_t -qca808x_ptp_tx_y1731_identify_reg_identify_set( - a_uint32_t dev_id, a_uint32_t phy_id, - a_uint32_t value) -{ - union ptp_tx_y1731_identify_reg_u reg_val; - sw_error_t ret = SW_OK; - - ret = qca808x_ptp_tx_y1731_identify_reg_get(dev_id, phy_id, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.identify = value; - ret = qca808x_ptp_tx_y1731_identify_reg_set(dev_id, phy_id, ®_val); - return ret; -} - -sw_error_t -qca808x_ptp_y1731_dm_control_reg_y1731_dmm_lpbk_en_get( - a_uint32_t dev_id, a_uint32_t phy_id, - a_uint32_t *value) -{ - union ptp_y1731_dm_control_reg_u reg_val; - sw_error_t ret = SW_OK; - - ret = qca808x_ptp_y1731_dm_control_reg_get(dev_id, phy_id, ®_val); - *value = reg_val.bf.y1731_dmm_lpbk_en; - return ret; -} - -sw_error_t -qca808x_ptp_y1731_dm_control_reg_y1731_dmm_lpbk_en_set( - a_uint32_t dev_id, a_uint32_t phy_id, - a_uint32_t value) -{ - union ptp_y1731_dm_control_reg_u reg_val; - sw_error_t ret = SW_OK; - - ret = qca808x_ptp_y1731_dm_control_reg_get(dev_id, phy_id, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.y1731_dmm_lpbk_en = value; - ret = qca808x_ptp_y1731_dm_control_reg_set(dev_id, phy_id, ®_val); - return ret; -} - -sw_error_t -qca808x_ptp_y1731_dm_control_reg_valid_msg_lev_bmp_get( - a_uint32_t dev_id, a_uint32_t phy_id, - a_uint32_t *value) -{ - union ptp_y1731_dm_control_reg_u reg_val; - sw_error_t ret = SW_OK; - - ret = qca808x_ptp_y1731_dm_control_reg_get(dev_id, phy_id, ®_val); - *value = reg_val.bf.valid_msg_lev_bmp; - return ret; -} - -sw_error_t -qca808x_ptp_y1731_dm_control_reg_valid_msg_lev_bmp_set( - a_uint32_t dev_id, a_uint32_t phy_id, - a_uint32_t value) -{ - union ptp_y1731_dm_control_reg_u reg_val; - sw_error_t ret = SW_OK; - - ret = qca808x_ptp_y1731_dm_control_reg_get(dev_id, phy_id, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.valid_msg_lev_bmp = value; - ret = qca808x_ptp_y1731_dm_control_reg_set(dev_id, phy_id, ®_val); - return ret; -} - -sw_error_t -qca808x_ptp_baud_config_reg_baud_rate_get( - a_uint32_t dev_id, a_uint32_t phy_id, - a_uint32_t *value) -{ - union ptp_baud_config_reg_u reg_val; - sw_error_t ret = SW_OK; - - ret = qca808x_ptp_baud_config_reg_get(dev_id, phy_id, ®_val); - *value = reg_val.bf.baud_rate; - return ret; -} - -sw_error_t -qca808x_ptp_baud_config_reg_baud_rate_set( - a_uint32_t dev_id, a_uint32_t phy_id, - a_uint32_t value) -{ - union ptp_baud_config_reg_u reg_val; - sw_error_t ret = SW_OK; - - ret = qca808x_ptp_baud_config_reg_get(dev_id, phy_id, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.baud_rate = value; - ret = qca808x_ptp_baud_config_reg_set(dev_id, phy_id, ®_val); - return ret; -} - -sw_error_t -qca808x_ptp_uart_configuration_reg_start_polarity_get( - a_uint32_t dev_id, a_uint32_t phy_id, - unsigned int *value) -{ - union ptp_uart_configuration_reg_u reg_val; - sw_error_t ret = SW_OK; - - ret = qca808x_ptp_uart_configuration_reg_get(dev_id, phy_id, ®_val); - *value = reg_val.bf.start_polarity; - return ret; -} - -sw_error_t -qca808x_ptp_uart_configuration_reg_start_polarity_set( - a_uint32_t dev_id, a_uint32_t phy_id, - a_uint32_t value) -{ - union ptp_uart_configuration_reg_u reg_val; - sw_error_t ret = SW_OK; - - ret = qca808x_ptp_uart_configuration_reg_get(dev_id, phy_id, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.start_polarity = value; - ret = qca808x_ptp_uart_configuration_reg_set(dev_id, phy_id, ®_val); - return ret; -} - -sw_error_t -qca808x_ptp_uart_configuration_reg_msb_first_get( - a_uint32_t dev_id, a_uint32_t phy_id, - unsigned int *value) -{ - union ptp_uart_configuration_reg_u reg_val; - sw_error_t ret = SW_OK; - - ret = qca808x_ptp_uart_configuration_reg_get(dev_id, phy_id, ®_val); - *value = reg_val.bf.msb_first; - return ret; -} - -sw_error_t -qca808x_ptp_uart_configuration_reg_msb_first_set( - a_uint32_t dev_id, a_uint32_t phy_id, - a_uint32_t value) -{ - union ptp_uart_configuration_reg_u reg_val; - sw_error_t ret = SW_OK; - - ret = qca808x_ptp_uart_configuration_reg_get(dev_id, phy_id, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.msb_first = value; - ret = qca808x_ptp_uart_configuration_reg_set(dev_id, phy_id, ®_val); - return ret; -} - -sw_error_t -qca808x_ptp_uart_configuration_reg_parity_en_get( - a_uint32_t dev_id, a_uint32_t phy_id, - unsigned int *value) -{ - union ptp_uart_configuration_reg_u reg_val; - sw_error_t ret = SW_OK; - - ret = qca808x_ptp_uart_configuration_reg_get(dev_id, phy_id, ®_val); - *value = reg_val.bf.parity_en; - return ret; -} - -sw_error_t -qca808x_ptp_uart_configuration_reg_parity_en_set( - a_uint32_t dev_id, a_uint32_t phy_id, - a_uint32_t value) -{ - union ptp_uart_configuration_reg_u reg_val; - sw_error_t ret = SW_OK; - - ret = qca808x_ptp_uart_configuration_reg_get(dev_id, phy_id, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.parity_en = value; - ret = qca808x_ptp_uart_configuration_reg_set(dev_id, phy_id, ®_val); - return ret; -} - -sw_error_t -qca808x_ptp_uart_configuration_reg_auto_tod_out_en_get( - a_uint32_t dev_id, a_uint32_t phy_id, - unsigned int *value) -{ - union ptp_uart_configuration_reg_u reg_val; - sw_error_t ret = SW_OK; - - ret = qca808x_ptp_uart_configuration_reg_get(dev_id, phy_id, ®_val); - *value = reg_val.bf.auto_tod_out_en; - return ret; -} - -sw_error_t -qca808x_ptp_uart_configuration_reg_auto_tod_out_en_set( - a_uint32_t dev_id, a_uint32_t phy_id, - a_uint32_t value) -{ - union ptp_uart_configuration_reg_u reg_val; - sw_error_t ret = SW_OK; - - ret = qca808x_ptp_uart_configuration_reg_get(dev_id, phy_id, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.auto_tod_out_en = value; - ret = qca808x_ptp_uart_configuration_reg_set(dev_id, phy_id, ®_val); - return ret; -} - -sw_error_t -qca808x_ptp_uart_configuration_reg_auto_tod_in_en_get( - a_uint32_t dev_id, a_uint32_t phy_id, - unsigned int *value) -{ - union ptp_uart_configuration_reg_u reg_val; - sw_error_t ret = SW_OK; - - ret = qca808x_ptp_uart_configuration_reg_get(dev_id, phy_id, ®_val); - *value = reg_val.bf.auto_tod_in_en; - return ret; -} - -sw_error_t -qca808x_ptp_uart_configuration_reg_auto_tod_in_en_set( - a_uint32_t dev_id, a_uint32_t phy_id, - a_uint32_t value) -{ - union ptp_uart_configuration_reg_u reg_val; - sw_error_t ret = SW_OK; - - ret = qca808x_ptp_uart_configuration_reg_get(dev_id, phy_id, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.auto_tod_in_en = value; - ret = qca808x_ptp_uart_configuration_reg_set(dev_id, phy_id, ®_val); - return ret; -} - -sw_error_t -qca808x_ptp_reset_buffer_reg_reset_get( - a_uint32_t dev_id, a_uint32_t phy_id, - a_uint32_t *value) -{ - union ptp_reset_buffer_reg_u reg_val; - sw_error_t ret = SW_OK; - - ret = qca808x_ptp_reset_buffer_reg_get(dev_id, phy_id, ®_val); - *value = reg_val.bf.reset; - return ret; -} - -sw_error_t -qca808x_ptp_reset_buffer_reg_reset_set( - a_uint32_t dev_id, a_uint32_t phy_id, - a_uint32_t value) -{ - union ptp_reset_buffer_reg_u reg_val; - sw_error_t ret = SW_OK; - - ret = qca808x_ptp_reset_buffer_reg_get(dev_id, phy_id, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.reset = value; - ret = qca808x_ptp_reset_buffer_reg_set(dev_id, phy_id, ®_val); - return ret; -} - -sw_error_t -qca808x_ptp_buffer_status_reg_tx_buffer_almost_empty_get( - a_uint32_t dev_id, a_uint32_t phy_id, - a_uint32_t *value) -{ - union ptp_buffer_status_reg_u reg_val; - sw_error_t ret = SW_OK; - - ret = qca808x_ptp_buffer_status_reg_get(dev_id, phy_id, ®_val); - *value = reg_val.bf.tx_buffer_almost_empty; - return ret; -} - -sw_error_t -qca808x_ptp_buffer_status_reg_tx_buffer_almost_empty_set( - a_uint32_t dev_id, a_uint32_t phy_id, - a_uint32_t value) -{ - union ptp_buffer_status_reg_u reg_val; - sw_error_t ret = SW_OK; - - ret = qca808x_ptp_buffer_status_reg_get(dev_id, phy_id, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.tx_buffer_almost_empty = value; - ret = qca808x_ptp_buffer_status_reg_set(dev_id, phy_id, ®_val); - return ret; -} - -sw_error_t -qca808x_ptp_buffer_status_reg_tx_buffer_almost_full_get( - a_uint32_t dev_id, a_uint32_t phy_id, - a_uint32_t *value) -{ - union ptp_buffer_status_reg_u reg_val; - sw_error_t ret = SW_OK; - - ret = qca808x_ptp_buffer_status_reg_get(dev_id, phy_id, ®_val); - *value = reg_val.bf.tx_buffer_almost_full; - return ret; -} - -sw_error_t -qca808x_ptp_buffer_status_reg_tx_buffer_almost_full_set( - a_uint32_t dev_id, a_uint32_t phy_id, - a_uint32_t value) -{ - union ptp_buffer_status_reg_u reg_val; - sw_error_t ret = SW_OK; - - ret = qca808x_ptp_buffer_status_reg_get(dev_id, phy_id, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.tx_buffer_almost_full = value; - ret = qca808x_ptp_buffer_status_reg_set(dev_id, phy_id, ®_val); - return ret; -} - -sw_error_t -qca808x_ptp_buffer_status_reg_tx_buffer_half_full_get( - a_uint32_t dev_id, a_uint32_t phy_id, - a_uint32_t *value) -{ - union ptp_buffer_status_reg_u reg_val; - sw_error_t ret = SW_OK; - - ret = qca808x_ptp_buffer_status_reg_get(dev_id, phy_id, ®_val); - *value = reg_val.bf.tx_buffer_half_full; - return ret; -} - -sw_error_t -qca808x_ptp_buffer_status_reg_tx_buffer_half_full_set( - a_uint32_t dev_id, a_uint32_t phy_id, - a_uint32_t value) -{ - union ptp_buffer_status_reg_u reg_val; - sw_error_t ret = SW_OK; - - ret = qca808x_ptp_buffer_status_reg_get(dev_id, phy_id, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.tx_buffer_half_full = value; - ret = qca808x_ptp_buffer_status_reg_set(dev_id, phy_id, ®_val); - return ret; -} - -sw_error_t -qca808x_ptp_buffer_status_reg_tx_buffer_full_get( - a_uint32_t dev_id, a_uint32_t phy_id, - a_uint32_t *value) -{ - union ptp_buffer_status_reg_u reg_val; - sw_error_t ret = SW_OK; - - ret = qca808x_ptp_buffer_status_reg_get(dev_id, phy_id, ®_val); - *value = reg_val.bf.tx_buffer_full; - return ret; -} - -sw_error_t -qca808x_ptp_buffer_status_reg_tx_buffer_full_set( - a_uint32_t dev_id, a_uint32_t phy_id, - a_uint32_t value) -{ - union ptp_buffer_status_reg_u reg_val; - sw_error_t ret = SW_OK; - - ret = qca808x_ptp_buffer_status_reg_get(dev_id, phy_id, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.tx_buffer_full = value; - ret = qca808x_ptp_buffer_status_reg_set(dev_id, phy_id, ®_val); - return ret; -} - -sw_error_t -qca808x_ptp_buffer_status_reg_rx_buffer_almost_empty_get( - a_uint32_t dev_id, a_uint32_t phy_id, - a_uint32_t *value) -{ - union ptp_buffer_status_reg_u reg_val; - sw_error_t ret = SW_OK; - - ret = qca808x_ptp_buffer_status_reg_get(dev_id, phy_id, ®_val); - *value = reg_val.bf.rx_buffer_almost_empty; - return ret; -} - -sw_error_t -qca808x_ptp_buffer_status_reg_rx_buffer_almost_empty_set( - a_uint32_t dev_id, a_uint32_t phy_id, - a_uint32_t value) -{ - union ptp_buffer_status_reg_u reg_val; - sw_error_t ret = SW_OK; - - ret = qca808x_ptp_buffer_status_reg_get(dev_id, phy_id, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.rx_buffer_almost_empty = value; - ret = qca808x_ptp_buffer_status_reg_set(dev_id, phy_id, ®_val); - return ret; -} - -sw_error_t -qca808x_ptp_buffer_status_reg_rx_buffer_almost_full_get( - a_uint32_t dev_id, a_uint32_t phy_id, - a_uint32_t *value) -{ - union ptp_buffer_status_reg_u reg_val; - sw_error_t ret = SW_OK; - - ret = qca808x_ptp_buffer_status_reg_get(dev_id, phy_id, ®_val); - *value = reg_val.bf.rx_buffer_almost_full; - return ret; -} - -sw_error_t -qca808x_ptp_buffer_status_reg_rx_buffer_almost_full_set( - a_uint32_t dev_id, a_uint32_t phy_id, - a_uint32_t value) -{ - union ptp_buffer_status_reg_u reg_val; - sw_error_t ret = SW_OK; - - ret = qca808x_ptp_buffer_status_reg_get(dev_id, phy_id, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.rx_buffer_almost_full = value; - ret = qca808x_ptp_buffer_status_reg_set(dev_id, phy_id, ®_val); - return ret; -} - -sw_error_t -qca808x_ptp_buffer_status_reg_rx_buffer_half_full_get( - a_uint32_t dev_id, a_uint32_t phy_id, - a_uint32_t *value) -{ - union ptp_buffer_status_reg_u reg_val; - sw_error_t ret = SW_OK; - - ret = qca808x_ptp_buffer_status_reg_get(dev_id, phy_id, ®_val); - *value = reg_val.bf.rx_buffer_half_full; - return ret; -} - -sw_error_t -qca808x_ptp_buffer_status_reg_rx_buffer_half_full_set( - a_uint32_t dev_id, a_uint32_t phy_id, - a_uint32_t value) -{ - union ptp_buffer_status_reg_u reg_val; - sw_error_t ret = SW_OK; - - ret = qca808x_ptp_buffer_status_reg_get(dev_id, phy_id, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.rx_buffer_half_full = value; - ret = qca808x_ptp_buffer_status_reg_set(dev_id, phy_id, ®_val); - return ret; -} - -sw_error_t -qca808x_ptp_buffer_status_reg_rx_buffer_full_get( - a_uint32_t dev_id, a_uint32_t phy_id, - a_uint32_t *value) -{ - union ptp_buffer_status_reg_u reg_val; - sw_error_t ret = SW_OK; - - ret = qca808x_ptp_buffer_status_reg_get(dev_id, phy_id, ®_val); - *value = reg_val.bf.rx_buffer_full; - return ret; -} - -sw_error_t -qca808x_ptp_buffer_status_reg_rx_buffer_full_set( - a_uint32_t dev_id, a_uint32_t phy_id, - a_uint32_t value) -{ - union ptp_buffer_status_reg_u reg_val; - sw_error_t ret = SW_OK; - - ret = qca808x_ptp_buffer_status_reg_get(dev_id, phy_id, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.rx_buffer_full = value; - ret = qca808x_ptp_buffer_status_reg_set(dev_id, phy_id, ®_val); - return ret; -} - -sw_error_t -qca808x_ptp_buffer_status_reg_rx_buffer_data_present_get( - a_uint32_t dev_id, a_uint32_t phy_id, - a_uint32_t *value) -{ - union ptp_buffer_status_reg_u reg_val; - sw_error_t ret = SW_OK; - - ret = qca808x_ptp_buffer_status_reg_get(dev_id, phy_id, ®_val); - *value = reg_val.bf.rx_buffer_data_present; - return ret; -} - -sw_error_t -qca808x_ptp_buffer_status_reg_rx_buffer_data_present_set( - a_uint32_t dev_id, a_uint32_t phy_id, - a_uint32_t value) -{ - union ptp_buffer_status_reg_u reg_val; - sw_error_t ret = SW_OK; - - ret = qca808x_ptp_buffer_status_reg_get(dev_id, phy_id, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.rx_buffer_data_present = value; - ret = qca808x_ptp_buffer_status_reg_set(dev_id, phy_id, ®_val); - return ret; -} - -sw_error_t -qca808x_ptp_tx_buffer_write_reg_tx_buffer_get( - a_uint32_t dev_id, a_uint32_t phy_id, - a_uint32_t *value) -{ - union ptp_tx_buffer_write_reg_u reg_val; - sw_error_t ret = SW_OK; - - ret = qca808x_ptp_tx_buffer_write_reg_get(dev_id, phy_id, ®_val); - *value = reg_val.bf.tx_buffer; - return ret; -} - -sw_error_t -qca808x_ptp_tx_buffer_write_reg_tx_buffer_set( - a_uint32_t dev_id, a_uint32_t phy_id, - a_uint32_t value) -{ - union ptp_tx_buffer_write_reg_u reg_val; - sw_error_t ret = SW_OK; - - ret = qca808x_ptp_tx_buffer_write_reg_get(dev_id, phy_id, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.tx_buffer = value; - ret = qca808x_ptp_tx_buffer_write_reg_set(dev_id, phy_id, ®_val); - return ret; -} - -sw_error_t -qca808x_ptp_rx_buffer_read_reg_rx_data_get( - a_uint32_t dev_id, a_uint32_t phy_id, - a_uint32_t *value) -{ - union ptp_rx_buffer_read_reg_u reg_val; - sw_error_t ret = SW_OK; - - ret = qca808x_ptp_rx_buffer_read_reg_get(dev_id, phy_id, ®_val); - *value = reg_val.bf.rx_data; - return ret; -} - -sw_error_t -qca808x_ptp_rx_buffer_read_reg_rx_data_set( - a_uint32_t dev_id, a_uint32_t phy_id, - a_uint32_t value) -{ - union ptp_rx_buffer_read_reg_u reg_val; - sw_error_t ret = SW_OK; - - ret = qca808x_ptp_rx_buffer_read_reg_get(dev_id, phy_id, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.rx_data = value; - ret = qca808x_ptp_rx_buffer_read_reg_set(dev_id, phy_id, ®_val); - return ret; -} - -sw_error_t -qca808x_ptp_rx_buffer_read_reg_rx_buffer_almost_empty_get( - a_uint32_t dev_id, a_uint32_t phy_id, - a_uint32_t *value) -{ - union ptp_rx_buffer_read_reg_u reg_val; - sw_error_t ret = SW_OK; - - ret = qca808x_ptp_rx_buffer_read_reg_get(dev_id, phy_id, ®_val); - *value = reg_val.bf.rx_buffer_almost_empty; - return ret; -} - -sw_error_t -qca808x_ptp_rx_buffer_read_reg_rx_buffer_almost_empty_set( - a_uint32_t dev_id, a_uint32_t phy_id, - a_uint32_t value) -{ - union ptp_rx_buffer_read_reg_u reg_val; - sw_error_t ret = SW_OK; - - ret = qca808x_ptp_rx_buffer_read_reg_get(dev_id, phy_id, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.rx_buffer_almost_empty = value; - ret = qca808x_ptp_rx_buffer_read_reg_set(dev_id, phy_id, ®_val); - return ret; -} - -sw_error_t -qca808x_ptp_rx_buffer_read_reg_rx_buffer_almost_full_get( - a_uint32_t dev_id, a_uint32_t phy_id, - a_uint32_t *value) -{ - union ptp_rx_buffer_read_reg_u reg_val; - sw_error_t ret = SW_OK; - - ret = qca808x_ptp_rx_buffer_read_reg_get(dev_id, phy_id, ®_val); - *value = reg_val.bf.rx_buffer_almost_full; - return ret; -} - -sw_error_t -qca808x_ptp_rx_buffer_read_reg_rx_buffer_almost_full_set( - a_uint32_t dev_id, a_uint32_t phy_id, - a_uint32_t value) -{ - union ptp_rx_buffer_read_reg_u reg_val; - sw_error_t ret = SW_OK; - - ret = qca808x_ptp_rx_buffer_read_reg_get(dev_id, phy_id, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.rx_buffer_almost_full = value; - ret = qca808x_ptp_rx_buffer_read_reg_set(dev_id, phy_id, ®_val); - return ret; -} - -sw_error_t -qca808x_ptp_rx_buffer_read_reg_rx_buffer_half_full_get( - a_uint32_t dev_id, a_uint32_t phy_id, - a_uint32_t *value) -{ - union ptp_rx_buffer_read_reg_u reg_val; - sw_error_t ret = SW_OK; - - ret = qca808x_ptp_rx_buffer_read_reg_get(dev_id, phy_id, ®_val); - *value = reg_val.bf.rx_buffer_half_full; - return ret; -} - -sw_error_t -qca808x_ptp_rx_buffer_read_reg_rx_buffer_half_full_set( - a_uint32_t dev_id, a_uint32_t phy_id, - a_uint32_t value) -{ - union ptp_rx_buffer_read_reg_u reg_val; - sw_error_t ret = SW_OK; - - ret = qca808x_ptp_rx_buffer_read_reg_get(dev_id, phy_id, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.rx_buffer_half_full = value; - ret = qca808x_ptp_rx_buffer_read_reg_set(dev_id, phy_id, ®_val); - return ret; -} - -sw_error_t -qca808x_ptp_rx_buffer_read_reg_rx_buffer_full_get( - a_uint32_t dev_id, a_uint32_t phy_id, - a_uint32_t *value) -{ - union ptp_rx_buffer_read_reg_u reg_val; - sw_error_t ret = SW_OK; - - ret = qca808x_ptp_rx_buffer_read_reg_get(dev_id, phy_id, ®_val); - *value = reg_val.bf.rx_buffer_full; - return ret; -} - -sw_error_t -qca808x_ptp_rx_buffer_read_reg_rx_buffer_full_set( - a_uint32_t dev_id, a_uint32_t phy_id, - a_uint32_t value) -{ - union ptp_rx_buffer_read_reg_u reg_val; - sw_error_t ret = SW_OK; - - ret = qca808x_ptp_rx_buffer_read_reg_get(dev_id, phy_id, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.rx_buffer_full = value; - ret = qca808x_ptp_rx_buffer_read_reg_set(dev_id, phy_id, ®_val); - return ret; -} - -sw_error_t -qca808x_ptp_rx_buffer_read_reg_rx_buffer_data_present_get( - a_uint32_t dev_id, a_uint32_t phy_id, - a_uint32_t *value) -{ - union ptp_rx_buffer_read_reg_u reg_val; - sw_error_t ret = SW_OK; - - ret = qca808x_ptp_rx_buffer_read_reg_get(dev_id, phy_id, ®_val); - *value = reg_val.bf.rx_buffer_data_present; - return ret; -} - -sw_error_t -qca808x_ptp_rx_buffer_read_reg_rx_buffer_data_present_set( - a_uint32_t dev_id, a_uint32_t phy_id, - a_uint32_t value) -{ - union ptp_rx_buffer_read_reg_u reg_val; - sw_error_t ret = SW_OK; - - ret = qca808x_ptp_rx_buffer_read_reg_get(dev_id, phy_id, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.rx_buffer_data_present = value; - ret = qca808x_ptp_rx_buffer_read_reg_set(dev_id, phy_id, ®_val); - return ret; -} - -// -sw_error_t -qca808x_ptp_loc_mac_addr_0_reg_get( - a_uint32_t dev_id, a_uint32_t phy_id, - union ptp_loc_mac_addr_0_reg_u *value) -{ - return qca808x_phy_ptp_mmd_read( - dev_id, - phy_id, QCA808X_PHY_MMD3_NUM, PTP_LOC_MAC_ADDR_0_REG_ADDRESS, - &value->val); -} - -sw_error_t -qca808x_ptp_loc_mac_addr_0_reg_set( - a_uint32_t dev_id, a_uint32_t phy_id, - union ptp_loc_mac_addr_0_reg_u *value) -{ - return qca808x_phy_ptp_mmd_write( - dev_id, - phy_id, QCA808X_PHY_MMD3_NUM, PTP_LOC_MAC_ADDR_0_REG_ADDRESS, - value->val); -} - -sw_error_t -qca808x_ptp_loc_mac_addr_1_reg_get( - a_uint32_t dev_id, a_uint32_t phy_id, - union ptp_loc_mac_addr_1_reg_u *value) -{ - return qca808x_phy_ptp_mmd_read( - dev_id, - phy_id, QCA808X_PHY_MMD3_NUM, PTP_LOC_MAC_ADDR_1_REG_ADDRESS, - &value->val); -} - -sw_error_t -qca808x_ptp_loc_mac_addr_1_reg_set( - a_uint32_t dev_id, a_uint32_t phy_id, - union ptp_loc_mac_addr_1_reg_u *value) -{ - return qca808x_phy_ptp_mmd_write( - dev_id, - phy_id, QCA808X_PHY_MMD3_NUM, PTP_LOC_MAC_ADDR_1_REG_ADDRESS, - value->val); -} - -sw_error_t -qca808x_ptp_loc_mac_addr_2_reg_get( - a_uint32_t dev_id, a_uint32_t phy_id, - union ptp_loc_mac_addr_2_reg_u *value) -{ - return qca808x_phy_ptp_mmd_read( - dev_id, - phy_id, QCA808X_PHY_MMD3_NUM, PTP_LOC_MAC_ADDR_2_REG_ADDRESS, - &value->val); -} - -sw_error_t -qca808x_ptp_loc_mac_addr_2_reg_set( - a_uint32_t dev_id, a_uint32_t phy_id, - union ptp_loc_mac_addr_2_reg_u *value) -{ - return qca808x_phy_ptp_mmd_write( - dev_id, - phy_id, QCA808X_PHY_MMD3_NUM, PTP_LOC_MAC_ADDR_2_REG_ADDRESS, - value->val); -} - -sw_error_t -qca808x_ptp_loc_mac_addr_0_reg_mac_addr_get( - a_uint32_t dev_id, a_uint32_t phy_id, - a_uint32_t *value) -{ - union ptp_loc_mac_addr_0_reg_u reg_val; - sw_error_t ret = SW_OK; - - ret = qca808x_ptp_loc_mac_addr_0_reg_get(dev_id, phy_id, ®_val); - *value = reg_val.bf.mac_addr; - return ret; -} - -sw_error_t -qca808x_ptp_loc_mac_addr_0_reg_mac_addr_set( - a_uint32_t dev_id, a_uint32_t phy_id, - a_uint32_t value) -{ - union ptp_loc_mac_addr_0_reg_u reg_val; - sw_error_t ret = SW_OK; - - ret = qca808x_ptp_loc_mac_addr_0_reg_get(dev_id, phy_id, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.mac_addr = value; - ret = qca808x_ptp_loc_mac_addr_0_reg_set(dev_id, phy_id, ®_val); - return ret; -} - -sw_error_t -qca808x_ptp_loc_mac_addr_1_reg_mac_addr_get( - a_uint32_t dev_id, a_uint32_t phy_id, - a_uint32_t *value) -{ - union ptp_loc_mac_addr_1_reg_u reg_val; - sw_error_t ret = SW_OK; - - ret = qca808x_ptp_loc_mac_addr_1_reg_get(dev_id, phy_id, ®_val); - *value = reg_val.bf.mac_addr; - return ret; -} - -sw_error_t -qca808x_ptp_loc_mac_addr_1_reg_mac_addr_set( - a_uint32_t dev_id, a_uint32_t phy_id, - a_uint32_t value) -{ - union ptp_loc_mac_addr_1_reg_u reg_val; - sw_error_t ret = SW_OK; - - ret = qca808x_ptp_loc_mac_addr_1_reg_get(dev_id, phy_id, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.mac_addr = value; - ret = qca808x_ptp_loc_mac_addr_1_reg_set(dev_id, phy_id, ®_val); - return ret; -} - -sw_error_t -qca808x_ptp_loc_mac_addr_2_reg_mac_addr_get( - a_uint32_t dev_id, a_uint32_t phy_id, - a_uint32_t *value) -{ - union ptp_loc_mac_addr_2_reg_u reg_val; - sw_error_t ret = SW_OK; - - ret = qca808x_ptp_loc_mac_addr_2_reg_get(dev_id, phy_id, ®_val); - *value = reg_val.bf.mac_addr; - return ret; -} - -sw_error_t -qca808x_ptp_loc_mac_addr_2_reg_mac_addr_set( - a_uint32_t dev_id, a_uint32_t phy_id, - a_uint32_t value) -{ - union ptp_loc_mac_addr_2_reg_u reg_val; - sw_error_t ret = SW_OK; - - ret = qca808x_ptp_loc_mac_addr_2_reg_get(dev_id, phy_id, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.mac_addr = value; - ret = qca808x_ptp_loc_mac_addr_2_reg_set(dev_id, phy_id, ®_val); - return ret; -} - -sw_error_t -qca808x_ptp_link_delay_0_reg_get( - a_uint32_t dev_id, a_uint32_t phy_id, - union ptp_link_delay_0_reg_u *value) -{ - return qca808x_phy_ptp_mmd_read( - dev_id, - phy_id, QCA808X_PHY_MMD3_NUM, PTP_LINK_DELAY_0_REG_ADDRESS, - &value->val); -} - -sw_error_t -qca808x_ptp_link_delay_0_reg_set( - a_uint32_t dev_id, a_uint32_t phy_id, - union ptp_link_delay_0_reg_u *value) -{ - return qca808x_phy_ptp_mmd_write( - dev_id, - phy_id, QCA808X_PHY_MMD3_NUM, PTP_LINK_DELAY_0_REG_ADDRESS, - value->val); -} - -sw_error_t -qca808x_ptp_link_delay_1_reg_get( - a_uint32_t dev_id, a_uint32_t phy_id, - union ptp_link_delay_1_reg_u *value) -{ - return qca808x_phy_ptp_mmd_read( - dev_id, - phy_id, QCA808X_PHY_MMD3_NUM, PTP_LINK_DELAY_1_REG_ADDRESS, - &value->val); -} - -sw_error_t -qca808x_ptp_link_delay_1_reg_set( - a_uint32_t dev_id, a_uint32_t phy_id, - union ptp_link_delay_1_reg_u *value) -{ - return qca808x_phy_ptp_mmd_write( - dev_id, - phy_id, QCA808X_PHY_MMD3_NUM, PTP_LINK_DELAY_1_REG_ADDRESS, - value->val); -} - -sw_error_t -qca808x_ptp_link_delay_0_reg_link_delay_get( - a_uint32_t dev_id, a_uint32_t phy_id, - a_uint32_t *value) -{ - union ptp_link_delay_0_reg_u reg_val; - sw_error_t ret = SW_OK; - - ret = qca808x_ptp_link_delay_0_reg_get(dev_id, phy_id, ®_val); - *value = reg_val.bf.link_delay; - return ret; -} - -sw_error_t -qca808x_ptp_link_delay_0_reg_link_delay_set( - a_uint32_t dev_id, a_uint32_t phy_id, - a_uint32_t value) -{ - union ptp_link_delay_0_reg_u reg_val; - sw_error_t ret = SW_OK; - - ret = qca808x_ptp_link_delay_0_reg_get(dev_id, phy_id, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.link_delay = value; - ret = qca808x_ptp_link_delay_0_reg_set(dev_id, phy_id, ®_val); - return ret; -} - -sw_error_t -qca808x_ptp_link_delay_1_reg_link_delay_get( - a_uint32_t dev_id, a_uint32_t phy_id, - a_uint32_t *value) -{ - union ptp_link_delay_1_reg_u reg_val; - sw_error_t ret = SW_OK; - - ret = qca808x_ptp_link_delay_1_reg_get(dev_id, phy_id, ®_val); - *value = reg_val.bf.link_delay; - return ret; -} - -sw_error_t -qca808x_ptp_link_delay_1_reg_link_delay_set( - a_uint32_t dev_id, a_uint32_t phy_id, - a_uint32_t value) -{ - union ptp_link_delay_1_reg_u reg_val; - sw_error_t ret = SW_OK; - - ret = qca808x_ptp_link_delay_1_reg_get(dev_id, phy_id, ®_val); - if (SW_OK != ret) - return ret; - reg_val.bf.link_delay = value; - ret = qca808x_ptp_link_delay_1_reg_set(dev_id, phy_id, ®_val); - return ret; -} - -sw_error_t -qca808x_ptp_misc_control_reg_get( - a_uint32_t dev_id, a_uint32_t phy_id, - union ptp_misc_control_reg_u *value) -{ - return qca808x_phy_ptp_mmd_read( - dev_id, - phy_id, QCA808X_PHY_MMD3_NUM, PTP_MISC_CONTROL_REG_ADDRESS, - &value->val); -} - -sw_error_t -qca808x_ptp_misc_control_reg_set( - a_uint32_t dev_id, a_uint32_t phy_id, - union ptp_misc_control_reg_u *value) -{ - return qca808x_phy_ptp_mmd_write( - dev_id, - phy_id, QCA808X_PHY_MMD3_NUM, PTP_MISC_CONTROL_REG_ADDRESS, - value->val); -} - -sw_error_t -qca808x_ptp_ingress_asymmetry_0_reg_get( - a_uint32_t dev_id, a_uint32_t phy_id, - union ptp_ingress_asymmetry_0_reg_u *value) -{ - return qca808x_phy_ptp_mmd_read( - dev_id, - phy_id, QCA808X_PHY_MMD3_NUM, PTP_INGRESS_ASYMMETRY_0_REG_ADDRESS, - &value->val); -} - -sw_error_t -qca808x_ptp_ingress_asymmetry_0_reg_set( - a_uint32_t dev_id, a_uint32_t phy_id, - union ptp_ingress_asymmetry_0_reg_u *value) -{ - return qca808x_phy_ptp_mmd_write( - dev_id, - phy_id, QCA808X_PHY_MMD3_NUM, PTP_INGRESS_ASYMMETRY_0_REG_ADDRESS, - value->val); -} - -sw_error_t -qca808x_ptp_ingress_asymmetry_1_reg_get( - a_uint32_t dev_id, a_uint32_t phy_id, - union ptp_ingress_asymmetry_1_reg_u *value) -{ - return qca808x_phy_ptp_mmd_read( - dev_id, - phy_id, QCA808X_PHY_MMD3_NUM, PTP_INGRESS_ASYMMETRY_1_REG_ADDRESS, - &value->val); -} - -sw_error_t -qca808x_ptp_ingress_asymmetry_1_reg_set( - a_uint32_t dev_id, a_uint32_t phy_id, - union ptp_ingress_asymmetry_1_reg_u *value) -{ - return qca808x_phy_ptp_mmd_write( - dev_id, - phy_id, QCA808X_PHY_MMD3_NUM, PTP_INGRESS_ASYMMETRY_1_REG_ADDRESS, - value->val); -} - -sw_error_t -qca808x_ptp_egress_asymmetry_0_reg_get( - a_uint32_t dev_id, a_uint32_t phy_id, - union ptp_egress_asymmetry_0_reg_u *value) -{ - return qca808x_phy_ptp_mmd_read( - dev_id, - phy_id, QCA808X_PHY_MMD3_NUM, PTP_EGRESS_ASYMMETRY_0_REG_ADDRESS, - &value->val); -} - -sw_error_t -qca808x_ptp_egress_asymmetry_0_reg_set( - a_uint32_t dev_id, a_uint32_t phy_id, - union ptp_egress_asymmetry_0_reg_u *value) -{ - return qca808x_phy_ptp_mmd_write( - dev_id, - phy_id, QCA808X_PHY_MMD3_NUM, PTP_EGRESS_ASYMMETRY_0_REG_ADDRESS, - value->val); -} - -sw_error_t -qca808x_ptp_egress_asymmetry_1_reg_get( - a_uint32_t dev_id, a_uint32_t phy_id, - union ptp_egress_asymmetry_1_reg_u *value) -{ - return qca808x_phy_ptp_mmd_read( - dev_id, - phy_id, QCA808X_PHY_MMD3_NUM, PTP_EGRESS_ASYMMETRY_1_REG_ADDRESS, - &value->val); -} - -sw_error_t -qca808x_ptp_egress_asymmetry_1_reg_set( - a_uint32_t dev_id, a_uint32_t phy_id, - union ptp_egress_asymmetry_1_reg_u *value) -{ - return qca808x_phy_ptp_mmd_write( - dev_id, - phy_id, QCA808X_PHY_MMD3_NUM, PTP_EGRESS_ASYMMETRY_1_REG_ADDRESS, - value->val); -} - -sw_error_t -qca808x_ptp_backup_reg_get( - a_uint32_t dev_id, a_uint32_t phy_id, - union ptp_backup_reg_u *value) -{ - return qca808x_phy_ptp_mmd_read( - dev_id, - phy_id, QCA808X_PHY_MMD3_NUM, PTP_BACKUP_REG_ADDRESS, - &value->val); -} - -sw_error_t -qca808x_ptp_backup_reg_set( - a_uint32_t dev_id, a_uint32_t phy_id, - union ptp_backup_reg_u *value) -{ - return qca808x_phy_ptp_mmd_write( - dev_id, - phy_id, QCA808X_PHY_MMD3_NUM, PTP_BACKUP_REG_ADDRESS, - value->val); -} - diff --git a/feeds/ipq807x/qca-ssdk/src/src/hsl/phy/sfp_phy.c b/feeds/ipq807x/qca-ssdk/src/src/hsl/phy/sfp_phy.c deleted file mode 100755 index 66bb1acd6..000000000 --- a/feeds/ipq807x/qca-ssdk/src/src/hsl/phy/sfp_phy.c +++ /dev/null @@ -1,253 +0,0 @@ -/* - * Copyright (c) 2018, 2020, The Linux Foundation. All rights reserved. - * Permission to use, copy, modify, and/or distribute this software for - * any purpose with or without fee is hereby granted, provided that the - * above copyright notice and this permission notice appear in all copies. - * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES - * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR - * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES - * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN - * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT - * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. - */ - -#include "sw.h" -#include "fal_port_ctrl.h" -#include "adpt.h" -#include "hsl_api.h" -#include "hsl.h" -#include "sfp_phy.h" -#include "aos_timer.h" -#include "hsl_phy.h" -#include -#include -#include -#include -#include "ssdk_plat.h" -#include "ssdk_phy_i2c.h" - -/****************************************************************************** -* -* sfp_phy_init - -* -*/ -#if (LINUX_VERSION_CODE < KERNEL_VERSION (5, 0, 0)) -#define SFP_PHY_FEATURES (SUPPORTED_FIBRE | \ - SUPPORTED_1000baseT_Full | \ - SUPPORTED_10000baseT_Full | \ - SUPPORTED_Pause | \ - SUPPORTED_Asym_Pause) -#else -__ETHTOOL_DECLARE_LINK_MODE_MASK(SFP_PHY_FEATURES) __ro_after_init; -#endif - -static int -sfp_phy_probe(struct phy_device *pdev) -{ - SSDK_INFO("sfp phy is probed!\n"); - return 0; -} - -static void -sfp_phy_remove(struct phy_device *pdev) -{ - return; -} - -static int -sfp_phy_config_aneg(struct phy_device *pdev) -{ - - return 0; -} - -static int -sfp_phy_aneg_done(struct phy_device *pdev) -{ - - return SFP_ANEG_DONE; -} - -static int -sfp_read_status(struct phy_device *pdev) -{ - sw_error_t rv; - fal_port_t port; - a_uint32_t addr; - struct qca_phy_priv *priv = pdev->priv; - struct port_phy_status phy_status; - adpt_api_t *p_api; - -#if (LINUX_VERSION_CODE >= KERNEL_VERSION(4,9,0)) - addr = pdev->mdio.addr; -#else - addr = pdev->addr; -#endif - port = qca_ssdk_phy_addr_to_port(priv->device_id, addr); - SW_RTN_ON_NULL(p_api = adpt_api_ptr_get(priv->device_id)); - rv = p_api->adpt_port_phy_status_get(priv->device_id, port, &phy_status); - pdev->link = phy_status.link_status; - pdev->speed = phy_status.speed; - pdev->duplex = phy_status.duplex; - - return rv; -} - -static struct phy_driver sfp_phy_driver = { - .name = "QCA SFP", - .phy_id = SFP_PHY, - .phy_id_mask = SFP_PHY_MASK, - .probe = sfp_phy_probe, - .remove = sfp_phy_remove, - .config_aneg = sfp_phy_config_aneg, - .aneg_done = sfp_phy_aneg_done, - .read_status = sfp_read_status, - .features = SFP_PHY_FEATURES, -#if (LINUX_VERSION_CODE >= KERNEL_VERSION(4,9,0)) - .mdiodrv.driver = { .owner = THIS_MODULE }, -#else - .driver = { .owner = THIS_MODULE }, -#endif -}; - -int sfp_phy_device_setup(a_uint32_t dev_id, a_uint32_t port, a_uint32_t phy_id) -{ -#if (LINUX_VERSION_CODE >= KERNEL_VERSION(4,4,0)) - struct phy_device *phydev; - struct qca_phy_priv *priv; - a_uint32_t addr = 0; - struct mii_bus *bus; - - priv = ssdk_phy_priv_data_get(dev_id); - /*create phy device*/ -#if defined(IN_PHY_I2C_MODE) - if (hsl_port_phy_access_type_get(dev_id, port) == PHY_I2C_ACCESS) { - addr = qca_ssdk_port_to_phy_mdio_fake_addr(dev_id, port); - } else -#endif - { - addr = qca_ssdk_port_to_phy_addr(dev_id, port); - } - bus = ssdk_miibus_get_by_device(dev_id); - phydev = phy_device_create(bus, addr, phy_id, false, NULL); - if (IS_ERR(phydev) || phydev == NULL) { - SSDK_ERROR("Failed to create phy device!\n"); - return SW_NOT_SUPPORTED; - } - /*register phy device*/ - phy_device_register(phydev); - - phydev->priv = priv; -#endif - return 0; -} - -void sfp_phy_device_remove(a_uint32_t dev_id, a_uint32_t port) -{ -#if (LINUX_VERSION_CODE >= KERNEL_VERSION(4,4,0)) - struct phy_device *phydev = NULL; - a_uint32_t addr = 0; - struct mii_bus *bus; - - bus = ssdk_miibus_get_by_device(dev_id); -#if defined(IN_PHY_I2C_MODE) - if (hsl_port_phy_access_type_get(dev_id, port) == PHY_I2C_ACCESS) { - addr = qca_ssdk_port_to_phy_mdio_fake_addr(dev_id, port); - } else -#endif - { - addr = qca_ssdk_port_to_phy_addr(dev_id, port); - } - - if (addr < PHY_MAX_ADDR) -#if (LINUX_VERSION_CODE >= KERNEL_VERSION(4, 9, 0)) - if (bus->mdio_map[addr]) - phydev = to_phy_device(&bus->mdio_map[addr]->dev); -#else - phydev = bus->phy_map[addr]; -#endif - if (phydev) - phy_device_remove(phydev); -#endif -} - -#if (LINUX_VERSION_CODE >= KERNEL_VERSION(5, 0, 0)) -static void sfp_features_init(void) -{ - const int features[] = { - ETHTOOL_LINK_MODE_FIBRE_BIT, - ETHTOOL_LINK_MODE_1000baseT_Full_BIT, - ETHTOOL_LINK_MODE_10000baseT_Full_BIT, - ETHTOOL_LINK_MODE_Pause_BIT, - ETHTOOL_LINK_MODE_Asym_Pause_BIT, - }; - - linkmode_set_bit_array(features, - ARRAY_SIZE(features), - SFP_PHY_FEATURES); -} -#endif - -int sfp_phy_init(a_uint32_t dev_id, a_uint32_t port_bmp) -{ - a_uint32_t port_id = 0; - - SSDK_INFO("sfp phy init for port 0x%x!\n", port_bmp); - - for (port_id = 0; port_id < SW_MAX_NR_PORT; port_id ++) { - if (port_bmp & (0x1 << port_id)) { - sfp_phy_device_setup(dev_id, port_id, SFP_PHY); - } - } -#if (LINUX_VERSION_CODE >= KERNEL_VERSION(5, 0, 0)) - sfp_features_init(); -#endif -#if (LINUX_VERSION_CODE >= KERNEL_VERSION(4,9,0)) - phy_driver_register(&sfp_phy_driver, THIS_MODULE); -#else - phy_driver_register(&sfp_phy_driver); -#endif - return 0; -} - -void sfp_phy_exit(a_uint32_t dev_id, a_uint32_t port_bmp) -{ - a_uint32_t port_id = 0; - - phy_driver_unregister(&sfp_phy_driver); - - for (port_id = 0; port_id < SW_MAX_NR_PORT; port_id ++) { - if (port_bmp & (0x1 << port_id)) { - sfp_phy_device_remove(dev_id, port_id); - } - } - -} -sw_error_t sfp_phy_interface_get_mode_status(a_uint32_t dev_id, - a_uint32_t phy_id, fal_port_interface_mode_t *interface_mode_status) -{ - sw_error_t rv = SW_OK; - a_uint16_t reg_data = 0, sfp_speed = 0; - - rv = qca_phy_i2c_mii_read(dev_id, SFP_E2PROM_ADDR, SFP_SPEED_ADDR, - ®_data); - SW_RTN_ON_ERROR(rv); - sfp_speed = SFP_TO_SFP_SPEED(reg_data); - SSDK_DEBUG("sfp_speed:%d\n", sfp_speed); - if(sfp_speed >= SFP_SPEED_1000M && - sfp_speed < SFP_SPEED_2500M) - { - *interface_mode_status = PORT_SGMII_FIBER; - } - else if(sfp_speed >= SFP_SPEED_10000M) - { - *interface_mode_status = PORT_10GBASE_R; - } - else - { - return SW_NOT_SUPPORTED; - } - - return rv; -} diff --git a/feeds/ipq807x/qca-ssdk/src/src/hsl/scomphy/Makefile b/feeds/ipq807x/qca-ssdk/src/src/hsl/scomphy/Makefile deleted file mode 100755 index 0e6e147da..000000000 --- a/feeds/ipq807x/qca-ssdk/src/src/hsl/scomphy/Makefile +++ /dev/null @@ -1,28 +0,0 @@ -LOC_DIR=src/hsl/scomphy -LIB=HSL - -include $(PRJ_PATH)/make/config.mk - -SRC_LIST=scomphy_reg_access.c scomphy_init.c - -ifeq (TRUE, $(IN_PORTCONTROL)) - SRC_LIST += scomphy_port_ctrl.c -endif - -ifeq (linux, $(OS)) - ifeq (KSLIB, $(MODULE_TYPE)) - ifneq (TRUE, $(KERNEL_MODE)) - SRC_LIST=scomphy_reg_access.c scomphy_init.c - endif - endif -endif - -ifeq (, $(findstring SCOMPHY, $(SUPPORT_CHIP))) - SRC_LIST= -endif - -include $(PRJ_PATH)/make/components.mk -include $(PRJ_PATH)/make/defs.mk -include $(PRJ_PATH)/make/target.mk - -all: dep obj diff --git a/feeds/ipq807x/qca-ssdk/src/src/hsl/scomphy/scomphy_init.c b/feeds/ipq807x/qca-ssdk/src/src/hsl/scomphy/scomphy_init.c deleted file mode 100755 index 7f82807d8..000000000 --- a/feeds/ipq807x/qca-ssdk/src/src/hsl/scomphy/scomphy_init.c +++ /dev/null @@ -1,196 +0,0 @@ -/* - * Copyright (c) 2017-2019, The Linux Foundation. All rights reserved. - * Permission to use, copy, modify, and/or distribute this software for - * any purpose with or without fee is hereby granted, provided that the - * above copyright notice and this permission notice appear in all copies. - * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES - * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR - * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES - * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN - * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT - * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. - */ - - -/** - * @defgroup scomphy_init SCOMPHY_INIT - * @{ - */ -#include "sw.h" -#include "hsl.h" -#include "hsl_dev.h" -#include "hsl_phy.h" -#include "hsl_port_prop.h" -#include "scomphy_port_ctrl.h" -#include "scomphy_reg_access.h" -#include "scomphy_init.h" - -static ssdk_init_cfg * scomphy_cfg[SW_MAX_NR_DEV] = { 0 }; - -static sw_error_t -scomphy_portproperty_init(a_uint32_t dev_id, hsl_init_mode mode) -{ - hsl_port_prop_t p_type; - hsl_dev_t *pdev = NULL; - fal_port_t port_id; - a_uint32_t port_bmp = qca_ssdk_port_bmp_get(dev_id); - - pdev = hsl_dev_ptr_get(dev_id); - if (pdev == NULL) - return SW_NOT_INITIALIZED; - - /* for port property set, SSDK should not generate some limitations */ - for (port_id = 1; port_id < SW_MAX_NR_PORT; port_id++) - { - if((1 << port_id) & port_bmp) - { - hsl_port_prop_portmap_set(dev_id, port_id); - - for (p_type = HSL_PP_PHY; p_type < HSL_PP_BUTT; p_type++) - { - SW_RTN_ON_ERROR(hsl_port_prop_set(dev_id, port_id, p_type)); - } - } - } - - return SW_OK; -} - -static sw_error_t -scomphy_dev_init(a_uint32_t dev_id, hsl_init_mode cpu_mode) -{ - sw_error_t rv = SW_OK; - hsl_dev_t *pdev = NULL; - a_uint8_t nr_ports = 0; - a_uint32_t port_bmp = qca_ssdk_port_bmp_get(dev_id); - - pdev = hsl_dev_ptr_get(dev_id); - if (pdev == NULL) - return SW_NOT_INITIALIZED; - - while (port_bmp) { - if (port_bmp & 1) - nr_ports++; - port_bmp >>= 1; - } - - pdev->nr_ports = nr_ports; - pdev->nr_phy = nr_ports; - pdev->cpu_port_nr = 0; - pdev->hw_vlan_query = A_TRUE; - pdev->cpu_mode = cpu_mode; - - return rv; -} - - -static sw_error_t -_scomphy_reset(a_uint32_t dev_id) -{ - sw_error_t rv = SW_OK; - a_uint32_t port_bmp = 0; - a_uint8_t port_id = 0; - - HSL_DEV_ID_CHECK(dev_id); - - port_bmp = qca_ssdk_port_bmp_get(dev_id); - while (port_bmp) { - if (port_bmp & 1) - SW_RTN_ON_ERROR(scomphy_port_reset(dev_id, port_id)); - - port_bmp >>= 1; - port_id++; - } - - return rv; -} - -sw_error_t -scomphy_cleanup(a_uint32_t dev_id) -{ - sw_error_t rv = SW_OK; - - if (scomphy_cfg[dev_id]) - { - SW_RTN_ON_ERROR(hsl_port_prop_cleanup_by_dev(dev_id)); - - aos_mem_free(scomphy_cfg[dev_id]); - scomphy_cfg[dev_id] = NULL; - } - - return rv; -} - -/** - * @brief reset hsl layer. - * @details Comments: - * This operation will reset hsl layer - * @param[in] dev_id device id - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -scomphy_reset(a_uint32_t dev_id) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _scomphy_reset(dev_id); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Init hsl layer. - * @details Comments: - * This operation will init hsl layer and hsl layer - * @param[in] dev_id device id - * @param[in] cfg configuration for initialization - * @return SW_OK or error code - */ -sw_error_t -scomphy_init(a_uint32_t dev_id, ssdk_init_cfg *cfg) -{ - HSL_DEV_ID_CHECK(dev_id); - - if (NULL == scomphy_cfg[dev_id]) - { - scomphy_cfg[dev_id] = aos_mem_alloc(sizeof (ssdk_init_cfg)); - } - - if (NULL == scomphy_cfg[dev_id]) - { - return SW_OUT_OF_MEM; - } - - aos_mem_copy(scomphy_cfg[dev_id], cfg, sizeof (ssdk_init_cfg)); - - SW_RTN_ON_ERROR(scomphy_reg_access_init(dev_id, cfg)); - - SW_RTN_ON_ERROR(scomphy_dev_init(dev_id, cfg->cpu_mode)); - - { - sw_error_t rv; - - SW_RTN_ON_ERROR(hsl_port_prop_init(dev_id)); - SW_RTN_ON_ERROR(hsl_port_prop_init_by_dev(dev_id)); - SW_RTN_ON_ERROR(scomphy_portproperty_init(dev_id, cfg->cpu_mode)); - - SCOMPHY_PORT_CTRL_INIT(rv, dev_id); - - { - hsl_api_t *p_api; - - SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id)); - p_api->dev_reset = scomphy_reset; - p_api->dev_clean = scomphy_cleanup; - } - } - - return SW_OK; -} - -/** - * @} - */ - diff --git a/feeds/ipq807x/qca-ssdk/src/src/hsl/scomphy/scomphy_port_ctrl.c b/feeds/ipq807x/qca-ssdk/src/src/hsl/scomphy/scomphy_port_ctrl.c deleted file mode 100644 index e55dcaa97..000000000 --- a/feeds/ipq807x/qca-ssdk/src/src/hsl/scomphy/scomphy_port_ctrl.c +++ /dev/null @@ -1,2078 +0,0 @@ -/* - * Copyright (c) 2017-2018, The Linux Foundation. All rights reserved. - * Permission to use, copy, modify, and/or distribute this software for - * any purpose with or without fee is hereby granted, provided that the - * above copyright notice and this permission notice appear in all copies. - * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES - * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR - * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES - * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN - * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT - * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. - */ - -/*qca808x_start*/ -/** - * @defgroup scomphy_port_ctrl SCOMPHY_PORT_CONTROL - * @{ - */ -#include "sw.h" -#include "hsl.h" -#include "hsl_dev.h" -#include "hsl_port_prop.h" -#include "scomphy_port_ctrl.h" -#include "hsl_phy.h" - -static sw_error_t -_scomphy_port_duplex_set (a_uint32_t dev_id, fal_port_t port_id, - fal_port_duplex_t duplex) -{ - sw_error_t rv; - a_uint32_t phy_id; - hsl_phy_ops_t *phy_drv; - - HSL_DEV_ID_CHECK (dev_id); - - if (A_TRUE != hsl_port_prop_check (dev_id, port_id, HSL_PP_PHY)) - { - return SW_BAD_PARAM; - } - - SW_RTN_ON_NULL (phy_drv = hsl_phy_api_ops_get (dev_id, port_id)); - if (NULL == phy_drv->phy_duplex_set) - return SW_NOT_SUPPORTED; - - if (FAL_DUPLEX_BUTT <= duplex) - { - return SW_BAD_PARAM; - } - rv = hsl_port_prop_get_phyid (dev_id, port_id, &phy_id); - SW_RTN_ON_ERROR (rv); - - rv = phy_drv->phy_duplex_set (dev_id, phy_id, duplex); - SW_RTN_ON_ERROR (rv); - return rv; -} - -static sw_error_t -_scomphy_port_duplex_get (a_uint32_t dev_id, fal_port_t port_id, - fal_port_duplex_t * pduplex) -{ - sw_error_t rv = SW_OK; - a_uint32_t phy_id; - hsl_phy_ops_t *phy_drv; - - HSL_DEV_ID_CHECK (dev_id); - - if (A_TRUE != hsl_port_prop_check (dev_id, port_id, HSL_PP_PHY)) - { - return SW_BAD_PARAM; - } - - SW_RTN_ON_NULL (phy_drv = hsl_phy_api_ops_get (dev_id, port_id)); - if (NULL == phy_drv->phy_duplex_get) - return SW_NOT_SUPPORTED; - - rv = hsl_port_prop_get_phyid (dev_id, port_id, &phy_id); - SW_RTN_ON_ERROR (rv); - - rv = phy_drv->phy_duplex_get (dev_id, phy_id, pduplex); - SW_RTN_ON_ERROR (rv); - - return rv; -} - -static sw_error_t -_scomphy_port_speed_set (a_uint32_t dev_id, fal_port_t port_id, - fal_port_speed_t speed) -{ - sw_error_t rv; - a_uint32_t phy_id; - hsl_phy_ops_t *phy_drv; - - HSL_DEV_ID_CHECK (dev_id); - - if (A_TRUE != hsl_port_prop_check (dev_id, port_id, HSL_PP_PHY)) - { - return SW_BAD_PARAM; - } - - SW_RTN_ON_NULL (phy_drv = hsl_phy_api_ops_get (dev_id, port_id)); - if (NULL == phy_drv->phy_speed_set) - return SW_NOT_SUPPORTED; - - rv = hsl_port_prop_get_phyid (dev_id, port_id, &phy_id); - SW_RTN_ON_ERROR (rv); - - rv = phy_drv->phy_speed_set (dev_id, phy_id, speed); - SW_RTN_ON_ERROR (rv); - return rv; -} - -static sw_error_t -_scomphy_port_speed_get (a_uint32_t dev_id, fal_port_t port_id, - fal_port_speed_t * pspeed) -{ - sw_error_t rv = SW_OK; - a_uint32_t phy_id; - hsl_phy_ops_t *phy_drv; - - HSL_DEV_ID_CHECK (dev_id); - - if (A_TRUE != hsl_port_prop_check (dev_id, port_id, HSL_PP_PHY)) - { - return SW_BAD_PARAM; - } - - SW_RTN_ON_NULL (phy_drv = hsl_phy_api_ops_get (dev_id, port_id)); - if (NULL == phy_drv->phy_speed_get) - return SW_NOT_SUPPORTED; - - rv = hsl_port_prop_get_phyid (dev_id, port_id, &phy_id); - SW_RTN_ON_ERROR (rv); - rv = phy_drv->phy_speed_get (dev_id, phy_id, pspeed); - SW_RTN_ON_ERROR (rv); - - return rv; -} - -static sw_error_t -_scomphy_port_autoneg_status_get (a_uint32_t dev_id, fal_port_t port_id, - a_bool_t * status) -{ - a_uint32_t phy_id; - sw_error_t rv; - hsl_phy_ops_t *phy_drv; - - HSL_DEV_ID_CHECK (dev_id); - - if (A_TRUE != hsl_port_prop_check (dev_id, port_id, HSL_PP_PHY)) - { - return SW_BAD_PARAM; - } - - SW_RTN_ON_NULL (phy_drv = hsl_phy_api_ops_get (dev_id, port_id)); - if (NULL == phy_drv->phy_autoneg_status_get) - return SW_NOT_SUPPORTED; - - rv = hsl_port_prop_get_phyid (dev_id, port_id, &phy_id); - SW_RTN_ON_ERROR (rv); - - *status = phy_drv->phy_autoneg_status_get (dev_id, phy_id); - - return SW_OK; -} - -static sw_error_t -_scomphy_port_autoneg_enable (a_uint32_t dev_id, fal_port_t port_id) -{ - sw_error_t rv; - a_uint32_t phy_id; - hsl_phy_ops_t *phy_drv; - - HSL_DEV_ID_CHECK (dev_id); - - if (A_TRUE != hsl_port_prop_check (dev_id, port_id, HSL_PP_PHY)) - { - return SW_BAD_PARAM; - } - - SW_RTN_ON_NULL (phy_drv = hsl_phy_api_ops_get (dev_id, port_id)); - if (NULL == phy_drv->phy_autoneg_enable_set) - return SW_NOT_SUPPORTED; - - rv = hsl_port_prop_get_phyid (dev_id, port_id, &phy_id); - SW_RTN_ON_ERROR (rv); - - rv = phy_drv->phy_autoneg_enable_set (dev_id, phy_id); - return rv; -} - -static sw_error_t -_scomphy_port_autoneg_restart (a_uint32_t dev_id, fal_port_t port_id) -{ - sw_error_t rv; - a_uint32_t phy_id; - hsl_phy_ops_t *phy_drv; - - HSL_DEV_ID_CHECK (dev_id); - - if (A_TRUE != hsl_port_prop_check (dev_id, port_id, HSL_PP_PHY)) - { - return SW_BAD_PARAM; - } - - SW_RTN_ON_NULL (phy_drv = hsl_phy_api_ops_get (dev_id, port_id)); - if (NULL == phy_drv->phy_restart_autoneg) - return SW_NOT_SUPPORTED; - - rv = hsl_port_prop_get_phyid (dev_id, port_id, &phy_id); - SW_RTN_ON_ERROR (rv); - - rv = phy_drv->phy_restart_autoneg (dev_id, phy_id); - return rv; -} - -static sw_error_t -_scomphy_port_autoneg_adv_set (a_uint32_t dev_id, fal_port_t port_id, - a_uint32_t autoadv) -{ - sw_error_t rv; - a_uint32_t phy_id; - hsl_phy_ops_t *phy_drv; - - HSL_DEV_ID_CHECK (dev_id); - - if (A_TRUE != hsl_port_prop_check (dev_id, port_id, HSL_PP_PHY)) - { - return SW_BAD_PARAM; - } - - SW_RTN_ON_NULL (phy_drv = hsl_phy_api_ops_get (dev_id, port_id)); - if (NULL == phy_drv->phy_autoneg_adv_set) - return SW_NOT_SUPPORTED; - - rv = hsl_port_prop_get_phyid (dev_id, port_id, &phy_id); - SW_RTN_ON_ERROR (rv); - - rv = phy_drv->phy_autoneg_adv_set (dev_id, phy_id, autoadv); - SW_RTN_ON_ERROR (rv); - - return SW_OK; -} - -static sw_error_t -_scomphy_port_autoneg_adv_get (a_uint32_t dev_id, fal_port_t port_id, - a_uint32_t * autoadv) -{ - sw_error_t rv; - a_uint32_t phy_id; - hsl_phy_ops_t *phy_drv; - - HSL_DEV_ID_CHECK (dev_id); - - if (A_TRUE != hsl_port_prop_check (dev_id, port_id, HSL_PP_PHY)) - { - return SW_BAD_PARAM; - } - - SW_RTN_ON_NULL (phy_drv = hsl_phy_api_ops_get (dev_id, port_id)); - if (NULL == phy_drv->phy_autoneg_adv_get) - return SW_NOT_SUPPORTED; - - rv = hsl_port_prop_get_phyid (dev_id, port_id, &phy_id); - SW_RTN_ON_ERROR (rv); - - *autoadv = 0; - rv = phy_drv->phy_autoneg_adv_get (dev_id, phy_id, autoadv); - SW_RTN_ON_ERROR (rv); - - return SW_OK; -} - -#ifndef IN_PORTCONTROL_MINI -static sw_error_t -_scomphy_port_powersave_set (a_uint32_t dev_id, fal_port_t port_id, - a_bool_t enable) -{ - sw_error_t rv; - a_uint32_t phy_id = 0; - hsl_phy_ops_t *phy_drv; - - HSL_DEV_ID_CHECK (dev_id); - - if (A_TRUE != hsl_port_prop_check (dev_id, port_id, HSL_PP_PHY)) - { - return SW_BAD_PARAM; - } - - SW_RTN_ON_NULL (phy_drv = hsl_phy_api_ops_get (dev_id, port_id)); - if (NULL == phy_drv->phy_powersave_set) - return SW_NOT_SUPPORTED; - - rv = hsl_port_prop_get_phyid (dev_id, port_id, &phy_id); - SW_RTN_ON_ERROR (rv); - - rv = phy_drv->phy_powersave_set (dev_id, phy_id, enable); - - return rv; -} - -static sw_error_t -_scomphy_port_powersave_get (a_uint32_t dev_id, fal_port_t port_id, - a_bool_t * enable) -{ - sw_error_t rv; - a_uint32_t phy_id = 0; - hsl_phy_ops_t *phy_drv; - - HSL_DEV_ID_CHECK (dev_id); - - if (A_TRUE != hsl_port_prop_check (dev_id, port_id, HSL_PP_PHY)) - { - return SW_BAD_PARAM; - } - - SW_RTN_ON_NULL (phy_drv = hsl_phy_api_ops_get (dev_id, port_id)); - if (NULL == phy_drv->phy_powersave_get) - return SW_NOT_SUPPORTED; - - rv = hsl_port_prop_get_phyid (dev_id, port_id, &phy_id); - SW_RTN_ON_ERROR (rv); - - rv = phy_drv->phy_powersave_get (dev_id, phy_id, enable); - - return rv; -} - -static sw_error_t -_scomphy_port_hibernate_set (a_uint32_t dev_id, fal_port_t port_id, - a_bool_t enable) -{ - sw_error_t rv; - a_uint32_t phy_id = 0; - hsl_phy_ops_t *phy_drv; - - HSL_DEV_ID_CHECK (dev_id); - - if (A_TRUE != hsl_port_prop_check (dev_id, port_id, HSL_PP_PHY)) - { - return SW_BAD_PARAM; - } - - SW_RTN_ON_NULL (phy_drv = hsl_phy_api_ops_get (dev_id, port_id)); - if (NULL == phy_drv->phy_hibernation_set) - return SW_NOT_SUPPORTED; - - rv = hsl_port_prop_get_phyid (dev_id, port_id, &phy_id); - SW_RTN_ON_ERROR (rv); - - rv = phy_drv->phy_hibernation_set (dev_id, phy_id, enable); - - return rv; -} - -static sw_error_t -_scomphy_port_hibernate_get (a_uint32_t dev_id, fal_port_t port_id, - a_bool_t * enable) -{ - sw_error_t rv; - a_uint32_t phy_id = 0; - hsl_phy_ops_t *phy_drv; - - HSL_DEV_ID_CHECK (dev_id); - - if (A_TRUE != hsl_port_prop_check (dev_id, port_id, HSL_PP_PHY)) - { - return SW_BAD_PARAM; - } - - SW_RTN_ON_NULL (phy_drv = hsl_phy_api_ops_get (dev_id, port_id)); - if (NULL == phy_drv->phy_hibernation_get) - return SW_NOT_SUPPORTED; - - rv = hsl_port_prop_get_phyid (dev_id, port_id, &phy_id); - SW_RTN_ON_ERROR (rv); - - rv = phy_drv->phy_hibernation_get (dev_id, phy_id, enable); - - return rv; -} - -static sw_error_t -_scomphy_port_cdt (a_uint32_t dev_id, fal_port_t port_id, a_uint32_t mdi_pair, - fal_cable_status_t * cable_status, a_uint32_t * cable_len) -{ - sw_error_t rv; - a_uint32_t phy_id = 0; - hsl_phy_ops_t *phy_drv; - - HSL_DEV_ID_CHECK (dev_id); - - if (A_TRUE != hsl_port_prop_check (dev_id, port_id, HSL_PP_PHY)) - { - return SW_BAD_PARAM; - } - - SW_RTN_ON_NULL (phy_drv = hsl_phy_api_ops_get (dev_id, port_id)); - if (NULL == phy_drv->phy_cdt) - return SW_NOT_SUPPORTED; - - rv = hsl_port_prop_get_phyid (dev_id, port_id, &phy_id); - SW_RTN_ON_ERROR (rv); - - rv = phy_drv->phy_cdt (dev_id, phy_id, mdi_pair, cable_status, cable_len); - - return rv; -} - -static sw_error_t -_scomphy_port_8023az_set (a_uint32_t dev_id, fal_port_t port_id, a_bool_t enable) -{ - sw_error_t rv; - a_uint32_t phy_id = 0; - hsl_phy_ops_t *phy_drv; - - HSL_DEV_ID_CHECK (dev_id); - if (A_TRUE != hsl_port_prop_check (dev_id, port_id, HSL_PP_PHY)) - { - return SW_BAD_PARAM; - } - - SW_RTN_ON_NULL (phy_drv = hsl_phy_api_ops_get (dev_id, port_id)); - if (NULL == phy_drv->phy_8023az_set) - return SW_NOT_SUPPORTED; - - rv = hsl_port_prop_get_phyid (dev_id, port_id, &phy_id); - SW_RTN_ON_ERROR (rv); - - rv = phy_drv->phy_8023az_set (dev_id, phy_id, enable); - - return rv; -} - -static sw_error_t -_scomphy_port_8023az_get (a_uint32_t dev_id, fal_port_t port_id, - a_bool_t * enable) -{ - sw_error_t rv; - a_uint32_t phy_id = 0; - hsl_phy_ops_t *phy_drv; - - HSL_DEV_ID_CHECK (dev_id); - - if (A_TRUE != hsl_port_prop_check (dev_id, port_id, HSL_PP_PHY)) - { - return SW_BAD_PARAM; - } - - SW_RTN_ON_NULL (phy_drv = hsl_phy_api_ops_get (dev_id, port_id)); - if (NULL == phy_drv->phy_8023az_get) - return SW_NOT_SUPPORTED; - - rv = hsl_port_prop_get_phyid (dev_id, port_id, &phy_id); - SW_RTN_ON_ERROR (rv); - - rv = phy_drv->phy_8023az_get (dev_id, phy_id, enable); - - return rv; -} - -static sw_error_t -_scomphy_port_mdix_set (a_uint32_t dev_id, fal_port_t port_id, - fal_port_mdix_mode_t mode) -{ - sw_error_t rv; - a_uint32_t phy_id = 0; - hsl_phy_ops_t *phy_drv; - - HSL_DEV_ID_CHECK (dev_id); - if (A_TRUE != hsl_port_prop_check (dev_id, port_id, HSL_PP_PHY)) - { - return SW_BAD_PARAM; - } - - SW_RTN_ON_NULL (phy_drv = hsl_phy_api_ops_get (dev_id, port_id)); - if (NULL == phy_drv->phy_mdix_set) - return SW_NOT_SUPPORTED; - - rv = hsl_port_prop_get_phyid (dev_id, port_id, &phy_id); - SW_RTN_ON_ERROR (rv); - - rv = phy_drv->phy_mdix_set (dev_id, phy_id, mode); - - return rv; -} - -static sw_error_t -_scomphy_port_mdix_get (a_uint32_t dev_id, fal_port_t port_id, - fal_port_mdix_mode_t * mode) -{ - sw_error_t rv; - a_uint32_t phy_id = 0; - hsl_phy_ops_t *phy_drv; - - HSL_DEV_ID_CHECK (dev_id); - - if (A_TRUE != hsl_port_prop_check (dev_id, port_id, HSL_PP_PHY)) - { - return SW_BAD_PARAM; - } - - SW_RTN_ON_NULL (phy_drv = hsl_phy_api_ops_get (dev_id, port_id)); - if (NULL == phy_drv->phy_mdix_get) - return SW_NOT_SUPPORTED; - - rv = hsl_port_prop_get_phyid (dev_id, port_id, &phy_id); - SW_RTN_ON_ERROR (rv); - - rv = phy_drv->phy_mdix_get (dev_id, phy_id, mode); - - return rv; -} - -static sw_error_t -_scomphy_port_mdix_status_get (a_uint32_t dev_id, fal_port_t port_id, - fal_port_mdix_status_t * mode) -{ - sw_error_t rv; - a_uint32_t phy_id = 0; - hsl_phy_ops_t *phy_drv; - - HSL_DEV_ID_CHECK (dev_id); - - if (A_TRUE != hsl_port_prop_check (dev_id, port_id, HSL_PP_PHY)) - { - return SW_BAD_PARAM; - } - - SW_RTN_ON_NULL (phy_drv = hsl_phy_api_ops_get (dev_id, port_id)); - if (NULL == phy_drv->phy_mdix_status_get) - return SW_NOT_SUPPORTED; - - rv = hsl_port_prop_get_phyid (dev_id, port_id, &phy_id); - SW_RTN_ON_ERROR (rv); - - rv = phy_drv->phy_mdix_status_get (dev_id, phy_id, mode); - - return rv; -} -/*qca808x_end*/ -static sw_error_t -_scomphy_port_combo_prefer_medium_set (a_uint32_t dev_id, fal_port_t port_id, - fal_port_medium_t phy_medium) -{ - sw_error_t rv; - a_uint32_t phy_id = 0; - hsl_phy_ops_t *phy_drv; - - HSL_DEV_ID_CHECK (dev_id); - if (A_TRUE != hsl_port_prop_check (dev_id, port_id, HSL_PP_PHY)) - { - return SW_BAD_PARAM; - } - - SW_RTN_ON_NULL (phy_drv = hsl_phy_api_ops_get (dev_id, port_id)); - if (NULL == phy_drv->phy_combo_prefer_medium_set) - return SW_NOT_SUPPORTED; - - rv = hsl_port_prop_get_phyid (dev_id, port_id, &phy_id); - SW_RTN_ON_ERROR (rv); - - rv = phy_drv->phy_combo_prefer_medium_set (dev_id, phy_id, phy_medium); - - return rv; -} - -static sw_error_t -_scomphy_port_combo_prefer_medium_get (a_uint32_t dev_id, fal_port_t port_id, - fal_port_medium_t * phy_medium) -{ - sw_error_t rv; - a_uint32_t phy_id = 0; - hsl_phy_ops_t *phy_drv; - - HSL_DEV_ID_CHECK (dev_id); - if (A_TRUE != hsl_port_prop_check (dev_id, port_id, HSL_PP_PHY)) - { - return SW_BAD_PARAM; - } - - SW_RTN_ON_NULL (phy_drv = hsl_phy_api_ops_get (dev_id, port_id)); - if (NULL == phy_drv->phy_combo_prefer_medium_get) - return SW_NOT_SUPPORTED; - - rv = hsl_port_prop_get_phyid (dev_id, port_id, &phy_id); - SW_RTN_ON_ERROR (rv); - - rv = phy_drv->phy_combo_prefer_medium_get (dev_id, phy_id, phy_medium); - - return rv; -} - -static sw_error_t -_scomphy_port_combo_medium_status_get (a_uint32_t dev_id, fal_port_t port_id, - fal_port_medium_t * phy_medium) -{ - sw_error_t rv; - a_uint32_t phy_id = 0; - hsl_phy_ops_t *phy_drv; - - HSL_DEV_ID_CHECK (dev_id); - if (A_TRUE != hsl_port_prop_check (dev_id, port_id, HSL_PP_PHY)) - { - return SW_BAD_PARAM; - } - - SW_RTN_ON_NULL (phy_drv = hsl_phy_api_ops_get (dev_id, port_id)); - if (NULL == phy_drv->phy_combo_medium_status_get) - return SW_NOT_SUPPORTED; - - rv = hsl_port_prop_get_phyid (dev_id, port_id, &phy_id); - SW_RTN_ON_ERROR (rv); - - rv = phy_drv->phy_combo_medium_status_get (dev_id, phy_id, phy_medium); - - return rv; -} - -static sw_error_t -_scomphy_port_combo_fiber_mode_set (a_uint32_t dev_id, fal_port_t port_id, - fal_port_fiber_mode_t fiber_mode) -{ - sw_error_t rv; - a_uint32_t phy_id = 0; - hsl_phy_ops_t *phy_drv; - - HSL_DEV_ID_CHECK (dev_id); - if (A_TRUE != hsl_port_prop_check (dev_id, port_id, HSL_PP_PHY)) - { - return SW_BAD_PARAM; - } - - SW_RTN_ON_NULL (phy_drv = hsl_phy_api_ops_get (dev_id, port_id)); - if (NULL == phy_drv->phy_combo_fiber_mode_set) - return SW_NOT_SUPPORTED; - - rv = hsl_port_prop_get_phyid (dev_id, port_id, &phy_id); - SW_RTN_ON_ERROR (rv); - - rv = phy_drv->phy_combo_fiber_mode_set (dev_id, phy_id, fiber_mode); - - return rv; -} - -static sw_error_t -_scomphy_port_combo_fiber_mode_get (a_uint32_t dev_id, fal_port_t port_id, - fal_port_fiber_mode_t * fiber_mode) -{ - sw_error_t rv; - a_uint32_t phy_id = 0; - hsl_phy_ops_t *phy_drv; - - HSL_DEV_ID_CHECK (dev_id); - if (A_TRUE != hsl_port_prop_check (dev_id, port_id, HSL_PP_PHY)) - { - return SW_BAD_PARAM; - } - - SW_RTN_ON_NULL (phy_drv = hsl_phy_api_ops_get (dev_id, port_id)); - if (NULL == phy_drv->phy_combo_fiber_mode_get) - return SW_NOT_SUPPORTED; - - rv = hsl_port_prop_get_phyid (dev_id, port_id, &phy_id); - SW_RTN_ON_ERROR (rv); - - rv = phy_drv->phy_combo_fiber_mode_get (dev_id, phy_id, fiber_mode); - - return rv; -} -/*qca808x_start*/ -static sw_error_t -_scomphy_port_local_loopback_set (a_uint32_t dev_id, fal_port_t port_id, - a_bool_t enable) -{ - sw_error_t rv; - a_uint32_t phy_id = 0; - hsl_phy_ops_t *phy_drv; - - HSL_DEV_ID_CHECK (dev_id); - if (A_TRUE != hsl_port_prop_check (dev_id, port_id, HSL_PP_PHY)) - { - return SW_BAD_PARAM; - } - - SW_RTN_ON_NULL (phy_drv = hsl_phy_api_ops_get (dev_id, port_id)); - if (NULL == phy_drv->phy_local_loopback_set) - return SW_NOT_SUPPORTED; - - rv = hsl_port_prop_get_phyid (dev_id, port_id, &phy_id); - SW_RTN_ON_ERROR (rv); - - rv = phy_drv->phy_local_loopback_set (dev_id, phy_id, enable); - - return rv; -} - -static sw_error_t -_scomphy_port_local_loopback_get (a_uint32_t dev_id, fal_port_t port_id, - a_bool_t * enable) -{ - sw_error_t rv; - a_uint32_t phy_id = 0; - hsl_phy_ops_t *phy_drv; - - HSL_DEV_ID_CHECK (dev_id); - - if (A_TRUE != hsl_port_prop_check (dev_id, port_id, HSL_PP_PHY)) - { - return SW_BAD_PARAM; - } - - SW_RTN_ON_NULL (phy_drv = hsl_phy_api_ops_get (dev_id, port_id)); - if (NULL == phy_drv->phy_local_loopback_get) - return SW_NOT_SUPPORTED; - - rv = hsl_port_prop_get_phyid (dev_id, port_id, &phy_id); - SW_RTN_ON_ERROR (rv); - - rv = phy_drv->phy_local_loopback_get (dev_id, phy_id, enable); - - return rv; -} - -static sw_error_t -_scomphy_port_remote_loopback_set (a_uint32_t dev_id, fal_port_t port_id, - a_bool_t enable) -{ - sw_error_t rv; - a_uint32_t phy_id = 0; - hsl_phy_ops_t *phy_drv; - - HSL_DEV_ID_CHECK (dev_id); - if (A_TRUE != hsl_port_prop_check (dev_id, port_id, HSL_PP_PHY)) - { - return SW_BAD_PARAM; - } - - SW_RTN_ON_NULL (phy_drv = hsl_phy_api_ops_get (dev_id, port_id)); - if (NULL == phy_drv->phy_remote_loopback_set) - return SW_NOT_SUPPORTED; - - rv = hsl_port_prop_get_phyid (dev_id, port_id, &phy_id); - SW_RTN_ON_ERROR (rv); - - rv = phy_drv->phy_remote_loopback_set (dev_id, phy_id, enable); - - return rv; -} - -static sw_error_t -_scomphy_port_remote_loopback_get (a_uint32_t dev_id, fal_port_t port_id, - a_bool_t * enable) -{ - sw_error_t rv; - a_uint32_t phy_id = 0; - hsl_phy_ops_t *phy_drv; - - HSL_DEV_ID_CHECK (dev_id); - - if (A_TRUE != hsl_port_prop_check (dev_id, port_id, HSL_PP_PHY)) - { - return SW_BAD_PARAM; - } - - SW_RTN_ON_NULL (phy_drv = hsl_phy_api_ops_get (dev_id, port_id)); - if (NULL == phy_drv->phy_remote_loopback_get) - return SW_NOT_SUPPORTED; - - rv = hsl_port_prop_get_phyid (dev_id, port_id, &phy_id); - SW_RTN_ON_ERROR (rv); - - rv = phy_drv->phy_remote_loopback_get (dev_id, phy_id, enable); - - return rv; -} -#endif - -static sw_error_t -_scomphy_port_power_off (a_uint32_t dev_id, fal_port_t port_id) -{ - sw_error_t rv; - a_uint32_t phy_id = 0; - hsl_phy_ops_t *phy_drv; - - HSL_DEV_ID_CHECK (dev_id); - - if (A_TRUE != hsl_port_prop_check (dev_id, port_id, HSL_PP_PHY)) - { - return SW_BAD_PARAM; - } - - SW_RTN_ON_NULL (phy_drv = hsl_phy_api_ops_get (dev_id, port_id)); - if (NULL == phy_drv->phy_power_off) - return SW_NOT_SUPPORTED; - - rv = hsl_port_prop_get_phyid (dev_id, port_id, &phy_id); - SW_RTN_ON_ERROR (rv); - - rv = phy_drv->phy_power_off(dev_id, phy_id); - - return rv; -} - -static sw_error_t -_scomphy_port_power_on (a_uint32_t dev_id, fal_port_t port_id) -{ - sw_error_t rv; - a_uint32_t phy_id = 0; - hsl_phy_ops_t *phy_drv; - - HSL_DEV_ID_CHECK (dev_id); - - if (A_TRUE != hsl_port_prop_check (dev_id, port_id, HSL_PP_PHY)) - { - return SW_BAD_PARAM; - } - - SW_RTN_ON_NULL (phy_drv = hsl_phy_api_ops_get (dev_id, port_id)); - if (NULL == phy_drv->phy_power_on) - return SW_NOT_SUPPORTED; - - rv = hsl_port_prop_get_phyid (dev_id, port_id, &phy_id); - SW_RTN_ON_ERROR (rv); - - rv = phy_drv->phy_power_on(dev_id, phy_id); - - return rv; -} - -#ifndef IN_PORTCONTROL_MINI -static sw_error_t -_scomphy_port_wol_status_set (a_uint32_t dev_id, fal_port_t port_id, - a_bool_t enable) -{ - sw_error_t rv; - a_uint32_t phy_id = 0; - hsl_phy_ops_t *phy_drv; - - HSL_DEV_ID_CHECK (dev_id); - if (A_TRUE != hsl_port_prop_check (dev_id, port_id, HSL_PP_PHY)) - { - return SW_BAD_PARAM; - } - - SW_RTN_ON_NULL (phy_drv = hsl_phy_api_ops_get (dev_id, port_id)); - if (NULL == phy_drv->phy_wol_status_set) - return SW_NOT_SUPPORTED; - - rv = hsl_port_prop_get_phyid (dev_id, port_id, &phy_id); - SW_RTN_ON_ERROR (rv); - - rv = phy_drv->phy_wol_status_set (dev_id, phy_id, enable); - - return rv; -} - -static sw_error_t -_scomphy_port_wol_status_get (a_uint32_t dev_id, fal_port_t port_id, - a_bool_t * enable) -{ - sw_error_t rv; - a_uint32_t phy_id = 0; - hsl_phy_ops_t *phy_drv; - - HSL_DEV_ID_CHECK (dev_id); - - if (A_TRUE != hsl_port_prop_check (dev_id, port_id, HSL_PP_PHY)) - { - return SW_BAD_PARAM; - } - - SW_RTN_ON_NULL (phy_drv = hsl_phy_api_ops_get (dev_id, port_id)); - if (NULL == phy_drv->phy_wol_status_get) - return SW_NOT_SUPPORTED; - - rv = hsl_port_prop_get_phyid (dev_id, port_id, &phy_id); - SW_RTN_ON_ERROR (rv); - - rv = phy_drv->phy_wol_status_get (dev_id, phy_id, enable); - - return rv; -} -/*qca808x_end*/ -static sw_error_t -_scomphy_port_interface_mode_set (a_uint32_t dev_id, fal_port_t port_id, - fal_port_interface_mode_t mode) -{ - sw_error_t rv; - a_uint32_t phy_id = 0; - hsl_phy_ops_t *phy_drv; - - HSL_DEV_ID_CHECK (dev_id); - - if (A_TRUE != hsl_port_prop_check (dev_id, port_id, HSL_PP_PHY)) - { - return SW_BAD_PARAM; - } - - SW_RTN_ON_NULL (phy_drv = hsl_phy_api_ops_get (dev_id, port_id)); - if (NULL == phy_drv->phy_interface_mode_set) - return SW_NOT_SUPPORTED; - - rv = hsl_port_prop_get_phyid (dev_id, port_id, &phy_id); - SW_RTN_ON_ERROR (rv); - - rv = phy_drv->phy_interface_mode_set (dev_id, phy_id,mode); - - return rv; -} - -static sw_error_t -_scomphy_port_interface_mode_get (a_uint32_t dev_id, fal_port_t port_id, - fal_port_interface_mode_t * mode) -{ - sw_error_t rv; - a_uint32_t phy_id = 0; - hsl_phy_ops_t *phy_drv; - - HSL_DEV_ID_CHECK (dev_id); - - if (A_TRUE != hsl_port_prop_check (dev_id, port_id, HSL_PP_PHY)) - { - return SW_BAD_PARAM; - } - - SW_RTN_ON_NULL (phy_drv = hsl_phy_api_ops_get (dev_id, port_id)); - if (NULL == phy_drv->phy_interface_mode_get) - return SW_NOT_SUPPORTED; - - rv = hsl_port_prop_get_phyid (dev_id, port_id, &phy_id); - SW_RTN_ON_ERROR (rv); - - rv = phy_drv->phy_interface_mode_get (dev_id, phy_id,mode); - - return rv; -} -/*qca808x_start*/ -static sw_error_t -_scomphy_port_interface_mode_status_get (a_uint32_t dev_id, fal_port_t port_id, - fal_port_interface_mode_t * mode) -{ - sw_error_t rv; - a_uint32_t phy_id = 0; - hsl_phy_ops_t *phy_drv; - - HSL_DEV_ID_CHECK (dev_id); - - if (A_TRUE != hsl_port_prop_check (dev_id, port_id, HSL_PP_PHY)) - { - return SW_BAD_PARAM; - } - - SW_RTN_ON_NULL (phy_drv = hsl_phy_api_ops_get (dev_id, port_id)); - if (NULL == phy_drv->phy_interface_mode_status_get) - return SW_NOT_SUPPORTED; - - rv = hsl_port_prop_get_phyid (dev_id, port_id, &phy_id); - SW_RTN_ON_ERROR (rv); - - rv = phy_drv->phy_interface_mode_status_get (dev_id, phy_id,mode); - - return rv; -} - -static sw_error_t -_scomphy_port_magic_frame_mac_set (a_uint32_t dev_id, fal_port_t port_id, - fal_mac_addr_t * mac) -{ - sw_error_t rv; - a_uint32_t phy_id = 0; - hsl_phy_ops_t *phy_drv; - - HSL_DEV_ID_CHECK (dev_id); - - if (A_TRUE != hsl_port_prop_check (dev_id, port_id, HSL_PP_PHY)) - { - return SW_BAD_PARAM; - } - - SW_RTN_ON_NULL (phy_drv = hsl_phy_api_ops_get (dev_id, port_id)); - if (NULL == phy_drv->phy_magic_frame_mac_set) - return SW_NOT_SUPPORTED; - - rv = hsl_port_prop_get_phyid (dev_id, port_id, &phy_id); - SW_RTN_ON_ERROR (rv); - - rv = phy_drv->phy_magic_frame_mac_set (dev_id, phy_id,mac); - - return rv; -} - -static sw_error_t -_scomphy_port_magic_frame_mac_get (a_uint32_t dev_id, fal_port_t port_id, - fal_mac_addr_t * mac) -{ - sw_error_t rv; - a_uint32_t phy_id = 0; - hsl_phy_ops_t *phy_drv; - - HSL_DEV_ID_CHECK (dev_id); - - if (A_TRUE != hsl_port_prop_check (dev_id, port_id, HSL_PP_PHY)) - { - return SW_BAD_PARAM; - } - - SW_RTN_ON_NULL (phy_drv = hsl_phy_api_ops_get (dev_id, port_id)); - if (NULL == phy_drv->phy_magic_frame_mac_get) - return SW_NOT_SUPPORTED; - - rv = hsl_port_prop_get_phyid (dev_id, port_id, &phy_id); - SW_RTN_ON_ERROR (rv); - - rv = phy_drv->phy_magic_frame_mac_get (dev_id, phy_id,mac); - - return rv; -} - -static sw_error_t -_scomphy_port_counter_set (a_uint32_t dev_id, fal_port_t port_id, a_bool_t enable) -{ - sw_error_t rv; - a_uint32_t phy_id = 0; - hsl_phy_ops_t *phy_drv; - - HSL_DEV_ID_CHECK (dev_id); - if (A_TRUE != hsl_port_prop_check (dev_id, port_id, HSL_PP_PHY)) - { - return SW_BAD_PARAM; - } - - SW_RTN_ON_NULL (phy_drv = hsl_phy_api_ops_get (dev_id, port_id)); - if (NULL == phy_drv->phy_counter_set) - return SW_NOT_SUPPORTED; - - rv = hsl_port_prop_get_phyid (dev_id, port_id, &phy_id); - SW_RTN_ON_ERROR (rv); - - rv = phy_drv->phy_counter_set (dev_id, phy_id, enable); - - return rv; -} - -static sw_error_t -_scomphy_port_counter_get (a_uint32_t dev_id, fal_port_t port_id, - a_bool_t * enable) -{ - sw_error_t rv; - a_uint32_t phy_id = 0; - hsl_phy_ops_t *phy_drv; - - HSL_DEV_ID_CHECK (dev_id); - - if (A_TRUE != hsl_port_prop_check (dev_id, port_id, HSL_PP_PHY)) - { - return SW_BAD_PARAM; - } - - SW_RTN_ON_NULL (phy_drv = hsl_phy_api_ops_get (dev_id, port_id)); - if (NULL == phy_drv->phy_counter_get) - return SW_NOT_SUPPORTED; - - rv = hsl_port_prop_get_phyid (dev_id, port_id, &phy_id); - SW_RTN_ON_ERROR (rv); - - rv = phy_drv->phy_counter_get (dev_id, phy_id, enable); - - return rv; -} - -static sw_error_t -_scomphy_port_counter_show (a_uint32_t dev_id, fal_port_t port_id, - fal_port_counter_info_t * counter_info) -{ - sw_error_t rv; - a_uint32_t phy_id = 0; - hsl_phy_ops_t *phy_drv; - - HSL_DEV_ID_CHECK (dev_id); - - if (A_TRUE != hsl_port_prop_check (dev_id, port_id, HSL_PP_PHY)) - { - return SW_BAD_PARAM; - } - - SW_RTN_ON_NULL (phy_drv = hsl_phy_api_ops_get (dev_id, port_id)); - if (NULL == phy_drv->phy_counter_show) - return SW_NOT_SUPPORTED; - - rv = hsl_port_prop_get_phyid (dev_id, port_id, &phy_id); - SW_RTN_ON_ERROR (rv); - - rv = phy_drv->phy_counter_show (dev_id, phy_id,counter_info); - - return rv; -} -#endif - -static sw_error_t -_scomphy_port_link_status_get (a_uint32_t dev_id, fal_port_t port_id, - a_bool_t * status) -{ - sw_error_t rv; - a_uint32_t phy_id; - hsl_phy_ops_t *phy_drv; - - HSL_DEV_ID_CHECK (dev_id); - - if (A_TRUE != hsl_port_prop_check (dev_id, port_id, HSL_PP_PHY)) - { - return SW_BAD_PARAM; - } - - SW_RTN_ON_NULL (phy_drv = hsl_phy_api_ops_get (dev_id, port_id)); - if (NULL == phy_drv->phy_link_status_get) - return SW_NOT_SUPPORTED; - - rv = hsl_port_prop_get_phyid (dev_id, port_id, &phy_id); - SW_RTN_ON_ERROR (rv); - - if (A_TRUE == phy_drv->phy_link_status_get (dev_id, phy_id)) - { - *status = A_TRUE; - } - else - { - *status = A_FALSE; - } - - return SW_OK; -} - -static sw_error_t -_scomphy_port_reset (a_uint32_t dev_id, fal_port_t port_id) -{ - sw_error_t rv; - a_uint32_t phy_id = 0; - hsl_phy_ops_t *phy_drv; - - HSL_DEV_ID_CHECK (dev_id); - - if (A_TRUE != hsl_port_prop_check (dev_id, port_id, HSL_PP_PHY)) - { - return SW_BAD_PARAM; - } - - SW_RTN_ON_NULL (phy_drv = hsl_phy_api_ops_get (dev_id, port_id)); - if (NULL == phy_drv->phy_reset) - return SW_NOT_SUPPORTED; - - rv = hsl_port_prop_get_phyid (dev_id, port_id, &phy_id); - SW_RTN_ON_ERROR (rv); - - rv = phy_drv->phy_reset(dev_id, phy_id); - - return rv; -} - -#ifndef IN_PORTCONTROL_MINI -static sw_error_t -_scomphy_port_phy_id_get (a_uint32_t dev_id, fal_port_t port_id, - a_uint16_t * org_id, a_uint16_t * rev_id) -{ - sw_error_t rv; - a_uint32_t phy_id = 0; - hsl_phy_ops_t *phy_drv; - a_uint32_t phy_data; - - HSL_DEV_ID_CHECK (dev_id); - - if (A_TRUE != hsl_port_prop_check (dev_id, port_id, HSL_PP_PHY)) - { - return SW_BAD_PARAM; - } - - SW_RTN_ON_NULL (phy_drv = hsl_phy_api_ops_get (dev_id, port_id)); - if (NULL == phy_drv->phy_id_get) - return SW_NOT_SUPPORTED; - - rv = hsl_port_prop_get_phyid (dev_id, port_id, &phy_id); - SW_RTN_ON_ERROR (rv); - - rv = phy_drv->phy_id_get (dev_id, phy_id, &phy_data); - SW_RTN_ON_ERROR (rv); - - *org_id = (phy_data >> 16) & 0xffff; - *rev_id = phy_data & 0xffff; - - return rv; -} -#endif - -/** - * @brief Set duplex mode on a particular port. - * @param[in] dev_id device id - * @param[in] port_id port id - * @param[in] duplex duplex mode - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -scomphy_port_duplex_set (a_uint32_t dev_id, fal_port_t port_id, - fal_port_duplex_t duplex) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _scomphy_port_duplex_set (dev_id, port_id, duplex); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Get duplex mode on a particular port. - * @param[in] dev_id device id - * @param[in] port_id port id - * @param[out] duplex duplex mode - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -scomphy_port_duplex_get (a_uint32_t dev_id, fal_port_t port_id, - fal_port_duplex_t * pduplex) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _scomphy_port_duplex_get (dev_id, port_id, pduplex); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Set speed on a particular port. - * @param[in] dev_id device id - * @param[in] port_id port id - * @param[in] speed port speed - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -scomphy_port_speed_set (a_uint32_t dev_id, fal_port_t port_id, - fal_port_speed_t speed) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _scomphy_port_speed_set (dev_id, port_id, speed); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Get speed on a particular port. - * @param[in] dev_id device id - * @param[in] port_id port id - * @param[out] speed port speed - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -scomphy_port_speed_get (a_uint32_t dev_id, fal_port_t port_id, - fal_port_speed_t * pspeed) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _scomphy_port_speed_get (dev_id, port_id, pspeed); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Get auto negotiation status on a particular port. - * @param[in] dev_id device id - * @param[in] port_id port id - * @param[out] status A_TRUE or A_FALSE - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -scomphy_port_autoneg_status_get (a_uint32_t dev_id, fal_port_t port_id, - a_bool_t * status) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _scomphy_port_autoneg_status_get (dev_id, port_id, status); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Enable auto negotiation status on a particular port. - * @param[in] dev_id device id - * @param[in] port_id port id - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -scomphy_port_autoneg_enable (a_uint32_t dev_id, fal_port_t port_id) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _scomphy_port_autoneg_enable (dev_id, port_id); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Restart auto negotiation procedule on a particular port. - * @param[in] dev_id device id - * @param[in] port_id port id - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -scomphy_port_autoneg_restart (a_uint32_t dev_id, fal_port_t port_id) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _scomphy_port_autoneg_restart (dev_id, port_id); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Set auto negotiation advtisement ability on a particular port. - * @details Comments: - * auto negotiation advtisement ability is defined by macro such as - * FAL_PHY_ADV_10T_HD, FAL_PHY_ADV_PAUSE... - * @param[in] dev_id device id - * @param[in] port_id port id - * @param[in] autoadv auto negotiation advtisement ability bit map - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -scomphy_port_autoneg_adv_set (a_uint32_t dev_id, fal_port_t port_id, - a_uint32_t autoadv) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _scomphy_port_autoneg_adv_set (dev_id, port_id, autoadv); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Get auto negotiation advtisement ability on a particular port. - * @param[in] dev_id device id - * @param[in] port_id port id - * @param[out] autoadv auto negotiation advtisement ability bit map - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -scomphy_port_autoneg_adv_get (a_uint32_t dev_id, fal_port_t port_id, - a_uint32_t * autoadv) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _scomphy_port_autoneg_adv_get (dev_id, port_id, autoadv); - HSL_API_UNLOCK; - return rv; -} - -#ifndef IN_PORTCONTROL_MINI -/** - * @brief Set powersaving status on a particular port. - * @param[in] dev_id device id - * @param[in] port_id port id - * @param[out] enable A_TRUE or A_FALSE - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -scomphy_port_powersave_set (a_uint32_t dev_id, fal_port_t port_id, - a_bool_t enable) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _scomphy_port_powersave_set (dev_id, port_id, enable); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Get powersaving status on a particular port. - * @param[in] dev_id device id - * @param[in] port_id port id - * @param[out] enable A_TRUE or A_FALSE - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -scomphy_port_powersave_get (a_uint32_t dev_id, fal_port_t port_id, - a_bool_t * enable) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _scomphy_port_powersave_get (dev_id, port_id, enable); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Set hibernate status on a particular port. - * @param[in] dev_id device id - * @param[in] port_id port id - * @param[out] enable A_TRUE or A_FALSE - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -scomphy_port_hibernate_set (a_uint32_t dev_id, fal_port_t port_id, - a_bool_t enable) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _scomphy_port_hibernate_set (dev_id, port_id, enable); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Get hibernate status on a particular port. - * @param[in] dev_id device id - * @param[in] port_id port id - * @param[out] enable A_TRUE or A_FALSE - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -scomphy_port_hibernate_get (a_uint32_t dev_id, fal_port_t port_id, - a_bool_t * enable) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _scomphy_port_hibernate_get (dev_id, port_id, enable); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Run cable diagnostic test on a particular port. - * @param[in] dev_id device id - * @param[in] port_id port id - * @param[in] mdi_pair mdi pair id - * @param[out] cable_status cable status - * @param[out] cable_len cable len - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -scomphy_port_cdt (a_uint32_t dev_id, fal_port_t port_id, a_uint32_t mdi_pair, - fal_cable_status_t * cable_status, a_uint32_t * cable_len) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _scomphy_port_cdt (dev_id, port_id, mdi_pair, cable_status, cable_len); - HSL_API_UNLOCK; - return rv; -} -/** - * @brief Set 802.3az status on a particular port. - * @param[in] dev_id device id - * @param[in] port_id port id - * @param[out] enable A_TRUE or A_FALSE - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -scomphy_port_8023az_set (a_uint32_t dev_id, fal_port_t port_id, a_bool_t enable) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _scomphy_port_8023az_set (dev_id, port_id, enable); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Get 8023az status on a particular port. - * @param[in] dev_id device id - * @param[in] port_id port id - * @param[out] enable A_TRUE or A_FALSE - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -scomphy_port_8023az_get (a_uint32_t dev_id, fal_port_t port_id, - a_bool_t * enable) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _scomphy_port_8023az_get (dev_id, port_id, enable); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Set mdix on a particular port. - * @param[in] dev_id device id - * @param[in] port_id port id - * @param[out] mode - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -scomphy_port_mdix_set (a_uint32_t dev_id, a_uint32_t phy_id, - fal_port_mdix_mode_t mode) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _scomphy_port_mdix_set (dev_id, phy_id, mode); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Get mdix configuration on a particular port. - * @param[in] dev_id device id - * @param[in] port_id port id - * @param[out] mode - * @return SW_OK or error code - */ - -HSL_LOCAL sw_error_t -scomphy_port_mdix_get (a_uint32_t dev_id, fal_port_t port_id, - fal_port_mdix_mode_t * mode) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _scomphy_port_mdix_get (dev_id, port_id, mode); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Get mdix status on a particular port. - * @param[in] dev_id device id - * @param[in] port_id port id - * @param[out] mode - * @return SW_OK or error code - */ - -HSL_LOCAL sw_error_t -scomphy_port_mdix_status_get (a_uint32_t dev_id, fal_port_t port_id, - fal_port_mdix_status_t * mode) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _scomphy_port_mdix_status_get (dev_id, port_id, mode); - HSL_API_UNLOCK; - return rv; -} -/*qca808x_end*/ -/** - * @brief Set combo prefer medium on a particular port. - * @param[in] dev_id device id - * @param[in] port_id port id - * @param[out] phy_medium [fiber or copper] - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -scomphy_port_combo_prefer_medium_set (a_uint32_t dev_id, a_uint32_t phy_id, - fal_port_medium_t phy_medium) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _scomphy_port_combo_prefer_medium_set (dev_id, phy_id, phy_medium); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Get combo prefer medium on a particular port. - * @param[in] dev_id device id - * @param[in] port_id port id - * @param[out] phy_medium [fiber or copper] - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -scomphy_port_combo_prefer_medium_get (a_uint32_t dev_id, a_uint32_t phy_id, - fal_port_medium_t * phy_medium) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _scomphy_port_combo_prefer_medium_get (dev_id, phy_id, phy_medium); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Get current combo medium status on a particular port. - * @param[in] dev_id device id - * @param[in] port_id port id - * @param[out] phy_medium [fiber or copper] - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -scomphy_port_combo_medium_status_get (a_uint32_t dev_id, a_uint32_t phy_id, - fal_port_medium_t * phy_medium) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _scomphy_port_combo_medium_status_get (dev_id, phy_id, phy_medium); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Set fiber mode on a particular port. - * @param[in] dev_id device id - * @param[in] port_id port id - * @param[out] fiber mode [1000bx or 100fx] - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -scomphy_port_combo_fiber_mode_set (a_uint32_t dev_id, a_uint32_t phy_id, - fal_port_fiber_mode_t fiber_mode) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _scomphy_port_combo_fiber_mode_set (dev_id, phy_id, fiber_mode); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Get fiber mode on a particular port. - * @param[in] dev_id device id - * @param[in] port_id port id - * @param[out] fiber mode [1000bx or 100fx] - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -scomphy_port_combo_fiber_mode_get (a_uint32_t dev_id, a_uint32_t phy_id, - fal_port_fiber_mode_t * fiber_mode) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _scomphy_port_combo_fiber_mode_get (dev_id, phy_id, fiber_mode); - HSL_API_UNLOCK; - return rv; -} -/*qca808x_start*/ -/** - * @brief Set phy local loop back on a particular port. - * @param[in] dev_id device id - * @param[in] port_id port id - * @param[in] enable A_TRUE or A_FALSE - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -scomphy_port_local_loopback_set (a_uint32_t dev_id, fal_port_t port_id, - a_bool_t enable) -{ - sw_error_t rv; - HSL_API_LOCK; - rv = _scomphy_port_local_loopback_set (dev_id, port_id, enable); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Get phy local loop back on a particular port. - * @param[in] dev_id device id - * @param[in] port_id port id - * @param[out] enable A_TRUE or A_FALSE - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -scomphy_port_local_loopback_get (a_uint32_t dev_id, fal_port_t port_id, - a_bool_t * enable) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _scomphy_port_local_loopback_get (dev_id, port_id, enable); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Set phy remote loop back on a particular port. - * @param[in] dev_id device id - * @param[in] port_id port id - * @param[in] enable A_TRUE or A_FALSE - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -scomphy_port_remote_loopback_set (a_uint32_t dev_id, fal_port_t port_id, - a_bool_t enable) -{ - sw_error_t rv; - HSL_API_LOCK; - rv = _scomphy_port_remote_loopback_set (dev_id, port_id, enable); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Get phy remote loop back on a particular port. - * @param[in] dev_id device id - * @param[in] port_id port id - * @param[out] enable A_TRUE or A_FALSE - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -scomphy_port_remote_loopback_get (a_uint32_t dev_id, fal_port_t port_id, - a_bool_t * enable) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _scomphy_port_remote_loopback_get (dev_id, port_id, enable); - HSL_API_UNLOCK; - return rv; -} -#endif - -/** - * @brief phy power off on a particular port. - * @param[in] dev_id device id - * @param[in] port_id port id - * @param[in] - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -scomphy_port_power_off (a_uint32_t dev_id, fal_port_t port_id) -{ - sw_error_t rv; - HSL_API_LOCK; - rv = _scomphy_port_power_off (dev_id, port_id); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief phy power on on a particular port. - * @param[in] dev_id device id - * @param[in] port_id port id - * @param[in] - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -scomphy_port_power_on (a_uint32_t dev_id, fal_port_t port_id) -{ - sw_error_t rv; - HSL_API_LOCK; - rv = _scomphy_port_power_on (dev_id, port_id); - HSL_API_UNLOCK; - return rv; -} - -#ifndef IN_PORTCONTROL_MINI -/** - * @brief Set phy wol enable on a particular port. - * @param[in] dev_id device id - * @param[in] port_id port id - * @param[in] enable A_TRUE or A_FALSE - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -scomphy_port_wol_status_set (a_uint32_t dev_id, fal_port_t port_id, - a_bool_t enable) -{ - sw_error_t rv; - HSL_API_LOCK; - rv = _scomphy_port_wol_status_set (dev_id, port_id, enable); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Get phy wol status on a particular port. - * @param[in] dev_id device id - * @param[in] port_id port id - * @param[out] enable A_TRUE or A_FALSE - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -scomphy_port_wol_status_get (a_uint32_t dev_id, fal_port_t port_id, - a_bool_t * enable) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _scomphy_port_wol_status_get (dev_id, port_id, enable); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Set phy magic frame mac on a particular port. - * @param[in] dev_id device id - * @param[in] port_id port id - * @param[in] mac address - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -scomphy_port_magic_frame_mac_set (a_uint32_t dev_id, fal_port_t port_id, - fal_mac_addr_t * mac) -{ - sw_error_t rv; - HSL_API_LOCK; - rv = _scomphy_port_magic_frame_mac_set (dev_id, port_id, mac); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Get phy magic frame mac on a particular port. - * @param[in] dev_id device id - * @param[in] port_id port id - * @param[out] mac address - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -scomphy_port_magic_frame_mac_get (a_uint32_t dev_id, fal_port_t port_id, - fal_mac_addr_t * mac) -{ - sw_error_t rv; - HSL_API_LOCK; - rv = _scomphy_port_magic_frame_mac_get (dev_id, port_id, mac); - HSL_API_UNLOCK; - return rv; -} -/*qca808x_end*/ -/** - * @brief Set phy interface mode. - * @param[in] dev_id device id - * @param[in] port_id port id - * @param[in] interface mode.. - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -scomphy_port_interface_mode_set (a_uint32_t dev_id, fal_port_t port_id, - fal_port_interface_mode_t mode) -{ - sw_error_t rv; - HSL_API_LOCK; - rv = _scomphy_port_interface_mode_set (dev_id, port_id, mode); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Set phy interface mode. - * @param[in] dev_id device id - * @param[in] port_id port id - * @param[out] interface mode.. - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -scomphy_port_interface_mode_get (a_uint32_t dev_id, fal_port_t port_id, - fal_port_interface_mode_t * mode) -{ - sw_error_t rv; - HSL_API_LOCK; - rv = _scomphy_port_interface_mode_get (dev_id, port_id, mode); - HSL_API_UNLOCK; - return rv; -} -/*qca808x_start*/ -/** - * @brief Set phy interface mode status. - * @param[in] dev_id device id - * @param[in] port_id port id - * @param[out] interface mode.. - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -scomphy_port_interface_mode_status_get (a_uint32_t dev_id, fal_port_t port_id, - fal_port_interface_mode_t * mode) -{ - sw_error_t rv; - HSL_API_LOCK; - rv = _scomphy_port_interface_mode_status_get (dev_id, port_id, mode); - HSL_API_UNLOCK; - return rv; -} -#endif - -/** - * @brief Get link status on particular port. - * @param[in] dev_id device id - * @param[in] port_id port id - * @param[out] status link status up (A_TRUE) or down (A_FALSE) - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -scomphy_port_link_status_get (a_uint32_t dev_id, fal_port_t port_id, - a_bool_t * status) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _scomphy_port_link_status_get (dev_id, port_id, status); - HSL_API_UNLOCK; - return rv; -} - -#ifndef IN_PORTCONTROL_MINI -/** - * @brief Set counter status on a particular port. - * @param[in] dev_id device id - * @param[in] port_id port id - * @param[out] enable A_TRUE or A_FALSE - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -scomphy_port_counter_set (a_uint32_t dev_id, fal_port_t port_id, a_bool_t enable) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _scomphy_port_counter_set (dev_id, port_id, enable); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Get counter status on a particular port. - * @param[in] dev_id device id - * @param[in] port_id port id - * @param[out] enable A_TRUE or A_FALSE - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -scomphy_port_counter_get (a_uint32_t dev_id, fal_port_t port_id, - a_bool_t * enable) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _scomphy_port_counter_get (dev_id, port_id, enable); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Get counter statistics on a particular port. - * @param[in] dev_id device id - * @param[in] port_id port id - * @param[out] frame counter statistics - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -scomphy_port_counter_show(a_uint32_t dev_id, fal_port_t port_id, - fal_port_counter_info_t * counter_info) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _scomphy_port_counter_show (dev_id, port_id, counter_info); - HSL_API_UNLOCK; - return rv; -} -#endif - -/** - * @brief software reset on a particular port. - * @param[in] dev_id device id - * @param[in] port_id port id - * @param[in] - * @return SW_OK or error code - */ -sw_error_t -scomphy_port_reset (a_uint32_t dev_id, fal_port_t port_id) -{ - sw_error_t rv; - HSL_API_LOCK; - rv = _scomphy_port_reset (dev_id, port_id); - HSL_API_UNLOCK; - return rv; -} - -#ifndef IN_PORTCONTROL_MINI -/** - * @brief Get phy id on a particular port. - * @param[in] dev_id device id - * @param[in] port_id port id - * @param[out] org_id and rev_id - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -scomphy_port_phy_id_get (a_uint32_t dev_id, fal_port_t port_id, - a_uint16_t * org_id, a_uint16_t * rev_id) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _scomphy_port_phy_id_get (dev_id, port_id, org_id,rev_id); - HSL_API_UNLOCK; - return rv; -} -#endif - -sw_error_t -scomphy_port_ctrl_init(a_uint32_t dev_id) -{ - HSL_DEV_ID_CHECK(dev_id); - -#ifndef HSL_STANDALONG - { - hsl_api_t *p_api; - - SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id)); - - p_api->port_duplex_get = scomphy_port_duplex_get; - p_api->port_duplex_set = scomphy_port_duplex_set; - p_api->port_speed_get = scomphy_port_speed_get; - p_api->port_speed_set = scomphy_port_speed_set; - p_api->port_autoneg_status_get = scomphy_port_autoneg_status_get; - p_api->port_autoneg_enable = scomphy_port_autoneg_enable; - p_api->port_autoneg_restart = scomphy_port_autoneg_restart; - p_api->port_autoneg_adv_get = scomphy_port_autoneg_adv_get; - p_api->port_autoneg_adv_set = scomphy_port_autoneg_adv_set; -#ifndef IN_PORTCONTROL_MINI - p_api->port_powersave_set = scomphy_port_powersave_set; - p_api->port_powersave_get = scomphy_port_powersave_get; - p_api->port_hibernate_set = scomphy_port_hibernate_set; - p_api->port_hibernate_get = scomphy_port_hibernate_get; - p_api->port_cdt = scomphy_port_cdt; - p_api->port_8023az_set = scomphy_port_8023az_set; - p_api->port_8023az_get = scomphy_port_8023az_get; - p_api->port_mdix_set = scomphy_port_mdix_set; - p_api->port_mdix_get = scomphy_port_mdix_get; - p_api->port_mdix_status_get = scomphy_port_mdix_status_get; -/*qca808x_end*/ - p_api->port_combo_prefer_medium_set = scomphy_port_combo_prefer_medium_set; - p_api->port_combo_prefer_medium_get = scomphy_port_combo_prefer_medium_get; - p_api->port_combo_medium_status_get = scomphy_port_combo_medium_status_get; - p_api->port_combo_fiber_mode_set = scomphy_port_combo_fiber_mode_set; - p_api->port_combo_fiber_mode_get = scomphy_port_combo_fiber_mode_get; -/*qca808x_start*/ - p_api->port_local_loopback_set = scomphy_port_local_loopback_set; - p_api->port_local_loopback_get = scomphy_port_local_loopback_get; - p_api->port_remote_loopback_set = scomphy_port_remote_loopback_set; - p_api->port_remote_loopback_get = scomphy_port_remote_loopback_get; -#endif - p_api->port_power_off = scomphy_port_power_off; - p_api->port_power_on = scomphy_port_power_on; -#ifndef IN_PORTCONTROL_MINI - p_api->port_wol_status_set = scomphy_port_wol_status_set; - p_api->port_wol_status_get = scomphy_port_wol_status_get; - p_api->port_magic_frame_mac_set = scomphy_port_magic_frame_mac_set; - p_api->port_magic_frame_mac_get = scomphy_port_magic_frame_mac_get; -/*qca808x_end*/ - p_api->port_interface_mode_set = scomphy_port_interface_mode_set; - p_api->port_interface_mode_get = scomphy_port_interface_mode_get; -/*qca808x_start*/ - p_api->port_interface_mode_status_get = scomphy_port_interface_mode_status_get; - p_api->port_counter_set = scomphy_port_counter_set; - p_api->port_counter_get = scomphy_port_counter_get; - p_api->port_counter_show = scomphy_port_counter_show; -#endif - p_api->port_link_status_get = scomphy_port_link_status_get; - p_api->port_reset = scomphy_port_reset; -#ifndef IN_PORTCONTROL_MINI - p_api->port_phy_id_get = scomphy_port_phy_id_get; -#endif - } -#endif - - return SW_OK; -} - -/** - * @} - */ -/*qca808x_end*/ diff --git a/feeds/ipq807x/qca-ssdk/src/src/hsl/scomphy/scomphy_reg_access.c b/feeds/ipq807x/qca-ssdk/src/src/hsl/scomphy/scomphy_reg_access.c deleted file mode 100755 index ed6f83c99..000000000 --- a/feeds/ipq807x/qca-ssdk/src/src/hsl/scomphy/scomphy_reg_access.c +++ /dev/null @@ -1,147 +0,0 @@ -/* - * Copyright (c) 2017-2019, The Linux Foundation. All rights reserved. - * Permission to use, copy, modify, and/or distribute this software for - * any purpose with or without fee is hereby granted, provided that the - * above copyright notice and this permission notice appear in all copies. - * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES - * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR - * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES - * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN - * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT - * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. - */ - -/*qca808x_start*/ -#include "sw.h" -#include "hsl.h" -#include "hsl_dev.h" -#include "sd.h" -#include "scomphy_reg_access.h" -#include "hsl_phy.h" - -#if defined(API_LOCK) -static aos_lock_t mdio_lock; -#define MDIO_LOCKER_INIT aos_lock_init(&mdio_lock) -#define MDIO_LOCKER_LOCK aos_lock(&mdio_lock) -#define MDIO_LOCKER_UNLOCK aos_unlock(&mdio_lock) -#else -#define MDIO_LOCKER_INIT -#define MDIO_LOCKER_LOCK -#define MDIO_LOCKER_UNLOCK -#endif - -sw_error_t -scomphy_phy_get(a_uint32_t dev_id, a_uint32_t phy_addr, - a_uint32_t reg, a_uint16_t * value) -{ - sw_error_t rv; - - MDIO_LOCKER_LOCK; - rv = sd_reg_mdio_get(dev_id, phy_addr, reg, value); - MDIO_LOCKER_UNLOCK; - return rv; -} - -sw_error_t -scomphy_phy_set(a_uint32_t dev_id, a_uint32_t phy_addr, - a_uint32_t reg, a_uint16_t value) -{ - sw_error_t rv; - - MDIO_LOCKER_LOCK; - rv = sd_reg_mdio_set(dev_id, phy_addr, reg, value); - MDIO_LOCKER_UNLOCK; - return rv; -} - -sw_error_t -scomphy_phy_i2c_get(a_uint32_t dev_id, a_uint32_t phy_addr, - a_uint32_t reg, a_uint16_t * value) -{ - sw_error_t rv; - - rv = sd_reg_i2c_get(dev_id, phy_addr, reg, value); - - return rv; -} - -sw_error_t -scomphy_phyi2c_set(a_uint32_t dev_id, a_uint32_t phy_addr, - a_uint32_t reg, a_uint16_t value) -{ - sw_error_t rv; - - rv = sd_reg_i2c_set(dev_id, phy_addr, reg, value); - - return rv; -} -/*qca808x_end*/ -sw_error_t -scomphy_reg_get(a_uint32_t dev_id, a_uint32_t reg_addr, - a_uint8_t *val, a_uint32_t len) -{ - sw_error_t rv; - - rv = sd_reg_hdr_get(dev_id, reg_addr, val, len); - - return rv; -} - -sw_error_t -scomphy_reg_set(a_uint32_t dev_id, a_uint32_t reg_addr, - a_uint8_t *val, a_uint32_t len) -{ - sw_error_t rv; - - rv = sd_reg_hdr_set(dev_id, reg_addr, val, len); - - return rv; -} - -sw_error_t -scomphy_uniphy_reg_get(a_uint32_t dev_id, a_uint32_t index, - a_uint32_t reg_addr, a_uint8_t *val, a_uint32_t len) -{ - sw_error_t rv; - - rv = sd_reg_uniphy_get(dev_id, index, reg_addr, val, len); - - return rv; -} - -sw_error_t -scomphy_uniphy_reg_set(a_uint32_t dev_id, a_uint32_t index, - a_uint32_t reg_addr, a_uint8_t *val, a_uint32_t len) -{ - sw_error_t rv; - - rv = sd_reg_uniphy_set(dev_id, index, reg_addr, val, len); - - return rv; -} -/*qca808x_start*/ -sw_error_t -scomphy_reg_access_init(a_uint32_t dev_id, ssdk_init_cfg *cfg) -{ - hsl_api_t *p_api; - - MDIO_LOCKER_INIT; - - SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id)); - p_api->phy_get = scomphy_phy_get; - p_api->phy_set = scomphy_phy_set; - p_api->phy_i2c_get = scomphy_phy_i2c_get; - p_api->phy_i2c_set = scomphy_phyi2c_set; -/*qca808x_end*/ - if(cfg->phy_id == MP_GEPHY) - { - p_api->reg_get = scomphy_reg_get; - p_api->reg_set = scomphy_reg_set; - p_api->uniphy_reg_get = scomphy_uniphy_reg_get; - p_api->uniphy_reg_set = scomphy_uniphy_reg_set; - } -/*qca808x_start*/ - return SW_OK; -} -/*qca808x_end*/ diff --git a/feeds/ipq807x/qca-ssdk/src/src/hsl/sfp/Makefile b/feeds/ipq807x/qca-ssdk/src/src/hsl/sfp/Makefile deleted file mode 100755 index 550ba4de2..000000000 --- a/feeds/ipq807x/qca-ssdk/src/src/hsl/sfp/Makefile +++ /dev/null @@ -1,16 +0,0 @@ -LOC_DIR=src/hsl/sfp -LIB=HSL - -include $(PRJ_PATH)/make/config.mk - -SRC_LIST= - -ifeq (TRUE, $(IN_SFP)) - SRC_LIST+=sfp.c sfp_access.c -endif - -include $(PRJ_PATH)/make/components.mk -include $(PRJ_PATH)/make/defs.mk -include $(PRJ_PATH)/make/target.mk - -all: dep obj diff --git a/feeds/ipq807x/qca-ssdk/src/src/hsl/sfp/sfp.c b/feeds/ipq807x/qca-ssdk/src/src/hsl/sfp/sfp.c deleted file mode 100644 index 4f5ca0f60..000000000 --- a/feeds/ipq807x/qca-ssdk/src/src/hsl/sfp/sfp.c +++ /dev/null @@ -1,2296 +0,0 @@ -/* - * Copyright (c) 2019, The Linux Foundation. All rights reserved. - * Permission to use, copy, modify, and/or distribute this software for - * any purpose with or without fee is hereby granted, provided that the - * above copyright notice and this permission notice appear in all copies. - * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES - * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR - * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES - * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN - * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT - * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. - */ - - -/** - * @defgroup - * @{ - */ -#include "sw.h" -#include "hsl.h" -#include "sfp_access.h" -#include "sfp_reg.h" - -sw_error_t -sfp_eeprom_data_get(a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t i2c_addr, - a_uint32_t offset, a_uint8_t *buf, a_uint32_t count) -{ - return sfp_data_tbl_get( - dev_id, index, i2c_addr, - offset, - buf, count); - -} - -sw_error_t -sfp_eeprom_data_set(a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t i2c_addr, - a_uint32_t offset, a_uint8_t *buf, a_uint32_t count) -{ - return sfp_data_tbl_set( - dev_id, index, i2c_addr, - offset, - buf, count); - -} - -sw_error_t -sfp_dev_type_get( - a_uint32_t dev_id, - a_uint32_t index, - union sfp_dev_type_u *value) -{ - return sfp_data_get( - dev_id, index, SFP_EEPROM_BASE_A0, - SFP_BASE_ADDR + SFP_DEV_TYPE_ADDRESS, - &value->val); -} - -sw_error_t -sfp_dev_type_ext_get( - a_uint32_t dev_id, - a_uint32_t index, - union sfp_dev_type_ext_u *value) -{ - return sfp_data_get( - dev_id, index, SFP_EEPROM_BASE_A0, - SFP_BASE_ADDR + SFP_DEV_TYPE_EXT_ADDRESS, - &value->val); -} - -sw_error_t -sfp_dev_connector_type_get( - a_uint32_t dev_id, - a_uint32_t index, - union sfp_dev_connector_type_u *value) -{ - return sfp_data_get( - dev_id, index, SFP_EEPROM_BASE_A0, - SFP_BASE_ADDR + SFP_DEV_CONNECTOR_TYPE_ADDRESS, - &value->val); -} - -sw_error_t -sfp_transc_get( - a_uint32_t dev_id, - a_uint32_t index, - union sfp_transc_u *value) -{ - return sfp_data_tbl_get( - dev_id, index, SFP_EEPROM_BASE_A0, - SFP_BASE_ADDR + SFP_TRANSC_ADDRESS, - value->val, 8); -} - -sw_error_t -sfp_encoding_get( - a_uint32_t dev_id, - a_uint32_t index, - union sfp_encoding_u *value) -{ - return sfp_data_get( - dev_id, index, SFP_EEPROM_BASE_A0, - SFP_BASE_ADDR + SFP_ENCODING_ADDRESS, - &value->val); -} - -sw_error_t -sfp_br_get( - a_uint32_t dev_id, - a_uint32_t index, - union sfp_br_u *value) -{ - return sfp_data_get( - dev_id, index, SFP_EEPROM_BASE_A0, - SFP_BASE_ADDR + SFP_BR_ADDRESS, - &value->val); -} - -sw_error_t -sfp_rate_get( - a_uint32_t dev_id, - a_uint32_t index, - union sfp_rate_u *value) -{ - return sfp_data_get( - dev_id, index, SFP_EEPROM_BASE_A0, - SFP_BASE_ADDR + SFP_RATE_ADDRESS, - &value->val); -} - -sw_error_t -sfp_link_len_get( - a_uint32_t dev_id, - a_uint32_t index, - union sfp_link_len_u *value) -{ - return sfp_data_tbl_get( - dev_id, index, SFP_EEPROM_BASE_A0, - SFP_BASE_ADDR + SFP_LINK_LEN_ADDRESS, - value->val, 6); -} - -sw_error_t -sfp_vendor_get( - a_uint32_t dev_id, - a_uint32_t index, - union sfp_vendor_u *value) -{ - return sfp_data_tbl_get( - dev_id, index, SFP_EEPROM_BASE_A0, - SFP_BASE_ADDR + SFP_VENDOR_ADDRESS, - value->val, 40); -} - -sw_error_t -sfp_laser_get( - a_uint32_t dev_id, - a_uint32_t index, - union sfp_laser_u *value) -{ - return sfp_data_tbl_get( - dev_id, index, SFP_EEPROM_BASE_A0, - SFP_BASE_ADDR + SFP_LASER_ADDRESS, - value->val, 2); -} - -sw_error_t -sfp_base_get( - a_uint32_t dev_id, - a_uint32_t index, - union sfp_base_u *value) -{ - return sfp_data_get( - dev_id, index, SFP_EEPROM_BASE_A0, - SFP_BASE_ADDR + SFP_BASE_ADDRESS, - &value->val); -} - -sw_error_t -sfp_option_get( - a_uint32_t dev_id, - a_uint32_t index, - union sfp_option_u *value) -{ - return sfp_data_tbl_get( - dev_id, index, SFP_EEPROM_BASE_A0, - SFP_BASE_ADDR + SFP_OPTION_ADDRESS, - value->val, 2); -} - -sw_error_t -sfp_rate_ctrl_get( - a_uint32_t dev_id, - a_uint32_t index, - union sfp_rate_ctrl_u *value) -{ - return sfp_data_tbl_get( - dev_id, index, SFP_EEPROM_BASE_A0, - SFP_BASE_ADDR + SFP_RATE_CTRL_ADDRESS, - value->val, 2); -} - -sw_error_t -sfp_vendor_ext_get( - a_uint32_t dev_id, - a_uint32_t index, - union sfp_vendor_ext_u *value) -{ - return sfp_data_tbl_get( - dev_id, index, SFP_EEPROM_BASE_A0, - SFP_BASE_ADDR + SFP_VENDOR_EXT_ADDRESS, - value->val, 24); -} - -sw_error_t -sfp_enhanced_get( - a_uint32_t dev_id, - a_uint32_t index, - union sfp_enhanced_u *value) -{ - return sfp_data_tbl_get( - dev_id, index, SFP_EEPROM_BASE_A0, - SFP_BASE_ADDR + SFP_ENHANCED_ADDRESS, - value->val, 3); -} - -sw_error_t -sfp_ext_get( - a_uint32_t dev_id, - a_uint32_t index, - union sfp_ext_u *value) -{ - return sfp_data_get( - dev_id, index, SFP_EEPROM_BASE_A0, - SFP_BASE_ADDR + SFP_EXT_ADDRESS, - &value->val); -} - -sw_error_t -sfp_dev_type_id_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union sfp_dev_type_u reg_val; - sw_error_t ret = SW_OK; - - ret = sfp_dev_type_get(dev_id, index, ®_val); - *value = reg_val.bf.id; - return ret; -} - -sw_error_t -sfp_dev_type_ext_id_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union sfp_dev_type_ext_u reg_val; - sw_error_t ret = SW_OK; - - ret = sfp_dev_type_ext_get(dev_id, index, ®_val); - *value = reg_val.bf.id; - return ret; -} - -sw_error_t -sfp_dev_connector_type_code_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union sfp_dev_connector_type_u reg_val; - sw_error_t ret = SW_OK; - - ret = sfp_dev_connector_type_get(dev_id, index, ®_val); - *value = reg_val.bf.code; - return ret; -} - -sw_error_t -sfp_transc_sonet_ccode_2_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union sfp_transc_u reg_val; - sw_error_t ret = SW_OK; - - ret = sfp_transc_get(dev_id, index, ®_val); - *value = reg_val.bf.sonet_ccode_2; - return ret; -} - -sw_error_t -sfp_transc_fiber_ch_tech_1_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union sfp_transc_u reg_val; - sw_error_t ret = SW_OK; - - ret = sfp_transc_get(dev_id, index, ®_val); - *value = reg_val.bf.fiber_ch_tech_1; - return ret; -} - -sw_error_t -sfp_transc_sonet_ccode_1_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union sfp_transc_u reg_val; - sw_error_t ret = SW_OK; - - ret = sfp_transc_get(dev_id, index, ®_val); - *value = reg_val.bf.sonet_ccode_1; - return ret; -} - -sw_error_t -sfp_transc_fiber_ch_speed_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union sfp_transc_u reg_val; - sw_error_t ret = SW_OK; - - ret = sfp_transc_get(dev_id, index, ®_val); - *value = reg_val.bf.fiber_ch_speed; - return ret; -} - -sw_error_t -sfp_transc_fiber_ch_tech_2_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union sfp_transc_u reg_val; - sw_error_t ret = SW_OK; - - ret = sfp_transc_get(dev_id, index, ®_val); - *value = reg_val.bf.fiber_ch_tech_2; - return ret; -} - -sw_error_t -sfp_transc_cable_tech_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union sfp_transc_u reg_val; - sw_error_t ret = SW_OK; - - ret = sfp_transc_get(dev_id, index, ®_val); - *value = reg_val.bf.cable_tech; - return ret; -} - -sw_error_t -sfp_transc_fiber_ch_link_len_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union sfp_transc_u reg_val; - sw_error_t ret = SW_OK; - - ret = sfp_transc_get(dev_id, index, ®_val); - *value = reg_val.bf.fiber_ch_link_len; - return ret; -} - -sw_error_t -sfp_transc_unallocated_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union sfp_transc_u reg_val; - sw_error_t ret = SW_OK; - - ret = sfp_transc_get(dev_id, index, ®_val); - *value = reg_val.bf.unallocated; - return ret; -} - -sw_error_t -sfp_transc_fiber_chan_tm_media_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union sfp_transc_u reg_val; - sw_error_t ret = SW_OK; - - ret = sfp_transc_get(dev_id, index, ®_val); - *value = reg_val.bf.fiber_chan_tm_media; - return ret; -} - -sw_error_t -sfp_transc_escon_ccode_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union sfp_transc_u reg_val; - sw_error_t ret = SW_OK; - - ret = sfp_transc_get(dev_id, index, ®_val); - *value = reg_val.bf.escon_ccode; - return ret; -} - -sw_error_t -sfp_transc_infiniband_ccode_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union sfp_transc_u reg_val; - sw_error_t ret = SW_OK; - - ret = sfp_transc_get(dev_id, index, ®_val); - *value = reg_val.bf.infiniband_ccode; - return ret; -} - -sw_error_t -sfp_transc_eth_ccode_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union sfp_transc_u reg_val; - sw_error_t ret = SW_OK; - - ret = sfp_transc_get(dev_id, index, ®_val); - *value = reg_val.bf.eth_ccode; - return ret; -} - -sw_error_t -sfp_transc_eth_10g_ccode_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union sfp_transc_u reg_val; - sw_error_t ret = SW_OK; - - ret = sfp_transc_get(dev_id, index, ®_val); - *value = reg_val.bf.eth_10g_ccode; - return ret; -} - -sw_error_t -sfp_encoding_code_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union sfp_encoding_u reg_val; - sw_error_t ret = SW_OK; - - ret = sfp_encoding_get(dev_id, index, ®_val); - *value = reg_val.bf.code; - return ret; -} - -sw_error_t -sfp_br_bit_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union sfp_br_u reg_val; - sw_error_t ret = SW_OK; - - ret = sfp_br_get(dev_id, index, ®_val); - *value = reg_val.bf.bit; - return ret; -} - -sw_error_t -sfp_rate_id_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union sfp_rate_u reg_val; - sw_error_t ret = SW_OK; - - ret = sfp_rate_get(dev_id, index, ®_val); - *value = reg_val.bf.id; - return ret; -} - -sw_error_t -sfp_link_len_om3_mode_1m_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union sfp_link_len_u reg_val; - sw_error_t ret = SW_OK; - - ret = sfp_link_len_get(dev_id, index, ®_val); - *value = reg_val.bf.om3_mode_1m; - return ret; -} - -sw_error_t -sfp_link_len_single_mode_100m_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union sfp_link_len_u reg_val; - sw_error_t ret = SW_OK; - - ret = sfp_link_len_get(dev_id, index, ®_val); - *value = reg_val.bf.single_mode_100m; - return ret; -} - -sw_error_t -sfp_link_len_om2_mode_10m_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union sfp_link_len_u reg_val; - sw_error_t ret = SW_OK; - - ret = sfp_link_len_get(dev_id, index, ®_val); - *value = reg_val.bf.om2_mode_10m; - return ret; -} - -sw_error_t -sfp_link_len_copper_mode_1m_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union sfp_link_len_u reg_val; - sw_error_t ret = SW_OK; - - ret = sfp_link_len_get(dev_id, index, ®_val); - *value = reg_val.bf.copper_mode_1m; - return ret; -} - -sw_error_t -sfp_link_len_om1_mode_10m_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union sfp_link_len_u reg_val; - sw_error_t ret = SW_OK; - - ret = sfp_link_len_get(dev_id, index, ®_val); - *value = reg_val.bf.om1_mode_10m; - return ret; -} - -sw_error_t -sfp_link_len_single_mode_km_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union sfp_link_len_u reg_val; - sw_error_t ret = SW_OK; - - ret = sfp_link_len_get(dev_id, index, ®_val); - *value = reg_val.bf.single_mode_km; - return ret; -} - -sw_error_t -sfp_vendor_rev_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint8_t value[4]) -{ - union sfp_vendor_u reg_val; - sw_error_t ret = SW_OK; - a_uint8_t i; - - ret = sfp_vendor_get(dev_id, index, ®_val); - - for (i = 0; i < 4; i++) { - value[i] = reg_val.val[i]; - } - - return ret; -} - -sw_error_t -sfp_vendor_name_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint8_t value[16]) -{ - union sfp_vendor_u reg_val; - sw_error_t ret = SW_OK; - a_uint8_t i; - - ret = sfp_vendor_get(dev_id, index, ®_val); - - for (i = 0; i < 16; i++) { - value[i] = reg_val.val[i]; - } - - return ret; -} - -sw_error_t -sfp_vendor_oui_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint8_t value[3]) -{ - union sfp_vendor_u reg_val; - sw_error_t ret = SW_OK; - a_uint8_t i; - - ret = sfp_vendor_get(dev_id, index, ®_val); - - for (i = 0; i < 3; i++) { - value[i] = reg_val.val[i]; - } - - return ret; -} - -sw_error_t -sfp_vendor_pn_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint8_t value[16]) -{ - union sfp_vendor_u reg_val; - sw_error_t ret = SW_OK; - a_uint8_t i; - - ret = sfp_vendor_get(dev_id, index, ®_val); - - for (i = 0; i < 16; i++) { - value[i] = reg_val.val[i]; - } - - return ret; -} -sw_error_t -sfp_laser_wavelength_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union sfp_laser_u reg_val; - sw_error_t ret = SW_OK; - - ret = sfp_laser_get(dev_id, index, ®_val); - *value = reg_val.bf.wavelength_0 << 8 - | reg_val.bf.wavelength_1; - return ret; -} - -sw_error_t -sfp_base_check_code_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union sfp_base_u reg_val; - sw_error_t ret = SW_OK; - - ret = sfp_base_get(dev_id, index, ®_val); - *value = reg_val.bf.check_code; - return ret; -} - -sw_error_t -sfp_option_linear_recv_output_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union sfp_option_u reg_val; - sw_error_t ret = SW_OK; - - ret = sfp_option_get(dev_id, index, ®_val); - *value = reg_val.bf.linear_recv_output; - return ret; -} - -sw_error_t -sfp_option_pwr_level_declar_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union sfp_option_u reg_val; - sw_error_t ret = SW_OK; - - ret = sfp_option_get(dev_id, index, ®_val); - *value = reg_val.bf.pwr_level_declar; - return ret; -} - -sw_error_t -sfp_option_unallocated_1_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union sfp_option_u reg_val; - sw_error_t ret = SW_OK; - - ret = sfp_option_get(dev_id, index, ®_val); - *value = reg_val.bf.unallocated_1; - return ret; -} - -sw_error_t -sfp_option_unallocated_3_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union sfp_option_u reg_val; - sw_error_t ret = SW_OK; - - ret = sfp_option_get(dev_id, index, ®_val); - *value = reg_val.bf.unallocated_3; - return ret; -} - -sw_error_t -sfp_option_loss_signal_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union sfp_option_u reg_val; - sw_error_t ret = SW_OK; - - ret = sfp_option_get(dev_id, index, ®_val); - *value = reg_val.bf.loss_signal; - return ret; -} - -sw_error_t -sfp_option_rate_sel_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union sfp_option_u reg_val; - sw_error_t ret = SW_OK; - - ret = sfp_option_get(dev_id, index, ®_val); - *value = reg_val.bf.rate_sel; - return ret; -} - -sw_error_t -sfp_option_unallocated_2_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union sfp_option_u reg_val; - sw_error_t ret = SW_OK; - - ret = sfp_option_get(dev_id, index, ®_val); - *value = reg_val.bf.unallocated_2; - return ret; -} - -sw_error_t -sfp_option_loss_invert_signal_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union sfp_option_u reg_val; - sw_error_t ret = SW_OK; - - ret = sfp_option_get(dev_id, index, ®_val); - *value = reg_val.bf.loss_invert_signal; - return ret; -} - -sw_error_t -sfp_option_tx_disable_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union sfp_option_u reg_val; - sw_error_t ret = SW_OK; - - ret = sfp_option_get(dev_id, index, ®_val); - *value = reg_val.bf.tx_disable; - return ret; -} - -sw_error_t -sfp_option_cool_transc_declar_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union sfp_option_u reg_val; - sw_error_t ret = SW_OK; - - ret = sfp_option_get(dev_id, index, ®_val); - *value = reg_val.bf.cool_transc_declar; - return ret; -} - -sw_error_t -sfp_option_tx_fault_signal_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union sfp_option_u reg_val; - sw_error_t ret = SW_OK; - - ret = sfp_option_get(dev_id, index, ®_val); - *value = reg_val.bf.tx_fault_signal; - return ret; -} - -sw_error_t -sfp_rate_ctrl_upper_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union sfp_rate_ctrl_u reg_val; - sw_error_t ret = SW_OK; - - ret = sfp_rate_ctrl_get(dev_id, index, ®_val); - *value = reg_val.bf.upper; - return ret; -} - -sw_error_t -sfp_rate_ctrl_lower_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union sfp_rate_ctrl_u reg_val; - sw_error_t ret = SW_OK; - - ret = sfp_rate_ctrl_get(dev_id, index, ®_val); - *value = reg_val.bf.lower; - return ret; -} - -sw_error_t -sfp_vendor_ext_date_code_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint8_t value[8]) -{ - union sfp_vendor_ext_u reg_val; - sw_error_t ret = SW_OK; - a_uint8_t i; - - ret = sfp_vendor_ext_get(dev_id, index, ®_val); - - for (i = 0; i < 8; i++) { - value[i] = reg_val.val[i]; - } - - return ret; -} - -sw_error_t -sfp_vendor_ext_sn_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint8_t value[16]) -{ - union sfp_vendor_ext_u reg_val; - sw_error_t ret = SW_OK; - a_uint8_t i; - - ret = sfp_vendor_ext_get(dev_id, index, ®_val); - - for (i = 0; i < 16; i++) { - value[i] = reg_val.val[i]; - } - - return ret; -} - -sw_error_t -sfp_enhanced_diag_mon_flag_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union sfp_enhanced_u reg_val; - sw_error_t ret = SW_OK; - - ret = sfp_enhanced_get(dev_id, index, ®_val); - *value = reg_val.bf.diag_mon_flag; - return ret; -} - -sw_error_t -sfp_enhanced_rx_los_op_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union sfp_enhanced_u reg_val; - sw_error_t ret = SW_OK; - - ret = sfp_enhanced_get(dev_id, index, ®_val); - *value = reg_val.bf.rx_los_op; - return ret; -} - -sw_error_t -sfp_enhanced_cmpl_feature_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union sfp_enhanced_u reg_val; - sw_error_t ret = SW_OK; - - ret = sfp_enhanced_get(dev_id, index, ®_val); - *value = reg_val.bf.cmpl_feature; - return ret; -} - -sw_error_t -sfp_enhanced_tx_disable_ctrl_op_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union sfp_enhanced_u reg_val; - sw_error_t ret = SW_OK; - - ret = sfp_enhanced_get(dev_id, index, ®_val); - *value = reg_val.bf.tx_disable_ctrl_op; - return ret; -} - -sw_error_t -sfp_enhanced_alarm_warning_flag_op_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union sfp_enhanced_u reg_val; - sw_error_t ret = SW_OK; - - ret = sfp_enhanced_get(dev_id, index, ®_val); - *value = reg_val.bf.alarm_warning_flag_op; - return ret; -} - -sw_error_t -sfp_enhanced_addr_mode_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union sfp_enhanced_u reg_val; - sw_error_t ret = SW_OK; - - ret = sfp_enhanced_get(dev_id, index, ®_val); - *value = reg_val.bf.addr_mode; - return ret; -} - -sw_error_t -sfp_enhanced_unallocated_op_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union sfp_enhanced_u reg_val; - sw_error_t ret = SW_OK; - - ret = sfp_enhanced_get(dev_id, index, ®_val); - *value = reg_val.bf.unallocated_op; - return ret; -} - -sw_error_t -sfp_enhanced_soft_rate_sel_op_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union sfp_enhanced_u reg_val; - sw_error_t ret = SW_OK; - - ret = sfp_enhanced_get(dev_id, index, ®_val); - *value = reg_val.bf.soft_rate_sel_op; - return ret; -} - -sw_error_t -sfp_enhanced_external_cal_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union sfp_enhanced_u reg_val; - sw_error_t ret = SW_OK; - - ret = sfp_enhanced_get(dev_id, index, ®_val); - *value = reg_val.bf.external_cal; - return ret; -} - -sw_error_t -sfp_enhanced_internal_cal_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union sfp_enhanced_u reg_val; - sw_error_t ret = SW_OK; - - ret = sfp_enhanced_get(dev_id, index, ®_val); - *value = reg_val.bf.internal_cal; - return ret; -} - -sw_error_t -sfp_enhanced_re_pwr_type_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union sfp_enhanced_u reg_val; - sw_error_t ret = SW_OK; - - ret = sfp_enhanced_get(dev_id, index, ®_val); - *value = reg_val.bf.re_pwr_type; - return ret; -} - -sw_error_t -sfp_enhanced_soft_rate_ctrl_op_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union sfp_enhanced_u reg_val; - sw_error_t ret = SW_OK; - - ret = sfp_enhanced_get(dev_id, index, ®_val); - *value = reg_val.bf.soft_rate_ctrl_op; - return ret; -} - -sw_error_t -sfp_enhanced_app_sel_op_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union sfp_enhanced_u reg_val; - sw_error_t ret = SW_OK; - - ret = sfp_enhanced_get(dev_id, index, ®_val); - *value = reg_val.bf.app_sel_op; - return ret; -} - -sw_error_t -sfp_enhanced_legacy_type_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union sfp_enhanced_u reg_val; - sw_error_t ret = SW_OK; - - ret = sfp_enhanced_get(dev_id, index, ®_val); - *value = reg_val.bf.legacy_type; - return ret; -} - -sw_error_t -sfp_enhanced_tx_fault_op_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union sfp_enhanced_u reg_val; - sw_error_t ret = SW_OK; - - ret = sfp_enhanced_get(dev_id, index, ®_val); - *value = reg_val.bf.tx_fault_op; - return ret; -} - -sw_error_t -sfp_enhanced_unallocated_type_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union sfp_enhanced_u reg_val; - sw_error_t ret = SW_OK; - - ret = sfp_enhanced_get(dev_id, index, ®_val); - *value = reg_val.bf.unallocated_type; - return ret; -} - -sw_error_t -sfp_ext_check_code_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union sfp_ext_u reg_val; - sw_error_t ret = SW_OK; - - ret = sfp_ext_get(dev_id, index, ®_val); - *value = reg_val.bf.check_code; - return ret; -} - -sw_error_t -sfp_diag_threshold_get( - a_uint32_t dev_id, - a_uint32_t index, - union sfp_diag_threshold_u *value) -{ - return sfp_data_tbl_get( - dev_id, index, SFP_EEPROM_DIAG_A2, - SFP_DIAG_BASE_ADDR + SFP_DIAG_THRESHOLD_ADDRESS, - value->val, 40); -} - -sw_error_t -sfp_diag_cal_const_get( - a_uint32_t dev_id, - a_uint32_t index, - union sfp_diag_cal_const_u *value) -{ - return sfp_data_tbl_get( - dev_id, index, SFP_EEPROM_DIAG_A2, - SFP_DIAG_BASE_ADDR + SFP_DIAG_CAL_CONST_ADDRESS, - value->val, 36); -} - -sw_error_t -sfp_diag_dmi_get( - a_uint32_t dev_id, - a_uint32_t index, - union sfp_diag_dmi_u *value) -{ - return sfp_data_get( - dev_id, index, SFP_EEPROM_DIAG_A2, - SFP_DIAG_BASE_ADDR + SFP_DIAG_DMI_ADDRESS, - &value->val); -} - -sw_error_t -sfp_diag_realtime_get( - a_uint32_t dev_id, - a_uint32_t index, - union sfp_diag_realtime_u *value) -{ - return sfp_data_tbl_get( - dev_id, index, SFP_EEPROM_DIAG_A2, - SFP_DIAG_BASE_ADDR + SFP_DIAG_REALTIME_ADDRESS, - value->val, 10); -} - -sw_error_t -sfp_diag_optional_ctrl_status_get( - a_uint32_t dev_id, - a_uint32_t index, - union sfp_diag_optional_ctrl_status_u *value) -{ - return sfp_data_get( - dev_id, index, SFP_EEPROM_DIAG_A2, - SFP_DIAG_BASE_ADDR + SFP_DIAG_OPTIONAL_CTRL_STATUS_ADDRESS, - value->val); -} - -sw_error_t -sfp_diag_flag_get( - a_uint32_t dev_id, - a_uint32_t index, - union sfp_diag_flag_u *value) -{ - return sfp_data_tbl_get( - dev_id, index, SFP_EEPROM_DIAG_A2, - SFP_DIAG_BASE_ADDR + SFP_DIAG_FLAG_ADDRESS, - value->val, 6); -} - -sw_error_t -sfp_diag_extended_ctrl_status_get( - a_uint32_t dev_id, - a_uint32_t index, - union sfp_diag_extended_ctrl_status_u *value) -{ - return sfp_data_tbl_get( - dev_id, index, SFP_EEPROM_DIAG_A2, - SFP_DIAG_BASE_ADDR + SFP_DIAG_EXTENDED_CTRL_STATUS_ADDRESS, - value->val, 2); -} - -sw_error_t -sfp_diag_threshold_rx_pwr_low_alarm_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union sfp_diag_threshold_u reg_val; - sw_error_t ret = SW_OK; - - ret = sfp_diag_threshold_get(dev_id, index, ®_val); - *value = reg_val.bf.rx_pwr_low_alarm_0 << 8 | \ - reg_val.bf.rx_pwr_low_alarm_1; - return ret; -} - -sw_error_t -sfp_diag_threshold_rx_pwr_high_warning_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union sfp_diag_threshold_u reg_val; - sw_error_t ret = SW_OK; - - ret = sfp_diag_threshold_get(dev_id, index, ®_val); - *value = reg_val.bf.rx_pwr_high_warning_0 << 8 | \ - reg_val.bf.rx_pwr_high_warning_1; - return ret; -} - -sw_error_t -sfp_diag_threshold_temp_low_alarm_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union sfp_diag_threshold_u reg_val; - sw_error_t ret = SW_OK; - - ret = sfp_diag_threshold_get(dev_id, index, ®_val); - *value = reg_val.bf.temp_low_alarm_0 << 8 | \ - reg_val.bf.temp_low_alarm_1; - return ret; -} - -sw_error_t -sfp_diag_threshold_vol_high_alarm_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union sfp_diag_threshold_u reg_val; - sw_error_t ret = SW_OK; - - ret = sfp_diag_threshold_get(dev_id, index, ®_val); - *value = reg_val.bf.vol_high_alarm_0 << 8 | \ - reg_val.bf.vol_high_alarm_1; - return ret; -} - -sw_error_t -sfp_diag_threshold_tx_pwr_high_alarm_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union sfp_diag_threshold_u reg_val; - sw_error_t ret = SW_OK; - - ret = sfp_diag_threshold_get(dev_id, index, ®_val); - *value = reg_val.bf.tx_pwr_high_alarm_0 << 8 | \ - reg_val.bf.tx_pwr_high_alarm_1; - return ret; -} - -sw_error_t -sfp_diag_threshold_bias_low_alarm_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union sfp_diag_threshold_u reg_val; - sw_error_t ret = SW_OK; - - ret = sfp_diag_threshold_get(dev_id, index, ®_val); - *value = reg_val.bf.bias_low_alarm_0 << 8 | \ - reg_val.bf.bias_low_alarm_1; - return ret; -} - -sw_error_t -sfp_diag_threshold_bias_high_alarm_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union sfp_diag_threshold_u reg_val; - sw_error_t ret = SW_OK; - - ret = sfp_diag_threshold_get(dev_id, index, ®_val); - *value = reg_val.bf.bias_high_alarm_0 << 8 | \ - reg_val.bf.bias_high_alarm_1; - return ret; -} - -sw_error_t -sfp_diag_threshold_vol_low_alarm_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union sfp_diag_threshold_u reg_val; - sw_error_t ret = SW_OK; - - ret = sfp_diag_threshold_get(dev_id, index, ®_val); - *value = reg_val.bf.vol_low_alarm_0 << 8 | \ - reg_val.bf.vol_low_alarm_1; - return ret; -} - -sw_error_t -sfp_diag_threshold_bias_high_warning_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union sfp_diag_threshold_u reg_val; - sw_error_t ret = SW_OK; - - ret = sfp_diag_threshold_get(dev_id, index, ®_val); - *value = reg_val.bf.bias_high_warning_0 << 8 | \ - reg_val.bf.bias_high_warning_1; - return ret; -} - -sw_error_t -sfp_diag_threshold_temp_high_warning_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union sfp_diag_threshold_u reg_val; - sw_error_t ret = SW_OK; - - ret = sfp_diag_threshold_get(dev_id, index, ®_val); - *value = reg_val.bf.temp_high_warning_0 << 8 | \ - reg_val.bf.temp_high_warning_1; - return ret; -} - -sw_error_t -sfp_diag_threshold_rx_pwr_low_warning_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union sfp_diag_threshold_u reg_val; - sw_error_t ret = SW_OK; - - ret = sfp_diag_threshold_get(dev_id, index, ®_val); - *value = reg_val.bf.rx_pwr_low_warning_0 << 8 | \ - reg_val.bf.rx_pwr_low_warning_1; - return ret; -} - -sw_error_t -sfp_diag_threshold_vol_low_warning_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union sfp_diag_threshold_u reg_val; - sw_error_t ret = SW_OK; - - ret = sfp_diag_threshold_get(dev_id, index, ®_val); - *value = reg_val.bf.vol_low_warning_0 << 8 | \ - reg_val.bf.vol_low_warning_1; - return ret; -} - -sw_error_t -sfp_diag_threshold_tx_pwr_low_alarm_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union sfp_diag_threshold_u reg_val; - sw_error_t ret = SW_OK; - - ret = sfp_diag_threshold_get(dev_id, index, ®_val); - *value = reg_val.bf.tx_pwr_low_alarm_0 << 8 | \ - reg_val.bf.tx_pwr_low_alarm_1; - return ret; -} - -sw_error_t -sfp_diag_threshold_bias_low_warning_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union sfp_diag_threshold_u reg_val; - sw_error_t ret = SW_OK; - - ret = sfp_diag_threshold_get(dev_id, index, ®_val); - *value = reg_val.bf.bias_low_warning_0 << 8 | \ - reg_val.bf.bias_low_warning_1; - return ret; -} - -sw_error_t -sfp_diag_threshold_temp_high_alarm_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union sfp_diag_threshold_u reg_val; - sw_error_t ret = SW_OK; - - ret = sfp_diag_threshold_get(dev_id, index, ®_val); - *value = reg_val.bf.temp_high_alarm_0 << 8 | \ - reg_val.bf.temp_high_alarm_1; - return ret; -} - -sw_error_t -sfp_diag_threshold_tx_pwr_high_warning_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union sfp_diag_threshold_u reg_val; - sw_error_t ret = SW_OK; - - ret = sfp_diag_threshold_get(dev_id, index, ®_val); - *value = reg_val.bf.tx_pwr_high_warning_0 << 8 | \ - reg_val.bf.tx_pwr_high_warning_1; - return ret; -} - -sw_error_t -sfp_diag_threshold_vol_high_warning_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union sfp_diag_threshold_u reg_val; - sw_error_t ret = SW_OK; - - ret = sfp_diag_threshold_get(dev_id, index, ®_val); - *value = reg_val.bf.vol_high_warning_0 << 8 | \ - reg_val.bf.vol_high_warning_1; - return ret; -} - -sw_error_t -sfp_diag_threshold_temp_low_warning_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union sfp_diag_threshold_u reg_val; - sw_error_t ret = SW_OK; - - ret = sfp_diag_threshold_get(dev_id, index, ®_val); - *value = reg_val.bf.temp_low_warning_0 << 8 | \ - reg_val.bf.temp_low_warning_1; - return ret; -} - -sw_error_t -sfp_diag_threshold_rx_pwr_high_alarm_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union sfp_diag_threshold_u reg_val; - sw_error_t ret = SW_OK; - - ret = sfp_diag_threshold_get(dev_id, index, ®_val); - *value = reg_val.bf.rx_pwr_high_alarm_0 << 8 | \ - reg_val.bf.rx_pwr_high_alarm_1; - return ret; -} - -sw_error_t -sfp_diag_threshold_tx_pwr_low_warning_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union sfp_diag_threshold_u reg_val; - sw_error_t ret = SW_OK; - - ret = sfp_diag_threshold_get(dev_id, index, ®_val); - *value = reg_val.bf.tx_pwr_low_warning_0 << 8 | \ - reg_val.bf.tx_pwr_low_warning_1; - return ret; -} - -sw_error_t -sfp_diag_cal_const_rx_pwr_1_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union sfp_diag_cal_const_u reg_val; - sw_error_t ret = SW_OK; - - ret = sfp_diag_cal_const_get(dev_id, index, ®_val); - *value = reg_val.bf.rx_pwr_1_0 << 24 | \ - reg_val.bf.rx_pwr_1_1 << 16 | \ - reg_val.bf.rx_pwr_1_2 << 8 | \ - reg_val.bf.rx_pwr_1_3; - return ret; -} - -sw_error_t -sfp_diag_cal_const_t_slope_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union sfp_diag_cal_const_u reg_val; - sw_error_t ret = SW_OK; - - ret = sfp_diag_cal_const_get(dev_id, index, ®_val); - *value = reg_val.bf.t_slope_0 << 8 | \ - reg_val.bf.t_slope_1; - return ret; -} - -sw_error_t -sfp_diag_cal_const_rx_pwr_3_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union sfp_diag_cal_const_u reg_val; - sw_error_t ret = SW_OK; - - ret = sfp_diag_cal_const_get(dev_id, index, ®_val); - *value = reg_val.bf.rx_pwr_3_0 << 24 | \ - reg_val.bf.rx_pwr_3_1 << 16 | \ - reg_val.bf.rx_pwr_3_2 << 8 | \ - reg_val.bf.rx_pwr_3_3; - return ret; -} - -sw_error_t -sfp_diag_cal_const_v_offset_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union sfp_diag_cal_const_u reg_val; - sw_error_t ret = SW_OK; - - ret = sfp_diag_cal_const_get(dev_id, index, ®_val); - *value = reg_val.bf.v_offset_0 << 8 | \ - reg_val.bf.v_offset_1; - return ret; -} - -sw_error_t -sfp_diag_cal_const_rx_pwr_2_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union sfp_diag_cal_const_u reg_val; - sw_error_t ret = SW_OK; - - ret = sfp_diag_cal_const_get(dev_id, index, ®_val); - *value = reg_val.bf.rx_pwr_2_0 << 24 | \ - reg_val.bf.rx_pwr_2_1 << 16 | \ - reg_val.bf.rx_pwr_2_2 << 8 | \ - reg_val.bf.rx_pwr_2_3; - return ret; -} - -sw_error_t -sfp_diag_cal_const_tx_i_slope_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union sfp_diag_cal_const_u reg_val; - sw_error_t ret = SW_OK; - - ret = sfp_diag_cal_const_get(dev_id, index, ®_val); - *value = reg_val.bf.tx_i_slope_0 << 8 | \ - reg_val.bf.tx_i_slope_1; - return ret; -} - -sw_error_t -sfp_diag_cal_const_tx_i_offset_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union sfp_diag_cal_const_u reg_val; - sw_error_t ret = SW_OK; - - ret = sfp_diag_cal_const_get(dev_id, index, ®_val); - *value = reg_val.bf.tx_i_offset_0 << 8 | \ - reg_val.bf.tx_i_offset_1; - return ret; -} - -sw_error_t -sfp_diag_cal_const_v_slope_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union sfp_diag_cal_const_u reg_val; - sw_error_t ret = SW_OK; - - ret = sfp_diag_cal_const_get(dev_id, index, ®_val); - *value = reg_val.bf.v_slope_0 << 8 | \ - reg_val.bf.v_slope_1; - return ret; -} - -sw_error_t -sfp_diag_cal_const_t_offset_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union sfp_diag_cal_const_u reg_val; - sw_error_t ret = SW_OK; - - ret = sfp_diag_cal_const_get(dev_id, index, ®_val); - *value = reg_val.bf.t_offset_0 << 8 | \ - reg_val.bf.t_offset_1; - return ret; -} - -sw_error_t -sfp_diag_cal_const_tx_pwr_offset_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union sfp_diag_cal_const_u reg_val; - sw_error_t ret = SW_OK; - - ret = sfp_diag_cal_const_get(dev_id, index, ®_val); - *value = reg_val.bf.tx_pwr_offset_0 << 8 | \ - reg_val.bf.tx_pwr_offset_1; - return ret; -} - -sw_error_t -sfp_diag_cal_const_tx_pwr_slope_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union sfp_diag_cal_const_u reg_val; - sw_error_t ret = SW_OK; - - ret = sfp_diag_cal_const_get(dev_id, index, ®_val); - *value = reg_val.bf.tx_pwr_slope_0 << 8 | \ - reg_val.bf.tx_pwr_slope_1; - return ret; -} - -sw_error_t -sfp_diag_cal_const_rx_pwr_4_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union sfp_diag_cal_const_u reg_val; - sw_error_t ret = SW_OK; - - ret = sfp_diag_cal_const_get(dev_id, index, ®_val); - *value = reg_val.bf.rx_pwr_4_0 << 24 | \ - reg_val.bf.rx_pwr_4_1 << 16 | \ - reg_val.bf.rx_pwr_4_2 << 8 | \ - reg_val.bf.rx_pwr_4_3; - return ret; -} - -sw_error_t -sfp_diag_cal_const_rx_pwr_0_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union sfp_diag_cal_const_u reg_val; - sw_error_t ret = SW_OK; - - ret = sfp_diag_cal_const_get(dev_id, index, ®_val); - *value = reg_val.bf.rx_pwr_0_0 << 24 | \ - reg_val.bf.rx_pwr_0_1 << 16 | \ - reg_val.bf.rx_pwr_0_2 << 8 | \ - reg_val.bf.rx_pwr_0_3; - return ret; -} - -sw_error_t -sfp_diag_dmi_check_code_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union sfp_diag_dmi_u reg_val; - sw_error_t ret = SW_OK; - - ret = sfp_diag_dmi_get(dev_id, index, ®_val); - *value = reg_val.bf.check_code; - return ret; -} - -sw_error_t -sfp_diag_realtime_vcc_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union sfp_diag_realtime_u reg_val; - sw_error_t ret = SW_OK; - - ret = sfp_diag_realtime_get(dev_id, index, ®_val); - *value = reg_val.bf.vcc_1 << 8 | \ - reg_val.bf.vcc_0; - return ret; -} - -sw_error_t -sfp_diag_realtime_tx_pwr_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union sfp_diag_realtime_u reg_val; - sw_error_t ret = SW_OK; - - ret = sfp_diag_realtime_get(dev_id, index, ®_val); - *value = reg_val.bf.tx_pwr_1 << 8 | \ - reg_val.bf.tx_pwr_0; - return ret; -} - -sw_error_t -sfp_diag_realtime_tx_bias_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union sfp_diag_realtime_u reg_val; - sw_error_t ret = SW_OK; - - ret = sfp_diag_realtime_get(dev_id, index, ®_val); - *value = reg_val.bf.tx_bias_1 << 8 | \ - reg_val.bf.tx_bias_0; - return ret; -} - -sw_error_t -sfp_diag_realtime_rx_pwr_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union sfp_diag_realtime_u reg_val; - sw_error_t ret = SW_OK; - - ret = sfp_diag_realtime_get(dev_id, index, ®_val); - *value = reg_val.bf.rx_pwr_1 << 8 | \ - reg_val.bf.rx_pwr_0; - return ret; -} - -sw_error_t -sfp_diag_realtime_tmp_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union sfp_diag_realtime_u reg_val; - sw_error_t ret = SW_OK; - - ret = sfp_diag_realtime_get(dev_id, index, ®_val); - *value = reg_val.bf.tmp_1 << 8 | \ - reg_val.bf.tmp_0; - return ret; -} - -sw_error_t -sfp_diag_optional_ctrl_status_rs_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union sfp_diag_optional_ctrl_status_u reg_val; - sw_error_t ret = SW_OK; - - ret = sfp_diag_optional_ctrl_status_get(dev_id, index, ®_val); - *value = reg_val.bf.rs; - return ret; -} - -sw_error_t -sfp_diag_optional_ctrl_status_tx_fault_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union sfp_diag_optional_ctrl_status_u reg_val; - sw_error_t ret = SW_OK; - - ret = sfp_diag_optional_ctrl_status_get(dev_id, index, ®_val); - *value = reg_val.bf.tx_fault; - return ret; -} - -sw_error_t -sfp_diag_optional_ctrl_status_rx_los_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union sfp_diag_optional_ctrl_status_u reg_val; - sw_error_t ret = SW_OK; - - ret = sfp_diag_optional_ctrl_status_get(dev_id, index, ®_val); - *value = reg_val.bf.rx_los; - return ret; -} - -sw_error_t -sfp_diag_optional_ctrl_status_data_ready_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union sfp_diag_optional_ctrl_status_u reg_val; - sw_error_t ret = SW_OK; - - ret = sfp_diag_optional_ctrl_status_get(dev_id, index, ®_val); - *value = reg_val.bf.data_ready; - return ret; -} - -sw_error_t -sfp_diag_optional_ctrl_status_soft_rate_sel_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union sfp_diag_optional_ctrl_status_u reg_val; - sw_error_t ret = SW_OK; - - ret = sfp_diag_optional_ctrl_status_get(dev_id, index, ®_val); - *value = reg_val.bf.soft_rate_sel; - return ret; -} - -sw_error_t -sfp_diag_optional_ctrl_status_soft_tx_disable_sel_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union sfp_diag_optional_ctrl_status_u reg_val; - sw_error_t ret = SW_OK; - - ret = sfp_diag_optional_ctrl_status_get(dev_id, index, ®_val); - *value = reg_val.bf.soft_tx_disable_sel; - return ret; -} - -sw_error_t -sfp_diag_optional_ctrl_status_rate_sel_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union sfp_diag_optional_ctrl_status_u reg_val; - sw_error_t ret = SW_OK; - - ret = sfp_diag_optional_ctrl_status_get(dev_id, index, ®_val); - *value = reg_val.bf.rate_sel; - return ret; -} - -sw_error_t -sfp_diag_optional_ctrl_status_tx_disable_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union sfp_diag_optional_ctrl_status_u reg_val; - sw_error_t ret = SW_OK; - - ret = sfp_diag_optional_ctrl_status_get(dev_id, index, ®_val); - *value = reg_val.bf.tx_disable; - return ret; -} - -sw_error_t -sfp_diag_flag_rx_pwr_low_alarm_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union sfp_diag_flag_u reg_val; - sw_error_t ret = SW_OK; - - ret = sfp_diag_flag_get(dev_id, index, ®_val); - *value = reg_val.bf.rx_pwr_low_alarm; - return ret; -} - -sw_error_t -sfp_diag_flag_rx_pwr_high_warning_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union sfp_diag_flag_u reg_val; - sw_error_t ret = SW_OK; - - ret = sfp_diag_flag_get(dev_id, index, ®_val); - *value = reg_val.bf.rx_pwr_high_warning; - return ret; -} - -sw_error_t -sfp_diag_flag_tx_bias_high_alarm_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union sfp_diag_flag_u reg_val; - sw_error_t ret = SW_OK; - - ret = sfp_diag_flag_get(dev_id, index, ®_val); - *value = reg_val.bf.tx_bias_high_alarm; - return ret; -} - -sw_error_t -sfp_diag_flag_tmp_high_alarm_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union sfp_diag_flag_u reg_val; - sw_error_t ret = SW_OK; - - ret = sfp_diag_flag_get(dev_id, index, ®_val); - *value = reg_val.bf.tmp_high_alarm; - return ret; -} - -sw_error_t -sfp_diag_flag_tmp_low_alarm_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union sfp_diag_flag_u reg_val; - sw_error_t ret = SW_OK; - - ret = sfp_diag_flag_get(dev_id, index, ®_val); - *value = reg_val.bf.tmp_low_alarm; - return ret; -} - -sw_error_t -sfp_diag_flag_tx_pwr_high_alarm_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union sfp_diag_flag_u reg_val; - sw_error_t ret = SW_OK; - - ret = sfp_diag_flag_get(dev_id, index, ®_val); - *value = reg_val.bf.tx_pwr_high_alarm; - return ret; -} - -sw_error_t -sfp_diag_flag_vcc_low_warning_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union sfp_diag_flag_u reg_val; - sw_error_t ret = SW_OK; - - ret = sfp_diag_flag_get(dev_id, index, ®_val); - *value = reg_val.bf.vcc_low_warning; - return ret; -} - -sw_error_t -sfp_diag_flag_vcc_high_warning_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union sfp_diag_flag_u reg_val; - sw_error_t ret = SW_OK; - - ret = sfp_diag_flag_get(dev_id, index, ®_val); - *value = reg_val.bf.vcc_high_warning; - return ret; -} - -sw_error_t -sfp_diag_flag_rx_pwr_low_warning_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union sfp_diag_flag_u reg_val; - sw_error_t ret = SW_OK; - - ret = sfp_diag_flag_get(dev_id, index, ®_val); - *value = reg_val.bf.rx_pwr_low_warning; - return ret; -} - -sw_error_t -sfp_diag_flag_unallocated_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union sfp_diag_flag_u reg_val; - sw_error_t ret = SW_OK; - - ret = sfp_diag_flag_get(dev_id, index, ®_val); - *value = reg_val.bf.unallocated_1 << 8 | \ - reg_val.bf.unallocated_0; - return ret; -} - -sw_error_t -sfp_diag_flag_tx_bias_high_warning_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union sfp_diag_flag_u reg_val; - sw_error_t ret = SW_OK; - - ret = sfp_diag_flag_get(dev_id, index, ®_val); - *value = reg_val.bf.tx_bias_high_warning; - return ret; -} - -sw_error_t -sfp_diag_flag_vcc_low_alarm_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union sfp_diag_flag_u reg_val; - sw_error_t ret = SW_OK; - - ret = sfp_diag_flag_get(dev_id, index, ®_val); - *value = reg_val.bf.vcc_low_alarm; - return ret; -} - -sw_error_t -sfp_diag_flag_tx_pwr_low_alarm_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union sfp_diag_flag_u reg_val; - sw_error_t ret = SW_OK; - - ret = sfp_diag_flag_get(dev_id, index, ®_val); - *value = reg_val.bf.tx_pwr_low_alarm; - return ret; -} - -sw_error_t -sfp_diag_flag_vcc_high_alarm_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union sfp_diag_flag_u reg_val; - sw_error_t ret = SW_OK; - - ret = sfp_diag_flag_get(dev_id, index, ®_val); - *value = reg_val.bf.vcc_high_alarm; - return ret; -} - -sw_error_t -sfp_diag_flag_tmp_low_warning_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union sfp_diag_flag_u reg_val; - sw_error_t ret = SW_OK; - - ret = sfp_diag_flag_get(dev_id, index, ®_val); - *value = reg_val.bf.tmp_low_warning; - return ret; -} - -sw_error_t -sfp_diag_flag_tx_bias_low_warning_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union sfp_diag_flag_u reg_val; - sw_error_t ret = SW_OK; - - ret = sfp_diag_flag_get(dev_id, index, ®_val); - *value = reg_val.bf.tx_bias_low_warning; - return ret; -} - -sw_error_t -sfp_diag_flag_tx_bias_low_alarm_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union sfp_diag_flag_u reg_val; - sw_error_t ret = SW_OK; - - ret = sfp_diag_flag_get(dev_id, index, ®_val); - *value = reg_val.bf.tx_bias_low_alarm; - return ret; -} - -sw_error_t -sfp_diag_flag_tmp_high_warning_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union sfp_diag_flag_u reg_val; - sw_error_t ret = SW_OK; - - ret = sfp_diag_flag_get(dev_id, index, ®_val); - *value = reg_val.bf.tmp_high_warning; - return ret; -} - -sw_error_t -sfp_diag_flag_tx_pwr_high_warning_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union sfp_diag_flag_u reg_val; - sw_error_t ret = SW_OK; - - ret = sfp_diag_flag_get(dev_id, index, ®_val); - *value = reg_val.bf.tx_pwr_high_warning; - return ret; -} - -sw_error_t -sfp_diag_flag_rx_pwr_high_alarm_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union sfp_diag_flag_u reg_val; - sw_error_t ret = SW_OK; - - ret = sfp_diag_flag_get(dev_id, index, ®_val); - *value = reg_val.bf.rx_pwr_high_alarm; - return ret; -} - -sw_error_t -sfp_diag_flag_tx_pwr_low_warning_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union sfp_diag_flag_u reg_val; - sw_error_t ret = SW_OK; - - ret = sfp_diag_flag_get(dev_id, index, ®_val); - *value = reg_val.bf.tx_pwr_low_warning; - return ret; -} - -sw_error_t -sfp_diag_extended_ctrl_status_unallocated_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union sfp_diag_extended_ctrl_status_u reg_val; - sw_error_t ret = SW_OK; - - ret = sfp_diag_extended_ctrl_status_get(dev_id, index, ®_val); - *value = reg_val.bf.unallocated_0 << 8 - | reg_val.bf.unallocated_1; - return ret; -} - -sw_error_t -sfp_diag_extended_ctrl_status_pwr_level_op_state_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union sfp_diag_extended_ctrl_status_u reg_val; - sw_error_t ret = SW_OK; - - ret = sfp_diag_extended_ctrl_status_get(dev_id, index, ®_val); - *value = reg_val.bf.pwr_level_op_state; - return ret; -} - -sw_error_t -sfp_diag_extended_ctrl_status_soft_rs_sel_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union sfp_diag_extended_ctrl_status_u reg_val; - sw_error_t ret = SW_OK; - - ret = sfp_diag_extended_ctrl_status_get(dev_id, index, ®_val); - *value = reg_val.bf.soft_rs_sel; - return ret; -} - -sw_error_t -sfp_diag_extended_ctrl_status_pwr_level_sel_get( - a_uint32_t dev_id, - a_uint32_t index, - a_uint32_t *value) -{ - union sfp_diag_extended_ctrl_status_u reg_val; - sw_error_t ret = SW_OK; - - ret = sfp_diag_extended_ctrl_status_get(dev_id, index, ®_val); - *value = reg_val.bf.pwr_level_sel; - return ret; -} - diff --git a/feeds/ipq807x/qca-ssdk/src/src/hsl/sfp/sfp_access.c b/feeds/ipq807x/qca-ssdk/src/src/hsl/sfp/sfp_access.c deleted file mode 100755 index 4d2e6b586..000000000 --- a/feeds/ipq807x/qca-ssdk/src/src/hsl/sfp/sfp_access.c +++ /dev/null @@ -1,59 +0,0 @@ -/* - * Copyright (c) 2019, The Linux Foundation. All rights reserved. - * Permission to use, copy, modify, and/or distribute this software for - * any purpose with or without fee is hereby granted, provided that the - * above copyright notice and this permission notice appear in all copies. - * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES - * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR - * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES - * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN - * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT - * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. - */ - - -/** - * @defgroup - * @{ - */ - -#include "sw.h" -#include "ssdk_init.h" -#include "ssdk_phy_i2c.h" - -sw_error_t -sfp_data_tbl_get(a_uint32_t dev_id, a_uint32_t index, a_uint32_t i2c_slave, - a_uint32_t data_addr, a_uint8_t *buf, a_uint32_t count) -{ - sw_error_t rv; - rv = qca_i2c_data_get(dev_id, i2c_slave, data_addr, buf, count); - return rv; -} - -sw_error_t -sfp_data_get(a_uint32_t dev_id, a_uint32_t index, a_uint32_t i2c_slave, - a_uint32_t data_addr, a_uint8_t *buf) -{ - sw_error_t rv; - rv = qca_i2c_data_get(dev_id, i2c_slave, data_addr, buf, 1); - return rv; -} - -sw_error_t -sfp_data_tbl_set(a_uint32_t dev_id, a_uint32_t index, a_uint32_t i2c_slave, - a_uint32_t data_addr, a_uint8_t *buf, a_uint32_t count) -{ - sw_error_t rv; - rv = qca_i2c_data_set(dev_id, i2c_slave, data_addr, buf, count); - return rv; -} - -sw_error_t -sfp_data_set(a_uint32_t dev_id, a_uint32_t index, a_uint32_t i2c_slave, - a_uint32_t data_addr, a_uint8_t *buf) -{ - sw_error_t rv; - rv = qca_i2c_data_set(dev_id, i2c_slave, data_addr, buf, 1); - return rv; -} diff --git a/feeds/ipq807x/qca-ssdk/src/src/hsl/shiva/Makefile b/feeds/ipq807x/qca-ssdk/src/src/hsl/shiva/Makefile deleted file mode 100755 index 20042efd9..000000000 --- a/feeds/ipq807x/qca-ssdk/src/src/hsl/shiva/Makefile +++ /dev/null @@ -1,84 +0,0 @@ -LOC_DIR=src/hsl/shiva -LIB=HSL - -include $(PRJ_PATH)/make/config.mk - -SRC_LIST=shiva_reg_access.c shiva_init.c - -ifeq (TRUE, $(IN_ACL)) - SRC_LIST += shiva_acl.c -endif - -ifeq (TRUE, $(IN_FDB)) - SRC_LIST += shiva_fdb.c -endif - -ifeq (TRUE, $(IN_IGMP)) - SRC_LIST += shiva_igmp.c -endif - -ifeq (TRUE, $(IN_LEAKY)) - SRC_LIST += shiva_leaky.c -endif - -ifeq (TRUE, $(IN_LED)) - SRC_LIST += shiva_led.c -endif - -ifeq (TRUE, $(IN_MIB)) - SRC_LIST += shiva_mib.c -endif - -ifeq (TRUE, $(IN_MIRROR)) - SRC_LIST += shiva_mirror.c -endif - -ifeq (TRUE, $(IN_MISC)) - SRC_LIST += shiva_misc.c -endif - -ifeq (TRUE, $(IN_PORTCONTROL)) - SRC_LIST += shiva_port_ctrl.c -endif - -ifeq (TRUE, $(IN_PORTVLAN)) - SRC_LIST += shiva_portvlan.c -endif - -ifeq (TRUE, $(IN_QOS)) - SRC_LIST += shiva_qos.c -endif - -ifeq (TRUE, $(IN_RATE)) - SRC_LIST += shiva_rate.c -endif - -ifeq (TRUE, $(IN_STP)) - SRC_LIST += shiva_stp.c -endif - -ifeq (TRUE, $(IN_VLAN)) - SRC_LIST += shiva_vlan.c -endif - -ifeq (TRUE, $(IN_REDUCED_ACL)) - SRC_LIST += shiva_reduced_acl.c -endif - -ifeq (linux, $(OS)) - ifeq (KSLIB, $(MODULE_TYPE)) - ifneq (TRUE, $(KERNEL_MODE)) - SRC_LIST=shiva_reg_access.c shiva_init.c - endif - endif -endif - -ifeq (, $(findstring SHIVA, $(SUPPORT_CHIP))) - SRC_LIST= -endif - -include $(PRJ_PATH)/make/components.mk -include $(PRJ_PATH)/make/defs.mk -include $(PRJ_PATH)/make/target.mk - -all: dep obj \ No newline at end of file diff --git a/feeds/ipq807x/qca-ssdk/src/src/hsl/shiva/shiva_acl.c b/feeds/ipq807x/qca-ssdk/src/src/hsl/shiva/shiva_acl.c deleted file mode 100755 index 837047f7f..000000000 --- a/feeds/ipq807x/qca-ssdk/src/src/hsl/shiva/shiva_acl.c +++ /dev/null @@ -1,3171 +0,0 @@ -/* - * Copyright (c) 2012, 2016, The Linux Foundation. All rights reserved. - * Permission to use, copy, modify, and/or distribute this software for - * any purpose with or without fee is hereby granted, provided that the - * above copyright notice and this permission notice appear in all copies. - * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES - * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR - * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES - * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN - * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT - * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. - */ - - -/** - * @defgroup shiva_acl SHIVA_ACL - * @{ - */ -#include "sw.h" -#include "hsl.h" -#include "hsl_dev.h" -#include "hsl_acl.h" -#include "shiva_acl.h" -#include "shiva_reg.h" - -//#define SHIVA_ACL_DEBUG -//#define SHIVA_SW_ENTRY -//#define SHIVA_ENTRY_DUMP - -typedef struct -{ - a_uint32_t list_id; - a_uint32_t list_pri; - a_uint32_t addr; - a_uint32_t size; - a_uint32_t status; - fal_pbmp_t bind_pts; -} shiva_acl_list_t; - -typedef struct -{ - a_uint32_t slct[6]; - a_uint32_t vlu[5]; - a_uint32_t msk[5]; - a_uint32_t typ; - a_uint32_t len; - a_uint32_t act[3]; -} shiva_acl_hw_rule_t; - -static shiva_acl_list_t *list_ent[SW_MAX_NR_DEV]; -static shiva_acl_hw_rule_t *hw_rule_ent; - -static a_uint32_t filter[SW_MAX_NR_DEV]; -static a_uint32_t filter_snap[SW_MAX_NR_DEV]; - -#define SHIVA_MAX_LIST 32 -#define SHIVA_MAX_RULE 32 - -#define ENT_FREE 0x1 -#define ENT_USED 0x2 - -#define SHIVA_RULE_VLU_ADDR 0x58400 -#define SHIVA_RULE_MSK_ADDR 0x58c00 -#define SHIVA_RULE_LEN_ADDR 0x58818 -#define SHIVA_RULE_TYP_ADDR 0x5881c -#define SHIVA_RULE_ACT_ADDR 0x58000 -#define SHIVA_RULE_SLCT_ADDR 0x58800 - -#define SHIVA_MAC_FILTER 1 -#define SHIVA_IP4_FILTER 2 -#define SHIVA_IP6R1_FILTER 3 -#define SHIVA_IP6R2_FILTER 4 -#define SHIVA_IP6R3_FILTER 5 -#define SHIVA_UDF_FILTER 6 - -#ifdef SHIVA_SW_ENTRY -static char *flt_vlu_mem = NULL; -static char *flt_msk_mem = NULL; -static char *flt_typ_mem = NULL; -static char *flt_len_mem = NULL; -static char *act_mem = NULL; -static char *slct_mem = NULL; -#endif - -static a_bool_t _shiva_acl_zero_addr(const fal_mac_addr_t addr); - -static a_bool_t -_shiva_acl_field_care(fal_acl_field_op_t op, a_uint32_t val, a_uint32_t mask, - a_uint32_t chkvlu); - -static sw_error_t -_shiva_acl_list_loc(a_uint32_t dev_id, a_uint32_t list_id, a_uint32_t * idx); - -static sw_error_t -_shiva_acl_filter_map_get(const shiva_acl_hw_rule_t * rule, - a_uint32_t flt_idx[], a_uint32_t * flt_nr); - -static sw_error_t -_shiva_acl_rule_mac_parse(fal_acl_rule_t * sw, - shiva_acl_hw_rule_t * hw, a_bool_t * b_care); - -static sw_error_t -_shiva_acl_rule_ip4_parse(fal_acl_rule_t * sw, - shiva_acl_hw_rule_t * hw, a_bool_t * b_care); - -static sw_error_t -_shiva_acl_rule_ip6r1_parse(fal_acl_rule_t * sw, - shiva_acl_hw_rule_t * hw, a_bool_t * b_care); - -static sw_error_t -_shiva_acl_rule_ip6r2_parse(fal_acl_rule_t * sw, - shiva_acl_hw_rule_t * hw, a_bool_t * b_care); - -static sw_error_t -_shiva_acl_rule_ip6r3_parse(fal_acl_rule_t * sw, - shiva_acl_hw_rule_t * hw, a_bool_t * b_care); - -static sw_error_t -_shiva_acl_rule_udf_parse(fal_acl_rule_t * sw, - shiva_acl_hw_rule_t * hw, a_bool_t * b_care); - -static sw_error_t -_shiva_acl_action_parse(a_uint32_t dev_id, const fal_acl_rule_t * sw, - shiva_acl_hw_rule_t * hw); - -static sw_error_t -_shiva_acl_rule_mac_reparse(fal_acl_rule_t * sw, - const shiva_acl_hw_rule_t * hw); - -static sw_error_t -_shiva_acl_rule_ip4_reparse(fal_acl_rule_t * sw, - const shiva_acl_hw_rule_t * hw); - -static sw_error_t -_shiva_acl_rule_ip6r1_reparse(fal_acl_rule_t * sw, - const shiva_acl_hw_rule_t * hw); - -static sw_error_t -_shiva_acl_rule_ip6r2_reparse(fal_acl_rule_t * sw, - const shiva_acl_hw_rule_t * hw); - -static sw_error_t -_shiva_acl_rule_ip6r3_reparse(fal_acl_rule_t * sw, - const shiva_acl_hw_rule_t * hw); - -static sw_error_t -_shiva_acl_rule_action_reparse(fal_acl_rule_t * sw, - const shiva_acl_hw_rule_t * hw); - -static sw_error_t -_shiva_acl_filter_alloc(a_uint32_t dev_id, a_uint32_t * idx); - -static void -_shiva_acl_filter_free(a_uint32_t dev_id, a_uint32_t idx); - -static void -_shiva_acl_filter_snap(a_uint32_t dev_id); - -static void -_shiva_acl_filter_commit(a_uint32_t dev_id); - -static sw_error_t -_shiva_acl_slct_update(shiva_acl_hw_rule_t * hw, a_uint32_t offset, - a_uint32_t flt_idx); - -static sw_error_t -_shiva_acl_filter_write(a_uint32_t dev_id, const shiva_acl_hw_rule_t * rule, - a_uint32_t flt_idx); - -static sw_error_t -_shiva_acl_action_write(a_uint32_t dev_id, const shiva_acl_hw_rule_t * rule, - a_uint32_t act_idx); - -static sw_error_t -_shiva_acl_slct_write(a_uint32_t dev_id, const shiva_acl_hw_rule_t * rule, - a_uint32_t slct_idx); - -static sw_error_t -_shiva_acl_filter_read(a_uint32_t dev_id, shiva_acl_hw_rule_t * rule, - a_uint32_t flt_idx); - -static sw_error_t -_shiva_acl_action_read(a_uint32_t dev_id, shiva_acl_hw_rule_t * rule, - a_uint32_t act_idx); - -static sw_error_t -_shiva_acl_slct_read(a_uint32_t dev_id, shiva_acl_hw_rule_t * rule, - a_uint32_t slct_idx); - -static sw_error_t -_shiva_acl_rule_set(a_uint32_t dev_id, a_uint32_t base_addr, - const shiva_acl_hw_rule_t * hw_rule_ent, - a_uint32_t rule_nr); - -static sw_error_t -_shiva_acl_rule_get(a_uint32_t dev_id, shiva_acl_hw_rule_t * rule, - a_uint32_t * ent_idx, a_uint32_t rule_idx); - -static sw_error_t -_shiva_acl_rule_sw_to_hw(a_uint32_t dev_id, fal_acl_rule_t * sw, - shiva_acl_hw_rule_t * hw, a_uint32_t * idx); - -static sw_error_t -_shiva_acl_rule_hw_to_sw(fal_acl_rule_t * sw, const shiva_acl_hw_rule_t * hw, - a_uint32_t ent_idx, a_uint32_t ent_nr); - -static sw_error_t -_shiva_acl_rule_copy(a_uint32_t dev_id, a_uint32_t src_slct_idx, - a_uint32_t dst_slct_idx, a_uint32_t size); - -static sw_error_t -_shiva_acl_rule_invalid(a_uint32_t dev_id, a_uint32_t rule_idx, - a_uint32_t size); - -static sw_error_t -_shiva_acl_rule_valid(a_uint32_t dev_id, a_uint32_t rule_idx, a_uint32_t size, - a_uint32_t flag); - -static sw_error_t -_shiva_acl_addr_update(a_uint32_t dev_id, a_uint32_t old_addr, - a_uint32_t new_addr, a_uint32_t list_id); - -static sw_error_t -_shiva_acl_rule_bind(a_uint32_t dev_id, a_uint32_t rule_idx, a_uint32_t ports); - -#ifdef SHIVA_ACL_DEBUG -static void -_shiva_acl_list_dump(a_uint32_t dev_id) -{ - a_uint32_t i; - - aos_printk("\ndev_id=%d list control infomation", dev_id); - for (i = 0; i < SHIVA_MAX_LIST; i++) - { - if (ENT_USED == list_ent[dev_id][i].status) - { - aos_printk("\nlist_id=%d list_pri=%d addr=%d size=%d idx=%d ", - list_ent[dev_id][i].list_id, - list_ent[dev_id][i].list_pri, - list_ent[dev_id][i].addr, list_ent[dev_id][i].size, i); - } - } - aos_printk("\n"); -} -#else -#define _shiva_acl_list_dump(dev_id) -#endif - -static a_bool_t -_shiva_acl_zero_addr(const fal_mac_addr_t addr) -{ - a_uint32_t i; - - for (i = 0; i < 6; i++) - { - if (addr.uc[i]) - { - return A_FALSE; - } - } - return A_TRUE; -} - -static a_bool_t -_shiva_acl_field_care(fal_acl_field_op_t op, a_uint32_t val, a_uint32_t mask, - a_uint32_t chkvlu) -{ - if (FAL_ACL_FIELD_MASK == op) - { - if (0 == mask) - return A_FALSE; - } - else if (FAL_ACL_FIELD_RANGE == op) - { - if ((0 == val) && (chkvlu == mask)) - return A_FALSE; - } - else if (FAL_ACL_FIELD_LE == op) - { - if (chkvlu == val) - return A_FALSE; - } - else if (FAL_ACL_FIELD_GE == op) - { - if (0 == val) - return A_FALSE; - } - else if (FAL_ACL_FIELD_NE == op) - { - return A_TRUE; - } - - return A_TRUE; -} - -static sw_error_t -_shiva_acl_list_loc(a_uint32_t dev_id, a_uint32_t list_id, a_uint32_t * idx) -{ - a_uint32_t i; - - for (i = 0; i < SHIVA_MAX_LIST; i++) - { - if ((ENT_USED == list_ent[dev_id][i].status) - && (list_id == list_ent[dev_id][i].list_id)) - { - *idx = i; - return SW_OK; - } - } - return SW_NOT_FOUND; -} - -static sw_error_t -_shiva_acl_filter_map_get(const shiva_acl_hw_rule_t * rule, - a_uint32_t flt_idx[], a_uint32_t * flt_nr) -{ - a_uint32_t flt_en, idx, i = 0; - - SW_GET_FIELD_BY_REG(RUL_SLCT0, ADDR0_EN, flt_en, (rule->slct[0])); - if (flt_en) - { - SW_GET_FIELD_BY_REG(RUL_SLCT1, ADDR0, idx, (rule->slct[1])); - flt_idx[i] = idx; - i++; - } - - SW_GET_FIELD_BY_REG(RUL_SLCT0, ADDR1_EN, flt_en, (rule->slct[0])); - if (flt_en) - { - SW_GET_FIELD_BY_REG(RUL_SLCT2, ADDR1, idx, (rule->slct[2])); - flt_idx[i] = idx; - i++; - } - - SW_GET_FIELD_BY_REG(RUL_SLCT0, ADDR2_EN, flt_en, (rule->slct[0])); - if (flt_en) - { - SW_GET_FIELD_BY_REG(RUL_SLCT3, ADDR2, idx, (rule->slct[3])); - flt_idx[i] = idx; - i++; - } - - SW_GET_FIELD_BY_REG(RUL_SLCT0, ADDR3_EN, flt_en, (rule->slct[0])); - if (flt_en) - { - SW_GET_FIELD_BY_REG(RUL_SLCT4, ADDR3, idx, (rule->slct[4])); - flt_idx[i] = idx; - i++; - } - - *flt_nr = i; - return SW_OK; -} - -static sw_error_t -_shiva_acl_rule_mac_parse(fal_acl_rule_t * sw, - shiva_acl_hw_rule_t * hw, a_bool_t * b_care) -{ - a_uint32_t i, len = 14; - - *b_care = A_FALSE; - - aos_mem_zero(&(hw->vlu[0]), sizeof (hw->vlu)); - aos_mem_zero(&(hw->msk[0]), sizeof (hw->msk)); - aos_mem_zero(&(hw->typ), sizeof (hw->typ)); - aos_mem_zero(&(hw->len), sizeof (hw->len)); - - SW_SET_REG_BY_FIELD(RUL_SLCT7, RULE_TYP, SHIVA_MAC_FILTER, hw->typ); - - if (FAL_FIELD_FLG_TST(sw->field_flg, FAL_ACL_FIELD_MAC_DA)) - { - if (A_TRUE != _shiva_acl_zero_addr(sw->dest_mac_mask)) - { - *b_care = A_TRUE; - } - - for (i = 0; i < 6; i++) - { - sw->dest_mac_val.uc[i] &= sw->dest_mac_mask.uc[i]; - } - - SW_SET_REG_BY_FIELD(MAC_RUL_V0, DAV_BYTE2, sw->dest_mac_val.uc[2], - hw->vlu[0]); - SW_SET_REG_BY_FIELD(MAC_RUL_V0, DAV_BYTE3, sw->dest_mac_val.uc[3], - hw->vlu[0]); - SW_SET_REG_BY_FIELD(MAC_RUL_V0, DAV_BYTE4, sw->dest_mac_val.uc[4], - hw->vlu[0]); - SW_SET_REG_BY_FIELD(MAC_RUL_V0, DAV_BYTE5, sw->dest_mac_val.uc[5], - hw->vlu[0]); - SW_SET_REG_BY_FIELD(MAC_RUL_V1, DAV_BYTE0, sw->dest_mac_val.uc[0], - hw->vlu[1]); - SW_SET_REG_BY_FIELD(MAC_RUL_V1, DAV_BYTE1, sw->dest_mac_val.uc[1], - hw->vlu[1]); - - SW_SET_REG_BY_FIELD(MAC_RUL_M0, DAM_BYTE2, sw->dest_mac_mask.uc[2], - hw->msk[0]); - SW_SET_REG_BY_FIELD(MAC_RUL_M0, DAM_BYTE3, sw->dest_mac_mask.uc[3], - hw->msk[0]); - SW_SET_REG_BY_FIELD(MAC_RUL_M0, DAM_BYTE4, sw->dest_mac_mask.uc[4], - hw->msk[0]); - SW_SET_REG_BY_FIELD(MAC_RUL_M0, DAM_BYTE5, sw->dest_mac_mask.uc[5], - hw->msk[0]); - SW_SET_REG_BY_FIELD(MAC_RUL_M1, DAM_BYTE0, sw->dest_mac_mask.uc[0], - hw->msk[1]); - SW_SET_REG_BY_FIELD(MAC_RUL_M1, DAM_BYTE1, sw->dest_mac_mask.uc[1], - hw->msk[1]); - } - - if (FAL_FIELD_FLG_TST(sw->field_flg, FAL_ACL_FIELD_MAC_SA)) - { - if (A_TRUE != _shiva_acl_zero_addr(sw->src_mac_mask)) - { - *b_care = A_TRUE; - } - - for (i = 0; i < 6; i++) - { - sw->src_mac_val.uc[i] &= sw->src_mac_mask.uc[i]; - } - - SW_SET_REG_BY_FIELD(MAC_RUL_V1, SAV_BYTE4, sw->src_mac_val.uc[4], - hw->vlu[1]); - SW_SET_REG_BY_FIELD(MAC_RUL_V1, SAV_BYTE5, sw->src_mac_val.uc[5], - hw->vlu[1]); - SW_SET_REG_BY_FIELD(MAC_RUL_V2, SAV_BYTE0, sw->src_mac_val.uc[0], - hw->vlu[2]); - SW_SET_REG_BY_FIELD(MAC_RUL_V2, SAV_BYTE1, sw->src_mac_val.uc[1], - hw->vlu[2]); - SW_SET_REG_BY_FIELD(MAC_RUL_V2, SAV_BYTE2, sw->src_mac_val.uc[2], - hw->vlu[2]); - SW_SET_REG_BY_FIELD(MAC_RUL_V2, SAV_BYTE3, sw->src_mac_val.uc[3], - hw->vlu[2]); - - SW_SET_REG_BY_FIELD(MAC_RUL_M1, SAM_BYTE4, sw->src_mac_mask.uc[4], - hw->msk[1]); - SW_SET_REG_BY_FIELD(MAC_RUL_M1, SAM_BYTE5, sw->src_mac_mask.uc[5], - hw->msk[1]); - SW_SET_REG_BY_FIELD(MAC_RUL_M2, SAM_BYTE0, sw->src_mac_mask.uc[0], - hw->msk[2]); - SW_SET_REG_BY_FIELD(MAC_RUL_M2, SAM_BYTE1, sw->src_mac_mask.uc[1], - hw->msk[2]); - SW_SET_REG_BY_FIELD(MAC_RUL_M2, SAM_BYTE2, sw->src_mac_mask.uc[2], - hw->msk[2]); - SW_SET_REG_BY_FIELD(MAC_RUL_M2, SAM_BYTE3, sw->src_mac_mask.uc[3], - hw->msk[2]); - } - - if (FAL_FIELD_FLG_TST(sw->field_flg, FAL_ACL_FIELD_MAC_ETHTYPE)) - { - if (0x0 != sw->ethtype_mask) - { - *b_care = A_TRUE; - } - - sw->ethtype_val &= sw->ethtype_mask; - SW_SET_REG_BY_FIELD(MAC_RUL_V3, ETHTYPV, sw->ethtype_val, hw->vlu[3]); - SW_SET_REG_BY_FIELD(MAC_RUL_M3, ETHTYPM, sw->ethtype_mask, hw->msk[3]); - } - - if (FAL_FIELD_FLG_TST(sw->field_flg, FAL_ACL_FIELD_MAC_TAGGED)) - { - if (0x0 != sw->tagged_mask) - { - *b_care = A_TRUE; - } - - sw->tagged_val &= sw->tagged_mask; - SW_SET_REG_BY_FIELD(MAC_RUL_V4, TAGGEDV, sw->tagged_val, hw->vlu[4]); - SW_SET_REG_BY_FIELD(MAC_RUL_V4, TAGGEDM, sw->tagged_mask, hw->vlu[4]); - } - - if (FAL_FIELD_FLG_TST(sw->field_flg, FAL_ACL_FIELD_MAC_UP)) - { - if (0x0 != sw->up_mask) - { - *b_care = A_TRUE; - } - - sw->up_val &= sw->up_mask; - SW_SET_REG_BY_FIELD(MAC_RUL_V3, VLANPRIV, sw->up_val, hw->vlu[3]); - SW_SET_REG_BY_FIELD(MAC_RUL_M3, VLANPRIM, sw->up_mask, hw->msk[3]); - } - - SW_SET_REG_BY_FIELD(MAC_RUL_V4, VIDMSK, 1, hw->vlu[4]); - if (FAL_FIELD_FLG_TST(sw->field_flg, FAL_ACL_FIELD_MAC_VID)) - { - if ((FAL_ACL_FIELD_MASK != sw->vid_op) - && (FAL_ACL_FIELD_RANGE != sw->vid_op) - && (FAL_ACL_FIELD_LE != sw->vid_op) - && (FAL_ACL_FIELD_GE != sw->vid_op)) - { - return SW_NOT_SUPPORTED; - } - - if (A_TRUE == - _shiva_acl_field_care(sw->vid_op, sw->vid_val, sw->vid_mask, - 0xfff)) - { - *b_care = A_TRUE; - } - - SW_SET_REG_BY_FIELD(MAC_RUL_V4, VIDMSK, 0, hw->vlu[4]); - if (FAL_ACL_FIELD_MASK == sw->vid_op) - { - sw->vid_val &= sw->vid_mask; - SW_SET_REG_BY_FIELD(MAC_RUL_V3, VLANIDV, sw->vid_val, hw->vlu[3]); - SW_SET_REG_BY_FIELD(MAC_RUL_M3, VLANIDM, sw->vid_mask, hw->msk[3]); - SW_SET_REG_BY_FIELD(MAC_RUL_V4, VIDMSK, 1, hw->vlu[4]); - } - else if (FAL_ACL_FIELD_RANGE == sw->vid_op) - { - SW_SET_REG_BY_FIELD(MAC_RUL_V3, VLANIDV, sw->vid_val, hw->vlu[3]); - SW_SET_REG_BY_FIELD(MAC_RUL_M3, VLANIDM, sw->vid_mask, hw->msk[3]); - } - else if (FAL_ACL_FIELD_LE == sw->vid_op) - { - SW_SET_REG_BY_FIELD(MAC_RUL_V3, VLANIDV, 0, hw->vlu[3]); - SW_SET_REG_BY_FIELD(MAC_RUL_M3, VLANIDM, sw->vid_val, hw->msk[3]); - } - else - { - SW_SET_REG_BY_FIELD(MAC_RUL_V3, VLANIDV, sw->vid_val, hw->vlu[3]); - SW_SET_REG_BY_FIELD(MAC_RUL_M3, VLANIDM, 0xfff, hw->msk[3]); - } - } - - if (FAL_FIELD_FLG_TST(sw->field_flg, FAL_ACL_FIELD_MAC_CFI)) - { - if (0x0 != sw->cfi_mask) - { - *b_care = A_TRUE; - } - - sw->cfi_val &= sw->cfi_mask; - SW_SET_REG_BY_FIELD(MAC_RUL_V3, VLANCFIV, sw->cfi_val, hw->vlu[3]); - SW_SET_REG_BY_FIELD(MAC_RUL_M3, VLANCFIM, sw->cfi_mask, hw->msk[3]); - } - - SW_SET_REG_BY_FIELD(RUL_SLCT6, RULE_LEN, len, hw->len); - - return SW_OK; -} - -static sw_error_t -_shiva_acl_rule_ip4_parse(fal_acl_rule_t * sw, - shiva_acl_hw_rule_t * hw, a_bool_t * b_care) -{ - a_uint32_t len = 34; - - *b_care = A_FALSE; - aos_mem_zero(&(hw->vlu[0]), sizeof (hw->vlu)); - aos_mem_zero(&(hw->msk[0]), sizeof (hw->msk)); - aos_mem_zero(&(hw->typ), sizeof (hw->typ)); - aos_mem_zero(&(hw->len), sizeof (hw->len)); - - SW_SET_REG_BY_FIELD(RUL_SLCT7, RULE_TYP, SHIVA_IP4_FILTER, hw->typ); - - if (FAL_FIELD_FLG_TST(sw->field_flg, FAL_ACL_FIELD_IP_DSCP)) - { - if (0x0 != sw->ip_dscp_mask) - { - *b_care = A_TRUE; - } - - sw->ip_dscp_val &= sw->ip_dscp_mask; - SW_SET_REG_BY_FIELD(IP4_RUL_V2, IP4DSCPV, sw->ip_dscp_val, hw->vlu[2]); - SW_SET_REG_BY_FIELD(IP4_RUL_M2, IP4DSCPM, sw->ip_dscp_mask, hw->msk[2]); - } - - if (FAL_FIELD_FLG_TST(sw->field_flg, FAL_ACL_FIELD_IP_PROTO)) - { - if (0x0 != sw->ip_proto_mask) - { - *b_care = A_TRUE; - } - - sw->ip_proto_val &= sw->ip_proto_mask; - SW_SET_REG_BY_FIELD(IP4_RUL_V2, IP4PROTV, sw->ip_proto_val, hw->vlu[2]); - SW_SET_REG_BY_FIELD(IP4_RUL_M2, IP4PROTM, sw->ip_proto_mask, - hw->msk[2]); - } - - if (FAL_FIELD_FLG_TST(sw->field_flg, FAL_ACL_FIELD_IP4_SIP)) - { - if (0x0 != sw->src_ip4_mask) - { - *b_care = A_TRUE; - } - sw->src_ip4_val &= sw->src_ip4_mask; - hw->vlu[1] = sw->src_ip4_val; - hw->msk[1] = sw->src_ip4_mask; - } - - if (FAL_FIELD_FLG_TST(sw->field_flg, FAL_ACL_FIELD_IP4_DIP)) - { - if (0x0 != sw->dest_ip4_mask) - { - *b_care = A_TRUE; - } - sw->dest_ip4_val &= sw->dest_ip4_mask; - hw->vlu[0] = sw->dest_ip4_val; - hw->msk[0] = sw->dest_ip4_mask; - } - - SW_SET_REG_BY_FIELD(IP4_RUL_M3, IP4SPORTM_EN, 1, hw->msk[3]); - if (FAL_FIELD_FLG_TST(sw->field_flg, FAL_ACL_FIELD_L4_SPORT)) - { - if ((FAL_ACL_FIELD_MASK != sw->src_l4port_op) - && (FAL_ACL_FIELD_RANGE != sw->src_l4port_op) - && (FAL_ACL_FIELD_LE != sw->src_l4port_op) - && (FAL_ACL_FIELD_GE != sw->src_l4port_op)) - { - return SW_NOT_SUPPORTED; - } - - if (A_FALSE == - _shiva_acl_field_care(sw->src_l4port_op, sw->src_l4port_val, - sw->src_l4port_mask, 0xffff)) - { - if (FAL_ACL_FIELD_MASK == sw->src_l4port_op) - { - sw->src_l4port_op = FAL_ACL_FIELD_RANGE; - sw->src_l4port_val = 0; - sw->src_l4port_mask = 0xffff; - } - } - *b_care = A_TRUE; - len = 38; - - SW_SET_REG_BY_FIELD(IP4_RUL_M3, IP4SPORTM_EN, 0, hw->msk[3]); - if (FAL_ACL_FIELD_MASK == sw->src_l4port_op) - { - sw->src_l4port_val &= sw->src_l4port_mask; - SW_SET_REG_BY_FIELD(IP4_RUL_V3, IP4SPORTV, sw->src_l4port_val, - hw->vlu[3]); - SW_SET_REG_BY_FIELD(IP4_RUL_M3, IP4SPORTM, sw->src_l4port_mask, - hw->msk[3]); - SW_SET_REG_BY_FIELD(IP4_RUL_M3, IP4SPORTM_EN, 1, hw->msk[3]); - } - else if (FAL_ACL_FIELD_RANGE == sw->src_l4port_op) - { - SW_SET_REG_BY_FIELD(IP4_RUL_V3, IP4SPORTV, sw->src_l4port_val, - hw->vlu[3]); - SW_SET_REG_BY_FIELD(IP4_RUL_M3, IP4SPORTM, sw->src_l4port_mask, - hw->msk[3]); - } - else if (FAL_ACL_FIELD_LE == sw->src_l4port_op) - { - SW_SET_REG_BY_FIELD(IP4_RUL_V3, IP4SPORTV, 0, hw->vlu[3]); - SW_SET_REG_BY_FIELD(IP4_RUL_M3, IP4SPORTM, sw->src_l4port_val, - hw->msk[3]); - } - else - { - SW_SET_REG_BY_FIELD(IP4_RUL_V3, IP4SPORTV, sw->src_l4port_val, - hw->vlu[3]); - SW_SET_REG_BY_FIELD(IP4_RUL_M3, IP4SPORTM, 0xffff, hw->msk[3]); - } - } - - SW_SET_REG_BY_FIELD(IP4_RUL_M3, IP4DPORTM_EN, 1, hw->msk[3]); - if (FAL_FIELD_FLG_TST(sw->field_flg, FAL_ACL_FIELD_L4_DPORT)) - { - if ((FAL_ACL_FIELD_MASK != sw->dest_l4port_op) - && (FAL_ACL_FIELD_RANGE != sw->dest_l4port_op) - && (FAL_ACL_FIELD_LE != sw->dest_l4port_op) - && (FAL_ACL_FIELD_GE != sw->dest_l4port_op)) - { - return SW_NOT_SUPPORTED; - } - - if (A_FALSE == - _shiva_acl_field_care(sw->dest_l4port_op, sw->dest_l4port_val, - sw->dest_l4port_mask, 0xffff)) - { - if (FAL_ACL_FIELD_MASK == sw->dest_l4port_op) - { - sw->dest_l4port_op = FAL_ACL_FIELD_RANGE; - sw->dest_l4port_val = 0; - sw->dest_l4port_mask = 0xffff; - } - } - *b_care = A_TRUE; - len = 38; - - SW_SET_REG_BY_FIELD(IP4_RUL_M3, IP4DPORTM_EN, 0, hw->msk[3]); - if (FAL_ACL_FIELD_MASK == sw->dest_l4port_op) - { - sw->dest_l4port_val &= sw->dest_l4port_mask; - SW_SET_REG_BY_FIELD(IP4_RUL_V2, IP4DPORTV, sw->dest_l4port_val, - hw->vlu[2]); - SW_SET_REG_BY_FIELD(IP4_RUL_M2, IP4DPORTM, sw->dest_l4port_mask, - hw->msk[2]); - SW_SET_REG_BY_FIELD(IP4_RUL_M3, IP4DPORTM_EN, 1, hw->msk[3]); - } - else if (FAL_ACL_FIELD_RANGE == sw->dest_l4port_op) - { - SW_SET_REG_BY_FIELD(IP4_RUL_V2, IP4DPORTV, sw->dest_l4port_val, - hw->vlu[2]); - SW_SET_REG_BY_FIELD(IP4_RUL_M2, IP4DPORTM, sw->dest_l4port_mask, - hw->msk[2]); - } - else if (FAL_ACL_FIELD_LE == sw->dest_l4port_op) - { - SW_SET_REG_BY_FIELD(IP4_RUL_V2, IP4DPORTV, 0, hw->vlu[2]); - SW_SET_REG_BY_FIELD(IP4_RUL_M2, IP4DPORTM, sw->dest_l4port_val, - hw->msk[2]); - } - else - { - SW_SET_REG_BY_FIELD(IP4_RUL_V2, IP4DPORTV, sw->dest_l4port_val, - hw->vlu[2]); - SW_SET_REG_BY_FIELD(IP4_RUL_M2, IP4DPORTM, 0xffff, hw->msk[2]); - } - } - - SW_SET_REG_BY_FIELD(RUL_SLCT6, RULE_LEN, len, hw->len); - - return SW_OK; -} - -static sw_error_t -_shiva_acl_rule_ip6r1_parse(fal_acl_rule_t * sw, - shiva_acl_hw_rule_t * hw, a_bool_t * b_care) -{ - a_uint32_t i, len = 54; - - *b_care = A_FALSE; - aos_mem_zero(&(hw->vlu[0]), sizeof (hw->vlu)); - aos_mem_zero(&(hw->msk[0]), sizeof (hw->msk)); - aos_mem_zero(&(hw->typ), sizeof (hw->typ)); - aos_mem_zero(&(hw->len), sizeof (hw->len)); - - SW_SET_REG_BY_FIELD(RUL_SLCT7, RULE_TYP, SHIVA_IP6R1_FILTER, hw->typ); - - if (FAL_FIELD_FLG_TST(sw->field_flg, FAL_ACL_FIELD_IP6_DIP)) - { - for (i = 0; i < 4; i++) - { - if (0x0 != sw->dest_ip6_mask.ul[i]) - { - *b_care = A_TRUE; - } - - sw->dest_ip6_val.ul[3 - i] &= sw->dest_ip6_mask.ul[3 - i]; - hw->vlu[i] = sw->dest_ip6_val.ul[3 - i]; - hw->msk[i] = sw->dest_ip6_mask.ul[3 - i]; - } - } - - SW_SET_REG_BY_FIELD(RUL_SLCT6, RULE_LEN, len, hw->len); - - return SW_OK; -} - -static sw_error_t -_shiva_acl_rule_ip6r2_parse(fal_acl_rule_t * sw, - shiva_acl_hw_rule_t * hw, a_bool_t * b_care) -{ - a_uint32_t i, len = 54; - - *b_care = A_FALSE; - aos_mem_zero(&(hw->vlu[0]), sizeof (hw->vlu)); - aos_mem_zero(&(hw->msk[0]), sizeof (hw->msk)); - aos_mem_zero(&(hw->typ), sizeof (hw->typ)); - aos_mem_zero(&(hw->len), sizeof (hw->len)); - - SW_SET_REG_BY_FIELD(RUL_SLCT7, RULE_TYP, SHIVA_IP6R2_FILTER, hw->typ); - - if (FAL_FIELD_FLG_TST(sw->field_flg, FAL_ACL_FIELD_IP6_SIP)) - { - for (i = 0; i < 4; i++) - { - if (0x0 != sw->src_ip6_mask.ul[i]) - { - *b_care = A_TRUE; - } - - sw->src_ip6_val.ul[3 - i] &= sw->src_ip6_mask.ul[3 - i]; - hw->vlu[i] = sw->src_ip6_val.ul[3 - i]; - hw->msk[i] = sw->src_ip6_mask.ul[3 - i]; - } - } - - SW_SET_REG_BY_FIELD(RUL_SLCT6, RULE_LEN, len, hw->len); - - return SW_OK; -} - -static sw_error_t -_shiva_acl_rule_ip6r3_parse(fal_acl_rule_t * sw, - shiva_acl_hw_rule_t * hw, a_bool_t * b_care) -{ - a_uint32_t len = 54; - - *b_care = A_FALSE; - aos_mem_zero(&(hw->vlu[0]), sizeof (hw->vlu)); - aos_mem_zero(&(hw->msk[0]), sizeof (hw->msk)); - aos_mem_zero(&(hw->typ), sizeof (hw->typ)); - aos_mem_zero(&(hw->len), sizeof (hw->len)); - - SW_SET_REG_BY_FIELD(RUL_SLCT7, RULE_TYP, SHIVA_IP6R3_FILTER, hw->typ); - - if (FAL_FIELD_FLG_TST(sw->field_flg, FAL_ACL_FIELD_IP6_LABEL)) - { - if (0x0 != sw->ip6_lable_mask) - { - *b_care = A_TRUE; - } - - sw->ip6_lable_val &= sw->ip6_lable_mask; - SW_SET_REG_BY_FIELD(IP6_RUL3_V1, IP6LABEL1V, sw->ip6_lable_val, - hw->vlu[1]); - SW_SET_REG_BY_FIELD(IP6_RUL3_M1, IP6LABEL1M, sw->ip6_lable_mask, - hw->msk[1]); - - SW_SET_REG_BY_FIELD(IP6_RUL3_V2, IP6LABEL2V, (sw->ip6_lable_val >> 16), - hw->vlu[2]); - SW_SET_REG_BY_FIELD(IP6_RUL3_M2, IP6LABEL2M, (sw->ip6_lable_mask >> 16), - hw->msk[2]); - } - - if (FAL_FIELD_FLG_TST(sw->field_flg, FAL_ACL_FIELD_IP_PROTO)) - { - if (0x0 != sw->ip_proto_mask) - { - *b_care = A_TRUE; - } - - sw->ip_proto_val &= sw->ip_proto_mask; - SW_SET_REG_BY_FIELD(IP6_RUL3_V0, IP6PROTV, sw->ip_proto_val, - hw->vlu[0]); - SW_SET_REG_BY_FIELD(IP6_RUL3_M0, IP6PROTM, sw->ip_proto_mask, - hw->msk[0]); - } - - if (FAL_FIELD_FLG_TST(sw->field_flg, FAL_ACL_FIELD_IP_DSCP)) - { - if (0x0 != sw->ip_dscp_mask) - { - *b_care = A_TRUE; - } - - sw->ip_dscp_val &= sw->ip_dscp_mask; - SW_SET_REG_BY_FIELD(IP6_RUL3_V0, IP6DSCPV, sw->ip_dscp_val, hw->vlu[0]); - SW_SET_REG_BY_FIELD(IP6_RUL3_M0, IP6DSCPM, sw->ip_dscp_mask, - hw->msk[0]); - } - - SW_SET_REG_BY_FIELD(IP6_RUL3_M3, IP6SPORTM_EN, 1, hw->msk[3]); - if (FAL_FIELD_FLG_TST(sw->field_flg, FAL_ACL_FIELD_L4_SPORT)) - { - if ((FAL_ACL_FIELD_MASK != sw->src_l4port_op) - && (FAL_ACL_FIELD_RANGE != sw->src_l4port_op) - && (FAL_ACL_FIELD_LE != sw->src_l4port_op) - && (FAL_ACL_FIELD_GE != sw->src_l4port_op)) - { - return SW_NOT_SUPPORTED; - } - - if (A_FALSE == - _shiva_acl_field_care(sw->src_l4port_op, sw->src_l4port_val, - sw->src_l4port_mask, 0xffff)) - { - if (FAL_ACL_FIELD_MASK == sw->src_l4port_op) - { - sw->src_l4port_op = FAL_ACL_FIELD_RANGE; - sw->src_l4port_val = 0; - sw->src_l4port_mask = 0xffff; - } - } - *b_care = A_TRUE; - len = 58; - - SW_SET_REG_BY_FIELD(IP6_RUL3_M3, IP6SPORTM_EN, 0, hw->msk[3]); - if (FAL_ACL_FIELD_MASK == sw->src_l4port_op) - { - sw->src_l4port_val &= sw->src_l4port_mask; - SW_SET_REG_BY_FIELD(IP6_RUL3_V3, IP6SPORTV, sw->src_l4port_val, - hw->vlu[3]); - SW_SET_REG_BY_FIELD(IP6_RUL3_M3, IP6SPORTM, sw->src_l4port_mask, - hw->msk[3]); - SW_SET_REG_BY_FIELD(IP6_RUL3_M3, IP6SPORTM_EN, 1, hw->msk[3]); - } - else if (FAL_ACL_FIELD_RANGE == sw->src_l4port_op) - { - SW_SET_REG_BY_FIELD(IP6_RUL3_V3, IP6SPORTV, sw->src_l4port_val, - hw->vlu[3]); - SW_SET_REG_BY_FIELD(IP6_RUL3_M3, IP6SPORTM, sw->src_l4port_mask, - hw->msk[3]); - } - else if (FAL_ACL_FIELD_LE == sw->src_l4port_op) - { - SW_SET_REG_BY_FIELD(IP6_RUL3_V3, IP6SPORTV, 0, hw->vlu[3]); - SW_SET_REG_BY_FIELD(IP6_RUL3_M3, IP6SPORTM, sw->src_l4port_val, - hw->msk[3]); - } - else - { - SW_SET_REG_BY_FIELD(IP6_RUL3_V3, IP6SPORTV, sw->src_l4port_val, - hw->vlu[3]); - SW_SET_REG_BY_FIELD(IP6_RUL3_M3, IP6SPORTM, 0xffff, hw->msk[3]); - } - } - - SW_SET_REG_BY_FIELD(IP6_RUL3_M3, IP6DPORTM_EN, 1, hw->msk[3]); - if (FAL_FIELD_FLG_TST(sw->field_flg, FAL_ACL_FIELD_L4_DPORT)) - { - if ((FAL_ACL_FIELD_MASK != sw->dest_l4port_op) - && (FAL_ACL_FIELD_RANGE != sw->dest_l4port_op) - && (FAL_ACL_FIELD_LE != sw->dest_l4port_op) - && (FAL_ACL_FIELD_GE != sw->dest_l4port_op)) - { - return SW_NOT_SUPPORTED; - } - - if (A_FALSE == - _shiva_acl_field_care(sw->dest_l4port_op, sw->dest_l4port_val, - sw->dest_l4port_mask, 0xffff)) - { - if (FAL_ACL_FIELD_MASK == sw->dest_l4port_op) - { - sw->dest_l4port_op = FAL_ACL_FIELD_RANGE; - sw->dest_l4port_val = 0; - sw->dest_l4port_mask = 0xffff; - } - } - *b_care = A_TRUE; - len = 58; - - SW_SET_REG_BY_FIELD(IP6_RUL3_M3, IP6DPORTM_EN, 0, hw->msk[3]); - if (FAL_ACL_FIELD_MASK == sw->dest_l4port_op) - { - sw->dest_l4port_val &= sw->dest_l4port_mask; - SW_SET_REG_BY_FIELD(IP6_RUL3_V2, IP6DPORTV, sw->dest_l4port_val, - hw->vlu[2]); - SW_SET_REG_BY_FIELD(IP6_RUL3_M2, IP6DPORTM, sw->dest_l4port_mask, - hw->msk[2]); - SW_SET_REG_BY_FIELD(IP6_RUL3_M3, IP6DPORTM_EN, 1, hw->msk[3]); - } - else if (FAL_ACL_FIELD_RANGE == sw->dest_l4port_op) - { - SW_SET_REG_BY_FIELD(IP6_RUL3_V2, IP6DPORTV, sw->dest_l4port_val, - hw->vlu[2]); - SW_SET_REG_BY_FIELD(IP6_RUL3_M2, IP6DPORTM, sw->dest_l4port_mask, - hw->msk[2]); - } - else if (FAL_ACL_FIELD_LE == sw->dest_l4port_op) - { - SW_SET_REG_BY_FIELD(IP6_RUL3_V2, IP6DPORTV, 0, hw->vlu[2]); - SW_SET_REG_BY_FIELD(IP6_RUL3_M2, IP6DPORTM, sw->dest_l4port_val, - hw->msk[2]); - } - else - { - SW_SET_REG_BY_FIELD(IP6_RUL3_V2, IP6DPORTV, sw->dest_l4port_val, - hw->vlu[2]); - SW_SET_REG_BY_FIELD(IP6_RUL3_M2, IP6DPORTM, 0xffff, hw->msk[2]); - } - } - - SW_SET_REG_BY_FIELD(RUL_SLCT6, RULE_LEN, len, hw->len); - - return SW_OK; -} - -#define SHIVA_MAX_UDF_OFFSET 127 -#define SHIVA_MAX_UDF_LENGTH 16 - -static sw_error_t -_shiva_acl_rule_udf_parse(fal_acl_rule_t * sw, - shiva_acl_hw_rule_t * hw, a_bool_t * b_care) -{ - a_uint32_t i, len = 0; - - if (FAL_ACL_UDF_TYPE_BUTT <= sw->udf_type) - { - return SW_BAD_PARAM; - } - - if (SHIVA_MAX_UDF_OFFSET < sw->udf_offset) - { - return SW_NOT_SUPPORTED; - } - - if (sw->udf_offset % 2) - { - return SW_NOT_SUPPORTED; - } - - if (SHIVA_MAX_UDF_LENGTH < sw->udf_len) - { - return SW_NOT_SUPPORTED; - } - - aos_mem_zero(&(hw->vlu[0]), sizeof (hw->vlu)); - aos_mem_zero(&(hw->msk[0]), sizeof (hw->msk)); - aos_mem_zero(&(hw->typ), sizeof (hw->typ)); - aos_mem_zero(&(hw->len), sizeof (hw->len)); - - *b_care = A_FALSE; - - SW_SET_REG_BY_FIELD(RUL_SLCT7, RULE_TYP, SHIVA_UDF_FILTER, hw->typ); - - if (!FAL_FIELD_FLG_TST(sw->field_flg, FAL_ACL_FIELD_UDF)) - { - return SW_OK; - } - - *b_care = A_TRUE; - if (FAL_ACL_UDF_TYPE_L2 == sw->udf_type) - { - SW_SET_REG_BY_FIELD(UDF_RUL_V4, LAYER_TYP, 0, hw->vlu[4]); - len = sw->udf_offset + sw->udf_len; - } - else - { - SW_SET_REG_BY_FIELD(UDF_RUL_V4, LAYER_TYP, 1, hw->vlu[4]); - len = 14 + sw->udf_offset + sw->udf_len; - } - SW_SET_REG_BY_FIELD(RUL_SLCT6, RULE_LEN, len, hw->len); - - SW_SET_REG_BY_FIELD(UDF_RUL_V4, LAYER_OFFSET, sw->udf_offset, hw->vlu[4]); - - for (i = 0; i < sw->udf_len; i++) - { - hw->vlu[3 - i / 4] |= ((sw->udf_mask[i] & sw->udf_val[i]) << (24 - 8 * (i % 4))); - hw->msk[3 - i / 4] |= ((sw->udf_mask[i]) << (24 - 8 * i)); - } - - return SW_OK; -} - -static sw_error_t -_shiva_acl_action_parse(a_uint32_t dev_id, const fal_acl_rule_t * sw, - shiva_acl_hw_rule_t * hw) -{ - aos_mem_zero(&(hw->act[0]), sizeof (hw->act)); - - if ((FAL_ACTION_FLG_TST(sw->action_flg, FAL_ACL_ACTION_MODIFY_VLAN)) - && (FAL_ACTION_FLG_TST(sw->action_flg, FAL_ACL_ACTION_NEST_VLAN))) - { - return SW_NOT_SUPPORTED; - } - - /* FAL_ACL_ACTION_PERMIT need't process */ - - /* we should ignore any other action flags when DENY bit is settd. */ - if (FAL_ACTION_FLG_TST(sw->action_flg, FAL_ACL_ACTION_DENY)) - { - SW_SET_REG_BY_FIELD(ACL_RSLT1, DES_PORT_EN, 1, hw->act[1]); - SW_SET_REG_BY_FIELD(ACL_RSLT1, PORT_MEM, 0, hw->act[1]); - return SW_OK; - } - - if (FAL_ACTION_FLG_TST(sw->action_flg, FAL_ACL_ACTION_RDTCPU)) - { - SW_SET_REG_BY_FIELD(ACL_RSLT2, RDTCPU, 1, hw->act[2]); - } - - if (FAL_ACTION_FLG_TST(sw->action_flg, FAL_ACL_ACTION_CPYCPU)) - { - SW_SET_REG_BY_FIELD(ACL_RSLT2, CPYCPU, 1, hw->act[2]); - } - - if (FAL_ACTION_FLG_TST(sw->action_flg, FAL_ACL_ACTION_MIRROR)) - { - SW_SET_REG_BY_FIELD(ACL_RSLT1, MIRR_EN, 1, hw->act[1]); - } - - if (FAL_ACTION_FLG_TST(sw->action_flg, FAL_ACL_ACTION_REDPT)) - { - SW_SET_REG_BY_FIELD(ACL_RSLT1, DES_PORT_EN, 1, hw->act[1]); - SW_SET_REG_BY_FIELD(ACL_RSLT1, PORT_MEM, sw->ports, hw->act[1]); - } - - if (FAL_ACTION_FLG_TST(sw->action_flg, FAL_ACL_ACTION_REMARK_UP)) - { - SW_SET_REG_BY_FIELD(ACL_RSLT1, REMARK_DOT1P, 1, hw->act[1]); - SW_SET_REG_BY_FIELD(ACL_RSLT1, DOT1P, sw->up, hw->act[1]); - } - - if (FAL_ACTION_FLG_TST(sw->action_flg, FAL_ACL_ACTION_REMARK_QUEUE)) - { - SW_SET_REG_BY_FIELD(ACL_RSLT1, REMARK_PRI_QU, 1, hw->act[1]); - SW_SET_REG_BY_FIELD(ACL_RSLT1, PRI_QU, sw->queue, hw->act[1]); - } - - if ((FAL_ACTION_FLG_TST(sw->action_flg, FAL_ACL_ACTION_MODIFY_VLAN)) - || (FAL_ACTION_FLG_TST(sw->action_flg, FAL_ACL_ACTION_NEST_VLAN))) - { - - SW_SET_REG_BY_FIELD(ACL_RSLT1, CHG_VID_EN, 1, hw->act[1]); - SW_SET_REG_BY_FIELD(ACL_RSLT1, VID, sw->vid, hw->act[1]); - SW_SET_REG_BY_FIELD(ACL_RSLT1, STAG_CHG_EN, 1, hw->act[1]); - if (FAL_ACTION_FLG_TST(sw->action_flg, FAL_ACL_ACTION_MODIFY_VLAN)) - { - SW_SET_REG_BY_FIELD(ACL_RSLT1, STAG_CHG_EN, 0, hw->act[1]); - - if (!FAL_ACTION_FLG_TST(sw->action_flg, FAL_ACL_ACTION_REDPT)) - { - SW_SET_REG_BY_FIELD(ACL_RSLT1, VID_MEM_EN, 1, hw->act[1]); - SW_SET_REG_BY_FIELD(ACL_RSLT1, PORT_MEM, sw->ports, hw->act[1]); - } - } - } - - return SW_OK; -} - -static sw_error_t -_shiva_acl_rule_mac_reparse(fal_acl_rule_t * sw, - const shiva_acl_hw_rule_t * hw) -{ - a_uint32_t mask_en; - - /* destnation mac address */ - SW_GET_FIELD_BY_REG(MAC_RUL_V0, DAV_BYTE2, sw->dest_mac_val.uc[2], - hw->vlu[0]); - SW_GET_FIELD_BY_REG(MAC_RUL_V0, DAV_BYTE3, sw->dest_mac_val.uc[3], - hw->vlu[0]); - SW_GET_FIELD_BY_REG(MAC_RUL_V0, DAV_BYTE4, sw->dest_mac_val.uc[4], - hw->vlu[0]); - SW_GET_FIELD_BY_REG(MAC_RUL_V0, DAV_BYTE5, sw->dest_mac_val.uc[5], - hw->vlu[0]); - SW_GET_FIELD_BY_REG(MAC_RUL_V1, DAV_BYTE0, sw->dest_mac_val.uc[0], - hw->vlu[1]); - SW_GET_FIELD_BY_REG(MAC_RUL_V1, DAV_BYTE1, sw->dest_mac_val.uc[1], - hw->vlu[1]); - - SW_GET_FIELD_BY_REG(MAC_RUL_M0, DAM_BYTE2, sw->dest_mac_mask.uc[2], - hw->msk[0]); - SW_GET_FIELD_BY_REG(MAC_RUL_M0, DAM_BYTE3, sw->dest_mac_mask.uc[3], - hw->msk[0]); - SW_GET_FIELD_BY_REG(MAC_RUL_M0, DAM_BYTE4, sw->dest_mac_mask.uc[4], - hw->msk[0]); - SW_GET_FIELD_BY_REG(MAC_RUL_M0, DAM_BYTE5, sw->dest_mac_mask.uc[5], - hw->msk[0]); - SW_GET_FIELD_BY_REG(MAC_RUL_M1, DAM_BYTE0, sw->dest_mac_mask.uc[0], - hw->msk[1]); - SW_GET_FIELD_BY_REG(MAC_RUL_M1, DAM_BYTE1, sw->dest_mac_mask.uc[1], - hw->msk[1]); - if (A_FALSE == _shiva_acl_zero_addr(sw->dest_mac_mask)) - { - FAL_FIELD_FLG_SET(sw->field_flg, FAL_ACL_FIELD_MAC_DA); - } - - /* source mac address */ - SW_GET_FIELD_BY_REG(MAC_RUL_V2, SAV_BYTE0, sw->src_mac_val.uc[0], - hw->vlu[2]); - SW_GET_FIELD_BY_REG(MAC_RUL_V2, SAV_BYTE1, sw->src_mac_val.uc[1], - hw->vlu[2]); - SW_GET_FIELD_BY_REG(MAC_RUL_V2, SAV_BYTE2, sw->src_mac_val.uc[2], - hw->vlu[2]); - SW_GET_FIELD_BY_REG(MAC_RUL_V2, SAV_BYTE3, sw->src_mac_val.uc[3], - hw->vlu[2]); - SW_GET_FIELD_BY_REG(MAC_RUL_V1, SAV_BYTE4, sw->src_mac_val.uc[4], - hw->vlu[1]); - SW_GET_FIELD_BY_REG(MAC_RUL_V1, SAV_BYTE5, sw->src_mac_val.uc[5], - hw->vlu[1]); - - SW_GET_FIELD_BY_REG(MAC_RUL_M2, SAM_BYTE0, sw->src_mac_mask.uc[0], - hw->msk[2]); - SW_GET_FIELD_BY_REG(MAC_RUL_M2, SAM_BYTE1, sw->src_mac_mask.uc[1], - hw->msk[2]); - SW_GET_FIELD_BY_REG(MAC_RUL_M2, SAM_BYTE2, sw->src_mac_mask.uc[2], - hw->msk[2]); - SW_GET_FIELD_BY_REG(MAC_RUL_M2, SAM_BYTE3, sw->src_mac_mask.uc[3], - hw->msk[2]); - SW_GET_FIELD_BY_REG(MAC_RUL_M1, SAM_BYTE4, sw->src_mac_mask.uc[4], - hw->msk[1]); - SW_GET_FIELD_BY_REG(MAC_RUL_M1, SAM_BYTE5, sw->src_mac_mask.uc[5], - hw->msk[1]); - if (A_FALSE == _shiva_acl_zero_addr(sw->src_mac_mask)) - { - FAL_FIELD_FLG_SET(sw->field_flg, FAL_ACL_FIELD_MAC_SA); - } - - /* ethernet type */ - SW_GET_FIELD_BY_REG(MAC_RUL_V3, ETHTYPV, sw->ethtype_val, hw->vlu[3]); - SW_GET_FIELD_BY_REG(MAC_RUL_M3, ETHTYPM, sw->ethtype_mask, hw->msk[3]); - if (0x0 != sw->ethtype_mask) - { - FAL_FIELD_FLG_SET(sw->field_flg, FAL_ACL_FIELD_MAC_ETHTYPE); - } - - /* packet tagged */ - SW_GET_FIELD_BY_REG(MAC_RUL_V4, TAGGEDV, sw->tagged_val, hw->vlu[4]); - SW_GET_FIELD_BY_REG(MAC_RUL_V4, TAGGEDM, sw->tagged_mask, hw->vlu[4]); - if (0x0 != sw->tagged_mask) - { - FAL_FIELD_FLG_SET(sw->field_flg, FAL_ACL_FIELD_MAC_TAGGED); - } - - /* vlan priority */ - SW_GET_FIELD_BY_REG(MAC_RUL_V3, VLANPRIV, sw->up_val, hw->vlu[3]); - SW_GET_FIELD_BY_REG(MAC_RUL_M3, VLANPRIM, sw->up_mask, hw->msk[3]); - if (0x0 != sw->up_mask) - { - FAL_FIELD_FLG_SET(sw->field_flg, FAL_ACL_FIELD_MAC_UP); - } - - /* vlanid */ - SW_GET_FIELD_BY_REG(MAC_RUL_V3, VLANIDV, sw->vid_val, hw->vlu[3]); - SW_GET_FIELD_BY_REG(MAC_RUL_M3, VLANIDM, sw->vid_mask, hw->msk[3]); - SW_GET_FIELD_BY_REG(MAC_RUL_V4, VIDMSK, mask_en, hw->vlu[4]); - if (mask_en) - { - sw->vid_op = FAL_ACL_FIELD_MASK; - } - else - { - sw->vid_op = FAL_ACL_FIELD_RANGE; - } - - if (A_TRUE == - _shiva_acl_field_care(sw->vid_op, (a_uint32_t) sw->vid_val, - (a_uint32_t) sw->vid_mask, 0xfff)) - { - FAL_FIELD_FLG_SET(sw->field_flg, FAL_ACL_FIELD_MAC_VID); - } - - /* vlan cfi */ - SW_GET_FIELD_BY_REG(MAC_RUL_V3, VLANCFIV, sw->cfi_val, hw->vlu[3]); - SW_GET_FIELD_BY_REG(MAC_RUL_M3, VLANCFIM, sw->cfi_mask, hw->msk[3]); - if (0x0 != sw->cfi_mask) - { - FAL_FIELD_FLG_SET(sw->field_flg, FAL_ACL_FIELD_MAC_CFI); - } - - return SW_OK; -} - -static sw_error_t -_shiva_acl_rule_ip4_reparse(fal_acl_rule_t * sw, - const shiva_acl_hw_rule_t * hw) -{ - a_uint32_t mask_en; - - sw->dest_ip4_val = hw->vlu[0]; - sw->dest_ip4_mask = hw->msk[0]; - if (0x0 != sw->dest_ip4_mask) - { - FAL_FIELD_FLG_SET(sw->field_flg, FAL_ACL_FIELD_IP4_DIP); - } - - sw->src_ip4_val = hw->vlu[1]; - sw->src_ip4_mask = hw->msk[1]; - if (0x0 != sw->src_ip4_mask) - { - FAL_FIELD_FLG_SET(sw->field_flg, FAL_ACL_FIELD_IP4_SIP); - } - - SW_GET_FIELD_BY_REG(IP4_RUL_V2, IP4PROTV, sw->ip_proto_val, hw->vlu[2]); - SW_GET_FIELD_BY_REG(IP4_RUL_M2, IP4PROTM, sw->ip_proto_mask, hw->msk[2]); - if (0x0 != sw->ip_proto_mask) - { - FAL_FIELD_FLG_SET(sw->field_flg, FAL_ACL_FIELD_IP_PROTO); - } - - SW_GET_FIELD_BY_REG(IP4_RUL_V2, IP4DSCPV, sw->ip_dscp_val, hw->vlu[2]); - SW_GET_FIELD_BY_REG(IP4_RUL_M2, IP4DSCPM, sw->ip_dscp_mask, hw->msk[2]); - if (0x0 != sw->ip_dscp_mask) - { - FAL_FIELD_FLG_SET(sw->field_flg, FAL_ACL_FIELD_IP_DSCP); - } - - SW_GET_FIELD_BY_REG(IP4_RUL_V2, IP4DPORTV, sw->dest_l4port_val, hw->vlu[2]); - SW_GET_FIELD_BY_REG(IP4_RUL_M2, IP4DPORTM, sw->dest_l4port_mask, - hw->msk[2]); - SW_GET_FIELD_BY_REG(IP4_RUL_M3, IP4DPORTM_EN, mask_en, hw->msk[3]); - if (mask_en) - { - sw->dest_l4port_op = FAL_ACL_FIELD_MASK; - } - else - { - sw->dest_l4port_op = FAL_ACL_FIELD_RANGE; - } - - if (A_TRUE == - _shiva_acl_field_care(sw->dest_l4port_op, - (a_uint32_t) sw->dest_l4port_val, - (a_uint32_t) sw->dest_l4port_mask, 0xffff)) - { - FAL_FIELD_FLG_SET(sw->field_flg, FAL_ACL_FIELD_L4_DPORT); - } - else if (FAL_ACL_FIELD_RANGE == sw->dest_l4port_op) - { - FAL_FIELD_FLG_SET(sw->field_flg, FAL_ACL_FIELD_L4_DPORT); - } - - SW_GET_FIELD_BY_REG(IP4_RUL_V3, IP4SPORTV, sw->src_l4port_val, hw->vlu[3]); - SW_GET_FIELD_BY_REG(IP4_RUL_M3, IP4SPORTM, sw->src_l4port_mask, hw->msk[3]); - SW_GET_FIELD_BY_REG(IP4_RUL_M3, IP4SPORTM_EN, mask_en, hw->msk[3]); - if (mask_en) - { - sw->src_l4port_op = FAL_ACL_FIELD_MASK; - } - else - { - sw->src_l4port_op = FAL_ACL_FIELD_RANGE; - } - - if (A_TRUE == - _shiva_acl_field_care(sw->src_l4port_op, - (a_uint32_t) sw->src_l4port_val, - (a_uint32_t) sw->src_l4port_mask, 0xffff)) - { - FAL_FIELD_FLG_SET(sw->field_flg, FAL_ACL_FIELD_L4_SPORT); - } - else if (FAL_ACL_FIELD_RANGE == sw->src_l4port_op) - { - FAL_FIELD_FLG_SET(sw->field_flg, FAL_ACL_FIELD_L4_SPORT); - } - - return SW_OK; -} - -static sw_error_t -_shiva_acl_rule_ip6r1_reparse(fal_acl_rule_t * sw, - const shiva_acl_hw_rule_t * hw) -{ - a_uint32_t i; - - for (i = 0; i < 4; i++) - { - sw->dest_ip6_val.ul[i] = hw->vlu[3 - i]; - sw->dest_ip6_mask.ul[i] = hw->msk[3 - i]; - if (0x0 != sw->dest_ip6_mask.ul[i]) - { - FAL_FIELD_FLG_SET(sw->field_flg, FAL_ACL_FIELD_IP6_DIP); - } - } - return SW_OK; -} - -static sw_error_t -_shiva_acl_rule_ip6r2_reparse(fal_acl_rule_t * sw, - const shiva_acl_hw_rule_t * hw) -{ - a_uint32_t i; - - for (i = 0; i < 4; i++) - { - sw->src_ip6_val.ul[i] = hw->vlu[3 - i]; - sw->src_ip6_mask.ul[i] = hw->msk[3 - i]; - if (0x0 != sw->src_ip6_mask.ul[i]) - { - FAL_FIELD_FLG_SET(sw->field_flg, FAL_ACL_FIELD_IP6_SIP); - } - } - return SW_OK; -} - -static sw_error_t -_shiva_acl_rule_ip6r3_reparse(fal_acl_rule_t * sw, - const shiva_acl_hw_rule_t * hw) -{ - a_uint32_t mask_en; - a_uint32_t tmp; - - SW_GET_FIELD_BY_REG(IP6_RUL3_V0, IP6PROTV, sw->ip_proto_val, hw->vlu[0]); - SW_GET_FIELD_BY_REG(IP6_RUL3_M0, IP6PROTM, sw->ip_proto_mask, hw->msk[0]); - if (0x0 != sw->ip_proto_mask) - { - FAL_FIELD_FLG_SET(sw->field_flg, FAL_ACL_FIELD_IP_PROTO); - } - - SW_GET_FIELD_BY_REG(IP6_RUL3_V0, IP6DSCPV, sw->ip_dscp_val, hw->vlu[0]); - SW_GET_FIELD_BY_REG(IP6_RUL3_M0, IP6DSCPM, sw->ip_dscp_mask, hw->msk[0]); - if (0x0 != sw->ip_dscp_mask) - { - FAL_FIELD_FLG_SET(sw->field_flg, FAL_ACL_FIELD_IP_DSCP); - } - - SW_GET_FIELD_BY_REG(IP6_RUL3_V2, IP6DPORTV, sw->dest_l4port_val, - hw->vlu[2]); - SW_GET_FIELD_BY_REG(IP6_RUL3_M2, IP6DPORTM, sw->dest_l4port_mask, - hw->msk[2]); - SW_GET_FIELD_BY_REG(IP6_RUL3_M3, IP6DPORTM_EN, mask_en, hw->msk[3]); - if (mask_en) - { - sw->dest_l4port_op = FAL_ACL_FIELD_MASK; - } - else - { - sw->dest_l4port_op = FAL_ACL_FIELD_RANGE; - } - - if (A_TRUE == - _shiva_acl_field_care(sw->dest_l4port_op, - (a_uint32_t) sw->dest_l4port_val, - (a_uint32_t) sw->dest_l4port_mask, 0xffff)) - { - FAL_FIELD_FLG_SET(sw->field_flg, FAL_ACL_FIELD_L4_DPORT); - } - else if (FAL_ACL_FIELD_RANGE == sw->dest_l4port_op) - { - FAL_FIELD_FLG_SET(sw->field_flg, FAL_ACL_FIELD_L4_DPORT); - } - - SW_GET_FIELD_BY_REG(IP6_RUL3_V3, IP6SPORTV, sw->src_l4port_val, hw->vlu[3]); - SW_GET_FIELD_BY_REG(IP6_RUL3_M3, IP6SPORTM, sw->src_l4port_mask, - hw->msk[3]); - SW_GET_FIELD_BY_REG(IP6_RUL3_M3, IP6SPORTM_EN, mask_en, hw->msk[3]); - if (mask_en) - { - sw->src_l4port_op = FAL_ACL_FIELD_MASK; - } - else - { - sw->src_l4port_op = FAL_ACL_FIELD_RANGE; - } - - if (A_TRUE == - _shiva_acl_field_care(sw->src_l4port_op, - (a_uint32_t) sw->src_l4port_val, - (a_uint32_t) sw->src_l4port_mask, 0xffff)) - { - FAL_FIELD_FLG_SET(sw->field_flg, FAL_ACL_FIELD_L4_SPORT); - } - else if (FAL_ACL_FIELD_RANGE == sw->src_l4port_op) - { - FAL_FIELD_FLG_SET(sw->field_flg, FAL_ACL_FIELD_L4_SPORT); - } - - SW_GET_FIELD_BY_REG(IP6_RUL3_V1, IP6LABEL1V, sw->ip6_lable_val, hw->vlu[1]); - SW_GET_FIELD_BY_REG(IP6_RUL3_M1, IP6LABEL1M, sw->ip6_lable_mask, - hw->msk[1]); - - SW_GET_FIELD_BY_REG(IP6_RUL3_V2, IP6LABEL2V, tmp, hw->vlu[2]); - sw->ip6_lable_val |= (tmp << 16); - SW_GET_FIELD_BY_REG(IP6_RUL3_M2, IP6LABEL2M, tmp, hw->msk[2]); - sw->ip6_lable_mask |= (tmp << 16); - - if (0x0 != sw->ip6_lable_mask) - { - FAL_FIELD_FLG_SET(sw->field_flg, FAL_ACL_FIELD_IP6_LABEL); - } - - return SW_OK; -} - -static sw_error_t -_shiva_acl_rule_udf_reparse(fal_acl_rule_t * sw, - const shiva_acl_hw_rule_t * hw) -{ - a_uint32_t i, tmp; - - FAL_FIELD_FLG_SET(sw->field_flg, FAL_ACL_FIELD_UDF); - - SW_GET_FIELD_BY_REG(UDF_RUL_V4, LAYER_OFFSET, tmp, hw->vlu[4]); - sw->udf_offset = tmp; - - SW_GET_FIELD_BY_REG(UDF_RUL_V4, LAYER_TYP, tmp, hw->vlu[4]); - if (tmp) - { - sw->udf_type = FAL_ACL_UDF_TYPE_L3; - sw->udf_len = hw->len - sw->udf_offset - 14; - } - else - { - sw->udf_type = FAL_ACL_UDF_TYPE_L2; - sw->udf_len = hw->len - sw->udf_offset; - } - - if (SHIVA_MAX_UDF_LENGTH < sw->udf_len) - { - return SW_READ_ERROR; - } - - for (i = 0; i < sw->udf_len; i++) - { - sw->udf_val[i] = ((hw->vlu[3 - i / 4]) >> (24 - 8 * (i % 4))) & 0xff; - sw->udf_mask[i] = ((hw->msk[3 - i / 4]) >> (24 - 8 * (i % 4))) & 0xff; - } - - return SW_OK; -} - -static sw_error_t -_shiva_acl_rule_action_reparse(fal_acl_rule_t * sw, - const shiva_acl_hw_rule_t * hw) -{ - a_uint32_t data; - - sw->match_cnt = hw->act[0]; - - sw->action_flg = 0; - SW_GET_FIELD_BY_REG(ACL_RSLT1, DES_PORT_EN, data, (hw->act[1])); - if (1 == data) - { - SW_GET_FIELD_BY_REG(ACL_RSLT1, PORT_MEM, data, (hw->act[1])); - sw->ports = data; - - FAL_ACTION_FLG_SET(sw->action_flg, FAL_ACL_ACTION_REDPT); - } - - SW_GET_FIELD_BY_REG(ACL_RSLT2, RDTCPU, data, (hw->act[2])); - if (1 == data) - { - FAL_ACTION_FLG_SET(sw->action_flg, FAL_ACL_ACTION_RDTCPU); - } - - SW_GET_FIELD_BY_REG(ACL_RSLT2, CPYCPU, data, (hw->act[2])); - if (1 == data) - { - FAL_ACTION_FLG_SET(sw->action_flg, FAL_ACL_ACTION_CPYCPU); - } - - SW_GET_FIELD_BY_REG(ACL_RSLT1, MIRR_EN, data, (hw->act[1])); - if (1 == data) - { - FAL_ACTION_FLG_SET(sw->action_flg, FAL_ACL_ACTION_MIRROR); - } - - SW_GET_FIELD_BY_REG(ACL_RSLT1, REMARK_DOT1P, data, (hw->act[1])); - if (1 == data) - { - SW_GET_FIELD_BY_REG(ACL_RSLT1, DOT1P, data, (hw->act[1])); - sw->up = data & 0x7; - - FAL_ACTION_FLG_SET(sw->action_flg, FAL_ACL_ACTION_REMARK_UP); - } - - SW_GET_FIELD_BY_REG(ACL_RSLT1, REMARK_PRI_QU, data, (hw->act[1])); - if (1 == data) - { - SW_GET_FIELD_BY_REG(ACL_RSLT1, PRI_QU, data, (hw->act[1])); - sw->queue = data & 0x3; - - FAL_ACTION_FLG_SET(sw->action_flg, FAL_ACL_ACTION_REMARK_QUEUE); - } - - SW_GET_FIELD_BY_REG(ACL_RSLT1, CHG_VID_EN, data, (hw->act[1])); - if (1 == data) - { - SW_GET_FIELD_BY_REG(ACL_RSLT1, STAG_CHG_EN, data, (hw->act[1])); - if (1 == data) - { - FAL_ACTION_FLG_SET(sw->action_flg, FAL_ACL_ACTION_NEST_VLAN); - } - else - { - FAL_ACTION_FLG_SET(sw->action_flg, FAL_ACL_ACTION_MODIFY_VLAN); - SW_GET_FIELD_BY_REG(ACL_RSLT1, PORT_MEM, data, (hw->act[1])); - sw->ports = data; - } - } - - SW_GET_FIELD_BY_REG(ACL_RSLT1, VID, data, (hw->act[1])); - sw->vid = data & 0xfff; - - return SW_OK; -} - -static sw_error_t -_shiva_acl_filter_alloc(a_uint32_t dev_id, a_uint32_t * idx) -{ - a_uint32_t i; - - for (i = 0; i < SHIVA_MAX_RULE; i++) - { - if (0 == (filter_snap[dev_id] & (0x1UL << i))) - { - filter_snap[dev_id] |= (0x1UL << i); - *idx = i; - return SW_OK; - } - } - return SW_NO_RESOURCE; -} - -static void -_shiva_acl_filter_free(a_uint32_t dev_id, a_uint32_t idx) -{ - filter_snap[dev_id] &= (~(0x1UL << idx)); -} - -static void -_shiva_acl_filter_snap(a_uint32_t dev_id) -{ - filter_snap[dev_id] = filter[dev_id]; - return; -} - -static void -_shiva_acl_filter_commit(a_uint32_t dev_id) -{ - filter[dev_id] = filter_snap[dev_id]; - return; -} - -static sw_error_t -_shiva_acl_slct_update(shiva_acl_hw_rule_t * hw, a_uint32_t offset, - a_uint32_t flt_idx) -{ - switch (offset) - { - case 0: - SW_SET_REG_BY_FIELD(RUL_SLCT0, ADDR0_EN, 1, hw->slct[0]); - SW_SET_REG_BY_FIELD(RUL_SLCT1, ADDR0, flt_idx, hw->slct[1]); - break; - - case 1: - SW_SET_REG_BY_FIELD(RUL_SLCT0, ADDR1_EN, 1, hw->slct[0]); - SW_SET_REG_BY_FIELD(RUL_SLCT2, ADDR1, flt_idx, hw->slct[2]); - break; - - case 2: - SW_SET_REG_BY_FIELD(RUL_SLCT0, ADDR2_EN, 1, hw->slct[0]); - SW_SET_REG_BY_FIELD(RUL_SLCT3, ADDR2, flt_idx, hw->slct[3]); - break; - - case 3: - SW_SET_REG_BY_FIELD(RUL_SLCT0, ADDR3_EN, 1, hw->slct[0]); - SW_SET_REG_BY_FIELD(RUL_SLCT4, ADDR3, flt_idx, hw->slct[4]); - break; - - default: - return SW_FAIL; - } - return SW_OK; -} - -static sw_error_t -_shiva_acl_filter_write(a_uint32_t dev_id, const shiva_acl_hw_rule_t * rule, - a_uint32_t flt_idx) -{ -#ifdef SHIVA_SW_ENTRY - char *memaddr; - - memaddr = flt_vlu_mem + (flt_idx << 5); - aos_mem_copy(memaddr, (char *) &(rule->vlu[0]), sizeof(rule->vlu)); - - memaddr = flt_msk_mem + (flt_idx << 5); - aos_mem_copy(memaddr, (char *) &(rule->msk[0]), sizeof(rule->vlu)); - - memaddr = flt_typ_mem + (flt_idx << 5); - aos_mem_copy(memaddr, (char *) &(rule->typ), sizeof(rule->typ)); - - memaddr = flt_len_mem + (flt_idx << 5); - aos_mem_copy(memaddr, (char *) &(rule->len), sizeof(rule->len)); - -#else - sw_error_t rv; - a_uint32_t i, base, addr; - - /* set filter value */ - base = SHIVA_RULE_VLU_ADDR + (flt_idx << 5); - for (i = 0; i < (sizeof(rule->vlu) / sizeof(a_uint32_t)); i++) - { - addr = base + (i << 2); - HSL_REG_ENTRY_GEN_SET(rv, dev_id, addr, sizeof (a_uint32_t), - (a_uint8_t *) (&(rule->vlu[i])), - sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - } - - /* set filter mask */ - base = SHIVA_RULE_MSK_ADDR + (flt_idx << 5); - for (i = 0; i < (sizeof(rule->msk) / sizeof(a_uint32_t)); i++) - { - addr = base + (i << 2); - HSL_REG_ENTRY_GEN_SET(rv, dev_id, addr, sizeof (a_uint32_t), - (a_uint8_t *) (&(rule->msk[i])), - sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - } - - /* set filter type */ - addr = SHIVA_RULE_TYP_ADDR + (flt_idx << 5); - HSL_REG_ENTRY_GEN_SET(rv, dev_id, addr, sizeof (a_uint32_t), - (a_uint8_t *) (&(rule->typ)), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - - /* set filter length */ - addr = SHIVA_RULE_LEN_ADDR + (flt_idx << 5); - HSL_REG_ENTRY_GEN_SET(rv, dev_id, addr, sizeof (a_uint32_t), - (a_uint8_t *) (&(rule->len)), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); -#endif - -#ifdef SHIVA_ENTRY_DUMP - a_uint32_t j; - aos_printk("\n_shiva_acl_filter_write flt_idx = %d type = %d len = %d\n", - flt_idx, rule->typ, rule->len); - for (j = 0; j < (sizeof(rule->vlu) / sizeof(a_uint32_t)); j++) - { - aos_printk("%08x ", rule->vlu[j]); - } - aos_printk("\n"); - for (j = 0; j < (sizeof(rule->msk) / sizeof(a_uint32_t)); j++) - { - aos_printk("%08x ", rule->msk[j]); - } -#endif - - return SW_OK; -} - -static sw_error_t -_shiva_acl_action_write(a_uint32_t dev_id, const shiva_acl_hw_rule_t * rule, - a_uint32_t act_idx) -{ -#ifdef SHIVA_SW_ENTRY - char *memaddr; - - memaddr = act_mem + (act_idx << 5); - aos_mem_copy(memaddr, (char *) &(rule->act[0]), sizeof(rule->act)); - -#else - sw_error_t rv; - a_uint32_t i, base, addr; - - /* set rule action */ - base = SHIVA_RULE_ACT_ADDR + (act_idx << 5); - for (i = 0; i < (sizeof(rule->act) / sizeof(a_uint32_t)); i++) - { - addr = base + (i << 2); - HSL_REG_ENTRY_GEN_SET(rv, dev_id, addr, sizeof (a_uint32_t), - (a_uint8_t *) (&(rule->act[i])), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - } -#endif - -#ifdef SHIVA_ENTRY_DUMP - a_uint32_t j; - aos_printk("\n_shiva_acl_action_write act_idx = %d\n", act_idx); - for (j = 0; j < (sizeof(rule->act) / sizeof(a_uint32_t)); j++) - { - aos_printk("%08x ", rule->act[j]); - } -#endif - - return SW_OK; -} - -static sw_error_t -_shiva_acl_slct_write(a_uint32_t dev_id, const shiva_acl_hw_rule_t * rule, - a_uint32_t slct_idx) -{ -#ifdef SHIVA_SW_ENTRY - char *memaddr; - - memaddr = slct_mem + (slct_idx << 5); - aos_mem_copy(memaddr, (char *) &(rule->slct[0]), sizeof(rule->slct)); - -#else - sw_error_t rv; - a_uint32_t base, addr; - a_uint32_t i; - - base = SHIVA_RULE_SLCT_ADDR + (slct_idx << 5); - - /* set filter address and source ports bitmap*/ - for (i = 1; i < (sizeof(rule->slct) / sizeof(a_uint32_t)); i++) - { - addr = base + (i << 2); - HSL_REG_ENTRY_GEN_SET(rv, dev_id, addr, sizeof (a_uint32_t), - (a_uint8_t *) (&(rule->slct[i])), - sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - } - - /* set filter enable */ - HSL_REG_ENTRY_GEN_SET(rv, dev_id, base, sizeof (a_uint32_t), - (a_uint8_t *) (&(rule->slct[0])), - sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); -#endif - -#ifdef SHIVA_ENTRY_DUMP - a_uint32_t j; - aos_printk("\n_shiva_acl_slct_write slct_idx = %d\n", slct_idx); - for (j = 0; j < (sizeof(rule->slct) / sizeof(a_uint32_t)); j++) - { - aos_printk("%08x ", rule->slct[j]); - } -#endif - - return SW_OK; -} - -static sw_error_t -_shiva_acl_filter_read(a_uint32_t dev_id, shiva_acl_hw_rule_t * rule, - a_uint32_t flt_idx) -{ -#ifdef SHIVA_SW_ENTRY - char *memaddr; - - memaddr = flt_vlu_mem + (flt_idx << 5); - aos_mem_copy((char *) &(rule->vlu[0]), memaddr, 20); - - memaddr = flt_msk_mem + (flt_idx << 5); - aos_mem_copy((char *) &(rule->msk[0]), memaddr, 20); - - memaddr = flt_typ_mem + (flt_idx << 5); - aos_mem_copy((char *) &(rule->typ), memaddr, 4); - - memaddr = flt_len_mem + (flt_idx << 5); - aos_mem_copy((char *) &(rule->len), memaddr, 4); - -#else - sw_error_t rv; - a_uint32_t i, base, addr; - - /* get filter value */ - base = SHIVA_RULE_VLU_ADDR + (flt_idx << 5); - for (i = 0; i < (sizeof(rule->vlu) / sizeof(a_uint32_t)); i++) - { - addr = base + (i << 2); - HSL_REG_ENTRY_GEN_GET(rv, dev_id, addr, sizeof (a_uint32_t), - (a_uint8_t *) (&(rule->vlu[i])), - sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - } - - /* get filter mask */ - base = SHIVA_RULE_MSK_ADDR + (flt_idx << 5); - for (i = 0; i < (sizeof(rule->msk) / sizeof(a_uint32_t)); i++) - { - addr = base + (i << 2); - HSL_REG_ENTRY_GEN_GET(rv, dev_id, addr, sizeof (a_uint32_t), - (a_uint8_t *) (&(rule->msk[i])), - sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - } - - /* get filter type */ - addr = SHIVA_RULE_TYP_ADDR + (flt_idx << 5); - HSL_REG_ENTRY_GEN_GET(rv, dev_id, addr, sizeof (a_uint32_t), - (a_uint8_t *) (&(rule->typ)), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - - /* get filter length */ - addr = SHIVA_RULE_LEN_ADDR + (flt_idx << 5); - HSL_REG_ENTRY_GEN_GET(rv, dev_id, addr, sizeof (a_uint32_t), - (a_uint8_t *) (&(rule->len)), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); -#endif - -#ifdef SHIVA_ENTRY_DUMP - a_uint32_t j; - aos_printk("\n_shiva_acl_filter_read flt_idx = %d type = %d len = %d \n", - flt_idx, rule->typ, rule->len); - for (j = 0; j < (sizeof(rule->vlu) / sizeof(a_uint32_t)); j++) - { - aos_printk("%08x ", rule->vlu[j]); - } - aos_printk("\n"); - for (j = 0; j < (sizeof(rule->msk) / sizeof(a_uint32_t)); j++) - { - aos_printk("%08x ", rule->msk[j]); - } -#endif - - return SW_OK; -} - -static sw_error_t -_shiva_acl_action_read(a_uint32_t dev_id, shiva_acl_hw_rule_t * rule, - a_uint32_t act_idx) -{ -#ifdef SHIVA_SW_ENTRY - char *memaddr; - - memaddr = act_mem + (act_idx << 5); - aos_mem_copy((char *) &(rule->act[0]), memaddr, sizeof(rule->act)); - -#else - sw_error_t rv; - a_uint32_t i, base, addr; - - /* get rule action */ - base = SHIVA_RULE_ACT_ADDR + (act_idx << 5); - for (i = 0; i < (sizeof(rule->act) / sizeof(a_uint32_t)); i++) - { - addr = base + (i << 2); - HSL_REG_ENTRY_GEN_GET(rv, dev_id, addr, sizeof (a_uint32_t), - (a_uint8_t *) (&(rule->act[i])), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - } -#endif - -#ifdef SHIVA_ENTRY_DUMP - a_uint32_t j; - aos_printk("\n_shiva_acl_action_read act_idx = %d ", act_idx); - for (j = 0; j < (sizeof(rule->act) / sizeof(a_uint32_t)); j++) - { - aos_printk("%08x ", rule->act[j]); - } -#endif - - return SW_OK; -} - -static sw_error_t -_shiva_acl_slct_read(a_uint32_t dev_id, shiva_acl_hw_rule_t * rule, - a_uint32_t slct_idx) -{ -#ifdef SHIVA_SW_ENTRY - char *memaddr; - - memaddr = slct_mem + (slct_idx << 5); - aos_mem_copy((char *) &(rule->slct[0]), memaddr, sizeof(rule->slct)); - -#else - sw_error_t rv; - a_uint32_t i, base, addr; - - base = SHIVA_RULE_SLCT_ADDR + (slct_idx << 5); - - /* get filter address and enable and source ports bitmap */ - for (i = 0; i < (sizeof(rule->slct) / sizeof(a_uint32_t)); i++) - { - addr = base + (i << 2); - HSL_REG_ENTRY_GEN_GET(rv, dev_id, addr, sizeof (a_uint32_t), - (a_uint8_t *) (&(rule->slct[i])), - sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - } -#endif - -#ifdef SHIVA_ENTRY_DUMP - a_uint32_t j; - aos_printk("\n_shiva_acl_slct_read slct_idx = %d\n", slct_idx); - for (j = 0; j < (sizeof(rule->slct) / sizeof(a_uint32_t)); j++) - { - aos_printk("%08x ", rule->slct[j]); - } -#endif - - return SW_OK; -} - -static sw_error_t -_shiva_acl_rule_set(a_uint32_t dev_id, a_uint32_t base_addr, - const shiva_acl_hw_rule_t * rule, a_uint32_t rule_nr) -{ - sw_error_t rv; - a_uint32_t ent_idx, tmp_ent_idx; - a_uint32_t i, flt_nr, flt_idx[4] = {0}; - a_uint32_t act_idx, slct_idx; - - act_idx = base_addr; - slct_idx = base_addr; - ent_idx = 0; - for (i = 0; i < rule_nr; i++) - { - tmp_ent_idx = ent_idx; - - rv = _shiva_acl_filter_map_get(&rule[ent_idx], flt_idx, &flt_nr); - SW_RTN_ON_ERROR(rv); - - if (!flt_nr) - { - return SW_FAIL; - } - - for (i = 0; i < flt_nr; i++) - { - rv = _shiva_acl_filter_write(dev_id, &(rule[ent_idx]), flt_idx[i]); - ent_idx++; - } - - rv = _shiva_acl_action_write(dev_id, &(rule[tmp_ent_idx]), act_idx); - SW_RTN_ON_ERROR(rv); - - rv = _shiva_acl_slct_write(dev_id, &(rule[tmp_ent_idx]), slct_idx); - SW_RTN_ON_ERROR(rv); - - act_idx++; - slct_idx++; - } - return SW_OK; -} - -static sw_error_t -_shiva_acl_rule_get(a_uint32_t dev_id, shiva_acl_hw_rule_t * rule, - a_uint32_t * ent_idx, a_uint32_t rule_idx) -{ - sw_error_t rv; - a_uint32_t i = 0, tmp_idx = 0, flt_nr = 0, flt_idx[4] = {0}; - - tmp_idx = *ent_idx; - - rv = _shiva_acl_slct_read(dev_id, &rule[tmp_idx], rule_idx); - SW_RTN_ON_ERROR(rv); - - rv = _shiva_acl_action_read(dev_id, &rule[tmp_idx], rule_idx); - SW_RTN_ON_ERROR(rv); - - rv = _shiva_acl_filter_map_get(&rule[tmp_idx], flt_idx, &flt_nr); - SW_RTN_ON_ERROR(rv); - - for (i = 0; i < flt_nr; i++) - { - rv = _shiva_acl_filter_read(dev_id, &rule[tmp_idx], flt_idx[i]); - SW_RTN_ON_ERROR(rv); - - tmp_idx++; - } - - *ent_idx = tmp_idx; - return SW_OK; -} - -static sw_error_t -_shiva_acl_rule_sw_to_hw(a_uint32_t dev_id, fal_acl_rule_t * sw, - shiva_acl_hw_rule_t * hw, a_uint32_t * idx) -{ - sw_error_t rv; - a_bool_t b_care; - a_bool_t b_valid = A_FALSE; - a_uint32_t tmp_idx; - - tmp_idx = *idx; - if (FAL_ACL_RULE_MAC == sw->rule_type) - { - rv = _shiva_acl_rule_udf_parse(sw, &hw[tmp_idx], &b_care); - SW_RTN_ON_ERROR(rv); - if (A_TRUE == b_care) - { - tmp_idx++; - } - - rv = _shiva_acl_rule_mac_parse(sw, &hw[tmp_idx], &b_care); - SW_RTN_ON_ERROR(rv); - tmp_idx++; - } - else if (FAL_ACL_RULE_IP4 == sw->rule_type) - { - rv = _shiva_acl_rule_udf_parse(sw, &hw[tmp_idx], &b_care); - SW_RTN_ON_ERROR(rv); - if (A_TRUE == b_care) - { - tmp_idx++; - } - - rv = _shiva_acl_rule_mac_parse(sw, &hw[tmp_idx], &b_care); - SW_RTN_ON_ERROR(rv); - if (A_TRUE == b_care) - { - tmp_idx++; - } - - rv = _shiva_acl_rule_ip4_parse(sw, &hw[tmp_idx], &b_care); - SW_RTN_ON_ERROR(rv); - tmp_idx++; - } - else if (FAL_ACL_RULE_IP6 == sw->rule_type) - { - rv = _shiva_acl_rule_udf_parse(sw, &hw[tmp_idx], &b_care); - SW_RTN_ON_ERROR(rv); - if (A_TRUE == b_care) - { - tmp_idx++; - } - - rv = _shiva_acl_rule_mac_parse(sw, &hw[tmp_idx], &b_care); - SW_RTN_ON_ERROR(rv); - if (A_TRUE == b_care) - { - tmp_idx++; - } - - rv = _shiva_acl_rule_ip6r1_parse(sw, &hw[tmp_idx], &b_care); - SW_RTN_ON_ERROR(rv); - if (A_TRUE == b_care) - { - tmp_idx++; - b_valid = A_TRUE; - } - - rv = _shiva_acl_rule_ip6r2_parse(sw, &hw[tmp_idx], &b_care); - SW_RTN_ON_ERROR(rv); - if (A_TRUE == b_care) - { - tmp_idx++; - b_valid = A_TRUE; - } - - rv = _shiva_acl_rule_ip6r3_parse(sw, &hw[tmp_idx], &b_care); - SW_RTN_ON_ERROR(rv); - if ((A_TRUE == b_care) || (A_FALSE == b_valid)) - { - tmp_idx++; - } - else - { - hw[tmp_idx - 1].len = hw[tmp_idx].len; - } - } - else if (FAL_ACL_RULE_UDF == sw->rule_type) - { - FAL_FIELD_FLG_SET(sw->field_flg, FAL_ACL_FIELD_UDF); - rv = _shiva_acl_rule_udf_parse(sw, &hw[tmp_idx], &b_care); - SW_RTN_ON_ERROR(rv); - tmp_idx++; - } - else - { - return SW_NOT_SUPPORTED; - } - - rv = _shiva_acl_action_parse(dev_id, sw, &(hw_rule_ent[*idx])); - SW_RTN_ON_ERROR(rv); - - *idx = tmp_idx; - return SW_OK; -} - -static sw_error_t -_shiva_acl_rule_hw_to_sw(fal_acl_rule_t * sw, const shiva_acl_hw_rule_t * hw, - a_uint32_t ent_idx, a_uint32_t ent_nr) -{ - sw_error_t rv; - a_uint32_t i, flt_typ; - a_bool_t b_mac = A_FALSE, b_ip4 = A_FALSE, b_ip6 = A_FALSE; - - rv = _shiva_acl_rule_action_reparse(sw, &hw[ent_idx]); - SW_RTN_ON_ERROR(rv); - - sw->rule_type = FAL_ACL_RULE_UDF; - for (i = 0; i < ent_nr; i++) - { - SW_GET_FIELD_BY_REG(RUL_SLCT7, RULE_TYP, flt_typ, hw[ent_idx + i].typ); - - if (SHIVA_UDF_FILTER == flt_typ) - { - rv = _shiva_acl_rule_udf_reparse(sw, &hw[ent_idx + i]); - SW_RTN_ON_ERROR(rv); - } - else if (SHIVA_MAC_FILTER == flt_typ) - { - rv = _shiva_acl_rule_mac_reparse(sw, &hw[ent_idx + i]); - SW_RTN_ON_ERROR(rv); - b_mac = A_TRUE; - } - else if (SHIVA_IP4_FILTER == flt_typ) - { - rv = _shiva_acl_rule_ip4_reparse(sw, &hw[ent_idx + i]); - SW_RTN_ON_ERROR(rv); - b_ip4 = A_TRUE; - } - else if (SHIVA_IP6R1_FILTER == flt_typ) - { - rv = _shiva_acl_rule_ip6r1_reparse(sw, &hw[ent_idx + i]); - SW_RTN_ON_ERROR(rv); - b_ip6 = A_TRUE; - } - else if (SHIVA_IP6R2_FILTER == flt_typ) - { - rv = _shiva_acl_rule_ip6r2_reparse(sw, &hw[ent_idx + i]); - SW_RTN_ON_ERROR(rv); - b_ip6 = A_TRUE; - } - else if (SHIVA_IP6R3_FILTER == flt_typ) - { - rv = _shiva_acl_rule_ip6r3_reparse(sw, &hw[ent_idx + i]); - SW_RTN_ON_ERROR(rv); - b_ip6 = A_TRUE; - } - else - { - return SW_FAIL; - } - } - - if (A_TRUE == b_mac) - { - sw->rule_type = FAL_ACL_RULE_MAC; - } - - if (A_TRUE == b_ip4) - { - sw->rule_type = FAL_ACL_RULE_IP4; - } - - if (A_TRUE == b_ip6) - { - sw->rule_type = FAL_ACL_RULE_IP6; - } - - return SW_OK; -} - -static sw_error_t -_shiva_acl_rule_copy(a_uint32_t dev_id, a_uint32_t src_slct_idx, - a_uint32_t dst_slct_idx, a_uint32_t size) -{ - sw_error_t rv; - a_uint32_t i; - a_int32_t step, src_idx, dst_idx; - shiva_acl_hw_rule_t rule; - - if (dst_slct_idx <= src_slct_idx) - { - src_idx = src_slct_idx & 0x7fffffff; - dst_idx = dst_slct_idx & 0x7fffffff; - step = 1; - } - else - { - src_idx = (src_slct_idx + size - 1) & 0x7fffffff; - dst_idx = (dst_slct_idx + size - 1) & 0x7fffffff; - step = -1; - } - - aos_mem_zero(&rule, sizeof (shiva_acl_hw_rule_t)); - for (i = 0; i < size; i++) - { - rv = _shiva_acl_rule_invalid(dev_id, (a_uint32_t) dst_idx, 1); - SW_RTN_ON_ERROR(rv); - - rv = _shiva_acl_action_read(dev_id, &rule, (a_uint32_t) src_idx); - SW_RTN_ON_ERROR(rv); - - rv = _shiva_acl_action_write(dev_id, &rule, (a_uint32_t) dst_idx); - SW_RTN_ON_ERROR(rv); - - rv = _shiva_acl_slct_read(dev_id, &rule, (a_uint32_t) src_idx); - SW_RTN_ON_ERROR(rv); - - rv = _shiva_acl_slct_write(dev_id, &rule, (a_uint32_t) dst_idx); - SW_RTN_ON_ERROR(rv); - - rv = _shiva_acl_rule_invalid(dev_id, (a_uint32_t) src_idx, 1); - SW_RTN_ON_ERROR(rv); - - src_idx += step; - dst_idx += step; - } - - return SW_OK; -} - -static sw_error_t -_shiva_acl_rule_invalid(a_uint32_t dev_id, a_uint32_t rule_idx, - a_uint32_t size) -{ - sw_error_t rv; - a_uint32_t base, flag, i; - - flag = 0; - for (i = 0; i < size; i++) - { - base = SHIVA_RULE_SLCT_ADDR + ((rule_idx + i) << 5); - HSL_REG_ENTRY_GEN_SET(rv, dev_id, base, sizeof (a_uint32_t), - (a_uint8_t *) (&flag), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - } - return SW_OK; -} - -static sw_error_t -_shiva_acl_rule_valid(a_uint32_t dev_id, a_uint32_t rule_idx, a_uint32_t size, - a_uint32_t flag) -{ - sw_error_t rv; - a_uint32_t base, i; - - for (i = 0; i < size; i++) - { - base = SHIVA_RULE_SLCT_ADDR + ((rule_idx + i) << 5); - HSL_REG_ENTRY_GEN_SET(rv, dev_id, base, sizeof (a_uint32_t), - (a_uint8_t *) (&flag), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - } - return SW_OK; -} - -static sw_error_t -_shiva_acl_addr_update(a_uint32_t dev_id, a_uint32_t old_addr, - a_uint32_t new_addr, a_uint32_t list_id) -{ - sw_error_t rv; - a_uint32_t idx; - - rv = _shiva_acl_list_loc(dev_id, list_id, &idx); - SW_RTN_ON_ERROR(rv); - - if (old_addr != list_ent[dev_id][idx].addr) - { - return SW_FAIL; - } - - list_ent[dev_id][idx].addr = new_addr; - return SW_OK; -} - -static sw_error_t -_shiva_acl_rule_bind(a_uint32_t dev_id, a_uint32_t rule_idx, a_uint32_t ports) -{ - sw_error_t rv; - shiva_acl_hw_rule_t rule; - - aos_mem_zero(&rule, sizeof (shiva_acl_hw_rule_t)); - - rv = _shiva_acl_slct_read(dev_id, &rule, rule_idx); - SW_RTN_ON_ERROR(rv); - - rv = _shiva_acl_rule_invalid(dev_id, rule_idx, 1); - SW_RTN_ON_ERROR(rv); - - SW_SET_REG_BY_FIELD(RUL_SLCT5, SRC_PT, ports, rule.slct[5]); - - rv = _shiva_acl_slct_write(dev_id, &rule, rule_idx); - SW_RTN_ON_ERROR(rv); - - rv = _shiva_acl_rule_valid(dev_id, rule_idx, 1, rule.slct[0]); - return rv; -} - -static sw_error_t -_shiva_acl_list_creat(a_uint32_t dev_id, a_uint32_t list_id, - a_uint32_t list_pri) -{ - a_uint32_t i, loc = SHIVA_MAX_LIST; - - HSL_DEV_ID_CHECK(dev_id); - - for (i = 0; i < SHIVA_MAX_LIST; i++) - { - if ((ENT_USED == list_ent[dev_id][i].status) - && (list_id == list_ent[dev_id][i].list_id)) - { - return SW_ALREADY_EXIST; - } - - if (ENT_FREE == list_ent[dev_id][i].status) - { - loc = i; - } - } - - if (SHIVA_MAX_LIST == loc) - { - return SW_NO_RESOURCE; - } - - aos_mem_zero(&(list_ent[dev_id][loc]), sizeof (shiva_acl_list_t)); - list_ent[dev_id][loc].list_id = list_id; - list_ent[dev_id][loc].list_pri = list_pri; - list_ent[dev_id][loc].status = ENT_USED; - _shiva_acl_list_dump(dev_id); - return SW_OK; -} - -static sw_error_t -_shiva_acl_list_destroy(a_uint32_t dev_id, a_uint32_t list_id) -{ - a_uint32_t list_idx; - - HSL_DEV_ID_CHECK(dev_id); - - for (list_idx = 0; list_idx < SHIVA_MAX_LIST; list_idx++) - { - if ((ENT_USED == list_ent[dev_id][list_idx].status) - && (list_id == list_ent[dev_id][list_idx].list_id)) - { - break; - } - } - - if (list_idx >= SHIVA_MAX_LIST) - { - return SW_NOT_FOUND; - } - - if (0 != list_ent[dev_id][list_idx].bind_pts) - { - return SW_NOT_SUPPORTED; - } - - if (0 != list_ent[dev_id][list_idx].size) - { - return SW_NOT_SUPPORTED; - } - - aos_mem_zero(&(list_ent[dev_id][list_idx]), sizeof (shiva_acl_list_t)); - list_ent[dev_id][list_idx].status = ENT_FREE; - _shiva_acl_list_dump(dev_id); - return SW_OK; -} - -static sw_error_t -_shiva_acl_rule_add(a_uint32_t dev_id, a_uint32_t list_id, - a_uint32_t rule_id, a_uint32_t rule_nr, - fal_acl_rule_t * rule) -{ - sw_error_t rv; - a_uint32_t hsl_f_rsc, list_new_size, list_addr; - a_uint32_t list_pri, list_idx, load_addr, bind_pts; - - HSL_DEV_ID_CHECK(dev_id); - - if ((0 == rule_nr) || (NULL == rule)) - { - return SW_BAD_PARAM; - } - - rv = hsl_acl_free_rsc_get(dev_id, &hsl_f_rsc); - SW_RTN_ON_ERROR(rv); - if (hsl_f_rsc < rule_nr) - { - return SW_NO_RESOURCE; - } - - rv = _shiva_acl_list_loc(dev_id, list_id, &list_idx); - SW_RTN_ON_ERROR(rv); - - if (rule_id != list_ent[dev_id][list_idx].size) - { - return SW_ALREADY_EXIST; - } - bind_pts = list_ent[dev_id][list_idx].bind_pts; - - _shiva_acl_filter_snap(dev_id); - - /* parse rule entry and alloc rule resource */ - { - a_uint32_t i, j; - a_uint32_t ent_idx, tmp_ent_idx, flt_idx; - - aos_mem_zero(hw_rule_ent, - SHIVA_MAX_RULE * sizeof (shiva_acl_hw_rule_t)); - - ent_idx = 0; - for (i = 0; i < rule_nr; i++) - { - tmp_ent_idx = ent_idx; - rv = _shiva_acl_rule_sw_to_hw(dev_id, &rule[i], - &hw_rule_ent[ent_idx], &ent_idx); - SW_RTN_ON_ERROR(rv); - - if (4 < (ent_idx - tmp_ent_idx)) - { - return SW_NOT_SUPPORTED; - } - - for (j = tmp_ent_idx; j < ent_idx; j++) - { - rv = _shiva_acl_filter_alloc(dev_id, &flt_idx); - SW_RTN_ON_ERROR(rv); - - rv = _shiva_acl_slct_update(&hw_rule_ent[tmp_ent_idx], - j - tmp_ent_idx, flt_idx); - SW_RTN_ON_ERROR(rv); - } - SW_SET_REG_BY_FIELD(RUL_SLCT5, SRC_PT, bind_pts, - hw_rule_ent[tmp_ent_idx].slct[5]); - } - } - - /* alloc hardware select entry resource */ - if (0 == list_ent[dev_id][list_idx].size) - { - list_new_size = rule_nr; - list_pri = list_ent[dev_id][list_idx].list_pri; - - rv = hsl_acl_blk_alloc(dev_id, list_pri, list_new_size, list_id, - &list_addr); - SW_RTN_ON_ERROR(rv); - - load_addr = list_addr; - } - else - { - list_new_size = list_ent[dev_id][list_idx].size + rule_nr; - list_addr = list_ent[dev_id][list_idx].addr; - - rv = hsl_acl_blk_resize(dev_id, list_addr, list_new_size); - SW_RTN_ON_ERROR(rv); - - /* must be careful resize opration maybe change list base address */ - list_addr = list_ent[dev_id][list_idx].addr; - load_addr = list_ent[dev_id][list_idx].size + list_addr; - } - - /* load acl rule to hardware */ - rv = _shiva_acl_rule_set(dev_id, load_addr, hw_rule_ent, rule_nr); - if (SW_OK != rv) - { - (void) hsl_acl_blk_resize(dev_id, list_addr, - list_ent[dev_id][list_idx].size); - return rv; - } - - /* update software list control information */ - list_ent[dev_id][list_idx].size = list_new_size; - list_ent[dev_id][list_idx].addr = list_addr; - - /* update hardware acl rule resource information */ - _shiva_acl_filter_commit(dev_id); - _shiva_acl_list_dump(dev_id); - return SW_OK; -} - -static sw_error_t -_shiva_acl_rule_delete(a_uint32_t dev_id, a_uint32_t list_id, - a_uint32_t rule_id, a_uint32_t rule_nr) -{ - sw_error_t rv; - a_uint32_t flt_idx[4] = {0}; - a_uint32_t i, j, flt_nr; - a_uint32_t list_idx = 0, addr, size, rule_idx, cnt; - - HSL_DEV_ID_CHECK(dev_id); - - rv = _shiva_acl_list_loc(dev_id, list_id, &list_idx); - SW_RTN_ON_ERROR(rv); - - if (0 == rule_nr) - { - return SW_BAD_PARAM; - } - - if ((rule_id + rule_nr) > list_ent[dev_id][list_idx].size) - { - return SW_NOT_FOUND; - } - - _shiva_acl_filter_snap(dev_id); - - /* free hardware filter resource */ - addr = list_ent[dev_id][list_idx].addr + rule_id; - for (i = 0; i < rule_nr; i++) - { - rv = _shiva_acl_slct_read(dev_id, &hw_rule_ent[0], i + addr); - SW_RTN_ON_ERROR(rv); - - rv = _shiva_acl_filter_map_get(&hw_rule_ent[0], flt_idx, &flt_nr); - SW_RTN_ON_ERROR(rv); - - for (j = 0; j < flt_nr; j++) - { - _shiva_acl_filter_free(dev_id, flt_idx[j]); - } - } - - cnt = list_ent[dev_id][list_idx].size - (rule_id + rule_nr); - rule_idx = list_ent[dev_id][list_idx].addr + (rule_id + rule_nr); - rv = _shiva_acl_rule_copy(dev_id, rule_idx, rule_idx - rule_nr, cnt); - SW_RTN_ON_ERROR(rv); - - addr = list_ent[dev_id][list_idx].addr; - size = list_ent[dev_id][list_idx].size; - rv = hsl_acl_blk_resize(dev_id, addr, size - rule_nr); - SW_RTN_ON_ERROR(rv); - - list_ent[dev_id][list_idx].size -= rule_nr; - _shiva_acl_filter_commit(dev_id); - _shiva_acl_list_dump(dev_id); - return SW_OK; -} - -static sw_error_t -_shiva_acl_rule_query(a_uint32_t dev_id, a_uint32_t list_id, - a_uint32_t rule_id, fal_acl_rule_t * rule) -{ - sw_error_t rv; - a_uint32_t list_idx, ent_idx, tmp_ent_idx, rule_idx; - - HSL_DEV_ID_CHECK(dev_id); - - rv = _shiva_acl_list_loc(dev_id, list_id, &list_idx); - SW_RTN_ON_ERROR(rv); - - if (rule_id >= list_ent[dev_id][list_idx].size) - { - return SW_NOT_FOUND; - } - - aos_mem_zero(rule, sizeof (fal_acl_rule_t)); - - ent_idx = 0; - tmp_ent_idx = 0; - rule_idx = list_ent[dev_id][list_idx].addr + rule_id; - rv = _shiva_acl_rule_get(dev_id, hw_rule_ent, &tmp_ent_idx, rule_idx); - SW_RTN_ON_ERROR(rv); - - rv = _shiva_acl_rule_hw_to_sw(rule, hw_rule_ent, ent_idx, - tmp_ent_idx - ent_idx); - return rv; -} - -static sw_error_t -_shiva_acl_list_bind(a_uint32_t dev_id, a_uint32_t list_id, - fal_acl_direc_t direc, fal_acl_bind_obj_t obj_t, - a_uint32_t obj_idx) -{ - sw_error_t rv; - a_uint32_t i, list_idx, rule_idx, base, ports; - - HSL_DEV_ID_CHECK(dev_id); - - if (FAL_ACL_DIREC_IN != direc) - { - return SW_NOT_SUPPORTED; - } - - if (FAL_ACL_BIND_PORT != obj_t) - { - return SW_NOT_SUPPORTED; - } - - rv = _shiva_acl_list_loc(dev_id, list_id, &list_idx); - SW_RTN_ON_ERROR(rv); - - if (list_ent[dev_id][list_idx].bind_pts & (0x1 << obj_idx)) - { - return SW_ALREADY_EXIST; - } - - base = list_ent[dev_id][list_idx].addr; - ports = list_ent[dev_id][list_idx].bind_pts | (0x1 << obj_idx); - for (i = 0; i < list_ent[dev_id][list_idx].size; i++) - { - rule_idx = base + i; - rv = _shiva_acl_rule_bind(dev_id, rule_idx, ports); - SW_RTN_ON_ERROR(rv); - } - - list_ent[dev_id][list_idx].bind_pts = ports; - return SW_OK; -} - -static sw_error_t -_shiva_acl_list_unbind(a_uint32_t dev_id, a_uint32_t list_id, - fal_acl_direc_t direc, fal_acl_bind_obj_t obj_t, - a_uint32_t obj_idx) -{ - sw_error_t rv; - a_uint32_t i, list_idx, rule_idx, base, ports; - - HSL_DEV_ID_CHECK(dev_id); - - if (FAL_ACL_DIREC_IN != direc) - { - return SW_NOT_SUPPORTED; - } - - if (FAL_ACL_BIND_PORT != obj_t) - { - return SW_NOT_SUPPORTED; - } - - rv = _shiva_acl_list_loc(dev_id, list_id, &list_idx); - SW_RTN_ON_ERROR(rv); - - if (!(list_ent[dev_id][list_idx].bind_pts & (0x1 << obj_idx))) - { - return SW_NOT_FOUND; - } - - base = list_ent[dev_id][list_idx].addr; - ports = list_ent[dev_id][list_idx].bind_pts & (~(0x1UL << obj_idx)); - for (i = 0; i < list_ent[dev_id][list_idx].size; i++) - { - rule_idx = base + i; - rv = _shiva_acl_rule_bind(dev_id, rule_idx, ports); - SW_RTN_ON_ERROR(rv); - } - - list_ent[dev_id][list_idx].bind_pts = ports; - return SW_OK; -} - -static sw_error_t -_shiva_acl_status_set(a_uint32_t dev_id, a_bool_t enable) -{ - sw_error_t rv; - a_uint32_t val; - - HSL_DEV_ID_CHECK(dev_id); - - if (A_TRUE == enable) - { - val = 1; - } - else if (A_FALSE == enable) - { - val = 0; - } - else - { - return SW_BAD_PARAM; - } - - HSL_REG_FIELD_SET(rv, dev_id, QM_CTL, 0, ACL_EN, - (a_uint8_t *) (&val), sizeof (a_uint32_t)); - return rv; -} - -static sw_error_t -_shiva_acl_status_get(a_uint32_t dev_id, a_bool_t * enable) -{ - sw_error_t rv; - a_uint32_t val = 0; - - HSL_DEV_ID_CHECK(dev_id); - - HSL_REG_FIELD_GET(rv, dev_id, QM_CTL, 0, ACL_EN, - (a_uint8_t *) (&val), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - - if (val) - { - *enable = A_TRUE; - } - else - { - *enable = A_FALSE; - } - - return SW_OK; -} - -HSL_LOCAL sw_error_t -shiva_acl_list_dump(a_uint32_t dev_id) -{ - a_uint32_t idx; - - aos_printk("\nshiva_acl_list_dump:\n"); - for (idx = 0; idx < SHIVA_MAX_LIST; idx++) - { - if (ENT_USED == list_ent[dev_id][idx].status) - { - aos_printk - ("\n[id]:%02d [pri]:%02d [size]:%02d [addr]:%02d [pts_map]:0x%02x", - list_ent[dev_id][idx].list_id, list_ent[dev_id][idx].list_pri, - list_ent[dev_id][idx].size, list_ent[dev_id][idx].addr, - list_ent[dev_id][idx].bind_pts); - } - } - aos_printk("\n"); - - return SW_OK; -} - -HSL_LOCAL sw_error_t -shiva_acl_rule_dump(a_uint32_t dev_id) -{ - a_uint32_t slt_idx, flt_nr, i, j; - a_uint32_t flt_idx[4] = {0}; - sw_error_t rv; - shiva_acl_hw_rule_t rule; - - aos_printk("\nshiva_acl_rule_dump:\n"); - - aos_printk("\nfilter_bitmap:0x%x", filter[dev_id]); - for (slt_idx = 0; slt_idx < SHIVA_MAX_RULE; slt_idx++) - { - aos_mem_zero(&rule, sizeof (shiva_acl_hw_rule_t)); - - rv = _shiva_acl_slct_read(dev_id, &rule, slt_idx); - if (SW_OK != rv) - { - continue; - } - - rv = _shiva_acl_filter_map_get(&rule, flt_idx, &flt_nr); - if (SW_OK != rv) - { - continue; - } - - aos_printk("\nslct_idx=%d ", slt_idx); - for (i = 0; i < flt_nr; i++) - { - aos_printk("flt%d_idx=%d ", i, flt_idx[i]); - } - - aos_printk("\nslt:"); - for (i = 0; i < (sizeof(rule.slct)/sizeof(a_uint32_t)); i++) - { - aos_printk("%08x ", rule.slct[i]); - } - - if (flt_nr) - { - rv = _shiva_acl_action_read(dev_id, &rule, slt_idx); - if (SW_OK != rv) - { - continue; - } - - aos_printk("\nact:"); - for (i = 0; i < (sizeof(rule.act)/sizeof(a_uint32_t)); i++) - { - aos_printk("%08x ", rule.act[i]); - } - - for (i = 0; i < flt_nr; i++) - { - rv = _shiva_acl_filter_read(dev_id, &rule, flt_idx[i]); - if (SW_OK != rv) - { - continue; - } - - aos_printk("\ntyp:%08x length:%08x", rule.typ, rule.len); - aos_printk("\nvlu:"); - for (j = 0; j < (sizeof(rule.vlu)/sizeof(a_uint32_t)); j++) - { - aos_printk("%08x ", rule.vlu[j]); - } - - aos_printk("\nmsk:"); - for (j = 0; j < (sizeof(rule.msk)/sizeof(a_uint32_t)); j++) - { - aos_printk("%08x ", rule.msk[j]); - } - aos_printk("\n"); - } - } - aos_printk("\n"); - } - - return SW_OK; -} - -sw_error_t -shiva_acl_reset(a_uint32_t dev_id) -{ - sw_error_t rv; - a_uint32_t i; - - HSL_DEV_ID_CHECK(dev_id); - - aos_mem_zero(hw_rule_ent, - (SHIVA_MAX_RULE + 3) * sizeof (shiva_acl_hw_rule_t)); - - aos_mem_zero(list_ent[dev_id], - SHIVA_MAX_LIST * sizeof (shiva_acl_list_t)); - - for (i = 0; i < SHIVA_MAX_LIST; i++) - { - list_ent[dev_id][i].status = ENT_FREE; - } - - filter[dev_id] = 0; - filter_snap[dev_id] = 0; - - rv = hsl_acl_pool_destroy(dev_id); - SW_RTN_ON_ERROR(rv); - - rv = hsl_acl_pool_creat(dev_id, SHIVA_MAX_LIST, SHIVA_MAX_RULE); - SW_RTN_ON_ERROR(rv); - - return SW_OK; -} - -/** - * @brief Creat an acl list - * @details Comments: - * If the priority of a list is more small then the priority is more high, - * that means the list could be first matched. - * @param[in] dev_id device id - * @param[in] list_id acl list id - * @param[in] list_pri acl list priority - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -shiva_acl_list_creat(a_uint32_t dev_id, a_uint32_t list_id, - a_uint32_t list_pri) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _shiva_acl_list_creat(dev_id, list_id, list_pri); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Destroy an acl list - * @param[in] dev_id device id - * @param[in] list_id acl list id - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -shiva_acl_list_destroy(a_uint32_t dev_id, a_uint32_t list_id) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _shiva_acl_list_destroy(dev_id, list_id); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Add one rule or more rules to an existing acl list - * @param[in] dev_id device id - * @param[in] list_id acl list id - * @param[in] rule_id first rule id of this adding operation in list - * @param[in] rule_nr rule number of this adding operation - * @param[in] rule rules content of this adding operation - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -shiva_acl_rule_add(a_uint32_t dev_id, a_uint32_t list_id, - a_uint32_t rule_id, a_uint32_t rule_nr, - fal_acl_rule_t * rule) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _shiva_acl_rule_add(dev_id, list_id, rule_id, rule_nr, rule); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Delete one rule or more rules from an existing acl list - * @param[in] dev_id device id - * @param[in] list_id acl list id - * @param[in] rule_id first rule id of this deleteing operation in list - * @param[in] rule_nr rule number of this deleteing operation - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -shiva_acl_rule_delete(a_uint32_t dev_id, a_uint32_t list_id, - a_uint32_t rule_id, a_uint32_t rule_nr) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _shiva_acl_rule_delete(dev_id, list_id, rule_id, rule_nr); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Query one particular rule in a particular acl list - * @param[in] dev_id device id - * @param[in] list_id acl list id - * @param[in] rule_id first rule id of this deleteing operation in list - * @param[out] rule rule content of this operation - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -shiva_acl_rule_query(a_uint32_t dev_id, a_uint32_t list_id, - a_uint32_t rule_id, fal_acl_rule_t * rule) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _shiva_acl_rule_query(dev_id, list_id, rule_id, rule); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Bind an acl list to a particular object - * @details Comments: - * If obj_t equals FAL_ACL_BIND_PORT then obj_idx means port id - * @param[in] dev_id device id - * @param[in] list_id acl list id - * @param[in] direc direction of this binding operation - * @param[in] obj_t object type of this binding operation - * @param[in] obj_idx object index of this binding operation - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -shiva_acl_list_bind(a_uint32_t dev_id, a_uint32_t list_id, - fal_acl_direc_t direc, fal_acl_bind_obj_t obj_t, - a_uint32_t obj_idx) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _shiva_acl_list_bind(dev_id, list_id, direc, obj_t, obj_idx); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Unbind an acl list from a particular object - * @details Comments: - * If obj_t equals FAL_ACL_BIND_PORT then obj_idx means port id - * @param[in] dev_id device id - * @param[in] list_id acl list id - * @param[in] direc direction of this unbinding operation - * @param[in] obj_t object type of this unbinding operation - * @param[in] obj_idx object index of this unbinding operation - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -shiva_acl_list_unbind(a_uint32_t dev_id, a_uint32_t list_id, - fal_acl_direc_t direc, fal_acl_bind_obj_t obj_t, - a_uint32_t obj_idx) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _shiva_acl_list_unbind(dev_id, list_id, direc, obj_t, obj_idx); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Set working status of ACL engine on a particular device - * @param[in] dev_id device id - * @param[in] enable A_TRUE or A_FALSE - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -shiva_acl_status_set(a_uint32_t dev_id, a_bool_t enable) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _shiva_acl_status_set(dev_id, enable); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Get working status of ACL engine on a particular device - * @param[in] dev_id device id - * @param[out] enable A_TRUE or A_FALSE - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -shiva_acl_status_get(a_uint32_t dev_id, a_bool_t * enable) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _shiva_acl_status_get(dev_id, enable); - HSL_API_UNLOCK; - return rv; -} - -sw_error_t -shiva_acl_init(a_uint32_t dev_id) -{ - static a_bool_t b_hw_rule = A_FALSE; - hsl_acl_func_t *acl_func; - shiva_acl_hw_rule_t rule; - sw_error_t rv; - a_uint32_t i; - - HSL_DEV_ID_CHECK(dev_id); - - if (A_FALSE == b_hw_rule) - { - hw_rule_ent = (shiva_acl_hw_rule_t *) - aos_mem_alloc((SHIVA_MAX_RULE + - 3) * sizeof (shiva_acl_hw_rule_t)); - if (NULL == hw_rule_ent) - { - return SW_NO_RESOURCE; - } - aos_mem_zero(hw_rule_ent, - (SHIVA_MAX_RULE + 3) * sizeof (shiva_acl_hw_rule_t)); - b_hw_rule = A_TRUE; - } - - list_ent[dev_id] = (shiva_acl_list_t *) - aos_mem_alloc(SHIVA_MAX_LIST * sizeof (shiva_acl_list_t)); - if (NULL == list_ent[dev_id]) - { - return SW_NO_RESOURCE; - } - aos_mem_zero(list_ent[dev_id], - SHIVA_MAX_LIST * sizeof (shiva_acl_list_t)); - - for (i = 0; i < SHIVA_MAX_LIST; i++) - { - list_ent[dev_id][i].status = ENT_FREE; - } - - filter[dev_id] = 0; - filter_snap[dev_id] = 0; - - rv = hsl_acl_pool_creat(dev_id, SHIVA_MAX_LIST, SHIVA_MAX_RULE); - SW_RTN_ON_ERROR(rv); - - acl_func = hsl_acl_ptr_get(dev_id); - SW_RTN_ON_NULL(acl_func); - - acl_func->acl_rule_copy = _shiva_acl_rule_copy; - acl_func->acl_rule_invalid = _shiva_acl_rule_invalid; - acl_func->acl_addr_update = _shiva_acl_addr_update; - - /* zero acl hardware memory */ - aos_mem_zero(&rule, sizeof (shiva_acl_hw_rule_t)); - for (i = 0; i < SHIVA_MAX_RULE; i++) - { - rv = _shiva_acl_slct_write(dev_id, &rule, i); - SW_RTN_ON_ERROR(rv); - } - -#ifdef SHIVA_SW_ENTRY - flt_vlu_mem = aos_mem_alloc(SHIVA_MAX_RULE * 32); - if (NULL == flt_vlu_mem) - { - return SW_NO_RESOURCE; - } - aos_mem_zero(flt_vlu_mem, SHIVA_MAX_RULE * 32); - - flt_msk_mem = aos_mem_alloc(SHIVA_MAX_RULE * 32); - if (NULL == flt_msk_mem) - { - return SW_NO_RESOURCE; - } - aos_mem_zero(flt_msk_mem, SHIVA_MAX_RULE * 32); - - flt_typ_mem = aos_mem_alloc(SHIVA_MAX_RULE * 4); - if (NULL == flt_typ_mem) - { - return SW_NO_RESOURCE; - } - aos_mem_zero(flt_typ_mem, SHIVA_MAX_RULE * 4); - - flt_len_mem = aos_mem_alloc(SHIVA_MAX_RULE * 4); - if (NULL == flt_len_mem) - { - return SW_NO_RESOURCE; - } - aos_mem_zero(flt_len_mem, SHIVA_MAX_RULE * 4); - - act_mem = aos_mem_alloc(SHIVA_MAX_RULE * 32); - if (NULL == act_mem) - { - return SW_NO_RESOURCE; - } - aos_mem_zero(act_mem, SHIVA_MAX_RULE * 32); - - slct_mem = aos_mem_alloc(SHIVA_MAX_RULE * 32); - if (NULL == slct_mem) - { - return SW_NO_RESOURCE; - } - aos_mem_zero(slct_mem, SHIVA_MAX_RULE * 32); -#endif - -#ifndef HSL_STANDALONG - { - hsl_api_t *p_api; - - SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id)); - - p_api->acl_list_creat = shiva_acl_list_creat; - p_api->acl_list_destroy = shiva_acl_list_destroy; - p_api->acl_list_bind = shiva_acl_list_bind; - p_api->acl_list_unbind = shiva_acl_list_unbind; - p_api->acl_rule_add = shiva_acl_rule_add; - p_api->acl_rule_delete = shiva_acl_rule_delete; - p_api->acl_rule_query = shiva_acl_rule_query; - p_api->acl_status_set = shiva_acl_status_set; - p_api->acl_status_get = shiva_acl_status_get; - p_api->acl_list_dump = shiva_acl_list_dump; - p_api->acl_rule_dump = shiva_acl_rule_dump; - } -#endif - - return SW_OK; -} - -/** - * @} - */ - diff --git a/feeds/ipq807x/qca-ssdk/src/src/hsl/shiva/shiva_fdb.c b/feeds/ipq807x/qca-ssdk/src/src/hsl/shiva/shiva_fdb.c deleted file mode 100755 index 5bc43b0fb..000000000 --- a/feeds/ipq807x/qca-ssdk/src/src/hsl/shiva/shiva_fdb.c +++ /dev/null @@ -1,1135 +0,0 @@ -/* - * Copyright (c) 2012, 2016, The Linux Foundation. All rights reserved. - * Permission to use, copy, modify, and/or distribute this software for - * any purpose with or without fee is hereby granted, provided that the - * above copyright notice and this permission notice appear in all copies. - * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES - * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR - * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES - * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN - * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT - * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. - */ - - -/** - * @defgroup shiva_fdb SHIVA_FDB - * @{ - */ -#include "sw.h" -#include "hsl.h" -#include "hsl_dev.h" -#include "hsl_port_prop.h" -#include "shiva_fdb.h" -#include "shiva_reg.h" - -#define ARL_FLUSH_ALL 1 -#define ARL_LOAD_ENTRY 2 -#define ARL_PURGE_ENTRY 3 -#define ARL_FLUSH_ALL_UNLOCK 4 -#define ARL_FLUSH_PORT_UNICAST 5 -#define ARL_NEXT_ENTRY 6 -#define ARL_FIND_ENTRY 7 - -#define ARL_FIRST_ENTRY 1001 -#define ARL_FLUSH_PORT_NO_STATIC 1002 -#define ARL_FLUSH_PORT_AND_STATIC 1003 - -static a_bool_t -shiva_fdb_is_zeroaddr(fal_mac_addr_t addr) -{ - a_uint32_t i; - - for (i = 0; i < 6; i++) - { - if (addr.uc[i]) - { - return A_FALSE; - } - } - - return A_TRUE; -} - -static void -shiva_fdb_fill_addr(fal_mac_addr_t addr, a_uint32_t * reg0, a_uint32_t * reg1) -{ - SW_SET_REG_BY_FIELD(ADDR_TABLE_FUNC1, AT_ADDR_BYTE0, addr.uc[0], *reg1); - SW_SET_REG_BY_FIELD(ADDR_TABLE_FUNC1, AT_ADDR_BYTE1, addr.uc[1], *reg1); - SW_SET_REG_BY_FIELD(ADDR_TABLE_FUNC1, AT_ADDR_BYTE2, addr.uc[2], *reg1); - SW_SET_REG_BY_FIELD(ADDR_TABLE_FUNC1, AT_ADDR_BYTE3, addr.uc[3], *reg1); - - SW_SET_REG_BY_FIELD(ADDR_TABLE_FUNC0, AT_ADDR_BYTE4, addr.uc[4], *reg0); - SW_SET_REG_BY_FIELD(ADDR_TABLE_FUNC0, AT_ADDR_BYTE5, addr.uc[5], *reg0); - - return; -} - -static sw_error_t -shiva_atu_sw_to_hw(a_uint32_t dev_id, const fal_fdb_entry_t * entry, - a_uint32_t reg[]) -{ - a_uint32_t port; - - if (A_FALSE == entry->portmap_en) - { - if (A_TRUE != - hsl_port_prop_check(dev_id, entry->port.id, HSL_PP_INCL_CPU)) - { - return SW_BAD_PARAM; - } - - port = 0x1UL << entry->port.id; - } - else - { - if (A_FALSE == - hsl_mports_prop_check(dev_id, entry->port.map, HSL_PP_INCL_CPU)) - { - return SW_BAD_PARAM; - } - - port = entry->port.map; - } - - if (FAL_MAC_CPY_TO_CPU == entry->dacmd) - { - SW_SET_REG_BY_FIELD(ADDR_TABLE_FUNC2, COPY_TO_CPU, 1, reg[2]); - } - else if (FAL_MAC_RDT_TO_CPU == entry->dacmd) - { - SW_SET_REG_BY_FIELD(ADDR_TABLE_FUNC2, REDRCT_TO_CPU, 1, reg[2]); - } - else if (FAL_MAC_FRWRD != entry->dacmd) - { - return SW_NOT_SUPPORTED; - } - - if (FAL_MAC_DROP == entry->sacmd) - { - SW_SET_REG_BY_FIELD(ADDR_TABLE_FUNC2, SA_DROP_EN, 1, reg[2]); - } - else if (FAL_MAC_FRWRD != entry->sacmd) - { - return SW_NOT_SUPPORTED; - } - - if (A_TRUE == entry->leaky_en) - { - SW_SET_REG_BY_FIELD(ADDR_TABLE_FUNC2, LEAKY_EN, 1, reg[2]); - } - else - { - SW_SET_REG_BY_FIELD(ADDR_TABLE_FUNC2, LEAKY_EN, 0, reg[2]); - } - - if (A_TRUE == entry->static_en) - { - SW_SET_REG_BY_FIELD(ADDR_TABLE_FUNC2, AT_STATUS, 15, reg[2]); - } - else - { - SW_SET_REG_BY_FIELD(ADDR_TABLE_FUNC2, AT_STATUS, 7, reg[2]); - } - - if (A_TRUE == entry->mirror_en) - { - SW_SET_REG_BY_FIELD(ADDR_TABLE_FUNC2, MIRROR_EN, 1, reg[2]); - } - - if (A_TRUE == entry->clone_en) - { - SW_SET_REG_BY_FIELD(ADDR_TABLE_FUNC2, CLONE_EN, 1, reg[2]); - } - - if (A_TRUE == entry->cross_pt_state) - { - SW_SET_REG_BY_FIELD(ADDR_TABLE_FUNC2, CROSS_PT, 1, reg[2]); - } - - if (A_TRUE == entry->da_pri_en) - { - hsl_dev_t *p_dev; - - SW_SET_REG_BY_FIELD(ADDR_TABLE_FUNC2, AT_PRI_EN, 1, reg[2]); - - SW_RTN_ON_NULL(p_dev = hsl_dev_ptr_get(dev_id)); - - if (entry->da_queue > (p_dev->nr_queue - 1)) - return SW_BAD_PARAM; - - SW_SET_REG_BY_FIELD(ADDR_TABLE_FUNC2, AT_PRI, entry->da_queue, reg[2]); - } - - SW_SET_REG_BY_FIELD(ADDR_TABLE_FUNC2, DES_PORT, port, reg[2]); - shiva_fdb_fill_addr(entry->addr, ®[0], ®[1]); - - return SW_OK; -} - -static void -shiva_atu_hw_to_sw(const a_uint32_t reg[], fal_fdb_entry_t * entry) -{ - a_uint32_t i, data; - - aos_mem_zero(entry, sizeof (fal_fdb_entry_t)); - - entry->dacmd = FAL_MAC_FRWRD; - SW_GET_FIELD_BY_REG(ADDR_TABLE_FUNC2, COPY_TO_CPU, data, reg[2]); - if (1 == data) - { - entry->dacmd = FAL_MAC_CPY_TO_CPU; - } - - SW_GET_FIELD_BY_REG(ADDR_TABLE_FUNC2, REDRCT_TO_CPU, data, reg[2]); - if (1 == data) - { - entry->dacmd = FAL_MAC_RDT_TO_CPU; - } - - entry->sacmd = FAL_MAC_FRWRD; - SW_GET_FIELD_BY_REG(ADDR_TABLE_FUNC2, SA_DROP_EN, data, reg[2]); - if (1 == data) - { - entry->sacmd = FAL_MAC_DROP; - } - - entry->leaky_en = A_FALSE; - SW_GET_FIELD_BY_REG(ADDR_TABLE_FUNC2, LEAKY_EN, data, reg[2]); - if (1 == data) - { - entry->leaky_en = A_TRUE; - } - - entry->static_en = A_FALSE; - SW_GET_FIELD_BY_REG(ADDR_TABLE_FUNC2, AT_STATUS, data, reg[2]); - if (0xf == data) - { - entry->static_en = A_TRUE; - } - - entry->mirror_en = A_FALSE; - SW_GET_FIELD_BY_REG(ADDR_TABLE_FUNC2, MIRROR_EN, data, reg[2]); - if (1 == data) - { - entry->mirror_en = A_TRUE; - } - - entry->clone_en = A_FALSE; - SW_GET_FIELD_BY_REG(ADDR_TABLE_FUNC2, CLONE_EN, data, reg[2]); - if (1 == data) - { - entry->clone_en = A_TRUE; - } - - entry->da_pri_en = A_FALSE; - SW_GET_FIELD_BY_REG(ADDR_TABLE_FUNC2, AT_PRI_EN, data, reg[2]); - if (1 == data) - { - SW_GET_FIELD_BY_REG(ADDR_TABLE_FUNC2, AT_PRI, data, reg[2]); - entry->da_pri_en = A_TRUE; - entry->da_queue = data & 0x3; - } - - entry->cross_pt_state = A_FALSE; - SW_GET_FIELD_BY_REG(ADDR_TABLE_FUNC2, CROSS_PT, data, reg[2]); - if (1 == data) - { - entry->cross_pt_state = A_TRUE; - } - - SW_GET_FIELD_BY_REG(ADDR_TABLE_FUNC2, DES_PORT, data, reg[2]); - - entry->portmap_en = A_TRUE; - entry->port.map = data; - - for (i = 0; i < 4; i++) - { - entry->addr.uc[i] = (reg[1] >> ((3 - i) << 3)) & 0xff; - } - - for (i = 4; i < 6; i++) - { - entry->addr.uc[i] = (reg[0] >> ((7 - i) << 3)) & 0xff; - } - - return; -} - -static sw_error_t -shiva_fdb_commit(a_uint32_t dev_id, a_uint32_t op) -{ - sw_error_t rv; - a_uint32_t busy = 1; - a_uint32_t full_vio; - a_uint32_t i = 1000; - a_uint32_t entry; - a_uint32_t hwop = op; - - while (busy && --i) - { - HSL_REG_FIELD_GET(rv, dev_id, ADDR_TABLE_FUNC0, 0, AT_BUSY, - (a_uint8_t *) (&busy), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - aos_udelay(5); - } - - if (0 == i) - { - return SW_BUSY; - } - - HSL_REG_ENTRY_GET(rv, dev_id, ADDR_TABLE_FUNC0, 0, - (a_uint8_t *) (&entry), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - - SW_SET_REG_BY_FIELD(ADDR_TABLE_FUNC0, AT_BUSY, 1, entry); - - if (ARL_FLUSH_PORT_AND_STATIC == hwop) - { - hwop = ARL_FLUSH_PORT_UNICAST; - SW_SET_REG_BY_FIELD(ADDR_TABLE_FUNC0, FLUSH_ST_EN, 1, entry); - } - - if (ARL_FLUSH_PORT_NO_STATIC == hwop) - { - hwop = ARL_FLUSH_PORT_UNICAST; - SW_SET_REG_BY_FIELD(ADDR_TABLE_FUNC0, FLUSH_ST_EN, 0, entry); - } - - SW_SET_REG_BY_FIELD(ADDR_TABLE_FUNC0, AT_FUNC, hwop, entry); - - HSL_REG_ENTRY_SET(rv, dev_id, ADDR_TABLE_FUNC0, 0, - (a_uint8_t *) (&entry), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - - busy = 1; - i = 1000; - while (busy && --i) - { - HSL_REG_FIELD_GET(rv, dev_id, ADDR_TABLE_FUNC0, 0, AT_BUSY, - (a_uint8_t *) (&busy), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - aos_udelay(5); - } - - if (0 == i) - { - return SW_FAIL; - } - - HSL_REG_FIELD_GET(rv, dev_id, ADDR_TABLE_FUNC0, 0, AT_FULL_VIO, - (a_uint8_t *) (&full_vio), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - - if (full_vio) - { - /* must clear AT_FULL_VOI bit */ - entry = 0x1000; - HSL_REG_ENTRY_SET(rv, dev_id, ADDR_TABLE_FUNC0, 0, - (a_uint8_t *) (&entry), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - - if (ARL_LOAD_ENTRY == hwop) - { - return SW_FULL; - } - else if ((ARL_PURGE_ENTRY == hwop) - || (ARL_FLUSH_PORT_UNICAST == hwop)) - { - return SW_NOT_FOUND; - } - else - { - return SW_FAIL; - } - } - - return SW_OK; -} - -static sw_error_t -shiva_atu_get(a_uint32_t dev_id, fal_fdb_entry_t * entry, a_uint32_t op) -{ - sw_error_t rv; - a_uint32_t reg[3] = { 0 }; - a_uint32_t status = 0; - a_uint32_t hwop = op; - - if ((ARL_NEXT_ENTRY == op) - || (ARL_FIND_ENTRY == op)) - { - shiva_fdb_fill_addr(entry->addr, ®[0], ®[1]); - } - - HSL_REG_ENTRY_SET(rv, dev_id, ADDR_TABLE_FUNC0, 0, - (a_uint8_t *) (®[0]), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - - HSL_REG_ENTRY_SET(rv, dev_id, ADDR_TABLE_FUNC1, 0, - (a_uint8_t *) (®[1]), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - - /* set status not zero */ - if (ARL_NEXT_ENTRY == op) - { - reg[2] = 0xf0000; - } - - if (ARL_FIRST_ENTRY == op) - { - hwop = ARL_NEXT_ENTRY; - } - - HSL_REG_ENTRY_SET(rv, dev_id, ADDR_TABLE_FUNC2, 0, - (a_uint8_t *) (®[2]), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - - rv = shiva_fdb_commit(dev_id, hwop); - SW_RTN_ON_ERROR(rv); - - /* get hardware enrety */ - HSL_REG_ENTRY_GET(rv, dev_id, ADDR_TABLE_FUNC0, 0, - (a_uint8_t *) (®[0]), sizeof (a_uint32_t)); - - SW_RTN_ON_ERROR(rv); - - HSL_REG_ENTRY_GET(rv, dev_id, ADDR_TABLE_FUNC1, 0, - (a_uint8_t *) (®[1]), sizeof (a_uint32_t)); - - SW_RTN_ON_ERROR(rv); - - HSL_REG_ENTRY_GET(rv, dev_id, ADDR_TABLE_FUNC2, 0, - (a_uint8_t *) (®[2]), sizeof (a_uint32_t)); - - SW_RTN_ON_ERROR(rv); - - SW_GET_FIELD_BY_REG(ADDR_TABLE_FUNC2, AT_STATUS, status, reg[2]); - - shiva_atu_hw_to_sw(reg, entry); - - /* If hardware return back with address and status all zero, - that means no other next valid entry in fdb table */ - if ((A_TRUE == shiva_fdb_is_zeroaddr(entry->addr)) - && (0 == status)) - { - if (ARL_NEXT_ENTRY == op) - { - return SW_NO_MORE; - } - else if ((ARL_FIND_ENTRY == op) - || (ARL_FIRST_ENTRY == op)) - { - return SW_NOT_FOUND; - } - else - { - return SW_FAIL; - } - } - else - { - return SW_OK; - } -} - -static sw_error_t -_shiva_fdb_add(a_uint32_t dev_id, const fal_fdb_entry_t * entry) -{ - sw_error_t rv; - a_uint32_t reg[3] = { 0, 0, 0 }; - - HSL_DEV_ID_CHECK(dev_id); - - rv = shiva_atu_sw_to_hw(dev_id, entry, reg); - SW_RTN_ON_ERROR(rv); - - HSL_REG_ENTRY_SET(rv, dev_id, ADDR_TABLE_FUNC2, 0, - (a_uint8_t *) (®[2]), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - - HSL_REG_ENTRY_SET(rv, dev_id, ADDR_TABLE_FUNC1, 0, (a_uint8_t *) (®[1]), - sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - - HSL_REG_ENTRY_SET(rv, dev_id, ADDR_TABLE_FUNC0, 0, (a_uint8_t *) (®[0]), - sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - - rv = shiva_fdb_commit(dev_id, ARL_LOAD_ENTRY); - - return rv; -} - -static sw_error_t -_shiva_fdb_del_all(a_uint32_t dev_id, a_uint32_t flag) -{ - sw_error_t rv; - - HSL_DEV_ID_CHECK(dev_id); - - if (FAL_FDB_DEL_STATIC & flag) - { - rv = shiva_fdb_commit(dev_id, ARL_FLUSH_ALL); - } - else - { - rv = shiva_fdb_commit(dev_id, ARL_FLUSH_ALL_UNLOCK); - } - - return rv; -} - -static sw_error_t -_shiva_fdb_del_by_port(a_uint32_t dev_id, fal_port_t port_id, a_uint32_t flag) -{ - sw_error_t rv; - a_uint32_t reg = 0; - - HSL_DEV_ID_CHECK(dev_id); - - if (A_FALSE == hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU)) - { - return SW_BAD_PARAM; - } - - SW_SET_REG_BY_FIELD(ADDR_TABLE_FUNC0, AT_PORT_NUM, port_id, reg); - - HSL_REG_ENTRY_SET(rv, dev_id, ADDR_TABLE_FUNC0, 0, (a_uint8_t *) (®), - sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - - if (FAL_FDB_DEL_STATIC & flag) - { - rv = shiva_fdb_commit(dev_id, ARL_FLUSH_PORT_AND_STATIC); - } - else - { - rv = shiva_fdb_commit(dev_id, ARL_FLUSH_PORT_NO_STATIC); - } - - return rv; -} - -static sw_error_t -_shiva_fdb_del_by_mac(a_uint32_t dev_id, const fal_fdb_entry_t * entry) -{ - sw_error_t rv; - a_uint32_t reg0 = 0, reg1 = 0; - - HSL_DEV_ID_CHECK(dev_id); - - shiva_fdb_fill_addr(entry->addr, ®0, ®1); - - HSL_REG_ENTRY_SET(rv, dev_id, ADDR_TABLE_FUNC1, 0, (a_uint8_t *) (®1), - sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - - HSL_REG_ENTRY_SET(rv, dev_id, ADDR_TABLE_FUNC0, 0, (a_uint8_t *) (®0), - sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - - rv = shiva_fdb_commit(dev_id, ARL_PURGE_ENTRY); - return rv; -} - -static sw_error_t -_shiva_fdb_first(a_uint32_t dev_id, fal_fdb_entry_t * entry) -{ - sw_error_t rv; - - HSL_DEV_ID_CHECK(dev_id); - - rv = shiva_atu_get(dev_id, entry, ARL_FIRST_ENTRY); - return rv; -} - -static sw_error_t -_shiva_fdb_find(a_uint32_t dev_id, fal_fdb_entry_t * entry) -{ - sw_error_t rv; - - HSL_DEV_ID_CHECK(dev_id); - - rv = shiva_atu_get(dev_id, entry, ARL_FIND_ENTRY); - return rv; -} - -static sw_error_t -_shiva_fdb_port_learn_set(a_uint32_t dev_id, fal_port_t port_id, - a_bool_t enable) -{ - a_uint32_t data; - sw_error_t rv; - - HSL_DEV_ID_CHECK(dev_id); - - if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU)) - { - return SW_BAD_PARAM; - } - - if (A_TRUE == enable) - { - data = 1; - } - else if (A_FALSE == enable) - { - data = 0; - } - else - { - return SW_BAD_PARAM; - } - - HSL_REG_FIELD_SET(rv, dev_id, PORT_CTL, port_id, LEARN_EN, - (a_uint8_t *) (&data), sizeof (a_uint32_t)); - return rv; -} - -static sw_error_t -_shiva_fdb_port_learn_get(a_uint32_t dev_id, fal_port_t port_id, - a_bool_t *enable) -{ - a_uint32_t data = 0; - sw_error_t rv; - - HSL_DEV_ID_CHECK(dev_id); - - if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU)) - { - return SW_BAD_PARAM; - } - - HSL_REG_FIELD_GET(rv, dev_id, PORT_CTL, port_id, LEARN_EN, - (a_uint8_t *) (&data), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - - if (1 == data) - { - *enable = A_TRUE; - } - else - { - *enable = A_FALSE; - } - - return SW_OK; -} - -static sw_error_t -_shiva_fdb_age_ctrl_set(a_uint32_t dev_id, a_bool_t enable) -{ - a_uint32_t data; - sw_error_t rv; - - HSL_DEV_ID_CHECK(dev_id); - - if (A_TRUE == enable) - { - data = 1; - } - else if (A_FALSE == enable) - { - data = 0; - } - else - { - return SW_BAD_PARAM; - } - - HSL_REG_FIELD_SET(rv, dev_id, ADDR_TABLE_CTL, 0, AGE_EN, - (a_uint8_t *) (&data), sizeof (a_uint32_t)); - return rv; -} - -static sw_error_t -_shiva_fdb_age_ctrl_get(a_uint32_t dev_id, a_bool_t *enable) -{ - a_uint32_t data = 0; - sw_error_t rv; - - HSL_DEV_ID_CHECK(dev_id); - - HSL_REG_FIELD_GET(rv, dev_id, ADDR_TABLE_CTL, 0, AGE_EN, - (a_uint8_t *) (&data), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - - if (1 == data) - { - *enable = A_TRUE; - } - else - { - *enable = A_FALSE; - } - - return SW_OK; -} - -static sw_error_t -_shiva_fdb_age_time_set(a_uint32_t dev_id, a_uint32_t * time) -{ - a_uint32_t data; - sw_error_t rv; - - HSL_DEV_ID_CHECK(dev_id); - - if ((65535 * 7 < *time) || (7 > *time)) - { - return SW_BAD_PARAM; - } - data = *time / 7; - *time = data * 7; - HSL_REG_FIELD_SET(rv, dev_id, ADDR_TABLE_CTL, 0, AGE_TIME, - (a_uint8_t *) (&data), sizeof (a_uint32_t)); - return rv; -} - -static sw_error_t -_shiva_fdb_age_time_get(a_uint32_t dev_id, a_uint32_t *time) -{ - a_uint32_t data = 0; - sw_error_t rv; - - HSL_DEV_ID_CHECK(dev_id); - - HSL_REG_FIELD_GET(rv, dev_id, ADDR_TABLE_CTL, 0, AGE_TIME, - (a_uint8_t *) (&data), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - - *time = data * 7; - return SW_OK; -} - -static void -_shiva_fdb_hw_to_sw(a_uint32_t tbl[3], fal_fdb_entry_t * entry) -{ - a_uint32_t i, data; - - aos_mem_zero(entry, sizeof (fal_fdb_entry_t)); - - entry->dacmd = FAL_MAC_FRWRD; - SW_GET_FIELD_BY_REG(FDB_TABLE_FUNC2, FDB_CPYCPU_EN, data, tbl[2]); - if (1 == data) - { - entry->dacmd = FAL_MAC_CPY_TO_CPU; - } - - SW_GET_FIELD_BY_REG(FDB_TABLE_FUNC2, FDB_RDTCPU_EN, data, tbl[2]); - if (1 == data) - { - entry->dacmd = FAL_MAC_RDT_TO_CPU; - } - - entry->leaky_en = A_FALSE; - SW_GET_FIELD_BY_REG(FDB_TABLE_FUNC2, FDB_LEANKY_EN, data, tbl[2]); - if (1 == data) - { - entry->leaky_en = A_TRUE; - } - - entry->static_en = A_FALSE; - SW_GET_FIELD_BY_REG(FDB_TABLE_FUNC2, FDB_STATUS, data, tbl[2]); - if (0xf == data) - { - entry->static_en = A_TRUE; - } - - entry->clone_en = A_FALSE; - SW_GET_FIELD_BY_REG(FDB_TABLE_FUNC1, FDB_MACCLONE_EN, data, tbl[1]); - if (1 == data) - { - entry->clone_en = A_TRUE; - } - - entry->sacmd = FAL_MAC_FRWRD; - SW_GET_FIELD_BY_REG(FDB_TABLE_FUNC1, FDB_SADROP_EN, data, tbl[1]); - if (1 == data) - { - entry->sacmd = FAL_MAC_DROP; - } - - entry->mirror_en = A_FALSE; - SW_GET_FIELD_BY_REG(FDB_TABLE_FUNC1, FDB_MIRROR_EN, data, tbl[1]); - if (1 == data) - { - entry->mirror_en = A_TRUE; - } - - entry->da_pri_en = A_FALSE; - SW_GET_FIELD_BY_REG(FDB_TABLE_FUNC1, FDB_PRIORITY_EN, data, tbl[1]); - if (1 == data) - { - SW_GET_FIELD_BY_REG(FDB_TABLE_FUNC1, FDB_PRIORITY, data, tbl[1]); - entry->da_pri_en = A_TRUE; - entry->da_queue = data & 0x3; - } - - entry->cross_pt_state = A_FALSE; - SW_GET_FIELD_BY_REG(FDB_TABLE_FUNC1, FDB_CROSS_STATE, data, tbl[1]); - if (1 == data) - { - entry->cross_pt_state = A_TRUE; - } - - SW_GET_FIELD_BY_REG(FDB_TABLE_FUNC1, FDB_DES_PORT, data, tbl[1]); - entry->portmap_en = A_TRUE; - entry->port.map = data; - - for (i = 2; i < 6; i++) - { - entry->addr.uc[i] = (tbl[0] >> ((5 - i) << 3)) & 0xff; - } - - for (i = 0; i < 2; i++) - { - entry->addr.uc[i] = (tbl[1] >> ((1 - i) << 3)) & 0xff; - } -} - -#define SHIVA_FDB_ENTRY_NUM 1024 -#define SHIVA_FDB_ENTRY_ADDR0 0x30000 -#define SHIVA_FDB_ENTRY_ADDR1 0x30004 -#define SHIVA_FDB_ENTRY_ADDR2 0x30008 - -static sw_error_t -_shiva_fdb_iterate(a_uint32_t dev_id, a_uint32_t * iterator, fal_fdb_entry_t * entry) -{ - a_uint32_t index, addr, data, tbl[3] = { 0 }; - sw_error_t rv; - - if ((NULL == iterator) || (NULL == entry)) - { - return SW_BAD_PTR; - } - - if (SHIVA_FDB_ENTRY_NUM == *iterator) - { - return SW_NO_MORE; - } - - if (SHIVA_FDB_ENTRY_NUM < *iterator) - { - return SW_BAD_PARAM; - } - - for (index = *iterator; index < SHIVA_FDB_ENTRY_NUM; index++) - { - addr = SHIVA_FDB_ENTRY_ADDR2 + (index << 4); - HSL_REG_ENTRY_GEN_GET(rv, dev_id, addr, sizeof (a_uint32_t), - (a_uint8_t *) (&(tbl[2])), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - - SW_GET_FIELD_BY_REG(FDB_TABLE_FUNC2, FDB_STATUS, data, tbl[2]); - if (data) - { - addr = SHIVA_FDB_ENTRY_ADDR0 + (index << 4); - HSL_REG_ENTRY_GEN_GET(rv, dev_id, addr, sizeof (a_uint32_t), - (a_uint8_t *) (&(tbl[0])), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - - addr = SHIVA_FDB_ENTRY_ADDR1 + (index << 4); - HSL_REG_ENTRY_GEN_GET(rv, dev_id, addr, sizeof (a_uint32_t), - (a_uint8_t *) (&(tbl[1])), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - - _shiva_fdb_hw_to_sw(tbl, entry); - break; - } - } - - if (SHIVA_FDB_ENTRY_NUM == index) - { - return SW_NO_MORE; - } - - *iterator = index + 1; - return SW_OK; -} - -/** - * @brief Add a Fdb entry - * @param[in] dev_id device id - * @param[in] entry fdb entry - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -shiva_fdb_add(a_uint32_t dev_id, const fal_fdb_entry_t * entry) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _shiva_fdb_add(dev_id, entry); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Delete all Fdb entries - * @details Comments: - * If set FAL_FDB_DEL_STATIC bit in flag which means delete all fdb - * entries otherwise only delete dynamic entries. - * @param[in] dev_id device id - * @param[in] flag delete operation option - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -shiva_fdb_del_all(a_uint32_t dev_id, a_uint32_t flag) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _shiva_fdb_del_all(dev_id, flag); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Delete Fdb entries on a particular port - * @details Comments: - * If set FAL_FDB_DEL_STATIC bit in flag which means delete all fdb - * entries otherwise only delete dynamic entries. - * @param[in] dev_id device id - * @param[in] port_id port id - * @param[in] flag delete operation option - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -shiva_fdb_del_by_port(a_uint32_t dev_id, fal_port_t port_id, a_uint32_t flag) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _shiva_fdb_del_by_port(dev_id, port_id, flag); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Delete a particular Fdb entry through mac address - * @details Comments: - * Only addr field in entry is meaning. For IVL learning vid or fid field - * also is meaning. - * @param[in] dev_id device id - * @param[in] entry fdb entry - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -shiva_fdb_del_by_mac(a_uint32_t dev_id, const fal_fdb_entry_t * entry) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _shiva_fdb_del_by_mac(dev_id, entry); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Get first Fdb entry from particular device - * @param[in] dev_id device id - * @param[out] entry fdb entry - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -shiva_fdb_first(a_uint32_t dev_id, fal_fdb_entry_t * entry) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _shiva_fdb_first(dev_id, entry); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Find a particular Fdb entry from device through mac address. - * @details Comments: - For input parameter only addr field in entry is meaning. - * @param[in] dev_id device id - * @param[in] entry fdb entry - * @param[out] entry fdb entry - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -shiva_fdb_find(a_uint32_t dev_id, fal_fdb_entry_t * entry) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _shiva_fdb_find(dev_id, entry); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Set dynamic address learning status on a particular port. - * @details Comments: - * This operation will enable or disable dynamic address learning - * feature on a particular port. - * @param[in] dev_id device id - * @param[in] port_id port id - * @param[in] enable enable or disable - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -shiva_fdb_port_learn_set(a_uint32_t dev_id, fal_port_t port_id, - a_bool_t enable) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _shiva_fdb_port_learn_set(dev_id, port_id, enable); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Get dynamic address learning status on a particular port. - * @param[in] dev_id device id - * @param[in] port_id port id - * @param[out] enable A_TRUE or A_FALSE - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -shiva_fdb_port_learn_get(a_uint32_t dev_id, fal_port_t port_id, - a_bool_t *enable) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _shiva_fdb_port_learn_get(dev_id, port_id, enable); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Set dynamic address aging status on particular device. - * @details Comments: - * This operation will enable or disable dynamic address aging - * feature on particular device. - * @param[in] dev_id device id - * @param[in] enable enable or disable - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -shiva_fdb_age_ctrl_set(a_uint32_t dev_id, a_bool_t enable) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _shiva_fdb_age_ctrl_set(dev_id, enable); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Get dynamic address aging status on particular device. - * @param[in] dev_id device id - * @param[in] enable enable or disable - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -shiva_fdb_age_ctrl_get(a_uint32_t dev_id, a_bool_t *enable) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _shiva_fdb_age_ctrl_get(dev_id, enable); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Set dynamic address aging time on a particular device. - * @details Comments: - * This operation will set dynamic address aging time on a particular device. - * The unit of time is second. Because different device has differnet - * hardware granularity function will return actual time in hardware. - * @param[in] dev_id device id - * @param time aging time - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -shiva_fdb_age_time_set(a_uint32_t dev_id, a_uint32_t * time) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _shiva_fdb_age_time_set(dev_id, time); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Get dynamic address aging time on a particular device. - * @param[in] dev_id device id - * @param[out] time aging time - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -shiva_fdb_age_time_get(a_uint32_t dev_id, a_uint32_t *time) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _shiva_fdb_age_time_get(dev_id, time); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Iterate all fdb entries on a particular device. - * @param[in] dev_id device id - * @param[in] iterator fdb entry index if it's zero means get the first entry - * @param[out] iterator next valid fdb entry index - * @param[out] entry fdb entry - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -shiva_fdb_iterate(a_uint32_t dev_id, a_uint32_t * iterator, fal_fdb_entry_t * entry) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _shiva_fdb_iterate(dev_id, iterator, entry); - HSL_API_UNLOCK; - return rv; -} - -sw_error_t -shiva_fdb_init(a_uint32_t dev_id) -{ - HSL_DEV_ID_CHECK(dev_id); - -#ifndef HSL_STANDALONG - { - hsl_api_t *p_api; - - SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id)); - - p_api->fdb_add = shiva_fdb_add; - p_api->fdb_del_all = shiva_fdb_del_all; - p_api->fdb_del_by_port = shiva_fdb_del_by_port; - p_api->fdb_del_by_mac = shiva_fdb_del_by_mac; - p_api->fdb_first = shiva_fdb_first; - p_api->fdb_find = shiva_fdb_find; - p_api->port_learn_set = shiva_fdb_port_learn_set; - p_api->port_learn_get = shiva_fdb_port_learn_get; - p_api->age_ctrl_set = shiva_fdb_age_ctrl_set; - p_api->age_ctrl_get = shiva_fdb_age_ctrl_get; - p_api->age_time_set = shiva_fdb_age_time_set; - p_api->age_time_get = shiva_fdb_age_time_get; - p_api->fdb_iterate = shiva_fdb_iterate; - } -#endif - - return SW_OK; -} - -/** - * @} - */ - diff --git a/feeds/ipq807x/qca-ssdk/src/src/hsl/shiva/shiva_igmp.c b/feeds/ipq807x/qca-ssdk/src/src/hsl/shiva/shiva_igmp.c deleted file mode 100755 index 2427d7884..000000000 --- a/feeds/ipq807x/qca-ssdk/src/src/hsl/shiva/shiva_igmp.c +++ /dev/null @@ -1,980 +0,0 @@ -/* - * Copyright (c) 2012, 2016 The Linux Foundation. All rights reserved. - * Permission to use, copy, modify, and/or distribute this software for - * any purpose with or without fee is hereby granted, provided that the - * above copyright notice and this permission notice appear in all copies. - * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES - * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR - * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES - * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN - * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT - * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. - */ - - -/** - * @defgroup shiva_igmp SHIVA_IGMP - * @{ - */ -#include "sw.h" -#include "hsl.h" -#include "hsl_dev.h" -#include "hsl_port_prop.h" -#include "shiva_igmp.h" -#include "shiva_reg.h" - -static sw_error_t -_shiva_port_igmps_status_set(a_uint32_t dev_id, fal_port_t port_id, a_bool_t enable) -{ - sw_error_t rv; - a_uint32_t val; - - HSL_DEV_ID_CHECK(dev_id); - - if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_EXCL_CPU)) - { - return SW_BAD_PARAM; - } - - if (A_TRUE == enable) - { - val = 1; - } - else if (A_FALSE == enable) - { - val = 0; - } - else - { - return SW_BAD_PARAM; - } - - HSL_REG_FIELD_SET(rv, dev_id, PORT_CTL, port_id, IGMP_MLD_EN, - (a_uint8_t *) (&val), sizeof (a_uint32_t)); - return rv; -} - -static sw_error_t -_shiva_port_igmps_status_get(a_uint32_t dev_id, fal_port_t port_id, a_bool_t *enable) -{ - sw_error_t rv; - a_uint32_t val = 0; - - HSL_DEV_ID_CHECK(dev_id); - - if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_EXCL_CPU)) - { - return SW_BAD_PARAM; - } - - HSL_REG_FIELD_GET(rv, dev_id, PORT_CTL, port_id, IGMP_MLD_EN, - (a_uint8_t *) (&val), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - - if (1 == val) - { - *enable = A_TRUE; - } - else - { - *enable = A_FALSE; - } - - return SW_OK; -} - -static sw_error_t -_shiva_igmp_mld_cmd_set(a_uint32_t dev_id, fal_fwd_cmd_t cmd) -{ - sw_error_t rv; - a_uint32_t val; - - HSL_DEV_ID_CHECK(dev_id); - - if (FAL_MAC_CPY_TO_CPU == cmd) - { - val = 1; - } - else if (FAL_MAC_RDT_TO_CPU == cmd) - { - val = 0; - } - else - { - return SW_NOT_SUPPORTED; - } - - HSL_REG_FIELD_SET(rv, dev_id, QM_CTL, 0, IGMP_COPY_EN, - (a_uint8_t *) (&val), sizeof (a_uint32_t)); - return rv; -} - -static sw_error_t -_shiva_igmp_mld_cmd_get(a_uint32_t dev_id, fal_fwd_cmd_t * cmd) -{ - sw_error_t rv; - a_uint32_t val = 0; - - HSL_DEV_ID_CHECK(dev_id); - - HSL_REG_FIELD_GET(rv, dev_id, QM_CTL, 0, IGMP_COPY_EN, - (a_uint8_t *) (&val), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - - if (1 == val) - { - *cmd = FAL_MAC_CPY_TO_CPU; - } - else - { - *cmd = FAL_MAC_RDT_TO_CPU; - } - - return SW_OK; -} - -static sw_error_t -_shiva_port_igmp_mld_join_set(a_uint32_t dev_id, fal_port_t port_id, a_bool_t enable) -{ - sw_error_t rv; - a_uint32_t val; - - HSL_DEV_ID_CHECK(dev_id); - - if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_EXCL_CPU)) - { - return SW_BAD_PARAM; - } - - if (A_TRUE == enable) - { - val = 1; - } - else if (A_FALSE == enable) - { - val = 0; - } - else - { - return SW_BAD_PARAM; - } - - HSL_REG_FIELD_SET(rv, dev_id, PORT_CTL, port_id, JOIN_EN, - (a_uint8_t *) (&val), sizeof (a_uint32_t)); - return rv; -} - -static sw_error_t -_shiva_port_igmp_mld_join_get(a_uint32_t dev_id, fal_port_t port_id, a_bool_t * enable) -{ - sw_error_t rv; - a_uint32_t val = 0; - - HSL_DEV_ID_CHECK(dev_id); - - if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_EXCL_CPU)) - { - return SW_BAD_PARAM; - } - - HSL_REG_FIELD_GET(rv, dev_id, PORT_CTL, port_id, JOIN_EN, - (a_uint8_t *) (&val), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - - if (val) - { - *enable = A_TRUE; - } - else - { - *enable = A_FALSE; - } - - return SW_OK; -} - -static sw_error_t -_shiva_port_igmp_mld_leave_set(a_uint32_t dev_id, fal_port_t port_id, a_bool_t enable) -{ - sw_error_t rv; - a_uint32_t val; - - HSL_DEV_ID_CHECK(dev_id); - - if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_EXCL_CPU)) - { - return SW_BAD_PARAM; - } - - if (A_TRUE == enable) - { - val = 1; - } - else if (A_FALSE == enable) - { - val = 0; - } - else - { - return SW_BAD_PARAM; - } - - HSL_REG_FIELD_SET(rv, dev_id, PORT_CTL, port_id, LEAVE_EN, - (a_uint8_t *) (&val), sizeof (a_uint32_t)); - return rv; -} - -static sw_error_t -_shiva_port_igmp_mld_leave_get(a_uint32_t dev_id, fal_port_t port_id, a_bool_t * enable) -{ - sw_error_t rv; - a_uint32_t val = 0; - - HSL_DEV_ID_CHECK(dev_id); - - if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_EXCL_CPU)) - { - return SW_BAD_PARAM; - } - - HSL_REG_FIELD_GET(rv, dev_id, PORT_CTL, port_id, LEAVE_EN, - (a_uint8_t *) (&val), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - - if (val) - { - *enable = A_TRUE; - } - else - { - *enable = A_FALSE; - } - - return SW_OK; -} - -static sw_error_t -_shiva_igmp_mld_rp_set(a_uint32_t dev_id, fal_pbmp_t pts) -{ - sw_error_t rv; - a_uint32_t val; - - HSL_DEV_ID_CHECK(dev_id); - - if (A_FALSE == hsl_mports_validity_check(dev_id, pts)) - { - return SW_BAD_PARAM; - } - val = pts; - HSL_REG_FIELD_SET(rv, dev_id, FLOOD_MASK, 0, IGMP_DP, - (a_uint8_t *) (&val), sizeof (a_uint32_t)); - return rv; -} - -static sw_error_t -_shiva_igmp_mld_rp_get(a_uint32_t dev_id, fal_pbmp_t * pts) -{ - sw_error_t rv; - a_uint32_t val = 0; - - HSL_DEV_ID_CHECK(dev_id); - - HSL_REG_FIELD_GET(rv, dev_id, FLOOD_MASK, 0, IGMP_DP, - (a_uint8_t *) (&val), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - - *pts = val; - return SW_OK; -} - -static sw_error_t -_shiva_igmp_mld_entry_creat_set(a_uint32_t dev_id, a_bool_t enable) -{ - sw_error_t rv; - a_uint32_t val; - - HSL_DEV_ID_CHECK(dev_id); - - if (A_TRUE == enable) - { - val = 1; - } - else if (A_FALSE == enable) - { - val = 0; - } - else - { - return SW_BAD_PARAM; - } - - HSL_REG_FIELD_SET(rv, dev_id, QM_CTL, 0, IGMP_CREAT_EN, - (a_uint8_t *) (&val), sizeof (a_uint32_t)); - return rv; -} - -static sw_error_t -_shiva_igmp_mld_entry_creat_get(a_uint32_t dev_id, a_bool_t * enable) -{ - sw_error_t rv; - a_uint32_t val = 0; - - HSL_DEV_ID_CHECK(dev_id); - - HSL_REG_FIELD_GET(rv, dev_id, QM_CTL, 0, IGMP_CREAT_EN, - (a_uint8_t *) (&val), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - - if (val) - { - *enable = A_TRUE; - } - else - { - *enable = A_FALSE; - } - - return SW_OK; -} - -static sw_error_t -_shiva_igmp_mld_entry_static_set(a_uint32_t dev_id, a_bool_t enable) -{ - sw_error_t rv; - a_uint32_t val; - - HSL_DEV_ID_CHECK(dev_id); - - if (A_TRUE == enable) - { - val = 0xf; - } - else if (A_FALSE == enable) - { - val = 0xe; - } - else - { - return SW_BAD_PARAM; - } - - HSL_REG_FIELD_SET(rv, dev_id, QM_CTL, 0, IGMP_JOIN_STATIC, - (a_uint8_t *) (&val), sizeof (a_uint32_t)); - return rv; -} - -static sw_error_t -_shiva_igmp_mld_entry_static_get(a_uint32_t dev_id, a_bool_t * enable) -{ - sw_error_t rv; - a_uint32_t val = 0; - - HSL_DEV_ID_CHECK(dev_id); - - HSL_REG_FIELD_GET(rv, dev_id, QM_CTL, 0, IGMP_JOIN_STATIC, - (a_uint8_t *) (&val), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - - if (0xf == val) - { - *enable = A_TRUE; - } - else - { - *enable = A_FALSE; - } - - return SW_OK; -} - -static sw_error_t -_shiva_igmp_mld_entry_leaky_set(a_uint32_t dev_id, a_bool_t enable) -{ - sw_error_t rv; - a_uint32_t val; - - HSL_DEV_ID_CHECK(dev_id); - - if (A_TRUE == enable) - { - val = 1; - } - else if (A_FALSE == enable) - { - val = 0; - } - else - { - return SW_BAD_PARAM; - } - - HSL_REG_FIELD_SET(rv, dev_id, QM_CTL, 0, IGMP_JOIN_LEAKY, - (a_uint8_t *) (&val), sizeof (a_uint32_t)); - return rv; -} - -static sw_error_t -_shiva_igmp_mld_entry_leaky_get(a_uint32_t dev_id, a_bool_t * enable) -{ - sw_error_t rv; - a_uint32_t val = 0; - - HSL_DEV_ID_CHECK(dev_id); - - HSL_REG_FIELD_GET(rv, dev_id, QM_CTL, 0, IGMP_JOIN_LEAKY, - (a_uint8_t *) (&val), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - - if (val) - { - *enable = A_TRUE; - } - else - { - *enable = A_FALSE; - } - - return SW_OK; -} - -static sw_error_t -_shiva_igmp_mld_entry_v3_set(a_uint32_t dev_id, a_bool_t enable) -{ - sw_error_t rv; - a_uint32_t val; - - HSL_DEV_ID_CHECK(dev_id); - - if (A_TRUE == enable) - { - val = 1; - } - else if (A_FALSE == enable) - { - val = 0; - } - else - { - return SW_BAD_PARAM; - } - - HSL_REG_FIELD_SET(rv, dev_id, QM_CTL, 0, IGMP_V3_EN, - (a_uint8_t *) (&val), sizeof (a_uint32_t)); - return rv; -} - -static sw_error_t -_shiva_igmp_mld_entry_v3_get(a_uint32_t dev_id, a_bool_t * enable) -{ - sw_error_t rv; - a_uint32_t val = 0; - - HSL_DEV_ID_CHECK(dev_id); - - HSL_REG_FIELD_GET(rv, dev_id, QM_CTL, 0, IGMP_V3_EN, - (a_uint8_t *) (&val), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - - if (val) - { - *enable = A_TRUE; - } - else - { - *enable = A_FALSE; - } - - return SW_OK; -} - -static sw_error_t -_shiva_igmp_mld_entry_queue_set(a_uint32_t dev_id, a_bool_t enable, a_uint32_t queue) -{ - sw_error_t rv; - a_uint32_t entry = 0; - hsl_dev_t *p_dev; - - HSL_DEV_ID_CHECK(dev_id); - - HSL_REG_ENTRY_GET(rv, dev_id, QM_CTL, 0, - (a_uint8_t *) (&entry), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - - if (A_TRUE == enable) - { - SW_SET_REG_BY_FIELD(QM_CTL, IGMP_PRI_EN, 1, entry); - SW_RTN_ON_NULL(p_dev = hsl_dev_ptr_get(dev_id)); - if (queue >= p_dev->nr_queue) - { - return SW_BAD_PARAM; - } - SW_SET_REG_BY_FIELD(QM_CTL, IGMP_PRI, queue, entry); - } - else if (A_FALSE == enable) - { - SW_SET_REG_BY_FIELD(QM_CTL, IGMP_PRI_EN, 0, entry); - SW_SET_REG_BY_FIELD(QM_CTL, IGMP_PRI, 0, entry); - } - else - { - return SW_BAD_PARAM; - } - - HSL_REG_ENTRY_SET(rv, dev_id, QM_CTL, 0, - (a_uint8_t *) (&entry), sizeof (a_uint32_t)); - return rv; -} - -static sw_error_t -_shiva_igmp_mld_entry_queue_get(a_uint32_t dev_id, a_bool_t * enable, a_uint32_t * queue) -{ - sw_error_t rv; - a_uint32_t entry = 0, data; - - HSL_DEV_ID_CHECK(dev_id); - - HSL_REG_ENTRY_GET(rv, dev_id, QM_CTL, 0, - (a_uint8_t *) (&entry), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - - SW_GET_FIELD_BY_REG(QM_CTL, IGMP_PRI_EN, data, entry); - if (data) - { - *enable = A_TRUE; - SW_GET_FIELD_BY_REG(QM_CTL, IGMP_PRI, data, entry); - *queue = data; - } - else - { - *enable = A_FALSE; - *queue = 0; - } - - return SW_OK; -} - -/** - * @brief Set igmp/mld packets snooping status on a particular port. - * @details Comments: - * After enabling igmp/mld snooping feature on a particular port all kinds - * igmp/mld packets received on this port would be acknowledged by hardware. - * Particular forwarding decision could be setted by fal_igmp_mld_cmd_set. - * @param[in] dev_id device id - * @param[in] port_id port id - * @param[in] enable A_TRUE or A_FALSE - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -shiva_port_igmps_status_set(a_uint32_t dev_id, fal_port_t port_id, a_bool_t enable) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _shiva_port_igmps_status_set(dev_id, port_id, enable); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Get igmp/mld packets snooping status on particular port. - * @param[in] dev_id device id - * @param[in] port_id port id - * @param[out] enable A_TRUE or A_FALSE - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -shiva_port_igmps_status_get(a_uint32_t dev_id, fal_port_t port_id, a_bool_t *enable) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _shiva_port_igmps_status_get(dev_id, port_id, enable); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Set igmp/mld packets forwarding command on a particular device. - * @details Comments: - * Particular device may only support parts of forwarding commands. - * This operation will take effect only after enabling igmp/mld snooping - * @param[in] dev_id device id - * @param[in] cmd forwarding command - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -shiva_igmp_mld_cmd_set(a_uint32_t dev_id, fal_fwd_cmd_t cmd) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _shiva_igmp_mld_cmd_set(dev_id, cmd); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Get igmp/mld packets forwarding command on a particular device. - * @param[in] dev_id device id - * @param[out] cmd forwarding command - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -shiva_igmp_mld_cmd_get(a_uint32_t dev_id, fal_fwd_cmd_t * cmd) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _shiva_igmp_mld_cmd_get(dev_id, cmd); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Set igmp/mld join packets hardware acknowledgement status on particular port. - * @details Comments: - * After enabling igmp/mld join feature on a particular port hardware will - * dynamic learning or changing multicast entry. - * @param[in] dev_id device id - * @param[in] port_id port id - * @param[in] enable A_TRUE or A_FALSE - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -shiva_port_igmp_mld_join_set(a_uint32_t dev_id, fal_port_t port_id, a_bool_t enable) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _shiva_port_igmp_mld_join_set(dev_id, port_id, enable); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Get igmp/mld join packets hardware acknowledgement status on a particular port. - * @param[in] dev_id device id - * @param[in] port_id port id - * @param[out] enable A_TRUE or A_FALSE - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -shiva_port_igmp_mld_join_get(a_uint32_t dev_id, fal_port_t port_id, a_bool_t * enable) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _shiva_port_igmp_mld_join_get(dev_id, port_id, enable); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Set igmp/mld leave packets hardware acknowledgement status on a particular port. - * @details Comments: - * After enabling igmp leave feature on a particular port hardware will dynamic - * deleting or changing multicast entry. - * @param[in] dev_id device id - * @param[in] port_id port id - * @param[in] enable A_TRUE or A_FALSE - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -shiva_port_igmp_mld_leave_set(a_uint32_t dev_id, fal_port_t port_id, a_bool_t enable) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _shiva_port_igmp_mld_leave_set(dev_id, port_id, enable); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Get igmp/mld leave packets hardware acknowledgement status on a particular port. - * @param[in] dev_id device id - * @param[in] port_id port id - * @param[out] enable A_TRUE or A_FALSE - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -shiva_port_igmp_mld_leave_get(a_uint32_t dev_id, fal_port_t port_id, a_bool_t * enable) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _shiva_port_igmp_mld_leave_get(dev_id, port_id, enable); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Set igmp/mld router ports on a particular device. - * @details Comments: - * After enabling igmp/mld join/leave feature on a particular port igmp/mld - * join/leave packets received on this port will be forwarded to router ports. - * @param[in] dev_id device id - * @param[in] pts dedicates ports - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -shiva_igmp_mld_rp_set(a_uint32_t dev_id, fal_pbmp_t pts) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _shiva_igmp_mld_rp_set(dev_id, pts); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Get igmp/mld router ports on a particular device. - * @param[in] dev_id device id - * @param[out] pts dedicates ports - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -shiva_igmp_mld_rp_get(a_uint32_t dev_id, fal_pbmp_t * pts) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _shiva_igmp_mld_rp_get(dev_id, pts); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Set the status of creating multicast entry during igmp/mld join/leave procedure. - * @details Comments: - * After enabling igmp/mld join/leave feature on a particular port if enable - * entry creat hardware will dynamic creat and delete multicast entry, - * otherwise hardware only can change destination ports of existing muticast entry. - * @param[in] dev_id device id - * @param[in] enable A_TRUE or A_FALSE - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -shiva_igmp_mld_entry_creat_set(a_uint32_t dev_id, a_bool_t enable) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _shiva_igmp_mld_entry_creat_set(dev_id, enable); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Get the status of creating multicast entry during igmp/mld join/leave procedure. - * @param[in] dev_id device id - * @param[out] enable A_TRUE or A_FALSE - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -shiva_igmp_mld_entry_creat_get(a_uint32_t dev_id, a_bool_t * enable) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _shiva_igmp_mld_entry_creat_get(dev_id, enable); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Set the static status of multicast entry which learned by hardware. - * @details Comments: - * After enabling igmp/mld join/leave feature on a particular port if enable - * static status hardware will not age out multicast entry which leardned by hardware, - * otherwise hardware will age out multicast entry which leardned by hardware. - * @param[in] dev_id device id - * @param[in] enable A_TRUE or A_FALSE - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -shiva_igmp_mld_entry_static_set(a_uint32_t dev_id, a_bool_t enable) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _shiva_igmp_mld_entry_static_set(dev_id, enable); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Get the static status of multicast entry which learned by hardware. - * @param[in] dev_id device id - * @param[out] enable A_TRUE or A_FALSE - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -shiva_igmp_mld_entry_static_get(a_uint32_t dev_id, a_bool_t * enable) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _shiva_igmp_mld_entry_static_get(dev_id, enable); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Set the leaky status of multicast entry which learned by hardware. - * @details Comments: - * After enabling igmp/mld join/leave feature on a particular port if enable - * leaky status hardware will set leaky flag of multicast entry which leardned by hardware, - * otherwise hardware will not set leaky flag of multicast entry which leardned by hardware. - * @param[in] dev_id device id - * @param[in] enable A_TRUE or A_FALSE - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -shiva_igmp_mld_entry_leaky_set(a_uint32_t dev_id, a_bool_t enable) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _shiva_igmp_mld_entry_leaky_set(dev_id, enable); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Get the leaky status of multicast entry which learned by hardware. - * @param[in] dev_id device id - * @param[out] enable A_TRUE or A_FALSE - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -shiva_igmp_mld_entry_leaky_get(a_uint32_t dev_id, a_bool_t * enable) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _shiva_igmp_mld_entry_leaky_get(dev_id, enable); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Set igmpv3/mldv2 packets hardware acknowledgement status on a particular device. - * @details Comments: - * After enabling igmp join/leave feature on a particular port hardware will dynamic - * creating or changing multicast entry after receiving igmpv3/mldv2 packets. - * @param[in] dev_id device id - * @param[in] enable A_TRUE or A_FALSE - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -shiva_igmp_mld_entry_v3_set(a_uint32_t dev_id, a_bool_t enable) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _shiva_igmp_mld_entry_v3_set(dev_id, enable); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Get igmpv3/mldv2 packets hardware acknowledgement status on a particular device. - * @param[in] dev_id device id - * @param[out] enable A_TRUE or A_FALSE - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -shiva_igmp_mld_entry_v3_get(a_uint32_t dev_id, a_bool_t * enable) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _shiva_igmp_mld_entry_v3_get(dev_id, enable); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Set the queue status of multicast entry which learned by hardware. - * @details Comments: - * After enabling igmp/mld join/leave feature on a particular port if enable - * leaky status hardware will set queue flag of multicast entry which leardned by hardware, - * otherwise hardware will not set queue flag of multicast entry which leardned by hardware. - * @param[in] dev_id device id - * @param[in] enable A_TRUE or A_FALSE - * @param[in] queue queue id - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -shiva_igmp_mld_entry_queue_set(a_uint32_t dev_id, a_bool_t enable, a_uint32_t queue) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _shiva_igmp_mld_entry_queue_set(dev_id, enable, queue); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Get the queue status of multicast entry which learned by hardware. - * @param[in] dev_id device id - * @param[out] enable A_TRUE or A_FALSE - * @param[out] queue queue id - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -shiva_igmp_mld_entry_queue_get(a_uint32_t dev_id, a_bool_t * enable, a_uint32_t * queue) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _shiva_igmp_mld_entry_queue_get(dev_id, enable, queue); - HSL_API_UNLOCK; - return rv; -} - -sw_error_t -shiva_igmp_init(a_uint32_t dev_id) -{ - HSL_DEV_ID_CHECK(dev_id); - -#ifndef HSL_STANDALONG - { - hsl_api_t *p_api; - - SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id)); - - p_api->port_igmps_status_set = shiva_port_igmps_status_set; - p_api->port_igmps_status_get = shiva_port_igmps_status_get; - p_api->igmp_mld_cmd_set = shiva_igmp_mld_cmd_set; - p_api->igmp_mld_cmd_get = shiva_igmp_mld_cmd_get; - p_api->port_igmp_join_set = shiva_port_igmp_mld_join_set; - p_api->port_igmp_join_get = shiva_port_igmp_mld_join_get; - p_api->port_igmp_leave_set = shiva_port_igmp_mld_leave_set; - p_api->port_igmp_leave_get = shiva_port_igmp_mld_leave_get; - p_api->igmp_rp_set = shiva_igmp_mld_rp_set; - p_api->igmp_rp_get = shiva_igmp_mld_rp_get; - p_api->igmp_entry_creat_set = shiva_igmp_mld_entry_creat_set; - p_api->igmp_entry_creat_get = shiva_igmp_mld_entry_creat_get; - p_api->igmp_entry_static_set = shiva_igmp_mld_entry_static_set; - p_api->igmp_entry_static_get = shiva_igmp_mld_entry_static_get; - p_api->igmp_entry_leaky_set = shiva_igmp_mld_entry_leaky_set; - p_api->igmp_entry_leaky_get = shiva_igmp_mld_entry_leaky_get; - p_api->igmp_entry_v3_set = shiva_igmp_mld_entry_v3_set; - p_api->igmp_entry_v3_get = shiva_igmp_mld_entry_v3_get; - p_api->igmp_entry_queue_set = shiva_igmp_mld_entry_queue_set; - p_api->igmp_entry_queue_get = shiva_igmp_mld_entry_queue_get; - } -#endif - - return SW_OK; -} - -/** - * @} - */ - diff --git a/feeds/ipq807x/qca-ssdk/src/src/hsl/shiva/shiva_init.c b/feeds/ipq807x/qca-ssdk/src/src/hsl/shiva/shiva_init.c deleted file mode 100755 index 1fea80f94..000000000 --- a/feeds/ipq807x/qca-ssdk/src/src/hsl/shiva/shiva_init.c +++ /dev/null @@ -1,448 +0,0 @@ -/* - * Copyright (c) 2012, 2016-2017, The Linux Foundation. All rights reserved. - * Permission to use, copy, modify, and/or distribute this software for - * any purpose with or without fee is hereby granted, provided that the - * above copyright notice and this permission notice appear in all copies. - * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES - * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR - * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES - * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN - * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT - * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. - */ - - -/** - * @defgroup shiva_init SHIVA_INIT - * @{ - */ -#include "sw.h" -#include "hsl.h" -#include "hsl_dev.h" -#include "hsl_port_prop.h" -#include "shiva_mib.h" -#include "shiva_port_ctrl.h" -#include "shiva_portvlan.h" -#include "shiva_vlan.h" -#include "shiva_fdb.h" -#include "shiva_qos.h" -#include "shiva_mirror.h" -#include "shiva_stp.h" -#include "shiva_rate.h" -#include "shiva_misc.h" -#include "shiva_leaky.h" -#include "shiva_igmp.h" -#include "shiva_acl.h" -#include "shiva_led.h" -#include "shiva_reg_access.h" -#include "shiva_reg.h" -#include "shiva_init.h" -#include "f1_phy.h" - -static ssdk_init_cfg * shiva_cfg[SW_MAX_NR_DEV] = { 0 }; - -#if !(defined(KERNEL_MODULE) && defined(USER_MODE)) -/* For SHIVA there are five internal PHY devices and seven MAC devices. - MAC0 always connect to external MAC device. - PHY4 can connect to MAC5 or external MAC device. - MAC6 always connect to external devices. - MAC1..MAC4 connect to internal PHY0..PHY3. -*/ -static sw_error_t -shiva_portproperty_init(a_uint32_t dev_id, hsl_init_mode mode) -{ - hsl_port_prop_t p_type; - hsl_dev_t *pdev = NULL; - fal_port_t port_id; - - pdev = hsl_dev_ptr_get(dev_id); - if (pdev == NULL) - return SW_NOT_INITIALIZED; - - for (port_id = 0; port_id < pdev->nr_ports; port_id++) - { - hsl_port_prop_portmap_set(dev_id, port_id); - - for (p_type = HSL_PP_PHY; p_type < HSL_PP_BUTT; p_type++) - { - if (HSL_NO_CPU == mode) - { - SW_RTN_ON_ERROR(hsl_port_prop_set(dev_id, port_id, p_type)); - continue; - } - - switch (p_type) - { - case HSL_PP_PHY: - if (HSL_CPU_1 != mode) - { - if ((port_id != pdev->cpu_port_nr) - && (port_id != (pdev->nr_ports -1)) - && (port_id != (pdev->nr_ports -2))) - { - SW_RTN_ON_ERROR(hsl_port_prop_set(dev_id, port_id, p_type)); - } - } - else - { - if ((port_id != pdev->cpu_port_nr) - && (port_id != pdev->nr_ports - 1)) - { - SW_RTN_ON_ERROR(hsl_port_prop_set(dev_id, port_id, p_type)); - } - } - break; - - case HSL_PP_INCL_CPU: - /* include cpu port but exclude wan port in some cases */ - if (!((HSL_CPU_2 == mode) && (port_id == (pdev->nr_ports - 2)))) - SW_RTN_ON_ERROR(hsl_port_prop_set(dev_id, port_id, p_type)); - - break; - - case HSL_PP_EXCL_CPU: - /* exclude cpu port and wan port in some cases */ - if ((port_id != pdev->cpu_port_nr) - && (!((HSL_CPU_2 == mode) && (port_id == (pdev->nr_ports - 2))))) - SW_RTN_ON_ERROR(hsl_port_prop_set(dev_id, port_id, p_type)); - break; - - default: - break; - } - } - - if (HSL_NO_CPU == mode) - { - SW_RTN_ON_ERROR(hsl_port_prop_set_phyid - (dev_id, port_id, port_id + 1)); - } - else - { - if (port_id != pdev->cpu_port_nr) - { - SW_RTN_ON_ERROR(hsl_port_prop_set_phyid - (dev_id, port_id, port_id - 1)); - } - } - } - - return SW_OK; -} - -static sw_error_t -shiva_hw_init(a_uint32_t dev_id, ssdk_init_cfg *cfg) -{ - hsl_dev_t *pdev = NULL; - a_uint32_t port_id; - a_uint32_t data = 0; - sw_error_t rv; - - pdev = hsl_dev_ptr_get(dev_id); - if (NULL == pdev) - { - return SW_NOT_INITIALIZED; - } - - for (port_id = 0; port_id < pdev->nr_ports; port_id++) - { - if (port_id == pdev->cpu_port_nr) - { - continue; - } - - HSL_REG_ENTRY_GET(rv, dev_id, PORT_STATUS, port_id, - (a_uint8_t *) (&data), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - - SW_SET_REG_BY_FIELD(PORT_STATUS, LINK_EN, 1, data); - - HSL_REG_ENTRY_SET(rv, dev_id, PORT_STATUS, port_id, - (a_uint8_t *) (&data), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - } - - return SW_OK; -} - -#if 0 -static sw_error_t -shiva_bist_test(a_uint32_t dev_id) -{ - a_uint32_t entry = 0, data, i; - sw_error_t rv; - - data = 1; - i = 0x1000; - while (data && --i) - { - HSL_REG_ENTRY_GET(rv, dev_id, BIST_CTRL, 0, - (a_uint8_t *) (&entry), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - SW_GET_FIELD_BY_REG(BIST_CTRL, BIST_BUSY, data, entry); - aos_udelay(5); - } - - if (0 == i) - { - return SW_INIT_ERROR; - } - - entry = 0; - SW_SET_REG_BY_FIELD(BIST_CTRL, BIST_BUSY, 1, entry); - SW_SET_REG_BY_FIELD(BIST_CTRL, PTN_EN2, 1, entry); - SW_SET_REG_BY_FIELD(BIST_CTRL, PTN_EN1, 1, entry); - SW_SET_REG_BY_FIELD(BIST_CTRL, PTN_EN0, 1, entry); - - HSL_REG_ENTRY_SET(rv, dev_id, BIST_CTRL, 0, - (a_uint8_t *) (&entry), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - - data = 1; - i = 0x1000; - while (data && --i) - { - HSL_REG_ENTRY_GET(rv, dev_id, BIST_CTRL, 0, - (a_uint8_t *) (&entry), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - SW_GET_FIELD_BY_REG(BIST_CTRL, BIST_BUSY, data, entry); - aos_udelay(5); - } - - if (0 == i) - { - return SW_INIT_ERROR; - } - - SW_GET_FIELD_BY_REG(BIST_CTRL, ERR_CNT, data, entry); - if (data) - { - SW_GET_FIELD_BY_REG(BIST_CTRL, ONE_ERR, data, entry); - if (!data) - { - return SW_INIT_ERROR; - } - - SW_GET_FIELD_BY_REG(BIST_CTRL, ERR_ADDR, data, entry); - - entry = 0; - SW_SET_REG_BY_FIELD(BIST_RCV, RCV_EN, 1, entry); - SW_SET_REG_BY_FIELD(BIST_RCV, RCV_ADDR, data, entry); - HSL_REG_ENTRY_SET(rv, dev_id, BIST_RCV, 0, - (a_uint8_t *) (&entry), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - } - else - { - return SW_OK; - } - - entry = 0; - SW_SET_REG_BY_FIELD(BIST_CTRL, BIST_BUSY, 1, entry); - SW_SET_REG_BY_FIELD(BIST_CTRL, PTN_EN2, 1, entry); - SW_SET_REG_BY_FIELD(BIST_CTRL, PTN_EN1, 1, entry); - SW_SET_REG_BY_FIELD(BIST_CTRL, PTN_EN0, 1, entry); - - HSL_REG_ENTRY_SET(rv, dev_id, BIST_CTRL, 0, - (a_uint8_t *) (&entry), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - - data = 1; - i = 0x1000; - while (data && --i) - { - HSL_REG_ENTRY_GET(rv, dev_id, BIST_CTRL, 0, - (a_uint8_t *) (&entry), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - SW_GET_FIELD_BY_REG(BIST_CTRL, BIST_BUSY, data, entry); - aos_udelay(5); - } - - if (0 == i) - { - return SW_INIT_ERROR; - } - - SW_GET_FIELD_BY_REG(BIST_CTRL, ERR_CNT, data, entry); - if (data) - { - return SW_INIT_ERROR; - } - - return SW_OK; -} -#endif -#endif - -static sw_error_t -shiva_dev_init(a_uint32_t dev_id, hsl_init_mode cpu_mode) -{ - hsl_dev_t *pdev = NULL; - - pdev = hsl_dev_ptr_get(dev_id); - if (pdev == NULL) - return SW_NOT_INITIALIZED; - - pdev->nr_ports = 7; - pdev->nr_phy = 5; - pdev->cpu_port_nr = 0; - pdev->nr_vlans = 4096; - pdev->hw_vlan_query = A_TRUE; - pdev->nr_queue = 4; - pdev->cpu_mode = cpu_mode; - - return SW_OK; -} - - -static sw_error_t -_shiva_reset(a_uint32_t dev_id) -{ -#if !(defined(KERNEL_MODULE) && defined(USER_MODE)) - sw_error_t rv; - a_uint32_t val; - - HSL_DEV_ID_CHECK(dev_id); - - val = 0x1; - HSL_REG_FIELD_SET(rv, dev_id, MASK_CTL, 0, SOFT_RST, - (a_uint8_t *) (&val), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - - rv = shiva_hw_init(dev_id, shiva_cfg[dev_id]); - SW_RTN_ON_ERROR(rv); - - SHIVA_ACL_RESET(rv, dev_id); -#endif - - return SW_OK; -} - -sw_error_t -shiva_cleanup(a_uint32_t dev_id) -{ - if (shiva_cfg[dev_id]) - { - aos_mem_free(shiva_cfg[dev_id]); - shiva_cfg[dev_id] = NULL; - } - - return SW_OK; -} - -/** - * @brief reset hsl layer. - * @details Comments: - * This operation will reset hsl layer - * @param[in] dev_id device id - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -shiva_reset(a_uint32_t dev_id) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _shiva_reset(dev_id); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Init hsl layer. - * @details Comments: - * This operation will init hsl layer and hsl layer - * @param[in] dev_id device id - * @param[in] cfg configuration for initialization - * @return SW_OK or error code - */ -sw_error_t -shiva_init(a_uint32_t dev_id, ssdk_init_cfg *cfg) -{ - sw_error_t rv; - HSL_DEV_ID_CHECK(dev_id); - - if (NULL == shiva_cfg[dev_id]) - { - shiva_cfg[dev_id] = aos_mem_alloc(sizeof (ssdk_init_cfg)); - } - - if (NULL == shiva_cfg[dev_id]) - { - return SW_OUT_OF_MEM; - } - - aos_mem_copy(shiva_cfg[dev_id], cfg, sizeof (ssdk_init_cfg)); - - SW_RTN_ON_ERROR(shiva_reg_access_init(dev_id, cfg->reg_mode)); - - SW_RTN_ON_ERROR(shiva_dev_init(dev_id, cfg->cpu_mode)); - -#if !(defined(KERNEL_MODULE) && defined(USER_MODE)) - { -/* - if(HSL_MDIO == cfg->reg_mode) - { - SW_RTN_ON_ERROR(shiva_bist_test(dev_id)); - - entry = 0x1; - HSL_REG_FIELD_SET(rv, dev_id, MASK_CTL, 0, SOFT_RST, - (a_uint8_t *) (&entry), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - - i = 0x10; - do - { - HSL_REG_FIELD_GET(rv, dev_id, MASK_CTL, 0, SOFT_RST, - (a_uint8_t *) (&entry), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - - aos_mdelay(10); - } - while (entry && --i); - - if (0 == i) - { - return SW_INIT_ERROR; - } - } -*/ - SW_RTN_ON_ERROR(hsl_port_prop_init(dev_id)); - SW_RTN_ON_ERROR(hsl_port_prop_init_by_dev(dev_id)); - SW_RTN_ON_ERROR(shiva_portproperty_init(dev_id, cfg->cpu_mode)); - - SHIVA_MIB_INIT(rv, dev_id); - SHIVA_PORT_CTRL_INIT(rv, dev_id); - SHIVA_PORTVLAN_INIT(rv, dev_id); - SHIVA_VLAN_INIT(rv, dev_id); - SHIVA_FDB_INIT(rv, dev_id); - SHIVA_QOS_INIT(rv, dev_id); - SHIVA_STP_INIT(rv, dev_id); - SHIVA_MIRR_INIT(rv, dev_id); - SHIVA_RATE_INIT(rv, dev_id); - SHIVA_MISC_INIT(rv, dev_id); - SHIVA_LEAKY_INIT(rv, dev_id); - SHIVA_IGMP_INIT(rv, dev_id); - SHIVA_ACL_INIT(rv, dev_id); - SHIVA_LED_INIT(rv, dev_id); - - { - hsl_api_t *p_api; - - SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id)); - p_api->dev_reset = shiva_reset; - p_api->dev_clean = shiva_cleanup; - } - - /*SW_RTN_ON_ERROR(shiva_hw_init(dev_id, cfg));*/ - } -#endif - - return SW_OK; -} - -/** - * @} - */ - diff --git a/feeds/ipq807x/qca-ssdk/src/src/hsl/shiva/shiva_leaky.c b/feeds/ipq807x/qca-ssdk/src/src/hsl/shiva/shiva_leaky.c deleted file mode 100755 index c68e66fb5..000000000 --- a/feeds/ipq807x/qca-ssdk/src/src/hsl/shiva/shiva_leaky.c +++ /dev/null @@ -1,526 +0,0 @@ -/* - * Copyright (c) 2012, 2016 The Linux Foundation. All rights reserved. - * Permission to use, copy, modify, and/or distribute this software for - * any purpose with or without fee is hereby granted, provided that the - * above copyright notice and this permission notice appear in all copies. - * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES - * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR - * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES - * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN - * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT - * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. - */ - - -/** - * @defgroup shiva_leaky SHIVA_LEAKY - * @{ - */ -#include "sw.h" -#include "hsl.h" -#include "hsl_dev.h" -#include "hsl_port_prop.h" -#include "shiva_leaky.h" -#include "shiva_reg.h" - -static sw_error_t -_shiva_uc_leaky_mode_set(a_uint32_t dev_id, - fal_leaky_ctrl_mode_t ctrl_mode) -{ - a_uint32_t data; - sw_error_t rv; - - HSL_DEV_ID_CHECK(dev_id); - - if (FAL_LEAKY_PORT_CTRL == ctrl_mode) - { - data = 0; - } - else if (FAL_LEAKY_FDB_CTRL == ctrl_mode) - { - data = 1; - } - else - { - return SW_BAD_PARAM; - } - - HSL_REG_FIELD_SET(rv, dev_id, FLOOD_MASK, 0, ARL_UNI_LEAKY, - (a_uint8_t *) (&data), sizeof (a_uint32_t)); - return rv; -} - -static sw_error_t -_shiva_uc_leaky_mode_get(a_uint32_t dev_id, - fal_leaky_ctrl_mode_t *ctrl_mode) -{ - a_uint32_t data = 0; - sw_error_t rv; - - HSL_DEV_ID_CHECK(dev_id); - - HSL_REG_FIELD_GET(rv, dev_id, FLOOD_MASK, 0, ARL_UNI_LEAKY, - (a_uint8_t *) (&data), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - - if (1 == data) - { - *ctrl_mode = FAL_LEAKY_FDB_CTRL; - } - else - { - *ctrl_mode = FAL_LEAKY_PORT_CTRL; - } - - return SW_OK; -} - -static sw_error_t -_shiva_mc_leaky_mode_set(a_uint32_t dev_id, - fal_leaky_ctrl_mode_t ctrl_mode) -{ - a_uint32_t data; - sw_error_t rv; - - HSL_DEV_ID_CHECK(dev_id); - - if (FAL_LEAKY_PORT_CTRL == ctrl_mode) - { - data = 0; - } - else if (FAL_LEAKY_FDB_CTRL == ctrl_mode) - { - data = 1; - } - else - { - return SW_BAD_PARAM; - } - - HSL_REG_FIELD_SET(rv, dev_id, FLOOD_MASK, 0, ARL_MUL_LEAKY, - (a_uint8_t *) (&data), sizeof (a_uint32_t)); - return rv; -} - -static sw_error_t -_shiva_mc_leaky_mode_get(a_uint32_t dev_id, - fal_leaky_ctrl_mode_t *ctrl_mode) -{ - a_uint32_t data = 0; - sw_error_t rv; - - HSL_DEV_ID_CHECK(dev_id); - - HSL_REG_FIELD_GET(rv, dev_id, FLOOD_MASK, 0, ARL_MUL_LEAKY, - (a_uint8_t *) (&data), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - - if (1 == data) - { - *ctrl_mode = FAL_LEAKY_FDB_CTRL; - } - else - { - *ctrl_mode = FAL_LEAKY_PORT_CTRL; - } - - return SW_OK; -} - -static sw_error_t -_shiva_port_arp_leaky_set(a_uint32_t dev_id, fal_port_t port_id, - a_bool_t enable) -{ - a_uint32_t data; - sw_error_t rv; - - HSL_DEV_ID_CHECK(dev_id); - - if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU)) - { - return SW_BAD_PARAM; - } - - if (A_TRUE == enable) - { - data = 1; - } - else if (A_FALSE == enable) - { - data = 0; - } - else - { - return SW_BAD_PARAM; - } - - HSL_REG_FIELD_SET(rv, dev_id, PORT_CTL, port_id, ARP_LEAKY_EN, - (a_uint8_t *) (&data), sizeof (a_uint32_t)); - return rv; -} - -static sw_error_t -_shiva_port_arp_leaky_get(a_uint32_t dev_id, fal_port_t port_id, - a_bool_t *enable) -{ - a_uint32_t data = 0; - sw_error_t rv; - - HSL_DEV_ID_CHECK(dev_id); - - if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU)) - { - return SW_BAD_PARAM; - } - - HSL_REG_FIELD_GET(rv, dev_id, PORT_CTL, port_id, ARP_LEAKY_EN, - (a_uint8_t *) (&data), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - - if (1 == data) - { - *enable = A_TRUE; - } - else - { - *enable = A_FALSE; - } - - return SW_OK; -} - -static sw_error_t -_shiva_port_uc_leaky_set(a_uint32_t dev_id, fal_port_t port_id, - a_bool_t enable) -{ - a_uint32_t data; - sw_error_t rv; - - HSL_DEV_ID_CHECK(dev_id); - - if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU)) - { - return SW_BAD_PARAM; - } - - if (A_TRUE == enable) - { - data = 1; - } - else if (A_FALSE == enable) - { - data = 0; - } - else - { - return SW_BAD_PARAM; - } - - HSL_REG_FIELD_SET(rv, dev_id, PORT_BASE_VLAN, port_id, UNI_LEAKY_EN, - (a_uint8_t *) (&data), sizeof (a_uint32_t)); - return rv; -} - -static sw_error_t -_shiva_port_uc_leaky_get(a_uint32_t dev_id, fal_port_t port_id, - a_bool_t *enable) -{ - a_uint32_t data = 0; - sw_error_t rv; - - HSL_DEV_ID_CHECK(dev_id); - - if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU)) - { - return SW_BAD_PARAM; - } - - HSL_REG_FIELD_GET(rv, dev_id, PORT_BASE_VLAN, port_id, UNI_LEAKY_EN, - (a_uint8_t *) (&data), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - - if (1 == data) - { - *enable = A_TRUE; - } - else - { - *enable = A_FALSE; - } - - return SW_OK; -} - -static sw_error_t -_shiva_port_mc_leaky_set(a_uint32_t dev_id, fal_port_t port_id, - a_bool_t enable) -{ - a_uint32_t data; - sw_error_t rv; - - HSL_DEV_ID_CHECK(dev_id); - - if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU)) - { - return SW_BAD_PARAM; - } - - if (A_TRUE == enable) - { - data = 1; - } - else if (A_FALSE == enable) - { - data = 0; - } - else - { - return SW_BAD_PARAM; - } - - HSL_REG_FIELD_SET(rv, dev_id, PORT_BASE_VLAN, port_id, MUL_LEAKY_EN, - (a_uint8_t *) (&data), sizeof (a_uint32_t)); - return rv; -} - -static sw_error_t -_shiva_port_mc_leaky_get(a_uint32_t dev_id, fal_port_t port_id, - a_bool_t *enable) -{ - a_uint32_t data = 0; - sw_error_t rv; - - HSL_DEV_ID_CHECK(dev_id); - - if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU)) - { - return SW_BAD_PARAM; - } - - HSL_REG_FIELD_GET(rv, dev_id, PORT_BASE_VLAN, port_id, MUL_LEAKY_EN, - (a_uint8_t *) (&data), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - - if (1 == data) - { - *enable = A_TRUE; - } - else - { - *enable = A_FALSE; - } - - return SW_OK; -} - -/** -* @brief Set unicast packets leaky control mode on a particular device. -* @param[in] dev_id device id -* @param[in] ctrl_mode leaky control mode -* @return SW_OK or error code -*/ -HSL_LOCAL sw_error_t -shiva_uc_leaky_mode_set(a_uint32_t dev_id, - fal_leaky_ctrl_mode_t ctrl_mode) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _shiva_uc_leaky_mode_set(dev_id, ctrl_mode); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Get unicast packets leaky control mode on a particular device. - * @param[in] dev_id device id - * @param[out] ctrl_mode leaky control mode - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -shiva_uc_leaky_mode_get(a_uint32_t dev_id, - fal_leaky_ctrl_mode_t *ctrl_mode) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _shiva_uc_leaky_mode_get(dev_id, ctrl_mode); - HSL_API_UNLOCK; - return rv; -} - -/** -* @brief Set multicast packets leaky control mode on a particular device. -* @param[in] dev_id device id -* @param[in] ctrl_mode leaky control mode -* @return SW_OK or error code -*/ -HSL_LOCAL sw_error_t -shiva_mc_leaky_mode_set(a_uint32_t dev_id, - fal_leaky_ctrl_mode_t ctrl_mode) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _shiva_mc_leaky_mode_set(dev_id, ctrl_mode); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Get multicast packets leaky control mode on a particular device. - * @param[in] dev_id device id - * @param[out] ctrl_mode leaky control mode - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -shiva_mc_leaky_mode_get(a_uint32_t dev_id, - fal_leaky_ctrl_mode_t *ctrl_mode) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _shiva_mc_leaky_mode_get(dev_id, ctrl_mode); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Set arp packets leaky status on a particular port. - * @param[in] dev_id device id - * @param[in] enable A_TRUE or A_FALSE - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -shiva_port_arp_leaky_set(a_uint32_t dev_id, fal_port_t port_id, - a_bool_t enable) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _shiva_port_arp_leaky_set(dev_id, port_id, enable); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Get arp packets leaky status on a particular port. - * @param[in] dev_id device id - * @param[out] enable A_TRUE or A_FALSE - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -shiva_port_arp_leaky_get(a_uint32_t dev_id, fal_port_t port_id, - a_bool_t *enable) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _shiva_port_arp_leaky_get(dev_id, port_id, enable); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Set unicast packets leaky status on a particular port. - * @param[in] dev_id device id - * @param[in] enable A_TRUE or A_FALSE - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -shiva_port_uc_leaky_set(a_uint32_t dev_id, fal_port_t port_id, - a_bool_t enable) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _shiva_port_uc_leaky_set(dev_id, port_id, enable); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Get unicast packets leaky status on a particular port. - * @param[in] dev_id device id - * @param[out] enable A_TRUE or A_FALSE - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -shiva_port_uc_leaky_get(a_uint32_t dev_id, fal_port_t port_id, - a_bool_t *enable) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _shiva_port_uc_leaky_get(dev_id, port_id, enable); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Set multicast packets leaky status on a particular port. - * @param[in] dev_id device id - * @param[in] enable A_TRUE or A_FALSE - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -shiva_port_mc_leaky_set(a_uint32_t dev_id, fal_port_t port_id, - a_bool_t enable) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _shiva_port_mc_leaky_set(dev_id, port_id, enable); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Get multicast packets leaky status on a particular port. - * @param[in] dev_id device id - * @param[out] enable A_TRUE or A_FALSE - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -shiva_port_mc_leaky_get(a_uint32_t dev_id, fal_port_t port_id, - a_bool_t *enable) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _shiva_port_mc_leaky_get(dev_id, port_id, enable); - HSL_API_UNLOCK; - return rv; -} - -sw_error_t -shiva_leaky_init(a_uint32_t dev_id) -{ - HSL_DEV_ID_CHECK(dev_id); - -#ifndef HSL_STANDALONG - { - hsl_api_t *p_api; - - SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id)); - p_api->uc_leaky_mode_set = shiva_uc_leaky_mode_set; - p_api->uc_leaky_mode_get = shiva_uc_leaky_mode_get; - p_api->mc_leaky_mode_set = shiva_mc_leaky_mode_set; - p_api->mc_leaky_mode_get = shiva_mc_leaky_mode_get; - p_api->port_arp_leaky_set = shiva_port_arp_leaky_set; - p_api->port_arp_leaky_get = shiva_port_arp_leaky_get; - p_api->port_uc_leaky_set = shiva_port_uc_leaky_set; - p_api->port_uc_leaky_get = shiva_port_uc_leaky_get; - p_api->port_mc_leaky_set = shiva_port_mc_leaky_set; - p_api->port_mc_leaky_get = shiva_port_mc_leaky_get; - } -#endif - - return SW_OK; -} - -/** - * @} - */ - diff --git a/feeds/ipq807x/qca-ssdk/src/src/hsl/shiva/shiva_led.c b/feeds/ipq807x/qca-ssdk/src/src/hsl/shiva/shiva_led.c deleted file mode 100755 index 06bcd3180..000000000 --- a/feeds/ipq807x/qca-ssdk/src/src/hsl/shiva/shiva_led.c +++ /dev/null @@ -1,428 +0,0 @@ -/* - * Copyright (c) 2012, 2016 The Linux Foundation. All rights reserved. - * Permission to use, copy, modify, and/or distribute this software for - * any purpose with or without fee is hereby granted, provided that the - * above copyright notice and this permission notice appear in all copies. - * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES - * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR - * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES - * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN - * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT - * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. - */ - - -/** - * @defgroup shiva_led SHIVA_LED - * @{ - */ -#include "sw.h" -#include "hsl.h" -#include "hsl_dev.h" -#include "shiva_led.h" -#include "shiva_reg.h" - -#define MAX_LED_PATTERN_ID 1 -#define LED_PATTERN_ADDR 0xB0 - -static sw_error_t -_shiva_led_ctrl_pattern_set(a_uint32_t dev_id, led_pattern_group_t group, - led_pattern_id_t id, led_ctrl_pattern_t * pattern) -{ - a_uint32_t data = 0, reg = 0, mode; - a_uint32_t addr; - sw_error_t rv; - - HSL_DEV_ID_CHECK(dev_id); - - if (group >= LED_GROUP_BUTT) - { - return SW_BAD_PARAM; - } - - if (id > MAX_LED_PATTERN_ID) - { - return SW_BAD_PARAM; - } - - if ((LED_MAC_PORT_GROUP == group) && (0 != id)) - { - return SW_BAD_PARAM; - } - - if (LED_MAC_PORT_GROUP == group) - { - addr = LED_PATTERN_ADDR + 8; - } - else - { - addr = LED_PATTERN_ADDR + (id << 2); - } - - if (LED_ALWAYS_OFF == pattern->mode) - { - mode = 0; - } - else if (LED_ALWAYS_BLINK == pattern->mode) - { - mode = 1; - } - else if (LED_ALWAYS_ON == pattern->mode) - { - mode = 2; - } - else if (LED_PATTERN_MAP_EN == pattern->mode) - { - mode = 3; - } - else - { - return SW_BAD_PARAM; - } - SW_SET_REG_BY_FIELD(LED_CTRL, PATTERN_EN, mode, data); - - if (pattern->map & (1 << FULL_DUPLEX_LIGHT_EN)) - { - SW_SET_REG_BY_FIELD(LED_CTRL, FULL_LIGHT_EN, 1, data); - } - - if (pattern->map & (1 << HALF_DUPLEX_LIGHT_EN)) - { - SW_SET_REG_BY_FIELD(LED_CTRL, HALF_LIGHT_EN, 1, data); - } - - if (pattern->map & (1 << POWER_ON_LIGHT_EN)) - { - SW_SET_REG_BY_FIELD(LED_CTRL, POWERON_LIGHT_EN, 1, data); - } - - if (pattern->map & (1 << LINK_1000M_LIGHT_EN)) - { - SW_SET_REG_BY_FIELD(LED_CTRL, GE_LIGHT_EN, 1, data); - } - - if (pattern->map & (1 << LINK_100M_LIGHT_EN)) - { - SW_SET_REG_BY_FIELD(LED_CTRL, FE_LIGHT_EN, 1, data); - } - - if (pattern->map & (1 << LINK_10M_LIGHT_EN)) - { - SW_SET_REG_BY_FIELD(LED_CTRL, ETH_LIGHT_EN, 1, data); - } - - if (pattern->map & (1 << COLLISION_BLINK_EN)) - { - SW_SET_REG_BY_FIELD(LED_CTRL, COL_BLINK_EN, 1, data); - } - - if (pattern->map & (1 << RX_TRAFFIC_BLINK_EN)) - { - SW_SET_REG_BY_FIELD(LED_CTRL, RX_BLINK_EN, 1, data); - } - - if (pattern->map & (1 << TX_TRAFFIC_BLINK_EN)) - { - SW_SET_REG_BY_FIELD(LED_CTRL, TX_BLINK_EN, 1, data); - } - - if (pattern->map & (1 << LINKUP_OVERRIDE_EN)) - { - SW_SET_REG_BY_FIELD(LED_CTRL, LINKUP_OVER_EN, 1, data); - } - else - { - SW_SET_REG_BY_FIELD(LED_CTRL, LINKUP_OVER_EN, 0, data); - } - - if (LED_BLINK_2HZ == pattern->freq) - { - SW_SET_REG_BY_FIELD(LED_CTRL, BLINK_FREQ, 0, data); - } - else if (LED_BLINK_4HZ == pattern->freq) - { - SW_SET_REG_BY_FIELD(LED_CTRL, BLINK_FREQ, 1, data); - } - else if (LED_BLINK_8HZ == pattern->freq) - { - SW_SET_REG_BY_FIELD(LED_CTRL, BLINK_FREQ, 2, data); - } - else if (LED_BLINK_TXRX == pattern->freq) - { - SW_SET_REG_BY_FIELD(LED_CTRL, BLINK_FREQ, 3, data); - } - else - { - return SW_BAD_PARAM; - } - - HSL_REG_ENTRY_GEN_GET(rv, dev_id, addr, sizeof (a_uint32_t), - (a_uint8_t *) (®), - sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - - if (LED_WAN_PORT_GROUP == group) - { - reg &= 0xffff; - reg |= (data << 16); - } - else - { - reg &= 0xffff0000; - reg |= data; - } - - HSL_REG_ENTRY_GEN_SET(rv, dev_id, addr, sizeof (a_uint32_t), - (a_uint8_t *) (®), - sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - - if (LED_WAN_PORT_GROUP == group) - { - return SW_OK; - } - - HSL_REG_ENTRY_GET(rv, dev_id, LED_PATTERN, 0, - (a_uint8_t *) (&data), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - - if (LED_LAN_PORT_GROUP == group) - { - if (id) - { - SW_SET_REG_BY_FIELD(LED_PATTERN, P3L1_MODE, mode, data); - SW_SET_REG_BY_FIELD(LED_PATTERN, P2L1_MODE, mode, data); - SW_SET_REG_BY_FIELD(LED_PATTERN, P1L1_MODE, mode, data); - } - else - { - SW_SET_REG_BY_FIELD(LED_PATTERN, P3L0_MODE, mode, data); - SW_SET_REG_BY_FIELD(LED_PATTERN, P2L0_MODE, mode, data); - SW_SET_REG_BY_FIELD(LED_PATTERN, P1L0_MODE, mode, data); - } - } - else - { - SW_SET_REG_BY_FIELD(LED_PATTERN, M6_MODE, mode, data); - SW_SET_REG_BY_FIELD(LED_PATTERN, M5_MODE, mode, data); - } - - HSL_REG_ENTRY_SET(rv, dev_id, LED_PATTERN, 0, - (a_uint8_t *) (&data), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - - return SW_OK; -} - -static sw_error_t -_shiva_led_ctrl_pattern_get(a_uint32_t dev_id, led_pattern_group_t group, - led_pattern_id_t id, led_ctrl_pattern_t * pattern) -{ - a_uint32_t data = 0, reg = 0, tmp; - a_uint32_t addr; - sw_error_t rv; - - HSL_DEV_ID_CHECK(dev_id); - - if (group >= LED_GROUP_BUTT) - { - return SW_BAD_PARAM; - } - - if (id > MAX_LED_PATTERN_ID) - { - return SW_BAD_PARAM; - } - - if ((LED_MAC_PORT_GROUP == group) && (0 != id)) - { - return SW_BAD_PARAM; - } - - aos_mem_zero(pattern, sizeof(led_ctrl_pattern_t)); - - if (LED_MAC_PORT_GROUP == group) - { - addr = LED_PATTERN_ADDR + 8; - } - else - { - addr = LED_PATTERN_ADDR + (id << 2); - } - - HSL_REG_ENTRY_GEN_GET(rv, dev_id, addr, sizeof (a_uint32_t), - (a_uint8_t *) (®), - sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - - if (LED_WAN_PORT_GROUP == group) - { - data = (reg >> 16) & 0xffff; - } - else - { - data = reg & 0xffff; - } - - SW_GET_FIELD_BY_REG(LED_CTRL, PATTERN_EN, tmp, data); - if (0 == tmp) - { - pattern->mode = LED_ALWAYS_OFF; - } - else if (1 == tmp) - { - pattern->mode = LED_ALWAYS_BLINK; - } - else if (2 == tmp) - { - pattern->mode = LED_ALWAYS_ON; - } - else - { - pattern->mode = LED_PATTERN_MAP_EN; - } - - SW_GET_FIELD_BY_REG(LED_CTRL, FULL_LIGHT_EN, tmp, data); - if (1 == tmp) - { - pattern->map |= (1 << FULL_DUPLEX_LIGHT_EN); - } - - SW_GET_FIELD_BY_REG(LED_CTRL, HALF_LIGHT_EN, tmp, data); - if (1 == tmp) - { - pattern->map |= (1 << HALF_DUPLEX_LIGHT_EN); - } - - SW_GET_FIELD_BY_REG(LED_CTRL, POWERON_LIGHT_EN, tmp, data); - if (1 == tmp) - { - pattern->map |= (1 << POWER_ON_LIGHT_EN); - } - - SW_GET_FIELD_BY_REG(LED_CTRL, GE_LIGHT_EN, tmp, data); - if (1 == tmp) - { - pattern->map |= (1 << LINK_1000M_LIGHT_EN); - } - - SW_GET_FIELD_BY_REG(LED_CTRL, FE_LIGHT_EN, tmp, data); - if (1 == tmp) - { - pattern->map |= (1 << LINK_100M_LIGHT_EN); - } - - SW_GET_FIELD_BY_REG(LED_CTRL, ETH_LIGHT_EN, tmp, data); - if (1 == tmp) - { - pattern->map |= (1 << LINK_10M_LIGHT_EN); - } - - SW_GET_FIELD_BY_REG(LED_CTRL, COL_BLINK_EN, tmp, data); - if (1 == tmp) - { - pattern->map |= (1 << COLLISION_BLINK_EN); - } - - SW_GET_FIELD_BY_REG(LED_CTRL, RX_BLINK_EN, tmp, data); - if (1 == tmp) - { - pattern->map |= (1 << RX_TRAFFIC_BLINK_EN); - } - - SW_GET_FIELD_BY_REG(LED_CTRL, TX_BLINK_EN, tmp, data); - if (1 == tmp) - { - pattern->map |= (1 << TX_TRAFFIC_BLINK_EN); - } - - SW_GET_FIELD_BY_REG(LED_CTRL, LINKUP_OVER_EN, tmp, data); - if (1 == tmp) - { - pattern->map |= (1 << LINKUP_OVERRIDE_EN); - } - - SW_GET_FIELD_BY_REG(LED_CTRL, BLINK_FREQ, tmp, data); - if (0 == tmp) - { - pattern->freq = LED_BLINK_2HZ; - } - else if (1 == tmp) - { - pattern->freq = LED_BLINK_4HZ; - } - else if (2 == tmp) - { - pattern->freq = LED_BLINK_8HZ; - } - else - { - pattern->freq = LED_BLINK_TXRX; - } - - return SW_OK; -} - -/** -* @brief Set led control pattern on a particular device. -* @param[in] dev_id device id -* @param[in] group pattern group, lan or wan -* @param[in] id pattern id -* @param[in] pattern led control pattern -* @return SW_OK or error code -*/ -HSL_LOCAL sw_error_t -shiva_led_ctrl_pattern_set(a_uint32_t dev_id, led_pattern_group_t group, - led_pattern_id_t id, led_ctrl_pattern_t * pattern) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _shiva_led_ctrl_pattern_set(dev_id, group, id, pattern); - HSL_API_UNLOCK; - return rv; -} - -/** -* @brief Get led control pattern on a particular device. -* @param[in] dev_id device id -* @param[in] group pattern group, lan or wan -* @param[in] id pattern id -* @param[out] pattern led control pattern -* @return SW_OK or error code -*/ -HSL_LOCAL sw_error_t -shiva_led_ctrl_pattern_get(a_uint32_t dev_id, led_pattern_group_t group, - led_pattern_id_t id, led_ctrl_pattern_t * pattern) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _shiva_led_ctrl_pattern_get(dev_id, group, id, pattern); - HSL_API_UNLOCK; - return rv; -} - -sw_error_t -shiva_led_init(a_uint32_t dev_id) -{ - HSL_DEV_ID_CHECK(dev_id); - -#ifndef HSL_STANDALONG - { - hsl_api_t *p_api; - - SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id)); - p_api->led_ctrl_pattern_set = shiva_led_ctrl_pattern_set; - p_api->led_ctrl_pattern_get = shiva_led_ctrl_pattern_get; - } -#endif - - return SW_OK; -} - -/** - * @} - */ - diff --git a/feeds/ipq807x/qca-ssdk/src/src/hsl/shiva/shiva_mib.c b/feeds/ipq807x/qca-ssdk/src/src/hsl/shiva/shiva_mib.c deleted file mode 100755 index 0122e561d..000000000 --- a/feeds/ipq807x/qca-ssdk/src/src/hsl/shiva/shiva_mib.c +++ /dev/null @@ -1,663 +0,0 @@ -/* - * Copyright (c) 2012, 2016 The Linux Foundation. All rights reserved. - * Permission to use, copy, modify, and/or distribute this software for - * any purpose with or without fee is hereby granted, provided that the - * above copyright notice and this permission notice appear in all copies. - * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES - * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR - * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES - * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN - * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT - * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. - */ - - -/** - * @defgroup shiva_mib SHIVA_MIB - * @{ - */ -#include "sw.h" -#include "hsl.h" -#include "hsl_dev.h" -#include "hsl_port_prop.h" -#include "shiva_mib.h" -#include "shiva_reg.h" - -static sw_error_t -_shiva_get_mib_info(a_uint32_t dev_id, fal_port_t port_id, - fal_mib_info_t * mib_info) -{ - a_uint32_t val = 0; - sw_error_t rv; - - HSL_DEV_ID_CHECK(dev_id); - - if (A_FALSE == hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU)) - { - return SW_OUT_OF_RANGE; - } - - HSL_REG_ENTRY_GET(rv, dev_id, MIB_RXBROAD, port_id, - (a_uint8_t *) (&val), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - mib_info->RxBroad = val; - - HSL_REG_ENTRY_GET(rv, dev_id, MIB_RXPAUSE, port_id, - (a_uint8_t *) (&val), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - mib_info->RxPause = val; - - HSL_REG_ENTRY_GET(rv, dev_id, MIB_RXMULTI, port_id, - (a_uint8_t *) (&val), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - mib_info->RxMulti = val; - - HSL_REG_ENTRY_GET(rv, dev_id, MIB_RXFCSERR, port_id, - (a_uint8_t *) (&val), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - mib_info->RxFcsErr = val; - - HSL_REG_ENTRY_GET(rv, dev_id, MIB_RXALLIGNERR, port_id, - (a_uint8_t *) (&val), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - mib_info->RxAllignErr = val; - - HSL_REG_ENTRY_GET(rv, dev_id, MIB_RXRUNT, port_id, (a_uint8_t *) (&val), - sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - mib_info->RxRunt = val; - - HSL_REG_ENTRY_GET(rv, dev_id, MIB_RXFRAGMENT, port_id, - (a_uint8_t *) (&val), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - mib_info->RxFragment = val; - - HSL_REG_ENTRY_GET(rv, dev_id, MIB_RX64BYTE, port_id, - (a_uint8_t *) (&val), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - mib_info->Rx64Byte = val; - - HSL_REG_ENTRY_GET(rv, dev_id, MIB_RX128BYTE, port_id, - (a_uint8_t *) (&val), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - mib_info->Rx128Byte = val; - - HSL_REG_ENTRY_GET(rv, dev_id, MIB_RX256BYTE, port_id, - (a_uint8_t *) (&val), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - mib_info->Rx256Byte = val; - - HSL_REG_ENTRY_GET(rv, dev_id, MIB_RX512BYTE, port_id, - (a_uint8_t *) (&val), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - mib_info->Rx512Byte = val; - - HSL_REG_ENTRY_GET(rv, dev_id, MIB_RX1024BYTE, port_id, - (a_uint8_t *) (&val), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - mib_info->Rx1024Byte = val; - - HSL_REG_ENTRY_GET(rv, dev_id, MIB_RX1518BYTE, port_id, - (a_uint8_t *) (&val), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - mib_info->Rx1518Byte = val; - - HSL_REG_ENTRY_GET(rv, dev_id, MIB_RXMAXBYTE, port_id, - (a_uint8_t *) (&val), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - mib_info->RxMaxByte = val; - - HSL_REG_ENTRY_GET(rv, dev_id, MIB_RXTOOLONG, port_id, - (a_uint8_t *) (&val), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - mib_info->RxTooLong = val; - - HSL_REG_ENTRY_GET(rv, dev_id, MIB_RXGOODBYTE_LO, port_id, - (a_uint8_t *) (&val), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - mib_info->RxGoodByte_lo = val; - - HSL_REG_ENTRY_GET(rv, dev_id, MIB_RXGOODBYTE_HI, port_id, - (a_uint8_t *) (&val), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - mib_info->RxGoodByte_hi = val; - - HSL_REG_ENTRY_GET(rv, dev_id, MIB_RXBADBYTE_LO, port_id, - (a_uint8_t *) (&val), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - mib_info->RxBadByte_lo = val; - - HSL_REG_ENTRY_GET(rv, dev_id, MIB_RXBADBYTE_HI, port_id, - (a_uint8_t *) (&val), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - mib_info->RxBadByte_hi = val; - - HSL_REG_ENTRY_GET(rv, dev_id, MIB_RXOVERFLOW, port_id, - (a_uint8_t *) (&val), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - mib_info->RxOverFlow = val; - - HSL_REG_ENTRY_GET(rv, dev_id, MIB_FILTERED, port_id, - (a_uint8_t *) (&val), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - mib_info->Filtered = val; - - HSL_REG_ENTRY_GET(rv, dev_id, MIB_TXBROAD, port_id, (a_uint8_t *) (&val), - sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - mib_info->TxBroad = val; - - HSL_REG_ENTRY_GET(rv, dev_id, MIB_TXPAUSE, port_id, (a_uint8_t *) (&val), - sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - mib_info->TxPause = val; - - HSL_REG_ENTRY_GET(rv, dev_id, MIB_TXMULTI, port_id, (a_uint8_t *) (&val), - sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - mib_info->TxMulti = val; - - HSL_REG_ENTRY_GET(rv, dev_id, MIB_TXUNDERRUN, port_id, - (a_uint8_t *) (&val), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - mib_info->TxUnderRun = val; - - HSL_REG_ENTRY_GET(rv, dev_id, MIB_TX64BYTE, port_id, - (a_uint8_t *) (&val), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - mib_info->Tx64Byte = val; - - HSL_REG_ENTRY_GET(rv, dev_id, MIB_TX128BYTE, port_id, - (a_uint8_t *) (&val), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - mib_info->Tx128Byte = val; - - HSL_REG_ENTRY_GET(rv, dev_id, MIB_TX256BYTE, port_id, - (a_uint8_t *) (&val), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - mib_info->Tx256Byte = val; - - HSL_REG_ENTRY_GET(rv, dev_id, MIB_TX512BYTE, port_id, - (a_uint8_t *) (&val), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - mib_info->Tx512Byte = val; - - HSL_REG_ENTRY_GET(rv, dev_id, MIB_TX1024BYTE, port_id, - (a_uint8_t *) (&val), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - mib_info->Tx1024Byte = val; - - HSL_REG_ENTRY_GET(rv, dev_id, MIB_TX1518BYTE, port_id, - (a_uint8_t *) (&val), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - mib_info->Tx1518Byte = val; - - HSL_REG_ENTRY_GET(rv, dev_id, MIB_TXMAXBYTE, port_id, - (a_uint8_t *) (&val), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - mib_info->TxMaxByte = val; - - HSL_REG_ENTRY_GET(rv, dev_id, MIB_TXOVERSIZE, port_id, - (a_uint8_t *) (&val), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - mib_info->TxOverSize = val; - - HSL_REG_ENTRY_GET(rv, dev_id, MIB_TXBYTE_LO, port_id, - (a_uint8_t *) (&val), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - mib_info->TxByte_lo = val; - - HSL_REG_ENTRY_GET(rv, dev_id, MIB_TXBYTE_HI, port_id, - (a_uint8_t *) (&val), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - mib_info->TxByte_hi = val; - - HSL_REG_ENTRY_GET(rv, dev_id, MIB_TXCOLLISION, port_id, - (a_uint8_t *) (&val), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - mib_info->TxCollision = val; - - HSL_REG_ENTRY_GET(rv, dev_id, MIB_TXABORTCOL, port_id, - (a_uint8_t *) (&val), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - mib_info->TxAbortCol = val; - - HSL_REG_ENTRY_GET(rv, dev_id, MIB_TXMULTICOL, port_id, - (a_uint8_t *) (&val), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - mib_info->TxMultiCol = val; - - HSL_REG_ENTRY_GET(rv, dev_id, MIB_TXSINGALCOL, port_id, - (a_uint8_t *) (&val), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - mib_info->TxSingalCol = val; - - HSL_REG_ENTRY_GET(rv, dev_id, MIB_TXEXCDEFER, port_id, - (a_uint8_t *) (&val), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - mib_info->TxExcDefer = val; - - HSL_REG_ENTRY_GET(rv, dev_id, MIB_TXDEFER, port_id, (a_uint8_t *) (&val), - sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - mib_info->TxDefer = val; - - HSL_REG_ENTRY_GET(rv, dev_id, MIB_TXLATECOL, port_id, - (a_uint8_t *) (&val), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - mib_info->TxLateCol = val; - - return SW_OK; -} - -static sw_error_t -_shiva_get_rx_mib_info(a_uint32_t dev_id, fal_port_t port_id, - fal_mib_info_t * mib_info) -{ - a_uint32_t val = 0; - sw_error_t rv; - - HSL_DEV_ID_CHECK(dev_id); - - if (A_FALSE == hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU)) - { - return SW_OUT_OF_RANGE; - } - - HSL_REG_ENTRY_GET(rv, dev_id, MIB_RXBROAD, port_id, - (a_uint8_t *) (&val), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - mib_info->RxBroad = val; - - HSL_REG_ENTRY_GET(rv, dev_id, MIB_RXPAUSE, port_id, - (a_uint8_t *) (&val), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - mib_info->RxPause = val; - - HSL_REG_ENTRY_GET(rv, dev_id, MIB_RXMULTI, port_id, - (a_uint8_t *) (&val), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - mib_info->RxMulti = val; - - HSL_REG_ENTRY_GET(rv, dev_id, MIB_RXFCSERR, port_id, - (a_uint8_t *) (&val), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - mib_info->RxFcsErr = val; - - HSL_REG_ENTRY_GET(rv, dev_id, MIB_RXALLIGNERR, port_id, - (a_uint8_t *) (&val), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - mib_info->RxAllignErr = val; - - HSL_REG_ENTRY_GET(rv, dev_id, MIB_RXRUNT, port_id, (a_uint8_t *) (&val), - sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - mib_info->RxRunt = val; - - HSL_REG_ENTRY_GET(rv, dev_id, MIB_RXFRAGMENT, port_id, - (a_uint8_t *) (&val), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - mib_info->RxFragment = val; - - HSL_REG_ENTRY_GET(rv, dev_id, MIB_RX64BYTE, port_id, - (a_uint8_t *) (&val), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - mib_info->Rx64Byte = val; - - HSL_REG_ENTRY_GET(rv, dev_id, MIB_RX128BYTE, port_id, - (a_uint8_t *) (&val), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - mib_info->Rx128Byte = val; - - HSL_REG_ENTRY_GET(rv, dev_id, MIB_RX256BYTE, port_id, - (a_uint8_t *) (&val), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - mib_info->Rx256Byte = val; - - HSL_REG_ENTRY_GET(rv, dev_id, MIB_RX512BYTE, port_id, - (a_uint8_t *) (&val), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - mib_info->Rx512Byte = val; - - HSL_REG_ENTRY_GET(rv, dev_id, MIB_RX1024BYTE, port_id, - (a_uint8_t *) (&val), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - mib_info->Rx1024Byte = val; - - HSL_REG_ENTRY_GET(rv, dev_id, MIB_RX1518BYTE, port_id, - (a_uint8_t *) (&val), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - mib_info->Rx1518Byte = val; - - HSL_REG_ENTRY_GET(rv, dev_id, MIB_RXMAXBYTE, port_id, - (a_uint8_t *) (&val), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - mib_info->RxMaxByte = val; - - HSL_REG_ENTRY_GET(rv, dev_id, MIB_RXTOOLONG, port_id, - (a_uint8_t *) (&val), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - mib_info->RxTooLong = val; - - HSL_REG_ENTRY_GET(rv, dev_id, MIB_RXGOODBYTE_LO, port_id, - (a_uint8_t *) (&val), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - mib_info->RxGoodByte_lo = val; - - HSL_REG_ENTRY_GET(rv, dev_id, MIB_RXGOODBYTE_HI, port_id, - (a_uint8_t *) (&val), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - mib_info->RxGoodByte_hi = val; - - HSL_REG_ENTRY_GET(rv, dev_id, MIB_RXBADBYTE_LO, port_id, - (a_uint8_t *) (&val), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - mib_info->RxBadByte_lo = val; - - HSL_REG_ENTRY_GET(rv, dev_id, MIB_RXBADBYTE_HI, port_id, - (a_uint8_t *) (&val), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - mib_info->RxBadByte_hi = val; - - HSL_REG_ENTRY_GET(rv, dev_id, MIB_RXOVERFLOW, port_id, - (a_uint8_t *) (&val), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - mib_info->RxOverFlow = val; - - HSL_REG_ENTRY_GET(rv, dev_id, MIB_FILTERED, port_id, - (a_uint8_t *) (&val), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - mib_info->Filtered = val; - - return SW_OK; -} - -static sw_error_t -_shiva_get_tx_mib_info(a_uint32_t dev_id, fal_port_t port_id, - fal_mib_info_t * mib_info) -{ - a_uint32_t val = 0; - sw_error_t rv; - - HSL_DEV_ID_CHECK(dev_id); - - if (A_FALSE == hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU)) - { - return SW_OUT_OF_RANGE; - } - - HSL_REG_ENTRY_GET(rv, dev_id, MIB_TXBROAD, port_id, (a_uint8_t *) (&val), - sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - mib_info->TxBroad = val; - - HSL_REG_ENTRY_GET(rv, dev_id, MIB_TXPAUSE, port_id, (a_uint8_t *) (&val), - sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - mib_info->TxPause = val; - - HSL_REG_ENTRY_GET(rv, dev_id, MIB_TXMULTI, port_id, (a_uint8_t *) (&val), - sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - mib_info->TxMulti = val; - - HSL_REG_ENTRY_GET(rv, dev_id, MIB_TXUNDERRUN, port_id, - (a_uint8_t *) (&val), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - mib_info->TxUnderRun = val; - - HSL_REG_ENTRY_GET(rv, dev_id, MIB_TX64BYTE, port_id, - (a_uint8_t *) (&val), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - mib_info->Tx64Byte = val; - - HSL_REG_ENTRY_GET(rv, dev_id, MIB_TX128BYTE, port_id, - (a_uint8_t *) (&val), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - mib_info->Tx128Byte = val; - - HSL_REG_ENTRY_GET(rv, dev_id, MIB_TX256BYTE, port_id, - (a_uint8_t *) (&val), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - mib_info->Tx256Byte = val; - - HSL_REG_ENTRY_GET(rv, dev_id, MIB_TX512BYTE, port_id, - (a_uint8_t *) (&val), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - mib_info->Tx512Byte = val; - - HSL_REG_ENTRY_GET(rv, dev_id, MIB_TX1024BYTE, port_id, - (a_uint8_t *) (&val), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - mib_info->Tx1024Byte = val; - - HSL_REG_ENTRY_GET(rv, dev_id, MIB_TX1518BYTE, port_id, - (a_uint8_t *) (&val), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - mib_info->Tx1518Byte = val; - - HSL_REG_ENTRY_GET(rv, dev_id, MIB_TXMAXBYTE, port_id, - (a_uint8_t *) (&val), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - mib_info->TxMaxByte = val; - - HSL_REG_ENTRY_GET(rv, dev_id, MIB_TXOVERSIZE, port_id, - (a_uint8_t *) (&val), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - mib_info->TxOverSize = val; - - HSL_REG_ENTRY_GET(rv, dev_id, MIB_TXBYTE_LO, port_id, - (a_uint8_t *) (&val), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - mib_info->TxByte_lo = val; - - HSL_REG_ENTRY_GET(rv, dev_id, MIB_TXBYTE_HI, port_id, - (a_uint8_t *) (&val), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - mib_info->TxByte_hi = val; - - HSL_REG_ENTRY_GET(rv, dev_id, MIB_TXCOLLISION, port_id, - (a_uint8_t *) (&val), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - mib_info->TxCollision = val; - - HSL_REG_ENTRY_GET(rv, dev_id, MIB_TXABORTCOL, port_id, - (a_uint8_t *) (&val), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - mib_info->TxAbortCol = val; - - HSL_REG_ENTRY_GET(rv, dev_id, MIB_TXMULTICOL, port_id, - (a_uint8_t *) (&val), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - mib_info->TxMultiCol = val; - - HSL_REG_ENTRY_GET(rv, dev_id, MIB_TXSINGALCOL, port_id, - (a_uint8_t *) (&val), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - mib_info->TxSingalCol = val; - - HSL_REG_ENTRY_GET(rv, dev_id, MIB_TXEXCDEFER, port_id, - (a_uint8_t *) (&val), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - mib_info->TxExcDefer = val; - - HSL_REG_ENTRY_GET(rv, dev_id, MIB_TXDEFER, port_id, (a_uint8_t *) (&val), - sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - mib_info->TxDefer = val; - - HSL_REG_ENTRY_GET(rv, dev_id, MIB_TXLATECOL, port_id, - (a_uint8_t *) (&val), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - mib_info->TxLateCol = val; - - return SW_OK; -} - -static sw_error_t -_shiva_mib_status_set(a_uint32_t dev_id, a_bool_t enable) -{ - sw_error_t rv; - a_uint32_t val; - - HSL_DEV_ID_CHECK(dev_id); - - if (A_TRUE == enable) - { - val = 1; - } - else if (A_FALSE == enable) - { - val = 0; - } - else - { - return SW_BAD_PARAM; - } - - HSL_REG_FIELD_SET(rv, dev_id, MIB_FUNC, 0, MIB_EN, - (a_uint8_t *) (&val), sizeof (a_uint32_t)); - return rv; -} - -static sw_error_t -_shiva_mib_status_get(a_uint32_t dev_id, a_bool_t * enable) -{ - sw_error_t rv; - a_uint32_t val = 0; - - HSL_DEV_ID_CHECK(dev_id); - - HSL_REG_FIELD_GET(rv, dev_id, MIB_FUNC, 0, MIB_EN, - (a_uint8_t *) (&val), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - - if (1 == val) - { - *enable = A_TRUE; - } - else - { - *enable = A_FALSE; - } - - return SW_OK; -} - -/** - * @brief Get mib infomation on particular port. - * @param[in] dev_id device id - * @param[in] port_id port id - * @param[out] mib_info mib infomation - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -shiva_get_mib_info(a_uint32_t dev_id, fal_port_t port_id, - fal_mib_info_t * mib_info) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _shiva_get_mib_info(dev_id, port_id, mib_info); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Get RX mib infomation on particular port. - * @param[in] dev_id device id - * @param[in] port_id port id - * @param[out] mib_info mib infomation - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -shiva_get_rx_mib_info(a_uint32_t dev_id, fal_port_t port_id, - fal_mib_info_t * mib_info) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _shiva_get_rx_mib_info(dev_id, port_id, mib_info); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Get TX mib infomation on particular port. - * @param[in] dev_id device id - * @param[in] port_id port id - * @param[out] mib_info mib infomation - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -shiva_get_tx_mib_info(a_uint32_t dev_id, fal_port_t port_id, - fal_mib_info_t * mib_info) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _shiva_get_tx_mib_info(dev_id, port_id, mib_info); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Set mib status on a particular device. - * @param[in] dev_id device id - * @param[in] enable A_TRUE or A_FALSE - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -shiva_mib_status_set(a_uint32_t dev_id, a_bool_t enable) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _shiva_mib_status_set(dev_id, enable); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Get mib status on a particular device. - * @param[in] dev_id device id - * @param[out] enable A_TRUE or A_FALSE - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -shiva_mib_status_get(a_uint32_t dev_id, a_bool_t * enable) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _shiva_mib_status_get(dev_id, enable); - HSL_API_UNLOCK; - return rv; -} - -sw_error_t -shiva_mib_init(a_uint32_t dev_id) -{ -#ifndef HSL_STANDALONG - hsl_api_t *p_api; -#endif - HSL_DEV_ID_CHECK(dev_id); - -#ifndef HSL_STANDALONG - SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id)); - - p_api->get_mib_info = shiva_get_mib_info; - p_api->get_rx_mib_info = shiva_get_rx_mib_info; - p_api->get_tx_mib_info = shiva_get_tx_mib_info; - p_api->mib_status_set = shiva_mib_status_set; - p_api->mib_status_get = shiva_mib_status_get; -#endif - - return SW_OK; -} - -/** - * @} - */ - diff --git a/feeds/ipq807x/qca-ssdk/src/src/hsl/shiva/shiva_mirror.c b/feeds/ipq807x/qca-ssdk/src/src/hsl/shiva/shiva_mirror.c deleted file mode 100755 index 07e05ec02..000000000 --- a/feeds/ipq807x/qca-ssdk/src/src/hsl/shiva/shiva_mirror.c +++ /dev/null @@ -1,317 +0,0 @@ -/* - * Copyright (c) 2012, 2016, The Linux Foundation. All rights reserved. - * Permission to use, copy, modify, and/or distribute this software for - * any purpose with or without fee is hereby granted, provided that the - * above copyright notice and this permission notice appear in all copies. - * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES - * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR - * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES - * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN - * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT - * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. - */ - - -/** - * @defgroup shiva_mirror SHIVA_MIRROR - * @{ - */ -#include "sw.h" -#include "hsl.h" -#include "hsl_dev.h" -#include "hsl_port_prop.h" -#include "shiva_mirror.h" -#include "shiva_reg.h" - -static sw_error_t -_shiva_mirr_analysis_port_set(a_uint32_t dev_id, fal_port_t port_id) -{ - sw_error_t rv; - a_uint32_t val; - - HSL_DEV_ID_CHECK(dev_id); - if (port_id != MIRROR_ANALYZER_NONE) { - if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU)) { - return SW_BAD_PARAM; - } - } - val = port_id; - HSL_REG_FIELD_SET(rv, dev_id, CPU_PORT, 0, MIRROR_PORT_NUM, - (a_uint8_t *) (&val), sizeof (a_uint32_t)); - return rv; -} - -static sw_error_t -_shiva_mirr_analysis_port_get(a_uint32_t dev_id, fal_port_t * port_id) -{ - sw_error_t rv; - a_uint32_t val = 0; - - HSL_DEV_ID_CHECK(dev_id); - - HSL_REG_FIELD_GET(rv, dev_id, CPU_PORT, 0, MIRROR_PORT_NUM, - (a_uint8_t *) (&val), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - - *port_id = val; - return SW_OK; -} - -static sw_error_t -_shiva_mirr_port_in_set(a_uint32_t dev_id, fal_port_t port_id, a_bool_t enable) -{ - sw_error_t rv; - a_uint32_t val; - - HSL_DEV_ID_CHECK(dev_id); - - if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU)) - { - return SW_BAD_PARAM; - } - - if (A_TRUE == enable) - { - val = 1; - } - else if (A_FALSE == enable) - { - val = 0; - } - else - { - return SW_BAD_PARAM; - } - - HSL_REG_FIELD_SET(rv, dev_id, PORT_CTL, port_id, ING_MIRROR_EN, - (a_uint8_t *) (&val), sizeof (a_uint32_t)); - return rv; -} - -static sw_error_t -_shiva_mirr_port_in_get(a_uint32_t dev_id, fal_port_t port_id, - a_bool_t * enable) -{ - sw_error_t rv; - a_uint32_t val = 0; - - HSL_DEV_ID_CHECK(dev_id); - - if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU)) - { - return SW_BAD_PARAM; - } - - HSL_REG_FIELD_GET(rv, dev_id, PORT_CTL, port_id, ING_MIRROR_EN, - (a_uint8_t *) (&val), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - - if (1 == val) - { - *enable = A_TRUE; - } - else - { - *enable = A_FALSE; - } - - return SW_OK; -} - -static sw_error_t -_shiva_mirr_port_eg_set(a_uint32_t dev_id, fal_port_t port_id, a_bool_t enable) -{ - sw_error_t rv; - a_uint32_t val; - - HSL_DEV_ID_CHECK(dev_id); - - if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU)) - { - return SW_BAD_PARAM; - } - - if (A_TRUE == enable) - { - val = 1; - } - else if (A_FALSE == enable) - { - val = 0; - } - else - { - return SW_BAD_PARAM; - } - - HSL_REG_FIELD_SET(rv, dev_id, PORT_CTL, port_id, EG_MIRROR_EN, - (a_uint8_t *) (&val), sizeof (a_uint32_t)); - return rv; -} - -static sw_error_t -_shiva_mirr_port_eg_get(a_uint32_t dev_id, fal_port_t port_id, a_bool_t * enable) -{ - sw_error_t rv; - a_uint32_t val = 0; - - HSL_DEV_ID_CHECK(dev_id); - - if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU)) - { - return SW_BAD_PARAM; - } - - HSL_REG_FIELD_GET(rv, dev_id, PORT_CTL, port_id, EG_MIRROR_EN, - (a_uint8_t *) (&val), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - - if (1 == val) - { - *enable = A_TRUE; - } - else - { - *enable = A_FALSE; - } - - return SW_OK; -} - -/** - * @details Comments: - * The analysis port works for both ingress and egress mirror. - * @brief Set mirror analyzer port on particular a device. - * @param[in] dev_id device id - * @param[in] port_id port id - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -shiva_mirr_analysis_port_set(a_uint32_t dev_id, fal_port_t port_id) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _shiva_mirr_analysis_port_set(dev_id, port_id); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Get mirror analysis port on particular a device. - * @param[in] dev_id device id - * @param[out] port_id port id - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -shiva_mirr_analysis_port_get(a_uint32_t dev_id, fal_port_t * port_id) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _shiva_mirr_analysis_port_get(dev_id, port_id); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Set ingress mirror status on particular a port. - * @param[in] dev_id device id - * @param[in] port_id port id - * @param[in] enable A_TRUE or A_FALSE - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -shiva_mirr_port_in_set(a_uint32_t dev_id, fal_port_t port_id, a_bool_t enable) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _shiva_mirr_port_in_set(dev_id, port_id, enable); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Get ingress mirror status on particular a port. - * @param[in] dev_id device id - * @param[in] port_id port id - * @param[out] enable A_TRUE or A_FALSE - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -shiva_mirr_port_in_get(a_uint32_t dev_id, fal_port_t port_id, - a_bool_t * enable) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _shiva_mirr_port_in_get(dev_id, port_id, enable); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Set egress mirror status on a particular port. - * @param[in] dev_id device id - * @param[in] port_id port id - * @param[in] enable A_TRUE or A_FALSE - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -shiva_mirr_port_eg_set(a_uint32_t dev_id, fal_port_t port_id, a_bool_t enable) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _shiva_mirr_port_eg_set(dev_id, port_id, enable); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Get egress mirror status on a particular port. - * @param[in] dev_id device id - * @param[in] port_id port id - * @param[out] enable A_TRUE or A_FALSE - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -shiva_mirr_port_eg_get(a_uint32_t dev_id, fal_port_t port_id, a_bool_t * enable) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _shiva_mirr_port_eg_get(dev_id, port_id, enable); - HSL_API_UNLOCK; - return rv; -} - -sw_error_t -shiva_mirr_init(a_uint32_t dev_id) -{ - HSL_DEV_ID_CHECK(dev_id); - -#ifndef HSL_STANDALONG - { - hsl_api_t *p_api; - - SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id)); - - p_api->mirr_analysis_port_set = shiva_mirr_analysis_port_set; - p_api->mirr_analysis_port_get = shiva_mirr_analysis_port_get; - p_api->mirr_port_in_set = shiva_mirr_port_in_set; - p_api->mirr_port_in_get = shiva_mirr_port_in_get; - p_api->mirr_port_eg_set = shiva_mirr_port_eg_set; - p_api->mirr_port_eg_get = shiva_mirr_port_eg_get; - } -#endif - - return SW_OK; -} - -/** - * @} - */ - diff --git a/feeds/ipq807x/qca-ssdk/src/src/hsl/shiva/shiva_misc.c b/feeds/ipq807x/qca-ssdk/src/src/hsl/shiva/shiva_misc.c deleted file mode 100755 index f5793a268..000000000 --- a/feeds/ipq807x/qca-ssdk/src/src/hsl/shiva/shiva_misc.c +++ /dev/null @@ -1,1749 +0,0 @@ -/* - * Copyright (c) 2012, 2016, The Linux Foundation. All rights reserved. - * Permission to use, copy, modify, and/or distribute this software for - * any purpose with or without fee is hereby granted, provided that the - * above copyright notice and this permission notice appear in all copies. - * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES - * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR - * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES - * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN - * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT - * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. - */ - - -/** - * @defgroup shiva_misc SHIVA_MISC - * @{ - */ -#include "sw.h" -#include "hsl.h" -#include "hsl_dev.h" -#include "hsl_port_prop.h" -#include "shiva_misc.h" -#include "shiva_reg.h" - -#define SHIVA_MAX_FRMAE_SIZE 9216 - -static sw_error_t -_shiva_arp_status_set(a_uint32_t dev_id, a_bool_t enable) -{ - a_uint32_t data; - sw_error_t rv; - - HSL_DEV_ID_CHECK(dev_id); - - if (A_TRUE == enable) - { - data = 1; - } - else if (A_FALSE == enable) - { - data = 0; - } - else - { - return SW_BAD_PARAM; - } - - HSL_REG_FIELD_SET(rv, dev_id, QM_CTL, 0, ARP_EN, - (a_uint8_t *) (&data), sizeof (a_uint32_t)); - return rv; -} - -static sw_error_t -_shiva_arp_status_get(a_uint32_t dev_id, a_bool_t *enable) -{ - a_uint32_t data = 0; - sw_error_t rv; - - HSL_DEV_ID_CHECK(dev_id); - - HSL_REG_FIELD_GET(rv, dev_id, QM_CTL, 0, ARP_EN, - (a_uint8_t *) (&data), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - - if (1 == data) - { - *enable = A_TRUE; - } - else - { - *enable = A_FALSE; - } - - return SW_OK; -} - -static sw_error_t -_shiva_frame_max_size_set(a_uint32_t dev_id, a_uint32_t size) -{ - a_uint32_t data; - sw_error_t rv; - - HSL_DEV_ID_CHECK(dev_id); - - if (SHIVA_MAX_FRMAE_SIZE < size) - { - return SW_BAD_PARAM; - } - - data = size; - HSL_REG_FIELD_SET(rv, dev_id, GLOBAL_CTL, 0, MAX_FRAME_SIZE, - (a_uint8_t *) (&data), sizeof (a_uint32_t)); - return rv; -} - -static sw_error_t -_shiva_frame_max_size_get(a_uint32_t dev_id, a_uint32_t *size) -{ - a_uint32_t data = 0; - sw_error_t rv; - - HSL_DEV_ID_CHECK(dev_id); - - HSL_REG_FIELD_GET(rv, dev_id, GLOBAL_CTL, 0, MAX_FRAME_SIZE, - (a_uint8_t *) (&data), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - - *size = data; - return SW_OK; -} - -static sw_error_t -_shiva_port_unk_sa_cmd_set(a_uint32_t dev_id, fal_port_t port_id, - fal_fwd_cmd_t cmd) -{ - sw_error_t rv; - a_uint32_t data = 0; - - HSL_DEV_ID_CHECK(dev_id); - - if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU)) - { - return SW_BAD_PARAM; - } - - HSL_REG_ENTRY_GET(rv, dev_id, PORT_CTL, port_id, (a_uint8_t *) (&data), - sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - - if (FAL_MAC_FRWRD == cmd) - { - SW_SET_REG_BY_FIELD(PORT_CTL, PORT_LOCK_EN, 0, data); - } - else if (FAL_MAC_DROP == cmd) - { - SW_SET_REG_BY_FIELD(PORT_CTL, PORT_LOCK_EN, 1, data); - SW_SET_REG_BY_FIELD(PORT_CTL, LOCK_DROP_EN, 1, data); - } - else if (FAL_MAC_RDT_TO_CPU == cmd) - { - SW_SET_REG_BY_FIELD(PORT_CTL, PORT_LOCK_EN, 1, data); - SW_SET_REG_BY_FIELD(PORT_CTL, LOCK_DROP_EN, 0, data); - } - else - { - return SW_NOT_SUPPORTED; - } - - HSL_REG_ENTRY_SET(rv, dev_id, PORT_CTL, port_id, (a_uint8_t *) (&data), - sizeof (a_uint32_t)); - return rv; -} - -static sw_error_t -_shiva_port_unk_sa_cmd_get(a_uint32_t dev_id, fal_port_t port_id, - fal_fwd_cmd_t * action) -{ - sw_error_t rv; - a_uint32_t data = 0; - a_uint32_t port_lock_en, port_drop_en; - - HSL_DEV_ID_CHECK(dev_id); - - if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU)) - { - return SW_BAD_PARAM; - } - - HSL_REG_ENTRY_GET(rv, dev_id, PORT_CTL, port_id, (a_uint8_t *) (&data), - sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - - SW_GET_FIELD_BY_REG(PORT_CTL, PORT_LOCK_EN, port_lock_en, data); - SW_GET_FIELD_BY_REG(PORT_CTL, LOCK_DROP_EN, port_drop_en, data); - - if (1 == port_lock_en) - { - if (1 == port_drop_en) - { - *action = FAL_MAC_DROP; - } - else - { - *action = FAL_MAC_RDT_TO_CPU; - } - } - else - { - *action = FAL_MAC_FRWRD; - } - - return SW_OK; -} - -static sw_error_t -_shiva_port_unk_uc_filter_set(a_uint32_t dev_id, fal_port_t port_id, - a_bool_t enable) -{ - sw_error_t rv; - a_uint32_t data = 0; - - HSL_DEV_ID_CHECK(dev_id); - - if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU)) - { - return SW_BAD_PARAM; - } - - HSL_REG_FIELD_GET(rv, dev_id, FLOOD_MASK, 0, UNI_FLOOD_DP, - (a_uint8_t *) (&data), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - - if (A_TRUE == enable) - { - data &= (~((a_uint32_t)0x1 << port_id)); - } - else if (A_FALSE == enable) - { - data |= (0x1 << port_id); - } - else - { - return SW_BAD_PARAM; - } - - HSL_REG_FIELD_SET(rv, dev_id, FLOOD_MASK, 0, UNI_FLOOD_DP, - (a_uint8_t *) (&data), sizeof (a_uint32_t)); - return rv; -} - -static sw_error_t -_shiva_port_unk_uc_filter_get(a_uint32_t dev_id, fal_port_t port_id, - a_bool_t * enable) -{ - sw_error_t rv; - a_uint32_t reg = 0, field; - - HSL_DEV_ID_CHECK(dev_id); - - if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU)) - { - return SW_BAD_PARAM; - } - - HSL_REG_FIELD_GET(rv, dev_id, FLOOD_MASK, 0, UNI_FLOOD_DP, - (a_uint8_t *) (®), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - - field = reg & (0x1 << port_id); - if (field) - { - *enable = A_FALSE; - } - else - { - *enable = A_TRUE; - } - - return SW_OK; -} - -static sw_error_t -_shiva_port_unk_mc_filter_set(a_uint32_t dev_id, fal_port_t port_id, - a_bool_t enable) -{ - sw_error_t rv; - a_uint32_t data = 0; - - HSL_DEV_ID_CHECK(dev_id); - - if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU)) - { - return SW_BAD_PARAM; - } - - HSL_REG_FIELD_GET(rv, dev_id, FLOOD_MASK, 0, MUL_FLOOD_DP, - (a_uint8_t *) (&data), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - - if (A_TRUE == enable) - { - data &= (~((a_uint32_t)0x1 << port_id)); - } - else if (A_FALSE == enable) - { - data |= (0x1 << port_id); - } - else - { - return SW_BAD_PARAM; - } - - HSL_REG_FIELD_SET(rv, dev_id, FLOOD_MASK, 0, MUL_FLOOD_DP, - (a_uint8_t *) (&data), sizeof (a_uint32_t)); - return rv; -} - -static sw_error_t -_shiva_port_unk_mc_filter_get(a_uint32_t dev_id, fal_port_t port_id, - a_bool_t * enable) -{ - sw_error_t rv; - a_uint32_t reg = 0, field; - - HSL_DEV_ID_CHECK(dev_id); - - if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU)) - { - return SW_BAD_PARAM; - } - - HSL_REG_FIELD_GET(rv, dev_id, FLOOD_MASK, 0, MUL_FLOOD_DP, - (a_uint8_t *) (®), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - - field = reg & (0x1 << port_id); - if (field) - { - *enable = A_FALSE; - } - else - { - *enable = A_TRUE; - } - - return SW_OK; -} - -static sw_error_t -_shiva_port_bc_filter_set(a_uint32_t dev_id, fal_port_t port_id, - a_bool_t enable) -{ - sw_error_t rv; - a_uint32_t data = 0; - - HSL_DEV_ID_CHECK(dev_id); - - if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU)) - { - return SW_BAD_PARAM; - } - - HSL_REG_FIELD_GET(rv, dev_id, FLOOD_MASK, 0, BC_FLOOD_DP, - (a_uint8_t *) (&data), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - - if (A_TRUE == enable) - { - data &= (~((a_uint32_t)0x1 << port_id)); - } - else if (A_FALSE == enable) - { - data |= (0x1 << port_id); - } - else - { - return SW_BAD_PARAM; - } - - HSL_REG_FIELD_SET(rv, dev_id, FLOOD_MASK, 0, BC_FLOOD_DP, - (a_uint8_t *) (&data), sizeof (a_uint32_t)); - return rv; -} - -static sw_error_t -_shiva_port_bc_filter_get(a_uint32_t dev_id, fal_port_t port_id, - a_bool_t * enable) -{ - sw_error_t rv; - a_uint32_t reg = 0, field; - - HSL_DEV_ID_CHECK(dev_id); - - if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU)) - { - return SW_BAD_PARAM; - } - - HSL_REG_FIELD_GET(rv, dev_id, FLOOD_MASK, 0, BC_FLOOD_DP, - (a_uint8_t *) (®), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - - field = reg & (0x1 << port_id); - if (field) - { - *enable = A_FALSE; - } - else - { - *enable = A_TRUE; - } - - return SW_OK; -} - -static sw_error_t -_shiva_cpu_port_status_set(a_uint32_t dev_id, a_bool_t enable) -{ - sw_error_t rv; - a_uint32_t val; - - HSL_DEV_ID_CHECK(dev_id); - - if (A_TRUE == enable) - { - val = 1; - } - else if (A_FALSE == enable) - { - val = 0; - } - else - { - return SW_BAD_PARAM; - } - - HSL_REG_FIELD_SET(rv, dev_id, CPU_PORT, 0, CPU_PORT_EN, - (a_uint8_t *) (&val), sizeof (a_uint32_t)); - return rv; -} - -static sw_error_t -_shiva_cpu_port_status_get(a_uint32_t dev_id, a_bool_t *enable) -{ - sw_error_t rv; - a_uint32_t val = 0; - - HSL_DEV_ID_CHECK(dev_id); - - HSL_REG_FIELD_GET(rv, dev_id, CPU_PORT, 0, CPU_PORT_EN, - (a_uint8_t *) (&val), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - - if (1 == val) - { - *enable = A_TRUE; - } - else - { - *enable = A_FALSE; - } - - return SW_OK; -} - -static sw_error_t -_shiva_pppoe_cmd_set(a_uint32_t dev_id, fal_fwd_cmd_t cmd) -{ - sw_error_t rv; - a_uint32_t val; - - HSL_DEV_ID_CHECK(dev_id); - - if (FAL_MAC_FRWRD == cmd) - { - val = 0; - } - else if (FAL_MAC_RDT_TO_CPU == cmd) - { - val = 1; - } - else - { - return SW_NOT_SUPPORTED; - } - - HSL_REG_FIELD_SET(rv, dev_id, QM_CTL, 0, PPPOE_RDT_EN, - (a_uint8_t *) (&val), sizeof (a_uint32_t)); - return rv; -} - -static sw_error_t -_shiva_pppoe_cmd_get(a_uint32_t dev_id, fal_fwd_cmd_t * cmd) -{ - sw_error_t rv; - a_uint32_t val = 0; - - HSL_DEV_ID_CHECK(dev_id); - - HSL_REG_FIELD_GET(rv, dev_id, QM_CTL, 0, PPPOE_RDT_EN, - (a_uint8_t *) (&val), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - - if (1 == val) - { - *cmd = FAL_MAC_RDT_TO_CPU; - } - else - { - *cmd = FAL_MAC_FRWRD; - } - - return SW_OK; -} - -static sw_error_t -_shiva_pppoe_status_set(a_uint32_t dev_id, a_bool_t enable) -{ - sw_error_t rv; - a_uint32_t val; - - HSL_DEV_ID_CHECK(dev_id); - - if (A_TRUE == enable) - { - val = 1; - } - else if (A_FALSE == enable) - { - val = 0; - } - else - { - return SW_BAD_PARAM; - } - - HSL_REG_FIELD_SET(rv, dev_id, QM_CTL, 0, PPPOE_EN, - (a_uint8_t *) (&val), sizeof (a_uint32_t)); - return rv; -} - -static sw_error_t -_shiva_pppoe_status_get(a_uint32_t dev_id, a_bool_t * enable) -{ - sw_error_t rv; - a_uint32_t val = 0; - - HSL_DEV_ID_CHECK(dev_id); - - HSL_REG_FIELD_GET(rv, dev_id, QM_CTL, 0, PPPOE_EN, - (a_uint8_t *) (&val), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - - if (1 == val) - { - *enable = A_TRUE; - } - else - { - *enable = A_FALSE; - } - - return SW_OK; -} - -static sw_error_t -_shiva_port_dhcp_set(a_uint32_t dev_id, fal_port_t port_id, a_bool_t enable) -{ - sw_error_t rv; - a_uint32_t val; - - HSL_DEV_ID_CHECK(dev_id); - - if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU)) - { - return SW_BAD_PARAM; - } - - if (A_TRUE == enable) - { - val = 1; - } - else if (A_FALSE == enable) - { - val = 0; - } - else - { - return SW_BAD_PARAM; - } - - HSL_REG_FIELD_SET(rv, dev_id, PORT_CTL, port_id, DHCP_EN, - (a_uint8_t *) (&val), sizeof (a_uint32_t)); - return rv; -} - -static sw_error_t -_shiva_port_dhcp_get(a_uint32_t dev_id, fal_port_t port_id, a_bool_t * enable) -{ - sw_error_t rv; - a_uint32_t val = 0; - - HSL_DEV_ID_CHECK(dev_id); - - if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU)) - { - return SW_BAD_PARAM; - } - - HSL_REG_FIELD_GET(rv, dev_id, PORT_CTL, port_id, DHCP_EN, - (a_uint8_t *) (&val), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - - if (1 == val) - { - *enable = A_TRUE; - } - else - { - *enable = A_FALSE; - } - - return SW_OK; -} - -static sw_error_t -_shiva_arp_cmd_set(a_uint32_t dev_id, fal_fwd_cmd_t cmd) -{ - sw_error_t rv; - a_uint32_t val; - - HSL_DEV_ID_CHECK(dev_id); - - if (FAL_MAC_CPY_TO_CPU == cmd) - { - val = 0; - } - else if (FAL_MAC_RDT_TO_CPU == cmd) - { - val = 1; - } - else - { - return SW_NOT_SUPPORTED; - } - - HSL_REG_FIELD_SET(rv, dev_id, QM_CTL, 0, ARP_CMD, - (a_uint8_t *) (&val), sizeof (a_uint32_t)); - return rv; -} - -static sw_error_t -_shiva_arp_cmd_get(a_uint32_t dev_id, fal_fwd_cmd_t * cmd) -{ - sw_error_t rv; - a_uint32_t val = 0; - - HSL_DEV_ID_CHECK(dev_id); - - HSL_REG_FIELD_GET(rv, dev_id, QM_CTL, 0, ARP_CMD, - (a_uint8_t *) (&val), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - - if (0 == val) - { - *cmd = FAL_MAC_CPY_TO_CPU; - } - else - { - *cmd = FAL_MAC_RDT_TO_CPU; - } - - return SW_OK; -} - -static sw_error_t -_shiva_eapol_cmd_set(a_uint32_t dev_id, fal_fwd_cmd_t cmd) -{ - sw_error_t rv; - a_uint32_t val; - - HSL_DEV_ID_CHECK(dev_id); - - if (FAL_MAC_CPY_TO_CPU == cmd) - { - val = 0; - } - else if (FAL_MAC_RDT_TO_CPU == cmd) - { - val = 1; - } - else - { - return SW_NOT_SUPPORTED; - } - - HSL_REG_FIELD_SET(rv, dev_id, QM_CTL, 0, EAPOL_CMD, - (a_uint8_t *) (&val), sizeof (a_uint32_t)); - return rv; -} - -static sw_error_t -_shiva_eapol_cmd_get(a_uint32_t dev_id, fal_fwd_cmd_t * cmd) -{ - sw_error_t rv; - a_uint32_t val = 0; - - HSL_DEV_ID_CHECK(dev_id); - - HSL_REG_FIELD_GET(rv, dev_id, QM_CTL, 0, EAPOL_CMD, - (a_uint8_t *) (&val), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - - if (0 == val) - { - *cmd = FAL_MAC_CPY_TO_CPU; - } - else - { - *cmd = FAL_MAC_RDT_TO_CPU; - } - - return SW_OK; -} - -#define SHIVA_MAX_PPPOE_SESSION 16 -#define SHIVA_MAX_SESSION_ID 0xffff - -static sw_error_t -_shiva_pppoe_session_add(a_uint32_t dev_id, a_uint32_t session_id, a_bool_t strip_hdr) -{ - sw_error_t rv; - a_uint32_t reg = 0, i, valid, cmd, id, entry_idx = 0xffff; - - HSL_DEV_ID_CHECK(dev_id); - - if (session_id > SHIVA_MAX_SESSION_ID) - { - return SW_BAD_PARAM; - } - - for (i = 0; i < SHIVA_MAX_PPPOE_SESSION; i++) - { - HSL_REG_ENTRY_GET(rv, dev_id, PPPOE_SESSION, i, - (a_uint8_t *) (®), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - - SW_GET_FIELD_BY_REG(PPPOE_SESSION, ENTRY_VALID, valid, reg); - SW_GET_FIELD_BY_REG(PPPOE_SESSION, SEESION_ID, id, reg); - - if (!valid) - { - entry_idx = i; - } - else if (id == session_id) - { - return SW_ALREADY_EXIST; - } - } - - if (0xffff == entry_idx) - { - return SW_NO_RESOURCE; - } - - SW_SET_REG_BY_FIELD(PPPOE_SESSION, ENTRY_VALID, 1, reg); - if (A_TRUE == strip_hdr) - { - cmd = 1; - } - else if (A_FALSE == strip_hdr) - { - cmd = 0; - } - else - { - return SW_NOT_SUPPORTED; - } - SW_SET_REG_BY_FIELD(PPPOE_SESSION, STRIP_EN, cmd, reg); - SW_SET_REG_BY_FIELD(PPPOE_SESSION, SEESION_ID, session_id, reg); - - HSL_REG_ENTRY_SET(rv, dev_id, PPPOE_SESSION, entry_idx, - (a_uint8_t *) (®), sizeof (a_uint32_t)); - return rv; -} - -static sw_error_t -_shiva_pppoe_session_del(a_uint32_t dev_id, a_uint32_t session_id) -{ - sw_error_t rv; - a_uint32_t reg = 0, i, valid, id; - - HSL_DEV_ID_CHECK(dev_id); - - if (session_id > SHIVA_MAX_SESSION_ID) - { - return SW_BAD_PARAM; - } - - for (i = 0; i < SHIVA_MAX_PPPOE_SESSION; i++) - { - HSL_REG_ENTRY_GET(rv, dev_id, PPPOE_SESSION, i, - (a_uint8_t *) (®), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - - SW_GET_FIELD_BY_REG(PPPOE_SESSION, ENTRY_VALID, valid, reg); - SW_GET_FIELD_BY_REG(PPPOE_SESSION, SEESION_ID, id, reg); - - if (valid && (id == session_id)) - { - SW_SET_REG_BY_FIELD(PPPOE_SESSION, ENTRY_VALID, 0, reg); - SW_SET_REG_BY_FIELD(PPPOE_SESSION, STRIP_EN, 0, reg); - SW_SET_REG_BY_FIELD(PPPOE_SESSION, SEESION_ID, 0, reg); - HSL_REG_ENTRY_SET(rv, dev_id, PPPOE_SESSION, i, - (a_uint8_t *) (®), sizeof (a_uint32_t)); - return rv; - } - } - - return SW_NOT_FOUND; -} - -static sw_error_t -_shiva_pppoe_session_get(a_uint32_t dev_id, a_uint32_t session_id, a_bool_t * strip_hdr) -{ - sw_error_t rv; - a_uint32_t reg = 0, i, valid, cmd, id; - - HSL_DEV_ID_CHECK(dev_id); - - if (session_id > SHIVA_MAX_SESSION_ID) - { - return SW_BAD_PARAM; - } - - for (i = 0; i < SHIVA_MAX_PPPOE_SESSION; i++) - { - HSL_REG_ENTRY_GET(rv, dev_id, PPPOE_SESSION, i, - (a_uint8_t *) (®), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - - SW_GET_FIELD_BY_REG(PPPOE_SESSION, ENTRY_VALID, valid, reg); - SW_GET_FIELD_BY_REG(PPPOE_SESSION, SEESION_ID, id, reg); - - if (valid && (id == session_id)) - { - SW_GET_FIELD_BY_REG(PPPOE_SESSION, STRIP_EN, cmd, reg); - if (cmd) - { - *strip_hdr = A_TRUE; - } - else - { - *strip_hdr = A_FALSE; - } - return SW_OK; - } - } - - return SW_NOT_FOUND; -} - -static sw_error_t -_shiva_eapol_status_set(a_uint32_t dev_id, a_uint32_t port_id, a_bool_t enable) -{ - a_uint32_t data; - sw_error_t rv; - - HSL_DEV_ID_CHECK(dev_id); - - if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU)) - { - return SW_BAD_PARAM; - } - - if (A_TRUE == enable) - { - data = 1; - } - else if (A_FALSE == enable) - { - data = 0; - } - else - { - return SW_BAD_PARAM; - } - - HSL_REG_FIELD_SET(rv, dev_id, PORT_CTL, port_id, EAPOL_EN, - (a_uint8_t *) (&data), sizeof (a_uint32_t)); - return rv; -} - -static sw_error_t -_shiva_eapol_status_get(a_uint32_t dev_id, a_uint32_t port_id, a_bool_t *enable) -{ - a_uint32_t data = 0; - sw_error_t rv; - - HSL_DEV_ID_CHECK(dev_id); - - if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU)) - { - return SW_BAD_PARAM; - } - - HSL_REG_FIELD_GET(rv, dev_id, PORT_CTL, port_id, EAPOL_EN, - (a_uint8_t *) (&data), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - - if (1 == data) - { - *enable = A_TRUE; - } - else - { - *enable = A_FALSE; - } - - return SW_OK; -} - -static sw_error_t -_shiva_ripv1_status_set(a_uint32_t dev_id, a_bool_t enable) -{ - a_uint32_t data; - sw_error_t rv; - - HSL_DEV_ID_CHECK(dev_id); - - if (A_TRUE != hsl_port_prop_check(dev_id, 0, HSL_PP_INCL_CPU)) - { - return SW_BAD_PARAM; - } - - if (A_TRUE == enable) - { - data = 1; - } - else if (A_FALSE == enable) - { - data = 0; - } - else - { - return SW_BAD_PARAM; - } - - HSL_REG_FIELD_SET(rv, dev_id, QM_CTL, 0, RIP_CPY_EN, - (a_uint8_t *) (&data), sizeof (a_uint32_t)); - return rv; -} - -static sw_error_t -_shiva_ripv1_status_get(a_uint32_t dev_id, a_bool_t *enable) -{ - a_uint32_t data = 0; - sw_error_t rv; - - HSL_DEV_ID_CHECK(dev_id); - - if (A_TRUE != hsl_port_prop_check(dev_id, 0, HSL_PP_INCL_CPU)) - { - return SW_BAD_PARAM; - } - - HSL_REG_FIELD_GET(rv, dev_id, QM_CTL, 0, RIP_CPY_EN, - (a_uint8_t *) (&data), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - - if (1 == data) - { - *enable = A_TRUE; - } - else - { - *enable = A_FALSE; - } - - return SW_OK; -} - -#if 0 -static sw_error_t -_shiva_loop_check_status_set(a_uint32_t dev_id, fal_loop_check_time_t time, a_bool_t enable) -{ - sw_error_t rv; - a_uint32_t data, intr; - - HSL_DEV_ID_CHECK(dev_id); - - if (A_TRUE == enable) - { - if (FAL_LOOP_CHECK_1MS == time) - { - data = 1; - } - else if (FAL_LOOP_CHECK_10MS == time) - { - data = 2; - } - else if (FAL_LOOP_CHECK_100MS == time) - { - data = 3; - } - else if (FAL_LOOP_CHECK_500MS == time) - { - data = 4; - } - else - { - return SW_BAD_PARAM; - } - intr = 1; - } - else - { - data = 0; - intr = 0; - } - - HSL_REG_FIELD_SET(rv, dev_id, ADDR_TABLE_CTL, 0, LOOP_CHK_TIME, - (a_uint8_t *) (&data), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - - HSL_REG_FIELD_SET(rv, dev_id, GLOBAL_INT_MASK, 0, GLBM_LOOP_CHECK, - (a_uint8_t *) (&intr), sizeof (a_uint32_t)); - - return rv; -} - -static sw_error_t -_shiva_loop_check_status_get(a_uint32_t dev_id, fal_loop_check_time_t * time, a_bool_t * enable) -{ - sw_error_t rv; - a_uint32_t data = 0; - - HSL_DEV_ID_CHECK(dev_id); - - HSL_REG_FIELD_GET(rv, dev_id, ADDR_TABLE_CTL, 0, LOOP_CHK_TIME, - (a_uint8_t *) (&data), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - - *enable = A_TRUE; - *time = FAL_LOOP_CHECK_1MS; - if (0 == data) - { - *enable = A_FALSE; - } - else if (2 == data) - { - *time = FAL_LOOP_CHECK_10MS; - } - else if (3 == data) - { - *time = FAL_LOOP_CHECK_100MS; - } - else if (4 == data) - { - *time = FAL_LOOP_CHECK_500MS; - } - - return SW_OK; -} - -static sw_error_t -_shiva_loop_check_info_get(a_uint32_t dev_id, a_uint32_t * old_port_id, a_uint32_t * new_port_id) -{ - sw_error_t rv; - a_uint32_t reg = 0, data; - - HSL_DEV_ID_CHECK(dev_id); - - HSL_REG_ENTRY_GET(rv, dev_id, LOOP_CHECK, 0, - (a_uint8_t *) (®), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - - SW_GET_FIELD_BY_REG(LOOP_CHECK, NEW_PORT, data, reg); - *new_port_id = data; - - SW_GET_FIELD_BY_REG(LOOP_CHECK, OLD_PORT, data, reg); - *old_port_id = data; - - return SW_OK; -} -#endif - -/** - * @brief Set arp packets hardware acknowledgement status on a particular device. - * @param[in] dev_id device id - * @param[in] enable A_TRUE or A_FALSE - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -shiva_arp_status_set(a_uint32_t dev_id, a_bool_t enable) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _shiva_arp_status_set(dev_id, enable); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Get arp packets hardware acknowledgement status on a particular device. - * @param[in] dev_id device id - * @param[out] enable A_TRUE or A_FALSE - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -shiva_arp_status_get(a_uint32_t dev_id, a_bool_t *enable) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _shiva_arp_status_get(dev_id, enable); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Set max frame size which device can received on a particular device. - * @details Comments: - * The granularity of packets size is byte. - * @param[in] dev_id device id - * @param[in] size packet size - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -shiva_frame_max_size_set(a_uint32_t dev_id, a_uint32_t size) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _shiva_frame_max_size_set(dev_id, size); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Get max frame size which device can received on a particular device. - * @details Comments: - * The unit of packets size is byte. - * @param[in] dev_id device id - * @param[out] size packet size - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -shiva_frame_max_size_get(a_uint32_t dev_id, a_uint32_t *size) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _shiva_frame_max_size_get(dev_id, size); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Set forwarding command for packets which source address is unknown on a particular port. - * @details Comments: - * Particular device may only support parts of forwarding commands. - * @param[in] dev_id device id - * @param[in] port_id port id - * @param[in] cmd forwarding command - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -shiva_port_unk_sa_cmd_set(a_uint32_t dev_id, fal_port_t port_id, - fal_fwd_cmd_t cmd) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _shiva_port_unk_sa_cmd_set(dev_id, port_id, cmd); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Get forwarding command for packets which source address is unknown on a particular port. - * @param[in] dev_id device id - * @param[in] port_id port id - * @param[out] cmd forwarding command - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -shiva_port_unk_sa_cmd_get(a_uint32_t dev_id, fal_port_t port_id, - fal_fwd_cmd_t * action) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _shiva_port_unk_sa_cmd_get(dev_id, port_id, action); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Set flooding status of unknown unicast packets on a particular port. - * @details Comments: - * If enable unknown unicast packets filter on one port then unknown - * unicast packets can't flood out from this port. - * @param[in] dev_id device id - * @param[in] port_id port id - * @param[in] enable A_TRUE or A_FALSE - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -shiva_port_unk_uc_filter_set(a_uint32_t dev_id, fal_port_t port_id, - a_bool_t enable) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _shiva_port_unk_uc_filter_set(dev_id, port_id, enable); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Get flooding status of unknown unicast packets on a particular port. - * @param[in] dev_id device id - * @param[in] port_id port id - * @param[out] enable A_TRUE or A_FALSE - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -shiva_port_unk_uc_filter_get(a_uint32_t dev_id, fal_port_t port_id, - a_bool_t * enable) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _shiva_port_unk_uc_filter_get(dev_id, port_id, enable); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Set flooding status of unknown multicast packets on a particular port. - * @details Comments: - * If enable unknown multicast packets filter on one port then unknown - * multicast packets can't flood out from this port. - * @param[in] dev_id device id - * @param[in] port_id port id - * @param[in] enable A_TRUE or A_FALSE - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -shiva_port_unk_mc_filter_set(a_uint32_t dev_id, fal_port_t port_id, - a_bool_t enable) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _shiva_port_unk_mc_filter_set(dev_id, port_id, enable); - HSL_API_UNLOCK; - return rv; -} - -/** @brief Get flooding status of unknown multicast packets on a particular port. - * @param[in] dev_id device id - * @param[in] port_id port id - * @param[out] enable A_TRUE or A_FALSE - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -shiva_port_unk_mc_filter_get(a_uint32_t dev_id, fal_port_t port_id, - a_bool_t * enable) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _shiva_port_unk_mc_filter_get(dev_id, port_id, enable); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Set flooding status of broadcast packets on a particular port. - * @details Comments: - * If enable unknown multicast packets filter on one port then unknown - * multicast packets can't flood out from this port. - * @param[in] dev_id device id - * @param[in] port_id port id - * @param[in] enable A_TRUE or A_FALSE - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -shiva_port_bc_filter_set(a_uint32_t dev_id, fal_port_t port_id, - a_bool_t enable) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _shiva_port_bc_filter_set(dev_id, port_id, enable); - HSL_API_UNLOCK; - return rv; -} - -/** @brief Get flooding status of broadcast packets on a particular port. - * @param[in] dev_id device id - * @param[in] port_id port id - * @param[out] enable A_TRUE or A_FALSE - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -shiva_port_bc_filter_get(a_uint32_t dev_id, fal_port_t port_id, - a_bool_t * enable) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _shiva_port_bc_filter_get(dev_id, port_id, enable); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Set cpu port status on a particular device. - * @param[in] dev_id device id - * @param[in] enable A_TRUE or A_FALSE - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -shiva_cpu_port_status_set(a_uint32_t dev_id, a_bool_t enable) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _shiva_cpu_port_status_set(dev_id, enable); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Get cpu port status on a particular device. - * @param[in] dev_id device id - * @param[in] enable A_TRUE or A_FALSE - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -shiva_cpu_port_status_get(a_uint32_t dev_id, a_bool_t *enable) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _shiva_cpu_port_status_get(dev_id, enable); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Set pppoe packets forwarding command on a particular device. - * @details comments: - * Particular device may only support parts of forwarding commands. - * Ihis operation will take effect only after enabling pppoe packets - * hardware acknowledgement - * @param[in] dev_id device id - * @param[in] cmd forwarding command - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -shiva_pppoe_cmd_set(a_uint32_t dev_id, fal_fwd_cmd_t cmd) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _shiva_pppoe_cmd_set(dev_id, cmd); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Get pppoe packets forwarding command on a particular device. - * @param[in] dev_id device id - * @param[out] cmd forwarding command - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -shiva_pppoe_cmd_get(a_uint32_t dev_id, fal_fwd_cmd_t * cmd) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _shiva_pppoe_cmd_get(dev_id, cmd); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Set pppoe packets hardware acknowledgement status on particular device. - * @details comments: - * Particular device may only support parts of pppoe packets. - * @param[in] dev_id device id - * @param[in] enable A_TRUE or A_FALSE - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -shiva_pppoe_status_set(a_uint32_t dev_id, a_bool_t enable) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _shiva_pppoe_status_set(dev_id, enable); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Get pppoe packets hardware acknowledgement status on a particular device. - * @param[in] dev_id device id - * @param[out] enable A_TRUE or A_FALSE - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -shiva_pppoe_status_get(a_uint32_t dev_id, a_bool_t * enable) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _shiva_pppoe_status_get(dev_id, enable); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Set dhcp packets hardware acknowledgement status on a particular device. - * @param[in] dev_id device id - * @param[in] enable A_TRUE or A_FALSE - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -shiva_port_dhcp_set(a_uint32_t dev_id, fal_port_t port_id, a_bool_t enable) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _shiva_port_dhcp_set(dev_id, port_id, enable); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Get dhcp packets hardware acknowledgement status on particular device. - * @param[in] dev_id device id - * @param[out] enable A_TRUE or A_FALSE - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -shiva_port_dhcp_get(a_uint32_t dev_id, fal_port_t port_id, a_bool_t * enable) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _shiva_port_dhcp_get(dev_id, port_id, enable); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Set arp packets forwarding command on a particular device. - * @details comments: - * Particular device may only support parts of forwarding commands. - * Ihis operation will take effect only after enabling arp packets - * hardware acknowledgement - * @param[in] dev_id device id - * @param[in] cmd forwarding command - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -shiva_arp_cmd_set(a_uint32_t dev_id, fal_fwd_cmd_t cmd) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _shiva_arp_cmd_set(dev_id, cmd); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Get arp packets forwarding command on a particular device. - * @param[in] dev_id device id - * @param[out] cmd forwarding command - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -shiva_arp_cmd_get(a_uint32_t dev_id, fal_fwd_cmd_t * cmd) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _shiva_arp_cmd_get(dev_id, cmd); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Set eapol packets forwarding command on a particular device. - * @details comments: - * Particular device may only support parts of forwarding commands. - * Ihis operation will take effect only after enabling eapol packets - * hardware acknowledgement - * @param[in] dev_id device id - * @param[in] cmd forwarding command - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -shiva_eapol_cmd_set(a_uint32_t dev_id, fal_fwd_cmd_t cmd) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _shiva_eapol_cmd_set(dev_id, cmd); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Get eapol packets forwarding command on a particular device. - * @param[in] dev_id device id - * @param[out] cmd forwarding command - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -shiva_eapol_cmd_get(a_uint32_t dev_id, fal_fwd_cmd_t * cmd) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _shiva_eapol_cmd_get(dev_id, cmd); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Add a pppoe session entry to a particular device. - * @param[in] dev_id device id - * @param[in] session_id pppoe session id - * @param[in] strip_hdr strip or not strip pppoe header - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -shiva_pppoe_session_add(a_uint32_t dev_id, a_uint32_t session_id, a_bool_t strip_hdr) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _shiva_pppoe_session_add(dev_id, session_id, strip_hdr); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Delete a pppoe session entry from a particular device. - * @param[in] dev_id device id - * @param[in] session_id pppoe session id - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -shiva_pppoe_session_del(a_uint32_t dev_id, a_uint32_t session_id) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _shiva_pppoe_session_del(dev_id, session_id); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Get a pppoe session entry from a particular device. - * @param[in] dev_id device id - * @param[in] session_id pppoe session id - * @param[out] strip_hdr strip or not strip pppoe header - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -shiva_pppoe_session_get(a_uint32_t dev_id, a_uint32_t session_id, a_bool_t * strip_hdr) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _shiva_pppoe_session_get(dev_id, session_id, strip_hdr); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Set eapol packets hardware acknowledgement status on a particular port. - * @param[in] dev_id device id - * @param[in] port_id port id - * @param[in] enable A_TRUE or A_FALSE - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -shiva_eapol_status_set(a_uint32_t dev_id, a_uint32_t port_id, a_bool_t enable) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _shiva_eapol_status_set(dev_id, port_id, enable); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Get eapol packets hardware acknowledgement status on a particular port. - * @param[in] dev_id device id - * @param[in] port_id port id - * @param[out] enable A_TRUE or A_FALSE - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -shiva_eapol_status_get(a_uint32_t dev_id, a_uint32_t port_id, a_bool_t *enable) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _shiva_eapol_status_get(dev_id, port_id, enable); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Set rip v1 packets hardware acknowledgement status on a particular port. - * @param[in] dev_id device id - * @param[in] enable A_TRUE or A_FALSE - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -shiva_ripv1_status_set(a_uint32_t dev_id, a_bool_t enable) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _shiva_ripv1_status_set(dev_id, enable); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Get rip v1 packets hardware acknowledgement status on a particular port. - * @param[in] dev_id device id - * @param[out] enable A_TRUE or A_FALSE - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -shiva_ripv1_status_get(a_uint32_t dev_id, a_bool_t *enable) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _shiva_ripv1_status_get(dev_id, enable); - HSL_API_UNLOCK; - return rv; -} - -#if 0 -/** - * @brief Set loopback checking status on a particular device. - * @param[in] dev_id device id - * @param[in] enable A_TRUE or A_FALSE - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -shiva_loop_check_status_set(a_uint32_t dev_id, fal_loop_check_time_t time, a_bool_t enable) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _shiva_loop_check_status_set(dev_id, time, enable); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Get loopback checking status on a particular device. - * @param[in] dev_id device id - * @param[out] enable A_TRUE or A_FALSE - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -shiva_loop_check_status_get(a_uint32_t dev_id, fal_loop_check_time_t * time, a_bool_t * enable) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _shiva_loop_check_status_get(dev_id, time, enable); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Get loopback checking information on a particular device. - * @param[in] dev_id device id - * @param[in] old_port_id - * @param[in] new_port_id - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -shiva_loop_check_info_get(a_uint32_t dev_id, a_uint32_t * old_port_id, a_uint32_t * new_port_id) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _shiva_loop_check_info_get(dev_id, old_port_id, new_port_id); - HSL_API_UNLOCK; - return rv; -} -#endif - -sw_error_t -shiva_misc_init(a_uint32_t dev_id) -{ - HSL_DEV_ID_CHECK(dev_id); - -#ifndef HSL_STANDALONG - { - hsl_api_t *p_api; - - SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id)); - - p_api->arp_status_set = shiva_arp_status_set; - p_api->arp_status_get = shiva_arp_status_get; - p_api->frame_max_size_set = shiva_frame_max_size_set; - p_api->frame_max_size_get = shiva_frame_max_size_get; - p_api->port_unk_sa_cmd_set = shiva_port_unk_sa_cmd_set; - p_api->port_unk_sa_cmd_get = shiva_port_unk_sa_cmd_get; - p_api->port_unk_uc_filter_set = shiva_port_unk_uc_filter_set; - p_api->port_unk_uc_filter_get = shiva_port_unk_uc_filter_get; - p_api->port_unk_mc_filter_set = shiva_port_unk_mc_filter_set; - p_api->port_unk_mc_filter_get = shiva_port_unk_mc_filter_get; - p_api->port_bc_filter_set = shiva_port_bc_filter_set; - p_api->port_bc_filter_get = shiva_port_bc_filter_get; - p_api->cpu_port_status_set = shiva_cpu_port_status_set; - p_api->cpu_port_status_get = shiva_cpu_port_status_get; - p_api->pppoe_cmd_set = shiva_pppoe_cmd_set; - p_api->pppoe_cmd_get = shiva_pppoe_cmd_get; - p_api->pppoe_status_set = shiva_pppoe_status_set; - p_api->pppoe_status_get = shiva_pppoe_status_get; - p_api->port_dhcp_set = shiva_port_dhcp_set; - p_api->port_dhcp_get = shiva_port_dhcp_get; - p_api->arp_cmd_set = shiva_arp_cmd_set; - p_api->arp_cmd_get = shiva_arp_cmd_get; - p_api->eapol_cmd_set = shiva_eapol_cmd_set; - p_api->eapol_cmd_get = shiva_eapol_cmd_get; - p_api->pppoe_session_add = shiva_pppoe_session_add; - p_api->pppoe_session_del = shiva_pppoe_session_del; - p_api->pppoe_session_get = shiva_pppoe_session_get; - p_api->eapol_status_set = shiva_eapol_status_set; - p_api->eapol_status_get = shiva_eapol_status_get; - p_api->ripv1_status_set = shiva_ripv1_status_set; - p_api->ripv1_status_get = shiva_ripv1_status_get; - } -#endif - - return SW_OK; -} - -/** - * @} - */ - diff --git a/feeds/ipq807x/qca-ssdk/src/src/hsl/shiva/shiva_port_ctrl.c b/feeds/ipq807x/qca-ssdk/src/src/hsl/shiva/shiva_port_ctrl.c deleted file mode 100755 index de5868a61..000000000 --- a/feeds/ipq807x/qca-ssdk/src/src/hsl/shiva/shiva_port_ctrl.c +++ /dev/null @@ -1,1384 +0,0 @@ -/* - * Copyright (c) 2012, 2015-2017, The Linux Foundation. All rights reserved. - * Permission to use, copy, modify, and/or distribute this software for - * any purpose with or without fee is hereby granted, provided that the - * above copyright notice and this permission notice appear in all copies. - * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES - * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR - * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES - * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN - * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT - * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. - */ - - -/** - * @defgroup shiva_port_ctrl SHIVA_PORT_CONTROL - * @{ - */ -#include "sw.h" -#include "hsl.h" -#include "hsl_dev.h" -#include "hsl_port_prop.h" -#include "shiva_port_ctrl.h" -#include "shiva_reg.h" -#include "hsl_phy.h" - - -static sw_error_t -_shiva_port_duplex_set(a_uint32_t dev_id, fal_port_t port_id, - fal_port_duplex_t duplex) -{ - sw_error_t rv; - a_uint32_t phy_id = 0; - a_uint32_t reg_save = 0; - a_uint32_t reg_val = 0, tmp; - hsl_phy_ops_t *phy_drv; - - HSL_DEV_ID_CHECK(dev_id); - - if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_PHY)) - { - return SW_BAD_PARAM; - } - - SW_RTN_ON_NULL (phy_drv = hsl_phy_api_ops_get (dev_id, port_id)); - if (NULL == phy_drv->phy_duplex_set) - return SW_NOT_SUPPORTED; - - if (FAL_DUPLEX_BUTT <= duplex) - { - return SW_BAD_PARAM; - } - - rv = hsl_port_prop_get_phyid(dev_id, port_id, &phy_id); - SW_RTN_ON_ERROR(rv); - - rv = phy_drv->phy_duplex_get(dev_id, phy_id, &tmp); - SW_RTN_ON_ERROR(rv); - if (tmp == duplex) - return SW_OK; - - //save reg value - HSL_REG_ENTRY_GET(rv, dev_id, PORT_STATUS, port_id, - (a_uint8_t *) (®_val), sizeof (a_uint32_t)); - reg_save = reg_val; - - SW_SET_REG_BY_FIELD(PORT_STATUS, LINK_EN, 0, reg_val); - SW_SET_REG_BY_FIELD(PORT_STATUS, RXMAC_EN, 0, reg_val); - SW_SET_REG_BY_FIELD(PORT_STATUS, TXMAC_EN, 0, reg_val); - - //set mac be config by sw and turn off RX TX MAC_EN - HSL_REG_ENTRY_SET(rv, dev_id, PORT_STATUS, port_id, - (a_uint8_t *) (®_val), sizeof (a_uint32_t)); - - rv = phy_drv->phy_duplex_set(dev_id, phy_id, duplex); - - //retore reg value - HSL_REG_ENTRY_SET(rv, dev_id, PORT_STATUS, port_id, - (a_uint8_t *) (®_save), sizeof (a_uint32_t)); - - return rv; -} - -static sw_error_t -_shiva_port_duplex_get(a_uint32_t dev_id, fal_port_t port_id, - fal_port_duplex_t * pduplex) -{ - sw_error_t rv; - a_uint32_t phy_id; - hsl_phy_ops_t *phy_drv; - - HSL_DEV_ID_CHECK(dev_id); - - if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_PHY)) - { - return SW_BAD_PARAM; - } - - SW_RTN_ON_NULL (phy_drv = hsl_phy_api_ops_get (dev_id, port_id)); - if (NULL == phy_drv->phy_duplex_get) - return SW_NOT_SUPPORTED; - - rv = hsl_port_prop_get_phyid(dev_id, port_id, &phy_id); - SW_RTN_ON_ERROR(rv); - - rv = phy_drv->phy_duplex_get(dev_id, phy_id, pduplex); - return rv; -} - -static sw_error_t -_shiva_port_speed_set(a_uint32_t dev_id, fal_port_t port_id, - fal_port_speed_t speed) -{ - sw_error_t rv; - a_uint32_t phy_id = 0; - hsl_phy_ops_t *phy_drv; - - HSL_DEV_ID_CHECK(dev_id); - - if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_PHY)) - { - return SW_BAD_PARAM; - } - SW_RTN_ON_NULL (phy_drv = hsl_phy_api_ops_get (dev_id, port_id)); - if (NULL == phy_drv->phy_speed_set) - return SW_NOT_SUPPORTED; - - rv = hsl_port_prop_get_phyid(dev_id, port_id, &phy_id); - SW_RTN_ON_ERROR(rv); - - if (FAL_SPEED_100 < speed) - { - return SW_BAD_PARAM; - } - - rv = phy_drv->phy_speed_set(dev_id, phy_id, speed); - - return rv; -} - -static sw_error_t -_shiva_port_phy_id_get (a_uint32_t dev_id, fal_port_t port_id, - a_uint16_t * org_id, a_uint16_t * rev_id) -{ - sw_error_t rv; - a_uint32_t phy_id = 0; - hsl_phy_ops_t *phy_drv; - a_uint32_t phy_data; - - HSL_DEV_ID_CHECK (dev_id); - - if (A_TRUE != hsl_port_prop_check (dev_id, port_id, HSL_PP_PHY)) - { - return SW_BAD_PARAM; - } - - SW_RTN_ON_NULL (phy_drv = hsl_phy_api_ops_get (dev_id, port_id)); - if (NULL == phy_drv->phy_id_get) - return SW_NOT_SUPPORTED; - - rv = hsl_port_prop_get_phyid (dev_id, port_id, &phy_id); - SW_RTN_ON_ERROR (rv); - - rv = phy_drv->phy_id_get (dev_id, phy_id, &phy_data); - SW_RTN_ON_ERROR (rv); - - *org_id = (phy_data >> 16) & 0xffff; - *rev_id = phy_data & 0xffff; - - return rv; -} - -static sw_error_t -_shiva_port_speed_get(a_uint32_t dev_id, fal_port_t port_id, - fal_port_speed_t * pspeed) -{ - sw_error_t rv; - a_uint32_t phy_id; - hsl_phy_ops_t *phy_drv; - - HSL_DEV_ID_CHECK(dev_id); - - if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_PHY)) - { - return SW_BAD_PARAM; - } - - SW_RTN_ON_NULL (phy_drv = hsl_phy_api_ops_get (dev_id, port_id)); - if (NULL == phy_drv->phy_speed_get) - return SW_NOT_SUPPORTED; - - rv = hsl_port_prop_get_phyid(dev_id, port_id, &phy_id); - SW_RTN_ON_ERROR(rv); - - rv = phy_drv->phy_speed_get(dev_id, phy_id, pspeed); - - return rv; -} - -static sw_error_t -_shiva_port_autoneg_status_get(a_uint32_t dev_id, fal_port_t port_id, - a_bool_t * status) -{ - a_uint32_t phy_id; - sw_error_t rv; - hsl_phy_ops_t *phy_drv; - - HSL_DEV_ID_CHECK(dev_id); - - if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_PHY)) - { - return SW_BAD_PARAM; - } - - SW_RTN_ON_NULL (phy_drv = hsl_phy_api_ops_get (dev_id, port_id)); - if (NULL == phy_drv->phy_autoneg_status_get) - return SW_NOT_SUPPORTED; - - rv = hsl_port_prop_get_phyid(dev_id, port_id, &phy_id); - SW_RTN_ON_ERROR(rv); - - *status = phy_drv->phy_autoneg_status_get(dev_id, phy_id); - - return SW_OK; -} - -static sw_error_t -_shiva_port_autoneg_enable(a_uint32_t dev_id, fal_port_t port_id) -{ - sw_error_t rv; - a_uint32_t phy_id; - hsl_phy_ops_t *phy_drv; - - HSL_DEV_ID_CHECK(dev_id); - - if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_PHY)) - { - return SW_BAD_PARAM; - } - - SW_RTN_ON_NULL (phy_drv = hsl_phy_api_ops_get (dev_id, port_id)); - if (NULL == phy_drv->phy_autoneg_enable_set) - return SW_NOT_SUPPORTED; - - rv = hsl_port_prop_get_phyid(dev_id, port_id, &phy_id); - SW_RTN_ON_ERROR(rv); - - rv = phy_drv->phy_autoneg_enable_set(dev_id, phy_id); - return rv; -} - -static sw_error_t -_shiva_port_autoneg_restart(a_uint32_t dev_id, fal_port_t port_id) -{ - sw_error_t rv; - a_uint32_t phy_id; - hsl_phy_ops_t *phy_drv; - - HSL_DEV_ID_CHECK(dev_id); - - if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_PHY)) - { - return SW_BAD_PARAM; - } - - SW_RTN_ON_NULL (phy_drv = hsl_phy_api_ops_get (dev_id, port_id)); - if (NULL == phy_drv->phy_restart_autoneg) - return SW_NOT_SUPPORTED; - - rv = hsl_port_prop_get_phyid(dev_id, port_id, &phy_id); - SW_RTN_ON_ERROR(rv); - - rv = phy_drv->phy_restart_autoneg(dev_id, phy_id); - return rv; -} - -static sw_error_t -_shiva_port_autoneg_adv_set(a_uint32_t dev_id, fal_port_t port_id, - a_uint32_t autoadv) -{ - sw_error_t rv; - a_uint32_t phy_id; - hsl_phy_ops_t *phy_drv; - - HSL_DEV_ID_CHECK(dev_id); - - if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_PHY)) - { - return SW_BAD_PARAM; - } - - SW_RTN_ON_NULL (phy_drv = hsl_phy_api_ops_get (dev_id, port_id)); - if (NULL == phy_drv->phy_autoneg_adv_set) - return SW_NOT_SUPPORTED; - - rv = hsl_port_prop_get_phyid(dev_id, port_id, &phy_id); - SW_RTN_ON_ERROR(rv); - - rv = phy_drv->phy_autoneg_adv_set(dev_id, phy_id, autoadv); - SW_RTN_ON_ERROR(rv); - - return SW_OK; -} - -static sw_error_t -_shiva_port_autoneg_adv_get(a_uint32_t dev_id, fal_port_t port_id, - a_uint32_t * autoadv) -{ - sw_error_t rv; - a_uint32_t phy_id; - hsl_phy_ops_t *phy_drv; - - HSL_DEV_ID_CHECK(dev_id); - - if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_PHY)) - { - return SW_BAD_PARAM; - } - - SW_RTN_ON_NULL (phy_drv = hsl_phy_api_ops_get (dev_id, port_id)); - if (NULL == phy_drv->phy_autoneg_adv_get) - return SW_NOT_SUPPORTED; - - rv = hsl_port_prop_get_phyid(dev_id, port_id, &phy_id); - SW_RTN_ON_ERROR(rv); - - *autoadv = 0; - rv = phy_drv->phy_autoneg_adv_get(dev_id, phy_id, autoadv); - SW_RTN_ON_ERROR(rv); - - return SW_OK; -} - -static sw_error_t -_shiva_port_hdr_status_set(a_uint32_t dev_id, fal_port_t port_id, - a_bool_t enable) -{ - sw_error_t rv; - a_uint32_t val; - - HSL_DEV_ID_CHECK(dev_id); - - if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU)) - { - return SW_BAD_PARAM; - } - - if (A_TRUE == enable) - { - val = 1; - } - else if (A_FALSE == enable) - { - val = 0; - } - else - { - return SW_BAD_PARAM; - } - - HSL_REG_FIELD_SET(rv, dev_id, PORT_CTL, port_id, HEAD_EN, - (a_uint8_t *) (&val), sizeof (a_uint32_t)); - - return rv; -} - -static sw_error_t -_shiva_port_hdr_status_get(a_uint32_t dev_id, fal_port_t port_id, - a_bool_t * enable) -{ - sw_error_t rv; - a_uint32_t val = 0; - - HSL_DEV_ID_CHECK(dev_id); - - if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU)) - { - return SW_BAD_PARAM; - } - - HSL_REG_FIELD_GET(rv, dev_id, PORT_CTL, port_id, HEAD_EN, - (a_uint8_t *) (&val), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - - if (1 == val) - { - *enable = A_TRUE; - } - else - { - *enable = A_FALSE; - } - - return SW_OK; -} - -static sw_error_t -_shiva_port_flowctrl_set(a_uint32_t dev_id, fal_port_t port_id, a_bool_t enable) -{ - sw_error_t rv; - a_uint32_t val, force, reg = 0, tmp; - - if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU)) - { - return SW_BAD_PARAM; - } - - if (A_TRUE == enable) - { - val = 1; - } - else if (A_FALSE == enable) - { - val = 0; - } - else - { - return SW_BAD_PARAM; - } - - HSL_REG_ENTRY_GET(rv, dev_id, PORT_STATUS, port_id, - (a_uint8_t *) (®), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - - SW_GET_FIELD_BY_REG(PORT_STATUS, FLOW_LINK_EN, force, reg); - if (force) - { - /* flow control isn't in force mode so can't set */ - return SW_DISABLE; - } - tmp = reg; - - SW_SET_REG_BY_FIELD(PORT_STATUS, RX_FLOW_EN, val, reg); - SW_SET_REG_BY_FIELD(PORT_STATUS, TX_FLOW_EN, val, reg); - SW_SET_REG_BY_FIELD(PORT_STATUS, TX_HALF_FLOW_EN, val, reg); - if (tmp == reg) - return SW_OK; - - HSL_REG_ENTRY_SET(rv, dev_id, PORT_STATUS, port_id, - (a_uint8_t *) (®), sizeof (a_uint32_t)); - return rv; -} - -static sw_error_t -_shiva_port_flowctrl_get(a_uint32_t dev_id, fal_port_t port_id, - a_bool_t * enable) -{ - sw_error_t rv; - a_uint32_t rx, reg = 0; - - if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU)) - { - return SW_BAD_PARAM; - } - - HSL_REG_ENTRY_GET(rv, dev_id, PORT_STATUS, port_id, - (a_uint8_t *) (®), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - - SW_GET_FIELD_BY_REG(PORT_STATUS, RX_FLOW_EN, rx, reg); - - if (1 == rx) - { - *enable = A_TRUE; - } - else - { - *enable = A_FALSE; - } - - return rv; -} - -static sw_error_t -_shiva_port_flowctrl_forcemode_set(a_uint32_t dev_id, fal_port_t port_id, - a_bool_t enable) -{ - sw_error_t rv; - a_uint32_t force, reg; - - if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU)) - { - return SW_BAD_PARAM; - } - - HSL_REG_ENTRY_GET(rv, dev_id, PORT_STATUS, port_id, - (a_uint8_t *) (®), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - - SW_GET_FIELD_BY_REG(PORT_STATUS, FLOW_LINK_EN, force, reg); - if (force != (a_uint32_t) enable) - { - return SW_OK; - } - - if (A_TRUE == enable) - { - SW_SET_REG_BY_FIELD(PORT_STATUS, FLOW_LINK_EN, 0, reg); - SW_SET_REG_BY_FIELD(PORT_STATUS, TX_FLOW_EN, 0, reg); - SW_SET_REG_BY_FIELD(PORT_STATUS, RX_FLOW_EN, 0, reg); - } - else if (A_FALSE == enable) - { - SW_SET_REG_BY_FIELD(PORT_STATUS, FLOW_LINK_EN, 1, reg); - } - else - { - return SW_BAD_PARAM; - } - SW_SET_REG_BY_FIELD(PORT_STATUS, TX_HALF_FLOW_EN, 0, reg); - - HSL_REG_ENTRY_SET(rv, dev_id, PORT_STATUS, port_id, - (a_uint8_t *) (®), sizeof (a_uint32_t)); - return rv; -} - -static sw_error_t -_shiva_port_flowctrl_forcemode_get(a_uint32_t dev_id, fal_port_t port_id, - a_bool_t * enable) -{ - sw_error_t rv; - a_uint32_t force, reg; - - if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU)) - { - return SW_BAD_PARAM; - } - - HSL_REG_ENTRY_GET(rv, dev_id, PORT_STATUS, port_id, - (a_uint8_t *) (®), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - - SW_GET_FIELD_BY_REG(PORT_STATUS, FLOW_LINK_EN, force, reg); - if (0 == force) - { - *enable = A_TRUE; - } - else - { - *enable = A_FALSE; - } - - return SW_OK; -} - -static sw_error_t -_shiva_port_powersave_set(a_uint32_t dev_id, fal_port_t port_id, - a_bool_t enable) -{ - sw_error_t rv; - a_uint32_t phy_id = 0; - hsl_phy_ops_t *phy_drv; - - HSL_DEV_ID_CHECK(dev_id); - - if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_PHY)) - { - return SW_BAD_PARAM; - } - - SW_RTN_ON_NULL (phy_drv = hsl_phy_api_ops_get (dev_id, port_id)); - if (NULL == phy_drv->phy_powersave_set) - return SW_NOT_SUPPORTED; - - rv = hsl_port_prop_get_phyid(dev_id, port_id, &phy_id); - SW_RTN_ON_ERROR(rv); - - rv = phy_drv->phy_powersave_set(dev_id, phy_id, enable); - - return rv; -} - -static sw_error_t -_shiva_port_powersave_get(a_uint32_t dev_id, fal_port_t port_id, - a_bool_t *enable) -{ - sw_error_t rv; - a_uint32_t phy_id = 0; - hsl_phy_ops_t *phy_drv; - - HSL_DEV_ID_CHECK(dev_id); - - if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_PHY)) - { - return SW_BAD_PARAM; - } - - SW_RTN_ON_NULL (phy_drv = hsl_phy_api_ops_get (dev_id, port_id)); - if (NULL == phy_drv->phy_powersave_get) - return SW_NOT_SUPPORTED; - - rv = hsl_port_prop_get_phyid(dev_id, port_id, &phy_id); - SW_RTN_ON_ERROR(rv); - - rv = phy_drv->phy_powersave_get(dev_id, phy_id, enable); - - return rv; -} - -static sw_error_t -_shiva_port_hibernate_set(a_uint32_t dev_id, fal_port_t port_id, - a_bool_t enable) -{ - sw_error_t rv; - a_uint32_t phy_id = 0; - hsl_phy_ops_t *phy_drv; - - HSL_DEV_ID_CHECK(dev_id); - - if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_PHY)) - { - return SW_BAD_PARAM; - } - - SW_RTN_ON_NULL (phy_drv = hsl_phy_api_ops_get (dev_id, port_id)); - if (NULL == phy_drv->phy_hibernation_set) - return SW_NOT_SUPPORTED; - - rv = hsl_port_prop_get_phyid(dev_id, port_id, &phy_id); - SW_RTN_ON_ERROR(rv); - - rv = phy_drv->phy_hibernation_set(dev_id, phy_id, enable); - - return rv; -} - -static sw_error_t -_shiva_port_hibernate_get(a_uint32_t dev_id, fal_port_t port_id, - a_bool_t *enable) -{ - sw_error_t rv; - a_uint32_t phy_id = 0; - hsl_phy_ops_t *phy_drv; - - HSL_DEV_ID_CHECK(dev_id); - - if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_PHY)) - { - return SW_BAD_PARAM; - } - - SW_RTN_ON_NULL (phy_drv = hsl_phy_api_ops_get (dev_id, port_id)); - if (NULL == phy_drv->phy_hibernation_get) - return SW_NOT_SUPPORTED; - - rv = hsl_port_prop_get_phyid(dev_id, port_id, &phy_id); - SW_RTN_ON_ERROR(rv); - - rv = phy_drv->phy_hibernation_get(dev_id, phy_id, enable); - - return rv; -} - -static sw_error_t -_shiva_port_cdt(a_uint32_t dev_id, fal_port_t port_id, a_uint32_t mdi_pair, - fal_cable_status_t *cable_status, a_uint32_t *cable_len) -{ - sw_error_t rv; - a_uint32_t phy_id = 0; - hsl_phy_ops_t *phy_drv; - - HSL_DEV_ID_CHECK(dev_id); - - if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_PHY)) - { - return SW_BAD_PARAM; - } - - SW_RTN_ON_NULL (phy_drv = hsl_phy_api_ops_get (dev_id, port_id)); - if (NULL == phy_drv->phy_cdt) - return SW_NOT_SUPPORTED; - - rv = hsl_port_prop_get_phyid(dev_id, port_id, &phy_id); - SW_RTN_ON_ERROR(rv); - - rv = phy_drv->phy_cdt(dev_id, phy_id, mdi_pair, cable_status, cable_len); - - return rv; -} - -static sw_error_t -_shiva_port_link_status_get(a_uint32_t dev_id, fal_port_t port_id, a_bool_t *status) -{ - sw_error_t rv; - a_uint32_t phy_id = 0; - hsl_phy_ops_t *phy_drv; - - HSL_DEV_ID_CHECK(dev_id); - - if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_PHY)) - { - return SW_BAD_PARAM; - } - - SW_RTN_ON_NULL (phy_drv = hsl_phy_api_ops_get (dev_id, port_id)); - if (NULL == phy_drv->phy_link_status_get) - return SW_NOT_SUPPORTED; - - rv = hsl_port_prop_get_phyid(dev_id, port_id, &phy_id); - SW_RTN_ON_ERROR(rv); - - *status = phy_drv->phy_link_status_get(dev_id, phy_id); - - return rv; -} - -static sw_error_t -_shiva_port_txfc_status_get(a_uint32_t dev_id, fal_port_t port_id, a_bool_t *enable) -{ - sw_error_t rv; - a_uint32_t tx_fc_full, tx_fc_half, reg = 0; - - if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU)) - { - return SW_BAD_PARAM; - } - - HSL_REG_ENTRY_GET(rv, dev_id, PORT_STATUS, port_id, - (a_uint8_t *) (®), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - - SW_GET_FIELD_BY_REG(PORT_STATUS, TX_FLOW_EN, tx_fc_full, reg); - SW_GET_FIELD_BY_REG(PORT_STATUS, TX_HALF_FLOW_EN, tx_fc_half, reg); - if (TX_FC_FULL_EN == tx_fc_full && TX_FC_HALF_EN == tx_fc_half) - { - *enable = A_TRUE; - } - else - { - *enable = A_FALSE; - } - - return rv; -} - -static sw_error_t -_shiva_port_txfc_status_set(a_uint32_t dev_id, fal_port_t port_id, a_bool_t enable) -{ - sw_error_t rv; - a_uint32_t force, reg = 0, tmp; - - if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU)) - { - return SW_BAD_PARAM; - } - - if (A_TRUE != enable && A_FALSE != enable) - { - return SW_BAD_PARAM; - } - - HSL_REG_ENTRY_GET(rv, dev_id, PORT_STATUS, port_id, - (a_uint8_t *) (®), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - - SW_GET_FIELD_BY_REG(PORT_STATUS, FLOW_LINK_EN, force, reg); - if (force) - { - /* flow control isn't in force mode so can't set */ - return SW_DISABLE; - } - tmp = reg; - SW_SET_REG_BY_FIELD(PORT_STATUS, TX_FLOW_EN, enable, reg); - SW_SET_REG_BY_FIELD(PORT_STATUS, TX_HALF_FLOW_EN, enable, reg); - if (tmp == reg) - return SW_OK; - - HSL_REG_ENTRY_SET(rv, dev_id, PORT_STATUS, port_id, - (a_uint8_t *) (®), sizeof (a_uint32_t)); - - return rv; -} - -static sw_error_t -_shiva_port_rxfc_status_get(a_uint32_t dev_id, fal_port_t port_id, a_bool_t *enable) -{ - sw_error_t rv; - a_uint32_t rx_fc, reg = 0; - - if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU)) - { - return SW_BAD_PARAM; - } - - HSL_REG_ENTRY_GET(rv, dev_id, PORT_STATUS, port_id, - (a_uint8_t *) (®), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - - SW_GET_FIELD_BY_REG(PORT_STATUS, RX_FLOW_EN, rx_fc, reg); - if (RX_FC_EN == rx_fc) - { - *enable = A_TRUE; - } - else - { - *enable = A_FALSE; - } - - return rv; -} - -static sw_error_t -_shiva_port_rxfc_status_set(a_uint32_t dev_id, fal_port_t port_id, a_bool_t enable) -{ - sw_error_t rv; - a_uint32_t force, reg = 0, tmp; - - if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU)) - { - return SW_BAD_PARAM; - } - - if (A_TRUE != enable && A_FALSE != enable) - { - return SW_BAD_PARAM; - } - - HSL_REG_ENTRY_GET(rv, dev_id, PORT_STATUS, port_id, - (a_uint8_t *) (®), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - - SW_GET_FIELD_BY_REG(PORT_STATUS, FLOW_LINK_EN, force, reg); - if (force) - { - /* flow control isn't in force mode so can't set */ - return SW_DISABLE; - } - tmp = reg; - - SW_SET_REG_BY_FIELD(PORT_STATUS, RX_FLOW_EN, enable, reg); - if (tmp == reg) - return SW_OK; - - HSL_REG_ENTRY_SET(rv, dev_id, PORT_STATUS, port_id, - (a_uint8_t *) (®), sizeof (a_uint32_t)); - - return rv; -} - -/** - * @brief Set duplex mode on a particular port. - * @param[in] dev_id device id - * @param[in] port_id port id - * @param[in] duplex duplex mode - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -shiva_port_duplex_set(a_uint32_t dev_id, fal_port_t port_id, - fal_port_duplex_t duplex) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _shiva_port_duplex_set(dev_id, port_id, duplex); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Get duplex mode on a particular port. - * @param[in] dev_id device id - * @param[in] port_id port id - * @param[out] duplex duplex mode - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -shiva_port_duplex_get(a_uint32_t dev_id, fal_port_t port_id, - fal_port_duplex_t * pduplex) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _shiva_port_duplex_get(dev_id, port_id, pduplex); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Set speed on a particular port. - * @param[in] dev_id device id - * @param[in] port_id port id - * @param[in] speed port speed - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -shiva_port_speed_set(a_uint32_t dev_id, fal_port_t port_id, - fal_port_speed_t speed) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _shiva_port_speed_set(dev_id, port_id, speed); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Get phy id on a particular port. - * @param[in] dev_id device id - * @param[in] port_id port id - * @param[out] org_id and rev_id - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -shiva_port_phy_id_get (a_uint32_t dev_id, fal_port_t port_id, - a_uint16_t * org_id, a_uint16_t * rev_id) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _shiva_port_phy_id_get (dev_id, port_id, org_id, rev_id); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Get speed on a particular port. - * @param[in] dev_id device id - * @param[in] port_id port id - * @param[out] speed port speed - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -shiva_port_speed_get(a_uint32_t dev_id, fal_port_t port_id, - fal_port_speed_t * pspeed) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _shiva_port_speed_get(dev_id, port_id, pspeed); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Get auto negotiation status on a particular port. - * @param[in] dev_id device id - * @param[in] port_id port id - * @param[out] status A_TRUE or A_FALSE - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -shiva_port_autoneg_status_get(a_uint32_t dev_id, fal_port_t port_id, - a_bool_t * status) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _shiva_port_autoneg_status_get(dev_id, port_id, status); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Enable auto negotiation status on a particular port. - * @param[in] dev_id device id - * @param[in] port_id port id - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -shiva_port_autoneg_enable(a_uint32_t dev_id, fal_port_t port_id) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _shiva_port_autoneg_enable(dev_id, port_id); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Restart auto negotiation procedule on a particular port. - * @param[in] dev_id device id - * @param[in] port_id port id - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -shiva_port_autoneg_restart(a_uint32_t dev_id, fal_port_t port_id) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _shiva_port_autoneg_restart(dev_id, port_id); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Set auto negotiation advtisement ability on a particular port. - * @details Comments: - * auto negotiation advtisement ability is defined by macro such as - * FAL_PHY_ADV_10T_HD, FAL_PHY_ADV_PAUSE... - * @param[in] dev_id device id - * @param[in] port_id port id - * @param[in] autoadv auto negotiation advtisement ability bit map - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -shiva_port_autoneg_adv_set(a_uint32_t dev_id, fal_port_t port_id, - a_uint32_t autoadv) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _shiva_port_autoneg_adv_set(dev_id, port_id, autoadv); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Get auto negotiation advtisement ability on a particular port. - * @param[in] dev_id device id - * @param[in] port_id port id - * @param[out] autoadv auto negotiation advtisement ability bit map - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -shiva_port_autoneg_adv_get(a_uint32_t dev_id, fal_port_t port_id, - a_uint32_t * autoadv) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _shiva_port_autoneg_adv_get(dev_id, port_id, autoadv); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Set status of Atheros header packets parsed on a particular port. - * @param[in] dev_id device id - * @param[in] port_id port id - * @param[in] enable A_TRUE or A_FALSE - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -shiva_port_hdr_status_set(a_uint32_t dev_id, fal_port_t port_id, - a_bool_t enable) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _shiva_port_hdr_status_set(dev_id, port_id, enable); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Get status of Atheros header packets parsed on a particular port. - * @param[in] dev_id device id - * @param[in] port_id port id - * @param[out] enable A_TRUE or A_FALSE - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -shiva_port_hdr_status_get(a_uint32_t dev_id, fal_port_t port_id, - a_bool_t * enable) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _shiva_port_hdr_status_get(dev_id, port_id, enable); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Set flow control status on a particular port. - * @param[in] dev_id device id - * @param[in] port_id port id - * @param[in] enable A_TRUE or A_FALSE - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -shiva_port_flowctrl_set(a_uint32_t dev_id, fal_port_t port_id, a_bool_t enable) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _shiva_port_flowctrl_set(dev_id, port_id, enable); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Get flow control status on a particular port. - * @param[in] dev_id device id - * @param[in] port_id port id - * @param[out] enable A_TRUE or A_FALSE - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -shiva_port_flowctrl_get(a_uint32_t dev_id, fal_port_t port_id, - a_bool_t * enable) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _shiva_port_flowctrl_get(dev_id, port_id, enable); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Set flow control force mode on a particular port. - * @param[in] dev_id device id - * @param[in] port_id port id - * @param[out] enable A_TRUE or A_FALSE - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -shiva_port_flowctrl_forcemode_set(a_uint32_t dev_id, fal_port_t port_id, - a_bool_t enable) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _shiva_port_flowctrl_forcemode_set(dev_id, port_id, enable); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Get flow control force mode on a particular port. - * @param[in] dev_id device id - * @param[in] port_id port id - * @param[out] enable A_TRUE or A_FALSE - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -shiva_port_flowctrl_forcemode_get(a_uint32_t dev_id, fal_port_t port_id, - a_bool_t * enable) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _shiva_port_flowctrl_forcemode_get(dev_id, port_id, enable); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Set powersaving status on a particular port. - * @param[in] dev_id device id - * @param[in] port_id port id - * @param[out] enable A_TRUE or A_FALSE - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -shiva_port_powersave_set(a_uint32_t dev_id, fal_port_t port_id, - a_bool_t enable) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _shiva_port_powersave_set(dev_id, port_id, enable); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Get powersaving status on a particular port. - * @param[in] dev_id device id - * @param[in] port_id port id - * @param[out] enable A_TRUE or A_FALSE - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -shiva_port_powersave_get(a_uint32_t dev_id, fal_port_t port_id, - a_bool_t *enable) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _shiva_port_powersave_get(dev_id, port_id, enable); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Set hibernate status on a particular port. - * @param[in] dev_id device id - * @param[in] port_id port id - * @param[out] enable A_TRUE or A_FALSE - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -shiva_port_hibernate_set(a_uint32_t dev_id, fal_port_t port_id, - a_bool_t enable) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _shiva_port_hibernate_set(dev_id, port_id, enable); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Get hibernate status on a particular port. - * @param[in] dev_id device id - * @param[in] port_id port id - * @param[out] enable A_TRUE or A_FALSE - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -shiva_port_hibernate_get(a_uint32_t dev_id, fal_port_t port_id, - a_bool_t *enable) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _shiva_port_hibernate_get(dev_id, port_id, enable); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Run cable diagnostic test on a particular port. - * @param[in] dev_id device id - * @param[in] port_id port id - * @param[in] mdi_pair mdi pair id - * @param[out] cable_status cable status - * @param[out] cable_len cable len - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -shiva_port_cdt(a_uint32_t dev_id, fal_port_t port_id, a_uint32_t mdi_pair, - fal_cable_status_t *cable_status, a_uint32_t *cable_len) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _shiva_port_cdt(dev_id, port_id, mdi_pair, cable_status, cable_len); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Get linkstatus on a particular port. - * @param[in] dev_id device id - * @param[in] port_id port id - * @param[out] status A_TRUE or A_FALSE - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -shiva_port_link_status_get(a_uint32_t dev_id, fal_port_t port_id, - a_bool_t *status) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _shiva_port_link_status_get(dev_id, port_id, status); - HSL_API_UNLOCK; - - return rv; -} - -/** - * @brief Get txfc status on a particular port. - * @param[in] dev_id device id - * @param[in] port_id port id - * @param[out] enable A_TRUE or A_FALSE - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -shiva_port_txfc_status_get(a_uint32_t dev_id, fal_port_t port_id, - a_bool_t * enable) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _shiva_port_txfc_status_get(dev_id, port_id, enable); - HSL_API_UNLOCK; - - return rv; -} - -/** - * @brief Set tx flow control status on a particular port. - * @param[in] dev_id device id - * @param[in] port_id port id - * @param[in] enable A_TRUE or A_FALSE - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -shiva_port_txfc_status_set(a_uint32_t dev_id, fal_port_t port_id, a_bool_t enable) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _shiva_port_txfc_status_set(dev_id, port_id, enable); - HSL_API_UNLOCK; - - return rv; -} - -/** - * @brief Get rxfc status on a particular port. - * @param[in] dev_id device id - * @param[in] port_id port id - * @param[out] enable A_TRUE or A_FALSE - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -shiva_port_rxfc_status_get(a_uint32_t dev_id, fal_port_t port_id, - a_bool_t * enable) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _shiva_port_rxfc_status_get(dev_id, port_id, enable); - HSL_API_UNLOCK; - - return rv; -} - -/** - * @brief Set rx flow control status on a particular port. - * @param[in] dev_id device id - * @param[in] port_id port id - * @param[in] enable A_TRUE or A_FALSE - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -shiva_port_rxfc_status_set(a_uint32_t dev_id, fal_port_t port_id, a_bool_t enable) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _shiva_port_rxfc_status_set(dev_id, port_id, enable); - HSL_API_UNLOCK; - - return rv; -} - -sw_error_t -shiva_port_ctrl_init(a_uint32_t dev_id) -{ - HSL_DEV_ID_CHECK(dev_id); - -#ifndef HSL_STANDALONG - { - hsl_api_t *p_api; - - SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id)); - - p_api->port_duplex_get = shiva_port_duplex_get; - p_api->port_duplex_set = shiva_port_duplex_set; - p_api->port_speed_get = shiva_port_speed_get; - p_api->port_speed_set = shiva_port_speed_set; - p_api->port_phy_id_get = shiva_port_phy_id_get; - p_api->port_autoneg_status_get = shiva_port_autoneg_status_get; - p_api->port_autoneg_enable = shiva_port_autoneg_enable; - p_api->port_autoneg_restart = shiva_port_autoneg_restart; - p_api->port_autoneg_adv_get = shiva_port_autoneg_adv_get; - p_api->port_autoneg_adv_set = shiva_port_autoneg_adv_set; - p_api->port_hdr_status_set = shiva_port_hdr_status_set; - p_api->port_hdr_status_get = shiva_port_hdr_status_get; - p_api->port_flowctrl_set = shiva_port_flowctrl_set; - p_api->port_flowctrl_get = shiva_port_flowctrl_get; - p_api->port_flowctrl_forcemode_set = shiva_port_flowctrl_forcemode_set; - p_api->port_flowctrl_forcemode_get = shiva_port_flowctrl_forcemode_get; - p_api->port_powersave_set = shiva_port_powersave_set; - p_api->port_powersave_get = shiva_port_powersave_get; - p_api->port_hibernate_set = shiva_port_hibernate_set; - p_api->port_hibernate_get = shiva_port_hibernate_get; - p_api->port_cdt = shiva_port_cdt; - p_api->port_link_status_get = shiva_port_link_status_get; - p_api->port_txfc_status_get = shiva_port_txfc_status_get; - p_api->port_txfc_status_set = shiva_port_txfc_status_set; - p_api->port_rxfc_status_get = shiva_port_rxfc_status_get; - p_api->port_rxfc_status_set = shiva_port_rxfc_status_set; - } -#endif - - return SW_OK; -} - -/** - * @} - */ - diff --git a/feeds/ipq807x/qca-ssdk/src/src/hsl/shiva/shiva_portvlan.c b/feeds/ipq807x/qca-ssdk/src/src/hsl/shiva/shiva_portvlan.c deleted file mode 100755 index b9292b060..000000000 --- a/feeds/ipq807x/qca-ssdk/src/src/hsl/shiva/shiva_portvlan.c +++ /dev/null @@ -1,1859 +0,0 @@ -/* - * Copyright (c) 2012, 2016, The Linux Foundation. All rights reserved. - * Permission to use, copy, modify, and/or distribute this software for - * any purpose with or without fee is hereby granted, provided that the - * above copyright notice and this permission notice appear in all copies. - * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES - * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR - * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES - * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN - * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT - * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. - */ - - -/** - * @defgroup shiva_port_vlan SHIVA_PORT_VLAN - * @{ - */ -#include "sw.h" -#include "hsl.h" -#include "hsl_dev.h" -#include "hsl_port_prop.h" -#include "shiva_portvlan.h" -#include "shiva_reg.h" - -#define MAX_VLAN_ID 4095 -#define SHIVA_MAX_VLAN_TRANS 16 -#define SHIVA_VLAN_TRANS_ADDR 0x59000 - -static sw_error_t -_shiva_port_1qmode_set(a_uint32_t dev_id, fal_port_t port_id, - fal_pt_1qmode_t port_1qmode) -{ - sw_error_t rv; - a_uint32_t regval[FAL_1Q_MODE_BUTT] = { 0, 3, 2, 1 }; - - HSL_DEV_ID_CHECK(dev_id); - - if (A_FALSE == hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU)) - { - return SW_BAD_PARAM; - } - - if (FAL_1Q_MODE_BUTT <= port_1qmode) - { - return SW_BAD_PARAM; - } - - HSL_REG_FIELD_SET(rv, dev_id, PORT_BASE_VLAN, port_id, DOT1Q_MODE, - (a_uint8_t *) (®val[port_1qmode]), - sizeof (a_uint32_t)); - - return rv; - -} - -static sw_error_t -_shiva_port_1qmode_get(a_uint32_t dev_id, fal_port_t port_id, - fal_pt_1qmode_t * pport_1qmode) -{ - sw_error_t rv; - a_uint32_t regval = 0; - fal_pt_1qmode_t retval[4] = { FAL_1Q_DISABLE, FAL_1Q_FALLBACK, - FAL_1Q_CHECK, FAL_1Q_SECURE - }; - - HSL_DEV_ID_CHECK(dev_id); - - if (A_FALSE == hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU)) - { - return SW_BAD_PARAM; - } - - SW_RTN_ON_NULL(pport_1qmode); - - HSL_REG_FIELD_GET(rv, dev_id, PORT_BASE_VLAN, port_id, DOT1Q_MODE, - (a_uint8_t *) (®val), sizeof (a_uint32_t)); - - SW_RTN_ON_ERROR(rv); - - *pport_1qmode = retval[regval & 0x3]; - - return SW_OK; - -} - -static sw_error_t -_shiva_port_egvlanmode_set(a_uint32_t dev_id, fal_port_t port_id, - fal_pt_1q_egmode_t port_egvlanmode) -{ - sw_error_t rv; - a_uint32_t regval[FAL_EG_MODE_BUTT] = { 0, 1, 2, 3}; - - HSL_DEV_ID_CHECK(dev_id); - - if (A_FALSE == hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU)) - { - return SW_BAD_PARAM; - } - - if (FAL_EG_MODE_BUTT <= port_egvlanmode) - { - return SW_BAD_PARAM; - } - - HSL_REG_FIELD_SET(rv, dev_id, PORT_CTL, port_id, EG_VLAN_MODE, - (a_uint8_t *) (®val[port_egvlanmode]), - sizeof (a_uint32_t)); - - return rv; - -} - -static sw_error_t -_shiva_port_egvlanmode_get(a_uint32_t dev_id, fal_port_t port_id, - fal_pt_1q_egmode_t * pport_egvlanmode) -{ - sw_error_t rv; - a_uint32_t regval = 0; - fal_pt_1q_egmode_t retval[4] = { FAL_EG_UNMODIFIED, FAL_EG_UNTAGGED, - FAL_EG_TAGGED, FAL_EG_HYBRID - }; - - HSL_DEV_ID_CHECK(dev_id); - - if (A_FALSE == hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU)) - { - return SW_BAD_PARAM; - } - - SW_RTN_ON_NULL(pport_egvlanmode); - - HSL_REG_FIELD_GET(rv, dev_id, PORT_CTL, port_id, EG_VLAN_MODE, - (a_uint8_t *) (®val), sizeof (a_uint32_t)); - - SW_RTN_ON_ERROR(rv); - - *pport_egvlanmode = retval[regval & 0x3]; - - return SW_OK; - -} - -static sw_error_t -_shiva_portvlan_member_add(a_uint32_t dev_id, fal_port_t port_id, - a_uint32_t mem_port_id) -{ - sw_error_t rv; - a_uint32_t regval = 0; - - HSL_DEV_ID_CHECK(dev_id); - - if (A_FALSE == hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU)) - { - return SW_BAD_PARAM; - } - - if (A_FALSE == hsl_port_prop_check(dev_id, mem_port_id, HSL_PP_INCL_CPU)) - { - return SW_BAD_PARAM; - } - - HSL_REG_FIELD_GET(rv, dev_id, PORT_BASE_VLAN, port_id, - PORT_VID_MEM, (a_uint8_t *) (®val), - sizeof (a_uint32_t)); - - SW_RTN_ON_ERROR(rv); - - regval |= (0x1UL << mem_port_id); - - HSL_REG_FIELD_SET(rv, dev_id, PORT_BASE_VLAN, port_id, - PORT_VID_MEM, (a_uint8_t *) (®val), - sizeof (a_uint32_t)); - - return rv; - -} - -static sw_error_t -_shiva_portvlan_member_del(a_uint32_t dev_id, fal_port_t port_id, - a_uint32_t mem_port_id) -{ - sw_error_t rv; - a_uint32_t regval = 0; - - HSL_DEV_ID_CHECK(dev_id); - - if (A_FALSE == hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU)) - { - return SW_BAD_PARAM; - } - - if (A_FALSE == hsl_port_prop_check(dev_id, mem_port_id, HSL_PP_INCL_CPU)) - { - return SW_BAD_PARAM; - } - - HSL_REG_FIELD_GET(rv, dev_id, PORT_BASE_VLAN, port_id, - PORT_VID_MEM, (a_uint8_t *) (®val), - sizeof (a_uint32_t)); - - SW_RTN_ON_ERROR(rv); - - regval &= (~(0x1UL << mem_port_id)); - - HSL_REG_FIELD_SET(rv, dev_id, PORT_BASE_VLAN, port_id, - PORT_VID_MEM, (a_uint8_t *) (®val), - sizeof (a_uint32_t)); - - return rv; - -} - -static sw_error_t -_shiva_portvlan_member_update(a_uint32_t dev_id, fal_port_t port_id, - fal_pbmp_t mem_port_map) -{ - sw_error_t rv; - - HSL_DEV_ID_CHECK(dev_id); - - if (A_FALSE == hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU)) - { - return SW_BAD_PARAM; - } - - if (A_FALSE == - hsl_mports_prop_check(dev_id, mem_port_map, HSL_PP_INCL_CPU)) - { - return SW_BAD_PARAM; - } - - HSL_REG_FIELD_SET(rv, dev_id, PORT_BASE_VLAN, port_id, - PORT_VID_MEM, (a_uint8_t *) (&mem_port_map), - sizeof (a_uint32_t)); - - return rv; -} - -static sw_error_t -_shiva_portvlan_member_get(a_uint32_t dev_id, fal_port_t port_id, - fal_pbmp_t * mem_port_map) -{ - sw_error_t rv; - - HSL_DEV_ID_CHECK(dev_id); - - if (A_FALSE == hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU)) - { - return SW_BAD_PARAM; - } - - *mem_port_map = 0; - HSL_REG_FIELD_GET(rv, dev_id, PORT_BASE_VLAN, port_id, - PORT_VID_MEM, (a_uint8_t *) mem_port_map, - sizeof (a_uint32_t)); - - SW_RTN_ON_ERROR(rv); - - return SW_OK; -} - -static sw_error_t -_shiva_port_force_default_vid_set(a_uint32_t dev_id, fal_port_t port_id, a_bool_t enable) -{ - sw_error_t rv; - a_uint32_t val; - - HSL_DEV_ID_CHECK(dev_id); - - if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU)) - { - return SW_BAD_PARAM; - } - - if (A_TRUE == enable) - { - val = 1; - } - else if (A_FALSE == enable) - { - val = 0; - } - else - { - return SW_BAD_PARAM; - } - - HSL_REG_FIELD_SET(rv, dev_id, PORT_DOT1AD, port_id, - FORCE_DEF_VID, (a_uint8_t *) (&val), - sizeof (a_uint32_t)); - return rv; -} - -static sw_error_t -_shiva_port_force_default_vid_get(a_uint32_t dev_id, fal_port_t port_id, a_bool_t * enable) -{ - sw_error_t rv; - a_uint32_t val = 0; - - HSL_DEV_ID_CHECK(dev_id); - - if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU)) - { - return SW_BAD_PARAM; - } - - HSL_REG_FIELD_GET(rv, dev_id, PORT_DOT1AD, port_id, - FORCE_DEF_VID, (a_uint8_t *) (&val), - sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - - if (val) - { - *enable = A_TRUE; - } - else - { - *enable = A_FALSE; - } - - return SW_OK; -} - -static sw_error_t -_shiva_port_force_portvlan_set(a_uint32_t dev_id, fal_port_t port_id, a_bool_t enable) -{ - sw_error_t rv; - a_uint32_t val; - - HSL_DEV_ID_CHECK(dev_id); - - if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU)) - { - return SW_BAD_PARAM; - } - - if (A_TRUE == enable) - { - val = 1; - } - else if (A_FALSE == enable) - { - val = 0; - } - else - { - return SW_BAD_PARAM; - } - - HSL_REG_FIELD_SET(rv, dev_id, PORT_DOT1AD, port_id, - FORCE_PVLAN, (a_uint8_t *) (&val), - sizeof (a_uint32_t)); - return rv; -} - -static sw_error_t -_shiva_port_force_portvlan_get(a_uint32_t dev_id, fal_port_t port_id, a_bool_t * enable) -{ - sw_error_t rv; - a_uint32_t val = 0; - - HSL_DEV_ID_CHECK(dev_id); - - if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU)) - { - return SW_BAD_PARAM; - } - - HSL_REG_FIELD_GET(rv, dev_id, PORT_DOT1AD, port_id, - FORCE_PVLAN, (a_uint8_t *) (&val), - sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - - if (val) - { - *enable = A_TRUE; - } - else - { - *enable = A_FALSE; - } - - return SW_OK; -} - -static sw_error_t -_shiva_nestvlan_tpid_set(a_uint32_t dev_id, a_uint32_t tpid) -{ - sw_error_t rv; - a_uint32_t val; - - HSL_DEV_ID_CHECK(dev_id); - - val = tpid; - HSL_REG_FIELD_SET(rv, dev_id, SERVICE_TAG, 0, - TAG_VALUE, (a_uint8_t *) (&val), - sizeof (a_uint32_t)); - return rv; -} - -static sw_error_t -_shiva_nestvlan_tpid_get(a_uint32_t dev_id, a_uint32_t *tpid) -{ - sw_error_t rv; - a_uint32_t val = 0; - - HSL_DEV_ID_CHECK(dev_id); - - HSL_REG_FIELD_GET(rv, dev_id, SERVICE_TAG, 0, - TAG_VALUE, (a_uint8_t *) (&val), - sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - - *tpid = val; - return SW_OK; -} - -static sw_error_t -_shiva_port_invlan_mode_set(a_uint32_t dev_id, fal_port_t port_id, - fal_pt_invlan_mode_t mode) -{ - sw_error_t rv; - a_uint32_t regval[FAL_INVLAN_MODE_BUTT] = { 0, 1, 2}; - - HSL_DEV_ID_CHECK(dev_id); - - if (A_FALSE == hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU)) - { - return SW_BAD_PARAM; - } - - if (FAL_INVLAN_MODE_BUTT <= mode) - { - return SW_BAD_PARAM; - } - - HSL_REG_FIELD_SET(rv, dev_id, PORT_BASE_VLAN, port_id, IN_VLAN_MODE, - (a_uint8_t *) (®val[mode]), - sizeof (a_uint32_t)); - - return rv; -} - -static sw_error_t -_shiva_port_invlan_mode_get(a_uint32_t dev_id, fal_port_t port_id, - fal_pt_invlan_mode_t * mode) -{ - sw_error_t rv; - a_uint32_t regval = 0; - fal_pt_invlan_mode_t retval[FAL_INVLAN_MODE_BUTT] = { FAL_INVLAN_ADMIT_ALL, - FAL_INVLAN_ADMIT_TAGGED, FAL_INVLAN_ADMIT_UNTAGGED - }; - - HSL_DEV_ID_CHECK(dev_id); - - if (A_FALSE == hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU)) - { - return SW_BAD_PARAM; - } - - SW_RTN_ON_NULL(mode); - - HSL_REG_FIELD_GET(rv, dev_id, PORT_BASE_VLAN, port_id, IN_VLAN_MODE, - (a_uint8_t *) (®val), - sizeof (a_uint32_t)); - - SW_RTN_ON_ERROR(rv); - - if (regval >= 3) - { - return SW_FAIL; - } - *mode = retval[regval & 0x3]; - - return rv; -} - -static sw_error_t -_shiva_port_tls_set(a_uint32_t dev_id, fal_port_t port_id, - a_bool_t enable) -{ - sw_error_t rv; - a_uint32_t val; - - HSL_DEV_ID_CHECK(dev_id); - - if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU)) - { - return SW_BAD_PARAM; - } - - if (A_TRUE == enable) - { - val = 1; - } - else if (A_FALSE == enable) - { - val = 0; - } - else - { - return SW_BAD_PARAM; - } - - HSL_REG_FIELD_SET(rv, dev_id, PORT_DOT1AD, port_id, - TLS_EN, (a_uint8_t *) (&val), - sizeof (a_uint32_t)); - return rv; -} - -static sw_error_t -_shiva_port_tls_get(a_uint32_t dev_id, fal_port_t port_id, - a_bool_t * enable) -{ - sw_error_t rv; - a_uint32_t val = 0; - - HSL_DEV_ID_CHECK(dev_id); - - if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU)) - { - return SW_BAD_PARAM; - } - - HSL_REG_FIELD_GET(rv, dev_id, PORT_DOT1AD, port_id, - TLS_EN, (a_uint8_t *) (&val), - sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - - if (1 == val) - { - *enable = A_TRUE; - } - else - { - *enable = A_FALSE; - } - - return SW_OK; -} - -static sw_error_t -_shiva_port_pri_propagation_set(a_uint32_t dev_id, fal_port_t port_id, - a_bool_t enable) -{ - sw_error_t rv; - a_uint32_t val; - - HSL_DEV_ID_CHECK(dev_id); - - if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU)) - { - return SW_BAD_PARAM; - } - - if (A_TRUE == enable) - { - val = 1; - } - else if (A_FALSE == enable) - { - val = 0; - } - else - { - return SW_BAD_PARAM; - } - - HSL_REG_FIELD_SET(rv, dev_id, PORT_BASE_VLAN, port_id, - PRI_PROPAGATION, (a_uint8_t *) (&val), - sizeof (a_uint32_t)); - return rv; -} - -static sw_error_t -_shiva_port_pri_propagation_get(a_uint32_t dev_id, fal_port_t port_id, - a_bool_t * enable) -{ - sw_error_t rv; - a_uint32_t val = 0; - - HSL_DEV_ID_CHECK(dev_id); - - if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU)) - { - return SW_BAD_PARAM; - } - - HSL_REG_FIELD_GET(rv, dev_id, PORT_BASE_VLAN, port_id, - PRI_PROPAGATION, (a_uint8_t *) (&val), - sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - - if (1 == val) - { - *enable = A_TRUE; - } - else - { - *enable = A_FALSE; - } - - return SW_OK; -} - -static sw_error_t -_shiva_port_default_svid_set(a_uint32_t dev_id, fal_port_t port_id, - a_uint32_t vid) -{ - sw_error_t rv; - a_uint32_t val; - - HSL_DEV_ID_CHECK(dev_id); - - if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU)) - { - return SW_BAD_PARAM; - } - - if ((0 == vid) || (vid > MAX_VLAN_ID)) - { - return SW_BAD_PARAM; - } - - val = vid; - HSL_REG_FIELD_SET(rv, dev_id, PORT_DOT1AD, port_id, - DEF_SVID, (a_uint8_t *) (&val), - sizeof (a_uint32_t)); - - return rv; -} - -static sw_error_t -_shiva_port_default_svid_get(a_uint32_t dev_id, fal_port_t port_id, - a_uint32_t * vid) -{ - sw_error_t rv; - a_uint32_t val = 0; - - HSL_DEV_ID_CHECK(dev_id); - - if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU)) - { - return SW_BAD_PARAM; - } - - HSL_REG_FIELD_GET(rv, dev_id, PORT_DOT1AD, port_id, - DEF_SVID, (a_uint8_t *) (&val), - sizeof (a_uint32_t)); - - *vid = val & 0xfff; - return rv; -} - -static sw_error_t -_shiva_port_default_cvid_set(a_uint32_t dev_id, fal_port_t port_id, - a_uint32_t vid) -{ - sw_error_t rv; - a_uint32_t val; - - HSL_DEV_ID_CHECK(dev_id); - - if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU)) - { - return SW_BAD_PARAM; - } - - if ((0 == vid) || (vid > MAX_VLAN_ID)) - { - return SW_BAD_PARAM; - } - - val = vid; - HSL_REG_FIELD_SET(rv, dev_id, PORT_DOT1AD, port_id, - DEF_CVID, (a_uint8_t *) (&val), - sizeof (a_uint32_t)); - - return rv; -} - -static sw_error_t -_shiva_port_default_cvid_get(a_uint32_t dev_id, fal_port_t port_id, - a_uint32_t * vid) -{ - sw_error_t rv; - a_uint32_t val = 0; - - HSL_DEV_ID_CHECK(dev_id); - - if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU)) - { - return SW_BAD_PARAM; - } - - HSL_REG_FIELD_GET(rv, dev_id, PORT_DOT1AD, port_id, - DEF_CVID, (a_uint8_t *) (&val), - sizeof (a_uint32_t)); - - *vid = val & 0xfff; - return rv; -} - -static sw_error_t -_shiva_port_vlan_propagation_set(a_uint32_t dev_id, fal_port_t port_id, - fal_vlan_propagation_mode_t mode) -{ - sw_error_t rv; - a_uint32_t reg = 0, p, c; - - HSL_DEV_ID_CHECK(dev_id); - - if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU)) - { - return SW_BAD_PARAM; - } - - if (FAL_VLAN_PROPAGATION_DISABLE == mode) - { - p = 0; - c = 0; - } - else if (FAL_VLAN_PROPAGATION_CLONE == mode) - { - p = 1; - c = 1; - } - else if (FAL_VLAN_PROPAGATION_REPLACE == mode) - { - p = 1; - c = 0; - } - else - { - return SW_BAD_PARAM; - } - - HSL_REG_ENTRY_GET(rv, dev_id, PORT_DOT1AD, port_id, - (a_uint8_t *) (®), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - - SW_SET_REG_BY_FIELD(PORT_DOT1AD, PROPAGATION_EN, p, reg); - SW_SET_REG_BY_FIELD(PORT_DOT1AD, CLONE, c, reg); - - HSL_REG_ENTRY_SET(rv, dev_id, PORT_DOT1AD, port_id, - (a_uint8_t *) (®), sizeof (a_uint32_t)); - return rv; -} - -static sw_error_t -_shiva_port_vlan_propagation_get(a_uint32_t dev_id, fal_port_t port_id, - fal_vlan_propagation_mode_t * mode) -{ - sw_error_t rv; - a_uint32_t reg = 0, p, c; - - HSL_DEV_ID_CHECK(dev_id); - - if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU)) - { - return SW_BAD_PARAM; - } - - HSL_REG_ENTRY_GET(rv, dev_id, PORT_DOT1AD, port_id, - (a_uint8_t *) (®), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - - SW_GET_FIELD_BY_REG(PORT_DOT1AD, PROPAGATION_EN, p, reg); - SW_GET_FIELD_BY_REG(PORT_DOT1AD, CLONE, c, reg); - - if (p) - { - if (c) - { - *mode = FAL_VLAN_PROPAGATION_CLONE; - } - else - { - *mode = FAL_VLAN_PROPAGATION_REPLACE; - } - } - else - { - *mode = FAL_VLAN_PROPAGATION_DISABLE; - } - - return SW_OK; -} - -static sw_error_t -_shiva_vlan_trans_read(a_uint32_t dev_id, a_uint32_t entry_idx, fal_pbmp_t * pbmp, fal_vlan_trans_entry_t *entry) -{ - sw_error_t rv; - a_uint32_t i, addr, table[2] = {0}; - - addr = SHIVA_VLAN_TRANS_ADDR + (entry_idx << 3); - - /* get vlan trans table */ - for (i = 0; i < 2; i++) - { - HSL_REG_ENTRY_GEN_GET(rv, dev_id, addr + (i << 2), sizeof (a_uint32_t), - (a_uint8_t *) (&(table[i])), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - } - - if (0x1 & (table[1] >> 4)) - { - entry->o_vid = table[0] & 0xfff; - entry->s_vid = (table[0] >> 12) & 0xfff; - entry->c_vid = ((table[0] >> 24) & 0xff) | ((table[1] & 0xf) << 8); - entry->bi_dir = (~(table[1] >> 5)) & 0x1; - *pbmp = (table[1] >> 6) & 0x7f; - return SW_OK; - } - else - { - return SW_EMPTY; - } -} - -static sw_error_t -_shiva_vlan_trans_write(a_uint32_t dev_id, a_uint32_t entry_idx, fal_pbmp_t pbmp, fal_vlan_trans_entry_t entry) -{ - sw_error_t rv; - a_uint32_t i, addr, table[2] = {0}; - - addr = SHIVA_VLAN_TRANS_ADDR + (entry_idx << 3); - - if (0 != pbmp) - { - table[0] = entry.o_vid & 0xfff; - table[0] |= ((entry.s_vid & 0xfff) << 12); - table[0] |= ((entry.c_vid & 0xff) << 24); - table[1] = (entry.c_vid >> 8) & 0xf; - table[1] |= (0x1 << 4); - table[1] |= (((~(entry.bi_dir))& 0x1) << 5); - table[1] |= (pbmp << 6); - } - - /* set vlan trans table */ - for (i = 0; i < 2; i++) - { - HSL_REG_ENTRY_GEN_SET(rv, dev_id, addr + (i << 2), sizeof (a_uint32_t), - (a_uint8_t *) (&(table[i])), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - } - - return SW_OK; -} - -static sw_error_t -_shiva_port_vlan_trans_add(a_uint32_t dev_id, fal_port_t port_id, fal_vlan_trans_entry_t *entry) -{ - sw_error_t rv; - fal_pbmp_t t_pbmp; - a_uint32_t idx, entry_idx = 0xffff, old_idx = 0xffff; - fal_vlan_trans_entry_t entry_temp; - - HSL_DEV_ID_CHECK(dev_id); - - if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU)) - { - return SW_BAD_PARAM; - } - - for (idx = 0; idx < SHIVA_MAX_VLAN_TRANS; idx++) - { - aos_mem_set(&entry_temp, 0, sizeof(fal_vlan_trans_entry_t)); - rv = _shiva_vlan_trans_read(dev_id, idx, &t_pbmp, &entry_temp); - if (SW_EMPTY == rv) - { - entry_idx = idx; - continue; - } - SW_RTN_ON_ERROR(rv); - - if (!aos_mem_cmp(&entry_temp, entry, sizeof(fal_vlan_trans_entry_t))) - { - if (SW_IS_PBMP_MEMBER(t_pbmp, port_id)) - { - return SW_ALREADY_EXIST; - } - old_idx = idx; - break; - } - } - - if (0xffff != old_idx) - { - t_pbmp |= (0x1 << port_id); - entry_idx = old_idx; - } - else if (0xffff != entry_idx) - { - t_pbmp = (0x1 << port_id); - aos_mem_copy(&entry_temp, entry, sizeof(fal_vlan_trans_entry_t)); - } - else - { - return SW_NO_RESOURCE; - } - - return _shiva_vlan_trans_write(dev_id, entry_idx, t_pbmp, entry_temp); -} - -static sw_error_t -_shiva_port_vlan_trans_del(a_uint32_t dev_id, fal_port_t port_id, fal_vlan_trans_entry_t *entry) -{ - sw_error_t rv; - fal_pbmp_t t_pbmp; - a_uint32_t idx, entry_idx = 0xffff; - fal_vlan_trans_entry_t entry_temp; - - HSL_DEV_ID_CHECK(dev_id); - - if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU)) - { - return SW_BAD_PARAM; - } - - for (idx = 0; idx < SHIVA_MAX_VLAN_TRANS; idx++) - { - aos_mem_set(&entry_temp, 0, sizeof(fal_vlan_trans_entry_t)); - rv = _shiva_vlan_trans_read(dev_id, idx, &t_pbmp, &entry_temp); - if (SW_EMPTY == rv) - { - continue; - } - SW_RTN_ON_ERROR(rv); - - if ((entry->o_vid == entry_temp.o_vid) - && (entry->bi_dir == entry_temp.bi_dir)) - { - if (SW_IS_PBMP_MEMBER(t_pbmp, port_id)) - { - entry_idx = idx; - break; - } - } - } - - if (0xffff != entry_idx) - { - t_pbmp &= (~(0x1 << port_id)); - } - else - { - return SW_NOT_FOUND; - } - - return _shiva_vlan_trans_write(dev_id, entry_idx, t_pbmp, entry_temp); -} - -static sw_error_t -_shiva_port_vlan_trans_get(a_uint32_t dev_id, fal_port_t port_id, fal_vlan_trans_entry_t *entry) -{ - sw_error_t rv; - fal_pbmp_t t_pbmp; - a_uint32_t idx; - fal_vlan_trans_entry_t entry_temp; - - HSL_DEV_ID_CHECK(dev_id); - - if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU)) - { - return SW_BAD_PARAM; - } - - for (idx = 0; idx < SHIVA_MAX_VLAN_TRANS; idx++) - { - aos_mem_set(&entry_temp, 0, sizeof(fal_vlan_trans_entry_t)); - rv = _shiva_vlan_trans_read(dev_id, idx, &t_pbmp, &entry_temp); - if (SW_EMPTY == rv) - { - continue; - } - - SW_RTN_ON_ERROR(rv); - if ((entry->o_vid == entry_temp.o_vid) - && (entry->bi_dir == entry_temp.bi_dir)) - { - if (SW_IS_PBMP_MEMBER(t_pbmp, port_id)) - { - aos_mem_copy(entry, &entry_temp, sizeof(fal_vlan_trans_entry_t)); - return SW_OK; - } - } - } - - return SW_NOT_FOUND; -} - -static sw_error_t -_shiva_port_vlan_trans_iterate(a_uint32_t dev_id, fal_port_t port_id, - a_uint32_t * iterator, fal_vlan_trans_entry_t * entry) -{ - a_uint32_t index; - sw_error_t rv; - fal_vlan_trans_entry_t entry_t; - fal_pbmp_t pbmp_t = 0; - - HSL_DEV_ID_CHECK(dev_id); - - if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU)) - { - return SW_BAD_PARAM; - } - - if ((NULL == iterator) || (NULL == entry)) - { - return SW_BAD_PTR; - } - - if (SHIVA_MAX_VLAN_TRANS == *iterator) - { - return SW_NO_MORE; - } - - if (SHIVA_MAX_VLAN_TRANS < *iterator) - { - return SW_BAD_PARAM; - } - - aos_mem_set(&entry_t, 0, sizeof(fal_vlan_trans_entry_t)); - for (index = *iterator; index < SHIVA_MAX_VLAN_TRANS; index++) - { - rv = _shiva_vlan_trans_read(dev_id, index, &pbmp_t, &entry_t); - if (SW_EMPTY == rv) - { - continue; - } - - if (SW_IS_PBMP_MEMBER(pbmp_t, port_id)) - { - aos_mem_copy(entry, &entry_t, sizeof(fal_vlan_trans_entry_t)); - break; - } - } - - if (SHIVA_MAX_VLAN_TRANS == index) - { - return SW_NO_MORE; - } - - *iterator = index + 1; - return SW_OK; -} - -static sw_error_t -_shiva_qinq_mode_set(a_uint32_t dev_id, fal_qinq_mode_t mode) -{ - sw_error_t rv; - a_uint32_t stag = 0; - - HSL_DEV_ID_CHECK(dev_id); - - if (FAL_QINQ_MODE_BUTT <= mode) - { - return SW_BAD_PARAM; - } - - if (FAL_QINQ_STAG_MODE == mode) - { - stag = 1; - } - - HSL_REG_FIELD_SET(rv, dev_id, ADDR_TABLE_CTL, 0, - STAG_MODE, (a_uint8_t *) (&stag), - sizeof (a_uint32_t)); - - return rv; -} - -static sw_error_t -_shiva_qinq_mode_get(a_uint32_t dev_id, fal_qinq_mode_t * mode) -{ - sw_error_t rv; - a_uint32_t stag = 0; - - HSL_DEV_ID_CHECK(dev_id); - - HSL_REG_FIELD_GET(rv, dev_id, ADDR_TABLE_CTL, 0, - STAG_MODE, (a_uint8_t *) (&stag), - sizeof (a_uint32_t)); - - SW_RTN_ON_ERROR(rv); - - if (stag) - { - *mode = FAL_QINQ_STAG_MODE; - } - else - { - *mode = FAL_QINQ_CTAG_MODE; - } - - return SW_OK; -} - -static sw_error_t -_shiva_port_qinq_role_set(a_uint32_t dev_id, fal_port_t port_id, fal_qinq_port_role_t role) -{ - sw_error_t rv; - a_uint32_t core = 0; - - HSL_DEV_ID_CHECK(dev_id); - - if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU)) - { - return SW_BAD_PARAM; - } - - if (FAL_QINQ_PORT_ROLE_BUTT <= role) - { - return SW_BAD_PARAM; - } - - if (FAL_QINQ_CORE_PORT == role) - { - core = 1; - } - - HSL_REG_FIELD_SET(rv, dev_id, PORT_BASE_VLAN, port_id, - COREP_EN, (a_uint8_t *) (&core), - sizeof (a_uint32_t)); - - return rv; -} - -static sw_error_t -_shiva_port_qinq_role_get(a_uint32_t dev_id, fal_port_t port_id, fal_qinq_port_role_t * role) -{ - sw_error_t rv; - a_uint32_t core = 0; - - HSL_DEV_ID_CHECK(dev_id); - - if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU)) - { - return SW_BAD_PARAM; - } - - HSL_REG_FIELD_GET(rv, dev_id, PORT_BASE_VLAN, port_id, - COREP_EN, (a_uint8_t *) (&core), - sizeof (a_uint32_t)); - - SW_RTN_ON_ERROR(rv); - - if (core) - { - *role = FAL_QINQ_CORE_PORT; - } - else - { - *role = FAL_QINQ_EDGE_PORT; - } - - return SW_OK; -} - -/** - * @brief Set 802.1q work mode on a particular port. - * @param[in] dev_id device id - * @param[in] port_id port id - * @param[in] port_1qmode 802.1q work mode - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -shiva_port_1qmode_set(a_uint32_t dev_id, fal_port_t port_id, - fal_pt_1qmode_t port_1qmode) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _shiva_port_1qmode_set(dev_id, port_id, port_1qmode); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Get 802.1q work mode on a particular port. - * @param[in] dev_id device id - * @param[in] port_id port id - * @param[out] port_1qmode 802.1q work mode - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -shiva_port_1qmode_get(a_uint32_t dev_id, fal_port_t port_id, - fal_pt_1qmode_t * pport_1qmode) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _shiva_port_1qmode_get(dev_id, port_id, pport_1qmode); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Set packets transmitted out vlan tagged mode on a particular port. - * @param[in] dev_id device id - * @param[in] port_id port id - * @param[in] port_egvlanmode packets transmitted out vlan tagged mode - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -shiva_port_egvlanmode_set(a_uint32_t dev_id, fal_port_t port_id, - fal_pt_1q_egmode_t port_egvlanmode) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _shiva_port_egvlanmode_set(dev_id, port_id, port_egvlanmode); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Get packets transmitted out vlan tagged mode on a particular port. - * @param[in] dev_id device id - * @param[in] port_id port id - * @param[out] port_egvlanmode packets transmitted out vlan tagged mode - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -shiva_port_egvlanmode_get(a_uint32_t dev_id, fal_port_t port_id, - fal_pt_1q_egmode_t * pport_egvlanmode) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _shiva_port_egvlanmode_get(dev_id, port_id, pport_egvlanmode); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Add member of port based vlan on a particular port. - * @param[in] dev_id device id - * @param[in] port_id port id - * @param[in] mem_port_id port member - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -shiva_portvlan_member_add(a_uint32_t dev_id, fal_port_t port_id, - a_uint32_t mem_port_id) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _shiva_portvlan_member_add(dev_id, port_id, mem_port_id); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Delete member of port based vlan on a particular port. - * @param[in] dev_id device id - * @param[in] port_id port id - * @param[in] mem_port_id port member - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -shiva_portvlan_member_del(a_uint32_t dev_id, fal_port_t port_id, - a_uint32_t mem_port_id) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _shiva_portvlan_member_del(dev_id, port_id, mem_port_id); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Update member of port based vlan on a particular port. - * @param[in] dev_id device id - * @param[in] port_id port id - * @param[in] mem_port_map port members - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -shiva_portvlan_member_update(a_uint32_t dev_id, fal_port_t port_id, - fal_pbmp_t mem_port_map) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _shiva_portvlan_member_update(dev_id, port_id, mem_port_map); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Get member of port based vlan on a particular port. - * @param[in] dev_id device id - * @param[in] port_id port id - * @param[out] mem_port_map port members - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -shiva_portvlan_member_get(a_uint32_t dev_id, fal_port_t port_id, - fal_pbmp_t * mem_port_map) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _shiva_portvlan_member_get(dev_id, port_id, mem_port_map); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Set force default vlan id status on a particular port. - * @param[in] dev_id device id - * @param[in] port_id port id - * @param[in] enable A_TRUE or A_FALSE - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -shiva_port_force_default_vid_set(a_uint32_t dev_id, fal_port_t port_id, a_bool_t enable) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _shiva_port_force_default_vid_set(dev_id, port_id, enable); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Get force default vlan id status on a particular port. - * @param[in] dev_id device id - * @param[in] port_id port id - * @param[out] enable A_TRUE or A_FALSE - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -shiva_port_force_default_vid_get(a_uint32_t dev_id, fal_port_t port_id, a_bool_t * enable) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _shiva_port_force_default_vid_get(dev_id, port_id, enable); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Set force port based vlan status on a particular port. - * @param[in] dev_id device id - * @param[in] port_id port id - * @param[in] enable A_TRUE or A_FALSE - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -shiva_port_force_portvlan_set(a_uint32_t dev_id, fal_port_t port_id, a_bool_t enable) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _shiva_port_force_portvlan_set(dev_id, port_id, enable); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Get force port based vlan status on a particular port. - * @param[in] dev_id device id - * @param[in] port_id port id - * @param[out] enable A_TRUE or A_FALSE - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -shiva_port_force_portvlan_get(a_uint32_t dev_id, fal_port_t port_id, a_bool_t * enable) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _shiva_port_force_portvlan_get(dev_id, port_id, enable); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Set nest vlan tpid on a particular device. - * @param[in] dev_id device id - * @param[in] tpid tag protocol identification - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -shiva_nestvlan_tpid_set(a_uint32_t dev_id, a_uint32_t tpid) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _shiva_nestvlan_tpid_set(dev_id, tpid); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Get nest vlan tpid on a particular device. - * @param[in] dev_id device id - * @param[out] tpid tag protocol identification - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -shiva_nestvlan_tpid_get(a_uint32_t dev_id, a_uint32_t *tpid) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _shiva_nestvlan_tpid_get(dev_id, tpid); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Set ingress vlan mode mode on a particular port. - * @param[in] dev_id device id - * @param[in] port_id port id - * @param[in] mode ingress vlan mode - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -shiva_port_invlan_mode_set(a_uint32_t dev_id, fal_port_t port_id, - fal_pt_invlan_mode_t mode) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _shiva_port_invlan_mode_set(dev_id, port_id, mode); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Get ingress vlan mode mode on a particular port. - * @param[in] dev_id device id - * @param[in] port_id port id - * @param[out] mode ingress vlan mode - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -shiva_port_invlan_mode_get(a_uint32_t dev_id, fal_port_t port_id, - fal_pt_invlan_mode_t * mode) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _shiva_port_invlan_mode_get(dev_id, port_id, mode); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Set tls status on a particular port. - * @param[in] dev_id device id - * @param[in] port_id port id - * @param[in] enable A_TRUE or A_FALSE - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -shiva_port_tls_set(a_uint32_t dev_id, fal_port_t port_id, - a_bool_t enable) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _shiva_port_tls_set(dev_id, port_id, enable); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Get tls status on a particular port. - * @param[in] dev_id device id - * @param[in] port_id port id - * @param[out] enable A_TRUE or A_FALSE - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -shiva_port_tls_get(a_uint32_t dev_id, fal_port_t port_id, - a_bool_t * enable) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _shiva_port_tls_get(dev_id, port_id, enable); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Set priority propagation status on a particular port. - * @param[in] dev_id device id - * @param[in] port_id port id - * @param[in] enable A_TRUE or A_FALSE - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -shiva_port_pri_propagation_set(a_uint32_t dev_id, fal_port_t port_id, - a_bool_t enable) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _shiva_port_pri_propagation_set(dev_id, port_id, enable); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Get priority propagation status on a particular port. - * @param[in] dev_id device id - * @param[in] port_id port id - * @param[out] enable A_TRUE or A_FALSE - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -shiva_port_pri_propagation_get(a_uint32_t dev_id, fal_port_t port_id, - a_bool_t * enable) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _shiva_port_pri_propagation_get(dev_id, port_id, enable); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Set default s-vid on a particular port. - * @param[in] dev_id device id - * @param[in] port_id port id - * @param[in] vid s-vid - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -shiva_port_default_svid_set(a_uint32_t dev_id, fal_port_t port_id, - a_uint32_t vid) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _shiva_port_default_svid_set(dev_id, port_id, vid); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Get default s-vid on a particular port. - * @param[in] dev_id device id - * @param[in] port_id port id - * @param[out] vid s-vid - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -shiva_port_default_svid_get(a_uint32_t dev_id, fal_port_t port_id, - a_uint32_t * vid) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _shiva_port_default_svid_get(dev_id, port_id, vid); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Set default c-vid on a particular port. - * @param[in] dev_id device id - * @param[in] port_id port id - * @param[in] vid c-vid - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -shiva_port_default_cvid_set(a_uint32_t dev_id, fal_port_t port_id, - a_uint32_t vid) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _shiva_port_default_cvid_set(dev_id, port_id, vid); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Get default c-vid on a particular port. - * @param[in] dev_id device id - * @param[in] port_id port id - * @param[out] vid c-vid - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -shiva_port_default_cvid_get(a_uint32_t dev_id, fal_port_t port_id, - a_uint32_t * vid) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _shiva_port_default_cvid_get(dev_id, port_id, vid); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Set vlan propagation status on a particular port. - * @param[in] dev_id device id - * @param[in] port_id port id - * @param[in] mode vlan propagation mode - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -shiva_port_vlan_propagation_set(a_uint32_t dev_id, fal_port_t port_id, - fal_vlan_propagation_mode_t mode) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _shiva_port_vlan_propagation_set(dev_id, port_id, mode); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Get vlan propagation status on a particular port. - * @param[in] dev_id device id - * @param[in] port_id port id - * @param[out] mode vlan propagation mode - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -shiva_port_vlan_propagation_get(a_uint32_t dev_id, fal_port_t port_id, - fal_vlan_propagation_mode_t * mode) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _shiva_port_vlan_propagation_get(dev_id, port_id, mode); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Add a vlan translation entry to a particular port. - * @param[in] dev_id device id - * @param[in] port_id port id - * @param entry vlan translation entry - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -shiva_port_vlan_trans_add(a_uint32_t dev_id, fal_port_t port_id, fal_vlan_trans_entry_t *entry) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _shiva_port_vlan_trans_add(dev_id, port_id, entry); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Delete a vlan translation entry from a particular port. - * @param[in] dev_id device id - * @param[in] port_id port id - * @param entry vlan translation entry - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -shiva_port_vlan_trans_del(a_uint32_t dev_id, fal_port_t port_id, fal_vlan_trans_entry_t *entry) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _shiva_port_vlan_trans_del(dev_id, port_id, entry); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Get a vlan translation entry from a particular port. - * @param[in] dev_id device id - * @param[in] port_id port id - * @param entry vlan translation entry - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -shiva_port_vlan_trans_get(a_uint32_t dev_id, fal_port_t port_id, fal_vlan_trans_entry_t *entry) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _shiva_port_vlan_trans_get(dev_id, port_id, entry); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Iterate all vlan translation entries from a particular port. - * @param[in] dev_id device id - * @param[in] port_id port id - * @param[in] iterator translation entry index if it's zero means get the first entry - * @param[out] iterator next valid translation entry index - * @param[out] entry vlan translation entry - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -shiva_port_vlan_trans_iterate(a_uint32_t dev_id, fal_port_t port_id, - a_uint32_t * iterator, fal_vlan_trans_entry_t * entry) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _shiva_port_vlan_trans_iterate(dev_id, port_id, iterator, entry); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Set switch qinq work mode on a particular device. - * @param[in] dev_id device id - * @param[in] mode qinq work mode - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -shiva_qinq_mode_set(a_uint32_t dev_id, fal_qinq_mode_t mode) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _shiva_qinq_mode_set(dev_id, mode); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Get switch qinq work mode on a particular device. - * @param[in] dev_id device id - * @param[out] mode qinq work mode - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -shiva_qinq_mode_get(a_uint32_t dev_id, fal_qinq_mode_t * mode) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _shiva_qinq_mode_get(dev_id, mode); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Set qinq role on a particular port. - * @param[in] dev_id device id - * @param[in] port_id port id - * @param[in] role port role - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -shiva_port_qinq_role_set(a_uint32_t dev_id, fal_port_t port_id, fal_qinq_port_role_t role) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _shiva_port_qinq_role_set(dev_id, port_id, role); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Get qinq role on a particular port. - * @param[in] dev_id device id - * @param[in] port_id port id - * @param[out] role port role - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -shiva_port_qinq_role_get(a_uint32_t dev_id, fal_port_t port_id, fal_qinq_port_role_t * role) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _shiva_port_qinq_role_get(dev_id, port_id, role); - HSL_API_UNLOCK; - return rv; -} - -sw_error_t -shiva_portvlan_init(a_uint32_t dev_id) -{ - a_uint32_t i; - sw_error_t rv; - fal_vlan_trans_entry_t entry_init; - hsl_api_t *p_api; - - HSL_DEV_ID_CHECK(dev_id); - - aos_mem_set(&entry_init, 0, sizeof(fal_vlan_trans_entry_t)); - entry_init.bi_dir = A_TRUE; - - for (i = 0; i < SHIVA_MAX_VLAN_TRANS; i++) - { - rv = _shiva_vlan_trans_write(dev_id, i, 0, entry_init); - SW_RTN_ON_ERROR(rv); - } - -#ifndef HSL_STANDALONG - - SW_RTN_ON_NULL (p_api = hsl_api_ptr_get(dev_id)); - - p_api->port_1qmode_get = shiva_port_1qmode_get; - p_api->port_1qmode_set = shiva_port_1qmode_set; - p_api->port_egvlanmode_get = shiva_port_egvlanmode_get; - p_api->port_egvlanmode_set = shiva_port_egvlanmode_set; - p_api->portvlan_member_add = shiva_portvlan_member_add; - p_api->portvlan_member_del = shiva_portvlan_member_del; - p_api->portvlan_member_update = shiva_portvlan_member_update; - p_api->portvlan_member_get = shiva_portvlan_member_get; - p_api->port_force_default_vid_set = shiva_port_force_default_vid_set; - p_api->port_force_default_vid_get = shiva_port_force_default_vid_get; - p_api->port_force_portvlan_set = shiva_port_force_portvlan_set; - p_api->port_force_portvlan_get = shiva_port_force_portvlan_get; - p_api->nestvlan_tpid_set = shiva_nestvlan_tpid_set; - p_api->nestvlan_tpid_get = shiva_nestvlan_tpid_get; - p_api->port_invlan_mode_set = shiva_port_invlan_mode_set; - p_api->port_invlan_mode_get = shiva_port_invlan_mode_get; - p_api->port_tls_set = shiva_port_tls_set; - p_api->port_tls_get = shiva_port_tls_get; - p_api->port_pri_propagation_set = shiva_port_pri_propagation_set; - p_api->port_pri_propagation_get = shiva_port_pri_propagation_get; - p_api->port_default_svid_set = shiva_port_default_svid_set; - p_api->port_default_svid_get = shiva_port_default_svid_get; - p_api->port_default_cvid_set = shiva_port_default_cvid_set; - p_api->port_default_cvid_get = shiva_port_default_cvid_get; - p_api->port_vlan_propagation_set = shiva_port_vlan_propagation_set; - p_api->port_vlan_propagation_get = shiva_port_vlan_propagation_get; - p_api->port_vlan_trans_add = shiva_port_vlan_trans_add; - p_api->port_vlan_trans_del = shiva_port_vlan_trans_del; - p_api->port_vlan_trans_get = shiva_port_vlan_trans_get; - p_api->qinq_mode_set = shiva_qinq_mode_set; - p_api->qinq_mode_get = shiva_qinq_mode_get; - p_api->port_qinq_role_set = shiva_port_qinq_role_set; - p_api->port_qinq_role_get = shiva_port_qinq_role_get; - p_api->port_vlan_trans_iterate = shiva_port_vlan_trans_iterate; -#endif - - return SW_OK; -} - -/** - * @} - */ - diff --git a/feeds/ipq807x/qca-ssdk/src/src/hsl/shiva/shiva_qos.c b/feeds/ipq807x/qca-ssdk/src/src/hsl/shiva/shiva_qos.c deleted file mode 100755 index 64221f7ab..000000000 --- a/feeds/ipq807x/qca-ssdk/src/src/hsl/shiva/shiva_qos.c +++ /dev/null @@ -1,1288 +0,0 @@ -/* - * Copyright (c) 2012, 2016, The Linux Foundation. All rights reserved. - * Permission to use, copy, modify, and/or distribute this software for - * any purpose with or without fee is hereby granted, provided that the - * above copyright notice and this permission notice appear in all copies. - * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES - * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR - * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES - * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN - * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT - * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. - */ - - -/** - * @defgroup shiva_qos SHIVA_QOS - * @{ - */ -#include "sw.h" -#include "hsl.h" -#include "hsl_dev.h" -#include "hsl_port_prop.h" -#include "shiva_qos.h" -#include "shiva_reg.h" - -#define SHIVA_QOS_QUEUE_TX_BUFFER_MAX 60 -#define SHIVA_QOS_PORT_TX_BUFFER_MAX 252 -#define SHIVA_QOS_PORT_RX_BUFFER_MAX 60 - -//#define SHIVA_MIN_QOS_MODE_PRI 0 -#define SHIVA_MAX_QOS_MODE_PRI 3 - -static sw_error_t -_shiva_qos_queue_tx_buf_status_set(a_uint32_t dev_id, fal_port_t port_id, - a_bool_t enable) -{ - a_uint32_t val = 0; - sw_error_t rv; - - if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU)) - { - return SW_BAD_PARAM; - } - - if (A_TRUE == enable) - { - val = 1; - } - else if (A_FALSE == enable) - { - val = 0; - } - else - { - return SW_BAD_PARAM; - } - - HSL_REG_FIELD_SET(rv, dev_id, QUEUE_CTL, port_id, QUEUE_DESC_EN, - (a_uint8_t *) (&val), sizeof (a_uint32_t)); - return rv; -} - -static sw_error_t -_shiva_qos_queue_tx_buf_status_get(a_uint32_t dev_id, fal_port_t port_id, - a_bool_t * enable) -{ - a_uint32_t val = 0; - sw_error_t rv; - - if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU)) - { - return SW_BAD_PARAM; - } - - HSL_REG_FIELD_GET(rv, dev_id, QUEUE_CTL, port_id, QUEUE_DESC_EN, - (a_uint8_t *) (&val), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - - if (1 == val) - { - *enable = A_TRUE; - } - else - { - *enable = A_FALSE; - } - - return SW_OK; -} - -static sw_error_t -_shiva_qos_port_tx_buf_status_set(a_uint32_t dev_id, fal_port_t port_id, - a_bool_t enable) -{ - a_uint32_t val = 0; - sw_error_t rv; - - if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU)) - { - return SW_BAD_PARAM; - } - - if (A_TRUE == enable) - { - val = 1; - } - else if (A_FALSE == enable) - { - val = 0; - } - else - { - return SW_BAD_PARAM; - } - - HSL_REG_FIELD_SET(rv, dev_id, QUEUE_CTL, port_id, PORT_DESC_EN, - (a_uint8_t *) (&val), sizeof (a_uint32_t)); - return rv; -} - -static sw_error_t -_shiva_qos_port_tx_buf_status_get(a_uint32_t dev_id, fal_port_t port_id, - a_bool_t * enable) -{ - a_uint32_t val = 0; - sw_error_t rv; - - if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU)) - { - return SW_BAD_PARAM; - } - - HSL_REG_FIELD_GET(rv, dev_id, QUEUE_CTL, port_id, PORT_DESC_EN, - (a_uint8_t *) (&val), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - - if (1 == val) - { - *enable = A_TRUE; - } - else - { - *enable = A_FALSE; - } - - return SW_OK; -} - -static sw_error_t -_shiva_qos_queue_tx_buf_nr_set(a_uint32_t dev_id, fal_port_t port_id, - fal_queue_t queue_id, a_uint32_t * number) -{ - a_uint32_t val = 0; - sw_error_t rv; - - if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU)) - { - return SW_BAD_PARAM; - } - - if (SHIVA_QOS_QUEUE_TX_BUFFER_MAX < *number) - { - return SW_BAD_PARAM; - } - - val = *number / 4; - *number = val << 2; - - if (0 == queue_id) - { - HSL_REG_FIELD_SET(rv, dev_id, QUEUE_CTL, port_id, QUEUE0_DESC_NR, - (a_uint8_t *) (&val), sizeof (a_uint32_t)); - } - else if (1 == queue_id) - { - HSL_REG_FIELD_SET(rv, dev_id, QUEUE_CTL, port_id, QUEUE1_DESC_NR, - (a_uint8_t *) (&val), sizeof (a_uint32_t)); - } - else if (2 == queue_id) - { - HSL_REG_FIELD_SET(rv, dev_id, QUEUE_CTL, port_id, QUEUE2_DESC_NR, - (a_uint8_t *) (&val), sizeof (a_uint32_t)); - } - else if (3 == queue_id) - { - HSL_REG_FIELD_SET(rv, dev_id, QUEUE_CTL, port_id, QUEUE3_DESC_NR, - (a_uint8_t *) (&val), sizeof (a_uint32_t)); - } - else - { - return SW_BAD_PARAM; - } - - return rv; -} - -static sw_error_t -_shiva_qos_queue_tx_buf_nr_get(a_uint32_t dev_id, fal_port_t port_id, - fal_queue_t queue_id, a_uint32_t * number) -{ - a_uint32_t val = 0; - sw_error_t rv; - - if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU)) - { - return SW_BAD_PARAM; - } - - if (0 == queue_id) - { - HSL_REG_FIELD_GET(rv, dev_id, QUEUE_CTL, port_id, QUEUE0_DESC_NR, - (a_uint8_t *) (&val), sizeof (a_uint32_t)); - } - else if (1 == queue_id) - { - HSL_REG_FIELD_GET(rv, dev_id, QUEUE_CTL, port_id, QUEUE1_DESC_NR, - (a_uint8_t *) (&val), sizeof (a_uint32_t)); - } - else if (2 == queue_id) - { - HSL_REG_FIELD_GET(rv, dev_id, QUEUE_CTL, port_id, QUEUE2_DESC_NR, - (a_uint8_t *) (&val), sizeof (a_uint32_t)); - } - else if (3 == queue_id) - { - HSL_REG_FIELD_GET(rv, dev_id, QUEUE_CTL, port_id, QUEUE3_DESC_NR, - (a_uint8_t *) (&val), sizeof (a_uint32_t)); - } - else - { - return SW_BAD_PARAM; - } - SW_RTN_ON_ERROR(rv); - - *number = val << 2; - return SW_OK; -} - -static sw_error_t -_shiva_qos_port_tx_buf_nr_set(a_uint32_t dev_id, fal_port_t port_id, - a_uint32_t * number) -{ - a_uint32_t val = 0; - sw_error_t rv; - - if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU)) - { - return SW_BAD_PARAM; - } - - if (SHIVA_QOS_PORT_TX_BUFFER_MAX < *number) - { - return SW_BAD_PARAM; - } - - val = *number / 4; - *number = val << 2; - HSL_REG_FIELD_SET(rv, dev_id, QUEUE_CTL, port_id, PORT_DESC_NR, - (a_uint8_t *) (&val), sizeof (a_uint32_t)); - return rv; -} - -static sw_error_t -_shiva_qos_port_tx_buf_nr_get(a_uint32_t dev_id, fal_port_t port_id, - a_uint32_t * number) -{ - a_uint32_t val = 0; - sw_error_t rv; - - if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU)) - { - return SW_BAD_PARAM; - } - - HSL_REG_FIELD_GET(rv, dev_id, QUEUE_CTL, port_id, PORT_DESC_NR, - (a_uint8_t *) (&val), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - - *number = val << 2; - return SW_OK; -} - -static sw_error_t -_shiva_qos_port_rx_buf_nr_set(a_uint32_t dev_id, fal_port_t port_id, - a_uint32_t * number) -{ - a_uint32_t val = 0; - sw_error_t rv; - - if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU)) - { - return SW_BAD_PARAM; - } - - if (SHIVA_QOS_PORT_RX_BUFFER_MAX < *number) - { - return SW_BAD_PARAM; - } - - val = *number / 4; - *number = val << 2; - HSL_REG_FIELD_SET(rv, dev_id, QUEUE_CTL, port_id, PORT_IN_DESC_EN, - (a_uint8_t *) (&val), sizeof (a_uint32_t)); - return rv; -} - -static sw_error_t -_shiva_qos_port_rx_buf_nr_get(a_uint32_t dev_id, fal_port_t port_id, - a_uint32_t * number) -{ - a_uint32_t val = 0; - sw_error_t rv; - - if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU)) - { - return SW_BAD_PARAM; - } - - HSL_REG_FIELD_GET(rv, dev_id, QUEUE_CTL, port_id, PORT_IN_DESC_EN, - (a_uint8_t *) (&val), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - - *number = val << 2; - return SW_OK; -} - -static sw_error_t -_shiva_cosmap_up_queue_set(a_uint32_t dev_id, a_uint32_t up, - fal_queue_t queue) -{ - sw_error_t rv; - a_uint32_t val; - hsl_dev_t *p_dev = NULL; - - HSL_DEV_ID_CHECK(dev_id); - - if (FAL_DOT1P_MAX < up) - { - return SW_BAD_PARAM; - } - - SW_RTN_ON_NULL(p_dev = hsl_dev_ptr_get(dev_id)); - if (p_dev->nr_queue <= queue) - { - return SW_BAD_PARAM; - } - - val = queue; - HSL_REG_FIELD_GEN_SET(rv, dev_id, TAG_PRI_MAPPING_OFFSET, 2, - (a_uint16_t) (up << 1), (a_uint8_t *) (&val), - sizeof (a_uint32_t)); - return rv; -} - -static sw_error_t -_shiva_cosmap_up_queue_get(a_uint32_t dev_id, a_uint32_t up, - fal_queue_t * queue) -{ - sw_error_t rv; - a_uint32_t val = 0; - - HSL_DEV_ID_CHECK(dev_id); - - if (FAL_DOT1P_MAX < up) - { - return SW_BAD_PARAM; - } - - HSL_REG_FIELD_GEN_GET(rv, dev_id, TAG_PRI_MAPPING_OFFSET, 2, - (a_uint16_t) (up << 1), (a_uint8_t *) (&val), - sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - - *queue = val; - return SW_OK; -} - -static sw_error_t -_shiva_cosmap_dscp_queue_set(a_uint32_t dev_id, a_uint32_t dscp, - fal_queue_t queue) -{ - sw_error_t rv; - a_uint32_t val; - a_uint32_t offsetaddr; - a_uint16_t fieldoffset; - hsl_dev_t *p_dev = NULL; - - HSL_DEV_ID_CHECK(dev_id); - - if (FAL_DSCP_MAX < dscp) - { - return SW_BAD_PARAM; - } - - SW_RTN_ON_NULL(p_dev = hsl_dev_ptr_get(dev_id)); - if (p_dev->nr_queue <= queue) - { - return SW_BAD_PARAM; - } - - offsetaddr = (dscp >> 4) << 2; - fieldoffset = (dscp & 0xf) << 1; - - val = queue; - HSL_REG_FIELD_GEN_SET(rv, dev_id, (IP_PRI_MAPPING_OFFSET + offsetaddr), - 2, fieldoffset, (a_uint8_t *) (&val), sizeof (a_uint32_t)); - return rv; -} - -static sw_error_t -_shiva_cosmap_dscp_queue_get(a_uint32_t dev_id, a_uint32_t dscp, - fal_queue_t * queue) -{ - sw_error_t rv; - a_uint32_t val = 0; - a_uint32_t offsetaddr; - a_uint16_t fieldoffset; - - HSL_DEV_ID_CHECK(dev_id); - - if (FAL_DSCP_MAX < dscp) - { - return SW_BAD_PARAM; - } - - offsetaddr = (dscp / 16) << 2; - fieldoffset = (dscp & 0xf) << 1; - - HSL_REG_FIELD_GEN_GET(rv, dev_id, (IP_PRI_MAPPING_OFFSET + offsetaddr), - 2, fieldoffset, (a_uint8_t *) (&val), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - - *queue = val; - return SW_OK; -} - -static sw_error_t -_shiva_qos_port_mode_set(a_uint32_t dev_id, fal_port_t port_id, - fal_qos_mode_t mode, a_bool_t enable) -{ - sw_error_t rv; - a_uint32_t val; - - HSL_DEV_ID_CHECK(dev_id); - - if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU)) - { - return SW_BAD_PARAM; - } - - if (A_TRUE == enable) - { - val = 1; - } - else if (A_FALSE == enable) - { - val = 0; - } - else - { - return SW_BAD_PARAM; - } - - if (FAL_QOS_DA_MODE == mode) - { - HSL_REG_FIELD_SET(rv, dev_id, PRI_CTL, port_id, DA_PRI_EN, - (a_uint8_t *) (&val), sizeof (a_uint32_t)); - } - else if (FAL_QOS_UP_MODE == mode) - { - HSL_REG_FIELD_SET(rv, dev_id, PRI_CTL, port_id, VLAN_PRI_EN, - (a_uint8_t *) (&val), sizeof (a_uint32_t)); - } - else if (FAL_QOS_DSCP_MODE == mode) - { - HSL_REG_FIELD_SET(rv, dev_id, PRI_CTL, port_id, IP_PRI_EN, - (a_uint8_t *) (&val), sizeof (a_uint32_t)); - } - else if (FAL_QOS_PORT_MODE == mode) - { - HSL_REG_FIELD_SET(rv, dev_id, PRI_CTL, port_id, PORT_PRI_EN, - (a_uint8_t *) (&val), sizeof (a_uint32_t)); - } - else - { - return SW_BAD_PARAM; - } - - return rv; -} - -static sw_error_t -_shiva_qos_port_mode_get(a_uint32_t dev_id, fal_port_t port_id, - fal_qos_mode_t mode, a_bool_t * enable) -{ - sw_error_t rv; - a_uint32_t val = 0; - - HSL_DEV_ID_CHECK(dev_id); - - if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU)) - { - return SW_BAD_PARAM; - } - - if (FAL_QOS_DA_MODE == mode) - { - HSL_REG_FIELD_GET(rv, dev_id, PRI_CTL, port_id, DA_PRI_EN, - (a_uint8_t *) (&val), sizeof (a_uint32_t)); - } - else if (FAL_QOS_UP_MODE == mode) - { - HSL_REG_FIELD_GET(rv, dev_id, PRI_CTL, port_id, VLAN_PRI_EN, - (a_uint8_t *) (&val), sizeof (a_uint32_t)); - } - else if (FAL_QOS_DSCP_MODE == mode) - { - HSL_REG_FIELD_GET(rv, dev_id, PRI_CTL, port_id, IP_PRI_EN, - (a_uint8_t *) (&val), sizeof (a_uint32_t)); - } - else if (FAL_QOS_PORT_MODE == mode) - { - HSL_REG_FIELD_GET(rv, dev_id, PRI_CTL, port_id, PORT_PRI_EN, - (a_uint8_t *) (&val), sizeof (a_uint32_t)); - } - else - { - return SW_BAD_PARAM; - } - SW_RTN_ON_ERROR(rv); - - if (1 == val) - { - *enable = A_TRUE; - } - else - { - *enable = A_FALSE; - } - - return SW_OK; -} - -static sw_error_t -_shiva_qos_port_mode_pri_set(a_uint32_t dev_id, fal_port_t port_id, - fal_qos_mode_t mode, a_uint32_t pri) -{ - sw_error_t rv; - a_uint32_t val = 0; - - HSL_DEV_ID_CHECK(dev_id); - - if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU)) - { - return SW_BAD_PARAM; - } - - if (SHIVA_MAX_QOS_MODE_PRI < pri) - { - return SW_BAD_PARAM; - } - - HSL_REG_ENTRY_GET(rv, dev_id, PRI_CTL, port_id, (a_uint8_t *) (&val), - sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - - if (FAL_QOS_DA_MODE == mode) - { - SW_SET_REG_BY_FIELD(PRI_CTL, DA_PRI_SEL, pri, val); - } - else if (FAL_QOS_UP_MODE == mode) - { - SW_SET_REG_BY_FIELD(PRI_CTL, VLAN_PRI_SEL, pri, val); - } - else if (FAL_QOS_DSCP_MODE == mode) - { - SW_SET_REG_BY_FIELD(PRI_CTL, IP_PRI_SEL, pri, val); - } - else if (FAL_QOS_PORT_MODE == mode) - { - SW_SET_REG_BY_FIELD(PRI_CTL, PORT_PRI_SEL, pri, val); - } - else - { - return SW_NOT_SUPPORTED; - } - - HSL_REG_ENTRY_SET(rv, dev_id, PRI_CTL, port_id, (a_uint8_t *) (&val), - sizeof (a_uint32_t)); - return rv; -} - -static sw_error_t -_shiva_qos_port_mode_pri_get(a_uint32_t dev_id, fal_port_t port_id, - fal_qos_mode_t mode, a_uint32_t * pri) -{ - sw_error_t rv; - a_uint32_t entry = 0, f_val; - - HSL_DEV_ID_CHECK(dev_id); - - if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU)) - { - return SW_BAD_PARAM; - } - - HSL_REG_ENTRY_GET(rv, dev_id, PRI_CTL, port_id, (a_uint8_t *) (&entry), - sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - - if (FAL_QOS_DA_MODE == mode) - { - SW_GET_FIELD_BY_REG(PRI_CTL, DA_PRI_SEL, f_val, entry); - } - else if (FAL_QOS_UP_MODE == mode) - { - SW_GET_FIELD_BY_REG(PRI_CTL, VLAN_PRI_SEL, f_val, entry); - } - else if (FAL_QOS_DSCP_MODE == mode) - { - SW_GET_FIELD_BY_REG(PRI_CTL, IP_PRI_SEL, f_val, entry); - } - else if (FAL_QOS_PORT_MODE == mode) - { - SW_GET_FIELD_BY_REG(PRI_CTL, PORT_PRI_SEL, f_val, entry); - } - else - { - return SW_NOT_SUPPORTED; - } - - *pri = f_val; - return SW_OK; -} - -static sw_error_t -_shiva_qos_port_default_up_set(a_uint32_t dev_id, fal_port_t port_id, - a_uint32_t up) -{ - sw_error_t rv; - a_uint32_t val; - - HSL_DEV_ID_CHECK(dev_id); - - if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU)) - { - return SW_BAD_PARAM; - } - - if (FAL_DOT1P_MAX < up) - { - return SW_BAD_PARAM; - } - - val = up; - HSL_REG_FIELD_SET(rv, dev_id, PORT_DOT1AD, port_id, ING_PRI, - (a_uint8_t *) (&val), sizeof (a_uint32_t)); - return rv; -} - -static sw_error_t -_shiva_qos_port_default_up_get(a_uint32_t dev_id, fal_port_t port_id, - a_uint32_t * up) -{ - sw_error_t rv; - a_uint32_t val = 0; - - HSL_DEV_ID_CHECK(dev_id); - - if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU)) - { - return SW_BAD_PARAM; - } - - HSL_REG_FIELD_GET(rv, dev_id, PORT_DOT1AD, port_id, ING_PRI, - (a_uint8_t *) (&val), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - - *up = val; - return SW_OK; -} - -static sw_error_t -_shiva_qos_port_sch_mode_set(a_uint32_t dev_id, a_uint32_t port_id, - fal_sch_mode_t mode, const a_uint32_t weight[]) -{ - sw_error_t rv; - a_uint32_t reg = 0, val, w[4] = {0}; - a_int32_t i, _index; - - HSL_DEV_ID_CHECK(dev_id); - - if (FAL_SCH_SP_MODE == mode) - { - val = 0; - _index = -1; - } - else if (FAL_SCH_WRR_MODE == mode) - { - val = 3; - _index = 3; - } - else if (FAL_SCH_MIX_MODE == mode) - { - val = 1; - _index = 2; - } - else if (FAL_SCH_MIX_PLUS_MODE == mode) - { - val = 2; - _index = 1; - } - else - { - return SW_NOT_SUPPORTED; - } - - for (i = _index; i >= 0; i--) - { - if (weight[i] > 0x1f) - { - return SW_BAD_PARAM; - } - w[i] = weight[i]; - } - - HSL_REG_ENTRY_GET(rv, dev_id, WRR_CTRL, port_id, (a_uint8_t *) (®), - sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - - SW_SET_REG_BY_FIELD(WRR_CTRL, SCH_MODE, val, reg); - SW_SET_REG_BY_FIELD(WRR_CTRL, Q3_W, w[3], reg); - SW_SET_REG_BY_FIELD(WRR_CTRL, Q2_W, w[2], reg); - SW_SET_REG_BY_FIELD(WRR_CTRL, Q1_W, w[1], reg); - SW_SET_REG_BY_FIELD(WRR_CTRL, Q0_W, w[0], reg); - - HSL_REG_ENTRY_SET(rv, dev_id, WRR_CTRL, port_id, - (a_uint8_t *) (®), sizeof (a_uint32_t)); - return rv; -} - -static sw_error_t -_shiva_qos_port_sch_mode_get(a_uint32_t dev_id, a_uint32_t port_id, - fal_sch_mode_t * mode, a_uint32_t weight[]) -{ - sw_error_t rv; - a_uint32_t val = 0, sch, w[4], i; - - HSL_DEV_ID_CHECK(dev_id); - - HSL_REG_ENTRY_GET(rv, dev_id, WRR_CTRL, port_id, (a_uint8_t *) (&val), - sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - - SW_GET_FIELD_BY_REG(WRR_CTRL, SCH_MODE, sch, val); - SW_GET_FIELD_BY_REG(WRR_CTRL, Q3_W, w[3], val); - SW_GET_FIELD_BY_REG(WRR_CTRL, Q2_W, w[2], val); - SW_GET_FIELD_BY_REG(WRR_CTRL, Q1_W, w[1], val); - SW_GET_FIELD_BY_REG(WRR_CTRL, Q0_W, w[0], val); - - if (0 == sch) - { - *mode = FAL_SCH_SP_MODE; - } - else if (1 == sch) - { - *mode = FAL_SCH_MIX_MODE; - } - else if (2 == sch) - { - *mode = FAL_SCH_MIX_PLUS_MODE; - } - else - { - *mode = FAL_SCH_WRR_MODE; - } - - for (i = 0; i < 6; i++) - { - weight[i] = 0; - } - - for (i = 0; i < 4; i++) - { - weight[i] = w[i]; - } - - return SW_OK; -} - -/** - * @brief Set buffer aggsinment status of transmitting queue on one particular port. - * @details Comments: - * If enable queue tx buffer on one port that means each queue of this port - * will have fixed number buffers when transmitting packets. Otherwise they - * share the whole buffers with other queues in device. - * @param[in] dev_id device id - * @param[in] port_id port id - * @param[in] enable A_TRUE or A_FALSE - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -shiva_qos_queue_tx_buf_status_set(a_uint32_t dev_id, fal_port_t port_id, - a_bool_t enable) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _shiva_qos_queue_tx_buf_status_set(dev_id, port_id, enable); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Get buffer aggsinment status of transmitting queue on particular port. - * @param[in] dev_id device id - * @param[in] port_id port id - * @param[in] enable A_TRUE or A_FALSE - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -shiva_qos_queue_tx_buf_status_get(a_uint32_t dev_id, fal_port_t port_id, - a_bool_t * enable) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _shiva_qos_queue_tx_buf_status_get(dev_id, port_id, enable); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Set buffer aggsinment status of transmitting port on one particular port. - * @details Comments: - If enable tx buffer on one port that means this port will have fixed - number buffers when transmitting packets. Otherwise they will - share the whole buffers with other ports in device. - * function will return actual buffer numbers in hardware. - * @param[in] dev_id device id - * @param[in] port_id port id - * @param[in] enable A_TRUE or A_FALSE - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -shiva_qos_port_tx_buf_status_set(a_uint32_t dev_id, fal_port_t port_id, - a_bool_t enable) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _shiva_qos_port_tx_buf_status_set(dev_id, port_id, enable); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Get buffer aggsinment status of transmitting port on one particular port. - * @param[in] dev_id device id - * @param[in] port_id port id - * @param[out] enable A_TRUE or A_FALSE - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -shiva_qos_port_tx_buf_status_get(a_uint32_t dev_id, fal_port_t port_id, - a_bool_t * enable) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _shiva_qos_port_tx_buf_status_get(dev_id, port_id, enable); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Set max occupied buffer number of transmitting queue on one particular port. - * @details Comments: - The step of buffer number in SHIVA is 4, function will return actual - buffer numbers in hardware. - The buffer number range for queue is 4 to 60. - * share the whole buffers with other ports in device. - * @param[in] dev_id device id - * @param[in] port_id port id - * @param[in] queue_id queue id - * @param number buffer number - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -shiva_qos_queue_tx_buf_nr_set(a_uint32_t dev_id, fal_port_t port_id, - fal_queue_t queue_id, a_uint32_t * number) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _shiva_qos_queue_tx_buf_nr_set(dev_id, port_id, queue_id, number); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Get max occupied buffer number of transmitting queue on one particular port. - * @param[in] dev_id device id - * @param[in] port_id port id - * @param[in] queue_id queue id - * @param[out] number buffer number - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -shiva_qos_queue_tx_buf_nr_get(a_uint32_t dev_id, fal_port_t port_id, - fal_queue_t queue_id, a_uint32_t * number) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _shiva_qos_queue_tx_buf_nr_get(dev_id, port_id, queue_id, number); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Set max occupied buffer number of transmitting port on one particular port. - * @details Comments: - The step of buffer number in SHIVA is four, function will return actual - buffer numbers in hardware. - The buffer number range for transmitting port is 4 to 124. - * @param[in] dev_id device id - * @param[in] port_id port id - * @param number buffer number - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -shiva_qos_port_tx_buf_nr_set(a_uint32_t dev_id, fal_port_t port_id, - a_uint32_t * number) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _shiva_qos_port_tx_buf_nr_set(dev_id, port_id, number); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Get max occupied buffer number of transmitting port on one particular port. - * @param[in] dev_id device id - * @param[in] port_id port id - * @param[out] number buffer number - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -shiva_qos_port_tx_buf_nr_get(a_uint32_t dev_id, fal_port_t port_id, - a_uint32_t * number) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _shiva_qos_port_tx_buf_nr_get(dev_id, port_id, number); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Set max occupied buffer number of receiving port on one particular port. - * @details Comments: - The step of buffer number in SHIVA is four, function will return actual - buffer numbers in hardware. - The buffer number range for receiving port is 4 to 60. - * @param[in] dev_id device id - * @param[in] port_id port id - * @param number buffer number - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -shiva_qos_port_rx_buf_nr_set(a_uint32_t dev_id, fal_port_t port_id, - a_uint32_t * number) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _shiva_qos_port_rx_buf_nr_set(dev_id, port_id, number); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Get max occupied buffer number of receiving port on one particular port. - * @param[in] dev_id device id - * @param[in] port_id port id - * @param[out] number buffer number - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -shiva_qos_port_rx_buf_nr_get(a_uint32_t dev_id, fal_port_t port_id, - a_uint32_t * number) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _shiva_qos_port_rx_buf_nr_get(dev_id, port_id, number); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Set user priority to mapping on one particular device. - * @param[in] dev_id device id - * @param[in] dot1p 802.1p - * @param[in] queue queue id - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -shiva_cosmap_up_queue_set(a_uint32_t dev_id, a_uint32_t up, - fal_queue_t queue) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _shiva_cosmap_up_queue_set(dev_id, up, queue); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Get user priority to mapping on one particular device. - * @param[in] dev_id device id - * @param[in] dot1p 802.1p - * @param[out] queue queue id - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -shiva_cosmap_up_queue_get(a_uint32_t dev_id, a_uint32_t up, - fal_queue_t * queue) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _shiva_cosmap_up_queue_get(dev_id, up, queue); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Set cos map dscp_2_queue item on one particular device. - * @param[in] dev_id device id - * @param[in] dscp dscp - * @param[in] queue queue id - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -shiva_cosmap_dscp_queue_set(a_uint32_t dev_id, a_uint32_t dscp, - fal_queue_t queue) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _shiva_cosmap_dscp_queue_set(dev_id, dscp, queue); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Get cos map dscp_2_queue item on one particular device. - * @param[in] dev_id device id - * @param[in] dscp dscp - * @param[out] queue queue id - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -shiva_cosmap_dscp_queue_get(a_uint32_t dev_id, a_uint32_t dscp, - fal_queue_t * queue) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _shiva_cosmap_dscp_queue_get(dev_id, dscp, queue); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Set port qos mode on a particular port. - * @param[in] dev_id device id - * @param[in] port_id port id - * @param[in] mode qos mode - * @param[in] enable A_TRUE of A_FALSE - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -shiva_qos_port_mode_set(a_uint32_t dev_id, fal_port_t port_id, - fal_qos_mode_t mode, a_bool_t enable) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _shiva_qos_port_mode_set(dev_id, port_id, mode, enable); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Get port qos mode on a particular port. - * @param[in] dev_id device id - * @param[in] port_id port id - * @param[in] mode qos mode - * @param[out] enable A_TRUE of A_FALSE - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -shiva_qos_port_mode_get(a_uint32_t dev_id, fal_port_t port_id, - fal_qos_mode_t mode, a_bool_t * enable) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _shiva_qos_port_mode_get(dev_id, port_id, mode, enable); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Set priority of one particular qos mode on one particular port. - * @details Comments: - If the priority of a mode is more small then the priority is more high. - Differnet mode should have differnet priority. - * @param[in] dev_id device id - * @param[in] port_id port id - * @param[in] mode qos mode - * @param[in] pri priority of one particular qos mode - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -shiva_qos_port_mode_pri_set(a_uint32_t dev_id, fal_port_t port_id, - fal_qos_mode_t mode, a_uint32_t pri) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _shiva_qos_port_mode_pri_set(dev_id, port_id, mode, pri); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Get priority of one particular qos mode on one particular port. - * @param[in] dev_id device id - * @param[in] port_id port id - * @param[in] mode qos mode - * @param[out] pri priority of one particular qos mode - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -shiva_qos_port_mode_pri_get(a_uint32_t dev_id, fal_port_t port_id, - fal_qos_mode_t mode, a_uint32_t * pri) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _shiva_qos_port_mode_pri_get(dev_id, port_id, mode, pri); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Set default user priority on one particular port. - * @param[in] dev_id device id - * @param[in] port_id port id - * @param[in] up 802.1p - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -shiva_qos_port_default_up_set(a_uint32_t dev_id, fal_port_t port_id, - a_uint32_t up) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _shiva_qos_port_default_up_set(dev_id, port_id, up); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Get default user priority on one particular port. - * @param[in] dev_id device id - * @param[in] port_id port id - * @param[out] up 802.1p - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -shiva_qos_port_default_up_get(a_uint32_t dev_id, fal_port_t port_id, - a_uint32_t * up) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _shiva_qos_port_default_up_get(dev_id, port_id, up); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Set traffic scheduling mode on particular one port. - * @details Comments: - * When scheduling mode is sp the weight is meaningless usually it's zero - * @param[in] dev_id device id - * @param[in] port_id port id - * @param[in] fal_sch_mode_t traffic scheduling mode - * @param[in] weight[] weight value for each queue when in wrr mode, - the max value supported by SHIVA is 0x1f. - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -shiva_qos_port_sch_mode_set(a_uint32_t dev_id, a_uint32_t port_id, - fal_sch_mode_t mode, const a_uint32_t weight[]) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _shiva_qos_port_sch_mode_set(dev_id, port_id, mode, weight); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Get traffic scheduling mode on particular port. - * @param[in] dev_id device id - * @param[in] port_id port id - * @param[out] fal_sch_mode_t traffic scheduling mode - * @param[out] weight weight value for wrr mode - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -shiva_qos_port_sch_mode_get(a_uint32_t dev_id, a_uint32_t port_id, - fal_sch_mode_t * mode, a_uint32_t weight[]) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _shiva_qos_port_sch_mode_get(dev_id, port_id, mode, weight); - HSL_API_UNLOCK; - return rv; -} - -sw_error_t -shiva_qos_init(a_uint32_t dev_id) -{ - HSL_DEV_ID_CHECK(dev_id); - -#ifndef HSL_STANDALONG - { - hsl_api_t *p_api; - - SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id)); - - p_api->qos_queue_tx_buf_status_set = shiva_qos_queue_tx_buf_status_set; - p_api->qos_queue_tx_buf_status_get = shiva_qos_queue_tx_buf_status_get; - p_api->qos_port_tx_buf_status_set = shiva_qos_port_tx_buf_status_set; - p_api->qos_port_tx_buf_status_get = shiva_qos_port_tx_buf_status_get; - p_api->qos_queue_tx_buf_nr_set = shiva_qos_queue_tx_buf_nr_set; - p_api->qos_queue_tx_buf_nr_get = shiva_qos_queue_tx_buf_nr_get; - p_api->qos_port_tx_buf_nr_set = shiva_qos_port_tx_buf_nr_set; - p_api->qos_port_tx_buf_nr_get = shiva_qos_port_tx_buf_nr_get; - p_api->qos_port_rx_buf_nr_set = shiva_qos_port_rx_buf_nr_set; - p_api->qos_port_rx_buf_nr_get = shiva_qos_port_rx_buf_nr_get; - p_api->cosmap_up_queue_set = shiva_cosmap_up_queue_set; - p_api->cosmap_up_queue_get = shiva_cosmap_up_queue_get; - p_api->cosmap_dscp_queue_set = shiva_cosmap_dscp_queue_set; - p_api->cosmap_dscp_queue_get = shiva_cosmap_dscp_queue_get; - p_api->qos_port_mode_set = shiva_qos_port_mode_set; - p_api->qos_port_mode_get = shiva_qos_port_mode_get; - p_api->qos_port_mode_pri_set = shiva_qos_port_mode_pri_set; - p_api->qos_port_mode_pri_get = shiva_qos_port_mode_pri_get; - p_api->qos_port_default_up_set = shiva_qos_port_default_up_set; - p_api->qos_port_default_up_get = shiva_qos_port_default_up_get; - p_api->qos_port_sch_mode_set = shiva_qos_port_sch_mode_set; - p_api->qos_port_sch_mode_get = shiva_qos_port_sch_mode_get; - } -#endif - - return SW_OK; -} - -/** - * @} - */ - diff --git a/feeds/ipq807x/qca-ssdk/src/src/hsl/shiva/shiva_rate.c b/feeds/ipq807x/qca-ssdk/src/src/hsl/shiva/shiva_rate.c deleted file mode 100755 index e6c64c023..000000000 --- a/feeds/ipq807x/qca-ssdk/src/src/hsl/shiva/shiva_rate.c +++ /dev/null @@ -1,852 +0,0 @@ -/* - * Copyright (c) 2012, 2016, The Linux Foundation. All rights reserved. - * Permission to use, copy, modify, and/or distribute this software for - * any purpose with or without fee is hereby granted, provided that the - * above copyright notice and this permission notice appear in all copies. - * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES - * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR - * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES - * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN - * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT - * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. - */ - - -/** - * @defgroup shiva_rate SHIVA_RATE - * @{ - */ -#include "sw.h" -#include "hsl.h" -#include "hsl_dev.h" -#include "hsl_port_prop.h" -#include "shiva_rate.h" -#include "shiva_reg.h" - -#define SHIVA_STORM_MIN_RATE_PPS 1000 -#define SHIVA_STORM_MAX_RATE_PPS (1024 * 1000) - -static sw_error_t -shiva_stormrate_sw_to_hw(a_uint32_t swrate, a_uint32_t * hwrate) -{ - a_uint32_t shrnr = 0; - a_uint32_t tmp = swrate / 1000; - - if ((SHIVA_STORM_MIN_RATE_PPS > swrate) - || (SHIVA_STORM_MAX_RATE_PPS < swrate)) - { - return SW_BAD_PARAM; - } - - while ((tmp != 0) && (shrnr < 12)) - { - tmp = tmp >> 1; - shrnr++; - } - - if (12 == shrnr) - { - return SW_BAD_PARAM; - } - - *hwrate = shrnr; - return SW_OK; -} - -static sw_error_t -shiva_stormrate_hw_to_sw(a_uint32_t hwrate, a_uint32_t * swrate) -{ - if (0 == hwrate) - { - hwrate = 1; - } - - if ((1 > hwrate) || (11 < hwrate)) - { - return SW_BAD_PARAM; - } - - *swrate = (1 << (hwrate - 1)) * 1000; - return SW_OK; -} - -static sw_error_t -_shiva_rate_queue_egrl_set(a_uint32_t dev_id, fal_port_t port_id, - fal_queue_t queue_id, a_uint32_t * speed, - a_bool_t enable) -{ - sw_error_t rv; - a_uint32_t val; - a_uint32_t portrl = 0; - - if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU)) - { - return SW_BAD_PARAM; - } - - HSL_REG_FIELD_GET(rv, dev_id, RATE_LIMIT0, port_id, EG_RATE_EN, - (a_uint8_t *) (&portrl), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - - if (A_TRUE == enable) - { - if (1 == portrl) - { - /* already enable port egress rate limit, queue and port - egress rate limit can't coexist */ - return SW_NOT_SUPPORTED; - } - - if ((0x7ffe << 5) < *speed) - { - return SW_BAD_PARAM; - } - val = *speed >> 5; - *speed = val << 5; - } - else if (A_FALSE == enable) - { - val = 0x7fff; - *speed = 0; - if (1 == portrl) - { - /* already enable port egress rate limit */ - return SW_OK; - } - } - else - { - return SW_BAD_PARAM; - } - - if (0 == queue_id) - { - HSL_REG_FIELD_SET(rv, dev_id, RATE_LIMIT1, port_id, EG_Q0_RATE, - (a_uint8_t *) (&val), sizeof (a_uint32_t)); - } - else if (1 == queue_id) - { - HSL_REG_FIELD_SET(rv, dev_id, RATE_LIMIT1, port_id, EG_Q1_RATE, - (a_uint8_t *) (&val), sizeof (a_uint32_t)); - } - else if (2 == queue_id) - { - HSL_REG_FIELD_SET(rv, dev_id, RATE_LIMIT2, port_id, EG_Q2_RATE, - (a_uint8_t *) (&val), sizeof (a_uint32_t)); - } - else if (3 == queue_id) - { - HSL_REG_FIELD_SET(rv, dev_id, RATE_LIMIT2, port_id, EG_Q3_RATE, - (a_uint8_t *) (&val), sizeof (a_uint32_t)); - } - else - { - return SW_BAD_PARAM; - } - - return rv; -} - -static sw_error_t -_shiva_rate_queue_egrl_get(a_uint32_t dev_id, fal_port_t port_id, - fal_queue_t queue_id, a_uint32_t * speed, - a_bool_t * enable) -{ - sw_error_t rv; - a_uint32_t val = 0; - - if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU)) - { - return SW_BAD_PARAM; - } - - HSL_REG_FIELD_GET(rv, dev_id, RATE_LIMIT0, port_id, EG_RATE_EN, - (a_uint8_t *) (&val), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - - if (1 == val) - { - /* already enable port egress rate limit */ - *speed = 0; - *enable = A_FALSE; - - return SW_OK; - } - - if (0 == queue_id) - { - HSL_REG_FIELD_GET(rv, dev_id, RATE_LIMIT1, port_id, EG_Q0_RATE, - (a_uint8_t *) (&val), sizeof (a_uint32_t)); - } - else if (1 == queue_id) - { - HSL_REG_FIELD_GET(rv, dev_id, RATE_LIMIT1, port_id, EG_Q1_RATE, - (a_uint8_t *) (&val), sizeof (a_uint32_t)); - } - else if (2 == queue_id) - { - HSL_REG_FIELD_GET(rv, dev_id, RATE_LIMIT2, port_id, EG_Q2_RATE, - (a_uint8_t *) (&val), sizeof (a_uint32_t)); - } - else if (3 == queue_id) - { - HSL_REG_FIELD_GET(rv, dev_id, RATE_LIMIT2, port_id, EG_Q3_RATE, - (a_uint8_t *) (&val), sizeof (a_uint32_t)); - } - else - { - return SW_BAD_PARAM; - } - - SW_RTN_ON_ERROR(rv); - - if (0x7fff == val) - { - *enable = A_FALSE; - } - else - { - *enable = A_TRUE; - *speed = val << 5; - } - - return SW_OK; -} - -static sw_error_t -_shiva_rate_port_egrl_set(a_uint32_t dev_id, fal_port_t port_id, - a_uint32_t * speed, a_bool_t enable) -{ - sw_error_t rv; - a_uint32_t val = 0; - a_uint32_t portrl = 0; - - HSL_DEV_ID_CHECK(dev_id); - - if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU)) - { - return SW_BAD_PARAM; - } - - HSL_REG_FIELD_GET(rv, dev_id, RATE_LIMIT0, port_id, EG_RATE_EN, - (a_uint8_t *) (&portrl), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - - if (A_FALSE == enable) - { - *speed = 0; - - /* if port egress rate limit current enable then disable */ - if (1 == portrl) - { - val = 0; - HSL_REG_FIELD_SET(rv, dev_id, RATE_LIMIT0, port_id, EG_RATE_EN, - (a_uint8_t *) (&val), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - - val = 0x7fff; - HSL_REG_FIELD_SET(rv, dev_id, RATE_LIMIT2, port_id, EG_Q3_RATE, - (a_uint8_t *) (&val), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - } - - rv = SW_OK; - } - else - { - if ((0x7ffe << 5) < *speed) - { - return SW_BAD_PARAM; - } - - /* not enable egress port rate limit */ - if (0 == portrl) - { - HSL_REG_FIELD_GET(rv, dev_id, RATE_LIMIT1, port_id, EG_Q0_RATE, - (a_uint8_t *) (&val), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - - if (0x7fff != val) - { - /* already enable egress queue0 rate limit, queue and port - egress rate limit can't coexist */ - return SW_NOT_SUPPORTED; - } - - HSL_REG_FIELD_GET(rv, dev_id, RATE_LIMIT1, port_id, EG_Q1_RATE, - (a_uint8_t *) (&val), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - - if (0x7fff != val) - { - /* already enable egress queue1 rate limit, queue and port - egress rate limit can't coexist */ - return SW_NOT_SUPPORTED; - } - - HSL_REG_FIELD_GET(rv, dev_id, RATE_LIMIT2, port_id, EG_Q2_RATE, - (a_uint8_t *) (&val), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - - if (0x7fff != val) - { - /* already enable egress queue2 rate limit, queue and port - egress rate limit can't coexist */ - return SW_NOT_SUPPORTED; - } - - HSL_REG_FIELD_GET(rv, dev_id, RATE_LIMIT2, port_id, EG_Q3_RATE, - (a_uint8_t *) (&val), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - - if (0x7fff != val) - { - /* already enable egress queue3 rate limit, queue and port - egress rate limit can't coexist */ - return SW_NOT_SUPPORTED; - } - - val = 1; - HSL_REG_FIELD_SET(rv, dev_id, RATE_LIMIT0, port_id, EG_RATE_EN, - (a_uint8_t *) (&val), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - } - - val = *speed >> 5; - *speed = val << 5; - HSL_REG_FIELD_SET(rv, dev_id, RATE_LIMIT2, port_id, EG_Q3_RATE, - (a_uint8_t *) (&val), sizeof (a_uint32_t)); - } - - return rv; -} - -static sw_error_t -_shiva_rate_port_egrl_get(a_uint32_t dev_id, fal_port_t port_id, - a_uint32_t * speed, a_bool_t * enable) -{ - sw_error_t rv; - a_uint32_t val = 0; - - HSL_DEV_ID_CHECK(dev_id); - - if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU)) - { - return SW_BAD_PARAM; - } - - HSL_REG_FIELD_GET(rv, dev_id, RATE_LIMIT0, port_id, EG_RATE_EN, - (a_uint8_t *) (&val), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - - if (0 == val) - { - *speed = 0; - *enable = A_FALSE; - return SW_OK; - } - - HSL_REG_FIELD_GET(rv, dev_id, RATE_LIMIT2, port_id, EG_Q3_RATE, - (a_uint8_t *) (&val), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - *enable = A_TRUE; - *speed = val << 5; - - return SW_OK; -} - -static sw_error_t -_shiva_rate_port_inrl_set(a_uint32_t dev_id, fal_port_t port_id, - a_uint32_t * speed, a_bool_t enable) -{ - sw_error_t rv; - a_uint32_t val; - - HSL_DEV_ID_CHECK(dev_id); - - if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU)) - { - return SW_BAD_PARAM; - } - - if (A_TRUE == enable) - { - if ((0x7ffe << 5) < *speed) - { - return SW_BAD_PARAM; - } - val = *speed >> 5; - *speed = val << 5; - } - else if (A_FALSE == enable) - { - val = 0x7fff; - *speed = 0; - } - else - { - return SW_BAD_PARAM; - } - - HSL_REG_FIELD_SET(rv, dev_id, RATE_LIMIT0, port_id, ING_RATE, - (a_uint8_t *) (&val), sizeof (a_uint32_t)); - return rv; -} - -static sw_error_t -_shiva_rate_port_inrl_get(a_uint32_t dev_id, fal_port_t port_id, - a_uint32_t * speed, a_bool_t * enable) -{ - sw_error_t rv; - a_uint32_t val = 0; - - HSL_DEV_ID_CHECK(dev_id); - - if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU)) - { - return SW_BAD_PARAM; - } - - HSL_REG_FIELD_GET(rv, dev_id, RATE_LIMIT0, port_id, ING_RATE, - (a_uint8_t *) (&val), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - - if (0x7fff == val) - { - *enable = A_FALSE; - *speed = 0; - } - else - { - *enable = A_TRUE; - *speed = val << 5; - } - - return SW_OK; -} - -static sw_error_t -_shiva_storm_ctrl_frame_set(a_uint32_t dev_id, fal_port_t port_id, - fal_storm_type_t storm_type, a_bool_t enable) -{ - a_uint32_t data; - sw_error_t rv; - - HSL_DEV_ID_CHECK(dev_id); - - if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU)) - { - return SW_BAD_PARAM; - } - - data = 2; - HSL_REG_FIELD_SET(rv, dev_id, STORM_CTL, port_id, UNIT, - (a_uint8_t *) (&data), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - - if (A_TRUE == enable) - { - data = 1; - } - else if (A_FALSE == enable) - { - data = 0; - } - else - { - return SW_BAD_PARAM; - } - - if (FAL_UNICAST_STORM == storm_type) - { - HSL_REG_FIELD_SET(rv, dev_id, STORM_CTL, port_id, UNI_EN, - (a_uint8_t *) (&data), sizeof (a_uint32_t)); - } - else if (FAL_MULTICAST_STORM == storm_type) - { - HSL_REG_FIELD_SET(rv, dev_id, STORM_CTL, port_id, MUL_EN, - (a_uint8_t *) (&data), sizeof (a_uint32_t)); - } - else if (FAL_BROADCAST_STORM == storm_type) - { - HSL_REG_FIELD_SET(rv, dev_id, STORM_CTL, port_id, BRO_EN, - (a_uint8_t *) (&data), sizeof (a_uint32_t)); - } - else - { - return SW_BAD_PARAM; - } - SW_RTN_ON_ERROR(rv); - - HSL_REG_FIELD_GET(rv, dev_id, STORM_CTL, port_id, RATE, - (a_uint8_t *) (&data), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - - if (0 == data) - { - data = 1; - HSL_REG_FIELD_SET(rv, dev_id, STORM_CTL, port_id, RATE, - (a_uint8_t *) (&data), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - } - - return SW_OK; -} - -static sw_error_t -_shiva_storm_ctrl_frame_get(a_uint32_t dev_id, fal_port_t port_id, - fal_storm_type_t storm_type, a_bool_t * enable) -{ - a_uint32_t data = 0; - sw_error_t rv; - - HSL_DEV_ID_CHECK(dev_id); - - if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU)) - { - return SW_BAD_PARAM; - } - - if (FAL_UNICAST_STORM == storm_type) - { - HSL_REG_FIELD_GET(rv, dev_id, STORM_CTL, port_id, UNI_EN, - (a_uint8_t *) (&data), sizeof (a_uint32_t)); - } - else if (FAL_MULTICAST_STORM == storm_type) - { - HSL_REG_FIELD_GET(rv, dev_id, STORM_CTL, port_id, MUL_EN, - (a_uint8_t *) (&data), sizeof (a_uint32_t)); - } - else if (FAL_BROADCAST_STORM == storm_type) - { - HSL_REG_FIELD_GET(rv, dev_id, STORM_CTL, port_id, BRO_EN, - (a_uint8_t *) (&data), sizeof (a_uint32_t)); - } - else - { - return SW_BAD_PARAM; - } - - SW_RTN_ON_ERROR(rv); - - if (1 == data) - { - data = 1; - *enable = A_TRUE; - } - else - { - *enable = A_FALSE; - } - - return SW_OK; -} - -static sw_error_t -_shiva_storm_ctrl_rate_set(a_uint32_t dev_id, fal_port_t port_id, - a_uint32_t * rate_in_pps) -{ - a_uint32_t data; - sw_error_t rv; - - HSL_DEV_ID_CHECK(dev_id); - - if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU)) - { - return SW_BAD_PARAM; - } - - rv = shiva_stormrate_sw_to_hw(*rate_in_pps, &data); - SW_RTN_ON_ERROR(rv); - - HSL_REG_FIELD_SET(rv, dev_id, STORM_CTL, port_id, RATE, - (a_uint8_t *) (&data), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - - rv = shiva_stormrate_hw_to_sw(data, rate_in_pps); - SW_RTN_ON_ERROR(rv); - - return SW_OK; -} - -static sw_error_t -_shiva_storm_ctrl_rate_get(a_uint32_t dev_id, fal_port_t port_id, - a_uint32_t * rate_in_pps) -{ - a_uint32_t data = 0; - sw_error_t rv; - - HSL_DEV_ID_CHECK(dev_id); - - if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU)) - { - return SW_BAD_PARAM; - } - - HSL_REG_FIELD_GET(rv, dev_id, STORM_CTL, port_id, RATE, - (a_uint8_t *) (&data), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - - rv = shiva_stormrate_hw_to_sw(data, rate_in_pps); - return rv; -} - -/** - * @brief Set queue egress rate limit status on one particular port and queue. - * @details Comments: - The granularity of speed is bps. - Because of hardware granularity function will return actual speed in hardware. - When disable queue egress rate limit input parameter speed is meaningless. - Egress queue rate limit can't coexist with port egress rate limit. - The step of speed is 32kbps. - * @param[in] dev_id device id - * @param[in] port_id port id - * @param[in] queue_id queue id - * @param speed rate limit speed - * @param[in] enable A_TRUE or A_FALSE - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -shiva_rate_queue_egrl_set(a_uint32_t dev_id, fal_port_t port_id, - fal_queue_t queue_id, a_uint32_t * speed, - a_bool_t enable) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _shiva_rate_queue_egrl_set(dev_id, port_id, queue_id, speed, enable); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Get queue egress rate limit status on one particular port and queue. - * @param[in] dev_id device id - * @param[in] port_id port id - * @param[in] queue_id queue id - * @param[out] speed rate limit speed - * @param[out] enable A_TRUE or A_FALSE - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -shiva_rate_queue_egrl_get(a_uint32_t dev_id, fal_port_t port_id, - fal_queue_t queue_id, a_uint32_t * speed, - a_bool_t * enable) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _shiva_rate_queue_egrl_get(dev_id, port_id, queue_id, speed, enable); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Set port egress rate limit status on one particular port. - * @details Comments: - The granularity of speed is bps. - Because of hardware granularity function will return actual speed in hardware. - When disable port egress rate limit input parameter speed is meaningless. - Egress port rate limit can't coexist with queue egress rate limit. - The step of speed is 32kbps. - * @param[in] dev_id device id - * @param[in] port_id port id - * @param speed rate limit speed - * @param[in] enable A_TRUE or A_FALSE - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -shiva_rate_port_egrl_set(a_uint32_t dev_id, fal_port_t port_id, - a_uint32_t * speed, a_bool_t enable) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _shiva_rate_port_egrl_set(dev_id, port_id, speed, enable); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Get port egress rate limit status on one particular port. - * @param[in] dev_id device id - * @param[in] port_id port id - * @param[out] speed rate limit speed - * @param[out] enable A_TRUE or A_FALSE - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -shiva_rate_port_egrl_get(a_uint32_t dev_id, fal_port_t port_id, - a_uint32_t * speed, a_bool_t * enable) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _shiva_rate_port_egrl_get(dev_id, port_id, speed, enable); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Set port ingress rate limit status on one particular port. - * @details Comments: - The granularity of speed is bps. - Because of hardware granularity function will return actual speed in hardware. - When disable port ingress rate limit input parameter speed is meaningless. - The step of speed is 32kbps. - * When disable port ingress rate limit input parameter speed is meaningless. - * @param[in] dev_id device id - * @param[in] port_id port id - * @param speed rate limit speed - * @param[in] enable A_TRUE or A_FALSE - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -shiva_rate_port_inrl_set(a_uint32_t dev_id, fal_port_t port_id, - a_uint32_t * speed, a_bool_t enable) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _shiva_rate_port_inrl_set(dev_id, port_id, speed, enable); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Get port ingress rate limit status on one particular port. - * @param[in] dev_id device id - * @param[in] port_id port id - * @param[out] speed rate limit speed - * @param[out] enable A_TRUE or A_FALSE - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -shiva_rate_port_inrl_get(a_uint32_t dev_id, fal_port_t port_id, - a_uint32_t * speed, a_bool_t * enable) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _shiva_rate_port_inrl_get(dev_id, port_id, speed, enable); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Set particular type storm control status on one particular port. - * @details Comments: - * When enable one particular packets type storm control this type packets - * speed will be calculated in storm control. - * @param[in] dev_id device id - * @param[in] port_id port id - * @param[in] frame_type packets type which causes storm - * @param[in] enable A_TRUE or A_FALSE - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -shiva_storm_ctrl_frame_set(a_uint32_t dev_id, fal_port_t port_id, - fal_storm_type_t storm_type, a_bool_t enable) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _shiva_storm_ctrl_frame_set(dev_id, port_id, storm_type, enable); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Get particular type storm control status on one particular port. - * @param[in] dev_id device id - * @param[in] port_id port id - * @param[in] frame_type packets type which causes storm - * @param[out] enable A_TRUE or A_FALSE - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -shiva_storm_ctrl_frame_get(a_uint32_t dev_id, fal_port_t port_id, - fal_storm_type_t storm_type, a_bool_t * enable) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _shiva_storm_ctrl_frame_get(dev_id, port_id, storm_type, enable); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Set storm control speed on one particular port. - * @details Comments: - Because of hardware granularity function will return actual speed in hardware. - The step of speed is kpps. - The speed range is from 1k to 1M - * @param[in] dev_id device id - * @param[in] port_id port id - * @param speed storm control speed - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -shiva_storm_ctrl_rate_set(a_uint32_t dev_id, fal_port_t port_id, - a_uint32_t * rate_in_pps) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _shiva_storm_ctrl_rate_set(dev_id, port_id, rate_in_pps); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Get storm control speed on one particular port. - * @param[in] dev_id device id - * @param[in] port_id port id - * @param[out] speed storm control speed - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -shiva_storm_ctrl_rate_get(a_uint32_t dev_id, fal_port_t port_id, - a_uint32_t * rate_in_pps) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _shiva_storm_ctrl_rate_get(dev_id, port_id, rate_in_pps); - HSL_API_UNLOCK; - return rv; -} - -sw_error_t -shiva_rate_init(a_uint32_t dev_id) -{ - HSL_DEV_ID_CHECK(dev_id); - -#ifndef HSL_STANDALONG - { - hsl_api_t *p_api; - - SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id)); - - p_api->rate_queue_egrl_set = shiva_rate_queue_egrl_set; - p_api->rate_queue_egrl_get = shiva_rate_queue_egrl_get; - p_api->rate_port_egrl_set = shiva_rate_port_egrl_set; - p_api->rate_port_egrl_get = shiva_rate_port_egrl_get; - p_api->rate_port_inrl_set = shiva_rate_port_inrl_set; - p_api->rate_port_inrl_get = shiva_rate_port_inrl_get; - p_api->storm_ctrl_frame_set = shiva_storm_ctrl_frame_set; - p_api->storm_ctrl_frame_get = shiva_storm_ctrl_frame_get; - p_api->storm_ctrl_rate_set = shiva_storm_ctrl_rate_set; - p_api->storm_ctrl_rate_get = shiva_storm_ctrl_rate_get; - } -#endif - - return SW_OK; -} - -/** - * @} - */ - diff --git a/feeds/ipq807x/qca-ssdk/src/src/hsl/shiva/shiva_reduced_acl.c b/feeds/ipq807x/qca-ssdk/src/src/hsl/shiva/shiva_reduced_acl.c deleted file mode 100755 index eb0062980..000000000 --- a/feeds/ipq807x/qca-ssdk/src/src/hsl/shiva/shiva_reduced_acl.c +++ /dev/null @@ -1,178 +0,0 @@ -/* - * Copyright (c) 2012, The Linux Foundation. All rights reserved. - * Permission to use, copy, modify, and/or distribute this software for - * any purpose with or without fee is hereby granted, provided that the - * above copyright notice and this permission notice appear in all copies. - * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES - * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR - * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES - * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN - * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT - * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. - */ - -#include "sw.h" -#include "shiva_reduced_acl.h" -#include "hsl.h" - -#define SHIVA_RULE_VLU_ADDR 0x58400 -#define SHIVA_RULE_MSK_ADDR 0x58c00 -#define SHIVA_RULE_LEN_ADDR 0x58818 -#define SHIVA_RULE_ACT_ADDR 0x58000 -#define SHIVA_RULE_SLCT_ADDR 0x58800 - -sw_error_t -shiva_acl_rule_write(a_uint32_t dev_id, a_uint32_t rule_idx, a_uint32_t vlu[8], - a_uint32_t msk[8]) -{ - sw_error_t rv; - a_uint32_t i, base, addr; - - /* set rule value */ - base = SHIVA_RULE_VLU_ADDR + (rule_idx << 5); - for (i = 0; i < 5; i++) - { - addr = base + (i << 2); - HSL_REG_ENTRY_GEN_SET(rv, dev_id, addr, sizeof (a_uint32_t), - (a_uint8_t *) (&(vlu[i])), - sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - } - - /* set rule mask */ - base = SHIVA_RULE_MSK_ADDR + (rule_idx << 5); - for (i = 0; i < 5; i++) - { - addr = base + (i << 2); - HSL_REG_ENTRY_GEN_SET(rv, dev_id, addr, sizeof (a_uint32_t), - (a_uint8_t *) (&(msk[i])), - sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - } - - return SW_OK; -} - -sw_error_t -shiva_acl_action_write(a_uint32_t dev_id, a_uint32_t act_idx, - a_uint32_t act[3]) -{ - sw_error_t rv; - a_uint32_t base, addr, i; - - /* set rule action */ - base = SHIVA_RULE_ACT_ADDR + (act_idx << 5); - for (i = 0; i < 3; i++) - { - addr = base + (i << 2); - HSL_REG_ENTRY_GEN_SET(rv, dev_id, addr, sizeof (a_uint32_t), - (a_uint8_t *) (&(act[i])), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - } - - return SW_OK; -} - -sw_error_t -shiva_acl_slct_write(a_uint32_t dev_id, a_uint32_t slct_idx, - a_uint32_t slct[8]) -{ - sw_error_t rv; - a_uint32_t base, addr; - a_uint32_t i; - - base = SHIVA_RULE_SLCT_ADDR + (slct_idx << 5); - - /* set rule address */ - for (i = 1; i < 7; i++) - { - addr = base + (i << 2); - HSL_REG_ENTRY_GEN_SET(rv, dev_id, addr, sizeof (a_uint32_t), - (a_uint8_t *) (&(slct[i])), - sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - } - - /* set rule enable */ - HSL_REG_ENTRY_GEN_SET(rv, dev_id, base, sizeof (a_uint32_t), - (a_uint8_t *) (&(slct[0])), - sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - - return SW_OK; -} - -sw_error_t -shiva_acl_rule_read(a_uint32_t dev_id, a_uint32_t rule_idx, a_uint32_t vlu[8], - a_uint32_t msk[8]) -{ - sw_error_t rv; - a_uint32_t i, base, addr; - - /* get rule value */ - base = SHIVA_RULE_VLU_ADDR + (rule_idx << 5); - for (i = 0; i < 5; i++) - { - addr = base + (i << 2); - HSL_REG_ENTRY_GEN_GET(rv, dev_id, addr, sizeof (a_uint32_t), - (a_uint8_t *) (&(vlu[i])), - sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - } - - /* get rule mask */ - base = SHIVA_RULE_MSK_ADDR + (rule_idx << 5); - for (i = 0; i < 5; i++) - { - addr = base + (i << 2); - HSL_REG_ENTRY_GEN_GET(rv, dev_id, addr, sizeof (a_uint32_t), - (a_uint8_t *) (&(msk[i])), - sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - } - - return SW_OK; -} - -sw_error_t -shiva_acl_action_read(a_uint32_t dev_id, a_uint32_t act_idx, - a_uint32_t act[3]) -{ - sw_error_t rv; - a_uint32_t base, addr, i; - - /* get rule action */ - base = SHIVA_RULE_ACT_ADDR + (act_idx << 5); - for (i = 0; i < 3; i++) - { - addr = base + (i << 2); - HSL_REG_ENTRY_GEN_GET(rv, dev_id, addr, sizeof (a_uint32_t), - (a_uint8_t *) (&(act[i])), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - } - - return SW_OK; -} - -sw_error_t -shiva_acl_slct_read(a_uint32_t dev_id, a_uint32_t slct_idx, - a_uint32_t slct[8]) -{ - sw_error_t rv; - a_uint32_t i, base, addr; - - base = SHIVA_RULE_SLCT_ADDR + (slct_idx << 5); - - /* get filter address and enable */ - for (i = 0; i < 7; i++) - { - addr = base + (i << 2); - HSL_REG_ENTRY_GEN_GET(rv, dev_id, addr, sizeof (a_uint32_t), - (a_uint8_t *) (&(slct[i])), - sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - } - - return SW_OK; -} diff --git a/feeds/ipq807x/qca-ssdk/src/src/hsl/shiva/shiva_reg_access.c b/feeds/ipq807x/qca-ssdk/src/src/hsl/shiva/shiva_reg_access.c deleted file mode 100755 index 6a7f57fde..000000000 --- a/feeds/ipq807x/qca-ssdk/src/src/hsl/shiva/shiva_reg_access.c +++ /dev/null @@ -1,271 +0,0 @@ -/* - * Copyright (c) 2012, 2016, The Linux Foundation. All rights reserved. - * Permission to use, copy, modify, and/or distribute this software for - * any purpose with or without fee is hereby granted, provided that the - * above copyright notice and this permission notice appear in all copies. - * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES - * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR - * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES - * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN - * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT - * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. - */ - - -#include "sw.h" -#include "hsl.h" -#include "hsl_dev.h" -#include "sd.h" -#include "shiva_reg_access.h" - -static hsl_access_mode reg_mode; - -#if defined(API_LOCK) -static aos_lock_t mdio_lock; -#define MDIO_LOCKER_INIT aos_lock_init(&mdio_lock) -#define MDIO_LOCKER_LOCK aos_lock(&mdio_lock) -#define MDIO_LOCKER_UNLOCK aos_unlock(&mdio_lock) -#else -#define MDIO_LOCKER_INIT -#define MDIO_LOCKER_LOCK -#define MDIO_LOCKER_UNLOCK -#endif - -static sw_error_t -_shiva_mdio_reg_get(a_uint32_t dev_id, a_uint32_t reg_addr, - a_uint8_t value[], a_uint32_t value_len) -{ - a_uint32_t reg_val; - - if (value_len != sizeof (a_uint32_t)) - return SW_BAD_LEN; - -#if 0 - /* change reg_addr to 16-bit word address, 32-bit aligned */ - reg_word_addr = (reg_addr & 0xfffffffc) >> 1; - - /* configure register high address */ - phy_addr = 0x18; - phy_reg = 0x0; - phy_val = (a_uint16_t) ((reg_word_addr >> 8) & 0x3ff); /* bit16-8 of reg address */ - - rv = sd_reg_mdio_set(dev_id, phy_addr, phy_reg, phy_val); - SW_RTN_ON_ERROR(rv); - - /* For some registers such as MIBs, since it is read/clear, we should */ - /* read the lower 16-bit register then the higher one */ - - /* read register in lower address */ - phy_addr = 0x10 | ((reg_word_addr >> 5) & 0x7); /* bit7-5 of reg address */ - phy_reg = (a_uint8_t) (reg_word_addr & 0x1f); /* bit4-0 of reg address */ - rv = sd_reg_mdio_get(dev_id, phy_addr, phy_reg, &tmp_val); - SW_RTN_ON_ERROR(rv); - reg_val = tmp_val; - - /* read register in higher address */ - reg_word_addr++; - phy_addr = 0x10 | ((reg_word_addr >> 5) & 0x7); /* bit7-5 of reg address */ - phy_reg = (a_uint8_t) (reg_word_addr & 0x1f); /* bit4-0 of reg address */ - rv = sd_reg_mdio_get(dev_id, phy_addr, phy_reg, &tmp_val); - SW_RTN_ON_ERROR(rv); - reg_val |= (((a_uint32_t)tmp_val) << 16); -#else - reg_val = sd_reg_mii_get(dev_id, reg_addr); -#endif - aos_mem_copy(value, ®_val, sizeof (a_uint32_t)); - - return SW_OK; -} - -static sw_error_t -_shiva_mdio_reg_set(a_uint32_t dev_id, a_uint32_t reg_addr, a_uint8_t value[], - a_uint32_t value_len) -{ - a_uint32_t reg_val = 0; - - if (value_len != sizeof (a_uint32_t)) - return SW_BAD_LEN; - - aos_mem_copy(®_val, value, sizeof (a_uint32_t)); - -#if 0 -/* change reg_addr to 16-bit word address, 32-bit aligned */ - reg_word_addr = (reg_addr & 0xfffffffc) >> 1; - - /* configure register high address */ - phy_addr = 0x18; - phy_reg = 0x0; - phy_val = (a_uint16_t) ((reg_word_addr >> 8) & 0x3ff); /* bit16-8 of reg address */ - - rv = sd_reg_mdio_set(dev_id, phy_addr, phy_reg, phy_val); - SW_RTN_ON_ERROR(rv); - - /* For some registers such as ARL and VLAN, since they include BUSY bit */ - /* in lower address, we should write the higher 16-bit register then the */ - /* lower one */ - - /* write register in higher address */ - reg_word_addr++; - phy_addr = 0x10 | ((reg_word_addr >> 5) & 0x7); /* bit7-5 of reg address */ - phy_reg = (a_uint8_t) (reg_word_addr & 0x1f); /* bit4-0 of reg address */ - phy_val = (a_uint16_t) ((reg_val >> 16) & 0xffff); - rv = sd_reg_mdio_set(dev_id, phy_addr, phy_reg, phy_val); - SW_RTN_ON_ERROR(rv); - - /* write register in lower address */ - reg_word_addr--; - phy_addr = 0x10 | ((reg_word_addr >> 5) & 0x7); /* bit7-5 of reg address */ - phy_reg = (a_uint8_t) (reg_word_addr & 0x1f); /* bit4-0 of reg address */ - phy_val = (a_uint16_t) (reg_val & 0xffff); - rv = sd_reg_mdio_set(dev_id, phy_addr, phy_reg, phy_val); - SW_RTN_ON_ERROR(rv); -#else - sd_reg_mii_set(dev_id, reg_addr, reg_val); -#endif - - return SW_OK; -} - -sw_error_t -shiva_phy_get(a_uint32_t dev_id, a_uint32_t phy_addr, - a_uint32_t reg, a_uint16_t * value) -{ - sw_error_t rv; - - MDIO_LOCKER_LOCK; - rv = sd_reg_mdio_get(dev_id, phy_addr, reg, value); - MDIO_LOCKER_UNLOCK; - - return rv; -} - -sw_error_t -shiva_phy_set(a_uint32_t dev_id, a_uint32_t phy_addr, - a_uint32_t reg, a_uint16_t value) -{ - sw_error_t rv; - - MDIO_LOCKER_LOCK; - rv = sd_reg_mdio_set(dev_id, phy_addr, reg, value); - MDIO_LOCKER_UNLOCK; - - return rv; -} - -sw_error_t -shiva_reg_get(a_uint32_t dev_id, a_uint32_t reg_addr, a_uint8_t value[], - a_uint32_t value_len) -{ - sw_error_t rv; - unsigned long flags; - - MDIO_LOCKER_LOCK; - if (HSL_MDIO == reg_mode) - { - aos_irq_save(flags); - rv = _shiva_mdio_reg_get(dev_id, reg_addr, value, value_len); - aos_irq_restore(flags); - } - else - { - rv = sd_reg_hdr_get(dev_id, reg_addr, value, value_len); - } - MDIO_LOCKER_UNLOCK; - - return rv; -} - -sw_error_t -shiva_reg_set(a_uint32_t dev_id, a_uint32_t reg_addr, a_uint8_t value[], - a_uint32_t value_len) -{ - sw_error_t rv; - unsigned long flags; - - MDIO_LOCKER_LOCK; - if (HSL_MDIO == reg_mode) - { - aos_irq_save(flags); - rv = _shiva_mdio_reg_set(dev_id, reg_addr, value, value_len); - aos_irq_restore(flags); - } - else - { - rv = sd_reg_hdr_set(dev_id, reg_addr, value, value_len); - } - MDIO_LOCKER_UNLOCK; - - return rv; -} - -sw_error_t -shiva_reg_field_get(a_uint32_t dev_id, a_uint32_t reg_addr, - a_uint32_t bit_offset, a_uint32_t field_len, - a_uint8_t value[], a_uint32_t value_len) -{ - a_uint32_t reg_val = 0; - - if ((bit_offset >= 32 || (field_len > 32)) || (field_len == 0)) - return SW_OUT_OF_RANGE; - - if (value_len != sizeof (a_uint32_t)) - return SW_BAD_LEN; - - SW_RTN_ON_ERROR(shiva_reg_get(dev_id, reg_addr, (a_uint8_t *) & reg_val, sizeof (a_uint32_t))); - - *((a_uint32_t *) value) = SW_REG_2_FIELD(reg_val, bit_offset, field_len); - return SW_OK; -} - -sw_error_t -shiva_reg_field_set(a_uint32_t dev_id, a_uint32_t reg_addr, - a_uint32_t bit_offset, a_uint32_t field_len, - const a_uint8_t value[], a_uint32_t value_len) -{ - a_uint32_t reg_val = 0; - a_uint32_t field_val = *((a_uint32_t *) value); - - if ((bit_offset >= 32 || (field_len > 32)) || (field_len == 0)) - return SW_OUT_OF_RANGE; - - if (value_len != sizeof (a_uint32_t)) - return SW_BAD_LEN; - - SW_RTN_ON_ERROR(shiva_reg_get(dev_id, reg_addr, (a_uint8_t *) & reg_val, sizeof (a_uint32_t))); - - SW_REG_SET_BY_FIELD_U32(reg_val, field_val, bit_offset, field_len); - - SW_RTN_ON_ERROR(shiva_reg_set(dev_id, reg_addr, (a_uint8_t *) & reg_val, sizeof (a_uint32_t))); - - return SW_OK; -} - -sw_error_t -shiva_reg_access_init(a_uint32_t dev_id, hsl_access_mode mode) -{ - hsl_api_t *p_api; - - MDIO_LOCKER_INIT; - reg_mode = mode; - - SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id)); - p_api->phy_get = shiva_phy_get; - p_api->phy_set = shiva_phy_set; - p_api->reg_get = shiva_reg_get; - p_api->reg_set = shiva_reg_set; - p_api->reg_field_get = shiva_reg_field_get; - p_api->reg_field_set = shiva_reg_field_set; - p_api->dev_access_set= shiva_access_mode_set; - - return SW_OK; -} - -sw_error_t -shiva_access_mode_set(a_uint32_t dev_id, hsl_access_mode mode) -{ - reg_mode = mode; - return SW_OK; - -} - diff --git a/feeds/ipq807x/qca-ssdk/src/src/hsl/shiva/shiva_stp.c b/feeds/ipq807x/qca-ssdk/src/src/hsl/shiva/shiva_stp.c deleted file mode 100755 index 62c588ce2..000000000 --- a/feeds/ipq807x/qca-ssdk/src/src/hsl/shiva/shiva_stp.c +++ /dev/null @@ -1,193 +0,0 @@ -/* - * Copyright (c) 2012, 2016, The Linux Foundation. All rights reserved. - * Permission to use, copy, modify, and/or distribute this software for - * any purpose with or without fee is hereby granted, provided that the - * above copyright notice and this permission notice appear in all copies. - * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES - * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR - * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES - * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN - * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT - * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. - */ - - -/** - * @defgroup shiva_stp SHIVA_STP - * @{ - */ -#include "sw.h" -#include "hsl.h" -#include "hsl_dev.h" -#include "hsl_port_prop.h" -#include "shiva_stp.h" -#include "shiva_reg.h" - -#define SHIVA_PORT_DISABLED 0 -#define SHIVA_STP_BLOCKING 1 -#define SHIVA_STP_LISTENING 2 -#define SHIVA_STP_LEARNING 3 -#define SHIVA_STP_FARWARDING 4 - -static sw_error_t -_shiva_stp_port_state_set(a_uint32_t dev_id, a_uint32_t st_id, - fal_port_t port_id, fal_stp_state_t state) -{ - sw_error_t rv; - a_uint32_t val; - - HSL_DEV_ID_CHECK(dev_id); - - if (FAL_SINGLE_STP_ID != st_id) - { - return SW_BAD_PARAM; - } - - if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_EXCL_CPU)) - { - return SW_BAD_PARAM; - } - - switch (state) - { - case FAL_STP_BLOKING: - val = SHIVA_STP_BLOCKING; - break; - case FAL_STP_LISTENING: - val = SHIVA_STP_LISTENING; - break; - case FAL_STP_LEARNING: - val = SHIVA_STP_LEARNING; - break; - case FAL_STP_FARWARDING: - val = SHIVA_STP_FARWARDING; - break; - case FAL_STP_DISABLED: - val = SHIVA_PORT_DISABLED; - break; - default: - return SW_BAD_PARAM; - } - - HSL_REG_FIELD_SET(rv, dev_id, PORT_CTL, port_id, PORT_STATE, - (a_uint8_t *) (&val), sizeof (a_uint32_t)); - return rv; -} - -static sw_error_t -_shiva_stp_port_state_get(a_uint32_t dev_id, a_uint32_t st_id, - fal_port_t port_id, fal_stp_state_t * state) -{ - sw_error_t rv; - a_uint32_t val = 0; - - HSL_DEV_ID_CHECK(dev_id); - - if (FAL_SINGLE_STP_ID != st_id) - { - return SW_BAD_PARAM; - } - - if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_EXCL_CPU)) - { - return SW_BAD_PARAM; - } - - HSL_REG_FIELD_GET(rv, dev_id, PORT_CTL, port_id, PORT_STATE, - (a_uint8_t *) (&val), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - - switch (val) - { - case SHIVA_STP_BLOCKING: - *state = FAL_STP_BLOKING; - break; - case SHIVA_STP_LISTENING: - *state = FAL_STP_LISTENING; - break; - case SHIVA_STP_LEARNING: - *state = FAL_STP_LEARNING; - break; - case SHIVA_STP_FARWARDING: - *state = FAL_STP_FARWARDING; - break; - case SHIVA_PORT_DISABLED: - *state = FAL_STP_DISABLED; - break; - default: - return SW_FAIL; - } - - return SW_OK; -} - -/** - * @brief Set port stp state on a particular spanning tree and port. - * @details Comments: - SHIVA only support single spanning tree so st_id should be - FAL_SINGLE_STP_ID that is zero. - * @param[in] dev_id device id - * @param[in] st_id spanning tree id - * @param[in] port_id port id - * @param[in] state port state for spanning tree - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -shiva_stp_port_state_set(a_uint32_t dev_id, a_uint32_t st_id, - fal_port_t port_id, fal_stp_state_t state) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _shiva_stp_port_state_set(dev_id, st_id, port_id, state); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Get port stp state on a particular spanning tree and port. - * @details Comments: - SHIVA only support single spanning tree so st_id should be - FAL_SINGLE_STP_ID that is zero. - * @param[in] dev_id device id - * @param[in] st_id spanning tree id - * @param[in] port_id port id - * @param[out] state port state for spanning tree - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -shiva_stp_port_state_get(a_uint32_t dev_id, a_uint32_t st_id, - fal_port_t port_id, fal_stp_state_t * state) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _shiva_stp_port_state_get(dev_id, st_id, port_id, state); - HSL_API_UNLOCK; - return rv; -} - -sw_error_t -shiva_stp_init(a_uint32_t dev_id) -{ - HSL_DEV_ID_CHECK(dev_id); - -#ifndef HSL_STANDALONG - { - hsl_api_t *p_api; - - SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id)); - - p_api->stp_port_state_set = shiva_stp_port_state_set; - p_api->stp_port_state_get = shiva_stp_port_state_get; - } -#endif - - return SW_OK; -} - -/** - * @} - */ - diff --git a/feeds/ipq807x/qca-ssdk/src/src/hsl/shiva/shiva_vlan.c b/feeds/ipq807x/qca-ssdk/src/src/hsl/shiva/shiva_vlan.c deleted file mode 100755 index 19dc70f9a..000000000 --- a/feeds/ipq807x/qca-ssdk/src/src/hsl/shiva/shiva_vlan.c +++ /dev/null @@ -1,524 +0,0 @@ -/* - * Copyright (c) 2012, The Linux Foundation. All rights reserved. - * Permission to use, copy, modify, and/or distribute this software for - * any purpose with or without fee is hereby granted, provided that the - * above copyright notice and this permission notice appear in all copies. - * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES - * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR - * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES - * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN - * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT - * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. - */ - - -/** - * @defgroup shiva_vlan SHIVA_VLAN - * @{ - */ -#include "sw.h" -#include "hsl.h" -#include "hsl_dev.h" -#include "hsl_port_prop.h" -#include "shiva_vlan.h" -#include "shiva_reg.h" - -#define MAX_VLAN_ID 4095 - -#define VLAN_FLUSH 1 -#define VLAN_LOAD_ENTRY 2 -#define VLAN_PURGE_ENTRY 3 -#define VLAN_REMOVE_PORT 4 -#define VLAN_NEXT_ENTRY 5 -#define VLAN_FIND_ENTRY 6 - -static void -shiva_vlan_hw_to_sw(const a_uint32_t reg[], fal_vlan_t * vlan_entry) -{ - a_uint32_t data; - - SW_GET_FIELD_BY_REG(VLAN_TABLE_FUNC0, VT_PRI_EN, data, reg[0]); - if (1 == data) - { - vlan_entry->vid_pri_en = A_TRUE; - - SW_GET_FIELD_BY_REG(VLAN_TABLE_FUNC0, VT_PRI, data, reg[0]); - vlan_entry->vid_pri = data & 0xff; - } - else - { - vlan_entry->vid_pri_en = A_FALSE; - } - - SW_GET_FIELD_BY_REG(VLAN_TABLE_FUNC0, VLAN_ID, data, reg[0]); - vlan_entry->vid = data & 0xffff; - - SW_GET_FIELD_BY_REG(VLAN_TABLE_FUNC1, VID_MEM, data, reg[1]); - vlan_entry->mem_ports = data; - - return; -} - -static sw_error_t -shiva_vlan_sw_to_hw(const fal_vlan_t * vlan_entry, a_uint32_t reg[]) -{ - if (A_TRUE == vlan_entry->vid_pri_en) - { - SW_SET_REG_BY_FIELD(VLAN_TABLE_FUNC0, VT_PRI_EN, 1, reg[0]); - SW_SET_REG_BY_FIELD(VLAN_TABLE_FUNC0, VT_PRI, vlan_entry->vid_pri, reg[0]); - } - else - { - SW_SET_REG_BY_FIELD(VLAN_TABLE_FUNC0, VT_PRI_EN, 0, reg[0]); - } - - SW_SET_REG_BY_FIELD(VLAN_TABLE_FUNC0, VLAN_ID, vlan_entry->vid, reg[0]); - - SW_SET_REG_BY_FIELD(VLAN_TABLE_FUNC1, VT_VALID, 1, reg[1]); - SW_SET_REG_BY_FIELD(VLAN_TABLE_FUNC1, VID_MEM, vlan_entry->mem_ports, reg[1]); - - if (0 != vlan_entry->u_ports) - { - return SW_BAD_VALUE; - } - - return SW_OK; -} - -static sw_error_t -shiva_vlan_commit(a_uint32_t dev_id, a_uint32_t op) -{ - a_uint32_t vt_busy = 1, i = 0x1000, vt_full, val; - sw_error_t rv; - - while (vt_busy && --i) - { - HSL_REG_FIELD_GET(rv, dev_id, VLAN_TABLE_FUNC0, 0, VT_BUSY, - (a_uint8_t *) (&vt_busy), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - aos_udelay(5); - } - - if (i == 0) - return SW_BUSY; - - HSL_REG_ENTRY_GET(rv, dev_id, VLAN_TABLE_FUNC0, 0, - (a_uint8_t *) (&val), sizeof (a_uint32_t)); - SW_SET_REG_BY_FIELD(VLAN_TABLE_FUNC0, VT_FUNC, op, val); - SW_SET_REG_BY_FIELD(VLAN_TABLE_FUNC0, VT_BUSY, 1, val); - - HSL_REG_ENTRY_SET(rv, dev_id, VLAN_TABLE_FUNC0, 0, - (a_uint8_t *) (&val), sizeof (a_uint32_t)); - - SW_RTN_ON_ERROR(rv); - - vt_busy = 1; - i = 0x1000; - while (vt_busy && --i) - { - HSL_REG_FIELD_GET(rv, dev_id, VLAN_TABLE_FUNC0, 0, VT_BUSY, - (a_uint8_t *) (&vt_busy), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - aos_udelay(5); - } - - if (i == 0) - return SW_FAIL; - - HSL_REG_FIELD_GET(rv, dev_id, VLAN_TABLE_FUNC0, 0, VT_FULL_VIO, - (a_uint8_t *) (&vt_full), sizeof (a_uint32_t)); - - SW_RTN_ON_ERROR(rv); - - if (vt_full) - { - val = 0x10; - HSL_REG_ENTRY_SET(rv, dev_id, VLAN_TABLE_FUNC0, 0, - (a_uint8_t *) (&val), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - if (VLAN_LOAD_ENTRY == op) - { - return SW_OK; - } - else if (VLAN_PURGE_ENTRY == op) - { - return SW_NOT_FOUND; - } - } - - HSL_REG_FIELD_GET(rv, dev_id, VLAN_TABLE_FUNC1, 0, VT_VALID, - (a_uint8_t *) (&val), sizeof (a_uint32_t)); - - SW_RTN_ON_ERROR(rv); - - if (!val) - { - if (VLAN_FIND_ENTRY == op) - return SW_NOT_FOUND; - - if (VLAN_NEXT_ENTRY == op) - return SW_NO_MORE; - } - - return SW_OK; -} - -static sw_error_t -_shiva_vlan_entry_append(a_uint32_t dev_id, const fal_vlan_t * vlan_entry) -{ - sw_error_t rv; - a_uint32_t reg[2] = { 0 }; - - HSL_DEV_ID_CHECK(dev_id); - - if ((vlan_entry->vid == 0) || (vlan_entry->vid > MAX_VLAN_ID)) - return SW_OUT_OF_RANGE; - - if (A_FALSE == hsl_mports_prop_check(dev_id, vlan_entry->mem_ports, HSL_PP_INCL_CPU)) - return SW_BAD_PARAM; - - rv = shiva_vlan_sw_to_hw(vlan_entry, reg); - SW_RTN_ON_ERROR(rv); - - HSL_REG_ENTRY_SET(rv, dev_id, VLAN_TABLE_FUNC0, 0, - (a_uint8_t *) (®[0]), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - - HSL_REG_ENTRY_SET(rv, dev_id, VLAN_TABLE_FUNC1, 0, - (a_uint8_t *) (®[1]), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - - rv = shiva_vlan_commit(dev_id, VLAN_LOAD_ENTRY); - return rv; -} - -static sw_error_t -_shiva_vlan_create(a_uint32_t dev_id, a_uint32_t vlan_id) -{ - sw_error_t rv; - a_uint32_t entry = 0; - - HSL_DEV_ID_CHECK(dev_id); - - if ((vlan_id == 0) || (vlan_id > MAX_VLAN_ID)) - return SW_OUT_OF_RANGE; - - /* set default value for VLAN_TABLE_FUNC0, all 0 except vid */ - entry = 0; - SW_SET_REG_BY_FIELD(VLAN_TABLE_FUNC0, VLAN_ID, vlan_id, entry); - HSL_REG_ENTRY_SET(rv, dev_id, VLAN_TABLE_FUNC0, 0, - (a_uint8_t *) (&entry), sizeof (a_uint32_t)); - - SW_RTN_ON_ERROR(rv); - - /* set default value for VLAN_TABLE_FUNC1, all 0 */ - entry = 0; - SW_SET_REG_BY_FIELD(VLAN_TABLE_FUNC1, VT_VALID, 1, entry); - HSL_REG_ENTRY_SET(rv, dev_id, VLAN_TABLE_FUNC1, 0, - (a_uint8_t *) (&entry), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - - rv = shiva_vlan_commit(dev_id, VLAN_LOAD_ENTRY); - return rv; -} - -static sw_error_t -_shiva_vlan_next(a_uint32_t dev_id, a_uint32_t vlan_id, fal_vlan_t * p_vlan) -{ - sw_error_t rv; - a_uint32_t reg[2] = { 0 }; - - HSL_DEV_ID_CHECK(dev_id); - - if (vlan_id > MAX_VLAN_ID) - return SW_OUT_OF_RANGE; - - aos_mem_zero(p_vlan, sizeof (fal_vlan_t)); - - SW_SET_REG_BY_FIELD(VLAN_TABLE_FUNC0, VLAN_ID, vlan_id, reg[0]); - HSL_REG_ENTRY_SET(rv, dev_id, VLAN_TABLE_FUNC0, 0, - (a_uint8_t *) (®[0]), sizeof (a_uint32_t)); - - SW_RTN_ON_ERROR(rv); - - rv = shiva_vlan_commit(dev_id, VLAN_NEXT_ENTRY); - SW_RTN_ON_ERROR(rv); - - HSL_REG_ENTRY_GET(rv, dev_id, VLAN_TABLE_FUNC0, 0, - (a_uint8_t *) (®[0]), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - - HSL_REG_ENTRY_GET(rv, dev_id, VLAN_TABLE_FUNC1, 0, - (a_uint8_t *) (®[1]), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - - shiva_vlan_hw_to_sw(reg, p_vlan); - - if (0 == p_vlan->vid) - return SW_NO_MORE; - else - return SW_OK; -} - -static sw_error_t -_shiva_vlan_find(a_uint32_t dev_id, a_uint32_t vlan_id, fal_vlan_t * p_vlan) -{ - sw_error_t rv; - a_uint32_t reg[2] = { 0 }; - - HSL_DEV_ID_CHECK(dev_id); - - if ((vlan_id == 0) || (vlan_id > MAX_VLAN_ID)) - return SW_OUT_OF_RANGE; - - aos_mem_zero(p_vlan, sizeof (fal_vlan_t)); - - SW_SET_REG_BY_FIELD(VLAN_TABLE_FUNC0, VLAN_ID, vlan_id, reg[0]); - HSL_REG_ENTRY_SET(rv, dev_id, VLAN_TABLE_FUNC0, 0, - (a_uint8_t *) (®[0]), sizeof (a_uint32_t)); - - SW_RTN_ON_ERROR(rv); - - rv = shiva_vlan_commit(dev_id, VLAN_FIND_ENTRY); - SW_RTN_ON_ERROR(rv); - - HSL_REG_ENTRY_GET(rv, dev_id, VLAN_TABLE_FUNC0, 0, - (a_uint8_t *) (®[0]), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - - HSL_REG_ENTRY_GET(rv, dev_id, VLAN_TABLE_FUNC1, 0, - (a_uint8_t *) (®[1]), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - - shiva_vlan_hw_to_sw(reg, p_vlan); - - return SW_OK; -} - -static sw_error_t -_shiva_vlan_member_update(a_uint32_t dev_id, a_uint32_t vlan_id, - fal_pbmp_t member, fal_pbmp_t u_member) -{ - sw_error_t rv; - a_uint32_t reg = 0; - - HSL_DEV_ID_CHECK(dev_id); - - if ((vlan_id == 0) || (vlan_id > MAX_VLAN_ID)) - return SW_OUT_OF_RANGE; - - if (A_FALSE == hsl_mports_prop_check(dev_id, member, HSL_PP_INCL_CPU)) - return SW_BAD_PARAM; - - if (u_member != 0) - return SW_BAD_PARAM; - - /* get vlan entry first */ - SW_SET_REG_BY_FIELD(VLAN_TABLE_FUNC0, VLAN_ID, vlan_id, reg); - HSL_REG_ENTRY_SET(rv, dev_id, VLAN_TABLE_FUNC0, 0, - (a_uint8_t *) (®), sizeof (a_uint32_t)); - - SW_RTN_ON_ERROR(rv); - - rv = shiva_vlan_commit(dev_id, VLAN_FIND_ENTRY); - SW_RTN_ON_ERROR(rv); - - /* set vlan member for VLAN_TABLE_FUNC1 */ - HSL_REG_FIELD_SET(rv, dev_id, VLAN_TABLE_FUNC1, 0, VID_MEM, - (a_uint8_t *) (&member), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - - rv = shiva_vlan_commit(dev_id, VLAN_LOAD_ENTRY); - /* when update port member through LOAD opration, hardware will - return VT_FULL_VIO, we should ignore it */ - if (SW_FULL == rv) - rv = SW_OK; - - return rv; -} - -static sw_error_t -_shiva_vlan_delete(a_uint32_t dev_id, a_uint32_t vlan_id) -{ - sw_error_t rv; - a_uint32_t reg; - - HSL_DEV_ID_CHECK(dev_id); - - if ((vlan_id == 0) || (vlan_id > MAX_VLAN_ID)) - return SW_OUT_OF_RANGE; - - reg = (a_int32_t) vlan_id; - HSL_REG_FIELD_SET(rv, dev_id, VLAN_TABLE_FUNC0, 0, VLAN_ID, - (a_uint8_t *) (®), sizeof (a_uint32_t)); - SW_RTN_ON_ERROR(rv); - - rv = shiva_vlan_commit(dev_id, VLAN_PURGE_ENTRY); - return rv; -} - -static sw_error_t -_shiva_vlan_flush(a_uint32_t dev_id) -{ - sw_error_t rv; - - HSL_DEV_ID_CHECK(dev_id); - rv = shiva_vlan_commit(dev_id, VLAN_FLUSH); - return rv; -} - -/** - * @brief Append a vlan entry on paticular device. - * @param[in] dev_id device id - * @param[in] vlan_entry vlan entry - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -shiva_vlan_entry_append(a_uint32_t dev_id, const fal_vlan_t * vlan_entry) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _shiva_vlan_entry_append(dev_id, vlan_entry); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Creat a vlan entry through vlan id on a paticular device. - * @details Comments: - * After this operation the member ports of the created vlan entry are null. - * @param[in] dev_id device id - * @param[in] vlan_id vlan id - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -shiva_vlan_create(a_uint32_t dev_id, a_uint32_t vlan_id) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _shiva_vlan_create(dev_id, vlan_id); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Next a vlan entry through vlan id on a paticular device. - * @details Comments: - * If the value of vid is zero this operation will get the first entry. - * @param[in] dev_id device id - * @param[in] vlan_id vlan id - * @param[out] p_vlan vlan entry - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -shiva_vlan_next(a_uint32_t dev_id, a_uint32_t vlan_id, fal_vlan_t * p_vlan) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _shiva_vlan_next(dev_id, vlan_id, p_vlan); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Find a vlan entry through vlan id on paticular device. - * @param[in] dev_id device id - * @param[in] vlan_id vlan id - * @param[out] p_vlan vlan entry - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -shiva_vlan_find(a_uint32_t dev_id, a_uint32_t vlan_id, fal_vlan_t * p_vlan) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _shiva_vlan_find(dev_id, vlan_id, p_vlan); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Update a vlan entry member port through vlan id on a paticular device. - * @param[in] dev_id device id - * @param[in] vlan_id vlan id - * @param[in] member member ports - * @param[in] u_member tagged or untagged infomation for member ports - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -shiva_vlan_member_update(a_uint32_t dev_id, a_uint32_t vlan_id, - fal_pbmp_t member, fal_pbmp_t u_member) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _shiva_vlan_member_update(dev_id, vlan_id, member, u_member); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Delete a vlan entry through vlan id on a paticular device. - * @param[in] dev_id device id - * @param[in] vlan_id vlan id - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -shiva_vlan_delete(a_uint32_t dev_id, a_uint32_t vlan_id) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _shiva_vlan_delete(dev_id, vlan_id); - HSL_API_UNLOCK; - return rv; -} - -/** - * @brief Flush all vlan entries on a paticular device. - * @param[in] dev_id device id - * @return SW_OK or error code - */ -HSL_LOCAL sw_error_t -shiva_vlan_flush(a_uint32_t dev_id) -{ - sw_error_t rv; - - HSL_API_LOCK; - rv = _shiva_vlan_flush(dev_id); - HSL_API_UNLOCK; - return rv; -} - -sw_error_t -shiva_vlan_init(a_uint32_t dev_id) -{ - hsl_api_t *p_api; - HSL_DEV_ID_CHECK(dev_id); - -#ifndef HSL_STANDALONG - - SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id)); - - p_api->vlan_entry_append = shiva_vlan_entry_append; - p_api->vlan_creat = shiva_vlan_create; - p_api->vlan_member_update = shiva_vlan_member_update; - p_api->vlan_delete = shiva_vlan_delete; - p_api->vlan_next = shiva_vlan_next; - p_api->vlan_find = shiva_vlan_find; - p_api->vlan_flush = shiva_vlan_flush; - -#endif - - return SW_OK; -} - -/** - * @} - */ - diff --git a/feeds/ipq807x/qca-ssdk/src/src/init/Makefile b/feeds/ipq807x/qca-ssdk/src/src/init/Makefile deleted file mode 100644 index e54dd0654..000000000 --- a/feeds/ipq807x/qca-ssdk/src/src/init/Makefile +++ /dev/null @@ -1,40 +0,0 @@ -LOC_DIR=src/init -LIB=INIT - -include $(PRJ_PATH)/make/config.mk - -SRC_LIST=ssdk_init.c ssdk_plat.c ssdk_interrupt.c ssdk_dts.c - -ifneq (ISISC, $(CHIP_TYPE)) - SRC_LIST += ssdk_clk.c -endif - -ifeq (TRUE, $(IN_LED)) - SRC_LIST += ssdk_led.c -endif - -ifeq (TRUE, $(IN_PHY_I2C_MODE)) - SRC_LIST += ssdk_phy_i2c.c -endif - -ifneq (,$(findstring HPPE, $(SUPPORT_CHIP))) - SRC_LIST += ssdk_hppe.c -endif - -ifneq (,$(findstring SCOMPHY, $(SUPPORT_CHIP))) - SRC_LIST += ssdk_scomphy.c -endif - -ifneq (,$(filter MP, $(SUPPORT_CHIP))) - SRC_LIST += ssdk_mp.c -endif - -ifeq (TRUE, $(SWCONFIG)) - SRC_LIST += ssdk_uci.c -endif - -include $(PRJ_PATH)/make/components.mk -include $(PRJ_PATH)/make/defs.mk -include $(PRJ_PATH)/make/target.mk - -all: dep obj diff --git a/feeds/ipq807x/qca-ssdk/src/src/init/ssdk_clk.c b/feeds/ipq807x/qca-ssdk/src/src/init/ssdk_clk.c deleted file mode 100755 index a3b39c403..000000000 --- a/feeds/ipq807x/qca-ssdk/src/src/init/ssdk_clk.c +++ /dev/null @@ -1,1305 +0,0 @@ -/* - * Copyright (c) 2017-2020, The Linux Foundation. All rights reserved. - * Permission to use, copy, modify, and/or distribute this software for - * any purpose with or without fee is hereby granted, provided that the - * above copyright notice and this permission notice appear in all copies. - * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES - * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR - * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES - * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN - * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT - * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. - */ -#include "sw.h" -#include "ssdk_init.h" -#include "ssdk_plat.h" -#include "ssdk_clk.h" -#include "ssdk_dts.h" -#if defined(HPPE) -#include "adpt_hppe.h" -#endif -#include "fal.h" -#include -#include -#include -#include -#if defined(CONFIG_OF) && (LINUX_VERSION_CODE >= KERNEL_VERSION(4,4,0)) -#include -#include -#include -#include -#include -#endif - -#if defined(CONFIG_OF) && (LINUX_VERSION_CODE >= KERNEL_VERSION(4,4,0)) -struct device_node *clock_node = NULL; -static struct clk *uniphy_port_clks[UNIPHYT_CLK_MAX] = {0}; - -struct device_node *rst_node = NULL; -struct reset_control *uniphy_rsts[UNIPHY_RST_MAX] = {0}; -struct reset_control *port_rsts[SSDK_MAX_PORT_NUM] = {0}; - -/* below 3 routines to be used as common */ -void ssdk_clock_rate_set_and_enable( - struct device_node *node, a_uint8_t* clock_id, a_uint32_t rate) -{ - struct clk *clk; - - if(ssdk_is_emulation(0)){ - SSDK_INFO("clock_id %s rate %d on emulation platform\n",clock_id, rate); - return; - } - - clk = of_clk_get_by_name(node, clock_id); - if (!IS_ERR(clk)) { - if (rate) - clk_set_rate(clk, rate); - - clk_prepare_enable(clk); - } -} - -void ssdk_gcc_reset(struct reset_control *rst, a_uint32_t action) -{ - if(ssdk_is_emulation(0)){ - SSDK_INFO("action %d on emulation platform\n",action); - return; - } - - if (action == SSDK_RESET_ASSERT) - reset_control_assert(rst); - else - reset_control_deassert(rst); - -} -#endif - -void ssdk_uniphy_reset( - a_uint32_t dev_id, - enum unphy_rst_type rst_type, - a_uint32_t action) -{ -#if defined(CONFIG_OF) && (LINUX_VERSION_CODE >= KERNEL_VERSION(4,4,0)) - struct reset_control *rst; - - rst = uniphy_rsts[rst_type]; - if (IS_ERR(rst)) { - SSDK_ERROR("reset(%d) nof exist!\n", rst_type); - return; - } - - ssdk_gcc_reset(rst, action); -#endif - -} - -void ssdk_port_reset( - a_uint32_t dev_id, - a_uint32_t port_id, - a_uint32_t action) -{ -#if defined(CONFIG_OF) && (LINUX_VERSION_CODE >= KERNEL_VERSION(4,4,0)) - struct reset_control *rst; - - if ((port_id < SSDK_PHYSICAL_PORT1) || (port_id > SSDK_PHYSICAL_PORT6)) - return; - - rst = port_rsts[port_id-1]; - if (IS_ERR(rst)) { - SSDK_ERROR("reset(%d) not exist!\n", port_id); - return; - } - - ssdk_gcc_reset(rst, action); -#endif - -} - -void ssdk_uniphy_clock_rate_set( - a_uint32_t dev_id, - enum unphy_clk_type clock_type, - a_uint32_t rate) -{ -#if defined(CONFIG_OF) && (LINUX_VERSION_CODE >= KERNEL_VERSION(4,4,0)) - struct clk *uniphy_clk; - - if(ssdk_is_emulation(dev_id)){ - SSDK_INFO("clock_type %d rate %d on emulation platform\n", - clock_type, rate); - return; - } - - uniphy_clk = uniphy_port_clks[clock_type]; - if (!IS_ERR(uniphy_clk)) { - if (rate) - if (clk_set_rate(uniphy_clk, rate)) - SSDK_INFO("%d set rate=%d fail\n", clock_type, rate); - } else - SSDK_INFO("%d set rate %x fail!\n", clock_type, rate); -#endif - -} - -void ssdk_uniphy_clock_enable( - a_uint32_t dev_id, - enum unphy_clk_type clock_type, - a_bool_t enable) -{ -#if defined(CONFIG_OF) && (LINUX_VERSION_CODE >= KERNEL_VERSION(4,4,0)) - struct clk *uniphy_clk; - - if(ssdk_is_emulation(dev_id)){ - SSDK_INFO("clock_type %d enable %d on emulation platform\n", - clock_type, enable); - return; - } - - uniphy_clk = uniphy_port_clks[clock_type]; - if (!IS_ERR(uniphy_clk)) { - if (enable) { - if (clk_prepare_enable(uniphy_clk)) - SSDK_ERROR("clock enable fail!\n"); - } else - clk_disable_unprepare(uniphy_clk); - } else { - SSDK_DEBUG("clock_type= %d enable=%d not find\n", - clock_type, enable); - } -#endif - -} - -#if defined(CONFIG_OF) && (LINUX_VERSION_CODE >= KERNEL_VERSION(4,4,0)) -#if defined(HPPE) || defined(MP) -struct clk_uniphy { - struct clk_hw hw; - u8 uniphy_index; - u8 dir; - unsigned long rate; -}; - -#define to_clk_uniphy(_hw) container_of(_hw, struct clk_uniphy, hw) - -static unsigned long -uniphy_clks_recalc_rate(struct clk_hw *hw, unsigned long parent_rate) -{ - struct clk_uniphy *uniphy = to_clk_uniphy(hw); - - return uniphy->rate; -} - -static int -uniphy_clks_determine_rate(struct clk_hw *hw, struct clk_rate_request *req) -{ - /* add logic for checking the current mode */ - if (req->rate <= UNIPHY_CLK_RATE_125M) - req->rate = UNIPHY_CLK_RATE_125M; - else - req->rate = UNIPHY_CLK_RATE_312M; - - return 0; -} - -static int -uniphy_clks_set_rate(struct clk_hw *hw, unsigned long rate, - unsigned long parent_rate) -{ - struct clk_uniphy *uniphy = to_clk_uniphy(hw); - - if (rate != UNIPHY_CLK_RATE_125M && rate != UNIPHY_CLK_RATE_312M) - return -1; - - uniphy->rate = rate; - - return 0; -} - -static const struct clk_ops clk_uniphy_ops = { - .recalc_rate = uniphy_clks_recalc_rate, - .determine_rate = uniphy_clks_determine_rate, - .set_rate = uniphy_clks_set_rate, -}; -#endif - -#if defined(HPPE) - -static struct clk_uniphy uniphy0_gcc_rx_clk = { - .hw.init = &(struct clk_init_data){ - .name = "uniphy0_gcc_rx_clk", - .ops = &clk_uniphy_ops, -#if (LINUX_VERSION_CODE < KERNEL_VERSION(4,9,0)) - .flags = CLK_IS_ROOT, -#endif - }, - .uniphy_index = 0, - .dir = UNIPHY_RX, - .rate = UNIPHY_DEFAULT_RATE, -}; - -static struct clk_uniphy uniphy0_gcc_tx_clk = { - .hw.init = &(struct clk_init_data){ - .name = "uniphy0_gcc_tx_clk", - .ops = &clk_uniphy_ops, -#if (LINUX_VERSION_CODE < KERNEL_VERSION(4,9,0)) - .flags = CLK_IS_ROOT, -#endif - }, - .uniphy_index = 0, - .dir = UNIPHY_TX, - .rate = UNIPHY_DEFAULT_RATE, -}; - -static struct clk_uniphy uniphy1_gcc_rx_clk = { - .hw.init = &(struct clk_init_data){ - .name = "uniphy1_gcc_rx_clk", - .ops = &clk_uniphy_ops, -#if (LINUX_VERSION_CODE < KERNEL_VERSION(4,9,0)) - .flags = CLK_IS_ROOT, -#endif - }, - .uniphy_index = 1, - .dir = UNIPHY_RX, - .rate = UNIPHY_DEFAULT_RATE, -}; - -static struct clk_uniphy uniphy1_gcc_tx_clk = { - .hw.init = &(struct clk_init_data){ - .name = "uniphy1_gcc_tx_clk", - .ops = &clk_uniphy_ops, -#if (LINUX_VERSION_CODE < KERNEL_VERSION(4,9,0)) - .flags = CLK_IS_ROOT, -#endif - }, - .uniphy_index = 1, - .dir = UNIPHY_TX, - .rate = UNIPHY_DEFAULT_RATE, -}; - -static struct clk_uniphy uniphy2_gcc_rx_clk = { - .hw.init = &(struct clk_init_data){ - .name = "uniphy2_gcc_rx_clk", - .ops = &clk_uniphy_ops, -#if (LINUX_VERSION_CODE < KERNEL_VERSION(4,9,0)) - .flags = CLK_IS_ROOT, -#endif - }, - .uniphy_index = 2, - .dir = UNIPHY_RX, - .rate = UNIPHY_DEFAULT_RATE, -}; - -static struct clk_uniphy uniphy2_gcc_tx_clk = { - .hw.init = &(struct clk_init_data){ - .name = "uniphy2_gcc_tx_clk", - .ops = &clk_uniphy_ops, -#if (LINUX_VERSION_CODE < KERNEL_VERSION(4,9,0)) - .flags = CLK_IS_ROOT, -#endif - }, - .uniphy_index = 2, - .dir = UNIPHY_TX, - .rate = UNIPHY_DEFAULT_RATE, -}; - -static struct clk_hw *uniphy_raw_clks[SSDK_MAX_UNIPHY_INSTANCE * 2] = { - &uniphy0_gcc_rx_clk.hw, &uniphy0_gcc_tx_clk.hw, - &uniphy1_gcc_rx_clk.hw, &uniphy1_gcc_tx_clk.hw, - &uniphy2_gcc_rx_clk.hw, &uniphy2_gcc_tx_clk.hw, -}; - -static char *ppe_clk_ids[UNIPHYT_CLK_MAX] = { - NSS_PORT1_RX_CLK, - NSS_PORT1_TX_CLK, - NSS_PORT2_RX_CLK, - NSS_PORT2_TX_CLK, - NSS_PORT3_RX_CLK, - NSS_PORT3_TX_CLK, - NSS_PORT4_RX_CLK, - NSS_PORT4_TX_CLK, - NSS_PORT5_RX_CLK, - NSS_PORT5_TX_CLK, - NSS_PORT6_RX_CLK, - NSS_PORT6_TX_CLK, - UNIPHY0_PORT1_RX_CLK, - UNIPHY0_PORT1_TX_CLK, - UNIPHY0_PORT2_RX_CLK, - UNIPHY0_PORT2_TX_CLK, - UNIPHY0_PORT3_RX_CLK, - UNIPHY0_PORT3_TX_CLK, - UNIPHY0_PORT4_RX_CLK, - UNIPHY0_PORT4_TX_CLK, - UNIPHY0_PORT5_RX_CLK, - UNIPHY0_PORT5_TX_CLK, - UNIPHY1_PORT5_RX_CLK, - UNIPHY1_PORT5_TX_CLK, - UNIPHY2_PORT6_RX_CLK, - UNIPHY2_PORT6_TX_CLK, - PORT5_RX_SRC, - PORT5_TX_SRC -}; - -static void ssdk_ppe_uniphy_clock_init(a_uint32_t revision) -{ - a_uint32_t i, inst_num; - struct clk *clk; - - if (revision == HPPE_REVISION) { - inst_num = SSDK_MAX_UNIPHY_INSTANCE; - } else { - inst_num = SSDK_MAX_UNIPHY_INSTANCE - 1; - } - - for (i = 0; i < inst_num * 2; i++) { - clk = clk_register(NULL, uniphy_raw_clks[i]); - if (IS_ERR(clk)) - SSDK_ERROR("Clk register %d fail!\n", i); - } - - for (i = NSS_PORT1_RX_CLK_E; i < UNIPHYT_CLK_MAX; i++) - uniphy_port_clks[i] = of_clk_get_by_name(clock_node, - ppe_clk_ids[i]); - - /* enable uniphy and mac clock */ - for (i = NSS_PORT1_RX_CLK_E; i < PORT5_RX_SRC_E; i++) - ssdk_uniphy_clock_enable(0, i, A_TRUE); -} - -static void ssdk_ppe_fixed_clock_init(a_uint32_t revision) -{ - /* AHB and sys clk */ - ssdk_clock_rate_set_and_enable(clock_node, CMN_AHB_CLK, 0); - ssdk_clock_rate_set_and_enable(clock_node, CMN_SYS_CLK, 0); - ssdk_clock_rate_set_and_enable(clock_node, UNIPHY0_AHB_CLK, - UNIPHY_AHB_CLK_RATE); - if (revision == HPPE_REVISION) { - ssdk_clock_rate_set_and_enable(clock_node, - UNIPHY0_SYS_CLK, - UNIPHY_SYS_CLK_RATE); - } else { - ssdk_clock_rate_set_and_enable(clock_node, - UNIPHY0_SYS_CLK, - CPPE_UNIPHY_SYS_CLK_RATE); - } - ssdk_clock_rate_set_and_enable(clock_node, UNIPHY1_AHB_CLK, - UNIPHY_AHB_CLK_RATE); - if (revision == HPPE_REVISION) { - ssdk_clock_rate_set_and_enable(clock_node, - UNIPHY1_SYS_CLK, - UNIPHY_SYS_CLK_RATE); - } else { - ssdk_clock_rate_set_and_enable(clock_node, - UNIPHY1_SYS_CLK, - CPPE_UNIPHY_SYS_CLK_RATE); - } - if (revision == HPPE_REVISION) { - ssdk_clock_rate_set_and_enable(clock_node, - UNIPHY2_AHB_CLK, - UNIPHY_AHB_CLK_RATE); - ssdk_clock_rate_set_and_enable(clock_node, - UNIPHY2_SYS_CLK, - UNIPHY_SYS_CLK_RATE); - } - - /* ppe related fixed clock init */ - ssdk_clock_rate_set_and_enable(clock_node, - PORT1_MAC_CLK, PPE_CLK_RATE); - ssdk_clock_rate_set_and_enable(clock_node, - PORT2_MAC_CLK, PPE_CLK_RATE); - ssdk_clock_rate_set_and_enable(clock_node, - PORT3_MAC_CLK, PPE_CLK_RATE); - ssdk_clock_rate_set_and_enable(clock_node, - PORT4_MAC_CLK, PPE_CLK_RATE); - ssdk_clock_rate_set_and_enable(clock_node, - PORT5_MAC_CLK, PPE_CLK_RATE); - if (revision == HPPE_REVISION) { - ssdk_clock_rate_set_and_enable(clock_node, - PORT6_MAC_CLK, PPE_CLK_RATE); - } - ssdk_clock_rate_set_and_enable(clock_node, - NSS_PPE_CLK, PPE_CLK_RATE); - ssdk_clock_rate_set_and_enable(clock_node, - NSS_PPE_CFG_CLK, PPE_CLK_RATE); - ssdk_clock_rate_set_and_enable(clock_node, - NSSNOC_PPE_CLK, PPE_CLK_RATE); - ssdk_clock_rate_set_and_enable(clock_node, - NSSNOC_PPE_CFG_CLK, PPE_CLK_RATE); - ssdk_clock_rate_set_and_enable(clock_node, - NSS_EDMA_CLK, PPE_CLK_RATE); - ssdk_clock_rate_set_and_enable(clock_node, - NSS_EDMA_CFG_CLK, PPE_CLK_RATE); - ssdk_clock_rate_set_and_enable(clock_node, - NSS_PPE_IPE_CLK, PPE_CLK_RATE); - if (revision == HPPE_REVISION) { - ssdk_clock_rate_set_and_enable(clock_node, - NSS_PPE_BTQ_CLK, PPE_CLK_RATE); - } - ssdk_clock_rate_set_and_enable(clock_node, - MDIO_AHB_CLK, MDIO_AHB_RATE); - if (revision == HPPE_REVISION) { - ssdk_clock_rate_set_and_enable(clock_node, - NSSNOC_CLK, NSS_NOC_RATE); - } else { - ssdk_clock_rate_set_and_enable(clock_node, - NSSNOC_CLK, NSSNOC_SNOC_RATE); - } - ssdk_clock_rate_set_and_enable(clock_node, - NSSNOC_SNOC_CLK, NSSNOC_SNOC_RATE); - if (revision == HPPE_REVISION) { - ssdk_clock_rate_set_and_enable(clock_node, - MEM_NOC_NSSAXI_CLK, NSS_AXI_RATE); - } - ssdk_clock_rate_set_and_enable(clock_node, - CRYPTO_PPE_CLK, PPE_CLK_RATE); - if (revision == HPPE_REVISION) { - ssdk_clock_rate_set_and_enable(clock_node, - NSS_IMEM_CLK, NSS_IMEM_RATE); - } - ssdk_clock_rate_set_and_enable(clock_node, - NSS_PTP_REF_CLK, PTP_REF_RARE); - if (revision == CPPE_REVISION) { - ssdk_clock_rate_set_and_enable(clock_node, - SNOC_NSSNOC_CLK, NSSNOC_SNOC_RATE); - } -} -#endif - -#if defined(MP) -#define TCSR_ETH_ADDR 0x19475C0 -#define TCSR_ETH_SIZE 0x4 -#define TCSR_GEPHY_LDO_BIAS_EN 0 -#define TCSR_ETH_LDO_RDY 0x4 - -#define GEPHY_LDO_BIAS_EN 0x1 -#define ETH_LDO_RDY 0x1 -#define CMN_PLL_LOCKED_ADDR 0x9B064 -#define CMN_PLL_LOCKED_SIZE 0x4 -#define CMN_PLL_LOCKED 0x4 -#define MP_RAW_CLOCK_INSTANCE 0x2 - -static char *mp_rst_ids[MP_BCR_RST_MAX] = { - GEHPY_BCR_RESET_ID, - UNIPHY_BCR_RESET_ID, - GMAC0_BCR_RESET_ID, - GMAC1_BCR_RESET_ID, - GEPHY_MISC_RESET_ID -}; - -static struct clk_uniphy gephy_gcc_rx_clk = { - .hw.init = &(struct clk_init_data){ - .name = "gephy_gcc_rx", - .ops = &clk_uniphy_ops, -#if (LINUX_VERSION_CODE < KERNEL_VERSION(4,9,0)) - .flags = CLK_IS_ROOT, -#endif - }, - .uniphy_index = 0, - .dir = UNIPHY_RX, - .rate = UNIPHY_DEFAULT_RATE, -}; - -static struct clk_uniphy gephy_gcc_tx_clk = { - .hw.init = &(struct clk_init_data){ - .name = "gephy_gcc_tx", - .ops = &clk_uniphy_ops, -#if (LINUX_VERSION_CODE < KERNEL_VERSION(4,9,0)) - .flags = CLK_IS_ROOT, -#endif - }, - .uniphy_index = 0, - .dir = UNIPHY_TX, - .rate = UNIPHY_DEFAULT_RATE, -}; - -static struct clk_uniphy uniphy_gcc_rx_clk = { - .hw.init = &(struct clk_init_data){ - .name = "uniphy_gcc_rx", - .ops = &clk_uniphy_ops, -#if (LINUX_VERSION_CODE < KERNEL_VERSION(4,9,0)) - .flags = CLK_IS_ROOT, -#endif - }, - .uniphy_index = 1, - .dir = UNIPHY_RX, - .rate = UNIPHY_DEFAULT_RATE, -}; - -static struct clk_uniphy uniphy_gcc_tx_clk = { - .hw.init = &(struct clk_init_data){ - .name = "uniphy_gcc_tx", - .ops = &clk_uniphy_ops, -#if (LINUX_VERSION_CODE < KERNEL_VERSION(4,9,0)) - .flags = CLK_IS_ROOT, -#endif - }, - .uniphy_index = 1, - .dir = UNIPHY_TX, - .rate = UNIPHY_DEFAULT_RATE, -}; - -static struct clk_hw *mp_raw_clks[MP_RAW_CLOCK_INSTANCE * 2] = { - &gephy_gcc_rx_clk.hw, &gephy_gcc_tx_clk.hw, - &uniphy_gcc_rx_clk.hw, &uniphy_gcc_tx_clk.hw, -}; - -static void ssdk_mp_fixed_clock_init(void) -{ - ssdk_clock_rate_set_and_enable(clock_node, CMN_AHB_CLK, 0); - ssdk_clock_rate_set_and_enable(clock_node, CMN_SYS_CLK, 0); - ssdk_clock_rate_set_and_enable(clock_node, UNIPHY_AHB_CLK, - UNIPHY_AHB_CLK_RATE); - ssdk_clock_rate_set_and_enable(clock_node, - UNIPHY_SYS_CLK, - MP_UNIPHY_SYS_CLK_RATE); - ssdk_clock_rate_set_and_enable(clock_node, - MDIO0_AHB_CLK, MDIO_AHB_RATE); - ssdk_clock_rate_set_and_enable(clock_node, - MDIO1_AHB_CLK, MDIO_AHB_RATE); - ssdk_clock_rate_set_and_enable(clock_node, - GMAC0_CFG_CLK, GMAC_CLK_RATE); - ssdk_clock_rate_set_and_enable(clock_node, - GMAC0_SYS_CLK, GMAC_CLK_RATE); - ssdk_clock_rate_set_and_enable(clock_node, - GMAC1_CFG_CLK, GMAC_CLK_RATE); - ssdk_clock_rate_set_and_enable(clock_node, - GMAC1_SYS_CLK, GMAC_CLK_RATE); - ssdk_clock_rate_set_and_enable(clock_node, - GMAC0_PTP_CLK, GMAC_CLK_RATE); - ssdk_clock_rate_set_and_enable(clock_node, - GMAC1_PTP_CLK, GMAC_CLK_RATE); - ssdk_clock_rate_set_and_enable(clock_node, - SNOC_GMAC0_AHB_CLK, GMAC_CLK_RATE); - ssdk_clock_rate_set_and_enable(clock_node, - SNOC_GMAC1_AHB_CLK, GMAC_CLK_RATE); -} - -static void ssdk_mp_uniphy_clock_init(void) -{ - a_uint32_t i, inst_num; - struct clk *clk; - struct clk **ports; - - inst_num = sizeof(mp_raw_clks) / sizeof(struct clk_hw *); - - for (i = 0; i < inst_num; i++) { - clk = clk_register(NULL, mp_raw_clks[i]); - if (IS_ERR(clk)) - SSDK_ERROR("Clk register %d fail!\n", i); - } - - ports = uniphy_port_clks; - ports[NSS_PORT1_RX_CLK_E] = of_clk_get_by_name(clock_node, - NSS_PORT1_RX_CLK); - ports[NSS_PORT1_TX_CLK_E] = of_clk_get_by_name(clock_node, - NSS_PORT1_TX_CLK); - ports[NSS_PORT2_RX_CLK_E] = of_clk_get_by_name(clock_node, - NSS_PORT2_RX_CLK); - ports[NSS_PORT2_TX_CLK_E] = of_clk_get_by_name(clock_node, - NSS_PORT2_TX_CLK); - ports[UNIPHY0_PORT1_RX_CLK_E] = of_clk_get_by_name(clock_node, - UNIPHY0_PORT1_RX_CLK); - ports[UNIPHY0_PORT1_TX_CLK_E] = of_clk_get_by_name(clock_node, - UNIPHY0_PORT1_TX_CLK); - ports[UNIPHY1_PORT5_RX_CLK_E] = of_clk_get_by_name(clock_node, - UNIPHY1_PORT5_RX_CLK); - ports[UNIPHY1_PORT5_TX_CLK_E] = of_clk_get_by_name(clock_node, - UNIPHY1_PORT5_TX_CLK); -} - -static void ssdk_mp_uniphy_clock_enable(void) -{ - ssdk_uniphy_clock_enable(0, NSS_PORT1_RX_CLK_E, A_TRUE); - ssdk_uniphy_clock_enable(0, NSS_PORT1_TX_CLK_E, A_TRUE); - ssdk_uniphy_clock_enable(0, NSS_PORT2_RX_CLK_E, A_TRUE); - ssdk_uniphy_clock_enable(0, NSS_PORT2_TX_CLK_E, A_TRUE); - ssdk_uniphy_clock_enable(0, UNIPHY0_PORT1_RX_CLK_E, A_TRUE); - ssdk_uniphy_clock_enable(0, UNIPHY0_PORT1_TX_CLK_E, A_TRUE); - ssdk_uniphy_clock_enable(0, UNIPHY1_PORT5_RX_CLK_E, A_TRUE); - ssdk_uniphy_clock_enable(0, UNIPHY1_PORT5_TX_CLK_E, A_TRUE); -} - -static void -ssdk_mp_tcsr_get(a_uint32_t tcsr_offset, a_uint32_t *tcsr_val) -{ - void __iomem *tcsr_base = NULL; - - tcsr_base = ioremap_nocache(TCSR_ETH_ADDR, TCSR_ETH_SIZE); - if (!tcsr_base) - { - SSDK_ERROR("Failed to map tcsr eth address!\n"); - return; - } - *tcsr_val = readl(tcsr_base + tcsr_offset); - iounmap(tcsr_base); - - return; -} - -static void -ssdk_mp_tcsr_set(a_uint32_t tcsr_offset, a_uint32_t tcsr_val) -{ - void __iomem *tcsr_base = NULL; - - tcsr_base = ioremap_nocache(TCSR_ETH_ADDR, TCSR_ETH_SIZE); - if (!tcsr_base) - { - SSDK_ERROR("Failed to map tcsr eth address!\n"); - return; - } - writel(tcsr_val, tcsr_base + tcsr_offset); - iounmap(tcsr_base); - - return; -} - -static void -ssdk_mp_cmnblk_enable(void) -{ - a_uint32_t reg_val; - - ssdk_mp_tcsr_get(TCSR_ETH_LDO_RDY, ®_val); - reg_val |= ETH_LDO_RDY; - ssdk_mp_tcsr_set(TCSR_ETH_LDO_RDY, reg_val); - - return; -} - -void -ssdk_mp_gephy_icc_efuse_load_enable(a_bool_t enable) -{ - a_uint32_t reg_val; - - ssdk_mp_tcsr_get(TCSR_GEPHY_LDO_BIAS_EN, ®_val); - if(!enable) - { - reg_val |= GEPHY_LDO_BIAS_EN; - } - else - { - reg_val &= ~GEPHY_LDO_BIAS_EN; - } - ssdk_mp_tcsr_set(TCSR_GEPHY_LDO_BIAS_EN, reg_val); -} - -static a_bool_t -ssdk_mp_cmnblk_stable_check(void) -{ - void __iomem *pll_lock = NULL; - a_uint32_t reg_val; - int i, loops = 20; - - pll_lock = ioremap_nocache(CMN_PLL_LOCKED_ADDR, CMN_PLL_LOCKED_SIZE); - if (!pll_lock) { - SSDK_ERROR("Failed to map CMN PLL LOCK register!\n"); - return A_FALSE; - } - - for (i = 0; i < loops; i++) { - reg_val = readl(pll_lock); - if (reg_val & CMN_PLL_LOCKED) { - break; - } - msleep(10); - } - - iounmap(pll_lock); - - if (i >= loops) { - return A_FALSE; - } else { - return A_TRUE; - } -} - -static void -ssdk_mp_reset_init(void) -{ -#if defined(CONFIG_OF) && (LINUX_VERSION_CODE >= KERNEL_VERSION(4,4,0)) - struct reset_control *rst; - a_uint32_t i; - - rst_node = of_find_node_by_name(NULL, "ess-switch"); - - for (i = 0; i < MP_BCR_RST_MAX; i++) { - rst = of_reset_control_get(rst_node, mp_rst_ids[i]); - if (IS_ERR(rst)) { - SSDK_ERROR("%s not exist!\n", mp_rst_ids[i]); - return; - } - ssdk_gcc_reset(rst, SSDK_RESET_ASSERT); - msleep(200); - ssdk_gcc_reset(rst, SSDK_RESET_DEASSERT); - msleep(200); - reset_control_put(rst); - } - - i = UNIPHY1_SOFT_RESET_E; - uniphy_rsts[i] = of_reset_control_get(rst_node, UNIPHY1_SOFT_RESET_ID); - - SSDK_INFO("MP reset successfully!\n"); -#endif -} - -static void ssdk_cmnblk_pll_src_set(enum cmnblk_pll_src_type pll_source) -{ - void __iomem *cmn_pll_src_base = NULL; - a_uint32_t reg_val; - - cmn_pll_src_base = ioremap_nocache(CMN_BLK_PLL_SRC_ADDR, CMN_BLK_SIZE); - if (!cmn_pll_src_base) { - SSDK_ERROR("Failed to map cmn pll source address!\n"); - return; - } - reg_val = readl(cmn_pll_src_base); - reg_val = (reg_val & PLL_CTRL_SRC_MASK) | (pll_source << 0x8); - writel(reg_val, cmn_pll_src_base); - iounmap(cmn_pll_src_base); - - return; -} -#endif -#endif - -#if defined(HPPE) || defined(MP) -static void ssdk_cmnblk_init(enum cmnblk_clk_type mode) -{ - void __iomem *gcc_pll_base = NULL; - a_uint32_t reg_val; - - gcc_pll_base = ioremap_nocache(CMN_BLK_ADDR, CMN_BLK_SIZE); - if (!gcc_pll_base) { - SSDK_ERROR("Failed to map gcc pll address!\n"); - return; - } - reg_val = readl(gcc_pll_base + 4); - - switch (mode) { - case INTERNAL_48MHZ: - reg_val = (reg_val & FREQUENCY_MASK) | INTERNAL_48MHZ_CLOCK; - break; - case EXTERNAL_50MHZ: - reg_val = (reg_val & FREQUENCY_MASK) | EXTERNAL_50MHZ_CLOCK; - break; - case EXTERNAL_25MHZ: - reg_val = (reg_val & FREQUENCY_MASK) | EXTERNAL_25MHZ_CLOCK; - break; - case EXTERNAL_31250KHZ: - reg_val = (reg_val & FREQUENCY_MASK) | EXTERNAL_31250KHZ_CLOCK; - break; - case EXTERNAL_40MHZ: - reg_val = (reg_val & FREQUENCY_MASK) | EXTERNAL_40MHZ_CLOCK; - break; - case EXTERNAL_48MHZ: - reg_val = (reg_val & FREQUENCY_MASK) | EXTERNAL_48MHZ_CLOCK; - break; -#if defined(MP) - case INTERNAL_96MHZ: - ssdk_cmnblk_pll_src_set(CMN_BLK_PLL_SRC_SEL_FROM_REG); - reg_val = (reg_val & PLL_REFCLK_DIV_MASK) | PLL_REFCLK_DIV_2; - break; -#endif - default: - return; - } - - writel(reg_val, gcc_pll_base + 0x4); - reg_val = readl(gcc_pll_base); - reg_val = reg_val | 0x40; - writel(reg_val, gcc_pll_base); - msleep(1); - reg_val = reg_val & (~0x40); - writel(reg_val, gcc_pll_base); - msleep(1); - writel(0xbf, gcc_pll_base); - msleep(1); - writel(0xff, gcc_pll_base); - msleep(1); - - iounmap(gcc_pll_base); -} - -void ssdk_port_mac_clock_reset( - a_uint32_t dev_id, - a_uint32_t port_id) -{ -#if defined(CONFIG_OF) && (LINUX_VERSION_CODE >= KERNEL_VERSION(4,4,0)) - ssdk_port_reset(dev_id, port_id, SSDK_RESET_ASSERT); - msleep(150); - ssdk_port_reset(dev_id, port_id, SSDK_RESET_DEASSERT); - msleep(150); -#endif - return; -} -#endif - -#if defined(HPPE) -static -void ssdk_uniphy1_clock_source_set(void) -{ -#if defined(CONFIG_OF) && (LINUX_VERSION_CODE >= KERNEL_VERSION(4,4,0)) - clk_set_parent(uniphy_port_clks[PORT5_RX_SRC_E], - uniphy_raw_clks[2]->clk); - clk_set_parent(uniphy_port_clks[PORT5_TX_SRC_E], - uniphy_raw_clks[3]->clk); -#endif -} - -void ssdk_uniphy_raw_clock_reset(a_uint8_t uniphy_index) -{ -#if defined(CONFIG_OF) && (LINUX_VERSION_CODE >= KERNEL_VERSION(4,4,0)) - a_uint32_t id; - - if (uniphy_index >= SSDK_MAX_UNIPHY_INSTANCE) - return; - - id = uniphy_index*2; - if (clk_set_rate(uniphy_raw_clks[id]->clk, UNIPHY_DEFAULT_RATE)) - SSDK_ERROR("set rate for %d fail!\n", id); - if (clk_set_rate(uniphy_raw_clks[id+1]->clk, UNIPHY_DEFAULT_RATE)) - SSDK_ERROR("set rate for %d fail!\n", id+1); -#endif -} - -void ssdk_uniphy_raw_clock_set( - a_uint8_t uniphy_index, - a_uint8_t direction, - a_uint32_t clock) -{ -#if defined(CONFIG_OF) && (LINUX_VERSION_CODE >= KERNEL_VERSION(4,4,0)) - a_uint32_t old_clock, id, mode; - - if ((uniphy_index >= SSDK_MAX_UNIPHY_INSTANCE) || - (direction > UNIPHY_TX) || - (clock != UNIPHY_CLK_RATE_125M && - clock != UNIPHY_CLK_RATE_312M)) - return; - - id = uniphy_index*2 + direction; - old_clock = clk_get_rate(uniphy_raw_clks[id]->clk); - - if (clock != old_clock) { - if (uniphy_index == SSDK_UNIPHY_INSTANCE1) { - if (UNIPHY_RX == direction) - ssdk_uniphy_clock_rate_set(0, - NSS_PORT5_RX_CLK_E, - NSS_PORT5_DFLT_RATE); - else - ssdk_uniphy_clock_rate_set(0, - NSS_PORT5_TX_CLK_E, - NSS_PORT5_DFLT_RATE); - } - if (clk_set_rate(uniphy_raw_clks[id]->clk, clock)) - SSDK_ERROR("set rate: %d fail!\n", clock); - } - - mode = ssdk_dt_global_get_mac_mode(0, SSDK_UNIPHY_INSTANCE1); - if (((uniphy_index == SSDK_UNIPHY_INSTANCE0) && - (mode == PORT_INTERFACE_MODE_MAX)) || - (uniphy_index == SSDK_UNIPHY_INSTANCE1)) { - if (clk_set_parent(uniphy_port_clks[PORT5_RX_SRC_E + direction], - uniphy_raw_clks[id]->clk)) - SSDK_ERROR("set parent fail!\n"); - } -#endif -} - -void ssdk_uniphy_port5_clock_source_set(void) -{ -#if defined(CONFIG_OF) && (LINUX_VERSION_CODE >= KERNEL_VERSION(4,4,0)) - a_uint32_t id, mode, i; - - mode = ssdk_dt_global_get_mac_mode(0, SSDK_UNIPHY_INSTANCE1); - - for (i = UNIPHY_RX; i <= UNIPHY_TX; i++) { - if (mode == PORT_INTERFACE_MODE_MAX) { - id = SSDK_UNIPHY_INSTANCE0*2 + i; - } else { - id = SSDK_UNIPHY_INSTANCE1*2 + i; - } - if (clk_set_parent(uniphy_port_clks[PORT5_RX_SRC_E + i], - uniphy_raw_clks[id]->clk)) { - SSDK_ERROR("set parent fail!\n"); - } - } -#endif -} - -static -void ssdk_gcc_ppe_clock_init(a_uint32_t revision, enum cmnblk_clk_type mode) -{ -#if defined(CONFIG_OF) && (LINUX_VERSION_CODE >= KERNEL_VERSION(4,4,0)) - ssdk_ppe_fixed_clock_init(revision); - /*fixme for cmn clock init*/ - ssdk_cmnblk_init(mode); - ssdk_ppe_uniphy_clock_init(revision); - ssdk_uniphy_port5_clock_source_set(); -#endif -} -#endif - -#if defined(MP) -void ssdk_gcc_mp_clock_init(enum cmnblk_clk_type mode) -{ -#if defined(CONFIG_OF) && (LINUX_VERSION_CODE >= KERNEL_VERSION(4,4,0)) - ssdk_mp_fixed_clock_init(); - ssdk_mp_uniphy_clock_init(); - ssdk_cmnblk_init(mode); - msleep(200); - ssdk_mp_cmnblk_enable(); - if (ssdk_mp_cmnblk_stable_check()) { - ssdk_mp_reset_init(); - ssdk_mp_uniphy_clock_enable(); - } else { - SSDK_ERROR("Cmnblock is still not stable!\n"); - } -#endif -} - -void ssdk_mp_raw_clock_set( - a_uint8_t uniphy_index, - a_uint8_t direction, - a_uint32_t clock) -{ -#if defined(CONFIG_OF) && (LINUX_VERSION_CODE >= KERNEL_VERSION(4,4,0)) - a_uint32_t old_clock, id; - - if ((uniphy_index >= MP_RAW_CLOCK_INSTANCE) || - (direction > UNIPHY_TX) || - (clock != UNIPHY_CLK_RATE_125M && - clock != UNIPHY_CLK_RATE_312M)) - return; - - if(ssdk_is_emulation(0)){ - SSDK_INFO("uniphy_index %d direction %d clock %d on emulation platform\n", - uniphy_index, direction, clock); - return; - } - - id = uniphy_index*2 + direction; - old_clock = clk_get_rate(mp_raw_clks[id]->clk); - - if (clock != old_clock) { - if (clk_set_rate(mp_raw_clks[id]->clk, clock)) - SSDK_ERROR("set rate: %d fail!\n", clock); - } -#endif -} - -#endif - -#if defined(HPPE) || defined(MP) -void ssdk_gcc_clock_init(void) -{ -#if defined(CONFIG_OF) && (LINUX_VERSION_CODE >= KERNEL_VERSION(4,4,0)) - enum cmnblk_clk_type cmnblk_clk_mode = INTERNAL_48MHZ; - a_uint8_t *mode = NULL; - - clock_node = of_find_node_by_name(NULL, "ess-switch"); - if (of_property_read_string(clock_node, "cmnblk_clk", - (const char **)&mode)) { - cmnblk_clk_mode = INTERNAL_48MHZ; - } else { - if (!strcmp(mode, "external_50MHz")) { - cmnblk_clk_mode = EXTERNAL_50MHZ; - } else if (!strcmp(mode, "external_25MHz")) { - cmnblk_clk_mode = EXTERNAL_25MHZ; - } else if (!strcmp(mode, "external_31250KHz")) { - cmnblk_clk_mode = EXTERNAL_31250KHZ; - } else if (!strcmp(mode, "external_40MHz")) { - cmnblk_clk_mode = EXTERNAL_40MHZ; - } else if (!strcmp(mode, "external_48MHz")) { - cmnblk_clk_mode = EXTERNAL_48MHZ; - } else if (!strcmp(mode, "internal_96MHz")) { - cmnblk_clk_mode = INTERNAL_96MHZ; - } - } - - if (of_device_is_compatible(clock_node, "qcom,ess-switch-ipq807x")) { -#if defined(HPPE) - ssdk_gcc_ppe_clock_init(HPPE_REVISION, cmnblk_clk_mode); -#endif - } else if (of_device_is_compatible(clock_node, - "qcom,ess-switch-ipq60xx")) { -#if defined(HPPE) - ssdk_gcc_ppe_clock_init(CPPE_REVISION, cmnblk_clk_mode); -#endif - } else if (of_device_is_compatible(clock_node, - "qcom,ess-switch-ipq50xx")) { -#if defined(MP) - ssdk_gcc_mp_clock_init(cmnblk_clk_mode); -#endif - } -#endif - SSDK_INFO("SSDK gcc clock init successfully!\n"); -} - -void -qca_gcc_uniphy_port_clock_set( - a_uint32_t dev_id, a_uint32_t uniphy_index, - a_uint32_t port_id, a_bool_t enable) -{ - - if (uniphy_index == SSDK_UNIPHY_INSTANCE2) { - ssdk_uniphy_clock_enable(dev_id, - UNIPHY2_PORT6_RX_CLK_E, enable); - ssdk_uniphy_clock_enable(dev_id, - UNIPHY2_PORT6_TX_CLK_E, enable); - } else if (uniphy_index == SSDK_UNIPHY_INSTANCE1) { - ssdk_uniphy_clock_enable(dev_id, - UNIPHY1_PORT5_RX_CLK_E, enable); - ssdk_uniphy_clock_enable(dev_id, - UNIPHY1_PORT5_TX_CLK_E, enable); - } else if (uniphy_index == SSDK_UNIPHY_INSTANCE0) { - switch (port_id) { - case SSDK_PHYSICAL_PORT1: - ssdk_uniphy_clock_enable(dev_id, - UNIPHY0_PORT1_RX_CLK_E, - enable); - ssdk_uniphy_clock_enable(dev_id, - UNIPHY0_PORT1_TX_CLK_E, - enable); - break; - case SSDK_PHYSICAL_PORT2: - ssdk_uniphy_clock_enable(dev_id, - UNIPHY0_PORT2_RX_CLK_E, - enable); - ssdk_uniphy_clock_enable(dev_id, - UNIPHY0_PORT2_TX_CLK_E, - enable); - break; - case SSDK_PHYSICAL_PORT3: - ssdk_uniphy_clock_enable(dev_id, - UNIPHY0_PORT3_RX_CLK_E, - enable); - ssdk_uniphy_clock_enable(dev_id, - UNIPHY0_PORT3_TX_CLK_E, - enable); - break; - case SSDK_PHYSICAL_PORT4: - ssdk_uniphy_clock_enable(dev_id, - UNIPHY0_PORT4_RX_CLK_E, - enable); - ssdk_uniphy_clock_enable(dev_id, - UNIPHY0_PORT4_TX_CLK_E, - enable); - break; - case SSDK_PHYSICAL_PORT5: - ssdk_uniphy_clock_enable(dev_id, - UNIPHY0_PORT5_RX_CLK_E, - enable); - ssdk_uniphy_clock_enable(dev_id, - UNIPHY0_PORT5_TX_CLK_E, - enable); - break; - default: - break; - } - } -} - -void -qca_gcc_mac_port_clock_set( - a_uint32_t dev_id, - a_uint32_t port_id, - a_bool_t enable) -{ - - switch (port_id) { - case SSDK_PHYSICAL_PORT1: - ssdk_uniphy_clock_enable(dev_id, - NSS_PORT1_RX_CLK_E, - enable); - ssdk_uniphy_clock_enable(dev_id, - NSS_PORT1_TX_CLK_E, - enable); - break; - case SSDK_PHYSICAL_PORT2: - ssdk_uniphy_clock_enable(dev_id, - NSS_PORT2_RX_CLK_E, - enable); - ssdk_uniphy_clock_enable(dev_id, - NSS_PORT2_TX_CLK_E, - enable); - break; - case SSDK_PHYSICAL_PORT3: - ssdk_uniphy_clock_enable(dev_id, - NSS_PORT3_RX_CLK_E, - enable); - ssdk_uniphy_clock_enable(dev_id, - NSS_PORT3_TX_CLK_E, - enable); - break; - case SSDK_PHYSICAL_PORT4: - ssdk_uniphy_clock_enable(dev_id, - NSS_PORT4_RX_CLK_E, - enable); - ssdk_uniphy_clock_enable(dev_id, - NSS_PORT4_TX_CLK_E, - enable); - break; - case SSDK_PHYSICAL_PORT5: - ssdk_uniphy_clock_enable(dev_id, - NSS_PORT5_RX_CLK_E, - enable); - ssdk_uniphy_clock_enable(dev_id, - NSS_PORT5_TX_CLK_E, - enable); - break; - case SSDK_PHYSICAL_PORT6: - ssdk_uniphy_clock_enable(dev_id, - NSS_PORT6_RX_CLK_E, - enable); - ssdk_uniphy_clock_enable(dev_id, - NSS_PORT6_TX_CLK_E, - enable); - break; - default: - break; - } -} - -void -ssdk_port_speed_clock_set( - a_uint32_t dev_id, - a_uint32_t port_id, - a_uint32_t rate) -{ -#if defined(HPPE) - a_uint32_t mode = 0; -#endif - - switch (port_id ) { - case SSDK_PHYSICAL_PORT1: - ssdk_uniphy_clock_rate_set(dev_id, - NSS_PORT1_RX_CLK_E, rate); - ssdk_uniphy_clock_rate_set(dev_id, - NSS_PORT1_TX_CLK_E, rate); - break; - case SSDK_PHYSICAL_PORT2: - ssdk_uniphy_clock_rate_set(dev_id, - NSS_PORT2_RX_CLK_E, rate); - ssdk_uniphy_clock_rate_set(dev_id, - NSS_PORT2_TX_CLK_E, rate); - break; -#if defined(HPPE) - case SSDK_PHYSICAL_PORT3: - ssdk_uniphy_clock_rate_set(dev_id, - NSS_PORT3_RX_CLK_E, rate); - ssdk_uniphy_clock_rate_set(dev_id, - NSS_PORT3_TX_CLK_E, rate); - break; - case SSDK_PHYSICAL_PORT4: - ssdk_uniphy_clock_rate_set(dev_id, - NSS_PORT4_RX_CLK_E, rate); - ssdk_uniphy_clock_rate_set(dev_id, - NSS_PORT4_TX_CLK_E, rate); - break; - case SSDK_PHYSICAL_PORT5: - ssdk_uniphy_clock_rate_set(dev_id, - NSS_PORT5_RX_CLK_E, rate); - ssdk_uniphy_clock_rate_set(dev_id, - NSS_PORT5_TX_CLK_E, rate); - mode = ssdk_dt_global_get_mac_mode(dev_id, SSDK_UNIPHY_INSTANCE1); - if (mode != PORT_INTERFACE_MODE_MAX) - ssdk_uniphy1_clock_source_set(); - break; - case SSDK_PHYSICAL_PORT6: - ssdk_uniphy_clock_rate_set(dev_id, - NSS_PORT6_RX_CLK_E, rate); - ssdk_uniphy_clock_rate_set(dev_id, - NSS_PORT6_TX_CLK_E, rate); - break; -#endif - default: - break; - } -} -#endif - -#if defined(HPPE) -#if defined(CONFIG_OF) && (LINUX_VERSION_CODE >= KERNEL_VERSION(4,4,0)) -static char *ppe_rst_ids[UNIPHY_RST_MAX] = { - UNIPHY0_SOFT_RESET_ID, - UNIPHY0_XPCS_RESET_ID, - UNIPHY1_SOFT_RESET_ID, - UNIPHY1_XPCS_RESET_ID, - UNIPHY2_SOFT_RESET_ID, - UNIPHY2_XPCS_RESET_ID, - UNIPHY0_PORT1_DISABLE_ID, - UNIPHY0_PORT2_DISABLE_ID, - UNIPHY0_PORT3_DISABLE_ID, - UNIPHY0_PORT4_DISABLE_ID, - UNIPHY0_PORT5_DISABLE_ID, - UNIPHY0_PORT_4_5_RESET_ID, - UNIPHY0_PORT_4_RESET_ID -}; -static char *port_rst_ids[SSDK_MAX_PORT_NUM] = { - SSDK_PORT1_RESET_ID, - SSDK_PORT2_RESET_ID, - SSDK_PORT3_RESET_ID, - SSDK_PORT4_RESET_ID, - SSDK_PORT5_RESET_ID, - SSDK_PORT6_RESET_ID, - NULL, NULL -}; -#endif - -void ssdk_ppe_reset_init(void) -{ -#if defined(CONFIG_OF) && (LINUX_VERSION_CODE >= KERNEL_VERSION(4,4,0)) - struct reset_control *rst; - a_uint32_t i; - - rst_node = of_find_node_by_name(NULL, "ess-switch"); - rst = of_reset_control_get(rst_node, PPE_RESET_ID); - if (IS_ERR(rst)) { - SSDK_ERROR("%s not exist!\n", PPE_RESET_ID); - return; - } - - ssdk_gcc_reset(rst, SSDK_RESET_ASSERT); - msleep(100); - ssdk_gcc_reset(rst, SSDK_RESET_DEASSERT); - msleep(100); - reset_control_put(rst); - SSDK_INFO("ppe reset successfully!\n"); - - for (i = UNIPHY0_SOFT_RESET_E; i < UNIPHY_RST_MAX; i++) - uniphy_rsts[i] = of_reset_control_get(rst_node, - ppe_rst_ids[i]); - - for (i = SSDK_PHYSICAL_PORT1; i < SSDK_PHYSICAL_PORT7; i++) - port_rsts[i-1] = of_reset_control_get(rst_node, - port_rst_ids[i-1]); -#endif -} - -void ssdk_gcc_uniphy_sys_set(a_uint32_t dev_id, a_uint32_t uniphy_index, - a_bool_t enable) -{ - enum unphy_rst_type rst_type; - - if (of_device_is_compatible(clock_node, "qcom,ess-switch-ipq60xx")){ - if (uniphy_index > SSDK_UNIPHY_INSTANCE1) { - return; - } - } - - if (uniphy_index == SSDK_UNIPHY_INSTANCE0) { - rst_type = UNIPHY0_SOFT_RESET_E; - } else if (uniphy_index == SSDK_UNIPHY_INSTANCE1) { - rst_type = UNIPHY1_SOFT_RESET_E; - } else { - rst_type = UNIPHY2_SOFT_RESET_E; - } - - if (enable == A_TRUE) { - ssdk_uniphy_reset(dev_id, rst_type, SSDK_RESET_DEASSERT); - } else { - ssdk_uniphy_reset(dev_id, rst_type, SSDK_RESET_ASSERT); - } - - return; -} -#endif - diff --git a/feeds/ipq807x/qca-ssdk/src/src/init/ssdk_dts.c b/feeds/ipq807x/qca-ssdk/src/src/init/ssdk_dts.c deleted file mode 100644 index ddc0e8af8..000000000 --- a/feeds/ipq807x/qca-ssdk/src/src/init/ssdk_dts.c +++ /dev/null @@ -1,1200 +0,0 @@ -/* - * Copyright (c) 2018-2020, The Linux Foundation. All rights reserved. - * Permission to use, copy, modify, and/or distribute this software for - * any purpose with or without fee is hereby granted, provided that the - * above copyright notice and this permission notice appear in all copies. - * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES - * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR - * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES - * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN - * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT - * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. - */ -#include -#include -#if defined(CONFIG_OF) -#include -#include -#include -#include -#endif -#include -#include - -#include "ssdk_init.h" -#include "ssdk_dts.h" -#include "ssdk_plat.h" -#include "hsl_phy.h" - -static ssdk_dt_global_t ssdk_dt_global = {0}; -#ifdef HPPE -#ifdef IN_QOS -a_uint8_t ssdk_tm_tick_mode_get(a_uint32_t dev_id) -{ - ssdk_dt_cfg* cfg = ssdk_dt_global.ssdk_dt_switch_nodes[dev_id]; - - return cfg->tm_tick_mode; -} - -ssdk_dt_scheduler_cfg* ssdk_bootup_shceduler_cfg_get(a_uint32_t dev_id) -{ - ssdk_dt_cfg* cfg = ssdk_dt_global.ssdk_dt_switch_nodes[dev_id]; - - return &cfg->scheduler_cfg; -} -#endif -#endif -#ifdef IN_BM -a_uint8_t ssdk_bm_tick_mode_get(a_uint32_t dev_id) -{ - ssdk_dt_cfg* cfg = ssdk_dt_global.ssdk_dt_switch_nodes[dev_id]; - - return cfg->bm_tick_mode; -} -#endif -#ifdef IN_QM -a_uint16_t ssdk_ucast_queue_start_get(a_uint32_t dev_id, a_uint32_t port) -{ - ssdk_dt_cfg* cfg = ssdk_dt_global.ssdk_dt_switch_nodes[dev_id]; - - return cfg->scheduler_cfg.pool[port].ucastq_start; -} -#endif -a_uint32_t ssdk_intf_mac_num_get(void) -{ - return ssdk_dt_global.num_intf_mac; -} - -a_uint8_t* ssdk_intf_macaddr_get(a_uint32_t index) -{ - return ssdk_dt_global.intf_mac[index].uc; -} - -a_uint32_t ssdk_dt_global_get_mac_mode(a_uint32_t dev_id, a_uint32_t index) -{ - if (index == 0) { - return ssdk_dt_global.ssdk_dt_switch_nodes[dev_id]->mac_mode; - } - if (index == 1) { - return ssdk_dt_global.ssdk_dt_switch_nodes[dev_id]->mac_mode1; - } - if (index == 2) { - return ssdk_dt_global.ssdk_dt_switch_nodes[dev_id]->mac_mode2; - } - - return 0; -} - -a_uint32_t ssdk_dt_global_set_mac_mode(a_uint32_t dev_id, a_uint32_t index, a_uint32_t mode) -{ - if (index == 0) - { - ssdk_dt_global.ssdk_dt_switch_nodes[dev_id]->mac_mode= mode; - } - if (index == 1) - { - ssdk_dt_global.ssdk_dt_switch_nodes[dev_id]->mac_mode1 = mode; - } - if (index == 2) - { - ssdk_dt_global.ssdk_dt_switch_nodes[dev_id]->mac_mode2 = mode; - } - - return 0; -} - -a_uint32_t ssdk_cpu_bmp_get(a_uint32_t dev_id) -{ - ssdk_dt_cfg* cfg = ssdk_dt_global.ssdk_dt_switch_nodes[dev_id]; - - return cfg->port_cfg.cpu_bmp; -} - -a_uint32_t ssdk_lan_bmp_get(a_uint32_t dev_id) -{ - ssdk_dt_cfg* cfg = ssdk_dt_global.ssdk_dt_switch_nodes[dev_id]; - - return cfg->port_cfg.lan_bmp; -} - -a_uint32_t ssdk_wan_bmp_get(a_uint32_t dev_id) -{ - ssdk_dt_cfg* cfg = ssdk_dt_global.ssdk_dt_switch_nodes[dev_id]; - - return cfg->port_cfg.wan_bmp; -} - -sw_error_t ssdk_lan_bmp_set(a_uint32_t dev_id, a_uint32_t lan_bmp) -{ - ssdk_dt_cfg* cfg = ssdk_dt_global.ssdk_dt_switch_nodes[dev_id]; - cfg->port_cfg.lan_bmp = lan_bmp; - - return SW_OK; -} - -sw_error_t ssdk_wan_bmp_set(a_uint32_t dev_id, a_uint32_t wan_bmp) -{ - ssdk_dt_cfg* cfg = ssdk_dt_global.ssdk_dt_switch_nodes[dev_id]; - cfg->port_cfg.wan_bmp = wan_bmp; - - return SW_OK; -} - -a_uint32_t ssdk_inner_bmp_get(a_uint32_t dev_id) -{ - ssdk_dt_cfg* cfg = ssdk_dt_global.ssdk_dt_switch_nodes[dev_id]; - - return cfg->port_cfg.inner_bmp; -} - -ssdk_port_phyinfo* ssdk_port_phyinfo_get(a_uint32_t dev_id, a_uint32_t port_id) -{ - a_uint32_t i; - ssdk_port_phyinfo *phyinfo_tmp = NULL; - ssdk_dt_cfg *cfg = ssdk_dt_global.ssdk_dt_switch_nodes[dev_id]; - - for (i = 0; i < cfg->phyinfo_num; i++) { - if (port_id == cfg->port_phyinfo[i].port_id) { - phyinfo_tmp = &cfg->port_phyinfo[i]; - break; - } else if (!(cfg->port_phyinfo[i].phy_features & PHY_F_INIT) && - phyinfo_tmp == NULL) { - phyinfo_tmp = &cfg->port_phyinfo[i]; - } - } - - return phyinfo_tmp; -} - -a_bool_t ssdk_port_feature_get(a_uint32_t dev_id, a_uint32_t port_id, phy_features_t feature) -{ - ssdk_port_phyinfo *phyinfo = ssdk_port_phyinfo_get(dev_id, port_id); - if (phyinfo && (phyinfo->phy_features & feature)) { - return A_TRUE; - } - return A_FALSE; -} - -a_uint32_t ssdk_port_force_speed_get(a_uint32_t dev_id, a_uint32_t port_id) -{ - ssdk_port_phyinfo *phyinfo = ssdk_port_phyinfo_get(dev_id, port_id); - if (phyinfo && (phyinfo->phy_features & PHY_F_FORCE)) { - return phyinfo->port_speed; - } - return FAL_SPEED_BUTT; -} - -struct mii_bus * -ssdk_dts_miibus_get(a_uint32_t dev_id, a_uint32_t phy_addr) -{ - a_uint32_t i; - ssdk_dt_cfg* cfg = ssdk_dt_global.ssdk_dt_switch_nodes[dev_id]; - - for (i = 0; i < cfg->phyinfo_num; i++) { - if (phy_addr == cfg->port_phyinfo[i].phy_addr || - phy_addr == cfg->port_phyinfo[i].phy_addr+1) - return cfg->port_phyinfo[i].miibus; - } - - return NULL; -} - -hsl_reg_mode ssdk_switch_reg_access_mode_get(a_uint32_t dev_id) -{ - ssdk_dt_cfg* cfg = ssdk_dt_global.ssdk_dt_switch_nodes[dev_id]; - - return cfg->switch_reg_access_mode; -} -#ifdef IN_UNIPHY -hsl_reg_mode ssdk_uniphy_reg_access_mode_get(a_uint32_t dev_id) -{ - ssdk_dt_cfg* cfg = ssdk_dt_global.ssdk_dt_switch_nodes[dev_id]; - - return cfg->uniphy_reg_access_mode; -} -#endif -#ifdef DESS -hsl_reg_mode ssdk_psgmii_reg_access_mode_get(a_uint32_t dev_id) -{ - ssdk_dt_cfg* cfg = ssdk_dt_global.ssdk_dt_switch_nodes[dev_id]; - - return cfg->psgmii_reg_access_mode; -} -#endif -void ssdk_switch_reg_map_info_get(a_uint32_t dev_id, ssdk_reg_map_info *info) -{ - ssdk_dt_cfg* cfg = ssdk_dt_global.ssdk_dt_switch_nodes[dev_id]; - - info->base_addr = cfg->switchreg_base_addr; - info->size = cfg->switchreg_size; -} -#ifdef DESS -void ssdk_psgmii_reg_map_info_get(a_uint32_t dev_id, ssdk_reg_map_info *info) -{ - ssdk_dt_cfg* cfg = ssdk_dt_global.ssdk_dt_switch_nodes[dev_id]; - - info->base_addr = cfg->psgmiireg_base_addr; - info->size = cfg->psgmiireg_size; -} -#endif -#ifdef IN_UNIPHY -void ssdk_uniphy_reg_map_info_get(a_uint32_t dev_id, ssdk_reg_map_info *info) -{ - ssdk_dt_cfg* cfg = ssdk_dt_global.ssdk_dt_switch_nodes[dev_id]; - - info->base_addr = cfg->uniphyreg_base_addr; - info->size = cfg->uniphyreg_size; -} -#endif -a_bool_t ssdk_ess_switch_flag_get(a_uint32_t dev_id) -{ - ssdk_dt_cfg* cfg = ssdk_dt_global.ssdk_dt_switch_nodes[dev_id]; - - return cfg->ess_switch_flag; -} - -a_uint32_t ssdk_device_id_get(a_uint32_t index) -{ - return ssdk_dt_global.ssdk_dt_switch_nodes[index]->device_id; -} - -struct device_node *ssdk_dts_node_get(a_uint32_t dev_id) -{ - ssdk_dt_cfg* cfg = ssdk_dt_global.ssdk_dt_switch_nodes[dev_id]; - - return cfg->of_node; -} - -struct clk *ssdk_dts_essclk_get(a_uint32_t dev_id) -{ - ssdk_dt_cfg* cfg = ssdk_dt_global.ssdk_dt_switch_nodes[dev_id]; - - return cfg->ess_clk; -} - -struct clk *ssdk_dts_cmnclk_get(a_uint32_t dev_id) -{ - ssdk_dt_cfg* cfg = ssdk_dt_global.ssdk_dt_switch_nodes[dev_id]; - - return cfg->cmnblk_clk; -} - -#ifndef BOARD_AR71XX -#if defined(CONFIG_OF) && (LINUX_VERSION_CODE >= KERNEL_VERSION(3,14,0)) -static void ssdk_dt_parse_mac_mode(a_uint32_t dev_id, - struct device_node *switch_node, ssdk_init_cfg *cfg) -{ - const __be32 *mac_mode; - a_uint32_t len = 0; - - mac_mode = of_get_property(switch_node, "switch_mac_mode", &len); - if (!mac_mode) - SSDK_INFO("mac mode doesn't exit!\n"); - else { - cfg->mac_mode = be32_to_cpup(mac_mode); - SSDK_INFO("mac mode = 0x%x\n", be32_to_cpup(mac_mode)); - ssdk_dt_global.ssdk_dt_switch_nodes[dev_id]->mac_mode = cfg->mac_mode; - } - - mac_mode = of_get_property(switch_node, "switch_mac_mode1", &len); - if(!mac_mode) - SSDK_INFO("mac mode1 doesn't exit!\n"); - else { - cfg->mac_mode1 = be32_to_cpup(mac_mode); - SSDK_INFO("mac mode1 = 0x%x\n", be32_to_cpup(mac_mode)); - ssdk_dt_global.ssdk_dt_switch_nodes[dev_id]->mac_mode1 = cfg->mac_mode1; - } - - mac_mode = of_get_property(switch_node, "switch_mac_mode2", &len); - if(!mac_mode) - SSDK_INFO("mac mode2 doesn't exit!\n"); - else { - cfg->mac_mode2 = be32_to_cpup(mac_mode); - SSDK_INFO("mac mode2 = 0x%x\n", be32_to_cpup(mac_mode)); - ssdk_dt_global.ssdk_dt_switch_nodes[dev_id]->mac_mode2 = cfg->mac_mode2; - } - - return; -} -#ifdef IN_UNIPHY -static void ssdk_dt_parse_uniphy(a_uint32_t dev_id) -{ - struct device_node *uniphy_node = NULL; - a_uint32_t len = 0; - const __be32 *reg_cfg; - ssdk_dt_cfg *cfg; - - /* read uniphy register base and address space */ - uniphy_node = of_find_node_by_name(NULL, "ess-uniphy"); - if (!uniphy_node) - SSDK_INFO("ess-uniphy DT doesn't exist!\n"); - else { - SSDK_INFO("ess-uniphy DT exist!\n"); - cfg = ssdk_dt_global.ssdk_dt_switch_nodes[dev_id]; - reg_cfg = of_get_property(uniphy_node, "reg", &len); - if(!reg_cfg) - SSDK_INFO("uniphy reg address doesn't exist!\n"); - else { - cfg->uniphyreg_base_addr = be32_to_cpup(reg_cfg); - cfg->uniphyreg_size = be32_to_cpup(reg_cfg + 1); - } - if (of_property_read_string(uniphy_node, "uniphy_access_mode", - (const char **)&cfg->uniphy_access_mode)) - SSDK_INFO("uniphy access mode doesn't exist!\n"); - else { - if(!strcmp(cfg->uniphy_access_mode, "local bus")) - cfg->uniphy_reg_access_mode = HSL_REG_LOCAL_BUS; - } - } - - return; -} -#endif -#ifdef HPPE -#ifdef IN_QOS -static void ssdk_dt_parse_l1_scheduler_cfg( - struct device_node *port_node, - a_uint32_t port_id, a_uint32_t dev_id) -{ - struct device_node *scheduler_node; - struct device_node *child; - ssdk_dt_scheduler_cfg *cfg = &(ssdk_dt_global.ssdk_dt_switch_nodes[dev_id]->scheduler_cfg); - a_uint32_t tmp_cfg[4]; - const __be32 *paddr; - a_uint32_t len, i, sp_id; - - scheduler_node = of_find_node_by_name(port_node, "l1scheduler"); - if (!scheduler_node) { - SSDK_ERROR("cannot find l1scheduler node for port\n"); - return; - } - for_each_available_child_of_node(scheduler_node, child) { - paddr = of_get_property(child, "sp", &len); - len /= sizeof(a_uint32_t); - if (!paddr) { - SSDK_ERROR("error reading sp property\n"); - return; - } - if (of_property_read_u32_array(child, - "cfg", tmp_cfg, 4)) { - SSDK_ERROR("error reading cfg property!\n"); - return; - } - for (i = 0; i < len; i++) { - sp_id = be32_to_cpup(paddr+i); - if (sp_id >= SSDK_L1SCHEDULER_CFG_MAX) { - SSDK_ERROR("Invalid parameter for sp(%d)\n", - sp_id); - return; - } - cfg->l1cfg[sp_id].valid = 1; - cfg->l1cfg[sp_id].port_id = port_id; - cfg->l1cfg[sp_id].cpri = tmp_cfg[0]; - cfg->l1cfg[sp_id].cdrr_id = tmp_cfg[1]; - cfg->l1cfg[sp_id].epri = tmp_cfg[2]; - cfg->l1cfg[sp_id].edrr_id = tmp_cfg[3]; - } - } -} - -static void ssdk_dt_parse_l0_queue_cfg( - a_uint32_t dev_id, - a_uint32_t port_id, - struct device_node *node, - a_uint8_t *queue_name, - a_uint8_t *loop_name) -{ - ssdk_dt_scheduler_cfg *cfg = &(ssdk_dt_global.ssdk_dt_switch_nodes[dev_id]->scheduler_cfg); - a_uint32_t tmp_cfg[5]; - const __be32 *paddr; - a_uint32_t len, i, queue_id, pri_loop; - - paddr = of_get_property(node, queue_name, &len); - len /= sizeof(a_uint32_t); - if (!paddr) { - SSDK_ERROR("error reading %s property\n", queue_name); - return; - } - if (of_property_read_u32_array(node, "cfg", tmp_cfg, 5)) { - SSDK_ERROR("error reading cfg property!\n"); - return; - } - if (of_property_read_u32(node, loop_name, &pri_loop)) { - for (i = 0; i < len; i++) { - queue_id = be32_to_cpup(paddr+i); - if (queue_id >= SSDK_L0SCHEDULER_CFG_MAX) { - SSDK_ERROR("Invalid parameter for queue(%d)\n", - queue_id); - return; - } - cfg->l0cfg[queue_id].valid = 1; - cfg->l0cfg[queue_id].port_id = port_id; - cfg->l0cfg[queue_id].sp_id = tmp_cfg[0]; - cfg->l0cfg[queue_id].cpri = tmp_cfg[1]; - cfg->l0cfg[queue_id].cdrr_id = tmp_cfg[2]; - cfg->l0cfg[queue_id].epri = tmp_cfg[3]; - cfg->l0cfg[queue_id].edrr_id = tmp_cfg[4]; - } - } else { - /* should one queue for loop */ - if (len != 1) { - SSDK_ERROR("should one queue for loop!\n"); - return; - } - queue_id = be32_to_cpup(paddr); - if (queue_id >= SSDK_L0SCHEDULER_CFG_MAX) { - SSDK_ERROR("Invalid parameter for queue(%d)\n", - queue_id); - return; - } - for (i = 0; i < pri_loop; i++) { - cfg->l0cfg[queue_id + i].valid = 1; - cfg->l0cfg[queue_id + i].port_id = port_id; - cfg->l0cfg[queue_id + i].sp_id = tmp_cfg[0] + i/SSDK_SP_MAX_PRIORITY; - cfg->l0cfg[queue_id + i].cpri = tmp_cfg[1] + i%SSDK_SP_MAX_PRIORITY; - cfg->l0cfg[queue_id + i].cdrr_id = tmp_cfg[2] + i; - cfg->l0cfg[queue_id + i].epri = tmp_cfg[3] + i%SSDK_SP_MAX_PRIORITY; - cfg->l0cfg[queue_id + i].edrr_id = tmp_cfg[4] + i; - } - } -} - -static void ssdk_dt_parse_l0_scheduler_cfg( - struct device_node *port_node, - a_uint32_t port_id, a_uint32_t dev_id) -{ - struct device_node *scheduler_node; - struct device_node *child; - - scheduler_node = of_find_node_by_name(port_node, "l0scheduler"); - if (!scheduler_node) { - SSDK_ERROR("Can't find l0scheduler node for port\n"); - return; - } - for_each_available_child_of_node(scheduler_node, child) { - ssdk_dt_parse_l0_queue_cfg(dev_id, port_id, child, - "ucast_queue", "ucast_loop_pri"); - ssdk_dt_parse_l0_queue_cfg(dev_id, port_id, child, - "mcast_queue", "mcast_loop_pri"); - } -} - -static void ssdk_dt_parse_scheduler_resource( - struct device_node *port_node, - a_uint32_t dev_id, a_uint32_t port_id) -{ - a_uint32_t uq[2], mq[2], l0sp[2], l0cdrr[2]; - a_uint32_t l0edrr[2], l1cdrr[2], l1edrr[2]; - ssdk_dt_scheduler_cfg *cfg = &(ssdk_dt_global.ssdk_dt_switch_nodes[dev_id]->scheduler_cfg); - - if (of_property_read_u32_array(port_node, "ucast_queue", uq, 2) - || of_property_read_u32_array(port_node, "mcast_queue", mq, 2) - || of_property_read_u32_array(port_node, "l0sp", l0sp, 2) - || of_property_read_u32_array(port_node, "l0cdrr", l0cdrr, 2) - || of_property_read_u32_array(port_node, "l0edrr", l0edrr, 2) - || of_property_read_u32_array(port_node, "l1cdrr", l1cdrr, 2) - || of_property_read_u32_array(port_node, "l1edrr", l1edrr, 2)){ - SSDK_ERROR("error reading port resource scheduler properties\n"); - return; - } - cfg->pool[port_id].ucastq_start = uq[0]; - cfg->pool[port_id].ucastq_end = uq[1]; - cfg->pool[port_id].mcastq_start = mq[0]; - cfg->pool[port_id].mcastq_end = mq[1]; - cfg->pool[port_id].l0sp_start = l0sp[0]; - cfg->pool[port_id].l0sp_end = l0sp[1]; - cfg->pool[port_id].l0cdrr_start = l0cdrr[0]; - cfg->pool[port_id].l0cdrr_end = l0cdrr[1]; - cfg->pool[port_id].l0edrr_start = l0edrr[0]; - cfg->pool[port_id].l0edrr_end = l0edrr[1]; - cfg->pool[port_id].l1cdrr_start = l1cdrr[0]; - cfg->pool[port_id].l1cdrr_end = l1cdrr[1]; - cfg->pool[port_id].l1edrr_start = l1edrr[0]; - cfg->pool[port_id].l1edrr_end = l1edrr[1]; -} - -static void ssdk_dt_parse_scheduler_cfg(a_uint32_t dev_id, struct device_node *switch_node) -{ - struct device_node *scheduler_node; - struct device_node *child; - a_uint32_t port_id; - - scheduler_node = of_find_node_by_name(switch_node, "port_scheduler_resource"); - if (!scheduler_node) { - SSDK_ERROR("cannot find port_scheduler_resource node\n"); - return; - } - for_each_available_child_of_node(scheduler_node, child) { - if (of_property_read_u32(child, "port_id", &port_id)) { - SSDK_ERROR("error reading for port_id property!\n"); - return; - } - if (port_id >= SSDK_MAX_PORT_NUM) { - SSDK_ERROR("invalid parameter for port_id(%d)!\n", port_id); - return; - } - ssdk_dt_parse_scheduler_resource(child, dev_id, port_id); - } - - scheduler_node = of_find_node_by_name(switch_node, "port_scheduler_config"); - if (!scheduler_node) { - SSDK_ERROR("cannot find port_scheduler_config node\n"); - return ; - } - for_each_available_child_of_node(scheduler_node, child) { - if (of_property_read_u32(child, "port_id", &port_id)) { - SSDK_ERROR("error reading for port_id property!\n"); - return; - } - if (port_id >= SSDK_MAX_PORT_NUM) { - SSDK_ERROR("invalid parameter for port_id(%d)!\n", port_id); - return; - } - ssdk_dt_parse_l1_scheduler_cfg(child, port_id, dev_id); - ssdk_dt_parse_l0_scheduler_cfg(child, port_id, dev_id); - } -} -#endif -#endif -static sw_error_t ssdk_dt_parse_phy_info(struct device_node *switch_node, a_uint32_t dev_id, - ssdk_init_cfg *cfg) -{ - struct device_node *phy_info_node, *port_node; - - ssdk_port_phyinfo *port_phyinfo; - a_uint8_t forced_duplex; - a_uint32_t port_id, phy_addr, phy_i2c_addr, forced_speed, len; - const __be32 *paddr; - a_bool_t phy_c45, phy_combo, phy_i2c, phy_forced; - const char *mac_type = NULL; - sw_error_t rv = SW_OK; - struct device_node *mdio_node; - int phy_reset_gpio = 0; - phy_dac_t phy_dac = {0}; - - phy_info_node = of_get_child_by_name(switch_node, "qcom,port_phyinfo"); - if (!phy_info_node) { - SSDK_INFO("qcom,port_phyinfo DT doesn't exist!\n"); - return SW_NOT_FOUND; - } - - for_each_available_child_of_node(phy_info_node, port_node) { - if (of_property_read_u32(port_node, "port_id", &port_id)) - return SW_BAD_VALUE; - - /* initialize phy_addr in case of undefined dts field */ - phy_addr = 0xff; - of_property_read_u32(port_node, "phy_address", &phy_addr); - - if (!cfg->port_cfg.wan_bmp) { - cfg->port_cfg.wan_bmp = BIT(port_id); - } else { - cfg->port_cfg.lan_bmp |= BIT(port_id); - } - - if (!of_property_read_u32(port_node, "forced-speed", &forced_speed) && - !of_property_read_u8(port_node, "forced-duplex", &forced_duplex)) { - phy_forced = A_TRUE; - } else { - phy_forced = A_FALSE; - } - paddr = of_get_property(port_node, "phy_dac", &len); - if(paddr) - { - phy_dac.mdac = be32_to_cpup(paddr); - phy_dac.edac = be32_to_cpup(paddr+1); - hsl_port_phy_dac_set(dev_id, port_id, phy_dac); - } - - phy_c45 = of_property_read_bool(port_node, - "ethernet-phy-ieee802.3-c45"); - phy_combo = of_property_read_bool(port_node, - "ethernet-phy-combo"); - mdio_node = of_parse_phandle(port_node, "mdiobus", 0); - phy_i2c = of_property_read_bool(port_node, "phy-i2c-mode"); - - if (phy_i2c) { - SSDK_INFO("[PORT %d] phy-i2c-mode\n", port_id); - hsl_port_phy_access_type_set(dev_id, port_id, PHY_I2C_ACCESS); - if (of_property_read_u32(port_node, "phy_i2c_address", - &phy_i2c_addr)) { - return SW_BAD_VALUE; - } - /* phy_i2c_address is the i2c slave addr */ - hsl_phy_address_init(dev_id, port_id, phy_i2c_addr); - /* phy_address is the mdio addr, - * which is a fake mdio addr in i2c mode */ - qca_ssdk_phy_mdio_fake_address_set(dev_id, port_id, phy_addr); - } else { - hsl_phy_address_init(dev_id, port_id, phy_addr); - } - - hsl_port_phy_combo_capability_set(dev_id, port_id, phy_combo); - hsl_port_phy_c45_capability_set(dev_id, port_id, phy_c45); - - port_phyinfo = ssdk_port_phyinfo_get(dev_id, port_id); - if (port_phyinfo) { - port_phyinfo->port_id = port_id; - port_phyinfo->phy_addr = phy_addr; - if (phy_c45) { - port_phyinfo->phy_features |= PHY_F_CLAUSE45; - } - - if (phy_combo) { - port_phyinfo->phy_features |= PHY_F_COMBO; - } - - if (phy_i2c) { - port_phyinfo->phy_features |= PHY_F_I2C; - } - - if (phy_forced) { - port_phyinfo->phy_features |= PHY_F_FORCE; - port_phyinfo->port_speed = forced_speed; - port_phyinfo->port_duplex = forced_duplex; - } - - if (!of_property_read_string(port_node, "port_mac_sel", &mac_type)) - { - SSDK_INFO("[PORT %d] port_mac_sel = %s\n", port_id, mac_type); - if (!strncmp("QGMAC_PORT", mac_type, 10)) { - port_phyinfo->phy_features |= PHY_F_QGMAC; - } - else if (!strncmp("XGMAC_PORT", mac_type, 10)) { - port_phyinfo->phy_features |= PHY_F_XGMAC; - } - } - - port_phyinfo->phy_features |= PHY_F_INIT; - - if (mdio_node) - { - port_phyinfo->miibus = of_mdio_find_bus(mdio_node); - phy_reset_gpio = of_get_named_gpio(mdio_node, "phy-reset-gpio", - SSDK_PHY_RESET_GPIO_INDEX); - if(phy_reset_gpio > 0) - { - SSDK_INFO("port%d's phy-reset-gpio is GPIO%d\n", port_id, - phy_reset_gpio); - hsl_port_phy_reset_gpio_set(dev_id, port_id, - (a_uint32_t)phy_reset_gpio); - } - } - } - } - - return rv; -} - -static void ssdk_dt_parse_mdio(a_uint32_t dev_id, struct device_node *switch_node, - ssdk_init_cfg *cfg) -{ - struct device_node *mdio_node = NULL; - struct device_node *child = NULL; - ssdk_port_phyinfo *port_phyinfo; - a_uint32_t len = 0, i = 1; - const __be32 *phy_addr; - const __be32 *c45_phy; - - /* prefer to get phy info from ess-switch node */ - if (SW_OK == ssdk_dt_parse_phy_info(switch_node, dev_id, cfg)) - return; - - mdio_node = of_find_node_by_name(NULL, "mdio"); - - if (!mdio_node) { - SSDK_INFO("mdio DT doesn't exist!\n"); - } - else { - SSDK_INFO("mdio DT exist!\n"); - for_each_available_child_of_node(mdio_node, child) { - phy_addr = of_get_property(child, "reg", &len); - if (phy_addr) { - hsl_phy_address_init(dev_id, i, be32_to_cpup(phy_addr)); - } - - c45_phy = of_get_property(child, "compatible", &len); - if (c45_phy) { - hsl_port_phy_c45_capability_set(dev_id, i, A_TRUE); - } - - port_phyinfo = ssdk_port_phyinfo_get(dev_id, i); - if (port_phyinfo) { - port_phyinfo->port_id = i; - if (phy_addr) { - port_phyinfo->phy_addr = be32_to_cpup(phy_addr); - } - if (c45_phy) { - port_phyinfo->phy_features |= PHY_F_CLAUSE45; - } - - port_phyinfo->phy_features |= PHY_F_INIT; - } - - if (!cfg->port_cfg.wan_bmp) { - cfg->port_cfg.wan_bmp = BIT(i); - } else { - cfg->port_cfg.lan_bmp |= BIT(i); - } - - i++; - if (i >= SW_MAX_NR_PORT) { - break; - } - } - } - return; -} - -static void ssdk_dt_parse_port_bmp(a_uint32_t dev_id, - struct device_node *switch_node, ssdk_init_cfg *cfg) -{ - a_uint32_t portbmp = 0; - - if (of_property_read_u32(switch_node, "switch_cpu_bmp", &cfg->port_cfg.cpu_bmp) - || of_property_read_u32(switch_node, "switch_lan_bmp", &cfg->port_cfg.lan_bmp) - || of_property_read_u32(switch_node, "switch_wan_bmp", &cfg->port_cfg.wan_bmp)) { - SSDK_INFO("port_bmp doesn't exist!\n"); - /* - * the bmp maybe initialized already, so just keep ongoing. - */ - } - - if (!of_property_read_u32(switch_node, "switch_inner_bmp", &cfg->port_cfg.inner_bmp)) { - ssdk_dt_global.ssdk_dt_switch_nodes[dev_id]->port_cfg.inner_bmp = - cfg->port_cfg.inner_bmp; - } - - ssdk_dt_global.ssdk_dt_switch_nodes[dev_id]->port_cfg.cpu_bmp = cfg->port_cfg.cpu_bmp; - ssdk_dt_global.ssdk_dt_switch_nodes[dev_id]->port_cfg.lan_bmp = cfg->port_cfg.lan_bmp; - ssdk_dt_global.ssdk_dt_switch_nodes[dev_id]->port_cfg.wan_bmp = cfg->port_cfg.wan_bmp; - - portbmp = cfg->port_cfg.lan_bmp | cfg->port_cfg.wan_bmp; - qca_ssdk_port_bmp_set(dev_id, portbmp); - - return; -} -#ifdef HPPE -static void ssdk_dt_parse_intf_mac(void) -{ - struct device_node *dp_node = NULL; - a_uint32_t dp = 0; - a_uint8_t *maddr = NULL; - char dp_name[8] = {0}; - - for (dp = 1; dp <= SSDK_MAX_NR_ETH; dp++) { - snprintf(dp_name, sizeof(dp_name), "dp%d", dp); - dp_node = of_find_node_by_name(NULL, dp_name); - if (!dp_node) { - continue; - } - maddr = (a_uint8_t *)of_get_mac_address(dp_node); -#if (LINUX_VERSION_CODE < KERNEL_VERSION(5, 0, 0)) - if (maddr && is_valid_ether_addr(maddr)) { -#else - if (!IS_ERR(maddr) && is_valid_ether_addr(maddr)) { -#endif - ssdk_dt_global.num_intf_mac++; - ether_addr_copy(ssdk_dt_global.intf_mac[dp-1].uc, maddr); - SSDK_INFO("%s MAC %02x:%02x:%02x:%02x:%02x:%02x\n", - dp_name, maddr[0], maddr[1], maddr[2], maddr[3], - maddr[4], maddr[5]); - } - } - return; -} -#endif -#ifdef DESS -static void ssdk_dt_parse_psgmii(ssdk_dt_cfg *ssdk_dt_priv) -{ - - struct device_node *psgmii_node = NULL; - const __be32 *reg_cfg; - a_uint32_t len = 0; - - psgmii_node = of_find_node_by_name(NULL, "ess-psgmii"); - if (!psgmii_node) { - SSDK_ERROR("cannot find ess-psgmii node\n"); - return; - } - - SSDK_INFO("ess-psgmii DT exist!\n"); - reg_cfg = of_get_property(psgmii_node, "reg", &len); - if(!reg_cfg) { - SSDK_ERROR("%s: error reading device node properties for reg\n", - psgmii_node->name); - return; - } - - ssdk_dt_priv->psgmiireg_base_addr = be32_to_cpup(reg_cfg); - ssdk_dt_priv->psgmiireg_size = be32_to_cpup(reg_cfg + 1); - if (of_property_read_string(psgmii_node, "psgmii_access_mode", - (const char **)&ssdk_dt_priv->psgmii_reg_access_str)) { - SSDK_ERROR("%s: error reading properties for psmgii_access_mode\n", - psgmii_node->name); - return; - } - if(!strcmp(ssdk_dt_priv->psgmii_reg_access_str, "local bus")) - ssdk_dt_priv->psgmii_reg_access_mode = HSL_REG_LOCAL_BUS; - - return; -} -#endif -static sw_error_t ssdk_dt_parse_access_mode(struct device_node *switch_node, - ssdk_dt_cfg *ssdk_dt_priv) -{ - const __be32 *reg_cfg; - a_uint32_t len = 0; - - if (of_property_read_string(switch_node, "switch_access_mode", - (const char **)&ssdk_dt_priv->reg_access_mode)) { - SSDK_ERROR("%s: error reading properties for switch_access_mode\n", - switch_node->name); - return SW_BAD_PARAM; - } - - SSDK_INFO("switch_access_mode: %s\n", ssdk_dt_priv->reg_access_mode); - if(!strcmp(ssdk_dt_priv->reg_access_mode, "local bus")) { - ssdk_dt_priv->switch_reg_access_mode = HSL_REG_LOCAL_BUS; - - reg_cfg = of_get_property(switch_node, "reg", &len); - if(!reg_cfg) { - SSDK_ERROR("%s: error reading properties for reg\n", - switch_node->name); - return SW_BAD_PARAM; - } - ssdk_dt_priv->switchreg_base_addr = be32_to_cpup(reg_cfg); - ssdk_dt_priv->switchreg_size = be32_to_cpup(reg_cfg + 1); - - SSDK_INFO("switchreg_base_addr: 0x%x\n", ssdk_dt_priv->switchreg_base_addr); - SSDK_INFO("switchreg_size: 0x%x\n", ssdk_dt_priv->switchreg_size); - } - else { - ssdk_dt_priv->switch_reg_access_mode = HSL_REG_MDIO; - } - - return SW_OK; - -} -#if (defined(DESS) || defined(MP)) -#ifdef IN_LED -static void ssdk_dt_parse_led(struct device_node *switch_node, - ssdk_init_cfg *cfg) -{ - struct device_node *child = NULL; - const __be32 *led_source, *led_number; - a_uint8_t *led_str; - a_uint32_t len = 0, i = 0; - - for_each_available_child_of_node(switch_node, child) { - - led_source = of_get_property(child, "source", &len); - if (!led_source) { - continue; - } - cfg->led_source_cfg[i].led_source_id = be32_to_cpup(led_source); - led_number = of_get_property(child, "led", &len); - if (led_number) - cfg->led_source_cfg[i].led_num = be32_to_cpup(led_number); - if (!of_property_read_string(child, "mode", (const char **)&led_str)) { - if (!strcmp(led_str, "normal")) - cfg->led_source_cfg[i].led_pattern.mode = LED_PATTERN_MAP_EN; - if (!strcmp(led_str, "on")) - cfg->led_source_cfg[i].led_pattern.mode = LED_ALWAYS_ON; - if (!strcmp(led_str, "blink")) - cfg->led_source_cfg[i].led_pattern.mode = LED_ALWAYS_BLINK; - if (!strcmp(led_str, "off")) - cfg->led_source_cfg[i].led_pattern.mode = LED_ALWAYS_OFF; - } - if (!of_property_read_string(child, "speed", (const char **)&led_str)) { - if (!strcmp(led_str, "10M")) - cfg->led_source_cfg[i].led_pattern.map = LED_MAP_10M_SPEED; - if (!strcmp(led_str, "100M")) - cfg->led_source_cfg[i].led_pattern.map = LED_MAP_100M_SPEED; - if (!strcmp(led_str, "1000M")) - cfg->led_source_cfg[i].led_pattern.map = LED_MAP_1000M_SPEED; - if (!strcmp(led_str, "2500M")) - cfg->led_source_cfg[i].led_pattern.map = LED_MAP_2500M_SPEED; - if (!strcmp(led_str, "all")) - cfg->led_source_cfg[i].led_pattern.map = LED_MAP_ALL_SPEED; - } - if (!of_property_read_string(child, "freq", (const char **)&led_str)) { - if (!strcmp(led_str, "2Hz")) - cfg->led_source_cfg[i].led_pattern.freq = LED_BLINK_2HZ; - if (!strcmp(led_str, "4Hz")) - cfg->led_source_cfg[i].led_pattern.freq = LED_BLINK_4HZ; - if (!strcmp(led_str, "8Hz")) - cfg->led_source_cfg[i].led_pattern.freq = LED_BLINK_8HZ; - if (!strcmp(led_str, "auto")) - cfg->led_source_cfg[i].led_pattern.freq = LED_BLINK_TXRX; - } - if (!of_property_read_string(child, "active", (const char **)&led_str)) { - if (!strcmp(led_str, "high")) - cfg->led_source_cfg[i].led_pattern.map |= BIT(LED_ACTIVE_HIGH); - } - if (!of_property_read_string(child, "blink_en", (const char **)&led_str)) { - if (!strcmp(led_str, "disable")) - cfg->led_source_cfg[i].led_pattern.map &= ~(BIT(RX_TRAFFIC_BLINK_EN)| - BIT(TX_TRAFFIC_BLINK_EN)); - } - i++; - } - cfg->led_source_num = i; - SSDK_INFO("current dts led_source_num is %d\n",cfg->led_source_num); - - return; -} -#endif -#endif -static sw_error_t ssdk_dt_get_switch_node(struct device_node **switch_node, - a_uint32_t num) -{ - struct device_node *switch_instance = NULL; - char ess_switch_name[64] = {0}; - - if (num == 0) - snprintf(ess_switch_name, sizeof(ess_switch_name), "ess-switch"); - else - snprintf(ess_switch_name, sizeof(ess_switch_name), "ess-switch%d", num); - - /* - * Get reference to ESS SWITCH device node from ess-instance node firstly. - */ - switch_instance = of_find_node_by_name(NULL, "ess-instance"); - *switch_node = of_find_node_by_name(switch_instance, ess_switch_name); - if (!*switch_node) { - SSDK_WARN("cannot find ess-switch node\n"); - return SW_BAD_PARAM; - } - - SSDK_INFO("ess-switch DT exist!\n"); - - if (!of_device_is_available(*switch_node)) - { - SSDK_WARN("ess-switch node[%s] is disabled\n", ess_switch_name); - return SW_DISABLE; - } - - return SW_OK; -} - -sw_error_t ssdk_dt_parse(ssdk_init_cfg *cfg, a_uint32_t num, a_uint32_t *dev_id) -{ - sw_error_t rv = SW_OK; - struct device_node *switch_node = NULL; - ssdk_dt_cfg *ssdk_dt_priv = NULL; - a_uint32_t len = 0; - const __be32 *device_id; - - rv = ssdk_dt_get_switch_node(&switch_node, num); - SW_RTN_ON_ERROR(rv); - - device_id = of_get_property(switch_node, "device_id", &len); - if(!device_id) - *dev_id = 0; - else - *dev_id = be32_to_cpup(device_id); - - ssdk_dt_priv = ssdk_dt_global.ssdk_dt_switch_nodes[*dev_id]; - ssdk_dt_priv->device_id = *dev_id; - ssdk_dt_priv->ess_switch_flag = A_TRUE; - ssdk_dt_priv->of_node = switch_node; - ssdk_dt_priv->ess_clk= ERR_PTR(-ENOENT); - ssdk_dt_priv->cmnblk_clk = ERR_PTR(-ENOENT); - - if(of_property_read_bool(switch_node,"qcom,emulation")){ - ssdk_dt_priv->is_emulation = A_TRUE; - SSDK_INFO("RUMI emulation\n"); - } - /* parse common dts info */ - rv = ssdk_dt_parse_access_mode(switch_node, ssdk_dt_priv); - SW_RTN_ON_ERROR(rv); - ssdk_dt_parse_mac_mode(*dev_id, switch_node, cfg); - ssdk_dt_parse_mdio(*dev_id, switch_node, cfg); - ssdk_dt_parse_port_bmp(*dev_id, switch_node, cfg); - - if (of_device_is_compatible(switch_node, "qcom,ess-switch")) { - /* DESS chip */ -#ifdef DESS -#ifdef IN_LED - ssdk_dt_parse_led(switch_node, cfg); -#endif - ssdk_dt_parse_psgmii(ssdk_dt_priv); - - ssdk_dt_priv->ess_clk = of_clk_get_by_name(switch_node, "ess_clk"); - if (IS_ERR(ssdk_dt_priv->ess_clk)) - SSDK_INFO("ess_clk doesn't exist!\n"); -#endif - } - else if (of_device_is_compatible(switch_node, "qcom,ess-switch-ipq807x") || - of_device_is_compatible(switch_node, "qcom,ess-switch-ipq60xx")) { - /* HPPE chip */ -#ifdef HPPE - a_uint32_t mode = 0; -#ifdef IN_UNIPHY - ssdk_dt_parse_uniphy(*dev_id); -#endif -#ifdef IN_QOS - ssdk_dt_parse_scheduler_cfg(*dev_id, switch_node); -#endif - ssdk_dt_parse_intf_mac(); - - ssdk_dt_priv->cmnblk_clk = of_clk_get_by_name(switch_node, "cmn_ahb_clk"); - if (!of_property_read_u32(switch_node, "tm_tick_mode", &mode)) - ssdk_dt_priv->tm_tick_mode = mode; -#endif - } - else if (of_device_is_compatible(switch_node, "qcom,ess-switch-ipq50xx")) { -#ifdef MP - ssdk_dt_priv->emu_chip_ver = MP_GEPHY; -#ifdef IN_UNIPHY - ssdk_dt_parse_uniphy(*dev_id); -#endif -#ifdef IN_LED - ssdk_dt_parse_led(switch_node, cfg); -#endif - ssdk_dt_priv->cmnblk_clk = of_clk_get_by_name(switch_node, "cmn_ahb_clk"); -#endif - } - else if (of_device_is_compatible(switch_node, "qcom,ess-switch-qca83xx")) { - /* s17/s17c chip */ - SSDK_INFO("switch node is qca83xx!\n"); - } - else { - SSDK_WARN("invalid compatible property\n"); - } - - return SW_OK; -} - -static a_uint32_t ssdk_get_switch_port_nums(a_uint32_t dev_id) -{ - struct device_node *child, *mdio_np, *port_np, *switch_np, *switch_instance; - a_uint32_t port_count = 0, switch_id = 0; - - switch_instance = of_find_node_by_name(NULL, "ess-instance"); - if (switch_instance) { /* multi ess-switch */ - for_each_available_child_of_node(switch_instance, switch_np) { - if (of_property_read_u32(switch_np, "device_id", &switch_id) < 0) { - switch_id = 0; - } - if (switch_id == dev_id) { - port_np = of_find_node_by_name(switch_np, "qcom,port_phyinfo"); - if (port_np) { - for_each_available_child_of_node(port_np, child) - port_count++; - break; - } - } - } - } else { /* single ess-switch */ - switch_np = of_find_node_by_name(NULL, "ess-switch"); - if (switch_np && dev_id == 0) { - port_np = of_find_node_by_name(switch_np, "qcom,port_phyinfo"); - if (port_np) { - for_each_available_child_of_node(port_np, child) - port_count++; - } else { - mdio_np = of_find_node_by_name(NULL, "mido"); - if (mdio_np) { - for_each_available_child_of_node(mdio_np, child) - port_count++; - } - } - } - } - - return port_count; -} -#endif -#endif - -int ssdk_switch_device_num_init(void) -{ - struct device_node *switch_instance = NULL; - a_uint32_t len = 0, port_n = 0; - const __be32 *num_devices; - a_uint32_t dev_num = 1, dev_id = 0; - - switch_instance = of_find_node_by_name(NULL, "ess-instance"); - if (switch_instance) { - num_devices = of_get_property(switch_instance, "num_devices", &len); - if (num_devices) - dev_num = be32_to_cpup(num_devices); - } - - ssdk_dt_global.ssdk_dt_switch_nodes = kzalloc(dev_num * sizeof(ssdk_dt_cfg *), GFP_KERNEL); - if (ssdk_dt_global.ssdk_dt_switch_nodes == NULL) { - return -ENOMEM; - } - - for (dev_id = 0; dev_id < dev_num; dev_id++) { - ssdk_dt_global.ssdk_dt_switch_nodes[dev_id] = kzalloc(sizeof(ssdk_dt_cfg), - GFP_KERNEL); - if (ssdk_dt_global.ssdk_dt_switch_nodes[dev_id] == NULL) { - return -ENOMEM; - } - -#ifndef BOARD_AR71XX -#if defined(CONFIG_OF) && (LINUX_VERSION_CODE >= KERNEL_VERSION(3,14,0)) - port_n = ssdk_get_switch_port_nums(dev_id); -#endif -#endif - if (!port_n) { - port_n = SW_MAX_NR_PORT; - } - ssdk_dt_global.ssdk_dt_switch_nodes[dev_id]->port_phyinfo = kzalloc(port_n * - sizeof(ssdk_port_phyinfo), GFP_KERNEL); - if (!ssdk_dt_global.ssdk_dt_switch_nodes[dev_id]->port_phyinfo) { - return -ENOMEM; - } - ssdk_dt_global.ssdk_dt_switch_nodes[dev_id]->phyinfo_num = port_n; - - ssdk_dt_global.ssdk_dt_switch_nodes[dev_id]->switch_reg_access_mode = HSL_REG_MDIO; - ssdk_dt_global.ssdk_dt_switch_nodes[dev_id]->psgmii_reg_access_mode = HSL_REG_MDIO; - ssdk_dt_global.ssdk_dt_switch_nodes[dev_id]->ess_switch_flag = A_FALSE; - } - - ssdk_dt_global.num_devices = dev_num; - SSDK_INFO("ess-switch dts node number: %d\n", dev_num); - - return 0; -} - -void ssdk_switch_device_num_exit(void) -{ - a_uint32_t dev_id = 0; - - for (dev_id = 0; dev_id < ssdk_dt_global.num_devices; dev_id++) { - if (ssdk_dt_global.ssdk_dt_switch_nodes[dev_id]->port_phyinfo) { - kfree(ssdk_dt_global.ssdk_dt_switch_nodes[dev_id]->port_phyinfo); - ssdk_dt_global.ssdk_dt_switch_nodes[dev_id]->port_phyinfo = NULL; - } - - if (ssdk_dt_global.ssdk_dt_switch_nodes[dev_id]) - kfree(ssdk_dt_global.ssdk_dt_switch_nodes[dev_id]); - ssdk_dt_global.ssdk_dt_switch_nodes[dev_id] = NULL; - } - - if (ssdk_dt_global.ssdk_dt_switch_nodes) - kfree(ssdk_dt_global.ssdk_dt_switch_nodes); - ssdk_dt_global.ssdk_dt_switch_nodes = NULL; - - ssdk_dt_global.num_devices = 0; -} - -a_uint32_t ssdk_switch_device_num_get(void) -{ - return ssdk_dt_global.num_devices; -} - -a_bool_t ssdk_is_emulation(a_uint32_t dev_id) -{ - return ssdk_dt_global.ssdk_dt_switch_nodes[dev_id]->is_emulation; -} -a_uint32_t ssdk_emu_chip_ver_get(a_uint32_t dev_id) -{ - return ssdk_dt_global.ssdk_dt_switch_nodes[dev_id]->emu_chip_ver; -} - diff --git a/feeds/ipq807x/qca-ssdk/src/src/init/ssdk_hppe.c b/feeds/ipq807x/qca-ssdk/src/src/init/ssdk_hppe.c deleted file mode 100755 index 3c0849684..000000000 --- a/feeds/ipq807x/qca-ssdk/src/src/init/ssdk_hppe.c +++ /dev/null @@ -1,1286 +0,0 @@ -/* - * Copyright (c) 2012, 2014-2019, 2021, The Linux Foundation. All rights reserved. - * Permission to use, copy, modify, and/or distribute this software for - * any purpose with or without fee is hereby granted, provided that the - * above copyright notice and this permission notice appear in all copies. - * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES - * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR - * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES - * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN - * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT - * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. - */ - -#include "ssdk_init.h" -#include "ssdk_dts.h" -#include "adpt.h" -#include "adpt_hppe.h" -#include "fal.h" -#include "ref_vsi.h" -#include "ssdk_clk.h" -#include "hsl_phy.h" - -#if defined(IN_VSI) -static sw_error_t qca_hppe_vsi_hw_init(a_uint32_t dev_id) -{ - return ppe_vsi_init(dev_id); -} -#endif - -#if defined(IN_FDB) -static sw_error_t qca_hppe_fdb_hw_init(a_uint32_t dev_id) -{ - a_uint32_t port = 0; - adpt_api_t *p_api; - - SW_RTN_ON_NULL(p_api = adpt_api_ptr_get(dev_id)); - SW_RTN_ON_NULL(p_api->adpt_port_bridge_txmac_set); - - for(port = SSDK_PHYSICAL_PORT0; port <= SSDK_PHYSICAL_PORT7; port++) { - if(port == SSDK_PHYSICAL_PORT0) { - fal_fdb_port_learning_ctrl_set(dev_id, port, A_FALSE, FAL_MAC_FRWRD); - fal_fdb_port_stamove_ctrl_set(dev_id, port, A_FALSE, FAL_MAC_FRWRD); - } else { - fal_fdb_port_learning_ctrl_set(dev_id, port, A_TRUE, FAL_MAC_FRWRD); - fal_fdb_port_stamove_ctrl_set(dev_id, port, A_TRUE, FAL_MAC_FRWRD); - } - fal_portvlan_member_update(dev_id, port, 0x7f); - if (port == SSDK_PHYSICAL_PORT0 || port == SSDK_PHYSICAL_PORT7) { - p_api->adpt_port_bridge_txmac_set(dev_id, port, A_TRUE); - } else { - p_api->adpt_port_bridge_txmac_set(dev_id, port, A_FALSE); - } - fal_port_promisc_mode_set(dev_id, port, A_TRUE); - } - - fal_fdb_aging_ctrl_set(dev_id, A_TRUE); - fal_fdb_learning_ctrl_set(dev_id, A_TRUE); - - return SW_OK; -} -#endif - -#if defined(IN_CTRLPKT) -#define RFDB_PROFILE_ID_STP 31 -static sw_error_t qca_hppe_ctlpkt_hw_init(a_uint32_t dev_id) -{ - fal_mac_addr_t mcast_mac_addr; - fal_ctrlpkt_action_t ctrlpkt_action; - fal_ctrlpkt_profile_t ctrlpkt_profile; - sw_error_t rv = SW_OK; - - memset(&ctrlpkt_action, 0, sizeof(ctrlpkt_action)); - memset(&ctrlpkt_profile, 0, sizeof(ctrlpkt_profile)); - memset(&mcast_mac_addr, 0, sizeof(mcast_mac_addr)); - - mcast_mac_addr.uc[0] = 0x01; - mcast_mac_addr.uc[1] = 0x80; - mcast_mac_addr.uc[2] = 0xc2; - rv = fal_mgmtctrl_rfdb_profile_set(dev_id, RFDB_PROFILE_ID_STP, - &mcast_mac_addr); - SW_RTN_ON_ERROR(rv); - - ctrlpkt_action.action = FAL_MAC_RDT_TO_CPU; - ctrlpkt_action.in_stp_bypass = A_TRUE; - - ctrlpkt_profile.action = ctrlpkt_action; - ctrlpkt_profile.port_map = qca_ssdk_port_bmp_get(dev_id); - ctrlpkt_profile.rfdb_profile_bitmap = (1 << RFDB_PROFILE_ID_STP); - rv = fal_mgmtctrl_ctrlpkt_profile_add(dev_id, &ctrlpkt_profile); - - return rv; -} -#endif - -#if defined(IN_PORTCONTROL) -static sw_error_t -qca_hppe_portctrl_hw_init(a_uint32_t dev_id) -{ - a_uint32_t i = 0; - a_uint32_t port_max = SSDK_PHYSICAL_PORT7; -#if defined(CPPE) - fal_loopback_config_t loopback_cfg; -#endif - - if(adpt_hppe_chip_revision_get(dev_id) == CPPE_REVISION) { - SSDK_INFO("Cypress PPE port initializing\n"); - port_max = SSDK_PHYSICAL_PORT6; - } else { - SSDK_INFO("Hawkeye PPE port initializing\n"); - port_max = SSDK_PHYSICAL_PORT7; - } - for(i = SSDK_PHYSICAL_PORT1; i < port_max; i++) { - qca_hppe_port_mac_type_set(dev_id, i, PORT_GMAC_TYPE); - fal_port_txmac_status_set (dev_id, i, A_FALSE); - fal_port_rxmac_status_set (dev_id, i, A_FALSE); - fal_port_rxfc_status_set(dev_id, i, A_FALSE); - fal_port_txfc_status_set(dev_id, i, A_FALSE); - fal_port_max_frame_size_set(dev_id, i, SSDK_MAX_FRAME_SIZE); - } - - for(i = SSDK_PHYSICAL_PORT5; i < port_max; i++) { - qca_hppe_port_mac_type_set(dev_id, i, PORT_XGMAC_TYPE); - fal_port_txmac_status_set (dev_id, i, A_FALSE); - fal_port_rxmac_status_set (dev_id, i, A_FALSE); - fal_port_rxfc_status_set(dev_id, i, A_FALSE); - fal_port_txfc_status_set(dev_id, i, A_FALSE); - fal_port_max_frame_size_set(dev_id, i, SSDK_MAX_FRAME_SIZE); - } - -#if defined(CPPE) - if (adpt_hppe_chip_revision_get(dev_id) == CPPE_REVISION) { - loopback_cfg.enable = A_TRUE; - loopback_cfg.crc_stripped = A_TRUE; - loopback_cfg.loopback_rate = FAL_DEFAULT_LOOPBACK_RATE; /* Mpps */ - fal_switch_port_loopback_set(dev_id, SSDK_PHYSICAL_PORT6, - &loopback_cfg); - fal_port_max_frame_size_set(dev_id, SSDK_PHYSICAL_PORT6, - SSDK_MAX_FRAME_SIZE); - } -#endif - return SW_OK; -} -#endif - -#if defined(IN_POLICER) -static sw_error_t -qca_hppe_policer_hw_init(a_uint32_t dev_id) -{ - a_uint32_t i = 0; - fal_policer_frame_type_t frame_type; - - fal_policer_timeslot_set(dev_id, HPPE_POLICER_TIMESLOT_DFT); - - for (i = SSDK_PHYSICAL_PORT0; i <= SSDK_PHYSICAL_PORT7; i++) { - fal_port_policer_compensation_byte_set(dev_id, i, 4); - } - - /* bypass policer for dropped frame */ - frame_type = FAL_FRAME_DROPPED; - fal_policer_bypass_en_set(dev_id, frame_type, A_TRUE); - - return SW_OK; -} -#endif - -#if defined(IN_SHAPER) -static sw_error_t -qca_hppe_shaper_hw_init(a_uint32_t dev_id) -{ - fal_shaper_token_number_t port_token_number, queue_token_number; - fal_shaper_token_number_t flow_token_number; - a_uint32_t i = 0; - - port_token_number.c_token_number_negative_en = A_FALSE; - port_token_number.c_token_number = HPPE_MAX_C_TOKEN_NUM; - queue_token_number.c_token_number_negative_en = A_FALSE; - queue_token_number.c_token_number = HPPE_MAX_C_TOKEN_NUM; - queue_token_number.e_token_number_negative_en = A_FALSE; - queue_token_number.e_token_number = HPPE_MAX_E_TOKEN_NUM; - flow_token_number.c_token_number_negative_en = A_FALSE; - flow_token_number.c_token_number = HPPE_MAX_C_TOKEN_NUM; - flow_token_number.e_token_number_negative_en = A_FALSE; - flow_token_number.e_token_number = HPPE_MAX_E_TOKEN_NUM; - - for (i = SSDK_PHYSICAL_PORT0; i <= SSDK_PHYSICAL_PORT7; i++) { - fal_port_shaper_token_number_set(dev_id, i, &port_token_number); - } - - for(i = 0; i < SSDK_L0SCHEDULER_CFG_MAX; i ++) { - fal_queue_shaper_token_number_set(dev_id, i, &queue_token_number); - } - - for(i = 0; i < SSDK_L1SCHEDULER_CFG_MAX; i ++) { - fal_flow_shaper_token_number_set(dev_id, i, &flow_token_number); - } - - fal_port_shaper_timeslot_set(dev_id, HPPE_PORT_SHAPER_TIMESLOT_DFT); - fal_flow_shaper_timeslot_set(dev_id, HPPE_FLOW_SHAPER_TIMESLOT_DFT); - fal_queue_shaper_timeslot_set(dev_id, HPPE_QUEUE_SHAPER_TIMESLOT_DFT); - fal_shaper_ipg_preamble_length_set(dev_id, - HPPE_SHAPER_IPG_PREAMBLE_LEN_DFT); - - return SW_OK; -} -#endif - -#if defined(IN_PORTVLAN) -static sw_error_t -qca_hppe_portvlan_hw_init(a_uint32_t dev_id) -{ - a_uint32_t port_id = 0, vsi_idx = 0; - fal_global_qinq_mode_t global_qinq_mode; - fal_port_qinq_role_t port_qinq_role; - fal_tpid_t in_eg_tpid; - fal_vlantag_egress_mode_t vlantag_eg_mode; - - /* configure ingress/egress global QinQ mode as ctag/ctag */ - global_qinq_mode.mask = 0x3; - global_qinq_mode.ingress_mode = FAL_QINQ_CTAG_MODE; - global_qinq_mode.egress_mode = FAL_QINQ_CTAG_MODE; - fal_global_qinq_mode_set(dev_id, &global_qinq_mode); - - /* configure port0, port7 ingress/egress QinQ role as core/core */ - port_qinq_role.mask = 0x3; - port_qinq_role.ingress_port_role = FAL_QINQ_CORE_PORT; - port_qinq_role.egress_port_role = FAL_QINQ_CORE_PORT; - fal_port_qinq_mode_set(dev_id, SSDK_PHYSICAL_PORT0, &port_qinq_role); - fal_port_qinq_mode_set(dev_id, SSDK_PHYSICAL_PORT7, &port_qinq_role); - /* configure port1 - port6 ingress/egress QinQ role as edge/edge */ - port_qinq_role.mask = 0x3; - port_qinq_role.ingress_port_role = FAL_QINQ_EDGE_PORT; - port_qinq_role.egress_port_role = FAL_QINQ_EDGE_PORT; - for (port_id = SSDK_PHYSICAL_PORT1; port_id <= SSDK_PHYSICAL_PORT6; - port_id++) { - fal_port_qinq_mode_set(dev_id, port_id, &port_qinq_role); - } - - /* configure ingress and egress stpid/ctpid as 0x88a8/0x8100 */ - in_eg_tpid.mask = 0x3; - in_eg_tpid.ctpid = FAL_DEF_VLAN_CTPID; - in_eg_tpid.stpid = FAL_DEF_VLAN_STPID; - fal_ingress_tpid_set(dev_id, &in_eg_tpid); - fal_egress_tpid_set(dev_id, &in_eg_tpid); - - /* configure the port0 - port7 of vsi0 - vsi31 to unmodified */ - for (vsi_idx = 0; vsi_idx <= FAL_VSI_MAX; vsi_idx++) { - for (port_id = SSDK_PHYSICAL_PORT0; - port_id <= SSDK_PHYSICAL_PORT7; port_id++) { - fal_port_vsi_egmode_set(dev_id, vsi_idx, - port_id, FAL_EG_UNMODIFIED); - } - } - - vlantag_eg_mode.mask = 0x3; - vlantag_eg_mode.stag_mode = FAL_EG_UNTOUCHED; - vlantag_eg_mode.ctag_mode = FAL_EG_UNTOUCHED; - /*stag/ctag egress mode as untouched/untouched*/ - fal_port_vlantag_egmode_set(dev_id, SSDK_PHYSICAL_PORT0, - &vlantag_eg_mode); - fal_port_vlantag_egmode_set(dev_id, SSDK_PHYSICAL_PORT7, - &vlantag_eg_mode); - /*vsi tag mode control to disable*/ - fal_port_vlantag_vsi_egmode_enable(dev_id, SSDK_PHYSICAL_PORT0, - A_FALSE); - fal_port_vlantag_vsi_egmode_enable(dev_id, SSDK_PHYSICAL_PORT7, - A_FALSE); - /*ingress vlan translation mismatched command as forward*/ - fal_port_vlan_xlt_miss_cmd_set(dev_id, SSDK_PHYSICAL_PORT0, - FAL_MAC_FRWRD); - - vlantag_eg_mode.stag_mode = FAL_EG_UNMODIFIED; - vlantag_eg_mode.ctag_mode = FAL_EG_UNMODIFIED; - for (port_id = SSDK_PHYSICAL_PORT1; port_id <= SSDK_PHYSICAL_PORT6; - port_id++) { - /*ingress vlan translation mismatched command as forward*/ - fal_port_vlan_xlt_miss_cmd_set(dev_id, port_id, FAL_MAC_FRWRD); - /*vsi tag mode control to enable*/ - fal_port_vlantag_vsi_egmode_enable(dev_id, port_id, A_TRUE); - /*stag/ctag egress mode as unmodified/unmodified*/ - fal_port_vlantag_egmode_set(dev_id, port_id, &vlantag_eg_mode); - } - - return SW_OK; -} -#endif - -#if defined(IN_BM) && defined(IN_QOS) -fal_port_scheduler_cfg_t port_scheduler0_tbl[] = { - {0xee, 6, 0}, - {0xde, 4, 5}, - {0x9f, 0, 6}, - {0xbe, 5, 0}, - {0x7e, 6, 7}, - {0x5f, 0, 5}, - {0x9f, 7, 6}, - {0xbe, 5, 0}, - {0xfc, 6, 1}, - {0xdd, 0, 5}, - {0xde, 1, 0}, - {0xbe, 5, 6}, - {0xbb, 0, 2}, - {0xdb, 6, 5}, - {0xde, 2, 0}, - {0xbe, 5, 6}, - {0x3f, 0, 7}, - {0x7e, 6, 0}, - {0xde, 7, 5}, - {0x9f, 0, 6}, - {0xb7, 5, 3}, - {0xf6, 6, 0}, - {0xde, 3, 5}, - {0x9f, 0, 6}, - {0xbe, 5, 0}, - {0xee, 6, 4}, - {0xcf, 0, 5}, - {0x9f, 4, 6}, - {0xbe, 5, 0}, - {0x7e, 6, 7}, - {0x5f, 0, 5}, - {0xde, 7, 0}, - {0xbe, 5, 6}, - {0xbd, 0, 1}, - {0xdd, 6, 5}, - {0xde, 1, 0}, - {0xbe, 5, 6}, - {0xbb, 0, 2}, - {0xfa, 6, 0}, - {0xde, 2, 5}, - {0x9f, 0, 6}, - {0x3f, 5, 7}, - {0x7e, 6, 0}, - {0xde, 7, 5}, - {0x9f, 0, 6}, - {0xb7, 5, 3}, - {0xf6, 6, 0}, - {0xde, 3, 5}, - {0x9f, 0, 6}, - {0xaf, 5, 4}, -}; - -fal_port_scheduler_cfg_t port_scheduler1_tbl[] = { - {0x30, 5, 6}, - {0x30, 4, 0}, - {0x30, 5, 6}, - {0x11, 0, 5}, - {0x50, 6, 0}, - {0x30, 5, 6}, - {0x21, 0, 4}, - {0x21, 5, 6}, - {0x30, 4, 0}, - {0x50, 6, 5}, - {0x11, 0, 6}, - {0x30, 5, 0}, - {0x30, 4, 6}, - {0x11, 0, 5}, - {0x50, 6, 0}, - {0x30, 5, 6}, - {0x11, 0, 5}, - {0x11, 4, 6}, - {0x30, 5, 0}, - {0x50, 6, 5}, - {0x11, 0, 6}, - {0x30, 5, 0}, - {0x30, 4, 6}, - {0x11, 0, 5}, - {0x50, 6, 0}, -}; - -fal_port_scheduler_cfg_t cppe_port_scheduler0_tbl[] = { - {0xb7, 0, 6}, - {0xbe, 3, 0}, - {0xde, 6, 5}, - {0xdd, 0, 1}, - {0xbd, 5, 6}, - {0xbe, 1, 0}, - {0xee, 6, 4}, - {0xcf, 0, 5}, - {0x9f, 4, 6}, - {0xbe, 5, 0}, - {0x7e, 6, 7}, - {0x5f, 0, 5}, - {0x9f, 7, 6}, - {0xbe, 5, 0}, - {0xfa, 6, 2}, - {0xbb, 0, 6}, - {0x9f, 2, 5}, - {0xcf, 6, 4}, - {0xee, 5, 0}, - {0xbe, 4, 6}, - {0x3f, 0, 7}, - {0x5f, 6, 5}, - {0xde, 7, 0}, - {0xbe, 5, 6}, - {0xb7, 0, 3}, - {0xe7, 6, 4}, - {0xee, 3, 0}, - {0xbe, 4, 6}, - {0x9f, 0, 5}, - {0xdd, 6, 1}, - {0xfc, 5, 0}, - {0xbe, 1, 6}, - {0x9f, 0, 5}, - {0x5f, 6, 7}, - {0x7e, 5, 0}, - {0xbe, 7, 6}, - {0xaf, 0, 4}, - {0xcf, 6, 5}, - {0x9f, 4, 6}, - {0xbe, 5, 0}, - {0xfa, 6, 2}, - {0xdb, 0, 5}, - {0x9f, 2, 6}, - {0xbe, 5, 0}, - {0x7e, 6, 7}, - {0x6f, 0, 4}, - {0xaf, 7, 6}, - {0x9f, 4, 5}, - {0xde, 6, 0}, - {0xf6, 5, 3}, -}; - -fal_port_tdm_tick_cfg_t port_tdm0_tbl[] = { - {1, FAL_PORT_TDB_DIR_INGRESS, 0}, - {1, FAL_PORT_TDB_DIR_EGRESS, 5}, - {1, FAL_PORT_TDB_DIR_INGRESS, 5}, - {1, FAL_PORT_TDB_DIR_EGRESS, 7}, - {1, FAL_PORT_TDB_DIR_INGRESS, 1}, - {1, FAL_PORT_TDB_DIR_EGRESS, 6}, - {1, FAL_PORT_TDB_DIR_INGRESS, 6}, - {1, FAL_PORT_TDB_DIR_EGRESS, 0}, - {1, FAL_PORT_TDB_DIR_INGRESS, 0}, - {1, FAL_PORT_TDB_DIR_EGRESS, 7}, - {1, FAL_PORT_TDB_DIR_INGRESS, 7}, - {1, FAL_PORT_TDB_DIR_EGRESS, 5}, - {1, FAL_PORT_TDB_DIR_INGRESS, 5}, - {1, FAL_PORT_TDB_DIR_EGRESS, 0}, - {1, FAL_PORT_TDB_DIR_INGRESS, 6}, - {1, FAL_PORT_TDB_DIR_EGRESS, 6}, - {1, FAL_PORT_TDB_DIR_INGRESS, 0}, - {1, FAL_PORT_TDB_DIR_EGRESS, 3}, - {1, FAL_PORT_TDB_DIR_INGRESS, 2}, - {1, FAL_PORT_TDB_DIR_EGRESS, 7}, - {1, FAL_PORT_TDB_DIR_INGRESS, 7}, - {1, FAL_PORT_TDB_DIR_EGRESS, 5}, - {1, FAL_PORT_TDB_DIR_INGRESS, 5}, - {1, FAL_PORT_TDB_DIR_EGRESS, 0}, - {1, FAL_PORT_TDB_DIR_INGRESS, 0}, - {1, FAL_PORT_TDB_DIR_EGRESS, 6}, - {1, FAL_PORT_TDB_DIR_INGRESS, 6}, - {1, FAL_PORT_TDB_DIR_EGRESS, 0}, - {1, FAL_PORT_TDB_DIR_INGRESS, 7}, - {1, FAL_PORT_TDB_DIR_EGRESS, 7}, - {1, FAL_PORT_TDB_DIR_INGRESS, 5}, - {1, FAL_PORT_TDB_DIR_EGRESS, 5}, - {1, FAL_PORT_TDB_DIR_INGRESS, 0}, - {1, FAL_PORT_TDB_DIR_EGRESS, 0}, - {1, FAL_PORT_TDB_DIR_INGRESS, 6}, - {1, FAL_PORT_TDB_DIR_EGRESS, 6}, - {1, FAL_PORT_TDB_DIR_INGRESS, 0}, - {1, FAL_PORT_TDB_DIR_EGRESS, 0}, - {1, FAL_PORT_TDB_DIR_INGRESS, 7}, - {1, FAL_PORT_TDB_DIR_EGRESS, 7}, - {1, FAL_PORT_TDB_DIR_INGRESS, 0}, - {1, FAL_PORT_TDB_DIR_EGRESS, 5}, - {1, FAL_PORT_TDB_DIR_INGRESS, 5}, - {1, FAL_PORT_TDB_DIR_EGRESS, 4}, - {1, FAL_PORT_TDB_DIR_INGRESS, 6}, - {1, FAL_PORT_TDB_DIR_EGRESS, 6}, - {1, FAL_PORT_TDB_DIR_INGRESS, 7}, - {1, FAL_PORT_TDB_DIR_EGRESS, 0}, - {1, FAL_PORT_TDB_DIR_INGRESS, 0}, - {1, FAL_PORT_TDB_DIR_EGRESS, 7}, - {1, FAL_PORT_TDB_DIR_INGRESS, 4}, - {1, FAL_PORT_TDB_DIR_EGRESS, 5}, - {1, FAL_PORT_TDB_DIR_INGRESS, 5}, - {1, FAL_PORT_TDB_DIR_EGRESS, 0}, - {1, FAL_PORT_TDB_DIR_INGRESS, 6}, - {1, FAL_PORT_TDB_DIR_EGRESS, 6}, - {1, FAL_PORT_TDB_DIR_INGRESS, 0}, - {1, FAL_PORT_TDB_DIR_EGRESS, 1}, - {1, FAL_PORT_TDB_DIR_INGRESS, 7}, - {1, FAL_PORT_TDB_DIR_EGRESS, 7}, - {1, FAL_PORT_TDB_DIR_INGRESS, 0}, - {1, FAL_PORT_TDB_DIR_EGRESS, 5}, - {1, FAL_PORT_TDB_DIR_INGRESS, 5}, - {1, FAL_PORT_TDB_DIR_EGRESS, 0}, - {1, FAL_PORT_TDB_DIR_INGRESS, 0}, - {1, FAL_PORT_TDB_DIR_EGRESS, 6}, - {1, FAL_PORT_TDB_DIR_INGRESS, 6}, - {1, FAL_PORT_TDB_DIR_EGRESS, 0}, - {1, FAL_PORT_TDB_DIR_INGRESS, 7}, - {1, FAL_PORT_TDB_DIR_EGRESS, 7}, - {1, FAL_PORT_TDB_DIR_INGRESS, 5}, - {1, FAL_PORT_TDB_DIR_EGRESS, 5}, - {1, FAL_PORT_TDB_DIR_INGRESS, 0}, - {1, FAL_PORT_TDB_DIR_EGRESS, 0}, - {1, FAL_PORT_TDB_DIR_INGRESS, 6}, - {1, FAL_PORT_TDB_DIR_EGRESS, 6}, - {1, FAL_PORT_TDB_DIR_INGRESS, 3}, - {1, FAL_PORT_TDB_DIR_EGRESS, 0}, - {1, FAL_PORT_TDB_DIR_INGRESS, 7}, - {1, FAL_PORT_TDB_DIR_EGRESS, 7}, - {1, FAL_PORT_TDB_DIR_INGRESS, 0}, - {1, FAL_PORT_TDB_DIR_EGRESS, 5}, - {1, FAL_PORT_TDB_DIR_INGRESS, 5}, - {1, FAL_PORT_TDB_DIR_EGRESS, 0}, - {1, FAL_PORT_TDB_DIR_INGRESS, 6}, - {1, FAL_PORT_TDB_DIR_EGRESS, 6}, - {1, FAL_PORT_TDB_DIR_INGRESS, 7}, - {1, FAL_PORT_TDB_DIR_EGRESS, 2}, - {1, FAL_PORT_TDB_DIR_INGRESS, 0}, - {1, FAL_PORT_TDB_DIR_EGRESS, 7}, - {1, FAL_PORT_TDB_DIR_INGRESS, 5}, - {1, FAL_PORT_TDB_DIR_EGRESS, 5}, - {1, FAL_PORT_TDB_DIR_INGRESS, 6}, - {1, FAL_PORT_TDB_DIR_EGRESS, 0}, - {1, FAL_PORT_TDB_DIR_INGRESS, 7}, - {1, FAL_PORT_TDB_DIR_EGRESS, 6}, -}; - -fal_port_tdm_tick_cfg_t cppe_port_tdm0_tbl[] = { - {1, FAL_PORT_TDB_DIR_INGRESS, 0}, - {1, FAL_PORT_TDB_DIR_EGRESS, 0}, - {1, FAL_PORT_TDB_DIR_INGRESS, 5}, - {1, FAL_PORT_TDB_DIR_EGRESS, 4}, - {1, FAL_PORT_TDB_DIR_INGRESS, 1}, - {1, FAL_PORT_TDB_DIR_EGRESS, 5}, - {1, FAL_PORT_TDB_DIR_INGRESS, 6}, - {1, FAL_PORT_TDB_DIR_EGRESS, 6}, - {1, FAL_PORT_TDB_DIR_INGRESS, 0}, - {1, FAL_PORT_TDB_DIR_EGRESS, 0}, - {1, FAL_PORT_TDB_DIR_INGRESS, 7}, - {1, FAL_PORT_TDB_DIR_EGRESS, 7}, - {1, FAL_PORT_TDB_DIR_INGRESS, 4}, - {1, FAL_PORT_TDB_DIR_EGRESS, 0}, - {1, FAL_PORT_TDB_DIR_INGRESS, 6}, - {1, FAL_PORT_TDB_DIR_EGRESS, 5}, - {1, FAL_PORT_TDB_DIR_INGRESS, 0}, - {1, FAL_PORT_TDB_DIR_EGRESS, 0}, - {1, FAL_PORT_TDB_DIR_INGRESS, 2}, - {1, FAL_PORT_TDB_DIR_EGRESS, 6}, - {1, FAL_PORT_TDB_DIR_INGRESS, 7}, - {1, FAL_PORT_TDB_DIR_EGRESS, 7}, - {1, FAL_PORT_TDB_DIR_INGRESS, 5}, - {1, FAL_PORT_TDB_DIR_EGRESS, 5}, - {1, FAL_PORT_TDB_DIR_INGRESS, 0}, - {1, FAL_PORT_TDB_DIR_EGRESS, 0}, - {1, FAL_PORT_TDB_DIR_INGRESS, 6}, - {1, FAL_PORT_TDB_DIR_EGRESS, 6}, - {1, FAL_PORT_TDB_DIR_INGRESS, 7}, - {1, FAL_PORT_TDB_DIR_EGRESS, 3}, - {1, FAL_PORT_TDB_DIR_INGRESS, 5}, - {1, FAL_PORT_TDB_DIR_EGRESS, 7}, - {1, FAL_PORT_TDB_DIR_INGRESS, 0}, - {1, FAL_PORT_TDB_DIR_EGRESS, 0}, - {1, FAL_PORT_TDB_DIR_INGRESS, 6}, - {1, FAL_PORT_TDB_DIR_EGRESS, 5}, - {1, FAL_PORT_TDB_DIR_INGRESS, 0}, - {1, FAL_PORT_TDB_DIR_EGRESS, 6}, - {1, FAL_PORT_TDB_DIR_INGRESS, 7}, - {1, FAL_PORT_TDB_DIR_EGRESS, 7}, - {1, FAL_PORT_TDB_DIR_INGRESS, 0}, - {1, FAL_PORT_TDB_DIR_EGRESS, 0}, - {1, FAL_PORT_TDB_DIR_INGRESS, 5}, - {1, FAL_PORT_TDB_DIR_EGRESS, 4}, - {1, FAL_PORT_TDB_DIR_INGRESS, 6}, - {1, FAL_PORT_TDB_DIR_EGRESS, 6}, - {1, FAL_PORT_TDB_DIR_INGRESS, 7}, - {1, FAL_PORT_TDB_DIR_EGRESS, 7}, - {1, FAL_PORT_TDB_DIR_INGRESS, 0}, - {1, FAL_PORT_TDB_DIR_EGRESS, 0}, - {1, FAL_PORT_TDB_DIR_INGRESS, 4}, - {1, FAL_PORT_TDB_DIR_EGRESS, 5}, - {1, FAL_PORT_TDB_DIR_INGRESS, 5}, - {1, FAL_PORT_TDB_DIR_EGRESS, 1}, - {1, FAL_PORT_TDB_DIR_INGRESS, 6}, - {1, FAL_PORT_TDB_DIR_EGRESS, 6}, - {1, FAL_PORT_TDB_DIR_INGRESS, 0}, - {1, FAL_PORT_TDB_DIR_EGRESS, 0}, - {1, FAL_PORT_TDB_DIR_INGRESS, 7}, - {1, FAL_PORT_TDB_DIR_EGRESS, 7}, - {1, FAL_PORT_TDB_DIR_INGRESS, 0}, - {1, FAL_PORT_TDB_DIR_EGRESS, 4}, - {1, FAL_PORT_TDB_DIR_INGRESS, 5}, - {1, FAL_PORT_TDB_DIR_EGRESS, 6}, - {1, FAL_PORT_TDB_DIR_INGRESS, 0}, - {1, FAL_PORT_TDB_DIR_EGRESS, 0}, - {1, FAL_PORT_TDB_DIR_INGRESS, 6}, - {1, FAL_PORT_TDB_DIR_EGRESS, 2}, - {1, FAL_PORT_TDB_DIR_INGRESS, 7}, - {1, FAL_PORT_TDB_DIR_EGRESS, 7}, - {1, FAL_PORT_TDB_DIR_INGRESS, 5}, - {1, FAL_PORT_TDB_DIR_EGRESS, 5}, - {1, FAL_PORT_TDB_DIR_INGRESS, 0}, - {1, FAL_PORT_TDB_DIR_EGRESS, 0}, - {1, FAL_PORT_TDB_DIR_INGRESS, 6}, - {1, FAL_PORT_TDB_DIR_EGRESS, 6}, - {1, FAL_PORT_TDB_DIR_INGRESS, 3}, - {1, FAL_PORT_TDB_DIR_EGRESS, 7}, - {1, FAL_PORT_TDB_DIR_INGRESS, 7}, - {1, FAL_PORT_TDB_DIR_EGRESS, 5}, - {1, FAL_PORT_TDB_DIR_INGRESS, 0}, - {1, FAL_PORT_TDB_DIR_EGRESS, 0}, - {1, FAL_PORT_TDB_DIR_INGRESS, 5}, - {1, FAL_PORT_TDB_DIR_EGRESS, 6}, - {1, FAL_PORT_TDB_DIR_INGRESS, 6}, - {1, FAL_PORT_TDB_DIR_EGRESS, 0}, - {1, FAL_PORT_TDB_DIR_INGRESS, 7}, - {1, FAL_PORT_TDB_DIR_EGRESS, 7}, - {1, FAL_PORT_TDB_DIR_INGRESS, 0}, - {1, FAL_PORT_TDB_DIR_EGRESS, 0}, - {1, FAL_PORT_TDB_DIR_INGRESS, 4}, - {1, FAL_PORT_TDB_DIR_EGRESS, 5}, - {1, FAL_PORT_TDB_DIR_INGRESS, 6}, - {1, FAL_PORT_TDB_DIR_EGRESS, 6}, - {1, FAL_PORT_TDB_DIR_INGRESS, 7}, - {1, FAL_PORT_TDB_DIR_EGRESS, 7}, -}; - -static sw_error_t -qca_hppe_tdm_hw_init(a_uint32_t dev_id) -{ - adpt_api_t *p_api; - a_uint32_t i = 0; - a_uint32_t num; - fal_port_tdm_ctrl_t tdm_ctrl; - fal_port_scheduler_cfg_t *scheduler_cfg; - fal_port_tdm_tick_cfg_t *bm_cfg; - a_uint8_t tm_tick_mode, bm_tick_mode; - - SW_RTN_ON_NULL(p_api = adpt_api_ptr_get(dev_id)); - SW_RTN_ON_NULL(p_api->adpt_port_scheduler_cfg_set); - SW_RTN_ON_NULL(p_api->adpt_tdm_tick_num_set); - - tm_tick_mode = ssdk_tm_tick_mode_get(dev_id); - bm_tick_mode = ssdk_bm_tick_mode_get(dev_id); - - if (tm_tick_mode == 0) { - if (adpt_hppe_chip_revision_get(dev_id) == CPPE_REVISION) { - num = sizeof(cppe_port_scheduler0_tbl) / - sizeof(fal_port_scheduler_cfg_t); - scheduler_cfg = cppe_port_scheduler0_tbl; - } else { - num = sizeof(port_scheduler0_tbl) / - sizeof(fal_port_scheduler_cfg_t); - scheduler_cfg = port_scheduler0_tbl; - } - } else if (tm_tick_mode == 1) { - num = sizeof(port_scheduler1_tbl) / sizeof(fal_port_scheduler_cfg_t); - scheduler_cfg = port_scheduler1_tbl; - } else { - return SW_BAD_VALUE; - } - - for (i = 0; i < num; i++) { - p_api->adpt_port_scheduler_cfg_set(dev_id, i, &scheduler_cfg[i]); - } - p_api->adpt_tdm_tick_num_set(dev_id, num); - - SW_RTN_ON_NULL(p_api->adpt_port_tdm_tick_cfg_set); - SW_RTN_ON_NULL(p_api->adpt_port_tdm_ctrl_set); - - if (bm_tick_mode == 0) { - if (adpt_hppe_chip_revision_get(dev_id) == CPPE_REVISION) { - num = sizeof(cppe_port_tdm0_tbl) / - sizeof(fal_port_tdm_tick_cfg_t); - bm_cfg = cppe_port_tdm0_tbl; - } else { - num = sizeof(port_tdm0_tbl) / - sizeof(fal_port_tdm_tick_cfg_t); - bm_cfg = port_tdm0_tbl; - } - } else { - return SW_BAD_VALUE; - } - for (i = 0; i < num; i++) { - p_api->adpt_port_tdm_tick_cfg_set(dev_id, i, &bm_cfg[i]); - } - tdm_ctrl.enable = A_TRUE; - tdm_ctrl.offset = A_FALSE; - tdm_ctrl.depth = num; - p_api->adpt_port_tdm_ctrl_set(dev_id, &tdm_ctrl); - SSDK_INFO("tdm setup num=%d\n", num); - return SW_OK; -} -#endif - -#if defined(IN_BM) -static sw_error_t -qca_hppe_bm_hw_init(a_uint32_t dev_id) -{ - a_uint32_t i = 0; - fal_bm_dynamic_cfg_t cfg; - a_uint32_t chip_ver = 0; - - chip_ver = adpt_hppe_chip_revision_get(dev_id); - - for (i = 0; i < HPPE_BM_PORT_NUM; i++) { - /* enable fc */ - fal_port_bm_ctrl_set(0, i, A_TRUE); - /* map to group 0 */ - fal_port_bufgroup_map_set(0, i, 0); - } - - if (chip_ver == CPPE_REVISION) { - fal_bm_bufgroup_buffer_set(dev_id, 0, 1024); - } else { - fal_bm_bufgroup_buffer_set(dev_id, 0, 1400); - } - - /* set reserved buffer */ - for (i = 0; i < HPPE_BM_PHY_PORT_OFFSET; i++) { - fal_bm_port_reserved_buffer_set(dev_id, i, 0, 100); - } - for (i = HPPE_BM_PHY_PORT_OFFSET; i < HPPE_BM_PORT_NUM-1; i++) { - fal_bm_port_reserved_buffer_set(dev_id, i, 0, 128); - } - if (chip_ver == CPPE_REVISION) { - fal_bm_port_reserved_buffer_set(dev_id, HPPE_BM_PORT_NUM -2, - 0, 40); - } - fal_bm_port_reserved_buffer_set(dev_id, HPPE_BM_PORT_NUM-1, 0, 40); - - memset(&cfg, 0, sizeof(cfg)); - cfg.resume_min_thresh = 0; - cfg.resume_off = 36; - cfg.weight= 4; - if (chip_ver == CPPE_REVISION) { - cfg.shared_ceiling = 216; - } else { - cfg.shared_ceiling = 250; - } - for (i = 0; i < HPPE_BM_PORT_NUM; i++) { - fal_bm_port_dynamic_thresh_set(dev_id, i, &cfg); - } - return SW_OK; -} -#endif - -#if defined(IN_QM) -static sw_error_t -qca_hppe_qm_hw_init(a_uint32_t dev_id) -{ - a_uint32_t i; - fal_ucast_queue_dest_t queue_dst; - fal_ac_obj_t obj; - fal_ac_ctrl_t ac_ctrl; - fal_ac_group_buffer_t group_buff; - fal_ac_dynamic_threshold_t dthresh_cfg; - fal_ac_static_threshold_t sthresh_cfg; - a_uint32_t qbase = 0; - a_uint32_t chip_ver = 0; - - memset(&queue_dst, 0, sizeof(queue_dst)); - - chip_ver = adpt_hppe_chip_revision_get(dev_id); - - /* - * Redirect service code 2 to queue 1 - * TODO: keep sync with NSS - */ - queue_dst.service_code_en = A_TRUE; - queue_dst.service_code = 2; - fal_ucast_queue_base_profile_set(dev_id, &queue_dst, 8, 0); - - queue_dst.service_code = 3; - fal_ucast_queue_base_profile_set(dev_id, &queue_dst, 128, 8); - - queue_dst.service_code = 4; - fal_ucast_queue_base_profile_set(dev_id, &queue_dst, 128, 8); - - queue_dst.service_code = 5; - fal_ucast_queue_base_profile_set(dev_id, &queue_dst, 0, 0); - - queue_dst.service_code = 6; - fal_ucast_queue_base_profile_set(dev_id, &queue_dst, 8, 0); - - queue_dst.service_code = 7; - fal_ucast_queue_base_profile_set(dev_id, &queue_dst, 240, 0); - - queue_dst.service_code_en = A_FALSE; - queue_dst.service_code = 0; - for(i = 0; i < SSDK_MAX_PORT_NUM; i++) { - queue_dst.dst_port = i; - qbase = ssdk_ucast_queue_start_get(dev_id, i); - fal_ucast_queue_base_profile_set(dev_id, &queue_dst, qbase, i); - } - - /* - * Enable PPE source profile 1 and map it to PPE queue 4 - */ - memset(&queue_dst, 0, sizeof(queue_dst)); - queue_dst.src_profile = 1; - - /* - * Enable service code mapping for profile 1 - */ - queue_dst.service_code_en = A_TRUE; - for (i = 0; i < SSDK_MAX_SERVICE_CODE_NUM; i++) { - queue_dst.service_code = i; - - if (i == 2 || i == 6) { - fal_ucast_queue_base_profile_set(dev_id, &queue_dst, 8, 0); - } else if (i == 3 || i == 4) { - fal_ucast_queue_base_profile_set(dev_id, &queue_dst, 128, 8); - } else { - fal_ucast_queue_base_profile_set(dev_id, &queue_dst, 4, 0); - } - } - queue_dst.service_code_en = A_FALSE; - queue_dst.service_code = 0; - - /* - * Enable cpu code mapping for profile 1 - */ - queue_dst.cpu_code_en = A_TRUE; - for (i = 0; i < SSDK_MAX_CPU_CODE_NUM; i++) { - queue_dst.cpu_code = i; - fal_ucast_queue_base_profile_set(dev_id, &queue_dst, 4, 0); - } - queue_dst.cpu_code_en = A_FALSE; - queue_dst.cpu_code = 0; - - /* - * Enable destination port mappings for profile 1 - */ - for (i = 0; i < SSDK_MAX_PORT_NUM; i++) { - queue_dst.dst_port = i; - qbase = ssdk_ucast_queue_start_get(dev_id, i); - fal_ucast_queue_base_profile_set(dev_id, &queue_dst, qbase, i); - } - - for (i = SSDK_MAX_PORT_NUM; i < SSDK_MAX_VIRTUAL_PORT_NUM; i++) { - queue_dst.dst_port = i; - fal_ucast_queue_base_profile_set(dev_id, &queue_dst, 4, 0); - } - queue_dst.dst_port = 0; - - /* queue ac*/ - ac_ctrl.ac_en = A_TRUE; - ac_ctrl.ac_fc_en = A_FALSE; - for (i = 0; i < SSDK_L0SCHEDULER_CFG_MAX; i++) { - obj.type = FAL_AC_QUEUE; - obj.obj_id = i; - fal_ac_ctrl_set(dev_id, &obj, &ac_ctrl); - fal_ac_queue_group_set(dev_id, i, 0); - fal_ac_prealloc_buffer_set(dev_id, &obj, 0); - } - - group_buff.prealloc_buffer = 0; - if (chip_ver == CPPE_REVISION) { - group_buff.total_buffer = 1506; - } else { - group_buff.total_buffer = 2000; - } - fal_ac_group_buffer_set(dev_id, 0, &group_buff); - - memset(&dthresh_cfg, 0, sizeof(dthresh_cfg)); - dthresh_cfg.shared_weight = 4; - if (chip_ver == CPPE_REVISION) { - dthresh_cfg.ceiling = 216; - } else { - dthresh_cfg.ceiling = 400; - } - dthresh_cfg.green_resume_off = 36; - for (i = 0; i < SSDK_L0SCHEDULER_UCASTQ_CFG_MAX; i++) { - fal_ac_dynamic_threshold_set(dev_id, i, &dthresh_cfg); - } - - memset(&sthresh_cfg, 0, sizeof(sthresh_cfg)); - if (chip_ver == CPPE_REVISION) { - sthresh_cfg.green_max = 144; - } else { - sthresh_cfg.green_max = 250; - } - sthresh_cfg.green_resume_off = 36; - for (i = SSDK_L0SCHEDULER_UCASTQ_CFG_MAX; i < SSDK_L0SCHEDULER_CFG_MAX; - i++) { - obj.type = FAL_AC_QUEUE; - obj.obj_id = i; - fal_ac_static_threshold_set(dev_id, &obj, &sthresh_cfg); - } - - return SW_OK; -} -#endif - -#if defined(IN_QOS) -static sw_error_t -qca_hppe_qos_scheduler_hw_init(a_uint32_t dev_id) -{ - a_uint32_t i = 0; - fal_qos_scheduler_cfg_t cfg; - fal_queue_bmp_t queue_bmp; - fal_qos_group_t group_sel; - fal_qos_pri_precedence_t pri_pre; - ssdk_dt_scheduler_cfg *dt_cfg = ssdk_bootup_shceduler_cfg_get(dev_id); - - memset(&cfg, 0, sizeof(cfg)); - - /* L1 shceduler */ - for (i = 0; i < SSDK_L1SCHEDULER_CFG_MAX; i++) { - if (dt_cfg->l1cfg[i].valid) { - cfg.sp_id = dt_cfg->l1cfg[i].port_id; - cfg.c_pri = dt_cfg->l1cfg[i].cpri; - cfg.e_pri = dt_cfg->l1cfg[i].epri; - cfg.c_drr_id = dt_cfg->l1cfg[i].cdrr_id; - cfg.e_drr_id = dt_cfg->l1cfg[i].edrr_id; - cfg.c_drr_wt = 1; - cfg.e_drr_wt = 1; - fal_queue_scheduler_set(dev_id, i, 1, - dt_cfg->l1cfg[i].port_id, &cfg); - } - } - - /* L0 shceduler */ - for (i = 0; i < SSDK_L0SCHEDULER_CFG_MAX; i++) { - if (dt_cfg->l0cfg[i].valid) { - cfg.sp_id = dt_cfg->l0cfg[i].sp_id; - cfg.c_pri = dt_cfg->l0cfg[i].cpri; - cfg.e_pri = dt_cfg->l0cfg[i].epri; - cfg.c_drr_id = dt_cfg->l0cfg[i].cdrr_id; - cfg.e_drr_id = dt_cfg->l0cfg[i].edrr_id; - cfg.c_drr_wt = 1; - cfg.e_drr_wt = 1; - fal_queue_scheduler_set(dev_id, i, - 0, dt_cfg->l0cfg[i].port_id, &cfg); - } - } - - /* queue--edma ring mapping*/ - memset(&queue_bmp, 0, sizeof(queue_bmp)); - queue_bmp.bmp[0] = 0xF; - fal_edma_ring_queue_map_set(dev_id, 0, &queue_bmp); - queue_bmp.bmp[0] = 0xF0; - fal_edma_ring_queue_map_set(dev_id, 3, &queue_bmp); - queue_bmp.bmp[0] = 0xF00; - fal_edma_ring_queue_map_set(dev_id, 1, &queue_bmp); - queue_bmp.bmp[0] = 0; - queue_bmp.bmp[4] = 0xFFFF; - fal_edma_ring_queue_map_set(dev_id, 2, &queue_bmp); - - /* chose qos group 0 */ - group_sel.dscp_group = 0; - group_sel.flow_group = 0; - group_sel.pcp_group = 0; - for (i = SSDK_PHYSICAL_PORT0; i <= SSDK_PHYSICAL_PORT7; i++) { - fal_qos_port_group_get(dev_id, i, &group_sel); - } - /* qos precedence */ - pri_pre.flow_pri = 4; - pri_pre.acl_pri = 2; - pri_pre.dscp_pri = 1; - pri_pre.pcp_pri = 0; - pri_pre.preheader_pri = 3; - for (i = SSDK_PHYSICAL_PORT0; i <= SSDK_PHYSICAL_PORT7; i++) { - fal_qos_port_pri_precedence_set(dev_id, i, &pri_pre); - } - - return SW_OK; -} -#endif - - -#if defined(IN_ACL) -#define LIST_ID_BYP_FDB_LRN 63/*reserved for bypass fdb learning*/ -#define LIST_PRI_BYP_FDB_LRN 32 - -sw_error_t qca_hppe_acl_byp_intf_mac_learn(a_uint32_t dev_id) -{ - a_uint32_t index = 0, num; - fal_acl_rule_t rule = { 0 }; - a_uint8_t* mac; - a_uint32_t port_bmp = qca_ssdk_port_bmp_get(dev_id); - - num = ssdk_intf_mac_num_get(); - if(num == 0){ - return SW_OK;/*No found interface MAC*/ - } - - /*Bypass fdb learn*/ - rule.rule_type = FAL_ACL_RULE_MAC; - rule.bypass_bitmap |= (1<= num) - break; - mac = ssdk_intf_macaddr_get(index); - memcpy(rule.src_mac_val.uc, mac, 6); - memset(rule.src_mac_mask.uc, 0xff, 6); - SSDK_DEBUG("%02x:%02x:%02x:%02x:%02x:%02x\n", rule.src_mac_val.uc[0], - rule.src_mac_val.uc[1], rule.src_mac_val.uc[2], rule.src_mac_val.uc[3], - rule.src_mac_val.uc[4], rule.src_mac_val.uc[5]); - fal_acl_rule_add(dev_id, LIST_ID_BYP_FDB_LRN, index, 1, &rule); - } - fal_acl_list_bind(dev_id, LIST_ID_BYP_FDB_LRN, FAL_ACL_DIREC_IN, - FAL_ACL_BIND_PORTBITMAP, port_bmp); - - return SW_OK; -} - -#if defined(IN_PTP) -sw_error_t qca_hppe_acl_remark_ptp_servcode(a_uint32_t dev_id) { -#define LIST_ID_L2_TAG_SERVICE_CODE_PTP 58 -#define LIST_ID_L4_TAG_SERVICE_CODE_PTP 59 -#define LIST_PRI_TAG_SERVICE_CODE_PTP 1 -#define PTP_EVENT_PKT_SERVICE_CODE 0x9 -#define PTP_EV_PORT 319 -#define PTP_MSG_SYNC 0 -#define PTP_MSG_PRESP 3 - - sw_error_t ret; - fal_func_ctrl_t func_ctrl, func_ctrl_old; - fal_servcode_config_t servcode_conf; - fal_acl_rule_t entry = {0}; - a_uint32_t index = 0, msg_type = 0; - a_uint32_t ptp_port_bmp = 0; - - /* only marking ptp packet with service code for the qca808x phy */ - ptp_port_bmp = qca_ssdk_phy_type_port_bmp_get(dev_id, QCA808X_PHY_CHIP); - - /* Not found the PHY with ptp feature */ - if (ptp_port_bmp == 0) { - return SW_OK; - } - - /* Create PTP ACL L2 list */ - ret = fal_acl_list_creat(dev_id, LIST_ID_L2_TAG_SERVICE_CODE_PTP, - LIST_PRI_TAG_SERVICE_CODE_PTP); - SW_RTN_ON_ERROR(ret); - - /* Set up UDF2 profile */ - ret = fal_acl_udf_profile_set(dev_id, FAL_ACL_UDF_NON_IP, 2, FAL_ACL_UDF_TYPE_L3, 0); - SW_RTN_ON_ERROR(ret); - - /* Tag service code for PTP packet */ - entry.service_code = PTP_EVENT_PKT_SERVICE_CODE; - entry.pri = LIST_PRI_TAG_SERVICE_CODE_PTP; - FAL_ACTION_FLG_SET(entry.action_flg, FAL_ACL_ACTION_SERVICE_CODE); - FAL_ACTION_FLG_SET(entry.action_flg, FAL_ACL_ACTION_PERMIT); - - /* L2 PTP packet */ - entry.rule_type = FAL_ACL_RULE_MAC; - - /* L2 PTP ethernet type 0x88f7 */ - entry.ethtype_val = ETH_P_1588; - entry.ethtype_mask = 0xffff; - FAL_FIELD_FLG_SET(entry.field_flg, FAL_ACL_FIELD_MAC_ETHTYPE); - - for (msg_type = PTP_MSG_SYNC; msg_type <= PTP_MSG_PRESP; msg_type++) { - /* L2 UDF2 for msg type */ - entry.udf2_val = (msg_type << 0x8); - entry.udf2_mask = 0x0f00; - FAL_FIELD_FLG_SET(entry.field_flg, FAL_ACL_FIELD_UDF2); - - /* Add PTP L2 rule to ACL list */ - ret = fal_acl_rule_add(dev_id, LIST_ID_L2_TAG_SERVICE_CODE_PTP, - index++, 1, &entry); - SW_RTN_ON_ERROR(ret); - } - - /* Unset L2 PTP ethernet type 0x88f7 */ - index = 0; - FAL_FIELD_FLG_CLR(entry.field_flg, FAL_ACL_FIELD_UDF2); - FAL_FIELD_FLG_CLR(entry.field_flg, FAL_ACL_FIELD_MAC_ETHTYPE); - - /* Create PTP ACL L4 list */ - ret = fal_acl_list_creat(dev_id, LIST_ID_L4_TAG_SERVICE_CODE_PTP, - LIST_PRI_TAG_SERVICE_CODE_PTP); - SW_RTN_ON_ERROR(ret); - - /* IPv4 PTP packet */ - entry.rule_type = FAL_ACL_RULE_IP4; - entry.is_ip_mask = 1; - entry.is_ip_val = A_TRUE; - FAL_FIELD_FLG_SET(entry.field_flg, FAL_ACL_FIELD_IP); - entry.is_ipv6_mask = 1; - entry.is_ipv6_val = A_FALSE; - FAL_FIELD_FLG_SET(entry.field_flg, FAL_ACL_FIELD_IPV6); - - /* PTP over UDP protocol */ - entry.ip_proto_val = IPPROTO_UDP; - entry.ip_proto_mask = 0xff; - FAL_FIELD_FLG_SET(entry.field_flg, FAL_ACL_FIELD_IP_PROTO); - - /* PTP UDP dest port 319 */ - entry.dest_l4port_op = FAL_ACL_FIELD_MASK; - entry.dest_l4port_val = PTP_EV_PORT; - entry.dest_l4port_mask = 0xffff; - FAL_FIELD_FLG_SET(entry.field_flg, FAL_ACL_FIELD_L4_DPORT); - - /* Add PTP IPv4 rule to ACL list */ - ret = fal_acl_rule_add(dev_id, LIST_ID_L4_TAG_SERVICE_CODE_PTP, index++, 1, &entry); - SW_RTN_ON_ERROR(ret); - - /* IPv6 PTP packet */ - entry.rule_type = FAL_ACL_RULE_IP6; - entry.is_ipv6_val = A_TRUE; - - /* Add PTP IPv6 rule to ACL list */ - ret = fal_acl_rule_add(dev_id, LIST_ID_L4_TAG_SERVICE_CODE_PTP, index++, 1, &entry); - SW_RTN_ON_ERROR(ret); - - /* Bind PTP ACL list to port bmp */ - ret = fal_acl_list_bind(dev_id, LIST_ID_L2_TAG_SERVICE_CODE_PTP, - FAL_ACL_DIREC_IN, FAL_ACL_BIND_PORTBITMAP, ptp_port_bmp); - SW_RTN_ON_ERROR(ret); - ret = fal_acl_list_bind(dev_id, LIST_ID_L4_TAG_SERVICE_CODE_PTP, - FAL_ACL_DIREC_IN, FAL_ACL_BIND_PORTBITMAP, ptp_port_bmp); - SW_RTN_ON_ERROR(ret); - - /* enable service code module temporarily */ - ret = fal_module_func_ctrl_get(dev_id, FAL_MODULE_SERVCODE, &func_ctrl_old); - SW_RTN_ON_ERROR(ret); - func_ctrl.bitmap[0] = (1<adpt_port_mux_mac_type_set); - SW_RTN_ON_NULL(p_api->adpt_uniphy_mode_set); - - - rv = p_api->adpt_uniphy_mode_set(dev_id, SSDK_UNIPHY_INSTANCE0, mode0); - SW_RTN_ON_ERROR(rv); - - rv = p_api->adpt_uniphy_mode_set(dev_id, SSDK_UNIPHY_INSTANCE1, mode1); - SW_RTN_ON_ERROR(rv); - - if(adpt_hppe_chip_revision_get(dev_id) == HPPE_REVISION) { - rv = p_api->adpt_uniphy_mode_set(dev_id, - SSDK_UNIPHY_INSTANCE2, mode2); - SW_RTN_ON_ERROR(rv); - } - for (index = SSDK_UNIPHY_INSTANCE0; index <= SSDK_UNIPHY_INSTANCE2; index ++) { - if (mode[index] == PORT_WRAPPER_MAX) { - ssdk_gcc_uniphy_sys_set(dev_id, index, A_FALSE); - } - } - - if(adpt_hppe_chip_revision_get(dev_id) == CPPE_REVISION) { - port_max = SSDK_PHYSICAL_PORT6; - } else { - port_max = SSDK_PHYSICAL_PORT7; - } - for(port_id = SSDK_PHYSICAL_PORT1; port_id < port_max; port_id++) { - rv = p_api->adpt_port_mux_mac_type_set(dev_id, port_id, mode0, mode1, mode2); - if(rv != SW_OK) { - SSDK_ERROR("port_id:%d, mode0:%d, mode1:%d, mode2:%d\n", port_id, mode0, mode1, mode2); - break; - } - } - - return rv; -} - - -#if defined(IN_FLOW) -static sw_error_t -qca_hppe_flow_hw_init(a_uint32_t dev_id) -{ - fal_flow_direction_t dir, dir_max; - fal_flow_mgmt_t mgmt; - sw_error_t rv; - - memset(&mgmt, 0, sizeof(fal_flow_mgmt_t)); - dir_max = FAL_FLOW_UNKOWN_DIR_DIR; - - /*set redirect to cpu for multicast flow*/ - for (dir = FAL_FLOW_LAN_TO_LAN_DIR; dir <= dir_max; dir++) { - rv = fal_flow_mgmt_get(dev_id, FAL_FLOW_MCAST, dir, &mgmt); - SW_RTN_ON_ERROR(rv); - mgmt.miss_action = FAL_MAC_RDT_TO_CPU; - rv = fal_flow_mgmt_set(dev_id, FAL_FLOW_MCAST, dir, &mgmt); - SW_RTN_ON_ERROR(rv); - } - return SW_OK; -} -#endif - -sw_error_t qca_hppe_hw_init(ssdk_init_cfg *cfg, a_uint32_t dev_id) -{ - sw_error_t rv = SW_OK; - - /* reset ppe */ - ssdk_ppe_reset_init(); - - rv = qca_switch_init(dev_id); - SW_RTN_ON_ERROR(rv); - -#if defined(IN_BM) - rv = qca_hppe_bm_hw_init(dev_id); - SW_RTN_ON_ERROR(rv); -#endif -#if defined(IN_QM) - rv = qca_hppe_qm_hw_init(dev_id); - SW_RTN_ON_ERROR(rv); -#endif -#if defined(IN_QOS) - rv = qca_hppe_qos_scheduler_hw_init(dev_id); - SW_RTN_ON_ERROR(rv); -#endif -#if defined(IN_BM) && defined(IN_QOS) - rv = qca_hppe_tdm_hw_init(dev_id); - SW_RTN_ON_ERROR(rv); -#endif -#if defined(IN_FDB) - rv= qca_hppe_fdb_hw_init(dev_id); - SW_RTN_ON_ERROR(rv); -#endif -#if defined(IN_VSI) - rv= qca_hppe_vsi_hw_init(dev_id); - SW_RTN_ON_ERROR(rv); -#endif -#if defined(IN_PORTVLAN) - rv = qca_hppe_portvlan_hw_init(dev_id); - SW_RTN_ON_ERROR(rv); -#endif -#if defined(IN_PORTCONTROL) - rv = qca_hppe_portctrl_hw_init(dev_id); - SW_RTN_ON_ERROR(rv); -#endif -#if defined(IN_POLICER) - rv = qca_hppe_policer_hw_init(dev_id); - SW_RTN_ON_ERROR(rv); -#endif -#if defined(IN_SHAPER) - rv = qca_hppe_shaper_hw_init(dev_id); - SW_RTN_ON_ERROR(rv); -#endif -#if defined(IN_FLOW) - rv = qca_hppe_flow_hw_init(dev_id); - SW_RTN_ON_ERROR(rv); -#endif -#if defined(IN_ACL) - rv = qca_hppe_acl_byp_intf_mac_learn(dev_id); - SW_RTN_ON_ERROR(rv); -#if defined(IN_PTP) - rv = qca_hppe_acl_remark_ptp_servcode(dev_id); - SW_RTN_ON_ERROR(rv); -#endif -#endif - rv = qca_hppe_interface_mode_init(dev_id, cfg->mac_mode, cfg->mac_mode1, - cfg->mac_mode2); - SW_RTN_ON_ERROR(rv); -#if defined(IN_CTRLPKT) - rv = qca_hppe_ctlpkt_hw_init(dev_id); - SW_RTN_ON_ERROR(rv); -#endif - - return rv; -} - diff --git a/feeds/ipq807x/qca-ssdk/src/src/init/ssdk_init.c b/feeds/ipq807x/qca-ssdk/src/src/init/ssdk_init.c deleted file mode 100755 index 84b858c43..000000000 --- a/feeds/ipq807x/qca-ssdk/src/src/init/ssdk_init.c +++ /dev/null @@ -1,3693 +0,0 @@ -/* - * Copyright (c) 2012, 2014-2021, The Linux Foundation. All rights reserved. - * Permission to use, copy, modify, and/or distribute this software for - * any purpose with or without fee is hereby granted, provided that the - * above copyright notice and this permission notice appear in all copies. - * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES - * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR - * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES - * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN - * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT - * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. - */ - -/*qca808x_start*/ -#include "sw.h" -#include "ssdk_init.h" -#include "fal_init.h" -#include "fal.h" -#include "hsl.h" -#include "hsl_dev.h" -#include "hsl_phy.h" -/*qca808x_end*/ -#include "ssdk_dts.h" -#include "ssdk_interrupt.h" -#include -#include -#include -/*qca808x_start*/ -#include -#include -#include -#include -/*qca808x_end*/ -//#include -#include -#include -#include -#include -#include -/*qca808x_start*/ -#include -#include -/*qca808x_end*/ -#include -#include -#include -#include -#include - -#if defined(IN_SWCONFIG) -#if defined(CONFIG_OF) && (LINUX_VERSION_CODE >= KERNEL_VERSION(3,14,0)) -#include -#else -#include -#endif -#endif - -#if defined(ISIS) ||defined(ISISC) ||defined(GARUDA) -#include -#endif -#if defined(ATHENA) ||defined(SHIVA) ||defined(HORUS) -#include -#endif -#ifdef IN_MALIBU_PHY -#include -#endif -#if defined(CONFIG_OF) && (LINUX_VERSION_CODE >= KERNEL_VERSION(4,1,0)) -/*qca808x_start*/ -#include -#include -#include -#include -#include -/*qca808x_end*/ -#ifdef BOARD_AR71XX -#ifdef CONFIG_AR8216_PHY -#include "drivers/net/phy/ar8327.h" -#endif -#include "drivers/net/ethernet/atheros/ag71xx/ag71xx.h" -#endif -#elif defined(CONFIG_OF) && (LINUX_VERSION_CODE >= KERNEL_VERSION(3,14,0)) -#include -#include -#include -#include -#include -#else -#include -#include -#include -#endif -/*qca808x_start*/ -#include "ssdk_plat.h" -/*qca808x_end*/ -#include "ssdk_clk.h" -#include "ssdk_led.h" -#include "ref_vlan.h" -#include "ref_fdb.h" -#include "ref_mib.h" -#include "ref_port_ctrl.h" -#include "ref_misc.h" -#include "ref_uci.h" -#include "ref_vsi.h" -#include "shell.h" -#ifdef BOARD_AR71XX -#include "ssdk_uci.h" -#endif -/*qca808x_start*/ -#if defined(IN_PHY_I2C_MODE) -#include "ssdk_phy_i2c.h" -#endif -/*qca808x_end*/ -#ifdef IN_IP -#if defined (CONFIG_NF_FLOW_COOKIE) -#include "fal_flowcookie.h" -#ifdef IN_SFE -#include -#endif -#endif -#endif - -#ifdef IN_RFS -#if defined(CONFIG_VLAN_8021Q) || defined(CONFIG_VLAN_8021Q_MODULE) -#include -#endif -#include -#ifdef IN_IP -#include "fal_rfs.h" -#endif -#endif -#include "adpt.h" -#ifdef HPPE -#include "ssdk_hppe.h" -#endif -#ifdef SCOMPHY -#include "ssdk_scomphy.h" -#endif - -#ifdef IN_RFS -struct rfs_device rfs_dev; -struct notifier_block ssdk_inet_notifier; -ssdk_rfs_intf_t rfs_intf_tbl[SSDK_RFS_INTF_MAX] = {{0}}; -#endif - -//#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3,14,0)) -struct notifier_block ssdk_dev_notifier; -//#endif - - -extern ssdk_chip_type SSDK_CURRENT_CHIP_TYPE; -extern a_uint32_t hsl_dev_wan_port_get(a_uint32_t dev_id); -extern void dess_rgmii_sw_mac_polling_task(struct qca_phy_priv *priv); -extern void qca_ar8327_sw_mac_polling_task(struct qca_phy_priv *priv); -extern void qca_ar8327_sw_mib_task(struct qca_phy_priv *priv); - -//#define PSGMII_DEBUG - -#define QCA_QM_WORK_DELAY 100 -#define QCA_QM_ITEM_NUMBER 41 -#define QCA_RGMII_WORK_DELAY 1000 -#define QCA_MAC_SW_SYNC_WORK_DELAY 1000 -#ifdef DESS -static bool qca_dess_rfs_registered = false; -#endif -/*qca808x_start*/ -struct qca_phy_priv **qca_phy_priv_global; - -struct qca_phy_priv* ssdk_phy_priv_data_get(a_uint32_t dev_id) -{ - if (dev_id >= SW_MAX_NR_DEV || !qca_phy_priv_global) - return NULL; - - return qca_phy_priv_global[dev_id]; -} -/*qca808x_end*/ - -a_uint32_t hppe_port_type[6] = {0,0,0,0,0,0}; // this variable should be init by ssdk_init - -a_uint32_t -qca_hppe_port_mac_type_get(a_uint32_t dev_id, a_uint32_t port_id) -{ - if ((port_id < 1) || (port_id > 6)) - return 0; - return hppe_port_type[port_id - 1]; -} - -a_uint32_t -qca_hppe_port_mac_type_set(a_uint32_t dev_id, a_uint32_t port_id, a_uint32_t port_type) -{ - if ((port_id < 1) || (port_id > 6)) - return 0; - hppe_port_type[port_id - 1] = port_type; - - return 0; -} - -#ifndef BOARD_AR71XX -#if defined(CONFIG_OF) && (LINUX_VERSION_CODE >= KERNEL_VERSION(3,14,0)) -static void -ssdk_phy_rgmii_set(struct qca_phy_priv *priv) -{ - struct device_node *np = NULL; - u32 rgmii_en = 0, tx_delay = 0, rx_delay = 0; - - if (priv->ess_switch_flag == A_TRUE) - np = priv->of_node; - else -#if (LINUX_VERSION_CODE >= KERNEL_VERSION(4,9,0)) - np = priv->phy->mdio.dev.of_node; -#else - np = priv->phy->dev.of_node; -#endif - - if (!np) - return; - - if (!of_property_read_u32(np, "phy_rgmii_en", &rgmii_en)) { - a_uint16_t val = 0; - /*enable RGMII mode */ - qca_ar8327_phy_dbg_read(0, AR8327_PORT5_PHY_ADDR, - AR8327_PHY_REG_MODE_SEL, &val); - val |= AR8327_PHY_RGMII_MODE; - qca_ar8327_phy_dbg_write(0, AR8327_PORT5_PHY_ADDR, - AR8327_PHY_REG_MODE_SEL, val); - if (!of_property_read_u32(np, "txclk_delay_en", &tx_delay) - && tx_delay == 1) { - qca_ar8327_phy_dbg_read(0, AR8327_PORT5_PHY_ADDR, - AR8327_PHY_REG_SYS_CTRL, &val); - val |= AR8327_PHY_RGMII_TX_DELAY; - qca_ar8327_phy_dbg_write(0, AR8327_PORT5_PHY_ADDR, - AR8327_PHY_REG_SYS_CTRL, val); - } - if (!of_property_read_u32(np, "rxclk_delay_en", &rx_delay) - && rx_delay == 1) { - qca_ar8327_phy_dbg_read(0, AR8327_PORT5_PHY_ADDR, - AR8327_PHY_REG_TEST_CTRL, &val); - val |= AR8327_PHY_RGMII_RX_DELAY; - qca_ar8327_phy_dbg_write(0, AR8327_PORT5_PHY_ADDR, - AR8327_PHY_REG_TEST_CTRL, val); - } - } -} -#else -static void -ssdk_phy_rgmii_set(struct qca_phy_priv *priv) -{ - struct ar8327_platform_data *plat_data; - - plat_data = priv->phy->dev.platform_data; - if (plat_data == NULL) { - return; - } - - if(plat_data->pad5_cfg) { - if(plat_data->pad5_cfg->mode == AR8327_PAD_PHY_RGMII) { - a_uint16_t val = 0; - /*enable RGMII mode */ - priv->phy_dbg_read(0, AR8327_PORT5_PHY_ADDR, - AR8327_PHY_REG_MODE_SEL, &val); - val |= AR8327_PHY_RGMII_MODE; - priv->phy_dbg_write(0, AR8327_PORT5_PHY_ADDR, - AR8327_PHY_REG_MODE_SEL, val); - if(plat_data->pad5_cfg->txclk_delay_en) { - priv->phy_dbg_read(0, AR8327_PORT5_PHY_ADDR, - AR8327_PHY_REG_SYS_CTRL, &val); - val |= AR8327_PHY_RGMII_TX_DELAY; - priv->phy_dbg_write(0, AR8327_PORT5_PHY_ADDR, - AR8327_PHY_REG_SYS_CTRL, val); - } - if(plat_data->pad5_cfg->rxclk_delay_en) { - priv->phy_dbg_read(0, AR8327_PORT5_PHY_ADDR, - AR8327_PHY_REG_TEST_CTRL, &val); - val |= AR8327_PHY_RGMII_RX_DELAY; - priv->phy_dbg_write(0, AR8327_PORT5_PHY_ADDR, - AR8327_PHY_REG_TEST_CTRL, val); - } - } - } -} -#endif -#endif - - -static void -qca_ar8327_phy_fixup(struct qca_phy_priv *priv, int phy) -{ - switch (priv->revision) { - case 1: - /* 100m waveform */ - priv->phy_dbg_write(priv->device_id, phy, 0, 0x02ea); - /* turn on giga clock */ - priv->phy_dbg_write(priv->device_id, phy, 0x3d, 0x68a0); - break; - - case 2: - priv->phy_mmd_write(priv->device_id, phy, 0x7, 0x3c); - priv->phy_mmd_write(priv->device_id, phy, 0x4007, 0x0); - /* fallthrough */ - case 4: - priv->phy_mmd_write(priv->device_id, phy, 0x3, 0x800d); - priv->phy_mmd_write(priv->device_id, phy, 0x4003, 0x803f); - - priv->phy_dbg_write(priv->device_id, phy, 0x3d, 0x6860); - priv->phy_dbg_write(priv->device_id, phy, 0x5, 0x2c46); - priv->phy_dbg_write(priv->device_id, phy, 0x3c, 0x6000); - break; - } -} - -#ifdef IN_PORTVLAN -static void qca_port_isolate(a_uint32_t dev_id) -{ - a_uint32_t port_id, mem_port_id, mem_port_map[AR8327_NUM_PORTS]={0}; - - for(port_id = 0; port_id < AR8327_NUM_PORTS; port_id++) - { - if(port_id == 6) - for(mem_port_id = 1; mem_port_id<= 4; mem_port_id++) - mem_port_map[port_id] |= (1 << mem_port_id); - else if (port_id == 0) - mem_port_map[port_id] |= (1 << 5); - else if (port_id >= 1 && port_id <= 4) - mem_port_map[port_id] |= (1 << 6); - else - mem_port_map[port_id] |= 1; - } - - for(port_id = 0; port_id < AR8327_NUM_PORTS; port_id++) - - fal_portvlan_member_update(dev_id, port_id, mem_port_map[port_id]); - -} - -void ssdk_portvlan_init(a_uint32_t dev_id) -{ - a_uint32_t port = 0; - a_uint32_t cpu_bmp, lan_bmp, wan_bmp; - - cpu_bmp = ssdk_cpu_bmp_get(dev_id); - lan_bmp = ssdk_lan_bmp_get(dev_id); - wan_bmp = ssdk_wan_bmp_get(dev_id); - - if (!(cpu_bmp | lan_bmp | wan_bmp)) { - qca_port_isolate(dev_id); - return; - } - - for(port = 0; port < SSDK_MAX_PORT_NUM; port++) - { - if(cpu_bmp & (1 << port)) - { - fal_portvlan_member_update(dev_id, port, lan_bmp|wan_bmp); - } - if(lan_bmp & (1 << port)) - { - fal_portvlan_member_update(dev_id, port, (lan_bmp|cpu_bmp)&(~(1<interface_mac_pad_set - && p_api->interface_mac_sgmii_set) - { - p_api->interface_mac_pad_set(device_id,0,0); - p_api->interface_mac_pad_set(device_id,5,0); - p_api->interface_mac_pad_set(device_id,6,0); - p_api->interface_mac_sgmii_set(device_id,AR8327_REG_PAD_SGMII_CTRL_HW_INIT); - } - else - { - SSDK_ERROR("API not support \n"); - } -} - -static void qca_switch_set_mac_force(struct qca_phy_priv *priv) -{ - a_uint32_t value, value0, i; - if (priv == NULL || (priv->mii_read == NULL) || (priv->mii_write == NULL)) { - SSDK_ERROR("In qca_switch_set_mac_force, private data is NULL!\r\n"); - return; - } - - for (i=0; i < AR8327_NUM_PORTS; ++i) { - /* b3:2=0,Tx/Rx Mac disable, - b9=0,LINK_EN disable */ - value0 = priv->mii_read(priv->device_id, AR8327_REG_PORT_STATUS(i)); - value = value0 & ~(AR8327_PORT_STATUS_LINK_AUTO | - AR8327_PORT_STATUS_TXMAC | - AR8327_PORT_STATUS_RXMAC); - priv->mii_write(priv->device_id, AR8327_REG_PORT_STATUS(i), value); - - /* Force speed to 1000M Full */ - value = priv->mii_read(priv->device_id, AR8327_REG_PORT_STATUS(i)); - value &= ~(AR8327_PORT_STATUS_DUPLEX | AR8327_PORT_STATUS_SPEED); - value |= AR8327_PORT_SPEED_1000M | AR8327_PORT_STATUS_DUPLEX; - priv->mii_write(priv->device_id, AR8327_REG_PORT_STATUS(i), value); - } - return; -} - -void -qca_ar8327_phy_enable(struct qca_phy_priv *priv) -{ - int i = 0; -#ifndef BOARD_AR71XX - ssdk_phy_rgmii_set(priv); -#endif - for (i = 0; i < AR8327_NUM_PHYS; i++) { - a_uint16_t value = 0; - - if (priv->version == QCA_VER_AR8327) - qca_ar8327_phy_fixup(priv, i); - - /* start autoneg*/ - priv->phy_write(priv->device_id, i, MII_ADVERTISE, ADVERTISE_ALL | - ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM); - //phy reg 0x9, b10,1 = Prefer multi-port device (master) - priv->phy_write(priv->device_id, i, MII_CTRL1000, (0x0400|ADVERTISE_1000FULL)); - - priv->phy_write(priv->device_id, i, MII_BMCR, BMCR_RESET | BMCR_ANENABLE); - - priv->phy_dbg_read(priv->device_id, i, 0, &value); - value &= (~(1<<12)); - priv->phy_dbg_write(priv->device_id, i, 0, value); - - msleep(100); - } -} -void qca_ar8327_sw_soft_reset(struct qca_phy_priv *priv) -{ - a_uint32_t value = 0; - - value = priv->mii_read(priv->device_id, AR8327_REG_CTRL); - value |= 0x80000000; - priv->mii_write(priv->device_id, AR8327_REG_CTRL, value); - /*Need wait reset done*/ - do { - udelay(10); - value = priv->mii_read(priv->device_id, AR8327_REG_CTRL); - } while(value & AR8327_CTRL_RESET); - do { - udelay(10); - value = priv->mii_read(priv->device_id, 0x20); - } while ((value & SSDK_GLOBAL_INITIALIZED_STATUS) != - SSDK_GLOBAL_INITIALIZED_STATUS); - - return; -} - -#if defined(CONFIG_OF) && (LINUX_VERSION_CODE >= KERNEL_VERSION(3,14,0)) -int qca_ar8327_hw_init(struct qca_phy_priv *priv) -{ - struct device_node *np = NULL; - const __be32 *paddr; - a_uint32_t reg, value, i; - a_int32_t len; - - if (priv->ess_switch_flag == A_TRUE) - np = priv->of_node; - else -#if (LINUX_VERSION_CODE >= KERNEL_VERSION(4,9,0)) - np = priv->phy->mdio.dev.of_node; -#else - np = priv->phy->dev.of_node; -#endif - - if(!np) - return -EINVAL; - - /*Before switch software reset, disable PHY and clear MAC PAD*/ - qca_ar8327_phy_linkdown(priv->device_id); - qca_mac_disable(priv->device_id); - msleep(1000); - - /*First software reset S17 chip*/ - qca_ar8327_sw_soft_reset(priv); - - /*After switch software reset, need disable all ports' MAC with 1000M FULL*/ - qca_switch_set_mac_force(priv); - - /* Configure switch register from DT information */ - paddr = of_get_property(np, "qca,ar8327-initvals", &len); - if (paddr) { - if (len < (2 * sizeof(*paddr))) { - SSDK_ERROR("len:%d < 2 * sizeof(*paddr):%zu\n", len, 2 * sizeof(*paddr)); - return -EINVAL; - } - - len /= sizeof(*paddr); - - for (i = 0; i < len - 1; i += 2) { - reg = be32_to_cpup(paddr + i); - value = be32_to_cpup(paddr + i + 1); - priv->mii_write(priv->device_id, reg, value); - } - } - - value = priv->mii_read(priv->device_id, AR8327_REG_MODULE_EN); - value &= ~AR8327_REG_MODULE_EN_QM_ERR; - value &= ~AR8327_REG_MODULE_EN_LOOKUP_ERR; - priv->mii_write(priv->device_id, AR8327_REG_MODULE_EN, value); - - qca_switch_init(priv->device_id); -#ifdef IN_PORTVLAN - ssdk_portvlan_init(priv->device_id); -#endif - qca_mac_enable_intr(priv); - qca_ar8327_phy_enable(priv); - - return 0; -} -#else -static a_uint32_t -qca_ar8327_get_pad_cfg(struct ar8327_pad_cfg *pad_cfg) -{ - a_uint32_t value = 0; - - if (pad_cfg == 0) { - return 0; - } - - if(pad_cfg->mode == AR8327_PAD_MAC2MAC_MII) { - value = AR8327_PAD_CTRL_MAC_MII_EN; - if (pad_cfg->rxclk_sel) - value |= AR8327_PAD_CTRL_MAC_MII_RXCLK_SEL; - if (pad_cfg->txclk_sel) - value |= AR8327_PAD_CTRL_MAC_MII_TXCLK_SEL; - - } else if (pad_cfg->mode == AR8327_PAD_MAC2MAC_GMII) { - value = AR8327_PAD_CTRL_MAC_GMII_EN; - if (pad_cfg->rxclk_sel) - value |= AR8327_PAD_CTRL_MAC_GMII_RXCLK_SEL; - if (pad_cfg->txclk_sel) - value |= AR8327_PAD_CTRL_MAC_GMII_TXCLK_SEL; - - } else if (pad_cfg->mode == AR8327_PAD_MAC_SGMII) { - value = AR8327_PAD_CTRL_SGMII_EN; - - /* WAR for AP136 board. */ - value |= pad_cfg->txclk_delay_sel << - AR8327_PAD_CTRL_RGMII_TXCLK_DELAY_SEL_S; - value |= pad_cfg->rxclk_delay_sel << - AR8327_PAD_CTRL_RGMII_RXCLK_DELAY_SEL_S; - if (pad_cfg->rxclk_delay_en) - value |= AR8327_PAD_CTRL_RGMII_RXCLK_DELAY_EN; - if (pad_cfg->txclk_delay_en) - value |= AR8327_PAD_CTRL_RGMII_TXCLK_DELAY_EN; - - } else if (pad_cfg->mode == AR8327_PAD_MAC2PHY_MII) { - value = AR8327_PAD_CTRL_PHY_MII_EN; - if (pad_cfg->rxclk_sel) - value |= AR8327_PAD_CTRL_PHY_MII_RXCLK_SEL; - if (pad_cfg->txclk_sel) - value |= AR8327_PAD_CTRL_PHY_MII_TXCLK_SEL; - - } else if (pad_cfg->mode == AR8327_PAD_MAC2PHY_GMII) { - value = AR8327_PAD_CTRL_PHY_GMII_EN; - if (pad_cfg->pipe_rxclk_sel) - value |= AR8327_PAD_CTRL_PHY_GMII_PIPE_RXCLK_SEL; - if (pad_cfg->rxclk_sel) - value |= AR8327_PAD_CTRL_PHY_GMII_RXCLK_SEL; - if (pad_cfg->txclk_sel) - value |= AR8327_PAD_CTRL_PHY_GMII_TXCLK_SEL; - - } else if (pad_cfg->mode == AR8327_PAD_MAC_RGMII) { - value = AR8327_PAD_CTRL_RGMII_EN; - value |= pad_cfg->txclk_delay_sel << - AR8327_PAD_CTRL_RGMII_TXCLK_DELAY_SEL_S; - value |= pad_cfg->rxclk_delay_sel << - AR8327_PAD_CTRL_RGMII_RXCLK_DELAY_SEL_S; - if (pad_cfg->rxclk_delay_en) - value |= AR8327_PAD_CTRL_RGMII_RXCLK_DELAY_EN; - if (pad_cfg->txclk_delay_en) - value |= AR8327_PAD_CTRL_RGMII_TXCLK_DELAY_EN; - - } else if (pad_cfg->mode == AR8327_PAD_PHY_GMII) { - value = AR8327_PAD_CTRL_PHYX_GMII_EN; - - } else if (pad_cfg->mode == AR8327_PAD_PHY_RGMII) { - value = AR8327_PAD_CTRL_PHYX_RGMII_EN; - - } else if (pad_cfg->mode == AR8327_PAD_PHY_MII) { - value = AR8327_PAD_CTRL_PHYX_MII_EN; - - } else { - value = 0; - } - - return value; -} - -#ifndef BOARD_AR71XX -static a_uint32_t -qca_ar8327_get_pwr_sel(struct qca_phy_priv *priv, - struct ar8327_platform_data *plat_data) -{ - struct ar8327_pad_cfg *cfg = NULL; - a_uint32_t value; - - if (!plat_data) { - return 0; - } - - value = priv->mii_read(priv->device_id, AR8327_REG_PAD_MAC_PWR_SEL); - - cfg = plat_data->pad0_cfg; - - if (cfg && (cfg->mode == AR8327_PAD_MAC_RGMII) && - cfg->rgmii_1_8v) { - value |= AR8327_PAD_MAC_PWR_RGMII0_1_8V; - } - - cfg = plat_data->pad5_cfg; - if (cfg && (cfg->mode == AR8327_PAD_MAC_RGMII) && - cfg->rgmii_1_8v) { - value |= AR8327_PAD_MAC_PWR_RGMII1_1_8V; - } - - cfg = plat_data->pad6_cfg; - if (cfg && (cfg->mode == AR8327_PAD_MAC_RGMII) && - cfg->rgmii_1_8v) { - value |= AR8327_PAD_MAC_PWR_RGMII1_1_8V; - } - - return value; -} -#endif - -static a_uint32_t -qca_ar8327_set_led_cfg(struct qca_phy_priv *priv, - struct ar8327_platform_data *plat_data, - a_uint32_t pos) -{ - struct ar8327_led_cfg *led_cfg; - a_uint32_t new_pos = pos; - - led_cfg = plat_data->led_cfg; - if (led_cfg) { - if (led_cfg->open_drain) - new_pos |= AR8327_POS_LED_OPEN_EN; - else - new_pos &= ~AR8327_POS_LED_OPEN_EN; - - priv->mii_write(priv->device_id, AR8327_REG_LED_CTRL_0, led_cfg->led_ctrl0); - priv->mii_write(priv->device_id, AR8327_REG_LED_CTRL_1, led_cfg->led_ctrl1); - priv->mii_write(priv->device_id, AR8327_REG_LED_CTRL_2, led_cfg->led_ctrl2); - priv->mii_write(priv->device_id, AR8327_REG_LED_CTRL_3, led_cfg->led_ctrl3); - - if (new_pos != pos) { - new_pos |= AR8327_POS_POWER_ON_SEL; - } - } - return new_pos; -} -#ifndef BOARD_AR71XX -static int -qca_ar8327_set_sgmii_cfg(struct qca_phy_priv *priv, - struct ar8327_platform_data *plat_data, - a_uint32_t* new_pos) -{ - a_uint32_t value = 0; - - /*configure the SGMII*/ - value = priv->mii_read(priv->device_id, AR8327_REG_PAD_SGMII_CTRL); - value &= ~(AR8327_PAD_SGMII_CTRL_MODE_CTRL); - value |= ((plat_data->sgmii_cfg->sgmii_mode) << - AR8327_PAD_SGMII_CTRL_MODE_CTRL_S); - - if (priv->version == QCA_VER_AR8337) { - value |= (AR8327_PAD_SGMII_CTRL_EN_PLL | - AR8327_PAD_SGMII_CTRL_EN_RX | - AR8327_PAD_SGMII_CTRL_EN_TX); - } else { - value &= ~(AR8327_PAD_SGMII_CTRL_EN_PLL | - AR8327_PAD_SGMII_CTRL_EN_RX | - AR8327_PAD_SGMII_CTRL_EN_TX); - } - value |= AR8327_PAD_SGMII_CTRL_EN_SD; - - priv->mii_write(priv->device_id, AR8327_REG_PAD_SGMII_CTRL, value); - - if (plat_data->sgmii_cfg->serdes_aen) { - *new_pos &= ~AR8327_POS_SERDES_AEN; - } else { - *new_pos |= AR8327_POS_SERDES_AEN; - } - return 0; -} -#endif - -static int -qca_ar8327_set_plat_data_cfg(struct qca_phy_priv *priv, - struct ar8327_platform_data *plat_data) -{ - a_uint32_t pos, new_pos; - - pos = priv->mii_read(priv->device_id, AR8327_REG_POS); - - new_pos = qca_ar8327_set_led_cfg(priv, plat_data, pos); - -#ifndef BOARD_AR71XX - /*configure the SGMII*/ - if (plat_data->sgmii_cfg) { - qca_ar8327_set_sgmii_cfg(priv, plat_data, &new_pos); - } -#endif - - priv->mii_write(priv->device_id, AR8327_REG_POS, new_pos); - - return 0; -} - -static int -qca_ar8327_set_pad_cfg(struct qca_phy_priv *priv, - struct ar8327_platform_data *plat_data) -{ - a_uint32_t pad0 = 0, pad5 = 0, pad6 = 0; - - pad0 = qca_ar8327_get_pad_cfg(plat_data->pad0_cfg); - priv->mii_write(priv->device_id, AR8327_REG_PAD0_CTRL, pad0); - - pad5 = qca_ar8327_get_pad_cfg(plat_data->pad5_cfg); - if(priv->version == QCA_VER_AR8337) { - pad5 |= AR8327_PAD_CTRL_RGMII_RXCLK_DELAY_EN; - } - priv->mii_write(priv->device_id, AR8327_REG_PAD5_CTRL, pad5); - - pad6 = qca_ar8327_get_pad_cfg(plat_data->pad6_cfg); - if(plat_data->pad5_cfg && - (plat_data->pad5_cfg->mode == AR8327_PAD_PHY_RGMII)) - pad6 |= AR8327_PAD_CTRL_PHYX_RGMII_EN; - priv->mii_write(priv->device_id, AR8327_REG_PAD6_CTRL, pad6); - - return 0; -} - -void -qca_ar8327_port_init(struct qca_phy_priv *priv, a_uint32_t port) -{ - struct ar8327_platform_data *plat_data; - struct ar8327_port_cfg *port_cfg; - a_uint32_t value; - - plat_data = priv->phy->dev.platform_data; - if (plat_data == NULL) { - return; - } - - if (((port == 0) && plat_data->pad0_cfg) || - ((port == 5) && plat_data->pad5_cfg) || - ((port == 6) && plat_data->pad6_cfg)) { - switch (port) { - case 0: - port_cfg = &plat_data->cpuport_cfg; - break; - case 5: - port_cfg = &plat_data->port5_cfg; - break; - case 6: - port_cfg = &plat_data->port6_cfg; - break; - } - } else { - return; - } - - /*disable mac at first*/ - fal_port_rxmac_status_set(priv->device_id, port, A_FALSE); - fal_port_txmac_status_set(priv->device_id, port, A_FALSE); - value = port_cfg->duplex ? FAL_FULL_DUPLEX : FAL_HALF_DUPLEX; - fal_port_duplex_set(priv->device_id, port, value); - value = port_cfg->txpause ? A_TRUE : A_FALSE; - fal_port_txfc_status_set(priv->device_id, port, value); - value = port_cfg->rxpause ? A_TRUE : A_FALSE; - fal_port_rxfc_status_set(priv->device_id, port, value); - if(port_cfg->speed == AR8327_PORT_SPEED_10) { - value = FAL_SPEED_10; - } else if(port_cfg->speed == AR8327_PORT_SPEED_100) { - value = FAL_SPEED_100; - } else if(port_cfg->speed == AR8327_PORT_SPEED_1000) { - value = FAL_SPEED_1000; - } else { - value = FAL_SPEED_1000; - } - fal_port_speed_set(priv->device_id, port, value); - /*enable mac at last*/ - udelay(800); - fal_port_rxmac_status_set(priv->device_id, port, A_TRUE); - fal_port_txmac_status_set(priv->device_id, port, A_TRUE); -} - -int -qca_ar8327_hw_init(struct qca_phy_priv *priv) -{ - struct ar8327_platform_data *plat_data; - a_uint32_t i = 0; - a_uint32_t value = 0; - - plat_data = priv->phy->dev.platform_data; - if (plat_data == NULL) { - return -EINVAL; - } - - /*Before switch software reset, disable PHY and clear MAC PAD*/ - qca_ar8327_phy_linkdown(priv->device_id); - qca_mac_disable(priv->device_id); - udelay(10); - - qca_ar8327_set_plat_data_cfg(priv, plat_data); - - /*mac reset*/ - priv->mii_write(priv->device_id, AR8327_REG_MAC_SFT_RST, 0x3fff); - - msleep(100); - - /*First software reset S17 chip*/ - qca_ar8327_sw_soft_reset(priv); - udelay(1000); - - /*After switch software reset, need disable all ports' MAC with 1000M FULL*/ - qca_switch_set_mac_force(priv); - - qca_ar8327_set_pad_cfg(priv, plat_data); - - value = priv->mii_read(priv->device_id, AR8327_REG_MODULE_EN); - value &= ~AR8327_REG_MODULE_EN_QM_ERR; - value &= ~AR8327_REG_MODULE_EN_LOOKUP_ERR; - priv->mii_write(priv->device_id, AR8327_REG_MODULE_EN, value); - - qca_switch_init(priv->device_id); - -#ifndef BOARD_AR71XX - value = qca_ar8327_get_pwr_sel(priv, plat_data); - priv->mii_write(priv->device_id, AR8327_REG_PAD_MAC_PWR_SEL, value); -#endif - - msleep(1000); - - for (i = 0; i < AR8327_NUM_PORTS; i++) { - qca_ar8327_port_init(priv, i); - } - - qca_ar8327_phy_enable(priv); - - return 0; -} -#endif - -#if defined(IN_SWCONFIG) -#ifndef BOARD_AR71XX -#if (LINUX_VERSION_CODE < KERNEL_VERSION(5, 0, 0)) -static int -qca_ar8327_sw_get_reg_val(struct switch_dev *dev, - int reg, int *val) -{ - return 0; -} - -static int -qca_ar8327_sw_set_reg_val(struct switch_dev *dev, - int reg, int val) -{ - return 0; -} -#endif -#endif -static struct switch_attr qca_ar8327_globals[] = { -#if defined(IN_VLAN) - { - .name = "enable_vlan", - .description = "Enable 8021q VLAN", - .type = SWITCH_TYPE_INT, - .set = qca_ar8327_sw_set_vlan, - .get = qca_ar8327_sw_get_vlan, - .max = 1 - }, -#endif -#if defined(IN_MISC) - { - .name = "max_frame_size", - .description = "Set Max frame Size Of Mac", - .type = SWITCH_TYPE_INT, - .set = qca_ar8327_sw_set_max_frame_size, - .get = qca_ar8327_sw_get_max_frame_size, - .max = 9018 - }, -#endif -#if defined(IN_MIB) - { - .name = "reset_mibs", - .description = "Reset All MIB Counters", - .type = SWITCH_TYPE_NOVAL, - .set = qca_ar8327_sw_set_reset_mibs, - }, -#endif -#ifdef IN_FDB - { - .name = "flush_arl", - .description = "Flush All ARL table", - .type = SWITCH_TYPE_NOVAL, - .set = qca_ar8327_sw_atu_flush, - }, - { - .name = "dump_arl", - .description = "Dump All ARL table", - .type = SWITCH_TYPE_STRING, - .get = qca_ar8327_sw_atu_dump, - }, -#endif - { - .name = "switch_ext", - .description = "Switch extended configuration", - .type = SWITCH_TYPE_EXT, - .set = qca_ar8327_sw_switch_ext, - }, -}; - -static struct switch_attr qca_ar8327_port[] = { -#if defined(IN_MIB) - { - .name = "reset_mib", - .description = "Reset Mib Counters", - .type = SWITCH_TYPE_NOVAL, - .set = qca_ar8327_sw_set_port_reset_mib, - }, - { - .name = "mib", - .description = "Get Mib Counters", - .type = SWITCH_TYPE_STRING, - .set = NULL, - .get = qca_ar8327_sw_get_port_mib, - }, -#endif -#if defined(IN_PORTCONTROL) - { - .type = SWITCH_TYPE_INT, - .name = "enable_eee", - .description = "Enable EEE", - .set = qca_ar8327_sw_set_eee, - .get = qca_ar8327_sw_get_eee, - .max = 1, - }, -#endif -}; - -#if defined(IN_VLAN) -static struct switch_attr qca_ar8327_vlan[] = { - { - .name = "vid", - .description = "Configure Vlan Id", - .type = SWITCH_TYPE_INT, - .set = qca_ar8327_sw_set_vid, - .get = qca_ar8327_sw_get_vid, - .max = 4094, - }, -}; -#endif - -const struct switch_dev_ops qca_ar8327_sw_ops = { - .attr_global = { - .attr = qca_ar8327_globals, - .n_attr = ARRAY_SIZE(qca_ar8327_globals), - }, - .attr_port = { - .attr = qca_ar8327_port, - .n_attr = ARRAY_SIZE(qca_ar8327_port), - }, -#if defined(IN_VLAN) - .attr_vlan = { - .attr = qca_ar8327_vlan, - .n_attr = ARRAY_SIZE(qca_ar8327_vlan), - }, - .get_port_pvid = qca_ar8327_sw_get_pvid, - .set_port_pvid = qca_ar8327_sw_set_pvid, - .get_vlan_ports = qca_ar8327_sw_get_ports, - .set_vlan_ports = qca_ar8327_sw_set_ports, - .apply_config = qca_ar8327_sw_hw_apply, -#endif -#if defined(IN_MISC) - .reset_switch = qca_ar8327_sw_reset_switch, -#endif -#if defined(IN_PORTCONTROL) - .get_port_link = qca_ar8327_sw_get_port_link, -#endif -#ifndef BOARD_AR71XX -#if (LINUX_VERSION_CODE < KERNEL_VERSION(5, 0, 0)) - .get_reg_val = qca_ar8327_sw_get_reg_val, - .set_reg_val = qca_ar8327_sw_set_reg_val, -#endif -#endif -}; -#endif - -#define SSDK_MIB_CHANGE_WQ - -static int -qca_phy_mib_task(struct qca_phy_priv *priv) -{ - qca_ar8327_sw_mib_task(priv); - return 0; -} - -static void -qca_phy_mib_work_task(struct work_struct *work) -{ - struct qca_phy_priv *priv = container_of(work, struct qca_phy_priv, - mib_dwork.work); - - mutex_lock(&priv->mib_lock); - - qca_phy_mib_task(priv); - - mutex_unlock(&priv->mib_lock); -#ifndef SSDK_MIB_CHANGE_WQ - schedule_delayed_work(&priv->mib_dwork, - msecs_to_jiffies(QCA_PHY_MIB_WORK_DELAY)); -#else - queue_delayed_work_on(0, system_long_wq, &priv->mib_dwork, - msecs_to_jiffies(QCA_PHY_MIB_WORK_DELAY)); -#endif -} - -int -qca_phy_mib_work_start(struct qca_phy_priv *priv) -{ - mutex_init(&priv->mib_lock); - if(SW_OK != fal_mib_counter_alloc(priv->device_id, &priv->mib_counters)){ - SSDK_ERROR("Memory allocation fail\n"); - return -ENOMEM; - } - - INIT_DELAYED_WORK(&priv->mib_dwork, qca_phy_mib_work_task); -#ifndef SSDK_MIB_CHANGE_WQ - schedule_delayed_work(&priv->mib_dwork, - msecs_to_jiffies(QCA_PHY_MIB_WORK_DELAY)); -#else - queue_delayed_work_on(0, system_long_wq, &priv->mib_dwork, - msecs_to_jiffies(QCA_PHY_MIB_WORK_DELAY)); -#endif - - return 0; -} - -void -qca_phy_mib_work_stop(struct qca_phy_priv *priv) -{ - if(!priv) - return; - if(priv->mib_counters) - kfree(priv->mib_counters); - cancel_delayed_work_sync(&priv->mib_dwork); -} - -#define SSDK_QM_CHANGE_WQ - -static void -qm_err_check_work_task_polling(struct work_struct *work) -{ - struct qca_phy_priv *priv = container_of(work, struct qca_phy_priv, - qm_dwork_polling.work); - - mutex_lock(&priv->qm_lock); - - qca_ar8327_sw_mac_polling_task(priv); - - mutex_unlock(&priv->qm_lock); - -#ifndef SSDK_QM_CHANGE_WQ - schedule_delayed_work(&priv->qm_dwork, - msecs_to_jiffies(QCA_QM_WORK_DELAY)); -#else - queue_delayed_work_on(0, system_long_wq, &priv->qm_dwork_polling, - msecs_to_jiffies(QCA_QM_WORK_DELAY)); -#endif -} - -static int config_gpio(a_uint32_t gpio_num) -{ - int error; - - if (gpio_is_valid(gpio_num)) - { - error = gpio_request_one(gpio_num, GPIOF_IN, "linkchange"); - if (error < 0) { - SSDK_ERROR("gpio request faild \n"); - return -1; - } - gpio_set_debounce(gpio_num, 60000); - } - else - { - SSDK_ERROR("gpio is invalid\n"); - return -1; - } - - return 0; -} -static int qca_link_polling_select(struct qca_phy_priv *priv) -{ - struct device_node *np = NULL; - const __be32 *link_polling_required, *link_intr_gpio; - a_int32_t len; - - if (priv->ess_switch_flag == A_TRUE) - np = priv->of_node; - else if(priv->version == QCA_VER_AR8337 || priv->version == QCA_VER_AR8327) -#if (LINUX_VERSION_CODE >= KERNEL_VERSION(4,9,0)) - np = priv->phy->mdio.dev.of_node; -#else - np = priv->phy->dev.of_node; -#endif - else - SSDK_ERROR("cannot find np node!\n"); - - if(!np) - { - SSDK_ERROR("np is null !\n"); - return -1; - } - - link_polling_required = of_get_property(np, "link-polling-required", &len); - if (!link_polling_required ) - { - SSDK_INFO("link-polling-required node does not exist\n"); - return -1; - } - priv->link_polling_required = be32_to_cpup(link_polling_required); - if(!priv->link_polling_required) - { - link_intr_gpio = of_get_property(np, "link-intr-gpio", &len); - if (!link_intr_gpio ) - { - SSDK_ERROR("cannot find link-intr-gpio node\n"); - return -1; - } - if(config_gpio(be32_to_cpup(link_intr_gpio))) - return -1; - priv->link_interrupt_no = gpio_to_irq (be32_to_cpup(link_intr_gpio)); - SSDK_INFO("the interrupt number is:%x\n",priv->link_interrupt_no); - } - - return 0; -} - -int -qm_err_check_work_start(struct qca_phy_priv *priv) -{ - /*Only valid for S17c chip*/ - if (priv->version != QCA_VER_AR8337 && - priv->version != QCA_VER_AR8327 && - priv->version != QCA_VER_DESS) - { - return 0; - } - - mutex_init(&priv->qm_lock); - INIT_DELAYED_WORK(&priv->qm_dwork_polling, qm_err_check_work_task_polling); -#ifndef SSDK_MIB_CHANGE_WQ - schedule_delayed_work(&priv->qm_dwork_polling, - msecs_to_jiffies(QCA_QM_WORK_DELAY)); -#else - queue_delayed_work_on(0, system_long_wq, &priv->qm_dwork_polling, - msecs_to_jiffies(QCA_QM_WORK_DELAY)); -#endif - - return 0; -} - -void -qm_err_check_work_stop(struct qca_phy_priv *priv) -{ - /*Only valid for S17c chip*/ - if (priv->version != QCA_VER_AR8337 && - priv->version != QCA_VER_AR8327 && - priv->version != QCA_VER_DESS) return; - - cancel_delayed_work_sync(&priv->qm_dwork_polling); - -} -#ifdef DESS -static void -dess_rgmii_mac_work_task(struct work_struct *work) -{ - struct qca_phy_priv *priv = container_of(work, struct qca_phy_priv, - rgmii_dwork.work); - - mutex_lock(&priv->rgmii_lock); - - dess_rgmii_sw_mac_polling_task(priv); - - mutex_unlock(&priv->rgmii_lock); - - schedule_delayed_work(&priv->rgmii_dwork, msecs_to_jiffies(QCA_RGMII_WORK_DELAY)); -} - -int -dess_rgmii_mac_work_start(struct qca_phy_priv *priv) -{ - mutex_init(&priv->rgmii_lock); - - INIT_DELAYED_WORK(&priv->rgmii_dwork, dess_rgmii_mac_work_task); - - schedule_delayed_work(&priv->rgmii_dwork, msecs_to_jiffies(QCA_RGMII_WORK_DELAY)); - - return 0; -} - -void -dess_rgmii_mac_work_stop(struct qca_phy_priv *priv) -{ - cancel_delayed_work_sync(&priv->rgmii_dwork); -} -#endif - -void -qca_mac_port_status_init(a_uint32_t dev_id, a_uint32_t port_id) -{ - if(port_id < SSDK_PHYSICAL_PORT1 || port_id >= SW_MAX_NR_PORT) - { - SSDK_ERROR("port %d does not support status init\n", port_id); - return; - } - qca_phy_priv_global[dev_id]->port_old_link[port_id - 1] = 0; - qca_phy_priv_global[dev_id]->port_old_speed[port_id - 1] = FAL_SPEED_BUTT; - qca_phy_priv_global[dev_id]->port_old_duplex[port_id - 1] = FAL_DUPLEX_BUTT; - qca_phy_priv_global[dev_id]->port_old_tx_flowctrl[port_id - 1] = A_FALSE; - qca_phy_priv_global[dev_id]->port_old_rx_flowctrl[port_id - 1] = A_FALSE; - qca_phy_priv_global[dev_id]->port_tx_flowctrl_forcemode[port_id - 1] = A_FALSE; - qca_phy_priv_global[dev_id]->port_rx_flowctrl_forcemode[port_id - 1] = A_FALSE; -} - -void -qca_mac_sw_sync_port_status_init(a_uint32_t dev_id) -{ - a_uint32_t port_id; - - for (port_id = SSDK_PHYSICAL_PORT1; port_id < SW_MAX_NR_PORT; port_id ++) { - qca_mac_port_status_init(dev_id, port_id); - } -} -void -qca_mac_sw_sync_work_task(struct work_struct *work) -{ - adpt_api_t *p_adpt_api; - - struct qca_phy_priv *priv = container_of(work, struct qca_phy_priv, - mac_sw_sync_dwork.work); - - mutex_lock(&priv->mac_sw_sync_lock); - - if((p_adpt_api = adpt_api_ptr_get(priv->device_id)) != NULL) { - if (NULL == p_adpt_api->adpt_port_polling_sw_sync_set) - return; - p_adpt_api->adpt_port_polling_sw_sync_set(priv); - } - - mutex_unlock(&priv->mac_sw_sync_lock); - - schedule_delayed_work(&priv->mac_sw_sync_dwork, - msecs_to_jiffies(QCA_MAC_SW_SYNC_WORK_DELAY)); -} - -int -qca_mac_sw_sync_work_start(struct qca_phy_priv *priv) -{ - if ((priv->version != QCA_VER_HPPE) && (priv->version != QCA_VER_SCOMPHY)) - return 0; - - if (priv->version == QCA_VER_HPPE) { - qca_mac_sw_sync_port_status_init(priv->device_id); - } - - mutex_init(&priv->mac_sw_sync_lock); - - INIT_DELAYED_WORK(&priv->mac_sw_sync_dwork, - qca_mac_sw_sync_work_task); - schedule_delayed_work(&priv->mac_sw_sync_dwork, - msecs_to_jiffies(QCA_MAC_SW_SYNC_WORK_DELAY)); - - return 0; -} - -void -qca_mac_sw_sync_work_stop(struct qca_phy_priv *priv) -{ - if ((priv->version != QCA_VER_HPPE) && (priv->version != QCA_VER_SCOMPHY)) { - return; - } - cancel_delayed_work_sync(&priv->mac_sw_sync_dwork); -} - -void -qca_mac_sw_sync_work_resume(struct qca_phy_priv *priv) -{ - if ((priv->version != QCA_VER_HPPE) && (priv->version != QCA_VER_SCOMPHY)) { - return; - } - - schedule_delayed_work(&priv->mac_sw_sync_dwork, - msecs_to_jiffies(QCA_MAC_SW_SYNC_WORK_DELAY)); -} - -int -qca_phy_id_chip(struct qca_phy_priv *priv) -{ - a_uint32_t value, version; - - value = qca_ar8216_mii_read(priv->device_id, AR8327_REG_CTRL); - version = value & (AR8327_CTRL_REVISION | - AR8327_CTRL_VERSION); - priv->version = (version & AR8327_CTRL_VERSION) >> - AR8327_CTRL_VERSION_S; - priv->revision = (version & AR8327_CTRL_REVISION); - - if((priv->version == QCA_VER_AR8327) || - (priv->version == QCA_VER_AR8337) || - (priv->version == QCA_VER_AR8227)) { - return 0; - - } else { - SSDK_ERROR("unsupported QCA device\n"); - return -ENODEV; - } -} - -#if defined(IN_SWCONFIG) -static int qca_switchdev_register(struct qca_phy_priv *priv) -{ - struct switch_dev *sw_dev; - int ret = SW_OK; - sw_dev = &priv->sw_dev; - - switch (priv->version) { - case QCA_VER_AR8227: - sw_dev->name = "QCA AR8227"; - sw_dev->alias = "QCA AR8227"; - break; - case QCA_VER_AR8327: - sw_dev->name = "QCA AR8327"; - sw_dev->alias = "QCA AR8327"; - break; - case QCA_VER_AR8337: - sw_dev->name = "QCA AR8337"; - sw_dev->alias = "QCA AR8337"; - break; - case QCA_VER_DESS: - sw_dev->name = "QCA DESS"; - sw_dev->alias = "QCA DESS"; - break; - case QCA_VER_HPPE: - sw_dev->name = "QCA HPPE"; - sw_dev->alias = "QCA HPPE"; - break; - case QCA_VER_SCOMPHY: -#ifdef MP - if(adapt_scomphy_revision_get(priv->device_id) - == MP_GEPHY) - { - sw_dev->name = "QCA MP"; - sw_dev->alias = "QCA MP"; - } -#endif - break; - default: - sw_dev->name = "unknown switch"; - sw_dev->alias = "unknown switch"; - break; - } - - sw_dev->ops = &qca_ar8327_sw_ops; - sw_dev->vlans = AR8327_MAX_VLANS; - sw_dev->ports = priv->ports; - - ret = register_switch(sw_dev, NULL); - if (ret != SW_OK) { - SSDK_ERROR("register_switch failed for %s\n", sw_dev->name); - return ret; - } - - return ret; -} -#endif - -static int -qca_phy_config_init(struct phy_device *pdev) -{ - struct qca_phy_priv *priv = pdev->priv; - int ret = 0; - -#if (LINUX_VERSION_CODE >= KERNEL_VERSION(4,9,0)) - if (pdev->mdio.addr != 0) { -#else - if (pdev->addr != 0) { -#endif - -#if (LINUX_VERSION_CODE < KERNEL_VERSION(5, 0, 0)) - pdev->supported |= SUPPORTED_1000baseT_Full; - pdev->advertising |= ADVERTISED_1000baseT_Full; -#else - linkmode_set_bit(ETHTOOL_LINK_MODE_1000baseT_Full_BIT, - pdev->supported); - linkmode_set_bit(ETHTOOL_LINK_MODE_1000baseT_Full_BIT, - pdev->advertising); -#endif - -#ifndef BOARD_AR71XX -#if defined(CONFIG_OF) && (LINUX_VERSION_CODE >= KERNEL_VERSION(3,14,0)) - ssdk_phy_rgmii_set(priv); -#endif -#endif - return 0; - } - - if (priv == NULL) - return -ENOMEM; - - priv->phy = pdev; - ret = qca_phy_id_chip(priv); - if (ret != 0) { - return ret; - } - - priv->mii_read = qca_ar8216_mii_read; - priv->mii_write = qca_ar8216_mii_write; - priv->phy_write = qca_ar8327_phy_write; - priv->phy_read = qca_ar8327_phy_read; - priv->phy_dbg_write = qca_ar8327_phy_dbg_write; - priv->phy_dbg_read = qca_ar8327_phy_dbg_read; - priv->phy_mmd_write = qca_ar8327_mmd_write; - priv->ports = AR8327_NUM_PORTS; - - ret = qca_link_polling_select(priv); - if(ret) - priv->link_polling_required = 1; - pdev->priv = priv; -#if (LINUX_VERSION_CODE < KERNEL_VERSION(5, 0, 0)) - pdev->supported |= SUPPORTED_1000baseT_Full; - pdev->advertising |= ADVERTISED_1000baseT_Full; -#else - linkmode_set_bit(ETHTOOL_LINK_MODE_1000baseT_Full_BIT, - pdev->supported); - linkmode_set_bit(ETHTOOL_LINK_MODE_1000baseT_Full_BIT, - pdev->advertising); -#endif - -#if defined(IN_SWCONFIG) - ret = qca_switchdev_register(priv); - if (ret != SW_OK) { - return ret; - } -#endif - priv->qca_ssdk_sw_dev_registered = A_TRUE; - - snprintf(priv->link_intr_name, IFNAMSIZ, "switch0"); - - ret = qca_ar8327_hw_init(priv); - if (ret != 0) { - return ret; - } - - qca_phy_mib_work_start(priv); - - if(priv->link_polling_required) - { - SSDK_INFO("polling is selected\n"); - ret = qm_err_check_work_start(priv); - if (ret != 0) - { - SSDK_ERROR("qm_err_check_work_start failed for chip 0x%02x%02x\n", priv->version, priv->revision); - return ret; - } - } - else - { - SSDK_INFO("interrupt is selected\n"); - priv->interrupt_flag = IRQF_TRIGGER_LOW; - ret = qca_intr_init(priv); - if(ret) - SSDK_ERROR("the interrupt init faild !\n"); - } - - return ret; -} - -#if defined(DESS) || defined(HPPE) || defined (ISISC) || defined (ISIS) || defined(MP) -static int ssdk_switch_register(a_uint32_t dev_id, ssdk_chip_type chip_type) -{ - struct qca_phy_priv *priv; - int ret = 0; - a_uint32_t chip_id = 0; - priv = qca_phy_priv_global[dev_id]; - - priv->mii_read = qca_ar8216_mii_read; - priv->mii_write = qca_ar8216_mii_write; - priv->phy_write = qca_ar8327_phy_write; - priv->phy_read = qca_ar8327_phy_read; - priv->phy_dbg_write = qca_ar8327_phy_dbg_write; - priv->phy_dbg_read = qca_ar8327_phy_dbg_read; - priv->phy_mmd_write = qca_ar8327_mmd_write; - - if (chip_type == CHIP_DESS) { - priv->ports = 6; - } else if ((chip_type == CHIP_ISIS) || (chip_type == CHIP_ISISC)) { - priv->ports = 7; - } else if (chip_type == CHIP_SCOMPHY) { -#ifdef MP - if(adapt_scomphy_revision_get(priv->device_id) == MP_GEPHY) { - /*for ipq50xx, port id is 1 and 2, port 0 is not available*/ - priv->ports = 3; - } -#endif - } else { - priv->ports = SSDK_MAX_PORT_NUM; - } - -#ifdef MP - if(chip_type == CHIP_SCOMPHY) - { - priv->version = QCA_VER_SCOMPHY; - SSDK_INFO("Chip version 0x%02x\n", priv->version); - } - else -#endif - { - if (fal_reg_get(dev_id, 0, (a_uint8_t *)&chip_id, 4) == SW_OK) { - priv->version = ((chip_id >> 8) & 0xff); - priv->revision = (chip_id & 0xff); - SSDK_INFO("Chip version 0x%02x%02x\n", priv->version, priv->revision); - } - } - - mutex_init(&priv->reg_mutex); - -#if defined(IN_SWCONFIG) - ret = qca_switchdev_register(priv); - if (ret != SW_OK) { - return ret; - } -#endif - - snprintf(priv->link_intr_name, IFNAMSIZ, "switch%d", dev_id); - - priv->qca_ssdk_sw_dev_registered = A_TRUE; - ret = qca_phy_mib_work_start(qca_phy_priv_global[dev_id]); - if (ret != 0) { - SSDK_ERROR("qca_phy_mib_work_start failed for chip 0x%02x%02x\n", priv->version, priv->revision); - return ret; - } - ret = qca_link_polling_select(priv); - if(ret) - priv->link_polling_required = 1; - if(priv->link_polling_required) - { - SSDK_INFO("polling is selected\n"); - ret = qm_err_check_work_start(priv); - if (ret != 0) - { - SSDK_ERROR("qm_err_check_work_start failed for chip 0x%02x%02x\n", priv->version, priv->revision); - return ret; - } - } - else - { - SSDK_INFO("interrupt is selected\n"); - priv->interrupt_flag = IRQF_TRIGGER_MASK; - ret = qca_intr_init(priv); - if(ret) - { - SSDK_ERROR("the interrupt init faild !\n"); - return ret; - } - } - -#if 0 -#ifdef DESS - if ((ssdk_dt_global.mac_mode == PORT_WRAPPER_SGMII0_RGMII5) - ||(ssdk_dt_global.mac_mode == PORT_WRAPPER_SGMII1_RGMII5) - ||(ssdk_dt_global.mac_mode == PORT_WRAPPER_SGMII0_RGMII4) - ||(ssdk_dt_global.mac_mode == PORT_WRAPPER_SGMII1_RGMII4) - ||(ssdk_dt_global.mac_mode == PORT_WRAPPER_SGMII4_RGMII4)) { - ret = dess_rgmii_mac_work_start(priv); - if (ret != 0) { - SSDK_ERROR("dess_rgmii_mac_work_start failed for chip 0x%02x%02x\n", priv->version, priv->revision); - return ret; - } - } -#endif -#endif -#ifdef HPPE - if (priv->version == QCA_VER_HPPE) { - ret = qca_mac_sw_sync_work_start(priv); - if (ret != 0) { - SSDK_ERROR("qca_mac_sw_sync_work_start failed for chip 0x%02x%02x\n", - priv->version, priv->revision); - return ret; - } - } -#endif - - return 0; - -} - -static int ssdk_switch_unregister(a_uint32_t dev_id) -{ - qca_phy_mib_work_stop(qca_phy_priv_global[dev_id]); - qm_err_check_work_stop(qca_phy_priv_global[dev_id]); -#ifdef HPPE - qca_mac_sw_sync_work_stop(qca_phy_priv_global[dev_id]); -#endif -#if defined(IN_SWCONFIG) - unregister_switch(&qca_phy_priv_global[dev_id]->sw_dev); -#endif - return 0; -} -#endif - -static int -qca_phy_read_status(struct phy_device *pdev) -{ - struct qca_phy_priv *priv = pdev->priv; - a_uint32_t port_status; - a_uint32_t port_speed; - int ret = 0, addr = 0; - -#if (LINUX_VERSION_CODE >= KERNEL_VERSION(4,9,0)) - addr = pdev->mdio.addr; -#else - addr = pdev->addr; -#endif - if (addr != 0) { - mutex_lock(&priv->reg_mutex); - ret = genphy_read_status(pdev); - mutex_unlock(&priv->reg_mutex); - return ret; - } - - mutex_lock(&priv->reg_mutex); - port_status = priv->mii_read(priv->device_id, AR8327_REG_PORT_STATUS(addr)); - mutex_unlock(&priv->reg_mutex); - - pdev->link = 1; - if (port_status & AR8327_PORT_STATUS_LINK_AUTO) { - pdev->link = !!(port_status & AR8327_PORT_STATUS_LINK_UP); - if (pdev->link == 0) { - return ret; - } - } - - port_speed = (port_status & AR8327_PORT_STATUS_SPEED) >> - AR8327_PORT_STATUS_SPEED_S; - - switch (port_speed) { - case AR8327_PORT_SPEED_10M: - pdev->speed = SPEED_10; - break; - case AR8327_PORT_SPEED_100M: - pdev->speed = SPEED_100; - break; - case AR8327_PORT_SPEED_1000M: - pdev->speed = SPEED_1000; - break; - default: - pdev->speed = 0; - break; - } - - if(port_status & AR8327_PORT_STATUS_DUPLEX) { - pdev->duplex = DUPLEX_FULL; - } else { - pdev->duplex = DUPLEX_HALF; - } - - pdev->state = PHY_RUNNING; - netif_carrier_on(pdev->attached_dev); - pdev->adjust_link(pdev->attached_dev); - - return ret; -} - -static int -qca_phy_config_aneg(struct phy_device *pdev) -{ -#if (LINUX_VERSION_CODE >= KERNEL_VERSION(4,9,0)) - if (pdev->mdio.addr != 0) { -#else - if (pdev->addr != 0) { -#endif - return genphy_config_aneg(pdev); - } - - return 0; -} - -int qca_phy_suspend(struct phy_device *phydev) -{ -#if (LINUX_VERSION_CODE >= KERNEL_VERSION(4,9,0)) - struct mii_bus *bus = phydev->mdio.bus; -#else - struct mii_bus *bus = phydev->bus; -#endif - int val = 0; - int addr; - -#if (LINUX_VERSION_CODE >= KERNEL_VERSION(4,9,0)) - addr = phydev->mdio.addr; -#else - addr = phydev->addr; -#endif - - val = mdiobus_read(bus, addr, MII_BMCR); - return mdiobus_write(bus, addr, MII_BMCR, (u16)(val | BMCR_PDOWN)); -} - -int qca_phy_resume(struct phy_device *phydev) -{ -#if (LINUX_VERSION_CODE >= KERNEL_VERSION(4,9,0)) - struct mii_bus *bus = phydev->mdio.bus; -#else - struct mii_bus *bus = phydev->bus; -#endif - int val = 0; - int addr; - -#if (LINUX_VERSION_CODE >= KERNEL_VERSION(4,9,0)) - addr = phydev->mdio.addr; -#else - addr = phydev->addr; -#endif - - val = mdiobus_read(bus, addr, MII_BMCR); - return mdiobus_write(bus, addr, MII_BMCR, (u16)(val & ~BMCR_PDOWN)); -} - -static int -qca_phy_probe(struct phy_device *pdev) -{ - struct qca_phy_priv *priv; - int ret; - - priv = kzalloc(sizeof(struct qca_phy_priv), GFP_KERNEL); - if (priv == NULL) { - return -ENOMEM; - } - - pdev->priv = priv; - priv->phy = pdev; - mutex_init(&priv->reg_mutex); - - ret = qca_phy_id_chip(priv); - return ret; -} - -static void -qca_phy_remove(struct phy_device *pdev) -{ - struct qca_phy_priv *priv = pdev->priv; - int addr; -#if (LINUX_VERSION_CODE >= KERNEL_VERSION(4,9,0)) - addr = pdev->mdio.addr; -#else - addr = pdev->addr; -#endif - - if ((addr == 0) && priv && (priv->ports != 0)) { - qca_phy_mib_work_stop(priv); - qm_err_check_work_stop(priv); -#if defined(IN_SWCONFIG) - if (priv->sw_dev.name != NULL) - unregister_switch(&priv->sw_dev); -#endif - } - - if (priv) { - kfree(priv); - } -} - -static struct phy_driver qca_phy_driver = { - .name = "QCA AR8216 AR8236 AR8316 AR8327 AR8337", - .phy_id = 0x004d0000, - .phy_id_mask= 0xffff0000, - .probe = qca_phy_probe, - .remove = qca_phy_remove, - .config_init= &qca_phy_config_init, - .config_aneg= &qca_phy_config_aneg, - .read_status= &qca_phy_read_status, - .suspend = qca_phy_suspend, - .resume = qca_phy_resume, - .features = PHY_BASIC_FEATURES, -#if (LINUX_VERSION_CODE >= KERNEL_VERSION(4,9,0)) - .mdiodrv.driver = { .owner = THIS_MODULE }, -#else - .driver = { .owner = THIS_MODULE }, -#endif -}; - -#ifndef BOARD_AR71XX -#if defined(CONFIG_OF) && (LINUX_VERSION_CODE >= KERNEL_VERSION(3,14,0)) -#ifdef DESS -struct reset_control *ess_rst = NULL; -struct reset_control *ess_mac_clock_disable[5] = {NULL,NULL,NULL,NULL,NULL}; - -void ssdk_ess_reset(void) -{ - if (!ess_rst) - return; - reset_control_assert(ess_rst); - mdelay(10); - reset_control_deassert(ess_rst); - mdelay(100); -} -#endif - -char ssdk_driver_name[] = "ess_ssdk"; - -static int ssdk_probe(struct platform_device *pdev) -{ - struct device_node *np; - - np = of_node_get(pdev->dev.of_node); - if (of_device_is_compatible(np, "qcom,ess-instance")) - return of_platform_populate(np, NULL, NULL, &pdev->dev); - -#ifdef DESS - ess_rst = devm_reset_control_get(&pdev->dev, "ess_rst"); - ess_mac_clock_disable[0] = devm_reset_control_get(&pdev->dev, "ess_mac1_clk_dis"); - ess_mac_clock_disable[1] = devm_reset_control_get(&pdev->dev, "ess_mac2_clk_dis"); - ess_mac_clock_disable[2] = devm_reset_control_get(&pdev->dev, "ess_mac3_clk_dis"); - ess_mac_clock_disable[3] = devm_reset_control_get(&pdev->dev, "ess_mac4_clk_dis"); - ess_mac_clock_disable[4] = devm_reset_control_get(&pdev->dev, "ess_mac5_clk_dis"); - - if (IS_ERR(ess_rst)) { - SSDK_INFO("ess_rst doesn't exist!\n"); - return 0; - } - if (!ess_mac_clock_disable[0]) { - SSDK_ERROR("ess_mac1_clock_disable fail!\n"); - return -1; - } - if (!ess_mac_clock_disable[1]) { - SSDK_ERROR("ess_mac2_clock_disable fail!\n"); - return -1; - } - if (!ess_mac_clock_disable[2]) { - SSDK_ERROR("ess_mac3_clock_disable fail!\n"); - return -1; - } - if (!ess_mac_clock_disable[3]) { - SSDK_ERROR("ess_mac4_clock_disable fail!\n"); - return -1; - } - if (!ess_mac_clock_disable[4]) { - SSDK_ERROR("ess_mac5_clock_disable fail!\n"); - return -1; - } -#endif - return 0; -} - -static const struct of_device_id ssdk_of_mtable[] = { - {.compatible = "qcom,ess-switch" }, - {.compatible = "qcom,ess-switch-ipq60xx" }, - {.compatible = "qcom,ess-switch-ipq807x" }, - {.compatible = "qcom,ess-instance" }, - {} -}; - -static struct platform_driver ssdk_driver = { - .driver = { - .name = ssdk_driver_name, - .owner = THIS_MODULE, - .of_match_table = ssdk_of_mtable, - }, - .probe = ssdk_probe, -}; -#endif -#endif -#ifdef DESS -static u32 phy_t_status = 0; -static a_uint16_t modectrl_data = 0; -void ssdk_malibu_psgmii_and_dakota_dess_reset(a_uint32_t dev_id, a_uint32_t first_phy_addr) -{ -#ifndef BOARD_AR71XX -#if defined(CONFIG_OF) && (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 14, 0)) - int m = 0, n = 0; - a_uint32_t psgmii_phy_addr; - - psgmii_phy_addr = first_phy_addr + 5; - - /*reset Malibu PSGMII and Dakota ESS start*/ - qca_ar8327_phy_write(dev_id, psgmii_phy_addr, 0x0, 0x005b);/*fix phy psgmii RX 20bit*/ - qca_ar8327_phy_write(dev_id, psgmii_phy_addr, 0x0, 0x001b);/*reset phy psgmii*/ - qca_ar8327_phy_write(dev_id, psgmii_phy_addr, 0x0, 0x005b);/*release reset phy psgmii*/ - /* mdelay(100); this 100ms be replaced with below malibu psgmii calibration process*/ - /*check malibu psgmii calibration done start*/ - n = 0; - while (n < 100) { - u16 status; - status = qca_phy_mmd_read(dev_id, psgmii_phy_addr, 1, 0x28); - if (status & BIT(0)) - break; - mdelay(10); - n++; - } -#ifdef PSGMII_DEBUG - if (n >= 100) - SSDK_INFO("MALIBU PSGMII PLL_VCO_CALIB NOT READY\n"); -#endif - mdelay(50); - /*check malibu psgmii calibration done end..*/ - qca_ar8327_phy_write(dev_id, psgmii_phy_addr, 0x1a, 0x2230);/*freeze phy psgmii RX CDR*/ - - ssdk_ess_reset(); - /*check dakota psgmii calibration done start*/ - m = 0; - while (m < 100) { - u32 status = 0; - qca_psgmii_reg_read(dev_id, 0xa0, (a_uint8_t *)&status, 4); - if (status & BIT(0)) - break; - mdelay(10); - m++; - } -#ifdef PSGMII_DEBUG - if (m >= 100) - SSDK_INFO("DAKOTA PSGMII PLL_VCO_CALIB NOT READY\n"); -#endif - mdelay(50); - /*check dakota psgmii calibration done end..*/ - qca_ar8327_phy_write(dev_id, psgmii_phy_addr, 0x1a, 0x3230);/*relesae phy psgmii RX CDR*/ - qca_ar8327_phy_write(dev_id, psgmii_phy_addr, 0x0, 0x005f);/*release phy psgmii RX 20bit*/ - mdelay(200); -#endif -#endif - /*reset Malibu PSGMII and Dakota ESS end*/ - return; -} - -static void ssdk_psgmii_phy_testing_printf(a_uint32_t phy, u32 tx_ok, u32 rx_ok, - u32 tx_counter_error, u32 rx_counter_error) -{ - SSDK_INFO("tx_ok = 0x%x, rx_ok = 0x%x, tx_counter_error = 0x%x, rx_counter_error = 0x%x\n", - tx_ok, rx_ok, tx_counter_error, rx_counter_error); - if (tx_ok== 0x3000 && tx_counter_error == 0) - SSDK_INFO("PHY %d single PSGMII test pass\n", phy); - else - SSDK_ERROR("PHY %d single PSGMII test fail\n", phy); - return; - -} -static void ssdk_psgmii_all_phy_testing_printf(a_uint32_t phy, u32 tx_ok, u32 rx_ok, - u32 tx_counter_error, u32 rx_counter_error) -{ - SSDK_INFO("tx_ok = 0x%x, rx_ok = 0x%x, tx_counter_error = 0x%x, rx_counter_error = 0x%x\n", - tx_ok, rx_ok, tx_counter_error, rx_counter_error); - if (tx_ok== 0x3000 && tx_counter_error == 0) - SSDK_INFO("PHY %d all PSGMII test pass\n", phy); - else - SSDK_ERROR("PHY %d all PSGMII test fail\n", phy); - return; - -} -void ssdk_psgmii_single_phy_testing(a_uint32_t dev_id, a_uint32_t phy, a_bool_t enable) -{ - int j = 0; - - u32 tx_counter_ok, tx_counter_error; - u32 rx_counter_ok, rx_counter_error; - u32 tx_counter_ok_high16; - u32 rx_counter_ok_high16; - u32 tx_ok, rx_ok; - qca_ar8327_phy_write(dev_id, phy, 0x0, 0x9000); - qca_ar8327_phy_write(dev_id, phy, 0x0, 0x4140); - j = 0; - while (j < 100) { - u16 status = 0; - qca_ar8327_phy_read(dev_id, phy, 0x11, &status); - if (status & (1 << 10)) - break; - mdelay(10); - j++; - } - /*add a 300ms delay as qm polling task existing*/ - if (enable == A_TRUE) - mdelay(300); - - /*enable check*/ - qca_phy_mmd_write(dev_id, phy, 7, 0x8029, 0x0000); - qca_phy_mmd_write(dev_id, phy, 7, 0x8029, 0x0003); - - /*start traffic*/ - qca_phy_mmd_write(dev_id, phy, 7, 0x8020, 0xa000); - mdelay(200); - - /*check counter*/ - tx_counter_ok = qca_phy_mmd_read(dev_id, phy, 7, 0x802e); - tx_counter_ok_high16 = qca_phy_mmd_read(dev_id, phy, 7, 0x802d); - tx_counter_error = qca_phy_mmd_read(dev_id, phy, 7, 0x802f); - rx_counter_ok = qca_phy_mmd_read(dev_id, phy, 7, 0x802b); - rx_counter_ok_high16 = qca_phy_mmd_read(dev_id, phy, 7, 0x802a); - rx_counter_error = qca_phy_mmd_read(dev_id, phy, 7, 0x802c); - tx_ok = tx_counter_ok + (tx_counter_ok_high16<<16); - rx_ok = rx_counter_ok + (rx_counter_ok_high16<<16); - if (tx_ok== 0x3000 && tx_counter_error == 0) { - /*success*/ - phy_t_status &= (~(1<= (first_phy_addr + 5)) - break; - mdelay(10); - j++; - } - /*add a 300ms delay as qm polling task existing*/ - if (enable == A_TRUE) - mdelay(300); - - /*enable check*/ - qca_phy_mmd_write(dev_id, 0x1f, 7, 0x8029, 0x0000); - qca_phy_mmd_write(dev_id, 0x1f, 7, 0x8029, 0x0003); - - /*start traffic*/ - qca_phy_mmd_write(dev_id, 0x1f, 7, 0x8020, 0xa000); - mdelay(200); - for (phy = first_phy_addr; phy < first_phy_addr + 5; phy++) { - u32 tx_counter_ok, tx_counter_error; - u32 rx_counter_ok, rx_counter_error; - u32 tx_counter_ok_high16; - u32 rx_counter_ok_high16; - u32 tx_ok, rx_ok; - /*check counter*/ - tx_counter_ok = qca_phy_mmd_read(dev_id, phy, 7, 0x802e); - tx_counter_ok_high16 = qca_phy_mmd_read(dev_id, phy, 7, 0x802d); - tx_counter_error = qca_phy_mmd_read(dev_id, phy, 7, 0x802f); - rx_counter_ok = qca_phy_mmd_read(dev_id, phy, 7, 0x802b); - rx_counter_ok_high16 = qca_phy_mmd_read(dev_id, phy, 7, 0x802a); - rx_counter_error = qca_phy_mmd_read(dev_id, phy, 7, 0x802c); - tx_ok = tx_counter_ok + (tx_counter_ok_high16<<16); - rx_ok = rx_counter_ok + (rx_counter_ok_high16<<16); - if (tx_ok== 0x3000 && tx_counter_error == 0) { - /*success*/ - phy_t_status &= (~(1<<(phy+8))); - } else { - phy_t_status |= (1<<(phy+8)); - } - - if (enable == A_TRUE) - ssdk_psgmii_all_phy_testing_printf(phy, tx_ok, - rx_ok, - tx_counter_error, rx_counter_error); - } - if (enable == A_TRUE) - SSDK_INFO("PHY final test result: 0x%x \r\n",phy_t_status); - -} - -void ssdk_psgmii_get_first_phy_address(a_uint32_t dev_id, - a_uint32_t *first_phy_addr) -{ - a_uint32_t port_id = 0, phy_addr = 0, phy_cnt = 0; - a_uint32_t port_bmp[SW_MAX_NR_DEV] = {0}; - - port_bmp[dev_id] = qca_ssdk_phy_type_port_bmp_get(dev_id, MALIBU_PHY_CHIP); - - for (port_id = 0; port_id < SW_MAX_NR_PORT; port_id ++) - { - if (port_bmp[dev_id] & (0x1 << port_id)) - { - phy_cnt ++; - phy_addr = qca_ssdk_port_to_phy_addr(dev_id, port_id); - if (phy_addr < *first_phy_addr) { - *first_phy_addr = phy_addr; - } - } - } - if ((phy_cnt == QCA8072_PHY_NUM) && (*first_phy_addr >= 0x3)) { - *first_phy_addr = *first_phy_addr - 3; - } -} - -void ssdk_psgmii_self_test(a_uint32_t dev_id, a_bool_t enable, a_uint32_t times, - a_uint32_t *result) -{ - int i = 0; - u32 value = 0; - a_uint32_t first_phy_addr = MAX_PHY_ADDR + 1, phy = 0; - - ssdk_psgmii_get_first_phy_address(dev_id, &first_phy_addr); - if ((first_phy_addr < 0) || (first_phy_addr > MAX_PHY_ADDR)) { - return; - } - - if (enable == A_FALSE) { - ssdk_malibu_psgmii_and_dakota_dess_reset(dev_id, first_phy_addr); - } - - qca_ar8327_phy_read(dev_id, first_phy_addr + 4, 0x1f, &modectrl_data); - qca_ar8327_phy_write(dev_id, first_phy_addr + 4, 0x1f, 0x8500);/*switch to access MII reg for copper*/ - for(phy = first_phy_addr; phy < first_phy_addr + 5; phy++) { - /*enable phy mdio broadcast write*/ - qca_phy_mmd_write(dev_id, phy, 7, 0x8028, 0x801f); - } - - /* force no link by power down */ - qca_ar8327_phy_write(dev_id, 0x1f, 0x0, 0x1840); - - /*packet number*/ - qca_phy_mmd_write(dev_id, 0x1f, 7, 0x8021, 0x3000); - qca_phy_mmd_write(dev_id, 0x1f, 7, 0x8062, 0x05e0); - - /*fix mdi status */ - qca_ar8327_phy_write(dev_id, 0x1f, 0x10, 0x6800); - - for(i = 0; i < times; i++) { - phy_t_status = 0; - - for(phy = 0; phy < 5; phy++) { - value = readl(qca_phy_priv_global[dev_id]->hw_addr + 0x66c + phy * 0xc); - writel((value|(1<<21)), (qca_phy_priv_global[dev_id]->hw_addr + 0x66c + phy * 0xc)); - } - - for (phy = first_phy_addr; phy < first_phy_addr + 5; phy++) { - ssdk_psgmii_single_phy_testing(dev_id, phy, enable); - } - ssdk_psgmii_all_phy_testing(dev_id, first_phy_addr, enable); - if (enable == A_FALSE) { - if (phy_t_status) { - ssdk_malibu_psgmii_and_dakota_dess_reset(dev_id, first_phy_addr); - } - else - { - break; - } - } - } - - *result = phy_t_status; -#ifdef PSGMII_DEBUG - if (i>=100) - SSDK_ERROR("PSGMII cannot recover\n"); - else - SSDK_INFO("PSGMII recovered after %d times reset\n",i); -#endif - /*configuration recover*/ - /*packet number*/ - qca_phy_mmd_write(dev_id, 0x1f, 7, 0x8021, 0x0); - /*disable check*/ - qca_phy_mmd_write(dev_id, 0x1f, 7, 0x8029, 0x0); - /*disable traffic*/ - qca_phy_mmd_write(dev_id, 0x1f, 7, 0x8020, 0x0); -} - - -void clear_self_test_config(a_uint32_t dev_id) -{ - u32 value = 0; - a_uint32_t first_phy_addr = MAX_PHY_ADDR + 1, phy = 0; - - ssdk_psgmii_get_first_phy_address(dev_id, &first_phy_addr); - if ((first_phy_addr < 0) || (first_phy_addr > MAX_PHY_ADDR)) { - return; - } - - /* disable EEE */ - /* qca_phy_mmd_write(0, 0x1f, 0x7, 0x3c, 0x0); */ - - /*disable phy internal loopback*/ - qca_ar8327_phy_write(dev_id, 0x1f, 0x10, 0x6860); - qca_ar8327_phy_write(dev_id, 0x1f, 0x0, 0x9040); - - for(phy = 0; phy < 5; phy++) - { - /*disable mac loop back*/ - value = readl(qca_phy_priv_global[dev_id]->hw_addr+0x66c+phy*0xc); - writel((value&(~(1<<21))), (qca_phy_priv_global[dev_id]->hw_addr+0x66c+phy*0xc)); - } - - for(phy = first_phy_addr; phy < first_phy_addr + 5; phy++) - { - /*diable phy mdio broadcast write*/ - qca_phy_mmd_write(dev_id, phy, 7, 0x8028, 0x001f); - - } - - qca_ar8327_phy_write(dev_id, first_phy_addr + 4, 0x1f, modectrl_data); - - /* clear fdb entry */ - fal_fdb_entry_flush(dev_id,1); -} -#endif -/*qca808x_start*/ -sw_error_t -ssdk_init(a_uint32_t dev_id, ssdk_init_cfg * cfg) -{ - sw_error_t rv; - - rv = fal_init(dev_id, cfg); - if (rv != SW_OK) - SSDK_ERROR("ssdk fal init failed: %d. \r\n", rv); - - rv = ssdk_phy_driver_init(dev_id, cfg); - if (rv != SW_OK) - SSDK_ERROR("ssdk phy init failed: %d. \r\n", rv); - - return rv; -} - -sw_error_t -ssdk_cleanup(void) -{ - sw_error_t rv; - - rv = fal_cleanup(); - rv = ssdk_phy_driver_cleanup(); - - return rv; -} -/*qca808x_end*/ - -sw_error_t -ssdk_hsl_access_mode_set(a_uint32_t dev_id, hsl_access_mode reg_mode) -{ - sw_error_t rv; - - rv = hsl_access_mode_set(dev_id, reg_mode); - return rv; -} - -void switch_cpuport_setup(a_uint32_t dev_id) -{ -#ifdef IN_PORTCONTROL - //According to HW suggestion, enable CPU port flow control for Dakota - fal_port_flowctrl_forcemode_set(dev_id, 0, A_TRUE); - fal_port_flowctrl_set(dev_id, 0, A_TRUE); - fal_port_duplex_set(dev_id, 0, FAL_FULL_DUPLEX); - fal_port_speed_set(dev_id, 0, FAL_SPEED_1000); - udelay(10); - fal_port_txmac_status_set(dev_id, 0, A_TRUE); - fal_port_rxmac_status_set(dev_id, 0, A_TRUE); -#endif -} -#ifdef IN_AQUANTIA_PHY -#ifdef CONFIG_MDIO -static struct mdio_if_info ssdk_mdio_ctl; -#endif -static struct net_device *ssdk_miireg_netdev = NULL; - -static int ssdk_miireg_open(struct net_device *netdev) -{ - return 0; -} -static int ssdk_miireg_close(struct net_device *netdev) -{ - return 0; -} - -static int ssdk_miireg_do_ioctl(struct net_device *netdev, - struct ifreq *ifr, int32_t cmd) -{ - int ret = -EINVAL; -#ifdef CONFIG_MDIO - struct mii_ioctl_data *mii_data = if_mii(ifr); - ret = mdio_mii_ioctl(&ssdk_mdio_ctl, mii_data, cmd); -#endif - return ret; -} - -static const struct net_device_ops ssdk_netdev_ops = { - .ndo_open = &ssdk_miireg_open, - .ndo_stop = &ssdk_miireg_close, - .ndo_do_ioctl = &ssdk_miireg_do_ioctl, -}; - -#ifdef CONFIG_MDIO -extern struct mutex switch_mdio_lock; -static int ssdk_miireg_ioctl_read(struct net_device *netdev, int phy_addr, int mmd, uint16_t addr) -{ - a_uint32_t reg = 0; - a_uint16_t val = 0; - - if (MDIO_DEVAD_NONE == mmd) { - qca_ar8327_phy_read(0, phy_addr, addr, &val); - return (int)val; - } - - reg = MII_ADDR_C45 | mmd << 16 | addr; - mutex_lock(&switch_mdio_lock); - qca_ar8327_phy_read(0, phy_addr, reg, &val); - mutex_unlock(&switch_mdio_lock); - - return (int)val; -} - -static int ssdk_miireg_ioctl_write(struct net_device *netdev, int phy_addr, int mmd, - uint16_t addr, uint16_t value) -{ - a_uint32_t reg = 0; - - if (MDIO_DEVAD_NONE == mmd) { - qca_ar8327_phy_write(0, phy_addr, addr, value); - return 0; - } - - reg = MII_ADDR_C45 | mmd << 16 | addr; - mutex_lock(&switch_mdio_lock); - qca_ar8327_phy_write(0, phy_addr, reg, value); - mutex_unlock(&switch_mdio_lock); - - return 0; -} -#endif - -static void ssdk_netdev_setup(struct net_device *dev) -{ - dev->netdev_ops = &ssdk_netdev_ops; -} -static void ssdk_miireg_ioctrl_register(void) -{ - if (ssdk_miireg_netdev) - return; -#ifdef CONFIG_MDIO - ssdk_mdio_ctl.mdio_read = ssdk_miireg_ioctl_read; - ssdk_mdio_ctl.mdio_write = ssdk_miireg_ioctl_write; - ssdk_mdio_ctl.mode_support = MDIO_SUPPORTS_C45; -#endif - -#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3,18,0)) - ssdk_miireg_netdev = alloc_netdev(100, "miireg", 0, ssdk_netdev_setup); -#else - ssdk_miireg_netdev = alloc_netdev(100, "miireg", ssdk_netdev_setup); -#endif - if (ssdk_miireg_netdev) - register_netdev(ssdk_miireg_netdev); -} - -static void ssdk_miireg_ioctrl_unregister(void) -{ - if (ssdk_miireg_netdev) { - unregister_netdev(ssdk_miireg_netdev); - kfree(ssdk_miireg_netdev); - ssdk_miireg_netdev = NULL; - } -} -#endif -static void ssdk_driver_register(a_uint32_t dev_id) -{ - hsl_reg_mode reg_mode; - a_bool_t flag; - - reg_mode = ssdk_switch_reg_access_mode_get(dev_id); - - if(reg_mode == HSL_REG_LOCAL_BUS) { -#ifndef BOARD_AR71XX -#if defined(CONFIG_OF) && (LINUX_VERSION_CODE >= KERNEL_VERSION(3,14,0)) - platform_driver_register(&ssdk_driver); -#endif -#endif - } - - flag = ssdk_ess_switch_flag_get(dev_id); - if(reg_mode == HSL_REG_MDIO && flag == A_FALSE) { - if(driver_find(qca_phy_driver.name, &mdio_bus_type)){ - SSDK_ERROR("QCA PHY driver had been Registered\n"); - return; - } - - SSDK_INFO("Register QCA PHY driver\n"); -#if (LINUX_VERSION_CODE >= KERNEL_VERSION(4,9,0)) - phy_driver_register(&qca_phy_driver, THIS_MODULE); -#else - phy_driver_register(&qca_phy_driver); -#endif - -#ifdef BOARD_AR71XX -#if defined(IN_SWCONFIG) - ssdk_uci_takeover_init(); -#endif - -#ifdef CONFIG_AR8216_PHY - ar8327_port_link_notify_register(ssdk_port_link_notify); -#endif - ar7240_port_link_notify_register(ssdk_port_link_notify); -#endif - } -} - -static void ssdk_driver_unregister(a_uint32_t dev_id) -{ - hsl_reg_mode reg_mode; - a_bool_t flag; - - reg_mode= ssdk_switch_reg_access_mode_get(dev_id); - flag = ssdk_ess_switch_flag_get(dev_id); - if(reg_mode == HSL_REG_MDIO && flag == A_FALSE) { - phy_driver_unregister(&qca_phy_driver); - -#if defined(BOARD_AR71XX) && defined(IN_SWCONFIG) - ssdk_uci_takeover_exit(); -#endif - } - - if (reg_mode == HSL_REG_LOCAL_BUS) { -#ifndef BOARD_AR71XX -#if defined(CONFIG_OF) && (LINUX_VERSION_CODE >= KERNEL_VERSION(3,14,0)) - platform_driver_unregister(&ssdk_driver); -#endif -#endif - } -} -/*qca808x_start*/ -static int chip_is_scomphy(a_uint32_t dev_id, ssdk_init_cfg* cfg) -{ - int rv = -ENODEV; - a_uint32_t phy_id = 0, port_id = 0; - a_uint32_t port_bmp = qca_ssdk_port_bmp_get(dev_id); - while (port_bmp) { - if (port_bmp & 0x1) { - phy_id = hsl_phyid_get(dev_id, port_id, cfg); - switch (phy_id) { -/*qca808x_end*/ - case QCA8030_PHY: - case QCA8033_PHY: - case QCA8035_PHY: - case MP_GEPHY: -/*qca808x_start*/ - case QCA8081_PHY_V1_1: - cfg->chip_type = CHIP_SCOMPHY; - /*MP GEPHY is always the first port*/ - if(cfg->phy_id == 0) - { - cfg->phy_id = phy_id; - } - rv = SW_OK; - break; - default: - break; - } - } - port_bmp >>= 1; - port_id++; - } - - return rv; -} - -static int chip_ver_get(a_uint32_t dev_id, ssdk_init_cfg* cfg) -{ - int rv = SW_OK; - a_uint8_t chip_ver = 0; - a_uint8_t chip_revision = 0; -/*qca808x_end*/ - hsl_reg_mode reg_mode; - - reg_mode= ssdk_switch_reg_access_mode_get(dev_id); - if(reg_mode == HSL_REG_MDIO) - { - chip_ver = (qca_ar8216_mii_read(dev_id, 0)&0xff00)>>8; - } - else { - a_uint32_t reg_val = 0; - qca_switch_reg_read(dev_id,0,(a_uint8_t *)®_val, 4); - chip_ver = (reg_val&0xff00)>>8; - chip_revision = reg_val&0xff; - } -/*qca808x_start*/ - if(chip_ver == QCA_VER_AR8227) - cfg->chip_type = CHIP_SHIVA; - else if(chip_ver == QCA_VER_AR8337) - cfg->chip_type = CHIP_ISISC; - else if(chip_ver == QCA_VER_AR8327) - cfg->chip_type = CHIP_ISIS; - else if(chip_ver == QCA_VER_DESS) - cfg->chip_type = CHIP_DESS; - else if(chip_ver == QCA_VER_HPPE) { - cfg->chip_type = CHIP_HPPE; - cfg->chip_revision = chip_revision; - } - else { - /* try single phy without switch connected */ - rv = chip_is_scomphy(dev_id, cfg); - } - - return rv; -} -/*qca808x_end*/ - -#ifdef DESS -static int ssdk_flow_default_act_init(a_uint32_t dev_id) -{ - a_uint32_t vrf_id = 0; - fal_flow_type_t type = 0; - for(vrf_id = FAL_MIN_VRF_ID; vrf_id <= FAL_MAX_VRF_ID; vrf_id++) - { - for(type = FAL_FLOW_LAN_TO_LAN; type <= FAL_FLOW_WAN_TO_WAN; type++) - { -#ifdef IN_IP -#ifndef IN_IP_MINI - fal_default_flow_cmd_set(dev_id, vrf_id, type, FAL_DEFAULT_FLOW_ADMIT_ALL); -#endif -#endif - } - } - - return 0; -} -static int ssdk_dess_mac_mode_init(a_uint32_t dev_id, a_uint32_t mac_mode) -{ - a_uint32_t reg_value; - u8 __iomem *gcc_addr = NULL; - - switch(mac_mode) { - case PORT_WRAPPER_PSGMII: - case PORT_WRAPPER_PSGMII_FIBER: - reg_value = 0x2200; - qca_psgmii_reg_write(dev_id, DESS_PSGMII_MODE_CONTROL, - (a_uint8_t *)®_value, 4); - reg_value = 0x8380; - qca_psgmii_reg_write(dev_id, DESS_PSGMIIPHY_TX_CONTROL, - (a_uint8_t *)®_value, 4); - break; - case PORT_WRAPPER_SGMII0_RGMII5: - case PORT_WRAPPER_SGMII1_RGMII5: - case PORT_WRAPPER_SGMII0_RGMII4: - case PORT_WRAPPER_SGMII1_RGMII4: - case PORT_WRAPPER_SGMII4_RGMII4: - - /*config sgmii */ - if ((mac_mode == PORT_WRAPPER_SGMII0_RGMII5) - ||(mac_mode == PORT_WRAPPER_SGMII0_RGMII4)) { - /*PSGMII channnel 0 as SGMII*/ - reg_value = 0x2001; - fal_psgmii_reg_set(dev_id, 0x1b4, - (a_uint8_t *)®_value, 4); - udelay(1000); - } - if ((mac_mode == PORT_WRAPPER_SGMII1_RGMII5) - ||(mac_mode == PORT_WRAPPER_SGMII1_RGMII4)) { - /*PSGMII channnel 1 as SGMII*/ - reg_value = 0x2003; - fal_psgmii_reg_set(dev_id, 0x1b4, - (a_uint8_t *)®_value, 4); - udelay(1000); - } - if ((mac_mode == PORT_WRAPPER_SGMII4_RGMII4)) { - /*PSGMII channnel 4 as SGMII*/ - reg_value = 0x2005; - fal_psgmii_reg_set(dev_id, 0x1b4, - (a_uint8_t *)®_value, 4); - udelay(1000); - } - - /*clock gen 1*/ - reg_value = 0xea6; - fal_psgmii_reg_set(dev_id, 0x13c, - (a_uint8_t *)®_value, 4); - mdelay(10); - /*softreset psgmii, fixme*/ - gcc_addr = ioremap_nocache(0x1812000, 0x200); - if (!gcc_addr) { - SSDK_ERROR("gcc map fail!\n"); - return 0; - } else { - SSDK_INFO("gcc map success!\n"); - writel(0x20, gcc_addr+0xc); - mdelay(10); - writel(0x0, gcc_addr+0xc); - mdelay(10); - iounmap(gcc_addr); - } - /*relock pll*/ - reg_value = 0x2803; - fal_psgmii_reg_set(dev_id, DESS_PSGMII_PLL_VCO_RELATED_CONTROL_1, - (a_uint8_t *)®_value, 4); - udelay(1000); - reg_value = 0x4ADA; - fal_psgmii_reg_set(dev_id, DESS_PSGMII_VCO_CALIBRATION_CONTROL_1, - (a_uint8_t *)®_value, 4); - udelay(1000); - reg_value = 0xADA; - fal_psgmii_reg_set(dev_id, DESS_PSGMII_VCO_CALIBRATION_CONTROL_1, - (a_uint8_t *)®_value, 4); - udelay(1000); - - /* Reconfig channel 0 as SGMII and re autoneg*/ - if ((mac_mode == PORT_WRAPPER_SGMII0_RGMII5) - ||(mac_mode == PORT_WRAPPER_SGMII0_RGMII4)) { - /*PSGMII channnel 0 as SGMII*/ - reg_value = 0x2001; - fal_psgmii_reg_set(dev_id, 0x1b4, - (a_uint8_t *)®_value, 4); - udelay(1000); - /* restart channel 0 autoneg*/ - reg_value = 0xc4; - fal_psgmii_reg_set(dev_id, 0x1c8, - (a_uint8_t *)®_value, 4); - mdelay(10); - reg_value = 0x44; - fal_psgmii_reg_set(dev_id, 0x1c8, - (a_uint8_t *)®_value, 4); - mdelay(10); - } - /* Reconfig channel 1 as SGMII and re autoneg*/ - if ((mac_mode == PORT_WRAPPER_SGMII1_RGMII5) - ||(mac_mode == PORT_WRAPPER_SGMII1_RGMII4)) { - - /*PSGMII channnel 1 as SGMII*/ - reg_value = 0x2003; - fal_psgmii_reg_set(dev_id, 0x1b4, - (a_uint8_t *)®_value, 4); - udelay(1000); - /* restart channel 1 autoneg*/ - reg_value = 0xc4; - fal_psgmii_reg_set(dev_id, 0x1e0, - (a_uint8_t *)®_value, 4); - mdelay(10); - reg_value = 0x44; - fal_psgmii_reg_set(dev_id, 0x1e0, - (a_uint8_t *)®_value, 4); - mdelay(10); - - } - /* Reconfig channel 4 as SGMII and re autoneg*/ - if ((mac_mode == PORT_WRAPPER_SGMII4_RGMII4)) { - /*PSGMII channnel 4 as SGMII*/ - reg_value = 0x2005; - fal_psgmii_reg_set(dev_id, 0x1b4, - (a_uint8_t *)®_value, 4); - udelay(1000); - /* restart channel 4 autoneg*/ - reg_value = 0xc4; - fal_psgmii_reg_set(dev_id, 0x228, - (a_uint8_t *)®_value, 4); - mdelay(10); - reg_value = 0x44; - fal_psgmii_reg_set(dev_id, 0x228, - (a_uint8_t *)®_value, 4); - mdelay(10); - } - - /* config RGMII*/ - reg_value = 0x400; - fal_reg_set(dev_id, 0x4, (a_uint8_t *)®_value, 4); - /* config mac5 RGMII*/ - if ((mac_mode == PORT_WRAPPER_SGMII0_RGMII5) - ||(mac_mode == PORT_WRAPPER_SGMII1_RGMII5)) { - qca_ar8327_phy_dbg_write(0, 4, 0x5, 0x2d47); - qca_ar8327_phy_dbg_write(0, 4, 0xb, 0xbc40); - qca_ar8327_phy_dbg_write(0, 4, 0x0, 0x82ee); - reg_value = 0x72; - qca_switch_reg_write(dev_id, 0x90, (a_uint8_t *)®_value, 4); - } - /* config mac4 RGMII*/ - if ((mac_mode == PORT_WRAPPER_SGMII0_RGMII4) - ||(mac_mode == PORT_WRAPPER_SGMII1_RGMII4) - ||(mac_mode == PORT_WRAPPER_SGMII4_RGMII4)) { - qca_ar8327_phy_dbg_write(dev_id, 4, 0x5, 0x2d47); - qca_ar8327_phy_dbg_write(dev_id, 4, 0xb, 0xbc40); - qca_ar8327_phy_dbg_write(dev_id, 4, 0x0, 0x82ee); - reg_value = 0x72; - qca_switch_reg_write(dev_id, 0x8c, (a_uint8_t *)®_value, 4); - } - break; - case PORT_WRAPPER_PSGMII_RMII0_RMII1: - case PORT_WRAPPER_PSGMII_RMII0: - case PORT_WRAPPER_PSGMII_RMII1: - reg_value = 0x2200; - qca_psgmii_reg_write(dev_id, DESS_PSGMII_MODE_CONTROL, - (a_uint8_t *)®_value, 4); - reg_value = 0x8380; - qca_psgmii_reg_write(dev_id, DESS_PSGMIIPHY_TX_CONTROL, - (a_uint8_t *)®_value, 4); - /*switch RMII clock source to gcc_ess_clk,ESS_RGMII_CTRL:0x0C000004,dakota rmii1/rmii0 master mode*/ - if(mac_mode== PORT_WRAPPER_PSGMII_RMII0_RMII1) - reg_value = 0x3000000; - if(mac_mode== PORT_WRAPPER_PSGMII_RMII0) - reg_value = 0x1000000; - if(mac_mode== PORT_WRAPPER_PSGMII_RMII1) - reg_value = 0x2000000; - qca_switch_reg_write(dev_id, 0x4, (a_uint8_t *)®_value, 4); - /*enable RMII MAC5 100M/full*/ - if(mac_mode == PORT_WRAPPER_PSGMII_RMII0_RMII1 || mac_mode == PORT_WRAPPER_PSGMII_RMII0) - { - reg_value = 0x7d; - qca_switch_reg_write(dev_id, 0x90, (a_uint8_t *)®_value, 4); - } - - /*enable RMII MAC4 100M/full*/ - if(mac_mode == PORT_WRAPPER_PSGMII_RMII0_RMII1 || mac_mode == PORT_WRAPPER_PSGMII_RMII1) - { - reg_value = 0x7d; - qca_switch_reg_write(dev_id, 0x8C, (a_uint8_t *)®_value, 4); - } - /*set QM CONTROL REGISTER FLOW_DROP_CNT as max*/ - reg_value = 0x7f007f; - qca_switch_reg_write(dev_id, 0x808, (a_uint8_t *)®_value, 4); - - /*relock PSGMII PLL*/ - reg_value = 0x2803; - fal_psgmii_reg_set(dev_id, DESS_PSGMII_PLL_VCO_RELATED_CONTROL_1, - (a_uint8_t *)®_value, 4); - udelay(1000); - reg_value = 0x4ADA; - fal_psgmii_reg_set(dev_id, DESS_PSGMII_VCO_CALIBRATION_CONTROL_1, - (a_uint8_t *)®_value, 4); - udelay(1000); - reg_value = 0xADA; - fal_psgmii_reg_set(dev_id, DESS_PSGMII_VCO_CALIBRATION_CONTROL_1, - (a_uint8_t *)®_value, 4); - udelay(1000); - break; - } - - return 0; -} - -#ifdef IN_TRUNK -#define MULTIPLE_WAN_PORT_CNT 2 -#define TRUNK_ID_OF_MULTIPLE_WAN_PORTS 0 - -static a_bool_t -ssdk_dess_multiple_wan_port_check(a_uint32_t dev_id, - a_uint32_t wan_bitmap) -{ - a_uint32_t port_id = SSDK_PHYSICAL_PORT0, wan_ports_cnt = 0; - - for(port_id = SSDK_PHYSICAL_PORT0; port_id < SSDK_MAX_PORT_NUM; - port_id++) - { - if(BIT(port_id) & wan_bitmap) - { - wan_ports_cnt++; - } - } - if(wan_ports_cnt >= MULTIPLE_WAN_PORT_CNT) - { - return A_TRUE; - } - else - { - return A_FALSE; - } -} - -sw_error_t -ssdk_dess_trunk_init(a_uint32_t dev_id, a_uint32_t wan_bitmap) -{ - sw_error_t rv = SW_OK; - - if(ssdk_dess_multiple_wan_port_check(dev_id, wan_bitmap)) - { - rv = fal_trunk_group_set(dev_id, TRUNK_ID_OF_MULTIPLE_WAN_PORTS, - A_TRUE, wan_bitmap); - SW_RTN_ON_ERROR(rv); - } - - return rv; -} -#endif - -static sw_error_t -qca_dess_hw_init(ssdk_init_cfg *cfg, a_uint32_t dev_id) -{ - a_uint32_t reg_value = 0; - hsl_api_t *p_api; - a_uint32_t psgmii_result = 0; - a_uint32_t mac_mode; - - mac_mode = ssdk_dt_global_get_mac_mode(dev_id, 0); - /*Do Malibu self test to fix packet drop issue firstly*/ - if ((mac_mode == PORT_WRAPPER_PSGMII) || - (mac_mode == PORT_WRAPPER_PSGMII_FIBER)) { - ssdk_psgmii_self_test(dev_id, A_FALSE, 100, &psgmii_result); - clear_self_test_config(dev_id); - } else { -#ifndef BOARD_AR71XX - ssdk_ess_reset(); -#endif - } - - qca_switch_init(dev_id); -#ifdef IN_PORTVLAN - ssdk_portvlan_init(dev_id); -#endif - -#ifdef IN_PORTVLAN - fal_port_rxhdr_mode_set(dev_id, 0, FAL_ALL_TYPE_FRAME_EN); -#endif -#ifdef IN_IP -#ifndef IN_IP_MINI - fal_ip_route_status_set(dev_id, A_TRUE); -#endif -#endif - - ssdk_flow_default_act_init(dev_id); - - /*set normal hash and disable nat/napt*/ - qca_switch_reg_read(dev_id, 0x0e38, (a_uint8_t *)®_value, 4); - reg_value = (reg_value|0x1000000|0x8); - reg_value &= ~2; - qca_switch_reg_write(dev_id, 0x0e38, (a_uint8_t *)®_value, 4); -#ifdef IN_IP -#ifndef IN_IP_MINI - fal_ip_vrf_base_addr_set(dev_id, 0, 0); -#endif -#endif - - p_api = hsl_api_ptr_get (dev_id); - if (p_api && p_api->port_flowctrl_thresh_set) - p_api->port_flowctrl_thresh_set(dev_id, 0, SSDK_PORT0_FC_THRESH_ON_DFLT, - SSDK_PORT0_FC_THRESH_OFF_DFLT); - - if (p_api && p_api->ip_glb_lock_time_set) - p_api->ip_glb_lock_time_set(dev_id, FAL_GLB_LOCK_TIME_100US); - - - /*config psgmii,sgmii or rgmii mode for Dakota*/ - ssdk_dess_mac_mode_init(dev_id, cfg->mac_mode); - - /*add BGA Board led contorl*/ - ssdk_dess_led_init(cfg); -#ifdef IN_TRUNK - SW_RTN_ON_ERROR(ssdk_dess_trunk_init(dev_id, cfg->port_cfg.wan_bmp)); -#endif - - return SW_OK; -} -#endif -/*qca808x_start*/ -static void ssdk_cfg_default_init(ssdk_init_cfg *cfg) -{ - memset(cfg, 0, sizeof(ssdk_init_cfg)); - cfg->cpu_mode = HSL_CPU_1; - cfg->nl_prot = 30; - cfg->reg_func.mdio_set = qca_ar8327_phy_write; - cfg->reg_func.mdio_get = qca_ar8327_phy_read; -#if defined(IN_PHY_I2C_MODE) - cfg->reg_func.i2c_set = qca_phy_i2c_write; - cfg->reg_func.i2c_get = qca_phy_i2c_read; -#endif -/*qca808x_end*/ - - cfg->reg_func.header_reg_set = qca_switch_reg_write; - cfg->reg_func.header_reg_get = qca_switch_reg_read; - cfg->reg_func.mii_reg_set = qca_ar8216_mii_write; - cfg->reg_func.mii_reg_get = qca_ar8216_mii_read; -/*qca808x_start*/ -} -/*qca808x_end*/ - -#ifdef IN_RFS -#if defined(CONFIG_RFS_ACCEL) -int ssdk_netdev_rfs_cb( - struct net_device *dev, - __be32 src, __be32 dst, - __be16 sport, __be16 dport, - u8 proto, u16 rxq_index, u32 action) -{ - return ssdk_rfs_ipct_rule_set(src, dst, sport, dport, - proto, rxq_index, action); -} -#endif - -#ifdef DESS -a_bool_t ssdk_intf_search( - a_uint8_t *mac, a_uint16_t vid, - a_uint8_t *ret_index, a_uint8_t *free_index) -{ - a_uint8_t i = 0; - - for (i = 0; i < SSDK_RFS_INTF_MAX; i++) { - if (rfs_intf_tbl[i].vid == 0) - *free_index = i; - if (!memcmp(rfs_intf_tbl[i].macaddr.uc, mac, 6) && - rfs_intf_tbl[i].vid == vid) { - /* find it */ - *ret_index = i; - return A_TRUE; - } - } - - /* Not find the same entry */ - return A_FALSE; -} - -static a_bool_t ssdk_is_raw_dev(struct net_device *dev) -{ - struct device *pdev; - - pdev = dev->dev.parent; - if (!pdev) - return A_FALSE; - - if (!strstr(dev_name(pdev), "edma")) - return A_FALSE; - else - return A_TRUE; -} - -static a_uint16_t ssdk_raw_dev_vid_get(struct net_device *dev) -{ -#ifdef CONFIG_RFS_ACCEL - const struct net_device_ops *ops; - - ops = dev->netdev_ops; - if (!ops || - !ops->ndo_get_default_vlan_tag) { - return 0; - } - return ops->ndo_get_default_vlan_tag(dev); -#else - return 0; -#endif -} - -static a_uint16_t ssdk_netdev_vid_get(struct net_device *dev) -{ - struct net_device *pdev; - a_uint16_t vid = 0; - - if (is_vlan_dev(dev)) { - pdev = vlan_dev_real_dev(dev); - if (!ssdk_is_raw_dev(pdev)) { - SSDK_DEBUG("The device %s is not expected!\n", dev->name); - return 0; - } - vid = vlan_dev_vlan_id(dev); - } else if (ssdk_is_raw_dev(dev)) { - vid = ssdk_raw_dev_vid_get(dev); - } else if (dev->priv_flags & IFF_EBRIDGE) { - /* Do nothing for bridge */ - } else { - SSDK_DEBUG("The device %s is not expected!\n", dev->name); - } - - return vid; -} - -static void ssdk_rfs_intf_add(struct net_device *dev) -{ - a_uint8_t *devmac = NULL; - a_uint16_t vid = 0; - fal_intf_mac_entry_t intf_entry; - sw_error_t rv = 0; - a_uint8_t index0, index1; - - /* get vid */ - vid = ssdk_netdev_vid_get(dev); - if (vid == 0) - return; - - /*get mac*/ - devmac = (a_uint8_t*)(dev->dev_addr); - - if (ssdk_intf_search(devmac, vid, &index0, &index1)) { - /* already exist, ignore */ - return; - } - rfs_intf_tbl[index1].vid = vid; - rfs_intf_tbl[index1].if_idx = dev->ifindex; - memcpy(&rfs_intf_tbl[index1].macaddr, devmac, ETH_ALEN); - - memset(&intf_entry, 0, sizeof(intf_entry)); - intf_entry.ip4_route = 1; - intf_entry.ip6_route = 1; - intf_entry.vid_low = vid; - intf_entry.vid_high = vid; - memcpy(&intf_entry.mac_addr, devmac, 6); - rv = fal_ip_intf_entry_add(0, &intf_entry); - if (rv) { - SSDK_ERROR("Faled to add intf entry, rv=%d\n", rv); - memset(&rfs_intf_tbl[index1], 0, sizeof(ssdk_rfs_intf_t)); - return; - } - - rfs_intf_tbl[index1].hw_idx = intf_entry.entry_id; - -} - -static void ssdk_rfs_intf_del(struct net_device *dev) -{ - a_uint8_t i = 0; - fal_intf_mac_entry_t intf_entry; - sw_error_t rv = 0; - - for (i = 0; i < SSDK_RFS_INTF_MAX; i++) { - if ((rfs_intf_tbl[i].if_idx == dev->ifindex) && - (rfs_intf_tbl[i].vid != 0)) { - intf_entry.entry_id = rfs_intf_tbl[i].hw_idx; - rv = fal_ip_intf_entry_del(0, 1, &intf_entry); - if (rv) { - SSDK_ERROR("Faled to del entry, rv=%d\n", rv); - } else { - memset(&rfs_intf_tbl[i], 0, sizeof(ssdk_rfs_intf_t)); - } - return; - } - } -} - -static int ssdk_inet_event(struct notifier_block *this, unsigned long event, void *ptr) -{ - struct net_device *dev = ((struct in_ifaddr *)ptr)->ifa_dev->dev; - - /* Ignore the wireless dev */ -#ifdef CONFIG_WIRELESS_EXT - if (dev->wireless_handlers) - return NOTIFY_DONE; - else -#endif - if (dev->ieee80211_ptr) - return NOTIFY_DONE; - - switch (event) { - case NETDEV_DOWN: - ssdk_rfs_intf_del(dev); - break; - case NETDEV_UP: - ssdk_rfs_intf_add(dev); - break; - } - return NOTIFY_DONE; -} -#endif -#endif - -//#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3,14,0)) -static int ssdk_dev_event(struct notifier_block *this, unsigned long event, void *ptr) -{ - int rv = 0; - ssdk_init_cfg cfg; -#ifdef MP - a_uint32_t port_id = 0, dev_id = 0; - struct qca_phy_priv *priv = ssdk_phy_priv_data_get(dev_id); - adpt_api_t *p_api = adpt_api_ptr_get(dev_id); -#endif - -#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3,14,0)) - struct net_device *dev = netdev_notifier_info_to_dev(ptr); -#else - struct net_device *dev = (struct net_device *)ptr; -#endif - - ssdk_cfg_default_init(&cfg); - rv = chip_ver_get(0, &cfg); - if (rv) { - SSDK_ERROR("chip verfion get failed\n"); - return NOTIFY_DONE; - } - switch (event) { -#ifdef IN_RFS -#if defined(CONFIG_RFS_ACCEL) - case NETDEV_UP: - if (strstr(dev->name, "eth")) { - if (dev->netdev_ops && dev->netdev_ops->ndo_register_rfs_filter) { - dev->netdev_ops->ndo_register_rfs_filter(dev, - ssdk_netdev_rfs_cb); - } - } - break; -#endif -#endif - case NETDEV_CHANGEMTU: - if(dev->type == ARPHRD_ETHER) { - if (cfg.chip_type == CHIP_DESS || - cfg.chip_type == CHIP_ISIS || - cfg.chip_type == CHIP_ISISC) { - struct net_device *eth_dev = NULL; - unsigned int mtu= 0; - - if(!strcmp(dev->name, "eth0")) { - eth_dev = dev_get_by_name(&init_net, "eth1"); - } else if (!strcmp(dev->name, "eth1")) { - eth_dev = dev_get_by_name(&init_net, "eth0"); - } else { - return NOTIFY_DONE; - } - if (!eth_dev) { - return NOTIFY_DONE; - } - mtu = dev->mtu > eth_dev->mtu ? dev->mtu : eth_dev->mtu; -#ifdef IN_MISC - fal_frame_max_size_set(0, mtu + 18); -#endif - dev_put(eth_dev); - } - } - break; -#ifdef MP - case NETDEV_CHANGE: - if ((cfg.chip_type == CHIP_SCOMPHY) && - (cfg.phy_id == MP_GEPHY)) { - if ((p_api == NULL) || (p_api->adpt_port_netdev_notify_set == NULL) - || (priv == NULL)) { - SSDK_ERROR("Failed to get pointer\n"); - return NOTIFY_DONE; - } - if (dev->phydev != NULL) { - int addr; -#if (LINUX_VERSION_CODE >= KERNEL_VERSION(4,9,0)) - addr = dev->phydev->mdio.addr; -#else - addr = dev->phydev->addr; -#endif - port_id = qca_ssdk_phy_addr_to_port(priv->device_id, - addr); - rv = p_api->adpt_port_netdev_notify_set(priv, port_id); - if (rv) { - SSDK_ERROR("netdev change notify failed\n"); - return NOTIFY_DONE; - } - } - } - break; -#endif - } - - return NOTIFY_DONE; -} - -#ifdef DESS -static void qca_dess_rfs_remove(void) -{ - /* ssdk_dt_global->switch_reg_access_mode == HSL_REG_LOCAL_BUS */ - if(qca_dess_rfs_registered){ -#if defined (CONFIG_NF_FLOW_COOKIE) -#ifdef IN_NAT -#ifdef IN_SFE - sfe_unregister_flow_cookie_cb(ssdk_flow_cookie_set); -#endif -#endif -#endif -#ifdef IN_RFS - rfs_ess_device_unregister(&rfs_dev); - unregister_inetaddr_notifier(&ssdk_inet_notifier); -#if defined(CONFIG_RFS_ACCEL) -#endif -#endif - qca_dess_rfs_registered = false; - } - -} - -static void qca_dess_rfs_init(void) -{ - if (!qca_dess_rfs_registered) { -#if defined (CONFIG_NF_FLOW_COOKIE) -#ifdef IN_NAT -#ifdef IN_SFE - sfe_register_flow_cookie_cb(ssdk_flow_cookie_set); -#endif -#endif -#endif - -#ifdef IN_RFS - memset(&rfs_dev, 0, sizeof(rfs_dev)); - rfs_dev.name = NULL; -#ifdef IN_FDB - rfs_dev.mac_rule_cb = ssdk_rfs_mac_rule_set; -#endif -#ifdef IN_IP - rfs_dev.ip4_rule_cb = ssdk_rfs_ip4_rule_set; - rfs_dev.ip6_rule_cb = ssdk_rfs_ip6_rule_set; -#endif - rfs_ess_device_register(&rfs_dev); -#if defined(CONFIG_RFS_ACCEL) -#endif - ssdk_inet_notifier.notifier_call = ssdk_inet_event; - ssdk_inet_notifier.priority = 1; - register_inetaddr_notifier(&ssdk_inet_notifier); -#endif - qca_dess_rfs_registered = true; - } -} -#endif -/*qca808x_start*/ -static void ssdk_free_priv(void) -{ - a_uint32_t dev_id, dev_num = 1; - - if(!qca_phy_priv_global) { - return; - } -/*qca808x_end*/ - dev_num = ssdk_switch_device_num_get(); -/*qca808x_start*/ - for (dev_id = 0; dev_id < dev_num; dev_id++) { - if (qca_phy_priv_global[dev_id]) { - kfree(qca_phy_priv_global[dev_id]); - } - - qca_phy_priv_global[dev_id] = NULL; - } - - kfree(qca_phy_priv_global); - - qca_phy_priv_global = NULL; -/*qca808x_end*/ - ssdk_switch_device_num_exit(); -/*qca808x_start*/ -} - -static int ssdk_alloc_priv(a_uint32_t dev_num) -{ - int rev = SW_OK; - a_uint32_t dev_id = 0; - - qca_phy_priv_global = kzalloc(dev_num * sizeof(struct qca_phy_priv *), GFP_KERNEL); - if (qca_phy_priv_global == NULL) { - return -ENOMEM; - } - - for (dev_id = 0; dev_id < dev_num; dev_id++) { - qca_phy_priv_global[dev_id] = kzalloc(sizeof(struct qca_phy_priv), GFP_KERNEL); - if (qca_phy_priv_global[dev_id] == NULL) { - return -ENOMEM; - } -/*qca808x_end*/ - qca_phy_priv_global[dev_id]->qca_ssdk_sw_dev_registered = A_FALSE; - qca_phy_priv_global[dev_id]->ess_switch_flag = A_FALSE; -/*qca808x_start*/ - qca_ssdk_port_bmp_init(dev_id); - qca_ssdk_phy_info_init(dev_id); - } - - return rev; -} - -#ifndef SSDK_STR -#define SSDK_STR "ssdk" -#endif -#if defined (ISISC) || defined (ISIS) -static void qca_ar8327_gpio_reset(struct qca_phy_priv *priv) -{ - struct device_node *np = NULL; - const __be32 *reset_gpio; - a_int32_t len; - int gpio_num = 0, ret = 0; - - if (priv->ess_switch_flag == A_TRUE) - np = priv->of_node; - else -#if (LINUX_VERSION_CODE >= KERNEL_VERSION(4,9,0)) - np = priv->phy->mdio.dev.of_node; -#else - np = priv->phy->dev.of_node; -#endif - if(!np) - return; - gpio_num = of_get_named_gpio(np, "reset_gpio", 0); - if(gpio_num < 0) - { - reset_gpio = of_get_property(np, "reset_gpio", &len); - if (!reset_gpio ) - { - SSDK_INFO("reset_gpio node does not exist\n"); - return; - } - gpio_num = be32_to_cpup(reset_gpio); - if(gpio_num <= 0) - { - SSDK_INFO("reset gpio doesn't exist\n "); - return; - } - } - ret = gpio_request(gpio_num, "reset_gpio"); - if(ret) - { - SSDK_ERROR("gpio%d request failed, ret:%d\n", gpio_num, ret); - return; - } - gpio_direction_output(gpio_num, SSDK_GPIO_RESET); - msleep(200); - gpio_set_value(gpio_num, SSDK_GPIO_RELEASE); - SSDK_INFO("GPIO%d reset switch done\n", gpio_num); - - gpio_free(gpio_num); - - return; -} -#endif -static int __init regi_init(void) -{ - a_uint32_t num = 0, dev_id = 0, dev_num = 1; - ssdk_init_cfg cfg; -/*qca808x_end*/ - garuda_init_spec_cfg chip_spec_cfg; -/*qca808x_start*/ - int rv = 0; -/*qca808x_end*/ - /*init switch device num firstly*/ - ssdk_switch_device_num_init(); - - dev_num = ssdk_switch_device_num_get(); -/*qca808x_start*/ - rv = ssdk_alloc_priv(dev_num); - if (rv) - goto out; - - for (num = 0; num < dev_num; num++) { - ssdk_cfg_default_init(&cfg); -/*qca808x_end*/ -#ifndef BOARD_AR71XX -#if defined(CONFIG_OF) && (LINUX_VERSION_CODE >= KERNEL_VERSION(3,14,0)) - if(SW_DISABLE == ssdk_dt_parse(&cfg, num, &dev_id)) { - SSDK_INFO("ess-switch node is unavalilable\n"); - continue; - } -#endif -#endif - - /* device id is the array index */ - qca_phy_priv_global[dev_id]->device_id = ssdk_device_id_get(dev_id); - qca_phy_priv_global[dev_id]->ess_switch_flag = ssdk_ess_switch_flag_get(dev_id); - qca_phy_priv_global[dev_id]->of_node = ssdk_dts_node_get(dev_id); -/*qca808x_start*/ - rv = ssdk_plat_init(&cfg, dev_id); - SW_CNTU_ON_ERROR_AND_COND1_OR_GOTO_OUT(rv, -ENODEV); -/*qca808x_end*/ - ssdk_driver_register(dev_id); -/*qca808x_start*/ - rv = chip_ver_get(dev_id, &cfg); - SW_CNTU_ON_ERROR_AND_COND1_OR_GOTO_OUT(rv, -ENODEV); -/*qca808x_end*/ -#ifdef IN_AQUANTIA_PHY - ssdk_miireg_ioctrl_register(); -#endif - memset(&chip_spec_cfg, 0, sizeof(garuda_init_spec_cfg)); - cfg.chip_spec_cfg = &chip_spec_cfg; -/*qca808x_start*/ - rv = ssdk_init(dev_id, &cfg); - SW_CNTU_ON_ERROR_AND_COND1_OR_GOTO_OUT(rv, -ENODEV); -/*qca808x_end*/ - - - switch (cfg.chip_type) - { - case CHIP_ISIS: - case CHIP_ISISC: -#if defined (ISISC) || defined (ISIS) - if (qca_phy_priv_global[dev_id]->ess_switch_flag == A_TRUE) { - SSDK_INFO("Initializing ISISC!!\n"); - qca_ar8327_gpio_reset(qca_phy_priv_global[dev_id]); - rv = ssdk_switch_register(dev_id, cfg.chip_type); - SW_CNTU_ON_ERROR_AND_COND1_OR_GOTO_OUT(rv, -ENODEV); - rv = qca_ar8327_hw_init(qca_phy_priv_global[dev_id]); - SSDK_INFO("Initializing ISISC Done!!\n"); - } -#endif - break; - case CHIP_HPPE: -#if defined(HPPE) - SSDK_INFO("Initializing HPPE!!\n"); - qca_hppe_hw_init(&cfg, dev_id); - rv = ssdk_switch_register(dev_id, cfg.chip_type); - SW_CNTU_ON_ERROR_AND_COND1_OR_GOTO_OUT(rv, -ENODEV); - SSDK_INFO("Initializing HPPE Done!!\n"); -#endif - break; - - case CHIP_DESS: -#if defined(DESS) - SSDK_INFO("Initializing DESS!!\n"); - - qca_dess_hw_init(&cfg, dev_id); - qca_dess_rfs_init(); - - /* Setup Cpu port for Dakota platform. */ - switch_cpuport_setup(dev_id); - rv = ssdk_switch_register(dev_id, cfg.chip_type); - SW_CNTU_ON_ERROR_AND_COND1_OR_GOTO_OUT(rv, -ENODEV); - SSDK_INFO("Initializing DESS Done!!\n"); -#endif - break; - - case CHIP_SHIVA: - case CHIP_ATHENA: - case CHIP_GARUDA: - case CHIP_HORUS: - case CHIP_UNSPECIFIED: - break; - case CHIP_SCOMPHY: -#if defined(SCOMPHY) - SSDK_INFO("Initializing SCOMPHY!\n"); - rv = qca_scomphy_hw_init(&cfg, dev_id); - SW_CNTU_ON_ERROR_AND_COND1_OR_GOTO_OUT(rv, -ENODEV); -#if defined(MP) - if(cfg.phy_id == MP_GEPHY) - { - rv = ssdk_switch_register(dev_id, cfg.chip_type); - SW_CNTU_ON_ERROR_AND_COND1_OR_GOTO_OUT(rv, -ENODEV); - } -#endif - SSDK_INFO("Initializing SCOMPHY Done!!\n"); -#endif - break; - } - - fal_module_func_init(dev_id, &cfg); -/*qca808x_start*/ - - } -/*qca808x_end*/ - - ssdk_sysfs_init(); - - if (rv == 0){ - /* register the notifier later should be ok */ - ssdk_dev_notifier.notifier_call = ssdk_dev_event; - ssdk_dev_notifier.priority = 1; - register_netdevice_notifier(&ssdk_dev_notifier); - } -/*qca808x_start*/ - -out: - if (rv == 0) - SSDK_INFO("qca-%s module init succeeded!\n", SSDK_STR); - else { - if (rv == -ENODEV) { - rv = 0; - SSDK_INFO("qca-%s module init, no device found!\n", SSDK_STR); - } else { - SSDK_INFO("qca-%s module init failed! (code: %d)\n", SSDK_STR, rv); - ssdk_free_priv(); - } - } - - return rv; -} - -static void __exit -regi_exit(void) -{ -/*qca808x_end*/ - a_uint32_t dev_id, dev_num = 1; -/*qca808x_start*/ - sw_error_t rv; -/*qca808x_end*/ - dev_num = ssdk_switch_device_num_get(); - for (dev_id = 0; dev_id < dev_num; dev_id++) { - ssdk_driver_unregister(dev_id); -#if defined(DESS) || defined(HPPE) || defined(ISISC) || defined(ISIS) || defined(MP) - if (qca_phy_priv_global[dev_id]->qca_ssdk_sw_dev_registered == A_TRUE) - ssdk_switch_unregister(dev_id); -#endif - } -/*qca808x_start*/ - rv = ssdk_cleanup(); - - if (rv == 0) - SSDK_INFO("qca-%s module exit done!\n", SSDK_STR); - else - SSDK_ERROR("qca-%s module exit failed! (code: %d)\n", SSDK_STR, rv); -/*qca808x_end*/ - -#ifdef DESS - qca_dess_rfs_remove(); -#endif - - ssdk_sysfs_exit(); -#ifdef IN_AQUANTIA_PHY - ssdk_miireg_ioctrl_unregister(); -#endif - for (dev_id = 0; dev_id < dev_num; dev_id++) { - ssdk_plat_exit(dev_id); - } - - unregister_netdevice_notifier(&ssdk_dev_notifier); -/*qca808x_start*/ - ssdk_free_priv(); -} - -module_init(regi_init); -module_exit(regi_exit); - -MODULE_DESCRIPTION("QCA SSDK Driver"); -MODULE_LICENSE("Dual BSD/GPL"); -/*qca808x_end*/ diff --git a/feeds/ipq807x/qca-ssdk/src/src/init/ssdk_interrupt.c b/feeds/ipq807x/qca-ssdk/src/src/init/ssdk_interrupt.c deleted file mode 100755 index 0e0bac81c..000000000 --- a/feeds/ipq807x/qca-ssdk/src/src/init/ssdk_interrupt.c +++ /dev/null @@ -1,209 +0,0 @@ -/* - * Copyright (c) 2017, The Linux Foundation. All rights reserved. - * Permission to use, copy, modify, and/or distribute this software for - * any purpose with or without fee is hereby granted, provided that the - * above copyright notice and this permission notice appear in all copies. - * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES - * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR - * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES - * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN - * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT - * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. - */ -#include "fal_init.h" -#include "fal_reg_access.h" -#include "sw.h" -#include "ssdk_init.h" -#include "fal_init.h" -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#if defined(ISIS) -#include -#elif defined(ISISC) -#include -#else -#include -#endif -#if defined(CONFIG_OF) && (LINUX_VERSION_CODE >= KERNEL_VERSION(4,1,0)) -#include -#elif defined(CONFIG_OF) && (LINUX_VERSION_CODE >= KERNEL_VERSION(3,14,0)) -#include -#include -#include -#include -#else -#include -#endif -#include "ssdk_plat.h" -#include "ref_port_ctrl.h" - -#define LINK_CHANGE_INTR 0x8000 -/*phy interrupt enable and status register*/ -#define INTERRUPT_ENABLE_REGISTER 0X12 -#define INTERRUPT_STATUS_REGISTER 0X13 - -extern void qca_ar8327_sw_mac_polling_task(struct qca_phy_priv *priv); - -static int qca_phy_disable_intr(struct qca_phy_priv *priv) -{ - a_uint32_t phy_number = 0; - a_uint16_t value; - - for(phy_number = 0; phy_number < 5; phy_number++) - { - value = 0; - priv->phy_write(priv->device_id, phy_number, INTERRUPT_ENABLE_REGISTER, value); - priv->phy_read(priv->device_id, phy_number, INTERRUPT_STATUS_REGISTER, &value); - } - - return 0; -} - -static int qca_mac_disable_intr(struct qca_phy_priv *priv) -{ - a_uint32_t data; - - fal_reg_get(priv->device_id, GBL_INT_MASK1_OFFSET, (a_uint8_t *)&data, 4); - if (data ) - { - data = 0; - fal_reg_set(priv->device_id, GBL_INT_MASK1_OFFSET,(a_uint8_t *)&data, 4); - } - /*fal_reg_get(0, 0x20, (a_uint8_t *)&data, 4); - if (data ) - { - data = 0; - fal_reg_set(0, 0x20,(a_uint8_t *)&data, 4); - } - - fal_reg_get(0, 0x28, (a_uint8_t *)&data, 4); - fal_reg_set(0, 0x28,(a_uint8_t *)&data, 4); - */ - - fal_reg_get(priv->device_id, GBL_INT_STATUS1_OFFSET, (a_uint8_t *)&data, 4); - fal_reg_set(priv->device_id, GBL_INT_STATUS1_OFFSET,(a_uint8_t *)&data, 4); - - return 0; -} - -static int qca_phy_enable_intr(struct qca_phy_priv *priv) -{ - a_uint16_t value = 0; - a_uint32_t phy_number; - - for(phy_number = 0; phy_number < 5; phy_number++) - { - priv->phy_read(priv->device_id, phy_number, INTERRUPT_STATUS_REGISTER, &value); - /*enable link change intr*/ - if( !priv->link_polling_required) - value = 0xc00; - priv->phy_write(priv->device_id,phy_number, INTERRUPT_ENABLE_REGISTER, value); - } - - return 0; -} - -int qca_mac_enable_intr(struct qca_phy_priv *priv) -{ - a_uint32_t data = 0; - - /*enable link change intr*/ - if( !priv->link_polling_required) - data = 0x8000; - fal_reg_set(priv->device_id, GBL_INT_MASK1_OFFSET, (a_uint8_t *)&data, 4); - - return 0; -} -static int qca_phy_clean_intr(struct qca_phy_priv *priv) -{ - a_uint32_t phy_number; - a_uint16_t value; - - for(phy_number = 0; phy_number < 5; phy_number++) - priv->phy_read(priv->device_id, phy_number, INTERRUPT_STATUS_REGISTER, &value); - - return 0; -} - -static int qca_mac_clean_intr(struct qca_phy_priv *priv) -{ - a_uint32_t data; - - fal_reg_get(priv->device_id, GBL_INT_STATUS1_OFFSET, (a_uint8_t *) &data, 4); - fal_reg_set(priv->device_id, GBL_INT_STATUS1_OFFSET, (a_uint8_t *)&data, 4); - - return 0; -} - -static void -qca_link_change_task(struct qca_phy_priv *priv) -{ - SSDK_DEBUG("qca_link_change_task is running\n"); - mutex_lock(&priv->qm_lock); - qca_ar8327_sw_mac_polling_task(priv); - mutex_unlock(&priv->qm_lock); -} - -static void -qca_intr_workqueue_task(struct work_struct *work) -{ - a_uint32_t data; - struct qca_phy_priv *priv = container_of(work, struct qca_phy_priv, intr_workqueue); - - fal_reg_get(priv->device_id, GBL_INT_STATUS1_OFFSET, (a_uint8_t*)&data, 4); - qca_phy_clean_intr(priv); - qca_mac_clean_intr(priv); - SSDK_DEBUG("data:%x, priv->version:%x\n", data, priv->version); - switch(priv->version) - { - case QCA_VER_DESS: - qca_link_change_task(priv); - break; - default: - if((data &LINK_CHANGE_INTR)) - qca_link_change_task(priv); - break; - } - enable_irq(priv->link_interrupt_no); -} - - static irqreturn_t qca_link_intr_handle(int irq, void *phy_priv) - { - struct qca_phy_priv *priv = (struct qca_phy_priv *)phy_priv; - - disable_irq_nosync(irq); - schedule_work(&priv->intr_workqueue); - SSDK_DEBUG("irq number is :%x\n",irq); - - return IRQ_HANDLED; - } - - int qca_intr_init(struct qca_phy_priv *priv) -{ - SSDK_DEBUG("start to init the interrupt!\n"); - mutex_init(&priv->qm_lock); - INIT_WORK(&priv->intr_workqueue, qca_intr_workqueue_task); - qca_phy_disable_intr(priv); - qca_mac_disable_intr(priv); - if(request_irq(priv->link_interrupt_no, qca_link_intr_handle, priv->interrupt_flag, priv->link_intr_name, priv)) - return -1; - qca_phy_enable_intr(priv); - qca_mac_enable_intr(priv); - - return 0; -} - diff --git a/feeds/ipq807x/qca-ssdk/src/src/init/ssdk_led.c b/feeds/ipq807x/qca-ssdk/src/src/init/ssdk_led.c deleted file mode 100644 index c5dcd08ef..000000000 --- a/feeds/ipq807x/qca-ssdk/src/src/init/ssdk_led.c +++ /dev/null @@ -1,159 +0,0 @@ -/* - * Copyright (c) 2012, 2014-2020, The Linux Foundation. All rights reserved. - * Permission to use, copy, modify, and/or distribute this software for - * any purpose with or without fee is hereby granted, provided that the - * above copyright notice and this permission notice appear in all copies. - * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES - * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR - * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES - * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN - * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT - * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. - */ -#include "sw.h" -#include "ssdk_init.h" -#include "ssdk_led.h" -#include -#include -#include -#include "ssdk_plat.h" - -#if defined(CONFIG_OF) -#if (LINUX_VERSION_CODE >= KERNEL_VERSION(4,1,0)) -#if (LINUX_VERSION_CODE < KERNEL_VERSION(4,5,0)) -#include -#endif -#else -#include -#endif -#endif - - -#ifdef DESS -#if (LINUX_VERSION_CODE < KERNEL_VERSION(4,5,0)) -static int ssdk_dess_led_source_select(int led_num, enum led_source src_type) -{ -#if defined(CONFIG_OF) -#if (LINUX_VERSION_CODE >= KERNEL_VERSION(4,1,0)) - ipq_led_source_select(led_num, src_type); -#else - ipq40xx_led_source_select(led_num, src_type); -#endif -#endif - return 0; -} -#endif - -int ssdk_dess_led_init(ssdk_init_cfg *cfg) -{ -#if (LINUX_VERSION_CODE < KERNEL_VERSION(4,5,0)) - a_uint32_t i,led_num, led_source_id,source_id; - led_ctrl_pattern_t pattern; - - if(cfg->led_source_num != 0) { - for (i = 0; i < cfg->led_source_num; i++) { - - led_source_id = cfg->led_source_cfg[i].led_source_id; - pattern.mode = cfg->led_source_cfg[i].led_pattern.mode; - pattern.map = cfg->led_source_cfg[i].led_pattern.map; - pattern.freq = cfg->led_source_cfg[i].led_pattern.freq; -#ifdef IN_LED - fal_led_source_pattern_set(0, led_source_id,&pattern); -#endif - led_num = ((led_source_id -1) /3) + 3; - source_id = led_source_id % 3; - if (source_id == SRC_SELECTION_1) { - if (led_source_id == LED_SRC_ID_1) { - ssdk_dess_led_source_select(led_num, - LAN0_1000_LNK_ACTIVITY); - } - if (led_source_id == LED_SRC_ID_4) { - ssdk_dess_led_source_select(led_num, - LAN1_1000_LNK_ACTIVITY); - } - if (led_source_id == LED_SRC_ID_7) { - ssdk_dess_led_source_select(led_num, - LAN2_1000_LNK_ACTIVITY); - } - if (led_source_id == LED_SRC_ID_10) { - ssdk_dess_led_source_select(led_num, - LAN3_1000_LNK_ACTIVITY); - } - if (led_source_id == LED_SRC_ID_13) { - ssdk_dess_led_source_select(led_num, - WAN_1000_LNK_ACTIVITY); - } - } - if (source_id == SRC_SELECTION_2) { - if (led_source_id == LED_SRC_ID_2) { - ssdk_dess_led_source_select(led_num, - LAN0_100_LNK_ACTIVITY); - } - if (led_source_id == LED_SRC_ID_5) { - ssdk_dess_led_source_select(led_num, - LAN1_100_LNK_ACTIVITY); - } - if (led_source_id == LED_SRC_ID_8) { - ssdk_dess_led_source_select(led_num, - LAN2_100_LNK_ACTIVITY); - } - if (led_source_id == LED_SRC_ID_11) { - ssdk_dess_led_source_select(led_num, - LAN3_100_LNK_ACTIVITY); - } - if (led_source_id == LED_SRC_ID_14) { - ssdk_dess_led_source_select(led_num, - WAN_100_LNK_ACTIVITY); - } - } - if (source_id == SRC_SELECTION_0) { - if (led_source_id == LED_SRC_ID_3) { - ssdk_dess_led_source_select(led_num, - LAN0_10_LNK_ACTIVITY); - } - if (led_source_id == LED_SRC_ID_6) { - ssdk_dess_led_source_select(led_num, - LAN1_10_LNK_ACTIVITY); - } - if (led_source_id == LED_SRC_ID_9) { - ssdk_dess_led_source_select(led_num, - LAN2_10_LNK_ACTIVITY); - } - if (led_source_id == LED_SRC_ID_12) { - ssdk_dess_led_source_select(led_num, - LAN3_10_LNK_ACTIVITY); - } - if (led_source_id == LED_SRC_ID_15) { - ssdk_dess_led_source_select(led_num, - WAN_10_LNK_ACTIVITY); - } - } - } - } -#endif - return 0; -} -#endif - -#ifdef IN_LED -sw_error_t ssdk_led_init(a_uint32_t dev_id, ssdk_init_cfg *cfg) -{ - a_uint32_t src_index = 0, led_src_id = 0; - sw_error_t rv = SW_OK; - led_ctrl_pattern_t pattern = {0}; - - for(src_index = 0; src_index < cfg->led_source_num; src_index++) - { - pattern.mode = cfg->led_source_cfg[src_index].led_pattern.mode; - pattern.map = cfg->led_source_cfg[src_index].led_pattern.map; - led_src_id = cfg->led_source_cfg[src_index].led_source_id; - SSDK_INFO("ssdk_led_mode:%x, ssdk_led_map:%x, ssdk_led_src_id:%x\n", - pattern.mode, pattern.map, led_src_id); - rv = fal_led_source_pattern_set(dev_id, led_src_id, &pattern); - SW_RTN_ON_ERROR(rv); - } - - return SW_OK; -} -#endif diff --git a/feeds/ipq807x/qca-ssdk/src/src/init/ssdk_mp.c b/feeds/ipq807x/qca-ssdk/src/src/init/ssdk_mp.c deleted file mode 100644 index d28670a4e..000000000 --- a/feeds/ipq807x/qca-ssdk/src/src/init/ssdk_mp.c +++ /dev/null @@ -1,120 +0,0 @@ -/* - * Copyright (c) 2019-2020, The Linux Foundation. All rights reserved. - * - * Permission to use, copy, modify, and/or distribute this software for any - * purpose with or without fee is hereby granted, provided that the above - * copyright notice and this permission notice appear in all copies. - * - * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES - * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR - * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES - * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN - * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF - * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. - */ - -#include "ssdk_init.h" -#include "ssdk_plat.h" -#include "ssdk_dts.h" -#include "ssdk_mp.h" -#include "adpt.h" -#include "ssdk_led.h" -#include "ssdk_clk.h" - -#ifdef IN_PORTCONTROL -sw_error_t -qca_mp_portctrl_hw_init(a_uint32_t dev_id) -{ - sw_error_t rv = SW_OK; - a_uint32_t i = 0; - fal_port_eee_cfg_t port_eee_cfg; - a_bool_t force_port; - - memset(&port_eee_cfg, 0, sizeof(fal_port_eee_cfg_t)); - - for (i = SSDK_PHYSICAL_PORT1; i <= SSDK_PHYSICAL_PORT2; i++) { - force_port = ssdk_port_feature_get(dev_id, i, - PHY_F_FORCE); - if (force_port == A_FALSE) { - fal_port_txmac_status_set (dev_id, i, A_FALSE); - fal_port_rxmac_status_set (dev_id, i, A_FALSE); - /* init mac's lpi wake up timer to 70us */ - port_eee_cfg.lpi_wakeup_timer = MP_LPI_WAKEUP_TIMER; - fal_port_interface_eee_cfg_set(dev_id, i, &port_eee_cfg); - } else { - fal_port_txmac_status_set (dev_id, i, A_TRUE); - fal_port_rxmac_status_set (dev_id, i, A_TRUE); - } - fal_port_rxfc_status_set(dev_id, i, A_FALSE); - fal_port_txfc_status_set(dev_id, i, A_FALSE); - fal_port_max_frame_size_set(dev_id, i, - FAL_DEFAULT_MAX_FRAME_SIZE); - fal_port_promisc_mode_set(dev_id, i, A_TRUE); - /* init software level port status */ - qca_mac_port_status_init(dev_id, i); - /*enable ICC efuse loading*/ - ssdk_mp_gephy_icc_efuse_load_enable(A_TRUE); - } - return rv; -} -#endif -sw_error_t -qca_mp_interface_mode_init(a_uint32_t dev_id) -{ - sw_error_t rv = SW_OK; - adpt_api_t *p_api; - a_uint32_t i = 0, mode = 0; - a_bool_t force_port; - a_uint32_t force_speed = 0; - - SW_RTN_ON_NULL(p_api = adpt_api_ptr_get(dev_id)); - SW_RTN_ON_NULL(p_api->adpt_uniphy_mode_set); - SW_RTN_ON_NULL(p_api->adpt_port_mac_speed_set); - SW_RTN_ON_NULL(p_api->adpt_port_mac_duplex_set); - - mode = ssdk_dt_global_get_mac_mode(dev_id, SSDK_UNIPHY_INSTANCE0); - - rv = p_api->adpt_uniphy_mode_set(dev_id, SSDK_UNIPHY_INSTANCE0, - mode); - SW_RTN_ON_ERROR(rv); - - for (i = SSDK_PHYSICAL_PORT1; i <= SSDK_PHYSICAL_PORT2; i++) { - force_port = ssdk_port_feature_get(dev_id, i, PHY_F_FORCE); - if (force_port == A_TRUE) { - force_speed = ssdk_port_force_speed_get(dev_id, i); - rv = p_api->adpt_port_mac_speed_set(dev_id, - i, force_speed); - } else { - rv = p_api->adpt_port_mac_speed_set(dev_id, - i, FAL_SPEED_1000); - } - SW_RTN_ON_ERROR(rv); - rv = p_api->adpt_port_mac_duplex_set(dev_id, i, FAL_FULL_DUPLEX); - SW_RTN_ON_ERROR(rv); - } - - return rv; -} - -sw_error_t -qca_mp_hw_init(a_uint32_t dev_id, ssdk_init_cfg *cfg) -{ - sw_error_t rv = SW_OK; - -#ifdef IN_PORTCONTROL - rv = qca_mp_portctrl_hw_init(dev_id); - SW_RTN_ON_ERROR(rv); -#endif -#ifdef IN_MIB - rv = fal_mib_cpukeep_set(dev_id, A_FALSE); - SW_RTN_ON_ERROR(rv); -#endif - rv = qca_mp_interface_mode_init(dev_id); - SW_RTN_ON_ERROR(rv) -#ifdef IN_LED - /*init MP led*/ - rv = ssdk_led_init(dev_id, cfg); -#endif - return rv; -} diff --git a/feeds/ipq807x/qca-ssdk/src/src/init/ssdk_phy_i2c.c b/feeds/ipq807x/qca-ssdk/src/src/init/ssdk_phy_i2c.c deleted file mode 100755 index 8d9c5ff30..000000000 --- a/feeds/ipq807x/qca-ssdk/src/src/init/ssdk_phy_i2c.c +++ /dev/null @@ -1,462 +0,0 @@ -/* - * Copyright (c) 2018, The Linux Foundation. All rights reserved. - * Permission to use, copy, modify, and/or distribute this software for - * any purpose with or without fee is hereby granted, provided that the - * above copyright notice and this permission notice appear in all copies. - * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES - * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR - * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES - * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN - * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT - * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. - */ -/*qca808x_start*/ -#include "sw.h" -#include "ssdk_phy_i2c.h" -#include -#include "ssdk_init.h" -#include "ssdk_plat.h" - -#define I2C_RW_LIMIT 8 -#define I2C_ADAPTER_DEFAULT_ID 0 - -/****************************************************************************** -* -* _qca_i2c_read - read data per i2c bus -* -* read data per i2c bus -*/ -static inline a_int16_t -_qca_i2c_read(a_uint32_t i2c_bus_id, a_uint32_t i2c_slave, - a_uint32_t data_addr, a_uint8_t *buf, a_uint32_t count) -{ - a_int16_t ret, i; - struct i2c_adapter *adapt; - a_uint8_t addrbuf[2]; - struct i2c_msg msg[2]; - - ret =0; - i = 0; - - if (data_addr & 0xff00) { - addrbuf[i++] = (data_addr >> 8) & 0xff; - } - - addrbuf[i++] = data_addr & 0xff; - - if (count > I2C_RW_LIMIT) { - count = I2C_RW_LIMIT; - } - - /* - * msg for configuring the address - */ - aos_mem_set(msg, 0, sizeof(msg)); - msg[0].addr = i2c_slave; - msg[0].len = i; - msg[0].buf = addrbuf; - - /* - * msg for acquiring data - */ - msg[1].addr = i2c_slave; - msg[1].flags = I2C_M_RD; - msg[1].len = count; - msg[1].buf = buf; - - adapt = i2c_get_adapter(i2c_bus_id); - if (adapt) { - ret = i2c_transfer(adapt, msg, ARRAY_SIZE(msg)); - i2c_put_adapter(adapt); - } - - if (ret == ARRAY_SIZE(msg)) { - return count; - } - - return ret; -} - -/****************************************************************************** -* -* qca_i2c_data_get - wrapper of reading data per i2c bus -* -* wrapper of reading data per i2c bus -*/ -sw_error_t -qca_i2c_data_get(a_uint32_t dev_id, a_uint32_t i2c_slave, - a_uint32_t data_addr, a_uint8_t *buf, a_uint32_t count) -{ - a_int16_t ret = 0, cur = 0; - a_uint16_t cnt = count; - - while (cnt) { - cur = _qca_i2c_read(I2C_ADAPTER_DEFAULT_ID, - i2c_slave, data_addr, buf, cnt); - - /* No such i2c_slave device */ - if (cur == -ENXIO) { - return SW_NO_RESOURCE; - } - - if (cur <= 0) { - break; - } - /* - * loop to acquire the data from the new - * address based on the returned count. - */ - cnt -= cur; - buf += cur; - data_addr += cur; - ret += cur; - } - - if (ret != count) { - return SW_FAIL; - } - - return SW_OK; -} - -/****************************************************************************** -* -* _qca_i2c_write - write data per i2c bus -* -* write data per i2c bus -*/ -static inline a_int16_t -_qca_i2c_write(a_uint32_t i2c_bus_id, a_uint32_t i2c_slave, - a_uint32_t data_addr, a_uint8_t *buf, a_uint32_t count) -{ - a_int16_t ret, i; - struct i2c_adapter *adapt; - struct i2c_msg msg; - a_uint8_t i2c_wbuf[I2C_RW_LIMIT+2]; - - ret = 0; - i = 0; - - if (data_addr & 0xff00) { - i2c_wbuf[i++] = (data_addr >> 8) & 0xff; - } - - /* - * the write buffer is for saving address - * and the data to sent. - */ - i2c_wbuf[i++] = data_addr & 0xff; - - if (count > I2C_RW_LIMIT) { - count = I2C_RW_LIMIT; - } - memcpy(&i2c_wbuf[i], buf, count); - - aos_mem_set(&msg, 0, sizeof(msg)); - msg.addr = i2c_slave; - msg.len = i + count; - msg.buf = i2c_wbuf; - - adapt = i2c_get_adapter(i2c_bus_id); - if (adapt) { - ret = i2c_transfer(adapt, &msg, 1); - i2c_put_adapter(adapt); - } - - if (ret == 1) { - return count; - } - - return ret; -} - -/****************************************************************************** -* -* qca_i2c_data_set - wrapper of writting data per i2c bus -* -* wrapper of writting data per i2c bus -*/ -sw_error_t -qca_i2c_data_set(a_uint32_t dev_id, a_uint32_t i2c_slave, - a_uint32_t data_addr, a_uint8_t *buf, a_uint32_t count) -{ - a_int16_t ret = 0, cur = 0; - a_uint16_t cnt = count; - - while (cnt) { - cur = _qca_i2c_write(I2C_ADAPTER_DEFAULT_ID, - i2c_slave, data_addr, buf, cnt); - - /* No such i2c_slave device */ - if (cur == -ENXIO) { - return SW_NO_RESOURCE; - } - - if (cur <= 0) { - break; - } - /* - * loop to write the data to the new - * address based on the returned count. - */ - cnt -= cur; - buf += cur; - data_addr += cur; - ret += cur; - } - - if (ret != count) { - return SW_FAIL; - } - - return SW_OK; -} - -/****************************************************************************** -* -* _qca_phy_i2c_mii_read - mii register i2c read -* -* mii register i2c read -*/ -sw_error_t -qca_phy_i2c_mii_read(a_uint32_t dev_id, a_uint32_t phy_addr, - a_uint32_t reg_addr, a_uint16_t *reg_data) -{ - sw_error_t ret; - a_uint8_t rx[2] = { 0 }; - - reg_addr &= 0xff; - - ret = qca_i2c_data_get(dev_id, phy_addr, - reg_addr, rx, sizeof(rx)); - - if (ret == SW_OK) { - *reg_data = (rx[0] << 8) | rx[1]; - } else { - *reg_data = 0xffff; - } - - return ret; -} - -/****************************************************************************** -* -* _qca_phy_i2c_mii_write - mii register i2c write -* -* mii register i2c write -*/ -sw_error_t -qca_phy_i2c_mii_write(a_uint32_t dev_id, a_uint32_t phy_addr, - a_uint32_t reg_addr, a_uint16_t reg_data) -{ - sw_error_t ret; - a_uint8_t tx[2] = {(reg_data >> 8) & 0xff, reg_data & 0xff}; - - reg_addr &= 0xff; - - ret = qca_i2c_data_set(dev_id, phy_addr, - reg_addr, tx, sizeof(tx)); - - return ret; -} - -#ifdef IN_PHY_I2C_MODE -/****************************************************************************** -* -* _qca_phy_i2c_mmd_read - mmd register i2c read -* -* mmd register i2c read -*/ -sw_error_t -qca_phy_i2c_mmd_read(a_uint32_t dev_id, a_uint32_t phy_addr, a_uint16_t mmd_num, - a_uint32_t reg_addr, a_uint16_t *reg_data) -{ - a_uint8_t ret; - struct i2c_adapter *adapt; - /* - TX buffer to send: - 1st byte: Bit[6](1:MMD 0:MII) Bit[5](1:MMD address 0:MMD data) Bit[4:0](MMD num) - 2nd byte is high 8bits of reg addr - 3rd byte is low 8bits of reg addr - 4th byte: add one extra byte at the end of address writing msg to avoid qca808x - treat it as data writing operation - */ - a_uint8_t tx[4] = { ((QCA_PHY_I2C_IS_MMD << QCA_PHY_I2C_MMD_OR_MII_SHIFT) | - (QCA_PHY_I2C_MMD_IS_ADDR << QCA_PHY_I2C_MMD_ADDR_OR_DATA_SHIFT) | mmd_num), - (reg_addr >> 8) & 0xff, reg_addr & 0xff, 0 }; - /* - RX buffer to receive: - 1st byte is high 8bits of reg data - 2nd byte is low 8bits of reg data - */ - a_uint8_t rx[2] = { 0 }; - struct i2c_msg msg[] = { - { .addr = phy_addr, .flags = 0, - .buf = tx, .len = sizeof(tx) }, - { .addr = phy_addr, .flags = I2C_M_RD, - .buf = rx, .len = sizeof(rx) } }; - - if((mmd_num != QCA_PHY_MMD1_NUM) && (mmd_num != QCA_PHY_MMD3_NUM) && - (mmd_num != QCA_PHY_MMD7_NUM)) { - SSDK_ERROR("wrong MMD number:[%d]\n", mmd_num); - return SW_FAIL; - } - - adapt = i2c_get_adapter(I2C_ADAPTER_DEFAULT_ID); - if (!adapt) { - return SW_FAIL; - } - - ret = i2c_transfer(adapt, msg, ARRAY_SIZE(msg)); - *reg_data = (rx[0] << 8) | rx[1]; - - i2c_put_adapter(adapt); - - if (ret != ARRAY_SIZE(msg)) { - return SW_FAIL; - } - - return SW_OK; -} - -/****************************************************************************** -* -* _qca_phy_i2c_mmd_write - mmd register i2c write -* -* mmd register i2c write -*/ -sw_error_t -qca_phy_i2c_mmd_write(a_uint32_t dev_id, a_uint32_t phy_addr, a_uint16_t mmd_num, - a_uint32_t reg_addr, a_uint16_t reg_data) -{ - a_uint8_t ret; - struct i2c_adapter *adapt; - /* - First TX buffer to send: - 1st byte: Bit[6](1:MMD 0:MII) Bit[5](1:MMD address 0:MMD data) Bit[4:0](MMD num) - 2nd byte is high 8bits of reg addr - 3rd byte is low 8bits of reg addr - 4th byte: add one extra byte at the end of address writing msg to avoid qca808x - treat it as data writing operation - */ - a_uint8_t tx[4] = { ((QCA_PHY_I2C_IS_MMD << QCA_PHY_I2C_MMD_OR_MII_SHIFT) | - (QCA_PHY_I2C_MMD_IS_ADDR << QCA_PHY_I2C_MMD_ADDR_OR_DATA_SHIFT) | mmd_num), - (reg_addr >> 8) & 0xff, reg_addr & 0xff, 0 }; - - /* - Second TX buffer to send: - 1st byte: Bit[6](1:MMD 0:MII) Bit[5](1:MMD address 0:MMD data) Bit[4:0](MMD num) - 2nd byte is high 8bits of reg data - 3rd byte is low 8bits of reg data - */ - a_uint8_t tx2[3] = { ((QCA_PHY_I2C_IS_MMD << QCA_PHY_I2C_MMD_OR_MII_SHIFT) | - (QCA_PHY_I2C_MMD_IS_DATA << QCA_PHY_I2C_MMD_ADDR_OR_DATA_SHIFT) | mmd_num), - (reg_data >> 8) & 0xff, reg_data & 0xff }; - - struct i2c_msg msg[] = { - { .addr = phy_addr, .flags = 0, - .buf = tx, .len = sizeof(tx) }, - { .addr = phy_addr, .flags = 0, - .buf = tx2, .len = sizeof(tx2) } }; - - if((mmd_num != QCA_PHY_MMD1_NUM) && (mmd_num != QCA_PHY_MMD3_NUM) && - (mmd_num != QCA_PHY_MMD7_NUM)) { - SSDK_ERROR("wrong MMD number:[%d]\n", mmd_num); - return SW_FAIL; - } - - adapt = i2c_get_adapter(I2C_ADAPTER_DEFAULT_ID); - if (!adapt) { - return SW_FAIL; - } - - ret = i2c_transfer(adapt, msg, ARRAY_SIZE(msg)); - - i2c_put_adapter(adapt); - - if (ret != ARRAY_SIZE(msg)) { - return SW_FAIL; - } - - return SW_OK; -} - -/****************************************************************************** -* -* qca_phy_is_i2c_addr - check if phy addr is i2c addr -* -* check if phy addr is i2c addr -*/ -a_bool_t -qca_phy_is_i2c_addr(a_uint32_t phy_addr) -{ - if(((phy_addr & QCA_PHY_I2C_DEVADDR_MASK) == - QCA_PHY_I2C_PHYCORE_DEVADDR) || - ((phy_addr & QCA_PHY_I2C_DEVADDR_MASK) == - QCA_PHY_I2C_SERDES_DEVADDR)) { - return A_TRUE; - } else { - return A_FALSE; - } -} - -/****************************************************************************** -* -* qca_phy_i2c_read - PHY register i2c read -* -* PHY register i2c read -*/ -sw_error_t -qca_phy_i2c_read(a_uint32_t dev_id, a_uint32_t phy_addr, - a_uint32_t reg_addr_c45, a_uint16_t *reg_data) -{ - a_uint32_t mmd_num = QCA_PHY_MII_ADDR_C45_MMD_NUM(reg_addr_c45); - a_uint32_t reg_addr = QCA_PHY_MII_ADDR_C45_REG_ADDR(reg_addr_c45); - - if(qca_phy_is_i2c_addr(phy_addr) == A_FALSE) { - return SW_BAD_PARAM; - } - - if(QCA_PHY_MII_ADDR_C45_IS_MMD(reg_addr_c45)) { - qca_phy_i2c_mmd_read(dev_id, phy_addr, mmd_num, reg_addr, reg_data); - - } else { - qca_phy_i2c_mii_read(dev_id, phy_addr, reg_addr, reg_data); - } - - return SW_OK; -} - -/****************************************************************************** -* -* qca_phy_i2c_write - PHY register i2c write -* -* PHY register i2c write -*/ -sw_error_t -qca_phy_i2c_write(a_uint32_t dev_id, a_uint32_t phy_addr, - a_uint32_t reg_addr_c45, a_uint16_t reg_data) -{ - a_uint32_t mmd_num = QCA_PHY_MII_ADDR_C45_MMD_NUM(reg_addr_c45); - a_uint32_t reg_addr = QCA_PHY_MII_ADDR_C45_REG_ADDR(reg_addr_c45); - - if(qca_phy_is_i2c_addr(phy_addr) == A_FALSE) { - return SW_BAD_PARAM; - } - - if(QCA_PHY_MII_ADDR_C45_IS_MMD(reg_addr_c45)) { - qca_phy_i2c_mmd_write(dev_id, phy_addr, mmd_num, reg_addr, reg_data); - - } else { - qca_phy_i2c_mii_write(dev_id, phy_addr, reg_addr, reg_data); - } - - return SW_OK; -} -/*qca808x_end*/ -EXPORT_SYMBOL(qca_phy_i2c_read); -EXPORT_SYMBOL(qca_phy_i2c_write); -/*qca808x_start*/ -#endif -/*qca808x_start*/ diff --git a/feeds/ipq807x/qca-ssdk/src/src/init/ssdk_plat.c b/feeds/ipq807x/qca-ssdk/src/src/init/ssdk_plat.c deleted file mode 100755 index 1bb848260..000000000 --- a/feeds/ipq807x/qca-ssdk/src/src/init/ssdk_plat.c +++ /dev/null @@ -1,1417 +0,0 @@ -/* - * Copyright (c) 2017-2019, The Linux Foundation. All rights reserved. - * Permission to use, copy, modify, and/or distribute this software for - * any purpose with or without fee is hereby granted, provided that the - * above copyright notice and this permission notice appear in all copies. - * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES - * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR - * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES - * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN - * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT - * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. - */ -/*qca808x_start*/ -#include "sw.h" -#include "ssdk_init.h" -#include "fal_init.h" -#include "fal.h" -#include "hsl.h" -#include "hsl_dev.h" -#include "ssdk_init.h" -/*qca808x_end*/ -#include "ssdk_dts.h" -#if (defined(HPPE) || defined(MP)) -#include "hppe_init.h" -#endif -#include -/*qca808x_start*/ -#include -/*qca808x_end*/ -#include -#include -#include -#include -#include -//#include -#include -#include -#include -#include -#include -#include -#include -#include - -#if defined(ISIS) ||defined(ISISC) ||defined(GARUDA) -#include -#endif -#if defined(ATHENA) ||defined(SHIVA) ||defined(HORUS) -#include -#endif -#ifdef IN_MALIBU_PHY -#include -#endif -/*qca808x_start*/ -#if defined(CONFIG_OF) && (LINUX_VERSION_CODE >= KERNEL_VERSION(4,1,0)) -#include -#include -#include -#elif defined(CONFIG_OF) && (LINUX_VERSION_CODE >= KERNEL_VERSION(3,14,0)) -#include -#include -#include -#include -#include -#else -#include -#include -#include -#endif -#include "ssdk_plat.h" -/*qca808x_end*/ -#include "ssdk_clk.h" -#include "ref_vlan.h" -#include "ref_fdb.h" -#include "ref_mib.h" -#include "ref_port_ctrl.h" -#include "ref_misc.h" -#include "ref_uci.h" -#include "shell.h" -#ifdef BOARD_AR71XX -#include "ssdk_uci.h" -#endif - -#include "hsl_phy.h" -#ifdef IN_LINUX_STD_PTP -#include "qca808x_ptp.h" -#endif - -#ifdef IN_IP -#if defined (CONFIG_NF_FLOW_COOKIE) -#include "fal_flowcookie.h" -#ifdef IN_SFE -#include -#endif -#endif -#endif - -#ifdef IN_RFS -#if defined(CONFIG_VLAN_8021Q) || defined(CONFIG_VLAN_8021Q_MODULE) -#include -#endif -#include -#ifdef IN_IP -#include "fal_rfs.h" -#endif -#endif - -#include "adpt.h" -/*qca808x_start*/ - -extern struct qca_phy_priv **qca_phy_priv_global; -extern ssdk_chip_type SSDK_CURRENT_CHIP_TYPE; -/*qca808x_end*/ -struct mutex switch_mdio_lock; - -#ifdef BOARD_IPQ806X -#define PLATFORM_MDIO_BUS_NAME "mdio-gpio" -#endif - -#ifdef BOARD_AR71XX -#define PLATFORM_MDIO_BUS_NAME "ag71xx-mdio" -#endif -/*qca808x_start*/ -#define MDIO_BUS_0 0 -#define MDIO_BUS_1 1 -/*qca808x_end*/ -#define PLATFORM_MDIO_BUS_NUM MDIO_BUS_0 - -#define ISIS_CHIP_ID 0x18 -#define ISIS_CHIP_REG 0 -#define SHIVA_CHIP_ID 0x1f -#define SHIVA_CHIP_REG 0x10 -#define HIGH_ADDR_DFLT 0x200 - -/* - * Using ISIS's address as default - */ -static int switch_chip_id = ISIS_CHIP_ID; -static int switch_chip_reg = ISIS_CHIP_REG; - -static int ssdk_dev_id = 0; -/*qca808x_start*/ -a_uint32_t ssdk_log_level = SSDK_LOG_LEVEL_DEFAULT; -/*qca808x_end*/ - -#if defined(CONFIG_OF) && (LINUX_VERSION_CODE >= KERNEL_VERSION(3,14,0)) -struct ag71xx_mdio { - struct mii_bus *mii_bus; - int mii_irq[PHY_MAX_ADDR]; - void __iomem *mdio_base; -}; -#endif - -#ifdef BOARD_AR71XX -static uint32_t switch_chip_id_adjuest(a_uint32_t dev_id) -{ - uint32_t chip_version = 0; - chip_version = (qca_ar8216_mii_read(dev_id, 0)&0xff00)>>8; - if((chip_version !=0) && (chip_version !=0xff)) - return 0; - - switch_chip_id = SHIVA_CHIP_ID; - switch_chip_reg = SHIVA_CHIP_REG; - - chip_version = (qca_ar8216_mii_read(dev_id, 0)&0xff00)>>8; - printk("chip_version:0x%x\n", chip_version); - return 1; -} -#endif - -static inline void -split_addr(uint32_t regaddr, uint16_t *r1, uint16_t *r2, uint16_t *page) -{ - regaddr >>= 1; - *r1 = regaddr & 0x1e; - - regaddr >>= 5; - *r2 = regaddr & 0x7; - - regaddr >>= 3; - *page = regaddr & 0x3ff; -} - -a_uint32_t -qca_ar8216_mii_read(a_uint32_t dev_id, a_uint32_t reg) -{ - struct mii_bus *bus; - uint16_t r1, r2, page; - uint16_t lo, hi; - - bus = qca_phy_priv_global[dev_id]->miibus; - - split_addr((uint32_t) reg, &r1, &r2, &page); - mutex_lock(&switch_mdio_lock); - mdiobus_write(bus, switch_chip_id, switch_chip_reg, page); - udelay(100); - lo = mdiobus_read(bus, 0x10 | r2, r1); - hi = mdiobus_read(bus, 0x10 | r2, r1 + 1); - mdiobus_write(bus, switch_chip_id, switch_chip_reg, HIGH_ADDR_DFLT); - mutex_unlock(&switch_mdio_lock); - return (hi << 16) | lo; -} - -void -qca_ar8216_mii_write(a_uint32_t dev_id, a_uint32_t reg, a_uint32_t val) -{ - struct mii_bus *bus; - uint16_t r1, r2, r3; - uint16_t lo, hi; - - bus = qca_phy_priv_global[dev_id]->miibus; - - split_addr((a_uint32_t) reg, &r1, &r2, &r3); - lo = val & 0xffff; - hi = (a_uint16_t) (val >> 16); - - mutex_lock(&switch_mdio_lock); - mdiobus_write(bus, switch_chip_id, switch_chip_reg, r3); - udelay(100); - if(SSDK_CURRENT_CHIP_TYPE != CHIP_SHIVA) { - mdiobus_write(bus, 0x10 | r2, r1, lo); - mdiobus_write(bus, 0x10 | r2, r1 + 1, hi); - } else { - mdiobus_write(bus, 0x10 | r2, r1 + 1, hi); - mdiobus_write(bus, 0x10 | r2, r1, lo); - } - mdiobus_write(bus, switch_chip_id, switch_chip_reg, HIGH_ADDR_DFLT); - mutex_unlock(&switch_mdio_lock); -} - -/*qca808x_start*/ -a_bool_t -phy_addr_validation_check(a_uint32_t phy_addr) -{ - - if ((phy_addr > SSDK_PHY_BCAST_ID) || (phy_addr < SSDK_PHY_MIN_ID)) - return A_FALSE; - else - return A_TRUE; -} - -static struct mii_bus * -ssdk_phy_miibus_get(a_uint32_t dev_id, a_uint32_t phy_addr) -{ - struct mii_bus *bus = NULL; -/*qca808x_end*/ -#ifndef BOARD_AR71XX -#if defined(CONFIG_OF) && (LINUX_VERSION_CODE >= KERNEL_VERSION(3,14,0)) - bus = ssdk_dts_miibus_get(dev_id, phy_addr); -#endif -#endif -/*qca808x_start*/ - if (!bus) - bus = qca_phy_priv_global[dev_id]->miibus; - - return bus; -} - -sw_error_t -qca_ar8327_phy_read(a_uint32_t dev_id, a_uint32_t phy_addr, - a_uint32_t reg, a_uint16_t* data) -{ - struct mii_bus *bus = NULL; - - if (A_TRUE != phy_addr_validation_check (phy_addr)) - { - return SW_BAD_PARAM; - } - - bus = ssdk_phy_miibus_get(dev_id, phy_addr); - if (!bus) - return SW_NOT_SUPPORTED; - - *data = mdiobus_read(bus, phy_addr, reg); - return 0; -} - -sw_error_t -qca_ar8327_phy_write(a_uint32_t dev_id, a_uint32_t phy_addr, - a_uint32_t reg, a_uint16_t data) -{ - struct mii_bus *bus = NULL; - - if (A_TRUE != phy_addr_validation_check (phy_addr)) - { - return SW_BAD_PARAM; - } - - bus = ssdk_phy_miibus_get(dev_id, phy_addr); - if (!bus) - return SW_NOT_SUPPORTED; - - mdiobus_write(bus, phy_addr, reg, data); - return 0; -} - -void -qca_ar8327_phy_dbg_write(a_uint32_t dev_id, a_uint32_t phy_addr, - a_uint16_t dbg_addr, a_uint16_t dbg_data) -{ - struct mii_bus *bus = NULL; - - if (A_TRUE != phy_addr_validation_check (phy_addr)) - { - return; - } - - bus = ssdk_phy_miibus_get(dev_id, phy_addr); - if (!bus) - return; - - mdiobus_write(bus, phy_addr, QCA_MII_DBG_ADDR, dbg_addr); - mdiobus_write(bus, phy_addr, QCA_MII_DBG_DATA, dbg_data); -} - -void -qca_ar8327_phy_dbg_read(a_uint32_t dev_id, a_uint32_t phy_addr, - a_uint16_t dbg_addr, a_uint16_t *dbg_data) -{ - struct mii_bus *bus = NULL; - - if (A_TRUE != phy_addr_validation_check (phy_addr)) - { - return; - } - - bus = ssdk_phy_miibus_get(dev_id, phy_addr); - if (!bus) - return; - - mdiobus_write(bus, phy_addr, QCA_MII_DBG_ADDR, dbg_addr); - *dbg_data = mdiobus_read(bus, phy_addr, QCA_MII_DBG_DATA); -} - - -void -qca_ar8327_mmd_write(a_uint32_t dev_id, a_uint32_t phy_addr, - a_uint16_t addr, a_uint16_t data) -{ - struct mii_bus *bus = NULL; - - if (A_TRUE != phy_addr_validation_check (phy_addr)) - { - return; - } - - bus = ssdk_phy_miibus_get(dev_id, phy_addr); - if (!bus) - return; - - mdiobus_write(bus, phy_addr, QCA_MII_MMD_ADDR, addr); - mdiobus_write(bus, phy_addr, QCA_MII_MMD_DATA, data); -} - -void qca_phy_mmd_write(u32 dev_id, u32 phy_id, - u16 mmd_num, u16 reg_id, u16 reg_val) -{ - qca_ar8327_phy_write(dev_id, phy_id, - QCA_MII_MMD_ADDR, mmd_num); - qca_ar8327_phy_write(dev_id, phy_id, - QCA_MII_MMD_DATA, reg_id); - qca_ar8327_phy_write(dev_id, phy_id, - QCA_MII_MMD_ADDR, - 0x4000 | mmd_num); - qca_ar8327_phy_write(dev_id, phy_id, - QCA_MII_MMD_DATA, reg_val); -} - -u16 qca_phy_mmd_read(u32 dev_id, u32 phy_id, - u16 mmd_num, u16 reg_id) -{ - u16 value = 0; - qca_ar8327_phy_write(dev_id, phy_id, - QCA_MII_MMD_ADDR, mmd_num); - qca_ar8327_phy_write(dev_id, phy_id, - QCA_MII_MMD_DATA, reg_id); - qca_ar8327_phy_write(dev_id, phy_id, - QCA_MII_MMD_ADDR, - 0x4000 | mmd_num); - qca_ar8327_phy_read(dev_id, phy_id, - QCA_MII_MMD_DATA, &value); - return value; -} -/*qca808x_end*/ -sw_error_t -qca_switch_reg_read(a_uint32_t dev_id, a_uint32_t reg_addr, a_uint8_t * reg_data, a_uint32_t len) -{ - uint32_t reg_val = 0; - - if (len != sizeof (a_uint32_t)) - return SW_BAD_LEN; - - if ((reg_addr%4)!= 0) - return SW_BAD_PARAM; - - reg_val = readl(qca_phy_priv_global[dev_id]->hw_addr + reg_addr); - - aos_mem_copy(reg_data, ®_val, sizeof (a_uint32_t)); - return 0; -} - -sw_error_t -qca_switch_reg_write(a_uint32_t dev_id, a_uint32_t reg_addr, a_uint8_t * reg_data, a_uint32_t len) -{ - uint32_t reg_val = 0; - if (len != sizeof (a_uint32_t)) - return SW_BAD_LEN; - - if ((reg_addr%4)!= 0) - return SW_BAD_PARAM; - - aos_mem_copy(®_val, reg_data, sizeof (a_uint32_t)); - writel(reg_val, qca_phy_priv_global[dev_id]->hw_addr + reg_addr); - return 0; -} - -sw_error_t -qca_psgmii_reg_read(a_uint32_t dev_id, a_uint32_t reg_addr, a_uint8_t * reg_data, a_uint32_t len) -{ -#ifdef DESS - uint32_t reg_val = 0; - - if (len != sizeof (a_uint32_t)) - return SW_BAD_LEN; - - if((reg_addr%4)!=0) - return SW_BAD_PARAM; - - if (qca_phy_priv_global[dev_id]->psgmii_hw_addr == NULL) - return SW_NOT_SUPPORTED; - - reg_val = readl(qca_phy_priv_global[dev_id]->psgmii_hw_addr + reg_addr); - - aos_mem_copy(reg_data, ®_val, sizeof (a_uint32_t)); -#endif - return 0; -} - -sw_error_t -qca_psgmii_reg_write(a_uint32_t dev_id, a_uint32_t reg_addr, a_uint8_t * reg_data, a_uint32_t len) -{ -#ifdef DESS - uint32_t reg_val = 0; - if (len != sizeof (a_uint32_t)) - return SW_BAD_LEN; - - if((reg_addr%4)!=0) - return SW_BAD_PARAM; - - if (qca_phy_priv_global[dev_id]->psgmii_hw_addr == NULL) - return SW_NOT_SUPPORTED; - - aos_mem_copy(®_val, reg_data, sizeof (a_uint32_t)); - writel(reg_val, qca_phy_priv_global[dev_id]->psgmii_hw_addr + reg_addr); -#endif - return 0; -} - -sw_error_t -qca_uniphy_reg_read(a_uint32_t dev_id, a_uint32_t uniphy_index, - a_uint32_t reg_addr, a_uint8_t * reg_data, a_uint32_t len) -{ -#if (defined(HPPE) || defined(MP)) - uint32_t reg_val = 0; - void __iomem *hppe_uniphy_base = NULL; - a_uint32_t reg_addr1, reg_addr2; - - if (len != sizeof (a_uint32_t)) - return SW_BAD_LEN; - - if (SSDK_UNIPHY_INSTANCE0 == uniphy_index) - hppe_uniphy_base = qca_phy_priv_global[dev_id]->uniphy_hw_addr; - else if (SSDK_UNIPHY_INSTANCE1 == uniphy_index) - hppe_uniphy_base = qca_phy_priv_global[dev_id]->uniphy_hw_addr + HPPE_UNIPHY_BASE1; - - else if (SSDK_UNIPHY_INSTANCE2 == uniphy_index) - hppe_uniphy_base = qca_phy_priv_global[dev_id]->uniphy_hw_addr + HPPE_UNIPHY_BASE2; - else - return SW_BAD_PARAM; - - if ( reg_addr > HPPE_UNIPHY_MAX_DIRECT_ACCESS_REG) - { - // uniphy reg indireclty access - reg_addr1 = (reg_addr & 0xffffff) >> 8; - writel(reg_addr1, hppe_uniphy_base + HPPE_UNIPHY_INDIRECT_REG_ADDR); - - reg_addr2 = reg_addr & HPPE_UNIPHY_INDIRECT_LOW_ADDR; - reg_addr = (HPPE_UNIPHY_INDIRECT_DATA << 10) | (reg_addr2 << 2); - - reg_val = readl(hppe_uniphy_base + reg_addr); - aos_mem_copy(reg_data, ®_val, sizeof (a_uint32_t)); - } - else - { // uniphy reg directly access - reg_val = readl(hppe_uniphy_base + reg_addr); - aos_mem_copy(reg_data, ®_val, sizeof (a_uint32_t)); - } -#endif - return 0; -} - -sw_error_t -qca_uniphy_reg_write(a_uint32_t dev_id, a_uint32_t uniphy_index, - a_uint32_t reg_addr, a_uint8_t * reg_data, a_uint32_t len) -{ -#if (defined(HPPE) || defined(MP)) - void __iomem *hppe_uniphy_base = NULL; - a_uint32_t reg_addr1, reg_addr2; - uint32_t reg_val = 0; - - if (len != sizeof (a_uint32_t)) - return SW_BAD_LEN; - - if (SSDK_UNIPHY_INSTANCE0 == uniphy_index) - hppe_uniphy_base = qca_phy_priv_global[dev_id]->uniphy_hw_addr; - else if (SSDK_UNIPHY_INSTANCE1 == uniphy_index) - hppe_uniphy_base = qca_phy_priv_global[dev_id]->uniphy_hw_addr + HPPE_UNIPHY_BASE1; - - else if (SSDK_UNIPHY_INSTANCE2 == uniphy_index) - hppe_uniphy_base = qca_phy_priv_global[dev_id]->uniphy_hw_addr + HPPE_UNIPHY_BASE2; - else - return SW_BAD_PARAM; - - if ( reg_addr > HPPE_UNIPHY_MAX_DIRECT_ACCESS_REG) - { - // uniphy reg indireclty access - reg_addr1 = (reg_addr & 0xffffff) >> 8; - writel(reg_addr1, hppe_uniphy_base + HPPE_UNIPHY_INDIRECT_REG_ADDR); - - reg_addr2 = reg_addr & HPPE_UNIPHY_INDIRECT_LOW_ADDR; - reg_addr = (HPPE_UNIPHY_INDIRECT_DATA << 10) | (reg_addr2 << 2); - aos_mem_copy(®_val, reg_data, sizeof (a_uint32_t)); - writel(reg_val, hppe_uniphy_base + reg_addr); - } - else - { // uniphy reg directly access - aos_mem_copy(®_val, reg_data, sizeof (a_uint32_t)); - writel(reg_val, hppe_uniphy_base + reg_addr); - } -#endif - return 0; -} -#ifndef BOARD_AR71XX -/*qca808x_start*/ -static int miibus_get(a_uint32_t dev_id) -{ -/*qca808x_end*/ -#if defined(CONFIG_OF) && (LINUX_VERSION_CODE >= KERNEL_VERSION(3,14,0)) -/*qca808x_start*/ - struct device_node *mdio_node = NULL; - struct device_node *switch_node = NULL; - struct platform_device *mdio_plat = NULL; - struct ipq40xx_mdio_data *mdio_data = NULL; - struct qca_phy_priv *priv; - hsl_reg_mode reg_mode = HSL_REG_LOCAL_BUS; - priv = qca_phy_priv_global[dev_id]; - switch_node = qca_phy_priv_global[dev_id]->of_node; - if (switch_node) { - mdio_node = of_parse_phandle(switch_node, "mdio-bus", 0); - if (mdio_node) { - priv->miibus = of_mdio_find_bus(mdio_node); - return 0; - } - } -/*qca808x_end*/ - reg_mode=ssdk_switch_reg_access_mode_get(dev_id); -/*qca808x_start*/ - if(reg_mode == HSL_REG_LOCAL_BUS) - mdio_node = of_find_compatible_node(NULL, NULL, "qcom,ipq40xx-mdio"); - else - mdio_node = of_find_compatible_node(NULL, NULL, "virtual,mdio-gpio"); - - if (!mdio_node) { - SSDK_ERROR("No MDIO node found in DTS!\n"); - return 1; - } - - mdio_plat = of_find_device_by_node(mdio_node); - if (!mdio_plat) { - SSDK_ERROR("cannot find platform device from mdio node\n"); - return 1; - } - - if(reg_mode == HSL_REG_LOCAL_BUS) - { - mdio_data = dev_get_drvdata(&mdio_plat->dev); - if (!mdio_data) { - SSDK_ERROR("cannot get mdio_data reference from device data\n"); - return 1; - } - priv->miibus = mdio_data->mii_bus; - } - else - priv->miibus = dev_get_drvdata(&mdio_plat->dev); - - if (!priv->miibus) { - SSDK_ERROR("cannot get mii bus reference from device data\n"); - return 1; - } -/*qca808x_end*/ -#else - struct device *miidev; - char busid[MII_BUS_ID_SIZE]; - struct qca_phy_priv *priv; - - priv = qca_phy_priv_global[dev_id]; - snprintf(busid, MII_BUS_ID_SIZE, "%s.%d", - PLATFORM_MDIO_BUS_NAME, PLATFORM_MDIO_BUS_NUM); - - miidev = bus_find_device_by_name(&platform_bus_type, NULL, busid); - if (!miidev) { - SSDK_ERROR("Failed to get miidev\n"); - return 1; - } - - priv->miibus = dev_get_drvdata(miidev); - - if(!priv->miibus){ - SSDK_ERROR("mdio bus '%s' get FAIL\n", busid); - return 1; - } -#endif -/*qca808x_start*/ - return 0; -} -/*qca808x_end*/ -#else -static int miibus_get(a_uint32_t dev_id) -{ - struct ag71xx_mdio *am; - struct qca_phy_priv *priv = qca_phy_priv_global[dev_id]; -#if defined(CONFIG_OF) && (LINUX_VERSION_CODE >= KERNEL_VERSION(3,14,0)) - struct device_node *mdio_node = NULL; - struct platform_device *mdio_plat = NULL; - - mdio_node = of_find_compatible_node(NULL, NULL, "qca,ag71xx-mdio"); - if (!mdio_node) { - SSDK_ERROR("No MDIO node found in DTS!\n"); - return 1; - } - mdio_plat = of_find_device_by_node(mdio_node); - if (!mdio_plat) { - SSDK_ERROR("cannot find platform device from mdio node\n"); - return 1; - } - am = dev_get_drvdata(&mdio_plat->dev); - if (!am) { - SSDK_ERROR("cannot get mdio_data reference from device data\n"); - return 1; - } - priv->miibus = am->mii_bus; - - switch_chip_id_adjuest(dev_id); -#else - struct device *miidev; - char busid[MII_BUS_ID_SIZE]; - - snprintf(busid, MII_BUS_ID_SIZE, "%s.%d", - PLATFORM_MDIO_BUS_NAME, PLATFORM_MDIO_BUS_NUM); - - miidev = bus_find_device_by_name(&platform_bus_type, NULL, busid); - if (!miidev) { - SSDK_ERROR("Failed to get miidev!\n"); - return 1; - } - am = dev_get_drvdata(miidev); - priv->miibus = am->mii_bus; - - if(switch_chip_id_adjuest(dev_id)) { - snprintf(busid, MII_BUS_ID_SIZE, "%s.%d", - PLATFORM_MDIO_BUS_NAME, MDIO_BUS_1); - - miidev = bus_find_device_by_name(&platform_bus_type, NULL, busid); - if (!miidev) { - SSDK_ERROR("Failed get mii bus\n"); - return 1; - } - - am = dev_get_drvdata(miidev); - priv->miibus = am->mii_bus; - SSDK_INFO("chip_version:0x%x\n", (qca_ar8216_mii_read(dev_id, 0)&0xff00)>>8); - } - - if(!miidev){ - SSDK_ERROR("mdio bus '%s' get FAIL\n", busid); - return 1; - } -#endif - - return 0; -} -#endif - -struct mii_bus *ssdk_miibus_get_by_device(a_uint32_t dev_id) -{ - return qca_phy_priv_global[dev_id]->miibus; -} - -static ssize_t ssdk_dev_id_get(struct device *dev, - struct device_attribute *attr, - char *buf) -{ - ssize_t count; - a_uint32_t num; - - num = (a_uint32_t)ssdk_dev_id; - - count = snprintf(buf, (ssize_t)PAGE_SIZE, "%u", num); - return count; -} - -static ssize_t ssdk_dev_id_set(struct device *dev, - struct device_attribute *attr, - const char *buf, size_t count) -{ - char num_buf[12]; - a_uint32_t num; - - if (count >= sizeof(num_buf)) return 0; - memcpy(num_buf, buf, count); - num_buf[count] = '\0'; - sscanf(num_buf, "%u", &num); - - ssdk_dev_id = num; - - return count; -} - -static ssize_t ssdk_log_level_get(struct device *dev, - struct device_attribute *attr, - char *buf) -{ - ssize_t count; - a_uint32_t num; - - num = ssdk_log_level; - - count = snprintf(buf, (ssize_t)PAGE_SIZE, "%u", num); - return count; -} - -static ssize_t ssdk_log_level_set(struct device *dev, - struct device_attribute *attr, - const char *buf, size_t count) -{ - char num_buf[12]; - a_uint32_t num; - - if (count >= sizeof(num_buf)) - return 0; - memcpy(num_buf, buf, count); - num_buf[count] = '\0'; - sscanf(num_buf, "%u", &num); - - ssdk_log_level = (a_uint32_t)num; - - return count; -} - -static ssize_t ssdk_packet_counter_get(struct device *dev, - struct device_attribute *attr, - char *buf) -{ - ssize_t count; - adpt_api_t *p_api; - - p_api = adpt_api_ptr_get(ssdk_dev_id); - if (p_api == NULL || p_api->adpt_debug_counter_get == NULL) - { - count = snprintf(buf, (ssize_t)PAGE_SIZE, "Unsupported\n"); - return count; - } - - count = snprintf(buf, (ssize_t)PAGE_SIZE, "\n"); - - p_api->adpt_debug_counter_get(A_FALSE); - - return count; -} - -static ssize_t ssdk_packet_counter_set(struct device *dev, - struct device_attribute *attr, - const char *buf, size_t count) -{ - char num_buf[12]; - adpt_api_t *p_api; - - p_api = adpt_api_ptr_get(ssdk_dev_id); - if (p_api == NULL || p_api->adpt_debug_counter_set == NULL) { - SSDK_WARN("Unsupported\n"); - return count; - } - - p_api->adpt_debug_counter_set(); - - if (count >= sizeof(num_buf)) - return 0; - memcpy(num_buf, buf, count); - num_buf[count] = '\0'; - - - return count; -} - -static ssize_t ssdk_byte_counter_get(struct device *dev, - struct device_attribute *attr, - char *buf) -{ - ssize_t count; - adpt_api_t *p_api; - - p_api = adpt_api_ptr_get(ssdk_dev_id); - if (p_api == NULL || p_api->adpt_debug_counter_get == NULL) - { - count = snprintf(buf, (ssize_t)PAGE_SIZE, "Unsupported\n"); - return count; - } - - count = snprintf(buf, (ssize_t)PAGE_SIZE, "\n"); - - p_api->adpt_debug_counter_get(A_TRUE); - - return count; -} - -static ssize_t ssdk_byte_counter_set(struct device *dev, - struct device_attribute *attr, - const char *buf, size_t count) -{ - char num_buf[12]; - adpt_api_t *p_api; - - p_api = adpt_api_ptr_get(ssdk_dev_id); - if (p_api == NULL || p_api->adpt_debug_counter_set == NULL) { - SSDK_WARN("Unsupported\n"); - return count; - } - - p_api->adpt_debug_counter_set(); - - if (count >= sizeof(num_buf)) - return 0; - memcpy(num_buf, buf, count); - num_buf[count] = '\0'; - - - return count; -} - -#ifdef HPPE -#ifdef IN_QOS -void ssdk_dts_port_scheduler_dump(a_uint32_t dev_id) -{ - a_uint32_t i; - ssdk_dt_portscheduler_cfg *portscheduler_cfg; - ssdk_dt_scheduler_cfg *scheduler_cfg; - a_uint8_t srcmsg[7][16]; - - scheduler_cfg = ssdk_bootup_shceduler_cfg_get(dev_id); - - printk("===============================port_scheduler_resource===========================\n"); - printk("portid ucastq mcastq 10sp 10cdrr 10edrr 11cdrr 11edrr\n"); - for (i = 0; i < SSDK_MAX_PORT_NUM; i++) - { - portscheduler_cfg = &scheduler_cfg->pool[i]; - snprintf(srcmsg[0], sizeof(srcmsg[0]), "<%d %d>", portscheduler_cfg->ucastq_start, - portscheduler_cfg->ucastq_end); - snprintf(srcmsg[1], sizeof(srcmsg[1]), "<%d %d>", portscheduler_cfg->mcastq_start, - portscheduler_cfg->mcastq_end); - snprintf(srcmsg[2], sizeof(srcmsg[2]), "<%d %d>", portscheduler_cfg->l0sp_start, - portscheduler_cfg->l0sp_end); - snprintf(srcmsg[3], sizeof(srcmsg[3]), "<%d %d>", portscheduler_cfg->l0cdrr_start, - portscheduler_cfg->l0cdrr_end); - snprintf(srcmsg[4], sizeof(srcmsg[4]), "<%d %d>", portscheduler_cfg->l0edrr_start, - portscheduler_cfg->l0edrr_end); - snprintf(srcmsg[5], sizeof(srcmsg[5]), "<%d %d>", portscheduler_cfg->l1cdrr_start, - portscheduler_cfg->l1cdrr_end); - snprintf(srcmsg[6], sizeof(srcmsg[6]), "<%d %d>", portscheduler_cfg->l1edrr_start, - portscheduler_cfg->l1edrr_end); - printk("%6d%11s%11s%9s%11s%11s%11s%11s\n", i, srcmsg[0], srcmsg[1], srcmsg[2], srcmsg[3], - srcmsg[4], srcmsg[5], srcmsg[6]); - } -} - -void ssdk_dts_l0scheduler_dump(a_uint32_t dev_id) -{ - a_uint32_t i; - ssdk_dt_l0scheduler_cfg *scheduler_cfg; - ssdk_dt_scheduler_cfg *cfg; - - cfg = ssdk_bootup_shceduler_cfg_get(dev_id); - printk("==========================l0scheduler_cfg===========================\n"); - printk("queue portid cpri cdrr_id epri edrr_id sp_id\n"); - for (i = 0; i < SSDK_L0SCHEDULER_CFG_MAX; i++) - { - scheduler_cfg = &cfg->l0cfg[i]; - if (scheduler_cfg->valid == 1) - printk("%5d%11d%9d%12d%9d%12d%10d\n", i, scheduler_cfg->port_id, - scheduler_cfg->cpri, scheduler_cfg->cdrr_id, scheduler_cfg->epri, - scheduler_cfg->edrr_id, scheduler_cfg->sp_id); - } -} - -void ssdk_dts_l1scheduler_dump(a_uint32_t dev_id) -{ - a_uint32_t i; - ssdk_dt_l1scheduler_cfg *scheduler_cfg; - ssdk_dt_scheduler_cfg *cfg; - - cfg = ssdk_bootup_shceduler_cfg_get(dev_id); - - printk("=====================l1scheduler_cfg=====================\n"); - printk("flow portid cpri cdrr_id epri edrr_id\n"); - for (i = 0; i < SSDK_L1SCHEDULER_CFG_MAX; i++) - { - scheduler_cfg = &cfg->l1cfg[i]; - if (scheduler_cfg->valid == 1) - printk("%4d%11d%9d%12d%9d%12d\n", i, scheduler_cfg->port_id, - scheduler_cfg->cpri, scheduler_cfg->cdrr_id, - scheduler_cfg->epri, scheduler_cfg->edrr_id); - } -} -#endif -#endif -static const a_int8_t *qca_phy_feature_str[QCA_PHY_FEATURE_MAX] = { - "PHY_CLAUSE45", - "PHY_COMBO", - "PHY_QGMAC", - "PHY_XGMAC", - "PHY_I2C", - "PHY_INIT", - "PHY_FORCE" -}; - -void ssdk_dts_phyinfo_dump(a_uint32_t dev_id) -{ - a_uint32_t i, j; - ssdk_port_phyinfo *port_phyinfo; - - printk("=====================port phyinfo========================\n"); - printk("portid phy_addr features\n"); - - for (i = 0; i <= SSDK_MAX_PORT_NUM; i++) { - port_phyinfo = ssdk_port_phyinfo_get(dev_id, i); - if (port_phyinfo) { - printk("%6d%13d%*s", port_phyinfo->port_id, - port_phyinfo->phy_addr, 5, ""); - for (j = 0; j < QCA_PHY_FEATURE_MAX; j++) { - if (port_phyinfo->phy_features & BIT(j) && BIT(j) != PHY_F_INIT) { - printk(KERN_CONT "%s ", qca_phy_feature_str[j]); - if (BIT(j) == PHY_F_FORCE) { - printk(KERN_CONT "(speed: %d, duplex: %s) ", - port_phyinfo->port_speed, - port_phyinfo->port_duplex > 0 ? - "full" : "half"); - } - } - } - printk(KERN_CONT "\n"); - } - } -} - -static ssize_t ssdk_dts_dump(struct device *dev, - struct device_attribute *attr, - char *buf) -{ - ssize_t count; - a_uint32_t dev_id, dev_num; - ssdk_reg_map_info map; - hsl_reg_mode mode; - - count = snprintf(buf, (ssize_t)PAGE_SIZE, "\n"); - - dev_num = ssdk_switch_device_num_get(); - for (dev_id = 0; dev_id < dev_num; dev_id ++) - { - ssdk_switch_reg_map_info_get(dev_id, &map); - mode = ssdk_switch_reg_access_mode_get(dev_id); - printk("=======================================================\n"); - printk("ess-switch\n"); - printk(" reg = <0x%x 0x%x>\n", map.base_addr, map.size); - if (mode == HSL_REG_LOCAL_BUS) - printk(" switch_access_mode = \n"); - else if (mode == HSL_REG_MDIO) - printk(" switch_access_mode = \n"); - else - printk(" switch_access_mode = <(null)>\n"); - printk(" switch_cpu_bmp = <0x%x>\n", ssdk_cpu_bmp_get(dev_id)); - printk(" switch_lan_bmp = <0x%x>\n", ssdk_lan_bmp_get(dev_id)); - printk(" switch_wan_bmp = <0x%x>\n", ssdk_wan_bmp_get(dev_id)); - printk(" switch_inner_bmp = <0x%x>\n", ssdk_inner_bmp_get(dev_id)); - printk(" switch_mac_mode = <0x%x>\n", ssdk_dt_global_get_mac_mode(dev_id, 0)); - printk(" switch_mac_mode1 = <0x%x>\n", ssdk_dt_global_get_mac_mode(dev_id, 1)); - printk(" switch_mac_mode2 = <0x%x>\n", ssdk_dt_global_get_mac_mode(dev_id, 2)); -#ifdef IN_BM - printk(" bm_tick_mode = <0x%x>\n", ssdk_bm_tick_mode_get(dev_id)); -#endif -#ifdef HPPE -#ifdef IN_QOS - printk(" tm_tick_mode = <0x%x>\n", ssdk_tm_tick_mode_get(dev_id)); -#endif -#endif -#ifdef DESS - printk("ess-psgmii\n"); - ssdk_psgmii_reg_map_info_get(dev_id, &map); - mode = ssdk_psgmii_reg_access_mode_get(dev_id); - printk(" reg = <0x%x 0x%x>\n", map.base_addr, map.size); - if (mode == HSL_REG_LOCAL_BUS) - printk(" psgmii_access_mode = \n"); - else if (mode == HSL_REG_MDIO) - printk(" psgmii_access_mode = \n"); - else - printk(" psgmii_access_mode = <(null)>\n"); -#endif -#ifdef IN_UNIPHY - printk("ess-uniphy\n"); - ssdk_uniphy_reg_map_info_get(dev_id, &map); - mode = ssdk_uniphy_reg_access_mode_get(dev_id); - printk(" reg = <0x%x 0x%x>\n", map.base_addr, map.size); - if (mode == HSL_REG_LOCAL_BUS) - printk(" uniphy_access_mode = \n"); - else if (mode == HSL_REG_MDIO) - printk(" uniphy_access_mode = \n"); - else - printk(" uniphy_access_mode = <(null)>\n"); -#endif -#ifdef HPPE -#ifdef IN_QOS - printk("\n"); - ssdk_dts_port_scheduler_dump(dev_id); - printk("\n"); - ssdk_dts_l0scheduler_dump(dev_id); - printk("\n"); - ssdk_dts_l1scheduler_dump(dev_id); -#endif -#endif - printk("\n"); - ssdk_dts_phyinfo_dump(dev_id); - } - - return count; -} - -static a_uint16_t phy_reg_val = 0; -static ssize_t ssdk_phy_write_reg_set(struct device *dev, - struct device_attribute *attr, - const char *buf, size_t count) -{ - char phy_buf[32]; - char *this_opt; - char *options = phy_buf; - unsigned int phy_addr, reg_addr, reg_value; - - if (count >= sizeof(phy_buf)) - return 0; - memcpy(phy_buf, buf, count); - phy_buf[count] = '\0'; - - this_opt = strsep(&options, " "); - if (!this_opt) - goto fail; - - kstrtouint(this_opt, 0, &phy_addr); - if ((options - phy_buf) >= (count - 1)) - goto fail; - - this_opt = strsep(&options, " "); - if (!this_opt) - goto fail; - - kstrtouint(this_opt, 0, ®_addr); - if ((options - phy_buf) >= (count - 1)) - goto fail; - - this_opt = strsep(&options, " "); - if (!this_opt) - goto fail; - - kstrtouint(this_opt, 0, ®_value); - - qca_ar8327_phy_write(0, phy_addr, reg_addr, reg_value); - - return count; - -fail: - printk("Format: phy_addr reg_addr reg_value\n"); - return -EINVAL; -} - -static ssize_t ssdk_phy_read_reg_get(struct device *dev, - struct device_attribute *attr, - char *buf) -{ - ssize_t count; - - count = snprintf(buf, (ssize_t)PAGE_SIZE, "reg_val = 0x%x\n", phy_reg_val); - return count; -} - -static ssize_t ssdk_phy_read_reg_set(struct device *dev, - struct device_attribute *attr, - const char *buf, size_t count) -{ - char phy_buf[32]; - char *this_opt; - char *options = phy_buf; - unsigned int phy_addr, reg_addr; - - if (count >= sizeof(phy_buf)) - return 0; - memcpy(phy_buf, buf, count); - phy_buf[count] = '\0'; - - this_opt = strsep(&options, " "); - if (!this_opt) - goto fail; - - kstrtouint(this_opt, 0, &phy_addr); - if ((options - phy_buf) >= (count - 1)) - goto fail; - - this_opt = strsep(&options, " "); - if (!this_opt) - goto fail; - - kstrtouint(this_opt, 0, ®_addr); - - qca_ar8327_phy_read(0, phy_addr, reg_addr, &phy_reg_val); - - return count; - -fail: - printk("Format: phy_addr reg_addr\n"); - return -EINVAL; -} - -#ifdef IN_LINUX_STD_PTP -static ssize_t ssdk_ptp_counter_get(struct device *dev, - struct device_attribute *attr, - char *buf) -{ - ssize_t count; - - count = snprintf(buf, (ssize_t)PAGE_SIZE, "\n"); - qca808x_ptp_stat_get(); - return count; -} - -static ssize_t ssdk_ptp_counter_set(struct device *dev, - struct device_attribute *attr, - const char *buf, size_t count) -{ - qca808x_ptp_stat_set(); - return count; -} -#endif - -static const struct device_attribute ssdk_dev_id_attr = - __ATTR(dev_id, 0660, ssdk_dev_id_get, ssdk_dev_id_set); -static const struct device_attribute ssdk_log_level_attr = - __ATTR(log_level, 0660, ssdk_log_level_get, ssdk_log_level_set); -static const struct device_attribute ssdk_packet_counter_attr = - __ATTR(packet_counter, 0660, ssdk_packet_counter_get, ssdk_packet_counter_set); -static const struct device_attribute ssdk_byte_counter_attr = - __ATTR(byte_counter, 0660, ssdk_byte_counter_get, ssdk_byte_counter_set); -static const struct device_attribute ssdk_dts_dump_attr = - __ATTR(dts_dump, 0660, ssdk_dts_dump, NULL); -static const struct device_attribute ssdk_phy_write_reg_attr = - __ATTR(phy_write_reg, 0660, NULL, ssdk_phy_write_reg_set); -static const struct device_attribute ssdk_phy_read_reg_attr = - __ATTR(phy_read_reg, 0660, ssdk_phy_read_reg_get, ssdk_phy_read_reg_set); -#ifdef IN_LINUX_STD_PTP -static const struct device_attribute ssdk_ptp_counter_attr = - __ATTR(ptp_packet_counter, 0660, ssdk_ptp_counter_get, ssdk_ptp_counter_set); -#endif -struct kobject *ssdk_sys = NULL; - -int ssdk_sysfs_init (void) -{ - int ret = 0; - - /* create /sys/ssdk/ dir */ - ssdk_sys = kobject_create_and_add("ssdk", NULL); - if (!ssdk_sys) { - printk("Failed to register SSDK sysfs\n"); - return ret; - } - - /* create /sys/ssdk/dev_id file */ - ret = sysfs_create_file(ssdk_sys, &ssdk_dev_id_attr.attr); - if (ret) { - printk("Failed to register SSDK dev id SysFS file\n"); - goto CLEANUP_1; - } - - /* create /sys/ssdk/log_level file */ - ret = sysfs_create_file(ssdk_sys, &ssdk_log_level_attr.attr); - if (ret) { - printk("Failed to register SSDK log level SysFS file\n"); - goto CLEANUP_2; - } - - /* create /sys/ssdk/packet_counter file */ - ret = sysfs_create_file(ssdk_sys, &ssdk_packet_counter_attr.attr); - if (ret) { - printk("Failed to register SSDK switch counter SysFS file\n"); - goto CLEANUP_3; - } - - /* create /sys/ssdk/byte_counter file */ - ret = sysfs_create_file(ssdk_sys, &ssdk_byte_counter_attr.attr); - if (ret) { - printk("Failed to register SSDK switch counter bytes SysFS file\n"); - goto CLEANUP_4; - } - - /* create /sys/ssdk/dts_dump file */ - ret = sysfs_create_file(ssdk_sys, &ssdk_dts_dump_attr.attr); - if (ret) { - printk("Failed to register SSDK switch show dts SysFS file\n"); - goto CLEANUP_5; - } - - /* create /sys/ssdk/phy_write_reg file */ - ret = sysfs_create_file(ssdk_sys, &ssdk_phy_write_reg_attr.attr); - if (ret) { - printk("Failed to register SSDK phy write reg file\n"); - goto CLEANUP_6; - } - - /* create /sys/ssdk/phy_read_reg file */ - ret = sysfs_create_file(ssdk_sys, &ssdk_phy_read_reg_attr.attr); - if (ret) { - printk("Failed to register SSDK phy read reg file\n"); - goto CLEANUP_7; - } - -#ifdef IN_LINUX_STD_PTP - /* create /sys/ssdk/ptp_packet_counter file */ - ret = sysfs_create_file(ssdk_sys, &ssdk_ptp_counter_attr.attr); - if (ret) { - printk("Failed to register SSDK ptp counter file\n"); - goto CLEANUP_8; - } -#endif - - return 0; - -#ifdef IN_LINUX_STD_PTP -CLEANUP_8: - sysfs_remove_file(ssdk_sys, &ssdk_phy_read_reg_attr.attr); -#endif -CLEANUP_7: - sysfs_remove_file(ssdk_sys, &ssdk_phy_write_reg_attr.attr); -CLEANUP_6: - sysfs_remove_file(ssdk_sys, &ssdk_dts_dump_attr.attr); -CLEANUP_5: - sysfs_remove_file(ssdk_sys, &ssdk_byte_counter_attr.attr); -CLEANUP_4: - sysfs_remove_file(ssdk_sys, &ssdk_packet_counter_attr.attr); -CLEANUP_3: - sysfs_remove_file(ssdk_sys, &ssdk_log_level_attr.attr); -CLEANUP_2: - sysfs_remove_file(ssdk_sys, &ssdk_dev_id_attr.attr); -CLEANUP_1: - kobject_put(ssdk_sys); - - return ret; -} - -void ssdk_sysfs_exit (void) -{ -#ifdef IN_LINUX_STD_PTP - sysfs_remove_file(ssdk_sys, &ssdk_ptp_counter_attr.attr); -#endif - sysfs_remove_file(ssdk_sys, &ssdk_phy_read_reg_attr.attr); - sysfs_remove_file(ssdk_sys, &ssdk_phy_write_reg_attr.attr); - sysfs_remove_file(ssdk_sys, &ssdk_dts_dump_attr.attr); - sysfs_remove_file(ssdk_sys, &ssdk_byte_counter_attr.attr); - sysfs_remove_file(ssdk_sys, &ssdk_packet_counter_attr.attr); - sysfs_remove_file(ssdk_sys, &ssdk_log_level_attr.attr); - sysfs_remove_file(ssdk_sys, &ssdk_dev_id_attr.attr); - kobject_put(ssdk_sys); -} - -/*qca808x_start*/ -int -ssdk_plat_init(ssdk_init_cfg *cfg, a_uint32_t dev_id) -{ -/*qca808x_end*/ - hsl_reg_mode reg_mode; - ssdk_reg_map_info map; - struct clk * ess_clk; - struct clk * cmn_clk; - #ifdef BOARD_AR71XX - int rv = 0; - #endif -/*qca808x_start*/ - printk("ssdk_plat_init start\n"); -/*qca808x_end*/ - mutex_init(&switch_mdio_lock); - - if(!ssdk_is_emulation(dev_id)){ -/*qca808x_start*/ - if(miibus_get(dev_id)) - return -ENODEV; -/*qca808x_end*/ - } -#ifdef IN_UNIPHY - reg_mode = ssdk_uniphy_reg_access_mode_get(dev_id); - if(reg_mode == HSL_REG_LOCAL_BUS) { - ssdk_uniphy_reg_map_info_get(dev_id, &map); - qca_phy_priv_global[dev_id]->uniphy_hw_addr = ioremap_nocache(map.base_addr, - map.size); - if (!qca_phy_priv_global[dev_id]->uniphy_hw_addr) { - SSDK_ERROR("%s ioremap fail.", __func__); - cfg->reg_func.uniphy_reg_set = NULL; - cfg->reg_func.uniphy_reg_get = NULL; - return -1; - } - cfg->reg_func.uniphy_reg_set = qca_uniphy_reg_write; - cfg->reg_func.uniphy_reg_get = qca_uniphy_reg_read; - } -#endif - reg_mode = ssdk_switch_reg_access_mode_get(dev_id); - if(reg_mode == HSL_REG_LOCAL_BUS) { - ssdk_switch_reg_map_info_get(dev_id, &map); - qca_phy_priv_global[dev_id]->hw_addr = ioremap_nocache(map.base_addr, - map.size); - if (!qca_phy_priv_global[dev_id]->hw_addr) { - SSDK_ERROR("%s ioremap fail.", __func__); - return -1; - } - ess_clk = ssdk_dts_essclk_get(dev_id); - cmn_clk = ssdk_dts_cmnclk_get(dev_id); - if (!IS_ERR(ess_clk)) { - /* Enable ess clock here */ - SSDK_INFO("Enable ess clk\n"); - clk_prepare_enable(ess_clk); - } else if (!IS_ERR(cmn_clk)) { -#if defined(HPPE) || defined(MP) - ssdk_gcc_clock_init(); -#endif - return 0; - } - - cfg->reg_mode = HSL_HEADER; - } -#ifdef DESS - reg_mode = ssdk_psgmii_reg_access_mode_get(dev_id); - if(reg_mode == HSL_REG_LOCAL_BUS) { - ssdk_psgmii_reg_map_info_get(dev_id, &map); - if (!request_mem_region(map.base_addr, - map.size, "psgmii_mem")) { - SSDK_ERROR("%s Unable to request psgmii resource.", __func__); - return -1; - } - - qca_phy_priv_global[dev_id]->psgmii_hw_addr = ioremap_nocache(map.base_addr, - map.size); - if (!qca_phy_priv_global[dev_id]->psgmii_hw_addr) { - SSDK_ERROR("%s ioremap fail.", __func__); - cfg->reg_func.psgmii_reg_set = NULL; - cfg->reg_func.psgmii_reg_get = NULL; - return -1; - } - - cfg->reg_func.psgmii_reg_set = qca_psgmii_reg_write; - cfg->reg_func.psgmii_reg_get = qca_psgmii_reg_read; - } -#endif - reg_mode = ssdk_switch_reg_access_mode_get(dev_id); - if(reg_mode == HSL_REG_MDIO) { - cfg->reg_mode = HSL_MDIO; - } else - return 0; -/*qca808x_start*/ - - return 0; -} - -void -ssdk_plat_exit(a_uint32_t dev_id) -{ -/*qca808x_end*/ - hsl_reg_mode reg_mode; -#ifdef DESS - ssdk_reg_map_info map; -#endif -/*qca808x_start*/ - printk("ssdk_plat_exit\n"); -/*qca808x_end*/ - reg_mode = ssdk_switch_reg_access_mode_get(dev_id); - if (reg_mode == HSL_REG_LOCAL_BUS) { - iounmap(qca_phy_priv_global[dev_id]->hw_addr); - } -#ifdef DESS - reg_mode = ssdk_psgmii_reg_access_mode_get(dev_id); - if (reg_mode == HSL_REG_LOCAL_BUS) { - ssdk_psgmii_reg_map_info_get(dev_id, &map); - iounmap(qca_phy_priv_global[dev_id]->psgmii_hw_addr); - release_mem_region(map.base_addr, - map.size); - } -#endif -#ifdef IN_UNIPHY - reg_mode = ssdk_uniphy_reg_access_mode_get(dev_id); - if (reg_mode == HSL_REG_LOCAL_BUS) { - iounmap(qca_phy_priv_global[dev_id]->uniphy_hw_addr); - } -#endif -/*qca808x_start*/ -} -/*qca808x_end*/ - diff --git a/feeds/ipq807x/qca-ssdk/src/src/init/ssdk_scomphy.c b/feeds/ipq807x/qca-ssdk/src/src/init/ssdk_scomphy.c deleted file mode 100644 index 15611445c..000000000 --- a/feeds/ipq807x/qca-ssdk/src/src/init/ssdk_scomphy.c +++ /dev/null @@ -1,40 +0,0 @@ -/* - * Copyright (c) 2019-2020, The Linux Foundation. All rights reserved. - * - * Permission to use, copy, modify, and/or distribute this software for any - * purpose with or without fee is hereby granted, provided that the above - * copyright notice and this permission notice appear in all copies. - * - * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES - * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR - * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES - * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN - * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF - * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. - */ - -#include "ssdk_init.h" - -#ifdef MP -#include "ssdk_mp.h" -#include "hsl_phy.h" -#endif - -sw_error_t qca_scomphy_hw_init(ssdk_init_cfg *cfg, a_uint32_t dev_id) -{ - sw_error_t rv = SW_OK; - - switch (cfg->phy_id) { -#ifdef MP - case MP_GEPHY: - rv = qca_mp_hw_init(dev_id, cfg); - SW_RTN_ON_ERROR(rv); - break; -#endif - default: - break; - } - return rv; -} - diff --git a/feeds/ipq807x/qca-ssdk/src/src/init/ssdk_uci.c b/feeds/ipq807x/qca-ssdk/src/src/init/ssdk_uci.c deleted file mode 100755 index aebea6439..000000000 --- a/feeds/ipq807x/qca-ssdk/src/src/init/ssdk_uci.c +++ /dev/null @@ -1,196 +0,0 @@ -/* - * Copyright (c) 2014-2015, The Linux Foundation. All rights reserved. - * Permission to use, copy, modify, and/or distribute this software for - * any purpose with or without fee is hereby granted, provided that the - * above copyright notice and this permission notice appear in all copies. - * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES - * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR - * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES - * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN - * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT - * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. - */ - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#if defined(CONFIG_OF) && (LINUX_VERSION_CODE >= KERNEL_VERSION(3,14,0)) -#include - #include -#else -#include -#include -#endif -#include "sw.h" -#include "ssdk_init.h" -#include "ssdk_plat.h" - -#ifdef BOARD_AR71XX - -struct switch_dev *old_sw_dev = NULL; -struct net_device *sw_attach_dev = NULL; -struct qca_phy_priv qca_priv; - -extern int qca_phy_id_chip(struct qca_phy_priv *priv); -extern const struct switch_dev_ops qca_ar8327_sw_ops; -extern int qca_phy_mib_work_start(struct qca_phy_priv *priv); -extern void qca_phy_mib_work_stop(struct qca_phy_priv *priv); - -int -ssdk_uci_sw_set_vlan(const struct switch_attr *attr, - struct switch_val *val) -{ - if(old_sw_dev) { - struct switch_dev_ops *ops = old_sw_dev->ops; - if(ops) { - struct switch_attrlist attr_global = ops->attr_global; - int i = 0; - struct switch_attr *g_attr = attr_global.attr; - for(i = 0; i < attr_global.n_attr; i++) { - if(!strcmp(g_attr[i].name, "enable_vlan") && - g_attr[i].set) { - g_attr[i].set(old_sw_dev, attr, val); - break; - } - } - } - } - return 0; -} - -int -ssdk_uci_sw_set_vid(const struct switch_attr *attr, - struct switch_val *val) -{ - if(old_sw_dev) { - struct switch_dev_ops *ops = old_sw_dev->ops; - if(ops) { - struct switch_attrlist attr_vlan = ops->attr_vlan; - int i = 0; - struct switch_attr *v_attr = attr_vlan.attr; - for(i = 0; i < attr_vlan.n_attr; i++) { - if(!strcmp(v_attr[i].name, "vid") && - v_attr[i].set) { - v_attr[i].set(old_sw_dev, attr, val); - break; - } - } - } - } - return 0; -} - - -int -ssdk_uci_sw_set_pvid(int port, int vlan) -{ - if(old_sw_dev) { - struct switch_dev_ops *ops = old_sw_dev->ops; - if(ops && ops->set_port_pvid) { - ops->set_port_pvid(old_sw_dev, port, vlan); - } - } - return 0; -} - -int -ssdk_uci_sw_set_ports(struct switch_val *val) -{ - if(old_sw_dev) { - struct switch_dev_ops *ops = old_sw_dev->ops; - if(ops && ops->set_vlan_ports) { - ops->set_vlan_ports(old_sw_dev, val); - } - } - return 0; -} - - -int ssdk_uci_takeover_init() -{ - struct qca_phy_priv *priv = &qca_priv; - struct switch_dev tmp_dev; - struct switch_dev *sdev = NULL; - struct net_device *tmp_net = NULL; - - /*only for s27*/ - if((qca_ar8216_mii_read(0, 0)&0xff00)>>8 != 0x02) - return 0; - - memset(&qca_priv, 0, sizeof(qca_priv)); - mutex_init(&priv->reg_mutex); - qca_phy_id_chip(priv); - priv->mii_read = qca_ar8216_mii_read; - priv->mii_write = qca_ar8216_mii_write; - priv->phy_write = qca_ar8327_phy_write; - priv->phy_dbg_write = qca_ar8327_phy_dbg_write; - priv->phy_dbg_read = qca_ar8327_phy_dbg_read; - priv->phy_mmd_write = qca_ar8327_mmd_write; - - priv->sw_dev.ops = &qca_ar8327_sw_ops; - priv->sw_dev.name = "QCA AR8327 AR8337"; - priv->sw_dev.vlans = AR8327_MAX_VLANS; - priv->sw_dev.ports = AR8327_NUM_PORTS; - memset(&tmp_dev, 0, sizeof(tmp_dev)); - tmp_dev.ops = &qca_ar8327_sw_ops; - tmp_dev.name = "ssdk probe"; - SSDK_DEBUG("SSDK uci takeover!\n"); - tmp_net = dev_get_by_name(&init_net, "eth1"); - if(!tmp_net) { - tmp_net = dev_get_by_name(&init_net, "eth0"); - if(!tmp_net) - return 0; - } - SSDK_DEBUG("using %s\n", tmp_net->name); - if(register_switch(&tmp_dev, tmp_net) < 0) { - SSDK_ERROR("register temp switch fail!\n"); - return 0; - } - list_for_each_entry(sdev, &tmp_dev.dev_list, dev_list) { - SSDK_DEBUG("Found %s\n", sdev->name); - if(!strcmp(sdev->name, "AR7240/AR9330 built-in switch") || - !strcmp(sdev->name, "AR934X built-in switch")) { - int err; - /*found*/ - sw_attach_dev = sdev->netdev; - old_sw_dev = sdev; - /*unregister openwrt switch device*/ - unregister_switch(sdev); - /*register ours*/ - SSDK_DEBUG("ssdk register switch, old name %s\n", sdev->name); - if(err = register_switch(&priv->sw_dev, sw_attach_dev) < 0) { - SSDK_ERROR("ssdk register switch fail %d!\n", err); - } - break; - } - } - /*anyway should unregister the temp switch dev*/ - unregister_switch(&tmp_dev); - if(sw_attach_dev) { - qca_phy_mib_work_start(&qca_priv); - } - return 0; -} - -void ssdk_uci_takeover_exit() -{ - if(sw_attach_dev && old_sw_dev) { - unregister_switch(&qca_priv.sw_dev); - register_switch(old_sw_dev, sw_attach_dev); - qca_phy_mib_work_stop(&qca_priv); - } -} - -#endif - - diff --git a/feeds/ipq807x/qca-ssdk/src/src/ref/Makefile b/feeds/ipq807x/qca-ssdk/src/src/ref/Makefile deleted file mode 100755 index fc2bca7de..000000000 --- a/feeds/ipq807x/qca-ssdk/src/src/ref/Makefile +++ /dev/null @@ -1,45 +0,0 @@ -LOC_DIR=src/ref -LIB=REF - -include $(PRJ_PATH)/make/config.mk - -SRC_LIST_TMP=ref_uci.c -SRC_SW_LIST=ref_misc.c ref_uci.c - -ifeq (TRUE, $(IN_FDB)) - SRC_LIST_TMP += ref_fdb.c -endif - -ifeq (TRUE, $(IN_MIB)) - SRC_LIST_TMP += ref_mib.c -endif - -ifeq (TRUE, $(IN_MISC)) - SRC_LIST_TMP += ref_misc.c -endif - -ifeq (TRUE, $(IN_PORTCONTROL)) - SRC_LIST_TMP += ref_port_ctrl.c -endif - -ifeq (TRUE, $(IN_VLAN)) - SRC_LIST_TMP += ref_vlan.c -endif - -ifeq (TRUE, $(IN_VSI)) - SRC_LIST_TMP += ref_vsi.c -endif - -ifeq (FALSE, $(SWCONFIG)) - SRC_LIST=$(filter-out $(SRC_SW_LIST), $(SRC_LIST_TMP)) -else - SRC_LIST=$(SRC_LIST_TMP) -endif - - -include $(PRJ_PATH)/make/components.mk -include $(PRJ_PATH)/make/defs.mk -include $(PRJ_PATH)/make/target.mk - -all: dep obj - diff --git a/feeds/ipq807x/qca-ssdk/src/src/ref/ref_fdb.c b/feeds/ipq807x/qca-ssdk/src/src/ref/ref_fdb.c deleted file mode 100644 index 7c1a5fcc9..000000000 --- a/feeds/ipq807x/qca-ssdk/src/src/ref/ref_fdb.c +++ /dev/null @@ -1,177 +0,0 @@ -/* - * Copyright (c) 2012, 2017, The Linux Foundation. All rights reserved. - * Permission to use, copy, modify, and/or distribute this software for - * any purpose with or without fee is hereby granted, provided that the - * above copyright notice and this permission notice appear in all copies. - * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES - * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR - * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES - * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN - * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT - * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. - */ - -#include "sw.h" -#include "ssdk_init.h" -#include "fal_init.h" -#include "fal_misc.h" -#include "fal_mib.h" -#include "fal_port_ctrl.h" -#include "fal_portvlan.h" -#include "fal_fdb.h" -#include "fal_stp.h" -#include "fal_igmp.h" -#include "fal_qos.h" -#include "hsl.h" -#include "hsl_dev.h" -#include "ssdk_init.h" -#include -#include -#include -#include -#include -#include -#include -//#include -#include -#if (LINUX_VERSION_CODE < KERNEL_VERSION(3,14,0)) -#include -#endif -#include -#include -#include -#include "ssdk_plat.h" -#include "ref_vlan.h" -#include "ref_fdb.h" - - -#if defined(IN_SWCONFIG) -int -qca_ar8327_sw_atu_flush(struct switch_dev *dev, - const struct switch_attr *attr, - struct switch_val *val) -{ - struct qca_phy_priv *priv = qca_phy_priv_get(dev); - /* 0: dynamic 1:dynamic, static */ - fal_fdb_entry_flush(priv->device_id, 1); - - return 0; -} - -int -qca_ar8327_sw_atu_dump(struct switch_dev *dev, - const struct switch_attr *attr, - struct switch_val *val) -{ - struct qca_phy_priv *priv = qca_phy_priv_get(dev); - a_uint32_t rv; - char *buf; - a_uint32_t len = 0; - a_uint32_t i = 0; - fal_fdb_op_t option; - fal_fdb_entry_t entry; - fal_pbmp_t port_bmp = 0; - a_uint32_t port_type = 0; - - buf = (char*) priv->buf; - memset(buf, 0, 2048); - memset(&option, 0, sizeof(fal_fdb_op_t)); - memset(&entry, 0, sizeof(fal_fdb_entry_t)); - - if (priv->version == QCA_VER_AR8227) - rv = fal_fdb_entry_getfirst(priv->device_id, &entry); - else - rv = fal_fdb_entry_extend_getfirst(priv->device_id, &option, &entry); - while (!rv) - { - len += snprintf(buf+len, 2048-len, "MAC: %02x:%02x:%02x:%02x:%02x:%02x ", - entry.addr.uc[0],entry.addr.uc[1],entry.addr.uc[2],entry.addr.uc[3], - entry.addr.uc[4],entry.addr.uc[5]); - if(entry.portmap_en == A_TRUE) { - port_bmp = entry.port.map; - len += snprintf(buf+len, 2048-len, - "PORTMAP: 0x%02x VID: 0x%x STATUS: 0x%x\n", - port_bmp, entry.fid, entry.static_en); - } else { - port_type = FAL_PORT_ID_TYPE(entry.port.id); - if(port_type == FAL_PORT_TYPE_PPORT) { - port_bmp = 1 << entry.port.id; - len += snprintf(buf+len, 2048-len, - "PORTMAP: 0x%02x VID: 0x%x STATUS: 0x%x\n", - port_bmp, entry.fid, entry.static_en); - } else { - len += snprintf(buf+len, 2048-len, - "DEST_INFO: 0x%02x VID: 0x%x STATUS: 0x%x\n", - entry.port.id, entry.fid, entry.static_en); - } - } - - if (2048-len < 74){ -// snprintf(buf+len, 2048-len, "Buffer not enough!\n"); - break; - } - if (priv->version == QCA_VER_AR8227) - rv = fal_fdb_entry_getnext_byindex(priv->device_id, &i, &entry); - else - rv = fal_fdb_entry_extend_getnext(priv->device_id, &option, &entry); - } - - val->value.s = (char*)(priv->buf); - val->len = len; - - return 0; -} -#endif - -#define MAX_PORT 6 -/* - * example: - * vid=4; - * char addr[6] = {0x00, 0x01, 0x02, 0x88, 0x00, 0xaa} - * - * return value: - * success: 0 - 5 - * fail: 0xffffffff - */ -fal_port_t -ref_fdb_get_port_by_mac(unsigned int vid, const char * addr) -{ - fal_fdb_entry_t entry; - unsigned char i; - sw_error_t rv; - a_uint32_t dev_id = 0; - - memset(&entry, 0, sizeof(entry)); - SSDK_DEBUG("the fdb entry with MAC:%x-%x-%x-%x-%x-%x, fid:%d will be searched\n", - addr[0], addr[1], addr[2], addr[3], addr[4], addr[5], vid); - entry.fid = vid; - for (i = 0; i < 6; i++) - entry.addr.uc[i] = addr[i]; - for(dev_id = 0; dev_id < SW_MAX_NR_DEV; dev_id++) - { - rv = fal_fdb_find(dev_id, &entry); - if (rv == SW_OK) - { - SSDK_DEBUG("device %d have the entry\n", dev_id); - break; - } - } - if(rv != SW_OK) - { - SSDK_DEBUG("the entry cannot be found\n"); - return 0xffffffff; - } - - for (i = 0; i < MAX_PORT; i++) - { - if (entry.port.id & (0x1 << i)) - { - return i; - } - } - return 0xffffffff; -} - -EXPORT_SYMBOL(ref_fdb_get_port_by_mac); - diff --git a/feeds/ipq807x/qca-ssdk/src/src/ref/ref_mib.c b/feeds/ipq807x/qca-ssdk/src/src/ref/ref_mib.c deleted file mode 100644 index add4e2e28..000000000 --- a/feeds/ipq807x/qca-ssdk/src/src/ref/ref_mib.c +++ /dev/null @@ -1,520 +0,0 @@ -/* - * Copyright (c) 2012, 2017, The Linux Foundation. All rights reserved. - * Permission to use, copy, modify, and/or distribute this software for - * any purpose with or without fee is hereby granted, provided that the - * above copyright notice and this permission notice appear in all copies. - * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES - * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR - * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES - * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN - * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT - * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. - */ - -#include "sw.h" -#include "ssdk_init.h" -#include "fal_init.h" -#include "fal_misc.h" -#include "fal_mib.h" -#include "fal_port_ctrl.h" -#include "fal_portvlan.h" -#include "fal_fdb.h" -#include "fal_stp.h" -#include "fal_igmp.h" -#include "fal_qos.h" -#include "hsl.h" -#include "hsl_dev.h" -#include "ssdk_init.h" -#include -#include -#include -#include -#include -#include -#include -//#include -#include -#if (LINUX_VERSION_CODE < KERNEL_VERSION(3,14,0)) -#include -#endif -#include -#include -#include -#include "ssdk_plat.h" -#include "ref_vlan.h" - -#if defined(IN_SWCONFIG) -int -_qca_ar8327_sw_capture_port_counter(struct switch_dev *dev, int port) -{ - fal_mib_info_t mib_Info; - struct qca_phy_priv *priv = qca_phy_priv_get(dev); - - memset(&mib_Info, 0, sizeof(mib_Info)); - fal_get_mib_info(priv->device_id, port, &mib_Info); - - return 0; -} - -int -qca_ar8327_sw_set_reset_mibs(struct switch_dev *dev, - const struct switch_attr *attr, - struct switch_val *val) -{ - int i = 0; - int len = 0; - struct qca_phy_priv *priv = qca_phy_priv_get(dev); - fal_mib_info_t mib_Info; - len = dev->ports * QCA_MIB_ITEM_NUMBER * - sizeof(*priv->mib_counters); - - mutex_lock(&priv->mib_lock); - memset(priv->mib_counters, '\0', len); - for (i = 0; i < dev->ports; i++) - { - fal_get_mib_info(priv->device_id, i, &mib_Info); - fal_mib_port_flush_counters(priv->device_id, i); - } - mutex_unlock(&priv->mib_lock); - - return 0; -} - -int -qca_ar8327_sw_set_port_reset_mib(struct switch_dev *dev, - const struct switch_attr *attr, - struct switch_val *val) -{ - int len = 0; - struct qca_phy_priv *priv = qca_phy_priv_get(dev); - fal_mib_info_t mib_Info; - len = QCA_MIB_ITEM_NUMBER * sizeof(*priv->mib_counters); - - mutex_lock(&priv->mib_lock); - - memset(priv->mib_counters + (val->port_vlan * QCA_MIB_ITEM_NUMBER), '\0', len); - - fal_get_mib_info(priv->device_id, val->port_vlan, &mib_Info); - fal_mib_port_flush_counters(priv->device_id, val->port_vlan); - mutex_unlock(&priv->mib_lock); - - return 0; -} - -#ifdef HPPE -static int qca_ar8327_sw_print_xgport_mib(struct switch_dev *dev, - const struct switch_attr *attr, struct switch_val *val) -{ - int port = 0; - int len = 0; - fal_xgmib_info_t xgmib_info; - - struct qca_phy_priv *priv = qca_phy_priv_get(dev); - char *buf = (char *)(priv->buf); - - port = val->port_vlan; - if (port >= dev->ports) - return -EINVAL; - - fal_get_xgmib_info(priv->device_id, port, &xgmib_info); - - mutex_lock(&priv->mib_lock); - - len += snprintf(buf + len, sizeof(priv->buf) - len, - "XG Port %d MIB counters\n", - port); - - len += snprintf(buf + len, sizeof(priv->buf) - len, - "%-18s: %llu\n", "RxFrame", xgmib_info.RxFrame); - - len += snprintf(buf + len, sizeof(priv->buf) - len, - "%-18s: %llu\n", "RxByte", xgmib_info.RxByte); - - len += snprintf(buf + len, sizeof(priv->buf) - len, - "%-18s: %llu\n", "RxByteGood", xgmib_info.RxByteGood); - - len += snprintf(buf + len, sizeof(priv->buf) - len, - "%-18s: %llu\n", "RxBroadGood", xgmib_info.RxBroadGood); - - len += snprintf(buf + len, sizeof(priv->buf) - len, - "%-18s: %llu\n", "RxMultiGood", xgmib_info.RxMultiGood); - - len += snprintf(buf + len, sizeof(priv->buf) - len, - "%-18s: %llu\n", "RxFcsErr", xgmib_info.RxFcsErr); - - len += snprintf(buf + len, sizeof(priv->buf) - len, - "%-18s: %llu\n", "RxRuntErr", xgmib_info.RxRuntErr ); - - len += snprintf(buf + len, sizeof(priv->buf) - len, - "%-18s: %llu\n", "RxJabberError", xgmib_info.RxJabberError); - - len += snprintf(buf + len, sizeof(priv->buf) - len, - "%-18s: %llu\n", "RxUndersizeGood", xgmib_info.RxUndersizeGood); - - len += snprintf(buf + len, sizeof(priv->buf) - len, - "%-18s: %llu\n", "RxOversizeGood", xgmib_info.RxOversizeGood); - - len += snprintf(buf + len, sizeof(priv->buf) - len, - "%-18s: %llu\n", "Rx64Byte", xgmib_info.Rx64Byte); - - len += snprintf(buf + len, sizeof(priv->buf) - len, - "%-18s: %llu\n", "Rx128Byte", xgmib_info.Rx128Byte); - - len += snprintf(buf + len, sizeof(priv->buf) - len, - "%-18s: %llu\n", "Rx256Byte", xgmib_info.Rx256Byte); - - len += snprintf(buf + len, sizeof(priv->buf) - len, - "%-18s: %llu\n", "Rx512Byte", xgmib_info.Rx512Byte); - - len += snprintf(buf + len, sizeof(priv->buf) - len, - "%-18s: %llu\n", "Rx1024Byte", xgmib_info.Rx1024Byte); - - len += snprintf(buf + len, sizeof(priv->buf) - len, - "%-18s: %llu\n", "RxMaxByte", xgmib_info.RxMaxByte); - - len += snprintf(buf + len, sizeof(priv->buf) - len, - "%-18s: %llu\n", "RxUnicastGood", xgmib_info.RxUnicastGood); - - len += snprintf(buf + len, sizeof(priv->buf) - len, - "%-18s: %llu\n", "RxLengthError", xgmib_info.RxLengthError); - - len += snprintf(buf + len, sizeof(priv->buf) - len, - "%-18s: %llu\n", "RxOutOfRangeError", xgmib_info.RxOutOfRangeError); - - len += snprintf(buf + len, sizeof(priv->buf) - len, - "%-18s: %llu\n", "RxPause", xgmib_info.RxPause); - - len += snprintf(buf + len, sizeof(priv->buf) - len, - "%-18s: %llu\n", "RxOverFlow", xgmib_info.RxOverFlow); - - len += snprintf(buf + len, sizeof(priv->buf) - len, - "%-18s: %llu\n", "RxVLANFrameGoodBad", xgmib_info.RxVLANFrameGoodBad); - - len += snprintf(buf + len, sizeof(priv->buf) - len, - "%-18s: %llu\n", "RxWatchDogError", xgmib_info.RxWatchDogError); - - len += snprintf(buf + len, sizeof(priv->buf) - len, - "%-18s: %llu\n", "RxLPIUsec", xgmib_info.RxLPIUsec); - - len += snprintf(buf + len, sizeof(priv->buf) - len, - "%-18s: %llu\n", "RxLPITran", xgmib_info.RxLPITran); - - len += snprintf(buf + len, sizeof(priv->buf) - len, - "%-18s: %llu\n", "RxDropFrameGoodBad", xgmib_info.RxDropFrameGoodBad); - - len += snprintf(buf + len, sizeof(priv->buf) - len, - "%-18s: %llu\n", "RxDropByteGoodBad", xgmib_info.RxDropByteGoodBad); - - len += snprintf(buf + len, sizeof(priv->buf) - len, - "%-18s: %llu\n", "TxByte", xgmib_info.TxByte); - - len += snprintf(buf + len, sizeof(priv->buf) - len, - "%-18s: %llu\n", "TxFrame", xgmib_info.TxFrame); - - len += snprintf(buf + len, sizeof(priv->buf) - len, - "%-18s: %llu\n", "TxBroadGood", xgmib_info.TxBroadGood); - - len += snprintf(buf + len, sizeof(priv->buf) - len, - "%-18s: %llu\n", "TxMultiGood", xgmib_info.TxMultiGood); - - len += snprintf(buf + len, sizeof(priv->buf) - len, - "%-18s: %llu\n", "Tx64Byte", xgmib_info.Tx64Byte); - - len += snprintf(buf + len, sizeof(priv->buf) - len, - "%-18s: %llu\n", "Tx128Byte", xgmib_info.Tx128Byte); - - len += snprintf(buf + len, sizeof(priv->buf) - len, - "%-18s: %llu\n", "Tx256Byte", xgmib_info.Tx256Byte); - - len += snprintf(buf + len, sizeof(priv->buf) - len, - "%-18s: %llu\n", "Tx512Byte", xgmib_info.Tx512Byte); - - len += snprintf(buf + len, sizeof(priv->buf) - len, - "%-18s: %llu\n", "Tx1024Byte", xgmib_info.Tx1024Byte); - - len += snprintf(buf + len, sizeof(priv->buf) - len, - "%-18s: %llu\n", "TxMaxByte", xgmib_info.TxMaxByte); - - len += snprintf(buf + len, sizeof(priv->buf) - len, - "%-18s: %llu\n", "TxUnicast", xgmib_info.TxUnicast); - - len += snprintf(buf + len, sizeof(priv->buf) - len, - "%-18s: %llu\n", "TxMulti", xgmib_info.TxMulti); - - len += snprintf(buf + len, sizeof(priv->buf) - len, - "%-18s: %llu\n", "TxBroad", xgmib_info.TxBroad); - - len += snprintf(buf + len, sizeof(priv->buf) - len, - "%-18s: %llu\n", "TxUnderFlowError", xgmib_info.TxUnderFlowError); - - len += snprintf(buf + len, sizeof(priv->buf) - len, - "%-18s: %llu\n", "TxByteGood", xgmib_info.TxByteGood); - - len += snprintf(buf + len, sizeof(priv->buf) - len, - "%-18s: %llu\n", "TxByteGood", xgmib_info.TxByteGood); - - len += snprintf(buf + len, sizeof(priv->buf) - len, - "%-18s: %llu\n", "TxPause", xgmib_info.TxPause); - - len += snprintf(buf + len, sizeof(priv->buf) - len, - "%-18s: %llu\n", "TxVLANFrameGood", xgmib_info.TxVLANFrameGood); - - len += snprintf(buf + len, sizeof(priv->buf) - len, - "%-18s: %llu\n", "TxLPIUsec", xgmib_info.TxLPIUsec); - - len += snprintf(buf + len, sizeof(priv->buf) - len, - "%-18s: %llu\n", "TxLPITran", xgmib_info.TxLPITran); - - mutex_unlock(&priv->mib_lock); - - val->value.s = buf; - val->len = len; - - return 0; -} -#endif - -int -qca_ar8327_sw_get_port_mib(struct switch_dev *dev, - const struct switch_attr *attr, - struct switch_val *val) -{ - int port = 0; - int len = 0; - int pos = 0; - - struct qca_phy_priv *priv = qca_phy_priv_get(dev); - char *buf = (char *)(priv->buf); - - port = val->port_vlan; - if (port >= dev->ports) - return -EINVAL; -#ifdef HPPE - if (priv->version == QCA_VER_HPPE && - qca_hppe_port_mac_type_get(priv->device_id, port) == PORT_XGMAC_TYPE) - { - qca_ar8327_sw_print_xgport_mib(dev, attr, val); - return 0; - } -#endif - mutex_lock(&priv->mib_lock); - _qca_ar8327_sw_capture_port_counter(dev, port); - pos = port * (sizeof(fal_mib_counter_t)/sizeof(a_uint64_t)); - len += snprintf(buf + len, sizeof(priv->buf) - len, - "Port %d MIB counters\n", - port); - - len += snprintf(buf + len, sizeof(priv->buf) - len, - "%-12s: %llu\n", - "RxBroad", - priv->mib_counters[pos++]); - len += snprintf(buf + len, sizeof(priv->buf) - len, - "%-12s: %llu\n", - "RxPause", - priv->mib_counters[pos++]); - len += snprintf(buf + len, sizeof(priv->buf) - len, - "%-12s: %llu\n", - "RxMulti", - priv->mib_counters[pos++]); - len += snprintf(buf + len, sizeof(priv->buf) - len, - "%-12s: %llu\n", - "RxFcsErr", - priv->mib_counters[pos++]); - len += snprintf(buf + len, sizeof(priv->buf) - len, - "%-12s: %llu\n", - "RxAlignErr", - priv->mib_counters[pos++]); - len += snprintf(buf + len, sizeof(priv->buf) - len, - "%-12s: %llu\n", - "RxRunt", - priv->mib_counters[pos++]); - len += snprintf(buf + len, sizeof(priv->buf) - len, - "%-12s: %llu\n", - "RxFragment", - priv->mib_counters[pos++]); - len += snprintf(buf + len, sizeof(priv->buf) - len, - "%-12s: %llu\n", - "Rx64Byte", - priv->mib_counters[pos++]); - len += snprintf(buf + len, sizeof(priv->buf) - len, - "%-12s: %llu\n", - "Rx128Byte", - priv->mib_counters[pos++]); - len += snprintf(buf + len, sizeof(priv->buf) - len, - "%-12s: %llu\n", - "Rx256Byte", - priv->mib_counters[pos++]); - len += snprintf(buf + len, sizeof(priv->buf) - len, - "%-12s: %llu\n", - "Rx512Byte", - priv->mib_counters[pos++]); - len += snprintf(buf + len, sizeof(priv->buf) - len, - "%-12s: %llu\n", - "Rx1024Byte", - priv->mib_counters[pos++]); - len += snprintf(buf + len, sizeof(priv->buf) - len, - "%-12s: %llu\n", - "Rx1518Byte", - priv->mib_counters[pos++]); - len += snprintf(buf + len, sizeof(priv->buf) - len, - "%-12s: %llu\n", - "RxMaxByte", - priv->mib_counters[pos++]); - len += snprintf(buf + len, sizeof(priv->buf) - len, - "%-12s: %llu\n", - "RxTooLong", - priv->mib_counters[pos++]); - len += snprintf(buf + len, sizeof(priv->buf) - len, - "%-12s: %llu\n", - "RxGoodByte", - priv->mib_counters[pos++]); - len += snprintf(buf + len, sizeof(priv->buf) - len, - "%-12s: %llu\n", - "RxBadByte", - priv->mib_counters[pos++]); - len += snprintf(buf + len, sizeof(priv->buf) - len, - "%-12s: %llu\n", - "RxOverFlow", - priv->mib_counters[pos++]); - len += snprintf(buf + len, sizeof(priv->buf) - len, - "%-12s: %llu\n", - "Filtered", - priv->mib_counters[pos++]); - len += snprintf(buf + len, sizeof(priv->buf) - len, - "%-12s: %llu\n", - "TxBroad", - priv->mib_counters[pos++]); - len += snprintf(buf + len, sizeof(priv->buf) - len, - "%-12s: %llu\n", - "TxPause", - priv->mib_counters[pos++]); - len += snprintf(buf + len, sizeof(priv->buf) - len, - "%-12s: %llu\n", - "TxMulti", - priv->mib_counters[pos++]); - len += snprintf(buf + len, sizeof(priv->buf) - len, - "%-12s: %llu\n", - "TxUnderRun", - priv->mib_counters[pos++]); - len += snprintf(buf + len, sizeof(priv->buf) - len, - "%-12s: %llu\n", - "Tx64Byte", - priv->mib_counters[pos++]); - len += snprintf(buf + len, sizeof(priv->buf) - len, - "%-12s: %llu\n", - "Tx128Byte", - priv->mib_counters[pos++]); - len += snprintf(buf + len, sizeof(priv->buf) - len, - "%-12s: %llu\n", - "Tx256Byte", - priv->mib_counters[pos++]); - len += snprintf(buf + len, sizeof(priv->buf) - len, - "%-12s: %llu\n", - "Tx512Byte", - priv->mib_counters[pos++]); - len += snprintf(buf + len, sizeof(priv->buf) - len, - "%-12s: %llu\n", - "Tx1024Byte", - priv->mib_counters[pos++]); - len += snprintf(buf + len, sizeof(priv->buf) - len, - "%-12s: %llu\n", - "Tx1518Byte", - priv->mib_counters[pos++]); - len += snprintf(buf + len, sizeof(priv->buf) - len, - "%-12s: %llu\n", - "TxMaxByte", - priv->mib_counters[pos++]); - len += snprintf(buf + len, sizeof(priv->buf) - len, - "%-12s: %llu\n", - "TxOverSize", - priv->mib_counters[pos++]); - len += snprintf(buf + len, sizeof(priv->buf) - len, - "%-12s: %llu\n", - "TxByte", - priv->mib_counters[pos++]); - len += snprintf(buf + len, sizeof(priv->buf) - len, - "%-12s: %llu\n", - "TxCollision", - priv->mib_counters[pos++]); - len += snprintf(buf + len, sizeof(priv->buf) - len, - "%-12s: %llu\n", - "TxAbortCol", - priv->mib_counters[pos++]); - len += snprintf(buf + len, sizeof(priv->buf) - len, - "%-12s: %llu\n", - "TxMultiCol", - priv->mib_counters[pos++]); - len += snprintf(buf + len, sizeof(priv->buf) - len, - "%-12s: %llu\n", - "TxSingleCol", - priv->mib_counters[pos++]); - len += snprintf(buf + len, sizeof(priv->buf) - len, - "%-12s: %llu\n", - "TxExcDefer", - priv->mib_counters[pos++]); - len += snprintf(buf + len, sizeof(priv->buf) - len, - "%-12s: %llu\n", - "TxDefer", - priv->mib_counters[pos++]); - len += snprintf(buf + len, sizeof(priv->buf) - len, - "%-12s: %llu\n", - "TxLateCol", - priv->mib_counters[pos++]); - len += snprintf(buf + len, sizeof(priv->buf) - len, - "%-12s: %llu\n", - "RxUniCast", - priv->mib_counters[pos++]); - len += snprintf(buf + len, sizeof(priv->buf) - len, - "%-12s: %llu\n", - "TxUniCast", - priv->mib_counters[pos++]); - mutex_unlock(&priv->mib_lock); - - val->value.s = buf; - val->len = len; - - return 0; -} -#endif - -int -_qca_ar8327_sw_capture_port_tx_counter(struct qca_phy_priv *priv, int port) -{ - fal_mib_info_t mib_Info; - - memset(&mib_Info, 0, sizeof(fal_mib_info_t)); - fal_get_tx_mib_info(priv->device_id, port, &mib_Info); - - return 0; -} - -int -_qca_ar8327_sw_capture_port_rx_counter(struct qca_phy_priv *priv, int port) -{ - fal_mib_info_t mib_Info; - - memset(&mib_Info, 0, sizeof(fal_mib_info_t)); - fal_get_rx_mib_info(priv->device_id, port, &mib_Info); - return 0; -} - -void -qca_ar8327_sw_mib_task(struct qca_phy_priv *priv) -{ - static int loop = 0; - - mutex_lock(&priv->reg_mutex); - if ((loop % 2) == 0) - _qca_ar8327_sw_capture_port_rx_counter(priv, loop/2); - else - _qca_ar8327_sw_capture_port_tx_counter(priv, loop/2); - - if(++loop == (2 * (priv->ports))) { - loop = 0; - } - - mutex_unlock(&priv->reg_mutex); - - return; -} diff --git a/feeds/ipq807x/qca-ssdk/src/src/ref/ref_misc.c b/feeds/ipq807x/qca-ssdk/src/src/ref/ref_misc.c deleted file mode 100755 index 5e05050d1..000000000 --- a/feeds/ipq807x/qca-ssdk/src/src/ref/ref_misc.c +++ /dev/null @@ -1,193 +0,0 @@ -/* - * Copyright (c) 2012, 2017, The Linux Foundation. All rights reserved. - * Permission to use, copy, modify, and/or distribute this software for - * any purpose with or without fee is hereby granted, provided that the - * above copyright notice and this permission notice appear in all copies. - * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES - * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR - * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES - * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN - * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT - * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. - */ - -#include "sw.h" -#include "ssdk_init.h" -#include "fal_init.h" -#include "fal_misc.h" -#include "fal_mib.h" -#include "fal_port_ctrl.h" -#include "fal_portvlan.h" -#include "fal_fdb.h" -#include "fal_stp.h" -#include "fal_igmp.h" -#include "fal_qos.h" -#include "hsl.h" -#include "hsl_dev.h" -#include "ssdk_init.h" -#include -#include -#include -#include -#include -#include -#include -//#include -#include -#if defined(CONFIG_OF) && (LINUX_VERSION_CODE >= KERNEL_VERSION(3,14,0)) -#include -#else -#include -#include -#endif -#include -#include -#include -#include "ssdk_plat.h" -#include "ref_vlan.h" -#ifdef MP -#include -#include "hsl_phy.h" -#endif - -int -qca_ar8327_sw_set_max_frame_size(struct switch_dev *dev, - const struct switch_attr *attr, - struct switch_val *val) -{ - struct qca_phy_priv *priv = qca_phy_priv_get(dev); - a_uint32_t size = val->value.i; - a_uint32_t ret; - a_uint32_t port_id = SSDK_PHYSICAL_PORT0; - - if (priv->version == QCA_VER_HPPE) - { - for(port_id = SSDK_PHYSICAL_PORT1; port_id <= SSDK_PHYSICAL_PORT6; - port_id++) - { - ret = fal_port_max_frame_size_set(priv->device_id, - port_id, size); - if(ret) - { - return -1; - } - } - } - else if (priv->version == QCA_VER_SCOMPHY) - { -#ifdef MP - if(adapt_scomphy_revision_get(priv->device_id) - == MP_GEPHY) - { - for(port_id = SSDK_PHYSICAL_PORT1; port_id <= SSDK_PHYSICAL_PORT2; - port_id++) - { - ret = fal_port_max_frame_size_set(priv->device_id, - port_id, size); - if(ret) - { - return -1; - } - } - } -#endif - } - else - { - ret = fal_frame_max_size_set(priv->device_id, size); - if (ret) - { - return -1; - } - } - - return 0; -} - -int -qca_ar8327_sw_get_max_frame_size(struct switch_dev *dev, - const struct switch_attr *attr, - struct switch_val *val) -{ - struct qca_phy_priv *priv = qca_phy_priv_get(dev); - a_uint32_t size = 0; - a_uint32_t ret = 0; - - if (priv->version == QCA_VER_HPPE) - { - ret = fal_port_max_frame_size_get(priv->device_id, - SSDK_PHYSICAL_PORT1, &size); - } - else if (priv->version == QCA_VER_SCOMPHY) - { -#ifdef MP - if(adapt_scomphy_revision_get(priv->device_id) - == MP_GEPHY) - { - ret = fal_port_max_frame_size_get(priv->device_id, - SSDK_PHYSICAL_PORT1, &size); - } -#endif - } - else - { - ret = fal_frame_max_size_get(priv->device_id, &size); - } - if (ret){ - return -1; - } - - val->value.i = size; - - return 0; -} - -int -qca_ar8327_sw_reset_switch(struct switch_dev *dev) -{ - struct qca_phy_priv *priv = qca_phy_priv_get(dev); - int rv = 0; - a_uint32_t mac_mode; - - mutex_lock(&priv->reg_mutex); - - /* flush all vlan translation unit entries */ - fal_vlan_flush(priv->device_id); - - /* reset VLAN shadow */ - priv->vlan = 0; - memset(priv->vlan_id, 0, sizeof(a_uint16_t) * AR8327_MAX_VLANS); - memset(priv->vlan_table, 0, sizeof(a_uint8_t) * AR8327_MAX_VLANS); - memset(priv->vlan_tagged, 0, sizeof(a_uint8_t) * AR8327_MAX_VLANS); - memset(priv->pvid, 0, sizeof(a_uint16_t) * AR8327_NUM_PORTS); - - mutex_unlock(&priv->reg_mutex); - - priv->init = true; - rv += qca_ar8327_sw_hw_apply(dev); - priv->init = false; - - mac_mode = ssdk_dt_global_get_mac_mode(priv->device_id, 0); - /* set mac5 flowcontol force for RGMII */ - if ((mac_mode == PORT_WRAPPER_SGMII0_RGMII5) - ||(mac_mode == PORT_WRAPPER_SGMII1_RGMII5)) { - fal_port_flowctrl_forcemode_set(priv->device_id, 5, A_TRUE); - fal_port_flowctrl_set(priv->device_id, 5, A_TRUE); - } - /* set mac4 flowcontol force for RGMII */ - if ((mac_mode == PORT_WRAPPER_SGMII0_RGMII4) - ||(mac_mode == PORT_WRAPPER_SGMII1_RGMII4) - ||(mac_mode == PORT_WRAPPER_SGMII4_RGMII4)) { - /* fix channel4 will recieve packets when enable channel0 as SGMII */ - if(mac_mode == PORT_WRAPPER_SGMII0_RGMII4) { - fal_port_txmac_status_set (priv->device_id, 5, A_FALSE); - fal_port_rxmac_status_set (priv->device_id, 5, A_FALSE); - } - fal_port_flowctrl_forcemode_set(priv->device_id, 4, A_TRUE); - fal_port_flowctrl_set(priv->device_id, 4, A_TRUE); - } - - return rv; -} - diff --git a/feeds/ipq807x/qca-ssdk/src/src/ref/ref_port_ctrl.c b/feeds/ipq807x/qca-ssdk/src/src/ref/ref_port_ctrl.c deleted file mode 100644 index b0a0b679e..000000000 --- a/feeds/ipq807x/qca-ssdk/src/src/ref/ref_port_ctrl.c +++ /dev/null @@ -1,775 +0,0 @@ -/* - * Copyright (c) 2012, 2016-2017, The Linux Foundation. All rights reserved. - * Permission to use, copy, modify, and/or distribute this software for - * any purpose with or without fee is hereby granted, provided that the - * above copyright notice and this permission notice appear in all copies. - * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES - * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR - * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES - * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN - * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT - * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. - */ - -#include "sw.h" -#include "ssdk_init.h" -#include "fal_init.h" -#include "fal_misc.h" -#include "fal_mib.h" -#include "fal_port_ctrl.h" -#include "fal_portvlan.h" -#include "fal_fdb.h" -#include "fal_stp.h" -#include "fal_igmp.h" -#include "fal_qos.h" -#include "hsl.h" -#include "hsl_dev.h" -#include "hsl_phy.h" -#include "ssdk_init.h" -#include -#include -#include -#include -#include -#include -#include -//#include -#include -#if defined(CONFIG_OF) && (LINUX_VERSION_CODE >= KERNEL_VERSION(3,14,0)) -#include -#else -#include -#endif -#include -#include -#include -#include "ssdk_plat.h" -#include "ref_vlan.h" -#include -#include "f1_phy.h" -#include "ref_port_ctrl.h" - -#if defined(CONFIG_OF) && (LINUX_VERSION_CODE >= KERNEL_VERSION(3,14,0)) -#ifdef DESS -extern struct reset_control *ess_mac_clock_disable[5]; -#endif -#endif - -#if defined(IN_SWCONFIG) -int -qca_ar8327_sw_get_port_link(struct switch_dev *dev, int port, - struct switch_port_link *link) -{ - struct qca_phy_priv *priv = qca_phy_priv_get(dev); - - fal_port_speed_t speed = FAL_SPEED_10; - fal_port_duplex_t duplex = FAL_FULL_DUPLEX; - fal_port_eee_cfg_t port_eee_cfg = {0}; - a_bool_t status = 0; - a_bool_t tx_fc = 0; - a_bool_t rx_fc = 0; - sw_error_t ret; - - mutex_lock(&priv->reg_mutex); - ret = fal_port_link_status_get(priv->device_id, port, &status); - if (ret == SW_OK) { - link->link = status; - } else { - mutex_unlock(&priv->reg_mutex); - return 0; - } - - ret = fal_port_speed_get(priv->device_id, port, &speed); - if (ret == SW_OK) { - if (speed == FAL_SPEED_10) { - link->speed = SWITCH_PORT_SPEED_10; - } else if (speed == FAL_SPEED_100) { - link->speed = SWITCH_PORT_SPEED_100; - } else if (speed == FAL_SPEED_1000) { - link->speed = SWITCH_PORT_SPEED_1000; - #if (LINUX_VERSION_CODE >= KERNEL_VERSION(4,4,0)) - } else if (speed == FAL_SPEED_2500) { - link->speed = SWITCH_PORT_SPEED_2500; - } else if (speed == FAL_SPEED_5000) { - link->speed = SWITCH_PORT_SPEED_5000; - } else if (speed == FAL_SPEED_10000) { - link->speed = SWITCH_PORT_SPEED_10000; - #endif - } else { - link->speed = SWITCH_PORT_SPEED_UNKNOWN; - } - } - - ret = fal_port_duplex_get(priv->device_id, port, &duplex); - if (ret == SW_OK) { - if (duplex == FAL_HALF_DUPLEX) { - link->duplex = 0; /* HALF */ - } else if (duplex == FAL_FULL_DUPLEX) { - link->duplex = 1; /* FULL */ - } - } - - ret = fal_port_rxfc_status_get(priv->device_id, port, &rx_fc); - if (ret == SW_OK) { - link->rx_flow = rx_fc; - } - - ret = fal_port_txfc_status_get(priv->device_id, port, &tx_fc); - if (ret == SW_OK) { - link->tx_flow = tx_fc; - } - ret = fal_port_interface_eee_cfg_get(priv->device_id, port, - &port_eee_cfg); - if(ret == SW_OK) - { - link->eee &= ~(ADVERTISED_100baseT_Full || ADVERTISED_1000baseT_Full); - if(port_eee_cfg.advertisement & FAL_PHY_EEE_100BASE_T) { - link->eee |= ADVERTISED_100baseT_Full; - } - if(port_eee_cfg.advertisement & FAL_PHY_EEE_1000BASE_T) { - link->eee |= ADVERTISED_1000baseT_Full; - } - } - mutex_unlock(&priv->reg_mutex); - - return 0; -} -#endif - -static int qca_switch_get_qm_status(struct qca_phy_priv *priv, a_uint32_t port_id, a_uint32_t *qm_buffer_err) -{ - a_uint32_t reg = 0; - a_uint32_t qm_val = 0; - - if (port_id < 0 || port_id > 6) { - *qm_buffer_err = 0; - return -1; - } - if (priv->version == 0x14) - { - if (port_id < 4) { - reg = 0x1D; - qca_switch_reg_write(priv->device_id, 0x820, (a_uint8_t *)®, 4); - qca_switch_reg_read(priv->device_id, 0x824, (a_uint8_t *)&qm_val, 4); - *qm_buffer_err = (qm_val >> (port_id * 8)) & 0xFF; - } else { - reg = 0x1E; - qca_switch_reg_write(priv->device_id, 0x820, (a_uint8_t *)®, 4); - qca_switch_reg_read(priv->device_id, 0x824, (a_uint8_t *)&qm_val, 4); - *qm_buffer_err = (qm_val >> ((port_id-4) * 8)) & 0xFF; - } - } - if (priv->version == QCA_VER_AR8337 || - priv->version == QCA_VER_AR8327) - { - if (port_id < 4) { - reg = 0x1D; - priv->mii_write(priv->device_id, 0x820, reg); - qm_val = priv->mii_read(priv->device_id, 0x824); - *qm_buffer_err = (qm_val >> (port_id * 8)) & 0xFF; - } else { - reg = 0x1E; - priv->mii_write(priv->device_id, 0x820, reg); - qm_val = priv->mii_read(priv->device_id, 0x824); - *qm_buffer_err = (qm_val >> ((port_id-4) * 8)) & 0xFF; - } - } - - return 0; -} - -static int qca_switch_force_mac_1000M_full(struct qca_phy_priv *priv, a_uint32_t port_id) -{ - a_uint32_t reg, value = 0; - - if (port_id < 0 || port_id > 6) - return -1; - if (priv->version == 0x14) - { - reg = AR8327_REG_PORT_STATUS(port_id); - qca_switch_reg_read(priv->device_id, reg, (a_uint8_t *)&value, 4); - value &= ~(BIT(6) | BITS(0,2)); - value |= AR8327_PORT_SPEED_1000M | BIT(6); - qca_switch_reg_write(priv->device_id, reg, (a_uint8_t *)&value, 4); - } - if (priv->version == QCA_VER_AR8337 || - priv->version == QCA_VER_AR8327) - { - reg = AR8327_REG_PORT_STATUS(port_id); - value = priv->mii_read(priv->device_id, reg); - value &= ~(BIT(6) | BITS(0,2)); - value |= AR8327_PORT_SPEED_1000M | BIT(6); - priv->mii_write(priv->device_id, reg, value); - } - return 0; -} - -static int qca_switch_force_mac_status(struct qca_phy_priv *priv, a_uint32_t port_id,a_uint32_t speed,a_uint32_t duplex) -{ - a_uint32_t reg, value = 0; - - if (port_id < 1 || port_id > 5) - return -1; - if (priv->version == 0x14) - { -#if defined(CONFIG_OF) && (LINUX_VERSION_CODE >= KERNEL_VERSION(3,14,0)) -#ifdef DESS - /*disable mac clock*/ - reset_control_assert(ess_mac_clock_disable[port_id -1]); - udelay(10); - reg = AR8327_REG_PORT_STATUS(port_id); - qca_switch_reg_read(priv->device_id,reg,(a_uint8_t*)&value,4); - value &= ~(BIT(6) | BITS(0,2)); - value |= speed | (duplex?BIT(6):0); - qca_switch_reg_write(priv->device_id,reg,(a_uint8_t*)&value,4); - /*enable mac clock*/ - reset_control_deassert(ess_mac_clock_disable[port_id -1]); -#endif -#endif - } - if (priv->version == QCA_VER_AR8337 || - priv->version == QCA_VER_AR8327) - { - reg = AR8327_REG_PORT_STATUS(port_id); - value = priv->mii_read(priv->device_id, reg); - value &= ~(BIT(6) | BITS(0,2)); - value |= speed | (duplex?BIT(6):0); - priv->mii_write(priv->device_id, reg,value); - } - - return 0; -} - -a_bool_t -qca_ar8327_sw_rgmii_mode_valid(a_uint32_t dev_id, a_uint32_t port_id) -{ - a_uint32_t rgmii_mode; - - rgmii_mode = ssdk_dt_global_get_mac_mode(dev_id, 0); - - if(((rgmii_mode == PORT_WRAPPER_SGMII0_RGMII5) || - (rgmii_mode == PORT_WRAPPER_SGMII1_RGMII5)) && (port_id == 5)) - return A_TRUE; - - if(((rgmii_mode == PORT_WRAPPER_SGMII0_RGMII4) || - (rgmii_mode == PORT_WRAPPER_SGMII1_RGMII4) || - (rgmii_mode == PORT_WRAPPER_SGMII4_RGMII4)) && (port_id == 4)) - return A_TRUE; - - return A_FALSE; -} - -static int -qca_switch_get_mac_link(struct qca_phy_priv *priv, a_uint32_t port_id, a_uint32_t *link) -{ - a_uint32_t reg, value = 0; - - if (port_id < 0 || port_id > 6) - return -1; - if (priv->version == 0x14) - { - reg = AR8327_REG_PORT_STATUS(port_id); - qca_switch_reg_read(priv->device_id,reg,(a_uint8_t*)&value,4); - *link = (value>>8)&0x1; - } - if (priv->version == QCA_VER_AR8337 || - priv->version == QCA_VER_AR8327) - { - reg = AR8327_REG_PORT_STATUS(port_id); - value = priv->mii_read(priv->device_id, reg); - *link = (value>>8)&0x1; - } - - return 0; -} - - -#define MDI_FROM_PHY_STATUS 1 -#define MDI_FROM_MANUAL 0 -#define PORT_LINK_UP 1 -#define PORT_LINK_DOWN 0 - -#define QM_NOT_EMPTY 1 -#define QM_EMPTY 0 - - -static a_uint32_t phy_current_speed = 2; -static a_uint32_t phy_current_duplex = 1; - -#if defined(IN_VLAN) -int qca_ar8327_sw_enable_vlan0(a_uint32_t dev_id, a_bool_t enable, a_uint8_t portmap); -int qca_ar8327_vlan_recovery(struct qca_phy_priv *priv) -{ - fal_pbmp_t portmask[AR8327_NUM_PORTS]; - int i, j; - a_uint32_t reg, val; - u8 mask ; - - mutex_lock(&priv->reg_mutex); - - memset(portmask, 0, sizeof(portmask)); - if (!priv->init) { - /*Handle VLAN 0 entry*/ - if (priv->vlan_id[0] == 0 && priv->vlan_table[0] == 0) { - qca_ar8327_sw_enable_vlan0(priv->device_id,A_FALSE, 0); - } - - /* calculate the port destination masks and load vlans - * into the vlan translation unit */ - for (j = 0; j < AR8327_MAX_VLANS; j++) { - /* - //############################# VLAN -1 ######################### - //## VID=1 VLAN member : P1-t,P2-t,P3-t,P4-t,P5-t, P6-t - or 610 000AAAB0 - or 614 80010002 - */ - if (priv->vlan_id[j]) { - /* reg 0x610 VLAN_TABLE_FUNC0_OFFSET*/ - reg = 0x610; - val = 0x00180000; - for (i = 0; i < priv->ports; ++i) { - mask = (1 << i); - portmask[i] |= ~mask & priv->vlan_table[j]; - if (mask & priv->vlan_table[j]) - { - val |= ((mask & priv->vlan_tagged[j]) ? - FAL_EG_TAGGED : - FAL_EG_UNTAGGED) << ((i<<1) + 4); - } - else - val |= (0x3) << ((i << 1) + 4); // not member. - } - priv->mii_write(priv->device_id, reg, val); - - /* reg 0x614 VLAN_TABLE_FUNC1_OFFSET*/ - reg = 0x614; - val = 0x80000002; // load en entry - val |= priv->vlan_id[j] << 16; - priv->mii_write(priv->device_id, reg, val); - } - } - - /*Hanlde VLAN 0 entry*/ - if (priv->vlan_id[0] == 0 && priv->vlan_table[0]) { - qca_ar8327_sw_enable_vlan0(priv->device_id,A_TRUE, priv->vlan_table[0]); - } - - } else { -#if defined(IN_PORTVLAN) - /* vlan disabled: port based vlan used */ - ssdk_portvlan_init(priv->device_id); -#endif - } - -#if defined(IN_PORTVLAN) - /* update the port destination mask registers and tag settings */ - for (i = 0; i < priv->ports; i++) { - int pvid; - fal_pt_1qmode_t ingressMode; - fal_pt_1q_egmode_t egressMode; - - if (priv->vlan) { - pvid = priv->vlan_id[priv->pvid[i]]; - if (priv->vlan_tagged[priv->pvid[i]] & (1 << i)) { - egressMode = FAL_EG_TAGGED; - } else { - egressMode = FAL_EG_UNTAGGED; - } - - ingressMode = FAL_1Q_SECURE; - } else { - pvid = 0; - egressMode = FAL_EG_UNTOUCHED; - ingressMode = FAL_1Q_DISABLE; - } - - /*If VLAN 0 existes, change member port - *egress mode as UNTOUCHED*/ - if (priv->vlan_id[0] == 0 && - priv->vlan_table[0] && - ((0x1 << i) & priv->vlan_table[0]) && - priv->vlan) { - egressMode = FAL_EG_UNTOUCHED; - } - - fal_port_1qmode_set(priv->device_id, i, ingressMode); - fal_port_egvlanmode_set(priv->device_id, i, egressMode); - fal_port_default_cvid_set(priv->device_id, i, pvid); - if (!priv->init && priv->vlan) { - fal_portvlan_member_update(priv->device_id, i, portmask[i]); - } - } -#endif - - mutex_unlock(&priv->reg_mutex); - - return 0; -} -#endif - -int qca_qm_error_check(struct qca_phy_priv *priv) -{ - a_uint32_t value = 0, qm_err_int=0; - - if (priv->version == QCA_VER_AR8337 || - priv->version == QCA_VER_AR8327) - { - value = priv->mii_read(priv->device_id, 0x24); - qm_err_int = value & BIT(14); // b14-QM_ERR_INT - - if(qm_err_int) - return 1; - - priv->mii_write(priv->device_id, 0x820, 0x0); - value = priv->mii_read(priv->device_id, 0x824); - } - if(priv->version==0x14) - { - qca_switch_reg_read(priv->device_id, 0x24, (a_uint8_t*)&value, 4); - qm_err_int = value & BIT(14); // b14-QM_ERR_INT - - if(qm_err_int) - return 1; - value = 0; - qca_switch_reg_write(priv->device_id, 0x820, (a_uint8_t*)&value, 4); - qca_switch_reg_read(priv->device_id, 0x824, (a_uint8_t*)&value, 4); - } - return value; -} - -void qca_ar8327_phy_linkdown(a_uint32_t dev_id); -int qca_ar8327_hw_init(struct qca_phy_priv *priv); - -int qca_qm_err_recovery(struct qca_phy_priv *priv) -{ - memset(priv->port_link_down, 0, sizeof(priv->port_link_down)); - memset(priv->port_link_up, 0, sizeof(priv->port_link_up)); - memset(priv->port_old_link, 0, sizeof(priv->port_old_link)); - memset(priv->port_old_speed, 0, sizeof(priv->port_old_speed)); - memset(priv->port_old_duplex, 0, sizeof(priv->port_old_duplex)); - memset(priv->port_old_phy_status, 0, sizeof(priv->port_old_phy_status)); - memset(priv->port_qm_buf, 0, sizeof(priv->port_qm_buf)); - - /* in soft reset recovery procedure */ - qca_ar8327_phy_linkdown(priv->device_id); - - qca_ar8327_hw_init(priv); - -#if defined(IN_VLAN) - qca_ar8327_vlan_recovery(priv); -#endif - - /*To add customerized recovery codes*/ - - return 1; -} - -a_bool_t -qca_ar8327_sw_mac_polling_port_valid(struct qca_phy_priv *priv, a_uint32_t port_id) -{ - a_uint32_t mac_mode; - - mac_mode = ssdk_dt_global_get_mac_mode(priv->device_id, 0); - - if( port_id >= AR8327_NUM_PORTS-1 || port_id < 1) - return A_FALSE; - - if(((mac_mode == PORT_WRAPPER_SGMII0_RGMII5) || - (mac_mode == PORT_WRAPPER_SGMII1_RGMII5)) && (port_id != 5)) - return A_FALSE; - - if(((mac_mode == PORT_WRAPPER_SGMII0_RGMII4) || - (mac_mode == PORT_WRAPPER_SGMII1_RGMII4) || - (mac_mode == PORT_WRAPPER_SGMII4_RGMII4)) && (port_id != 4)) - return A_FALSE; - - return A_TRUE; -} -void -qca_phy_status_get(a_uint32_t dev_id, a_uint32_t port_id, a_uint32_t *speed_status, a_uint32_t *link_status, a_uint32_t *duplex_status) -{ - a_uint16_t port_phy_status; - a_uint32_t phy_addr; - - phy_addr = qca_ssdk_port_to_phy_addr(dev_id, port_id); - if (qca_ar8327_sw_rgmii_mode_valid(dev_id, port_id) == A_TRUE) - phy_addr = 4; - - qca_ar8327_phy_read(dev_id, phy_addr, F1_PHY_SPEC_STATUS, &port_phy_status); - *speed_status = (a_uint32_t)((port_phy_status >> 14) & 0x03); - *link_status = (a_uint32_t)((port_phy_status & BIT(10)) >> 10); - *duplex_status = (a_uint32_t)((port_phy_status & BIT(13)) >> 13); -} - -/* Initialize notifier list for QCA SSDK */ -static BLOCKING_NOTIFIER_HEAD(ssdk_port_link_notifier_list); - -int ssdk_port_link_notify(unsigned char port_id, - unsigned char link, unsigned char speed, unsigned char duplex) -{ - ssdk_port_status port_status; - - port_status.port_id = port_id; - port_status.port_link = link; - port_status.speed = speed; - port_status.duplex = duplex; - - return blocking_notifier_call_chain(&ssdk_port_link_notifier_list, 0, &port_status); -} - -int ssdk_port_link_notify_register(struct notifier_block *nb) -{ - return blocking_notifier_chain_register(&ssdk_port_link_notifier_list, nb); -} -EXPORT_SYMBOL(ssdk_port_link_notify_register); - -int ssdk_port_link_notify_unregister(struct notifier_block *nb) -{ - return blocking_notifier_chain_unregister(&ssdk_port_link_notifier_list, nb); -} -EXPORT_SYMBOL(ssdk_port_link_notify_unregister); - - -void -qca_ar8327_sw_mac_polling_task(struct qca_phy_priv *priv) -{ - static int task_count = 0; - a_uint32_t i, dev_id = 0; - a_uint32_t value; - a_uint32_t link = 0, speed = 0, duplex = 0; - a_uint32_t qm_buffer_err = 0, phy_addr = 0; - a_uint16_t port_phy_status[AR8327_NUM_PORTS] = {0,0,0,0,0,0,0}; - static a_uint32_t qm_err_cnt[AR8327_NUM_PORTS] = {0,0,0,0,0,0,0}; - - static a_uint32_t link_cnt[AR8327_NUM_PORTS] = {0,0,0,0,0,0,0}; - - dev_id = priv->device_id; - - /*Only valid for S17c chip*/ - if (priv->version != QCA_VER_AR8337 && - priv->version != QCA_VER_AR8327 && - priv->version != 0x14) - return; - - value = qca_qm_error_check(priv); - if(value) - { - if(priv->version != 0x14) - qca_qm_err_recovery(priv); - return; - } - - ++task_count; - - for (i = 1; i < AR8327_NUM_PORTS-1; i++) { - phy_addr = qca_ssdk_port_to_phy_addr(dev_id, i); - if(qca_ar8327_sw_mac_polling_port_valid(priv, i) == A_FALSE) - continue; - - if (qca_ar8327_sw_rgmii_mode_valid(dev_id, i) == A_FALSE) - qca_switch_get_mac_link(priv, i, &link); - else - { - qca_phy_status_get(dev_id, i, &speed, &link, &duplex); - } - if (link != priv->port_old_link[i]) { - if (qca_ar8327_sw_rgmii_mode_valid(dev_id, i) == A_FALSE) - { - qca_phy_status_get(dev_id, i, &speed, &link, &duplex); - } - ++link_cnt[i]; - /* Up --> Down */ - if ((priv->port_old_link[i] == PORT_LINK_UP) && (link == PORT_LINK_DOWN)) { - - if (qca_ar8327_sw_rgmii_mode_valid(dev_id, i) == A_TRUE) - { - fal_port_rxmac_status_set(dev_id, i, A_FALSE); - fal_port_txmac_status_set(dev_id, i, A_FALSE); - } - else - { - fal_port_link_forcemode_set(dev_id, i, A_TRUE); - SSDK_DEBUG("%s, %d, port_id %d link down\n",__FUNCTION__,__LINE__,i); - } - priv->port_link_down[i]=0; - ssdk_port_link_notify(i, 0, 0, 0); -#ifdef IN_FDB - fal_fdb_del_by_port(dev_id, i, 0);/*flush all dynamic fdb of this port*/ -#endif - if(priv->version != 0x14){ - /* Check queue buffer */ - a_uint16_t value = 0; - qm_err_cnt[i] = 0; - qca_switch_get_qm_status(priv, i, &qm_buffer_err); - - if (qm_buffer_err) { - priv->port_qm_buf[i] = QM_NOT_EMPTY; - } - else { - priv->port_qm_buf[i] = QM_EMPTY; - - /* Force MAC 1000M Full before auto negotiation */ - qca_switch_force_mac_1000M_full(priv, i); - mdelay(10); - SSDK_DEBUG("%s, %d, port %d link down\n",__FUNCTION__,__LINE__,i); - } - qca_ar8327_phy_dbg_read(dev_id, phy_addr, 0, &value); - value &= (~(1<<12)); - qca_ar8327_phy_dbg_write(dev_id, phy_addr, 0, value); - } - } - /* Down --> Up */ - else if ((priv->port_old_link[i] == PORT_LINK_DOWN) && (link == PORT_LINK_UP)) { - - if (priv->port_link_up[i] < 1) { - ++(priv->port_link_up[i]); - qca_switch_get_qm_status(priv, i, &qm_buffer_err); - if (qm_buffer_err) { - if(priv->version != 0x14) - qca_qm_err_recovery(priv); - if(priv->link_polling_required) - return; - } - } - if(priv->port_link_up[i] >=1) - { - priv->port_link_up[i]=0; - qca_switch_force_mac_status(priv, i, speed, duplex); - udelay(100); - if (qca_ar8327_sw_rgmii_mode_valid(dev_id, i) == A_FALSE) { - fal_port_link_forcemode_set(dev_id, i, A_FALSE); - } - else - { - fal_port_rxmac_status_set(dev_id, i, A_TRUE); - fal_port_txmac_status_set(dev_id, i, A_TRUE); - } - udelay(100); - SSDK_DEBUG("%s, %d, port %d link up speed %d, duplex %d\n",__FUNCTION__,__LINE__,i, speed, duplex); - ssdk_port_link_notify(i, 1, speed, duplex); - if((speed == 0x01) && (priv->version != 0x14))/*PHY is link up 100M*/ - { - a_uint16_t value = 0; - qca_ar8327_phy_dbg_read(dev_id, phy_addr, 0, &value); - value |= (1<<12); - qca_ar8327_phy_dbg_write(dev_id, phy_addr, 0, value); - } - } - } - if ((priv->port_link_down[i] == 0) - && (priv->port_link_up[i] == 0)){ - /* Save the current status */ - priv->port_old_speed[i] = speed; - priv->port_old_link[i] = link; - priv->port_old_duplex[i] = duplex; - priv->port_old_phy_status[i] = port_phy_status[i]; - } - } - - if (priv->port_qm_buf[i] == QM_NOT_EMPTY) { - /* Check QM */ - qca_switch_get_qm_status(priv, i, &qm_buffer_err); - if (qm_buffer_err) { - priv->port_qm_buf[i] = QM_NOT_EMPTY; - ++qm_err_cnt[i]; - } - else { - priv->port_qm_buf[i] = QM_EMPTY; - qm_err_cnt[i] = 0; - - /* Force MAC 1000M Full before auto negotiation */ - qca_switch_force_mac_1000M_full(priv, i); - } - } - } - return ; -} - -void -dess_rgmii_sw_mac_polling_task(struct qca_phy_priv *priv) -{ - a_uint32_t mac_mode; - a_uint16_t phy_spec_status, phy_link_status; - a_uint32_t speed, duplex; - - mac_mode = ssdk_dt_global_get_mac_mode(priv->device_id, 0); - - if ((mac_mode == PORT_WRAPPER_SGMII0_RGMII5) - ||(mac_mode == PORT_WRAPPER_SGMII1_RGMII5) - ||(mac_mode == PORT_WRAPPER_SGMII0_RGMII4) - ||(mac_mode == PORT_WRAPPER_SGMII1_RGMII4) - ||(mac_mode == PORT_WRAPPER_SGMII4_RGMII4)) { - qca_ar8327_phy_read(priv->device_id, 4, 0x11, &phy_spec_status); - phy_link_status = (a_uint16_t)((phy_spec_status & BIT(10)) >> 10); - if (phy_link_status == 1) { - speed = (a_uint32_t)((phy_spec_status >> 14) & 0x03); - duplex = (a_uint32_t)((phy_spec_status & BIT(13)) >> 13); - if ((speed != phy_current_speed) || (duplex != phy_current_duplex)) { - if ((mac_mode == PORT_WRAPPER_SGMII0_RGMII5) - ||(mac_mode == PORT_WRAPPER_SGMII1_RGMII5)) - qca_switch_force_mac_status(priv, 5,speed,duplex); - - if ((mac_mode == PORT_WRAPPER_SGMII0_RGMII4) - ||(mac_mode == PORT_WRAPPER_SGMII1_RGMII4) - ||(mac_mode == PORT_WRAPPER_SGMII4_RGMII4)) - qca_switch_force_mac_status(priv, 4,speed,duplex); - } - phy_current_speed = speed; - phy_current_duplex = duplex; - } - } - - return; -} - -#ifdef IN_SWCONFIG -int qca_ar8327_sw_set_eee(struct switch_dev *dev, - const struct switch_attr *attr, struct switch_val *val) -{ - sw_error_t rv = SW_OK; - struct qca_phy_priv *priv = qca_phy_priv_get(dev); - fal_port_eee_cfg_t port_eee_cfg; - - SSDK_DEBUG("configure EEE for dev_id: %d, port %d as %d\n", - priv->device_id, val->port_vlan, val->value.i); - rv = fal_port_interface_eee_cfg_get(priv->device_id, val->port_vlan, &port_eee_cfg); - if(rv != SW_OK) - { - return -1; - } - port_eee_cfg.enable = val->value.i; - port_eee_cfg.lpi_tx_enable = val->value.i; - - if(port_eee_cfg.enable) - { - port_eee_cfg.advertisement = FAL_PHY_EEE_100BASE_T | FAL_PHY_EEE_1000BASE_T; - } - rv = fal_port_interface_eee_cfg_set(priv->device_id, val->port_vlan, &port_eee_cfg); - if(rv != SW_OK) - { - return -1; - } - - return 0; -} - -int qca_ar8327_sw_get_eee(struct switch_dev *dev, - const struct switch_attr *attr, struct switch_val *val) -{ - sw_error_t rv = SW_OK; - struct qca_phy_priv *priv = qca_phy_priv_get(dev); - fal_port_eee_cfg_t port_eee_cfg; - - SSDK_DEBUG("get EEE for dev_id: %d, port %d\n", - priv->device_id, val->port_vlan); - rv = fal_port_interface_eee_cfg_get(priv->device_id, val->port_vlan, &port_eee_cfg); - if(rv != SW_OK) - { - return -1; - } - val->value.i = port_eee_cfg.enable; - - return 0; -} -#endif diff --git a/feeds/ipq807x/qca-ssdk/src/src/ref/ref_uci.c b/feeds/ipq807x/qca-ssdk/src/src/ref/ref_uci.c deleted file mode 100755 index a4291051d..000000000 --- a/feeds/ipq807x/qca-ssdk/src/src/ref/ref_uci.c +++ /dev/null @@ -1,11839 +0,0 @@ -/* - * Copyright (c) 2013, 2015, 2017-2019, 2021, The Linux Foundation. All rights reserved. - * - * Permission to use, copy, modify, and/or distribute this software for any - * purpose with or without fee is hereby granted, provided that the above - * copyright notice and this permission notice appear in all copies. - * - * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES - * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR - * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES - * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN - * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF - * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. - */ - -#include "sw.h" -#include "ssdk_init.h" -#include "fal_init.h" -#ifdef IN_MISC -#include "fal_misc.h" -#endif -#ifdef IN_MIB -#include "fal_mib.h" -#endif -#ifdef IN_PORTCONTROL -#include "fal_port_ctrl.h" -#endif -#ifdef IN_PORTVLAN -#include "fal_portvlan.h" -#endif -#ifdef IN_FDB -#include "fal_fdb.h" -#endif -#ifdef IN_STP -#include "fal_stp.h" -#endif -#ifdef IN_IGMP -#include "fal_igmp.h" -#endif -#ifdef IN_QOS -#include "fal_qos.h" -#endif -#ifdef IN_ACL -#include "fal_acl.h" -#endif -#ifdef IN_PPPOE -#include "fal_pppoe.h" -#endif -#ifdef IN_SERVCODE -#include "fal_servcode.h" -#endif -#ifdef IN_CTRLPKT -#include "fal_ctrlpkt.h" -#endif -#ifdef IN_POLICER -#include "fal_policer.h" -#endif -#ifdef IN_SHAPER -#include "fal_shaper.h" -#endif -#include "hsl.h" -#include "hsl_dev.h" -#include "ssdk_init.h" -#include "shell.h" -#include "shell_io.h" -#include "shell_sw.h" -#include -#include -#include -#include -#include -#include -#include -#include -#if defined(CONFIG_OF) && (LINUX_VERSION_CODE >= KERNEL_VERSION(3,14,0)) -#include -#else -#include -#include -#endif -#include -#include -#include -#include "ssdk_plat.h" -#include -#include "ref_uci.h" - -#define MOD_NAME_MAX_LEN 32 -#define COMMAND_NAME_MAX_LEN 128 -#define COMMAND_LINE_MAX_LEN 1024 -#define SWITCH_CFG_LEN_MAX 64 -char module_name[MOD_NAME_MAX_LEN] = {0}; -char command_name[COMMAND_NAME_MAX_LEN] = {0}; -char whole_command_line[COMMAND_LINE_MAX_LEN] = {0}; -char *val_ptr[SWITCH_CFG_LEN_MAX] = {0}; -static unsigned int parameter_length = 0; -#ifdef IN_NAT -static char *vrf_dflt_str = "0"; -static char *lb_dflt_str = "0"; -static char *cookie_dflt_str = "0"; -static char *priority_dflt_str = "no"; -static char *param_dflt_str = " "; -#endif - -#ifdef IN_QOS -#ifndef IN_QOS_MINI -static int -parse_qos_qtxbufsts(struct switch_val *val) -{ - struct switch_ext *switch_ext_p, *ext_value_p; - int rv = 0; - switch_ext_p = val->value.ext_val; - while(switch_ext_p) { - ext_value_p = switch_ext_p; - - if(!strcmp(ext_value_p->option_name, "name")) { - switch_ext_p = switch_ext_p->next; - continue; - } else if(!strcmp(ext_value_p->option_name, "port_id")) { - val_ptr[0] = (char*)ext_value_p->option_value; - } else if(!strcmp(ext_value_p->option_name, "buffer_limit")) { - val_ptr[1] = (char*)ext_value_p->option_value; - } else { - rv = -1; - break; - } - - parameter_length++; - switch_ext_p = switch_ext_p->next; - } - - return rv; -} - -static int -parse_qos_qtxbufnr(struct switch_val *val) -{ - struct switch_ext *switch_ext_p, *ext_value_p; - int rv = 0; - switch_ext_p = val->value.ext_val; - while(switch_ext_p) { - ext_value_p = switch_ext_p; - - if(!strcmp(ext_value_p->option_name, "name")) { - switch_ext_p = switch_ext_p->next; - continue; - } else if(!strcmp(ext_value_p->option_name, "port_id")) { - val_ptr[0] = (char*)ext_value_p->option_value; - } else if(!strcmp(ext_value_p->option_name, "queue_id")) { - val_ptr[1] = (char*)ext_value_p->option_value; - } else if(!strcmp(ext_value_p->option_name, "number")) { - val_ptr[2] = (char*)ext_value_p->option_value; - } else { - rv = -1; - break; - } - - parameter_length++; - switch_ext_p = switch_ext_p->next; - } - - return rv; -} - -static int -parse_qos_pttxbufsts(struct switch_val *val) -{ - struct switch_ext *switch_ext_p, *ext_value_p; - int rv = 0; - switch_ext_p = val->value.ext_val; - while(switch_ext_p) { - ext_value_p = switch_ext_p; - - if(!strcmp(ext_value_p->option_name, "name")) { - switch_ext_p = switch_ext_p->next; - continue; - } else if(!strcmp(ext_value_p->option_name, "port_id")) { - val_ptr[0] = (char*)ext_value_p->option_value; - } else if(!strcmp(ext_value_p->option_name, "buffer_limit")) { - val_ptr[1] = (char*)ext_value_p->option_value; - } else { - rv = -1; - break; - } - - parameter_length++; - switch_ext_p = switch_ext_p->next; - } - - return rv; -} - -static int -parse_qos_pttxbufnr(struct switch_val *val) -{ - struct switch_ext *switch_ext_p, *ext_value_p; - int rv = 0; - switch_ext_p = val->value.ext_val; - while(switch_ext_p) { - ext_value_p = switch_ext_p; - - if(!strcmp(ext_value_p->option_name, "name")) { - switch_ext_p = switch_ext_p->next; - continue; - } else if(!strcmp(ext_value_p->option_name, "port_id")) { - val_ptr[0] = (char*)ext_value_p->option_value; - } else if(!strcmp(ext_value_p->option_name, "number")) { - val_ptr[1] = (char*)ext_value_p->option_value; - } else { - rv = -1; - break; - } - - parameter_length++; - switch_ext_p = switch_ext_p->next; - } - - return rv; -} - -static int -parse_qos_ptrxbufnr(struct switch_val *val) -{ - struct switch_ext *switch_ext_p, *ext_value_p; - int rv = 0; - switch_ext_p = val->value.ext_val; - while(switch_ext_p) { - ext_value_p = switch_ext_p; - - if(!strcmp(ext_value_p->option_name, "name")) { - switch_ext_p = switch_ext_p->next; - continue; - } else if(!strcmp(ext_value_p->option_name, "port_id")) { - val_ptr[0] = (char*)ext_value_p->option_value; - } else if(!strcmp(ext_value_p->option_name, "number")) { - val_ptr[1] = (char*)ext_value_p->option_value; - } else { - rv = -1; - break; - } - - parameter_length++; - switch_ext_p = switch_ext_p->next; - } - - return rv; -} - -static int -parse_qos_ptreden(struct switch_val *val) -{ - struct switch_ext *switch_ext_p, *ext_value_p; - int rv = 0; - switch_ext_p = val->value.ext_val; - while(switch_ext_p) { - ext_value_p = switch_ext_p; - - if(!strcmp(ext_value_p->option_name, "name")) { - switch_ext_p = switch_ext_p->next; - continue; - } else if(!strcmp(ext_value_p->option_name, "port_id")) { - val_ptr[0] = (char*)ext_value_p->option_value; - } else if(!strcmp(ext_value_p->option_name, "red_status")) { - val_ptr[1] = (char*)ext_value_p->option_value; - } else { - rv = -1; - break; - } - - parameter_length++; - switch_ext_p = switch_ext_p->next; - } - - return rv; -} - -static int -parse_qos_ptmode(struct switch_val *val) -{ - struct switch_ext *switch_ext_p, *ext_value_p; - int rv = 0; - switch_ext_p = val->value.ext_val; - while(switch_ext_p) { - ext_value_p = switch_ext_p; - - if(!strcmp(ext_value_p->option_name, "name")) { - switch_ext_p = switch_ext_p->next; - continue; - } else if(!strcmp(ext_value_p->option_name, "port_id")) { - val_ptr[0] = (char*)ext_value_p->option_value; - } else if(!strcmp(ext_value_p->option_name, "mode")) { - val_ptr[1] = (char*)ext_value_p->option_value; - } else if(!strcmp(ext_value_p->option_name, "status")) { - val_ptr[2] = (char*)ext_value_p->option_value; - } else { - rv = -1; - break; - } - - parameter_length++; - switch_ext_p = switch_ext_p->next; - } - - return rv; -} - -static int -parse_qos_ptmodepri(struct switch_val *val) -{ - struct switch_ext *switch_ext_p, *ext_value_p; - int rv = 0; - switch_ext_p = val->value.ext_val; - while(switch_ext_p) { - ext_value_p = switch_ext_p; - - if(!strcmp(ext_value_p->option_name, "name")) { - switch_ext_p = switch_ext_p->next; - continue; - } else if(!strcmp(ext_value_p->option_name, "port_id")) { - val_ptr[0] = (char*)ext_value_p->option_value; - } else if(!strcmp(ext_value_p->option_name, "mode")) { - val_ptr[1] = (char*)ext_value_p->option_value; - } else if(!strcmp(ext_value_p->option_name, "priority")) { - val_ptr[2] = (char*)ext_value_p->option_value; - } else { - rv = -1; - break; - } - - parameter_length++; - switch_ext_p = switch_ext_p->next; - } - - return rv; -} - -static int -parse_qos_ptschmode(struct switch_val *val) -{ - struct switch_ext *switch_ext_p, *ext_value_p; - int rv = 0; - switch_ext_p = val->value.ext_val; - while(switch_ext_p) { - ext_value_p = switch_ext_p; - - if(!strcmp(ext_value_p->option_name, "name")) { - switch_ext_p = switch_ext_p->next; - continue; - } else if(!strcmp(ext_value_p->option_name, "port_id")) { - val_ptr[0] = (char*)ext_value_p->option_value; - } else if(!strcmp(ext_value_p->option_name, "mode")) { - val_ptr[1] = (char*)ext_value_p->option_value; - } else if(!strcmp(ext_value_p->option_name, "weight")) { - val_ptr[2] = (char*)ext_value_p->option_value; - } else { - rv = -1; - break; - } - - parameter_length++; - switch_ext_p = switch_ext_p->next; - } - - return rv; -} - -static int -parse_qos_ptdefaultspri(struct switch_val *val) -{ - struct switch_ext *switch_ext_p, *ext_value_p; - int rv = 0; - switch_ext_p = val->value.ext_val; - while(switch_ext_p) { - ext_value_p = switch_ext_p; - - if(!strcmp(ext_value_p->option_name, "name")) { - switch_ext_p = switch_ext_p->next; - continue; - } else if(!strcmp(ext_value_p->option_name, "port_id")) { - val_ptr[0] = (char*)ext_value_p->option_value; - } else if(!strcmp(ext_value_p->option_name, "stag_pri")) { - val_ptr[1] = (char*)ext_value_p->option_value; - } else { - rv = -1; - break; - } - - parameter_length++; - switch_ext_p = switch_ext_p->next; - } - - return rv; -} - -static int -parse_qos_ptdefaultcpri(struct switch_val *val) -{ - struct switch_ext *switch_ext_p, *ext_value_p; - int rv = 0; - switch_ext_p = val->value.ext_val; - while(switch_ext_p) { - ext_value_p = switch_ext_p; - - if(!strcmp(ext_value_p->option_name, "name")) { - switch_ext_p = switch_ext_p->next; - continue; - } else if(!strcmp(ext_value_p->option_name, "port_id")) { - val_ptr[0] = (char*)ext_value_p->option_value; - } else if(!strcmp(ext_value_p->option_name, "ctag_pri")) { - val_ptr[1] = (char*)ext_value_p->option_value; - } else { - rv = -1; - break; - } - - parameter_length++; - switch_ext_p = switch_ext_p->next; - } - - return rv; -} - -static int -parse_qos_ptfsprists(struct switch_val *val) -{ - struct switch_ext *switch_ext_p, *ext_value_p; - int rv = 0; - switch_ext_p = val->value.ext_val; - while(switch_ext_p) { - ext_value_p = switch_ext_p; - - if(!strcmp(ext_value_p->option_name, "name")) { - switch_ext_p = switch_ext_p->next; - continue; - } else if(!strcmp(ext_value_p->option_name, "port_id")) { - val_ptr[0] = (char*)ext_value_p->option_value; - } else if(!strcmp(ext_value_p->option_name, "force_stag_pri_status")) { - val_ptr[1] = (char*)ext_value_p->option_value; - } else { - rv = -1; - break; - } - - parameter_length++; - switch_ext_p = switch_ext_p->next; - } - - return rv; -} - -static int -parse_qos_ptfcprists(struct switch_val *val) -{ - struct switch_ext *switch_ext_p, *ext_value_p; - int rv = 0; - switch_ext_p = val->value.ext_val; - while(switch_ext_p) { - ext_value_p = switch_ext_p; - - if(!strcmp(ext_value_p->option_name, "name")) { - switch_ext_p = switch_ext_p->next; - continue; - } else if(!strcmp(ext_value_p->option_name, "port_id")) { - val_ptr[0] = (char*)ext_value_p->option_value; - } else if(!strcmp(ext_value_p->option_name, "force_ctag_pri_status")) { - val_ptr[1] = (char*)ext_value_p->option_value; - } else { - rv = -1; - break; - } - - parameter_length++; - switch_ext_p = switch_ext_p->next; - } - - return rv; -} - -static int -parse_qos_ptquremark(struct switch_val *val) -{ - struct switch_ext *switch_ext_p, *ext_value_p; - int rv = 0; - switch_ext_p = val->value.ext_val; - while(switch_ext_p) { - ext_value_p = switch_ext_p; - - if(!strcmp(ext_value_p->option_name, "name")) { - switch_ext_p = switch_ext_p->next; - continue; - } else if(!strcmp(ext_value_p->option_name, "port_id")) { - val_ptr[0] = (char*)ext_value_p->option_value; - } else if(!strcmp(ext_value_p->option_name, "queue_id")) { - val_ptr[1] = (char*)ext_value_p->option_value; - } else if(!strcmp(ext_value_p->option_name, "table_id")) { - val_ptr[2] = (char*)ext_value_p->option_value; - } else if(!strcmp(ext_value_p->option_name, "status")) { - val_ptr[3] = (char*)ext_value_p->option_value; - } else { - rv = -1; - break; - } - - parameter_length++; - switch_ext_p = switch_ext_p->next; - } - - return rv; -} - -static int -parse_qos_ptgroup(struct switch_val *val) -{ - struct switch_ext *switch_ext_p, *ext_value_p; - int rv = 0; - - switch_ext_p = val->value.ext_val; - while (switch_ext_p) { - ext_value_p = switch_ext_p; - - if (!strcmp(ext_value_p->option_name, "name")) { - switch_ext_p = switch_ext_p->next; - continue; - } else if (!strcmp(ext_value_p->option_name, "port_id")) { - val_ptr[0] = (char*)ext_value_p->option_value; - } else if (!strcmp(ext_value_p->option_name, "pcpgroup")) { - val_ptr[1] = (char*)ext_value_p->option_value; - } else if (!strcmp(ext_value_p->option_name, "dscpgroup")) { - val_ptr[2] = (char*)ext_value_p->option_value; - } else if (!strcmp(ext_value_p->option_name, "flowgroup")) { - val_ptr[3] = (char*)ext_value_p->option_value; - } else { - rv = -1; - break; - } - - parameter_length++; - switch_ext_p = switch_ext_p->next; - } - - return rv; -} - -static int -parse_qos_ptpri(struct switch_val *val) -{ - struct switch_ext *switch_ext_p, *ext_value_p; - int rv = 0; - - switch_ext_p = val->value.ext_val; - while (switch_ext_p) { - ext_value_p = switch_ext_p; - - if (!strcmp(ext_value_p->option_name, "name")) { - switch_ext_p = switch_ext_p->next; - continue; - } else if (!strcmp(ext_value_p->option_name, "port_id")) { - val_ptr[0] = (char*)ext_value_p->option_value; - } else if (!strcmp(ext_value_p->option_name, "pcpprec")) { - val_ptr[1] = (char*)ext_value_p->option_value; - } else if (!strcmp(ext_value_p->option_name, "dscpprec")) { - val_ptr[2] = (char*)ext_value_p->option_value; - } else if (!strcmp(ext_value_p->option_name, "preheaderprec")) { - val_ptr[3] = (char*)ext_value_p->option_value; - } else if (!strcmp(ext_value_p->option_name, "flowprec")) { - val_ptr[4] = (char*)ext_value_p->option_value; - } else if (!strcmp(ext_value_p->option_name, "aclprec")) { - val_ptr[5] = (char*)ext_value_p->option_value; - } else if (!strcmp(ext_value_p->option_name, "postaclprec")) { - val_ptr[6] = (char*)ext_value_p->option_value; - } else if (!strcmp(ext_value_p->option_name, "pcpprecforce")) { - val_ptr[7] = (char*)ext_value_p->option_value; - } else if (!strcmp(ext_value_p->option_name, "dscpprecforce")) { - val_ptr[8] = (char*)ext_value_p->option_value; - } else { - rv = -1; - break; - } - - parameter_length++; - switch_ext_p = switch_ext_p->next; - } - - return rv; -} - -static int -parse_qos_ptremark(struct switch_val *val) -{ - struct switch_ext *switch_ext_p, *ext_value_p; - int rv = 0; - - switch_ext_p = val->value.ext_val; - while (switch_ext_p) { - ext_value_p = switch_ext_p; - - if (!strcmp(ext_value_p->option_name, "name")) { - switch_ext_p = switch_ext_p->next; - continue; - } else if (!strcmp(ext_value_p->option_name, "port_id")) { - val_ptr[0] = (char*)ext_value_p->option_value; - } else if (!strcmp(ext_value_p->option_name, "pcp_change_en")) { - val_ptr[1] = (char*)ext_value_p->option_value; - } else if (!strcmp(ext_value_p->option_name, "dei_change_en")) { - val_ptr[2] = (char*)ext_value_p->option_value; - } else if (!strcmp(ext_value_p->option_name, "dscp_change_en")) { - val_ptr[3] = (char*)ext_value_p->option_value; - } else { - rv = -1; - break; - } - - parameter_length++; - switch_ext_p = switch_ext_p->next; - } - - return rv; -} -static int -parse_qos_pcpmap(struct switch_val *val) -{ - struct switch_ext *switch_ext_p, *ext_value_p; - int rv = 0; - - switch_ext_p = val->value.ext_val; - while (switch_ext_p) { - ext_value_p = switch_ext_p; - - if (!strcmp(ext_value_p->option_name, "name")) { - switch_ext_p = switch_ext_p->next; - continue; - } else if (!strcmp(ext_value_p->option_name, "group_id")) { - val_ptr[0] = (char*)ext_value_p->option_value; - } else if (!strcmp(ext_value_p->option_name, "pcp")) { - val_ptr[1] = (char*)ext_value_p->option_value; - } else if (!strcmp(ext_value_p->option_name, "internalpcp")) { - val_ptr[2] = (char*)ext_value_p->option_value; - } else if (!strcmp(ext_value_p->option_name, "internaldei")) { - val_ptr[3] = (char*)ext_value_p->option_value; - } else if (!strcmp(ext_value_p->option_name, "internalpri")) { - val_ptr[4] = (char*)ext_value_p->option_value; - } else if (!strcmp(ext_value_p->option_name, "internaldscp")) { - val_ptr[5] = (char*)ext_value_p->option_value; - } else if (!strcmp(ext_value_p->option_name, "internaldropprec")) { - val_ptr[6] = (char*)ext_value_p->option_value; - } else if (!strcmp(ext_value_p->option_name, "dscpmask")) { - val_ptr[7] = (char*)ext_value_p->option_value; - } else if (!strcmp(ext_value_p->option_name, "dscpen")) { - val_ptr[8] = (char*)ext_value_p->option_value; - } else if (!strcmp(ext_value_p->option_name, "pcpen")) { - val_ptr[9] = (char*)ext_value_p->option_value; - } else if (!strcmp(ext_value_p->option_name, "deien")) { - val_ptr[10] = (char*)ext_value_p->option_value; - } else if (!strcmp(ext_value_p->option_name, "prien")) { - val_ptr[11] = (char*)ext_value_p->option_value; - } else if (!strcmp(ext_value_p->option_name, "dpen")) { - val_ptr[12] = (char*)ext_value_p->option_value; - } else if (!strcmp(ext_value_p->option_name, "qosprec")) { - val_ptr[13] = (char*)ext_value_p->option_value; - } else { - rv = -1; - break; - } - - parameter_length++; - switch_ext_p = switch_ext_p->next; - } - - return rv; -} - -static int -parse_qos_flowmap(struct switch_val *val) -{ - struct switch_ext *switch_ext_p, *ext_value_p; - int rv = 0; - - switch_ext_p = val->value.ext_val; - while (switch_ext_p) { - ext_value_p = switch_ext_p; - - if (!strcmp(ext_value_p->option_name, "name")) { - switch_ext_p = switch_ext_p->next; - continue; - } else if (!strcmp(ext_value_p->option_name, "group_id")) { - val_ptr[0] = (char*)ext_value_p->option_value; - } else if (!strcmp(ext_value_p->option_name, "flow_id")) { - val_ptr[1] = (char*)ext_value_p->option_value; - } else if (!strcmp(ext_value_p->option_name, "internalpcp")) { - val_ptr[2] = (char*)ext_value_p->option_value; - } else if (!strcmp(ext_value_p->option_name, "internaldei")) { - val_ptr[3] = (char*)ext_value_p->option_value; - } else if (!strcmp(ext_value_p->option_name, "internalpri")) { - val_ptr[4] = (char*)ext_value_p->option_value; - } else if (!strcmp(ext_value_p->option_name, "internaldscp")) { - val_ptr[5] = (char*)ext_value_p->option_value; - } else if (!strcmp(ext_value_p->option_name, "internaldropprec")) { - val_ptr[6] = (char*)ext_value_p->option_value; - } else { - rv = -1; - break; - } - - parameter_length++; - switch_ext_p = switch_ext_p->next; - } - - return rv; -} - -static int -parse_qos_dscpmap(struct switch_val *val) -{ - struct switch_ext *switch_ext_p, *ext_value_p; - int rv = 0; - - switch_ext_p = val->value.ext_val; - while (switch_ext_p) { - ext_value_p = switch_ext_p; - - if (!strcmp(ext_value_p->option_name, "name")) { - switch_ext_p = switch_ext_p->next; - continue; - } else if (!strcmp(ext_value_p->option_name, "group_id")) { - val_ptr[0] = (char*)ext_value_p->option_value; - } else if (!strcmp(ext_value_p->option_name, "dscp")) { - val_ptr[1] = (char*)ext_value_p->option_value; - } else if (!strcmp(ext_value_p->option_name, "internalpcp")) { - val_ptr[2] = (char*)ext_value_p->option_value; - } else if (!strcmp(ext_value_p->option_name, "internaldei")) { - val_ptr[3] = (char*)ext_value_p->option_value; - } else if (!strcmp(ext_value_p->option_name, "internalpri")) { - val_ptr[4] = (char*)ext_value_p->option_value; - } else if (!strcmp(ext_value_p->option_name, "internaldscp")) { - val_ptr[5] = (char*)ext_value_p->option_value; - } else if (!strcmp(ext_value_p->option_name, "internaldropprec")) { - val_ptr[6] = (char*)ext_value_p->option_value; - } else { - rv = -1; - break; - } - - parameter_length++; - switch_ext_p = switch_ext_p->next; - } - - return rv; -} - -static int -parse_qos_qscheduler(struct switch_val *val) -{ - struct switch_ext *switch_ext_p, *ext_value_p; - int rv = 0; - - switch_ext_p = val->value.ext_val; - while (switch_ext_p) { - ext_value_p = switch_ext_p; - - if (!strcmp(ext_value_p->option_name, "name")) { - switch_ext_p = switch_ext_p->next; - continue; - } else if (!strcmp(ext_value_p->option_name, "node_id")) { - val_ptr[0] = (char*)ext_value_p->option_value; - } else if (!strcmp(ext_value_p->option_name, "level")) { - val_ptr[1] = (char*)ext_value_p->option_value; - } else if (!strcmp(ext_value_p->option_name, "port_id")) { - val_ptr[2] = (char*)ext_value_p->option_value; - } else if (!strcmp(ext_value_p->option_name, "spid")) { - val_ptr[3] = (char*)ext_value_p->option_value; - } else if (!strcmp(ext_value_p->option_name, "edrrpri")) { - val_ptr[4] = (char*)ext_value_p->option_value; - } else if (!strcmp(ext_value_p->option_name, "cdrrpri")) { - val_ptr[5] = (char*)ext_value_p->option_value; - } else if (!strcmp(ext_value_p->option_name, "cdrr_id")) { - val_ptr[6] = (char*)ext_value_p->option_value; - } else if (!strcmp(ext_value_p->option_name, "edrr_id")) { - val_ptr[7] = (char*)ext_value_p->option_value; - } else if (!strcmp(ext_value_p->option_name, "edrrweight")) { - val_ptr[8] = (char*)ext_value_p->option_value; - } else if (!strcmp(ext_value_p->option_name, "cdrrweight")) { - val_ptr[9] = (char*)ext_value_p->option_value; - } else if (!strcmp(ext_value_p->option_name, "cdrrunit")) { - val_ptr[10] = (char*)ext_value_p->option_value; - } else if (!strcmp(ext_value_p->option_name, "edrrunit")) { - val_ptr[11] = (char*)ext_value_p->option_value; - } else if (!strcmp(ext_value_p->option_name, "drr_frame_mode")) { - val_ptr[12] = (char*)ext_value_p->option_value; - } else { - rv = -1; - break; - } - - parameter_length++; - switch_ext_p = switch_ext_p->next; - } - - return rv; -} - -static int -parse_qos_ringqueue(struct switch_val *val) -{ - struct switch_ext *switch_ext_p, *ext_value_p; - int rv = 0; - - switch_ext_p = val->value.ext_val; - while (switch_ext_p) { - ext_value_p = switch_ext_p; - - if (!strcmp(ext_value_p->option_name, "name")) { - switch_ext_p = switch_ext_p->next; - continue; - } else if (!strcmp(ext_value_p->option_name, "ring_id")) { - val_ptr[0] = (char*)ext_value_p->option_value; - } else if (!strcmp(ext_value_p->option_name, "queuebmp0")) { - val_ptr[1] = (char*)ext_value_p->option_value; - } else if (!strcmp(ext_value_p->option_name, "queuebmp1")) { - val_ptr[2] = (char*)ext_value_p->option_value; - } else if (!strcmp(ext_value_p->option_name, "queuebmp2")) { - val_ptr[3] = (char*)ext_value_p->option_value; - } else if (!strcmp(ext_value_p->option_name, "queuebmp3")) { - val_ptr[4] = (char*)ext_value_p->option_value; - } else if (!strcmp(ext_value_p->option_name, "queuebmp4")) { - val_ptr[5] = (char*)ext_value_p->option_value; - } else if (!strcmp(ext_value_p->option_name, "queuebmp5")) { - val_ptr[6] = (char*)ext_value_p->option_value; - } else if (!strcmp(ext_value_p->option_name, "queuebmp6")) { - val_ptr[7] = (char*)ext_value_p->option_value; - } else if (!strcmp(ext_value_p->option_name, "queuebmp7")) { - val_ptr[8] = (char*)ext_value_p->option_value; - } else if (!strcmp(ext_value_p->option_name, "queuebmp8")) { - val_ptr[9] = (char*)ext_value_p->option_value; - } else if (!strcmp(ext_value_p->option_name, "queuebmp9")) { - val_ptr[10] = (char*)ext_value_p->option_value; - } else { - rv = -1; - break; - } - - parameter_length++; - switch_ext_p = switch_ext_p->next; - } - - return rv; -} - -static int -parse_qos_dequeue(struct switch_val *val) -{ - struct switch_ext *switch_ext_p, *ext_value_p; - int rv = 0; - - switch_ext_p = val->value.ext_val; - while (switch_ext_p) { - ext_value_p = switch_ext_p; - - if (!strcmp(ext_value_p->option_name, "name")) { - switch_ext_p = switch_ext_p->next; - continue; - } else if (!strcmp(ext_value_p->option_name, "queue_id")) { - val_ptr[0] = (char*)ext_value_p->option_value; - } else if (!strcmp(ext_value_p->option_name, "dequeue_ctrl_en")) { - val_ptr[1] = (char*)ext_value_p->option_value; - } else { - rv = -1; - break; - } - - parameter_length++; - switch_ext_p = switch_ext_p->next; - } - - return rv; -} - -static int -parse_qos_portscheduler(struct switch_val *val) -{ - struct switch_ext *switch_ext_p, *ext_value_p; - int rv = 0; - - switch_ext_p = val->value.ext_val; - while (switch_ext_p) { - ext_value_p = switch_ext_p; - - if (!strcmp(ext_value_p->option_name, "name")) { - switch_ext_p = switch_ext_p->next; - continue; - } else if (!strcmp(ext_value_p->option_name, "port_id")) { - val_ptr[0] = (char*)ext_value_p->option_value; - } else { - rv = -1; - break; - } - - parameter_length++; - switch_ext_p = switch_ext_p->next; - } - - return rv; -} - -#endif -#endif - -#ifdef IN_COSMAP -static int -parse_cos_mappri2q(struct switch_val *val) -{ - struct switch_ext *switch_ext_p, *ext_value_p; - int rv = 0; - switch_ext_p = val->value.ext_val; - while(switch_ext_p) { - ext_value_p = switch_ext_p; - - if(!strcmp(ext_value_p->option_name, "name")) { - switch_ext_p = switch_ext_p->next; - continue; - } else if(!strcmp(ext_value_p->option_name, "pri")) { - val_ptr[0] = (char*)ext_value_p->option_value; - } else if(!strcmp(ext_value_p->option_name, "queue")) { - val_ptr[1] = (char*)ext_value_p->option_value; - } else { - rv = -1; - break; - } - - parameter_length++; - switch_ext_p = switch_ext_p->next; - } - - return rv; -} - -static int -parse_cos_mappri2ehq(struct switch_val *val) -{ - struct switch_ext *switch_ext_p, *ext_value_p; - int rv = 0; - switch_ext_p = val->value.ext_val; - while(switch_ext_p) { - ext_value_p = switch_ext_p; - - if(!strcmp(ext_value_p->option_name, "name")) { - switch_ext_p = switch_ext_p->next; - continue; - } else if(!strcmp(ext_value_p->option_name, "pri")) { - val_ptr[0] = (char*)ext_value_p->option_value; - } else if(!strcmp(ext_value_p->option_name, "enhance_queue")) { - val_ptr[1] = (char*)ext_value_p->option_value; - } else { - rv = -1; - break; - } - - parameter_length++; - switch_ext_p = switch_ext_p->next; - } - - return rv; -} - -#ifndef IN_COSMAP_MINI -static int -parse_cos_mapdscp2pri(struct switch_val *val) -{ - struct switch_ext *switch_ext_p, *ext_value_p; - int rv = 0; - switch_ext_p = val->value.ext_val; - while(switch_ext_p) { - ext_value_p = switch_ext_p; - - if(!strcmp(ext_value_p->option_name, "name")) { - switch_ext_p = switch_ext_p->next; - continue; - } else if(!strcmp(ext_value_p->option_name, "dscp")) { - val_ptr[0] = (char*)ext_value_p->option_value; - } else if(!strcmp(ext_value_p->option_name, "pri")) { - val_ptr[1] = (char*)ext_value_p->option_value; - } else { - rv = -1; - break; - } - - parameter_length++; - switch_ext_p = switch_ext_p->next; - } - - return rv; -} - -static int -parse_cos_mapdscp2dp(struct switch_val *val) -{ - struct switch_ext *switch_ext_p, *ext_value_p; - int rv = 0; - switch_ext_p = val->value.ext_val; - while(switch_ext_p) { - ext_value_p = switch_ext_p; - - if(!strcmp(ext_value_p->option_name, "name")) { - switch_ext_p = switch_ext_p->next; - continue; - } else if(!strcmp(ext_value_p->option_name, "dscp")) { - val_ptr[0] = (char*)ext_value_p->option_value; - } else if(!strcmp(ext_value_p->option_name, "cfi")) { - val_ptr[1] = (char*)ext_value_p->option_value; - } else { - rv = -1; - break; - } - - parameter_length++; - switch_ext_p = switch_ext_p->next; - } - - return rv; -} - -static int -parse_cos_mapup2pri(struct switch_val *val) -{ - struct switch_ext *switch_ext_p, *ext_value_p; - int rv = 0; - switch_ext_p = val->value.ext_val; - while(switch_ext_p) { - ext_value_p = switch_ext_p; - - if(!strcmp(ext_value_p->option_name, "name")) { - switch_ext_p = switch_ext_p->next; - continue; - } else if(!strcmp(ext_value_p->option_name, "up")) { - val_ptr[0] = (char*)ext_value_p->option_value; - } else if(!strcmp(ext_value_p->option_name, "pri")) { - val_ptr[1] = (char*)ext_value_p->option_value; - } else { - rv = -1; - break; - } - - parameter_length++; - switch_ext_p = switch_ext_p->next; - } - - return rv; -} - -static int -parse_cos_mapup2dp(struct switch_val *val) -{ - struct switch_ext *switch_ext_p, *ext_value_p; - int rv = 0; - switch_ext_p = val->value.ext_val; - while(switch_ext_p) { - ext_value_p = switch_ext_p; - - if(!strcmp(ext_value_p->option_name, "name")) { - switch_ext_p = switch_ext_p->next; - continue; - } else if(!strcmp(ext_value_p->option_name, "up")) { - val_ptr[0] = (char*)ext_value_p->option_value; - } else if(!strcmp(ext_value_p->option_name, "cfi")) { - val_ptr[1] = (char*)ext_value_p->option_value; - } else { - rv = -1; - break; - } - - parameter_length++; - switch_ext_p = switch_ext_p->next; - } - - return rv; -} - -static int -parse_cos_mapdscp2ehpri(struct switch_val *val) -{ - struct switch_ext *switch_ext_p, *ext_value_p; - int rv = 0; - switch_ext_p = val->value.ext_val; - while(switch_ext_p) { - ext_value_p = switch_ext_p; - - if(!strcmp(ext_value_p->option_name, "name")) { - switch_ext_p = switch_ext_p->next; - continue; - } else if(!strcmp(ext_value_p->option_name, "dscp")) { - val_ptr[0] = (char*)ext_value_p->option_value; - } else if(!strcmp(ext_value_p->option_name, "pri")) { - val_ptr[1] = (char*)ext_value_p->option_value; - } else { - rv = -1; - break; - } - - parameter_length++; - switch_ext_p = switch_ext_p->next; - } - - return rv; -} - -static int -parse_cos_mapdscp2ehdp(struct switch_val *val) -{ - struct switch_ext *switch_ext_p, *ext_value_p; - int rv = 0; - switch_ext_p = val->value.ext_val; - while(switch_ext_p) { - ext_value_p = switch_ext_p; - - if(!strcmp(ext_value_p->option_name, "name")) { - switch_ext_p = switch_ext_p->next; - continue; - } else if(!strcmp(ext_value_p->option_name, "dscp")) { - val_ptr[0] = (char*)ext_value_p->option_value; - } else if(!strcmp(ext_value_p->option_name, "cfi")) { - val_ptr[1] = (char*)ext_value_p->option_value; - } else { - rv = -1; - break; - } - - parameter_length++; - switch_ext_p = switch_ext_p->next; - } - - return rv; -} - -static int -parse_cos_mapup2ehpri(struct switch_val *val) -{ - struct switch_ext *switch_ext_p, *ext_value_p; - int rv = 0; - switch_ext_p = val->value.ext_val; - while(switch_ext_p) { - ext_value_p = switch_ext_p; - - if(!strcmp(ext_value_p->option_name, "name")) { - switch_ext_p = switch_ext_p->next; - continue; - } else if(!strcmp(ext_value_p->option_name, "up")) { - val_ptr[0] = (char*)ext_value_p->option_value; - } else if(!strcmp(ext_value_p->option_name, "pri")) { - val_ptr[1] = (char*)ext_value_p->option_value; - } else { - rv = -1; - break; - } - - parameter_length++; - switch_ext_p = switch_ext_p->next; - } - - return rv; -} - -static int -parse_cos_mapup2ehdp(struct switch_val *val) -{ - struct switch_ext *switch_ext_p, *ext_value_p; - int rv = 0; - switch_ext_p = val->value.ext_val; - while(switch_ext_p) { - ext_value_p = switch_ext_p; - - if(!strcmp(ext_value_p->option_name, "name")) { - switch_ext_p = switch_ext_p->next; - continue; - } else if(!strcmp(ext_value_p->option_name, "up")) { - val_ptr[0] = (char*)ext_value_p->option_value; - } else if(!strcmp(ext_value_p->option_name, "cfi")) { - val_ptr[1] = (char*)ext_value_p->option_value; - } else { - rv = -1; - break; - } - - parameter_length++; - switch_ext_p = switch_ext_p->next; - } - - return rv; -} - -static int -parse_cos_mapegremark(struct switch_val *val) -{ - struct switch_ext *switch_ext_p, *ext_value_p; - int rv = 0; - switch_ext_p = val->value.ext_val; - while(switch_ext_p) { - ext_value_p = switch_ext_p; - - if(!strcmp(ext_value_p->option_name, "name")) { - switch_ext_p = switch_ext_p->next; - continue; - } else if(!strcmp(ext_value_p->option_name, "id")) { - val_ptr[0] = (char*)ext_value_p->option_value; - } else if(!strcmp(ext_value_p->option_name, "remark_dscp")) { - val_ptr[1] = (char*)ext_value_p->option_value; - } else if(!strcmp(ext_value_p->option_name, "remark_up")) { - val_ptr[2] = (char*)ext_value_p->option_value; - } else if(!strcmp(ext_value_p->option_name, "remark_dei")) { - val_ptr[3] = (char*)ext_value_p->option_value; - } else if(!strcmp(ext_value_p->option_name, "green_dscp")) { - val_ptr[4] = (char*)ext_value_p->option_value; - } else if(!strcmp(ext_value_p->option_name, "yellow_dscp")) { - val_ptr[5] = (char*)ext_value_p->option_value; - } else if(!strcmp(ext_value_p->option_name, "green_up")) { - val_ptr[6] = (char*)ext_value_p->option_value; - } else if(!strcmp(ext_value_p->option_name, "yellow_up")) { - val_ptr[7] = (char*)ext_value_p->option_value; - } else if(!strcmp(ext_value_p->option_name, "green_dei")) { - val_ptr[8] = (char*)ext_value_p->option_value; - } else if(!strcmp(ext_value_p->option_name, "yellow_dei")) { - val_ptr[9] = (char*)ext_value_p->option_value; - } else { - rv = -1; - break; - } - - parameter_length++; - switch_ext_p = switch_ext_p->next; - } - - return rv; -} -#endif -#endif - -#ifdef IN_RATE -static int -parse_rate_portpolicer(struct switch_val *val) -{ - struct switch_ext *switch_ext_p, *ext_value_p; - int rv = 0; - switch_ext_p = val->value.ext_val; - while(switch_ext_p) { - ext_value_p = switch_ext_p; - - if(!strcmp(ext_value_p->option_name, "name")) { - switch_ext_p = switch_ext_p->next; - continue; - } else if(!strcmp(ext_value_p->option_name, "port_id")) { - val_ptr[0] = (char*)ext_value_p->option_value; - } else if(!strcmp(ext_value_p->option_name, "combine_enable")) { - val_ptr[1] = (char*)ext_value_p->option_value; - } else if(!strcmp(ext_value_p->option_name, "byte_based")) { - val_ptr[2] = (char*)ext_value_p->option_value; - } else if(!strcmp(ext_value_p->option_name, "couple_flag")) { - val_ptr[3] = (char*)ext_value_p->option_value; - } else if(!strcmp(ext_value_p->option_name, "color_aware")) { - val_ptr[4] = (char*)ext_value_p->option_value; - } else if(!strcmp(ext_value_p->option_name, "deficit_flag")) { - val_ptr[5] = (char*)ext_value_p->option_value; - } else if(!strcmp(ext_value_p->option_name, "c_bucket_enable")) { - val_ptr[6] = (char*)ext_value_p->option_value; - } else if(!strcmp(ext_value_p->option_name, "cir")) { - val_ptr[7] = (char*)ext_value_p->option_value; - } else if(!strcmp(ext_value_p->option_name, "cbs")) { - val_ptr[8] = (char*)ext_value_p->option_value; - } else if(!strcmp(ext_value_p->option_name, "c_rate_flag")) { - val_ptr[9] = (char*)ext_value_p->option_value; - } else if(!strcmp(ext_value_p->option_name, "c_meter_interval")) { - val_ptr[10] = (char*)ext_value_p->option_value; - } else if(!strcmp(ext_value_p->option_name, "e_bucket_enable")) { - val_ptr[11] = (char*)ext_value_p->option_value; - } else if(!strcmp(ext_value_p->option_name, "eir")) { - val_ptr[12] = (char*)ext_value_p->option_value; - } else if(!strcmp(ext_value_p->option_name, "ebs")) { - val_ptr[13] = (char*)ext_value_p->option_value; - } else if(!strcmp(ext_value_p->option_name, "e_rate_flag")) { - val_ptr[14] = (char*)ext_value_p->option_value; - } else if(!strcmp(ext_value_p->option_name, "e_meter_interval")) { - val_ptr[15] = (char*)ext_value_p->option_value; - } else { - rv = -1; - break; - } - - parameter_length++; - switch_ext_p = switch_ext_p->next; - } - - return rv; -} - -static int -parse_rate_portshaper(struct switch_val *val) -{ - struct switch_ext *switch_ext_p, *ext_value_p; - int rv = 0; - switch_ext_p = val->value.ext_val; - while(switch_ext_p) { - ext_value_p = switch_ext_p; - - if(!strcmp(ext_value_p->option_name, "name")) { - switch_ext_p = switch_ext_p->next; - continue; - } else if(!strcmp(ext_value_p->option_name, "port_id")) { - val_ptr[0] = (char*)ext_value_p->option_value; - } else if(!strcmp(ext_value_p->option_name, "status")) { - val_ptr[1] = (char*)ext_value_p->option_value; - } else if(!strcmp(ext_value_p->option_name, "byte_based")) { - val_ptr[2] = (char*)ext_value_p->option_value; - } else if(!strcmp(ext_value_p->option_name, "cir")) { - val_ptr[3] = (char*)ext_value_p->option_value; - } else if(!strcmp(ext_value_p->option_name, "cbs")) { - val_ptr[4] = (char*)ext_value_p->option_value; - } else if(!strcmp(ext_value_p->option_name, "eir")) { - val_ptr[5] = (char*)ext_value_p->option_value; - } else if(!strcmp(ext_value_p->option_name, "ebs")) { - val_ptr[6] = (char*)ext_value_p->option_value; - } else { - rv = -1; - break; - } - - parameter_length++; - switch_ext_p = switch_ext_p->next; - } - - return rv; -} - -static int -parse_rate_queueshaper(struct switch_val *val) -{ - struct switch_ext *switch_ext_p, *ext_value_p; - int rv = 0; - switch_ext_p = val->value.ext_val; - while(switch_ext_p) { - ext_value_p = switch_ext_p; - - if(!strcmp(ext_value_p->option_name, "name")) { - switch_ext_p = switch_ext_p->next; - continue; - } else if(!strcmp(ext_value_p->option_name, "port_id")) { - val_ptr[0] = (char*)ext_value_p->option_value; - } else if(!strcmp(ext_value_p->option_name, "queue_id")) { - val_ptr[1] = (char*)ext_value_p->option_value; - } else if(!strcmp(ext_value_p->option_name, "status")) { - val_ptr[2] = (char*)ext_value_p->option_value; - } else if(!strcmp(ext_value_p->option_name, "byte_based")) { - val_ptr[3] = (char*)ext_value_p->option_value; - } else if(!strcmp(ext_value_p->option_name, "cir")) { - val_ptr[4] = (char*)ext_value_p->option_value; - } else if(!strcmp(ext_value_p->option_name, "cbs")) { - val_ptr[5] = (char*)ext_value_p->option_value; - } else if(!strcmp(ext_value_p->option_name, "eir")) { - val_ptr[6] = (char*)ext_value_p->option_value; - } else if(!strcmp(ext_value_p->option_name, "ebs")) { - val_ptr[7] = (char*)ext_value_p->option_value; - } else { - rv = -1; - break; - } - - parameter_length++; - switch_ext_p = switch_ext_p->next; - } - - return rv; -} - -static int -parse_rate_aclpolicer(struct switch_val *val) -{ - struct switch_ext *switch_ext_p, *ext_value_p; - int rv = 0; - switch_ext_p = val->value.ext_val; - while(switch_ext_p) { - ext_value_p = switch_ext_p; - - if(!strcmp(ext_value_p->option_name, "name")) { - switch_ext_p = switch_ext_p->next; - continue; - } else if(!strcmp(ext_value_p->option_name, "policer_id")) { - val_ptr[0] = (char*)ext_value_p->option_value; - } else if(!strcmp(ext_value_p->option_name, "counter_mode")) { - val_ptr[1] = (char*)ext_value_p->option_value; - } else if(!strcmp(ext_value_p->option_name, "byte_based")) { - val_ptr[2] = (char*)ext_value_p->option_value; - } else if(!strcmp(ext_value_p->option_name, "couple_flag")) { - val_ptr[3] = (char*)ext_value_p->option_value; - } else if(!strcmp(ext_value_p->option_name, "color_aware")) { - val_ptr[4] = (char*)ext_value_p->option_value; - } else if(!strcmp(ext_value_p->option_name, "deficit_flag")) { - val_ptr[5] = (char*)ext_value_p->option_value; - } else if(!strcmp(ext_value_p->option_name, "cir")) { - val_ptr[6] = (char*)ext_value_p->option_value; - } else if(!strcmp(ext_value_p->option_name, "cbs")) { - val_ptr[7] = (char*)ext_value_p->option_value; - } else if(!strcmp(ext_value_p->option_name, "eir")) { - val_ptr[8] = (char*)ext_value_p->option_value; - } else if(!strcmp(ext_value_p->option_name, "ebs")) { - val_ptr[9] = (char*)ext_value_p->option_value; - } else if(!strcmp(ext_value_p->option_name, "meter_interval")) { - val_ptr[10] = (char*)ext_value_p->option_value; - } else { - rv = -1; - break; - } - - parameter_length++; - switch_ext_p = switch_ext_p->next; - } - - return rv; -} - -static int -parse_rate_ptaddratebyte(struct switch_val *val) -{ - struct switch_ext *switch_ext_p, *ext_value_p; - int rv = 0; - switch_ext_p = val->value.ext_val; - while(switch_ext_p) { - ext_value_p = switch_ext_p; - - if(!strcmp(ext_value_p->option_name, "name")) { - switch_ext_p = switch_ext_p->next; - continue; - } else if(!strcmp(ext_value_p->option_name, "port_id")) { - val_ptr[0] = (char*)ext_value_p->option_value; - } else if(!strcmp(ext_value_p->option_name, "add_rate_bytes")) { - val_ptr[1] = (char*)ext_value_p->option_value; - } else { - rv = -1; - break; - } - - parameter_length++; - switch_ext_p = switch_ext_p->next; - } - - return rv; -} - -static int -parse_rate_ptgolflowen(struct switch_val *val) -{ - struct switch_ext *switch_ext_p, *ext_value_p; - int rv = 0; - switch_ext_p = val->value.ext_val; - while(switch_ext_p) { - ext_value_p = switch_ext_p; - - if(!strcmp(ext_value_p->option_name, "name")) { - switch_ext_p = switch_ext_p->next; - continue; - } else if(!strcmp(ext_value_p->option_name, "port_id")) { - val_ptr[0] = (char*)ext_value_p->option_value; - } else if(!strcmp(ext_value_p->option_name, "golbal_flow_control_status")) { - val_ptr[1] = (char*)ext_value_p->option_value; - } else { - rv = -1; - break; - } - - parameter_length++; - switch_ext_p = switch_ext_p->next; - } - - return rv; -} -#endif - -#ifdef IN_PORTCONTROL -#ifndef IN_PORTCONTROL_MINI -static int -parse_port_duplex(struct switch_val *val) -{ - struct switch_ext *switch_ext_p, *ext_value_p; - int rv = 0; - switch_ext_p = val->value.ext_val; - while(switch_ext_p) { - ext_value_p = switch_ext_p; - - if(!strcmp(ext_value_p->option_name, "name")) { - switch_ext_p = switch_ext_p->next; - continue; - } else if(!strcmp(ext_value_p->option_name, "port_id")) { - val_ptr[0] = (char*)ext_value_p->option_value; - } else if(!strcmp(ext_value_p->option_name, "duplex")) { - val_ptr[1] = (char*)ext_value_p->option_value; - } else { - rv = -1; - break; - } - - parameter_length++; - switch_ext_p = switch_ext_p->next; - } - - return rv; -} - -static int -parse_port_speed(struct switch_val *val) -{ - struct switch_ext *switch_ext_p, *ext_value_p; - int rv = 0; - switch_ext_p = val->value.ext_val; - while(switch_ext_p) { - ext_value_p = switch_ext_p; - - if(!strcmp(ext_value_p->option_name, "name")) { - switch_ext_p = switch_ext_p->next; - continue; - } else if(!strcmp(ext_value_p->option_name, "port_id")) { - val_ptr[0] = (char*)ext_value_p->option_value; - } else if(!strcmp(ext_value_p->option_name, "speed")) { - val_ptr[1] = (char*)ext_value_p->option_value; - } else { - rv = -1; - break; - } - - parameter_length++; - switch_ext_p = switch_ext_p->next; - } - - return rv; -} - -static int -parse_port_autoadv(struct switch_val *val) -{ - struct switch_ext *switch_ext_p, *ext_value_p; - int rv = 0; - switch_ext_p = val->value.ext_val; - while(switch_ext_p) { - ext_value_p = switch_ext_p; - - if(!strcmp(ext_value_p->option_name, "name")) { - switch_ext_p = switch_ext_p->next; - continue; - } else if(!strcmp(ext_value_p->option_name, "port_id")) { - val_ptr[0] = (char*)ext_value_p->option_value; - } else if(!strcmp(ext_value_p->option_name, "auto_adv")) { - val_ptr[1] = (char*)ext_value_p->option_value; - } else { - rv = -1; - break; - } - - parameter_length++; - switch_ext_p = switch_ext_p->next; - } - - return rv; -} - -static int -parse_port_autonegenable(struct switch_val *val) -{ - struct switch_ext *switch_ext_p, *ext_value_p; - int rv = 0; - switch_ext_p = val->value.ext_val; - while(switch_ext_p) { - ext_value_p = switch_ext_p; - - if(!strcmp(ext_value_p->option_name, "name")) { - switch_ext_p = switch_ext_p->next; - continue; - } else if(!strcmp(ext_value_p->option_name, "port_id")) { - val_ptr[0] = (char*)ext_value_p->option_value; - } else { - rv = -1; - break; - } - - parameter_length++; - switch_ext_p = switch_ext_p->next; - } - - return rv; -} - -static int -parse_port_autonegrestart(struct switch_val *val) -{ - struct switch_ext *switch_ext_p, *ext_value_p; - int rv = 0; - switch_ext_p = val->value.ext_val; - while(switch_ext_p) { - ext_value_p = switch_ext_p; - - if(!strcmp(ext_value_p->option_name, "name")) { - switch_ext_p = switch_ext_p->next; - continue; - } else if(!strcmp(ext_value_p->option_name, "port_id")) { - val_ptr[0] = (char*)ext_value_p->option_value; - } else { - rv = -1; - break; - } - - parameter_length++; - switch_ext_p = switch_ext_p->next; - } - - return rv; -} -#endif -static int -parse_port_txhdr(struct switch_val *val) -{ - struct switch_ext *switch_ext_p, *ext_value_p; - int rv = 0; - switch_ext_p = val->value.ext_val; - while(switch_ext_p) { - ext_value_p = switch_ext_p; - - if(!strcmp(ext_value_p->option_name, "name")) { - switch_ext_p = switch_ext_p->next; - continue; - } else if(!strcmp(ext_value_p->option_name, "port_id")) { - val_ptr[0] = (char*)ext_value_p->option_value; - } else if(!strcmp(ext_value_p->option_name, "tx_frame_atheros_header_tag_status")) { - val_ptr[1] = (char*)ext_value_p->option_value; - } else { - rv = -1; - break; - } - - parameter_length++; - switch_ext_p = switch_ext_p->next; - } - - return rv; -} - -static int -parse_port_rxhdr(struct switch_val *val) -{ - struct switch_ext *switch_ext_p, *ext_value_p; - int rv = 0; - switch_ext_p = val->value.ext_val; - while(switch_ext_p) { - ext_value_p = switch_ext_p; - - if(!strcmp(ext_value_p->option_name, "name")) { - switch_ext_p = switch_ext_p->next; - continue; - } else if(!strcmp(ext_value_p->option_name, "port_id")) { - val_ptr[0] = (char*)ext_value_p->option_value; - } else if(!strcmp(ext_value_p->option_name, "rx_frame_atheros_header_tag_status")) { - val_ptr[1] = (char*)ext_value_p->option_value; - } else { - rv = -1; - break; - } - - parameter_length++; - switch_ext_p = switch_ext_p->next; - } - - return rv; -} - -static int -parse_port_hdrtype(struct switch_val *val) -{ - struct switch_ext *switch_ext_p, *ext_value_p; - int rv = 0; - switch_ext_p = val->value.ext_val; - while(switch_ext_p) { - ext_value_p = switch_ext_p; - - if(!strcmp(ext_value_p->option_name, "name")) { - switch_ext_p = switch_ext_p->next; - continue; - } else if(!strcmp(ext_value_p->option_name, "atheros_header_tag_status")) { - val_ptr[0] = (char*)ext_value_p->option_value; - } else if(!strcmp(ext_value_p->option_name, "atheros_header_tag_type")) { - val_ptr[1] = (char*)ext_value_p->option_value; - } else { - rv = -1; - break; - } - - parameter_length++; - switch_ext_p = switch_ext_p->next; - } - - return rv; -} -#ifndef IN_PORTCONTROL_MINI -static int -parse_port_flowctrl(struct switch_val *val) -{ - struct switch_ext *switch_ext_p, *ext_value_p; - int rv = 0; - switch_ext_p = val->value.ext_val; - while(switch_ext_p) { - ext_value_p = switch_ext_p; - - if(!strcmp(ext_value_p->option_name, "name")) { - switch_ext_p = switch_ext_p->next; - continue; - } else if(!strcmp(ext_value_p->option_name, "port_id")) { - val_ptr[0] = (char*)ext_value_p->option_value; - } else if(!strcmp(ext_value_p->option_name, "flow_control_status")) { - val_ptr[1] = (char*)ext_value_p->option_value; - } else { - rv = -1; - break; - } - - parameter_length++; - switch_ext_p = switch_ext_p->next; - } - - return rv; -} - -static int -parse_port_flowctrlforcemode(struct switch_val *val) -{ - struct switch_ext *switch_ext_p, *ext_value_p; - int rv = 0; - switch_ext_p = val->value.ext_val; - while(switch_ext_p) { - ext_value_p = switch_ext_p; - - if(!strcmp(ext_value_p->option_name, "name")) { - switch_ext_p = switch_ext_p->next; - continue; - } else if(!strcmp(ext_value_p->option_name, "port_id")) { - val_ptr[0] = (char*)ext_value_p->option_value; - } else if(!strcmp(ext_value_p->option_name, "flow_control_force_mode_status")) { - val_ptr[1] = (char*)ext_value_p->option_value; - } else { - rv = -1; - break; - } - - parameter_length++; - switch_ext_p = switch_ext_p->next; - } - - return rv; -} - -static int -parse_port_powersave(struct switch_val *val) -{ - struct switch_ext *switch_ext_p, *ext_value_p; - int rv = 0; - switch_ext_p = val->value.ext_val; - while(switch_ext_p) { - ext_value_p = switch_ext_p; - - if(!strcmp(ext_value_p->option_name, "name")) { - switch_ext_p = switch_ext_p->next; - continue; - } else if(!strcmp(ext_value_p->option_name, "port_id")) { - val_ptr[0] = (char*)ext_value_p->option_value; - } else if(!strcmp(ext_value_p->option_name, "power_save_status")) { - val_ptr[1] = (char*)ext_value_p->option_value; - } else { - rv = -1; - break; - } - - parameter_length++; - switch_ext_p = switch_ext_p->next; - } - - return rv; -} - -static int -parse_port_hibernate(struct switch_val *val) -{ - struct switch_ext *switch_ext_p, *ext_value_p; - int rv = 0; - switch_ext_p = val->value.ext_val; - while(switch_ext_p) { - ext_value_p = switch_ext_p; - - if(!strcmp(ext_value_p->option_name, "name")) { - switch_ext_p = switch_ext_p->next; - continue; - } else if(!strcmp(ext_value_p->option_name, "port_id")) { - val_ptr[0] = (char*)ext_value_p->option_value; - } else if(!strcmp(ext_value_p->option_name, "hibernate_status")) { - val_ptr[1] = (char*)ext_value_p->option_value; - } else { - rv = -1; - break; - } - - parameter_length++; - switch_ext_p = switch_ext_p->next; - } - - return rv; -} - -static int -parse_port_txmacstatus(struct switch_val *val) -{ - struct switch_ext *switch_ext_p, *ext_value_p; - int rv = 0; - switch_ext_p = val->value.ext_val; - while(switch_ext_p) { - ext_value_p = switch_ext_p; - - if(!strcmp(ext_value_p->option_name, "name")) { - switch_ext_p = switch_ext_p->next; - continue; - } else if(!strcmp(ext_value_p->option_name, "port_id")) { - val_ptr[0] = (char*)ext_value_p->option_value; - } else if(!strcmp(ext_value_p->option_name, "tx_mac_status")) { - val_ptr[1] = (char*)ext_value_p->option_value; - } else { - rv = -1; - break; - } - - parameter_length++; - switch_ext_p = switch_ext_p->next; - } - - return rv; -} - -static int -parse_port_rxmacstatus(struct switch_val *val) -{ - struct switch_ext *switch_ext_p, *ext_value_p; - int rv = 0; - switch_ext_p = val->value.ext_val; - while(switch_ext_p) { - ext_value_p = switch_ext_p; - - if(!strcmp(ext_value_p->option_name, "name")) { - switch_ext_p = switch_ext_p->next; - continue; - } else if(!strcmp(ext_value_p->option_name, "port_id")) { - val_ptr[0] = (char*)ext_value_p->option_value; - } else if(!strcmp(ext_value_p->option_name, "rx_mac_status")) { - val_ptr[1] = (char*)ext_value_p->option_value; - } else { - rv = -1; - break; - } - - parameter_length++; - switch_ext_p = switch_ext_p->next; - } - - return rv; -} - -static int -parse_port_txfcstatus(struct switch_val *val) -{ - struct switch_ext *switch_ext_p, *ext_value_p; - int rv = 0; - switch_ext_p = val->value.ext_val; - while(switch_ext_p) { - ext_value_p = switch_ext_p; - - if(!strcmp(ext_value_p->option_name, "name")) { - switch_ext_p = switch_ext_p->next; - continue; - } else if(!strcmp(ext_value_p->option_name, "port_id")) { - val_ptr[0] = (char*)ext_value_p->option_value; - } else if(!strcmp(ext_value_p->option_name, "tx_flow_control_status")) { - val_ptr[1] = (char*)ext_value_p->option_value; - } else { - rv = -1; - break; - } - - parameter_length++; - switch_ext_p = switch_ext_p->next; - } - - return rv; -} - -static int -parse_port_rxfcstatus(struct switch_val *val) -{ - struct switch_ext *switch_ext_p, *ext_value_p; - int rv = 0; - switch_ext_p = val->value.ext_val; - while(switch_ext_p) { - ext_value_p = switch_ext_p; - - if(!strcmp(ext_value_p->option_name, "name")) { - switch_ext_p = switch_ext_p->next; - continue; - } else if(!strcmp(ext_value_p->option_name, "port_id")) { - val_ptr[0] = (char*)ext_value_p->option_value; - } else if(!strcmp(ext_value_p->option_name, "rx_flow_control_status")) { - val_ptr[1] = (char*)ext_value_p->option_value; - } else { - rv = -1; - break; - } - - parameter_length++; - switch_ext_p = switch_ext_p->next; - } - - return rv; -} -#endif -#ifndef IN_PORTCONTROL_MINI -static int -parse_port_bpstatus(struct switch_val *val) -{ - struct switch_ext *switch_ext_p, *ext_value_p; - int rv = 0; - switch_ext_p = val->value.ext_val; - while(switch_ext_p) { - ext_value_p = switch_ext_p; - - if(!strcmp(ext_value_p->option_name, "name")) { - switch_ext_p = switch_ext_p->next; - continue; - } else if(!strcmp(ext_value_p->option_name, "port_id")) { - val_ptr[0] = (char*)ext_value_p->option_value; - } else if(!strcmp(ext_value_p->option_name, "back_presure_status")) { - val_ptr[1] = (char*)ext_value_p->option_value; - } else { - rv = -1; - break; - } - - parameter_length++; - switch_ext_p = switch_ext_p->next; - } - - return rv; -} - -static int -parse_port_linkforcemode(struct switch_val *val) -{ - struct switch_ext *switch_ext_p, *ext_value_p; - int rv = 0; - switch_ext_p = val->value.ext_val; - while(switch_ext_p) { - ext_value_p = switch_ext_p; - - if(!strcmp(ext_value_p->option_name, "name")) { - switch_ext_p = switch_ext_p->next; - continue; - } else if(!strcmp(ext_value_p->option_name, "port_id")) { - val_ptr[0] = (char*)ext_value_p->option_value; - } else if(!strcmp(ext_value_p->option_name, "link_force_mode_status")) { - val_ptr[1] = (char*)ext_value_p->option_value; - } else { - rv = -1; - break; - } - - parameter_length++; - switch_ext_p = switch_ext_p->next; - } - - return rv; -} - -static int -parse_port_macloopback(struct switch_val *val) -{ - struct switch_ext *switch_ext_p, *ext_value_p; - int rv = 0; - switch_ext_p = val->value.ext_val; - while(switch_ext_p) { - ext_value_p = switch_ext_p; - - if(!strcmp(ext_value_p->option_name, "name")) { - switch_ext_p = switch_ext_p->next; - continue; - } else if(!strcmp(ext_value_p->option_name, "port_id")) { - val_ptr[0] = (char*)ext_value_p->option_value; - } else if(!strcmp(ext_value_p->option_name, "mac_loopback_status")) { - val_ptr[1] = (char*)ext_value_p->option_value; - } else { - rv = -1; - break; - } - - parameter_length++; - switch_ext_p = switch_ext_p->next; - } - - return rv; -} - -static int -parse_port_congedrop(struct switch_val *val) -{ - struct switch_ext *switch_ext_p, *ext_value_p; - int rv = 0; - switch_ext_p = val->value.ext_val; - while(switch_ext_p) { - ext_value_p = switch_ext_p; - - if(!strcmp(ext_value_p->option_name, "name")) { - switch_ext_p = switch_ext_p->next; - continue; - } else if(!strcmp(ext_value_p->option_name, "port_id")) { - val_ptr[0] = (char*)ext_value_p->option_value; - } else if(!strcmp(ext_value_p->option_name, "queue_id")) { - val_ptr[1] = (char*)ext_value_p->option_value; - } else if(!strcmp(ext_value_p->option_name, "status")) { - val_ptr[2] = (char*)ext_value_p->option_value; - } else { - rv = -1; - break; - } - - parameter_length++; - switch_ext_p = switch_ext_p->next; - } - - return rv; -} - -static int -parse_port_ringfcthresh(struct switch_val *val) -{ - struct switch_ext *switch_ext_p, *ext_value_p; - int rv = 0; - switch_ext_p = val->value.ext_val; - while(switch_ext_p) { - ext_value_p = switch_ext_p; - - if(!strcmp(ext_value_p->option_name, "name")) { - switch_ext_p = switch_ext_p->next; - continue; - } else if(!strcmp(ext_value_p->option_name, "ring_id")) { - val_ptr[0] = (char*)ext_value_p->option_value; - } else if(!strcmp(ext_value_p->option_name, "on_thresh")) { - val_ptr[1] = (char*)ext_value_p->option_value; - } else if(!strcmp(ext_value_p->option_name, "off_thresh")) { - val_ptr[2] = (char*)ext_value_p->option_value; - } else { - rv = -1; - break; - } - - parameter_length++; - switch_ext_p = switch_ext_p->next; - } - - return rv; -} - - - -static int -parse_port_ieee8023az(struct switch_val *val) -{ - struct switch_ext *switch_ext_p, *ext_value_p; - int rv = 0; - switch_ext_p = val->value.ext_val; - while(switch_ext_p) { - ext_value_p = switch_ext_p; - if(!strcmp(ext_value_p->option_name, "name")) { - switch_ext_p = switch_ext_p->next; - continue; - } else if(!strcmp(ext_value_p->option_name, "port_id")) { - val_ptr[0] = (char*)ext_value_p->option_value; - } else if(!strcmp(ext_value_p->option_name, "mode")) { - val_ptr[1] = (char*)ext_value_p->option_value; - } else { - rv = -1; - break; - } - parameter_length++; - switch_ext_p = switch_ext_p->next; - } - - return rv; -} - -static int -parse_port_crossover(struct switch_val *val) -{ - struct switch_ext *switch_ext_p, *ext_value_p; - int rv = 0; - switch_ext_p = val->value.ext_val; - while(switch_ext_p) { - ext_value_p = switch_ext_p; - if(!strcmp(ext_value_p->option_name, "name")) { - switch_ext_p = switch_ext_p->next; - continue; - } else if(!strcmp(ext_value_p->option_name, "port_id")) { - val_ptr[0] = (char*)ext_value_p->option_value; - } else if(!strcmp(ext_value_p->option_name, "mode")) { - val_ptr[1] = (char*)ext_value_p->option_value; - } else { - rv = -1; - break; - } - parameter_length++; - switch_ext_p = switch_ext_p->next; - } - - return rv; -} - -static int -parse_port_prefermedium(struct switch_val *val) -{ - struct switch_ext *switch_ext_p, *ext_value_p; - int rv = 0; - switch_ext_p = val->value.ext_val; - while(switch_ext_p) { - ext_value_p = switch_ext_p; - if(!strcmp(ext_value_p->option_name, "name")) { - switch_ext_p = switch_ext_p->next; - continue; - } else if(!strcmp(ext_value_p->option_name, "port_id")) { - val_ptr[0] = (char*)ext_value_p->option_value; - } else if(!strcmp(ext_value_p->option_name, "mode")) { - val_ptr[1] = (char*)ext_value_p->option_value; - } else { - rv = -1; - break; - } - parameter_length++; - switch_ext_p = switch_ext_p->next; - } - - return rv; -} - -static int -parse_port_fibermode(struct switch_val *val) -{ - struct switch_ext *switch_ext_p, *ext_value_p; - int rv = 0; - switch_ext_p = val->value.ext_val; - while(switch_ext_p) { - ext_value_p = switch_ext_p; - if(!strcmp(ext_value_p->option_name, "name")) { - switch_ext_p = switch_ext_p->next; - continue; - } else if(!strcmp(ext_value_p->option_name, "port_id")) { - val_ptr[0] = (char*)ext_value_p->option_value; - } else if(!strcmp(ext_value_p->option_name, "mode")) { - val_ptr[1] = (char*)ext_value_p->option_value; - } else { - rv = -1; - break; - } - parameter_length++; - switch_ext_p = switch_ext_p->next; - } - - return rv; -} - -static int -parse_port_localloopback(struct switch_val *val) -{ - struct switch_ext *switch_ext_p, *ext_value_p; - int rv = 0; - switch_ext_p = val->value.ext_val; - while(switch_ext_p) { - ext_value_p = switch_ext_p; - if(!strcmp(ext_value_p->option_name, "name")) { - switch_ext_p = switch_ext_p->next; - continue; - } else if(!strcmp(ext_value_p->option_name, "port_id")) { - val_ptr[0] = (char*)ext_value_p->option_value; - } else if(!strcmp(ext_value_p->option_name, "mode")) { - val_ptr[1] = (char*)ext_value_p->option_value; - } else { - rv = -1; - break; - } - parameter_length++; - switch_ext_p = switch_ext_p->next; - } - - return rv; -} - -static int -parse_port_remoteloopback(struct switch_val *val) -{ - struct switch_ext *switch_ext_p, *ext_value_p; - int rv = 0; - switch_ext_p = val->value.ext_val; - while(switch_ext_p) { - ext_value_p = switch_ext_p; - if(!strcmp(ext_value_p->option_name, "name")) { - switch_ext_p = switch_ext_p->next; - continue; - } else if(!strcmp(ext_value_p->option_name, "port_id")) { - val_ptr[0] = (char*)ext_value_p->option_value; - } else if(!strcmp(ext_value_p->option_name, "mode")) { - val_ptr[1] = (char*)ext_value_p->option_value; - } else { - rv = -1; - break; - } - parameter_length++; - switch_ext_p = switch_ext_p->next; - } - - return rv; -} - -static int -parse_port_magicframemac(struct switch_val *val) -{ - struct switch_ext *switch_ext_p, *ext_value_p; - int rv = 0; - switch_ext_p = val->value.ext_val; - while(switch_ext_p) { - ext_value_p = switch_ext_p; - if(!strcmp(ext_value_p->option_name, "name")) { - switch_ext_p = switch_ext_p->next; - continue; - } else if(!strcmp(ext_value_p->option_name, "port_id")) { - val_ptr[0] = (char*)ext_value_p->option_value; - } else if(!strcmp(ext_value_p->option_name, "macaddr")) { - val_ptr[1] = (char*)ext_value_p->option_value; - } else { - rv = -1; - break; - } - parameter_length++; - switch_ext_p = switch_ext_p->next; - } - - return rv; -} - -static int -parse_port_wolstatus(struct switch_val *val) -{ - struct switch_ext *switch_ext_p, *ext_value_p; - int rv = 0; - switch_ext_p = val->value.ext_val; - while(switch_ext_p) { - ext_value_p = switch_ext_p; - if(!strcmp(ext_value_p->option_name, "name")) { - switch_ext_p = switch_ext_p->next; - continue; - } else if(!strcmp(ext_value_p->option_name, "port_id")) { - val_ptr[0] = (char*)ext_value_p->option_value; - } else if(!strcmp(ext_value_p->option_name, "mode")) { - val_ptr[1] = (char*)ext_value_p->option_value; - } else { - rv = -1; - break; - } - parameter_length++; - switch_ext_p = switch_ext_p->next; - } - - return rv; -} - -static int -parse_port_interfacemode(struct switch_val *val) -{ - struct switch_ext *switch_ext_p, *ext_value_p; - int rv = 0; - switch_ext_p = val->value.ext_val; - while(switch_ext_p) { - ext_value_p = switch_ext_p; - if(!strcmp(ext_value_p->option_name, "name")) { - switch_ext_p = switch_ext_p->next; - continue; - } else if(!strcmp(ext_value_p->option_name, "port_id")) { - val_ptr[0] = (char*)ext_value_p->option_value; - } else if(!strcmp(ext_value_p->option_name, "mode")) { - val_ptr[1] = (char*)ext_value_p->option_value; - } else { - rv = -1; - break; - } - parameter_length++; - switch_ext_p = switch_ext_p->next; - } - - return rv; -} - -static int -parse_port_interfacemodeapply(struct switch_val *val) -{ - struct switch_ext *switch_ext_p, *ext_value_p; - int rv = 0; - - switch_ext_p = val->value.ext_val; - while(switch_ext_p) { - ext_value_p = switch_ext_p; - - if(!strcmp(ext_value_p->option_name, "name")) { - switch_ext_p = switch_ext_p->next; - continue; - } else { - rv = -1; - break; - } - - parameter_length++; - switch_ext_p = switch_ext_p->next; - } - - return rv; -} - -static int -parse_port_poweron(struct switch_val *val) -{ - struct switch_ext *switch_ext_p, *ext_value_p; - int rv = 0; - switch_ext_p = val->value.ext_val; - while(switch_ext_p) { - ext_value_p = switch_ext_p; - if(!strcmp(ext_value_p->option_name, "name")) { - switch_ext_p = switch_ext_p->next; - continue; - } else if(!strcmp(ext_value_p->option_name, "port_id")) { - val_ptr[0] = (char*)ext_value_p->option_value; - } else { - rv = -1; - break; - } - parameter_length++; - switch_ext_p = switch_ext_p->next; - } - - return rv; -} - -static int -parse_port_poweroff(struct switch_val *val) -{ - struct switch_ext *switch_ext_p, *ext_value_p; - int rv = 0; - switch_ext_p = val->value.ext_val; - while(switch_ext_p) { - ext_value_p = switch_ext_p; - if(!strcmp(ext_value_p->option_name, "name")) { - switch_ext_p = switch_ext_p->next; - continue; - } else if(!strcmp(ext_value_p->option_name, "port_id")) { - val_ptr[0] = (char*)ext_value_p->option_value; - } else { - rv = -1; - break; - } - parameter_length++; - switch_ext_p = switch_ext_p->next; - } - - return rv; -} - -static int -parse_port_reset(struct switch_val *val) -{ - struct switch_ext *switch_ext_p, *ext_value_p; - int rv = 0; - switch_ext_p = val->value.ext_val; - while(switch_ext_p) { - ext_value_p = switch_ext_p; - if(!strcmp(ext_value_p->option_name, "name")) { - switch_ext_p = switch_ext_p->next; - continue; - } else if(!strcmp(ext_value_p->option_name, "port_id")) { - val_ptr[0] = (char*)ext_value_p->option_value; - } else { - rv = -1; - break; - } - parameter_length++; - switch_ext_p = switch_ext_p->next; - } - - return rv; -} - -static int -parse_port_interface8023az(struct switch_val *val) -{ - struct switch_ext *switch_ext_p, *ext_value_p; - int rv = 0; - switch_ext_p = val->value.ext_val; - while(switch_ext_p) { - ext_value_p = switch_ext_p; - if(!strcmp(ext_value_p->option_name, "name")) { - switch_ext_p = switch_ext_p->next; - continue; - } else if(!strcmp(ext_value_p->option_name, "port_id")) { - val_ptr[0] = (char*)ext_value_p->option_value; - } else if(!strcmp(ext_value_p->option_name, "mode")) { - val_ptr[1] = (char*)ext_value_p->option_value; - } else { - rv = -1; - break; - } - parameter_length++; - switch_ext_p = switch_ext_p->next; - } - - return rv; -} - -static int -parse_port_promiscmode(struct switch_val *val) -{ - struct switch_ext *switch_ext_p, *ext_value_p; - int rv = 0; - switch_ext_p = val->value.ext_val; - while(switch_ext_p) { - ext_value_p = switch_ext_p; - - if(!strcmp(ext_value_p->option_name, "name")) { - switch_ext_p = switch_ext_p->next; - continue; - } else if(!strcmp(ext_value_p->option_name, "port_id")) { - val_ptr[0] = (char*)ext_value_p->option_value; - } else if(!strcmp(ext_value_p->option_name, "promisc_mode")) { - val_ptr[1] = (char*)ext_value_p->option_value; - } else { - rv = -1; - break; - } - - parameter_length++; - switch_ext_p = switch_ext_p->next; - } - - return rv; -} -static int -parse_port_eeecfg(struct switch_val *val) -{ - struct switch_ext *switch_ext_p, *ext_value_p; - int rv = 0; - switch_ext_p = val->value.ext_val; - while(switch_ext_p) { - ext_value_p = switch_ext_p; - if(!strcmp(ext_value_p->option_name, "name")) { - switch_ext_p = switch_ext_p->next; - continue; - } else if(!strcmp(ext_value_p->option_name, "port_id")) { - val_ptr[0] = (char*)ext_value_p->option_value; - } else if(!strcmp(ext_value_p->option_name, "eee_en")) { - val_ptr[1] = (char*)ext_value_p->option_value; - } else if(!strcmp(ext_value_p->option_name, "eee_capability")) { - val_ptr[2] = (char*)ext_value_p->option_value; - } else if(!strcmp(ext_value_p->option_name, "lpi_sleep_timer")) { - val_ptr[3] = (char*)ext_value_p->option_value; - } else if(!strcmp(ext_value_p->option_name, "advertisement")) { - val_ptr[4] = (char*)ext_value_p->option_value; - } else if(!strcmp(ext_value_p->option_name, "lpi_tx_en")) { - val_ptr[5] = (char*)ext_value_p->option_value; - } else if(!strcmp(ext_value_p->option_name, "eee_status")) { - val_ptr[6] = (char*)ext_value_p->option_value; - } else if(!strcmp(ext_value_p->option_name, "lpi_wakeup_timer")) { - val_ptr[7] = (char*)ext_value_p->option_value; - } else if(!strcmp(ext_value_p->option_name, "link_partner_advertisement")) { - val_ptr[8] = (char*)ext_value_p->option_value; - } else { - rv = -1; - break; - } - parameter_length++; - switch_ext_p = switch_ext_p->next; - } - - return rv; -} - -static int -parse_port_srcfiltercfg(struct switch_val *val) -{ - struct switch_ext *switch_ext_p, *ext_value_p; - int rv = 0; - switch_ext_p = val->value.ext_val; - while(switch_ext_p) { - ext_value_p = switch_ext_p; - - if(!strcmp(ext_value_p->option_name, "name")) { - switch_ext_p = switch_ext_p->next; - continue; - } else if(!strcmp(ext_value_p->option_name, "port_id")) { - val_ptr[0] = (char*)ext_value_p->option_value; - } else if(!strcmp(ext_value_p->option_name, "srcfilter_enable")) { - val_ptr[1] = (char*)ext_value_p->option_value; - } else if(!strcmp(ext_value_p->option_name, "srcfilter_mode")) { - val_ptr[2] = (char*)ext_value_p->option_value; - } else { - rv = -1; - break; - } - - parameter_length++; - switch_ext_p = switch_ext_p->next; - } - - return rv; -} - -static int -parse_port_framemaxsize(struct switch_val *val) -{ - struct switch_ext *switch_ext_p, *ext_value_p; - int rv = 0; - switch_ext_p = val->value.ext_val; - while(switch_ext_p) { - ext_value_p = switch_ext_p; - - if(!strcmp(ext_value_p->option_name, "name")) { - switch_ext_p = switch_ext_p->next; - continue; - } else if(!strcmp(ext_value_p->option_name, "port_id")) { - val_ptr[0] = (char*)ext_value_p->option_value; - } else if(!strcmp(ext_value_p->option_name, "frame_max_size")) { - val_ptr[1] = (char*)ext_value_p->option_value; - } else { - rv = -1; - break; - } - - parameter_length++; - switch_ext_p = switch_ext_p->next; - } - - return rv; -} - -static int -parse_port_mtu(struct switch_val *val) -{ - struct switch_ext *switch_ext_p, *ext_value_p; - int rv = 0; - switch_ext_p = val->value.ext_val; - while(switch_ext_p) { - ext_value_p = switch_ext_p; - - if(!strcmp(ext_value_p->option_name, "name")) { - switch_ext_p = switch_ext_p->next; - continue; - } else if(!strcmp(ext_value_p->option_name, "port_id")) { - val_ptr[0] = (char*)ext_value_p->option_value; - } else if(!strcmp(ext_value_p->option_name, "mtusize")) { - val_ptr[1] = (char*)ext_value_p->option_value; - } else if(!strcmp(ext_value_p->option_name, "mtuaction")) { - val_ptr[2] = (char*)ext_value_p->option_value; - } else { - rv = -1; - break; - } - - parameter_length++; - switch_ext_p = switch_ext_p->next; - } - - return rv; -} - -static int -parse_port_mru(struct switch_val *val) -{ - struct switch_ext *switch_ext_p, *ext_value_p; - int rv = 0; - switch_ext_p = val->value.ext_val; - while(switch_ext_p) { - ext_value_p = switch_ext_p; - - if(!strcmp(ext_value_p->option_name, "name")) { - switch_ext_p = switch_ext_p->next; - continue; - } else if(!strcmp(ext_value_p->option_name, "port_id")) { - val_ptr[0] = (char*)ext_value_p->option_value; - } else if(!strcmp(ext_value_p->option_name, "mrusize")) { - val_ptr[1] = (char*)ext_value_p->option_value; - } else if(!strcmp(ext_value_p->option_name, "mruaction")) { - val_ptr[2] = (char*)ext_value_p->option_value; - } else { - rv = -1; - break; - } - - parameter_length++; - switch_ext_p = switch_ext_p->next; - } - - return rv; -} - -static int -parse_port_srcfilter(struct switch_val *val) -{ - struct switch_ext *switch_ext_p, *ext_value_p; - int rv = 0; - switch_ext_p = val->value.ext_val; - while(switch_ext_p) { - ext_value_p = switch_ext_p; - - if(!strcmp(ext_value_p->option_name, "name")) { - switch_ext_p = switch_ext_p->next; - continue; - } else if(!strcmp(ext_value_p->option_name, "port_id")) { - val_ptr[0] = (char*)ext_value_p->option_value; - } else if(!strcmp(ext_value_p->option_name, "status_en")) { - val_ptr[1] = (char*)ext_value_p->option_value; - } else { - rv = -1; - break; - } - - parameter_length++; - switch_ext_p = switch_ext_p->next; - } - - return rv; -} - -static int -parse_switch_port_loopback(struct switch_val *val) -{ - struct switch_ext *switch_ext_p, *ext_value_p; - int rv = 0; - switch_ext_p = val->value.ext_val; - while(switch_ext_p) { - ext_value_p = switch_ext_p; - - if(!strcmp(ext_value_p->option_name, "name")) { - switch_ext_p = switch_ext_p->next; - continue; - } else if(!strcmp(ext_value_p->option_name, "port_id")) { - val_ptr[0] = (char*)ext_value_p->option_value; - } else if(!strcmp(ext_value_p->option_name, "loopback_en")) { - val_ptr[1] = (char*)ext_value_p->option_value; - } else if(!strcmp(ext_value_p->option_name, "crc_stripped_en")) { - val_ptr[2] = (char*)ext_value_p->option_value; - } else if(!strcmp(ext_value_p->option_name, "loopback_rate")) { - val_ptr[3] = (char*)ext_value_p->option_value; - } else { - rv = -1; - break; - } - - parameter_length++; - switch_ext_p = switch_ext_p->next; - } - - return rv; -} - -#endif -#endif - -#ifdef IN_PORTVLAN -static int -parse_portvlan_ingress(struct switch_val *val) -{ - struct switch_ext *switch_ext_p, *ext_value_p; - int rv = 0; - switch_ext_p = val->value.ext_val; - while(switch_ext_p) { - ext_value_p = switch_ext_p; - - if(!strcmp(ext_value_p->option_name, "name")) { - switch_ext_p = switch_ext_p->next; - continue; - } else if(!strcmp(ext_value_p->option_name, "port_id")) { - val_ptr[0] = (char*)ext_value_p->option_value; - } else if(!strcmp(ext_value_p->option_name, "ingress_vlan_mode")) { - val_ptr[1] = (char*)ext_value_p->option_value; - } else { - rv = -1; - break; - } - - parameter_length++; - switch_ext_p = switch_ext_p->next; - } - - return rv; -} - -static int -parse_portvlan_egress(struct switch_val *val) -{ - struct switch_ext *switch_ext_p, *ext_value_p; - int rv = 0; - switch_ext_p = val->value.ext_val; - while(switch_ext_p) { - ext_value_p = switch_ext_p; - - if(!strcmp(ext_value_p->option_name, "name")) { - switch_ext_p = switch_ext_p->next; - continue; - } else if(!strcmp(ext_value_p->option_name, "port_id")) { - val_ptr[0] = (char*)ext_value_p->option_value; - } else if(!strcmp(ext_value_p->option_name, "egress_vlan_mode")) { - val_ptr[1] = (char*)ext_value_p->option_value; - } else { - rv = -1; - break; - } - - parameter_length++; - switch_ext_p = switch_ext_p->next; - } - - return rv; -} - -static int -parse_portvlan_member(struct switch_val *val) -{ - struct switch_ext *switch_ext_p, *ext_value_p; - int rv = 0; - switch_ext_p = val->value.ext_val; - while(switch_ext_p) { - ext_value_p = switch_ext_p; - - if(!strcmp(ext_value_p->option_name, "name")) { - switch_ext_p = switch_ext_p->next; - continue; - } else if(!strcmp(ext_value_p->option_name, "port_id")) { - val_ptr[0] = (char*)ext_value_p->option_value; - } else if(!strcmp(ext_value_p->option_name, "member")) { - val_ptr[1] = (char*)ext_value_p->option_value; - } else { - rv = -1; - break; - } - - parameter_length++; - switch_ext_p = switch_ext_p->next; - } - - return rv; -} - -static int -parse_portvlan_forcevid(struct switch_val *val) -{ - struct switch_ext *switch_ext_p, *ext_value_p; - int rv = 0; - switch_ext_p = val->value.ext_val; - while(switch_ext_p) { - ext_value_p = switch_ext_p; - - if(!strcmp(ext_value_p->option_name, "name")) { - switch_ext_p = switch_ext_p->next; - continue; - } else if(!strcmp(ext_value_p->option_name, "port_id")) { - val_ptr[0] = (char*)ext_value_p->option_value; - } else if(!strcmp(ext_value_p->option_name, "force_vid_status")) { - val_ptr[1] = (char*)ext_value_p->option_value; - } else { - rv = -1; - break; - } - - parameter_length++; - switch_ext_p = switch_ext_p->next; - } - - return rv; -} - -static int -parse_portvlan_forcemode(struct switch_val *val) -{ - struct switch_ext *switch_ext_p, *ext_value_p; - int rv = 0; - switch_ext_p = val->value.ext_val; - while(switch_ext_p) { - ext_value_p = switch_ext_p; - - if(!strcmp(ext_value_p->option_name, "name")) { - switch_ext_p = switch_ext_p->next; - continue; - } else if(!strcmp(ext_value_p->option_name, "port_id")) { - val_ptr[0] = (char*)ext_value_p->option_value; - } else if(!strcmp(ext_value_p->option_name, "force_mode")) { - val_ptr[1] = (char*)ext_value_p->option_value; - } else { - rv = -1; - break; - } - - parameter_length++; - switch_ext_p = switch_ext_p->next; - } - - return rv; -} - -static int -parse_portvlan_svlantpid(struct switch_val *val) -{ - struct switch_ext *switch_ext_p, *ext_value_p; - int rv = 0; - switch_ext_p = val->value.ext_val; - while(switch_ext_p) { - ext_value_p = switch_ext_p; - - if(!strcmp(ext_value_p->option_name, "name")) { - switch_ext_p = switch_ext_p->next; - continue; - } else if(!strcmp(ext_value_p->option_name, "stag_tpid")) { - val_ptr[0] = (char*)ext_value_p->option_value; - } else { - rv = -1; - break; - } - - parameter_length++; - switch_ext_p = switch_ext_p->next; - } - - return rv; -} -static int -parse_portvlan_defaultsvid(struct switch_val *val) -{ - struct switch_ext *switch_ext_p, *ext_value_p; - int rv = 0; - switch_ext_p = val->value.ext_val; - while(switch_ext_p) { - ext_value_p = switch_ext_p; - - if(!strcmp(ext_value_p->option_name, "name")) { - switch_ext_p = switch_ext_p->next; - continue; - } else if(!strcmp(ext_value_p->option_name, "port_id")) { - val_ptr[0] = (char*)ext_value_p->option_value; - } else if(!strcmp(ext_value_p->option_name, "default_stag_vid")) { - val_ptr[1] = (char*)ext_value_p->option_value; - } else { - rv = -1; - break; - } - - parameter_length++; - switch_ext_p = switch_ext_p->next; - } - - return rv; -} -static int -parse_portvlan_defaultcvid(struct switch_val *val) -{ - struct switch_ext *switch_ext_p, *ext_value_p; - int rv = 0; - switch_ext_p = val->value.ext_val; - while(switch_ext_p) { - ext_value_p = switch_ext_p; - - if(!strcmp(ext_value_p->option_name, "name")) { - switch_ext_p = switch_ext_p->next; - continue; - } else if(!strcmp(ext_value_p->option_name, "port_id")) { - val_ptr[0] = (char*)ext_value_p->option_value; - } else if(!strcmp(ext_value_p->option_name, "default_ctag_vid")) { - val_ptr[1] = (char*)ext_value_p->option_value; - } else { - rv = -1; - break; - } - - parameter_length++; - switch_ext_p = switch_ext_p->next; - } - - return rv; -} - -static int -parse_portvlan_globalqinqmode(struct switch_val *val) -{ - struct switch_ext *switch_ext_p, *ext_value_p; - int rv = 0; - - switch_ext_p = val->value.ext_val; - while (switch_ext_p) { - ext_value_p = switch_ext_p; - - if (!strcmp(ext_value_p->option_name, "name")) { - switch_ext_p = switch_ext_p->next; - continue; - } else if (!strcmp(ext_value_p->option_name, "mask")) { - val_ptr[0] = (char*)ext_value_p->option_value; - } else if (!strcmp(ext_value_p->option_name, "ingress_qinq_mode")) { - val_ptr[1] = (char*)ext_value_p->option_value; - } else if (!strcmp(ext_value_p->option_name, "egress_qinq_mode")) { - val_ptr[2] = (char*)ext_value_p->option_value; - } else { - rv = -1; - break; - } - - parameter_length++; - switch_ext_p = switch_ext_p->next; - } - - return rv; -} - -static int -parse_portvlan_ptqinqmode(struct switch_val *val) -{ - struct switch_ext *switch_ext_p, *ext_value_p; - int rv = 0; - - switch_ext_p = val->value.ext_val; - while (switch_ext_p) { - ext_value_p = switch_ext_p; - - if (!strcmp(ext_value_p->option_name, "name")) { - switch_ext_p = switch_ext_p->next; - continue; - } else if (!strcmp(ext_value_p->option_name, "port_id")) { - val_ptr[0] = (char*)ext_value_p->option_value; - } else if (!strcmp(ext_value_p->option_name, "mask")) { - val_ptr[1] = (char*)ext_value_p->option_value; - } else if (!strcmp(ext_value_p->option_name, "ingress_qinq_role")) { - val_ptr[2] = (char*)ext_value_p->option_value; - } else if (!strcmp(ext_value_p->option_name, "egress_qinq_role")) { - val_ptr[3] = (char*)ext_value_p->option_value; - } else { - rv = -1; - break; - } - - parameter_length++; - switch_ext_p = switch_ext_p->next; - } - - return rv; -} -#ifdef HPPE -static int -parse_portvlan_intpid(struct switch_val *val) -{ - struct switch_ext *switch_ext_p, *ext_value_p; - int rv = 0; - - switch_ext_p = val->value.ext_val; - while (switch_ext_p) { - ext_value_p = switch_ext_p; - - if (!strcmp(ext_value_p->option_name, "name")) { - switch_ext_p = switch_ext_p->next; - continue; - } else if (!strcmp(ext_value_p->option_name, "mask")) { - val_ptr[0] = (char*)ext_value_p->option_value; - } else if (!strcmp(ext_value_p->option_name, "ctagtpid")) { - val_ptr[1] = (char*)ext_value_p->option_value; - } else if (!strcmp(ext_value_p->option_name, "stagtpid")) { - val_ptr[2] = (char*)ext_value_p->option_value; - } else { - rv = -1; - break; - } - - parameter_length++; - switch_ext_p = switch_ext_p->next; - } - - return rv; -} - -static int -parse_portvlan_egtpid(struct switch_val *val) -{ - struct switch_ext *switch_ext_p, *ext_value_p; - int rv = 0; - - switch_ext_p = val->value.ext_val; - while (switch_ext_p) { - ext_value_p = switch_ext_p; - - if (!strcmp(ext_value_p->option_name, "name")) { - switch_ext_p = switch_ext_p->next; - continue; - } else if (!strcmp(ext_value_p->option_name, "mask")) { - val_ptr[0] = (char*)ext_value_p->option_value; - } else if (!strcmp(ext_value_p->option_name, "ctagtpid")) { - val_ptr[1] = (char*)ext_value_p->option_value; - } else if (!strcmp(ext_value_p->option_name, "stagtpid")) { - val_ptr[2] = (char*)ext_value_p->option_value; - } else { - rv = -1; - break; - } - - parameter_length++; - switch_ext_p = switch_ext_p->next; - } - - return rv; -} - -static int -parse_portvlan_ingressfilter(struct switch_val *val) -{ - struct switch_ext *switch_ext_p, *ext_value_p; - int rv = 0; - - switch_ext_p = val->value.ext_val; - while (switch_ext_p) { - ext_value_p = switch_ext_p; - - if (!strcmp(ext_value_p->option_name, "name")) { - switch_ext_p = switch_ext_p->next; - continue; - } else if (!strcmp(ext_value_p->option_name, "port_id")) { - val_ptr[0] = (char*)ext_value_p->option_value; - } else if (!strcmp(ext_value_p->option_name, "membership_filter_en")) { - val_ptr[1] = (char*)ext_value_p->option_value; - } else if (!strcmp(ext_value_p->option_name, "tagged_filter_en")) { - val_ptr[2] = (char*)ext_value_p->option_value; - } else if (!strcmp(ext_value_p->option_name, "untagged_filter_en")) { - val_ptr[3] = (char*)ext_value_p->option_value; - } else if (!strcmp(ext_value_p->option_name, "priority_tagged_filter_en")) { - val_ptr[4] = (char*)ext_value_p->option_value; - } else { - rv = -1; - break; - } - - parameter_length++; - switch_ext_p = switch_ext_p->next; - } - - return rv; -} - -static int -parse_portvlan_defaultvlantag(struct switch_val *val) -{ - struct switch_ext *switch_ext_p, *ext_value_p; - int rv = 0; - - switch_ext_p = val->value.ext_val; - while (switch_ext_p) { - ext_value_p = switch_ext_p; - - if (!strcmp(ext_value_p->option_name, "name")) { - switch_ext_p = switch_ext_p->next; - continue; - } else if (!strcmp(ext_value_p->option_name, "port_id")) { - val_ptr[0] = (char*)ext_value_p->option_value; - } else if (!strcmp(ext_value_p->option_name, "direction")) { - val_ptr[1] = (char*)ext_value_p->option_value; - } else if (!strcmp(ext_value_p->option_name, "default_ctag_vid_en")) { - val_ptr[2] = (char*)ext_value_p->option_value; - } else if (!strcmp(ext_value_p->option_name, "default_stag_vid_en")) { - val_ptr[3] = (char*)ext_value_p->option_value; - } else if (!strcmp(ext_value_p->option_name, "mask")) { - val_ptr[4] = (char*)ext_value_p->option_value; - } else if (!strcmp(ext_value_p->option_name, "default_ctag_vid")) { - val_ptr[5] = (char*)ext_value_p->option_value; - } else if (!strcmp(ext_value_p->option_name, "default_stag_vid")) { - val_ptr[6] = (char*)ext_value_p->option_value; - } else if (!strcmp(ext_value_p->option_name, "default_ctag_pri")) { - val_ptr[7] = (char*)ext_value_p->option_value; - } else if (!strcmp(ext_value_p->option_name, "default_stag_pri")) { - val_ptr[8] = (char*)ext_value_p->option_value; - } else if (!strcmp(ext_value_p->option_name, "default_ctag_dei")) { - val_ptr[9] = (char*)ext_value_p->option_value; - } else if (!strcmp(ext_value_p->option_name, "default_stag_dei")) { - val_ptr[10] = (char*)ext_value_p->option_value; - } else { - rv = -1; - break; - } - - parameter_length++; - switch_ext_p = switch_ext_p->next; - } - - return rv; -} - -static int -parse_portvlan_tagpropagation(struct switch_val *val) -{ - struct switch_ext *switch_ext_p, *ext_value_p; - int rv = 0; - - switch_ext_p = val->value.ext_val; - while (switch_ext_p) { - ext_value_p = switch_ext_p; - - if (!strcmp(ext_value_p->option_name, "name")) { - switch_ext_p = switch_ext_p->next; - continue; - } else if (!strcmp(ext_value_p->option_name, "port_id")) { - val_ptr[0] = (char*)ext_value_p->option_value; - } else if (!strcmp(ext_value_p->option_name, "direction")) { - val_ptr[1] = (char*)ext_value_p->option_value; - } else if (!strcmp(ext_value_p->option_name, "mask")) { - val_ptr[2] = (char*)ext_value_p->option_value; - } else if (!strcmp(ext_value_p->option_name, "vid_propagation_en")) { - val_ptr[3] = (char*)ext_value_p->option_value; - } else if (!strcmp(ext_value_p->option_name, "pri_propagation_en")) { - val_ptr[4] = (char*)ext_value_p->option_value; - } else if (!strcmp(ext_value_p->option_name, "dei_propagation_en")) { - val_ptr[5] = (char*)ext_value_p->option_value; - } else { - rv = -1; - break; - } - - parameter_length++; - switch_ext_p = switch_ext_p->next; - } - - return rv; -} - -static int -parse_portvlan_translationmissaction(struct switch_val *val) -{ - struct switch_ext *switch_ext_p, *ext_value_p; - int rv = 0; - - switch_ext_p = val->value.ext_val; - while (switch_ext_p) { - ext_value_p = switch_ext_p; - - if (!strcmp(ext_value_p->option_name, "name")) { - switch_ext_p = switch_ext_p->next; - continue; - } else if (!strcmp(ext_value_p->option_name, "port_id")) { - val_ptr[0] = (char*)ext_value_p->option_value; - } else if (!strcmp(ext_value_p->option_name, "translation_miss_action")) { - val_ptr[1] = (char*)ext_value_p->option_value; - } else { - rv = -1; - break; - } - - parameter_length++; - switch_ext_p = switch_ext_p->next; - } - - return rv; -} -#endif -static int -parse_portvlan_egmode(struct switch_val *val) -{ - struct switch_ext *switch_ext_p, *ext_value_p; - int rv = 0; - - switch_ext_p = val->value.ext_val; - while (switch_ext_p) { - ext_value_p = switch_ext_p; - - if (!strcmp(ext_value_p->option_name, "name")) { - switch_ext_p = switch_ext_p->next; - continue; - } else if (!strcmp(ext_value_p->option_name, "port_id")) { - val_ptr[0] = (char*)ext_value_p->option_value; - } else if (!strcmp(ext_value_p->option_name, "mask")) { - val_ptr[1] = (char*)ext_value_p->option_value; - } else if (!strcmp(ext_value_p->option_name, "ctag_egress_vlan_mode")) { - val_ptr[2] = (char*)ext_value_p->option_value; - } else if (!strcmp(ext_value_p->option_name, "stag_egress_vlan_mode")) { - val_ptr[3] = (char*)ext_value_p->option_value; - } else { - rv = -1; - break; - } - - parameter_length++; - switch_ext_p = switch_ext_p->next; - } - - return rv; -} -#ifdef HPPE -static int -parse_portvlan_vsiegmode(struct switch_val *val) -{ - struct switch_ext *switch_ext_p, *ext_value_p; - int rv = 0; - - switch_ext_p = val->value.ext_val; - while (switch_ext_p) { - ext_value_p = switch_ext_p; - - if (!strcmp(ext_value_p->option_name, "name")) { - switch_ext_p = switch_ext_p->next; - continue; - } else if (!strcmp(ext_value_p->option_name, "vsi")) { - val_ptr[0] = (char*)ext_value_p->option_value; - } else if (!strcmp(ext_value_p->option_name, "port_id")) { - val_ptr[1] = (char*)ext_value_p->option_value; - } else if (!strcmp(ext_value_p->option_name, "vsi_egress_vlan_mode")) { - val_ptr[2] = (char*)ext_value_p->option_value; - } else { - rv = -1; - break; - } - - parameter_length++; - switch_ext_p = switch_ext_p->next; - } - - return rv; -} - -static int -parse_portvlan_vsiegmodeen(struct switch_val *val) -{ - struct switch_ext *switch_ext_p, *ext_value_p; - int rv = 0; - - switch_ext_p = val->value.ext_val; - while (switch_ext_p) { - ext_value_p = switch_ext_p; - - if (!strcmp(ext_value_p->option_name, "name")) { - switch_ext_p = switch_ext_p->next; - continue; - } else if (!strcmp(ext_value_p->option_name, "port_id")) { - val_ptr[0] = (char*)ext_value_p->option_value; - } else if (!strcmp(ext_value_p->option_name, "vsi_egress_vlan_mode_en")) { - val_ptr[1] = (char*)ext_value_p->option_value; - } else { - rv = -1; - break; - } - - parameter_length++; - switch_ext_p = switch_ext_p->next; - } - - return rv; -} - -static int -parse_portvlan_counter(struct switch_val *val) -{ - struct switch_ext *switch_ext_p, *ext_value_p; - int rv = 0; - - switch_ext_p = val->value.ext_val; - while (switch_ext_p) { - ext_value_p = switch_ext_p; - - if (!strcmp(ext_value_p->option_name, "name")) { - switch_ext_p = switch_ext_p->next; - continue; - } else if (!strcmp(ext_value_p->option_name, "index")) { - val_ptr[0] = (char*)ext_value_p->option_value; - } else { - rv = -1; - break; - } - - parameter_length++; - switch_ext_p = switch_ext_p->next; - } - - return rv; -} - -static int -parse_portvlan_translationadv(struct switch_val *val) -{ - struct switch_ext *switch_ext_p, *ext_value_p; - int rv = 0; - - switch_ext_p = val->value.ext_val; - while (switch_ext_p) { - ext_value_p = switch_ext_p; - - if (!strcmp(ext_value_p->option_name, "name")) { - switch_ext_p = switch_ext_p->next; - continue; - } else if (!strcmp(ext_value_p->option_name, "port_id")) { - val_ptr[0] = (char*)ext_value_p->option_value; - } else if (!strcmp(ext_value_p->option_name, "direction")) { - val_ptr[1] = (char*)ext_value_p->option_value; - } else if (!strcmp(ext_value_p->option_name, "stagformat")) { - val_ptr[2] = (char*)ext_value_p->option_value; - } else if (!strcmp(ext_value_p->option_name, "svid_en")) { - val_ptr[3] = (char*)ext_value_p->option_value; - } else if (!strcmp(ext_value_p->option_name, "svid")) { - val_ptr[4] = (char*)ext_value_p->option_value; - } else if (!strcmp(ext_value_p->option_name, "spcp_en")) { - val_ptr[5] = (char*)ext_value_p->option_value; - } else if (!strcmp(ext_value_p->option_name, "spcp")) { - val_ptr[6] = (char*)ext_value_p->option_value; - } else if (!strcmp(ext_value_p->option_name, "sdei_en")) { - val_ptr[7] = (char*)ext_value_p->option_value; - } else if (!strcmp(ext_value_p->option_name, "sdei")) { - val_ptr[8] = (char*)ext_value_p->option_value; - } else if (!strcmp(ext_value_p->option_name, "ctagformat")) { - val_ptr[9] = (char*)ext_value_p->option_value; - } else if (!strcmp(ext_value_p->option_name, "cvid_en")) { - val_ptr[10] = (char*)ext_value_p->option_value; - } else if (!strcmp(ext_value_p->option_name, "cvid")) { - val_ptr[11] = (char*)ext_value_p->option_value; - } else if (!strcmp(ext_value_p->option_name, "cpcp_en")) { - val_ptr[12] = (char*)ext_value_p->option_value; - } else if (!strcmp(ext_value_p->option_name, "cpcp")) { - val_ptr[13] = (char*)ext_value_p->option_value; - } else if (!strcmp(ext_value_p->option_name, "cdei_en")) { - val_ptr[14] = (char*)ext_value_p->option_value; - } else if (!strcmp(ext_value_p->option_name, "cdei")) { - val_ptr[15] = (char*)ext_value_p->option_value; - } else if (!strcmp(ext_value_p->option_name, "frame_type_en")) { - val_ptr[16] = (char*)ext_value_p->option_value; - } else if (!strcmp(ext_value_p->option_name, "frametype")) { - val_ptr[17] = (char*)ext_value_p->option_value; - } else if (!strcmp(ext_value_p->option_name, "protocol_en")) { - val_ptr[18] = (char*)ext_value_p->option_value; - } else if (!strcmp(ext_value_p->option_name, "protocol")) { - val_ptr[19] = (char*)ext_value_p->option_value; - } else if (!strcmp(ext_value_p->option_name, "vsivalid")) { - val_ptr[20] = (char*)ext_value_p->option_value; - } else if (!strcmp(ext_value_p->option_name, "vsi_en")) { - val_ptr[21] = (char*)ext_value_p->option_value; - } else if (!strcmp(ext_value_p->option_name, "vsi")) { - val_ptr[22] = (char*)ext_value_p->option_value; - } else if (!strcmp(ext_value_p->option_name, "swap_svid_cvid")) { - val_ptr[23] = (char*)ext_value_p->option_value; - } else if (!strcmp(ext_value_p->option_name, "svid_translation_cmd")) { - val_ptr[24] = (char*)ext_value_p->option_value; - } else if (!strcmp(ext_value_p->option_name, "svidtranslation")) { - val_ptr[25] = (char*)ext_value_p->option_value; - } else if (!strcmp(ext_value_p->option_name, "cvid_translation_cmd")) { - val_ptr[26] = (char*)ext_value_p->option_value; - } else if (!strcmp(ext_value_p->option_name, "cvidtranslation")) { - val_ptr[27] = (char*)ext_value_p->option_value; - } else if (!strcmp(ext_value_p->option_name, "swap_spcp_cpcp")) { - val_ptr[28] = (char*)ext_value_p->option_value; - } else if (!strcmp(ext_value_p->option_name, "spcp_translation_en")) { - val_ptr[29] = (char*)ext_value_p->option_value; - } else if (!strcmp(ext_value_p->option_name, "spcptranslation")) { - val_ptr[30] = (char*)ext_value_p->option_value; - } else if (!strcmp(ext_value_p->option_name, "cpcp_translation_en")) { - val_ptr[31] = (char*)ext_value_p->option_value; - } else if (!strcmp(ext_value_p->option_name, "cpcptranslation")) { - val_ptr[32] = (char*)ext_value_p->option_value; - } else if (!strcmp(ext_value_p->option_name, "swap_sdei_cdei")) { - val_ptr[33] = (char*)ext_value_p->option_value; - } else if (!strcmp(ext_value_p->option_name, "sdei_translation_en")) { - val_ptr[34] = (char*)ext_value_p->option_value; - } else if (!strcmp(ext_value_p->option_name, "sdeitranslation")) { - val_ptr[35] = (char*)ext_value_p->option_value; - } else if (!strcmp(ext_value_p->option_name, "cdei_translation_en")) { - val_ptr[36] = (char*)ext_value_p->option_value; - } else if (!strcmp(ext_value_p->option_name, "cdeitranslation")) { - val_ptr[37] = (char*)ext_value_p->option_value; - } else if (!strcmp(ext_value_p->option_name, "counter_en")) { - val_ptr[38] = (char*)ext_value_p->option_value; - } else if (!strcmp(ext_value_p->option_name, "counter_id")) { - val_ptr[39] = (char*)ext_value_p->option_value; - } else if (!strcmp(ext_value_p->option_name, "vsi_translation_en")) { - val_ptr[40] = (char*)ext_value_p->option_value; - } else if (!strcmp(ext_value_p->option_name, "vsitranslation")) { - val_ptr[41] = (char*)ext_value_p->option_value; - } else { - rv = -1; - break; - } - - parameter_length++; - switch_ext_p = switch_ext_p->next; - } - - return rv; -} -#endif -#ifndef IN_PORTVLAN_MINI -static int -parse_portvlan_invlan(struct switch_val *val) -{ - struct switch_ext *switch_ext_p, *ext_value_p; - int rv = 0; - switch_ext_p = val->value.ext_val; - while(switch_ext_p) { - ext_value_p = switch_ext_p; - - if(!strcmp(ext_value_p->option_name, "name")) { - switch_ext_p = switch_ext_p->next; - continue; - } else if(!strcmp(ext_value_p->option_name, "port_id")) { - val_ptr[0] = (char*)ext_value_p->option_value; - } else if(!strcmp(ext_value_p->option_name, "ingress_tag_mode")) { - val_ptr[1] = (char*)ext_value_p->option_value; - } else { - rv = -1; - break; - } - - parameter_length++; - switch_ext_p = switch_ext_p->next; - } - - return rv; -} - -static int -parse_portvlan_tlsmode(struct switch_val *val) -{ - struct switch_ext *switch_ext_p, *ext_value_p; - int rv = 0; - switch_ext_p = val->value.ext_val; - while(switch_ext_p) { - ext_value_p = switch_ext_p; - - if(!strcmp(ext_value_p->option_name, "name")) { - switch_ext_p = switch_ext_p->next; - continue; - } else if(!strcmp(ext_value_p->option_name, "port_id")) { - val_ptr[0] = (char*)ext_value_p->option_value; - } else if(!strcmp(ext_value_p->option_name, "tls_mode")) { - val_ptr[1] = (char*)ext_value_p->option_value; - } else { - rv = -1; - break; - } - - parameter_length++; - switch_ext_p = switch_ext_p->next; - } - - return rv; -} - -static int -parse_portvlan_pripropagation(struct switch_val *val) -{ - struct switch_ext *switch_ext_p, *ext_value_p; - int rv = 0; - switch_ext_p = val->value.ext_val; - while(switch_ext_p) { - ext_value_p = switch_ext_p; - - if(!strcmp(ext_value_p->option_name, "name")) { - switch_ext_p = switch_ext_p->next; - continue; - } else if(!strcmp(ext_value_p->option_name, "port_id")) { - val_ptr[0] = (char*)ext_value_p->option_value; - } else if(!strcmp(ext_value_p->option_name, "vlan_priority_propagation_status")) { - val_ptr[1] = (char*)ext_value_p->option_value; - } else { - rv = -1; - break; - } - - parameter_length++; - switch_ext_p = switch_ext_p->next; - } - - return rv; -} - - - -static int -parse_portvlan_vlanpropagation(struct switch_val *val) -{ - struct switch_ext *switch_ext_p, *ext_value_p; - int rv = 0; - switch_ext_p = val->value.ext_val; - while(switch_ext_p) { - ext_value_p = switch_ext_p; - - if(!strcmp(ext_value_p->option_name, "name")) { - switch_ext_p = switch_ext_p->next; - continue; - } else if(!strcmp(ext_value_p->option_name, "port_id")) { - val_ptr[0] = (char*)ext_value_p->option_value; - } else if(!strcmp(ext_value_p->option_name, "vlan_propagation_mode")) { - val_ptr[1] = (char*)ext_value_p->option_value; - } else { - rv = -1; - break; - } - - parameter_length++; - switch_ext_p = switch_ext_p->next; - } - - return rv; -} - -static int -parse_portvlan_translation(struct switch_val *val) -{ - struct switch_ext *switch_ext_p, *ext_value_p; - int rv = 0; - switch_ext_p = val->value.ext_val; - while(switch_ext_p) { - ext_value_p = switch_ext_p; - - if(!strcmp(ext_value_p->option_name, "name")) { - switch_ext_p = switch_ext_p->next; - continue; - } else if(!strcmp(ext_value_p->option_name, "port_id")) { - val_ptr[0] = (char*)ext_value_p->option_value; - } else if(!strcmp(ext_value_p->option_name, "original_vid")) { - val_ptr[1] = (char*)ext_value_p->option_value; - } else if(!strcmp(ext_value_p->option_name, "bi_direction")) { - val_ptr[2] = (char*)ext_value_p->option_value; - } else if(!strcmp(ext_value_p->option_name, "forward_direction")) { - val_ptr[3] = (char*)ext_value_p->option_value; - } else if(!strcmp(ext_value_p->option_name, "reverse_direction")) { - val_ptr[4] = (char*)ext_value_p->option_value; - } else if(!strcmp(ext_value_p->option_name, "svid")) { - val_ptr[5] = (char*)ext_value_p->option_value; - } else if(!strcmp(ext_value_p->option_name, "cvid")) { - val_ptr[6] = (char*)ext_value_p->option_value; - } else if(!strcmp(ext_value_p->option_name, "original_vid_is_cvid")) { - val_ptr[7] = (char*)ext_value_p->option_value; - } else if(!strcmp(ext_value_p->option_name, "svid_enable")) { - val_ptr[8] = (char*)ext_value_p->option_value; - } else if(!strcmp(ext_value_p->option_name, "cvid_enable")) { - val_ptr[9] = (char*)ext_value_p->option_value; - } else if(!strcmp(ext_value_p->option_name, "one_2_one_vlan")) { - val_ptr[10] = (char*)ext_value_p->option_value; - } else { - rv = -1; - break; - } - - parameter_length++; - switch_ext_p = switch_ext_p->next; - } - - return rv; -} - -static int -parse_portvlan_qinqmode(struct switch_val *val) -{ - struct switch_ext *switch_ext_p, *ext_value_p; - int rv = 0; - switch_ext_p = val->value.ext_val; - while(switch_ext_p) { - ext_value_p = switch_ext_p; - - if(!strcmp(ext_value_p->option_name, "name")) { - switch_ext_p = switch_ext_p->next; - continue; - } else if(!strcmp(ext_value_p->option_name, "port_id")) { - val_ptr[0] = (char*)ext_value_p->option_value; - } else if(!strcmp(ext_value_p->option_name, "qinq_mode")) { - val_ptr[1] = (char*)ext_value_p->option_value; - } else { - rv = -1; - break; - } - - parameter_length++; - switch_ext_p = switch_ext_p->next; - } - - return rv; -} - -static int -parse_portvlan_qinqrole(struct switch_val *val) -{ - struct switch_ext *switch_ext_p, *ext_value_p; - int rv = 0; - switch_ext_p = val->value.ext_val; - while(switch_ext_p) { - ext_value_p = switch_ext_p; - - if(!strcmp(ext_value_p->option_name, "name")) { - switch_ext_p = switch_ext_p->next; - continue; - } else if(!strcmp(ext_value_p->option_name, "port_id")) { - val_ptr[0] = (char*)ext_value_p->option_value; - } else if(!strcmp(ext_value_p->option_name, "qinq_role")) { - val_ptr[1] = (char*)ext_value_p->option_value; - } else { - rv = -1; - break; - } - - parameter_length++; - switch_ext_p = switch_ext_p->next; - } - - return rv; -} - -static int -parse_portvlan_macvlanxlt(struct switch_val *val) -{ - struct switch_ext *switch_ext_p, *ext_value_p; - int rv = 0; - switch_ext_p = val->value.ext_val; - while(switch_ext_p) { - ext_value_p = switch_ext_p; - - if(!strcmp(ext_value_p->option_name, "name")) { - switch_ext_p = switch_ext_p->next; - continue; - } else if(!strcmp(ext_value_p->option_name, "port_id")) { - val_ptr[0] = (char*)ext_value_p->option_value; - } else if(!strcmp(ext_value_p->option_name, "egress_mac_based_vlan")) { - val_ptr[1] = (char*)ext_value_p->option_value; - } else { - rv = -1; - break; - } - - parameter_length++; - switch_ext_p = switch_ext_p->next; - } - - return rv; -} - -static int -parse_portvlan_netiso(struct switch_val *val) -{ - struct switch_ext *switch_ext_p, *ext_value_p; - int rv = 0; - switch_ext_p = val->value.ext_val; - while(switch_ext_p) { - ext_value_p = switch_ext_p; - - if(!strcmp(ext_value_p->option_name, "name")) { - switch_ext_p = switch_ext_p->next; - continue; - } else if(!strcmp(ext_value_p->option_name, "net_isolate")) { - val_ptr[0] = (char*)ext_value_p->option_value; - } else { - rv = -1; - break; - } - - parameter_length++; - switch_ext_p = switch_ext_p->next; - } - - return rv; -} - -static int -parse_portvlan_egbypass(struct switch_val *val) -{ - struct switch_ext *switch_ext_p, *ext_value_p; - int rv = 0; - switch_ext_p = val->value.ext_val; - while(switch_ext_p) { - ext_value_p = switch_ext_p; - - if(!strcmp(ext_value_p->option_name, "name")) { - switch_ext_p = switch_ext_p->next; - continue; - } else if(!strcmp(ext_value_p->option_name, "egress_translation_filter_bypass")) { - val_ptr[0] = (char*)ext_value_p->option_value; - } else { - rv = -1; - break; - } - - parameter_length++; - switch_ext_p = switch_ext_p->next; - } - - return rv; -} - -static int -parse_portvlan_ptvrfid(struct switch_val *val) -{ - struct switch_ext *switch_ext_p, *ext_value_p; - int rv = 0; - switch_ext_p = val->value.ext_val; - while(switch_ext_p) { - ext_value_p = switch_ext_p; - - if(!strcmp(ext_value_p->option_name, "name")) { - switch_ext_p = switch_ext_p->next; - continue; - } else if(!strcmp(ext_value_p->option_name, "port_id")) { - val_ptr[0] = (char*)ext_value_p->option_value; - } else if(!strcmp(ext_value_p->option_name, "vrf_id")) { - val_ptr[1] = (char*)ext_value_p->option_value; - } else { - rv = -1; - break; - } - - parameter_length++; - switch_ext_p = switch_ext_p->next; - } - - return rv; -} -#endif -#endif - -#ifdef IN_VLAN -static int -parse_vlan_entry(struct switch_val *val) -{ - struct switch_ext *switch_ext_p, *ext_value_p; - int rv = 0; - switch_ext_p = val->value.ext_val; - while(switch_ext_p) { - ext_value_p = switch_ext_p; - - if(!strcmp(ext_value_p->option_name, "name")) { - switch_ext_p = switch_ext_p->next; - continue; - } else if(!strcmp(ext_value_p->option_name, "vlan_id")) { - val_ptr[0] = (char*)ext_value_p->option_value; - } else { - rv = -1; - break; - } - - parameter_length++; - switch_ext_p = switch_ext_p->next; - } - - return rv; -} - -static int -parse_vlan_member(struct switch_val *val) -{ - struct switch_ext *switch_ext_p, *ext_value_p; - int rv = 0; - switch_ext_p = val->value.ext_val; - while(switch_ext_p) { - ext_value_p = switch_ext_p; - - if(!strcmp(ext_value_p->option_name, "name")) { - switch_ext_p = switch_ext_p->next; - continue; - } else if(!strcmp(ext_value_p->option_name, "vlan_id")) { - val_ptr[0] = (char*)ext_value_p->option_value; - } else if(!strcmp(ext_value_p->option_name, "port_id")) { - val_ptr[1] = (char*)ext_value_p->option_value; - } else if(!strcmp(ext_value_p->option_name, "tag_mode")) { - val_ptr[2] = (char*)ext_value_p->option_value; - } else { - rv = -1; - break; - } - - parameter_length++; - switch_ext_p = switch_ext_p->next; - } - - return rv; -} -#ifndef IN_VLAN_MINI -static int -parse_vlan_learnsts(struct switch_val *val) -{ - struct switch_ext *switch_ext_p, *ext_value_p; - int rv = 0; - switch_ext_p = val->value.ext_val; - while(switch_ext_p) { - ext_value_p = switch_ext_p; - - if(!strcmp(ext_value_p->option_name, "name")) { - switch_ext_p = switch_ext_p->next; - continue; - } else if(!strcmp(ext_value_p->option_name, "vlan_id")) { - val_ptr[0] = (char*)ext_value_p->option_value; - } else if(!strcmp(ext_value_p->option_name, "learn_status")) { - val_ptr[1] = (char*)ext_value_p->option_value; - } else { - rv = -1; - break; - } - - parameter_length++; - switch_ext_p = switch_ext_p->next; - } - - return rv; -} -#endif -#endif - -#ifdef IN_FDB -#ifndef IN_FDB_MINI -static int -parse_fdb_entry(struct switch_val *val) -{ - struct switch_ext *switch_ext_p, *ext_value_p; - int rv = 0; - switch_ext_p = val->value.ext_val; - while(switch_ext_p) { - ext_value_p = switch_ext_p; - - if(!strcmp(ext_value_p->option_name, "name")) { - switch_ext_p = switch_ext_p->next; - continue; - } else if(!strcmp(ext_value_p->option_name, "addr")) { - val_ptr[0] = (char*)ext_value_p->option_value; - } else if(!strcmp(ext_value_p->option_name, "fid")) { - val_ptr[1] = (char*)ext_value_p->option_value; - } else if(!strcmp(ext_value_p->option_name, "dacmd")) { - val_ptr[2] = (char*)ext_value_p->option_value; - } else if(!strcmp(ext_value_p->option_name, "sacmd")) { - val_ptr[3] = (char*)ext_value_p->option_value; - } else if(!strcmp(ext_value_p->option_name, "dest_port")) { - val_ptr[4] = (char*)ext_value_p->option_value; - } else if(!strcmp(ext_value_p->option_name, "static")) { - val_ptr[5] = (char*)ext_value_p->option_value; - } else if(!strcmp(ext_value_p->option_name, "leaky")) { - val_ptr[6] = (char*)ext_value_p->option_value; - } else if(!strcmp(ext_value_p->option_name, "mirror")) { - val_ptr[7] = (char*)ext_value_p->option_value; - } else if(!strcmp(ext_value_p->option_name, "clone")) { - val_ptr[8] = (char*)ext_value_p->option_value; - } else if(!strcmp(ext_value_p->option_name, "queue_override")) { - val_ptr[9] = (char*)ext_value_p->option_value; - } else if(!strcmp(ext_value_p->option_name, "cross_pt_state")) { - val_ptr[10] = (char*)ext_value_p->option_value; - } else if(!strcmp(ext_value_p->option_name, "white_list_en")) { - val_ptr[11] = (char*)ext_value_p->option_value; - } else if(!strcmp(ext_value_p->option_name, "load_balance_en")) { - val_ptr[12] = (char*)ext_value_p->option_value; - } else if(!strcmp(ext_value_p->option_name, "load_balance")) { - val_ptr[13] = (char*)ext_value_p->option_value; - } else { - rv = -1; - break; - } - - parameter_length++; - switch_ext_p = switch_ext_p->next; - } - - if(val_ptr[12] == NULL) { - val_ptr[12] = "no"; - parameter_length++; - } - return rv; -} - -static int -parse_fdb_resventry(struct switch_val *val) -{ - struct switch_ext *switch_ext_p, *ext_value_p; - int rv = 0; - switch_ext_p = val->value.ext_val; - while(switch_ext_p) { - ext_value_p = switch_ext_p; - - if(!strcmp(ext_value_p->option_name, "name")) { - switch_ext_p = switch_ext_p->next; - continue; - } else if(!strcmp(ext_value_p->option_name, "addr")) { - val_ptr[0] = (char*)ext_value_p->option_value; - } else if(!strcmp(ext_value_p->option_name, "fid")) { - val_ptr[1] = (char*)ext_value_p->option_value; - } else if(!strcmp(ext_value_p->option_name, "dacmd")) { - val_ptr[2] = (char*)ext_value_p->option_value; - } else if(!strcmp(ext_value_p->option_name, "sacmd")) { - val_ptr[3] = (char*)ext_value_p->option_value; - } else if(!strcmp(ext_value_p->option_name, "dest_port")) { - val_ptr[4] = (char*)ext_value_p->option_value; - } else if(!strcmp(ext_value_p->option_name, "static")) { - val_ptr[5] = (char*)ext_value_p->option_value; - } else if(!strcmp(ext_value_p->option_name, "leaky")) { - val_ptr[6] = (char*)ext_value_p->option_value; - } else if(!strcmp(ext_value_p->option_name, "mirror")) { - val_ptr[7] = (char*)ext_value_p->option_value; - } else if(!strcmp(ext_value_p->option_name, "clone")) { - val_ptr[8] = (char*)ext_value_p->option_value; - } else if(!strcmp(ext_value_p->option_name, "queue_override")) { - val_ptr[9] = (char*)ext_value_p->option_value; - } else if(!strcmp(ext_value_p->option_name, "cross_pt_state")) { - val_ptr[10] = (char*)ext_value_p->option_value; - } else if(!strcmp(ext_value_p->option_name, "white_list_en")) { - val_ptr[11] = (char*)ext_value_p->option_value; - } else { - rv = -1; - break; - } - - parameter_length++; - switch_ext_p = switch_ext_p->next; - } - - return rv; -} -#endif -static int -parse_fdb_portlearn(struct switch_val *val) -{ - struct switch_ext *switch_ext_p, *ext_value_p; - int rv = 0; - switch_ext_p = val->value.ext_val; - while(switch_ext_p) { - ext_value_p = switch_ext_p; - - if(!strcmp(ext_value_p->option_name, "name")) { - switch_ext_p = switch_ext_p->next; - continue; - } else if(!strcmp(ext_value_p->option_name, "port_id")) { - val_ptr[0] = (char*)ext_value_p->option_value; - } else if(!strcmp(ext_value_p->option_name, "learn_status")) { - val_ptr[1] = (char*)ext_value_p->option_value; - } else { - rv = -1; - break; - } - - parameter_length++; - switch_ext_p = switch_ext_p->next; - } - - return rv; -} -#ifndef IN_FDB_MINI -static int -parse_fdb_agectrl(struct switch_val *val) -{ - struct switch_ext *switch_ext_p, *ext_value_p; - int rv = 0; - switch_ext_p = val->value.ext_val; - while(switch_ext_p) { - ext_value_p = switch_ext_p; - - if(!strcmp(ext_value_p->option_name, "name")) { - switch_ext_p = switch_ext_p->next; - continue; - } else if(!strcmp(ext_value_p->option_name, "aging_status")) { - val_ptr[0] = (char*)ext_value_p->option_value; - } else { - rv = -1; - break; - } - - parameter_length++; - switch_ext_p = switch_ext_p->next; - } - - return rv; -} - -static int -parse_fdb_agetime(struct switch_val *val) -{ - struct switch_ext *switch_ext_p, *ext_value_p; - int rv = 0; - switch_ext_p = val->value.ext_val; - while(switch_ext_p) { - ext_value_p = switch_ext_p; - - if(!strcmp(ext_value_p->option_name, "name")) { - switch_ext_p = switch_ext_p->next; - continue; - } else if(!strcmp(ext_value_p->option_name, "aging_time")) { - val_ptr[0] = (char*)ext_value_p->option_value; - } else { - rv = -1; - break; - } - - parameter_length++; - switch_ext_p = switch_ext_p->next; - } - - return rv; -} - -static int -parse_fdb_vlansmode(struct switch_val *val) -{ - struct switch_ext *switch_ext_p, *ext_value_p; - int rv = 0; - switch_ext_p = val->value.ext_val; - while(switch_ext_p) { - ext_value_p = switch_ext_p; - - if(!strcmp(ext_value_p->option_name, "name")) { - switch_ext_p = switch_ext_p->next; - continue; - } else if(!strcmp(ext_value_p->option_name, "vlan_searching_mode")) { - val_ptr[0] = (char*)ext_value_p->option_value; - } else { - rv = -1; - break; - } - - parameter_length++; - switch_ext_p = switch_ext_p->next; - } - - return rv; -} - -static int -parse_fdb_ptlearnlimit(struct switch_val *val) -{ - struct switch_ext *switch_ext_p, *ext_value_p; - int rv = 0; - switch_ext_p = val->value.ext_val; - while(switch_ext_p) { - ext_value_p = switch_ext_p; - - if(!strcmp(ext_value_p->option_name, "name")) { - switch_ext_p = switch_ext_p->next; - continue; - } else if(!strcmp(ext_value_p->option_name, "port_id")) { - val_ptr[0] = (char*)ext_value_p->option_value; - } else if(!strcmp(ext_value_p->option_name, "learn_limit_status")) { - val_ptr[1] = (char*)ext_value_p->option_value; - } else if(!strcmp(ext_value_p->option_name, "learn_limit_counter")) { - val_ptr[2] = (char*)ext_value_p->option_value; - } else { - rv = -1; - break; - } - - parameter_length++; - switch_ext_p = switch_ext_p->next; - } - - return rv; -} - -static int -parse_fdb_ptlearnexceedcmd(struct switch_val *val) -{ - struct switch_ext *switch_ext_p, *ext_value_p; - int rv = 0; - switch_ext_p = val->value.ext_val; - while(switch_ext_p) { - ext_value_p = switch_ext_p; - - if(!strcmp(ext_value_p->option_name, "name")) { - switch_ext_p = switch_ext_p->next; - continue; - } else if(!strcmp(ext_value_p->option_name, "port_id")) { - val_ptr[0] = (char*)ext_value_p->option_value; - } else if(!strcmp(ext_value_p->option_name, "learn_exceed_cmd")) { - val_ptr[1] = (char*)ext_value_p->option_value; - } else { - rv = -1; - break; - } - - parameter_length++; - switch_ext_p = switch_ext_p->next; - } - - return rv; -} - -static int -parse_fdb_learnlimit(struct switch_val *val) -{ - struct switch_ext *switch_ext_p, *ext_value_p; - int rv = 0; - switch_ext_p = val->value.ext_val; - while(switch_ext_p) { - ext_value_p = switch_ext_p; - - if(!strcmp(ext_value_p->option_name, "name")) { - switch_ext_p = switch_ext_p->next; - continue; - } else if(!strcmp(ext_value_p->option_name, "learn_limit_status")) { - val_ptr[0] = (char*)ext_value_p->option_value; - } else if(!strcmp(ext_value_p->option_name, "learn_limit_counter")) { - val_ptr[1] = (char*)ext_value_p->option_value; - } else { - rv = -1; - break; - } - - parameter_length++; - switch_ext_p = switch_ext_p->next; - } - - return rv; -} - -static int -parse_fdb_learnexceedcmd(struct switch_val *val) -{ - struct switch_ext *switch_ext_p, *ext_value_p; - int rv = 0; - switch_ext_p = val->value.ext_val; - while(switch_ext_p) { - ext_value_p = switch_ext_p; - - if(!strcmp(ext_value_p->option_name, "name")) { - switch_ext_p = switch_ext_p->next; - continue; - } else if(!strcmp(ext_value_p->option_name, "learn_exceed_cmd")) { - val_ptr[0] = (char*)ext_value_p->option_value; - } else { - rv = -1; - break; - } - - parameter_length++; - switch_ext_p = switch_ext_p->next; - } - - return rv; -} - -static int -parse_fdb_ptlearnstatic(struct switch_val *val) -{ - struct switch_ext *switch_ext_p, *ext_value_p; - int rv = 0; - switch_ext_p = val->value.ext_val; - while(switch_ext_p) { - ext_value_p = switch_ext_p; - - if(!strcmp(ext_value_p->option_name, "name")) { - switch_ext_p = switch_ext_p->next; - continue; - } else if(!strcmp(ext_value_p->option_name, "port_id")) { - val_ptr[0] = (char*)ext_value_p->option_value; - } else if(!strcmp(ext_value_p->option_name, "learn_static_status")) { - val_ptr[1] = (char*)ext_value_p->option_value; - } else { - rv = -1; - break; - } - - parameter_length++; - switch_ext_p = switch_ext_p->next; - } - - return rv; -} - -static int -parse_fdb_learnctrl(struct switch_val *val) -{ - struct switch_ext *switch_ext_p, *ext_value_p; - int rv = 0; - - switch_ext_p = val->value.ext_val; - while (switch_ext_p) { - ext_value_p = switch_ext_p; - - if (!strcmp(ext_value_p->option_name, "name")) { - switch_ext_p = switch_ext_p->next; - continue; - } else if (!strcmp(ext_value_p->option_name, "learn_status")) { - val_ptr[0] = (char*)ext_value_p->option_value; - } else { - rv = -1; - break; - } - - parameter_length++; - switch_ext_p = switch_ext_p->next; - } - - return rv; -} - -static int -parse_fdb_ptlearnctrl(struct switch_val *val) -{ - struct switch_ext *switch_ext_p, *ext_value_p; - int rv = 0; - - switch_ext_p = val->value.ext_val; - while (switch_ext_p) { - ext_value_p = switch_ext_p; - - if (!strcmp(ext_value_p->option_name, "name")) { - switch_ext_p = switch_ext_p->next; - continue; - } else if (!strcmp(ext_value_p->option_name, "port_id")) { - val_ptr[0] = (char*)ext_value_p->option_value; - } else if (!strcmp(ext_value_p->option_name, "learn_status")) { - val_ptr[1] = (char*)ext_value_p->option_value; - } else if (!strcmp(ext_value_p->option_name, "learnaction")) { - val_ptr[2] = (char*)ext_value_p->option_value; - } else { - rv = -1; - break; - } - - parameter_length++; - switch_ext_p = switch_ext_p->next; - } - - return rv; -} - -static int -parse_fdb_ptstationmove(struct switch_val *val) -{ - struct switch_ext *switch_ext_p, *ext_value_p; - int rv = 0; - - switch_ext_p = val->value.ext_val; - while (switch_ext_p) { - ext_value_p = switch_ext_p; - - if (!strcmp(ext_value_p->option_name, "name")) { - switch_ext_p = switch_ext_p->next; - continue; - } else if (!strcmp(ext_value_p->option_name, "port_id")) { - val_ptr[0] = (char*)ext_value_p->option_value; - } else if (!strcmp(ext_value_p->option_name, "stationmove_en")) { - val_ptr[1] = (char*)ext_value_p->option_value; - } else if (!strcmp(ext_value_p->option_name, "stationmove_action")) { - val_ptr[2] = (char*)ext_value_p->option_value; - } else { - rv = -1; - break; - } - - parameter_length++; - switch_ext_p = switch_ext_p->next; - } - - return rv; -} - -static int -parse_fdb_ptmaclimitctrl(struct switch_val *val) -{ - struct switch_ext *switch_ext_p, *ext_value_p; - int rv = 0; - - switch_ext_p = val->value.ext_val; - while (switch_ext_p) { - ext_value_p = switch_ext_p; - - if (!strcmp(ext_value_p->option_name, "name")) { - switch_ext_p = switch_ext_p->next; - continue; - } else if (!strcmp(ext_value_p->option_name, "port_id")) { - val_ptr[0] = (char*)ext_value_p->option_value; - } else if (!strcmp(ext_value_p->option_name, "maclimit_status")) { - val_ptr[1] = (char*)ext_value_p->option_value; - } else if (!strcmp(ext_value_p->option_name, "maclimit_counter")) { - val_ptr[2] = (char*)ext_value_p->option_value; - } else if (!strcmp(ext_value_p->option_name, "maclimit_exceed_action")) { - val_ptr[3] = (char*)ext_value_p->option_value; - } else { - rv = -1; - break; - } - - parameter_length++; - switch_ext_p = switch_ext_p->next; - } - - return rv; -} -#endif -#endif - -#ifdef IN_RSS_HASH -static int -parse_rsshash_config(struct switch_val *val) -{ - struct switch_ext *switch_ext_p, *ext_value_p; - int rv = 0; - - switch_ext_p = val->value.ext_val; - while (switch_ext_p) { - ext_value_p = switch_ext_p; - - if (!strcmp(ext_value_p->option_name, "name")) { - switch_ext_p = switch_ext_p->next; - continue; - } else if (!strcmp(ext_value_p->option_name, "hash_mode")) { - val_ptr[0] = (char*)ext_value_p->option_value; - } else if (!strcmp(ext_value_p->option_name, "hask_mask")) { - val_ptr[1] = (char*)ext_value_p->option_value; - } else if (!strcmp(ext_value_p->option_name, "hash_fragment_mode")) { - val_ptr[2] = (char*)ext_value_p->option_value; - } else if (!strcmp(ext_value_p->option_name, "hash_seed")) { - val_ptr[3] = (char*)ext_value_p->option_value; - } else if (!strcmp(ext_value_p->option_name, "hash_sip_mix")) { - val_ptr[4] = (char*)ext_value_p->option_value; - } else if (!strcmp(ext_value_p->option_name, "hash_dip_mix")) { - val_ptr[5] = (char*)ext_value_p->option_value; - } else if (!strcmp(ext_value_p->option_name, "hash_protocol_mix")) { - val_ptr[6] = (char*)ext_value_p->option_value; - } else if (!strcmp(ext_value_p->option_name, "hash_sport_mix")) { - val_ptr[7] = (char*)ext_value_p->option_value; - } else if (!strcmp(ext_value_p->option_name, "hash_dport_mix")) { - val_ptr[8] = (char*)ext_value_p->option_value; - } else if (!strcmp(ext_value_p->option_name, "hash_fin_inner")) { - val_ptr[9] = (char*)ext_value_p->option_value; - } else if (!strcmp(ext_value_p->option_name, "hash_fin_outer")) { - val_ptr[10] = (char*)ext_value_p->option_value; - } else { - rv = -1; - break; - } - - parameter_length++; - switch_ext_p = switch_ext_p->next; - } - - return rv; -} -#endif - -#ifdef IN_IGMP -static int -parse_igmp_mode(struct switch_val *val) -{ - struct switch_ext *switch_ext_p, *ext_value_p; - int rv = 0; - switch_ext_p = val->value.ext_val; - while(switch_ext_p) { - ext_value_p = switch_ext_p; - - if(!strcmp(ext_value_p->option_name, "name")) { - switch_ext_p = switch_ext_p->next; - continue; - } else if(!strcmp(ext_value_p->option_name, "port_id")) { - val_ptr[0] = (char*)ext_value_p->option_value; - } else if(!strcmp(ext_value_p->option_name, "igmp_mode")) { - val_ptr[1] = (char*)ext_value_p->option_value; - } else { - rv = -1; - break; - } - - parameter_length++; - switch_ext_p = switch_ext_p->next; - } - - return rv; -} - -static int -parse_igmp_cmd(struct switch_val *val) -{ - struct switch_ext *switch_ext_p, *ext_value_p; - int rv = 0; - switch_ext_p = val->value.ext_val; - while(switch_ext_p) { - ext_value_p = switch_ext_p; - - if(!strcmp(ext_value_p->option_name, "name")) { - switch_ext_p = switch_ext_p->next; - continue; - } else if(!strcmp(ext_value_p->option_name, "igmp_command")) { - val_ptr[0] = (char*)ext_value_p->option_value; - } else { - rv = -1; - break; - } - - parameter_length++; - switch_ext_p = switch_ext_p->next; - } - - return rv; -} - -static int -parse_igmp_portjoin(struct switch_val *val) -{ - struct switch_ext *switch_ext_p, *ext_value_p; - int rv = 0; - switch_ext_p = val->value.ext_val; - while(switch_ext_p) { - ext_value_p = switch_ext_p; - - if(!strcmp(ext_value_p->option_name, "name")) { - switch_ext_p = switch_ext_p->next; - continue; - } else if(!strcmp(ext_value_p->option_name, "port_id")) { - val_ptr[0] = (char*)ext_value_p->option_value; - } else if(!strcmp(ext_value_p->option_name, "join_status")) { - val_ptr[1] = (char*)ext_value_p->option_value; - } else { - rv = -1; - break; - } - - parameter_length++; - switch_ext_p = switch_ext_p->next; - } - - return rv; -} - -static int -parse_igmp_portleave(struct switch_val *val) -{ - struct switch_ext *switch_ext_p, *ext_value_p; - int rv = 0; - switch_ext_p = val->value.ext_val; - while(switch_ext_p) { - ext_value_p = switch_ext_p; - - if(!strcmp(ext_value_p->option_name, "name")) { - switch_ext_p = switch_ext_p->next; - continue; - } else if(!strcmp(ext_value_p->option_name, "port_id")) { - val_ptr[0] = (char*)ext_value_p->option_value; - } else if(!strcmp(ext_value_p->option_name, "leave_status")) { - val_ptr[1] = (char*)ext_value_p->option_value; - } else { - rv = -1; - break; - } - - parameter_length++; - switch_ext_p = switch_ext_p->next; - } - - return rv; -} - -static int -parse_igmp_rp(struct switch_val *val) -{ - struct switch_ext *switch_ext_p, *ext_value_p; - int rv = 0; - switch_ext_p = val->value.ext_val; - while(switch_ext_p) { - ext_value_p = switch_ext_p; - - if(!strcmp(ext_value_p->option_name, "name")) { - switch_ext_p = switch_ext_p->next; - continue; - } else if(!strcmp(ext_value_p->option_name, "route_port_bitmap")) { - val_ptr[0] = (char*)ext_value_p->option_value; - } else { - rv = -1; - break; - } - - parameter_length++; - switch_ext_p = switch_ext_p->next; - } - - return rv; -} - -static int -parse_igmp_createstatus(struct switch_val *val) -{ - struct switch_ext *switch_ext_p, *ext_value_p; - int rv = 0; - switch_ext_p = val->value.ext_val; - while(switch_ext_p) { - ext_value_p = switch_ext_p; - - if(!strcmp(ext_value_p->option_name, "name")) { - switch_ext_p = switch_ext_p->next; - continue; - } else if(!strcmp(ext_value_p->option_name, "create_status")) { - val_ptr[0] = (char*)ext_value_p->option_value; - } else { - rv = -1; - break; - } - - parameter_length++; - switch_ext_p = switch_ext_p->next; - } - - return rv; -} - -static int -parse_igmp_static(struct switch_val *val) -{ - struct switch_ext *switch_ext_p, *ext_value_p; - int rv = 0; - switch_ext_p = val->value.ext_val; - while(switch_ext_p) { - ext_value_p = switch_ext_p; - - if(!strcmp(ext_value_p->option_name, "name")) { - switch_ext_p = switch_ext_p->next; - continue; - } else if(!strcmp(ext_value_p->option_name, "static_status")) { - val_ptr[0] = (char*)ext_value_p->option_value; - } else { - rv = -1; - break; - } - - parameter_length++; - switch_ext_p = switch_ext_p->next; - } - - return rv; -} - -static int -parse_igmp_leaky(struct switch_val *val) -{ - struct switch_ext *switch_ext_p, *ext_value_p; - int rv = 0; - switch_ext_p = val->value.ext_val; - while(switch_ext_p) { - ext_value_p = switch_ext_p; - - if(!strcmp(ext_value_p->option_name, "name")) { - switch_ext_p = switch_ext_p->next; - continue; - } else if(!strcmp(ext_value_p->option_name, "leaky_status")) { - val_ptr[0] = (char*)ext_value_p->option_value; - } else { - rv = -1; - break; - } - - parameter_length++; - switch_ext_p = switch_ext_p->next; - } - - return rv; -} - -static int -parse_igmp_version3(struct switch_val *val) -{ - struct switch_ext *switch_ext_p, *ext_value_p; - int rv = 0; - switch_ext_p = val->value.ext_val; - while(switch_ext_p) { - ext_value_p = switch_ext_p; - - if(!strcmp(ext_value_p->option_name, "name")) { - switch_ext_p = switch_ext_p->next; - continue; - } else if(!strcmp(ext_value_p->option_name, "version3_status")) { - val_ptr[0] = (char*)ext_value_p->option_value; - } else { - rv = -1; - break; - } - - parameter_length++; - switch_ext_p = switch_ext_p->next; - } - - return rv; -} - -static int -parse_igmp_queue(struct switch_val *val) -{ - struct switch_ext *switch_ext_p, *ext_value_p; - int rv = 0; - switch_ext_p = val->value.ext_val; - while(switch_ext_p) { - ext_value_p = switch_ext_p; - - if(!strcmp(ext_value_p->option_name, "name")) { - switch_ext_p = switch_ext_p->next; - continue; - } else if(!strcmp(ext_value_p->option_name, "status")) { - val_ptr[0] = (char*)ext_value_p->option_value; - } else if(!strcmp(ext_value_p->option_name, "queue_id")) { - val_ptr[1] = (char*)ext_value_p->option_value; - } else { - rv = -1; - break; - } - - parameter_length++; - switch_ext_p = switch_ext_p->next; - } - - return rv; -} - -static int -parse_igmp_ptlearnlimit(struct switch_val *val) -{ - struct switch_ext *switch_ext_p, *ext_value_p; - int rv = 0; - switch_ext_p = val->value.ext_val; - while(switch_ext_p) { - ext_value_p = switch_ext_p; - - if(!strcmp(ext_value_p->option_name, "name")) { - switch_ext_p = switch_ext_p->next; - continue; - } else if(!strcmp(ext_value_p->option_name, "port_id")) { - val_ptr[0] = (char*)ext_value_p->option_value; - } else if(!strcmp(ext_value_p->option_name, "learn_limit_status")) { - val_ptr[1] = (char*)ext_value_p->option_value; - } else if(!strcmp(ext_value_p->option_name, "learn_limit_counter")) { - val_ptr[2] = (char*)ext_value_p->option_value; - } else { - rv = -1; - break; - } - - parameter_length++; - switch_ext_p = switch_ext_p->next; - } - - return rv; -} - -static int -parse_igmp_ptlearnexceedcmd(struct switch_val *val) -{ - struct switch_ext *switch_ext_p, *ext_value_p; - int rv = 0; - switch_ext_p = val->value.ext_val; - while(switch_ext_p) { - ext_value_p = switch_ext_p; - - if(!strcmp(ext_value_p->option_name, "name")) { - switch_ext_p = switch_ext_p->next; - continue; - } else if(!strcmp(ext_value_p->option_name, "port_id")) { - val_ptr[0] = (char*)ext_value_p->option_value; - } else if(!strcmp(ext_value_p->option_name, "learn_exceed_cmd")) { - val_ptr[1] = (char*)ext_value_p->option_value; - } else { - rv = -1; - break; - } - - parameter_length++; - switch_ext_p = switch_ext_p->next; - } - - return rv; -} - -static int -parse_igmp_multi(struct switch_val *val) -{ - struct switch_ext *switch_ext_p, *ext_value_p; - int rv = 0; - switch_ext_p = val->value.ext_val; - while(switch_ext_p) { - ext_value_p = switch_ext_p; - - if(!strcmp(ext_value_p->option_name, "name")) { - switch_ext_p = switch_ext_p->next; - continue; - } else if(!strcmp(ext_value_p->option_name, "group_type")) { - val_ptr[0] = (char*)ext_value_p->option_value; - } else if(!strcmp(ext_value_p->option_name, "group_ip_addr")) { - val_ptr[1] = (char*)ext_value_p->option_value; - } else if(!strcmp(ext_value_p->option_name, "source_type")) { - val_ptr[2] = (char*)ext_value_p->option_value; - } else if(!strcmp(ext_value_p->option_name, "source_ip_addr")) { - val_ptr[3] = (char*)ext_value_p->option_value; - } else if(!strcmp(ext_value_p->option_name, "portmap")) { - val_ptr[4] = (char*)ext_value_p->option_value; - } else if(!strcmp(ext_value_p->option_name, "vlanid")) { - val_ptr[5] = (char*)ext_value_p->option_value; - } else { - rv = -1; - break; - } - - parameter_length++; - switch_ext_p = switch_ext_p->next; - } - - return rv; -} -#endif - -#ifdef IN_SEC -static int -parse_sec_mac(struct switch_val *val) -{ - struct switch_ext *switch_ext_p, *ext_value_p; - int rv = 0; - switch_ext_p = val->value.ext_val; - while(switch_ext_p) { - ext_value_p = switch_ext_p; - - if(!strcmp(ext_value_p->option_name, "name")) { - switch_ext_p = switch_ext_p->next; - continue; - } else if(!strcmp(ext_value_p->option_name, "item")) { - val_ptr[0] = (char*)ext_value_p->option_value; - } else if(!strcmp(ext_value_p->option_name, "value")) { - val_ptr[1] = (char*)ext_value_p->option_value; - } else { - rv = -1; - break; - } - - parameter_length++; - switch_ext_p = switch_ext_p->next; - } - - return rv; -} - -static int -parse_sec_ip(struct switch_val *val) -{ - struct switch_ext *switch_ext_p, *ext_value_p; - int rv = 0; - switch_ext_p = val->value.ext_val; - while(switch_ext_p) { - ext_value_p = switch_ext_p; - - if(!strcmp(ext_value_p->option_name, "name")) { - switch_ext_p = switch_ext_p->next; - continue; - } else if(!strcmp(ext_value_p->option_name, "item")) { - val_ptr[0] = (char*)ext_value_p->option_value; - } else if(!strcmp(ext_value_p->option_name, "value")) { - val_ptr[1] = (char*)ext_value_p->option_value; - } else { - rv = -1; - break; - } - - parameter_length++; - switch_ext_p = switch_ext_p->next; - } - - return rv; -} - -static int -parse_sec_ip4(struct switch_val *val) -{ - struct switch_ext *switch_ext_p, *ext_value_p; - int rv = 0; - switch_ext_p = val->value.ext_val; - while(switch_ext_p) { - ext_value_p = switch_ext_p; - - if(!strcmp(ext_value_p->option_name, "name")) { - switch_ext_p = switch_ext_p->next; - continue; - } else if(!strcmp(ext_value_p->option_name, "item")) { - val_ptr[0] = (char*)ext_value_p->option_value; - } else if(!strcmp(ext_value_p->option_name, "value")) { - val_ptr[1] = (char*)ext_value_p->option_value; - } else { - rv = -1; - break; - } - - parameter_length++; - switch_ext_p = switch_ext_p->next; - } - - return rv; -} - -static int -parse_sec_ip6(struct switch_val *val) -{ - struct switch_ext *switch_ext_p, *ext_value_p; - int rv = 0; - switch_ext_p = val->value.ext_val; - while(switch_ext_p) { - ext_value_p = switch_ext_p; - - if(!strcmp(ext_value_p->option_name, "name")) { - switch_ext_p = switch_ext_p->next; - continue; - } else if(!strcmp(ext_value_p->option_name, "item")) { - val_ptr[0] = (char*)ext_value_p->option_value; - } else if(!strcmp(ext_value_p->option_name, "value")) { - val_ptr[1] = (char*)ext_value_p->option_value; - } else { - rv = -1; - break; - } - - parameter_length++; - switch_ext_p = switch_ext_p->next; - } - - return rv; -} - -static int -parse_sec_tcp(struct switch_val *val) -{ - struct switch_ext *switch_ext_p, *ext_value_p; - int rv = 0; - switch_ext_p = val->value.ext_val; - while(switch_ext_p) { - ext_value_p = switch_ext_p; - - if(!strcmp(ext_value_p->option_name, "name")) { - switch_ext_p = switch_ext_p->next; - continue; - } else if(!strcmp(ext_value_p->option_name, "item")) { - val_ptr[0] = (char*)ext_value_p->option_value; - } else if(!strcmp(ext_value_p->option_name, "value")) { - val_ptr[1] = (char*)ext_value_p->option_value; - } else { - rv = -1; - break; - } - - parameter_length++; - switch_ext_p = switch_ext_p->next; - } - - return rv; -} - -static int -parse_sec_udp(struct switch_val *val) -{ - struct switch_ext *switch_ext_p, *ext_value_p; - int rv = 0; - switch_ext_p = val->value.ext_val; - while(switch_ext_p) { - ext_value_p = switch_ext_p; - - if(!strcmp(ext_value_p->option_name, "name")) { - switch_ext_p = switch_ext_p->next; - continue; - } else if(!strcmp(ext_value_p->option_name, "item")) { - val_ptr[0] = (char*)ext_value_p->option_value; - } else if(!strcmp(ext_value_p->option_name, "value")) { - val_ptr[1] = (char*)ext_value_p->option_value; - } else { - rv = -1; - break; - } - - parameter_length++; - switch_ext_p = switch_ext_p->next; - } - - return rv; -} - -static int -parse_sec_icmp4(struct switch_val *val) -{ - struct switch_ext *switch_ext_p, *ext_value_p; - int rv = 0; - switch_ext_p = val->value.ext_val; - while(switch_ext_p) { - ext_value_p = switch_ext_p; - - if(!strcmp(ext_value_p->option_name, "name")) { - switch_ext_p = switch_ext_p->next; - continue; - } else if(!strcmp(ext_value_p->option_name, "item")) { - val_ptr[0] = (char*)ext_value_p->option_value; - } else if(!strcmp(ext_value_p->option_name, "value")) { - val_ptr[1] = (char*)ext_value_p->option_value; - } else { - rv = -1; - break; - } - - parameter_length++; - switch_ext_p = switch_ext_p->next; - } - - return rv; -} - -static int -parse_sec_icmp6(struct switch_val *val) -{ - struct switch_ext *switch_ext_p, *ext_value_p; - int rv = 0; - switch_ext_p = val->value.ext_val; - while(switch_ext_p) { - ext_value_p = switch_ext_p; - - if(!strcmp(ext_value_p->option_name, "name")) { - switch_ext_p = switch_ext_p->next; - continue; - } else if(!strcmp(ext_value_p->option_name, "item")) { - val_ptr[0] = (char*)ext_value_p->option_value; - } else if(!strcmp(ext_value_p->option_name, "value")) { - val_ptr[1] = (char*)ext_value_p->option_value; - } else { - rv = -1; - break; - } - - parameter_length++; - switch_ext_p = switch_ext_p->next; - } - - return rv; -} -#ifdef HPPE -static int -parse_sec_expctrl(struct switch_val *val) -{ - struct switch_ext *switch_ext_p, *ext_value_p; - int rv = 0; - - switch_ext_p = val->value.ext_val; - while (switch_ext_p) { - ext_value_p = switch_ext_p; - - if (!strcmp(ext_value_p->option_name, "name")) { - switch_ext_p = switch_ext_p->next; - continue; - } else if (!strcmp(ext_value_p->option_name, "excep_type")) { - val_ptr[0] = (char*)ext_value_p->option_value; - } else if (!strcmp(ext_value_p->option_name, "excep_cmd")) { - val_ptr[1] = (char*)ext_value_p->option_value; - } else if (!strcmp(ext_value_p->option_name, "deacclr_en")) { - val_ptr[2] = (char*)ext_value_p->option_value; - } else if (!strcmp(ext_value_p->option_name, "l3route_only_en")) { - val_ptr[3] = (char*)ext_value_p->option_value; - } else if (!strcmp(ext_value_p->option_name, "l2fwd_only_en")) { - val_ptr[4] = (char*)ext_value_p->option_value; - } else if (!strcmp(ext_value_p->option_name, "l2flow_en")) { - val_ptr[5] = (char*)ext_value_p->option_value; - } else if (!strcmp(ext_value_p->option_name, "l3flow_en")) { - val_ptr[6] = (char*)ext_value_p->option_value; - } else if (!strcmp(ext_value_p->option_name, "multicast_en")) { - val_ptr[7] = (char*)ext_value_p->option_value; - } else { - rv = -1; - break; - } - - parameter_length++; - switch_ext_p = switch_ext_p->next; - } - - return rv; -} - -static int -parse_sec_l3parser(struct switch_val *val) -{ - struct switch_ext *switch_ext_p, *ext_value_p; - int rv = 0; - - switch_ext_p = val->value.ext_val; - while (switch_ext_p) { - ext_value_p = switch_ext_p; - - if (!strcmp(ext_value_p->option_name, "name")) { - switch_ext_p = switch_ext_p->next; - continue; - } else if (!strcmp(ext_value_p->option_name, "small_ip4ttl")) { - val_ptr[0] = (char*)ext_value_p->option_value; - } else if (!strcmp(ext_value_p->option_name, "small_ip6hoplimit")) { - val_ptr[1] = (char*)ext_value_p->option_value; - } else { - rv = -1; - break; - } - - parameter_length++; - switch_ext_p = switch_ext_p->next; - } - - return rv; -} - -static int -parse_sec_l4parser(struct switch_val *val) -{ - struct switch_ext *switch_ext_p, *ext_value_p; - int rv = 0; - - switch_ext_p = val->value.ext_val; - while (switch_ext_p) { - ext_value_p = switch_ext_p; - - if (!strcmp(ext_value_p->option_name, "name")) { - switch_ext_p = switch_ext_p->next; - continue; - } else if (!strcmp(ext_value_p->option_name, "tcpflag0")) { - val_ptr[0] = (char*)ext_value_p->option_value; - } else if (!strcmp(ext_value_p->option_name, "tcpflag0_mask")) { - val_ptr[1] = (char*)ext_value_p->option_value; - } else if (!strcmp(ext_value_p->option_name, "tcpflag1")) { - val_ptr[2] = (char*)ext_value_p->option_value; - } else if (!strcmp(ext_value_p->option_name, "tcpflag1_mask")) { - val_ptr[3] = (char*)ext_value_p->option_value; - } else if (!strcmp(ext_value_p->option_name, "tcpflag2")) { - val_ptr[4] = (char*)ext_value_p->option_value; - } else if (!strcmp(ext_value_p->option_name, "tcpflag2_mask")) { - val_ptr[5] = (char*)ext_value_p->option_value; - } else if (!strcmp(ext_value_p->option_name, "tcpflag3")) { - val_ptr[6] = (char*)ext_value_p->option_value; - } else if (!strcmp(ext_value_p->option_name, "tcpflag3_mask")) { - val_ptr[7] = (char*)ext_value_p->option_value; - } else if (!strcmp(ext_value_p->option_name, "tcpflag4")) { - val_ptr[8] = (char*)ext_value_p->option_value; - } else if (!strcmp(ext_value_p->option_name, "tcpflag4_mask")) { - val_ptr[9] = (char*)ext_value_p->option_value; - } else if (!strcmp(ext_value_p->option_name, "tcpflag5")) { - val_ptr[10] = (char*)ext_value_p->option_value; - } else if (!strcmp(ext_value_p->option_name, "tcpflag5_mask")) { - val_ptr[11] = (char*)ext_value_p->option_value; - } else if (!strcmp(ext_value_p->option_name, "tcpflag6")) { - val_ptr[12] = (char*)ext_value_p->option_value; - } else if (!strcmp(ext_value_p->option_name, "tcpflag6_mask")) { - val_ptr[13] = (char*)ext_value_p->option_value; - } else if (!strcmp(ext_value_p->option_name, "tcpflag7")) { - val_ptr[14] = (char*)ext_value_p->option_value; - } else if (!strcmp(ext_value_p->option_name, "tcpflag7_mask")) { - val_ptr[15] = (char*)ext_value_p->option_value; - } else { - rv = -1; - break; - } - - parameter_length++; - switch_ext_p = switch_ext_p->next; - } - - return rv; -} -#endif -#endif - -#ifdef IN_MISC -#ifndef IN_MISC_MINI -static int -parse_misc_framemaxsize(struct switch_val *val) -{ - struct switch_ext *switch_ext_p, *ext_value_p; - int rv = 0; - switch_ext_p = val->value.ext_val; - while(switch_ext_p) { - ext_value_p = switch_ext_p; - - if(!strcmp(ext_value_p->option_name, "name")) { - switch_ext_p = switch_ext_p->next; - continue; - } else if(!strcmp(ext_value_p->option_name, "frame_max_size")) { - val_ptr[0] = (char*)ext_value_p->option_value; - } else { - rv = -1; - break; - } - - parameter_length++; - switch_ext_p = switch_ext_p->next; - } - - return rv; -} -#endif -static int -parse_misc_ptunkucfilter(struct switch_val *val) -{ - struct switch_ext *switch_ext_p, *ext_value_p; - int rv = 0; - switch_ext_p = val->value.ext_val; - while(switch_ext_p) { - ext_value_p = switch_ext_p; - - if(!strcmp(ext_value_p->option_name, "name")) { - switch_ext_p = switch_ext_p->next; - continue; - } else if(!strcmp(ext_value_p->option_name, "port")) { - val_ptr[0] = (char*)ext_value_p->option_value; - } else if(!strcmp(ext_value_p->option_name, "status")) { - val_ptr[1] = (char*)ext_value_p->option_value; - } else { - rv = -1; - break; - } - - parameter_length++; - switch_ext_p = switch_ext_p->next; - } - - return rv; -} - -static int -parse_misc_ptunkmcfilter(struct switch_val *val) -{ - struct switch_ext *switch_ext_p, *ext_value_p; - int rv = 0; - switch_ext_p = val->value.ext_val; - while(switch_ext_p) { - ext_value_p = switch_ext_p; - - if(!strcmp(ext_value_p->option_name, "name")) { - switch_ext_p = switch_ext_p->next; - continue; - } else if(!strcmp(ext_value_p->option_name, "port")) { - val_ptr[0] = (char*)ext_value_p->option_value; - } else if(!strcmp(ext_value_p->option_name, "status")) { - val_ptr[1] = (char*)ext_value_p->option_value; - } else { - rv = -1; - break; - } - - parameter_length++; - switch_ext_p = switch_ext_p->next; - } - - return rv; -} - -static int -parse_misc_ptbcfilter(struct switch_val *val) -{ - struct switch_ext *switch_ext_p, *ext_value_p; - int rv = 0; - switch_ext_p = val->value.ext_val; - while(switch_ext_p) { - ext_value_p = switch_ext_p; - - if(!strcmp(ext_value_p->option_name, "name")) { - switch_ext_p = switch_ext_p->next; - continue; - } else if(!strcmp(ext_value_p->option_name, "port")) { - val_ptr[0] = (char*)ext_value_p->option_value; - } else if(!strcmp(ext_value_p->option_name, "status")) { - val_ptr[1] = (char*)ext_value_p->option_value; - } else { - rv = -1; - break; - } - - parameter_length++; - switch_ext_p = switch_ext_p->next; - } - - return rv; -} -#ifndef IN_MISC_MINI -static int -parse_misc_autoneg(struct switch_val *val) -{ - struct switch_ext *switch_ext_p, *ext_value_p; - int rv = 0; - switch_ext_p = val->value.ext_val; - while(switch_ext_p) { - ext_value_p = switch_ext_p; - - if(!strcmp(ext_value_p->option_name, "name")) { - switch_ext_p = switch_ext_p->next; - continue; - } else if(!strcmp(ext_value_p->option_name, "port")) { - val_ptr[0] = (char*)ext_value_p->option_value; - } else { - rv = -1; - break; - } - - parameter_length++; - switch_ext_p = switch_ext_p->next; - } - - return rv; -} -#endif -static int -parse_misc_cpuport(struct switch_val *val) -{ - struct switch_ext *switch_ext_p, *ext_value_p; - int rv = 0; - switch_ext_p = val->value.ext_val; - while(switch_ext_p) { - ext_value_p = switch_ext_p; - - if(!strcmp(ext_value_p->option_name, "name")) { - switch_ext_p = switch_ext_p->next; - continue; - } else if(!strcmp(ext_value_p->option_name, "status")) { - val_ptr[0] = (char*)ext_value_p->option_value; - } else { - rv = -1; - break; - } - - parameter_length++; - switch_ext_p = switch_ext_p->next; - } - - return rv; -} -#ifndef IN_MISC_MINI -static int -parse_misc_pppoecmd(struct switch_val *val) -{ - struct switch_ext *switch_ext_p, *ext_value_p; - int rv = 0; - switch_ext_p = val->value.ext_val; - while(switch_ext_p) { - ext_value_p = switch_ext_p; - - if(!strcmp(ext_value_p->option_name, "name")) { - switch_ext_p = switch_ext_p->next; - continue; - } else if(!strcmp(ext_value_p->option_name, "action")) { - val_ptr[0] = (char*)ext_value_p->option_value; - } else { - rv = -1; - break; - } - - parameter_length++; - switch_ext_p = switch_ext_p->next; - } - - return rv; -} - -static int -parse_misc_pppoe(struct switch_val *val) -{ - struct switch_ext *switch_ext_p, *ext_value_p; - int rv = 0; - switch_ext_p = val->value.ext_val; - while(switch_ext_p) { - ext_value_p = switch_ext_p; - - if(!strcmp(ext_value_p->option_name, "name")) { - switch_ext_p = switch_ext_p->next; - continue; - } else if(!strcmp(ext_value_p->option_name, "status")) { - val_ptr[0] = (char*)ext_value_p->option_value; - } else { - rv = -1; - break; - } - - parameter_length++; - switch_ext_p = switch_ext_p->next; - } - - return rv; -} - -static int -parse_misc_ptdhcp(struct switch_val *val) -{ - struct switch_ext *switch_ext_p, *ext_value_p; - int rv = 0; - switch_ext_p = val->value.ext_val; - while(switch_ext_p) { - ext_value_p = switch_ext_p; - - if(!strcmp(ext_value_p->option_name, "name")) { - switch_ext_p = switch_ext_p->next; - continue; - } else if(!strcmp(ext_value_p->option_name, "port")) { - val_ptr[0] = (char*)ext_value_p->option_value; - } else if(!strcmp(ext_value_p->option_name, "status")) { - val_ptr[1] = (char*)ext_value_p->option_value; - } else { - rv = -1; - break; - } - - parameter_length++; - switch_ext_p = switch_ext_p->next; - } - - return rv; -} - -static int -parse_misc_arpcmd(struct switch_val *val) -{ - struct switch_ext *switch_ext_p, *ext_value_p; - int rv = 0; - switch_ext_p = val->value.ext_val; - while(switch_ext_p) { - ext_value_p = switch_ext_p; - - if(!strcmp(ext_value_p->option_name, "name")) { - switch_ext_p = switch_ext_p->next; - continue; - } else if(!strcmp(ext_value_p->option_name, "action")) { - val_ptr[0] = (char*)ext_value_p->option_value; - } else { - rv = -1; - break; - } - - parameter_length++; - switch_ext_p = switch_ext_p->next; - } - - return rv; -} -#endif -static int -parse_misc_eapolcmd(struct switch_val *val) -{ - struct switch_ext *switch_ext_p, *ext_value_p; - int rv = 0; - switch_ext_p = val->value.ext_val; - while(switch_ext_p) { - ext_value_p = switch_ext_p; - - if(!strcmp(ext_value_p->option_name, "name")) { - switch_ext_p = switch_ext_p->next; - continue; - } else if(!strcmp(ext_value_p->option_name, "action")) { - val_ptr[0] = (char*)ext_value_p->option_value; - } else { - rv = -1; - break; - } - - parameter_length++; - switch_ext_p = switch_ext_p->next; - } - - return rv; -} - -static int -parse_misc_eapolstatus(struct switch_val *val) -{ - struct switch_ext *switch_ext_p, *ext_value_p; - int rv = 0; - switch_ext_p = val->value.ext_val; - while(switch_ext_p) { - ext_value_p = switch_ext_p; - - if(!strcmp(ext_value_p->option_name, "name")) { - switch_ext_p = switch_ext_p->next; - continue; - } else if(!strcmp(ext_value_p->option_name, "port")) { - val_ptr[0] = (char*)ext_value_p->option_value; - } else if(!strcmp(ext_value_p->option_name, "status")) { - val_ptr[1] = (char*)ext_value_p->option_value; - } else { - rv = -1; - break; - } - - parameter_length++; - switch_ext_p = switch_ext_p->next; - } - - return rv; -} -#ifndef IN_MISC_MINI -static int -parse_misc_rip(struct switch_val *val) -{ - struct switch_ext *switch_ext_p, *ext_value_p; - int rv = 0; - switch_ext_p = val->value.ext_val; - while(switch_ext_p) { - ext_value_p = switch_ext_p; - - if(!strcmp(ext_value_p->option_name, "name")) { - switch_ext_p = switch_ext_p->next; - continue; - } else if(!strcmp(ext_value_p->option_name, "status")) { - val_ptr[0] = (char*)ext_value_p->option_value; - } else { - rv = -1; - break; - } - - parameter_length++; - switch_ext_p = switch_ext_p->next; - } - - return rv; -} - -static int -parse_misc_ptarpreq(struct switch_val *val) -{ - struct switch_ext *switch_ext_p, *ext_value_p; - int rv = 0; - switch_ext_p = val->value.ext_val; - while(switch_ext_p) { - ext_value_p = switch_ext_p; - - if(!strcmp(ext_value_p->option_name, "name")) { - switch_ext_p = switch_ext_p->next; - continue; - } else if(!strcmp(ext_value_p->option_name, "port")) { - val_ptr[0] = (char*)ext_value_p->option_value; - } else if(!strcmp(ext_value_p->option_name, "status")) { - val_ptr[1] = (char*)ext_value_p->option_value; - } else { - rv = -1; - break; - } - - parameter_length++; - switch_ext_p = switch_ext_p->next; - } - - return rv; -} - -static int -parse_misc_ptarpack(struct switch_val *val) -{ - struct switch_ext *switch_ext_p, *ext_value_p; - int rv = 0; - switch_ext_p = val->value.ext_val; - while(switch_ext_p) { - ext_value_p = switch_ext_p; - - if(!strcmp(ext_value_p->option_name, "name")) { - switch_ext_p = switch_ext_p->next; - continue; - } else if(!strcmp(ext_value_p->option_name, "port")) { - val_ptr[0] = (char*)ext_value_p->option_value; - } else if(!strcmp(ext_value_p->option_name, "status")) { - val_ptr[1] = (char*)ext_value_p->option_value; - } else { - rv = -1; - break; - } - - parameter_length++; - switch_ext_p = switch_ext_p->next; - } - - return rv; -} - -static int -parse_misc_extendpppoe(struct switch_val *val) -{ - struct switch_ext *switch_ext_p, *ext_value_p; - int rv = 0; - switch_ext_p = val->value.ext_val; - while(switch_ext_p) { - ext_value_p = switch_ext_p; - - if(!strcmp(ext_value_p->option_name, "name")) { - switch_ext_p = switch_ext_p->next; - continue; - } else if(!strcmp(ext_value_p->option_name, "entry_id")) { - val_ptr[0] = (char*)ext_value_p->option_value; - } else if(!strcmp(ext_value_p->option_name, "session_id")) { - val_ptr[1] = (char*)ext_value_p->option_value; - } else if(!strcmp(ext_value_p->option_name, "multicast_session")) { - val_ptr[2] = (char*)ext_value_p->option_value; - } else if(!strcmp(ext_value_p->option_name, "unicast_session")) { - val_ptr[3] = (char*)ext_value_p->option_value; - } else if(!strcmp(ext_value_p->option_name, "vrf_id")) { - val_ptr[4] = (char*)ext_value_p->option_value; - } else if(!strcmp(ext_value_p->option_name, "port")) { - val_ptr[5] = (char*)ext_value_p->option_value; - } else if(!strcmp(ext_value_p->option_name, "l3if_index")) { - val_ptr[6] = (char*)ext_value_p->option_value; - } else if(!strcmp(ext_value_p->option_name, "l3if_index_valid")) { - val_ptr[7] = (char*)ext_value_p->option_value; - } else if(!strcmp(ext_value_p->option_name, "smacaddr")) { - val_ptr[8] = (char*)ext_value_p->option_value; - } else if(!strcmp(ext_value_p->option_name, "smacaddr_valid")) { - val_ptr[9] = (char*)ext_value_p->option_value; - } else { - rv = -1; - break; - } - - parameter_length++; - switch_ext_p = switch_ext_p->next; - } - - return rv; -} - -static int -parse_misc_pppoeid(struct switch_val *val) -{ - struct switch_ext *switch_ext_p, *ext_value_p; - int rv = 0; - switch_ext_p = val->value.ext_val; - while(switch_ext_p) { - ext_value_p = switch_ext_p; - - if(!strcmp(ext_value_p->option_name, "name")) { - switch_ext_p = switch_ext_p->next; - continue; - } else if(!strcmp(ext_value_p->option_name, "index")) { - val_ptr[0] = (char*)ext_value_p->option_value; - } else if(!strcmp(ext_value_p->option_name, "pppoe_id")) { - val_ptr[1] = (char*)ext_value_p->option_value; - } else { - rv = -1; - break; - } - - parameter_length++; - switch_ext_p = switch_ext_p->next; - } - - return rv; -} - -static int -parse_misc_cpuvid(struct switch_val *val) -{ - struct switch_ext *switch_ext_p, *ext_value_p; - int rv = 0; - switch_ext_p = val->value.ext_val; - while(switch_ext_p) { - ext_value_p = switch_ext_p; - - if(!strcmp(ext_value_p->option_name, "name")) { - switch_ext_p = switch_ext_p->next; - continue; - } else if(!strcmp(ext_value_p->option_name, "status")) { - val_ptr[0] = (char*)ext_value_p->option_value; - } else { - rv = -1; - break; - } - - parameter_length++; - switch_ext_p = switch_ext_p->next; - } - - return rv; -} - -static int -parse_misc_rtdpppoe(struct switch_val *val) -{ - struct switch_ext *switch_ext_p, *ext_value_p; - int rv = 0; - switch_ext_p = val->value.ext_val; - while(switch_ext_p) { - ext_value_p = switch_ext_p; - - if(!strcmp(ext_value_p->option_name, "name")) { - switch_ext_p = switch_ext_p->next; - continue; - } else if(!strcmp(ext_value_p->option_name, "status")) { - val_ptr[0] = (char*)ext_value_p->option_value; - } else { - rv = -1; - break; - } - - parameter_length++; - switch_ext_p = switch_ext_p->next; - } - - return rv; -} - -static int -parse_misc_glomacaddr(struct switch_val *val) -{ - struct switch_ext *switch_ext_p, *ext_value_p; - int rv = 0; - switch_ext_p = val->value.ext_val; - while(switch_ext_p) { - ext_value_p = switch_ext_p; - - if(!strcmp(ext_value_p->option_name, "name")) { - switch_ext_p = switch_ext_p->next; - continue; - } else if(!strcmp(ext_value_p->option_name, "macaddr")) { - val_ptr[0] = (char*)ext_value_p->option_value; - } else { - rv = -1; - break; - } - - parameter_length++; - switch_ext_p = switch_ext_p->next; - } - - return rv; -} - -static int -parse_misc_framecrc(struct switch_val *val) -{ - struct switch_ext *switch_ext_p, *ext_value_p; - int rv = 0; - switch_ext_p = val->value.ext_val; - while(switch_ext_p) { - ext_value_p = switch_ext_p; - - if(!strcmp(ext_value_p->option_name, "name")) { - switch_ext_p = switch_ext_p->next; - continue; - } else if(!strcmp(ext_value_p->option_name, "status")) { - val_ptr[0] = (char*)ext_value_p->option_value; - } else { - rv = -1; - break; - } - - parameter_length++; - switch_ext_p = switch_ext_p->next; - } - - return rv; -} - -static int -parse_misc_pppoeen(struct switch_val *val) -{ - struct switch_ext *switch_ext_p, *ext_value_p; - int rv = 0; - - switch_ext_p = val->value.ext_val; - while (switch_ext_p) { - ext_value_p = switch_ext_p; - - if (!strcmp(ext_value_p->option_name, "name")) { - switch_ext_p = switch_ext_p->next; - continue; - } else if (!strcmp(ext_value_p->option_name, "l3if_index")) { - val_ptr[0] = (char*)ext_value_p->option_value; - } else if (!strcmp(ext_value_p->option_name, "pppoe_en")) { - val_ptr[1] = (char*)ext_value_p->option_value; - } else { - rv = -1; - break; - } - - parameter_length++; - switch_ext_p = switch_ext_p->next; - } - - return rv; -} -#endif -#endif - -#ifdef IN_IP -#ifndef IN_IP_MINI -static int -parse_ip_hostentry(struct switch_val *val) -{ - struct switch_ext *switch_ext_p, *ext_value_p; - int rv = 0; - char* vrf_temp = "0"; - val_ptr[6] = vrf_temp; - parameter_length ++; - val_ptr[7] = vrf_temp; - parameter_length ++; - val_ptr[12] = param_dflt_str; - parameter_length ++; - val_ptr[13] = vrf_temp; - parameter_length ++; - val_ptr[14] = vrf_temp; - parameter_length ++; - val_ptr[15] = vrf_temp; - parameter_length ++; - val_ptr[16] = param_dflt_str; - parameter_length ++; - val_ptr[17] = param_dflt_str; - parameter_length ++; - switch_ext_p = val->value.ext_val; - while(switch_ext_p) { - ext_value_p = switch_ext_p; - - if(!strcmp(ext_value_p->option_name, "name")) { - switch_ext_p = switch_ext_p->next; - continue; - } else if(!strcmp(ext_value_p->option_name, "entry_id")) { - val_ptr[0] = (char*)ext_value_p->option_value; - } else if(!strcmp(ext_value_p->option_name, "entry_flags")) { - val_ptr[1] = (char*)ext_value_p->option_value; - } else if(!strcmp(ext_value_p->option_name, "entry_status")) { - val_ptr[2] = (char*)ext_value_p->option_value; - } else if(!strcmp(ext_value_p->option_name, "ip_addr")) { - val_ptr[3] = (char*)ext_value_p->option_value; - } else if(!strcmp(ext_value_p->option_name, "mac_addr")) { - val_ptr[4] = (char*)ext_value_p->option_value; - } else if(!strcmp(ext_value_p->option_name, "interface_id")) { - val_ptr[5] = (char*)ext_value_p->option_value; - } else if(!strcmp(ext_value_p->option_name, "load_balance_num")) { - val_ptr[6] = (char*)ext_value_p->option_value; - parameter_length --; - } else if(!strcmp(ext_value_p->option_name, "vrf_id")) { - val_ptr[7] = (char*)ext_value_p->option_value; - parameter_length --; - } else if(!strcmp(ext_value_p->option_name, "port_id")) { - val_ptr[8] = (char*)ext_value_p->option_value; - } else if(!strcmp(ext_value_p->option_name, "action")) { - val_ptr[9] = (char*)ext_value_p->option_value; - } else if(!strcmp(ext_value_p->option_name, "mirror")) { - val_ptr[10] = (char*)ext_value_p->option_value; - } else if(!strcmp(ext_value_p->option_name, "counter")) { - val_ptr[11] = (char*)ext_value_p->option_value; - } else if(!strcmp(ext_value_p->option_name, "counter_id")) { - val_ptr[12] = (char*)ext_value_p->option_value; - parameter_length --; - } else if (!strcmp(ext_value_p->option_name, "dstinfo")) { - val_ptr[13] = (char*)ext_value_p->option_value; - parameter_length --; - } else if (!strcmp(ext_value_p->option_name, "synctoggle")) { - val_ptr[14] = (char*)ext_value_p->option_value; - parameter_length --; - } else if (!strcmp(ext_value_p->option_name, "lan_wan")) { - val_ptr[15] = (char*)ext_value_p->option_value; - parameter_length --; - } else if (!strcmp(ext_value_p->option_name, "vsi")) { - val_ptr[16] = (char*)ext_value_p->option_value; - parameter_length --; - } else if (!strcmp(ext_value_p->option_name, "sip_addr")) { - val_ptr[17] = (char*)ext_value_p->option_value; - parameter_length --; - } else { - rv = -1; - break; - } - - parameter_length++; - switch_ext_p = switch_ext_p->next; - } - - return rv; -} - -static int -parse_ip_intfentry(struct switch_val *val) -{ - struct switch_ext *switch_ext_p, *ext_value_p; - int rv = 0; - char* vrf_temp = "0"; - val_ptr[1] = vrf_temp; - parameter_length ++; - switch_ext_p = val->value.ext_val; - while(switch_ext_p) { - ext_value_p = switch_ext_p; - - if(!strcmp(ext_value_p->option_name, "name")) { - switch_ext_p = switch_ext_p->next; - continue; - } else if(!strcmp(ext_value_p->option_name, "entry_id")) { - val_ptr[0] = (char*)ext_value_p->option_value; - } else if(!strcmp(ext_value_p->option_name, "vrf_id")) { - val_ptr[1] = (char*)ext_value_p->option_value; - parameter_length --; - } else if(!strcmp(ext_value_p->option_name, "vlan_low")) { - val_ptr[2] = (char*)ext_value_p->option_value; - } else if(!strcmp(ext_value_p->option_name, "vlan_high")) { - val_ptr[3] = (char*)ext_value_p->option_value; - } else if(!strcmp(ext_value_p->option_name, "mac_addr")) { - val_ptr[4] = (char*)ext_value_p->option_value; - } else if(!strcmp(ext_value_p->option_name, "ipv4_route")) { - val_ptr[5] = (char*)ext_value_p->option_value; - } else if(!strcmp(ext_value_p->option_name, "ipv6_route")) { - val_ptr[6] = (char*)ext_value_p->option_value; - } else { - rv = -1; - break; - } - - parameter_length++; - switch_ext_p = switch_ext_p->next; - } - - return rv; -} - -static int -parse_ip_ptarplearn(struct switch_val *val) -{ - struct switch_ext *switch_ext_p, *ext_value_p; - int rv = 0; - switch_ext_p = val->value.ext_val; - while(switch_ext_p) { - ext_value_p = switch_ext_p; - - if(!strcmp(ext_value_p->option_name, "name")) { - switch_ext_p = switch_ext_p->next; - continue; - } else if(!strcmp(ext_value_p->option_name, "port")) { - val_ptr[0] = (char*)ext_value_p->option_value; - } else if(!strcmp(ext_value_p->option_name, "status")) { - val_ptr[1] = (char*)ext_value_p->option_value; - } else { - rv = -1; - break; - } - - parameter_length++; - switch_ext_p = switch_ext_p->next; - } - - return rv; -} - -static int -parse_ip_arplearn(struct switch_val *val) -{ - struct switch_ext *switch_ext_p, *ext_value_p; - int rv = 0; - switch_ext_p = val->value.ext_val; - while(switch_ext_p) { - ext_value_p = switch_ext_p; - - if(!strcmp(ext_value_p->option_name, "name")) { - switch_ext_p = switch_ext_p->next; - continue; - } else if(!strcmp(ext_value_p->option_name, "mode")) { - val_ptr[0] = (char*)ext_value_p->option_value; - } else { - rv = -1; - break; - } - - parameter_length++; - switch_ext_p = switch_ext_p->next; - } - - return rv; -} - -static int -parse_ip_ptipsrcguard(struct switch_val *val) -{ - struct switch_ext *switch_ext_p, *ext_value_p; - int rv = 0; - switch_ext_p = val->value.ext_val; - while(switch_ext_p) { - ext_value_p = switch_ext_p; - - if(!strcmp(ext_value_p->option_name, "name")) { - switch_ext_p = switch_ext_p->next; - continue; - } else if(!strcmp(ext_value_p->option_name, "port")) { - val_ptr[0] = (char*)ext_value_p->option_value; - } else if(!strcmp(ext_value_p->option_name, "source_guard_mode")) { - val_ptr[1] = (char*)ext_value_p->option_value; - } else { - rv = -1; - break; - } - - parameter_length++; - switch_ext_p = switch_ext_p->next; - } - - return rv; -} - -static int -parse_ip_ptarpsrcguard(struct switch_val *val) -{ - struct switch_ext *switch_ext_p, *ext_value_p; - int rv = 0; - switch_ext_p = val->value.ext_val; - while(switch_ext_p) { - ext_value_p = switch_ext_p; - - if(!strcmp(ext_value_p->option_name, "name")) { - switch_ext_p = switch_ext_p->next; - continue; - } else if(!strcmp(ext_value_p->option_name, "port")) { - val_ptr[0] = (char*)ext_value_p->option_value; - } else if(!strcmp(ext_value_p->option_name, "source_guard_mode")) { - val_ptr[1] = (char*)ext_value_p->option_value; - } else { - rv = -1; - break; - } - - parameter_length++; - switch_ext_p = switch_ext_p->next; - } - - return rv; -} - -static int -parse_ip_routestatus(struct switch_val *val) -{ - struct switch_ext *switch_ext_p, *ext_value_p; - int rv = 0; - switch_ext_p = val->value.ext_val; - while(switch_ext_p) { - ext_value_p = switch_ext_p; - - if(!strcmp(ext_value_p->option_name, "name")) { - switch_ext_p = switch_ext_p->next; - continue; - } else if(!strcmp(ext_value_p->option_name, "status")) { - val_ptr[0] = (char*)ext_value_p->option_value; - } else { - rv = -1; - break; - } - - parameter_length++; - switch_ext_p = switch_ext_p->next; - } - - return rv; -} - -static int -parse_ip_ipunksrc(struct switch_val *val) -{ - struct switch_ext *switch_ext_p, *ext_value_p; - int rv = 0; - switch_ext_p = val->value.ext_val; - while(switch_ext_p) { - ext_value_p = switch_ext_p; - - if(!strcmp(ext_value_p->option_name, "name")) { - switch_ext_p = switch_ext_p->next; - continue; - } else if(!strcmp(ext_value_p->option_name, "action")) { - val_ptr[0] = (char*)ext_value_p->option_value; - } else { - rv = -1; - break; - } - - parameter_length++; - switch_ext_p = switch_ext_p->next; - } - - return rv; -} - -static int -parse_ip_arpunksrc(struct switch_val *val) -{ - struct switch_ext *switch_ext_p, *ext_value_p; - int rv = 0; - switch_ext_p = val->value.ext_val; - while(switch_ext_p) { - ext_value_p = switch_ext_p; - - if(!strcmp(ext_value_p->option_name, "name")) { - switch_ext_p = switch_ext_p->next; - continue; - } else if(!strcmp(ext_value_p->option_name, "action")) { - val_ptr[0] = (char*)ext_value_p->option_value; - } else { - rv = -1; - break; - } - - parameter_length++; - switch_ext_p = switch_ext_p->next; - } - - return rv; -} - -static int -parse_ip_agetime(struct switch_val *val) -{ - struct switch_ext *switch_ext_p, *ext_value_p; - int rv = 0; - switch_ext_p = val->value.ext_val; - while(switch_ext_p) { - ext_value_p = switch_ext_p; - - if(!strcmp(ext_value_p->option_name, "name")) { - switch_ext_p = switch_ext_p->next; - continue; - } else if(!strcmp(ext_value_p->option_name, "age_time")) { - val_ptr[0] = (char*)ext_value_p->option_value; - } else { - rv = -1; - break; - } - - parameter_length++; - switch_ext_p = switch_ext_p->next; - } - - return rv; -} - -static int -parse_ip_wcmphashmode(struct switch_val *val) -{ - struct switch_ext *switch_ext_p, *ext_value_p; - int rv = 0; - switch_ext_p = val->value.ext_val; - while(switch_ext_p) { - ext_value_p = switch_ext_p; - - if(!strcmp(ext_value_p->option_name, "name")) { - switch_ext_p = switch_ext_p->next; - continue; - } else if(!strcmp(ext_value_p->option_name, "wcmp_hash_mode")) { - val_ptr[0] = (char*)ext_value_p->option_value; - } else { - rv = -1; - break; - } - - parameter_length++; - switch_ext_p = switch_ext_p->next; - } - - return rv; -} - -static int -parse_ip_defaultflowcmd(struct switch_val *val) -{ - struct switch_ext *switch_ext_p, *ext_value_p; - int rv = 0; - switch_ext_p = val->value.ext_val; - while(switch_ext_p) { - ext_value_p = switch_ext_p; - - if(!strcmp(ext_value_p->option_name, "name")) { - switch_ext_p = switch_ext_p->next; - continue; - } else if(!strcmp(ext_value_p->option_name, "vrf_id")) { - val_ptr[0] = (char*)ext_value_p->option_value; - } else if(!strcmp(ext_value_p->option_name, "flow_type")) { - val_ptr[1] = (char*)ext_value_p->option_value; - } else if(!strcmp(ext_value_p->option_name, "flow_cmd")) { - val_ptr[2] = (char*)ext_value_p->option_value; - } else { - rv = -1; - break; - } - - parameter_length++; - switch_ext_p = switch_ext_p->next; - } - - return rv; -} - -static int -parse_ip_defaultrtflowcmd(struct switch_val *val) -{ - struct switch_ext *switch_ext_p, *ext_value_p; - int rv = 0; - switch_ext_p = val->value.ext_val; - while(switch_ext_p) { - ext_value_p = switch_ext_p; - - if(!strcmp(ext_value_p->option_name, "name")) { - switch_ext_p = switch_ext_p->next; - continue; - } else if(!strcmp(ext_value_p->option_name, "vrf_id")) { - val_ptr[0] = (char*)ext_value_p->option_value; - } else if(!strcmp(ext_value_p->option_name, "flow_type")) { - val_ptr[1] = (char*)ext_value_p->option_value; - } else if(!strcmp(ext_value_p->option_name, "flow_cmd")) { - val_ptr[2] = (char*)ext_value_p->option_value; - } else { - rv = -1; - break; - } - - parameter_length++; - switch_ext_p = switch_ext_p->next; - } - - return rv; -} - -static int -parse_ip_hostroute(struct switch_val *val) -{ - struct switch_ext *switch_ext_p, *ext_value_p; - int rv = 0; - switch_ext_p = val->value.ext_val; - while(switch_ext_p) { - ext_value_p = switch_ext_p; - - if(!strcmp(ext_value_p->option_name, "name")) { - switch_ext_p = switch_ext_p->next; - continue; - } else if(!strcmp(ext_value_p->option_name, "entry_id")) { - val_ptr[0] = (char*)ext_value_p->option_value; - } else if(!strcmp(ext_value_p->option_name, "entry_valid")) { - val_ptr[1] = (char*)ext_value_p->option_value; - } else if(!strcmp(ext_value_p->option_name, "vrf_id")) { - val_ptr[2] = (char*)ext_value_p->option_value; - } else if(!strcmp(ext_value_p->option_name, "ip_version")) { - val_ptr[3] = (char*)ext_value_p->option_value; - } else if(!strcmp(ext_value_p->option_name, "ip_addr")) { - val_ptr[4] = (char*)ext_value_p->option_value; - } else if(!strcmp(ext_value_p->option_name, "prefix_length")) { - val_ptr[5] = (char*)ext_value_p->option_value; - } else { - rv = -1; - break; - } - - parameter_length++; - switch_ext_p = switch_ext_p->next; - } - - return rv; -} - -static int -parse_ip_defaultroute(struct switch_val *val) -{ - struct switch_ext *switch_ext_p, *ext_value_p; - int rv = 0; - switch_ext_p = val->value.ext_val; - while(switch_ext_p) { - ext_value_p = switch_ext_p; - - if(!strcmp(ext_value_p->option_name, "name")) { - switch_ext_p = switch_ext_p->next; - continue; - } else if(!strcmp(ext_value_p->option_name, "entry_id")) { - val_ptr[0] = (char*)ext_value_p->option_value; - } else if(!strcmp(ext_value_p->option_name, "entry_valid")) { - val_ptr[1] = (char*)ext_value_p->option_value; - } else if(!strcmp(ext_value_p->option_name, "vrf_id")) { - val_ptr[2] = (char*)ext_value_p->option_value; - } else if(!strcmp(ext_value_p->option_name, "route_type")) { - val_ptr[3] = (char*)ext_value_p->option_value; - } else if(!strcmp(ext_value_p->option_name, "index")) { - val_ptr[4] = (char*)ext_value_p->option_value; - } else { - rv = -1; - break; - } - - parameter_length++; - switch_ext_p = switch_ext_p->next; - } - - return rv; -} - -static int -parse_ip_vrfbaseaddr(struct switch_val *val) -{ - struct switch_ext *switch_ext_p, *ext_value_p; - int rv = 0; - switch_ext_p = val->value.ext_val; - while(switch_ext_p) { - ext_value_p = switch_ext_p; - - if(!strcmp(ext_value_p->option_name, "name")) { - switch_ext_p = switch_ext_p->next; - continue; - } else if(!strcmp(ext_value_p->option_name, "vrf_id")) { - val_ptr[0] = (char*)ext_value_p->option_value; - } else if(!strcmp(ext_value_p->option_name, "base_addr")) { - val_ptr[1] = (char*)ext_value_p->option_value; - } else { - rv = -1; - break; - } - - parameter_length++; - switch_ext_p = switch_ext_p->next; - } - - return rv; -} - -static int -parse_ip_vrfbasemask(struct switch_val *val) -{ - struct switch_ext *switch_ext_p, *ext_value_p; - int rv = 0; - switch_ext_p = val->value.ext_val; - while(switch_ext_p) { - ext_value_p = switch_ext_p; - - if(!strcmp(ext_value_p->option_name, "name")) { - switch_ext_p = switch_ext_p->next; - continue; - } else if(!strcmp(ext_value_p->option_name, "vrf_id")) { - val_ptr[0] = (char*)ext_value_p->option_value; - } else if(!strcmp(ext_value_p->option_name, "base_mask")) { - val_ptr[1] = (char*)ext_value_p->option_value; - } else { - rv = -1; - break; - } - - parameter_length++; - switch_ext_p = switch_ext_p->next; - } - - return rv; -} - -static int -parse_ip_rfsip4(struct switch_val *val) -{ - struct switch_ext *switch_ext_p, *ext_value_p; - int rv = 0; - switch_ext_p = val->value.ext_val; - while(switch_ext_p) { - ext_value_p = switch_ext_p; - - if(!strcmp(ext_value_p->option_name, "name")) { - switch_ext_p = switch_ext_p->next; - continue; - } else if(!strcmp(ext_value_p->option_name, "mac_addr")) { - val_ptr[0] = (char*)ext_value_p->option_value; - } else if(!strcmp(ext_value_p->option_name, "ip4_addr")) { - val_ptr[1] = (char*)ext_value_p->option_value; - } else if(!strcmp(ext_value_p->option_name, "vlan_id")) { - val_ptr[2] = (char*)ext_value_p->option_value; - } else if(!strcmp(ext_value_p->option_name, "load_balance")) { - val_ptr[3] = (char*)ext_value_p->option_value; - } else { - rv = -1; - break; - } - - parameter_length++; - switch_ext_p = switch_ext_p->next; - } - - return rv; -} - -static int -parse_ip_rfsip6(struct switch_val *val) -{ - struct switch_ext *switch_ext_p, *ext_value_p; - int rv = 0; - switch_ext_p = val->value.ext_val; - while(switch_ext_p) { - ext_value_p = switch_ext_p; - - if(!strcmp(ext_value_p->option_name, "name")) { - switch_ext_p = switch_ext_p->next; - continue; - } else if(!strcmp(ext_value_p->option_name, "mac_addr")) { - val_ptr[0] = (char*)ext_value_p->option_value; - } else if(!strcmp(ext_value_p->option_name, "ip6_addr")) { - val_ptr[1] = (char*)ext_value_p->option_value; - } else if(!strcmp(ext_value_p->option_name, "vlan_id")) { - val_ptr[2] = (char*)ext_value_p->option_value; - } else if(!strcmp(ext_value_p->option_name, "load_balance")) { - val_ptr[3] = (char*)ext_value_p->option_value; - } else { - rv = -1; - break; - } - - parameter_length++; - switch_ext_p = switch_ext_p->next; - } - - return rv; -} - -static int -parse_ip_vsiarpsg(struct switch_val *val) -{ - struct switch_ext *switch_ext_p, *ext_value_p; - int rv = 0; - - switch_ext_p = val->value.ext_val; - while (switch_ext_p) { - ext_value_p = switch_ext_p; - - if (!strcmp(ext_value_p->option_name, "name")) { - switch_ext_p = switch_ext_p->next; - continue; - } else if (!strcmp(ext_value_p->option_name, "vsi")) { - val_ptr[0] = (char*)ext_value_p->option_value; - } else if (!strcmp(ext_value_p->option_name, "ip4_arp_sourceguard_en")) { - val_ptr[1] = (char*)ext_value_p->option_value; - } else if (!strcmp(ext_value_p->option_name, "ip4_arp_sourceguard_violation_action")) { - val_ptr[2] = (char*)ext_value_p->option_value; - } else if (!strcmp(ext_value_p->option_name, "ip4_arp_sourceguard_port_en")) { - val_ptr[3] = (char*)ext_value_p->option_value; - } else if (!strcmp(ext_value_p->option_name, "ip4_arp_sourceguard_svlan_en")) { - val_ptr[4] = (char*)ext_value_p->option_value; - } else if (!strcmp(ext_value_p->option_name, "ip4_arp_sourcegurad_cvlan_en")) { - val_ptr[5] = (char*)ext_value_p->option_value; - } else if (!strcmp(ext_value_p->option_name, "ip4_arp_sourceunkown_action")) { - val_ptr[6] = (char*)ext_value_p->option_value; - } else if (!strcmp(ext_value_p->option_name, "ip6_nd_sourceguard_en")) { - val_ptr[7] = (char*)ext_value_p->option_value; - } else if (!strcmp(ext_value_p->option_name, "ip6_nd_sourceguard_violation_action")) { - val_ptr[8] = (char*)ext_value_p->option_value; - } else if (!strcmp(ext_value_p->option_name, "ip6_nd_sourceguard_port_en")) { - val_ptr[9] = (char*)ext_value_p->option_value; - } else if (!strcmp(ext_value_p->option_name, "ip6_nd_sourceguard_svlan_en")) { - val_ptr[10] = (char*)ext_value_p->option_value; - } else if (!strcmp(ext_value_p->option_name, "ip6_nd_sourceguard_cvlan_en")) { - val_ptr[11] = (char*)ext_value_p->option_value; - } else if (!strcmp(ext_value_p->option_name, "ip6_nd_sourceunknown_action")) { - val_ptr[12] = (char*)ext_value_p->option_value; - } else { - rv = -1; - break; - } - - parameter_length++; - switch_ext_p = switch_ext_p->next; - } - - return rv; -} - -static int -parse_ip_vsisg(struct switch_val *val) -{ - struct switch_ext *switch_ext_p, *ext_value_p; - int rv = 0; - - switch_ext_p = val->value.ext_val; - while (switch_ext_p) { - ext_value_p = switch_ext_p; - - if (!strcmp(ext_value_p->option_name, "name")) { - switch_ext_p = switch_ext_p->next; - continue; - } else if (!strcmp(ext_value_p->option_name, "vsi")) { - val_ptr[0] = (char*)ext_value_p->option_value; - } else if (!strcmp(ext_value_p->option_name, "ip4_sourceguard_en")) { - val_ptr[1] = (char*)ext_value_p->option_value; - } else if (!strcmp(ext_value_p->option_name, "ip4_sourcegurad_violation_action")) { - val_ptr[2] = (char*)ext_value_p->option_value; - } else if (!strcmp(ext_value_p->option_name, "ip4_sourceguard_port_en")) { - val_ptr[3] = (char*)ext_value_p->option_value; - } else if (!strcmp(ext_value_p->option_name, "ip4_sourceguard_svlan_en")) { - val_ptr[4] = (char*)ext_value_p->option_value; - } else if (!strcmp(ext_value_p->option_name, "ip4_sourceguard_cvlan_en")) { - val_ptr[5] = (char*)ext_value_p->option_value; - } else if (!strcmp(ext_value_p->option_name, "ip4_sourceunkown_action")) { - val_ptr[6] = (char*)ext_value_p->option_value; - } else if (!strcmp(ext_value_p->option_name, "ip6_sourceguard_en")) { - val_ptr[7] = (char*)ext_value_p->option_value; - } else if (!strcmp(ext_value_p->option_name, "ip6_sourceguard_violation_action")) { - val_ptr[8] = (char*)ext_value_p->option_value; - } else if (!strcmp(ext_value_p->option_name, "ip6_sourceguard_port_en")) { - val_ptr[9] = (char*)ext_value_p->option_value; - } else if (!strcmp(ext_value_p->option_name, "ip6_sourceguard_svlan_en")) { - val_ptr[10] = (char*)ext_value_p->option_value; - } else if (!strcmp(ext_value_p->option_name, "ip6_sourceguard_cvlan_en")) { - val_ptr[11] = (char*)ext_value_p->option_value; - } else if (!strcmp(ext_value_p->option_name, "ip6_sourceunknown_action")) { - val_ptr[12] = (char*)ext_value_p->option_value; - } else { - rv = -1; - break; - } - - parameter_length++; - switch_ext_p = switch_ext_p->next; - } - - return rv; -} - -static int -parse_ip_portarpsg(struct switch_val *val) -{ - struct switch_ext *switch_ext_p, *ext_value_p; - int rv = 0; - - switch_ext_p = val->value.ext_val; - while (switch_ext_p) { - ext_value_p = switch_ext_p; - - if (!strcmp(ext_value_p->option_name, "name")) { - switch_ext_p = switch_ext_p->next; - continue; - } else if (!strcmp(ext_value_p->option_name, "port_id")) { - val_ptr[0] = (char*)ext_value_p->option_value; - } else if (!strcmp(ext_value_p->option_name, "ip4_arp_sourceguard_en")) { - val_ptr[1] = (char*)ext_value_p->option_value; - } else if (!strcmp(ext_value_p->option_name, "ip4_arp_sourceguard_violation_action")) { - val_ptr[2] = (char*)ext_value_p->option_value; - } else if (!strcmp(ext_value_p->option_name, "ip4_arp_sourceguard_port_en")) { - val_ptr[3] = (char*)ext_value_p->option_value; - } else if (!strcmp(ext_value_p->option_name, "ip4_arp_sourceguard_svlan_en")) { - val_ptr[4] = (char*)ext_value_p->option_value; - } else if (!strcmp(ext_value_p->option_name, "ip4_arp_sourceguard_cvlan_en")) { - val_ptr[5] = (char*)ext_value_p->option_value; - } else if (!strcmp(ext_value_p->option_name, "ip4_arp_sourceunkown_action")) { - val_ptr[6] = (char*)ext_value_p->option_value; - } else if (!strcmp(ext_value_p->option_name, "ip6_nd_sourceguard_en")) { - val_ptr[7] = (char*)ext_value_p->option_value; - } else if (!strcmp(ext_value_p->option_name, "ip6_nd_sourceguard_violation_action")) { - val_ptr[8] = (char*)ext_value_p->option_value; - } else if (!strcmp(ext_value_p->option_name, "ip6_nd_sourceguard_port_en")) { - val_ptr[9] = (char*)ext_value_p->option_value; - } else if (!strcmp(ext_value_p->option_name, "ip6_nd_sourceguard_svlan_en")) { - val_ptr[10] = (char*)ext_value_p->option_value; - } else if (!strcmp(ext_value_p->option_name, "ip6_nd_sourceguard_cvlan_en")) { - val_ptr[11] = (char*)ext_value_p->option_value; - } else if (!strcmp(ext_value_p->option_name, "ip6_nd_sourceunkown_action")) { - val_ptr[12] = (char*)ext_value_p->option_value; - } else { - rv = -1; - break; - } - - parameter_length++; - switch_ext_p = switch_ext_p->next; - } - - return rv; -} - -static int -parse_ip_portsg(struct switch_val *val) -{ - struct switch_ext *switch_ext_p, *ext_value_p; - int rv = 0; - - switch_ext_p = val->value.ext_val; - while (switch_ext_p) { - ext_value_p = switch_ext_p; - - if (!strcmp(ext_value_p->option_name, "name")) { - switch_ext_p = switch_ext_p->next; - continue; - } else if (!strcmp(ext_value_p->option_name, "port_id")) { - val_ptr[0] = (char*)ext_value_p->option_value; - } else if (!strcmp(ext_value_p->option_name, "ip4_sourceguard_en")) { - val_ptr[1] = (char*)ext_value_p->option_value; - } else if (!strcmp(ext_value_p->option_name, "ip4_sourceguard_violation_action")) { - val_ptr[2] = (char*)ext_value_p->option_value; - } else if (!strcmp(ext_value_p->option_name, "ip4_sourceguard_port_en")) { - val_ptr[3] = (char*)ext_value_p->option_value; - } else if (!strcmp(ext_value_p->option_name, "ip4_sourceguard_svlan_en")) { - val_ptr[4] = (char*)ext_value_p->option_value; - } else if (!strcmp(ext_value_p->option_name, "ip4_sourceguard_cvlan_en")) { - val_ptr[5] = (char*)ext_value_p->option_value; - } else if (!strcmp(ext_value_p->option_name, "ip4_sourceunkown_action")) { - val_ptr[6] = (char*)ext_value_p->option_value; - } else if (!strcmp(ext_value_p->option_name, "ip6_sourceguard_en")) { - val_ptr[7] = (char*)ext_value_p->option_value; - } else if (!strcmp(ext_value_p->option_name, "ip6_sourceguard_violation_action")) { - val_ptr[8] = (char*)ext_value_p->option_value; - } else if (!strcmp(ext_value_p->option_name, "ip6_sourceguard_port_en")) { - val_ptr[9] = (char*)ext_value_p->option_value; - } else if (!strcmp(ext_value_p->option_name, "ip6_sourceguard_svlan_en")) { - val_ptr[10] = (char*)ext_value_p->option_value; - } else if (!strcmp(ext_value_p->option_name, "ip6_sourceguard_cvlan_en")) { - val_ptr[11] = (char*)ext_value_p->option_value; - } else if (!strcmp(ext_value_p->option_name, "ip6_sourceunkown_action")) { - val_ptr[12] = (char*)ext_value_p->option_value; - } else { - rv = -1; - break; - } - - parameter_length++; - switch_ext_p = switch_ext_p->next; - } - - return rv; -} - -static int -parse_ip_pubip(struct switch_val *val) -{ - struct switch_ext *switch_ext_p, *ext_value_p; - int rv = 0; - - switch_ext_p = val->value.ext_val; - while (switch_ext_p) { - ext_value_p = switch_ext_p; - - if (!strcmp(ext_value_p->option_name, "name")) { - switch_ext_p = switch_ext_p->next; - continue; - } else if (!strcmp(ext_value_p->option_name, "index")) { - val_ptr[0] = (char*)ext_value_p->option_value; - } else if (!strcmp(ext_value_p->option_name, "ip4addr")) { - val_ptr[1] = (char*)ext_value_p->option_value; - } else { - rv = -1; - break; - } - - parameter_length++; - switch_ext_p = switch_ext_p->next; - } - - return rv; -} - -static int -parse_ip_networkroute(struct switch_val *val) -{ - struct switch_ext *switch_ext_p, *ext_value_p; - int rv = 0; - - switch_ext_p = val->value.ext_val; - while (switch_ext_p) { - ext_value_p = switch_ext_p; - - if (!strcmp(ext_value_p->option_name, "name")) { - switch_ext_p = switch_ext_p->next; - continue; - } else if (!strcmp(ext_value_p->option_name, "index")) { - val_ptr[0] = (char*)ext_value_p->option_value; - } else if (!strcmp(ext_value_p->option_name, "type")) { - val_ptr[1] = (char*)ext_value_p->option_value; - } else if (!strcmp(ext_value_p->option_name, "action")) { - val_ptr[4] = (char*)ext_value_p->option_value; - } else if (!strcmp(ext_value_p->option_name, "dstinfo")) { - val_ptr[5] = (char*)ext_value_p->option_value; - } else if (!strcmp(ext_value_p->option_name, "lan_wan")) { - val_ptr[6] = (char*)ext_value_p->option_value; - } else if (!strcmp(ext_value_p->option_name, "ip4addr")) { - val_ptr[2] = (char*)ext_value_p->option_value; - } else if (!strcmp(ext_value_p->option_name, "ip4addr_mask")) { - val_ptr[3] = (char*)ext_value_p->option_value; - } else { - rv = -1; - break; - } - - parameter_length++; - switch_ext_p = switch_ext_p->next; - } - - return rv; -} - -static int -parse_ip_intf(struct switch_val *val) -{ - struct switch_ext *switch_ext_p, *ext_value_p; - int rv = 0; - - switch_ext_p = val->value.ext_val; - while (switch_ext_p) { - ext_value_p = switch_ext_p; - - if (!strcmp(ext_value_p->option_name, "name")) { - switch_ext_p = switch_ext_p->next; - continue; - } else if (!strcmp(ext_value_p->option_name, "index")) { - val_ptr[0] = (char*)ext_value_p->option_value; - } else if (!strcmp(ext_value_p->option_name, "mru")) { - val_ptr[1] = (char*)ext_value_p->option_value; - } else if (!strcmp(ext_value_p->option_name, "mtu")) { - val_ptr[2] = (char*)ext_value_p->option_value; - } else if (!strcmp(ext_value_p->option_name, "ttl_dec_bypass_en")) { - val_ptr[3] = (char*)ext_value_p->option_value; - } else if (!strcmp(ext_value_p->option_name, "ip4_unicast_route_en")) { - val_ptr[4] = (char*)ext_value_p->option_value; - } else if (!strcmp(ext_value_p->option_name, "ip6_unicast_route_en")) { - val_ptr[5] = (char*)ext_value_p->option_value; - } else if (!strcmp(ext_value_p->option_name, "icmp_trigger_en")) { - val_ptr[6] = (char*)ext_value_p->option_value; - } else if (!strcmp(ext_value_p->option_name, "ttl_exceed_action")) { - val_ptr[7] = (char*)ext_value_p->option_value; - } else if (!strcmp(ext_value_p->option_name, "ttl_exceed_deacclr_en")) { - val_ptr[8] = (char*)ext_value_p->option_value; - } else if (!strcmp(ext_value_p->option_name, "macaddr_bitmap")) { - val_ptr[9] = (char*)ext_value_p->option_value; - } else if (!strcmp(ext_value_p->option_name, "macaddr")) { - val_ptr[10] = (char*)ext_value_p->option_value; - } else { - rv = -1; - break; - } - - parameter_length++; - switch_ext_p = switch_ext_p->next; - } - - return rv; -} - -static int -parse_ip_vsiintf(struct switch_val *val) -{ - struct switch_ext *switch_ext_p, *ext_value_p; - int rv = 0; - - switch_ext_p = val->value.ext_val; - while (switch_ext_p) { - ext_value_p = switch_ext_p; - - if (!strcmp(ext_value_p->option_name, "name")) { - switch_ext_p = switch_ext_p->next; - continue; - } else if (!strcmp(ext_value_p->option_name, "vsi")) { - val_ptr[0] = (char*)ext_value_p->option_value; - } else if (!strcmp(ext_value_p->option_name, "l3if_valid")) { - val_ptr[1] = (char*)ext_value_p->option_value; - } else if (!strcmp(ext_value_p->option_name, "l3if_index")) { - val_ptr[2] = (char*)ext_value_p->option_value; - } else { - rv = -1; - break; - } - - parameter_length++; - switch_ext_p = switch_ext_p->next; - } - - return rv; -} - -static int -parse_ip_portintf(struct switch_val *val) -{ - struct switch_ext *switch_ext_p, *ext_value_p; - int rv = 0; - - switch_ext_p = val->value.ext_val; - while (switch_ext_p) { - ext_value_p = switch_ext_p; - - if (!strcmp(ext_value_p->option_name, "name")) { - switch_ext_p = switch_ext_p->next; - continue; - } else if (!strcmp(ext_value_p->option_name, "port_id")) { - val_ptr[0] = (char*)ext_value_p->option_value; - } else if (!strcmp(ext_value_p->option_name, "l3if_valid")) { - val_ptr[1] = (char*)ext_value_p->option_value; - } else if (!strcmp(ext_value_p->option_name, "l3if_index")) { - val_ptr[2] = (char*)ext_value_p->option_value; - } else { - rv = -1; - break; - } - - parameter_length++; - switch_ext_p = switch_ext_p->next; - } - - return rv; -} - -static int -parse_ip_nexthop(struct switch_val *val) -{ - struct switch_ext *switch_ext_p, *ext_value_p; - int rv = 0; - - switch_ext_p = val->value.ext_val; - while (switch_ext_p) { - ext_value_p = switch_ext_p; - - if (!strcmp(ext_value_p->option_name, "name")) { - switch_ext_p = switch_ext_p->next; - continue; - } else if (!strcmp(ext_value_p->option_name, "index")) { - val_ptr[0] = (char*)ext_value_p->option_value; - } else if (!strcmp(ext_value_p->option_name, "type")) { - val_ptr[1] = (char*)ext_value_p->option_value; - } else if (!strcmp(ext_value_p->option_name, "port_id")) { - val_ptr[2] = (char*)ext_value_p->option_value; - } else if (!strcmp(ext_value_p->option_name, "l3if_index")) { - val_ptr[3] = (char*)ext_value_p->option_value; - } else if (!strcmp(ext_value_p->option_name, "ip_to_me_en")) { - val_ptr[4] = (char*)ext_value_p->option_value; - } else if (!strcmp(ext_value_p->option_name, "pub_ip_index")) { - val_ptr[5] = (char*)ext_value_p->option_value; - } else if (!strcmp(ext_value_p->option_name, "stag_fmt")) { - val_ptr[6] = (char*)ext_value_p->option_value; - } else if (!strcmp(ext_value_p->option_name, "svid")) { - val_ptr[7] = (char*)ext_value_p->option_value; - } else if (!strcmp(ext_value_p->option_name, "ctag_fmt")) { - val_ptr[8] = (char*)ext_value_p->option_value; - } else if (!strcmp(ext_value_p->option_name, "cvid")) { - val_ptr[9] = (char*)ext_value_p->option_value; - } else if (!strcmp(ext_value_p->option_name, "macaddr")) { - val_ptr[10] = (char*)ext_value_p->option_value; - } else if (!strcmp(ext_value_p->option_name, "dnat_ip")) { - val_ptr[11] = (char*)ext_value_p->option_value; - } else { - rv = -1; - break; - } - - parameter_length++; - switch_ext_p = switch_ext_p->next; - } - - return rv; -} - -static int -parse_ip_portmac(struct switch_val *val) -{ - struct switch_ext *switch_ext_p, *ext_value_p; - int rv = 0; - - switch_ext_p = val->value.ext_val; - while (switch_ext_p) { - ext_value_p = switch_ext_p; - - if (!strcmp(ext_value_p->option_name, "name")) { - switch_ext_p = switch_ext_p->next; - continue; - } else if (!strcmp(ext_value_p->option_name, "port_id")) { - val_ptr[0] = (char*)ext_value_p->option_value; - } else if (!strcmp(ext_value_p->option_name, "valid")) { - val_ptr[1] = (char*)ext_value_p->option_value; - } else if (!strcmp(ext_value_p->option_name, "macaddr")) { - val_ptr[2] = (char*)ext_value_p->option_value; - } else { - rv = -1; - break; - } - - parameter_length++; - switch_ext_p = switch_ext_p->next; - } - - return rv; -} - -static int -parse_ip_routemiss(struct switch_val *val) -{ - struct switch_ext *switch_ext_p, *ext_value_p; - int rv = 0; - - switch_ext_p = val->value.ext_val; - while (switch_ext_p) { - ext_value_p = switch_ext_p; - - if (!strcmp(ext_value_p->option_name, "name")) { - switch_ext_p = switch_ext_p->next; - continue; - } else if (!strcmp(ext_value_p->option_name, "action")) { - val_ptr[0] = (char*)ext_value_p->option_value; - } else { - rv = -1; - break; - } - - parameter_length++; - switch_ext_p = switch_ext_p->next; - } - - return rv; -} - -static int -parse_ip_mcmode(struct switch_val *val) -{ - struct switch_ext *switch_ext_p, *ext_value_p; - int rv = 0; - - switch_ext_p = val->value.ext_val; - while (switch_ext_p) { - ext_value_p = switch_ext_p; - - if (!strcmp(ext_value_p->option_name, "name")) { - switch_ext_p = switch_ext_p->next; - continue; - } else if (!strcmp(ext_value_p->option_name, "vsi")) { - val_ptr[0] = (char*)ext_value_p->option_value; - } else if (!strcmp(ext_value_p->option_name, "l2_ip4_multicast_en")) { - val_ptr[1] = (char*)ext_value_p->option_value; - } else if (!strcmp(ext_value_p->option_name, "l2_ip4_multicast_mode")) { - val_ptr[2] = (char*)ext_value_p->option_value; - } else if (!strcmp(ext_value_p->option_name, "l2_ip6_multicast_en")) { - val_ptr[3] = (char*)ext_value_p->option_value; - } else if (!strcmp(ext_value_p->option_name, "l2_ip6_multicast_mode")) { - val_ptr[4] = (char*)ext_value_p->option_value; - } else { - rv = -1; - break; - } - - parameter_length++; - switch_ext_p = switch_ext_p->next; - } - - return rv; -} - -static int -parse_ip_globalctrl(struct switch_val *val) -{ - struct switch_ext *switch_ext_p, *ext_value_p; - int rv = 0; - - switch_ext_p = val->value.ext_val; - while (switch_ext_p) { - ext_value_p = switch_ext_p; - - if (!strcmp(ext_value_p->option_name, "name")) { - switch_ext_p = switch_ext_p->next; - continue; - } else if (!strcmp(ext_value_p->option_name, "mru_fail_action")) { - val_ptr[0] = (char*)ext_value_p->option_value; - } else if (!strcmp(ext_value_p->option_name, "mru_deacclr_en")) { - val_ptr[1] = (char*)ext_value_p->option_value; - } else if (!strcmp(ext_value_p->option_name, "mtu_fail_action")) { - val_ptr[2] = (char*)ext_value_p->option_value; - } else if (!strcmp(ext_value_p->option_name, "mtu_deacclr_en")) { - val_ptr[3] = (char*)ext_value_p->option_value; - } else if (!strcmp(ext_value_p->option_name, "mtu_nonfrag_fail_action")) { - val_ptr[4] = (char*)ext_value_p->option_value; - } else if (!strcmp(ext_value_p->option_name, "mtu_nonfrag_deacclr_en")) { - val_ptr[5] = (char*)ext_value_p->option_value; - } else if (!strcmp(ext_value_p->option_name, "prefix_bc_action")) { - val_ptr[6] = (char*)ext_value_p->option_value; - } else if (!strcmp(ext_value_p->option_name, "prefix_deacclr_en")) { - val_ptr[7] = (char*)ext_value_p->option_value; - } else if (!strcmp(ext_value_p->option_name, "icmp_redirect_action")) { - val_ptr[8] = (char*)ext_value_p->option_value; - } else if (!strcmp(ext_value_p->option_name, "icmp_redirect_deacclr_en")) { - val_ptr[9] = (char*)ext_value_p->option_value; - } else if (!strcmp(ext_value_p->option_name, "hash_mode_0")) { - val_ptr[10] = (char*)ext_value_p->option_value; - } else if (!strcmp(ext_value_p->option_name, "hash_mode_1")) { - val_ptr[11] = (char*)ext_value_p->option_value; - } else { - rv = -1; - break; - } - - parameter_length++; - switch_ext_p = switch_ext_p->next; - } - - return rv; -} -#endif -#endif - -#ifdef IN_NAT -static int -parse_nat_natentry(struct switch_val *val) -{ - struct switch_ext *switch_ext_p, *ext_value_p; - int rv = 0; - switch_ext_p = val->value.ext_val; - val_ptr[4] = vrf_dflt_str; - parameter_length ++; - val_ptr[12] = param_dflt_str; - parameter_length ++; - while(switch_ext_p) { - ext_value_p = switch_ext_p; - - if(!strcmp(ext_value_p->option_name, "name")) { - switch_ext_p = switch_ext_p->next; - continue; - } else if(!strcmp(ext_value_p->option_name, "entry_id")) { - val_ptr[0] = (char*)ext_value_p->option_value; - } else if(!strcmp(ext_value_p->option_name, "entry_flags")) { - val_ptr[1] = (char*)ext_value_p->option_value; - } else if(!strcmp(ext_value_p->option_name, "entry_status")) { - val_ptr[2] = (char*)ext_value_p->option_value; - } else if(!strcmp(ext_value_p->option_name, "select_index")) { - val_ptr[3] = (char*)ext_value_p->option_value; - } else if(!strcmp(ext_value_p->option_name, "vrf_id")) { - val_ptr[4] = (char*)ext_value_p->option_value; - parameter_length --; - } else if(!strcmp(ext_value_p->option_name, "src_addr")) { - val_ptr[5] = (char*)ext_value_p->option_value; - } else if(!strcmp(ext_value_p->option_name, "translate_addr")) { - val_ptr[6] = (char*)ext_value_p->option_value; - } else if(!strcmp(ext_value_p->option_name, "port_number")) { - val_ptr[7] = (char*)ext_value_p->option_value; - } else if(!strcmp(ext_value_p->option_name, "port_range")) { - val_ptr[8] = (char*)ext_value_p->option_value; - } else if(!strcmp(ext_value_p->option_name, "action")) { - val_ptr[9] = (char*)ext_value_p->option_value; - } else if(!strcmp(ext_value_p->option_name, "mirror")) { - val_ptr[10] = (char*)ext_value_p->option_value; - } else if(!strcmp(ext_value_p->option_name, "counter")) { - val_ptr[11] = (char*)ext_value_p->option_value; - } else if(!strcmp(ext_value_p->option_name, "counter_id")) { - val_ptr[12] = (char*)ext_value_p->option_value; - parameter_length --; - } else { - rv = -1; - break; - } - - parameter_length++; - switch_ext_p = switch_ext_p->next; - } - - return rv; -} - -static int -parse_nat_naptentry(struct switch_val *val) -{ - struct switch_ext *switch_ext_p, *ext_value_p; - int rv = 0; - switch_ext_p = val->value.ext_val; - val_ptr[3] = vrf_dflt_str; - parameter_length ++; - val_ptr[4] = cookie_dflt_str; - parameter_length ++; - val_ptr[5] = lb_dflt_str; - parameter_length ++; - val_ptr[15] = param_dflt_str; - parameter_length ++; - val_ptr[16] = priority_dflt_str; - parameter_length ++; - val_ptr[17] = param_dflt_str; - parameter_length ++; - while(switch_ext_p) { - ext_value_p = switch_ext_p; - - if(!strcmp(ext_value_p->option_name, "name")) { - switch_ext_p = switch_ext_p->next; - continue; - } else if(!strcmp(ext_value_p->option_name, "entry_id")) { - val_ptr[0] = (char*)ext_value_p->option_value; - } else if(!strcmp(ext_value_p->option_name, "entry_flags")) { - val_ptr[1] = (char*)ext_value_p->option_value; - } else if(!strcmp(ext_value_p->option_name, "entry_status")) { - val_ptr[2] = (char*)ext_value_p->option_value; - } else if(!strcmp(ext_value_p->option_name, "vrf_id")) { - val_ptr[3] = (char*)ext_value_p->option_value; - parameter_length --; - } else if(!strcmp(ext_value_p->option_name, "flow_cookie")) { - val_ptr[4] = (char*)ext_value_p->option_value; - parameter_length --; - } else if(!strcmp(ext_value_p->option_name, "load_balance")) { - val_ptr[5] = (char*)ext_value_p->option_value; - parameter_length --; - } else if(!strcmp(ext_value_p->option_name, "src_addr")) { - val_ptr[6] = (char*)ext_value_p->option_value; - } else if(!strcmp(ext_value_p->option_name, "dst_addr")) { - val_ptr[7] = (char*)ext_value_p->option_value; - } else if(!strcmp(ext_value_p->option_name, "translate_addr")) { - val_ptr[8] = (char*)ext_value_p->option_value; - } else if(!strcmp(ext_value_p->option_name, "src_port")) { - val_ptr[9] = (char*)ext_value_p->option_value; - } else if(!strcmp(ext_value_p->option_name, "dst_port")) { - val_ptr[10] = (char*)ext_value_p->option_value; - } else if(!strcmp(ext_value_p->option_name, "translate_port")) { - val_ptr[11] = (char*)ext_value_p->option_value; - } else if(!strcmp(ext_value_p->option_name, "action")) { - val_ptr[12] = (char*)ext_value_p->option_value; - } else if(!strcmp(ext_value_p->option_name, "mirror")) { - val_ptr[13] = (char*)ext_value_p->option_value; - } else if(!strcmp(ext_value_p->option_name, "counter")) { - val_ptr[14] = (char*)ext_value_p->option_value; - } else if(!strcmp(ext_value_p->option_name, "counter_id")) { - val_ptr[15] = (char*)ext_value_p->option_value; - parameter_length --; - } else if(!strcmp(ext_value_p->option_name, "priority")) { - val_ptr[16] = (char*)ext_value_p->option_value; - parameter_length --; - } else if(!strcmp(ext_value_p->option_name, "priority_val")) { - val_ptr[17] = (char*)ext_value_p->option_value; - parameter_length --; - } else { - rv = -1; - break; - } - - parameter_length++; - switch_ext_p = switch_ext_p->next; - } - - return rv; -} - -static int -parse_nat_flowentry(struct switch_val *val) -{ - struct switch_ext *switch_ext_p, *ext_value_p; - int rv = 0; - switch_ext_p = val->value.ext_val; - val_ptr[13] = param_dflt_str; - parameter_length ++; - val_ptr[15] = param_dflt_str; - parameter_length ++; - while(switch_ext_p) { - ext_value_p = switch_ext_p; - - if(!strcmp(ext_value_p->option_name, "name")) { - switch_ext_p = switch_ext_p->next; - continue; - } else if(!strcmp(ext_value_p->option_name, "entry_id")) { - val_ptr[0] = (char*)ext_value_p->option_value; - } else if(!strcmp(ext_value_p->option_name, "entry_flags")) { - val_ptr[1] = (char*)ext_value_p->option_value; - } else if(!strcmp(ext_value_p->option_name, "entry_status")) { - val_ptr[2] = (char*)ext_value_p->option_value; - } else if(!strcmp(ext_value_p->option_name, "vrf_id")) { - val_ptr[3] = (char*)ext_value_p->option_value; - } else if(!strcmp(ext_value_p->option_name, "flow_cookie")) { - val_ptr[4] = (char*)ext_value_p->option_value; - } else if(!strcmp(ext_value_p->option_name, "load_balance")) { - val_ptr[5] = (char*)ext_value_p->option_value; - } else if(!strcmp(ext_value_p->option_name, "src_addr")) { - val_ptr[6] = (char*)ext_value_p->option_value; - } else if(!strcmp(ext_value_p->option_name, "dst_addr")) { - val_ptr[7] = (char*)ext_value_p->option_value; - } else if(!strcmp(ext_value_p->option_name, "src_port")) { - val_ptr[8] = (char*)ext_value_p->option_value; - } else if(!strcmp(ext_value_p->option_name, "dst_port")) { - val_ptr[9] = (char*)ext_value_p->option_value; - } else if(!strcmp(ext_value_p->option_name, "action")) { - val_ptr[10] = (char*)ext_value_p->option_value; - } else if(!strcmp(ext_value_p->option_name, "mirror")) { - val_ptr[11] = (char*)ext_value_p->option_value; - } else if(!strcmp(ext_value_p->option_name, "counter")) { - val_ptr[12] = (char*)ext_value_p->option_value; - } else if(!strcmp(ext_value_p->option_name, "counter_id")) { - val_ptr[13] = (char*)ext_value_p->option_value; - parameter_length --; - } else if(!strcmp(ext_value_p->option_name, "priority")) { - val_ptr[14] = (char*)ext_value_p->option_value; - } else if(!strcmp(ext_value_p->option_name, "priority_val")) { - val_ptr[15] = (char*)ext_value_p->option_value; - parameter_length --; - } else { - rv = -1; - break; - } - - parameter_length++; - switch_ext_p = switch_ext_p->next; - } - - return rv; -} - -static int -parse_nat_flowcookie(struct switch_val *val) -{ - struct switch_ext *switch_ext_p, *ext_value_p; - int rv = 0; - switch_ext_p = val->value.ext_val; - while(switch_ext_p) { - ext_value_p = switch_ext_p; - - if(!strcmp(ext_value_p->option_name, "name")) { - switch_ext_p = switch_ext_p->next; - continue; - } else if(!strcmp(ext_value_p->option_name, "proto")) { - val_ptr[0] = (char*)ext_value_p->option_value; - } else if(!strcmp(ext_value_p->option_name, "src_addr")) { - val_ptr[1] = (char*)ext_value_p->option_value; - } else if(!strcmp(ext_value_p->option_name, "dst_addr")) { - val_ptr[2] = (char*)ext_value_p->option_value; - } else if(!strcmp(ext_value_p->option_name, "src_port")) { - val_ptr[3] = (char*)ext_value_p->option_value; - } else if(!strcmp(ext_value_p->option_name, "dst_port")) { - val_ptr[4] = (char*)ext_value_p->option_value; - } else if(!strcmp(ext_value_p->option_name, "flow_cookie")) { - val_ptr[5] = (char*)ext_value_p->option_value; - } else { - rv = -1; - break; - } - - parameter_length++; - switch_ext_p = switch_ext_p->next; - } - - return rv; -} - -static int -parse_nat_flowrfs(struct switch_val *val) -{ - struct switch_ext *switch_ext_p, *ext_value_p; - int rv = 0; - switch_ext_p = val->value.ext_val; - while(switch_ext_p) { - ext_value_p = switch_ext_p; - - if(!strcmp(ext_value_p->option_name, "name")) { - switch_ext_p = switch_ext_p->next; - continue; - } else if(!strcmp(ext_value_p->option_name, "action")) { - val_ptr[0] = (char*)ext_value_p->option_value; - } else if(!strcmp(ext_value_p->option_name, "proto")) { - val_ptr[1] = (char*)ext_value_p->option_value; - } else if(!strcmp(ext_value_p->option_name, "src_addr")) { - val_ptr[2] = (char*)ext_value_p->option_value; - } else if(!strcmp(ext_value_p->option_name, "dst_addr")) { - val_ptr[3] = (char*)ext_value_p->option_value; - } else if(!strcmp(ext_value_p->option_name, "src_port")) { - val_ptr[4] = (char*)ext_value_p->option_value; - } else if(!strcmp(ext_value_p->option_name, "dst_port")) { - val_ptr[5] = (char*)ext_value_p->option_value; - } else if(!strcmp(ext_value_p->option_name, "flow_rfs")) { - val_ptr[6] = (char*)ext_value_p->option_value; - } else { - rv = -1; - break; - } - - parameter_length++; - switch_ext_p = switch_ext_p->next; - } - - return rv; -} - - - -static int -parse_nat_natstatus(struct switch_val *val) -{ - struct switch_ext *switch_ext_p, *ext_value_p; - int rv = 0; - switch_ext_p = val->value.ext_val; - while(switch_ext_p) { - ext_value_p = switch_ext_p; - - if(!strcmp(ext_value_p->option_name, "name")) { - switch_ext_p = switch_ext_p->next; - continue; - } else if(!strcmp(ext_value_p->option_name, "status")) { - val_ptr[0] = (char*)ext_value_p->option_value; - } else { - rv = -1; - break; - } - - parameter_length++; - switch_ext_p = switch_ext_p->next; - } - - return rv; -} - -static int -parse_nat_naptstatus(struct switch_val *val) -{ - struct switch_ext *switch_ext_p, *ext_value_p; - int rv = 0; - switch_ext_p = val->value.ext_val; - while(switch_ext_p) { - ext_value_p = switch_ext_p; - - if(!strcmp(ext_value_p->option_name, "name")) { - switch_ext_p = switch_ext_p->next; - continue; - } else if(!strcmp(ext_value_p->option_name, "status")) { - val_ptr[0] = (char*)ext_value_p->option_value; - } else { - rv = -1; - break; - } - - parameter_length++; - switch_ext_p = switch_ext_p->next; - } - - return rv; -} - -static int -parse_nat_nathash(struct switch_val *val) -{ - struct switch_ext *switch_ext_p, *ext_value_p; - int rv = 0; - switch_ext_p = val->value.ext_val; - while(switch_ext_p) { - ext_value_p = switch_ext_p; - - if(!strcmp(ext_value_p->option_name, "name")) { - switch_ext_p = switch_ext_p->next; - continue; - } else if(!strcmp(ext_value_p->option_name, "hash_flag")) { - val_ptr[0] = (char*)ext_value_p->option_value; - } else { - rv = -1; - break; - } - - parameter_length++; - switch_ext_p = switch_ext_p->next; - } - - return rv; -} - -static int -parse_nat_naptmode(struct switch_val *val) -{ - struct switch_ext *switch_ext_p, *ext_value_p; - int rv = 0; - switch_ext_p = val->value.ext_val; - while(switch_ext_p) { - ext_value_p = switch_ext_p; - - if(!strcmp(ext_value_p->option_name, "name")) { - switch_ext_p = switch_ext_p->next; - continue; - } else if(!strcmp(ext_value_p->option_name, "napt_mode")) { - val_ptr[0] = (char*)ext_value_p->option_value; - } else { - rv = -1; - break; - } - - parameter_length++; - switch_ext_p = switch_ext_p->next; - } - - return rv; -} - -static int -parse_nat_prvbaseaddr(struct switch_val *val) -{ - struct switch_ext *switch_ext_p, *ext_value_p; - int rv = 0; - switch_ext_p = val->value.ext_val; - while(switch_ext_p) { - ext_value_p = switch_ext_p; - - if(!strcmp(ext_value_p->option_name, "name")) { - switch_ext_p = switch_ext_p->next; - continue; - } else if(!strcmp(ext_value_p->option_name, "base_addr")) { - val_ptr[0] = (char*)ext_value_p->option_value; - } else { - rv = -1; - break; - } - - parameter_length++; - switch_ext_p = switch_ext_p->next; - } - - return rv; -} - -static int -parse_nat_prvaddrmode(struct switch_val *val) -{ - struct switch_ext *switch_ext_p, *ext_value_p; - int rv = 0; - switch_ext_p = val->value.ext_val; - while(switch_ext_p) { - ext_value_p = switch_ext_p; - - if(!strcmp(ext_value_p->option_name, "name")) { - switch_ext_p = switch_ext_p->next; - continue; - } else if(!strcmp(ext_value_p->option_name, "status")) { - val_ptr[0] = (char*)ext_value_p->option_value; - } else { - rv = -1; - break; - } - - parameter_length++; - switch_ext_p = switch_ext_p->next; - } - - return rv; -} - -static int -parse_nat_pubaddr(struct switch_val *val) -{ - struct switch_ext *switch_ext_p, *ext_value_p; - int rv = 0; - switch_ext_p = val->value.ext_val; - while(switch_ext_p) { - ext_value_p = switch_ext_p; - - if(!strcmp(ext_value_p->option_name, "name")) { - switch_ext_p = switch_ext_p->next; - continue; - } else if(!strcmp(ext_value_p->option_name, "entry_id")) { - val_ptr[0] = (char*)ext_value_p->option_value; - } else if(!strcmp(ext_value_p->option_name, "pub_addr")) { - val_ptr[1] = (char*)ext_value_p->option_value; - } else { - rv = -1; - break; - } - - parameter_length++; - switch_ext_p = switch_ext_p->next; - } - - return rv; -} - -static int -parse_nat_natunksess(struct switch_val *val) -{ - struct switch_ext *switch_ext_p, *ext_value_p; - int rv = 0; - switch_ext_p = val->value.ext_val; - while(switch_ext_p) { - ext_value_p = switch_ext_p; - - if(!strcmp(ext_value_p->option_name, "name")) { - switch_ext_p = switch_ext_p->next; - continue; - } else if(!strcmp(ext_value_p->option_name, "action")) { - val_ptr[0] = (char*)ext_value_p->option_value; - } else { - rv = -1; - break; - } - - parameter_length++; - switch_ext_p = switch_ext_p->next; - } - - return rv; -} - -static int -parse_nat_prvbasemask(struct switch_val *val) -{ - struct switch_ext *switch_ext_p, *ext_value_p; - int rv = 0; - switch_ext_p = val->value.ext_val; - while(switch_ext_p) { - ext_value_p = switch_ext_p; - - if(!strcmp(ext_value_p->option_name, "name")) { - switch_ext_p = switch_ext_p->next; - continue; - } else if(!strcmp(ext_value_p->option_name, "base_addr_mask")) { - val_ptr[0] = (char*)ext_value_p->option_value; - } else { - rv = -1; - break; - } - - parameter_length++; - switch_ext_p = switch_ext_p->next; - } - - return rv; -} - -static int -parse_nat_global(struct switch_val *val) -{ - struct switch_ext *switch_ext_p, *ext_value_p; - int rv = 0; - char *sync_str = "disable"; - char *portbmp_str = "0x20"; - val_ptr[1] = sync_str; - parameter_length++; - val_ptr[2] = portbmp_str; - parameter_length++; - switch_ext_p = val->value.ext_val; - while(switch_ext_p) { - ext_value_p = switch_ext_p; - - if(!strcmp(ext_value_p->option_name, "name")) { - switch_ext_p = switch_ext_p->next; - continue; - } else if(!strcmp(ext_value_p->option_name, "status")) { - val_ptr[0] = (char*)ext_value_p->option_value; - } else if(!strcmp(ext_value_p->option_name, "sync")) { - val_ptr[1] = (char*)ext_value_p->option_value; - parameter_length--; - } else if(!strcmp(ext_value_p->option_name, "portbmp")) { - val_ptr[2] = (char*)ext_value_p->option_value; - parameter_length--; - } else { - rv = -1; - break; - } - - parameter_length++; - switch_ext_p = switch_ext_p->next; - } - - return rv; -} -#endif - -#ifdef IN_STP -static int -parse_stp_portstate(struct switch_val *val) -{ - struct switch_ext *switch_ext_p, *ext_value_p; - int rv = 0; - switch_ext_p = val->value.ext_val; - while(switch_ext_p) { - ext_value_p = switch_ext_p; - - if(!strcmp(ext_value_p->option_name, "name")) { - switch_ext_p = switch_ext_p->next; - continue; - } else if(!strcmp(ext_value_p->option_name, "stp_id")) { - val_ptr[0] = (char*)ext_value_p->option_value; - } else if(!strcmp(ext_value_p->option_name, "port_id")) { - val_ptr[1] = (char*)ext_value_p->option_value; - } else if(!strcmp(ext_value_p->option_name, "stp_status")) { - val_ptr[2] = (char*)ext_value_p->option_value; - } else { - rv = -1; - break; - } - - parameter_length++; - switch_ext_p = switch_ext_p->next; - } - - return rv; -} -#endif - -#ifdef IN_MIRROR -static int -parse_mirror_analypt(struct switch_val *val) -{ - struct switch_ext *switch_ext_p, *ext_value_p; - int rv = 0; - switch_ext_p = val->value.ext_val; - while(switch_ext_p) { - ext_value_p = switch_ext_p; - - if(!strcmp(ext_value_p->option_name, "name")) { - switch_ext_p = switch_ext_p->next; - continue; - } else if(!strcmp(ext_value_p->option_name, "analysis_port")) { - val_ptr[0] = (char*)ext_value_p->option_value; - } else { - rv = -1; - break; - } - - parameter_length++; - switch_ext_p = switch_ext_p->next; - } - - return rv; -} - -static int -parse_mirror_ptingress(struct switch_val *val) -{ - struct switch_ext *switch_ext_p, *ext_value_p; - int rv = 0; - switch_ext_p = val->value.ext_val; - while(switch_ext_p) { - ext_value_p = switch_ext_p; - - if(!strcmp(ext_value_p->option_name, "name")) { - switch_ext_p = switch_ext_p->next; - continue; - } else if(!strcmp(ext_value_p->option_name, "ingress_port")) { - val_ptr[0] = (char*)ext_value_p->option_value; - } else if(!strcmp(ext_value_p->option_name, "status")) { - val_ptr[1] = (char*)ext_value_p->option_value; - } else { - rv = -1; - break; - } - - parameter_length++; - switch_ext_p = switch_ext_p->next; - } - - return rv; -} - -static int -parse_mirror_ptegress(struct switch_val *val) -{ - struct switch_ext *switch_ext_p, *ext_value_p; - int rv = 0; - switch_ext_p = val->value.ext_val; - while(switch_ext_p) { - ext_value_p = switch_ext_p; - - if(!strcmp(ext_value_p->option_name, "name")) { - switch_ext_p = switch_ext_p->next; - continue; - } else if(!strcmp(ext_value_p->option_name, "egress_port")) { - val_ptr[0] = (char*)ext_value_p->option_value; - } else if(!strcmp(ext_value_p->option_name, "status")) { - val_ptr[1] = (char*)ext_value_p->option_value; - } else { - rv = -1; - break; - } - - parameter_length++; - switch_ext_p = switch_ext_p->next; - } - - return rv; -} - -static int -parse_mirror_analycfg(struct switch_val *val) -{ - struct switch_ext *switch_ext_p, *ext_value_p; - int rv = 0; - - switch_ext_p = val->value.ext_val; - while (switch_ext_p) { - ext_value_p = switch_ext_p; - - if (!strcmp(ext_value_p->option_name, "name")) { - switch_ext_p = switch_ext_p->next; - continue; - } else if (!strcmp(ext_value_p->option_name, "direction")) { - val_ptr[0] = (char*)ext_value_p->option_value; - } else if (!strcmp(ext_value_p->option_name, "analysis_port")) { - val_ptr[1] = (char*)ext_value_p->option_value; - } else if (!strcmp(ext_value_p->option_name, "analysis_priority")) { - val_ptr[2] = (char*)ext_value_p->option_value; - } else { - rv = -1; - break; - } - - parameter_length++; - switch_ext_p = switch_ext_p->next; - } - - return rv; -} -#endif - -#ifdef IN_LEAKY -static int -parse_leaky_ucmode(struct switch_val *val) -{ - struct switch_ext *switch_ext_p, *ext_value_p; - int rv = 0; - switch_ext_p = val->value.ext_val; - while(switch_ext_p) { - ext_value_p = switch_ext_p; - - if(!strcmp(ext_value_p->option_name, "name")) { - switch_ext_p = switch_ext_p->next; - continue; - } else if(!strcmp(ext_value_p->option_name, "unicast_leaky_mode")) { - val_ptr[0] = (char*)ext_value_p->option_value; - } else { - rv = -1; - break; - } - - parameter_length++; - switch_ext_p = switch_ext_p->next; - } - - return rv; -} - -static int -parse_leaky_mcmode(struct switch_val *val) -{ - struct switch_ext *switch_ext_p, *ext_value_p; - int rv = 0; - switch_ext_p = val->value.ext_val; - while(switch_ext_p) { - ext_value_p = switch_ext_p; - - if(!strcmp(ext_value_p->option_name, "name")) { - switch_ext_p = switch_ext_p->next; - continue; - } else if(!strcmp(ext_value_p->option_name, "multicast_leaky_mode")) { - val_ptr[0] = (char*)ext_value_p->option_value; - } else { - rv = -1; - break; - } - - parameter_length++; - switch_ext_p = switch_ext_p->next; - } - - return rv; -} - -static int -parse_leaky_arpmode(struct switch_val *val) -{ - struct switch_ext *switch_ext_p, *ext_value_p; - int rv = 0; - switch_ext_p = val->value.ext_val; - while(switch_ext_p) { - ext_value_p = switch_ext_p; - - if(!strcmp(ext_value_p->option_name, "name")) { - switch_ext_p = switch_ext_p->next; - continue; - } else if(!strcmp(ext_value_p->option_name, "port")) { - val_ptr[0] = (char*)ext_value_p->option_value; - } else if(!strcmp(ext_value_p->option_name, "status")) { - val_ptr[1] = (char*)ext_value_p->option_value; - } else { - rv = -1; - break; - } - - parameter_length++; - switch_ext_p = switch_ext_p->next; - } - - return rv; -} - -static int -parse_leaky_ptucmode(struct switch_val *val) -{ - struct switch_ext *switch_ext_p, *ext_value_p; - int rv = 0; - switch_ext_p = val->value.ext_val; - while(switch_ext_p) { - ext_value_p = switch_ext_p; - - if(!strcmp(ext_value_p->option_name, "name")) { - switch_ext_p = switch_ext_p->next; - continue; - } else if(!strcmp(ext_value_p->option_name, "port")) { - val_ptr[0] = (char*)ext_value_p->option_value; - } else if(!strcmp(ext_value_p->option_name, "status")) { - val_ptr[1] = (char*)ext_value_p->option_value; - } else { - rv = -1; - break; - } - - parameter_length++; - switch_ext_p = switch_ext_p->next; - } - - return rv; -} - -static int -parse_leaky_ptmcmode(struct switch_val *val) -{ - struct switch_ext *switch_ext_p, *ext_value_p; - int rv = 0; - switch_ext_p = val->value.ext_val; - while(switch_ext_p) { - ext_value_p = switch_ext_p; - - if(!strcmp(ext_value_p->option_name, "name")) { - switch_ext_p = switch_ext_p->next; - continue; - } else if(!strcmp(ext_value_p->option_name, "port")) { - val_ptr[0] = (char*)ext_value_p->option_value; - } else if(!strcmp(ext_value_p->option_name, "status")) { - val_ptr[1] = (char*)ext_value_p->option_value; - } else { - rv = -1; - break; - } - - parameter_length++; - switch_ext_p = switch_ext_p->next; - } - - return rv; -} -#endif - -#ifdef IN_TRUNK -static int -parse_trunk_group(struct switch_val *val) -{ - struct switch_ext *switch_ext_p, *ext_value_p; - int rv = 0; - switch_ext_p = val->value.ext_val; - while(switch_ext_p) { - ext_value_p = switch_ext_p; - - if(!strcmp(ext_value_p->option_name, "name")) { - switch_ext_p = switch_ext_p->next; - continue; - } else if(!strcmp(ext_value_p->option_name, "trunk_id")) { - val_ptr[0] = (char*)ext_value_p->option_value; - } else if(!strcmp(ext_value_p->option_name, "status")) { - val_ptr[1] = (char*)ext_value_p->option_value; - } else if(!strcmp(ext_value_p->option_name, "trunk_port_bitmap")) { - val_ptr[2] = (char*)ext_value_p->option_value; - } else { - rv = -1; - break; - } - - parameter_length++; - switch_ext_p = switch_ext_p->next; - } - - return rv; -} - -static int -parse_trunk_hashmode(struct switch_val *val) -{ - struct switch_ext *switch_ext_p, *ext_value_p; - int rv = 0; - switch_ext_p = val->value.ext_val; - while(switch_ext_p) { - ext_value_p = switch_ext_p; - - if(!strcmp(ext_value_p->option_name, "name")) { - switch_ext_p = switch_ext_p->next; - continue; - } else if(!strcmp(ext_value_p->option_name, "trunk_hash_mode")) { - val_ptr[0] = (char*)ext_value_p->option_value; - } else { - rv = -1; - break; - } - - parameter_length++; - switch_ext_p = switch_ext_p->next; - } - - return rv; -} - -static int -parse_trunk_failover(struct switch_val *val) -{ - struct switch_ext *switch_ext_p, *ext_value_p; - int rv = 0; - - switch_ext_p = val->value.ext_val; - while (switch_ext_p) { - ext_value_p = switch_ext_p; - - if (!strcmp(ext_value_p->option_name, "name")) { - switch_ext_p = switch_ext_p->next; - continue; - } else if (!strcmp(ext_value_p->option_name, "failover_en")) { - val_ptr[0] = (char*)ext_value_p->option_value; - } else { - rv = -1; - break; - } - - parameter_length++; - switch_ext_p = switch_ext_p->next; - } - - return rv; -} -#endif - -#ifdef IN_MIB -static int -parse_mib_status(struct switch_val *val) -{ - struct switch_ext *switch_ext_p, *ext_value_p; - int rv = 0; - switch_ext_p = val->value.ext_val; - while(switch_ext_p) { - ext_value_p = switch_ext_p; - - if(!strcmp(ext_value_p->option_name, "name")) { - switch_ext_p = switch_ext_p->next; - continue; - } else if(!strcmp(ext_value_p->option_name, "status")) { - val_ptr[0] = (char*)ext_value_p->option_value; - } else { - rv = -1; - break; - } - - parameter_length++; - switch_ext_p = switch_ext_p->next; - } - - return rv; -} - -static int -parse_mib_cpukeep(struct switch_val *val) -{ - struct switch_ext *switch_ext_p, *ext_value_p; - int rv = 0; - switch_ext_p = val->value.ext_val; - while(switch_ext_p) { - ext_value_p = switch_ext_p; - - if(!strcmp(ext_value_p->option_name, "name")) { - switch_ext_p = switch_ext_p->next; - continue; - } else if(!strcmp(ext_value_p->option_name, "status")) { - val_ptr[0] = (char*)ext_value_p->option_value; - } else { - rv = -1; - break; - } - - parameter_length++; - switch_ext_p = switch_ext_p->next; - } - - return rv; -} -#endif - -#ifdef IN_ACL -static int -parse_acl_rule(struct switch_val *val, a_uint32_t dev_id) -{ - a_uint32_t prio = 0; - a_uint32_t i; - a_uint32_t portmap = 0; - a_uint32_t rule_id = 0; - a_uint32_t obj_type = 0; - a_uint32_t obj_value = 0; - a_uint32_t list_id = 0xffffffff; - fal_acl_rule_t rule; - struct switch_ext *switch_ext_p, *ext_value_p; - int rv = 0; - a_uint32_t tmpdata = 0; - memset(&rule, 0, sizeof(fal_acl_rule_t)); - switch_ext_p = val->value.ext_val; - while(switch_ext_p) { - ext_value_p = switch_ext_p; - - if(!strcmp(ext_value_p->option_name, "name")) { - switch_ext_p = switch_ext_p->next; - continue; - } else if(!strcmp(ext_value_p->option_name, "list_id")) { - cmd_data_check_uint32((char*)ext_value_p->option_value, - &list_id, sizeof(a_uint32_t)); - val_ptr[0] = (char*)ext_value_p->option_value; - } else if(!strcmp(ext_value_p->option_name, "rule_id")) { - cmd_data_check_uint32((char*)ext_value_p->option_value, - &rule_id, sizeof(a_uint32_t)); - if(rule_id == 0) { - printk("ACL rule ID should begin with 1. Please Notice!\r\n"); - } - val_ptr[1] = (char*)ext_value_p->option_value; - } else if(!strcmp(ext_value_p->option_name, "priority")) { - cmd_data_check_uint32((char*)ext_value_p->option_value, - &prio, sizeof(a_uint32_t)); - val_ptr[2] = (char*)ext_value_p->option_value; - } else if(!strcmp(ext_value_p->option_name, "rule_type")) { - cmd_data_check_ruletype((char*)ext_value_p->option_value, - &(rule.rule_type), sizeof(a_uint32_t)); - val_ptr[3] = (char*)ext_value_p->option_value; - } else if(!strcmp(ext_value_p->option_name, "is_postrouting")) { - cmd_data_check_confirm((char*)ext_value_p->option_value, A_FALSE, - &(rule.post_routing), sizeof(rule.post_routing)); - FAL_FIELD_FLG_SET(rule.field_flg, - FAL_ACL_FIELD_POST_ROURING_EN); - } else if(!strcmp(ext_value_p->option_name, "acl_pool")) { - cmd_data_check_integer((char*)ext_value_p->option_value, - &(tmpdata), 1, 0); - rule.acl_pool = tmpdata; - FAL_FIELD_FLG_SET(rule.field_flg, - FAL_ACL_FIELD_RES_CHAIN); - } else if(!strcmp(ext_value_p->option_name, "dst_mac_address")) { - cmd_data_check_macaddr((char*)ext_value_p->option_value, - &(rule.dest_mac_val), sizeof(fal_mac_addr_t)); - FAL_FIELD_FLG_SET(rule.field_flg, - FAL_ACL_FIELD_MAC_DA); - } else if(!strcmp(ext_value_p->option_name, "dst_mac_address_mask")) { - cmd_data_check_macaddr((char*)ext_value_p->option_value, - &(rule.dest_mac_mask), sizeof(fal_mac_addr_t)); - } else if(!strcmp(ext_value_p->option_name, "src_mac_address")) { - cmd_data_check_macaddr((char*)ext_value_p->option_value, - &(rule.src_mac_val), sizeof(fal_mac_addr_t)); - FAL_FIELD_FLG_SET(rule.field_flg, - FAL_ACL_FIELD_MAC_SA); - } else if(!strcmp(ext_value_p->option_name, "src_mac_address_mask")) { - cmd_data_check_macaddr((char*)ext_value_p->option_value, - &(rule.src_mac_mask), sizeof(fal_mac_addr_t)); - } else if(!strcmp(ext_value_p->option_name, "ethernet_type")) { - cmd_data_check_uint16((char*)ext_value_p->option_value, - &(tmpdata), sizeof(tmpdata)); - rule.ethtype_val = tmpdata; - FAL_FIELD_FLG_SET(rule.field_flg, - FAL_ACL_FIELD_MAC_ETHTYPE); - } else if(!strcmp(ext_value_p->option_name, "ethernet_type_mask")) { - cmd_data_check_uint16((char*)ext_value_p->option_value, - &(tmpdata), sizeof(tmpdata)); - rule.ethtype_mask = tmpdata; - } else if(!strcmp(ext_value_p->option_name, "vlan_id")) { - cmd_data_check_uint16((char*)ext_value_p->option_value, - &tmpdata, sizeof(tmpdata)); - rule.vid_val = tmpdata; - FAL_FIELD_FLG_SET(rule.field_flg, - FAL_ACL_FIELD_MAC_VID); - } else if(!strcmp(ext_value_p->option_name, "vlan_id_mask")) { - cmd_data_check_uint16((char*)ext_value_p->option_value, - &tmpdata, sizeof(tmpdata)); - rule.vid_mask = tmpdata; - } else if(!strcmp(ext_value_p->option_name, "vlan_priority")) { - cmd_data_check_uint16((char*)ext_value_p->option_value, - &tmpdata, sizeof(tmpdata)); - rule.up_val = tmpdata; - FAL_FIELD_FLG_SET(rule.field_flg, - FAL_ACL_FIELD_MAC_UP); - } else if(!strcmp(ext_value_p->option_name, "vlan_priority_mask")) { - cmd_data_check_uint16((char*)ext_value_p->option_value, - &tmpdata, sizeof(tmpdata)); - rule.up_mask = tmpdata; - } else if(!strcmp(ext_value_p->option_name, "tagged")) { - cmd_data_check_uint16((char*)ext_value_p->option_value, - &tmpdata, sizeof(tmpdata)); - rule.tagged_val = tmpdata; - rule.tagged_mask = 1; - FAL_FIELD_FLG_SET(rule.field_flg, - FAL_ACL_FIELD_MAC_TAGGED); - } else if(!strcmp(ext_value_p->option_name, "tagged_mask")) { - cmd_data_check_uint16((char*)ext_value_p->option_value, - &tmpdata, sizeof(tmpdata)); - rule.tagged_mask = tmpdata; - } else if(!strcmp(ext_value_p->option_name, "cfi")) { - cmd_data_check_uint16((char*)ext_value_p->option_value, - &tmpdata, sizeof(tmpdata)); - rule.cfi_val = tmpdata; - rule.cfi_mask = 1; - FAL_FIELD_FLG_SET(rule.field_flg, - FAL_ACL_FIELD_MAC_CFI); - } else if(!strcmp(ext_value_p->option_name, "ctagged")) { - cmd_data_check_uint16((char*)ext_value_p->option_value, - &tmpdata, sizeof(tmpdata)); - rule.ctagged_val = tmpdata; - rule.ctagged_mask = BITS(0,3); - FAL_FIELD_FLG_SET(rule.field_flg, - FAL_ACL_FIELD_MAC_CTAGGED); - } else if(!strcmp(ext_value_p->option_name, "ctag_vlan_id")) { - cmd_data_check_uint16((char*)ext_value_p->option_value, - &(tmpdata), sizeof(tmpdata)); - rule.ctag_vid_val = tmpdata; - FAL_FIELD_FLG_SET(rule.field_flg, - FAL_ACL_FIELD_MAC_CTAG_VID); - } else if(!strcmp(ext_value_p->option_name, "ctag_vlan_id_mask")) { - cmd_data_check_uint16((char*)ext_value_p->option_value, - &tmpdata, sizeof(tmpdata)); - rule.ctag_vid_mask = tmpdata; - } else if(!strcmp(ext_value_p->option_name, "ctag_vlan_priority")) { - cmd_data_check_uint16((char*)ext_value_p->option_value, - &tmpdata, sizeof(tmpdata)); - rule.ctag_pri_val = tmpdata; - FAL_FIELD_FLG_SET(rule.field_flg, - FAL_ACL_FIELD_MAC_CTAG_PRI); - } else if(!strcmp(ext_value_p->option_name, "ctag_vlan_priority_mask")) { - cmd_data_check_uint16((char*)ext_value_p->option_value, - &tmpdata, sizeof(tmpdata)); - rule.ctag_pri_mask = tmpdata; - } else if(!strcmp(ext_value_p->option_name, "ctag_cfi")) { - cmd_data_check_uint16((char*)ext_value_p->option_value, - &tmpdata, sizeof(tmpdata)); - rule.ctag_cfi_val = tmpdata; - rule.ctag_cfi_mask = 1; - FAL_FIELD_FLG_SET(rule.field_flg, - FAL_ACL_FIELD_MAC_CTAG_CFI); - } else if(!strcmp(ext_value_p->option_name, "stagged")) { - cmd_data_check_uint16((char*)ext_value_p->option_value, - &tmpdata, sizeof(tmpdata)); - rule.stagged_val = tmpdata; - rule.stagged_mask = BITS(0,3); - FAL_FIELD_FLG_SET(rule.field_flg, - FAL_ACL_FIELD_MAC_STAGGED); - } else if(!strcmp(ext_value_p->option_name, "stag_vlan_id")) { - cmd_data_check_uint16((char*)ext_value_p->option_value, - &tmpdata, sizeof(tmpdata)); - rule.stag_vid_val = tmpdata; - FAL_FIELD_FLG_SET(rule.field_flg, - FAL_ACL_FIELD_MAC_STAG_VID); - } else if(!strcmp(ext_value_p->option_name, "stag_vlan_id_mask")) { - cmd_data_check_uint16((char*)ext_value_p->option_value, - &tmpdata, sizeof(tmpdata)); - rule.stag_vid_mask = tmpdata; - } else if(!strcmp(ext_value_p->option_name, "stag_vlan_priority")) { - cmd_data_check_uint16((char*)ext_value_p->option_value, - &tmpdata, sizeof(tmpdata)); - rule.stag_pri_val = tmpdata; - FAL_FIELD_FLG_SET(rule.field_flg, - FAL_ACL_FIELD_MAC_STAG_PRI); - } else if(!strcmp(ext_value_p->option_name, "stag_vlan_priority_mask")) { - cmd_data_check_uint16((char*)ext_value_p->option_value, - &(tmpdata), sizeof(tmpdata)); - rule.stag_pri_mask = tmpdata; - } else if(!strcmp(ext_value_p->option_name, "stag_dei")) { - cmd_data_check_uint16((char*)ext_value_p->option_value, - &tmpdata, sizeof(tmpdata)); - rule.stag_dei_val = tmpdata; - rule.stag_dei_mask = 1; - FAL_FIELD_FLG_SET(rule.field_flg, - FAL_ACL_FIELD_MAC_STAG_DEI); - } else if(!strcmp(ext_value_p->option_name, "ipv4_src_address")) { - cmd_data_check_ip4addr((char*)ext_value_p->option_value, - &(rule.src_ip4_val), 4); - FAL_FIELD_FLG_SET(rule.field_flg, - FAL_ACL_FIELD_IP4_SIP); - } else if(!strcmp(ext_value_p->option_name, "ipv4_src_address_mask")) { - cmd_data_check_ip4addr((char*)ext_value_p->option_value, - &(rule.src_ip4_mask), 4); - } else if(!strcmp(ext_value_p->option_name, "ipv4_dst_address")) { - cmd_data_check_ip4addr((char*)ext_value_p->option_value, - &(rule.dest_ip4_val), 4); - FAL_FIELD_FLG_SET(rule.field_flg, - FAL_ACL_FIELD_IP4_DIP); - } else if(!strcmp(ext_value_p->option_name, "ipv4_dst_address_mask")) { - cmd_data_check_ip4addr((char*)ext_value_p->option_value, - &(rule.dest_ip4_mask), 4); - } else if(!strcmp(ext_value_p->option_name, "ipv6_src_address")) { - cmd_data_check_ip6addr((char*)ext_value_p->option_value, - &(rule.src_ip6_val), 16); - FAL_FIELD_FLG_SET(rule.field_flg, - FAL_ACL_FIELD_IP6_SIP); - } else if(!strcmp(ext_value_p->option_name, "ipv6_src_address_mask")) { - cmd_data_check_ip6addr((char*)ext_value_p->option_value, - &(rule.src_ip6_mask), 16); - } else if(!strcmp(ext_value_p->option_name, "ipv6_dst_address")) { - cmd_data_check_ip6addr((char*)ext_value_p->option_value, - &(rule.dest_ip6_val), 16); - FAL_FIELD_FLG_SET(rule.field_flg, - FAL_ACL_FIELD_IP6_DIP); - } else if(!strcmp(ext_value_p->option_name, "ipv6_dst_address_mask")) { - cmd_data_check_ip6addr((char*)ext_value_p->option_value, - &(rule.dest_ip6_mask), 16); - } else if(!strcmp(ext_value_p->option_name, "ipv6_flow_label")) { - cmd_data_check_uint32((char*)ext_value_p->option_value, - &(rule.ip6_lable_val), - sizeof(rule.ip6_lable_val)); - FAL_FIELD_FLG_SET(rule.field_flg, - FAL_ACL_FIELD_IP6_LABEL); - } else if(!strcmp(ext_value_p->option_name, "ipv6_flow_label_mask")) { - cmd_data_check_uint32((char*)ext_value_p->option_value, - &(rule.ip6_lable_mask), - sizeof(rule.ip6_lable_mask)); - } else if(!strcmp(ext_value_p->option_name, "ip_protocol")) { - cmd_data_check_uint8((char*)ext_value_p->option_value, - &tmpdata, sizeof(tmpdata)); - rule.ip_proto_val = tmpdata; - FAL_FIELD_FLG_SET(rule.field_flg, - FAL_ACL_FIELD_IP_PROTO); - } else if(!strcmp(ext_value_p->option_name, "ip_protocol_mask")) { - cmd_data_check_uint8((char*)ext_value_p->option_value, - &tmpdata, sizeof(tmpdata)); - rule.ip_proto_mask = tmpdata; - } else if(!strcmp(ext_value_p->option_name, "ip_dscp")) { - cmd_data_check_uint8((char*)ext_value_p->option_value, - &tmpdata, sizeof(tmpdata)); - rule.ip_dscp_val = tmpdata; - FAL_FIELD_FLG_SET(rule.field_flg, - FAL_ACL_FIELD_IP_DSCP); - } else if(!strcmp(ext_value_p->option_name, "ip_dscp_mask")) { - cmd_data_check_uint8((char*)ext_value_p->option_value, - &tmpdata, sizeof(tmpdata)); - rule.ip_dscp_mask = tmpdata; - } else if(!strcmp(ext_value_p->option_name, "ip_dst_port")) { - cmd_data_check_uint16((char*)ext_value_p->option_value, - &tmpdata, sizeof(tmpdata)); - rule.dest_l4port_val = tmpdata; - FAL_FIELD_FLG_SET(rule.field_flg, - FAL_ACL_FIELD_L4_DPORT); - rule.dest_l4port_op = FAL_ACL_FIELD_MASK; - } else if(!strcmp(ext_value_p->option_name, "ip_dst_port_mask")) { - cmd_data_check_uint16((char*)ext_value_p->option_value, - &tmpdata, sizeof(tmpdata)); - rule.dest_l4port_mask = tmpdata; - } else if(!strcmp(ext_value_p->option_name, "ip_src_port")) { - cmd_data_check_uint16((char*)ext_value_p->option_value, - &tmpdata, sizeof(tmpdata)); - rule.src_l4port_val = tmpdata; - FAL_FIELD_FLG_SET(rule.field_flg, - FAL_ACL_FIELD_L4_SPORT); - rule.src_l4port_op = FAL_ACL_FIELD_MASK; - } else if(!strcmp(ext_value_p->option_name, "ip_src_port_mask")) { - cmd_data_check_uint16((char*)ext_value_p->option_value, - &tmpdata, sizeof(tmpdata)); - rule.src_l4port_mask = tmpdata; - } else if(!strcmp(ext_value_p->option_name, "icmp_type")) { - cmd_data_check_uint8((char*)ext_value_p->option_value, - &tmpdata, sizeof(tmpdata)); - rule.icmp_type_val = tmpdata; - FAL_FIELD_FLG_SET(rule.field_flg, - FAL_ACL_FIELD_ICMP_TYPE); - } else if(!strcmp(ext_value_p->option_name, "icmp_type_mask")) { - cmd_data_check_uint8((char*)ext_value_p->option_value, - &tmpdata, sizeof(tmpdata)); - rule.icmp_type_mask = tmpdata; - } else if(!strcmp(ext_value_p->option_name, "icmp_code")) { - cmd_data_check_uint8((char*)ext_value_p->option_value, - &tmpdata, sizeof(tmpdata)); - rule.icmp_code_val = tmpdata; - FAL_FIELD_FLG_SET(rule.field_flg, - FAL_ACL_FIELD_ICMP_CODE); - } else if(!strcmp(ext_value_p->option_name, "icmp_code_mask")) { - cmd_data_check_uint8((char*)ext_value_p->option_value, - &tmpdata, sizeof(tmpdata)); - rule.icmp_code_mask = tmpdata; - } else if(!strcmp(ext_value_p->option_name, "tcp_flag")) { - cmd_data_check_uint8((char*)ext_value_p->option_value, - &tmpdata, sizeof(tmpdata)); - rule.tcp_flag_val = tmpdata; - FAL_FIELD_FLG_SET(rule.field_flg, - FAL_ACL_FIELD_TCP_FLAG); - } else if(!strcmp(ext_value_p->option_name, "tcp_flag_mask")) { - cmd_data_check_uint8((char*)ext_value_p->option_value, - &tmpdata, sizeof(tmpdata)); - rule.tcp_flag_mask = tmpdata; - } else if(!strcmp(ext_value_p->option_name, "ripv1")) { - cmd_data_check_uint8((char*)ext_value_p->option_value, - &tmpdata, sizeof(tmpdata)); - rule.ripv1_val = tmpdata; - rule.ripv1_mask = 1; - FAL_FIELD_FLG_SET(rule.field_flg, - FAL_ACL_FIELD_RIPV1); - } else if(!strcmp(ext_value_p->option_name, "dhcpv4")) { - cmd_data_check_uint16((char*)ext_value_p->option_value, - &tmpdata, sizeof(tmpdata)); - rule.dhcpv4_val = tmpdata; - rule.dhcpv4_mask = 1; - FAL_FIELD_FLG_SET(rule.field_flg, - FAL_ACL_FIELD_DHCPV4); - } else if(!strcmp(ext_value_p->option_name, "dhcpv6")) { - cmd_data_check_uint16((char*)ext_value_p->option_value, - &tmpdata, sizeof(tmpdata)); - rule.dhcpv6_val = tmpdata; - rule.dhcpv6_mask = 1; - FAL_FIELD_FLG_SET(rule.field_flg, - FAL_ACL_FIELD_DHCPV6); - } else if(!strcmp(ext_value_p->option_name, "udf_start")) { - cmd_data_check_udf_type((char*)ext_value_p->option_value, - &rule.udf_type, sizeof(rule.udf_type)); - FAL_FIELD_FLG_SET(rule.field_flg, FAL_ACL_FIELD_UDF); - } else if(!strcmp(ext_value_p->option_name, "udf_offset")) { - cmd_data_check_uint8((char*)ext_value_p->option_value, - &tmpdata, sizeof(tmpdata)); - rule.udf_offset = tmpdata; - } else if(!strcmp(ext_value_p->option_name, "udf_length")) { - cmd_data_check_uint8((char*)ext_value_p->option_value, - &tmpdata, sizeof(tmpdata)); - rule.udf_len = tmpdata; - } else if(!strcmp(ext_value_p->option_name, "udf_value")) { - tmpdata = sizeof(rule.udf_val); - cmd_data_check_udf_element((char*)ext_value_p->option_value, - (a_uint8_t *)&rule.udf_val, (a_uint32_t *)&tmpdata); - } else if(!strcmp(ext_value_p->option_name, "udf_mask")) { - tmpdata = sizeof(rule.udf_mask); - cmd_data_check_udf_element((char*)ext_value_p->option_value, - (a_uint8_t *)&rule.udf_mask, (a_uint32_t *)&tmpdata); - } else if(!strcmp(ext_value_p->option_name, "is_ip")) { - cmd_data_check_confirm((char*)ext_value_p->option_value, A_FALSE, - &(rule.is_ip_val), sizeof(rule.is_ip_val)); - rule.is_ip_mask = 1; - FAL_FIELD_FLG_SET(rule.field_flg, FAL_ACL_FIELD_IP); - } else if(!strcmp(ext_value_p->option_name, "is_ip6")) { - cmd_data_check_confirm((char*)ext_value_p->option_value, A_FALSE, - &(rule.is_ipv6_val), sizeof(rule.is_ipv6_val)); - rule.is_ipv6_mask = 1; - FAL_FIELD_FLG_SET(rule.field_flg, FAL_ACL_FIELD_IPV6); - } else if(!strcmp(ext_value_p->option_name, "is_fakemacheader")) { - cmd_data_check_confirm((char*)ext_value_p->option_value, A_FALSE, - &(rule.is_fake_mac_header_val), sizeof(rule.is_fake_mac_header_val)); - rule.is_fake_mac_header_mask = 1; - FAL_FIELD_FLG_SET(rule.field_flg, FAL_ACL_FIELD_FAKE_MAC_HEADER); - } else if(!strcmp(ext_value_p->option_name, "is_snap")) { - cmd_data_check_confirm((char*)ext_value_p->option_value, A_FALSE, - &(rule.is_snap_val), sizeof(rule.is_snap_val)); - rule.is_snap_mask = 1; - FAL_FIELD_FLG_SET(rule.field_flg, FAL_ACL_FIELD_SNAP); - } else if(!strcmp(ext_value_p->option_name, "is_ethernet")) { - cmd_data_check_confirm((char*)ext_value_p->option_value, A_FALSE, - &(rule.is_ethernet_val), sizeof(rule.is_ethernet_val)); - rule.is_ethernet_mask = 1; - FAL_FIELD_FLG_SET(rule.field_flg, FAL_ACL_FIELD_ETHERNET); - } else if(!strcmp(ext_value_p->option_name, "is_fragment")) { - cmd_data_check_confirm((char*)ext_value_p->option_value, A_FALSE, - &(rule.is_fragement_val), sizeof(rule.is_fragement_val)); - rule.is_fragement_mask = 1; - FAL_FIELD_FLG_SET(rule.field_flg, FAL_ACL_FIELD_L3_FRAGMENT); - } else if(!strcmp(ext_value_p->option_name, "is_ahheader")) { - cmd_data_check_confirm((char*)ext_value_p->option_value, A_FALSE, - &(rule.is_ah_header_val), sizeof(rule.is_ah_header_val)); - rule.is_ah_header_mask = 1; - FAL_FIELD_FLG_SET(rule.field_flg, FAL_ACL_FIELD_AH_HEADER); - } else if(!strcmp(ext_value_p->option_name, "is_espheader")) { - cmd_data_check_confirm((char*)ext_value_p->option_value, A_FALSE, - &(rule.is_esp_header_val), sizeof(rule.is_esp_header_val)); - rule.is_esp_header_mask = 1; - FAL_FIELD_FLG_SET(rule.field_flg, FAL_ACL_FIELD_ESP_HEADER); - } else if(!strcmp(ext_value_p->option_name, "is_mobilityheader")) { - cmd_data_check_confirm((char*)ext_value_p->option_value, A_FALSE, - &(rule.is_mobility_header_val), sizeof(rule.is_mobility_header_val)); - rule.is_mobility_header_val = 1; - FAL_FIELD_FLG_SET(rule.field_flg, FAL_ACL_FIELD_MOBILITY_HEADER); - } else if(!strcmp(ext_value_p->option_name, "is_fragmentheader")) { - cmd_data_check_confirm((char*)ext_value_p->option_value, A_FALSE, - &(rule.is_fragment_header_val), sizeof(rule.is_fragment_header_val)); - rule.is_fragment_header_mask = 1; - FAL_FIELD_FLG_SET(rule.field_flg, FAL_ACL_FIELD_FRAGMENT_HEADER); - } else if(!strcmp(ext_value_p->option_name, "is_otherheader")) { - cmd_data_check_confirm((char*)ext_value_p->option_value, A_FALSE, - &(rule.is_other_header_val), sizeof(rule.is_other_header_val)); - rule.is_other_header_mask = 1; - FAL_FIELD_FLG_SET(rule.field_flg, FAL_ACL_FIELD_OTHER_EXT_HEADER); - } else if(!strcmp(ext_value_p->option_name, "is_ip4option")) { - cmd_data_check_confirm((char*)ext_value_p->option_value, A_FALSE, - &(rule.is_ipv4_option_val), sizeof(rule.is_ipv4_option_val)); - rule.is_ipv4_option_mask = 1; - FAL_FIELD_FLG_SET(rule.field_flg, FAL_ACL_FIELD_IPV4_OPTION); - } else if(!strcmp(ext_value_p->option_name, "is_firstfragment")) { - cmd_data_check_confirm((char*)ext_value_p->option_value, A_FALSE, - &(rule.is_first_frag_val), sizeof(rule.is_first_frag_val)); - rule.is_first_frag_mask = 1; - FAL_FIELD_FLG_SET(rule.field_flg, FAL_ACL_FIELD_FIRST_FRAGMENT); - } else if(!strcmp(ext_value_p->option_name, "vsi_valid")) { - cmd_data_check_confirm((char*)ext_value_p->option_value, A_FALSE, - &(rule.vsi_valid), sizeof(rule.vsi_valid)); - rule.vsi_mask = 1; - FAL_FIELD_FLG_SET(rule.field_flg, FAL_ACL_FIELD_VSI_VALID); - } else if(!strcmp(ext_value_p->option_name, "vsi")) { - cmd_data_check_uint8((char*)ext_value_p->option_value, - &tmpdata, sizeof(tmpdata)); - rule.vsi = tmpdata; - FAL_FIELD_FLG_SET(rule.field_flg, FAL_ACL_FIELD_VSI); - } else if(!strcmp(ext_value_p->option_name, "vsi_mask")) { - cmd_data_check_uint8((char*)ext_value_p->option_value, - &tmpdata, sizeof(tmpdata)); - rule.vsi_mask = tmpdata; - } else if(!strcmp(ext_value_p->option_name, "pppoe_session_id")) { - cmd_data_check_uint16((char*)ext_value_p->option_value, - &tmpdata, sizeof(tmpdata)); - rule.pppoe_sessionid = tmpdata; - FAL_FIELD_FLG_SET(rule.field_flg, FAL_ACL_FIELD_PPPOE_SESSIONID); - } else if(!strcmp(ext_value_p->option_name, "pppoe_session_id_mask")) { - cmd_data_check_uint16((char*)ext_value_p->option_value, - &tmpdata, sizeof(tmpdata)); - rule.pppoe_sessionid_mask = tmpdata; - } else if(!strcmp(ext_value_p->option_name, "l3ttl")) { - cmd_data_check_uint8((char*)ext_value_p->option_value, - &tmpdata, sizeof(tmpdata)); - rule.l3_ttl = tmpdata; - FAL_FIELD_FLG_SET(rule.field_flg, FAL_ACL_FIELD_L3_TTL); - } else if(!strcmp(ext_value_p->option_name, "l3ttl_mask")) { - cmd_data_check_uint8((char*)ext_value_p->option_value, - &tmpdata, sizeof(tmpdata)); - rule.l3_ttl_mask= tmpdata; - } else if(!strcmp(ext_value_p->option_name, "l3length")) { - cmd_data_check_uint16((char*)ext_value_p->option_value, - &tmpdata, sizeof(tmpdata)); - rule.l3_length = tmpdata; - FAL_FIELD_FLG_SET(rule.field_flg, FAL_ACL_FIELD_L3_LENGTH); - } else if(!strcmp(ext_value_p->option_name, "l3length_mask")) { - cmd_data_check_uint16((char*)ext_value_p->option_value, - &tmpdata, sizeof(tmpdata)); - rule.l3_length_mask = tmpdata; - } else if(!strcmp(ext_value_p->option_name, "l3packettype")) { - cmd_data_check_uint16((char*)ext_value_p->option_value, - &tmpdata, sizeof(tmpdata)); - rule.l3_pkt_type = tmpdata; - FAL_FIELD_FLG_SET(rule.field_flg, FAL_ACL_FIELD_IP_PKT_TYPE); - } else if(!strcmp(ext_value_p->option_name, "l3packettype_mask")) { - cmd_data_check_uint16((char*)ext_value_p->option_value, - &tmpdata, sizeof(tmpdata)); - rule.l3_pkt_type_mask = tmpdata; - } else if(!strcmp(ext_value_p->option_name, "user_defined_op0")) { - fal_acl_field_op_t op = FAL_ACL_FIELD_MASK; - cmd_data_check_fieldop((char*)ext_value_p->option_value, - FAL_ACL_FIELD_MASK, &op); - printk("%s, %d", (char*)ext_value_p->option_value, op); - rule.udf0_op= op; - } else if(!strcmp(ext_value_p->option_name, "user_defined_val0")) { - cmd_data_check_uint16((char*)ext_value_p->option_value, - &tmpdata, sizeof(tmpdata)); - rule.udf0_val = tmpdata; - FAL_FIELD_FLG_SET(rule.field_flg, FAL_ACL_FIELD_UDF0); - } else if(!strcmp(ext_value_p->option_name, "user_defined_val0_mask")) { - cmd_data_check_uint16((char*)ext_value_p->option_value, - &tmpdata, sizeof(tmpdata)); - rule.udf0_mask = tmpdata; - } else if(!strcmp(ext_value_p->option_name, "user_defined_op1")) { - fal_acl_field_op_t op = FAL_ACL_FIELD_MASK; - cmd_data_check_fieldop((char*)ext_value_p->option_value, - FAL_ACL_FIELD_MASK, &op); - rule.udf1_op= op; - } else if(!strcmp(ext_value_p->option_name, "user_defined_val1")) { - cmd_data_check_uint16((char*)ext_value_p->option_value, - &tmpdata, sizeof(tmpdata)); - rule.udf1_val = tmpdata; - FAL_FIELD_FLG_SET(rule.field_flg, FAL_ACL_FIELD_UDF1); - } else if(!strcmp(ext_value_p->option_name, "user_defined_val1_mask")) { - cmd_data_check_uint16((char*)ext_value_p->option_value, - &tmpdata, sizeof(tmpdata)); - rule.udf1_mask = tmpdata; - } else if(!strcmp(ext_value_p->option_name, "user_defined_val2")) { - cmd_data_check_uint16((char*)ext_value_p->option_value, - &tmpdata, sizeof(tmpdata)); - rule.udf2_val = tmpdata; - FAL_FIELD_FLG_SET(rule.field_flg, FAL_ACL_FIELD_UDF2); - } else if(!strcmp(ext_value_p->option_name, "user_defined_val2_mask")) { - cmd_data_check_uint16((char*)ext_value_p->option_value, - &tmpdata, sizeof(tmpdata)); - rule.udf2_mask = tmpdata; - } else if(!strcmp(ext_value_p->option_name, "user_defined_val3")) { - cmd_data_check_uint16((char*)ext_value_p->option_value, - &tmpdata, sizeof(tmpdata)); - rule.udf3_val = tmpdata; - FAL_FIELD_FLG_SET(rule.field_flg, FAL_ACL_FIELD_UDF3); - } else if(!strcmp(ext_value_p->option_name, "user_defined_val3_mask")) { - cmd_data_check_uint16((char*)ext_value_p->option_value, - &tmpdata, sizeof(tmpdata)); - rule.udf3_mask = tmpdata; - } else if(!strcmp(ext_value_p->option_name, "inverse_check_fields")) { - if (!strcmp(ext_value_p->option_value, "y") || - !strcmp(ext_value_p->option_value, "yes")) { - FAL_FIELD_FLG_SET(rule.field_flg, - FAL_ACL_FIELD_INVERSE_ALL); - } else if(!strcmp(ext_value_p->option_value, "n") || - !strcmp(ext_value_p->option_value, "no")) { - FAL_FIELD_FLG_CLR(rule.field_flg, - FAL_ACL_FIELD_INVERSE_ALL); - } - } else if(!strcmp(ext_value_p->option_name, "packet_drop")) { - if(!strcmp(ext_value_p->option_value, "y") || - !strcmp(ext_value_p->option_value, "yes")) { - FAL_ACTION_FLG_SET(rule.action_flg, - FAL_ACL_ACTION_DENY); - } else if(!strcmp(ext_value_p->option_value, "n") || - !strcmp(ext_value_p->option_value, "no")){ - FAL_ACTION_FLG_CLR(rule.action_flg, - FAL_ACL_ACTION_DENY); - FAL_ACTION_FLG_SET(rule.action_flg, - FAL_ACL_ACTION_PERMIT); - } - } else if(!strcmp(ext_value_p->option_name, "dscp_of_remark")) { - cmd_data_check_uint8((char*)ext_value_p->option_value, - &tmpdata, sizeof(tmpdata)); - rule.dscp = tmpdata; - FAL_ACTION_FLG_SET(rule.action_flg, - FAL_ACL_ACTION_REMARK_DSCP); - } -#if defined(CPPE) - else if(!strcmp(ext_value_p->option_name, "dscp_of_remark_mask")) { - cmd_data_check_uint8((char*)ext_value_p->option_value, - &tmpdata, sizeof(tmpdata)); - rule.dscp_mask = tmpdata; - } -#endif - else if(!strcmp(ext_value_p->option_name, "vlan_priority_of_remark")) { - cmd_data_check_uint8((char*)ext_value_p->option_value, - &tmpdata, sizeof(tmpdata)); - rule.up = tmpdata; - } else if(!strcmp(ext_value_p->option_name, "queue_of_remark")) { - cmd_data_check_uint8((char*)ext_value_p->option_value, - &tmpdata, sizeof(tmpdata)); - rule.queue = tmpdata; - FAL_ACTION_FLG_SET(rule.action_flg, - FAL_ACL_ACTION_REMARK_QUEUE); - } else if(!strcmp(ext_value_p->option_name, "port_bitmap")) { - cmd_data_check_pbmp((char*)ext_value_p->option_value, &portmap, 4); - } else if(!strcmp((char*)ext_value_p->option_name, "obj_type")) { - cmd_data_check_uint32((char*)ext_value_p->option_value, &obj_type, 4); - } else if(!strcmp((char*)ext_value_p->option_name, "obj_value")) { - cmd_data_check_uint32((char*)ext_value_p->option_value, &obj_value, 4); - } else if(!strcmp((char*)ext_value_p->option_name, "user_defined_field_value")) { - cmd_data_check_udf_element((char*)ext_value_p->option_value, - (a_uint8_t *)&(rule.udf_val[0]), (a_uint32_t *)&(rule.udf_len)); - FAL_FIELD_FLG_SET(rule.field_flg, - FAL_ACL_FIELD_UDF); - } else if(!strcmp(ext_value_p->option_name, "user_defined_field_mask")) { - cmd_data_check_udf_element((char*)ext_value_p->option_value, - (a_uint8_t *)&(rule.udf_mask[0]), (a_uint32_t *)&(rule.udf_len)); - } else if(!strcmp(ext_value_p->option_name, "redirect_to_cpu")) { - if(!strcmp(ext_value_p->option_value, "y") || - !strcmp(ext_value_p->option_value, "yes")) { - FAL_ACTION_FLG_SET(rule.action_flg, - FAL_ACL_ACTION_RDTCPU); - } else if(!strcmp(ext_value_p->option_value, "n") || - !strcmp(ext_value_p->option_value, "no")){ - FAL_ACTION_FLG_CLR(rule.action_flg, - FAL_ACL_ACTION_RDTCPU); - } - } else if(!strcmp(ext_value_p->option_name, "copy_to_cpu")) { - if(!strcmp(ext_value_p->option_value, "y") || - !strcmp(ext_value_p->option_value, "yes")) { - FAL_ACTION_FLG_SET(rule.action_flg, - FAL_ACL_ACTION_CPYCPU); - } else if(!strcmp(ext_value_p->option_value, "n") || - !strcmp(ext_value_p->option_value, "no")){ - FAL_ACTION_FLG_CLR(rule.action_flg, - FAL_ACL_ACTION_CPYCPU); - } - } else if(!strcmp(ext_value_p->option_name, "redirect_to_ports")) { - FAL_ACTION_FLG_SET(rule.action_flg, - FAL_ACL_ACTION_REDPT); - cmd_data_check_pbmp((char*)ext_value_p->option_value, &rule.ports, 4); - } else if(!strcmp(ext_value_p->option_name, "mirror")) { - if(!strcmp(ext_value_p->option_value, "y") || - !strcmp(ext_value_p->option_value, "yes")) { - FAL_ACTION_FLG_SET(rule.action_flg, - FAL_ACL_ACTION_MIRROR); - } else if(!strcmp(ext_value_p->option_value, "n") || - !strcmp(ext_value_p->option_value, "no")){ - FAL_ACTION_FLG_CLR(rule.action_flg, - FAL_ACL_ACTION_MIRROR); - } - } else if(!strcmp(ext_value_p->option_name, "remark_lookup_vid")) { - if(!strcmp(ext_value_p->option_value, "y") || - !strcmp(ext_value_p->option_value, "yes")) { - FAL_ACTION_FLG_SET(rule.action_flg, - FAL_ACL_ACTION_REMARK_LOOKUP_VID); - } else if(!strcmp(ext_value_p->option_value, "n") || - !strcmp(ext_value_p->option_value, "no")){ - FAL_ACTION_FLG_CLR(rule.action_flg, - FAL_ACL_ACTION_REMARK_LOOKUP_VID); - } - } else if(!strcmp(ext_value_p->option_name, "stag_vid_of_remark")) { - FAL_ACTION_FLG_SET(rule.action_flg, - FAL_ACL_ACTION_REMARK_STAG_VID); - cmd_data_check_uint16((char*)ext_value_p->option_value, (a_uint32_t *)&rule.stag_vid, 4); - } else if(!strcmp(ext_value_p->option_name, "stag_priority_of_remark")) { - FAL_ACTION_FLG_SET(rule.action_flg, - FAL_ACL_ACTION_REMARK_STAG_PRI); - cmd_data_check_uint16((char*)ext_value_p->option_value, (a_uint32_t *)&rule.stag_pri, 4); - } else if(!strcmp(ext_value_p->option_name, "stag_dei_of_remark")) { - FAL_ACTION_FLG_SET(rule.action_flg, - FAL_ACL_ACTION_REMARK_STAG_DEI); - cmd_data_check_uint16((char*)ext_value_p->option_value, (a_uint32_t *)&rule.stag_dei, 4); - } else if(!strcmp(ext_value_p->option_name, "ctag_vid_of_remark")) { - FAL_ACTION_FLG_SET(rule.action_flg, - FAL_ACL_ACTION_REMARK_CTAG_VID); - cmd_data_check_uint16((char*)ext_value_p->option_value, (a_uint32_t *)&rule.ctag_vid, 4); - } else if(!strcmp(ext_value_p->option_name, "ctag_priority_of_remark")) { - FAL_ACTION_FLG_SET(rule.action_flg, - FAL_ACL_ACTION_REMARK_CTAG_PRI); - cmd_data_check_uint16((char*)ext_value_p->option_value, (a_uint32_t *)&rule.ctag_pri, 4); - } else if(!strcmp(ext_value_p->option_name, "ctag_cfi_of_remark")) { - FAL_ACTION_FLG_SET(rule.action_flg, - FAL_ACL_ACTION_REMARK_CTAG_CFI); - cmd_data_check_uint16((char*)ext_value_p->option_value, (a_uint32_t *)&rule.ctag_cfi, 4); - } else if(!strcmp(ext_value_p->option_name, "action_policer_id")) { - cmd_data_check_uint16((char*)ext_value_p->option_value, - (a_uint32_t *)&(rule.policer_ptr), sizeof(a_uint32_t)); - FAL_ACTION_FLG_SET(rule.action_flg, - FAL_ACL_ACTION_POLICER_EN); - } else if(!strcmp(ext_value_p->option_name, "action_arp_ptr")) { - cmd_data_check_uint16((char*)ext_value_p->option_value, - (a_uint32_t *)&(rule.arp_ptr), sizeof(a_uint32_t)); - FAL_ACTION_FLG_SET(rule.action_flg, - FAL_ACL_ACTION_ARP_EN); - } else if(!strcmp(ext_value_p->option_name, "action_wcmp_ptr")) { - cmd_data_check_uint16((char*)ext_value_p->option_value, - (a_uint32_t *)&(rule.wcmp_ptr), sizeof(a_uint32_t)); - FAL_ACTION_FLG_SET(rule.action_flg, - FAL_ACL_ACTION_WCMP_EN); - } else if(!strcmp(ext_value_p->option_name, "action_snat")) { - if(!strcmp(ext_value_p->option_value, "y") || - !strcmp(ext_value_p->option_value, "yes")) { - FAL_ACTION_FLG_SET(rule.action_flg, - FAL_ACL_ACTION_POLICY_FORWARD_EN); - rule.policy_fwd |= FAL_ACL_POLICY_SNAT; - } else if(!strcmp(ext_value_p->option_value, "n") || - !strcmp(ext_value_p->option_value, "no")){ - rule.policy_fwd &= ~ FAL_ACL_POLICY_SNAT; - } - } else if(!strcmp(ext_value_p->option_name, "action_dnat")) { - if(!strcmp(ext_value_p->option_value, "y") || - !strcmp(ext_value_p->option_value, "yes")) { - FAL_ACTION_FLG_SET(rule.action_flg, - FAL_ACL_ACTION_POLICY_FORWARD_EN); - rule.policy_fwd |= FAL_ACL_POLICY_DNAT; - } else if(!strcmp(ext_value_p->option_value, "n") || - !strcmp(ext_value_p->option_value, "no")){ - rule.policy_fwd &= ~ FAL_ACL_POLICY_DNAT; - } - } else if(!strcmp(ext_value_p->option_name, "bypass_egress_translation")) { - if(!strcmp(ext_value_p->option_value, "y") || - !strcmp(ext_value_p->option_value, "yes")) { - FAL_ACTION_FLG_SET(rule.action_flg, - FAL_ACL_ACTION_BYPASS_EGRESS_TRANS); - } else if(!strcmp(ext_value_p->option_value, "n") || - !strcmp(ext_value_p->option_value, "no")){ - FAL_ACTION_FLG_CLR(rule.action_flg, - FAL_ACL_ACTION_BYPASS_EGRESS_TRANS); - } - } else if(!strcmp(ext_value_p->option_name, "interrupt_trigger")) { - if(!strcmp(ext_value_p->option_value, "y") || - !strcmp(ext_value_p->option_value, "yes")) { - FAL_ACTION_FLG_SET(rule.action_flg, - FAL_ACL_ACTION_MATCH_TRIGGER_INTR); - } else if(!strcmp(ext_value_p->option_value, "n") || - !strcmp(ext_value_p->option_value, "no")){ - FAL_ACTION_FLG_CLR(rule.action_flg, - FAL_ACL_ACTION_MATCH_TRIGGER_INTR); - } - } else if(!strcmp(ext_value_p->option_name, "bypass_bitmap")) { - cmd_data_check_uint32((char*)ext_value_p->option_value, - &(rule.bypass_bitmap), sizeof(rule.bypass_bitmap)); - } else if(!strcmp(ext_value_p->option_name, "enqueue_priority")) { - cmd_data_check_uint8((char*)ext_value_p->option_value, - &tmpdata, sizeof(tmpdata)); - rule.enqueue_pri = tmpdata; - FAL_ACTION_FLG_SET(rule.action_flg, FAL_ACL_ACTION_ENQUEUE_PRI); - } else if(!strcmp(ext_value_p->option_name, "stagformat")) { - cmd_data_check_uint8((char*)ext_value_p->option_value, - &tmpdata, sizeof(tmpdata)); - rule.stag_fmt = tmpdata; - FAL_ACTION_FLG_SET(rule.action_flg, FAL_ACL_ACTION_REMARK_STAG_VID); - } else if(!strcmp(ext_value_p->option_name, "ctagformat")) { - cmd_data_check_uint8((char*)ext_value_p->option_value, - &tmpdata, sizeof(tmpdata)); - rule.ctag_fmt = tmpdata; - FAL_ACTION_FLG_SET(rule.action_flg, FAL_ACL_ACTION_REMARK_CTAG_VID); - } else if(!strcmp(ext_value_p->option_name, "internaldropprec")) { - cmd_data_check_uint8((char*)ext_value_p->option_value, - &tmpdata, sizeof(tmpdata)); - rule.int_dp = tmpdata; - FAL_ACTION_FLG_SET(rule.action_flg, FAL_ACL_ACTION_INT_DP); - } else if(!strcmp(ext_value_p->option_name, "servicecode")) { - cmd_data_check_uint8((char*)ext_value_p->option_value, - &tmpdata, sizeof(tmpdata)); - rule.service_code= tmpdata; - FAL_ACTION_FLG_SET(rule.action_flg, FAL_ACL_ACTION_SERVICE_CODE); - } else if(!strcmp(ext_value_p->option_name, "cpucode")) { - cmd_data_check_uint8((char*)ext_value_p->option_value, - &tmpdata, sizeof(tmpdata)); - rule.cpu_code = tmpdata; - FAL_ACTION_FLG_SET(rule.action_flg, FAL_ACL_ACTION_CPU_CODE); - } else if(!strcmp(ext_value_p->option_name, "metadata_en")) { - cmd_data_check_uint8((char*)ext_value_p->option_value, - &tmpdata, sizeof(tmpdata)); - if(tmpdata) - FAL_ACTION_FLG_SET(rule.action_flg, FAL_ACL_ACTION_METADATA_EN); - } else if(!strcmp(ext_value_p->option_name, "synctoggle")) { - cmd_data_check_uint8((char*)ext_value_p->option_value, - &tmpdata, sizeof(tmpdata)); - if(tmpdata) - FAL_ACTION_FLG_SET(rule.action_flg, FAL_ACL_ACTION_SYN_TOGGLE); - } -#if defined(CPPE) - else if(!strcmp(ext_value_p->option_name, "qos_res_prec")) { - cmd_data_check_uint8((char*)ext_value_p->option_value, - &tmpdata, sizeof(tmpdata)); - rule.qos_res_prec = tmpdata; - } -#endif - - parameter_length++; - switch_ext_p = switch_ext_p->next; - } - /*to be compatible with previous version which didn't define list id*/ - if(0xffffffff == list_id) { - list_id = rule_id; - rule_id = 0; - } else { - rule.pri = prio & 0x7; - prio = (prio >> 3) & 0x3f; - } - SSDK_DEBUG("uci set acl list %d, rule %d\n", list_id, rule_id); - SSDK_DEBUG("uci set acl portbitmap 0x%x, obj_type %d, obj_value %d\n", - portmap, obj_type, obj_value); - fal_acl_list_creat(dev_id, list_id, prio); - fal_acl_rule_add(dev_id, list_id, rule_id, 1, &rule); - /*bind to port bitmap*/ - if( portmap != 0 ) { - for (i = 0; i < AR8327_NUM_PORTS; i++) { - fal_acl_list_unbind(dev_id, list_id, 0, 0, i); - if (portmap & (0x1 << i)) { - rv = fal_acl_list_bind(dev_id, list_id, 0, 0, i); - if(rv != SW_OK){ - SSDK_ERROR("uci set acl fail %d\n", rv); - } - } - } - } else { - rv = fal_acl_list_bind(dev_id, list_id, 0, obj_type, obj_value); - if(rv != SW_OK){ - SSDK_ERROR("uci set acl fail %d\n", rv); - } - } - fal_acl_status_set(dev_id, A_TRUE); - - return rv; -} - -static int -parse_acl_udfprofile(struct switch_val *val) -{ - struct switch_ext *switch_ext_p, *ext_value_p; - int rv = 0; - switch_ext_p = val->value.ext_val; - while(switch_ext_p) { - ext_value_p = switch_ext_p; - - if(!strcmp(ext_value_p->option_name, "name")) { - switch_ext_p = switch_ext_p->next; - continue; - } else if(!strcmp(ext_value_p->option_name, "port")) { - val_ptr[0] = (char*)ext_value_p->option_value; - } else if(!strcmp(ext_value_p->option_name, "user_defined_type")) { - val_ptr[1] = (char*)ext_value_p->option_value; - } else if(!strcmp(ext_value_p->option_name, "user_defined_offset")) { - val_ptr[2] = (char*)ext_value_p->option_value; - } else if(!strcmp(ext_value_p->option_name, "user_defined_length")) { - val_ptr[3] = (char*)ext_value_p->option_value; - } else { - rv = -1; - break; - } - - parameter_length++; - switch_ext_p = switch_ext_p->next; - } - - return rv; -} - -static int -parse_acl_udf(struct switch_val *val) -{ - struct switch_ext *switch_ext_p, *ext_value_p; - int rv = 0; - - switch_ext_p = val->value.ext_val; - while (switch_ext_p) { - ext_value_p = switch_ext_p; - - if (!strcmp(ext_value_p->option_name, "name")) { - switch_ext_p = switch_ext_p->next; - continue; - } else if (!strcmp(ext_value_p->option_name, "packet_type")) { - val_ptr[0] = (char*)ext_value_p->option_value; - } else if (!strcmp(ext_value_p->option_name, "index")) { - val_ptr[1] = (char*)ext_value_p->option_value; - } else if (!strcmp(ext_value_p->option_name, "user_defined_type")) { - val_ptr[2] = (char*)ext_value_p->option_value; - } else if (!strcmp(ext_value_p->option_name, "user_defined_offset")) { - val_ptr[3] = (char*)ext_value_p->option_value; - } else { - rv = -1; - break; - } - - parameter_length++; - switch_ext_p = switch_ext_p->next; - } - - return rv; -} - -#endif - -#ifdef IN_FLOW -static int -parse_flow_entry(struct switch_val *val) -{ - struct switch_ext *switch_ext_p, *ext_value_p; - int rv = 0; - - switch_ext_p = val->value.ext_val; - while (switch_ext_p) { - ext_value_p = switch_ext_p; - - if (!strcmp(ext_value_p->option_name, "name")) { - switch_ext_p = switch_ext_p->next; - continue; - } else if (!strcmp(ext_value_p->option_name, "add_mode")) { - val_ptr[0] = (char*)ext_value_p->option_value; - } else if (!strcmp(ext_value_p->option_name, "entry_id")) { - val_ptr[1] = (char*)ext_value_p->option_value; - } else if (!strcmp(ext_value_p->option_name, "entrytype")) { - val_ptr[2] = (char*)ext_value_p->option_value; - } else if (!strcmp(ext_value_p->option_name, "host_addr_type")) { - val_ptr[3] = (char*)ext_value_p->option_value; - } else if (!strcmp(ext_value_p->option_name, "host_addr_index")) { - val_ptr[4] = (char*)ext_value_p->option_value; - } else if (!strcmp(ext_value_p->option_name, "protocol")) { - val_ptr[5] = (char*)ext_value_p->option_value; - } else if (!strcmp(ext_value_p->option_name, "age")) { - val_ptr[6] = (char*)ext_value_p->option_value; - } else if (!strcmp(ext_value_p->option_name, "srcintf_valid")) { - val_ptr[7] = (char*)ext_value_p->option_value; - } else if (!strcmp(ext_value_p->option_name, "srcintf_index")) { - val_ptr[8] = (char*)ext_value_p->option_value; - } else if (!strcmp(ext_value_p->option_name, "fwdtype")) { - val_ptr[9] = (char*)ext_value_p->option_value; - } else if (!strcmp(ext_value_p->option_name, "snat_nexthop")) { - val_ptr[10] = (char*)ext_value_p->option_value; - } else if (!strcmp(ext_value_p->option_name, "snat_srcport")) { - val_ptr[11] = (char*)ext_value_p->option_value; - } else if (!strcmp(ext_value_p->option_name, "dnat_nexthop")) { - val_ptr[12] = (char*)ext_value_p->option_value; - } else if (!strcmp(ext_value_p->option_name, "dnat_dstport")) { - val_ptr[13] = (char*)ext_value_p->option_value; - } else if (!strcmp(ext_value_p->option_name, "route_nexthop")) { - val_ptr[14] = (char*)ext_value_p->option_value; - } else if (!strcmp(ext_value_p->option_name, "portvalid")) { - val_ptr[15] = (char*)ext_value_p->option_value; - } else if (!strcmp(ext_value_p->option_name, "routeport")) { - val_ptr[16] = (char*)ext_value_p->option_value; - } else if (!strcmp(ext_value_p->option_name, "bridgeport")) { - val_ptr[17] = (char*)ext_value_p->option_value; - } else if (!strcmp(ext_value_p->option_name, "deacclr_en")) { - val_ptr[18] = (char*)ext_value_p->option_value; - } else if (!strcmp(ext_value_p->option_name, "copy_tocpu_en")) { - val_ptr[19] = (char*)ext_value_p->option_value; - } else if (!strcmp(ext_value_p->option_name, "syntoggle")) { - val_ptr[20] = (char*)ext_value_p->option_value; - } else if (!strcmp(ext_value_p->option_name, "priprofile")) { - val_ptr[21] = (char*)ext_value_p->option_value; - } else if (!strcmp(ext_value_p->option_name, "sevicecode")) { - val_ptr[22] = (char*)ext_value_p->option_value; - } else if (!strcmp(ext_value_p->option_name, "iptype")) { - val_ptr[23] = (char*)ext_value_p->option_value; - } else if (!strcmp(ext_value_p->option_name, "ip4addr")) { - val_ptr[26] = (char*)ext_value_p->option_value; - } else if (!strcmp(ext_value_p->option_name, "srcport")) { - val_ptr[24] = (char*)ext_value_p->option_value; - } else if (!strcmp(ext_value_p->option_name, "dstport")) { - val_ptr[25] = (char*)ext_value_p->option_value; - } else if (!strcmp(ext_value_p->option_name, "tree_id")) { - val_ptr[27] = (char*)ext_value_p->option_value; - } else { - rv = -1; - break; - } - - parameter_length++; - switch_ext_p = switch_ext_p->next; - } - - return rv; -} - -static int -parse_flow_status(struct switch_val *val) -{ - struct switch_ext *switch_ext_p, *ext_value_p; - int rv = 0; - - switch_ext_p = val->value.ext_val; - while (switch_ext_p) { - ext_value_p = switch_ext_p; - - if (!strcmp(ext_value_p->option_name, "name")) { - switch_ext_p = switch_ext_p->next; - continue; - } else if (!strcmp(ext_value_p->option_name, "status")) { - val_ptr[0] = (char*)ext_value_p->option_value; - } else { - rv = -1; - break; - } - - parameter_length++; - switch_ext_p = switch_ext_p->next; - } - - return rv; -} - -static int -parse_flow_age(struct switch_val *val) -{ - struct switch_ext *switch_ext_p, *ext_value_p; - int rv = 0; - - switch_ext_p = val->value.ext_val; - while (switch_ext_p) { - ext_value_p = switch_ext_p; - - if (!strcmp(ext_value_p->option_name, "name")) { - switch_ext_p = switch_ext_p->next; - continue; - } else if (!strcmp(ext_value_p->option_name, "agetime")) { - val_ptr[0] = (char*)ext_value_p->option_value; - } else if (!strcmp(ext_value_p->option_name, "ageunit")) { - val_ptr[1] = (char*)ext_value_p->option_value; - } else { - rv = -1; - break; - } - - parameter_length++; - switch_ext_p = switch_ext_p->next; - } - - return rv; -} - -static int -parse_flow_mgmt(struct switch_val *val) -{ - struct switch_ext *switch_ext_p, *ext_value_p; - int rv = 0; - - switch_ext_p = val->value.ext_val; - while (switch_ext_p) { - ext_value_p = switch_ext_p; - - if (!strcmp(ext_value_p->option_name, "name")) { - switch_ext_p = switch_ext_p->next; - continue; - } else if (!strcmp(ext_value_p->option_name, "flowtype")) { - val_ptr[0] = (char*)ext_value_p->option_value; - } else if (!strcmp(ext_value_p->option_name, "flowdirection")) { - val_ptr[1] = (char*)ext_value_p->option_value; - } else if (!strcmp(ext_value_p->option_name, "flow_miss_action")) { - val_ptr[2] = (char*)ext_value_p->option_value; - } else if (!strcmp(ext_value_p->option_name, "frag_bypass_en")) { - val_ptr[3] = (char*)ext_value_p->option_value; - } else if (!strcmp(ext_value_p->option_name, "tcp_specific_bypass_en")) { - val_ptr[4] = (char*)ext_value_p->option_value; - } else if (!strcmp(ext_value_p->option_name, "all_bypass_en")) { - val_ptr[5] = (char*)ext_value_p->option_value; - } else if (!strcmp(ext_value_p->option_name, "keysel")) { - val_ptr[6] = (char*)ext_value_p->option_value; - } else { - rv = -1; - break; - } - - parameter_length++; - switch_ext_p = switch_ext_p->next; - } - - return rv; -} - -static int -parse_flow_host(struct switch_val *val) -{ - struct switch_ext *switch_ext_p, *ext_value_p; - int rv = 0; - - switch_ext_p = val->value.ext_val; - while (switch_ext_p) { - ext_value_p = switch_ext_p; - - if (!strcmp(ext_value_p->option_name, "name")) { - switch_ext_p = switch_ext_p->next; - continue; - } else if (!strcmp(ext_value_p->option_name, "add_mode")) { - val_ptr[0] = (char*)ext_value_p->option_value; - } else if (!strcmp(ext_value_p->option_name, "entry_id")) { - val_ptr[1] = (char*)ext_value_p->option_value; - } else if (!strcmp(ext_value_p->option_name, "entrytype")) { - val_ptr[2] = (char*)ext_value_p->option_value; - } else if (!strcmp(ext_value_p->option_name, "host_addr_type")) { - val_ptr[3] = (char*)ext_value_p->option_value; - } else if (!strcmp(ext_value_p->option_name, "host_addr_index")) { - val_ptr[4] = (char*)ext_value_p->option_value; - } else if (!strcmp(ext_value_p->option_name, "protocol")) { - val_ptr[5] = (char*)ext_value_p->option_value; - } else if (!strcmp(ext_value_p->option_name, "age")) { - val_ptr[6] = (char*)ext_value_p->option_value; - } else if (!strcmp(ext_value_p->option_name, "srcintf_valid")) { - val_ptr[7] = (char*)ext_value_p->option_value; - } else if (!strcmp(ext_value_p->option_name, "srcintf_index")) { - val_ptr[8] = (char*)ext_value_p->option_value; - } else if (!strcmp(ext_value_p->option_name, "fwdtype")) { - val_ptr[9] = (char*)ext_value_p->option_value; - } else if (!strcmp(ext_value_p->option_name, "snat_nexthop")) { - val_ptr[10] = (char*)ext_value_p->option_value; - } else if (!strcmp(ext_value_p->option_name, "snat_srcport")) { - val_ptr[11] = (char*)ext_value_p->option_value; - } else if (!strcmp(ext_value_p->option_name, "dnat_nexthop")) { - val_ptr[12] = (char*)ext_value_p->option_value; - } else if (!strcmp(ext_value_p->option_name, "dnat_dstport")) { - val_ptr[13] = (char*)ext_value_p->option_value; - } else if (!strcmp(ext_value_p->option_name, "route_nexthop")) { - val_ptr[14] = (char*)ext_value_p->option_value; - } else if (!strcmp(ext_value_p->option_name, "portvalid")) { - val_ptr[15] = (char*)ext_value_p->option_value; - } else if (!strcmp(ext_value_p->option_name, "routeport")) { - val_ptr[16] = (char*)ext_value_p->option_value; - } else if (!strcmp(ext_value_p->option_name, "bridgeport")) { - val_ptr[17] = (char*)ext_value_p->option_value; - } else if (!strcmp(ext_value_p->option_name, "deacclr_en")) { - val_ptr[18] = (char*)ext_value_p->option_value; - } else if (!strcmp(ext_value_p->option_name, "copy_tocpu_en")) { - val_ptr[19] = (char*)ext_value_p->option_value; - } else if (!strcmp(ext_value_p->option_name, "syntoggle")) { - val_ptr[20] = (char*)ext_value_p->option_value; - } else if (!strcmp(ext_value_p->option_name, "priprofile")) { - val_ptr[21] = (char*)ext_value_p->option_value; - } else if (!strcmp(ext_value_p->option_name, "sevicecode")) { - val_ptr[22] = (char*)ext_value_p->option_value; - } else if (!strcmp(ext_value_p->option_name, "iptype")) { - val_ptr[23] = (char*)ext_value_p->option_value; - } else if (!strcmp(ext_value_p->option_name, "ip4addr")) { - val_ptr[26] = (char*)ext_value_p->option_value; - } else if (!strcmp(ext_value_p->option_name, "srcport")) { - val_ptr[24] = (char*)ext_value_p->option_value; - } else if (!strcmp(ext_value_p->option_name, "dstport")) { - val_ptr[25] = (char*)ext_value_p->option_value; - } else if (!strcmp(ext_value_p->option_name, "tree_id")) { - val_ptr[27] = (char*)ext_value_p->option_value; - } else if (!strcmp(ext_value_p->option_name, "ipentry_id")) { - val_ptr[28] = (char*)ext_value_p->option_value; - } else if (!strcmp(ext_value_p->option_name, "entry_flags")) { - val_ptr[29] = (char*)ext_value_p->option_value; - } else if (!strcmp(ext_value_p->option_name, "entry_status")) { - val_ptr[30] = (char*)ext_value_p->option_value; - } else if (!strcmp(ext_value_p->option_name, "ip_addr")) { - val_ptr[31] = (char*)ext_value_p->option_value; - } else if (!strcmp(ext_value_p->option_name, "mac_addr")) { - val_ptr[32] = (char*)ext_value_p->option_value; - } else if (!strcmp(ext_value_p->option_name, "interface_id")) { - val_ptr[33] = (char*)ext_value_p->option_value; - } else if (!strcmp(ext_value_p->option_name, "load_balance_num")) { - val_ptr[34] = (char*)ext_value_p->option_value; - } else if (!strcmp(ext_value_p->option_name, "vrf_id")) { - val_ptr[35] = (char*)ext_value_p->option_value; - } else if (!strcmp(ext_value_p->option_name, "port_id")) { - val_ptr[36] = (char*)ext_value_p->option_value; - } else if (!strcmp(ext_value_p->option_name, "action")) { - val_ptr[37] = (char*)ext_value_p->option_value; - } else if (!strcmp(ext_value_p->option_name, "mirror")) { - val_ptr[38] = (char*)ext_value_p->option_value; - } else if (!strcmp(ext_value_p->option_name, "counter")) { - val_ptr[39] = (char*)ext_value_p->option_value; - } else if (!strcmp(ext_value_p->option_name, "destinfo")) { - val_ptr[40] = (char*)ext_value_p->option_value; - } else if (!strcmp(ext_value_p->option_name, "ip_synctoggle")) { - val_ptr[41] = (char*)ext_value_p->option_value; - } else if (!strcmp(ext_value_p->option_name, "lan_wan")) { - val_ptr[42] = (char*)ext_value_p->option_value; - } else { - rv = -1; - break; - } - - parameter_length++; - switch_ext_p = switch_ext_p->next; - } - - return rv; -} - -static int -parse_flow_global(struct switch_val *val) -{ - struct switch_ext *switch_ext_p, *ext_value_p; - int rv = 0; - - switch_ext_p = val->value.ext_val; - while (switch_ext_p) { - ext_value_p = switch_ext_p; - - if (!strcmp(ext_value_p->option_name, "name")) { - switch_ext_p = switch_ext_p->next; - continue; - } else if (!strcmp(ext_value_p->option_name, "srcif_check_action")) { - val_ptr[0] = (char*)ext_value_p->option_value; - } else if (!strcmp(ext_value_p->option_name, "srcif_check_deacclr_en")) { - val_ptr[1] = (char*)ext_value_p->option_value; - } else if (!strcmp(ext_value_p->option_name, "service_loop_en")) { - val_ptr[2] = (char*)ext_value_p->option_value; - } else if (!strcmp(ext_value_p->option_name, "service_loop_action")) { - val_ptr[3] = (char*)ext_value_p->option_value; - } else if (!strcmp(ext_value_p->option_name, "service_loop_deacclr_en")) { - val_ptr[4] = (char*)ext_value_p->option_value; - } else if (!strcmp(ext_value_p->option_name, "flow_deacclr_action")) { - val_ptr[5] = (char*)ext_value_p->option_value; - } else if (!strcmp(ext_value_p->option_name, "sync_mismatch_action")) { - val_ptr[6] = (char*)ext_value_p->option_value; - } else if (!strcmp(ext_value_p->option_name, "sync_mismatch_deacclr_en")) { - val_ptr[7] = (char*)ext_value_p->option_value; - } else if (!strcmp(ext_value_p->option_name, "hash_mode_0")) { - val_ptr[8] = (char*)ext_value_p->option_value; - } else if (!strcmp(ext_value_p->option_name, "hash_mode_1")) { - val_ptr[9] = (char*)ext_value_p->option_value; - } else { - rv = -1; - break; - } - - parameter_length++; - switch_ext_p = switch_ext_p->next; - } - - return rv; -} -#endif - -#ifdef IN_BM -static int -parse_bm_ctrl(struct switch_val *val) -{ - struct switch_ext *switch_ext_p, *ext_value_p; - int rv = 0; - - switch_ext_p = val->value.ext_val; - while (switch_ext_p) { - ext_value_p = switch_ext_p; - - if (!strcmp(ext_value_p->option_name, "name")) { - switch_ext_p = switch_ext_p->next; - continue; - } else if (!strcmp(ext_value_p->option_name, "port_id")) { - val_ptr[0] = (char*)ext_value_p->option_value; - } else if (!strcmp(ext_value_p->option_name, "enable")) { - val_ptr[1] = (char*)ext_value_p->option_value; - } else { - rv = -1; - break; - } - - parameter_length++; - switch_ext_p = switch_ext_p->next; - } - - return rv; -} - -static int -parse_bm_portgroupmap(struct switch_val *val) -{ - struct switch_ext *switch_ext_p, *ext_value_p; - int rv = 0; - - switch_ext_p = val->value.ext_val; - while (switch_ext_p) { - ext_value_p = switch_ext_p; - - if (!strcmp(ext_value_p->option_name, "name")) { - switch_ext_p = switch_ext_p->next; - continue; - } else if (!strcmp(ext_value_p->option_name, "port_id")) { - val_ptr[0] = (char*)ext_value_p->option_value; - } else if (!strcmp(ext_value_p->option_name, "group_id")) { - val_ptr[1] = (char*)ext_value_p->option_value; - } else { - rv = -1; - break; - } - - parameter_length++; - switch_ext_p = switch_ext_p->next; - } - - return rv; -} - -static int -parse_bm_groupbuff(struct switch_val *val) -{ - struct switch_ext *switch_ext_p, *ext_value_p; - int rv = 0; - - switch_ext_p = val->value.ext_val; - while (switch_ext_p) { - ext_value_p = switch_ext_p; - - if (!strcmp(ext_value_p->option_name, "name")) { - switch_ext_p = switch_ext_p->next; - continue; - } else if (!strcmp(ext_value_p->option_name, "group_id")) { - val_ptr[0] = (char*)ext_value_p->option_value; - } else if (!strcmp(ext_value_p->option_name, "bufnum")) { - val_ptr[1] = (char*)ext_value_p->option_value; - } else { - rv = -1; - break; - } - - parameter_length++; - switch_ext_p = switch_ext_p->next; - } - - return rv; -} - -static int -parse_bm_portrsvbuff(struct switch_val *val) -{ - struct switch_ext *switch_ext_p, *ext_value_p; - int rv = 0; - - switch_ext_p = val->value.ext_val; - while (switch_ext_p) { - ext_value_p = switch_ext_p; - - if (!strcmp(ext_value_p->option_name, "name")) { - switch_ext_p = switch_ext_p->next; - continue; - } else if (!strcmp(ext_value_p->option_name, "port_id")) { - val_ptr[0] = (char*)ext_value_p->option_value; - } else if (!strcmp(ext_value_p->option_name, "prealloc_bufnum")) { - val_ptr[1] = (char*)ext_value_p->option_value; - } else if (!strcmp(ext_value_p->option_name, "react_bufnum")) { - val_ptr[2] = (char*)ext_value_p->option_value; - } else { - rv = -1; - break; - } - - parameter_length++; - switch_ext_p = switch_ext_p->next; - } - - return rv; -} - -static int -parse_bm_portsthresh(struct switch_val *val) -{ - struct switch_ext *switch_ext_p, *ext_value_p; - int rv = 0; - - switch_ext_p = val->value.ext_val; - while (switch_ext_p) { - ext_value_p = switch_ext_p; - - if (!strcmp(ext_value_p->option_name, "name")) { - switch_ext_p = switch_ext_p->next; - continue; - } else if (!strcmp(ext_value_p->option_name, "port_id")) { - val_ptr[0] = (char*)ext_value_p->option_value; - } else if (!strcmp(ext_value_p->option_name, "maxthreshold")) { - val_ptr[1] = (char*)ext_value_p->option_value; - } else if (!strcmp(ext_value_p->option_name, "resume_offset")) { - val_ptr[2] = (char*)ext_value_p->option_value; - } else { - rv = -1; - break; - } - - parameter_length++; - switch_ext_p = switch_ext_p->next; - } - - return rv; -} - -static int -parse_bm_portdthresh(struct switch_val *val) -{ - struct switch_ext *switch_ext_p, *ext_value_p; - int rv = 0; - - switch_ext_p = val->value.ext_val; - while (switch_ext_p) { - ext_value_p = switch_ext_p; - - if (!strcmp(ext_value_p->option_name, "name")) { - switch_ext_p = switch_ext_p->next; - continue; - } else if (!strcmp(ext_value_p->option_name, "port_id")) { - val_ptr[0] = (char*)ext_value_p->option_value; - } else if (!strcmp(ext_value_p->option_name, "weight")) { - val_ptr[1] = (char*)ext_value_p->option_value; - } else if (!strcmp(ext_value_p->option_name, "sharedceiling")) { - val_ptr[2] = (char*)ext_value_p->option_value; - } else if (!strcmp(ext_value_p->option_name, "resumeoffset")) { - val_ptr[3] = (char*)ext_value_p->option_value; - } else if (!strcmp(ext_value_p->option_name, "resume_min_threshold")) { - val_ptr[4] = (char*)ext_value_p->option_value; - } else { - rv = -1; - break; - } - - parameter_length++; - switch_ext_p = switch_ext_p->next; - } - - return rv; -} - -#endif - -#ifdef IN_QM -static int -parse_qm_ucastqbase(struct switch_val *val) -{ - struct switch_ext *switch_ext_p, *ext_value_p; - int rv = 0; - - switch_ext_p = val->value.ext_val; - while (switch_ext_p) { - ext_value_p = switch_ext_p; - - if (!strcmp(ext_value_p->option_name, "name")) { - switch_ext_p = switch_ext_p->next; - continue; - } else if (!strcmp(ext_value_p->option_name, "srcprofile")) { - val_ptr[0] = (char*)ext_value_p->option_value; - } else if (!strcmp(ext_value_p->option_name, "servicecode_en")) { - val_ptr[1] = (char*)ext_value_p->option_value; - } else if (!strcmp(ext_value_p->option_name, "servicecode")) { - val_ptr[2] = (char*)ext_value_p->option_value; - } else if (!strcmp(ext_value_p->option_name, "cpucode_en")) { - val_ptr[3] = (char*)ext_value_p->option_value; - } else if (!strcmp(ext_value_p->option_name, "cpucode")) { - val_ptr[4] = (char*)ext_value_p->option_value; - } else if (!strcmp(ext_value_p->option_name, "destport")) { - val_ptr[5] = (char*)ext_value_p->option_value; - } else if (!strcmp(ext_value_p->option_name, "queuebase")) { - val_ptr[6] = (char*)ext_value_p->option_value; - } else if (!strcmp(ext_value_p->option_name, "profile")) { - val_ptr[7] = (char*)ext_value_p->option_value; - } else { - rv = -1; - break; - } - - parameter_length++; - switch_ext_p = switch_ext_p->next; - } - - return rv; -} - -static int -parse_qm_ucastpriclass(struct switch_val *val) -{ - struct switch_ext *switch_ext_p, *ext_value_p; - int rv = 0; - - switch_ext_p = val->value.ext_val; - while (switch_ext_p) { - ext_value_p = switch_ext_p; - - if (!strcmp(ext_value_p->option_name, "name")) { - switch_ext_p = switch_ext_p->next; - continue; - } else if (!strcmp(ext_value_p->option_name, "profile")) { - val_ptr[0] = (char*)ext_value_p->option_value; - } else if (!strcmp(ext_value_p->option_name, "priority")) { - val_ptr[1] = (char*)ext_value_p->option_value; - } else if (!strcmp(ext_value_p->option_name, "class")) { - val_ptr[2] = (char*)ext_value_p->option_value; - } else { - rv = -1; - break; - } - - parameter_length++; - switch_ext_p = switch_ext_p->next; - } - - return rv; -} - -static int -parse_qm_mcastpriclass(struct switch_val *val) -{ - struct switch_ext *switch_ext_p, *ext_value_p; - int rv = 0; - - switch_ext_p = val->value.ext_val; - while (switch_ext_p) { - ext_value_p = switch_ext_p; - - if (!strcmp(ext_value_p->option_name, "name")) { - switch_ext_p = switch_ext_p->next; - continue; - } else if (!strcmp(ext_value_p->option_name, "port_id")) { - val_ptr[0] = (char*)ext_value_p->option_value; - } else if (!strcmp(ext_value_p->option_name, "priority")) { - val_ptr[1] = (char*)ext_value_p->option_value; - } else if (!strcmp(ext_value_p->option_name, "class")) { - val_ptr[2] = (char*)ext_value_p->option_value; - } else { - rv = -1; - break; - } - - parameter_length++; - switch_ext_p = switch_ext_p->next; - } - - return rv; -} - -static int -parse_qm_queue(struct switch_val *val) -{ - struct switch_ext *switch_ext_p, *ext_value_p; - int rv = 0; - - switch_ext_p = val->value.ext_val; - while (switch_ext_p) { - ext_value_p = switch_ext_p; - - if (!strcmp(ext_value_p->option_name, "name")) { - switch_ext_p = switch_ext_p->next; - continue; - } else if (!strcmp(ext_value_p->option_name, "port_id")) { - val_ptr[0] = (char*)ext_value_p->option_value; - } else if (!strcmp(ext_value_p->option_name, "queue_id")) { - val_ptr[1] = (char*)ext_value_p->option_value; - } else { - rv = -1; - break; - } - - parameter_length++; - switch_ext_p = switch_ext_p->next; - } - - return rv; -} - -static int -parse_qm_ucasthash(struct switch_val *val) -{ - struct switch_ext *switch_ext_p, *ext_value_p; - int rv = 0; - - switch_ext_p = val->value.ext_val; - while (switch_ext_p) { - ext_value_p = switch_ext_p; - - if (!strcmp(ext_value_p->option_name, "name")) { - switch_ext_p = switch_ext_p->next; - continue; - } else if (!strcmp(ext_value_p->option_name, "profile")) { - val_ptr[0] = (char*)ext_value_p->option_value; - } else if (!strcmp(ext_value_p->option_name, "rsshash")) { - val_ptr[1] = (char*)ext_value_p->option_value; - } else if (!strcmp(ext_value_p->option_name, "queuehash")) { - val_ptr[2] = (char*)ext_value_p->option_value; - } else { - rv = -1; - break; - } - - parameter_length++; - switch_ext_p = switch_ext_p->next; - } - - return rv; -} - -static int -parse_qm_ucastdflthash(struct switch_val *val) -{ - struct switch_ext *switch_ext_p, *ext_value_p; - int rv = 0; - - switch_ext_p = val->value.ext_val; - while (switch_ext_p) { - ext_value_p = switch_ext_p; - - if (!strcmp(ext_value_p->option_name, "name")) { - switch_ext_p = switch_ext_p->next; - continue; - } else if (!strcmp(ext_value_p->option_name, "queuevalue")) { - val_ptr[0] = (char*)ext_value_p->option_value; - } else { - rv = -1; - break; - } - - parameter_length++; - switch_ext_p = switch_ext_p->next; - } - - return rv; -} - -static int -parse_qm_mcastcpucode(struct switch_val *val) -{ - struct switch_ext *switch_ext_p, *ext_value_p; - int rv = 0; - - switch_ext_p = val->value.ext_val; - while (switch_ext_p) { - ext_value_p = switch_ext_p; - - if (!strcmp(ext_value_p->option_name, "name")) { - switch_ext_p = switch_ext_p->next; - continue; - } else if (!strcmp(ext_value_p->option_name, "cpucode")) { - val_ptr[0] = (char*)ext_value_p->option_value; - } else if (!strcmp(ext_value_p->option_name, "class")) { - val_ptr[1] = (char*)ext_value_p->option_value; - } else { - rv = -1; - break; - } - - parameter_length++; - switch_ext_p = switch_ext_p->next; - } - - return rv; -} - -static int -parse_qm_acctrl(struct switch_val *val) -{ - struct switch_ext *switch_ext_p, *ext_value_p; - int rv = 0; - - switch_ext_p = val->value.ext_val; - while (switch_ext_p) { - ext_value_p = switch_ext_p; - - if (!strcmp(ext_value_p->option_name, "name")) { - switch_ext_p = switch_ext_p->next; - continue; - } else if (!strcmp(ext_value_p->option_name, "type")) { - val_ptr[0] = (char*)ext_value_p->option_value; - } else if (!strcmp(ext_value_p->option_name, "obj_id")) { - val_ptr[1] = (char*)ext_value_p->option_value; - } else if (!strcmp(ext_value_p->option_name, "admis_ctrl_en")) { - val_ptr[2] = (char*)ext_value_p->option_value; - } else if (!strcmp(ext_value_p->option_name, "admis_flowctrl_en")) { - val_ptr[3] = (char*)ext_value_p->option_value; - } else { - rv = -1; - break; - } - - parameter_length++; - switch_ext_p = switch_ext_p->next; - } - - return rv; -} - -static int -parse_qm_acprebuffer(struct switch_val *val) -{ - struct switch_ext *switch_ext_p, *ext_value_p; - int rv = 0; - - switch_ext_p = val->value.ext_val; - while (switch_ext_p) { - ext_value_p = switch_ext_p; - - if (!strcmp(ext_value_p->option_name, "name")) { - switch_ext_p = switch_ext_p->next; - continue; - } else if (!strcmp(ext_value_p->option_name, "type")) { - val_ptr[0] = (char*)ext_value_p->option_value; - } else if (!strcmp(ext_value_p->option_name, "obj_id")) { - val_ptr[1] = (char*)ext_value_p->option_value; - } else if (!strcmp(ext_value_p->option_name, "bufnum")) { - val_ptr[2] = (char*)ext_value_p->option_value; - } else { - rv = -1; - break; - } - - parameter_length++; - switch_ext_p = switch_ext_p->next; - } - - return rv; -} - -static int -parse_qm_acqgroup(struct switch_val *val) -{ - struct switch_ext *switch_ext_p, *ext_value_p; - int rv = 0; - - switch_ext_p = val->value.ext_val; - while (switch_ext_p) { - ext_value_p = switch_ext_p; - - if (!strcmp(ext_value_p->option_name, "name")) { - switch_ext_p = switch_ext_p->next; - continue; - } else if (!strcmp(ext_value_p->option_name, "queue_id")) { - val_ptr[0] = (char*)ext_value_p->option_value; - } else if (!strcmp(ext_value_p->option_name, "group_id")) { - val_ptr[1] = (char*)ext_value_p->option_value; - } else { - rv = -1; - break; - } - - parameter_length++; - switch_ext_p = switch_ext_p->next; - } - - return rv; -} - -static int -parse_qm_acsthresh(struct switch_val *val) -{ - struct switch_ext *switch_ext_p, *ext_value_p; - int rv = 0; - - switch_ext_p = val->value.ext_val; - while (switch_ext_p) { - ext_value_p = switch_ext_p; - - if (!strcmp(ext_value_p->option_name, "name")) { - switch_ext_p = switch_ext_p->next; - continue; - } else if (!strcmp(ext_value_p->option_name, "type")) { - val_ptr[0] = (char*)ext_value_p->option_value; - } else if (!strcmp(ext_value_p->option_name, "obj_id")) { - val_ptr[1] = (char*)ext_value_p->option_value; - } else if (!strcmp(ext_value_p->option_name, "color_en")) { - val_ptr[2] = (char*)ext_value_p->option_value; - } else if (!strcmp(ext_value_p->option_name, "wred_en")) { - val_ptr[3] = (char*)ext_value_p->option_value; - } else if (!strcmp(ext_value_p->option_name, "greenmax")) { - val_ptr[4] = (char*)ext_value_p->option_value; - } else if (!strcmp(ext_value_p->option_name, "green_min_offset")) { - val_ptr[5] = (char*)ext_value_p->option_value; - } else if (!strcmp(ext_value_p->option_name, "yel_max_offset")) { - val_ptr[6] = (char*)ext_value_p->option_value; - } else if (!strcmp(ext_value_p->option_name, "yel_min_offset")) { - val_ptr[7] = (char*)ext_value_p->option_value; - } else if (!strcmp(ext_value_p->option_name, "red_max_offset")) { - val_ptr[8] = (char*)ext_value_p->option_value; - } else if (!strcmp(ext_value_p->option_name, "red_min_offset")) { - val_ptr[9] = (char*)ext_value_p->option_value; - } else if (!strcmp(ext_value_p->option_name, "green_resume_offset")) { - val_ptr[10] = (char*)ext_value_p->option_value; - } else if (!strcmp(ext_value_p->option_name, "yel_resume_offset")) { - val_ptr[11] = (char*)ext_value_p->option_value; - } else if (!strcmp(ext_value_p->option_name, "red_resume_offset")) { - val_ptr[12] = (char*)ext_value_p->option_value; - } else { - rv = -1; - break; - } - - parameter_length++; - switch_ext_p = switch_ext_p->next; - } - - return rv; -} - -static int -parse_qm_acdthresh(struct switch_val *val) -{ - struct switch_ext *switch_ext_p, *ext_value_p; - int rv = 0; - - switch_ext_p = val->value.ext_val; - while (switch_ext_p) { - ext_value_p = switch_ext_p; - - if (!strcmp(ext_value_p->option_name, "name")) { - switch_ext_p = switch_ext_p->next; - continue; - } else if (!strcmp(ext_value_p->option_name, "queue_id")) { - val_ptr[0] = (char*)ext_value_p->option_value; - } else if (!strcmp(ext_value_p->option_name, "color_en")) { - val_ptr[1] = (char*)ext_value_p->option_value; - } else if (!strcmp(ext_value_p->option_name, "wred_en")) { - val_ptr[2] = (char*)ext_value_p->option_value; - } else if (!strcmp(ext_value_p->option_name, "sharedweight")) { - val_ptr[3] = (char*)ext_value_p->option_value; - } else if (!strcmp(ext_value_p->option_name, "green_min_offset")) { - val_ptr[4] = (char*)ext_value_p->option_value; - } else if (!strcmp(ext_value_p->option_name, "yel_max_offset")) { - val_ptr[5] = (char*)ext_value_p->option_value; - } else if (!strcmp(ext_value_p->option_name, "yel_min_offset")) { - val_ptr[6] = (char*)ext_value_p->option_value; - } else if (!strcmp(ext_value_p->option_name, "red_max_offset")) { - val_ptr[7] = (char*)ext_value_p->option_value; - } else if (!strcmp(ext_value_p->option_name, "red_min_offset")) { - val_ptr[8] = (char*)ext_value_p->option_value; - } else if (!strcmp(ext_value_p->option_name, "green_resume_off")) { - val_ptr[9] = (char*)ext_value_p->option_value; - } else if (!strcmp(ext_value_p->option_name, "yel_resume_offset")) { - val_ptr[10] = (char*)ext_value_p->option_value; - } else if (!strcmp(ext_value_p->option_name, "red_resume_offset")) { - val_ptr[11] = (char*)ext_value_p->option_value; - } else if (!strcmp(ext_value_p->option_name, "ceiling")) { - val_ptr[12] = (char*)ext_value_p->option_value; - } else { - rv = -1; - break; - } - - parameter_length++; - switch_ext_p = switch_ext_p->next; - } - - return rv; -} - -static int -parse_qm_acgbuff(struct switch_val *val) -{ - struct switch_ext *switch_ext_p, *ext_value_p; - int rv = 0; - - switch_ext_p = val->value.ext_val; - while (switch_ext_p) { - ext_value_p = switch_ext_p; - - if (!strcmp(ext_value_p->option_name, "name")) { - switch_ext_p = switch_ext_p->next; - continue; - } else if (!strcmp(ext_value_p->option_name, "group_id")) { - val_ptr[0] = (char*)ext_value_p->option_value; - } else if (!strcmp(ext_value_p->option_name, "prealloc_bufnum")) { - val_ptr[1] = (char*)ext_value_p->option_value; - } else if (!strcmp(ext_value_p->option_name, "total_bufnum")) { - val_ptr[2] = (char*)ext_value_p->option_value; - } else { - rv = -1; - break; - } - - parameter_length++; - switch_ext_p = switch_ext_p->next; - } - - return rv; -} - -static int -parse_qm_cntctrl(struct switch_val *val) -{ - struct switch_ext *switch_ext_p, *ext_value_p; - int rv = 0; - - switch_ext_p = val->value.ext_val; - while (switch_ext_p) { - ext_value_p = switch_ext_p; - - if (!strcmp(ext_value_p->option_name, "name")) { - switch_ext_p = switch_ext_p->next; - continue; - } else if (!strcmp(ext_value_p->option_name, "cnt_en")) { - val_ptr[0] = (char*)ext_value_p->option_value; - } else { - rv = -1; - break; - } - - parameter_length++; - switch_ext_p = switch_ext_p->next; - } - - return rv; -} - -static int -parse_qm_cnt(struct switch_val *val) -{ - struct switch_ext *switch_ext_p, *ext_value_p; - int rv = 0; - - switch_ext_p = val->value.ext_val; - while (switch_ext_p) { - ext_value_p = switch_ext_p; - - if (!strcmp(ext_value_p->option_name, "name")) { - switch_ext_p = switch_ext_p->next; - continue; - } else if (!strcmp(ext_value_p->option_name, "queue_id")) { - val_ptr[0] = (char*)ext_value_p->option_value; - } else { - rv = -1; - break; - } - - parameter_length++; - switch_ext_p = switch_ext_p->next; - } - - return rv; -} - -static int -parse_qm_enqueue(struct switch_val *val) -{ - struct switch_ext *switch_ext_p, *ext_value_p; - int rv = 0; - - switch_ext_p = val->value.ext_val; - while (switch_ext_p) { - ext_value_p = switch_ext_p; - - if (!strcmp(ext_value_p->option_name, "name")) { - switch_ext_p = switch_ext_p->next; - continue; - } else if (!strcmp(ext_value_p->option_name, "queue_id")) { - val_ptr[0] = (char*)ext_value_p->option_value; - } else if (!strcmp(ext_value_p->option_name, "enqueue_en")) { - val_ptr[1] = (char*)ext_value_p->option_value; - } else { - rv = -1; - break; - } - - parameter_length++; - switch_ext_p = switch_ext_p->next; - } - - return rv; -} - -static int -parse_qm_srcprofile(struct switch_val *val) -{ - struct switch_ext *switch_ext_p, *ext_value_p; - int rv = 0; - - switch_ext_p = val->value.ext_val; - while (switch_ext_p) { - ext_value_p = switch_ext_p; - - if (!strcmp(ext_value_p->option_name, "name")) { - switch_ext_p = switch_ext_p->next; - continue; - } else if (!strcmp(ext_value_p->option_name, "port_id")) { - val_ptr[0] = (char*)ext_value_p->option_value; - } else if (!strcmp(ext_value_p->option_name, "sourceprofile")) { - val_ptr[1] = (char*)ext_value_p->option_value; - } else { - rv = -1; - break; - } - - parameter_length++; - switch_ext_p = switch_ext_p->next; - } - - return rv; -} - -#endif - -#ifdef IN_SERVCODE -static int -parse_servcode_config(struct switch_val *val) -{ - struct switch_ext *switch_ext_p, *ext_value_p; - int rv = 0; - - switch_ext_p = val->value.ext_val; - while (switch_ext_p) { - ext_value_p = switch_ext_p; - - if (!strcmp(ext_value_p->option_name, "name")) { - switch_ext_p = switch_ext_p->next; - continue; - } else if (!strcmp(ext_value_p->option_name, "servcode_id")) { - val_ptr[0] = (char*)ext_value_p->option_value; - } else if (!strcmp(ext_value_p->option_name, "destport_en")) { - val_ptr[1] = (char*)ext_value_p->option_value; - } else if (!strcmp(ext_value_p->option_name, "destport_id")) { - val_ptr[2] = (char*)ext_value_p->option_value; - } else if (!strcmp(ext_value_p->option_name, "bypass_bitmap_0")) { - val_ptr[3] = (char*)ext_value_p->option_value; - } else if (!strcmp(ext_value_p->option_name, "bypass_bitmap_1")) { - val_ptr[4] = (char*)ext_value_p->option_value; - } else if (!strcmp(ext_value_p->option_name, "bypass_bitmap_2")) { - val_ptr[5] = (char*)ext_value_p->option_value; - } else if (!strcmp(ext_value_p->option_name, "direction")) { - val_ptr[6] = (char*)ext_value_p->option_value; - } else if (!strcmp(ext_value_p->option_name, "field_update_bitmap")) { - val_ptr[7] = (char*)ext_value_p->option_value; - } else if (!strcmp(ext_value_p->option_name, "next_servicecode")) { - val_ptr[8] = (char*)ext_value_p->option_value; - } else if (!strcmp(ext_value_p->option_name, "hardwareservices")) { - val_ptr[9] = (char*)ext_value_p->option_value; - } else if (!strcmp(ext_value_p->option_name, "offsetselection")) { - val_ptr[10] = (char*)ext_value_p->option_value; - } else { - rv = -1; - break; - } - - parameter_length++; - switch_ext_p = switch_ext_p->next; - } - - return rv; -} - -static int -parse_servcode_loopcheck(struct switch_val *val) -{ - struct switch_ext *switch_ext_p, *ext_value_p; - int rv = 0; - - switch_ext_p = val->value.ext_val; - while (switch_ext_p) { - ext_value_p = switch_ext_p; - - if (!strcmp(ext_value_p->option_name, "name")) { - switch_ext_p = switch_ext_p->next; - continue; - } else if (!strcmp(ext_value_p->option_name, "loopcheck_en")) { - val_ptr[0] = (char*)ext_value_p->option_value; - } else { - rv = -1; - break; - } - - parameter_length++; - switch_ext_p = switch_ext_p->next; - } - - return rv; -} -#endif - -#ifdef IN_CTRLPKT -static int -parse_ctrlpkt_ethernettype(struct switch_val *val) -{ - struct switch_ext *switch_ext_p, *ext_value_p; - int rv = 0; - - switch_ext_p = val->value.ext_val; - while (switch_ext_p) { - ext_value_p = switch_ext_p; - - if (!strcmp(ext_value_p->option_name, "name")) { - switch_ext_p = switch_ext_p->next; - continue; - } else if (!strcmp(ext_value_p->option_name, "profile_id")) { - val_ptr[0] = (char*)ext_value_p->option_value; - } else if (!strcmp(ext_value_p->option_name, "ethernettype")) { - val_ptr[1] = (char*)ext_value_p->option_value; - } else { - rv = -1; - break; - } - - parameter_length++; - switch_ext_p = switch_ext_p->next; - } - - return rv; -} - -static int -parse_ctrlpkt_rfdb(struct switch_val *val) -{ - struct switch_ext *switch_ext_p, *ext_value_p; - int rv = 0; - - switch_ext_p = val->value.ext_val; - while (switch_ext_p) { - ext_value_p = switch_ext_p; - - if (!strcmp(ext_value_p->option_name, "name")) { - switch_ext_p = switch_ext_p->next; - continue; - } else if (!strcmp(ext_value_p->option_name, "profile_id")) { - val_ptr[0] = (char*)ext_value_p->option_value; - } else if (!strcmp(ext_value_p->option_name, "rfdb_macaddr")) { - val_ptr[1] = (char*)ext_value_p->option_value; - } else { - rv = -1; - break; - } - - parameter_length++; - switch_ext_p = switch_ext_p->next; - } - - return rv; -} - -static int -parse_ctrlpkt_appprofile(struct switch_val *val) -{ - struct switch_ext *switch_ext_p, *ext_value_p; - int rv = 0; - - switch_ext_p = val->value.ext_val; - while (switch_ext_p) { - ext_value_p = switch_ext_p; - - if (!strcmp(ext_value_p->option_name, "name")) { - switch_ext_p = switch_ext_p->next; - continue; - } else if (!strcmp(ext_value_p->option_name, "port_bitmap")) { - val_ptr[0] = (char*)ext_value_p->option_value; - } else if (!strcmp(ext_value_p->option_name, "ethtype_profile_bitmap")) { - val_ptr[1] = (char*)ext_value_p->option_value; - } else if (!strcmp(ext_value_p->option_name, "rfdb_profile_bitmap")) { - val_ptr[2] = (char*)ext_value_p->option_value; - } else if (!strcmp(ext_value_p->option_name, "eapol_en")) { - val_ptr[3] = (char*)ext_value_p->option_value; - } else if (!strcmp(ext_value_p->option_name, "pppoe_en")) { - val_ptr[4] = (char*)ext_value_p->option_value; - } else if (!strcmp(ext_value_p->option_name, "igmp_en")) { - val_ptr[5] = (char*)ext_value_p->option_value; - } else if (!strcmp(ext_value_p->option_name, "arp_request_en")) { - val_ptr[6] = (char*)ext_value_p->option_value; - } else if (!strcmp(ext_value_p->option_name, "arp_reponse_en")) { - val_ptr[7] = (char*)ext_value_p->option_value; - } else if (!strcmp(ext_value_p->option_name, "dhcp4_en")) { - val_ptr[8] = (char*)ext_value_p->option_value; - } else if (!strcmp(ext_value_p->option_name, "dhcp6_en")) { - val_ptr[9] = (char*)ext_value_p->option_value; - } else if (!strcmp(ext_value_p->option_name, "mld_en")) { - val_ptr[10] = (char*)ext_value_p->option_value; - } else if (!strcmp(ext_value_p->option_name, "ip6ns_en")) { - val_ptr[11] = (char*)ext_value_p->option_value; - } else if (!strcmp(ext_value_p->option_name, "ip6na_en")) { - val_ptr[12] = (char*)ext_value_p->option_value; - } else if (!strcmp(ext_value_p->option_name, "ctrlpkt_profile_action")) { - val_ptr[13] = (char*)ext_value_p->option_value; - } else if (!strcmp(ext_value_p->option_name, "sourceguard_bypass")) { - val_ptr[14] = (char*)ext_value_p->option_value; - } else if (!strcmp(ext_value_p->option_name, "l2filter_bypass")) { - val_ptr[15] = (char*)ext_value_p->option_value; - } else if (!strcmp(ext_value_p->option_name, "ingress_stp_bypass")) { - val_ptr[16] = (char*)ext_value_p->option_value; - } else if (!strcmp(ext_value_p->option_name, "ingress_vlan_filter_bypass")) { - val_ptr[17] = (char*)ext_value_p->option_value; - } else { - rv = -1; - break; - } - - parameter_length++; - switch_ext_p = switch_ext_p->next; - } - - return rv; -} -#endif - -#ifdef IN_POLICER -static int -parse_policer_timeslot(struct switch_val *val) -{ - struct switch_ext *switch_ext_p, *ext_value_p; - int rv = 0; - switch_ext_p = val->value.ext_val; - while(switch_ext_p) { - ext_value_p = switch_ext_p; - - if(!strcmp(ext_value_p->option_name, "name")) { - switch_ext_p = switch_ext_p->next; - continue; - } else if(!strcmp(ext_value_p->option_name, "timeslot")) { - val_ptr[0] = (char*)ext_value_p->option_value; - } else { - rv = -1; - break; - } - - parameter_length++; - switch_ext_p = switch_ext_p->next; - } - - return rv; -} - -static int -parse_policer_fcscompensation(struct switch_val *val) -{ - struct switch_ext *switch_ext_p, *ext_value_p; - int rv = 0; - switch_ext_p = val->value.ext_val; - while(switch_ext_p) { - ext_value_p = switch_ext_p; - - if(!strcmp(ext_value_p->option_name, "name")) { - switch_ext_p = switch_ext_p->next; - continue; - } else if(!strcmp(ext_value_p->option_name, "port_id")) { - val_ptr[0] = (char*)ext_value_p->option_value; - } else if(!strcmp(ext_value_p->option_name, "fcscompensation_length")) { - val_ptr[1] = (char*)ext_value_p->option_value; - } else { - rv = -1; - break; - } - - parameter_length++; - switch_ext_p = switch_ext_p->next; - } - - return rv; -} - -static int -parse_policer_portentry(struct switch_val *val) -{ - struct switch_ext *switch_ext_p, *ext_value_p; - int rv = 0; - switch_ext_p = val->value.ext_val; - while(switch_ext_p) { - ext_value_p = switch_ext_p; - - if(!strcmp(ext_value_p->option_name, "name")) { - switch_ext_p = switch_ext_p->next; - continue; - } else if(!strcmp(ext_value_p->option_name, "port_id")) { - val_ptr[0] = (char*)ext_value_p->option_value; - } else if(!strcmp(ext_value_p->option_name, "policer_en")) { - val_ptr[1] = (char*)ext_value_p->option_value; - } else if(!strcmp(ext_value_p->option_name, "coupling_en")) { - val_ptr[2] = (char*)ext_value_p->option_value; - } else if(!strcmp(ext_value_p->option_name, "colormode")) { - val_ptr[3] = (char*)ext_value_p->option_value; - } else if(!strcmp(ext_value_p->option_name, "frametype")) { - val_ptr[4] = (char*)ext_value_p->option_value; - } else if(!strcmp(ext_value_p->option_name, "metermode")) { - val_ptr[5] = (char*)ext_value_p->option_value; - } else if(!strcmp(ext_value_p->option_name, "meterunit")) { - val_ptr[6] = (char*)ext_value_p->option_value; - } else if(!strcmp(ext_value_p->option_name, "cir")) { - val_ptr[7] = (char*)ext_value_p->option_value; - } else if(!strcmp(ext_value_p->option_name, "cbs")) { - val_ptr[8] = (char*)ext_value_p->option_value; - } else if(!strcmp(ext_value_p->option_name, "eir")) { - val_ptr[9] = (char*)ext_value_p->option_value; - } else if(!strcmp(ext_value_p->option_name, "ebs")) { - val_ptr[10] = (char*)ext_value_p->option_value; - } else if(!strcmp(ext_value_p->option_name, "yellow_priremark_en")) { - val_ptr[11] = (char*)ext_value_p->option_value; - } else if(!strcmp(ext_value_p->option_name, "yellow_dropprec_remark_en")) { - val_ptr[12] = (char*)ext_value_p->option_value; - } else if(!strcmp(ext_value_p->option_name, "yellow_pcpremark_en")) { - val_ptr[13] = (char*)ext_value_p->option_value; - } else if(!strcmp(ext_value_p->option_name, "yellow_deiremark_en")) { - val_ptr[14] = (char*)ext_value_p->option_value; - } else if(!strcmp(ext_value_p->option_name, "yellowpri")) { - val_ptr[15] = (char*)ext_value_p->option_value; - } else if(!strcmp(ext_value_p->option_name, "yellow_dropprec")) { - val_ptr[16] = (char*)ext_value_p->option_value; - } else if(!strcmp(ext_value_p->option_name, "yellowpcp")) { - val_ptr[17] = (char*)ext_value_p->option_value; - } else if(!strcmp(ext_value_p->option_name, "yellowdei")) { - val_ptr[18] = (char*)ext_value_p->option_value; - } else if(!strcmp(ext_value_p->option_name, "redaction")) { - val_ptr[19] = (char*)ext_value_p->option_value; - } else if(!strcmp(ext_value_p->option_name, "red_priremark_en")) { - val_ptr[20] = (char*)ext_value_p->option_value; - } else if(!strcmp(ext_value_p->option_name, "red_dropprec_remark_en")) { - val_ptr[21] = (char*)ext_value_p->option_value; - } else if(!strcmp(ext_value_p->option_name, "red_pcpremark_en")) { - val_ptr[22] = (char*)ext_value_p->option_value; - } else if(!strcmp(ext_value_p->option_name, "red_deiremark_en")) { - val_ptr[23] = (char*)ext_value_p->option_value; - } else if(!strcmp(ext_value_p->option_name, "redpri")) { - val_ptr[24] = (char*)ext_value_p->option_value; - } else if(!strcmp(ext_value_p->option_name, "red_dropprec")) { - val_ptr[25] = (char*)ext_value_p->option_value; - } else if(!strcmp(ext_value_p->option_name, "redpcp")) { - val_ptr[26] = (char*)ext_value_p->option_value; - } else if(!strcmp(ext_value_p->option_name, "reddei")) { - val_ptr[27] = (char*)ext_value_p->option_value; - } else { - rv = -1; - break; - } - - parameter_length++; - switch_ext_p = switch_ext_p->next; - } - - return rv; -} - -static int -parse_policer_aclentry(struct switch_val *val) -{ - struct switch_ext *switch_ext_p, *ext_value_p; - int rv = 0; - switch_ext_p = val->value.ext_val; - while(switch_ext_p) { - ext_value_p = switch_ext_p; - - if(!strcmp(ext_value_p->option_name, "name")) { - switch_ext_p = switch_ext_p->next; - continue; - } else if(!strcmp(ext_value_p->option_name, "index")) { - val_ptr[0] = (char*)ext_value_p->option_value; - } else if(!strcmp(ext_value_p->option_name, "policer_en")) { - val_ptr[1] = (char*)ext_value_p->option_value; - } else if(!strcmp(ext_value_p->option_name, "coupling_en")) { - val_ptr[2] = (char*)ext_value_p->option_value; - } else if(!strcmp(ext_value_p->option_name, "colormode")) { - val_ptr[3] = (char*)ext_value_p->option_value; - } else if(!strcmp(ext_value_p->option_name, "metermode")) { - val_ptr[4] = (char*)ext_value_p->option_value; - } else if(!strcmp(ext_value_p->option_name, "meterunit")) { - val_ptr[5] = (char*)ext_value_p->option_value; - } else if(!strcmp(ext_value_p->option_name, "cir")) { - val_ptr[6] = (char*)ext_value_p->option_value; - } else if(!strcmp(ext_value_p->option_name, "cbs")) { - val_ptr[7] = (char*)ext_value_p->option_value; - } else if(!strcmp(ext_value_p->option_name, "eir")) { - val_ptr[8] = (char*)ext_value_p->option_value; - } else if(!strcmp(ext_value_p->option_name, "ebs")) { - val_ptr[9] = (char*)ext_value_p->option_value; - } else if(!strcmp(ext_value_p->option_name, "yellow_priremark_en")) { - val_ptr[10] = (char*)ext_value_p->option_value; - } else if(!strcmp(ext_value_p->option_name, "yellow_dropprec_remark_en")) { - val_ptr[11] = (char*)ext_value_p->option_value; - } else if(!strcmp(ext_value_p->option_name, "yellow_pcpremark_en")) { - val_ptr[12] = (char*)ext_value_p->option_value; - } else if(!strcmp(ext_value_p->option_name, "yellow_deiremark_en")) { - val_ptr[13] = (char*)ext_value_p->option_value; - } else if(!strcmp(ext_value_p->option_name, "yellowpri")) { - val_ptr[14] = (char*)ext_value_p->option_value; - } else if(!strcmp(ext_value_p->option_name, "yellow_dropprec")) { - val_ptr[15] = (char*)ext_value_p->option_value; - } else if(!strcmp(ext_value_p->option_name, "yellowpcp")) { - val_ptr[16] = (char*)ext_value_p->option_value; - } else if(!strcmp(ext_value_p->option_name, "yellowdei")) { - val_ptr[17] = (char*)ext_value_p->option_value; - } else if(!strcmp(ext_value_p->option_name, "redaction")) { - val_ptr[18] = (char*)ext_value_p->option_value; - } else if(!strcmp(ext_value_p->option_name, "red_priremark_en")) { - val_ptr[19] = (char*)ext_value_p->option_value; - } else if(!strcmp(ext_value_p->option_name, "red_dropprec_remark_en")) { - val_ptr[20] = (char*)ext_value_p->option_value; - } else if(!strcmp(ext_value_p->option_name, "red_pcpremark_en")) { - val_ptr[21] = (char*)ext_value_p->option_value; - } else if(!strcmp(ext_value_p->option_name, "red_deiremark_en")) { - val_ptr[22] = (char*)ext_value_p->option_value; - } else if(!strcmp(ext_value_p->option_name, "redpri")) { - val_ptr[23] = (char*)ext_value_p->option_value; - } else if(!strcmp(ext_value_p->option_name, "red_dropprec")) { - val_ptr[24] = (char*)ext_value_p->option_value; - } else if(!strcmp(ext_value_p->option_name, "redpcp")) { - val_ptr[25] = (char*)ext_value_p->option_value; - } else if(!strcmp(ext_value_p->option_name, "reddei")) { - val_ptr[26] = (char*)ext_value_p->option_value; - } else { - rv = -1; - break; - } - - parameter_length++; - switch_ext_p = switch_ext_p->next; - } - - return rv; -} - -static int -parse_policer_bypass(struct switch_val *val) -{ - struct switch_ext *switch_ext_p, *ext_value_p; - int rv = 0; - switch_ext_p = val->value.ext_val; - while(switch_ext_p) { - ext_value_p = switch_ext_p; - - if(!strcmp(ext_value_p->option_name, "name")) { - switch_ext_p = switch_ext_p->next; - continue; - } else if(!strcmp(ext_value_p->option_name, "frame_type")) { - val_ptr[0] = (char*)ext_value_p->option_value; - } else if(!strcmp(ext_value_p->option_name, "bypass_status")) { - val_ptr[1] = (char*)ext_value_p->option_value; - } else { - rv = -1; - break; - } - - parameter_length++; - switch_ext_p = switch_ext_p->next; - } - - return rv; -} - -#endif - -#ifdef IN_SHAPER -static int -parse_shaper_porttimeslot(struct switch_val *val) -{ - struct switch_ext *switch_ext_p, *ext_value_p; - int rv = 0; - switch_ext_p = val->value.ext_val; - while(switch_ext_p) { - ext_value_p = switch_ext_p; - - if(!strcmp(ext_value_p->option_name, "name")) { - switch_ext_p = switch_ext_p->next; - continue; - } else if(!strcmp(ext_value_p->option_name, "timeslot")) { - val_ptr[0] = (char*)ext_value_p->option_value; - } else { - rv = -1; - break; - } - - parameter_length++; - switch_ext_p = switch_ext_p->next; - } - - return rv; -} - -static int -parse_shaper_flowtimeslot(struct switch_val *val) -{ - struct switch_ext *switch_ext_p, *ext_value_p; - int rv = 0; - switch_ext_p = val->value.ext_val; - while(switch_ext_p) { - ext_value_p = switch_ext_p; - - if(!strcmp(ext_value_p->option_name, "name")) { - switch_ext_p = switch_ext_p->next; - continue; - } else if(!strcmp(ext_value_p->option_name, "timeslot")) { - val_ptr[0] = (char*)ext_value_p->option_value; - } else { - rv = -1; - break; - } - - parameter_length++; - switch_ext_p = switch_ext_p->next; - } - - return rv; -} - -static int -parse_shaper_queuetimeslot(struct switch_val *val) -{ - struct switch_ext *switch_ext_p, *ext_value_p; - int rv = 0; - switch_ext_p = val->value.ext_val; - while(switch_ext_p) { - ext_value_p = switch_ext_p; - - if(!strcmp(ext_value_p->option_name, "name")) { - switch_ext_p = switch_ext_p->next; - continue; - } else if(!strcmp(ext_value_p->option_name, "timeslot")) { - val_ptr[0] = (char*)ext_value_p->option_value; - } else { - rv = -1; - break; - } - - parameter_length++; - switch_ext_p = switch_ext_p->next; - } - - return rv; -} - -static int -parse_shaper_ipgcompensation(struct switch_val *val) -{ - struct switch_ext *switch_ext_p, *ext_value_p; - int rv = 0; - switch_ext_p = val->value.ext_val; - while(switch_ext_p) { - ext_value_p = switch_ext_p; - - if(!strcmp(ext_value_p->option_name, "name")) { - switch_ext_p = switch_ext_p->next; - continue; - } else if(!strcmp(ext_value_p->option_name, "ipgcompensation_length")) { - val_ptr[0] = (char*)ext_value_p->option_value; - } else { - rv = -1; - break; - } - - parameter_length++; - switch_ext_p = switch_ext_p->next; - } - - return rv; -} - -static int -parse_shaper_porttoken(struct switch_val *val) -{ - struct switch_ext *switch_ext_p, *ext_value_p; - int rv = 0; - switch_ext_p = val->value.ext_val; - while(switch_ext_p) { - ext_value_p = switch_ext_p; - - if(!strcmp(ext_value_p->option_name, "name")) { - switch_ext_p = switch_ext_p->next; - continue; - } else if(!strcmp(ext_value_p->option_name, "port_id")) { - val_ptr[0] = (char*)ext_value_p->option_value; - } else if(!strcmp(ext_value_p->option_name, "ctoken_negative_en")) { - val_ptr[1] = (char*)ext_value_p->option_value; - } else if(!strcmp(ext_value_p->option_name, "ctokennum")) { - val_ptr[2] = (char*)ext_value_p->option_value; - } else { - rv = -1; - break; - } - - parameter_length++; - switch_ext_p = switch_ext_p->next; - } - - return rv; -} - -static int -parse_shaper_flowtoken(struct switch_val *val) -{ - struct switch_ext *switch_ext_p, *ext_value_p; - int rv = 0; - switch_ext_p = val->value.ext_val; - while(switch_ext_p) { - ext_value_p = switch_ext_p; - - if(!strcmp(ext_value_p->option_name, "name")) { - switch_ext_p = switch_ext_p->next; - continue; - } else if(!strcmp(ext_value_p->option_name, "flow_id")) { - val_ptr[0] = (char*)ext_value_p->option_value; - } else if(!strcmp(ext_value_p->option_name, "ctoken_negative_en")) { - val_ptr[1] = (char*)ext_value_p->option_value; - } else if(!strcmp(ext_value_p->option_name, "ctokennum")) { - val_ptr[2] = (char*)ext_value_p->option_value; - } else if(!strcmp(ext_value_p->option_name, "etoken_negative_en")) { - val_ptr[3] = (char*)ext_value_p->option_value; - } else if(!strcmp(ext_value_p->option_name, "etokennum")) { - val_ptr[4] = (char*)ext_value_p->option_value; - } else { - rv = -1; - break; - } - - parameter_length++; - switch_ext_p = switch_ext_p->next; - } - - return rv; -} - -static int -parse_shaper_queuetoken(struct switch_val *val) -{ - struct switch_ext *switch_ext_p, *ext_value_p; - int rv = 0; - switch_ext_p = val->value.ext_val; - while(switch_ext_p) { - ext_value_p = switch_ext_p; - - if(!strcmp(ext_value_p->option_name, "name")) { - switch_ext_p = switch_ext_p->next; - continue; - } else if(!strcmp(ext_value_p->option_name, "queue_id")) { - val_ptr[0] = (char*)ext_value_p->option_value; - } else if(!strcmp(ext_value_p->option_name, "ctoken_negative_en")) { - val_ptr[1] = (char*)ext_value_p->option_value; - } else if(!strcmp(ext_value_p->option_name, "ctokennum")) { - val_ptr[2] = (char*)ext_value_p->option_value; - } else if(!strcmp(ext_value_p->option_name, "etoken_negative_en")) { - val_ptr[3] = (char*)ext_value_p->option_value; - } else if(!strcmp(ext_value_p->option_name, "etokennum")) { - val_ptr[4] = (char*)ext_value_p->option_value; - } else { - rv = -1; - break; - } - - parameter_length++; - switch_ext_p = switch_ext_p->next; - } - - return rv; -} - -static int -parse_shaper_portshaper(struct switch_val *val) -{ - struct switch_ext *switch_ext_p, *ext_value_p; - int rv = 0; - switch_ext_p = val->value.ext_val; - while(switch_ext_p) { - ext_value_p = switch_ext_p; - - if(!strcmp(ext_value_p->option_name, "name")) { - switch_ext_p = switch_ext_p->next; - continue; - } else if(!strcmp(ext_value_p->option_name, "port_id")) { - val_ptr[0] = (char*)ext_value_p->option_value; - } else if(!strcmp(ext_value_p->option_name, "meterunit")) { - val_ptr[1] = (char*)ext_value_p->option_value; - } else if(!strcmp(ext_value_p->option_name, "cshaper_en")) { - val_ptr[2] = (char*)ext_value_p->option_value; - } else if(!strcmp(ext_value_p->option_name, "cir")) { - val_ptr[3] = (char*)ext_value_p->option_value; - } else if(!strcmp(ext_value_p->option_name, "cbs")) { - val_ptr[4] = (char*)ext_value_p->option_value; - } else if(!strcmp(ext_value_p->option_name, "framemode")) { - val_ptr[5] = (char*)ext_value_p->option_value; - } else { - rv = -1; - break; - } - - parameter_length++; - switch_ext_p = switch_ext_p->next; - } - - return rv; -} - -static int -parse_shaper_queueshaper(struct switch_val *val) -{ - struct switch_ext *switch_ext_p, *ext_value_p; - int rv = 0; - switch_ext_p = val->value.ext_val; - while(switch_ext_p) { - ext_value_p = switch_ext_p; - - if(!strcmp(ext_value_p->option_name, "name")) { - switch_ext_p = switch_ext_p->next; - continue; - } else if(!strcmp(ext_value_p->option_name, "queue_id")) { - val_ptr[0] = (char*)ext_value_p->option_value; - } else if(!strcmp(ext_value_p->option_name, "coupling_en")) { - val_ptr[1] = (char*)ext_value_p->option_value; - } else if(!strcmp(ext_value_p->option_name, "meterunit")) { - val_ptr[2] = (char*)ext_value_p->option_value; - } else if(!strcmp(ext_value_p->option_name, "cshaper_en")) { - val_ptr[3] = (char*)ext_value_p->option_value; - } else if(!strcmp(ext_value_p->option_name, "cir")) { - val_ptr[4] = (char*)ext_value_p->option_value; - } else if(!strcmp(ext_value_p->option_name, "cbs")) { - val_ptr[5] = (char*)ext_value_p->option_value; - } else if(!strcmp(ext_value_p->option_name, "eshaper_en")) { - val_ptr[6] = (char*)ext_value_p->option_value; - } else if(!strcmp(ext_value_p->option_name, "eir")) { - val_ptr[7] = (char*)ext_value_p->option_value; - } else if(!strcmp(ext_value_p->option_name, "ebs")) { - val_ptr[8] = (char*)ext_value_p->option_value; - } else if(!strcmp(ext_value_p->option_name, "framemode")) { - val_ptr[9] = (char*)ext_value_p->option_value; - } else { - rv = -1; - break; - } - - parameter_length++; - switch_ext_p = switch_ext_p->next; - } - - return rv; -} - -static int -parse_shaper_flowshaper(struct switch_val *val) -{ - struct switch_ext *switch_ext_p, *ext_value_p; - int rv = 0; - switch_ext_p = val->value.ext_val; - while(switch_ext_p) { - ext_value_p = switch_ext_p; - - if(!strcmp(ext_value_p->option_name, "name")) { - switch_ext_p = switch_ext_p->next; - continue; - } else if(!strcmp(ext_value_p->option_name, "flow_id")) { - val_ptr[0] = (char*)ext_value_p->option_value; - } else if(!strcmp(ext_value_p->option_name, "coupling_en")) { - val_ptr[1] = (char*)ext_value_p->option_value; - } else if(!strcmp(ext_value_p->option_name, "meterunit")) { - val_ptr[2] = (char*)ext_value_p->option_value; - } else if(!strcmp(ext_value_p->option_name, "cshaper_en")) { - val_ptr[3] = (char*)ext_value_p->option_value; - } else if(!strcmp(ext_value_p->option_name, "cir")) { - val_ptr[4] = (char*)ext_value_p->option_value; - } else if(!strcmp(ext_value_p->option_name, "cbs")) { - val_ptr[5] = (char*)ext_value_p->option_value; - } else if(!strcmp(ext_value_p->option_name, "eshaper_en")) { - val_ptr[6] = (char*)ext_value_p->option_value; - } else if(!strcmp(ext_value_p->option_name, "eir")) { - val_ptr[7] = (char*)ext_value_p->option_value; - } else if(!strcmp(ext_value_p->option_name, "ebs")) { - val_ptr[8] = (char*)ext_value_p->option_value; - } else if(!strcmp(ext_value_p->option_name, "framemode")) { - val_ptr[9] = (char*)ext_value_p->option_value; - } else { - rv = -1; - break; - } - - parameter_length++; - switch_ext_p = switch_ext_p->next; - } - - return rv; -} -#endif - -#ifdef IN_QOS -static int -parse_qos(const char *command_name, struct switch_val *val) -{ - int rv = -1; - #ifndef IN_QOS_MINI - if(!strcmp(command_name, "QTxBufSts")) { - rv = parse_qos_qtxbufsts(val); - } else if(!strcmp(command_name, "QTxBufNr")) { - rv = parse_qos_qtxbufnr(val); - } else if(!strcmp(command_name, "PtTxBufSts")) { - rv = parse_qos_pttxbufsts(val); - } else if(!strcmp(command_name, "PtTxBufNr")) { - rv = parse_qos_pttxbufnr(val); - } else if(!strcmp(command_name, "PtRxBufNr")) { - rv = parse_qos_ptrxbufnr(val); - } else if(!strcmp(command_name, "PtRedEn")) { - rv = parse_qos_ptreden(val); - } else if(!strcmp(command_name, "PtMode")) { - rv = parse_qos_ptmode(val); - } else if(!strcmp(command_name, "PtModePri")) { - rv = parse_qos_ptmodepri(val); - } else if(!strcmp(command_name, "PtschMode")) { - rv = parse_qos_ptschmode(val); - } else if(!strcmp(command_name, "PtDefaultSpri")) { - rv = parse_qos_ptdefaultspri(val); - } else if(!strcmp(command_name, "PtDefaultCpri")) { - rv = parse_qos_ptdefaultcpri(val); - } else if(!strcmp(command_name, "PtFSpriSts")) { - rv = parse_qos_ptfsprists(val); - } else if(!strcmp(command_name, "PtFCpriSts")) { - rv = parse_qos_ptfcprists(val); - } else if(!strcmp(command_name, "PtQuRemark")) { - rv = parse_qos_ptquremark(val); - } else if (!strcmp(command_name, "Ptgroup")) { - rv = parse_qos_ptgroup(val); - } else if (!strcmp(command_name, "Ptpriprece")) { - rv = parse_qos_ptpri(val); - } else if (!strcmp(command_name, "Ptremark")) { - rv = parse_qos_ptremark(val); - } else if (!strcmp(command_name, "Pcpmap")) { - rv = parse_qos_pcpmap(val); - } else if (!strcmp(command_name, "Flowmap")) { - rv = parse_qos_flowmap(val); - } else if (!strcmp(command_name, "Dscpmap")) { - rv = parse_qos_dscpmap(val); - } else if (!strcmp(command_name, "Qscheduler")) { - rv = parse_qos_qscheduler(val); - } else if (!strcmp(command_name, "Ringqueue")) { - rv = parse_qos_ringqueue(val); - } else if (!strcmp(command_name, "Dequeue")) { - rv = parse_qos_dequeue(val); - } else if (!strcmp(command_name, "Portscheduler")) { - rv = parse_qos_portscheduler(val); - } - #endif - - return rv; -} -#endif - -#ifdef IN_COSMAP -static int -parse_cos(const char *command_name, struct switch_val *val) -{ - int rv = -1; - if(!strcmp(command_name, "Pri2Q")) { - rv = parse_cos_mappri2q(val); - } else if(!strcmp(command_name, "Pri2Ehq")) { - rv = parse_cos_mappri2ehq(val); - } - #ifndef IN_COSMAP_MINI - else if(!strcmp(command_name, "Dscp2Pri")) { - rv = parse_cos_mapdscp2pri(val); - } else if(!strcmp(command_name, "Dscp2Dp")) { - rv = parse_cos_mapdscp2dp(val); - } else if(!strcmp(command_name, "Up2Pri")) { - rv = parse_cos_mapup2pri(val); - } else if(!strcmp(command_name, "Up2Dp")) { - rv = parse_cos_mapup2dp(val); - } else if(!strcmp(command_name, "Dscp2ehPri")) { - rv = parse_cos_mapdscp2ehpri(val); - } else if(!strcmp(command_name, "Dscp2ehDp")) { - rv = parse_cos_mapdscp2ehdp(val); - } else if(!strcmp(command_name, "Up2ehPri")) { - rv = parse_cos_mapup2ehpri(val); - } else if(!strcmp(command_name, "Up2ehDp")) { - rv = parse_cos_mapup2ehdp(val); - } else if(!strcmp(command_name, "EgRemark")) { - rv = parse_cos_mapegremark(val); - } - #endif - - return rv; -} -#endif - -#ifdef IN_RATE -static int -parse_rate(const char *command_name, struct switch_val *val) -{ - int rv = -1; - if(!strcmp(command_name, "PortPolicer")) { - rv = parse_rate_portpolicer(val); - } else if(!strcmp(command_name, "PortShaper")) { - rv = parse_rate_portshaper(val); - } else if(!strcmp(command_name, "QueueShaper")) { - rv = parse_rate_queueshaper(val); - } else if(!strcmp(command_name, "AclPolicer")) { - rv = parse_rate_aclpolicer(val); - } else if(!strcmp(command_name, "PtAddRateByte")) { - rv = parse_rate_ptaddratebyte(val); - } else if(!strcmp(command_name, "PtGolflowen")) { - rv = parse_rate_ptgolflowen(val); - } - - return rv; -} -#endif - -#ifdef IN_PORTCONTROL -static int -parse_port(const char *command_name, struct switch_val *val) -{ - int rv = -1; - if(!strcmp(command_name, "TxHdr")) { - rv = parse_port_txhdr(val); - } else if(!strcmp(command_name, "RxHdr")) { - rv = parse_port_rxhdr(val); - } else if(!strcmp(command_name, "HdrType")) { - rv = parse_port_hdrtype(val); - } - #ifndef IN_PORTCONTROL_MINI - else if(!strcmp(command_name, "Duplex")) { - rv = parse_port_duplex(val); - } else if(!strcmp(command_name, "Speed")) { - rv = parse_port_speed(val); - } else if(!strcmp(command_name, "AutoAdv")) { - rv = parse_port_autoadv(val); - } else if(!strcmp(command_name, "AutoNegEnable")) { - rv = parse_port_autonegenable(val); - } else if(!strcmp(command_name, "AutoNegRestart")) { - rv = parse_port_autonegrestart(val); - } else if(!strcmp(command_name, "FlowCtrl")) { - rv = parse_port_flowctrl(val); - } else if(!strcmp(command_name, "FlowCtrlForceMode")) { - rv = parse_port_flowctrlforcemode(val); - } else if(!strcmp(command_name, "PowerSave")) { - rv = parse_port_powersave(val); - } else if(!strcmp(command_name, "Hibernate")) { - rv = parse_port_hibernate(val); - } else if(!strcmp(command_name, "TxMacStatus")) { - rv = parse_port_txmacstatus(val); - } else if(!strcmp(command_name, "RxMacStatus")) { - rv = parse_port_rxmacstatus(val); - } else if(!strcmp(command_name, "TxFcStatus")) { - rv = parse_port_txfcstatus(val); - } else if(!strcmp(command_name, "RxFcStatus")) { - rv = parse_port_rxfcstatus(val); - } else if(!strcmp(command_name, "BpStatus")) { - rv = parse_port_bpstatus(val); - } else if(!strcmp(command_name, "LinkForceMode")) { - rv = parse_port_linkforcemode(val); - } else if(!strcmp(command_name, "MacLoopback")) { - rv = parse_port_macloopback(val); - } else if(!strcmp(command_name, "CongeDrop")) { - rv = parse_port_congedrop(val); - } else if(!strcmp(command_name, "RingFcThresh")) { - rv = parse_port_ringfcthresh(val); - } else if(!strcmp(command_name, "Ieee8023az")) { - rv = parse_port_ieee8023az(val); - } else if(!strcmp(command_name, "Crossover")) { - rv = parse_port_crossover(val); - } else if(!strcmp(command_name, "PreferMedium")) { - rv = parse_port_prefermedium(val); - } else if(!strcmp(command_name, "FiberMode")) { - rv = parse_port_fibermode(val); - } else if(!strcmp(command_name, "LocalLoopback")) { - rv = parse_port_localloopback(val); - } else if(!strcmp(command_name, "RemoteLoopback")) { - rv = parse_port_remoteloopback(val); - } else if(!strcmp(command_name, "MagicFrameMac")) { - rv = parse_port_magicframemac(val); - } else if(!strcmp(command_name, "Wolstatus")) { - rv = parse_port_wolstatus(val); - } else if(!strcmp(command_name, "InterfaceMode")) { - rv = parse_port_interfacemode(val); - } else if(!strcmp(command_name, "InterfaceModeApply")) { - rv = parse_port_interfacemodeapply(val); - } else if(!strcmp(command_name, "Poweron")) { - rv = parse_port_poweron(val); - } else if(!strcmp(command_name, "Poweroff")) { - rv = parse_port_poweroff(val); - } else if(!strcmp(command_name, "Reset")) { - rv = parse_port_reset(val); - } else if(!strcmp(command_name, "FrameMaxSize")) { - rv = parse_port_framemaxsize(val); - } else if(!strcmp(command_name, "Mtu")) { - rv = parse_port_mtu(val); - } else if(!strcmp(command_name, "Mru")) { - rv = parse_port_mru(val); - } else if(!strcmp(command_name, "Srcfilter")) { - rv = parse_port_srcfilter(val); - } else if(!strcmp(command_name, "Interface3az")) { - rv = parse_port_interface8023az(val); - } else if(!strcmp(command_name, "Promiscmode")) { - rv = parse_port_promiscmode(val); - } else if(!strcmp(command_name, "Eeecfg")) { - rv = parse_port_eeecfg(val); - }else if(!strcmp(command_name, "Srcfiltercfg")) { - rv = parse_port_srcfiltercfg(val); - } else if(!strcmp(command_name, "SwitchPortLoopback")) { - rv = parse_switch_port_loopback(val); - } - #endif - - return rv; -} -#endif - -#ifdef IN_PORTVLAN -static int -parse_portvlan(const char *command_name, struct switch_val *val) -{ - int rv = -1; - if(!strcmp(command_name, "Ingress")) { - rv = parse_portvlan_ingress(val); - } else if(!strcmp(command_name, "Egress")) { - rv = parse_portvlan_egress(val); - } else if(!strcmp(command_name, "Member")) { - rv = parse_portvlan_member(val); - } else if(!strcmp(command_name, "ForceVid")) { - rv = parse_portvlan_forcevid(val); - } else if(!strcmp(command_name, "ForceMode")) { - rv = parse_portvlan_forcemode(val); - } else if(!strcmp(command_name, "SVlanTPID")) { - rv = parse_portvlan_svlantpid(val); - } else if(!strcmp(command_name, "DefaultSvid")) { - rv = parse_portvlan_defaultsvid(val); - } else if(!strcmp(command_name, "DefaultCvid")) { - rv = parse_portvlan_defaultcvid(val); - } else if (!strcmp(command_name, "GlobalQinQMode")) { - rv = parse_portvlan_globalqinqmode(val); - } else if (!strcmp(command_name, "PtQinQMode")) { - rv = parse_portvlan_ptqinqmode(val); -#ifdef HPPE - } else if (!strcmp(command_name, "InTpid")) { - rv = parse_portvlan_intpid(val); - } else if (!strcmp(command_name, "EgTpid")) { - rv = parse_portvlan_egtpid(val); - } else if (!strcmp(command_name, "IngressFilter")) { - rv = parse_portvlan_ingressfilter(val); - } else if (!strcmp(command_name, "DefaultVlanTag")) { - rv = parse_portvlan_defaultvlantag(val); - } else if (!strcmp(command_name, "TagPropagation")) { - rv = parse_portvlan_tagpropagation(val); - } else if (!strcmp(command_name, "TranslationMissAction")) { - rv = parse_portvlan_translationmissaction(val); -#endif - } else if (!strcmp(command_name, "EgMode")) { - rv = parse_portvlan_egmode(val); -#ifdef HPPE - } else if (!strcmp(command_name, "VsiEgMode")) { - rv = parse_portvlan_vsiegmode(val); - } else if (!strcmp(command_name, "VsiEgModeEn")) { - rv = parse_portvlan_vsiegmodeen(val); - } else if (!strcmp(command_name, "Counter")) { - rv = parse_portvlan_counter(val); - } else if (!strcmp(command_name, "TranslationAdv")) { - rv = parse_portvlan_translationadv(val); -#endif - } - #ifndef IN_PORTVLAN_MINI - else if(!strcmp(command_name, "InVlan")) { - rv = parse_portvlan_invlan(val); - } else if(!strcmp(command_name, "TlsMode")) { - rv = parse_portvlan_tlsmode(val); - } else if(!strcmp(command_name, "PriPropagation")) { - rv = parse_portvlan_pripropagation(val); - } else if(!strcmp(command_name, "VlanPropagation")) { - rv = parse_portvlan_vlanpropagation(val); - } else if(!strcmp(command_name, "Translation")) { - rv = parse_portvlan_translation(val); - } else if(!strcmp(command_name, "QinqMode")) { - rv = parse_portvlan_qinqmode(val); - } else if(!strcmp(command_name, "QinqRole")) { - rv = parse_portvlan_qinqrole(val); - } else if(!strcmp(command_name, "MacVlanXlt")) { - rv = parse_portvlan_macvlanxlt(val); - } else if(!strcmp(command_name, "Netiso")) { - rv = parse_portvlan_netiso(val); - } else if(!strcmp(command_name, "EgBypass")) { - rv = parse_portvlan_egbypass(val); - } else if(!strcmp(command_name, "Ptvrfid")) { - rv = parse_portvlan_ptvrfid(val); - } - #endif - - return rv; -} -#endif - -#ifdef IN_VLAN -static int -parse_vlan(const char *command_name, struct switch_val *val) -{ - int rv = -1; - if(!strcmp(command_name, "Entry")) { - rv = parse_vlan_entry(val); - } else if(!strcmp(command_name, "Member")) { - rv = parse_vlan_member(val); - } - #ifndef IN_VLAN_MINI - else if(!strcmp(command_name, "LearnSts")) { - rv = parse_vlan_learnsts(val); - } - #endif - - return rv; -} -#endif - -#ifdef IN_FDB -static int -parse_fdb(const char *command_name, struct switch_val *val) -{ - int rv = -1; - if(!strcmp(command_name, "PortLearn")) { - rv = parse_fdb_portlearn(val); - } - #ifndef IN_FDB_MINI - else if(!strcmp(command_name, "Resventry")) { - rv = parse_fdb_resventry(val); - } else if(!strcmp(command_name, "Entry")) { - rv = parse_fdb_entry(val); - } else if(!strcmp(command_name, "AgeCtrl")) { - rv = parse_fdb_agectrl(val); - } else if(!strcmp(command_name, "AgeTime")) { - rv = parse_fdb_agetime(val); - } else if(!strcmp(command_name, "Vlansmode")) { - rv = parse_fdb_vlansmode(val); - } else if(!strcmp(command_name, "Ptlearnlimit")) { - rv = parse_fdb_ptlearnlimit(val); - } else if(!strcmp(command_name, "Ptlearnexceedcmd")) { - rv = parse_fdb_ptlearnexceedcmd(val); - } else if(!strcmp(command_name, "Learnlimit")) { - rv = parse_fdb_learnlimit(val); - } else if(!strcmp(command_name, "Learnexceedcmd")) { - rv = parse_fdb_learnexceedcmd(val); - } else if(!strcmp(command_name, "PtLearnstatic")) { - rv = parse_fdb_ptlearnstatic(val); - } else if (!strcmp(command_name, "LearnCtrl")) { - rv = parse_fdb_learnctrl(val); - } else if (!strcmp(command_name, "PtLearnCtrl")) { - rv = parse_fdb_ptlearnctrl(val); - } else if (!strcmp(command_name, "PtStationMove")) { - rv = parse_fdb_ptstationmove(val); - } else if (!strcmp(command_name, "PtMacLimitCtrl")) { - rv = parse_fdb_ptmaclimitctrl(val); - } - #endif - - return rv; -} -#endif - -#ifdef IN_RSS_HASH -static int -parse_rsshash(const char *command_name, struct switch_val *val) -{ - int rv = -1; - if (!strcmp(command_name, "Config")) { - rv = parse_rsshash_config(val); - } - - return rv; -} -#endif - -#ifdef IN_IGMP -static int -parse_igmp(const char *command_name, struct switch_val *val) -{ - int rv = -1; - if(!strcmp(command_name, "Mode")) { - rv = parse_igmp_mode(val); - } else if(!strcmp(command_name, "Cmd")) { - rv = parse_igmp_cmd(val); - } else if(!strcmp(command_name, "PortJoin")) { - rv = parse_igmp_portjoin(val); - } else if(!strcmp(command_name, "PortLeave")) { - rv = parse_igmp_portleave(val); - } else if(!strcmp(command_name, "Rp")) { - rv = parse_igmp_rp(val); - } else if(!strcmp(command_name, "CreateStatus")) { - rv = parse_igmp_createstatus(val); - } else if(!strcmp(command_name, "Static")) { - rv = parse_igmp_static(val); - } else if(!strcmp(command_name, "Leaky")) { - rv = parse_igmp_leaky(val); - } else if(!strcmp(command_name, "Version3")) { - rv = parse_igmp_version3(val); - } else if(!strcmp(command_name, "Queue")) { - rv = parse_igmp_queue(val); - } else if(!strcmp(command_name, "Ptlearnlimit")) { - rv = parse_igmp_ptlearnlimit(val); - } else if(!strcmp(command_name, "Ptlearnexceedcmd")) { - rv = parse_igmp_ptlearnexceedcmd(val); - } else if(!strcmp(command_name, "Multi")) { - rv = parse_igmp_multi(val); - } - - return rv; -} -#endif - -#ifdef IN_SEC -static int -parse_sec(const char *command_name, struct switch_val *val) -{ - int rv = -1; - if(!strcmp(command_name, "Mac")) { - rv = parse_sec_mac(val); - } else if(!strcmp(command_name, "Ip")) { - rv = parse_sec_ip(val); - } else if(!strcmp(command_name, "Ip4")) { - rv = parse_sec_ip4(val); - } else if(!strcmp(command_name, "Ip6")) { - rv = parse_sec_ip6(val); - } else if(!strcmp(command_name, "Tcp")) { - rv = parse_sec_tcp(val); - } else if(!strcmp(command_name, "Udp")) { - rv = parse_sec_udp(val); - } else if(!strcmp(command_name, "Icmp4")) { - rv = parse_sec_icmp4(val); - } else if(!strcmp(command_name, "Icmp6")) { - rv = parse_sec_icmp6(val); -#ifdef HPPE - } else if (!strcmp(command_name, "Expctrl")) { - rv = parse_sec_expctrl(val); - } else if (!strcmp(command_name, "L3parser")) { - rv = parse_sec_l3parser(val); - } else if (!strcmp(command_name, "L4parser")) { - rv = parse_sec_l4parser(val); -#endif - } - - return rv; -} -#endif - -#ifdef IN_MISC -static int -parse_misc(const char *command_name, struct switch_val *val) -{ - int rv = -1; - if(!strcmp(command_name, "Eapolcmd")) { - rv = parse_misc_eapolcmd(val); - } else if(!strcmp(command_name, "Eapolstatus")) { - rv = parse_misc_eapolstatus(val); - } else if(!strcmp(command_name, "CpuPort")) { - rv = parse_misc_cpuport(val); - } else if(!strcmp(command_name, "PtUnkUcFilter")) { - rv = parse_misc_ptunkucfilter(val); - } else if(!strcmp(command_name, "PtUnkMcFilter")) { - rv = parse_misc_ptunkmcfilter(val); - } else if(!strcmp(command_name, "PtBcFilter")) { - rv = parse_misc_ptbcfilter(val); - } - #ifndef IN_MISC_MINI - else if(!strcmp(command_name, "CpuVid")) { - rv = parse_misc_cpuvid(val); - } else if(!strcmp(command_name, "FrameMaxSize")) { - rv = parse_misc_framemaxsize(val); - } else if(!strcmp(command_name, "AutoNeg")) { - rv = parse_misc_autoneg(val); - } else if(!strcmp(command_name, "PppoeCmd")) { - rv = parse_misc_pppoecmd(val); - } else if(!strcmp(command_name, "Pppoe")) { - rv = parse_misc_pppoe(val); - } else if(!strcmp(command_name, "PtDhcp")) { - rv = parse_misc_ptdhcp(val); - } else if(!strcmp(command_name, "Arpcmd")) { - rv = parse_misc_arpcmd(val); - } else if(!strcmp(command_name, "Rip")) { - rv = parse_misc_rip(val); - } else if(!strcmp(command_name, "Ptarpreq")) { - rv = parse_misc_ptarpreq(val); - } else if(!strcmp(command_name, "Ptarpack")) { - rv = parse_misc_ptarpack(val); - } else if(!strcmp(command_name, "Extendpppoe")) { - rv = parse_misc_extendpppoe(val); - } else if(!strcmp(command_name, "Pppoeid")) { - rv = parse_misc_pppoeid(val); - } else if(!strcmp(command_name, "RtdPppoe")) { - rv = parse_misc_rtdpppoe(val); - } else if(!strcmp(command_name, "GloMacAddr")) { - rv = parse_misc_glomacaddr(val); - } else if(!strcmp(command_name, "Framecrc")) { - rv = parse_misc_framecrc(val); - } else if(!strcmp(command_name, "Pppoeen")) { - rv = parse_misc_pppoeen(val); - } - #endif - - return rv; -} -#endif - -#ifdef IN_IP -static int -parse_ip(const char *command_name, struct switch_val *val) -{ - int rv = -1; -#ifndef IN_IP_MINI - if(!strcmp(command_name, "Hostentry")) { - rv = parse_ip_hostentry(val); - } else if(!strcmp(command_name, "Intfentry")) { - rv = parse_ip_intfentry(val); - } else if(!strcmp(command_name, "Ptarplearn")) { - rv = parse_ip_ptarplearn(val); - } else if(!strcmp(command_name, "Arplearn")) { - rv = parse_ip_arplearn(val); - } else if(!strcmp(command_name, "Ptipsrcguard")) { - rv = parse_ip_ptipsrcguard(val); - } else if(!strcmp(command_name, "Ptarpsrcguard")) { - rv = parse_ip_ptarpsrcguard(val); - } else if(!strcmp(command_name, "Routestatus")) { - rv = parse_ip_routestatus(val); - } else if(!strcmp(command_name, "Ipunksrc")) { - rv = parse_ip_ipunksrc(val); - } else if(!strcmp(command_name, "Arpunksrc")) { - rv = parse_ip_arpunksrc(val); - } else if(!strcmp(command_name, "IpAgetime")) { - rv = parse_ip_agetime(val); - } else if(!strcmp(command_name, "Wcmphashmode")) { - rv = parse_ip_wcmphashmode(val); - } else if(!strcmp(command_name, "Defaultflowcmd")) { - rv = parse_ip_defaultflowcmd(val); - } else if(!strcmp(command_name, "Defaultrtflowcmd")) { - rv = parse_ip_defaultrtflowcmd(val); - } else if(!strcmp(command_name, "HostRoute")) { - rv = parse_ip_hostroute(val); - } else if(!strcmp(command_name, "DefaultRoute")) { - rv = parse_ip_defaultroute(val); - } else if(!strcmp(command_name, "Vrfbaseaddr")) { - rv = parse_ip_vrfbaseaddr(val); - } else if(!strcmp(command_name, "Vrfbasemask")) { - rv = parse_ip_vrfbasemask(val); - } else if(!strcmp(command_name, "Rfsip4")) { - rv = parse_ip_rfsip4(val); - } else if(!strcmp(command_name, "Rfsip6")) { - rv = parse_ip_rfsip6(val); - } else if (!strcmp(command_name, "Vsiarpsg")) { - rv = parse_ip_vsiarpsg(val); - } else if (!strcmp(command_name, "Vsisg")) { - rv = parse_ip_vsisg(val); - } else if (!strcmp(command_name, "Portarpsg")) { - rv = parse_ip_portarpsg(val); - } else if (!strcmp(command_name, "Portsg")) { - rv = parse_ip_portsg(val); - } else if (!strcmp(command_name, "Pubip")) { - rv = parse_ip_pubip(val); - } else if (!strcmp(command_name, "Networkroute")) { - rv = parse_ip_networkroute(val); - } else if (!strcmp(command_name, "Intf")) { - rv = parse_ip_intf(val); - } else if (!strcmp(command_name, "Vsiintf")) { - rv = parse_ip_vsiintf(val); - } else if (!strcmp(command_name, "Portintf")) { - rv = parse_ip_portintf(val); - } else if (!strcmp(command_name, "Nexthop")) { - rv = parse_ip_nexthop(val); - } else if (!strcmp(command_name, "Portmac")) { - rv = parse_ip_portmac(val); - } else if (!strcmp(command_name, "Routemiss")) { - rv = parse_ip_routemiss(val); - } else if (!strcmp(command_name, "Mcmode")) { - rv = parse_ip_mcmode(val); - } else if (!strcmp(command_name, "Globalctrl")) { - rv = parse_ip_globalctrl(val); - } else if (!strcmp(command_name, "Hostentry")) { - rv = parse_ip_hostentry(val); - } -#endif - return rv; -} -#endif - -#ifdef IN_NAT -static int -parse_nat(const char *command_name, struct switch_val *val) -{ - int rv = -1; - if(!strcmp(command_name, "Natentry")) { - rv = parse_nat_natentry(val); - } else if(!strcmp(command_name, "Naptentry")) { - rv = parse_nat_naptentry(val); - } else if(!strcmp(command_name, "Flowentry")) { - rv = parse_nat_flowentry(val); - } else if(!strcmp(command_name, "Flowcookie")) { - rv = parse_nat_flowcookie(val); - } else if(!strcmp(command_name, "Flowrfs")) { - rv = parse_nat_flowrfs(val); - } else if(!strcmp(command_name, "Natstatus")) { - rv = parse_nat_natstatus(val); - } else if(!strcmp(command_name, "Naptstatus")) { - rv = parse_nat_naptstatus(val); - } else if(!strcmp(command_name, "Nathash")) { - rv = parse_nat_nathash(val); - } else if(!strcmp(command_name, "Naptmode")) { - rv = parse_nat_naptmode(val); - } else if(!strcmp(command_name, "Prvbaseaddr")) { - rv = parse_nat_prvbaseaddr(val); - } else if(!strcmp(command_name, "Prvaddrmode")) { - rv = parse_nat_prvaddrmode(val); - } else if(!strcmp(command_name, "Pubaddr")) { - rv = parse_nat_pubaddr(val); - } else if(!strcmp(command_name, "Natunksess")) { - rv = parse_nat_natunksess(val); - } else if(!strcmp(command_name, "Prvbasemask")) { - rv = parse_nat_prvbasemask(val); - } else if(!strcmp(command_name, "Global")) { - rv = parse_nat_global(val); - } - - return rv; -} -#endif - -#ifdef IN_STP -static int -parse_stp(const char *command_name, struct switch_val *val) -{ - int rv = -1; - if(!strcmp(command_name, "PortState")) { - rv = parse_stp_portstate(val); - } - - return rv; -} -#endif - -#ifdef IN_MIRROR -static int -parse_mirror(const char *command_name, struct switch_val *val) -{ - int rv = -1; - if(!strcmp(command_name, "AnalyPt")) { - rv = parse_mirror_analypt(val); - } else if(!strcmp(command_name, "PtIngress")) { - rv = parse_mirror_ptingress(val); - } else if(!strcmp(command_name, "PtEgress")) { - rv = parse_mirror_ptegress(val); - } else if (!strcmp(command_name, "AnalyCfg")) { - rv = parse_mirror_analycfg(val); - } - - return rv; -} -#endif - -#ifdef IN_LEAKY -static int -parse_leaky(const char *command_name, struct switch_val *val) -{ - int rv = -1; - if(!strcmp(command_name, "UcMode")) { - rv = parse_leaky_ucmode(val); - } else if(!strcmp(command_name, "McMode")) { - rv = parse_leaky_mcmode(val); - } else if(!strcmp(command_name, "ArpMode")) { - rv = parse_leaky_arpmode(val); - } else if(!strcmp(command_name, "PtUcMode")) { - rv = parse_leaky_ptucmode(val); - } else if(!strcmp(command_name, "PtMcMode")) { - rv = parse_leaky_ptmcmode(val); - } - - return rv; -} -#endif - -#ifdef IN_TRUNK -static int -parse_trunk(const char *command_name, struct switch_val *val) -{ - int rv = -1; - if(!strcmp(command_name, "Group")) { - rv = parse_trunk_group(val); - } else if(!strcmp(command_name, "Hashmode")) { - rv = parse_trunk_hashmode(val); - } else if (!strcmp(command_name, "Failover")) { - rv = parse_trunk_failover(val); - } - - return rv; -} -#endif - -#ifdef IN_MIB -static int -parse_mib(const char *command_name, struct switch_val *val) -{ - int rv = -1; - if(!strcmp(command_name, "Status")) { - rv = parse_mib_status(val); - } else if(!strcmp(command_name, "CpuKeep")) { - rv = parse_mib_cpukeep(val); - } - - return rv; -} -#endif - -#ifdef IN_ACL -static int -parse_acl(const char *command_name, struct switch_val *val, a_uint32_t dev_id) -{ - int rv = -1; - if(!strcmp(command_name, "Rule")) { - rv = parse_acl_rule(val, dev_id); - } else if(!strcmp(command_name, "Udfprofile")) { - rv = parse_acl_udfprofile(val); - } else if(!strcmp(command_name, "Udf")) { - rv = parse_acl_udf(val); - } - - return rv; -} -#endif - -#ifdef IN_FLOW -static int -parse_flow(const char *command_name, struct switch_val *val) -{ - int rv = -1; - if (!strcmp(command_name, "Entry")) { - rv = parse_flow_entry(val); - } else if (!strcmp(command_name, "Status")) { - rv = parse_flow_status(val); - } else if (!strcmp(command_name, "Agetime")) { - rv = parse_flow_age(val); - } else if (!strcmp(command_name, "Mgmt")) { - rv = parse_flow_mgmt(val); - } else if (!strcmp(command_name, "Host")) { - rv = parse_flow_host(val); - } else if (!strcmp(command_name, "Global")) { - rv = parse_flow_global(val); - } - - return rv; -} -#endif - -#ifdef IN_BM -static int -parse_bm(const char *command_name, struct switch_val *val) -{ - int rv = -1; - if (!strcmp(command_name, "Ctrl")) { - rv = parse_bm_ctrl(val); - } else if (!strcmp(command_name, "Portgroupmap")) { - rv = parse_bm_portgroupmap(val); - } else if (!strcmp(command_name, "Groupbuff")) { - rv = parse_bm_groupbuff(val); - } else if (!strcmp(command_name, "Portrsvbuff")) { - rv = parse_bm_portrsvbuff(val); - } else if (!strcmp(command_name, "Portsthresh")) { - rv = parse_bm_portsthresh(val); - } else if (!strcmp(command_name, "Portdthresh")) { - rv = parse_bm_portdthresh(val); - } - - return rv; -} -#endif - -#ifdef IN_QM -static int -parse_qm(const char *command_name, struct switch_val *val) -{ - int rv = -1; - if (!strcmp(command_name, "Ucastqbase")) { - rv = parse_qm_ucastqbase(val); - } else if (!strcmp(command_name, "Ucastpriclass")) { - rv = parse_qm_ucastpriclass(val); - } else if (!strcmp(command_name, "Mcastpriclass")) { - rv = parse_qm_mcastpriclass(val); - } else if (!strcmp(command_name, "Queue")) { - rv = parse_qm_queue(val); - } else if (!strcmp(command_name, "Ucasthash")) { - rv = parse_qm_ucasthash(val); - } else if (!strcmp(command_name, "Ucastdflthash")) { - rv = parse_qm_ucastdflthash(val); - } else if (!strcmp(command_name, "Mcastcpucode")) { - rv = parse_qm_mcastcpucode(val); - } else if (!strcmp(command_name, "Acctrl")) { - rv = parse_qm_acctrl(val); - } else if (!strcmp(command_name, "Acprebuffer")) { - rv = parse_qm_acprebuffer(val); - } else if (!strcmp(command_name, "Acqgroup")) { - rv = parse_qm_acqgroup(val); - } else if (!strcmp(command_name, "Acstaticthresh")) { - rv = parse_qm_acsthresh(val); - } else if (!strcmp(command_name, "Acdynamicthresh")) { - rv = parse_qm_acdthresh(val); - } else if (!strcmp(command_name, "Acgroupbuff")) { - rv = parse_qm_acgbuff(val); - } else if (!strcmp(command_name, "Cntctrl")) { - rv = parse_qm_cntctrl(val); - } else if (!strcmp(command_name, "Cnt")) { - rv = parse_qm_cnt(val); - } else if (!strcmp(command_name, "Enqueue")) { - rv = parse_qm_enqueue(val); - } else if (!strcmp(command_name, "Srcprofile")) { - rv = parse_qm_srcprofile(val); - } - - return rv; -} -#endif - -#ifdef IN_SERVCODE -static int -parse_servcode(const char *command_name, struct switch_val *val) -{ - int rv = -1; - if (!strcmp(command_name, "Config")) { - rv = parse_servcode_config(val); - } else if (!strcmp(command_name, "Loopcheck")) { - rv = parse_servcode_loopcheck(val); - } - - return rv; -} -#endif - -#ifdef IN_CTRLPKT -static int -parse_ctrlpkt(const char *command_name, struct switch_val *val) -{ - int rv = -1; - if (!strcmp(command_name, "EthernetType")) { - rv = parse_ctrlpkt_ethernettype(val); - } else if (!strcmp(command_name, "Rfdb")) { - rv = parse_ctrlpkt_rfdb(val); - } else if (!strcmp(command_name, "AppProfile")) { - rv = parse_ctrlpkt_appprofile(val); - } - - return rv; -} -#endif - -#ifdef IN_POLICER -static int -parse_policer(const char *command_name, struct switch_val *val) -{ - int rv = -1; - if(!strcmp(command_name, "Timeslot")) { - rv = parse_policer_timeslot(val); - } else if(!strcmp(command_name, "Fcscompensation")) { - rv = parse_policer_fcscompensation(val); - } else if(!strcmp(command_name, "Portentry")) { - rv = parse_policer_portentry(val); - } else if(!strcmp(command_name, "Aclentry")) { - rv = parse_policer_aclentry(val); - } else if(!strcmp(command_name, "Bypass")) { - rv = parse_policer_bypass(val); - } - - return rv; -} -#endif - -#ifdef IN_SHAPER -static int -parse_shaper(const char *command_name, struct switch_val *val) -{ - int rv = -1; - if(!strcmp(command_name, "Porttimeslot")) { - rv = parse_shaper_porttimeslot(val); - } else if(!strcmp(command_name, "Flowtimeslot")) { - rv = parse_shaper_flowtimeslot(val); - } else if(!strcmp(command_name, "Queuetimeslot")) { - rv = parse_shaper_queuetimeslot(val); - } else if(!strcmp(command_name, "Ipgcompensation")) { - rv = parse_shaper_ipgcompensation(val); - } else if(!strcmp(command_name, "Porttoken")) { - rv = parse_shaper_porttoken(val); - } else if(!strcmp(command_name, "Flowtoken")) { - rv = parse_shaper_flowtoken(val); - } else if(!strcmp(command_name, "Queuetoken")) { - rv = parse_shaper_queuetoken(val); - } else if(!strcmp(command_name, "Portshaper")) { - rv = parse_shaper_portshaper(val); - } else if(!strcmp(command_name, "Queueshaper")) { - rv = parse_shaper_queueshaper(val); - } else if(!strcmp(command_name, "Flowshaper")) { - rv = parse_shaper_flowshaper(val); - } - - return rv; -} -#endif - -#ifdef IN_VSI -static int -parse_vsi_portbasedvsi(struct switch_val *val) -{ - struct switch_ext *switch_ext_p, *ext_value_p; - int rv = 0; - - switch_ext_p = val->value.ext_val; - while (switch_ext_p) { - ext_value_p = switch_ext_p; - - if (!strcmp(ext_value_p->option_name, "name")) { - switch_ext_p = switch_ext_p->next; - continue; - } else if (!strcmp(ext_value_p->option_name, "port_id")) { - val_ptr[0] = (char*)ext_value_p->option_value; - } else if (!strcmp(ext_value_p->option_name, "vsi")) { - val_ptr[1] = (char*)ext_value_p->option_value; - } else { - rv = -1; - break; - } - - parameter_length++; - switch_ext_p = switch_ext_p->next; - } - - return rv; -} - -static int -parse_vsi_vlanbasedvsi(struct switch_val *val) -{ - struct switch_ext *switch_ext_p, *ext_value_p; - int rv = 0; - - switch_ext_p = val->value.ext_val; - while (switch_ext_p) { - ext_value_p = switch_ext_p; - - if (!strcmp(ext_value_p->option_name, "name")) { - switch_ext_p = switch_ext_p->next; - continue; - } else if (!strcmp(ext_value_p->option_name, "port_id")) { - val_ptr[0] = (char*)ext_value_p->option_value; - } else if (!strcmp(ext_value_p->option_name, "svid")) { - val_ptr[1] = (char*)ext_value_p->option_value; - } else if (!strcmp(ext_value_p->option_name, "cvid")) { - val_ptr[2] = (char*)ext_value_p->option_value; - } else if (!strcmp(ext_value_p->option_name, "vsi")) { - val_ptr[3] = (char*)ext_value_p->option_value; - } else { - rv = -1; - break; - } - - parameter_length++; - switch_ext_p = switch_ext_p->next; - } - - return rv; -} - -static int -parse_vsi_learnctrl(struct switch_val *val) -{ - struct switch_ext *switch_ext_p, *ext_value_p; - int rv = 0; - - switch_ext_p = val->value.ext_val; - while (switch_ext_p) { - ext_value_p = switch_ext_p; - - if (!strcmp(ext_value_p->option_name, "name")) { - switch_ext_p = switch_ext_p->next; - continue; - } else if (!strcmp(ext_value_p->option_name, "vsi")) { - val_ptr[0] = (char*)ext_value_p->option_value; - } else if (!strcmp(ext_value_p->option_name, "learn_status")) { - val_ptr[1] = (char*)ext_value_p->option_value; - } else if (!strcmp(ext_value_p->option_name, "learnaction")) { - val_ptr[2] = (char*)ext_value_p->option_value; - } else { - rv = -1; - break; - } - - parameter_length++; - switch_ext_p = switch_ext_p->next; - } - - return rv; -} - -static int -parse_vsi_stationmove(struct switch_val *val) -{ - struct switch_ext *switch_ext_p, *ext_value_p; - int rv = 0; - - switch_ext_p = val->value.ext_val; - while (switch_ext_p) { - ext_value_p = switch_ext_p; - - if (!strcmp(ext_value_p->option_name, "name")) { - switch_ext_p = switch_ext_p->next; - continue; - } else if (!strcmp(ext_value_p->option_name, "vsi")) { - val_ptr[0] = (char*)ext_value_p->option_value; - } else if (!strcmp(ext_value_p->option_name, "stationmove_en")) { - val_ptr[1] = (char*)ext_value_p->option_value; - } else if (!strcmp(ext_value_p->option_name, "stationmove_action")) { - val_ptr[2] = (char*)ext_value_p->option_value; - } else { - rv = -1; - break; - } - - parameter_length++; - switch_ext_p = switch_ext_p->next; - } - - return rv; -} - -static int -parse_vsi_member(struct switch_val *val) -{ - struct switch_ext *switch_ext_p, *ext_value_p; - int rv = 0; - - switch_ext_p = val->value.ext_val; - while (switch_ext_p) { - ext_value_p = switch_ext_p; - - if (!strcmp(ext_value_p->option_name, "name")) { - switch_ext_p = switch_ext_p->next; - continue; - } else if (!strcmp(ext_value_p->option_name, "vsi")) { - val_ptr[0] = (char*)ext_value_p->option_value; - } else if (!strcmp(ext_value_p->option_name, "membership")) { - val_ptr[1] = (char*)ext_value_p->option_value; - } else if (!strcmp(ext_value_p->option_name, "unknown_unicast_membership")) { - val_ptr[2] = (char*)ext_value_p->option_value; - } else if (!strcmp(ext_value_p->option_name, "unknown_multicast_membership")) { - val_ptr[3] = (char*)ext_value_p->option_value; - } else if (!strcmp(ext_value_p->option_name, "broadcast_membership")) { - val_ptr[4] = (char*)ext_value_p->option_value; - } else { - rv = -1; - break; - } - - parameter_length++; - switch_ext_p = switch_ext_p->next; - } - - return rv; -} - -static int -parse_vsi(const char *command_name, struct switch_val *val) -{ - int rv = -1; - if (!strcmp(command_name, "Portbasedvsi")) { - rv = parse_vsi_portbasedvsi(val); - } else if (!strcmp(command_name, "Vlanbasedvsi")) { - rv = parse_vsi_vlanbasedvsi(val); - } else if (!strcmp(command_name, "Learnctrl")) { - rv = parse_vsi_learnctrl(val); - } else if (!strcmp(command_name, "Stationmove")) { - rv = parse_vsi_stationmove(val); - } else if (!strcmp(command_name, "Member")) { - rv = parse_vsi_member(val); - } - - return rv; -} -#endif - -static int -parse_debug_module_func(struct switch_val *val) -{ - struct switch_ext *switch_ext_p, *ext_value_p; - int rv = 0; - - switch_ext_p = val->value.ext_val; - while (switch_ext_p) { - ext_value_p = switch_ext_p; - - if (!strcmp(ext_value_p->option_name, "name")) { - switch_ext_p = switch_ext_p->next; - continue; - } else if (!strcmp(ext_value_p->option_name, "module")) { - val_ptr[0] = (char*)ext_value_p->option_value; - } else if (!strcmp(ext_value_p->option_name, "bitmap0")) { - val_ptr[1] = (char*)ext_value_p->option_value; - } else if (!strcmp(ext_value_p->option_name, "bitmap1")) { - val_ptr[2] = (char*)ext_value_p->option_value; - } else if (!strcmp(ext_value_p->option_name, "bitmap2")) { - val_ptr[3] = (char*)ext_value_p->option_value; - } else { - rv = -1; - break; - } - - parameter_length++; - switch_ext_p = switch_ext_p->next; - } - - return rv; -} - -static int -parse_debug(const char *command_name, struct switch_val *val) -{ - int rv = -1; - if (!strcmp(command_name, "Module_func")) { - rv = parse_debug_module_func(val); - } - return rv; -} - -static int name_transfer(char *name, char *module, char *cmd) -{ - char *p; - unsigned int i = 0, len = 0; - - p = name + 1; - len = strlen(name); - for(i=1; i='A'&&*p<='Z') - break; - p++; - } - - if(ivalue.ext_val; - - memset(whole_command_line, 0, sizeof(whole_command_line)); - memset(module_name, 0, sizeof(module_name)); - memset(command_name, 0, sizeof(command_name)); - while(switch_ext_p) { - ext_value_p = switch_ext_p; - if(!strcmp(ext_value_p->option_name, "name")) { - name_transfer((char*)ext_value_p->option_value, module_name, command_name); - SSDK_DEBUG("module_name:%s command_name:%s\n", module_name, command_name); - break; - } - switch_ext_p = switch_ext_p->next; - } - - parameter_length = 0; - - if(!strcmp(module_name, "Qos")) { -#ifdef IN_QOS - rv = parse_qos(command_name, val); -#endif - } else if(!strcmp(module_name, "Cosmap")) { -#ifdef IN_COSMAP - rv = parse_cos(command_name, val); -#endif - } else if(!strcmp(module_name, "Rate")) { -#ifdef IN_RATE - rv = parse_rate(command_name, val); -#endif - } else if(!strcmp(module_name, "Port")) { -#ifdef IN_PORTCONTROL - rv = parse_port(command_name, val); -#endif - } else if(!strcmp(module_name, "Portvlan")) { -#ifdef IN_PORTVLAN - rv = parse_portvlan(command_name, val); -#endif - } else if(!strcmp(module_name, "Vlan")) { -#ifdef IN_VLAN - rv = parse_vlan(command_name, val); -#endif - } else if(!strcmp(module_name, "Fdb")) { -#ifdef IN_FDB - rv = parse_fdb(command_name, val); -#endif - } else if(!strcmp(module_name, "Rsshash")) { -#ifdef IN_RSS_HASH - rv = parse_rsshash(command_name, val); -#endif - } else if(!strcmp(module_name, "Igmp")) { -#ifdef IN_IGMP - rv = parse_igmp(command_name, val); -#endif - } else if(!strcmp(module_name, "Sec")) { -#ifdef IN_SEC - rv = parse_sec(command_name, val); -#endif - } else if(!strcmp(module_name, "Misc")) { -#ifdef IN_MISC - rv = parse_misc(command_name, val); -#endif - } else if(!strcmp(module_name, "Ip")) { -#ifdef IN_IP - rv = parse_ip(command_name, val); -#endif - } else if(!strcmp(module_name, "Nat")) { -#ifdef IN_NAT - rv = parse_nat(command_name, val); -#endif - } else if(!strcmp(module_name, "Stp")) { -#ifdef IN_STP - rv = parse_stp(command_name, val); -#endif - } else if(!strcmp(module_name, "Mirror")) { -#ifdef IN_MIRROR - rv = parse_mirror(command_name, val); -#endif - } else if(!strcmp(module_name, "Leaky")) { -#ifdef IN_LEAKY - rv = parse_leaky(command_name, val); -#endif - } else if(!strcmp(module_name, "Trunk")) { -#ifdef IN_TRUNK - rv = parse_trunk(command_name, val); -#endif - } else if(!strcmp(module_name, "Mib")) { -#ifdef IN_MIB - rv = parse_mib(command_name, val); -#endif - } else if(!strcmp(module_name, "Acl")) { -#ifdef IN_ACL - rv = parse_acl(command_name, val, priv->device_id); -#endif - } else if(!strcmp(module_name, "Flow")) { -#ifdef IN_FLOW - rv = parse_flow(command_name, val); -#endif - } else if(!strcmp(module_name, "Bm")) { -#ifdef IN_BM - rv = parse_bm(command_name, val); -#endif - } else if(!strcmp(module_name, "Qm")) { -#ifdef IN_QM - rv = parse_qm(command_name, val); -#endif - } else if(!strcmp(module_name, "Servcode")) { -#ifdef IN_SERVCODE - rv = parse_servcode(command_name, val); -#endif - } else if(!strcmp(module_name, "Ctrlpkt")) { -#ifdef IN_CTRLPKT - rv = parse_ctrlpkt(command_name, val); -#endif - } else if(!strcmp(module_name, "Policer")) { -#ifdef IN_POLICER - rv = parse_policer(command_name, val); -#endif - } else if(!strcmp(module_name, "Shaper")) { -#ifdef IN_SHAPER - rv = parse_shaper(command_name, val); -#endif - } else if(!strcmp(module_name, "Vsi")) { -#ifdef IN_VSI - rv = parse_vsi(command_name, val); -#endif - } else if(!strcmp(module_name, "Debug")) { - rv = parse_debug(command_name, val); - } - - if(!rv) { - strlcat(whole_command_line, module_name, sizeof(whole_command_line)); - strlcat(whole_command_line, " ", sizeof(whole_command_line)); - strlcat(whole_command_line, command_name, sizeof(whole_command_line)); - strlcat(whole_command_line, " ", sizeof(whole_command_line)); - strlcat(whole_command_line, "set", sizeof(whole_command_line)); - strlcat(whole_command_line, " ", sizeof(whole_command_line)); - for(i=0; idevice_id); - set_talk_mode(0); - rv = cmd_run_one(whole_command_line); - set_talk_mode(1); - - SSDK_DEBUG("cmd_run_one: ret=%d\r\n", rv); - - return rv; -} diff --git a/feeds/ipq807x/qca-ssdk/src/src/ref/ref_vlan.c b/feeds/ipq807x/qca-ssdk/src/src/ref/ref_vlan.c deleted file mode 100755 index 4b99f2c4c..000000000 --- a/feeds/ipq807x/qca-ssdk/src/src/ref/ref_vlan.c +++ /dev/null @@ -1,562 +0,0 @@ -/* - * Copyright (c) 2012, 2014, 2017, The Linux Foundation. All rights reserved. - * Permission to use, copy, modify, and/or distribute this software for - * any purpose with or without fee is hereby granted, provided that the - * above copyright notice and this permission notice appear in all copies. - * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES - * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR - * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES - * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN - * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT - * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. - */ - -#include "sw.h" -#include "ssdk_init.h" -#include "fal_init.h" -#include "fal_misc.h" -#include "fal_mib.h" -#include "fal_port_ctrl.h" -#include "fal_portvlan.h" -#include "fal_fdb.h" -#include "fal_stp.h" -#include "fal_igmp.h" -#include "fal_qos.h" -#include "fal_acl.h" -#include "hsl.h" -#include "hsl_dev.h" -#include "ssdk_init.h" -#include "ssdk_dts.h" -#include "hsl_phy.h" -#include -#include -#include -#include -#include -#include -#include -//#include -#include -#if (LINUX_VERSION_CODE < KERNEL_VERSION(3,14,0)) -#include -#endif -#include -#include -#include -#include "ssdk_plat.h" -#include "ref_vlan.h" -#ifdef BOARD_AR71XX -#include "ssdk_uci.h" -#endif - - -extern ssdk_chip_type SSDK_CURRENT_CHIP_TYPE; - -#if !defined(IN_VLAN_MINI) -sw_error_t -qca_lan_wan_cfg_set(a_uint32_t dev_id, qca_lan_wan_cfg_t *lan_wan_cfg) -{ - a_uint32_t i = 0, lan_bmp = 0, wan_bmp = 0; - sw_error_t rv = SW_OK; - fal_vlan_t vlan_entry; - - SW_RTN_ON_NULL(lan_wan_cfg); - - switch (SSDK_CURRENT_CHIP_TYPE) { - case CHIP_ISIS: - case CHIP_ISISC: - case CHIP_DESS: - break; - default: - return SW_NOT_SUPPORTED; - } - - fal_vlan_flush(dev_id); - aos_mem_set(&vlan_entry, 0, sizeof(vlan_entry)); - - if (lan_wan_cfg->lan_only_mode) { -#if defined(IN_PORTVLAN) - while (i < sizeof(lan_wan_cfg->v_port_info)/sizeof(lan_wan_cfg->v_port_info[0])) { - if (lan_wan_cfg->v_port_info[i].valid) { - /* use the portbased vlan table for forwarding */ - rv = fal_port_1qmode_set(dev_id, - lan_wan_cfg->v_port_info[i].port_id, - FAL_1Q_DISABLE); - SW_RTN_ON_ERROR(rv); - rv = fal_port_egvlanmode_set(dev_id, - lan_wan_cfg->v_port_info[i].port_id, - FAL_EG_UNMODIFIED); - SW_RTN_ON_ERROR(rv); - rv = fal_port_default_cvid_set(dev_id, - lan_wan_cfg->v_port_info[i].port_id, - 0); - SW_RTN_ON_ERROR(rv); - lan_bmp |= (0x1 << lan_wan_cfg->v_port_info[i].port_id); - } - i++; - } - /* CPU port 0 configurations */ - rv = fal_port_1qmode_set(dev_id, SSDK_PORT_CPU, FAL_1Q_DISABLE); - SW_RTN_ON_ERROR(rv); - rv = fal_port_egvlanmode_set(dev_id, SSDK_PORT_CPU, FAL_EG_UNMODIFIED); - SW_RTN_ON_ERROR(rv); - rv = fal_port_default_cvid_set(dev_id, SSDK_PORT_CPU, 0); - SW_RTN_ON_ERROR(rv); - rv = fal_portvlan_member_update(dev_id, SSDK_PORT_CPU, lan_bmp); - SW_RTN_ON_ERROR(rv); -#endif - } else { - while (i < sizeof(lan_wan_cfg->v_port_info)/sizeof(lan_wan_cfg->v_port_info[0])) { - if (lan_wan_cfg->v_port_info[i].valid) { - rv = fal_vlan_find(dev_id, - lan_wan_cfg->v_port_info[i].vid, &vlan_entry); - /* create vlan entry if the vlan entry does not exist */ - if (rv == SW_NOT_FOUND) { - rv = fal_vlan_create(dev_id, - lan_wan_cfg->v_port_info[i].vid); - SW_RTN_ON_ERROR(rv); -#if defined(IN_PORTVLAN) - rv = fal_port_1qmode_set(dev_id, - SSDK_PORT_CPU, FAL_1Q_SECURE); - SW_RTN_ON_ERROR(rv); -#endif - rv = fal_vlan_member_add(dev_id, - lan_wan_cfg->v_port_info[i].vid, - SSDK_PORT_CPU, FAL_EG_TAGGED); - SW_RTN_ON_ERROR(rv); - } - rv = fal_vlan_member_add(dev_id, - lan_wan_cfg->v_port_info[i].vid, - lan_wan_cfg->v_port_info[i].port_id, - FAL_EG_UNTAGGED); - SW_RTN_ON_ERROR(rv); -#if defined(IN_PORTVLAN) - rv = fal_port_1qmode_set(dev_id, - lan_wan_cfg->v_port_info[i].port_id, - FAL_1Q_SECURE); - SW_RTN_ON_ERROR(rv); - - rv = fal_port_default_cvid_set(dev_id, - lan_wan_cfg->v_port_info[i].port_id, - lan_wan_cfg->v_port_info[i].vid); - SW_RTN_ON_ERROR(rv); -#endif - if (lan_wan_cfg->v_port_info[i].is_wan_port) { - wan_bmp |= (0x1 << lan_wan_cfg->v_port_info[i].port_id); - } else { - lan_bmp |= (0x1 << lan_wan_cfg->v_port_info[i].port_id); - } - } - i++; - } - } - ssdk_lan_bmp_set(dev_id, lan_bmp); - ssdk_wan_bmp_set(dev_id, wan_bmp); - qca_ssdk_port_bmp_set(dev_id, lan_bmp|wan_bmp); -#if defined(DESS) && defined(IN_TRUNK) - if(SSDK_CURRENT_CHIP_TYPE == CHIP_DESS) { - ssdk_dess_trunk_init(dev_id, wan_bmp); - } -#endif -#if defined(IN_PORTVLAN) - ssdk_portvlan_init(dev_id); -#endif - return rv; -} - -sw_error_t -qca_lan_wan_cfg_get(a_uint32_t dev_id, qca_lan_wan_cfg_t *lan_wan_cfg) -{ - sw_error_t rv = SW_OK; - fal_vlan_t vlan_entry; - fal_pbmp_t member_pmap, lan_bmp, wan_bmp; - a_uint32_t port_id, entry_id, vlan_id; - - SW_RTN_ON_NULL(lan_wan_cfg); - - switch (SSDK_CURRENT_CHIP_TYPE) { - case CHIP_ISIS: - case CHIP_ISISC: - case CHIP_DESS: - break; - default: - return SW_NOT_SUPPORTED; - } - - lan_bmp = ssdk_lan_bmp_get(dev_id); - wan_bmp = ssdk_wan_bmp_get(dev_id); - - member_pmap = lan_bmp | wan_bmp; - vlan_id = FAL_NEXT_ENTRY_FIRST_ID; - entry_id = 0; - - while (1) { - aos_mem_set(&vlan_entry, 0, sizeof(vlan_entry)); - rv = fal_vlan_next(dev_id, vlan_id, &vlan_entry); - if (rv != SW_OK) { - break; - } - - /* - * the special port id should be existed only in one vlan entry - * starting from port 1. - */ - port_id = 1; - while (vlan_entry.mem_ports >> port_id) { - if (((vlan_entry.mem_ports >> port_id) & 1) && - SW_IS_PBMP_MEMBER(member_pmap, port_id)) { - lan_wan_cfg->v_port_info[entry_id].port_id = port_id; - lan_wan_cfg->v_port_info[entry_id].vid = vlan_entry.vid; - lan_wan_cfg->v_port_info[entry_id].valid = A_TRUE; - lan_wan_cfg->v_port_info[entry_id].is_wan_port = - SW_IS_PBMP_MEMBER(wan_bmp, port_id) ? A_TRUE : A_FALSE; - entry_id++; - } - port_id++; - } - vlan_id = vlan_entry.vid; - } - - /* - * no vlan entry exists, the portbased vlan used. - */ -#if defined(IN_PORTVLAN) - if (entry_id == 0) { - lan_wan_cfg->lan_only_mode = A_TRUE; - port_id = 1; - while (lan_bmp >> port_id) { - if ((lan_bmp >> port_id) & 1) { - lan_wan_cfg->v_port_info[entry_id].port_id = port_id; - lan_wan_cfg->v_port_info[entry_id].vid = 0; - lan_wan_cfg->v_port_info[entry_id].is_wan_port = A_FALSE; - - member_pmap = 0; -#if !defined(IN_PORTVLAN_MINI) - fal_portvlan_member_get(dev_id, port_id, &member_pmap); -#endif - lan_wan_cfg->v_port_info[entry_id].valid = - member_pmap ? A_TRUE : A_FALSE; - entry_id++; - } - port_id++; - } - } -#endif - return SW_OK; -} -#endif - -int -qca_ar8327_sw_enable_vlan0(a_uint32_t dev_id, a_bool_t enable, a_uint8_t portmap) -{ - fal_vlan_t entry; - fal_acl_rule_t rule; - int i = 0; - - memset(&entry, 0, sizeof(fal_vlan_t)); - memset(&rule, 0, sizeof(fal_acl_rule_t)); - for (i = 0; i < AR8327_NUM_PORTS; i ++) { - fal_port_tls_set(dev_id, i, A_FALSE); - fal_port_vlan_propagation_set(dev_id, i, FAL_VLAN_PROPAGATION_REPLACE); - } - - if (enable) { - entry.fid = 0; - entry.mem_ports = portmap; - entry.unmodify_ports = portmap; - entry.vid = 0; - fal_vlan_entry_append(dev_id, &entry); - for (i = 0; i < AR8327_NUM_PORTS; i++) { - if (portmap & (0x1 << i)) { - fal_port_egvlanmode_set(dev_id, i, FAL_EG_UNTOUCHED); - fal_port_tls_set(dev_id, i, A_TRUE); - fal_port_vlan_propagation_set(dev_id, i, FAL_VLAN_PROPAGATION_DISABLE); - fal_acl_port_udf_profile_set(dev_id, i, FAL_ACL_UDF_TYPE_L2, 12, 4); - } - } - - fal_acl_list_creat(dev_id, 0, 0); - rule.rule_type = FAL_ACL_RULE_UDF; - rule.udf_len = 4; - rule.udf_val[0] = 0x81; - rule.udf_val[1] = 0; - rule.udf_val[2] = 0; - rule.udf_val[3] = 0; - rule.udf_mask[0] = 0xff; - rule.udf_mask[1] = 0xff; - rule.udf_mask[2] = 0xf; - rule.udf_mask[3] = 0xff; - FAL_FIELD_FLG_SET(rule.field_flg, FAL_ACL_FIELD_UDF); - FAL_ACTION_FLG_SET(rule.action_flg, FAL_ACL_ACTION_REMARK_LOOKUP_VID); - fal_acl_rule_add(dev_id, 0, 0, 1, &rule); - for (i = 0; i < AR8327_NUM_PORTS; i ++) { - fal_acl_list_unbind(dev_id, 0, 0, 0, i); - if (portmap & (0x1 << i)) { - fal_acl_list_bind(dev_id, 0, 0, 0, i); - } - } - fal_acl_status_set(dev_id, A_TRUE); - } - else { - fal_acl_rule_delete(dev_id, 0, 0, 1); - } - - return 0; -} - -#if defined(IN_SWCONFIG) -int -qca_ar8327_sw_set_vlan(struct switch_dev *dev, - const struct switch_attr *attr, - struct switch_val *val) -{ - struct qca_phy_priv *priv = qca_phy_priv_get(dev); - - priv->vlan = !!val->value.i; - - #ifdef BOARD_AR71XX - if(SSDK_CURRENT_CHIP_TYPE == CHIP_SHIVA) { - ssdk_uci_sw_set_vlan(attr, val); - } - #endif - - return 0; -} - -int -qca_ar8327_sw_get_vlan(struct switch_dev *dev, - const struct switch_attr *attr, - struct switch_val *val) -{ - struct qca_phy_priv *priv = qca_phy_priv_get(dev); - - val->value.i = priv->vlan; - - return 0; -} - -int -qca_ar8327_sw_set_vid(struct switch_dev *dev, - const struct switch_attr *attr, - struct switch_val *val) -{ - struct qca_phy_priv *priv = qca_phy_priv_get(dev); - - priv->vlan_id[val->port_vlan] = val->value.i; - -#ifdef BOARD_AR71XX - if(SSDK_CURRENT_CHIP_TYPE == CHIP_SHIVA) { - ssdk_uci_sw_set_vid(attr, val); - } -#endif - - return 0; -} - -int -qca_ar8327_sw_get_vid(struct switch_dev *dev, - const struct switch_attr *attr, - struct switch_val *val) -{ - struct qca_phy_priv *priv = qca_phy_priv_get(dev); - - val->value.i = priv->vlan_id[val->port_vlan]; - - return 0; -} - -int -qca_ar8327_sw_get_pvid(struct switch_dev *dev, int port, int *vlan) -{ - struct qca_phy_priv *priv = qca_phy_priv_get(dev); - - *vlan = priv->pvid[port]; - - return 0; -} - -int -qca_ar8327_sw_set_pvid(struct switch_dev *dev, int port, int vlan) -{ - struct qca_phy_priv *priv = qca_phy_priv_get(dev); - - /* make sure no invalid PVIDs get set */ - if (vlan >= dev->vlans) - return -1; - - priv->pvid[port] = vlan; - -#ifdef BOARD_AR71XX - if(SSDK_CURRENT_CHIP_TYPE == CHIP_SHIVA) { - ssdk_uci_sw_set_pvid(port, vlan); - } -#endif - - return 0; -} - -int -qca_ar8327_sw_get_ports(struct switch_dev *dev, struct switch_val *val) -{ - struct qca_phy_priv *priv = qca_phy_priv_get(dev); - a_uint8_t ports = priv->vlan_table[val->port_vlan]; - int i; - - val->len = 0; - for (i = 0; i < dev->ports; i++) { - struct switch_port *p; - - if (!(ports & (1 << i))) - continue; - - p = &val->value.ports[val->len++]; - p->id = i; - if (priv->vlan_tagged[val->port_vlan] & (1 << i)) - p->flags = (1 << SWITCH_PORT_FLAG_TAGGED); - else - p->flags = 0; - - /*Handle for VLAN 0*/ - if (val->port_vlan == 0) - p->flags = (1 << SWITCH_PORT_FLAG_TAGGED); - } - - return 0; -} - -int -qca_ar8327_sw_set_ports(struct switch_dev *dev, struct switch_val *val) -{ - struct qca_phy_priv *priv = qca_phy_priv_get(dev); - a_uint8_t *vt = &priv->vlan_table[val->port_vlan]; - int i; - -#ifdef BOARD_AR71XX - if(SSDK_CURRENT_CHIP_TYPE == CHIP_SHIVA) { - ssdk_uci_sw_set_ports(val); - } -#endif - - /*Handle for VLAN 0*/ - if (val->port_vlan == 0) { - priv->vlan_table[0] = 0; - for (i = 0; i < val->len; i++) { - struct switch_port *p = &val->value.ports[i]; - priv->vlan_table[0] |= (1 << p->id); - } - - return 0; - } - if (priv->vlan_id[val->port_vlan] == 0) - priv->vlan_id[val->port_vlan] = val->port_vlan; - *vt = 0; - for (i = 0; i < val->len; i++) { - struct switch_port *p = &val->value.ports[i]; - - if (p->flags & (1 << SWITCH_PORT_FLAG_TAGGED)) { - priv->vlan_tagged[val->port_vlan] |= (1 << p->id); - } else { - priv->vlan_tagged[val->port_vlan] &= ~(1 << p->id); - priv->pvid[p->id] = val->port_vlan; - } - - *vt |= 1 << p->id; - } - - return 0; -} - -int -qca_ar8327_sw_hw_apply(struct switch_dev *dev) -{ - struct qca_phy_priv *priv = qca_phy_priv_get(dev); - fal_pbmp_t *portmask = NULL; - int i, j; - - if (priv->version == QCA_VER_HPPE) { - return 0; - } - - portmask = aos_mem_alloc(sizeof(fal_pbmp_t) * dev->ports); - if (portmask == NULL) { - SSDK_ERROR("%s: portmask malloc failed. \n", __func__); - return -1; - } - memset(portmask, 0, sizeof(fal_pbmp_t) * dev->ports); - - mutex_lock(&priv->reg_mutex); - - if (!priv->init) { - /*Handle VLAN 0 entry*/ - if (priv->vlan_id[0] == 0 && priv->vlan_table[0] == 0) { - qca_ar8327_sw_enable_vlan0(priv->device_id, A_FALSE, 0); - } - - /* calculate the port destination masks and load vlans - * into the vlan translation unit */ - for (j = 0; j < AR8327_MAX_VLANS; j++) { - u8 vp = priv->vlan_table[j]; - - if (!vp) { - fal_vlan_delete(priv->device_id, priv->vlan_id[j]); - continue; - } - fal_vlan_delete(priv->device_id, priv->vlan_id[j]); - fal_vlan_create(priv->device_id, priv->vlan_id[j]); - - for (i = 0; i < dev->ports; i++) { - u8 mask = (1 << i); - if (vp & mask) { - fal_vlan_member_add(priv->device_id, priv->vlan_id[j], i, - (mask & priv->vlan_tagged[j])? FAL_EG_TAGGED : FAL_EG_UNTAGGED); - portmask[i] |= vp & ~mask; - } - } - if (SSDK_CURRENT_CHIP_TYPE == CHIP_SHIVA) - fal_vlan_member_update(priv->device_id,priv->vlan_id[j],vp,0); - } - - /*Hanlde VLAN 0 entry*/ - if (priv->vlan_id[0] == 0 && priv->vlan_table[0]) { - qca_ar8327_sw_enable_vlan0(priv->device_id,A_TRUE, priv->vlan_table[0]); - } - - } else { - /* vlan disabled: port based vlan used */ - ssdk_portvlan_init(priv->device_id); - } - - /* update the port destination mask registers and tag settings */ - for (i = 0; i < dev->ports; i++) { - int pvid; - fal_pt_1qmode_t ingressMode; - fal_pt_1q_egmode_t egressMode; - - if (priv->vlan) { - pvid = priv->vlan_id[priv->pvid[i]]; - ingressMode = FAL_1Q_SECURE; - } else { - pvid = 0; - ingressMode = FAL_1Q_DISABLE; - } - egressMode = FAL_EG_UNTOUCHED; - - fal_port_1qmode_set(priv->device_id, i, ingressMode); - fal_port_egvlanmode_set(priv->device_id, i, egressMode); - fal_port_default_cvid_set(priv->device_id, i, pvid); - if (!priv->init && priv->vlan) { - fal_portvlan_member_update(priv->device_id, i, portmask[i]); - } - } - - aos_mem_free(portmask); - portmask = NULL; - - mutex_unlock(&priv->reg_mutex); - - return 0; -} -#endif - - diff --git a/feeds/ipq807x/qca-ssdk/src/src/ref/ref_vsi.c b/feeds/ipq807x/qca-ssdk/src/src/ref/ref_vsi.c deleted file mode 100755 index 1c7900d09..000000000 --- a/feeds/ipq807x/qca-ssdk/src/src/ref/ref_vsi.c +++ /dev/null @@ -1,494 +0,0 @@ -/* - * Copyright (c) 2016-2017, The Linux Foundation. All rights reserved. - * Permission to use, copy, modify, and/or distribute this software for - * any purpose with or without fee is hereby granted, provided that the - * above copyright notice and this permission notice appear in all copies. - * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES - * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR - * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES - * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN - * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT - * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. - */ -#include "ref_vsi.h" -#include "ssdk_init.h" -#include "ssdk_plat.h" - -#define PPE_VSI_MAX FAL_VSI_MAX -#define PPE_VSI_RESERVE_MAX 6 - -static ref_vsi_t ref_vsi_mapping[SW_MAX_NR_DEV][PPE_VSI_MAX+1] ={{{0, 0, NULL}, - {0, 0, NULL}, - {0, 0, NULL}}}; -static a_uint32_t default_port_vsi[PPE_VSI_PPORT_NR] = {0, 1, 2, 3, 4, 5, 6};/*PPORT*/ - -static aos_lock_t ppe_vlan_vsi_lock[SW_MAX_NR_DEV]; - -static sw_error_t -_ppe_vsi_member_init(a_uint32_t dev_id, a_uint32_t vsi_id) -{ - fal_vsi_member_t vsi_member; - - aos_mem_zero(&vsi_member, sizeof(vsi_member)); - - vsi_member.member_ports = 0x1; - vsi_member.umc_ports = 0x1; - vsi_member.uuc_ports = 0x1; - vsi_member.bc_ports = 0x1; - - fal_vsi_member_set(dev_id, vsi_id, &vsi_member); - - return SW_OK; -} - -static sw_error_t -_ppe_vsi_member_update(a_uint32_t dev_id, a_uint32_t vsi_id, - fal_port_t port_id, a_uint32_t op) -{ - sw_error_t rv; - fal_vsi_member_t vsi_member; - - rv = fal_vsi_member_get( dev_id, vsi_id, &vsi_member); - if( rv != SW_OK ) - return rv; - if( PPE_VSI_DEL == op ) - { - vsi_member.member_ports &= (~(1<stag_vid) && - (ctag_vid == p_vsi_info->ctag_vid)) - { - p_vsi_info->vport_bitmap |= 1 << port_id; - break; - } - p_vsi_info = p_vsi_info->pNext; - } - - if(p_vsi_info == NULL)/*create a new entry if no match*/ - { - SSDK_DEBUG("port %d svlan %d cvlan %d vsi %d create new entry\n", - port_id, stag_vid, ctag_vid, vsi_id); - p_vsi_info = aos_mem_alloc(sizeof(ref_vlan_info_t)); - if(p_vsi_info == NULL) - { - SSDK_ERROR("port %d svlan %d cvlan %d vsi %d aos_mem_alloc fail\n", - port_id, stag_vid, ctag_vid, vsi_id); - return SW_NO_RESOURCE; - } - p_vsi_info->vport_bitmap = 1 << port_id; - p_vsi_info->stag_vid = stag_vid; - p_vsi_info->ctag_vid = ctag_vid; - p_vsi_info->pNext = (ref_vsi_mapping[dev_id][vsi_id].pHead); - ref_vsi_mapping[dev_id][vsi_id].pHead = p_vsi_info; - } - - return rv; -} - -static sw_error_t _ppe_vlan_vsi_mapping_del(a_uint32_t dev_id, fal_port_t port_id, - a_uint32_t stag_vid, a_uint32_t ctag_vid, a_uint32_t vsi_id) -{ - ref_vlan_info_t *p_vsi_info = NULL; - ref_vlan_info_t *p_prev = NULL; - sw_error_t rv; - a_bool_t in_vsi = 0; - - rv = fal_port_vlan_vsi_set(dev_id, port_id, stag_vid, ctag_vid, PPE_VSI_INVALID); - if( rv != SW_OK ) - { - SSDK_ERROR("port %d svlan %d cvlan %d vsi %d set fail, rv = %d\n", - port_id, stag_vid, ctag_vid, vsi_id, rv); - return rv; - } - - /*vlan based vsi update*/ - p_vsi_info = ref_vsi_mapping[dev_id][vsi_id].pHead; - p_prev = p_vsi_info; - while(p_vsi_info != NULL) - { - if(p_vsi_info->vport_bitmap & (1 << port_id)) - { - if((ctag_vid == p_vsi_info->ctag_vid) && - (stag_vid == p_vsi_info->stag_vid)) - { - /*update software data*/ - p_vsi_info->vport_bitmap &= (~(1 << port_id)); - if(p_vsi_info->vport_bitmap == 0)/*free node if bitmap is 0*/ - { - if(p_vsi_info == ref_vsi_mapping[dev_id][vsi_id].pHead) - { - ref_vsi_mapping[dev_id][vsi_id].pHead = - p_vsi_info->pNext; - } - else - { - p_prev->pNext = p_vsi_info->pNext; - } - aos_mem_free(p_vsi_info); - p_vsi_info = NULL; - break; - } - } - else - { - in_vsi = 1;/*port + another vlan --> vsi*/ - } - } - p_prev = p_vsi_info; - p_vsi_info = p_vsi_info->pNext; - } - - if(in_vsi == 0 && - (!(1 << port_id & ref_vsi_mapping[dev_id][vsi_id].pport_bitmap))) - { - rv = _ppe_vsi_member_update(dev_id, vsi_id, port_id, PPE_VSI_DEL); - if( rv != SW_OK ) - { - SSDK_ERROR("port %d svlan %d cvlan %d vsi %d fail, rv = %d\n", - port_id, stag_vid, ctag_vid, vsi_id, rv); - return rv; - } - } - - return SW_OK; -} - -static sw_error_t _ppe_port_vsi_mapping_update(a_uint32_t dev_id, - fal_port_t port_id, a_uint32_t vsi_id) -{ - ref_vsi_t *p_vsi = NULL; - sw_error_t rv; - a_uint32_t i = 0; - - - if(ref_vsi_mapping[dev_id][vsi_id].valid == 0) - { - SSDK_ERROR("port %d vsi %d entry not found\n", port_id, vsi_id); - return SW_NOT_FOUND; - } - - /*check port previous vsi*/ - for( i = 0; i <= PPE_VSI_MAX; i++ ) - { - p_vsi = &(ref_vsi_mapping[dev_id][i]); - if(p_vsi->valid != 0 && (p_vsi->pport_bitmap & (1 << port_id))) - { - /*remmove from preious vsi*/ - rv = _ppe_vsi_member_update(dev_id, i, port_id, PPE_VSI_DEL); - if( rv != SW_OK ) - return rv; - p_vsi->pport_bitmap &= (~(1<vport_bitmap & (1 << port_id)) && - (ctag_vid== p_vsi_info->ctag_vid) && - (stag_vid== p_vsi_info->stag_vid)) - { - *vsi_id = i; - SSDK_DEBUG("Returned port %d svlan %d cvlan %d vsi %d\n", - port_id, stag_vid, ctag_vid, *vsi_id); - aos_unlock_bh(&ppe_vlan_vsi_lock[dev_id]); - - return SW_OK; - } - p_vsi_info = p_vsi_info->pNext; - } - } - aos_unlock_bh(&ppe_vlan_vsi_lock[dev_id]); - return SW_NOT_FOUND; -} - - -/*called when - 1. switchdev create physical interface for port - 2. add physical interface to a bridge*/ -sw_error_t -ppe_port_vsi_set(a_uint32_t dev_id, fal_port_t port_id, a_uint32_t vsi_id) -{ - sw_error_t rv = SW_OK; - - REF_DEV_ID_CHECK(dev_id); - SSDK_DEBUG("port %d, vsi %d\n", port_id, vsi_id); - if(!(FAL_IS_PPORT(port_id)) && !(FAL_IS_VPORT(port_id))) - return SW_BAD_VALUE; - - if(vsi_id > PPE_VSI_MAX){ - SSDK_ERROR("invalid VSI port %d, vsi %d\n", port_id, vsi_id); - return SW_BAD_VALUE; - } - - if(FAL_IS_PPORT(port_id)){ - rv = _ppe_port_vsi_mapping_update(dev_id, FAL_PORT_ID_VALUE(port_id), vsi_id); - if( rv != SW_OK ) - return rv; - } - return rv; -} - -sw_error_t -ppe_port_vsi_get(a_uint32_t dev_id, fal_port_t port_id, a_uint32_t *vsi_id) -{ - if(FAL_IS_PPORT(port_id)) - { - a_uint32_t i = 0; - for( i = 0; i <= PPE_VSI_MAX; i++ ) - { - if((ref_vsi_mapping[dev_id][i].valid != 0)&& - (ref_vsi_mapping[dev_id][i].pport_bitmap & (1 << port_id))) - { - *vsi_id = i; - SSDK_DEBUG("returned port %d, vsi %d\n", port_id, *vsi_id); - return SW_OK; - } - } - } - SSDK_ERROR("VSI is not configured on port %d\n", port_id); - return SW_NOT_FOUND; -} - -sw_error_t ppe_vsi_alloc(a_uint32_t dev_id, a_uint32_t *vsi) -{ - a_uint32_t vsi_id; - - REF_DEV_ID_CHECK(dev_id); - REF_NULL_POINT_CHECK(vsi); - SSDK_DEBUG("requesting vsi\n"); - - for( vsi_id = PPE_VSI_RESERVE_MAX+1; vsi_id <= PPE_VSI_MAX; vsi_id++ ) - { - if(ref_vsi_mapping[dev_id][vsi_id].valid == 0) - { - fal_vsi_newaddr_lrn_t newaddr_lrn; - fal_vsi_stamove_t stamove; - ref_vsi_mapping[dev_id][vsi_id].valid = 1; - ref_vsi_mapping[dev_id][vsi_id].pport_bitmap = 0; - ref_vsi_mapping[dev_id][vsi_id].pHead = NULL; - *vsi = vsi_id; - _ppe_vsi_member_init(dev_id, vsi_id); - newaddr_lrn.lrn_en = 1; - newaddr_lrn.action = 0; - fal_vsi_newaddr_lrn_set(dev_id, vsi_id, &newaddr_lrn); - stamove.stamove_en = 1; - stamove.action = 0; - fal_vsi_stamove_set(dev_id, vsi_id, &stamove); - SSDK_DEBUG("vsi %d allocated\n", *vsi); - return SW_OK; - } - } - - return SW_NO_RESOURCE; -} - -sw_error_t ppe_vsi_free(a_uint32_t dev_id, a_uint32_t vsi_id) -{ - ref_vlan_info_t *p_vsi_info = NULL; - REF_DEV_ID_CHECK(dev_id); - - if( vsi_id <= PPE_VSI_RESERVE_MAX || vsi_id > PPE_VSI_MAX ) - return SW_OUT_OF_RANGE; - - p_vsi_info = ref_vsi_mapping[dev_id][vsi_id].pHead; - while(p_vsi_info != NULL) - { - ref_vlan_info_t *ptemp = p_vsi_info; - p_vsi_info = p_vsi_info->pNext; - SSDK_DEBUG("port 0x%x svlan %d cvlan %d, vsi %d free vsi info\n", - ptemp->vport_bitmap, ptemp->stag_vid, ptemp->ctag_vid, vsi_id); - aos_mem_free(ptemp); - } - ref_vsi_mapping[dev_id][vsi_id].valid = 0; - ref_vsi_mapping[dev_id][vsi_id].pHead = NULL; - ref_vsi_mapping[dev_id][vsi_id].pport_bitmap = 0; - - SSDK_DEBUG("vsi %d released\n", vsi_id); - - return SW_OK; -} - -static void ppe_init_one_vsi(a_uint32_t dev_id, a_uint32_t vsi_id) -{ - if(ref_vsi_mapping[dev_id][vsi_id].valid == 0) - { - ref_vsi_mapping[dev_id][vsi_id].valid = 1; - ref_vsi_mapping[dev_id][vsi_id].pport_bitmap = 0; - ref_vsi_mapping[dev_id][vsi_id].pHead = NULL; - _ppe_vsi_member_init(dev_id, vsi_id); - } - - return; -} - -sw_error_t ppe_vsi_init(a_uint32_t dev_id) -{ - fal_port_t port_id; - fal_vsi_newaddr_lrn_t newaddr_lrn = {0}; - fal_vsi_stamove_t stamove = {0}; - - newaddr_lrn.action = 0; - newaddr_lrn.lrn_en = 1; - stamove.action = 0; - stamove.stamove_en = 1; - for(port_id = SSDK_PHYSICAL_PORT1; port_id <= SSDK_PHYSICAL_PORT7; port_id++) - { - ppe_init_one_vsi(dev_id, default_port_vsi[port_id-1]); - fal_vsi_newaddr_lrn_set(dev_id, default_port_vsi[port_id-1], &newaddr_lrn); - fal_vsi_stamove_set(dev_id, default_port_vsi[port_id-1], &stamove); - /*fal_port_vsi_set(0, port_id, default_port_vsi[port_id-1]);*/ - ppe_port_vsi_set(dev_id, port_id, default_port_vsi[port_id-1]); - } - - aos_lock_init(&ppe_vlan_vsi_lock[dev_id]); - - return SW_OK; -} - - -sw_error_t ppe_vsi_tbl_dump(a_uint32_t dev_id) -{ - a_uint32_t vsi_id; - ref_vlan_info_t *p_vsi_info = NULL; - - REF_DEV_ID_CHECK(dev_id); - printk("########Software VSI mapping table\n"); - for( vsi_id = 0; vsi_id <= PPE_VSI_MAX; vsi_id++ ) - { - if(ref_vsi_mapping[dev_id][vsi_id].valid == 0) - continue; - p_vsi_info = ref_vsi_mapping[dev_id][vsi_id].pHead; - printk("vsi %d, port bitmap 0x%x\n",vsi_id, ref_vsi_mapping[dev_id][vsi_id].pport_bitmap); - while(p_vsi_info != NULL) - { - printk("%8s svlan %d, cvlan %d, port bitmap 0x%x\n","", - p_vsi_info->stag_vid, p_vsi_info->ctag_vid, p_vsi_info->vport_bitmap); - p_vsi_info = p_vsi_info->pNext; - } - } - - return SW_OK; -} - -EXPORT_SYMBOL(ppe_port_vlan_vsi_set); -EXPORT_SYMBOL(ppe_port_vlan_vsi_get); -EXPORT_SYMBOL(ppe_port_vsi_set); -EXPORT_SYMBOL(ppe_port_vsi_get); -EXPORT_SYMBOL(ppe_vsi_alloc); -EXPORT_SYMBOL(ppe_vsi_free); - - diff --git a/feeds/ipq807x/qca-ssdk/src/src/sal/Makefile b/feeds/ipq807x/qca-ssdk/src/src/sal/Makefile deleted file mode 100755 index 805ae0f63..000000000 --- a/feeds/ipq807x/qca-ssdk/src/src/sal/Makefile +++ /dev/null @@ -1,12 +0,0 @@ -LOC_DIR=src/sal -LIB=SAL - -include $(PRJ_PATH)/make/config.mk - -SRC_LIST=$(wildcard *.c) - -include $(PRJ_PATH)/make/components.mk -include $(PRJ_PATH)/make/defs.mk -include $(PRJ_PATH)/make/target.mk - -all: dep obj diff --git a/feeds/ipq807x/qca-ssdk/src/src/sal/sd/Makefile b/feeds/ipq807x/qca-ssdk/src/src/sal/sd/Makefile deleted file mode 100755 index 74c50e2eb..000000000 --- a/feeds/ipq807x/qca-ssdk/src/src/sal/sd/Makefile +++ /dev/null @@ -1,12 +0,0 @@ -LOC_DIR=src/sal/sd -LIB=SAL - -include $(PRJ_PATH)/make/config.mk - -SRC_LIST=$(wildcard *.c) - -include $(PRJ_PATH)/make/components.mk -include $(PRJ_PATH)/make/defs.mk -include $(PRJ_PATH)/make/target.mk - -all: dep obj \ No newline at end of file diff --git a/feeds/ipq807x/qca-ssdk/src/src/sal/sd/linux/Makefile b/feeds/ipq807x/qca-ssdk/src/src/sal/sd/linux/Makefile deleted file mode 100755 index a038efc6d..000000000 --- a/feeds/ipq807x/qca-ssdk/src/src/sal/sd/linux/Makefile +++ /dev/null @@ -1,12 +0,0 @@ -LOC_DIR=src/sal/sd/linux -LIB=SAL - -include $(PRJ_PATH)/make/config.mk - -SRC_LIST=$(wildcard *.c) - -include $(PRJ_PATH)/make/components.mk -include $(PRJ_PATH)/make/defs.mk -include $(PRJ_PATH)/make/target.mk - -all: dep obj \ No newline at end of file diff --git a/feeds/ipq807x/qca-ssdk/src/src/sal/sd/linux/uk_interface/Makefile b/feeds/ipq807x/qca-ssdk/src/src/sal/sd/linux/uk_interface/Makefile deleted file mode 100755 index a4bac32fe..000000000 --- a/feeds/ipq807x/qca-ssdk/src/src/sal/sd/linux/uk_interface/Makefile +++ /dev/null @@ -1,34 +0,0 @@ -LOC_DIR=src/sal/sd/linux/uk_interface -LIB=SAL - -include $(PRJ_PATH)/make/config.mk - -SRC_LIST= - -ifeq (TRUE, $(UK_IF)) -ifeq (KSLIB, $(MODULE_TYPE)) - ifeq (TRUE, $(UK_NETLINK)) - SRC_LIST=sw_api_ks_netlink.c - endif - - ifeq (TRUE, $(UK_IOCTL)) - SRC_LIST=sw_api_ks_ioctl.c - endif -endif - -ifeq (USLIB, $(MODULE_TYPE)) - ifeq (TRUE, $(UK_NETLINK)) - SRC_LIST=sw_api_us_netlink.c - endif - - ifeq (TRUE, $(UK_IOCTL)) - SRC_LIST=sw_api_us_ioctl.c - endif -endif -endif - -include $(PRJ_PATH)/make/components.mk -include $(PRJ_PATH)/make/defs.mk -include $(PRJ_PATH)/make/target.mk - -all: dep obj \ No newline at end of file diff --git a/feeds/ipq807x/qca-ssdk/src/src/sal/sd/linux/uk_interface/sw_api_ks_ioctl.c b/feeds/ipq807x/qca-ssdk/src/src/sal/sd/linux/uk_interface/sw_api_ks_ioctl.c deleted file mode 100755 index 2988a6e33..000000000 --- a/feeds/ipq807x/qca-ssdk/src/src/sal/sd/linux/uk_interface/sw_api_ks_ioctl.c +++ /dev/null @@ -1,316 +0,0 @@ -/* - * Copyright (c) 2012, 2017-2018, The Linux Foundation. All rights reserved. - * Permission to use, copy, modify, and/or distribute this software for - * any purpose with or without fee is hereby granted, provided that the - * above copyright notice and this permission notice appear in all copies. - * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES - * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR - * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES - * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN - * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT - * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. - */ - - -#include "sw.h" -#include "sw_api.h" - -#ifdef KVER26 /*Linux Kernel 2.6 */ -#define __USER __user -#else /*Linux Kernel 2.4 */ -#include -#define __USER -#endif /*KVER26 */ - -#ifdef KVER34 -#include -#include -#include -#else -#include -#include -//#include -#endif - -#include -#include -#include -#include "api_access.h" -#include "sw_api_ks.h" -#ifdef KVER32 -#include -#include -#endif -#include -#include "ssdk_init.h" -#include "ssdk_plat.h" - -static int -switch_open(struct inode * inode,struct file * file); - -static int -switch_close(struct inode * inode, struct file * file); - - -#ifdef KVER32 //for linux3.2 -static long -switch_ioctl(struct file * file, unsigned int cmd, unsigned long arg); -#else -static long -switch_ioctl(struct inode *inode, struct file * file, unsigned int cmd, unsigned long arg); -#endif - -static unsigned long *cmd_buf = NULL; - -static struct mutex api_ioctl_lock; - -static struct file_operations switch_device_fops = -{ - .owner = THIS_MODULE, - .read = NULL, - .write = NULL, - .poll = NULL, - .unlocked_ioctl= switch_ioctl, - .open = switch_open, - .release = switch_close -}; - -#ifndef SHELL_DEV -#define SHELL_DEV "switch_ssdk" -#endif -static struct miscdevice switch_device = -{ - MISC_DYNAMIC_MINOR, - SHELL_DEV, - &switch_device_fops -}; - -static sw_error_t -input_parser(sw_api_param_t *p, a_uint32_t nr_param, unsigned long *args) -{ - a_uint32_t i = 0, buf_head = nr_param; - a_uint32_t offset = sizeof(unsigned long); - a_uint32_t credit = sizeof(unsigned long) - 1; - - for (i = 0; i < nr_param; i++) - { - if (p->param_type & SW_PARAM_PTR) - { - cmd_buf[i] = (unsigned long) & cmd_buf[buf_head]; - buf_head += (p->data_size + credit) / offset; - - if (buf_head > (SW_MAX_API_BUF / offset)) - { - SSDK_ERROR("Lengh of command is more than cmd buffer\n"); - return SW_NO_RESOURCE; - } - - if (p->param_type & SW_PARAM_IN) - { - if (copy_from_user((a_uint8_t*)(cmd_buf[i]), (void __USER *)args[i + 2], - ((p->data_size + credit) / offset) * offset)) - { - SSDK_ERROR("copy_from_user fail\n"); - return SW_NO_RESOURCE; - } - SSDK_DEBUG("Input parameter %d: ", i); - SSDK_DUMP_BUF(DEBUG, (unsigned long *)cmd_buf[i], - ((p->data_size + credit) / offset)); - } - } - else - { - cmd_buf[i] = args[i + 2]; - SSDK_DEBUG("Input parameter %d: %ld\n", i, cmd_buf[i]); - } - p++; - } - return SW_OK; -} - -static sw_error_t -output_parser(sw_api_param_t *p, a_uint32_t nr_param, unsigned long *args) -{ - a_uint32_t i =0; - a_uint32_t offset = sizeof(unsigned long); - a_uint32_t credit = sizeof(unsigned long) - 1; - - for (i = 0; i < nr_param; i++) - { - if (p->param_type & SW_PARAM_OUT) - { - SSDK_DEBUG("Output parameter %d: ", i); - SSDK_DUMP_BUF(DEBUG, (unsigned long *)cmd_buf[i], - ((p->data_size + credit) / offset)); - if (copy_to_user((void __USER *) args[i + 2], (unsigned long *) cmd_buf[i], - ((p->data_size + credit) / offset) * offset)) - { - SSDK_ERROR("copy_to_user fail\n"); - return SW_NO_RESOURCE; - } - } - p++; - } - - return SW_OK; -} - -static sw_error_t -sw_api_cmd(unsigned long * args) -{ - unsigned long *p = cmd_buf, api_id = args[0], nr_param = 0; - sw_error_t(*func) (unsigned long, ...); - sw_api_param_t *pp; - sw_api_func_t *fp; - sw_error_t rv; - sw_api_t sw_api; - - SSDK_DEBUG("api_id is %ld\n", api_id); - sw_api.api_id = api_id; - rv = sw_api_get(&sw_api); - SW_OUT_ON_ERROR(rv); - - fp = sw_api.api_fp; - pp = sw_api.api_pp; - nr_param = sw_api.api_nr; - - /* Clean up cmd_buf */ - aos_mem_set(cmd_buf, 0, SW_MAX_API_BUF); - rv = input_parser(pp, nr_param, args); - SW_OUT_ON_ERROR(rv); - func = fp->func; - - switch (nr_param) - { - case 1: - rv = (func) (p[0]); - break; - case 2: - rv = (func) (p[0], p[1]); - break; - case 3: - rv = (func) (p[0], p[1], p[2]); - break; - case 4: - rv = (func) (p[0], p[1], p[2], p[3]); - break; - case 5: - rv = (func) (p[0], p[1], p[2], p[3], p[4]); - break; - case 6: - rv = (func) (p[0], p[1], p[2], p[3], p[4], p[5]); - break; - case 7: - rv = (func) (p[0], p[1], p[2], p[3], p[4], p[5], p[6]); - break; - case 8: - rv = (func) (p[0], p[1], p[2], p[3], p[4], p[5], p[6], p[7]); - break; - case 9: - rv = (func) (p[0], p[1], p[2], p[3], p[4], p[5], p[6], p[7], p[8]); - break; - case 10: - rv = (func) (p[0], p[1], p[2], p[3], p[4], p[5], - p[6], p[7], p[8], p[9]); - break; - default: - rv = SW_OUT_OF_RANGE; - } - - SW_OUT_ON_ERROR(rv); - rv = output_parser(pp, nr_param, args); - -out: - return rv; -} - -static int -switch_open(struct inode * inode,struct file * file) -{ - return SW_OK; -} - -static int -switch_close(struct inode * inode, struct file * file) -{ - return SW_OK; -} - -#ifdef KVER32 -static long -switch_ioctl(struct file * file, unsigned int cmd, unsigned long arg) -#else -static long -switch_ioctl(struct inode *inode, struct file * file, unsigned int cmd, unsigned long arg) -#endif -{ - unsigned long args[SW_MAX_API_PARAM], rtn; - sw_error_t rv = SW_NO_RESOURCE; - void __user *argp = (void __user *)arg; - - SSDK_DEBUG("Recieved IOCTL call\n"); - if (copy_from_user(args, argp, sizeof (args))) - { - SSDK_ERROR("copy_from_user fail\n"); - return SW_NO_RESOURCE; - } - - mutex_lock(&api_ioctl_lock); - rv = sw_api_cmd(args); - mutex_unlock(&api_ioctl_lock); - - /* return API result to user */ - rtn = (unsigned long) rv; - if (copy_to_user - ((void __USER *) args[1], &rtn, sizeof (unsigned long))) - { - SSDK_ERROR("copy_to_user fail\n"); - rv = SW_NO_RESOURCE; - } - - return SW_OK; -} - -sw_error_t -sw_uk_init(a_uint32_t nl_prot) -{ - if (!cmd_buf) - { - if((cmd_buf = (unsigned long *) aos_mem_alloc(SW_MAX_API_BUF)) == NULL) - { - return SW_OUT_OF_MEM; - } - -#if defined UK_MINOR_DEV - switch_device.minor = UK_MINOR_DEV; -#else - switch_device.minor = nl_prot; -#endif - - if (misc_register(&switch_device)) - { - return SW_INIT_ERROR; - } - - mutex_init(&api_ioctl_lock); - } - - return SW_OK; -} - -sw_error_t -sw_uk_cleanup(void) -{ - if (cmd_buf) - { - aos_mem_free(cmd_buf); - cmd_buf = NULL; - - mutex_destroy(&api_ioctl_lock); - misc_deregister(&switch_device); - } - - return SW_OK; -} - diff --git a/feeds/ipq807x/qca-ssdk/src/src/sal/sd/linux/uk_interface/sw_api_ks_netlink.c b/feeds/ipq807x/qca-ssdk/src/src/sal/sd/linux/uk_interface/sw_api_ks_netlink.c deleted file mode 100755 index 3ad5da193..000000000 --- a/feeds/ipq807x/qca-ssdk/src/src/sal/sd/linux/uk_interface/sw_api_ks_netlink.c +++ /dev/null @@ -1,789 +0,0 @@ -/* - * Copyright (c) 2012, The Linux Foundation. All rights reserved. - * Permission to use, copy, modify, and/or distribute this software for - * any purpose with or without fee is hereby granted, provided that the - * above copyright notice and this permission notice appear in all copies. - * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES - * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR - * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES - * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN - * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT - * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. - */ - - - -#include "sw.h" -#include "sw_api.h" - -#ifdef KVER26 /*Linux Kernel 2.6 */ -#define __USER __user -#else /*Linux Kernel 2.4 */ -#include -#define __USER -#define CLONE_KERNEL (CLONE_FS | CLONE_FILES | CLONE_SIGHAND) -#define for_each_process(p) for_each_task(p) -#endif /*KVER26 */ -#include -#include -#include -#include -#include "api_access.h" -#include "sw_api_ks.h" - -#if 0 -#define dprintk(args...) aos_printk(args) -#else -#define dprintk(args...) -#endif - -/*configurable value for max creating request of kernel thread*/ -#define PID_THREADS_MAX 32 - -#define RSV_PID_LOC_0 (0) -#define RSV_PID_LOC_1 (1) - -#define PID_TAB_MAX PID_THREADS_MAX -#define PID_TAB_NOT_FOUND PID_TAB_MAX+1 - -static pid_t pid_parents[PID_TAB_MAX] = {0}; -static pid_t pid_childs[PID_TAB_MAX] = {0}; -static wait_queue_head_t pid_child_wait[PID_TAB_MAX]; -static struct semaphore pid_tab_sem; - -static unsigned long *cmd_buf = NULL; -static struct semaphore api_sem; -static struct sock *ssdk_nl_sk = NULL; -static struct sk_buff * skb_array[PID_TAB_MAX] = {0}; - -static sw_error_t -input_parser(sw_api_param_t *p, a_uint32_t nr_param, a_uint32_t *args) -{ - a_uint32_t i = 0, buf_head = nr_param; - - for (i = 0; i < nr_param; i++) - { - if (p->param_type & SW_PARAM_PTR) - { - cmd_buf[i] = (a_uint32_t) & cmd_buf[buf_head]; - buf_head += (p->data_size + 3) / 4; - - if (buf_head > (SW_MAX_API_BUF / 4)) - return SW_NO_RESOURCE; - - if (p->param_type & SW_PARAM_IN) - { - if (copy_from_user((a_uint8_t*)(cmd_buf[i]), (void __USER *)args[i + 2], ((p->data_size + 3) >> 2) << 2)) - return SW_NO_RESOURCE; - } - } - else - { - cmd_buf[i] = args[i + 2]; - } - p++; - } - return SW_OK; -} - -static sw_error_t -output_parser(sw_api_param_t *p, a_uint32_t nr_param, a_uint32_t *args) -{ - a_uint32_t i =0; - - for (i = 0; i < nr_param; i++) - { - if (p->param_type & SW_PARAM_OUT) - { - if (copy_to_user - ((void __USER *) args[i + 2], (a_uint32_t *) cmd_buf[i], ((p->data_size + 3) >> 2) << 2)) - return SW_NO_RESOURCE; - } - p++; - } - - return SW_OK; -} - -static sw_error_t -sw_api_cmd(a_uint32_t * args) -{ - a_uint32_t *p = cmd_buf, api_id = args[0], nr_param = 0; - sw_error_t(*func) (a_uint32_t, ...); - sw_api_param_t *pp; - sw_api_func_t *fp; - sw_error_t rv; - sw_api_t sw_api; - - down(&api_sem); - - sw_api.api_id = api_id; - rv = sw_api_get(&sw_api); - SW_OUT_ON_ERROR(rv); - - fp = sw_api.api_fp; - pp = sw_api.api_pp; - nr_param = sw_api.api_nr; - - rv = input_parser(pp, nr_param, args); - SW_OUT_ON_ERROR(rv); - func = fp->func; - - switch (nr_param) - { - case 1: - rv = (func) (p[0]); - break; - case 2: - rv = (func) (p[0], p[1]); - break; - case 3: - rv = (func) (p[0], p[1], p[2]); - break; - case 4: - rv = (func) (p[0], p[1], p[2], p[3]); - break; - case 5: - rv = (func) (p[0], p[1], p[2], p[3], p[4]); - break; - case 6: - rv = (func) (p[0], p[1], p[2], p[3], p[4], p[5]); - break; - case 7: - rv = (func) (p[0], p[1], p[2], p[3], p[4], p[5], p[6]); - break; - case 8: - rv = (func) (p[0], p[1], p[2], p[3], p[4], p[5], p[6], p[7]); - break; - case 9: - rv = (func) (p[0], p[1], p[2], p[3], p[4], p[5], p[6], p[7], p[8]); - break; - case 10: - rv = (func) (p[0], p[1], p[2], p[3], p[4], p[5], - p[6], p[7], p[8], p[9]); - break; - default: - rv = SW_OUT_OF_RANGE; - } - - SW_OUT_ON_ERROR(rv); - rv = output_parser(pp, nr_param, args); - -out: - up(&api_sem); - return rv; -} - -static inline int pid_find(pid_t pid, pid_t pids[]) -{ - a_uint32_t i, loc = PID_TAB_NOT_FOUND; - - for(i = 0; i< PID_TAB_MAX; i++) - { - if(pids[i] == pid) - { - loc = i; - break; - } - } - return loc; -} - -static inline a_bool_t pid_exit(pid_t parent_pid) -{ - struct task_struct *p; - a_bool_t rtn = A_TRUE; - - for_each_process(p) - { - if(parent_pid == p->pid) - { - rtn = A_FALSE; - break; - } - } - - return rtn; -} - -static inline void pid_free(a_uint32_t loc) -{ - if (down_interruptible(&pid_tab_sem)) - return; - - pid_childs[loc] = 0; - pid_parents[loc] = 0; - - up(&pid_tab_sem); -} - -static inline a_bool_t pid_full(void) -{ - return (pid_find(0, pid_parents) == PID_TAB_NOT_FOUND)?A_TRUE:A_FALSE; -} - -static a_uint32_t pid_find_save (pid_t parent_pid, pid_t child_pid) -{ - a_uint32_t loc = PID_TAB_NOT_FOUND; - - if(!parent_pid && !child_pid) - { - dprintk("child and father can't both zero\n"); - return loc; - } - - if (down_interruptible(&pid_tab_sem)) - return loc; - - if(!parent_pid) - { - /*find locate by child_pid*/ - loc = pid_find(child_pid, pid_childs); - - } - else - { - /*find locate by parent_pid*/ - loc = pid_find(parent_pid, pid_parents); - - if(child_pid) - { - loc = pid_find(0, pid_parents); - - if(loc != PID_TAB_NOT_FOUND) - { - pid_childs[loc] = child_pid; - pid_parents[loc] = parent_pid; - } - } - } - - up(&pid_tab_sem); - return loc; -} - -#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,22) -static void -sw_api_excep_ack(struct sock *sk, pid_t pid) -{ - sw_error_t rv = SW_NO_RESOURCE; - a_uint32_t args[SW_MAX_API_PARAM], rtn; - struct sk_buff *skb, *skb_first = NULL; - struct nlmsghdr *nlh = NULL; - - while(1) - { -#ifdef KVER26 - skb = skb_dequeue(&sk->sk_receive_queue); -#else - skb = skb_dequeue(&sk->receive_queue); -#endif - if (!skb) - { - dprintk("pid error: skb = null\n"); - return; - } - - nlh = (struct nlmsghdr *)skb->data; - if (!nlh) - { - dprintk("pid error: nlh = null\n"); - return; - } - - if(nlh->nlmsg_pid == pid) - { - break; - } - - if(!skb_first) - { - skb_first = skb; - } - else if (skb_first == skb) - { - dprintk("can't found my skb???\n"); - return; - } - -#ifdef KVER26 - skb_queue_tail(&sk->sk_receive_queue, skb); -#else - skb_queue_tail(&sk->receive_queue, skb); -#endif - } - - if(nlh->nlmsg_len < (SW_MAX_PAYLOAD + sizeof(nlmsghdr))) - { - dprintk("data length is less than %d bytes\n", SW_MAX_PAYLOAD); - SW_OUT_ON_ERROR(SW_ABORTED); - } - aos_mem_copy(args, NLMSG_DATA(nlh), SW_MAX_PAYLOAD); - /* return API result to user */ - rtn = (a_uint32_t) rv; - if (copy_to_user - ((void __USER *) args[1], (a_uint32_t *) & rtn, sizeof (a_uint32_t))) - { - rv = SW_NO_RESOURCE; - } - - NETLINK_CB(skb).pid = 0; - NETLINK_CB(skb).dst_pid = nlh->nlmsg_pid; -#ifdef KVER26 - NETLINK_CB(skb).dst_group = 0; -#else - NETLINK_CB(skb).dst_groups = 0; -#endif - - netlink_unicast(sk, skb, nlh->nlmsg_pid, MSG_DONTWAIT); -} - -static void -sw_api_exec(struct sock *sk, pid_t pid) -{ - sw_error_t rv = SW_NO_RESOURCE; - a_uint32_t args[SW_MAX_API_PARAM], rtn; - struct sk_buff *skb, *skb_first = NULL; - struct nlmsghdr *nlh = NULL; - - while(1) - { -#ifdef KVER26 - skb = skb_dequeue(&sk->sk_receive_queue); -#else - skb = skb_dequeue(&sk->receive_queue); -#endif - if (!skb) - { - dprintk("pid error: skb = null\n"); - return; - } - - nlh = (struct nlmsghdr *)skb->data; - if (!nlh) - { - dprintk("pid error: nlh = null\n"); - return; - } - - if(nlh->nlmsg_pid == pid) - { - break; - } - - if(!skb_first) - { - skb_first = skb; - } - else if (skb_first == skb) - { - dprintk("can't found my skb???\n"); - return; - } - -#ifdef KVER26 - skb_queue_tail(&sk->sk_receive_queue, skb); -#else - skb_queue_tail(&sk->receive_queue, skb); -#endif - } - - if(nlh->nlmsg_len < (SW_MAX_PAYLOAD + sizeof(nlmsghdr))) - { - dprintk("data length is less than %d bytes\n", SW_MAX_PAYLOAD); - SW_OUT_ON_ERROR(SW_ABORTED); - } - aos_mem_copy(args, NLMSG_DATA(nlh), SW_MAX_PAYLOAD); - - rv = sw_api_cmd(args); - /* return API result to user */ - rtn = (a_uint32_t) rv; - if (copy_to_user - ((void __USER *) args[1], (a_uint32_t *) & rtn, sizeof (a_uint32_t))) - { - rv = SW_NO_RESOURCE; - } - - NETLINK_CB(skb).pid = 0; - NETLINK_CB(skb).dst_pid = nlh->nlmsg_pid; -#ifdef KVER26 - NETLINK_CB(skb).dst_group = 0; -#else - NETLINK_CB(skb).dst_groups = 0; -#endif - - netlink_unicast(sk, skb, nlh->nlmsg_pid, MSG_DONTWAIT); -} - - -static int sw_api_thread(void *sk) -{ - a_uint32_t loc, i; - pid_t parent_pid = 0, child_pid = current->pid; - - while ((loc = pid_find_save(parent_pid, child_pid)) == PID_TAB_NOT_FOUND) - schedule_timeout(1*HZ); - - parent_pid = pid_parents[loc]; - dprintk("thread child [%d] find parent [%d] at %d \n", child_pid, parent_pid, loc); - - if ((RSV_PID_LOC_0 == loc) || (RSV_PID_LOC_1 == loc)) - { - for(i=0; ; i++) - { - if(i && !sleep_on_timeout(&pid_child_wait[loc], (5*HZ))) - { - if(pid_exit(parent_pid) == A_FALSE) - continue; - - pid_free(loc); - dprintk("thread child[%d] exit!\n", child_pid); - return 0; - } - - sw_api_exec(sk, parent_pid); - } - } - else - { - sw_api_exec(sk, parent_pid); - pid_free(loc); - } - - return 0; -} - -static void -sw_api_netlink(struct sock *sk, int len) -{ - pid_t parent_pid = current->pid, child_pid = 0; - a_uint32_t loc = pid_find_save (parent_pid, child_pid); - - if(loc == PID_TAB_NOT_FOUND) - { - if(pid_full()) - { - dprintk("###threads exceed the max [%d] for pid [%d]!###\n", PID_TAB_MAX, parent_pid); - sw_api_excep_ack(sk, parent_pid); - return; - } -#if 1 - struct task_struct *p; - p = kthread_create(sw_api_thread, (void *)ssdk_nl_sk, "netlink_child"); - if (IS_ERR(p)) - { - dprintk("thread can't be created for netlink\n"); - return; - } - child_pid = p->pid; -#else - if ((child_pid = kernel_thread(sw_api_thread, ssdk_nl_sk, CLONE_KERNEL)) < 0) - { - dprintk("thread can't be created for netlink\n"); - return; - } -#endif - dprintk("[%d] create child [%d] at %d\n", parent_pid, child_pid, loc); - pid_find_save(parent_pid, child_pid); - wake_up_process(p); - } - else - { - dprintk("[%d] wake up child [%d] at %d\n", parent_pid, pid_childs[loc], loc); - wake_up(&pid_child_wait[loc]); - } - - return; - -} - -#else - -static void -sw_api_excep_ack_26_22(struct sk_buff *skb) -{ - sw_error_t rv = SW_NO_RESOURCE; - a_uint32_t args[SW_MAX_API_PARAM], rtn, size, dst_pid; - struct nlmsghdr *nlh = NULL; - struct sk_buff *rep; - - nlh = (struct nlmsghdr *)skb->data; - if (!nlh) - { - dprintk("pid error: nlh = null\n"); - return; - } - dst_pid = nlh->nlmsg_pid; - - if(nlh->nlmsg_len < (SW_MAX_PAYLOAD + sizeof(nlmsghdr))) - { - dprintk("data length is less than %d bytes\n", SW_MAX_PAYLOAD); - SW_OUT_ON_ERROR(SW_ABORTED); - } - aos_mem_copy(args, NLMSG_DATA(nlh), SW_MAX_PAYLOAD); - /* return API result to user */ - rtn = (a_uint32_t) rv; - if (copy_to_user - ((void __USER *) args[1], (a_uint32_t *) & rtn, sizeof (a_uint32_t))) - { - rv = SW_NO_RESOURCE; - } - - size = NLMSG_SPACE(0); - rep = alloc_skb(size, GFP_ATOMIC); - if (!rep) - { - dprintk("reply socket buffer allocation error... \n"); - return; - } - nlh = nlmsg_put(rep, 0, 0, 0, 0, 0); - - NETLINK_CB(rep).pid = 0; - NETLINK_CB(rep).dst_group = 0; - netlink_unicast(ssdk_nl_sk, rep, dst_pid, MSG_DONTWAIT); -} - -static void -sw_api_exec_26_22(pid_t parent_pid) -{ - sw_error_t rv = SW_NO_RESOURCE; - a_uint32_t loc, args[SW_MAX_API_PARAM], rtn, skblen, nlmsglen, size, dst_pid; - struct nlmsghdr *nlh = NULL; - struct sk_buff *skb; - struct sk_buff *rep; - - loc = pid_find(parent_pid, pid_parents); - if (PID_TAB_NOT_FOUND == loc) - { - dprintk("parent PID not found - (%d)\n", parent_pid); - return; - } - - skb = skb_array[loc]; - if (!skb) - { - dprintk("skb null pointer error\n"); - return; - } - - skblen = skb->len; - if (skb->len < sizeof(nlh)) - { - dprintk("skb len error - (%d)\n", skb->len); - SW_OUT_ON_ERROR(SW_ABORTED); - } - - nlh = (struct nlmsghdr *)skb->data; - if (!nlh) - { - dprintk("pid error: nlh = null\n"); - SW_OUT_ON_ERROR(SW_ABORTED); - } - - nlmsglen = nlh->nlmsg_len; - if (nlmsglen < sizeof(*nlh) || skblen < nlmsglen) - { - dprintk("nlmsglen error - (%d)\n", nlmsglen); - SW_OUT_ON_ERROR(SW_ABORTED); - } - dst_pid = nlh->nlmsg_pid; - - if(nlmsglen < (SW_MAX_PAYLOAD + sizeof(nlmsghdr))) - { - dprintk("data length is less than %d bytes\n", SW_MAX_PAYLOAD); - SW_OUT_ON_ERROR(SW_ABORTED); - } - aos_mem_copy(args, NLMSG_DATA(nlh), SW_MAX_PAYLOAD); - rv = sw_api_cmd(args); - - /* return API result to user */ - rtn = (a_uint32_t) rv; - if (copy_to_user - ((void __USER *) args[1], (a_uint32_t *) & rtn, sizeof (a_uint32_t))) - { - rv = SW_NO_RESOURCE; - } - - size = NLMSG_SPACE(0); - rep = alloc_skb(size, GFP_ATOMIC); - if (!rep) - { - dprintk("reply socket buffer allocation error... \n"); - SW_OUT_ON_ERROR(SW_ABORTED); - } - nlh = nlmsg_put(rep, 0, 0, 0, 0, 0); - - NETLINK_CB(rep).pid = 0; - NETLINK_CB(rep).dst_group = 0; - netlink_unicast(ssdk_nl_sk, rep, dst_pid, MSG_DONTWAIT); - -out: - skb_array[loc] = NULL; - kfree_skb(skb); -} - -static int -sw_api_thread_26_22(void * data) -{ - a_uint32_t loc, i; - pid_t parent_pid = 0, child_pid = current->pid; - - while ((loc = pid_find_save(parent_pid, child_pid)) == PID_TAB_NOT_FOUND) - schedule_timeout(1*HZ); - - parent_pid = pid_parents[loc]; - dprintk("thread child [%d] find parent [%d] at %d \n", child_pid, parent_pid, loc); - - if ((RSV_PID_LOC_0 == loc) || (RSV_PID_LOC_1 == loc)) - { - for(i=0; ; i++) - { - if(i && !sleep_on_timeout(&pid_child_wait[loc], (5*HZ))) - { - if(pid_exit(parent_pid) == A_FALSE) - continue; - - pid_free(loc); - dprintk("thread child[%d] exit!\n", child_pid); - return 0; - } - - sw_api_exec_26_22(parent_pid); - } - } - else - { - sw_api_exec_26_22(parent_pid); - pid_free(loc); - } - - return 0; -} - -static void -sw_api_netlink_26_22(struct sk_buff *skb) -{ - pid_t parent_pid = current->pid, child_pid = 0; - a_uint32_t loc = pid_find_save (parent_pid, child_pid); - - if(loc == PID_TAB_NOT_FOUND) - { - if(pid_full()) - { - dprintk("###threads exceed the max [%d] for pid [%d]!###\n", PID_TAB_MAX, parent_pid); - sw_api_excep_ack_26_22(skb); - return; - } - - loc = pid_find_save(parent_pid, 0xffffffff); - -#if 1 - struct task_struct *p; - p = kthread_create(sw_api_thread_26_22, (void *)ssdk_nl_sk, "netlink_child"); - if (IS_ERR(p)) - { - dprintk("thread can't be created for netlink\n"); - return; - } - - skb_array[loc] = skb_get(skb); - child_pid = p->pid; - pid_childs[loc] = child_pid; - wake_up_process(p); -#else - if ((child_pid = kernel_thread(sw_api_thread_26_22, NULL, CLONE_KERNEL)) < 0) - { - dprintk("thread can't be created for netlink\n"); - return; - } -#endif - dprintk("[%d] create child [%d] at %d\n", parent_pid, child_pid, loc); - } - else - { - dprintk("[%d] wake up child [%d] at %d\n", parent_pid, pid_childs[loc], loc); - skb_array[loc] = skb_get(skb); - wake_up(&pid_child_wait[loc]); - } - - return; -} -#endif - -sw_error_t -sw_uk_init(a_uint32_t nl_prot) -{ - a_uint32_t i, protocol; - - if (!cmd_buf) - { - if((cmd_buf = (a_uint32_t *) aos_mem_alloc(SW_MAX_API_BUF)) == NULL) - return SW_OUT_OF_MEM; - } - - if (!ssdk_nl_sk) - { -#if defined UK_NL_PROT - protocol = UK_NL_PROT; -#else - protocol = nl_prot; -#endif - -#ifdef KVER26 -#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,22) - ssdk_nl_sk = netlink_kernel_create(&init_net, protocol, 0, sw_api_netlink_26_22, NULL, THIS_MODULE); -#else - ssdk_nl_sk = netlink_kernel_create(protocol, 0, sw_api_netlink, THIS_MODULE); -#endif -#else - ssdk_nl_sk = netlink_kernel_create(protocol, sw_api_netlink); -#endif - if (!ssdk_nl_sk) - { - dprintk("netlink_kernel_create fail at nl_prot:[%d]\n", protocol); - return SW_NO_RESOURCE; - } - else - { -#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,22) - dprintk("netlink_kernel_create succeeded at nl_prot: [%d] (>2.6.22)\n", protocol); -#else - dprintk("netlink_kernel_create succeeded at nl_prot: [%d] (<2.6.22)\n", protocol); -#endif - } - } - - init_MUTEX(&pid_tab_sem); - init_MUTEX(&api_sem); - - for(i = 0; i < PID_TAB_MAX; i++) - { - init_waitqueue_head(&pid_child_wait[i]); - } - - return SW_OK; -} - -sw_error_t -sw_uk_cleanup(void) -{ - if (cmd_buf) - { - aos_mem_free(cmd_buf); - cmd_buf = NULL; - } - - if (ssdk_nl_sk) - { -#ifdef KVER26 - sock_release(ssdk_nl_sk->sk_socket); -#else - sock_release(ssdk_nl_sk->socket); -#endif - ssdk_nl_sk = NULL; - } - - return SW_OK; -} - diff --git a/feeds/ipq807x/qca-ssdk/src/src/sal/sd/sd.c b/feeds/ipq807x/qca-ssdk/src/src/sal/sd/sd.c deleted file mode 100755 index 39c053037..000000000 --- a/feeds/ipq807x/qca-ssdk/src/src/sal/sd/sd.c +++ /dev/null @@ -1,371 +0,0 @@ -/* - * Copyright (c) 2012, 2017-2018, The Linux Foundation. All rights reserved. - * Permission to use, copy, modify, and/or distribute this software for - * any purpose with or without fee is hereby granted, provided that the - * above copyright notice and this permission notice appear in all copies. - * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES - * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR - * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES - * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN - * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT - * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. - */ - -/*qca808x_start*/ -#include "sw.h" -#include "ssdk_init.h" -#include "sd.h" -#include "sw_api.h" -#if ((!defined(KERNEL_MODULE)) && defined(UK_IF)) -#include "sw_api_us.h" -#endif - -mdio_reg_set ssdk_mdio_set = NULL; -mdio_reg_get ssdk_mdio_get = NULL; -i2c_reg_set ssdk_i2c_set = NULL; -i2c_reg_get ssdk_i2c_get = NULL; -/*qca808x_end*/ -hdr_reg_set ssdk_hdr_reg_set = NULL; -hdr_reg_get ssdk_hdr_reg_get = NULL; -psgmii_reg_set ssdk_psgmii_reg_set = NULL; -psgmii_reg_get ssdk_psgmii_reg_get = NULL; -uniphy_reg_set ssdk_uniphy_reg_set = NULL; -uniphy_reg_get ssdk_uniphy_reg_get = NULL; -mii_reg_set ssdk_mii_reg_set = NULL; -mii_reg_get ssdk_mii_reg_get = NULL; - -/*qca808x_start*/ -sw_error_t -sd_reg_mdio_set(a_uint32_t dev_id, a_uint32_t phy, a_uint32_t reg, - a_uint16_t data) -{ - sw_error_t rv = SW_OK; - - if (NULL != ssdk_mdio_set) - { - rv = ssdk_mdio_set(dev_id, phy, reg, data); - } - else - { -#if ((!defined(KERNEL_MODULE)) && defined(UK_IF)) - { - a_uint32_t args[SW_MAX_API_PARAM]; - - args[0] = SW_API_PHY_SET; - args[1] = (a_uint32_t) & rv; - args[2] = dev_id; - args[3] = phy; - args[4] = reg; - args[5] = data; - if (SW_OK != sw_uk_if(args)) - { - return SW_FAIL; - } - } -#else - return SW_NOT_SUPPORTED; -#endif - } - - return rv; -} - -sw_error_t -sd_reg_mdio_get(a_uint32_t dev_id, a_uint32_t phy, a_uint32_t reg, a_uint16_t * data) -{ - sw_error_t rv = SW_OK; - - if (NULL != ssdk_mdio_get) - { - rv = ssdk_mdio_get(dev_id, phy, reg, data); - } - else - { -#if ((!defined(KERNEL_MODULE)) && defined(UK_IF)) - { - a_uint32_t args[SW_MAX_API_PARAM]; - a_uint32_t tmp; - - args[0] = SW_API_PHY_GET; - args[1] = (a_uint32_t) & rv; - args[2] = dev_id; - args[3] = phy; - args[4] = reg; - args[5] = (a_uint32_t) & tmp; - if (SW_OK != sw_uk_if(args)) - { - return SW_FAIL; - } - *data = *((a_uint16_t *)&tmp); - } -#else - return SW_NOT_SUPPORTED; -#endif - } - - return rv; -} - -sw_error_t -sd_reg_i2c_set(a_uint32_t dev_id, a_uint32_t phy, a_uint32_t reg, - a_uint16_t data) -{ - sw_error_t rv = SW_OK; - - if (NULL != ssdk_i2c_set) - { - rv = ssdk_i2c_set(dev_id, phy, reg, data); - } - else - { -#if ((!defined(KERNEL_MODULE)) && defined(UK_IF)) - { - a_uint32_t args[SW_MAX_API_PARAM]; - - args[0] = SW_API_PHY_I2C_SET; - args[1] = (a_uint32_t) & rv; - args[2] = dev_id; - args[3] = phy; - args[4] = reg; - args[5] = data; - if (SW_OK != sw_uk_if(args)) - { - return SW_FAIL; - } - } -#else - return SW_NOT_SUPPORTED; -#endif - } - - return rv; -} - -sw_error_t -sd_reg_i2c_get(a_uint32_t dev_id, a_uint32_t phy, a_uint32_t reg, a_uint16_t * data) -{ - sw_error_t rv = SW_OK; - - if (NULL != ssdk_i2c_get) - { - rv = ssdk_i2c_get(dev_id, phy, reg, data); - } - else - { -#if ((!defined(KERNEL_MODULE)) && defined(UK_IF)) - { - a_uint32_t args[SW_MAX_API_PARAM]; - a_uint32_t tmp; - - args[0] = SW_API_PHY_I2C_GET; - args[1] = (a_uint32_t) & rv; - args[2] = dev_id; - args[3] = phy; - args[4] = reg; - args[5] = (a_uint32_t) & tmp; - if (SW_OK != sw_uk_if(args)) - { - return SW_FAIL; - } - *data = *((a_uint16_t *)&tmp); - } -#else - return SW_NOT_SUPPORTED; -#endif - } - - return rv; -} -/*qca808x_end*/ -sw_error_t -sd_reg_hdr_set(a_uint32_t dev_id, a_uint32_t reg_addr, a_uint8_t * reg_data, a_uint32_t len) -{ - sw_error_t rv; - - if (NULL != ssdk_hdr_reg_set) - { - rv = ssdk_hdr_reg_set(dev_id, reg_addr, reg_data, len); - } - else - { - return SW_NOT_SUPPORTED; - } - - return rv; -} - -sw_error_t -sd_reg_hdr_get(a_uint32_t dev_id, a_uint32_t reg_addr, a_uint8_t * reg_data, a_uint32_t len) -{ - sw_error_t rv; - - if (NULL != ssdk_hdr_reg_get) - { - rv = ssdk_hdr_reg_get(dev_id, reg_addr, reg_data, len); - } - else - { - return SW_NOT_SUPPORTED; - } - - return rv; -} - -sw_error_t -sd_reg_psgmii_set(a_uint32_t dev_id, a_uint32_t reg_addr, a_uint8_t * reg_data, a_uint32_t len) -{ - sw_error_t rv; - - if (NULL != ssdk_psgmii_reg_set) - { - rv = ssdk_psgmii_reg_set(dev_id, reg_addr, reg_data, len); - } - else - { - return SW_NOT_SUPPORTED; - } - - return rv; -} - -sw_error_t -sd_reg_psgmii_get(a_uint32_t dev_id, a_uint32_t reg_addr, a_uint8_t * reg_data, a_uint32_t len) -{ - sw_error_t rv; - - if (NULL != ssdk_psgmii_reg_get) - { - rv = ssdk_psgmii_reg_get(dev_id, reg_addr, reg_data, len); - } - else - { - return SW_NOT_SUPPORTED; - } - - return rv; -} - -sw_error_t -sd_reg_uniphy_set(a_uint32_t dev_id, a_uint32_t index, a_uint32_t reg_addr, - a_uint8_t * reg_data, a_uint32_t len) -{ - sw_error_t rv; - - if (NULL != ssdk_uniphy_reg_set) - { - rv = ssdk_uniphy_reg_set(dev_id, index, reg_addr, reg_data, len); - } - else - { - return SW_NOT_SUPPORTED; - } - - return rv; -} - -sw_error_t -sd_reg_uniphy_get(a_uint32_t dev_id, a_uint32_t index, a_uint32_t reg_addr, - a_uint8_t * reg_data, a_uint32_t len) -{ - sw_error_t rv; - - if (NULL != ssdk_uniphy_reg_get) - { - rv = ssdk_uniphy_reg_get(dev_id, index, reg_addr, reg_data, len); - } - else - { - return SW_NOT_SUPPORTED; - } - - return rv; -} - -void -sd_reg_mii_set(a_uint32_t dev_id, a_uint32_t reg, a_uint32_t val) -{ - if (NULL != ssdk_mii_reg_set) - { - ssdk_mii_reg_set(dev_id, reg, val); - } -} - -a_uint32_t -sd_reg_mii_get(a_uint32_t dev_id, a_uint32_t reg) -{ - a_uint32_t value = 0; - - if (NULL != ssdk_mii_reg_get) - { - value = ssdk_mii_reg_get(dev_id, reg); - } - - return value; -} -/*qca808x_start*/ -sw_error_t -sd_init(a_uint32_t dev_id, ssdk_init_cfg * cfg) -{ - if (NULL != cfg->reg_func.mdio_set) - { - ssdk_mdio_set = cfg->reg_func.mdio_set; - } - - if (NULL != cfg->reg_func.mdio_get) - { - ssdk_mdio_get = cfg->reg_func.mdio_get; - } - - if (NULL != cfg->reg_func.i2c_set) - { - ssdk_i2c_set = cfg->reg_func.i2c_set; - } - - if (NULL != cfg->reg_func.i2c_get) - { - ssdk_i2c_get = cfg->reg_func.i2c_get; - } -/*qca808x_end*/ - if (NULL != cfg->reg_func.header_reg_set) - { - ssdk_hdr_reg_set = cfg->reg_func.header_reg_set; - } - - if (NULL != cfg->reg_func.header_reg_get) - { - ssdk_hdr_reg_get = cfg->reg_func.header_reg_get; - } - - if (NULL != cfg->reg_func.psgmii_reg_set) - { - ssdk_psgmii_reg_set = cfg->reg_func.psgmii_reg_set; - } - - if (NULL != cfg->reg_func.psgmii_reg_get) - { - ssdk_psgmii_reg_get = cfg->reg_func.psgmii_reg_get; - } - if (NULL != cfg->reg_func.uniphy_reg_set) - { - ssdk_uniphy_reg_set = cfg->reg_func.uniphy_reg_set; - } - - if (NULL != cfg->reg_func.uniphy_reg_get) - { - ssdk_uniphy_reg_get = cfg->reg_func.uniphy_reg_get; - } - - if (NULL != cfg->reg_func.mii_reg_set) - { - ssdk_mii_reg_set = cfg->reg_func.mii_reg_set; - } - - if (NULL != cfg->reg_func.mii_reg_get) - { - ssdk_mii_reg_get = cfg->reg_func.mii_reg_get; - } -/*qca808x_start*/ - return SW_OK; -} -/*qca808x_end*/ diff --git a/feeds/ipq807x/qca-ssdk/src/src/shell_lib/Makefile b/feeds/ipq807x/qca-ssdk/src/src/shell_lib/Makefile deleted file mode 100755 index 2336b4f98..000000000 --- a/feeds/ipq807x/qca-ssdk/src/src/shell_lib/Makefile +++ /dev/null @@ -1,12 +0,0 @@ -LOC_DIR=src/shell_lib -LIB=SHELIB - -include $(PRJ_PATH)/make/config.mk - -SRC_LIST=$(wildcard *.c) - -include $(PRJ_PATH)/make/components.mk -include $(PRJ_PATH)/make/defs.mk -include $(PRJ_PATH)/make/target.mk - -all: dep obj \ No newline at end of file diff --git a/feeds/ipq807x/qca-ssdk/src/src/shell_lib/shell.c b/feeds/ipq807x/qca-ssdk/src/src/shell_lib/shell.c deleted file mode 100755 index e0912561f..000000000 --- a/feeds/ipq807x/qca-ssdk/src/src/shell_lib/shell.c +++ /dev/null @@ -1,555 +0,0 @@ -/* - * Copyright (c) 2013, 2017, The Linux Foundation. All rights reserved. - * - * Permission to use, copy, modify, and/or distribute this software for any - * purpose with or without fee is hereby granted, provided that the above - * copyright notice and this permission notice appear in all copies. - * - * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES - * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR - * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES - * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN - * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF - * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. - */ - -#include "shell.h" -#include "shell_io.h" -#include "shell_sw.h" -#include "shell_config.h" -#include "api_access.h" - -unsigned long ioctl_buf[IOCTL_BUF_SIZE]; -unsigned long ioctl_argp[CMDSTR_ARGS_MAX*4]; - -void -cmd_print_error(sw_error_t rtn) -{ - -} - -void -cmd_print(char *fmt, ...) -{ - -} - -static sw_error_t -cmd_input_parser(unsigned long *arg_val, a_uint32_t arg_index, sw_api_param_t *pp) -{ - a_int16_t i; - unsigned long *pbuf; - a_uint16_t rtn_size = 1; - sw_api_param_t *pptmp = NULL;; - - pbuf = ioctl_buf + rtn_size; /*reserve for return value */ - - for (i = 0; i < arg_index; i++) - { - pptmp = pp + i; - if (pptmp->param_type & SW_PARAM_PTR) - { - pbuf += (pptmp->data_size + 3) / 4; - } - } - - if (pptmp == NULL) - return SW_BAD_PTR; - - if ((pbuf - ioctl_buf + (pptmp->data_size + 3) / 4) > (IOCTL_BUF_SIZE/4)) - { - return SW_NO_RESOURCE; - } - - *arg_val = (unsigned long) pbuf; - - return SW_OK; -} - -static sw_error_t -cmd_api_func(sw_api_func_t *fp, a_uint32_t nr_param, unsigned long * args) -{ - unsigned long *p = &args[2]; - sw_error_t rv; - - switch (nr_param) - { - case 0: - { - sw_error_t(*func) (void); - func = fp->func; - rv = (func) (); - break; - } - case 1: - { - sw_error_t(*func1) (unsigned long); - func1 = fp->func; - rv = (func1) (p[0]); - break; - } - case 2: - { - sw_error_t(*func2) (unsigned long, unsigned long); - func2 = fp->func; - rv = (func2) (p[0], p[1]); - break; - } - case 3: - { - sw_error_t(*func3) (unsigned long, unsigned long, unsigned long); - func3 = fp->func; - rv = (func3) (p[0], p[1], p[2]); - break; - } - case 4: - { - sw_error_t(*func4) (unsigned long, unsigned long, unsigned long, \ - unsigned long); - func4 = fp->func; - rv = (func4) (p[0], p[1], p[2], p[3]); - break; - } - case 5: - { - sw_error_t(*func5) (unsigned long, unsigned long, unsigned long, \ - unsigned long, unsigned long); - func5 = fp->func; - rv = (func5) (p[0], p[1], p[2], p[3], p[4]); - break; - } - case 6: - { - sw_error_t(*func6) (unsigned long, unsigned long, unsigned long, \ - unsigned long, unsigned long, unsigned long); - func6 = fp->func; - rv = (func6) (p[0], p[1], p[2], p[3], p[4], p[5]); - break; - } - case 7: - { - sw_error_t(*func7) (unsigned long, unsigned long, unsigned long, \ - unsigned long, unsigned long, unsigned long, unsigned long); - func7 = fp->func; - rv = (func7) (p[0], p[1], p[2], p[3], p[4], p[5], p[6]); - break; - } - case 8: - { - sw_error_t(*func8) (unsigned long, unsigned long, unsigned long, \ - unsigned long, unsigned long, unsigned long, unsigned long, \ - unsigned long); - func8 = fp->func; - rv = (func8) (p[0], p[1], p[2], p[3], p[4], p[5], p[6], p[7]); - break; - } - case 9: - { - sw_error_t(*func9) (unsigned long, unsigned long, unsigned long, \ - unsigned long, unsigned long, unsigned long, unsigned long, \ - unsigned long, unsigned long); - func9 = fp->func; - rv = (func9) (p[0], p[1], p[2], p[3], p[4], p[5], p[6], p[7], p[8]); - break; - } - case 10: - { - sw_error_t(*func10) (unsigned long, unsigned long, unsigned long, \ - unsigned long, unsigned long, unsigned long, unsigned long, \ - unsigned long, unsigned long, unsigned long); - func10 = fp->func; - rv = (func10) (p[0], p[1], p[2], p[3], p[4], p[5], - p[6], p[7], p[8], p[9]); - break; - } - default: - rv = SW_OUT_OF_RANGE; - } - - *(unsigned long *) args[1] = rv; - - return rv; -} -#if 0 -static sw_error_t -cmd_api_output(sw_api_param_t *pp, a_uint32_t nr_param, a_uint32_t * args) -{ - a_uint16_t i; - a_uint32_t *pbuf; - a_uint16_t rtn_size = 1; - sw_error_t rtn = (sw_error_t) (*ioctl_buf); - sw_api_param_t *pptmp = NULL; - - if (rtn != SW_OK) - { - cmd_print_error(rtn); - return rtn; - } - - pbuf = ioctl_buf + rtn_size; - for (i = 0; i < nr_param; i++) - { - pptmp = pp + i; - if (pptmp->param_type & SW_PARAM_PTR) - { - - if (pptmp->param_type & SW_PARAM_OUT) - { - - sw_data_type_t *data_type; - if (!(data_type = cmd_data_type_find(pptmp->data_type))) - return SW_NO_SUCH; - - if (data_type->show_func) - { - data_type->show_func(pptmp->param_name, pbuf, pptmp->data_size); - } - else - { - dprintf("\n Error, not define output print function!"); - } - } - - if ((pbuf - ioctl_buf + - (pptmp->data_size + 3) / 4) > (IOCTL_BUF_SIZE/4)) - return SW_NO_RESOURCE; - - pbuf += (pptmp->data_size + 3) / 4; - - } - } - return SW_OK; -} -#endif -void -cmd_strtol(char *str, a_uint32_t * arg_val) -{ - if (str[0] == '0' && (str[1] == 'x' || str[1] == 'X')) - sscanf(str, "%x", arg_val); - else - sscanf(str, "%d", arg_val); -} - -static sw_error_t -cmd_parse_api(char **cmd_str, unsigned long * arg_val) -{ - char *tmp_str; - a_uint32_t arg_index, arg_start = 2, reserve_index = 1; /*reserve for dev_id */ - a_uint32_t last_param_in = 0; - unsigned long *temp; - void *pentry; - sw_api_param_t *pptmp = NULL; - sw_api_t sw_api; - a_uint32_t ignorecnt = 0, jump = 0; - sw_data_type_t *data_type; - sw_api.api_id = arg_val[0]; - SW_RTN_ON_ERROR(sw_api_get(&sw_api)); - - /*set device id */ - arg_val[arg_start] = get_devid(); - - for (arg_index = reserve_index; arg_index < sw_api.api_nr; arg_index++) - { - tmp_str = NULL; - pptmp = sw_api.api_pp + arg_index; - - if (!(pptmp->param_type & SW_PARAM_IN)) - { - ignorecnt++; - } - - if (pptmp->param_type & SW_PARAM_IN) - { - tmp_str = cmd_str[arg_index - reserve_index - ignorecnt + jump]; - last_param_in = arg_index; - if((pptmp->api_id == 314) && last_param_in == 2) last_param_in = 4;//SW_API_FDB_EXTEND_NEXT wr - if((pptmp->api_id == 327) && last_param_in == 2) last_param_in = 4;//SW_API_FDB_EXTEND_FIRST wr - } - temp = &arg_val[arg_start + arg_index]; - - if (!(data_type = cmd_data_type_find(pptmp->data_type))) - return SW_NO_SUCH; - - pentry = temp; - if (pptmp->param_type & SW_PARAM_PTR) - { - if (cmd_input_parser(temp, arg_index, sw_api.api_pp) != SW_OK) - return SW_NO_RESOURCE; - - pentry = (void *) *temp; - } - - if (pptmp->param_type & SW_PARAM_IN) - { -#if 1 - if(pptmp->param_type & SW_PARAM_PTR) //quiet mode - { - if(!get_talk_mode()) - set_full_cmdstrp((char **)(cmd_str + (last_param_in - reserve_index) + jump)); - } -#endif - /*check and convert input param */ - if (data_type->param_check != NULL) - { - if (data_type->param_check(tmp_str, (a_uint32_t *)pentry, (a_uint32_t)pptmp->data_size) != SW_OK) - return SW_BAD_PARAM; - if(!get_talk_mode() && (pptmp->param_type & SW_PARAM_PTR)) { - if (get_jump()) - jump += get_jump() -1; - } - } - } - } - - /*superfluous args */ - /* - if(cmd_str[last_param_in] != NULL) - return SW_BAD_PARAM; - */ - - return SW_OK; -} - -/*user command api*/ -sw_error_t -cmd_exec_api(unsigned long *arg_val) -{ - sw_error_t rv; - sw_api_t sw_api; - - sw_api.api_id = arg_val[0]; - SW_RTN_ON_ERROR(sw_api_get(&sw_api)); - - /*save cmd return value */ - arg_val[1] = (unsigned long) ioctl_buf; - /*save set device id */ - arg_val[2] = get_devid(); - - rv = cmd_api_func(sw_api.api_fp, sw_api.api_nr, arg_val); - SW_RTN_ON_ERROR(rv); - - #if 0 - rv = cmd_api_output(sw_api.api_pp, sw_api.api_nr, arg_val); - SW_RTN_ON_ERROR(rv); - #endif - - return rv; -} - - -void -cmd_print_usage (int cmd_index, int cmd_index_sub) -{ - #if 0 - if(GCMD_NAME(cmd_index)) - dprintf("usage: %s", GCMD_NAME(cmd_index)); - - if (GCMD_SUB_NAME(cmd_index, cmd_index_sub)) - dprintf(" %s", GCMD_SUB_NAME(cmd_index, cmd_index_sub)); - - if(GCMD_SUB_ACT(cmd_index, cmd_index_sub) && GCMD_SUB_USAGE(cmd_index, cmd_index_sub)) - dprintf(" %s %s\n\n", GCMD_SUB_ACT(cmd_index, cmd_index_sub), - GCMD_SUB_USAGE(cmd_index, cmd_index_sub)); - #endif -} -/* - main function - input args: - arg_val[0] = cmd_num - arg_val[1] = rtn_code - arg_val[2] = dev_id - arg_val[3] = dbg_cmd_num or other -*/ - -/*command string lookup*/ -a_uint32_t -cmd_lookup(char **cmd_str, int *cmd_index, int *cmd_index_sub) -{ - a_uint32_t no, sub_no; - a_uint32_t cmd_deepth = 0; - - *cmd_index = GCMD_DESC_NO_MATCH; - *cmd_index_sub = GCMD_DESC_NO_MATCH; - - if (cmd_str[0] == NULL) - return cmd_deepth; - - for (no = 0; GCMD_DESC_VALID(no); no++) - { - if (strcasecmp(cmd_str[0], GCMD_NAME(no))) - continue; - - for (sub_no = 0; GCMD_SUB_DESC_VALID(no, sub_no); sub_no++) - { - if (cmd_str[1] != NULL && cmd_str[2] != NULL) - { - - if (GCMD_SUB_NAME(no, sub_no) && GCMD_SUB_ACT(no, sub_no) - && !strcasecmp(cmd_str[1], GCMD_SUB_NAME(no, sub_no)) - && !strcasecmp(cmd_str[2], GCMD_SUB_ACT(no, sub_no))) - { - *cmd_index = no; - *cmd_index_sub = sub_no; - cmd_deepth = 3; - return cmd_deepth; - } - - else if (!GCMD_SUB_NAME(no, sub_no) && GCMD_SUB_ACT(no, sub_no) - && !strcasecmp(cmd_str[1], GCMD_SUB_ACT(no, sub_no))) - { - *cmd_index = no; - *cmd_index_sub = sub_no; - cmd_deepth = 2; - return cmd_deepth; - } - } - else if (cmd_str[1] != NULL && cmd_str[2] == NULL) - { - - if (!GCMD_SUB_NAME(no, sub_no) && GCMD_SUB_ACT(no, sub_no) - && !strcasecmp(cmd_str[1], GCMD_SUB_ACT(no, sub_no))) - { - *cmd_index = no; - *cmd_index_sub = sub_no; - cmd_deepth = 2; - return cmd_deepth; - } - } - } - } - - return cmd_deepth; -} - -static unsigned long * -cmd_parse(char *cmd_str, int *cmd_index, int *cmd_index_sub) -{ - int cmd_nr = 0; - unsigned long *arg_val = ioctl_argp; - char *tmp_str[CMDSTR_ARGS_MAX]; - int rtn_code = 0; - int cmd_depth; - - if (cmd_str == NULL) - return NULL; - - memset(arg_val, 0, CMDSTR_ARGS_MAX * sizeof (unsigned long)); - - /* split string into array */ - if ((tmp_str[cmd_nr] = (void *) strsep(&cmd_str, " ")) == NULL) - return NULL; - - /*handle help */ - if (!strcasecmp(tmp_str[cmd_nr], "help")) - { - return NULL; - } - - while (tmp_str[cmd_nr]) - { - if (++cmd_nr == 3) - break; - - tmp_str[cmd_nr] = (void *) strsep(&cmd_str, " "); - } - - /*commond string lookup */ - cmd_depth = cmd_lookup(tmp_str, cmd_index, cmd_index_sub); - - if (*cmd_index == GCMD_DESC_NO_MATCH || *cmd_index_sub == GCMD_DESC_NO_MATCH) - { - return NULL; - } - - /*parse param */ - cmd_nr = 0; - if (cmd_depth == 2) - { - tmp_str[cmd_nr] = tmp_str[2]; - cmd_nr++; - } - - tmp_str[cmd_nr] = (void *) strsep(&cmd_str, " "); - while (tmp_str[cmd_nr]) - { - if (strcmp(tmp_str[cmd_nr], "")) - if (++cmd_nr == CMDSTR_ARGS_MAX) - break; - tmp_str[cmd_nr] = (void *) strsep(&cmd_str, " "); - } - - arg_val[0] = GCMD_SUB_API(*cmd_index, *cmd_index_sub); - arg_val[1] = (unsigned long) ioctl_buf; - - if (arg_val[0] < SW_API_MAX) - { - /*api command parse */ - rtn_code = cmd_parse_api(tmp_str, arg_val); - - } - else - { - rtn_code = SW_BAD_PARAM; - } - - if(rtn_code != SW_OK) - { - cmd_print_error(rtn_code); - - if(rtn_code == SW_BAD_PARAM) - cmd_print_usage(*cmd_index, *cmd_index_sub); - - return NULL; - } - - return arg_val; -} - -static int -cmd_exec(unsigned long *arg_val, int cmd_index, int cmd_index_sub) -{ - unsigned long api_id = arg_val[0]; - sw_error_t rtn = SW_OK; - - if( api_id < SW_API_MAX ) - { - rtn = cmd_exec_api(arg_val); - - } - else if ((api_id > SW_API_MAX ) && (api_id < SW_CMD_MAX)) - { - } - else - { - rtn = SW_BAD_PARAM; - } - - if(rtn != SW_OK) - cmd_print_error(rtn); - - return 0; -} - -int -cmd_run_one(char *cmd_str) -{ - unsigned long *arg_list; - int cmd_index = 0, cmd_index_sub = 0; - - if ((arg_list = cmd_parse(cmd_str, &cmd_index, &cmd_index_sub)) != NULL) - { - cmd_exec(arg_list, cmd_index, cmd_index_sub); - } - - return SW_OK; -} - -/* Dummy function to avoid linker complaints */ -void __aeabi_unwind_cpp_pr0(void) -{ -}; -void __aeabi_unwind_cpp_pr1(void) -{ -}; - diff --git a/feeds/ipq807x/qca-ssdk/src/src/shell_lib/shell_config.c b/feeds/ipq807x/qca-ssdk/src/src/shell_lib/shell_config.c deleted file mode 100755 index 1b00daf3e..000000000 --- a/feeds/ipq807x/qca-ssdk/src/src/shell_lib/shell_config.c +++ /dev/null @@ -1,1513 +0,0 @@ -/* - * Copyright (c) 2013, 2015-2019, 2021, The Linux Foundation. All rights reserved. - * - * Permission to use, copy, modify, and/or distribute this software for any - * purpose with or without fee is hereby granted, provided that the above - * copyright notice and this permission notice appear in all copies. - * - * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES - * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR - * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES - * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN - * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF - * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. - */ - -#include "shell_config.h" -#include "shell_sw.h" - -#if 0 -/*cmdline tree descript*/ -struct cmd_des_t gcmd_des[] = -{ - /*port ctrl*/ -#ifdef IN_PORTCONTROL - { - "port", "config port control", - { - {"duplex", "set", "set duplex mode of a port", " ", SW_API_PT_DUPLEX_SET, NULL}, - {"speed", "set", "set speed mode of a port", " <10|100|1000>", SW_API_PT_SPEED_SET, NULL}, - {"autoAdv", "set", "set auto-negotiation advertisement of a port", " ", SW_API_PT_AN_ADV_SET, NULL}, - {"autoNeg", "enable", "enable auto-negotiation of a port", "", SW_API_PT_AN_ENABLE, NULL}, - {"autoNeg", "restart", "restart auto-negotiation process of a port", "", SW_API_PT_AN_RESTART, NULL}, - {"autoNegenable", "set", "enable auto-negotiation of a port", "", SW_API_PT_AN_ENABLE, NULL}, - {"autoNegrestart", "set", "restart auto-negotiation process of a port", "", SW_API_PT_AN_RESTART, NULL}, - {"header", "set", "set atheros header/tag status of a port", " ", SW_API_PT_HDR_SET, NULL}, - {"txhdr", "set", "set tx frame atheros header/tag status of a port", " ", SW_API_PT_TXHDR_SET, NULL}, - {"rxhdr", "set", "set rx frame atheros header/tag status of a port", " ", SW_API_PT_RXHDR_SET, NULL}, - {"hdrtype", "set", "set atheros header/tag type", " ", SW_API_HEADER_TYPE_SET, NULL}, - {"flowCtrl", "set", "set flow control status of a port", " ", SW_API_PT_FLOWCTRL_SET, NULL}, - {"flowCtrlforcemode", "set", "set flow control force mode of a port", " ", SW_API_PT_FLOWCTRL_MODE_SET, NULL}, - {"powersave", "set", "set powersave status of a port", " ", SW_API_PT_POWERSAVE_SET, NULL}, - {"hibernate", "set", "set hibernate status of a port", " ", SW_API_PT_HIBERNATE_SET, NULL}, - {"cdt", "run", "run cable diagnostic test of a port", " ", SW_API_PT_CDT, NULL}, - {"txmacstatus", "set", "set txmac status of a port", " ", SW_API_TXMAC_STATUS_SET, NULL}, - {"rxmacstatus", "set", "set rxmac status of a port", " ", SW_API_RXMAC_STATUS_SET, NULL}, - {"txfcstatus", "set", "set tx flow control status of a port", " ", SW_API_TXFC_STATUS_SET, NULL}, - {"rxfcstatus", "set", "set rx flow control status of a port", " ", SW_API_RXFC_STATUS_SET, NULL}, - {"bpstatus", "set", "set back pressure status of a port", " ", SW_API_BP_STATUS_SET, NULL}, - {"linkforcemode", "set", "set link force mode of a port", " ", SW_API_PT_LINK_MODE_SET, NULL}, - {"macLoopback", "set", "set mac level loop back mode of port", " ", SW_API_PT_MAC_LOOPBACK_SET, NULL}, - {"congedrop", "set", "set congestion drop of port queue", " ", SW_API_PT_CONGESTION_DROP_SET, NULL}, - {"ringfcthresh", "set", "set flwo ctrl thres of ring", " ", SW_API_PT_RING_FLOW_CTRL_THRES_SET, NULL}, - {"Ieee8023az", "set", "set 8023az status of a port", " ", SW_API_PT_8023AZ_SET, NULL}, - {"crossover", "set", "set crossover mode of a port", " ", SW_API_PT_MDIX_SET, NULL}, - {"crossover", "get", "get crossover mode of a port", "", SW_API_PT_MDIX_GET, NULL}, - {"crossover", "status", "get current crossover status of a port", "", SW_API_PT_MDIX_STATUS_GET, NULL}, - {"preferMedium", "set", "set prefer medium of a combo port", " ", SW_API_PT_COMBO_PREFER_MEDIUM_SET, NULL}, - {"preferMedium", "get", "get prefer medium of a combo port", "", SW_API_PT_COMBO_PREFER_MEDIUM_GET, NULL}, - {"mediumType", "get", "get current medium status of a combo port", "", SW_API_PT_COMBO_MEDIUM_STATUS_GET, NULL}, - {"fiberMode", "set", "set fiber mode of a combo fiber port", " <100fx|1000bx>", SW_API_PT_COMBO_FIBER_MODE_SET, NULL}, - {"fiberMode", "get", "get fiber mode of a combo fiber port", "", SW_API_PT_COMBO_FIBER_MODE_GET, NULL}, - {"localLoopback", "set", "set local loopback of a port", " ", SW_API_PT_LOCAL_LOOPBACK_SET, NULL}, - {"localLoopback", "get", "get local loopback of a port", "", SW_API_PT_LOCAL_LOOPBACK_GET, NULL}, - {"remoteLoopback", "set", "set remote loopback of a port", " ", SW_API_PT_REMOTE_LOOPBACK_SET, NULL}, - {"remoteLoopback", "get", "get remote loopback of a port", "", SW_API_PT_REMOTE_LOOPBACK_GET, NULL}, - {"reset", "set", "reset phy of a port", "", SW_API_PT_RESET, NULL}, - {"poweroff", "set", "power off phy of a port", "", SW_API_PT_POWER_OFF, NULL}, - {"poweron", "set", "power on phy of a port", "", SW_API_PT_POWER_ON, NULL}, - {"magicFrameMac", "set", "set magic frame mac address of a port", " ", SW_API_PT_MAGIC_FRAME_MAC_SET, NULL}, - {"magicFrameMac", "get", "get magic frame mac address of a port", "", SW_API_PT_MAGIC_FRAME_MAC_GET, NULL}, - {"phyId", "get", "get phy id of a port", "", SW_API_PT_PHY_ID_GET, NULL}, - {"wolstatus", "set", "set wol status of a port", " ", SW_API_PT_WOL_STATUS_SET, NULL}, - {"wolstatus", "get", "get wol status of a port", "", SW_API_PT_WOL_STATUS_GET, NULL}, - {"interfaceMode", "set", "set interface mode of phy", " ", SW_API_PT_INTERFACE_MODE_SET, NULL}, - {"interfaceMode", "get", "get interface mode of phy", "", SW_API_PT_INTERFACE_MODE_GET, NULL}, - {"interfaceMode", "status", "get current interface mode of phy", "", SW_API_PT_INTERFACE_MODE_STATUS_GET, NULL}, - {"counter", "set", "set counter status of a port", " ", SW_API_PT_COUNTER_SET, NULL}, - {"counter", "get", "get counter status of a port", "", SW_API_PT_COUNTER_GET, NULL}, - {"counter", "show", "show counter statistics of a port", "", SW_API_PT_COUNTER_SHOW, NULL}, - {NULL, NULL, NULL, NULL, (int)NULL, NULL},/*end of desc*/ - }, - }, -#endif - - /*vlan*/ -#ifdef IN_VLAN - { - "vlan", "config VLAN table", - { - {"entry", "set", "create a VLAN entry", "", SW_API_VLAN_ADD, NULL}, - {"entry", "create", "create a VLAN entry", "", SW_API_VLAN_ADD, NULL}, - {"entry", "del", "delete a VLAN entryn", "", SW_API_VLAN_DEL, NULL}, - {"entry", "update", "update port member of a VLAN entry", " <0>", SW_API_VLAN_MEM_UPDATE, NULL}, - {"entry", "find", "find a VLAN entry by VLAN id", "", SW_API_VLAN_FIND, NULL}, - {"entry", "next", "find next VLAN entry by VLAN id", "",SW_API_VLAN_NEXT, NULL}, - {"entry", "append", "append a VLAN entry", "", SW_API_VLAN_APPEND, NULL}, - {"entry", "flush", "flush all VLAN entries", "",SW_API_VLAN_FLUSH, NULL}, - {"fid", "set", "set VLAN entry fid", " ",SW_API_VLAN_FID_SET, NULL}, - {"member", "set", "add VLAN entry member", " ",SW_API_VLAN_MEMBER_ADD, NULL}, - {"member", "add", "add VLAN entry member", " ",SW_API_VLAN_MEMBER_ADD, NULL}, - {"member", "del", "del VLAN entry member", " ",SW_API_VLAN_MEMBER_DEL, NULL}, - {"learnsts", "set", "set VLAN entry learn status", " ",SW_API_VLAN_LEARN_STATE_SET, NULL}, - {NULL, NULL, NULL, NULL, (int)NULL, NULL}/*end of desc*/ - }, - }, -#endif - - /*portvlan*/ -#ifdef IN_PORTVLAN - { - "portVlan", "config port base VLAN", - { - {"ingress", "set", "set ingress VLAN mode of a port", " ", SW_API_PT_ING_MODE_SET, NULL}, - {"egress", "set", "set egress VLAN mode of a port", " ", SW_API_PT_EG_MODE_SET, NULL}, - {"member", "set", "add a member to the port based VLAN of a port", " ", SW_API_PT_VLAN_MEM_UPDATE, NULL}, - {"member", "add", "add a member to the port based VLAN of a port", " ", SW_API_PT_VLAN_MEM_ADD, NULL}, - {"member", "del", "delete a member from the port based VLAN of a port", " ", SW_API_PT_VLAN_MEM_DEL, NULL}, - {"member", "update", "update members of the port based VLAN of a port", " ", SW_API_PT_VLAN_MEM_UPDATE, NULL}, - {"defaultVid", "set", "set default VLAN id of a port", " ", SW_API_PT_DEF_VID_SET, NULL}, - {"forceVid", "set", "set VLAN id enforcement status of a port", " ", SW_API_PT_FORCE_DEF_VID_SET, NULL}, - {"forceMode", "set", "set port based VLAN enforcement status of a port", " ", SW_API_PT_FORCE_PORTVLAN_SET, NULL}, - {"nestVlan", "set", "set nest VLAN status of a port", " ", SW_API_PT_NESTVLAN_SET, NULL}, - {"sVlanTPID", "set", "set service VLAN tpid", "", SW_API_NESTVLAN_TPID_SET, NULL}, - {"invlan", "set", "set port invlan mode", " ", SW_API_PT_IN_VLAN_MODE_SET, NULL}, - {"tlsMode", "set", "set TLS mode", " ", SW_API_PT_TLS_SET, NULL}, - {"priPropagation", "set", "set priority propagation", " ", SW_API_PT_PRI_PROPAGATION_SET, NULL}, - {"defaultSVid", "set", "set default SVID", " ", SW_API_PT_DEF_SVID_SET, NULL}, - {"defaultCVid", "set", "set default CVID", " ", SW_API_PT_DEF_CVID_SET, NULL}, - {"vlanPropagation", "set", "set vlan propagation", " ", SW_API_PT_VLAN_PROPAGATION_SET, NULL}, - {"translation", "set", "add vlan translation", "", SW_API_PT_VLAN_TRANS_ADD, NULL}, - {"translation", "add", "add vlan translation", "", SW_API_PT_VLAN_TRANS_ADD, NULL}, - {"translation", "del", "del vlan translation", "", SW_API_PT_VLAN_TRANS_DEL, NULL}, - {"translation", "iterate", "iterate vlan translation tables", " ", SW_API_PT_VLAN_TRANS_ITERATE, NULL}, - {"qinqMode", "set", "set qinq mode", "", SW_API_QINQ_MODE_SET, NULL}, - {"qinqRole", "set", "set qinq role", " ", SW_API_PT_QINQ_ROLE_SET, NULL}, - {"macvlanxlt", "set", "set mac vlan xlt status", " ", SW_API_PT_MAC_VLAN_XLT_SET, NULL}, - {"netiso", "set", "enable public/private net isolate", "", SW_API_NETISOLATE_SET, NULL}, - {"egbypass", "set", "enable egress translation filter bypass", "", SW_API_EG_FLTR_BYPASS_EN_SET, NULL}, - {"ptvrfid", "set", "set port VRF ID", " ", SW_API_PT_VRF_ID_SET, NULL}, - {NULL, NULL, NULL, NULL, (int)NULL, NULL}/*end of desc*/ - }, - }, -#endif - - /*fdb*/ -#ifdef IN_FDB - { - "fdb", "config FDB table", - { - {"entry", "set", "add a FDB entry", "", SW_API_FDB_ADD, NULL}, - {"entry", "add", "add a FDB entry", "", SW_API_FDB_ADD, NULL}, - {"entry", "del", "delete a FDB entry", "", SW_API_FDB_DELMAC, NULL}, - {"entry", "flush", "flush all FDB entries", "<0:dynamic only|1:dynamic and static>", SW_API_FDB_DELALL, NULL}, - {"entry", "find", "find a FDB entry", "", SW_API_FDB_FIND, NULL}, - {"entry", "iterate", "iterate all FDB entries", "", SW_API_FDB_ITERATE, NULL}, - {"entry", "extendnext", "find next FDB entry in extend mode", "", SW_API_FDB_EXTEND_NEXT, NULL}, - {"entry", "extendfirst", "find first FDB entry in extend mode", "", SW_API_FDB_EXTEND_FIRST, NULL}, - {"entry", "transfer", "transfer port info in FDB entry", " ", SW_API_FDB_TRANSFER, NULL}, - {"portEntry", "flush", "flush all FDB entries by a port", " <0:dynamic only|1:dynamic and static>", SW_API_FDB_DELPORT, NULL}, - {"firstEntry", "find", "find the first FDB entry", "", SW_API_FDB_FIRST, NULL}, - {"nextEntry", "find", "find next FDB entry", "", SW_API_FDB_NEXT, NULL}, - {"portLearn", "set", "set FDB entry learning status of a port", " ", SW_API_FDB_PT_LEARN_SET, NULL}, - {"ageCtrl", "set", "set FDB entry aging status", "", SW_API_FDB_AGE_CTRL_SET, NULL}, - {"vlansmode", "set", "set FDB vlan search mode", "", SW_API_FDB_VLAN_IVL_SVL_SET, NULL}, - {"ageTime", "set", "set FDB entry aging time", "", SW_API_FDB_AGE_TIME_SET, NULL}, - {"ptlearnlimit", "set", "set port FDB entry learn limit", " ", SW_API_PT_FDB_LEARN_LIMIT_SET, NULL}, - {"ptlearnexceedcmd", "set", "set port forwarding cmd when exceed learn limit", " ", SW_API_PT_FDB_LEARN_EXCEED_CMD_SET, NULL}, - {"learnlimit", "set", "set FDB entry learn limit", " ", SW_API_FDB_LEARN_LIMIT_SET, NULL}, - {"learnexceedcmd", "set", "set forwarding cmd when exceed learn limit", "", SW_API_FDB_LEARN_EXCEED_CMD_SET, NULL}, - {"resventry", "set", "add a reserve FDB entry", "", SW_API_FDB_RESV_ADD, NULL}, - {"resventry", "add", "add a reserve FDB entry", "", SW_API_FDB_RESV_ADD, NULL}, - {"resventry", "del", "delete reserve a FDB entry", "", SW_API_FDB_RESV_DEL, NULL}, - {"resventry", "find", "find a reserve FDB entry", "", SW_API_FDB_RESV_FIND, NULL}, - {"resventry", "iterate", "iterate all reserve FDB entries", "", SW_API_FDB_RESV_ITERATE, NULL}, - {"ptLearnstatic", "set", "set FDB entry learning static status of a port", " ", SW_API_FDB_PT_LEARN_STATIC_SET, NULL}, - {"port", "add", "add one port to a FDB entry", " ", SW_API_FDB_PORT_ADD, NULL}, - {"port", "del", "del one port from a FDB entry", " ", SW_API_FDB_PORT_DEL, NULL}, - {NULL, NULL, NULL, NULL, (int)NULL, NULL}/*end of desc*/ - }, - }, -#endif - - /*acl*/ -#ifdef IN_ACL - { - "acl", "config ACL", - { - {"list", "create", "create an ACL list", " ", SW_API_ACL_LIST_CREAT, NULL}, - {"list", "destroy", "destroy an ACL list", "", SW_API_ACL_LIST_DESTROY, NULL}, - {"list", "bind", "bind an ACL list to a port", " <0-0:direction> <0-0:objtype> ", SW_API_ACL_LIST_BIND, NULL}, - {"list", "unbind", "unbind an ACL list from a port", " <0-0:direction> <0-0:objtype> ", SW_API_ACL_LIST_UNBIND, NULL}, - {"rule", "add", "add ACL rules to an ACL list", " ", SW_API_ACL_RULE_ADD, NULL}, - {"rule", "del", "delete ACL rules from an ACL list", " ", SW_API_ACL_RULE_DELETE, NULL}, - {"rule", "query", "query a ACL rule", " ", SW_API_ACL_RULE_QUERY, NULL}, - {"rule", "active", "active ACL rules in an ACL list", " ", SW_API_ACL_RULE_ACTIVE, NULL}, - {"rule", "deactive", "deactive ACL rules in an ACL list", " ", SW_API_ACL_RULE_DEACTIVE, NULL}, - {"srcfiltersts", "set", "set status of ACL rules source filter", " ", SW_API_ACL_RULE_SRC_FILTER_STS_SET, NULL}, - {"status", "set", "set status of ACL engine", "", SW_API_ACL_STATUS_SET, NULL}, - {"udfprofile", "set", "set port udf profile", " ", SW_API_ACL_PT_UDF_PROFILE_SET, NULL}, - {NULL, NULL, NULL, NULL, (int)NULL, NULL}/*end of desc*/ - }, - }, -#endif - - /*qos*/ -#ifdef IN_QOS - { - "qos", "config Qos", - { -#ifndef ISISC - {"schMode", "set", "set traffic scheduling mode", " ", SW_API_QOS_SCH_MODE_SET, NULL}, -#endif - {"qTxBufSts", "set", "set queue tx buffer counting status of a port", " ", SW_API_QOS_QU_TX_BUF_ST_SET, NULL}, -#ifdef ISISC - {"qTxBufNr", "set", "set queue tx buffer number", " ", SW_API_QOS_QU_TX_BUF_NR_SET, NULL}, -#else - {"qTxBufNr", "set", "set queue tx buffer number", " ", SW_API_QOS_QU_TX_BUF_NR_SET, NULL}, -#endif - {"ptTxBufSts", "set", "set port tx buffer counting status of a port", " ", SW_API_QOS_PT_TX_BUF_ST_SET, NULL}, - {"ptRedEn", "set", "set status of port wred of a port", " ", SW_API_QOS_PT_RED_EN_SET, NULL}, -#ifdef ISISC - {"ptTxBufNr", "set", "set port tx buffer number", " ", SW_API_QOS_PT_TX_BUF_NR_SET, NULL}, -#else - {"ptTxBufNr", "set", "set port tx buffer number", " ", SW_API_QOS_PT_TX_BUF_NR_SET, NULL}, -#endif -#ifdef ISISC - {"ptRxBufNr", "set", "set port rx buffer number", " ", SW_API_QOS_PT_RX_BUF_NR_SET, NULL}, -#else - {"ptRxBufNr", "set", "set port rx buffer number", " ", SW_API_QOS_PT_RX_BUF_NR_SET, NULL}, -#endif -#ifndef ISISC - {"up2q", "set", "set user priority to queue mapping", " ", SW_API_COSMAP_UP_QU_SET, NULL}, - {"dscp2q", "set", "set dscp to queue mapping", " ", SW_API_COSMAP_DSCP_QU_SET, NULL}, -#endif -#ifdef ISISC - {"ptMode", "set", "set Qos mode of a port", " ", SW_API_QOS_PT_MODE_SET, NULL}, - {"ptModePri", "set", "set the priority of Qos modes of a port", " ", SW_API_QOS_PT_MODE_PRI_SET, NULL}, -#else - {"ptMode", "set", "set Qos mode of a port", " ", SW_API_QOS_PT_MODE_SET, NULL}, - {"ptModePri", "set", "set the priority of Qos modes of a port", " ", SW_API_QOS_PT_MODE_PRI_SET, NULL}, -#endif -#ifndef ISISC - {"ptDefaultUp", "set", "set default user priority for received frames of a port", " ", SW_API_QOS_PORT_DEF_UP_SET, NULL}, -#endif - {"ptschMode", "set", "set port traffic scheduling mode", " ", SW_API_QOS_PORT_SCH_MODE_SET, NULL}, - {"ptDefaultSpri", "set", "set default stag priority for received frames of a port", " ", SW_API_QOS_PT_DEF_SPRI_SET, NULL}, - {"ptDefaultCpri", "set", "set default ctag priority for received frames of a port", " ", SW_API_QOS_PT_DEF_CPRI_SET, NULL}, - {"ptFSpriSts", "set", "set port force Stag priority status for received frames of a port", " ", SW_API_QOS_PT_FORCE_SPRI_ST_SET, NULL}, - {"ptFCpriSts", "set", "set port force Ctag priority status for received frames of a port", " ", SW_API_QOS_PT_FORCE_CPRI_ST_SET, NULL}, - {"ptQuRemark", "set", "set egress queue based remark", " ", SW_API_QOS_QUEUE_REMARK_SET, NULL}, - {NULL, NULL, NULL, NULL, (int)NULL, NULL}/*end of desc*/ - }, - }, -#endif - - /*igmp*/ -#ifdef IN_IGMP - { - "igmp", "config IGMP/MLD", - { - {"mode", "set", "set IGMP/MLD snooping status of a port", " ", SW_API_PT_IGMPS_MODE_SET, NULL}, - {"cmd", "set", "set IGMP/MLD frames forwarding command", "", SW_API_IGMP_MLD_CMD_SET, NULL}, - {"portJoin", "set", "set IGMP/MLD hardware joining status", " ", SW_API_IGMP_PT_JOIN_SET, NULL}, - {"portLeave", "set", "set IGMP/MLD hardware leaving status", " ", SW_API_IGMP_PT_LEAVE_SET, NULL}, - {"rp", "set", "set IGMP/MLD router ports", "", SW_API_IGMP_RP_SET, NULL}, - {"createStatus", "set", "set IGMP/MLD ability for creating entry", "", SW_API_IGMP_ENTRY_CREAT_SET, NULL}, - {"static", "set", "set IGMP/MLD static status for creating entry", "", SW_API_IGMP_ENTRY_STATIC_SET, NULL}, - {"leaky", "set", "set IGMP/MLD leaky status for creating entry", "", SW_API_IGMP_ENTRY_LEAKY_SET, NULL}, - {"version3", "set", "set IGMP v3/MLD v2 status for creating entry", "", SW_API_IGMP_ENTRY_V3_SET, NULL}, - {"queue", "set", "set IGMP/MLD queue status for creating entry", " ", SW_API_IGMP_ENTRY_QUEUE_SET, NULL}, - {"ptlearnlimit", "set", "set port Multicast entry learn limit", " ", SW_API_PT_IGMP_LEARN_LIMIT_SET, NULL}, - {"ptlearnexceedcmd", "set", "set port forwarding cmd when exceed multicast learn limit", " ", SW_API_PT_IGMP_LEARN_EXCEED_CMD_SET, NULL}, - {"multi", "set", "set igmp/mld entry", "", SW_API_IGMP_SG_ENTRY_SET, NULL}, - {"multi", "clear", "clear igmp/mld entry", "", SW_API_IGMP_SG_ENTRY_CLEAR, NULL}, - {"multi", "show", "show all igmp/mld entry", "", SW_API_IGMP_SG_ENTRY_SHOW, NULL}, - {NULL, NULL, NULL, NULL, (int)NULL, NULL}/*end of desc*/ - }, - }, -#endif - - /*leaky*/ -#ifdef IN_LEAKY - { - "leaky", "config leaky", - { - {"ucMode", "set", "set unicast packets leaky mode", "", SW_API_UC_LEAKY_MODE_SET, NULL}, - {"mcMode", "set", "set multicast packets leaky mode", "", SW_API_MC_LEAKY_MODE_SET, NULL}, - {"arpMode", "set", "set arp packets leaky mode", " ", SW_API_ARP_LEAKY_MODE_SET, NULL}, - {"ptUcMode", "set", "set unicast packets leaky status of a port", " ", SW_API_PT_UC_LEAKY_MODE_SET, NULL}, - {"ptMcMode", "set", "set multicast packets leaky status of a port", " ", SW_API_PT_MC_LEAKY_MODE_SET, NULL}, - {NULL, NULL, NULL, NULL, (int)NULL, NULL}/*end of desc*/ - }, - }, -#endif - - /*mirror*/ -#ifdef IN_MIRROR - { - "mirror", "config mirror", - { - {"analyPt", "set", "set mirror analysis port", "", SW_API_MIRROR_ANALY_PT_SET, NULL}, - {"ptIngress", "set", "set ingress mirror status of a port", " ", SW_API_MIRROR_IN_PT_SET, NULL}, - {"ptEgress", "set", "set egress mirror status of a port", " ", SW_API_MIRROR_EG_PT_SET, NULL}, - {NULL, NULL, NULL, NULL, (int)NULL, NULL}/*end of desc*/ - }, - }, -#endif - - /*rate*/ -#ifdef IN_RATE - { - "rate", "config rate limit", - { -#ifndef ISISC - {"qEgress", "set", "set egress rate limit of a queue", " ", SW_API_RATE_QU_EGRL_SET, NULL}, - {"ptEgress", "set", "set egress rate limit of a port", " ", SW_API_RATE_PT_EGRL_SET, NULL}, - {"ptIngress", "set", "set ingress rate limit of a port", " ", SW_API_RATE_PT_INRL_SET, NULL}, - {"stormCtrl", "set", "set storm control status of a particular frame type", " ", SW_API_STORM_CTRL_FRAME_SET, NULL}, - {"stormCtrlRate", "set", "set storm ctrl rate", " ", SW_API_STORM_CTRL_RATE_SET, NULL}, -#endif - {"portpolicer", "set", "set port policer", "", SW_API_RATE_PORT_POLICER_SET, NULL}, - {"portshaper", "set", "set port egress shaper", " ", SW_API_RATE_PORT_SHAPER_SET, NULL}, - {"queueshaper", "set", "set queue egress shaper", " ", SW_API_RATE_QUEUE_SHAPER_SET, NULL}, - {"aclpolicer", "set", "set acl policer", "", SW_API_RATE_ACL_POLICER_SET, NULL}, - {"ptAddRateByte", "set", "set add_rate_byte when cal rate ", " ", SW_API_RATE_PT_ADDRATEBYTE_SET, NULL}, - {"ptgolflowen", "set", "set status of port globle flow control", " ", SW_API_RATE_PT_GOL_FLOW_EN_SET, NULL}, - {NULL, NULL, NULL, NULL, (int)NULL, NULL}/*end of desc*/ - }, - }, -#endif - -#ifdef IN_SEC -#ifdef ISISC - { - "sec", "config security", - { - {"mac", "set", "set MAC layer related security", " ", SW_API_SEC_MAC_SET, NULL}, - {"ip", "set", "set IP layer related security", " ", SW_API_SEC_IP_SET, NULL}, - {"ip4", "set", "set IP4 related security", " ", SW_API_SEC_IP4_SET, NULL}, - {"ip6", "set", "set IP6 related security", " ", SW_API_SEC_IP6_SET, NULL}, - {"tcp", "set", "set TCP related security", " ", SW_API_SEC_TCP_SET, NULL}, - {"udp", "set", "set UDP related security", " ", SW_API_SEC_UDP_SET, NULL}, - {"icmp4", "set", "set ICMP4 related security", " ", SW_API_SEC_ICMP4_SET, NULL}, - {"icmp6", "set", "set ICMP6 related security", " ", SW_API_SEC_ICMP6_SET, NULL}, - {NULL, NULL, NULL, NULL, (int)NULL, NULL}/*end of desc*/ - }, - }, -#endif -#endif - - /*stp*/ -#ifdef IN_STP - { - "stp", "config STP", - { - {"portState", "set", "set STP state of a port", " ", SW_API_STP_PT_STATE_SET, NULL}, - {NULL, NULL, NULL, NULL, (int)NULL, NULL}/*end of desc*/ - }, - }, -#endif - - /*mib*/ -#ifdef IN_MIB - { - "mib", "show MIB statistics information", - { - {"status", "set", "set mib status", "", SW_API_MIB_STATUS_SET, NULL}, - {"counters", "flush", "flush counters of a port", "", SW_API_PT_MIB_FLUSH_COUNTERS, NULL}, - {"cpuKeep", "set", "set cpu keep bit", "", SW_API_MIB_CPU_KEEP_SET, NULL}, - {NULL, NULL, NULL, NULL, (int)NULL, NULL}/*end of desc*/ - }, - }, -#endif - - /* led */ -#ifdef IN_LED - { - "led", "set/get led control pattern", - { - {"ctrlpattern", "set", "set led control pattern", " ", SW_API_LED_PATTERN_SET, NULL}, - {NULL, NULL, NULL, NULL, (int)NULL, NULL}/*end of desc*/ - }, - }, -#endif - - /* cosmap */ -#ifdef IN_COSMAP - { - "cosmap", "set/get cosmap table", - { - {"dscp2pri", "set", "set dscp to priority map table", " ", SW_API_COSMAP_DSCP_TO_PRI_SET, NULL}, - {"dscp2dp", "set", "set dscp to dp map table", " ", SW_API_COSMAP_DSCP_TO_DP_SET, NULL}, - {"up2pri", "set", "set dot1p to priority map table", " ", SW_API_COSMAP_UP_TO_PRI_SET, NULL}, - {"up2dp", "set", "set dot1p to dp map table", " ", SW_API_COSMAP_UP_TO_DP_SET, NULL}, - {"dscp2ehpri", "set", "set dscp to priority map table for WAN port", " ", SW_API_COSMAP_DSCP_TO_EHPRI_SET, NULL}, - {"dscp2ehdp", "set", "set dscp to dp map table for WAN port", " ", SW_API_COSMAP_DSCP_TO_EHDP_SET, NULL}, - {"up2ehpri", "set", "set dot1p to priority map table for WAN port", " ", SW_API_COSMAP_UP_TO_EHPRI_SET, NULL}, - {"up2ehdp", "set", "set dot1p to dp map table for WAN port", " ", SW_API_COSMAP_UP_TO_EHDP_SET, NULL}, - {"pri2q", "set", "set priority to queue mapping", " ", SW_API_COSMAP_PRI_TO_QU_SET, NULL}, - {"pri2ehq", "set", "set priority to enhanced queue mapping", " ", SW_API_COSMAP_PRI_TO_EHQU_SET, NULL}, - {"egRemark", "set", "set egress remark table", "", SW_API_COSMAP_EG_REMARK_SET, NULL}, - {NULL, NULL, NULL, NULL, (int)NULL, NULL}/*end of desc*/ - }, - }, -#endif - - /*misc*/ -#ifdef IN_MISC - { - "misc", "config miscellaneous", - { -#ifndef ISISC - {"arp", "set", "set arp packets hardware identification status", "", SW_API_ARP_STATUS_SET, NULL}, -#endif - {"frameMaxSize", "set", "set the maximal received frame size of the device", "", SW_API_FRAME_MAX_SIZE_SET, NULL}, -#ifndef ISISC - {"ptUnkSaCmd", "set", "set forwarding command for frames with unknown source address", " ", SW_API_PT_UNK_SA_CMD_SET, NULL}, -#endif - {"ptUnkUcFilter", "set", "set flooding status of unknown unicast frames", " ", SW_API_PT_UNK_UC_FILTER_SET, NULL}, - {"ptUnkMcFilter", "set", "set flooding status of unknown multicast frames", " ", SW_API_PT_UNK_MC_FILTER_SET, NULL}, - {"ptBcFilter", "set", "set flooding status of broadcast frames", " ", SW_API_PT_BC_FILTER_SET, NULL}, - {"cpuPort", "set", "set cpu port status", "", SW_API_CPU_PORT_STATUS_SET, NULL}, -#ifndef ISISC - {"bctoCpu", "set", "set broadcast frames to Cpu port status", "", SW_API_BC_TO_CPU_PORT_SET, NULL}, -#endif -#ifdef ISISC - {"PppoeCmd", "set", "set pppoe frames forwarding command", "", SW_API_PPPOE_CMD_SET, NULL}, -#else - {"PppoeCmd", "set", "set pppoe frames forwarding command", "", SW_API_PPPOE_CMD_SET, NULL}, -#endif - {"Pppoe", "set", "set pppoe frames hardware identification status", "", SW_API_PPPOE_STATUS_SET, NULL}, - {"ptDhcp", "set", "set dhcp frames hardware identification status", " ", SW_API_PT_DHCP_SET, NULL}, -#ifdef ISISC - {"arpcmd", "set", "set arp packets forwarding command", "", SW_API_ARP_CMD_SET, NULL}, -#else - {"arpcmd", "set", "set arp packets forwarding command", "", SW_API_ARP_CMD_SET, NULL}, -#endif -#ifdef ISISC - {"eapolcmd", "set", "set eapol packets forwarding command", "", SW_API_EAPOL_CMD_SET, NULL}, -#else - {"eapolcmd", "set", "set eapol packets forwarding command", "", SW_API_EAPOL_CMD_SET, NULL}, -#endif -#ifndef ISISC - {"pppoesession", "add", "add a pppoe session entry", " ", SW_API_PPPOE_SESSION_ADD, NULL}, - {"pppoesession", "del", "del a pppoe session entry", "", SW_API_PPPOE_SESSION_DEL, NULL}, -#endif - {"eapolstatus", "set", "set eapol frames hardware identification status", " ", SW_API_EAPOL_STATUS_SET, NULL}, - {"rip", "set", "set rip packets copy to cpu status", "", SW_API_RIPV1_STATUS_SET, NULL}, - {"ptarpreq", "set", "set arp request packets hardware identification status", " ", SW_API_PT_ARP_REQ_STATUS_SET, NULL}, - {"ptarpack", "set", "set arp ack packets hardware identification status", " ", SW_API_PT_ARP_ACK_STATUS_SET, NULL}, - {"extendpppoe", "set", "add a pppoe session entry", "", SW_API_PPPOE_SESSION_TABLE_ADD, NULL}, - {"extendpppoe", "add", "add a pppoe session entry", "", SW_API_PPPOE_SESSION_TABLE_ADD, NULL}, - {"extendpppoe", "del", "del a pppoe session entry", "", SW_API_PPPOE_SESSION_TABLE_DEL, NULL}, - {"pppoeid", "set", "set a pppoe session id entry", " ", SW_API_PPPOE_SESSION_ID_SET, NULL}, - {"intrmask", "set", "set switch interrupt mask", "", SW_API_INTR_MASK_SET, NULL}, - {"intrstatus", "clear", "clear switch interrupt status", "", SW_API_INTR_STATUS_CLEAR, NULL}, - {"intrportlinkmask", "set", "set link interrupt mask of a port", " ", SW_API_INTR_PORT_LINK_MASK_SET, NULL}, - {"intrmaskmaclinkchg", "set", "set switch interrupt mask for mac link change", " ", SW_API_INTR_MASK_MAC_LINKCHG_SET, NULL}, - {"intrstatusmaclinkchg", "clear", "clear switch interrupt status for mac link change", "", SW_API_INTR_STATUS_MAC_LINKCHG_CLEAR, NULL}, - {"cpuVid", "set", "set to_cpu vid status", "", SW_API_CPU_VID_EN_SET, NULL}, - {"rtdPppoe", "set", "set RM_RTD_PPPOE_EN status", "", SW_API_RTD_PPPOE_EN_SET, NULL}, - {"glomacaddr", "set", "set global macaddr", "", SW_API_GLOBAL_MACADDR_SET, NULL}, - {"lldp", "set", "set lldp frames hardware identification status", "", SW_API_LLDP_STATUS_SET, NULL}, - {"framecrc", "set", "set frame crc reserve enable", "", SW_API_FRAME_CRC_RESERVE_SET, NULL}, - {NULL, NULL, NULL, NULL, (int)NULL, NULL}/*end of desc*/ - }, - }, -#endif - - /* IP */ -#ifdef IN_IP - { - "ip", "config ip", - { - {"hostentry", "set", "add host entry", "", SW_API_IP_HOST_ADD, NULL}, - {"hostentry", "add", "add host entry", "", SW_API_IP_HOST_ADD, NULL}, - {"hostentry", "del", "del host entry", "", SW_API_IP_HOST_DEL, NULL}, - {"hostentry", "next", "next host entry", "", SW_API_IP_HOST_NEXT, NULL}, - {"hostentry", "bindcnt", "bind counter to host entry", " ", SW_API_IP_HOST_COUNTER_BIND, NULL}, - {"hostentry", "bindpppoe", "bind pppoe to host entry", " ", SW_API_IP_HOST_PPPOE_BIND, NULL}, - {"ptarplearn", "set", "set port arp learn flag, bit0 req bit1 ack", " ", SW_API_IP_PT_ARP_LEARN_SET, NULL}, - {"arplearn", "set", "set arp learn mode", "", SW_API_IP_ARP_LEARN_SET, NULL}, - {"ptipsrcguard", "set", "set ip source guard mode", " ", SW_API_IP_SOURCE_GUARD_SET, NULL}, - {"ptarpsrcguard", "set", "set arp source guard mode", " ", SW_API_IP_ARP_GUARD_SET, NULL}, - {"routestatus", "set", "set ip route status", "", SW_API_IP_ROUTE_STATUS_SET, NULL}, - {"intfentry", "set", "add interface mac address", "", SW_API_IP_INTF_ENTRY_ADD, NULL}, - {"intfentry", "add", "add interface mac address", "", SW_API_IP_INTF_ENTRY_ADD, NULL}, - {"intfentry", "del", "del interface mac address", "", SW_API_IP_INTF_ENTRY_DEL, NULL}, - {"ipunksrc", "set", "set ip unkown source command", "", SW_API_IP_UNK_SOURCE_CMD_SET, NULL}, - {"arpunksrc", "set", "set arp unkown source command", "", SW_API_ARP_UNK_SOURCE_CMD_SET, NULL}, - {"ipagetime", "set", "set dynamic ip entry age time", "